Drop of kernel from broadcom for 7252
rm -rf .
cp -prf ~/bcm/refsw5.2/314-1.7/src/linux/* .
git add -A
git status
git commit
Change-Id: I3e2e8c4f1394d4eebe59180a11c482a683be7ebc
diff --git a/Documentation/devicetree/bindings/arm/brcm-brcmstb.txt b/Documentation/devicetree/bindings/arm/brcm-brcmstb.txt
index 3c436cc..fe4299d 100644
--- a/Documentation/devicetree/bindings/arm/brcm-brcmstb.txt
+++ b/Documentation/devicetree/bindings/arm/brcm-brcmstb.txt
@@ -20,6 +20,16 @@
- compatible: "brcm,bcm<chip_id>-hif-cpubiuctrl", "syscon"
- compatible: "brcm,bcm<chip_id>-hif-continuation", "syscon"
+hif-cpubiuctrl node
+-------------------
+
+Required properties:
+ - compatible: "brcm,bcm<chip_id>-hif-cpubiuctrl", "syscon"
+
+Optional properties:
+ - brcm,write-pairing: boolean property, when present indicates
+ that write pairing should be enabled for this chip
+
example:
rdb {
#address-cells = <1>;
@@ -35,6 +45,7 @@
hif_cpubiuctrl: syscon@3e2400 {
compatible = "brcm,bcm7445-hif-cpubiuctrl", "syscon";
reg = <0x3e2400 0x5b4>;
+ brcm,write-pairing;
};
hif_continuation: syscon@452000 {
diff --git a/Documentation/devicetree/bindings/clock/multiplier-clock.txt b/Documentation/devicetree/bindings/clock/multiplier-clock.txt
new file mode 100644
index 0000000..ca682ef
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/multiplier-clock.txt
@@ -0,0 +1,84 @@
+Binding for simple multiplier clock.
+
+This binding uses the common clock binding[1]. It assumes a
+register-mapped adjustable clock rate multiplier that does not gate and has
+only one input clock or parent. By default the value programmed into
+the register is one less than the actual multiplier value. E.g:
+
+register value actual multiplier value
+0 1
+1 2
+2 3
+
+This assumption may be modified by the following optional properties:
+
+index-starts-at-one - valid multiplier values start at 1, not the default
+of 0. E.g:
+register value actual multiplier value
+1 1
+2 2
+3 3
+
+index-power-of-two - valid multiplier values are powers of two. E.g:
+register value actual multiplier value
+0 1
+1 2
+2 4
+
+index-allow-zero - same as index_one, but zero is multiply-by-1. E.g:
+register value actual multiplier value
+0 1
+1 1
+2 2
+
+Additionally a table of valid multipliers may be supplied like so:
+
+ table = <4 0>, <8, 1>;
+
+where the first value in the pair is the multiplier and the second value is
+the programmed register bitfield.
+
+The binding must also provide the register to control the multiplier and
+the mask for the corresponding control bits. Optionally the number of
+bits to shift that mask, if necessary. If the shift value is missing it
+is the same as supplying a zero shift.
+
+[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
+
+Required properties:
+- compatible : shall be "multiplier-clock".
+- #clock-cells : from common clock binding; shall be set to 0.
+- clocks : link to phandle of parent clock
+- reg : base address for register controlling adjustable multiplier
+- bit-mask : arbitrary bitmask for programming the adjustable multiplier
+
+Optional properties:
+- clock-output-names : from common clock binding.
+- table : array of integer pairs defining multipliers & bitfield values
+- bit-shift : number of bits to shift the bit-mask, defaults to
+ (ffs(mask) - 1) if not present
+- index-starts-at-one : valid multiplier programming starts at 1, not zero
+- index-power-of-two : valid multiplier programming must be a power of two
+- index-allow-zero : implies index-one, and programming zero results in
+ multiply-by-one
+- index-max-mult-at-zero : same as index-starts-at-one, but the value
+ of zero implies a multiplier of 2^width of the register field.
+
+Examples:
+ clock_foo: clock_foo at 4a008100 {
+ compatible = "multiplier-clock";
+ #clock-cells = <0>;
+ clocks = <&clock_baz>;
+ reg = <0x4a008100 0x4>
+ mask = <0x3>
+ };
+
+ clock_bar: clock_bar at 4a008108 {
+ #clock-cells = <0>;
+ compatible = "multiplier-clock";
+ clocks = <&clock_foo>;
+ reg = <0x4a008108 0x4>;
+ mask = <0x1>;
+ shift = <0>;
+ table = < 4 0 >, < 8 1 >;
+ };
diff --git a/Documentation/devicetree/bindings/gpio/brcm,brcmstb-gpio.txt b/Documentation/devicetree/bindings/gpio/brcm,brcmstb-gpio.txt
new file mode 100644
index 0000000..5eb6b4a
--- /dev/null
+++ b/Documentation/devicetree/bindings/gpio/brcm,brcmstb-gpio.txt
@@ -0,0 +1,85 @@
+Broadcom STB "UPG GIO" GPIO controller
+
+The controller's registers are organized as sets of eight 32-bit
+registers with each set controlling a bank of up to 32 pins. A single
+interrupt is shared for all of the banks handled by the controller.
+
+Required properties:
+
+- compatible:
+ Must be "brcm,brcmstb-gpio"
+
+- reg:
+ Define the base and range of the I/O address space containing
+ the brcmstb GPIO controller registers
+
+- #gpio-cells:
+ Should be <2>. The first cell is the pin number (within the controller's
+ pin space), and the second is used for the following:
+ bit[0]: polarity (0 for active-high, 1 for active-low)
+
+- gpio-controller:
+ Specifies that the node is a GPIO controller.
+
+- brcm,gpio-bank-widths:
+ Number of GPIO lines for each bank. Number of elements must
+ correspond to number of banks suggested by the 'reg' property.
+
+Optional properties:
+
+- interrupts:
+ The interrupt shared by all GPIO lines for this controller.
+
+- interrupt-parent:
+ phandle of the parent interrupt controller
+
+- interrupts-extended:
+ Alternate form of specifying interrupts and parents that allows for
+ multiple parents. This takes precedence over 'interrupts' and
+ 'interrupt-parent'. This probably must be used if the wakeup-source
+ property is provided because that may have a different interrupt parent.
+
+- #interrupt-cells:
+ Should be <2>. The first cell is the GPIO number, the second should specify
+ flags. The following subset of flags is supported:
+ - bits[3:0] trigger type and level flags
+ 1 = low-to-high edge triggered
+ 2 = high-to-low edge triggered
+ 4 = active high level-sensitive
+ 8 = active low level-sensitive
+ Valid combinations are 1, 2, 3, 4, 8.
+ See also Documentation/devicetree/bindings/interrupt-controller/interrupts.txt
+
+- interrupt-controller:
+ Marks the device node as an interrupt controller
+
+- wakeup-source:
+ GPIOs for this controller can be used as a wakeup source
+
+Example:
+ upg_gio: gpio@f040a700 {
+ #gpio-cells = <2>;
+ #interrupt-cells = <2>;
+ compatible = "brcm,bcm7445-gpio", "brcm,brcmstb-gpio";
+ gpio-controller;
+ interrupt-controller;
+ reg = <0xf040a700 0x80>;
+ interrupt-parent = <&irq0_intc>;
+ interrupts = <0x6>;
+ brcm,gpio-bank-widths = <32 32 32 24>;
+ };
+
+ upg_gio_aon: gpio@f04172c0 {
+ #gpio-cells = <2>;
+ #interrupt-cells = <2>;
+ compatible = "brcm,bcm7445-gpio", "brcm,brcmstb-gpio";
+ gpio-controller;
+ interrupt-controller;
+ reg = <0xf04172c0 0x40>;
+ interrupt-parent = <&irq0_aon_intc>;
+ interrupts = <0x6>;
+ interrupts-extended = <&irq0_aon_intc 0x6>,
+ <&aon_pm_l2_intc 0x5>;
+ wakeup-source;
+ brcm,gpio-bank-widths = <18 4>;
+ };
diff --git a/Documentation/devicetree/bindings/net/fixed-link.txt b/Documentation/devicetree/bindings/net/fixed-link.txt
new file mode 100644
index 0000000..e956de1
--- /dev/null
+++ b/Documentation/devicetree/bindings/net/fixed-link.txt
@@ -0,0 +1,30 @@
+Fixed link Device Tree binding
+------------------------------
+
+Some Ethernet MACs have a "fixed link", and are not connected to a
+normal MDIO-managed PHY device. For those situations, a Device Tree
+binding allows to describe a "fixed link".
+
+Such a fixed link situation is described by creating a 'fixed-link'
+sub-node of the Ethernet MAC device node, with the following
+properties:
+
+* 'speed' (integer, mandatory), to indicate the link speed. Accepted
+ values are 10, 100 and 1000
+* 'full-duplex' (boolean, optional), to indicate that full duplex is
+ used. When absent, half duplex is assumed.
+* 'pause' (boolean, optional), to indicate that pause should be
+ enabled.
+* 'asym-pause' (boolean, optional), to indicate that asym_pause should
+ be enabled.
+
+Example:
+
+ethernet@0 {
+ ...
+ fixed-link {
+ speed = <1000>;
+ full-duplex;
+ };
+ ...
+};
diff --git a/Documentation/devicetree/bindings/net/phy.txt b/Documentation/devicetree/bindings/net/phy.txt
index 58307d0..4e00b3b 100644
--- a/Documentation/devicetree/bindings/net/phy.txt
+++ b/Documentation/devicetree/bindings/net/phy.txt
@@ -21,6 +21,9 @@
elements.
- max-speed: Maximum PHY supported speed (10, 100, 1000...)
+- broken-turn-around: If set, indicates the PHY device does not correctly
+ release the turn around line low at the end of a MDIO transaction.
+
Example:
ethernet-phy@0 {
diff --git a/Documentation/devicetree/bindings/thermal/brcmstb-thermal.txt b/Documentation/devicetree/bindings/thermal/brcmstb-thermal.txt
new file mode 100644
index 0000000..880e623
--- /dev/null
+++ b/Documentation/devicetree/bindings/thermal/brcmstb-thermal.txt
@@ -0,0 +1,20 @@
+* Broadcom STB (BCM7xxx) thermal management
+
+Thermal management core, provided by the AVS TMON hardware block.
+
+Required properties:
+
+- compatible: "brcm,avs-tmon-bcm7445" and/or "brcm,avs-tmon"
+- reg: address range for the AVS TMON registers
+- interrupts: 'TMON' interrupt, for high/low threshold triggers
+- interrupt-names: "tmon"
+
+Example:
+
+ thermal@f04d1500 {
+ compatible = "brcm,avs-tmon-bcm7445", "brcm,avs-tmon";
+ interrupt-names = "tmon";
+ interrupt-parent = <&avs_host_l2_intc>;
+ reg = <0xf04d1500 0x28>;
+ interrupts = <0x6>;
+ };
diff --git a/Documentation/gpio/consumer.txt b/Documentation/gpio/consumer.txt
index e42f77d..09854fe 100644
--- a/Documentation/gpio/consumer.txt
+++ b/Documentation/gpio/consumer.txt
@@ -154,6 +154,7 @@
void gpiod_set_raw_value(struct gpio_desc *desc, int value)
int gpiod_get_raw_value_cansleep(const struct gpio_desc *desc)
void gpiod_set_raw_value_cansleep(struct gpio_desc *desc, int value)
+ int gpiod_direction_output_raw(struct gpio_desc *desc, int value)
The active-low state of a GPIO can also be queried using the following call:
diff --git a/Documentation/kernel-parameters.txt b/Documentation/kernel-parameters.txt
index 7116fda..ddb0f1c 100644
--- a/Documentation/kernel-parameters.txt
+++ b/Documentation/kernel-parameters.txt
@@ -44,6 +44,7 @@
AVR32 AVR32 architecture is enabled.
AX25 Appropriate AX.25 support is enabled.
BLACKFIN Blackfin architecture is enabled.
+ BRCMSTB Broadcom STB platform support is enabled.
CLK Common clock infrastructure is enabled.
CMA Contiguous Memory Area support is enabled.
DRM Direct Rendering Management support is enabled.
@@ -503,6 +504,14 @@
embedded devices based on command line input.
See Documentation/block/cmdline-partition.txt
+ bmem=size[KMG][@offset[KMG]] [KNL,BRCM]
+ Set aside a contiguous reserved memory region at the
+ specified location. Can be provided multiple times,
+ once for each reservation. Note: there is a default
+ reservation, and manually specifying any region will
+ disable the defaults. Specifying bmem=0 will disable
+ bmem entirely.
+
boot_delay= Milliseconds to delay each printk during boot.
Values larger than 10 seconds (10000) are changed to
no delay (0).
@@ -510,6 +519,11 @@
bootmem_debug [KNL] Enable bootmem allocator debug messages.
+ brcm_cma=size[KMG][@offset[KMG]] [KNL,BRCM]
+ Set aside a contiguous memory region to be used as a
+ CMA area at the specified location. Can be provided
+ multiple times, once for each reservation.
+
bttv.card= [HW,V4L] bttv (bt848 + bt878 based grabber cards)
bttv.radio= Most important insmod options are available as
kernel args too.
@@ -603,9 +617,13 @@
Also note the kernel might malfunction if you disable
some critical bits.
- cma=nn[MG] [ARM,KNL]
- Sets the size of kernel global memory area for contiguous
- memory allocations. For more information, see
+ cma=nn[MG]@[start[MG][-end[MG]]]
+ [ARM,X86,KNL]
+ Sets the size of kernel global memory area for
+ contiguous memory allocations and optionally the
+ placement constraint by the physical address range of
+ memory allocations. A value of 0 disables CMA
+ altogether. For more information, see
include/linux/dma-contiguous.h
cmo_free_hint= [PPC] Format: { yes | no }
@@ -3119,6 +3137,13 @@
improve throughput, but will also increase the
amount of memory reserved for use by the client.
+ suspend.pm_test_delay=
+ [SUSPEND]
+ Sets the number of seconds to remain in a suspend test
+ mode before resuming the system (see
+ /sys/power/pm_test). Only available when CONFIG_PM_DEBUG
+ is set. Default value is 5.
+
swapaccount=[0|1]
[KNL] Enable accounting of swap in memory resource
controller if no parameter or 1 is given or disable
diff --git a/Documentation/power/basic-pm-debugging.txt b/Documentation/power/basic-pm-debugging.txt
index edeecd4..b96098c 100644
--- a/Documentation/power/basic-pm-debugging.txt
+++ b/Documentation/power/basic-pm-debugging.txt
@@ -75,12 +75,14 @@
# echo platform > /sys/power/disk
# echo disk > /sys/power/state
-Then, the kernel will try to freeze processes, suspend devices, wait 5 seconds,
-resume devices and thaw processes. If "platform" is written to
+Then, the kernel will try to freeze processes, suspend devices, wait a few
+seconds (5 by default, but configurable by the suspend.pm_test_delay module
+parameter), resume devices and thaw processes. If "platform" is written to
/sys/power/pm_test , then after suspending devices the kernel will additionally
invoke the global control methods (eg. ACPI global control methods) used to
-prepare the platform firmware for hibernation. Next, it will wait 5 seconds and
-invoke the platform (eg. ACPI) global methods used to cancel hibernation etc.
+prepare the platform firmware for hibernation. Next, it will wait a
+configurable number of seconds and invoke the platform (eg. ACPI) global
+methods used to cancel hibernation etc.
Writing "none" to /sys/power/pm_test causes the kernel to switch to the normal
hibernation/suspend operations. Also, when open for reading, /sys/power/pm_test
diff --git a/Makefile b/Makefile
index 6285316..129efe6 100644
--- a/Makefile
+++ b/Makefile
@@ -2,7 +2,7 @@
PATCHLEVEL = 14
SUBLEVEL = 28
#EXTRAVERSION =
-EXTRAVERSION = -1.4
+EXTRAVERSION = -1.7
NAME = Remembering Coco
# *DOCUMENTATION*
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index ddc7b47..433bccf 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -1632,7 +1632,7 @@
# selected platforms.
config ARCH_NR_GPIO
int
- default 1024 if ARCH_SHMOBILE || ARCH_TEGRA
+ default 1024 if ARCH_BRCMSTB || ARCH_SHMOBILE || ARCH_TEGRA
default 512 if ARCH_EXYNOS || ARCH_KEYSTONE || SOC_OMAP5 || SOC_DRA7XX || ARCH_S3C24XX || ARCH_S3C64XX
default 392 if ARCH_U8500
default 352 if ARCH_VT8500
diff --git a/arch/arm/Kconfig.debug b/arch/arm/Kconfig.debug
index 7b9d655..6c02643 100644
--- a/arch/arm/Kconfig.debug
+++ b/arch/arm/Kconfig.debug
@@ -1061,11 +1061,9 @@
default 0xe0000000 if ARCH_SPEAR13XX
default 0xf0000be0 if ARCH_EBSA110
default 0xf040a900 if DEBUG_BRCMSTB_UART && BCM3390A0
- default 0xf0406c00 if DEBUG_BRCMSTB_UART && BCM7145A0
default 0xf040a900 if DEBUG_BRCMSTB_UART && BCM7145B0
default 0xf040b400 if DEBUG_BRCMSTB_UART && BCM7250B0
default 0xf040b000 if DEBUG_BRCMSTB_UART && BCM7364A0
- default 0xf040b000 if DEBUG_BRCMSTB_UART && BCM7366B0
default 0xf040b000 if DEBUG_BRCMSTB_UART && BCM7366C0
default 0xf040a900 if DEBUG_BRCMSTB_UART && BCM7439B0
default 0xf040ab00 if DEBUG_BRCMSTB_UART && BCM7445D0
@@ -1105,11 +1103,9 @@
default 0xfb009000 if DEBUG_REALVIEW_STD_PORT
default 0xfb10c000 if DEBUG_REALVIEW_PB1176_PORT
default 0xfc40a900 if DEBUG_BRCMSTB_UART && BCM3390A0
- default 0xfc406c00 if DEBUG_BRCMSTB_UART && BCM7145A0
default 0xfc40a900 if DEBUG_BRCMSTB_UART && BCM7145B0
default 0xfc40b400 if DEBUG_BRCMSTB_UART && BCM7250B0
default 0xfc40b000 if DEBUG_BRCMSTB_UART && BCM7364A0
- default 0xfc40b000 if DEBUG_BRCMSTB_UART && BCM7366B0
default 0xfc40b000 if DEBUG_BRCMSTB_UART && BCM7366C0
default 0xfc40a900 if DEBUG_BRCMSTB_UART && BCM7439B0
default 0xfc40ab00 if DEBUG_BRCMSTB_UART && BCM7445D0
diff --git a/arch/arm/configs/brcmstb_defconfig b/arch/arm/configs/brcmstb_defconfig
index 53a9830..7f0d16d 100644
--- a/arch/arm/configs/brcmstb_defconfig
+++ b/arch/arm/configs/brcmstb_defconfig
@@ -19,6 +19,8 @@
CONFIG_ARM_LPAE=y
CONFIG_PCI=y
CONFIG_PCI_MSI=y
+CONFIG_PCIEPORTBUS=y
+# CONFIG_PCIEAER is not set
CONFIG_SMP=y
CONFIG_ARM_PSCI=y
CONFIG_AEABI=y
@@ -28,16 +30,18 @@
CONFIG_CMA=y
CONFIG_ARM_APPENDED_DTB=y
CONFIG_ARM_ATAG_DTB_COMPAT=y
-CONFIG_KEXEC=y
+# CONFIG_KEXEC is not set
CONFIG_CPU_FREQ=y
CONFIG_CPU_FREQ_GOV_POWERSAVE=y
CONFIG_CPU_FREQ_GOV_USERSPACE=y
CONFIG_CPU_FREQ_GOV_ONDEMAND=y
CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y
CONFIG_CPU_IDLE=y
+CONFIG_CRAMFS=y
CONFIG_VFP=y
CONFIG_NEON=y
CONFIG_PM_RUNTIME=y
+CONFIG_PM_DEBUG=y
CONFIG_NET=y
CONFIG_PACKET=y
CONFIG_UNIX=y
@@ -145,11 +149,16 @@
CONFIG_I2C_CHARDEV=y
CONFIG_SPI=y
CONFIG_SPI_BITBANG=y
+CONFIG_GPIOLIB=y
CONFIG_POWER_SUPPLY=y
CONFIG_POWER_RESET=y
# CONFIG_HWMON is not set
CONFIG_THERMAL=y
+CONFIG_THERMAL_DEFAULT_GOV_USER_SPACE=y
+CONFIG_THERMAL_GOV_STEP_WISE=y
CONFIG_CPU_THERMAL=y
+CONFIG_INTEL_POWERCLAMP=y
+CONFIG_BRCMSTB_THERMAL=y
CONFIG_MEDIA_SUPPORT=y
CONFIG_MEDIA_CAMERA_SUPPORT=y
CONFIG_MEDIA_USB_SUPPORT=y
@@ -168,12 +177,19 @@
CONFIG_MMC_BLOCK_MINORS=16
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_PLTFM=y
+CONFIG_BRCMSTB_BMEM=y
+CONFIG_BRCMSTB_CMA=y
+CONFIG_BRCMSTB_MEMORY_API=y
+CONFIG_BRCMSTB_SRPD=y
+CONFIG_BRCMSTB_WKTMR=y
# CONFIG_IOMMU_SUPPORT is not set
CONFIG_RESET_CONTROLLER=y
CONFIG_GENERIC_PHY=y
CONFIG_EXT4_FS=y
CONFIG_JBD2_DEBUG=y
CONFIG_FUSE_FS=y
+CONFIG_FHANDLE=y
+CONFIG_CGROUPS=y
CONFIG_CUSE=y
CONFIG_ISO9660_FS=y
CONFIG_JOLIET=y
diff --git a/arch/arm/configs/brcmstb_hardened_defconfig b/arch/arm/configs/brcmstb_hardened_defconfig
new file mode 100644
index 0000000..0fd8099
--- /dev/null
+++ b/arch/arm/configs/brcmstb_hardened_defconfig
@@ -0,0 +1,177 @@
+# CONFIG_LOCALVERSION_AUTO is not set
+# CONFIG_SWAP is not set
+CONFIG_SYSVIPC=y
+CONFIG_POSIX_MQUEUE=y
+CONFIG_NO_HZ=y
+CONFIG_HIGH_RES_TIMERS=y
+CONFIG_IRQ_TIME_ACCOUNTING=y
+CONFIG_LOG_BUF_SHIFT=16
+CONFIG_BLK_DEV_INITRD=y
+CONFIG_EXPERT=y
+# CONFIG_KALLSYMS is not set
+# CONFIG_PRINTK is not set
+# CONFIG_BUG is not set
+# CONFIG_ELF_CORE is not set
+# CONFIG_COMPAT_BRK is not set
+CONFIG_CC_STACKPROTECTOR_REGULAR=y
+CONFIG_MODULES=y
+CONFIG_MODVERSIONS=y
+# CONFIG_LBDAF is not set
+# CONFIG_BLK_DEV_BSG is not set
+CONFIG_ARCH_BCM=y
+CONFIG_ARCH_BRCMSTB=y
+# CONFIG_BRCM_MOCA is not set
+CONFIG_ARM_LPAE=y
+CONFIG_PCI=y
+CONFIG_PCI_MSI=y
+CONFIG_PCIEPORTBUS=y
+# CONFIG_PCIEAER is not set
+CONFIG_SMP=y
+CONFIG_AEABI=y
+CONFIG_HIGHMEM=y
+CONFIG_HIGHPTE=y
+CONFIG_SPARSEMEM_MANUAL=y
+CONFIG_DEFAULT_MMAP_MIN_ADDR=32768
+CONFIG_CMA=y
+# CONFIG_ATAGS is not set
+CONFIG_ARM_APPENDED_DTB=y
+CONFIG_CPU_FREQ=y
+CONFIG_CPU_FREQ_GOV_POWERSAVE=y
+CONFIG_CPU_FREQ_GOV_USERSPACE=y
+CONFIG_CPU_FREQ_GOV_ONDEMAND=y
+CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y
+CONFIG_CPU_IDLE=y
+CONFIG_VFP=y
+CONFIG_NEON=y
+CONFIG_PM_RUNTIME=y
+CONFIG_NET=y
+CONFIG_PACKET=y
+CONFIG_UNIX=y
+CONFIG_INET=y
+CONFIG_IP_MULTICAST=y
+CONFIG_IP_PNP=y
+CONFIG_IP_PNP_DHCP=y
+CONFIG_IP_PNP_BOOTP=y
+CONFIG_IP_PNP_RARP=y
+# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
+# CONFIG_INET_XFRM_MODE_TUNNEL is not set
+# CONFIG_INET_XFRM_MODE_BEET is not set
+# CONFIG_INET_LRO is not set
+CONFIG_INET_UDP_DIAG=y
+# CONFIG_IPV6 is not set
+CONFIG_NETFILTER=y
+CONFIG_IP_NF_IPTABLES=y
+CONFIG_BRIDGE=y
+CONFIG_DEVTMPFS=y
+CONFIG_DEVTMPFS_MOUNT=y
+CONFIG_DMA_CMA=y
+CONFIG_CMA_ALIGNMENT=12
+CONFIG_MTD=y
+CONFIG_MTD_BLOCK=y
+CONFIG_MTD_CFI=y
+CONFIG_MTD_JEDECPROBE=y
+CONFIG_MTD_CFI_INTELEXT=y
+CONFIG_MTD_CFI_AMDSTD=y
+CONFIG_MTD_CFI_STAA=y
+CONFIG_MTD_ROM=y
+CONFIG_MTD_ABSENT=y
+CONFIG_MTD_PHYSMAP_OF=y
+CONFIG_MTD_M25P80=y
+CONFIG_MTD_UBI=y
+CONFIG_MTD_UBI_GLUEBI=y
+CONFIG_PROC_DEVICETREE=y
+CONFIG_BLK_DEV_LOOP=y
+CONFIG_BLK_DEV_RAM=y
+CONFIG_BLK_DEV_RAM_SIZE=8192
+CONFIG_NETDEVICES=y
+# CONFIG_NET_VENDOR_3COM is not set
+# CONFIG_NET_VENDOR_ADAPTEC is not set
+# CONFIG_NET_VENDOR_ALTEON is not set
+# CONFIG_NET_VENDOR_AMD is not set
+# CONFIG_NET_VENDOR_ARC is not set
+# CONFIG_NET_VENDOR_ATHEROS is not set
+# CONFIG_NET_CADENCE is not set
+# CONFIG_NET_VENDOR_BROCADE is not set
+# CONFIG_NET_VENDOR_CHELSIO is not set
+# CONFIG_NET_VENDOR_CIRRUS is not set
+# CONFIG_NET_VENDOR_CISCO is not set
+# CONFIG_NET_VENDOR_DEC is not set
+# CONFIG_NET_VENDOR_DLINK is not set
+# CONFIG_NET_VENDOR_EMULEX is not set
+# CONFIG_NET_VENDOR_EXAR is not set
+# CONFIG_NET_VENDOR_FARADAY is not set
+# CONFIG_NET_VENDOR_HP is not set
+# CONFIG_NET_VENDOR_INTEL is not set
+# CONFIG_NET_VENDOR_MARVELL is not set
+# CONFIG_NET_VENDOR_MELLANOX is not set
+# CONFIG_NET_VENDOR_MICREL is not set
+# CONFIG_NET_VENDOR_MICROCHIP is not set
+# CONFIG_NET_VENDOR_MYRI is not set
+# CONFIG_NET_VENDOR_NATSEMI is not set
+# CONFIG_NET_VENDOR_NVIDIA is not set
+# CONFIG_NET_VENDOR_OKI is not set
+# CONFIG_NET_PACKET_ENGINE is not set
+# CONFIG_NET_VENDOR_QLOGIC is not set
+# CONFIG_NET_VENDOR_REALTEK is not set
+# CONFIG_NET_VENDOR_RDC is not set
+# CONFIG_NET_VENDOR_SEEQ is not set
+# CONFIG_NET_VENDOR_SILAN is not set
+# CONFIG_NET_VENDOR_SIS is not set
+# CONFIG_NET_VENDOR_SMSC is not set
+# CONFIG_NET_VENDOR_STMICRO is not set
+# CONFIG_NET_VENDOR_SUN is not set
+# CONFIG_NET_VENDOR_TEHUTI is not set
+# CONFIG_NET_VENDOR_TI is not set
+# CONFIG_NET_VENDOR_VIA is not set
+# CONFIG_NET_VENDOR_WIZNET is not set
+# CONFIG_INPUT is not set
+# CONFIG_SERIO is not set
+# CONFIG_VT is not set
+# CONFIG_LEGACY_PTYS is not set
+# CONFIG_DEVKMEM is not set
+CONFIG_SERIAL_8250=y
+# CONFIG_SERIAL_8250_DEPRECATED_OPTIONS is not set
+CONFIG_SERIAL_8250_CONSOLE=y
+# CONFIG_SERIAL_8250_PCI is not set
+CONFIG_SERIAL_OF_PLATFORM=y
+CONFIG_HW_RANDOM=y
+CONFIG_I2C=y
+CONFIG_I2C_CHARDEV=y
+CONFIG_I2C_MUX=y
+CONFIG_SPI=y
+CONFIG_SPI_BITBANG=y
+CONFIG_POWER_SUPPLY=y
+CONFIG_POWER_RESET=y
+# CONFIG_HWMON is not set
+CONFIG_THERMAL=y
+CONFIG_CPU_THERMAL=y
+CONFIG_BRCMSTB_THERMAL=y
+CONFIG_SOUND=y
+CONFIG_SND=y
+# CONFIG_SND_VERBOSE_PROCFS is not set
+# CONFIG_SND_PCI is not set
+# CONFIG_SND_SPI is not set
+# CONFIG_SND_USB is not set
+CONFIG_SND_SOC=y
+CONFIG_USB=y
+CONFIG_USB_MON=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_OHCI_HCD=y
+CONFIG_MMC=y
+CONFIG_MMC_BLOCK_MINORS=16
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_PLTFM=y
+# CONFIG_IOMMU_SUPPORT is not set
+CONFIG_TMPFS=y
+# CONFIG_MISC_FILESYSTEMS is not set
+# CONFIG_NETWORK_FILESYSTEMS is not set
+CONFIG_NLS_CODEPAGE_437=y
+CONFIG_NLS_ISO8859_1=y
+# CONFIG_SCHED_DEBUG is not set
+# CONFIG_FTRACE is not set
+CONFIG_STRICT_DEVMEM=y
+# CONFIG_ARM_UNWIND is not set
+CONFIG_SECURITY_DMESG_RESTRICT=y
+# CONFIG_CRYPTO_ANSI_CPRNG is not set
+# CONFIG_CRYPTO_HW is not set
diff --git a/arch/arm/include/asm/bug.h b/arch/arm/include/asm/bug.h
index b274bde..cf81d39 100644
--- a/arch/arm/include/asm/bug.h
+++ b/arch/arm/include/asm/bug.h
@@ -5,8 +5,6 @@
#include <linux/types.h>
#include <asm/opcodes.h>
-#ifdef CONFIG_BUG
-
/*
* Use a suitable undefined instruction to use for ARM/Thumb2 bug handling.
* We need to be careful not to conflict with those used by other modules and
@@ -56,7 +54,6 @@
#endif /* CONFIG_DEBUG_BUGVERBOSE */
#define HAVE_ARCH_BUG
-#endif /* CONFIG_BUG */
#include <asm-generic/bug.h>
diff --git a/arch/arm/include/asm/cacheflush.h b/arch/arm/include/asm/cacheflush.h
index 8b8b616..2d9b492 100644
--- a/arch/arm/include/asm/cacheflush.h
+++ b/arch/arm/include/asm/cacheflush.h
@@ -199,7 +199,7 @@
*/
#if (defined(CONFIG_CPU_V7) && \
(defined(CONFIG_CPU_V6) || defined(CONFIG_CPU_V6K))) || \
- defined(CONFIG_SMP_ON_UP)
+ defined(CONFIG_SMP_ON_UP) || defined(CONFIG_CACHE_B15_RAC)
#define __flush_icache_preferred __cpuc_flush_icache_all
#elif __LINUX_ARM_ARCH__ >= 7 && defined(CONFIG_SMP)
#define __flush_icache_preferred __flush_icache_all_v7_smp
diff --git a/arch/arm/include/asm/glue-cache.h b/arch/arm/include/asm/glue-cache.h
index a3c24cd..11f33b5 100644
--- a/arch/arm/include/asm/glue-cache.h
+++ b/arch/arm/include/asm/glue-cache.h
@@ -117,6 +117,10 @@
# endif
#endif
+#if defined(CONFIG_CACHE_B15_RAC)
+# define MULTI_CACHE 1
+#endif
+
#if defined(CONFIG_CPU_V7M)
# ifdef _CACHE
# define MULTI_CACHE 1
diff --git a/arch/arm/include/asm/hardware/cache-b15-rac.h b/arch/arm/include/asm/hardware/cache-b15-rac.h
new file mode 100644
index 0000000..76b888f
--- /dev/null
+++ b/arch/arm/include/asm/hardware/cache-b15-rac.h
@@ -0,0 +1,12 @@
+#ifndef __ASM_ARM_HARDWARE_CACHE_B15_RAC_H
+#define __ASM_ARM_HARDWARE_CACHE_B15_RAC_H
+
+#ifndef __ASSEMBLY__
+
+void b15_flush_kern_cache_all(void);
+void b15_flush_kern_cache_louis(void);
+void b15_flush_icache_all(void);
+
+#endif
+
+#endif
diff --git a/arch/arm/include/asm/smp.h b/arch/arm/include/asm/smp.h
index 22a3b9b..772435b 100644
--- a/arch/arm/include/asm/smp.h
+++ b/arch/arm/include/asm/smp.h
@@ -114,6 +114,15 @@
#endif
};
+struct of_cpu_method {
+ const char *method;
+ struct smp_operations *ops;
+};
+
+#define CPU_METHOD_OF_DECLARE(name, _method, _ops) \
+ static const struct of_cpu_method __cpu_method_of_table_##name \
+ __used __section(__cpu_method_of_table) \
+ = { .method = _method, .ops = _ops }
/*
* set platform specific SMP operations
*/
diff --git a/arch/arm/kernel/devtree.c b/arch/arm/kernel/devtree.c
index a896e28..a5111ea 100644
--- a/arch/arm/kernel/devtree.c
+++ b/arch/arm/kernel/devtree.c
@@ -18,6 +18,7 @@
#include <linux/of_fdt.h>
#include <linux/of_irq.h>
#include <linux/of_platform.h>
+#include <linux/smp.h>
#include <asm/cputype.h>
#include <asm/setup.h>
@@ -92,6 +93,34 @@
}
}
+#ifdef CONFIG_SMP
+extern struct of_cpu_method __cpu_method_of_table_begin[];
+extern struct of_cpu_method __cpu_method_of_table_end[];
+
+static int __init set_smp_ops_by_method(struct device_node *node)
+{
+ const char *method;
+ struct of_cpu_method *m = __cpu_method_of_table_begin;
+
+ if (of_property_read_string(node, "enable-method", &method))
+ return 0;
+
+ for (; m < __cpu_method_of_table_end; m++)
+ if (!strcmp(m->method, method)) {
+ smp_set_ops(m->ops);
+ return 1;
+ }
+
+ return 0;
+}
+#else
+static inline int set_smp_ops_by_method(struct device_node *node)
+{
+ return 1;
+}
+#endif
+
+
/*
* arm_dt_init_cpu_maps - Function retrieves cpu nodes from the device tree
* and builds the cpu logical map array containing MPIDR values related to
@@ -108,6 +137,7 @@
* read as 0.
*/
struct device_node *cpu, *cpus;
+ int found_method = 0;
u32 i, j, cpuidx = 1;
u32 mpidr = is_smp() ? read_cpuid_mpidr() & MPIDR_HWID_BITMASK : 0;
@@ -179,8 +209,18 @@
}
tmp_map[i] = hwid;
+
+ if (!found_method)
+ found_method = set_smp_ops_by_method(cpu);
}
+ /*
+ * Fallback to an enable-method in the cpus node if nothing found in
+ * a cpu node.
+ */
+ if (!found_method)
+ set_smp_ops_by_method(cpus);
+
if (!bootcpu_valid) {
pr_warn("DT missing boot CPU MPIDR[23:0], fall back to default cpu_logical_map\n");
return;
diff --git a/arch/arm/mach-bcm/Kconfig b/arch/arm/mach-bcm/Kconfig
index e7427a2..e08cdba 100644
--- a/arch/arm/mach-bcm/Kconfig
+++ b/arch/arm/mach-bcm/Kconfig
@@ -47,6 +47,9 @@
select ARM_ERRATA_798181 if SMP
select ARCH_DMA_ADDR_T_64BIT if ARM_LPAE
select GENERIC_IRQ_CHIP
+ select BRCMSTB_GISB_ARB
+ select SOC_BRCMSTB
+ select ARCH_WANT_OPTIONAL_GPIOLIB
help
Say Y if you intend to run the kernel on a Broadcom ARM-based STB
chipset.
@@ -73,16 +76,6 @@
select BRCM_HAS_MOCA_20_GEN23
select BRCM_MSPI_64B_WORDS
-config BCM7145A0
- bool "7145 Ax"
- select BCM7145
- select BRCM_HAS_NAND_MAJOR_7
- select BRCM_HAS_NAND_MINOR_0
- select BRCM_HAS_BSPI_V4
- select BRCM_HAS_MOCA_20_GEN23
- select BRCM_MSPI_64B_WORDS
- select BRCMSTB_USE_MEGA_BARRIER
-
config BCM7145B0
bool "7145 Bx"
select BCM7145
@@ -112,17 +105,6 @@
select BRCM_MSPI_64B_WORDS
select BRCMSTB_XPT_HASH if PM
-config BCM7366B0
- bool "7366 Bx"
- select BCM7366
- select BRCM_GENET_V4
- select BRCM_HAS_NAND_MAJOR_7
- select BRCM_HAS_NAND_MINOR_1
- select BRCM_HAS_BSPI_V4
- select BRCM_HAS_MOCA_20_GEN23
- select BRCM_MSPI_64B_WORDS
- select BRCMSTB_XPT_HASH if PM
-
config BCM7366C0
bool "7366 Cx"
select BCM7366
@@ -144,17 +126,6 @@
select BRCM_HAS_MOCA_20_GEN23
select BRCM_MSPI_64B_WORDS
-config BCM7439A0
- bool "7439 Ax"
- select BCM7439
- select BRCM_GENET_V4
- select BRCM_HAS_NAND_MAJOR_7
- select BRCM_HAS_NAND_MINOR_0
- select BRCM_HAS_BSPI_V4
- select BRCM_HAS_MOCA_20_GEN23
- select BRCM_MSPI_64B_WORDS
- select BRCMSTB_USE_MEGA_BARRIER
-
config BCM7439B0
bool "7439 Bx"
select BCM7439
@@ -405,16 +376,6 @@
config BRCM_MSPI_64B_WORDS
bool
-# Apply the mega-barrier prior to DMA operations to workaround
-# issue noted in HW7445-1301 and derivatives.
-config BRCMSTB_USE_MEGA_BARRIER
- bool
- select CMA
-
-# Perform memory hashing before entering S3, using XPT DMA
-config BRCMSTB_XPT_HASH
- bool
-
config BRCM_USB_OHCI
tristate
diff --git a/arch/arm/mach-bcm/Makefile b/arch/arm/mach-bcm/Makefile
index 8e4146e..f06b508 100644
--- a/arch/arm/mach-bcm/Makefile
+++ b/arch/arm/mach-bcm/Makefile
@@ -14,9 +14,8 @@
plus_sec := $(call as-instr,.arch_extension sec,+sec)
AFLAGS_bcm_kona_smc_asm.o :=-Wa,-march=armv7-a$(plus_sec)
-obj-$(CONFIG_ARCH_BRCMSTB) := brcmstb.o cma_driver.o wktmr-brcmstb.o gisb-brcmstb.o srpd-brcmstb.o
-obj-$(CONFIG_SMP) += headsmp-brcmstb.o
-obj-$(CONFIG_HOTPLUG_CPU) += hotplug-brcmstb.o
+ifeq ($(CONFIG_ARCH_BRCMSTB),y)
+obj-y += brcmstb.o
+obj-$(CONFIG_SMP) += headsmp-brcmstb.o platsmp-brcmstb.o
obj-$(CONFIG_PCI) += pci-brcmstb.o
-obj-$(CONFIG_PM) += pm-brcmstb.o s2-brcmstb.o regsave.o
-obj-$(CONFIG_BRCMSTB_XPT_HASH) += xpt_dma.o
+endif
diff --git a/arch/arm/mach-bcm/brcmstb.c b/arch/arm/mach-bcm/brcmstb.c
index 3bfddd5..2a6ba6c 100644
--- a/arch/arm/mach-bcm/brcmstb.c
+++ b/arch/arm/mach-bcm/brcmstb.c
@@ -27,8 +27,8 @@
#include <linux/of_platform.h>
#include <linux/platform_device.h>
#include <linux/printk.h>
-#include <linux/smp.h>
#if defined(CONFIG_BRCMSTB)
+#include <linux/brcmstb/bmem.h>
#include <linux/brcmstb/brcmstb.h>
#include <linux/brcmstb/cma_driver.h>
#endif
@@ -45,8 +45,6 @@
#include <asm/mach/time.h>
#include <asm/setup.h>
-#include "brcmstb.h"
-
/***********************************************************************
* STB CPU (main application processor)
***********************************************************************/
@@ -61,6 +59,10 @@
/*
* HACK: The following drivers are still using BDEV macros:
* - XPT DMA
+ * - SPI
+ * - NAND
+ * - SDHCI
+ * - MoCA
*
* Once these drivers have migrated over to using 'of_iomap()' and standard
* register accessors, we can eliminate this static mapping.
@@ -81,80 +83,22 @@
static void __init brcmstb_reserve(void)
{
+ brcmstb_memory_reserve();
cma_reserve();
+ bmem_reserve();
}
-#ifdef CONFIG_FIXED_PHY
-static int of_add_one_fixed_phy(struct device_node *np)
-{
- struct fixed_phy_status status = {};
- u32 *fixed_link;
- int ret;
-
- fixed_link = (u32 *)of_get_property(np, "fixed-link", NULL);
- if (!fixed_link)
- return 1;
-
- status.link = 1;
- status.duplex = be32_to_cpu(fixed_link[1]);
- /* Force full-duplex settings here, since BOLT v0.86 would set MoCA
- * links to half-duplex, and that might cause packet losses since the
- * link between GENET or SWITCH and MoCA's ECL is full-duplex.
- *
- * BOLT does not support configuring the duplex type, so we can safely
- * override this to DUPLEX_FULL.
- */
- status.duplex = DUPLEX_FULL;
- status.speed = be32_to_cpu(fixed_link[2]);
- status.pause = be32_to_cpu(fixed_link[3]);
- status.asym_pause = be32_to_cpu(fixed_link[4]);
-
- ret = fixed_phy_add(PHY_POLL, be32_to_cpu(fixed_link[0]), &status);
- if (ret)
- of_node_put(np);
-
- return ret;
-}
-
-static int __init of_add_fixed_phys(void)
-{
- struct device_node *np, *child, *port;
-
- for_each_compatible_node(np, NULL, "brcm,bcm7445-switch-v4.0") {
- for_each_child_of_node(np, child) {
- for_each_child_of_node(child, port) {
- if (of_add_one_fixed_phy(port))
- continue;
- }
- }
- }
-
- /* SYSTEMPORT Ethernet MAC also uses the 'fixed-link' property */
- for_each_compatible_node(np, NULL, "brcm,systemport-v1.00")
- of_add_one_fixed_phy(np);
-
- /* GENET uses the 'fixed-link' property */
- for_each_compatible_node(np, NULL, "brcm,genet-v4")
- of_add_one_fixed_phy(np);
-
- return 0;
-}
-#else
-static inline void of_add_fixed_phys(void)
-{
-}
-#endif /* CONFIG_FIXED_PHY */
-
#define CPU_CREDIT_REG_OFFSET 0x184
#define CPU_CREDIT_REG_MCPx_WR_PAIRING_EN_MASK 0x70000000
static void __iomem *cpubiuctrl_base;
+static unsigned int mcp_wr_pairing_en;
/*
- * HW7445-1920: Disable MCP write pairing to improve stability on long term
- * stress test.
+ * HW7445-1920: On affected chips, disable MCP write pairing to improve
+ * stability on long term stress test.
*/
-static int __init disable_mcp_write_pairing(void)
+static int __init mcp_write_pairing_set(void)
{
u32 creds = 0;
@@ -162,7 +106,11 @@
return -1;
creds = __raw_readl(cpubiuctrl_base + CPU_CREDIT_REG_OFFSET);
- if (creds & CPU_CREDIT_REG_MCPx_WR_PAIRING_EN_MASK) {
+ if (mcp_wr_pairing_en) {
+ pr_info("MCP: Enabling write pairing\n");
+ __raw_writel(creds | CPU_CREDIT_REG_MCPx_WR_PAIRING_EN_MASK,
+ cpubiuctrl_base + CPU_CREDIT_REG_OFFSET);
+ } else if (creds & CPU_CREDIT_REG_MCPx_WR_PAIRING_EN_MASK) {
pr_info("MCP: Disabling write pairing\n");
__raw_writel(creds & ~CPU_CREDIT_REG_MCPx_WR_PAIRING_EN_MASK,
cpubiuctrl_base + CPU_CREDIT_REG_OFFSET);
@@ -185,6 +133,8 @@
if (!cpubiuctrl_base)
pr_err("failed to remap BIU control base\n");
+ mcp_wr_pairing_en = of_property_read_bool(np, "brcm,write-pairing");
+
of_node_put(np);
}
@@ -212,35 +162,20 @@
};
#endif
-void brcmstb_irq0_init(void)
-{
- BDEV_WR(BCHP_IRQ0_IRQEN, BCHP_IRQ0_IRQEN_uarta_irqen_MASK
- | BCHP_IRQ0_IRQEN_uartb_irqen_MASK
- | BCHP_IRQ0_IRQEN_uartc_irqen_MASK
- );
-}
-
static void __init brcmstb_init_irq(void)
{
/* Force lazily-disabled IRQs to be masked before suspend */
gic_arch_extn.flags |= IRQCHIP_MASK_ON_SUSPEND;
- brcmstb_irq0_init();
irqchip_init();
}
static void __init brcmstb_init_machine(void)
{
struct platform_device_info devinfo = { .name = "cpufreq-cpu0", };
- int ret;
of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
cma_register();
- of_add_fixed_phys();
- brcmstb_hook_fault_code();
- ret = brcmstb_pm_init();
- if (ret)
- pr_warn("PM: initialization failed with code %d\n", ret);
platform_device_register_full(&devinfo);
#ifdef CONFIG_PM_SLEEP
register_syscore_ops(&brcmstb_cpu_credit_syscore_ops);
@@ -250,93 +185,11 @@
static void __init brcmstb_init_early(void)
{
setup_hifcpubiuctrl_regs();
- if (disable_mcp_write_pairing())
+ if (mcp_write_pairing_set())
pr_err("MCP: Unable to disable write pairing!\n");
add_preferred_console("ttyS", 0, "115200");
}
-#ifdef CONFIG_BRCMSTB_USE_MEGA_BARRIER
-static phys_addr_t so_mem_paddr[NR_BANKS];
-static void __iomem *so_mem_vaddr[NR_BANKS];
-
-static struct cma_dev *cma_dev_get_by_addr(phys_addr_t start, phys_addr_t end)
-{
- int i = 0;
- for (i = 0; i < CMA_DEV_MAX; i++) {
- struct cma_dev *cma_dev = cma_dev_get_cma_dev(i);
- if (!cma_dev)
- continue;
-
- if (cma_dev->range.base >= start &&
- (cma_dev->range.base + cma_dev->range.size) <= end)
- return cma_dev;
- }
-
- return NULL;
-}
-
-static int brcmstb_mega_barrier_init(void)
-{
- int bank_nr;
-
- pr_info("brcmstb: setting up mega-barrier workaround\n");
-
- for_each_bank(bank_nr, &meminfo) {
- struct page *page;
- struct cma_dev *cma_dev;
- const struct membank *bank = &meminfo.bank[bank_nr];
- const int len = PAGE_SIZE;
-
- cma_dev = cma_dev_get_by_addr(bank_phys_start(bank),
- bank_phys_end(bank));
- if (!cma_dev) {
- phys_addr_t start = bank_phys_start(bank);
- phys_addr_t end = bank_phys_end(bank);
- pr_warn("no cma dev for addr range (%pa,%pa) exists\n",
- &start,
- &end);
- continue;
- }
-
- page = dma_alloc_from_contiguous(cma_dev->dev,
- len >> PAGE_SHIFT, 0);
- if (!page) {
- pr_err("failed to alloc page for dummy store on bank %d\n",
- bank_nr);
- continue;
- }
-
- so_mem_paddr[bank_nr] = page_to_phys(page);
- so_mem_vaddr[bank_nr] = cma_dev_kva_map(page, len >> PAGE_SHIFT,
- pgprot_noncached(pgprot_kernel));
- }
-
- return 0;
-}
-late_initcall(brcmstb_mega_barrier_init);
-
-/*
- * The suggested workaround requires a dummy store to memory mapped as
- * STRONGLY ORDERED on each MEMC, followed by a data sync barrier.
- *
- * This function should be called following all cache flush operations.
- */
-void brcmstb_mega_barrier(void)
-{
- int bank_nr;
-
- __asm__("dsb");
-
- for (bank_nr = 0; bank_nr < NR_BANKS; bank_nr++) {
- if (so_mem_vaddr[bank_nr])
- writel_relaxed(0, so_mem_vaddr[bank_nr]);
- }
-
- __asm__("dsb");
-}
-EXPORT_SYMBOL(brcmstb_mega_barrier);
-#endif /* CONFIG_BRCMSTB_USE_MEGA_BARRIER */
-
static void __init brcmstb_init_time(void)
{
brcmstb_clocks_init();
@@ -344,57 +197,6 @@
}
#endif /* CONFIG_BRCMSTB */
-/***********************************************************************
- * SMP boot
- ***********************************************************************/
-
-#ifdef CONFIG_SMP
-static DEFINE_SPINLOCK(boot_lock);
-
-static void brcmstb_secondary_init(unsigned int cpu)
-{
- /*
- * Synchronise with the boot thread.
- */
- spin_lock(&boot_lock);
- spin_unlock(&boot_lock);
-}
-
-static int brcmstb_boot_secondary(unsigned int cpu,
- struct task_struct *idle)
-{
- /*
- * set synchronisation state between this boot processor
- * and the secondary one
- */
- spin_lock(&boot_lock);
-
- /* Bring up power to the core if necessary */
- if (brcmstb_cpu_get_power_state(cpu) == 0)
- brcmstb_cpu_power_on(cpu);
-
- brcmstb_cpu_boot(cpu);
-
- /*
- * now the secondary core is starting up let it run its
- * calibrations, then wait for it to finish
- */
- spin_unlock(&boot_lock);
-
- return 0;
-}
-
-struct smp_operations brcmstb_smp_ops __initdata = {
- .smp_prepare_cpus = brcmstb_cpu_ctrl_setup,
- .smp_secondary_init = brcmstb_secondary_init,
- .smp_boot_secondary = brcmstb_boot_secondary,
-#ifdef CONFIG_HOTPLUG_CPU
- .cpu_kill = brcmstb_cpu_kill,
- .cpu_die = brcmstb_cpu_die,
-#endif
-};
-#endif /* CONFIG_SMP */
-
DT_MACHINE_START(BRCMSTB, "Broadcom STB (Flattened Device Tree)")
.dt_compat = brcmstb_match,
#if defined(CONFIG_BRCMSTB)
@@ -405,7 +207,4 @@
.init_irq = brcmstb_init_irq,
.init_time = brcmstb_init_time,
#endif
-#ifdef CONFIG_SMP
- .smp = smp_ops(brcmstb_smp_ops),
-#endif
MACHINE_END
diff --git a/arch/arm/mach-bcm/brcmstb.h b/arch/arm/mach-bcm/brcmstb.h
deleted file mode 100644
index 59eaa95..0000000
--- a/arch/arm/mach-bcm/brcmstb.h
+++ /dev/null
@@ -1,67 +0,0 @@
-/*
- * Copyright (C) 2013 Broadcom Corporation
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation version 2.
- *
- * This program is distributed "as is" WITHOUT ANY WARRANTY of any
- * kind, whether express or implied; without even the implied warranty
- * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#ifndef __BRCMSTB_H__
-#define __BRCMSTB_H__
-
-#if !defined(__ASSEMBLY__)
-#include <linux/smp.h>
-#endif
-
-#if !defined(__ASSEMBLY__)
-extern void brcmstb_secondary_startup(void);
-extern void brcmstb_cpu_boot(unsigned int cpu);
-extern void brcmstb_cpu_power_on(unsigned int cpu);
-extern int brcmstb_cpu_get_power_state(unsigned int cpu);
-extern struct smp_operations brcmstb_smp_ops;
-#if defined(CONFIG_HOTPLUG_CPU)
-extern void brcmstb_cpu_die(unsigned int cpu);
-extern int brcmstb_cpu_kill(unsigned int cpu);
-void __init brcmstb_cpu_ctrl_setup(unsigned int max_cpus);
-#else
-static inline void brcmstb_cpu_die(unsigned int cpu) {}
-static inline int brcmstb_cpu_kill(unsigned int cpu)
-{
- return 0;
-}
-static inline void __init brcmstb_cpu_ctrl_setup(unsigned int max_cpus) {}
-#endif
-#ifdef CONFIG_CMA
-extern void __init cma_reserve(void);
-extern void __init cma_register(void);
-#else
-static inline void cma_reserve(void) { }
-static inline void cma_register(void) { }
-#endif
-#endif
-
-#ifdef CONFIG_PM
-int brcmstb_regsave_init(void);
-int brcmstb_pm_init(void);
-#else
-static inline int brcmstb_pm_init(void)
-{
- return 0;
-}
-
-static inline int brcmstb_regsave_init(void)
-{
- return 0;
-}
-#endif /* CONFIG_PM */
-
-extern void brcmstb_hook_fault_code(void);
-
-void brcmstb_irq0_init(void);
-
-#endif /* __BRCMSTB_H__ */
diff --git a/arch/arm/mach-bcm/headsmp-brcmstb.h b/arch/arm/mach-bcm/headsmp-brcmstb.h
new file mode 100644
index 0000000..884a41a
--- /dev/null
+++ b/arch/arm/mach-bcm/headsmp-brcmstb.h
@@ -0,0 +1,23 @@
+/*
+ * Copyright (C) 2013 Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation version 2.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef __HEADSMP_BRCMSTB_H__
+#define __HEADSMP_BRCMSTB_H__
+
+#if !defined(__ASSEMBLY__)
+
+extern void brcmstb_secondary_startup(void);
+
+#endif /* !defined(__ASSEMBLY__) */
+
+#endif /* __HEADSMP_BRCMSTB_H__ */
diff --git a/arch/arm/mach-bcm/pci-brcmstb.c b/arch/arm/mach-bcm/pci-brcmstb.c
index 4ac193f..5a8591b 100644
--- a/arch/arm/mach-bcm/pci-brcmstb.c
+++ b/arch/arm/mach-bcm/pci-brcmstb.c
@@ -16,6 +16,7 @@
*/
#include <linux/init.h>
#include <linux/types.h>
+#include <linux/slab.h>
#include <linux/pci.h>
#include <linux/kernel.h>
#include <linux/ioport.h>
@@ -23,6 +24,7 @@
#include <linux/delay.h>
#include <linux/io.h>
#include <linux/clk.h>
+#include <linux/list.h>
#include <linux/printk.h>
#include <linux/syscore_ops.h>
#include <linux/of_irq.h>
@@ -52,6 +54,7 @@
#define PCIE_MISC_RC_BAR3_CONFIG_HI 0x4040
#define PCIE_MISC_MSI_BAR_CONFIG_LO 0x4044
#define PCIE_MISC_MSI_BAR_CONFIG_HI 0x4048
+#define PCIE_MISC_PCIE_CTRL 0x4064
#define PCIE_MISC_PCIE_STATUS 0x4068
#define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_LIMIT 0x4070
#define PCIE_MISC_HARD_PCIE_HARD_DEBUG 0x4204
@@ -62,8 +65,8 @@
#define PCIE_EXT_CFG_PCIE_EXT_CFG_DATA 0x9004
#define PCIE_RGR1_SW_INIT_1 0x9210
-#define BRCM_MAX_PCI_CONTROLLERS 0x2
#define BRCM_NUM_PCI_OUT_WINS 0x4
+#define BRCM_MAX_SCB 0x4
#define PCI_BUSNUM_SHIFT 20
#define PCI_SLOT_SHIFT 15
@@ -83,14 +86,13 @@
};
static int brcm_setup_pcie_bridge(int nr, struct pci_sys_data *sys);
-struct pci_bus __init *brcm_pci_sys_scan_bus(int nr, struct pci_sys_data *sys);
static int __init brcm_map_irq(const struct pci_dev *dev, u8 slot, u8 pin);
static struct hw_pci brcm_pcie_hw __initdata = {
.nr_controllers = 0,
.setup = brcm_setup_pcie_bridge,
- .scan = brcm_pci_sys_scan_bus,
.map_irq = brcm_map_irq,
+ .ops = &brcm_pci_ops,
};
struct brcm_window {
@@ -103,27 +105,28 @@
/* Internal Bus Controller Information.*/
-static struct brcm_pci_bus {
+struct brcm_pcie {
+ struct list_head list;
void __iomem *base;
char name[8];
bool suspended;
- int busnr_start;
- int busnr_end;
struct clk *clk;
struct device_node *dn;
int pcie_irq[4];
int num_out_wins;
bool ssc;
int gen;
+ int scb_size_vals[BRCM_MAX_SCB];
struct brcm_window out_wins[BRCM_NUM_PCI_OUT_WINS];
struct pci_sys_data *sys;
struct device *dev;
-} brcm_buses[BRCM_MAX_PCI_CONTROLLERS];
+};
+static struct list_head brcm_pcie;
static int brcm_num_pci_controllers;
-static int next_busnr;
static int num_memc;
static void turn_off(void __iomem *base);
+static void enter_l23(struct brcm_pcie *pcie);
/***********************************************************************
@@ -138,6 +141,21 @@
#endif
+static void remove_pcie(struct brcm_pcie *pcie)
+{
+ struct list_head *pos, *q;
+ struct brcm_pcie *tmp;
+
+ list_for_each_safe(pos, q, &brcm_pcie) {
+ tmp = list_entry(pos, struct brcm_pcie, list);
+ if (tmp == pcie) {
+ list_del(pos);
+ break;
+ }
+ }
+}
+
+
/* negative return value indicates error */
static int mdio_read(void __iomem *base, u8 phyad, u8 regad)
{
@@ -175,20 +193,6 @@
}
-static int busnr_to_nr(int busnr)
-{
- int i;
-
- for (i = 0; i < brcm_num_pci_controllers; i++) {
- struct brcm_pci_bus *bus = &brcm_buses[i];
- if (bus->busnr_start >= 0
- && bus->busnr_start <= busnr
- && busnr <= bus->busnr_end)
- return i;
- }
- return -EINVAL;
-}
-
static void wr_fld(void __iomem *p, u32 mask, int shift, u32 val)
{
u32 reg = __raw_readl(p);
@@ -269,18 +273,18 @@
}
-static int is_pcie_link_up(int nr)
+static int is_pcie_link_up(struct brcm_pcie *pcie)
{
- void __iomem *base = brcm_buses[nr].base;
+ void __iomem *base = pcie->base;
u32 val = __raw_readl(base + PCIE_MISC_PCIE_STATUS);
return ((val & 0x30) == 0x30) ? 1 : 0;
}
-static void brcm_pcie_setup_early(int nr)
+static void brcm_pcie_setup_early(struct brcm_pcie *pcie)
{
- struct brcm_pci_bus *bus = &brcm_buses[nr];
- void __iomem *base = bus->base;
+ void __iomem *base = pcie->base;
+ unsigned int scb_size_val;
int i;
/* reset the bridge and the endpoint device */
@@ -299,8 +303,8 @@
/* enable SCB_MAX_BURST_SIZE | CSR_READ_UR_MODE | SCB_ACCESS_EN */
__raw_writel(0x81e03000, base + PCIE_MISC_MISC_CTRL);
- for (i = 0; i < bus->num_out_wins; i++) {
- struct brcm_window *w = &bus->out_wins[i];
+ for (i = 0; i < pcie->num_out_wins; i++) {
+ struct brcm_window *w = &pcie->out_wins[i];
set_pcie_outbound_win(base, i, w->cpu_addr, w->size);
}
@@ -308,14 +312,25 @@
__raw_writel(0x00000011, base + PCIE_MISC_RC_BAR2_CONFIG_LO);
__raw_writel(0x00000000, base + PCIE_MISC_RC_BAR2_CONFIG_HI);
- /* field: SCB0_SIZE = 1 Gb */
- wr_fld(base + PCIE_MISC_MISC_CTRL, 0xf8000000, 27, 0x0f);
- /* field: SCB1_SIZE = 1 Gb */
- if (num_memc > 1)
- wr_fld(base + PCIE_MISC_MISC_CTRL, 0x07c00000, 22, 0x0f);
- /* field: SCB2_SIZE = 1 Gb */
- if (num_memc > 2)
- wr_fld(base + PCIE_MISC_MISC_CTRL, 0x0000001f, 0, 0x0f);
+ /* field: SCB0_SIZE, default = 0xf (1 GB) */
+ scb_size_val = pcie->scb_size_vals[0] ? pcie->scb_size_vals[0] : 0xf;
+ wr_fld(base + PCIE_MISC_MISC_CTRL, 0xf8000000, 27, scb_size_val);
+
+ /* field: SCB1_SIZE, default = 0xf (1 GB) */
+ if (num_memc > 1) {
+ scb_size_val = pcie->scb_size_vals[1]
+ ? pcie->scb_size_vals[1] : 0xf;
+ wr_fld(base + PCIE_MISC_MISC_CTRL, 0x07c00000,
+ 22, scb_size_val);
+ }
+
+ /* field: SCB2_SIZE, default = 0xf (1 GB) */
+ if (num_memc > 2) {
+ scb_size_val = pcie->scb_size_vals[2]
+ ? pcie->scb_size_vals[2] : 0xf;
+ wr_fld(base + PCIE_MISC_MISC_CTRL, 0x0000001f,
+ 0, scb_size_val);
+ }
/* disable the PCIE->GISB memory window */
__raw_writel(0x00000000, base + PCIE_MISC_RC_BAR1_CONFIG_LO);
@@ -334,11 +349,11 @@
__raw_writel(0xffffffff, base + PCIE_INTR2_CPU_MASK_SET);
(void) __raw_readl(base + PCIE_INTR2_CPU_MASK_SET);
- if (bus->ssc)
+ if (pcie->ssc)
if (set_ssc(base))
- dev_err(bus->dev, "error while configuring ssc mode\n");
- if (bus->gen)
- set_gen(base, bus->gen);
+ dev_err(pcie->dev, "error while configuring ssc mode\n");
+ if (pcie->gen)
+ set_gen(base, pcie->gen);
/* take the EP device out of reset */
/* field: PCIE_SW_PERST = 0 */
@@ -348,29 +363,25 @@
static int brcm_setup_pcie_bridge(int nr, struct pci_sys_data *sys)
{
- struct brcm_pci_bus *bus = &brcm_buses[nr];
- void __iomem *base = bus->base;
- const int limit = bus->suspended ? 1000 : 100;
+ struct brcm_pcie *pcie = sys->private_data;
+ void __iomem *base = pcie->base;
+ const int limit = pcie->suspended ? 1000 : 100;
struct clk *clk;
unsigned status;
static const char *link_speed[4] = { "???", "2.5", "5.0", "8.0" };
int i, j;
- bus->sys = sys;
- if (!bus->suspended) {
- bus->busnr_start = sys->busnr;
- bus->busnr_end = 0xff;
- }
+ pcie->sys = sys;
/* Give the RC/EP time to wake up, before trying to configure RC.
* Intermittently check status for link-up, up to a total of 100ms
* when we don't know if the device is there, and up to 1000ms if
* we do know the device is there. */
- for (i = 1, j = 0; j < limit && !is_pcie_link_up(nr); j += i, i = i*2)
+ for (i = 1, j = 0; j < limit && !is_pcie_link_up(pcie); j += i, i = i*2)
mdelay(i + j > limit ? limit - j : i);
- if (!is_pcie_link_up(nr)) {
- dev_info(bus->dev, "link down\n");
+ if (!is_pcie_link_up(pcie)) {
+ dev_info(pcie->dev, "link down\n");
goto FAIL;
}
@@ -378,19 +389,19 @@
* a PCI-PCI bridge */
wr_fld_rb(base + PCIE_RC_CFG_PRIV1_ID_VAL3, 0x00ffffff, 0, 0x060400);
- if (!bus->suspended)
- for (i = 0; i < bus->num_out_wins; i++)
+ if (!pcie->suspended)
+ for (i = 0; i < pcie->num_out_wins; i++)
pci_add_resource_offset(&sys->resources,
- &bus->out_wins[i].pcie_iomem_res,
+ &pcie->out_wins[i].pcie_iomem_res,
sys->mem_offset);
status = __raw_readl(base + PCIE_RC_CFG_PCIE_LINK_STATUS_CONTROL);
- dev_info(bus->dev, "link up, %s Gbps x%u\n",
+ dev_info(pcie->dev, "link up, %s Gbps x%u\n",
link_speed[((status & 0x000f0000) >> 16) & 0x3],
(status & 0x03f00000) >> 20);
- if (bus->ssc && is_ssc(base) != 0)
- dev_err(bus->dev, "failed to enter ssc mode\n");
+ if (pcie->ssc && is_ssc(base) != 0)
+ dev_err(pcie->dev, "failed to enter ssc mode\n");
/* Enable configuration request retry (see pci_scan_device()) */
/* field RC_CRS_EN = 1 */
@@ -401,40 +412,28 @@
wr_fld_rb(base + PCIE_RC_CFG_VENDOR_VENDOR_SPECIFIC_REG1, 0x0000000c, 2,
DATA_ENDIAN);
+ /* Refclk from RC should be gated with CLKREQ# input when ASPM L0s,L1
+ * is enabled => setting the CLKREQ_DEBUG_ENABLE field to 1. */
+ wr_fld_rb(base + PCIE_MISC_HARD_PCIE_HARD_DEBUG, 0x00000002, 1, 1);
+
return 1;
FAIL:
-#if defined(CONFIG_PM)
- turn_off(base);
-#endif
- clk = brcm_buses[nr].clk;
- if (bus->suspended)
+ if (IS_ENABLED(CONFIG_PM))
+ turn_off(base);
+
+ clk = pcie->clk;
+ if (pcie->suspended)
clk_disable(clk);
else {
clk_disable_unprepare(clk);
clk_put(clk);
- bus->busnr_start = -1;
- bus->busnr_end = -1;
+ remove_pcie(pcie);
}
return 0;
}
-struct pci_bus __init *brcm_pci_sys_scan_bus(int nr, struct pci_sys_data *sys)
-{
- struct pci_bus *pbus;
- struct brcm_pci_bus *bus = &brcm_buses[nr];
-
- dev_info(bus->dev, "scanning root bus %d, busnr %d\n", nr, sys->busnr);
- pbus = pci_scan_root_bus(bus->dev, sys->busnr, &brcm_pci_ops, sys,
- &sys->resources);
- bus->busnr_end = pbus->busn_res.end;
- next_busnr = bus->busnr_end + 1;
- return pbus;
-}
-
-
-#if defined(CONFIG_PM)
/*
* syscore device to handle PCIe bus suspend and resume
*/
@@ -443,6 +442,8 @@
{
/* Reset endpoint device */
wr_fld_rb(base + PCIE_RGR1_SW_INIT_1, 0x00000001, 0, 1);
+ /* deassert request for L23 in case it was asserted */
+ wr_fld_rb(base + PCIE_MISC_PCIE_CTRL, 0x1, 0, 0);
/* SERDES_IDDQ = 1 */
wr_fld_rb(base + PCIE_MISC_HARD_PCIE_HARD_DEBUG, 0x08000000,
27, 1);
@@ -451,20 +452,33 @@
}
+static void enter_l23(struct brcm_pcie *pcie)
+{
+ void __iomem *base = pcie->base;
+ int timeout = 1000;
+ int l23;
+
+ /* assert request for L23 */
+ wr_fld_rb(base + PCIE_MISC_PCIE_CTRL, 0x1, 0, 1);
+ do {
+ /* poll L23 status */
+ l23 = __raw_readl(base + PCIE_MISC_PCIE_STATUS) & (1 << 6);
+ } while (--timeout && !l23);
+
+ if (!timeout)
+ dev_err(pcie->dev, "failed to enter L23\n");
+}
+
+
static int pcie_suspend(void)
{
- int i;
+ struct brcm_pcie *pcie;
- for (i = 0; i < brcm_num_pci_controllers; i++) {
- struct brcm_pci_bus *bus = &brcm_buses[i];
- void __iomem *base = bus->base;
-
- if (bus->busnr_start < 0)
- continue;
-
- turn_off(base);
- clk_disable(bus->clk);
- bus->suspended = true;
+ list_for_each_entry(pcie, &brcm_pcie, list) {
+ enter_l23(pcie);
+ turn_off(pcie->base);
+ clk_disable(pcie->clk);
+ pcie->suspended = true;
}
return 0;
}
@@ -472,16 +486,14 @@
static void pcie_resume(void)
{
- int i;
+ int i = 0;
+ struct brcm_pcie *pcie;
- for (i = 0; i < brcm_num_pci_controllers; i++) {
- struct brcm_pci_bus *bus = &brcm_buses[i];
- void __iomem *base = bus->base;
+ list_for_each_entry(pcie, &brcm_pcie, list) {
+ void __iomem *base;
- if (bus->busnr_start < 0)
- continue;
-
- clk_enable(bus->clk);
+ base = pcie->base;
+ clk_enable(pcie->clk);
/* Take bridge out of reset so we can access the SERDES reg */
wr_fld_rb(base + PCIE_RGR1_SW_INIT_1, 0x00000002, 1, 0);
@@ -492,17 +504,12 @@
/* wait for serdes to be stable */
udelay(100);
- brcm_pcie_setup_early(i);
+ brcm_pcie_setup_early(pcie);
}
- for (i = 0; i < brcm_num_pci_controllers; i++) {
- struct brcm_pci_bus *bus = &brcm_buses[i];
-
- if (bus->busnr_start < 0)
- continue;
-
- brcm_setup_pcie_bridge(i, bus->sys);
- bus->suspended = false;
+ list_for_each_entry(pcie, &brcm_pcie, list) {
+ brcm_setup_pcie_bridge(i++, pcie->sys);
+ pcie->suspended = false;
}
}
@@ -510,7 +517,6 @@
.suspend = pcie_suspend,
.resume = pcie_resume,
};
-#endif
/***********************************************************************
@@ -544,16 +550,17 @@
int where, int size, u32 data)
{
u32 val = 0, mask, shift;
- int nr = busnr_to_nr(bus->number);
+ struct pci_sys_data *sys = bus->sysdata;
+ struct brcm_pcie *pcie = sys->private_data;
void __iomem *base;
bool rc_access;
int idx;
- if (nr < 0 || !is_pcie_link_up(nr))
+ if (!is_pcie_link_up(pcie))
return PCIBIOS_DEVICE_NOT_FOUND;
- base = brcm_buses[nr].base;
- rc_access = bus->number == brcm_buses[nr].busnr_start;
+ base = pcie->base;
+ rc_access = sys->busnr == bus->number;
idx = cfg_index(bus->number, devfn, where);
BUG_ON(((where & 3) + size) > 4);
@@ -585,17 +592,18 @@
static int brcm_pci_read_config(struct pci_bus *bus, unsigned int devfn,
int where, int size, u32 *data)
{
+ struct pci_sys_data *sys = bus->sysdata;
+ struct brcm_pcie *pcie = sys->private_data;
u32 val, mask, shift;
- int nr = busnr_to_nr(bus->number);
void __iomem *base;
bool rc_access;
int idx;
- if (nr < 0 || !is_pcie_link_up(nr))
+ if (!is_pcie_link_up(pcie))
return PCIBIOS_DEVICE_NOT_FOUND;
- base = brcm_buses[nr].base;
- rc_access = bus->number == brcm_buses[nr].busnr_start;
+ base = pcie->base;
+ rc_access = sys->busnr == bus->number;
idx = cfg_index(bus->number, devfn, where);
BUG_ON(((where & 3) + size) > 4);
@@ -624,11 +632,13 @@
***********************************************************************/
static int __init brcm_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
{
- int nr = busnr_to_nr(dev->bus->number);
- if (nr >= 0) {
+ struct pci_sys_data *sys = dev->bus->sysdata;
+ struct brcm_pcie *pcie = sys->private_data;
+
+ if (pcie) {
if ((pin - 1) > 3)
return 0;
- return brcm_buses[nr].pcie_irq[pin - 1];
+ return pcie->pcie_irq[pin - 1];
}
return 0;
}
@@ -640,13 +650,13 @@
static void __attribute__((__section__("pci_fixup_early")))
brcm_pcibios_fixup(struct pci_dev *dev)
{
+ struct pci_sys_data *sys = dev->bus->sysdata;
+ struct brcm_pcie *pcie = sys->private_data;
int slot = PCI_SLOT(dev->devfn);
- int nr = busnr_to_nr(dev->bus->number);
- struct brcm_pci_bus *bus = &brcm_buses[nr];
- dev_info(bus->dev,
+ dev_info(pcie->dev,
"found device %04x:%04x on bus %d (%s), slot %d (irq %d)\n",
- dev->vendor, dev->device, dev->bus->number, bus->name,
+ dev->vendor, dev->device, dev->bus->number, pcie->name,
slot, brcm_map_irq(dev, slot, 1));
}
DECLARE_PCI_FIXUP_EARLY(PCI_ANY_ID, PCI_ANY_ID, brcm_pcibios_fixup);
@@ -660,12 +670,16 @@
struct device_node *dn = pdev->dev.of_node, *mdn;
const u32 *imap_prop;
int len, i, irq_offset, rlen, pna, np, ret;
- struct brcm_pci_bus *bus = &brcm_buses[brcm_num_pci_controllers];
+ struct brcm_pcie *pcie;
struct resource *r;
- const u32 *ranges;
+ const u32 *ranges, *log2_scb_sizes, *dma_ranges;
void __iomem *base;
u32 tmp;
+ pcie = devm_kzalloc(&pdev->dev, sizeof(struct brcm_pcie), GFP_KERNEL);
+ if (!pcie)
+ return -ENOMEM;
+
/* 'num_memc' will be set only by the first controller, and all
* other controllers will use the value set by the first. */
if (num_memc == 0)
@@ -689,52 +703,73 @@
irq_offset = irq_of_parse_and_map(dn, 0);
for (i = 0; i < 4 && i*4 < len; i++)
- bus->pcie_irq[i] = irq_offset
+ pcie->pcie_irq[i] = irq_offset
+ of_read_number(imap_prop + (i * 7 + 5), 1);
- snprintf(bus->name,
- sizeof(bus->name)-1, "PCIe%d", brcm_num_pci_controllers);
- bus->suspended = false;
- bus->clk = of_clk_get_by_name(dn, "sw_pcie");
- if (IS_ERR(bus->clk)) {
+ snprintf(pcie->name,
+ sizeof(pcie->name)-1, "PCIe%d", brcm_num_pci_controllers);
+ pcie->suspended = false;
+ pcie->clk = of_clk_get_by_name(dn, "sw_pcie");
+ if (IS_ERR(pcie->clk)) {
dev_err(&pdev->dev, "could not get clock\n");
- bus->clk = NULL;
+ pcie->clk = NULL;
}
- ret = clk_prepare_enable(bus->clk);
+ ret = clk_prepare_enable(pcie->clk);
if (ret) {
dev_err(&pdev->dev, "could not enable clock\n");
return ret;
}
- bus->dn = dn;
- bus->base = base;
- bus->dev = &pdev->dev;
- bus->gen = 0;
+ pcie->dn = dn;
+ pcie->base = base;
+ pcie->dev = &pdev->dev;
+ pcie->gen = 0;
ret = of_property_read_u32(dn, "brcm,gen", &tmp);
if (ret == 0) {
if (tmp > 0 && tmp < 3)
- bus->gen = (int) tmp;
+ pcie->gen = (int) tmp;
else
- dev_warn(bus->dev, "bad DT value for prop 'brcm,gen");
+ dev_warn(pcie->dev, "bad DT value for prop 'brcm,gen");
} else if (ret != -EINVAL) {
- dev_warn(bus->dev, "error reading DT prop 'brcm,gen");
+ dev_warn(pcie->dev, "error reading DT prop 'brcm,gen");
}
- bus->ssc = of_property_read_bool(dn, "brcm,ssc");
+ pcie->ssc = of_property_read_bool(dn, "brcm,ssc");
+
+ /* Get the value for the log2 of the scb sizes. Subtract 15 from
+ * each because the target register field has 0==disabled and 1==64KB.
+ */
+ log2_scb_sizes = of_get_property(dn, "brcm,log2-scb-sizes", &rlen);
+ if (log2_scb_sizes != NULL)
+ for (i = 0; i < rlen/4; i++)
+ pcie->scb_size_vals[i]
+ = (int) of_read_number(log2_scb_sizes + i, 1)
+ - 15;
+
+ /* Look for the dma-ranges property. If it exists, issue a warning
+ * as PCIe drivers may not work. This is because the identity
+ * mapping between system memory and PCIe space is not preserved,
+ * and we need Linux to massage the dma_addr_t values it gets
+ * from dma memory allocation. This functionality will be added
+ * in the near future.
+ */
+ dma_ranges = of_get_property(dn, "dma-ranges", &rlen);
+ if (dma_ranges != NULL)
+ dev_warn(pcie->dev, "no identity map; PCI drivers may fail");
ranges = of_get_property(dn, "ranges", &rlen);
if (ranges == NULL) {
- dev_err(bus->dev, "no ranges property in dev tree.\n");
+ dev_err(pcie->dev, "no ranges property in dev tree.\n");
return -EINVAL;
}
/* set up CPU->PCIE memory windows (max of four) */
pna = of_n_addr_cells(dn);
np = pna + 5;
- bus->num_out_wins = rlen / (np * 4);
+ pcie->num_out_wins = rlen / (np * 4);
- for (i = 0; i < bus->num_out_wins; i++) {
- struct brcm_window *w = &bus->out_wins[i];
+ for (i = 0; i < pcie->num_out_wins; i++) {
+ struct brcm_window *w = &pcie->out_wins[i];
w->info = (u32) of_read_ulong(ranges + 0, 1);
w->pci_addr = of_read_number(ranges + 1, 2);
w->cpu_addr = of_translate_address(dn, ranges + 3);
@@ -760,9 +795,10 @@
* before attempting configuration accesses. So we let the link
* negotiation happen in the background instead of busy-waiting.
*/
- brcm_pcie_setup_early(brcm_num_pci_controllers);
-
+ brcm_pcie_setup_early(pcie);
+ list_add_tail(&pcie->list, &brcm_pcie);
brcm_num_pci_controllers++;
+
return 0;
}
@@ -786,21 +822,30 @@
int __init brcm_pcibios_init(void)
{
- int i, ret;
+ int ret;
- for (i = 0; i < BRCM_MAX_PCI_CONTROLLERS; i++) {
- brcm_buses[i].busnr_start = -1;
- brcm_buses[i].busnr_end = -1;
- }
-
+ INIT_LIST_HEAD(&brcm_pcie);
ret = platform_driver_probe(&brcm_pci_driver, brcm_pci_probe);
if (!ret && brcm_num_pci_controllers > 0) {
- brcm_pcie_hw.nr_controllers = brcm_num_pci_controllers;
-#if defined(CONFIG_PM)
- register_syscore_ops(&pcie_pm_ops);
-#endif
+ void **private_data;
+ struct brcm_pcie *pcie;
+ int i = 0;
+ brcm_pcie_hw.nr_controllers = brcm_num_pci_controllers;
+ if (IS_ENABLED(CONFIG_PM))
+ register_syscore_ops(&pcie_pm_ops);
+
+ private_data = kzalloc(brcm_num_pci_controllers
+ * sizeof(void *), GFP_KERNEL);
+ if (!private_data)
+ return -ENOMEM;
+ list_for_each_entry(pcie, &brcm_pcie, list)
+ private_data[i++] = pcie;
+ BUG_ON(i != brcm_num_pci_controllers);
+ brcm_pcie_hw.private_data = private_data;
pci_common_init(&brcm_pcie_hw);
+ kfree(brcm_pcie_hw.private_data);
+ brcm_pcie_hw.private_data = NULL;
}
return ret;
}
diff --git a/arch/arm/mach-bcm/hotplug-brcmstb.c b/arch/arm/mach-bcm/platsmp-brcmstb.c
similarity index 87%
rename from arch/arm/mach-bcm/hotplug-brcmstb.c
rename to arch/arm/mach-bcm/platsmp-brcmstb.c
index b5317a0..434b7b3 100644
--- a/arch/arm/mach-bcm/hotplug-brcmstb.c
+++ b/arch/arm/mach-bcm/platsmp-brcmstb.c
@@ -1,7 +1,7 @@
/*
- * Broadcom STB CPU hotplug support for ARM
+ * Broadcom STB CPU SMP and hotplug support for ARM
*
- * Copyright (C) 2013 Broadcom Corporation
+ * Copyright (C) 2013-2015 Broadcom Corporation
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
@@ -13,15 +13,12 @@
* GNU General Public License for more details.
*/
-#include <linux/delay.h>
-#include <linux/device.h>
#include <linux/errno.h>
#include <linux/init.h>
#include <linux/io.h>
#include <linux/jiffies.h>
#include <linux/of_address.h>
#include <linux/of_irq.h>
-#include <linux/of_platform.h>
#include <linux/printk.h>
#include <linux/regmap.h>
#include <linux/smp.h>
@@ -32,7 +29,7 @@
#include <asm/mach-types.h>
#include <asm/smp_plat.h>
-#include "brcmstb.h"
+#include "headsmp-brcmstb.h"
enum {
ZONE_MAN_CLKEN_MASK = BIT(0),
@@ -58,6 +55,8 @@
static u32 cpu0_pwr_zone_ctrl_reg;
static u32 cpu_rst_cfg_reg;
static u32 hif_cont_reg;
+
+#ifdef CONFIG_HOTPLUG_CPU
static DEFINE_PER_CPU_ALIGNED(int, per_cpu_sw_state);
static int per_cpu_sw_state_rd(u32 cpu)
@@ -77,6 +76,9 @@
sync_cache_w(SHIFT_PERCPU_PTR(&per_cpu_sw_state, per_cpu_offset(cpu)));
dsb_sev();
}
+#else
+static inline void per_cpu_sw_state_wr(u32 cpu, int val) { }
+#endif
static void __iomem *pwr_ctrl_get_base(u32 cpu)
{
@@ -140,7 +142,7 @@
writel_relaxed(boot_addr, hif_cont_block + hif_cont_reg + 4 + reg_ofs);
}
-void brcmstb_cpu_boot(u32 cpu)
+static void brcmstb_cpu_boot(u32 cpu)
{
/* Mark this CPU as "up" */
per_cpu_sw_state_wr(cpu, 1);
@@ -155,7 +157,7 @@
cpu_rst_cfg_set(cpu, 0);
}
-void brcmstb_cpu_power_on(u32 cpu)
+static void brcmstb_cpu_power_on(u32 cpu)
{
/*
* The secondary cores power was cut, so we must go through
@@ -179,13 +181,15 @@
pwr_ctrl_set(cpu, ZONE_MAN_RESET_CNTL_MASK, -1);
}
-int brcmstb_cpu_get_power_state(u32 cpu)
+static int brcmstb_cpu_get_power_state(u32 cpu)
{
int tmp = pwr_ctrl_rd(cpu);
return (tmp & ZONE_RESET_STATE_MASK) ? 0 : 1;
}
-void __ref brcmstb_cpu_die(u32 cpu)
+#ifdef CONFIG_HOTPLUG_CPU
+
+static void __ref brcmstb_cpu_die(u32 cpu)
{
v7_exit_coherency_flush(all);
@@ -208,7 +212,7 @@
;
}
-int brcmstb_cpu_kill(u32 cpu)
+static int brcmstb_cpu_kill(u32 cpu)
{
/*
* Ordinarily, the hardware forbids power-down of CPU0 (which is good
@@ -247,6 +251,8 @@
return 1;
}
+#endif /* CONFIG_HOTPLUG_CPU */
+
static int __init setup_hifcpubiuctrl_regs(struct device_node *np)
{
int rc = 0;
@@ -326,7 +332,7 @@
return rc;
}
-void __init brcmstb_cpu_ctrl_setup(unsigned int max_cpus)
+static void __init brcmstb_cpu_ctrl_setup(unsigned int max_cpus)
{
int rc;
struct device_node *np;
@@ -347,3 +353,25 @@
if (rc)
return;
}
+
+static int brcmstb_boot_secondary(unsigned int cpu, struct task_struct *idle)
+{
+ /* Bring up power to the core if necessary */
+ if (brcmstb_cpu_get_power_state(cpu) == 0)
+ brcmstb_cpu_power_on(cpu);
+
+ brcmstb_cpu_boot(cpu);
+
+ return 0;
+}
+
+static struct smp_operations brcmstb_smp_ops __initdata = {
+ .smp_prepare_cpus = brcmstb_cpu_ctrl_setup,
+ .smp_boot_secondary = brcmstb_boot_secondary,
+#ifdef CONFIG_HOTPLUG_CPU
+ .cpu_kill = brcmstb_cpu_kill,
+ .cpu_die = brcmstb_cpu_die,
+#endif
+};
+
+CPU_METHOD_OF_DECLARE(brcmstb_smp, "brcm,brahma-b15", &brcmstb_smp_ops);
diff --git a/arch/arm/mm/Kconfig b/arch/arm/mm/Kconfig
index e9c290c..f4ab655 100644
--- a/arch/arm/mm/Kconfig
+++ b/arch/arm/mm/Kconfig
@@ -853,6 +853,14 @@
The outer cache has a outer_cache_fns.sync function pointer
that can be used to drain the write buffer of the outer cache.
+config CACHE_B15_RAC
+ bool "Enable the Broadcom Brahma-B15 read-ahead cache controller"
+ depends on ARCH_BRCMSTB
+ default y
+ help
+ This option enables the Broadcom Brahma-B15 read-ahead cache
+ controller. If disabled, the read-ahead cache remains off.
+
config CACHE_FEROCEON_L2
bool "Enable the Feroceon L2 cache controller"
depends on ARCH_KIRKWOOD || ARCH_MV78XX0
diff --git a/arch/arm/mm/Makefile b/arch/arm/mm/Makefile
index 7f39ce2..d66ff37 100644
--- a/arch/arm/mm/Makefile
+++ b/arch/arm/mm/Makefile
@@ -95,6 +95,7 @@
AFLAGS_proc-v6.o :=-Wa,-march=armv6
AFLAGS_proc-v7.o :=-Wa,-march=armv7-a
+obj-$(CONFIG_CACHE_B15_RAC) += cache-b15-rac.o
obj-$(CONFIG_CACHE_FEROCEON_L2) += cache-feroceon-l2.o
obj-$(CONFIG_CACHE_L2X0) += cache-l2x0.o
obj-$(CONFIG_CACHE_XSC3L2) += cache-xsc3l2.o
diff --git a/arch/arm/mm/cache-b15-rac.c b/arch/arm/mm/cache-b15-rac.c
new file mode 100644
index 0000000..e43d688
--- /dev/null
+++ b/arch/arm/mm/cache-b15-rac.c
@@ -0,0 +1,368 @@
+/*
+ * Broadcom Brahma-B15 CPU read-ahead cache management functions
+ *
+ * Copyright (C) 2015, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/err.h>
+#include <linux/spinlock.h>
+#include <linux/io.h>
+#include <linux/bitops.h>
+#include <linux/of_address.h>
+#include <linux/notifier.h>
+#include <linux/cpu.h>
+#include <linux/syscore_ops.h>
+#include <linux/reboot.h>
+
+#include <asm/cacheflush.h>
+#include <asm/hardware/cache-b15-rac.h>
+
+extern void v7_flush_kern_cache_all(void);
+extern void v7_flush_kern_cache_louis(void);
+extern void v7_flush_icache_all(void);
+
+/* RAC register offsets, relative to the HIF_CPU_BIUCTRL register base */
+#define RAC_CONFIG0_REG (0x78)
+#define RACENPREF_MASK (0x3)
+#define RACPREFINST_SHIFT (0)
+#define RACENINST_SHIFT (2)
+#define RACPREFDATA_SHIFT (4)
+#define RACENDATA_SHIFT (6)
+#define RAC_CPU_SHIFT (8)
+#define RACCFG_MASK (0xff)
+#define RAC_CONFIG1_REG (0x7c)
+#define RAC_FLUSH_REG (0x80)
+#define FLUSH_RAC (1 << 0)
+
+/* Bitmask to enable instruction and data prefetching with a 256-bytes stride */
+#define RAC_DATA_INST_EN_MASK (1 << RACPREFINST_SHIFT | \
+ RACENPREF_MASK << RACENINST_SHIFT | \
+ 1 << RACPREFDATA_SHIFT | \
+ RACENPREF_MASK << RACENDATA_SHIFT)
+
+#define RAC_ENABLED (1 << 0)
+/* Special state where we want to bypass the spinlock and call directly
+ * into the v7 cache maintenance operations during suspend/resume
+ */
+#define RAC_SUSPENDED (1 << 1)
+
+static void __iomem *b15_rac_base;
+static DEFINE_SPINLOCK(rac_lock);
+static u32 rac_config0_reg;
+
+/* Initialization flag to avoid checking for b15_rac_base, and to prevent
+ * multi-platform kernels from crashing here as well.
+ */
+static unsigned long b15_rac_flags;
+
+static inline u32 __b15_rac_disable(void)
+{
+ u32 val = __raw_readl(b15_rac_base + RAC_CONFIG0_REG);
+ __raw_writel(0, b15_rac_base + RAC_CONFIG0_REG);
+ dmb();
+ return val;
+}
+
+static inline void __b15_rac_flush(void)
+{
+ u32 reg;
+
+ __raw_writel(FLUSH_RAC, b15_rac_base + RAC_FLUSH_REG);
+ do {
+ /* This dmb() is required to force the Bus Interface Unit
+ * to clean oustanding writes, and forces an idle cycle
+ * to be inserted.
+ */
+ dmb();
+ reg = __raw_readl(b15_rac_base + RAC_FLUSH_REG);
+ } while (reg & RAC_FLUSH_REG);
+}
+
+static inline u32 b15_rac_disable_and_flush(void)
+{
+ u32 reg;
+
+ reg = __b15_rac_disable();
+ __b15_rac_flush();
+ return reg;
+}
+
+static inline void __b15_rac_enable(u32 val)
+{
+ __raw_writel(val, b15_rac_base + RAC_CONFIG0_REG);
+ /* dsb() is required here to be consistent with __flush_icache_all() */
+ dsb();
+}
+
+#define BUILD_RAC_CACHE_OP(name, bar) \
+void b15_flush_##name(void) \
+{ \
+ unsigned int do_flush; \
+ u32 val = 0; \
+ \
+ if (test_bit(RAC_SUSPENDED, &b15_rac_flags)) { \
+ v7_flush_##name(); \
+ bar; \
+ return; \
+ } \
+ \
+ spin_lock(&rac_lock); \
+ do_flush = test_bit(RAC_ENABLED, &b15_rac_flags); \
+ if (do_flush) \
+ val = b15_rac_disable_and_flush(); \
+ v7_flush_##name(); \
+ if (!do_flush) \
+ bar; \
+ else \
+ __b15_rac_enable(val); \
+ spin_unlock(&rac_lock); \
+}
+
+#define nobarrier
+
+/* The readahead cache present in the Brahma-B15 CPU is a special piece of
+ * hardware after the integrated L2 cache of the B15 CPU complex whose purpose
+ * is to prefetch instruction and/or data with a line size of either 64 bytes
+ * or 256 bytes. The rationale is that the data-bus of the CPU interface is
+ * optimized for 256-bytes transactions, and enabling the readahead cache
+ * provides a significant performance boost we want it enabled (typically
+ * twice the performance for a memcpy benchmark application).
+ *
+ * The readahead cache is transparent for Modified Virtual Addresses
+ * cache maintenance operations: ICIMVAU, DCIMVAC, DCCMVAC, DCCMVAU and
+ * DCCIMVAC.
+ *
+ * It is however not transparent for the following cache maintenance
+ * operations: DCISW, DCCSW, DCCISW, ICIALLUIS and ICIALLU which is precisely
+ * what we are patching here with our BUILD_RAC_CACHE_OP here.
+ */
+
+BUILD_RAC_CACHE_OP(kern_cache_all, nobarrier);
+BUILD_RAC_CACHE_OP(kern_cache_louis, nobarrier);
+BUILD_RAC_CACHE_OP(icache_all, dsb());
+
+static void b15_rac_enable(void)
+{
+ unsigned int cpu;
+ u32 enable = 0;
+
+ for_each_possible_cpu(cpu)
+ enable |= (RAC_DATA_INST_EN_MASK << (cpu * RAC_CPU_SHIFT));
+
+ b15_rac_disable_and_flush();
+ __b15_rac_enable(enable);
+}
+
+static int b15_rac_reboot_notifier(struct notifier_block *nb,
+ unsigned long action,
+ void *data)
+{
+ /* During kexec, we are not yet migrated on the boot CPU, so we need to
+ * make sure we are SMP safe here. Once the RAC is disabled, flag it as
+ * suspended such that the hotplug notifier returns early.
+ */
+ if (action == SYS_RESTART) {
+ spin_lock(&rac_lock);
+ b15_rac_disable_and_flush();
+ clear_bit(RAC_ENABLED, &b15_rac_flags);
+ set_bit(RAC_SUSPENDED, &b15_rac_flags);
+ spin_unlock(&rac_lock);
+ }
+
+ return NOTIFY_DONE;
+}
+
+static struct notifier_block b15_rac_reboot_nb = {
+ .notifier_call = b15_rac_reboot_notifier,
+};
+
+#ifdef CONFIG_HOTPLUG_CPU
+static void b15_rac_hotplug_start(void)
+{
+ /* Indicate that we are starting a hotplug procedure */
+ clear_bit(RAC_ENABLED, &b15_rac_flags);
+
+ /* Disable the readahead cache and save its value to a global */
+ rac_config0_reg = b15_rac_disable_and_flush();
+}
+
+static void b15_rac_hotplug_end(void)
+{
+ /* And enable it */
+ __b15_rac_enable(rac_config0_reg);
+ set_bit(RAC_ENABLED, &b15_rac_flags);
+}
+
+/* The CPU hotplug case is the most interesting one, we basically need to make
+ * sure that the RAC is disabled for the entire system prior to having a CPU
+ * die, in particular prior to this dying CPU having exited the coherency
+ * domain.
+ *
+ * Once this CPU is marked dead, we can safely re-enable the RAC for the
+ * remaining CPUs in the system which are still online.
+ *
+ * Offlining a CPU is the problematic case, onlining a CPU is not much of an
+ * issue since the CPU and its cache-level hierarchy will start filling with
+ * the RAC disabled, so L1 and L2 only.
+ *
+ * In this function, we should NOT have to verify any unsafe setting/condition
+ * b15_rac_base:
+ *
+ * It is protected by the RAC_ENABLED flag which is cleared by default, and
+ * being cleared when initial procedure is done. b15_rac_base had been set at
+ * that time.
+ *
+ * RAC_ENABLED:
+ * There is a small timing windows, in b15_rac_init(), between
+ * register_cpu_notifier(&b15_rac_cpu_nb);
+ * ...
+ * set RAC_ENABLED
+ * However, there is no hotplug activity based on the Linux booting procedure.
+ *
+ * Regarding the notification actions, we will receive CPU_DOWN_PREPARE,
+ * CPU_DOWN_FAILED, CPU_DYING, CPU_DEAD, and CPU_POST_DEAD notification (see
+ * _cpu_down() for detail).
+ *
+ * Since we have to disable RAC for all cores, we keep RAC on as long as as
+ * possible (disable it as late as possible) to gain the cache benefit.
+ *
+ * Thus, CPU_DYING/CPU_DEAD pair are chosen.
+ *
+ * We are choosing not do disable the RAC on a per-CPU basis, here, if we did
+ * we would want to consider disabling it as early as possible to benefit the
+ * other active CPUs.
+ */
+static int b15_rac_cpu_notify(struct notifier_block *self,
+ unsigned long action, void *hcpu)
+{
+ action &= ~CPU_TASKS_FROZEN;
+
+ if (action != CPU_DYING && action != CPU_DOWN_FAILED &&
+ action != CPU_DEAD)
+ return NOTIFY_OK;
+
+ /* During kexec/reboot, the RAC is disabled via the reboot notifier
+ * return early here.
+ */
+ if (test_bit(RAC_SUSPENDED, &b15_rac_flags))
+ return NOTIFY_DONE;
+
+ spin_lock(&rac_lock);
+ switch (action) {
+ /* called on the dying CPU, exactly what we want */
+ case CPU_DYING:
+ b15_rac_hotplug_start();
+ break;
+
+ /* called on a non-dying CPU, what we want too */
+ case CPU_DOWN_FAILED:
+ case CPU_DEAD:
+ b15_rac_hotplug_end();
+ break;
+ }
+ spin_unlock(&rac_lock);
+
+ return NOTIFY_OK;
+}
+
+static struct notifier_block b15_rac_cpu_nb = {
+ .notifier_call = b15_rac_cpu_notify,
+};
+#endif /* CONFIG_HOTPLUG_CPU */
+
+#ifdef CONFIG_PM_SLEEP
+static int b15_rac_suspend(void)
+{
+ /* Suspend the read-ahead cache oeprations, forcing our cache
+ * implementation to fallback to the regular ARMv7 calls.
+ *
+ * We are guaranteed to be running on the boot CPU at this point and
+ * with every other CPU quiesced, so setting RAC_SUSPENDED is not racy
+ * here.
+ */
+ rac_config0_reg = b15_rac_disable_and_flush();
+ set_bit(RAC_SUSPENDED, &b15_rac_flags);
+
+ return 0;
+}
+
+static void b15_rac_resume(void)
+{
+ /* Coming out of a S3 suspend/resume cycle, the read-ahead cache
+ * register RAC_CONFIG0_REG will be restored to its default value, make
+ * sure we re-enable it and set the enable flag, we are also guaranteed
+ * to run on the boot CPU, so not racy again.
+ */
+ __b15_rac_enable(rac_config0_reg);
+ clear_bit(RAC_SUSPENDED, &b15_rac_flags);
+}
+
+static struct syscore_ops b15_rac_syscore_ops = {
+ .suspend = b15_rac_suspend,
+ .resume = b15_rac_resume,
+};
+#endif
+
+static int __init b15_rac_init(void)
+{
+ struct device_node *dn;
+ int ret = 0, cpu;
+ u32 reg, en_mask = 0;
+
+ dn = of_find_compatible_node(NULL, NULL, "brcm,brcmstb-cpu-biu-ctrl");
+ if (!dn)
+ return -ENODEV;
+
+ if (WARN(num_possible_cpus() > 4, "RAC only supports 4 CPUs\n"))
+ goto out;
+
+ b15_rac_base = of_iomap(dn, 0);
+ if (!b15_rac_base) {
+ pr_err("failed to remap BIU control base\n");
+ ret = -ENOMEM;
+ goto out;
+ }
+
+ ret = register_reboot_notifier(&b15_rac_reboot_nb);
+ if (ret) {
+ pr_err("failed to register reboot notifier\n");
+ iounmap(b15_rac_base);
+ goto out;
+ }
+
+#ifdef CONFIG_HOTPLUG_CPU
+ ret = register_cpu_notifier(&b15_rac_cpu_nb);
+ if (ret) {
+ pr_err("failed to register notifier block\n");
+ iounmap(b15_rac_base);
+ unregister_reboot_notifier(&b15_rac_reboot_nb);
+ goto out;
+ }
+#endif
+
+#ifdef CONFIG_PM_SLEEP
+ register_syscore_ops(&b15_rac_syscore_ops);
+#endif
+
+ spin_lock(&rac_lock);
+ reg = __raw_readl(b15_rac_base + RAC_CONFIG0_REG);
+ for_each_possible_cpu(cpu)
+ en_mask |= ((1 << RACPREFDATA_SHIFT) << (cpu * RAC_CPU_SHIFT));
+ WARN(reg & en_mask, "Read-ahead cache not previously disabled\n");
+
+ b15_rac_enable();
+ set_bit(RAC_ENABLED, &b15_rac_flags);
+ spin_unlock(&rac_lock);
+
+ pr_info("Broadcom Brahma-B15 readahead cache at: 0x%p\n",
+ b15_rac_base + RAC_CONFIG0_REG);
+
+out:
+ of_node_put(dn);
+ return ret;
+}
+arch_initcall(b15_rac_init);
diff --git a/arch/arm/mm/cache-v7.S b/arch/arm/mm/cache-v7.S
index 4978bde..c5e59e5 100644
--- a/arch/arm/mm/cache-v7.S
+++ b/arch/arm/mm/cache-v7.S
@@ -15,6 +15,7 @@
#include <asm/assembler.h>
#include <asm/errno.h>
#include <asm/unwind.h>
+#include <asm/hardware/cache-b15-rac.h>
#include "proc-macros.S"
@@ -369,7 +370,6 @@
cmp r0, r1
blo 1b
dsb
- issue_brcmstb_mega_barrier
mov pc, lr
ENDPROC(v7_dma_inv_range)
@@ -392,7 +392,6 @@
cmp r0, r1
blo 1b
dsb
- issue_brcmstb_mega_barrier
mov pc, lr
ENDPROC(v7_dma_clean_range)
@@ -415,7 +414,6 @@
cmp r0, r1
blo 1b
dsb
- issue_brcmstb_mega_barrier
mov pc, lr
ENDPROC(v7_dma_flush_range)
@@ -449,3 +447,23 @@
@ define struct cpu_cache_fns (see <asm/cacheflush.h> and proc-macros.S)
define_cache_functions v7
+
+ /* The Broadcom Brahma-B15 read-ahead cache requires some modifications
+ * to the v7_cache_fns, we only override the ones we need
+ */
+#ifndef CONFIG_CACHE_B15_RAC
+ globl_equ b15_flush_icache_all, v7_flush_icache_all
+ globl_equ b15_flush_kern_cache_all, v7_flush_kern_cache_all
+ globl_equ b15_flush_kern_cache_louis, v7_flush_kern_cache_louis
+#endif
+ globl_equ b15_flush_user_cache_all, v7_flush_user_cache_all
+ globl_equ b15_flush_user_cache_range, v7_flush_user_cache_range
+ globl_equ b15_coherent_kern_range, v7_coherent_kern_range
+ globl_equ b15_coherent_user_range, v7_coherent_user_range
+ globl_equ b15_flush_kern_dcache_area, v7_flush_kern_dcache_area
+
+ globl_equ b15_dma_map_area, v7_dma_map_area
+ globl_equ b15_dma_unmap_area, v7_dma_unmap_area
+ globl_equ b15_dma_flush_range, v7_dma_flush_range
+
+ define_cache_functions b15
diff --git a/arch/arm/mm/dma-mapping.c b/arch/arm/mm/dma-mapping.c
index 11b3914..90160c3 100644
--- a/arch/arm/mm/dma-mapping.c
+++ b/arch/arm/mm/dma-mapping.c
@@ -26,6 +26,7 @@
#include <linux/io.h>
#include <linux/vmalloc.h>
#include <linux/sizes.h>
+#include <linux/cma.h>
#include <asm/memory.h>
#include <asm/highmem.h>
@@ -393,7 +394,7 @@
if (!pages)
goto no_pages;
- if (IS_ENABLED(CONFIG_DMA_CMA))
+ if (dev_get_cma_area(NULL))
ptr = __alloc_from_contiguous(NULL, pool->size, prot, &page,
atomic_pool_init);
else
@@ -704,7 +705,7 @@
addr = __alloc_simple_buffer(dev, size, gfp, &page);
else if (!(gfp & __GFP_WAIT))
addr = __alloc_from_pool(size, &page);
- else if (!IS_ENABLED(CONFIG_DMA_CMA))
+ else if (!dev_get_cma_area(dev))
addr = __alloc_remap_buffer(dev, size, gfp, prot, &page, caller);
else
addr = __alloc_from_contiguous(dev, size, prot, &page, caller);
@@ -793,7 +794,7 @@
__dma_free_buffer(page, size);
} else if (__free_from_pool(cpu_addr, size)) {
return;
- } else if (!IS_ENABLED(CONFIG_DMA_CMA)) {
+ } else if (!dev_get_cma_area(dev)) {
__dma_free_remap(cpu_addr, size);
__dma_free_buffer(page, size);
} else {
diff --git a/arch/arm/mm/init.c b/arch/arm/mm/init.c
index 2a77ba8..626fc8b 100644
--- a/arch/arm/mm/init.c
+++ b/arch/arm/mm/init.c
@@ -22,6 +22,7 @@
#include <linux/memblock.h>
#include <linux/dma-contiguous.h>
#include <linux/sizes.h>
+#include <linux/cma.h>
#include <asm/mach-types.h>
#include <asm/memblock.h>
@@ -122,6 +123,9 @@
printk("%d pages of RAM\n", total);
printk("%d free pages\n", free);
printk("%d reserved pages\n", reserved);
+#ifdef CONFIG_CMA
+ printk("%lu cma reserved pages\n", totalcma_pages);
+#endif
printk("%d slab pages\n", slab);
printk("%d pages shared\n", shared);
printk("%d pages swap cached\n", cached);
@@ -319,11 +323,24 @@
arm_mm_memblock_reserve();
arm_dt_memblock_reserve();
+#ifdef CONFIG_BRCMSTB
+ /*
+ * Moved before platform reserve so that we can find all the
+ * non-cma, non-bmem reserved areas without implementing interval
+ * subtraction
+ */
+ early_init_fdt_scan_reserved_mem();
+
+ /* reserve any platform specific memblock areas */
+ if (mdesc->reserve)
+ mdesc->reserve();
+#else
/* reserve any platform specific memblock areas */
if (mdesc->reserve)
mdesc->reserve();
early_init_fdt_scan_reserved_mem();
+#endif
/*
* reserve memory for DMA contigouos allocations,
diff --git a/arch/arm/mm/mmu.c b/arch/arm/mm/mmu.c
index f15c22e..14428d2 100644
--- a/arch/arm/mm/mmu.c
+++ b/arch/arm/mm/mmu.c
@@ -1028,10 +1028,15 @@
static void * __initdata vmalloc_min =
(void *)(VMALLOC_END - (240 << 20) - VMALLOC_OFFSET);
+static bool __initdata brcmstb_did_override_vmalloc;
+
/*
* vmalloc=size forces the vmalloc area to be exactly 'size'
* bytes. This can be used to increase (or decrease) the vmalloc
* area - the default is 240m.
+ *
+ * NOTE: different default for BRCMSTB with >= 1GiB RAM, see
+ * brcmstb_maybe_increase_vmalloc() below.
*/
static int __init early_vmalloc(char *arg)
{
@@ -1052,17 +1057,35 @@
}
vmalloc_min = (void *)(VMALLOC_END - vmalloc_reserve);
+ brcmstb_did_override_vmalloc = true;
return 0;
}
early_param("vmalloc", early_vmalloc);
+static void __init brcmstb_maybe_increase_vmalloc(void)
+{
+#ifdef CONFIG_BRCMSTB
+ if (brcmstb_did_override_vmalloc)
+ return;
+ if (meminfo.bank[0].size >= SZ_1G || meminfo.nr_banks > 1) {
+ vmalloc_min = (void *)(VMALLOC_END - (744 << 20) -
+ VMALLOC_OFFSET);
+ }
+#else
+ return;
+#endif
+}
+
phys_addr_t arm_lowmem_limit __initdata = 0;
void __init sanity_check_meminfo(void)
{
phys_addr_t memblock_limit = 0;
int i, j, highmem = 0;
- phys_addr_t vmalloc_limit = __pa(vmalloc_min - 1) + 1;
+ phys_addr_t vmalloc_limit;
+
+ brcmstb_maybe_increase_vmalloc();
+ vmalloc_limit = __pa(vmalloc_min - 1) + 1;
for (i = 0, j = 0; i < meminfo.nr_banks; i++) {
struct membank *bank = &meminfo.bank[j];
diff --git a/arch/arm/mm/proc-macros.S b/arch/arm/mm/proc-macros.S
index b9e35f9..ee1d805 100644
--- a/arch/arm/mm/proc-macros.S
+++ b/arch/arm/mm/proc-macros.S
@@ -6,9 +6,6 @@
*/
#include <asm/asm-offsets.h>
#include <asm/thread_info.h>
-#ifdef CONFIG_BRCMSTB
-#include <linux/brcmstb/brcmstb.h>
-#endif
/*
* vma_vm_mm - get mm pointer from vma pointer (vma->vm_mm)
@@ -334,11 +331,3 @@
.globl \x
.equ \x, \y
.endm
-
-.macro issue_brcmstb_mega_barrier
-#ifdef CONFIG_BRCMSTB_USE_MEGA_BARRIER
- stmdb sp!, {r0, lr}
- blx brcmstb_mega_barrier
- ldmia sp!, {r0, lr}
-#endif
-.endm
diff --git a/arch/arm/mm/proc-v7-2level.S b/arch/arm/mm/proc-v7-2level.S
index 1db6721..f1f3cd2 100644
--- a/arch/arm/mm/proc-v7-2level.S
+++ b/arch/arm/mm/proc-v7-2level.S
@@ -123,15 +123,8 @@
* WRITEBACK 011 10 11 11
* reserved 110
* WRITEALLOC 111 10 01 01
-#ifdef CONFIG_BRCMSTB_USE_MEGA_BARRIER
- * Have to mark all device memory as STRONGLY ORDERED
- * to support workaround for H/W bug.
- * DEV_SHARED 100 00
- * DEV_NONSHARED 100 00
-#else
* DEV_SHARED 100 01
* DEV_NONSHARED 100 01
-#endif
* DEV_WC 001 10
* DEV_CACHED 011 10
*
@@ -143,11 +136,7 @@
* NS1 = PRRR[19] = 1 - normal shareable property
* NOS = PRRR[24+n] = 1 - not outer shareable
*/
-#ifdef CONFIG_BRCMSTB_USE_MEGA_BARRIER
-.equ PRRR, 0xff0a80a8
-#else
.equ PRRR, 0xff0a81a8
-#endif
.equ NMRR, 0x40e040e0
/*
diff --git a/arch/arm/mm/proc-v7.S b/arch/arm/mm/proc-v7.S
index 467fe51..2a6e3e4 100644
--- a/arch/arm/mm/proc-v7.S
+++ b/arch/arm/mm/proc-v7.S
@@ -408,7 +408,7 @@
/*
* Standard v7 proc info content
*/
-.macro __v7_proc initfunc, mm_mmuflags = 0, io_mmuflags = 0, hwcaps = 0, proc_fns = v7_processor_functions
+.macro __v7_proc initfunc, mm_mmuflags = 0, io_mmuflags = 0, hwcaps = 0, proc_fns = v7_processor_functions, cache_fns = v7_cache_fns
ALT_SMP(.long PMD_TYPE_SECT | PMD_SECT_AP_WRITE | PMD_SECT_AP_READ | \
PMD_SECT_AF | PMD_FLAGS_SMP | \mm_mmuflags)
ALT_UP(.long PMD_TYPE_SECT | PMD_SECT_AP_WRITE | PMD_SECT_AP_READ | \
@@ -424,7 +424,7 @@
.long \proc_fns
.long v7wbi_tlb_fns
.long v6_user_fns
- .long v7_cache_fns
+ .long \cache_fns
.endm
#ifndef CONFIG_ARM_LPAE
@@ -499,7 +499,7 @@
__v7_b15mp_proc_info:
.long 0x420f00f0
.long 0xff0ffff0
- __v7_proc __v7_b15mp_setup
+ __v7_proc __v7_b15mp_setup, cache_fns = b15_cache_fns
.size __v7_b15mp_proc_info, . - __v7_b15mp_proc_info
/*
diff --git a/arch/powerpc/kvm/book3s_hv_builtin.c b/arch/powerpc/kvm/book3s_hv_builtin.c
index 8cd0dae..7d44fb0 100644
--- a/arch/powerpc/kvm/book3s_hv_builtin.c
+++ b/arch/powerpc/kvm/book3s_hv_builtin.c
@@ -178,6 +178,7 @@
align_size = HPT_ALIGN_PAGES << PAGE_SHIFT;
align_size = max(kvm_rma_pages << PAGE_SHIFT, align_size);
- kvm_cma_declare_contiguous(selected_size, align_size);
+ cma_declare_contiguous(0, selected_size, 0, align_size,
+ KVM_CMA_CHUNK_ORDER - PAGE_SHIFT, false, &kvm_cma);
}
}
diff --git a/arch/x86/include/asm/bug.h b/arch/x86/include/asm/bug.h
index 2f03ff0..ba38ebb 100644
--- a/arch/x86/include/asm/bug.h
+++ b/arch/x86/include/asm/bug.h
@@ -1,7 +1,6 @@
#ifndef _ASM_X86_BUG_H
#define _ASM_X86_BUG_H
-#ifdef CONFIG_BUG
#define HAVE_ARCH_BUG
#ifdef CONFIG_DEBUG_BUGVERBOSE
@@ -33,8 +32,6 @@
} while (0)
#endif
-#endif /* !CONFIG_BUG */
-
#include <asm-generic/bug.h>
#endif /* _ASM_X86_BUG_H */
diff --git a/arch/x86/kernel/setup.c b/arch/x86/kernel/setup.c
index ce72964..5df9657 100644
--- a/arch/x86/kernel/setup.c
+++ b/arch/x86/kernel/setup.c
@@ -1120,7 +1120,7 @@
setup_real_mode();
memblock_set_current_limit(get_max_mapped());
- dma_contiguous_reserve(0);
+ dma_contiguous_reserve(max_pfn_mapped << PAGE_SHIFT);
/*
* NOTE: On x86-32, only from this point on, fixmaps are ready for use.
diff --git a/drivers/Kconfig b/drivers/Kconfig
index b3138fb..37f955f 100644
--- a/drivers/Kconfig
+++ b/drivers/Kconfig
@@ -130,6 +130,8 @@
source "drivers/platform/Kconfig"
+source "drivers/soc/Kconfig"
+
source "drivers/clk/Kconfig"
source "drivers/hwspinlock/Kconfig"
diff --git a/drivers/Makefile b/drivers/Makefile
index 8e3b8b0..171b789 100644
--- a/drivers/Makefile
+++ b/drivers/Makefile
@@ -33,6 +33,9 @@
# really early.
obj-$(CONFIG_DMADEVICES) += dma/
+# SOC specific infrastructure drivers.
+obj-y += soc/
+
obj-$(CONFIG_VIRTIO) += virtio/
obj-$(CONFIG_XEN) += xen/
diff --git a/drivers/ata/sata_brcmstb.c b/drivers/ata/sata_brcmstb.c
index 60bafc8..3eda314 100644
--- a/drivers/ata/sata_brcmstb.c
+++ b/drivers/ata/sata_brcmstb.c
@@ -163,25 +163,6 @@
writel((DATA_ENDIAN << 4) | (DATA_ENDIAN << 2) | (MMIO_ENDIAN << 0),
top_regs + SATA_TOP_CTRL_BUS_CTRL);
- if (brcm_pdata->quirks & SATA_BRCM_QK_NONCQ) {
- /* Temporarily allow writing to AHCI RO registers */
- u32 reg = readl(top_regs + SATA_TOP_CTRL_BUS_CTRL);
- reg |= SATA_TOP_CTRL_BUS_CTRL_OVERRIDE_HWINIT;
- writel(reg, top_regs + SATA_TOP_CTRL_BUS_CTRL);
-
- /* Clear out the NCQ bit so the AHCI driver will not issue
- * FPDMA/NCQ commands.
- */
- reg = readl(ahci_regs + HOST_CAP);
- reg &= ~HOST_CAP_NCQ;
- writel(reg, ahci_regs + HOST_CAP);
-
- /* Re-enable AHCI RO property */
- reg = readl(top_regs + SATA_TOP_CTRL_BUS_CTRL);
- reg &= ~SATA_TOP_CTRL_BUS_CTRL_OVERRIDE_HWINIT;
- writel(reg, top_regs + SATA_TOP_CTRL_BUS_CTRL);
- }
-
done:
if (top_regs)
iounmap(top_regs);
@@ -349,20 +330,6 @@
return status;
}
-static void brcm_ahci_setup_quirks(struct platform_device *pdev)
-{
- struct sata_brcm_pdata *brcm_pdata = pdev->dev.platform_data;
-
- brcm_pdata->quirks = 0;
-
- if (of_machine_is_compatible("brcm,bcm7145a0")) {
- brcm_pdata->quirks |= SATA_BRCM_QK_ALT_RST;
- brcm_pdata->quirks |= SATA_BRCM_QK_NONCQ;
- } else if (of_machine_is_compatible("brcm,bcm7439a0")) {
- brcm_pdata->quirks |= SATA_BRCM_QK_ALT_RST;
- }
-}
-
static int setup_ahci_pdata(struct platform_device *pdev,
struct ahci_platform_data *ahci_pd)
{
@@ -410,9 +377,6 @@
status = brcm_ahci_parse_dt_node(pdev);
if (status)
goto err_cleanup;
-
- brcm_ahci_setup_quirks(pdev);
-
/*
* Configure the platform AHCI device
*/
diff --git a/drivers/ata/sata_brcmstb.h b/drivers/ata/sata_brcmstb.h
index b11e557..09c3534 100644
--- a/drivers/ata/sata_brcmstb.h
+++ b/drivers/ata/sata_brcmstb.h
@@ -80,12 +80,6 @@
TXPMD_REG_BANK_LEGACY = 0x1a0,
};
-enum sata_brcm_quirks {
- SATA_BRCM_QK_INIT_PHY = BIT(0),
- SATA_BRCM_QK_ALT_RST = BIT(1),
- SATA_BRCM_QK_NONCQ = BIT(2),
-};
-
/**
* struct pdev_map - Doubly-linked list used to associate a struct device
* its associated platform devices.
diff --git a/drivers/ata/sata_brcmstb_phy.c b/drivers/ata/sata_brcmstb_phy.c
index 3ae8c4d..7d68c52 100644
--- a/drivers/ata/sata_brcmstb_phy.c
+++ b/drivers/ata/sata_brcmstb_phy.c
@@ -168,19 +168,6 @@
};
void __iomem *top_ctrl;
- if (pdata->quirks & SATA_BRCM_QK_ALT_RST) {
-#if (defined(CONFIG_BRCMSTB) && \
-defined(BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_sata_phy_disable_MASK))
- /*
- * This version of the chip placed the reset bit in a non-SATA
- * IP register.
- */
- BDEV_WR_F(SUN_TOP_CTRL_GENERAL_CTRL_0, sata_phy_disable, 0);
-#else
- pr_err("Unable to handle quirk SATA_BRCM_QK_ALT_RST\n");
-#endif
- }
-
top_ctrl = ioremap(pdata->top_ctrl_base_addr, SATA_TOP_CTRL_REG_LENGTH);
if (!top_ctrl) {
pr_err("failed to ioremap SATA top ctrl regs\n");
@@ -252,28 +239,9 @@
goto err;
}
- if (pdata->phy_generation == 0x2800) {
+ if (pdata->phy_generation == 0x2800)
cfg_op = &cfg_op_tbl[SATA_PHY_MDIO_28NM];
-
- if (pdata->quirks & SATA_BRCM_QK_INIT_PHY) {
- /* The 28nm SATA PHY has incorrect PLL settings upon
- * chip reset.
- * The workaround suggested by the H/W team requires
- * initialization of the PLL registers in order to force
- * calibration.
- *
- * For more information, refer to: HWxxxx
- */
- const u32 PLL_SM_CTRL_0_DFLT = 0x3089;
-
- sata_mdio_wr_28nm(base, port, PLL_REG_BANK_0,
- PLL_REG_BANK_0_PLLCONTROL_0,
- 0x00000000, PLL_SM_CTRL_0_DFLT);
- sata_mdio_wr_28nm(base, port, PLL_REG_BANK_0,
- PLL_REG_BANK_0_PLLCONTROL_0,
- 0xfffffffe, 0x0);
- }
- } else
+ else
cfg_op = &cfg_op_tbl[SATA_PHY_MDIO_LEGACY];
if (enable) {
diff --git a/drivers/base/Kconfig b/drivers/base/Kconfig
index 0b4aaeb..37cfb33 100644
--- a/drivers/base/Kconfig
+++ b/drivers/base/Kconfig
@@ -208,6 +208,9 @@
to allocate big physically-contiguous blocks of memory for use with
hardware components that do not support I/O map nor scatter-gather.
+ You can disable CMA by specifying "cma=0" on the kernel's command
+ line.
+
For more information see <include/linux/dma-contiguous.h>.
If unsure, say "n".
@@ -266,16 +269,6 @@
If unsure, leave the default value "8".
-config CMA_AREAS
- int "Maximum count of the CMA device-private areas"
- default 7
- help
- CMA allows to create CMA areas for particular devices. This parameter
- sets the maximum number of such device private CMA areas in the
- system.
-
- If unsure, leave the default value "7".
-
endif
endmenu
diff --git a/drivers/base/dma-contiguous.c b/drivers/base/dma-contiguous.c
index 53a7c7c..473ff48 100644
--- a/drivers/base/dma-contiguous.c
+++ b/drivers/base/dma-contiguous.c
@@ -24,16 +24,9 @@
#include <linux/memblock.h>
#include <linux/err.h>
-#include <linux/mm.h>
-#include <linux/mutex.h>
-#include <linux/page-isolation.h>
#include <linux/sizes.h>
-#include <linux/slab.h>
-#include <linux/swap.h>
-#include <linux/mm_types.h>
#include <linux/dma-contiguous.h>
-
-struct cma *dma_contiguous_default_area;
+#include <linux/cma.h>
#ifdef CONFIG_CMA_SIZE_MBYTES
#define CMA_SIZE_MBYTES CONFIG_CMA_SIZE_MBYTES
@@ -41,6 +34,8 @@
#define CMA_SIZE_MBYTES 0
#endif
+struct cma *dma_contiguous_default_area;
+
/*
* Default global CMA area size can be defined in kernel's .config.
* This is useful mainly for distro maintainers to create a kernel
@@ -53,11 +48,22 @@
*/
static const phys_addr_t size_bytes = CMA_SIZE_MBYTES * SZ_1M;
static phys_addr_t size_cmdline = -1;
+static phys_addr_t base_cmdline;
+static phys_addr_t limit_cmdline;
static int __init early_cma(char *p)
{
pr_debug("%s(%s)\n", __func__, p);
size_cmdline = memparse(p, &p);
+ if (*p != '@')
+ return 0;
+ base_cmdline = memparse(p + 1, &p);
+ if (*p != '-') {
+ limit_cmdline = base_cmdline + size_cmdline;
+ return 0;
+ }
+ limit_cmdline = memparse(p + 1, &p);
+
return 0;
}
early_param("cma", early_cma);
@@ -101,11 +107,18 @@
void __init dma_contiguous_reserve(phys_addr_t limit)
{
phys_addr_t selected_size = 0;
+ phys_addr_t selected_base = 0;
+ phys_addr_t selected_limit = limit;
+ bool fixed = false;
pr_debug("%s(limit %08lx)\n", __func__, (unsigned long)limit);
if (size_cmdline != -1) {
selected_size = size_cmdline;
+ selected_base = base_cmdline;
+ selected_limit = min_not_zero(limit_cmdline, limit);
+ if (base_cmdline + size_cmdline == limit_cmdline)
+ fixed = true;
} else {
#ifdef CONFIG_CMA_SIZE_SEL_MBYTES
selected_size = size_bytes;
@@ -122,147 +135,45 @@
pr_debug("%s: reserving %ld MiB for global area\n", __func__,
(unsigned long)selected_size / SZ_1M);
- dma_contiguous_reserve_area(selected_size, 0, limit,
- &dma_contiguous_default_area);
+ dma_contiguous_reserve_area(selected_size, selected_base,
+ selected_limit,
+ &dma_contiguous_default_area,
+ fixed);
}
-};
-
-static DEFINE_MUTEX(cma_mutex);
-
-static int __init cma_activate_area(struct cma *cma)
-{
- int bitmap_size = BITS_TO_LONGS(cma->count) * sizeof(long);
- unsigned long base_pfn = cma->base_pfn, pfn = base_pfn;
- unsigned i = cma->count >> pageblock_order;
- struct zone *zone;
-
- cma->bitmap = kzalloc(bitmap_size, GFP_KERNEL);
-
- if (!cma->bitmap)
- return -ENOMEM;
-
- WARN_ON_ONCE(!pfn_valid(pfn));
- zone = page_zone(pfn_to_page(pfn));
-
- do {
- unsigned j;
- base_pfn = pfn;
- for (j = pageblock_nr_pages; j; --j, pfn++) {
- WARN_ON_ONCE(!pfn_valid(pfn));
- /*
- * alloc_contig_range requires the pfn range
- * specified to be in the same zone. Make this
- * simple by forcing the entire CMA resv range
- * to be in the same zone.
- */
- if (page_zone(pfn_to_page(pfn)) != zone)
- goto err;
- }
- init_cma_reserved_pageblock(pfn_to_page(base_pfn));
- } while (--i);
-
- return 0;
-
-err:
- kfree(cma->bitmap);
- return -EINVAL;
}
-static struct cma cma_areas[MAX_CMA_AREAS];
-static unsigned cma_area_count;
-
-static int __init cma_init_reserved_areas(void)
-{
- int i;
-
- for (i = 0; i < cma_area_count; i++) {
- int ret = cma_activate_area(&cma_areas[i]);
- if (ret)
- return ret;
- }
-
- return 0;
-}
-core_initcall(cma_init_reserved_areas);
-
/**
* dma_contiguous_reserve_area() - reserve custom contiguous area
* @size: Size of the reserved area (in bytes),
* @base: Base address of the reserved area optional, use 0 for any
* @limit: End address of the reserved memory (optional, 0 for any).
* @res_cma: Pointer to store the created cma region.
+ * @fixed: hint about where to place the reserved area
*
* This function reserves memory from early allocator. It should be
* called by arch specific code once the early allocator (memblock or bootmem)
* has been activated and all other subsystems have already allocated/reserved
* memory. This function allows to create custom reserved areas for specific
* devices.
+ *
+ * If @fixed is true, reserve contiguous area at exactly @base. If false,
+ * reserve in range from @base to @limit.
*/
int __init dma_contiguous_reserve_area(phys_addr_t size, phys_addr_t base,
- phys_addr_t limit, struct cma **res_cma)
+ phys_addr_t limit, struct cma **res_cma,
+ bool fixed)
{
- struct cma *cma = &cma_areas[cma_area_count];
- phys_addr_t alignment;
- int ret = 0;
+ int ret;
- pr_debug("%s(size %lx, base %08lx, limit %08lx)\n", __func__,
- (unsigned long)size, (unsigned long)base,
- (unsigned long)limit);
-
- /* Sanity checks */
- if (cma_area_count == ARRAY_SIZE(cma_areas)) {
- pr_err("Not enough slots for CMA reserved regions!\n");
- return -ENOSPC;
- }
-
- if (!size)
- return -EINVAL;
-
- /* Sanitise input arguments */
- alignment = PAGE_SIZE << max(MAX_ORDER - 1, pageblock_order);
- base = ALIGN(base, alignment);
- size = ALIGN(size, alignment);
- limit &= ~(alignment - 1);
-
- /* Reserve memory */
- if (base) {
- if (memblock_is_region_reserved(base, size) ||
- memblock_reserve(base, size) < 0) {
- ret = -EBUSY;
- goto err;
- }
- } else {
- /*
- * Use __memblock_alloc_base() since
- * memblock_alloc_base() panic()s.
- */
- phys_addr_t addr = __memblock_alloc_base(size, alignment, limit);
- if (!addr) {
- ret = -ENOMEM;
- goto err;
- } else {
- base = addr;
- }
- }
-
- /*
- * Each reserved area must be initialised later, when more kernel
- * subsystems (like slab allocator) are available.
- */
- cma->base_pfn = PFN_DOWN(base);
- cma->count = size >> PAGE_SHIFT;
- *res_cma = cma;
- cma_area_count++;
-
- pr_info("CMA: reserved %ld MiB at %pa\n", (unsigned long)size / SZ_1M,
- &base);
+ ret = cma_declare_contiguous(base, size, limit, 0, 0, fixed, res_cma);
+ if (ret)
+ return ret;
/* Architecture specific contiguous memory fixup. */
- dma_contiguous_early_fixup(base, size);
+ dma_contiguous_early_fixup(cma_get_base(*res_cma),
+ cma_get_size(*res_cma));
+
return 0;
-err:
- pr_err("CMA: failed to reserve %ld MiB\n", (unsigned long)size / SZ_1M);
- return ret;
}
/**
@@ -273,58 +184,16 @@
*
* This function allocates memory buffer for specified device. It uses
* device specific contiguous memory area if available or the default
- * global one. Requires architecture specific get_dev_cma_area() helper
+ * global one. Requires architecture specific dev_get_cma_area() helper
* function.
*/
struct page *dma_alloc_from_contiguous(struct device *dev, int count,
unsigned int align)
{
- unsigned long mask, offset, pfn, pageno, start = 0;
- struct cma *cma = dev_get_cma_area(dev);
- struct page *page = NULL;
- int ret;
-
- if (!cma || !cma->count)
- return NULL;
-
if (align > CONFIG_CMA_ALIGNMENT)
align = CONFIG_CMA_ALIGNMENT;
- pr_debug("%s(cma %p, count %d, align %d)\n", __func__, (void *)cma,
- count, align);
-
- if (!count)
- return NULL;
-
- mask = (1 << align) - 1;
- offset = ALIGN(cma->base_pfn, 1 << align) - cma->base_pfn;
-
- mutex_lock(&cma_mutex);
-
- for (;;) {
- pageno = bitmap_find_next_zero_area_off(cma->bitmap, cma->count,
- start, count, mask, offset);
- if (pageno >= cma->count)
- break;
-
- pfn = cma->base_pfn + pageno;
- ret = alloc_contig_range(pfn, pfn + count, MIGRATE_CMA);
- if (ret == 0) {
- bitmap_set(cma->bitmap, pageno, count);
- page = pfn_to_page(pfn);
- break;
- } else if (ret != -EBUSY) {
- break;
- }
- pr_debug("%s(): memory range at %p is busy, retrying\n",
- __func__, pfn_to_page(pfn));
- /* try again with a bit different memory target */
- start = pageno + mask + 1;
- }
-
- mutex_unlock(&cma_mutex);
- pr_debug("%s(): returned %p\n", __func__, page);
- return page;
+ return cma_alloc(dev_get_cma_area(dev), count, align);
}
/**
@@ -340,25 +209,71 @@
bool dma_release_from_contiguous(struct device *dev, struct page *pages,
int count)
{
- struct cma *cma = dev_get_cma_area(dev);
- unsigned long pfn;
-
- if (!cma || !pages)
- return false;
-
- pr_debug("%s(page %p)\n", __func__, (void *)pages);
-
- pfn = page_to_pfn(pages);
-
- if (pfn < cma->base_pfn || pfn >= cma->base_pfn + cma->count)
- return false;
-
- VM_BUG_ON(pfn + count > cma->base_pfn + cma->count);
-
- mutex_lock(&cma_mutex);
- bitmap_clear(cma->bitmap, pfn - cma->base_pfn, count);
- free_contig_range(pfn, count);
- mutex_unlock(&cma_mutex);
-
- return true;
+ return cma_release(dev_get_cma_area(dev), pages, count);
}
+
+/*
+ * Support for reserved memory regions defined in device tree
+ */
+#ifdef CONFIG_OF_RESERVED_MEM
+#include <linux/of.h>
+#include <linux/of_fdt.h>
+#include <linux/of_reserved_mem.h>
+
+#undef pr_fmt
+#define pr_fmt(fmt) fmt
+
+static void rmem_cma_device_init(struct reserved_mem *rmem, struct device *dev)
+{
+ dev_set_cma_area(dev, rmem->priv);
+}
+
+static void rmem_cma_device_release(struct reserved_mem *rmem,
+ struct device *dev)
+{
+ dev_set_cma_area(dev, NULL);
+}
+
+static const struct reserved_mem_ops rmem_cma_ops = {
+ .device_init = rmem_cma_device_init,
+ .device_release = rmem_cma_device_release,
+};
+
+static int __init rmem_cma_setup(struct reserved_mem *rmem)
+{
+ phys_addr_t align = PAGE_SIZE << max(MAX_ORDER - 1, pageblock_order);
+ phys_addr_t mask = align - 1;
+ unsigned long node = rmem->fdt_node;
+ struct cma *cma;
+ int err;
+
+ if (!of_get_flat_dt_prop(node, "reusable", NULL) ||
+ of_get_flat_dt_prop(node, "no-map", NULL))
+ return -EINVAL;
+
+ if ((rmem->base & mask) || (rmem->size & mask)) {
+ pr_err("Reserved memory: incorrect alignment of CMA region\n");
+ return -EINVAL;
+ }
+
+ err = cma_init_reserved_mem(rmem->base, rmem->size, 0, &cma);
+ if (err) {
+ pr_err("Reserved memory: unable to setup CMA region\n");
+ return err;
+ }
+ /* Architecture specific contiguous memory fixup. */
+ dma_contiguous_early_fixup(rmem->base, rmem->size);
+
+ if (of_get_flat_dt_prop(node, "linux,cma-default", NULL))
+ dma_contiguous_set_default(cma);
+
+ rmem->ops = &rmem_cma_ops;
+ rmem->priv = cma;
+
+ pr_info("Reserved memory: created CMA memory pool at %pa, size %ld MiB\n",
+ &rmem->base, (unsigned long)rmem->size / SZ_1M);
+
+ return 0;
+}
+RESERVEDMEM_OF_DECLARE(cma, "shared-dma-pool", rmem_cma_setup);
+#endif
diff --git a/drivers/bus/Kconfig b/drivers/bus/Kconfig
index 552373c..c3e3d37 100644
--- a/drivers/bus/Kconfig
+++ b/drivers/bus/Kconfig
@@ -4,6 +4,14 @@
menu "Bus devices"
+config BRCMSTB_GISB_ARB
+ bool "Broadcom STB GISB bus arbiter"
+ depends on ARM || MIPS
+ help
+ Driver for the Broadcom Set Top Box System-on-a-chip internal bus
+ arbiter. This driver provides timeout and target abort error handling
+ and internal bus master decoding.
+
config IMX_WEIM
bool "Freescale EIM DRIVER"
depends on ARCH_MXC
diff --git a/drivers/bus/Makefile b/drivers/bus/Makefile
index 8947bdd..04dee20 100644
--- a/drivers/bus/Makefile
+++ b/drivers/bus/Makefile
@@ -2,6 +2,7 @@
# Makefile for the bus drivers.
#
+obj-$(CONFIG_BRCMSTB_GISB_ARB) += brcmstb_gisb.o
obj-$(CONFIG_IMX_WEIM) += imx-weim.o
obj-$(CONFIG_MVEBU_MBUS) += mvebu-mbus.o
obj-$(CONFIG_OMAP_OCP2SCP) += omap-ocp2scp.o
diff --git a/arch/arm/mach-bcm/gisb-brcmstb.c b/drivers/bus/brcmstb_gisb.c
similarity index 96%
rename from arch/arm/mach-bcm/gisb-brcmstb.c
rename to drivers/bus/brcmstb_gisb.c
index 9f92861..d27fe41 100644
--- a/arch/arm/mach-bcm/gisb-brcmstb.c
+++ b/drivers/bus/brcmstb_gisb.c
@@ -166,12 +166,6 @@
return ret;
}
-void __init brcmstb_hook_fault_code(void)
-{
- hook_fault_code(22, brcmstb_bus_error_handler, SIGBUS, 0,
- "imprecise external abort");
-}
-
static irqreturn_t brcmstb_gisb_timeout_handler(int irq, void *dev_id)
{
brcmstb_gisb_arb_decode_addr(dev_id, "timeout");
@@ -198,7 +192,7 @@
.attrs = gisb_arb_sysfs_attrs,
};
-static int brcmstb_gisb_arb_probe(struct platform_device *pdev)
+static int __init brcmstb_gisb_arb_probe(struct platform_device *pdev)
{
struct device_node *dn = pdev->dev.of_node;
struct brcmstb_gisb_arb_device *gdev;
@@ -267,6 +261,9 @@
list_add_tail(&gdev->next, &brcmstb_gisb_arb_device_list);
+ hook_fault_code(22, brcmstb_bus_error_handler, SIGBUS, 0,
+ "imprecise external abort");
+
dev_info(&pdev->dev, "registered mem: %p, irqs: %d, %d\n",
gdev->base, timeout_irq, tea_irq);
@@ -312,7 +309,6 @@
};
static struct platform_driver brcmstb_gisb_arb_driver = {
- .probe = brcmstb_gisb_arb_probe,
.driver = {
.name = "brcm-gisb-arb",
.owner = THIS_MODULE,
@@ -323,7 +319,8 @@
static int __init brcm_gisb_driver_init(void)
{
- return platform_driver_register(&brcmstb_gisb_arb_driver);
+ return platform_driver_probe(&brcmstb_gisb_arb_driver,
+ brcmstb_gisb_arb_probe);
}
module_init(brcm_gisb_driver_init);
diff --git a/drivers/char/bmoca.c b/drivers/char/bmoca.c
index 55dc64d..5a7f6e5 100644
--- a/drivers/char/bmoca.c
+++ b/drivers/char/bmoca.c
@@ -142,6 +142,7 @@
#define FLUSH_IRQ 1
#define FLUSH_DMA_ONLY 2
#define FLUSH_REQRESP_ONLY 3
+#define FLUSH_WOL_ONLY 4
#define DEFAULT_PHY_CLOCK (300 * 1000000)
#define MOCA_SUSPEND_TIMEOUT_MS 300
@@ -184,6 +185,7 @@
unsigned int moca2host_mmp_inbox_0_offset;
unsigned int moca2host_mmp_inbox_1_offset;
unsigned int moca2host_mmp_inbox_2_offset;
+ unsigned int extras_mmp_outbox_3_offset;
unsigned int h2m_resp_bit[2]; /* indexed by cpu */
unsigned int h2m_req_bit[2]; /* indexed by cpu */
unsigned int sideband_gmii_fc_offset;
@@ -232,7 +234,6 @@
int enabled;
int running;
- int wol_enabled;
struct clk *clk;
struct clk *phy_clk;
struct clk *cpu_clk;
@@ -364,6 +365,7 @@
.moca2host_mmp_inbox_0_offset = 0x001ffd58,
.moca2host_mmp_inbox_1_offset = 0x001ffd5c,
.moca2host_mmp_inbox_2_offset = 0x001ffd60,
+ .extras_mmp_outbox_3_offset = 0x001fec3c,
.h2m_resp_bit[1] = 0x10,
.h2m_req_bit[1] = 0x20,
.h2m_resp_bit[0] = 0x1,
@@ -401,6 +403,8 @@
[MOCA_SUSPENDING_GOT_ACK] = "suspending got ACK",
[MOCA_SUSPENDED] = "suspended",
[MOCA_RESUMING] = "resuming",
+ [MOCA_RESUMING_ASSERT] = "resuming ASSERT",
+ [MOCA_RESUMING_WDOG] = "resuming WDOG"
};
/* support for multiple MoCA devices */
@@ -418,6 +422,7 @@
#define M2H_NEXTCHUNK BIT(3)
#define M2H_NEXTCHUNK_CPU0 BIT(4)
#define M2H_WDT_CPU0 BIT(6)
+#define M2H_WOL BIT(7)
#define M2H_WDT_CPU1 BIT(10)
#define M2H_DMA BIT(11)
@@ -425,6 +430,9 @@
#define M2H_REQ_CPU0 BIT(14)
#define M2H_ASSERT_CPU0 BIT(15)
+#define ASSERT_PENDING_CPU0 BIT(0)
+#define ASSERT_PENDING_CPU1 BIT(1)
+
/* does this word contain a NIL byte (i.e. end of string)? */
#define HAS0(x) ((((x) & 0xff) == 0) || \
(((x) & 0xff00) == 0) || \
@@ -665,6 +673,11 @@
M2H_RESP_CPU0 | M2H_REQ_CPU0));
MOCA_RD(priv->base + r->l2_clear_offset);
}
+ if (flush == FLUSH_WOL_ONLY) {
+ MOCA_WR(priv->base + r->l2_clear_offset,
+ stat & M2H_WOL);
+ MOCA_RD(priv->base + r->l2_clear_offset);
+ }
spin_unlock_irqrestore(&priv->irq_status_lock, flags);
@@ -1390,8 +1403,10 @@
mutex_lock(&priv->dev_mutex);
+
if (priv->enabled) {
mask = moca_irq_status(priv, FLUSH_IRQ);
+
if (mask & M2H_DMA) {
mask &= ~M2H_DMA;
complete(&priv->copy_complete);
@@ -1432,13 +1447,13 @@
ret = moca_recvmsg(priv, priv->core_req_offset,
priv->core_req_size, 0, 1);
if (ret == -ENOMEM)
- priv->assert_pending = 2;
+ priv->assert_pending = ASSERT_PENDING_CPU1;
}
if (mask & M2H_ASSERT_CPU0) {
ret = moca_recvmsg(priv, priv->core_req_offset,
priv->core_req_size, 0, 0);
if (ret == -ENOMEM)
- priv->assert_pending = 1;
+ priv->assert_pending = ASSERT_PENDING_CPU0;
}
/* M2H_WDT_CPU1 is mapped to the only CPU for MoCA11 HW */
if (mask & M2H_WDT_CPU1) {
@@ -1955,20 +1970,6 @@
ret = -EIO;
break;
case MOCA_IOCTL_WOL:
- if (arg) {
- device_set_wakeup_enable(&priv->pdev->dev, 1);
- if (!priv->wol_enabled)
- enable_irq_wake(priv->wol_irq);
- priv->wol_enabled = 1;
- } else {
- device_set_wakeup_enable(&priv->pdev->dev, 0);
- /* Avoid unbalanced disable_irq_wake calls */
- if (priv->wol_enabled)
- disable_irq_wake(priv->wol_irq);
- priv->wol_enabled = 0;
- }
- dev_info(priv->dev, "WOL is %s\n",
- priv->wol_enabled ? "enabled" : "disabled");
ret = 0;
break;
case MOCA_IOCTL_SET_CPU_RATE:
@@ -2053,10 +2054,10 @@
return -EIO;
}
- if (priv->assert_pending & 2) {
+ if (priv->assert_pending & ASSERT_PENDING_CPU1) {
if (moca_recvmsg(priv, priv->core_req_offset,
priv->core_req_size, 0, 1) != -ENOMEM)
- priv->assert_pending &= ~2;
+ priv->assert_pending &= ~ASSERT_PENDING_CPU1;
else
dev_warn(priv->dev,
"moca_recvmsg assert failed\n");
@@ -2064,7 +2065,7 @@
if (priv->assert_pending & 1) {
if (moca_recvmsg(priv, priv->core_req_offset,
priv->core_req_size, 0, 0) != -ENOMEM)
- priv->assert_pending &= ~1;
+ priv->assert_pending &= ~ASSERT_PENDING_CPU0;
else
dev_warn(priv->dev,
"moca_recvmsg assert failed\n");
@@ -2242,21 +2243,21 @@
/* mandatory entries */
/* get the common clocks from bmoca node */
- priv->clk = of_clk_get_by_name(of_node, "sw_moca");
+ priv->clk = devm_clk_get(&pdev->dev, "sw_moca");
if (IS_ERR(priv->clk)) {
dev_err(&pdev->dev,
"can't find sw_moca clk\n");
priv->clk = NULL;
}
- priv->cpu_clk = of_clk_get_by_name(of_node, "sw_moca_cpu");
+ priv->cpu_clk = devm_clk_get(&pdev->dev, "sw_moca_cpu");
if (IS_ERR(priv->cpu_clk)) {
dev_err(&pdev->dev,
"can't find moca_cpu clk\n");
priv->cpu_clk = NULL;
}
- priv->phy_clk = of_clk_get_by_name(of_node, "sw_moca_phy");
+ priv->phy_clk = devm_clk_get(&pdev->dev, "sw_moca_phy");
if (IS_ERR(priv->phy_clk)) {
dev_err(&pdev->dev,
"can't find moca_phy clk\n");
@@ -2449,7 +2450,6 @@
long timeout = msecs_to_jiffies(MOCA_SUSPEND_TIMEOUT_MS);
mutex_lock(&priv->dev_mutex);
-
if (moca_in_reset(priv)) {
dev_warn(priv->dev, "MoCA core powered off\n");
goto out;
@@ -2490,11 +2490,27 @@
int rc;
mutex_lock(&priv->dev_mutex);
+
if (moca_in_reset(priv)) {
dev_warn(priv->dev, "MoCA core in reset\n");
goto out;
}
+ if (priv->state == MOCA_RESUMING_ASSERT) {
+ /*
+ * There should be an assert message queued.
+ * It doesn't matter what CPU, mocad will figure it out.
+ */
+ int ret = moca_recvmsg(priv, priv->core_req_offset,
+ priv->core_req_size, 0, 1);
+ if (ret == -ENOMEM)
+ priv->assert_pending = ASSERT_PENDING_CPU1;
+ ret = moca_recvmsg(priv, priv->core_req_offset,
+ priv->core_req_size, 0, 0);
+ if (ret == -ENOMEM)
+ priv->assert_pending |= ASSERT_PENDING_CPU0;
+ }
+
if (priv->state != MOCA_RESUMING) {
dev_warn(priv->dev, "state %s should be %s\n",
moca_state_string[priv->state],
@@ -2553,12 +2569,40 @@
{
return unregister_pm_notifier(&priv->pm_notifier);
}
-#endif
+#else
+
+static inline void moca_set_pm_state(struct moca_priv_data *priv,
+ enum moca_pm_states state)
+{
+}
+
+#endif /* CONFIG_PM */
static irqreturn_t moca_wol_isr(int irq, void *dev_id)
{
struct moca_priv_data *priv = dev_id;
+ /* get status reg and log */
+ u32 stat = moca_irq_status(priv, FLUSH_WOL_ONLY);
+ u32 assert_code_in = 0;
+ if (moca_is_20(priv))
+ assert_code_in = MOCA_RD(priv->base +
+ priv->regs->extras_mmp_outbox_3_offset);
+
+ /* Assert takes precedence over Watchdog, takes precedence over WoL */
+ if (((stat & M2H_WOL) && assert_code_in != 0)
+ || (stat & (M2H_ASSERT | M2H_ASSERT_CPU0))) {
+ dev_dbg(priv->dev, "ASSERT %x!\n", assert_code_in);
+ moca_set_pm_state(priv, MOCA_RESUMING_ASSERT);
+ } else if (stat & M2H_WOL) {
+ dev_dbg(priv->dev, "WOL!\n");
+ }
+
+ if (stat & (M2H_WDT_CPU1 | M2H_WDT_CPU0)) {
+ dev_dbg(priv->dev, "WATCHDOG!\n");
+ moca_set_pm_state(priv, MOCA_RESUMING_WDOG);
+ }
+
pm_wakeup_event(&priv->pdev->dev, 0);
return IRQ_HANDLED;
@@ -2567,11 +2611,11 @@
static int moca_probe(struct platform_device *pdev)
{
struct moca_priv_data *priv;
- struct resource *mres, *ires;
+ struct resource *mres;
int minor, err;
struct moca_platform_data *pd;
- priv = kzalloc(sizeof(*priv), GFP_KERNEL);
+ priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
if (!priv) {
dev_err(&pdev->dev, "out of memory\n");
return -ENOMEM;
@@ -2583,7 +2627,7 @@
#if defined(CONFIG_OF)
err = moca_parse_dt_node(priv);
if (err)
- goto bad;
+ return err;
#endif
pd = pdev->dev.platform_data;
priv->hw_rev = pd->hw_rev;
@@ -2602,8 +2646,7 @@
else {
dev_err(&pdev->dev, "unsupported MoCA HWREV: %x\n",
pd->hw_rev);
- err = -EINVAL;
- goto bad;
+ return -EINVAL;
}
init_waitqueue_head(&priv->host_msg_wq);
@@ -2634,27 +2677,27 @@
if (priv->minor == -1) {
dev_err(&pdev->dev, "can't allocate minor device\n");
- err = -EIO;
- goto bad;
+ return -EIO;
}
mres = platform_get_resource(pdev, IORESOURCE_MEM, 0);
- ires = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
- if (!mres || !ires) {
- dev_err(&pdev->dev, "can't get resources\n");
- err = -EIO;
- goto bad;
+ priv->base = devm_ioremap_resource(&pdev->dev, mres);
+ if (IS_ERR(priv->base))
+ return PTR_ERR(priv->base);
+
+ priv->irq = platform_get_irq(pdev, 0);
+ if (priv->irq < 0) {
+ dev_err(&pdev->dev, "can't get IRQ\n");
+ return -EIO;
}
- priv->base = ioremap(mres->start, mres->end - mres->start + 1);
- priv->irq = ires->start;
priv->wol_irq = platform_get_irq(pdev, 1);
if (priv->wol_irq < 0)
dev_err(&pdev->dev, "can't find IRQs\n");
if (pd->bcm3450_i2c_base)
- priv->i2c_base = ioremap(pd->bcm3450_i2c_base,
- sizeof(struct bsc_regs));
+ priv->i2c_base = devm_ioremap(&pdev->dev, pd->bcm3450_i2c_base,
+ sizeof(struct bsc_regs));
/* leave core in reset until we get an ioctl */
moca_hw_reset(priv);
@@ -2662,16 +2705,17 @@
if (request_irq(priv->irq, moca_interrupt, 0, "moca",
priv) < 0) {
dev_err(&pdev->dev, "can't request interrupt\n");
- err = -EIO;
- goto bad2;
+ return -EIO;
}
/* Request the WOL interrupt line and advertise suspend if available */
- priv->wol_enabled = 0;
err = devm_request_irq(&pdev->dev, priv->wol_irq, moca_wol_isr, 0,
"mocawol", priv);
- if (!err && !(priv->wol_irq < 0))
+ if (!err && !(priv->wol_irq < 0)) {
device_set_wakeup_capable(&pdev->dev, 1);
+ device_set_wakeup_enable(&priv->pdev->dev, 1);
+ enable_irq_wake(priv->wol_irq);
+ }
moca_hw_init(priv, MOCA_ENABLE);
moca_disable_irq(priv);
@@ -2698,46 +2742,22 @@
if (err) {
dev_err(&pdev->dev, "register_pm_notifier failed err %d\n",
err);
- goto bad2;
+ return err;
}
#endif
return 0;
-
-bad2:
- if (priv->base)
- iounmap(priv->base);
- if (priv->i2c_base)
- iounmap(priv->i2c_base);
-bad:
- kfree(priv);
- return err;
}
static int moca_remove(struct platform_device *pdev)
{
struct moca_priv_data *priv = dev_get_drvdata(&pdev->dev);
- struct clk *clk = priv->clk;
- struct clk *phy_clk = priv->phy_clk;
- struct clk *cpu_clk = priv->cpu_clk;
- struct clk *wol_clk = priv->wol_clk;
int err = 0;
if (priv->dev)
device_destroy(moca_class, MKDEV(MOCA_MAJOR, priv->minor));
minor_tbl[priv->minor] = NULL;
- free_irq(priv->irq, priv);
- if (priv->i2c_base)
- iounmap(priv->i2c_base);
- if (priv->base)
- iounmap(priv->base);
-
- clk_put(cpu_clk);
- clk_put(phy_clk);
- clk_put(clk);
- clk_put(wol_clk);
-
#ifdef CONFIG_PM
err = moca_unregister_pm_notifier(priv);
if (err) {
@@ -2745,12 +2765,11 @@
err);
}
#endif
- kfree(priv);
return err;
}
-#ifdef CONFIG_PM
+#ifdef CONFIG_PM_SLEEP
static int moca_suspend(struct device *dev)
{
int minor;
@@ -2793,8 +2812,10 @@
for (minor = 0; minor < NUM_MINORS; minor++) {
struct moca_priv_data *priv = minor_tbl[minor];
+
if (priv && priv->enabled) {
- if (moca_in_reset(priv)) {
+ if (priv->state != MOCA_RESUMING_WDOG
+ && moca_in_reset(priv)) {
/*
* If we lost power to the block
* (e.g. unclean S3 transition), but
@@ -2812,37 +2833,31 @@
}
mutex_lock(&priv->dev_mutex);
- if (priv->enabled && priv->state != MOCA_SUSPENDED)
+ if (priv->state != MOCA_SUSPENDED)
dev_warn(priv->dev, "state %s should be %s\n",
moca_state_string[priv->state],
moca_state_string[MOCA_SUSPENDED]);
- moca_set_pm_state(priv, MOCA_RESUMING);
+ if (priv->state != MOCA_RESUMING_ASSERT
+ && priv->state != MOCA_RESUMING_WDOG)
+ moca_set_pm_state(priv, MOCA_RESUMING);
mutex_unlock(&priv->dev_mutex);
}
}
return 0;
}
-
-static const struct dev_pm_ops moca_pm_ops = {
- .suspend = moca_suspend,
- .resume = moca_resume,
-};
-
#endif
+static SIMPLE_DEV_PM_OPS(moca_pm_ops, moca_suspend, moca_resume);
+
static struct platform_driver moca_plat_drv = {
.probe = moca_probe,
.remove = moca_remove,
.driver = {
.name = "bmoca",
.owner = THIS_MODULE,
-#ifdef CONFIG_PM
.pm = &moca_pm_ops,
-#endif
-#ifdef CONFIG_OF
.of_match_table = of_match_ptr(bmoca_instance_match),
-#endif
},
};
diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile
index be0e6af..9f9e1d8 100644
--- a/drivers/clk/Makefile
+++ b/drivers/clk/Makefile
@@ -6,6 +6,7 @@
obj-$(CONFIG_COMMON_CLK) += clk-fixed-factor.o
obj-$(CONFIG_COMMON_CLK) += clk-fixed-rate.o
obj-$(CONFIG_COMMON_CLK) += clk-gate.o
+obj-$(CONFIG_COMMON_CLK) += clk-multiplier.o
obj-$(CONFIG_COMMON_CLK) += clk-mux.o
obj-$(CONFIG_COMMON_CLK) += clk-composite.o
diff --git a/drivers/clk/clk-brcmstb.c b/drivers/clk/clk-brcmstb.c
index e0a93ab..eede1f5 100644
--- a/drivers/clk/clk-brcmstb.c
+++ b/drivers/clk/clk-brcmstb.c
@@ -483,6 +483,8 @@
.data = of_fixed_factor_clk_setup, },
{ .compatible = "divider-clock",
.data = of_divider_clk_setup, },
+ { .compatible = "multiplier-clock",
+ .data = of_multiplier_clk_setup, },
{}
};
diff --git a/drivers/clk/clk-divider.c b/drivers/clk/clk-divider.c
index 5a6cee0..99a458a 100644
--- a/drivers/clk/clk-divider.c
+++ b/drivers/clk/clk-divider.c
@@ -161,7 +161,7 @@
if (!(__clk_get_flags(hw->clk) & CLK_SET_RATE_PARENT)) {
parent_rate = *best_parent_rate;
- bestdiv = DIV_ROUND_UP(parent_rate, rate);
+ bestdiv = DIV_ROUND_UP_ULL((u64)parent_rate, rate);
bestdiv = bestdiv == 0 ? 1 : bestdiv;
bestdiv = bestdiv > maxdiv ? maxdiv : bestdiv;
return bestdiv;
@@ -391,6 +391,7 @@
u8 clk_divider_flags = 0;
u32 mask = 0;
u32 shift = 0;
+ u32 width;
struct clk_div_table *table;
of_property_read_string(node, "clock-output-names", &clk_name);
@@ -408,6 +409,11 @@
node->name);
return;
}
+ width = fls(mask);
+ if ((1 << width) - 1 != mask) {
+ pr_err("%s: bad bit-mask for %s\n", __func__, node->name);
+ return;
+ }
if (of_property_read_u32(node, "bit-shift", &shift)) {
shift = __ffs(mask);
@@ -432,7 +438,7 @@
return;
clk = _register_divider(NULL, clk_name, parent_name, 0, reg, shift,
- mask, clk_divider_flags, table, NULL);
+ width, clk_divider_flags, table, NULL);
if (!IS_ERR(clk))
of_clk_add_provider(node, of_clk_src_simple_get, clk);
diff --git a/drivers/clk/clk-multiplier.c b/drivers/clk/clk-multiplier.c
new file mode 100644
index 0000000..e7b452d
--- /dev/null
+++ b/drivers/clk/clk-multiplier.c
@@ -0,0 +1,550 @@
+/*
+ * Copyright (C) 2015 Jim Quinlan, Broadcom <jim2101024@gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * Adjustable multiplier clock implementation. This is essentially
+ * the mirror of clk-divider.c.
+ */
+
+#include <linux/clk-provider.h>
+#include <linux/module.h>
+#include <linux/slab.h>
+#include <linux/io.h>
+#include <linux/err.h>
+#include <linux/string.h>
+#include <linux/log2.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+
+/*
+ * DOC: basic adjustable multiplier clock that cannot gate
+ *
+ * Traits of this clock:
+ * prepare - clk_prepare only ensures that parents are prepared
+ * enable - clk_enable only ensures that parents are enabled
+ * rate - rate is adjustable. clk->rate = (parent->rate * multiplier)
+ * parent - fixed parent. No clk_set_parent support
+ */
+
+#define to_clk_multiplier(_hw) container_of(_hw, struct clk_multiplier, hw)
+
+#define mult_mask(width) ((1 << (width)) - 1)
+
+static unsigned int _get_table_minmult(const struct clk_mult_table *table)
+{
+ unsigned int minmult = UINT_MAX;
+ const struct clk_mult_table *clkt;
+
+ for (clkt = table; clkt->mult; clkt++)
+ if (clkt->mult < minmult)
+ minmult = clkt->mult;
+ return minmult;
+}
+
+static unsigned int _get_table_maxmult(const struct clk_mult_table *table)
+{
+ unsigned int maxmult = 0;
+ const struct clk_mult_table *clkt;
+
+ for (clkt = table; clkt->mult; clkt++)
+ if (clkt->mult > maxmult)
+ maxmult = clkt->mult;
+ return maxmult;
+}
+
+static unsigned int _get_minmult(const struct clk_mult_table *table)
+{
+ if (table)
+ return _get_table_minmult(table);
+ return 1;
+}
+
+static unsigned int _get_maxmult(const struct clk_mult_table *table, u8 width,
+ unsigned long flags)
+{
+ if (flags & CLK_MULTIPLIER_ONE_BASED)
+ return mult_mask(width);
+ if (flags & CLK_MULTIPLIER_POWER_OF_TWO)
+ return 1 << mult_mask(width);
+ if (table)
+ return _get_table_maxmult(table);
+ return mult_mask(width) + 1;
+}
+
+static unsigned int _get_table_mult(const struct clk_mult_table *table,
+ unsigned int val)
+{
+ const struct clk_mult_table *clkt;
+
+ for (clkt = table; clkt->mult; clkt++)
+ if (clkt->val == val)
+ return clkt->mult;
+ return 0;
+}
+
+static unsigned int _get_mult(const struct clk_mult_table *table,
+ u8 width, unsigned int val, unsigned long flags)
+{
+ if (flags & CLK_MULTIPLIER_ONE_BASED)
+ return val;
+ if (flags & CLK_MULTIPLIER_POWER_OF_TWO)
+ return 1 << val;
+ if (flags & CLK_MULTIPLIER_MAX_MULT_AT_ZERO)
+ return val ? val : mult_mask(width) + 1;
+ if (table)
+ return _get_table_mult(table, val);
+ return val + 1;
+}
+
+static unsigned int _get_table_val(const struct clk_mult_table *table,
+ unsigned int mult)
+{
+ const struct clk_mult_table *clkt;
+
+ for (clkt = table; clkt->mult; clkt++)
+ if (clkt->mult == mult)
+ return clkt->val;
+ return 0;
+}
+
+static unsigned int _get_val(const struct clk_mult_table *table,
+ u8 width, unsigned int mult, unsigned long flags)
+{
+ if (flags & CLK_MULTIPLIER_ONE_BASED)
+ return mult;
+ if (flags & CLK_MULTIPLIER_POWER_OF_TWO)
+ return __ffs(mult);
+ if (flags & CLK_MULTIPLIER_MAX_MULT_AT_ZERO)
+ return (mult == mult_mask(width) + 1)
+ ? 0 : mult;
+ if (table)
+ return _get_table_val(table, mult);
+ return mult - 1;
+}
+
+unsigned long multiplier_recalc_rate(struct clk_hw *hw,
+ unsigned long parent_rate,
+ unsigned int val,
+ const struct clk_mult_table *table,
+ unsigned long flags)
+{
+ struct clk_multiplier *multiplier = to_clk_multiplier(hw);
+ unsigned int mult;
+
+ mult = _get_mult(table, multiplier->width, val, flags);
+ if (!mult) {
+ WARN(!(flags & CLK_MULTIPLIER_ALLOW_ZERO),
+ "%s: Zero multiplier and CLK_MULTIPLIER_ALLOW_ZERO not set\n",
+ __clk_get_name(hw->clk));
+ return parent_rate;
+ }
+
+ return parent_rate * mult;
+}
+EXPORT_SYMBOL_GPL(multiplier_recalc_rate);
+
+static unsigned long clk_multiplier_recalc_rate(struct clk_hw *hw,
+ unsigned long parent_rate)
+{
+ struct clk_multiplier *multiplier = to_clk_multiplier(hw);
+ unsigned int val;
+
+ val = clk_readl(multiplier->reg) >> multiplier->shift;
+ val &= mult_mask(multiplier->width);
+
+ return multiplier_recalc_rate(hw, parent_rate, val, multiplier->table,
+ multiplier->flags);
+}
+
+static bool _is_valid_table_mult(const struct clk_mult_table *table,
+ unsigned int mult)
+{
+ const struct clk_mult_table *clkt;
+
+ for (clkt = table; clkt->mult; clkt++)
+ if (clkt->mult == mult)
+ return true;
+ return false;
+}
+
+static bool _is_valid_mult(const struct clk_mult_table *table,
+ unsigned int mult, unsigned long flags)
+{
+ if (flags & CLK_MULTIPLIER_POWER_OF_TWO)
+ return is_power_of_2(mult);
+ if (table)
+ return _is_valid_table_mult(table, mult);
+ return true;
+}
+
+static int clk_multiplier_bestmult(struct clk_hw *hw, unsigned long rate,
+ unsigned long *best_parent_rate,
+ const struct clk_mult_table *table, u8 width,
+ unsigned long flags)
+{
+ int i, bestmult = 0;
+ unsigned long parent_rate, best = 0, now, maxmult, minmult;
+ unsigned long parent_rate_saved = *best_parent_rate;
+
+ if (!rate)
+ rate = 1;
+
+ minmult = _get_minmult(table);
+ maxmult = _get_maxmult(table, width, flags);
+
+ if (!(__clk_get_flags(hw->clk) & CLK_SET_RATE_PARENT)) {
+ parent_rate = *best_parent_rate;
+ bestmult = rate / parent_rate;
+ bestmult = bestmult == 0 ? minmult : bestmult;
+ bestmult = bestmult > maxmult ? maxmult : bestmult;
+ return bestmult;
+ }
+
+ /*
+ * The maximum multiplier we can use without overflowing
+ * unsigned long in rate * i below
+ */
+ maxmult = min(ULONG_MAX / parent_rate_saved, maxmult);
+
+ for (i = 1; i <= maxmult; i++) {
+ if (!_is_valid_mult(table, i, flags))
+ continue;
+ if (rate == parent_rate_saved * i) {
+ /*
+ * It's the most ideal case if the requested rate can be
+ * multiplied from parent clock without needing to
+ * change the parent rate, so return the multiplier
+ * immediately.
+ */
+ *best_parent_rate = parent_rate_saved;
+ return i;
+ }
+ parent_rate = __clk_round_rate(__clk_get_parent(hw->clk),
+ rate / i);
+ now = parent_rate * i;
+ if (now <= rate && now > best) {
+ bestmult = i;
+ best = now;
+ *best_parent_rate = parent_rate;
+ }
+ }
+
+ if (!bestmult) {
+ bestmult = _get_minmult(table);
+ *best_parent_rate
+ = __clk_round_rate(__clk_get_parent(hw->clk), 1);
+ }
+
+ return bestmult;
+}
+
+long multiplier_round_rate(struct clk_hw *hw, unsigned long rate,
+ unsigned long *prate,
+ const struct clk_mult_table *table,
+ u8 width, unsigned long flags)
+{
+ int mult;
+
+ mult = clk_multiplier_bestmult(hw, rate, prate, table, width, flags);
+
+ return *prate * mult;
+}
+EXPORT_SYMBOL_GPL(multiplier_round_rate);
+
+static long clk_multiplier_round_rate(struct clk_hw *hw, unsigned long rate,
+ unsigned long *prate)
+{
+ struct clk_multiplier *multiplier = to_clk_multiplier(hw);
+ int bestmult;
+
+ /* if read only, just return current value */
+ if (multiplier->flags & CLK_MULTIPLIER_READ_ONLY) {
+ bestmult = readl(multiplier->reg) >> multiplier->shift;
+ bestmult &= mult_mask(multiplier->width);
+ bestmult = _get_mult(multiplier->table, multiplier->width,
+ bestmult, multiplier->flags);
+ if ((__clk_get_flags(hw->clk) & CLK_SET_RATE_PARENT))
+ *prate = __clk_round_rate(__clk_get_parent(hw->clk),
+ rate);
+ return *prate * bestmult;
+ }
+
+ return multiplier_round_rate(hw, rate, prate, multiplier->table,
+ multiplier->width, multiplier->flags);
+}
+
+int multiplier_get_val(unsigned long rate, unsigned long parent_rate,
+ const struct clk_mult_table *table, u8 width,
+ unsigned long flags)
+{
+ unsigned int mult, value;
+
+ mult = rate / parent_rate;
+ value = _get_val(table, width, mult, flags);
+ return min_t(unsigned int, value, mult_mask(width));
+}
+EXPORT_SYMBOL_GPL(multiplier_get_val);
+
+static int clk_multiplier_set_rate(struct clk_hw *hw, unsigned long rate,
+ unsigned long parent_rate)
+{
+ struct clk_multiplier *multiplier = to_clk_multiplier(hw);
+ unsigned int value;
+ unsigned long flags = 0;
+ u32 val;
+
+ value = multiplier_get_val(rate, parent_rate, multiplier->table,
+ multiplier->width, multiplier->flags);
+
+ if (multiplier->lock)
+ spin_lock_irqsave(multiplier->lock, flags);
+
+ if (multiplier->flags & CLK_MULTIPLIER_HIWORD_MASK) {
+ val = mult_mask(multiplier->width) << (multiplier->shift + 16);
+ } else {
+ val = clk_readl(multiplier->reg);
+ val &= ~(mult_mask(multiplier->width) << multiplier->shift);
+ }
+ val |= value << multiplier->shift;
+ clk_writel(val, multiplier->reg);
+
+ if (multiplier->lock)
+ spin_unlock_irqrestore(multiplier->lock, flags);
+
+ return 0;
+}
+
+const struct clk_ops clk_multiplier_ops = {
+ .recalc_rate = clk_multiplier_recalc_rate,
+ .round_rate = clk_multiplier_round_rate,
+ .set_rate = clk_multiplier_set_rate,
+};
+EXPORT_SYMBOL_GPL(clk_multiplier_ops);
+
+const struct clk_ops clk_multiplier_ro_ops = {
+ .recalc_rate = clk_multiplier_recalc_rate,
+};
+EXPORT_SYMBOL_GPL(clk_multiplier_ro_ops);
+
+static struct clk *_register_multiplier(struct device *dev, const char *name,
+ const char *parent_name, unsigned long flags,
+ void __iomem *reg, u8 shift, u8 width,
+ u8 clk_multiplier_flags, const struct clk_mult_table *table,
+ spinlock_t *lock)
+{
+ struct clk_multiplier *mult;
+ struct clk *clk;
+ struct clk_init_data init;
+
+ if (clk_multiplier_flags & CLK_MULTIPLIER_HIWORD_MASK) {
+ if (width + shift > 16) {
+ pr_warn("multiplier value exceeds LOWORD field\n");
+ return ERR_PTR(-EINVAL);
+ }
+ }
+
+ /* allocate the multiplier */
+ mult = kzalloc(sizeof(struct clk_multiplier), GFP_KERNEL);
+ if (!mult)
+ return ERR_PTR(-ENOMEM);
+
+ init.name = name;
+ if (clk_multiplier_flags & CLK_MULTIPLIER_READ_ONLY)
+ init.ops = &clk_multiplier_ro_ops;
+ else
+ init.ops = &clk_multiplier_ops;
+ init.flags = flags | CLK_IS_BASIC;
+ init.parent_names = (parent_name ? &parent_name : NULL);
+ init.num_parents = (parent_name ? 1 : 0);
+
+ /* struct clk_multiplier assignments */
+ mult->reg = reg;
+ mult->shift = shift;
+ mult->width = width;
+ mult->flags = clk_multiplier_flags;
+ mult->lock = lock;
+ mult->hw.init = &init;
+ mult->table = table;
+
+ /* register the clock */
+ clk = clk_register(dev, &mult->hw);
+
+ if (IS_ERR(clk))
+ kfree(mult);
+
+ return clk;
+}
+
+/**
+ * clk_register_multiplier - register a multiplier clock with the clock framework
+ * @dev: device registering this clock
+ * @name: name of this clock
+ * @parent_name: name of clock's parent
+ * @flags: framework-specific flags
+ * @reg: register address to adjust multiplier
+ * @shift: number of bits to shift the bitfield
+ * @width: width of the bitfield
+ * @clk_multiplier_flags: multiplier-specific flags for this clock
+ * @lock: shared register lock for this clock
+ */
+struct clk *clk_register_multiplier(struct device *dev, const char *name,
+ const char *parent_name, unsigned long flags,
+ void __iomem *reg, u8 shift, u8 width,
+ u8 clk_multiplier_flags, spinlock_t *lock)
+{
+ return _register_multiplier(dev, name, parent_name, flags, reg, shift,
+ width, clk_multiplier_flags, NULL, lock);
+}
+EXPORT_SYMBOL_GPL(clk_register_multiplier);
+
+/**
+ * clk_register_multiplier_table - register a table based multiplier clock with
+ * the clock framework
+ * @dev: device registering this clock
+ * @name: name of this clock
+ * @parent_name: name of clock's parent
+ * @flags: framework-specific flags
+ * @reg: register address to adjust multiplier
+ * @shift: number of bits to shift the bitfield
+ * @width: width of the bitfield
+ * @clk_multiplier_flags: multiplier-specific flags for this clock
+ * @table: array of multiplier/value pairs ending with a mult set to 0
+ * @lock: shared register lock for this clock
+ */
+struct clk *clk_register_multiplier_table(struct device *dev, const char *name,
+ const char *parent_name, unsigned long flags,
+ void __iomem *reg, u8 shift, u8 width,
+ u8 clk_multiplier_flags, const struct clk_mult_table *table,
+ spinlock_t *lock)
+{
+ return _register_multiplier(dev, name, parent_name, flags, reg, shift,
+ width, clk_multiplier_flags, table, lock);
+}
+EXPORT_SYMBOL_GPL(clk_register_multiplier_table);
+
+void clk_unregister_multiplier(struct clk *clk)
+{
+ struct clk_multiplier *mult;
+ struct clk_hw *hw;
+
+ hw = __clk_get_hw(clk);
+ if (!hw)
+ return;
+
+ mult = to_clk_multiplier(hw);
+
+ clk_unregister(clk);
+ kfree(mult);
+}
+EXPORT_SYMBOL_GPL(clk_unregister_multiplier);
+
+#ifdef CONFIG_OF
+static struct clk_mult_table *of_clk_get_mult_table(struct device_node *node)
+{
+ int i;
+ unsigned int table_size;
+ struct clk_mult_table *table;
+ const __be32 *tablespec;
+ u32 val;
+
+ tablespec = of_get_property(node, "table", (int *) &table_size);
+
+ if (!tablespec)
+ return NULL;
+
+ table_size /= sizeof(struct clk_mult_table);
+
+ if (!table_size) {
+ pr_err("%s: %s table has zero length\n", __func__,
+ node->name);
+ return ERR_PTR(-EINVAL);
+ }
+
+ table = kzalloc(sizeof(struct clk_mult_table) * (table_size + 1),
+ GFP_KERNEL);
+ if (!table) {
+ pr_err("%s: unable to allocate memory for %s table\n", __func__,
+ node->name);
+ return NULL;
+ }
+
+ for (i = 0; i < table_size; i++) {
+ of_property_read_u32_index(node, "table", i * 2, &val);
+ table[i].mult = val;
+ of_property_read_u32_index(node, "table", i * 2 + 1, &val);
+ table[i].val = val;
+ }
+
+ return table;
+}
+
+/**
+ * of_multiplier_clk_setup() - Setup function for simple mult rate clock
+ */
+void of_multiplier_clk_setup(struct device_node *node)
+{
+ struct clk *clk;
+ const char *clk_name = node->name;
+ void __iomem *reg;
+ const char *parent_name;
+ u8 clk_multiplier_flags = 0;
+ u32 mask = 0;
+ u32 shift = 0;
+ u32 width;
+ struct clk_mult_table *table;
+
+ of_property_read_string(node, "clock-output-names", &clk_name);
+
+ parent_name = of_clk_get_parent_name(node, 0);
+
+ reg = of_iomap(node, 0);
+ if (!reg) {
+ pr_err("%s: no memory mapped for property reg\n", __func__);
+ return;
+ }
+
+ if (of_property_read_u32(node, "bit-mask", &mask)) {
+ pr_err("%s: missing bit-mask property for %s\n", __func__,
+ node->name);
+ return;
+ }
+ width = fls(mask);
+ if ((1 << width) - 1 != mask) {
+ pr_err("%s: bad bit-mask for %s\n", __func__, node->name);
+ return;
+ }
+
+ if (of_property_read_u32(node, "bit-shift", &shift)) {
+ shift = __ffs(mask);
+ pr_debug("%s: bit-shift property defaults to 0x%x for %s\n",
+ __func__, shift, node->name);
+ }
+
+ if (of_property_read_bool(node, "index-starts-at-one"))
+ clk_multiplier_flags |= CLK_MULTIPLIER_ONE_BASED;
+
+ if (of_property_read_bool(node, "index-power-of-two"))
+ clk_multiplier_flags |= CLK_MULTIPLIER_POWER_OF_TWO;
+
+ if (of_property_read_bool(node, "index-allow-zero"))
+ clk_multiplier_flags |= CLK_MULTIPLIER_ALLOW_ZERO;
+
+ if (of_property_read_bool(node, "index-max-mult-at-zero"))
+ clk_multiplier_flags |= CLK_MULTIPLIER_MAX_MULT_AT_ZERO;
+
+ table = of_clk_get_mult_table(node);
+ if (IS_ERR(table))
+ return;
+
+ clk = _register_multiplier(NULL, clk_name, parent_name, 0, reg, shift,
+ width, clk_multiplier_flags, table, NULL);
+
+ if (!IS_ERR(clk))
+ of_clk_add_provider(node, of_clk_src_simple_get, clk);
+}
+EXPORT_SYMBOL_GPL(of_multiplier_clk_setup);
+CLK_OF_DECLARE(multiplier_clk, "multiplier-clock", of_multiplier_clk_setup);
+#endif
diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig
index 903f24d..09dddfb 100644
--- a/drivers/gpio/Kconfig
+++ b/drivers/gpio/Kconfig
@@ -55,6 +55,9 @@
def_bool y
depends on ACPI
+config GPIOLIB_IRQCHIP
+ bool
+
config DEBUG_GPIO
bool "Debug GPIO calls"
depends on DEBUG_KERNEL
@@ -108,6 +111,15 @@
comment "Memory mapped GPIO drivers:"
+config GPIO_BRCMSTB
+ tristate "BRCMSTB GPIO support"
+ default y if ARCH_BRCMSTB
+ depends on OF_GPIO && (ARCH_BRCMSTB || COMPILE_TEST)
+ select GPIO_GENERIC
+ select GPIOLIB_IRQCHIP
+ help
+ Say yes here to enable GPIO support for Broadcom STB (BCM7XXX) SoCs.
+
config GPIO_CLPS711X
tristate "CLPS711X GPIO support"
depends on ARCH_CLPS711X || COMPILE_TEST
diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile
index 5d50179..b487bbd 100644
--- a/drivers/gpio/Makefile
+++ b/drivers/gpio/Makefile
@@ -17,6 +17,7 @@
obj-$(CONFIG_GPIO_AMD8111) += gpio-amd8111.o
obj-$(CONFIG_GPIO_ARIZONA) += gpio-arizona.o
obj-$(CONFIG_GPIO_BCM_KONA) += gpio-bcm-kona.o
+obj-$(CONFIG_GPIO_BRCMSTB) += gpio-brcmstb.o
obj-$(CONFIG_GPIO_BT8XX) += gpio-bt8xx.o
obj-$(CONFIG_GPIO_CLPS711X) += gpio-clps711x.o
obj-$(CONFIG_GPIO_CS5535) += gpio-cs5535.o
diff --git a/drivers/gpio/gpio-brcmstb.c b/drivers/gpio/gpio-brcmstb.c
new file mode 100644
index 0000000..2212ab8
--- /dev/null
+++ b/drivers/gpio/gpio-brcmstb.c
@@ -0,0 +1,558 @@
+/*
+ * Copyright (C) 2015 Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation version 2.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/bitops.h>
+#include <linux/gpio/driver.h>
+#include <linux/of_device.h>
+#include <linux/of_irq.h>
+#include <linux/module.h>
+#include <linux/basic_mmio_gpio.h>
+#include <linux/irqdomain.h>
+#include <linux/irqchip/chained_irq.h>
+#include <linux/interrupt.h>
+#include <linux/reboot.h>
+
+#define GIO_BANK_SIZE 0x20
+#define GIO_ODEN(bank) (((bank) * GIO_BANK_SIZE) + 0x00)
+#define GIO_DATA(bank) (((bank) * GIO_BANK_SIZE) + 0x04)
+#define GIO_IODIR(bank) (((bank) * GIO_BANK_SIZE) + 0x08)
+#define GIO_EC(bank) (((bank) * GIO_BANK_SIZE) + 0x0c)
+#define GIO_EI(bank) (((bank) * GIO_BANK_SIZE) + 0x10)
+#define GIO_MASK(bank) (((bank) * GIO_BANK_SIZE) + 0x14)
+#define GIO_LEVEL(bank) (((bank) * GIO_BANK_SIZE) + 0x18)
+#define GIO_STAT(bank) (((bank) * GIO_BANK_SIZE) + 0x1c)
+
+struct brcmstb_gpio_bank {
+ struct list_head node;
+ int id;
+ struct bgpio_chip bgc;
+ struct brcmstb_gpio_priv *parent_priv;
+ u32 width;
+ struct irq_chip irq_chip;
+};
+
+struct brcmstb_gpio_priv {
+ struct list_head bank_list;
+ void __iomem *reg_base;
+ struct platform_device *pdev;
+ int parent_irq;
+ int gpio_base;
+ bool can_wake;
+ int parent_wake_irq;
+ struct notifier_block reboot_notifier;
+};
+
+#define MAX_GPIO_PER_BANK 32
+#define GPIO_BANK(gpio) ((gpio) >> 5)
+/* assumes MAX_GPIO_PER_BANK is a multiple of 2 */
+#define GPIO_BIT(gpio) ((gpio) & (MAX_GPIO_PER_BANK - 1))
+
+static inline struct brcmstb_gpio_bank *
+brcmstb_gpio_gc_to_bank(struct gpio_chip *gc)
+{
+ struct bgpio_chip *bgc = to_bgpio_chip(gc);
+ return container_of(bgc, struct brcmstb_gpio_bank, bgc);
+}
+
+static inline struct brcmstb_gpio_priv *
+brcmstb_gpio_gc_to_priv(struct gpio_chip *gc)
+{
+ struct brcmstb_gpio_bank *bank = brcmstb_gpio_gc_to_bank(gc);
+ return bank->parent_priv;
+}
+
+static void brcmstb_gpio_set_imask(struct brcmstb_gpio_bank *bank,
+ unsigned int offset, bool enable)
+{
+ struct bgpio_chip *bgc = &bank->bgc;
+ struct brcmstb_gpio_priv *priv = bank->parent_priv;
+ u32 mask = bgc->pin2mask(bgc, offset);
+ u32 imask;
+ unsigned long flags;
+
+ spin_lock_irqsave(&bgc->lock, flags);
+ imask = bgc->read_reg(priv->reg_base + GIO_MASK(bank->id));
+ if (enable)
+ imask |= mask;
+ else
+ imask &= ~mask;
+ bgc->write_reg(priv->reg_base + GIO_MASK(bank->id), imask);
+ spin_unlock_irqrestore(&bgc->lock, flags);
+}
+
+/* -------------------- IRQ chip functions -------------------- */
+
+static void brcmstb_gpio_irq_mask(struct irq_data *d)
+{
+ struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
+ struct brcmstb_gpio_bank *bank = brcmstb_gpio_gc_to_bank(gc);
+
+ brcmstb_gpio_set_imask(bank, d->hwirq, false);
+}
+
+static void brcmstb_gpio_irq_unmask(struct irq_data *d)
+{
+ struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
+ struct brcmstb_gpio_bank *bank = brcmstb_gpio_gc_to_bank(gc);
+
+ brcmstb_gpio_set_imask(bank, d->hwirq, true);
+}
+
+static int brcmstb_gpio_irq_set_type(struct irq_data *d, unsigned int type)
+{
+ struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
+ struct brcmstb_gpio_bank *bank = brcmstb_gpio_gc_to_bank(gc);
+ struct brcmstb_gpio_priv *priv = bank->parent_priv;
+ u32 mask = BIT(d->hwirq);
+ u32 edge_insensitive, iedge_insensitive;
+ u32 edge_config, iedge_config;
+ u32 level, ilevel;
+ unsigned long flags;
+
+ switch (type) {
+ case IRQ_TYPE_LEVEL_LOW:
+ level = 0;
+ edge_config = 0;
+ edge_insensitive = 0;
+ break;
+ case IRQ_TYPE_LEVEL_HIGH:
+ level = mask;
+ edge_config = 0;
+ edge_insensitive = 0;
+ break;
+ case IRQ_TYPE_EDGE_FALLING:
+ level = 0;
+ edge_config = 0;
+ edge_insensitive = 0;
+ break;
+ case IRQ_TYPE_EDGE_RISING:
+ level = 0;
+ edge_config = mask;
+ edge_insensitive = 0;
+ break;
+ case IRQ_TYPE_EDGE_BOTH:
+ level = 0;
+ edge_config = 0; /* don't care, but want known value */
+ edge_insensitive = mask;
+ break;
+ default:
+ return -EINVAL;
+ }
+
+ spin_lock_irqsave(&bank->bgc.lock, flags);
+
+ iedge_config = bank->bgc.read_reg(priv->reg_base +
+ GIO_EC(bank->id)) & ~mask;
+ iedge_insensitive = bank->bgc.read_reg(priv->reg_base +
+ GIO_EI(bank->id)) & ~mask;
+ ilevel = bank->bgc.read_reg(priv->reg_base +
+ GIO_LEVEL(bank->id)) & ~mask;
+
+ bank->bgc.write_reg(priv->reg_base + GIO_EC(bank->id),
+ iedge_config | edge_config);
+ bank->bgc.write_reg(priv->reg_base + GIO_EI(bank->id),
+ iedge_insensitive | edge_insensitive);
+ bank->bgc.write_reg(priv->reg_base + GIO_LEVEL(bank->id),
+ ilevel | level);
+
+ spin_unlock_irqrestore(&bank->bgc.lock, flags);
+ return 0;
+}
+
+static int __brcmstb_gpio_irq_set_wake(struct brcmstb_gpio_priv *priv,
+ unsigned int enable)
+{
+ int ret = 0;
+
+ /*
+ * Only enable wake IRQ once for however many hwirqs can wake
+ * since they all use the same wake IRQ. Mask will be set
+ * up appropriately thanks to IRQCHIP_MASK_ON_SUSPEND flag.
+ */
+ if (enable)
+ ret = enable_irq_wake(priv->parent_wake_irq);
+ else
+ ret = disable_irq_wake(priv->parent_wake_irq);
+ if (ret)
+ dev_err(&priv->pdev->dev, "failed to %s wake-up interrupt\n",
+ enable ? "enable" : "disable");
+ return ret;
+}
+
+static int brcmstb_gpio_irq_set_wake(struct irq_data *d, unsigned int enable)
+{
+ struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
+ struct brcmstb_gpio_priv *priv = brcmstb_gpio_gc_to_priv(gc);
+
+ return __brcmstb_gpio_irq_set_wake(priv, enable);
+}
+
+static irqreturn_t brcmstb_gpio_wake_irq_handler(int irq, void *data)
+{
+ struct brcmstb_gpio_priv *priv = data;
+
+ if (!priv || irq != priv->parent_wake_irq)
+ return IRQ_NONE;
+ pm_wakeup_event(&priv->pdev->dev, 0);
+ return IRQ_HANDLED;
+}
+
+static void brcmstb_gpio_irq_bank_handler(int irq,
+ struct brcmstb_gpio_bank *bank)
+{
+ struct brcmstb_gpio_priv *priv = bank->parent_priv;
+ struct irq_domain *irq_domain = bank->bgc.gc.irqdomain;
+ void __iomem *reg_base = priv->reg_base;
+ unsigned long status;
+ unsigned long flags;
+
+ spin_lock_irqsave(&bank->bgc.lock, flags);
+ while ((status = bank->bgc.read_reg(reg_base + GIO_STAT(bank->id)) &
+ bank->bgc.read_reg(reg_base + GIO_MASK(bank->id)))) {
+ int bit;
+ for_each_set_bit(bit, &status, 32) {
+ u32 stat = bank->bgc.read_reg(reg_base +
+ GIO_STAT(bank->id));
+ if (bit >= bank->width)
+ dev_warn(&priv->pdev->dev,
+ "IRQ for invalid GPIO (bank=%d, offset=%d)\n",
+ bank->id, bit);
+ bank->bgc.write_reg(reg_base + GIO_STAT(bank->id),
+ stat | BIT(bit));
+ generic_handle_irq(irq_find_mapping(irq_domain, bit));
+ }
+ }
+ spin_unlock_irqrestore(&bank->bgc.lock, flags);
+}
+
+/* Each UPG GIO block has one IRQ for all banks */
+static void brcmstb_gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
+{
+ struct gpio_chip *gc = irq_desc_get_handler_data(desc);
+ struct brcmstb_gpio_priv *priv = brcmstb_gpio_gc_to_priv(gc);
+ struct irq_chip *chip = irq_desc_get_chip(desc);
+ struct list_head *pos;
+
+ /* Interrupts weren't properly cleared during probe */
+ BUG_ON(!priv || !chip);
+
+ chained_irq_enter(chip, desc);
+ list_for_each(pos, &priv->bank_list) {
+ struct brcmstb_gpio_bank *bank =
+ list_entry(pos, struct brcmstb_gpio_bank, node);
+ brcmstb_gpio_irq_bank_handler(irq, bank);
+ }
+ chained_irq_exit(chip, desc);
+}
+
+static int brcmstb_gpio_reboot(struct notifier_block *nb,
+ unsigned long action, void *data)
+{
+ struct brcmstb_gpio_priv *priv =
+ container_of(nb, struct brcmstb_gpio_priv, reboot_notifier);
+
+ /* Enable GPIO for S5 cold boot */
+ if (action == SYS_POWER_OFF)
+ __brcmstb_gpio_irq_set_wake(priv, 1);
+
+ return NOTIFY_DONE;
+}
+
+/* Make sure that the number of banks matches up between properties */
+static int brcmstb_gpio_sanity_check_banks(struct device *dev,
+ struct device_node *np, struct resource *res)
+{
+ int res_num_banks = resource_size(res) / GIO_BANK_SIZE;
+ int num_banks = of_property_count_u32_elems(np, "brcm,gpio-bank-widths");
+
+ if (res_num_banks != num_banks) {
+ dev_err(dev, "Mismatch in banks: res had %d, bank-widths had %d\n",
+ res_num_banks, num_banks);
+ return -EINVAL;
+ } else {
+ return 0;
+ }
+}
+
+static int brcmstb_gpio_remove(struct platform_device *pdev)
+{
+ struct brcmstb_gpio_priv *priv = platform_get_drvdata(pdev);
+ struct list_head *pos;
+ struct brcmstb_gpio_bank *bank;
+ int ret = 0;
+
+ if (!priv) {
+ dev_err(&pdev->dev, "called %s without drvdata!\n", __func__);
+ return -EFAULT;
+ }
+
+ /*
+ * You can lose return values below, but we report all errors, and it's
+ * more important to actually perform all of the steps.
+ */
+ list_for_each(pos, &priv->bank_list) {
+ bank = list_entry(pos, struct brcmstb_gpio_bank, node);
+ ret = bgpio_remove(&bank->bgc);
+ if (ret)
+ dev_err(&pdev->dev, "gpiochip_remove fail in cleanup\n");
+ }
+ if (priv->reboot_notifier.notifier_call) {
+ ret = unregister_reboot_notifier(&priv->reboot_notifier);
+ if (ret)
+ dev_err(&pdev->dev,
+ "failed to unregister reboot notifier\n");
+ }
+ return ret;
+}
+
+static int brcmstb_gpio_of_xlate(struct gpio_chip *gc,
+ const struct of_phandle_args *gpiospec, u32 *flags)
+{
+ struct brcmstb_gpio_priv *priv = brcmstb_gpio_gc_to_priv(gc);
+ struct brcmstb_gpio_bank *bank = brcmstb_gpio_gc_to_bank(gc);
+ int offset;
+
+ if (gc->of_gpio_n_cells != 2) {
+ WARN_ON(1);
+ return -EINVAL;
+ }
+
+ if (WARN_ON(gpiospec->args_count < gc->of_gpio_n_cells))
+ return -EINVAL;
+
+ offset = gpiospec->args[0] - (gc->base - priv->gpio_base);
+ if (offset >= gc->ngpio || offset < 0)
+ return -EINVAL;
+
+ if (unlikely(offset >= bank->width)) {
+ dev_warn_ratelimited(&priv->pdev->dev,
+ "Received request for invalid GPIO offset %d\n",
+ gpiospec->args[0]);
+ }
+
+ if (flags)
+ *flags = gpiospec->args[1];
+
+ return offset;
+}
+
+/* Before calling, must have bank->parent_irq set and gpiochip registered */
+static int brcmstb_gpio_irq_setup(struct platform_device *pdev,
+ struct brcmstb_gpio_bank *bank)
+{
+ struct brcmstb_gpio_priv *priv = bank->parent_priv;
+ struct device *dev = &pdev->dev;
+ struct device_node *np = dev->of_node;
+
+ bank->irq_chip.name = dev_name(dev);
+ bank->irq_chip.irq_mask = brcmstb_gpio_irq_mask;
+ bank->irq_chip.irq_unmask = brcmstb_gpio_irq_unmask;
+ bank->irq_chip.irq_set_type = brcmstb_gpio_irq_set_type;
+
+ /* Ensures that all non-wakeup IRQs are disabled at suspend */
+ bank->irq_chip.flags = IRQCHIP_MASK_ON_SUSPEND;
+
+ if (IS_ENABLED(CONFIG_PM_SLEEP) && !priv->can_wake &&
+ of_property_read_bool(np, "wakeup-source")) {
+ priv->parent_wake_irq = platform_get_irq(pdev, 1);
+ if (priv->parent_wake_irq < 0) {
+ dev_warn(dev,
+ "Couldn't get wake IRQ - GPIOs will not be able to wake from sleep");
+ } else {
+ int err;
+
+ /*
+ * Set wakeup capability before requesting wakeup
+ * interrupt, so we can process boot-time "wakeups"
+ * (e.g., from S5 cold boot)
+ */
+ device_set_wakeup_capable(dev, true);
+ device_wakeup_enable(dev);
+ err = devm_request_irq(dev, priv->parent_wake_irq,
+ brcmstb_gpio_wake_irq_handler, 0,
+ "brcmstb-gpio-wake", priv);
+
+ if (err < 0) {
+ dev_err(dev, "Couldn't request wake IRQ");
+ return err;
+ }
+
+ priv->reboot_notifier.notifier_call =
+ brcmstb_gpio_reboot;
+ register_reboot_notifier(&priv->reboot_notifier);
+ priv->can_wake = true;
+ }
+ }
+
+ if (priv->can_wake)
+ bank->irq_chip.irq_set_wake = brcmstb_gpio_irq_set_wake;
+
+ gpiochip_irqchip_add(&bank->bgc.gc, &bank->irq_chip, 0,
+ handle_simple_irq, IRQ_TYPE_NONE);
+ gpiochip_set_chained_irqchip(&bank->bgc.gc, &bank->irq_chip,
+ priv->parent_irq, brcmstb_gpio_irq_handler);
+
+ return 0;
+}
+
+static int brcmstb_gpio_probe(struct platform_device *pdev)
+{
+ struct device *dev = &pdev->dev;
+ struct device_node *np = dev->of_node;
+ void __iomem *reg_base;
+ struct brcmstb_gpio_priv *priv;
+ struct resource *res;
+ struct property *prop;
+ const __be32 *p;
+ u32 bank_width;
+ int num_banks = 0;
+ int err;
+ static int gpio_base;
+
+ priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
+ if (!priv)
+ return -ENOMEM;
+ platform_set_drvdata(pdev, priv);
+ INIT_LIST_HEAD(&priv->bank_list);
+
+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ reg_base = devm_ioremap_resource(dev, res);
+ if (IS_ERR(reg_base))
+ return PTR_ERR(reg_base);
+
+ priv->gpio_base = gpio_base;
+ priv->reg_base = reg_base;
+ priv->pdev = pdev;
+
+ if (of_property_read_bool(np, "interrupt-controller")) {
+ priv->parent_irq = platform_get_irq(pdev, 0);
+ if (priv->parent_irq < 0) {
+#ifdef CONFIG_BCM7120_L2_IRQ
+ dev_err(dev, "Couldn't get IRQ");
+ return -ENOENT;
+#else
+ /* TODO: change back when BCM7120_L2_IRQ is default */
+ dev_warn(dev, "Couldn't get IRQ. Enable CONFIG_BCM7120_L2_IRQ if you want GPIO interrupt support\n");
+#endif
+ }
+ } else {
+ priv->parent_irq = -ENOENT;
+ }
+
+ if (brcmstb_gpio_sanity_check_banks(dev, np, res))
+ return -EINVAL;
+
+ of_property_for_each_u32(np, "brcm,gpio-bank-widths", prop, p,
+ bank_width) {
+ struct brcmstb_gpio_bank *bank;
+ struct bgpio_chip *bgc;
+ struct gpio_chip *gc;
+
+ bank = devm_kzalloc(dev, sizeof(*bank), GFP_KERNEL);
+ if (!bank) {
+ err = -ENOMEM;
+ goto fail;
+ }
+
+ bank->parent_priv = priv;
+ bank->id = num_banks;
+ if (bank_width <= 0 || bank_width > MAX_GPIO_PER_BANK) {
+ dev_err(dev, "Invalid bank width %d\n", bank_width);
+ goto fail;
+ } else {
+ bank->width = bank_width;
+ }
+
+ /*
+ * Regs are 4 bytes wide, have data reg, no set/clear regs,
+ * and direction bits have 0 = output and 1 = input
+ */
+ bgc = &bank->bgc;
+ err = bgpio_init(bgc, dev, 4,
+ reg_base + GIO_DATA(bank->id),
+ NULL, NULL, NULL,
+ reg_base + GIO_IODIR(bank->id), 0);
+ if (err) {
+ dev_err(dev, "bgpio_init() failed\n");
+ goto fail;
+ }
+
+ gc = &bgc->gc;
+ gc->of_node = np;
+ gc->owner = THIS_MODULE;
+ gc->label = np->full_name;
+ gc->base = gpio_base;
+ gc->of_gpio_n_cells = 2;
+ gc->of_xlate = brcmstb_gpio_of_xlate;
+ /* not all ngpio lines are valid, will use bank width later */
+ gc->ngpio = MAX_GPIO_PER_BANK;
+
+ /*
+ * Mask all interrupts by default, since wakeup interrupts may
+ * be retained from S5 cold boot
+ */
+ bank->bgc.write_reg(reg_base + GIO_MASK(bank->id), 0);
+
+ err = gpiochip_add(gc);
+ if (err) {
+ dev_err(dev, "Could not add gpiochip for bank %d\n",
+ bank->id);
+ goto fail;
+ }
+ gpio_base += gc->ngpio;
+
+ if (priv->parent_irq >= 0) {
+ err = brcmstb_gpio_irq_setup(pdev, bank);
+ if (err)
+ goto fail;
+ }
+
+ dev_dbg(dev, "bank=%d, base=%d, ngpio=%d, width=%d\n", bank->id,
+ gc->base, gc->ngpio, bank->width);
+
+ /* Everything looks good, so add bank to list */
+ list_add(&bank->node, &priv->bank_list);
+
+ num_banks++;
+ }
+
+ dev_info(dev, "Registered %d banks (GPIO(s): %d-%d)\n",
+ num_banks, priv->gpio_base, gpio_base - 1);
+
+ return 0;
+
+fail:
+ (void) brcmstb_gpio_remove(pdev);
+ return err;
+}
+
+static struct of_device_id brcmstb_gpio_of_match[] = {
+ { .compatible = "brcm,brcmstb-gpio" },
+ {},
+};
+
+MODULE_DEVICE_TABLE(of, brcmstb_gpio_of_match);
+
+static struct platform_driver brcmstb_gpio_driver = {
+ .driver = {
+ .name = "brcmstb-gpio",
+ .of_match_table = brcmstb_gpio_of_match,
+ },
+ .probe = brcmstb_gpio_probe,
+ .remove = brcmstb_gpio_remove,
+};
+module_platform_driver(brcmstb_gpio_driver);
+
+MODULE_AUTHOR("Gregory Fong");
+MODULE_DESCRIPTION("Driver for Broadcom BRCMSTB SoC UPG GPIO");
+MODULE_LICENSE("GPL v2");
diff --git a/drivers/gpio/gpiolib.c b/drivers/gpio/gpiolib.c
index 50c4922..66b1cc2 100644
--- a/drivers/gpio/gpiolib.c
+++ b/drivers/gpio/gpiolib.c
@@ -66,9 +66,7 @@
#define GPIO_FLAGS_MASK ((1 << ID_SHIFT) - 1)
#define GPIO_TRIGGER_MASK (BIT(FLAG_TRIG_FALL) | BIT(FLAG_TRIG_RISE))
-#ifdef CONFIG_DEBUG_FS
const char *label;
-#endif
};
static struct gpio_desc gpio_desc[ARCH_NR_GPIOS];
@@ -87,7 +85,6 @@
/* With descriptor prefix */
-#ifdef CONFIG_DEBUG_FS
#define gpiod_emerg(desc, fmt, ...) \
pr_emerg("gpio-%d (%s): " fmt, desc_to_gpio(desc), desc->label ? : "?",\
##__VA_ARGS__)
@@ -106,20 +103,6 @@
#define gpiod_dbg(desc, fmt, ...) \
pr_debug("gpio-%d (%s): " fmt, desc_to_gpio(desc), desc->label ? : "?",\
##__VA_ARGS__)
-#else
-#define gpiod_emerg(desc, fmt, ...) \
- pr_emerg("gpio-%d: " fmt, desc_to_gpio(desc), ##__VA_ARGS__)
-#define gpiod_crit(desc, fmt, ...) \
- pr_crit("gpio-%d: " fmt, desc_to_gpio(desc), ##__VA_ARGS__)
-#define gpiod_err(desc, fmt, ...) \
- pr_err("gpio-%d: " fmt, desc_to_gpio(desc), ##__VA_ARGS__)
-#define gpiod_warn(desc, fmt, ...) \
- pr_warn("gpio-%d: " fmt, desc_to_gpio(desc), ##__VA_ARGS__)
-#define gpiod_info(desc, fmt, ...) \
- pr_info("gpio-%d: " fmt, desc_to_gpio(desc), ##__VA_ARGS__)
-#define gpiod_dbg(desc, fmt, ...) \
- pr_debug("gpio-%d: " fmt, desc_to_gpio(desc), ##__VA_ARGS__)
-#endif
/* With chip prefix */
@@ -138,9 +121,7 @@
static inline void desc_set_label(struct gpio_desc *d, const char *label)
{
-#ifdef CONFIG_DEBUG_FS
d->label = label;
-#endif
}
/*
@@ -164,16 +145,17 @@
EXPORT_SYMBOL_GPL(gpio_to_desc);
/**
- * Convert an offset on a certain chip to a corresponding descriptor
+ * Get the GPIO descriptor corresponding to the given hw number for this chip.
*/
-static struct gpio_desc *gpiochip_offset_to_desc(struct gpio_chip *chip,
- unsigned int offset)
+struct gpio_desc *gpiochip_get_desc(struct gpio_chip *chip,
+ u16 hwnum)
{
- if (offset >= chip->ngpio)
+ if (hwnum >= chip->ngpio)
return ERR_PTR(-EINVAL);
- return &chip->desc[offset];
+ return &chip->desc[hwnum];
}
+EXPORT_SYMBOL_GPL(gpiochip_get_desc);
/**
* Convert a GPIO descriptor to the integer namespace.
@@ -350,9 +332,9 @@
if (!test_bit(FLAG_EXPORT, &desc->flags))
status = -EIO;
else if (sysfs_streq(buf, "high"))
- status = gpiod_direction_output(desc, 1);
+ status = gpiod_direction_output_raw(desc, 1);
else if (sysfs_streq(buf, "out") || sysfs_streq(buf, "low"))
- status = gpiod_direction_output(desc, 0);
+ status = gpiod_direction_output_raw(desc, 0);
else if (sysfs_streq(buf, "in"))
status = gpiod_direction_input(desc);
else
@@ -1222,6 +1204,9 @@
spin_unlock_irqrestore(&gpio_lock, flags);
+ if (status)
+ goto fail;
+
#ifdef CONFIG_PINCTRL
INIT_LIST_HEAD(&chip->pin_ranges);
#endif
@@ -1229,12 +1214,12 @@
of_gpiochip_add(chip);
acpi_gpiochip_add(chip);
- if (status)
- goto fail;
-
status = gpiochip_export(chip);
- if (status)
+ if (status) {
+ acpi_gpiochip_remove(chip);
+ of_gpiochip_remove(chip);
goto fail;
+ }
pr_debug("%s: registered GPIOs %d to %d on device: %s\n", __func__,
chip->base, chip->base + chip->ngpio - 1,
@@ -1253,6 +1238,9 @@
}
EXPORT_SYMBOL_GPL(gpiochip_add);
+/* Forward-declaration */
+static void gpiochip_irqchip_remove(struct gpio_chip *gpiochip);
+
/**
* gpiochip_remove() - unregister a gpio_chip
* @chip: the chip to unregister
@@ -1267,6 +1255,7 @@
spin_lock_irqsave(&gpio_lock, flags);
+ gpiochip_irqchip_remove(chip);
gpiochip_remove_pin_ranges(chip);
of_gpiochip_remove(chip);
acpi_gpiochip_remove(chip);
@@ -1337,6 +1326,240 @@
return gpiochip_find((void *)name, gpiochip_match_name);
}
+#ifdef CONFIG_GPIOLIB_IRQCHIP
+
+/*
+ * The following is irqchip helper code for gpiochips.
+ */
+
+/**
+ * gpiochip_add_chained_irqchip() - adds a chained irqchip to a gpiochip
+ * @gpiochip: the gpiochip to add the irqchip to
+ * @irqchip: the irqchip to add to the gpiochip
+ * @parent_irq: the irq number corresponding to the parent IRQ for this
+ * chained irqchip
+ * @parent_handler: the parent interrupt handler for the accumulated IRQ
+ * coming out of the gpiochip
+ */
+void gpiochip_set_chained_irqchip(struct gpio_chip *gpiochip,
+ struct irq_chip *irqchip,
+ int parent_irq,
+ irq_flow_handler_t parent_handler)
+{
+ if (gpiochip->can_sleep) {
+ chip_err(gpiochip, "you cannot have chained interrupts on a chip that may sleep\n");
+ return;
+ }
+
+ /*
+ * The parent irqchip is already using the chip_data for this
+ * irqchip, so our callbacks simply use the handler_data.
+ */
+ irq_set_handler_data(parent_irq, gpiochip);
+ irq_set_chained_handler(parent_irq, parent_handler);
+}
+EXPORT_SYMBOL_GPL(gpiochip_set_chained_irqchip);
+
+/*
+ * This lock class tells lockdep that GPIO irqs are in a different
+ * category than their parents, so it won't report false recursion.
+ */
+static struct lock_class_key gpiochip_irq_lock_class;
+
+/**
+ * gpiochip_irq_map() - maps an IRQ into a GPIO irqchip
+ * @d: the irqdomain used by this irqchip
+ * @irq: the global irq number used by this GPIO irqchip irq
+ * @hwirq: the local IRQ/GPIO line offset on this gpiochip
+ *
+ * This function will set up the mapping for a certain IRQ line on a
+ * gpiochip by assigning the gpiochip as chip data, and using the irqchip
+ * stored inside the gpiochip.
+ */
+static int gpiochip_irq_map(struct irq_domain *d, unsigned int irq,
+ irq_hw_number_t hwirq)
+{
+ struct gpio_chip *chip = d->host_data;
+
+ irq_set_chip_data(irq, chip);
+ irq_set_lockdep_class(irq, &gpiochip_irq_lock_class);
+ irq_set_chip_and_handler(irq, chip->irqchip, chip->irq_handler);
+ /* Chips that can sleep need nested thread handlers */
+ if (chip->can_sleep)
+ irq_set_nested_thread(irq, 1);
+#ifdef CONFIG_ARM
+ set_irq_flags(irq, IRQF_VALID);
+#else
+ irq_set_noprobe(irq);
+#endif
+ /*
+ * No set-up of the hardware will happen if IRQ_TYPE_NONE
+ * is passed as default type.
+ */
+ if (chip->irq_default_type != IRQ_TYPE_NONE)
+ irq_set_irq_type(irq, chip->irq_default_type);
+
+ return 0;
+}
+
+static void gpiochip_irq_unmap(struct irq_domain *d, unsigned int irq)
+{
+ struct gpio_chip *chip = d->host_data;
+
+#ifdef CONFIG_ARM
+ set_irq_flags(irq, 0);
+#endif
+ if (chip->can_sleep)
+ irq_set_nested_thread(irq, 0);
+ irq_set_chip_and_handler(irq, NULL, NULL);
+ irq_set_chip_data(irq, NULL);
+}
+
+static const struct irq_domain_ops gpiochip_domain_ops = {
+ .map = gpiochip_irq_map,
+ .unmap = gpiochip_irq_unmap,
+ /* Virtually all GPIO irqchips are twocell:ed */
+ .xlate = irq_domain_xlate_twocell,
+};
+
+static int gpiochip_irq_reqres(struct irq_data *d)
+{
+ struct gpio_chip *chip = irq_data_get_irq_chip_data(d);
+
+ if (gpio_lock_as_irq(chip, d->hwirq)) {
+ chip_err(chip,
+ "unable to lock HW IRQ %lu for IRQ\n",
+ d->hwirq);
+ return -EINVAL;
+ }
+ return 0;
+}
+
+static void gpiochip_irq_relres(struct irq_data *d)
+{
+ struct gpio_chip *chip = irq_data_get_irq_chip_data(d);
+
+ gpio_unlock_as_irq(chip, d->hwirq);
+}
+
+static int gpiochip_to_irq(struct gpio_chip *chip, unsigned offset)
+{
+ return irq_find_mapping(chip->irqdomain, offset);
+}
+
+/**
+ * gpiochip_irqchip_remove() - removes an irqchip added to a gpiochip
+ * @gpiochip: the gpiochip to remove the irqchip from
+ *
+ * This is called only from gpiochip_remove()
+ */
+static void gpiochip_irqchip_remove(struct gpio_chip *gpiochip)
+{
+ unsigned int offset;
+
+ /* Remove all IRQ mappings and delete the domain */
+ if (gpiochip->irqdomain) {
+ for (offset = 0; offset < gpiochip->ngpio; offset++)
+ irq_dispose_mapping(gpiochip->irq_base + offset);
+ irq_domain_remove(gpiochip->irqdomain);
+ }
+
+ if (gpiochip->irqchip) {
+ gpiochip->irqchip->irq_request_resources = NULL;
+ gpiochip->irqchip->irq_release_resources = NULL;
+ gpiochip->irqchip = NULL;
+ }
+}
+
+/**
+ * gpiochip_irqchip_add() - adds an irqchip to a gpiochip
+ * @gpiochip: the gpiochip to add the irqchip to
+ * @irqchip: the irqchip to add to the gpiochip
+ * @first_irq: if not dynamically assigned, the base (first) IRQ to
+ * allocate gpiochip irqs from
+ * @handler: the irq handler to use (often a predefined irq core function)
+ * @type: the default type for IRQs on this irqchip, pass IRQ_TYPE_NONE
+ * to have the core avoid setting up any default type in the hardware.
+ *
+ * This function closely associates a certain irqchip with a certain
+ * gpiochip, providing an irq domain to translate the local IRQs to
+ * global irqs in the gpiolib core, and making sure that the gpiochip
+ * is passed as chip data to all related functions. Driver callbacks
+ * need to use container_of() to get their local state containers back
+ * from the gpiochip passed as chip data. An irqdomain will be stored
+ * in the gpiochip that shall be used by the driver to handle IRQ number
+ * translation. The gpiochip will need to be initialized and registered
+ * before calling this function.
+ *
+ * This function will handle two cell:ed simple IRQs and assumes all
+ * the pins on the gpiochip can generate a unique IRQ. Everything else
+ * need to be open coded.
+ */
+int gpiochip_irqchip_add(struct gpio_chip *gpiochip,
+ struct irq_chip *irqchip,
+ unsigned int first_irq,
+ irq_flow_handler_t handler,
+ unsigned int type)
+{
+ struct device_node *of_node;
+ unsigned int offset;
+ unsigned irq_base = 0;
+
+ if (!gpiochip || !irqchip)
+ return -EINVAL;
+
+ if (!gpiochip->dev) {
+ pr_err("missing gpiochip .dev parent pointer\n");
+ return -EINVAL;
+ }
+ of_node = gpiochip->dev->of_node;
+#ifdef CONFIG_OF_GPIO
+ /*
+ * If the gpiochip has an assigned OF node this takes precendence
+ * FIXME: get rid of this and use gpiochip->dev->of_node everywhere
+ */
+ if (gpiochip->of_node)
+ of_node = gpiochip->of_node;
+#endif
+ gpiochip->irqchip = irqchip;
+ gpiochip->irq_handler = handler;
+ gpiochip->irq_default_type = type;
+ gpiochip->to_irq = gpiochip_to_irq;
+ gpiochip->irqdomain = irq_domain_add_simple(of_node,
+ gpiochip->ngpio, first_irq,
+ &gpiochip_domain_ops, gpiochip);
+ if (!gpiochip->irqdomain) {
+ gpiochip->irqchip = NULL;
+ return -EINVAL;
+ }
+ irqchip->irq_request_resources = gpiochip_irq_reqres;
+ irqchip->irq_release_resources = gpiochip_irq_relres;
+
+ /*
+ * Prepare the mapping since the irqchip shall be orthogonal to
+ * any gpiochip calls. If the first_irq was zero, this is
+ * necessary to allocate descriptors for all IRQs.
+ */
+ for (offset = 0; offset < gpiochip->ngpio; offset++) {
+ irq_base = irq_create_mapping(gpiochip->irqdomain, offset);
+ if (offset == 0)
+ /*
+ * Store the base into the gpiochip to be used when
+ * unmapping the irqs.
+ */
+ gpiochip->irq_base = irq_base;
+ }
+
+ return 0;
+}
+EXPORT_SYMBOL_GPL(gpiochip_irqchip_add);
+
+#else /* CONFIG_GPIOLIB_IRQCHIP */
+
+static void gpiochip_irqchip_remove(struct gpio_chip *gpiochip) {}
+
+#endif /* CONFIG_GPIOLIB_IRQCHIP */
+
#ifdef CONFIG_PINCTRL
/**
@@ -1457,26 +1680,14 @@
* on each other, and help provide better diagnostics in debugfs.
* They're called even less than the "set direction" calls.
*/
-static int gpiod_request(struct gpio_desc *desc, const char *label)
+static int __gpiod_request(struct gpio_desc *desc, const char *label)
{
- struct gpio_chip *chip;
- int status = -EPROBE_DEFER;
+ struct gpio_chip *chip = desc->chip;
+ int status;
unsigned long flags;
- if (!desc) {
- pr_warn("%s: invalid GPIO\n", __func__);
- return -EINVAL;
- }
-
spin_lock_irqsave(&gpio_lock, flags);
- chip = desc->chip;
- if (chip == NULL)
- goto done;
-
- if (!try_module_get(chip->owner))
- goto done;
-
/* NOTE: gpio_request() can be called in early boot,
* before IRQs are enabled, for non-sleeping (SOC) GPIOs.
*/
@@ -1486,7 +1697,6 @@
status = 0;
} else {
status = -EBUSY;
- module_put(chip->owner);
goto done;
}
@@ -1498,7 +1708,6 @@
if (status < 0) {
desc_set_label(desc, NULL);
- module_put(chip->owner);
clear_bit(FLAG_REQUESTED, &desc->flags);
goto done;
}
@@ -1510,9 +1719,34 @@
spin_lock_irqsave(&gpio_lock, flags);
}
done:
+ spin_unlock_irqrestore(&gpio_lock, flags);
+ return status;
+}
+
+static int gpiod_request(struct gpio_desc *desc, const char *label)
+{
+ int status = -EPROBE_DEFER;
+ struct gpio_chip *chip;
+
+ if (!desc) {
+ pr_warn("%s: invalid GPIO\n", __func__);
+ return -EINVAL;
+ }
+
+ chip = desc->chip;
+ if (!chip)
+ goto done;
+
+ if (try_module_get(chip->owner)) {
+ status = __gpiod_request(desc, label);
+ if (status < 0)
+ module_put(chip->owner);
+ }
+
+done:
if (status)
gpiod_dbg(desc, "%s: status %d\n", __func__, status);
- spin_unlock_irqrestore(&gpio_lock, flags);
+
return status;
}
@@ -1522,18 +1756,14 @@
}
EXPORT_SYMBOL_GPL(gpio_request);
-static void gpiod_free(struct gpio_desc *desc)
+static bool __gpiod_free(struct gpio_desc *desc)
{
+ bool ret = false;
unsigned long flags;
struct gpio_chip *chip;
might_sleep();
- if (!desc) {
- WARN_ON(extra_checks);
- return;
- }
-
gpiod_unexport(desc);
spin_lock_irqsave(&gpio_lock, flags);
@@ -1547,15 +1777,23 @@
spin_lock_irqsave(&gpio_lock, flags);
}
desc_set_label(desc, NULL);
- module_put(desc->chip->owner);
clear_bit(FLAG_ACTIVE_LOW, &desc->flags);
clear_bit(FLAG_REQUESTED, &desc->flags);
clear_bit(FLAG_OPEN_DRAIN, &desc->flags);
clear_bit(FLAG_OPEN_SOURCE, &desc->flags);
- } else
- WARN_ON(extra_checks);
+ ret = true;
+ }
spin_unlock_irqrestore(&gpio_lock, flags);
+ return ret;
+}
+
+static void gpiod_free(struct gpio_desc *desc)
+{
+ if (desc && __gpiod_free(desc))
+ module_put(desc->chip->owner);
+ else
+ WARN_ON(extra_checks);
}
void gpio_free(unsigned gpio)
@@ -1590,7 +1828,7 @@
if (flags & GPIOF_DIR_IN)
err = gpiod_direction_input(desc);
else
- err = gpiod_direction_output(desc,
+ err = gpiod_direction_output_raw(desc,
(flags & GPIOF_INIT_HIGH) ? 1 : 0);
if (err)
@@ -1651,8 +1889,8 @@
* @offset: of signal within controller's 0..(ngpio - 1) range
*
* Returns NULL if the GPIO is not currently requested, else a string.
- * If debugfs support is enabled, the string returned is the label passed
- * to gpio_request(); otherwise it is a meaningless constant.
+ * The string returned is the label passed to gpio_request(); if none has been
+ * passed it is a meaningless, non-NULL constant.
*
* This function is for use by GPIO controller drivers. The label can
* help with diagnostics, and knowing that the signal is used as a GPIO
@@ -1669,14 +1907,41 @@
if (test_bit(FLAG_REQUESTED, &desc->flags) == 0)
return NULL;
-#ifdef CONFIG_DEBUG_FS
return desc->label;
-#else
- return "?";
-#endif
}
EXPORT_SYMBOL_GPL(gpiochip_is_requested);
+/**
+ * gpiochip_request_own_desc - Allow GPIO chip to request its own descriptor
+ * @desc: GPIO descriptor to request
+ * @label: label for the GPIO
+ *
+ * Function allows GPIO chip drivers to request and use their own GPIO
+ * descriptors via gpiolib API. Difference to gpiod_request() is that this
+ * function will not increase reference count of the GPIO chip module. This
+ * allows the GPIO chip module to be unloaded as needed (we assume that the
+ * GPIO chip driver handles freeing the GPIOs it has requested).
+ */
+int gpiochip_request_own_desc(struct gpio_desc *desc, const char *label)
+{
+ if (!desc || !desc->chip)
+ return -EINVAL;
+
+ return __gpiod_request(desc, label);
+}
+
+/**
+ * gpiochip_free_own_desc - Free GPIO requested by the chip driver
+ * @desc: GPIO descriptor to free
+ *
+ * Function frees the given GPIO requested previously with
+ * gpiochip_request_own_desc().
+ */
+void gpiochip_free_own_desc(struct gpio_desc *desc)
+{
+ if (desc)
+ __gpiod_free(desc);
+}
/* Drivers MUST set GPIO direction before making get/set calls. In
* some cases this is done in early boot, before IRQs are enabled.
@@ -1756,28 +2021,13 @@
}
EXPORT_SYMBOL_GPL(gpiod_direction_input);
-/**
- * gpiod_direction_output - set the GPIO direction to input
- * @desc: GPIO to set to output
- * @value: initial output value of the GPIO
- *
- * Set the direction of the passed GPIO to output, such as gpiod_set_value() can
- * be called safely on it. The initial value of the output must be specified.
- *
- * Return 0 in case of success, else an error code.
- */
-int gpiod_direction_output(struct gpio_desc *desc, int value)
+static int _gpiod_direction_output_raw(struct gpio_desc *desc, int value)
{
unsigned long flags;
struct gpio_chip *chip;
int status = -EINVAL;
int offset;
- if (!desc || !desc->chip) {
- pr_warn("%s: invalid GPIO\n", __func__);
- return -EINVAL;
- }
-
/* GPIOs used for IRQs shall not be set as output */
if (test_bit(FLAG_USED_AS_IRQ, &desc->flags)) {
gpiod_err(desc,
@@ -1840,6 +2090,50 @@
gpiod_dbg(desc, "%s: gpio status %d\n", __func__, status);
return status;
}
+
+/**
+ * gpiod_direction_output_raw - set the GPIO direction to output
+ * @desc: GPIO to set to output
+ * @value: initial output value of the GPIO
+ *
+ * Set the direction of the passed GPIO to output, such as gpiod_set_value() can
+ * be called safely on it. The initial value of the output must be specified
+ * as raw value on the physical line without regard for the ACTIVE_LOW status.
+ *
+ * Return 0 in case of success, else an error code.
+ */
+int gpiod_direction_output_raw(struct gpio_desc *desc, int value)
+{
+ if (!desc || !desc->chip) {
+ pr_warn("%s: invalid GPIO\n", __func__);
+ return -EINVAL;
+ }
+ return _gpiod_direction_output_raw(desc, value);
+}
+EXPORT_SYMBOL_GPL(gpiod_direction_output_raw);
+
+/**
+ * gpiod_direction_output - set the GPIO direction to output
+ * @desc: GPIO to set to output
+ * @value: initial output value of the GPIO
+ *
+ * Set the direction of the passed GPIO to output, such as gpiod_set_value() can
+ * be called safely on it. The initial value of the output must be specified
+ * as the logical value of the GPIO, i.e. taking its ACTIVE_LOW status into
+ * account.
+ *
+ * Return 0 in case of success, else an error code.
+ */
+int gpiod_direction_output(struct gpio_desc *desc, int value)
+{
+ if (!desc || !desc->chip) {
+ pr_warn("%s: invalid GPIO\n", __func__);
+ return -EINVAL;
+ }
+ if (test_bit(FLAG_ACTIVE_LOW, &desc->flags))
+ value = !value;
+ return _gpiod_direction_output_raw(desc, value);
+}
EXPORT_SYMBOL_GPL(gpiod_direction_output);
/**
@@ -1928,15 +2222,15 @@
* that the GPIO was actually requested.
*/
-static int _gpiod_get_raw_value(const struct gpio_desc *desc)
+static bool _gpiod_get_raw_value(const struct gpio_desc *desc)
{
struct gpio_chip *chip;
- int value;
+ bool value;
int offset;
chip = desc->chip;
offset = gpio_chip_hwgpio(desc);
- value = chip->get ? chip->get(chip, offset) : 0;
+ value = chip->get ? chip->get(chip, offset) : false;
trace_gpio_value(desc_to_gpio(desc), 1, value);
return value;
}
@@ -1992,7 +2286,7 @@
* @desc: gpio descriptor whose state need to be set.
* @value: Non-zero for setting it HIGH otherise it will set to LOW.
*/
-static void _gpio_set_open_drain_value(struct gpio_desc *desc, int value)
+static void _gpio_set_open_drain_value(struct gpio_desc *desc, bool value)
{
int err = 0;
struct gpio_chip *chip = desc->chip;
@@ -2019,7 +2313,7 @@
* @desc: gpio descriptor whose state need to be set.
* @value: Non-zero for setting it HIGH otherise it will set to LOW.
*/
-static void _gpio_set_open_source_value(struct gpio_desc *desc, int value)
+static void _gpio_set_open_source_value(struct gpio_desc *desc, bool value)
{
int err = 0;
struct gpio_chip *chip = desc->chip;
@@ -2041,7 +2335,7 @@
__func__, err);
}
-static void _gpiod_set_raw_value(struct gpio_desc *desc, int value)
+static void _gpiod_set_raw_value(struct gpio_desc *desc, bool value)
{
struct gpio_chip *chip;
@@ -2137,10 +2431,7 @@
* @gpio: the GPIO line to lock as used for IRQ
*
* This is used directly by GPIO drivers that want to lock down
- * a certain GPIO line to be used as IRQs, for example in the
- * .to_irq() callback of their gpio_chip, or in the .irq_enable()
- * of its irq_chip implementation if the GPIO is known from that
- * code.
+ * a certain GPIO line to be used for IRQs.
*/
int gpiod_lock_as_irq(struct gpio_desc *desc)
{
@@ -2161,7 +2452,7 @@
int gpio_lock_as_irq(struct gpio_chip *chip, unsigned int offset)
{
- return gpiod_lock_as_irq(gpiochip_offset_to_desc(chip, offset));
+ return gpiod_lock_as_irq(gpiochip_get_desc(chip, offset));
}
EXPORT_SYMBOL_GPL(gpio_lock_as_irq);
@@ -2183,7 +2474,7 @@
void gpio_unlock_as_irq(struct gpio_chip *chip, unsigned int offset)
{
- return gpiod_unlock_as_irq(gpiochip_offset_to_desc(chip, offset));
+ return gpiod_unlock_as_irq(gpiochip_get_desc(chip, offset));
}
EXPORT_SYMBOL_GPL(gpio_unlock_as_irq);
@@ -2284,22 +2575,27 @@
mutex_unlock(&gpio_lookup_lock);
}
-#ifdef CONFIG_OF
static struct gpio_desc *of_find_gpio(struct device *dev, const char *con_id,
unsigned int idx,
enum gpio_lookup_flags *flags)
{
+ static const char *suffixes[] = { "gpios", "gpio" };
char prop_name[32]; /* 32 is max size of property name */
enum of_gpio_flags of_flags;
struct gpio_desc *desc;
+ unsigned int i;
- if (con_id)
- snprintf(prop_name, 32, "%s-gpios", con_id);
- else
- snprintf(prop_name, 32, "gpios");
+ for (i = 0; i < ARRAY_SIZE(suffixes); i++) {
+ if (con_id)
+ snprintf(prop_name, 32, "%s-%s", con_id, suffixes[i]);
+ else
+ snprintf(prop_name, 32, "%s", suffixes[i]);
- desc = of_get_named_gpiod_flags(dev->of_node, prop_name, idx,
- &of_flags);
+ desc = of_get_named_gpiod_flags(dev->of_node, prop_name, idx,
+ &of_flags);
+ if (!IS_ERR(desc) || (PTR_ERR(desc) == -EPROBE_DEFER))
+ break;
+ }
if (IS_ERR(desc))
return desc;
@@ -2309,14 +2605,6 @@
return desc;
}
-#else
-static struct gpio_desc *of_find_gpio(struct device *dev, const char *con_id,
- unsigned int idx,
- enum gpio_lookup_flags *flags)
-{
- return ERR_PTR(-ENODEV);
-}
-#endif
static struct gpio_desc *acpi_find_gpio(struct device *dev, const char *con_id,
unsigned int idx,
@@ -2404,7 +2692,7 @@
return ERR_PTR(-EINVAL);
}
- desc = gpiochip_offset_to_desc(chip, p->chip_hwnum);
+ desc = gpiochip_get_desc(chip, p->chip_hwnum);
*flags = p->flags;
return desc;
@@ -2414,7 +2702,7 @@
}
/**
- * gpio_get - obtain a GPIO for a given GPIO function
+ * gpiod_get - obtain a GPIO for a given GPIO function
* @dev: GPIO consumer, can be NULL for system-global GPIOs
* @con_id: function within the GPIO consumer
*
diff --git a/drivers/gpio/gpiolib.h b/drivers/gpio/gpiolib.h
index 82be586..cf09294 100644
--- a/drivers/gpio/gpiolib.h
+++ b/drivers/gpio/gpiolib.h
@@ -43,4 +43,7 @@
}
#endif
+int gpiochip_request_own_desc(struct gpio_desc *desc, const char *label);
+void gpiochip_free_own_desc(struct gpio_desc *desc);
+
#endif /* GPIOLIB_H */
diff --git a/drivers/hwmon/lm75.c b/drivers/hwmon/lm75.c
index 84a55ea..7b06712 100644
--- a/drivers/hwmon/lm75.c
+++ b/drivers/hwmon/lm75.c
@@ -177,6 +177,10 @@
.attrs = lm75_attributes,
};
+static const struct thermal_zone_of_device_ops lm75_of_thermal_ops = {
+ .get_temp = lm75_read_temp,
+};
+
/*-----------------------------------------------------------------------*/
/* device probe and removal */
@@ -290,10 +294,9 @@
goto exit_remove;
}
- data->tz = thermal_zone_of_sensor_register(&client->dev,
- 0,
+ data->tz = thermal_zone_of_sensor_register(&client->dev, 0,
&client->dev,
- lm75_read_temp, NULL);
+ &lm75_of_thermal_ops);
if (IS_ERR(data->tz))
data->tz = NULL;
diff --git a/drivers/hwmon/tmp102.c b/drivers/hwmon/tmp102.c
index 6748b45..0f09271 100644
--- a/drivers/hwmon/tmp102.c
+++ b/drivers/hwmon/tmp102.c
@@ -159,6 +159,10 @@
#define TMP102_CONFIG (TMP102_CONF_TM | TMP102_CONF_EM | TMP102_CONF_CR1)
#define TMP102_CONFIG_RD_ONLY (TMP102_CONF_R0 | TMP102_CONF_R1 | TMP102_CONF_AL)
+static const struct thermal_zone_of_device_ops tmp102_of_thermal_ops = {
+ .get_temp = tmp102_read_temp,
+};
+
static int tmp102_probe(struct i2c_client *client,
const struct i2c_device_id *id)
{
@@ -218,7 +222,7 @@
tmp102->tz = thermal_zone_of_sensor_register(&client->dev, 0,
&client->dev,
- tmp102_read_temp, NULL);
+ &tmp102_of_thermal_ops);
if (IS_ERR(tmp102->tz))
tmp102->tz = NULL;
diff --git a/drivers/mmc/core/core.c b/drivers/mmc/core/core.c
index 098374b..d56c12d 100644
--- a/drivers/mmc/core/core.c
+++ b/drivers/mmc/core/core.c
@@ -2582,12 +2582,8 @@
*/
int mmc_flush_cache(struct mmc_card *card)
{
- struct mmc_host *host = card->host;
int err = 0;
- if (!(host->caps2 & MMC_CAP2_CACHE_CTRL))
- return err;
-
if (mmc_card_mmc(card) &&
(card->ext_csd.cache_size > 0) &&
(card->ext_csd.cache_ctrl & 1)) {
@@ -2614,8 +2610,7 @@
unsigned int timeout;
int err = 0;
- if (!(host->caps2 & MMC_CAP2_CACHE_CTRL) ||
- mmc_card_is_removable(host))
+ if (mmc_card_is_removable(host))
return err;
if (card && mmc_card_mmc(card) &&
diff --git a/drivers/mmc/core/mmc.c b/drivers/mmc/core/mmc.c
index 98e9eb0..7bbfbc7 100644
--- a/drivers/mmc/core/mmc.c
+++ b/drivers/mmc/core/mmc.c
@@ -1287,8 +1287,7 @@
* If cache size is higher than 0, this indicates
* the existence of cache and it can be turned on.
*/
- if ((host->caps2 & MMC_CAP2_CACHE_CTRL) &&
- card->ext_csd.cache_size > 0) {
+ if (card->ext_csd.cache_size > 0) {
err = mmc_switch(card, EXT_CSD_CMD_SET_NORMAL,
EXT_CSD_CACHE_CTRL, 1,
card->ext_csd.generic_cmd6_time);
diff --git a/drivers/mmc/host/sdhci-brcmstb.c b/drivers/mmc/host/sdhci-brcmstb.c
index 97d9107..e1ffd45 100644
--- a/drivers/mmc/host/sdhci-brcmstb.c
+++ b/drivers/mmc/host/sdhci-brcmstb.c
@@ -31,7 +31,7 @@
#define SDIO_CFG_REG(x, y) (x + BCHP_SDIO_0_CFG_##y - \
BCHP_SDIO_0_CFG_REG_START)
-#if defined(CONFIG_BCM7439A0) || defined(CONFIG_BCM74371A0)
+#if defined(CONFIG_BCM74371A0)
/*
* HW7445-1183
* Setting the RESET_ALL or RESET_DATA bits will hang the SDIO
@@ -57,8 +57,7 @@
#if defined(CONFIG_BCM3390A0) || defined(CONFIG_BCM7145B0) || \
defined(CONFIG_BCM7250B0) || defined(CONFIG_BCM7364A0) || \
- defined(CONFIG_BCM7366B0) || defined(CONFIG_BCM7439B0) || \
- defined(CONFIG_BCM7445D0)
+ defined(CONFIG_BCM7439B0) || defined(CONFIG_BCM7445D0)
static int sdhci_override_caps(struct platform_device *pdev,
uint32_t cap0_setbits,
uint32_t cap0_clearbits,
@@ -155,7 +154,7 @@
goto undo_clk_get;
/* Only enable reset workaround for 7439a0 and 74371a0 senior */
-#if defined(CONFIG_BCM7439A0) || defined(CONFIG_BCM74371A0)
+#if defined(CONFIG_BCM74371A0)
if (BRCM_CHIP_ID() == 0x7439)
sdhci_brcmstb_pdata.ops = &sdhci_brcmstb_ops;
#endif
diff --git a/drivers/mtd/devices/m25p80.c b/drivers/mtd/devices/m25p80.c
index ad19139..bdac757 100644
--- a/drivers/mtd/devices/m25p80.c
+++ b/drivers/mtd/devices/m25p80.c
@@ -50,6 +50,7 @@
#define OPCODE_SE 0xd8 /* Sector erase (usually 64KiB) */
#define OPCODE_RDID 0x9f /* Read JEDEC ID */
#define OPCODE_RDCR 0x35 /* Read configuration register */
+#define OPCODE_RDFSR 0x70 /* Read flag status register */
/* 4-byte address opcodes - used on Spansion and some Macronix flashes. */
#define OPCODE_NORM_READ_4B 0x13 /* Read data bytes (low frequency) */
@@ -81,6 +82,9 @@
#define SR_QUAD_EN_MX 0x40 /* Macronix Quad I/O */
+/* Flag Status Register bits */
+#define FSR_READY 0x80
+
/* Configuration Register bits. */
#define CR_QUAD_EN_SPAN 0x2 /* Spansion Quad I/O */
@@ -98,6 +102,10 @@
M25P80_QUAD,
};
+enum m25p_option_flags {
+ M25P_F_USE_FSR = BIT(0),
+};
+
struct m25p {
struct spi_device *spi;
struct mutex lock;
@@ -109,6 +117,8 @@
u8 program_opcode;
u8 *command;
enum read_type flash_read;
+
+ u32 flags;
};
static inline struct m25p *mtd_to_m25p(struct mtd_info *mtd)
@@ -145,6 +155,26 @@
}
/*
+ * Read the flag status register, returning its value in the location
+ * Return the status register value.
+ * Returns negative if error occurred.
+ */
+static int read_fsr(struct m25p *flash)
+{
+ ssize_t ret;
+ u8 code = OPCODE_RDFSR;
+ u8 val;
+
+ ret = spi_write_then_read(flash->spi, &code, 1, &val, 1);
+ if (ret < 0) {
+ dev_err(&flash->spi->dev, "error %d reading FSR\n", (int)ret);
+ return ret;
+ }
+
+ return val;
+}
+
+/*
* Read configuration register, returning its value in the
* location. Return the configuration register value.
* Returns negative if error occured.
@@ -233,7 +263,7 @@
* Service routine to read status register until ready, or timeout occurs.
* Returns non-zero if error.
*/
-static int wait_till_ready(struct m25p *flash)
+static int wait_till_sr_ready(struct m25p *flash)
{
unsigned long deadline;
int sr;
@@ -253,6 +283,40 @@
return 1;
}
+static int wait_till_fsr_ready(struct m25p *flash)
+{
+ unsigned long deadline;
+ int sr;
+ int fsr;
+
+ deadline = jiffies + MAX_READY_WAIT_JIFFIES;
+
+ do {
+ cond_resched();
+
+ sr = read_sr(flash);
+ if (sr < 0) {
+ break;
+ } else if (!(sr & SR_WIP)) {
+ fsr = read_fsr(flash);
+ if (fsr < 0)
+ break;
+ if (fsr & FSR_READY)
+ return 0;
+ }
+ } while (!time_after_eq(jiffies, deadline));
+
+ return -ETIMEDOUT;
+}
+
+static int wait_till_ready(struct m25p *flash)
+{
+ if (flash->flags & M25P_F_USE_FSR)
+ return wait_till_fsr_ready(flash);
+ else
+ return wait_till_sr_ready(flash);
+}
+
/*
* Write status Register and configuration register with 2 bytes
* The first byte will be written to the status register, while the
@@ -856,6 +920,7 @@
#define M25P_NO_FR 0x08 /* Can't do fastread */
#define SECT_4K_PMC 0x10 /* OPCODE_BE_4K_PMC works uniformly */
#define M25P80_QUAD_READ 0x20 /* Flash supports Quad Read */
+#define USE_FSR 0x80 /* use flag status register */
};
#define INFO(_jedec_id, _ext_id, _sector_size, _n_sectors, _flags) \
@@ -941,6 +1006,8 @@
{ "n25q128a13", INFO(0x20ba18, 0, 64 * 1024, 256, 0) },
{ "n25q256a", INFO(0x20ba19, 0, 64 * 1024, 512, SECT_4K) },
{ "n25q512a", INFO(0x20bb20, 0, 64 * 1024, 1024, SECT_4K) },
+ { "n25q512ax3", INFO(0x20ba20, 0, 64 * 1024, 1024, USE_FSR) },
+ { "n25q00", INFO(0x20ba21, 0, 64 * 1024, 2048, USE_FSR) },
/* PMC */
{ "pm25lv512", INFO(0, 0, 32 * 1024, 2, SECT_4K_PMC) },
@@ -1191,6 +1258,9 @@
else
flash->mtd._write = m25p80_write;
+ if ((info->flags & USE_FSR))
+ flash->flags |= M25P_F_USE_FSR;
+
/* prefer "small sector" erase if possible */
if (info->flags & SECT_4K) {
flash->erase_opcode = OPCODE_BE_4K;
diff --git a/drivers/mtd/nand/brcmstb_nand.c b/drivers/mtd/nand/brcmstb_nand.c
index 623ba67..1e8cb25 100644
--- a/drivers/mtd/nand/brcmstb_nand.c
+++ b/drivers/mtd/nand/brcmstb_nand.c
@@ -53,16 +53,6 @@
static int wp_on = 1;
module_param(wp_on, int, 0444);
-/* SWLINUX-2527: support a workaround for bugs filed in, e.g., HW7445-988 */
-#if defined(CONFIG_BCM7145A0)
-#define HW7445_988_WORKAROUND
-#endif
-
-/* CRNAND-34: FLASH DMA must use 512B transfer sizes */
-#define CRNAND_34_WORKAROUND() IS_ENABLED(CONFIG_BCM7439A0)
-
-#define CRNAND_34_STEPSIZE 512
-
/***********************************************************************
* Definitions
***********************************************************************/
@@ -240,8 +230,7 @@
/* List of NAND hosts (one for each chip-select) */
struct list_head host_list;
- struct brcm_nand_dma_desc *dma_descs;
- unsigned int num_dma_descs;
+ struct brcm_nand_dma_desc *dma_desc;
dma_addr_t dma_pa;
/* in-memory cache of the FLASH_CACHE, used only for some commands */
@@ -251,11 +240,6 @@
u32 nand_cs_nand_xor;
u32 corr_stat_threshold;
u32 flash_dma_mode;
-
-#ifdef HW7445_988_WORKAROUND
- /* HW7445-988: need to skip some interrupts for PROGRAM_PAGE */
- int skip_irq;
-#endif
};
struct brcmstb_nand_cfg {
@@ -631,13 +615,6 @@
if (ctrl->dma_pending)
return IRQ_HANDLED;
-#ifdef HW7445_988_WORKAROUND
- /* HW7445-988: ignore certain interrupts */
- if (ctrl->skip_irq > 0) {
- ctrl->skip_irq--;
- return IRQ_HANDLED;
- }
-#endif
complete(&ctrl->done);
return IRQ_HANDLED;
}
@@ -710,10 +687,6 @@
BDEV_RD(BCHP_HIF_INTR2_CPU_STATUS),
BDEV_RD(BCHP_NAND_INTFC_STATUS));
}
-#ifdef HW7445_988_WORKAROUND
- /* HW7445-988: if we timed out, stop skipping interrupts */
- ctrl->skip_irq = 0;
-#endif
ctrl->cmd_pending = 0;
return BDEV_RD_F(NAND_INTFC_STATUS, FLASH_STATUS);
}
@@ -998,33 +971,20 @@
struct brcmstb_nand_controller *ctrl = host->ctrl;
dma_addr_t buf_pa;
int dir = dma_cmd == CMD_PAGE_READ ? DMA_FROM_DEVICE : DMA_TO_DEVICE;
- int step = len, offs, i;
buf_pa = dma_map_single(&host->pdev->dev, buf, len, dir);
- /* CRNAND-34: DMA reads must be split into fine-grained linked-lists */
- if (CRNAND_34_WORKAROUND())
- step = CRNAND_34_STEPSIZE;
+ brcmstb_nand_fill_dma_desc(host, ctrl->dma_desc, addr, buf_pa, len,
+ dma_cmd, true, true, 0);
- for (offs = 0, i = 0; offs < len; offs += step, i++) {
- bool begin = offs == 0;
- bool end = (offs + step) >= len;
- brcmstb_nand_fill_dma_desc(host, &ctrl->dma_descs[i],
- addr + offs, buf_pa + offs, step, dma_cmd,
- begin, end, end ? 0 : flash_dma_get_desc_pa(ctrl, i + 1));
- }
-
- BUG_ON(i > (int)ctrl->num_dma_descs);
-
- brcmstb_nand_dma_run(host, flash_dma_get_desc_pa(ctrl, 0));
+ brcmstb_nand_dma_run(host, ctrl->dma_pa);
dma_unmap_single(&host->pdev->dev, buf_pa, len, dir);
- for (offs = 0, i = 0; offs < len; offs += step, i++)
- if (ctrl->dma_descs[i].status_valid & FLASH_DMA_ECC_ERROR)
- return -EBADMSG;
- else if (ctrl->dma_descs[i].status_valid & FLASH_DMA_CORR_ERROR)
- return -EUCLEAN;
+ if (ctrl->dma_desc->status_valid & FLASH_DMA_ECC_ERROR)
+ return -EBADMSG;
+ else if (ctrl->dma_desc->status_valid & FLASH_DMA_CORR_ERROR)
+ return -EUCLEAN;
return 0;
}
@@ -1293,8 +1253,6 @@
(host->cs << 16) | ((addr >> 32) & 0xffff));
for (i = 0; i < trans; i++, addr += FC_BYTES) {
- int cmd = CMD_PROGRAM_PAGE;
-
/* full address MUST be set before populating FC */
BDEV_WR_RB(BCHP_NAND_CMD_ADDRESS, addr & 0xffffffff);
@@ -1310,29 +1268,8 @@
host->hwcfg.sector_size_1k);
}
-#ifdef HW7445_988_WORKAROUND
- /*
- * HW7445-988: when programming with SECTOR_SIZE_1K=1, just use
- * PROGRAM_SPARE_AREA for every other 512B -- to fill
- * the spare area without triggering the ping-pong IRQ bug
- */
- if (host->hwcfg.sector_size_1k && !(i & 0x01)) {
- cmd = CMD_PROGRAM_SPARE_AREA;
- } else {
- cmd = CMD_PROGRAM_PAGE;
-
- /*
- * HW7445-988: for PROGRAM_PAGE (all sector sizes)
- * ignore the first interrupt except for the last
- * sector
- */
- if ((i + 1) != trans)
- ctrl->skip_irq = 1;
- }
-#endif
-
/* we cannot use SPARE_AREA_PROGRAM when PARTIAL_PAGE_EN=0 */
- brcmstb_nand_send_cmd(host, cmd);
+ brcmstb_nand_send_cmd(host, CMD_PROGRAM_PAGE);
status = brcmstb_nand_waitfunc(mtd, chip);
if (status & NAND_STATUS_FAIL) {
@@ -1833,30 +1770,6 @@
* Platform driver setup (per controller)
***********************************************************************/
-/**
- * Allocate one or more FLASH_DMA descriptors
- */
-static int brcmstb_nand_alloc_dma_descrs(struct device *dev,
- struct brcmstb_nand_controller *ctrl, unsigned int num_descs)
-{
- struct brcm_nand_dma_desc *descs;
- dma_addr_t pa;
-
- if (num_descs == 0)
- return -EINVAL;
-
- descs = dmam_alloc_coherent(dev, num_descs * sizeof(*descs), &pa,
- GFP_KERNEL);
- if (!descs)
- return -ENOMEM;
-
- ctrl->dma_descs = descs;
- ctrl->num_dma_descs = num_descs;
- ctrl->dma_pa = pa;
-
- return 0;
-}
-
static int brcmstb_nand_check_irq_cascade(struct device *dev,
struct brcmstb_nand_controller *ctrl)
{
@@ -1928,8 +1841,6 @@
/* FLASH_DMA */
res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "flash-dma");
if (res) {
- int count;
-
ctrl->flash_dma_base = devm_request_and_ioremap(dev, res);
if (!ctrl->flash_dma_base)
return -ENODEV;
@@ -1937,15 +1848,12 @@
flash_dma_writel(ctrl, FLASH_DMA_MODE, 1); /* linked-list */
flash_dma_writel(ctrl, FLASH_DMA_ERROR_STATUS, 0);
- if (CRNAND_34_WORKAROUND())
- count = NAND_MAX_PAGESIZE / CRNAND_34_STEPSIZE;
- else
- count = 1;
-
/* Allocate descriptor(s) */
- ret = brcmstb_nand_alloc_dma_descrs(dev, ctrl, count);
- if (ret)
- return ret;
+ ctrl->dma_desc = dmam_alloc_coherent(dev,
+ sizeof(*ctrl->dma_desc),
+ &ctrl->dma_pa, GFP_KERNEL);
+ if (!ctrl->dma_desc)
+ return -ENOMEM;
if (ctrl->irq_cascaded) {
ctrl->dma_irq = platform_get_irq(pdev, 1);
diff --git a/drivers/net/dsa/bcm_sf2.c b/drivers/net/dsa/bcm_sf2.c
index 6b64e47..87d49f2 100644
--- a/drivers/net/dsa/bcm_sf2.c
+++ b/drivers/net/dsa/bcm_sf2.c
@@ -24,6 +24,8 @@
#include <linux/of_address.h>
#include <net/dsa.h>
#include <linux/ethtool.h>
+#include <linux/if_bridge.h>
+#include <linux/brcmphy.h>
#include "bcm_sf2.h"
#include "bcm_sf2_regs.h"
@@ -349,10 +351,14 @@
if (port == 7)
intrl2_1_mask_clear(priv, P_IRQ_MASK(P7_IRQ_OFF));
- /* Set this port, and only this one to be in the default VLAN */
+ /* Set this port, and only this one to be in the default VLAN,
+ * if member of a bridge, restore its membership prior to
+ * bringing down this port.
+ */
reg = core_readl(priv, CORE_PORT_VLAN_CTL_PORT(port));
reg &= ~PORT_VLAN_CTRL_MASK;
reg |= (1 << port);
+ reg |= priv->port_sts[port].vlan_ctl_mask;
core_writel(priv, reg, CORE_PORT_VLAN_CTL_PORT(port));
bcm_sf2_imp_vlan_setup(ds, cpu_port);
@@ -455,6 +461,145 @@
return 0;
}
+/* Fast-ageing of ARL entries for a given port, equivalent to an ARL
+ * flush for that port.
+ */
+static int bcm_sf2_sw_fast_age_port(struct dsa_switch *ds, int port)
+{
+ struct bcm_sf2_priv *priv = ds_to_priv(ds);
+ unsigned int timeout = 1000;
+ u32 reg;
+
+ core_writel(priv, port, CORE_FAST_AGE_PORT);
+
+ reg = core_readl(priv, CORE_FAST_AGE_CTRL);
+ reg |= EN_AGE_PORT | FAST_AGE_STR_DONE;
+ core_writel(priv, reg, CORE_FAST_AGE_CTRL);
+
+ do {
+ reg = core_readl(priv, CORE_FAST_AGE_CTRL);
+ if (!(reg & FAST_AGE_STR_DONE))
+ break;
+
+ cpu_relax();
+ } while (timeout--);
+
+ if (!timeout)
+ return -ETIMEDOUT;
+
+ return 0;
+}
+
+static void bcm_sf2_sw_br_join(struct dsa_switch *ds, int port,
+ u32 br_port_mask)
+{
+ struct bcm_sf2_priv *priv = ds_to_priv(ds);
+ unsigned int i;
+ u32 reg, p_ctl;
+
+ p_ctl = core_readl(priv, CORE_PORT_VLAN_CTL_PORT(port));
+
+ for (i = 0; i < priv->hw_params.num_ports; i++) {
+ if (!((1 << i) & br_port_mask))
+ continue;
+
+ /* Add this local port to the remote port VLAN control
+ * membership and update the remote port bitmask
+ */
+ reg = core_readl(priv, CORE_PORT_VLAN_CTL_PORT(i));
+ reg |= 1 << port;
+ core_writel(priv, reg, CORE_PORT_VLAN_CTL_PORT(i));
+ priv->port_sts[i].vlan_ctl_mask = reg;
+
+ p_ctl |= 1 << i;
+ }
+
+ /* Configure the local port VLAN control membership to include
+ * remote ports and update the local port bitmask
+ */
+ core_writel(priv, p_ctl, CORE_PORT_VLAN_CTL_PORT(port));
+ priv->port_sts[port].vlan_ctl_mask = p_ctl;
+}
+
+static void bcm_sf2_sw_br_leave(struct dsa_switch *ds, int port,
+ u32 br_port_mask)
+{
+ struct bcm_sf2_priv *priv = ds_to_priv(ds);
+ unsigned int i;
+ u32 reg, p_ctl;
+
+ p_ctl = core_readl(priv, CORE_PORT_VLAN_CTL_PORT(port));
+
+ for (i = 0; i < priv->hw_params.num_ports; i++) {
+ /* Don't touch the remaining ports */
+ if (!((1 << i) & br_port_mask))
+ continue;
+
+ reg = core_readl(priv, CORE_PORT_VLAN_CTL_PORT(i));
+ reg &= ~(1 << port);
+ core_writel(priv, reg, CORE_PORT_VLAN_CTL_PORT(i));
+ priv->port_sts[port].vlan_ctl_mask = reg;
+
+ /* Prevent self removal to preserve isolation */
+ if (port != i)
+ p_ctl &= ~(1 << i);
+ }
+
+ core_writel(priv, p_ctl, CORE_PORT_VLAN_CTL_PORT(port));
+ priv->port_sts[port].vlan_ctl_mask = p_ctl;
+}
+
+static void bcm_sf2_sw_br_set_stp_state(struct dsa_switch *ds, int port,
+ unsigned int state)
+{
+ struct bcm_sf2_priv *priv = ds_to_priv(ds);
+ u8 hw_state, cur_hw_state;
+ int ret = 0;
+ u32 reg;
+
+ reg = core_readl(priv, CORE_G_PCTL_PORT(port));
+ cur_hw_state = reg >> G_MISTP_STATE_SHIFT;
+
+ switch (state) {
+ case BR_STATE_DISABLED:
+ hw_state = G_MISTP_DIS_STATE;
+ break;
+ case BR_STATE_LISTENING:
+ hw_state = G_MISTP_LISTEN_STATE;
+ break;
+ case BR_STATE_LEARNING:
+ hw_state = G_MISTP_LEARN_STATE;
+ break;
+ case BR_STATE_FORWARDING:
+ hw_state = G_MISTP_FWD_STATE;
+ break;
+ case BR_STATE_BLOCKING:
+ hw_state = G_MISTP_BLOCK_STATE;
+ break;
+ default:
+ pr_err("%s: invalid STP state: %d\n", __func__, state);
+ return;
+ }
+
+ /* Fast-age ARL entries if we are moving a port from Learning or
+ * Forwarding state to Disabled, Blocking or Listening state
+ */
+ if (cur_hw_state != hw_state) {
+ if (cur_hw_state & 4 && !(hw_state & 4)) {
+ ret = bcm_sf2_sw_fast_age_port(ds, port);
+ if (ret) {
+ pr_err("%s: fast-ageing failed\n", __func__);
+ return;
+ }
+ }
+ }
+
+ reg = core_readl(priv, CORE_G_PCTL_PORT(port));
+ reg &= ~(G_MISTP_STATE_MASK << G_MISTP_STATE_SHIFT);
+ reg |= hw_state;
+ core_writel(priv, reg, CORE_G_PCTL_PORT(port));
+}
+
static irqreturn_t bcm_sf2_switch_0_isr(int irq, void *dev_id)
{
struct bcm_sf2_priv *priv = dev_id;
@@ -610,9 +755,20 @@
}
/* Include the pseudo-PHY address and the broadcast PHY address to
- * divert reads towards our workaround
+ * divert reads towards our workaround. This is only required for
+ * 7445D0, since 7445E0 disconnects the internal switch pseudo-PHY such
+ * that we can use the regular SWITCH_MDIO master controller instead.
+ *
+ * By default, DSA initializes ds->phys_mii_mask to ds->phys_port_mask
+ * to have a 1:1 mapping between Port address and PHY address in order
+ * to utilize the slave_mii_bus instance to read from Port PHYs. This is
+ * not what we want here, so we initialize phys_mii_mask 0 to always
+ * utilize the "master" MDIO bus backed by "mdio-unimac".
*/
- ds->phys_mii_mask |= ((1 << 30) | (1 << 0));
+ if (of_machine_is_compatible("brcm,bcm7445d0"))
+ ds->phys_mii_mask |= ((1 << BRCM_PSEUDO_PHY_ADDR) | (1 << 0));
+ else
+ ds->phys_mii_mask = 0;
rev = reg_readl(priv, REG_SWITCH_REVISION);
priv->hw_params.top_rev = (rev >> SWITCH_TOP_REV_SHIFT) &
@@ -700,7 +856,7 @@
*/
switch (addr) {
case 0:
- case 30:
+ case BRCM_PSEUDO_PHY_ADDR:
return bcm_sf2_sw_indir_rw(ds, 1, addr, regnum, 0);
default:
return 0xffff;
@@ -715,7 +871,7 @@
*/
switch (addr) {
case 0:
- case 30:
+ case BRCM_PSEUDO_PHY_ADDR:
bcm_sf2_sw_indir_rw(ds, 0, addr, regnum, val);
break;
}
@@ -829,6 +985,8 @@
*/
if (port == 7) {
status->link = priv->port_sts[port].link;
+ if (!status->link)
+ netif_carrier_off(ds->ports[port]);
status->duplex = 1;
} else {
status->link = 1;
@@ -995,6 +1153,9 @@
.port_disable = bcm_sf2_port_disable,
.get_eee = bcm_sf2_sw_get_eee,
.set_eee = bcm_sf2_sw_set_eee,
+ .br_join = bcm_sf2_sw_br_join,
+ .br_leave = bcm_sf2_sw_br_leave,
+ .br_set_stp_state = bcm_sf2_sw_br_set_stp_state,
};
static int __init bcm_sf2_init(void)
diff --git a/drivers/net/dsa/bcm_sf2.h b/drivers/net/dsa/bcm_sf2.h
index 18caa88..a0f364d 100644
--- a/drivers/net/dsa/bcm_sf2.h
+++ b/drivers/net/dsa/bcm_sf2.h
@@ -47,6 +47,8 @@
bool enabled;
struct ethtool_eee eee;
+
+ u32 vlan_ctl_mask;
};
struct bcm_sf2_priv {
@@ -104,14 +106,21 @@
* using the REG_DIR_DATA_{READ,WRITE} ancillary registers. The 'indir_lock'
* spinlock is automatically grabbed and released to provide relative
* atomiticy with latched reads/writes.
+ *
+ * For reads, we first need to read the regular 32-bits register, and then
+ * issue a read to the REG_DIR_DATA_READ register and assemble the 64-bits
+ * quantity.
+ *
+ * For writes, it is the opposite, we need to write to REG_DIR_DATA_WRITE and
+ * then to the regular 32-bits register.
*/
#define SF2_IO64_MACRO(name) \
static inline u64 name##_readq(struct bcm_sf2_priv *priv, u32 off) \
{ \
u32 indir, dir; \
spin_lock(&priv->indir_lock); \
- indir = reg_readl(priv, REG_DIR_DATA_READ); \
dir = __raw_readl(priv->name + off); \
+ indir = reg_readl(priv, REG_DIR_DATA_READ); \
spin_unlock(&priv->indir_lock); \
return (u64)indir << 32 | dir; \
} \
diff --git a/drivers/net/dsa/bcm_sf2_regs.h b/drivers/net/dsa/bcm_sf2_regs.h
index 53e4f19..873fbd0 100644
--- a/drivers/net/dsa/bcm_sf2_regs.h
+++ b/drivers/net/dsa/bcm_sf2_regs.h
@@ -164,6 +164,21 @@
#define EN_CHIP_RST (1 << 6)
#define EN_SW_RESET (1 << 4)
+#define CORE_FAST_AGE_CTRL 0x00220
+#define EN_FAST_AGE_STATIC (1 << 0)
+#define EN_AGE_DYNAMIC (1 << 1)
+#define EN_AGE_PORT (1 << 2)
+#define EN_AGE_VLAN (1 << 3)
+#define EN_AGE_SPT (1 << 4)
+#define EN_AGE_MCAST (1 << 5)
+#define FAST_AGE_STR_DONE (1 << 7)
+
+#define CORE_FAST_AGE_PORT 0x00224
+#define AGE_PORT_MASK 0xf
+
+#define CORE_FAST_AGE_VID 0x00228
+#define AGE_VID_MASK 0x3fff
+
#define CORE_LNKSTS 0x00400
#define LNK_STS_MASK 0x1ff
diff --git a/drivers/net/ethernet/broadcom/bcmsysport.c b/drivers/net/ethernet/broadcom/bcmsysport.c
index c9d85e8..a876621 100644
--- a/drivers/net/ethernet/broadcom/bcmsysport.c
+++ b/drivers/net/ethernet/broadcom/bcmsysport.c
@@ -285,9 +285,9 @@
/* RBUF misc statistics */
STAT_RBUF("rbuf_ovflow_cnt", mib.rbuf_ovflow_cnt, RBUF_OVFL_DISC_CNTR),
STAT_RBUF("rbuf_err_cnt", mib.rbuf_err_cnt, RBUF_ERR_PKT_CNTR),
- STAT_MIB_RX("alloc_rx_buff_failed", mib.alloc_rx_buff_failed),
- STAT_MIB_RX("rx_dma_failed", mib.rx_dma_failed),
- STAT_MIB_TX("tx_dma_failed", mib.tx_dma_failed),
+ STAT_MIB_SOFT("alloc_rx_buff_failed", mib.alloc_rx_buff_failed),
+ STAT_MIB_SOFT("rx_dma_failed", mib.rx_dma_failed),
+ STAT_MIB_SOFT("tx_dma_failed", mib.tx_dma_failed),
};
#define BCM_SYSPORT_STATS_LEN ARRAY_SIZE(bcm_sysport_gstrings_stats)
@@ -356,6 +356,7 @@
s = &bcm_sysport_gstrings_stats[i];
switch (s->type) {
case BCM_SYSPORT_STAT_NETDEV:
+ case BCM_SYSPORT_STAT_SOFT:
continue;
case BCM_SYSPORT_STAT_MIB_RX:
case BCM_SYSPORT_STAT_MIB_TX:
@@ -467,6 +468,67 @@
return 0;
}
+static int bcm_sysport_get_coalesce(struct net_device *dev,
+ struct ethtool_coalesce *ec)
+{
+ struct bcm_sysport_priv *priv = netdev_priv(dev);
+ u32 reg;
+
+ reg = tdma_readl(priv, TDMA_DESC_RING_INTR_CONTROL(0));
+
+ ec->tx_coalesce_usecs = (reg >> RING_TIMEOUT_SHIFT) * 8192 / 1000;
+ ec->tx_max_coalesced_frames = reg & RING_INTR_THRESH_MASK;
+
+ reg = rdma_readl(priv, RDMA_MBDONE_INTR);
+
+ ec->rx_coalesce_usecs = (reg >> RDMA_TIMEOUT_SHIFT) * 8192 / 1000;
+ ec->rx_max_coalesced_frames = reg & RDMA_INTR_THRESH_MASK;
+
+ return 0;
+}
+
+static int bcm_sysport_set_coalesce(struct net_device *dev,
+ struct ethtool_coalesce *ec)
+{
+ struct bcm_sysport_priv *priv = netdev_priv(dev);
+ unsigned int i;
+ u32 reg;
+
+ /* Base system clock is 125Mhz, DMA timeout is this reference clock
+ * divided by 1024, which yield roughly 8.192 us, our maximum value has
+ * to fit in the RING_TIMEOUT_MASK (16 bits).
+ */
+ if (ec->tx_max_coalesced_frames > RING_INTR_THRESH_MASK ||
+ ec->tx_coalesce_usecs > (RING_TIMEOUT_MASK * 8) + 1 ||
+ ec->rx_max_coalesced_frames > RDMA_INTR_THRESH_MASK ||
+ ec->rx_coalesce_usecs > (RDMA_TIMEOUT_MASK * 8) + 1)
+ return -EINVAL;
+
+ if ((ec->tx_coalesce_usecs == 0 && ec->tx_max_coalesced_frames == 0) ||
+ (ec->rx_coalesce_usecs == 0 && ec->rx_max_coalesced_frames == 0))
+ return -EINVAL;
+
+ for (i = 0; i < dev->num_tx_queues; i++) {
+ reg = tdma_readl(priv, TDMA_DESC_RING_INTR_CONTROL(i));
+ reg &= ~(RING_INTR_THRESH_MASK |
+ RING_TIMEOUT_MASK << RING_TIMEOUT_SHIFT);
+ reg |= ec->tx_max_coalesced_frames;
+ reg |= DIV_ROUND_UP(ec->tx_coalesce_usecs * 1000, 8192) <<
+ RING_TIMEOUT_SHIFT;
+ tdma_writel(priv, reg, TDMA_DESC_RING_INTR_CONTROL(i));
+ }
+
+ reg = rdma_readl(priv, RDMA_MBDONE_INTR);
+ reg &= ~(RDMA_INTR_THRESH_MASK |
+ RDMA_TIMEOUT_MASK << RDMA_TIMEOUT_SHIFT);
+ reg |= ec->rx_max_coalesced_frames;
+ reg |= DIV_ROUND_UP(ec->rx_coalesce_usecs * 1000, 8192) <<
+ RDMA_TIMEOUT_SHIFT;
+ rdma_writel(priv, reg, RDMA_MBDONE_INTR);
+
+ return 0;
+}
+
static void bcm_sysport_free_cb(struct bcm_sysport_cb *cb)
{
dev_kfree_skb_any(cb->skb);
@@ -499,12 +561,7 @@
}
dma_unmap_addr_set(cb, dma_addr, mapping);
- dma_desc_set_addr(priv, priv->rx_bd_assign_ptr, mapping);
-
- priv->rx_bd_assign_index++;
- priv->rx_bd_assign_index &= (priv->num_rx_bds - 1);
- priv->rx_bd_assign_ptr = priv->rx_bds +
- (priv->rx_bd_assign_index * DESC_SIZE);
+ dma_desc_set_addr(priv, cb->bd_addr, mapping);
netif_dbg(priv, rx_status, ndev, "RX refill\n");
@@ -518,7 +575,7 @@
unsigned int i;
for (i = 0; i < priv->num_rx_bds; i++) {
- cb = &priv->rx_cbs[priv->rx_bd_assign_index];
+ cb = &priv->rx_cbs[i];
if (cb->skb)
continue;
@@ -595,6 +652,14 @@
p_index, priv->rx_c_index, priv->rx_read_ptr,
len, status);
+ if (unlikely(len > RX_BUF_LENGTH)) {
+ netif_err(priv, rx_status, ndev, "oversized packet\n");
+ ndev->stats.rx_over_errors++;
+ ndev->stats.rx_errors++;
+ dev_kfree_skb_any(skb);
+ goto refill;
+ }
+
if (unlikely(!(status & DESC_EOP) || !(status & DESC_SOP))) {
netif_err(priv, rx_status, ndev, "fragmented packet!\n");
ndev->stats.rx_dropped++;
@@ -1249,14 +1314,14 @@
static int bcm_sysport_init_rx_ring(struct bcm_sysport_priv *priv)
{
+ struct bcm_sysport_cb *cb;
u32 reg;
int ret;
+ int i;
/* Initialize SW view of the RX ring */
priv->num_rx_bds = NUM_RX_DESC;
priv->rx_bds = priv->base + SYS_PORT_RDMA_OFFSET;
- priv->rx_bd_assign_ptr = priv->rx_bds;
- priv->rx_bd_assign_index = 0;
priv->rx_c_index = 0;
priv->rx_read_ptr = 0;
priv->rx_cbs = kzalloc(priv->num_rx_bds *
@@ -1266,6 +1331,11 @@
return -ENOMEM;
}
+ for (i = 0; i < priv->num_rx_bds; i++) {
+ cb = priv->rx_cbs + i;
+ cb->bd_addr = priv->rx_bds + i * DESC_SIZE;
+ }
+
ret = bcm_sysport_alloc_rx_bufs(priv);
if (ret) {
netif_err(priv, hw, priv->netdev, "SKB allocation failed\n");
@@ -1468,8 +1538,8 @@
/* Read CRC forward */
priv->crc_fwd = !!(umac_readl(priv, UMAC_CMD) & CMD_CRC_FWD);
- priv->phydev = of_phy_connect_fixed_link(dev, bcm_sysport_adj_link,
- priv->phy_interface);
+ priv->phydev = of_phy_connect(dev, priv->phy_dn, bcm_sysport_adj_link,
+ 0, priv->phy_interface);
if (!priv->phydev) {
netdev_err(dev, "could not attach to PHY\n");
ret = -ENODEV;
@@ -1628,6 +1698,8 @@
.get_sset_count = bcm_sysport_get_sset_count,
.get_wol = bcm_sysport_get_wol,
.set_wol = bcm_sysport_set_wol,
+ .get_coalesce = bcm_sysport_get_coalesce,
+ .set_coalesce = bcm_sysport_set_coalesce,
};
static const struct net_device_ops bcm_sysport_netdev_ops = {
@@ -1692,6 +1764,19 @@
if (priv->phy_interface < 0)
priv->phy_interface = PHY_INTERFACE_MODE_GMII;
+ /* In the case of a fixed PHY, the DT node associated
+ * to the PHY is the Ethernet MAC DT node.
+ */
+ if (of_phy_is_fixed_link(dn)) {
+ ret = of_phy_register_fixed_link(dn);
+ if (ret) {
+ dev_err(&pdev->dev, "failed to register fixed PHY\n");
+ goto err;
+ }
+
+ priv->phy_dn = dn;
+ }
+
/* Initialize netdevice members */
macaddr = of_get_mac_address(dn);
if (!macaddr || !is_valid_ether_addr(macaddr)) {
diff --git a/drivers/net/ethernet/broadcom/bcmsysport.h b/drivers/net/ethernet/broadcom/bcmsysport.h
index 03b3602..0549941 100644
--- a/drivers/net/ethernet/broadcom/bcmsysport.h
+++ b/drivers/net/ethernet/broadcom/bcmsysport.h
@@ -302,7 +302,7 @@
#define RDMA_END_ADDR_LO 0x102c
#define RDMA_MBDONE_INTR 0x1030
-#define RDMA_INTR_THRESH_MASK 0xff
+#define RDMA_INTR_THRESH_MASK 0x1ff
#define RDMA_TIMEOUT_SHIFT 16
#define RDMA_TIMEOUT_MASK 0xffff
@@ -580,6 +580,7 @@
BCM_SYSPORT_STAT_RUNT,
BCM_SYSPORT_STAT_RXCHK,
BCM_SYSPORT_STAT_RBUF,
+ BCM_SYSPORT_STAT_SOFT,
};
/* Macros to help define ethtool statistics */
@@ -600,6 +601,7 @@
#define STAT_MIB_RX(str, m) STAT_MIB(str, m, BCM_SYSPORT_STAT_MIB_RX)
#define STAT_MIB_TX(str, m) STAT_MIB(str, m, BCM_SYSPORT_STAT_MIB_TX)
#define STAT_RUNT(str, m) STAT_MIB(str, m, BCM_SYSPORT_STAT_RUNT)
+#define STAT_MIB_SOFT(str, m) STAT_MIB(str, m, BCM_SYSPORT_STAT_SOFT)
#define STAT_RXCHK(str, m, ofs) { \
.stat_string = str, \
@@ -668,14 +670,13 @@
/* Receive queue */
void __iomem *rx_bds;
- void __iomem *rx_bd_assign_ptr;
- unsigned int rx_bd_assign_index;
struct bcm_sysport_cb *rx_cbs;
unsigned int num_rx_bds;
unsigned int rx_read_ptr;
unsigned int rx_c_index;
/* PHY device */
+ struct device_node *phy_dn;
struct phy_device *phydev;
phy_interface_t phy_interface;
int old_pause;
diff --git a/drivers/net/ethernet/broadcom/genet/bcmgenet.c b/drivers/net/ethernet/broadcom/genet/bcmgenet.c
index f767c23..f563a0b 100644
--- a/drivers/net/ethernet/broadcom/genet/bcmgenet.c
+++ b/drivers/net/ethernet/broadcom/genet/bcmgenet.c
@@ -862,12 +862,12 @@
};
/* Power down the unimac, based on mode. */
-static void bcmgenet_power_down(struct bcmgenet_priv *priv,
+static int bcmgenet_power_down(struct bcmgenet_priv *priv,
enum bcmgenet_power_mode mode)
{
struct net_device *dev;
- int ret = 0;
u32 reg;
+ int ret = 0;
dev = priv->dev;
switch (mode) {
@@ -886,8 +886,7 @@
break;
case GENET_POWER_WOL_MAGIC:
ret = bcmgenet_wol_power_down_cfg(priv, mode);
- if (ret)
- return;
+ break;
case GENET_POWER_PASSIVE:
/* Power down LED */
@@ -896,12 +895,15 @@
reg |= (EXT_PWR_DOWN_PHY |
EXT_PWR_DOWN_DLL | EXT_PWR_DOWN_BIAS);
bcmgenet_ext_writel(priv, reg, EXT_EXT_PWR_MGMT);
+
+ bcmgenet_phy_power_set(priv->dev, false);
}
break;
default:
break;
}
+ return ret;
}
static void bcmgenet_power_up(struct bcmgenet_priv *priv,
@@ -935,6 +937,7 @@
/* enable APD */
reg |= EXT_PWR_DN_EN_LD;
bcmgenet_ext_writel(priv, reg, EXT_EXT_PWR_MGMT);
+ bcmgenet_phy_power_set(priv->dev, true);
bcmgenet_mii_reset(priv->dev);
}
default:
@@ -2193,18 +2196,6 @@
bcmgenet_umac_writel(priv, (addr[4] << 8) | addr[5], UMAC_MAC1);
}
-static int bcmgenet_wol_resume(struct bcmgenet_priv *priv)
-{
- /* From WOL-enabled suspend, switch to regular clock */
- if (priv->wolopts)
- clk_disable_unprepare(priv->clk_wol);
-
- /* Speed settings must be restored */
- bcmgenet_mii_config(priv->dev, false);
-
- return 0;
-}
-
/* Returns a reusable dma control register value */
static u32 bcmgenet_dma_disable(struct bcmgenet_priv *priv)
{
@@ -2250,9 +2241,6 @@
umac_enable_set(priv, CMD_TX_EN | CMD_RX_EN, true);
- if (priv->phy_type == BRCM_PHY_TYPE_INT)
- bcmgenet_power_up(priv, GENET_POWER_PASSIVE);
-
netif_tx_start_all_queues(dev);
phy_start(priv->phydev);
@@ -2272,6 +2260,12 @@
if (ret)
return ret;
+ /* If this is an internal GPHY, power it back on now, before UniMAC is
+ * brought out of reset as absolutely no UniMAC activity is allowed
+ */
+ if (priv->phy_type == BRCM_PHY_TYPE_INT)
+ bcmgenet_power_up(priv, GENET_POWER_PASSIVE);
+
/* take MAC out of reset */
bcmgenet_umac_reset(priv);
@@ -2387,11 +2381,11 @@
free_irq(priv->irq1, priv);
if (priv->phy_type == BRCM_PHY_TYPE_INT)
- bcmgenet_power_down(priv, GENET_POWER_PASSIVE);
+ ret = bcmgenet_power_down(priv, GENET_POWER_PASSIVE);
clk_disable_unprepare(priv->clk);
- return 0;
+ return ret;
}
static void bcmgenet_timeout(struct net_device *dev)
@@ -2912,14 +2906,16 @@
/* Prepare the device for Wake-on-LAN */
if (device_may_wakeup(d) && priv->wolopts) {
- bcmgenet_power_down(priv, GENET_POWER_WOL_MAGIC);
+ ret = bcmgenet_power_down(priv, GENET_POWER_WOL_MAGIC);
clk_prepare_enable(priv->clk_wol);
+ } else if (priv->phy_type == BRCM_PHY_TYPE_INT) {
+ ret = bcmgenet_power_down(priv, GENET_POWER_PASSIVE);
}
/* Turn off the clocks */
clk_disable_unprepare(priv->clk);
- return 0;
+ return ret;
}
static int bcmgenet_resume(struct device *d)
@@ -2938,15 +2934,24 @@
if (ret)
return ret;
+ /* If this is an internal GPHY, power it back on now, before UniMAC is
+ * brought out of reset as absolutely no UniMAC activity is allowed
+ */
+ if (priv->phy_type == BRCM_PHY_TYPE_INT)
+ bcmgenet_power_up(priv, GENET_POWER_PASSIVE);
+
bcmgenet_umac_reset(priv);
ret = init_umac(priv);
if (ret)
goto out_clk_disable;
- ret = bcmgenet_wol_resume(priv);
- if (ret)
- goto out_clk_disable;
+ /* From WOL-enabled suspend, switch to regular clock */
+ if (priv->wolopts)
+ clk_disable_unprepare(priv->clk_wol);
+
+ /* Speed settings must be restored */
+ bcmgenet_mii_config(priv->dev, false);
/* disable ethernet MAC while updating its registers */
umac_enable_set(priv, CMD_TX_EN | CMD_RX_EN, 0);
diff --git a/drivers/net/ethernet/broadcom/genet/bcmgenet.c.rej b/drivers/net/ethernet/broadcom/genet/bcmgenet.c.rej
deleted file mode 100644
index 30445e9..0000000
--- a/drivers/net/ethernet/broadcom/genet/bcmgenet.c.rej
+++ /dev/null
@@ -1,48 +0,0 @@
---- drivers/net/ethernet/broadcom/genet/bcmgenet.c
-+++ drivers/net/ethernet/broadcom/genet/bcmgenet.c
-@@ -1045,22 +1075,12 @@
- last_c_index &= (num_tx_bds - 1);
- }
-
-- if (ring->free_bds > (MAX_SKB_FRAGS + 1)
-- && netif_tx_queue_stopped(txq)) {
-- if (ring->index == DESC_INDEX) {
-- /* Disable txdma bdone/pdone interrupt if we have
-- * free tx bds
-- */
-- bcmgenet_intrl2_0_writel(priv,
-- UMAC_IRQ_TXDMA_BDONE | UMAC_IRQ_TXDMA_PDONE,
-- INTRL2_CPU_MASK_SET);
-- } else {
-- bcmgenet_intrl2_1_writel(priv, (1 << ring->index),
-- INTRL2_CPU_MASK_SET);
-- priv->int1_mask |= (1 << ring->index);
-- }
-+ if (ring->free_bds > (MAX_SKB_FRAGS + 1))
-+ ring->int_disable(priv, ring);
-+
-+ if (netif_tx_queue_stopped(txq))
- netif_tx_wake_queue(txq);
-- }
-+
- ring->c_index = c_index;
- }
-
-@@ -1325,16 +1345,7 @@
-
- if (ring->free_bds <= (MAX_SKB_FRAGS + 1)) {
- netif_tx_stop_queue(txq);
-- if (index == DESC_INDEX)
-- bcmgenet_intrl2_0_writel(priv,
-- UMAC_IRQ_TXDMA_BDONE |
-- UMAC_IRQ_TXDMA_PDONE,
-- INTRL2_CPU_MASK_CLEAR);
-- else {
-- bcmgenet_intrl2_1_writel(priv, (1 << index),
-- INTRL2_CPU_MASK_CLEAR);
-- priv->int1_mask &= ~(1 << index);
-- }
-+ ring->int_enable(priv, ring);
- }
-
- out:
diff --git a/drivers/net/ethernet/broadcom/genet/bcmgenet.h b/drivers/net/ethernet/broadcom/genet/bcmgenet.h
index 53a3232..13d1ca6 100644
--- a/drivers/net/ethernet/broadcom/genet/bcmgenet.h
+++ b/drivers/net/ethernet/broadcom/genet/bcmgenet.h
@@ -30,7 +30,19 @@
#include <linux/mii.h>
#include <linux/if_vlan.h>
#include <linux/phy.h>
-#include <linux/brcmstb/brcmstb.h>
+
+/* BCMGENET device tree properties */
+#define BRCM_PHY_ID_AUTO 0x100
+#define BRCM_PHY_ID_NONE 0x101
+
+#define BRCM_PHY_TYPE_INT 1
+#define BRCM_PHY_TYPE_EXT_MII 2
+#define BRCM_PHY_TYPE_EXT_RVMII 3
+#define BRCM_PHY_TYPE_EXT_RGMII 4
+#define BRCM_PHY_TYPE_EXT_RGMII_IBS 5
+#define BRCM_PHY_TYPE_EXT_RGMII_NO_ID 6
+#define BRCM_PHY_TYPE_MOCA 7
+
/* total number of Buffer Descriptors, same for Rx/Tx */
#define TOTAL_DESC 256
@@ -368,6 +380,7 @@
#define EXT_GPHY_CTRL 0x1C
#define EXT_CFG_IDDQ_BIAS (1 << 0)
#define EXT_CFG_PWR_DOWN (1 << 1)
+#define EXT_CK25_DIS (1 << 4)
#define EXT_GPHY_RESET (1 << 5)
/* DMA rings size */
@@ -667,6 +680,7 @@
int bcmgenet_mii_config(struct net_device *dev, bool init);
void bcmgenet_mii_exit(struct net_device *dev);
void bcmgenet_mii_reset(struct net_device *dev);
+void bcmgenet_phy_power_set(struct net_device *dev, bool enable);
void bcmgenet_mii_setup(struct net_device *dev);
#endif /* __BCMGENET_H__ */
diff --git a/drivers/net/ethernet/broadcom/genet/bcmgenet_wol.c b/drivers/net/ethernet/broadcom/genet/bcmgenet_wol.c
index 25c7147..b700219 100644
--- a/drivers/net/ethernet/broadcom/genet/bcmgenet_wol.c
+++ b/drivers/net/ethernet/broadcom/genet/bcmgenet_wol.c
@@ -80,15 +80,17 @@
if (wol->wolopts & ~(WAKE_MAGIC | WAKE_MAGICSECURE))
return -EINVAL;
+ reg = bcmgenet_umac_readl(priv, UMAC_MPD_CTRL);
if (wol->wolopts & WAKE_MAGICSECURE) {
bcmgenet_umac_writel(priv, get_unaligned_be16(&wol->sopass[0]),
UMAC_MPD_PW_MS);
bcmgenet_umac_writel(priv, get_unaligned_be32(&wol->sopass[2]),
UMAC_MPD_PW_LS);
- reg = bcmgenet_umac_readl(priv, UMAC_MPD_CTRL);
reg |= MPD_PW_EN;
- bcmgenet_umac_writel(priv, reg, UMAC_MPD_CTRL);
+ } else {
+ reg &= ~MPD_PW_EN;
}
+ bcmgenet_umac_writel(priv, reg, UMAC_MPD_CTRL);
/* Flag the device and relevant IRQ as wakeup capable */
if (wol->wolopts) {
diff --git a/drivers/net/ethernet/broadcom/genet/bcmmii.c b/drivers/net/ethernet/broadcom/genet/bcmmii.c
index aff4f35..f892cd7 100644
--- a/drivers/net/ethernet/broadcom/genet/bcmmii.c
+++ b/drivers/net/ethernet/broadcom/genet/bcmmii.c
@@ -62,7 +62,8 @@
/* Don't check error codes from switches, as some of them are
* known to return MDIO_READ_FAIL on good transactions
*/
- if (!priv->sw_type && (ret & MDIO_READ_FAIL)) {
+ if (!(bus->phy_ignore_ta_mask & 1 << phy_id) &&
+ (ret & MDIO_READ_FAIL)) {
netif_dbg(priv, hw, dev, "MDIO read failure\n");
ret = 0;
}
@@ -182,9 +183,6 @@
{
struct bcmgenet_priv *priv = netdev_priv(dev);
- bcmgenet_mii_write(priv->mii_bus, priv->phy_addr, MII_BMCR, BMCR_RESET);
- udelay(1);
-
/* call the PHY driver specific init routine */
phy_init_hw(priv->phydev);
phy_start_aneg(priv->phydev);
@@ -196,7 +194,7 @@
* micro seconds always works. The post-reset delay of 20 micro seconds could
* be eliminated but better be safe than sorry.
*/
-static void bcmgenet_ephy_power_up(struct net_device *dev)
+void bcmgenet_phy_power_set(struct net_device *dev, bool enable)
{
struct bcmgenet_priv *priv = netdev_priv(dev);
u32 reg = 0;
@@ -206,14 +204,25 @@
return;
reg = bcmgenet_ext_readl(priv, EXT_GPHY_CTRL);
- reg &= ~(EXT_CFG_IDDQ_BIAS | EXT_CFG_PWR_DOWN);
- reg |= EXT_GPHY_RESET;
- bcmgenet_ext_writel(priv, reg, EXT_GPHY_CTRL);
- mdelay(2);
+ if (enable) {
+ reg &= ~EXT_CK25_DIS;
+ bcmgenet_ext_writel(priv, reg, EXT_GPHY_CTRL);
+ mdelay(1);
- reg &= ~EXT_GPHY_RESET;
+ reg &= ~(EXT_CFG_IDDQ_BIAS | EXT_CFG_PWR_DOWN);
+ reg |= EXT_GPHY_RESET;
+ bcmgenet_ext_writel(priv, reg, EXT_GPHY_CTRL);
+ mdelay(1);
+
+ reg &= ~EXT_GPHY_RESET;
+ } else {
+ reg |= EXT_CFG_IDDQ_BIAS | EXT_CFG_PWR_DOWN | EXT_GPHY_RESET;
+ bcmgenet_ext_writel(priv, reg, EXT_GPHY_CTRL);
+ mdelay(1);
+ reg |= EXT_CK25_DIS;
+ }
bcmgenet_ext_writel(priv, reg, EXT_GPHY_CTRL);
- udelay(20);
+ udelay(60);
}
static int bcmgenet_mii_probe(struct net_device *dev)
@@ -259,14 +268,9 @@
phydev = phy_connect(dev, phy_id, bcmgenet_mii_setup,
priv->phy_interface);
} else {
- if (priv->phy_dn)
- phydev = of_phy_connect(dev, priv->phy_dn,
+ phydev = of_phy_connect(dev, priv->phy_dn,
bcmgenet_mii_setup, phy_flags,
priv->phy_interface);
- else
- phydev = of_phy_connect_fixed_link(dev,
- bcmgenet_mii_setup,
- priv->phy_interface);
}
if (!phydev) {
@@ -349,8 +353,8 @@
struct bcmgenet_priv *priv = netdev_priv(dev);
u32 reg;
- /* Power up EPHY */
- bcmgenet_ephy_power_up(dev);
+ /* Power up PHY */
+ bcmgenet_phy_power_set(dev, true);
/* enable APD */
reg = bcmgenet_ext_readl(priv, EXT_EXT_PWR_MGMT);
reg |= EXT_PWR_DN_EN_LD;
@@ -380,6 +384,7 @@
switch (priv->phy_interface) {
case PHY_INTERFACE_MODE_NA:
+ case PHY_INTERFACE_MODE_MOCA:
phy_name = "internal PHY";
/* Irrespective of the actually configured PHY speed (100 or
* 1000) GENETv4 only has an internal GPHY so we will just end
@@ -439,9 +444,6 @@
phy_name = "external RGMII (no delay)";
else
phy_name = "external RGMII (TX delay)";
- reg = bcmgenet_ext_readl(priv, EXT_RGMII_OOB_CTRL);
- reg |= RGMII_MODE_EN | id_mode_dis;
- bcmgenet_ext_writel(priv, reg, EXT_RGMII_OOB_CTRL);
bcmgenet_sys_writel(priv,
PORT_MODE_EXT_GPHY, SYS_PORT_CTRL);
priv->phy_supported = PHY_GBIT_FEATURES;
@@ -456,6 +458,15 @@
return -EINVAL;
}
+ /* This is an external PHY, aka xMII, so we need to enable the RGMII
+ * block for the interface to work
+ */
+ if (priv->ext_phy) {
+ reg = bcmgenet_ext_readl(priv, EXT_RGMII_OOB_CTRL);
+ reg |= RGMII_MODE_EN | id_mode_dis;
+ bcmgenet_ext_writel(priv, reg, EXT_RGMII_OOB_CTRL);
+ }
+
if (init)
dev_info(&priv->pdev->dev, "configuring instance for %s\n",
phy_name);
@@ -469,10 +480,9 @@
struct device *kdev = &priv->pdev->dev;
struct device_node *mdio_dn;
const char *phy_mode_str = NULL;
- const __be32 *fixed_link;
u32 propval;
int phy_mode;
- int ret, sz;
+ int ret;
mdio_dn = of_get_next_child(dn, NULL);
if (!mdio_dn) {
@@ -492,14 +502,13 @@
if (!of_property_read_u32(priv->phy_dn, "max-speed", &propval))
priv->phy_speed = propval;
} else {
- /* Read the link speed from the fixed-link property */
- fixed_link = of_get_property(dn, "fixed-link", &sz);
- if (!fixed_link || sz < sizeof(*fixed_link)) {
- ret = -ENODEV;
- goto out;
+ if (of_phy_is_fixed_link(dn)) {
+ ret = of_phy_register_fixed_link(dn);
+ if (ret)
+ return ret;
}
- priv->phy_speed = be32_to_cpu(fixed_link[2]);
+ priv->phy_dn = of_node_get(dn);
}
/* Get the link mode */
diff --git a/drivers/net/phy/bcm7xxx.c b/drivers/net/phy/bcm7xxx.c
index b30f01d..6764fe0 100644
--- a/drivers/net/phy/bcm7xxx.c
+++ b/drivers/net/phy/bcm7xxx.c
@@ -155,8 +155,8 @@
/* AFE_RX_LP_COUNTER, set RX bandwidth to maximum */
phy_write_misc(phydev, 0x0038, 0x0003, 0x7fc0);
- /* AFE_TX_CONFIG, set 1000BT Cfeed=110 for all ports */
- phy_write_misc(phydev, 0x0039, 0x0000, 0x0061);
+ /* AFE_TX_CONFIG, set 100BT Cfeed=011 to improve rise/fall time */
+ phy_write_misc(phydev, 0x0039, 0x0000, 0x0431);
/* AFE_VDCA_ICTRL_0, set Iq=1101 instead of 0111 for AB symmetry */
phy_write_misc(phydev, 0x0039, 0x0001, 0xa7da);
@@ -186,6 +186,9 @@
/* AFE_RXCONFIG_1, provide more margin for INL/DNL measurement on ATE */
phy_write_misc(phydev, 0x0038, 0x0001, 0x9b2f);
+ /* AFE_TX_CONFIG, set 100BT Cfeed=011 to improve rise/fall time */
+ phy_write_misc(phydev, 0x0039, 0x0000, 0x0431);
+
/* AFE_VDCA_ICTRL_0, set Iq=1101 instead of 0111 for AB symmetry */
phy_write_misc(phydev, 0x0039, 0x0001, 0xa7da);
diff --git a/drivers/net/phy/ethsw.c b/drivers/net/phy/ethsw.c
index e3b1ac9..b63e39c 100644
--- a/drivers/net/phy/ethsw.c
+++ b/drivers/net/phy/ethsw.c
@@ -26,6 +26,7 @@
#include <linux/ctype.h>
#include <linux/stddef.h>
#include <linux/phy.h>
+#include <linux/brcmphy.h>
#include <linux/module.h>
#define BCM53125_PHY_ID 0x03625f20
@@ -34,8 +35,6 @@
static unsigned char swdata[16];
static struct proc_dir_entry *p;
-#define PSEUDO_PHY_ADDR 0x1e
-
#define REG_PSEUDO_PHY_MII_REG16 0x10
#define REG_PPM_REG16_SWITCH_PAGE_NUMBER_SHIFT 8
#define REG_PPM_REG16_MDIO_ENABLE 0x01
@@ -146,7 +145,7 @@
int v, vm[4];
int i;
- phy_id = PSEUDO_PHY_ADDR;
+ phy_id = BRCM_PSEUDO_PHY_ADDR;
v = (page << REG_PPM_REG16_SWITCH_PAGE_NUMBER_SHIFT) | REG_PPM_REG16_MDIO_ENABLE;
mdiobus_write(phydev->bus, phy_id, REG_PSEUDO_PHY_MII_REG16, v);
@@ -215,7 +214,7 @@
int v;
int i;
- phy_id = PSEUDO_PHY_ADDR;
+ phy_id = BRCM_PSEUDO_PHY_ADDR;
v = (page << REG_PPM_REG16_SWITCH_PAGE_NUMBER_SHIFT) | REG_PPM_REG16_MDIO_ENABLE;
mdiobus_write(phydev->bus, phy_id, REG_PSEUDO_PHY_MII_REG16, v);
@@ -730,7 +729,7 @@
* address 0 as this is the default PHY addressing supported
* for BCM53xxx switches
*/
- if (phydev->addr != PSEUDO_PHY_ADDR && phydev->addr != 0) {
+ if (phydev->addr != BRCM_PSEUDO_PHY_ADDR && phydev->addr != 0) {
dev_err(&phydev->dev, "invalid PHY address %d\n",
phydev->addr);
return -ENODEV;
@@ -742,6 +741,12 @@
}
ethsw_add_proc_files(phydev);
+ /* Tell the MDIO bus controller that this switch's pseudo-PHY has a
+ * broken turn-around and it should ignore read failures. See ING JIRA
+ * SF-357.
+ */
+ phydev->bus->phy_ignore_ta_mask |= 1 << BRCM_PSEUDO_PHY_ADDR;
+
return 0;
}
diff --git a/drivers/net/phy/fixed.c b/drivers/net/phy/fixed.c
index cd38d99..72851be 100644
--- a/drivers/net/phy/fixed.c
+++ b/drivers/net/phy/fixed.c
@@ -21,6 +21,7 @@
#include <linux/phy_fixed.h>
#include <linux/err.h>
#include <linux/slab.h>
+#include <linux/of.h>
#define MII_REGS_NUM 29
@@ -31,7 +32,7 @@
};
struct fixed_phy {
- int id;
+ int addr;
u16 regs[MII_REGS_NUM];
struct phy_device *phydev;
struct fixed_phy_status status;
@@ -104,8 +105,8 @@
if (fp->status.asym_pause)
lpa |= LPA_PAUSE_ASYM;
- fp->regs[MII_PHYSID1] = fp->id >> 16;
- fp->regs[MII_PHYSID2] = fp->id;
+ fp->regs[MII_PHYSID1] = 0;
+ fp->regs[MII_PHYSID2] = 0;
fp->regs[MII_BMSR] = bmsr;
fp->regs[MII_BMCR] = bmcr;
@@ -115,7 +116,7 @@
return 0;
}
-static int fixed_mdio_read(struct mii_bus *bus, int phy_id, int reg_num)
+static int fixed_mdio_read(struct mii_bus *bus, int phy_addr, int reg_num)
{
struct fixed_mdio_bus *fmb = bus->priv;
struct fixed_phy *fp;
@@ -135,7 +136,7 @@
}
list_for_each_entry(fp, &fmb->phys, node) {
- if (fp->id == phy_id) {
+ if (fp->addr == phy_addr) {
/* Issue callback if user registered it. */
if (fp->link_update) {
fp->link_update(fp->phydev->attached_dev,
@@ -149,7 +150,7 @@
return 0xFFFF;
}
-static int fixed_mdio_write(struct mii_bus *bus, int phy_id, int reg_num,
+static int fixed_mdio_write(struct mii_bus *bus, int phy_addr, int reg_num,
u16 val)
{
return 0;
@@ -171,7 +172,7 @@
return -EINVAL;
list_for_each_entry(fp, &fmb->phys, node) {
- if (fp->id == phydev->phy_id) {
+ if (fp->addr == phydev->addr) {
fp->link_update = link_update;
fp->phydev = phydev;
return 0;
@@ -182,7 +183,7 @@
}
EXPORT_SYMBOL_GPL(fixed_phy_set_link_update);
-int fixed_phy_add(unsigned int irq, int phy_id,
+int fixed_phy_add(unsigned int irq, int phy_addr,
struct fixed_phy_status *status)
{
int ret;
@@ -195,9 +196,9 @@
memset(fp->regs, 0xFF, sizeof(fp->regs[0]) * MII_REGS_NUM);
- fmb->irqs[phy_id] = irq;
+ fmb->irqs[phy_addr] = irq;
- fp->id = phy_id;
+ fp->addr = phy_addr;
fp->status = *status;
ret = fixed_phy_update_regs(fp);
@@ -214,6 +215,66 @@
}
EXPORT_SYMBOL_GPL(fixed_phy_add);
+void fixed_phy_del(int phy_addr)
+{
+ struct fixed_mdio_bus *fmb = &platform_fmb;
+ struct fixed_phy *fp, *tmp;
+
+ list_for_each_entry_safe(fp, tmp, &fmb->phys, node) {
+ if (fp->addr == phy_addr) {
+ list_del(&fp->node);
+ kfree(fp);
+ return;
+ }
+ }
+}
+EXPORT_SYMBOL_GPL(fixed_phy_del);
+
+static int phy_fixed_addr;
+static DEFINE_SPINLOCK(phy_fixed_addr_lock);
+
+int fixed_phy_register(unsigned int irq,
+ struct fixed_phy_status *status,
+ struct device_node *np)
+{
+ struct fixed_mdio_bus *fmb = &platform_fmb;
+ struct phy_device *phy;
+ int phy_addr;
+ int ret;
+
+ /* Get the next available PHY address, up to PHY_MAX_ADDR */
+ spin_lock(&phy_fixed_addr_lock);
+ if (phy_fixed_addr == PHY_MAX_ADDR) {
+ spin_unlock(&phy_fixed_addr_lock);
+ return -ENOSPC;
+ }
+ phy_addr = phy_fixed_addr++;
+ spin_unlock(&phy_fixed_addr_lock);
+
+ ret = fixed_phy_add(PHY_POLL, phy_addr, status);
+ if (ret < 0)
+ return ret;
+
+ phy = get_phy_device(fmb->mii_bus, phy_addr, false);
+ if (!phy || IS_ERR(phy)) {
+ fixed_phy_del(phy_addr);
+ return -EINVAL;
+ }
+
+ of_node_get(np);
+ phy->dev.of_node = np;
+
+ ret = phy_device_register(phy);
+ if (ret) {
+ phy_device_free(phy);
+ of_node_put(np);
+ fixed_phy_del(phy_addr);
+ return ret;
+ }
+
+ return 0;
+}
+
static int __init fixed_mdio_bus_init(void)
{
struct fixed_mdio_bus *fmb = &platform_fmb;
diff --git a/drivers/net/phy/mdio-bitbang.c b/drivers/net/phy/mdio-bitbang.c
index daec9b0..61a543c 100644
--- a/drivers/net/phy/mdio-bitbang.c
+++ b/drivers/net/phy/mdio-bitbang.c
@@ -165,8 +165,11 @@
ctrl->ops->set_mdio_dir(ctrl, 0);
- /* check the turnaround bit: the PHY should be driving it to zero */
- if (mdiobb_get_bit(ctrl) != 0) {
+ /* check the turnaround bit: the PHY should be driving it to zero, if this
+ * PHY is listed in phy_ignore_ta_mask as having broken TA, skip that
+ */
+ if (mdiobb_get_bit(ctrl) != 0 &&
+ !(bus->phy_ignore_ta_mask & (1 << phy))) {
/* PHY didn't drive TA low -- flush any bits it
* may be trying to send.
*/
diff --git a/drivers/net/phy/mdio-unimac.c b/drivers/net/phy/mdio-unimac.c
index fb59e80..8e55167 100644
--- a/drivers/net/phy/mdio-unimac.c
+++ b/drivers/net/phy/mdio-unimac.c
@@ -82,7 +82,7 @@
return -ETIMEDOUT;
cmd = __raw_readl(priv->base + MDIO_CMD);
- if (cmd & MDIO_READ_FAIL)
+ if (!(bus->phy_ignore_ta_mask & 1 << phy_id) && (cmd & MDIO_READ_FAIL))
return -EIO;
return cmd & 0xffff;
diff --git a/drivers/net/phy/mdio_bus.c b/drivers/net/phy/mdio_bus.c
index 71e4900..fc70686 100644
--- a/drivers/net/phy/mdio_bus.c
+++ b/drivers/net/phy/mdio_bus.c
@@ -326,9 +326,13 @@
if (!drv || !phydrv->suspend)
return false;
- /* PHY not attached? May suspend. */
+ /* PHY not attached? May suspend if the PHY has not already been
+ * suspended as part of a prior call to phy_disconnect() ->
+ * phy_detach() -> phy_suspend() because the parent netdev might be the
+ * MDIO bus driver and clock gated at this point.
+ */
if (!netdev)
- return true;
+ return !phydev->suspended;
/* Don't suspend PHY if the attched netdev parent may wakeup.
* The parent may point to a PCI device, as in tg3 driver.
@@ -348,7 +352,6 @@
static int mdio_bus_suspend(struct device *dev)
{
- struct phy_driver *phydrv = to_phy_driver(dev->driver);
struct phy_device *phydev = to_phy_device(dev);
/* We must stop the state machine manually, otherwise it stops out of
@@ -362,19 +365,18 @@
if (!mdio_bus_phy_may_suspend(phydev))
return 0;
- return phydrv->suspend(phydev);
+ return phy_suspend(phydev);
}
static int mdio_bus_resume(struct device *dev)
{
- struct phy_driver *phydrv = to_phy_driver(dev->driver);
struct phy_device *phydev = to_phy_device(dev);
int ret;
if (!mdio_bus_phy_may_suspend(phydev))
goto no_resume;
- ret = phydrv->resume(phydev);
+ ret = phy_resume(phydev);
if (ret < 0)
return ret;
diff --git a/drivers/net/phy/phy.c b/drivers/net/phy/phy.c
index d2722da..5e87beb 100644
--- a/drivers/net/phy/phy.c
+++ b/drivers/net/phy/phy.c
@@ -283,7 +283,10 @@
ethtool_cmd_speed_set(cmd, phydev->speed);
cmd->duplex = phydev->duplex;
- cmd->port = PORT_MII;
+ if (phydev->interface == PHY_INTERFACE_MODE_MOCA)
+ cmd->port = PORT_BNC;
+ else
+ cmd->port = PORT_MII;
cmd->phy_address = phydev->addr;
cmd->transceiver = phy_is_internal(phydev) ?
XCVR_INTERNAL : XCVR_EXTERNAL;
diff --git a/drivers/net/phy/phy_device.c b/drivers/net/phy/phy_device.c
index 25f7419..ad52d01 100644
--- a/drivers/net/phy/phy_device.c
+++ b/drivers/net/phy/phy_device.c
@@ -684,6 +684,7 @@
{
struct phy_driver *phydrv = to_phy_driver(phydev->dev.driver);
struct ethtool_wolinfo wol = { .cmd = ETHTOOL_GWOL };
+ int ret = 0;
/* If the device has WOL enabled, we cannot suspend the PHY */
phy_ethtool_get_wol(phydev, &wol);
@@ -691,16 +692,29 @@
return -EBUSY;
if (phydrv->suspend)
- return phydrv->suspend(phydev);
+ ret = phydrv->suspend(phydev);
+
+ if (ret)
+ return ret;
+
+ phydev->suspended = true;
+
return 0;
}
int phy_resume(struct phy_device *phydev)
{
struct phy_driver *phydrv = to_phy_driver(phydev->dev.driver);
+ int ret = 0;
if (phydrv->resume)
- return phydrv->resume(phydev);
+ ret = phydrv->resume(phydev);
+
+ if (ret)
+ return ret;
+
+ phydev->suspended = false;
+
return 0;
}
diff --git a/drivers/of/base.c b/drivers/of/base.c
index 3935614..e5ccae9 100644
--- a/drivers/of/base.c
+++ b/drivers/of/base.c
@@ -904,6 +904,38 @@
EXPORT_SYMBOL(of_find_node_by_phandle);
/**
+ * of_property_count_elems_of_size - Count the number of elements in a property
+ *
+ * @np: device node from which the property value is to be read.
+ * @propname: name of the property to be searched.
+ * @elem_size: size of the individual element
+ *
+ * Search for a property in a device node and count the number of elements of
+ * size elem_size in it. Returns number of elements on sucess, -EINVAL if the
+ * property does not exist or its length does not match a multiple of elem_size
+ * and -ENODATA if the property does not have a value.
+ */
+int of_property_count_elems_of_size(const struct device_node *np,
+ const char *propname, int elem_size)
+{
+ struct property *prop = of_find_property(np, propname, NULL);
+
+ if (!prop)
+ return -EINVAL;
+ if (!prop->value)
+ return -ENODATA;
+
+ if (prop->length % elem_size != 0) {
+ pr_err("size of %s in node %s is not a multiple of %d\n",
+ propname, np->full_name, elem_size);
+ return -EINVAL;
+ }
+
+ return prop->length / elem_size;
+}
+EXPORT_SYMBOL_GPL(of_property_count_elems_of_size);
+
+/**
* of_find_property_value_of_size
*
* @np: device node from which the property value is to be read.
diff --git a/drivers/of/of_mdio.c b/drivers/of/of_mdio.c
index bf7f8ec..62ad6f0 100644
--- a/drivers/of/of_mdio.c
+++ b/drivers/of/of_mdio.c
@@ -14,6 +14,7 @@
#include <linux/netdevice.h>
#include <linux/err.h>
#include <linux/phy.h>
+#include <linux/phy_fixed.h>
#include <linux/of.h>
#include <linux/of_irq.h>
#include <linux/of_mdio.h>
@@ -68,6 +69,9 @@
phy->irq = mdio->irq[addr];
}
+ if (of_property_read_bool(child, "broken-turn-around"))
+ mdio->phy_ignore_ta_mask |= 1 << addr;
+
/* Associate the OF node with the device structure so it
* can be looked up later */
of_node_get(child);
@@ -285,3 +289,71 @@
return phy_attach_direct(dev, phy, flags, iface) ? NULL : phy;
}
EXPORT_SYMBOL(of_phy_attach);
+
+#if defined(CONFIG_FIXED_PHY)
+/*
+ * of_phy_is_fixed_link() and of_phy_register_fixed_link() must
+ * support two DT bindings:
+ * - the old DT binding, where 'fixed-link' was a property with 5
+ * cells encoding various informations about the fixed PHY
+ * - the new DT binding, where 'fixed-link' is a sub-node of the
+ * Ethernet device.
+ */
+bool of_phy_is_fixed_link(struct device_node *np)
+{
+ struct device_node *dn;
+ int len;
+
+ /* New binding */
+ dn = of_get_child_by_name(np, "fixed-link");
+ if (dn) {
+ of_node_put(dn);
+ return true;
+ }
+
+ /* Old binding */
+ if (of_get_property(np, "fixed-link", &len) &&
+ len == (5 * sizeof(__be32)))
+ return true;
+
+ return false;
+}
+EXPORT_SYMBOL(of_phy_is_fixed_link);
+
+int of_phy_register_fixed_link(struct device_node *np)
+{
+ struct fixed_phy_status status = {};
+ struct device_node *fixed_link_node;
+ const __be32 *fixed_link_prop;
+ int len;
+
+ /* New binding */
+ fixed_link_node = of_get_child_by_name(np, "fixed-link");
+ if (fixed_link_node) {
+ status.link = 1;
+ status.duplex = of_property_read_bool(fixed_link_node,
+ "full-duplex");
+ if (of_property_read_u32(fixed_link_node, "speed", &status.speed))
+ return -EINVAL;
+ status.pause = of_property_read_bool(fixed_link_node, "pause");
+ status.asym_pause = of_property_read_bool(fixed_link_node,
+ "asym-pause");
+ of_node_put(fixed_link_node);
+ return fixed_phy_register(PHY_POLL, &status, np);
+ }
+
+ /* Old binding */
+ fixed_link_prop = of_get_property(np, "fixed-link", &len);
+ if (fixed_link_prop && len == (5 * sizeof(__be32))) {
+ status.link = 1;
+ status.duplex = be32_to_cpu(fixed_link_prop[1]);
+ status.speed = be32_to_cpu(fixed_link_prop[2]);
+ status.pause = be32_to_cpu(fixed_link_prop[3]);
+ status.asym_pause = be32_to_cpu(fixed_link_prop[4]);
+ return fixed_phy_register(PHY_POLL, &status, np);
+ }
+
+ return -ENODEV;
+}
+EXPORT_SYMBOL(of_phy_register_fixed_link);
+#endif
diff --git a/drivers/of/of_net.c b/drivers/of/of_net.c
index a208a45..9590914 100644
--- a/drivers/of/of_net.c
+++ b/drivers/of/of_net.c
@@ -31,6 +31,7 @@
[PHY_INTERFACE_MODE_RTBI] = "rtbi",
[PHY_INTERFACE_MODE_SMII] = "smii",
[PHY_INTERFACE_MODE_XGMII] = "xgmii",
+ [PHY_INTERFACE_MODE_MOCA] = "moca",
};
/**
diff --git a/drivers/of/of_reserved_mem.c b/drivers/of/of_reserved_mem.c
index 69b8117..12e450e 100644
--- a/drivers/of/of_reserved_mem.c
+++ b/drivers/of/of_reserved_mem.c
@@ -170,6 +170,33 @@
return 0;
}
+static const struct of_device_id __rmem_of_table_sentinel
+ __used __section(__reservedmem_of_table_end);
+
+/**
+ * res_mem_init_node() - call region specific reserved memory init code
+ */
+static int __init __reserved_mem_init_node(struct reserved_mem *rmem)
+{
+ extern const struct of_device_id __reservedmem_of_table[];
+ const struct of_device_id *i;
+
+ for (i = __reservedmem_of_table; i < &__rmem_of_table_sentinel; i++) {
+ reservedmem_of_init_fn initfn = i->data;
+ const char *compat = i->compatible;
+
+ if (!of_flat_dt_is_compatible(rmem->fdt_node, compat))
+ continue;
+
+ if (initfn(rmem) == 0) {
+ pr_info("Reserved memory: initialized node %s, compatible id %s\n",
+ rmem->name, compat);
+ return 0;
+ }
+ }
+ return -ENOENT;
+}
+
/**
* fdt_init_reserved_mem - allocate and init all saved reserved memory regions
*/
@@ -184,5 +211,7 @@
if (rmem->size == 0)
err = __reserved_mem_alloc_size(node, rmem->name,
&rmem->base, &rmem->size);
+ if (err == 0)
+ __reserved_mem_init_node(rmem);
}
}
diff --git a/drivers/soc/Kconfig b/drivers/soc/Kconfig
new file mode 100644
index 0000000..74cc7dc
--- /dev/null
+++ b/drivers/soc/Kconfig
@@ -0,0 +1,5 @@
+menu "SOC (System On Chip) specific Drivers"
+
+source "drivers/soc/brcmstb/Kconfig"
+
+endmenu
diff --git a/drivers/soc/Makefile b/drivers/soc/Makefile
new file mode 100644
index 0000000..9e057ea
--- /dev/null
+++ b/drivers/soc/Makefile
@@ -0,0 +1,5 @@
+#
+# Makefile for the Linux Kernel SOC specific device drivers.
+#
+
+obj-$(CONFIG_SOC_BRCMSTB) += brcmstb/
diff --git a/drivers/soc/brcmstb/Kconfig b/drivers/soc/brcmstb/Kconfig
new file mode 100644
index 0000000..1c5ccb2
--- /dev/null
+++ b/drivers/soc/brcmstb/Kconfig
@@ -0,0 +1,74 @@
+config SOC_BRCMSTB
+ bool
+
+menu "Broadcom STB SoC drivers"
+ depends on SOC_BRCMSTB
+
+config BRCMSTB_IRQ0_STUB
+ bool "Enable stub IRQ0 driver"
+ default y
+ depends on !BCM7120_L2_IRQ
+ help
+ This enables the stub IRQ0 driver, for configuring the IRQ0
+ forwarding mask to enable the UARTs, but not do anything else with
+ the IRQ0 block. This driver is really a hack, and it exists solely
+ because Nexus wants to share the IRQ0 registers without telling
+ Linux.
+
+ It is highly recommended to either enable this or BCM7120_L2_IRQ.
+
+config BRCMSTB_BMEM
+ bool "Enable BMEM reserved A/V memory"
+ depends on HAVE_MEMBLOCK && ARCH_BRCMSTB && BRCMSTB_MEMORY_API
+ help
+ The A/V peripherals (managed by the PI/Nexus middleware) require
+ large, contiguous memory regions to be set aside at boot time. This
+ option sets those up in a default config that reserves most of
+ memory. Also allows the user to manually define region sizes and
+ locations using the 'bmem' command line param. Allows for O_DIRECT
+ I/O using these regions, mmap() from user programs, and
+ ioremap() from kernel drivers.
+
+ If you are planning to use Broadcom middleware, choose Y here.
+
+config BRCMSTB_CMA
+ bool "Broadcom STB CMA"
+ depends on ARCH_BRCMSTB && ARM && CMA && BRCMSTB_MEMORY_API
+ help
+ This driver provides the ioctls for manipulating with the reserved
+ areas used by Broadcom middleware, as well as the functions for the
+ kernel interface. It also provides register and reserve functions
+ for setting up the CMA regions it uses at early boot.
+
+ If you are planning to use Broadcom middleware, choose Y here.
+
+config BRCMSTB_MEMORY_API
+ bool "Enable BRCMSTB memory API"
+ depends on HAVE_MEMBLOCK && ARCH_BRCMSTB
+ select LIBFDT
+ help
+ This provides information on how system memory is arranged so that
+ Broadcom STB middleware can determine how to set up its memory heaps.
+
+ If you are planning to use Broadcom middleware, choose Y here.
+
+config BRCMSTB_PM
+ bool "Support suspend/resume for STB platforms"
+ default y
+ depends on PM
+ depends on ARM && ARCH_BRCMSTB
+
+config BRCMSTB_SRPD
+ tristate "Support enabling DDR self-refresh modes"
+ help
+ Provides a sysfs interface for setting the self-refresh timeout
+ value on Broadcom STB memory controllers.
+
+config BRCMSTB_WKTMR
+ tristate "Support wake-up timer"
+
+# Perform memory hashing before entering S3, using XPT DMA
+config BRCMSTB_XPT_HASH
+ bool
+
+endmenu
diff --git a/drivers/soc/brcmstb/Makefile b/drivers/soc/brcmstb/Makefile
new file mode 100644
index 0000000..b25afad
--- /dev/null
+++ b/drivers/soc/brcmstb/Makefile
@@ -0,0 +1,11 @@
+obj-$(CONFIG_BRCMSTB_PM) += pm/
+
+obj-y += common.o
+obj-$(CONFIG_BRCMSTB_BMEM) += bmem.o
+obj-$(CONFIG_BRCMSTB_CMA) += cma_driver.o
+obj-$(CONFIG_BRCMSTB_IRQ0_STUB) += irq0-stub.o
+obj-$(CONFIG_BRCMSTB_MEMORY_API) += memory.o
+obj-$(CONFIG_BRCMSTB_SRPD) += srpd.o
+obj-$(CONFIG_BRCMSTB_WKTMR) += wktmr.o
+
+CFLAGS_memory.o += -I$(src)/../../../scripts/dtc/libfdt
diff --git a/drivers/soc/brcmstb/bmem.c b/drivers/soc/brcmstb/bmem.c
new file mode 100644
index 0000000..3d5c69b
--- /dev/null
+++ b/drivers/soc/brcmstb/bmem.c
@@ -0,0 +1,290 @@
+/*
+ * Copyright © 2015 Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License, version 2, as
+ * published by the Free Software Foundation (the "GPL").
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ * General Public License for more details.
+ *
+ * A copy of the GPL is available at
+ * http://www.broadcom.com/licenses/GPLv2.php or from the Free Software
+ * Foundation at https://www.gnu.org/licenses/ .
+ */
+
+#define pr_fmt(fmt) "bmem: " fmt
+
+#include <asm/setup.h>
+#include <linux/ctype.h>
+#include <linux/device.h>
+#include <linux/ioport.h>
+#include <linux/memblock.h>
+#include <linux/platform_device.h>
+#include <linux/sizes.h>
+#include <linux/slab.h>
+#include <linux/brcmstb/bmem.h>
+#include <linux/brcmstb/memory_api.h>
+
+#if 0
+#define DBG pr_info
+#else
+#define DBG(...) /* */
+#endif
+
+#define MAX_BMEM_REGIONS 8
+
+struct bmem_region {
+ phys_addr_t addr;
+ phys_addr_t size;
+ bool valid;
+};
+
+static struct bmem_region bmem_regions[MAX_BMEM_REGIONS];
+static struct platform_device *brcmstb_pdev;
+static unsigned int n_bmem_regions;
+static bool bmem_disabled;
+
+/***********************************************************************
+ * BMEM (reserved A/V buffer memory) support
+ ***********************************************************************/
+
+static int __init __bmem_setup(phys_addr_t addr, phys_addr_t size)
+{
+ if (n_bmem_regions == MAX_BMEM_REGIONS) {
+ pr_warn_once("too many regions, ignoring extras\n");
+ return -E2BIG;
+ }
+
+ bmem_regions[n_bmem_regions].addr = addr;
+ bmem_regions[n_bmem_regions].size = size;
+ n_bmem_regions++;
+ return 0;
+}
+
+/*
+ * Parses command line for bmem= options
+ */
+static int __init bmem_setup(char *str)
+{
+ phys_addr_t addr = 0, size;
+ char *orig_str = str;
+ int ret;
+
+ size = memparse(str, &str);
+ if (*str == '@')
+ addr = memparse(str + 1, &str);
+
+ if ((addr & ~PAGE_MASK) || (size & ~PAGE_MASK)) {
+ pr_warn("ignoring invalid range '%s' (is it missing an 'M' suffix?)\n",
+ orig_str);
+ return 0;
+ }
+
+ if (size == 0) {
+ pr_info("disabling reserved memory\n");
+ bmem_disabled = true;
+ return 0;
+ }
+
+ ret = __bmem_setup(addr, size);
+ if (!ret)
+ brcmstb_memory_override_defaults = true;
+ return ret;
+}
+early_param("bmem", bmem_setup);
+
+/*
+ * Returns index if the supplied range falls entirely within a bmem region
+ */
+int bmem_find_region(phys_addr_t addr, phys_addr_t size)
+{
+ int i, idx = 0;
+
+ for (i = 0; i < n_bmem_regions; i++) {
+ if (!bmem_regions[i].valid)
+ continue;
+ if ((addr >= bmem_regions[i].addr) &&
+ ((addr + size) <=
+ (bmem_regions[i].addr + bmem_regions[i].size))) {
+ return idx;
+ }
+ idx++;
+ }
+ return -ENOENT;
+}
+
+/*
+ * Finds the IDX'th valid bmem region, and fills in addr/size if it exists.
+ * Returns 0 on success, <0 on failure.
+ * Can pass in NULL for addr and/or size if you only care about return value.
+ */
+int bmem_region_info(int idx, phys_addr_t *addr, phys_addr_t *size)
+{
+ int i;
+
+ for (i = 0; i < n_bmem_regions; i++) {
+ if (!bmem_regions[i].valid)
+ continue;
+ if (!idx) {
+ if (addr)
+ *addr = bmem_regions[i].addr;
+ if (size)
+ *size = bmem_regions[i].size;
+ return 0;
+ }
+ idx--;
+ }
+ return -ENOENT;
+}
+
+static void __init bmem_setup_defaults(void)
+{
+ int iter;
+
+ for_each_bank(iter, &meminfo) {
+ phys_addr_t start, size;
+
+ if (n_bmem_regions == MAX_BMEM_REGIONS) {
+ pr_warn_once("%s: too many regions, ignoring extras\n",
+ __func__);
+ return;
+ }
+
+ /* fill in start and size */
+ if (brcmstb_memory_get_default_reserve(iter, &start, &size))
+ continue;
+
+ __bmem_setup(start, size);
+ }
+}
+
+void __init bmem_reserve(void)
+{
+ int i;
+ int ret;
+
+ if (bmem_disabled) {
+ n_bmem_regions = 0;
+ return;
+ }
+
+ if (brcmstb_default_reserve == BRCMSTB_RESERVE_BMEM &&
+ !n_bmem_regions &&
+ !brcmstb_memory_override_defaults)
+ bmem_setup_defaults();
+
+ for (i = 0; i < n_bmem_regions; ++i) {
+ ret = memblock_reserve(bmem_regions[i].addr,
+ bmem_regions[i].size);
+ if (ret) {
+ pr_err("memblock_reserve(%pa, %pa) failed: %d\n",
+ &bmem_regions[i].addr,
+ &bmem_regions[i].size, ret);
+ } else {
+ bmem_regions[i].valid = true;
+ pr_info("Reserved %lu MiB at %pa\n",
+ (unsigned long) bmem_regions[i].size / SZ_1M,
+ &bmem_regions[i].addr);
+ }
+ }
+}
+
+/*
+ * Create /proc/iomem entries for bmem
+ */
+static int __init bmem_region_setup(void)
+{
+ int i, idx = 0;
+
+ for (i = 0; i < n_bmem_regions; i++) {
+ struct resource *r;
+ char *name;
+
+ if (!bmem_regions[i].valid)
+ continue;
+
+ r = kzalloc(sizeof(*r), GFP_KERNEL);
+ name = kzalloc(16, GFP_KERNEL);
+ if (!r || !name)
+ break;
+
+ sprintf(name, "bmem.%d", idx);
+ r->start = bmem_regions[i].addr;
+ r->end = bmem_regions[i].addr + bmem_regions[i].size - 1;
+ r->flags = IORESOURCE_MEM;
+ r->name = name;
+
+ insert_resource(&iomem_resource, r);
+ idx++;
+ }
+ return 0;
+}
+arch_initcall(bmem_region_setup);
+
+static ssize_t show_bmem(struct device *dev,
+ struct device_attribute *attr, char *buf)
+{
+ unsigned long idx = 0;
+ phys_addr_t addr = 0, size = 0;
+ const char *name = attr->attr.name;
+ int ret;
+
+ while (*name != 0) {
+ if (isdigit(*name)) {
+ ret = kstrtoul(name, 10, &idx);
+ if (ret)
+ return ret;
+ break;
+ }
+ name++;
+ }
+ bmem_region_info(idx, &addr, &size);
+
+ return snprintf(buf, PAGE_SIZE, "%pa %pa\n", &addr, &size);
+}
+
+static int __init brcm_pdev_init(void)
+{
+ struct device *dev;
+ int i;
+
+ brcmstb_pdev = platform_device_alloc("brcmstb", -1);
+ if (brcmstb_pdev == NULL) {
+ pr_err("%s: can't allocate device\n", __func__);
+ return -ENODEV;
+ }
+ platform_device_add(brcmstb_pdev);
+ dev = &brcmstb_pdev->dev;
+
+ /* create an attribute for each bmem region */
+ for (i = 0; ; i++) {
+ phys_addr_t addr, size;
+ struct device_attribute *attr;
+ char *name;
+
+ if (bmem_region_info(i, &addr, &size) < 0)
+ break;
+ attr = kzalloc(sizeof(*attr), GFP_KERNEL);
+ if (attr == NULL)
+ break;
+
+ name = kzalloc(16, GFP_KERNEL);
+ if (name == NULL)
+ break;
+ snprintf(name, 16, "bmem.%d", i);
+
+ sysfs_attr_init(&attr->attr);
+ attr->attr.name = name;
+ attr->attr.mode = 0444;
+ attr->show = show_bmem;
+
+ if (device_create_file(dev, attr) != 0)
+ WARN(1, "Can't create sysfs file\n");
+ }
+
+ return 0;
+}
+arch_initcall(brcm_pdev_init);
diff --git a/arch/arm/mach-bcm/cma_driver.c b/drivers/soc/brcmstb/cma_driver.c
similarity index 73%
rename from arch/arm/mach-bcm/cma_driver.c
rename to drivers/soc/brcmstb/cma_driver.c
index a5ac8d0..983ab66 100644
--- a/arch/arm/mach-bcm/cma_driver.c
+++ b/drivers/soc/brcmstb/cma_driver.c
@@ -1,7 +1,7 @@
/*
* cma_driver.c - Broadcom STB platform CMA driver
*
- * Copyright (C) 2009 - 2013 Broadcom Corporation
+ * Copyright © 2009 - 2015 Broadcom Corporation
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
@@ -13,9 +13,9 @@
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
- * You should have received a copy of the GNU General Public License
- * along with this program; see the file COPYING. If not, write to
- * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
+ * A copy of the GPL is available at
+ * http://www.broadcom.com/licenses/GPLv2.php or from the Free Software
+ * Foundation at https://www.gnu.org/licenses/ .
*/
#define pr_fmt(fmt) "cma_driver: " fmt
@@ -32,6 +32,7 @@
#include <linux/sched.h>
#include <linux/spinlock.h>
#include <linux/brcmstb/cma_driver.h>
+#include <linux/brcmstb/memory_api.h>
#include <linux/mmzone.h>
#include <linux/vmalloc.h>
#include <linux/memblock.h>
@@ -39,6 +40,7 @@
#include <linux/bitmap.h>
#include <linux/highmem.h>
#include <linux/dma-contiguous.h>
+#include <linux/cma.h>
#include <linux/sizes.h>
#include <linux/vme.h>
#include <asm/div64.h>
@@ -66,15 +68,22 @@
struct cma_region_rsv_data {
int nr_regions_valid;
struct cma_pdev_data regions[NR_BANKS];
- long long unsigned prm_kern_rsv_mb;
long long unsigned prm_low_lim_mb;
int prm_low_kern_rsv_pct;
};
+struct cma_rsv_region {
+ phys_addr_t addr;
+ phys_addr_t size;
+};
+
+static struct cma_rsv_region cma_rsv_setup_data[MAX_CMA_AREAS];
+static unsigned int n_cma_regions;
+static bool cma_disabled;
+
/* CMA region reservation */
static struct cma_region_rsv_data cma_data __initdata = {
- .prm_kern_rsv_mb = 256 << 20,
.prm_low_lim_mb = 32 << 20,
.prm_low_kern_rsv_pct = 20,
};
@@ -85,17 +94,6 @@
};
/*
- * The default kernel reservation on systems with low and high-memory. The
- * size of the memblock minus this variable will be given to CMA
- */
-static int __init cma_kern_rsv_set(char *p)
-{
- cma_data.prm_kern_rsv_mb = memparse(p, NULL);
- return !cma_data.prm_kern_rsv_mb ? -EINVAL : 0;
-}
-early_param("brcm_cma_kern_rsv", cma_kern_rsv_set);
-
-/*
* The lowest low-memory memblock size needed in order to reserve a cma region
* on systems with no high-memory.
*/
@@ -117,201 +115,119 @@
}
early_param("brcm_cma_low_kern_rsv_pct", cma_low_kern_rsv_pct_set);
-/*
- * Determine how many bytes of memory have been reserved in the DT
- * reserve map (/memreserve/).
- *
- * Note: It is expected that the only user of /memreserve/ is the bolt
- * 'splashmem' implementation. All other users that require contiguous memory
- * should use the standard CMA interfaces.
- */
-static u32 __init parse_static_rsv_entries(const u64 range_start,
- const u64 range_size)
+static int __init __cma_rsv_setup(phys_addr_t addr, phys_addr_t size)
{
- u64 *rsv_map;
- u32 bytes_reserved = 0;
- const u64 range_end = range_start + range_size;
-
- if (!initial_boot_params) {
- pr_err("no fdt found\n");
- return 0;
+ if (n_cma_regions == MAX_CMA_AREAS) {
+ pr_warn_once("%s: too many regions, ignoring extras\n",
+ __func__);
+ return -EINVAL;
}
- rsv_map = ((void *)initial_boot_params) +
- be32_to_cpu(initial_boot_params->off_mem_rsvmap);
- for (;;) {
- const u64 base = be64_to_cpup(rsv_map++);
- const u64 size = be64_to_cpup(rsv_map++);
- const u64 end = base + size;
-
- if (!size)
- break;
-
- /* 'splashmem' is expected to only carve memory out at the end
- * of the MEMC. All other reservations should modify the
- * DT 'memory' node so that the automatic CMA reservation
- * code doesn't fail.
- */
- if (base >= range_start && base < range_end) {
- if (end >= range_start) {
- if (end < range_end)
- bytes_reserved += size;
- else
- bytes_reserved += range_end - base;
- }
- }
- }
-
- return bytes_reserved;
-}
-
-static int __init cma_calc_rsv_range(int bank_nr, phys_addr_t *size)
-{
- /* This is the alignment used in dma_contiguous_reserve_area() */
- const phys_addr_t alignment =
- PAGE_SIZE << max(MAX_ORDER - 1, pageblock_order);
- u64 total = 0;
- u32 bytes_reserved;
- struct membank *bank = &meminfo.bank[bank_nr];
-
- /*
- * In DT, the 'reg' property in the 'memory' node is typically
- * arranged as follows:
- *
- * <base0 size0 base1 size1 [...] baseN sizeN>
- *
- * where N = the number of logical partitions in the memory map.
- *
- * The 'logical partitions' are typically memory controllers.
- *
- * According to ARM DEN 0001C, systems typically populate DRAM at high
- * PAs in the physical address space. However, system limitations
- * require placement of DRAM at low PAs. To that end, there is a need
- * to provide contiguous memory in low-memory regions, to support the
- * needs of system peripherals.
- *
- * Further, the current ARM kernel exploits large linear mappings in
- * low-memory, to reduce TLB pressure and increase overall system
- * performance. In a 3G/1G user/kernel memory split, the 1G portion of
- * kernel address space is further broken down into a low and high
- * memory region. The high-memory region is defined by the kernel
- * to be used for vmalloc (see arch/arm/mm/mmu.c).
- *
- * The code below will workaround the aforementioned demands on
- * low-memory (which resides in bank_nr = 0), and any special
- * kernel-specific boundaries.
- *
- */
- if (bank_nr == 0) {
- if ((meminfo.nr_banks == 1) && !bank->highmem) {
- u32 rem;
- u64 tmp;
-
- if (bank->size < cma_data.prm_low_lim_mb) {
- /* don't bother */
- pr_err("low memory block too small\n");
- return -EINVAL;
- }
-
- /* kernel reserves X percent, cma gets the rest */
- tmp = ((u64)bank->size) *
- (100 - cma_data.prm_low_kern_rsv_pct);
- rem = do_div(tmp, 100);
- total = tmp + rem;
- } else {
- if (bank->size >= cma_data.prm_kern_rsv_mb) {
- total = bank->size - cma_data.prm_kern_rsv_mb;
- } else {
- pr_debug("bank start=0x%pa size=0x%pa is smaller than cma_data.prm_kern_rsv_mb=0x%llx - skipping\n",
- &bank->start,
- &bank->size,
- cma_data.prm_kern_rsv_mb);
- return -EINVAL;
- }
- }
- } else if (bank->start >= VME_A32_MAX && bank->size > SZ_64M) {
- /*
- * Nexus can't use the address extension range yet, just reserve
- * 64 MiB in these areas until we have a firmer specification.
- */
- total = SZ_64M;
- } else {
- total = bank->size;
- }
-
- /* Subtract the size of any DT-based (/memreserve/) memblock
- * reservations that overlap with the current range from the total.
- */
- bytes_reserved = parse_static_rsv_entries(bank->start, total);
- if (total >= bytes_reserved)
- total -= bytes_reserved;
-
- *size = round_down(total, alignment);
-
+ cma_rsv_setup_data[n_cma_regions].addr = addr;
+ cma_rsv_setup_data[n_cma_regions].size = size;
+ n_cma_regions++;
return 0;
}
/*
- * Create maximum-sized CMA regions for each memblock.
- *
- * This function MUST be called by the platform 'reserve' function.
- *
- * Notes:
- * - Memblocks are initially generated based on the ranges specified in the
- * DT memory node.
- *
- * - After initialization by the DT memory node, a memblock may be split,
- * depending on whether it spans a special memory region (such as the
- * arm_lowmem_limit).
- *
- * - The kernel lives in valuable low-memory. Therefore, it is not possible to
- * create a CMA region which spans the entire low-memory memblock. Thus a
- * "fudge" constant, param_cma_kern_rsv, is used to adjust the low-memory
- * CMA region.
+ * We don't do too much checking here because it will be handled by the CMA
+ * reservation code
*/
-void __init cma_reserve(void)
+static int __init cma_rsv_setup(char *str)
{
+ phys_addr_t addr = 0;
+ phys_addr_t size = 0;
+ int ret;
+
+ size = (phys_addr_t) memparse(str, &str);
+ if (*str == '@')
+ addr = (phys_addr_t)memparse(str + 1, &str);
+
+ if (size == 0) {
+ pr_info("disabling reserved memory\n");
+ cma_disabled = true;
+ return 0;
+ }
+
+ ret = __cma_rsv_setup(addr, size);
+ if (!ret)
+ brcmstb_memory_override_defaults = true;
+ return ret;
+}
+early_param("brcm_cma", cma_rsv_setup);
+
+static void __init cma_reserve_one(struct membank *bank, int region_idx)
+{
+ struct cma_rsv_region *region = &cma_rsv_setup_data[region_idx];
+ struct cma *tmp_cma_area;
+ phys_addr_t base;
+ phys_addr_t size;
int rc;
+
+ if ((bank->start <= region->addr) &&
+ ((bank->start + bank->size) >=
+ (region->addr + region->size))) {
+ base = region->addr;
+ size = region->size;
+ pr_debug("reserve: %pa, %pa\n", &base, &size);
+ rc = dma_contiguous_reserve_area(size, base, 0,
+ &tmp_cma_area, 1);
+ if (rc) {
+ pr_err("reservation failed (base=%pa,size=%pa,rc=%d)\n",
+ &base, &size, rc);
+ /*
+ * This will help us see if a stray memory reservation
+ * is fragmenting the memblock when 'debug' is passed
+ * to the kernel at boot.
+ */
+ memblock_dump_all();
+ } else {
+ struct cma_pdev_data *pd =
+ &cma_data.regions[cma_data.nr_regions_valid];
+ pd->start = PFN_PHYS(tmp_cma_area->base_pfn);
+ pd->size = size;
+ /* Pre-allocate all regions */
+ pd->do_prealloc = 1;
+ pd->cma_area = tmp_cma_area;
+ cma_data.nr_regions_valid++;
+ }
+ }
+}
+
+void __init cma_setup_defaults(void)
+{
int iter;
for_each_bank(iter, &meminfo) {
- struct cma *tmp_cma_area;
- struct membank *bank = &meminfo.bank[iter];
- phys_addr_t size = 0;
- phys_addr_t bank_end = bank->start + bank->size;
+ phys_addr_t start, size;
- if (cma_data.nr_regions_valid == NR_BANKS)
- pr_err("cma_data.regions overflow\n");
-
- if (cma_calc_rsv_range(iter, &size))
+ /* fill in start and size */
+ if (brcmstb_memory_get_default_reserve(iter, &start, &size))
continue;
- pr_debug("try to reserve 0x%pa in 0x%pa-0x%pa\n", &size,
- &bank->start, &bank_end);
- rc = dma_contiguous_reserve_area(size, bank->start,
- bank_end, &tmp_cma_area);
- if (rc) {
- pr_err("reservation failed (bank=0x%pa-0x%pa,size=0x%pa,rc=%d)\n",
- &bank->start, &bank_end, &size, rc);
- /*
- * This will help us see if a stray memory reservation
- * is fragmenting the memblock.
- */
- memblock_debug = 1;
- memblock_dump_all();
- memblock_debug = 0;
- } else {
- cma_data.regions[cma_data.nr_regions_valid].start =
- PFN_PHYS(tmp_cma_area->base_pfn);
- cma_data.regions[cma_data.nr_regions_valid].size = size;
+ (void) __cma_rsv_setup(start, size);
+ }
+}
- /* Pre-allocate all regions */
- cma_data.regions[cma_data.nr_regions_valid].do_prealloc
- = 1;
- cma_data.regions[cma_data.nr_regions_valid].cma_area =
- tmp_cma_area;
- cma_data.nr_regions_valid++;
- }
+void __init cma_reserve(void)
+{
+ int iter;
+
+ if (cma_disabled) {
+ n_cma_regions = 0;
+ return;
+ }
+
+ if (brcmstb_default_reserve == BRCMSTB_RESERVE_CMA &&
+ !n_cma_regions &&
+ !brcmstb_memory_override_defaults)
+ cma_setup_defaults();
+
+ for_each_bank(iter, &meminfo) {
+ int i;
+
+ for (i = 0; i < n_cma_regions; ++i)
+ cma_reserve_one(&meminfo.bank[iter], i);
}
}
@@ -423,64 +339,6 @@
return 0;
}
-#define NUM_BUS_RANGES 10
-#define BUS_RANGE_ULIMIT_SHIFT 4
-#define BUS_RANGE_LLIMIT_SHIFT 4
-#define BUS_RANGE_PA_SHIFT 12
-
-enum {
- BUSNUM_MCP0 = 0x4,
- BUSNUM_MCP1 = 0x5,
- BUSNUM_MCP2 = 0x6,
-};
-
-/*
- * If the DT nodes are handy, determine which MEMC holds the specified
- * physical address.
- */
-static int phys_addr_to_memc(phys_addr_t pa)
-{
- int memc = -1;
- int i;
- struct device_node *np;
- void __iomem *cpubiuctrl = NULL;
- void __iomem *curr;
-
- np = of_find_compatible_node(NULL, NULL, "brcm,brcmstb-cpu-biu-ctrl");
- if (!np)
- goto cleanup;
-
- cpubiuctrl = of_iomap(np, 0);
- if (!cpubiuctrl)
- goto cleanup;
-
- for (i = 0, curr = cpubiuctrl; i < NUM_BUS_RANGES; i++, curr += 8) {
- const u64 ulimit_raw = readl(curr);
- const u64 llimit_raw = readl(curr + 4);
- const u64 ulimit =
- ((ulimit_raw >> BUS_RANGE_ULIMIT_SHIFT)
- << BUS_RANGE_PA_SHIFT) | 0xfff;
- const u64 llimit = (llimit_raw >> BUS_RANGE_LLIMIT_SHIFT)
- << BUS_RANGE_PA_SHIFT;
- const u32 busnum = (u32)(ulimit_raw & 0xf);
-
- if (pa >= llimit && pa <= ulimit) {
- if (busnum >= BUSNUM_MCP0 && busnum <= BUSNUM_MCP2) {
- memc = busnum - BUSNUM_MCP0;
- break;
- }
- }
- }
-
-cleanup:
- if (cpubiuctrl)
- iounmap(cpubiuctrl);
-
- of_node_put(np);
-
- return memc;
-}
-
/**
* cma_dev_get_cma_dev() - Get a cma_dev * by memc index
*
@@ -1043,7 +901,7 @@
cma_dev->range.base = data->start;
cma_dev->range.size = data->size;
cma_dev->cma_dev_index = pdev->id;
- cma_dev->memc = phys_addr_to_memc(data->start);
+ cma_dev->memc = brcmstb_memory_phys_addr_to_memc(data->start);
if (!data->cma_area) {
pr_err("null cma area\n");
@@ -1122,13 +980,6 @@
u32 size;
size = cma_dev->range.size;
-#ifdef CONFIG_BRCMSTB_USE_MEGA_BARRIER
- /* Every CMA device needs to accomodate the mega-barrier page if a
- * pre-allocation is needed.
- */
- if (size > PAGE_SIZE)
- size -= PAGE_SIZE;
-#endif
ret = cma_dev_get_mem(cma_dev, &addr, size, 0);
if (ret)
diff --git a/drivers/soc/brcmstb/common.c b/drivers/soc/brcmstb/common.c
new file mode 100644
index 0000000..c262c02
--- /dev/null
+++ b/drivers/soc/brcmstb/common.c
@@ -0,0 +1,33 @@
+/*
+ * Copyright © 2014 NVIDIA Corporation
+ * Copyright © 2015 Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/of.h>
+
+#include <soc/brcmstb/common.h>
+
+static const struct of_device_id brcmstb_machine_match[] = {
+ { .compatible = "brcm,brcmstb", },
+ { }
+};
+
+bool soc_is_brcmstb(void)
+{
+ struct device_node *root;
+
+ root = of_find_node_by_path("/");
+ if (!root)
+ return false;
+
+ return of_match_node(brcmstb_machine_match, root) != NULL;
+}
diff --git a/drivers/soc/brcmstb/irq0-stub.c b/drivers/soc/brcmstb/irq0-stub.c
new file mode 100644
index 0000000..9a8a006
--- /dev/null
+++ b/drivers/soc/brcmstb/irq0-stub.c
@@ -0,0 +1,44 @@
+/*
+ * Copyright (C) 2015 Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation version 2.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/brcmstb/brcmstb.h>
+#include <linux/syscore_ops.h>
+#include <soc/brcmstb/common.h>
+
+static void __brcmstb_irq0_init(void)
+{
+ BDEV_WR(BCHP_IRQ0_IRQEN, BCHP_IRQ0_IRQEN_uarta_irqen_MASK
+ | BCHP_IRQ0_IRQEN_uartb_irqen_MASK
+ | BCHP_IRQ0_IRQEN_uartc_irqen_MASK
+ );
+}
+
+#ifdef CONFIG_PM_SLEEP
+static struct syscore_ops brcmstb_irq0_syscore_ops = {
+ .resume = __brcmstb_irq0_init,
+};
+#endif
+
+static int brcmstb_irq0_init(void)
+{
+ if (!soc_is_brcmstb())
+ return 0;
+
+ __brcmstb_irq0_init();
+#ifdef CONFIG_PM_SLEEP
+ register_syscore_ops(&brcmstb_irq0_syscore_ops);
+#endif
+
+ return 0;
+}
+early_initcall(brcmstb_irq0_init);
diff --git a/drivers/soc/brcmstb/memory.c b/drivers/soc/brcmstb/memory.c
new file mode 100644
index 0000000..2c249fc
--- /dev/null
+++ b/drivers/soc/brcmstb/memory.c
@@ -0,0 +1,465 @@
+/*
+ * Copyright © 2015 Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * A copy of the GPL is available at
+ * http://www.broadcom.com/licenses/GPLv2.php or from the Free Software
+ * Foundation at https://www.gnu.org/licenses/ .
+ */
+
+#include <asm/page.h>
+#include <asm/setup.h> /* for meminfo */
+#include <linux/device.h>
+#include <linux/io.h>
+#include <linux/libfdt.h>
+#include <linux/memblock.h>
+#include <linux/mm.h> /* for high_memory */
+#include <linux/of_address.h>
+#include <linux/of_fdt.h>
+#include <linux/vme.h>
+#include <linux/brcmstb/bmem.h>
+#include <linux/brcmstb/cma_driver.h>
+#include <linux/brcmstb/memory_api.h>
+
+/* -------------------- Constants -------------------- */
+
+#define DEFAULT_LOWMEM_PCT 20 /* used if only one membank */
+
+/* Macros to help extract property data */
+#define U8TOU32(b, offs) \
+ ((((u32)b[0+offs] << 0) & 0x000000ff) | \
+ (((u32)b[1+offs] << 8) & 0x0000ff00) | \
+ (((u32)b[2+offs] << 16) & 0x00ff0000) | \
+ (((u32)b[3+offs] << 24) & 0xff000000))
+
+#define DT_PROP_DATA_TO_U32(b, offs) (fdt32_to_cpu(U8TOU32(b, offs)))
+
+/* Constants used when retrieving memc info */
+#define NUM_BUS_RANGES 10
+#define BUS_RANGE_ULIMIT_SHIFT 4
+#define BUS_RANGE_LLIMIT_SHIFT 4
+#define BUS_RANGE_PA_SHIFT 12
+
+enum {
+ BUSNUM_MCP0 = 0x4,
+ BUSNUM_MCP1 = 0x5,
+ BUSNUM_MCP2 = 0x6,
+};
+
+/* -------------------- Shared and local vars -------------------- */
+
+const enum brcmstb_reserve_type brcmstb_default_reserve = BRCMSTB_RESERVE_CMA;
+bool brcmstb_memory_override_defaults = false;
+
+static struct {
+ struct brcmstb_range range[MAX_BRCMSTB_RESERVED_RANGE];
+ int count;
+} reserved_init;
+
+/* -------------------- Functions -------------------- */
+
+/*
+ * If the DT nodes are handy, determine which MEMC holds the specified
+ * physical address.
+ */
+int brcmstb_memory_phys_addr_to_memc(phys_addr_t pa)
+{
+ int memc = -1;
+ int i;
+ struct device_node *np;
+ void __iomem *cpubiuctrl = NULL;
+ void __iomem *curr;
+
+ np = of_find_compatible_node(NULL, NULL, "brcm,brcmstb-cpu-biu-ctrl");
+ if (!np)
+ goto cleanup;
+
+ cpubiuctrl = of_iomap(np, 0);
+ if (!cpubiuctrl)
+ goto cleanup;
+
+ for (i = 0, curr = cpubiuctrl; i < NUM_BUS_RANGES; i++, curr += 8) {
+ const u64 ulimit_raw = readl(curr);
+ const u64 llimit_raw = readl(curr + 4);
+ const u64 ulimit =
+ ((ulimit_raw >> BUS_RANGE_ULIMIT_SHIFT)
+ << BUS_RANGE_PA_SHIFT) | 0xfff;
+ const u64 llimit = (llimit_raw >> BUS_RANGE_LLIMIT_SHIFT)
+ << BUS_RANGE_PA_SHIFT;
+ const u32 busnum = (u32)(ulimit_raw & 0xf);
+
+ if (pa >= llimit && pa <= ulimit) {
+ if (busnum >= BUSNUM_MCP0 && busnum <= BUSNUM_MCP2) {
+ memc = busnum - BUSNUM_MCP0;
+ break;
+ }
+ }
+ }
+
+cleanup:
+ if (cpubiuctrl)
+ iounmap(cpubiuctrl);
+
+ of_node_put(np);
+
+ return memc;
+}
+
+static int populate_memc(struct brcmstb_memory *mem, int addr_cells,
+ int size_cells)
+{
+ const void *fdt = initial_boot_params;
+ const int mem_offset = fdt_path_offset(fdt, "/memory");
+ const struct fdt_property *prop;
+ int proplen, cellslen;
+ int i;
+
+ if (mem_offset < 0) {
+ pr_err("No memory node?\n");
+ return -EINVAL;
+ }
+
+ prop = fdt_get_property(fdt, mem_offset, "reg", &proplen);
+ cellslen = (int)sizeof(u32) * (addr_cells + size_cells);
+ if ((proplen % cellslen) != 0) {
+ pr_err("Invalid length of reg prop: %d\n", proplen);
+ return -EINVAL;
+ }
+
+ for (i = 0; i < proplen / cellslen; ++i) {
+ u64 addr = 0;
+ u64 size = 0;
+ int memc_idx;
+ int range_idx;
+ int j;
+
+ for (j = 0; j < addr_cells; ++j) {
+ int offset = (cellslen * i) + (sizeof(u32) * j);
+ addr |= (u64)DT_PROP_DATA_TO_U32(prop->data, offset) <<
+ ((addr_cells - j - 1) * 32);
+ }
+ for (j = 0; j < size_cells; ++j) {
+ int offset = (cellslen * i) +
+ (sizeof(u32) * (j + addr_cells));
+ size |= (u64)DT_PROP_DATA_TO_U32(prop->data, offset) <<
+ ((size_cells - j - 1) * 32);
+ }
+
+ if ((phys_addr_t)addr != addr) {
+ pr_err("phys_addr_t is smaller than provided address 0x%llx!\n",
+ addr);
+ return -EINVAL;
+ }
+
+ memc_idx = brcmstb_memory_phys_addr_to_memc((phys_addr_t)addr);
+ if (memc_idx == -1) {
+ pr_err("address 0x%llx does not appear to be in any memc\n",
+ addr);
+ return -EINVAL;
+ }
+
+ range_idx = mem->memc[memc_idx].count;
+ if (mem->memc[memc_idx].count >= MAX_BRCMSTB_RANGE)
+ pr_warn("%s: Exceeded max ranges for memc%d\n",
+ __func__, memc_idx);
+ else {
+ mem->memc[memc_idx].range[range_idx].addr = addr;
+ mem->memc[memc_idx].range[range_idx].size = size;
+ }
+ ++mem->memc[memc_idx].count;
+ }
+
+ return 0;
+}
+
+static int populate_lowmem(struct brcmstb_memory *mem)
+{
+#ifdef CONFIG_ARM
+ mem->lowmem.range[0].addr = __pa(PAGE_OFFSET);
+ mem->lowmem.range[0].size = (unsigned long)high_memory - PAGE_OFFSET;
+ ++mem->lowmem.count;
+ return 0;
+#else
+ return -ENOSYS;
+#endif
+}
+
+static int populate_bmem(struct brcmstb_memory *mem)
+{
+#ifdef CONFIG_BRCMSTB_BMEM
+ phys_addr_t addr, size;
+ int i;
+
+ for (i = 0; i < MAX_BRCMSTB_RANGE; ++i) {
+ if (bmem_region_info(i, &addr, &size))
+ break; /* no more regions */
+ mem->bmem.range[i].addr = addr;
+ mem->bmem.range[i].size = size;
+ ++mem->bmem.count;
+ }
+ if (i >= MAX_BRCMSTB_RANGE) {
+ while (bmem_region_info(i, &addr, &size) == 0) {
+ pr_warn("%s: Exceeded max ranges\n", __func__);
+ ++mem->bmem.count;
+ }
+ }
+
+ return 0;
+#else
+ return -ENOSYS;
+#endif
+}
+
+static int populate_cma(struct brcmstb_memory *mem)
+{
+#ifdef CONFIG_BRCMSTB_CMA
+ int i;
+
+ for (i = 0; i < CMA_NUM_RANGES; ++i) {
+ struct cma_dev *cdev = cma_dev_get_cma_dev(i);
+ if (cdev == NULL)
+ break;
+ if (i >= MAX_BRCMSTB_RANGE)
+ pr_warn("%s: Exceeded max ranges\n", __func__);
+ else {
+ mem->cma.range[i].addr = cdev->range.base;
+ mem->cma.range[i].size = cdev->range.size;
+ }
+ ++mem->cma.count;
+ }
+
+ return 0;
+#else
+ return -ENOSYS;
+#endif
+}
+
+static int populate_reserved(struct brcmstb_memory *mem)
+{
+#ifdef CONFIG_HAVE_MEMBLOCK
+ memcpy(&mem->reserved, &reserved_init, sizeof(reserved_init));
+ return 0;
+#else
+ return -ENOSYS;
+#endif
+}
+
+/**
+ * brcmstb_memory_get_default_reserve() - find default reservation for given ID
+ * @bank_nr: bank index
+ * @pstart: pointer to the start address (output)
+ * @psize: pointer to the size address (output)
+ *
+ * NOTE: This interface will change in future kernels that do not have meminfo
+ *
+ * This takes in the bank number and determines the size and address of the
+ * default region reserved for refsw within the bank.
+ */
+int __init brcmstb_memory_get_default_reserve(int bank_nr,
+ phys_addr_t *pstart, phys_addr_t *psize)
+{
+ /* min alignment for mm core */
+ const phys_addr_t alignment =
+ PAGE_SIZE << max(MAX_ORDER - 1, pageblock_order);
+ struct membank *bank = &meminfo.bank[bank_nr];
+ phys_addr_t start = bank->start;
+ phys_addr_t size = 0;
+ phys_addr_t newstart, newsize;
+ int i;
+
+ if (!pstart || !psize)
+ return -EFAULT;
+
+ if (bank_nr == 0) {
+ if (meminfo.nr_banks == 1) {
+ u32 rem;
+ u64 tmp;
+
+ BUG_ON(bank->highmem);
+ if (bank->size < SZ_32M) {
+ pr_err("low memory too small for default bmem\n");
+ return -EINVAL;
+ }
+
+ /* kernel reserves X percent, bmem gets the rest */
+ tmp = ((u64)bank->size) * (100 - DEFAULT_LOWMEM_PCT);
+ rem = do_div(tmp, 100);
+ size = tmp + rem;
+ start = bank->start + bank->size - size;
+ } else {
+ /* If more than one bank, don't use first bank */
+ return -EINVAL;
+ }
+ } else if (bank->start >= VME_A32_MAX && bank->size > SZ_64M) {
+ /*
+ * Nexus doesn't use the address extension range yet, just
+ * reserve 64 MiB in these areas until we have a firmer
+ * specification
+ */
+ size = SZ_64M;
+ } else {
+ size = bank->size;
+ }
+
+ /*
+ * To keep things simple, we only handle the case where reserved memory
+ * is at the start or end of a region.
+ */
+ i = 0;
+ while (i < memblock.reserved.cnt) {
+ struct memblock_region *region = &memblock.reserved.regions[i];
+ newstart = start;
+ newsize = size;
+
+ if (start >= region->base &&
+ start < region->base + region->size) {
+ newstart = region->base + region->size;
+ newsize = size - (newstart - start);
+ } else if (start < region->base) {
+ if (start + size < region->base + region->size) {
+ newsize = region->base - start;
+ } else if (start + size >=
+ region->base + region->size) {
+ /* unhandled condition */
+ pr_err("%s: Split region %pa@%pa, reserve will fail\n",
+ __func__, &size, &start);
+ /* enable 'debug' param for dump output */
+ memblock_dump_all();
+ return -EINVAL;
+ }
+ }
+ /* see if we had any modifications */
+ if (newsize != size || newstart != start) {
+ pr_debug("%s: moving default region from %pa@%pa to %pa@%pa\n",
+ __func__, &size, &start, &newsize,
+ &newstart);
+ size = newsize;
+ start = newstart;
+ i = 0; /* start over */
+ } else {
+ ++i;
+ }
+ }
+
+ /* Fix up alignment */
+ newstart = ALIGN(start, alignment);
+ if (newstart != start) {
+ pr_debug("adjusting start from %pa to %pa\n",
+ &start, &newstart);
+ start = newstart;
+ }
+ newsize = round_down(size, alignment);
+ if (newsize != size) {
+ pr_debug("adjusting size from %pa to %pa\n",
+ &size, &newsize);
+ size = newsize;
+ }
+
+ if (size == 0) {
+ pr_debug("size available in bank was 0 - skipping\n");
+ return -EINVAL;
+ }
+
+ *pstart = start;
+ *psize = size;
+
+ return 0;
+}
+
+/**
+ * brcmstb_memory_reserve() - fill in static brcmstb_memory structure
+ *
+ * This is a boot-time initialization function used to copy the information
+ * stored in the memblock reserve function that is discarded after boot.
+ */
+void __init brcmstb_memory_reserve(void)
+{
+#ifdef CONFIG_HAVE_MEMBLOCK
+ struct memblock_type *type = &memblock.reserved;
+ int i;
+
+ for (i = 0; i < type->cnt; ++i) {
+ struct memblock_region *region = &type->regions[i];
+
+ if (i >= MAX_BRCMSTB_RESERVED_RANGE)
+ pr_warn_once("%s: Exceeded max ranges\n", __func__);
+ else {
+ reserved_init.range[i].addr = region->base;
+ reserved_init.range[i].size = region->size;
+ }
+ ++reserved_init.count;
+ }
+#else
+ pr_err("No memblock, cannot get reserved range\n");
+#endif
+}
+
+/*
+ * brcmstb_memory_get() - fill in brcmstb_memory structure
+ * @mem: pointer to allocated struct brcmstb_memory to fill
+ *
+ * The brcmstb_memory struct is required by the brcmstb middleware to
+ * determine how to set up its memory heaps. This function expects that the
+ * passed pointer is valid. The struct does not need to have be zeroed
+ * before calling.
+ */
+int brcmstb_memory_get(struct brcmstb_memory *mem)
+{
+ const void *fdt = initial_boot_params;
+ const struct fdt_property *prop;
+ int addr_cells = 1, size_cells = 1;
+ int proplen;
+ int ret;
+
+ if (!mem)
+ return -EFAULT;
+
+ if (!fdt) {
+ pr_err("No device tree?\n");
+ return -EINVAL;
+ }
+
+ /* Get root size and address cells if specified */
+ prop = fdt_get_property(fdt, 0, "#size-cells", &proplen);
+ if (prop)
+ size_cells = DT_PROP_DATA_TO_U32(prop->data, 0);
+ pr_debug("size_cells = %x\n", size_cells);
+
+ prop = fdt_get_property(fdt, 0, "#address-cells", &proplen);
+ if (prop)
+ addr_cells = DT_PROP_DATA_TO_U32(prop->data, 0);
+ pr_debug("address_cells = %x\n", addr_cells);
+
+ memset(mem, 0, sizeof(*mem));
+
+ ret = populate_memc(mem, addr_cells, size_cells);
+ if (ret)
+ return ret;
+
+ ret = populate_lowmem(mem);
+ if (ret)
+ return ret;
+
+ ret = populate_bmem(mem);
+ if (ret)
+ pr_debug("bmem is disabled\n");
+
+ ret = populate_cma(mem);
+ if (ret)
+ pr_debug("cma is disabled\n");
+
+ ret = populate_reserved(mem);
+ if (ret)
+ return ret;
+
+ return 0;
+}
+EXPORT_SYMBOL(brcmstb_memory_get);
diff --git a/drivers/soc/brcmstb/pm/Makefile b/drivers/soc/brcmstb/pm/Makefile
new file mode 100644
index 0000000..5bb9d55
--- /dev/null
+++ b/drivers/soc/brcmstb/pm/Makefile
@@ -0,0 +1,2 @@
+obj-y += pm.o s2.o regsave.o
+obj-$(CONFIG_BRCMSTB_XPT_HASH) += xpt_dma.o
diff --git a/arch/arm/mach-bcm/aon_defs.h b/drivers/soc/brcmstb/pm/aon_defs.h
similarity index 100%
rename from arch/arm/mach-bcm/aon_defs.h
rename to drivers/soc/brcmstb/pm/aon_defs.h
diff --git a/arch/arm/mach-bcm/pm-brcmstb.c b/drivers/soc/brcmstb/pm/pm.c
similarity index 93%
rename from arch/arm/mach-bcm/pm-brcmstb.c
rename to drivers/soc/brcmstb/pm/pm.c
index 3e6decb..3f3d26b 100644
--- a/arch/arm/mach-bcm/pm-brcmstb.c
+++ b/drivers/soc/brcmstb/pm/pm.c
@@ -1,5 +1,5 @@
/*
- * ARM-specific support for Broadcom STB S2 power management
+ * ARM-specific support for Broadcom STB S2/S3/S5 power management
*
* Copyright © 2014 Broadcom Corporation
*
@@ -37,8 +37,10 @@
#include <asm/suspend.h>
#include <asm/setup.h>
-#include "brcmstb.h"
-#include "pm-brcmstb.h"
+#include <linux/brcmstb/brcmstb.h>
+#include <soc/brcmstb/common.h>
+
+#include "pm.h"
#include "aon_defs.h"
#include "xpt_dma.h"
@@ -88,12 +90,15 @@
#define PM_INITIATE_FAIL 0xfe
/* Several chips have an old PM_INITIATE interface that doesn't ACK commands */
-#define PM_INITIATE_NO_ACK (IS_ENABLED(CONFIG_BCM7439A0) || \
- IS_ENABLED(CONFIG_BCM74371A0))
+#define PM_INITIATE_NO_ACK IS_ENABLED(CONFIG_BCM74371A0)
static struct brcmstb_pm_control ctrl;
static suspend_state_t suspend_state;
+#define MAX_EXCLUDE 16
+static int num_exclusions;
+static struct dma_region exclusions[MAX_EXCLUDE];
+
extern const unsigned long brcmstb_pm_do_s2_sz;
extern asmlinkage int brcmstb_pm_do_s2(void __iomem *aon_ctrl_base,
void __iomem *ddr_phy_pll_status);
@@ -187,6 +192,12 @@
if (ret)
pr_err("BSP handshake failed\n");
+ /*
+ * HACK: BSP may have internal race on the CLOCK_STOP command.
+ * Avoid touching the BSP for a few milliseconds.
+ */
+ mdelay(3);
+
return ret;
}
@@ -502,6 +513,9 @@
if (nregs < 0)
return nregs;
+ /* Flush out before hashing main memory */
+ flush_cache_all();
+
/* Get base pointers */
descs_pa = params_pa + offsetof(struct brcmstb_s3_params, descriptors);
descs = (struct mcpb_dma_desc *)params->descriptors;
@@ -515,6 +529,21 @@
return 0;
}
+int brcmstb_pm_mem_exclude(phys_addr_t addr, size_t len)
+{
+ if (num_exclusions >= MAX_EXCLUDE) {
+ pr_err("exclusion list is full\n");
+ return -ENOSPC;
+ }
+
+ exclusions[num_exclusions].addr = addr;
+ exclusions[num_exclusions].len = len;
+ num_exclusions++;
+
+ return 0;
+}
+EXPORT_SYMBOL(brcmstb_pm_mem_exclude);
+
/*
* This function is called on a new stack, so don't allow inlining (which will
* generate stack references on the old stack)
@@ -526,16 +555,13 @@
phys_addr_t reentry = virt_to_phys(&cpu_resume);
u32 flags = 0;
enum bsp_initiate_command cmd;
- int i, ret;
- /* exempt S3 parameters from hashing */
- struct dma_region except[] = {
- {
- .addr = params_pa,
- .len = sizeof(*params),
- },
- };
+ int i, ret, num_exclude;
- flush_cache_all();
+ ret = brcmstb_pm_mem_exclude(params_pa, sizeof(*params));
+ if (ret) {
+ pr_err("failed to add parameter exclusion region\n");
+ return ret;
+ }
/* Clear parameter structure */
memset(params, 0, sizeof(*params));
@@ -552,9 +578,13 @@
return -EIO;
}
+ /* Reset exclusion regions */
+ num_exclude = num_exclusions;
+ num_exclusions = 0;
+
/* Hash main memory */
- ret = brcmstb_pm_s3_main_memory_hash(params, params_pa, except,
- ARRAY_SIZE(except));
+ ret = brcmstb_pm_s3_main_memory_hash(params, params_pa, exclusions,
+ num_exclude);
if (ret)
return ret;
@@ -671,11 +701,6 @@
return ret;
}
-static void brcmstb_pm_finish(void)
-{
- brcmstb_irq0_init();
-}
-
static void brcmstb_pm_end(void)
{
suspend_state = PM_SUSPEND_ON;
@@ -698,7 +723,6 @@
.end = brcmstb_pm_end,
.prepare = brcmstb_pm_prepare,
.enter = brcmstb_pm_enter,
- .finish = brcmstb_pm_finish,
.valid = brcmstb_pm_valid,
};
@@ -789,13 +813,16 @@
return base;
}
-int brcmstb_pm_init(void)
+static int brcmstb_pm_init(void)
{
struct device_node *dn;
void __iomem *base;
int ret, i;
const struct ddr_phy_ofdata *ddr_phy_data;
+ if (!soc_is_brcmstb())
+ return 0;
+
/* AON ctrl registers */
base = brcmstb_ioremap_match(aon_ctrl_dt_ids, 0, NULL, NULL);
if (IS_ERR_OR_NULL(base)) {
@@ -883,5 +910,9 @@
out:
kfree(ctrl.s3_params);
+ pr_warn("PM: initialization failed with code %d\n", ret);
+
return ret;
}
+
+arch_initcall(brcmstb_pm_init);
diff --git a/arch/arm/mach-bcm/pm-brcmstb.h b/drivers/soc/brcmstb/pm/pm.h
similarity index 100%
rename from arch/arm/mach-bcm/pm-brcmstb.h
rename to drivers/soc/brcmstb/pm/pm.h
diff --git a/arch/arm/mach-bcm/regsave.c b/drivers/soc/brcmstb/pm/regsave.c
similarity index 100%
rename from arch/arm/mach-bcm/regsave.c
rename to drivers/soc/brcmstb/pm/regsave.c
diff --git a/arch/arm/mach-bcm/s2-brcmstb.S b/drivers/soc/brcmstb/pm/s2.S
similarity index 97%
rename from arch/arm/mach-bcm/s2-brcmstb.S
rename to drivers/soc/brcmstb/pm/s2.S
index bcdbe07..704c4ec 100644
--- a/arch/arm/mach-bcm/s2-brcmstb.S
+++ b/drivers/soc/brcmstb/pm/s2.S
@@ -14,7 +14,7 @@
#include <linux/linkage.h>
#include <asm/assembler.h>
-#include "pm-brcmstb.h"
+#include "pm.h"
.text
.align 3
diff --git a/arch/arm/mach-bcm/xpt_dma.c b/drivers/soc/brcmstb/pm/xpt_dma.c
similarity index 100%
rename from arch/arm/mach-bcm/xpt_dma.c
rename to drivers/soc/brcmstb/pm/xpt_dma.c
diff --git a/arch/arm/mach-bcm/xpt_dma.h b/drivers/soc/brcmstb/pm/xpt_dma.h
similarity index 100%
rename from arch/arm/mach-bcm/xpt_dma.h
rename to drivers/soc/brcmstb/pm/xpt_dma.h
diff --git a/arch/arm/mach-bcm/srpd-brcmstb.c b/drivers/soc/brcmstb/srpd.c
similarity index 100%
rename from arch/arm/mach-bcm/srpd-brcmstb.c
rename to drivers/soc/brcmstb/srpd.c
diff --git a/arch/arm/mach-bcm/wktmr-brcmstb.c b/drivers/soc/brcmstb/wktmr.c
similarity index 96%
rename from arch/arm/mach-bcm/wktmr-brcmstb.c
rename to drivers/soc/brcmstb/wktmr.c
index 5741682..61d60c1 100644
--- a/arch/arm/mach-bcm/wktmr-brcmstb.c
+++ b/drivers/soc/brcmstb/wktmr.c
@@ -151,18 +151,16 @@
timer->dev = dev;
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
- timer->base = devm_request_and_ioremap(dev, res);
- if (!timer->base)
- return -ENODEV;
+ timer->base = devm_ioremap_resource(dev, res);
+ if (IS_ERR(timer->base))
+ return PTR_ERR(timer->base);
/*
* Set wakeup capability before requesting wakeup interrupt, so we can
* process boot-time "wakeups" (e.g., from S5 soft-off)
*/
device_set_wakeup_capable(dev, true);
- ret = device_wakeup_enable(dev);
- if (ret)
- return ret;
+ device_wakeup_enable(dev);
timer->irq = platform_get_irq(pdev, 0);
if ((int)timer->irq < 0)
@@ -171,7 +169,7 @@
ret = devm_request_irq(dev, timer->irq, brcmstb_waketmr_irq, 0,
DRV_NAME, timer);
if (ret < 0)
- return -ENODEV;
+ return ret;
timer->reboot_notifier.notifier_call = brcmstb_waketmr_reboot;
register_reboot_notifier(&timer->reboot_notifier);
diff --git a/drivers/spi/spi-brcmstb.c b/drivers/spi/spi-brcmstb.c
index 4244495..e22a740 100644
--- a/drivers/spi/spi-brcmstb.c
+++ b/drivers/spi/spi-brcmstb.c
@@ -854,7 +854,7 @@
}
bcmspi_set_chip_select(priv, msg->spi->chip_select);
- /* first transfer - OPCODE_READ + 3-byte address */
+ /* first transfer - OPCODE_READ + {3,4}-byte address */
trans = list_entry(msg->transfers.next, struct spi_transfer,
transfer_list);
buf = (void *)trans->tx_buf;
@@ -868,21 +868,30 @@
priv->bspi_hw->flash_upper_addr_byte = 0;
#endif
- /*
- * addr coming into this function is a raw flash offset
- * we need to convert it to the BSPI address
- */
addr = (buf[idx] << 16) | (buf[idx+1] << 8) | buf[idx+2];
- addr = (addr + 0xc00000) & 0xffffff;
/* second transfer - read result into buffer */
trans = list_entry(msg->transfers.next->next, struct spi_transfer,
transfer_list);
buf = (void *)trans->rx_buf;
-
len = trans->len;
+#if CONFIG_BRCM_BSPI_MAJOR_VERS < 4
+ /*
+ * The address coming into this function is a raw flash offset. But
+ * for BSPI <= V3, we need to convert it to a remapped BSPI address.
+ * If it crosses a 4MB boundary, just revert back to using MSPI.
+ */
+ addr = (addr + 0xc00000) & 0xffffff;
+
+ if (ADDR_TO_4MBYTE_SEGMENT(addr) ^
+ ADDR_TO_4MBYTE_SEGMENT(addr + len - 1)) {
+ spin_unlock_irqrestore(&priv->lock, flags);
+ return -1;
+ }
+#endif
+
/* non-aligned and very short transfers are handled by MSPI */
if (unlikely(!DWORD_ALIGNED(addr) ||
!DWORD_ALIGNED(buf) ||
@@ -894,12 +903,6 @@
bcmspi_enable_bspi(priv);
- /* We assume address will never cross 4Mbyte boundary
- * within one transfer. If it does
- * read might be incorrect */
- BUG_ON(ADDR_TO_4MBYTE_SEGMENT(addr) ^
- ADDR_TO_4MBYTE_SEGMENT(addr+len-1));
-
len_in_dwords = (len + 3) >> 2;
/* initialize software parameters */
@@ -1214,8 +1217,9 @@
bcmspi_disable_bspi(priv);
#if CONFIG_BRCM_BSPI_MAJOR_VERS >= 4
- /* BSPI 4.1 on ARM (e.g., 7445a0) defaults to XOR enabled */
- priv->bspi_hw->xor_enable = 0;
+ /* Force a sane 1:1 mapping of BSPI address -> flash offset */
+ priv->bspi_hw->xor_enable = 1;
+ priv->bspi_hw->xor_value = 0;
#endif
priv->bspi_hw->b0_ctrl = 0;
diff --git a/drivers/thermal/Kconfig b/drivers/thermal/Kconfig
index 5f88d76..2d5d51b 100644
--- a/drivers/thermal/Kconfig
+++ b/drivers/thermal/Kconfig
@@ -189,8 +189,7 @@
config INTEL_POWERCLAMP
tristate "Intel PowerClamp idle injection driver"
depends on THERMAL
- depends on X86
- depends on CPU_SUP_INTEL
+ depends on (X86 && CPU_SUP_INTEL) || ARM
help
Enable this to enable Intel PowerClamp idle injection driver. This
enforce idle time which results in more package C-state residency. The
@@ -222,6 +221,10 @@
the Intel Thermal Daemon can use this information to allow the user
to select his laptop to run without turning on the fans.
+config BRCMSTB_THERMAL
+ tristate "Broadcom STB AVS TMON thermal driver"
+ depends on ARCH_BRCMSTB
+
menu "Texas Instruments thermal drivers"
source "drivers/thermal/ti-soc-thermal/Kconfig"
endmenu
diff --git a/drivers/thermal/Makefile b/drivers/thermal/Makefile
index 54e4ec9..b8a66a4 100644
--- a/drivers/thermal/Makefile
+++ b/drivers/thermal/Makefile
@@ -31,3 +31,4 @@
obj-$(CONFIG_X86_PKG_TEMP_THERMAL) += x86_pkg_temp_thermal.o
obj-$(CONFIG_TI_SOC_THERMAL) += ti-soc-thermal/
obj-$(CONFIG_ACPI_INT3403_THERMAL) += int3403_thermal.o
+obj-$(CONFIG_BRCMSTB_THERMAL) += brcmstb_thermal.o
diff --git a/drivers/thermal/brcmstb_thermal.c b/drivers/thermal/brcmstb_thermal.c
new file mode 100644
index 0000000..8782ffa
--- /dev/null
+++ b/drivers/thermal/brcmstb_thermal.c
@@ -0,0 +1,396 @@
+/*
+ * Broadcom STB AVS TMON thermal sensor driver
+ *
+ * Copyright (C) 2015 Broadcom Corporation
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#define DRV_NAME "brcmstb_thermal"
+
+#define pr_fmt(fmt) DRV_NAME ": " fmt
+
+#include <linux/bitops.h>
+#include <linux/device.h>
+#include <linux/err.h>
+#include <linux/io.h>
+#include <linux/irqreturn.h>
+#include <linux/interrupt.h>
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/platform_device.h>
+#include <linux/of_device.h>
+#include <linux/thermal.h>
+
+#define AVS_TMON_STATUS 0x00
+ #define AVS_TMON_STATUS_valid_msk BIT(11)
+ #define AVS_TMON_STATUS_data_msk GENMASK(10, 1)
+ #define AVS_TMON_STATUS_data_shift 1
+
+#define AVS_TMON_EN_OVERTEMP_RESET 0x04
+ #define AVS_TMON_EN_OVERTEMP_RESET_msk BIT(0)
+
+#define AVS_TMON_RESET_THRESH 0x08
+ #define AVS_TMON_RESET_THRESH_msk GENMASK(10, 1)
+ #define AVS_TMON_RESET_THRESH_shift 1
+
+#define AVS_TMON_INT_IDLE_TIME 0x10
+
+#define AVS_TMON_EN_TEMP_INT_SRCS 0x14
+ #define AVS_TMON_EN_TEMP_INT_SRCS_high BIT(1)
+ #define AVS_TMON_EN_TEMP_INT_SRCS_low BIT(0)
+
+#define AVS_TMON_INT_THRESH 0x18
+ #define AVS_TMON_INT_THRESH_high_msk GENMASK(26, 17)
+ #define AVS_TMON_INT_THRESH_high_shift 17
+ #define AVS_TMON_INT_THRESH_low_msk GENMASK(10, 1)
+ #define AVS_TMON_INT_THRESH_low_shift 1
+
+#define AVS_TMON_TEMP_INT_CODE 0x1c
+#define AVS_TMON_TP_TEST_ENABLE 0x20
+
+enum avs_tmon_trip_type {
+ TMON_TRIP_TYPE_LOW = 0,
+ TMON_TRIP_TYPE_HIGH,
+ TMON_TRIP_TYPE_RESET,
+ TMON_TRIP_TYPE_MAX,
+};
+
+struct avs_tmon_trip {
+ /* HW bit to enable the trip */
+ u32 enable_offs;
+ u32 enable_mask;
+
+ /* HW field to read the trip temperature */
+ u32 reg_offs;
+ u32 reg_msk;
+ int reg_shift;
+};
+
+static struct avs_tmon_trip avs_tmon_trips[] = {
+ /* Trips when temperature is below threshold */
+ [TMON_TRIP_TYPE_LOW] = {
+ .enable_offs = AVS_TMON_EN_TEMP_INT_SRCS,
+ .enable_mask = AVS_TMON_EN_TEMP_INT_SRCS_low,
+ .reg_offs = AVS_TMON_INT_THRESH,
+ .reg_msk = AVS_TMON_INT_THRESH_low_msk,
+ .reg_shift = AVS_TMON_INT_THRESH_low_shift,
+ },
+ /* Trips when temperature is above threshold */
+ [TMON_TRIP_TYPE_HIGH] = {
+ .enable_offs = AVS_TMON_EN_TEMP_INT_SRCS,
+ .enable_mask = AVS_TMON_EN_TEMP_INT_SRCS_high,
+ .reg_offs = AVS_TMON_INT_THRESH,
+ .reg_msk = AVS_TMON_INT_THRESH_high_msk,
+ .reg_shift = AVS_TMON_INT_THRESH_high_shift,
+ },
+ /* Automatically resets chip when above threshold */
+ [TMON_TRIP_TYPE_RESET] = {
+ .enable_offs = AVS_TMON_EN_OVERTEMP_RESET,
+ .enable_mask = AVS_TMON_EN_OVERTEMP_RESET_msk,
+ .reg_offs = AVS_TMON_RESET_THRESH,
+ .reg_msk = AVS_TMON_RESET_THRESH_msk,
+ .reg_shift = AVS_TMON_RESET_THRESH_shift,
+ },
+};
+
+enum {
+ /*
+ * Using the of-thermal framework
+ */
+ AVS_TMON_OF_SENSOR_DRIVER,
+
+ /*
+ * Old DT bindings didn't include the of-sensor framework, so support a
+ * full zone implementation temporarily
+ */
+ AVS_TMON_ZONE_DRIVER,
+};
+
+struct brcmstb_thermal_priv {
+ void __iomem *tmon_base;
+ struct thermal_zone_device *thermal;
+
+ /* Did this driver register as a sensor or as a zone? */
+ int regtype;
+};
+
+/* Convert a HW code to a temperature reading (millidegree celsius) */
+static inline int avs_tmon_code_to_temp(u32 code)
+{
+ return (4100400U - code * 4870U) / 10U;
+}
+
+/*
+ * Convert a temperature value (millidegree celsius) to a HW code
+ *
+ * @temp: temperature to convert
+ * @low: if true, round toward the low side
+ */
+static inline u32 avs_tmon_temp_to_code(unsigned long temp, bool low)
+{
+ if (low)
+ return DIV_ROUND_UP(4100400U - temp * 10U, 4870U);
+ else
+ return (4100400U - temp * 10U) / 4870U;
+}
+
+static int brcmstb_get_temp(void *data, long *temp)
+{
+ struct brcmstb_thermal_priv *priv = data;
+ u32 val;
+
+ val = __raw_readl(priv->tmon_base + AVS_TMON_STATUS);
+
+ if (!(val & AVS_TMON_STATUS_valid_msk)) {
+ dev_err(&priv->thermal->device, "reading not valid\n");
+ return -EIO;
+ }
+
+ val = (val & AVS_TMON_STATUS_data_msk) >> AVS_TMON_STATUS_data_shift;
+
+ *temp = avs_tmon_code_to_temp(val);
+
+ return 0;
+}
+
+/*
+ * Active when the of-thermal framework is not used
+ */
+static int brcmstb_get_zone_temp(struct thermal_zone_device *thermal,
+ unsigned long *temp)
+{
+ return brcmstb_get_temp(thermal->devdata, temp);
+}
+
+static void avs_tmon_trip_enable(struct brcmstb_thermal_priv *priv,
+ enum avs_tmon_trip_type type, int en)
+{
+ struct avs_tmon_trip *trip = &avs_tmon_trips[type];
+ u32 val = __raw_readl(priv->tmon_base + trip->enable_offs);
+
+ pr_debug("%s trip, type %d\n", en ? "enable" : "disable", type);
+
+ if (en)
+ val |= trip->enable_mask;
+ else
+ val &= ~trip->enable_mask;
+
+ __raw_writel(val, priv->tmon_base + trip->enable_offs);
+}
+
+static int avs_tmon_get_trip_temp(struct brcmstb_thermal_priv *priv,
+ enum avs_tmon_trip_type type)
+{
+ struct avs_tmon_trip *trip = &avs_tmon_trips[type];
+ u32 val = __raw_readl(priv->tmon_base + trip->reg_offs);
+
+ val &= trip->reg_msk;
+ val >>= trip->reg_shift;
+
+ return avs_tmon_code_to_temp(val);
+}
+
+static void avs_tmon_set_trip_temp(struct brcmstb_thermal_priv *priv,
+ enum avs_tmon_trip_type type,
+ unsigned long temp)
+{
+ struct avs_tmon_trip *trip = &avs_tmon_trips[type];
+ u32 val, orig;
+
+ pr_debug("set temp %d to %lu\n", type, temp);
+
+ /* round toward low temp for the low interrupt */
+ val = avs_tmon_temp_to_code(temp, type == TMON_TRIP_TYPE_LOW);
+
+ /* TODO: Check for overflow? */
+ val <<= trip->reg_shift;
+ val &= trip->reg_msk;
+
+ orig = __raw_readl(priv->tmon_base + trip->reg_offs);
+ orig &= ~trip->reg_msk;
+ orig |= val;
+ __raw_writel(orig, priv->tmon_base + trip->reg_offs);
+}
+
+static int avs_tmon_get_intr_temp(struct brcmstb_thermal_priv *priv)
+{
+ u32 val;
+
+ val = __raw_readl(priv->tmon_base + AVS_TMON_TEMP_INT_CODE);
+ return avs_tmon_code_to_temp(val);
+}
+
+static irqreturn_t brcmstb_tmon_irq_thread(int irq, void *data)
+{
+ struct brcmstb_thermal_priv *priv = data;
+ unsigned long low, high, intr;
+
+ low = avs_tmon_get_trip_temp(priv, TMON_TRIP_TYPE_LOW);
+ high = avs_tmon_get_trip_temp(priv, TMON_TRIP_TYPE_HIGH);
+ intr = avs_tmon_get_intr_temp(priv);
+
+ dev_dbg(&priv->thermal->device, "low/intr/high: %lu/%lu/%lu\n",
+ low, intr, high);
+
+ /* Disable high-temp until next threshold shift */
+ if (intr >= high)
+ avs_tmon_trip_enable(priv, TMON_TRIP_TYPE_HIGH, 0);
+ /* Disable low-temp until next threshold shift */
+ if (intr <= low)
+ avs_tmon_trip_enable(priv, TMON_TRIP_TYPE_LOW, 0);
+
+ /*
+ * Notify using the interrupt temperature, in case the temperature
+ * changes before it can next be read out
+ */
+ thermal_zone_device_update_temp(priv->thermal, intr);
+
+ return IRQ_HANDLED;
+}
+
+static int brcmstb_set_trips(void *data, unsigned long low, unsigned long high)
+{
+ struct brcmstb_thermal_priv *priv = data;
+
+ pr_debug("set trips %lu <--> %lu\n", low, high);
+
+ if (low) {
+ avs_tmon_set_trip_temp(priv, TMON_TRIP_TYPE_LOW, low);
+ avs_tmon_trip_enable(priv, TMON_TRIP_TYPE_LOW, 1);
+ } else {
+ avs_tmon_trip_enable(priv, TMON_TRIP_TYPE_LOW, 0);
+ }
+
+ if (high < ULONG_MAX) {
+ avs_tmon_set_trip_temp(priv, TMON_TRIP_TYPE_HIGH, high);
+ avs_tmon_trip_enable(priv, TMON_TRIP_TYPE_HIGH, 1);
+ } else {
+ avs_tmon_trip_enable(priv, TMON_TRIP_TYPE_HIGH, 0);
+ }
+
+ return 0;
+}
+
+static struct thermal_zone_device_ops zone_ops = {
+ .get_temp = brcmstb_get_zone_temp,
+};
+
+static struct thermal_zone_of_device_ops of_ops = {
+ .get_temp = brcmstb_get_temp,
+ .set_trips = brcmstb_set_trips,
+};
+
+static const struct of_device_id brcmstb_thermal_id_table[] = {
+ { .compatible = "brcm,avs-tmon" },
+ {},
+};
+MODULE_DEVICE_TABLE(of, brcmstb_thermal_id_table);
+
+/*
+ * Deprecated: we should be using the of-thermal framework, rather than
+ * registering our own thermal zone. This is provided as a temporary help, in
+ * case of an old device tree which does not include the thermal-zones node and
+ * sensor phandles.
+ */
+static int brcmstb_thermal_zone_probe(struct platform_device *pdev,
+ struct brcmstb_thermal_priv *priv)
+{
+ priv->thermal = thermal_zone_device_register("avs_tmon", 0, 0, priv,
+ &zone_ops, NULL, 0, 0);
+ if (IS_ERR(priv->thermal)) {
+ dev_err(&pdev->dev, "failed to register zone device\n");
+ return PTR_ERR(priv->thermal);
+ }
+
+ priv->regtype = AVS_TMON_ZONE_DRIVER;
+ dev_info(&pdev->dev, "registered AVS TMON zone driver\n");
+
+ return 0;
+}
+
+static int brcmstb_thermal_probe(struct platform_device *pdev)
+{
+ struct thermal_zone_device *thermal;
+ struct brcmstb_thermal_priv *priv;
+ struct resource *res;
+ int irq, ret;
+
+ priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
+ if (!priv)
+ return -ENOMEM;
+
+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ priv->tmon_base = devm_ioremap_resource(&pdev->dev, res);
+ if (IS_ERR(priv->tmon_base))
+ return PTR_ERR(priv->tmon_base);
+
+ platform_set_drvdata(pdev, priv);
+
+ thermal = thermal_zone_of_sensor_register(&pdev->dev, 0, priv, &of_ops);
+ if (IS_ERR(thermal))
+ /*
+ * Fall back to registering our own zone, for legacy purposes
+ */
+ return brcmstb_thermal_zone_probe(pdev, priv);
+ priv->thermal = thermal;
+
+ irq = platform_get_irq(pdev, 0);
+ if (irq < 0) {
+ dev_err(&pdev->dev, "could not get IRQ\n");
+ ret = irq;
+ goto err;
+ }
+ ret = devm_request_threaded_irq(&pdev->dev, irq, NULL,
+ brcmstb_tmon_irq_thread, IRQF_ONESHOT,
+ DRV_NAME, priv);
+ if (ret < 0) {
+ dev_err(&pdev->dev, "could not request IRQ: %d\n", ret);
+ goto err;
+ }
+
+ priv->regtype = AVS_TMON_OF_SENSOR_DRIVER;
+ dev_info(&pdev->dev, "registered AVS TMON of-sensor driver\n");
+
+ return 0;
+
+err:
+ thermal_zone_device_unregister(thermal);
+ return ret;
+}
+
+static int brcmstb_thermal_exit(struct platform_device *pdev)
+{
+ struct brcmstb_thermal_priv *priv = platform_get_drvdata(pdev);
+ struct thermal_zone_device *thermal = priv->thermal;
+
+ if (priv->regtype == AVS_TMON_ZONE_DRIVER)
+ thermal_zone_device_unregister(thermal);
+ else
+ thermal_zone_of_sensor_unregister(&pdev->dev, priv->thermal);
+
+ return 0;
+}
+
+static struct platform_driver brcmstb_thermal_driver = {
+ .probe = brcmstb_thermal_probe,
+ .remove = brcmstb_thermal_exit,
+ .driver = {
+ .name = DRV_NAME,
+ .owner = THIS_MODULE,
+ .of_match_table = brcmstb_thermal_id_table,
+ },
+};
+module_platform_driver(brcmstb_thermal_driver);
+
+MODULE_LICENSE("GPL");
+MODULE_AUTHOR("Brian Norris");
+MODULE_DESCRIPTION("Broadcom STB AVS TMON thermal driver");
diff --git a/drivers/thermal/fair_share.c b/drivers/thermal/fair_share.c
index 944ba2f..6e0a3fb 100644
--- a/drivers/thermal/fair_share.c
+++ b/drivers/thermal/fair_share.c
@@ -23,6 +23,7 @@
*/
#include <linux/thermal.h>
+#include <trace/events/thermal.h>
#include "thermal_core.h"
@@ -34,6 +35,7 @@
{
int count = 0;
unsigned long trip_temp;
+ enum thermal_trip_type trip_type;
if (tz->trips == 0 || !tz->ops->get_trip_temp)
return 0;
@@ -43,6 +45,16 @@
if (tz->temperature < trip_temp)
break;
}
+
+ /*
+ * count > 0 only if temperature is greater than first trip
+ * point, in which case, trip_point = count - 1
+ */
+ if (count > 0) {
+ tz->ops->get_trip_type(tz, count - 1, &trip_type);
+ trace_thermal_zone_trip(tz, count - 1, trip_type);
+ }
+
return count;
}
diff --git a/drivers/thermal/intel_powerclamp.c b/drivers/thermal/intel_powerclamp.c
index a084325..292070d 100644
--- a/drivers/thermal/intel_powerclamp.c
+++ b/drivers/thermal/intel_powerclamp.c
@@ -52,12 +52,18 @@
#include <linux/seq_file.h>
#include <linux/sched/rt.h>
+#include <asm/hardirq.h>
+#ifdef CONFIG_X86
#include <asm/nmi.h>
#include <asm/msr.h>
#include <asm/mwait.h>
#include <asm/cpu_device_id.h>
#include <asm/idle.h>
-#include <asm/hardirq.h>
+
+static unsigned int target_mwait;
+#elif CONFIG_ARM
+#include <asm/proc-fns.h>
+#endif
#define MAX_TARGET_RATIO (50U)
/* For each undisturbed clamping period (no extra wake ups during idle time),
@@ -71,7 +77,6 @@
*/
#define DEFAULT_DURATION_JIFFIES (6)
-static unsigned int target_mwait;
static struct dentry *debug_dir;
/* user selected target */
@@ -178,6 +183,7 @@
"\twindow size results in slower response time but more smooth\n"
"\tclamping results. default to 2.");
+#ifdef CONFIG_X86
static void find_target_mwait(void)
{
unsigned int eax, ebx, ecx, edx;
@@ -255,6 +261,7 @@
return count;
}
+#endif
static void noop_timer(unsigned long foo)
{
@@ -325,6 +332,28 @@
}
}
+#ifdef CONFIG_X86
+static void inline powerclamp_get_cstate_inform(u64 *msr_now, u64 *tsc_now)
+{
+ *msr_now = pkg_state_counter();
+ rdtscll(*tsc_now);
+}
+#elif CONFIG_ARM
+static void inline powerclamp_get_cstate_inform(u64 *idle, u64 *wall)
+{
+ u64 _wall;
+ int cpu;
+
+ *idle = 0;
+ *wall = 0;
+
+ for_each_online_cpu(cpu) {
+ *idle += get_cpu_idle_time_us(cpu, &_wall);
+ *wall += _wall;
+ }
+}
+#endif
+
static bool powerclamp_adjust_controls(unsigned int target_ratio,
unsigned int guard, unsigned int win)
{
@@ -333,8 +362,7 @@
u64 val64;
/* check result for the last window */
- msr_now = pkg_state_counter();
- rdtscll(tsc_now);
+ powerclamp_get_cstate_inform(&msr_now, &tsc_now);
/* calculate pkg cstate vs tsc ratio */
if (!msr_last || !tsc_last)
@@ -362,6 +390,32 @@
return set_target_ratio + guard <= current_ratio;
}
+#ifdef CONFIG_X86
+static void powerclamp_enter_idle(void)
+{
+ unsigned long ecx = 1;
+ unsigned long eax = target_mwait;
+
+ /*
+ * REVISIT: may call enter_idle() to notify drivers who
+ * can save power during cpu idle. same for exit_idle()
+ */
+ local_touch_nmi();
+ stop_critical_timings();
+ mwait_idle_with_hints(eax, ecx);
+ start_critical_timings();
+ atomic_inc(&idle_wakeup_counter);
+}
+#elif CONFIG_ARM
+static void powerclamp_enter_idle(void)
+{
+ stop_critical_timings();
+ cpu_do_idle();
+ start_critical_timings();
+ atomic_inc(&idle_wakeup_counter);
+}
+#endif
+
static int clamp_thread(void *arg)
{
int cpunr = (unsigned long)arg;
@@ -437,20 +491,9 @@
preempt_disable();
tick_nohz_idle_enter();
/* mwait until target jiffies is reached */
- while (time_before(jiffies, target_jiffies)) {
- unsigned long ecx = 1;
- unsigned long eax = target_mwait;
+ while (time_before(jiffies, target_jiffies))
+ powerclamp_enter_idle();
- /*
- * REVISIT: may call enter_idle() to notify drivers who
- * can save power during cpu idle. same for exit_idle()
- */
- local_touch_nmi();
- stop_critical_timings();
- mwait_idle_with_hints(eax, ecx);
- start_critical_timings();
- atomic_inc(&idle_wakeup_counter);
- }
tick_nohz_idle_exit();
preempt_enable();
}
@@ -472,13 +515,12 @@
static u64 tsc_last;
static unsigned long jiffies_last;
- u64 msr_now;
+ u64 msr_now = 0;
unsigned long jiffies_now;
- u64 tsc_now;
+ u64 tsc_now = 0;
u64 val64;
- msr_now = pkg_state_counter();
- rdtscll(tsc_now);
+ powerclamp_get_cstate_inform(&msr_now, &tsc_now);
jiffies_now = jiffies;
/* calculate pkg cstate vs tsc ratio */
@@ -506,11 +548,13 @@
unsigned long cpu;
struct task_struct *thread;
+#ifdef CONFIG_X86
/* check if pkg cstate counter is completely 0, abort in this case */
if (!has_pkg_state_counter()) {
pr_err("pkg cstate counter not functional, abort\n");
return -EINVAL;
}
+#endif
set_target_ratio = clamp(set_target_ratio, 0U, MAX_TARGET_RATIO - 1);
/* prevent cpu hotplug */
@@ -668,6 +712,7 @@
.set_cur_state = powerclamp_set_cur_state,
};
+#ifdef CONFIG_X86
/* runs on Nehalem and later */
static const struct x86_cpu_id intel_powerclamp_ids[] = {
{ X86_VENDOR_INTEL, 6, 0x1a},
@@ -690,9 +735,11 @@
{}
};
MODULE_DEVICE_TABLE(x86cpu, intel_powerclamp_ids);
+#endif
static int powerclamp_probe(void)
{
+#ifdef CONFIG_X86
if (!x86_match_cpu(intel_powerclamp_ids)) {
pr_err("Intel powerclamp does not run on family %d model %d\n",
boot_cpu_data.x86, boot_cpu_data.x86_model);
@@ -706,7 +753,7 @@
/* find the deepest mwait value */
find_target_mwait();
-
+#endif
return 0;
}
diff --git a/drivers/thermal/of-thermal.c b/drivers/thermal/of-thermal.c
index 04b1be7..50a9599 100644
--- a/drivers/thermal/of-thermal.c
+++ b/drivers/thermal/of-thermal.c
@@ -30,27 +30,13 @@
#include <linux/err.h>
#include <linux/export.h>
#include <linux/string.h>
+#include <linux/thermal.h>
#include "thermal_core.h"
/*** Private data structures to represent thermal device tree data ***/
/**
- * struct __thermal_trip - representation of a point in temperature domain
- * @np: pointer to struct device_node that this trip point was created from
- * @temperature: temperature value in miliCelsius
- * @hysteresis: relative hysteresis in miliCelsius
- * @type: trip point type
- */
-
-struct __thermal_trip {
- struct device_node *np;
- unsigned long int temperature;
- unsigned long int hysteresis;
- enum thermal_trip_type type;
-};
-
-/**
* struct __thermal_bind_param - a match between trip and cooling device
* @cooling_device: a pointer to identify the referred cooling device
* @trip_id: the trip point index
@@ -77,8 +63,7 @@
* @num_tbps: number of thermal bind params
* @tbps: an array of thermal bind params (0..num_tbps - 1)
* @sensor_data: sensor private data used while reading temperature and trend
- * @get_temp: sensor callback to read temperature
- * @get_trend: sensor callback to read temperature trend
+ * @ops: set of callbacks to handle the thermal zone based on DT
*/
struct __thermal_zone {
@@ -88,7 +73,7 @@
/* trip data */
int ntrips;
- struct __thermal_trip *trips;
+ struct thermal_trip *trips;
/* cooling binding data */
int num_tbps;
@@ -96,8 +81,7 @@
/* sensor interface */
void *sensor_data;
- int (*get_temp)(void *, long *);
- int (*get_trend)(void *, long *);
+ const struct thermal_zone_of_device_ops *ops;
};
/*** DT thermal zone device callbacks ***/
@@ -107,34 +91,122 @@
{
struct __thermal_zone *data = tz->devdata;
- if (!data->get_temp)
+ if (!data->ops)
return -EINVAL;
- return data->get_temp(data->sensor_data, temp);
+ return data->ops->get_temp(data->sensor_data, temp);
+}
+
+static int of_thermal_set_trips(struct thermal_zone_device *tz,
+ unsigned long low, unsigned long high)
+{
+ struct __thermal_zone *data = tz->devdata;
+
+ if (!data->ops || !data->ops->set_trips)
+ return -ENOSYS;
+
+ return data->ops->set_trips(data->sensor_data, low, high);
+}
+
+/**
+ * of_thermal_get_ntrips - function to export number of available trip
+ * points.
+ * @tz: pointer to a thermal zone
+ *
+ * This function is a globally visible wrapper to get number of trip points
+ * stored in the local struct __thermal_zone
+ *
+ * Return: number of available trip points, -ENODEV when data not available
+ */
+int of_thermal_get_ntrips(struct thermal_zone_device *tz)
+{
+ struct __thermal_zone *data = tz->devdata;
+
+ if (!data || IS_ERR(data))
+ return -ENODEV;
+
+ return data->ntrips;
+}
+EXPORT_SYMBOL_GPL(of_thermal_get_ntrips);
+
+/**
+ * of_thermal_is_trip_valid - function to check if trip point is valid
+ *
+ * @tz: pointer to a thermal zone
+ * @trip: trip point to evaluate
+ *
+ * This function is responsible for checking if passed trip point is valid
+ *
+ * Return: true if trip point is valid, false otherwise
+ */
+bool of_thermal_is_trip_valid(struct thermal_zone_device *tz, int trip)
+{
+ struct __thermal_zone *data = tz->devdata;
+
+ if (!data || trip >= data->ntrips || trip < 0)
+ return false;
+
+ return true;
+}
+EXPORT_SYMBOL_GPL(of_thermal_is_trip_valid);
+
+/**
+ * of_thermal_get_trip_points - function to get access to a globally exported
+ * trip points
+ *
+ * @tz: pointer to a thermal zone
+ *
+ * This function provides a pointer to trip points table
+ *
+ * Return: pointer to trip points table, NULL otherwise
+ */
+const struct thermal_trip * const
+of_thermal_get_trip_points(struct thermal_zone_device *tz)
+{
+ struct __thermal_zone *data = tz->devdata;
+
+ if (!data)
+ return NULL;
+
+ return data->trips;
+}
+EXPORT_SYMBOL_GPL(of_thermal_get_trip_points);
+
+/**
+ * of_thermal_set_emul_temp - function to set emulated temperature
+ *
+ * @tz: pointer to a thermal zone
+ * @temp: temperature to set
+ *
+ * This function gives the ability to set emulated value of temperature,
+ * which is handy for debugging
+ *
+ * Return: zero on success, error code otherwise
+ */
+static int of_thermal_set_emul_temp(struct thermal_zone_device *tz,
+ unsigned long temp)
+{
+ struct __thermal_zone *data = tz->devdata;
+
+ if (!data->ops || !data->ops->set_emul_temp)
+ return -ENOSYS;
+
+ return data->ops->set_emul_temp(data->sensor_data, temp);
}
static int of_thermal_get_trend(struct thermal_zone_device *tz, int trip,
enum thermal_trend *trend)
{
struct __thermal_zone *data = tz->devdata;
- long dev_trend;
int r;
- if (!data->get_trend)
- return -EINVAL;
+ if (!data->ops || !data->ops->get_trend)
+ return -ENOSYS;
- r = data->get_trend(data->sensor_data, &dev_trend);
+ r = data->ops->get_trend(data->sensor_data, trip, trend);
if (r)
return r;
- /* TODO: These intervals might have some thresholds, but in core code */
- if (dev_trend > 0)
- *trend = THERMAL_TREND_RAISING;
- else if (dev_trend < 0)
- *trend = THERMAL_TREND_DROPPING;
- else
- *trend = THERMAL_TREND_STABLE;
-
return 0;
}
@@ -156,8 +228,8 @@
ret = thermal_zone_bind_cooling_device(thermal,
tbp->trip_id, cdev,
- tbp->min,
- tbp->max);
+ tbp->max,
+ tbp->min);
if (ret)
return ret;
}
@@ -304,7 +376,12 @@
return -EINVAL;
}
-static struct thermal_zone_device_ops of_thermal_ops = {
+static const struct thermal_zone_device_ops of_thermal_ops = {
+ .get_temp = of_thermal_get_temp,
+ .set_trips = of_thermal_set_trips,
+ .get_trend = of_thermal_get_trend,
+ .set_emul_temp = of_thermal_set_emul_temp,
+
.get_mode = of_thermal_get_mode,
.set_mode = of_thermal_set_mode,
@@ -324,8 +401,7 @@
static struct thermal_zone_device *
thermal_zone_of_add_sensor(struct device_node *zone,
struct device_node *sensor, void *data,
- int (*get_temp)(void *, long *),
- int (*get_trend)(void *, long *))
+ const struct thermal_zone_of_device_ops *ops)
{
struct thermal_zone_device *tzd;
struct __thermal_zone *tz;
@@ -336,13 +412,16 @@
tz = tzd->devdata;
+ if (!ops)
+ return ERR_PTR(-EINVAL);
+
+ if (!ops->get_temp)
+ return ERR_PTR(-EINVAL);
+
mutex_lock(&tzd->lock);
- tz->get_temp = get_temp;
- tz->get_trend = get_trend;
+ tz->ops = ops;
tz->sensor_data = data;
- tzd->ops->get_temp = of_thermal_get_temp;
- tzd->ops->get_trend = of_thermal_get_trend;
mutex_unlock(&tzd->lock);
return tzd;
@@ -356,8 +435,7 @@
* than one sensors
* @data: a private pointer (owned by the caller) that will be passed
* back, when a temperature reading is needed.
- * @get_temp: a pointer to a function that reads the sensor temperature.
- * @get_trend: a pointer to a function that reads the sensor temperature trend.
+ * @ops: struct thermal_zone_of_device_ops *. Must contain at least .get_temp.
*
* This function will search the list of thermal zones described in device
* tree and look for the zone that refer to the sensor device pointed by
@@ -382,25 +460,31 @@
* check the return value with help of IS_ERR() helper.
*/
struct thermal_zone_device *
-thermal_zone_of_sensor_register(struct device *dev, int sensor_id,
- void *data, int (*get_temp)(void *, long *),
- int (*get_trend)(void *, long *))
+thermal_zone_of_sensor_register(struct device *dev, int sensor_id, void *data,
+ const struct thermal_zone_of_device_ops *ops)
{
struct device_node *np, *child, *sensor_np;
+ struct thermal_zone_device *tzd = ERR_PTR(-ENODEV);
np = of_find_node_by_name(NULL, "thermal-zones");
if (!np)
return ERR_PTR(-ENODEV);
- if (!dev || !dev->of_node)
+ if (!dev || !dev->of_node) {
+ of_node_put(np);
return ERR_PTR(-EINVAL);
+ }
- sensor_np = dev->of_node;
+ sensor_np = of_node_get(dev->of_node);
for_each_child_of_node(np, child) {
struct of_phandle_args sensor_specs;
int ret, id;
+ /* Check whether child is enabled or not */
+ if (!of_device_is_available(child))
+ continue;
+
/* For now, thermal framework supports only 1 sensor per zone */
ret = of_parse_phandle_with_args(child, "thermal-sensors",
"#thermal-sensor-cells",
@@ -418,16 +502,22 @@
}
if (sensor_specs.np == sensor_np && id == sensor_id) {
- of_node_put(np);
- return thermal_zone_of_add_sensor(child, sensor_np,
- data,
- get_temp,
- get_trend);
+ tzd = thermal_zone_of_add_sensor(child, sensor_np,
+ data, ops);
+ if (!IS_ERR(tzd))
+ tzd->ops->set_mode(tzd, THERMAL_DEVICE_ENABLED);
+
+ of_node_put(sensor_specs.np);
+ of_node_put(child);
+ goto exit;
}
+ of_node_put(sensor_specs.np);
}
+exit:
+ of_node_put(sensor_np);
of_node_put(np);
- return ERR_PTR(-ENODEV);
+ return tzd;
}
EXPORT_SYMBOL_GPL(thermal_zone_of_sensor_register);
@@ -461,11 +551,7 @@
return;
mutex_lock(&tzd->lock);
- tzd->ops->get_temp = NULL;
- tzd->ops->get_trend = NULL;
-
- tz->get_temp = NULL;
- tz->get_trend = NULL;
+ tz->ops = NULL;
tz->sensor_data = NULL;
mutex_unlock(&tzd->lock);
}
@@ -489,7 +575,7 @@
*/
static int thermal_of_populate_bind_params(struct device_node *np,
struct __thermal_bind_params *__tbp,
- struct __thermal_trip *trips,
+ struct thermal_trip *trips,
int ntrips)
{
struct of_phandle_args cooling_spec;
@@ -592,7 +678,7 @@
* Return: 0 on success, proper error code otherwise
*/
static int thermal_of_populate_trip(struct device_node *np,
- struct __thermal_trip *trip)
+ struct thermal_trip *trip)
{
int prop;
int ret;
@@ -619,6 +705,7 @@
/* Required for cooling map matching */
trip->np = np;
+ of_node_get(np);
return 0;
}
@@ -712,11 +799,12 @@
}
i = 0;
- for_each_child_of_node(child, gchild)
+ for_each_child_of_node(child, gchild) {
ret = thermal_of_populate_bind_params(gchild, &tz->tbps[i++],
tz->trips, tz->ntrips);
if (ret)
goto free_tbps;
+ }
finish:
of_node_put(child);
@@ -725,9 +813,14 @@
return tz;
free_tbps:
+ for (i = 0; i < tz->num_tbps; i++)
+ of_node_put(tz->tbps[i].cooling_device);
kfree(tz->tbps);
free_trips:
+ for (i = 0; i < tz->ntrips; i++)
+ of_node_put(tz->trips[i].np);
kfree(tz->trips);
+ of_node_put(gchild);
free_tz:
kfree(tz);
of_node_put(child);
@@ -737,7 +830,13 @@
static inline void of_thermal_free_zone(struct __thermal_zone *tz)
{
+ int i;
+
+ for (i = 0; i < tz->num_tbps; i++)
+ of_node_put(tz->tbps[i].cooling_device);
kfree(tz->tbps);
+ for (i = 0; i < tz->ntrips; i++)
+ of_node_put(tz->trips[i].np);
kfree(tz->trips);
kfree(tz);
}
@@ -758,7 +857,6 @@
{
struct device_node *np, *child;
struct __thermal_zone *tz;
- struct thermal_zone_device_ops *ops;
np = of_find_node_by_name(NULL, "thermal-zones");
if (!np) {
@@ -770,6 +868,10 @@
struct thermal_zone_device *zone;
struct thermal_zone_params *tzp;
+ /* Check whether child is enabled or not */
+ if (!of_device_is_available(child))
+ continue;
+
tz = thermal_of_build_thermal_zone(child);
if (IS_ERR(tz)) {
pr_err("failed to build thermal zone %s: %ld\n",
@@ -778,37 +880,33 @@
continue;
}
- ops = kmemdup(&of_thermal_ops, sizeof(*ops), GFP_KERNEL);
- if (!ops)
- goto exit_free;
-
tzp = kzalloc(sizeof(*tzp), GFP_KERNEL);
- if (!tzp) {
- kfree(ops);
+ if (!tzp)
goto exit_free;
- }
/* No hwmon because there might be hwmon drivers registering */
tzp->no_hwmon = true;
zone = thermal_zone_device_register(child->name, tz->ntrips,
0, tz,
- ops, tzp,
+ &of_thermal_ops, tzp,
tz->passive_delay,
tz->polling_delay);
if (IS_ERR(zone)) {
pr_err("Failed to build %s zone %ld\n", child->name,
PTR_ERR(zone));
kfree(tzp);
- kfree(ops);
of_thermal_free_zone(tz);
/* attempting to build remaining zones still */
}
}
+ of_node_put(np);
return 0;
exit_free:
+ of_node_put(child);
+ of_node_put(np);
of_thermal_free_zone(tz);
/* no memory available, so free what we have built */
@@ -837,6 +935,10 @@
for_each_child_of_node(np, child) {
struct thermal_zone_device *zone;
+ /* Check whether child is enabled or not */
+ if (!of_device_is_available(child))
+ continue;
+
zone = thermal_zone_get_zone_by_name(child->name);
if (IS_ERR(zone))
continue;
@@ -846,4 +948,5 @@
kfree(zone->ops);
of_thermal_free_zone(zone->devdata);
}
+ of_node_put(np);
}
diff --git a/drivers/thermal/step_wise.c b/drivers/thermal/step_wise.c
index f251521..fdd1f52 100644
--- a/drivers/thermal/step_wise.c
+++ b/drivers/thermal/step_wise.c
@@ -23,6 +23,7 @@
*/
#include <linux/thermal.h>
+#include <trace/events/thermal.h>
#include "thermal_core.h"
@@ -76,7 +77,7 @@
next_target = instance->upper;
break;
case THERMAL_TREND_DROPPING:
- if (cur_state == instance->lower) {
+ if (cur_state <= instance->lower) {
if (!throttle)
next_target = THERMAL_NO_TARGET;
} else {
@@ -129,8 +130,10 @@
trend = get_tz_trend(tz, trip);
- if (tz->temperature >= trip_temp)
+ if (tz->temperature >= trip_temp) {
throttle = true;
+ trace_thermal_zone_trip(tz, trip, trip_type);
+ }
dev_dbg(&tz->device, "Trip%d[type=%d,temp=%ld]:trend=%d,throttle=%d\n",
trip, trip_type, trip_temp, trend, throttle);
diff --git a/drivers/thermal/thermal_core.c b/drivers/thermal/thermal_core.c
index 284733e..4c8fdfc 100644
--- a/drivers/thermal/thermal_core.c
+++ b/drivers/thermal/thermal_core.c
@@ -38,6 +38,9 @@
#include <net/netlink.h>
#include <net/genetlink.h>
+#define CREATE_TRACE_POINTS
+#include <trace/events/thermal.h>
+
#include "thermal_core.h"
#include "thermal_hwmon.h"
@@ -365,9 +368,11 @@
tz->ops->get_trip_temp(tz, trip, &trip_temp);
/* If we have not crossed the trip_temp, we do not care. */
- if (tz->temperature < trip_temp)
+ if (trip_temp <= 0 || tz->temperature < trip_temp)
return;
+ trace_thermal_zone_trip(tz, trip, trip_type);
+
if (tz->ops->notify)
tz->ops->notify(tz, trip, trip_type);
@@ -408,76 +413,139 @@
*/
int thermal_zone_get_temp(struct thermal_zone_device *tz, unsigned long *temp)
{
- int ret = -EINVAL;
-#ifdef CONFIG_THERMAL_EMULATION
- int count;
- unsigned long crit_temp = -1UL;
- enum thermal_trip_type type;
-#endif
+ int ret;
- if (!tz || IS_ERR(tz) || !tz->ops->get_temp)
- goto exit;
+ if (!tz || IS_ERR(tz))
+ return -EINVAL;
+
+ if (!tz->ops->get_temp)
+ return -ENOSYS;
mutex_lock(&tz->lock);
ret = tz->ops->get_temp(tz, temp);
-#ifdef CONFIG_THERMAL_EMULATION
- if (!tz->emul_temperature)
- goto skip_emul;
- for (count = 0; count < tz->trips; count++) {
- ret = tz->ops->get_trip_type(tz, count, &type);
- if (!ret && type == THERMAL_TRIP_CRITICAL) {
- ret = tz->ops->get_trip_temp(tz, count, &crit_temp);
- break;
- }
- }
-
- if (ret)
- goto skip_emul;
-
- if (*temp < crit_temp)
+ if (IS_ENABLED(CONFIG_THERMAL_EMULATION) && tz->emul_temperature)
*temp = tz->emul_temperature;
-skip_emul:
-#endif
+
mutex_unlock(&tz->lock);
-exit:
+
return ret;
}
EXPORT_SYMBOL_GPL(thermal_zone_get_temp);
-static void update_temperature(struct thermal_zone_device *tz)
+/*
+ * If not implemented, return -ENOSYS
+ * Otherwise:
+ * Return trip point number (>= 0) if triggered
+ * Return invalid trip number (tz->trips) if not triggered
+ */
+static int thermal_zone_set_trips(struct thermal_zone_device *tz)
{
- long temp;
- int ret;
+ unsigned long low = 0;
+ unsigned long high = ULONG_MAX;
+ unsigned long trip_temp, hysteresis;
+ unsigned long temp = tz->temperature;
+ unsigned long last = tz->last_temperature;
+ unsigned long notify_temp = 0; /* minimum */
+ int notify_trip = tz->trips; /* maximum */
+ int i;
- ret = thermal_zone_get_temp(tz, &temp);
- if (ret) {
- dev_warn(&tz->device, "failed to read out thermal zone %d\n",
- tz->id);
- return;
+ if (!tz->ops->set_trips)
+ return -ENOSYS;
+
+ /* No need to change trip points */
+ if (temp > tz->prev_low_trip && temp < tz->prev_high_trip)
+ return notify_trip;
+
+ for (i = 0; i < tz->trips; i++) {
+ unsigned long trip_low;
+
+ tz->ops->get_trip_temp(tz, i, &trip_temp);
+ tz->ops->get_trip_hyst(tz, i, &hysteresis);
+
+ trip_low = trip_temp - hysteresis;
+
+ if (trip_low < temp && trip_low > low)
+ low = trip_low;
+
+ if (trip_temp > temp && trip_temp < high)
+ high = trip_temp;
+
+ /* Report only when traversing a trip point */
+ if (trip_low > notify_temp && last > trip_low
+ && trip_low > temp) {
+ notify_trip = i;
+ notify_temp = trip_low;
+ } else if (trip_temp > notify_temp && last < trip_temp
+ && trip_temp < temp) {
+ notify_trip = i;
+ notify_temp = trip_temp;
+ }
}
+ tz->prev_low_trip = low;
+ tz->prev_high_trip = high;
+
+ dev_dbg(&tz->device, "new temperature boundaries: %lu < x < %lu\n",
+ low, high);
+
+ tz->ops->set_trips(tz, low, high);
+
+ return notify_trip;
+}
+
+/*
+ * Equivalent to thermal_zone_device_update(), except that the notifier can
+ * provide the temperature directly. This is useful in case the update is
+ * driven by a hardware interrupt, and we don't want to risk a race between the
+ * notification and the next temperature reading.
+ */
+void thermal_zone_device_update_temp(struct thermal_zone_device *tz,
+ long temp)
+{
+ int count, trip;
+
mutex_lock(&tz->lock);
tz->last_temperature = tz->temperature;
tz->temperature = temp;
mutex_unlock(&tz->lock);
+ trace_thermal_temperature(tz);
dev_dbg(&tz->device, "last_temperature=%d, current_temperature=%d\n",
tz->last_temperature, tz->temperature);
+
+ trip = thermal_zone_set_trips(tz);
+
+ if (trip < 0) {
+ /* Update isn't targeting a particular trip */
+ for (count = 0; count < tz->trips; count++)
+ handle_thermal_trip(tz, count);
+ } else if (trip < tz->trips) {
+ handle_thermal_trip(tz, trip);
+ } else {
+ dev_dbg(&tz->device, "update didn't target any trip point\n");
+ }
}
+EXPORT_SYMBOL_GPL(thermal_zone_device_update_temp);
void thermal_zone_device_update(struct thermal_zone_device *tz)
{
- int count;
+ long temp;
+ int ret;
- if (!tz->ops->get_temp)
+ ret = thermal_zone_get_temp(tz, &temp);
+
+ if (ret == -ENOSYS)
return;
- update_temperature(tz);
+ if (ret) {
+ dev_warn(&tz->device, "failed to read out thermal zone %d\n",
+ tz->id);
+ return;
+ }
- for (count = 0; count < tz->trips; count++)
- handle_thermal_trip(tz, count);
+ thermal_zone_device_update_temp(tz, temp);
}
EXPORT_SYMBOL_GPL(thermal_zone_device_update);
@@ -751,6 +819,7 @@
snprintf(name, sizeof(name), "%s", buf);
mutex_lock(&thermal_governor_lock);
+ mutex_lock(&tz->lock);
gov = __find_governor(strim(name));
if (!gov)
@@ -760,6 +829,7 @@
ret = count;
exit:
+ mutex_unlock(&tz->lock);
mutex_unlock(&thermal_governor_lock);
return ret;
}
@@ -780,16 +850,42 @@
struct thermal_zone_device *tz = to_thermal_zone(dev);
int ret = 0;
unsigned long temperature;
+ int trip;
+ unsigned long crit_temp;
+ enum thermal_trip_type type;
if (kstrtoul(buf, 10, &temperature))
return -EINVAL;
- if (!tz->ops->set_emul_temp) {
+ for (trip = 0; trip < tz->trips; trip++) {
+ ret = tz->ops->get_trip_type(tz, trip, &type);
+ if (ret)
+ return ret;
+
+ if (type != THERMAL_TRIP_CRITICAL)
+ continue;
+
+ ret = tz->ops->get_trip_temp(tz, trip, &crit_temp);
+ if (ret)
+ return ret;
+
+ if (temperature >= crit_temp) {
+ dev_err(&tz->device, "Will not emulate critical temperature %luC (tcrit=%luC)\n",
+ temperature / 1000, crit_temp / 1000);
+ return -EINVAL;
+ }
+ }
+
+ if (tz->ops->set_emul_temp)
+ ret = tz->ops->set_emul_temp(tz, temperature);
+ else
+ ret = -ENOSYS;
+
+ if (ret == -ENOSYS) {
mutex_lock(&tz->lock);
tz->emul_temperature = temperature;
mutex_unlock(&tz->lock);
- } else {
- ret = tz->ops->set_emul_temp(tz, temperature);
+ ret = 0;
}
if (!ret)
@@ -922,7 +1018,7 @@
struct thermal_zone_device *pos1;
struct thermal_cooling_device *pos2;
unsigned long max_state;
- int result;
+ int result, ret;
if (trip >= tz->trips || (trip < 0 && trip != THERMAL_TRIPS_NONE))
return -EINVAL;
@@ -939,7 +1035,9 @@
if (tz != pos1 || cdev != pos2)
return -EINVAL;
- cdev->ops->get_max_state(cdev, &max_state);
+ ret = cdev->ops->get_max_state(cdev, &max_state);
+ if (ret)
+ return ret;
/* lower default 0, upper default max_state */
lower = lower == THERMAL_NO_LIMIT ? 0 : lower;
@@ -1287,6 +1385,7 @@
mutex_unlock(&cdev->lock);
cdev->ops->set_cur_state(cdev, target);
cdev->updated = true;
+ trace_cdev_update(cdev, target);
dev_dbg(&cdev->device, "set to state %lu\n", target);
}
EXPORT_SYMBOL(thermal_cdev_update);
@@ -1443,7 +1542,7 @@
*/
struct thermal_zone_device *thermal_zone_device_register(const char *type,
int trips, int mask, void *devdata,
- struct thermal_zone_device_ops *ops,
+ const struct thermal_zone_device_ops *ops,
const struct thermal_zone_params *tzp,
int passive_delay, int polling_delay)
{
@@ -1563,13 +1662,9 @@
INIT_DELAYED_WORK(&(tz->poll_queue), thermal_zone_device_check);
- if (!tz->ops->get_temp)
- thermal_zone_device_set_polling(tz, 0);
-
thermal_zone_device_update(tz);
- if (!result)
- return tz;
+ return tz;
unregister:
release_idr(&thermal_tz_idr, &thermal_idr_lock, tz->id);
diff --git a/drivers/thermal/thermal_core.h b/drivers/thermal/thermal_core.h
index 3db339f..65f2fb4 100644
--- a/drivers/thermal/thermal_core.h
+++ b/drivers/thermal/thermal_core.h
@@ -81,9 +81,27 @@
#ifdef CONFIG_THERMAL_OF
int of_parse_thermal_zones(void);
void of_thermal_destroy_zones(void);
+int of_thermal_get_ntrips(struct thermal_zone_device *);
+bool of_thermal_is_trip_valid(struct thermal_zone_device *, int);
+const struct thermal_trip * const
+of_thermal_get_trip_points(struct thermal_zone_device *);
#else
static inline int of_parse_thermal_zones(void) { return 0; }
static inline void of_thermal_destroy_zones(void) { }
+static inline int of_thermal_get_ntrips(struct thermal_zone_device *tz)
+{
+ return 0;
+}
+static inline bool of_thermal_is_trip_valid(struct thermal_zone_device *tz,
+ int trip)
+{
+ return 0;
+}
+static inline const struct thermal_trip * const
+of_thermal_get_trip_points(struct thermal_zone_device *tz)
+{
+ return NULL;
+}
#endif
#endif /* __THERMAL_CORE_H__ */
diff --git a/drivers/thermal/ti-soc-thermal/ti-thermal-common.c b/drivers/thermal/ti-soc-thermal/ti-thermal-common.c
index 9eec26d..8a712b4 100644
--- a/drivers/thermal/ti-soc-thermal/ti-thermal-common.c
+++ b/drivers/thermal/ti-soc-thermal/ti-thermal-common.c
@@ -239,7 +239,7 @@
return 0;
}
-static int __ti_thermal_get_trend(void *p, long *trend)
+static int __ti_thermal_get_trend(void *p, int trip, enum thermal_trend *trend)
{
struct ti_thermal_data *data = p;
struct ti_bandgap *bgp;
@@ -252,22 +252,6 @@
if (ret)
return ret;
- *trend = tr;
-
- return 0;
-}
-
-/* Get the temperature trend callback functions for thermal zone */
-static int ti_thermal_get_trend(struct thermal_zone_device *thermal,
- int trip, enum thermal_trend *trend)
-{
- int ret;
- long tr;
-
- ret = __ti_thermal_get_trend(thermal->devdata, &tr);
- if (ret)
- return ret;
-
if (tr > 0)
*trend = THERMAL_TREND_RAISING;
else if (tr < 0)
@@ -278,6 +262,13 @@
return 0;
}
+/* Get the temperature trend callback functions for thermal zone */
+static int ti_thermal_get_trend(struct thermal_zone_device *thermal,
+ int trip, enum thermal_trend *trend)
+{
+ return __ti_thermal_get_trend(thermal->devdata, trip, trend);
+}
+
/* Get critical temperature callback functions for thermal zone */
static int ti_thermal_get_crit_temp(struct thermal_zone_device *thermal,
unsigned long *temp)
@@ -286,6 +277,11 @@
return ti_thermal_get_trip_temp(thermal, OMAP_TRIP_NUMBER - 1, temp);
}
+static const struct thermal_zone_of_device_ops ti_of_thermal_ops = {
+ .get_temp = __ti_thermal_get_temp,
+ .get_trend = __ti_thermal_get_trend,
+};
+
static struct thermal_zone_device_ops ti_thermal_ops = {
.get_temp = ti_thermal_get_temp,
.get_trend = ti_thermal_get_trend,
@@ -333,8 +329,7 @@
/* in case this is specified by DT */
data->ti_thermal = thermal_zone_of_sensor_register(bgp->dev, id,
- data, __ti_thermal_get_temp,
- __ti_thermal_get_trend);
+ data, &ti_of_thermal_ops);
if (IS_ERR(data->ti_thermal)) {
/* Create thermal zone */
data->ti_thermal = thermal_zone_device_register(domain,
diff --git a/drivers/thermal/user_space.c b/drivers/thermal/user_space.c
index 10adcdd..61118d4 100644
--- a/drivers/thermal/user_space.c
+++ b/drivers/thermal/user_space.c
@@ -22,6 +22,8 @@
* ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
*/
+#include <linux/kernel.h>
+#include <linux/slab.h>
#include <linux/thermal.h>
#include "thermal_core.h"
@@ -34,10 +36,25 @@
*/
static int notify_user_space(struct thermal_zone_device *tz, int trip)
{
+ char *envp[] = { NULL, NULL, NULL };
+ int ret = 0;
+
+ envp[0] = kasprintf(GFP_KERNEL, "TRIPNUM=%u", trip);
+ envp[1] = kasprintf(GFP_KERNEL, "TEMPERATURE=%d", tz->temperature);
+ if (!envp[0] || !envp[1]) {
+ ret = -ENOMEM;
+ goto out;
+ }
+
mutex_lock(&tz->lock);
- kobject_uevent(&tz->device.kobj, KOBJ_CHANGE);
+ kobject_uevent_env(&tz->device.kobj, KOBJ_CHANGE, envp);
mutex_unlock(&tz->lock);
- return 0;
+
+out:
+ kfree(envp[0]);
+ kfree(envp[1]);
+
+ return ret;
}
static struct thermal_governor thermal_gov_user_space = {
diff --git a/drivers/tty/serial/8250/8250_core.c b/drivers/tty/serial/8250/8250_core.c
index 2bb1020..70fde5a 100644
--- a/drivers/tty/serial/8250/8250_core.c
+++ b/drivers/tty/serial/8250/8250_core.c
@@ -65,8 +65,6 @@
static unsigned int skip_txen_test; /* force skip of txen test at init time */
-static void wait_for_xmitr(struct uart_8250_port *up, int bits);
-
/*
* Debugging.
*/
@@ -301,13 +299,6 @@
.tx_loadsz = 1024,
.flags = UART_CAP_HFIFO,
},
- [PORT_BRCM_BUGGY_DW] = {
- .name = "BuggyDW",
- .fifo_size = 32,
- .tx_loadsz = 32,
- .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
- .flags = UART_CAP_FIFO | UART_NATSEMI,
- },
[PORT_8250_CIR] = {
.name = "CIR port"
},
@@ -431,26 +422,6 @@
return readl(p->membase + offset);
}
-/*
- * SWLINUX-2948: Chips with UARTs marked BuggyDW have an unresettable "busy
- * detect" interrupt that can be triggered by writing LCR when UART is busy
- * (one case is when receive data is present in RBR). Work around this by:
- * 1. clearing and initializing FIFOs
- * 2. writing LCR (racing against external input)
- */
-static void safer_mem32_serial_out(struct uart_port *p, int offset, int value)
-{
- struct uart_8250_port *up =
- container_of(p, struct uart_8250_port, port);
- if (offset == UART_LCR) {
- wait_for_xmitr(up, BOTH_EMPTY);
- serial8250_clear_and_reinit_fifos(up);
- mem32_serial_out(p, offset, value);
- } else {
- mem32_serial_out(p, offset, value);
- }
-}
-
static unsigned int io_serial_in(struct uart_port *p, int offset)
{
offset = offset << p->regshift;
@@ -488,8 +459,6 @@
case UPIO_MEM32:
p->serial_in = mem32_serial_in;
p->serial_out = mem32_serial_out;
- if (p->flags & UPF_SAFER_LCR_WRITES)
- p->serial_out = safer_mem32_serial_out;
break;
#if defined(CONFIG_MIPS_ALCHEMY) || defined(CONFIG_SERIAL_8250_RT288X)
diff --git a/drivers/tty/serial/of_serial.c b/drivers/tty/serial/of_serial.c
index 8c9974a..dcab12f 100644
--- a/drivers/tty/serial/of_serial.c
+++ b/drivers/tty/serial/of_serial.c
@@ -133,17 +133,6 @@
if (type == PORT_TEGRA)
port->handle_break = tegra_serial_handle_break;
- if (type == PORT_BRCM_BUGGY_DW)
- port->flags |= UPF_SAFER_LCR_WRITES;
-
-#if defined(CONFIG_BCM7145A0) || defined(CONFIG_BCM7439A0)
- /*
- * All of these chips definitely have an unresettable busy
- * detect serial interrupt.
- */
- port->flags |= UPF_SAFER_LCR_WRITES;
-#endif
-
return 0;
out:
if (info->clk)
@@ -319,10 +308,6 @@
* A few common types, add more as needed.
*/
static struct of_device_id of_platform_serial_table[] = {
-#ifdef CONFIG_BRCMSTB
- { .compatible = "brcm,buggy-dw-apb-uart",
- .data = (void *)PORT_BRCM_BUGGY_DW, },
-#endif
{ .compatible = "ns8250", .data = (void *)PORT_8250, },
{ .compatible = "ns16450", .data = (void *)PORT_16450, },
{ .compatible = "ns16550a", .data = (void *)PORT_16550A, },
diff --git a/drivers/usb/host/usb-brcm-common-init.c b/drivers/usb/host/usb-brcm-common-init.c
index f38673e..43d585e 100644
--- a/drivers/usb/host/usb-brcm-common-init.c
+++ b/drivers/usb/host/usb-brcm-common-init.c
@@ -1,15 +1,29 @@
/*
- * Copyright (C) 2014 Broadcom Corporation
+ * Copyright (C) 2014-2015 Broadcom Corporation
*
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * 3. Neither the name of the project nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
*
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
+ * THIS SOFTWARE IS PROVIDED BY THE PROJECT AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE PROJECT OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
*/
/*
@@ -22,12 +36,10 @@
#include "common.h"
#include "bchp_common.h"
#include "bchp_usb_ctrl.h"
+#include "bchp_sun_top_ctrl.h"
#include "timer.h"
#define msleep bolt_msleep
#define udelay bolt_usleep
-#if defined(BCHP_USB1_CTRL_REG_START)
-#include "bchp_usb1_ctrl.h"
-#endif
#else
#include <linux/delay.h>
#include <linux/brcmstb/brcmstb.h>
@@ -35,23 +47,15 @@
#include "usb-brcm-common-init.h"
-#if defined(BCHP_USB_CTRL_REG_START)
#define USB_CTRL_REG(base, reg) (base + BCHP_USB_CTRL_##reg - \
BCHP_USB_CTRL_SETUP)
#define USB_CTRL_MASK(reg, field) (BCHP_USB_CTRL_##reg##_##field##_MASK)
-#define USB_CTRL_SHIFT(reg, field) (BCHP_USB_CTRL_##reg##_##field##_SHIFT)
-#elif defined(BCHP_USB1_CTRL_REG_START)
-#define USB_CTRL_REG(base, reg) (base + BCHP_USB1_CTRL_##reg - \
- BCHP_USB1_CTRL_SETUP)
-#define USB_CTRL_MASK(reg, field) (BCHP_USB1_CTRL_##reg##_##field##_MASK)
-#define USB_CTRL_SHIFT(reg, field) (BCHP_USB1_CTRL_##reg##_##field##_SHIFT)
-#endif
-
#define USB_CTRL_SET(base, reg, mask) DEV_SET(USB_CTRL_REG(base, reg), \
USB_CTRL_MASK(reg, mask))
-
#define USB_CTRL_UNSET(base, reg, mask) DEV_UNSET(USB_CTRL_REG(base, reg), \
USB_CTRL_MASK(reg, mask))
+#define USB_XHCI_EC_REG(base, reg) (base + BCHP_USB_XHCI_EC_##reg - \
+ BCHP_USB_XHCI_EC_REG_START)
#define MDIO_USB2 0
#define MDIO_USB3 (1 << 31)
@@ -106,31 +110,23 @@
}
-static void usb_phy_ldo_fix(uintptr_t usbctrl)
+static void usb_phy_ldo_fix(uintptr_t ctrl_base)
{
- USB_CTRL_UNSET(usbctrl, PLL_CTL, PLL_RESETB);
- DEV_WR(USB_CTRL_REG(usbctrl, UTMI_CTL_1), 0);
- DEV_WR(USB_CTRL_REG(usbctrl, PLL_LDO_CTL),
- USB_CTRL_MASK(PLL_LDO_CTL, AFE_CORERDY_VDDC));
-#if defined(BCHP_USB_CTRL_PLL_CTL_PLL_IDDQ_PWRDN_MASK) || \
- defined(BCHP_USB1_CTRL_PLL_CTL_PLL_IDDQ_PWRDN_MASK)
- USB_CTRL_SET(usbctrl, PLL_CTL, PLL_IDDQ_PWRDN);
- msleep(10);
- USB_CTRL_UNSET(usbctrl, PLL_CTL, PLL_IDDQ_PWRDN);
-#else
- USB_CTRL_SET(usbctrl, USB_PM, USB_PWRDN);
- msleep(10);
- USB_CTRL_UNSET(usbctrl, USB_PM, USB_PWRDN);
-#endif
- USB_CTRL_SET(usbctrl, PLL_LDO_CTL, AFE_BG_PWRDWNB);
- USB_CTRL_SET(usbctrl, PLL_LDO_CTL, AFE_LDO_PWRDWNB);
+ /* first disable FSM but also leave it that way */
+ /* to allow normal suspend/resume */
+ DEV_UNSET(USB_CTRL_REG(ctrl_base, UTMI_CTL_1),
+ USB_CTRL_MASK(UTMI_CTL_1, POWER_UP_FSM_EN_P1) |
+ USB_CTRL_MASK(UTMI_CTL_1, POWER_UP_FSM_EN));
+
+ /* reset USB 2.0 PLL */
+ USB_CTRL_UNSET(ctrl_base, PLL_CTL, PLL_RESETB);
msleep(1);
- DEV_WR(USB_CTRL_REG(usbctrl, UTMI_CTL_1),
- USB_CTRL_MASK(UTMI_CTL_1, UTMI_SOFT_RESETB) |
- USB_CTRL_MASK(UTMI_CTL_1, UTMI_SOFT_RESETB_P1));
- USB_CTRL_SET(usbctrl, PLL_CTL, PLL_RESETB);
+ USB_CTRL_SET(ctrl_base, PLL_CTL, PLL_RESETB);
+ msleep(10);
+
}
+
static void usb2_eye_fix(uintptr_t ctrl_base)
{
/* Increase USB 2.0 TX level to meet spec requirement */
@@ -153,40 +149,11 @@
/* Enable USB 3.0 TX spread spectrum */
usb_mdio_write(ctrl_base, 0x1f, 0x8040, MDIO_USB3);
- val = usb_mdio_read(ctrl_base, 0x01, MDIO_USB3) | 3;
+ val = usb_mdio_read(ctrl_base, 0x01, MDIO_USB3) | 0xf;
usb_mdio_write(ctrl_base, 0x01, val, MDIO_USB3);
}
-void brcm_usb_common_ctrl_xhci_soft_reset(uintptr_t ctrl, int on_off)
-{
-#if defined(BCHP_USB_CTRL_USB_PM_xhc_soft_resetb_MASK) || \
- defined(BCHP_USB1_CTRL_USB_PM_xhc_soft_resetb_MASK)
- /* Assert reset */
- if (on_off) {
- DEV_UNSET(USB_CTRL_REG(ctrl, USB_PM),
- USB_CTRL_MASK(USB_PM, xhc_soft_resetb));
- }
- /* De-assert reset */
- else {
- DEV_SET(USB_CTRL_REG(ctrl, USB_PM),
- USB_CTRL_MASK(USB_PM, xhc_soft_resetb));
- }
-#else
- /* Assert reset */
- if (on_off) {
- DEV_UNSET(USB_CTRL_REG(ctrl, USB30_CTL1),
- USB_CTRL_MASK(USB30_CTL1, xhc_soft_resetb));
- }
- /* De-assert reset */
- else {
- DEV_SET(USB_CTRL_REG(ctrl, USB30_CTL1),
- USB_CTRL_MASK(USB30_CTL1, xhc_soft_resetb));
- }
-#endif
-}
-
-
static void memc_fix(uintptr_t ctrl_base)
{
#if defined(CONFIG_BCM7445D0)
@@ -194,7 +161,7 @@
* This is a workaround for HW7445-1869 where a DMA write ends up
* doing a read pre-fetch after the end of the DMA buffer. This
* causes a problem when the DMA buffer is at the end of physical
- * memory, causing the pre-fetch read to access non-existand memory,
+ * memory, causing the pre-fetch read to access non-existent memory,
* and the chip bondout has MEMC2 disabled. When the pre-fetch read
* tries to use the disabled MEMC2, it hangs the bus. The workaround
* is to disable MEMC2 access in the usb controller which avoids
@@ -215,87 +182,122 @@
#endif
}
-void brcm_usb_common_ctrl_init(uintptr_t ctrl, int ioc, int ipp, int xhci)
+#if defined(CONFIG_BCM74371A0)
+#if defined(_BOLT_)
+#include "bchp_usb_xhci_ec.h"
+#endif
+static void usb3_otp_fix(uintptr_t ctrl_base, uintptr_t xhci_ec_base)
+{
+ uintptr_t val;
+
+ if (xhci_ec_base == 0)
+ return;
+ DEV_WR(USB_XHCI_EC_REG(xhci_ec_base, IRAADR), 0xa20c);
+ val = DEV_RD(USB_XHCI_EC_REG(xhci_ec_base, IRADAT));
+
+ /* set cfg_pick_ss_lock */
+ val |= (1 << 27);
+ DEV_WR(USB_XHCI_EC_REG(xhci_ec_base, IRADAT), val);
+
+ /* Reset USB 3.0 PHY for workaround to take effect */
+ USB_CTRL_UNSET(ctrl_base, USB30_CTL1, phy3_resetb);
+ USB_CTRL_SET(ctrl_base, USB30_CTL1, phy3_resetb);
+}
+#else
+static void usb3_otp_fix(uintptr_t ctrl_base, uintptr_t xhci_ec_regs)
+{
+}
+#endif
+
+
+static void xhci_soft_reset(uintptr_t ctrl, int on_off)
+{
+ /* Assert reset */
+ if (on_off) {
+#if defined(BCHP_USB_CTRL_USB_PM_xhc_soft_resetb_MASK)
+ USB_CTRL_UNSET(ctrl, USB_PM, xhc_soft_resetb);
+#else
+ USB_CTRL_UNSET(ctrl, USB30_CTL1, xhc_soft_resetb);
+#endif
+ }
+ /* De-assert reset */
+ else {
+#if defined(BCHP_USB_CTRL_USB_PM_xhc_soft_resetb_MASK)
+ USB_CTRL_SET(ctrl, USB_PM, xhc_soft_resetb);
+#else
+ USB_CTRL_SET(ctrl, USB30_CTL1, xhc_soft_resetb);
+#endif
+ }
+}
+
+
+void brcm_usb_common_init(struct brcm_usb_common_init_params *params)
{
uint32_t reg;
+ uintptr_t ctrl = params->ctrl_regs;
-#if defined(CONFIG_BCM7145A0)
- if (xhci) {
- /* Updating USB 3.0 PHY registers */
- /* fix PLL lock */
- usb_mdio_write(ctrl, 0x1f, 0x8000, MDIO_USB3);
- usb_mdio_write(ctrl, 0x0d, 0x0020, MDIO_USB3);
- usb_mdio_write(ctrl, 0x0e, 0x000e, MDIO_USB3);
- usb_mdio_write(ctrl, 0x12, 0x19f8, MDIO_USB3);
- usb_mdio_write(ctrl, 0x01, 0x0000, MDIO_USB3);
- usb_mdio_write(ctrl, 0x01, 0x9000, MDIO_USB3);
- usb_mdio_write(ctrl, 0x1f, 0x8060, MDIO_USB3);
- /* Tx demphasis override */
- usb_mdio_write(ctrl, 0x0c, 0x8840, MDIO_USB3);
- /* max margin error count */
- usb_mdio_write(ctrl, 0x05, 0xff08, MDIO_USB3);
- /* deglitch params 6,3 */
- usb_mdio_write(ctrl, 0x03, 0x6302, MDIO_USB3);
- }
-#endif
-#if defined(CONFIG_BCM7439A0) || defined(CONFIG_BCM7366)
+ xhci_soft_reset(ctrl, 1);
+#if defined(CONFIG_BCM7366)
/*
* The PHY3_SOFT_RESETB bits default to the wrong state.
*/
- DEV_SET(USB_CTRL_REG(ctrl, USB30_PCTL), 0x20002);
+ DEV_SET(USB_CTRL_REG(ctrl, USB30_PCTL),
+ USB_CTRL_MASK(USB30_PCTL, PHY3_SOFT_RESETB_P1) |
+ USB_CTRL_MASK(USB30_PCTL, PHY3_SOFT_RESETB));
+#endif
+#if defined(CONFIG_BCM7366C0)
+ /*
+ * Don't enable this so the memory controller doesn't read
+ * into memory holes. NOTE: This bit is low true on 7366C0.
+ */
+ DEV_SET(USB_CTRL_REG(ctrl, EBRIDGE),
+ USB_CTRL_MASK(EBRIDGE, ESTOP_SCB_REQ));
#endif
-#if defined(BCHP_USB_CTRL_PLL_CTL_PLL_IDDQ_PWRDN_MASK) || \
- defined(BCHP_USB1_CTRL_PLL_CTL_PLL_IDDQ_PWRDN_MASK)
/* Take USB out of power down */
- DEV_UNSET(USB_CTRL_REG(ctrl, PLL_CTL),
- USB_CTRL_MASK(PLL_CTL, PLL_IDDQ_PWRDN));
+#if defined(BCHP_USB_CTRL_PLL_CTL_PLL_IDDQ_PWRDN_MASK)
+ USB_CTRL_UNSET(ctrl, PLL_CTL, PLL_IDDQ_PWRDN);
/* 1 millisecond - for USB clocks to settle down */
msleep(1);
-#else
- /* Take USB out of power down */
- DEV_UNSET(USB_CTRL_REG(ctrl, USB_PM),
- USB_CTRL_MASK(USB_PM, USB_PWRDN));
+#endif
+#if defined(BCHP_USB_CTRL_USB_PM_USB_PWRDN_MASK)
+ /* 3390a0 & 7439b0 so far. */
+ USB_CTRL_UNSET(ctrl, USB_PM, USB_PWRDN);
/* 1 millisecond - for USB clocks to settle down */
msleep(1);
#endif
-#if defined(CONFIG_BCM7445D0)
- DEV_UNSET(USB_CTRL_REG(ctrl, UTMI_CTL_1),
- USB_CTRL_MASK(UTMI_CTL_1, POWER_UP_FSM_EN_P1) |
- USB_CTRL_MASK(UTMI_CTL_1, POWER_UP_FSM_EN));
-#endif
-
-#if defined(BCHP_USB_CTRL_USB30_CTL1_usb3_ipp_MASK) || \
- defined(BCHP_USB1_CTRL_USB30_CTL1_usb3_ipp_MASK)
+#if defined(BCHP_USB_CTRL_USB30_CTL1_usb3_ipp_MASK)
/* Starting with the 7445d0, there are no longer separate 3.0
* versions of IOC and IPP.
*/
- DEV_SET(USB_CTRL_REG(ctrl, USB30_CTL1),
- USB_CTRL_MASK(USB30_CTL1, usb3_ipp) |
- USB_CTRL_MASK(USB30_CTL1, usb3_ioc));
+ if (params->ioc)
+ USB_CTRL_SET(ctrl, USB30_CTL1, usb3_ioc);
+ if (params->ipp)
+ USB_CTRL_SET(ctrl, USB30_CTL1, usb3_ipp);
#endif
-#if !defined(CONFIG_BCM7439A0) && !defined(CONFIG_BCM74371A0) && \
- !defined(CONFIG_BCM7364A0)
+#if !defined(CONFIG_BCM74371A0) && !defined(CONFIG_BCM7364)
/*
* HW7439-637: 7439a0 and its derivatives do not have large enough
* descriptor storage for this.
*/
- DEV_SET(USB_CTRL_REG(ctrl, SETUP),
- USB_CTRL_MASK(SETUP, ss_ehci64bit_en));
+ USB_CTRL_SET(ctrl, SETUP, ss_ehci64bit_en);
#endif
- /* Make sure it's low to insure a rising edge. */
- DEV_UNSET(USB_CTRL_REG(ctrl, USB30_CTL1),
- USB_CTRL_MASK(USB30_CTL1, phy3_pll_seq_start));
- DEV_SET(USB_CTRL_REG(ctrl, USB30_CTL1),
- USB_CTRL_MASK(USB30_CTL1, phy3_pll_seq_start));
- DEV_SET(USB_CTRL_REG(ctrl, PLL_CTL),
- USB_CTRL_MASK(PLL_CTL, PLL_SUSPEND_EN));
+
+ /*
+ * Kick start USB3 PHY
+ * Make sure it's low to insure a rising edge.
+ */
+ USB_CTRL_UNSET(ctrl, USB30_CTL1, phy3_pll_seq_start);
+ USB_CTRL_SET(ctrl, USB30_CTL1, phy3_pll_seq_start);
+
+ /* Block auto PLL suspend by USB2 PHY */
+ USB_CTRL_SET(ctrl, PLL_CTL, PLL_SUSPEND_EN);
usb2_eye_fix(ctrl);
usb_phy_ldo_fix(ctrl);
- if (xhci) {
+ if (params->has_xhci) {
usb3_pll_fix(ctrl);
usb3_ssc_enable(ctrl);
}
@@ -305,11 +307,16 @@
reg &= ~USB_CTRL_SETUP_CONDITIONAL_BITS;
reg |= ENDIAN_SETTINGS;
-#if defined(CONFIG_BCM7364A0)
- /* Suppress overcurrent indication from USB30 ports */
- reg |= BCHP_USB_CTRL_SETUP_OC3_DISABLE_MASK;
+#if defined(CONFIG_BCM7364)
+ if ((BDEV_RD(BCHP_SUN_TOP_CTRL_PRODUCT_ID) == 0x73640000))
+ /* Suppress overcurrent indication from USB30 ports for A0 */
+ reg |= USB_CTRL_MASK(SETUP, OC3_DISABLE);
#endif
+#if defined(BCHP_USB_CTRL_SETUP_strap_ipp_sel_MASK)
+ /* override ipp strap pin (if it exits) */
+ reg &= ~(USB_CTRL_MASK(SETUP, strap_ipp_sel));
+#endif
/*
* Make sure the the second and third memory controller
* interfaces are enabled.
@@ -318,21 +325,16 @@
USB_CTRL_MASK(SETUP, scb2_en));
/* Override the default OC and PP polarity */
- if (ioc)
+ if (params->ioc)
reg |= USB_CTRL_MASK(SETUP, IOC);
- if (ipp)
+ if (params->ipp)
reg |= USB_CTRL_MASK(SETUP, IPP);
DEV_WR(USB_CTRL_REG(ctrl, SETUP), reg);
- /* override lame bridge defaults */
- reg = DEV_RD(USB_CTRL_REG(ctrl, OBRIDGE));
- reg &= ~USB_CTRL_MASK(OBRIDGE, OBR_SEQ_EN);
- DEV_WR(USB_CTRL_REG(ctrl, OBRIDGE), reg);
- reg = DEV_RD(USB_CTRL_REG(ctrl, EBRIDGE));
- reg &= ~USB_CTRL_MASK(EBRIDGE, EBR_SEQ_EN);
- reg &= ~USB_CTRL_MASK(EBRIDGE, EBR_SCB_SIZE);
- reg |= (0x08 << USB_CTRL_SHIFT(EBRIDGE, EBR_SCB_SIZE));
- DEV_WR(USB_CTRL_REG(ctrl, EBRIDGE), reg);
memc_fix(ctrl);
+ if (params->has_xhci) {
+ xhci_soft_reset(ctrl, 0);
+ usb3_otp_fix(ctrl, params->xhci_ec_regs);
+ }
}
diff --git a/drivers/usb/host/usb-brcm-common-init.h b/drivers/usb/host/usb-brcm-common-init.h
index a153c31..8e5f771 100644
--- a/drivers/usb/host/usb-brcm-common-init.h
+++ b/drivers/usb/host/usb-brcm-common-init.h
@@ -1,21 +1,42 @@
/*
- * Copyright (C) 2014 Broadcom Corporation
+ * Copyright (C) 2014-2015 Broadcom Corporation
*
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * 3. Neither the name of the project nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
*
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
+ * THIS SOFTWARE IS PROVIDED BY THE PROJECT AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE PROJECT OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
*/
#ifndef _USB_BRCM_COMMON_INIT_H
#define _USB_BRCM_COMMON_INIT_H
-void brcm_usb_common_ctrl_init(uintptr_t ctrl, int ioc, int ipp, int xhci);
-void brcm_usb_common_ctrl_xhci_soft_reset(uintptr_t ctrl, int on_off);
+struct brcm_usb_common_init_params {
+ uintptr_t ctrl_regs;
+ int ioc;
+ int ipp;
+ int has_xhci;
+ uintptr_t xhci_ec_regs;
+};
+
+void brcm_usb_common_init(struct brcm_usb_common_init_params *params);
#endif /* _USB_BRCM_COMMON_INIT_H */
diff --git a/drivers/usb/host/usb-brcm.c b/drivers/usb/host/usb-brcm.c
index 8acfbac..7cf231e 100644
--- a/drivers/usb/host/usb-brcm.c
+++ b/drivers/usb/host/usb-brcm.c
@@ -28,6 +28,7 @@
struct brcm_usb_instance {
void __iomem *ctrl_regs;
+ void __iomem *xhci_ec_regs;
int ioc;
int ipp;
int has_xhci;
@@ -131,9 +132,11 @@
{
struct device_node *dn = pdev->dev.of_node;
struct resource ctrl_res;
+ struct resource xhci_ec_res;
const u32 *prop;
struct brcm_usb_instance *priv;
struct device_node *node;
+ struct brcm_usb_common_init_params params;
int err;
priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
@@ -152,6 +155,9 @@
return -EINVAL;
}
+ if (!of_address_to_resource(dn, 1, &xhci_ec_res))
+ priv->xhci_ec_regs =
+ devm_request_and_ioremap(&pdev->dev, &xhci_ec_res);
prop = of_get_property(dn, "ipp", NULL);
if (prop)
priv->ipp = be32_to_cpup(prop);
@@ -171,9 +177,12 @@
err = clk_prepare_enable(priv->usb_clk);
if (err)
return err;
- brcm_usb_common_ctrl_xhci_soft_reset((uintptr_t)priv->ctrl_regs, false);
- brcm_usb_common_ctrl_init((uintptr_t)priv->ctrl_regs, priv->ioc,
- priv->ipp, priv->has_xhci);
+ params.ctrl_regs = (uintptr_t)priv->ctrl_regs;
+ params.ioc = priv->ioc;
+ params.ipp = priv->ipp;
+ params.has_xhci = priv->has_xhci;
+ params.xhci_ec_regs = (uintptr_t)priv->xhci_ec_regs;
+ brcm_usb_common_init(¶ms);
return of_platform_populate(dn, NULL, NULL, NULL);
}
@@ -189,10 +198,15 @@
static int brcm_usb_instance_resume(struct device *dev)
{
struct brcm_usb_instance *priv = dev_get_drvdata(dev);
+ struct brcm_usb_common_init_params params;
+
clk_enable(priv->usb_clk);
- brcm_usb_common_ctrl_xhci_soft_reset((uintptr_t)priv->ctrl_regs, false);
- brcm_usb_common_ctrl_init((uintptr_t)priv->ctrl_regs, priv->ioc,
- priv->ipp, priv->has_xhci);
+ params.ctrl_regs = (uintptr_t)priv->ctrl_regs;
+ params.ioc = priv->ioc;
+ params.ipp = priv->ipp;
+ params.has_xhci = priv->has_xhci;
+ params.xhci_ec_regs = (uintptr_t)priv->xhci_ec_regs;
+ brcm_usb_common_init(¶ms);
return 0;
}
#endif /* CONFIG_PM_SLEEP */
diff --git a/fs/proc/meminfo.c b/fs/proc/meminfo.c
index 136e548..181c388 100644
--- a/fs/proc/meminfo.c
+++ b/fs/proc/meminfo.c
@@ -12,6 +12,9 @@
#include <linux/vmstat.h>
#include <linux/atomic.h>
#include <linux/vmalloc.h>
+#ifdef CONFIG_CMA
+#include <linux/cma.h>
+#endif
#include <asm/page.h>
#include <asm/pgtable.h>
#include "internal.h"
@@ -138,6 +141,10 @@
#ifdef CONFIG_TRANSPARENT_HUGEPAGE
"AnonHugePages: %8lu kB\n"
#endif
+#ifdef CONFIG_CMA
+ "CmaTotal: %8lu kB\n"
+ "CmaFree: %8lu kB\n"
+#endif
,
K(i.totalram),
K(i.freeram),
@@ -187,12 +194,16 @@
vmi.used >> 10,
vmi.largest_chunk >> 10
#ifdef CONFIG_MEMORY_FAILURE
- ,atomic_long_read(&num_poisoned_pages) << (PAGE_SHIFT - 10)
+ , atomic_long_read(&num_poisoned_pages) << (PAGE_SHIFT - 10)
#endif
#ifdef CONFIG_TRANSPARENT_HUGEPAGE
- ,K(global_page_state(NR_ANON_TRANSPARENT_HUGEPAGES) *
+ , K(global_page_state(NR_ANON_TRANSPARENT_HUGEPAGES) *
HPAGE_PMD_NR)
#endif
+#ifdef CONFIG_CMA
+ , K(totalcma_pages)
+ , K(global_page_state(NR_FREE_CMA_PAGES))
+#endif
);
hugetlb_report_meminfo(m);
diff --git a/include/asm-generic/bug.h b/include/asm-generic/bug.h
index 7d10f96..bbd2872 100644
--- a/include/asm-generic/bug.h
+++ b/include/asm-generic/bug.h
@@ -112,12 +112,13 @@
#endif
#ifndef HAVE_ARCH_BUG_ON
-#define BUG_ON(condition) do { if (condition) ; } while(0)
+#define BUG_ON(condition) do { if (unlikely(condition)) BUG(); } while(0)
#endif
#ifndef HAVE_ARCH_WARN_ON
#define WARN_ON(condition) ({ \
int __ret_warn_on = !!(condition); \
+ (void)__ret_warn_on; \
unlikely(__ret_warn_on); \
})
#endif
@@ -125,6 +126,8 @@
#ifndef WARN
#define WARN(condition, format...) ({ \
int __ret_warn_on = !!(condition); \
+ if (0 && (__ret_warn_on)) \
+ printk(format); \
unlikely(__ret_warn_on); \
})
#endif
diff --git a/include/asm-generic/gpio.h b/include/asm-generic/gpio.h
index a5f56a0..23e3645 100644
--- a/include/asm-generic/gpio.h
+++ b/include/asm-generic/gpio.h
@@ -69,7 +69,7 @@
}
static inline int gpio_direction_output(unsigned gpio, int value)
{
- return gpiod_direction_output(gpio_to_desc(gpio), value);
+ return gpiod_direction_output_raw(gpio_to_desc(gpio), value);
}
static inline int gpio_set_debounce(unsigned gpio, unsigned debounce)
diff --git a/include/asm-generic/vmlinux.lds.h b/include/asm-generic/vmlinux.lds.h
index bc2121f..146e4ff 100644
--- a/include/asm-generic/vmlinux.lds.h
+++ b/include/asm-generic/vmlinux.lds.h
@@ -167,6 +167,25 @@
#define CLK_OF_TABLES()
#endif
+#ifdef CONFIG_OF_RESERVED_MEM
+#define RESERVEDMEM_OF_TABLES() \
+ . = ALIGN(8); \
+ VMLINUX_SYMBOL(__reservedmem_of_table) = .; \
+ *(__reservedmem_of_table) \
+ *(__reservedmem_of_table_end)
+#else
+#define RESERVEDMEM_OF_TABLES()
+#endif
+
+#ifdef CONFIG_SMP
+#define CPU_METHOD_OF_TABLES() . = ALIGN(8); \
+ VMLINUX_SYMBOL(__cpu_method_of_table_begin) = .; \
+ *(__cpu_method_of_table) \
+ VMLINUX_SYMBOL(__cpu_method_of_table_end) = .;
+#else
+#define CPU_METHOD_OF_TABLES()
+#endif
+
#define KERNEL_DTB() \
STRUCT_ALIGN(); \
VMLINUX_SYMBOL(__dtb_start) = .; \
@@ -490,7 +509,9 @@
TRACE_SYSCALLS() \
MEM_DISCARD(init.rodata) \
CLK_OF_TABLES() \
+ RESERVEDMEM_OF_TABLES() \
CLKSRC_OF_TABLES() \
+ CPU_METHOD_OF_TABLES() \
KERNEL_DTB() \
IRQCHIP_OF_MATCH_TABLE()
diff --git a/include/dt-bindings/thermal/thermal.h b/include/dt-bindings/thermal/thermal.h
index 59822a9..b5e6b00 100644
--- a/include/dt-bindings/thermal/thermal.h
+++ b/include/dt-bindings/thermal/thermal.h
@@ -11,7 +11,7 @@
#define _DT_BINDINGS_THERMAL_THERMAL_H
/* On cooling devices upper and lower limits */
-#define THERMAL_NO_LIMIT (-1UL)
+#define THERMAL_NO_LIMIT (~0)
#endif
diff --git a/include/linux/bmoca.h b/include/linux/bmoca.h
index e193cb8..fac7f4e 100644
--- a/include/linux/bmoca.h
+++ b/include/linux/bmoca.h
@@ -142,6 +142,8 @@
MOCA_SUSPENDING_GOT_ACK,
MOCA_SUSPENDED,
MOCA_RESUMING,
+ MOCA_RESUMING_ASSERT,
+ MOCA_RESUMING_WDOG,
MOCA_NONE
};
diff --git a/include/linux/brcmphy.h b/include/linux/brcmphy.h
index 2008100..85017d1 100644
--- a/include/linux/brcmphy.h
+++ b/include/linux/brcmphy.h
@@ -1,6 +1,11 @@
#ifndef _LINUX_BRCMPHY_H
#define _LINUX_BRCMPHY_H
+/* All Broadcom Ethernet switches have a pseudo-PHY at address 30 which is used
+ * to configure the switch internal registers via MDIO accesses.
+ */
+#define BRCM_PSEUDO_PHY_ADDR 30
+
#define PHY_ID_BCM50610 0x0143bd60
#define PHY_ID_BCM50610M 0x0143bd70
#define PHY_ID_BCM5241 0x0143bc30
diff --git a/include/linux/brcmstb/7145a0/bchp_aon_ctrl.h b/include/linux/brcmstb/7145a0/bchp_aon_ctrl.h
deleted file mode 100644
index c88161c..0000000
--- a/include/linux/brcmstb/7145a0/bchp_aon_ctrl.h
+++ /dev/null
@@ -1,1911 +0,0 @@
-/***************************************************************************
- * Copyright (c) 1999-2013, Broadcom Corporation
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
- *
- * Module Description:
- * DO NOT EDIT THIS FILE DIRECTLY
- *
- * This module was generated magically with RDB from a source description
- * file. You must edit the source file for changes to be made to this file.
- *
- *
- * Date: Generated on Sat Apr 6 03:07:46 2013
- * MD5 Checksum d41d8cd98f00b204e9800998ecf8427e
- *
- * Compiled with: RDB Utility combo_header.pl
- * RDB Parser 3.0
- * unknown unknown
- * Perl Interpreter 5.008008
- * Operating System linux
- *
- * Revision History:
- *
- * $brcm_Log: $
- *
- ***************************************************************************/
-
-#ifndef BCHP_AON_CTRL_H__
-#define BCHP_AON_CTRL_H__
-
-/***************************************************************************
- *AON_CTRL - AON Control Registers
- ***************************************************************************/
-#define BCHP_AON_CTRL_RESET_CTRL 0x20410000 /* Reset Control register for AON */
-#define BCHP_AON_CTRL_PM_CTRL 0x20410004 /* Control register for Power Controller */
-#define BCHP_AON_CTRL_PM_STATUS 0x20410008 /* Status register for Power Controller */
-#define BCHP_AON_CTRL_PM_IRQ_INPUT_STATUS 0x2041000c /* Power Management IRQ input status */
-#define BCHP_AON_CTRL_PM_CPU_WAIT_COUNT 0x20410010 /* Power Management Wait counter in place of Wait for Host CPU IRQ */
-#define BCHP_AON_CTRL_PM_CPU_GUARDBAND_TIMER 0x20410014 /* Power Good Guardband Timer for Host CPU */
-#define BCHP_AON_CTRL_PM_S3_STANDBY_TIMER 0x20410018 /* Deep Standby or Battery Standby Assertion Timer */
-#define BCHP_AON_CTRL_PM_S3_WAKEUP_TIMER 0x2041001c /* Deep Standby or Battery Standby Wakeup Timer */
-#define BCHP_AON_CTRL_PM_FAST_PWRDN_PRECHARGE 0x20410020 /* Control register for Power Controller */
-#define BCHP_AON_CTRL_PM_LED_CTRL 0x20410024 /* LED set control register */
-#define BCHP_AON_CTRL_PM_LED_AUTO_ON_ENABLES 0x20410028 /* LED set control register */
-#define BCHP_AON_CTRL_PM_CM_STATUS 0x2041002c /* CM Status register for Power Controller */
-#define BCHP_AON_CTRL_HLCD_CTRL 0x20410030 /* HW LED Clock Driver Control */
-#define BCHP_AON_CTRL_SECOND_FRACTION_COUNTER 0x20410034 /* Second Fraction Counter Initial value */
-#define BCHP_AON_CTRL_TIME_COUNTER 0x20410038 /* Hour/Minute Counter Initial value */
-#define BCHP_AON_CTRL_LED_DIGIT_CODE_0 0x2041003c /* Digit Code for digit 0, 1, 2, 3 */
-#define BCHP_AON_CTRL_LED_DIGIT_CODE_1 0x20410040 /* Digit Code for digit 4, 5, 6, 7 */
-#define BCHP_AON_CTRL_LED_DIGIT_CODE_2 0x20410044 /* Digit Code for digit 8, 9 */
-#define BCHP_AON_CTRL_LED_DIGIT_ADDR_OFFSET 0x20410048 /* Hour MSD/LSD and minute MSD/LSD address offset */
-#define BCHP_AON_CTRL_LED_STATUS_CTRL 0x2041004c /* LED status control */
-#define BCHP_AON_CTRL_GENERAL_CTRL_0 0x20410050 /* General control register 0 */
-#define BCHP_AON_CTRL_GENERAL_STATUS_0 0x20410054 /* General status register 0 */
-#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0 0x20410058 /* General control register without scan 0 */
-#define BCHP_AON_CTRL_PM_BATTERY_MODE_DEBUG_STATUS 0x2041005c /* Battery Mode Debug Status */
-#define BCHP_AON_CTRL_PM_BATTERY_MODE_FAILSAFE_TIMER 0x20410060 /* Battery Standby Mode Failsafe Timer */
-#define BCHP_AON_CTRL_REBOOT_ON_POWERLOSS_TIMER 0x20410064 /* Reboot on AC Powerloss Timer */
-#define BCHP_AON_CTRL_UNCLEARED_SCRATCH 0x20410068 /* Scratch register */
-#define BCHP_AON_CTRL_RESET_HISTORY 0x2041006c /* Reset History Register For AON */
-#define BCHP_AON_CTRL_NMI_CTRL 0x20410070 /* Control register for NMI */
-#define BCHP_AON_CTRL_ANA_XTAL_CONTROL 0x20410074 /* Ana xtal gisb control */
-#define BCHP_AON_CTRL_SUB_TEST_MODE_CTRL 0x20410078 /* Test_mode control register */
-#define BCHP_AON_CTRL_SUB_TEST_MODE 0x2041007c /* Register source for sub_test_mode */
-#define BCHP_AON_CTRL_LATCHED_TEST_MODE 0x20410080 /* Final latched testmode value */
-#define BCHP_AON_CTRL_LATCHED_SUB_TEST_MODE 0x20410084 /* Final latched sub-testmode value */
-#define BCHP_AON_CTRL_PM_INITIATE 0x20410088 /* Power down initiate */
-#define BCHP_AON_CTRL_HOST_MISC_CMDS 0x2041008c /* Power up restore */
-#define BCHP_AON_CTRL_ANA_XTAL_EXT_CML_CONTROL 0x20410090 /* Ana xtal external CML control */
-#define BCHP_AON_CTRL_SPARE_CTRL_0 0x20410094 /* Spare control bits reserved for future use */
-#define BCHP_AON_CTRL_SPARE_CTRL_1 0x20410098 /* Spare control bits reserved for future use */
-
-/***************************************************************************
- *RESET_CTRL - Reset Control register for AON
- ***************************************************************************/
-/* AON_CTRL :: RESET_CTRL :: reserved0 [31:04] */
-#define BCHP_AON_CTRL_RESET_CTRL_reserved0_MASK 0xfffffff0
-#define BCHP_AON_CTRL_RESET_CTRL_reserved0_SHIFT 4
-
-/* AON_CTRL :: RESET_CTRL :: front_panel_reset_enable_lock [03:03] */
-#define BCHP_AON_CTRL_RESET_CTRL_front_panel_reset_enable_lock_MASK 0x00000008
-#define BCHP_AON_CTRL_RESET_CTRL_front_panel_reset_enable_lock_SHIFT 3
-#define BCHP_AON_CTRL_RESET_CTRL_front_panel_reset_enable_lock_DEFAULT 0x00000000
-
-/* AON_CTRL :: RESET_CTRL :: front_panel_reset_enable [02:02] */
-#define BCHP_AON_CTRL_RESET_CTRL_front_panel_reset_enable_MASK 0x00000004
-#define BCHP_AON_CTRL_RESET_CTRL_front_panel_reset_enable_SHIFT 2
-#define BCHP_AON_CTRL_RESET_CTRL_front_panel_reset_enable_DEFAULT 0x00000000
-
-/* AON_CTRL :: RESET_CTRL :: front_panel_reset_polarity [01:01] */
-#define BCHP_AON_CTRL_RESET_CTRL_front_panel_reset_polarity_MASK 0x00000002
-#define BCHP_AON_CTRL_RESET_CTRL_front_panel_reset_polarity_SHIFT 1
-#define BCHP_AON_CTRL_RESET_CTRL_front_panel_reset_polarity_DEFAULT 0x00000000
-
-/* AON_CTRL :: RESET_CTRL :: clear_reset_history [00:00] */
-#define BCHP_AON_CTRL_RESET_CTRL_clear_reset_history_MASK 0x00000001
-#define BCHP_AON_CTRL_RESET_CTRL_clear_reset_history_SHIFT 0
-#define BCHP_AON_CTRL_RESET_CTRL_clear_reset_history_DEFAULT 0x00000000
-
-/***************************************************************************
- *PM_CTRL - Control register for Power Controller
- ***************************************************************************/
-/* AON_CTRL :: PM_CTRL :: reserved0 [31:20] */
-#define BCHP_AON_CTRL_PM_CTRL_reserved0_MASK 0xfff00000
-#define BCHP_AON_CTRL_PM_CTRL_reserved0_SHIFT 20
-
-/* AON_CTRL :: PM_CTRL :: pm_clear_battery_mode_debug_status [19:19] */
-#define BCHP_AON_CTRL_PM_CTRL_pm_clear_battery_mode_debug_status_MASK 0x00080000
-#define BCHP_AON_CTRL_PM_CTRL_pm_clear_battery_mode_debug_status_SHIFT 19
-
-/* AON_CTRL :: PM_CTRL :: reboot_on_powerloss [18:18] */
-#define BCHP_AON_CTRL_PM_CTRL_reboot_on_powerloss_MASK 0x00040000
-#define BCHP_AON_CTRL_PM_CTRL_reboot_on_powerloss_SHIFT 18
-#define BCHP_AON_CTRL_PM_CTRL_reboot_on_powerloss_DEFAULT 0x00000000
-
-/* AON_CTRL :: PM_CTRL :: pm_battery_mode_failsafe_timer_start [17:17] */
-#define BCHP_AON_CTRL_PM_CTRL_pm_battery_mode_failsafe_timer_start_MASK 0x00020000
-#define BCHP_AON_CTRL_PM_CTRL_pm_battery_mode_failsafe_timer_start_SHIFT 17
-
-/* AON_CTRL :: PM_CTRL :: pm_battery_mode_failsafe_timer_enable [16:16] */
-#define BCHP_AON_CTRL_PM_CTRL_pm_battery_mode_failsafe_timer_enable_MASK 0x00010000
-#define BCHP_AON_CTRL_PM_CTRL_pm_battery_mode_failsafe_timer_enable_SHIFT 16
-#define BCHP_AON_CTRL_PM_CTRL_pm_battery_mode_failsafe_timer_enable_DEFAULT 0x00000000
-
-/* AON_CTRL :: PM_CTRL :: pm_allow_s2_to_battery_standby [15:15] */
-#define BCHP_AON_CTRL_PM_CTRL_pm_allow_s2_to_battery_standby_MASK 0x00008000
-#define BCHP_AON_CTRL_PM_CTRL_pm_allow_s2_to_battery_standby_SHIFT 15
-#define BCHP_AON_CTRL_PM_CTRL_pm_allow_s2_to_battery_standby_DEFAULT 0x00000000
-
-/* AON_CTRL :: PM_CTRL :: pm_allow_docsis_in_s2_standby [14:14] */
-#define BCHP_AON_CTRL_PM_CTRL_pm_allow_docsis_in_s2_standby_MASK 0x00004000
-#define BCHP_AON_CTRL_PM_CTRL_pm_allow_docsis_in_s2_standby_SHIFT 14
-#define BCHP_AON_CTRL_PM_CTRL_pm_allow_docsis_in_s2_standby_DEFAULT 0x00000000
-
-/* AON_CTRL :: PM_CTRL :: pm_set_force_battery_mode [13:13] */
-#define BCHP_AON_CTRL_PM_CTRL_pm_set_force_battery_mode_MASK 0x00002000
-#define BCHP_AON_CTRL_PM_CTRL_pm_set_force_battery_mode_SHIFT 13
-
-/* AON_CTRL :: PM_CTRL :: pm_set_auto_battery_mode_rules [12:12] */
-#define BCHP_AON_CTRL_PM_CTRL_pm_set_auto_battery_mode_rules_MASK 0x00001000
-#define BCHP_AON_CTRL_PM_CTRL_pm_set_auto_battery_mode_rules_SHIFT 12
-
-/* AON_CTRL :: PM_CTRL :: pm_wait_for_avs_ready [11:11] */
-#define BCHP_AON_CTRL_PM_CTRL_pm_wait_for_avs_ready_MASK 0x00000800
-#define BCHP_AON_CTRL_PM_CTRL_pm_wait_for_avs_ready_SHIFT 11
-#define BCHP_AON_CTRL_PM_CTRL_pm_wait_for_avs_ready_DEFAULT 0x00000000
-
-/* AON_CTRL :: PM_CTRL :: pm_wait_on_u2u_deregister [10:10] */
-#define BCHP_AON_CTRL_PM_CTRL_pm_wait_on_u2u_deregister_MASK 0x00000400
-#define BCHP_AON_CTRL_PM_CTRL_pm_wait_on_u2u_deregister_SHIFT 10
-#define BCHP_AON_CTRL_PM_CTRL_pm_wait_on_u2u_deregister_DEFAULT 0x00000000
-
-/* AON_CTRL :: PM_CTRL :: pm_battery_standby [09:09] */
-#define BCHP_AON_CTRL_PM_CTRL_pm_battery_standby_MASK 0x00000200
-#define BCHP_AON_CTRL_PM_CTRL_pm_battery_standby_SHIFT 9
-#define BCHP_AON_CTRL_PM_CTRL_pm_battery_standby_DEFAULT 0x00000000
-
-/* AON_CTRL :: PM_CTRL :: pm_battery_stby_nmi_mask [08:08] */
-#define BCHP_AON_CTRL_PM_CTRL_pm_battery_stby_nmi_mask_MASK 0x00000100
-#define BCHP_AON_CTRL_PM_CTRL_pm_battery_stby_nmi_mask_SHIFT 8
-#define BCHP_AON_CTRL_PM_CTRL_pm_battery_stby_nmi_mask_DEFAULT 0x00000001
-
-/* AON_CTRL :: PM_CTRL :: min_s3_width_timer_bypass [07:07] */
-#define BCHP_AON_CTRL_PM_CTRL_min_s3_width_timer_bypass_MASK 0x00000080
-#define BCHP_AON_CTRL_PM_CTRL_min_s3_width_timer_bypass_SHIFT 7
-#define BCHP_AON_CTRL_PM_CTRL_min_s3_width_timer_bypass_DEFAULT 0x00000000
-
-/* AON_CTRL :: PM_CTRL :: pm_fast_power_down [06:06] */
-#define BCHP_AON_CTRL_PM_CTRL_pm_fast_power_down_MASK 0x00000040
-#define BCHP_AON_CTRL_PM_CTRL_pm_fast_power_down_SHIFT 6
-#define BCHP_AON_CTRL_PM_CTRL_pm_fast_power_down_DEFAULT 0x00000000
-
-/* AON_CTRL :: PM_CTRL :: pm_warm_boot [05:05] */
-#define BCHP_AON_CTRL_PM_CTRL_pm_warm_boot_MASK 0x00000020
-#define BCHP_AON_CTRL_PM_CTRL_pm_warm_boot_SHIFT 5
-#define BCHP_AON_CTRL_PM_CTRL_pm_warm_boot_DEFAULT 0x00000000
-
-/* AON_CTRL :: PM_CTRL :: pm_deep_standby [04:04] */
-#define BCHP_AON_CTRL_PM_CTRL_pm_deep_standby_MASK 0x00000010
-#define BCHP_AON_CTRL_PM_CTRL_pm_deep_standby_SHIFT 4
-#define BCHP_AON_CTRL_PM_CTRL_pm_deep_standby_DEFAULT 0x00000000
-
-/* AON_CTRL :: PM_CTRL :: pm_enable_cpu_pwrdn [03:03] */
-#define BCHP_AON_CTRL_PM_CTRL_pm_enable_cpu_pwrdn_MASK 0x00000008
-#define BCHP_AON_CTRL_PM_CTRL_pm_enable_cpu_pwrdn_SHIFT 3
-#define BCHP_AON_CTRL_PM_CTRL_pm_enable_cpu_pwrdn_DEFAULT 0x00000001
-
-/* AON_CTRL :: PM_CTRL :: pm_use_cpu_ready_ctrl [02:02] */
-#define BCHP_AON_CTRL_PM_CTRL_pm_use_cpu_ready_ctrl_MASK 0x00000004
-#define BCHP_AON_CTRL_PM_CTRL_pm_use_cpu_ready_ctrl_SHIFT 2
-#define BCHP_AON_CTRL_PM_CTRL_pm_use_cpu_ready_ctrl_DEFAULT 0x00000000
-
-/* AON_CTRL :: PM_CTRL :: pm_enable_pll_pwrdn [01:01] */
-#define BCHP_AON_CTRL_PM_CTRL_pm_enable_pll_pwrdn_MASK 0x00000002
-#define BCHP_AON_CTRL_PM_CTRL_pm_enable_pll_pwrdn_SHIFT 1
-#define BCHP_AON_CTRL_PM_CTRL_pm_enable_pll_pwrdn_DEFAULT 0x00000000
-
-/* AON_CTRL :: PM_CTRL :: pm_start_pwrdn [00:00] */
-#define BCHP_AON_CTRL_PM_CTRL_pm_start_pwrdn_MASK 0x00000001
-#define BCHP_AON_CTRL_PM_CTRL_pm_start_pwrdn_SHIFT 0
-
-/***************************************************************************
- *PM_STATUS - Status register for Power Controller
- ***************************************************************************/
-/* AON_CTRL :: PM_STATUS :: pm_wait_count_upper_bits [31:28] */
-#define BCHP_AON_CTRL_PM_STATUS_pm_wait_count_upper_bits_MASK 0xf0000000
-#define BCHP_AON_CTRL_PM_STATUS_pm_wait_count_upper_bits_SHIFT 28
-
-/* AON_CTRL :: PM_STATUS :: pm_wait_counter_active [27:27] */
-#define BCHP_AON_CTRL_PM_STATUS_pm_wait_counter_active_MASK 0x08000000
-#define BCHP_AON_CTRL_PM_STATUS_pm_wait_counter_active_SHIFT 27
-
-/* AON_CTRL :: PM_STATUS :: pm_power_down_cpu [26:26] */
-#define BCHP_AON_CTRL_PM_STATUS_pm_power_down_cpu_MASK 0x04000000
-#define BCHP_AON_CTRL_PM_STATUS_pm_power_down_cpu_SHIFT 26
-
-/* AON_CTRL :: PM_STATUS :: pm_cpu_reset_b [25:25] */
-#define BCHP_AON_CTRL_PM_STATUS_pm_cpu_reset_b_MASK 0x02000000
-#define BCHP_AON_CTRL_PM_STATUS_pm_cpu_reset_b_SHIFT 25
-
-/* AON_CTRL :: PM_STATUS :: pm_s3_wakeup_reset_ [24:24] */
-#define BCHP_AON_CTRL_PM_STATUS_pm_s3_wakeup_reset__MASK 0x01000000
-#define BCHP_AON_CTRL_PM_STATUS_pm_s3_wakeup_reset__SHIFT 24
-
-/* AON_CTRL :: PM_STATUS :: pm_boundary_scan_request [23:23] */
-#define BCHP_AON_CTRL_PM_STATUS_pm_boundary_scan_request_MASK 0x00800000
-#define BCHP_AON_CTRL_PM_STATUS_pm_boundary_scan_request_SHIFT 23
-
-/* AON_CTRL :: PM_STATUS :: pm_fast_pd_precharge_valid [22:22] */
-#define BCHP_AON_CTRL_PM_STATUS_pm_fast_pd_precharge_valid_MASK 0x00400000
-#define BCHP_AON_CTRL_PM_STATUS_pm_fast_pd_precharge_valid_SHIFT 22
-
-/* AON_CTRL :: PM_STATUS :: pm_led_out [21:21] */
-#define BCHP_AON_CTRL_PM_STATUS_pm_led_out_MASK 0x00200000
-#define BCHP_AON_CTRL_PM_STATUS_pm_led_out_SHIFT 21
-
-/* AON_CTRL :: PM_STATUS :: pm_standby_b [20:20] */
-#define BCHP_AON_CTRL_PM_STATUS_pm_standby_b_MASK 0x00100000
-#define BCHP_AON_CTRL_PM_STATUS_pm_standby_b_SHIFT 20
-
-/* AON_CTRL :: PM_STATUS :: pm_ignore_inputs_ng [19:19] */
-#define BCHP_AON_CTRL_PM_STATUS_pm_ignore_inputs_ng_MASK 0x00080000
-#define BCHP_AON_CTRL_PM_STATUS_pm_ignore_inputs_ng_SHIFT 19
-
-/* AON_CTRL :: PM_STATUS :: pm_ignore_inputs [18:18] */
-#define BCHP_AON_CTRL_PM_STATUS_pm_ignore_inputs_MASK 0x00040000
-#define BCHP_AON_CTRL_PM_STATUS_pm_ignore_inputs_SHIFT 18
-
-/* AON_CTRL :: PM_STATUS :: pm_s2_standby [17:17] */
-#define BCHP_AON_CTRL_PM_STATUS_pm_s2_standby_MASK 0x00020000
-#define BCHP_AON_CTRL_PM_STATUS_pm_s2_standby_SHIFT 17
-
-/* AON_CTRL :: PM_STATUS :: pm_pwrdn_pll_req [16:16] */
-#define BCHP_AON_CTRL_PM_STATUS_pm_pwrdn_pll_req_MASK 0x00010000
-#define BCHP_AON_CTRL_PM_STATUS_pm_pwrdn_pll_req_SHIFT 16
-
-/* AON_CTRL :: PM_STATUS :: pm_dis_xtal_clocks [15:15] */
-#define BCHP_AON_CTRL_PM_STATUS_pm_dis_xtal_clocks_MASK 0x00008000
-#define BCHP_AON_CTRL_PM_STATUS_pm_dis_xtal_clocks_SHIFT 15
-
-/* AON_CTRL :: PM_STATUS :: pm_dis_all_clocks [14:14] */
-#define BCHP_AON_CTRL_PM_STATUS_pm_dis_all_clocks_MASK 0x00004000
-#define BCHP_AON_CTRL_PM_STATUS_pm_dis_all_clocks_SHIFT 14
-
-/* AON_CTRL :: PM_STATUS :: pm_dphy_standby [13:13] */
-#define BCHP_AON_CTRL_PM_STATUS_pm_dphy_standby_MASK 0x00002000
-#define BCHP_AON_CTRL_PM_STATUS_pm_dphy_standby_SHIFT 13
-
-/* AON_CTRL :: PM_STATUS :: pm_dis_cpu_clock [12:12] */
-#define BCHP_AON_CTRL_PM_STATUS_pm_dis_cpu_clock_MASK 0x00001000
-#define BCHP_AON_CTRL_PM_STATUS_pm_dis_cpu_clock_SHIFT 12
-
-/* AON_CTRL :: PM_STATUS :: pm_dis_avd_rptd_clock [11:11] */
-#define BCHP_AON_CTRL_PM_STATUS_pm_dis_avd_rptd_clock_MASK 0x00000800
-#define BCHP_AON_CTRL_PM_STATUS_pm_dis_avd_rptd_clock_SHIFT 11
-
-/* AON_CTRL :: PM_STATUS :: pm_power_ctrl_disable [10:10] */
-#define BCHP_AON_CTRL_PM_STATUS_pm_power_ctrl_disable_MASK 0x00000400
-#define BCHP_AON_CTRL_PM_STATUS_pm_power_ctrl_disable_SHIFT 10
-
-/* AON_CTRL :: PM_STATUS :: pm_pll_lock [09:09] */
-#define BCHP_AON_CTRL_PM_STATUS_pm_pll_lock_MASK 0x00000200
-#define BCHP_AON_CTRL_PM_STATUS_pm_pll_lock_SHIFT 9
-
-/* AON_CTRL :: PM_STATUS :: pm_dram_ready_for_pwrdn [08:08] */
-#define BCHP_AON_CTRL_PM_STATUS_pm_dram_ready_for_pwrdn_MASK 0x00000100
-#define BCHP_AON_CTRL_PM_STATUS_pm_dram_ready_for_pwrdn_SHIFT 8
-
-/* AON_CTRL :: PM_STATUS :: pm_bsp_ready_for_pwrdn [07:07] */
-#define BCHP_AON_CTRL_PM_STATUS_pm_bsp_ready_for_pwrdn_MASK 0x00000080
-#define BCHP_AON_CTRL_PM_STATUS_pm_bsp_ready_for_pwrdn_SHIFT 7
-
-/* AON_CTRL :: PM_STATUS :: pm_cpu_ready_for_pwrdn [06:06] */
-#define BCHP_AON_CTRL_PM_STATUS_pm_cpu_ready_for_pwrdn_MASK 0x00000040
-#define BCHP_AON_CTRL_PM_STATUS_pm_cpu_ready_for_pwrdn_SHIFT 6
-
-/* AON_CTRL :: PM_STATUS :: pm_sec_avd_rptd_clk_disable [05:05] */
-#define BCHP_AON_CTRL_PM_STATUS_pm_sec_avd_rptd_clk_disable_MASK 0x00000020
-#define BCHP_AON_CTRL_PM_STATUS_pm_sec_avd_rptd_clk_disable_SHIFT 5
-
-/* AON_CTRL :: PM_STATUS :: pm_state [04:00] */
-#define BCHP_AON_CTRL_PM_STATUS_pm_state_MASK 0x0000001f
-#define BCHP_AON_CTRL_PM_STATUS_pm_state_SHIFT 0
-#define BCHP_AON_CTRL_PM_STATUS_pm_state_PM_ACTIVE 0
-#define BCHP_AON_CTRL_PM_STATUS_pm_state_PM_PWRDN_RDY 1
-#define BCHP_AON_CTRL_PM_STATUS_pm_state_PM_DISABLE_AVD_RPTD 2
-#define BCHP_AON_CTRL_PM_STATUS_pm_state_PM_DISABLE_CPU 3
-#define BCHP_AON_CTRL_PM_STATUS_pm_state_PM_TRANSITION_TO_STANDBY 4
-#define BCHP_AON_CTRL_PM_STATUS_pm_state_PM_STANDBY 5
-#define BCHP_AON_CTRL_PM_STATUS_pm_state_PM_STANDBY_WITH_PLLS_ON 6
-#define BCHP_AON_CTRL_PM_STATUS_pm_state_PM_HOLD_CPU_POWERED_DOWN 7
-#define BCHP_AON_CTRL_PM_STATUS_pm_state_PM_POWER_UP_CPU 8
-#define BCHP_AON_CTRL_PM_STATUS_pm_state_PM_TRANSITION_TO_ACTIVE 9
-#define BCHP_AON_CTRL_PM_STATUS_pm_state_PM_FAST_PWRDN 10
-#define BCHP_AON_CTRL_PM_STATUS_pm_state_PM_DEEP_STANDBY_ENTRY_S1 11
-#define BCHP_AON_CTRL_PM_STATUS_pm_state_PM_DEEP_STANDBY_COLD_ENTRY_S2 12
-#define BCHP_AON_CTRL_PM_STATUS_pm_state_PM_DEEP_STANDBY_WARM_ENTRY_S2 13
-#define BCHP_AON_CTRL_PM_STATUS_pm_state_PM_DEEP_STANDBY_ENTRY_S3 14
-#define BCHP_AON_CTRL_PM_STATUS_pm_state_PM_DEEP_STANDBY 15
-#define BCHP_AON_CTRL_PM_STATUS_pm_state_PM_DEEP_STANDBY_EXIT_S1 16
-#define BCHP_AON_CTRL_PM_STATUS_pm_state_PM_DEEP_STANDBY_EXIT_S2 17
-#define BCHP_AON_CTRL_PM_STATUS_pm_state_PM_BATTERY_STANDBY_ENTRY_S1 18
-#define BCHP_AON_CTRL_PM_STATUS_pm_state_PM_BATTERY_STANDBY_COLD_ENTRY_S2 19
-#define BCHP_AON_CTRL_PM_STATUS_pm_state_PM_BATTERY_STANDBY_WARM_ENTRY_S2 20
-#define BCHP_AON_CTRL_PM_STATUS_pm_state_PM_BATTERY_STANDBY_ENTRY_S3 21
-#define BCHP_AON_CTRL_PM_STATUS_pm_state_PM_BATTERY_STANDBY 22
-#define BCHP_AON_CTRL_PM_STATUS_pm_state_PM_BATTERY_STANDBY_EXIT_S1 23
-#define BCHP_AON_CTRL_PM_STATUS_pm_state_PM_BATTERY_STANDBY_EXIT_S2 24
-
-/***************************************************************************
- *PM_IRQ_INPUT_STATUS - Power Management IRQ input status
- ***************************************************************************/
-/* AON_CTRL :: PM_IRQ_INPUT_STATUS :: pm_irq_input_status [31:00] */
-#define BCHP_AON_CTRL_PM_IRQ_INPUT_STATUS_pm_irq_input_status_MASK 0xffffffff
-#define BCHP_AON_CTRL_PM_IRQ_INPUT_STATUS_pm_irq_input_status_SHIFT 0
-
-/***************************************************************************
- *PM_CPU_WAIT_COUNT - Power Management Wait counter in place of Wait for Host CPU IRQ
- ***************************************************************************/
-/* AON_CTRL :: PM_CPU_WAIT_COUNT :: reserved0 [31:16] */
-#define BCHP_AON_CTRL_PM_CPU_WAIT_COUNT_reserved0_MASK 0xffff0000
-#define BCHP_AON_CTRL_PM_CPU_WAIT_COUNT_reserved0_SHIFT 16
-
-/* AON_CTRL :: PM_CPU_WAIT_COUNT :: counter_start_value [15:00] */
-#define BCHP_AON_CTRL_PM_CPU_WAIT_COUNT_counter_start_value_MASK 0x0000ffff
-#define BCHP_AON_CTRL_PM_CPU_WAIT_COUNT_counter_start_value_SHIFT 0
-#define BCHP_AON_CTRL_PM_CPU_WAIT_COUNT_counter_start_value_DEFAULT 0x00000010
-
-/***************************************************************************
- *PM_CPU_GUARDBAND_TIMER - Power Good Guardband Timer for Host CPU
- ***************************************************************************/
-/* AON_CTRL :: PM_CPU_GUARDBAND_TIMER :: reserved0 [31:10] */
-#define BCHP_AON_CTRL_PM_CPU_GUARDBAND_TIMER_reserved0_MASK 0xfffffc00
-#define BCHP_AON_CTRL_PM_CPU_GUARDBAND_TIMER_reserved0_SHIFT 10
-
-/* AON_CTRL :: PM_CPU_GUARDBAND_TIMER :: counter_start_value [09:00] */
-#define BCHP_AON_CTRL_PM_CPU_GUARDBAND_TIMER_counter_start_value_MASK 0x000003ff
-#define BCHP_AON_CTRL_PM_CPU_GUARDBAND_TIMER_counter_start_value_SHIFT 0
-#define BCHP_AON_CTRL_PM_CPU_GUARDBAND_TIMER_counter_start_value_DEFAULT 0x0000007f
-
-/***************************************************************************
- *PM_S3_STANDBY_TIMER - Deep Standby or Battery Standby Assertion Timer
- ***************************************************************************/
-/* AON_CTRL :: PM_S3_STANDBY_TIMER :: reserved0 [31:27] */
-#define BCHP_AON_CTRL_PM_S3_STANDBY_TIMER_reserved0_MASK 0xf8000000
-#define BCHP_AON_CTRL_PM_S3_STANDBY_TIMER_reserved0_SHIFT 27
-
-/* AON_CTRL :: PM_S3_STANDBY_TIMER :: counter_start_value [26:00] */
-#define BCHP_AON_CTRL_PM_S3_STANDBY_TIMER_counter_start_value_MASK 0x07ffffff
-#define BCHP_AON_CTRL_PM_S3_STANDBY_TIMER_counter_start_value_SHIFT 0
-#define BCHP_AON_CTRL_PM_S3_STANDBY_TIMER_counter_start_value_DEFAULT 0x00083d60
-
-/***************************************************************************
- *PM_S3_WAKEUP_TIMER - Deep Standby or Battery Standby Wakeup Timer
- ***************************************************************************/
-/* AON_CTRL :: PM_S3_WAKEUP_TIMER :: reserved0 [31:27] */
-#define BCHP_AON_CTRL_PM_S3_WAKEUP_TIMER_reserved0_MASK 0xf8000000
-#define BCHP_AON_CTRL_PM_S3_WAKEUP_TIMER_reserved0_SHIFT 27
-
-/* AON_CTRL :: PM_S3_WAKEUP_TIMER :: counter_start_value [26:00] */
-#define BCHP_AON_CTRL_PM_S3_WAKEUP_TIMER_counter_start_value_MASK 0x07ffffff
-#define BCHP_AON_CTRL_PM_S3_WAKEUP_TIMER_counter_start_value_SHIFT 0
-#define BCHP_AON_CTRL_PM_S3_WAKEUP_TIMER_counter_start_value_DEFAULT 0x00083d60
-
-/***************************************************************************
- *PM_FAST_PWRDN_PRECHARGE - Control register for Power Controller
- ***************************************************************************/
-/* AON_CTRL :: PM_FAST_PWRDN_PRECHARGE :: reserved0 [31:24] */
-#define BCHP_AON_CTRL_PM_FAST_PWRDN_PRECHARGE_reserved0_MASK 0xff000000
-#define BCHP_AON_CTRL_PM_FAST_PWRDN_PRECHARGE_reserved0_SHIFT 24
-
-/* AON_CTRL :: PM_FAST_PWRDN_PRECHARGE :: pm_fast_power_down_precharge [23:00] */
-#define BCHP_AON_CTRL_PM_FAST_PWRDN_PRECHARGE_pm_fast_power_down_precharge_MASK 0x00ffffff
-#define BCHP_AON_CTRL_PM_FAST_PWRDN_PRECHARGE_pm_fast_power_down_precharge_SHIFT 0
-#define BCHP_AON_CTRL_PM_FAST_PWRDN_PRECHARGE_pm_fast_power_down_precharge_DEFAULT 0x00000000
-
-/***************************************************************************
- *PM_LED_CTRL - LED set control register
- ***************************************************************************/
-/* AON_CTRL :: PM_LED_CTRL :: reserved0 [31:03] */
-#define BCHP_AON_CTRL_PM_LED_CTRL_reserved0_MASK 0xfffffff8
-#define BCHP_AON_CTRL_PM_LED_CTRL_reserved0_SHIFT 3
-
-/* AON_CTRL :: PM_LED_CTRL :: led_status [02:02] */
-#define BCHP_AON_CTRL_PM_LED_CTRL_led_status_MASK 0x00000004
-#define BCHP_AON_CTRL_PM_LED_CTRL_led_status_SHIFT 2
-
-/* AON_CTRL :: PM_LED_CTRL :: led_turn_on [01:01] */
-#define BCHP_AON_CTRL_PM_LED_CTRL_led_turn_on_MASK 0x00000002
-#define BCHP_AON_CTRL_PM_LED_CTRL_led_turn_on_SHIFT 1
-
-/* AON_CTRL :: PM_LED_CTRL :: led_turn_off [00:00] */
-#define BCHP_AON_CTRL_PM_LED_CTRL_led_turn_off_MASK 0x00000001
-#define BCHP_AON_CTRL_PM_LED_CTRL_led_turn_off_SHIFT 0
-
-/***************************************************************************
- *PM_LED_AUTO_ON_ENABLES - LED set control register
- ***************************************************************************/
-/* AON_CTRL :: PM_LED_AUTO_ON_ENABLES :: led_status [31:00] */
-#define BCHP_AON_CTRL_PM_LED_AUTO_ON_ENABLES_led_status_MASK 0xffffffff
-#define BCHP_AON_CTRL_PM_LED_AUTO_ON_ENABLES_led_status_SHIFT 0
-#define BCHP_AON_CTRL_PM_LED_AUTO_ON_ENABLES_led_status_DEFAULT 0x00000000
-
-/***************************************************************************
- *PM_CM_STATUS - CM Status register for Power Controller
- ***************************************************************************/
-/* AON_CTRL :: PM_CM_STATUS :: reserved0 [31:16] */
-#define BCHP_AON_CTRL_PM_CM_STATUS_reserved0_MASK 0xffff0000
-#define BCHP_AON_CTRL_PM_CM_STATUS_reserved0_SHIFT 16
-
-/* AON_CTRL :: PM_CM_STATUS :: pm_battery_failsafe_timer_expired_flag [15:15] */
-#define BCHP_AON_CTRL_PM_CM_STATUS_pm_battery_failsafe_timer_expired_flag_MASK 0x00008000
-#define BCHP_AON_CTRL_PM_CM_STATUS_pm_battery_failsafe_timer_expired_flag_SHIFT 15
-
-/* AON_CTRL :: PM_CM_STATUS :: pm_auto_battery_mode_rules [14:14] */
-#define BCHP_AON_CTRL_PM_CM_STATUS_pm_auto_battery_mode_rules_MASK 0x00004000
-#define BCHP_AON_CTRL_PM_CM_STATUS_pm_auto_battery_mode_rules_SHIFT 14
-
-/* AON_CTRL :: PM_CM_STATUS :: pm_cm_s3_wakeup_reset_ [13:13] */
-#define BCHP_AON_CTRL_PM_CM_STATUS_pm_cm_s3_wakeup_reset__MASK 0x00002000
-#define BCHP_AON_CTRL_PM_CM_STATUS_pm_cm_s3_wakeup_reset__SHIFT 13
-
-/* AON_CTRL :: PM_CM_STATUS :: pm_standby_b [12:12] */
-#define BCHP_AON_CTRL_PM_CM_STATUS_pm_standby_b_MASK 0x00001000
-#define BCHP_AON_CTRL_PM_CM_STATUS_pm_standby_b_SHIFT 12
-
-/* AON_CTRL :: PM_CM_STATUS :: pm_ignore_inputs_ng [11:11] */
-#define BCHP_AON_CTRL_PM_CM_STATUS_pm_ignore_inputs_ng_MASK 0x00000800
-#define BCHP_AON_CTRL_PM_CM_STATUS_pm_ignore_inputs_ng_SHIFT 11
-
-/* AON_CTRL :: PM_CM_STATUS :: pm_ignore_inputs [10:10] */
-#define BCHP_AON_CTRL_PM_CM_STATUS_pm_ignore_inputs_MASK 0x00000400
-#define BCHP_AON_CTRL_PM_CM_STATUS_pm_ignore_inputs_SHIFT 10
-
-/* AON_CTRL :: PM_CM_STATUS :: pm_pwrdn_pll_req [09:09] */
-#define BCHP_AON_CTRL_PM_CM_STATUS_pm_pwrdn_pll_req_MASK 0x00000200
-#define BCHP_AON_CTRL_PM_CM_STATUS_pm_pwrdn_pll_req_SHIFT 9
-
-/* AON_CTRL :: PM_CM_STATUS :: pm_dis_xtal_clocks [08:08] */
-#define BCHP_AON_CTRL_PM_CM_STATUS_pm_dis_xtal_clocks_MASK 0x00000100
-#define BCHP_AON_CTRL_PM_CM_STATUS_pm_dis_xtal_clocks_SHIFT 8
-
-/* AON_CTRL :: PM_CM_STATUS :: pm_dis_all_clocks [07:07] */
-#define BCHP_AON_CTRL_PM_CM_STATUS_pm_dis_all_clocks_MASK 0x00000080
-#define BCHP_AON_CTRL_PM_CM_STATUS_pm_dis_all_clocks_SHIFT 7
-
-/* AON_CTRL :: PM_CM_STATUS :: pm_dphy_standby [06:06] */
-#define BCHP_AON_CTRL_PM_CM_STATUS_pm_dphy_standby_MASK 0x00000040
-#define BCHP_AON_CTRL_PM_CM_STATUS_pm_dphy_standby_SHIFT 6
-
-/* AON_CTRL :: PM_CM_STATUS :: pm_hardware_battery_mode_transition [05:05] */
-#define BCHP_AON_CTRL_PM_CM_STATUS_pm_hardware_battery_mode_transition_MASK 0x00000020
-#define BCHP_AON_CTRL_PM_CM_STATUS_pm_hardware_battery_mode_transition_SHIFT 5
-
-/* AON_CTRL :: PM_CM_STATUS :: pm_bmu_intr_ap_lost_level [04:04] */
-#define BCHP_AON_CTRL_PM_CM_STATUS_pm_bmu_intr_ap_lost_level_MASK 0x00000010
-#define BCHP_AON_CTRL_PM_CM_STATUS_pm_bmu_intr_ap_lost_level_SHIFT 4
-
-/* AON_CTRL :: PM_CM_STATUS :: pm_gisb_idle_status [03:03] */
-#define BCHP_AON_CTRL_PM_CM_STATUS_pm_gisb_idle_status_MASK 0x00000008
-#define BCHP_AON_CTRL_PM_CM_STATUS_pm_gisb_idle_status_SHIFT 3
-
-/* AON_CTRL :: PM_CM_STATUS :: pm_avs_ready_for_pwrdn [02:02] */
-#define BCHP_AON_CTRL_PM_CM_STATUS_pm_avs_ready_for_pwrdn_MASK 0x00000004
-#define BCHP_AON_CTRL_PM_CM_STATUS_pm_avs_ready_for_pwrdn_SHIFT 2
-
-/* AON_CTRL :: PM_CM_STATUS :: pm_u2u_deregister [01:01] */
-#define BCHP_AON_CTRL_PM_CM_STATUS_pm_u2u_deregister_MASK 0x00000002
-#define BCHP_AON_CTRL_PM_CM_STATUS_pm_u2u_deregister_SHIFT 1
-
-/* AON_CTRL :: PM_CM_STATUS :: pm_dram_ready_for_pwrdn [00:00] */
-#define BCHP_AON_CTRL_PM_CM_STATUS_pm_dram_ready_for_pwrdn_MASK 0x00000001
-#define BCHP_AON_CTRL_PM_CM_STATUS_pm_dram_ready_for_pwrdn_SHIFT 0
-
-/***************************************************************************
- *HLCD_CTRL - HW LED Clock Driver Control
- ***************************************************************************/
-/* AON_CTRL :: HLCD_CTRL :: reserved0 [31:02] */
-#define BCHP_AON_CTRL_HLCD_CTRL_reserved0_MASK 0xfffffffc
-#define BCHP_AON_CTRL_HLCD_CTRL_reserved0_SHIFT 2
-
-/* AON_CTRL :: HLCD_CTRL :: hlcd_enable_status [01:01] */
-#define BCHP_AON_CTRL_HLCD_CTRL_hlcd_enable_status_MASK 0x00000002
-#define BCHP_AON_CTRL_HLCD_CTRL_hlcd_enable_status_SHIFT 1
-
-/* AON_CTRL :: HLCD_CTRL :: hlcd_enable [00:00] */
-#define BCHP_AON_CTRL_HLCD_CTRL_hlcd_enable_MASK 0x00000001
-#define BCHP_AON_CTRL_HLCD_CTRL_hlcd_enable_SHIFT 0
-#define BCHP_AON_CTRL_HLCD_CTRL_hlcd_enable_DEFAULT 0x00000000
-
-/***************************************************************************
- *SECOND_FRACTION_COUNTER - Second Fraction Counter Initial value
- ***************************************************************************/
-/* AON_CTRL :: SECOND_FRACTION_COUNTER :: reserved0 [31:25] */
-#define BCHP_AON_CTRL_SECOND_FRACTION_COUNTER_reserved0_MASK 0xfe000000
-#define BCHP_AON_CTRL_SECOND_FRACTION_COUNTER_reserved0_SHIFT 25
-
-/* AON_CTRL :: SECOND_FRACTION_COUNTER :: second_fraction_counter_init [24:00] */
-#define BCHP_AON_CTRL_SECOND_FRACTION_COUNTER_second_fraction_counter_init_MASK 0x01ffffff
-#define BCHP_AON_CTRL_SECOND_FRACTION_COUNTER_second_fraction_counter_init_SHIFT 0
-#define BCHP_AON_CTRL_SECOND_FRACTION_COUNTER_second_fraction_counter_init_DEFAULT 0x00000000
-
-/***************************************************************************
- *TIME_COUNTER - Hour/Minute Counter Initial value
- ***************************************************************************/
-/* AON_CTRL :: TIME_COUNTER :: reserved0 [31:20] */
-#define BCHP_AON_CTRL_TIME_COUNTER_reserved0_MASK 0xfff00000
-#define BCHP_AON_CTRL_TIME_COUNTER_reserved0_SHIFT 20
-
-/* AON_CTRL :: TIME_COUNTER :: hour_display_mode [19:19] */
-#define BCHP_AON_CTRL_TIME_COUNTER_hour_display_mode_MASK 0x00080000
-#define BCHP_AON_CTRL_TIME_COUNTER_hour_display_mode_SHIFT 19
-#define BCHP_AON_CTRL_TIME_COUNTER_hour_display_mode_DEFAULT 0x00000000
-
-/* AON_CTRL :: TIME_COUNTER :: mode_12h_24h_init [18:18] */
-#define BCHP_AON_CTRL_TIME_COUNTER_mode_12h_24h_init_MASK 0x00040000
-#define BCHP_AON_CTRL_TIME_COUNTER_mode_12h_24h_init_SHIFT 18
-#define BCHP_AON_CTRL_TIME_COUNTER_mode_12h_24h_init_DEFAULT 0x00000000
-
-/* AON_CTRL :: TIME_COUNTER :: am_pm_counter_init [17:17] */
-#define BCHP_AON_CTRL_TIME_COUNTER_am_pm_counter_init_MASK 0x00020000
-#define BCHP_AON_CTRL_TIME_COUNTER_am_pm_counter_init_SHIFT 17
-#define BCHP_AON_CTRL_TIME_COUNTER_am_pm_counter_init_DEFAULT 0x00000000
-
-/* AON_CTRL :: TIME_COUNTER :: hour_counter_init [16:12] */
-#define BCHP_AON_CTRL_TIME_COUNTER_hour_counter_init_MASK 0x0001f000
-#define BCHP_AON_CTRL_TIME_COUNTER_hour_counter_init_SHIFT 12
-#define BCHP_AON_CTRL_TIME_COUNTER_hour_counter_init_DEFAULT 0x00000000
-
-/* AON_CTRL :: TIME_COUNTER :: minute_counter_init [11:06] */
-#define BCHP_AON_CTRL_TIME_COUNTER_minute_counter_init_MASK 0x00000fc0
-#define BCHP_AON_CTRL_TIME_COUNTER_minute_counter_init_SHIFT 6
-#define BCHP_AON_CTRL_TIME_COUNTER_minute_counter_init_DEFAULT 0x00000000
-
-/* AON_CTRL :: TIME_COUNTER :: second_counter_init [05:00] */
-#define BCHP_AON_CTRL_TIME_COUNTER_second_counter_init_MASK 0x0000003f
-#define BCHP_AON_CTRL_TIME_COUNTER_second_counter_init_SHIFT 0
-#define BCHP_AON_CTRL_TIME_COUNTER_second_counter_init_DEFAULT 0x00000000
-
-/***************************************************************************
- *LED_DIGIT_CODE_0 - Digit Code for digit 0, 1, 2, 3
- ***************************************************************************/
-/* AON_CTRL :: LED_DIGIT_CODE_0 :: digit_code_3 [31:24] */
-#define BCHP_AON_CTRL_LED_DIGIT_CODE_0_digit_code_3_MASK 0xff000000
-#define BCHP_AON_CTRL_LED_DIGIT_CODE_0_digit_code_3_SHIFT 24
-#define BCHP_AON_CTRL_LED_DIGIT_CODE_0_digit_code_3_DEFAULT 0x00000000
-
-/* AON_CTRL :: LED_DIGIT_CODE_0 :: digit_code_2 [23:16] */
-#define BCHP_AON_CTRL_LED_DIGIT_CODE_0_digit_code_2_MASK 0x00ff0000
-#define BCHP_AON_CTRL_LED_DIGIT_CODE_0_digit_code_2_SHIFT 16
-#define BCHP_AON_CTRL_LED_DIGIT_CODE_0_digit_code_2_DEFAULT 0x00000000
-
-/* AON_CTRL :: LED_DIGIT_CODE_0 :: digit_code_1 [15:08] */
-#define BCHP_AON_CTRL_LED_DIGIT_CODE_0_digit_code_1_MASK 0x0000ff00
-#define BCHP_AON_CTRL_LED_DIGIT_CODE_0_digit_code_1_SHIFT 8
-#define BCHP_AON_CTRL_LED_DIGIT_CODE_0_digit_code_1_DEFAULT 0x00000000
-
-/* AON_CTRL :: LED_DIGIT_CODE_0 :: digit_code_0 [07:00] */
-#define BCHP_AON_CTRL_LED_DIGIT_CODE_0_digit_code_0_MASK 0x000000ff
-#define BCHP_AON_CTRL_LED_DIGIT_CODE_0_digit_code_0_SHIFT 0
-#define BCHP_AON_CTRL_LED_DIGIT_CODE_0_digit_code_0_DEFAULT 0x00000000
-
-/***************************************************************************
- *LED_DIGIT_CODE_1 - Digit Code for digit 4, 5, 6, 7
- ***************************************************************************/
-/* AON_CTRL :: LED_DIGIT_CODE_1 :: digit_code_7 [31:24] */
-#define BCHP_AON_CTRL_LED_DIGIT_CODE_1_digit_code_7_MASK 0xff000000
-#define BCHP_AON_CTRL_LED_DIGIT_CODE_1_digit_code_7_SHIFT 24
-#define BCHP_AON_CTRL_LED_DIGIT_CODE_1_digit_code_7_DEFAULT 0x00000000
-
-/* AON_CTRL :: LED_DIGIT_CODE_1 :: digit_code_6 [23:16] */
-#define BCHP_AON_CTRL_LED_DIGIT_CODE_1_digit_code_6_MASK 0x00ff0000
-#define BCHP_AON_CTRL_LED_DIGIT_CODE_1_digit_code_6_SHIFT 16
-#define BCHP_AON_CTRL_LED_DIGIT_CODE_1_digit_code_6_DEFAULT 0x00000000
-
-/* AON_CTRL :: LED_DIGIT_CODE_1 :: digit_code_5 [15:08] */
-#define BCHP_AON_CTRL_LED_DIGIT_CODE_1_digit_code_5_MASK 0x0000ff00
-#define BCHP_AON_CTRL_LED_DIGIT_CODE_1_digit_code_5_SHIFT 8
-#define BCHP_AON_CTRL_LED_DIGIT_CODE_1_digit_code_5_DEFAULT 0x00000000
-
-/* AON_CTRL :: LED_DIGIT_CODE_1 :: digit_code_4 [07:00] */
-#define BCHP_AON_CTRL_LED_DIGIT_CODE_1_digit_code_4_MASK 0x000000ff
-#define BCHP_AON_CTRL_LED_DIGIT_CODE_1_digit_code_4_SHIFT 0
-#define BCHP_AON_CTRL_LED_DIGIT_CODE_1_digit_code_4_DEFAULT 0x00000000
-
-/***************************************************************************
- *LED_DIGIT_CODE_2 - Digit Code for digit 8, 9
- ***************************************************************************/
-/* AON_CTRL :: LED_DIGIT_CODE_2 :: reserved0 [31:16] */
-#define BCHP_AON_CTRL_LED_DIGIT_CODE_2_reserved0_MASK 0xffff0000
-#define BCHP_AON_CTRL_LED_DIGIT_CODE_2_reserved0_SHIFT 16
-
-/* AON_CTRL :: LED_DIGIT_CODE_2 :: digit_code_9 [15:08] */
-#define BCHP_AON_CTRL_LED_DIGIT_CODE_2_digit_code_9_MASK 0x0000ff00
-#define BCHP_AON_CTRL_LED_DIGIT_CODE_2_digit_code_9_SHIFT 8
-#define BCHP_AON_CTRL_LED_DIGIT_CODE_2_digit_code_9_DEFAULT 0x00000000
-
-/* AON_CTRL :: LED_DIGIT_CODE_2 :: digit_code_8 [07:00] */
-#define BCHP_AON_CTRL_LED_DIGIT_CODE_2_digit_code_8_MASK 0x000000ff
-#define BCHP_AON_CTRL_LED_DIGIT_CODE_2_digit_code_8_SHIFT 0
-#define BCHP_AON_CTRL_LED_DIGIT_CODE_2_digit_code_8_DEFAULT 0x00000000
-
-/***************************************************************************
- *LED_DIGIT_ADDR_OFFSET - Hour MSD/LSD and minute MSD/LSD address offset
- ***************************************************************************/
-/* AON_CTRL :: LED_DIGIT_ADDR_OFFSET :: hour_msd_addr_offset [31:24] */
-#define BCHP_AON_CTRL_LED_DIGIT_ADDR_OFFSET_hour_msd_addr_offset_MASK 0xff000000
-#define BCHP_AON_CTRL_LED_DIGIT_ADDR_OFFSET_hour_msd_addr_offset_SHIFT 24
-#define BCHP_AON_CTRL_LED_DIGIT_ADDR_OFFSET_hour_msd_addr_offset_DEFAULT 0x00000020
-
-/* AON_CTRL :: LED_DIGIT_ADDR_OFFSET :: hour_lsd_addr_offset [23:16] */
-#define BCHP_AON_CTRL_LED_DIGIT_ADDR_OFFSET_hour_lsd_addr_offset_MASK 0x00ff0000
-#define BCHP_AON_CTRL_LED_DIGIT_ADDR_OFFSET_hour_lsd_addr_offset_SHIFT 16
-#define BCHP_AON_CTRL_LED_DIGIT_ADDR_OFFSET_hour_lsd_addr_offset_DEFAULT 0x00000024
-
-/* AON_CTRL :: LED_DIGIT_ADDR_OFFSET :: minute_msd_addr_offset [15:08] */
-#define BCHP_AON_CTRL_LED_DIGIT_ADDR_OFFSET_minute_msd_addr_offset_MASK 0x0000ff00
-#define BCHP_AON_CTRL_LED_DIGIT_ADDR_OFFSET_minute_msd_addr_offset_SHIFT 8
-#define BCHP_AON_CTRL_LED_DIGIT_ADDR_OFFSET_minute_msd_addr_offset_DEFAULT 0x00000018
-
-/* AON_CTRL :: LED_DIGIT_ADDR_OFFSET :: minute_lsd_addr_offset [07:00] */
-#define BCHP_AON_CTRL_LED_DIGIT_ADDR_OFFSET_minute_lsd_addr_offset_MASK 0x000000ff
-#define BCHP_AON_CTRL_LED_DIGIT_ADDR_OFFSET_minute_lsd_addr_offset_SHIFT 0
-#define BCHP_AON_CTRL_LED_DIGIT_ADDR_OFFSET_minute_lsd_addr_offset_DEFAULT 0x0000001c
-
-/***************************************************************************
- *LED_STATUS_CTRL - LED status control
- ***************************************************************************/
-/* AON_CTRL :: LED_STATUS_CTRL :: reserved0 [31:28] */
-#define BCHP_AON_CTRL_LED_STATUS_CTRL_reserved0_MASK 0xf0000000
-#define BCHP_AON_CTRL_LED_STATUS_CTRL_reserved0_SHIFT 28
-
-/* AON_CTRL :: LED_STATUS_CTRL :: hlcd_state [27:25] */
-#define BCHP_AON_CTRL_LED_STATUS_CTRL_hlcd_state_MASK 0x0e000000
-#define BCHP_AON_CTRL_LED_STATUS_CTRL_hlcd_state_SHIFT 25
-#define BCHP_AON_CTRL_LED_STATUS_CTRL_hlcd_state_HLCD_IDLE 0
-#define BCHP_AON_CTRL_LED_STATUS_CTRL_hlcd_state_HLCD_COUNT 1
-#define BCHP_AON_CTRL_LED_STATUS_CTRL_hlcd_state_HLCD_PROGRAM_MINUTE_LSD 2
-#define BCHP_AON_CTRL_LED_STATUS_CTRL_hlcd_state_HLCD_PROGRAM_MINUTE_MSD 3
-#define BCHP_AON_CTRL_LED_STATUS_CTRL_hlcd_state_HLCD_PROGRAM_HOUR_LSD 4
-#define BCHP_AON_CTRL_LED_STATUS_CTRL_hlcd_state_HLCD_PROGRAM_HOUR_MSD 5
-#define BCHP_AON_CTRL_LED_STATUS_CTRL_hlcd_state_HLCD_PROGRAM_STATUS 6
-
-/* AON_CTRL :: LED_STATUS_CTRL :: status_update_enable [24:24] */
-#define BCHP_AON_CTRL_LED_STATUS_CTRL_status_update_enable_MASK 0x01000000
-#define BCHP_AON_CTRL_LED_STATUS_CTRL_status_update_enable_SHIFT 24
-#define BCHP_AON_CTRL_LED_STATUS_CTRL_status_update_enable_DEFAULT 0x00000000
-
-/* AON_CTRL :: LED_STATUS_CTRL :: status_mask [23:12] */
-#define BCHP_AON_CTRL_LED_STATUS_CTRL_status_mask_MASK 0x00fff000
-#define BCHP_AON_CTRL_LED_STATUS_CTRL_status_mask_SHIFT 12
-#define BCHP_AON_CTRL_LED_STATUS_CTRL_status_mask_DEFAULT 0x00000000
-
-/* AON_CTRL :: LED_STATUS_CTRL :: status_bit_offset [11:08] */
-#define BCHP_AON_CTRL_LED_STATUS_CTRL_status_bit_offset_MASK 0x00000f00
-#define BCHP_AON_CTRL_LED_STATUS_CTRL_status_bit_offset_SHIFT 8
-#define BCHP_AON_CTRL_LED_STATUS_CTRL_status_bit_offset_DEFAULT 0x00000000
-
-/* AON_CTRL :: LED_STATUS_CTRL :: status_addr_offset [07:00] */
-#define BCHP_AON_CTRL_LED_STATUS_CTRL_status_addr_offset_MASK 0x000000ff
-#define BCHP_AON_CTRL_LED_STATUS_CTRL_status_addr_offset_SHIFT 0
-#define BCHP_AON_CTRL_LED_STATUS_CTRL_status_addr_offset_DEFAULT 0x00000000
-
-/***************************************************************************
- *GENERAL_CTRL_0 - General control register 0
- ***************************************************************************/
-/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_31 [31:31] */
-#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_31_MASK 0x80000000
-#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_31_SHIFT 31
-#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_31_DEFAULT 0x00000001
-
-/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_30 [30:30] */
-#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_30_MASK 0x40000000
-#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_30_SHIFT 30
-#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_30_DEFAULT 0x00000001
-
-/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_29 [29:29] */
-#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_29_MASK 0x20000000
-#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_29_SHIFT 29
-#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_29_DEFAULT 0x00000001
-
-/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_28 [28:28] */
-#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_28_MASK 0x10000000
-#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_28_SHIFT 28
-#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_28_DEFAULT 0x00000001
-
-/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_27 [27:27] */
-#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_27_MASK 0x08000000
-#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_27_SHIFT 27
-#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_27_DEFAULT 0x00000001
-
-/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_26 [26:26] */
-#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_26_MASK 0x04000000
-#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_26_SHIFT 26
-#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_26_DEFAULT 0x00000001
-
-/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_25 [25:25] */
-#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_25_MASK 0x02000000
-#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_25_SHIFT 25
-#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_25_DEFAULT 0x00000001
-
-/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_24 [24:24] */
-#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_24_MASK 0x01000000
-#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_24_SHIFT 24
-#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_24_DEFAULT 0x00000001
-
-/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_23 [23:23] */
-#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_23_MASK 0x00800000
-#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_23_SHIFT 23
-#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_23_DEFAULT 0x00000001
-
-/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_22 [22:22] */
-#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_22_MASK 0x00400000
-#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_22_SHIFT 22
-#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_22_DEFAULT 0x00000001
-
-/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_21 [21:21] */
-#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_21_MASK 0x00200000
-#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_21_SHIFT 21
-#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_21_DEFAULT 0x00000001
-
-/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_20 [20:20] */
-#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_20_MASK 0x00100000
-#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_20_SHIFT 20
-#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_20_DEFAULT 0x00000001
-
-/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_19 [19:19] */
-#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_19_MASK 0x00080000
-#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_19_SHIFT 19
-#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_19_DEFAULT 0x00000001
-
-/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_18 [18:18] */
-#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_18_MASK 0x00040000
-#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_18_SHIFT 18
-#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_18_DEFAULT 0x00000001
-
-/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_17 [17:17] */
-#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_17_MASK 0x00020000
-#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_17_SHIFT 17
-#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_17_DEFAULT 0x00000001
-
-/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_16 [16:16] */
-#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_16_MASK 0x00010000
-#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_16_SHIFT 16
-#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_16_DEFAULT 0x00000001
-
-/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_15 [15:15] */
-#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_15_MASK 0x00008000
-#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_15_SHIFT 15
-#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_15_DEFAULT 0x00000000
-
-/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_14 [14:14] */
-#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_14_MASK 0x00004000
-#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_14_SHIFT 14
-#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_14_DEFAULT 0x00000000
-
-/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_13 [13:13] */
-#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_13_MASK 0x00002000
-#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_13_SHIFT 13
-#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_13_DEFAULT 0x00000000
-
-/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_12 [12:12] */
-#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_12_MASK 0x00001000
-#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_12_SHIFT 12
-#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_12_DEFAULT 0x00000000
-
-/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_11 [11:11] */
-#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_11_MASK 0x00000800
-#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_11_SHIFT 11
-#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_11_DEFAULT 0x00000000
-
-/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_10 [10:10] */
-#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_10_MASK 0x00000400
-#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_10_SHIFT 10
-#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_10_DEFAULT 0x00000000
-
-/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_9 [09:09] */
-#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_9_MASK 0x00000200
-#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_9_SHIFT 9
-#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_9_DEFAULT 0x00000000
-
-/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_8 [08:08] */
-#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_8_MASK 0x00000100
-#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_8_SHIFT 8
-#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_8_DEFAULT 0x00000000
-
-/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_7 [07:07] */
-#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_7_MASK 0x00000080
-#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_7_SHIFT 7
-#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_7_DEFAULT 0x00000000
-
-/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_6 [06:06] */
-#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_6_MASK 0x00000040
-#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_6_SHIFT 6
-#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_6_DEFAULT 0x00000000
-
-/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_5 [05:05] */
-#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_5_MASK 0x00000020
-#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_5_SHIFT 5
-#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_5_DEFAULT 0x00000000
-
-/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_4 [04:04] */
-#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_4_MASK 0x00000010
-#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_4_SHIFT 4
-#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_4_DEFAULT 0x00000000
-
-/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_3 [03:03] */
-#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_3_MASK 0x00000008
-#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_3_SHIFT 3
-#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_3_DEFAULT 0x00000000
-
-/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_2 [02:02] */
-#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_2_MASK 0x00000004
-#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_2_SHIFT 2
-#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_2_DEFAULT 0x00000000
-
-/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_1 [01:01] */
-#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_1_MASK 0x00000002
-#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_1_SHIFT 1
-#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_1_DEFAULT 0x00000000
-
-/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_0 [00:00] */
-#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_0_MASK 0x00000001
-#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_0_SHIFT 0
-#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_0_DEFAULT 0x00000000
-
-/***************************************************************************
- *GENERAL_STATUS_0 - General status register 0
- ***************************************************************************/
-/* AON_CTRL :: GENERAL_STATUS_0 :: reserved0 [31:08] */
-#define BCHP_AON_CTRL_GENERAL_STATUS_0_reserved0_MASK 0xffffff00
-#define BCHP_AON_CTRL_GENERAL_STATUS_0_reserved0_SHIFT 8
-
-/* AON_CTRL :: GENERAL_STATUS_0 :: general_status0_7 [07:07] */
-#define BCHP_AON_CTRL_GENERAL_STATUS_0_general_status0_7_MASK 0x00000080
-#define BCHP_AON_CTRL_GENERAL_STATUS_0_general_status0_7_SHIFT 7
-
-/* AON_CTRL :: GENERAL_STATUS_0 :: general_status0_6 [06:06] */
-#define BCHP_AON_CTRL_GENERAL_STATUS_0_general_status0_6_MASK 0x00000040
-#define BCHP_AON_CTRL_GENERAL_STATUS_0_general_status0_6_SHIFT 6
-
-/* AON_CTRL :: GENERAL_STATUS_0 :: general_status0_5 [05:05] */
-#define BCHP_AON_CTRL_GENERAL_STATUS_0_general_status0_5_MASK 0x00000020
-#define BCHP_AON_CTRL_GENERAL_STATUS_0_general_status0_5_SHIFT 5
-
-/* AON_CTRL :: GENERAL_STATUS_0 :: general_status0_4 [04:04] */
-#define BCHP_AON_CTRL_GENERAL_STATUS_0_general_status0_4_MASK 0x00000010
-#define BCHP_AON_CTRL_GENERAL_STATUS_0_general_status0_4_SHIFT 4
-
-/* AON_CTRL :: GENERAL_STATUS_0 :: general_status0_3 [03:03] */
-#define BCHP_AON_CTRL_GENERAL_STATUS_0_general_status0_3_MASK 0x00000008
-#define BCHP_AON_CTRL_GENERAL_STATUS_0_general_status0_3_SHIFT 3
-
-/* AON_CTRL :: GENERAL_STATUS_0 :: general_status0_2 [02:02] */
-#define BCHP_AON_CTRL_GENERAL_STATUS_0_general_status0_2_MASK 0x00000004
-#define BCHP_AON_CTRL_GENERAL_STATUS_0_general_status0_2_SHIFT 2
-
-/* AON_CTRL :: GENERAL_STATUS_0 :: general_status0_1 [01:01] */
-#define BCHP_AON_CTRL_GENERAL_STATUS_0_general_status0_1_MASK 0x00000002
-#define BCHP_AON_CTRL_GENERAL_STATUS_0_general_status0_1_SHIFT 1
-
-/* AON_CTRL :: GENERAL_STATUS_0 :: ejtag_ce_wakeup_event [00:00] */
-#define BCHP_AON_CTRL_GENERAL_STATUS_0_ejtag_ce_wakeup_event_MASK 0x00000001
-#define BCHP_AON_CTRL_GENERAL_STATUS_0_ejtag_ce_wakeup_event_SHIFT 0
-
-/***************************************************************************
- *GENERAL_CTRL_NO_SCAN_0 - General control register without scan 0
- ***************************************************************************/
-/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_31 [31:31] */
-#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_31_MASK 0x80000000
-#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_31_SHIFT 31
-#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_31_DEFAULT 0x00000001
-
-/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_30 [30:30] */
-#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_30_MASK 0x40000000
-#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_30_SHIFT 30
-#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_30_DEFAULT 0x00000001
-
-/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_29 [29:29] */
-#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_29_MASK 0x20000000
-#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_29_SHIFT 29
-#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_29_DEFAULT 0x00000001
-
-/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_28 [28:28] */
-#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_28_MASK 0x10000000
-#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_28_SHIFT 28
-#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_28_DEFAULT 0x00000001
-
-/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_27 [27:27] */
-#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_27_MASK 0x08000000
-#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_27_SHIFT 27
-#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_27_DEFAULT 0x00000001
-
-/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_26 [26:26] */
-#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_26_MASK 0x04000000
-#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_26_SHIFT 26
-#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_26_DEFAULT 0x00000001
-
-/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_25 [25:25] */
-#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_25_MASK 0x02000000
-#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_25_SHIFT 25
-#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_25_DEFAULT 0x00000001
-
-/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_24 [24:24] */
-#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_24_MASK 0x01000000
-#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_24_SHIFT 24
-#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_24_DEFAULT 0x00000001
-
-/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_23 [23:23] */
-#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_23_MASK 0x00800000
-#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_23_SHIFT 23
-#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_23_DEFAULT 0x00000001
-
-/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_22 [22:22] */
-#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_22_MASK 0x00400000
-#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_22_SHIFT 22
-#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_22_DEFAULT 0x00000001
-
-/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_21 [21:21] */
-#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_21_MASK 0x00200000
-#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_21_SHIFT 21
-#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_21_DEFAULT 0x00000001
-
-/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_20 [20:20] */
-#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_20_MASK 0x00100000
-#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_20_SHIFT 20
-#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_20_DEFAULT 0x00000001
-
-/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_19 [19:19] */
-#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_19_MASK 0x00080000
-#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_19_SHIFT 19
-#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_19_DEFAULT 0x00000001
-
-/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_18 [18:18] */
-#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_18_MASK 0x00040000
-#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_18_SHIFT 18
-#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_18_DEFAULT 0x00000001
-
-/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_17 [17:17] */
-#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_17_MASK 0x00020000
-#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_17_SHIFT 17
-#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_17_DEFAULT 0x00000001
-
-/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_16 [16:16] */
-#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_16_MASK 0x00010000
-#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_16_SHIFT 16
-#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_16_DEFAULT 0x00000001
-
-/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_15 [15:15] */
-#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_15_MASK 0x00008000
-#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_15_SHIFT 15
-#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_15_DEFAULT 0x00000000
-
-/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_14 [14:14] */
-#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_14_MASK 0x00004000
-#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_14_SHIFT 14
-#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_14_DEFAULT 0x00000000
-
-/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_13 [13:13] */
-#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_13_MASK 0x00002000
-#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_13_SHIFT 13
-#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_13_DEFAULT 0x00000000
-
-/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_12 [12:12] */
-#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_12_MASK 0x00001000
-#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_12_SHIFT 12
-#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_12_DEFAULT 0x00000000
-
-/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_11 [11:11] */
-#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_11_MASK 0x00000800
-#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_11_SHIFT 11
-#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_11_DEFAULT 0x00000000
-
-/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_10 [10:10] */
-#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_10_MASK 0x00000400
-#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_10_SHIFT 10
-#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_10_DEFAULT 0x00000000
-
-/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_9 [09:09] */
-#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_9_MASK 0x00000200
-#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_9_SHIFT 9
-#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_9_DEFAULT 0x00000000
-
-/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_8 [08:08] */
-#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_8_MASK 0x00000100
-#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_8_SHIFT 8
-#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_8_DEFAULT 0x00000000
-
-/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_7 [07:07] */
-#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_7_MASK 0x00000080
-#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_7_SHIFT 7
-#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_7_DEFAULT 0x00000000
-
-/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_6 [06:06] */
-#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_6_MASK 0x00000040
-#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_6_SHIFT 6
-#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_6_DEFAULT 0x00000000
-
-/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_5 [05:05] */
-#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_5_MASK 0x00000020
-#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_5_SHIFT 5
-#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_5_DEFAULT 0x00000000
-
-/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_4 [04:04] */
-#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_4_MASK 0x00000010
-#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_4_SHIFT 4
-#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_4_DEFAULT 0x00000000
-
-/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_3 [03:03] */
-#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_3_MASK 0x00000008
-#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_3_SHIFT 3
-#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_3_DEFAULT 0x00000000
-
-/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_2 [02:02] */
-#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_2_MASK 0x00000004
-#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_2_SHIFT 2
-#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_2_DEFAULT 0x00000000
-
-/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_1 [01:01] */
-#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_1_MASK 0x00000002
-#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_1_SHIFT 1
-#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_1_DEFAULT 0x00000000
-
-/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_0 [00:00] */
-#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_0_MASK 0x00000001
-#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_0_SHIFT 0
-#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_0_DEFAULT 0x00000000
-
-/***************************************************************************
- *PM_BATTERY_MODE_DEBUG_STATUS - Battery Mode Debug Status
- ***************************************************************************/
-/* AON_CTRL :: PM_BATTERY_MODE_DEBUG_STATUS :: reserved0 [31:14] */
-#define BCHP_AON_CTRL_PM_BATTERY_MODE_DEBUG_STATUS_reserved0_MASK 0xffffc000
-#define BCHP_AON_CTRL_PM_BATTERY_MODE_DEBUG_STATUS_reserved0_SHIFT 14
-
-/* AON_CTRL :: PM_BATTERY_MODE_DEBUG_STATUS :: pm_battery_failsafe_timer_expired_flag [13:13] */
-#define BCHP_AON_CTRL_PM_BATTERY_MODE_DEBUG_STATUS_pm_battery_failsafe_timer_expired_flag_MASK 0x00002000
-#define BCHP_AON_CTRL_PM_BATTERY_MODE_DEBUG_STATUS_pm_battery_failsafe_timer_expired_flag_SHIFT 13
-
-/* AON_CTRL :: PM_BATTERY_MODE_DEBUG_STATUS :: pm_hardware_battery_mode_transition [12:12] */
-#define BCHP_AON_CTRL_PM_BATTERY_MODE_DEBUG_STATUS_pm_hardware_battery_mode_transition_MASK 0x00001000
-#define BCHP_AON_CTRL_PM_BATTERY_MODE_DEBUG_STATUS_pm_hardware_battery_mode_transition_SHIFT 12
-
-/* AON_CTRL :: PM_BATTERY_MODE_DEBUG_STATUS :: pm_gisb_idle_status [11:11] */
-#define BCHP_AON_CTRL_PM_BATTERY_MODE_DEBUG_STATUS_pm_gisb_idle_status_MASK 0x00000800
-#define BCHP_AON_CTRL_PM_BATTERY_MODE_DEBUG_STATUS_pm_gisb_idle_status_SHIFT 11
-
-/* AON_CTRL :: PM_BATTERY_MODE_DEBUG_STATUS :: pm_avs_ready_for_pwrdn [10:10] */
-#define BCHP_AON_CTRL_PM_BATTERY_MODE_DEBUG_STATUS_pm_avs_ready_for_pwrdn_MASK 0x00000400
-#define BCHP_AON_CTRL_PM_BATTERY_MODE_DEBUG_STATUS_pm_avs_ready_for_pwrdn_SHIFT 10
-
-/* AON_CTRL :: PM_BATTERY_MODE_DEBUG_STATUS :: pm_u2u_deregister [09:09] */
-#define BCHP_AON_CTRL_PM_BATTERY_MODE_DEBUG_STATUS_pm_u2u_deregister_MASK 0x00000200
-#define BCHP_AON_CTRL_PM_BATTERY_MODE_DEBUG_STATUS_pm_u2u_deregister_SHIFT 9
-
-/* AON_CTRL :: PM_BATTERY_MODE_DEBUG_STATUS :: pm_dram_ready_for_pwrdn [08:08] */
-#define BCHP_AON_CTRL_PM_BATTERY_MODE_DEBUG_STATUS_pm_dram_ready_for_pwrdn_MASK 0x00000100
-#define BCHP_AON_CTRL_PM_BATTERY_MODE_DEBUG_STATUS_pm_dram_ready_for_pwrdn_SHIFT 8
-
-/* AON_CTRL :: PM_BATTERY_MODE_DEBUG_STATUS :: pm_bsp_ready_for_pwrdn [07:07] */
-#define BCHP_AON_CTRL_PM_BATTERY_MODE_DEBUG_STATUS_pm_bsp_ready_for_pwrdn_MASK 0x00000080
-#define BCHP_AON_CTRL_PM_BATTERY_MODE_DEBUG_STATUS_pm_bsp_ready_for_pwrdn_SHIFT 7
-
-/* AON_CTRL :: PM_BATTERY_MODE_DEBUG_STATUS :: pm_cpu_ready_for_pwrdn [06:06] */
-#define BCHP_AON_CTRL_PM_BATTERY_MODE_DEBUG_STATUS_pm_cpu_ready_for_pwrdn_MASK 0x00000040
-#define BCHP_AON_CTRL_PM_BATTERY_MODE_DEBUG_STATUS_pm_cpu_ready_for_pwrdn_SHIFT 6
-
-/* AON_CTRL :: PM_BATTERY_MODE_DEBUG_STATUS :: pm_sec_avd_rptd_clk_disable [05:05] */
-#define BCHP_AON_CTRL_PM_BATTERY_MODE_DEBUG_STATUS_pm_sec_avd_rptd_clk_disable_MASK 0x00000020
-#define BCHP_AON_CTRL_PM_BATTERY_MODE_DEBUG_STATUS_pm_sec_avd_rptd_clk_disable_SHIFT 5
-
-/* AON_CTRL :: PM_BATTERY_MODE_DEBUG_STATUS :: pm_state [04:00] */
-#define BCHP_AON_CTRL_PM_BATTERY_MODE_DEBUG_STATUS_pm_state_MASK 0x0000001f
-#define BCHP_AON_CTRL_PM_BATTERY_MODE_DEBUG_STATUS_pm_state_SHIFT 0
-#define BCHP_AON_CTRL_PM_BATTERY_MODE_DEBUG_STATUS_pm_state_PM_ACTIVE 0
-#define BCHP_AON_CTRL_PM_BATTERY_MODE_DEBUG_STATUS_pm_state_PM_PWRDN_RDY 1
-#define BCHP_AON_CTRL_PM_BATTERY_MODE_DEBUG_STATUS_pm_state_PM_DISABLE_AVD_RPTD 2
-#define BCHP_AON_CTRL_PM_BATTERY_MODE_DEBUG_STATUS_pm_state_PM_DISABLE_CPU 3
-#define BCHP_AON_CTRL_PM_BATTERY_MODE_DEBUG_STATUS_pm_state_PM_TRANSITION_TO_STANDBY 4
-#define BCHP_AON_CTRL_PM_BATTERY_MODE_DEBUG_STATUS_pm_state_PM_STANDBY 5
-#define BCHP_AON_CTRL_PM_BATTERY_MODE_DEBUG_STATUS_pm_state_PM_STANDBY_WITH_PLLS_ON 6
-#define BCHP_AON_CTRL_PM_BATTERY_MODE_DEBUG_STATUS_pm_state_PM_HOLD_CPU_POWERED_DOWN 7
-#define BCHP_AON_CTRL_PM_BATTERY_MODE_DEBUG_STATUS_pm_state_PM_POWER_UP_CPU 8
-#define BCHP_AON_CTRL_PM_BATTERY_MODE_DEBUG_STATUS_pm_state_PM_TRANSITION_TO_ACTIVE 9
-#define BCHP_AON_CTRL_PM_BATTERY_MODE_DEBUG_STATUS_pm_state_PM_FAST_PWRDN 10
-#define BCHP_AON_CTRL_PM_BATTERY_MODE_DEBUG_STATUS_pm_state_PM_DEEP_STANDBY_ENTRY_S1 11
-#define BCHP_AON_CTRL_PM_BATTERY_MODE_DEBUG_STATUS_pm_state_PM_DEEP_STANDBY_COLD_ENTRY_S2 12
-#define BCHP_AON_CTRL_PM_BATTERY_MODE_DEBUG_STATUS_pm_state_PM_DEEP_STANDBY_WARM_ENTRY_S2 13
-#define BCHP_AON_CTRL_PM_BATTERY_MODE_DEBUG_STATUS_pm_state_PM_DEEP_STANDBY_ENTRY_S3 14
-#define BCHP_AON_CTRL_PM_BATTERY_MODE_DEBUG_STATUS_pm_state_PM_DEEP_STANDBY 15
-#define BCHP_AON_CTRL_PM_BATTERY_MODE_DEBUG_STATUS_pm_state_PM_DEEP_STANDBY_EXIT_S1 16
-#define BCHP_AON_CTRL_PM_BATTERY_MODE_DEBUG_STATUS_pm_state_PM_DEEP_STANDBY_EXIT_S2 17
-#define BCHP_AON_CTRL_PM_BATTERY_MODE_DEBUG_STATUS_pm_state_PM_BATTERY_STANDBY_ENTRY_S1 18
-#define BCHP_AON_CTRL_PM_BATTERY_MODE_DEBUG_STATUS_pm_state_PM_BATTERY_STANDBY_COLD_ENTRY_S2 19
-#define BCHP_AON_CTRL_PM_BATTERY_MODE_DEBUG_STATUS_pm_state_PM_BATTERY_STANDBY_WARM_ENTRY_S2 20
-#define BCHP_AON_CTRL_PM_BATTERY_MODE_DEBUG_STATUS_pm_state_PM_BATTERY_STANDBY_ENTRY_S3 21
-#define BCHP_AON_CTRL_PM_BATTERY_MODE_DEBUG_STATUS_pm_state_PM_BATTERY_STANDBY 22
-#define BCHP_AON_CTRL_PM_BATTERY_MODE_DEBUG_STATUS_pm_state_PM_BATTERY_STANDBY_EXIT_S1 23
-#define BCHP_AON_CTRL_PM_BATTERY_MODE_DEBUG_STATUS_pm_state_PM_BATTERY_STANDBY_EXIT_S2 24
-
-/***************************************************************************
- *PM_BATTERY_MODE_FAILSAFE_TIMER - Battery Standby Mode Failsafe Timer
- ***************************************************************************/
-/* AON_CTRL :: PM_BATTERY_MODE_FAILSAFE_TIMER :: reserved0 [31:23] */
-#define BCHP_AON_CTRL_PM_BATTERY_MODE_FAILSAFE_TIMER_reserved0_MASK 0xff800000
-#define BCHP_AON_CTRL_PM_BATTERY_MODE_FAILSAFE_TIMER_reserved0_SHIFT 23
-
-/* AON_CTRL :: PM_BATTERY_MODE_FAILSAFE_TIMER :: counter_start_value [22:00] */
-#define BCHP_AON_CTRL_PM_BATTERY_MODE_FAILSAFE_TIMER_counter_start_value_MASK 0x007fffff
-#define BCHP_AON_CTRL_PM_BATTERY_MODE_FAILSAFE_TIMER_counter_start_value_SHIFT 0
-#define BCHP_AON_CTRL_PM_BATTERY_MODE_FAILSAFE_TIMER_counter_start_value_DEFAULT 0x0001a5e0
-
-/***************************************************************************
- *REBOOT_ON_POWERLOSS_TIMER - Reboot on AC Powerloss Timer
- ***************************************************************************/
-/* AON_CTRL :: REBOOT_ON_POWERLOSS_TIMER :: reserved0 [31:27] */
-#define BCHP_AON_CTRL_REBOOT_ON_POWERLOSS_TIMER_reserved0_MASK 0xf8000000
-#define BCHP_AON_CTRL_REBOOT_ON_POWERLOSS_TIMER_reserved0_SHIFT 27
-
-/* AON_CTRL :: REBOOT_ON_POWERLOSS_TIMER :: counter_start_value [26:00] */
-#define BCHP_AON_CTRL_REBOOT_ON_POWERLOSS_TIMER_counter_start_value_MASK 0x07ffffff
-#define BCHP_AON_CTRL_REBOOT_ON_POWERLOSS_TIMER_counter_start_value_SHIFT 0
-#define BCHP_AON_CTRL_REBOOT_ON_POWERLOSS_TIMER_counter_start_value_DEFAULT 0x00000000
-
-/***************************************************************************
- *UNCLEARED_SCRATCH - Scratch register
- ***************************************************************************/
-/* AON_CTRL :: UNCLEARED_SCRATCH :: uncleared_scratch [31:00] */
-#define BCHP_AON_CTRL_UNCLEARED_SCRATCH_uncleared_scratch_MASK 0xffffffff
-#define BCHP_AON_CTRL_UNCLEARED_SCRATCH_uncleared_scratch_SHIFT 0
-#define BCHP_AON_CTRL_UNCLEARED_SCRATCH_uncleared_scratch_DEFAULT 0x00000000
-
-/***************************************************************************
- *RESET_HISTORY - Reset History Register For AON
- ***************************************************************************/
-/* AON_CTRL :: RESET_HISTORY :: aux_chip_level_reset_0 [31:31] */
-#define BCHP_AON_CTRL_RESET_HISTORY_aux_chip_level_reset_0_MASK 0x80000000
-#define BCHP_AON_CTRL_RESET_HISTORY_aux_chip_level_reset_0_SHIFT 31
-#define BCHP_AON_CTRL_RESET_HISTORY_aux_chip_level_reset_0_DEFAULT 0x00000000
-
-/* AON_CTRL :: RESET_HISTORY :: aux_chip_edge_reset_1 [30:30] */
-#define BCHP_AON_CTRL_RESET_HISTORY_aux_chip_edge_reset_1_MASK 0x40000000
-#define BCHP_AON_CTRL_RESET_HISTORY_aux_chip_edge_reset_1_SHIFT 30
-#define BCHP_AON_CTRL_RESET_HISTORY_aux_chip_edge_reset_1_DEFAULT 0x00000000
-
-/* AON_CTRL :: RESET_HISTORY :: aux_chip_edge_reset_0 [29:29] */
-#define BCHP_AON_CTRL_RESET_HISTORY_aux_chip_edge_reset_0_MASK 0x20000000
-#define BCHP_AON_CTRL_RESET_HISTORY_aux_chip_edge_reset_0_SHIFT 29
-#define BCHP_AON_CTRL_RESET_HISTORY_aux_chip_edge_reset_0_DEFAULT 0x00000000
-
-/* AON_CTRL :: RESET_HISTORY :: scpu_ejtag_reset [28:28] */
-#define BCHP_AON_CTRL_RESET_HISTORY_scpu_ejtag_reset_MASK 0x10000000
-#define BCHP_AON_CTRL_RESET_HISTORY_scpu_ejtag_reset_SHIFT 28
-#define BCHP_AON_CTRL_RESET_HISTORY_scpu_ejtag_reset_DEFAULT 0x00000000
-
-/* AON_CTRL :: RESET_HISTORY :: rg_cpu_ejtag_reset [27:27] */
-#define BCHP_AON_CTRL_RESET_HISTORY_rg_cpu_ejtag_reset_MASK 0x08000000
-#define BCHP_AON_CTRL_RESET_HISTORY_rg_cpu_ejtag_reset_SHIFT 27
-#define BCHP_AON_CTRL_RESET_HISTORY_rg_cpu_ejtag_reset_DEFAULT 0x00000000
-
-/* AON_CTRL :: RESET_HISTORY :: cm_cpu_ejtag_reset [26:26] */
-#define BCHP_AON_CTRL_RESET_HISTORY_cm_cpu_ejtag_reset_MASK 0x04000000
-#define BCHP_AON_CTRL_RESET_HISTORY_cm_cpu_ejtag_reset_SHIFT 26
-#define BCHP_AON_CTRL_RESET_HISTORY_cm_cpu_ejtag_reset_DEFAULT 0x00000000
-
-/* AON_CTRL :: RESET_HISTORY :: host_cpu_ejtag_reset [25:25] */
-#define BCHP_AON_CTRL_RESET_HISTORY_host_cpu_ejtag_reset_MASK 0x02000000
-#define BCHP_AON_CTRL_RESET_HISTORY_host_cpu_ejtag_reset_SHIFT 25
-#define BCHP_AON_CTRL_RESET_HISTORY_host_cpu_ejtag_reset_DEFAULT 0x00000000
-
-/* AON_CTRL :: RESET_HISTORY :: powerloss_reset [24:24] */
-#define BCHP_AON_CTRL_RESET_HISTORY_powerloss_reset_MASK 0x01000000
-#define BCHP_AON_CTRL_RESET_HISTORY_powerloss_reset_SHIFT 24
-
-/* AON_CTRL :: RESET_HISTORY :: cm_overvoltage_1_reset [23:23] */
-#define BCHP_AON_CTRL_RESET_HISTORY_cm_overvoltage_1_reset_MASK 0x00800000
-#define BCHP_AON_CTRL_RESET_HISTORY_cm_overvoltage_1_reset_SHIFT 23
-#define BCHP_AON_CTRL_RESET_HISTORY_cm_overvoltage_1_reset_DEFAULT 0x00000000
-
-/* AON_CTRL :: RESET_HISTORY :: cm_undervoltage_1_reset [22:22] */
-#define BCHP_AON_CTRL_RESET_HISTORY_cm_undervoltage_1_reset_MASK 0x00400000
-#define BCHP_AON_CTRL_RESET_HISTORY_cm_undervoltage_1_reset_SHIFT 22
-#define BCHP_AON_CTRL_RESET_HISTORY_cm_undervoltage_1_reset_DEFAULT 0x00000000
-
-/* AON_CTRL :: RESET_HISTORY :: cm_undervoltage_0_reset [21:21] */
-#define BCHP_AON_CTRL_RESET_HISTORY_cm_undervoltage_0_reset_MASK 0x00200000
-#define BCHP_AON_CTRL_RESET_HISTORY_cm_undervoltage_0_reset_SHIFT 21
-#define BCHP_AON_CTRL_RESET_HISTORY_cm_undervoltage_0_reset_DEFAULT 0x00000000
-
-/* AON_CTRL :: RESET_HISTORY :: overvoltage_1_reset [20:20] */
-#define BCHP_AON_CTRL_RESET_HISTORY_overvoltage_1_reset_MASK 0x00100000
-#define BCHP_AON_CTRL_RESET_HISTORY_overvoltage_1_reset_SHIFT 20
-#define BCHP_AON_CTRL_RESET_HISTORY_overvoltage_1_reset_DEFAULT 0x00000000
-
-/* AON_CTRL :: RESET_HISTORY :: undervoltage_1_reset [19:19] */
-#define BCHP_AON_CTRL_RESET_HISTORY_undervoltage_1_reset_MASK 0x00080000
-#define BCHP_AON_CTRL_RESET_HISTORY_undervoltage_1_reset_SHIFT 19
-#define BCHP_AON_CTRL_RESET_HISTORY_undervoltage_1_reset_DEFAULT 0x00000000
-
-/* AON_CTRL :: RESET_HISTORY :: undervoltage_0_reset [18:18] */
-#define BCHP_AON_CTRL_RESET_HISTORY_undervoltage_0_reset_MASK 0x00040000
-#define BCHP_AON_CTRL_RESET_HISTORY_undervoltage_0_reset_SHIFT 18
-#define BCHP_AON_CTRL_RESET_HISTORY_undervoltage_0_reset_DEFAULT 0x00000000
-
-/* AON_CTRL :: RESET_HISTORY :: cm_overtemp_reset [17:17] */
-#define BCHP_AON_CTRL_RESET_HISTORY_cm_overtemp_reset_MASK 0x00020000
-#define BCHP_AON_CTRL_RESET_HISTORY_cm_overtemp_reset_SHIFT 17
-#define BCHP_AON_CTRL_RESET_HISTORY_cm_overtemp_reset_DEFAULT 0x00000000
-
-/* AON_CTRL :: RESET_HISTORY :: overtemp_reset [16:16] */
-#define BCHP_AON_CTRL_RESET_HISTORY_overtemp_reset_MASK 0x00010000
-#define BCHP_AON_CTRL_RESET_HISTORY_overtemp_reset_SHIFT 16
-#define BCHP_AON_CTRL_RESET_HISTORY_overtemp_reset_DEFAULT 0x00000000
-
-/* AON_CTRL :: RESET_HISTORY :: security_master_reset [15:15] */
-#define BCHP_AON_CTRL_RESET_HISTORY_security_master_reset_MASK 0x00008000
-#define BCHP_AON_CTRL_RESET_HISTORY_security_master_reset_SHIFT 15
-#define BCHP_AON_CTRL_RESET_HISTORY_security_master_reset_DEFAULT 0x00000000
-
-/* AON_CTRL :: RESET_HISTORY :: aux_software_master_reset [14:14] */
-#define BCHP_AON_CTRL_RESET_HISTORY_aux_software_master_reset_MASK 0x00004000
-#define BCHP_AON_CTRL_RESET_HISTORY_aux_software_master_reset_SHIFT 14
-
-/* AON_CTRL :: RESET_HISTORY :: local_software_master_reset [13:13] */
-#define BCHP_AON_CTRL_RESET_HISTORY_local_software_master_reset_MASK 0x00002000
-#define BCHP_AON_CTRL_RESET_HISTORY_local_software_master_reset_SHIFT 13
-
-/* AON_CTRL :: RESET_HISTORY :: software_master_reset [12:12] */
-#define BCHP_AON_CTRL_RESET_HISTORY_software_master_reset_MASK 0x00001000
-#define BCHP_AON_CTRL_RESET_HISTORY_software_master_reset_SHIFT 12
-#define BCHP_AON_CTRL_RESET_HISTORY_software_master_reset_DEFAULT 0x00000000
-
-/* AON_CTRL :: RESET_HISTORY :: pcie_1_hot_boot_reset [11:11] */
-#define BCHP_AON_CTRL_RESET_HISTORY_pcie_1_hot_boot_reset_MASK 0x00000800
-#define BCHP_AON_CTRL_RESET_HISTORY_pcie_1_hot_boot_reset_SHIFT 11
-#define BCHP_AON_CTRL_RESET_HISTORY_pcie_1_hot_boot_reset_DEFAULT 0x00000000
-
-/* AON_CTRL :: RESET_HISTORY :: pcie_0_hot_boot_reset [10:10] */
-#define BCHP_AON_CTRL_RESET_HISTORY_pcie_0_hot_boot_reset_MASK 0x00000400
-#define BCHP_AON_CTRL_RESET_HISTORY_pcie_0_hot_boot_reset_SHIFT 10
-#define BCHP_AON_CTRL_RESET_HISTORY_pcie_0_hot_boot_reset_DEFAULT 0x00000000
-
-/* AON_CTRL :: RESET_HISTORY :: rg_watchdog_timer_reset [09:09] */
-#define BCHP_AON_CTRL_RESET_HISTORY_rg_watchdog_timer_reset_MASK 0x00000200
-#define BCHP_AON_CTRL_RESET_HISTORY_rg_watchdog_timer_reset_SHIFT 9
-#define BCHP_AON_CTRL_RESET_HISTORY_rg_watchdog_timer_reset_DEFAULT 0x00000000
-
-/* AON_CTRL :: RESET_HISTORY :: cm_watchdog_timer_reset [08:08] */
-#define BCHP_AON_CTRL_RESET_HISTORY_cm_watchdog_timer_reset_MASK 0x00000100
-#define BCHP_AON_CTRL_RESET_HISTORY_cm_watchdog_timer_reset_SHIFT 8
-#define BCHP_AON_CTRL_RESET_HISTORY_cm_watchdog_timer_reset_DEFAULT 0x00000000
-
-/* AON_CTRL :: RESET_HISTORY :: host_watchdog_timer_reset [07:07] */
-#define BCHP_AON_CTRL_RESET_HISTORY_host_watchdog_timer_reset_MASK 0x00000080
-#define BCHP_AON_CTRL_RESET_HISTORY_host_watchdog_timer_reset_SHIFT 7
-#define BCHP_AON_CTRL_RESET_HISTORY_host_watchdog_timer_reset_DEFAULT 0x00000000
-
-/* AON_CTRL :: RESET_HISTORY :: smartcard_insert_reset [06:06] */
-#define BCHP_AON_CTRL_RESET_HISTORY_smartcard_insert_reset_MASK 0x00000040
-#define BCHP_AON_CTRL_RESET_HISTORY_smartcard_insert_reset_SHIFT 6
-#define BCHP_AON_CTRL_RESET_HISTORY_smartcard_insert_reset_DEFAULT 0x00000000
-
-/* AON_CTRL :: RESET_HISTORY :: cm_s3_wakeup_reset [05:05] */
-#define BCHP_AON_CTRL_RESET_HISTORY_cm_s3_wakeup_reset_MASK 0x00000020
-#define BCHP_AON_CTRL_RESET_HISTORY_cm_s3_wakeup_reset_SHIFT 5
-#define BCHP_AON_CTRL_RESET_HISTORY_cm_s3_wakeup_reset_DEFAULT 0x00000000
-
-/* AON_CTRL :: RESET_HISTORY :: s3_wakeup_reset [04:04] */
-#define BCHP_AON_CTRL_RESET_HISTORY_s3_wakeup_reset_MASK 0x00000010
-#define BCHP_AON_CTRL_RESET_HISTORY_s3_wakeup_reset_SHIFT 4
-#define BCHP_AON_CTRL_RESET_HISTORY_s3_wakeup_reset_DEFAULT 0x00000000
-
-/* AON_CTRL :: RESET_HISTORY :: front_panel_4sec_reset [03:03] */
-#define BCHP_AON_CTRL_RESET_HISTORY_front_panel_4sec_reset_MASK 0x00000008
-#define BCHP_AON_CTRL_RESET_HISTORY_front_panel_4sec_reset_SHIFT 3
-#define BCHP_AON_CTRL_RESET_HISTORY_front_panel_4sec_reset_DEFAULT 0x00000000
-
-/* AON_CTRL :: RESET_HISTORY :: tap_in_system_reset [02:02] */
-#define BCHP_AON_CTRL_RESET_HISTORY_tap_in_system_reset_MASK 0x00000004
-#define BCHP_AON_CTRL_RESET_HISTORY_tap_in_system_reset_SHIFT 2
-#define BCHP_AON_CTRL_RESET_HISTORY_tap_in_system_reset_DEFAULT 0x00000000
-
-/* AON_CTRL :: RESET_HISTORY :: main_chip_reset_input [01:01] */
-#define BCHP_AON_CTRL_RESET_HISTORY_main_chip_reset_input_MASK 0x00000002
-#define BCHP_AON_CTRL_RESET_HISTORY_main_chip_reset_input_SHIFT 1
-#define BCHP_AON_CTRL_RESET_HISTORY_main_chip_reset_input_DEFAULT 0x00000000
-
-/* AON_CTRL :: RESET_HISTORY :: power_on_reset [00:00] */
-#define BCHP_AON_CTRL_RESET_HISTORY_power_on_reset_MASK 0x00000001
-#define BCHP_AON_CTRL_RESET_HISTORY_power_on_reset_SHIFT 0
-#define BCHP_AON_CTRL_RESET_HISTORY_power_on_reset_DEFAULT 0x00000001
-
-/***************************************************************************
- *NMI_CTRL - Control register for NMI
- ***************************************************************************/
-/* AON_CTRL :: NMI_CTRL :: nmi_config_lock [31:31] */
-#define BCHP_AON_CTRL_NMI_CTRL_nmi_config_lock_MASK 0x80000000
-#define BCHP_AON_CTRL_NMI_CTRL_nmi_config_lock_SHIFT 31
-#define BCHP_AON_CTRL_NMI_CTRL_nmi_config_lock_DEFAULT 0x00000000
-
-/* AON_CTRL :: NMI_CTRL :: reserved0 [30:03] */
-#define BCHP_AON_CTRL_NMI_CTRL_reserved0_MASK 0x7ffffff8
-#define BCHP_AON_CTRL_NMI_CTRL_reserved0_SHIFT 3
-
-/* AON_CTRL :: NMI_CTRL :: nmi_pad_monitor [02:02] */
-#define BCHP_AON_CTRL_NMI_CTRL_nmi_pad_monitor_MASK 0x00000004
-#define BCHP_AON_CTRL_NMI_CTRL_nmi_pad_monitor_SHIFT 2
-
-/* AON_CTRL :: NMI_CTRL :: config_nmi_polarity [01:01] */
-#define BCHP_AON_CTRL_NMI_CTRL_config_nmi_polarity_MASK 0x00000002
-#define BCHP_AON_CTRL_NMI_CTRL_config_nmi_polarity_SHIFT 1
-#define BCHP_AON_CTRL_NMI_CTRL_config_nmi_polarity_DEFAULT 0x00000000
-
-/* AON_CTRL :: NMI_CTRL :: disable_pad_nmi [00:00] */
-#define BCHP_AON_CTRL_NMI_CTRL_disable_pad_nmi_MASK 0x00000001
-#define BCHP_AON_CTRL_NMI_CTRL_disable_pad_nmi_SHIFT 0
-#define BCHP_AON_CTRL_NMI_CTRL_disable_pad_nmi_DEFAULT 0x00000001
-
-/***************************************************************************
- *ANA_XTAL_CONTROL - Ana xtal gisb control
- ***************************************************************************/
-/* AON_CTRL :: ANA_XTAL_CONTROL :: reserved0 [31:08] */
-#define BCHP_AON_CTRL_ANA_XTAL_CONTROL_reserved0_MASK 0xffffff00
-#define BCHP_AON_CTRL_ANA_XTAL_CONTROL_reserved0_SHIFT 8
-
-/* AON_CTRL :: ANA_XTAL_CONTROL :: osc_select_current_gisb_control [07:07] */
-#define BCHP_AON_CTRL_ANA_XTAL_CONTROL_osc_select_current_gisb_control_MASK 0x00000080
-#define BCHP_AON_CTRL_ANA_XTAL_CONTROL_osc_select_current_gisb_control_SHIFT 7
-#define BCHP_AON_CTRL_ANA_XTAL_CONTROL_osc_select_current_gisb_control_DEFAULT 0x00000000
-
-/* AON_CTRL :: ANA_XTAL_CONTROL :: osc_cml_sel_pd [06:03] */
-#define BCHP_AON_CTRL_ANA_XTAL_CONTROL_osc_cml_sel_pd_MASK 0x00000078
-#define BCHP_AON_CTRL_ANA_XTAL_CONTROL_osc_cml_sel_pd_SHIFT 3
-#define BCHP_AON_CTRL_ANA_XTAL_CONTROL_osc_cml_sel_pd_DEFAULT 0x00000000
-
-/* AON_CTRL :: ANA_XTAL_CONTROL :: osc_d2cbias_gisb_control [02:00] */
-#define BCHP_AON_CTRL_ANA_XTAL_CONTROL_osc_d2cbias_gisb_control_MASK 0x00000007
-#define BCHP_AON_CTRL_ANA_XTAL_CONTROL_osc_d2cbias_gisb_control_SHIFT 0
-#define BCHP_AON_CTRL_ANA_XTAL_CONTROL_osc_d2cbias_gisb_control_DEFAULT 0x00000004
-
-/***************************************************************************
- *SUB_TEST_MODE_CTRL - Test_mode control register
- ***************************************************************************/
-/* AON_CTRL :: SUB_TEST_MODE_CTRL :: reserved0 [31:01] */
-#define BCHP_AON_CTRL_SUB_TEST_MODE_CTRL_reserved0_MASK 0xfffffffe
-#define BCHP_AON_CTRL_SUB_TEST_MODE_CTRL_reserved0_SHIFT 1
-
-/* AON_CTRL :: SUB_TEST_MODE_CTRL :: use_sub_test_mode_reg_src [00:00] */
-#define BCHP_AON_CTRL_SUB_TEST_MODE_CTRL_use_sub_test_mode_reg_src_MASK 0x00000001
-#define BCHP_AON_CTRL_SUB_TEST_MODE_CTRL_use_sub_test_mode_reg_src_SHIFT 0
-#define BCHP_AON_CTRL_SUB_TEST_MODE_CTRL_use_sub_test_mode_reg_src_DEFAULT 0x00000000
-
-/***************************************************************************
- *SUB_TEST_MODE - Register source for sub_test_mode
- ***************************************************************************/
-/* AON_CTRL :: SUB_TEST_MODE :: reserved0 [31:08] */
-#define BCHP_AON_CTRL_SUB_TEST_MODE_reserved0_MASK 0xffffff00
-#define BCHP_AON_CTRL_SUB_TEST_MODE_reserved0_SHIFT 8
-
-/* AON_CTRL :: SUB_TEST_MODE :: sub_test_mode_spare_1 [07:07] */
-#define BCHP_AON_CTRL_SUB_TEST_MODE_sub_test_mode_spare_1_MASK 0x00000080
-#define BCHP_AON_CTRL_SUB_TEST_MODE_sub_test_mode_spare_1_SHIFT 7
-#define BCHP_AON_CTRL_SUB_TEST_MODE_sub_test_mode_spare_1_DEFAULT 0x00000000
-
-/* AON_CTRL :: SUB_TEST_MODE :: sub_test_mode_spare_0 [06:06] */
-#define BCHP_AON_CTRL_SUB_TEST_MODE_sub_test_mode_spare_0_MASK 0x00000040
-#define BCHP_AON_CTRL_SUB_TEST_MODE_sub_test_mode_spare_0_SHIFT 6
-#define BCHP_AON_CTRL_SUB_TEST_MODE_sub_test_mode_spare_0_DEFAULT 0x00000000
-
-/* AON_CTRL :: SUB_TEST_MODE :: sub_test_mode_fast_tspi [05:05] */
-#define BCHP_AON_CTRL_SUB_TEST_MODE_sub_test_mode_fast_tspi_MASK 0x00000020
-#define BCHP_AON_CTRL_SUB_TEST_MODE_sub_test_mode_fast_tspi_SHIFT 5
-#define BCHP_AON_CTRL_SUB_TEST_MODE_sub_test_mode_fast_tspi_DEFAULT 0x00000000
-
-/* AON_CTRL :: SUB_TEST_MODE :: sub_test_mode_hold_cpu_in_reset [04:04] */
-#define BCHP_AON_CTRL_SUB_TEST_MODE_sub_test_mode_hold_cpu_in_reset_MASK 0x00000010
-#define BCHP_AON_CTRL_SUB_TEST_MODE_sub_test_mode_hold_cpu_in_reset_SHIFT 4
-#define BCHP_AON_CTRL_SUB_TEST_MODE_sub_test_mode_hold_cpu_in_reset_DEFAULT 0x00000000
-
-/* AON_CTRL :: SUB_TEST_MODE :: sub_test_mode_spi_slave_enable [03:03] */
-#define BCHP_AON_CTRL_SUB_TEST_MODE_sub_test_mode_spi_slave_enable_MASK 0x00000008
-#define BCHP_AON_CTRL_SUB_TEST_MODE_sub_test_mode_spi_slave_enable_SHIFT 3
-#define BCHP_AON_CTRL_SUB_TEST_MODE_sub_test_mode_spi_slave_enable_DEFAULT 0x00000000
-
-/* AON_CTRL :: SUB_TEST_MODE :: sub_test_mode_extend_reset [02:02] */
-#define BCHP_AON_CTRL_SUB_TEST_MODE_sub_test_mode_extend_reset_MASK 0x00000004
-#define BCHP_AON_CTRL_SUB_TEST_MODE_sub_test_mode_extend_reset_SHIFT 2
-#define BCHP_AON_CTRL_SUB_TEST_MODE_sub_test_mode_extend_reset_DEFAULT 0x00000000
-
-/* AON_CTRL :: SUB_TEST_MODE :: sub_test_mode_bsp_debug [01:00] */
-#define BCHP_AON_CTRL_SUB_TEST_MODE_sub_test_mode_bsp_debug_MASK 0x00000003
-#define BCHP_AON_CTRL_SUB_TEST_MODE_sub_test_mode_bsp_debug_SHIFT 0
-#define BCHP_AON_CTRL_SUB_TEST_MODE_sub_test_mode_bsp_debug_DEFAULT 0x00000000
-
-/***************************************************************************
- *LATCHED_TEST_MODE - Final latched testmode value
- ***************************************************************************/
-/* AON_CTRL :: LATCHED_TEST_MODE :: latched_test_mode [31:00] */
-#define BCHP_AON_CTRL_LATCHED_TEST_MODE_latched_test_mode_MASK 0xffffffff
-#define BCHP_AON_CTRL_LATCHED_TEST_MODE_latched_test_mode_SHIFT 0
-
-/***************************************************************************
- *LATCHED_SUB_TEST_MODE - Final latched sub-testmode value
- ***************************************************************************/
-/* AON_CTRL :: LATCHED_SUB_TEST_MODE :: latched_sub_test_mode [31:00] */
-#define BCHP_AON_CTRL_LATCHED_SUB_TEST_MODE_latched_sub_test_mode_MASK 0xffffffff
-#define BCHP_AON_CTRL_LATCHED_SUB_TEST_MODE_latched_sub_test_mode_SHIFT 0
-
-/***************************************************************************
- *PM_INITIATE - Power down initiate
- ***************************************************************************/
-/* AON_CTRL :: PM_INITIATE :: reserved0 [31:08] */
-#define BCHP_AON_CTRL_PM_INITIATE_reserved0_MASK 0xffffff00
-#define BCHP_AON_CTRL_PM_INITIATE_reserved0_SHIFT 8
-
-/* AON_CTRL :: PM_INITIATE :: pm_initiate_7 [07:07] */
-#define BCHP_AON_CTRL_PM_INITIATE_pm_initiate_7_MASK 0x00000080
-#define BCHP_AON_CTRL_PM_INITIATE_pm_initiate_7_SHIFT 7
-#define BCHP_AON_CTRL_PM_INITIATE_pm_initiate_7_DEFAULT 0x00000000
-
-/* AON_CTRL :: PM_INITIATE :: pm_initiate_6 [06:06] */
-#define BCHP_AON_CTRL_PM_INITIATE_pm_initiate_6_MASK 0x00000040
-#define BCHP_AON_CTRL_PM_INITIATE_pm_initiate_6_SHIFT 6
-#define BCHP_AON_CTRL_PM_INITIATE_pm_initiate_6_DEFAULT 0x00000000
-
-/* AON_CTRL :: PM_INITIATE :: pm_initiate_5 [05:05] */
-#define BCHP_AON_CTRL_PM_INITIATE_pm_initiate_5_MASK 0x00000020
-#define BCHP_AON_CTRL_PM_INITIATE_pm_initiate_5_SHIFT 5
-#define BCHP_AON_CTRL_PM_INITIATE_pm_initiate_5_DEFAULT 0x00000000
-
-/* AON_CTRL :: PM_INITIATE :: pm_initiate_4 [04:04] */
-#define BCHP_AON_CTRL_PM_INITIATE_pm_initiate_4_MASK 0x00000010
-#define BCHP_AON_CTRL_PM_INITIATE_pm_initiate_4_SHIFT 4
-#define BCHP_AON_CTRL_PM_INITIATE_pm_initiate_4_DEFAULT 0x00000000
-
-/* AON_CTRL :: PM_INITIATE :: pm_initiate_3 [03:03] */
-#define BCHP_AON_CTRL_PM_INITIATE_pm_initiate_3_MASK 0x00000008
-#define BCHP_AON_CTRL_PM_INITIATE_pm_initiate_3_SHIFT 3
-#define BCHP_AON_CTRL_PM_INITIATE_pm_initiate_3_DEFAULT 0x00000000
-
-/* AON_CTRL :: PM_INITIATE :: pm_initiate_2 [02:02] */
-#define BCHP_AON_CTRL_PM_INITIATE_pm_initiate_2_MASK 0x00000004
-#define BCHP_AON_CTRL_PM_INITIATE_pm_initiate_2_SHIFT 2
-#define BCHP_AON_CTRL_PM_INITIATE_pm_initiate_2_DEFAULT 0x00000000
-
-/* AON_CTRL :: PM_INITIATE :: pm_initiate_1 [01:01] */
-#define BCHP_AON_CTRL_PM_INITIATE_pm_initiate_1_MASK 0x00000002
-#define BCHP_AON_CTRL_PM_INITIATE_pm_initiate_1_SHIFT 1
-#define BCHP_AON_CTRL_PM_INITIATE_pm_initiate_1_DEFAULT 0x00000000
-
-/* AON_CTRL :: PM_INITIATE :: pm_initiate_0 [00:00] */
-#define BCHP_AON_CTRL_PM_INITIATE_pm_initiate_0_MASK 0x00000001
-#define BCHP_AON_CTRL_PM_INITIATE_pm_initiate_0_SHIFT 0
-#define BCHP_AON_CTRL_PM_INITIATE_pm_initiate_0_DEFAULT 0x00000000
-
-/***************************************************************************
- *HOST_MISC_CMDS - Power up restore
- ***************************************************************************/
-/* AON_CTRL :: HOST_MISC_CMDS :: reserved0 [31:08] */
-#define BCHP_AON_CTRL_HOST_MISC_CMDS_reserved0_MASK 0xffffff00
-#define BCHP_AON_CTRL_HOST_MISC_CMDS_reserved0_SHIFT 8
-
-/* AON_CTRL :: HOST_MISC_CMDS :: host_misc_cmds_7 [07:07] */
-#define BCHP_AON_CTRL_HOST_MISC_CMDS_host_misc_cmds_7_MASK 0x00000080
-#define BCHP_AON_CTRL_HOST_MISC_CMDS_host_misc_cmds_7_SHIFT 7
-#define BCHP_AON_CTRL_HOST_MISC_CMDS_host_misc_cmds_7_DEFAULT 0x00000000
-
-/* AON_CTRL :: HOST_MISC_CMDS :: host_misc_cmds_6 [06:06] */
-#define BCHP_AON_CTRL_HOST_MISC_CMDS_host_misc_cmds_6_MASK 0x00000040
-#define BCHP_AON_CTRL_HOST_MISC_CMDS_host_misc_cmds_6_SHIFT 6
-#define BCHP_AON_CTRL_HOST_MISC_CMDS_host_misc_cmds_6_DEFAULT 0x00000000
-
-/* AON_CTRL :: HOST_MISC_CMDS :: host_misc_cmds_5 [05:05] */
-#define BCHP_AON_CTRL_HOST_MISC_CMDS_host_misc_cmds_5_MASK 0x00000020
-#define BCHP_AON_CTRL_HOST_MISC_CMDS_host_misc_cmds_5_SHIFT 5
-#define BCHP_AON_CTRL_HOST_MISC_CMDS_host_misc_cmds_5_DEFAULT 0x00000000
-
-/* AON_CTRL :: HOST_MISC_CMDS :: host_misc_cmds_4 [04:04] */
-#define BCHP_AON_CTRL_HOST_MISC_CMDS_host_misc_cmds_4_MASK 0x00000010
-#define BCHP_AON_CTRL_HOST_MISC_CMDS_host_misc_cmds_4_SHIFT 4
-#define BCHP_AON_CTRL_HOST_MISC_CMDS_host_misc_cmds_4_DEFAULT 0x00000000
-
-/* AON_CTRL :: HOST_MISC_CMDS :: host_misc_cmds_3 [03:03] */
-#define BCHP_AON_CTRL_HOST_MISC_CMDS_host_misc_cmds_3_MASK 0x00000008
-#define BCHP_AON_CTRL_HOST_MISC_CMDS_host_misc_cmds_3_SHIFT 3
-#define BCHP_AON_CTRL_HOST_MISC_CMDS_host_misc_cmds_3_DEFAULT 0x00000000
-
-/* AON_CTRL :: HOST_MISC_CMDS :: host_misc_cmds_2 [02:02] */
-#define BCHP_AON_CTRL_HOST_MISC_CMDS_host_misc_cmds_2_MASK 0x00000004
-#define BCHP_AON_CTRL_HOST_MISC_CMDS_host_misc_cmds_2_SHIFT 2
-#define BCHP_AON_CTRL_HOST_MISC_CMDS_host_misc_cmds_2_DEFAULT 0x00000000
-
-/* AON_CTRL :: HOST_MISC_CMDS :: dram_scram_key_reuse_req [01:01] */
-#define BCHP_AON_CTRL_HOST_MISC_CMDS_dram_scram_key_reuse_req_MASK 0x00000002
-#define BCHP_AON_CTRL_HOST_MISC_CMDS_dram_scram_key_reuse_req_SHIFT 1
-#define BCHP_AON_CTRL_HOST_MISC_CMDS_dram_scram_key_reuse_req_DEFAULT 0x00000000
-
-/* AON_CTRL :: HOST_MISC_CMDS :: pm_restore [00:00] */
-#define BCHP_AON_CTRL_HOST_MISC_CMDS_pm_restore_MASK 0x00000001
-#define BCHP_AON_CTRL_HOST_MISC_CMDS_pm_restore_SHIFT 0
-#define BCHP_AON_CTRL_HOST_MISC_CMDS_pm_restore_DEFAULT 0x00000000
-
-/***************************************************************************
- *ANA_XTAL_EXT_CML_CONTROL - Ana xtal external CML control
- ***************************************************************************/
-/* AON_CTRL :: ANA_XTAL_EXT_CML_CONTROL :: reserved0 [31:06] */
-#define BCHP_AON_CTRL_ANA_XTAL_EXT_CML_CONTROL_reserved0_MASK 0xffffffc0
-#define BCHP_AON_CTRL_ANA_XTAL_EXT_CML_CONTROL_reserved0_SHIFT 6
-
-/* AON_CTRL :: ANA_XTAL_EXT_CML_CONTROL :: osc_PMSM_S3_pd_buffer [05:05] */
-#define BCHP_AON_CTRL_ANA_XTAL_EXT_CML_CONTROL_osc_PMSM_S3_pd_buffer_MASK 0x00000020
-#define BCHP_AON_CTRL_ANA_XTAL_EXT_CML_CONTROL_osc_PMSM_S3_pd_buffer_SHIFT 5
-#define BCHP_AON_CTRL_ANA_XTAL_EXT_CML_CONTROL_osc_PMSM_S3_pd_buffer_DEFAULT 0x00000000
-
-/* AON_CTRL :: ANA_XTAL_EXT_CML_CONTROL :: osc_override_strap [04:04] */
-#define BCHP_AON_CTRL_ANA_XTAL_EXT_CML_CONTROL_osc_override_strap_MASK 0x00000010
-#define BCHP_AON_CTRL_ANA_XTAL_EXT_CML_CONTROL_osc_override_strap_SHIFT 4
-#define BCHP_AON_CTRL_ANA_XTAL_EXT_CML_CONTROL_osc_override_strap_DEFAULT 0x00000000
-
-/* AON_CTRL :: ANA_XTAL_EXT_CML_CONTROL :: osc_pd_buffer [03:03] */
-#define BCHP_AON_CTRL_ANA_XTAL_EXT_CML_CONTROL_osc_pd_buffer_MASK 0x00000008
-#define BCHP_AON_CTRL_ANA_XTAL_EXT_CML_CONTROL_osc_pd_buffer_SHIFT 3
-#define BCHP_AON_CTRL_ANA_XTAL_EXT_CML_CONTROL_osc_pd_buffer_DEFAULT 0x00000000
-
-/* AON_CTRL :: ANA_XTAL_EXT_CML_CONTROL :: osc_div2_sel [02:02] */
-#define BCHP_AON_CTRL_ANA_XTAL_EXT_CML_CONTROL_osc_div2_sel_MASK 0x00000004
-#define BCHP_AON_CTRL_ANA_XTAL_EXT_CML_CONTROL_osc_div2_sel_SHIFT 2
-#define BCHP_AON_CTRL_ANA_XTAL_EXT_CML_CONTROL_osc_div2_sel_DEFAULT 0x00000001
-
-/* AON_CTRL :: ANA_XTAL_EXT_CML_CONTROL :: osc_current [01:00] */
-#define BCHP_AON_CTRL_ANA_XTAL_EXT_CML_CONTROL_osc_current_MASK 0x00000003
-#define BCHP_AON_CTRL_ANA_XTAL_EXT_CML_CONTROL_osc_current_SHIFT 0
-#define BCHP_AON_CTRL_ANA_XTAL_EXT_CML_CONTROL_osc_current_DEFAULT 0x00000001
-
-/***************************************************************************
- *SPARE_CTRL_0 - Spare control bits reserved for future use
- ***************************************************************************/
-/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_31 [31:31] */
-#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_31_MASK 0x80000000
-#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_31_SHIFT 31
-#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_31_DEFAULT 0x00000001
-
-/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_30 [30:30] */
-#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_30_MASK 0x40000000
-#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_30_SHIFT 30
-#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_30_DEFAULT 0x00000001
-
-/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_29 [29:29] */
-#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_29_MASK 0x20000000
-#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_29_SHIFT 29
-#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_29_DEFAULT 0x00000001
-
-/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_28 [28:28] */
-#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_28_MASK 0x10000000
-#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_28_SHIFT 28
-#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_28_DEFAULT 0x00000001
-
-/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_27 [27:27] */
-#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_27_MASK 0x08000000
-#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_27_SHIFT 27
-#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_27_DEFAULT 0x00000001
-
-/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_26 [26:26] */
-#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_26_MASK 0x04000000
-#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_26_SHIFT 26
-#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_26_DEFAULT 0x00000001
-
-/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_25 [25:25] */
-#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_25_MASK 0x02000000
-#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_25_SHIFT 25
-#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_25_DEFAULT 0x00000001
-
-/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_24 [24:24] */
-#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_24_MASK 0x01000000
-#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_24_SHIFT 24
-#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_24_DEFAULT 0x00000001
-
-/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_23 [23:23] */
-#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_23_MASK 0x00800000
-#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_23_SHIFT 23
-#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_23_DEFAULT 0x00000000
-
-/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_22 [22:22] */
-#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_22_MASK 0x00400000
-#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_22_SHIFT 22
-#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_22_DEFAULT 0x00000000
-
-/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_21 [21:21] */
-#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_21_MASK 0x00200000
-#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_21_SHIFT 21
-#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_21_DEFAULT 0x00000000
-
-/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_20 [20:20] */
-#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_20_MASK 0x00100000
-#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_20_SHIFT 20
-#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_20_DEFAULT 0x00000000
-
-/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_19 [19:19] */
-#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_19_MASK 0x00080000
-#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_19_SHIFT 19
-#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_19_DEFAULT 0x00000000
-
-/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_18 [18:18] */
-#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_18_MASK 0x00040000
-#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_18_SHIFT 18
-#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_18_DEFAULT 0x00000000
-
-/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_17 [17:17] */
-#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_17_MASK 0x00020000
-#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_17_SHIFT 17
-#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_17_DEFAULT 0x00000000
-
-/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_16 [16:16] */
-#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_16_MASK 0x00010000
-#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_16_SHIFT 16
-#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_16_DEFAULT 0x00000000
-
-/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_15 [15:15] */
-#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_15_MASK 0x00008000
-#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_15_SHIFT 15
-#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_15_DEFAULT 0x00000000
-
-/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_14 [14:14] */
-#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_14_MASK 0x00004000
-#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_14_SHIFT 14
-#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_14_DEFAULT 0x00000000
-
-/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_13 [13:13] */
-#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_13_MASK 0x00002000
-#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_13_SHIFT 13
-#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_13_DEFAULT 0x00000000
-
-/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_12 [12:12] */
-#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_12_MASK 0x00001000
-#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_12_SHIFT 12
-#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_12_DEFAULT 0x00000000
-
-/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_11 [11:11] */
-#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_11_MASK 0x00000800
-#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_11_SHIFT 11
-#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_11_DEFAULT 0x00000000
-
-/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_10 [10:10] */
-#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_10_MASK 0x00000400
-#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_10_SHIFT 10
-#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_10_DEFAULT 0x00000000
-
-/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_09 [09:09] */
-#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_09_MASK 0x00000200
-#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_09_SHIFT 9
-#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_09_DEFAULT 0x00000000
-
-/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_08 [08:08] */
-#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_08_MASK 0x00000100
-#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_08_SHIFT 8
-#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_08_DEFAULT 0x00000000
-
-/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_07 [07:07] */
-#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_07_MASK 0x00000080
-#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_07_SHIFT 7
-#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_07_DEFAULT 0x00000000
-
-/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_06 [06:06] */
-#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_06_MASK 0x00000040
-#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_06_SHIFT 6
-#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_06_DEFAULT 0x00000000
-
-/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_05 [05:05] */
-#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_05_MASK 0x00000020
-#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_05_SHIFT 5
-#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_05_DEFAULT 0x00000000
-
-/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_04 [04:04] */
-#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_04_MASK 0x00000010
-#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_04_SHIFT 4
-#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_04_DEFAULT 0x00000000
-
-/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_03 [03:03] */
-#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_03_MASK 0x00000008
-#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_03_SHIFT 3
-#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_03_DEFAULT 0x00000000
-
-/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_02 [02:02] */
-#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_02_MASK 0x00000004
-#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_02_SHIFT 2
-#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_02_DEFAULT 0x00000000
-
-/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_01 [01:01] */
-#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_01_MASK 0x00000002
-#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_01_SHIFT 1
-#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_01_DEFAULT 0x00000000
-
-/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_00 [00:00] */
-#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_00_MASK 0x00000001
-#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_00_SHIFT 0
-#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_00_DEFAULT 0x00000000
-
-/***************************************************************************
- *SPARE_CTRL_1 - Spare control bits reserved for future use
- ***************************************************************************/
-/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_31 [31:31] */
-#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_31_MASK 0x80000000
-#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_31_SHIFT 31
-#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_31_DEFAULT 0x00000001
-
-/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_30 [30:30] */
-#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_30_MASK 0x40000000
-#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_30_SHIFT 30
-#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_30_DEFAULT 0x00000001
-
-/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_29 [29:29] */
-#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_29_MASK 0x20000000
-#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_29_SHIFT 29
-#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_29_DEFAULT 0x00000001
-
-/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_28 [28:28] */
-#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_28_MASK 0x10000000
-#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_28_SHIFT 28
-#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_28_DEFAULT 0x00000001
-
-/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_27 [27:27] */
-#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_27_MASK 0x08000000
-#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_27_SHIFT 27
-#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_27_DEFAULT 0x00000001
-
-/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_26 [26:26] */
-#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_26_MASK 0x04000000
-#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_26_SHIFT 26
-#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_26_DEFAULT 0x00000001
-
-/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_25 [25:25] */
-#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_25_MASK 0x02000000
-#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_25_SHIFT 25
-#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_25_DEFAULT 0x00000001
-
-/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_24 [24:24] */
-#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_24_MASK 0x01000000
-#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_24_SHIFT 24
-#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_24_DEFAULT 0x00000001
-
-/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_23 [23:23] */
-#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_23_MASK 0x00800000
-#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_23_SHIFT 23
-#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_23_DEFAULT 0x00000000
-
-/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_22 [22:22] */
-#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_22_MASK 0x00400000
-#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_22_SHIFT 22
-#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_22_DEFAULT 0x00000000
-
-/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_21 [21:21] */
-#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_21_MASK 0x00200000
-#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_21_SHIFT 21
-#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_21_DEFAULT 0x00000000
-
-/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_20 [20:20] */
-#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_20_MASK 0x00100000
-#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_20_SHIFT 20
-#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_20_DEFAULT 0x00000000
-
-/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_19 [19:19] */
-#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_19_MASK 0x00080000
-#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_19_SHIFT 19
-#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_19_DEFAULT 0x00000000
-
-/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_18 [18:18] */
-#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_18_MASK 0x00040000
-#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_18_SHIFT 18
-#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_18_DEFAULT 0x00000000
-
-/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_17 [17:17] */
-#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_17_MASK 0x00020000
-#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_17_SHIFT 17
-#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_17_DEFAULT 0x00000000
-
-/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_16 [16:16] */
-#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_16_MASK 0x00010000
-#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_16_SHIFT 16
-#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_16_DEFAULT 0x00000000
-
-/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_15 [15:15] */
-#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_15_MASK 0x00008000
-#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_15_SHIFT 15
-#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_15_DEFAULT 0x00000000
-
-/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_14 [14:14] */
-#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_14_MASK 0x00004000
-#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_14_SHIFT 14
-#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_14_DEFAULT 0x00000000
-
-/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_13 [13:13] */
-#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_13_MASK 0x00002000
-#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_13_SHIFT 13
-#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_13_DEFAULT 0x00000000
-
-/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_12 [12:12] */
-#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_12_MASK 0x00001000
-#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_12_SHIFT 12
-#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_12_DEFAULT 0x00000000
-
-/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_11 [11:11] */
-#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_11_MASK 0x00000800
-#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_11_SHIFT 11
-#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_11_DEFAULT 0x00000000
-
-/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_10 [10:10] */
-#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_10_MASK 0x00000400
-#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_10_SHIFT 10
-#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_10_DEFAULT 0x00000000
-
-/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_09 [09:09] */
-#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_09_MASK 0x00000200
-#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_09_SHIFT 9
-#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_09_DEFAULT 0x00000000
-
-/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_08 [08:08] */
-#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_08_MASK 0x00000100
-#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_08_SHIFT 8
-#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_08_DEFAULT 0x00000000
-
-/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_07 [07:07] */
-#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_07_MASK 0x00000080
-#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_07_SHIFT 7
-#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_07_DEFAULT 0x00000000
-
-/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_06 [06:06] */
-#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_06_MASK 0x00000040
-#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_06_SHIFT 6
-#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_06_DEFAULT 0x00000000
-
-/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_05 [05:05] */
-#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_05_MASK 0x00000020
-#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_05_SHIFT 5
-#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_05_DEFAULT 0x00000000
-
-/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_04 [04:04] */
-#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_04_MASK 0x00000010
-#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_04_SHIFT 4
-#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_04_DEFAULT 0x00000000
-
-/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_03 [03:03] */
-#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_03_MASK 0x00000008
-#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_03_SHIFT 3
-#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_03_DEFAULT 0x00000000
-
-/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_02 [02:02] */
-#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_02_MASK 0x00000004
-#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_02_SHIFT 2
-#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_02_DEFAULT 0x00000000
-
-/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_01 [01:01] */
-#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_01_MASK 0x00000002
-#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_01_SHIFT 1
-#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_01_DEFAULT 0x00000000
-
-/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_00 [00:00] */
-#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_00_MASK 0x00000001
-#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_00_SHIFT 0
-#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_00_DEFAULT 0x00000000
-
-/***************************************************************************
- *SYSTEM_DATA_RAM%i - System Data RAM Address 0..127
- ***************************************************************************/
-#define BCHP_AON_CTRL_SYSTEM_DATA_RAMi_ARRAY_BASE 0x20410200
-#define BCHP_AON_CTRL_SYSTEM_DATA_RAMi_ARRAY_START 0
-#define BCHP_AON_CTRL_SYSTEM_DATA_RAMi_ARRAY_END 127
-#define BCHP_AON_CTRL_SYSTEM_DATA_RAMi_ARRAY_ELEMENT_SIZE 32
-
-/***************************************************************************
- *SYSTEM_DATA_RAM%i - System Data RAM Address 0..127
- ***************************************************************************/
-/* AON_CTRL :: SYSTEM_DATA_RAMi :: SYSTEM_DATA_RAM [31:00] */
-#define BCHP_AON_CTRL_SYSTEM_DATA_RAMi_SYSTEM_DATA_RAM_MASK 0xffffffff
-#define BCHP_AON_CTRL_SYSTEM_DATA_RAMi_SYSTEM_DATA_RAM_SHIFT 0
-
-
-#endif /* #ifndef BCHP_AON_CTRL_H__ */
-
-/* End of File */
diff --git a/include/linux/brcmstb/7145a0/bchp_aon_pin_ctrl.h b/include/linux/brcmstb/7145a0/bchp_aon_pin_ctrl.h
deleted file mode 100644
index a0cb113..0000000
--- a/include/linux/brcmstb/7145a0/bchp_aon_pin_ctrl.h
+++ /dev/null
@@ -1,481 +0,0 @@
-/***************************************************************************
- * Copyright (c) 1999-2013, Broadcom Corporation
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
- *
- * Module Description:
- * DO NOT EDIT THIS FILE DIRECTLY
- *
- * This module was generated magically with RDB from a source description
- * file. You must edit the source file for changes to be made to this file.
- *
- *
- * Date: Generated on Sat Apr 6 03:07:49 2013
- * MD5 Checksum d41d8cd98f00b204e9800998ecf8427e
- *
- * Compiled with: RDB Utility combo_header.pl
- * RDB Parser 3.0
- * unknown unknown
- * Perl Interpreter 5.008008
- * Operating System linux
- *
- * Revision History:
- *
- * $brcm_Log: $
- *
- ***************************************************************************/
-
-#ifndef BCHP_AON_PIN_CTRL_H__
-#define BCHP_AON_PIN_CTRL_H__
-
-/***************************************************************************
- *AON_PIN_CTRL - AON Pinmux Control Registers
- ***************************************************************************/
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0 0x20410500 /* Pinmux control register 0 */
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1 0x20410504 /* Pinmux control register 1 */
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2 0x20410508 /* Pinmux control register 2 */
-#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0 0x2041050c /* Pad pull-up/pull-down control register 0 */
-#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1 0x20410510 /* Pad pull-up/pull-down control register 1 */
-#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_2 0x20410514 /* Pad pull-up/pull-down control register 2 */
-#define BCHP_AON_PIN_CTRL_BYP_CLK_UNSELECT_0 0x20410518 /* Bypass clock unselect register 0 */
-
-/***************************************************************************
- *PIN_MUX_CTRL_0 - Pinmux control register 0
- ***************************************************************************/
-/* AON_PIN_CTRL :: PIN_MUX_CTRL_0 :: aon_gpio_07 [31:28] */
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_07_MASK 0xf0000000
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_07_SHIFT 28
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_07_DEFAULT 0x00000000
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_07_AON_GPIO_07 0
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_07_LED_LS_3 1
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_07_LED_LD_15 2
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_07_UART_RXD_3 3
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_07_PM_AON_GPIO_07 4
-
-/* AON_PIN_CTRL :: PIN_MUX_CTRL_0 :: aon_gpio_06 [27:24] */
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_06_MASK 0x0f000000
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_06_SHIFT 24
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_06_DEFAULT 0x00000000
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_06_AON_GPIO_06 0
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_06_LED_LS_2 1
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_06_LED_LD_14 2
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_06_UART_TXD_3 3
-
-/* AON_PIN_CTRL :: PIN_MUX_CTRL_0 :: aon_gpio_05 [23:20] */
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_05_MASK 0x00f00000
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_05_SHIFT 20
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_05_DEFAULT 0x00000000
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_05_AON_GPIO_05 0
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_05_LED_LS_1 1
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_05_LED_LD_13 2
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_05_SPI_M_SS2B 3
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_05_PM_AON_GPIO_05 4
-
-/* AON_PIN_CTRL :: PIN_MUX_CTRL_0 :: aon_gpio_04 [19:16] */
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_04_MASK 0x000f0000
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_04_SHIFT 16
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_04_DEFAULT 0x00000000
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_04_AON_GPIO_04 0
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_04_LED_LS_0 1
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_04_LED_LD_12 2
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_04_SPI_M_SS1B 3
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_04_UART_TXD_1 4
-
-/* AON_PIN_CTRL :: PIN_MUX_CTRL_0 :: aon_gpio_03 [15:12] */
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_03_MASK 0x0000f000
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_03_SHIFT 12
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_03_DEFAULT 0x00000000
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_03_AON_GPIO_03 0
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_03_LED_KD_3 1
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_03_LED_LD_11 2
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_03_SPI_M_SS0B 3
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_03_UART_RTS_1 4
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_03_PM_AON_GPIO_03 5
-
-/* AON_PIN_CTRL :: PIN_MUX_CTRL_0 :: aon_gpio_02 [11:08] */
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_02_MASK 0x00000f00
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_02_SHIFT 8
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_02_DEFAULT 0x00000000
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_02_AON_GPIO_02 0
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_02_LED_KD_2 1
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_02_LED_LD_10 2
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_02_SPI_M_MISO 3
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_02_UART_CTS_1 4
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_02_PM_AON_GPIO_02 5
-
-/* AON_PIN_CTRL :: PIN_MUX_CTRL_0 :: aon_gpio_01 [07:04] */
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_01_MASK 0x000000f0
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_01_SHIFT 4
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_01_DEFAULT 0x00000000
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_01_AON_GPIO_01 0
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_01_LED_KD_1 1
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_01_LED_LD_9 2
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_01_SPI_M_MOSI 3
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_01_UART_RXD_1 4
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_01_PM_AON_GPIO_01 5
-
-/* AON_PIN_CTRL :: PIN_MUX_CTRL_0 :: aon_gpio_00 [03:00] */
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_00_MASK 0x0000000f
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_00_SHIFT 0
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_00_DEFAULT 0x00000000
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_00_AON_GPIO_00 0
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_00_LED_KD_0 1
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_00_LED_LD_8 2
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_00_SPI_M_SCK 3
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_00_SATA_MDCLK 4
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_00_PM_AON_GPIO_00 5
-
-/***************************************************************************
- *PIN_MUX_CTRL_1 - Pinmux control register 1
- ***************************************************************************/
-/* AON_PIN_CTRL :: PIN_MUX_CTRL_1 :: aon_gpio_15 [31:28] */
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_15_MASK 0xf0000000
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_15_SHIFT 28
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_15_DEFAULT 0x00000000
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_15_AON_GPIO_15 0
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_15_LED_LD_6 1
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_15_UART_CTS_2 2
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_15_SATA_MDIO 3
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_15_PM_AON_GPIO_15 4
-
-/* AON_PIN_CTRL :: PIN_MUX_CTRL_1 :: aon_gpio_14 [27:24] */
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_14_MASK 0x0f000000
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_14_SHIFT 24
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_14_DEFAULT 0x00000000
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_14_AON_GPIO_14 0
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_14_LED_LD_5 1
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_14_UART_RXD_2 2
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_14_I2S_LR0_OUT 3
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_14_PM_AON_GPIO_14 4
-
-/* AON_PIN_CTRL :: PIN_MUX_CTRL_1 :: aon_gpio_13 [23:20] */
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_13_MASK 0x00f00000
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_13_SHIFT 20
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_13_DEFAULT 0x00000000
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_13_AON_GPIO_13 0
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_13_LED_LD_4 1
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_13_UART_TXD_2 2
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_13_I2S_DATA0_OUT 3
-
-/* AON_PIN_CTRL :: PIN_MUX_CTRL_1 :: aon_gpio_12 [19:16] */
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_12_MASK 0x000f0000
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_12_SHIFT 16
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_12_DEFAULT 0x00000000
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_12_AON_GPIO_12 0
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_12_LED_LD_3 1
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_12_UART_RTS_2 2
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_12_I2S_CLK0_OUT 3
-
-/* AON_PIN_CTRL :: PIN_MUX_CTRL_1 :: aon_gpio_11 [15:12] */
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_11_MASK 0x0000f000
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_11_SHIFT 12
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_11_DEFAULT 0x00000000
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_11_AON_GPIO_11 0
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_11_LED_LD_2 1
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_11_UART_CTS_0 2
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_11_PM_AON_GPIO_11 3
-
-/* AON_PIN_CTRL :: PIN_MUX_CTRL_1 :: aon_gpio_10 [11:08] */
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_10_MASK 0x00000f00
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_10_SHIFT 8
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_10_DEFAULT 0x00000000
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_10_AON_GPIO_10 0
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_10_LED_LD_1 1
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_10_UART_RTS_0 2
-
-/* AON_PIN_CTRL :: PIN_MUX_CTRL_1 :: aon_gpio_09 [07:04] */
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_09_MASK 0x000000f0
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_09_SHIFT 4
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_09_DEFAULT 0x00000000
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_09_AON_GPIO_09 0
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_09_LED_LD_0 1
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_09_UART_RXD_0 2
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_09_IR_IN1 3
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_09_PM_AON_GPIO_09 4
-
-/* AON_PIN_CTRL :: PIN_MUX_CTRL_1 :: aon_gpio_08 [03:00] */
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_08_MASK 0x0000000f
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_08_SHIFT 0
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_08_DEFAULT 0x00000000
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_08_AON_GPIO_08 0
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_08_LED_LS_4 1
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_08_UART_TXD_0 2
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_08_PM_AON_GPIO_08 3
-
-/***************************************************************************
- *PIN_MUX_CTRL_2 - Pinmux control register 2
- ***************************************************************************/
-/* AON_PIN_CTRL :: PIN_MUX_CTRL_2 :: aon_sgpio_05 [31:28] */
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_sgpio_05_MASK 0xf0000000
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_sgpio_05_SHIFT 28
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_sgpio_05_DEFAULT 0x00000000
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_sgpio_05_AON_SGPIO_05 0
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_sgpio_05_BSC_M2_SDA 1
-
-/* AON_PIN_CTRL :: PIN_MUX_CTRL_2 :: aon_sgpio_04 [27:24] */
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_sgpio_04_MASK 0x0f000000
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_sgpio_04_SHIFT 24
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_sgpio_04_DEFAULT 0x00000000
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_sgpio_04_AON_SGPIO_04 0
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_sgpio_04_BSC_M2_SCL 1
-
-/* AON_PIN_CTRL :: PIN_MUX_CTRL_2 :: aon_sgpio_03 [23:20] */
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_sgpio_03_MASK 0x00f00000
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_sgpio_03_SHIFT 20
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_sgpio_03_DEFAULT 0x00000000
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_sgpio_03_AON_SGPIO_03 0
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_sgpio_03_BSC_M1_SDA 1
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_sgpio_03_HDMI_RX_BSC_SDA 2
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_sgpio_03_BSC_S1_SDA 3
-
-/* AON_PIN_CTRL :: PIN_MUX_CTRL_2 :: aon_sgpio_02 [19:16] */
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_sgpio_02_MASK 0x000f0000
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_sgpio_02_SHIFT 16
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_sgpio_02_DEFAULT 0x00000000
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_sgpio_02_AON_SGPIO_02 0
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_sgpio_02_BSC_M1_SCL 1
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_sgpio_02_HDMI_RX_BSC_SCL 2
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_sgpio_02_BSC_S1_SCL 3
-
-/* AON_PIN_CTRL :: PIN_MUX_CTRL_2 :: aon_sgpio_01 [15:12] */
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_sgpio_01_MASK 0x0000f000
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_sgpio_01_SHIFT 12
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_sgpio_01_DEFAULT 0x00000000
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_sgpio_01_AON_SGPIO_01 0
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_sgpio_01_BSC_M0_SDA 1
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_sgpio_01_HDMI_TX_BSC_SDA 2
-
-/* AON_PIN_CTRL :: PIN_MUX_CTRL_2 :: aon_sgpio_00 [11:08] */
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_sgpio_00_MASK 0x00000f00
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_sgpio_00_SHIFT 8
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_sgpio_00_DEFAULT 0x00000000
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_sgpio_00_AON_SGPIO_00 0
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_sgpio_00_BSC_M0_SCL 1
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_sgpio_00_HDMI_TX_BSC_SCL 2
-
-/* AON_PIN_CTRL :: PIN_MUX_CTRL_2 :: aon_gpio_17 [07:04] */
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_17_MASK 0x000000f0
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_17_SHIFT 4
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_17_DEFAULT 0x00000001
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_17_AON_GPIO_17 0
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_17_LED_OUT 1
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_17_PM_AON_GPIO_17 2
-
-/* AON_PIN_CTRL :: PIN_MUX_CTRL_2 :: aon_gpio_16 [03:00] */
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_16_MASK 0x0000000f
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_16_SHIFT 0
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_16_DEFAULT 0x00000000
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_16_AON_GPIO_16 0
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_16_LED_LD_7 1
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_16_PM_AON_GPIO_16 2
-
-/***************************************************************************
- *PIN_MUX_PAD_CTRL_0 - Pad pull-up/pull-down control register 0
- ***************************************************************************/
-/* AON_PIN_CTRL :: PIN_MUX_PAD_CTRL_0 :: spare_pad_ctrl_0 [31:30] */
-#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_spare_pad_ctrl_0_MASK 0xc0000000
-#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_spare_pad_ctrl_0_SHIFT 30
-#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_spare_pad_ctrl_0_DEFAULT 0x00000000
-#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_spare_pad_ctrl_0_PULL_NONE 0
-#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_spare_pad_ctrl_0_PULL_DOWN 1
-#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_spare_pad_ctrl_0_PULL_UP 2
-
-/* AON_PIN_CTRL :: PIN_MUX_PAD_CTRL_0 :: aon_gpio_05_pad_ctrl [29:28] */
-#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_05_pad_ctrl_MASK 0x30000000
-#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_05_pad_ctrl_SHIFT 28
-#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_05_pad_ctrl_DEFAULT 0x00000001
-#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_05_pad_ctrl_PULL_NONE 0
-#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_05_pad_ctrl_PULL_DOWN 1
-#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_05_pad_ctrl_PULL_UP 2
-
-/* AON_PIN_CTRL :: PIN_MUX_PAD_CTRL_0 :: reserved0 [27:26] */
-#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_reserved0_MASK 0x0c000000
-#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_reserved0_SHIFT 26
-
-/* AON_PIN_CTRL :: PIN_MUX_PAD_CTRL_0 :: aon_gpio_03_pad_ctrl [25:24] */
-#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_03_pad_ctrl_MASK 0x03000000
-#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_03_pad_ctrl_SHIFT 24
-#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_03_pad_ctrl_DEFAULT 0x00000000
-#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_03_pad_ctrl_PULL_NONE 0
-#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_03_pad_ctrl_PULL_DOWN 1
-#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_03_pad_ctrl_PULL_UP 2
-
-/* AON_PIN_CTRL :: PIN_MUX_PAD_CTRL_0 :: aon_gpio_02_pad_ctrl [23:22] */
-#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_02_pad_ctrl_MASK 0x00c00000
-#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_02_pad_ctrl_SHIFT 22
-#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_02_pad_ctrl_DEFAULT 0x00000000
-#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_02_pad_ctrl_PULL_NONE 0
-#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_02_pad_ctrl_PULL_DOWN 1
-#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_02_pad_ctrl_PULL_UP 2
-
-/* AON_PIN_CTRL :: PIN_MUX_PAD_CTRL_0 :: aon_gpio_01_pad_ctrl [21:20] */
-#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_01_pad_ctrl_MASK 0x00300000
-#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_01_pad_ctrl_SHIFT 20
-#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_01_pad_ctrl_DEFAULT 0x00000000
-#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_01_pad_ctrl_PULL_NONE 0
-#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_01_pad_ctrl_PULL_DOWN 1
-#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_01_pad_ctrl_PULL_UP 2
-
-/* AON_PIN_CTRL :: PIN_MUX_PAD_CTRL_0 :: aon_gpio_00_pad_ctrl [19:18] */
-#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_00_pad_ctrl_MASK 0x000c0000
-#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_00_pad_ctrl_SHIFT 18
-#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_00_pad_ctrl_DEFAULT 0x00000000
-#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_00_pad_ctrl_PULL_NONE 0
-#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_00_pad_ctrl_PULL_DOWN 1
-#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_00_pad_ctrl_PULL_UP 2
-
-/* AON_PIN_CTRL :: PIN_MUX_PAD_CTRL_0 :: reserved1 [17:00] */
-#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_reserved1_MASK 0x0003ffff
-#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_reserved1_SHIFT 0
-
-/***************************************************************************
- *PIN_MUX_PAD_CTRL_1 - Pad pull-up/pull-down control register 1
- ***************************************************************************/
-/* AON_PIN_CTRL :: PIN_MUX_PAD_CTRL_1 :: spare_pad_ctrl_1 [31:30] */
-#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_spare_pad_ctrl_1_MASK 0xc0000000
-#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_spare_pad_ctrl_1_SHIFT 30
-#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_spare_pad_ctrl_1_DEFAULT 0x00000000
-#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_spare_pad_ctrl_1_PULL_NONE 0
-#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_spare_pad_ctrl_1_PULL_DOWN 1
-#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_spare_pad_ctrl_1_PULL_UP 2
-
-/* AON_PIN_CTRL :: PIN_MUX_PAD_CTRL_1 :: reserved0 [29:24] */
-#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_reserved0_MASK 0x3f000000
-#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_reserved0_SHIFT 24
-
-/* AON_PIN_CTRL :: PIN_MUX_PAD_CTRL_1 :: aon_gpio_17_pad_ctrl [23:22] */
-#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_17_pad_ctrl_MASK 0x00c00000
-#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_17_pad_ctrl_SHIFT 22
-#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_17_pad_ctrl_DEFAULT 0x00000001
-#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_17_pad_ctrl_PULL_NONE 0
-#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_17_pad_ctrl_PULL_DOWN 1
-#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_17_pad_ctrl_PULL_UP 2
-
-/* AON_PIN_CTRL :: PIN_MUX_PAD_CTRL_1 :: aon_gpio_16_pad_ctrl [21:20] */
-#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_16_pad_ctrl_MASK 0x00300000
-#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_16_pad_ctrl_SHIFT 20
-#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_16_pad_ctrl_DEFAULT 0x00000001
-#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_16_pad_ctrl_PULL_NONE 0
-#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_16_pad_ctrl_PULL_DOWN 1
-#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_16_pad_ctrl_PULL_UP 2
-
-/* AON_PIN_CTRL :: PIN_MUX_PAD_CTRL_1 :: aon_gpio_15_pad_ctrl [19:18] */
-#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_15_pad_ctrl_MASK 0x000c0000
-#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_15_pad_ctrl_SHIFT 18
-#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_15_pad_ctrl_DEFAULT 0x00000001
-#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_15_pad_ctrl_PULL_NONE 0
-#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_15_pad_ctrl_PULL_DOWN 1
-#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_15_pad_ctrl_PULL_UP 2
-
-/* AON_PIN_CTRL :: PIN_MUX_PAD_CTRL_1 :: aon_gpio_14_pad_ctrl [17:16] */
-#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_14_pad_ctrl_MASK 0x00030000
-#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_14_pad_ctrl_SHIFT 16
-#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_14_pad_ctrl_DEFAULT 0x00000001
-#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_14_pad_ctrl_PULL_NONE 0
-#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_14_pad_ctrl_PULL_DOWN 1
-#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_14_pad_ctrl_PULL_UP 2
-
-/* AON_PIN_CTRL :: PIN_MUX_PAD_CTRL_1 :: reserved1 [15:12] */
-#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_reserved1_MASK 0x0000f000
-#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_reserved1_SHIFT 12
-
-/* AON_PIN_CTRL :: PIN_MUX_PAD_CTRL_1 :: aon_gpio_11_pad_ctrl [11:10] */
-#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_11_pad_ctrl_MASK 0x00000c00
-#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_11_pad_ctrl_SHIFT 10
-#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_11_pad_ctrl_DEFAULT 0x00000001
-#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_11_pad_ctrl_PULL_NONE 0
-#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_11_pad_ctrl_PULL_DOWN 1
-#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_11_pad_ctrl_PULL_UP 2
-
-/* AON_PIN_CTRL :: PIN_MUX_PAD_CTRL_1 :: reserved2 [09:08] */
-#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_reserved2_MASK 0x00000300
-#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_reserved2_SHIFT 8
-
-/* AON_PIN_CTRL :: PIN_MUX_PAD_CTRL_1 :: aon_gpio_09_pad_ctrl [07:06] */
-#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_09_pad_ctrl_MASK 0x000000c0
-#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_09_pad_ctrl_SHIFT 6
-#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_09_pad_ctrl_DEFAULT 0x00000001
-#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_09_pad_ctrl_PULL_NONE 0
-#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_09_pad_ctrl_PULL_DOWN 1
-#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_09_pad_ctrl_PULL_UP 2
-
-/* AON_PIN_CTRL :: PIN_MUX_PAD_CTRL_1 :: aon_gpio_08_pad_ctrl [05:04] */
-#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_08_pad_ctrl_MASK 0x00000030
-#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_08_pad_ctrl_SHIFT 4
-#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_08_pad_ctrl_DEFAULT 0x00000001
-#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_08_pad_ctrl_PULL_NONE 0
-#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_08_pad_ctrl_PULL_DOWN 1
-#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_08_pad_ctrl_PULL_UP 2
-
-/* AON_PIN_CTRL :: PIN_MUX_PAD_CTRL_1 :: aon_gpio_07_pad_ctrl [03:02] */
-#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_07_pad_ctrl_MASK 0x0000000c
-#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_07_pad_ctrl_SHIFT 2
-#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_07_pad_ctrl_DEFAULT 0x00000001
-#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_07_pad_ctrl_PULL_NONE 0
-#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_07_pad_ctrl_PULL_DOWN 1
-#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_07_pad_ctrl_PULL_UP 2
-
-/* AON_PIN_CTRL :: PIN_MUX_PAD_CTRL_1 :: reserved3 [01:00] */
-#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_reserved3_MASK 0x00000003
-#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_reserved3_SHIFT 0
-
-/***************************************************************************
- *PIN_MUX_PAD_CTRL_2 - Pad pull-up/pull-down control register 2
- ***************************************************************************/
-/* AON_PIN_CTRL :: PIN_MUX_PAD_CTRL_2 :: reserved0 [31:08] */
-#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_2_reserved0_MASK 0xffffff00
-#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_2_reserved0_SHIFT 8
-
-/* AON_PIN_CTRL :: PIN_MUX_PAD_CTRL_2 :: spare_pad_ctrl_2 [07:06] */
-#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_2_spare_pad_ctrl_2_MASK 0x000000c0
-#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_2_spare_pad_ctrl_2_SHIFT 6
-#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_2_spare_pad_ctrl_2_DEFAULT 0x00000000
-#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_2_spare_pad_ctrl_2_PULL_NONE 0
-#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_2_spare_pad_ctrl_2_PULL_DOWN 1
-#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_2_spare_pad_ctrl_2_PULL_UP 2
-
-/* AON_PIN_CTRL :: PIN_MUX_PAD_CTRL_2 :: reserved1 [05:00] */
-#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_2_reserved1_MASK 0x0000003f
-#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_2_reserved1_SHIFT 0
-
-/***************************************************************************
- *BYP_CLK_UNSELECT_0 - Bypass clock unselect register 0
- ***************************************************************************/
-/* AON_PIN_CTRL :: BYP_CLK_UNSELECT_0 :: reserved0 [31:04] */
-#define BCHP_AON_PIN_CTRL_BYP_CLK_UNSELECT_0_reserved0_MASK 0xfffffff0
-#define BCHP_AON_PIN_CTRL_BYP_CLK_UNSELECT_0_reserved0_SHIFT 4
-
-/* AON_PIN_CTRL :: BYP_CLK_UNSELECT_0 :: unsel_byp_clk_on_aon_gpio_11 [03:03] */
-#define BCHP_AON_PIN_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_aon_gpio_11_MASK 0x00000008
-#define BCHP_AON_PIN_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_aon_gpio_11_SHIFT 3
-#define BCHP_AON_PIN_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_aon_gpio_11_DEFAULT 0x00000000
-
-/* AON_PIN_CTRL :: BYP_CLK_UNSELECT_0 :: unsel_byp_clk_on_aon_gpio_10 [02:02] */
-#define BCHP_AON_PIN_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_aon_gpio_10_MASK 0x00000004
-#define BCHP_AON_PIN_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_aon_gpio_10_SHIFT 2
-#define BCHP_AON_PIN_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_aon_gpio_10_DEFAULT 0x00000000
-
-/* AON_PIN_CTRL :: BYP_CLK_UNSELECT_0 :: unsel_byp_clk_on_aon_gpio_09 [01:01] */
-#define BCHP_AON_PIN_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_aon_gpio_09_MASK 0x00000002
-#define BCHP_AON_PIN_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_aon_gpio_09_SHIFT 1
-#define BCHP_AON_PIN_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_aon_gpio_09_DEFAULT 0x00000000
-
-/* AON_PIN_CTRL :: BYP_CLK_UNSELECT_0 :: unsel_byp_clk_on_aon_hdmi_rx_cec [00:00] */
-#define BCHP_AON_PIN_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_aon_hdmi_rx_cec_MASK 0x00000001
-#define BCHP_AON_PIN_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_aon_hdmi_rx_cec_SHIFT 0
-#define BCHP_AON_PIN_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_aon_hdmi_rx_cec_DEFAULT 0x00000000
-
-#endif /* #ifndef BCHP_AON_PIN_CTRL_H__ */
-
-/* End of File */
diff --git a/include/linux/brcmstb/7145a0/bchp_aon_pm_l2.h b/include/linux/brcmstb/7145a0/bchp_aon_pm_l2.h
deleted file mode 100644
index 3615f78..0000000
--- a/include/linux/brcmstb/7145a0/bchp_aon_pm_l2.h
+++ /dev/null
@@ -1,1346 +0,0 @@
-/***************************************************************************
- * Copyright (c) 1999-2014, Broadcom Corporation
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
- *
- * Module Description:
- * DO NOT EDIT THIS FILE DIRECTLY
- *
- * This module was generated magically with RDB from a source description
- * file. You must edit the source file for changes to be made to this file.
- *
- *
- * Date: Generated on Wed Sep 3 13:17:40 2014
- * Full Compile MD5 Checksum a8ee62ccf9dde43435c825f266da463d
- * (minus title and desc)
- * MD5 Checksum e373b364a1742e13a0f9eb15fd8aa94f
- *
- * Compiled with: RDB Utility combo_header.pl
- * RDB Parser 3.0
- * unknown unknown
- * Perl Interpreter 5.008005
- * Operating System linux
- *
- * Revision History:
- *
- * $brcm_Log: $
- *
- ***************************************************************************/
-
-#ifndef BCHP_AON_PM_L2_H__
-#define BCHP_AON_PM_L2_H__
-
-/***************************************************************************
- *AON_PM_L2 - AON Power Management L2 Interrupt Controller Registers
- ***************************************************************************/
-#define BCHP_AON_PM_L2_CPU_STATUS 0x20410440 /* CPU interrupt Status Register */
-#define BCHP_AON_PM_L2_CPU_SET 0x20410444 /* CPU interrupt Set Register */
-#define BCHP_AON_PM_L2_CPU_CLEAR 0x20410448 /* CPU interrupt Clear Register */
-#define BCHP_AON_PM_L2_CPU_MASK_STATUS 0x2041044c /* CPU interrupt Mask Status Register */
-#define BCHP_AON_PM_L2_CPU_MASK_SET 0x20410450 /* CPU interrupt Mask Set Register */
-#define BCHP_AON_PM_L2_CPU_MASK_CLEAR 0x20410454 /* CPU interrupt Mask Clear Register */
-#define BCHP_AON_PM_L2_PCI_STATUS 0x20410458 /* PCI interrupt Status Register */
-#define BCHP_AON_PM_L2_PCI_SET 0x2041045c /* PCI interrupt Set Register */
-#define BCHP_AON_PM_L2_PCI_CLEAR 0x20410460 /* PCI interrupt Clear Register */
-#define BCHP_AON_PM_L2_PCI_MASK_STATUS 0x20410464 /* PCI interrupt Mask Status Register */
-#define BCHP_AON_PM_L2_PCI_MASK_SET 0x20410468 /* PCI interrupt Mask Set Register */
-#define BCHP_AON_PM_L2_PCI_MASK_CLEAR 0x2041046c /* PCI interrupt Mask Clear Register */
-
-/***************************************************************************
- *CPU_STATUS - CPU interrupt Status Register
- ***************************************************************************/
-/* AON_PM_L2 :: CPU_STATUS :: reserved0 [31:20] */
-#define BCHP_AON_PM_L2_CPU_STATUS_reserved0_MASK 0xfff00000
-#define BCHP_AON_PM_L2_CPU_STATUS_reserved0_SHIFT 20
-
-/* AON_PM_L2 :: CPU_STATUS :: DCS_PH3_RESET [19:19] */
-#define BCHP_AON_PM_L2_CPU_STATUS_DCS_PH3_RESET_MASK 0x00080000
-#define BCHP_AON_PM_L2_CPU_STATUS_DCS_PH3_RESET_SHIFT 19
-#define BCHP_AON_PM_L2_CPU_STATUS_DCS_PH3_RESET_DEFAULT 0x00000000
-
-/* AON_PM_L2 :: CPU_STATUS :: FP_RESET [18:18] */
-#define BCHP_AON_PM_L2_CPU_STATUS_FP_RESET_MASK 0x00040000
-#define BCHP_AON_PM_L2_CPU_STATUS_FP_RESET_SHIFT 18
-#define BCHP_AON_PM_L2_CPU_STATUS_FP_RESET_DEFAULT 0x00000000
-
-/* AON_PM_L2 :: CPU_STATUS :: BOUNDARY_SCAN_REQ [17:17] */
-#define BCHP_AON_PM_L2_CPU_STATUS_BOUNDARY_SCAN_REQ_MASK 0x00020000
-#define BCHP_AON_PM_L2_CPU_STATUS_BOUNDARY_SCAN_REQ_SHIFT 17
-#define BCHP_AON_PM_L2_CPU_STATUS_BOUNDARY_SCAN_REQ_DEFAULT 0x00000000
-
-/* AON_PM_L2 :: CPU_STATUS :: DCS_HEADEND_INTR [16:16] */
-#define BCHP_AON_PM_L2_CPU_STATUS_DCS_HEADEND_INTR_MASK 0x00010000
-#define BCHP_AON_PM_L2_CPU_STATUS_DCS_HEADEND_INTR_SHIFT 16
-#define BCHP_AON_PM_L2_CPU_STATUS_DCS_HEADEND_INTR_DEFAULT 0x00000000
-
-/* AON_PM_L2 :: CPU_STATUS :: BMU_INTR_BATT_LOW [15:15] */
-#define BCHP_AON_PM_L2_CPU_STATUS_BMU_INTR_BATT_LOW_MASK 0x00008000
-#define BCHP_AON_PM_L2_CPU_STATUS_BMU_INTR_BATT_LOW_SHIFT 15
-#define BCHP_AON_PM_L2_CPU_STATUS_BMU_INTR_BATT_LOW_DEFAULT 0x00000000
-
-/* AON_PM_L2 :: CPU_STATUS :: BMU_INTR_AP_RESTORED [14:14] */
-#define BCHP_AON_PM_L2_CPU_STATUS_BMU_INTR_AP_RESTORED_MASK 0x00004000
-#define BCHP_AON_PM_L2_CPU_STATUS_BMU_INTR_AP_RESTORED_SHIFT 14
-#define BCHP_AON_PM_L2_CPU_STATUS_BMU_INTR_AP_RESTORED_DEFAULT 0x00000000
-
-/* AON_PM_L2 :: CPU_STATUS :: BMU_INTR_AP_LOST [13:13] */
-#define BCHP_AON_PM_L2_CPU_STATUS_BMU_INTR_AP_LOST_MASK 0x00002000
-#define BCHP_AON_PM_L2_CPU_STATUS_BMU_INTR_AP_LOST_SHIFT 13
-#define BCHP_AON_PM_L2_CPU_STATUS_BMU_INTR_AP_LOST_DEFAULT 0x00000000
-
-/* AON_PM_L2 :: CPU_STATUS :: USB0 [12:12] */
-#define BCHP_AON_PM_L2_CPU_STATUS_USB0_MASK 0x00001000
-#define BCHP_AON_PM_L2_CPU_STATUS_USB0_SHIFT 12
-#define BCHP_AON_PM_L2_CPU_STATUS_USB0_DEFAULT 0x00000000
-
-/* AON_PM_L2 :: CPU_STATUS :: MOCA [11:11] */
-#define BCHP_AON_PM_L2_CPU_STATUS_MOCA_MASK 0x00000800
-#define BCHP_AON_PM_L2_CPU_STATUS_MOCA_SHIFT 11
-#define BCHP_AON_PM_L2_CPU_STATUS_MOCA_DEFAULT 0x00000000
-
-/* AON_PM_L2 :: CPU_STATUS :: XPT_PMU [10:10] */
-#define BCHP_AON_PM_L2_CPU_STATUS_XPT_PMU_MASK 0x00000400
-#define BCHP_AON_PM_L2_CPU_STATUS_XPT_PMU_SHIFT 10
-#define BCHP_AON_PM_L2_CPU_STATUS_XPT_PMU_DEFAULT 0x00000000
-
-/* AON_PM_L2 :: CPU_STATUS :: CAP [09:09] */
-#define BCHP_AON_PM_L2_CPU_STATUS_CAP_MASK 0x00000200
-#define BCHP_AON_PM_L2_CPU_STATUS_CAP_SHIFT 9
-#define BCHP_AON_PM_L2_CPU_STATUS_CAP_DEFAULT 0x00000000
-
-/* AON_PM_L2 :: CPU_STATUS :: WOL_UNIMAC2 [08:08] */
-#define BCHP_AON_PM_L2_CPU_STATUS_WOL_UNIMAC2_MASK 0x00000100
-#define BCHP_AON_PM_L2_CPU_STATUS_WOL_UNIMAC2_SHIFT 8
-#define BCHP_AON_PM_L2_CPU_STATUS_WOL_UNIMAC2_DEFAULT 0x00000000
-
-/* AON_PM_L2 :: CPU_STATUS :: WOL_UNIMAC1 [07:07] */
-#define BCHP_AON_PM_L2_CPU_STATUS_WOL_UNIMAC1_MASK 0x00000080
-#define BCHP_AON_PM_L2_CPU_STATUS_WOL_UNIMAC1_SHIFT 7
-#define BCHP_AON_PM_L2_CPU_STATUS_WOL_UNIMAC1_DEFAULT 0x00000000
-
-/* AON_PM_L2 :: CPU_STATUS :: WOL_UNIMAC0 [06:06] */
-#define BCHP_AON_PM_L2_CPU_STATUS_WOL_UNIMAC0_MASK 0x00000040
-#define BCHP_AON_PM_L2_CPU_STATUS_WOL_UNIMAC0_SHIFT 6
-#define BCHP_AON_PM_L2_CPU_STATUS_WOL_UNIMAC0_DEFAULT 0x00000000
-
-/* AON_PM_L2 :: CPU_STATUS :: GPIO [05:05] */
-#define BCHP_AON_PM_L2_CPU_STATUS_GPIO_MASK 0x00000020
-#define BCHP_AON_PM_L2_CPU_STATUS_GPIO_SHIFT 5
-#define BCHP_AON_PM_L2_CPU_STATUS_GPIO_DEFAULT 0x00000000
-
-/* AON_PM_L2 :: CPU_STATUS :: NMI_B_INTR [04:04] */
-#define BCHP_AON_PM_L2_CPU_STATUS_NMI_B_INTR_MASK 0x00000010
-#define BCHP_AON_PM_L2_CPU_STATUS_NMI_B_INTR_SHIFT 4
-#define BCHP_AON_PM_L2_CPU_STATUS_NMI_B_INTR_DEFAULT 0x00000000
-
-/* AON_PM_L2 :: CPU_STATUS :: TIMER_INTR [03:03] */
-#define BCHP_AON_PM_L2_CPU_STATUS_TIMER_INTR_MASK 0x00000008
-#define BCHP_AON_PM_L2_CPU_STATUS_TIMER_INTR_SHIFT 3
-#define BCHP_AON_PM_L2_CPU_STATUS_TIMER_INTR_DEFAULT 0x00000000
-
-/* AON_PM_L2 :: CPU_STATUS :: KPD_INTR [02:02] */
-#define BCHP_AON_PM_L2_CPU_STATUS_KPD_INTR_MASK 0x00000004
-#define BCHP_AON_PM_L2_CPU_STATUS_KPD_INTR_SHIFT 2
-#define BCHP_AON_PM_L2_CPU_STATUS_KPD_INTR_DEFAULT 0x00000000
-
-/* AON_PM_L2 :: CPU_STATUS :: IRR_INTR [01:01] */
-#define BCHP_AON_PM_L2_CPU_STATUS_IRR_INTR_MASK 0x00000002
-#define BCHP_AON_PM_L2_CPU_STATUS_IRR_INTR_SHIFT 1
-#define BCHP_AON_PM_L2_CPU_STATUS_IRR_INTR_DEFAULT 0x00000000
-
-/* AON_PM_L2 :: CPU_STATUS :: CEC_INTR [00:00] */
-#define BCHP_AON_PM_L2_CPU_STATUS_CEC_INTR_MASK 0x00000001
-#define BCHP_AON_PM_L2_CPU_STATUS_CEC_INTR_SHIFT 0
-#define BCHP_AON_PM_L2_CPU_STATUS_CEC_INTR_DEFAULT 0x00000000
-
-/***************************************************************************
- *CPU_SET - CPU interrupt Set Register
- ***************************************************************************/
-/* AON_PM_L2 :: CPU_SET :: reserved0 [31:20] */
-#define BCHP_AON_PM_L2_CPU_SET_reserved0_MASK 0xfff00000
-#define BCHP_AON_PM_L2_CPU_SET_reserved0_SHIFT 20
-
-/* AON_PM_L2 :: CPU_SET :: DCS_PH3_RESET [19:19] */
-#define BCHP_AON_PM_L2_CPU_SET_DCS_PH3_RESET_MASK 0x00080000
-#define BCHP_AON_PM_L2_CPU_SET_DCS_PH3_RESET_SHIFT 19
-#define BCHP_AON_PM_L2_CPU_SET_DCS_PH3_RESET_DEFAULT 0x00000000
-
-/* AON_PM_L2 :: CPU_SET :: FP_RESET [18:18] */
-#define BCHP_AON_PM_L2_CPU_SET_FP_RESET_MASK 0x00040000
-#define BCHP_AON_PM_L2_CPU_SET_FP_RESET_SHIFT 18
-#define BCHP_AON_PM_L2_CPU_SET_FP_RESET_DEFAULT 0x00000000
-
-/* AON_PM_L2 :: CPU_SET :: BOUNDARY_SCAN_REQ [17:17] */
-#define BCHP_AON_PM_L2_CPU_SET_BOUNDARY_SCAN_REQ_MASK 0x00020000
-#define BCHP_AON_PM_L2_CPU_SET_BOUNDARY_SCAN_REQ_SHIFT 17
-#define BCHP_AON_PM_L2_CPU_SET_BOUNDARY_SCAN_REQ_DEFAULT 0x00000000
-
-/* AON_PM_L2 :: CPU_SET :: DCS_HEADEND_INTR [16:16] */
-#define BCHP_AON_PM_L2_CPU_SET_DCS_HEADEND_INTR_MASK 0x00010000
-#define BCHP_AON_PM_L2_CPU_SET_DCS_HEADEND_INTR_SHIFT 16
-#define BCHP_AON_PM_L2_CPU_SET_DCS_HEADEND_INTR_DEFAULT 0x00000000
-
-/* AON_PM_L2 :: CPU_SET :: BMU_INTR_BATT_LOW [15:15] */
-#define BCHP_AON_PM_L2_CPU_SET_BMU_INTR_BATT_LOW_MASK 0x00008000
-#define BCHP_AON_PM_L2_CPU_SET_BMU_INTR_BATT_LOW_SHIFT 15
-#define BCHP_AON_PM_L2_CPU_SET_BMU_INTR_BATT_LOW_DEFAULT 0x00000000
-
-/* AON_PM_L2 :: CPU_SET :: BMU_INTR_AP_RESTORED [14:14] */
-#define BCHP_AON_PM_L2_CPU_SET_BMU_INTR_AP_RESTORED_MASK 0x00004000
-#define BCHP_AON_PM_L2_CPU_SET_BMU_INTR_AP_RESTORED_SHIFT 14
-#define BCHP_AON_PM_L2_CPU_SET_BMU_INTR_AP_RESTORED_DEFAULT 0x00000000
-
-/* AON_PM_L2 :: CPU_SET :: BMU_INTR_AP_LOST [13:13] */
-#define BCHP_AON_PM_L2_CPU_SET_BMU_INTR_AP_LOST_MASK 0x00002000
-#define BCHP_AON_PM_L2_CPU_SET_BMU_INTR_AP_LOST_SHIFT 13
-#define BCHP_AON_PM_L2_CPU_SET_BMU_INTR_AP_LOST_DEFAULT 0x00000000
-
-/* AON_PM_L2 :: CPU_SET :: USB0 [12:12] */
-#define BCHP_AON_PM_L2_CPU_SET_USB0_MASK 0x00001000
-#define BCHP_AON_PM_L2_CPU_SET_USB0_SHIFT 12
-#define BCHP_AON_PM_L2_CPU_SET_USB0_DEFAULT 0x00000000
-
-/* AON_PM_L2 :: CPU_SET :: MOCA [11:11] */
-#define BCHP_AON_PM_L2_CPU_SET_MOCA_MASK 0x00000800
-#define BCHP_AON_PM_L2_CPU_SET_MOCA_SHIFT 11
-#define BCHP_AON_PM_L2_CPU_SET_MOCA_DEFAULT 0x00000000
-
-/* AON_PM_L2 :: CPU_SET :: XPT_PMU [10:10] */
-#define BCHP_AON_PM_L2_CPU_SET_XPT_PMU_MASK 0x00000400
-#define BCHP_AON_PM_L2_CPU_SET_XPT_PMU_SHIFT 10
-#define BCHP_AON_PM_L2_CPU_SET_XPT_PMU_DEFAULT 0x00000000
-
-/* AON_PM_L2 :: CPU_SET :: CAP [09:09] */
-#define BCHP_AON_PM_L2_CPU_SET_CAP_MASK 0x00000200
-#define BCHP_AON_PM_L2_CPU_SET_CAP_SHIFT 9
-#define BCHP_AON_PM_L2_CPU_SET_CAP_DEFAULT 0x00000000
-
-/* AON_PM_L2 :: CPU_SET :: WOL_UNIMAC2 [08:08] */
-#define BCHP_AON_PM_L2_CPU_SET_WOL_UNIMAC2_MASK 0x00000100
-#define BCHP_AON_PM_L2_CPU_SET_WOL_UNIMAC2_SHIFT 8
-#define BCHP_AON_PM_L2_CPU_SET_WOL_UNIMAC2_DEFAULT 0x00000000
-
-/* AON_PM_L2 :: CPU_SET :: WOL_UNIMAC1 [07:07] */
-#define BCHP_AON_PM_L2_CPU_SET_WOL_UNIMAC1_MASK 0x00000080
-#define BCHP_AON_PM_L2_CPU_SET_WOL_UNIMAC1_SHIFT 7
-#define BCHP_AON_PM_L2_CPU_SET_WOL_UNIMAC1_DEFAULT 0x00000000
-
-/* AON_PM_L2 :: CPU_SET :: WOL_UNIMAC0 [06:06] */
-#define BCHP_AON_PM_L2_CPU_SET_WOL_UNIMAC0_MASK 0x00000040
-#define BCHP_AON_PM_L2_CPU_SET_WOL_UNIMAC0_SHIFT 6
-#define BCHP_AON_PM_L2_CPU_SET_WOL_UNIMAC0_DEFAULT 0x00000000
-
-/* AON_PM_L2 :: CPU_SET :: GPIO [05:05] */
-#define BCHP_AON_PM_L2_CPU_SET_GPIO_MASK 0x00000020
-#define BCHP_AON_PM_L2_CPU_SET_GPIO_SHIFT 5
-#define BCHP_AON_PM_L2_CPU_SET_GPIO_DEFAULT 0x00000000
-
-/* AON_PM_L2 :: CPU_SET :: NMI_B_INTR [04:04] */
-#define BCHP_AON_PM_L2_CPU_SET_NMI_B_INTR_MASK 0x00000010
-#define BCHP_AON_PM_L2_CPU_SET_NMI_B_INTR_SHIFT 4
-#define BCHP_AON_PM_L2_CPU_SET_NMI_B_INTR_DEFAULT 0x00000000
-
-/* AON_PM_L2 :: CPU_SET :: TIMER_INTR [03:03] */
-#define BCHP_AON_PM_L2_CPU_SET_TIMER_INTR_MASK 0x00000008
-#define BCHP_AON_PM_L2_CPU_SET_TIMER_INTR_SHIFT 3
-#define BCHP_AON_PM_L2_CPU_SET_TIMER_INTR_DEFAULT 0x00000000
-
-/* AON_PM_L2 :: CPU_SET :: KPD_INTR [02:02] */
-#define BCHP_AON_PM_L2_CPU_SET_KPD_INTR_MASK 0x00000004
-#define BCHP_AON_PM_L2_CPU_SET_KPD_INTR_SHIFT 2
-#define BCHP_AON_PM_L2_CPU_SET_KPD_INTR_DEFAULT 0x00000000
-
-/* AON_PM_L2 :: CPU_SET :: IRR_INTR [01:01] */
-#define BCHP_AON_PM_L2_CPU_SET_IRR_INTR_MASK 0x00000002
-#define BCHP_AON_PM_L2_CPU_SET_IRR_INTR_SHIFT 1
-#define BCHP_AON_PM_L2_CPU_SET_IRR_INTR_DEFAULT 0x00000000
-
-/* AON_PM_L2 :: CPU_SET :: CEC_INTR [00:00] */
-#define BCHP_AON_PM_L2_CPU_SET_CEC_INTR_MASK 0x00000001
-#define BCHP_AON_PM_L2_CPU_SET_CEC_INTR_SHIFT 0
-#define BCHP_AON_PM_L2_CPU_SET_CEC_INTR_DEFAULT 0x00000000
-
-/***************************************************************************
- *CPU_CLEAR - CPU interrupt Clear Register
- ***************************************************************************/
-/* AON_PM_L2 :: CPU_CLEAR :: reserved0 [31:20] */
-#define BCHP_AON_PM_L2_CPU_CLEAR_reserved0_MASK 0xfff00000
-#define BCHP_AON_PM_L2_CPU_CLEAR_reserved0_SHIFT 20
-
-/* AON_PM_L2 :: CPU_CLEAR :: DCS_PH3_RESET [19:19] */
-#define BCHP_AON_PM_L2_CPU_CLEAR_DCS_PH3_RESET_MASK 0x00080000
-#define BCHP_AON_PM_L2_CPU_CLEAR_DCS_PH3_RESET_SHIFT 19
-#define BCHP_AON_PM_L2_CPU_CLEAR_DCS_PH3_RESET_DEFAULT 0x00000000
-
-/* AON_PM_L2 :: CPU_CLEAR :: FP_RESET [18:18] */
-#define BCHP_AON_PM_L2_CPU_CLEAR_FP_RESET_MASK 0x00040000
-#define BCHP_AON_PM_L2_CPU_CLEAR_FP_RESET_SHIFT 18
-#define BCHP_AON_PM_L2_CPU_CLEAR_FP_RESET_DEFAULT 0x00000000
-
-/* AON_PM_L2 :: CPU_CLEAR :: BOUNDARY_SCAN_REQ [17:17] */
-#define BCHP_AON_PM_L2_CPU_CLEAR_BOUNDARY_SCAN_REQ_MASK 0x00020000
-#define BCHP_AON_PM_L2_CPU_CLEAR_BOUNDARY_SCAN_REQ_SHIFT 17
-#define BCHP_AON_PM_L2_CPU_CLEAR_BOUNDARY_SCAN_REQ_DEFAULT 0x00000000
-
-/* AON_PM_L2 :: CPU_CLEAR :: DCS_HEADEND_INTR [16:16] */
-#define BCHP_AON_PM_L2_CPU_CLEAR_DCS_HEADEND_INTR_MASK 0x00010000
-#define BCHP_AON_PM_L2_CPU_CLEAR_DCS_HEADEND_INTR_SHIFT 16
-#define BCHP_AON_PM_L2_CPU_CLEAR_DCS_HEADEND_INTR_DEFAULT 0x00000000
-
-/* AON_PM_L2 :: CPU_CLEAR :: BMU_INTR_BATT_LOW [15:15] */
-#define BCHP_AON_PM_L2_CPU_CLEAR_BMU_INTR_BATT_LOW_MASK 0x00008000
-#define BCHP_AON_PM_L2_CPU_CLEAR_BMU_INTR_BATT_LOW_SHIFT 15
-#define BCHP_AON_PM_L2_CPU_CLEAR_BMU_INTR_BATT_LOW_DEFAULT 0x00000000
-
-/* AON_PM_L2 :: CPU_CLEAR :: BMU_INTR_AP_RESTORED [14:14] */
-#define BCHP_AON_PM_L2_CPU_CLEAR_BMU_INTR_AP_RESTORED_MASK 0x00004000
-#define BCHP_AON_PM_L2_CPU_CLEAR_BMU_INTR_AP_RESTORED_SHIFT 14
-#define BCHP_AON_PM_L2_CPU_CLEAR_BMU_INTR_AP_RESTORED_DEFAULT 0x00000000
-
-/* AON_PM_L2 :: CPU_CLEAR :: BMU_INTR_AP_LOST [13:13] */
-#define BCHP_AON_PM_L2_CPU_CLEAR_BMU_INTR_AP_LOST_MASK 0x00002000
-#define BCHP_AON_PM_L2_CPU_CLEAR_BMU_INTR_AP_LOST_SHIFT 13
-#define BCHP_AON_PM_L2_CPU_CLEAR_BMU_INTR_AP_LOST_DEFAULT 0x00000000
-
-/* AON_PM_L2 :: CPU_CLEAR :: USB0 [12:12] */
-#define BCHP_AON_PM_L2_CPU_CLEAR_USB0_MASK 0x00001000
-#define BCHP_AON_PM_L2_CPU_CLEAR_USB0_SHIFT 12
-#define BCHP_AON_PM_L2_CPU_CLEAR_USB0_DEFAULT 0x00000000
-
-/* AON_PM_L2 :: CPU_CLEAR :: MOCA [11:11] */
-#define BCHP_AON_PM_L2_CPU_CLEAR_MOCA_MASK 0x00000800
-#define BCHP_AON_PM_L2_CPU_CLEAR_MOCA_SHIFT 11
-#define BCHP_AON_PM_L2_CPU_CLEAR_MOCA_DEFAULT 0x00000000
-
-/* AON_PM_L2 :: CPU_CLEAR :: XPT_PMU [10:10] */
-#define BCHP_AON_PM_L2_CPU_CLEAR_XPT_PMU_MASK 0x00000400
-#define BCHP_AON_PM_L2_CPU_CLEAR_XPT_PMU_SHIFT 10
-#define BCHP_AON_PM_L2_CPU_CLEAR_XPT_PMU_DEFAULT 0x00000000
-
-/* AON_PM_L2 :: CPU_CLEAR :: CAP [09:09] */
-#define BCHP_AON_PM_L2_CPU_CLEAR_CAP_MASK 0x00000200
-#define BCHP_AON_PM_L2_CPU_CLEAR_CAP_SHIFT 9
-#define BCHP_AON_PM_L2_CPU_CLEAR_CAP_DEFAULT 0x00000000
-
-/* AON_PM_L2 :: CPU_CLEAR :: WOL_UNIMAC2 [08:08] */
-#define BCHP_AON_PM_L2_CPU_CLEAR_WOL_UNIMAC2_MASK 0x00000100
-#define BCHP_AON_PM_L2_CPU_CLEAR_WOL_UNIMAC2_SHIFT 8
-#define BCHP_AON_PM_L2_CPU_CLEAR_WOL_UNIMAC2_DEFAULT 0x00000000
-
-/* AON_PM_L2 :: CPU_CLEAR :: WOL_UNIMAC1 [07:07] */
-#define BCHP_AON_PM_L2_CPU_CLEAR_WOL_UNIMAC1_MASK 0x00000080
-#define BCHP_AON_PM_L2_CPU_CLEAR_WOL_UNIMAC1_SHIFT 7
-#define BCHP_AON_PM_L2_CPU_CLEAR_WOL_UNIMAC1_DEFAULT 0x00000000
-
-/* AON_PM_L2 :: CPU_CLEAR :: WOL_UNIMAC0 [06:06] */
-#define BCHP_AON_PM_L2_CPU_CLEAR_WOL_UNIMAC0_MASK 0x00000040
-#define BCHP_AON_PM_L2_CPU_CLEAR_WOL_UNIMAC0_SHIFT 6
-#define BCHP_AON_PM_L2_CPU_CLEAR_WOL_UNIMAC0_DEFAULT 0x00000000
-
-/* AON_PM_L2 :: CPU_CLEAR :: GPIO [05:05] */
-#define BCHP_AON_PM_L2_CPU_CLEAR_GPIO_MASK 0x00000020
-#define BCHP_AON_PM_L2_CPU_CLEAR_GPIO_SHIFT 5
-#define BCHP_AON_PM_L2_CPU_CLEAR_GPIO_DEFAULT 0x00000000
-
-/* AON_PM_L2 :: CPU_CLEAR :: NMI_B_INTR [04:04] */
-#define BCHP_AON_PM_L2_CPU_CLEAR_NMI_B_INTR_MASK 0x00000010
-#define BCHP_AON_PM_L2_CPU_CLEAR_NMI_B_INTR_SHIFT 4
-#define BCHP_AON_PM_L2_CPU_CLEAR_NMI_B_INTR_DEFAULT 0x00000000
-
-/* AON_PM_L2 :: CPU_CLEAR :: TIMER_INTR [03:03] */
-#define BCHP_AON_PM_L2_CPU_CLEAR_TIMER_INTR_MASK 0x00000008
-#define BCHP_AON_PM_L2_CPU_CLEAR_TIMER_INTR_SHIFT 3
-#define BCHP_AON_PM_L2_CPU_CLEAR_TIMER_INTR_DEFAULT 0x00000000
-
-/* AON_PM_L2 :: CPU_CLEAR :: KPD_INTR [02:02] */
-#define BCHP_AON_PM_L2_CPU_CLEAR_KPD_INTR_MASK 0x00000004
-#define BCHP_AON_PM_L2_CPU_CLEAR_KPD_INTR_SHIFT 2
-#define BCHP_AON_PM_L2_CPU_CLEAR_KPD_INTR_DEFAULT 0x00000000
-
-/* AON_PM_L2 :: CPU_CLEAR :: IRR_INTR [01:01] */
-#define BCHP_AON_PM_L2_CPU_CLEAR_IRR_INTR_MASK 0x00000002
-#define BCHP_AON_PM_L2_CPU_CLEAR_IRR_INTR_SHIFT 1
-#define BCHP_AON_PM_L2_CPU_CLEAR_IRR_INTR_DEFAULT 0x00000000
-
-/* AON_PM_L2 :: CPU_CLEAR :: CEC_INTR [00:00] */
-#define BCHP_AON_PM_L2_CPU_CLEAR_CEC_INTR_MASK 0x00000001
-#define BCHP_AON_PM_L2_CPU_CLEAR_CEC_INTR_SHIFT 0
-#define BCHP_AON_PM_L2_CPU_CLEAR_CEC_INTR_DEFAULT 0x00000000
-
-/***************************************************************************
- *CPU_MASK_STATUS - CPU interrupt Mask Status Register
- ***************************************************************************/
-/* AON_PM_L2 :: CPU_MASK_STATUS :: reserved0 [31:20] */
-#define BCHP_AON_PM_L2_CPU_MASK_STATUS_reserved0_MASK 0xfff00000
-#define BCHP_AON_PM_L2_CPU_MASK_STATUS_reserved0_SHIFT 20
-
-/* AON_PM_L2 :: CPU_MASK_STATUS :: DCS_PH3_RESET [19:19] */
-#define BCHP_AON_PM_L2_CPU_MASK_STATUS_DCS_PH3_RESET_MASK 0x00080000
-#define BCHP_AON_PM_L2_CPU_MASK_STATUS_DCS_PH3_RESET_SHIFT 19
-#define BCHP_AON_PM_L2_CPU_MASK_STATUS_DCS_PH3_RESET_DEFAULT 0x00000001
-
-/* AON_PM_L2 :: CPU_MASK_STATUS :: FP_RESET [18:18] */
-#define BCHP_AON_PM_L2_CPU_MASK_STATUS_FP_RESET_MASK 0x00040000
-#define BCHP_AON_PM_L2_CPU_MASK_STATUS_FP_RESET_SHIFT 18
-#define BCHP_AON_PM_L2_CPU_MASK_STATUS_FP_RESET_DEFAULT 0x00000001
-
-/* AON_PM_L2 :: CPU_MASK_STATUS :: BOUNDARY_SCAN_REQ [17:17] */
-#define BCHP_AON_PM_L2_CPU_MASK_STATUS_BOUNDARY_SCAN_REQ_MASK 0x00020000
-#define BCHP_AON_PM_L2_CPU_MASK_STATUS_BOUNDARY_SCAN_REQ_SHIFT 17
-#define BCHP_AON_PM_L2_CPU_MASK_STATUS_BOUNDARY_SCAN_REQ_DEFAULT 0x00000001
-
-/* AON_PM_L2 :: CPU_MASK_STATUS :: DCS_HEADEND_INTR [16:16] */
-#define BCHP_AON_PM_L2_CPU_MASK_STATUS_DCS_HEADEND_INTR_MASK 0x00010000
-#define BCHP_AON_PM_L2_CPU_MASK_STATUS_DCS_HEADEND_INTR_SHIFT 16
-#define BCHP_AON_PM_L2_CPU_MASK_STATUS_DCS_HEADEND_INTR_DEFAULT 0x00000001
-
-/* AON_PM_L2 :: CPU_MASK_STATUS :: BMU_INTR_BATT_LOW [15:15] */
-#define BCHP_AON_PM_L2_CPU_MASK_STATUS_BMU_INTR_BATT_LOW_MASK 0x00008000
-#define BCHP_AON_PM_L2_CPU_MASK_STATUS_BMU_INTR_BATT_LOW_SHIFT 15
-#define BCHP_AON_PM_L2_CPU_MASK_STATUS_BMU_INTR_BATT_LOW_DEFAULT 0x00000001
-
-/* AON_PM_L2 :: CPU_MASK_STATUS :: BMU_INTR_AP_RESTORED [14:14] */
-#define BCHP_AON_PM_L2_CPU_MASK_STATUS_BMU_INTR_AP_RESTORED_MASK 0x00004000
-#define BCHP_AON_PM_L2_CPU_MASK_STATUS_BMU_INTR_AP_RESTORED_SHIFT 14
-#define BCHP_AON_PM_L2_CPU_MASK_STATUS_BMU_INTR_AP_RESTORED_DEFAULT 0x00000001
-
-/* AON_PM_L2 :: CPU_MASK_STATUS :: BMU_INTR_AP_LOST [13:13] */
-#define BCHP_AON_PM_L2_CPU_MASK_STATUS_BMU_INTR_AP_LOST_MASK 0x00002000
-#define BCHP_AON_PM_L2_CPU_MASK_STATUS_BMU_INTR_AP_LOST_SHIFT 13
-#define BCHP_AON_PM_L2_CPU_MASK_STATUS_BMU_INTR_AP_LOST_DEFAULT 0x00000001
-
-/* AON_PM_L2 :: CPU_MASK_STATUS :: USB0 [12:12] */
-#define BCHP_AON_PM_L2_CPU_MASK_STATUS_USB0_MASK 0x00001000
-#define BCHP_AON_PM_L2_CPU_MASK_STATUS_USB0_SHIFT 12
-#define BCHP_AON_PM_L2_CPU_MASK_STATUS_USB0_DEFAULT 0x00000001
-
-/* AON_PM_L2 :: CPU_MASK_STATUS :: MOCA [11:11] */
-#define BCHP_AON_PM_L2_CPU_MASK_STATUS_MOCA_MASK 0x00000800
-#define BCHP_AON_PM_L2_CPU_MASK_STATUS_MOCA_SHIFT 11
-#define BCHP_AON_PM_L2_CPU_MASK_STATUS_MOCA_DEFAULT 0x00000001
-
-/* AON_PM_L2 :: CPU_MASK_STATUS :: XPT_PMU [10:10] */
-#define BCHP_AON_PM_L2_CPU_MASK_STATUS_XPT_PMU_MASK 0x00000400
-#define BCHP_AON_PM_L2_CPU_MASK_STATUS_XPT_PMU_SHIFT 10
-#define BCHP_AON_PM_L2_CPU_MASK_STATUS_XPT_PMU_DEFAULT 0x00000001
-
-/* AON_PM_L2 :: CPU_MASK_STATUS :: CAP [09:09] */
-#define BCHP_AON_PM_L2_CPU_MASK_STATUS_CAP_MASK 0x00000200
-#define BCHP_AON_PM_L2_CPU_MASK_STATUS_CAP_SHIFT 9
-#define BCHP_AON_PM_L2_CPU_MASK_STATUS_CAP_DEFAULT 0x00000001
-
-/* AON_PM_L2 :: CPU_MASK_STATUS :: WOL_GENET2 [08:08] */
-#define BCHP_AON_PM_L2_CPU_MASK_STATUS_WOL_GENET2_MASK 0x00000100
-#define BCHP_AON_PM_L2_CPU_MASK_STATUS_WOL_GENET2_SHIFT 8
-#define BCHP_AON_PM_L2_CPU_MASK_STATUS_WOL_GENET2_DEFAULT 0x00000001
-
-/* AON_PM_L2 :: CPU_MASK_STATUS :: WOL_GENET1 [07:07] */
-#define BCHP_AON_PM_L2_CPU_MASK_STATUS_WOL_GENET1_MASK 0x00000080
-#define BCHP_AON_PM_L2_CPU_MASK_STATUS_WOL_GENET1_SHIFT 7
-#define BCHP_AON_PM_L2_CPU_MASK_STATUS_WOL_GENET1_DEFAULT 0x00000001
-
-/* AON_PM_L2 :: CPU_MASK_STATUS :: WOL_GENET0 [06:06] */
-#define BCHP_AON_PM_L2_CPU_MASK_STATUS_WOL_GENET0_MASK 0x00000040
-#define BCHP_AON_PM_L2_CPU_MASK_STATUS_WOL_GENET0_SHIFT 6
-#define BCHP_AON_PM_L2_CPU_MASK_STATUS_WOL_GENET0_DEFAULT 0x00000001
-
-/* AON_PM_L2 :: CPU_MASK_STATUS :: GPIO [05:05] */
-#define BCHP_AON_PM_L2_CPU_MASK_STATUS_GPIO_MASK 0x00000020
-#define BCHP_AON_PM_L2_CPU_MASK_STATUS_GPIO_SHIFT 5
-#define BCHP_AON_PM_L2_CPU_MASK_STATUS_GPIO_DEFAULT 0x00000001
-
-/* AON_PM_L2 :: CPU_MASK_STATUS :: NMI_B_INTR [04:04] */
-#define BCHP_AON_PM_L2_CPU_MASK_STATUS_NMI_B_INTR_MASK 0x00000010
-#define BCHP_AON_PM_L2_CPU_MASK_STATUS_NMI_B_INTR_SHIFT 4
-#define BCHP_AON_PM_L2_CPU_MASK_STATUS_NMI_B_INTR_DEFAULT 0x00000001
-
-/* AON_PM_L2 :: CPU_MASK_STATUS :: TIMER_INTR [03:03] */
-#define BCHP_AON_PM_L2_CPU_MASK_STATUS_TIMER_INTR_MASK 0x00000008
-#define BCHP_AON_PM_L2_CPU_MASK_STATUS_TIMER_INTR_SHIFT 3
-#define BCHP_AON_PM_L2_CPU_MASK_STATUS_TIMER_INTR_DEFAULT 0x00000001
-
-/* AON_PM_L2 :: CPU_MASK_STATUS :: KPD_INTR [02:02] */
-#define BCHP_AON_PM_L2_CPU_MASK_STATUS_KPD_INTR_MASK 0x00000004
-#define BCHP_AON_PM_L2_CPU_MASK_STATUS_KPD_INTR_SHIFT 2
-#define BCHP_AON_PM_L2_CPU_MASK_STATUS_KPD_INTR_DEFAULT 0x00000001
-
-/* AON_PM_L2 :: CPU_MASK_STATUS :: IRR_INTR [01:01] */
-#define BCHP_AON_PM_L2_CPU_MASK_STATUS_IRR_INTR_MASK 0x00000002
-#define BCHP_AON_PM_L2_CPU_MASK_STATUS_IRR_INTR_SHIFT 1
-#define BCHP_AON_PM_L2_CPU_MASK_STATUS_IRR_INTR_DEFAULT 0x00000001
-
-/* AON_PM_L2 :: CPU_MASK_STATUS :: CEC_INTR [00:00] */
-#define BCHP_AON_PM_L2_CPU_MASK_STATUS_CEC_INTR_MASK 0x00000001
-#define BCHP_AON_PM_L2_CPU_MASK_STATUS_CEC_INTR_SHIFT 0
-#define BCHP_AON_PM_L2_CPU_MASK_STATUS_CEC_INTR_DEFAULT 0x00000001
-
-/***************************************************************************
- *CPU_MASK_SET - CPU interrupt Mask Set Register
- ***************************************************************************/
-/* AON_PM_L2 :: CPU_MASK_SET :: reserved0 [31:20] */
-#define BCHP_AON_PM_L2_CPU_MASK_SET_reserved0_MASK 0xfff00000
-#define BCHP_AON_PM_L2_CPU_MASK_SET_reserved0_SHIFT 20
-
-/* AON_PM_L2 :: CPU_MASK_SET :: DCS_PH3_RESET [19:19] */
-#define BCHP_AON_PM_L2_CPU_MASK_SET_DCS_PH3_RESET_MASK 0x00080000
-#define BCHP_AON_PM_L2_CPU_MASK_SET_DCS_PH3_RESET_SHIFT 19
-#define BCHP_AON_PM_L2_CPU_MASK_SET_DCS_PH3_RESET_DEFAULT 0x00000001
-
-/* AON_PM_L2 :: CPU_MASK_SET :: FP_RESET [18:18] */
-#define BCHP_AON_PM_L2_CPU_MASK_SET_FP_RESET_MASK 0x00040000
-#define BCHP_AON_PM_L2_CPU_MASK_SET_FP_RESET_SHIFT 18
-#define BCHP_AON_PM_L2_CPU_MASK_SET_FP_RESET_DEFAULT 0x00000001
-
-/* AON_PM_L2 :: CPU_MASK_SET :: BOUNDARY_SCAN_REQ [17:17] */
-#define BCHP_AON_PM_L2_CPU_MASK_SET_BOUNDARY_SCAN_REQ_MASK 0x00020000
-#define BCHP_AON_PM_L2_CPU_MASK_SET_BOUNDARY_SCAN_REQ_SHIFT 17
-#define BCHP_AON_PM_L2_CPU_MASK_SET_BOUNDARY_SCAN_REQ_DEFAULT 0x00000001
-
-/* AON_PM_L2 :: CPU_MASK_SET :: DCS_HEADEND_INTR [16:16] */
-#define BCHP_AON_PM_L2_CPU_MASK_SET_DCS_HEADEND_INTR_MASK 0x00010000
-#define BCHP_AON_PM_L2_CPU_MASK_SET_DCS_HEADEND_INTR_SHIFT 16
-#define BCHP_AON_PM_L2_CPU_MASK_SET_DCS_HEADEND_INTR_DEFAULT 0x00000001
-
-/* AON_PM_L2 :: CPU_MASK_SET :: BMU_INTR_BATT_LOW [15:15] */
-#define BCHP_AON_PM_L2_CPU_MASK_SET_BMU_INTR_BATT_LOW_MASK 0x00008000
-#define BCHP_AON_PM_L2_CPU_MASK_SET_BMU_INTR_BATT_LOW_SHIFT 15
-#define BCHP_AON_PM_L2_CPU_MASK_SET_BMU_INTR_BATT_LOW_DEFAULT 0x00000001
-
-/* AON_PM_L2 :: CPU_MASK_SET :: BMU_INTR_AP_RESTORED [14:14] */
-#define BCHP_AON_PM_L2_CPU_MASK_SET_BMU_INTR_AP_RESTORED_MASK 0x00004000
-#define BCHP_AON_PM_L2_CPU_MASK_SET_BMU_INTR_AP_RESTORED_SHIFT 14
-#define BCHP_AON_PM_L2_CPU_MASK_SET_BMU_INTR_AP_RESTORED_DEFAULT 0x00000001
-
-/* AON_PM_L2 :: CPU_MASK_SET :: BMU_INTR_AP_LOST [13:13] */
-#define BCHP_AON_PM_L2_CPU_MASK_SET_BMU_INTR_AP_LOST_MASK 0x00002000
-#define BCHP_AON_PM_L2_CPU_MASK_SET_BMU_INTR_AP_LOST_SHIFT 13
-#define BCHP_AON_PM_L2_CPU_MASK_SET_BMU_INTR_AP_LOST_DEFAULT 0x00000001
-
-/* AON_PM_L2 :: CPU_MASK_SET :: USB0 [12:12] */
-#define BCHP_AON_PM_L2_CPU_MASK_SET_USB0_MASK 0x00001000
-#define BCHP_AON_PM_L2_CPU_MASK_SET_USB0_SHIFT 12
-#define BCHP_AON_PM_L2_CPU_MASK_SET_USB0_DEFAULT 0x00000001
-
-/* AON_PM_L2 :: CPU_MASK_SET :: MOCA [11:11] */
-#define BCHP_AON_PM_L2_CPU_MASK_SET_MOCA_MASK 0x00000800
-#define BCHP_AON_PM_L2_CPU_MASK_SET_MOCA_SHIFT 11
-#define BCHP_AON_PM_L2_CPU_MASK_SET_MOCA_DEFAULT 0x00000001
-
-/* AON_PM_L2 :: CPU_MASK_SET :: XPT_PMU [10:10] */
-#define BCHP_AON_PM_L2_CPU_MASK_SET_XPT_PMU_MASK 0x00000400
-#define BCHP_AON_PM_L2_CPU_MASK_SET_XPT_PMU_SHIFT 10
-#define BCHP_AON_PM_L2_CPU_MASK_SET_XPT_PMU_DEFAULT 0x00000001
-
-/* AON_PM_L2 :: CPU_MASK_SET :: CAP [09:09] */
-#define BCHP_AON_PM_L2_CPU_MASK_SET_CAP_MASK 0x00000200
-#define BCHP_AON_PM_L2_CPU_MASK_SET_CAP_SHIFT 9
-#define BCHP_AON_PM_L2_CPU_MASK_SET_CAP_DEFAULT 0x00000001
-
-/* AON_PM_L2 :: CPU_MASK_SET :: WOL_GENET2 [08:08] */
-#define BCHP_AON_PM_L2_CPU_MASK_SET_WOL_GENET2_MASK 0x00000100
-#define BCHP_AON_PM_L2_CPU_MASK_SET_WOL_GENET2_SHIFT 8
-#define BCHP_AON_PM_L2_CPU_MASK_SET_WOL_GENET2_DEFAULT 0x00000001
-
-/* AON_PM_L2 :: CPU_MASK_SET :: WOL_GENET1 [07:07] */
-#define BCHP_AON_PM_L2_CPU_MASK_SET_WOL_GENET1_MASK 0x00000080
-#define BCHP_AON_PM_L2_CPU_MASK_SET_WOL_GENET1_SHIFT 7
-#define BCHP_AON_PM_L2_CPU_MASK_SET_WOL_GENET1_DEFAULT 0x00000001
-
-/* AON_PM_L2 :: CPU_MASK_SET :: WOL_GENET0 [06:06] */
-#define BCHP_AON_PM_L2_CPU_MASK_SET_WOL_GENET0_MASK 0x00000040
-#define BCHP_AON_PM_L2_CPU_MASK_SET_WOL_GENET0_SHIFT 6
-#define BCHP_AON_PM_L2_CPU_MASK_SET_WOL_GENET0_DEFAULT 0x00000001
-
-/* AON_PM_L2 :: CPU_MASK_SET :: GPIO [05:05] */
-#define BCHP_AON_PM_L2_CPU_MASK_SET_GPIO_MASK 0x00000020
-#define BCHP_AON_PM_L2_CPU_MASK_SET_GPIO_SHIFT 5
-#define BCHP_AON_PM_L2_CPU_MASK_SET_GPIO_DEFAULT 0x00000001
-
-/* AON_PM_L2 :: CPU_MASK_SET :: NMI_B_INTR [04:04] */
-#define BCHP_AON_PM_L2_CPU_MASK_SET_NMI_B_INTR_MASK 0x00000010
-#define BCHP_AON_PM_L2_CPU_MASK_SET_NMI_B_INTR_SHIFT 4
-#define BCHP_AON_PM_L2_CPU_MASK_SET_NMI_B_INTR_DEFAULT 0x00000001
-
-/* AON_PM_L2 :: CPU_MASK_SET :: TIMER_INTR [03:03] */
-#define BCHP_AON_PM_L2_CPU_MASK_SET_TIMER_INTR_MASK 0x00000008
-#define BCHP_AON_PM_L2_CPU_MASK_SET_TIMER_INTR_SHIFT 3
-#define BCHP_AON_PM_L2_CPU_MASK_SET_TIMER_INTR_DEFAULT 0x00000001
-
-/* AON_PM_L2 :: CPU_MASK_SET :: KPD_INTR [02:02] */
-#define BCHP_AON_PM_L2_CPU_MASK_SET_KPD_INTR_MASK 0x00000004
-#define BCHP_AON_PM_L2_CPU_MASK_SET_KPD_INTR_SHIFT 2
-#define BCHP_AON_PM_L2_CPU_MASK_SET_KPD_INTR_DEFAULT 0x00000001
-
-/* AON_PM_L2 :: CPU_MASK_SET :: IRR_INTR [01:01] */
-#define BCHP_AON_PM_L2_CPU_MASK_SET_IRR_INTR_MASK 0x00000002
-#define BCHP_AON_PM_L2_CPU_MASK_SET_IRR_INTR_SHIFT 1
-#define BCHP_AON_PM_L2_CPU_MASK_SET_IRR_INTR_DEFAULT 0x00000001
-
-/* AON_PM_L2 :: CPU_MASK_SET :: CEC_INTR [00:00] */
-#define BCHP_AON_PM_L2_CPU_MASK_SET_CEC_INTR_MASK 0x00000001
-#define BCHP_AON_PM_L2_CPU_MASK_SET_CEC_INTR_SHIFT 0
-#define BCHP_AON_PM_L2_CPU_MASK_SET_CEC_INTR_DEFAULT 0x00000001
-
-/***************************************************************************
- *CPU_MASK_CLEAR - CPU interrupt Mask Clear Register
- ***************************************************************************/
-/* AON_PM_L2 :: CPU_MASK_CLEAR :: reserved0 [31:20] */
-#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_reserved0_MASK 0xfff00000
-#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_reserved0_SHIFT 20
-
-/* AON_PM_L2 :: CPU_MASK_CLEAR :: DCS_PH3_RESET [19:19] */
-#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_DCS_PH3_RESET_MASK 0x00080000
-#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_DCS_PH3_RESET_SHIFT 19
-#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_DCS_PH3_RESET_DEFAULT 0x00000001
-
-/* AON_PM_L2 :: CPU_MASK_CLEAR :: FP_RESET [18:18] */
-#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_FP_RESET_MASK 0x00040000
-#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_FP_RESET_SHIFT 18
-#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_FP_RESET_DEFAULT 0x00000001
-
-/* AON_PM_L2 :: CPU_MASK_CLEAR :: BOUNDARY_SCAN_REQ [17:17] */
-#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_BOUNDARY_SCAN_REQ_MASK 0x00020000
-#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_BOUNDARY_SCAN_REQ_SHIFT 17
-#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_BOUNDARY_SCAN_REQ_DEFAULT 0x00000001
-
-/* AON_PM_L2 :: CPU_MASK_CLEAR :: DCS_HEADEND_INTR [16:16] */
-#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_DCS_HEADEND_INTR_MASK 0x00010000
-#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_DCS_HEADEND_INTR_SHIFT 16
-#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_DCS_HEADEND_INTR_DEFAULT 0x00000001
-
-/* AON_PM_L2 :: CPU_MASK_CLEAR :: BMU_INTR_BATT_LOW [15:15] */
-#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_BMU_INTR_BATT_LOW_MASK 0x00008000
-#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_BMU_INTR_BATT_LOW_SHIFT 15
-#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_BMU_INTR_BATT_LOW_DEFAULT 0x00000001
-
-/* AON_PM_L2 :: CPU_MASK_CLEAR :: BMU_INTR_AP_RESTORED [14:14] */
-#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_BMU_INTR_AP_RESTORED_MASK 0x00004000
-#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_BMU_INTR_AP_RESTORED_SHIFT 14
-#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_BMU_INTR_AP_RESTORED_DEFAULT 0x00000001
-
-/* AON_PM_L2 :: CPU_MASK_CLEAR :: BMU_INTR_AP_LOST [13:13] */
-#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_BMU_INTR_AP_LOST_MASK 0x00002000
-#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_BMU_INTR_AP_LOST_SHIFT 13
-#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_BMU_INTR_AP_LOST_DEFAULT 0x00000001
-
-/* AON_PM_L2 :: CPU_MASK_CLEAR :: USB0 [12:12] */
-#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_USB0_MASK 0x00001000
-#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_USB0_SHIFT 12
-#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_USB0_DEFAULT 0x00000001
-
-/* AON_PM_L2 :: CPU_MASK_CLEAR :: MOCA [11:11] */
-#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_MOCA_MASK 0x00000800
-#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_MOCA_SHIFT 11
-#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_MOCA_DEFAULT 0x00000001
-
-/* AON_PM_L2 :: CPU_MASK_CLEAR :: XPT_PMU [10:10] */
-#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_XPT_PMU_MASK 0x00000400
-#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_XPT_PMU_SHIFT 10
-#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_XPT_PMU_DEFAULT 0x00000001
-
-/* AON_PM_L2 :: CPU_MASK_CLEAR :: CAP [09:09] */
-#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_CAP_MASK 0x00000200
-#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_CAP_SHIFT 9
-#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_CAP_DEFAULT 0x00000001
-
-/* AON_PM_L2 :: CPU_MASK_CLEAR :: WOL_GENET2 [08:08] */
-#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_WOL_GENET2_MASK 0x00000100
-#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_WOL_GENET2_SHIFT 8
-#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_WOL_GENET2_DEFAULT 0x00000001
-
-/* AON_PM_L2 :: CPU_MASK_CLEAR :: WOL_GENET1 [07:07] */
-#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_WOL_GENET1_MASK 0x00000080
-#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_WOL_GENET1_SHIFT 7
-#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_WOL_GENET1_DEFAULT 0x00000001
-
-/* AON_PM_L2 :: CPU_MASK_CLEAR :: WOL_GENET0 [06:06] */
-#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_WOL_GENET0_MASK 0x00000040
-#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_WOL_GENET0_SHIFT 6
-#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_WOL_GENET0_DEFAULT 0x00000001
-
-/* AON_PM_L2 :: CPU_MASK_CLEAR :: GPIO [05:05] */
-#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_GPIO_MASK 0x00000020
-#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_GPIO_SHIFT 5
-#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_GPIO_DEFAULT 0x00000001
-
-/* AON_PM_L2 :: CPU_MASK_CLEAR :: NMI_B_INTR [04:04] */
-#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_NMI_B_INTR_MASK 0x00000010
-#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_NMI_B_INTR_SHIFT 4
-#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_NMI_B_INTR_DEFAULT 0x00000001
-
-/* AON_PM_L2 :: CPU_MASK_CLEAR :: TIMER_INTR [03:03] */
-#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_TIMER_INTR_MASK 0x00000008
-#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_TIMER_INTR_SHIFT 3
-#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_TIMER_INTR_DEFAULT 0x00000001
-
-/* AON_PM_L2 :: CPU_MASK_CLEAR :: KPD_INTR [02:02] */
-#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_KPD_INTR_MASK 0x00000004
-#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_KPD_INTR_SHIFT 2
-#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_KPD_INTR_DEFAULT 0x00000001
-
-/* AON_PM_L2 :: CPU_MASK_CLEAR :: IRR_INTR [01:01] */
-#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_IRR_INTR_MASK 0x00000002
-#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_IRR_INTR_SHIFT 1
-#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_IRR_INTR_DEFAULT 0x00000001
-
-/* AON_PM_L2 :: CPU_MASK_CLEAR :: CEC_INTR [00:00] */
-#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_CEC_INTR_MASK 0x00000001
-#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_CEC_INTR_SHIFT 0
-#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_CEC_INTR_DEFAULT 0x00000001
-
-/***************************************************************************
- *PCI_STATUS - PCI interrupt Status Register
- ***************************************************************************/
-/* AON_PM_L2 :: PCI_STATUS :: reserved0 [31:20] */
-#define BCHP_AON_PM_L2_PCI_STATUS_reserved0_MASK 0xfff00000
-#define BCHP_AON_PM_L2_PCI_STATUS_reserved0_SHIFT 20
-
-/* AON_PM_L2 :: PCI_STATUS :: DCS_PH3_RESET [19:19] */
-#define BCHP_AON_PM_L2_PCI_STATUS_DCS_PH3_RESET_MASK 0x00080000
-#define BCHP_AON_PM_L2_PCI_STATUS_DCS_PH3_RESET_SHIFT 19
-#define BCHP_AON_PM_L2_PCI_STATUS_DCS_PH3_RESET_DEFAULT 0x00000000
-
-/* AON_PM_L2 :: PCI_STATUS :: FP_RESET [18:18] */
-#define BCHP_AON_PM_L2_PCI_STATUS_FP_RESET_MASK 0x00040000
-#define BCHP_AON_PM_L2_PCI_STATUS_FP_RESET_SHIFT 18
-#define BCHP_AON_PM_L2_PCI_STATUS_FP_RESET_DEFAULT 0x00000000
-
-/* AON_PM_L2 :: PCI_STATUS :: BOUNDARY_SCAN_REQ [17:17] */
-#define BCHP_AON_PM_L2_PCI_STATUS_BOUNDARY_SCAN_REQ_MASK 0x00020000
-#define BCHP_AON_PM_L2_PCI_STATUS_BOUNDARY_SCAN_REQ_SHIFT 17
-#define BCHP_AON_PM_L2_PCI_STATUS_BOUNDARY_SCAN_REQ_DEFAULT 0x00000000
-
-/* AON_PM_L2 :: PCI_STATUS :: DCS_HEADEND_INTR [16:16] */
-#define BCHP_AON_PM_L2_PCI_STATUS_DCS_HEADEND_INTR_MASK 0x00010000
-#define BCHP_AON_PM_L2_PCI_STATUS_DCS_HEADEND_INTR_SHIFT 16
-#define BCHP_AON_PM_L2_PCI_STATUS_DCS_HEADEND_INTR_DEFAULT 0x00000000
-
-/* AON_PM_L2 :: PCI_STATUS :: BMU_INTR_BATT_LOW [15:15] */
-#define BCHP_AON_PM_L2_PCI_STATUS_BMU_INTR_BATT_LOW_MASK 0x00008000
-#define BCHP_AON_PM_L2_PCI_STATUS_BMU_INTR_BATT_LOW_SHIFT 15
-#define BCHP_AON_PM_L2_PCI_STATUS_BMU_INTR_BATT_LOW_DEFAULT 0x00000000
-
-/* AON_PM_L2 :: PCI_STATUS :: BMU_INTR_AP_RESTORED [14:14] */
-#define BCHP_AON_PM_L2_PCI_STATUS_BMU_INTR_AP_RESTORED_MASK 0x00004000
-#define BCHP_AON_PM_L2_PCI_STATUS_BMU_INTR_AP_RESTORED_SHIFT 14
-#define BCHP_AON_PM_L2_PCI_STATUS_BMU_INTR_AP_RESTORED_DEFAULT 0x00000000
-
-/* AON_PM_L2 :: PCI_STATUS :: BMU_INTR_AP_LOST [13:13] */
-#define BCHP_AON_PM_L2_PCI_STATUS_BMU_INTR_AP_LOST_MASK 0x00002000
-#define BCHP_AON_PM_L2_PCI_STATUS_BMU_INTR_AP_LOST_SHIFT 13
-#define BCHP_AON_PM_L2_PCI_STATUS_BMU_INTR_AP_LOST_DEFAULT 0x00000000
-
-/* AON_PM_L2 :: PCI_STATUS :: USB0 [12:12] */
-#define BCHP_AON_PM_L2_PCI_STATUS_USB0_MASK 0x00001000
-#define BCHP_AON_PM_L2_PCI_STATUS_USB0_SHIFT 12
-#define BCHP_AON_PM_L2_PCI_STATUS_USB0_DEFAULT 0x00000000
-
-/* AON_PM_L2 :: PCI_STATUS :: MOCA [11:11] */
-#define BCHP_AON_PM_L2_PCI_STATUS_MOCA_MASK 0x00000800
-#define BCHP_AON_PM_L2_PCI_STATUS_MOCA_SHIFT 11
-#define BCHP_AON_PM_L2_PCI_STATUS_MOCA_DEFAULT 0x00000000
-
-/* AON_PM_L2 :: PCI_STATUS :: XPT_PMU [10:10] */
-#define BCHP_AON_PM_L2_PCI_STATUS_XPT_PMU_MASK 0x00000400
-#define BCHP_AON_PM_L2_PCI_STATUS_XPT_PMU_SHIFT 10
-#define BCHP_AON_PM_L2_PCI_STATUS_XPT_PMU_DEFAULT 0x00000000
-
-/* AON_PM_L2 :: PCI_STATUS :: CAP [09:09] */
-#define BCHP_AON_PM_L2_PCI_STATUS_CAP_MASK 0x00000200
-#define BCHP_AON_PM_L2_PCI_STATUS_CAP_SHIFT 9
-#define BCHP_AON_PM_L2_PCI_STATUS_CAP_DEFAULT 0x00000000
-
-/* AON_PM_L2 :: PCI_STATUS :: WOL_UNIMAC2 [08:08] */
-#define BCHP_AON_PM_L2_PCI_STATUS_WOL_UNIMAC2_MASK 0x00000100
-#define BCHP_AON_PM_L2_PCI_STATUS_WOL_UNIMAC2_SHIFT 8
-#define BCHP_AON_PM_L2_PCI_STATUS_WOL_UNIMAC2_DEFAULT 0x00000000
-
-/* AON_PM_L2 :: PCI_STATUS :: WOL_UNIMAC1 [07:07] */
-#define BCHP_AON_PM_L2_PCI_STATUS_WOL_UNIMAC1_MASK 0x00000080
-#define BCHP_AON_PM_L2_PCI_STATUS_WOL_UNIMAC1_SHIFT 7
-#define BCHP_AON_PM_L2_PCI_STATUS_WOL_UNIMAC1_DEFAULT 0x00000000
-
-/* AON_PM_L2 :: PCI_STATUS :: WOL_UNIMAC0 [06:06] */
-#define BCHP_AON_PM_L2_PCI_STATUS_WOL_UNIMAC0_MASK 0x00000040
-#define BCHP_AON_PM_L2_PCI_STATUS_WOL_UNIMAC0_SHIFT 6
-#define BCHP_AON_PM_L2_PCI_STATUS_WOL_UNIMAC0_DEFAULT 0x00000000
-
-/* AON_PM_L2 :: PCI_STATUS :: GPIO [05:05] */
-#define BCHP_AON_PM_L2_PCI_STATUS_GPIO_MASK 0x00000020
-#define BCHP_AON_PM_L2_PCI_STATUS_GPIO_SHIFT 5
-#define BCHP_AON_PM_L2_PCI_STATUS_GPIO_DEFAULT 0x00000000
-
-/* AON_PM_L2 :: PCI_STATUS :: NMI_B_INTR [04:04] */
-#define BCHP_AON_PM_L2_PCI_STATUS_NMI_B_INTR_MASK 0x00000010
-#define BCHP_AON_PM_L2_PCI_STATUS_NMI_B_INTR_SHIFT 4
-#define BCHP_AON_PM_L2_PCI_STATUS_NMI_B_INTR_DEFAULT 0x00000000
-
-/* AON_PM_L2 :: PCI_STATUS :: TIMER_INTR [03:03] */
-#define BCHP_AON_PM_L2_PCI_STATUS_TIMER_INTR_MASK 0x00000008
-#define BCHP_AON_PM_L2_PCI_STATUS_TIMER_INTR_SHIFT 3
-#define BCHP_AON_PM_L2_PCI_STATUS_TIMER_INTR_DEFAULT 0x00000000
-
-/* AON_PM_L2 :: PCI_STATUS :: KPD_INTR [02:02] */
-#define BCHP_AON_PM_L2_PCI_STATUS_KPD_INTR_MASK 0x00000004
-#define BCHP_AON_PM_L2_PCI_STATUS_KPD_INTR_SHIFT 2
-#define BCHP_AON_PM_L2_PCI_STATUS_KPD_INTR_DEFAULT 0x00000000
-
-/* AON_PM_L2 :: PCI_STATUS :: IRR_INTR [01:01] */
-#define BCHP_AON_PM_L2_PCI_STATUS_IRR_INTR_MASK 0x00000002
-#define BCHP_AON_PM_L2_PCI_STATUS_IRR_INTR_SHIFT 1
-#define BCHP_AON_PM_L2_PCI_STATUS_IRR_INTR_DEFAULT 0x00000000
-
-/* AON_PM_L2 :: PCI_STATUS :: CEC_INTR [00:00] */
-#define BCHP_AON_PM_L2_PCI_STATUS_CEC_INTR_MASK 0x00000001
-#define BCHP_AON_PM_L2_PCI_STATUS_CEC_INTR_SHIFT 0
-#define BCHP_AON_PM_L2_PCI_STATUS_CEC_INTR_DEFAULT 0x00000000
-
-/***************************************************************************
- *PCI_SET - PCI interrupt Set Register
- ***************************************************************************/
-/* AON_PM_L2 :: PCI_SET :: reserved0 [31:20] */
-#define BCHP_AON_PM_L2_PCI_SET_reserved0_MASK 0xfff00000
-#define BCHP_AON_PM_L2_PCI_SET_reserved0_SHIFT 20
-
-/* AON_PM_L2 :: PCI_SET :: DCS_PH3_RESET [19:19] */
-#define BCHP_AON_PM_L2_PCI_SET_DCS_PH3_RESET_MASK 0x00080000
-#define BCHP_AON_PM_L2_PCI_SET_DCS_PH3_RESET_SHIFT 19
-#define BCHP_AON_PM_L2_PCI_SET_DCS_PH3_RESET_DEFAULT 0x00000000
-
-/* AON_PM_L2 :: PCI_SET :: FP_RESET [18:18] */
-#define BCHP_AON_PM_L2_PCI_SET_FP_RESET_MASK 0x00040000
-#define BCHP_AON_PM_L2_PCI_SET_FP_RESET_SHIFT 18
-#define BCHP_AON_PM_L2_PCI_SET_FP_RESET_DEFAULT 0x00000000
-
-/* AON_PM_L2 :: PCI_SET :: BOUNDARY_SCAN_REQ [17:17] */
-#define BCHP_AON_PM_L2_PCI_SET_BOUNDARY_SCAN_REQ_MASK 0x00020000
-#define BCHP_AON_PM_L2_PCI_SET_BOUNDARY_SCAN_REQ_SHIFT 17
-#define BCHP_AON_PM_L2_PCI_SET_BOUNDARY_SCAN_REQ_DEFAULT 0x00000000
-
-/* AON_PM_L2 :: PCI_SET :: DCS_HEADEND_INTR [16:16] */
-#define BCHP_AON_PM_L2_PCI_SET_DCS_HEADEND_INTR_MASK 0x00010000
-#define BCHP_AON_PM_L2_PCI_SET_DCS_HEADEND_INTR_SHIFT 16
-#define BCHP_AON_PM_L2_PCI_SET_DCS_HEADEND_INTR_DEFAULT 0x00000000
-
-/* AON_PM_L2 :: PCI_SET :: BMU_INTR_BATT_LOW [15:15] */
-#define BCHP_AON_PM_L2_PCI_SET_BMU_INTR_BATT_LOW_MASK 0x00008000
-#define BCHP_AON_PM_L2_PCI_SET_BMU_INTR_BATT_LOW_SHIFT 15
-#define BCHP_AON_PM_L2_PCI_SET_BMU_INTR_BATT_LOW_DEFAULT 0x00000000
-
-/* AON_PM_L2 :: PCI_SET :: BMU_INTR_AP_RESTORED [14:14] */
-#define BCHP_AON_PM_L2_PCI_SET_BMU_INTR_AP_RESTORED_MASK 0x00004000
-#define BCHP_AON_PM_L2_PCI_SET_BMU_INTR_AP_RESTORED_SHIFT 14
-#define BCHP_AON_PM_L2_PCI_SET_BMU_INTR_AP_RESTORED_DEFAULT 0x00000000
-
-/* AON_PM_L2 :: PCI_SET :: BMU_INTR_AP_LOST [13:13] */
-#define BCHP_AON_PM_L2_PCI_SET_BMU_INTR_AP_LOST_MASK 0x00002000
-#define BCHP_AON_PM_L2_PCI_SET_BMU_INTR_AP_LOST_SHIFT 13
-#define BCHP_AON_PM_L2_PCI_SET_BMU_INTR_AP_LOST_DEFAULT 0x00000000
-
-/* AON_PM_L2 :: PCI_SET :: USB0 [12:12] */
-#define BCHP_AON_PM_L2_PCI_SET_USB0_MASK 0x00001000
-#define BCHP_AON_PM_L2_PCI_SET_USB0_SHIFT 12
-#define BCHP_AON_PM_L2_PCI_SET_USB0_DEFAULT 0x00000000
-
-/* AON_PM_L2 :: PCI_SET :: MOCA [11:11] */
-#define BCHP_AON_PM_L2_PCI_SET_MOCA_MASK 0x00000800
-#define BCHP_AON_PM_L2_PCI_SET_MOCA_SHIFT 11
-#define BCHP_AON_PM_L2_PCI_SET_MOCA_DEFAULT 0x00000000
-
-/* AON_PM_L2 :: PCI_SET :: XPT_PMU [10:10] */
-#define BCHP_AON_PM_L2_PCI_SET_XPT_PMU_MASK 0x00000400
-#define BCHP_AON_PM_L2_PCI_SET_XPT_PMU_SHIFT 10
-#define BCHP_AON_PM_L2_PCI_SET_XPT_PMU_DEFAULT 0x00000000
-
-/* AON_PM_L2 :: PCI_SET :: CAP [09:09] */
-#define BCHP_AON_PM_L2_PCI_SET_CAP_MASK 0x00000200
-#define BCHP_AON_PM_L2_PCI_SET_CAP_SHIFT 9
-#define BCHP_AON_PM_L2_PCI_SET_CAP_DEFAULT 0x00000000
-
-/* AON_PM_L2 :: PCI_SET :: WOL_UNIMAC2 [08:08] */
-#define BCHP_AON_PM_L2_PCI_SET_WOL_UNIMAC2_MASK 0x00000100
-#define BCHP_AON_PM_L2_PCI_SET_WOL_UNIMAC2_SHIFT 8
-#define BCHP_AON_PM_L2_PCI_SET_WOL_UNIMAC2_DEFAULT 0x00000000
-
-/* AON_PM_L2 :: PCI_SET :: WOL_UNIMAC1 [07:07] */
-#define BCHP_AON_PM_L2_PCI_SET_WOL_UNIMAC1_MASK 0x00000080
-#define BCHP_AON_PM_L2_PCI_SET_WOL_UNIMAC1_SHIFT 7
-#define BCHP_AON_PM_L2_PCI_SET_WOL_UNIMAC1_DEFAULT 0x00000000
-
-/* AON_PM_L2 :: PCI_SET :: WOL_UNIMAC0 [06:06] */
-#define BCHP_AON_PM_L2_PCI_SET_WOL_UNIMAC0_MASK 0x00000040
-#define BCHP_AON_PM_L2_PCI_SET_WOL_UNIMAC0_SHIFT 6
-#define BCHP_AON_PM_L2_PCI_SET_WOL_UNIMAC0_DEFAULT 0x00000000
-
-/* AON_PM_L2 :: PCI_SET :: GPIO [05:05] */
-#define BCHP_AON_PM_L2_PCI_SET_GPIO_MASK 0x00000020
-#define BCHP_AON_PM_L2_PCI_SET_GPIO_SHIFT 5
-#define BCHP_AON_PM_L2_PCI_SET_GPIO_DEFAULT 0x00000000
-
-/* AON_PM_L2 :: PCI_SET :: NMI_B_INTR [04:04] */
-#define BCHP_AON_PM_L2_PCI_SET_NMI_B_INTR_MASK 0x00000010
-#define BCHP_AON_PM_L2_PCI_SET_NMI_B_INTR_SHIFT 4
-#define BCHP_AON_PM_L2_PCI_SET_NMI_B_INTR_DEFAULT 0x00000000
-
-/* AON_PM_L2 :: PCI_SET :: TIMER_INTR [03:03] */
-#define BCHP_AON_PM_L2_PCI_SET_TIMER_INTR_MASK 0x00000008
-#define BCHP_AON_PM_L2_PCI_SET_TIMER_INTR_SHIFT 3
-#define BCHP_AON_PM_L2_PCI_SET_TIMER_INTR_DEFAULT 0x00000000
-
-/* AON_PM_L2 :: PCI_SET :: KPD_INTR [02:02] */
-#define BCHP_AON_PM_L2_PCI_SET_KPD_INTR_MASK 0x00000004
-#define BCHP_AON_PM_L2_PCI_SET_KPD_INTR_SHIFT 2
-#define BCHP_AON_PM_L2_PCI_SET_KPD_INTR_DEFAULT 0x00000000
-
-/* AON_PM_L2 :: PCI_SET :: IRR_INTR [01:01] */
-#define BCHP_AON_PM_L2_PCI_SET_IRR_INTR_MASK 0x00000002
-#define BCHP_AON_PM_L2_PCI_SET_IRR_INTR_SHIFT 1
-#define BCHP_AON_PM_L2_PCI_SET_IRR_INTR_DEFAULT 0x00000000
-
-/* AON_PM_L2 :: PCI_SET :: CEC_INTR [00:00] */
-#define BCHP_AON_PM_L2_PCI_SET_CEC_INTR_MASK 0x00000001
-#define BCHP_AON_PM_L2_PCI_SET_CEC_INTR_SHIFT 0
-#define BCHP_AON_PM_L2_PCI_SET_CEC_INTR_DEFAULT 0x00000000
-
-/***************************************************************************
- *PCI_CLEAR - PCI interrupt Clear Register
- ***************************************************************************/
-/* AON_PM_L2 :: PCI_CLEAR :: reserved0 [31:20] */
-#define BCHP_AON_PM_L2_PCI_CLEAR_reserved0_MASK 0xfff00000
-#define BCHP_AON_PM_L2_PCI_CLEAR_reserved0_SHIFT 20
-
-/* AON_PM_L2 :: PCI_CLEAR :: DCS_PH3_RESET [19:19] */
-#define BCHP_AON_PM_L2_PCI_CLEAR_DCS_PH3_RESET_MASK 0x00080000
-#define BCHP_AON_PM_L2_PCI_CLEAR_DCS_PH3_RESET_SHIFT 19
-#define BCHP_AON_PM_L2_PCI_CLEAR_DCS_PH3_RESET_DEFAULT 0x00000000
-
-/* AON_PM_L2 :: PCI_CLEAR :: FP_RESET [18:18] */
-#define BCHP_AON_PM_L2_PCI_CLEAR_FP_RESET_MASK 0x00040000
-#define BCHP_AON_PM_L2_PCI_CLEAR_FP_RESET_SHIFT 18
-#define BCHP_AON_PM_L2_PCI_CLEAR_FP_RESET_DEFAULT 0x00000000
-
-/* AON_PM_L2 :: PCI_CLEAR :: BOUNDARY_SCAN_REQ [17:17] */
-#define BCHP_AON_PM_L2_PCI_CLEAR_BOUNDARY_SCAN_REQ_MASK 0x00020000
-#define BCHP_AON_PM_L2_PCI_CLEAR_BOUNDARY_SCAN_REQ_SHIFT 17
-#define BCHP_AON_PM_L2_PCI_CLEAR_BOUNDARY_SCAN_REQ_DEFAULT 0x00000000
-
-/* AON_PM_L2 :: PCI_CLEAR :: DCS_HEADEND_INTR [16:16] */
-#define BCHP_AON_PM_L2_PCI_CLEAR_DCS_HEADEND_INTR_MASK 0x00010000
-#define BCHP_AON_PM_L2_PCI_CLEAR_DCS_HEADEND_INTR_SHIFT 16
-#define BCHP_AON_PM_L2_PCI_CLEAR_DCS_HEADEND_INTR_DEFAULT 0x00000000
-
-/* AON_PM_L2 :: PCI_CLEAR :: BMU_INTR_BATT_LOW [15:15] */
-#define BCHP_AON_PM_L2_PCI_CLEAR_BMU_INTR_BATT_LOW_MASK 0x00008000
-#define BCHP_AON_PM_L2_PCI_CLEAR_BMU_INTR_BATT_LOW_SHIFT 15
-#define BCHP_AON_PM_L2_PCI_CLEAR_BMU_INTR_BATT_LOW_DEFAULT 0x00000000
-
-/* AON_PM_L2 :: PCI_CLEAR :: BMU_INTR_AP_RESTORED [14:14] */
-#define BCHP_AON_PM_L2_PCI_CLEAR_BMU_INTR_AP_RESTORED_MASK 0x00004000
-#define BCHP_AON_PM_L2_PCI_CLEAR_BMU_INTR_AP_RESTORED_SHIFT 14
-#define BCHP_AON_PM_L2_PCI_CLEAR_BMU_INTR_AP_RESTORED_DEFAULT 0x00000000
-
-/* AON_PM_L2 :: PCI_CLEAR :: BMU_INTR_AP_LOST [13:13] */
-#define BCHP_AON_PM_L2_PCI_CLEAR_BMU_INTR_AP_LOST_MASK 0x00002000
-#define BCHP_AON_PM_L2_PCI_CLEAR_BMU_INTR_AP_LOST_SHIFT 13
-#define BCHP_AON_PM_L2_PCI_CLEAR_BMU_INTR_AP_LOST_DEFAULT 0x00000000
-
-/* AON_PM_L2 :: PCI_CLEAR :: USB0 [12:12] */
-#define BCHP_AON_PM_L2_PCI_CLEAR_USB0_MASK 0x00001000
-#define BCHP_AON_PM_L2_PCI_CLEAR_USB0_SHIFT 12
-#define BCHP_AON_PM_L2_PCI_CLEAR_USB0_DEFAULT 0x00000000
-
-/* AON_PM_L2 :: PCI_CLEAR :: MOCA [11:11] */
-#define BCHP_AON_PM_L2_PCI_CLEAR_MOCA_MASK 0x00000800
-#define BCHP_AON_PM_L2_PCI_CLEAR_MOCA_SHIFT 11
-#define BCHP_AON_PM_L2_PCI_CLEAR_MOCA_DEFAULT 0x00000000
-
-/* AON_PM_L2 :: PCI_CLEAR :: XPT_PMU [10:10] */
-#define BCHP_AON_PM_L2_PCI_CLEAR_XPT_PMU_MASK 0x00000400
-#define BCHP_AON_PM_L2_PCI_CLEAR_XPT_PMU_SHIFT 10
-#define BCHP_AON_PM_L2_PCI_CLEAR_XPT_PMU_DEFAULT 0x00000000
-
-/* AON_PM_L2 :: PCI_CLEAR :: CAP [09:09] */
-#define BCHP_AON_PM_L2_PCI_CLEAR_CAP_MASK 0x00000200
-#define BCHP_AON_PM_L2_PCI_CLEAR_CAP_SHIFT 9
-#define BCHP_AON_PM_L2_PCI_CLEAR_CAP_DEFAULT 0x00000000
-
-/* AON_PM_L2 :: PCI_CLEAR :: WOL_UNIMAC2 [08:08] */
-#define BCHP_AON_PM_L2_PCI_CLEAR_WOL_UNIMAC2_MASK 0x00000100
-#define BCHP_AON_PM_L2_PCI_CLEAR_WOL_UNIMAC2_SHIFT 8
-#define BCHP_AON_PM_L2_PCI_CLEAR_WOL_UNIMAC2_DEFAULT 0x00000000
-
-/* AON_PM_L2 :: PCI_CLEAR :: WOL_UNIMAC1 [07:07] */
-#define BCHP_AON_PM_L2_PCI_CLEAR_WOL_UNIMAC1_MASK 0x00000080
-#define BCHP_AON_PM_L2_PCI_CLEAR_WOL_UNIMAC1_SHIFT 7
-#define BCHP_AON_PM_L2_PCI_CLEAR_WOL_UNIMAC1_DEFAULT 0x00000000
-
-/* AON_PM_L2 :: PCI_CLEAR :: WOL_UNIMAC0 [06:06] */
-#define BCHP_AON_PM_L2_PCI_CLEAR_WOL_UNIMAC0_MASK 0x00000040
-#define BCHP_AON_PM_L2_PCI_CLEAR_WOL_UNIMAC0_SHIFT 6
-#define BCHP_AON_PM_L2_PCI_CLEAR_WOL_UNIMAC0_DEFAULT 0x00000000
-
-/* AON_PM_L2 :: PCI_CLEAR :: GPIO [05:05] */
-#define BCHP_AON_PM_L2_PCI_CLEAR_GPIO_MASK 0x00000020
-#define BCHP_AON_PM_L2_PCI_CLEAR_GPIO_SHIFT 5
-#define BCHP_AON_PM_L2_PCI_CLEAR_GPIO_DEFAULT 0x00000000
-
-/* AON_PM_L2 :: PCI_CLEAR :: NMI_B_INTR [04:04] */
-#define BCHP_AON_PM_L2_PCI_CLEAR_NMI_B_INTR_MASK 0x00000010
-#define BCHP_AON_PM_L2_PCI_CLEAR_NMI_B_INTR_SHIFT 4
-#define BCHP_AON_PM_L2_PCI_CLEAR_NMI_B_INTR_DEFAULT 0x00000000
-
-/* AON_PM_L2 :: PCI_CLEAR :: TIMER_INTR [03:03] */
-#define BCHP_AON_PM_L2_PCI_CLEAR_TIMER_INTR_MASK 0x00000008
-#define BCHP_AON_PM_L2_PCI_CLEAR_TIMER_INTR_SHIFT 3
-#define BCHP_AON_PM_L2_PCI_CLEAR_TIMER_INTR_DEFAULT 0x00000000
-
-/* AON_PM_L2 :: PCI_CLEAR :: KPD_INTR [02:02] */
-#define BCHP_AON_PM_L2_PCI_CLEAR_KPD_INTR_MASK 0x00000004
-#define BCHP_AON_PM_L2_PCI_CLEAR_KPD_INTR_SHIFT 2
-#define BCHP_AON_PM_L2_PCI_CLEAR_KPD_INTR_DEFAULT 0x00000000
-
-/* AON_PM_L2 :: PCI_CLEAR :: IRR_INTR [01:01] */
-#define BCHP_AON_PM_L2_PCI_CLEAR_IRR_INTR_MASK 0x00000002
-#define BCHP_AON_PM_L2_PCI_CLEAR_IRR_INTR_SHIFT 1
-#define BCHP_AON_PM_L2_PCI_CLEAR_IRR_INTR_DEFAULT 0x00000000
-
-/* AON_PM_L2 :: PCI_CLEAR :: CEC_INTR [00:00] */
-#define BCHP_AON_PM_L2_PCI_CLEAR_CEC_INTR_MASK 0x00000001
-#define BCHP_AON_PM_L2_PCI_CLEAR_CEC_INTR_SHIFT 0
-#define BCHP_AON_PM_L2_PCI_CLEAR_CEC_INTR_DEFAULT 0x00000000
-
-/***************************************************************************
- *PCI_MASK_STATUS - PCI interrupt Mask Status Register
- ***************************************************************************/
-/* AON_PM_L2 :: PCI_MASK_STATUS :: reserved0 [31:20] */
-#define BCHP_AON_PM_L2_PCI_MASK_STATUS_reserved0_MASK 0xfff00000
-#define BCHP_AON_PM_L2_PCI_MASK_STATUS_reserved0_SHIFT 20
-
-/* AON_PM_L2 :: PCI_MASK_STATUS :: DCS_PH3_RESET [19:19] */
-#define BCHP_AON_PM_L2_PCI_MASK_STATUS_DCS_PH3_RESET_MASK 0x00080000
-#define BCHP_AON_PM_L2_PCI_MASK_STATUS_DCS_PH3_RESET_SHIFT 19
-#define BCHP_AON_PM_L2_PCI_MASK_STATUS_DCS_PH3_RESET_DEFAULT 0x00000001
-
-/* AON_PM_L2 :: PCI_MASK_STATUS :: FP_RESET [18:18] */
-#define BCHP_AON_PM_L2_PCI_MASK_STATUS_FP_RESET_MASK 0x00040000
-#define BCHP_AON_PM_L2_PCI_MASK_STATUS_FP_RESET_SHIFT 18
-#define BCHP_AON_PM_L2_PCI_MASK_STATUS_FP_RESET_DEFAULT 0x00000001
-
-/* AON_PM_L2 :: PCI_MASK_STATUS :: BOUNDARY_SCAN_REQ [17:17] */
-#define BCHP_AON_PM_L2_PCI_MASK_STATUS_BOUNDARY_SCAN_REQ_MASK 0x00020000
-#define BCHP_AON_PM_L2_PCI_MASK_STATUS_BOUNDARY_SCAN_REQ_SHIFT 17
-#define BCHP_AON_PM_L2_PCI_MASK_STATUS_BOUNDARY_SCAN_REQ_DEFAULT 0x00000001
-
-/* AON_PM_L2 :: PCI_MASK_STATUS :: DCS_HEADEND_INTR [16:16] */
-#define BCHP_AON_PM_L2_PCI_MASK_STATUS_DCS_HEADEND_INTR_MASK 0x00010000
-#define BCHP_AON_PM_L2_PCI_MASK_STATUS_DCS_HEADEND_INTR_SHIFT 16
-#define BCHP_AON_PM_L2_PCI_MASK_STATUS_DCS_HEADEND_INTR_DEFAULT 0x00000001
-
-/* AON_PM_L2 :: PCI_MASK_STATUS :: BMU_INTR_BATT_LOW [15:15] */
-#define BCHP_AON_PM_L2_PCI_MASK_STATUS_BMU_INTR_BATT_LOW_MASK 0x00008000
-#define BCHP_AON_PM_L2_PCI_MASK_STATUS_BMU_INTR_BATT_LOW_SHIFT 15
-#define BCHP_AON_PM_L2_PCI_MASK_STATUS_BMU_INTR_BATT_LOW_DEFAULT 0x00000001
-
-/* AON_PM_L2 :: PCI_MASK_STATUS :: BMU_INTR_AP_RESTORED [14:14] */
-#define BCHP_AON_PM_L2_PCI_MASK_STATUS_BMU_INTR_AP_RESTORED_MASK 0x00004000
-#define BCHP_AON_PM_L2_PCI_MASK_STATUS_BMU_INTR_AP_RESTORED_SHIFT 14
-#define BCHP_AON_PM_L2_PCI_MASK_STATUS_BMU_INTR_AP_RESTORED_DEFAULT 0x00000001
-
-/* AON_PM_L2 :: PCI_MASK_STATUS :: BMU_INTR_AP_LOST [13:13] */
-#define BCHP_AON_PM_L2_PCI_MASK_STATUS_BMU_INTR_AP_LOST_MASK 0x00002000
-#define BCHP_AON_PM_L2_PCI_MASK_STATUS_BMU_INTR_AP_LOST_SHIFT 13
-#define BCHP_AON_PM_L2_PCI_MASK_STATUS_BMU_INTR_AP_LOST_DEFAULT 0x00000001
-
-/* AON_PM_L2 :: PCI_MASK_STATUS :: USB0 [12:12] */
-#define BCHP_AON_PM_L2_PCI_MASK_STATUS_USB0_MASK 0x00001000
-#define BCHP_AON_PM_L2_PCI_MASK_STATUS_USB0_SHIFT 12
-#define BCHP_AON_PM_L2_PCI_MASK_STATUS_USB0_DEFAULT 0x00000001
-
-/* AON_PM_L2 :: PCI_MASK_STATUS :: MOCA [11:11] */
-#define BCHP_AON_PM_L2_PCI_MASK_STATUS_MOCA_MASK 0x00000800
-#define BCHP_AON_PM_L2_PCI_MASK_STATUS_MOCA_SHIFT 11
-#define BCHP_AON_PM_L2_PCI_MASK_STATUS_MOCA_DEFAULT 0x00000001
-
-/* AON_PM_L2 :: PCI_MASK_STATUS :: XPT_PMU [10:10] */
-#define BCHP_AON_PM_L2_PCI_MASK_STATUS_XPT_PMU_MASK 0x00000400
-#define BCHP_AON_PM_L2_PCI_MASK_STATUS_XPT_PMU_SHIFT 10
-#define BCHP_AON_PM_L2_PCI_MASK_STATUS_XPT_PMU_DEFAULT 0x00000001
-
-/* AON_PM_L2 :: PCI_MASK_STATUS :: CAP [09:09] */
-#define BCHP_AON_PM_L2_PCI_MASK_STATUS_CAP_MASK 0x00000200
-#define BCHP_AON_PM_L2_PCI_MASK_STATUS_CAP_SHIFT 9
-#define BCHP_AON_PM_L2_PCI_MASK_STATUS_CAP_DEFAULT 0x00000001
-
-/* AON_PM_L2 :: PCI_MASK_STATUS :: WOL_GENET2 [08:08] */
-#define BCHP_AON_PM_L2_PCI_MASK_STATUS_WOL_GENET2_MASK 0x00000100
-#define BCHP_AON_PM_L2_PCI_MASK_STATUS_WOL_GENET2_SHIFT 8
-#define BCHP_AON_PM_L2_PCI_MASK_STATUS_WOL_GENET2_DEFAULT 0x00000001
-
-/* AON_PM_L2 :: PCI_MASK_STATUS :: WOL_GENET1 [07:07] */
-#define BCHP_AON_PM_L2_PCI_MASK_STATUS_WOL_GENET1_MASK 0x00000080
-#define BCHP_AON_PM_L2_PCI_MASK_STATUS_WOL_GENET1_SHIFT 7
-#define BCHP_AON_PM_L2_PCI_MASK_STATUS_WOL_GENET1_DEFAULT 0x00000001
-
-/* AON_PM_L2 :: PCI_MASK_STATUS :: WOL_GENET0 [06:06] */
-#define BCHP_AON_PM_L2_PCI_MASK_STATUS_WOL_GENET0_MASK 0x00000040
-#define BCHP_AON_PM_L2_PCI_MASK_STATUS_WOL_GENET0_SHIFT 6
-#define BCHP_AON_PM_L2_PCI_MASK_STATUS_WOL_GENET0_DEFAULT 0x00000001
-
-/* AON_PM_L2 :: PCI_MASK_STATUS :: GPIO [05:05] */
-#define BCHP_AON_PM_L2_PCI_MASK_STATUS_GPIO_MASK 0x00000020
-#define BCHP_AON_PM_L2_PCI_MASK_STATUS_GPIO_SHIFT 5
-#define BCHP_AON_PM_L2_PCI_MASK_STATUS_GPIO_DEFAULT 0x00000001
-
-/* AON_PM_L2 :: PCI_MASK_STATUS :: NMI_B_INTR [04:04] */
-#define BCHP_AON_PM_L2_PCI_MASK_STATUS_NMI_B_INTR_MASK 0x00000010
-#define BCHP_AON_PM_L2_PCI_MASK_STATUS_NMI_B_INTR_SHIFT 4
-#define BCHP_AON_PM_L2_PCI_MASK_STATUS_NMI_B_INTR_DEFAULT 0x00000001
-
-/* AON_PM_L2 :: PCI_MASK_STATUS :: TIMER_INTR [03:03] */
-#define BCHP_AON_PM_L2_PCI_MASK_STATUS_TIMER_INTR_MASK 0x00000008
-#define BCHP_AON_PM_L2_PCI_MASK_STATUS_TIMER_INTR_SHIFT 3
-#define BCHP_AON_PM_L2_PCI_MASK_STATUS_TIMER_INTR_DEFAULT 0x00000001
-
-/* AON_PM_L2 :: PCI_MASK_STATUS :: KPD_INTR [02:02] */
-#define BCHP_AON_PM_L2_PCI_MASK_STATUS_KPD_INTR_MASK 0x00000004
-#define BCHP_AON_PM_L2_PCI_MASK_STATUS_KPD_INTR_SHIFT 2
-#define BCHP_AON_PM_L2_PCI_MASK_STATUS_KPD_INTR_DEFAULT 0x00000001
-
-/* AON_PM_L2 :: PCI_MASK_STATUS :: IRR_INTR [01:01] */
-#define BCHP_AON_PM_L2_PCI_MASK_STATUS_IRR_INTR_MASK 0x00000002
-#define BCHP_AON_PM_L2_PCI_MASK_STATUS_IRR_INTR_SHIFT 1
-#define BCHP_AON_PM_L2_PCI_MASK_STATUS_IRR_INTR_DEFAULT 0x00000001
-
-/* AON_PM_L2 :: PCI_MASK_STATUS :: CEC_INTR [00:00] */
-#define BCHP_AON_PM_L2_PCI_MASK_STATUS_CEC_INTR_MASK 0x00000001
-#define BCHP_AON_PM_L2_PCI_MASK_STATUS_CEC_INTR_SHIFT 0
-#define BCHP_AON_PM_L2_PCI_MASK_STATUS_CEC_INTR_DEFAULT 0x00000001
-
-/***************************************************************************
- *PCI_MASK_SET - PCI interrupt Mask Set Register
- ***************************************************************************/
-/* AON_PM_L2 :: PCI_MASK_SET :: reserved0 [31:20] */
-#define BCHP_AON_PM_L2_PCI_MASK_SET_reserved0_MASK 0xfff00000
-#define BCHP_AON_PM_L2_PCI_MASK_SET_reserved0_SHIFT 20
-
-/* AON_PM_L2 :: PCI_MASK_SET :: DCS_PH3_RESET [19:19] */
-#define BCHP_AON_PM_L2_PCI_MASK_SET_DCS_PH3_RESET_MASK 0x00080000
-#define BCHP_AON_PM_L2_PCI_MASK_SET_DCS_PH3_RESET_SHIFT 19
-#define BCHP_AON_PM_L2_PCI_MASK_SET_DCS_PH3_RESET_DEFAULT 0x00000001
-
-/* AON_PM_L2 :: PCI_MASK_SET :: FP_RESET [18:18] */
-#define BCHP_AON_PM_L2_PCI_MASK_SET_FP_RESET_MASK 0x00040000
-#define BCHP_AON_PM_L2_PCI_MASK_SET_FP_RESET_SHIFT 18
-#define BCHP_AON_PM_L2_PCI_MASK_SET_FP_RESET_DEFAULT 0x00000001
-
-/* AON_PM_L2 :: PCI_MASK_SET :: BOUNDARY_SCAN_REQ [17:17] */
-#define BCHP_AON_PM_L2_PCI_MASK_SET_BOUNDARY_SCAN_REQ_MASK 0x00020000
-#define BCHP_AON_PM_L2_PCI_MASK_SET_BOUNDARY_SCAN_REQ_SHIFT 17
-#define BCHP_AON_PM_L2_PCI_MASK_SET_BOUNDARY_SCAN_REQ_DEFAULT 0x00000001
-
-/* AON_PM_L2 :: PCI_MASK_SET :: DCS_HEADEND_INTR [16:16] */
-#define BCHP_AON_PM_L2_PCI_MASK_SET_DCS_HEADEND_INTR_MASK 0x00010000
-#define BCHP_AON_PM_L2_PCI_MASK_SET_DCS_HEADEND_INTR_SHIFT 16
-#define BCHP_AON_PM_L2_PCI_MASK_SET_DCS_HEADEND_INTR_DEFAULT 0x00000001
-
-/* AON_PM_L2 :: PCI_MASK_SET :: BMU_INTR_BATT_LOW [15:15] */
-#define BCHP_AON_PM_L2_PCI_MASK_SET_BMU_INTR_BATT_LOW_MASK 0x00008000
-#define BCHP_AON_PM_L2_PCI_MASK_SET_BMU_INTR_BATT_LOW_SHIFT 15
-#define BCHP_AON_PM_L2_PCI_MASK_SET_BMU_INTR_BATT_LOW_DEFAULT 0x00000001
-
-/* AON_PM_L2 :: PCI_MASK_SET :: BMU_INTR_AP_RESTORED [14:14] */
-#define BCHP_AON_PM_L2_PCI_MASK_SET_BMU_INTR_AP_RESTORED_MASK 0x00004000
-#define BCHP_AON_PM_L2_PCI_MASK_SET_BMU_INTR_AP_RESTORED_SHIFT 14
-#define BCHP_AON_PM_L2_PCI_MASK_SET_BMU_INTR_AP_RESTORED_DEFAULT 0x00000001
-
-/* AON_PM_L2 :: PCI_MASK_SET :: BMU_INTR_AP_LOST [13:13] */
-#define BCHP_AON_PM_L2_PCI_MASK_SET_BMU_INTR_AP_LOST_MASK 0x00002000
-#define BCHP_AON_PM_L2_PCI_MASK_SET_BMU_INTR_AP_LOST_SHIFT 13
-#define BCHP_AON_PM_L2_PCI_MASK_SET_BMU_INTR_AP_LOST_DEFAULT 0x00000001
-
-/* AON_PM_L2 :: PCI_MASK_SET :: USB0 [12:12] */
-#define BCHP_AON_PM_L2_PCI_MASK_SET_USB0_MASK 0x00001000
-#define BCHP_AON_PM_L2_PCI_MASK_SET_USB0_SHIFT 12
-#define BCHP_AON_PM_L2_PCI_MASK_SET_USB0_DEFAULT 0x00000001
-
-/* AON_PM_L2 :: PCI_MASK_SET :: MOCA [11:11] */
-#define BCHP_AON_PM_L2_PCI_MASK_SET_MOCA_MASK 0x00000800
-#define BCHP_AON_PM_L2_PCI_MASK_SET_MOCA_SHIFT 11
-#define BCHP_AON_PM_L2_PCI_MASK_SET_MOCA_DEFAULT 0x00000001
-
-/* AON_PM_L2 :: PCI_MASK_SET :: XPT_PMU [10:10] */
-#define BCHP_AON_PM_L2_PCI_MASK_SET_XPT_PMU_MASK 0x00000400
-#define BCHP_AON_PM_L2_PCI_MASK_SET_XPT_PMU_SHIFT 10
-#define BCHP_AON_PM_L2_PCI_MASK_SET_XPT_PMU_DEFAULT 0x00000001
-
-/* AON_PM_L2 :: PCI_MASK_SET :: CAP [09:09] */
-#define BCHP_AON_PM_L2_PCI_MASK_SET_CAP_MASK 0x00000200
-#define BCHP_AON_PM_L2_PCI_MASK_SET_CAP_SHIFT 9
-#define BCHP_AON_PM_L2_PCI_MASK_SET_CAP_DEFAULT 0x00000001
-
-/* AON_PM_L2 :: PCI_MASK_SET :: WOL_GENET2 [08:08] */
-#define BCHP_AON_PM_L2_PCI_MASK_SET_WOL_GENET2_MASK 0x00000100
-#define BCHP_AON_PM_L2_PCI_MASK_SET_WOL_GENET2_SHIFT 8
-#define BCHP_AON_PM_L2_PCI_MASK_SET_WOL_GENET2_DEFAULT 0x00000001
-
-/* AON_PM_L2 :: PCI_MASK_SET :: WOL_GENET1 [07:07] */
-#define BCHP_AON_PM_L2_PCI_MASK_SET_WOL_GENET1_MASK 0x00000080
-#define BCHP_AON_PM_L2_PCI_MASK_SET_WOL_GENET1_SHIFT 7
-#define BCHP_AON_PM_L2_PCI_MASK_SET_WOL_GENET1_DEFAULT 0x00000001
-
-/* AON_PM_L2 :: PCI_MASK_SET :: WOL_GENET0 [06:06] */
-#define BCHP_AON_PM_L2_PCI_MASK_SET_WOL_GENET0_MASK 0x00000040
-#define BCHP_AON_PM_L2_PCI_MASK_SET_WOL_GENET0_SHIFT 6
-#define BCHP_AON_PM_L2_PCI_MASK_SET_WOL_GENET0_DEFAULT 0x00000001
-
-/* AON_PM_L2 :: PCI_MASK_SET :: GPIO [05:05] */
-#define BCHP_AON_PM_L2_PCI_MASK_SET_GPIO_MASK 0x00000020
-#define BCHP_AON_PM_L2_PCI_MASK_SET_GPIO_SHIFT 5
-#define BCHP_AON_PM_L2_PCI_MASK_SET_GPIO_DEFAULT 0x00000001
-
-/* AON_PM_L2 :: PCI_MASK_SET :: NMI_B_INTR [04:04] */
-#define BCHP_AON_PM_L2_PCI_MASK_SET_NMI_B_INTR_MASK 0x00000010
-#define BCHP_AON_PM_L2_PCI_MASK_SET_NMI_B_INTR_SHIFT 4
-#define BCHP_AON_PM_L2_PCI_MASK_SET_NMI_B_INTR_DEFAULT 0x00000001
-
-/* AON_PM_L2 :: PCI_MASK_SET :: TIMER_INTR [03:03] */
-#define BCHP_AON_PM_L2_PCI_MASK_SET_TIMER_INTR_MASK 0x00000008
-#define BCHP_AON_PM_L2_PCI_MASK_SET_TIMER_INTR_SHIFT 3
-#define BCHP_AON_PM_L2_PCI_MASK_SET_TIMER_INTR_DEFAULT 0x00000001
-
-/* AON_PM_L2 :: PCI_MASK_SET :: KPD_INTR [02:02] */
-#define BCHP_AON_PM_L2_PCI_MASK_SET_KPD_INTR_MASK 0x00000004
-#define BCHP_AON_PM_L2_PCI_MASK_SET_KPD_INTR_SHIFT 2
-#define BCHP_AON_PM_L2_PCI_MASK_SET_KPD_INTR_DEFAULT 0x00000001
-
-/* AON_PM_L2 :: PCI_MASK_SET :: IRR_INTR [01:01] */
-#define BCHP_AON_PM_L2_PCI_MASK_SET_IRR_INTR_MASK 0x00000002
-#define BCHP_AON_PM_L2_PCI_MASK_SET_IRR_INTR_SHIFT 1
-#define BCHP_AON_PM_L2_PCI_MASK_SET_IRR_INTR_DEFAULT 0x00000001
-
-/* AON_PM_L2 :: PCI_MASK_SET :: CEC_INTR [00:00] */
-#define BCHP_AON_PM_L2_PCI_MASK_SET_CEC_INTR_MASK 0x00000001
-#define BCHP_AON_PM_L2_PCI_MASK_SET_CEC_INTR_SHIFT 0
-#define BCHP_AON_PM_L2_PCI_MASK_SET_CEC_INTR_DEFAULT 0x00000001
-
-/***************************************************************************
- *PCI_MASK_CLEAR - PCI interrupt Mask Clear Register
- ***************************************************************************/
-/* AON_PM_L2 :: PCI_MASK_CLEAR :: reserved0 [31:20] */
-#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_reserved0_MASK 0xfff00000
-#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_reserved0_SHIFT 20
-
-/* AON_PM_L2 :: PCI_MASK_CLEAR :: DCS_PH3_RESET [19:19] */
-#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_DCS_PH3_RESET_MASK 0x00080000
-#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_DCS_PH3_RESET_SHIFT 19
-#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_DCS_PH3_RESET_DEFAULT 0x00000001
-
-/* AON_PM_L2 :: PCI_MASK_CLEAR :: FP_RESET [18:18] */
-#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_FP_RESET_MASK 0x00040000
-#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_FP_RESET_SHIFT 18
-#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_FP_RESET_DEFAULT 0x00000001
-
-/* AON_PM_L2 :: PCI_MASK_CLEAR :: BOUNDARY_SCAN_REQ [17:17] */
-#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_BOUNDARY_SCAN_REQ_MASK 0x00020000
-#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_BOUNDARY_SCAN_REQ_SHIFT 17
-#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_BOUNDARY_SCAN_REQ_DEFAULT 0x00000001
-
-/* AON_PM_L2 :: PCI_MASK_CLEAR :: DCS_HEADEND_INTR [16:16] */
-#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_DCS_HEADEND_INTR_MASK 0x00010000
-#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_DCS_HEADEND_INTR_SHIFT 16
-#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_DCS_HEADEND_INTR_DEFAULT 0x00000001
-
-/* AON_PM_L2 :: PCI_MASK_CLEAR :: BMU_INTR_BATT_LOW [15:15] */
-#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_BMU_INTR_BATT_LOW_MASK 0x00008000
-#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_BMU_INTR_BATT_LOW_SHIFT 15
-#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_BMU_INTR_BATT_LOW_DEFAULT 0x00000001
-
-/* AON_PM_L2 :: PCI_MASK_CLEAR :: BMU_INTR_AP_RESTORED [14:14] */
-#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_BMU_INTR_AP_RESTORED_MASK 0x00004000
-#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_BMU_INTR_AP_RESTORED_SHIFT 14
-#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_BMU_INTR_AP_RESTORED_DEFAULT 0x00000001
-
-/* AON_PM_L2 :: PCI_MASK_CLEAR :: BMU_INTR_AP_LOST [13:13] */
-#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_BMU_INTR_AP_LOST_MASK 0x00002000
-#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_BMU_INTR_AP_LOST_SHIFT 13
-#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_BMU_INTR_AP_LOST_DEFAULT 0x00000001
-
-/* AON_PM_L2 :: PCI_MASK_CLEAR :: USB0 [12:12] */
-#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_USB0_MASK 0x00001000
-#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_USB0_SHIFT 12
-#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_USB0_DEFAULT 0x00000001
-
-/* AON_PM_L2 :: PCI_MASK_CLEAR :: MOCA [11:11] */
-#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_MOCA_MASK 0x00000800
-#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_MOCA_SHIFT 11
-#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_MOCA_DEFAULT 0x00000001
-
-/* AON_PM_L2 :: PCI_MASK_CLEAR :: XPT_PMU [10:10] */
-#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_XPT_PMU_MASK 0x00000400
-#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_XPT_PMU_SHIFT 10
-#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_XPT_PMU_DEFAULT 0x00000001
-
-/* AON_PM_L2 :: PCI_MASK_CLEAR :: CAP [09:09] */
-#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_CAP_MASK 0x00000200
-#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_CAP_SHIFT 9
-#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_CAP_DEFAULT 0x00000001
-
-/* AON_PM_L2 :: PCI_MASK_CLEAR :: WOL_GENET2 [08:08] */
-#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_WOL_GENET2_MASK 0x00000100
-#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_WOL_GENET2_SHIFT 8
-#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_WOL_GENET2_DEFAULT 0x00000001
-
-/* AON_PM_L2 :: PCI_MASK_CLEAR :: WOL_GENET1 [07:07] */
-#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_WOL_GENET1_MASK 0x00000080
-#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_WOL_GENET1_SHIFT 7
-#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_WOL_GENET1_DEFAULT 0x00000001
-
-/* AON_PM_L2 :: PCI_MASK_CLEAR :: WOL_GENET0 [06:06] */
-#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_WOL_GENET0_MASK 0x00000040
-#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_WOL_GENET0_SHIFT 6
-#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_WOL_GENET0_DEFAULT 0x00000001
-
-/* AON_PM_L2 :: PCI_MASK_CLEAR :: GPIO [05:05] */
-#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_GPIO_MASK 0x00000020
-#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_GPIO_SHIFT 5
-#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_GPIO_DEFAULT 0x00000001
-
-/* AON_PM_L2 :: PCI_MASK_CLEAR :: NMI_B_INTR [04:04] */
-#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_NMI_B_INTR_MASK 0x00000010
-#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_NMI_B_INTR_SHIFT 4
-#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_NMI_B_INTR_DEFAULT 0x00000001
-
-/* AON_PM_L2 :: PCI_MASK_CLEAR :: TIMER_INTR [03:03] */
-#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_TIMER_INTR_MASK 0x00000008
-#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_TIMER_INTR_SHIFT 3
-#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_TIMER_INTR_DEFAULT 0x00000001
-
-/* AON_PM_L2 :: PCI_MASK_CLEAR :: KPD_INTR [02:02] */
-#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_KPD_INTR_MASK 0x00000004
-#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_KPD_INTR_SHIFT 2
-#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_KPD_INTR_DEFAULT 0x00000001
-
-/* AON_PM_L2 :: PCI_MASK_CLEAR :: IRR_INTR [01:01] */
-#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_IRR_INTR_MASK 0x00000002
-#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_IRR_INTR_SHIFT 1
-#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_IRR_INTR_DEFAULT 0x00000001
-
-/* AON_PM_L2 :: PCI_MASK_CLEAR :: CEC_INTR [00:00] */
-#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_CEC_INTR_MASK 0x00000001
-#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_CEC_INTR_SHIFT 0
-#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_CEC_INTR_DEFAULT 0x00000001
-
-#endif /* #ifndef BCHP_AON_PM_L2_H__ */
-
-/* End of File */
diff --git a/include/linux/brcmstb/7145a0/bchp_bspi.h b/include/linux/brcmstb/7145a0/bchp_bspi.h
deleted file mode 100644
index 677b449..0000000
--- a/include/linux/brcmstb/7145a0/bchp_bspi.h
+++ /dev/null
@@ -1,443 +0,0 @@
-/***************************************************************************
- * Copyright (c) 1999-2013, Broadcom Corporation
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
- *
- * Module Description:
- * DO NOT EDIT THIS FILE DIRECTLY
- *
- * This module was generated magically with RDB from a source description
- * file. You must edit the source file for changes to be made to this file.
- *
- *
- * Date: Generated on Sat Apr 6 03:07:45 2013
- * MD5 Checksum d41d8cd98f00b204e9800998ecf8427e
- *
- * Compiled with: RDB Utility combo_header.pl
- * RDB Parser 3.0
- * unknown unknown
- * Perl Interpreter 5.008008
- * Operating System linux
- *
- * Revision History:
- *
- * $brcm_Log: $
- *
- ***************************************************************************/
-
-#ifndef BCHP_BSPI_H__
-#define BCHP_BSPI_H__
-
-/***************************************************************************
- *BSPI - Public BSPI Control Registers
- ***************************************************************************/
-#define BCHP_BSPI_REVISION_ID 0x203d3200 /* Revision ID */
-#define BCHP_BSPI_SCRATCH 0x203d3204 /* Revision ID */
-#define BCHP_BSPI_MAST_N_BOOT_CTRL 0x203d3208 /* Master/Boot SPI Control Register */
-#define BCHP_BSPI_BUSY_STATUS 0x203d320c /* BSPI Busy Status Register */
-#define BCHP_BSPI_INTR_STATUS 0x203d3210 /* Interrupt Status Register */
-#define BCHP_BSPI_B0_STATUS 0x203d3214 /* Prefetch Buffer 0 Status Register */
-#define BCHP_BSPI_B0_CTRL 0x203d3218 /* Prefetch Buffer 0 Control Register */
-#define BCHP_BSPI_B1_STATUS 0x203d321c /* Prefetch Buffer 1 Status Register */
-#define BCHP_BSPI_B1_CTRL 0x203d3220 /* Prefetch Buffer 1 Control Register */
-#define BCHP_BSPI_STRAP_OVERRIDE_CTRL 0x203d3224 /* Dual/Single Receive Mode Control Register */
-#define BCHP_BSPI_FLEX_MODE_ENABLE 0x203d3228 /* Flexible Control Mode Enable Register */
-#define BCHP_BSPI_BITS_PER_CYCLE 0x203d322c /* Bits per cycle "b-p-c" Control Register */
-#define BCHP_BSPI_BITS_PER_PHASE 0x203d3230 /* Bits per Phase "b-p-p" Control Register */
-#define BCHP_BSPI_CMD_AND_MODE_BYTE 0x203d3234 /* Command and Mode Data Register */
-#define BCHP_BSPI_BSPI_FLASH_UPPER_ADDR_BYTE 0x203d3238 /* Bspi FLash upper address byte register */
-#define BCHP_BSPI_BSPI_XOR_VALUE 0x203d323c /* BSPI FLASH XOR Value Register */
-#define BCHP_BSPI_BSPI_XOR_ENABLE 0x203d3240 /* BSPI FLASH XOR Enable Register */
-#define BCHP_BSPI_BSPI_PIO_MODE_ENABLE 0x203d3244 /* BSPI Pin Programmed IO Mode Enable Register */
-#define BCHP_BSPI_BSPI_PIO_IODIR 0x203d3248 /* BSPI Pin Programmed IO Mode Direction Register */
-#define BCHP_BSPI_BSPI_PIO_DATA 0x203d324c /* BSPI Pin Programmed IO Mode Data Register */
-
-/***************************************************************************
- *REVISION_ID - Revision ID
- ***************************************************************************/
-/* BSPI :: REVISION_ID :: reserved0 [31:16] */
-#define BCHP_BSPI_REVISION_ID_reserved0_MASK 0xffff0000
-#define BCHP_BSPI_REVISION_ID_reserved0_SHIFT 16
-
-/* BSPI :: REVISION_ID :: MAJOR [15:08] */
-#define BCHP_BSPI_REVISION_ID_MAJOR_MASK 0x0000ff00
-#define BCHP_BSPI_REVISION_ID_MAJOR_SHIFT 8
-#define BCHP_BSPI_REVISION_ID_MAJOR_DEFAULT 0x00000004
-
-/* BSPI :: REVISION_ID :: MINOR [07:00] */
-#define BCHP_BSPI_REVISION_ID_MINOR_MASK 0x000000ff
-#define BCHP_BSPI_REVISION_ID_MINOR_SHIFT 0
-#define BCHP_BSPI_REVISION_ID_MINOR_DEFAULT 0x00000001
-
-/***************************************************************************
- *SCRATCH - Revision ID
- ***************************************************************************/
-/* BSPI :: SCRATCH :: SCRATCH [31:00] */
-#define BCHP_BSPI_SCRATCH_SCRATCH_MASK 0xffffffff
-#define BCHP_BSPI_SCRATCH_SCRATCH_SHIFT 0
-#define BCHP_BSPI_SCRATCH_SCRATCH_DEFAULT 0x00000000
-
-/***************************************************************************
- *MAST_N_BOOT_CTRL - Master/Boot SPI Control Register
- ***************************************************************************/
-/* BSPI :: MAST_N_BOOT_CTRL :: reserved0 [31:01] */
-#define BCHP_BSPI_MAST_N_BOOT_CTRL_reserved0_MASK 0xfffffffe
-#define BCHP_BSPI_MAST_N_BOOT_CTRL_reserved0_SHIFT 1
-
-/* BSPI :: MAST_N_BOOT_CTRL :: mast_n_boot [00:00] */
-#define BCHP_BSPI_MAST_N_BOOT_CTRL_mast_n_boot_MASK 0x00000001
-#define BCHP_BSPI_MAST_N_BOOT_CTRL_mast_n_boot_SHIFT 0
-#define BCHP_BSPI_MAST_N_BOOT_CTRL_mast_n_boot_DEFAULT 0x00000000
-
-/***************************************************************************
- *BUSY_STATUS - BSPI Busy Status Register
- ***************************************************************************/
-/* BSPI :: BUSY_STATUS :: reserved0 [31:01] */
-#define BCHP_BSPI_BUSY_STATUS_reserved0_MASK 0xfffffffe
-#define BCHP_BSPI_BUSY_STATUS_reserved0_SHIFT 1
-
-/* BSPI :: BUSY_STATUS :: busy [00:00] */
-#define BCHP_BSPI_BUSY_STATUS_busy_MASK 0x00000001
-#define BCHP_BSPI_BUSY_STATUS_busy_SHIFT 0
-#define BCHP_BSPI_BUSY_STATUS_busy_DEFAULT 0x00000000
-
-/***************************************************************************
- *INTR_STATUS - Interrupt Status Register
- ***************************************************************************/
-/* BSPI :: INTR_STATUS :: reserved0 [31:02] */
-#define BCHP_BSPI_INTR_STATUS_reserved0_MASK 0xfffffffc
-#define BCHP_BSPI_INTR_STATUS_reserved0_SHIFT 2
-
-/* BSPI :: INTR_STATUS :: intr_1 [01:01] */
-#define BCHP_BSPI_INTR_STATUS_intr_1_MASK 0x00000002
-#define BCHP_BSPI_INTR_STATUS_intr_1_SHIFT 1
-#define BCHP_BSPI_INTR_STATUS_intr_1_DEFAULT 0x00000000
-
-/* BSPI :: INTR_STATUS :: intr_0 [00:00] */
-#define BCHP_BSPI_INTR_STATUS_intr_0_MASK 0x00000001
-#define BCHP_BSPI_INTR_STATUS_intr_0_SHIFT 0
-#define BCHP_BSPI_INTR_STATUS_intr_0_DEFAULT 0x00000000
-
-/***************************************************************************
- *B0_STATUS - Prefetch Buffer 0 Status Register
- ***************************************************************************/
-/* BSPI :: B0_STATUS :: reserved0 [31:31] */
-#define BCHP_BSPI_B0_STATUS_reserved0_MASK 0x80000000
-#define BCHP_BSPI_B0_STATUS_reserved0_SHIFT 31
-
-/* BSPI :: B0_STATUS :: b0_prefetch_active [30:30] */
-#define BCHP_BSPI_B0_STATUS_b0_prefetch_active_MASK 0x40000000
-#define BCHP_BSPI_B0_STATUS_b0_prefetch_active_SHIFT 30
-#define BCHP_BSPI_B0_STATUS_b0_prefetch_active_DEFAULT 0x00000000
-
-/* BSPI :: B0_STATUS :: b0_full [29:29] */
-#define BCHP_BSPI_B0_STATUS_b0_full_MASK 0x20000000
-#define BCHP_BSPI_B0_STATUS_b0_full_SHIFT 29
-#define BCHP_BSPI_B0_STATUS_b0_full_DEFAULT 0x00000000
-
-/* BSPI :: B0_STATUS :: b0_empty [28:28] */
-#define BCHP_BSPI_B0_STATUS_b0_empty_MASK 0x10000000
-#define BCHP_BSPI_B0_STATUS_b0_empty_SHIFT 28
-#define BCHP_BSPI_B0_STATUS_b0_empty_DEFAULT 0x00000001
-
-/* BSPI :: B0_STATUS :: b0_miss [27:27] */
-#define BCHP_BSPI_B0_STATUS_b0_miss_MASK 0x08000000
-#define BCHP_BSPI_B0_STATUS_b0_miss_SHIFT 27
-#define BCHP_BSPI_B0_STATUS_b0_miss_DEFAULT 0x00000000
-
-/* BSPI :: B0_STATUS :: b0_hit [26:26] */
-#define BCHP_BSPI_B0_STATUS_b0_hit_MASK 0x04000000
-#define BCHP_BSPI_B0_STATUS_b0_hit_SHIFT 26
-#define BCHP_BSPI_B0_STATUS_b0_hit_DEFAULT 0x00000000
-
-/* BSPI :: B0_STATUS :: b0_address [25:00] */
-#define BCHP_BSPI_B0_STATUS_b0_address_MASK 0x03ffffff
-#define BCHP_BSPI_B0_STATUS_b0_address_SHIFT 0
-#define BCHP_BSPI_B0_STATUS_b0_address_DEFAULT 0x00000000
-
-/***************************************************************************
- *B0_CTRL - Prefetch Buffer 0 Control Register
- ***************************************************************************/
-/* BSPI :: B0_CTRL :: reserved0 [31:01] */
-#define BCHP_BSPI_B0_CTRL_reserved0_MASK 0xfffffffe
-#define BCHP_BSPI_B0_CTRL_reserved0_SHIFT 1
-
-/* BSPI :: B0_CTRL :: b0_flush [00:00] */
-#define BCHP_BSPI_B0_CTRL_b0_flush_MASK 0x00000001
-#define BCHP_BSPI_B0_CTRL_b0_flush_SHIFT 0
-#define BCHP_BSPI_B0_CTRL_b0_flush_DEFAULT 0x00000000
-
-/***************************************************************************
- *B1_STATUS - Prefetch Buffer 1 Status Register
- ***************************************************************************/
-/* BSPI :: B1_STATUS :: reserved0 [31:31] */
-#define BCHP_BSPI_B1_STATUS_reserved0_MASK 0x80000000
-#define BCHP_BSPI_B1_STATUS_reserved0_SHIFT 31
-
-/* BSPI :: B1_STATUS :: b1_prefetch_active [30:30] */
-#define BCHP_BSPI_B1_STATUS_b1_prefetch_active_MASK 0x40000000
-#define BCHP_BSPI_B1_STATUS_b1_prefetch_active_SHIFT 30
-#define BCHP_BSPI_B1_STATUS_b1_prefetch_active_DEFAULT 0x00000000
-
-/* BSPI :: B1_STATUS :: b1_full [29:29] */
-#define BCHP_BSPI_B1_STATUS_b1_full_MASK 0x20000000
-#define BCHP_BSPI_B1_STATUS_b1_full_SHIFT 29
-#define BCHP_BSPI_B1_STATUS_b1_full_DEFAULT 0x00000000
-
-/* BSPI :: B1_STATUS :: b1_empty [28:28] */
-#define BCHP_BSPI_B1_STATUS_b1_empty_MASK 0x10000000
-#define BCHP_BSPI_B1_STATUS_b1_empty_SHIFT 28
-#define BCHP_BSPI_B1_STATUS_b1_empty_DEFAULT 0x00000001
-
-/* BSPI :: B1_STATUS :: b1_miss [27:27] */
-#define BCHP_BSPI_B1_STATUS_b1_miss_MASK 0x08000000
-#define BCHP_BSPI_B1_STATUS_b1_miss_SHIFT 27
-#define BCHP_BSPI_B1_STATUS_b1_miss_DEFAULT 0x00000000
-
-/* BSPI :: B1_STATUS :: b1_hit [26:26] */
-#define BCHP_BSPI_B1_STATUS_b1_hit_MASK 0x04000000
-#define BCHP_BSPI_B1_STATUS_b1_hit_SHIFT 26
-#define BCHP_BSPI_B1_STATUS_b1_hit_DEFAULT 0x00000000
-
-/* BSPI :: B1_STATUS :: b1_address [25:00] */
-#define BCHP_BSPI_B1_STATUS_b1_address_MASK 0x03ffffff
-#define BCHP_BSPI_B1_STATUS_b1_address_SHIFT 0
-#define BCHP_BSPI_B1_STATUS_b1_address_DEFAULT 0x00000000
-
-/***************************************************************************
- *B1_CTRL - Prefetch Buffer 1 Control Register
- ***************************************************************************/
-/* BSPI :: B1_CTRL :: reserved0 [31:01] */
-#define BCHP_BSPI_B1_CTRL_reserved0_MASK 0xfffffffe
-#define BCHP_BSPI_B1_CTRL_reserved0_SHIFT 1
-
-/* BSPI :: B1_CTRL :: b1_flush [00:00] */
-#define BCHP_BSPI_B1_CTRL_b1_flush_MASK 0x00000001
-#define BCHP_BSPI_B1_CTRL_b1_flush_SHIFT 0
-#define BCHP_BSPI_B1_CTRL_b1_flush_DEFAULT 0x00000000
-
-/***************************************************************************
- *STRAP_OVERRIDE_CTRL - Dual/Single Receive Mode Control Register
- ***************************************************************************/
-/* BSPI :: STRAP_OVERRIDE_CTRL :: reserved0 [31:05] */
-#define BCHP_BSPI_STRAP_OVERRIDE_CTRL_reserved0_MASK 0xffffffe0
-#define BCHP_BSPI_STRAP_OVERRIDE_CTRL_reserved0_SHIFT 5
-
-/* BSPI :: STRAP_OVERRIDE_CTRL :: endian_mode [04:04] */
-#define BCHP_BSPI_STRAP_OVERRIDE_CTRL_endian_mode_MASK 0x00000010
-#define BCHP_BSPI_STRAP_OVERRIDE_CTRL_endian_mode_SHIFT 4
-#define BCHP_BSPI_STRAP_OVERRIDE_CTRL_endian_mode_DEFAULT 0x00000000
-
-/* BSPI :: STRAP_OVERRIDE_CTRL :: data_quad [03:03] */
-#define BCHP_BSPI_STRAP_OVERRIDE_CTRL_data_quad_MASK 0x00000008
-#define BCHP_BSPI_STRAP_OVERRIDE_CTRL_data_quad_SHIFT 3
-#define BCHP_BSPI_STRAP_OVERRIDE_CTRL_data_quad_DEFAULT 0x00000000
-
-/* BSPI :: STRAP_OVERRIDE_CTRL :: addr_4byte_n_3byte [02:02] */
-#define BCHP_BSPI_STRAP_OVERRIDE_CTRL_addr_4byte_n_3byte_MASK 0x00000004
-#define BCHP_BSPI_STRAP_OVERRIDE_CTRL_addr_4byte_n_3byte_SHIFT 2
-#define BCHP_BSPI_STRAP_OVERRIDE_CTRL_addr_4byte_n_3byte_DEFAULT 0x00000000
-
-/* BSPI :: STRAP_OVERRIDE_CTRL :: data_dual_n_sgl [01:01] */
-#define BCHP_BSPI_STRAP_OVERRIDE_CTRL_data_dual_n_sgl_MASK 0x00000002
-#define BCHP_BSPI_STRAP_OVERRIDE_CTRL_data_dual_n_sgl_SHIFT 1
-#define BCHP_BSPI_STRAP_OVERRIDE_CTRL_data_dual_n_sgl_DEFAULT 0x00000000
-
-/* BSPI :: STRAP_OVERRIDE_CTRL :: override [00:00] */
-#define BCHP_BSPI_STRAP_OVERRIDE_CTRL_override_MASK 0x00000001
-#define BCHP_BSPI_STRAP_OVERRIDE_CTRL_override_SHIFT 0
-#define BCHP_BSPI_STRAP_OVERRIDE_CTRL_override_DEFAULT 0x00000000
-
-/***************************************************************************
- *FLEX_MODE_ENABLE - Flexible Control Mode Enable Register
- ***************************************************************************/
-/* BSPI :: FLEX_MODE_ENABLE :: reserved0 [31:01] */
-#define BCHP_BSPI_FLEX_MODE_ENABLE_reserved0_MASK 0xfffffffe
-#define BCHP_BSPI_FLEX_MODE_ENABLE_reserved0_SHIFT 1
-
-/* BSPI :: FLEX_MODE_ENABLE :: bspi_flex_mode_enable [00:00] */
-#define BCHP_BSPI_FLEX_MODE_ENABLE_bspi_flex_mode_enable_MASK 0x00000001
-#define BCHP_BSPI_FLEX_MODE_ENABLE_bspi_flex_mode_enable_SHIFT 0
-#define BCHP_BSPI_FLEX_MODE_ENABLE_bspi_flex_mode_enable_DEFAULT 0x00000000
-
-/***************************************************************************
- *BITS_PER_CYCLE - Bits per cycle "b-p-c" Control Register
- ***************************************************************************/
-/* BSPI :: BITS_PER_CYCLE :: reserved0 [31:26] */
-#define BCHP_BSPI_BITS_PER_CYCLE_reserved0_MASK 0xfc000000
-#define BCHP_BSPI_BITS_PER_CYCLE_reserved0_SHIFT 26
-
-/* BSPI :: BITS_PER_CYCLE :: cmd_bpc_select [25:24] */
-#define BCHP_BSPI_BITS_PER_CYCLE_cmd_bpc_select_MASK 0x03000000
-#define BCHP_BSPI_BITS_PER_CYCLE_cmd_bpc_select_SHIFT 24
-#define BCHP_BSPI_BITS_PER_CYCLE_cmd_bpc_select_DEFAULT 0x00000000
-
-/* BSPI :: BITS_PER_CYCLE :: reserved1 [23:18] */
-#define BCHP_BSPI_BITS_PER_CYCLE_reserved1_MASK 0x00fc0000
-#define BCHP_BSPI_BITS_PER_CYCLE_reserved1_SHIFT 18
-
-/* BSPI :: BITS_PER_CYCLE :: addr_bpc_select [17:16] */
-#define BCHP_BSPI_BITS_PER_CYCLE_addr_bpc_select_MASK 0x00030000
-#define BCHP_BSPI_BITS_PER_CYCLE_addr_bpc_select_SHIFT 16
-#define BCHP_BSPI_BITS_PER_CYCLE_addr_bpc_select_DEFAULT 0x00000000
-
-/* BSPI :: BITS_PER_CYCLE :: reserved2 [15:10] */
-#define BCHP_BSPI_BITS_PER_CYCLE_reserved2_MASK 0x0000fc00
-#define BCHP_BSPI_BITS_PER_CYCLE_reserved2_SHIFT 10
-
-/* BSPI :: BITS_PER_CYCLE :: mode_bpc_select [09:08] */
-#define BCHP_BSPI_BITS_PER_CYCLE_mode_bpc_select_MASK 0x00000300
-#define BCHP_BSPI_BITS_PER_CYCLE_mode_bpc_select_SHIFT 8
-#define BCHP_BSPI_BITS_PER_CYCLE_mode_bpc_select_DEFAULT 0x00000000
-
-/* BSPI :: BITS_PER_CYCLE :: reserved3 [07:02] */
-#define BCHP_BSPI_BITS_PER_CYCLE_reserved3_MASK 0x000000fc
-#define BCHP_BSPI_BITS_PER_CYCLE_reserved3_SHIFT 2
-
-/* BSPI :: BITS_PER_CYCLE :: data_bpc_select [01:00] */
-#define BCHP_BSPI_BITS_PER_CYCLE_data_bpc_select_MASK 0x00000003
-#define BCHP_BSPI_BITS_PER_CYCLE_data_bpc_select_SHIFT 0
-#define BCHP_BSPI_BITS_PER_CYCLE_data_bpc_select_DEFAULT 0x00000000
-
-/***************************************************************************
- *BITS_PER_PHASE - Bits per Phase "b-p-p" Control Register
- ***************************************************************************/
-/* BSPI :: BITS_PER_PHASE :: reserved0 [31:25] */
-#define BCHP_BSPI_BITS_PER_PHASE_reserved0_MASK 0xfe000000
-#define BCHP_BSPI_BITS_PER_PHASE_reserved0_SHIFT 25
-
-/* BSPI :: BITS_PER_PHASE :: cmd_bpp_select [24:24] */
-#define BCHP_BSPI_BITS_PER_PHASE_cmd_bpp_select_MASK 0x01000000
-#define BCHP_BSPI_BITS_PER_PHASE_cmd_bpp_select_SHIFT 24
-#define BCHP_BSPI_BITS_PER_PHASE_cmd_bpp_select_DEFAULT 0x00000000
-
-/* BSPI :: BITS_PER_PHASE :: reserved1 [23:17] */
-#define BCHP_BSPI_BITS_PER_PHASE_reserved1_MASK 0x00fe0000
-#define BCHP_BSPI_BITS_PER_PHASE_reserved1_SHIFT 17
-
-/* BSPI :: BITS_PER_PHASE :: addr_bpp_select [16:16] */
-#define BCHP_BSPI_BITS_PER_PHASE_addr_bpp_select_MASK 0x00010000
-#define BCHP_BSPI_BITS_PER_PHASE_addr_bpp_select_SHIFT 16
-#define BCHP_BSPI_BITS_PER_PHASE_addr_bpp_select_DEFAULT 0x00000000
-
-/* BSPI :: BITS_PER_PHASE :: reserved2 [15:09] */
-#define BCHP_BSPI_BITS_PER_PHASE_reserved2_MASK 0x0000fe00
-#define BCHP_BSPI_BITS_PER_PHASE_reserved2_SHIFT 9
-
-/* BSPI :: BITS_PER_PHASE :: mode_bpp [08:08] */
-#define BCHP_BSPI_BITS_PER_PHASE_mode_bpp_MASK 0x00000100
-#define BCHP_BSPI_BITS_PER_PHASE_mode_bpp_SHIFT 8
-#define BCHP_BSPI_BITS_PER_PHASE_mode_bpp_DEFAULT 0x00000000
-
-/* BSPI :: BITS_PER_PHASE :: dummy_cycles [07:00] */
-#define BCHP_BSPI_BITS_PER_PHASE_dummy_cycles_MASK 0x000000ff
-#define BCHP_BSPI_BITS_PER_PHASE_dummy_cycles_SHIFT 0
-#define BCHP_BSPI_BITS_PER_PHASE_dummy_cycles_DEFAULT 0x00000008
-
-/***************************************************************************
- *CMD_AND_MODE_BYTE - Command and Mode Data Register
- ***************************************************************************/
-/* BSPI :: CMD_AND_MODE_BYTE :: reserved0 [31:24] */
-#define BCHP_BSPI_CMD_AND_MODE_BYTE_reserved0_MASK 0xff000000
-#define BCHP_BSPI_CMD_AND_MODE_BYTE_reserved0_SHIFT 24
-
-/* BSPI :: CMD_AND_MODE_BYTE :: bspi_mode_byte [23:16] */
-#define BCHP_BSPI_CMD_AND_MODE_BYTE_bspi_mode_byte_MASK 0x00ff0000
-#define BCHP_BSPI_CMD_AND_MODE_BYTE_bspi_mode_byte_SHIFT 16
-#define BCHP_BSPI_CMD_AND_MODE_BYTE_bspi_mode_byte_DEFAULT 0x00000000
-
-/* BSPI :: CMD_AND_MODE_BYTE :: reserved1 [15:08] */
-#define BCHP_BSPI_CMD_AND_MODE_BYTE_reserved1_MASK 0x0000ff00
-#define BCHP_BSPI_CMD_AND_MODE_BYTE_reserved1_SHIFT 8
-
-/* BSPI :: CMD_AND_MODE_BYTE :: bspi_cmd_byte [07:00] */
-#define BCHP_BSPI_CMD_AND_MODE_BYTE_bspi_cmd_byte_MASK 0x000000ff
-#define BCHP_BSPI_CMD_AND_MODE_BYTE_bspi_cmd_byte_SHIFT 0
-#define BCHP_BSPI_CMD_AND_MODE_BYTE_bspi_cmd_byte_DEFAULT 0x0000000b
-
-/***************************************************************************
- *BSPI_FLASH_UPPER_ADDR_BYTE - Bspi FLash upper address byte register
- ***************************************************************************/
-/* BSPI :: BSPI_FLASH_UPPER_ADDR_BYTE :: bspi_flash_upper_addr [31:24] */
-#define BCHP_BSPI_BSPI_FLASH_UPPER_ADDR_BYTE_bspi_flash_upper_addr_MASK 0xff000000
-#define BCHP_BSPI_BSPI_FLASH_UPPER_ADDR_BYTE_bspi_flash_upper_addr_SHIFT 24
-#define BCHP_BSPI_BSPI_FLASH_UPPER_ADDR_BYTE_bspi_flash_upper_addr_DEFAULT 0x00000000
-
-/* BSPI :: BSPI_FLASH_UPPER_ADDR_BYTE :: reserved0 [23:00] */
-#define BCHP_BSPI_BSPI_FLASH_UPPER_ADDR_BYTE_reserved0_MASK 0x00ffffff
-#define BCHP_BSPI_BSPI_FLASH_UPPER_ADDR_BYTE_reserved0_SHIFT 0
-
-/***************************************************************************
- *BSPI_XOR_VALUE - BSPI FLASH XOR Value Register
- ***************************************************************************/
-/* BSPI :: BSPI_XOR_VALUE :: bspi_xor_value [31:20] */
-#define BCHP_BSPI_BSPI_XOR_VALUE_bspi_xor_value_MASK 0xfff00000
-#define BCHP_BSPI_BSPI_XOR_VALUE_bspi_xor_value_SHIFT 20
-#define BCHP_BSPI_BSPI_XOR_VALUE_bspi_xor_value_DEFAULT 0x00000e00
-
-/* BSPI :: BSPI_XOR_VALUE :: reserved0 [19:00] */
-#define BCHP_BSPI_BSPI_XOR_VALUE_reserved0_MASK 0x000fffff
-#define BCHP_BSPI_BSPI_XOR_VALUE_reserved0_SHIFT 0
-
-/***************************************************************************
- *BSPI_XOR_ENABLE - BSPI FLASH XOR Enable Register
- ***************************************************************************/
-/* BSPI :: BSPI_XOR_ENABLE :: reserved0 [31:01] */
-#define BCHP_BSPI_BSPI_XOR_ENABLE_reserved0_MASK 0xfffffffe
-#define BCHP_BSPI_BSPI_XOR_ENABLE_reserved0_SHIFT 1
-
-/* BSPI :: BSPI_XOR_ENABLE :: bspi_xor_enable [00:00] */
-#define BCHP_BSPI_BSPI_XOR_ENABLE_bspi_xor_enable_MASK 0x00000001
-#define BCHP_BSPI_BSPI_XOR_ENABLE_bspi_xor_enable_SHIFT 0
-#define BCHP_BSPI_BSPI_XOR_ENABLE_bspi_xor_enable_DEFAULT 0x00000001
-
-/***************************************************************************
- *BSPI_PIO_MODE_ENABLE - BSPI Pin Programmed IO Mode Enable Register
- ***************************************************************************/
-/* BSPI :: BSPI_PIO_MODE_ENABLE :: reserved0 [31:01] */
-#define BCHP_BSPI_BSPI_PIO_MODE_ENABLE_reserved0_MASK 0xfffffffe
-#define BCHP_BSPI_BSPI_PIO_MODE_ENABLE_reserved0_SHIFT 1
-
-/* BSPI :: BSPI_PIO_MODE_ENABLE :: bspi_pio_mode [00:00] */
-#define BCHP_BSPI_BSPI_PIO_MODE_ENABLE_bspi_pio_mode_MASK 0x00000001
-#define BCHP_BSPI_BSPI_PIO_MODE_ENABLE_bspi_pio_mode_SHIFT 0
-#define BCHP_BSPI_BSPI_PIO_MODE_ENABLE_bspi_pio_mode_DEFAULT 0x00000000
-
-/***************************************************************************
- *BSPI_PIO_IODIR - BSPI Pin Programmed IO Mode Direction Register
- ***************************************************************************/
-/* BSPI :: BSPI_PIO_IODIR :: reserved0 [31:03] */
-#define BCHP_BSPI_BSPI_PIO_IODIR_reserved0_MASK 0xfffffff8
-#define BCHP_BSPI_BSPI_PIO_IODIR_reserved0_SHIFT 3
-
-/* BSPI :: BSPI_PIO_IODIR :: bspi_pio_dir [02:00] */
-#define BCHP_BSPI_BSPI_PIO_IODIR_bspi_pio_dir_MASK 0x00000007
-#define BCHP_BSPI_BSPI_PIO_IODIR_bspi_pio_dir_SHIFT 0
-#define BCHP_BSPI_BSPI_PIO_IODIR_bspi_pio_dir_DEFAULT 0x00000003
-
-/***************************************************************************
- *BSPI_PIO_DATA - BSPI Pin Programmed IO Mode Data Register
- ***************************************************************************/
-/* BSPI :: BSPI_PIO_DATA :: reserved0 [31:03] */
-#define BCHP_BSPI_BSPI_PIO_DATA_reserved0_MASK 0xfffffff8
-#define BCHP_BSPI_BSPI_PIO_DATA_reserved0_SHIFT 3
-
-/* BSPI :: BSPI_PIO_DATA :: bspi_pio_data [02:00] */
-#define BCHP_BSPI_BSPI_PIO_DATA_bspi_pio_data_MASK 0x00000007
-#define BCHP_BSPI_BSPI_PIO_DATA_bspi_pio_data_SHIFT 0
-#define BCHP_BSPI_BSPI_PIO_DATA_bspi_pio_data_DEFAULT 0x00000000
-
-#endif /* #ifndef BCHP_BSPI_H__ */
-
-/* End of File */
diff --git a/include/linux/brcmstb/7145a0/bchp_bspi_raf.h b/include/linux/brcmstb/7145a0/bchp_bspi_raf.h
deleted file mode 100644
index f186769..0000000
--- a/include/linux/brcmstb/7145a0/bchp_bspi_raf.h
+++ /dev/null
@@ -1,160 +0,0 @@
-/***************************************************************************
- * Copyright (c) 1999-2013, Broadcom Corporation
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
- *
- * Module Description:
- * DO NOT EDIT THIS FILE DIRECTLY
- *
- * This module was generated magically with RDB from a source description
- * file. You must edit the source file for changes to be made to this file.
- *
- *
- * Date: Generated on Sat Apr 6 03:07:51 2013
- * MD5 Checksum d41d8cd98f00b204e9800998ecf8427e
- *
- * Compiled with: RDB Utility combo_header.pl
- * RDB Parser 3.0
- * unknown unknown
- * Perl Interpreter 5.008008
- * Operating System linux
- *
- * Revision History:
- *
- * $brcm_Log: $
- *
- ***************************************************************************/
-
-#ifndef BCHP_BSPI_RAF_H__
-#define BCHP_BSPI_RAF_H__
-
-/***************************************************************************
- *BSPI_RAF - Public Linear Read BSPI Pipe Registers
- ***************************************************************************/
-#define BCHP_BSPI_RAF_START_ADDR 0x203d3300 /* Physical Starting Address Location in Flash device */
-#define BCHP_BSPI_RAF_NUM_WORDS 0x203d3304 /* Number of Words to be fetched */
-#define BCHP_BSPI_RAF_CTRL 0x203d3308 /* RAF Session Control Register */
-#define BCHP_BSPI_RAF_FULLNESS 0x203d330c /* Fullness indicator for the read ahead buffer */
-#define BCHP_BSPI_RAF_WATERMARK 0x203d3310 /* Watermark level in the read ahead buffer that triggers an interrupt */
-#define BCHP_BSPI_RAF_STATUS 0x203d3314 /* Linear Read Status Register */
-#define BCHP_BSPI_RAF_READ_DATA 0x203d3318 /* Read data from Raf-buffer */
-#define BCHP_BSPI_RAF_WORD_CNT 0x203d331c /* Current number of words fetched from Flash */
-#define BCHP_BSPI_RAF_CURR_ADDR 0x203d3320 /* Current read address for the linear read session */
-
-/***************************************************************************
- *START_ADDR - Physical Starting Address Location in Flash device
- ***************************************************************************/
-/* BSPI_RAF :: START_ADDR :: START_ADDR [31:00] */
-#define BCHP_BSPI_RAF_START_ADDR_START_ADDR_MASK 0xffffffff
-#define BCHP_BSPI_RAF_START_ADDR_START_ADDR_SHIFT 0
-#define BCHP_BSPI_RAF_START_ADDR_START_ADDR_DEFAULT 0x00000000
-
-/***************************************************************************
- *NUM_WORDS - Number of Words to be fetched
- ***************************************************************************/
-/* BSPI_RAF :: NUM_WORDS :: NumWords [31:00] */
-#define BCHP_BSPI_RAF_NUM_WORDS_NumWords_MASK 0xffffffff
-#define BCHP_BSPI_RAF_NUM_WORDS_NumWords_SHIFT 0
-#define BCHP_BSPI_RAF_NUM_WORDS_NumWords_DEFAULT 0x00000000
-
-/***************************************************************************
- *CTRL - RAF Session Control Register
- ***************************************************************************/
-/* BSPI_RAF :: CTRL :: reserved0 [31:02] */
-#define BCHP_BSPI_RAF_CTRL_reserved0_MASK 0xfffffffc
-#define BCHP_BSPI_RAF_CTRL_reserved0_SHIFT 2
-
-/* BSPI_RAF :: CTRL :: CLEAR [01:01] */
-#define BCHP_BSPI_RAF_CTRL_CLEAR_MASK 0x00000002
-#define BCHP_BSPI_RAF_CTRL_CLEAR_SHIFT 1
-#define BCHP_BSPI_RAF_CTRL_CLEAR_DEFAULT 0x00000000
-
-/* BSPI_RAF :: CTRL :: START [00:00] */
-#define BCHP_BSPI_RAF_CTRL_START_MASK 0x00000001
-#define BCHP_BSPI_RAF_CTRL_START_SHIFT 0
-#define BCHP_BSPI_RAF_CTRL_START_DEFAULT 0x00000000
-
-/***************************************************************************
- *FULLNESS - Fullness indicator for the read ahead buffer
- ***************************************************************************/
-/* BSPI_RAF :: FULLNESS :: reserved0 [31:07] */
-#define BCHP_BSPI_RAF_FULLNESS_reserved0_MASK 0xffffff80
-#define BCHP_BSPI_RAF_FULLNESS_reserved0_SHIFT 7
-
-/* BSPI_RAF :: FULLNESS :: FULLNESS [06:00] */
-#define BCHP_BSPI_RAF_FULLNESS_FULLNESS_MASK 0x0000007f
-#define BCHP_BSPI_RAF_FULLNESS_FULLNESS_SHIFT 0
-#define BCHP_BSPI_RAF_FULLNESS_FULLNESS_DEFAULT 0x00000000
-
-/***************************************************************************
- *WATERMARK - Watermark level in the read ahead buffer that triggers an interrupt
- ***************************************************************************/
-/* BSPI_RAF :: WATERMARK :: reserved0 [31:02] */
-#define BCHP_BSPI_RAF_WATERMARK_reserved0_MASK 0xfffffffc
-#define BCHP_BSPI_RAF_WATERMARK_reserved0_SHIFT 2
-
-/* BSPI_RAF :: WATERMARK :: FULLNESS_WATERMARK [01:00] */
-#define BCHP_BSPI_RAF_WATERMARK_FULLNESS_WATERMARK_MASK 0x00000003
-#define BCHP_BSPI_RAF_WATERMARK_FULLNESS_WATERMARK_SHIFT 0
-#define BCHP_BSPI_RAF_WATERMARK_FULLNESS_WATERMARK_DEFAULT 0x00000000
-
-/***************************************************************************
- *STATUS - Linear Read Status Register
- ***************************************************************************/
-/* BSPI_RAF :: STATUS :: reserved0 [31:03] */
-#define BCHP_BSPI_RAF_STATUS_reserved0_MASK 0xfffffff8
-#define BCHP_BSPI_RAF_STATUS_reserved0_SHIFT 3
-
-/* BSPI_RAF :: STATUS :: FIFO_FULL [02:02] */
-#define BCHP_BSPI_RAF_STATUS_FIFO_FULL_MASK 0x00000004
-#define BCHP_BSPI_RAF_STATUS_FIFO_FULL_SHIFT 2
-#define BCHP_BSPI_RAF_STATUS_FIFO_FULL_DEFAULT 0x00000000
-
-/* BSPI_RAF :: STATUS :: FIFO_EMPTY [01:01] */
-#define BCHP_BSPI_RAF_STATUS_FIFO_EMPTY_MASK 0x00000002
-#define BCHP_BSPI_RAF_STATUS_FIFO_EMPTY_SHIFT 1
-#define BCHP_BSPI_RAF_STATUS_FIFO_EMPTY_DEFAULT 0x00000001
-
-/* BSPI_RAF :: STATUS :: SESSION_BUSY [00:00] */
-#define BCHP_BSPI_RAF_STATUS_SESSION_BUSY_MASK 0x00000001
-#define BCHP_BSPI_RAF_STATUS_SESSION_BUSY_SHIFT 0
-#define BCHP_BSPI_RAF_STATUS_SESSION_BUSY_DEFAULT 0x00000000
-
-/***************************************************************************
- *READ_DATA - Read data from Raf-buffer
- ***************************************************************************/
-/* BSPI_RAF :: READ_DATA :: DATA [31:00] */
-#define BCHP_BSPI_RAF_READ_DATA_DATA_MASK 0xffffffff
-#define BCHP_BSPI_RAF_READ_DATA_DATA_SHIFT 0
-#define BCHP_BSPI_RAF_READ_DATA_DATA_DEFAULT 0x00000000
-
-/***************************************************************************
- *WORD_CNT - Current number of words fetched from Flash
- ***************************************************************************/
-/* BSPI_RAF :: WORD_CNT :: CURRENT_WORD_COUNT [31:00] */
-#define BCHP_BSPI_RAF_WORD_CNT_CURRENT_WORD_COUNT_MASK 0xffffffff
-#define BCHP_BSPI_RAF_WORD_CNT_CURRENT_WORD_COUNT_SHIFT 0
-#define BCHP_BSPI_RAF_WORD_CNT_CURRENT_WORD_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *CURR_ADDR - Current read address for the linear read session
- ***************************************************************************/
-/* BSPI_RAF :: CURR_ADDR :: CURRENT_ADDRESS [31:00] */
-#define BCHP_BSPI_RAF_CURR_ADDR_CURRENT_ADDRESS_MASK 0xffffffff
-#define BCHP_BSPI_RAF_CURR_ADDR_CURRENT_ADDRESS_SHIFT 0
-#define BCHP_BSPI_RAF_CURR_ADDR_CURRENT_ADDRESS_DEFAULT 0x00000000
-
-#endif /* #ifndef BCHP_BSPI_RAF_H__ */
-
-/* End of File */
diff --git a/include/linux/brcmstb/7145a0/bchp_clkgen.h b/include/linux/brcmstb/7145a0/bchp_clkgen.h
deleted file mode 100644
index 6a5aa68..0000000
--- a/include/linux/brcmstb/7145a0/bchp_clkgen.h
+++ /dev/null
@@ -1,11632 +0,0 @@
-/***************************************************************************
- * Copyright (c) 1999-2013, Broadcom Corporation
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
- *
- * Module Description:
- * DO NOT EDIT THIS FILE DIRECTLY
- *
- * This module was generated magically with RDB from a source description
- * file. You must edit the source file for changes to be made to this file.
- *
- *
- * Date: Generated on Sat Apr 6 03:07:45 2013
- * MD5 Checksum d41d8cd98f00b204e9800998ecf8427e
- *
- * Compiled with: RDB Utility combo_header.pl
- * RDB Parser 3.0
- * unknown unknown
- * Perl Interpreter 5.008008
- * Operating System linux
- *
- * Revision History:
- *
- * $brcm_Log: $
- *
- ***************************************************************************/
-
-#ifndef BCHP_CLKGEN_H__
-#define BCHP_CLKGEN_H__
-
-/***************************************************************************
- *CLKGEN - clkgen registers
- ***************************************************************************/
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_BG_PWRON 0x20480000 /* Bandgap Power on */
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_CHANNEL_CTRL_CH_0 0x20480004 /* PLL CHANNEL control CH 0 */
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_CHANNEL_CTRL_CH_1 0x20480008 /* PLL CHANNEL control CH 1 */
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2 0x2048000c /* PLL CHANNEL control CH 2 */
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3 0x20480010 /* PLL CHANNEL control CH 3 */
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_CHANNEL_CTRL_CH_4 0x20480014 /* PLL CHANNEL control CH 4 */
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_DIV 0x20480018 /* Pre multiplier */
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_GAIN 0x2048001c /* PLL GAIN */
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_HOLD_CH_ALL 0x20480020 /* Hold PLL all channels */
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_LDO_CTRL 0x20480024 /* Ldo voltage control */
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_LDO_PWRON 0x20480028 /* LDO Power on */
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_LOCK_STATUS 0x2048002c /* Lock Status */
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_MISC 0x20480030 /* Mscellaneous control bus. */
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_MISC2 0x20480034 /* Mscellaneous control bus continued. */
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_PWRON 0x20480038 /* Poweron */
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_RESET 0x2048003c /* Resets */
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_SSC_MODE_CONTROL_HIGH 0x20480040 /* Higher bits of Spread Spectrum mode control */
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_SSC_MODE_CONTROL_LOW 0x20480044 /* Lower bits of Spread Spectrum mode control */
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_STATUS 0x20480048 /* Status */
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_BG_PWRON 0x2048004c /* Bandgap Power on */
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_CHANNEL_CTRL_CH_0 0x20480050 /* PLL CHANNEL control CH 0 */
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_CHANNEL_CTRL_CH_1 0x20480054 /* PLL CHANNEL control CH 1 */
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_CHANNEL_CTRL_CH_2 0x20480058 /* PLL CHANNEL control CH 2 */
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_CHANNEL_CTRL_CH_3 0x2048005c /* PLL CHANNEL control CH 3 */
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_CHANNEL_CTRL_CH_4 0x20480060 /* PLL CHANNEL control CH 4 */
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_DIV 0x20480064 /* Pre multiplier */
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_GAIN 0x20480068 /* PLL GAIN */
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_HOLD_CH_ALL 0x2048006c /* Hold PLL all channels */
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_LDO_CTRL 0x20480070 /* Ldo voltage control */
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_LDO_PWRON 0x20480074 /* LDO Power on */
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_LOCK_STATUS 0x20480078 /* Lock Status */
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_MISC 0x2048007c /* Mscellaneous control bus. */
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_MISC2 0x20480080 /* Mscellaneous control bus continued. */
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_PWRON 0x20480084 /* Poweron */
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_RESET 0x20480088 /* Resets */
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_SSC_MODE_CONTROL_HIGH 0x2048008c /* Higher bits of Spread Spectrum mode control */
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_SSC_MODE_CONTROL_LOW 0x20480090 /* Lower bits of Spread Spectrum mode control */
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_STATUS 0x20480094 /* Status */
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_BG_PWRON 0x20480098 /* Bandgap Power on */
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_CHANNEL_CTRL_CH_2 0x2048009c /* PLL CHANNEL control CH 2 */
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_DIV 0x204800a0 /* Pre multiplier */
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_GAIN 0x204800a4 /* PLL GAIN */
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_HOLD_CH_ALL 0x204800a8 /* Hold PLL all channels */
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_LDO_CTRL 0x204800ac /* Ldo voltage control */
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_LDO_PWRON 0x204800b0 /* LDO Power on */
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_LOCK_STATUS 0x204800b4 /* Lock Status */
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_MISC 0x204800b8 /* Mscellaneous control bus. */
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_MISC2 0x204800bc /* Mscellaneous control bus continued. */
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_PWRON 0x204800c0 /* Poweron */
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_RESET 0x204800c4 /* Resets */
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_SSC_MODE_CONTROL_HIGH 0x204800c8 /* Higher bits of Spread Spectrum mode control */
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_SSC_MODE_CONTROL_LOW 0x204800cc /* Lower bits of Spread Spectrum mode control */
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_STATUS 0x204800d0 /* Status */
-#define BCHP_CLKGEN_PLL_AUDIO0_PLL_BG_PWRON 0x204800d4 /* Bandgap Power on */
-#define BCHP_CLKGEN_PLL_AUDIO0_PLL_DIV 0x204800d8 /* Pre multiplier */
-#define BCHP_CLKGEN_PLL_AUDIO0_PLL_GAIN 0x204800dc /* PLL GAIN */
-#define BCHP_CLKGEN_PLL_AUDIO0_PLL_LDO_CTRL 0x204800e0 /* Ldo voltage control */
-#define BCHP_CLKGEN_PLL_AUDIO0_PLL_LDO_PWRON 0x204800e4 /* LDO Power on */
-#define BCHP_CLKGEN_PLL_AUDIO0_PLL_LOCK_STATUS 0x204800e8 /* Lock Status */
-#define BCHP_CLKGEN_PLL_AUDIO0_PLL_PWRON 0x204800ec /* Poweron */
-#define BCHP_CLKGEN_PLL_AUDIO0_PLL_RESET 0x204800f0 /* Resets */
-#define BCHP_CLKGEN_PLL_AUDIO0_PLL_SSC_MODE_CONTROL_HIGH 0x204800f4 /* Higher bits of Spread Spectrum mode control */
-#define BCHP_CLKGEN_PLL_AUDIO0_PLL_SSC_MODE_CONTROL_LOW 0x204800f8 /* Lower bits of Spread Spectrum mode control */
-#define BCHP_CLKGEN_PLL_AUDIO0_PLL_STATUS 0x204800fc /* Status */
-#define BCHP_CLKGEN_PLL_AUDIO1_PLL_BG_PWRON 0x20480100 /* Bandgap Power on */
-#define BCHP_CLKGEN_PLL_AUDIO1_PLL_DIV 0x20480104 /* Pre multiplier */
-#define BCHP_CLKGEN_PLL_AUDIO1_PLL_GAIN 0x20480108 /* PLL GAIN */
-#define BCHP_CLKGEN_PLL_AUDIO1_PLL_LDO_CTRL 0x2048010c /* Ldo voltage control */
-#define BCHP_CLKGEN_PLL_AUDIO1_PLL_LDO_PWRON 0x20480110 /* LDO Power on */
-#define BCHP_CLKGEN_PLL_AUDIO1_PLL_LOCK_STATUS 0x20480114 /* Lock Status */
-#define BCHP_CLKGEN_PLL_AUDIO1_PLL_PWRON 0x20480118 /* Poweron */
-#define BCHP_CLKGEN_PLL_AUDIO1_PLL_RESET 0x2048011c /* Resets */
-#define BCHP_CLKGEN_PLL_AUDIO1_PLL_SSC_MODE_CONTROL_HIGH 0x20480120 /* Higher bits of Spread Spectrum mode control */
-#define BCHP_CLKGEN_PLL_AUDIO1_PLL_SSC_MODE_CONTROL_LOW 0x20480124 /* Lower bits of Spread Spectrum mode control */
-#define BCHP_CLKGEN_PLL_AUDIO1_PLL_STATUS 0x20480128 /* Status */
-#define BCHP_CLKGEN_PLL_AUDIO2_PLL_BG_PWRON 0x2048012c /* Bandgap Power on */
-#define BCHP_CLKGEN_PLL_AUDIO2_PLL_DIV 0x20480130 /* Pre multiplier */
-#define BCHP_CLKGEN_PLL_AUDIO2_PLL_GAIN 0x20480134 /* PLL GAIN */
-#define BCHP_CLKGEN_PLL_AUDIO2_PLL_LDO_CTRL 0x20480138 /* Ldo voltage control */
-#define BCHP_CLKGEN_PLL_AUDIO2_PLL_LDO_PWRON 0x2048013c /* LDO Power on */
-#define BCHP_CLKGEN_PLL_AUDIO2_PLL_LOCK_STATUS 0x20480140 /* Lock Status */
-#define BCHP_CLKGEN_PLL_AUDIO2_PLL_PWRON 0x20480144 /* Poweron */
-#define BCHP_CLKGEN_PLL_AUDIO2_PLL_RESET 0x20480148 /* Resets */
-#define BCHP_CLKGEN_PLL_AUDIO2_PLL_SSC_MODE_CONTROL_HIGH 0x2048014c /* Higher bits of Spread Spectrum mode control */
-#define BCHP_CLKGEN_PLL_AUDIO2_PLL_SSC_MODE_CONTROL_LOW 0x20480150 /* Lower bits of Spread Spectrum mode control */
-#define BCHP_CLKGEN_PLL_AUDIO2_PLL_STATUS 0x20480154 /* Status */
-#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_0 0x20480158 /* PLL CHANNEL control CH 0 */
-#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_1 0x2048015c /* PLL CHANNEL control CH 1 */
-#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_2 0x20480160 /* PLL CHANNEL control CH 2 */
-#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_3 0x20480164 /* PLL CHANNEL control CH 3 */
-#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_4 0x20480168 /* PLL CHANNEL control CH 4 */
-#define BCHP_CLKGEN_PLL_AVD_PLL_DIV 0x2048016c /* Pre multiplier */
-#define BCHP_CLKGEN_PLL_AVD_PLL_GAIN 0x20480170 /* PLL GAIN */
-#define BCHP_CLKGEN_PLL_AVD_PLL_LDO_PWRON 0x20480174 /* LDO Power on */
-#define BCHP_CLKGEN_PLL_AVD_PLL_LOCK_STATUS 0x20480178 /* Lock Status */
-#define BCHP_CLKGEN_PLL_AVD_PLL_MISC 0x2048017c /* Mscellaneous control bus. */
-#define BCHP_CLKGEN_PLL_AVD_PLL_MISC2 0x20480180 /* Mscellaneous control bus continued. */
-#define BCHP_CLKGEN_PLL_AVD_PLL_PWRON 0x20480184 /* Poweron */
-#define BCHP_CLKGEN_PLL_AVD_PLL_RESET 0x20480188 /* Resets */
-#define BCHP_CLKGEN_PLL_AVD_PLL_SSC_MODE_CONTROL_HIGH 0x2048018c /* Higher bits of Spread Spectrum mode control */
-#define BCHP_CLKGEN_PLL_AVD_PLL_SSC_MODE_CONTROL_LOW 0x20480190 /* Lower bits of Spread Spectrum mode control */
-#define BCHP_CLKGEN_PLL_AVD_PLL_STATUS 0x20480194 /* Status */
-#define BCHP_CLKGEN_PLL_CPU_CORE_PLL_CHANNEL_CTRL_CH_0 0x20480198 /* PLL CHANNEL control CH 0 */
-#define BCHP_CLKGEN_PLL_CPU_CORE_PLL_CHANNEL_CTRL_CH_1 0x2048019c /* PLL CHANNEL control CH 1 */
-#define BCHP_CLKGEN_PLL_CPU_CORE_PLL_DIV 0x204801a0 /* Pre multiplier */
-#define BCHP_CLKGEN_PLL_CPU_CORE_PLL_FRAC 0x204801a4 /* Fractional */
-#define BCHP_CLKGEN_PLL_CPU_CORE_PLL_GAIN 0x204801a8 /* PLL GAIN */
-#define BCHP_CLKGEN_PLL_CPU_CORE_PLL_LDO_PWRON 0x204801ac /* LDO Power on */
-#define BCHP_CLKGEN_PLL_CPU_CORE_PLL_LOCK_STATUS 0x204801b0 /* Lock Status */
-#define BCHP_CLKGEN_PLL_CPU_CORE_PLL_MISC 0x204801b4 /* Mscellaneous control bus. */
-#define BCHP_CLKGEN_PLL_CPU_CORE_PLL_MISC2 0x204801b8 /* Mscellaneous control bus continued. */
-#define BCHP_CLKGEN_PLL_CPU_CORE_PLL_PWRON 0x204801bc /* Poweron */
-#define BCHP_CLKGEN_PLL_CPU_CORE_PLL_RESET 0x204801c0 /* Resets */
-#define BCHP_CLKGEN_PLL_CPU_CORE_PLL_SSC_MODE_CONTROL_HIGH 0x204801c4 /* Higher bits of Spread Spectrum mode control */
-#define BCHP_CLKGEN_PLL_CPU_CORE_PLL_SSC_MODE_CONTROL_LOW 0x204801c8 /* Lower bits of Spread Spectrum mode control */
-#define BCHP_CLKGEN_PLL_CPU_CORE_PLL_STATUS 0x204801cc /* Status */
-#define BCHP_CLKGEN_PLL_CPU_ROUTER_PLL_CHANNEL_CTRL_CH_0 0x204801d0 /* PLL CHANNEL control CH 0 */
-#define BCHP_CLKGEN_PLL_CPU_ROUTER_PLL_CHANNEL_CTRL_CH_1 0x204801d4 /* PLL CHANNEL control CH 1 */
-#define BCHP_CLKGEN_PLL_CPU_ROUTER_PLL_DIV 0x204801d8 /* Pre multiplier */
-#define BCHP_CLKGEN_PLL_CPU_ROUTER_PLL_FRAC 0x204801dc /* Fractional */
-#define BCHP_CLKGEN_PLL_CPU_ROUTER_PLL_GAIN 0x204801e0 /* PLL GAIN */
-#define BCHP_CLKGEN_PLL_CPU_ROUTER_PLL_LDO_PWRON 0x204801e4 /* LDO Power on */
-#define BCHP_CLKGEN_PLL_CPU_ROUTER_PLL_LOCK_STATUS 0x204801e8 /* Lock Status */
-#define BCHP_CLKGEN_PLL_CPU_ROUTER_PLL_MISC 0x204801ec /* Mscellaneous control bus. */
-#define BCHP_CLKGEN_PLL_CPU_ROUTER_PLL_MISC2 0x204801f0 /* Mscellaneous control bus continued. */
-#define BCHP_CLKGEN_PLL_CPU_ROUTER_PLL_PWRON 0x204801f4 /* Poweron */
-#define BCHP_CLKGEN_PLL_CPU_ROUTER_PLL_RESET 0x204801f8 /* Resets */
-#define BCHP_CLKGEN_PLL_CPU_ROUTER_PLL_SSC_MODE_CONTROL_HIGH 0x204801fc /* Higher bits of Spread Spectrum mode control */
-#define BCHP_CLKGEN_PLL_CPU_ROUTER_PLL_SSC_MODE_CONTROL_LOW 0x20480200 /* Lower bits of Spread Spectrum mode control */
-#define BCHP_CLKGEN_PLL_CPU_ROUTER_PLL_STATUS 0x20480204 /* Status */
-#define BCHP_CLKGEN_PLL_LC_PLL_CHANNEL_CTRL_CH_0 0x20480208 /* PLL CHANNEL control CH 0 */
-#define BCHP_CLKGEN_PLL_LC_PLL_CHANNEL_CTRL_CH_1 0x2048020c /* PLL CHANNEL control CH 1 */
-#define BCHP_CLKGEN_PLL_LC_PLL_CHANNEL_CTRL_CH_2 0x20480210 /* PLL CHANNEL control CH 2 */
-#define BCHP_CLKGEN_PLL_LC_PLL_CHANNEL_CTRL_CH_3 0x20480214 /* PLL CHANNEL control CH 3 */
-#define BCHP_CLKGEN_PLL_LC_PLL_CONTROL 0x20480218 /* Miscellaneous Controls */
-#define BCHP_CLKGEN_PLL_LC_PLL_DIV 0x2048021c /* Pre multiplier */
-#define BCHP_CLKGEN_PLL_LC_PLL_GAIN 0x20480220 /* PLL GAIN */
-#define BCHP_CLKGEN_PLL_LC_PLL_HOLD_CH_ALL 0x20480224 /* Hold PLL all channels */
-#define BCHP_CLKGEN_PLL_LC_PLL_LDO_CTRL 0x20480228 /* Ldo voltage control */
-#define BCHP_CLKGEN_PLL_LC_PLL_LDO_PWRON 0x2048022c /* LDO Power on */
-#define BCHP_CLKGEN_PLL_LC_PLL_LOCK_STATUS 0x20480230 /* Lock Status */
-#define BCHP_CLKGEN_PLL_LC_PLL_MISC 0x20480234 /* Mscellaneous control bus. */
-#define BCHP_CLKGEN_PLL_LC_PLL_MISC2 0x20480238 /* Mscellaneous control bus continued. */
-#define BCHP_CLKGEN_PLL_LC_PLL_OUTSEL_SEL 0x2048023c /* selection of the output clock from the PLL core */
-#define BCHP_CLKGEN_PLL_LC_PLL_PWRON 0x20480240 /* Poweron */
-#define BCHP_CLKGEN_PLL_LC_PLL_RESET 0x20480244 /* Resets */
-#define BCHP_CLKGEN_PLL_LC_PLL_STATUS 0x20480248 /* Status */
-#define BCHP_CLKGEN_PLL_LC_PLL_TEST 0x2048024c /* enable and selection pf PLL test */
-#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_0 0x20480250 /* PLL CHANNEL control CH 0 */
-#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_1 0x20480254 /* PLL CHANNEL control CH 1 */
-#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_2 0x20480258 /* PLL CHANNEL control CH 2 */
-#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_3 0x2048025c /* PLL CHANNEL control CH 3 */
-#define BCHP_CLKGEN_PLL_MOCA_PLL_DIV 0x20480260 /* Pre multiplier */
-#define BCHP_CLKGEN_PLL_MOCA_PLL_GAIN 0x20480264 /* PLL GAIN */
-#define BCHP_CLKGEN_PLL_MOCA_PLL_LDO_PWRON 0x20480268 /* LDO Power on */
-#define BCHP_CLKGEN_PLL_MOCA_PLL_LOCK_STATUS 0x2048026c /* Lock Status */
-#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC 0x20480270 /* Mscellaneous control bus. */
-#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC2 0x20480274 /* Mscellaneous control bus continued. */
-#define BCHP_CLKGEN_PLL_MOCA_PLL_PWRON 0x20480278 /* Poweron */
-#define BCHP_CLKGEN_PLL_MOCA_PLL_RESET 0x2048027c /* Resets */
-#define BCHP_CLKGEN_PLL_MOCA_PLL_SSC_MODE_CONTROL_HIGH 0x20480280 /* Higher bits of Spread Spectrum mode control */
-#define BCHP_CLKGEN_PLL_MOCA_PLL_SSC_MODE_CONTROL_LOW 0x20480284 /* Lower bits of Spread Spectrum mode control */
-#define BCHP_CLKGEN_PLL_MOCA_PLL_STATUS 0x20480288 /* Status */
-#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_0 0x2048028c /* PLL CHANNEL control CH 0 */
-#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_1 0x20480290 /* PLL CHANNEL control CH 1 */
-#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_2 0x20480294 /* PLL CHANNEL control CH 2 */
-#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_3 0x20480298 /* PLL CHANNEL control CH 3 */
-#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_4 0x2048029c /* PLL CHANNEL control CH 4 */
-#define BCHP_CLKGEN_PLL_RAAGA_PLL_DIV 0x204802a0 /* Pre multiplier */
-#define BCHP_CLKGEN_PLL_RAAGA_PLL_GAIN 0x204802a4 /* PLL GAIN */
-#define BCHP_CLKGEN_PLL_RAAGA_PLL_LDO_PWRON 0x204802a8 /* LDO Power on */
-#define BCHP_CLKGEN_PLL_RAAGA_PLL_LOCK_STATUS 0x204802ac /* Lock Status */
-#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC 0x204802b0 /* Mscellaneous control bus. */
-#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC2 0x204802b4 /* Mscellaneous control bus continued. */
-#define BCHP_CLKGEN_PLL_RAAGA_PLL_PWRON 0x204802b8 /* Poweron */
-#define BCHP_CLKGEN_PLL_RAAGA_PLL_RESET 0x204802bc /* Resets */
-#define BCHP_CLKGEN_PLL_RAAGA_PLL_SSC_MODE_CONTROL_HIGH 0x204802c0 /* Higher bits of Spread Spectrum mode control */
-#define BCHP_CLKGEN_PLL_RAAGA_PLL_SSC_MODE_CONTROL_LOW 0x204802c4 /* Lower bits of Spread Spectrum mode control */
-#define BCHP_CLKGEN_PLL_RAAGA_PLL_STATUS 0x204802c8 /* Status */
-#define BCHP_CLKGEN_PLL_SC0_PLL_CHANNEL_CTRL_CH_0 0x204802cc /* PLL CHANNEL control CH 0 */
-#define BCHP_CLKGEN_PLL_SC0_PLL_DIV 0x204802d0 /* Pre multiplier */
-#define BCHP_CLKGEN_PLL_SC0_PLL_FRAC 0x204802d4 /* Fractional */
-#define BCHP_CLKGEN_PLL_SC0_PLL_GAIN 0x204802d8 /* PLL GAIN */
-#define BCHP_CLKGEN_PLL_SC0_PLL_LDO_PWRON 0x204802dc /* LDO Power on */
-#define BCHP_CLKGEN_PLL_SC0_PLL_LOCK_STATUS 0x204802e0 /* Lock Status */
-#define BCHP_CLKGEN_PLL_SC0_PLL_MISC 0x204802e4 /* Mscellaneous control bus. */
-#define BCHP_CLKGEN_PLL_SC0_PLL_MISC2 0x204802e8 /* Mscellaneous control bus continued. */
-#define BCHP_CLKGEN_PLL_SC0_PLL_PWRON 0x204802ec /* Poweron */
-#define BCHP_CLKGEN_PLL_SC0_PLL_RESET 0x204802f0 /* Resets */
-#define BCHP_CLKGEN_PLL_SC0_PLL_SSC_MODE_CONTROL_HIGH 0x204802f4 /* Higher bits of Spread Spectrum mode control */
-#define BCHP_CLKGEN_PLL_SC0_PLL_SSC_MODE_CONTROL_LOW 0x204802f8 /* Lower bits of Spread Spectrum mode control */
-#define BCHP_CLKGEN_PLL_SC0_PLL_STATUS 0x204802fc /* Status */
-#define BCHP_CLKGEN_PLL_SC1_PLL_CHANNEL_CTRL_CH_0 0x20480300 /* PLL CHANNEL control CH 0 */
-#define BCHP_CLKGEN_PLL_SC1_PLL_DIV 0x20480304 /* Pre multiplier */
-#define BCHP_CLKGEN_PLL_SC1_PLL_FRAC 0x20480308 /* Fractional */
-#define BCHP_CLKGEN_PLL_SC1_PLL_GAIN 0x2048030c /* PLL GAIN */
-#define BCHP_CLKGEN_PLL_SC1_PLL_LDO_PWRON 0x20480310 /* LDO Power on */
-#define BCHP_CLKGEN_PLL_SC1_PLL_LOCK_STATUS 0x20480314 /* Lock Status */
-#define BCHP_CLKGEN_PLL_SC1_PLL_MISC 0x20480318 /* Mscellaneous control bus. */
-#define BCHP_CLKGEN_PLL_SC1_PLL_MISC2 0x2048031c /* Mscellaneous control bus continued. */
-#define BCHP_CLKGEN_PLL_SC1_PLL_PWRON 0x20480320 /* Poweron */
-#define BCHP_CLKGEN_PLL_SC1_PLL_RESET 0x20480324 /* Resets */
-#define BCHP_CLKGEN_PLL_SC1_PLL_SSC_MODE_CONTROL_HIGH 0x20480328 /* Higher bits of Spread Spectrum mode control */
-#define BCHP_CLKGEN_PLL_SC1_PLL_SSC_MODE_CONTROL_LOW 0x2048032c /* Lower bits of Spread Spectrum mode control */
-#define BCHP_CLKGEN_PLL_SC1_PLL_STATUS 0x20480330 /* Status */
-#define BCHP_CLKGEN_PLL_SWITCH_PLL_CHANNEL_CTRL_CH_0 0x20480334 /* PLL CHANNEL control CH 0 */
-#define BCHP_CLKGEN_PLL_SWITCH_PLL_CHANNEL_CTRL_CH_1 0x20480338 /* PLL CHANNEL control CH 1 */
-#define BCHP_CLKGEN_PLL_SWITCH_PLL_CHANNEL_CTRL_CH_3 0x2048033c /* PLL CHANNEL control CH 3 */
-#define BCHP_CLKGEN_PLL_SWITCH_PLL_DIV 0x20480340 /* Pre multiplier */
-#define BCHP_CLKGEN_PLL_SWITCH_PLL_GAIN 0x20480344 /* PLL GAIN */
-#define BCHP_CLKGEN_PLL_SWITCH_PLL_LDO_PWRON 0x20480348 /* LDO Power on */
-#define BCHP_CLKGEN_PLL_SWITCH_PLL_LOCK_STATUS 0x2048034c /* Lock Status */
-#define BCHP_CLKGEN_PLL_SWITCH_PLL_MISC 0x20480350 /* Mscellaneous control bus. */
-#define BCHP_CLKGEN_PLL_SWITCH_PLL_MISC2 0x20480354 /* Mscellaneous control bus continued. */
-#define BCHP_CLKGEN_PLL_SWITCH_PLL_PWRON 0x20480358 /* Poweron */
-#define BCHP_CLKGEN_PLL_SWITCH_PLL_RESET 0x2048035c /* Resets */
-#define BCHP_CLKGEN_PLL_SWITCH_PLL_SSC_MODE_CONTROL_HIGH 0x20480360 /* Higher bits of Spread Spectrum mode control */
-#define BCHP_CLKGEN_PLL_SWITCH_PLL_SSC_MODE_CONTROL_LOW 0x20480364 /* Lower bits of Spread Spectrum mode control */
-#define BCHP_CLKGEN_PLL_SWITCH_PLL_STATUS 0x20480368 /* Status */
-#define BCHP_CLKGEN_PLL_SYS0_PLL_BG_PWRON 0x2048036c /* Bandgap Power on */
-#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_0 0x20480370 /* PLL CHANNEL control CH 0 */
-#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_1 0x20480374 /* PLL CHANNEL control CH 1 */
-#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2 0x20480378 /* PLL CHANNEL control CH 2 */
-#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3 0x2048037c /* PLL CHANNEL control CH 3 */
-#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_4 0x20480380 /* PLL CHANNEL control CH 4 */
-#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_5 0x20480384 /* PLL CHANNEL control CH 5 */
-#define BCHP_CLKGEN_PLL_SYS0_PLL_DIV 0x20480388 /* Pre multiplier */
-#define BCHP_CLKGEN_PLL_SYS0_PLL_GAIN 0x2048038c /* PLL GAIN */
-#define BCHP_CLKGEN_PLL_SYS0_PLL_HOLD_CH_ALL 0x20480390 /* Hold PLL all channels */
-#define BCHP_CLKGEN_PLL_SYS0_PLL_LDO_CTRL 0x20480394 /* Ldo voltage control */
-#define BCHP_CLKGEN_PLL_SYS0_PLL_LDO_PWRON 0x20480398 /* LDO Power on */
-#define BCHP_CLKGEN_PLL_SYS0_PLL_LOCK_STATUS 0x2048039c /* Lock Status */
-#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC 0x204803a0 /* Mscellaneous control bus. */
-#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC2 0x204803a4 /* Mscellaneous control bus continued. */
-#define BCHP_CLKGEN_PLL_SYS0_PLL_PWRON 0x204803a8 /* Poweron */
-#define BCHP_CLKGEN_PLL_SYS0_PLL_RESET 0x204803ac /* Resets */
-#define BCHP_CLKGEN_PLL_SYS0_PLL_SSC_MODE_CONTROL_HIGH 0x204803b0 /* Higher bits of Spread Spectrum mode control */
-#define BCHP_CLKGEN_PLL_SYS0_PLL_SSC_MODE_CONTROL_LOW 0x204803b4 /* Lower bits of Spread Spectrum mode control */
-#define BCHP_CLKGEN_PLL_SYS0_PLL_STATUS 0x204803b8 /* Status */
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_BG_PWRON 0x204803bc /* Bandgap Power on */
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_CHANNEL_CTRL_CH_0 0x204803c0 /* PLL CHANNEL control CH 0 */
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_CHANNEL_CTRL_CH_1 0x204803c4 /* PLL CHANNEL control CH 1 */
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_CHANNEL_CTRL_CH_2 0x204803c8 /* PLL CHANNEL control CH 2 */
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_DIV 0x204803cc /* Pre multiplier */
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_FRAC 0x204803d0 /* Fractional */
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_GAIN 0x204803d4 /* PLL GAIN */
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_HOLD_CH_ALL 0x204803d8 /* Hold PLL all channels */
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_LDO_CTRL 0x204803dc /* Ldo voltage control */
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_LDO_PWRON 0x204803e0 /* LDO Power on */
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_LOCK_STATUS 0x204803e4 /* Lock Status */
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_MISC 0x204803e8 /* Mscellaneous control bus. */
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_MISC2 0x204803ec /* Mscellaneous control bus continued. */
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_PWRON 0x204803f0 /* Poweron */
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_RESET 0x204803f4 /* Resets */
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_SSC_MODE_CONTROL_HIGH 0x204803f8 /* Higher bits of Spread Spectrum mode control */
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_SSC_MODE_CONTROL_LOW 0x204803fc /* Lower bits of Spread Spectrum mode control */
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_STATUS 0x20480400 /* Status */
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_BG_PWRON 0x20480404 /* Bandgap Power on */
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_CHANNEL_CTRL_CH_0 0x20480408 /* PLL CHANNEL control CH 0 */
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_CHANNEL_CTRL_CH_1 0x2048040c /* PLL CHANNEL control CH 1 */
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_CHANNEL_CTRL_CH_2 0x20480410 /* PLL CHANNEL control CH 2 */
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_DIV 0x20480414 /* Pre multiplier */
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_FRAC 0x20480418 /* Fractional */
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_GAIN 0x2048041c /* PLL GAIN */
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_HOLD_CH_ALL 0x20480420 /* Hold PLL all channels */
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_LDO_CTRL 0x20480424 /* Ldo voltage control */
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_LDO_PWRON 0x20480428 /* LDO Power on */
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_LOCK_STATUS 0x2048042c /* Lock Status */
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_MISC 0x20480430 /* Mscellaneous control bus. */
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_MISC2 0x20480434 /* Mscellaneous control bus continued. */
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_PWRON 0x20480438 /* Poweron */
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_RESET 0x2048043c /* Resets */
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_SSC_MODE_CONTROL_HIGH 0x20480440 /* Higher bits of Spread Spectrum mode control */
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_SSC_MODE_CONTROL_LOW 0x20480444 /* Lower bits of Spread Spectrum mode control */
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_STATUS 0x20480448 /* Status */
-#define BCHP_CLKGEN_PLL_VCXO2_PLL_BG_PWRON 0x2048044c /* Bandgap Power on */
-#define BCHP_CLKGEN_PLL_VCXO2_PLL_CHANNEL_CTRL_CH_0 0x20480450 /* PLL CHANNEL control CH 0 */
-#define BCHP_CLKGEN_PLL_VCXO2_PLL_CHANNEL_CTRL_CH_1 0x20480454 /* PLL CHANNEL control CH 1 */
-#define BCHP_CLKGEN_PLL_VCXO2_PLL_CHANNEL_CTRL_CH_2 0x20480458 /* PLL CHANNEL control CH 2 */
-#define BCHP_CLKGEN_PLL_VCXO2_PLL_DIV 0x2048045c /* Pre multiplier */
-#define BCHP_CLKGEN_PLL_VCXO2_PLL_FRAC 0x20480460 /* Fractional */
-#define BCHP_CLKGEN_PLL_VCXO2_PLL_GAIN 0x20480464 /* PLL GAIN */
-#define BCHP_CLKGEN_PLL_VCXO2_PLL_HOLD_CH_ALL 0x20480468 /* Hold PLL all channels */
-#define BCHP_CLKGEN_PLL_VCXO2_PLL_LDO_CTRL 0x2048046c /* Ldo voltage control */
-#define BCHP_CLKGEN_PLL_VCXO2_PLL_LDO_PWRON 0x20480470 /* LDO Power on */
-#define BCHP_CLKGEN_PLL_VCXO2_PLL_LOCK_STATUS 0x20480474 /* Lock Status */
-#define BCHP_CLKGEN_PLL_VCXO2_PLL_MISC 0x20480478 /* Mscellaneous control bus. */
-#define BCHP_CLKGEN_PLL_VCXO2_PLL_MISC2 0x2048047c /* Mscellaneous control bus continued. */
-#define BCHP_CLKGEN_PLL_VCXO2_PLL_PWRON 0x20480480 /* Poweron */
-#define BCHP_CLKGEN_PLL_VCXO2_PLL_RESET 0x20480484 /* Resets */
-#define BCHP_CLKGEN_PLL_VCXO2_PLL_SSC_MODE_CONTROL_HIGH 0x20480488 /* Higher bits of Spread Spectrum mode control */
-#define BCHP_CLKGEN_PLL_VCXO2_PLL_SSC_MODE_CONTROL_LOW 0x2048048c /* Lower bits of Spread Spectrum mode control */
-#define BCHP_CLKGEN_PLL_VCXO2_PLL_STATUS 0x20480490 /* Status */
-#define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_0 0x20480494 /* PLL CHANNEL control CH 0 */
-#define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_1 0x20480498 /* PLL CHANNEL control CH 1 */
-#define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_2 0x2048049c /* PLL CHANNEL control CH 2 */
-#define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_3 0x204804a0 /* PLL CHANNEL control CH 3 */
-#define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_4 0x204804a4 /* PLL CHANNEL control CH 4 */
-#define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_5 0x204804a8 /* PLL CHANNEL control CH 5 */
-#define BCHP_CLKGEN_PLL_XPT_PLL_DIV 0x204804ac /* Pre multiplier */
-#define BCHP_CLKGEN_PLL_XPT_PLL_GAIN 0x204804b0 /* PLL GAIN */
-#define BCHP_CLKGEN_PLL_XPT_PLL_LDO_PWRON 0x204804b4 /* LDO Power on */
-#define BCHP_CLKGEN_PLL_XPT_PLL_LOCK_STATUS 0x204804b8 /* Lock Status */
-#define BCHP_CLKGEN_PLL_XPT_PLL_MISC 0x204804bc /* Mscellaneous control bus. */
-#define BCHP_CLKGEN_PLL_XPT_PLL_MISC2 0x204804c0 /* Mscellaneous control bus continued. */
-#define BCHP_CLKGEN_PLL_XPT_PLL_PWRON 0x204804c4 /* Poweron */
-#define BCHP_CLKGEN_PLL_XPT_PLL_RESET 0x204804c8 /* Resets */
-#define BCHP_CLKGEN_PLL_XPT_PLL_SSC_MODE_CONTROL_HIGH 0x204804cc /* Higher bits of Spread Spectrum mode control */
-#define BCHP_CLKGEN_PLL_XPT_PLL_SSC_MODE_CONTROL_LOW 0x204804d0 /* Lower bits of Spread Spectrum mode control */
-#define BCHP_CLKGEN_PLL_XPT_PLL_STATUS 0x204804d4 /* Status */
-#define BCHP_CLKGEN_ANA_QDAC_TS28HPM_6MX_2MR_FC_H_E_INST_CLOCK_DISABLE 0x204804d8 /* Disable ANA_QDAC_TS28HPM_6MX_2MR_FC_H_E_INST's clocks */
-#define BCHP_CLKGEN_ANA_QDAC_TS28HPM_6MX_2MR_FC_H_E_INST_CLOCK_DISABLE_STATUS 0x204804dc /* Clock Disable Status */
-#define BCHP_CLKGEN_ANA_SW_AVS_TS28HPM_6MX_2MR_FC_H_E_INST_CLOCK_DISABLE 0x204804e0 /* Disable ANA_SW_AVS_TS28HPM_6MX_2MR_FC_H_E_INST's clocks */
-#define BCHP_CLKGEN_ANA_SW_AVS_TS28HPM_6MX_2MR_FC_H_E_INST_CLOCK_DISABLE_STATUS 0x204804e4 /* Clock Disable Status */
-#define BCHP_CLKGEN_APM_CHIP_TOP_INST_CLOCK_ENABLE 0x204804e8 /* Apm chip top inst clock enable */
-#define BCHP_CLKGEN_APM_CHIP_TOP_INST_CLOCK_ENABLE_STATUS 0x204804ec /* Clock Enable Status */
-#define BCHP_CLKGEN_AVD_SID1_TOP_INST_CLOCK_ENABLE 0x204804f0 /* Avd sid1 top inst clock enable */
-#define BCHP_CLKGEN_AVD_SID1_TOP_INST_CLOCK_ENABLE_SID 0x204804f4 /* Avd sid1 top inst clock enable sid */
-#define BCHP_CLKGEN_AVD_SID1_TOP_INST_CLOCK_ENABLE_SID_STATUS 0x204804f8 /* Clock Enable Status */
-#define BCHP_CLKGEN_AVD_SID1_TOP_INST_CLOCK_ENABLE_STATUS 0x204804fc /* Clock Enable Status */
-#define BCHP_CLKGEN_AVD_SID1_TOP_INST_OBSERVE_CLOCK 0x20480500 /* Avd sid1 top inst observe clock */
-#define BCHP_CLKGEN_BVN_MVP_TOP_INST_CLOCK_ENABLE 0x20480504 /* Bvn mvp top inst clock enable */
-#define BCHP_CLKGEN_BVN_MVP_TOP_INST_CLOCK_ENABLE_STATUS 0x20480508 /* Clock Enable Status */
-#define BCHP_CLKGEN_BVN_TOP_INST_CLOCK_ENABLE 0x2048050c /* Bvn top inst clock enable */
-#define BCHP_CLKGEN_BVN_TOP_INST_CLOCK_ENABLE_STATUS 0x20480510 /* Clock Enable Status */
-#define BCHP_CLKGEN_CLKGEN_CLOCK_DISABLE 0x20480514 /* Disable CLKGEN's clocks */
-#define BCHP_CLKGEN_CLKGEN_CLOCK_DISABLE_STATUS 0x20480518 /* Clock Disable Status */
-#define BCHP_CLKGEN_CLKGEN_INST_CLOCK_ENABLE 0x2048051c /* Clkgen inst clock enable */
-#define BCHP_CLKGEN_CLKGEN_INST_CLOCK_ENABLE_STATUS 0x20480520 /* Clock Enable Status */
-#define BCHP_CLKGEN_CLOCK_MONITOR_CONTROL 0x20480524 /* Clock Monitor Control */
-#define BCHP_CLKGEN_CLOCK_MONITOR_MAX_COUNT 0x20480528 /* Clock Monitor Max Reference Count */
-#define BCHP_CLKGEN_CLOCK_MONITOR_REF_COUNTER 0x2048052c /* Clock Monitor Reference Counter */
-#define BCHP_CLKGEN_CLOCK_MONITOR_REF_DONE 0x20480530 /* Clock Monitor Reference Counter */
-#define BCHP_CLKGEN_CLOCK_MONITOR_VIEW_COUNTER 0x20480534 /* Clock Monitor View Counter */
-#define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_ENABLE 0x20480538 /* Core xpt inst clock enable */
-#define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_ENABLE_STATUS 0x2048053c /* Clock Enable Status */
-#define BCHP_CLKGEN_CORE_XPT_INST_OBSERVE_CLOCK 0x20480540 /* Core xpt inst observe clock */
-#define BCHP_CLKGEN_CPU4355_BCM_MIPS_TOP_INST_CLOCK_DISABLE 0x20480544 /* Disable CPU4355_BCM_MIPS_TOP_INST's clocks */
-#define BCHP_CLKGEN_CPU4355_BCM_MIPS_TOP_INST_CLOCK_DISABLE_STATUS 0x20480548 /* Clock Disable Status */
-#define BCHP_CLKGEN_CPU4355_BCM_MIPS_TOP_INST_CLOCK_ENABLE 0x2048054c /* Cpu4355 bcm mips top inst clock enable */
-#define BCHP_CLKGEN_CPU4355_BCM_MIPS_TOP_INST_CLOCK_ENABLE_STATUS 0x20480550 /* Clock Enable Status */
-#define BCHP_CLKGEN_D3DSMAC_X4_TOP_INST_CLOCK_DISABLE 0x20480554 /* Disable D3DSMAC_X4_TOP_INST's clocks */
-#define BCHP_CLKGEN_D3DSMAC_X4_TOP_INST_CLOCK_DISABLE_STATUS 0x20480558 /* Clock Disable Status */
-#define BCHP_CLKGEN_D3DSMAC_X4_TOP_INST_CLOCK_ENABLE 0x2048055c /* D3dsmac x4 top inst clock enable */
-#define BCHP_CLKGEN_D3DSMAC_X4_TOP_INST_CLOCK_ENABLE_STATUS 0x20480560 /* Clock Enable Status */
-#define BCHP_CLKGEN_DECT_UBUS_TOP_INST_CLOCK_DISABLE 0x20480564 /* Disable DECT_UBUS_TOP_INST's clocks */
-#define BCHP_CLKGEN_DECT_UBUS_TOP_INST_CLOCK_DISABLE_STATUS 0x20480568 /* Clock Disable Status */
-#define BCHP_CLKGEN_DECT_UBUS_TOP_INST_CLOCK_ENABLE 0x2048056c /* Dect ubus top inst clock enable */
-#define BCHP_CLKGEN_DECT_UBUS_TOP_INST_CLOCK_ENABLE_STATUS 0x20480570 /* Clock Enable Status */
-#define BCHP_CLKGEN_DISABLE_AVS_TOP_DURING_S2 0x20480574 /* Disable AVS_TOP 54MHz clocks during S2 standby. */
-#define BCHP_CLKGEN_DISABLE_AVS_TOP_DURING_S2_SECURE 0x20480578 /* Secure AVS_TOP clock disable. Set at start-up to guarantee AVS_TOP is clock gated in S2 standby. */
-#define BCHP_CLKGEN_BSPI_CLOCK_SELECT 0x2048057c /* PLL RDB Macro Disable */
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_RDB_MACRO_CTRL 0x20480580 /* PLL RDB Macro Disable */
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_RESET_STATUS 0x20480584 /* DOCSIS_PLL_SYS2 Reset Status */
-#define BCHP_CLKGEN_DS_TOPA_INST_CLOCK_ENABLE 0x20480588 /* Ds topa inst clock enable */
-#define BCHP_CLKGEN_DS_TOPA_INST_CLOCK_ENABLE_STATUS 0x2048058c /* Clock Enable Status */
-#define BCHP_CLKGEN_DS_TOPB_INST_CLOCK_ENABLE 0x20480590 /* Ds topb inst clock enable */
-#define BCHP_CLKGEN_DS_TOPB_INST_CLOCK_ENABLE_STATUS 0x20480594 /* Clock Enable Status */
-#define BCHP_CLKGEN_DS_TOPC_INST_CLOCK_ENABLE 0x20480598 /* Ds topc inst clock enable */
-#define BCHP_CLKGEN_DS_TOPC_INST_CLOCK_ENABLE_STATUS 0x2048059c /* Clock Enable Status */
-#define BCHP_CLKGEN_DS_TOPD_INST_CLOCK_ENABLE 0x204805a0 /* Ds topd inst clock enable */
-#define BCHP_CLKGEN_DS_TOPD_INST_CLOCK_ENABLE_STATUS 0x204805a4 /* Clock Enable Status */
-#define BCHP_CLKGEN_DS_WFE_TOP_INST_CLOCK_ENABLE 0x204805a8 /* Ds wfe top inst clock enable */
-#define BCHP_CLKGEN_DS_WFE_TOP_INST_CLOCK_ENABLE_STATUS 0x204805ac /* Clock Enable Status */
-#define BCHP_CLKGEN_DTP_DFAP_TOP_INST_CLOCK_DISABLE 0x204805b0 /* Disable DTP_DFAP_TOP_INST's clocks */
-#define BCHP_CLKGEN_DTP_DFAP_TOP_INST_CLOCK_DISABLE_STATUS 0x204805b4 /* Clock Disable Status */
-#define BCHP_CLKGEN_DTP_DFAP_TOP_INST_CLOCK_ENABLE 0x204805b8 /* Dtp dfap top inst clock enable */
-#define BCHP_CLKGEN_DTP_DFAP_TOP_INST_CLOCK_ENABLE_STATUS 0x204805bc /* Clock Enable Status */
-#define BCHP_CLKGEN_DVP_HR_INST_CLOCK_DISABLE 0x204805c0 /* Disable DVP_HR_INST's clocks */
-#define BCHP_CLKGEN_DVP_HR_INST_CLOCK_DISABLE_STATUS 0x204805c4 /* Clock Disable Status */
-#define BCHP_CLKGEN_DVP_HR_INST_CLOCK_ENABLE 0x204805c8 /* Dvp hr inst clock enable */
-#define BCHP_CLKGEN_DVP_HR_INST_CLOCK_ENABLE_STATUS 0x204805cc /* Clock Enable Status */
-#define BCHP_CLKGEN_DVP_HR_INST_ENABLE 0x204805d0 /* Dvp hr inst enable */
-#define BCHP_CLKGEN_DVP_HR_INST_OBSERVE_CLOCK 0x204805d4 /* Dvp hr inst observe clock */
-#define BCHP_CLKGEN_DVP_HT_INST_CLOCK_DISABLE 0x204805d8 /* Disable DVP_HT_INST's clocks */
-#define BCHP_CLKGEN_DVP_HT_INST_CLOCK_DISABLE_STATUS 0x204805dc /* Clock Disable Status */
-#define BCHP_CLKGEN_DVP_HT_INST_CLOCK_ENABLE 0x204805e0 /* Dvp ht inst clock enable */
-#define BCHP_CLKGEN_DVP_HT_INST_CLOCK_ENABLE_STATUS 0x204805e4 /* Clock Enable Status */
-#define BCHP_CLKGEN_DVP_HT_INST_OBSERVE_CLOCK 0x204805e8 /* Dvp ht inst observe clock */
-#define BCHP_CLKGEN_EAGLET_TOP_CORE_INST_CLOCK_ENABLE 0x204805ec /* Eaglet top core inst clock enable */
-#define BCHP_CLKGEN_EAGLET_TOP_CORE_INST_CLOCK_ENABLE_STATUS 0x204805f0 /* Clock Enable Status */
-#define BCHP_CLKGEN_EAGLET_TOP_ROUTER_INST_CLOCK_ENABLE 0x204805f4 /* Eaglet top router inst clock enable */
-#define BCHP_CLKGEN_EAGLET_TOP_ROUTER_INST_CLOCK_ENABLE_STATUS 0x204805f8 /* Clock Enable Status */
-#define BCHP_CLKGEN_EAGLET_TOP_ROUTER_INST_SELECT 0x204805fc /* Eaglet top router inst select */
-#define BCHP_CLKGEN_EGPHY28_4PORT_33V_90O_FC_INST_CLOCK_SELECT 0x20480600 /* Egphy28 4port 33v 90o fc inst clock select */
-#define BCHP_CLKGEN_G2U_U2U_UBUS_MOD_SS_INST_CLOCK_ENABLE 0x20480604 /* G2u u2u ubus mod ss inst clock enable */
-#define BCHP_CLKGEN_G2U_U2U_UBUS_MOD_SS_INST_CLOCK_ENABLE_STATUS 0x20480608 /* Clock Enable Status */
-#define BCHP_CLKGEN_GFAP_TOP_INST_CLOCK_DISABLE 0x2048060c /* Disable GFAP_TOP_INST's clocks */
-#define BCHP_CLKGEN_GFAP_TOP_INST_CLOCK_DISABLE_STATUS 0x20480610 /* Clock Disable Status */
-#define BCHP_CLKGEN_GFAP_TOP_INST_CLOCK_ENABLE 0x20480614 /* Gfap top inst clock enable */
-#define BCHP_CLKGEN_GFAP_TOP_INST_CLOCK_ENABLE0 0x20480618 /* Gfap top inst clock enable0 */
-#define BCHP_CLKGEN_GFAP_TOP_INST_CLOCK_ENABLE0_STATUS 0x2048061c /* Clock Enable Status */
-#define BCHP_CLKGEN_GFAP_TOP_INST_CLOCK_ENABLE_STATUS 0x20480620 /* Clock Enable Status */
-#define BCHP_CLKGEN_GRAPHICS_INST_CLOCK_ENABLE 0x20480624 /* Graphics inst clock enable */
-#define BCHP_CLKGEN_GRAPHICS_INST_CLOCK_ENABLE0 0x20480628 /* Graphics inst clock enable0 */
-#define BCHP_CLKGEN_GRAPHICS_INST_CLOCK_ENABLE0_STATUS 0x2048062c /* Clock Enable Status */
-#define BCHP_CLKGEN_GRAPHICS_INST_CLOCK_ENABLE1 0x20480630 /* Graphics inst clock enable1 */
-#define BCHP_CLKGEN_GRAPHICS_INST_CLOCK_ENABLE1_STATUS 0x20480634 /* Clock Enable Status */
-#define BCHP_CLKGEN_GRAPHICS_INST_CLOCK_ENABLE_M2MC0 0x20480638 /* Graphics inst clock enable m2mc0 */
-#define BCHP_CLKGEN_GRAPHICS_INST_CLOCK_ENABLE_M2MC0_STATUS 0x2048063c /* Clock Enable Status */
-#define BCHP_CLKGEN_GRAPHICS_INST_CLOCK_ENABLE_M2MC1 0x20480640 /* Graphics inst clock enable m2mc1 */
-#define BCHP_CLKGEN_GRAPHICS_INST_CLOCK_ENABLE_M2MC1_STATUS 0x20480644 /* Clock Enable Status */
-#define BCHP_CLKGEN_GRAPHICS_INST_CLOCK_ENABLE_STATUS 0x20480648 /* Clock Enable Status */
-#define BCHP_CLKGEN_GRAPHICS_INST_OBSERVE_CLOCK 0x2048064c /* Graphics inst observe clock */
-#define BCHP_CLKGEN_HIF_INST_CLOCK_DISABLE 0x20480650 /* Disable HIF_INST's clocks */
-#define BCHP_CLKGEN_HIF_INST_CLOCK_DISABLE_STATUS 0x20480654 /* Clock Disable Status */
-#define BCHP_CLKGEN_HIF_INST_CLOCK_ENABLE 0x20480658 /* Hif inst clock enable */
-#define BCHP_CLKGEN_HIF_INST_CLOCK_ENABLE_STATUS 0x2048065c /* Clock Enable Status */
-#define BCHP_CLKGEN_HIF_INST_OBSERVE_CLOCK 0x20480660 /* Hif inst observe clock */
-#define BCHP_CLKGEN_HVD0_TOP_INST_CLOCK_ENABLE 0x20480664 /* Hvd0 top inst clock enable */
-#define BCHP_CLKGEN_HVD0_TOP_INST_CLOCK_ENABLE_STATUS 0x20480668 /* Clock Enable Status */
-#define BCHP_CLKGEN_HVD0_TOP_INST_OBSERVE_CLOCK 0x2048066c /* Hvd0 top inst observe clock */
-#define BCHP_CLKGEN_INTERNAL_MUX_SELECT 0x20480670 /* Mux selects for Internal clocks */
-#define BCHP_CLKGEN_ITU656_0_MUX_SELECT 0x20480674 /* Mux selects for itu656_0 clocks */
-#define BCHP_CLKGEN_LEAP_TOP_INST_CLOCK_DISABLE 0x20480678 /* Disable LEAP_TOP_INST's clocks */
-#define BCHP_CLKGEN_LEAP_TOP_INST_CLOCK_DISABLE_STATUS 0x2048067c /* Clock Disable Status */
-#define BCHP_CLKGEN_LEAP_TOP_INST_CLOCK_ENABLE 0x20480680 /* Leap top inst clock enable */
-#define BCHP_CLKGEN_LEAP_TOP_INST_CLOCK_ENABLE_STATUS 0x20480684 /* Clock Enable Status */
-#define BCHP_CLKGEN_LEAP_TOP_INST_OBSERVE_CLOCK 0x20480688 /* Leap top inst observe clock */
-#define BCHP_CLKGEN_MEMSYS_32_WRAPPER_0_INST_CLOCK_ENABLE 0x2048068c /* Memsys 32 wrapper 0 inst clock enable */
-#define BCHP_CLKGEN_MEMSYS_32_WRAPPER_0_INST_CLOCK_ENABLE_STATUS 0x20480690 /* Clock Enable Status */
-#define BCHP_CLKGEN_MEMSYS_32_WRAPPER_0_INST_OBSERVE_CLOCK 0x20480694 /* Memsys 32 wrapper 0 inst observe clock */
-#define BCHP_CLKGEN_MEMSYS_32_WRAPPER_0_INST_STATUS 0x20480698 /* Memsys 32 wrapper 0 inst status */
-#define BCHP_CLKGEN_MEMSYS_32_WRAPPER_1_INST_CLOCK_ENABLE 0x2048069c /* Memsys 32 wrapper 1 inst clock enable */
-#define BCHP_CLKGEN_MEMSYS_32_WRAPPER_1_INST_CLOCK_ENABLE_STATUS 0x204806a0 /* Clock Enable Status */
-#define BCHP_CLKGEN_MEMSYS_32_WRAPPER_1_INST_OBSERVE_CLOCK 0x204806a4 /* Memsys 32 wrapper 1 inst observe clock */
-#define BCHP_CLKGEN_MEMSYS_32_WRAPPER_1_INST_STATUS 0x204806a8 /* Memsys 32 wrapper 1 inst status */
-#define BCHP_CLKGEN_MOCAMAC_TOP_INST_CLOCK_ENABLE 0x204806ac /* Mocamac top inst clock enable */
-#define BCHP_CLKGEN_MOCAMAC_TOP_INST_CLOCK_ENABLE_STATUS 0x204806b0 /* Clock Enable Status */
-#define BCHP_CLKGEN_MOCAMAC_TOP_INST_OBSERVE_CLOCK 0x204806b4 /* Mocamac top inst observe clock */
-#define BCHP_CLKGEN_MOCAPHY_TOP_INST_CLOCK_ENABLE 0x204806b8 /* Mocaphy top inst clock enable */
-#define BCHP_CLKGEN_MOCAPHY_TOP_INST_CLOCK_ENABLE_STATUS 0x204806bc /* Clock Enable Status */
-#define BCHP_CLKGEN_MOCAPHY_TOP_INST_OBSERVE_CLOCK 0x204806c0 /* Mocaphy top inst observe clock */
-#define BCHP_CLKGEN_MULTI_CLOCK_DISABLE 0x204806c4 /* Disable MULTI's clocks */
-#define BCHP_CLKGEN_MULTI_CLOCK_DISABLE_STATUS 0x204806c8 /* Clock Disable Status */
-#define BCHP_CLKGEN_PAD_CLK_OUT0_OBSERVATION 0x204806cc /* Select observation clk */
-#define BCHP_CLKGEN_PAD_CLK_OUT1_OBSERVATION 0x204806d0 /* Select observation clk */
-#define BCHP_CLKGEN_PAD_CLOCK_DISABLE 0x204806d4 /* Disable PAD's clocks */
-#define BCHP_CLKGEN_PAD_CLOCK_DISABLE_STATUS 0x204806d8 /* Clock Disable Status */
-#define BCHP_CLKGEN_PAD_MUX_SELECT 0x204806dc /* Mux selects for Pad clocks */
-#define BCHP_CLKGEN_PCIE_X2_TOP_INST_CLOCK_DISABLE 0x204806e0 /* Disable PCIE_X2_TOP_INST's clocks */
-#define BCHP_CLKGEN_PCIE_X2_TOP_INST_CLOCK_DISABLE_STATUS 0x204806e4 /* Clock Disable Status */
-#define BCHP_CLKGEN_PCIE_X2_TOP_INST_CLOCK_ENABLE 0x204806e8 /* Pcie x2 top inst clock enable */
-#define BCHP_CLKGEN_PCIE_X2_TOP_INST_CLOCK_ENABLE_STATUS 0x204806ec /* Clock Enable Status */
-#define BCHP_CLKGEN_PCIE_X2_TOP_INST_OBSERVE_CLOCK 0x204806f0 /* Pcie x2 top inst observe clock */
-#define BCHP_CLKGEN_PLL_AUDIO0_PLL_RESET_STATUS 0x204806f4 /* PLL_AUDIO0 Reset Status */
-#define BCHP_CLKGEN_PLL_AUDIO1_PLL_RESET_STATUS 0x204806f8 /* PLL_AUDIO1 Reset Status */
-#define BCHP_CLKGEN_PLL_AUDIO2_PLL_RESET_STATUS 0x204806fc /* PLL_AUDIO2 Reset Status */
-#define BCHP_CLKGEN_PLL_AVD_PLL_RESET_STATUS 0x20480700 /* PLL_AVD Reset Status */
-#define BCHP_CLKGEN_PLL_AVD_RDB_MACRO_CTRL 0x20480704 /* PLL RDB Macro Disable */
-#define BCHP_CLKGEN_PLL_CPU_CORE_GLITCHLESS_SWITCH_REQUEST 0x20480708 /* PLL_CPU_CORE Glitchless Clock Switching */
-#define BCHP_CLKGEN_PLL_CPU_CORE_GLITCHLESS_SWITCH_STATUS 0x2048070c /* PLL_CPU_CORE Glitchless Switching */
-#define BCHP_CLKGEN_PLL_CPU_CORE_PLL_RESET_STATUS 0x20480710 /* PLL_CPU_CORE Reset Status */
-#define BCHP_CLKGEN_PLL_CPU_CORE_RDB_MACRO_CTRL 0x20480714 /* PLL RDB Macro Disable */
-#define BCHP_CLKGEN_PLL_CPU_ROUTER_PLL_RESET_STATUS 0x20480718 /* PLL_CPU_ROUTER Reset Status */
-#define BCHP_CLKGEN_PLL_CPU_ROUTER_RDB_MACRO_CTRL 0x2048071c /* PLL RDB Macro Disable */
-#define BCHP_CLKGEN_PLL_LC_PLL_RESET_STATUS 0x20480720 /* PLL_LC Reset Status */
-#define BCHP_CLKGEN_PLL_LC_RDB_MACRO_CTRL 0x20480724 /* PLL RDB Macro Disable */
-#define BCHP_CLKGEN_PLL_MOCA_PLL_RESET_STATUS 0x20480728 /* PLL_MOCA Reset Status */
-#define BCHP_CLKGEN_PLL_MOCA_RDB_MACRO_CTRL 0x2048072c /* PLL RDB Macro Disable */
-#define BCHP_CLKGEN_PLL_RAAGA_PLL_RESET_STATUS 0x20480730 /* PLL_RAAGA Reset Status */
-#define BCHP_CLKGEN_PLL_RAAGA_RDB_MACRO_CTRL 0x20480734 /* PLL RDB Macro Disable */
-#define BCHP_CLKGEN_PLL_SC0_PLL_RESET_STATUS 0x20480738 /* PLL_SC0 Reset Status */
-#define BCHP_CLKGEN_PLL_SC0_RDB_MACRO_CTRL 0x2048073c /* PLL RDB Macro Disable */
-#define BCHP_CLKGEN_PLL_SC1_PLL_RESET_STATUS 0x20480740 /* PLL_SC1 Reset Status */
-#define BCHP_CLKGEN_PLL_SC1_RDB_MACRO_CTRL 0x20480744 /* PLL RDB Macro Disable */
-#define BCHP_CLKGEN_PLL_STRAP_OVERRIDE 0x20480748 /* Disable */
-#define BCHP_CLKGEN_PLL_SWITCH_PLL_RESET_STATUS 0x2048074c /* PLL_SWITCH Reset Status */
-#define BCHP_CLKGEN_PLL_SYS0_RDB_MACRO_CTRL 0x20480750 /* PLL RDB Macro Disable */
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_RESET_STATUS 0x20480754 /* PLL_VCXO0 Reset Status */
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_RESET_STATUS 0x20480758 /* PLL_VCXO1 Reset Status */
-#define BCHP_CLKGEN_PLL_VCXO2_PLL_RESET_STATUS 0x2048075c /* PLL_VCXO2 Reset Status */
-#define BCHP_CLKGEN_PLL_XPT_RDB_MACRO_CTRL 0x20480760 /* PLL RDB Macro Disable */
-#define BCHP_CLKGEN_PM_CLOCK_Async_ALIVE_SEL 0x20480764 /* Select clocks that can stay alive during power management standby mode. */
-#define BCHP_CLKGEN_PM_PLL_ALIVE_SEL 0x20480768 /* PLL Alive in Standby Mode */
-#define BCHP_CLKGEN_PM_PLL_LDO_POWERUP 0x2048076c /* Power management LDO PLL */
-#define BCHP_CLKGEN_PROD_OTP_INST_CLOCK_DISABLE 0x20480770 /* Disable PROD_OTP_INST's clocks */
-#define BCHP_CLKGEN_PROD_OTP_INST_CLOCK_DISABLE_STATUS 0x20480774 /* Clock Disable Status */
-#define BCHP_CLKGEN_PROD_OTP_INST_CLOCK_ENABLE 0x20480778 /* Prod otp inst clock enable */
-#define BCHP_CLKGEN_PROD_OTP_INST_CLOCK_ENABLE_STATUS 0x2048077c /* Clock Enable Status */
-#define BCHP_CLKGEN_RAAGA_DSP_TOP_0_INST_CLOCK_ENABLE 0x20480780 /* Raaga dsp top 0 inst clock enable */
-#define BCHP_CLKGEN_RAAGA_DSP_TOP_0_INST_CLOCK_ENABLE_STATUS 0x20480784 /* Clock Enable Status */
-#define BCHP_CLKGEN_RAAGA_DSP_TOP_0_INST_OBSERVE_CLOCK 0x20480788 /* Raaga dsp top 0 inst observe clock */
-#define BCHP_CLKGEN_RAAGA_DSP_TOP_1_INST_CLOCK_ENABLE 0x2048078c /* Raaga dsp top 1 inst clock enable */
-#define BCHP_CLKGEN_RAAGA_DSP_TOP_1_INST_CLOCK_ENABLE_STATUS 0x20480790 /* Clock Enable Status */
-#define BCHP_CLKGEN_RAAGA_DSP_TOP_1_INST_OBSERVE_CLOCK 0x20480794 /* Raaga dsp top 1 inst observe clock */
-#define BCHP_CLKGEN_RFM_TOP_INST_CLOCK_ENABLE 0x20480798 /* Rfm top inst clock enable */
-#define BCHP_CLKGEN_RFM_TOP_INST_CLOCK_ENABLE_STATUS 0x2048079c /* Clock Enable Status */
-#define BCHP_CLKGEN_RFM_TOP_INST_OBSERVE_CLOCK 0x204807a0 /* Rfm top inst observe clock */
-#define BCHP_CLKGEN_SATA3_TOP_INST_CLOCK_DISABLE 0x204807a4 /* Disable SATA3_TOP_INST's clocks */
-#define BCHP_CLKGEN_SATA3_TOP_INST_CLOCK_DISABLE_STATUS 0x204807a8 /* Clock Disable Status */
-#define BCHP_CLKGEN_SATA3_TOP_INST_CLOCK_ENABLE 0x204807ac /* Sata3 top inst clock enable */
-#define BCHP_CLKGEN_SATA3_TOP_INST_CLOCK_ENABLE_STATUS 0x204807b0 /* Clock Enable Status */
-#define BCHP_CLKGEN_SATA3_TOP_INST_CLOCK_SELECT 0x204807b4 /* Sata3 top inst clock select */
-#define BCHP_CLKGEN_SATA3_TOP_INST_OBSERVE_CLOCK 0x204807b8 /* Sata3 top inst observe clock */
-#define BCHP_CLKGEN_SECTOP_INST_CLOCK_ENABLE 0x204807bc /* Sectop inst clock enable */
-#define BCHP_CLKGEN_SECTOP_INST_CLOCK_ENABLE_STATUS 0x204807c0 /* Clock Enable Status */
-#define BCHP_CLKGEN_SECTOP_INST_OBSERVE_CLOCK 0x204807c4 /* Sectop inst observe clock */
-#define BCHP_CLKGEN_SMARTCARD_MUX_SELECT 0x204807c8 /* Mux selects for Smartcard clocks */
-#define BCHP_CLKGEN_SPARE 0x204807cc /* Spares */
-#define BCHP_CLKGEN_SWITCH_TOP_INST_CLOCK_DISABLE 0x204807d0 /* Disable SWITCH_TOP_INST's clocks */
-#define BCHP_CLKGEN_SWITCH_TOP_INST_CLOCK_DISABLE_STATUS 0x204807d4 /* Clock Disable Status */
-#define BCHP_CLKGEN_SWITCH_TOP_INST_CLOCK_ENABLE 0x204807d8 /* Switch top inst clock enable */
-#define BCHP_CLKGEN_SWITCH_TOP_INST_CLOCK_ENABLE_STATUS 0x204807dc /* Clock Enable Status */
-#define BCHP_CLKGEN_SWITCH_TOP_INST_OBSERVE_CLOCK 0x204807e0 /* Switch top inst observe clock */
-#define BCHP_CLKGEN_SYS_CTRL_INST_CLOCK_DISABLE 0x204807e4 /* Disable SYS_CTRL_INST's clocks */
-#define BCHP_CLKGEN_SYS_CTRL_INST_CLOCK_DISABLE_STATUS 0x204807e8 /* Clock Disable Status */
-#define BCHP_CLKGEN_TESTPORT 0x204807ec /* Special Testport Controls */
-#define BCHP_CLKGEN_UBUS_MOD_PERIPH_FPM_INST_CLOCK_DISABLE 0x204807f0 /* Disable UBUS_MOD_PERIPH_FPM_INST's clocks */
-#define BCHP_CLKGEN_UBUS_MOD_PERIPH_FPM_INST_CLOCK_DISABLE_STATUS 0x204807f4 /* Clock Disable Status */
-#define BCHP_CLKGEN_UBUS_MOD_PERIPH_FPM_INST_CLOCK_ENABLE 0x204807f8 /* Ubus mod periph fpm inst clock enable */
-#define BCHP_CLKGEN_UBUS_MOD_PERIPH_FPM_INST_CLOCK_ENABLE_STATUS 0x204807fc /* Clock Enable Status */
-#define BCHP_CLKGEN_UNIMAC_MBDMA_TOP_ROUTER_1_INST_CLOCK_DISABLE 0x20480800 /* Disable UNIMAC_MBDMA_TOP_ROUTER_1_INST's clocks */
-#define BCHP_CLKGEN_UNIMAC_MBDMA_TOP_ROUTER_1_INST_CLOCK_DISABLE_STATUS 0x20480804 /* Clock Disable Status */
-#define BCHP_CLKGEN_UNIMAC_MBDMA_TOP_ROUTER_1_INST_CLOCK_ENABLE 0x20480808 /* Unimac mbdma top router 1 inst clock enable */
-#define BCHP_CLKGEN_UNIMAC_MBDMA_TOP_ROUTER_1_INST_CLOCK_ENABLE_STATUS 0x2048080c /* Clock Enable Status */
-#define BCHP_CLKGEN_UNIMAC_MBDMA_TOP_ROUTER_INST_CLOCK_DISABLE 0x20480810 /* Disable UNIMAC_MBDMA_TOP_ROUTER_INST's clocks */
-#define BCHP_CLKGEN_UNIMAC_MBDMA_TOP_ROUTER_INST_CLOCK_DISABLE_STATUS 0x20480814 /* Clock Disable Status */
-#define BCHP_CLKGEN_UNIMAC_MBDMA_TOP_ROUTER_INST_CLOCK_ENABLE 0x20480818 /* Unimac mbdma top router inst clock enable */
-#define BCHP_CLKGEN_UNIMAC_MBDMA_TOP_ROUTER_INST_CLOCK_ENABLE_STATUS 0x2048081c /* Clock Enable Status */
-#define BCHP_CLKGEN_UNIMAC_MBDMA_TOP_STB_INST_CLOCK_DISABLE 0x20480820 /* Disable UNIMAC_MBDMA_TOP_STB_INST's clocks */
-#define BCHP_CLKGEN_UNIMAC_MBDMA_TOP_STB_INST_CLOCK_DISABLE_STATUS 0x20480824 /* Clock Disable Status */
-#define BCHP_CLKGEN_UNIMAC_MBDMA_TOP_STB_INST_CLOCK_ENABLE 0x20480828 /* Unimac mbdma top stb inst clock enable */
-#define BCHP_CLKGEN_UNIMAC_MBDMA_TOP_STB_INST_CLOCK_ENABLE_STATUS 0x2048082c /* Clock Enable Status */
-#define BCHP_CLKGEN_UNIMAC_MBDMA_TOP_WAN_INST_CLOCK_DISABLE 0x20480830 /* Disable UNIMAC_MBDMA_TOP_WAN_INST's clocks */
-#define BCHP_CLKGEN_UNIMAC_MBDMA_TOP_WAN_INST_CLOCK_DISABLE_STATUS 0x20480834 /* Clock Disable Status */
-#define BCHP_CLKGEN_UNIMAC_MBDMA_TOP_WAN_INST_CLOCK_ENABLE 0x20480838 /* Unimac mbdma top wan inst clock enable */
-#define BCHP_CLKGEN_UNIMAC_MBDMA_TOP_WAN_INST_CLOCK_ENABLE_STATUS 0x2048083c /* Clock Enable Status */
-#define BCHP_CLKGEN_USB0_TOP_INST_CLOCK_DISABLE 0x20480840 /* Disable USB0_TOP_INST's clocks */
-#define BCHP_CLKGEN_USB0_TOP_INST_CLOCK_DISABLE_STATUS 0x20480844 /* Clock Disable Status */
-#define BCHP_CLKGEN_USB0_TOP_INST_CLOCK_ENABLE 0x20480848 /* Usb0 top inst clock enable */
-#define BCHP_CLKGEN_USB0_TOP_INST_CLOCK_ENABLE_AHB 0x2048084c /* Usb0 top inst clock enable ahb */
-#define BCHP_CLKGEN_USB0_TOP_INST_CLOCK_ENABLE_AHB_STATUS 0x20480850 /* Clock Enable Status */
-#define BCHP_CLKGEN_USB0_TOP_INST_CLOCK_ENABLE_AXI 0x20480854 /* Usb0 top inst clock enable axi */
-#define BCHP_CLKGEN_USB0_TOP_INST_CLOCK_ENABLE_AXI_STATUS 0x20480858 /* Clock Enable Status */
-#define BCHP_CLKGEN_USB0_TOP_INST_CLOCK_ENABLE_STATUS 0x2048085c /* Clock Enable Status */
-#define BCHP_CLKGEN_USB0_TOP_INST_OBSERVE_CLOCK 0x20480860 /* Usb0 top inst observe clock */
-#define BCHP_CLKGEN_USMAC_TC8X_DAVIC_TOP_INST_CLOCK_DISABLE 0x20480864 /* Disable USMAC_TC8X_DAVIC_TOP_INST's clocks */
-#define BCHP_CLKGEN_USMAC_TC8X_DAVIC_TOP_INST_CLOCK_DISABLE_STATUS 0x20480868 /* Clock Disable Status */
-#define BCHP_CLKGEN_USMAC_TC8X_DAVIC_TOP_INST_CLOCK_ENABLE 0x2048086c /* Usmac tc8x davic top inst clock enable */
-#define BCHP_CLKGEN_USMAC_TC8X_DAVIC_TOP_INST_CLOCK_ENABLE_STATUS 0x20480870 /* Clock Enable Status */
-#define BCHP_CLKGEN_US_TOP_INST_CLOCK_ENABLE 0x20480874 /* Us top inst clock enable */
-#define BCHP_CLKGEN_US_TOP_INST_CLOCK_ENABLE_STATUS 0x20480878 /* Clock Enable Status */
-#define BCHP_CLKGEN_UTP_CRYPTO_SEGDMA_TOP_INST_CLOCK_DISABLE 0x2048087c /* Disable UTP_CRYPTO_SEGDMA_TOP_INST's clocks */
-#define BCHP_CLKGEN_UTP_CRYPTO_SEGDMA_TOP_INST_CLOCK_DISABLE_STATUS 0x20480880 /* Clock Disable Status */
-#define BCHP_CLKGEN_UTP_CRYPTO_SEGDMA_TOP_INST_CLOCK_ENABLE 0x20480884 /* Utp crypto segdma top inst clock enable */
-#define BCHP_CLKGEN_UTP_CRYPTO_SEGDMA_TOP_INST_CLOCK_ENABLE_STATUS 0x20480888 /* Clock Enable Status */
-#define BCHP_CLKGEN_V3D_TOP_INST_CLOCK_ENABLE 0x2048088c /* V3d top inst clock enable */
-#define BCHP_CLKGEN_V3D_TOP_INST_CLOCK_ENABLE_STATUS 0x20480890 /* Clock Enable Status */
-#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_DISABLE 0x20480894 /* Disable VEC_AIO_TOP_INST's clocks */
-#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_DISABLE_STATUS 0x20480898 /* Clock Disable Status */
-#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE 0x2048089c /* Vec aio top inst clock enable */
-#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_STATUS 0x204808a0 /* Clock Enable Status */
-#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC_QDAC_INTF 0x204808a4 /* Vec aio top inst clock enable vec qdac intf */
-#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC_QDAC_INTF_STATUS 0x204808a8 /* Clock Enable Status */
-#define BCHP_CLKGEN_VEC_AIO_TOP_INST_OBSERVE_CLOCK 0x204808ac /* Vec aio top inst observe clock */
-#define BCHP_CLKGEN_VICE2_0_INST_CLOCK_ENABLE 0x204808b0 /* Vice2 0 inst clock enable */
-#define BCHP_CLKGEN_VICE2_0_INST_CLOCK_ENABLE_STATUS 0x204808b4 /* Clock Enable Status */
-#define BCHP_CLKGEN_VICE2_1_INST_CLOCK_ENABLE 0x204808b8 /* Vice2 1 inst clock enable */
-#define BCHP_CLKGEN_VICE2_1_INST_CLOCK_ENABLE_STATUS 0x204808bc /* Clock Enable Status */
-
-/***************************************************************************
- *DOCSIS_PLL_SYS0_PLL_BG_PWRON - Bandgap Power on
- ***************************************************************************/
-/* CLKGEN :: DOCSIS_PLL_SYS0_PLL_BG_PWRON :: reserved0 [31:01] */
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_BG_PWRON_reserved0_MASK 0xfffffffe
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_BG_PWRON_reserved0_SHIFT 1
-
-/* CLKGEN :: DOCSIS_PLL_SYS0_PLL_BG_PWRON :: BG_PWRON_PLL [00:00] */
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_BG_PWRON_BG_PWRON_PLL_MASK 0x00000001
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_BG_PWRON_BG_PWRON_PLL_SHIFT 0
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_BG_PWRON_BG_PWRON_PLL_DEFAULT 0x00000001
-
-/***************************************************************************
- *DOCSIS_PLL_SYS0_PLL_CHANNEL_CTRL_CH_0 - PLL CHANNEL control CH 0
- ***************************************************************************/
-/* CLKGEN :: DOCSIS_PLL_SYS0_PLL_CHANNEL_CTRL_CH_0 :: reserved0 [31:11] */
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_CHANNEL_CTRL_CH_0_reserved0_MASK 0xfffff800
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_CHANNEL_CTRL_CH_0_reserved0_SHIFT 11
-
-/* CLKGEN :: DOCSIS_PLL_SYS0_PLL_CHANNEL_CTRL_CH_0 :: POST_DIVIDER_HOLD_CH0 [10:10] */
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_MASK 0x00000400
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_SHIFT 10
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_DEFAULT 0x00000000
-
-/* CLKGEN :: DOCSIS_PLL_SYS0_PLL_CHANNEL_CTRL_CH_0 :: PHASE_OFFSET_CH0 [09:09] */
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_MASK 0x00000200
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_SHIFT 9
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_DEFAULT 0x00000000
-
-/* CLKGEN :: DOCSIS_PLL_SYS0_PLL_CHANNEL_CTRL_CH_0 :: MDIV_CH0 [08:01] */
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_MASK 0x000001fe
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_SHIFT 1
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_DEFAULT 0x0000000c
-
-/* CLKGEN :: DOCSIS_PLL_SYS0_PLL_CHANNEL_CTRL_CH_0 :: CLOCK_DIS_CH0 [00:00] */
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_MASK 0x00000001
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_SHIFT 0
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_DEFAULT 0x00000000
-
-/***************************************************************************
- *DOCSIS_PLL_SYS0_PLL_CHANNEL_CTRL_CH_1 - PLL CHANNEL control CH 1
- ***************************************************************************/
-/* CLKGEN :: DOCSIS_PLL_SYS0_PLL_CHANNEL_CTRL_CH_1 :: reserved0 [31:11] */
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_CHANNEL_CTRL_CH_1_reserved0_MASK 0xfffff800
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_CHANNEL_CTRL_CH_1_reserved0_SHIFT 11
-
-/* CLKGEN :: DOCSIS_PLL_SYS0_PLL_CHANNEL_CTRL_CH_1 :: POST_DIVIDER_HOLD_CH1 [10:10] */
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_MASK 0x00000400
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_SHIFT 10
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_DEFAULT 0x00000000
-
-/* CLKGEN :: DOCSIS_PLL_SYS0_PLL_CHANNEL_CTRL_CH_1 :: PHASE_OFFSET_CH1 [09:09] */
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_MASK 0x00000200
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_SHIFT 9
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_DEFAULT 0x00000000
-
-/* CLKGEN :: DOCSIS_PLL_SYS0_PLL_CHANNEL_CTRL_CH_1 :: MDIV_CH1 [08:01] */
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_MASK 0x000001fe
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_SHIFT 1
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_DEFAULT 0x0000000e
-
-/* CLKGEN :: DOCSIS_PLL_SYS0_PLL_CHANNEL_CTRL_CH_1 :: CLOCK_DIS_CH1 [00:00] */
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_MASK 0x00000001
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_SHIFT 0
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_DEFAULT 0x00000000
-
-/***************************************************************************
- *DOCSIS_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2 - PLL CHANNEL control CH 2
- ***************************************************************************/
-/* CLKGEN :: DOCSIS_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2 :: reserved0 [31:11] */
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2_reserved0_MASK 0xfffff800
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2_reserved0_SHIFT 11
-
-/* CLKGEN :: DOCSIS_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2 :: POST_DIVIDER_HOLD_CH2 [10:10] */
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_HOLD_CH2_MASK 0x00000400
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_HOLD_CH2_SHIFT 10
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_HOLD_CH2_DEFAULT 0x00000000
-
-/* CLKGEN :: DOCSIS_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2 :: PHASE_OFFSET_CH2 [09:09] */
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2_PHASE_OFFSET_CH2_MASK 0x00000200
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2_PHASE_OFFSET_CH2_SHIFT 9
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2_PHASE_OFFSET_CH2_DEFAULT 0x00000000
-
-/* CLKGEN :: DOCSIS_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2 :: MDIV_CH2 [08:01] */
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2_MDIV_CH2_MASK 0x000001fe
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2_MDIV_CH2_SHIFT 1
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2_MDIV_CH2_DEFAULT 0x00000012
-
-/* CLKGEN :: DOCSIS_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2 :: CLOCK_DIS_CH2 [00:00] */
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2_CLOCK_DIS_CH2_MASK 0x00000001
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2_CLOCK_DIS_CH2_SHIFT 0
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2_CLOCK_DIS_CH2_DEFAULT 0x00000000
-
-/***************************************************************************
- *DOCSIS_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3 - PLL CHANNEL control CH 3
- ***************************************************************************/
-/* CLKGEN :: DOCSIS_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3 :: reserved0 [31:11] */
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3_reserved0_MASK 0xfffff800
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3_reserved0_SHIFT 11
-
-/* CLKGEN :: DOCSIS_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3 :: POST_DIVIDER_HOLD_CH3 [10:10] */
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_HOLD_CH3_MASK 0x00000400
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_HOLD_CH3_SHIFT 10
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_HOLD_CH3_DEFAULT 0x00000000
-
-/* CLKGEN :: DOCSIS_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3 :: PHASE_OFFSET_CH3 [09:09] */
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3_PHASE_OFFSET_CH3_MASK 0x00000200
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3_PHASE_OFFSET_CH3_SHIFT 9
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3_PHASE_OFFSET_CH3_DEFAULT 0x00000000
-
-/* CLKGEN :: DOCSIS_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3 :: MDIV_CH3 [08:01] */
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3_MDIV_CH3_MASK 0x000001fe
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3_MDIV_CH3_SHIFT 1
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3_MDIV_CH3_DEFAULT 0x00000090
-
-/* CLKGEN :: DOCSIS_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3 :: CLOCK_DIS_CH3 [00:00] */
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3_CLOCK_DIS_CH3_MASK 0x00000001
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3_CLOCK_DIS_CH3_SHIFT 0
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3_CLOCK_DIS_CH3_DEFAULT 0x00000000
-
-/***************************************************************************
- *DOCSIS_PLL_SYS0_PLL_CHANNEL_CTRL_CH_4 - PLL CHANNEL control CH 4
- ***************************************************************************/
-/* CLKGEN :: DOCSIS_PLL_SYS0_PLL_CHANNEL_CTRL_CH_4 :: reserved0 [31:11] */
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_CHANNEL_CTRL_CH_4_reserved0_MASK 0xfffff800
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_CHANNEL_CTRL_CH_4_reserved0_SHIFT 11
-
-/* CLKGEN :: DOCSIS_PLL_SYS0_PLL_CHANNEL_CTRL_CH_4 :: POST_DIVIDER_HOLD_CH4 [10:10] */
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_CHANNEL_CTRL_CH_4_POST_DIVIDER_HOLD_CH4_MASK 0x00000400
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_CHANNEL_CTRL_CH_4_POST_DIVIDER_HOLD_CH4_SHIFT 10
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_CHANNEL_CTRL_CH_4_POST_DIVIDER_HOLD_CH4_DEFAULT 0x00000000
-
-/* CLKGEN :: DOCSIS_PLL_SYS0_PLL_CHANNEL_CTRL_CH_4 :: PHASE_OFFSET_CH4 [09:09] */
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_CHANNEL_CTRL_CH_4_PHASE_OFFSET_CH4_MASK 0x00000200
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_CHANNEL_CTRL_CH_4_PHASE_OFFSET_CH4_SHIFT 9
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_CHANNEL_CTRL_CH_4_PHASE_OFFSET_CH4_DEFAULT 0x00000000
-
-/* CLKGEN :: DOCSIS_PLL_SYS0_PLL_CHANNEL_CTRL_CH_4 :: MDIV_CH4 [08:01] */
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_CHANNEL_CTRL_CH_4_MDIV_CH4_MASK 0x000001fe
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_CHANNEL_CTRL_CH_4_MDIV_CH4_SHIFT 1
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_CHANNEL_CTRL_CH_4_MDIV_CH4_DEFAULT 0x00000024
-
-/* CLKGEN :: DOCSIS_PLL_SYS0_PLL_CHANNEL_CTRL_CH_4 :: CLOCK_DIS_CH4 [00:00] */
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_CHANNEL_CTRL_CH_4_CLOCK_DIS_CH4_MASK 0x00000001
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_CHANNEL_CTRL_CH_4_CLOCK_DIS_CH4_SHIFT 0
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_CHANNEL_CTRL_CH_4_CLOCK_DIS_CH4_DEFAULT 0x00000000
-
-/***************************************************************************
- *DOCSIS_PLL_SYS0_PLL_DIV - Pre multiplier
- ***************************************************************************/
-/* CLKGEN :: DOCSIS_PLL_SYS0_PLL_DIV :: reserved0 [31:14] */
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_DIV_reserved0_MASK 0xffffc000
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_DIV_reserved0_SHIFT 14
-
-/* CLKGEN :: DOCSIS_PLL_SYS0_PLL_DIV :: PDIV [13:10] */
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_DIV_PDIV_MASK 0x00003c00
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_DIV_PDIV_SHIFT 10
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_DIV_PDIV_DEFAULT 0x00000002
-
-/* CLKGEN :: DOCSIS_PLL_SYS0_PLL_DIV :: NDIV_INT [09:00] */
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_DIV_NDIV_INT_MASK 0x000003ff
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_DIV_NDIV_INT_SHIFT 0
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_DIV_NDIV_INT_DEFAULT 0x00000090
-
-/***************************************************************************
- *DOCSIS_PLL_SYS0_PLL_GAIN - PLL GAIN
- ***************************************************************************/
-/* CLKGEN :: DOCSIS_PLL_SYS0_PLL_GAIN :: reserved0 [31:10] */
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_GAIN_reserved0_MASK 0xfffffc00
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_GAIN_reserved0_SHIFT 10
-
-/* CLKGEN :: DOCSIS_PLL_SYS0_PLL_GAIN :: LOOP_GAIN_PROPORTIONAL_IN_PHASE [09:06] */
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_MASK 0x000003c0
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_SHIFT 6
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_DEFAULT 0x00000007
-
-/* CLKGEN :: DOCSIS_PLL_SYS0_PLL_GAIN :: LOOP_GAIN_IN_FREQ [05:03] */
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_GAIN_LOOP_GAIN_IN_FREQ_MASK 0x00000038
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_GAIN_LOOP_GAIN_IN_FREQ_SHIFT 3
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_GAIN_LOOP_GAIN_IN_FREQ_DEFAULT 0x00000000
-
-/* CLKGEN :: DOCSIS_PLL_SYS0_PLL_GAIN :: LOOP_GAIN_INTEGRATOR_IN_PHASE [02:00] */
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_MASK 0x00000007
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_SHIFT 0
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_DEFAULT 0x00000004
-
-/***************************************************************************
- *DOCSIS_PLL_SYS0_PLL_HOLD_CH_ALL - Hold PLL all channels
- ***************************************************************************/
-/* CLKGEN :: DOCSIS_PLL_SYS0_PLL_HOLD_CH_ALL :: reserved0 [31:01] */
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_HOLD_CH_ALL_reserved0_MASK 0xfffffffe
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_HOLD_CH_ALL_reserved0_SHIFT 1
-
-/* CLKGEN :: DOCSIS_PLL_SYS0_PLL_HOLD_CH_ALL :: HOLD_CH_ALL [00:00] */
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_HOLD_CH_ALL_HOLD_CH_ALL_MASK 0x00000001
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_HOLD_CH_ALL_HOLD_CH_ALL_SHIFT 0
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_HOLD_CH_ALL_HOLD_CH_ALL_DEFAULT 0x00000000
-
-/***************************************************************************
- *DOCSIS_PLL_SYS0_PLL_LDO_CTRL - Ldo voltage control
- ***************************************************************************/
-/* CLKGEN :: DOCSIS_PLL_SYS0_PLL_LDO_CTRL :: reserved0 [31:16] */
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_LDO_CTRL_reserved0_MASK 0xffff0000
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_LDO_CTRL_reserved0_SHIFT 16
-
-/* CLKGEN :: DOCSIS_PLL_SYS0_PLL_LDO_CTRL :: LDO_CTRL [15:00] */
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_LDO_CTRL_LDO_CTRL_MASK 0x0000ffff
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_LDO_CTRL_LDO_CTRL_SHIFT 0
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_LDO_CTRL_LDO_CTRL_DEFAULT 0x00000005
-
-/***************************************************************************
- *DOCSIS_PLL_SYS0_PLL_LDO_PWRON - LDO Power on
- ***************************************************************************/
-/* CLKGEN :: DOCSIS_PLL_SYS0_PLL_LDO_PWRON :: reserved0 [31:01] */
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_LDO_PWRON_reserved0_MASK 0xfffffffe
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_LDO_PWRON_reserved0_SHIFT 1
-
-/* CLKGEN :: DOCSIS_PLL_SYS0_PLL_LDO_PWRON :: LDO_PWRON_PLL [00:00] */
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_LDO_PWRON_LDO_PWRON_PLL_MASK 0x00000001
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_LDO_PWRON_LDO_PWRON_PLL_SHIFT 0
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_LDO_PWRON_LDO_PWRON_PLL_DEFAULT 0x00000001
-
-/***************************************************************************
- *DOCSIS_PLL_SYS0_PLL_LOCK_STATUS - Lock Status
- ***************************************************************************/
-/* CLKGEN :: DOCSIS_PLL_SYS0_PLL_LOCK_STATUS :: reserved0 [31:02] */
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_LOCK_STATUS_reserved0_MASK 0xfffffffc
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_LOCK_STATUS_reserved0_SHIFT 2
-
-/* CLKGEN :: DOCSIS_PLL_SYS0_PLL_LOCK_STATUS :: LOCK_LOST [01:01] */
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_LOCK_STATUS_LOCK_LOST_MASK 0x00000002
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_LOCK_STATUS_LOCK_LOST_SHIFT 1
-
-/* CLKGEN :: DOCSIS_PLL_SYS0_PLL_LOCK_STATUS :: LOCK [00:00] */
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_LOCK_STATUS_LOCK_MASK 0x00000001
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_LOCK_STATUS_LOCK_SHIFT 0
-
-/***************************************************************************
- *DOCSIS_PLL_SYS0_PLL_MISC - Mscellaneous control bus.
- ***************************************************************************/
-/* CLKGEN :: DOCSIS_PLL_SYS0_PLL_MISC :: VCO_RANGE_LOW [31:31] */
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_MISC_VCO_RANGE_LOW_MASK 0x80000000
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_MISC_VCO_RANGE_LOW_SHIFT 31
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_MISC_VCO_RANGE_LOW_DEFAULT 0x00000000
-
-/* CLKGEN :: DOCSIS_PLL_SYS0_PLL_MISC :: VCO_RANGE_HIGH [30:30] */
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_MISC_VCO_RANGE_HIGH_MASK 0x40000000
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_MISC_VCO_RANGE_HIGH_SHIFT 30
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_MISC_VCO_RANGE_HIGH_DEFAULT 0x00000001
-
-/* CLKGEN :: DOCSIS_PLL_SYS0_PLL_MISC :: VCO_DIV2 [29:29] */
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_MISC_VCO_DIV2_MASK 0x20000000
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_MISC_VCO_DIV2_SHIFT 29
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_MISC_VCO_DIV2_DEFAULT 0x00000000
-
-/* CLKGEN :: DOCSIS_PLL_SYS0_PLL_MISC :: STAT_UPDATE [28:28] */
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_MISC_STAT_UPDATE_MASK 0x10000000
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_MISC_STAT_UPDATE_SHIFT 28
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_MISC_STAT_UPDATE_DEFAULT 0x00000000
-
-/* CLKGEN :: DOCSIS_PLL_SYS0_PLL_MISC :: STAT_SELECT [27:25] */
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_MISC_STAT_SELECT_MASK 0x0e000000
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_MISC_STAT_SELECT_SHIFT 25
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_MISC_STAT_SELECT_DEFAULT 0x00000000
-
-/* CLKGEN :: DOCSIS_PLL_SYS0_PLL_MISC :: STAT_RESET [24:24] */
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_MISC_STAT_RESET_MASK 0x01000000
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_MISC_STAT_RESET_SHIFT 24
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_MISC_STAT_RESET_DEFAULT 0x00000000
-
-/* CLKGEN :: DOCSIS_PLL_SYS0_PLL_MISC :: STAT_MODE [23:22] */
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_MISC_STAT_MODE_MASK 0x00c00000
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_MISC_STAT_MODE_SHIFT 22
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_MISC_STAT_MODE_DEFAULT 0x00000000
-
-/* CLKGEN :: DOCSIS_PLL_SYS0_PLL_MISC :: REF_ALT_OFFS [21:21] */
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_MISC_REF_ALT_OFFS_MASK 0x00200000
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_MISC_REF_ALT_OFFS_SHIFT 21
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_MISC_REF_ALT_OFFS_DEFAULT 0x00000000
-
-/* CLKGEN :: DOCSIS_PLL_SYS0_PLL_MISC :: PWM_RATE [20:19] */
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_MISC_PWM_RATE_MASK 0x00180000
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_MISC_PWM_RATE_SHIFT 19
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_MISC_PWM_RATE_DEFAULT 0x00000000
-
-/* CLKGEN :: DOCSIS_PLL_SYS0_PLL_MISC :: POST_CTRL_RESETB [18:17] */
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_MISC_POST_CTRL_RESETB_MASK 0x00060000
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_MISC_POST_CTRL_RESETB_SHIFT 17
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_MISC_POST_CTRL_RESETB_DEFAULT 0x00000003
-
-/* CLKGEN :: DOCSIS_PLL_SYS0_PLL_MISC :: NDIV_RELOCK [16:16] */
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_MISC_NDIV_RELOCK_MASK 0x00010000
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_MISC_NDIV_RELOCK_SHIFT 16
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_MISC_NDIV_RELOCK_DEFAULT 0x00000000
-
-/* CLKGEN :: DOCSIS_PLL_SYS0_PLL_MISC :: FAST_LOCK [15:15] */
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_MISC_FAST_LOCK_MASK 0x00008000
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_MISC_FAST_LOCK_SHIFT 15
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_MISC_FAST_LOCK_DEFAULT 0x00000000
-
-/* CLKGEN :: DOCSIS_PLL_SYS0_PLL_MISC :: DITHER_DISABLE [14:14] */
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_MISC_DITHER_DISABLE_MASK 0x00004000
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_MISC_DITHER_DISABLE_SHIFT 14
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_MISC_DITHER_DISABLE_DEFAULT 0x00000000
-
-/* CLKGEN :: DOCSIS_PLL_SYS0_PLL_MISC :: DCO_CTRL_BYPASS_ENABLE [13:13] */
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_MASK 0x00002000
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_SHIFT 13
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_DEFAULT 0x00000000
-
-/* CLKGEN :: DOCSIS_PLL_SYS0_PLL_MISC :: DCO_CTRL_BYPASS [12:01] */
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_MISC_DCO_CTRL_BYPASS_MASK 0x00001ffe
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_MISC_DCO_CTRL_BYPASS_SHIFT 1
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_MISC_DCO_CTRL_BYPASS_DEFAULT 0x00000000
-
-/* CLKGEN :: DOCSIS_PLL_SYS0_PLL_MISC :: AUX_CTRL [00:00] */
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_MISC_AUX_CTRL_MASK 0x00000001
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_MISC_AUX_CTRL_SHIFT 0
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_MISC_AUX_CTRL_DEFAULT 0x00000000
-
-/***************************************************************************
- *DOCSIS_PLL_SYS0_PLL_MISC2 - Mscellaneous control bus continued.
- ***************************************************************************/
-/* CLKGEN :: DOCSIS_PLL_SYS0_PLL_MISC2 :: PLLRESERVED0 [31:01] */
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_MISC2_PLLRESERVED0_MASK 0xfffffffe
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_MISC2_PLLRESERVED0_SHIFT 1
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_MISC2_PLLRESERVED0_DEFAULT 0x00000000
-
-/* CLKGEN :: DOCSIS_PLL_SYS0_PLL_MISC2 :: DIG_INPUT_SEL [00:00] */
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_MISC2_DIG_INPUT_SEL_MASK 0x00000001
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_MISC2_DIG_INPUT_SEL_SHIFT 0
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_MISC2_DIG_INPUT_SEL_DEFAULT 0x00000000
-
-/***************************************************************************
- *DOCSIS_PLL_SYS0_PLL_PWRON - Poweron
- ***************************************************************************/
-/* CLKGEN :: DOCSIS_PLL_SYS0_PLL_PWRON :: reserved0 [31:01] */
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_PWRON_reserved0_MASK 0xfffffffe
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_PWRON_reserved0_SHIFT 1
-
-/* CLKGEN :: DOCSIS_PLL_SYS0_PLL_PWRON :: PWRON_PLL [00:00] */
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_PWRON_PWRON_PLL_MASK 0x00000001
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_PWRON_PWRON_PLL_SHIFT 0
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_PWRON_PWRON_PLL_DEFAULT 0x00000001
-
-/***************************************************************************
- *DOCSIS_PLL_SYS0_PLL_RESET - Resets
- ***************************************************************************/
-/* CLKGEN :: DOCSIS_PLL_SYS0_PLL_RESET :: reserved0 [31:01] */
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_RESET_reserved0_MASK 0xfffffffe
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_RESET_reserved0_SHIFT 1
-
-/* CLKGEN :: DOCSIS_PLL_SYS0_PLL_RESET :: RESETD [00:00] */
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_RESET_RESETD_MASK 0x00000001
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_RESET_RESETD_SHIFT 0
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_RESET_RESETD_DEFAULT 0x00000000
-
-/***************************************************************************
- *DOCSIS_PLL_SYS0_PLL_SSC_MODE_CONTROL_HIGH - Higher bits of Spread Spectrum mode control
- ***************************************************************************/
-/* CLKGEN :: DOCSIS_PLL_SYS0_PLL_SSC_MODE_CONTROL_HIGH :: reserved0 [31:16] */
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_SSC_MODE_CONTROL_HIGH_reserved0_MASK 0xffff0000
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_SSC_MODE_CONTROL_HIGH_reserved0_SHIFT 16
-
-/* CLKGEN :: DOCSIS_PLL_SYS0_PLL_SSC_MODE_CONTROL_HIGH :: SSC_STEP [15:00] */
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_MASK 0x0000ffff
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_SHIFT 0
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *DOCSIS_PLL_SYS0_PLL_SSC_MODE_CONTROL_LOW - Lower bits of Spread Spectrum mode control
- ***************************************************************************/
-/* CLKGEN :: DOCSIS_PLL_SYS0_PLL_SSC_MODE_CONTROL_LOW :: reserved0 [31:23] */
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_SSC_MODE_CONTROL_LOW_reserved0_MASK 0xff800000
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_SSC_MODE_CONTROL_LOW_reserved0_SHIFT 23
-
-/* CLKGEN :: DOCSIS_PLL_SYS0_PLL_SSC_MODE_CONTROL_LOW :: SSC_MODE [22:22] */
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_MASK 0x00400000
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_SHIFT 22
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_DEFAULT 0x00000000
-
-/* CLKGEN :: DOCSIS_PLL_SYS0_PLL_SSC_MODE_CONTROL_LOW :: SSC_LIMIT [21:00] */
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_MASK 0x003fffff
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_SHIFT 0
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_DEFAULT 0x00000000
-
-/***************************************************************************
- *DOCSIS_PLL_SYS0_PLL_STATUS - Status
- ***************************************************************************/
-/* CLKGEN :: DOCSIS_PLL_SYS0_PLL_STATUS :: reserved0 [31:12] */
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_STATUS_reserved0_MASK 0xfffff000
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_STATUS_reserved0_SHIFT 12
-
-/* CLKGEN :: DOCSIS_PLL_SYS0_PLL_STATUS :: TEST_STATUS [11:00] */
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_STATUS_TEST_STATUS_MASK 0x00000fff
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_STATUS_TEST_STATUS_SHIFT 0
-
-/***************************************************************************
- *DOCSIS_PLL_SYS1_PLL_BG_PWRON - Bandgap Power on
- ***************************************************************************/
-/* CLKGEN :: DOCSIS_PLL_SYS1_PLL_BG_PWRON :: reserved0 [31:01] */
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_BG_PWRON_reserved0_MASK 0xfffffffe
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_BG_PWRON_reserved0_SHIFT 1
-
-/* CLKGEN :: DOCSIS_PLL_SYS1_PLL_BG_PWRON :: BG_PWRON_PLL [00:00] */
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_BG_PWRON_BG_PWRON_PLL_MASK 0x00000001
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_BG_PWRON_BG_PWRON_PLL_SHIFT 0
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_BG_PWRON_BG_PWRON_PLL_DEFAULT 0x00000001
-
-/***************************************************************************
- *DOCSIS_PLL_SYS1_PLL_CHANNEL_CTRL_CH_0 - PLL CHANNEL control CH 0
- ***************************************************************************/
-/* CLKGEN :: DOCSIS_PLL_SYS1_PLL_CHANNEL_CTRL_CH_0 :: reserved0 [31:11] */
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_CHANNEL_CTRL_CH_0_reserved0_MASK 0xfffff800
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_CHANNEL_CTRL_CH_0_reserved0_SHIFT 11
-
-/* CLKGEN :: DOCSIS_PLL_SYS1_PLL_CHANNEL_CTRL_CH_0 :: POST_DIVIDER_HOLD_CH0 [10:10] */
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_MASK 0x00000400
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_SHIFT 10
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_DEFAULT 0x00000000
-
-/* CLKGEN :: DOCSIS_PLL_SYS1_PLL_CHANNEL_CTRL_CH_0 :: PHASE_OFFSET_CH0 [09:09] */
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_MASK 0x00000200
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_SHIFT 9
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_DEFAULT 0x00000000
-
-/* CLKGEN :: DOCSIS_PLL_SYS1_PLL_CHANNEL_CTRL_CH_0 :: MDIV_CH0 [08:01] */
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_MASK 0x000001fe
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_SHIFT 1
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_DEFAULT 0x00000009
-
-/* CLKGEN :: DOCSIS_PLL_SYS1_PLL_CHANNEL_CTRL_CH_0 :: CLOCK_DIS_CH0 [00:00] */
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_MASK 0x00000001
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_SHIFT 0
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_DEFAULT 0x00000000
-
-/***************************************************************************
- *DOCSIS_PLL_SYS1_PLL_CHANNEL_CTRL_CH_1 - PLL CHANNEL control CH 1
- ***************************************************************************/
-/* CLKGEN :: DOCSIS_PLL_SYS1_PLL_CHANNEL_CTRL_CH_1 :: reserved0 [31:11] */
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_CHANNEL_CTRL_CH_1_reserved0_MASK 0xfffff800
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_CHANNEL_CTRL_CH_1_reserved0_SHIFT 11
-
-/* CLKGEN :: DOCSIS_PLL_SYS1_PLL_CHANNEL_CTRL_CH_1 :: POST_DIVIDER_HOLD_CH1 [10:10] */
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_MASK 0x00000400
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_SHIFT 10
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_DEFAULT 0x00000000
-
-/* CLKGEN :: DOCSIS_PLL_SYS1_PLL_CHANNEL_CTRL_CH_1 :: PHASE_OFFSET_CH1 [09:09] */
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_MASK 0x00000200
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_SHIFT 9
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_DEFAULT 0x00000000
-
-/* CLKGEN :: DOCSIS_PLL_SYS1_PLL_CHANNEL_CTRL_CH_1 :: MDIV_CH1 [08:01] */
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_MASK 0x000001fe
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_SHIFT 1
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_DEFAULT 0x00000006
-
-/* CLKGEN :: DOCSIS_PLL_SYS1_PLL_CHANNEL_CTRL_CH_1 :: CLOCK_DIS_CH1 [00:00] */
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_MASK 0x00000001
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_SHIFT 0
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_DEFAULT 0x00000000
-
-/***************************************************************************
- *DOCSIS_PLL_SYS1_PLL_CHANNEL_CTRL_CH_2 - PLL CHANNEL control CH 2
- ***************************************************************************/
-/* CLKGEN :: DOCSIS_PLL_SYS1_PLL_CHANNEL_CTRL_CH_2 :: reserved0 [31:11] */
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_CHANNEL_CTRL_CH_2_reserved0_MASK 0xfffff800
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_CHANNEL_CTRL_CH_2_reserved0_SHIFT 11
-
-/* CLKGEN :: DOCSIS_PLL_SYS1_PLL_CHANNEL_CTRL_CH_2 :: POST_DIVIDER_HOLD_CH2 [10:10] */
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_HOLD_CH2_MASK 0x00000400
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_HOLD_CH2_SHIFT 10
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_HOLD_CH2_DEFAULT 0x00000000
-
-/* CLKGEN :: DOCSIS_PLL_SYS1_PLL_CHANNEL_CTRL_CH_2 :: PHASE_OFFSET_CH2 [09:09] */
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_CHANNEL_CTRL_CH_2_PHASE_OFFSET_CH2_MASK 0x00000200
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_CHANNEL_CTRL_CH_2_PHASE_OFFSET_CH2_SHIFT 9
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_CHANNEL_CTRL_CH_2_PHASE_OFFSET_CH2_DEFAULT 0x00000000
-
-/* CLKGEN :: DOCSIS_PLL_SYS1_PLL_CHANNEL_CTRL_CH_2 :: MDIV_CH2 [08:01] */
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_CHANNEL_CTRL_CH_2_MDIV_CH2_MASK 0x000001fe
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_CHANNEL_CTRL_CH_2_MDIV_CH2_SHIFT 1
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_CHANNEL_CTRL_CH_2_MDIV_CH2_DEFAULT 0x00000012
-
-/* CLKGEN :: DOCSIS_PLL_SYS1_PLL_CHANNEL_CTRL_CH_2 :: CLOCK_DIS_CH2 [00:00] */
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_CHANNEL_CTRL_CH_2_CLOCK_DIS_CH2_MASK 0x00000001
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_CHANNEL_CTRL_CH_2_CLOCK_DIS_CH2_SHIFT 0
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_CHANNEL_CTRL_CH_2_CLOCK_DIS_CH2_DEFAULT 0x00000000
-
-/***************************************************************************
- *DOCSIS_PLL_SYS1_PLL_CHANNEL_CTRL_CH_3 - PLL CHANNEL control CH 3
- ***************************************************************************/
-/* CLKGEN :: DOCSIS_PLL_SYS1_PLL_CHANNEL_CTRL_CH_3 :: reserved0 [31:11] */
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_CHANNEL_CTRL_CH_3_reserved0_MASK 0xfffff800
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_CHANNEL_CTRL_CH_3_reserved0_SHIFT 11
-
-/* CLKGEN :: DOCSIS_PLL_SYS1_PLL_CHANNEL_CTRL_CH_3 :: POST_DIVIDER_HOLD_CH3 [10:10] */
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_HOLD_CH3_MASK 0x00000400
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_HOLD_CH3_SHIFT 10
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_HOLD_CH3_DEFAULT 0x00000000
-
-/* CLKGEN :: DOCSIS_PLL_SYS1_PLL_CHANNEL_CTRL_CH_3 :: PHASE_OFFSET_CH3 [09:09] */
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_CHANNEL_CTRL_CH_3_PHASE_OFFSET_CH3_MASK 0x00000200
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_CHANNEL_CTRL_CH_3_PHASE_OFFSET_CH3_SHIFT 9
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_CHANNEL_CTRL_CH_3_PHASE_OFFSET_CH3_DEFAULT 0x00000000
-
-/* CLKGEN :: DOCSIS_PLL_SYS1_PLL_CHANNEL_CTRL_CH_3 :: MDIV_CH3 [08:01] */
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_CHANNEL_CTRL_CH_3_MDIV_CH3_MASK 0x000001fe
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_CHANNEL_CTRL_CH_3_MDIV_CH3_SHIFT 1
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_CHANNEL_CTRL_CH_3_MDIV_CH3_DEFAULT 0x00000024
-
-/* CLKGEN :: DOCSIS_PLL_SYS1_PLL_CHANNEL_CTRL_CH_3 :: CLOCK_DIS_CH3 [00:00] */
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_CHANNEL_CTRL_CH_3_CLOCK_DIS_CH3_MASK 0x00000001
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_CHANNEL_CTRL_CH_3_CLOCK_DIS_CH3_SHIFT 0
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_CHANNEL_CTRL_CH_3_CLOCK_DIS_CH3_DEFAULT 0x00000000
-
-/***************************************************************************
- *DOCSIS_PLL_SYS1_PLL_CHANNEL_CTRL_CH_4 - PLL CHANNEL control CH 4
- ***************************************************************************/
-/* CLKGEN :: DOCSIS_PLL_SYS1_PLL_CHANNEL_CTRL_CH_4 :: reserved0 [31:11] */
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_CHANNEL_CTRL_CH_4_reserved0_MASK 0xfffff800
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_CHANNEL_CTRL_CH_4_reserved0_SHIFT 11
-
-/* CLKGEN :: DOCSIS_PLL_SYS1_PLL_CHANNEL_CTRL_CH_4 :: POST_DIVIDER_HOLD_CH4 [10:10] */
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_CHANNEL_CTRL_CH_4_POST_DIVIDER_HOLD_CH4_MASK 0x00000400
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_CHANNEL_CTRL_CH_4_POST_DIVIDER_HOLD_CH4_SHIFT 10
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_CHANNEL_CTRL_CH_4_POST_DIVIDER_HOLD_CH4_DEFAULT 0x00000000
-
-/* CLKGEN :: DOCSIS_PLL_SYS1_PLL_CHANNEL_CTRL_CH_4 :: PHASE_OFFSET_CH4 [09:09] */
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_CHANNEL_CTRL_CH_4_PHASE_OFFSET_CH4_MASK 0x00000200
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_CHANNEL_CTRL_CH_4_PHASE_OFFSET_CH4_SHIFT 9
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_CHANNEL_CTRL_CH_4_PHASE_OFFSET_CH4_DEFAULT 0x00000000
-
-/* CLKGEN :: DOCSIS_PLL_SYS1_PLL_CHANNEL_CTRL_CH_4 :: MDIV_CH4 [08:01] */
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_CHANNEL_CTRL_CH_4_MDIV_CH4_MASK 0x000001fe
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_CHANNEL_CTRL_CH_4_MDIV_CH4_SHIFT 1
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_CHANNEL_CTRL_CH_4_MDIV_CH4_DEFAULT 0x0000000c
-
-/* CLKGEN :: DOCSIS_PLL_SYS1_PLL_CHANNEL_CTRL_CH_4 :: CLOCK_DIS_CH4 [00:00] */
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_CHANNEL_CTRL_CH_4_CLOCK_DIS_CH4_MASK 0x00000001
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_CHANNEL_CTRL_CH_4_CLOCK_DIS_CH4_SHIFT 0
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_CHANNEL_CTRL_CH_4_CLOCK_DIS_CH4_DEFAULT 0x00000000
-
-/***************************************************************************
- *DOCSIS_PLL_SYS1_PLL_DIV - Pre multiplier
- ***************************************************************************/
-/* CLKGEN :: DOCSIS_PLL_SYS1_PLL_DIV :: reserved0 [31:14] */
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_DIV_reserved0_MASK 0xffffc000
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_DIV_reserved0_SHIFT 14
-
-/* CLKGEN :: DOCSIS_PLL_SYS1_PLL_DIV :: PDIV [13:10] */
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_DIV_PDIV_MASK 0x00003c00
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_DIV_PDIV_SHIFT 10
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_DIV_PDIV_DEFAULT 0x00000003
-
-/* CLKGEN :: DOCSIS_PLL_SYS1_PLL_DIV :: NDIV_INT [09:00] */
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_DIV_NDIV_INT_MASK 0x000003ff
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_DIV_NDIV_INT_SHIFT 0
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_DIV_NDIV_INT_DEFAULT 0x000000c8
-
-/***************************************************************************
- *DOCSIS_PLL_SYS1_PLL_GAIN - PLL GAIN
- ***************************************************************************/
-/* CLKGEN :: DOCSIS_PLL_SYS1_PLL_GAIN :: reserved0 [31:10] */
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_GAIN_reserved0_MASK 0xfffffc00
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_GAIN_reserved0_SHIFT 10
-
-/* CLKGEN :: DOCSIS_PLL_SYS1_PLL_GAIN :: LOOP_GAIN_PROPORTIONAL_IN_PHASE [09:06] */
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_MASK 0x000003c0
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_SHIFT 6
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_DEFAULT 0x00000005
-
-/* CLKGEN :: DOCSIS_PLL_SYS1_PLL_GAIN :: LOOP_GAIN_IN_FREQ [05:03] */
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_GAIN_LOOP_GAIN_IN_FREQ_MASK 0x00000038
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_GAIN_LOOP_GAIN_IN_FREQ_SHIFT 3
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_GAIN_LOOP_GAIN_IN_FREQ_DEFAULT 0x00000000
-
-/* CLKGEN :: DOCSIS_PLL_SYS1_PLL_GAIN :: LOOP_GAIN_INTEGRATOR_IN_PHASE [02:00] */
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_MASK 0x00000007
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_SHIFT 0
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_DEFAULT 0x00000003
-
-/***************************************************************************
- *DOCSIS_PLL_SYS1_PLL_HOLD_CH_ALL - Hold PLL all channels
- ***************************************************************************/
-/* CLKGEN :: DOCSIS_PLL_SYS1_PLL_HOLD_CH_ALL :: reserved0 [31:01] */
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_HOLD_CH_ALL_reserved0_MASK 0xfffffffe
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_HOLD_CH_ALL_reserved0_SHIFT 1
-
-/* CLKGEN :: DOCSIS_PLL_SYS1_PLL_HOLD_CH_ALL :: HOLD_CH_ALL [00:00] */
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_HOLD_CH_ALL_HOLD_CH_ALL_MASK 0x00000001
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_HOLD_CH_ALL_HOLD_CH_ALL_SHIFT 0
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_HOLD_CH_ALL_HOLD_CH_ALL_DEFAULT 0x00000000
-
-/***************************************************************************
- *DOCSIS_PLL_SYS1_PLL_LDO_CTRL - Ldo voltage control
- ***************************************************************************/
-/* CLKGEN :: DOCSIS_PLL_SYS1_PLL_LDO_CTRL :: reserved0 [31:16] */
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_LDO_CTRL_reserved0_MASK 0xffff0000
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_LDO_CTRL_reserved0_SHIFT 16
-
-/* CLKGEN :: DOCSIS_PLL_SYS1_PLL_LDO_CTRL :: LDO_CTRL [15:00] */
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_LDO_CTRL_LDO_CTRL_MASK 0x0000ffff
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_LDO_CTRL_LDO_CTRL_SHIFT 0
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_LDO_CTRL_LDO_CTRL_DEFAULT 0x00000005
-
-/***************************************************************************
- *DOCSIS_PLL_SYS1_PLL_LDO_PWRON - LDO Power on
- ***************************************************************************/
-/* CLKGEN :: DOCSIS_PLL_SYS1_PLL_LDO_PWRON :: reserved0 [31:01] */
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_LDO_PWRON_reserved0_MASK 0xfffffffe
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_LDO_PWRON_reserved0_SHIFT 1
-
-/* CLKGEN :: DOCSIS_PLL_SYS1_PLL_LDO_PWRON :: LDO_PWRON_PLL [00:00] */
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_LDO_PWRON_LDO_PWRON_PLL_MASK 0x00000001
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_LDO_PWRON_LDO_PWRON_PLL_SHIFT 0
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_LDO_PWRON_LDO_PWRON_PLL_DEFAULT 0x00000001
-
-/***************************************************************************
- *DOCSIS_PLL_SYS1_PLL_LOCK_STATUS - Lock Status
- ***************************************************************************/
-/* CLKGEN :: DOCSIS_PLL_SYS1_PLL_LOCK_STATUS :: reserved0 [31:02] */
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_LOCK_STATUS_reserved0_MASK 0xfffffffc
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_LOCK_STATUS_reserved0_SHIFT 2
-
-/* CLKGEN :: DOCSIS_PLL_SYS1_PLL_LOCK_STATUS :: LOCK_LOST [01:01] */
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_LOCK_STATUS_LOCK_LOST_MASK 0x00000002
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_LOCK_STATUS_LOCK_LOST_SHIFT 1
-
-/* CLKGEN :: DOCSIS_PLL_SYS1_PLL_LOCK_STATUS :: LOCK [00:00] */
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_LOCK_STATUS_LOCK_MASK 0x00000001
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_LOCK_STATUS_LOCK_SHIFT 0
-
-/***************************************************************************
- *DOCSIS_PLL_SYS1_PLL_MISC - Mscellaneous control bus.
- ***************************************************************************/
-/* CLKGEN :: DOCSIS_PLL_SYS1_PLL_MISC :: VCO_RANGE_LOW [31:31] */
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_MISC_VCO_RANGE_LOW_MASK 0x80000000
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_MISC_VCO_RANGE_LOW_SHIFT 31
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_MISC_VCO_RANGE_LOW_DEFAULT 0x00000000
-
-/* CLKGEN :: DOCSIS_PLL_SYS1_PLL_MISC :: VCO_RANGE_HIGH [30:30] */
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_MISC_VCO_RANGE_HIGH_MASK 0x40000000
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_MISC_VCO_RANGE_HIGH_SHIFT 30
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_MISC_VCO_RANGE_HIGH_DEFAULT 0x00000001
-
-/* CLKGEN :: DOCSIS_PLL_SYS1_PLL_MISC :: VCO_DIV2 [29:29] */
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_MISC_VCO_DIV2_MASK 0x20000000
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_MISC_VCO_DIV2_SHIFT 29
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_MISC_VCO_DIV2_DEFAULT 0x00000000
-
-/* CLKGEN :: DOCSIS_PLL_SYS1_PLL_MISC :: STAT_UPDATE [28:28] */
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_MISC_STAT_UPDATE_MASK 0x10000000
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_MISC_STAT_UPDATE_SHIFT 28
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_MISC_STAT_UPDATE_DEFAULT 0x00000000
-
-/* CLKGEN :: DOCSIS_PLL_SYS1_PLL_MISC :: STAT_SELECT [27:25] */
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_MISC_STAT_SELECT_MASK 0x0e000000
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_MISC_STAT_SELECT_SHIFT 25
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_MISC_STAT_SELECT_DEFAULT 0x00000000
-
-/* CLKGEN :: DOCSIS_PLL_SYS1_PLL_MISC :: STAT_RESET [24:24] */
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_MISC_STAT_RESET_MASK 0x01000000
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_MISC_STAT_RESET_SHIFT 24
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_MISC_STAT_RESET_DEFAULT 0x00000000
-
-/* CLKGEN :: DOCSIS_PLL_SYS1_PLL_MISC :: STAT_MODE [23:22] */
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_MISC_STAT_MODE_MASK 0x00c00000
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_MISC_STAT_MODE_SHIFT 22
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_MISC_STAT_MODE_DEFAULT 0x00000000
-
-/* CLKGEN :: DOCSIS_PLL_SYS1_PLL_MISC :: REF_ALT_OFFS [21:21] */
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_MISC_REF_ALT_OFFS_MASK 0x00200000
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_MISC_REF_ALT_OFFS_SHIFT 21
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_MISC_REF_ALT_OFFS_DEFAULT 0x00000000
-
-/* CLKGEN :: DOCSIS_PLL_SYS1_PLL_MISC :: PWM_RATE [20:19] */
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_MISC_PWM_RATE_MASK 0x00180000
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_MISC_PWM_RATE_SHIFT 19
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_MISC_PWM_RATE_DEFAULT 0x00000000
-
-/* CLKGEN :: DOCSIS_PLL_SYS1_PLL_MISC :: POST_CTRL_RESETB [18:17] */
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_MISC_POST_CTRL_RESETB_MASK 0x00060000
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_MISC_POST_CTRL_RESETB_SHIFT 17
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_MISC_POST_CTRL_RESETB_DEFAULT 0x00000003
-
-/* CLKGEN :: DOCSIS_PLL_SYS1_PLL_MISC :: NDIV_RELOCK [16:16] */
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_MISC_NDIV_RELOCK_MASK 0x00010000
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_MISC_NDIV_RELOCK_SHIFT 16
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_MISC_NDIV_RELOCK_DEFAULT 0x00000000
-
-/* CLKGEN :: DOCSIS_PLL_SYS1_PLL_MISC :: FAST_LOCK [15:15] */
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_MISC_FAST_LOCK_MASK 0x00008000
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_MISC_FAST_LOCK_SHIFT 15
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_MISC_FAST_LOCK_DEFAULT 0x00000000
-
-/* CLKGEN :: DOCSIS_PLL_SYS1_PLL_MISC :: DITHER_DISABLE [14:14] */
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_MISC_DITHER_DISABLE_MASK 0x00004000
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_MISC_DITHER_DISABLE_SHIFT 14
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_MISC_DITHER_DISABLE_DEFAULT 0x00000000
-
-/* CLKGEN :: DOCSIS_PLL_SYS1_PLL_MISC :: DCO_CTRL_BYPASS_ENABLE [13:13] */
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_MASK 0x00002000
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_SHIFT 13
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_DEFAULT 0x00000000
-
-/* CLKGEN :: DOCSIS_PLL_SYS1_PLL_MISC :: DCO_CTRL_BYPASS [12:01] */
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_MISC_DCO_CTRL_BYPASS_MASK 0x00001ffe
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_MISC_DCO_CTRL_BYPASS_SHIFT 1
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_MISC_DCO_CTRL_BYPASS_DEFAULT 0x00000000
-
-/* CLKGEN :: DOCSIS_PLL_SYS1_PLL_MISC :: AUX_CTRL [00:00] */
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_MISC_AUX_CTRL_MASK 0x00000001
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_MISC_AUX_CTRL_SHIFT 0
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_MISC_AUX_CTRL_DEFAULT 0x00000000
-
-/***************************************************************************
- *DOCSIS_PLL_SYS1_PLL_MISC2 - Mscellaneous control bus continued.
- ***************************************************************************/
-/* CLKGEN :: DOCSIS_PLL_SYS1_PLL_MISC2 :: PLLRESERVED0 [31:01] */
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_MISC2_PLLRESERVED0_MASK 0xfffffffe
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_MISC2_PLLRESERVED0_SHIFT 1
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_MISC2_PLLRESERVED0_DEFAULT 0x00000000
-
-/* CLKGEN :: DOCSIS_PLL_SYS1_PLL_MISC2 :: DIG_INPUT_SEL [00:00] */
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_MISC2_DIG_INPUT_SEL_MASK 0x00000001
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_MISC2_DIG_INPUT_SEL_SHIFT 0
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_MISC2_DIG_INPUT_SEL_DEFAULT 0x00000000
-
-/***************************************************************************
- *DOCSIS_PLL_SYS1_PLL_PWRON - Poweron
- ***************************************************************************/
-/* CLKGEN :: DOCSIS_PLL_SYS1_PLL_PWRON :: reserved0 [31:01] */
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_PWRON_reserved0_MASK 0xfffffffe
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_PWRON_reserved0_SHIFT 1
-
-/* CLKGEN :: DOCSIS_PLL_SYS1_PLL_PWRON :: PWRON_PLL [00:00] */
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_PWRON_PWRON_PLL_MASK 0x00000001
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_PWRON_PWRON_PLL_SHIFT 0
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_PWRON_PWRON_PLL_DEFAULT 0x00000001
-
-/***************************************************************************
- *DOCSIS_PLL_SYS1_PLL_RESET - Resets
- ***************************************************************************/
-/* CLKGEN :: DOCSIS_PLL_SYS1_PLL_RESET :: reserved0 [31:01] */
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_RESET_reserved0_MASK 0xfffffffe
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_RESET_reserved0_SHIFT 1
-
-/* CLKGEN :: DOCSIS_PLL_SYS1_PLL_RESET :: RESETD [00:00] */
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_RESET_RESETD_MASK 0x00000001
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_RESET_RESETD_SHIFT 0
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_RESET_RESETD_DEFAULT 0x00000000
-
-/***************************************************************************
- *DOCSIS_PLL_SYS1_PLL_SSC_MODE_CONTROL_HIGH - Higher bits of Spread Spectrum mode control
- ***************************************************************************/
-/* CLKGEN :: DOCSIS_PLL_SYS1_PLL_SSC_MODE_CONTROL_HIGH :: reserved0 [31:16] */
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_SSC_MODE_CONTROL_HIGH_reserved0_MASK 0xffff0000
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_SSC_MODE_CONTROL_HIGH_reserved0_SHIFT 16
-
-/* CLKGEN :: DOCSIS_PLL_SYS1_PLL_SSC_MODE_CONTROL_HIGH :: SSC_STEP [15:00] */
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_MASK 0x0000ffff
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_SHIFT 0
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *DOCSIS_PLL_SYS1_PLL_SSC_MODE_CONTROL_LOW - Lower bits of Spread Spectrum mode control
- ***************************************************************************/
-/* CLKGEN :: DOCSIS_PLL_SYS1_PLL_SSC_MODE_CONTROL_LOW :: reserved0 [31:23] */
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_SSC_MODE_CONTROL_LOW_reserved0_MASK 0xff800000
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_SSC_MODE_CONTROL_LOW_reserved0_SHIFT 23
-
-/* CLKGEN :: DOCSIS_PLL_SYS1_PLL_SSC_MODE_CONTROL_LOW :: SSC_MODE [22:22] */
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_MASK 0x00400000
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_SHIFT 22
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_DEFAULT 0x00000000
-
-/* CLKGEN :: DOCSIS_PLL_SYS1_PLL_SSC_MODE_CONTROL_LOW :: SSC_LIMIT [21:00] */
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_MASK 0x003fffff
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_SHIFT 0
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_DEFAULT 0x00000000
-
-/***************************************************************************
- *DOCSIS_PLL_SYS1_PLL_STATUS - Status
- ***************************************************************************/
-/* CLKGEN :: DOCSIS_PLL_SYS1_PLL_STATUS :: reserved0 [31:12] */
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_STATUS_reserved0_MASK 0xfffff000
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_STATUS_reserved0_SHIFT 12
-
-/* CLKGEN :: DOCSIS_PLL_SYS1_PLL_STATUS :: TEST_STATUS [11:00] */
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_STATUS_TEST_STATUS_MASK 0x00000fff
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_STATUS_TEST_STATUS_SHIFT 0
-
-/***************************************************************************
- *DOCSIS_PLL_SYS2_PLL_BG_PWRON - Bandgap Power on
- ***************************************************************************/
-/* CLKGEN :: DOCSIS_PLL_SYS2_PLL_BG_PWRON :: reserved0 [31:01] */
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_BG_PWRON_reserved0_MASK 0xfffffffe
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_BG_PWRON_reserved0_SHIFT 1
-
-/* CLKGEN :: DOCSIS_PLL_SYS2_PLL_BG_PWRON :: BG_PWRON_PLL [00:00] */
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_BG_PWRON_BG_PWRON_PLL_MASK 0x00000001
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_BG_PWRON_BG_PWRON_PLL_SHIFT 0
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_BG_PWRON_BG_PWRON_PLL_DEFAULT 0x00000001
-
-/***************************************************************************
- *DOCSIS_PLL_SYS2_PLL_CHANNEL_CTRL_CH_2 - PLL CHANNEL control CH 2
- ***************************************************************************/
-/* CLKGEN :: DOCSIS_PLL_SYS2_PLL_CHANNEL_CTRL_CH_2 :: reserved0 [31:11] */
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_CHANNEL_CTRL_CH_2_reserved0_MASK 0xfffff800
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_CHANNEL_CTRL_CH_2_reserved0_SHIFT 11
-
-/* CLKGEN :: DOCSIS_PLL_SYS2_PLL_CHANNEL_CTRL_CH_2 :: POST_DIVIDER_HOLD_CH2 [10:10] */
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_HOLD_CH2_MASK 0x00000400
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_HOLD_CH2_SHIFT 10
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_HOLD_CH2_DEFAULT 0x00000000
-
-/* CLKGEN :: DOCSIS_PLL_SYS2_PLL_CHANNEL_CTRL_CH_2 :: PHASE_OFFSET_CH2 [09:09] */
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_CHANNEL_CTRL_CH_2_PHASE_OFFSET_CH2_MASK 0x00000200
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_CHANNEL_CTRL_CH_2_PHASE_OFFSET_CH2_SHIFT 9
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_CHANNEL_CTRL_CH_2_PHASE_OFFSET_CH2_DEFAULT 0x00000000
-
-/* CLKGEN :: DOCSIS_PLL_SYS2_PLL_CHANNEL_CTRL_CH_2 :: MDIV_CH2 [08:01] */
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_CHANNEL_CTRL_CH_2_MDIV_CH2_MASK 0x000001fe
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_CHANNEL_CTRL_CH_2_MDIV_CH2_SHIFT 1
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_CHANNEL_CTRL_CH_2_MDIV_CH2_DEFAULT 0x00000009
-
-/* CLKGEN :: DOCSIS_PLL_SYS2_PLL_CHANNEL_CTRL_CH_2 :: CLOCK_DIS_CH2 [00:00] */
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_CHANNEL_CTRL_CH_2_CLOCK_DIS_CH2_MASK 0x00000001
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_CHANNEL_CTRL_CH_2_CLOCK_DIS_CH2_SHIFT 0
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_CHANNEL_CTRL_CH_2_CLOCK_DIS_CH2_DEFAULT 0x00000000
-
-/***************************************************************************
- *DOCSIS_PLL_SYS2_PLL_DIV - Pre multiplier
- ***************************************************************************/
-/* CLKGEN :: DOCSIS_PLL_SYS2_PLL_DIV :: reserved0 [31:14] */
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_DIV_reserved0_MASK 0xffffc000
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_DIV_reserved0_SHIFT 14
-
-/* CLKGEN :: DOCSIS_PLL_SYS2_PLL_DIV :: PDIV [13:10] */
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_DIV_PDIV_MASK 0x00003c00
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_DIV_PDIV_SHIFT 10
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_DIV_PDIV_DEFAULT 0x00000003
-
-/* CLKGEN :: DOCSIS_PLL_SYS2_PLL_DIV :: NDIV_INT [09:00] */
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_DIV_NDIV_INT_MASK 0x000003ff
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_DIV_NDIV_INT_SHIFT 0
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_DIV_NDIV_INT_DEFAULT 0x0000007d
-
-/***************************************************************************
- *DOCSIS_PLL_SYS2_PLL_GAIN - PLL GAIN
- ***************************************************************************/
-/* CLKGEN :: DOCSIS_PLL_SYS2_PLL_GAIN :: reserved0 [31:10] */
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_GAIN_reserved0_MASK 0xfffffc00
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_GAIN_reserved0_SHIFT 10
-
-/* CLKGEN :: DOCSIS_PLL_SYS2_PLL_GAIN :: LOOP_GAIN_PROPORTIONAL_IN_PHASE [09:06] */
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_MASK 0x000003c0
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_SHIFT 6
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_DEFAULT 0x00000007
-
-/* CLKGEN :: DOCSIS_PLL_SYS2_PLL_GAIN :: LOOP_GAIN_IN_FREQ [05:03] */
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_GAIN_LOOP_GAIN_IN_FREQ_MASK 0x00000038
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_GAIN_LOOP_GAIN_IN_FREQ_SHIFT 3
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_GAIN_LOOP_GAIN_IN_FREQ_DEFAULT 0x00000000
-
-/* CLKGEN :: DOCSIS_PLL_SYS2_PLL_GAIN :: LOOP_GAIN_INTEGRATOR_IN_PHASE [02:00] */
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_MASK 0x00000007
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_SHIFT 0
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_DEFAULT 0x00000003
-
-/***************************************************************************
- *DOCSIS_PLL_SYS2_PLL_HOLD_CH_ALL - Hold PLL all channels
- ***************************************************************************/
-/* CLKGEN :: DOCSIS_PLL_SYS2_PLL_HOLD_CH_ALL :: reserved0 [31:01] */
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_HOLD_CH_ALL_reserved0_MASK 0xfffffffe
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_HOLD_CH_ALL_reserved0_SHIFT 1
-
-/* CLKGEN :: DOCSIS_PLL_SYS2_PLL_HOLD_CH_ALL :: HOLD_CH_ALL [00:00] */
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_HOLD_CH_ALL_HOLD_CH_ALL_MASK 0x00000001
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_HOLD_CH_ALL_HOLD_CH_ALL_SHIFT 0
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_HOLD_CH_ALL_HOLD_CH_ALL_DEFAULT 0x00000000
-
-/***************************************************************************
- *DOCSIS_PLL_SYS2_PLL_LDO_CTRL - Ldo voltage control
- ***************************************************************************/
-/* CLKGEN :: DOCSIS_PLL_SYS2_PLL_LDO_CTRL :: reserved0 [31:16] */
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_LDO_CTRL_reserved0_MASK 0xffff0000
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_LDO_CTRL_reserved0_SHIFT 16
-
-/* CLKGEN :: DOCSIS_PLL_SYS2_PLL_LDO_CTRL :: LDO_CTRL [15:00] */
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_LDO_CTRL_LDO_CTRL_MASK 0x0000ffff
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_LDO_CTRL_LDO_CTRL_SHIFT 0
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_LDO_CTRL_LDO_CTRL_DEFAULT 0x00000005
-
-/***************************************************************************
- *DOCSIS_PLL_SYS2_PLL_LDO_PWRON - LDO Power on
- ***************************************************************************/
-/* CLKGEN :: DOCSIS_PLL_SYS2_PLL_LDO_PWRON :: reserved0 [31:01] */
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_LDO_PWRON_reserved0_MASK 0xfffffffe
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_LDO_PWRON_reserved0_SHIFT 1
-
-/* CLKGEN :: DOCSIS_PLL_SYS2_PLL_LDO_PWRON :: LDO_PWRON_PLL [00:00] */
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_LDO_PWRON_LDO_PWRON_PLL_MASK 0x00000001
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_LDO_PWRON_LDO_PWRON_PLL_SHIFT 0
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_LDO_PWRON_LDO_PWRON_PLL_DEFAULT 0x00000001
-
-/***************************************************************************
- *DOCSIS_PLL_SYS2_PLL_LOCK_STATUS - Lock Status
- ***************************************************************************/
-/* CLKGEN :: DOCSIS_PLL_SYS2_PLL_LOCK_STATUS :: reserved0 [31:02] */
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_LOCK_STATUS_reserved0_MASK 0xfffffffc
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_LOCK_STATUS_reserved0_SHIFT 2
-
-/* CLKGEN :: DOCSIS_PLL_SYS2_PLL_LOCK_STATUS :: LOCK_LOST [01:01] */
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_LOCK_STATUS_LOCK_LOST_MASK 0x00000002
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_LOCK_STATUS_LOCK_LOST_SHIFT 1
-
-/* CLKGEN :: DOCSIS_PLL_SYS2_PLL_LOCK_STATUS :: LOCK [00:00] */
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_LOCK_STATUS_LOCK_MASK 0x00000001
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_LOCK_STATUS_LOCK_SHIFT 0
-
-/***************************************************************************
- *DOCSIS_PLL_SYS2_PLL_MISC - Mscellaneous control bus.
- ***************************************************************************/
-/* CLKGEN :: DOCSIS_PLL_SYS2_PLL_MISC :: VCO_RANGE_LOW [31:31] */
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_MISC_VCO_RANGE_LOW_MASK 0x80000000
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_MISC_VCO_RANGE_LOW_SHIFT 31
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_MISC_VCO_RANGE_LOW_DEFAULT 0x00000000
-
-/* CLKGEN :: DOCSIS_PLL_SYS2_PLL_MISC :: VCO_RANGE_HIGH [30:30] */
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_MISC_VCO_RANGE_HIGH_MASK 0x40000000
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_MISC_VCO_RANGE_HIGH_SHIFT 30
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_MISC_VCO_RANGE_HIGH_DEFAULT 0x00000001
-
-/* CLKGEN :: DOCSIS_PLL_SYS2_PLL_MISC :: VCO_DIV2 [29:29] */
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_MISC_VCO_DIV2_MASK 0x20000000
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_MISC_VCO_DIV2_SHIFT 29
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_MISC_VCO_DIV2_DEFAULT 0x00000000
-
-/* CLKGEN :: DOCSIS_PLL_SYS2_PLL_MISC :: STAT_UPDATE [28:28] */
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_MISC_STAT_UPDATE_MASK 0x10000000
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_MISC_STAT_UPDATE_SHIFT 28
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_MISC_STAT_UPDATE_DEFAULT 0x00000000
-
-/* CLKGEN :: DOCSIS_PLL_SYS2_PLL_MISC :: STAT_SELECT [27:25] */
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_MISC_STAT_SELECT_MASK 0x0e000000
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_MISC_STAT_SELECT_SHIFT 25
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_MISC_STAT_SELECT_DEFAULT 0x00000000
-
-/* CLKGEN :: DOCSIS_PLL_SYS2_PLL_MISC :: STAT_RESET [24:24] */
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_MISC_STAT_RESET_MASK 0x01000000
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_MISC_STAT_RESET_SHIFT 24
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_MISC_STAT_RESET_DEFAULT 0x00000000
-
-/* CLKGEN :: DOCSIS_PLL_SYS2_PLL_MISC :: STAT_MODE [23:22] */
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_MISC_STAT_MODE_MASK 0x00c00000
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_MISC_STAT_MODE_SHIFT 22
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_MISC_STAT_MODE_DEFAULT 0x00000000
-
-/* CLKGEN :: DOCSIS_PLL_SYS2_PLL_MISC :: REF_ALT_OFFS [21:21] */
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_MISC_REF_ALT_OFFS_MASK 0x00200000
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_MISC_REF_ALT_OFFS_SHIFT 21
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_MISC_REF_ALT_OFFS_DEFAULT 0x00000000
-
-/* CLKGEN :: DOCSIS_PLL_SYS2_PLL_MISC :: PWM_RATE [20:19] */
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_MISC_PWM_RATE_MASK 0x00180000
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_MISC_PWM_RATE_SHIFT 19
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_MISC_PWM_RATE_DEFAULT 0x00000000
-
-/* CLKGEN :: DOCSIS_PLL_SYS2_PLL_MISC :: POST_CTRL_RESETB [18:17] */
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_MISC_POST_CTRL_RESETB_MASK 0x00060000
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_MISC_POST_CTRL_RESETB_SHIFT 17
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_MISC_POST_CTRL_RESETB_DEFAULT 0x00000000
-
-/* CLKGEN :: DOCSIS_PLL_SYS2_PLL_MISC :: NDIV_RELOCK [16:16] */
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_MISC_NDIV_RELOCK_MASK 0x00010000
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_MISC_NDIV_RELOCK_SHIFT 16
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_MISC_NDIV_RELOCK_DEFAULT 0x00000000
-
-/* CLKGEN :: DOCSIS_PLL_SYS2_PLL_MISC :: FAST_LOCK [15:15] */
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_MISC_FAST_LOCK_MASK 0x00008000
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_MISC_FAST_LOCK_SHIFT 15
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_MISC_FAST_LOCK_DEFAULT 0x00000000
-
-/* CLKGEN :: DOCSIS_PLL_SYS2_PLL_MISC :: DITHER_DISABLE [14:14] */
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_MISC_DITHER_DISABLE_MASK 0x00004000
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_MISC_DITHER_DISABLE_SHIFT 14
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_MISC_DITHER_DISABLE_DEFAULT 0x00000000
-
-/* CLKGEN :: DOCSIS_PLL_SYS2_PLL_MISC :: DCO_CTRL_BYPASS_ENABLE [13:13] */
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_MASK 0x00002000
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_SHIFT 13
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_DEFAULT 0x00000000
-
-/* CLKGEN :: DOCSIS_PLL_SYS2_PLL_MISC :: DCO_CTRL_BYPASS [12:01] */
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_MISC_DCO_CTRL_BYPASS_MASK 0x00001ffe
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_MISC_DCO_CTRL_BYPASS_SHIFT 1
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_MISC_DCO_CTRL_BYPASS_DEFAULT 0x00000000
-
-/* CLKGEN :: DOCSIS_PLL_SYS2_PLL_MISC :: AUX_CTRL [00:00] */
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_MISC_AUX_CTRL_MASK 0x00000001
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_MISC_AUX_CTRL_SHIFT 0
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_MISC_AUX_CTRL_DEFAULT 0x00000000
-
-/***************************************************************************
- *DOCSIS_PLL_SYS2_PLL_MISC2 - Mscellaneous control bus continued.
- ***************************************************************************/
-/* CLKGEN :: DOCSIS_PLL_SYS2_PLL_MISC2 :: PLLRESERVED0 [31:01] */
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_MISC2_PLLRESERVED0_MASK 0xfffffffe
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_MISC2_PLLRESERVED0_SHIFT 1
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_MISC2_PLLRESERVED0_DEFAULT 0x00000000
-
-/* CLKGEN :: DOCSIS_PLL_SYS2_PLL_MISC2 :: DIG_INPUT_SEL [00:00] */
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_MISC2_DIG_INPUT_SEL_MASK 0x00000001
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_MISC2_DIG_INPUT_SEL_SHIFT 0
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_MISC2_DIG_INPUT_SEL_DEFAULT 0x00000000
-
-/***************************************************************************
- *DOCSIS_PLL_SYS2_PLL_PWRON - Poweron
- ***************************************************************************/
-/* CLKGEN :: DOCSIS_PLL_SYS2_PLL_PWRON :: reserved0 [31:01] */
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_PWRON_reserved0_MASK 0xfffffffe
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_PWRON_reserved0_SHIFT 1
-
-/* CLKGEN :: DOCSIS_PLL_SYS2_PLL_PWRON :: PWRON_PLL [00:00] */
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_PWRON_PWRON_PLL_MASK 0x00000001
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_PWRON_PWRON_PLL_SHIFT 0
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_PWRON_PWRON_PLL_DEFAULT 0x00000001
-
-/***************************************************************************
- *DOCSIS_PLL_SYS2_PLL_RESET - Resets
- ***************************************************************************/
-/* CLKGEN :: DOCSIS_PLL_SYS2_PLL_RESET :: reserved0 [31:02] */
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_RESET_reserved0_MASK 0xfffffffc
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_RESET_reserved0_SHIFT 2
-
-/* CLKGEN :: DOCSIS_PLL_SYS2_PLL_RESET :: RESETD [01:01] */
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_RESET_RESETD_MASK 0x00000002
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_RESET_RESETD_SHIFT 1
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_RESET_RESETD_DEFAULT 0x00000000
-
-/* CLKGEN :: DOCSIS_PLL_SYS2_PLL_RESET :: RESETA [00:00] */
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_RESET_RESETA_MASK 0x00000001
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_RESET_RESETA_SHIFT 0
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_RESET_RESETA_DEFAULT 0x00000000
-
-/***************************************************************************
- *DOCSIS_PLL_SYS2_PLL_SSC_MODE_CONTROL_HIGH - Higher bits of Spread Spectrum mode control
- ***************************************************************************/
-/* CLKGEN :: DOCSIS_PLL_SYS2_PLL_SSC_MODE_CONTROL_HIGH :: reserved0 [31:16] */
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_SSC_MODE_CONTROL_HIGH_reserved0_MASK 0xffff0000
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_SSC_MODE_CONTROL_HIGH_reserved0_SHIFT 16
-
-/* CLKGEN :: DOCSIS_PLL_SYS2_PLL_SSC_MODE_CONTROL_HIGH :: SSC_STEP [15:00] */
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_MASK 0x0000ffff
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_SHIFT 0
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *DOCSIS_PLL_SYS2_PLL_SSC_MODE_CONTROL_LOW - Lower bits of Spread Spectrum mode control
- ***************************************************************************/
-/* CLKGEN :: DOCSIS_PLL_SYS2_PLL_SSC_MODE_CONTROL_LOW :: reserved0 [31:23] */
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_SSC_MODE_CONTROL_LOW_reserved0_MASK 0xff800000
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_SSC_MODE_CONTROL_LOW_reserved0_SHIFT 23
-
-/* CLKGEN :: DOCSIS_PLL_SYS2_PLL_SSC_MODE_CONTROL_LOW :: SSC_MODE [22:22] */
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_MASK 0x00400000
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_SHIFT 22
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_DEFAULT 0x00000000
-
-/* CLKGEN :: DOCSIS_PLL_SYS2_PLL_SSC_MODE_CONTROL_LOW :: SSC_LIMIT [21:00] */
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_MASK 0x003fffff
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_SHIFT 0
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_DEFAULT 0x00000000
-
-/***************************************************************************
- *DOCSIS_PLL_SYS2_PLL_STATUS - Status
- ***************************************************************************/
-/* CLKGEN :: DOCSIS_PLL_SYS2_PLL_STATUS :: reserved0 [31:12] */
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_STATUS_reserved0_MASK 0xfffff000
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_STATUS_reserved0_SHIFT 12
-
-/* CLKGEN :: DOCSIS_PLL_SYS2_PLL_STATUS :: TEST_STATUS [11:00] */
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_STATUS_TEST_STATUS_MASK 0x00000fff
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_STATUS_TEST_STATUS_SHIFT 0
-
-/***************************************************************************
- *PLL_AUDIO0_PLL_BG_PWRON - Bandgap Power on
- ***************************************************************************/
-/* CLKGEN :: PLL_AUDIO0_PLL_BG_PWRON :: reserved0 [31:01] */
-#define BCHP_CLKGEN_PLL_AUDIO0_PLL_BG_PWRON_reserved0_MASK 0xfffffffe
-#define BCHP_CLKGEN_PLL_AUDIO0_PLL_BG_PWRON_reserved0_SHIFT 1
-
-/* CLKGEN :: PLL_AUDIO0_PLL_BG_PWRON :: BG_PWRON_PLL [00:00] */
-#define BCHP_CLKGEN_PLL_AUDIO0_PLL_BG_PWRON_BG_PWRON_PLL_MASK 0x00000001
-#define BCHP_CLKGEN_PLL_AUDIO0_PLL_BG_PWRON_BG_PWRON_PLL_SHIFT 0
-#define BCHP_CLKGEN_PLL_AUDIO0_PLL_BG_PWRON_BG_PWRON_PLL_DEFAULT 0x00000001
-
-/***************************************************************************
- *PLL_AUDIO0_PLL_DIV - Pre multiplier
- ***************************************************************************/
-/* CLKGEN :: PLL_AUDIO0_PLL_DIV :: reserved0 [31:04] */
-#define BCHP_CLKGEN_PLL_AUDIO0_PLL_DIV_reserved0_MASK 0xfffffff0
-#define BCHP_CLKGEN_PLL_AUDIO0_PLL_DIV_reserved0_SHIFT 4
-
-/* CLKGEN :: PLL_AUDIO0_PLL_DIV :: PDIV [03:00] */
-#define BCHP_CLKGEN_PLL_AUDIO0_PLL_DIV_PDIV_MASK 0x0000000f
-#define BCHP_CLKGEN_PLL_AUDIO0_PLL_DIV_PDIV_SHIFT 0
-#define BCHP_CLKGEN_PLL_AUDIO0_PLL_DIV_PDIV_DEFAULT 0x00000000
-
-/***************************************************************************
- *PLL_AUDIO0_PLL_GAIN - PLL GAIN
- ***************************************************************************/
-/* CLKGEN :: PLL_AUDIO0_PLL_GAIN :: reserved0 [31:10] */
-#define BCHP_CLKGEN_PLL_AUDIO0_PLL_GAIN_reserved0_MASK 0xfffffc00
-#define BCHP_CLKGEN_PLL_AUDIO0_PLL_GAIN_reserved0_SHIFT 10
-
-/* CLKGEN :: PLL_AUDIO0_PLL_GAIN :: LOOP_GAIN_PROPORTIONAL_IN_PHASE [09:06] */
-#define BCHP_CLKGEN_PLL_AUDIO0_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_MASK 0x000003c0
-#define BCHP_CLKGEN_PLL_AUDIO0_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_SHIFT 6
-#define BCHP_CLKGEN_PLL_AUDIO0_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_DEFAULT 0x00000008
-
-/* CLKGEN :: PLL_AUDIO0_PLL_GAIN :: LOOP_GAIN_IN_FREQ [05:03] */
-#define BCHP_CLKGEN_PLL_AUDIO0_PLL_GAIN_LOOP_GAIN_IN_FREQ_MASK 0x00000038
-#define BCHP_CLKGEN_PLL_AUDIO0_PLL_GAIN_LOOP_GAIN_IN_FREQ_SHIFT 3
-#define BCHP_CLKGEN_PLL_AUDIO0_PLL_GAIN_LOOP_GAIN_IN_FREQ_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_AUDIO0_PLL_GAIN :: LOOP_GAIN_INTEGRATOR_IN_PHASE [02:00] */
-#define BCHP_CLKGEN_PLL_AUDIO0_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_MASK 0x00000007
-#define BCHP_CLKGEN_PLL_AUDIO0_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_SHIFT 0
-#define BCHP_CLKGEN_PLL_AUDIO0_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_DEFAULT 0x00000004
-
-/***************************************************************************
- *PLL_AUDIO0_PLL_LDO_CTRL - Ldo voltage control
- ***************************************************************************/
-/* CLKGEN :: PLL_AUDIO0_PLL_LDO_CTRL :: reserved0 [31:16] */
-#define BCHP_CLKGEN_PLL_AUDIO0_PLL_LDO_CTRL_reserved0_MASK 0xffff0000
-#define BCHP_CLKGEN_PLL_AUDIO0_PLL_LDO_CTRL_reserved0_SHIFT 16
-
-/* CLKGEN :: PLL_AUDIO0_PLL_LDO_CTRL :: LDO_CTRL [15:00] */
-#define BCHP_CLKGEN_PLL_AUDIO0_PLL_LDO_CTRL_LDO_CTRL_MASK 0x0000ffff
-#define BCHP_CLKGEN_PLL_AUDIO0_PLL_LDO_CTRL_LDO_CTRL_SHIFT 0
-#define BCHP_CLKGEN_PLL_AUDIO0_PLL_LDO_CTRL_LDO_CTRL_DEFAULT 0x00000005
-
-/***************************************************************************
- *PLL_AUDIO0_PLL_LDO_PWRON - LDO Power on
- ***************************************************************************/
-/* CLKGEN :: PLL_AUDIO0_PLL_LDO_PWRON :: reserved0 [31:01] */
-#define BCHP_CLKGEN_PLL_AUDIO0_PLL_LDO_PWRON_reserved0_MASK 0xfffffffe
-#define BCHP_CLKGEN_PLL_AUDIO0_PLL_LDO_PWRON_reserved0_SHIFT 1
-
-/* CLKGEN :: PLL_AUDIO0_PLL_LDO_PWRON :: LDO_PWRON_PLL [00:00] */
-#define BCHP_CLKGEN_PLL_AUDIO0_PLL_LDO_PWRON_LDO_PWRON_PLL_MASK 0x00000001
-#define BCHP_CLKGEN_PLL_AUDIO0_PLL_LDO_PWRON_LDO_PWRON_PLL_SHIFT 0
-#define BCHP_CLKGEN_PLL_AUDIO0_PLL_LDO_PWRON_LDO_PWRON_PLL_DEFAULT 0x00000001
-
-/***************************************************************************
- *PLL_AUDIO0_PLL_LOCK_STATUS - Lock Status
- ***************************************************************************/
-/* CLKGEN :: PLL_AUDIO0_PLL_LOCK_STATUS :: reserved0 [31:02] */
-#define BCHP_CLKGEN_PLL_AUDIO0_PLL_LOCK_STATUS_reserved0_MASK 0xfffffffc
-#define BCHP_CLKGEN_PLL_AUDIO0_PLL_LOCK_STATUS_reserved0_SHIFT 2
-
-/* CLKGEN :: PLL_AUDIO0_PLL_LOCK_STATUS :: LOCK_LOST [01:01] */
-#define BCHP_CLKGEN_PLL_AUDIO0_PLL_LOCK_STATUS_LOCK_LOST_MASK 0x00000002
-#define BCHP_CLKGEN_PLL_AUDIO0_PLL_LOCK_STATUS_LOCK_LOST_SHIFT 1
-
-/* CLKGEN :: PLL_AUDIO0_PLL_LOCK_STATUS :: LOCK [00:00] */
-#define BCHP_CLKGEN_PLL_AUDIO0_PLL_LOCK_STATUS_LOCK_MASK 0x00000001
-#define BCHP_CLKGEN_PLL_AUDIO0_PLL_LOCK_STATUS_LOCK_SHIFT 0
-
-/***************************************************************************
- *PLL_AUDIO0_PLL_PWRON - Poweron
- ***************************************************************************/
-/* CLKGEN :: PLL_AUDIO0_PLL_PWRON :: reserved0 [31:01] */
-#define BCHP_CLKGEN_PLL_AUDIO0_PLL_PWRON_reserved0_MASK 0xfffffffe
-#define BCHP_CLKGEN_PLL_AUDIO0_PLL_PWRON_reserved0_SHIFT 1
-
-/* CLKGEN :: PLL_AUDIO0_PLL_PWRON :: PWRON_PLL [00:00] */
-#define BCHP_CLKGEN_PLL_AUDIO0_PLL_PWRON_PWRON_PLL_MASK 0x00000001
-#define BCHP_CLKGEN_PLL_AUDIO0_PLL_PWRON_PWRON_PLL_SHIFT 0
-#define BCHP_CLKGEN_PLL_AUDIO0_PLL_PWRON_PWRON_PLL_DEFAULT 0x00000001
-
-/***************************************************************************
- *PLL_AUDIO0_PLL_RESET - Resets
- ***************************************************************************/
-/* CLKGEN :: PLL_AUDIO0_PLL_RESET :: reserved0 [31:02] */
-#define BCHP_CLKGEN_PLL_AUDIO0_PLL_RESET_reserved0_MASK 0xfffffffc
-#define BCHP_CLKGEN_PLL_AUDIO0_PLL_RESET_reserved0_SHIFT 2
-
-/* CLKGEN :: PLL_AUDIO0_PLL_RESET :: RESETD [01:01] */
-#define BCHP_CLKGEN_PLL_AUDIO0_PLL_RESET_RESETD_MASK 0x00000002
-#define BCHP_CLKGEN_PLL_AUDIO0_PLL_RESET_RESETD_SHIFT 1
-#define BCHP_CLKGEN_PLL_AUDIO0_PLL_RESET_RESETD_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_AUDIO0_PLL_RESET :: RESETA [00:00] */
-#define BCHP_CLKGEN_PLL_AUDIO0_PLL_RESET_RESETA_MASK 0x00000001
-#define BCHP_CLKGEN_PLL_AUDIO0_PLL_RESET_RESETA_SHIFT 0
-#define BCHP_CLKGEN_PLL_AUDIO0_PLL_RESET_RESETA_DEFAULT 0x00000000
-
-/***************************************************************************
- *PLL_AUDIO0_PLL_SSC_MODE_CONTROL_HIGH - Higher bits of Spread Spectrum mode control
- ***************************************************************************/
-/* CLKGEN :: PLL_AUDIO0_PLL_SSC_MODE_CONTROL_HIGH :: reserved0 [31:16] */
-#define BCHP_CLKGEN_PLL_AUDIO0_PLL_SSC_MODE_CONTROL_HIGH_reserved0_MASK 0xffff0000
-#define BCHP_CLKGEN_PLL_AUDIO0_PLL_SSC_MODE_CONTROL_HIGH_reserved0_SHIFT 16
-
-/* CLKGEN :: PLL_AUDIO0_PLL_SSC_MODE_CONTROL_HIGH :: SSC_STEP [15:00] */
-#define BCHP_CLKGEN_PLL_AUDIO0_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_MASK 0x0000ffff
-#define BCHP_CLKGEN_PLL_AUDIO0_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_SHIFT 0
-#define BCHP_CLKGEN_PLL_AUDIO0_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *PLL_AUDIO0_PLL_SSC_MODE_CONTROL_LOW - Lower bits of Spread Spectrum mode control
- ***************************************************************************/
-/* CLKGEN :: PLL_AUDIO0_PLL_SSC_MODE_CONTROL_LOW :: reserved0 [31:23] */
-#define BCHP_CLKGEN_PLL_AUDIO0_PLL_SSC_MODE_CONTROL_LOW_reserved0_MASK 0xff800000
-#define BCHP_CLKGEN_PLL_AUDIO0_PLL_SSC_MODE_CONTROL_LOW_reserved0_SHIFT 23
-
-/* CLKGEN :: PLL_AUDIO0_PLL_SSC_MODE_CONTROL_LOW :: SSC_MODE [22:22] */
-#define BCHP_CLKGEN_PLL_AUDIO0_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_MASK 0x00400000
-#define BCHP_CLKGEN_PLL_AUDIO0_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_SHIFT 22
-#define BCHP_CLKGEN_PLL_AUDIO0_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_AUDIO0_PLL_SSC_MODE_CONTROL_LOW :: SSC_LIMIT [21:00] */
-#define BCHP_CLKGEN_PLL_AUDIO0_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_MASK 0x003fffff
-#define BCHP_CLKGEN_PLL_AUDIO0_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_SHIFT 0
-#define BCHP_CLKGEN_PLL_AUDIO0_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_DEFAULT 0x00000000
-
-/***************************************************************************
- *PLL_AUDIO0_PLL_STATUS - Status
- ***************************************************************************/
-/* CLKGEN :: PLL_AUDIO0_PLL_STATUS :: reserved0 [31:12] */
-#define BCHP_CLKGEN_PLL_AUDIO0_PLL_STATUS_reserved0_MASK 0xfffff000
-#define BCHP_CLKGEN_PLL_AUDIO0_PLL_STATUS_reserved0_SHIFT 12
-
-/* CLKGEN :: PLL_AUDIO0_PLL_STATUS :: TEST_STATUS [11:00] */
-#define BCHP_CLKGEN_PLL_AUDIO0_PLL_STATUS_TEST_STATUS_MASK 0x00000fff
-#define BCHP_CLKGEN_PLL_AUDIO0_PLL_STATUS_TEST_STATUS_SHIFT 0
-
-/***************************************************************************
- *PLL_AUDIO1_PLL_BG_PWRON - Bandgap Power on
- ***************************************************************************/
-/* CLKGEN :: PLL_AUDIO1_PLL_BG_PWRON :: reserved0 [31:01] */
-#define BCHP_CLKGEN_PLL_AUDIO1_PLL_BG_PWRON_reserved0_MASK 0xfffffffe
-#define BCHP_CLKGEN_PLL_AUDIO1_PLL_BG_PWRON_reserved0_SHIFT 1
-
-/* CLKGEN :: PLL_AUDIO1_PLL_BG_PWRON :: BG_PWRON_PLL [00:00] */
-#define BCHP_CLKGEN_PLL_AUDIO1_PLL_BG_PWRON_BG_PWRON_PLL_MASK 0x00000001
-#define BCHP_CLKGEN_PLL_AUDIO1_PLL_BG_PWRON_BG_PWRON_PLL_SHIFT 0
-#define BCHP_CLKGEN_PLL_AUDIO1_PLL_BG_PWRON_BG_PWRON_PLL_DEFAULT 0x00000001
-
-/***************************************************************************
- *PLL_AUDIO1_PLL_DIV - Pre multiplier
- ***************************************************************************/
-/* CLKGEN :: PLL_AUDIO1_PLL_DIV :: reserved0 [31:04] */
-#define BCHP_CLKGEN_PLL_AUDIO1_PLL_DIV_reserved0_MASK 0xfffffff0
-#define BCHP_CLKGEN_PLL_AUDIO1_PLL_DIV_reserved0_SHIFT 4
-
-/* CLKGEN :: PLL_AUDIO1_PLL_DIV :: PDIV [03:00] */
-#define BCHP_CLKGEN_PLL_AUDIO1_PLL_DIV_PDIV_MASK 0x0000000f
-#define BCHP_CLKGEN_PLL_AUDIO1_PLL_DIV_PDIV_SHIFT 0
-#define BCHP_CLKGEN_PLL_AUDIO1_PLL_DIV_PDIV_DEFAULT 0x00000000
-
-/***************************************************************************
- *PLL_AUDIO1_PLL_GAIN - PLL GAIN
- ***************************************************************************/
-/* CLKGEN :: PLL_AUDIO1_PLL_GAIN :: reserved0 [31:10] */
-#define BCHP_CLKGEN_PLL_AUDIO1_PLL_GAIN_reserved0_MASK 0xfffffc00
-#define BCHP_CLKGEN_PLL_AUDIO1_PLL_GAIN_reserved0_SHIFT 10
-
-/* CLKGEN :: PLL_AUDIO1_PLL_GAIN :: LOOP_GAIN_PROPORTIONAL_IN_PHASE [09:06] */
-#define BCHP_CLKGEN_PLL_AUDIO1_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_MASK 0x000003c0
-#define BCHP_CLKGEN_PLL_AUDIO1_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_SHIFT 6
-#define BCHP_CLKGEN_PLL_AUDIO1_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_DEFAULT 0x00000008
-
-/* CLKGEN :: PLL_AUDIO1_PLL_GAIN :: LOOP_GAIN_IN_FREQ [05:03] */
-#define BCHP_CLKGEN_PLL_AUDIO1_PLL_GAIN_LOOP_GAIN_IN_FREQ_MASK 0x00000038
-#define BCHP_CLKGEN_PLL_AUDIO1_PLL_GAIN_LOOP_GAIN_IN_FREQ_SHIFT 3
-#define BCHP_CLKGEN_PLL_AUDIO1_PLL_GAIN_LOOP_GAIN_IN_FREQ_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_AUDIO1_PLL_GAIN :: LOOP_GAIN_INTEGRATOR_IN_PHASE [02:00] */
-#define BCHP_CLKGEN_PLL_AUDIO1_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_MASK 0x00000007
-#define BCHP_CLKGEN_PLL_AUDIO1_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_SHIFT 0
-#define BCHP_CLKGEN_PLL_AUDIO1_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_DEFAULT 0x00000004
-
-/***************************************************************************
- *PLL_AUDIO1_PLL_LDO_CTRL - Ldo voltage control
- ***************************************************************************/
-/* CLKGEN :: PLL_AUDIO1_PLL_LDO_CTRL :: reserved0 [31:16] */
-#define BCHP_CLKGEN_PLL_AUDIO1_PLL_LDO_CTRL_reserved0_MASK 0xffff0000
-#define BCHP_CLKGEN_PLL_AUDIO1_PLL_LDO_CTRL_reserved0_SHIFT 16
-
-/* CLKGEN :: PLL_AUDIO1_PLL_LDO_CTRL :: LDO_CTRL [15:00] */
-#define BCHP_CLKGEN_PLL_AUDIO1_PLL_LDO_CTRL_LDO_CTRL_MASK 0x0000ffff
-#define BCHP_CLKGEN_PLL_AUDIO1_PLL_LDO_CTRL_LDO_CTRL_SHIFT 0
-#define BCHP_CLKGEN_PLL_AUDIO1_PLL_LDO_CTRL_LDO_CTRL_DEFAULT 0x00000005
-
-/***************************************************************************
- *PLL_AUDIO1_PLL_LDO_PWRON - LDO Power on
- ***************************************************************************/
-/* CLKGEN :: PLL_AUDIO1_PLL_LDO_PWRON :: reserved0 [31:01] */
-#define BCHP_CLKGEN_PLL_AUDIO1_PLL_LDO_PWRON_reserved0_MASK 0xfffffffe
-#define BCHP_CLKGEN_PLL_AUDIO1_PLL_LDO_PWRON_reserved0_SHIFT 1
-
-/* CLKGEN :: PLL_AUDIO1_PLL_LDO_PWRON :: LDO_PWRON_PLL [00:00] */
-#define BCHP_CLKGEN_PLL_AUDIO1_PLL_LDO_PWRON_LDO_PWRON_PLL_MASK 0x00000001
-#define BCHP_CLKGEN_PLL_AUDIO1_PLL_LDO_PWRON_LDO_PWRON_PLL_SHIFT 0
-#define BCHP_CLKGEN_PLL_AUDIO1_PLL_LDO_PWRON_LDO_PWRON_PLL_DEFAULT 0x00000001
-
-/***************************************************************************
- *PLL_AUDIO1_PLL_LOCK_STATUS - Lock Status
- ***************************************************************************/
-/* CLKGEN :: PLL_AUDIO1_PLL_LOCK_STATUS :: reserved0 [31:02] */
-#define BCHP_CLKGEN_PLL_AUDIO1_PLL_LOCK_STATUS_reserved0_MASK 0xfffffffc
-#define BCHP_CLKGEN_PLL_AUDIO1_PLL_LOCK_STATUS_reserved0_SHIFT 2
-
-/* CLKGEN :: PLL_AUDIO1_PLL_LOCK_STATUS :: LOCK_LOST [01:01] */
-#define BCHP_CLKGEN_PLL_AUDIO1_PLL_LOCK_STATUS_LOCK_LOST_MASK 0x00000002
-#define BCHP_CLKGEN_PLL_AUDIO1_PLL_LOCK_STATUS_LOCK_LOST_SHIFT 1
-
-/* CLKGEN :: PLL_AUDIO1_PLL_LOCK_STATUS :: LOCK [00:00] */
-#define BCHP_CLKGEN_PLL_AUDIO1_PLL_LOCK_STATUS_LOCK_MASK 0x00000001
-#define BCHP_CLKGEN_PLL_AUDIO1_PLL_LOCK_STATUS_LOCK_SHIFT 0
-
-/***************************************************************************
- *PLL_AUDIO1_PLL_PWRON - Poweron
- ***************************************************************************/
-/* CLKGEN :: PLL_AUDIO1_PLL_PWRON :: reserved0 [31:01] */
-#define BCHP_CLKGEN_PLL_AUDIO1_PLL_PWRON_reserved0_MASK 0xfffffffe
-#define BCHP_CLKGEN_PLL_AUDIO1_PLL_PWRON_reserved0_SHIFT 1
-
-/* CLKGEN :: PLL_AUDIO1_PLL_PWRON :: PWRON_PLL [00:00] */
-#define BCHP_CLKGEN_PLL_AUDIO1_PLL_PWRON_PWRON_PLL_MASK 0x00000001
-#define BCHP_CLKGEN_PLL_AUDIO1_PLL_PWRON_PWRON_PLL_SHIFT 0
-#define BCHP_CLKGEN_PLL_AUDIO1_PLL_PWRON_PWRON_PLL_DEFAULT 0x00000001
-
-/***************************************************************************
- *PLL_AUDIO1_PLL_RESET - Resets
- ***************************************************************************/
-/* CLKGEN :: PLL_AUDIO1_PLL_RESET :: reserved0 [31:02] */
-#define BCHP_CLKGEN_PLL_AUDIO1_PLL_RESET_reserved0_MASK 0xfffffffc
-#define BCHP_CLKGEN_PLL_AUDIO1_PLL_RESET_reserved0_SHIFT 2
-
-/* CLKGEN :: PLL_AUDIO1_PLL_RESET :: RESETD [01:01] */
-#define BCHP_CLKGEN_PLL_AUDIO1_PLL_RESET_RESETD_MASK 0x00000002
-#define BCHP_CLKGEN_PLL_AUDIO1_PLL_RESET_RESETD_SHIFT 1
-#define BCHP_CLKGEN_PLL_AUDIO1_PLL_RESET_RESETD_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_AUDIO1_PLL_RESET :: RESETA [00:00] */
-#define BCHP_CLKGEN_PLL_AUDIO1_PLL_RESET_RESETA_MASK 0x00000001
-#define BCHP_CLKGEN_PLL_AUDIO1_PLL_RESET_RESETA_SHIFT 0
-#define BCHP_CLKGEN_PLL_AUDIO1_PLL_RESET_RESETA_DEFAULT 0x00000000
-
-/***************************************************************************
- *PLL_AUDIO1_PLL_SSC_MODE_CONTROL_HIGH - Higher bits of Spread Spectrum mode control
- ***************************************************************************/
-/* CLKGEN :: PLL_AUDIO1_PLL_SSC_MODE_CONTROL_HIGH :: reserved0 [31:16] */
-#define BCHP_CLKGEN_PLL_AUDIO1_PLL_SSC_MODE_CONTROL_HIGH_reserved0_MASK 0xffff0000
-#define BCHP_CLKGEN_PLL_AUDIO1_PLL_SSC_MODE_CONTROL_HIGH_reserved0_SHIFT 16
-
-/* CLKGEN :: PLL_AUDIO1_PLL_SSC_MODE_CONTROL_HIGH :: SSC_STEP [15:00] */
-#define BCHP_CLKGEN_PLL_AUDIO1_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_MASK 0x0000ffff
-#define BCHP_CLKGEN_PLL_AUDIO1_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_SHIFT 0
-#define BCHP_CLKGEN_PLL_AUDIO1_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *PLL_AUDIO1_PLL_SSC_MODE_CONTROL_LOW - Lower bits of Spread Spectrum mode control
- ***************************************************************************/
-/* CLKGEN :: PLL_AUDIO1_PLL_SSC_MODE_CONTROL_LOW :: reserved0 [31:23] */
-#define BCHP_CLKGEN_PLL_AUDIO1_PLL_SSC_MODE_CONTROL_LOW_reserved0_MASK 0xff800000
-#define BCHP_CLKGEN_PLL_AUDIO1_PLL_SSC_MODE_CONTROL_LOW_reserved0_SHIFT 23
-
-/* CLKGEN :: PLL_AUDIO1_PLL_SSC_MODE_CONTROL_LOW :: SSC_MODE [22:22] */
-#define BCHP_CLKGEN_PLL_AUDIO1_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_MASK 0x00400000
-#define BCHP_CLKGEN_PLL_AUDIO1_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_SHIFT 22
-#define BCHP_CLKGEN_PLL_AUDIO1_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_AUDIO1_PLL_SSC_MODE_CONTROL_LOW :: SSC_LIMIT [21:00] */
-#define BCHP_CLKGEN_PLL_AUDIO1_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_MASK 0x003fffff
-#define BCHP_CLKGEN_PLL_AUDIO1_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_SHIFT 0
-#define BCHP_CLKGEN_PLL_AUDIO1_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_DEFAULT 0x00000000
-
-/***************************************************************************
- *PLL_AUDIO1_PLL_STATUS - Status
- ***************************************************************************/
-/* CLKGEN :: PLL_AUDIO1_PLL_STATUS :: reserved0 [31:12] */
-#define BCHP_CLKGEN_PLL_AUDIO1_PLL_STATUS_reserved0_MASK 0xfffff000
-#define BCHP_CLKGEN_PLL_AUDIO1_PLL_STATUS_reserved0_SHIFT 12
-
-/* CLKGEN :: PLL_AUDIO1_PLL_STATUS :: TEST_STATUS [11:00] */
-#define BCHP_CLKGEN_PLL_AUDIO1_PLL_STATUS_TEST_STATUS_MASK 0x00000fff
-#define BCHP_CLKGEN_PLL_AUDIO1_PLL_STATUS_TEST_STATUS_SHIFT 0
-
-/***************************************************************************
- *PLL_AUDIO2_PLL_BG_PWRON - Bandgap Power on
- ***************************************************************************/
-/* CLKGEN :: PLL_AUDIO2_PLL_BG_PWRON :: reserved0 [31:01] */
-#define BCHP_CLKGEN_PLL_AUDIO2_PLL_BG_PWRON_reserved0_MASK 0xfffffffe
-#define BCHP_CLKGEN_PLL_AUDIO2_PLL_BG_PWRON_reserved0_SHIFT 1
-
-/* CLKGEN :: PLL_AUDIO2_PLL_BG_PWRON :: BG_PWRON_PLL [00:00] */
-#define BCHP_CLKGEN_PLL_AUDIO2_PLL_BG_PWRON_BG_PWRON_PLL_MASK 0x00000001
-#define BCHP_CLKGEN_PLL_AUDIO2_PLL_BG_PWRON_BG_PWRON_PLL_SHIFT 0
-#define BCHP_CLKGEN_PLL_AUDIO2_PLL_BG_PWRON_BG_PWRON_PLL_DEFAULT 0x00000001
-
-/***************************************************************************
- *PLL_AUDIO2_PLL_DIV - Pre multiplier
- ***************************************************************************/
-/* CLKGEN :: PLL_AUDIO2_PLL_DIV :: reserved0 [31:04] */
-#define BCHP_CLKGEN_PLL_AUDIO2_PLL_DIV_reserved0_MASK 0xfffffff0
-#define BCHP_CLKGEN_PLL_AUDIO2_PLL_DIV_reserved0_SHIFT 4
-
-/* CLKGEN :: PLL_AUDIO2_PLL_DIV :: PDIV [03:00] */
-#define BCHP_CLKGEN_PLL_AUDIO2_PLL_DIV_PDIV_MASK 0x0000000f
-#define BCHP_CLKGEN_PLL_AUDIO2_PLL_DIV_PDIV_SHIFT 0
-#define BCHP_CLKGEN_PLL_AUDIO2_PLL_DIV_PDIV_DEFAULT 0x00000000
-
-/***************************************************************************
- *PLL_AUDIO2_PLL_GAIN - PLL GAIN
- ***************************************************************************/
-/* CLKGEN :: PLL_AUDIO2_PLL_GAIN :: reserved0 [31:10] */
-#define BCHP_CLKGEN_PLL_AUDIO2_PLL_GAIN_reserved0_MASK 0xfffffc00
-#define BCHP_CLKGEN_PLL_AUDIO2_PLL_GAIN_reserved0_SHIFT 10
-
-/* CLKGEN :: PLL_AUDIO2_PLL_GAIN :: LOOP_GAIN_PROPORTIONAL_IN_PHASE [09:06] */
-#define BCHP_CLKGEN_PLL_AUDIO2_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_MASK 0x000003c0
-#define BCHP_CLKGEN_PLL_AUDIO2_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_SHIFT 6
-#define BCHP_CLKGEN_PLL_AUDIO2_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_DEFAULT 0x00000008
-
-/* CLKGEN :: PLL_AUDIO2_PLL_GAIN :: LOOP_GAIN_IN_FREQ [05:03] */
-#define BCHP_CLKGEN_PLL_AUDIO2_PLL_GAIN_LOOP_GAIN_IN_FREQ_MASK 0x00000038
-#define BCHP_CLKGEN_PLL_AUDIO2_PLL_GAIN_LOOP_GAIN_IN_FREQ_SHIFT 3
-#define BCHP_CLKGEN_PLL_AUDIO2_PLL_GAIN_LOOP_GAIN_IN_FREQ_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_AUDIO2_PLL_GAIN :: LOOP_GAIN_INTEGRATOR_IN_PHASE [02:00] */
-#define BCHP_CLKGEN_PLL_AUDIO2_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_MASK 0x00000007
-#define BCHP_CLKGEN_PLL_AUDIO2_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_SHIFT 0
-#define BCHP_CLKGEN_PLL_AUDIO2_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_DEFAULT 0x00000004
-
-/***************************************************************************
- *PLL_AUDIO2_PLL_LDO_CTRL - Ldo voltage control
- ***************************************************************************/
-/* CLKGEN :: PLL_AUDIO2_PLL_LDO_CTRL :: reserved0 [31:16] */
-#define BCHP_CLKGEN_PLL_AUDIO2_PLL_LDO_CTRL_reserved0_MASK 0xffff0000
-#define BCHP_CLKGEN_PLL_AUDIO2_PLL_LDO_CTRL_reserved0_SHIFT 16
-
-/* CLKGEN :: PLL_AUDIO2_PLL_LDO_CTRL :: LDO_CTRL [15:00] */
-#define BCHP_CLKGEN_PLL_AUDIO2_PLL_LDO_CTRL_LDO_CTRL_MASK 0x0000ffff
-#define BCHP_CLKGEN_PLL_AUDIO2_PLL_LDO_CTRL_LDO_CTRL_SHIFT 0
-#define BCHP_CLKGEN_PLL_AUDIO2_PLL_LDO_CTRL_LDO_CTRL_DEFAULT 0x00000005
-
-/***************************************************************************
- *PLL_AUDIO2_PLL_LDO_PWRON - LDO Power on
- ***************************************************************************/
-/* CLKGEN :: PLL_AUDIO2_PLL_LDO_PWRON :: reserved0 [31:01] */
-#define BCHP_CLKGEN_PLL_AUDIO2_PLL_LDO_PWRON_reserved0_MASK 0xfffffffe
-#define BCHP_CLKGEN_PLL_AUDIO2_PLL_LDO_PWRON_reserved0_SHIFT 1
-
-/* CLKGEN :: PLL_AUDIO2_PLL_LDO_PWRON :: LDO_PWRON_PLL [00:00] */
-#define BCHP_CLKGEN_PLL_AUDIO2_PLL_LDO_PWRON_LDO_PWRON_PLL_MASK 0x00000001
-#define BCHP_CLKGEN_PLL_AUDIO2_PLL_LDO_PWRON_LDO_PWRON_PLL_SHIFT 0
-#define BCHP_CLKGEN_PLL_AUDIO2_PLL_LDO_PWRON_LDO_PWRON_PLL_DEFAULT 0x00000001
-
-/***************************************************************************
- *PLL_AUDIO2_PLL_LOCK_STATUS - Lock Status
- ***************************************************************************/
-/* CLKGEN :: PLL_AUDIO2_PLL_LOCK_STATUS :: reserved0 [31:02] */
-#define BCHP_CLKGEN_PLL_AUDIO2_PLL_LOCK_STATUS_reserved0_MASK 0xfffffffc
-#define BCHP_CLKGEN_PLL_AUDIO2_PLL_LOCK_STATUS_reserved0_SHIFT 2
-
-/* CLKGEN :: PLL_AUDIO2_PLL_LOCK_STATUS :: LOCK_LOST [01:01] */
-#define BCHP_CLKGEN_PLL_AUDIO2_PLL_LOCK_STATUS_LOCK_LOST_MASK 0x00000002
-#define BCHP_CLKGEN_PLL_AUDIO2_PLL_LOCK_STATUS_LOCK_LOST_SHIFT 1
-
-/* CLKGEN :: PLL_AUDIO2_PLL_LOCK_STATUS :: LOCK [00:00] */
-#define BCHP_CLKGEN_PLL_AUDIO2_PLL_LOCK_STATUS_LOCK_MASK 0x00000001
-#define BCHP_CLKGEN_PLL_AUDIO2_PLL_LOCK_STATUS_LOCK_SHIFT 0
-
-/***************************************************************************
- *PLL_AUDIO2_PLL_PWRON - Poweron
- ***************************************************************************/
-/* CLKGEN :: PLL_AUDIO2_PLL_PWRON :: reserved0 [31:01] */
-#define BCHP_CLKGEN_PLL_AUDIO2_PLL_PWRON_reserved0_MASK 0xfffffffe
-#define BCHP_CLKGEN_PLL_AUDIO2_PLL_PWRON_reserved0_SHIFT 1
-
-/* CLKGEN :: PLL_AUDIO2_PLL_PWRON :: PWRON_PLL [00:00] */
-#define BCHP_CLKGEN_PLL_AUDIO2_PLL_PWRON_PWRON_PLL_MASK 0x00000001
-#define BCHP_CLKGEN_PLL_AUDIO2_PLL_PWRON_PWRON_PLL_SHIFT 0
-#define BCHP_CLKGEN_PLL_AUDIO2_PLL_PWRON_PWRON_PLL_DEFAULT 0x00000001
-
-/***************************************************************************
- *PLL_AUDIO2_PLL_RESET - Resets
- ***************************************************************************/
-/* CLKGEN :: PLL_AUDIO2_PLL_RESET :: reserved0 [31:02] */
-#define BCHP_CLKGEN_PLL_AUDIO2_PLL_RESET_reserved0_MASK 0xfffffffc
-#define BCHP_CLKGEN_PLL_AUDIO2_PLL_RESET_reserved0_SHIFT 2
-
-/* CLKGEN :: PLL_AUDIO2_PLL_RESET :: RESETD [01:01] */
-#define BCHP_CLKGEN_PLL_AUDIO2_PLL_RESET_RESETD_MASK 0x00000002
-#define BCHP_CLKGEN_PLL_AUDIO2_PLL_RESET_RESETD_SHIFT 1
-#define BCHP_CLKGEN_PLL_AUDIO2_PLL_RESET_RESETD_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_AUDIO2_PLL_RESET :: RESETA [00:00] */
-#define BCHP_CLKGEN_PLL_AUDIO2_PLL_RESET_RESETA_MASK 0x00000001
-#define BCHP_CLKGEN_PLL_AUDIO2_PLL_RESET_RESETA_SHIFT 0
-#define BCHP_CLKGEN_PLL_AUDIO2_PLL_RESET_RESETA_DEFAULT 0x00000000
-
-/***************************************************************************
- *PLL_AUDIO2_PLL_SSC_MODE_CONTROL_HIGH - Higher bits of Spread Spectrum mode control
- ***************************************************************************/
-/* CLKGEN :: PLL_AUDIO2_PLL_SSC_MODE_CONTROL_HIGH :: reserved0 [31:16] */
-#define BCHP_CLKGEN_PLL_AUDIO2_PLL_SSC_MODE_CONTROL_HIGH_reserved0_MASK 0xffff0000
-#define BCHP_CLKGEN_PLL_AUDIO2_PLL_SSC_MODE_CONTROL_HIGH_reserved0_SHIFT 16
-
-/* CLKGEN :: PLL_AUDIO2_PLL_SSC_MODE_CONTROL_HIGH :: SSC_STEP [15:00] */
-#define BCHP_CLKGEN_PLL_AUDIO2_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_MASK 0x0000ffff
-#define BCHP_CLKGEN_PLL_AUDIO2_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_SHIFT 0
-#define BCHP_CLKGEN_PLL_AUDIO2_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *PLL_AUDIO2_PLL_SSC_MODE_CONTROL_LOW - Lower bits of Spread Spectrum mode control
- ***************************************************************************/
-/* CLKGEN :: PLL_AUDIO2_PLL_SSC_MODE_CONTROL_LOW :: reserved0 [31:23] */
-#define BCHP_CLKGEN_PLL_AUDIO2_PLL_SSC_MODE_CONTROL_LOW_reserved0_MASK 0xff800000
-#define BCHP_CLKGEN_PLL_AUDIO2_PLL_SSC_MODE_CONTROL_LOW_reserved0_SHIFT 23
-
-/* CLKGEN :: PLL_AUDIO2_PLL_SSC_MODE_CONTROL_LOW :: SSC_MODE [22:22] */
-#define BCHP_CLKGEN_PLL_AUDIO2_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_MASK 0x00400000
-#define BCHP_CLKGEN_PLL_AUDIO2_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_SHIFT 22
-#define BCHP_CLKGEN_PLL_AUDIO2_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_AUDIO2_PLL_SSC_MODE_CONTROL_LOW :: SSC_LIMIT [21:00] */
-#define BCHP_CLKGEN_PLL_AUDIO2_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_MASK 0x003fffff
-#define BCHP_CLKGEN_PLL_AUDIO2_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_SHIFT 0
-#define BCHP_CLKGEN_PLL_AUDIO2_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_DEFAULT 0x00000000
-
-/***************************************************************************
- *PLL_AUDIO2_PLL_STATUS - Status
- ***************************************************************************/
-/* CLKGEN :: PLL_AUDIO2_PLL_STATUS :: reserved0 [31:12] */
-#define BCHP_CLKGEN_PLL_AUDIO2_PLL_STATUS_reserved0_MASK 0xfffff000
-#define BCHP_CLKGEN_PLL_AUDIO2_PLL_STATUS_reserved0_SHIFT 12
-
-/* CLKGEN :: PLL_AUDIO2_PLL_STATUS :: TEST_STATUS [11:00] */
-#define BCHP_CLKGEN_PLL_AUDIO2_PLL_STATUS_TEST_STATUS_MASK 0x00000fff
-#define BCHP_CLKGEN_PLL_AUDIO2_PLL_STATUS_TEST_STATUS_SHIFT 0
-
-/***************************************************************************
- *PLL_AVD_PLL_CHANNEL_CTRL_CH_0 - PLL CHANNEL control CH 0
- ***************************************************************************/
-/* CLKGEN :: PLL_AVD_PLL_CHANNEL_CTRL_CH_0 :: reserved0 [31:11] */
-#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_0_reserved0_MASK 0xfffff800
-#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_0_reserved0_SHIFT 11
-
-/* CLKGEN :: PLL_AVD_PLL_CHANNEL_CTRL_CH_0 :: POST_DIVIDER_HOLD_CH0 [10:10] */
-#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_MASK 0x00000400
-#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_SHIFT 10
-#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_AVD_PLL_CHANNEL_CTRL_CH_0 :: PHASE_OFFSET_CH0 [09:09] */
-#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_MASK 0x00000200
-#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_SHIFT 9
-#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_AVD_PLL_CHANNEL_CTRL_CH_0 :: MDIV_CH0 [08:01] */
-#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_MASK 0x000001fe
-#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_SHIFT 1
-#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_DEFAULT 0x00000008
-
-/* CLKGEN :: PLL_AVD_PLL_CHANNEL_CTRL_CH_0 :: CLOCK_DIS_CH0 [00:00] */
-#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_MASK 0x00000001
-#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_SHIFT 0
-#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_DEFAULT 0x00000000
-
-/***************************************************************************
- *PLL_AVD_PLL_CHANNEL_CTRL_CH_1 - PLL CHANNEL control CH 1
- ***************************************************************************/
-/* CLKGEN :: PLL_AVD_PLL_CHANNEL_CTRL_CH_1 :: reserved0 [31:11] */
-#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_1_reserved0_MASK 0xfffff800
-#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_1_reserved0_SHIFT 11
-
-/* CLKGEN :: PLL_AVD_PLL_CHANNEL_CTRL_CH_1 :: POST_DIVIDER_HOLD_CH1 [10:10] */
-#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_MASK 0x00000400
-#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_SHIFT 10
-#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_AVD_PLL_CHANNEL_CTRL_CH_1 :: PHASE_OFFSET_CH1 [09:09] */
-#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_MASK 0x00000200
-#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_SHIFT 9
-#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_AVD_PLL_CHANNEL_CTRL_CH_1 :: MDIV_CH1 [08:01] */
-#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_MASK 0x000001fe
-#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_SHIFT 1
-#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_DEFAULT 0x00000007
-
-/* CLKGEN :: PLL_AVD_PLL_CHANNEL_CTRL_CH_1 :: CLOCK_DIS_CH1 [00:00] */
-#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_MASK 0x00000001
-#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_SHIFT 0
-#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_DEFAULT 0x00000000
-
-/***************************************************************************
- *PLL_AVD_PLL_CHANNEL_CTRL_CH_2 - PLL CHANNEL control CH 2
- ***************************************************************************/
-/* CLKGEN :: PLL_AVD_PLL_CHANNEL_CTRL_CH_2 :: reserved0 [31:11] */
-#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_2_reserved0_MASK 0xfffff800
-#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_2_reserved0_SHIFT 11
-
-/* CLKGEN :: PLL_AVD_PLL_CHANNEL_CTRL_CH_2 :: POST_DIVIDER_HOLD_CH2 [10:10] */
-#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_HOLD_CH2_MASK 0x00000400
-#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_HOLD_CH2_SHIFT 10
-#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_HOLD_CH2_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_AVD_PLL_CHANNEL_CTRL_CH_2 :: PHASE_OFFSET_CH2 [09:09] */
-#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_2_PHASE_OFFSET_CH2_MASK 0x00000200
-#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_2_PHASE_OFFSET_CH2_SHIFT 9
-#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_2_PHASE_OFFSET_CH2_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_AVD_PLL_CHANNEL_CTRL_CH_2 :: MDIV_CH2 [08:01] */
-#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_2_MDIV_CH2_MASK 0x000001fe
-#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_2_MDIV_CH2_SHIFT 1
-#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_2_MDIV_CH2_DEFAULT 0x00000008
-
-/* CLKGEN :: PLL_AVD_PLL_CHANNEL_CTRL_CH_2 :: CLOCK_DIS_CH2 [00:00] */
-#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_2_CLOCK_DIS_CH2_MASK 0x00000001
-#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_2_CLOCK_DIS_CH2_SHIFT 0
-#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_2_CLOCK_DIS_CH2_DEFAULT 0x00000000
-
-/***************************************************************************
- *PLL_AVD_PLL_CHANNEL_CTRL_CH_3 - PLL CHANNEL control CH 3
- ***************************************************************************/
-/* CLKGEN :: PLL_AVD_PLL_CHANNEL_CTRL_CH_3 :: reserved0 [31:11] */
-#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_3_reserved0_MASK 0xfffff800
-#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_3_reserved0_SHIFT 11
-
-/* CLKGEN :: PLL_AVD_PLL_CHANNEL_CTRL_CH_3 :: POST_DIVIDER_HOLD_CH3 [10:10] */
-#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_HOLD_CH3_MASK 0x00000400
-#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_HOLD_CH3_SHIFT 10
-#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_HOLD_CH3_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_AVD_PLL_CHANNEL_CTRL_CH_3 :: PHASE_OFFSET_CH3 [09:09] */
-#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_3_PHASE_OFFSET_CH3_MASK 0x00000200
-#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_3_PHASE_OFFSET_CH3_SHIFT 9
-#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_3_PHASE_OFFSET_CH3_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_AVD_PLL_CHANNEL_CTRL_CH_3 :: MDIV_CH3 [08:01] */
-#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_3_MDIV_CH3_MASK 0x000001fe
-#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_3_MDIV_CH3_SHIFT 1
-#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_3_MDIV_CH3_DEFAULT 0x00000007
-
-/* CLKGEN :: PLL_AVD_PLL_CHANNEL_CTRL_CH_3 :: CLOCK_DIS_CH3 [00:00] */
-#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_3_CLOCK_DIS_CH3_MASK 0x00000001
-#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_3_CLOCK_DIS_CH3_SHIFT 0
-#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_3_CLOCK_DIS_CH3_DEFAULT 0x00000000
-
-/***************************************************************************
- *PLL_AVD_PLL_CHANNEL_CTRL_CH_4 - PLL CHANNEL control CH 4
- ***************************************************************************/
-/* CLKGEN :: PLL_AVD_PLL_CHANNEL_CTRL_CH_4 :: reserved0 [31:11] */
-#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_4_reserved0_MASK 0xfffff800
-#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_4_reserved0_SHIFT 11
-
-/* CLKGEN :: PLL_AVD_PLL_CHANNEL_CTRL_CH_4 :: POST_DIVIDER_HOLD_CH4 [10:10] */
-#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_4_POST_DIVIDER_HOLD_CH4_MASK 0x00000400
-#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_4_POST_DIVIDER_HOLD_CH4_SHIFT 10
-#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_4_POST_DIVIDER_HOLD_CH4_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_AVD_PLL_CHANNEL_CTRL_CH_4 :: PHASE_OFFSET_CH4 [09:09] */
-#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_4_PHASE_OFFSET_CH4_MASK 0x00000200
-#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_4_PHASE_OFFSET_CH4_SHIFT 9
-#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_4_PHASE_OFFSET_CH4_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_AVD_PLL_CHANNEL_CTRL_CH_4 :: MDIV_CH4 [08:01] */
-#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_4_MDIV_CH4_MASK 0x000001fe
-#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_4_MDIV_CH4_SHIFT 1
-#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_4_MDIV_CH4_DEFAULT 0x00000064
-
-/* CLKGEN :: PLL_AVD_PLL_CHANNEL_CTRL_CH_4 :: CLOCK_DIS_CH4 [00:00] */
-#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_4_CLOCK_DIS_CH4_MASK 0x00000001
-#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_4_CLOCK_DIS_CH4_SHIFT 0
-#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_4_CLOCK_DIS_CH4_DEFAULT 0x00000000
-
-/***************************************************************************
- *PLL_AVD_PLL_DIV - Pre multiplier
- ***************************************************************************/
-/* CLKGEN :: PLL_AVD_PLL_DIV :: reserved0 [31:14] */
-#define BCHP_CLKGEN_PLL_AVD_PLL_DIV_reserved0_MASK 0xffffc000
-#define BCHP_CLKGEN_PLL_AVD_PLL_DIV_reserved0_SHIFT 14
-
-/* CLKGEN :: PLL_AVD_PLL_DIV :: PDIV [13:10] */
-#define BCHP_CLKGEN_PLL_AVD_PLL_DIV_PDIV_MASK 0x00003c00
-#define BCHP_CLKGEN_PLL_AVD_PLL_DIV_PDIV_SHIFT 10
-#define BCHP_CLKGEN_PLL_AVD_PLL_DIV_PDIV_DEFAULT 0x00000003
-
-/* CLKGEN :: PLL_AVD_PLL_DIV :: NDIV_INT [09:00] */
-#define BCHP_CLKGEN_PLL_AVD_PLL_DIV_NDIV_INT_MASK 0x000003ff
-#define BCHP_CLKGEN_PLL_AVD_PLL_DIV_NDIV_INT_SHIFT 0
-#define BCHP_CLKGEN_PLL_AVD_PLL_DIV_NDIV_INT_DEFAULT 0x000000c8
-
-/***************************************************************************
- *PLL_AVD_PLL_GAIN - PLL GAIN
- ***************************************************************************/
-/* CLKGEN :: PLL_AVD_PLL_GAIN :: reserved0 [31:10] */
-#define BCHP_CLKGEN_PLL_AVD_PLL_GAIN_reserved0_MASK 0xfffffc00
-#define BCHP_CLKGEN_PLL_AVD_PLL_GAIN_reserved0_SHIFT 10
-
-/* CLKGEN :: PLL_AVD_PLL_GAIN :: LOOP_GAIN_PROPORTIONAL_IN_PHASE [09:06] */
-#define BCHP_CLKGEN_PLL_AVD_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_MASK 0x000003c0
-#define BCHP_CLKGEN_PLL_AVD_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_SHIFT 6
-#define BCHP_CLKGEN_PLL_AVD_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_DEFAULT 0x00000005
-
-/* CLKGEN :: PLL_AVD_PLL_GAIN :: LOOP_GAIN_IN_FREQ [05:03] */
-#define BCHP_CLKGEN_PLL_AVD_PLL_GAIN_LOOP_GAIN_IN_FREQ_MASK 0x00000038
-#define BCHP_CLKGEN_PLL_AVD_PLL_GAIN_LOOP_GAIN_IN_FREQ_SHIFT 3
-#define BCHP_CLKGEN_PLL_AVD_PLL_GAIN_LOOP_GAIN_IN_FREQ_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_AVD_PLL_GAIN :: LOOP_GAIN_INTEGRATOR_IN_PHASE [02:00] */
-#define BCHP_CLKGEN_PLL_AVD_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_MASK 0x00000007
-#define BCHP_CLKGEN_PLL_AVD_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_SHIFT 0
-#define BCHP_CLKGEN_PLL_AVD_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_DEFAULT 0x00000002
-
-/***************************************************************************
- *PLL_AVD_PLL_LDO_PWRON - LDO Power on
- ***************************************************************************/
-/* CLKGEN :: PLL_AVD_PLL_LDO_PWRON :: reserved0 [31:01] */
-#define BCHP_CLKGEN_PLL_AVD_PLL_LDO_PWRON_reserved0_MASK 0xfffffffe
-#define BCHP_CLKGEN_PLL_AVD_PLL_LDO_PWRON_reserved0_SHIFT 1
-
-/* CLKGEN :: PLL_AVD_PLL_LDO_PWRON :: LDO_PWRON_PLL [00:00] */
-#define BCHP_CLKGEN_PLL_AVD_PLL_LDO_PWRON_LDO_PWRON_PLL_MASK 0x00000001
-#define BCHP_CLKGEN_PLL_AVD_PLL_LDO_PWRON_LDO_PWRON_PLL_SHIFT 0
-#define BCHP_CLKGEN_PLL_AVD_PLL_LDO_PWRON_LDO_PWRON_PLL_DEFAULT 0x00000001
-
-/***************************************************************************
- *PLL_AVD_PLL_LOCK_STATUS - Lock Status
- ***************************************************************************/
-/* CLKGEN :: PLL_AVD_PLL_LOCK_STATUS :: reserved0 [31:02] */
-#define BCHP_CLKGEN_PLL_AVD_PLL_LOCK_STATUS_reserved0_MASK 0xfffffffc
-#define BCHP_CLKGEN_PLL_AVD_PLL_LOCK_STATUS_reserved0_SHIFT 2
-
-/* CLKGEN :: PLL_AVD_PLL_LOCK_STATUS :: LOCK_LOST [01:01] */
-#define BCHP_CLKGEN_PLL_AVD_PLL_LOCK_STATUS_LOCK_LOST_MASK 0x00000002
-#define BCHP_CLKGEN_PLL_AVD_PLL_LOCK_STATUS_LOCK_LOST_SHIFT 1
-
-/* CLKGEN :: PLL_AVD_PLL_LOCK_STATUS :: LOCK [00:00] */
-#define BCHP_CLKGEN_PLL_AVD_PLL_LOCK_STATUS_LOCK_MASK 0x00000001
-#define BCHP_CLKGEN_PLL_AVD_PLL_LOCK_STATUS_LOCK_SHIFT 0
-
-/***************************************************************************
- *PLL_AVD_PLL_MISC - Mscellaneous control bus.
- ***************************************************************************/
-/* CLKGEN :: PLL_AVD_PLL_MISC :: VCO_RANGE [31:30] */
-#define BCHP_CLKGEN_PLL_AVD_PLL_MISC_VCO_RANGE_MASK 0xc0000000
-#define BCHP_CLKGEN_PLL_AVD_PLL_MISC_VCO_RANGE_SHIFT 30
-#define BCHP_CLKGEN_PLL_AVD_PLL_MISC_VCO_RANGE_DEFAULT 0x00000002
-
-/* CLKGEN :: PLL_AVD_PLL_MISC :: VCO_FB_DIV2 [29:29] */
-#define BCHP_CLKGEN_PLL_AVD_PLL_MISC_VCO_FB_DIV2_MASK 0x20000000
-#define BCHP_CLKGEN_PLL_AVD_PLL_MISC_VCO_FB_DIV2_SHIFT 29
-#define BCHP_CLKGEN_PLL_AVD_PLL_MISC_VCO_FB_DIV2_DEFAULT 0x00000001
-
-/* CLKGEN :: PLL_AVD_PLL_MISC :: STAT_UPDATE [28:28] */
-#define BCHP_CLKGEN_PLL_AVD_PLL_MISC_STAT_UPDATE_MASK 0x10000000
-#define BCHP_CLKGEN_PLL_AVD_PLL_MISC_STAT_UPDATE_SHIFT 28
-#define BCHP_CLKGEN_PLL_AVD_PLL_MISC_STAT_UPDATE_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_AVD_PLL_MISC :: STAT_SELECT [27:25] */
-#define BCHP_CLKGEN_PLL_AVD_PLL_MISC_STAT_SELECT_MASK 0x0e000000
-#define BCHP_CLKGEN_PLL_AVD_PLL_MISC_STAT_SELECT_SHIFT 25
-#define BCHP_CLKGEN_PLL_AVD_PLL_MISC_STAT_SELECT_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_AVD_PLL_MISC :: STAT_RESET [24:24] */
-#define BCHP_CLKGEN_PLL_AVD_PLL_MISC_STAT_RESET_MASK 0x01000000
-#define BCHP_CLKGEN_PLL_AVD_PLL_MISC_STAT_RESET_SHIFT 24
-#define BCHP_CLKGEN_PLL_AVD_PLL_MISC_STAT_RESET_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_AVD_PLL_MISC :: STAT_MODE [23:22] */
-#define BCHP_CLKGEN_PLL_AVD_PLL_MISC_STAT_MODE_MASK 0x00c00000
-#define BCHP_CLKGEN_PLL_AVD_PLL_MISC_STAT_MODE_SHIFT 22
-#define BCHP_CLKGEN_PLL_AVD_PLL_MISC_STAT_MODE_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_AVD_PLL_MISC :: PWM_RATE [21:20] */
-#define BCHP_CLKGEN_PLL_AVD_PLL_MISC_PWM_RATE_MASK 0x00300000
-#define BCHP_CLKGEN_PLL_AVD_PLL_MISC_PWM_RATE_SHIFT 20
-#define BCHP_CLKGEN_PLL_AVD_PLL_MISC_PWM_RATE_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_AVD_PLL_MISC :: POST_CTRL_RESETB [19:18] */
-#define BCHP_CLKGEN_PLL_AVD_PLL_MISC_POST_CTRL_RESETB_MASK 0x000c0000
-#define BCHP_CLKGEN_PLL_AVD_PLL_MISC_POST_CTRL_RESETB_SHIFT 18
-#define BCHP_CLKGEN_PLL_AVD_PLL_MISC_POST_CTRL_RESETB_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_AVD_PLL_MISC :: PLLRESERVED2 [17:16] */
-#define BCHP_CLKGEN_PLL_AVD_PLL_MISC_PLLRESERVED2_MASK 0x00030000
-#define BCHP_CLKGEN_PLL_AVD_PLL_MISC_PLLRESERVED2_SHIFT 16
-#define BCHP_CLKGEN_PLL_AVD_PLL_MISC_PLLRESERVED2_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_AVD_PLL_MISC :: PLLRESERVED1 [15:15] */
-#define BCHP_CLKGEN_PLL_AVD_PLL_MISC_PLLRESERVED1_MASK 0x00008000
-#define BCHP_CLKGEN_PLL_AVD_PLL_MISC_PLLRESERVED1_SHIFT 15
-#define BCHP_CLKGEN_PLL_AVD_PLL_MISC_PLLRESERVED1_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_AVD_PLL_MISC :: NDIV_RELOCK [14:14] */
-#define BCHP_CLKGEN_PLL_AVD_PLL_MISC_NDIV_RELOCK_MASK 0x00004000
-#define BCHP_CLKGEN_PLL_AVD_PLL_MISC_NDIV_RELOCK_SHIFT 14
-#define BCHP_CLKGEN_PLL_AVD_PLL_MISC_NDIV_RELOCK_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_AVD_PLL_MISC :: FAST_LOCK [13:13] */
-#define BCHP_CLKGEN_PLL_AVD_PLL_MISC_FAST_LOCK_MASK 0x00002000
-#define BCHP_CLKGEN_PLL_AVD_PLL_MISC_FAST_LOCK_SHIFT 13
-#define BCHP_CLKGEN_PLL_AVD_PLL_MISC_FAST_LOCK_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_AVD_PLL_MISC :: DCO_CTRL_BYPASS_ENABLE [12:12] */
-#define BCHP_CLKGEN_PLL_AVD_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_MASK 0x00001000
-#define BCHP_CLKGEN_PLL_AVD_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_SHIFT 12
-#define BCHP_CLKGEN_PLL_AVD_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_AVD_PLL_MISC :: DCO_CTRL_BYPASS [11:00] */
-#define BCHP_CLKGEN_PLL_AVD_PLL_MISC_DCO_CTRL_BYPASS_MASK 0x00000fff
-#define BCHP_CLKGEN_PLL_AVD_PLL_MISC_DCO_CTRL_BYPASS_SHIFT 0
-#define BCHP_CLKGEN_PLL_AVD_PLL_MISC_DCO_CTRL_BYPASS_DEFAULT 0x00000000
-
-/***************************************************************************
- *PLL_AVD_PLL_MISC2 - Mscellaneous control bus continued.
- ***************************************************************************/
-/* CLKGEN :: PLL_AVD_PLL_MISC2 :: PLLRESERVED0 [31:02] */
-#define BCHP_CLKGEN_PLL_AVD_PLL_MISC2_PLLRESERVED0_MASK 0xfffffffc
-#define BCHP_CLKGEN_PLL_AVD_PLL_MISC2_PLLRESERVED0_SHIFT 2
-#define BCHP_CLKGEN_PLL_AVD_PLL_MISC2_PLLRESERVED0_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_AVD_PLL_MISC2 :: LDO [01:00] */
-#define BCHP_CLKGEN_PLL_AVD_PLL_MISC2_LDO_MASK 0x00000003
-#define BCHP_CLKGEN_PLL_AVD_PLL_MISC2_LDO_SHIFT 0
-#define BCHP_CLKGEN_PLL_AVD_PLL_MISC2_LDO_DEFAULT 0x00000001
-
-/***************************************************************************
- *PLL_AVD_PLL_PWRON - Poweron
- ***************************************************************************/
-/* CLKGEN :: PLL_AVD_PLL_PWRON :: reserved0 [31:01] */
-#define BCHP_CLKGEN_PLL_AVD_PLL_PWRON_reserved0_MASK 0xfffffffe
-#define BCHP_CLKGEN_PLL_AVD_PLL_PWRON_reserved0_SHIFT 1
-
-/* CLKGEN :: PLL_AVD_PLL_PWRON :: PWRON_PLL [00:00] */
-#define BCHP_CLKGEN_PLL_AVD_PLL_PWRON_PWRON_PLL_MASK 0x00000001
-#define BCHP_CLKGEN_PLL_AVD_PLL_PWRON_PWRON_PLL_SHIFT 0
-#define BCHP_CLKGEN_PLL_AVD_PLL_PWRON_PWRON_PLL_DEFAULT 0x00000001
-
-/***************************************************************************
- *PLL_AVD_PLL_RESET - Resets
- ***************************************************************************/
-/* CLKGEN :: PLL_AVD_PLL_RESET :: reserved0 [31:02] */
-#define BCHP_CLKGEN_PLL_AVD_PLL_RESET_reserved0_MASK 0xfffffffc
-#define BCHP_CLKGEN_PLL_AVD_PLL_RESET_reserved0_SHIFT 2
-
-/* CLKGEN :: PLL_AVD_PLL_RESET :: RESETD [01:01] */
-#define BCHP_CLKGEN_PLL_AVD_PLL_RESET_RESETD_MASK 0x00000002
-#define BCHP_CLKGEN_PLL_AVD_PLL_RESET_RESETD_SHIFT 1
-#define BCHP_CLKGEN_PLL_AVD_PLL_RESET_RESETD_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_AVD_PLL_RESET :: RESETA [00:00] */
-#define BCHP_CLKGEN_PLL_AVD_PLL_RESET_RESETA_MASK 0x00000001
-#define BCHP_CLKGEN_PLL_AVD_PLL_RESET_RESETA_SHIFT 0
-#define BCHP_CLKGEN_PLL_AVD_PLL_RESET_RESETA_DEFAULT 0x00000000
-
-/***************************************************************************
- *PLL_AVD_PLL_SSC_MODE_CONTROL_HIGH - Higher bits of Spread Spectrum mode control
- ***************************************************************************/
-/* CLKGEN :: PLL_AVD_PLL_SSC_MODE_CONTROL_HIGH :: reserved0 [31:16] */
-#define BCHP_CLKGEN_PLL_AVD_PLL_SSC_MODE_CONTROL_HIGH_reserved0_MASK 0xffff0000
-#define BCHP_CLKGEN_PLL_AVD_PLL_SSC_MODE_CONTROL_HIGH_reserved0_SHIFT 16
-
-/* CLKGEN :: PLL_AVD_PLL_SSC_MODE_CONTROL_HIGH :: SSC_STEP [15:00] */
-#define BCHP_CLKGEN_PLL_AVD_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_MASK 0x0000ffff
-#define BCHP_CLKGEN_PLL_AVD_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_SHIFT 0
-#define BCHP_CLKGEN_PLL_AVD_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *PLL_AVD_PLL_SSC_MODE_CONTROL_LOW - Lower bits of Spread Spectrum mode control
- ***************************************************************************/
-/* CLKGEN :: PLL_AVD_PLL_SSC_MODE_CONTROL_LOW :: reserved0 [31:23] */
-#define BCHP_CLKGEN_PLL_AVD_PLL_SSC_MODE_CONTROL_LOW_reserved0_MASK 0xff800000
-#define BCHP_CLKGEN_PLL_AVD_PLL_SSC_MODE_CONTROL_LOW_reserved0_SHIFT 23
-
-/* CLKGEN :: PLL_AVD_PLL_SSC_MODE_CONTROL_LOW :: SSC_MODE [22:22] */
-#define BCHP_CLKGEN_PLL_AVD_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_MASK 0x00400000
-#define BCHP_CLKGEN_PLL_AVD_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_SHIFT 22
-#define BCHP_CLKGEN_PLL_AVD_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_AVD_PLL_SSC_MODE_CONTROL_LOW :: SSC_LIMIT [21:00] */
-#define BCHP_CLKGEN_PLL_AVD_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_MASK 0x003fffff
-#define BCHP_CLKGEN_PLL_AVD_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_SHIFT 0
-#define BCHP_CLKGEN_PLL_AVD_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_DEFAULT 0x00000000
-
-/***************************************************************************
- *PLL_AVD_PLL_STATUS - Status
- ***************************************************************************/
-/* CLKGEN :: PLL_AVD_PLL_STATUS :: reserved0 [31:12] */
-#define BCHP_CLKGEN_PLL_AVD_PLL_STATUS_reserved0_MASK 0xfffff000
-#define BCHP_CLKGEN_PLL_AVD_PLL_STATUS_reserved0_SHIFT 12
-
-/* CLKGEN :: PLL_AVD_PLL_STATUS :: TEST_STATUS [11:00] */
-#define BCHP_CLKGEN_PLL_AVD_PLL_STATUS_TEST_STATUS_MASK 0x00000fff
-#define BCHP_CLKGEN_PLL_AVD_PLL_STATUS_TEST_STATUS_SHIFT 0
-
-/***************************************************************************
- *PLL_CPU_CORE_PLL_CHANNEL_CTRL_CH_0 - PLL CHANNEL control CH 0
- ***************************************************************************/
-/* CLKGEN :: PLL_CPU_CORE_PLL_CHANNEL_CTRL_CH_0 :: reserved0 [31:11] */
-#define BCHP_CLKGEN_PLL_CPU_CORE_PLL_CHANNEL_CTRL_CH_0_reserved0_MASK 0xfffff800
-#define BCHP_CLKGEN_PLL_CPU_CORE_PLL_CHANNEL_CTRL_CH_0_reserved0_SHIFT 11
-
-/* CLKGEN :: PLL_CPU_CORE_PLL_CHANNEL_CTRL_CH_0 :: POST_DIVIDER_HOLD_CH0 [10:10] */
-#define BCHP_CLKGEN_PLL_CPU_CORE_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_MASK 0x00000400
-#define BCHP_CLKGEN_PLL_CPU_CORE_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_SHIFT 10
-#define BCHP_CLKGEN_PLL_CPU_CORE_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_CPU_CORE_PLL_CHANNEL_CTRL_CH_0 :: PHASE_OFFSET_CH0 [09:09] */
-#define BCHP_CLKGEN_PLL_CPU_CORE_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_MASK 0x00000200
-#define BCHP_CLKGEN_PLL_CPU_CORE_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_SHIFT 9
-#define BCHP_CLKGEN_PLL_CPU_CORE_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_CPU_CORE_PLL_CHANNEL_CTRL_CH_0 :: MDIV_CH0 [08:01] */
-#define BCHP_CLKGEN_PLL_CPU_CORE_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_MASK 0x000001fe
-#define BCHP_CLKGEN_PLL_CPU_CORE_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_SHIFT 1
-#define BCHP_CLKGEN_PLL_CPU_CORE_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_DEFAULT 0x00000002
-
-/* CLKGEN :: PLL_CPU_CORE_PLL_CHANNEL_CTRL_CH_0 :: CLOCK_DIS_CH0 [00:00] */
-#define BCHP_CLKGEN_PLL_CPU_CORE_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_MASK 0x00000001
-#define BCHP_CLKGEN_PLL_CPU_CORE_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_SHIFT 0
-#define BCHP_CLKGEN_PLL_CPU_CORE_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_DEFAULT 0x00000000
-
-/***************************************************************************
- *PLL_CPU_CORE_PLL_CHANNEL_CTRL_CH_1 - PLL CHANNEL control CH 1
- ***************************************************************************/
-/* CLKGEN :: PLL_CPU_CORE_PLL_CHANNEL_CTRL_CH_1 :: reserved0 [31:11] */
-#define BCHP_CLKGEN_PLL_CPU_CORE_PLL_CHANNEL_CTRL_CH_1_reserved0_MASK 0xfffff800
-#define BCHP_CLKGEN_PLL_CPU_CORE_PLL_CHANNEL_CTRL_CH_1_reserved0_SHIFT 11
-
-/* CLKGEN :: PLL_CPU_CORE_PLL_CHANNEL_CTRL_CH_1 :: POST_DIVIDER_HOLD_CH1 [10:10] */
-#define BCHP_CLKGEN_PLL_CPU_CORE_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_MASK 0x00000400
-#define BCHP_CLKGEN_PLL_CPU_CORE_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_SHIFT 10
-#define BCHP_CLKGEN_PLL_CPU_CORE_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_CPU_CORE_PLL_CHANNEL_CTRL_CH_1 :: PHASE_OFFSET_CH1 [09:09] */
-#define BCHP_CLKGEN_PLL_CPU_CORE_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_MASK 0x00000200
-#define BCHP_CLKGEN_PLL_CPU_CORE_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_SHIFT 9
-#define BCHP_CLKGEN_PLL_CPU_CORE_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_CPU_CORE_PLL_CHANNEL_CTRL_CH_1 :: MDIV_CH1 [08:01] */
-#define BCHP_CLKGEN_PLL_CPU_CORE_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_MASK 0x000001fe
-#define BCHP_CLKGEN_PLL_CPU_CORE_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_SHIFT 1
-#define BCHP_CLKGEN_PLL_CPU_CORE_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_DEFAULT 0x00000064
-
-/* CLKGEN :: PLL_CPU_CORE_PLL_CHANNEL_CTRL_CH_1 :: CLOCK_DIS_CH1 [00:00] */
-#define BCHP_CLKGEN_PLL_CPU_CORE_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_MASK 0x00000001
-#define BCHP_CLKGEN_PLL_CPU_CORE_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_SHIFT 0
-#define BCHP_CLKGEN_PLL_CPU_CORE_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_DEFAULT 0x00000001
-
-/***************************************************************************
- *PLL_CPU_CORE_PLL_DIV - Pre multiplier
- ***************************************************************************/
-/* CLKGEN :: PLL_CPU_CORE_PLL_DIV :: reserved0 [31:14] */
-#define BCHP_CLKGEN_PLL_CPU_CORE_PLL_DIV_reserved0_MASK 0xffffc000
-#define BCHP_CLKGEN_PLL_CPU_CORE_PLL_DIV_reserved0_SHIFT 14
-
-/* CLKGEN :: PLL_CPU_CORE_PLL_DIV :: PDIV [13:10] */
-#define BCHP_CLKGEN_PLL_CPU_CORE_PLL_DIV_PDIV_MASK 0x00003c00
-#define BCHP_CLKGEN_PLL_CPU_CORE_PLL_DIV_PDIV_SHIFT 10
-#define BCHP_CLKGEN_PLL_CPU_CORE_PLL_DIV_PDIV_DEFAULT 0x00000003
-
-/* CLKGEN :: PLL_CPU_CORE_PLL_DIV :: NDIV_INT [09:00] */
-#define BCHP_CLKGEN_PLL_CPU_CORE_PLL_DIV_NDIV_INT_MASK 0x000003ff
-#define BCHP_CLKGEN_PLL_CPU_CORE_PLL_DIV_NDIV_INT_SHIFT 0
-#define BCHP_CLKGEN_PLL_CPU_CORE_PLL_DIV_NDIV_INT_DEFAULT 0x000000a7
-
-/***************************************************************************
- *PLL_CPU_CORE_PLL_FRAC - Fractional
- ***************************************************************************/
-/* CLKGEN :: PLL_CPU_CORE_PLL_FRAC :: reserved0 [31:20] */
-#define BCHP_CLKGEN_PLL_CPU_CORE_PLL_FRAC_reserved0_MASK 0xfff00000
-#define BCHP_CLKGEN_PLL_CPU_CORE_PLL_FRAC_reserved0_SHIFT 20
-
-/* CLKGEN :: PLL_CPU_CORE_PLL_FRAC :: FRAC_CONTROL [19:00] */
-#define BCHP_CLKGEN_PLL_CPU_CORE_PLL_FRAC_FRAC_CONTROL_MASK 0x000fffff
-#define BCHP_CLKGEN_PLL_CPU_CORE_PLL_FRAC_FRAC_CONTROL_SHIFT 0
-#define BCHP_CLKGEN_PLL_CPU_CORE_PLL_FRAC_FRAC_CONTROL_DEFAULT 0x00000000
-
-/***************************************************************************
- *PLL_CPU_CORE_PLL_GAIN - PLL GAIN
- ***************************************************************************/
-/* CLKGEN :: PLL_CPU_CORE_PLL_GAIN :: reserved0 [31:10] */
-#define BCHP_CLKGEN_PLL_CPU_CORE_PLL_GAIN_reserved0_MASK 0xfffffc00
-#define BCHP_CLKGEN_PLL_CPU_CORE_PLL_GAIN_reserved0_SHIFT 10
-
-/* CLKGEN :: PLL_CPU_CORE_PLL_GAIN :: LOOP_GAIN_PROPORTIONAL_IN_PHASE [09:06] */
-#define BCHP_CLKGEN_PLL_CPU_CORE_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_MASK 0x000003c0
-#define BCHP_CLKGEN_PLL_CPU_CORE_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_SHIFT 6
-#define BCHP_CLKGEN_PLL_CPU_CORE_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_DEFAULT 0x00000005
-
-/* CLKGEN :: PLL_CPU_CORE_PLL_GAIN :: LOOP_GAIN_IN_FREQ [05:03] */
-#define BCHP_CLKGEN_PLL_CPU_CORE_PLL_GAIN_LOOP_GAIN_IN_FREQ_MASK 0x00000038
-#define BCHP_CLKGEN_PLL_CPU_CORE_PLL_GAIN_LOOP_GAIN_IN_FREQ_SHIFT 3
-#define BCHP_CLKGEN_PLL_CPU_CORE_PLL_GAIN_LOOP_GAIN_IN_FREQ_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_CPU_CORE_PLL_GAIN :: LOOP_GAIN_INTEGRATOR_IN_PHASE [02:00] */
-#define BCHP_CLKGEN_PLL_CPU_CORE_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_MASK 0x00000007
-#define BCHP_CLKGEN_PLL_CPU_CORE_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_SHIFT 0
-#define BCHP_CLKGEN_PLL_CPU_CORE_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_DEFAULT 0x00000002
-
-/***************************************************************************
- *PLL_CPU_CORE_PLL_LDO_PWRON - LDO Power on
- ***************************************************************************/
-/* CLKGEN :: PLL_CPU_CORE_PLL_LDO_PWRON :: reserved0 [31:01] */
-#define BCHP_CLKGEN_PLL_CPU_CORE_PLL_LDO_PWRON_reserved0_MASK 0xfffffffe
-#define BCHP_CLKGEN_PLL_CPU_CORE_PLL_LDO_PWRON_reserved0_SHIFT 1
-
-/* CLKGEN :: PLL_CPU_CORE_PLL_LDO_PWRON :: LDO_PWRON_PLL [00:00] */
-#define BCHP_CLKGEN_PLL_CPU_CORE_PLL_LDO_PWRON_LDO_PWRON_PLL_MASK 0x00000001
-#define BCHP_CLKGEN_PLL_CPU_CORE_PLL_LDO_PWRON_LDO_PWRON_PLL_SHIFT 0
-#define BCHP_CLKGEN_PLL_CPU_CORE_PLL_LDO_PWRON_LDO_PWRON_PLL_DEFAULT 0x00000001
-
-/***************************************************************************
- *PLL_CPU_CORE_PLL_LOCK_STATUS - Lock Status
- ***************************************************************************/
-/* CLKGEN :: PLL_CPU_CORE_PLL_LOCK_STATUS :: reserved0 [31:02] */
-#define BCHP_CLKGEN_PLL_CPU_CORE_PLL_LOCK_STATUS_reserved0_MASK 0xfffffffc
-#define BCHP_CLKGEN_PLL_CPU_CORE_PLL_LOCK_STATUS_reserved0_SHIFT 2
-
-/* CLKGEN :: PLL_CPU_CORE_PLL_LOCK_STATUS :: LOCK_LOST [01:01] */
-#define BCHP_CLKGEN_PLL_CPU_CORE_PLL_LOCK_STATUS_LOCK_LOST_MASK 0x00000002
-#define BCHP_CLKGEN_PLL_CPU_CORE_PLL_LOCK_STATUS_LOCK_LOST_SHIFT 1
-
-/* CLKGEN :: PLL_CPU_CORE_PLL_LOCK_STATUS :: LOCK [00:00] */
-#define BCHP_CLKGEN_PLL_CPU_CORE_PLL_LOCK_STATUS_LOCK_MASK 0x00000001
-#define BCHP_CLKGEN_PLL_CPU_CORE_PLL_LOCK_STATUS_LOCK_SHIFT 0
-
-/***************************************************************************
- *PLL_CPU_CORE_PLL_MISC - Mscellaneous control bus.
- ***************************************************************************/
-/* CLKGEN :: PLL_CPU_CORE_PLL_MISC :: VCO_RANGE [31:30] */
-#define BCHP_CLKGEN_PLL_CPU_CORE_PLL_MISC_VCO_RANGE_MASK 0xc0000000
-#define BCHP_CLKGEN_PLL_CPU_CORE_PLL_MISC_VCO_RANGE_SHIFT 30
-#define BCHP_CLKGEN_PLL_CPU_CORE_PLL_MISC_VCO_RANGE_DEFAULT 0x00000002
-
-/* CLKGEN :: PLL_CPU_CORE_PLL_MISC :: VCO_FB_DIV2 [29:29] */
-#define BCHP_CLKGEN_PLL_CPU_CORE_PLL_MISC_VCO_FB_DIV2_MASK 0x20000000
-#define BCHP_CLKGEN_PLL_CPU_CORE_PLL_MISC_VCO_FB_DIV2_SHIFT 29
-#define BCHP_CLKGEN_PLL_CPU_CORE_PLL_MISC_VCO_FB_DIV2_DEFAULT 0x00000001
-
-/* CLKGEN :: PLL_CPU_CORE_PLL_MISC :: STAT_UPDATE [28:28] */
-#define BCHP_CLKGEN_PLL_CPU_CORE_PLL_MISC_STAT_UPDATE_MASK 0x10000000
-#define BCHP_CLKGEN_PLL_CPU_CORE_PLL_MISC_STAT_UPDATE_SHIFT 28
-#define BCHP_CLKGEN_PLL_CPU_CORE_PLL_MISC_STAT_UPDATE_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_CPU_CORE_PLL_MISC :: STAT_SELECT [27:25] */
-#define BCHP_CLKGEN_PLL_CPU_CORE_PLL_MISC_STAT_SELECT_MASK 0x0e000000
-#define BCHP_CLKGEN_PLL_CPU_CORE_PLL_MISC_STAT_SELECT_SHIFT 25
-#define BCHP_CLKGEN_PLL_CPU_CORE_PLL_MISC_STAT_SELECT_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_CPU_CORE_PLL_MISC :: STAT_RESET [24:24] */
-#define BCHP_CLKGEN_PLL_CPU_CORE_PLL_MISC_STAT_RESET_MASK 0x01000000
-#define BCHP_CLKGEN_PLL_CPU_CORE_PLL_MISC_STAT_RESET_SHIFT 24
-#define BCHP_CLKGEN_PLL_CPU_CORE_PLL_MISC_STAT_RESET_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_CPU_CORE_PLL_MISC :: STAT_MODE [23:22] */
-#define BCHP_CLKGEN_PLL_CPU_CORE_PLL_MISC_STAT_MODE_MASK 0x00c00000
-#define BCHP_CLKGEN_PLL_CPU_CORE_PLL_MISC_STAT_MODE_SHIFT 22
-#define BCHP_CLKGEN_PLL_CPU_CORE_PLL_MISC_STAT_MODE_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_CPU_CORE_PLL_MISC :: PWM_RATE [21:20] */
-#define BCHP_CLKGEN_PLL_CPU_CORE_PLL_MISC_PWM_RATE_MASK 0x00300000
-#define BCHP_CLKGEN_PLL_CPU_CORE_PLL_MISC_PWM_RATE_SHIFT 20
-#define BCHP_CLKGEN_PLL_CPU_CORE_PLL_MISC_PWM_RATE_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_CPU_CORE_PLL_MISC :: POST_CTRL_RESETB [19:18] */
-#define BCHP_CLKGEN_PLL_CPU_CORE_PLL_MISC_POST_CTRL_RESETB_MASK 0x000c0000
-#define BCHP_CLKGEN_PLL_CPU_CORE_PLL_MISC_POST_CTRL_RESETB_SHIFT 18
-#define BCHP_CLKGEN_PLL_CPU_CORE_PLL_MISC_POST_CTRL_RESETB_DEFAULT 0x00000003
-
-/* CLKGEN :: PLL_CPU_CORE_PLL_MISC :: PLLRESERVED2 [17:16] */
-#define BCHP_CLKGEN_PLL_CPU_CORE_PLL_MISC_PLLRESERVED2_MASK 0x00030000
-#define BCHP_CLKGEN_PLL_CPU_CORE_PLL_MISC_PLLRESERVED2_SHIFT 16
-#define BCHP_CLKGEN_PLL_CPU_CORE_PLL_MISC_PLLRESERVED2_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_CPU_CORE_PLL_MISC :: PLLRESERVED1 [15:15] */
-#define BCHP_CLKGEN_PLL_CPU_CORE_PLL_MISC_PLLRESERVED1_MASK 0x00008000
-#define BCHP_CLKGEN_PLL_CPU_CORE_PLL_MISC_PLLRESERVED1_SHIFT 15
-#define BCHP_CLKGEN_PLL_CPU_CORE_PLL_MISC_PLLRESERVED1_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_CPU_CORE_PLL_MISC :: NDIV_RELOCK [14:14] */
-#define BCHP_CLKGEN_PLL_CPU_CORE_PLL_MISC_NDIV_RELOCK_MASK 0x00004000
-#define BCHP_CLKGEN_PLL_CPU_CORE_PLL_MISC_NDIV_RELOCK_SHIFT 14
-#define BCHP_CLKGEN_PLL_CPU_CORE_PLL_MISC_NDIV_RELOCK_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_CPU_CORE_PLL_MISC :: FAST_LOCK [13:13] */
-#define BCHP_CLKGEN_PLL_CPU_CORE_PLL_MISC_FAST_LOCK_MASK 0x00002000
-#define BCHP_CLKGEN_PLL_CPU_CORE_PLL_MISC_FAST_LOCK_SHIFT 13
-#define BCHP_CLKGEN_PLL_CPU_CORE_PLL_MISC_FAST_LOCK_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_CPU_CORE_PLL_MISC :: DCO_CTRL_BYPASS_ENABLE [12:12] */
-#define BCHP_CLKGEN_PLL_CPU_CORE_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_MASK 0x00001000
-#define BCHP_CLKGEN_PLL_CPU_CORE_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_SHIFT 12
-#define BCHP_CLKGEN_PLL_CPU_CORE_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_CPU_CORE_PLL_MISC :: DCO_CTRL_BYPASS [11:00] */
-#define BCHP_CLKGEN_PLL_CPU_CORE_PLL_MISC_DCO_CTRL_BYPASS_MASK 0x00000fff
-#define BCHP_CLKGEN_PLL_CPU_CORE_PLL_MISC_DCO_CTRL_BYPASS_SHIFT 0
-#define BCHP_CLKGEN_PLL_CPU_CORE_PLL_MISC_DCO_CTRL_BYPASS_DEFAULT 0x00000000
-
-/***************************************************************************
- *PLL_CPU_CORE_PLL_MISC2 - Mscellaneous control bus continued.
- ***************************************************************************/
-/* CLKGEN :: PLL_CPU_CORE_PLL_MISC2 :: PLLRESERVED0 [31:02] */
-#define BCHP_CLKGEN_PLL_CPU_CORE_PLL_MISC2_PLLRESERVED0_MASK 0xfffffffc
-#define BCHP_CLKGEN_PLL_CPU_CORE_PLL_MISC2_PLLRESERVED0_SHIFT 2
-#define BCHP_CLKGEN_PLL_CPU_CORE_PLL_MISC2_PLLRESERVED0_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_CPU_CORE_PLL_MISC2 :: LDO [01:00] */
-#define BCHP_CLKGEN_PLL_CPU_CORE_PLL_MISC2_LDO_MASK 0x00000003
-#define BCHP_CLKGEN_PLL_CPU_CORE_PLL_MISC2_LDO_SHIFT 0
-#define BCHP_CLKGEN_PLL_CPU_CORE_PLL_MISC2_LDO_DEFAULT 0x00000001
-
-/***************************************************************************
- *PLL_CPU_CORE_PLL_PWRON - Poweron
- ***************************************************************************/
-/* CLKGEN :: PLL_CPU_CORE_PLL_PWRON :: reserved0 [31:01] */
-#define BCHP_CLKGEN_PLL_CPU_CORE_PLL_PWRON_reserved0_MASK 0xfffffffe
-#define BCHP_CLKGEN_PLL_CPU_CORE_PLL_PWRON_reserved0_SHIFT 1
-
-/* CLKGEN :: PLL_CPU_CORE_PLL_PWRON :: PWRON_PLL [00:00] */
-#define BCHP_CLKGEN_PLL_CPU_CORE_PLL_PWRON_PWRON_PLL_MASK 0x00000001
-#define BCHP_CLKGEN_PLL_CPU_CORE_PLL_PWRON_PWRON_PLL_SHIFT 0
-#define BCHP_CLKGEN_PLL_CPU_CORE_PLL_PWRON_PWRON_PLL_DEFAULT 0x00000001
-
-/***************************************************************************
- *PLL_CPU_CORE_PLL_RESET - Resets
- ***************************************************************************/
-/* CLKGEN :: PLL_CPU_CORE_PLL_RESET :: reserved0 [31:02] */
-#define BCHP_CLKGEN_PLL_CPU_CORE_PLL_RESET_reserved0_MASK 0xfffffffc
-#define BCHP_CLKGEN_PLL_CPU_CORE_PLL_RESET_reserved0_SHIFT 2
-
-/* CLKGEN :: PLL_CPU_CORE_PLL_RESET :: RESETD [01:01] */
-#define BCHP_CLKGEN_PLL_CPU_CORE_PLL_RESET_RESETD_MASK 0x00000002
-#define BCHP_CLKGEN_PLL_CPU_CORE_PLL_RESET_RESETD_SHIFT 1
-#define BCHP_CLKGEN_PLL_CPU_CORE_PLL_RESET_RESETD_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_CPU_CORE_PLL_RESET :: RESETA [00:00] */
-#define BCHP_CLKGEN_PLL_CPU_CORE_PLL_RESET_RESETA_MASK 0x00000001
-#define BCHP_CLKGEN_PLL_CPU_CORE_PLL_RESET_RESETA_SHIFT 0
-#define BCHP_CLKGEN_PLL_CPU_CORE_PLL_RESET_RESETA_DEFAULT 0x00000000
-
-/***************************************************************************
- *PLL_CPU_CORE_PLL_SSC_MODE_CONTROL_HIGH - Higher bits of Spread Spectrum mode control
- ***************************************************************************/
-/* CLKGEN :: PLL_CPU_CORE_PLL_SSC_MODE_CONTROL_HIGH :: reserved0 [31:16] */
-#define BCHP_CLKGEN_PLL_CPU_CORE_PLL_SSC_MODE_CONTROL_HIGH_reserved0_MASK 0xffff0000
-#define BCHP_CLKGEN_PLL_CPU_CORE_PLL_SSC_MODE_CONTROL_HIGH_reserved0_SHIFT 16
-
-/* CLKGEN :: PLL_CPU_CORE_PLL_SSC_MODE_CONTROL_HIGH :: SSC_STEP [15:00] */
-#define BCHP_CLKGEN_PLL_CPU_CORE_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_MASK 0x0000ffff
-#define BCHP_CLKGEN_PLL_CPU_CORE_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_SHIFT 0
-#define BCHP_CLKGEN_PLL_CPU_CORE_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *PLL_CPU_CORE_PLL_SSC_MODE_CONTROL_LOW - Lower bits of Spread Spectrum mode control
- ***************************************************************************/
-/* CLKGEN :: PLL_CPU_CORE_PLL_SSC_MODE_CONTROL_LOW :: reserved0 [31:23] */
-#define BCHP_CLKGEN_PLL_CPU_CORE_PLL_SSC_MODE_CONTROL_LOW_reserved0_MASK 0xff800000
-#define BCHP_CLKGEN_PLL_CPU_CORE_PLL_SSC_MODE_CONTROL_LOW_reserved0_SHIFT 23
-
-/* CLKGEN :: PLL_CPU_CORE_PLL_SSC_MODE_CONTROL_LOW :: SSC_MODE [22:22] */
-#define BCHP_CLKGEN_PLL_CPU_CORE_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_MASK 0x00400000
-#define BCHP_CLKGEN_PLL_CPU_CORE_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_SHIFT 22
-#define BCHP_CLKGEN_PLL_CPU_CORE_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_CPU_CORE_PLL_SSC_MODE_CONTROL_LOW :: SSC_LIMIT [21:00] */
-#define BCHP_CLKGEN_PLL_CPU_CORE_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_MASK 0x003fffff
-#define BCHP_CLKGEN_PLL_CPU_CORE_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_SHIFT 0
-#define BCHP_CLKGEN_PLL_CPU_CORE_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_DEFAULT 0x00000000
-
-/***************************************************************************
- *PLL_CPU_CORE_PLL_STATUS - Status
- ***************************************************************************/
-/* CLKGEN :: PLL_CPU_CORE_PLL_STATUS :: reserved0 [31:12] */
-#define BCHP_CLKGEN_PLL_CPU_CORE_PLL_STATUS_reserved0_MASK 0xfffff000
-#define BCHP_CLKGEN_PLL_CPU_CORE_PLL_STATUS_reserved0_SHIFT 12
-
-/* CLKGEN :: PLL_CPU_CORE_PLL_STATUS :: TEST_STATUS [11:00] */
-#define BCHP_CLKGEN_PLL_CPU_CORE_PLL_STATUS_TEST_STATUS_MASK 0x00000fff
-#define BCHP_CLKGEN_PLL_CPU_CORE_PLL_STATUS_TEST_STATUS_SHIFT 0
-
-/***************************************************************************
- *PLL_CPU_ROUTER_PLL_CHANNEL_CTRL_CH_0 - PLL CHANNEL control CH 0
- ***************************************************************************/
-/* CLKGEN :: PLL_CPU_ROUTER_PLL_CHANNEL_CTRL_CH_0 :: reserved0 [31:11] */
-#define BCHP_CLKGEN_PLL_CPU_ROUTER_PLL_CHANNEL_CTRL_CH_0_reserved0_MASK 0xfffff800
-#define BCHP_CLKGEN_PLL_CPU_ROUTER_PLL_CHANNEL_CTRL_CH_0_reserved0_SHIFT 11
-
-/* CLKGEN :: PLL_CPU_ROUTER_PLL_CHANNEL_CTRL_CH_0 :: POST_DIVIDER_HOLD_CH0 [10:10] */
-#define BCHP_CLKGEN_PLL_CPU_ROUTER_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_MASK 0x00000400
-#define BCHP_CLKGEN_PLL_CPU_ROUTER_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_SHIFT 10
-#define BCHP_CLKGEN_PLL_CPU_ROUTER_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_CPU_ROUTER_PLL_CHANNEL_CTRL_CH_0 :: PHASE_OFFSET_CH0 [09:09] */
-#define BCHP_CLKGEN_PLL_CPU_ROUTER_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_MASK 0x00000200
-#define BCHP_CLKGEN_PLL_CPU_ROUTER_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_SHIFT 9
-#define BCHP_CLKGEN_PLL_CPU_ROUTER_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_CPU_ROUTER_PLL_CHANNEL_CTRL_CH_0 :: MDIV_CH0 [08:01] */
-#define BCHP_CLKGEN_PLL_CPU_ROUTER_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_MASK 0x000001fe
-#define BCHP_CLKGEN_PLL_CPU_ROUTER_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_SHIFT 1
-#define BCHP_CLKGEN_PLL_CPU_ROUTER_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_DEFAULT 0x00000002
-
-/* CLKGEN :: PLL_CPU_ROUTER_PLL_CHANNEL_CTRL_CH_0 :: CLOCK_DIS_CH0 [00:00] */
-#define BCHP_CLKGEN_PLL_CPU_ROUTER_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_MASK 0x00000001
-#define BCHP_CLKGEN_PLL_CPU_ROUTER_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_SHIFT 0
-#define BCHP_CLKGEN_PLL_CPU_ROUTER_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_DEFAULT 0x00000000
-
-/***************************************************************************
- *PLL_CPU_ROUTER_PLL_CHANNEL_CTRL_CH_1 - PLL CHANNEL control CH 1
- ***************************************************************************/
-/* CLKGEN :: PLL_CPU_ROUTER_PLL_CHANNEL_CTRL_CH_1 :: reserved0 [31:11] */
-#define BCHP_CLKGEN_PLL_CPU_ROUTER_PLL_CHANNEL_CTRL_CH_1_reserved0_MASK 0xfffff800
-#define BCHP_CLKGEN_PLL_CPU_ROUTER_PLL_CHANNEL_CTRL_CH_1_reserved0_SHIFT 11
-
-/* CLKGEN :: PLL_CPU_ROUTER_PLL_CHANNEL_CTRL_CH_1 :: POST_DIVIDER_HOLD_CH1 [10:10] */
-#define BCHP_CLKGEN_PLL_CPU_ROUTER_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_MASK 0x00000400
-#define BCHP_CLKGEN_PLL_CPU_ROUTER_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_SHIFT 10
-#define BCHP_CLKGEN_PLL_CPU_ROUTER_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_CPU_ROUTER_PLL_CHANNEL_CTRL_CH_1 :: PHASE_OFFSET_CH1 [09:09] */
-#define BCHP_CLKGEN_PLL_CPU_ROUTER_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_MASK 0x00000200
-#define BCHP_CLKGEN_PLL_CPU_ROUTER_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_SHIFT 9
-#define BCHP_CLKGEN_PLL_CPU_ROUTER_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_CPU_ROUTER_PLL_CHANNEL_CTRL_CH_1 :: MDIV_CH1 [08:01] */
-#define BCHP_CLKGEN_PLL_CPU_ROUTER_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_MASK 0x000001fe
-#define BCHP_CLKGEN_PLL_CPU_ROUTER_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_SHIFT 1
-#define BCHP_CLKGEN_PLL_CPU_ROUTER_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_DEFAULT 0x00000064
-
-/* CLKGEN :: PLL_CPU_ROUTER_PLL_CHANNEL_CTRL_CH_1 :: CLOCK_DIS_CH1 [00:00] */
-#define BCHP_CLKGEN_PLL_CPU_ROUTER_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_MASK 0x00000001
-#define BCHP_CLKGEN_PLL_CPU_ROUTER_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_SHIFT 0
-#define BCHP_CLKGEN_PLL_CPU_ROUTER_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_DEFAULT 0x00000001
-
-/***************************************************************************
- *PLL_CPU_ROUTER_PLL_DIV - Pre multiplier
- ***************************************************************************/
-/* CLKGEN :: PLL_CPU_ROUTER_PLL_DIV :: reserved0 [31:14] */
-#define BCHP_CLKGEN_PLL_CPU_ROUTER_PLL_DIV_reserved0_MASK 0xffffc000
-#define BCHP_CLKGEN_PLL_CPU_ROUTER_PLL_DIV_reserved0_SHIFT 14
-
-/* CLKGEN :: PLL_CPU_ROUTER_PLL_DIV :: PDIV [13:10] */
-#define BCHP_CLKGEN_PLL_CPU_ROUTER_PLL_DIV_PDIV_MASK 0x00003c00
-#define BCHP_CLKGEN_PLL_CPU_ROUTER_PLL_DIV_PDIV_SHIFT 10
-#define BCHP_CLKGEN_PLL_CPU_ROUTER_PLL_DIV_PDIV_DEFAULT 0x00000003
-
-/* CLKGEN :: PLL_CPU_ROUTER_PLL_DIV :: NDIV_INT [09:00] */
-#define BCHP_CLKGEN_PLL_CPU_ROUTER_PLL_DIV_NDIV_INT_MASK 0x000003ff
-#define BCHP_CLKGEN_PLL_CPU_ROUTER_PLL_DIV_NDIV_INT_SHIFT 0
-#define BCHP_CLKGEN_PLL_CPU_ROUTER_PLL_DIV_NDIV_INT_DEFAULT 0x000000a7
-
-/***************************************************************************
- *PLL_CPU_ROUTER_PLL_FRAC - Fractional
- ***************************************************************************/
-/* CLKGEN :: PLL_CPU_ROUTER_PLL_FRAC :: reserved0 [31:20] */
-#define BCHP_CLKGEN_PLL_CPU_ROUTER_PLL_FRAC_reserved0_MASK 0xfff00000
-#define BCHP_CLKGEN_PLL_CPU_ROUTER_PLL_FRAC_reserved0_SHIFT 20
-
-/* CLKGEN :: PLL_CPU_ROUTER_PLL_FRAC :: FRAC_CONTROL [19:00] */
-#define BCHP_CLKGEN_PLL_CPU_ROUTER_PLL_FRAC_FRAC_CONTROL_MASK 0x000fffff
-#define BCHP_CLKGEN_PLL_CPU_ROUTER_PLL_FRAC_FRAC_CONTROL_SHIFT 0
-#define BCHP_CLKGEN_PLL_CPU_ROUTER_PLL_FRAC_FRAC_CONTROL_DEFAULT 0x00000000
-
-/***************************************************************************
- *PLL_CPU_ROUTER_PLL_GAIN - PLL GAIN
- ***************************************************************************/
-/* CLKGEN :: PLL_CPU_ROUTER_PLL_GAIN :: reserved0 [31:10] */
-#define BCHP_CLKGEN_PLL_CPU_ROUTER_PLL_GAIN_reserved0_MASK 0xfffffc00
-#define BCHP_CLKGEN_PLL_CPU_ROUTER_PLL_GAIN_reserved0_SHIFT 10
-
-/* CLKGEN :: PLL_CPU_ROUTER_PLL_GAIN :: LOOP_GAIN_PROPORTIONAL_IN_PHASE [09:06] */
-#define BCHP_CLKGEN_PLL_CPU_ROUTER_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_MASK 0x000003c0
-#define BCHP_CLKGEN_PLL_CPU_ROUTER_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_SHIFT 6
-#define BCHP_CLKGEN_PLL_CPU_ROUTER_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_DEFAULT 0x00000005
-
-/* CLKGEN :: PLL_CPU_ROUTER_PLL_GAIN :: LOOP_GAIN_IN_FREQ [05:03] */
-#define BCHP_CLKGEN_PLL_CPU_ROUTER_PLL_GAIN_LOOP_GAIN_IN_FREQ_MASK 0x00000038
-#define BCHP_CLKGEN_PLL_CPU_ROUTER_PLL_GAIN_LOOP_GAIN_IN_FREQ_SHIFT 3
-#define BCHP_CLKGEN_PLL_CPU_ROUTER_PLL_GAIN_LOOP_GAIN_IN_FREQ_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_CPU_ROUTER_PLL_GAIN :: LOOP_GAIN_INTEGRATOR_IN_PHASE [02:00] */
-#define BCHP_CLKGEN_PLL_CPU_ROUTER_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_MASK 0x00000007
-#define BCHP_CLKGEN_PLL_CPU_ROUTER_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_SHIFT 0
-#define BCHP_CLKGEN_PLL_CPU_ROUTER_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_DEFAULT 0x00000002
-
-/***************************************************************************
- *PLL_CPU_ROUTER_PLL_LDO_PWRON - LDO Power on
- ***************************************************************************/
-/* CLKGEN :: PLL_CPU_ROUTER_PLL_LDO_PWRON :: reserved0 [31:01] */
-#define BCHP_CLKGEN_PLL_CPU_ROUTER_PLL_LDO_PWRON_reserved0_MASK 0xfffffffe
-#define BCHP_CLKGEN_PLL_CPU_ROUTER_PLL_LDO_PWRON_reserved0_SHIFT 1
-
-/* CLKGEN :: PLL_CPU_ROUTER_PLL_LDO_PWRON :: LDO_PWRON_PLL [00:00] */
-#define BCHP_CLKGEN_PLL_CPU_ROUTER_PLL_LDO_PWRON_LDO_PWRON_PLL_MASK 0x00000001
-#define BCHP_CLKGEN_PLL_CPU_ROUTER_PLL_LDO_PWRON_LDO_PWRON_PLL_SHIFT 0
-#define BCHP_CLKGEN_PLL_CPU_ROUTER_PLL_LDO_PWRON_LDO_PWRON_PLL_DEFAULT 0x00000001
-
-/***************************************************************************
- *PLL_CPU_ROUTER_PLL_LOCK_STATUS - Lock Status
- ***************************************************************************/
-/* CLKGEN :: PLL_CPU_ROUTER_PLL_LOCK_STATUS :: reserved0 [31:02] */
-#define BCHP_CLKGEN_PLL_CPU_ROUTER_PLL_LOCK_STATUS_reserved0_MASK 0xfffffffc
-#define BCHP_CLKGEN_PLL_CPU_ROUTER_PLL_LOCK_STATUS_reserved0_SHIFT 2
-
-/* CLKGEN :: PLL_CPU_ROUTER_PLL_LOCK_STATUS :: LOCK_LOST [01:01] */
-#define BCHP_CLKGEN_PLL_CPU_ROUTER_PLL_LOCK_STATUS_LOCK_LOST_MASK 0x00000002
-#define BCHP_CLKGEN_PLL_CPU_ROUTER_PLL_LOCK_STATUS_LOCK_LOST_SHIFT 1
-
-/* CLKGEN :: PLL_CPU_ROUTER_PLL_LOCK_STATUS :: LOCK [00:00] */
-#define BCHP_CLKGEN_PLL_CPU_ROUTER_PLL_LOCK_STATUS_LOCK_MASK 0x00000001
-#define BCHP_CLKGEN_PLL_CPU_ROUTER_PLL_LOCK_STATUS_LOCK_SHIFT 0
-
-/***************************************************************************
- *PLL_CPU_ROUTER_PLL_MISC - Mscellaneous control bus.
- ***************************************************************************/
-/* CLKGEN :: PLL_CPU_ROUTER_PLL_MISC :: VCO_RANGE [31:30] */
-#define BCHP_CLKGEN_PLL_CPU_ROUTER_PLL_MISC_VCO_RANGE_MASK 0xc0000000
-#define BCHP_CLKGEN_PLL_CPU_ROUTER_PLL_MISC_VCO_RANGE_SHIFT 30
-#define BCHP_CLKGEN_PLL_CPU_ROUTER_PLL_MISC_VCO_RANGE_DEFAULT 0x00000002
-
-/* CLKGEN :: PLL_CPU_ROUTER_PLL_MISC :: VCO_FB_DIV2 [29:29] */
-#define BCHP_CLKGEN_PLL_CPU_ROUTER_PLL_MISC_VCO_FB_DIV2_MASK 0x20000000
-#define BCHP_CLKGEN_PLL_CPU_ROUTER_PLL_MISC_VCO_FB_DIV2_SHIFT 29
-#define BCHP_CLKGEN_PLL_CPU_ROUTER_PLL_MISC_VCO_FB_DIV2_DEFAULT 0x00000001
-
-/* CLKGEN :: PLL_CPU_ROUTER_PLL_MISC :: STAT_UPDATE [28:28] */
-#define BCHP_CLKGEN_PLL_CPU_ROUTER_PLL_MISC_STAT_UPDATE_MASK 0x10000000
-#define BCHP_CLKGEN_PLL_CPU_ROUTER_PLL_MISC_STAT_UPDATE_SHIFT 28
-#define BCHP_CLKGEN_PLL_CPU_ROUTER_PLL_MISC_STAT_UPDATE_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_CPU_ROUTER_PLL_MISC :: STAT_SELECT [27:25] */
-#define BCHP_CLKGEN_PLL_CPU_ROUTER_PLL_MISC_STAT_SELECT_MASK 0x0e000000
-#define BCHP_CLKGEN_PLL_CPU_ROUTER_PLL_MISC_STAT_SELECT_SHIFT 25
-#define BCHP_CLKGEN_PLL_CPU_ROUTER_PLL_MISC_STAT_SELECT_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_CPU_ROUTER_PLL_MISC :: STAT_RESET [24:24] */
-#define BCHP_CLKGEN_PLL_CPU_ROUTER_PLL_MISC_STAT_RESET_MASK 0x01000000
-#define BCHP_CLKGEN_PLL_CPU_ROUTER_PLL_MISC_STAT_RESET_SHIFT 24
-#define BCHP_CLKGEN_PLL_CPU_ROUTER_PLL_MISC_STAT_RESET_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_CPU_ROUTER_PLL_MISC :: STAT_MODE [23:22] */
-#define BCHP_CLKGEN_PLL_CPU_ROUTER_PLL_MISC_STAT_MODE_MASK 0x00c00000
-#define BCHP_CLKGEN_PLL_CPU_ROUTER_PLL_MISC_STAT_MODE_SHIFT 22
-#define BCHP_CLKGEN_PLL_CPU_ROUTER_PLL_MISC_STAT_MODE_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_CPU_ROUTER_PLL_MISC :: PWM_RATE [21:20] */
-#define BCHP_CLKGEN_PLL_CPU_ROUTER_PLL_MISC_PWM_RATE_MASK 0x00300000
-#define BCHP_CLKGEN_PLL_CPU_ROUTER_PLL_MISC_PWM_RATE_SHIFT 20
-#define BCHP_CLKGEN_PLL_CPU_ROUTER_PLL_MISC_PWM_RATE_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_CPU_ROUTER_PLL_MISC :: POST_CTRL_RESETB [19:18] */
-#define BCHP_CLKGEN_PLL_CPU_ROUTER_PLL_MISC_POST_CTRL_RESETB_MASK 0x000c0000
-#define BCHP_CLKGEN_PLL_CPU_ROUTER_PLL_MISC_POST_CTRL_RESETB_SHIFT 18
-#define BCHP_CLKGEN_PLL_CPU_ROUTER_PLL_MISC_POST_CTRL_RESETB_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_CPU_ROUTER_PLL_MISC :: PLLRESERVED2 [17:16] */
-#define BCHP_CLKGEN_PLL_CPU_ROUTER_PLL_MISC_PLLRESERVED2_MASK 0x00030000
-#define BCHP_CLKGEN_PLL_CPU_ROUTER_PLL_MISC_PLLRESERVED2_SHIFT 16
-#define BCHP_CLKGEN_PLL_CPU_ROUTER_PLL_MISC_PLLRESERVED2_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_CPU_ROUTER_PLL_MISC :: PLLRESERVED1 [15:15] */
-#define BCHP_CLKGEN_PLL_CPU_ROUTER_PLL_MISC_PLLRESERVED1_MASK 0x00008000
-#define BCHP_CLKGEN_PLL_CPU_ROUTER_PLL_MISC_PLLRESERVED1_SHIFT 15
-#define BCHP_CLKGEN_PLL_CPU_ROUTER_PLL_MISC_PLLRESERVED1_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_CPU_ROUTER_PLL_MISC :: NDIV_RELOCK [14:14] */
-#define BCHP_CLKGEN_PLL_CPU_ROUTER_PLL_MISC_NDIV_RELOCK_MASK 0x00004000
-#define BCHP_CLKGEN_PLL_CPU_ROUTER_PLL_MISC_NDIV_RELOCK_SHIFT 14
-#define BCHP_CLKGEN_PLL_CPU_ROUTER_PLL_MISC_NDIV_RELOCK_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_CPU_ROUTER_PLL_MISC :: FAST_LOCK [13:13] */
-#define BCHP_CLKGEN_PLL_CPU_ROUTER_PLL_MISC_FAST_LOCK_MASK 0x00002000
-#define BCHP_CLKGEN_PLL_CPU_ROUTER_PLL_MISC_FAST_LOCK_SHIFT 13
-#define BCHP_CLKGEN_PLL_CPU_ROUTER_PLL_MISC_FAST_LOCK_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_CPU_ROUTER_PLL_MISC :: DCO_CTRL_BYPASS_ENABLE [12:12] */
-#define BCHP_CLKGEN_PLL_CPU_ROUTER_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_MASK 0x00001000
-#define BCHP_CLKGEN_PLL_CPU_ROUTER_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_SHIFT 12
-#define BCHP_CLKGEN_PLL_CPU_ROUTER_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_CPU_ROUTER_PLL_MISC :: DCO_CTRL_BYPASS [11:00] */
-#define BCHP_CLKGEN_PLL_CPU_ROUTER_PLL_MISC_DCO_CTRL_BYPASS_MASK 0x00000fff
-#define BCHP_CLKGEN_PLL_CPU_ROUTER_PLL_MISC_DCO_CTRL_BYPASS_SHIFT 0
-#define BCHP_CLKGEN_PLL_CPU_ROUTER_PLL_MISC_DCO_CTRL_BYPASS_DEFAULT 0x00000000
-
-/***************************************************************************
- *PLL_CPU_ROUTER_PLL_MISC2 - Mscellaneous control bus continued.
- ***************************************************************************/
-/* CLKGEN :: PLL_CPU_ROUTER_PLL_MISC2 :: PLLRESERVED0 [31:02] */
-#define BCHP_CLKGEN_PLL_CPU_ROUTER_PLL_MISC2_PLLRESERVED0_MASK 0xfffffffc
-#define BCHP_CLKGEN_PLL_CPU_ROUTER_PLL_MISC2_PLLRESERVED0_SHIFT 2
-#define BCHP_CLKGEN_PLL_CPU_ROUTER_PLL_MISC2_PLLRESERVED0_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_CPU_ROUTER_PLL_MISC2 :: LDO [01:00] */
-#define BCHP_CLKGEN_PLL_CPU_ROUTER_PLL_MISC2_LDO_MASK 0x00000003
-#define BCHP_CLKGEN_PLL_CPU_ROUTER_PLL_MISC2_LDO_SHIFT 0
-#define BCHP_CLKGEN_PLL_CPU_ROUTER_PLL_MISC2_LDO_DEFAULT 0x00000001
-
-/***************************************************************************
- *PLL_CPU_ROUTER_PLL_PWRON - Poweron
- ***************************************************************************/
-/* CLKGEN :: PLL_CPU_ROUTER_PLL_PWRON :: reserved0 [31:01] */
-#define BCHP_CLKGEN_PLL_CPU_ROUTER_PLL_PWRON_reserved0_MASK 0xfffffffe
-#define BCHP_CLKGEN_PLL_CPU_ROUTER_PLL_PWRON_reserved0_SHIFT 1
-
-/* CLKGEN :: PLL_CPU_ROUTER_PLL_PWRON :: PWRON_PLL [00:00] */
-#define BCHP_CLKGEN_PLL_CPU_ROUTER_PLL_PWRON_PWRON_PLL_MASK 0x00000001
-#define BCHP_CLKGEN_PLL_CPU_ROUTER_PLL_PWRON_PWRON_PLL_SHIFT 0
-#define BCHP_CLKGEN_PLL_CPU_ROUTER_PLL_PWRON_PWRON_PLL_DEFAULT 0x00000001
-
-/***************************************************************************
- *PLL_CPU_ROUTER_PLL_RESET - Resets
- ***************************************************************************/
-/* CLKGEN :: PLL_CPU_ROUTER_PLL_RESET :: reserved0 [31:02] */
-#define BCHP_CLKGEN_PLL_CPU_ROUTER_PLL_RESET_reserved0_MASK 0xfffffffc
-#define BCHP_CLKGEN_PLL_CPU_ROUTER_PLL_RESET_reserved0_SHIFT 2
-
-/* CLKGEN :: PLL_CPU_ROUTER_PLL_RESET :: RESETD [01:01] */
-#define BCHP_CLKGEN_PLL_CPU_ROUTER_PLL_RESET_RESETD_MASK 0x00000002
-#define BCHP_CLKGEN_PLL_CPU_ROUTER_PLL_RESET_RESETD_SHIFT 1
-#define BCHP_CLKGEN_PLL_CPU_ROUTER_PLL_RESET_RESETD_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_CPU_ROUTER_PLL_RESET :: RESETA [00:00] */
-#define BCHP_CLKGEN_PLL_CPU_ROUTER_PLL_RESET_RESETA_MASK 0x00000001
-#define BCHP_CLKGEN_PLL_CPU_ROUTER_PLL_RESET_RESETA_SHIFT 0
-#define BCHP_CLKGEN_PLL_CPU_ROUTER_PLL_RESET_RESETA_DEFAULT 0x00000000
-
-/***************************************************************************
- *PLL_CPU_ROUTER_PLL_SSC_MODE_CONTROL_HIGH - Higher bits of Spread Spectrum mode control
- ***************************************************************************/
-/* CLKGEN :: PLL_CPU_ROUTER_PLL_SSC_MODE_CONTROL_HIGH :: reserved0 [31:16] */
-#define BCHP_CLKGEN_PLL_CPU_ROUTER_PLL_SSC_MODE_CONTROL_HIGH_reserved0_MASK 0xffff0000
-#define BCHP_CLKGEN_PLL_CPU_ROUTER_PLL_SSC_MODE_CONTROL_HIGH_reserved0_SHIFT 16
-
-/* CLKGEN :: PLL_CPU_ROUTER_PLL_SSC_MODE_CONTROL_HIGH :: SSC_STEP [15:00] */
-#define BCHP_CLKGEN_PLL_CPU_ROUTER_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_MASK 0x0000ffff
-#define BCHP_CLKGEN_PLL_CPU_ROUTER_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_SHIFT 0
-#define BCHP_CLKGEN_PLL_CPU_ROUTER_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *PLL_CPU_ROUTER_PLL_SSC_MODE_CONTROL_LOW - Lower bits of Spread Spectrum mode control
- ***************************************************************************/
-/* CLKGEN :: PLL_CPU_ROUTER_PLL_SSC_MODE_CONTROL_LOW :: reserved0 [31:23] */
-#define BCHP_CLKGEN_PLL_CPU_ROUTER_PLL_SSC_MODE_CONTROL_LOW_reserved0_MASK 0xff800000
-#define BCHP_CLKGEN_PLL_CPU_ROUTER_PLL_SSC_MODE_CONTROL_LOW_reserved0_SHIFT 23
-
-/* CLKGEN :: PLL_CPU_ROUTER_PLL_SSC_MODE_CONTROL_LOW :: SSC_MODE [22:22] */
-#define BCHP_CLKGEN_PLL_CPU_ROUTER_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_MASK 0x00400000
-#define BCHP_CLKGEN_PLL_CPU_ROUTER_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_SHIFT 22
-#define BCHP_CLKGEN_PLL_CPU_ROUTER_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_CPU_ROUTER_PLL_SSC_MODE_CONTROL_LOW :: SSC_LIMIT [21:00] */
-#define BCHP_CLKGEN_PLL_CPU_ROUTER_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_MASK 0x003fffff
-#define BCHP_CLKGEN_PLL_CPU_ROUTER_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_SHIFT 0
-#define BCHP_CLKGEN_PLL_CPU_ROUTER_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_DEFAULT 0x00000000
-
-/***************************************************************************
- *PLL_CPU_ROUTER_PLL_STATUS - Status
- ***************************************************************************/
-/* CLKGEN :: PLL_CPU_ROUTER_PLL_STATUS :: reserved0 [31:12] */
-#define BCHP_CLKGEN_PLL_CPU_ROUTER_PLL_STATUS_reserved0_MASK 0xfffff000
-#define BCHP_CLKGEN_PLL_CPU_ROUTER_PLL_STATUS_reserved0_SHIFT 12
-
-/* CLKGEN :: PLL_CPU_ROUTER_PLL_STATUS :: TEST_STATUS [11:00] */
-#define BCHP_CLKGEN_PLL_CPU_ROUTER_PLL_STATUS_TEST_STATUS_MASK 0x00000fff
-#define BCHP_CLKGEN_PLL_CPU_ROUTER_PLL_STATUS_TEST_STATUS_SHIFT 0
-
-/***************************************************************************
- *PLL_LC_PLL_CHANNEL_CTRL_CH_0 - PLL CHANNEL control CH 0
- ***************************************************************************/
-/* CLKGEN :: PLL_LC_PLL_CHANNEL_CTRL_CH_0 :: reserved0 [31:11] */
-#define BCHP_CLKGEN_PLL_LC_PLL_CHANNEL_CTRL_CH_0_reserved0_MASK 0xfffff800
-#define BCHP_CLKGEN_PLL_LC_PLL_CHANNEL_CTRL_CH_0_reserved0_SHIFT 11
-
-/* CLKGEN :: PLL_LC_PLL_CHANNEL_CTRL_CH_0 :: POST_DIVIDER_HOLD_CH0 [10:10] */
-#define BCHP_CLKGEN_PLL_LC_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_MASK 0x00000400
-#define BCHP_CLKGEN_PLL_LC_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_SHIFT 10
-#define BCHP_CLKGEN_PLL_LC_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_LC_PLL_CHANNEL_CTRL_CH_0 :: PHASE_OFFSET_CH0 [09:09] */
-#define BCHP_CLKGEN_PLL_LC_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_MASK 0x00000200
-#define BCHP_CLKGEN_PLL_LC_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_SHIFT 9
-#define BCHP_CLKGEN_PLL_LC_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_LC_PLL_CHANNEL_CTRL_CH_0 :: MDIV_CH0 [08:01] */
-#define BCHP_CLKGEN_PLL_LC_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_MASK 0x000001fe
-#define BCHP_CLKGEN_PLL_LC_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_SHIFT 1
-#define BCHP_CLKGEN_PLL_LC_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_DEFAULT 0x0000006c
-
-/* CLKGEN :: PLL_LC_PLL_CHANNEL_CTRL_CH_0 :: CLOCK_DIS_CH0 [00:00] */
-#define BCHP_CLKGEN_PLL_LC_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_MASK 0x00000001
-#define BCHP_CLKGEN_PLL_LC_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_SHIFT 0
-#define BCHP_CLKGEN_PLL_LC_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_DEFAULT 0x00000000
-
-/***************************************************************************
- *PLL_LC_PLL_CHANNEL_CTRL_CH_1 - PLL CHANNEL control CH 1
- ***************************************************************************/
-/* CLKGEN :: PLL_LC_PLL_CHANNEL_CTRL_CH_1 :: reserved0 [31:11] */
-#define BCHP_CLKGEN_PLL_LC_PLL_CHANNEL_CTRL_CH_1_reserved0_MASK 0xfffff800
-#define BCHP_CLKGEN_PLL_LC_PLL_CHANNEL_CTRL_CH_1_reserved0_SHIFT 11
-
-/* CLKGEN :: PLL_LC_PLL_CHANNEL_CTRL_CH_1 :: POST_DIVIDER_HOLD_CH1 [10:10] */
-#define BCHP_CLKGEN_PLL_LC_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_MASK 0x00000400
-#define BCHP_CLKGEN_PLL_LC_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_SHIFT 10
-#define BCHP_CLKGEN_PLL_LC_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_LC_PLL_CHANNEL_CTRL_CH_1 :: PHASE_OFFSET_CH1 [09:09] */
-#define BCHP_CLKGEN_PLL_LC_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_MASK 0x00000200
-#define BCHP_CLKGEN_PLL_LC_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_SHIFT 9
-#define BCHP_CLKGEN_PLL_LC_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_LC_PLL_CHANNEL_CTRL_CH_1 :: MDIV_CH1 [08:01] */
-#define BCHP_CLKGEN_PLL_LC_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_MASK 0x000001fe
-#define BCHP_CLKGEN_PLL_LC_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_SHIFT 1
-#define BCHP_CLKGEN_PLL_LC_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_DEFAULT 0x0000002d
-
-/* CLKGEN :: PLL_LC_PLL_CHANNEL_CTRL_CH_1 :: CLOCK_DIS_CH1 [00:00] */
-#define BCHP_CLKGEN_PLL_LC_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_MASK 0x00000001
-#define BCHP_CLKGEN_PLL_LC_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_SHIFT 0
-#define BCHP_CLKGEN_PLL_LC_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_DEFAULT 0x00000000
-
-/***************************************************************************
- *PLL_LC_PLL_CHANNEL_CTRL_CH_2 - PLL CHANNEL control CH 2
- ***************************************************************************/
-/* CLKGEN :: PLL_LC_PLL_CHANNEL_CTRL_CH_2 :: reserved0 [31:11] */
-#define BCHP_CLKGEN_PLL_LC_PLL_CHANNEL_CTRL_CH_2_reserved0_MASK 0xfffff800
-#define BCHP_CLKGEN_PLL_LC_PLL_CHANNEL_CTRL_CH_2_reserved0_SHIFT 11
-
-/* CLKGEN :: PLL_LC_PLL_CHANNEL_CTRL_CH_2 :: POST_DIVIDER_HOLD_CH2 [10:10] */
-#define BCHP_CLKGEN_PLL_LC_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_HOLD_CH2_MASK 0x00000400
-#define BCHP_CLKGEN_PLL_LC_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_HOLD_CH2_SHIFT 10
-#define BCHP_CLKGEN_PLL_LC_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_HOLD_CH2_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_LC_PLL_CHANNEL_CTRL_CH_2 :: PHASE_OFFSET_CH2 [09:09] */
-#define BCHP_CLKGEN_PLL_LC_PLL_CHANNEL_CTRL_CH_2_PHASE_OFFSET_CH2_MASK 0x00000200
-#define BCHP_CLKGEN_PLL_LC_PLL_CHANNEL_CTRL_CH_2_PHASE_OFFSET_CH2_SHIFT 9
-#define BCHP_CLKGEN_PLL_LC_PLL_CHANNEL_CTRL_CH_2_PHASE_OFFSET_CH2_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_LC_PLL_CHANNEL_CTRL_CH_2 :: MDIV_CH2 [08:01] */
-#define BCHP_CLKGEN_PLL_LC_PLL_CHANNEL_CTRL_CH_2_MDIV_CH2_MASK 0x000001fe
-#define BCHP_CLKGEN_PLL_LC_PLL_CHANNEL_CTRL_CH_2_MDIV_CH2_SHIFT 1
-#define BCHP_CLKGEN_PLL_LC_PLL_CHANNEL_CTRL_CH_2_MDIV_CH2_DEFAULT 0x00000036
-
-/* CLKGEN :: PLL_LC_PLL_CHANNEL_CTRL_CH_2 :: CLOCK_DIS_CH2 [00:00] */
-#define BCHP_CLKGEN_PLL_LC_PLL_CHANNEL_CTRL_CH_2_CLOCK_DIS_CH2_MASK 0x00000001
-#define BCHP_CLKGEN_PLL_LC_PLL_CHANNEL_CTRL_CH_2_CLOCK_DIS_CH2_SHIFT 0
-#define BCHP_CLKGEN_PLL_LC_PLL_CHANNEL_CTRL_CH_2_CLOCK_DIS_CH2_DEFAULT 0x00000000
-
-/***************************************************************************
- *PLL_LC_PLL_CHANNEL_CTRL_CH_3 - PLL CHANNEL control CH 3
- ***************************************************************************/
-/* CLKGEN :: PLL_LC_PLL_CHANNEL_CTRL_CH_3 :: reserved0 [31:11] */
-#define BCHP_CLKGEN_PLL_LC_PLL_CHANNEL_CTRL_CH_3_reserved0_MASK 0xfffff800
-#define BCHP_CLKGEN_PLL_LC_PLL_CHANNEL_CTRL_CH_3_reserved0_SHIFT 11
-
-/* CLKGEN :: PLL_LC_PLL_CHANNEL_CTRL_CH_3 :: POST_DIVIDER_HOLD_CH3 [10:10] */
-#define BCHP_CLKGEN_PLL_LC_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_HOLD_CH3_MASK 0x00000400
-#define BCHP_CLKGEN_PLL_LC_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_HOLD_CH3_SHIFT 10
-#define BCHP_CLKGEN_PLL_LC_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_HOLD_CH3_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_LC_PLL_CHANNEL_CTRL_CH_3 :: PHASE_OFFSET_CH3 [09:09] */
-#define BCHP_CLKGEN_PLL_LC_PLL_CHANNEL_CTRL_CH_3_PHASE_OFFSET_CH3_MASK 0x00000200
-#define BCHP_CLKGEN_PLL_LC_PLL_CHANNEL_CTRL_CH_3_PHASE_OFFSET_CH3_SHIFT 9
-#define BCHP_CLKGEN_PLL_LC_PLL_CHANNEL_CTRL_CH_3_PHASE_OFFSET_CH3_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_LC_PLL_CHANNEL_CTRL_CH_3 :: MDIV_CH3 [08:01] */
-#define BCHP_CLKGEN_PLL_LC_PLL_CHANNEL_CTRL_CH_3_MDIV_CH3_MASK 0x000001fe
-#define BCHP_CLKGEN_PLL_LC_PLL_CHANNEL_CTRL_CH_3_MDIV_CH3_SHIFT 1
-#define BCHP_CLKGEN_PLL_LC_PLL_CHANNEL_CTRL_CH_3_MDIV_CH3_DEFAULT 0x00000036
-
-/* CLKGEN :: PLL_LC_PLL_CHANNEL_CTRL_CH_3 :: CLOCK_DIS_CH3 [00:00] */
-#define BCHP_CLKGEN_PLL_LC_PLL_CHANNEL_CTRL_CH_3_CLOCK_DIS_CH3_MASK 0x00000001
-#define BCHP_CLKGEN_PLL_LC_PLL_CHANNEL_CTRL_CH_3_CLOCK_DIS_CH3_SHIFT 0
-#define BCHP_CLKGEN_PLL_LC_PLL_CHANNEL_CTRL_CH_3_CLOCK_DIS_CH3_DEFAULT 0x00000001
-
-/***************************************************************************
- *PLL_LC_PLL_CONTROL - Miscellaneous Controls
- ***************************************************************************/
-/* CLKGEN :: PLL_LC_PLL_CONTROL :: reserved0 [31:01] */
-#define BCHP_CLKGEN_PLL_LC_PLL_CONTROL_reserved0_MASK 0xfffffffe
-#define BCHP_CLKGEN_PLL_LC_PLL_CONTROL_reserved0_SHIFT 1
-
-/* CLKGEN :: PLL_LC_PLL_CONTROL :: REF_SEL [00:00] */
-#define BCHP_CLKGEN_PLL_LC_PLL_CONTROL_REF_SEL_MASK 0x00000001
-#define BCHP_CLKGEN_PLL_LC_PLL_CONTROL_REF_SEL_SHIFT 0
-#define BCHP_CLKGEN_PLL_LC_PLL_CONTROL_REF_SEL_DEFAULT 0x00000000
-
-/***************************************************************************
- *PLL_LC_PLL_DIV - Pre multiplier
- ***************************************************************************/
-/* CLKGEN :: PLL_LC_PLL_DIV :: reserved0 [31:14] */
-#define BCHP_CLKGEN_PLL_LC_PLL_DIV_reserved0_MASK 0xffffc000
-#define BCHP_CLKGEN_PLL_LC_PLL_DIV_reserved0_SHIFT 14
-
-/* CLKGEN :: PLL_LC_PLL_DIV :: PDIV [13:10] */
-#define BCHP_CLKGEN_PLL_LC_PLL_DIV_PDIV_MASK 0x00003c00
-#define BCHP_CLKGEN_PLL_LC_PLL_DIV_PDIV_SHIFT 10
-#define BCHP_CLKGEN_PLL_LC_PLL_DIV_PDIV_DEFAULT 0x00000002
-
-/* CLKGEN :: PLL_LC_PLL_DIV :: NDIV_INT [09:00] */
-#define BCHP_CLKGEN_PLL_LC_PLL_DIV_NDIV_INT_MASK 0x000003ff
-#define BCHP_CLKGEN_PLL_LC_PLL_DIV_NDIV_INT_SHIFT 0
-#define BCHP_CLKGEN_PLL_LC_PLL_DIV_NDIV_INT_DEFAULT 0x00000064
-
-/***************************************************************************
- *PLL_LC_PLL_GAIN - PLL GAIN
- ***************************************************************************/
-/* CLKGEN :: PLL_LC_PLL_GAIN :: reserved0 [31:07] */
-#define BCHP_CLKGEN_PLL_LC_PLL_GAIN_reserved0_MASK 0xffffff80
-#define BCHP_CLKGEN_PLL_LC_PLL_GAIN_reserved0_SHIFT 7
-
-/* CLKGEN :: PLL_LC_PLL_GAIN :: LOOP_GAIN_PROPORTIONAL_IN_PHASE [06:03] */
-#define BCHP_CLKGEN_PLL_LC_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_MASK 0x00000078
-#define BCHP_CLKGEN_PLL_LC_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_SHIFT 3
-#define BCHP_CLKGEN_PLL_LC_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_DEFAULT 0x00000006
-
-/* CLKGEN :: PLL_LC_PLL_GAIN :: LOOP_GAIN_INTEGRATOR_IN_PHASE [02:00] */
-#define BCHP_CLKGEN_PLL_LC_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_MASK 0x00000007
-#define BCHP_CLKGEN_PLL_LC_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_SHIFT 0
-#define BCHP_CLKGEN_PLL_LC_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_DEFAULT 0x00000002
-
-/***************************************************************************
- *PLL_LC_PLL_HOLD_CH_ALL - Hold PLL all channels
- ***************************************************************************/
-/* CLKGEN :: PLL_LC_PLL_HOLD_CH_ALL :: reserved0 [31:01] */
-#define BCHP_CLKGEN_PLL_LC_PLL_HOLD_CH_ALL_reserved0_MASK 0xfffffffe
-#define BCHP_CLKGEN_PLL_LC_PLL_HOLD_CH_ALL_reserved0_SHIFT 1
-
-/* CLKGEN :: PLL_LC_PLL_HOLD_CH_ALL :: HOLD_CH_ALL [00:00] */
-#define BCHP_CLKGEN_PLL_LC_PLL_HOLD_CH_ALL_HOLD_CH_ALL_MASK 0x00000001
-#define BCHP_CLKGEN_PLL_LC_PLL_HOLD_CH_ALL_HOLD_CH_ALL_SHIFT 0
-#define BCHP_CLKGEN_PLL_LC_PLL_HOLD_CH_ALL_HOLD_CH_ALL_DEFAULT 0x00000000
-
-/***************************************************************************
- *PLL_LC_PLL_LDO_CTRL - Ldo voltage control
- ***************************************************************************/
-/* CLKGEN :: PLL_LC_PLL_LDO_CTRL :: reserved0 [31:06] */
-#define BCHP_CLKGEN_PLL_LC_PLL_LDO_CTRL_reserved0_MASK 0xffffffc0
-#define BCHP_CLKGEN_PLL_LC_PLL_LDO_CTRL_reserved0_SHIFT 6
-
-/* CLKGEN :: PLL_LC_PLL_LDO_CTRL :: LDO_CTRL [05:00] */
-#define BCHP_CLKGEN_PLL_LC_PLL_LDO_CTRL_LDO_CTRL_MASK 0x0000003f
-#define BCHP_CLKGEN_PLL_LC_PLL_LDO_CTRL_LDO_CTRL_SHIFT 0
-#define BCHP_CLKGEN_PLL_LC_PLL_LDO_CTRL_LDO_CTRL_DEFAULT 0x00000004
-
-/***************************************************************************
- *PLL_LC_PLL_LDO_PWRON - LDO Power on
- ***************************************************************************/
-/* CLKGEN :: PLL_LC_PLL_LDO_PWRON :: reserved0 [31:01] */
-#define BCHP_CLKGEN_PLL_LC_PLL_LDO_PWRON_reserved0_MASK 0xfffffffe
-#define BCHP_CLKGEN_PLL_LC_PLL_LDO_PWRON_reserved0_SHIFT 1
-
-/* CLKGEN :: PLL_LC_PLL_LDO_PWRON :: LDO_PWRON_PLL [00:00] */
-#define BCHP_CLKGEN_PLL_LC_PLL_LDO_PWRON_LDO_PWRON_PLL_MASK 0x00000001
-#define BCHP_CLKGEN_PLL_LC_PLL_LDO_PWRON_LDO_PWRON_PLL_SHIFT 0
-#define BCHP_CLKGEN_PLL_LC_PLL_LDO_PWRON_LDO_PWRON_PLL_DEFAULT 0x00000001
-
-/***************************************************************************
- *PLL_LC_PLL_LOCK_STATUS - Lock Status
- ***************************************************************************/
-/* CLKGEN :: PLL_LC_PLL_LOCK_STATUS :: reserved0 [31:01] */
-#define BCHP_CLKGEN_PLL_LC_PLL_LOCK_STATUS_reserved0_MASK 0xfffffffe
-#define BCHP_CLKGEN_PLL_LC_PLL_LOCK_STATUS_reserved0_SHIFT 1
-
-/* CLKGEN :: PLL_LC_PLL_LOCK_STATUS :: LOCK [00:00] */
-#define BCHP_CLKGEN_PLL_LC_PLL_LOCK_STATUS_LOCK_MASK 0x00000001
-#define BCHP_CLKGEN_PLL_LC_PLL_LOCK_STATUS_LOCK_SHIFT 0
-
-/***************************************************************************
- *PLL_LC_PLL_MISC - Mscellaneous control bus.
- ***************************************************************************/
-/* CLKGEN :: PLL_LC_PLL_MISC :: VCO_PREDIV_RATIO [31:31] */
-#define BCHP_CLKGEN_PLL_LC_PLL_MISC_VCO_PREDIV_RATIO_MASK 0x80000000
-#define BCHP_CLKGEN_PLL_LC_PLL_MISC_VCO_PREDIV_RATIO_SHIFT 31
-#define BCHP_CLKGEN_PLL_LC_PLL_MISC_VCO_PREDIV_RATIO_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_LC_PLL_MISC :: T2D_DELAY_SEL_LOW [30:28] */
-#define BCHP_CLKGEN_PLL_LC_PLL_MISC_T2D_DELAY_SEL_LOW_MASK 0x70000000
-#define BCHP_CLKGEN_PLL_LC_PLL_MISC_T2D_DELAY_SEL_LOW_SHIFT 28
-#define BCHP_CLKGEN_PLL_LC_PLL_MISC_T2D_DELAY_SEL_LOW_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_LC_PLL_MISC :: SEL_MEASURE_UNIT [27:25] */
-#define BCHP_CLKGEN_PLL_LC_PLL_MISC_SEL_MEASURE_UNIT_MASK 0x0e000000
-#define BCHP_CLKGEN_PLL_LC_PLL_MISC_SEL_MEASURE_UNIT_SHIFT 25
-#define BCHP_CLKGEN_PLL_LC_PLL_MISC_SEL_MEASURE_UNIT_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_LC_PLL_MISC :: RESET_MEASURE_MODE [24:24] */
-#define BCHP_CLKGEN_PLL_LC_PLL_MISC_RESET_MEASURE_MODE_MASK 0x01000000
-#define BCHP_CLKGEN_PLL_LC_PLL_MISC_RESET_MEASURE_MODE_SHIFT 24
-#define BCHP_CLKGEN_PLL_LC_PLL_MISC_RESET_MEASURE_MODE_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_LC_PLL_MISC :: LOAD_DCO_BYP_WORD [23:23] */
-#define BCHP_CLKGEN_PLL_LC_PLL_MISC_LOAD_DCO_BYP_WORD_MASK 0x00800000
-#define BCHP_CLKGEN_PLL_LC_PLL_MISC_LOAD_DCO_BYP_WORD_SHIFT 23
-#define BCHP_CLKGEN_PLL_LC_PLL_MISC_LOAD_DCO_BYP_WORD_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_LC_PLL_MISC :: FREQ_BYP_WORD [22:07] */
-#define BCHP_CLKGEN_PLL_LC_PLL_MISC_FREQ_BYP_WORD_MASK 0x007fff80
-#define BCHP_CLKGEN_PLL_LC_PLL_MISC_FREQ_BYP_WORD_SHIFT 7
-#define BCHP_CLKGEN_PLL_LC_PLL_MISC_FREQ_BYP_WORD_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_LC_PLL_MISC :: EN_VCO_OUTPUT [06:06] */
-#define BCHP_CLKGEN_PLL_LC_PLL_MISC_EN_VCO_OUTPUT_MASK 0x00000040
-#define BCHP_CLKGEN_PLL_LC_PLL_MISC_EN_VCO_OUTPUT_SHIFT 6
-#define BCHP_CLKGEN_PLL_LC_PLL_MISC_EN_VCO_OUTPUT_DEFAULT 0x00000001
-
-/* CLKGEN :: PLL_LC_PLL_MISC :: EN_DCO_BYP_WORD [05:05] */
-#define BCHP_CLKGEN_PLL_LC_PLL_MISC_EN_DCO_BYP_WORD_MASK 0x00000020
-#define BCHP_CLKGEN_PLL_LC_PLL_MISC_EN_DCO_BYP_WORD_SHIFT 5
-#define BCHP_CLKGEN_PLL_LC_PLL_MISC_EN_DCO_BYP_WORD_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_LC_PLL_MISC :: EN_BANGBANG_MODE [04:04] */
-#define BCHP_CLKGEN_PLL_LC_PLL_MISC_EN_BANGBANG_MODE_MASK 0x00000010
-#define BCHP_CLKGEN_PLL_LC_PLL_MISC_EN_BANGBANG_MODE_SHIFT 4
-#define BCHP_CLKGEN_PLL_LC_PLL_MISC_EN_BANGBANG_MODE_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_LC_PLL_MISC :: CTRL_MEASURE_MODE [03:02] */
-#define BCHP_CLKGEN_PLL_LC_PLL_MISC_CTRL_MEASURE_MODE_MASK 0x0000000c
-#define BCHP_CLKGEN_PLL_LC_PLL_MISC_CTRL_MEASURE_MODE_SHIFT 2
-#define BCHP_CLKGEN_PLL_LC_PLL_MISC_CTRL_MEASURE_MODE_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_LC_PLL_MISC :: CHANGE_MEASURE_UNIT [01:01] */
-#define BCHP_CLKGEN_PLL_LC_PLL_MISC_CHANGE_MEASURE_UNIT_MASK 0x00000002
-#define BCHP_CLKGEN_PLL_LC_PLL_MISC_CHANGE_MEASURE_UNIT_SHIFT 1
-#define BCHP_CLKGEN_PLL_LC_PLL_MISC_CHANGE_MEASURE_UNIT_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_LC_PLL_MISC :: BOOST_BIAS_CIRCUIT [00:00] */
-#define BCHP_CLKGEN_PLL_LC_PLL_MISC_BOOST_BIAS_CIRCUIT_MASK 0x00000001
-#define BCHP_CLKGEN_PLL_LC_PLL_MISC_BOOST_BIAS_CIRCUIT_SHIFT 0
-#define BCHP_CLKGEN_PLL_LC_PLL_MISC_BOOST_BIAS_CIRCUIT_DEFAULT 0x00000000
-
-/***************************************************************************
- *PLL_LC_PLL_MISC2 - Mscellaneous control bus continued.
- ***************************************************************************/
-/* CLKGEN :: PLL_LC_PLL_MISC2 :: T2D_DELAY_SEL_HIGH [31:31] */
-#define BCHP_CLKGEN_PLL_LC_PLL_MISC2_T2D_DELAY_SEL_HIGH_MASK 0x80000000
-#define BCHP_CLKGEN_PLL_LC_PLL_MISC2_T2D_DELAY_SEL_HIGH_SHIFT 31
-#define BCHP_CLKGEN_PLL_LC_PLL_MISC2_T2D_DELAY_SEL_HIGH_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_LC_PLL_MISC2 :: SEL_TEST_CLK [30:30] */
-#define BCHP_CLKGEN_PLL_LC_PLL_MISC2_SEL_TEST_CLK_MASK 0x40000000
-#define BCHP_CLKGEN_PLL_LC_PLL_MISC2_SEL_TEST_CLK_SHIFT 30
-#define BCHP_CLKGEN_PLL_LC_PLL_MISC2_SEL_TEST_CLK_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_LC_PLL_MISC2 :: SEL_DIFF_REFCLK_SRC [29:29] */
-#define BCHP_CLKGEN_PLL_LC_PLL_MISC2_SEL_DIFF_REFCLK_SRC_MASK 0x20000000
-#define BCHP_CLKGEN_PLL_LC_PLL_MISC2_SEL_DIFF_REFCLK_SRC_SHIFT 29
-#define BCHP_CLKGEN_PLL_LC_PLL_MISC2_SEL_DIFF_REFCLK_SRC_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_LC_PLL_MISC2 :: PLLRESERVED0 [28:11] */
-#define BCHP_CLKGEN_PLL_LC_PLL_MISC2_PLLRESERVED0_MASK 0x1ffff800
-#define BCHP_CLKGEN_PLL_LC_PLL_MISC2_PLLRESERVED0_SHIFT 11
-#define BCHP_CLKGEN_PLL_LC_PLL_MISC2_PLLRESERVED0_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_LC_PLL_MISC2 :: INTERNAL_RESET_MODE [10:09] */
-#define BCHP_CLKGEN_PLL_LC_PLL_MISC2_INTERNAL_RESET_MODE_MASK 0x00000600
-#define BCHP_CLKGEN_PLL_LC_PLL_MISC2_INTERNAL_RESET_MODE_SHIFT 9
-#define BCHP_CLKGEN_PLL_LC_PLL_MISC2_INTERNAL_RESET_MODE_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_LC_PLL_MISC2 :: EN_TEST_CLK [08:08] */
-#define BCHP_CLKGEN_PLL_LC_PLL_MISC2_EN_TEST_CLK_MASK 0x00000100
-#define BCHP_CLKGEN_PLL_LC_PLL_MISC2_EN_TEST_CLK_SHIFT 8
-#define BCHP_CLKGEN_PLL_LC_PLL_MISC2_EN_TEST_CLK_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_LC_PLL_MISC2 :: EN_BYPCLK_1 [07:07] */
-#define BCHP_CLKGEN_PLL_LC_PLL_MISC2_EN_BYPCLK_1_MASK 0x00000080
-#define BCHP_CLKGEN_PLL_LC_PLL_MISC2_EN_BYPCLK_1_SHIFT 7
-#define BCHP_CLKGEN_PLL_LC_PLL_MISC2_EN_BYPCLK_1_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_LC_PLL_MISC2 :: EN_BYPCLK_0 [06:06] */
-#define BCHP_CLKGEN_PLL_LC_PLL_MISC2_EN_BYPCLK_0_MASK 0x00000040
-#define BCHP_CLKGEN_PLL_LC_PLL_MISC2_EN_BYPCLK_0_SHIFT 6
-#define BCHP_CLKGEN_PLL_LC_PLL_MISC2_EN_BYPCLK_0_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_LC_PLL_MISC2 :: DCO_PWM_RATE_CTRL [05:04] */
-#define BCHP_CLKGEN_PLL_LC_PLL_MISC2_DCO_PWM_RATE_CTRL_MASK 0x00000030
-#define BCHP_CLKGEN_PLL_LC_PLL_MISC2_DCO_PWM_RATE_CTRL_SHIFT 4
-#define BCHP_CLKGEN_PLL_LC_PLL_MISC2_DCO_PWM_RATE_CTRL_DEFAULT 0x00000002
-
-/* CLKGEN :: PLL_LC_PLL_MISC2 :: CTRL_2ND_POLE [03:00] */
-#define BCHP_CLKGEN_PLL_LC_PLL_MISC2_CTRL_2ND_POLE_MASK 0x0000000f
-#define BCHP_CLKGEN_PLL_LC_PLL_MISC2_CTRL_2ND_POLE_SHIFT 0
-#define BCHP_CLKGEN_PLL_LC_PLL_MISC2_CTRL_2ND_POLE_DEFAULT 0x00000000
-
-/***************************************************************************
- *PLL_LC_PLL_OUTSEL_SEL - selection of the output clock from the PLL core
- ***************************************************************************/
-/* CLKGEN :: PLL_LC_PLL_OUTSEL_SEL :: reserved0 [31:03] */
-#define BCHP_CLKGEN_PLL_LC_PLL_OUTSEL_SEL_reserved0_MASK 0xfffffff8
-#define BCHP_CLKGEN_PLL_LC_PLL_OUTSEL_SEL_reserved0_SHIFT 3
-
-/* CLKGEN :: PLL_LC_PLL_OUTSEL_SEL :: OUTPUT_SEL [02:00] */
-#define BCHP_CLKGEN_PLL_LC_PLL_OUTSEL_SEL_OUTPUT_SEL_MASK 0x00000007
-#define BCHP_CLKGEN_PLL_LC_PLL_OUTSEL_SEL_OUTPUT_SEL_SHIFT 0
-#define BCHP_CLKGEN_PLL_LC_PLL_OUTSEL_SEL_OUTPUT_SEL_DEFAULT 0x00000000
-
-/***************************************************************************
- *PLL_LC_PLL_PWRON - Poweron
- ***************************************************************************/
-/* CLKGEN :: PLL_LC_PLL_PWRON :: reserved0 [31:01] */
-#define BCHP_CLKGEN_PLL_LC_PLL_PWRON_reserved0_MASK 0xfffffffe
-#define BCHP_CLKGEN_PLL_LC_PLL_PWRON_reserved0_SHIFT 1
-
-/* CLKGEN :: PLL_LC_PLL_PWRON :: PWRON_PLL [00:00] */
-#define BCHP_CLKGEN_PLL_LC_PLL_PWRON_PWRON_PLL_MASK 0x00000001
-#define BCHP_CLKGEN_PLL_LC_PLL_PWRON_PWRON_PLL_SHIFT 0
-#define BCHP_CLKGEN_PLL_LC_PLL_PWRON_PWRON_PLL_DEFAULT 0x00000001
-
-/***************************************************************************
- *PLL_LC_PLL_RESET - Resets
- ***************************************************************************/
-/* CLKGEN :: PLL_LC_PLL_RESET :: reserved0 [31:02] */
-#define BCHP_CLKGEN_PLL_LC_PLL_RESET_reserved0_MASK 0xfffffffc
-#define BCHP_CLKGEN_PLL_LC_PLL_RESET_reserved0_SHIFT 2
-
-/* CLKGEN :: PLL_LC_PLL_RESET :: RESETD [01:01] */
-#define BCHP_CLKGEN_PLL_LC_PLL_RESET_RESETD_MASK 0x00000002
-#define BCHP_CLKGEN_PLL_LC_PLL_RESET_RESETD_SHIFT 1
-#define BCHP_CLKGEN_PLL_LC_PLL_RESET_RESETD_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_LC_PLL_RESET :: RESETA [00:00] */
-#define BCHP_CLKGEN_PLL_LC_PLL_RESET_RESETA_MASK 0x00000001
-#define BCHP_CLKGEN_PLL_LC_PLL_RESET_RESETA_SHIFT 0
-#define BCHP_CLKGEN_PLL_LC_PLL_RESET_RESETA_DEFAULT 0x00000000
-
-/***************************************************************************
- *PLL_LC_PLL_STATUS - Status
- ***************************************************************************/
-/* CLKGEN :: PLL_LC_PLL_STATUS :: TEST_STATUS [31:00] */
-#define BCHP_CLKGEN_PLL_LC_PLL_STATUS_TEST_STATUS_MASK 0xffffffff
-#define BCHP_CLKGEN_PLL_LC_PLL_STATUS_TEST_STATUS_SHIFT 0
-
-/***************************************************************************
- *PLL_LC_PLL_TEST - enable and selection pf PLL test
- ***************************************************************************/
-/* CLKGEN :: PLL_LC_PLL_TEST :: reserved0 [31:04] */
-#define BCHP_CLKGEN_PLL_LC_PLL_TEST_reserved0_MASK 0xfffffff0
-#define BCHP_CLKGEN_PLL_LC_PLL_TEST_reserved0_SHIFT 4
-
-/* CLKGEN :: PLL_LC_PLL_TEST :: TEST_SEL [03:01] */
-#define BCHP_CLKGEN_PLL_LC_PLL_TEST_TEST_SEL_MASK 0x0000000e
-#define BCHP_CLKGEN_PLL_LC_PLL_TEST_TEST_SEL_SHIFT 1
-#define BCHP_CLKGEN_PLL_LC_PLL_TEST_TEST_SEL_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_LC_PLL_TEST :: TEST_ENABLE [00:00] */
-#define BCHP_CLKGEN_PLL_LC_PLL_TEST_TEST_ENABLE_MASK 0x00000001
-#define BCHP_CLKGEN_PLL_LC_PLL_TEST_TEST_ENABLE_SHIFT 0
-#define BCHP_CLKGEN_PLL_LC_PLL_TEST_TEST_ENABLE_DEFAULT 0x00000000
-
-/***************************************************************************
- *PLL_MOCA_PLL_CHANNEL_CTRL_CH_0 - PLL CHANNEL control CH 0
- ***************************************************************************/
-/* CLKGEN :: PLL_MOCA_PLL_CHANNEL_CTRL_CH_0 :: reserved0 [31:11] */
-#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_0_reserved0_MASK 0xfffff800
-#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_0_reserved0_SHIFT 11
-
-/* CLKGEN :: PLL_MOCA_PLL_CHANNEL_CTRL_CH_0 :: POST_DIVIDER_HOLD_CH0 [10:10] */
-#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_MASK 0x00000400
-#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_SHIFT 10
-#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_MOCA_PLL_CHANNEL_CTRL_CH_0 :: PHASE_OFFSET_CH0 [09:09] */
-#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_MASK 0x00000200
-#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_SHIFT 9
-#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_MOCA_PLL_CHANNEL_CTRL_CH_0 :: MDIV_CH0 [08:01] */
-#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_MASK 0x000001fe
-#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_SHIFT 1
-#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_DEFAULT 0x00000009
-
-/* CLKGEN :: PLL_MOCA_PLL_CHANNEL_CTRL_CH_0 :: CLOCK_DIS_CH0 [00:00] */
-#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_MASK 0x00000001
-#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_SHIFT 0
-#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_DEFAULT 0x00000000
-
-/***************************************************************************
- *PLL_MOCA_PLL_CHANNEL_CTRL_CH_1 - PLL CHANNEL control CH 1
- ***************************************************************************/
-/* CLKGEN :: PLL_MOCA_PLL_CHANNEL_CTRL_CH_1 :: reserved0 [31:11] */
-#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_1_reserved0_MASK 0xfffff800
-#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_1_reserved0_SHIFT 11
-
-/* CLKGEN :: PLL_MOCA_PLL_CHANNEL_CTRL_CH_1 :: POST_DIVIDER_HOLD_CH1 [10:10] */
-#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_MASK 0x00000400
-#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_SHIFT 10
-#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_MOCA_PLL_CHANNEL_CTRL_CH_1 :: PHASE_OFFSET_CH1 [09:09] */
-#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_MASK 0x00000200
-#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_SHIFT 9
-#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_MOCA_PLL_CHANNEL_CTRL_CH_1 :: MDIV_CH1 [08:01] */
-#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_MASK 0x000001fe
-#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_SHIFT 1
-#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_DEFAULT 0x00000009
-
-/* CLKGEN :: PLL_MOCA_PLL_CHANNEL_CTRL_CH_1 :: CLOCK_DIS_CH1 [00:00] */
-#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_MASK 0x00000001
-#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_SHIFT 0
-#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_DEFAULT 0x00000000
-
-/***************************************************************************
- *PLL_MOCA_PLL_CHANNEL_CTRL_CH_2 - PLL CHANNEL control CH 2
- ***************************************************************************/
-/* CLKGEN :: PLL_MOCA_PLL_CHANNEL_CTRL_CH_2 :: reserved0 [31:11] */
-#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_2_reserved0_MASK 0xfffff800
-#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_2_reserved0_SHIFT 11
-
-/* CLKGEN :: PLL_MOCA_PLL_CHANNEL_CTRL_CH_2 :: POST_DIVIDER_HOLD_CH2 [10:10] */
-#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_HOLD_CH2_MASK 0x00000400
-#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_HOLD_CH2_SHIFT 10
-#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_HOLD_CH2_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_MOCA_PLL_CHANNEL_CTRL_CH_2 :: PHASE_OFFSET_CH2 [09:09] */
-#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_2_PHASE_OFFSET_CH2_MASK 0x00000200
-#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_2_PHASE_OFFSET_CH2_SHIFT 9
-#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_2_PHASE_OFFSET_CH2_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_MOCA_PLL_CHANNEL_CTRL_CH_2 :: MDIV_CH2 [08:01] */
-#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_2_MDIV_CH2_MASK 0x000001fe
-#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_2_MDIV_CH2_SHIFT 1
-#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_2_MDIV_CH2_DEFAULT 0x00000024
-
-/* CLKGEN :: PLL_MOCA_PLL_CHANNEL_CTRL_CH_2 :: CLOCK_DIS_CH2 [00:00] */
-#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_2_CLOCK_DIS_CH2_MASK 0x00000001
-#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_2_CLOCK_DIS_CH2_SHIFT 0
-#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_2_CLOCK_DIS_CH2_DEFAULT 0x00000000
-
-/***************************************************************************
- *PLL_MOCA_PLL_CHANNEL_CTRL_CH_3 - PLL CHANNEL control CH 3
- ***************************************************************************/
-/* CLKGEN :: PLL_MOCA_PLL_CHANNEL_CTRL_CH_3 :: reserved0 [31:11] */
-#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_3_reserved0_MASK 0xfffff800
-#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_3_reserved0_SHIFT 11
-
-/* CLKGEN :: PLL_MOCA_PLL_CHANNEL_CTRL_CH_3 :: POST_DIVIDER_HOLD_CH3 [10:10] */
-#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_HOLD_CH3_MASK 0x00000400
-#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_HOLD_CH3_SHIFT 10
-#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_HOLD_CH3_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_MOCA_PLL_CHANNEL_CTRL_CH_3 :: PHASE_OFFSET_CH3 [09:09] */
-#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_3_PHASE_OFFSET_CH3_MASK 0x00000200
-#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_3_PHASE_OFFSET_CH3_SHIFT 9
-#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_3_PHASE_OFFSET_CH3_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_MOCA_PLL_CHANNEL_CTRL_CH_3 :: MDIV_CH3 [08:01] */
-#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_3_MDIV_CH3_MASK 0x000001fe
-#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_3_MDIV_CH3_SHIFT 1
-#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_3_MDIV_CH3_DEFAULT 0x00000012
-
-/* CLKGEN :: PLL_MOCA_PLL_CHANNEL_CTRL_CH_3 :: CLOCK_DIS_CH3 [00:00] */
-#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_3_CLOCK_DIS_CH3_MASK 0x00000001
-#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_3_CLOCK_DIS_CH3_SHIFT 0
-#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_3_CLOCK_DIS_CH3_DEFAULT 0x00000000
-
-/***************************************************************************
- *PLL_MOCA_PLL_DIV - Pre multiplier
- ***************************************************************************/
-/* CLKGEN :: PLL_MOCA_PLL_DIV :: reserved0 [31:14] */
-#define BCHP_CLKGEN_PLL_MOCA_PLL_DIV_reserved0_MASK 0xffffc000
-#define BCHP_CLKGEN_PLL_MOCA_PLL_DIV_reserved0_SHIFT 14
-
-/* CLKGEN :: PLL_MOCA_PLL_DIV :: PDIV [13:10] */
-#define BCHP_CLKGEN_PLL_MOCA_PLL_DIV_PDIV_MASK 0x00003c00
-#define BCHP_CLKGEN_PLL_MOCA_PLL_DIV_PDIV_SHIFT 10
-#define BCHP_CLKGEN_PLL_MOCA_PLL_DIV_PDIV_DEFAULT 0x00000003
-
-/* CLKGEN :: PLL_MOCA_PLL_DIV :: NDIV_INT [09:00] */
-#define BCHP_CLKGEN_PLL_MOCA_PLL_DIV_NDIV_INT_MASK 0x000003ff
-#define BCHP_CLKGEN_PLL_MOCA_PLL_DIV_NDIV_INT_SHIFT 0
-#define BCHP_CLKGEN_PLL_MOCA_PLL_DIV_NDIV_INT_DEFAULT 0x000000c8
-
-/***************************************************************************
- *PLL_MOCA_PLL_GAIN - PLL GAIN
- ***************************************************************************/
-/* CLKGEN :: PLL_MOCA_PLL_GAIN :: reserved0 [31:10] */
-#define BCHP_CLKGEN_PLL_MOCA_PLL_GAIN_reserved0_MASK 0xfffffc00
-#define BCHP_CLKGEN_PLL_MOCA_PLL_GAIN_reserved0_SHIFT 10
-
-/* CLKGEN :: PLL_MOCA_PLL_GAIN :: LOOP_GAIN_PROPORTIONAL_IN_PHASE [09:06] */
-#define BCHP_CLKGEN_PLL_MOCA_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_MASK 0x000003c0
-#define BCHP_CLKGEN_PLL_MOCA_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_SHIFT 6
-#define BCHP_CLKGEN_PLL_MOCA_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_DEFAULT 0x00000005
-
-/* CLKGEN :: PLL_MOCA_PLL_GAIN :: LOOP_GAIN_IN_FREQ [05:03] */
-#define BCHP_CLKGEN_PLL_MOCA_PLL_GAIN_LOOP_GAIN_IN_FREQ_MASK 0x00000038
-#define BCHP_CLKGEN_PLL_MOCA_PLL_GAIN_LOOP_GAIN_IN_FREQ_SHIFT 3
-#define BCHP_CLKGEN_PLL_MOCA_PLL_GAIN_LOOP_GAIN_IN_FREQ_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_MOCA_PLL_GAIN :: LOOP_GAIN_INTEGRATOR_IN_PHASE [02:00] */
-#define BCHP_CLKGEN_PLL_MOCA_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_MASK 0x00000007
-#define BCHP_CLKGEN_PLL_MOCA_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_SHIFT 0
-#define BCHP_CLKGEN_PLL_MOCA_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_DEFAULT 0x00000002
-
-/***************************************************************************
- *PLL_MOCA_PLL_LDO_PWRON - LDO Power on
- ***************************************************************************/
-/* CLKGEN :: PLL_MOCA_PLL_LDO_PWRON :: reserved0 [31:01] */
-#define BCHP_CLKGEN_PLL_MOCA_PLL_LDO_PWRON_reserved0_MASK 0xfffffffe
-#define BCHP_CLKGEN_PLL_MOCA_PLL_LDO_PWRON_reserved0_SHIFT 1
-
-/* CLKGEN :: PLL_MOCA_PLL_LDO_PWRON :: LDO_PWRON_PLL [00:00] */
-#define BCHP_CLKGEN_PLL_MOCA_PLL_LDO_PWRON_LDO_PWRON_PLL_MASK 0x00000001
-#define BCHP_CLKGEN_PLL_MOCA_PLL_LDO_PWRON_LDO_PWRON_PLL_SHIFT 0
-#define BCHP_CLKGEN_PLL_MOCA_PLL_LDO_PWRON_LDO_PWRON_PLL_DEFAULT 0x00000001
-
-/***************************************************************************
- *PLL_MOCA_PLL_LOCK_STATUS - Lock Status
- ***************************************************************************/
-/* CLKGEN :: PLL_MOCA_PLL_LOCK_STATUS :: reserved0 [31:02] */
-#define BCHP_CLKGEN_PLL_MOCA_PLL_LOCK_STATUS_reserved0_MASK 0xfffffffc
-#define BCHP_CLKGEN_PLL_MOCA_PLL_LOCK_STATUS_reserved0_SHIFT 2
-
-/* CLKGEN :: PLL_MOCA_PLL_LOCK_STATUS :: LOCK_LOST [01:01] */
-#define BCHP_CLKGEN_PLL_MOCA_PLL_LOCK_STATUS_LOCK_LOST_MASK 0x00000002
-#define BCHP_CLKGEN_PLL_MOCA_PLL_LOCK_STATUS_LOCK_LOST_SHIFT 1
-
-/* CLKGEN :: PLL_MOCA_PLL_LOCK_STATUS :: LOCK [00:00] */
-#define BCHP_CLKGEN_PLL_MOCA_PLL_LOCK_STATUS_LOCK_MASK 0x00000001
-#define BCHP_CLKGEN_PLL_MOCA_PLL_LOCK_STATUS_LOCK_SHIFT 0
-
-/***************************************************************************
- *PLL_MOCA_PLL_MISC - Mscellaneous control bus.
- ***************************************************************************/
-/* CLKGEN :: PLL_MOCA_PLL_MISC :: VCO_RANGE [31:30] */
-#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_VCO_RANGE_MASK 0xc0000000
-#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_VCO_RANGE_SHIFT 30
-#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_VCO_RANGE_DEFAULT 0x00000002
-
-/* CLKGEN :: PLL_MOCA_PLL_MISC :: VCO_FB_DIV2 [29:29] */
-#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_VCO_FB_DIV2_MASK 0x20000000
-#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_VCO_FB_DIV2_SHIFT 29
-#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_VCO_FB_DIV2_DEFAULT 0x00000001
-
-/* CLKGEN :: PLL_MOCA_PLL_MISC :: STAT_UPDATE [28:28] */
-#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_STAT_UPDATE_MASK 0x10000000
-#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_STAT_UPDATE_SHIFT 28
-#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_STAT_UPDATE_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_MOCA_PLL_MISC :: STAT_SELECT [27:25] */
-#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_STAT_SELECT_MASK 0x0e000000
-#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_STAT_SELECT_SHIFT 25
-#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_STAT_SELECT_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_MOCA_PLL_MISC :: STAT_RESET [24:24] */
-#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_STAT_RESET_MASK 0x01000000
-#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_STAT_RESET_SHIFT 24
-#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_STAT_RESET_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_MOCA_PLL_MISC :: STAT_MODE [23:22] */
-#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_STAT_MODE_MASK 0x00c00000
-#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_STAT_MODE_SHIFT 22
-#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_STAT_MODE_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_MOCA_PLL_MISC :: PWM_RATE [21:20] */
-#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_PWM_RATE_MASK 0x00300000
-#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_PWM_RATE_SHIFT 20
-#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_PWM_RATE_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_MOCA_PLL_MISC :: POST_CTRL_RESETB [19:18] */
-#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_POST_CTRL_RESETB_MASK 0x000c0000
-#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_POST_CTRL_RESETB_SHIFT 18
-#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_POST_CTRL_RESETB_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_MOCA_PLL_MISC :: PLLRESERVED2 [17:16] */
-#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_PLLRESERVED2_MASK 0x00030000
-#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_PLLRESERVED2_SHIFT 16
-#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_PLLRESERVED2_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_MOCA_PLL_MISC :: PLLRESERVED1 [15:15] */
-#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_PLLRESERVED1_MASK 0x00008000
-#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_PLLRESERVED1_SHIFT 15
-#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_PLLRESERVED1_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_MOCA_PLL_MISC :: NDIV_RELOCK [14:14] */
-#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_NDIV_RELOCK_MASK 0x00004000
-#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_NDIV_RELOCK_SHIFT 14
-#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_NDIV_RELOCK_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_MOCA_PLL_MISC :: FAST_LOCK [13:13] */
-#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_FAST_LOCK_MASK 0x00002000
-#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_FAST_LOCK_SHIFT 13
-#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_FAST_LOCK_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_MOCA_PLL_MISC :: DCO_CTRL_BYPASS_ENABLE [12:12] */
-#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_MASK 0x00001000
-#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_SHIFT 12
-#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_MOCA_PLL_MISC :: DCO_CTRL_BYPASS [11:00] */
-#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_DCO_CTRL_BYPASS_MASK 0x00000fff
-#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_DCO_CTRL_BYPASS_SHIFT 0
-#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_DCO_CTRL_BYPASS_DEFAULT 0x00000000
-
-/***************************************************************************
- *PLL_MOCA_PLL_MISC2 - Mscellaneous control bus continued.
- ***************************************************************************/
-/* CLKGEN :: PLL_MOCA_PLL_MISC2 :: PLLRESERVED0 [31:02] */
-#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC2_PLLRESERVED0_MASK 0xfffffffc
-#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC2_PLLRESERVED0_SHIFT 2
-#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC2_PLLRESERVED0_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_MOCA_PLL_MISC2 :: LDO [01:00] */
-#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC2_LDO_MASK 0x00000003
-#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC2_LDO_SHIFT 0
-#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC2_LDO_DEFAULT 0x00000001
-
-/***************************************************************************
- *PLL_MOCA_PLL_PWRON - Poweron
- ***************************************************************************/
-/* CLKGEN :: PLL_MOCA_PLL_PWRON :: reserved0 [31:01] */
-#define BCHP_CLKGEN_PLL_MOCA_PLL_PWRON_reserved0_MASK 0xfffffffe
-#define BCHP_CLKGEN_PLL_MOCA_PLL_PWRON_reserved0_SHIFT 1
-
-/* CLKGEN :: PLL_MOCA_PLL_PWRON :: PWRON_PLL [00:00] */
-#define BCHP_CLKGEN_PLL_MOCA_PLL_PWRON_PWRON_PLL_MASK 0x00000001
-#define BCHP_CLKGEN_PLL_MOCA_PLL_PWRON_PWRON_PLL_SHIFT 0
-#define BCHP_CLKGEN_PLL_MOCA_PLL_PWRON_PWRON_PLL_DEFAULT 0x00000001
-
-/***************************************************************************
- *PLL_MOCA_PLL_RESET - Resets
- ***************************************************************************/
-/* CLKGEN :: PLL_MOCA_PLL_RESET :: reserved0 [31:02] */
-#define BCHP_CLKGEN_PLL_MOCA_PLL_RESET_reserved0_MASK 0xfffffffc
-#define BCHP_CLKGEN_PLL_MOCA_PLL_RESET_reserved0_SHIFT 2
-
-/* CLKGEN :: PLL_MOCA_PLL_RESET :: RESETD [01:01] */
-#define BCHP_CLKGEN_PLL_MOCA_PLL_RESET_RESETD_MASK 0x00000002
-#define BCHP_CLKGEN_PLL_MOCA_PLL_RESET_RESETD_SHIFT 1
-#define BCHP_CLKGEN_PLL_MOCA_PLL_RESET_RESETD_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_MOCA_PLL_RESET :: RESETA [00:00] */
-#define BCHP_CLKGEN_PLL_MOCA_PLL_RESET_RESETA_MASK 0x00000001
-#define BCHP_CLKGEN_PLL_MOCA_PLL_RESET_RESETA_SHIFT 0
-#define BCHP_CLKGEN_PLL_MOCA_PLL_RESET_RESETA_DEFAULT 0x00000000
-
-/***************************************************************************
- *PLL_MOCA_PLL_SSC_MODE_CONTROL_HIGH - Higher bits of Spread Spectrum mode control
- ***************************************************************************/
-/* CLKGEN :: PLL_MOCA_PLL_SSC_MODE_CONTROL_HIGH :: reserved0 [31:16] */
-#define BCHP_CLKGEN_PLL_MOCA_PLL_SSC_MODE_CONTROL_HIGH_reserved0_MASK 0xffff0000
-#define BCHP_CLKGEN_PLL_MOCA_PLL_SSC_MODE_CONTROL_HIGH_reserved0_SHIFT 16
-
-/* CLKGEN :: PLL_MOCA_PLL_SSC_MODE_CONTROL_HIGH :: SSC_STEP [15:00] */
-#define BCHP_CLKGEN_PLL_MOCA_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_MASK 0x0000ffff
-#define BCHP_CLKGEN_PLL_MOCA_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_SHIFT 0
-#define BCHP_CLKGEN_PLL_MOCA_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *PLL_MOCA_PLL_SSC_MODE_CONTROL_LOW - Lower bits of Spread Spectrum mode control
- ***************************************************************************/
-/* CLKGEN :: PLL_MOCA_PLL_SSC_MODE_CONTROL_LOW :: reserved0 [31:23] */
-#define BCHP_CLKGEN_PLL_MOCA_PLL_SSC_MODE_CONTROL_LOW_reserved0_MASK 0xff800000
-#define BCHP_CLKGEN_PLL_MOCA_PLL_SSC_MODE_CONTROL_LOW_reserved0_SHIFT 23
-
-/* CLKGEN :: PLL_MOCA_PLL_SSC_MODE_CONTROL_LOW :: SSC_MODE [22:22] */
-#define BCHP_CLKGEN_PLL_MOCA_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_MASK 0x00400000
-#define BCHP_CLKGEN_PLL_MOCA_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_SHIFT 22
-#define BCHP_CLKGEN_PLL_MOCA_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_MOCA_PLL_SSC_MODE_CONTROL_LOW :: SSC_LIMIT [21:00] */
-#define BCHP_CLKGEN_PLL_MOCA_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_MASK 0x003fffff
-#define BCHP_CLKGEN_PLL_MOCA_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_SHIFT 0
-#define BCHP_CLKGEN_PLL_MOCA_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_DEFAULT 0x00000000
-
-/***************************************************************************
- *PLL_MOCA_PLL_STATUS - Status
- ***************************************************************************/
-/* CLKGEN :: PLL_MOCA_PLL_STATUS :: reserved0 [31:12] */
-#define BCHP_CLKGEN_PLL_MOCA_PLL_STATUS_reserved0_MASK 0xfffff000
-#define BCHP_CLKGEN_PLL_MOCA_PLL_STATUS_reserved0_SHIFT 12
-
-/* CLKGEN :: PLL_MOCA_PLL_STATUS :: TEST_STATUS [11:00] */
-#define BCHP_CLKGEN_PLL_MOCA_PLL_STATUS_TEST_STATUS_MASK 0x00000fff
-#define BCHP_CLKGEN_PLL_MOCA_PLL_STATUS_TEST_STATUS_SHIFT 0
-
-/***************************************************************************
- *PLL_RAAGA_PLL_CHANNEL_CTRL_CH_0 - PLL CHANNEL control CH 0
- ***************************************************************************/
-/* CLKGEN :: PLL_RAAGA_PLL_CHANNEL_CTRL_CH_0 :: reserved0 [31:11] */
-#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_0_reserved0_MASK 0xfffff800
-#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_0_reserved0_SHIFT 11
-
-/* CLKGEN :: PLL_RAAGA_PLL_CHANNEL_CTRL_CH_0 :: POST_DIVIDER_HOLD_CH0 [10:10] */
-#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_MASK 0x00000400
-#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_SHIFT 10
-#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_RAAGA_PLL_CHANNEL_CTRL_CH_0 :: PHASE_OFFSET_CH0 [09:09] */
-#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_MASK 0x00000200
-#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_SHIFT 9
-#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_RAAGA_PLL_CHANNEL_CTRL_CH_0 :: MDIV_CH0 [08:01] */
-#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_MASK 0x000001fe
-#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_SHIFT 1
-#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_DEFAULT 0x00000007
-
-/* CLKGEN :: PLL_RAAGA_PLL_CHANNEL_CTRL_CH_0 :: CLOCK_DIS_CH0 [00:00] */
-#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_MASK 0x00000001
-#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_SHIFT 0
-#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_DEFAULT 0x00000000
-
-/***************************************************************************
- *PLL_RAAGA_PLL_CHANNEL_CTRL_CH_1 - PLL CHANNEL control CH 1
- ***************************************************************************/
-/* CLKGEN :: PLL_RAAGA_PLL_CHANNEL_CTRL_CH_1 :: reserved0 [31:11] */
-#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_1_reserved0_MASK 0xfffff800
-#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_1_reserved0_SHIFT 11
-
-/* CLKGEN :: PLL_RAAGA_PLL_CHANNEL_CTRL_CH_1 :: POST_DIVIDER_HOLD_CH1 [10:10] */
-#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_MASK 0x00000400
-#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_SHIFT 10
-#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_RAAGA_PLL_CHANNEL_CTRL_CH_1 :: PHASE_OFFSET_CH1 [09:09] */
-#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_MASK 0x00000200
-#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_SHIFT 9
-#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_RAAGA_PLL_CHANNEL_CTRL_CH_1 :: MDIV_CH1 [08:01] */
-#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_MASK 0x000001fe
-#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_SHIFT 1
-#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_DEFAULT 0x00000007
-
-/* CLKGEN :: PLL_RAAGA_PLL_CHANNEL_CTRL_CH_1 :: CLOCK_DIS_CH1 [00:00] */
-#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_MASK 0x00000001
-#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_SHIFT 0
-#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_DEFAULT 0x00000000
-
-/***************************************************************************
- *PLL_RAAGA_PLL_CHANNEL_CTRL_CH_2 - PLL CHANNEL control CH 2
- ***************************************************************************/
-/* CLKGEN :: PLL_RAAGA_PLL_CHANNEL_CTRL_CH_2 :: reserved0 [31:11] */
-#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_2_reserved0_MASK 0xfffff800
-#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_2_reserved0_SHIFT 11
-
-/* CLKGEN :: PLL_RAAGA_PLL_CHANNEL_CTRL_CH_2 :: POST_DIVIDER_HOLD_CH2 [10:10] */
-#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_HOLD_CH2_MASK 0x00000400
-#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_HOLD_CH2_SHIFT 10
-#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_HOLD_CH2_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_RAAGA_PLL_CHANNEL_CTRL_CH_2 :: PHASE_OFFSET_CH2 [09:09] */
-#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_2_PHASE_OFFSET_CH2_MASK 0x00000200
-#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_2_PHASE_OFFSET_CH2_SHIFT 9
-#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_2_PHASE_OFFSET_CH2_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_RAAGA_PLL_CHANNEL_CTRL_CH_2 :: MDIV_CH2 [08:01] */
-#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_2_MDIV_CH2_MASK 0x000001fe
-#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_2_MDIV_CH2_SHIFT 1
-#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_2_MDIV_CH2_DEFAULT 0x0000000b
-
-/* CLKGEN :: PLL_RAAGA_PLL_CHANNEL_CTRL_CH_2 :: CLOCK_DIS_CH2 [00:00] */
-#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_2_CLOCK_DIS_CH2_MASK 0x00000001
-#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_2_CLOCK_DIS_CH2_SHIFT 0
-#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_2_CLOCK_DIS_CH2_DEFAULT 0x00000000
-
-/***************************************************************************
- *PLL_RAAGA_PLL_CHANNEL_CTRL_CH_3 - PLL CHANNEL control CH 3
- ***************************************************************************/
-/* CLKGEN :: PLL_RAAGA_PLL_CHANNEL_CTRL_CH_3 :: reserved0 [31:11] */
-#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_3_reserved0_MASK 0xfffff800
-#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_3_reserved0_SHIFT 11
-
-/* CLKGEN :: PLL_RAAGA_PLL_CHANNEL_CTRL_CH_3 :: POST_DIVIDER_HOLD_CH3 [10:10] */
-#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_HOLD_CH3_MASK 0x00000400
-#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_HOLD_CH3_SHIFT 10
-#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_HOLD_CH3_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_RAAGA_PLL_CHANNEL_CTRL_CH_3 :: PHASE_OFFSET_CH3 [09:09] */
-#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_3_PHASE_OFFSET_CH3_MASK 0x00000200
-#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_3_PHASE_OFFSET_CH3_SHIFT 9
-#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_3_PHASE_OFFSET_CH3_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_RAAGA_PLL_CHANNEL_CTRL_CH_3 :: MDIV_CH3 [08:01] */
-#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_3_MDIV_CH3_MASK 0x000001fe
-#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_3_MDIV_CH3_SHIFT 1
-#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_3_MDIV_CH3_DEFAULT 0x0000000b
-
-/* CLKGEN :: PLL_RAAGA_PLL_CHANNEL_CTRL_CH_3 :: CLOCK_DIS_CH3 [00:00] */
-#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_3_CLOCK_DIS_CH3_MASK 0x00000001
-#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_3_CLOCK_DIS_CH3_SHIFT 0
-#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_3_CLOCK_DIS_CH3_DEFAULT 0x00000000
-
-/***************************************************************************
- *PLL_RAAGA_PLL_CHANNEL_CTRL_CH_4 - PLL CHANNEL control CH 4
- ***************************************************************************/
-/* CLKGEN :: PLL_RAAGA_PLL_CHANNEL_CTRL_CH_4 :: reserved0 [31:11] */
-#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_4_reserved0_MASK 0xfffff800
-#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_4_reserved0_SHIFT 11
-
-/* CLKGEN :: PLL_RAAGA_PLL_CHANNEL_CTRL_CH_4 :: POST_DIVIDER_HOLD_CH4 [10:10] */
-#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_4_POST_DIVIDER_HOLD_CH4_MASK 0x00000400
-#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_4_POST_DIVIDER_HOLD_CH4_SHIFT 10
-#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_4_POST_DIVIDER_HOLD_CH4_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_RAAGA_PLL_CHANNEL_CTRL_CH_4 :: PHASE_OFFSET_CH4 [09:09] */
-#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_4_PHASE_OFFSET_CH4_MASK 0x00000200
-#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_4_PHASE_OFFSET_CH4_SHIFT 9
-#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_4_PHASE_OFFSET_CH4_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_RAAGA_PLL_CHANNEL_CTRL_CH_4 :: MDIV_CH4 [08:01] */
-#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_4_MDIV_CH4_MASK 0x000001fe
-#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_4_MDIV_CH4_SHIFT 1
-#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_4_MDIV_CH4_DEFAULT 0x00000064
-
-/* CLKGEN :: PLL_RAAGA_PLL_CHANNEL_CTRL_CH_4 :: CLOCK_DIS_CH4 [00:00] */
-#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_4_CLOCK_DIS_CH4_MASK 0x00000001
-#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_4_CLOCK_DIS_CH4_SHIFT 0
-#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_4_CLOCK_DIS_CH4_DEFAULT 0x00000001
-
-/***************************************************************************
- *PLL_RAAGA_PLL_DIV - Pre multiplier
- ***************************************************************************/
-/* CLKGEN :: PLL_RAAGA_PLL_DIV :: reserved0 [31:14] */
-#define BCHP_CLKGEN_PLL_RAAGA_PLL_DIV_reserved0_MASK 0xffffc000
-#define BCHP_CLKGEN_PLL_RAAGA_PLL_DIV_reserved0_SHIFT 14
-
-/* CLKGEN :: PLL_RAAGA_PLL_DIV :: PDIV [13:10] */
-#define BCHP_CLKGEN_PLL_RAAGA_PLL_DIV_PDIV_MASK 0x00003c00
-#define BCHP_CLKGEN_PLL_RAAGA_PLL_DIV_PDIV_SHIFT 10
-#define BCHP_CLKGEN_PLL_RAAGA_PLL_DIV_PDIV_DEFAULT 0x00000002
-
-/* CLKGEN :: PLL_RAAGA_PLL_DIV :: NDIV_INT [09:00] */
-#define BCHP_CLKGEN_PLL_RAAGA_PLL_DIV_NDIV_INT_MASK 0x000003ff
-#define BCHP_CLKGEN_PLL_RAAGA_PLL_DIV_NDIV_INT_SHIFT 0
-#define BCHP_CLKGEN_PLL_RAAGA_PLL_DIV_NDIV_INT_DEFAULT 0x0000008f
-
-/***************************************************************************
- *PLL_RAAGA_PLL_GAIN - PLL GAIN
- ***************************************************************************/
-/* CLKGEN :: PLL_RAAGA_PLL_GAIN :: reserved0 [31:10] */
-#define BCHP_CLKGEN_PLL_RAAGA_PLL_GAIN_reserved0_MASK 0xfffffc00
-#define BCHP_CLKGEN_PLL_RAAGA_PLL_GAIN_reserved0_SHIFT 10
-
-/* CLKGEN :: PLL_RAAGA_PLL_GAIN :: LOOP_GAIN_PROPORTIONAL_IN_PHASE [09:06] */
-#define BCHP_CLKGEN_PLL_RAAGA_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_MASK 0x000003c0
-#define BCHP_CLKGEN_PLL_RAAGA_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_SHIFT 6
-#define BCHP_CLKGEN_PLL_RAAGA_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_DEFAULT 0x00000005
-
-/* CLKGEN :: PLL_RAAGA_PLL_GAIN :: LOOP_GAIN_IN_FREQ [05:03] */
-#define BCHP_CLKGEN_PLL_RAAGA_PLL_GAIN_LOOP_GAIN_IN_FREQ_MASK 0x00000038
-#define BCHP_CLKGEN_PLL_RAAGA_PLL_GAIN_LOOP_GAIN_IN_FREQ_SHIFT 3
-#define BCHP_CLKGEN_PLL_RAAGA_PLL_GAIN_LOOP_GAIN_IN_FREQ_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_RAAGA_PLL_GAIN :: LOOP_GAIN_INTEGRATOR_IN_PHASE [02:00] */
-#define BCHP_CLKGEN_PLL_RAAGA_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_MASK 0x00000007
-#define BCHP_CLKGEN_PLL_RAAGA_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_SHIFT 0
-#define BCHP_CLKGEN_PLL_RAAGA_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_DEFAULT 0x00000002
-
-/***************************************************************************
- *PLL_RAAGA_PLL_LDO_PWRON - LDO Power on
- ***************************************************************************/
-/* CLKGEN :: PLL_RAAGA_PLL_LDO_PWRON :: reserved0 [31:01] */
-#define BCHP_CLKGEN_PLL_RAAGA_PLL_LDO_PWRON_reserved0_MASK 0xfffffffe
-#define BCHP_CLKGEN_PLL_RAAGA_PLL_LDO_PWRON_reserved0_SHIFT 1
-
-/* CLKGEN :: PLL_RAAGA_PLL_LDO_PWRON :: LDO_PWRON_PLL [00:00] */
-#define BCHP_CLKGEN_PLL_RAAGA_PLL_LDO_PWRON_LDO_PWRON_PLL_MASK 0x00000001
-#define BCHP_CLKGEN_PLL_RAAGA_PLL_LDO_PWRON_LDO_PWRON_PLL_SHIFT 0
-#define BCHP_CLKGEN_PLL_RAAGA_PLL_LDO_PWRON_LDO_PWRON_PLL_DEFAULT 0x00000001
-
-/***************************************************************************
- *PLL_RAAGA_PLL_LOCK_STATUS - Lock Status
- ***************************************************************************/
-/* CLKGEN :: PLL_RAAGA_PLL_LOCK_STATUS :: reserved0 [31:02] */
-#define BCHP_CLKGEN_PLL_RAAGA_PLL_LOCK_STATUS_reserved0_MASK 0xfffffffc
-#define BCHP_CLKGEN_PLL_RAAGA_PLL_LOCK_STATUS_reserved0_SHIFT 2
-
-/* CLKGEN :: PLL_RAAGA_PLL_LOCK_STATUS :: LOCK_LOST [01:01] */
-#define BCHP_CLKGEN_PLL_RAAGA_PLL_LOCK_STATUS_LOCK_LOST_MASK 0x00000002
-#define BCHP_CLKGEN_PLL_RAAGA_PLL_LOCK_STATUS_LOCK_LOST_SHIFT 1
-
-/* CLKGEN :: PLL_RAAGA_PLL_LOCK_STATUS :: LOCK [00:00] */
-#define BCHP_CLKGEN_PLL_RAAGA_PLL_LOCK_STATUS_LOCK_MASK 0x00000001
-#define BCHP_CLKGEN_PLL_RAAGA_PLL_LOCK_STATUS_LOCK_SHIFT 0
-
-/***************************************************************************
- *PLL_RAAGA_PLL_MISC - Mscellaneous control bus.
- ***************************************************************************/
-/* CLKGEN :: PLL_RAAGA_PLL_MISC :: VCO_RANGE [31:30] */
-#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_VCO_RANGE_MASK 0xc0000000
-#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_VCO_RANGE_SHIFT 30
-#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_VCO_RANGE_DEFAULT 0x00000002
-
-/* CLKGEN :: PLL_RAAGA_PLL_MISC :: VCO_FB_DIV2 [29:29] */
-#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_VCO_FB_DIV2_MASK 0x20000000
-#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_VCO_FB_DIV2_SHIFT 29
-#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_VCO_FB_DIV2_DEFAULT 0x00000001
-
-/* CLKGEN :: PLL_RAAGA_PLL_MISC :: STAT_UPDATE [28:28] */
-#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_STAT_UPDATE_MASK 0x10000000
-#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_STAT_UPDATE_SHIFT 28
-#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_STAT_UPDATE_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_RAAGA_PLL_MISC :: STAT_SELECT [27:25] */
-#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_STAT_SELECT_MASK 0x0e000000
-#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_STAT_SELECT_SHIFT 25
-#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_STAT_SELECT_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_RAAGA_PLL_MISC :: STAT_RESET [24:24] */
-#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_STAT_RESET_MASK 0x01000000
-#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_STAT_RESET_SHIFT 24
-#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_STAT_RESET_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_RAAGA_PLL_MISC :: STAT_MODE [23:22] */
-#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_STAT_MODE_MASK 0x00c00000
-#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_STAT_MODE_SHIFT 22
-#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_STAT_MODE_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_RAAGA_PLL_MISC :: PWM_RATE [21:20] */
-#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_PWM_RATE_MASK 0x00300000
-#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_PWM_RATE_SHIFT 20
-#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_PWM_RATE_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_RAAGA_PLL_MISC :: POST_CTRL_RESETB [19:18] */
-#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_POST_CTRL_RESETB_MASK 0x000c0000
-#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_POST_CTRL_RESETB_SHIFT 18
-#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_POST_CTRL_RESETB_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_RAAGA_PLL_MISC :: PLLRESERVED2 [17:16] */
-#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_PLLRESERVED2_MASK 0x00030000
-#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_PLLRESERVED2_SHIFT 16
-#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_PLLRESERVED2_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_RAAGA_PLL_MISC :: PLLRESERVED1 [15:15] */
-#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_PLLRESERVED1_MASK 0x00008000
-#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_PLLRESERVED1_SHIFT 15
-#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_PLLRESERVED1_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_RAAGA_PLL_MISC :: NDIV_RELOCK [14:14] */
-#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_NDIV_RELOCK_MASK 0x00004000
-#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_NDIV_RELOCK_SHIFT 14
-#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_NDIV_RELOCK_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_RAAGA_PLL_MISC :: FAST_LOCK [13:13] */
-#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_FAST_LOCK_MASK 0x00002000
-#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_FAST_LOCK_SHIFT 13
-#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_FAST_LOCK_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_RAAGA_PLL_MISC :: DCO_CTRL_BYPASS_ENABLE [12:12] */
-#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_MASK 0x00001000
-#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_SHIFT 12
-#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_RAAGA_PLL_MISC :: DCO_CTRL_BYPASS [11:00] */
-#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_DCO_CTRL_BYPASS_MASK 0x00000fff
-#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_DCO_CTRL_BYPASS_SHIFT 0
-#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_DCO_CTRL_BYPASS_DEFAULT 0x00000000
-
-/***************************************************************************
- *PLL_RAAGA_PLL_MISC2 - Mscellaneous control bus continued.
- ***************************************************************************/
-/* CLKGEN :: PLL_RAAGA_PLL_MISC2 :: PLLRESERVED0 [31:02] */
-#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC2_PLLRESERVED0_MASK 0xfffffffc
-#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC2_PLLRESERVED0_SHIFT 2
-#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC2_PLLRESERVED0_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_RAAGA_PLL_MISC2 :: LDO [01:00] */
-#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC2_LDO_MASK 0x00000003
-#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC2_LDO_SHIFT 0
-#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC2_LDO_DEFAULT 0x00000001
-
-/***************************************************************************
- *PLL_RAAGA_PLL_PWRON - Poweron
- ***************************************************************************/
-/* CLKGEN :: PLL_RAAGA_PLL_PWRON :: reserved0 [31:01] */
-#define BCHP_CLKGEN_PLL_RAAGA_PLL_PWRON_reserved0_MASK 0xfffffffe
-#define BCHP_CLKGEN_PLL_RAAGA_PLL_PWRON_reserved0_SHIFT 1
-
-/* CLKGEN :: PLL_RAAGA_PLL_PWRON :: PWRON_PLL [00:00] */
-#define BCHP_CLKGEN_PLL_RAAGA_PLL_PWRON_PWRON_PLL_MASK 0x00000001
-#define BCHP_CLKGEN_PLL_RAAGA_PLL_PWRON_PWRON_PLL_SHIFT 0
-#define BCHP_CLKGEN_PLL_RAAGA_PLL_PWRON_PWRON_PLL_DEFAULT 0x00000001
-
-/***************************************************************************
- *PLL_RAAGA_PLL_RESET - Resets
- ***************************************************************************/
-/* CLKGEN :: PLL_RAAGA_PLL_RESET :: reserved0 [31:02] */
-#define BCHP_CLKGEN_PLL_RAAGA_PLL_RESET_reserved0_MASK 0xfffffffc
-#define BCHP_CLKGEN_PLL_RAAGA_PLL_RESET_reserved0_SHIFT 2
-
-/* CLKGEN :: PLL_RAAGA_PLL_RESET :: RESETD [01:01] */
-#define BCHP_CLKGEN_PLL_RAAGA_PLL_RESET_RESETD_MASK 0x00000002
-#define BCHP_CLKGEN_PLL_RAAGA_PLL_RESET_RESETD_SHIFT 1
-#define BCHP_CLKGEN_PLL_RAAGA_PLL_RESET_RESETD_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_RAAGA_PLL_RESET :: RESETA [00:00] */
-#define BCHP_CLKGEN_PLL_RAAGA_PLL_RESET_RESETA_MASK 0x00000001
-#define BCHP_CLKGEN_PLL_RAAGA_PLL_RESET_RESETA_SHIFT 0
-#define BCHP_CLKGEN_PLL_RAAGA_PLL_RESET_RESETA_DEFAULT 0x00000000
-
-/***************************************************************************
- *PLL_RAAGA_PLL_SSC_MODE_CONTROL_HIGH - Higher bits of Spread Spectrum mode control
- ***************************************************************************/
-/* CLKGEN :: PLL_RAAGA_PLL_SSC_MODE_CONTROL_HIGH :: reserved0 [31:16] */
-#define BCHP_CLKGEN_PLL_RAAGA_PLL_SSC_MODE_CONTROL_HIGH_reserved0_MASK 0xffff0000
-#define BCHP_CLKGEN_PLL_RAAGA_PLL_SSC_MODE_CONTROL_HIGH_reserved0_SHIFT 16
-
-/* CLKGEN :: PLL_RAAGA_PLL_SSC_MODE_CONTROL_HIGH :: SSC_STEP [15:00] */
-#define BCHP_CLKGEN_PLL_RAAGA_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_MASK 0x0000ffff
-#define BCHP_CLKGEN_PLL_RAAGA_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_SHIFT 0
-#define BCHP_CLKGEN_PLL_RAAGA_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *PLL_RAAGA_PLL_SSC_MODE_CONTROL_LOW - Lower bits of Spread Spectrum mode control
- ***************************************************************************/
-/* CLKGEN :: PLL_RAAGA_PLL_SSC_MODE_CONTROL_LOW :: reserved0 [31:23] */
-#define BCHP_CLKGEN_PLL_RAAGA_PLL_SSC_MODE_CONTROL_LOW_reserved0_MASK 0xff800000
-#define BCHP_CLKGEN_PLL_RAAGA_PLL_SSC_MODE_CONTROL_LOW_reserved0_SHIFT 23
-
-/* CLKGEN :: PLL_RAAGA_PLL_SSC_MODE_CONTROL_LOW :: SSC_MODE [22:22] */
-#define BCHP_CLKGEN_PLL_RAAGA_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_MASK 0x00400000
-#define BCHP_CLKGEN_PLL_RAAGA_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_SHIFT 22
-#define BCHP_CLKGEN_PLL_RAAGA_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_RAAGA_PLL_SSC_MODE_CONTROL_LOW :: SSC_LIMIT [21:00] */
-#define BCHP_CLKGEN_PLL_RAAGA_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_MASK 0x003fffff
-#define BCHP_CLKGEN_PLL_RAAGA_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_SHIFT 0
-#define BCHP_CLKGEN_PLL_RAAGA_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_DEFAULT 0x00000000
-
-/***************************************************************************
- *PLL_RAAGA_PLL_STATUS - Status
- ***************************************************************************/
-/* CLKGEN :: PLL_RAAGA_PLL_STATUS :: reserved0 [31:12] */
-#define BCHP_CLKGEN_PLL_RAAGA_PLL_STATUS_reserved0_MASK 0xfffff000
-#define BCHP_CLKGEN_PLL_RAAGA_PLL_STATUS_reserved0_SHIFT 12
-
-/* CLKGEN :: PLL_RAAGA_PLL_STATUS :: TEST_STATUS [11:00] */
-#define BCHP_CLKGEN_PLL_RAAGA_PLL_STATUS_TEST_STATUS_MASK 0x00000fff
-#define BCHP_CLKGEN_PLL_RAAGA_PLL_STATUS_TEST_STATUS_SHIFT 0
-
-/***************************************************************************
- *PLL_SC0_PLL_CHANNEL_CTRL_CH_0 - PLL CHANNEL control CH 0
- ***************************************************************************/
-/* CLKGEN :: PLL_SC0_PLL_CHANNEL_CTRL_CH_0 :: reserved0 [31:11] */
-#define BCHP_CLKGEN_PLL_SC0_PLL_CHANNEL_CTRL_CH_0_reserved0_MASK 0xfffff800
-#define BCHP_CLKGEN_PLL_SC0_PLL_CHANNEL_CTRL_CH_0_reserved0_SHIFT 11
-
-/* CLKGEN :: PLL_SC0_PLL_CHANNEL_CTRL_CH_0 :: POST_DIVIDER_HOLD_CH0 [10:10] */
-#define BCHP_CLKGEN_PLL_SC0_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_MASK 0x00000400
-#define BCHP_CLKGEN_PLL_SC0_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_SHIFT 10
-#define BCHP_CLKGEN_PLL_SC0_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_SC0_PLL_CHANNEL_CTRL_CH_0 :: PHASE_OFFSET_CH0 [09:09] */
-#define BCHP_CLKGEN_PLL_SC0_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_MASK 0x00000200
-#define BCHP_CLKGEN_PLL_SC0_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_SHIFT 9
-#define BCHP_CLKGEN_PLL_SC0_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_SC0_PLL_CHANNEL_CTRL_CH_0 :: MDIV_CH0 [08:01] */
-#define BCHP_CLKGEN_PLL_SC0_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_MASK 0x000001fe
-#define BCHP_CLKGEN_PLL_SC0_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_SHIFT 1
-#define BCHP_CLKGEN_PLL_SC0_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_DEFAULT 0x00000030
-
-/* CLKGEN :: PLL_SC0_PLL_CHANNEL_CTRL_CH_0 :: CLOCK_DIS_CH0 [00:00] */
-#define BCHP_CLKGEN_PLL_SC0_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_MASK 0x00000001
-#define BCHP_CLKGEN_PLL_SC0_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_SHIFT 0
-#define BCHP_CLKGEN_PLL_SC0_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_DEFAULT 0x00000000
-
-/***************************************************************************
- *PLL_SC0_PLL_DIV - Pre multiplier
- ***************************************************************************/
-/* CLKGEN :: PLL_SC0_PLL_DIV :: reserved0 [31:14] */
-#define BCHP_CLKGEN_PLL_SC0_PLL_DIV_reserved0_MASK 0xffffc000
-#define BCHP_CLKGEN_PLL_SC0_PLL_DIV_reserved0_SHIFT 14
-
-/* CLKGEN :: PLL_SC0_PLL_DIV :: PDIV [13:10] */
-#define BCHP_CLKGEN_PLL_SC0_PLL_DIV_PDIV_MASK 0x00003c00
-#define BCHP_CLKGEN_PLL_SC0_PLL_DIV_PDIV_SHIFT 10
-#define BCHP_CLKGEN_PLL_SC0_PLL_DIV_PDIV_DEFAULT 0x00000002
-
-/* CLKGEN :: PLL_SC0_PLL_DIV :: NDIV_INT [09:00] */
-#define BCHP_CLKGEN_PLL_SC0_PLL_DIV_NDIV_INT_MASK 0x000003ff
-#define BCHP_CLKGEN_PLL_SC0_PLL_DIV_NDIV_INT_SHIFT 0
-#define BCHP_CLKGEN_PLL_SC0_PLL_DIV_NDIV_INT_DEFAULT 0x00000030
-
-/***************************************************************************
- *PLL_SC0_PLL_FRAC - Fractional
- ***************************************************************************/
-/* CLKGEN :: PLL_SC0_PLL_FRAC :: reserved0 [31:20] */
-#define BCHP_CLKGEN_PLL_SC0_PLL_FRAC_reserved0_MASK 0xfff00000
-#define BCHP_CLKGEN_PLL_SC0_PLL_FRAC_reserved0_SHIFT 20
-
-/* CLKGEN :: PLL_SC0_PLL_FRAC :: FRAC_CONTROL [19:00] */
-#define BCHP_CLKGEN_PLL_SC0_PLL_FRAC_FRAC_CONTROL_MASK 0x000fffff
-#define BCHP_CLKGEN_PLL_SC0_PLL_FRAC_FRAC_CONTROL_SHIFT 0
-#define BCHP_CLKGEN_PLL_SC0_PLL_FRAC_FRAC_CONTROL_DEFAULT 0x00000000
-
-/***************************************************************************
- *PLL_SC0_PLL_GAIN - PLL GAIN
- ***************************************************************************/
-/* CLKGEN :: PLL_SC0_PLL_GAIN :: reserved0 [31:10] */
-#define BCHP_CLKGEN_PLL_SC0_PLL_GAIN_reserved0_MASK 0xfffffc00
-#define BCHP_CLKGEN_PLL_SC0_PLL_GAIN_reserved0_SHIFT 10
-
-/* CLKGEN :: PLL_SC0_PLL_GAIN :: LOOP_GAIN_PROPORTIONAL_IN_PHASE [09:06] */
-#define BCHP_CLKGEN_PLL_SC0_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_MASK 0x000003c0
-#define BCHP_CLKGEN_PLL_SC0_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_SHIFT 6
-#define BCHP_CLKGEN_PLL_SC0_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_DEFAULT 0x00000005
-
-/* CLKGEN :: PLL_SC0_PLL_GAIN :: LOOP_GAIN_IN_FREQ [05:03] */
-#define BCHP_CLKGEN_PLL_SC0_PLL_GAIN_LOOP_GAIN_IN_FREQ_MASK 0x00000038
-#define BCHP_CLKGEN_PLL_SC0_PLL_GAIN_LOOP_GAIN_IN_FREQ_SHIFT 3
-#define BCHP_CLKGEN_PLL_SC0_PLL_GAIN_LOOP_GAIN_IN_FREQ_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_SC0_PLL_GAIN :: LOOP_GAIN_INTEGRATOR_IN_PHASE [02:00] */
-#define BCHP_CLKGEN_PLL_SC0_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_MASK 0x00000007
-#define BCHP_CLKGEN_PLL_SC0_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_SHIFT 0
-#define BCHP_CLKGEN_PLL_SC0_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_DEFAULT 0x00000002
-
-/***************************************************************************
- *PLL_SC0_PLL_LDO_PWRON - LDO Power on
- ***************************************************************************/
-/* CLKGEN :: PLL_SC0_PLL_LDO_PWRON :: reserved0 [31:01] */
-#define BCHP_CLKGEN_PLL_SC0_PLL_LDO_PWRON_reserved0_MASK 0xfffffffe
-#define BCHP_CLKGEN_PLL_SC0_PLL_LDO_PWRON_reserved0_SHIFT 1
-
-/* CLKGEN :: PLL_SC0_PLL_LDO_PWRON :: LDO_PWRON_PLL [00:00] */
-#define BCHP_CLKGEN_PLL_SC0_PLL_LDO_PWRON_LDO_PWRON_PLL_MASK 0x00000001
-#define BCHP_CLKGEN_PLL_SC0_PLL_LDO_PWRON_LDO_PWRON_PLL_SHIFT 0
-#define BCHP_CLKGEN_PLL_SC0_PLL_LDO_PWRON_LDO_PWRON_PLL_DEFAULT 0x00000001
-
-/***************************************************************************
- *PLL_SC0_PLL_LOCK_STATUS - Lock Status
- ***************************************************************************/
-/* CLKGEN :: PLL_SC0_PLL_LOCK_STATUS :: reserved0 [31:02] */
-#define BCHP_CLKGEN_PLL_SC0_PLL_LOCK_STATUS_reserved0_MASK 0xfffffffc
-#define BCHP_CLKGEN_PLL_SC0_PLL_LOCK_STATUS_reserved0_SHIFT 2
-
-/* CLKGEN :: PLL_SC0_PLL_LOCK_STATUS :: LOCK_LOST [01:01] */
-#define BCHP_CLKGEN_PLL_SC0_PLL_LOCK_STATUS_LOCK_LOST_MASK 0x00000002
-#define BCHP_CLKGEN_PLL_SC0_PLL_LOCK_STATUS_LOCK_LOST_SHIFT 1
-
-/* CLKGEN :: PLL_SC0_PLL_LOCK_STATUS :: LOCK [00:00] */
-#define BCHP_CLKGEN_PLL_SC0_PLL_LOCK_STATUS_LOCK_MASK 0x00000001
-#define BCHP_CLKGEN_PLL_SC0_PLL_LOCK_STATUS_LOCK_SHIFT 0
-
-/***************************************************************************
- *PLL_SC0_PLL_MISC - Mscellaneous control bus.
- ***************************************************************************/
-/* CLKGEN :: PLL_SC0_PLL_MISC :: VCO_RANGE [31:30] */
-#define BCHP_CLKGEN_PLL_SC0_PLL_MISC_VCO_RANGE_MASK 0xc0000000
-#define BCHP_CLKGEN_PLL_SC0_PLL_MISC_VCO_RANGE_SHIFT 30
-#define BCHP_CLKGEN_PLL_SC0_PLL_MISC_VCO_RANGE_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_SC0_PLL_MISC :: VCO_FB_DIV2 [29:29] */
-#define BCHP_CLKGEN_PLL_SC0_PLL_MISC_VCO_FB_DIV2_MASK 0x20000000
-#define BCHP_CLKGEN_PLL_SC0_PLL_MISC_VCO_FB_DIV2_SHIFT 29
-#define BCHP_CLKGEN_PLL_SC0_PLL_MISC_VCO_FB_DIV2_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_SC0_PLL_MISC :: STAT_UPDATE [28:28] */
-#define BCHP_CLKGEN_PLL_SC0_PLL_MISC_STAT_UPDATE_MASK 0x10000000
-#define BCHP_CLKGEN_PLL_SC0_PLL_MISC_STAT_UPDATE_SHIFT 28
-#define BCHP_CLKGEN_PLL_SC0_PLL_MISC_STAT_UPDATE_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_SC0_PLL_MISC :: STAT_SELECT [27:25] */
-#define BCHP_CLKGEN_PLL_SC0_PLL_MISC_STAT_SELECT_MASK 0x0e000000
-#define BCHP_CLKGEN_PLL_SC0_PLL_MISC_STAT_SELECT_SHIFT 25
-#define BCHP_CLKGEN_PLL_SC0_PLL_MISC_STAT_SELECT_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_SC0_PLL_MISC :: STAT_RESET [24:24] */
-#define BCHP_CLKGEN_PLL_SC0_PLL_MISC_STAT_RESET_MASK 0x01000000
-#define BCHP_CLKGEN_PLL_SC0_PLL_MISC_STAT_RESET_SHIFT 24
-#define BCHP_CLKGEN_PLL_SC0_PLL_MISC_STAT_RESET_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_SC0_PLL_MISC :: STAT_MODE [23:22] */
-#define BCHP_CLKGEN_PLL_SC0_PLL_MISC_STAT_MODE_MASK 0x00c00000
-#define BCHP_CLKGEN_PLL_SC0_PLL_MISC_STAT_MODE_SHIFT 22
-#define BCHP_CLKGEN_PLL_SC0_PLL_MISC_STAT_MODE_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_SC0_PLL_MISC :: PWM_RATE [21:20] */
-#define BCHP_CLKGEN_PLL_SC0_PLL_MISC_PWM_RATE_MASK 0x00300000
-#define BCHP_CLKGEN_PLL_SC0_PLL_MISC_PWM_RATE_SHIFT 20
-#define BCHP_CLKGEN_PLL_SC0_PLL_MISC_PWM_RATE_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_SC0_PLL_MISC :: POST_CTRL_RESETB [19:18] */
-#define BCHP_CLKGEN_PLL_SC0_PLL_MISC_POST_CTRL_RESETB_MASK 0x000c0000
-#define BCHP_CLKGEN_PLL_SC0_PLL_MISC_POST_CTRL_RESETB_SHIFT 18
-#define BCHP_CLKGEN_PLL_SC0_PLL_MISC_POST_CTRL_RESETB_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_SC0_PLL_MISC :: PLLRESERVED2 [17:16] */
-#define BCHP_CLKGEN_PLL_SC0_PLL_MISC_PLLRESERVED2_MASK 0x00030000
-#define BCHP_CLKGEN_PLL_SC0_PLL_MISC_PLLRESERVED2_SHIFT 16
-#define BCHP_CLKGEN_PLL_SC0_PLL_MISC_PLLRESERVED2_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_SC0_PLL_MISC :: PLLRESERVED1 [15:15] */
-#define BCHP_CLKGEN_PLL_SC0_PLL_MISC_PLLRESERVED1_MASK 0x00008000
-#define BCHP_CLKGEN_PLL_SC0_PLL_MISC_PLLRESERVED1_SHIFT 15
-#define BCHP_CLKGEN_PLL_SC0_PLL_MISC_PLLRESERVED1_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_SC0_PLL_MISC :: NDIV_RELOCK [14:14] */
-#define BCHP_CLKGEN_PLL_SC0_PLL_MISC_NDIV_RELOCK_MASK 0x00004000
-#define BCHP_CLKGEN_PLL_SC0_PLL_MISC_NDIV_RELOCK_SHIFT 14
-#define BCHP_CLKGEN_PLL_SC0_PLL_MISC_NDIV_RELOCK_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_SC0_PLL_MISC :: FAST_LOCK [13:13] */
-#define BCHP_CLKGEN_PLL_SC0_PLL_MISC_FAST_LOCK_MASK 0x00002000
-#define BCHP_CLKGEN_PLL_SC0_PLL_MISC_FAST_LOCK_SHIFT 13
-#define BCHP_CLKGEN_PLL_SC0_PLL_MISC_FAST_LOCK_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_SC0_PLL_MISC :: DCO_CTRL_BYPASS_ENABLE [12:12] */
-#define BCHP_CLKGEN_PLL_SC0_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_MASK 0x00001000
-#define BCHP_CLKGEN_PLL_SC0_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_SHIFT 12
-#define BCHP_CLKGEN_PLL_SC0_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_SC0_PLL_MISC :: DCO_CTRL_BYPASS [11:00] */
-#define BCHP_CLKGEN_PLL_SC0_PLL_MISC_DCO_CTRL_BYPASS_MASK 0x00000fff
-#define BCHP_CLKGEN_PLL_SC0_PLL_MISC_DCO_CTRL_BYPASS_SHIFT 0
-#define BCHP_CLKGEN_PLL_SC0_PLL_MISC_DCO_CTRL_BYPASS_DEFAULT 0x00000000
-
-/***************************************************************************
- *PLL_SC0_PLL_MISC2 - Mscellaneous control bus continued.
- ***************************************************************************/
-/* CLKGEN :: PLL_SC0_PLL_MISC2 :: PLLRESERVED0 [31:02] */
-#define BCHP_CLKGEN_PLL_SC0_PLL_MISC2_PLLRESERVED0_MASK 0xfffffffc
-#define BCHP_CLKGEN_PLL_SC0_PLL_MISC2_PLLRESERVED0_SHIFT 2
-#define BCHP_CLKGEN_PLL_SC0_PLL_MISC2_PLLRESERVED0_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_SC0_PLL_MISC2 :: LDO [01:00] */
-#define BCHP_CLKGEN_PLL_SC0_PLL_MISC2_LDO_MASK 0x00000003
-#define BCHP_CLKGEN_PLL_SC0_PLL_MISC2_LDO_SHIFT 0
-#define BCHP_CLKGEN_PLL_SC0_PLL_MISC2_LDO_DEFAULT 0x00000001
-
-/***************************************************************************
- *PLL_SC0_PLL_PWRON - Poweron
- ***************************************************************************/
-/* CLKGEN :: PLL_SC0_PLL_PWRON :: reserved0 [31:01] */
-#define BCHP_CLKGEN_PLL_SC0_PLL_PWRON_reserved0_MASK 0xfffffffe
-#define BCHP_CLKGEN_PLL_SC0_PLL_PWRON_reserved0_SHIFT 1
-
-/* CLKGEN :: PLL_SC0_PLL_PWRON :: PWRON_PLL [00:00] */
-#define BCHP_CLKGEN_PLL_SC0_PLL_PWRON_PWRON_PLL_MASK 0x00000001
-#define BCHP_CLKGEN_PLL_SC0_PLL_PWRON_PWRON_PLL_SHIFT 0
-#define BCHP_CLKGEN_PLL_SC0_PLL_PWRON_PWRON_PLL_DEFAULT 0x00000001
-
-/***************************************************************************
- *PLL_SC0_PLL_RESET - Resets
- ***************************************************************************/
-/* CLKGEN :: PLL_SC0_PLL_RESET :: reserved0 [31:02] */
-#define BCHP_CLKGEN_PLL_SC0_PLL_RESET_reserved0_MASK 0xfffffffc
-#define BCHP_CLKGEN_PLL_SC0_PLL_RESET_reserved0_SHIFT 2
-
-/* CLKGEN :: PLL_SC0_PLL_RESET :: RESETD [01:01] */
-#define BCHP_CLKGEN_PLL_SC0_PLL_RESET_RESETD_MASK 0x00000002
-#define BCHP_CLKGEN_PLL_SC0_PLL_RESET_RESETD_SHIFT 1
-#define BCHP_CLKGEN_PLL_SC0_PLL_RESET_RESETD_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_SC0_PLL_RESET :: RESETA [00:00] */
-#define BCHP_CLKGEN_PLL_SC0_PLL_RESET_RESETA_MASK 0x00000001
-#define BCHP_CLKGEN_PLL_SC0_PLL_RESET_RESETA_SHIFT 0
-#define BCHP_CLKGEN_PLL_SC0_PLL_RESET_RESETA_DEFAULT 0x00000000
-
-/***************************************************************************
- *PLL_SC0_PLL_SSC_MODE_CONTROL_HIGH - Higher bits of Spread Spectrum mode control
- ***************************************************************************/
-/* CLKGEN :: PLL_SC0_PLL_SSC_MODE_CONTROL_HIGH :: reserved0 [31:16] */
-#define BCHP_CLKGEN_PLL_SC0_PLL_SSC_MODE_CONTROL_HIGH_reserved0_MASK 0xffff0000
-#define BCHP_CLKGEN_PLL_SC0_PLL_SSC_MODE_CONTROL_HIGH_reserved0_SHIFT 16
-
-/* CLKGEN :: PLL_SC0_PLL_SSC_MODE_CONTROL_HIGH :: SSC_STEP [15:00] */
-#define BCHP_CLKGEN_PLL_SC0_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_MASK 0x0000ffff
-#define BCHP_CLKGEN_PLL_SC0_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_SHIFT 0
-#define BCHP_CLKGEN_PLL_SC0_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *PLL_SC0_PLL_SSC_MODE_CONTROL_LOW - Lower bits of Spread Spectrum mode control
- ***************************************************************************/
-/* CLKGEN :: PLL_SC0_PLL_SSC_MODE_CONTROL_LOW :: reserved0 [31:23] */
-#define BCHP_CLKGEN_PLL_SC0_PLL_SSC_MODE_CONTROL_LOW_reserved0_MASK 0xff800000
-#define BCHP_CLKGEN_PLL_SC0_PLL_SSC_MODE_CONTROL_LOW_reserved0_SHIFT 23
-
-/* CLKGEN :: PLL_SC0_PLL_SSC_MODE_CONTROL_LOW :: SSC_MODE [22:22] */
-#define BCHP_CLKGEN_PLL_SC0_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_MASK 0x00400000
-#define BCHP_CLKGEN_PLL_SC0_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_SHIFT 22
-#define BCHP_CLKGEN_PLL_SC0_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_SC0_PLL_SSC_MODE_CONTROL_LOW :: SSC_LIMIT [21:00] */
-#define BCHP_CLKGEN_PLL_SC0_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_MASK 0x003fffff
-#define BCHP_CLKGEN_PLL_SC0_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_SHIFT 0
-#define BCHP_CLKGEN_PLL_SC0_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_DEFAULT 0x00000000
-
-/***************************************************************************
- *PLL_SC0_PLL_STATUS - Status
- ***************************************************************************/
-/* CLKGEN :: PLL_SC0_PLL_STATUS :: reserved0 [31:12] */
-#define BCHP_CLKGEN_PLL_SC0_PLL_STATUS_reserved0_MASK 0xfffff000
-#define BCHP_CLKGEN_PLL_SC0_PLL_STATUS_reserved0_SHIFT 12
-
-/* CLKGEN :: PLL_SC0_PLL_STATUS :: TEST_STATUS [11:00] */
-#define BCHP_CLKGEN_PLL_SC0_PLL_STATUS_TEST_STATUS_MASK 0x00000fff
-#define BCHP_CLKGEN_PLL_SC0_PLL_STATUS_TEST_STATUS_SHIFT 0
-
-/***************************************************************************
- *PLL_SC1_PLL_CHANNEL_CTRL_CH_0 - PLL CHANNEL control CH 0
- ***************************************************************************/
-/* CLKGEN :: PLL_SC1_PLL_CHANNEL_CTRL_CH_0 :: reserved0 [31:11] */
-#define BCHP_CLKGEN_PLL_SC1_PLL_CHANNEL_CTRL_CH_0_reserved0_MASK 0xfffff800
-#define BCHP_CLKGEN_PLL_SC1_PLL_CHANNEL_CTRL_CH_0_reserved0_SHIFT 11
-
-/* CLKGEN :: PLL_SC1_PLL_CHANNEL_CTRL_CH_0 :: POST_DIVIDER_HOLD_CH0 [10:10] */
-#define BCHP_CLKGEN_PLL_SC1_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_MASK 0x00000400
-#define BCHP_CLKGEN_PLL_SC1_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_SHIFT 10
-#define BCHP_CLKGEN_PLL_SC1_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_SC1_PLL_CHANNEL_CTRL_CH_0 :: PHASE_OFFSET_CH0 [09:09] */
-#define BCHP_CLKGEN_PLL_SC1_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_MASK 0x00000200
-#define BCHP_CLKGEN_PLL_SC1_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_SHIFT 9
-#define BCHP_CLKGEN_PLL_SC1_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_SC1_PLL_CHANNEL_CTRL_CH_0 :: MDIV_CH0 [08:01] */
-#define BCHP_CLKGEN_PLL_SC1_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_MASK 0x000001fe
-#define BCHP_CLKGEN_PLL_SC1_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_SHIFT 1
-#define BCHP_CLKGEN_PLL_SC1_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_DEFAULT 0x00000030
-
-/* CLKGEN :: PLL_SC1_PLL_CHANNEL_CTRL_CH_0 :: CLOCK_DIS_CH0 [00:00] */
-#define BCHP_CLKGEN_PLL_SC1_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_MASK 0x00000001
-#define BCHP_CLKGEN_PLL_SC1_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_SHIFT 0
-#define BCHP_CLKGEN_PLL_SC1_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_DEFAULT 0x00000000
-
-/***************************************************************************
- *PLL_SC1_PLL_DIV - Pre multiplier
- ***************************************************************************/
-/* CLKGEN :: PLL_SC1_PLL_DIV :: reserved0 [31:14] */
-#define BCHP_CLKGEN_PLL_SC1_PLL_DIV_reserved0_MASK 0xffffc000
-#define BCHP_CLKGEN_PLL_SC1_PLL_DIV_reserved0_SHIFT 14
-
-/* CLKGEN :: PLL_SC1_PLL_DIV :: PDIV [13:10] */
-#define BCHP_CLKGEN_PLL_SC1_PLL_DIV_PDIV_MASK 0x00003c00
-#define BCHP_CLKGEN_PLL_SC1_PLL_DIV_PDIV_SHIFT 10
-#define BCHP_CLKGEN_PLL_SC1_PLL_DIV_PDIV_DEFAULT 0x00000002
-
-/* CLKGEN :: PLL_SC1_PLL_DIV :: NDIV_INT [09:00] */
-#define BCHP_CLKGEN_PLL_SC1_PLL_DIV_NDIV_INT_MASK 0x000003ff
-#define BCHP_CLKGEN_PLL_SC1_PLL_DIV_NDIV_INT_SHIFT 0
-#define BCHP_CLKGEN_PLL_SC1_PLL_DIV_NDIV_INT_DEFAULT 0x00000030
-
-/***************************************************************************
- *PLL_SC1_PLL_FRAC - Fractional
- ***************************************************************************/
-/* CLKGEN :: PLL_SC1_PLL_FRAC :: reserved0 [31:20] */
-#define BCHP_CLKGEN_PLL_SC1_PLL_FRAC_reserved0_MASK 0xfff00000
-#define BCHP_CLKGEN_PLL_SC1_PLL_FRAC_reserved0_SHIFT 20
-
-/* CLKGEN :: PLL_SC1_PLL_FRAC :: FRAC_CONTROL [19:00] */
-#define BCHP_CLKGEN_PLL_SC1_PLL_FRAC_FRAC_CONTROL_MASK 0x000fffff
-#define BCHP_CLKGEN_PLL_SC1_PLL_FRAC_FRAC_CONTROL_SHIFT 0
-#define BCHP_CLKGEN_PLL_SC1_PLL_FRAC_FRAC_CONTROL_DEFAULT 0x00000000
-
-/***************************************************************************
- *PLL_SC1_PLL_GAIN - PLL GAIN
- ***************************************************************************/
-/* CLKGEN :: PLL_SC1_PLL_GAIN :: reserved0 [31:10] */
-#define BCHP_CLKGEN_PLL_SC1_PLL_GAIN_reserved0_MASK 0xfffffc00
-#define BCHP_CLKGEN_PLL_SC1_PLL_GAIN_reserved0_SHIFT 10
-
-/* CLKGEN :: PLL_SC1_PLL_GAIN :: LOOP_GAIN_PROPORTIONAL_IN_PHASE [09:06] */
-#define BCHP_CLKGEN_PLL_SC1_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_MASK 0x000003c0
-#define BCHP_CLKGEN_PLL_SC1_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_SHIFT 6
-#define BCHP_CLKGEN_PLL_SC1_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_DEFAULT 0x00000005
-
-/* CLKGEN :: PLL_SC1_PLL_GAIN :: LOOP_GAIN_IN_FREQ [05:03] */
-#define BCHP_CLKGEN_PLL_SC1_PLL_GAIN_LOOP_GAIN_IN_FREQ_MASK 0x00000038
-#define BCHP_CLKGEN_PLL_SC1_PLL_GAIN_LOOP_GAIN_IN_FREQ_SHIFT 3
-#define BCHP_CLKGEN_PLL_SC1_PLL_GAIN_LOOP_GAIN_IN_FREQ_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_SC1_PLL_GAIN :: LOOP_GAIN_INTEGRATOR_IN_PHASE [02:00] */
-#define BCHP_CLKGEN_PLL_SC1_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_MASK 0x00000007
-#define BCHP_CLKGEN_PLL_SC1_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_SHIFT 0
-#define BCHP_CLKGEN_PLL_SC1_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_DEFAULT 0x00000002
-
-/***************************************************************************
- *PLL_SC1_PLL_LDO_PWRON - LDO Power on
- ***************************************************************************/
-/* CLKGEN :: PLL_SC1_PLL_LDO_PWRON :: reserved0 [31:01] */
-#define BCHP_CLKGEN_PLL_SC1_PLL_LDO_PWRON_reserved0_MASK 0xfffffffe
-#define BCHP_CLKGEN_PLL_SC1_PLL_LDO_PWRON_reserved0_SHIFT 1
-
-/* CLKGEN :: PLL_SC1_PLL_LDO_PWRON :: LDO_PWRON_PLL [00:00] */
-#define BCHP_CLKGEN_PLL_SC1_PLL_LDO_PWRON_LDO_PWRON_PLL_MASK 0x00000001
-#define BCHP_CLKGEN_PLL_SC1_PLL_LDO_PWRON_LDO_PWRON_PLL_SHIFT 0
-#define BCHP_CLKGEN_PLL_SC1_PLL_LDO_PWRON_LDO_PWRON_PLL_DEFAULT 0x00000001
-
-/***************************************************************************
- *PLL_SC1_PLL_LOCK_STATUS - Lock Status
- ***************************************************************************/
-/* CLKGEN :: PLL_SC1_PLL_LOCK_STATUS :: reserved0 [31:02] */
-#define BCHP_CLKGEN_PLL_SC1_PLL_LOCK_STATUS_reserved0_MASK 0xfffffffc
-#define BCHP_CLKGEN_PLL_SC1_PLL_LOCK_STATUS_reserved0_SHIFT 2
-
-/* CLKGEN :: PLL_SC1_PLL_LOCK_STATUS :: LOCK_LOST [01:01] */
-#define BCHP_CLKGEN_PLL_SC1_PLL_LOCK_STATUS_LOCK_LOST_MASK 0x00000002
-#define BCHP_CLKGEN_PLL_SC1_PLL_LOCK_STATUS_LOCK_LOST_SHIFT 1
-
-/* CLKGEN :: PLL_SC1_PLL_LOCK_STATUS :: LOCK [00:00] */
-#define BCHP_CLKGEN_PLL_SC1_PLL_LOCK_STATUS_LOCK_MASK 0x00000001
-#define BCHP_CLKGEN_PLL_SC1_PLL_LOCK_STATUS_LOCK_SHIFT 0
-
-/***************************************************************************
- *PLL_SC1_PLL_MISC - Mscellaneous control bus.
- ***************************************************************************/
-/* CLKGEN :: PLL_SC1_PLL_MISC :: VCO_RANGE [31:30] */
-#define BCHP_CLKGEN_PLL_SC1_PLL_MISC_VCO_RANGE_MASK 0xc0000000
-#define BCHP_CLKGEN_PLL_SC1_PLL_MISC_VCO_RANGE_SHIFT 30
-#define BCHP_CLKGEN_PLL_SC1_PLL_MISC_VCO_RANGE_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_SC1_PLL_MISC :: VCO_FB_DIV2 [29:29] */
-#define BCHP_CLKGEN_PLL_SC1_PLL_MISC_VCO_FB_DIV2_MASK 0x20000000
-#define BCHP_CLKGEN_PLL_SC1_PLL_MISC_VCO_FB_DIV2_SHIFT 29
-#define BCHP_CLKGEN_PLL_SC1_PLL_MISC_VCO_FB_DIV2_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_SC1_PLL_MISC :: STAT_UPDATE [28:28] */
-#define BCHP_CLKGEN_PLL_SC1_PLL_MISC_STAT_UPDATE_MASK 0x10000000
-#define BCHP_CLKGEN_PLL_SC1_PLL_MISC_STAT_UPDATE_SHIFT 28
-#define BCHP_CLKGEN_PLL_SC1_PLL_MISC_STAT_UPDATE_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_SC1_PLL_MISC :: STAT_SELECT [27:25] */
-#define BCHP_CLKGEN_PLL_SC1_PLL_MISC_STAT_SELECT_MASK 0x0e000000
-#define BCHP_CLKGEN_PLL_SC1_PLL_MISC_STAT_SELECT_SHIFT 25
-#define BCHP_CLKGEN_PLL_SC1_PLL_MISC_STAT_SELECT_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_SC1_PLL_MISC :: STAT_RESET [24:24] */
-#define BCHP_CLKGEN_PLL_SC1_PLL_MISC_STAT_RESET_MASK 0x01000000
-#define BCHP_CLKGEN_PLL_SC1_PLL_MISC_STAT_RESET_SHIFT 24
-#define BCHP_CLKGEN_PLL_SC1_PLL_MISC_STAT_RESET_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_SC1_PLL_MISC :: STAT_MODE [23:22] */
-#define BCHP_CLKGEN_PLL_SC1_PLL_MISC_STAT_MODE_MASK 0x00c00000
-#define BCHP_CLKGEN_PLL_SC1_PLL_MISC_STAT_MODE_SHIFT 22
-#define BCHP_CLKGEN_PLL_SC1_PLL_MISC_STAT_MODE_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_SC1_PLL_MISC :: PWM_RATE [21:20] */
-#define BCHP_CLKGEN_PLL_SC1_PLL_MISC_PWM_RATE_MASK 0x00300000
-#define BCHP_CLKGEN_PLL_SC1_PLL_MISC_PWM_RATE_SHIFT 20
-#define BCHP_CLKGEN_PLL_SC1_PLL_MISC_PWM_RATE_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_SC1_PLL_MISC :: POST_CTRL_RESETB [19:18] */
-#define BCHP_CLKGEN_PLL_SC1_PLL_MISC_POST_CTRL_RESETB_MASK 0x000c0000
-#define BCHP_CLKGEN_PLL_SC1_PLL_MISC_POST_CTRL_RESETB_SHIFT 18
-#define BCHP_CLKGEN_PLL_SC1_PLL_MISC_POST_CTRL_RESETB_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_SC1_PLL_MISC :: PLLRESERVED2 [17:16] */
-#define BCHP_CLKGEN_PLL_SC1_PLL_MISC_PLLRESERVED2_MASK 0x00030000
-#define BCHP_CLKGEN_PLL_SC1_PLL_MISC_PLLRESERVED2_SHIFT 16
-#define BCHP_CLKGEN_PLL_SC1_PLL_MISC_PLLRESERVED2_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_SC1_PLL_MISC :: PLLRESERVED1 [15:15] */
-#define BCHP_CLKGEN_PLL_SC1_PLL_MISC_PLLRESERVED1_MASK 0x00008000
-#define BCHP_CLKGEN_PLL_SC1_PLL_MISC_PLLRESERVED1_SHIFT 15
-#define BCHP_CLKGEN_PLL_SC1_PLL_MISC_PLLRESERVED1_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_SC1_PLL_MISC :: NDIV_RELOCK [14:14] */
-#define BCHP_CLKGEN_PLL_SC1_PLL_MISC_NDIV_RELOCK_MASK 0x00004000
-#define BCHP_CLKGEN_PLL_SC1_PLL_MISC_NDIV_RELOCK_SHIFT 14
-#define BCHP_CLKGEN_PLL_SC1_PLL_MISC_NDIV_RELOCK_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_SC1_PLL_MISC :: FAST_LOCK [13:13] */
-#define BCHP_CLKGEN_PLL_SC1_PLL_MISC_FAST_LOCK_MASK 0x00002000
-#define BCHP_CLKGEN_PLL_SC1_PLL_MISC_FAST_LOCK_SHIFT 13
-#define BCHP_CLKGEN_PLL_SC1_PLL_MISC_FAST_LOCK_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_SC1_PLL_MISC :: DCO_CTRL_BYPASS_ENABLE [12:12] */
-#define BCHP_CLKGEN_PLL_SC1_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_MASK 0x00001000
-#define BCHP_CLKGEN_PLL_SC1_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_SHIFT 12
-#define BCHP_CLKGEN_PLL_SC1_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_SC1_PLL_MISC :: DCO_CTRL_BYPASS [11:00] */
-#define BCHP_CLKGEN_PLL_SC1_PLL_MISC_DCO_CTRL_BYPASS_MASK 0x00000fff
-#define BCHP_CLKGEN_PLL_SC1_PLL_MISC_DCO_CTRL_BYPASS_SHIFT 0
-#define BCHP_CLKGEN_PLL_SC1_PLL_MISC_DCO_CTRL_BYPASS_DEFAULT 0x00000000
-
-/***************************************************************************
- *PLL_SC1_PLL_MISC2 - Mscellaneous control bus continued.
- ***************************************************************************/
-/* CLKGEN :: PLL_SC1_PLL_MISC2 :: PLLRESERVED0 [31:02] */
-#define BCHP_CLKGEN_PLL_SC1_PLL_MISC2_PLLRESERVED0_MASK 0xfffffffc
-#define BCHP_CLKGEN_PLL_SC1_PLL_MISC2_PLLRESERVED0_SHIFT 2
-#define BCHP_CLKGEN_PLL_SC1_PLL_MISC2_PLLRESERVED0_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_SC1_PLL_MISC2 :: LDO [01:00] */
-#define BCHP_CLKGEN_PLL_SC1_PLL_MISC2_LDO_MASK 0x00000003
-#define BCHP_CLKGEN_PLL_SC1_PLL_MISC2_LDO_SHIFT 0
-#define BCHP_CLKGEN_PLL_SC1_PLL_MISC2_LDO_DEFAULT 0x00000001
-
-/***************************************************************************
- *PLL_SC1_PLL_PWRON - Poweron
- ***************************************************************************/
-/* CLKGEN :: PLL_SC1_PLL_PWRON :: reserved0 [31:01] */
-#define BCHP_CLKGEN_PLL_SC1_PLL_PWRON_reserved0_MASK 0xfffffffe
-#define BCHP_CLKGEN_PLL_SC1_PLL_PWRON_reserved0_SHIFT 1
-
-/* CLKGEN :: PLL_SC1_PLL_PWRON :: PWRON_PLL [00:00] */
-#define BCHP_CLKGEN_PLL_SC1_PLL_PWRON_PWRON_PLL_MASK 0x00000001
-#define BCHP_CLKGEN_PLL_SC1_PLL_PWRON_PWRON_PLL_SHIFT 0
-#define BCHP_CLKGEN_PLL_SC1_PLL_PWRON_PWRON_PLL_DEFAULT 0x00000001
-
-/***************************************************************************
- *PLL_SC1_PLL_RESET - Resets
- ***************************************************************************/
-/* CLKGEN :: PLL_SC1_PLL_RESET :: reserved0 [31:02] */
-#define BCHP_CLKGEN_PLL_SC1_PLL_RESET_reserved0_MASK 0xfffffffc
-#define BCHP_CLKGEN_PLL_SC1_PLL_RESET_reserved0_SHIFT 2
-
-/* CLKGEN :: PLL_SC1_PLL_RESET :: RESETD [01:01] */
-#define BCHP_CLKGEN_PLL_SC1_PLL_RESET_RESETD_MASK 0x00000002
-#define BCHP_CLKGEN_PLL_SC1_PLL_RESET_RESETD_SHIFT 1
-#define BCHP_CLKGEN_PLL_SC1_PLL_RESET_RESETD_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_SC1_PLL_RESET :: RESETA [00:00] */
-#define BCHP_CLKGEN_PLL_SC1_PLL_RESET_RESETA_MASK 0x00000001
-#define BCHP_CLKGEN_PLL_SC1_PLL_RESET_RESETA_SHIFT 0
-#define BCHP_CLKGEN_PLL_SC1_PLL_RESET_RESETA_DEFAULT 0x00000000
-
-/***************************************************************************
- *PLL_SC1_PLL_SSC_MODE_CONTROL_HIGH - Higher bits of Spread Spectrum mode control
- ***************************************************************************/
-/* CLKGEN :: PLL_SC1_PLL_SSC_MODE_CONTROL_HIGH :: reserved0 [31:16] */
-#define BCHP_CLKGEN_PLL_SC1_PLL_SSC_MODE_CONTROL_HIGH_reserved0_MASK 0xffff0000
-#define BCHP_CLKGEN_PLL_SC1_PLL_SSC_MODE_CONTROL_HIGH_reserved0_SHIFT 16
-
-/* CLKGEN :: PLL_SC1_PLL_SSC_MODE_CONTROL_HIGH :: SSC_STEP [15:00] */
-#define BCHP_CLKGEN_PLL_SC1_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_MASK 0x0000ffff
-#define BCHP_CLKGEN_PLL_SC1_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_SHIFT 0
-#define BCHP_CLKGEN_PLL_SC1_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *PLL_SC1_PLL_SSC_MODE_CONTROL_LOW - Lower bits of Spread Spectrum mode control
- ***************************************************************************/
-/* CLKGEN :: PLL_SC1_PLL_SSC_MODE_CONTROL_LOW :: reserved0 [31:23] */
-#define BCHP_CLKGEN_PLL_SC1_PLL_SSC_MODE_CONTROL_LOW_reserved0_MASK 0xff800000
-#define BCHP_CLKGEN_PLL_SC1_PLL_SSC_MODE_CONTROL_LOW_reserved0_SHIFT 23
-
-/* CLKGEN :: PLL_SC1_PLL_SSC_MODE_CONTROL_LOW :: SSC_MODE [22:22] */
-#define BCHP_CLKGEN_PLL_SC1_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_MASK 0x00400000
-#define BCHP_CLKGEN_PLL_SC1_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_SHIFT 22
-#define BCHP_CLKGEN_PLL_SC1_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_SC1_PLL_SSC_MODE_CONTROL_LOW :: SSC_LIMIT [21:00] */
-#define BCHP_CLKGEN_PLL_SC1_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_MASK 0x003fffff
-#define BCHP_CLKGEN_PLL_SC1_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_SHIFT 0
-#define BCHP_CLKGEN_PLL_SC1_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_DEFAULT 0x00000000
-
-/***************************************************************************
- *PLL_SC1_PLL_STATUS - Status
- ***************************************************************************/
-/* CLKGEN :: PLL_SC1_PLL_STATUS :: reserved0 [31:12] */
-#define BCHP_CLKGEN_PLL_SC1_PLL_STATUS_reserved0_MASK 0xfffff000
-#define BCHP_CLKGEN_PLL_SC1_PLL_STATUS_reserved0_SHIFT 12
-
-/* CLKGEN :: PLL_SC1_PLL_STATUS :: TEST_STATUS [11:00] */
-#define BCHP_CLKGEN_PLL_SC1_PLL_STATUS_TEST_STATUS_MASK 0x00000fff
-#define BCHP_CLKGEN_PLL_SC1_PLL_STATUS_TEST_STATUS_SHIFT 0
-
-/***************************************************************************
- *PLL_SWITCH_PLL_CHANNEL_CTRL_CH_0 - PLL CHANNEL control CH 0
- ***************************************************************************/
-/* CLKGEN :: PLL_SWITCH_PLL_CHANNEL_CTRL_CH_0 :: reserved0 [31:11] */
-#define BCHP_CLKGEN_PLL_SWITCH_PLL_CHANNEL_CTRL_CH_0_reserved0_MASK 0xfffff800
-#define BCHP_CLKGEN_PLL_SWITCH_PLL_CHANNEL_CTRL_CH_0_reserved0_SHIFT 11
-
-/* CLKGEN :: PLL_SWITCH_PLL_CHANNEL_CTRL_CH_0 :: POST_DIVIDER_HOLD_CH0 [10:10] */
-#define BCHP_CLKGEN_PLL_SWITCH_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_MASK 0x00000400
-#define BCHP_CLKGEN_PLL_SWITCH_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_SHIFT 10
-#define BCHP_CLKGEN_PLL_SWITCH_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_SWITCH_PLL_CHANNEL_CTRL_CH_0 :: PHASE_OFFSET_CH0 [09:09] */
-#define BCHP_CLKGEN_PLL_SWITCH_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_MASK 0x00000200
-#define BCHP_CLKGEN_PLL_SWITCH_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_SHIFT 9
-#define BCHP_CLKGEN_PLL_SWITCH_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_SWITCH_PLL_CHANNEL_CTRL_CH_0 :: MDIV_CH0 [08:01] */
-#define BCHP_CLKGEN_PLL_SWITCH_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_MASK 0x000001fe
-#define BCHP_CLKGEN_PLL_SWITCH_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_SHIFT 1
-#define BCHP_CLKGEN_PLL_SWITCH_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_DEFAULT 0x0000005a
-
-/* CLKGEN :: PLL_SWITCH_PLL_CHANNEL_CTRL_CH_0 :: CLOCK_DIS_CH0 [00:00] */
-#define BCHP_CLKGEN_PLL_SWITCH_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_MASK 0x00000001
-#define BCHP_CLKGEN_PLL_SWITCH_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_SHIFT 0
-#define BCHP_CLKGEN_PLL_SWITCH_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_DEFAULT 0x00000000
-
-/***************************************************************************
- *PLL_SWITCH_PLL_CHANNEL_CTRL_CH_1 - PLL CHANNEL control CH 1
- ***************************************************************************/
-/* CLKGEN :: PLL_SWITCH_PLL_CHANNEL_CTRL_CH_1 :: reserved0 [31:11] */
-#define BCHP_CLKGEN_PLL_SWITCH_PLL_CHANNEL_CTRL_CH_1_reserved0_MASK 0xfffff800
-#define BCHP_CLKGEN_PLL_SWITCH_PLL_CHANNEL_CTRL_CH_1_reserved0_SHIFT 11
-
-/* CLKGEN :: PLL_SWITCH_PLL_CHANNEL_CTRL_CH_1 :: POST_DIVIDER_HOLD_CH1 [10:10] */
-#define BCHP_CLKGEN_PLL_SWITCH_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_MASK 0x00000400
-#define BCHP_CLKGEN_PLL_SWITCH_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_SHIFT 10
-#define BCHP_CLKGEN_PLL_SWITCH_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_SWITCH_PLL_CHANNEL_CTRL_CH_1 :: PHASE_OFFSET_CH1 [09:09] */
-#define BCHP_CLKGEN_PLL_SWITCH_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_MASK 0x00000200
-#define BCHP_CLKGEN_PLL_SWITCH_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_SHIFT 9
-#define BCHP_CLKGEN_PLL_SWITCH_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_SWITCH_PLL_CHANNEL_CTRL_CH_1 :: MDIV_CH1 [08:01] */
-#define BCHP_CLKGEN_PLL_SWITCH_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_MASK 0x000001fe
-#define BCHP_CLKGEN_PLL_SWITCH_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_SHIFT 1
-#define BCHP_CLKGEN_PLL_SWITCH_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_DEFAULT 0x00000009
-
-/* CLKGEN :: PLL_SWITCH_PLL_CHANNEL_CTRL_CH_1 :: CLOCK_DIS_CH1 [00:00] */
-#define BCHP_CLKGEN_PLL_SWITCH_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_MASK 0x00000001
-#define BCHP_CLKGEN_PLL_SWITCH_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_SHIFT 0
-#define BCHP_CLKGEN_PLL_SWITCH_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_DEFAULT 0x00000000
-
-/***************************************************************************
- *PLL_SWITCH_PLL_CHANNEL_CTRL_CH_3 - PLL CHANNEL control CH 3
- ***************************************************************************/
-/* CLKGEN :: PLL_SWITCH_PLL_CHANNEL_CTRL_CH_3 :: reserved0 [31:11] */
-#define BCHP_CLKGEN_PLL_SWITCH_PLL_CHANNEL_CTRL_CH_3_reserved0_MASK 0xfffff800
-#define BCHP_CLKGEN_PLL_SWITCH_PLL_CHANNEL_CTRL_CH_3_reserved0_SHIFT 11
-
-/* CLKGEN :: PLL_SWITCH_PLL_CHANNEL_CTRL_CH_3 :: POST_DIVIDER_HOLD_CH3 [10:10] */
-#define BCHP_CLKGEN_PLL_SWITCH_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_HOLD_CH3_MASK 0x00000400
-#define BCHP_CLKGEN_PLL_SWITCH_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_HOLD_CH3_SHIFT 10
-#define BCHP_CLKGEN_PLL_SWITCH_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_HOLD_CH3_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_SWITCH_PLL_CHANNEL_CTRL_CH_3 :: PHASE_OFFSET_CH3 [09:09] */
-#define BCHP_CLKGEN_PLL_SWITCH_PLL_CHANNEL_CTRL_CH_3_PHASE_OFFSET_CH3_MASK 0x00000200
-#define BCHP_CLKGEN_PLL_SWITCH_PLL_CHANNEL_CTRL_CH_3_PHASE_OFFSET_CH3_SHIFT 9
-#define BCHP_CLKGEN_PLL_SWITCH_PLL_CHANNEL_CTRL_CH_3_PHASE_OFFSET_CH3_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_SWITCH_PLL_CHANNEL_CTRL_CH_3 :: MDIV_CH3 [08:01] */
-#define BCHP_CLKGEN_PLL_SWITCH_PLL_CHANNEL_CTRL_CH_3_MDIV_CH3_MASK 0x000001fe
-#define BCHP_CLKGEN_PLL_SWITCH_PLL_CHANNEL_CTRL_CH_3_MDIV_CH3_SHIFT 1
-#define BCHP_CLKGEN_PLL_SWITCH_PLL_CHANNEL_CTRL_CH_3_MDIV_CH3_DEFAULT 0x00000005
-
-/* CLKGEN :: PLL_SWITCH_PLL_CHANNEL_CTRL_CH_3 :: CLOCK_DIS_CH3 [00:00] */
-#define BCHP_CLKGEN_PLL_SWITCH_PLL_CHANNEL_CTRL_CH_3_CLOCK_DIS_CH3_MASK 0x00000001
-#define BCHP_CLKGEN_PLL_SWITCH_PLL_CHANNEL_CTRL_CH_3_CLOCK_DIS_CH3_SHIFT 0
-#define BCHP_CLKGEN_PLL_SWITCH_PLL_CHANNEL_CTRL_CH_3_CLOCK_DIS_CH3_DEFAULT 0x00000000
-
-/***************************************************************************
- *PLL_SWITCH_PLL_DIV - Pre multiplier
- ***************************************************************************/
-/* CLKGEN :: PLL_SWITCH_PLL_DIV :: reserved0 [31:14] */
-#define BCHP_CLKGEN_PLL_SWITCH_PLL_DIV_reserved0_MASK 0xffffc000
-#define BCHP_CLKGEN_PLL_SWITCH_PLL_DIV_reserved0_SHIFT 14
-
-/* CLKGEN :: PLL_SWITCH_PLL_DIV :: PDIV [13:10] */
-#define BCHP_CLKGEN_PLL_SWITCH_PLL_DIV_PDIV_MASK 0x00003c00
-#define BCHP_CLKGEN_PLL_SWITCH_PLL_DIV_PDIV_SHIFT 10
-#define BCHP_CLKGEN_PLL_SWITCH_PLL_DIV_PDIV_DEFAULT 0x00000003
-
-/* CLKGEN :: PLL_SWITCH_PLL_DIV :: NDIV_INT [09:00] */
-#define BCHP_CLKGEN_PLL_SWITCH_PLL_DIV_NDIV_INT_MASK 0x000003ff
-#define BCHP_CLKGEN_PLL_SWITCH_PLL_DIV_NDIV_INT_SHIFT 0
-#define BCHP_CLKGEN_PLL_SWITCH_PLL_DIV_NDIV_INT_DEFAULT 0x0000007d
-
-/***************************************************************************
- *PLL_SWITCH_PLL_GAIN - PLL GAIN
- ***************************************************************************/
-/* CLKGEN :: PLL_SWITCH_PLL_GAIN :: reserved0 [31:10] */
-#define BCHP_CLKGEN_PLL_SWITCH_PLL_GAIN_reserved0_MASK 0xfffffc00
-#define BCHP_CLKGEN_PLL_SWITCH_PLL_GAIN_reserved0_SHIFT 10
-
-/* CLKGEN :: PLL_SWITCH_PLL_GAIN :: LOOP_GAIN_PROPORTIONAL_IN_PHASE [09:06] */
-#define BCHP_CLKGEN_PLL_SWITCH_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_MASK 0x000003c0
-#define BCHP_CLKGEN_PLL_SWITCH_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_SHIFT 6
-#define BCHP_CLKGEN_PLL_SWITCH_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_DEFAULT 0x00000005
-
-/* CLKGEN :: PLL_SWITCH_PLL_GAIN :: LOOP_GAIN_IN_FREQ [05:03] */
-#define BCHP_CLKGEN_PLL_SWITCH_PLL_GAIN_LOOP_GAIN_IN_FREQ_MASK 0x00000038
-#define BCHP_CLKGEN_PLL_SWITCH_PLL_GAIN_LOOP_GAIN_IN_FREQ_SHIFT 3
-#define BCHP_CLKGEN_PLL_SWITCH_PLL_GAIN_LOOP_GAIN_IN_FREQ_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_SWITCH_PLL_GAIN :: LOOP_GAIN_INTEGRATOR_IN_PHASE [02:00] */
-#define BCHP_CLKGEN_PLL_SWITCH_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_MASK 0x00000007
-#define BCHP_CLKGEN_PLL_SWITCH_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_SHIFT 0
-#define BCHP_CLKGEN_PLL_SWITCH_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_DEFAULT 0x00000002
-
-/***************************************************************************
- *PLL_SWITCH_PLL_LDO_PWRON - LDO Power on
- ***************************************************************************/
-/* CLKGEN :: PLL_SWITCH_PLL_LDO_PWRON :: reserved0 [31:01] */
-#define BCHP_CLKGEN_PLL_SWITCH_PLL_LDO_PWRON_reserved0_MASK 0xfffffffe
-#define BCHP_CLKGEN_PLL_SWITCH_PLL_LDO_PWRON_reserved0_SHIFT 1
-
-/* CLKGEN :: PLL_SWITCH_PLL_LDO_PWRON :: LDO_PWRON_PLL [00:00] */
-#define BCHP_CLKGEN_PLL_SWITCH_PLL_LDO_PWRON_LDO_PWRON_PLL_MASK 0x00000001
-#define BCHP_CLKGEN_PLL_SWITCH_PLL_LDO_PWRON_LDO_PWRON_PLL_SHIFT 0
-#define BCHP_CLKGEN_PLL_SWITCH_PLL_LDO_PWRON_LDO_PWRON_PLL_DEFAULT 0x00000001
-
-/***************************************************************************
- *PLL_SWITCH_PLL_LOCK_STATUS - Lock Status
- ***************************************************************************/
-/* CLKGEN :: PLL_SWITCH_PLL_LOCK_STATUS :: reserved0 [31:02] */
-#define BCHP_CLKGEN_PLL_SWITCH_PLL_LOCK_STATUS_reserved0_MASK 0xfffffffc
-#define BCHP_CLKGEN_PLL_SWITCH_PLL_LOCK_STATUS_reserved0_SHIFT 2
-
-/* CLKGEN :: PLL_SWITCH_PLL_LOCK_STATUS :: LOCK_LOST [01:01] */
-#define BCHP_CLKGEN_PLL_SWITCH_PLL_LOCK_STATUS_LOCK_LOST_MASK 0x00000002
-#define BCHP_CLKGEN_PLL_SWITCH_PLL_LOCK_STATUS_LOCK_LOST_SHIFT 1
-
-/* CLKGEN :: PLL_SWITCH_PLL_LOCK_STATUS :: LOCK [00:00] */
-#define BCHP_CLKGEN_PLL_SWITCH_PLL_LOCK_STATUS_LOCK_MASK 0x00000001
-#define BCHP_CLKGEN_PLL_SWITCH_PLL_LOCK_STATUS_LOCK_SHIFT 0
-
-/***************************************************************************
- *PLL_SWITCH_PLL_MISC - Mscellaneous control bus.
- ***************************************************************************/
-/* CLKGEN :: PLL_SWITCH_PLL_MISC :: VCO_RANGE [31:30] */
-#define BCHP_CLKGEN_PLL_SWITCH_PLL_MISC_VCO_RANGE_MASK 0xc0000000
-#define BCHP_CLKGEN_PLL_SWITCH_PLL_MISC_VCO_RANGE_SHIFT 30
-#define BCHP_CLKGEN_PLL_SWITCH_PLL_MISC_VCO_RANGE_DEFAULT 0x00000002
-
-/* CLKGEN :: PLL_SWITCH_PLL_MISC :: VCO_FB_DIV2 [29:29] */
-#define BCHP_CLKGEN_PLL_SWITCH_PLL_MISC_VCO_FB_DIV2_MASK 0x20000000
-#define BCHP_CLKGEN_PLL_SWITCH_PLL_MISC_VCO_FB_DIV2_SHIFT 29
-#define BCHP_CLKGEN_PLL_SWITCH_PLL_MISC_VCO_FB_DIV2_DEFAULT 0x00000001
-
-/* CLKGEN :: PLL_SWITCH_PLL_MISC :: STAT_UPDATE [28:28] */
-#define BCHP_CLKGEN_PLL_SWITCH_PLL_MISC_STAT_UPDATE_MASK 0x10000000
-#define BCHP_CLKGEN_PLL_SWITCH_PLL_MISC_STAT_UPDATE_SHIFT 28
-#define BCHP_CLKGEN_PLL_SWITCH_PLL_MISC_STAT_UPDATE_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_SWITCH_PLL_MISC :: STAT_SELECT [27:25] */
-#define BCHP_CLKGEN_PLL_SWITCH_PLL_MISC_STAT_SELECT_MASK 0x0e000000
-#define BCHP_CLKGEN_PLL_SWITCH_PLL_MISC_STAT_SELECT_SHIFT 25
-#define BCHP_CLKGEN_PLL_SWITCH_PLL_MISC_STAT_SELECT_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_SWITCH_PLL_MISC :: STAT_RESET [24:24] */
-#define BCHP_CLKGEN_PLL_SWITCH_PLL_MISC_STAT_RESET_MASK 0x01000000
-#define BCHP_CLKGEN_PLL_SWITCH_PLL_MISC_STAT_RESET_SHIFT 24
-#define BCHP_CLKGEN_PLL_SWITCH_PLL_MISC_STAT_RESET_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_SWITCH_PLL_MISC :: STAT_MODE [23:22] */
-#define BCHP_CLKGEN_PLL_SWITCH_PLL_MISC_STAT_MODE_MASK 0x00c00000
-#define BCHP_CLKGEN_PLL_SWITCH_PLL_MISC_STAT_MODE_SHIFT 22
-#define BCHP_CLKGEN_PLL_SWITCH_PLL_MISC_STAT_MODE_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_SWITCH_PLL_MISC :: PWM_RATE [21:20] */
-#define BCHP_CLKGEN_PLL_SWITCH_PLL_MISC_PWM_RATE_MASK 0x00300000
-#define BCHP_CLKGEN_PLL_SWITCH_PLL_MISC_PWM_RATE_SHIFT 20
-#define BCHP_CLKGEN_PLL_SWITCH_PLL_MISC_PWM_RATE_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_SWITCH_PLL_MISC :: POST_CTRL_RESETB [19:18] */
-#define BCHP_CLKGEN_PLL_SWITCH_PLL_MISC_POST_CTRL_RESETB_MASK 0x000c0000
-#define BCHP_CLKGEN_PLL_SWITCH_PLL_MISC_POST_CTRL_RESETB_SHIFT 18
-#define BCHP_CLKGEN_PLL_SWITCH_PLL_MISC_POST_CTRL_RESETB_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_SWITCH_PLL_MISC :: PLLRESERVED2 [17:16] */
-#define BCHP_CLKGEN_PLL_SWITCH_PLL_MISC_PLLRESERVED2_MASK 0x00030000
-#define BCHP_CLKGEN_PLL_SWITCH_PLL_MISC_PLLRESERVED2_SHIFT 16
-#define BCHP_CLKGEN_PLL_SWITCH_PLL_MISC_PLLRESERVED2_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_SWITCH_PLL_MISC :: PLLRESERVED1 [15:15] */
-#define BCHP_CLKGEN_PLL_SWITCH_PLL_MISC_PLLRESERVED1_MASK 0x00008000
-#define BCHP_CLKGEN_PLL_SWITCH_PLL_MISC_PLLRESERVED1_SHIFT 15
-#define BCHP_CLKGEN_PLL_SWITCH_PLL_MISC_PLLRESERVED1_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_SWITCH_PLL_MISC :: NDIV_RELOCK [14:14] */
-#define BCHP_CLKGEN_PLL_SWITCH_PLL_MISC_NDIV_RELOCK_MASK 0x00004000
-#define BCHP_CLKGEN_PLL_SWITCH_PLL_MISC_NDIV_RELOCK_SHIFT 14
-#define BCHP_CLKGEN_PLL_SWITCH_PLL_MISC_NDIV_RELOCK_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_SWITCH_PLL_MISC :: FAST_LOCK [13:13] */
-#define BCHP_CLKGEN_PLL_SWITCH_PLL_MISC_FAST_LOCK_MASK 0x00002000
-#define BCHP_CLKGEN_PLL_SWITCH_PLL_MISC_FAST_LOCK_SHIFT 13
-#define BCHP_CLKGEN_PLL_SWITCH_PLL_MISC_FAST_LOCK_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_SWITCH_PLL_MISC :: DCO_CTRL_BYPASS_ENABLE [12:12] */
-#define BCHP_CLKGEN_PLL_SWITCH_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_MASK 0x00001000
-#define BCHP_CLKGEN_PLL_SWITCH_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_SHIFT 12
-#define BCHP_CLKGEN_PLL_SWITCH_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_SWITCH_PLL_MISC :: DCO_CTRL_BYPASS [11:00] */
-#define BCHP_CLKGEN_PLL_SWITCH_PLL_MISC_DCO_CTRL_BYPASS_MASK 0x00000fff
-#define BCHP_CLKGEN_PLL_SWITCH_PLL_MISC_DCO_CTRL_BYPASS_SHIFT 0
-#define BCHP_CLKGEN_PLL_SWITCH_PLL_MISC_DCO_CTRL_BYPASS_DEFAULT 0x00000000
-
-/***************************************************************************
- *PLL_SWITCH_PLL_MISC2 - Mscellaneous control bus continued.
- ***************************************************************************/
-/* CLKGEN :: PLL_SWITCH_PLL_MISC2 :: PLLRESERVED0 [31:02] */
-#define BCHP_CLKGEN_PLL_SWITCH_PLL_MISC2_PLLRESERVED0_MASK 0xfffffffc
-#define BCHP_CLKGEN_PLL_SWITCH_PLL_MISC2_PLLRESERVED0_SHIFT 2
-#define BCHP_CLKGEN_PLL_SWITCH_PLL_MISC2_PLLRESERVED0_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_SWITCH_PLL_MISC2 :: LDO [01:00] */
-#define BCHP_CLKGEN_PLL_SWITCH_PLL_MISC2_LDO_MASK 0x00000003
-#define BCHP_CLKGEN_PLL_SWITCH_PLL_MISC2_LDO_SHIFT 0
-#define BCHP_CLKGEN_PLL_SWITCH_PLL_MISC2_LDO_DEFAULT 0x00000001
-
-/***************************************************************************
- *PLL_SWITCH_PLL_PWRON - Poweron
- ***************************************************************************/
-/* CLKGEN :: PLL_SWITCH_PLL_PWRON :: reserved0 [31:01] */
-#define BCHP_CLKGEN_PLL_SWITCH_PLL_PWRON_reserved0_MASK 0xfffffffe
-#define BCHP_CLKGEN_PLL_SWITCH_PLL_PWRON_reserved0_SHIFT 1
-
-/* CLKGEN :: PLL_SWITCH_PLL_PWRON :: PWRON_PLL [00:00] */
-#define BCHP_CLKGEN_PLL_SWITCH_PLL_PWRON_PWRON_PLL_MASK 0x00000001
-#define BCHP_CLKGEN_PLL_SWITCH_PLL_PWRON_PWRON_PLL_SHIFT 0
-#define BCHP_CLKGEN_PLL_SWITCH_PLL_PWRON_PWRON_PLL_DEFAULT 0x00000001
-
-/***************************************************************************
- *PLL_SWITCH_PLL_RESET - Resets
- ***************************************************************************/
-/* CLKGEN :: PLL_SWITCH_PLL_RESET :: reserved0 [31:02] */
-#define BCHP_CLKGEN_PLL_SWITCH_PLL_RESET_reserved0_MASK 0xfffffffc
-#define BCHP_CLKGEN_PLL_SWITCH_PLL_RESET_reserved0_SHIFT 2
-
-/* CLKGEN :: PLL_SWITCH_PLL_RESET :: RESETD [01:01] */
-#define BCHP_CLKGEN_PLL_SWITCH_PLL_RESET_RESETD_MASK 0x00000002
-#define BCHP_CLKGEN_PLL_SWITCH_PLL_RESET_RESETD_SHIFT 1
-#define BCHP_CLKGEN_PLL_SWITCH_PLL_RESET_RESETD_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_SWITCH_PLL_RESET :: RESETA [00:00] */
-#define BCHP_CLKGEN_PLL_SWITCH_PLL_RESET_RESETA_MASK 0x00000001
-#define BCHP_CLKGEN_PLL_SWITCH_PLL_RESET_RESETA_SHIFT 0
-#define BCHP_CLKGEN_PLL_SWITCH_PLL_RESET_RESETA_DEFAULT 0x00000000
-
-/***************************************************************************
- *PLL_SWITCH_PLL_SSC_MODE_CONTROL_HIGH - Higher bits of Spread Spectrum mode control
- ***************************************************************************/
-/* CLKGEN :: PLL_SWITCH_PLL_SSC_MODE_CONTROL_HIGH :: reserved0 [31:16] */
-#define BCHP_CLKGEN_PLL_SWITCH_PLL_SSC_MODE_CONTROL_HIGH_reserved0_MASK 0xffff0000
-#define BCHP_CLKGEN_PLL_SWITCH_PLL_SSC_MODE_CONTROL_HIGH_reserved0_SHIFT 16
-
-/* CLKGEN :: PLL_SWITCH_PLL_SSC_MODE_CONTROL_HIGH :: SSC_STEP [15:00] */
-#define BCHP_CLKGEN_PLL_SWITCH_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_MASK 0x0000ffff
-#define BCHP_CLKGEN_PLL_SWITCH_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_SHIFT 0
-#define BCHP_CLKGEN_PLL_SWITCH_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *PLL_SWITCH_PLL_SSC_MODE_CONTROL_LOW - Lower bits of Spread Spectrum mode control
- ***************************************************************************/
-/* CLKGEN :: PLL_SWITCH_PLL_SSC_MODE_CONTROL_LOW :: reserved0 [31:23] */
-#define BCHP_CLKGEN_PLL_SWITCH_PLL_SSC_MODE_CONTROL_LOW_reserved0_MASK 0xff800000
-#define BCHP_CLKGEN_PLL_SWITCH_PLL_SSC_MODE_CONTROL_LOW_reserved0_SHIFT 23
-
-/* CLKGEN :: PLL_SWITCH_PLL_SSC_MODE_CONTROL_LOW :: SSC_MODE [22:22] */
-#define BCHP_CLKGEN_PLL_SWITCH_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_MASK 0x00400000
-#define BCHP_CLKGEN_PLL_SWITCH_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_SHIFT 22
-#define BCHP_CLKGEN_PLL_SWITCH_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_SWITCH_PLL_SSC_MODE_CONTROL_LOW :: SSC_LIMIT [21:00] */
-#define BCHP_CLKGEN_PLL_SWITCH_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_MASK 0x003fffff
-#define BCHP_CLKGEN_PLL_SWITCH_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_SHIFT 0
-#define BCHP_CLKGEN_PLL_SWITCH_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_DEFAULT 0x00000000
-
-/***************************************************************************
- *PLL_SWITCH_PLL_STATUS - Status
- ***************************************************************************/
-/* CLKGEN :: PLL_SWITCH_PLL_STATUS :: reserved0 [31:12] */
-#define BCHP_CLKGEN_PLL_SWITCH_PLL_STATUS_reserved0_MASK 0xfffff000
-#define BCHP_CLKGEN_PLL_SWITCH_PLL_STATUS_reserved0_SHIFT 12
-
-/* CLKGEN :: PLL_SWITCH_PLL_STATUS :: TEST_STATUS [11:00] */
-#define BCHP_CLKGEN_PLL_SWITCH_PLL_STATUS_TEST_STATUS_MASK 0x00000fff
-#define BCHP_CLKGEN_PLL_SWITCH_PLL_STATUS_TEST_STATUS_SHIFT 0
-
-/***************************************************************************
- *PLL_SYS0_PLL_BG_PWRON - Bandgap Power on
- ***************************************************************************/
-/* CLKGEN :: PLL_SYS0_PLL_BG_PWRON :: reserved0 [31:01] */
-#define BCHP_CLKGEN_PLL_SYS0_PLL_BG_PWRON_reserved0_MASK 0xfffffffe
-#define BCHP_CLKGEN_PLL_SYS0_PLL_BG_PWRON_reserved0_SHIFT 1
-
-/* CLKGEN :: PLL_SYS0_PLL_BG_PWRON :: BG_PWRON_PLL [00:00] */
-#define BCHP_CLKGEN_PLL_SYS0_PLL_BG_PWRON_BG_PWRON_PLL_MASK 0x00000001
-#define BCHP_CLKGEN_PLL_SYS0_PLL_BG_PWRON_BG_PWRON_PLL_SHIFT 0
-#define BCHP_CLKGEN_PLL_SYS0_PLL_BG_PWRON_BG_PWRON_PLL_DEFAULT 0x00000001
-
-/***************************************************************************
- *PLL_SYS0_PLL_CHANNEL_CTRL_CH_0 - PLL CHANNEL control CH 0
- ***************************************************************************/
-/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_0 :: reserved0 [31:11] */
-#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_0_reserved0_MASK 0xfffff800
-#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_0_reserved0_SHIFT 11
-
-/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_0 :: POST_DIVIDER_HOLD_CH0 [10:10] */
-#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_MASK 0x00000400
-#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_SHIFT 10
-#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_0 :: PHASE_OFFSET_CH0 [09:09] */
-#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_MASK 0x00000200
-#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_SHIFT 9
-#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_0 :: MDIV_CH0 [08:01] */
-#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_MASK 0x000001fe
-#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_SHIFT 1
-#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_DEFAULT 0x00000012
-
-/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_0 :: CLOCK_DIS_CH0 [00:00] */
-#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_MASK 0x00000001
-#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_SHIFT 0
-#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_DEFAULT 0x00000000
-
-/***************************************************************************
- *PLL_SYS0_PLL_CHANNEL_CTRL_CH_1 - PLL CHANNEL control CH 1
- ***************************************************************************/
-/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_1 :: reserved0 [31:11] */
-#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_1_reserved0_MASK 0xfffff800
-#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_1_reserved0_SHIFT 11
-
-/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_1 :: POST_DIVIDER_HOLD_CH1 [10:10] */
-#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_MASK 0x00000400
-#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_SHIFT 10
-#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_1 :: PHASE_OFFSET_CH1 [09:09] */
-#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_MASK 0x00000200
-#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_SHIFT 9
-#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_1 :: MDIV_CH1 [08:01] */
-#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_MASK 0x000001fe
-#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_SHIFT 1
-#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_DEFAULT 0x0000000c
-
-/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_1 :: CLOCK_DIS_CH1 [00:00] */
-#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_MASK 0x00000001
-#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_SHIFT 0
-#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_DEFAULT 0x00000000
-
-/***************************************************************************
- *PLL_SYS0_PLL_CHANNEL_CTRL_CH_2 - PLL CHANNEL control CH 2
- ***************************************************************************/
-/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_2 :: reserved0 [31:11] */
-#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2_reserved0_MASK 0xfffff800
-#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2_reserved0_SHIFT 11
-
-/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_2 :: POST_DIVIDER_HOLD_CH2 [10:10] */
-#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_HOLD_CH2_MASK 0x00000400
-#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_HOLD_CH2_SHIFT 10
-#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_HOLD_CH2_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_2 :: PHASE_OFFSET_CH2 [09:09] */
-#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2_PHASE_OFFSET_CH2_MASK 0x00000200
-#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2_PHASE_OFFSET_CH2_SHIFT 9
-#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2_PHASE_OFFSET_CH2_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_2 :: MDIV_CH2 [08:01] */
-#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2_MDIV_CH2_MASK 0x000001fe
-#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2_MDIV_CH2_SHIFT 1
-#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2_MDIV_CH2_DEFAULT 0x0000000c
-
-/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_2 :: CLOCK_DIS_CH2 [00:00] */
-#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2_CLOCK_DIS_CH2_MASK 0x00000001
-#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2_CLOCK_DIS_CH2_SHIFT 0
-#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2_CLOCK_DIS_CH2_DEFAULT 0x00000000
-
-/***************************************************************************
- *PLL_SYS0_PLL_CHANNEL_CTRL_CH_3 - PLL CHANNEL control CH 3
- ***************************************************************************/
-/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_3 :: reserved0 [31:11] */
-#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3_reserved0_MASK 0xfffff800
-#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3_reserved0_SHIFT 11
-
-/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_3 :: POST_DIVIDER_HOLD_CH3 [10:10] */
-#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_HOLD_CH3_MASK 0x00000400
-#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_HOLD_CH3_SHIFT 10
-#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_HOLD_CH3_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_3 :: PHASE_OFFSET_CH3 [09:09] */
-#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3_PHASE_OFFSET_CH3_MASK 0x00000200
-#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3_PHASE_OFFSET_CH3_SHIFT 9
-#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3_PHASE_OFFSET_CH3_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_3 :: MDIV_CH3 [08:01] */
-#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3_MDIV_CH3_MASK 0x000001fe
-#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3_MDIV_CH3_SHIFT 1
-#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3_MDIV_CH3_DEFAULT 0x00000012
-
-/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_3 :: CLOCK_DIS_CH3 [00:00] */
-#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3_CLOCK_DIS_CH3_MASK 0x00000001
-#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3_CLOCK_DIS_CH3_SHIFT 0
-#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3_CLOCK_DIS_CH3_DEFAULT 0x00000000
-
-/***************************************************************************
- *PLL_SYS0_PLL_CHANNEL_CTRL_CH_4 - PLL CHANNEL control CH 4
- ***************************************************************************/
-/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_4 :: reserved0 [31:11] */
-#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_4_reserved0_MASK 0xfffff800
-#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_4_reserved0_SHIFT 11
-
-/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_4 :: POST_DIVIDER_HOLD_CH4 [10:10] */
-#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_4_POST_DIVIDER_HOLD_CH4_MASK 0x00000400
-#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_4_POST_DIVIDER_HOLD_CH4_SHIFT 10
-#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_4_POST_DIVIDER_HOLD_CH4_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_4 :: PHASE_OFFSET_CH4 [09:09] */
-#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_4_PHASE_OFFSET_CH4_MASK 0x00000200
-#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_4_PHASE_OFFSET_CH4_SHIFT 9
-#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_4_PHASE_OFFSET_CH4_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_4 :: MDIV_CH4 [08:01] */
-#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_4_MDIV_CH4_MASK 0x000001fe
-#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_4_MDIV_CH4_SHIFT 1
-#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_4_MDIV_CH4_DEFAULT 0x00000024
-
-/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_4 :: CLOCK_DIS_CH4 [00:00] */
-#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_4_CLOCK_DIS_CH4_MASK 0x00000001
-#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_4_CLOCK_DIS_CH4_SHIFT 0
-#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_4_CLOCK_DIS_CH4_DEFAULT 0x00000000
-
-/***************************************************************************
- *PLL_SYS0_PLL_CHANNEL_CTRL_CH_5 - PLL CHANNEL control CH 5
- ***************************************************************************/
-/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_5 :: reserved0 [31:11] */
-#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_5_reserved0_MASK 0xfffff800
-#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_5_reserved0_SHIFT 11
-
-/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_5 :: POST_DIVIDER_HOLD_CH5 [10:10] */
-#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_5_POST_DIVIDER_HOLD_CH5_MASK 0x00000400
-#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_5_POST_DIVIDER_HOLD_CH5_SHIFT 10
-#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_5_POST_DIVIDER_HOLD_CH5_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_5 :: PHASE_OFFSET_CH5 [09:09] */
-#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_5_PHASE_OFFSET_CH5_MASK 0x00000200
-#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_5_PHASE_OFFSET_CH5_SHIFT 9
-#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_5_PHASE_OFFSET_CH5_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_5 :: MDIV_CH5 [08:01] */
-#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_5_MDIV_CH5_MASK 0x000001fe
-#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_5_MDIV_CH5_SHIFT 1
-#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_5_MDIV_CH5_DEFAULT 0x00000012
-
-/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_5 :: CLOCK_DIS_CH5 [00:00] */
-#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_5_CLOCK_DIS_CH5_MASK 0x00000001
-#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_5_CLOCK_DIS_CH5_SHIFT 0
-#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_5_CLOCK_DIS_CH5_DEFAULT 0x00000000
-
-/***************************************************************************
- *PLL_SYS0_PLL_DIV - Pre multiplier
- ***************************************************************************/
-/* CLKGEN :: PLL_SYS0_PLL_DIV :: reserved0 [31:14] */
-#define BCHP_CLKGEN_PLL_SYS0_PLL_DIV_reserved0_MASK 0xffffc000
-#define BCHP_CLKGEN_PLL_SYS0_PLL_DIV_reserved0_SHIFT 14
-
-/* CLKGEN :: PLL_SYS0_PLL_DIV :: PDIV [13:10] */
-#define BCHP_CLKGEN_PLL_SYS0_PLL_DIV_PDIV_MASK 0x00003c00
-#define BCHP_CLKGEN_PLL_SYS0_PLL_DIV_PDIV_SHIFT 10
-#define BCHP_CLKGEN_PLL_SYS0_PLL_DIV_PDIV_DEFAULT 0x00000001
-
-/* CLKGEN :: PLL_SYS0_PLL_DIV :: NDIV_INT [09:00] */
-#define BCHP_CLKGEN_PLL_SYS0_PLL_DIV_NDIV_INT_MASK 0x000003ff
-#define BCHP_CLKGEN_PLL_SYS0_PLL_DIV_NDIV_INT_SHIFT 0
-#define BCHP_CLKGEN_PLL_SYS0_PLL_DIV_NDIV_INT_DEFAULT 0x00000048
-
-/***************************************************************************
- *PLL_SYS0_PLL_GAIN - PLL GAIN
- ***************************************************************************/
-/* CLKGEN :: PLL_SYS0_PLL_GAIN :: reserved0 [31:10] */
-#define BCHP_CLKGEN_PLL_SYS0_PLL_GAIN_reserved0_MASK 0xfffffc00
-#define BCHP_CLKGEN_PLL_SYS0_PLL_GAIN_reserved0_SHIFT 10
-
-/* CLKGEN :: PLL_SYS0_PLL_GAIN :: LOOP_GAIN_PROPORTIONAL_IN_PHASE [09:06] */
-#define BCHP_CLKGEN_PLL_SYS0_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_MASK 0x000003c0
-#define BCHP_CLKGEN_PLL_SYS0_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_SHIFT 6
-#define BCHP_CLKGEN_PLL_SYS0_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_DEFAULT 0x00000008
-
-/* CLKGEN :: PLL_SYS0_PLL_GAIN :: LOOP_GAIN_IN_FREQ [05:03] */
-#define BCHP_CLKGEN_PLL_SYS0_PLL_GAIN_LOOP_GAIN_IN_FREQ_MASK 0x00000038
-#define BCHP_CLKGEN_PLL_SYS0_PLL_GAIN_LOOP_GAIN_IN_FREQ_SHIFT 3
-#define BCHP_CLKGEN_PLL_SYS0_PLL_GAIN_LOOP_GAIN_IN_FREQ_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_SYS0_PLL_GAIN :: LOOP_GAIN_INTEGRATOR_IN_PHASE [02:00] */
-#define BCHP_CLKGEN_PLL_SYS0_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_MASK 0x00000007
-#define BCHP_CLKGEN_PLL_SYS0_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_SHIFT 0
-#define BCHP_CLKGEN_PLL_SYS0_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_DEFAULT 0x00000004
-
-/***************************************************************************
- *PLL_SYS0_PLL_HOLD_CH_ALL - Hold PLL all channels
- ***************************************************************************/
-/* CLKGEN :: PLL_SYS0_PLL_HOLD_CH_ALL :: reserved0 [31:01] */
-#define BCHP_CLKGEN_PLL_SYS0_PLL_HOLD_CH_ALL_reserved0_MASK 0xfffffffe
-#define BCHP_CLKGEN_PLL_SYS0_PLL_HOLD_CH_ALL_reserved0_SHIFT 1
-
-/* CLKGEN :: PLL_SYS0_PLL_HOLD_CH_ALL :: HOLD_CH_ALL [00:00] */
-#define BCHP_CLKGEN_PLL_SYS0_PLL_HOLD_CH_ALL_HOLD_CH_ALL_MASK 0x00000001
-#define BCHP_CLKGEN_PLL_SYS0_PLL_HOLD_CH_ALL_HOLD_CH_ALL_SHIFT 0
-#define BCHP_CLKGEN_PLL_SYS0_PLL_HOLD_CH_ALL_HOLD_CH_ALL_DEFAULT 0x00000000
-
-/***************************************************************************
- *PLL_SYS0_PLL_LDO_CTRL - Ldo voltage control
- ***************************************************************************/
-/* CLKGEN :: PLL_SYS0_PLL_LDO_CTRL :: reserved0 [31:16] */
-#define BCHP_CLKGEN_PLL_SYS0_PLL_LDO_CTRL_reserved0_MASK 0xffff0000
-#define BCHP_CLKGEN_PLL_SYS0_PLL_LDO_CTRL_reserved0_SHIFT 16
-
-/* CLKGEN :: PLL_SYS0_PLL_LDO_CTRL :: LDO_CTRL [15:00] */
-#define BCHP_CLKGEN_PLL_SYS0_PLL_LDO_CTRL_LDO_CTRL_MASK 0x0000ffff
-#define BCHP_CLKGEN_PLL_SYS0_PLL_LDO_CTRL_LDO_CTRL_SHIFT 0
-#define BCHP_CLKGEN_PLL_SYS0_PLL_LDO_CTRL_LDO_CTRL_DEFAULT 0x00000005
-
-/***************************************************************************
- *PLL_SYS0_PLL_LDO_PWRON - LDO Power on
- ***************************************************************************/
-/* CLKGEN :: PLL_SYS0_PLL_LDO_PWRON :: reserved0 [31:01] */
-#define BCHP_CLKGEN_PLL_SYS0_PLL_LDO_PWRON_reserved0_MASK 0xfffffffe
-#define BCHP_CLKGEN_PLL_SYS0_PLL_LDO_PWRON_reserved0_SHIFT 1
-
-/* CLKGEN :: PLL_SYS0_PLL_LDO_PWRON :: LDO_PWRON_PLL [00:00] */
-#define BCHP_CLKGEN_PLL_SYS0_PLL_LDO_PWRON_LDO_PWRON_PLL_MASK 0x00000001
-#define BCHP_CLKGEN_PLL_SYS0_PLL_LDO_PWRON_LDO_PWRON_PLL_SHIFT 0
-#define BCHP_CLKGEN_PLL_SYS0_PLL_LDO_PWRON_LDO_PWRON_PLL_DEFAULT 0x00000001
-
-/***************************************************************************
- *PLL_SYS0_PLL_LOCK_STATUS - Lock Status
- ***************************************************************************/
-/* CLKGEN :: PLL_SYS0_PLL_LOCK_STATUS :: reserved0 [31:02] */
-#define BCHP_CLKGEN_PLL_SYS0_PLL_LOCK_STATUS_reserved0_MASK 0xfffffffc
-#define BCHP_CLKGEN_PLL_SYS0_PLL_LOCK_STATUS_reserved0_SHIFT 2
-
-/* CLKGEN :: PLL_SYS0_PLL_LOCK_STATUS :: LOCK_LOST [01:01] */
-#define BCHP_CLKGEN_PLL_SYS0_PLL_LOCK_STATUS_LOCK_LOST_MASK 0x00000002
-#define BCHP_CLKGEN_PLL_SYS0_PLL_LOCK_STATUS_LOCK_LOST_SHIFT 1
-
-/* CLKGEN :: PLL_SYS0_PLL_LOCK_STATUS :: LOCK [00:00] */
-#define BCHP_CLKGEN_PLL_SYS0_PLL_LOCK_STATUS_LOCK_MASK 0x00000001
-#define BCHP_CLKGEN_PLL_SYS0_PLL_LOCK_STATUS_LOCK_SHIFT 0
-
-/***************************************************************************
- *PLL_SYS0_PLL_MISC - Mscellaneous control bus.
- ***************************************************************************/
-/* CLKGEN :: PLL_SYS0_PLL_MISC :: VCO_RANGE_LOW [31:31] */
-#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_VCO_RANGE_LOW_MASK 0x80000000
-#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_VCO_RANGE_LOW_SHIFT 31
-#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_VCO_RANGE_LOW_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_SYS0_PLL_MISC :: VCO_RANGE_HIGH [30:30] */
-#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_VCO_RANGE_HIGH_MASK 0x40000000
-#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_VCO_RANGE_HIGH_SHIFT 30
-#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_VCO_RANGE_HIGH_DEFAULT 0x00000001
-
-/* CLKGEN :: PLL_SYS0_PLL_MISC :: VCO_DIV2 [29:29] */
-#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_VCO_DIV2_MASK 0x20000000
-#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_VCO_DIV2_SHIFT 29
-#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_VCO_DIV2_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_SYS0_PLL_MISC :: STAT_UPDATE [28:28] */
-#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_STAT_UPDATE_MASK 0x10000000
-#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_STAT_UPDATE_SHIFT 28
-#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_STAT_UPDATE_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_SYS0_PLL_MISC :: STAT_SELECT [27:25] */
-#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_STAT_SELECT_MASK 0x0e000000
-#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_STAT_SELECT_SHIFT 25
-#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_STAT_SELECT_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_SYS0_PLL_MISC :: STAT_RESET [24:24] */
-#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_STAT_RESET_MASK 0x01000000
-#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_STAT_RESET_SHIFT 24
-#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_STAT_RESET_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_SYS0_PLL_MISC :: STAT_MODE [23:22] */
-#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_STAT_MODE_MASK 0x00c00000
-#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_STAT_MODE_SHIFT 22
-#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_STAT_MODE_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_SYS0_PLL_MISC :: REF_ALT_OFFS [21:21] */
-#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_REF_ALT_OFFS_MASK 0x00200000
-#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_REF_ALT_OFFS_SHIFT 21
-#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_REF_ALT_OFFS_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_SYS0_PLL_MISC :: PWM_RATE [20:19] */
-#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_PWM_RATE_MASK 0x00180000
-#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_PWM_RATE_SHIFT 19
-#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_PWM_RATE_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_SYS0_PLL_MISC :: POST_CTRL_RESETB [18:17] */
-#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_POST_CTRL_RESETB_MASK 0x00060000
-#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_POST_CTRL_RESETB_SHIFT 17
-#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_POST_CTRL_RESETB_DEFAULT 0x00000003
-
-/* CLKGEN :: PLL_SYS0_PLL_MISC :: NDIV_RELOCK [16:16] */
-#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_NDIV_RELOCK_MASK 0x00010000
-#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_NDIV_RELOCK_SHIFT 16
-#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_NDIV_RELOCK_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_SYS0_PLL_MISC :: FAST_LOCK [15:15] */
-#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_FAST_LOCK_MASK 0x00008000
-#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_FAST_LOCK_SHIFT 15
-#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_FAST_LOCK_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_SYS0_PLL_MISC :: DITHER_DISABLE [14:14] */
-#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_DITHER_DISABLE_MASK 0x00004000
-#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_DITHER_DISABLE_SHIFT 14
-#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_DITHER_DISABLE_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_SYS0_PLL_MISC :: DCO_CTRL_BYPASS_ENABLE [13:13] */
-#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_MASK 0x00002000
-#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_SHIFT 13
-#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_SYS0_PLL_MISC :: DCO_CTRL_BYPASS [12:01] */
-#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_DCO_CTRL_BYPASS_MASK 0x00001ffe
-#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_DCO_CTRL_BYPASS_SHIFT 1
-#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_DCO_CTRL_BYPASS_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_SYS0_PLL_MISC :: AUX_CTRL [00:00] */
-#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_AUX_CTRL_MASK 0x00000001
-#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_AUX_CTRL_SHIFT 0
-#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_AUX_CTRL_DEFAULT 0x00000000
-
-/***************************************************************************
- *PLL_SYS0_PLL_MISC2 - Mscellaneous control bus continued.
- ***************************************************************************/
-/* CLKGEN :: PLL_SYS0_PLL_MISC2 :: PLLRESERVED0 [31:01] */
-#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC2_PLLRESERVED0_MASK 0xfffffffe
-#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC2_PLLRESERVED0_SHIFT 1
-#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC2_PLLRESERVED0_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_SYS0_PLL_MISC2 :: DIG_INPUT_SEL [00:00] */
-#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC2_DIG_INPUT_SEL_MASK 0x00000001
-#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC2_DIG_INPUT_SEL_SHIFT 0
-#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC2_DIG_INPUT_SEL_DEFAULT 0x00000000
-
-/***************************************************************************
- *PLL_SYS0_PLL_PWRON - Poweron
- ***************************************************************************/
-/* CLKGEN :: PLL_SYS0_PLL_PWRON :: reserved0 [31:01] */
-#define BCHP_CLKGEN_PLL_SYS0_PLL_PWRON_reserved0_MASK 0xfffffffe
-#define BCHP_CLKGEN_PLL_SYS0_PLL_PWRON_reserved0_SHIFT 1
-
-/* CLKGEN :: PLL_SYS0_PLL_PWRON :: PWRON_PLL [00:00] */
-#define BCHP_CLKGEN_PLL_SYS0_PLL_PWRON_PWRON_PLL_MASK 0x00000001
-#define BCHP_CLKGEN_PLL_SYS0_PLL_PWRON_PWRON_PLL_SHIFT 0
-#define BCHP_CLKGEN_PLL_SYS0_PLL_PWRON_PWRON_PLL_DEFAULT 0x00000001
-
-/***************************************************************************
- *PLL_SYS0_PLL_RESET - Resets
- ***************************************************************************/
-/* CLKGEN :: PLL_SYS0_PLL_RESET :: reserved0 [31:01] */
-#define BCHP_CLKGEN_PLL_SYS0_PLL_RESET_reserved0_MASK 0xfffffffe
-#define BCHP_CLKGEN_PLL_SYS0_PLL_RESET_reserved0_SHIFT 1
-
-/* CLKGEN :: PLL_SYS0_PLL_RESET :: RESETD [00:00] */
-#define BCHP_CLKGEN_PLL_SYS0_PLL_RESET_RESETD_MASK 0x00000001
-#define BCHP_CLKGEN_PLL_SYS0_PLL_RESET_RESETD_SHIFT 0
-#define BCHP_CLKGEN_PLL_SYS0_PLL_RESET_RESETD_DEFAULT 0x00000000
-
-/***************************************************************************
- *PLL_SYS0_PLL_SSC_MODE_CONTROL_HIGH - Higher bits of Spread Spectrum mode control
- ***************************************************************************/
-/* CLKGEN :: PLL_SYS0_PLL_SSC_MODE_CONTROL_HIGH :: reserved0 [31:16] */
-#define BCHP_CLKGEN_PLL_SYS0_PLL_SSC_MODE_CONTROL_HIGH_reserved0_MASK 0xffff0000
-#define BCHP_CLKGEN_PLL_SYS0_PLL_SSC_MODE_CONTROL_HIGH_reserved0_SHIFT 16
-
-/* CLKGEN :: PLL_SYS0_PLL_SSC_MODE_CONTROL_HIGH :: SSC_STEP [15:00] */
-#define BCHP_CLKGEN_PLL_SYS0_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_MASK 0x0000ffff
-#define BCHP_CLKGEN_PLL_SYS0_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_SHIFT 0
-#define BCHP_CLKGEN_PLL_SYS0_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *PLL_SYS0_PLL_SSC_MODE_CONTROL_LOW - Lower bits of Spread Spectrum mode control
- ***************************************************************************/
-/* CLKGEN :: PLL_SYS0_PLL_SSC_MODE_CONTROL_LOW :: reserved0 [31:23] */
-#define BCHP_CLKGEN_PLL_SYS0_PLL_SSC_MODE_CONTROL_LOW_reserved0_MASK 0xff800000
-#define BCHP_CLKGEN_PLL_SYS0_PLL_SSC_MODE_CONTROL_LOW_reserved0_SHIFT 23
-
-/* CLKGEN :: PLL_SYS0_PLL_SSC_MODE_CONTROL_LOW :: SSC_MODE [22:22] */
-#define BCHP_CLKGEN_PLL_SYS0_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_MASK 0x00400000
-#define BCHP_CLKGEN_PLL_SYS0_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_SHIFT 22
-#define BCHP_CLKGEN_PLL_SYS0_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_SYS0_PLL_SSC_MODE_CONTROL_LOW :: SSC_LIMIT [21:00] */
-#define BCHP_CLKGEN_PLL_SYS0_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_MASK 0x003fffff
-#define BCHP_CLKGEN_PLL_SYS0_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_SHIFT 0
-#define BCHP_CLKGEN_PLL_SYS0_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_DEFAULT 0x00000000
-
-/***************************************************************************
- *PLL_SYS0_PLL_STATUS - Status
- ***************************************************************************/
-/* CLKGEN :: PLL_SYS0_PLL_STATUS :: reserved0 [31:12] */
-#define BCHP_CLKGEN_PLL_SYS0_PLL_STATUS_reserved0_MASK 0xfffff000
-#define BCHP_CLKGEN_PLL_SYS0_PLL_STATUS_reserved0_SHIFT 12
-
-/* CLKGEN :: PLL_SYS0_PLL_STATUS :: TEST_STATUS [11:00] */
-#define BCHP_CLKGEN_PLL_SYS0_PLL_STATUS_TEST_STATUS_MASK 0x00000fff
-#define BCHP_CLKGEN_PLL_SYS0_PLL_STATUS_TEST_STATUS_SHIFT 0
-
-/***************************************************************************
- *PLL_VCXO0_PLL_BG_PWRON - Bandgap Power on
- ***************************************************************************/
-/* CLKGEN :: PLL_VCXO0_PLL_BG_PWRON :: reserved0 [31:01] */
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_BG_PWRON_reserved0_MASK 0xfffffffe
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_BG_PWRON_reserved0_SHIFT 1
-
-/* CLKGEN :: PLL_VCXO0_PLL_BG_PWRON :: BG_PWRON_PLL [00:00] */
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_BG_PWRON_BG_PWRON_PLL_MASK 0x00000001
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_BG_PWRON_BG_PWRON_PLL_SHIFT 0
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_BG_PWRON_BG_PWRON_PLL_DEFAULT 0x00000001
-
-/***************************************************************************
- *PLL_VCXO0_PLL_CHANNEL_CTRL_CH_0 - PLL CHANNEL control CH 0
- ***************************************************************************/
-/* CLKGEN :: PLL_VCXO0_PLL_CHANNEL_CTRL_CH_0 :: reserved0 [31:11] */
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_CHANNEL_CTRL_CH_0_reserved0_MASK 0xfffff800
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_CHANNEL_CTRL_CH_0_reserved0_SHIFT 11
-
-/* CLKGEN :: PLL_VCXO0_PLL_CHANNEL_CTRL_CH_0 :: POST_DIVIDER_HOLD_CH0 [10:10] */
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_MASK 0x00000400
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_SHIFT 10
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_VCXO0_PLL_CHANNEL_CTRL_CH_0 :: PHASE_OFFSET_CH0 [09:09] */
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_MASK 0x00000200
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_SHIFT 9
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_VCXO0_PLL_CHANNEL_CTRL_CH_0 :: MDIV_CH0 [08:01] */
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_MASK 0x000001fe
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_SHIFT 1
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_DEFAULT 0x00000040
-
-/* CLKGEN :: PLL_VCXO0_PLL_CHANNEL_CTRL_CH_0 :: CLOCK_DIS_CH0 [00:00] */
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_MASK 0x00000001
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_SHIFT 0
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_DEFAULT 0x00000000
-
-/***************************************************************************
- *PLL_VCXO0_PLL_CHANNEL_CTRL_CH_1 - PLL CHANNEL control CH 1
- ***************************************************************************/
-/* CLKGEN :: PLL_VCXO0_PLL_CHANNEL_CTRL_CH_1 :: reserved0 [31:11] */
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_CHANNEL_CTRL_CH_1_reserved0_MASK 0xfffff800
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_CHANNEL_CTRL_CH_1_reserved0_SHIFT 11
-
-/* CLKGEN :: PLL_VCXO0_PLL_CHANNEL_CTRL_CH_1 :: POST_DIVIDER_HOLD_CH1 [10:10] */
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_MASK 0x00000400
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_SHIFT 10
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_VCXO0_PLL_CHANNEL_CTRL_CH_1 :: PHASE_OFFSET_CH1 [09:09] */
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_MASK 0x00000200
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_SHIFT 9
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_VCXO0_PLL_CHANNEL_CTRL_CH_1 :: MDIV_CH1 [08:01] */
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_MASK 0x000001fe
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_SHIFT 1
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_DEFAULT 0x000000fa
-
-/* CLKGEN :: PLL_VCXO0_PLL_CHANNEL_CTRL_CH_1 :: CLOCK_DIS_CH1 [00:00] */
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_MASK 0x00000001
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_SHIFT 0
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_DEFAULT 0x00000000
-
-/***************************************************************************
- *PLL_VCXO0_PLL_CHANNEL_CTRL_CH_2 - PLL CHANNEL control CH 2
- ***************************************************************************/
-/* CLKGEN :: PLL_VCXO0_PLL_CHANNEL_CTRL_CH_2 :: reserved0 [31:11] */
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_CHANNEL_CTRL_CH_2_reserved0_MASK 0xfffff800
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_CHANNEL_CTRL_CH_2_reserved0_SHIFT 11
-
-/* CLKGEN :: PLL_VCXO0_PLL_CHANNEL_CTRL_CH_2 :: POST_DIVIDER_HOLD_CH2 [10:10] */
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_HOLD_CH2_MASK 0x00000400
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_HOLD_CH2_SHIFT 10
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_HOLD_CH2_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_VCXO0_PLL_CHANNEL_CTRL_CH_2 :: PHASE_OFFSET_CH2 [09:09] */
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_CHANNEL_CTRL_CH_2_PHASE_OFFSET_CH2_MASK 0x00000200
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_CHANNEL_CTRL_CH_2_PHASE_OFFSET_CH2_SHIFT 9
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_CHANNEL_CTRL_CH_2_PHASE_OFFSET_CH2_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_VCXO0_PLL_CHANNEL_CTRL_CH_2 :: MDIV_CH2 [08:01] */
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_CHANNEL_CTRL_CH_2_MDIV_CH2_MASK 0x000001fe
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_CHANNEL_CTRL_CH_2_MDIV_CH2_SHIFT 1
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_CHANNEL_CTRL_CH_2_MDIV_CH2_DEFAULT 0x0000007d
-
-/* CLKGEN :: PLL_VCXO0_PLL_CHANNEL_CTRL_CH_2 :: CLOCK_DIS_CH2 [00:00] */
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_CHANNEL_CTRL_CH_2_CLOCK_DIS_CH2_MASK 0x00000001
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_CHANNEL_CTRL_CH_2_CLOCK_DIS_CH2_SHIFT 0
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_CHANNEL_CTRL_CH_2_CLOCK_DIS_CH2_DEFAULT 0x00000000
-
-/***************************************************************************
- *PLL_VCXO0_PLL_DIV - Pre multiplier
- ***************************************************************************/
-/* CLKGEN :: PLL_VCXO0_PLL_DIV :: reserved0 [31:14] */
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_DIV_reserved0_MASK 0xffffc000
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_DIV_reserved0_SHIFT 14
-
-/* CLKGEN :: PLL_VCXO0_PLL_DIV :: PDIV [13:10] */
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_DIV_PDIV_MASK 0x00003c00
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_DIV_PDIV_SHIFT 10
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_DIV_PDIV_DEFAULT 0x00000002
-
-/* CLKGEN :: PLL_VCXO0_PLL_DIV :: NDIV_INT [09:00] */
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_DIV_NDIV_INT_MASK 0x000003ff
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_DIV_NDIV_INT_SHIFT 0
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_DIV_NDIV_INT_DEFAULT 0x00000040
-
-/***************************************************************************
- *PLL_VCXO0_PLL_FRAC - Fractional
- ***************************************************************************/
-/* CLKGEN :: PLL_VCXO0_PLL_FRAC :: reserved0 [31:20] */
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_FRAC_reserved0_MASK 0xfff00000
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_FRAC_reserved0_SHIFT 20
-
-/* CLKGEN :: PLL_VCXO0_PLL_FRAC :: FRAC_CONTROL [19:00] */
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_FRAC_FRAC_CONTROL_MASK 0x000fffff
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_FRAC_FRAC_CONTROL_SHIFT 0
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_FRAC_FRAC_CONTROL_DEFAULT 0x00000000
-
-/***************************************************************************
- *PLL_VCXO0_PLL_GAIN - PLL GAIN
- ***************************************************************************/
-/* CLKGEN :: PLL_VCXO0_PLL_GAIN :: reserved0 [31:10] */
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_GAIN_reserved0_MASK 0xfffffc00
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_GAIN_reserved0_SHIFT 10
-
-/* CLKGEN :: PLL_VCXO0_PLL_GAIN :: LOOP_GAIN_PROPORTIONAL_IN_PHASE [09:06] */
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_MASK 0x000003c0
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_SHIFT 6
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_DEFAULT 0x00000008
-
-/* CLKGEN :: PLL_VCXO0_PLL_GAIN :: LOOP_GAIN_IN_FREQ [05:03] */
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_GAIN_LOOP_GAIN_IN_FREQ_MASK 0x00000038
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_GAIN_LOOP_GAIN_IN_FREQ_SHIFT 3
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_GAIN_LOOP_GAIN_IN_FREQ_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_VCXO0_PLL_GAIN :: LOOP_GAIN_INTEGRATOR_IN_PHASE [02:00] */
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_MASK 0x00000007
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_SHIFT 0
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_DEFAULT 0x00000004
-
-/***************************************************************************
- *PLL_VCXO0_PLL_HOLD_CH_ALL - Hold PLL all channels
- ***************************************************************************/
-/* CLKGEN :: PLL_VCXO0_PLL_HOLD_CH_ALL :: reserved0 [31:01] */
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_HOLD_CH_ALL_reserved0_MASK 0xfffffffe
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_HOLD_CH_ALL_reserved0_SHIFT 1
-
-/* CLKGEN :: PLL_VCXO0_PLL_HOLD_CH_ALL :: HOLD_CH_ALL [00:00] */
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_HOLD_CH_ALL_HOLD_CH_ALL_MASK 0x00000001
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_HOLD_CH_ALL_HOLD_CH_ALL_SHIFT 0
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_HOLD_CH_ALL_HOLD_CH_ALL_DEFAULT 0x00000000
-
-/***************************************************************************
- *PLL_VCXO0_PLL_LDO_CTRL - Ldo voltage control
- ***************************************************************************/
-/* CLKGEN :: PLL_VCXO0_PLL_LDO_CTRL :: reserved0 [31:16] */
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_LDO_CTRL_reserved0_MASK 0xffff0000
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_LDO_CTRL_reserved0_SHIFT 16
-
-/* CLKGEN :: PLL_VCXO0_PLL_LDO_CTRL :: LDO_CTRL [15:00] */
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_LDO_CTRL_LDO_CTRL_MASK 0x0000ffff
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_LDO_CTRL_LDO_CTRL_SHIFT 0
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_LDO_CTRL_LDO_CTRL_DEFAULT 0x00000005
-
-/***************************************************************************
- *PLL_VCXO0_PLL_LDO_PWRON - LDO Power on
- ***************************************************************************/
-/* CLKGEN :: PLL_VCXO0_PLL_LDO_PWRON :: reserved0 [31:01] */
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_LDO_PWRON_reserved0_MASK 0xfffffffe
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_LDO_PWRON_reserved0_SHIFT 1
-
-/* CLKGEN :: PLL_VCXO0_PLL_LDO_PWRON :: LDO_PWRON_PLL [00:00] */
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_LDO_PWRON_LDO_PWRON_PLL_MASK 0x00000001
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_LDO_PWRON_LDO_PWRON_PLL_SHIFT 0
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_LDO_PWRON_LDO_PWRON_PLL_DEFAULT 0x00000001
-
-/***************************************************************************
- *PLL_VCXO0_PLL_LOCK_STATUS - Lock Status
- ***************************************************************************/
-/* CLKGEN :: PLL_VCXO0_PLL_LOCK_STATUS :: reserved0 [31:02] */
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_LOCK_STATUS_reserved0_MASK 0xfffffffc
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_LOCK_STATUS_reserved0_SHIFT 2
-
-/* CLKGEN :: PLL_VCXO0_PLL_LOCK_STATUS :: LOCK_LOST [01:01] */
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_LOCK_STATUS_LOCK_LOST_MASK 0x00000002
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_LOCK_STATUS_LOCK_LOST_SHIFT 1
-
-/* CLKGEN :: PLL_VCXO0_PLL_LOCK_STATUS :: LOCK [00:00] */
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_LOCK_STATUS_LOCK_MASK 0x00000001
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_LOCK_STATUS_LOCK_SHIFT 0
-
-/***************************************************************************
- *PLL_VCXO0_PLL_MISC - Mscellaneous control bus.
- ***************************************************************************/
-/* CLKGEN :: PLL_VCXO0_PLL_MISC :: VCO_RANGE_LOW [31:31] */
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_MISC_VCO_RANGE_LOW_MASK 0x80000000
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_MISC_VCO_RANGE_LOW_SHIFT 31
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_MISC_VCO_RANGE_LOW_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_VCXO0_PLL_MISC :: VCO_RANGE_HIGH [30:30] */
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_MISC_VCO_RANGE_HIGH_MASK 0x40000000
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_MISC_VCO_RANGE_HIGH_SHIFT 30
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_MISC_VCO_RANGE_HIGH_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_VCXO0_PLL_MISC :: VCO_DIV2 [29:29] */
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_MISC_VCO_DIV2_MASK 0x20000000
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_MISC_VCO_DIV2_SHIFT 29
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_MISC_VCO_DIV2_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_VCXO0_PLL_MISC :: STAT_UPDATE [28:28] */
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_MISC_STAT_UPDATE_MASK 0x10000000
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_MISC_STAT_UPDATE_SHIFT 28
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_MISC_STAT_UPDATE_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_VCXO0_PLL_MISC :: STAT_SELECT [27:25] */
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_MISC_STAT_SELECT_MASK 0x0e000000
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_MISC_STAT_SELECT_SHIFT 25
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_MISC_STAT_SELECT_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_VCXO0_PLL_MISC :: STAT_RESET [24:24] */
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_MISC_STAT_RESET_MASK 0x01000000
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_MISC_STAT_RESET_SHIFT 24
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_MISC_STAT_RESET_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_VCXO0_PLL_MISC :: STAT_MODE [23:22] */
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_MISC_STAT_MODE_MASK 0x00c00000
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_MISC_STAT_MODE_SHIFT 22
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_MISC_STAT_MODE_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_VCXO0_PLL_MISC :: REF_ALT_OFFS [21:21] */
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_MISC_REF_ALT_OFFS_MASK 0x00200000
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_MISC_REF_ALT_OFFS_SHIFT 21
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_MISC_REF_ALT_OFFS_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_VCXO0_PLL_MISC :: PWM_RATE [20:19] */
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_MISC_PWM_RATE_MASK 0x00180000
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_MISC_PWM_RATE_SHIFT 19
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_MISC_PWM_RATE_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_VCXO0_PLL_MISC :: POST_CTRL_RESETB [18:17] */
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_MISC_POST_CTRL_RESETB_MASK 0x00060000
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_MISC_POST_CTRL_RESETB_SHIFT 17
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_MISC_POST_CTRL_RESETB_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_VCXO0_PLL_MISC :: NDIV_RELOCK [16:16] */
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_MISC_NDIV_RELOCK_MASK 0x00010000
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_MISC_NDIV_RELOCK_SHIFT 16
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_MISC_NDIV_RELOCK_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_VCXO0_PLL_MISC :: FAST_LOCK [15:15] */
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_MISC_FAST_LOCK_MASK 0x00008000
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_MISC_FAST_LOCK_SHIFT 15
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_MISC_FAST_LOCK_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_VCXO0_PLL_MISC :: DITHER_DISABLE [14:14] */
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_MISC_DITHER_DISABLE_MASK 0x00004000
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_MISC_DITHER_DISABLE_SHIFT 14
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_MISC_DITHER_DISABLE_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_VCXO0_PLL_MISC :: DCO_CTRL_BYPASS_ENABLE [13:13] */
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_MASK 0x00002000
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_SHIFT 13
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_VCXO0_PLL_MISC :: DCO_CTRL_BYPASS [12:01] */
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_MISC_DCO_CTRL_BYPASS_MASK 0x00001ffe
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_MISC_DCO_CTRL_BYPASS_SHIFT 1
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_MISC_DCO_CTRL_BYPASS_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_VCXO0_PLL_MISC :: AUX_CTRL [00:00] */
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_MISC_AUX_CTRL_MASK 0x00000001
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_MISC_AUX_CTRL_SHIFT 0
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_MISC_AUX_CTRL_DEFAULT 0x00000000
-
-/***************************************************************************
- *PLL_VCXO0_PLL_MISC2 - Mscellaneous control bus continued.
- ***************************************************************************/
-/* CLKGEN :: PLL_VCXO0_PLL_MISC2 :: PLLRESERVED0 [31:01] */
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_MISC2_PLLRESERVED0_MASK 0xfffffffe
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_MISC2_PLLRESERVED0_SHIFT 1
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_MISC2_PLLRESERVED0_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_VCXO0_PLL_MISC2 :: DIG_INPUT_SEL [00:00] */
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_MISC2_DIG_INPUT_SEL_MASK 0x00000001
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_MISC2_DIG_INPUT_SEL_SHIFT 0
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_MISC2_DIG_INPUT_SEL_DEFAULT 0x00000000
-
-/***************************************************************************
- *PLL_VCXO0_PLL_PWRON - Poweron
- ***************************************************************************/
-/* CLKGEN :: PLL_VCXO0_PLL_PWRON :: reserved0 [31:01] */
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_PWRON_reserved0_MASK 0xfffffffe
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_PWRON_reserved0_SHIFT 1
-
-/* CLKGEN :: PLL_VCXO0_PLL_PWRON :: PWRON_PLL [00:00] */
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_PWRON_PWRON_PLL_MASK 0x00000001
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_PWRON_PWRON_PLL_SHIFT 0
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_PWRON_PWRON_PLL_DEFAULT 0x00000001
-
-/***************************************************************************
- *PLL_VCXO0_PLL_RESET - Resets
- ***************************************************************************/
-/* CLKGEN :: PLL_VCXO0_PLL_RESET :: reserved0 [31:02] */
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_RESET_reserved0_MASK 0xfffffffc
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_RESET_reserved0_SHIFT 2
-
-/* CLKGEN :: PLL_VCXO0_PLL_RESET :: RESETD [01:01] */
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_RESET_RESETD_MASK 0x00000002
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_RESET_RESETD_SHIFT 1
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_RESET_RESETD_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_VCXO0_PLL_RESET :: RESETA [00:00] */
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_RESET_RESETA_MASK 0x00000001
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_RESET_RESETA_SHIFT 0
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_RESET_RESETA_DEFAULT 0x00000000
-
-/***************************************************************************
- *PLL_VCXO0_PLL_SSC_MODE_CONTROL_HIGH - Higher bits of Spread Spectrum mode control
- ***************************************************************************/
-/* CLKGEN :: PLL_VCXO0_PLL_SSC_MODE_CONTROL_HIGH :: reserved0 [31:16] */
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_SSC_MODE_CONTROL_HIGH_reserved0_MASK 0xffff0000
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_SSC_MODE_CONTROL_HIGH_reserved0_SHIFT 16
-
-/* CLKGEN :: PLL_VCXO0_PLL_SSC_MODE_CONTROL_HIGH :: SSC_STEP [15:00] */
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_MASK 0x0000ffff
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_SHIFT 0
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *PLL_VCXO0_PLL_SSC_MODE_CONTROL_LOW - Lower bits of Spread Spectrum mode control
- ***************************************************************************/
-/* CLKGEN :: PLL_VCXO0_PLL_SSC_MODE_CONTROL_LOW :: reserved0 [31:23] */
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_SSC_MODE_CONTROL_LOW_reserved0_MASK 0xff800000
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_SSC_MODE_CONTROL_LOW_reserved0_SHIFT 23
-
-/* CLKGEN :: PLL_VCXO0_PLL_SSC_MODE_CONTROL_LOW :: SSC_MODE [22:22] */
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_MASK 0x00400000
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_SHIFT 22
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_VCXO0_PLL_SSC_MODE_CONTROL_LOW :: SSC_LIMIT [21:00] */
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_MASK 0x003fffff
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_SHIFT 0
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_DEFAULT 0x00000000
-
-/***************************************************************************
- *PLL_VCXO0_PLL_STATUS - Status
- ***************************************************************************/
-/* CLKGEN :: PLL_VCXO0_PLL_STATUS :: reserved0 [31:12] */
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_STATUS_reserved0_MASK 0xfffff000
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_STATUS_reserved0_SHIFT 12
-
-/* CLKGEN :: PLL_VCXO0_PLL_STATUS :: TEST_STATUS [11:00] */
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_STATUS_TEST_STATUS_MASK 0x00000fff
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_STATUS_TEST_STATUS_SHIFT 0
-
-/***************************************************************************
- *PLL_VCXO1_PLL_BG_PWRON - Bandgap Power on
- ***************************************************************************/
-/* CLKGEN :: PLL_VCXO1_PLL_BG_PWRON :: reserved0 [31:01] */
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_BG_PWRON_reserved0_MASK 0xfffffffe
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_BG_PWRON_reserved0_SHIFT 1
-
-/* CLKGEN :: PLL_VCXO1_PLL_BG_PWRON :: BG_PWRON_PLL [00:00] */
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_BG_PWRON_BG_PWRON_PLL_MASK 0x00000001
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_BG_PWRON_BG_PWRON_PLL_SHIFT 0
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_BG_PWRON_BG_PWRON_PLL_DEFAULT 0x00000001
-
-/***************************************************************************
- *PLL_VCXO1_PLL_CHANNEL_CTRL_CH_0 - PLL CHANNEL control CH 0
- ***************************************************************************/
-/* CLKGEN :: PLL_VCXO1_PLL_CHANNEL_CTRL_CH_0 :: reserved0 [31:11] */
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_CHANNEL_CTRL_CH_0_reserved0_MASK 0xfffff800
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_CHANNEL_CTRL_CH_0_reserved0_SHIFT 11
-
-/* CLKGEN :: PLL_VCXO1_PLL_CHANNEL_CTRL_CH_0 :: POST_DIVIDER_HOLD_CH0 [10:10] */
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_MASK 0x00000400
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_SHIFT 10
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_VCXO1_PLL_CHANNEL_CTRL_CH_0 :: PHASE_OFFSET_CH0 [09:09] */
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_MASK 0x00000200
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_SHIFT 9
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_VCXO1_PLL_CHANNEL_CTRL_CH_0 :: MDIV_CH0 [08:01] */
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_MASK 0x000001fe
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_SHIFT 1
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_DEFAULT 0x00000040
-
-/* CLKGEN :: PLL_VCXO1_PLL_CHANNEL_CTRL_CH_0 :: CLOCK_DIS_CH0 [00:00] */
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_MASK 0x00000001
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_SHIFT 0
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_DEFAULT 0x00000000
-
-/***************************************************************************
- *PLL_VCXO1_PLL_CHANNEL_CTRL_CH_1 - PLL CHANNEL control CH 1
- ***************************************************************************/
-/* CLKGEN :: PLL_VCXO1_PLL_CHANNEL_CTRL_CH_1 :: reserved0 [31:11] */
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_CHANNEL_CTRL_CH_1_reserved0_MASK 0xfffff800
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_CHANNEL_CTRL_CH_1_reserved0_SHIFT 11
-
-/* CLKGEN :: PLL_VCXO1_PLL_CHANNEL_CTRL_CH_1 :: POST_DIVIDER_HOLD_CH1 [10:10] */
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_MASK 0x00000400
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_SHIFT 10
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_VCXO1_PLL_CHANNEL_CTRL_CH_1 :: PHASE_OFFSET_CH1 [09:09] */
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_MASK 0x00000200
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_SHIFT 9
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_VCXO1_PLL_CHANNEL_CTRL_CH_1 :: MDIV_CH1 [08:01] */
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_MASK 0x000001fe
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_SHIFT 1
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_DEFAULT 0x000000fa
-
-/* CLKGEN :: PLL_VCXO1_PLL_CHANNEL_CTRL_CH_1 :: CLOCK_DIS_CH1 [00:00] */
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_MASK 0x00000001
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_SHIFT 0
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_DEFAULT 0x00000000
-
-/***************************************************************************
- *PLL_VCXO1_PLL_CHANNEL_CTRL_CH_2 - PLL CHANNEL control CH 2
- ***************************************************************************/
-/* CLKGEN :: PLL_VCXO1_PLL_CHANNEL_CTRL_CH_2 :: reserved0 [31:11] */
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_CHANNEL_CTRL_CH_2_reserved0_MASK 0xfffff800
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_CHANNEL_CTRL_CH_2_reserved0_SHIFT 11
-
-/* CLKGEN :: PLL_VCXO1_PLL_CHANNEL_CTRL_CH_2 :: POST_DIVIDER_HOLD_CH2 [10:10] */
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_HOLD_CH2_MASK 0x00000400
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_HOLD_CH2_SHIFT 10
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_HOLD_CH2_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_VCXO1_PLL_CHANNEL_CTRL_CH_2 :: PHASE_OFFSET_CH2 [09:09] */
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_CHANNEL_CTRL_CH_2_PHASE_OFFSET_CH2_MASK 0x00000200
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_CHANNEL_CTRL_CH_2_PHASE_OFFSET_CH2_SHIFT 9
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_CHANNEL_CTRL_CH_2_PHASE_OFFSET_CH2_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_VCXO1_PLL_CHANNEL_CTRL_CH_2 :: MDIV_CH2 [08:01] */
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_CHANNEL_CTRL_CH_2_MDIV_CH2_MASK 0x000001fe
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_CHANNEL_CTRL_CH_2_MDIV_CH2_SHIFT 1
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_CHANNEL_CTRL_CH_2_MDIV_CH2_DEFAULT 0x0000007d
-
-/* CLKGEN :: PLL_VCXO1_PLL_CHANNEL_CTRL_CH_2 :: CLOCK_DIS_CH2 [00:00] */
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_CHANNEL_CTRL_CH_2_CLOCK_DIS_CH2_MASK 0x00000001
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_CHANNEL_CTRL_CH_2_CLOCK_DIS_CH2_SHIFT 0
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_CHANNEL_CTRL_CH_2_CLOCK_DIS_CH2_DEFAULT 0x00000000
-
-/***************************************************************************
- *PLL_VCXO1_PLL_DIV - Pre multiplier
- ***************************************************************************/
-/* CLKGEN :: PLL_VCXO1_PLL_DIV :: reserved0 [31:14] */
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_DIV_reserved0_MASK 0xffffc000
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_DIV_reserved0_SHIFT 14
-
-/* CLKGEN :: PLL_VCXO1_PLL_DIV :: PDIV [13:10] */
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_DIV_PDIV_MASK 0x00003c00
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_DIV_PDIV_SHIFT 10
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_DIV_PDIV_DEFAULT 0x00000002
-
-/* CLKGEN :: PLL_VCXO1_PLL_DIV :: NDIV_INT [09:00] */
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_DIV_NDIV_INT_MASK 0x000003ff
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_DIV_NDIV_INT_SHIFT 0
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_DIV_NDIV_INT_DEFAULT 0x00000040
-
-/***************************************************************************
- *PLL_VCXO1_PLL_FRAC - Fractional
- ***************************************************************************/
-/* CLKGEN :: PLL_VCXO1_PLL_FRAC :: reserved0 [31:20] */
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_FRAC_reserved0_MASK 0xfff00000
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_FRAC_reserved0_SHIFT 20
-
-/* CLKGEN :: PLL_VCXO1_PLL_FRAC :: FRAC_CONTROL [19:00] */
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_FRAC_FRAC_CONTROL_MASK 0x000fffff
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_FRAC_FRAC_CONTROL_SHIFT 0
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_FRAC_FRAC_CONTROL_DEFAULT 0x00000000
-
-/***************************************************************************
- *PLL_VCXO1_PLL_GAIN - PLL GAIN
- ***************************************************************************/
-/* CLKGEN :: PLL_VCXO1_PLL_GAIN :: reserved0 [31:10] */
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_GAIN_reserved0_MASK 0xfffffc00
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_GAIN_reserved0_SHIFT 10
-
-/* CLKGEN :: PLL_VCXO1_PLL_GAIN :: LOOP_GAIN_PROPORTIONAL_IN_PHASE [09:06] */
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_MASK 0x000003c0
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_SHIFT 6
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_DEFAULT 0x00000008
-
-/* CLKGEN :: PLL_VCXO1_PLL_GAIN :: LOOP_GAIN_IN_FREQ [05:03] */
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_GAIN_LOOP_GAIN_IN_FREQ_MASK 0x00000038
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_GAIN_LOOP_GAIN_IN_FREQ_SHIFT 3
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_GAIN_LOOP_GAIN_IN_FREQ_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_VCXO1_PLL_GAIN :: LOOP_GAIN_INTEGRATOR_IN_PHASE [02:00] */
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_MASK 0x00000007
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_SHIFT 0
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_DEFAULT 0x00000004
-
-/***************************************************************************
- *PLL_VCXO1_PLL_HOLD_CH_ALL - Hold PLL all channels
- ***************************************************************************/
-/* CLKGEN :: PLL_VCXO1_PLL_HOLD_CH_ALL :: reserved0 [31:01] */
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_HOLD_CH_ALL_reserved0_MASK 0xfffffffe
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_HOLD_CH_ALL_reserved0_SHIFT 1
-
-/* CLKGEN :: PLL_VCXO1_PLL_HOLD_CH_ALL :: HOLD_CH_ALL [00:00] */
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_HOLD_CH_ALL_HOLD_CH_ALL_MASK 0x00000001
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_HOLD_CH_ALL_HOLD_CH_ALL_SHIFT 0
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_HOLD_CH_ALL_HOLD_CH_ALL_DEFAULT 0x00000000
-
-/***************************************************************************
- *PLL_VCXO1_PLL_LDO_CTRL - Ldo voltage control
- ***************************************************************************/
-/* CLKGEN :: PLL_VCXO1_PLL_LDO_CTRL :: reserved0 [31:16] */
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_LDO_CTRL_reserved0_MASK 0xffff0000
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_LDO_CTRL_reserved0_SHIFT 16
-
-/* CLKGEN :: PLL_VCXO1_PLL_LDO_CTRL :: LDO_CTRL [15:00] */
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_LDO_CTRL_LDO_CTRL_MASK 0x0000ffff
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_LDO_CTRL_LDO_CTRL_SHIFT 0
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_LDO_CTRL_LDO_CTRL_DEFAULT 0x00000005
-
-/***************************************************************************
- *PLL_VCXO1_PLL_LDO_PWRON - LDO Power on
- ***************************************************************************/
-/* CLKGEN :: PLL_VCXO1_PLL_LDO_PWRON :: reserved0 [31:01] */
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_LDO_PWRON_reserved0_MASK 0xfffffffe
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_LDO_PWRON_reserved0_SHIFT 1
-
-/* CLKGEN :: PLL_VCXO1_PLL_LDO_PWRON :: LDO_PWRON_PLL [00:00] */
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_LDO_PWRON_LDO_PWRON_PLL_MASK 0x00000001
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_LDO_PWRON_LDO_PWRON_PLL_SHIFT 0
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_LDO_PWRON_LDO_PWRON_PLL_DEFAULT 0x00000001
-
-/***************************************************************************
- *PLL_VCXO1_PLL_LOCK_STATUS - Lock Status
- ***************************************************************************/
-/* CLKGEN :: PLL_VCXO1_PLL_LOCK_STATUS :: reserved0 [31:02] */
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_LOCK_STATUS_reserved0_MASK 0xfffffffc
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_LOCK_STATUS_reserved0_SHIFT 2
-
-/* CLKGEN :: PLL_VCXO1_PLL_LOCK_STATUS :: LOCK_LOST [01:01] */
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_LOCK_STATUS_LOCK_LOST_MASK 0x00000002
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_LOCK_STATUS_LOCK_LOST_SHIFT 1
-
-/* CLKGEN :: PLL_VCXO1_PLL_LOCK_STATUS :: LOCK [00:00] */
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_LOCK_STATUS_LOCK_MASK 0x00000001
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_LOCK_STATUS_LOCK_SHIFT 0
-
-/***************************************************************************
- *PLL_VCXO1_PLL_MISC - Mscellaneous control bus.
- ***************************************************************************/
-/* CLKGEN :: PLL_VCXO1_PLL_MISC :: VCO_RANGE_LOW [31:31] */
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_MISC_VCO_RANGE_LOW_MASK 0x80000000
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_MISC_VCO_RANGE_LOW_SHIFT 31
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_MISC_VCO_RANGE_LOW_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_VCXO1_PLL_MISC :: VCO_RANGE_HIGH [30:30] */
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_MISC_VCO_RANGE_HIGH_MASK 0x40000000
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_MISC_VCO_RANGE_HIGH_SHIFT 30
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_MISC_VCO_RANGE_HIGH_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_VCXO1_PLL_MISC :: VCO_DIV2 [29:29] */
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_MISC_VCO_DIV2_MASK 0x20000000
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_MISC_VCO_DIV2_SHIFT 29
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_MISC_VCO_DIV2_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_VCXO1_PLL_MISC :: STAT_UPDATE [28:28] */
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_MISC_STAT_UPDATE_MASK 0x10000000
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_MISC_STAT_UPDATE_SHIFT 28
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_MISC_STAT_UPDATE_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_VCXO1_PLL_MISC :: STAT_SELECT [27:25] */
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_MISC_STAT_SELECT_MASK 0x0e000000
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_MISC_STAT_SELECT_SHIFT 25
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_MISC_STAT_SELECT_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_VCXO1_PLL_MISC :: STAT_RESET [24:24] */
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_MISC_STAT_RESET_MASK 0x01000000
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_MISC_STAT_RESET_SHIFT 24
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_MISC_STAT_RESET_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_VCXO1_PLL_MISC :: STAT_MODE [23:22] */
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_MISC_STAT_MODE_MASK 0x00c00000
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_MISC_STAT_MODE_SHIFT 22
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_MISC_STAT_MODE_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_VCXO1_PLL_MISC :: REF_ALT_OFFS [21:21] */
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_MISC_REF_ALT_OFFS_MASK 0x00200000
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_MISC_REF_ALT_OFFS_SHIFT 21
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_MISC_REF_ALT_OFFS_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_VCXO1_PLL_MISC :: PWM_RATE [20:19] */
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_MISC_PWM_RATE_MASK 0x00180000
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_MISC_PWM_RATE_SHIFT 19
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_MISC_PWM_RATE_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_VCXO1_PLL_MISC :: POST_CTRL_RESETB [18:17] */
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_MISC_POST_CTRL_RESETB_MASK 0x00060000
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_MISC_POST_CTRL_RESETB_SHIFT 17
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_MISC_POST_CTRL_RESETB_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_VCXO1_PLL_MISC :: NDIV_RELOCK [16:16] */
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_MISC_NDIV_RELOCK_MASK 0x00010000
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_MISC_NDIV_RELOCK_SHIFT 16
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_MISC_NDIV_RELOCK_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_VCXO1_PLL_MISC :: FAST_LOCK [15:15] */
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_MISC_FAST_LOCK_MASK 0x00008000
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_MISC_FAST_LOCK_SHIFT 15
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_MISC_FAST_LOCK_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_VCXO1_PLL_MISC :: DITHER_DISABLE [14:14] */
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_MISC_DITHER_DISABLE_MASK 0x00004000
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_MISC_DITHER_DISABLE_SHIFT 14
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_MISC_DITHER_DISABLE_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_VCXO1_PLL_MISC :: DCO_CTRL_BYPASS_ENABLE [13:13] */
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_MASK 0x00002000
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_SHIFT 13
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_VCXO1_PLL_MISC :: DCO_CTRL_BYPASS [12:01] */
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_MISC_DCO_CTRL_BYPASS_MASK 0x00001ffe
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_MISC_DCO_CTRL_BYPASS_SHIFT 1
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_MISC_DCO_CTRL_BYPASS_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_VCXO1_PLL_MISC :: AUX_CTRL [00:00] */
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_MISC_AUX_CTRL_MASK 0x00000001
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_MISC_AUX_CTRL_SHIFT 0
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_MISC_AUX_CTRL_DEFAULT 0x00000000
-
-/***************************************************************************
- *PLL_VCXO1_PLL_MISC2 - Mscellaneous control bus continued.
- ***************************************************************************/
-/* CLKGEN :: PLL_VCXO1_PLL_MISC2 :: PLLRESERVED0 [31:01] */
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_MISC2_PLLRESERVED0_MASK 0xfffffffe
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_MISC2_PLLRESERVED0_SHIFT 1
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_MISC2_PLLRESERVED0_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_VCXO1_PLL_MISC2 :: DIG_INPUT_SEL [00:00] */
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_MISC2_DIG_INPUT_SEL_MASK 0x00000001
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_MISC2_DIG_INPUT_SEL_SHIFT 0
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_MISC2_DIG_INPUT_SEL_DEFAULT 0x00000000
-
-/***************************************************************************
- *PLL_VCXO1_PLL_PWRON - Poweron
- ***************************************************************************/
-/* CLKGEN :: PLL_VCXO1_PLL_PWRON :: reserved0 [31:01] */
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_PWRON_reserved0_MASK 0xfffffffe
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_PWRON_reserved0_SHIFT 1
-
-/* CLKGEN :: PLL_VCXO1_PLL_PWRON :: PWRON_PLL [00:00] */
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_PWRON_PWRON_PLL_MASK 0x00000001
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_PWRON_PWRON_PLL_SHIFT 0
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_PWRON_PWRON_PLL_DEFAULT 0x00000001
-
-/***************************************************************************
- *PLL_VCXO1_PLL_RESET - Resets
- ***************************************************************************/
-/* CLKGEN :: PLL_VCXO1_PLL_RESET :: reserved0 [31:02] */
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_RESET_reserved0_MASK 0xfffffffc
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_RESET_reserved0_SHIFT 2
-
-/* CLKGEN :: PLL_VCXO1_PLL_RESET :: RESETD [01:01] */
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_RESET_RESETD_MASK 0x00000002
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_RESET_RESETD_SHIFT 1
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_RESET_RESETD_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_VCXO1_PLL_RESET :: RESETA [00:00] */
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_RESET_RESETA_MASK 0x00000001
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_RESET_RESETA_SHIFT 0
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_RESET_RESETA_DEFAULT 0x00000000
-
-/***************************************************************************
- *PLL_VCXO1_PLL_SSC_MODE_CONTROL_HIGH - Higher bits of Spread Spectrum mode control
- ***************************************************************************/
-/* CLKGEN :: PLL_VCXO1_PLL_SSC_MODE_CONTROL_HIGH :: reserved0 [31:16] */
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_SSC_MODE_CONTROL_HIGH_reserved0_MASK 0xffff0000
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_SSC_MODE_CONTROL_HIGH_reserved0_SHIFT 16
-
-/* CLKGEN :: PLL_VCXO1_PLL_SSC_MODE_CONTROL_HIGH :: SSC_STEP [15:00] */
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_MASK 0x0000ffff
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_SHIFT 0
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *PLL_VCXO1_PLL_SSC_MODE_CONTROL_LOW - Lower bits of Spread Spectrum mode control
- ***************************************************************************/
-/* CLKGEN :: PLL_VCXO1_PLL_SSC_MODE_CONTROL_LOW :: reserved0 [31:23] */
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_SSC_MODE_CONTROL_LOW_reserved0_MASK 0xff800000
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_SSC_MODE_CONTROL_LOW_reserved0_SHIFT 23
-
-/* CLKGEN :: PLL_VCXO1_PLL_SSC_MODE_CONTROL_LOW :: SSC_MODE [22:22] */
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_MASK 0x00400000
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_SHIFT 22
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_VCXO1_PLL_SSC_MODE_CONTROL_LOW :: SSC_LIMIT [21:00] */
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_MASK 0x003fffff
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_SHIFT 0
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_DEFAULT 0x00000000
-
-/***************************************************************************
- *PLL_VCXO1_PLL_STATUS - Status
- ***************************************************************************/
-/* CLKGEN :: PLL_VCXO1_PLL_STATUS :: reserved0 [31:12] */
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_STATUS_reserved0_MASK 0xfffff000
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_STATUS_reserved0_SHIFT 12
-
-/* CLKGEN :: PLL_VCXO1_PLL_STATUS :: TEST_STATUS [11:00] */
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_STATUS_TEST_STATUS_MASK 0x00000fff
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_STATUS_TEST_STATUS_SHIFT 0
-
-/***************************************************************************
- *PLL_VCXO2_PLL_BG_PWRON - Bandgap Power on
- ***************************************************************************/
-/* CLKGEN :: PLL_VCXO2_PLL_BG_PWRON :: reserved0 [31:01] */
-#define BCHP_CLKGEN_PLL_VCXO2_PLL_BG_PWRON_reserved0_MASK 0xfffffffe
-#define BCHP_CLKGEN_PLL_VCXO2_PLL_BG_PWRON_reserved0_SHIFT 1
-
-/* CLKGEN :: PLL_VCXO2_PLL_BG_PWRON :: BG_PWRON_PLL [00:00] */
-#define BCHP_CLKGEN_PLL_VCXO2_PLL_BG_PWRON_BG_PWRON_PLL_MASK 0x00000001
-#define BCHP_CLKGEN_PLL_VCXO2_PLL_BG_PWRON_BG_PWRON_PLL_SHIFT 0
-#define BCHP_CLKGEN_PLL_VCXO2_PLL_BG_PWRON_BG_PWRON_PLL_DEFAULT 0x00000001
-
-/***************************************************************************
- *PLL_VCXO2_PLL_CHANNEL_CTRL_CH_0 - PLL CHANNEL control CH 0
- ***************************************************************************/
-/* CLKGEN :: PLL_VCXO2_PLL_CHANNEL_CTRL_CH_0 :: reserved0 [31:11] */
-#define BCHP_CLKGEN_PLL_VCXO2_PLL_CHANNEL_CTRL_CH_0_reserved0_MASK 0xfffff800
-#define BCHP_CLKGEN_PLL_VCXO2_PLL_CHANNEL_CTRL_CH_0_reserved0_SHIFT 11
-
-/* CLKGEN :: PLL_VCXO2_PLL_CHANNEL_CTRL_CH_0 :: POST_DIVIDER_HOLD_CH0 [10:10] */
-#define BCHP_CLKGEN_PLL_VCXO2_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_MASK 0x00000400
-#define BCHP_CLKGEN_PLL_VCXO2_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_SHIFT 10
-#define BCHP_CLKGEN_PLL_VCXO2_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_VCXO2_PLL_CHANNEL_CTRL_CH_0 :: PHASE_OFFSET_CH0 [09:09] */
-#define BCHP_CLKGEN_PLL_VCXO2_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_MASK 0x00000200
-#define BCHP_CLKGEN_PLL_VCXO2_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_SHIFT 9
-#define BCHP_CLKGEN_PLL_VCXO2_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_VCXO2_PLL_CHANNEL_CTRL_CH_0 :: MDIV_CH0 [08:01] */
-#define BCHP_CLKGEN_PLL_VCXO2_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_MASK 0x000001fe
-#define BCHP_CLKGEN_PLL_VCXO2_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_SHIFT 1
-#define BCHP_CLKGEN_PLL_VCXO2_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_DEFAULT 0x00000040
-
-/* CLKGEN :: PLL_VCXO2_PLL_CHANNEL_CTRL_CH_0 :: CLOCK_DIS_CH0 [00:00] */
-#define BCHP_CLKGEN_PLL_VCXO2_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_MASK 0x00000001
-#define BCHP_CLKGEN_PLL_VCXO2_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_SHIFT 0
-#define BCHP_CLKGEN_PLL_VCXO2_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_DEFAULT 0x00000000
-
-/***************************************************************************
- *PLL_VCXO2_PLL_CHANNEL_CTRL_CH_1 - PLL CHANNEL control CH 1
- ***************************************************************************/
-/* CLKGEN :: PLL_VCXO2_PLL_CHANNEL_CTRL_CH_1 :: reserved0 [31:11] */
-#define BCHP_CLKGEN_PLL_VCXO2_PLL_CHANNEL_CTRL_CH_1_reserved0_MASK 0xfffff800
-#define BCHP_CLKGEN_PLL_VCXO2_PLL_CHANNEL_CTRL_CH_1_reserved0_SHIFT 11
-
-/* CLKGEN :: PLL_VCXO2_PLL_CHANNEL_CTRL_CH_1 :: POST_DIVIDER_HOLD_CH1 [10:10] */
-#define BCHP_CLKGEN_PLL_VCXO2_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_MASK 0x00000400
-#define BCHP_CLKGEN_PLL_VCXO2_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_SHIFT 10
-#define BCHP_CLKGEN_PLL_VCXO2_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_VCXO2_PLL_CHANNEL_CTRL_CH_1 :: PHASE_OFFSET_CH1 [09:09] */
-#define BCHP_CLKGEN_PLL_VCXO2_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_MASK 0x00000200
-#define BCHP_CLKGEN_PLL_VCXO2_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_SHIFT 9
-#define BCHP_CLKGEN_PLL_VCXO2_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_VCXO2_PLL_CHANNEL_CTRL_CH_1 :: MDIV_CH1 [08:01] */
-#define BCHP_CLKGEN_PLL_VCXO2_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_MASK 0x000001fe
-#define BCHP_CLKGEN_PLL_VCXO2_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_SHIFT 1
-#define BCHP_CLKGEN_PLL_VCXO2_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_DEFAULT 0x000000fa
-
-/* CLKGEN :: PLL_VCXO2_PLL_CHANNEL_CTRL_CH_1 :: CLOCK_DIS_CH1 [00:00] */
-#define BCHP_CLKGEN_PLL_VCXO2_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_MASK 0x00000001
-#define BCHP_CLKGEN_PLL_VCXO2_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_SHIFT 0
-#define BCHP_CLKGEN_PLL_VCXO2_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_DEFAULT 0x00000000
-
-/***************************************************************************
- *PLL_VCXO2_PLL_CHANNEL_CTRL_CH_2 - PLL CHANNEL control CH 2
- ***************************************************************************/
-/* CLKGEN :: PLL_VCXO2_PLL_CHANNEL_CTRL_CH_2 :: reserved0 [31:11] */
-#define BCHP_CLKGEN_PLL_VCXO2_PLL_CHANNEL_CTRL_CH_2_reserved0_MASK 0xfffff800
-#define BCHP_CLKGEN_PLL_VCXO2_PLL_CHANNEL_CTRL_CH_2_reserved0_SHIFT 11
-
-/* CLKGEN :: PLL_VCXO2_PLL_CHANNEL_CTRL_CH_2 :: POST_DIVIDER_HOLD_CH2 [10:10] */
-#define BCHP_CLKGEN_PLL_VCXO2_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_HOLD_CH2_MASK 0x00000400
-#define BCHP_CLKGEN_PLL_VCXO2_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_HOLD_CH2_SHIFT 10
-#define BCHP_CLKGEN_PLL_VCXO2_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_HOLD_CH2_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_VCXO2_PLL_CHANNEL_CTRL_CH_2 :: PHASE_OFFSET_CH2 [09:09] */
-#define BCHP_CLKGEN_PLL_VCXO2_PLL_CHANNEL_CTRL_CH_2_PHASE_OFFSET_CH2_MASK 0x00000200
-#define BCHP_CLKGEN_PLL_VCXO2_PLL_CHANNEL_CTRL_CH_2_PHASE_OFFSET_CH2_SHIFT 9
-#define BCHP_CLKGEN_PLL_VCXO2_PLL_CHANNEL_CTRL_CH_2_PHASE_OFFSET_CH2_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_VCXO2_PLL_CHANNEL_CTRL_CH_2 :: MDIV_CH2 [08:01] */
-#define BCHP_CLKGEN_PLL_VCXO2_PLL_CHANNEL_CTRL_CH_2_MDIV_CH2_MASK 0x000001fe
-#define BCHP_CLKGEN_PLL_VCXO2_PLL_CHANNEL_CTRL_CH_2_MDIV_CH2_SHIFT 1
-#define BCHP_CLKGEN_PLL_VCXO2_PLL_CHANNEL_CTRL_CH_2_MDIV_CH2_DEFAULT 0x0000007d
-
-/* CLKGEN :: PLL_VCXO2_PLL_CHANNEL_CTRL_CH_2 :: CLOCK_DIS_CH2 [00:00] */
-#define BCHP_CLKGEN_PLL_VCXO2_PLL_CHANNEL_CTRL_CH_2_CLOCK_DIS_CH2_MASK 0x00000001
-#define BCHP_CLKGEN_PLL_VCXO2_PLL_CHANNEL_CTRL_CH_2_CLOCK_DIS_CH2_SHIFT 0
-#define BCHP_CLKGEN_PLL_VCXO2_PLL_CHANNEL_CTRL_CH_2_CLOCK_DIS_CH2_DEFAULT 0x00000000
-
-/***************************************************************************
- *PLL_VCXO2_PLL_DIV - Pre multiplier
- ***************************************************************************/
-/* CLKGEN :: PLL_VCXO2_PLL_DIV :: reserved0 [31:14] */
-#define BCHP_CLKGEN_PLL_VCXO2_PLL_DIV_reserved0_MASK 0xffffc000
-#define BCHP_CLKGEN_PLL_VCXO2_PLL_DIV_reserved0_SHIFT 14
-
-/* CLKGEN :: PLL_VCXO2_PLL_DIV :: PDIV [13:10] */
-#define BCHP_CLKGEN_PLL_VCXO2_PLL_DIV_PDIV_MASK 0x00003c00
-#define BCHP_CLKGEN_PLL_VCXO2_PLL_DIV_PDIV_SHIFT 10
-#define BCHP_CLKGEN_PLL_VCXO2_PLL_DIV_PDIV_DEFAULT 0x00000002
-
-/* CLKGEN :: PLL_VCXO2_PLL_DIV :: NDIV_INT [09:00] */
-#define BCHP_CLKGEN_PLL_VCXO2_PLL_DIV_NDIV_INT_MASK 0x000003ff
-#define BCHP_CLKGEN_PLL_VCXO2_PLL_DIV_NDIV_INT_SHIFT 0
-#define BCHP_CLKGEN_PLL_VCXO2_PLL_DIV_NDIV_INT_DEFAULT 0x00000040
-
-/***************************************************************************
- *PLL_VCXO2_PLL_FRAC - Fractional
- ***************************************************************************/
-/* CLKGEN :: PLL_VCXO2_PLL_FRAC :: reserved0 [31:20] */
-#define BCHP_CLKGEN_PLL_VCXO2_PLL_FRAC_reserved0_MASK 0xfff00000
-#define BCHP_CLKGEN_PLL_VCXO2_PLL_FRAC_reserved0_SHIFT 20
-
-/* CLKGEN :: PLL_VCXO2_PLL_FRAC :: FRAC_CONTROL [19:00] */
-#define BCHP_CLKGEN_PLL_VCXO2_PLL_FRAC_FRAC_CONTROL_MASK 0x000fffff
-#define BCHP_CLKGEN_PLL_VCXO2_PLL_FRAC_FRAC_CONTROL_SHIFT 0
-#define BCHP_CLKGEN_PLL_VCXO2_PLL_FRAC_FRAC_CONTROL_DEFAULT 0x00000000
-
-/***************************************************************************
- *PLL_VCXO2_PLL_GAIN - PLL GAIN
- ***************************************************************************/
-/* CLKGEN :: PLL_VCXO2_PLL_GAIN :: reserved0 [31:10] */
-#define BCHP_CLKGEN_PLL_VCXO2_PLL_GAIN_reserved0_MASK 0xfffffc00
-#define BCHP_CLKGEN_PLL_VCXO2_PLL_GAIN_reserved0_SHIFT 10
-
-/* CLKGEN :: PLL_VCXO2_PLL_GAIN :: LOOP_GAIN_PROPORTIONAL_IN_PHASE [09:06] */
-#define BCHP_CLKGEN_PLL_VCXO2_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_MASK 0x000003c0
-#define BCHP_CLKGEN_PLL_VCXO2_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_SHIFT 6
-#define BCHP_CLKGEN_PLL_VCXO2_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_DEFAULT 0x00000008
-
-/* CLKGEN :: PLL_VCXO2_PLL_GAIN :: LOOP_GAIN_IN_FREQ [05:03] */
-#define BCHP_CLKGEN_PLL_VCXO2_PLL_GAIN_LOOP_GAIN_IN_FREQ_MASK 0x00000038
-#define BCHP_CLKGEN_PLL_VCXO2_PLL_GAIN_LOOP_GAIN_IN_FREQ_SHIFT 3
-#define BCHP_CLKGEN_PLL_VCXO2_PLL_GAIN_LOOP_GAIN_IN_FREQ_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_VCXO2_PLL_GAIN :: LOOP_GAIN_INTEGRATOR_IN_PHASE [02:00] */
-#define BCHP_CLKGEN_PLL_VCXO2_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_MASK 0x00000007
-#define BCHP_CLKGEN_PLL_VCXO2_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_SHIFT 0
-#define BCHP_CLKGEN_PLL_VCXO2_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_DEFAULT 0x00000004
-
-/***************************************************************************
- *PLL_VCXO2_PLL_HOLD_CH_ALL - Hold PLL all channels
- ***************************************************************************/
-/* CLKGEN :: PLL_VCXO2_PLL_HOLD_CH_ALL :: reserved0 [31:01] */
-#define BCHP_CLKGEN_PLL_VCXO2_PLL_HOLD_CH_ALL_reserved0_MASK 0xfffffffe
-#define BCHP_CLKGEN_PLL_VCXO2_PLL_HOLD_CH_ALL_reserved0_SHIFT 1
-
-/* CLKGEN :: PLL_VCXO2_PLL_HOLD_CH_ALL :: HOLD_CH_ALL [00:00] */
-#define BCHP_CLKGEN_PLL_VCXO2_PLL_HOLD_CH_ALL_HOLD_CH_ALL_MASK 0x00000001
-#define BCHP_CLKGEN_PLL_VCXO2_PLL_HOLD_CH_ALL_HOLD_CH_ALL_SHIFT 0
-#define BCHP_CLKGEN_PLL_VCXO2_PLL_HOLD_CH_ALL_HOLD_CH_ALL_DEFAULT 0x00000000
-
-/***************************************************************************
- *PLL_VCXO2_PLL_LDO_CTRL - Ldo voltage control
- ***************************************************************************/
-/* CLKGEN :: PLL_VCXO2_PLL_LDO_CTRL :: reserved0 [31:16] */
-#define BCHP_CLKGEN_PLL_VCXO2_PLL_LDO_CTRL_reserved0_MASK 0xffff0000
-#define BCHP_CLKGEN_PLL_VCXO2_PLL_LDO_CTRL_reserved0_SHIFT 16
-
-/* CLKGEN :: PLL_VCXO2_PLL_LDO_CTRL :: LDO_CTRL [15:00] */
-#define BCHP_CLKGEN_PLL_VCXO2_PLL_LDO_CTRL_LDO_CTRL_MASK 0x0000ffff
-#define BCHP_CLKGEN_PLL_VCXO2_PLL_LDO_CTRL_LDO_CTRL_SHIFT 0
-#define BCHP_CLKGEN_PLL_VCXO2_PLL_LDO_CTRL_LDO_CTRL_DEFAULT 0x00000005
-
-/***************************************************************************
- *PLL_VCXO2_PLL_LDO_PWRON - LDO Power on
- ***************************************************************************/
-/* CLKGEN :: PLL_VCXO2_PLL_LDO_PWRON :: reserved0 [31:01] */
-#define BCHP_CLKGEN_PLL_VCXO2_PLL_LDO_PWRON_reserved0_MASK 0xfffffffe
-#define BCHP_CLKGEN_PLL_VCXO2_PLL_LDO_PWRON_reserved0_SHIFT 1
-
-/* CLKGEN :: PLL_VCXO2_PLL_LDO_PWRON :: LDO_PWRON_PLL [00:00] */
-#define BCHP_CLKGEN_PLL_VCXO2_PLL_LDO_PWRON_LDO_PWRON_PLL_MASK 0x00000001
-#define BCHP_CLKGEN_PLL_VCXO2_PLL_LDO_PWRON_LDO_PWRON_PLL_SHIFT 0
-#define BCHP_CLKGEN_PLL_VCXO2_PLL_LDO_PWRON_LDO_PWRON_PLL_DEFAULT 0x00000001
-
-/***************************************************************************
- *PLL_VCXO2_PLL_LOCK_STATUS - Lock Status
- ***************************************************************************/
-/* CLKGEN :: PLL_VCXO2_PLL_LOCK_STATUS :: reserved0 [31:02] */
-#define BCHP_CLKGEN_PLL_VCXO2_PLL_LOCK_STATUS_reserved0_MASK 0xfffffffc
-#define BCHP_CLKGEN_PLL_VCXO2_PLL_LOCK_STATUS_reserved0_SHIFT 2
-
-/* CLKGEN :: PLL_VCXO2_PLL_LOCK_STATUS :: LOCK_LOST [01:01] */
-#define BCHP_CLKGEN_PLL_VCXO2_PLL_LOCK_STATUS_LOCK_LOST_MASK 0x00000002
-#define BCHP_CLKGEN_PLL_VCXO2_PLL_LOCK_STATUS_LOCK_LOST_SHIFT 1
-
-/* CLKGEN :: PLL_VCXO2_PLL_LOCK_STATUS :: LOCK [00:00] */
-#define BCHP_CLKGEN_PLL_VCXO2_PLL_LOCK_STATUS_LOCK_MASK 0x00000001
-#define BCHP_CLKGEN_PLL_VCXO2_PLL_LOCK_STATUS_LOCK_SHIFT 0
-
-/***************************************************************************
- *PLL_VCXO2_PLL_MISC - Mscellaneous control bus.
- ***************************************************************************/
-/* CLKGEN :: PLL_VCXO2_PLL_MISC :: VCO_RANGE_LOW [31:31] */
-#define BCHP_CLKGEN_PLL_VCXO2_PLL_MISC_VCO_RANGE_LOW_MASK 0x80000000
-#define BCHP_CLKGEN_PLL_VCXO2_PLL_MISC_VCO_RANGE_LOW_SHIFT 31
-#define BCHP_CLKGEN_PLL_VCXO2_PLL_MISC_VCO_RANGE_LOW_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_VCXO2_PLL_MISC :: VCO_RANGE_HIGH [30:30] */
-#define BCHP_CLKGEN_PLL_VCXO2_PLL_MISC_VCO_RANGE_HIGH_MASK 0x40000000
-#define BCHP_CLKGEN_PLL_VCXO2_PLL_MISC_VCO_RANGE_HIGH_SHIFT 30
-#define BCHP_CLKGEN_PLL_VCXO2_PLL_MISC_VCO_RANGE_HIGH_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_VCXO2_PLL_MISC :: VCO_DIV2 [29:29] */
-#define BCHP_CLKGEN_PLL_VCXO2_PLL_MISC_VCO_DIV2_MASK 0x20000000
-#define BCHP_CLKGEN_PLL_VCXO2_PLL_MISC_VCO_DIV2_SHIFT 29
-#define BCHP_CLKGEN_PLL_VCXO2_PLL_MISC_VCO_DIV2_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_VCXO2_PLL_MISC :: STAT_UPDATE [28:28] */
-#define BCHP_CLKGEN_PLL_VCXO2_PLL_MISC_STAT_UPDATE_MASK 0x10000000
-#define BCHP_CLKGEN_PLL_VCXO2_PLL_MISC_STAT_UPDATE_SHIFT 28
-#define BCHP_CLKGEN_PLL_VCXO2_PLL_MISC_STAT_UPDATE_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_VCXO2_PLL_MISC :: STAT_SELECT [27:25] */
-#define BCHP_CLKGEN_PLL_VCXO2_PLL_MISC_STAT_SELECT_MASK 0x0e000000
-#define BCHP_CLKGEN_PLL_VCXO2_PLL_MISC_STAT_SELECT_SHIFT 25
-#define BCHP_CLKGEN_PLL_VCXO2_PLL_MISC_STAT_SELECT_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_VCXO2_PLL_MISC :: STAT_RESET [24:24] */
-#define BCHP_CLKGEN_PLL_VCXO2_PLL_MISC_STAT_RESET_MASK 0x01000000
-#define BCHP_CLKGEN_PLL_VCXO2_PLL_MISC_STAT_RESET_SHIFT 24
-#define BCHP_CLKGEN_PLL_VCXO2_PLL_MISC_STAT_RESET_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_VCXO2_PLL_MISC :: STAT_MODE [23:22] */
-#define BCHP_CLKGEN_PLL_VCXO2_PLL_MISC_STAT_MODE_MASK 0x00c00000
-#define BCHP_CLKGEN_PLL_VCXO2_PLL_MISC_STAT_MODE_SHIFT 22
-#define BCHP_CLKGEN_PLL_VCXO2_PLL_MISC_STAT_MODE_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_VCXO2_PLL_MISC :: REF_ALT_OFFS [21:21] */
-#define BCHP_CLKGEN_PLL_VCXO2_PLL_MISC_REF_ALT_OFFS_MASK 0x00200000
-#define BCHP_CLKGEN_PLL_VCXO2_PLL_MISC_REF_ALT_OFFS_SHIFT 21
-#define BCHP_CLKGEN_PLL_VCXO2_PLL_MISC_REF_ALT_OFFS_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_VCXO2_PLL_MISC :: PWM_RATE [20:19] */
-#define BCHP_CLKGEN_PLL_VCXO2_PLL_MISC_PWM_RATE_MASK 0x00180000
-#define BCHP_CLKGEN_PLL_VCXO2_PLL_MISC_PWM_RATE_SHIFT 19
-#define BCHP_CLKGEN_PLL_VCXO2_PLL_MISC_PWM_RATE_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_VCXO2_PLL_MISC :: POST_CTRL_RESETB [18:17] */
-#define BCHP_CLKGEN_PLL_VCXO2_PLL_MISC_POST_CTRL_RESETB_MASK 0x00060000
-#define BCHP_CLKGEN_PLL_VCXO2_PLL_MISC_POST_CTRL_RESETB_SHIFT 17
-#define BCHP_CLKGEN_PLL_VCXO2_PLL_MISC_POST_CTRL_RESETB_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_VCXO2_PLL_MISC :: NDIV_RELOCK [16:16] */
-#define BCHP_CLKGEN_PLL_VCXO2_PLL_MISC_NDIV_RELOCK_MASK 0x00010000
-#define BCHP_CLKGEN_PLL_VCXO2_PLL_MISC_NDIV_RELOCK_SHIFT 16
-#define BCHP_CLKGEN_PLL_VCXO2_PLL_MISC_NDIV_RELOCK_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_VCXO2_PLL_MISC :: FAST_LOCK [15:15] */
-#define BCHP_CLKGEN_PLL_VCXO2_PLL_MISC_FAST_LOCK_MASK 0x00008000
-#define BCHP_CLKGEN_PLL_VCXO2_PLL_MISC_FAST_LOCK_SHIFT 15
-#define BCHP_CLKGEN_PLL_VCXO2_PLL_MISC_FAST_LOCK_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_VCXO2_PLL_MISC :: DITHER_DISABLE [14:14] */
-#define BCHP_CLKGEN_PLL_VCXO2_PLL_MISC_DITHER_DISABLE_MASK 0x00004000
-#define BCHP_CLKGEN_PLL_VCXO2_PLL_MISC_DITHER_DISABLE_SHIFT 14
-#define BCHP_CLKGEN_PLL_VCXO2_PLL_MISC_DITHER_DISABLE_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_VCXO2_PLL_MISC :: DCO_CTRL_BYPASS_ENABLE [13:13] */
-#define BCHP_CLKGEN_PLL_VCXO2_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_MASK 0x00002000
-#define BCHP_CLKGEN_PLL_VCXO2_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_SHIFT 13
-#define BCHP_CLKGEN_PLL_VCXO2_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_VCXO2_PLL_MISC :: DCO_CTRL_BYPASS [12:01] */
-#define BCHP_CLKGEN_PLL_VCXO2_PLL_MISC_DCO_CTRL_BYPASS_MASK 0x00001ffe
-#define BCHP_CLKGEN_PLL_VCXO2_PLL_MISC_DCO_CTRL_BYPASS_SHIFT 1
-#define BCHP_CLKGEN_PLL_VCXO2_PLL_MISC_DCO_CTRL_BYPASS_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_VCXO2_PLL_MISC :: AUX_CTRL [00:00] */
-#define BCHP_CLKGEN_PLL_VCXO2_PLL_MISC_AUX_CTRL_MASK 0x00000001
-#define BCHP_CLKGEN_PLL_VCXO2_PLL_MISC_AUX_CTRL_SHIFT 0
-#define BCHP_CLKGEN_PLL_VCXO2_PLL_MISC_AUX_CTRL_DEFAULT 0x00000000
-
-/***************************************************************************
- *PLL_VCXO2_PLL_MISC2 - Mscellaneous control bus continued.
- ***************************************************************************/
-/* CLKGEN :: PLL_VCXO2_PLL_MISC2 :: PLLRESERVED0 [31:01] */
-#define BCHP_CLKGEN_PLL_VCXO2_PLL_MISC2_PLLRESERVED0_MASK 0xfffffffe
-#define BCHP_CLKGEN_PLL_VCXO2_PLL_MISC2_PLLRESERVED0_SHIFT 1
-#define BCHP_CLKGEN_PLL_VCXO2_PLL_MISC2_PLLRESERVED0_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_VCXO2_PLL_MISC2 :: DIG_INPUT_SEL [00:00] */
-#define BCHP_CLKGEN_PLL_VCXO2_PLL_MISC2_DIG_INPUT_SEL_MASK 0x00000001
-#define BCHP_CLKGEN_PLL_VCXO2_PLL_MISC2_DIG_INPUT_SEL_SHIFT 0
-#define BCHP_CLKGEN_PLL_VCXO2_PLL_MISC2_DIG_INPUT_SEL_DEFAULT 0x00000000
-
-/***************************************************************************
- *PLL_VCXO2_PLL_PWRON - Poweron
- ***************************************************************************/
-/* CLKGEN :: PLL_VCXO2_PLL_PWRON :: reserved0 [31:01] */
-#define BCHP_CLKGEN_PLL_VCXO2_PLL_PWRON_reserved0_MASK 0xfffffffe
-#define BCHP_CLKGEN_PLL_VCXO2_PLL_PWRON_reserved0_SHIFT 1
-
-/* CLKGEN :: PLL_VCXO2_PLL_PWRON :: PWRON_PLL [00:00] */
-#define BCHP_CLKGEN_PLL_VCXO2_PLL_PWRON_PWRON_PLL_MASK 0x00000001
-#define BCHP_CLKGEN_PLL_VCXO2_PLL_PWRON_PWRON_PLL_SHIFT 0
-#define BCHP_CLKGEN_PLL_VCXO2_PLL_PWRON_PWRON_PLL_DEFAULT 0x00000001
-
-/***************************************************************************
- *PLL_VCXO2_PLL_RESET - Resets
- ***************************************************************************/
-/* CLKGEN :: PLL_VCXO2_PLL_RESET :: reserved0 [31:02] */
-#define BCHP_CLKGEN_PLL_VCXO2_PLL_RESET_reserved0_MASK 0xfffffffc
-#define BCHP_CLKGEN_PLL_VCXO2_PLL_RESET_reserved0_SHIFT 2
-
-/* CLKGEN :: PLL_VCXO2_PLL_RESET :: RESETD [01:01] */
-#define BCHP_CLKGEN_PLL_VCXO2_PLL_RESET_RESETD_MASK 0x00000002
-#define BCHP_CLKGEN_PLL_VCXO2_PLL_RESET_RESETD_SHIFT 1
-#define BCHP_CLKGEN_PLL_VCXO2_PLL_RESET_RESETD_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_VCXO2_PLL_RESET :: RESETA [00:00] */
-#define BCHP_CLKGEN_PLL_VCXO2_PLL_RESET_RESETA_MASK 0x00000001
-#define BCHP_CLKGEN_PLL_VCXO2_PLL_RESET_RESETA_SHIFT 0
-#define BCHP_CLKGEN_PLL_VCXO2_PLL_RESET_RESETA_DEFAULT 0x00000000
-
-/***************************************************************************
- *PLL_VCXO2_PLL_SSC_MODE_CONTROL_HIGH - Higher bits of Spread Spectrum mode control
- ***************************************************************************/
-/* CLKGEN :: PLL_VCXO2_PLL_SSC_MODE_CONTROL_HIGH :: reserved0 [31:16] */
-#define BCHP_CLKGEN_PLL_VCXO2_PLL_SSC_MODE_CONTROL_HIGH_reserved0_MASK 0xffff0000
-#define BCHP_CLKGEN_PLL_VCXO2_PLL_SSC_MODE_CONTROL_HIGH_reserved0_SHIFT 16
-
-/* CLKGEN :: PLL_VCXO2_PLL_SSC_MODE_CONTROL_HIGH :: SSC_STEP [15:00] */
-#define BCHP_CLKGEN_PLL_VCXO2_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_MASK 0x0000ffff
-#define BCHP_CLKGEN_PLL_VCXO2_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_SHIFT 0
-#define BCHP_CLKGEN_PLL_VCXO2_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *PLL_VCXO2_PLL_SSC_MODE_CONTROL_LOW - Lower bits of Spread Spectrum mode control
- ***************************************************************************/
-/* CLKGEN :: PLL_VCXO2_PLL_SSC_MODE_CONTROL_LOW :: reserved0 [31:23] */
-#define BCHP_CLKGEN_PLL_VCXO2_PLL_SSC_MODE_CONTROL_LOW_reserved0_MASK 0xff800000
-#define BCHP_CLKGEN_PLL_VCXO2_PLL_SSC_MODE_CONTROL_LOW_reserved0_SHIFT 23
-
-/* CLKGEN :: PLL_VCXO2_PLL_SSC_MODE_CONTROL_LOW :: SSC_MODE [22:22] */
-#define BCHP_CLKGEN_PLL_VCXO2_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_MASK 0x00400000
-#define BCHP_CLKGEN_PLL_VCXO2_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_SHIFT 22
-#define BCHP_CLKGEN_PLL_VCXO2_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_VCXO2_PLL_SSC_MODE_CONTROL_LOW :: SSC_LIMIT [21:00] */
-#define BCHP_CLKGEN_PLL_VCXO2_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_MASK 0x003fffff
-#define BCHP_CLKGEN_PLL_VCXO2_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_SHIFT 0
-#define BCHP_CLKGEN_PLL_VCXO2_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_DEFAULT 0x00000000
-
-/***************************************************************************
- *PLL_VCXO2_PLL_STATUS - Status
- ***************************************************************************/
-/* CLKGEN :: PLL_VCXO2_PLL_STATUS :: reserved0 [31:12] */
-#define BCHP_CLKGEN_PLL_VCXO2_PLL_STATUS_reserved0_MASK 0xfffff000
-#define BCHP_CLKGEN_PLL_VCXO2_PLL_STATUS_reserved0_SHIFT 12
-
-/* CLKGEN :: PLL_VCXO2_PLL_STATUS :: TEST_STATUS [11:00] */
-#define BCHP_CLKGEN_PLL_VCXO2_PLL_STATUS_TEST_STATUS_MASK 0x00000fff
-#define BCHP_CLKGEN_PLL_VCXO2_PLL_STATUS_TEST_STATUS_SHIFT 0
-
-/***************************************************************************
- *PLL_XPT_PLL_CHANNEL_CTRL_CH_0 - PLL CHANNEL control CH 0
- ***************************************************************************/
-/* CLKGEN :: PLL_XPT_PLL_CHANNEL_CTRL_CH_0 :: reserved0 [31:11] */
-#define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_0_reserved0_MASK 0xfffff800
-#define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_0_reserved0_SHIFT 11
-
-/* CLKGEN :: PLL_XPT_PLL_CHANNEL_CTRL_CH_0 :: POST_DIVIDER_HOLD_CH0 [10:10] */
-#define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_MASK 0x00000400
-#define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_SHIFT 10
-#define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_XPT_PLL_CHANNEL_CTRL_CH_0 :: PHASE_OFFSET_CH0 [09:09] */
-#define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_MASK 0x00000200
-#define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_SHIFT 9
-#define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_XPT_PLL_CHANNEL_CTRL_CH_0 :: MDIV_CH0 [08:01] */
-#define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_MASK 0x000001fe
-#define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_SHIFT 1
-#define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_DEFAULT 0x00000008
-
-/* CLKGEN :: PLL_XPT_PLL_CHANNEL_CTRL_CH_0 :: CLOCK_DIS_CH0 [00:00] */
-#define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_MASK 0x00000001
-#define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_SHIFT 0
-#define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_DEFAULT 0x00000000
-
-/***************************************************************************
- *PLL_XPT_PLL_CHANNEL_CTRL_CH_1 - PLL CHANNEL control CH 1
- ***************************************************************************/
-/* CLKGEN :: PLL_XPT_PLL_CHANNEL_CTRL_CH_1 :: reserved0 [31:11] */
-#define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_1_reserved0_MASK 0xfffff800
-#define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_1_reserved0_SHIFT 11
-
-/* CLKGEN :: PLL_XPT_PLL_CHANNEL_CTRL_CH_1 :: POST_DIVIDER_HOLD_CH1 [10:10] */
-#define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_MASK 0x00000400
-#define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_SHIFT 10
-#define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_XPT_PLL_CHANNEL_CTRL_CH_1 :: PHASE_OFFSET_CH1 [09:09] */
-#define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_MASK 0x00000200
-#define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_SHIFT 9
-#define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_XPT_PLL_CHANNEL_CTRL_CH_1 :: MDIV_CH1 [08:01] */
-#define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_MASK 0x000001fe
-#define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_SHIFT 1
-#define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_DEFAULT 0x0000000c
-
-/* CLKGEN :: PLL_XPT_PLL_CHANNEL_CTRL_CH_1 :: CLOCK_DIS_CH1 [00:00] */
-#define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_MASK 0x00000001
-#define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_SHIFT 0
-#define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_DEFAULT 0x00000000
-
-/***************************************************************************
- *PLL_XPT_PLL_CHANNEL_CTRL_CH_2 - PLL CHANNEL control CH 2
- ***************************************************************************/
-/* CLKGEN :: PLL_XPT_PLL_CHANNEL_CTRL_CH_2 :: reserved0 [31:11] */
-#define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_2_reserved0_MASK 0xfffff800
-#define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_2_reserved0_SHIFT 11
-
-/* CLKGEN :: PLL_XPT_PLL_CHANNEL_CTRL_CH_2 :: POST_DIVIDER_HOLD_CH2 [10:10] */
-#define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_HOLD_CH2_MASK 0x00000400
-#define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_HOLD_CH2_SHIFT 10
-#define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_HOLD_CH2_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_XPT_PLL_CHANNEL_CTRL_CH_2 :: PHASE_OFFSET_CH2 [09:09] */
-#define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_2_PHASE_OFFSET_CH2_MASK 0x00000200
-#define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_2_PHASE_OFFSET_CH2_SHIFT 9
-#define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_2_PHASE_OFFSET_CH2_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_XPT_PLL_CHANNEL_CTRL_CH_2 :: MDIV_CH2 [08:01] */
-#define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_2_MDIV_CH2_MASK 0x000001fe
-#define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_2_MDIV_CH2_SHIFT 1
-#define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_2_MDIV_CH2_DEFAULT 0x0000000a
-
-/* CLKGEN :: PLL_XPT_PLL_CHANNEL_CTRL_CH_2 :: CLOCK_DIS_CH2 [00:00] */
-#define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_2_CLOCK_DIS_CH2_MASK 0x00000001
-#define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_2_CLOCK_DIS_CH2_SHIFT 0
-#define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_2_CLOCK_DIS_CH2_DEFAULT 0x00000000
-
-/***************************************************************************
- *PLL_XPT_PLL_CHANNEL_CTRL_CH_3 - PLL CHANNEL control CH 3
- ***************************************************************************/
-/* CLKGEN :: PLL_XPT_PLL_CHANNEL_CTRL_CH_3 :: reserved0 [31:11] */
-#define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_3_reserved0_MASK 0xfffff800
-#define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_3_reserved0_SHIFT 11
-
-/* CLKGEN :: PLL_XPT_PLL_CHANNEL_CTRL_CH_3 :: POST_DIVIDER_HOLD_CH3 [10:10] */
-#define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_HOLD_CH3_MASK 0x00000400
-#define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_HOLD_CH3_SHIFT 10
-#define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_HOLD_CH3_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_XPT_PLL_CHANNEL_CTRL_CH_3 :: PHASE_OFFSET_CH3 [09:09] */
-#define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_3_PHASE_OFFSET_CH3_MASK 0x00000200
-#define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_3_PHASE_OFFSET_CH3_SHIFT 9
-#define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_3_PHASE_OFFSET_CH3_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_XPT_PLL_CHANNEL_CTRL_CH_3 :: MDIV_CH3 [08:01] */
-#define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_3_MDIV_CH3_MASK 0x000001fe
-#define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_3_MDIV_CH3_SHIFT 1
-#define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_3_MDIV_CH3_DEFAULT 0x0000000f
-
-/* CLKGEN :: PLL_XPT_PLL_CHANNEL_CTRL_CH_3 :: CLOCK_DIS_CH3 [00:00] */
-#define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_3_CLOCK_DIS_CH3_MASK 0x00000001
-#define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_3_CLOCK_DIS_CH3_SHIFT 0
-#define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_3_CLOCK_DIS_CH3_DEFAULT 0x00000000
-
-/***************************************************************************
- *PLL_XPT_PLL_CHANNEL_CTRL_CH_4 - PLL CHANNEL control CH 4
- ***************************************************************************/
-/* CLKGEN :: PLL_XPT_PLL_CHANNEL_CTRL_CH_4 :: reserved0 [31:11] */
-#define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_4_reserved0_MASK 0xfffff800
-#define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_4_reserved0_SHIFT 11
-
-/* CLKGEN :: PLL_XPT_PLL_CHANNEL_CTRL_CH_4 :: POST_DIVIDER_HOLD_CH4 [10:10] */
-#define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_4_POST_DIVIDER_HOLD_CH4_MASK 0x00000400
-#define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_4_POST_DIVIDER_HOLD_CH4_SHIFT 10
-#define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_4_POST_DIVIDER_HOLD_CH4_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_XPT_PLL_CHANNEL_CTRL_CH_4 :: PHASE_OFFSET_CH4 [09:09] */
-#define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_4_PHASE_OFFSET_CH4_MASK 0x00000200
-#define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_4_PHASE_OFFSET_CH4_SHIFT 9
-#define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_4_PHASE_OFFSET_CH4_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_XPT_PLL_CHANNEL_CTRL_CH_4 :: MDIV_CH4 [08:01] */
-#define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_4_MDIV_CH4_MASK 0x000001fe
-#define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_4_MDIV_CH4_SHIFT 1
-#define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_4_MDIV_CH4_DEFAULT 0x0000000a
-
-/* CLKGEN :: PLL_XPT_PLL_CHANNEL_CTRL_CH_4 :: CLOCK_DIS_CH4 [00:00] */
-#define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_4_CLOCK_DIS_CH4_MASK 0x00000001
-#define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_4_CLOCK_DIS_CH4_SHIFT 0
-#define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_4_CLOCK_DIS_CH4_DEFAULT 0x00000000
-
-/***************************************************************************
- *PLL_XPT_PLL_CHANNEL_CTRL_CH_5 - PLL CHANNEL control CH 5
- ***************************************************************************/
-/* CLKGEN :: PLL_XPT_PLL_CHANNEL_CTRL_CH_5 :: reserved0 [31:11] */
-#define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_5_reserved0_MASK 0xfffff800
-#define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_5_reserved0_SHIFT 11
-
-/* CLKGEN :: PLL_XPT_PLL_CHANNEL_CTRL_CH_5 :: POST_DIVIDER_HOLD_CH5 [10:10] */
-#define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_5_POST_DIVIDER_HOLD_CH5_MASK 0x00000400
-#define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_5_POST_DIVIDER_HOLD_CH5_SHIFT 10
-#define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_5_POST_DIVIDER_HOLD_CH5_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_XPT_PLL_CHANNEL_CTRL_CH_5 :: PHASE_OFFSET_CH5 [09:09] */
-#define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_5_PHASE_OFFSET_CH5_MASK 0x00000200
-#define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_5_PHASE_OFFSET_CH5_SHIFT 9
-#define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_5_PHASE_OFFSET_CH5_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_XPT_PLL_CHANNEL_CTRL_CH_5 :: MDIV_CH5 [08:01] */
-#define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_5_MDIV_CH5_MASK 0x000001fe
-#define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_5_MDIV_CH5_SHIFT 1
-#define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_5_MDIV_CH5_DEFAULT 0x00000008
-
-/* CLKGEN :: PLL_XPT_PLL_CHANNEL_CTRL_CH_5 :: CLOCK_DIS_CH5 [00:00] */
-#define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_5_CLOCK_DIS_CH5_MASK 0x00000001
-#define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_5_CLOCK_DIS_CH5_SHIFT 0
-#define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_5_CLOCK_DIS_CH5_DEFAULT 0x00000000
-
-/***************************************************************************
- *PLL_XPT_PLL_DIV - Pre multiplier
- ***************************************************************************/
-/* CLKGEN :: PLL_XPT_PLL_DIV :: reserved0 [31:14] */
-#define BCHP_CLKGEN_PLL_XPT_PLL_DIV_reserved0_MASK 0xffffc000
-#define BCHP_CLKGEN_PLL_XPT_PLL_DIV_reserved0_SHIFT 14
-
-/* CLKGEN :: PLL_XPT_PLL_DIV :: PDIV [13:10] */
-#define BCHP_CLKGEN_PLL_XPT_PLL_DIV_PDIV_MASK 0x00003c00
-#define BCHP_CLKGEN_PLL_XPT_PLL_DIV_PDIV_SHIFT 10
-#define BCHP_CLKGEN_PLL_XPT_PLL_DIV_PDIV_DEFAULT 0x00000002
-
-/* CLKGEN :: PLL_XPT_PLL_DIV :: NDIV_INT [09:00] */
-#define BCHP_CLKGEN_PLL_XPT_PLL_DIV_NDIV_INT_MASK 0x000003ff
-#define BCHP_CLKGEN_PLL_XPT_PLL_DIV_NDIV_INT_SHIFT 0
-#define BCHP_CLKGEN_PLL_XPT_PLL_DIV_NDIV_INT_DEFAULT 0x00000078
-
-/***************************************************************************
- *PLL_XPT_PLL_GAIN - PLL GAIN
- ***************************************************************************/
-/* CLKGEN :: PLL_XPT_PLL_GAIN :: reserved0 [31:10] */
-#define BCHP_CLKGEN_PLL_XPT_PLL_GAIN_reserved0_MASK 0xfffffc00
-#define BCHP_CLKGEN_PLL_XPT_PLL_GAIN_reserved0_SHIFT 10
-
-/* CLKGEN :: PLL_XPT_PLL_GAIN :: LOOP_GAIN_PROPORTIONAL_IN_PHASE [09:06] */
-#define BCHP_CLKGEN_PLL_XPT_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_MASK 0x000003c0
-#define BCHP_CLKGEN_PLL_XPT_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_SHIFT 6
-#define BCHP_CLKGEN_PLL_XPT_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_DEFAULT 0x00000005
-
-/* CLKGEN :: PLL_XPT_PLL_GAIN :: LOOP_GAIN_IN_FREQ [05:03] */
-#define BCHP_CLKGEN_PLL_XPT_PLL_GAIN_LOOP_GAIN_IN_FREQ_MASK 0x00000038
-#define BCHP_CLKGEN_PLL_XPT_PLL_GAIN_LOOP_GAIN_IN_FREQ_SHIFT 3
-#define BCHP_CLKGEN_PLL_XPT_PLL_GAIN_LOOP_GAIN_IN_FREQ_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_XPT_PLL_GAIN :: LOOP_GAIN_INTEGRATOR_IN_PHASE [02:00] */
-#define BCHP_CLKGEN_PLL_XPT_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_MASK 0x00000007
-#define BCHP_CLKGEN_PLL_XPT_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_SHIFT 0
-#define BCHP_CLKGEN_PLL_XPT_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_DEFAULT 0x00000002
-
-/***************************************************************************
- *PLL_XPT_PLL_LDO_PWRON - LDO Power on
- ***************************************************************************/
-/* CLKGEN :: PLL_XPT_PLL_LDO_PWRON :: reserved0 [31:01] */
-#define BCHP_CLKGEN_PLL_XPT_PLL_LDO_PWRON_reserved0_MASK 0xfffffffe
-#define BCHP_CLKGEN_PLL_XPT_PLL_LDO_PWRON_reserved0_SHIFT 1
-
-/* CLKGEN :: PLL_XPT_PLL_LDO_PWRON :: LDO_PWRON_PLL [00:00] */
-#define BCHP_CLKGEN_PLL_XPT_PLL_LDO_PWRON_LDO_PWRON_PLL_MASK 0x00000001
-#define BCHP_CLKGEN_PLL_XPT_PLL_LDO_PWRON_LDO_PWRON_PLL_SHIFT 0
-#define BCHP_CLKGEN_PLL_XPT_PLL_LDO_PWRON_LDO_PWRON_PLL_DEFAULT 0x00000001
-
-/***************************************************************************
- *PLL_XPT_PLL_LOCK_STATUS - Lock Status
- ***************************************************************************/
-/* CLKGEN :: PLL_XPT_PLL_LOCK_STATUS :: reserved0 [31:02] */
-#define BCHP_CLKGEN_PLL_XPT_PLL_LOCK_STATUS_reserved0_MASK 0xfffffffc
-#define BCHP_CLKGEN_PLL_XPT_PLL_LOCK_STATUS_reserved0_SHIFT 2
-
-/* CLKGEN :: PLL_XPT_PLL_LOCK_STATUS :: LOCK_LOST [01:01] */
-#define BCHP_CLKGEN_PLL_XPT_PLL_LOCK_STATUS_LOCK_LOST_MASK 0x00000002
-#define BCHP_CLKGEN_PLL_XPT_PLL_LOCK_STATUS_LOCK_LOST_SHIFT 1
-
-/* CLKGEN :: PLL_XPT_PLL_LOCK_STATUS :: LOCK [00:00] */
-#define BCHP_CLKGEN_PLL_XPT_PLL_LOCK_STATUS_LOCK_MASK 0x00000001
-#define BCHP_CLKGEN_PLL_XPT_PLL_LOCK_STATUS_LOCK_SHIFT 0
-
-/***************************************************************************
- *PLL_XPT_PLL_MISC - Mscellaneous control bus.
- ***************************************************************************/
-/* CLKGEN :: PLL_XPT_PLL_MISC :: VCO_RANGE [31:30] */
-#define BCHP_CLKGEN_PLL_XPT_PLL_MISC_VCO_RANGE_MASK 0xc0000000
-#define BCHP_CLKGEN_PLL_XPT_PLL_MISC_VCO_RANGE_SHIFT 30
-#define BCHP_CLKGEN_PLL_XPT_PLL_MISC_VCO_RANGE_DEFAULT 0x00000002
-
-/* CLKGEN :: PLL_XPT_PLL_MISC :: VCO_FB_DIV2 [29:29] */
-#define BCHP_CLKGEN_PLL_XPT_PLL_MISC_VCO_FB_DIV2_MASK 0x20000000
-#define BCHP_CLKGEN_PLL_XPT_PLL_MISC_VCO_FB_DIV2_SHIFT 29
-#define BCHP_CLKGEN_PLL_XPT_PLL_MISC_VCO_FB_DIV2_DEFAULT 0x00000001
-
-/* CLKGEN :: PLL_XPT_PLL_MISC :: STAT_UPDATE [28:28] */
-#define BCHP_CLKGEN_PLL_XPT_PLL_MISC_STAT_UPDATE_MASK 0x10000000
-#define BCHP_CLKGEN_PLL_XPT_PLL_MISC_STAT_UPDATE_SHIFT 28
-#define BCHP_CLKGEN_PLL_XPT_PLL_MISC_STAT_UPDATE_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_XPT_PLL_MISC :: STAT_SELECT [27:25] */
-#define BCHP_CLKGEN_PLL_XPT_PLL_MISC_STAT_SELECT_MASK 0x0e000000
-#define BCHP_CLKGEN_PLL_XPT_PLL_MISC_STAT_SELECT_SHIFT 25
-#define BCHP_CLKGEN_PLL_XPT_PLL_MISC_STAT_SELECT_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_XPT_PLL_MISC :: STAT_RESET [24:24] */
-#define BCHP_CLKGEN_PLL_XPT_PLL_MISC_STAT_RESET_MASK 0x01000000
-#define BCHP_CLKGEN_PLL_XPT_PLL_MISC_STAT_RESET_SHIFT 24
-#define BCHP_CLKGEN_PLL_XPT_PLL_MISC_STAT_RESET_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_XPT_PLL_MISC :: STAT_MODE [23:22] */
-#define BCHP_CLKGEN_PLL_XPT_PLL_MISC_STAT_MODE_MASK 0x00c00000
-#define BCHP_CLKGEN_PLL_XPT_PLL_MISC_STAT_MODE_SHIFT 22
-#define BCHP_CLKGEN_PLL_XPT_PLL_MISC_STAT_MODE_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_XPT_PLL_MISC :: PWM_RATE [21:20] */
-#define BCHP_CLKGEN_PLL_XPT_PLL_MISC_PWM_RATE_MASK 0x00300000
-#define BCHP_CLKGEN_PLL_XPT_PLL_MISC_PWM_RATE_SHIFT 20
-#define BCHP_CLKGEN_PLL_XPT_PLL_MISC_PWM_RATE_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_XPT_PLL_MISC :: POST_CTRL_RESETB [19:18] */
-#define BCHP_CLKGEN_PLL_XPT_PLL_MISC_POST_CTRL_RESETB_MASK 0x000c0000
-#define BCHP_CLKGEN_PLL_XPT_PLL_MISC_POST_CTRL_RESETB_SHIFT 18
-#define BCHP_CLKGEN_PLL_XPT_PLL_MISC_POST_CTRL_RESETB_DEFAULT 0x00000003
-
-/* CLKGEN :: PLL_XPT_PLL_MISC :: PLLRESERVED2 [17:16] */
-#define BCHP_CLKGEN_PLL_XPT_PLL_MISC_PLLRESERVED2_MASK 0x00030000
-#define BCHP_CLKGEN_PLL_XPT_PLL_MISC_PLLRESERVED2_SHIFT 16
-#define BCHP_CLKGEN_PLL_XPT_PLL_MISC_PLLRESERVED2_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_XPT_PLL_MISC :: PLLRESERVED1 [15:15] */
-#define BCHP_CLKGEN_PLL_XPT_PLL_MISC_PLLRESERVED1_MASK 0x00008000
-#define BCHP_CLKGEN_PLL_XPT_PLL_MISC_PLLRESERVED1_SHIFT 15
-#define BCHP_CLKGEN_PLL_XPT_PLL_MISC_PLLRESERVED1_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_XPT_PLL_MISC :: NDIV_RELOCK [14:14] */
-#define BCHP_CLKGEN_PLL_XPT_PLL_MISC_NDIV_RELOCK_MASK 0x00004000
-#define BCHP_CLKGEN_PLL_XPT_PLL_MISC_NDIV_RELOCK_SHIFT 14
-#define BCHP_CLKGEN_PLL_XPT_PLL_MISC_NDIV_RELOCK_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_XPT_PLL_MISC :: FAST_LOCK [13:13] */
-#define BCHP_CLKGEN_PLL_XPT_PLL_MISC_FAST_LOCK_MASK 0x00002000
-#define BCHP_CLKGEN_PLL_XPT_PLL_MISC_FAST_LOCK_SHIFT 13
-#define BCHP_CLKGEN_PLL_XPT_PLL_MISC_FAST_LOCK_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_XPT_PLL_MISC :: DCO_CTRL_BYPASS_ENABLE [12:12] */
-#define BCHP_CLKGEN_PLL_XPT_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_MASK 0x00001000
-#define BCHP_CLKGEN_PLL_XPT_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_SHIFT 12
-#define BCHP_CLKGEN_PLL_XPT_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_XPT_PLL_MISC :: DCO_CTRL_BYPASS [11:00] */
-#define BCHP_CLKGEN_PLL_XPT_PLL_MISC_DCO_CTRL_BYPASS_MASK 0x00000fff
-#define BCHP_CLKGEN_PLL_XPT_PLL_MISC_DCO_CTRL_BYPASS_SHIFT 0
-#define BCHP_CLKGEN_PLL_XPT_PLL_MISC_DCO_CTRL_BYPASS_DEFAULT 0x00000000
-
-/***************************************************************************
- *PLL_XPT_PLL_MISC2 - Mscellaneous control bus continued.
- ***************************************************************************/
-/* CLKGEN :: PLL_XPT_PLL_MISC2 :: PLLRESERVED0 [31:02] */
-#define BCHP_CLKGEN_PLL_XPT_PLL_MISC2_PLLRESERVED0_MASK 0xfffffffc
-#define BCHP_CLKGEN_PLL_XPT_PLL_MISC2_PLLRESERVED0_SHIFT 2
-#define BCHP_CLKGEN_PLL_XPT_PLL_MISC2_PLLRESERVED0_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_XPT_PLL_MISC2 :: LDO [01:00] */
-#define BCHP_CLKGEN_PLL_XPT_PLL_MISC2_LDO_MASK 0x00000003
-#define BCHP_CLKGEN_PLL_XPT_PLL_MISC2_LDO_SHIFT 0
-#define BCHP_CLKGEN_PLL_XPT_PLL_MISC2_LDO_DEFAULT 0x00000001
-
-/***************************************************************************
- *PLL_XPT_PLL_PWRON - Poweron
- ***************************************************************************/
-/* CLKGEN :: PLL_XPT_PLL_PWRON :: reserved0 [31:01] */
-#define BCHP_CLKGEN_PLL_XPT_PLL_PWRON_reserved0_MASK 0xfffffffe
-#define BCHP_CLKGEN_PLL_XPT_PLL_PWRON_reserved0_SHIFT 1
-
-/* CLKGEN :: PLL_XPT_PLL_PWRON :: PWRON_PLL [00:00] */
-#define BCHP_CLKGEN_PLL_XPT_PLL_PWRON_PWRON_PLL_MASK 0x00000001
-#define BCHP_CLKGEN_PLL_XPT_PLL_PWRON_PWRON_PLL_SHIFT 0
-#define BCHP_CLKGEN_PLL_XPT_PLL_PWRON_PWRON_PLL_DEFAULT 0x00000001
-
-/***************************************************************************
- *PLL_XPT_PLL_RESET - Resets
- ***************************************************************************/
-/* CLKGEN :: PLL_XPT_PLL_RESET :: reserved0 [31:01] */
-#define BCHP_CLKGEN_PLL_XPT_PLL_RESET_reserved0_MASK 0xfffffffe
-#define BCHP_CLKGEN_PLL_XPT_PLL_RESET_reserved0_SHIFT 1
-
-/* CLKGEN :: PLL_XPT_PLL_RESET :: RESETD [00:00] */
-#define BCHP_CLKGEN_PLL_XPT_PLL_RESET_RESETD_MASK 0x00000001
-#define BCHP_CLKGEN_PLL_XPT_PLL_RESET_RESETD_SHIFT 0
-#define BCHP_CLKGEN_PLL_XPT_PLL_RESET_RESETD_DEFAULT 0x00000000
-
-/***************************************************************************
- *PLL_XPT_PLL_SSC_MODE_CONTROL_HIGH - Higher bits of Spread Spectrum mode control
- ***************************************************************************/
-/* CLKGEN :: PLL_XPT_PLL_SSC_MODE_CONTROL_HIGH :: reserved0 [31:16] */
-#define BCHP_CLKGEN_PLL_XPT_PLL_SSC_MODE_CONTROL_HIGH_reserved0_MASK 0xffff0000
-#define BCHP_CLKGEN_PLL_XPT_PLL_SSC_MODE_CONTROL_HIGH_reserved0_SHIFT 16
-
-/* CLKGEN :: PLL_XPT_PLL_SSC_MODE_CONTROL_HIGH :: SSC_STEP [15:00] */
-#define BCHP_CLKGEN_PLL_XPT_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_MASK 0x0000ffff
-#define BCHP_CLKGEN_PLL_XPT_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_SHIFT 0
-#define BCHP_CLKGEN_PLL_XPT_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *PLL_XPT_PLL_SSC_MODE_CONTROL_LOW - Lower bits of Spread Spectrum mode control
- ***************************************************************************/
-/* CLKGEN :: PLL_XPT_PLL_SSC_MODE_CONTROL_LOW :: reserved0 [31:23] */
-#define BCHP_CLKGEN_PLL_XPT_PLL_SSC_MODE_CONTROL_LOW_reserved0_MASK 0xff800000
-#define BCHP_CLKGEN_PLL_XPT_PLL_SSC_MODE_CONTROL_LOW_reserved0_SHIFT 23
-
-/* CLKGEN :: PLL_XPT_PLL_SSC_MODE_CONTROL_LOW :: SSC_MODE [22:22] */
-#define BCHP_CLKGEN_PLL_XPT_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_MASK 0x00400000
-#define BCHP_CLKGEN_PLL_XPT_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_SHIFT 22
-#define BCHP_CLKGEN_PLL_XPT_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_XPT_PLL_SSC_MODE_CONTROL_LOW :: SSC_LIMIT [21:00] */
-#define BCHP_CLKGEN_PLL_XPT_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_MASK 0x003fffff
-#define BCHP_CLKGEN_PLL_XPT_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_SHIFT 0
-#define BCHP_CLKGEN_PLL_XPT_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_DEFAULT 0x00000000
-
-/***************************************************************************
- *PLL_XPT_PLL_STATUS - Status
- ***************************************************************************/
-/* CLKGEN :: PLL_XPT_PLL_STATUS :: reserved0 [31:12] */
-#define BCHP_CLKGEN_PLL_XPT_PLL_STATUS_reserved0_MASK 0xfffff000
-#define BCHP_CLKGEN_PLL_XPT_PLL_STATUS_reserved0_SHIFT 12
-
-/* CLKGEN :: PLL_XPT_PLL_STATUS :: TEST_STATUS [11:00] */
-#define BCHP_CLKGEN_PLL_XPT_PLL_STATUS_TEST_STATUS_MASK 0x00000fff
-#define BCHP_CLKGEN_PLL_XPT_PLL_STATUS_TEST_STATUS_SHIFT 0
-
-/***************************************************************************
- *ANA_QDAC_TS28HPM_6MX_2MR_FC_H_E_INST_CLOCK_DISABLE - Disable ANA_QDAC_TS28HPM_6MX_2MR_FC_H_E_INST's clocks
- ***************************************************************************/
-/* CLKGEN :: ANA_QDAC_TS28HPM_6MX_2MR_FC_H_E_INST_CLOCK_DISABLE :: reserved0 [31:01] */
-#define BCHP_CLKGEN_ANA_QDAC_TS28HPM_6MX_2MR_FC_H_E_INST_CLOCK_DISABLE_reserved0_MASK 0xfffffffe
-#define BCHP_CLKGEN_ANA_QDAC_TS28HPM_6MX_2MR_FC_H_E_INST_CLOCK_DISABLE_reserved0_SHIFT 1
-
-/* CLKGEN :: ANA_QDAC_TS28HPM_6MX_2MR_FC_H_E_INST_CLOCK_DISABLE :: DISABLE_ADC_4P5_CLOCK [00:00] */
-#define BCHP_CLKGEN_ANA_QDAC_TS28HPM_6MX_2MR_FC_H_E_INST_CLOCK_DISABLE_DISABLE_ADC_4P5_CLOCK_MASK 0x00000001
-#define BCHP_CLKGEN_ANA_QDAC_TS28HPM_6MX_2MR_FC_H_E_INST_CLOCK_DISABLE_DISABLE_ADC_4P5_CLOCK_SHIFT 0
-#define BCHP_CLKGEN_ANA_QDAC_TS28HPM_6MX_2MR_FC_H_E_INST_CLOCK_DISABLE_DISABLE_ADC_4P5_CLOCK_DEFAULT 0x00000000
-
-/***************************************************************************
- *ANA_QDAC_TS28HPM_6MX_2MR_FC_H_E_INST_CLOCK_DISABLE_STATUS - Clock Disable Status
- ***************************************************************************/
-/* CLKGEN :: ANA_QDAC_TS28HPM_6MX_2MR_FC_H_E_INST_CLOCK_DISABLE_STATUS :: reserved0 [31:01] */
-#define BCHP_CLKGEN_ANA_QDAC_TS28HPM_6MX_2MR_FC_H_E_INST_CLOCK_DISABLE_STATUS_reserved0_MASK 0xfffffffe
-#define BCHP_CLKGEN_ANA_QDAC_TS28HPM_6MX_2MR_FC_H_E_INST_CLOCK_DISABLE_STATUS_reserved0_SHIFT 1
-
-/* CLKGEN :: ANA_QDAC_TS28HPM_6MX_2MR_FC_H_E_INST_CLOCK_DISABLE_STATUS :: DISABLE_ADC_4P5_CLOCK_STATUS [00:00] */
-#define BCHP_CLKGEN_ANA_QDAC_TS28HPM_6MX_2MR_FC_H_E_INST_CLOCK_DISABLE_STATUS_DISABLE_ADC_4P5_CLOCK_STATUS_MASK 0x00000001
-#define BCHP_CLKGEN_ANA_QDAC_TS28HPM_6MX_2MR_FC_H_E_INST_CLOCK_DISABLE_STATUS_DISABLE_ADC_4P5_CLOCK_STATUS_SHIFT 0
-
-/***************************************************************************
- *ANA_SW_AVS_TS28HPM_6MX_2MR_FC_H_E_INST_CLOCK_DISABLE - Disable ANA_SW_AVS_TS28HPM_6MX_2MR_FC_H_E_INST's clocks
- ***************************************************************************/
-/* CLKGEN :: ANA_SW_AVS_TS28HPM_6MX_2MR_FC_H_E_INST_CLOCK_DISABLE :: reserved0 [31:01] */
-#define BCHP_CLKGEN_ANA_SW_AVS_TS28HPM_6MX_2MR_FC_H_E_INST_CLOCK_DISABLE_reserved0_MASK 0xfffffffe
-#define BCHP_CLKGEN_ANA_SW_AVS_TS28HPM_6MX_2MR_FC_H_E_INST_CLOCK_DISABLE_reserved0_SHIFT 1
-
-/* CLKGEN :: ANA_SW_AVS_TS28HPM_6MX_2MR_FC_H_E_INST_CLOCK_DISABLE :: DISABLE_SYSTEM_54_VR_CLOCK [00:00] */
-#define BCHP_CLKGEN_ANA_SW_AVS_TS28HPM_6MX_2MR_FC_H_E_INST_CLOCK_DISABLE_DISABLE_SYSTEM_54_VR_CLOCK_MASK 0x00000001
-#define BCHP_CLKGEN_ANA_SW_AVS_TS28HPM_6MX_2MR_FC_H_E_INST_CLOCK_DISABLE_DISABLE_SYSTEM_54_VR_CLOCK_SHIFT 0
-#define BCHP_CLKGEN_ANA_SW_AVS_TS28HPM_6MX_2MR_FC_H_E_INST_CLOCK_DISABLE_DISABLE_SYSTEM_54_VR_CLOCK_DEFAULT 0x00000000
-
-/***************************************************************************
- *ANA_SW_AVS_TS28HPM_6MX_2MR_FC_H_E_INST_CLOCK_DISABLE_STATUS - Clock Disable Status
- ***************************************************************************/
-/* CLKGEN :: ANA_SW_AVS_TS28HPM_6MX_2MR_FC_H_E_INST_CLOCK_DISABLE_STATUS :: reserved0 [31:01] */
-#define BCHP_CLKGEN_ANA_SW_AVS_TS28HPM_6MX_2MR_FC_H_E_INST_CLOCK_DISABLE_STATUS_reserved0_MASK 0xfffffffe
-#define BCHP_CLKGEN_ANA_SW_AVS_TS28HPM_6MX_2MR_FC_H_E_INST_CLOCK_DISABLE_STATUS_reserved0_SHIFT 1
-
-/* CLKGEN :: ANA_SW_AVS_TS28HPM_6MX_2MR_FC_H_E_INST_CLOCK_DISABLE_STATUS :: DISABLE_SYSTEM_54_VR_CLOCK_STATUS [00:00] */
-#define BCHP_CLKGEN_ANA_SW_AVS_TS28HPM_6MX_2MR_FC_H_E_INST_CLOCK_DISABLE_STATUS_DISABLE_SYSTEM_54_VR_CLOCK_STATUS_MASK 0x00000001
-#define BCHP_CLKGEN_ANA_SW_AVS_TS28HPM_6MX_2MR_FC_H_E_INST_CLOCK_DISABLE_STATUS_DISABLE_SYSTEM_54_VR_CLOCK_STATUS_SHIFT 0
-
-/***************************************************************************
- *APM_CHIP_TOP_INST_CLOCK_ENABLE - Apm chip top inst clock enable
- ***************************************************************************/
-/* CLKGEN :: APM_CHIP_TOP_INST_CLOCK_ENABLE :: reserved0 [31:01] */
-#define BCHP_CLKGEN_APM_CHIP_TOP_INST_CLOCK_ENABLE_reserved0_MASK 0xfffffffe
-#define BCHP_CLKGEN_APM_CHIP_TOP_INST_CLOCK_ENABLE_reserved0_SHIFT 1
-
-/* CLKGEN :: APM_CHIP_TOP_INST_CLOCK_ENABLE :: APM_54_CLOCK_ENABLE [00:00] */
-#define BCHP_CLKGEN_APM_CHIP_TOP_INST_CLOCK_ENABLE_APM_54_CLOCK_ENABLE_MASK 0x00000001
-#define BCHP_CLKGEN_APM_CHIP_TOP_INST_CLOCK_ENABLE_APM_54_CLOCK_ENABLE_SHIFT 0
-#define BCHP_CLKGEN_APM_CHIP_TOP_INST_CLOCK_ENABLE_APM_54_CLOCK_ENABLE_DEFAULT 0x00000001
-
-/***************************************************************************
- *APM_CHIP_TOP_INST_CLOCK_ENABLE_STATUS - Clock Enable Status
- ***************************************************************************/
-/* CLKGEN :: APM_CHIP_TOP_INST_CLOCK_ENABLE_STATUS :: reserved0 [31:01] */
-#define BCHP_CLKGEN_APM_CHIP_TOP_INST_CLOCK_ENABLE_STATUS_reserved0_MASK 0xfffffffe
-#define BCHP_CLKGEN_APM_CHIP_TOP_INST_CLOCK_ENABLE_STATUS_reserved0_SHIFT 1
-
-/* CLKGEN :: APM_CHIP_TOP_INST_CLOCK_ENABLE_STATUS :: APM_54_CLOCK_ENABLE_STATUS [00:00] */
-#define BCHP_CLKGEN_APM_CHIP_TOP_INST_CLOCK_ENABLE_STATUS_APM_54_CLOCK_ENABLE_STATUS_MASK 0x00000001
-#define BCHP_CLKGEN_APM_CHIP_TOP_INST_CLOCK_ENABLE_STATUS_APM_54_CLOCK_ENABLE_STATUS_SHIFT 0
-
-/***************************************************************************
- *AVD_SID1_TOP_INST_CLOCK_ENABLE - Avd sid1 top inst clock enable
- ***************************************************************************/
-/* CLKGEN :: AVD_SID1_TOP_INST_CLOCK_ENABLE :: reserved0 [31:05] */
-#define BCHP_CLKGEN_AVD_SID1_TOP_INST_CLOCK_ENABLE_reserved0_MASK 0xffffffe0
-#define BCHP_CLKGEN_AVD_SID1_TOP_INST_CLOCK_ENABLE_reserved0_SHIFT 5
-
-/* CLKGEN :: AVD_SID1_TOP_INST_CLOCK_ENABLE :: AVD_SID1_SCB_CLOCK_ENABLE [04:04] */
-#define BCHP_CLKGEN_AVD_SID1_TOP_INST_CLOCK_ENABLE_AVD_SID1_SCB_CLOCK_ENABLE_MASK 0x00000010
-#define BCHP_CLKGEN_AVD_SID1_TOP_INST_CLOCK_ENABLE_AVD_SID1_SCB_CLOCK_ENABLE_SHIFT 4
-#define BCHP_CLKGEN_AVD_SID1_TOP_INST_CLOCK_ENABLE_AVD_SID1_SCB_CLOCK_ENABLE_DEFAULT 0x00000001
-
-/* CLKGEN :: AVD_SID1_TOP_INST_CLOCK_ENABLE :: AVD_SID1_GISB_CLOCK_ENABLE [03:03] */
-#define BCHP_CLKGEN_AVD_SID1_TOP_INST_CLOCK_ENABLE_AVD_SID1_GISB_CLOCK_ENABLE_MASK 0x00000008
-#define BCHP_CLKGEN_AVD_SID1_TOP_INST_CLOCK_ENABLE_AVD_SID1_GISB_CLOCK_ENABLE_SHIFT 3
-#define BCHP_CLKGEN_AVD_SID1_TOP_INST_CLOCK_ENABLE_AVD_SID1_GISB_CLOCK_ENABLE_DEFAULT 0x00000001
-
-/* CLKGEN :: AVD_SID1_TOP_INST_CLOCK_ENABLE :: AVD_SID1_CPU_CLOCK_ENABLE [02:02] */
-#define BCHP_CLKGEN_AVD_SID1_TOP_INST_CLOCK_ENABLE_AVD_SID1_CPU_CLOCK_ENABLE_MASK 0x00000004
-#define BCHP_CLKGEN_AVD_SID1_TOP_INST_CLOCK_ENABLE_AVD_SID1_CPU_CLOCK_ENABLE_SHIFT 2
-#define BCHP_CLKGEN_AVD_SID1_TOP_INST_CLOCK_ENABLE_AVD_SID1_CPU_CLOCK_ENABLE_DEFAULT 0x00000001
-
-/* CLKGEN :: AVD_SID1_TOP_INST_CLOCK_ENABLE :: AVD_SID1_CORE_CLOCK_ENABLE [01:01] */
-#define BCHP_CLKGEN_AVD_SID1_TOP_INST_CLOCK_ENABLE_AVD_SID1_CORE_CLOCK_ENABLE_MASK 0x00000002
-#define BCHP_CLKGEN_AVD_SID1_TOP_INST_CLOCK_ENABLE_AVD_SID1_CORE_CLOCK_ENABLE_SHIFT 1
-#define BCHP_CLKGEN_AVD_SID1_TOP_INST_CLOCK_ENABLE_AVD_SID1_CORE_CLOCK_ENABLE_DEFAULT 0x00000001
-
-/* CLKGEN :: AVD_SID1_TOP_INST_CLOCK_ENABLE :: AVD_SID1_54_CLOCK_ENABLE [00:00] */
-#define BCHP_CLKGEN_AVD_SID1_TOP_INST_CLOCK_ENABLE_AVD_SID1_54_CLOCK_ENABLE_MASK 0x00000001
-#define BCHP_CLKGEN_AVD_SID1_TOP_INST_CLOCK_ENABLE_AVD_SID1_54_CLOCK_ENABLE_SHIFT 0
-#define BCHP_CLKGEN_AVD_SID1_TOP_INST_CLOCK_ENABLE_AVD_SID1_54_CLOCK_ENABLE_DEFAULT 0x00000001
-
-/***************************************************************************
- *AVD_SID1_TOP_INST_CLOCK_ENABLE_SID - Avd sid1 top inst clock enable sid
- ***************************************************************************/
-/* CLKGEN :: AVD_SID1_TOP_INST_CLOCK_ENABLE_SID :: reserved0 [31:01] */
-#define BCHP_CLKGEN_AVD_SID1_TOP_INST_CLOCK_ENABLE_SID_reserved0_MASK 0xfffffffe
-#define BCHP_CLKGEN_AVD_SID1_TOP_INST_CLOCK_ENABLE_SID_reserved0_SHIFT 1
-
-/* CLKGEN :: AVD_SID1_TOP_INST_CLOCK_ENABLE_SID :: SID_CORE_CLOCK_ENABLE_SID [00:00] */
-#define BCHP_CLKGEN_AVD_SID1_TOP_INST_CLOCK_ENABLE_SID_SID_CORE_CLOCK_ENABLE_SID_MASK 0x00000001
-#define BCHP_CLKGEN_AVD_SID1_TOP_INST_CLOCK_ENABLE_SID_SID_CORE_CLOCK_ENABLE_SID_SHIFT 0
-#define BCHP_CLKGEN_AVD_SID1_TOP_INST_CLOCK_ENABLE_SID_SID_CORE_CLOCK_ENABLE_SID_DEFAULT 0x00000001
-
-/***************************************************************************
- *AVD_SID1_TOP_INST_CLOCK_ENABLE_SID_STATUS - Clock Enable Status
- ***************************************************************************/
-/* CLKGEN :: AVD_SID1_TOP_INST_CLOCK_ENABLE_SID_STATUS :: reserved0 [31:01] */
-#define BCHP_CLKGEN_AVD_SID1_TOP_INST_CLOCK_ENABLE_SID_STATUS_reserved0_MASK 0xfffffffe
-#define BCHP_CLKGEN_AVD_SID1_TOP_INST_CLOCK_ENABLE_SID_STATUS_reserved0_SHIFT 1
-
-/* CLKGEN :: AVD_SID1_TOP_INST_CLOCK_ENABLE_SID_STATUS :: SID_CORE_CLOCK_ENABLE_SID_STATUS [00:00] */
-#define BCHP_CLKGEN_AVD_SID1_TOP_INST_CLOCK_ENABLE_SID_STATUS_SID_CORE_CLOCK_ENABLE_SID_STATUS_MASK 0x00000001
-#define BCHP_CLKGEN_AVD_SID1_TOP_INST_CLOCK_ENABLE_SID_STATUS_SID_CORE_CLOCK_ENABLE_SID_STATUS_SHIFT 0
-
-/***************************************************************************
- *AVD_SID1_TOP_INST_CLOCK_ENABLE_STATUS - Clock Enable Status
- ***************************************************************************/
-/* CLKGEN :: AVD_SID1_TOP_INST_CLOCK_ENABLE_STATUS :: reserved0 [31:05] */
-#define BCHP_CLKGEN_AVD_SID1_TOP_INST_CLOCK_ENABLE_STATUS_reserved0_MASK 0xffffffe0
-#define BCHP_CLKGEN_AVD_SID1_TOP_INST_CLOCK_ENABLE_STATUS_reserved0_SHIFT 5
-
-/* CLKGEN :: AVD_SID1_TOP_INST_CLOCK_ENABLE_STATUS :: AVD_SID1_SCB_CLOCK_ENABLE_STATUS [04:04] */
-#define BCHP_CLKGEN_AVD_SID1_TOP_INST_CLOCK_ENABLE_STATUS_AVD_SID1_SCB_CLOCK_ENABLE_STATUS_MASK 0x00000010
-#define BCHP_CLKGEN_AVD_SID1_TOP_INST_CLOCK_ENABLE_STATUS_AVD_SID1_SCB_CLOCK_ENABLE_STATUS_SHIFT 4
-
-/* CLKGEN :: AVD_SID1_TOP_INST_CLOCK_ENABLE_STATUS :: AVD_SID1_GISB_CLOCK_ENABLE_STATUS [03:03] */
-#define BCHP_CLKGEN_AVD_SID1_TOP_INST_CLOCK_ENABLE_STATUS_AVD_SID1_GISB_CLOCK_ENABLE_STATUS_MASK 0x00000008
-#define BCHP_CLKGEN_AVD_SID1_TOP_INST_CLOCK_ENABLE_STATUS_AVD_SID1_GISB_CLOCK_ENABLE_STATUS_SHIFT 3
-
-/* CLKGEN :: AVD_SID1_TOP_INST_CLOCK_ENABLE_STATUS :: AVD_SID1_CPU_CLOCK_ENABLE_STATUS [02:02] */
-#define BCHP_CLKGEN_AVD_SID1_TOP_INST_CLOCK_ENABLE_STATUS_AVD_SID1_CPU_CLOCK_ENABLE_STATUS_MASK 0x00000004
-#define BCHP_CLKGEN_AVD_SID1_TOP_INST_CLOCK_ENABLE_STATUS_AVD_SID1_CPU_CLOCK_ENABLE_STATUS_SHIFT 2
-
-/* CLKGEN :: AVD_SID1_TOP_INST_CLOCK_ENABLE_STATUS :: AVD_SID1_CORE_CLOCK_ENABLE_STATUS [01:01] */
-#define BCHP_CLKGEN_AVD_SID1_TOP_INST_CLOCK_ENABLE_STATUS_AVD_SID1_CORE_CLOCK_ENABLE_STATUS_MASK 0x00000002
-#define BCHP_CLKGEN_AVD_SID1_TOP_INST_CLOCK_ENABLE_STATUS_AVD_SID1_CORE_CLOCK_ENABLE_STATUS_SHIFT 1
-
-/* CLKGEN :: AVD_SID1_TOP_INST_CLOCK_ENABLE_STATUS :: AVD_SID1_54_CLOCK_ENABLE_STATUS [00:00] */
-#define BCHP_CLKGEN_AVD_SID1_TOP_INST_CLOCK_ENABLE_STATUS_AVD_SID1_54_CLOCK_ENABLE_STATUS_MASK 0x00000001
-#define BCHP_CLKGEN_AVD_SID1_TOP_INST_CLOCK_ENABLE_STATUS_AVD_SID1_54_CLOCK_ENABLE_STATUS_SHIFT 0
-
-/***************************************************************************
- *AVD_SID1_TOP_INST_OBSERVE_CLOCK - Avd sid1 top inst observe clock
- ***************************************************************************/
-/* CLKGEN :: AVD_SID1_TOP_INST_OBSERVE_CLOCK :: reserved0 [31:06] */
-#define BCHP_CLKGEN_AVD_SID1_TOP_INST_OBSERVE_CLOCK_reserved0_MASK 0xffffffc0
-#define BCHP_CLKGEN_AVD_SID1_TOP_INST_OBSERVE_CLOCK_reserved0_SHIFT 6
-
-/* CLKGEN :: AVD_SID1_TOP_INST_OBSERVE_CLOCK :: AVD_SID1_ENABLE_OBSERVE_CLOCK [05:05] */
-#define BCHP_CLKGEN_AVD_SID1_TOP_INST_OBSERVE_CLOCK_AVD_SID1_ENABLE_OBSERVE_CLOCK_MASK 0x00000020
-#define BCHP_CLKGEN_AVD_SID1_TOP_INST_OBSERVE_CLOCK_AVD_SID1_ENABLE_OBSERVE_CLOCK_SHIFT 5
-#define BCHP_CLKGEN_AVD_SID1_TOP_INST_OBSERVE_CLOCK_AVD_SID1_ENABLE_OBSERVE_CLOCK_DEFAULT 0x00000000
-
-/* CLKGEN :: AVD_SID1_TOP_INST_OBSERVE_CLOCK :: AVD_SID1_ENABLE_DIVIDER_OBSERVE_CLOCK [04:04] */
-#define BCHP_CLKGEN_AVD_SID1_TOP_INST_OBSERVE_CLOCK_AVD_SID1_ENABLE_DIVIDER_OBSERVE_CLOCK_MASK 0x00000010
-#define BCHP_CLKGEN_AVD_SID1_TOP_INST_OBSERVE_CLOCK_AVD_SID1_ENABLE_DIVIDER_OBSERVE_CLOCK_SHIFT 4
-#define BCHP_CLKGEN_AVD_SID1_TOP_INST_OBSERVE_CLOCK_AVD_SID1_ENABLE_DIVIDER_OBSERVE_CLOCK_DEFAULT 0x00000000
-
-/* CLKGEN :: AVD_SID1_TOP_INST_OBSERVE_CLOCK :: AVD_SID1_CONTROL_OBSERVE_CLOCK [03:00] */
-#define BCHP_CLKGEN_AVD_SID1_TOP_INST_OBSERVE_CLOCK_AVD_SID1_CONTROL_OBSERVE_CLOCK_MASK 0x0000000f
-#define BCHP_CLKGEN_AVD_SID1_TOP_INST_OBSERVE_CLOCK_AVD_SID1_CONTROL_OBSERVE_CLOCK_SHIFT 0
-#define BCHP_CLKGEN_AVD_SID1_TOP_INST_OBSERVE_CLOCK_AVD_SID1_CONTROL_OBSERVE_CLOCK_DEFAULT 0x00000000
-
-/***************************************************************************
- *BVN_MVP_TOP_INST_CLOCK_ENABLE - Bvn mvp top inst clock enable
- ***************************************************************************/
-/* CLKGEN :: BVN_MVP_TOP_INST_CLOCK_ENABLE :: reserved0 [31:04] */
-#define BCHP_CLKGEN_BVN_MVP_TOP_INST_CLOCK_ENABLE_reserved0_MASK 0xfffffff0
-#define BCHP_CLKGEN_BVN_MVP_TOP_INST_CLOCK_ENABLE_reserved0_SHIFT 4
-
-/* CLKGEN :: BVN_MVP_TOP_INST_CLOCK_ENABLE :: BVND_SCB_CLOCK_ENABLE [03:03] */
-#define BCHP_CLKGEN_BVN_MVP_TOP_INST_CLOCK_ENABLE_BVND_SCB_CLOCK_ENABLE_MASK 0x00000008
-#define BCHP_CLKGEN_BVN_MVP_TOP_INST_CLOCK_ENABLE_BVND_SCB_CLOCK_ENABLE_SHIFT 3
-#define BCHP_CLKGEN_BVN_MVP_TOP_INST_CLOCK_ENABLE_BVND_SCB_CLOCK_ENABLE_DEFAULT 0x00000001
-
-/* CLKGEN :: BVN_MVP_TOP_INST_CLOCK_ENABLE :: BVND_BVB_CLOCK_ENABLE [02:02] */
-#define BCHP_CLKGEN_BVN_MVP_TOP_INST_CLOCK_ENABLE_BVND_BVB_CLOCK_ENABLE_MASK 0x00000004
-#define BCHP_CLKGEN_BVN_MVP_TOP_INST_CLOCK_ENABLE_BVND_BVB_CLOCK_ENABLE_SHIFT 2
-#define BCHP_CLKGEN_BVN_MVP_TOP_INST_CLOCK_ENABLE_BVND_BVB_CLOCK_ENABLE_DEFAULT 0x00000001
-
-/* CLKGEN :: BVN_MVP_TOP_INST_CLOCK_ENABLE :: BVND_54_CLOCK_ENABLE [01:01] */
-#define BCHP_CLKGEN_BVN_MVP_TOP_INST_CLOCK_ENABLE_BVND_54_CLOCK_ENABLE_MASK 0x00000002
-#define BCHP_CLKGEN_BVN_MVP_TOP_INST_CLOCK_ENABLE_BVND_54_CLOCK_ENABLE_SHIFT 1
-#define BCHP_CLKGEN_BVN_MVP_TOP_INST_CLOCK_ENABLE_BVND_54_CLOCK_ENABLE_DEFAULT 0x00000001
-
-/* CLKGEN :: BVN_MVP_TOP_INST_CLOCK_ENABLE :: BVND_108_CLOCK_ENABLE [00:00] */
-#define BCHP_CLKGEN_BVN_MVP_TOP_INST_CLOCK_ENABLE_BVND_108_CLOCK_ENABLE_MASK 0x00000001
-#define BCHP_CLKGEN_BVN_MVP_TOP_INST_CLOCK_ENABLE_BVND_108_CLOCK_ENABLE_SHIFT 0
-#define BCHP_CLKGEN_BVN_MVP_TOP_INST_CLOCK_ENABLE_BVND_108_CLOCK_ENABLE_DEFAULT 0x00000001
-
-/***************************************************************************
- *BVN_MVP_TOP_INST_CLOCK_ENABLE_STATUS - Clock Enable Status
- ***************************************************************************/
-/* CLKGEN :: BVN_MVP_TOP_INST_CLOCK_ENABLE_STATUS :: reserved0 [31:04] */
-#define BCHP_CLKGEN_BVN_MVP_TOP_INST_CLOCK_ENABLE_STATUS_reserved0_MASK 0xfffffff0
-#define BCHP_CLKGEN_BVN_MVP_TOP_INST_CLOCK_ENABLE_STATUS_reserved0_SHIFT 4
-
-/* CLKGEN :: BVN_MVP_TOP_INST_CLOCK_ENABLE_STATUS :: BVND_SCB_CLOCK_ENABLE_STATUS [03:03] */
-#define BCHP_CLKGEN_BVN_MVP_TOP_INST_CLOCK_ENABLE_STATUS_BVND_SCB_CLOCK_ENABLE_STATUS_MASK 0x00000008
-#define BCHP_CLKGEN_BVN_MVP_TOP_INST_CLOCK_ENABLE_STATUS_BVND_SCB_CLOCK_ENABLE_STATUS_SHIFT 3
-
-/* CLKGEN :: BVN_MVP_TOP_INST_CLOCK_ENABLE_STATUS :: BVND_BVB_CLOCK_ENABLE_STATUS [02:02] */
-#define BCHP_CLKGEN_BVN_MVP_TOP_INST_CLOCK_ENABLE_STATUS_BVND_BVB_CLOCK_ENABLE_STATUS_MASK 0x00000004
-#define BCHP_CLKGEN_BVN_MVP_TOP_INST_CLOCK_ENABLE_STATUS_BVND_BVB_CLOCK_ENABLE_STATUS_SHIFT 2
-
-/* CLKGEN :: BVN_MVP_TOP_INST_CLOCK_ENABLE_STATUS :: BVND_54_CLOCK_ENABLE_STATUS [01:01] */
-#define BCHP_CLKGEN_BVN_MVP_TOP_INST_CLOCK_ENABLE_STATUS_BVND_54_CLOCK_ENABLE_STATUS_MASK 0x00000002
-#define BCHP_CLKGEN_BVN_MVP_TOP_INST_CLOCK_ENABLE_STATUS_BVND_54_CLOCK_ENABLE_STATUS_SHIFT 1
-
-/* CLKGEN :: BVN_MVP_TOP_INST_CLOCK_ENABLE_STATUS :: BVND_108_CLOCK_ENABLE_STATUS [00:00] */
-#define BCHP_CLKGEN_BVN_MVP_TOP_INST_CLOCK_ENABLE_STATUS_BVND_108_CLOCK_ENABLE_STATUS_MASK 0x00000001
-#define BCHP_CLKGEN_BVN_MVP_TOP_INST_CLOCK_ENABLE_STATUS_BVND_108_CLOCK_ENABLE_STATUS_SHIFT 0
-
-/***************************************************************************
- *BVN_TOP_INST_CLOCK_ENABLE - Bvn top inst clock enable
- ***************************************************************************/
-/* CLKGEN :: BVN_TOP_INST_CLOCK_ENABLE :: reserved0 [31:04] */
-#define BCHP_CLKGEN_BVN_TOP_INST_CLOCK_ENABLE_reserved0_MASK 0xfffffff0
-#define BCHP_CLKGEN_BVN_TOP_INST_CLOCK_ENABLE_reserved0_SHIFT 4
-
-/* CLKGEN :: BVN_TOP_INST_CLOCK_ENABLE :: BVN_SCB_CLOCK_ENABLE [03:03] */
-#define BCHP_CLKGEN_BVN_TOP_INST_CLOCK_ENABLE_BVN_SCB_CLOCK_ENABLE_MASK 0x00000008
-#define BCHP_CLKGEN_BVN_TOP_INST_CLOCK_ENABLE_BVN_SCB_CLOCK_ENABLE_SHIFT 3
-#define BCHP_CLKGEN_BVN_TOP_INST_CLOCK_ENABLE_BVN_SCB_CLOCK_ENABLE_DEFAULT 0x00000001
-
-/* CLKGEN :: BVN_TOP_INST_CLOCK_ENABLE :: BVN_GISB_CLOCK_ENABLE [02:02] */
-#define BCHP_CLKGEN_BVN_TOP_INST_CLOCK_ENABLE_BVN_GISB_CLOCK_ENABLE_MASK 0x00000004
-#define BCHP_CLKGEN_BVN_TOP_INST_CLOCK_ENABLE_BVN_GISB_CLOCK_ENABLE_SHIFT 2
-#define BCHP_CLKGEN_BVN_TOP_INST_CLOCK_ENABLE_BVN_GISB_CLOCK_ENABLE_DEFAULT 0x00000001
-
-/* CLKGEN :: BVN_TOP_INST_CLOCK_ENABLE :: BVN_BVB_CLOCK_ENABLE [01:01] */
-#define BCHP_CLKGEN_BVN_TOP_INST_CLOCK_ENABLE_BVN_BVB_CLOCK_ENABLE_MASK 0x00000002
-#define BCHP_CLKGEN_BVN_TOP_INST_CLOCK_ENABLE_BVN_BVB_CLOCK_ENABLE_SHIFT 1
-#define BCHP_CLKGEN_BVN_TOP_INST_CLOCK_ENABLE_BVN_BVB_CLOCK_ENABLE_DEFAULT 0x00000001
-
-/* CLKGEN :: BVN_TOP_INST_CLOCK_ENABLE :: BVN_54_CLOCK_ENABLE [00:00] */
-#define BCHP_CLKGEN_BVN_TOP_INST_CLOCK_ENABLE_BVN_54_CLOCK_ENABLE_MASK 0x00000001
-#define BCHP_CLKGEN_BVN_TOP_INST_CLOCK_ENABLE_BVN_54_CLOCK_ENABLE_SHIFT 0
-#define BCHP_CLKGEN_BVN_TOP_INST_CLOCK_ENABLE_BVN_54_CLOCK_ENABLE_DEFAULT 0x00000001
-
-/***************************************************************************
- *BVN_TOP_INST_CLOCK_ENABLE_STATUS - Clock Enable Status
- ***************************************************************************/
-/* CLKGEN :: BVN_TOP_INST_CLOCK_ENABLE_STATUS :: reserved0 [31:04] */
-#define BCHP_CLKGEN_BVN_TOP_INST_CLOCK_ENABLE_STATUS_reserved0_MASK 0xfffffff0
-#define BCHP_CLKGEN_BVN_TOP_INST_CLOCK_ENABLE_STATUS_reserved0_SHIFT 4
-
-/* CLKGEN :: BVN_TOP_INST_CLOCK_ENABLE_STATUS :: BVN_SCB_CLOCK_ENABLE_STATUS [03:03] */
-#define BCHP_CLKGEN_BVN_TOP_INST_CLOCK_ENABLE_STATUS_BVN_SCB_CLOCK_ENABLE_STATUS_MASK 0x00000008
-#define BCHP_CLKGEN_BVN_TOP_INST_CLOCK_ENABLE_STATUS_BVN_SCB_CLOCK_ENABLE_STATUS_SHIFT 3
-
-/* CLKGEN :: BVN_TOP_INST_CLOCK_ENABLE_STATUS :: BVN_GISB_CLOCK_ENABLE_STATUS [02:02] */
-#define BCHP_CLKGEN_BVN_TOP_INST_CLOCK_ENABLE_STATUS_BVN_GISB_CLOCK_ENABLE_STATUS_MASK 0x00000004
-#define BCHP_CLKGEN_BVN_TOP_INST_CLOCK_ENABLE_STATUS_BVN_GISB_CLOCK_ENABLE_STATUS_SHIFT 2
-
-/* CLKGEN :: BVN_TOP_INST_CLOCK_ENABLE_STATUS :: BVN_BVB_CLOCK_ENABLE_STATUS [01:01] */
-#define BCHP_CLKGEN_BVN_TOP_INST_CLOCK_ENABLE_STATUS_BVN_BVB_CLOCK_ENABLE_STATUS_MASK 0x00000002
-#define BCHP_CLKGEN_BVN_TOP_INST_CLOCK_ENABLE_STATUS_BVN_BVB_CLOCK_ENABLE_STATUS_SHIFT 1
-
-/* CLKGEN :: BVN_TOP_INST_CLOCK_ENABLE_STATUS :: BVN_54_CLOCK_ENABLE_STATUS [00:00] */
-#define BCHP_CLKGEN_BVN_TOP_INST_CLOCK_ENABLE_STATUS_BVN_54_CLOCK_ENABLE_STATUS_MASK 0x00000001
-#define BCHP_CLKGEN_BVN_TOP_INST_CLOCK_ENABLE_STATUS_BVN_54_CLOCK_ENABLE_STATUS_SHIFT 0
-
-/***************************************************************************
- *CLKGEN_CLOCK_DISABLE - Disable CLKGEN's clocks
- ***************************************************************************/
-/* CLKGEN :: CLKGEN_CLOCK_DISABLE :: reserved0 [31:01] */
-#define BCHP_CLKGEN_CLKGEN_CLOCK_DISABLE_reserved0_MASK 0xfffffffe
-#define BCHP_CLKGEN_CLKGEN_CLOCK_DISABLE_reserved0_SHIFT 1
-
-/* CLKGEN :: CLKGEN_CLOCK_DISABLE :: DISABLE_OSC_DIGITAL_CLOCK [00:00] */
-#define BCHP_CLKGEN_CLKGEN_CLOCK_DISABLE_DISABLE_OSC_DIGITAL_CLOCK_MASK 0x00000001
-#define BCHP_CLKGEN_CLKGEN_CLOCK_DISABLE_DISABLE_OSC_DIGITAL_CLOCK_SHIFT 0
-#define BCHP_CLKGEN_CLKGEN_CLOCK_DISABLE_DISABLE_OSC_DIGITAL_CLOCK_DEFAULT 0x00000000
-
-/***************************************************************************
- *CLKGEN_CLOCK_DISABLE_STATUS - Clock Disable Status
- ***************************************************************************/
-/* CLKGEN :: CLKGEN_CLOCK_DISABLE_STATUS :: reserved0 [31:01] */
-#define BCHP_CLKGEN_CLKGEN_CLOCK_DISABLE_STATUS_reserved0_MASK 0xfffffffe
-#define BCHP_CLKGEN_CLKGEN_CLOCK_DISABLE_STATUS_reserved0_SHIFT 1
-
-/* CLKGEN :: CLKGEN_CLOCK_DISABLE_STATUS :: DISABLE_OSC_DIGITAL_CLOCK_STATUS [00:00] */
-#define BCHP_CLKGEN_CLKGEN_CLOCK_DISABLE_STATUS_DISABLE_OSC_DIGITAL_CLOCK_STATUS_MASK 0x00000001
-#define BCHP_CLKGEN_CLKGEN_CLOCK_DISABLE_STATUS_DISABLE_OSC_DIGITAL_CLOCK_STATUS_SHIFT 0
-
-/***************************************************************************
- *CLKGEN_INST_CLOCK_ENABLE - Clkgen inst clock enable
- ***************************************************************************/
-/* CLKGEN :: CLKGEN_INST_CLOCK_ENABLE :: reserved0 [31:03] */
-#define BCHP_CLKGEN_CLKGEN_INST_CLOCK_ENABLE_reserved0_MASK 0xfffffff8
-#define BCHP_CLKGEN_CLKGEN_INST_CLOCK_ENABLE_reserved0_SHIFT 3
-
-/* CLKGEN :: CLKGEN_INST_CLOCK_ENABLE :: CG_TP_CLOCK_ENABLE [02:02] */
-#define BCHP_CLKGEN_CLKGEN_INST_CLOCK_ENABLE_CG_TP_CLOCK_ENABLE_MASK 0x00000004
-#define BCHP_CLKGEN_CLKGEN_INST_CLOCK_ENABLE_CG_TP_CLOCK_ENABLE_SHIFT 2
-#define BCHP_CLKGEN_CLKGEN_INST_CLOCK_ENABLE_CG_TP_CLOCK_ENABLE_DEFAULT 0x00000001
-
-/* CLKGEN :: CLKGEN_INST_CLOCK_ENABLE :: CG_GISB_CLOCK_ENABLE [01:01] */
-#define BCHP_CLKGEN_CLKGEN_INST_CLOCK_ENABLE_CG_GISB_CLOCK_ENABLE_MASK 0x00000002
-#define BCHP_CLKGEN_CLKGEN_INST_CLOCK_ENABLE_CG_GISB_CLOCK_ENABLE_SHIFT 1
-#define BCHP_CLKGEN_CLKGEN_INST_CLOCK_ENABLE_CG_GISB_CLOCK_ENABLE_DEFAULT 0x00000001
-
-/* CLKGEN :: CLKGEN_INST_CLOCK_ENABLE :: CG_54_CLOCK_ENABLE [00:00] */
-#define BCHP_CLKGEN_CLKGEN_INST_CLOCK_ENABLE_CG_54_CLOCK_ENABLE_MASK 0x00000001
-#define BCHP_CLKGEN_CLKGEN_INST_CLOCK_ENABLE_CG_54_CLOCK_ENABLE_SHIFT 0
-#define BCHP_CLKGEN_CLKGEN_INST_CLOCK_ENABLE_CG_54_CLOCK_ENABLE_DEFAULT 0x00000001
-
-/***************************************************************************
- *CLKGEN_INST_CLOCK_ENABLE_STATUS - Clock Enable Status
- ***************************************************************************/
-/* CLKGEN :: CLKGEN_INST_CLOCK_ENABLE_STATUS :: reserved0 [31:03] */
-#define BCHP_CLKGEN_CLKGEN_INST_CLOCK_ENABLE_STATUS_reserved0_MASK 0xfffffff8
-#define BCHP_CLKGEN_CLKGEN_INST_CLOCK_ENABLE_STATUS_reserved0_SHIFT 3
-
-/* CLKGEN :: CLKGEN_INST_CLOCK_ENABLE_STATUS :: CG_TP_CLOCK_ENABLE_STATUS [02:02] */
-#define BCHP_CLKGEN_CLKGEN_INST_CLOCK_ENABLE_STATUS_CG_TP_CLOCK_ENABLE_STATUS_MASK 0x00000004
-#define BCHP_CLKGEN_CLKGEN_INST_CLOCK_ENABLE_STATUS_CG_TP_CLOCK_ENABLE_STATUS_SHIFT 2
-
-/* CLKGEN :: CLKGEN_INST_CLOCK_ENABLE_STATUS :: CG_GISB_CLOCK_ENABLE_STATUS [01:01] */
-#define BCHP_CLKGEN_CLKGEN_INST_CLOCK_ENABLE_STATUS_CG_GISB_CLOCK_ENABLE_STATUS_MASK 0x00000002
-#define BCHP_CLKGEN_CLKGEN_INST_CLOCK_ENABLE_STATUS_CG_GISB_CLOCK_ENABLE_STATUS_SHIFT 1
-
-/* CLKGEN :: CLKGEN_INST_CLOCK_ENABLE_STATUS :: CG_54_CLOCK_ENABLE_STATUS [00:00] */
-#define BCHP_CLKGEN_CLKGEN_INST_CLOCK_ENABLE_STATUS_CG_54_CLOCK_ENABLE_STATUS_MASK 0x00000001
-#define BCHP_CLKGEN_CLKGEN_INST_CLOCK_ENABLE_STATUS_CG_54_CLOCK_ENABLE_STATUS_SHIFT 0
-
-/***************************************************************************
- *CLOCK_MONITOR_CONTROL - Clock Monitor Control
- ***************************************************************************/
-/* CLKGEN :: CLOCK_MONITOR_CONTROL :: reserved0 [31:04] */
-#define BCHP_CLKGEN_CLOCK_MONITOR_CONTROL_reserved0_MASK 0xfffffff0
-#define BCHP_CLKGEN_CLOCK_MONITOR_CONTROL_reserved0_SHIFT 4
-
-/* CLKGEN :: CLOCK_MONITOR_CONTROL :: STOP_VIEW_COUNTER [03:03] */
-#define BCHP_CLKGEN_CLOCK_MONITOR_CONTROL_STOP_VIEW_COUNTER_MASK 0x00000008
-#define BCHP_CLKGEN_CLOCK_MONITOR_CONTROL_STOP_VIEW_COUNTER_SHIFT 3
-#define BCHP_CLKGEN_CLOCK_MONITOR_CONTROL_STOP_VIEW_COUNTER_DEFAULT 0x00000001
-
-/* CLKGEN :: CLOCK_MONITOR_CONTROL :: STOP_REF_COUNTER [02:02] */
-#define BCHP_CLKGEN_CLOCK_MONITOR_CONTROL_STOP_REF_COUNTER_MASK 0x00000004
-#define BCHP_CLKGEN_CLOCK_MONITOR_CONTROL_STOP_REF_COUNTER_SHIFT 2
-#define BCHP_CLKGEN_CLOCK_MONITOR_CONTROL_STOP_REF_COUNTER_DEFAULT 0x00000001
-
-/* CLKGEN :: CLOCK_MONITOR_CONTROL :: RESET_COUNTERS [01:01] */
-#define BCHP_CLKGEN_CLOCK_MONITOR_CONTROL_RESET_COUNTERS_MASK 0x00000002
-#define BCHP_CLKGEN_CLOCK_MONITOR_CONTROL_RESET_COUNTERS_SHIFT 1
-#define BCHP_CLKGEN_CLOCK_MONITOR_CONTROL_RESET_COUNTERS_DEFAULT 0x00000001
-
-/* CLKGEN :: CLOCK_MONITOR_CONTROL :: LAUNCH_AUTO_REF_COUNT [00:00] */
-#define BCHP_CLKGEN_CLOCK_MONITOR_CONTROL_LAUNCH_AUTO_REF_COUNT_MASK 0x00000001
-#define BCHP_CLKGEN_CLOCK_MONITOR_CONTROL_LAUNCH_AUTO_REF_COUNT_SHIFT 0
-#define BCHP_CLKGEN_CLOCK_MONITOR_CONTROL_LAUNCH_AUTO_REF_COUNT_DEFAULT 0x00000001
-
-/***************************************************************************
- *CLOCK_MONITOR_MAX_COUNT - Clock Monitor Max Reference Count
- ***************************************************************************/
-/* CLKGEN :: CLOCK_MONITOR_MAX_COUNT :: SET_MAX_REF_COUNT [31:00] */
-#define BCHP_CLKGEN_CLOCK_MONITOR_MAX_COUNT_SET_MAX_REF_COUNT_MASK 0xffffffff
-#define BCHP_CLKGEN_CLOCK_MONITOR_MAX_COUNT_SET_MAX_REF_COUNT_SHIFT 0
-#define BCHP_CLKGEN_CLOCK_MONITOR_MAX_COUNT_SET_MAX_REF_COUNT_DEFAULT 0xffffffff
-
-/***************************************************************************
- *CLOCK_MONITOR_REF_COUNTER - Clock Monitor Reference Counter
- ***************************************************************************/
-/* CLKGEN :: CLOCK_MONITOR_REF_COUNTER :: READ_MAX_COUNT [31:00] */
-#define BCHP_CLKGEN_CLOCK_MONITOR_REF_COUNTER_READ_MAX_COUNT_MASK 0xffffffff
-#define BCHP_CLKGEN_CLOCK_MONITOR_REF_COUNTER_READ_MAX_COUNT_SHIFT 0
-
-/***************************************************************************
- *CLOCK_MONITOR_REF_DONE - Clock Monitor Reference Counter
- ***************************************************************************/
-/* CLKGEN :: CLOCK_MONITOR_REF_DONE :: reserved0 [31:01] */
-#define BCHP_CLKGEN_CLOCK_MONITOR_REF_DONE_reserved0_MASK 0xfffffffe
-#define BCHP_CLKGEN_CLOCK_MONITOR_REF_DONE_reserved0_SHIFT 1
-
-/* CLKGEN :: CLOCK_MONITOR_REF_DONE :: REF_COUNT_DONE [00:00] */
-#define BCHP_CLKGEN_CLOCK_MONITOR_REF_DONE_REF_COUNT_DONE_MASK 0x00000001
-#define BCHP_CLKGEN_CLOCK_MONITOR_REF_DONE_REF_COUNT_DONE_SHIFT 0
-
-/***************************************************************************
- *CLOCK_MONITOR_VIEW_COUNTER - Clock Monitor View Counter
- ***************************************************************************/
-/* CLKGEN :: CLOCK_MONITOR_VIEW_COUNTER :: READ_MAX_COUNT [31:00] */
-#define BCHP_CLKGEN_CLOCK_MONITOR_VIEW_COUNTER_READ_MAX_COUNT_MASK 0xffffffff
-#define BCHP_CLKGEN_CLOCK_MONITOR_VIEW_COUNTER_READ_MAX_COUNT_SHIFT 0
-
-/***************************************************************************
- *CORE_XPT_INST_CLOCK_ENABLE - Core xpt inst clock enable
- ***************************************************************************/
-/* CLKGEN :: CORE_XPT_INST_CLOCK_ENABLE :: reserved0 [31:05] */
-#define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_ENABLE_reserved0_MASK 0xffffffe0
-#define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_ENABLE_reserved0_SHIFT 5
-
-/* CLKGEN :: CORE_XPT_INST_CLOCK_ENABLE :: XPT_SCB_CLOCK_ENABLE [04:04] */
-#define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_ENABLE_XPT_SCB_CLOCK_ENABLE_MASK 0x00000010
-#define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_ENABLE_XPT_SCB_CLOCK_ENABLE_SHIFT 4
-#define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_ENABLE_XPT_SCB_CLOCK_ENABLE_DEFAULT 0x00000001
-
-/* CLKGEN :: CORE_XPT_INST_CLOCK_ENABLE :: XPT_GISB_CLOCK_ENABLE [03:03] */
-#define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_ENABLE_XPT_GISB_CLOCK_ENABLE_MASK 0x00000008
-#define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_ENABLE_XPT_GISB_CLOCK_ENABLE_SHIFT 3
-#define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_ENABLE_XPT_GISB_CLOCK_ENABLE_DEFAULT 0x00000001
-
-/* CLKGEN :: CORE_XPT_INST_CLOCK_ENABLE :: XPT_CORE_CLOCK_ENABLE [02:02] */
-#define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_ENABLE_XPT_CORE_CLOCK_ENABLE_MASK 0x00000004
-#define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_ENABLE_XPT_CORE_CLOCK_ENABLE_SHIFT 2
-#define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_ENABLE_XPT_CORE_CLOCK_ENABLE_DEFAULT 0x00000001
-
-/* CLKGEN :: CORE_XPT_INST_CLOCK_ENABLE :: XPT_54_CLOCK_ENABLE [01:01] */
-#define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_ENABLE_XPT_54_CLOCK_ENABLE_MASK 0x00000002
-#define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_ENABLE_XPT_54_CLOCK_ENABLE_SHIFT 1
-#define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_ENABLE_XPT_54_CLOCK_ENABLE_DEFAULT 0x00000001
-
-/* CLKGEN :: CORE_XPT_INST_CLOCK_ENABLE :: XPT_108_CLOCK_ENABLE [00:00] */
-#define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_ENABLE_XPT_108_CLOCK_ENABLE_MASK 0x00000001
-#define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_ENABLE_XPT_108_CLOCK_ENABLE_SHIFT 0
-#define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_ENABLE_XPT_108_CLOCK_ENABLE_DEFAULT 0x00000001
-
-/***************************************************************************
- *CORE_XPT_INST_CLOCK_ENABLE_STATUS - Clock Enable Status
- ***************************************************************************/
-/* CLKGEN :: CORE_XPT_INST_CLOCK_ENABLE_STATUS :: reserved0 [31:05] */
-#define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_ENABLE_STATUS_reserved0_MASK 0xffffffe0
-#define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_ENABLE_STATUS_reserved0_SHIFT 5
-
-/* CLKGEN :: CORE_XPT_INST_CLOCK_ENABLE_STATUS :: XPT_SCB_CLOCK_ENABLE_STATUS [04:04] */
-#define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_ENABLE_STATUS_XPT_SCB_CLOCK_ENABLE_STATUS_MASK 0x00000010
-#define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_ENABLE_STATUS_XPT_SCB_CLOCK_ENABLE_STATUS_SHIFT 4
-
-/* CLKGEN :: CORE_XPT_INST_CLOCK_ENABLE_STATUS :: XPT_GISB_CLOCK_ENABLE_STATUS [03:03] */
-#define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_ENABLE_STATUS_XPT_GISB_CLOCK_ENABLE_STATUS_MASK 0x00000008
-#define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_ENABLE_STATUS_XPT_GISB_CLOCK_ENABLE_STATUS_SHIFT 3
-
-/* CLKGEN :: CORE_XPT_INST_CLOCK_ENABLE_STATUS :: XPT_CORE_CLOCK_ENABLE_STATUS [02:02] */
-#define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_ENABLE_STATUS_XPT_CORE_CLOCK_ENABLE_STATUS_MASK 0x00000004
-#define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_ENABLE_STATUS_XPT_CORE_CLOCK_ENABLE_STATUS_SHIFT 2
-
-/* CLKGEN :: CORE_XPT_INST_CLOCK_ENABLE_STATUS :: XPT_54_CLOCK_ENABLE_STATUS [01:01] */
-#define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_ENABLE_STATUS_XPT_54_CLOCK_ENABLE_STATUS_MASK 0x00000002
-#define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_ENABLE_STATUS_XPT_54_CLOCK_ENABLE_STATUS_SHIFT 1
-
-/* CLKGEN :: CORE_XPT_INST_CLOCK_ENABLE_STATUS :: XPT_108_CLOCK_ENABLE_STATUS [00:00] */
-#define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_ENABLE_STATUS_XPT_108_CLOCK_ENABLE_STATUS_MASK 0x00000001
-#define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_ENABLE_STATUS_XPT_108_CLOCK_ENABLE_STATUS_SHIFT 0
-
-/***************************************************************************
- *CORE_XPT_INST_OBSERVE_CLOCK - Core xpt inst observe clock
- ***************************************************************************/
-/* CLKGEN :: CORE_XPT_INST_OBSERVE_CLOCK :: reserved0 [31:06] */
-#define BCHP_CLKGEN_CORE_XPT_INST_OBSERVE_CLOCK_reserved0_MASK 0xffffffc0
-#define BCHP_CLKGEN_CORE_XPT_INST_OBSERVE_CLOCK_reserved0_SHIFT 6
-
-/* CLKGEN :: CORE_XPT_INST_OBSERVE_CLOCK :: XPT_ENABLE_OBSERVE_CLOCK [05:05] */
-#define BCHP_CLKGEN_CORE_XPT_INST_OBSERVE_CLOCK_XPT_ENABLE_OBSERVE_CLOCK_MASK 0x00000020
-#define BCHP_CLKGEN_CORE_XPT_INST_OBSERVE_CLOCK_XPT_ENABLE_OBSERVE_CLOCK_SHIFT 5
-#define BCHP_CLKGEN_CORE_XPT_INST_OBSERVE_CLOCK_XPT_ENABLE_OBSERVE_CLOCK_DEFAULT 0x00000000
-
-/* CLKGEN :: CORE_XPT_INST_OBSERVE_CLOCK :: XPT_ENABLE_DIVIDER_OBSERVE_CLOCK [04:04] */
-#define BCHP_CLKGEN_CORE_XPT_INST_OBSERVE_CLOCK_XPT_ENABLE_DIVIDER_OBSERVE_CLOCK_MASK 0x00000010
-#define BCHP_CLKGEN_CORE_XPT_INST_OBSERVE_CLOCK_XPT_ENABLE_DIVIDER_OBSERVE_CLOCK_SHIFT 4
-#define BCHP_CLKGEN_CORE_XPT_INST_OBSERVE_CLOCK_XPT_ENABLE_DIVIDER_OBSERVE_CLOCK_DEFAULT 0x00000000
-
-/* CLKGEN :: CORE_XPT_INST_OBSERVE_CLOCK :: XPT_CONTROL_OBSERVE_CLOCK [03:00] */
-#define BCHP_CLKGEN_CORE_XPT_INST_OBSERVE_CLOCK_XPT_CONTROL_OBSERVE_CLOCK_MASK 0x0000000f
-#define BCHP_CLKGEN_CORE_XPT_INST_OBSERVE_CLOCK_XPT_CONTROL_OBSERVE_CLOCK_SHIFT 0
-#define BCHP_CLKGEN_CORE_XPT_INST_OBSERVE_CLOCK_XPT_CONTROL_OBSERVE_CLOCK_DEFAULT 0x00000000
-
-/***************************************************************************
- *CPU4355_BCM_MIPS_TOP_INST_CLOCK_DISABLE - Disable CPU4355_BCM_MIPS_TOP_INST's clocks
- ***************************************************************************/
-/* CLKGEN :: CPU4355_BCM_MIPS_TOP_INST_CLOCK_DISABLE :: reserved0 [31:01] */
-#define BCHP_CLKGEN_CPU4355_BCM_MIPS_TOP_INST_CLOCK_DISABLE_reserved0_MASK 0xfffffffe
-#define BCHP_CLKGEN_CPU4355_BCM_MIPS_TOP_INST_CLOCK_DISABLE_reserved0_SHIFT 1
-
-/* CLKGEN :: CPU4355_BCM_MIPS_TOP_INST_CLOCK_DISABLE :: DISABLE_MIPS_MCLK_CLOCK [00:00] */
-#define BCHP_CLKGEN_CPU4355_BCM_MIPS_TOP_INST_CLOCK_DISABLE_DISABLE_MIPS_MCLK_CLOCK_MASK 0x00000001
-#define BCHP_CLKGEN_CPU4355_BCM_MIPS_TOP_INST_CLOCK_DISABLE_DISABLE_MIPS_MCLK_CLOCK_SHIFT 0
-#define BCHP_CLKGEN_CPU4355_BCM_MIPS_TOP_INST_CLOCK_DISABLE_DISABLE_MIPS_MCLK_CLOCK_DEFAULT 0x00000000
-
-/***************************************************************************
- *CPU4355_BCM_MIPS_TOP_INST_CLOCK_DISABLE_STATUS - Clock Disable Status
- ***************************************************************************/
-/* CLKGEN :: CPU4355_BCM_MIPS_TOP_INST_CLOCK_DISABLE_STATUS :: reserved0 [31:01] */
-#define BCHP_CLKGEN_CPU4355_BCM_MIPS_TOP_INST_CLOCK_DISABLE_STATUS_reserved0_MASK 0xfffffffe
-#define BCHP_CLKGEN_CPU4355_BCM_MIPS_TOP_INST_CLOCK_DISABLE_STATUS_reserved0_SHIFT 1
-
-/* CLKGEN :: CPU4355_BCM_MIPS_TOP_INST_CLOCK_DISABLE_STATUS :: DISABLE_MIPS_MCLK_CLOCK_STATUS [00:00] */
-#define BCHP_CLKGEN_CPU4355_BCM_MIPS_TOP_INST_CLOCK_DISABLE_STATUS_DISABLE_MIPS_MCLK_CLOCK_STATUS_MASK 0x00000001
-#define BCHP_CLKGEN_CPU4355_BCM_MIPS_TOP_INST_CLOCK_DISABLE_STATUS_DISABLE_MIPS_MCLK_CLOCK_STATUS_SHIFT 0
-
-/***************************************************************************
- *CPU4355_BCM_MIPS_TOP_INST_CLOCK_ENABLE - Cpu4355 bcm mips top inst clock enable
- ***************************************************************************/
-/* CLKGEN :: CPU4355_BCM_MIPS_TOP_INST_CLOCK_ENABLE :: reserved0 [31:02] */
-#define BCHP_CLKGEN_CPU4355_BCM_MIPS_TOP_INST_CLOCK_ENABLE_reserved0_MASK 0xfffffffc
-#define BCHP_CLKGEN_CPU4355_BCM_MIPS_TOP_INST_CLOCK_ENABLE_reserved0_SHIFT 2
-
-/* CLKGEN :: CPU4355_BCM_MIPS_TOP_INST_CLOCK_ENABLE :: MIPS_SCB_CLOCK_ENABLE [01:01] */
-#define BCHP_CLKGEN_CPU4355_BCM_MIPS_TOP_INST_CLOCK_ENABLE_MIPS_SCB_CLOCK_ENABLE_MASK 0x00000002
-#define BCHP_CLKGEN_CPU4355_BCM_MIPS_TOP_INST_CLOCK_ENABLE_MIPS_SCB_CLOCK_ENABLE_SHIFT 1
-#define BCHP_CLKGEN_CPU4355_BCM_MIPS_TOP_INST_CLOCK_ENABLE_MIPS_SCB_CLOCK_ENABLE_DEFAULT 0x00000001
-
-/* CLKGEN :: CPU4355_BCM_MIPS_TOP_INST_CLOCK_ENABLE :: MIPS_54_CLOCK_ENABLE [00:00] */
-#define BCHP_CLKGEN_CPU4355_BCM_MIPS_TOP_INST_CLOCK_ENABLE_MIPS_54_CLOCK_ENABLE_MASK 0x00000001
-#define BCHP_CLKGEN_CPU4355_BCM_MIPS_TOP_INST_CLOCK_ENABLE_MIPS_54_CLOCK_ENABLE_SHIFT 0
-#define BCHP_CLKGEN_CPU4355_BCM_MIPS_TOP_INST_CLOCK_ENABLE_MIPS_54_CLOCK_ENABLE_DEFAULT 0x00000001
-
-/***************************************************************************
- *CPU4355_BCM_MIPS_TOP_INST_CLOCK_ENABLE_STATUS - Clock Enable Status
- ***************************************************************************/
-/* CLKGEN :: CPU4355_BCM_MIPS_TOP_INST_CLOCK_ENABLE_STATUS :: reserved0 [31:02] */
-#define BCHP_CLKGEN_CPU4355_BCM_MIPS_TOP_INST_CLOCK_ENABLE_STATUS_reserved0_MASK 0xfffffffc
-#define BCHP_CLKGEN_CPU4355_BCM_MIPS_TOP_INST_CLOCK_ENABLE_STATUS_reserved0_SHIFT 2
-
-/* CLKGEN :: CPU4355_BCM_MIPS_TOP_INST_CLOCK_ENABLE_STATUS :: MIPS_SCB_CLOCK_ENABLE_STATUS [01:01] */
-#define BCHP_CLKGEN_CPU4355_BCM_MIPS_TOP_INST_CLOCK_ENABLE_STATUS_MIPS_SCB_CLOCK_ENABLE_STATUS_MASK 0x00000002
-#define BCHP_CLKGEN_CPU4355_BCM_MIPS_TOP_INST_CLOCK_ENABLE_STATUS_MIPS_SCB_CLOCK_ENABLE_STATUS_SHIFT 1
-
-/* CLKGEN :: CPU4355_BCM_MIPS_TOP_INST_CLOCK_ENABLE_STATUS :: MIPS_54_CLOCK_ENABLE_STATUS [00:00] */
-#define BCHP_CLKGEN_CPU4355_BCM_MIPS_TOP_INST_CLOCK_ENABLE_STATUS_MIPS_54_CLOCK_ENABLE_STATUS_MASK 0x00000001
-#define BCHP_CLKGEN_CPU4355_BCM_MIPS_TOP_INST_CLOCK_ENABLE_STATUS_MIPS_54_CLOCK_ENABLE_STATUS_SHIFT 0
-
-/***************************************************************************
- *D3DSMAC_X4_TOP_INST_CLOCK_DISABLE - Disable D3DSMAC_X4_TOP_INST's clocks
- ***************************************************************************/
-/* CLKGEN :: D3DSMAC_X4_TOP_INST_CLOCK_DISABLE :: reserved0 [31:02] */
-#define BCHP_CLKGEN_D3DSMAC_X4_TOP_INST_CLOCK_DISABLE_reserved0_MASK 0xfffffffc
-#define BCHP_CLKGEN_D3DSMAC_X4_TOP_INST_CLOCK_DISABLE_reserved0_SHIFT 2
-
-/* CLKGEN :: D3DSMAC_X4_TOP_INST_CLOCK_DISABLE :: DISABLE_DSMAC_MPEG_SCAN_CLOCK [01:01] */
-#define BCHP_CLKGEN_D3DSMAC_X4_TOP_INST_CLOCK_DISABLE_DISABLE_DSMAC_MPEG_SCAN_CLOCK_MASK 0x00000002
-#define BCHP_CLKGEN_D3DSMAC_X4_TOP_INST_CLOCK_DISABLE_DISABLE_DSMAC_MPEG_SCAN_CLOCK_SHIFT 1
-#define BCHP_CLKGEN_D3DSMAC_X4_TOP_INST_CLOCK_DISABLE_DISABLE_DSMAC_MPEG_SCAN_CLOCK_DEFAULT 0x00000000
-
-/* CLKGEN :: D3DSMAC_X4_TOP_INST_CLOCK_DISABLE :: DISABLE_DSMAC_MAC_CLOCK [00:00] */
-#define BCHP_CLKGEN_D3DSMAC_X4_TOP_INST_CLOCK_DISABLE_DISABLE_DSMAC_MAC_CLOCK_MASK 0x00000001
-#define BCHP_CLKGEN_D3DSMAC_X4_TOP_INST_CLOCK_DISABLE_DISABLE_DSMAC_MAC_CLOCK_SHIFT 0
-#define BCHP_CLKGEN_D3DSMAC_X4_TOP_INST_CLOCK_DISABLE_DISABLE_DSMAC_MAC_CLOCK_DEFAULT 0x00000000
-
-/***************************************************************************
- *D3DSMAC_X4_TOP_INST_CLOCK_DISABLE_STATUS - Clock Disable Status
- ***************************************************************************/
-/* CLKGEN :: D3DSMAC_X4_TOP_INST_CLOCK_DISABLE_STATUS :: reserved0 [31:02] */
-#define BCHP_CLKGEN_D3DSMAC_X4_TOP_INST_CLOCK_DISABLE_STATUS_reserved0_MASK 0xfffffffc
-#define BCHP_CLKGEN_D3DSMAC_X4_TOP_INST_CLOCK_DISABLE_STATUS_reserved0_SHIFT 2
-
-/* CLKGEN :: D3DSMAC_X4_TOP_INST_CLOCK_DISABLE_STATUS :: DISABLE_DSMAC_MPEG_SCAN_CLOCK_STATUS [01:01] */
-#define BCHP_CLKGEN_D3DSMAC_X4_TOP_INST_CLOCK_DISABLE_STATUS_DISABLE_DSMAC_MPEG_SCAN_CLOCK_STATUS_MASK 0x00000002
-#define BCHP_CLKGEN_D3DSMAC_X4_TOP_INST_CLOCK_DISABLE_STATUS_DISABLE_DSMAC_MPEG_SCAN_CLOCK_STATUS_SHIFT 1
-
-/* CLKGEN :: D3DSMAC_X4_TOP_INST_CLOCK_DISABLE_STATUS :: DISABLE_DSMAC_MAC_CLOCK_STATUS [00:00] */
-#define BCHP_CLKGEN_D3DSMAC_X4_TOP_INST_CLOCK_DISABLE_STATUS_DISABLE_DSMAC_MAC_CLOCK_STATUS_MASK 0x00000001
-#define BCHP_CLKGEN_D3DSMAC_X4_TOP_INST_CLOCK_DISABLE_STATUS_DISABLE_DSMAC_MAC_CLOCK_STATUS_SHIFT 0
-
-/***************************************************************************
- *D3DSMAC_X4_TOP_INST_CLOCK_ENABLE - D3dsmac x4 top inst clock enable
- ***************************************************************************/
-/* CLKGEN :: D3DSMAC_X4_TOP_INST_CLOCK_ENABLE :: reserved0 [31:02] */
-#define BCHP_CLKGEN_D3DSMAC_X4_TOP_INST_CLOCK_ENABLE_reserved0_MASK 0xfffffffc
-#define BCHP_CLKGEN_D3DSMAC_X4_TOP_INST_CLOCK_ENABLE_reserved0_SHIFT 2
-
-/* CLKGEN :: D3DSMAC_X4_TOP_INST_CLOCK_ENABLE :: DSMAC_SCB_CLOCK_ENABLE [01:01] */
-#define BCHP_CLKGEN_D3DSMAC_X4_TOP_INST_CLOCK_ENABLE_DSMAC_SCB_CLOCK_ENABLE_MASK 0x00000002
-#define BCHP_CLKGEN_D3DSMAC_X4_TOP_INST_CLOCK_ENABLE_DSMAC_SCB_CLOCK_ENABLE_SHIFT 1
-#define BCHP_CLKGEN_D3DSMAC_X4_TOP_INST_CLOCK_ENABLE_DSMAC_SCB_CLOCK_ENABLE_DEFAULT 0x00000001
-
-/* CLKGEN :: D3DSMAC_X4_TOP_INST_CLOCK_ENABLE :: DSMAC_54_CLOCK_ENABLE [00:00] */
-#define BCHP_CLKGEN_D3DSMAC_X4_TOP_INST_CLOCK_ENABLE_DSMAC_54_CLOCK_ENABLE_MASK 0x00000001
-#define BCHP_CLKGEN_D3DSMAC_X4_TOP_INST_CLOCK_ENABLE_DSMAC_54_CLOCK_ENABLE_SHIFT 0
-#define BCHP_CLKGEN_D3DSMAC_X4_TOP_INST_CLOCK_ENABLE_DSMAC_54_CLOCK_ENABLE_DEFAULT 0x00000001
-
-/***************************************************************************
- *D3DSMAC_X4_TOP_INST_CLOCK_ENABLE_STATUS - Clock Enable Status
- ***************************************************************************/
-/* CLKGEN :: D3DSMAC_X4_TOP_INST_CLOCK_ENABLE_STATUS :: reserved0 [31:02] */
-#define BCHP_CLKGEN_D3DSMAC_X4_TOP_INST_CLOCK_ENABLE_STATUS_reserved0_MASK 0xfffffffc
-#define BCHP_CLKGEN_D3DSMAC_X4_TOP_INST_CLOCK_ENABLE_STATUS_reserved0_SHIFT 2
-
-/* CLKGEN :: D3DSMAC_X4_TOP_INST_CLOCK_ENABLE_STATUS :: DSMAC_SCB_CLOCK_ENABLE_STATUS [01:01] */
-#define BCHP_CLKGEN_D3DSMAC_X4_TOP_INST_CLOCK_ENABLE_STATUS_DSMAC_SCB_CLOCK_ENABLE_STATUS_MASK 0x00000002
-#define BCHP_CLKGEN_D3DSMAC_X4_TOP_INST_CLOCK_ENABLE_STATUS_DSMAC_SCB_CLOCK_ENABLE_STATUS_SHIFT 1
-
-/* CLKGEN :: D3DSMAC_X4_TOP_INST_CLOCK_ENABLE_STATUS :: DSMAC_54_CLOCK_ENABLE_STATUS [00:00] */
-#define BCHP_CLKGEN_D3DSMAC_X4_TOP_INST_CLOCK_ENABLE_STATUS_DSMAC_54_CLOCK_ENABLE_STATUS_MASK 0x00000001
-#define BCHP_CLKGEN_D3DSMAC_X4_TOP_INST_CLOCK_ENABLE_STATUS_DSMAC_54_CLOCK_ENABLE_STATUS_SHIFT 0
-
-/***************************************************************************
- *DECT_UBUS_TOP_INST_CLOCK_DISABLE - Disable DECT_UBUS_TOP_INST's clocks
- ***************************************************************************/
-/* CLKGEN :: DECT_UBUS_TOP_INST_CLOCK_DISABLE :: reserved0 [31:01] */
-#define BCHP_CLKGEN_DECT_UBUS_TOP_INST_CLOCK_DISABLE_reserved0_MASK 0xfffffffe
-#define BCHP_CLKGEN_DECT_UBUS_TOP_INST_CLOCK_DISABLE_reserved0_SHIFT 1
-
-/* CLKGEN :: DECT_UBUS_TOP_INST_CLOCK_DISABLE :: DISABLE_DECT_DEV_278_CLOCK [00:00] */
-#define BCHP_CLKGEN_DECT_UBUS_TOP_INST_CLOCK_DISABLE_DISABLE_DECT_DEV_278_CLOCK_MASK 0x00000001
-#define BCHP_CLKGEN_DECT_UBUS_TOP_INST_CLOCK_DISABLE_DISABLE_DECT_DEV_278_CLOCK_SHIFT 0
-#define BCHP_CLKGEN_DECT_UBUS_TOP_INST_CLOCK_DISABLE_DISABLE_DECT_DEV_278_CLOCK_DEFAULT 0x00000000
-
-/***************************************************************************
- *DECT_UBUS_TOP_INST_CLOCK_DISABLE_STATUS - Clock Disable Status
- ***************************************************************************/
-/* CLKGEN :: DECT_UBUS_TOP_INST_CLOCK_DISABLE_STATUS :: reserved0 [31:01] */
-#define BCHP_CLKGEN_DECT_UBUS_TOP_INST_CLOCK_DISABLE_STATUS_reserved0_MASK 0xfffffffe
-#define BCHP_CLKGEN_DECT_UBUS_TOP_INST_CLOCK_DISABLE_STATUS_reserved0_SHIFT 1
-
-/* CLKGEN :: DECT_UBUS_TOP_INST_CLOCK_DISABLE_STATUS :: DISABLE_DECT_DEV_278_CLOCK_STATUS [00:00] */
-#define BCHP_CLKGEN_DECT_UBUS_TOP_INST_CLOCK_DISABLE_STATUS_DISABLE_DECT_DEV_278_CLOCK_STATUS_MASK 0x00000001
-#define BCHP_CLKGEN_DECT_UBUS_TOP_INST_CLOCK_DISABLE_STATUS_DISABLE_DECT_DEV_278_CLOCK_STATUS_SHIFT 0
-
-/***************************************************************************
- *DECT_UBUS_TOP_INST_CLOCK_ENABLE - Dect ubus top inst clock enable
- ***************************************************************************/
-/* CLKGEN :: DECT_UBUS_TOP_INST_CLOCK_ENABLE :: reserved0 [31:01] */
-#define BCHP_CLKGEN_DECT_UBUS_TOP_INST_CLOCK_ENABLE_reserved0_MASK 0xfffffffe
-#define BCHP_CLKGEN_DECT_UBUS_TOP_INST_CLOCK_ENABLE_reserved0_SHIFT 1
-
-/* CLKGEN :: DECT_UBUS_TOP_INST_CLOCK_ENABLE :: DECT_54_CLOCK_ENABLE [00:00] */
-#define BCHP_CLKGEN_DECT_UBUS_TOP_INST_CLOCK_ENABLE_DECT_54_CLOCK_ENABLE_MASK 0x00000001
-#define BCHP_CLKGEN_DECT_UBUS_TOP_INST_CLOCK_ENABLE_DECT_54_CLOCK_ENABLE_SHIFT 0
-#define BCHP_CLKGEN_DECT_UBUS_TOP_INST_CLOCK_ENABLE_DECT_54_CLOCK_ENABLE_DEFAULT 0x00000001
-
-/***************************************************************************
- *DECT_UBUS_TOP_INST_CLOCK_ENABLE_STATUS - Clock Enable Status
- ***************************************************************************/
-/* CLKGEN :: DECT_UBUS_TOP_INST_CLOCK_ENABLE_STATUS :: reserved0 [31:01] */
-#define BCHP_CLKGEN_DECT_UBUS_TOP_INST_CLOCK_ENABLE_STATUS_reserved0_MASK 0xfffffffe
-#define BCHP_CLKGEN_DECT_UBUS_TOP_INST_CLOCK_ENABLE_STATUS_reserved0_SHIFT 1
-
-/* CLKGEN :: DECT_UBUS_TOP_INST_CLOCK_ENABLE_STATUS :: DECT_54_CLOCK_ENABLE_STATUS [00:00] */
-#define BCHP_CLKGEN_DECT_UBUS_TOP_INST_CLOCK_ENABLE_STATUS_DECT_54_CLOCK_ENABLE_STATUS_MASK 0x00000001
-#define BCHP_CLKGEN_DECT_UBUS_TOP_INST_CLOCK_ENABLE_STATUS_DECT_54_CLOCK_ENABLE_STATUS_SHIFT 0
-
-/***************************************************************************
- *DISABLE_AVS_TOP_DURING_S2 - Disable AVS_TOP 54MHz clocks during S2 standby.
- ***************************************************************************/
-/* CLKGEN :: DISABLE_AVS_TOP_DURING_S2 :: reserved0 [31:01] */
-#define BCHP_CLKGEN_DISABLE_AVS_TOP_DURING_S2_reserved0_MASK 0xfffffffe
-#define BCHP_CLKGEN_DISABLE_AVS_TOP_DURING_S2_reserved0_SHIFT 1
-
-/* CLKGEN :: DISABLE_AVS_TOP_DURING_S2 :: DISABLE_AVS_TOP [00:00] */
-#define BCHP_CLKGEN_DISABLE_AVS_TOP_DURING_S2_DISABLE_AVS_TOP_MASK 0x00000001
-#define BCHP_CLKGEN_DISABLE_AVS_TOP_DURING_S2_DISABLE_AVS_TOP_SHIFT 0
-#define BCHP_CLKGEN_DISABLE_AVS_TOP_DURING_S2_DISABLE_AVS_TOP_DEFAULT 0x00000000
-
-/***************************************************************************
- *DISABLE_AVS_TOP_DURING_S2_SECURE - Secure AVS_TOP clock disable. Set at start-up to guarantee AVS_TOP is clock gated in S2 standby.
- ***************************************************************************/
-/* CLKGEN :: DISABLE_AVS_TOP_DURING_S2_SECURE :: reserved0 [31:01] */
-#define BCHP_CLKGEN_DISABLE_AVS_TOP_DURING_S2_SECURE_reserved0_MASK 0xfffffffe
-#define BCHP_CLKGEN_DISABLE_AVS_TOP_DURING_S2_SECURE_reserved0_SHIFT 1
-
-/* CLKGEN :: DISABLE_AVS_TOP_DURING_S2_SECURE :: DISABLE_AVS_TOP_SECURE [00:00] */
-#define BCHP_CLKGEN_DISABLE_AVS_TOP_DURING_S2_SECURE_DISABLE_AVS_TOP_SECURE_MASK 0x00000001
-#define BCHP_CLKGEN_DISABLE_AVS_TOP_DURING_S2_SECURE_DISABLE_AVS_TOP_SECURE_SHIFT 0
-#define BCHP_CLKGEN_DISABLE_AVS_TOP_DURING_S2_SECURE_DISABLE_AVS_TOP_SECURE_DEFAULT 0x00000000
-
-/***************************************************************************
- *BSPI_CLOCK_SELECT - PLL RDB Macro Disable
- ***************************************************************************/
-/* CLKGEN :: BSPI_CLOCK_SELECT :: reserved0 [31:03] */
-#define BCHP_CLKGEN_BSPI_CLOCK_SELECT_reserved0_MASK 0xfffffff8
-#define BCHP_CLKGEN_BSPI_CLOCK_SELECT_reserved0_SHIFT 3
-
-/* CLKGEN :: BSPI_CLOCK_SELECT :: SPI_CLOCK_FREQ_SEL [02:01] */
-#define BCHP_CLKGEN_BSPI_CLOCK_SELECT_SPI_CLOCK_FREQ_SEL_MASK 0x00000006
-#define BCHP_CLKGEN_BSPI_CLOCK_SELECT_SPI_CLOCK_FREQ_SEL_SHIFT 1
-#define BCHP_CLKGEN_BSPI_CLOCK_SELECT_SPI_CLOCK_FREQ_SEL_DEFAULT 0x00000000
-
-/* CLKGEN :: BSPI_CLOCK_SELECT :: SPI_CLOCK_OVERRIDE_STRAP [00:00] */
-#define BCHP_CLKGEN_BSPI_CLOCK_SELECT_SPI_CLOCK_OVERRIDE_STRAP_MASK 0x00000001
-#define BCHP_CLKGEN_BSPI_CLOCK_SELECT_SPI_CLOCK_OVERRIDE_STRAP_SHIFT 0
-#define BCHP_CLKGEN_BSPI_CLOCK_SELECT_SPI_CLOCK_OVERRIDE_STRAP_DEFAULT 0x00000000
-
-/***************************************************************************
- *DOCSIS_PLL_SYS1_RDB_MACRO_CTRL - PLL RDB Macro Disable
- ***************************************************************************/
-/* CLKGEN :: DOCSIS_PLL_SYS1_RDB_MACRO_CTRL :: reserved0 [31:09] */
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_RDB_MACRO_CTRL_reserved0_MASK 0xfffffe00
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_RDB_MACRO_CTRL_reserved0_SHIFT 9
-
-/* CLKGEN :: DOCSIS_PLL_SYS1_RDB_MACRO_CTRL :: DOCSIS_PLL_SYS1_CHANNEL4_FREQ_DISABLE_RDB_MACRO [08:08] */
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_RDB_MACRO_CTRL_DOCSIS_PLL_SYS1_CHANNEL4_FREQ_DISABLE_RDB_MACRO_MASK 0x00000100
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_RDB_MACRO_CTRL_DOCSIS_PLL_SYS1_CHANNEL4_FREQ_DISABLE_RDB_MACRO_SHIFT 8
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_RDB_MACRO_CTRL_DOCSIS_PLL_SYS1_CHANNEL4_FREQ_DISABLE_RDB_MACRO_DEFAULT 0x00000000
-
-/* CLKGEN :: DOCSIS_PLL_SYS1_RDB_MACRO_CTRL :: DOCSIS_PLL_SYS1_CHANNEL3_FREQ_DISABLE_RDB_MACRO [07:07] */
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_RDB_MACRO_CTRL_DOCSIS_PLL_SYS1_CHANNEL3_FREQ_DISABLE_RDB_MACRO_MASK 0x00000080
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_RDB_MACRO_CTRL_DOCSIS_PLL_SYS1_CHANNEL3_FREQ_DISABLE_RDB_MACRO_SHIFT 7
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_RDB_MACRO_CTRL_DOCSIS_PLL_SYS1_CHANNEL3_FREQ_DISABLE_RDB_MACRO_DEFAULT 0x00000000
-
-/* CLKGEN :: DOCSIS_PLL_SYS1_RDB_MACRO_CTRL :: DOCSIS_PLL_SYS1_CHANNEL1_FREQ_DISABLE_RDB_MACRO [06:06] */
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_RDB_MACRO_CTRL_DOCSIS_PLL_SYS1_CHANNEL1_FREQ_DISABLE_RDB_MACRO_MASK 0x00000040
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_RDB_MACRO_CTRL_DOCSIS_PLL_SYS1_CHANNEL1_FREQ_DISABLE_RDB_MACRO_SHIFT 6
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_RDB_MACRO_CTRL_DOCSIS_PLL_SYS1_CHANNEL1_FREQ_DISABLE_RDB_MACRO_DEFAULT 0x00000000
-
-/* CLKGEN :: DOCSIS_PLL_SYS1_RDB_MACRO_CTRL :: CHANNEL4_FREQ [05:04] */
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_RDB_MACRO_CTRL_CHANNEL4_FREQ_MASK 0x00000030
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_RDB_MACRO_CTRL_CHANNEL4_FREQ_SHIFT 4
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_RDB_MACRO_CTRL_CHANNEL4_FREQ_DEFAULT 0x00000000
-
-/* CLKGEN :: DOCSIS_PLL_SYS1_RDB_MACRO_CTRL :: CHANNEL3_FREQ [03:02] */
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_RDB_MACRO_CTRL_CHANNEL3_FREQ_MASK 0x0000000c
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_RDB_MACRO_CTRL_CHANNEL3_FREQ_SHIFT 2
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_RDB_MACRO_CTRL_CHANNEL3_FREQ_DEFAULT 0x00000000
-
-/* CLKGEN :: DOCSIS_PLL_SYS1_RDB_MACRO_CTRL :: CHANNEL1_FREQ [01:00] */
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_RDB_MACRO_CTRL_CHANNEL1_FREQ_MASK 0x00000003
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_RDB_MACRO_CTRL_CHANNEL1_FREQ_SHIFT 0
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_RDB_MACRO_CTRL_CHANNEL1_FREQ_DEFAULT 0x00000000
-
-/***************************************************************************
- *DOCSIS_PLL_SYS2_PLL_RESET_STATUS - DOCSIS_PLL_SYS2 Reset Status
- ***************************************************************************/
-/* CLKGEN :: DOCSIS_PLL_SYS2_PLL_RESET_STATUS :: reserved0 [31:02] */
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_RESET_STATUS_reserved0_MASK 0xfffffffc
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_RESET_STATUS_reserved0_SHIFT 2
-
-/* CLKGEN :: DOCSIS_PLL_SYS2_PLL_RESET_STATUS :: PLL_DRESET_STATUS [01:01] */
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_RESET_STATUS_PLL_DRESET_STATUS_MASK 0x00000002
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_RESET_STATUS_PLL_DRESET_STATUS_SHIFT 1
-
-/* CLKGEN :: DOCSIS_PLL_SYS2_PLL_RESET_STATUS :: PLL_ARESET_STATUS [00:00] */
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_RESET_STATUS_PLL_ARESET_STATUS_MASK 0x00000001
-#define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_RESET_STATUS_PLL_ARESET_STATUS_SHIFT 0
-
-/***************************************************************************
- *DS_TOPA_INST_CLOCK_ENABLE - Ds topa inst clock enable
- ***************************************************************************/
-/* CLKGEN :: DS_TOPA_INST_CLOCK_ENABLE :: reserved0 [31:01] */
-#define BCHP_CLKGEN_DS_TOPA_INST_CLOCK_ENABLE_reserved0_MASK 0xfffffffe
-#define BCHP_CLKGEN_DS_TOPA_INST_CLOCK_ENABLE_reserved0_SHIFT 1
-
-/* CLKGEN :: DS_TOPA_INST_CLOCK_ENABLE :: DSA_54_CLOCK_ENABLE [00:00] */
-#define BCHP_CLKGEN_DS_TOPA_INST_CLOCK_ENABLE_DSA_54_CLOCK_ENABLE_MASK 0x00000001
-#define BCHP_CLKGEN_DS_TOPA_INST_CLOCK_ENABLE_DSA_54_CLOCK_ENABLE_SHIFT 0
-#define BCHP_CLKGEN_DS_TOPA_INST_CLOCK_ENABLE_DSA_54_CLOCK_ENABLE_DEFAULT 0x00000001
-
-/***************************************************************************
- *DS_TOPA_INST_CLOCK_ENABLE_STATUS - Clock Enable Status
- ***************************************************************************/
-/* CLKGEN :: DS_TOPA_INST_CLOCK_ENABLE_STATUS :: reserved0 [31:01] */
-#define BCHP_CLKGEN_DS_TOPA_INST_CLOCK_ENABLE_STATUS_reserved0_MASK 0xfffffffe
-#define BCHP_CLKGEN_DS_TOPA_INST_CLOCK_ENABLE_STATUS_reserved0_SHIFT 1
-
-/* CLKGEN :: DS_TOPA_INST_CLOCK_ENABLE_STATUS :: DSA_54_CLOCK_ENABLE_STATUS [00:00] */
-#define BCHP_CLKGEN_DS_TOPA_INST_CLOCK_ENABLE_STATUS_DSA_54_CLOCK_ENABLE_STATUS_MASK 0x00000001
-#define BCHP_CLKGEN_DS_TOPA_INST_CLOCK_ENABLE_STATUS_DSA_54_CLOCK_ENABLE_STATUS_SHIFT 0
-
-/***************************************************************************
- *DS_TOPB_INST_CLOCK_ENABLE - Ds topb inst clock enable
- ***************************************************************************/
-/* CLKGEN :: DS_TOPB_INST_CLOCK_ENABLE :: reserved0 [31:01] */
-#define BCHP_CLKGEN_DS_TOPB_INST_CLOCK_ENABLE_reserved0_MASK 0xfffffffe
-#define BCHP_CLKGEN_DS_TOPB_INST_CLOCK_ENABLE_reserved0_SHIFT 1
-
-/* CLKGEN :: DS_TOPB_INST_CLOCK_ENABLE :: DSB_54_CLOCK_ENABLE [00:00] */
-#define BCHP_CLKGEN_DS_TOPB_INST_CLOCK_ENABLE_DSB_54_CLOCK_ENABLE_MASK 0x00000001
-#define BCHP_CLKGEN_DS_TOPB_INST_CLOCK_ENABLE_DSB_54_CLOCK_ENABLE_SHIFT 0
-#define BCHP_CLKGEN_DS_TOPB_INST_CLOCK_ENABLE_DSB_54_CLOCK_ENABLE_DEFAULT 0x00000001
-
-/***************************************************************************
- *DS_TOPB_INST_CLOCK_ENABLE_STATUS - Clock Enable Status
- ***************************************************************************/
-/* CLKGEN :: DS_TOPB_INST_CLOCK_ENABLE_STATUS :: reserved0 [31:01] */
-#define BCHP_CLKGEN_DS_TOPB_INST_CLOCK_ENABLE_STATUS_reserved0_MASK 0xfffffffe
-#define BCHP_CLKGEN_DS_TOPB_INST_CLOCK_ENABLE_STATUS_reserved0_SHIFT 1
-
-/* CLKGEN :: DS_TOPB_INST_CLOCK_ENABLE_STATUS :: DSB_54_CLOCK_ENABLE_STATUS [00:00] */
-#define BCHP_CLKGEN_DS_TOPB_INST_CLOCK_ENABLE_STATUS_DSB_54_CLOCK_ENABLE_STATUS_MASK 0x00000001
-#define BCHP_CLKGEN_DS_TOPB_INST_CLOCK_ENABLE_STATUS_DSB_54_CLOCK_ENABLE_STATUS_SHIFT 0
-
-/***************************************************************************
- *DS_TOPC_INST_CLOCK_ENABLE - Ds topc inst clock enable
- ***************************************************************************/
-/* CLKGEN :: DS_TOPC_INST_CLOCK_ENABLE :: reserved0 [31:02] */
-#define BCHP_CLKGEN_DS_TOPC_INST_CLOCK_ENABLE_reserved0_MASK 0xfffffffc
-#define BCHP_CLKGEN_DS_TOPC_INST_CLOCK_ENABLE_reserved0_SHIFT 2
-
-/* CLKGEN :: DS_TOPC_INST_CLOCK_ENABLE :: DSC_GISB_CLOCK_ENABLE [01:01] */
-#define BCHP_CLKGEN_DS_TOPC_INST_CLOCK_ENABLE_DSC_GISB_CLOCK_ENABLE_MASK 0x00000002
-#define BCHP_CLKGEN_DS_TOPC_INST_CLOCK_ENABLE_DSC_GISB_CLOCK_ENABLE_SHIFT 1
-#define BCHP_CLKGEN_DS_TOPC_INST_CLOCK_ENABLE_DSC_GISB_CLOCK_ENABLE_DEFAULT 0x00000001
-
-/* CLKGEN :: DS_TOPC_INST_CLOCK_ENABLE :: DSC_54_CLOCK_ENABLE [00:00] */
-#define BCHP_CLKGEN_DS_TOPC_INST_CLOCK_ENABLE_DSC_54_CLOCK_ENABLE_MASK 0x00000001
-#define BCHP_CLKGEN_DS_TOPC_INST_CLOCK_ENABLE_DSC_54_CLOCK_ENABLE_SHIFT 0
-#define BCHP_CLKGEN_DS_TOPC_INST_CLOCK_ENABLE_DSC_54_CLOCK_ENABLE_DEFAULT 0x00000001
-
-/***************************************************************************
- *DS_TOPC_INST_CLOCK_ENABLE_STATUS - Clock Enable Status
- ***************************************************************************/
-/* CLKGEN :: DS_TOPC_INST_CLOCK_ENABLE_STATUS :: reserved0 [31:02] */
-#define BCHP_CLKGEN_DS_TOPC_INST_CLOCK_ENABLE_STATUS_reserved0_MASK 0xfffffffc
-#define BCHP_CLKGEN_DS_TOPC_INST_CLOCK_ENABLE_STATUS_reserved0_SHIFT 2
-
-/* CLKGEN :: DS_TOPC_INST_CLOCK_ENABLE_STATUS :: DSC_GISB_CLOCK_ENABLE_STATUS [01:01] */
-#define BCHP_CLKGEN_DS_TOPC_INST_CLOCK_ENABLE_STATUS_DSC_GISB_CLOCK_ENABLE_STATUS_MASK 0x00000002
-#define BCHP_CLKGEN_DS_TOPC_INST_CLOCK_ENABLE_STATUS_DSC_GISB_CLOCK_ENABLE_STATUS_SHIFT 1
-
-/* CLKGEN :: DS_TOPC_INST_CLOCK_ENABLE_STATUS :: DSC_54_CLOCK_ENABLE_STATUS [00:00] */
-#define BCHP_CLKGEN_DS_TOPC_INST_CLOCK_ENABLE_STATUS_DSC_54_CLOCK_ENABLE_STATUS_MASK 0x00000001
-#define BCHP_CLKGEN_DS_TOPC_INST_CLOCK_ENABLE_STATUS_DSC_54_CLOCK_ENABLE_STATUS_SHIFT 0
-
-/***************************************************************************
- *DS_TOPD_INST_CLOCK_ENABLE - Ds topd inst clock enable
- ***************************************************************************/
-/* CLKGEN :: DS_TOPD_INST_CLOCK_ENABLE :: reserved0 [31:01] */
-#define BCHP_CLKGEN_DS_TOPD_INST_CLOCK_ENABLE_reserved0_MASK 0xfffffffe
-#define BCHP_CLKGEN_DS_TOPD_INST_CLOCK_ENABLE_reserved0_SHIFT 1
-
-/* CLKGEN :: DS_TOPD_INST_CLOCK_ENABLE :: DSC_54_CLOCK_ENABLE [00:00] */
-#define BCHP_CLKGEN_DS_TOPD_INST_CLOCK_ENABLE_DSC_54_CLOCK_ENABLE_MASK 0x00000001
-#define BCHP_CLKGEN_DS_TOPD_INST_CLOCK_ENABLE_DSC_54_CLOCK_ENABLE_SHIFT 0
-#define BCHP_CLKGEN_DS_TOPD_INST_CLOCK_ENABLE_DSC_54_CLOCK_ENABLE_DEFAULT 0x00000001
-
-/***************************************************************************
- *DS_TOPD_INST_CLOCK_ENABLE_STATUS - Clock Enable Status
- ***************************************************************************/
-/* CLKGEN :: DS_TOPD_INST_CLOCK_ENABLE_STATUS :: reserved0 [31:01] */
-#define BCHP_CLKGEN_DS_TOPD_INST_CLOCK_ENABLE_STATUS_reserved0_MASK 0xfffffffe
-#define BCHP_CLKGEN_DS_TOPD_INST_CLOCK_ENABLE_STATUS_reserved0_SHIFT 1
-
-/* CLKGEN :: DS_TOPD_INST_CLOCK_ENABLE_STATUS :: DSC_54_CLOCK_ENABLE_STATUS [00:00] */
-#define BCHP_CLKGEN_DS_TOPD_INST_CLOCK_ENABLE_STATUS_DSC_54_CLOCK_ENABLE_STATUS_MASK 0x00000001
-#define BCHP_CLKGEN_DS_TOPD_INST_CLOCK_ENABLE_STATUS_DSC_54_CLOCK_ENABLE_STATUS_SHIFT 0
-
-/***************************************************************************
- *DS_WFE_TOP_INST_CLOCK_ENABLE - Ds wfe top inst clock enable
- ***************************************************************************/
-/* CLKGEN :: DS_WFE_TOP_INST_CLOCK_ENABLE :: reserved0 [31:01] */
-#define BCHP_CLKGEN_DS_WFE_TOP_INST_CLOCK_ENABLE_reserved0_MASK 0xfffffffe
-#define BCHP_CLKGEN_DS_WFE_TOP_INST_CLOCK_ENABLE_reserved0_SHIFT 1
-
-/* CLKGEN :: DS_WFE_TOP_INST_CLOCK_ENABLE :: WFE_54_CLOCK_ENABLE [00:00] */
-#define BCHP_CLKGEN_DS_WFE_TOP_INST_CLOCK_ENABLE_WFE_54_CLOCK_ENABLE_MASK 0x00000001
-#define BCHP_CLKGEN_DS_WFE_TOP_INST_CLOCK_ENABLE_WFE_54_CLOCK_ENABLE_SHIFT 0
-#define BCHP_CLKGEN_DS_WFE_TOP_INST_CLOCK_ENABLE_WFE_54_CLOCK_ENABLE_DEFAULT 0x00000001
-
-/***************************************************************************
- *DS_WFE_TOP_INST_CLOCK_ENABLE_STATUS - Clock Enable Status
- ***************************************************************************/
-/* CLKGEN :: DS_WFE_TOP_INST_CLOCK_ENABLE_STATUS :: reserved0 [31:01] */
-#define BCHP_CLKGEN_DS_WFE_TOP_INST_CLOCK_ENABLE_STATUS_reserved0_MASK 0xfffffffe
-#define BCHP_CLKGEN_DS_WFE_TOP_INST_CLOCK_ENABLE_STATUS_reserved0_SHIFT 1
-
-/* CLKGEN :: DS_WFE_TOP_INST_CLOCK_ENABLE_STATUS :: WFE_54_CLOCK_ENABLE_STATUS [00:00] */
-#define BCHP_CLKGEN_DS_WFE_TOP_INST_CLOCK_ENABLE_STATUS_WFE_54_CLOCK_ENABLE_STATUS_MASK 0x00000001
-#define BCHP_CLKGEN_DS_WFE_TOP_INST_CLOCK_ENABLE_STATUS_WFE_54_CLOCK_ENABLE_STATUS_SHIFT 0
-
-/***************************************************************************
- *DTP_DFAP_TOP_INST_CLOCK_DISABLE - Disable DTP_DFAP_TOP_INST's clocks
- ***************************************************************************/
-/* CLKGEN :: DTP_DFAP_TOP_INST_CLOCK_DISABLE :: reserved0 [31:03] */
-#define BCHP_CLKGEN_DTP_DFAP_TOP_INST_CLOCK_DISABLE_reserved0_MASK 0xfffffff8
-#define BCHP_CLKGEN_DTP_DFAP_TOP_INST_CLOCK_DISABLE_reserved0_SHIFT 3
-
-/* CLKGEN :: DTP_DFAP_TOP_INST_CLOCK_DISABLE :: DISABLE_DFAP_324_CLOCK [02:02] */
-#define BCHP_CLKGEN_DTP_DFAP_TOP_INST_CLOCK_DISABLE_DISABLE_DFAP_324_CLOCK_MASK 0x00000004
-#define BCHP_CLKGEN_DTP_DFAP_TOP_INST_CLOCK_DISABLE_DISABLE_DFAP_324_CLOCK_SHIFT 2
-#define BCHP_CLKGEN_DTP_DFAP_TOP_INST_CLOCK_DISABLE_DISABLE_DFAP_324_CLOCK_DEFAULT 0x00000000
-
-/* CLKGEN :: DTP_DFAP_TOP_INST_CLOCK_DISABLE :: DISABLE_DFAP_216_CLOCK [01:01] */
-#define BCHP_CLKGEN_DTP_DFAP_TOP_INST_CLOCK_DISABLE_DISABLE_DFAP_216_CLOCK_MASK 0x00000002
-#define BCHP_CLKGEN_DTP_DFAP_TOP_INST_CLOCK_DISABLE_DISABLE_DFAP_216_CLOCK_SHIFT 1
-#define BCHP_CLKGEN_DTP_DFAP_TOP_INST_CLOCK_DISABLE_DISABLE_DFAP_216_CLOCK_DEFAULT 0x00000000
-
-/* CLKGEN :: DTP_DFAP_TOP_INST_CLOCK_DISABLE :: DISABLE_CG_TCK_SCAN_CLOCK [00:00] */
-#define BCHP_CLKGEN_DTP_DFAP_TOP_INST_CLOCK_DISABLE_DISABLE_CG_TCK_SCAN_CLOCK_MASK 0x00000001
-#define BCHP_CLKGEN_DTP_DFAP_TOP_INST_CLOCK_DISABLE_DISABLE_CG_TCK_SCAN_CLOCK_SHIFT 0
-#define BCHP_CLKGEN_DTP_DFAP_TOP_INST_CLOCK_DISABLE_DISABLE_CG_TCK_SCAN_CLOCK_DEFAULT 0x00000000
-
-/***************************************************************************
- *DTP_DFAP_TOP_INST_CLOCK_DISABLE_STATUS - Clock Disable Status
- ***************************************************************************/
-/* CLKGEN :: DTP_DFAP_TOP_INST_CLOCK_DISABLE_STATUS :: reserved0 [31:03] */
-#define BCHP_CLKGEN_DTP_DFAP_TOP_INST_CLOCK_DISABLE_STATUS_reserved0_MASK 0xfffffff8
-#define BCHP_CLKGEN_DTP_DFAP_TOP_INST_CLOCK_DISABLE_STATUS_reserved0_SHIFT 3
-
-/* CLKGEN :: DTP_DFAP_TOP_INST_CLOCK_DISABLE_STATUS :: DISABLE_DFAP_324_CLOCK_STATUS [02:02] */
-#define BCHP_CLKGEN_DTP_DFAP_TOP_INST_CLOCK_DISABLE_STATUS_DISABLE_DFAP_324_CLOCK_STATUS_MASK 0x00000004
-#define BCHP_CLKGEN_DTP_DFAP_TOP_INST_CLOCK_DISABLE_STATUS_DISABLE_DFAP_324_CLOCK_STATUS_SHIFT 2
-
-/* CLKGEN :: DTP_DFAP_TOP_INST_CLOCK_DISABLE_STATUS :: DISABLE_DFAP_216_CLOCK_STATUS [01:01] */
-#define BCHP_CLKGEN_DTP_DFAP_TOP_INST_CLOCK_DISABLE_STATUS_DISABLE_DFAP_216_CLOCK_STATUS_MASK 0x00000002
-#define BCHP_CLKGEN_DTP_DFAP_TOP_INST_CLOCK_DISABLE_STATUS_DISABLE_DFAP_216_CLOCK_STATUS_SHIFT 1
-
-/* CLKGEN :: DTP_DFAP_TOP_INST_CLOCK_DISABLE_STATUS :: DISABLE_CG_TCK_SCAN_CLOCK_STATUS [00:00] */
-#define BCHP_CLKGEN_DTP_DFAP_TOP_INST_CLOCK_DISABLE_STATUS_DISABLE_CG_TCK_SCAN_CLOCK_STATUS_MASK 0x00000001
-#define BCHP_CLKGEN_DTP_DFAP_TOP_INST_CLOCK_DISABLE_STATUS_DISABLE_CG_TCK_SCAN_CLOCK_STATUS_SHIFT 0
-
-/***************************************************************************
- *DTP_DFAP_TOP_INST_CLOCK_ENABLE - Dtp dfap top inst clock enable
- ***************************************************************************/
-/* CLKGEN :: DTP_DFAP_TOP_INST_CLOCK_ENABLE :: reserved0 [31:02] */
-#define BCHP_CLKGEN_DTP_DFAP_TOP_INST_CLOCK_ENABLE_reserved0_MASK 0xfffffffc
-#define BCHP_CLKGEN_DTP_DFAP_TOP_INST_CLOCK_ENABLE_reserved0_SHIFT 2
-
-/* CLKGEN :: DTP_DFAP_TOP_INST_CLOCK_ENABLE :: DFAP_SCB_CLOCK_ENABLE [01:01] */
-#define BCHP_CLKGEN_DTP_DFAP_TOP_INST_CLOCK_ENABLE_DFAP_SCB_CLOCK_ENABLE_MASK 0x00000002
-#define BCHP_CLKGEN_DTP_DFAP_TOP_INST_CLOCK_ENABLE_DFAP_SCB_CLOCK_ENABLE_SHIFT 1
-#define BCHP_CLKGEN_DTP_DFAP_TOP_INST_CLOCK_ENABLE_DFAP_SCB_CLOCK_ENABLE_DEFAULT 0x00000001
-
-/* CLKGEN :: DTP_DFAP_TOP_INST_CLOCK_ENABLE :: DFAP_54_CLOCK_ENABLE [00:00] */
-#define BCHP_CLKGEN_DTP_DFAP_TOP_INST_CLOCK_ENABLE_DFAP_54_CLOCK_ENABLE_MASK 0x00000001
-#define BCHP_CLKGEN_DTP_DFAP_TOP_INST_CLOCK_ENABLE_DFAP_54_CLOCK_ENABLE_SHIFT 0
-#define BCHP_CLKGEN_DTP_DFAP_TOP_INST_CLOCK_ENABLE_DFAP_54_CLOCK_ENABLE_DEFAULT 0x00000001
-
-/***************************************************************************
- *DTP_DFAP_TOP_INST_CLOCK_ENABLE_STATUS - Clock Enable Status
- ***************************************************************************/
-/* CLKGEN :: DTP_DFAP_TOP_INST_CLOCK_ENABLE_STATUS :: reserved0 [31:02] */
-#define BCHP_CLKGEN_DTP_DFAP_TOP_INST_CLOCK_ENABLE_STATUS_reserved0_MASK 0xfffffffc
-#define BCHP_CLKGEN_DTP_DFAP_TOP_INST_CLOCK_ENABLE_STATUS_reserved0_SHIFT 2
-
-/* CLKGEN :: DTP_DFAP_TOP_INST_CLOCK_ENABLE_STATUS :: DFAP_SCB_CLOCK_ENABLE_STATUS [01:01] */
-#define BCHP_CLKGEN_DTP_DFAP_TOP_INST_CLOCK_ENABLE_STATUS_DFAP_SCB_CLOCK_ENABLE_STATUS_MASK 0x00000002
-#define BCHP_CLKGEN_DTP_DFAP_TOP_INST_CLOCK_ENABLE_STATUS_DFAP_SCB_CLOCK_ENABLE_STATUS_SHIFT 1
-
-/* CLKGEN :: DTP_DFAP_TOP_INST_CLOCK_ENABLE_STATUS :: DFAP_54_CLOCK_ENABLE_STATUS [00:00] */
-#define BCHP_CLKGEN_DTP_DFAP_TOP_INST_CLOCK_ENABLE_STATUS_DFAP_54_CLOCK_ENABLE_STATUS_MASK 0x00000001
-#define BCHP_CLKGEN_DTP_DFAP_TOP_INST_CLOCK_ENABLE_STATUS_DFAP_54_CLOCK_ENABLE_STATUS_SHIFT 0
-
-/***************************************************************************
- *DVP_HR_INST_CLOCK_DISABLE - Disable DVP_HR_INST's clocks
- ***************************************************************************/
-/* CLKGEN :: DVP_HR_INST_CLOCK_DISABLE :: reserved0 [31:01] */
-#define BCHP_CLKGEN_DVP_HR_INST_CLOCK_DISABLE_reserved0_MASK 0xfffffffe
-#define BCHP_CLKGEN_DVP_HR_INST_CLOCK_DISABLE_reserved0_SHIFT 1
-
-/* CLKGEN :: DVP_HR_INST_CLOCK_DISABLE :: DISABLE_DVPHR_ALWAYSON_CLOCK [00:00] */
-#define BCHP_CLKGEN_DVP_HR_INST_CLOCK_DISABLE_DISABLE_DVPHR_ALWAYSON_CLOCK_MASK 0x00000001
-#define BCHP_CLKGEN_DVP_HR_INST_CLOCK_DISABLE_DISABLE_DVPHR_ALWAYSON_CLOCK_SHIFT 0
-#define BCHP_CLKGEN_DVP_HR_INST_CLOCK_DISABLE_DISABLE_DVPHR_ALWAYSON_CLOCK_DEFAULT 0x00000000
-
-/***************************************************************************
- *DVP_HR_INST_CLOCK_DISABLE_STATUS - Clock Disable Status
- ***************************************************************************/
-/* CLKGEN :: DVP_HR_INST_CLOCK_DISABLE_STATUS :: reserved0 [31:01] */
-#define BCHP_CLKGEN_DVP_HR_INST_CLOCK_DISABLE_STATUS_reserved0_MASK 0xfffffffe
-#define BCHP_CLKGEN_DVP_HR_INST_CLOCK_DISABLE_STATUS_reserved0_SHIFT 1
-
-/* CLKGEN :: DVP_HR_INST_CLOCK_DISABLE_STATUS :: DISABLE_DVPHR_ALWAYSON_CLOCK_STATUS [00:00] */
-#define BCHP_CLKGEN_DVP_HR_INST_CLOCK_DISABLE_STATUS_DISABLE_DVPHR_ALWAYSON_CLOCK_STATUS_MASK 0x00000001
-#define BCHP_CLKGEN_DVP_HR_INST_CLOCK_DISABLE_STATUS_DISABLE_DVPHR_ALWAYSON_CLOCK_STATUS_SHIFT 0
-
-/***************************************************************************
- *DVP_HR_INST_CLOCK_ENABLE - Dvp hr inst clock enable
- ***************************************************************************/
-/* CLKGEN :: DVP_HR_INST_CLOCK_ENABLE :: reserved0 [31:04] */
-#define BCHP_CLKGEN_DVP_HR_INST_CLOCK_ENABLE_reserved0_MASK 0xfffffff0
-#define BCHP_CLKGEN_DVP_HR_INST_CLOCK_ENABLE_reserved0_SHIFT 4
-
-/* CLKGEN :: DVP_HR_INST_CLOCK_ENABLE :: DVPHR_BVB_CLOCK_ENABLE [03:03] */
-#define BCHP_CLKGEN_DVP_HR_INST_CLOCK_ENABLE_DVPHR_BVB_CLOCK_ENABLE_MASK 0x00000008
-#define BCHP_CLKGEN_DVP_HR_INST_CLOCK_ENABLE_DVPHR_BVB_CLOCK_ENABLE_SHIFT 3
-#define BCHP_CLKGEN_DVP_HR_INST_CLOCK_ENABLE_DVPHR_BVB_CLOCK_ENABLE_DEFAULT 0x00000001
-
-/* CLKGEN :: DVP_HR_INST_CLOCK_ENABLE :: DVPHR_54_CLOCK_ENABLE [02:02] */
-#define BCHP_CLKGEN_DVP_HR_INST_CLOCK_ENABLE_DVPHR_54_CLOCK_ENABLE_MASK 0x00000004
-#define BCHP_CLKGEN_DVP_HR_INST_CLOCK_ENABLE_DVPHR_54_CLOCK_ENABLE_SHIFT 2
-#define BCHP_CLKGEN_DVP_HR_INST_CLOCK_ENABLE_DVPHR_54_CLOCK_ENABLE_DEFAULT 0x00000001
-
-/* CLKGEN :: DVP_HR_INST_CLOCK_ENABLE :: DVPHR_324_CLOCK_ENABLE [01:01] */
-#define BCHP_CLKGEN_DVP_HR_INST_CLOCK_ENABLE_DVPHR_324_CLOCK_ENABLE_MASK 0x00000002
-#define BCHP_CLKGEN_DVP_HR_INST_CLOCK_ENABLE_DVPHR_324_CLOCK_ENABLE_SHIFT 1
-#define BCHP_CLKGEN_DVP_HR_INST_CLOCK_ENABLE_DVPHR_324_CLOCK_ENABLE_DEFAULT 0x00000001
-
-/* CLKGEN :: DVP_HR_INST_CLOCK_ENABLE :: DVPHR_108_CLOCK_ENABLE [00:00] */
-#define BCHP_CLKGEN_DVP_HR_INST_CLOCK_ENABLE_DVPHR_108_CLOCK_ENABLE_MASK 0x00000001
-#define BCHP_CLKGEN_DVP_HR_INST_CLOCK_ENABLE_DVPHR_108_CLOCK_ENABLE_SHIFT 0
-#define BCHP_CLKGEN_DVP_HR_INST_CLOCK_ENABLE_DVPHR_108_CLOCK_ENABLE_DEFAULT 0x00000001
-
-/***************************************************************************
- *DVP_HR_INST_CLOCK_ENABLE_STATUS - Clock Enable Status
- ***************************************************************************/
-/* CLKGEN :: DVP_HR_INST_CLOCK_ENABLE_STATUS :: reserved0 [31:04] */
-#define BCHP_CLKGEN_DVP_HR_INST_CLOCK_ENABLE_STATUS_reserved0_MASK 0xfffffff0
-#define BCHP_CLKGEN_DVP_HR_INST_CLOCK_ENABLE_STATUS_reserved0_SHIFT 4
-
-/* CLKGEN :: DVP_HR_INST_CLOCK_ENABLE_STATUS :: DVPHR_BVB_CLOCK_ENABLE_STATUS [03:03] */
-#define BCHP_CLKGEN_DVP_HR_INST_CLOCK_ENABLE_STATUS_DVPHR_BVB_CLOCK_ENABLE_STATUS_MASK 0x00000008
-#define BCHP_CLKGEN_DVP_HR_INST_CLOCK_ENABLE_STATUS_DVPHR_BVB_CLOCK_ENABLE_STATUS_SHIFT 3
-
-/* CLKGEN :: DVP_HR_INST_CLOCK_ENABLE_STATUS :: DVPHR_54_CLOCK_ENABLE_STATUS [02:02] */
-#define BCHP_CLKGEN_DVP_HR_INST_CLOCK_ENABLE_STATUS_DVPHR_54_CLOCK_ENABLE_STATUS_MASK 0x00000004
-#define BCHP_CLKGEN_DVP_HR_INST_CLOCK_ENABLE_STATUS_DVPHR_54_CLOCK_ENABLE_STATUS_SHIFT 2
-
-/* CLKGEN :: DVP_HR_INST_CLOCK_ENABLE_STATUS :: DVPHR_324_CLOCK_ENABLE_STATUS [01:01] */
-#define BCHP_CLKGEN_DVP_HR_INST_CLOCK_ENABLE_STATUS_DVPHR_324_CLOCK_ENABLE_STATUS_MASK 0x00000002
-#define BCHP_CLKGEN_DVP_HR_INST_CLOCK_ENABLE_STATUS_DVPHR_324_CLOCK_ENABLE_STATUS_SHIFT 1
-
-/* CLKGEN :: DVP_HR_INST_CLOCK_ENABLE_STATUS :: DVPHR_108_CLOCK_ENABLE_STATUS [00:00] */
-#define BCHP_CLKGEN_DVP_HR_INST_CLOCK_ENABLE_STATUS_DVPHR_108_CLOCK_ENABLE_STATUS_MASK 0x00000001
-#define BCHP_CLKGEN_DVP_HR_INST_CLOCK_ENABLE_STATUS_DVPHR_108_CLOCK_ENABLE_STATUS_SHIFT 0
-
-/***************************************************************************
- *DVP_HR_INST_ENABLE - Dvp hr inst enable
- ***************************************************************************/
-/* CLKGEN :: DVP_HR_INST_ENABLE :: reserved0 [31:01] */
-#define BCHP_CLKGEN_DVP_HR_INST_ENABLE_reserved0_MASK 0xfffffffe
-#define BCHP_CLKGEN_DVP_HR_INST_ENABLE_reserved0_SHIFT 1
-
-/* CLKGEN :: DVP_HR_INST_ENABLE :: DVPHR_SCAN_CLK_324_ENABLE [00:00] */
-#define BCHP_CLKGEN_DVP_HR_INST_ENABLE_DVPHR_SCAN_CLK_324_ENABLE_MASK 0x00000001
-#define BCHP_CLKGEN_DVP_HR_INST_ENABLE_DVPHR_SCAN_CLK_324_ENABLE_SHIFT 0
-#define BCHP_CLKGEN_DVP_HR_INST_ENABLE_DVPHR_SCAN_CLK_324_ENABLE_DEFAULT 0x00000000
-
-/***************************************************************************
- *DVP_HR_INST_OBSERVE_CLOCK - Dvp hr inst observe clock
- ***************************************************************************/
-/* CLKGEN :: DVP_HR_INST_OBSERVE_CLOCK :: reserved0 [31:06] */
-#define BCHP_CLKGEN_DVP_HR_INST_OBSERVE_CLOCK_reserved0_MASK 0xffffffc0
-#define BCHP_CLKGEN_DVP_HR_INST_OBSERVE_CLOCK_reserved0_SHIFT 6
-
-/* CLKGEN :: DVP_HR_INST_OBSERVE_CLOCK :: DVPHR_ENABLE_OBSERVE_CLOCK [05:05] */
-#define BCHP_CLKGEN_DVP_HR_INST_OBSERVE_CLOCK_DVPHR_ENABLE_OBSERVE_CLOCK_MASK 0x00000020
-#define BCHP_CLKGEN_DVP_HR_INST_OBSERVE_CLOCK_DVPHR_ENABLE_OBSERVE_CLOCK_SHIFT 5
-#define BCHP_CLKGEN_DVP_HR_INST_OBSERVE_CLOCK_DVPHR_ENABLE_OBSERVE_CLOCK_DEFAULT 0x00000000
-
-/* CLKGEN :: DVP_HR_INST_OBSERVE_CLOCK :: DVPHR_ENABLE_DIVIDER_OBSERVE_CLOCK [04:04] */
-#define BCHP_CLKGEN_DVP_HR_INST_OBSERVE_CLOCK_DVPHR_ENABLE_DIVIDER_OBSERVE_CLOCK_MASK 0x00000010
-#define BCHP_CLKGEN_DVP_HR_INST_OBSERVE_CLOCK_DVPHR_ENABLE_DIVIDER_OBSERVE_CLOCK_SHIFT 4
-#define BCHP_CLKGEN_DVP_HR_INST_OBSERVE_CLOCK_DVPHR_ENABLE_DIVIDER_OBSERVE_CLOCK_DEFAULT 0x00000000
-
-/* CLKGEN :: DVP_HR_INST_OBSERVE_CLOCK :: DVPHR_CONTROL_OBSERVE_CLOCK [03:00] */
-#define BCHP_CLKGEN_DVP_HR_INST_OBSERVE_CLOCK_DVPHR_CONTROL_OBSERVE_CLOCK_MASK 0x0000000f
-#define BCHP_CLKGEN_DVP_HR_INST_OBSERVE_CLOCK_DVPHR_CONTROL_OBSERVE_CLOCK_SHIFT 0
-#define BCHP_CLKGEN_DVP_HR_INST_OBSERVE_CLOCK_DVPHR_CONTROL_OBSERVE_CLOCK_DEFAULT 0x00000000
-
-/***************************************************************************
- *DVP_HT_INST_CLOCK_DISABLE - Disable DVP_HT_INST's clocks
- ***************************************************************************/
-/* CLKGEN :: DVP_HT_INST_CLOCK_DISABLE :: reserved0 [31:01] */
-#define BCHP_CLKGEN_DVP_HT_INST_CLOCK_DISABLE_reserved0_MASK 0xfffffffe
-#define BCHP_CLKGEN_DVP_HT_INST_CLOCK_DISABLE_reserved0_SHIFT 1
-
-/* CLKGEN :: DVP_HT_INST_CLOCK_DISABLE :: DISABLE_DVPHT_IIC_MASTER_CLOCK [00:00] */
-#define BCHP_CLKGEN_DVP_HT_INST_CLOCK_DISABLE_DISABLE_DVPHT_IIC_MASTER_CLOCK_MASK 0x00000001
-#define BCHP_CLKGEN_DVP_HT_INST_CLOCK_DISABLE_DISABLE_DVPHT_IIC_MASTER_CLOCK_SHIFT 0
-#define BCHP_CLKGEN_DVP_HT_INST_CLOCK_DISABLE_DISABLE_DVPHT_IIC_MASTER_CLOCK_DEFAULT 0x00000000
-
-/***************************************************************************
- *DVP_HT_INST_CLOCK_DISABLE_STATUS - Clock Disable Status
- ***************************************************************************/
-/* CLKGEN :: DVP_HT_INST_CLOCK_DISABLE_STATUS :: reserved0 [31:01] */
-#define BCHP_CLKGEN_DVP_HT_INST_CLOCK_DISABLE_STATUS_reserved0_MASK 0xfffffffe
-#define BCHP_CLKGEN_DVP_HT_INST_CLOCK_DISABLE_STATUS_reserved0_SHIFT 1
-
-/* CLKGEN :: DVP_HT_INST_CLOCK_DISABLE_STATUS :: DISABLE_DVPHT_IIC_MASTER_CLOCK_STATUS [00:00] */
-#define BCHP_CLKGEN_DVP_HT_INST_CLOCK_DISABLE_STATUS_DISABLE_DVPHT_IIC_MASTER_CLOCK_STATUS_MASK 0x00000001
-#define BCHP_CLKGEN_DVP_HT_INST_CLOCK_DISABLE_STATUS_DISABLE_DVPHT_IIC_MASTER_CLOCK_STATUS_SHIFT 0
-
-/***************************************************************************
- *DVP_HT_INST_CLOCK_ENABLE - Dvp ht inst clock enable
- ***************************************************************************/
-/* CLKGEN :: DVP_HT_INST_CLOCK_ENABLE :: reserved0 [31:04] */
-#define BCHP_CLKGEN_DVP_HT_INST_CLOCK_ENABLE_reserved0_MASK 0xfffffff0
-#define BCHP_CLKGEN_DVP_HT_INST_CLOCK_ENABLE_reserved0_SHIFT 4
-
-/* CLKGEN :: DVP_HT_INST_CLOCK_ENABLE :: DVPHT_BVB_CLOCK_ENABLE [03:03] */
-#define BCHP_CLKGEN_DVP_HT_INST_CLOCK_ENABLE_DVPHT_BVB_CLOCK_ENABLE_MASK 0x00000008
-#define BCHP_CLKGEN_DVP_HT_INST_CLOCK_ENABLE_DVPHT_BVB_CLOCK_ENABLE_SHIFT 3
-#define BCHP_CLKGEN_DVP_HT_INST_CLOCK_ENABLE_DVPHT_BVB_CLOCK_ENABLE_DEFAULT 0x00000001
-
-/* CLKGEN :: DVP_HT_INST_CLOCK_ENABLE :: DVPHT_54_CLOCK_ENABLE [02:02] */
-#define BCHP_CLKGEN_DVP_HT_INST_CLOCK_ENABLE_DVPHT_54_CLOCK_ENABLE_MASK 0x00000004
-#define BCHP_CLKGEN_DVP_HT_INST_CLOCK_ENABLE_DVPHT_54_CLOCK_ENABLE_SHIFT 2
-#define BCHP_CLKGEN_DVP_HT_INST_CLOCK_ENABLE_DVPHT_54_CLOCK_ENABLE_DEFAULT 0x00000001
-
-/* CLKGEN :: DVP_HT_INST_CLOCK_ENABLE :: DVPHT_324_CLOCK_ENABLE [01:01] */
-#define BCHP_CLKGEN_DVP_HT_INST_CLOCK_ENABLE_DVPHT_324_CLOCK_ENABLE_MASK 0x00000002
-#define BCHP_CLKGEN_DVP_HT_INST_CLOCK_ENABLE_DVPHT_324_CLOCK_ENABLE_SHIFT 1
-#define BCHP_CLKGEN_DVP_HT_INST_CLOCK_ENABLE_DVPHT_324_CLOCK_ENABLE_DEFAULT 0x00000001
-
-/* CLKGEN :: DVP_HT_INST_CLOCK_ENABLE :: DVPHT_108_CLOCK_ENABLE [00:00] */
-#define BCHP_CLKGEN_DVP_HT_INST_CLOCK_ENABLE_DVPHT_108_CLOCK_ENABLE_MASK 0x00000001
-#define BCHP_CLKGEN_DVP_HT_INST_CLOCK_ENABLE_DVPHT_108_CLOCK_ENABLE_SHIFT 0
-#define BCHP_CLKGEN_DVP_HT_INST_CLOCK_ENABLE_DVPHT_108_CLOCK_ENABLE_DEFAULT 0x00000001
-
-/***************************************************************************
- *DVP_HT_INST_CLOCK_ENABLE_STATUS - Clock Enable Status
- ***************************************************************************/
-/* CLKGEN :: DVP_HT_INST_CLOCK_ENABLE_STATUS :: reserved0 [31:04] */
-#define BCHP_CLKGEN_DVP_HT_INST_CLOCK_ENABLE_STATUS_reserved0_MASK 0xfffffff0
-#define BCHP_CLKGEN_DVP_HT_INST_CLOCK_ENABLE_STATUS_reserved0_SHIFT 4
-
-/* CLKGEN :: DVP_HT_INST_CLOCK_ENABLE_STATUS :: DVPHT_BVB_CLOCK_ENABLE_STATUS [03:03] */
-#define BCHP_CLKGEN_DVP_HT_INST_CLOCK_ENABLE_STATUS_DVPHT_BVB_CLOCK_ENABLE_STATUS_MASK 0x00000008
-#define BCHP_CLKGEN_DVP_HT_INST_CLOCK_ENABLE_STATUS_DVPHT_BVB_CLOCK_ENABLE_STATUS_SHIFT 3
-
-/* CLKGEN :: DVP_HT_INST_CLOCK_ENABLE_STATUS :: DVPHT_54_CLOCK_ENABLE_STATUS [02:02] */
-#define BCHP_CLKGEN_DVP_HT_INST_CLOCK_ENABLE_STATUS_DVPHT_54_CLOCK_ENABLE_STATUS_MASK 0x00000004
-#define BCHP_CLKGEN_DVP_HT_INST_CLOCK_ENABLE_STATUS_DVPHT_54_CLOCK_ENABLE_STATUS_SHIFT 2
-
-/* CLKGEN :: DVP_HT_INST_CLOCK_ENABLE_STATUS :: DVPHT_324_CLOCK_ENABLE_STATUS [01:01] */
-#define BCHP_CLKGEN_DVP_HT_INST_CLOCK_ENABLE_STATUS_DVPHT_324_CLOCK_ENABLE_STATUS_MASK 0x00000002
-#define BCHP_CLKGEN_DVP_HT_INST_CLOCK_ENABLE_STATUS_DVPHT_324_CLOCK_ENABLE_STATUS_SHIFT 1
-
-/* CLKGEN :: DVP_HT_INST_CLOCK_ENABLE_STATUS :: DVPHT_108_CLOCK_ENABLE_STATUS [00:00] */
-#define BCHP_CLKGEN_DVP_HT_INST_CLOCK_ENABLE_STATUS_DVPHT_108_CLOCK_ENABLE_STATUS_MASK 0x00000001
-#define BCHP_CLKGEN_DVP_HT_INST_CLOCK_ENABLE_STATUS_DVPHT_108_CLOCK_ENABLE_STATUS_SHIFT 0
-
-/***************************************************************************
- *DVP_HT_INST_OBSERVE_CLOCK - Dvp ht inst observe clock
- ***************************************************************************/
-/* CLKGEN :: DVP_HT_INST_OBSERVE_CLOCK :: reserved0 [31:06] */
-#define BCHP_CLKGEN_DVP_HT_INST_OBSERVE_CLOCK_reserved0_MASK 0xffffffc0
-#define BCHP_CLKGEN_DVP_HT_INST_OBSERVE_CLOCK_reserved0_SHIFT 6
-
-/* CLKGEN :: DVP_HT_INST_OBSERVE_CLOCK :: DVPHT_ENABLE_OBSERVE_CLOCK [05:05] */
-#define BCHP_CLKGEN_DVP_HT_INST_OBSERVE_CLOCK_DVPHT_ENABLE_OBSERVE_CLOCK_MASK 0x00000020
-#define BCHP_CLKGEN_DVP_HT_INST_OBSERVE_CLOCK_DVPHT_ENABLE_OBSERVE_CLOCK_SHIFT 5
-#define BCHP_CLKGEN_DVP_HT_INST_OBSERVE_CLOCK_DVPHT_ENABLE_OBSERVE_CLOCK_DEFAULT 0x00000000
-
-/* CLKGEN :: DVP_HT_INST_OBSERVE_CLOCK :: DVPHT_ENABLE_DIVIDER_OBSERVE_CLOCK [04:04] */
-#define BCHP_CLKGEN_DVP_HT_INST_OBSERVE_CLOCK_DVPHT_ENABLE_DIVIDER_OBSERVE_CLOCK_MASK 0x00000010
-#define BCHP_CLKGEN_DVP_HT_INST_OBSERVE_CLOCK_DVPHT_ENABLE_DIVIDER_OBSERVE_CLOCK_SHIFT 4
-#define BCHP_CLKGEN_DVP_HT_INST_OBSERVE_CLOCK_DVPHT_ENABLE_DIVIDER_OBSERVE_CLOCK_DEFAULT 0x00000000
-
-/* CLKGEN :: DVP_HT_INST_OBSERVE_CLOCK :: DVPHT_CONTROL_OBSERVE_CLOCK [03:00] */
-#define BCHP_CLKGEN_DVP_HT_INST_OBSERVE_CLOCK_DVPHT_CONTROL_OBSERVE_CLOCK_MASK 0x0000000f
-#define BCHP_CLKGEN_DVP_HT_INST_OBSERVE_CLOCK_DVPHT_CONTROL_OBSERVE_CLOCK_SHIFT 0
-#define BCHP_CLKGEN_DVP_HT_INST_OBSERVE_CLOCK_DVPHT_CONTROL_OBSERVE_CLOCK_DEFAULT 0x00000000
-
-/***************************************************************************
- *EAGLET_TOP_CORE_INST_CLOCK_ENABLE - Eaglet top core inst clock enable
- ***************************************************************************/
-/* CLKGEN :: EAGLET_TOP_CORE_INST_CLOCK_ENABLE :: reserved0 [31:04] */
-#define BCHP_CLKGEN_EAGLET_TOP_CORE_INST_CLOCK_ENABLE_reserved0_MASK 0xfffffff0
-#define BCHP_CLKGEN_EAGLET_TOP_CORE_INST_CLOCK_ENABLE_reserved0_SHIFT 4
-
-/* CLKGEN :: EAGLET_TOP_CORE_INST_CLOCK_ENABLE :: A15C_SCB_CLOCK_ENABLE [03:03] */
-#define BCHP_CLKGEN_EAGLET_TOP_CORE_INST_CLOCK_ENABLE_A15C_SCB_CLOCK_ENABLE_MASK 0x00000008
-#define BCHP_CLKGEN_EAGLET_TOP_CORE_INST_CLOCK_ENABLE_A15C_SCB_CLOCK_ENABLE_SHIFT 3
-#define BCHP_CLKGEN_EAGLET_TOP_CORE_INST_CLOCK_ENABLE_A15C_SCB_CLOCK_ENABLE_DEFAULT 0x00000001
-
-/* CLKGEN :: EAGLET_TOP_CORE_INST_CLOCK_ENABLE :: A15C_GISB_CLOCK_ENABLE [02:02] */
-#define BCHP_CLKGEN_EAGLET_TOP_CORE_INST_CLOCK_ENABLE_A15C_GISB_CLOCK_ENABLE_MASK 0x00000004
-#define BCHP_CLKGEN_EAGLET_TOP_CORE_INST_CLOCK_ENABLE_A15C_GISB_CLOCK_ENABLE_SHIFT 2
-#define BCHP_CLKGEN_EAGLET_TOP_CORE_INST_CLOCK_ENABLE_A15C_GISB_CLOCK_ENABLE_DEFAULT 0x00000001
-
-/* CLKGEN :: EAGLET_TOP_CORE_INST_CLOCK_ENABLE :: A15C_CPU_SECURE_CLOCK_ENABLE [01:01] */
-#define BCHP_CLKGEN_EAGLET_TOP_CORE_INST_CLOCK_ENABLE_A15C_CPU_SECURE_CLOCK_ENABLE_MASK 0x00000002
-#define BCHP_CLKGEN_EAGLET_TOP_CORE_INST_CLOCK_ENABLE_A15C_CPU_SECURE_CLOCK_ENABLE_SHIFT 1
-#define BCHP_CLKGEN_EAGLET_TOP_CORE_INST_CLOCK_ENABLE_A15C_CPU_SECURE_CLOCK_ENABLE_DEFAULT 0x00000001
-
-/* CLKGEN :: EAGLET_TOP_CORE_INST_CLOCK_ENABLE :: A15C_CPU_C_54_CLOCK_ENABLE [00:00] */
-#define BCHP_CLKGEN_EAGLET_TOP_CORE_INST_CLOCK_ENABLE_A15C_CPU_C_54_CLOCK_ENABLE_MASK 0x00000001
-#define BCHP_CLKGEN_EAGLET_TOP_CORE_INST_CLOCK_ENABLE_A15C_CPU_C_54_CLOCK_ENABLE_SHIFT 0
-#define BCHP_CLKGEN_EAGLET_TOP_CORE_INST_CLOCK_ENABLE_A15C_CPU_C_54_CLOCK_ENABLE_DEFAULT 0x00000001
-
-/***************************************************************************
- *EAGLET_TOP_CORE_INST_CLOCK_ENABLE_STATUS - Clock Enable Status
- ***************************************************************************/
-/* CLKGEN :: EAGLET_TOP_CORE_INST_CLOCK_ENABLE_STATUS :: reserved0 [31:04] */
-#define BCHP_CLKGEN_EAGLET_TOP_CORE_INST_CLOCK_ENABLE_STATUS_reserved0_MASK 0xfffffff0
-#define BCHP_CLKGEN_EAGLET_TOP_CORE_INST_CLOCK_ENABLE_STATUS_reserved0_SHIFT 4
-
-/* CLKGEN :: EAGLET_TOP_CORE_INST_CLOCK_ENABLE_STATUS :: A15C_SCB_CLOCK_ENABLE_STATUS [03:03] */
-#define BCHP_CLKGEN_EAGLET_TOP_CORE_INST_CLOCK_ENABLE_STATUS_A15C_SCB_CLOCK_ENABLE_STATUS_MASK 0x00000008
-#define BCHP_CLKGEN_EAGLET_TOP_CORE_INST_CLOCK_ENABLE_STATUS_A15C_SCB_CLOCK_ENABLE_STATUS_SHIFT 3
-
-/* CLKGEN :: EAGLET_TOP_CORE_INST_CLOCK_ENABLE_STATUS :: A15C_GISB_CLOCK_ENABLE_STATUS [02:02] */
-#define BCHP_CLKGEN_EAGLET_TOP_CORE_INST_CLOCK_ENABLE_STATUS_A15C_GISB_CLOCK_ENABLE_STATUS_MASK 0x00000004
-#define BCHP_CLKGEN_EAGLET_TOP_CORE_INST_CLOCK_ENABLE_STATUS_A15C_GISB_CLOCK_ENABLE_STATUS_SHIFT 2
-
-/* CLKGEN :: EAGLET_TOP_CORE_INST_CLOCK_ENABLE_STATUS :: A15C_CPU_SECURE_CLOCK_ENABLE_STATUS [01:01] */
-#define BCHP_CLKGEN_EAGLET_TOP_CORE_INST_CLOCK_ENABLE_STATUS_A15C_CPU_SECURE_CLOCK_ENABLE_STATUS_MASK 0x00000002
-#define BCHP_CLKGEN_EAGLET_TOP_CORE_INST_CLOCK_ENABLE_STATUS_A15C_CPU_SECURE_CLOCK_ENABLE_STATUS_SHIFT 1
-
-/* CLKGEN :: EAGLET_TOP_CORE_INST_CLOCK_ENABLE_STATUS :: A15C_CPU_C_54_CLOCK_ENABLE_STATUS [00:00] */
-#define BCHP_CLKGEN_EAGLET_TOP_CORE_INST_CLOCK_ENABLE_STATUS_A15C_CPU_C_54_CLOCK_ENABLE_STATUS_MASK 0x00000001
-#define BCHP_CLKGEN_EAGLET_TOP_CORE_INST_CLOCK_ENABLE_STATUS_A15C_CPU_C_54_CLOCK_ENABLE_STATUS_SHIFT 0
-
-/***************************************************************************
- *EAGLET_TOP_ROUTER_INST_CLOCK_ENABLE - Eaglet top router inst clock enable
- ***************************************************************************/
-/* CLKGEN :: EAGLET_TOP_ROUTER_INST_CLOCK_ENABLE :: reserved0 [31:04] */
-#define BCHP_CLKGEN_EAGLET_TOP_ROUTER_INST_CLOCK_ENABLE_reserved0_MASK 0xfffffff0
-#define BCHP_CLKGEN_EAGLET_TOP_ROUTER_INST_CLOCK_ENABLE_reserved0_SHIFT 4
-
-/* CLKGEN :: EAGLET_TOP_ROUTER_INST_CLOCK_ENABLE :: A15R_SCB_CLOCK_ENABLE [03:03] */
-#define BCHP_CLKGEN_EAGLET_TOP_ROUTER_INST_CLOCK_ENABLE_A15R_SCB_CLOCK_ENABLE_MASK 0x00000008
-#define BCHP_CLKGEN_EAGLET_TOP_ROUTER_INST_CLOCK_ENABLE_A15R_SCB_CLOCK_ENABLE_SHIFT 3
-#define BCHP_CLKGEN_EAGLET_TOP_ROUTER_INST_CLOCK_ENABLE_A15R_SCB_CLOCK_ENABLE_DEFAULT 0x00000001
-
-/* CLKGEN :: EAGLET_TOP_ROUTER_INST_CLOCK_ENABLE :: A15R_GISB_CLOCK_ENABLE [02:02] */
-#define BCHP_CLKGEN_EAGLET_TOP_ROUTER_INST_CLOCK_ENABLE_A15R_GISB_CLOCK_ENABLE_MASK 0x00000004
-#define BCHP_CLKGEN_EAGLET_TOP_ROUTER_INST_CLOCK_ENABLE_A15R_GISB_CLOCK_ENABLE_SHIFT 2
-#define BCHP_CLKGEN_EAGLET_TOP_ROUTER_INST_CLOCK_ENABLE_A15R_GISB_CLOCK_ENABLE_DEFAULT 0x00000001
-
-/* CLKGEN :: EAGLET_TOP_ROUTER_INST_CLOCK_ENABLE :: A15R_CPU_SECURE_CLOCK_ENABLE [01:01] */
-#define BCHP_CLKGEN_EAGLET_TOP_ROUTER_INST_CLOCK_ENABLE_A15R_CPU_SECURE_CLOCK_ENABLE_MASK 0x00000002
-#define BCHP_CLKGEN_EAGLET_TOP_ROUTER_INST_CLOCK_ENABLE_A15R_CPU_SECURE_CLOCK_ENABLE_SHIFT 1
-#define BCHP_CLKGEN_EAGLET_TOP_ROUTER_INST_CLOCK_ENABLE_A15R_CPU_SECURE_CLOCK_ENABLE_DEFAULT 0x00000001
-
-/* CLKGEN :: EAGLET_TOP_ROUTER_INST_CLOCK_ENABLE :: A15R_CPU_54_CLOCK_ENABLE [00:00] */
-#define BCHP_CLKGEN_EAGLET_TOP_ROUTER_INST_CLOCK_ENABLE_A15R_CPU_54_CLOCK_ENABLE_MASK 0x00000001
-#define BCHP_CLKGEN_EAGLET_TOP_ROUTER_INST_CLOCK_ENABLE_A15R_CPU_54_CLOCK_ENABLE_SHIFT 0
-#define BCHP_CLKGEN_EAGLET_TOP_ROUTER_INST_CLOCK_ENABLE_A15R_CPU_54_CLOCK_ENABLE_DEFAULT 0x00000001
-
-/***************************************************************************
- *EAGLET_TOP_ROUTER_INST_CLOCK_ENABLE_STATUS - Clock Enable Status
- ***************************************************************************/
-/* CLKGEN :: EAGLET_TOP_ROUTER_INST_CLOCK_ENABLE_STATUS :: reserved0 [31:04] */
-#define BCHP_CLKGEN_EAGLET_TOP_ROUTER_INST_CLOCK_ENABLE_STATUS_reserved0_MASK 0xfffffff0
-#define BCHP_CLKGEN_EAGLET_TOP_ROUTER_INST_CLOCK_ENABLE_STATUS_reserved0_SHIFT 4
-
-/* CLKGEN :: EAGLET_TOP_ROUTER_INST_CLOCK_ENABLE_STATUS :: A15R_SCB_CLOCK_ENABLE_STATUS [03:03] */
-#define BCHP_CLKGEN_EAGLET_TOP_ROUTER_INST_CLOCK_ENABLE_STATUS_A15R_SCB_CLOCK_ENABLE_STATUS_MASK 0x00000008
-#define BCHP_CLKGEN_EAGLET_TOP_ROUTER_INST_CLOCK_ENABLE_STATUS_A15R_SCB_CLOCK_ENABLE_STATUS_SHIFT 3
-
-/* CLKGEN :: EAGLET_TOP_ROUTER_INST_CLOCK_ENABLE_STATUS :: A15R_GISB_CLOCK_ENABLE_STATUS [02:02] */
-#define BCHP_CLKGEN_EAGLET_TOP_ROUTER_INST_CLOCK_ENABLE_STATUS_A15R_GISB_CLOCK_ENABLE_STATUS_MASK 0x00000004
-#define BCHP_CLKGEN_EAGLET_TOP_ROUTER_INST_CLOCK_ENABLE_STATUS_A15R_GISB_CLOCK_ENABLE_STATUS_SHIFT 2
-
-/* CLKGEN :: EAGLET_TOP_ROUTER_INST_CLOCK_ENABLE_STATUS :: A15R_CPU_SECURE_CLOCK_ENABLE_STATUS [01:01] */
-#define BCHP_CLKGEN_EAGLET_TOP_ROUTER_INST_CLOCK_ENABLE_STATUS_A15R_CPU_SECURE_CLOCK_ENABLE_STATUS_MASK 0x00000002
-#define BCHP_CLKGEN_EAGLET_TOP_ROUTER_INST_CLOCK_ENABLE_STATUS_A15R_CPU_SECURE_CLOCK_ENABLE_STATUS_SHIFT 1
-
-/* CLKGEN :: EAGLET_TOP_ROUTER_INST_CLOCK_ENABLE_STATUS :: A15R_CPU_54_CLOCK_ENABLE_STATUS [00:00] */
-#define BCHP_CLKGEN_EAGLET_TOP_ROUTER_INST_CLOCK_ENABLE_STATUS_A15R_CPU_54_CLOCK_ENABLE_STATUS_MASK 0x00000001
-#define BCHP_CLKGEN_EAGLET_TOP_ROUTER_INST_CLOCK_ENABLE_STATUS_A15R_CPU_54_CLOCK_ENABLE_STATUS_SHIFT 0
-
-/***************************************************************************
- *EAGLET_TOP_ROUTER_INST_SELECT - Eaglet top router inst select
- ***************************************************************************/
-/* CLKGEN :: EAGLET_TOP_ROUTER_INST_SELECT :: reserved0 [31:01] */
-#define BCHP_CLKGEN_EAGLET_TOP_ROUTER_INST_SELECT_reserved0_MASK 0xfffffffe
-#define BCHP_CLKGEN_EAGLET_TOP_ROUTER_INST_SELECT_reserved0_SHIFT 1
-
-/* CLKGEN :: EAGLET_TOP_ROUTER_INST_SELECT :: ROUTER_CPU_PLL_CLOCK_SELECT [00:00] */
-#define BCHP_CLKGEN_EAGLET_TOP_ROUTER_INST_SELECT_ROUTER_CPU_PLL_CLOCK_SELECT_MASK 0x00000001
-#define BCHP_CLKGEN_EAGLET_TOP_ROUTER_INST_SELECT_ROUTER_CPU_PLL_CLOCK_SELECT_SHIFT 0
-#define BCHP_CLKGEN_EAGLET_TOP_ROUTER_INST_SELECT_ROUTER_CPU_PLL_CLOCK_SELECT_DEFAULT 0x00000000
-
-/***************************************************************************
- *EGPHY28_4PORT_33V_90O_FC_INST_CLOCK_SELECT - Egphy28 4port 33v 90o fc inst clock select
- ***************************************************************************/
-/* CLKGEN :: EGPHY28_4PORT_33V_90O_FC_INST_CLOCK_SELECT :: reserved0 [31:02] */
-#define BCHP_CLKGEN_EGPHY28_4PORT_33V_90O_FC_INST_CLOCK_SELECT_reserved0_MASK 0xfffffffc
-#define BCHP_CLKGEN_EGPHY28_4PORT_33V_90O_FC_INST_CLOCK_SELECT_reserved0_SHIFT 2
-
-/* CLKGEN :: EGPHY28_4PORT_33V_90O_FC_INST_CLOCK_SELECT :: EGPHY_PLL_CLOCK_SELECT [01:01] */
-#define BCHP_CLKGEN_EGPHY28_4PORT_33V_90O_FC_INST_CLOCK_SELECT_EGPHY_PLL_CLOCK_SELECT_MASK 0x00000002
-#define BCHP_CLKGEN_EGPHY28_4PORT_33V_90O_FC_INST_CLOCK_SELECT_EGPHY_PLL_CLOCK_SELECT_SHIFT 1
-#define BCHP_CLKGEN_EGPHY28_4PORT_33V_90O_FC_INST_CLOCK_SELECT_EGPHY_PLL_CLOCK_SELECT_DEFAULT 0x00000000
-
-/* CLKGEN :: EGPHY28_4PORT_33V_90O_FC_INST_CLOCK_SELECT :: EGPHY_25_50_CLOCK_SELECT [00:00] */
-#define BCHP_CLKGEN_EGPHY28_4PORT_33V_90O_FC_INST_CLOCK_SELECT_EGPHY_25_50_CLOCK_SELECT_MASK 0x00000001
-#define BCHP_CLKGEN_EGPHY28_4PORT_33V_90O_FC_INST_CLOCK_SELECT_EGPHY_25_50_CLOCK_SELECT_SHIFT 0
-#define BCHP_CLKGEN_EGPHY28_4PORT_33V_90O_FC_INST_CLOCK_SELECT_EGPHY_25_50_CLOCK_SELECT_DEFAULT 0x00000000
-
-/***************************************************************************
- *G2U_U2U_UBUS_MOD_SS_INST_CLOCK_ENABLE - G2u u2u ubus mod ss inst clock enable
- ***************************************************************************/
-/* CLKGEN :: G2U_U2U_UBUS_MOD_SS_INST_CLOCK_ENABLE :: reserved0 [31:02] */
-#define BCHP_CLKGEN_G2U_U2U_UBUS_MOD_SS_INST_CLOCK_ENABLE_reserved0_MASK 0xfffffffc
-#define BCHP_CLKGEN_G2U_U2U_UBUS_MOD_SS_INST_CLOCK_ENABLE_reserved0_SHIFT 2
-
-/* CLKGEN :: G2U_U2U_UBUS_MOD_SS_INST_CLOCK_ENABLE :: G2U_GISB_CLOCK_ENABLE [01:01] */
-#define BCHP_CLKGEN_G2U_U2U_UBUS_MOD_SS_INST_CLOCK_ENABLE_G2U_GISB_CLOCK_ENABLE_MASK 0x00000002
-#define BCHP_CLKGEN_G2U_U2U_UBUS_MOD_SS_INST_CLOCK_ENABLE_G2U_GISB_CLOCK_ENABLE_SHIFT 1
-#define BCHP_CLKGEN_G2U_U2U_UBUS_MOD_SS_INST_CLOCK_ENABLE_G2U_GISB_CLOCK_ENABLE_DEFAULT 0x00000001
-
-/* CLKGEN :: G2U_U2U_UBUS_MOD_SS_INST_CLOCK_ENABLE :: G2U_54_CLOCK_ENABLE [00:00] */
-#define BCHP_CLKGEN_G2U_U2U_UBUS_MOD_SS_INST_CLOCK_ENABLE_G2U_54_CLOCK_ENABLE_MASK 0x00000001
-#define BCHP_CLKGEN_G2U_U2U_UBUS_MOD_SS_INST_CLOCK_ENABLE_G2U_54_CLOCK_ENABLE_SHIFT 0
-#define BCHP_CLKGEN_G2U_U2U_UBUS_MOD_SS_INST_CLOCK_ENABLE_G2U_54_CLOCK_ENABLE_DEFAULT 0x00000001
-
-/***************************************************************************
- *G2U_U2U_UBUS_MOD_SS_INST_CLOCK_ENABLE_STATUS - Clock Enable Status
- ***************************************************************************/
-/* CLKGEN :: G2U_U2U_UBUS_MOD_SS_INST_CLOCK_ENABLE_STATUS :: reserved0 [31:02] */
-#define BCHP_CLKGEN_G2U_U2U_UBUS_MOD_SS_INST_CLOCK_ENABLE_STATUS_reserved0_MASK 0xfffffffc
-#define BCHP_CLKGEN_G2U_U2U_UBUS_MOD_SS_INST_CLOCK_ENABLE_STATUS_reserved0_SHIFT 2
-
-/* CLKGEN :: G2U_U2U_UBUS_MOD_SS_INST_CLOCK_ENABLE_STATUS :: G2U_GISB_CLOCK_ENABLE_STATUS [01:01] */
-#define BCHP_CLKGEN_G2U_U2U_UBUS_MOD_SS_INST_CLOCK_ENABLE_STATUS_G2U_GISB_CLOCK_ENABLE_STATUS_MASK 0x00000002
-#define BCHP_CLKGEN_G2U_U2U_UBUS_MOD_SS_INST_CLOCK_ENABLE_STATUS_G2U_GISB_CLOCK_ENABLE_STATUS_SHIFT 1
-
-/* CLKGEN :: G2U_U2U_UBUS_MOD_SS_INST_CLOCK_ENABLE_STATUS :: G2U_54_CLOCK_ENABLE_STATUS [00:00] */
-#define BCHP_CLKGEN_G2U_U2U_UBUS_MOD_SS_INST_CLOCK_ENABLE_STATUS_G2U_54_CLOCK_ENABLE_STATUS_MASK 0x00000001
-#define BCHP_CLKGEN_G2U_U2U_UBUS_MOD_SS_INST_CLOCK_ENABLE_STATUS_G2U_54_CLOCK_ENABLE_STATUS_SHIFT 0
-
-/***************************************************************************
- *GFAP_TOP_INST_CLOCK_DISABLE - Disable GFAP_TOP_INST's clocks
- ***************************************************************************/
-/* CLKGEN :: GFAP_TOP_INST_CLOCK_DISABLE :: reserved0 [31:03] */
-#define BCHP_CLKGEN_GFAP_TOP_INST_CLOCK_DISABLE_reserved0_MASK 0xfffffff8
-#define BCHP_CLKGEN_GFAP_TOP_INST_CLOCK_DISABLE_reserved0_SHIFT 3
-
-/* CLKGEN :: GFAP_TOP_INST_CLOCK_DISABLE :: DISABLE_GFAP_324_CLOCK [02:02] */
-#define BCHP_CLKGEN_GFAP_TOP_INST_CLOCK_DISABLE_DISABLE_GFAP_324_CLOCK_MASK 0x00000004
-#define BCHP_CLKGEN_GFAP_TOP_INST_CLOCK_DISABLE_DISABLE_GFAP_324_CLOCK_SHIFT 2
-#define BCHP_CLKGEN_GFAP_TOP_INST_CLOCK_DISABLE_DISABLE_GFAP_324_CLOCK_DEFAULT 0x00000000
-
-/* CLKGEN :: GFAP_TOP_INST_CLOCK_DISABLE :: DISABLE_GFAP_25_CLOCK [01:01] */
-#define BCHP_CLKGEN_GFAP_TOP_INST_CLOCK_DISABLE_DISABLE_GFAP_25_CLOCK_MASK 0x00000002
-#define BCHP_CLKGEN_GFAP_TOP_INST_CLOCK_DISABLE_DISABLE_GFAP_25_CLOCK_SHIFT 1
-#define BCHP_CLKGEN_GFAP_TOP_INST_CLOCK_DISABLE_DISABLE_GFAP_25_CLOCK_DEFAULT 0x00000000
-
-/* CLKGEN :: GFAP_TOP_INST_CLOCK_DISABLE :: DISABLE_CG_TCK_SCAN_CLOCK [00:00] */
-#define BCHP_CLKGEN_GFAP_TOP_INST_CLOCK_DISABLE_DISABLE_CG_TCK_SCAN_CLOCK_MASK 0x00000001
-#define BCHP_CLKGEN_GFAP_TOP_INST_CLOCK_DISABLE_DISABLE_CG_TCK_SCAN_CLOCK_SHIFT 0
-#define BCHP_CLKGEN_GFAP_TOP_INST_CLOCK_DISABLE_DISABLE_CG_TCK_SCAN_CLOCK_DEFAULT 0x00000000
-
-/***************************************************************************
- *GFAP_TOP_INST_CLOCK_DISABLE_STATUS - Clock Disable Status
- ***************************************************************************/
-/* CLKGEN :: GFAP_TOP_INST_CLOCK_DISABLE_STATUS :: reserved0 [31:03] */
-#define BCHP_CLKGEN_GFAP_TOP_INST_CLOCK_DISABLE_STATUS_reserved0_MASK 0xfffffff8
-#define BCHP_CLKGEN_GFAP_TOP_INST_CLOCK_DISABLE_STATUS_reserved0_SHIFT 3
-
-/* CLKGEN :: GFAP_TOP_INST_CLOCK_DISABLE_STATUS :: DISABLE_GFAP_324_CLOCK_STATUS [02:02] */
-#define BCHP_CLKGEN_GFAP_TOP_INST_CLOCK_DISABLE_STATUS_DISABLE_GFAP_324_CLOCK_STATUS_MASK 0x00000004
-#define BCHP_CLKGEN_GFAP_TOP_INST_CLOCK_DISABLE_STATUS_DISABLE_GFAP_324_CLOCK_STATUS_SHIFT 2
-
-/* CLKGEN :: GFAP_TOP_INST_CLOCK_DISABLE_STATUS :: DISABLE_GFAP_25_CLOCK_STATUS [01:01] */
-#define BCHP_CLKGEN_GFAP_TOP_INST_CLOCK_DISABLE_STATUS_DISABLE_GFAP_25_CLOCK_STATUS_MASK 0x00000002
-#define BCHP_CLKGEN_GFAP_TOP_INST_CLOCK_DISABLE_STATUS_DISABLE_GFAP_25_CLOCK_STATUS_SHIFT 1
-
-/* CLKGEN :: GFAP_TOP_INST_CLOCK_DISABLE_STATUS :: DISABLE_CG_TCK_SCAN_CLOCK_STATUS [00:00] */
-#define BCHP_CLKGEN_GFAP_TOP_INST_CLOCK_DISABLE_STATUS_DISABLE_CG_TCK_SCAN_CLOCK_STATUS_MASK 0x00000001
-#define BCHP_CLKGEN_GFAP_TOP_INST_CLOCK_DISABLE_STATUS_DISABLE_CG_TCK_SCAN_CLOCK_STATUS_SHIFT 0
-
-/***************************************************************************
- *GFAP_TOP_INST_CLOCK_ENABLE - Gfap top inst clock enable
- ***************************************************************************/
-/* CLKGEN :: GFAP_TOP_INST_CLOCK_ENABLE :: reserved0 [31:02] */
-#define BCHP_CLKGEN_GFAP_TOP_INST_CLOCK_ENABLE_reserved0_MASK 0xfffffffc
-#define BCHP_CLKGEN_GFAP_TOP_INST_CLOCK_ENABLE_reserved0_SHIFT 2
-
-/* CLKGEN :: GFAP_TOP_INST_CLOCK_ENABLE :: GFAP_54_CLOCK_ENABLE [01:01] */
-#define BCHP_CLKGEN_GFAP_TOP_INST_CLOCK_ENABLE_GFAP_54_CLOCK_ENABLE_MASK 0x00000002
-#define BCHP_CLKGEN_GFAP_TOP_INST_CLOCK_ENABLE_GFAP_54_CLOCK_ENABLE_SHIFT 1
-#define BCHP_CLKGEN_GFAP_TOP_INST_CLOCK_ENABLE_GFAP_54_CLOCK_ENABLE_DEFAULT 0x00000001
-
-/* CLKGEN :: GFAP_TOP_INST_CLOCK_ENABLE :: GFAP_324_CLOCK_ENABLE [00:00] */
-#define BCHP_CLKGEN_GFAP_TOP_INST_CLOCK_ENABLE_GFAP_324_CLOCK_ENABLE_MASK 0x00000001
-#define BCHP_CLKGEN_GFAP_TOP_INST_CLOCK_ENABLE_GFAP_324_CLOCK_ENABLE_SHIFT 0
-#define BCHP_CLKGEN_GFAP_TOP_INST_CLOCK_ENABLE_GFAP_324_CLOCK_ENABLE_DEFAULT 0x00000001
-
-/***************************************************************************
- *GFAP_TOP_INST_CLOCK_ENABLE0 - Gfap top inst clock enable0
- ***************************************************************************/
-/* CLKGEN :: GFAP_TOP_INST_CLOCK_ENABLE0 :: reserved0 [31:02] */
-#define BCHP_CLKGEN_GFAP_TOP_INST_CLOCK_ENABLE0_reserved0_MASK 0xfffffffc
-#define BCHP_CLKGEN_GFAP_TOP_INST_CLOCK_ENABLE0_reserved0_SHIFT 2
-
-/* CLKGEN :: GFAP_TOP_INST_CLOCK_ENABLE0 :: GFAP_SCB_CLOCK_ENABLE0 [01:01] */
-#define BCHP_CLKGEN_GFAP_TOP_INST_CLOCK_ENABLE0_GFAP_SCB_CLOCK_ENABLE0_MASK 0x00000002
-#define BCHP_CLKGEN_GFAP_TOP_INST_CLOCK_ENABLE0_GFAP_SCB_CLOCK_ENABLE0_SHIFT 1
-#define BCHP_CLKGEN_GFAP_TOP_INST_CLOCK_ENABLE0_GFAP_SCB_CLOCK_ENABLE0_DEFAULT 0x00000001
-
-/* CLKGEN :: GFAP_TOP_INST_CLOCK_ENABLE0 :: GFAP_M2MC0_GISB_CLOCK_ENABLE0 [00:00] */
-#define BCHP_CLKGEN_GFAP_TOP_INST_CLOCK_ENABLE0_GFAP_M2MC0_GISB_CLOCK_ENABLE0_MASK 0x00000001
-#define BCHP_CLKGEN_GFAP_TOP_INST_CLOCK_ENABLE0_GFAP_M2MC0_GISB_CLOCK_ENABLE0_SHIFT 0
-#define BCHP_CLKGEN_GFAP_TOP_INST_CLOCK_ENABLE0_GFAP_M2MC0_GISB_CLOCK_ENABLE0_DEFAULT 0x00000001
-
-/***************************************************************************
- *GFAP_TOP_INST_CLOCK_ENABLE0_STATUS - Clock Enable Status
- ***************************************************************************/
-/* CLKGEN :: GFAP_TOP_INST_CLOCK_ENABLE0_STATUS :: reserved0 [31:02] */
-#define BCHP_CLKGEN_GFAP_TOP_INST_CLOCK_ENABLE0_STATUS_reserved0_MASK 0xfffffffc
-#define BCHP_CLKGEN_GFAP_TOP_INST_CLOCK_ENABLE0_STATUS_reserved0_SHIFT 2
-
-/* CLKGEN :: GFAP_TOP_INST_CLOCK_ENABLE0_STATUS :: GFAP_SCB_CLOCK_ENABLE0_STATUS [01:01] */
-#define BCHP_CLKGEN_GFAP_TOP_INST_CLOCK_ENABLE0_STATUS_GFAP_SCB_CLOCK_ENABLE0_STATUS_MASK 0x00000002
-#define BCHP_CLKGEN_GFAP_TOP_INST_CLOCK_ENABLE0_STATUS_GFAP_SCB_CLOCK_ENABLE0_STATUS_SHIFT 1
-
-/* CLKGEN :: GFAP_TOP_INST_CLOCK_ENABLE0_STATUS :: GFAP_M2MC0_GISB_CLOCK_ENABLE0_STATUS [00:00] */
-#define BCHP_CLKGEN_GFAP_TOP_INST_CLOCK_ENABLE0_STATUS_GFAP_M2MC0_GISB_CLOCK_ENABLE0_STATUS_MASK 0x00000001
-#define BCHP_CLKGEN_GFAP_TOP_INST_CLOCK_ENABLE0_STATUS_GFAP_M2MC0_GISB_CLOCK_ENABLE0_STATUS_SHIFT 0
-
-/***************************************************************************
- *GFAP_TOP_INST_CLOCK_ENABLE_STATUS - Clock Enable Status
- ***************************************************************************/
-/* CLKGEN :: GFAP_TOP_INST_CLOCK_ENABLE_STATUS :: reserved0 [31:02] */
-#define BCHP_CLKGEN_GFAP_TOP_INST_CLOCK_ENABLE_STATUS_reserved0_MASK 0xfffffffc
-#define BCHP_CLKGEN_GFAP_TOP_INST_CLOCK_ENABLE_STATUS_reserved0_SHIFT 2
-
-/* CLKGEN :: GFAP_TOP_INST_CLOCK_ENABLE_STATUS :: GFAP_54_CLOCK_ENABLE_STATUS [01:01] */
-#define BCHP_CLKGEN_GFAP_TOP_INST_CLOCK_ENABLE_STATUS_GFAP_54_CLOCK_ENABLE_STATUS_MASK 0x00000002
-#define BCHP_CLKGEN_GFAP_TOP_INST_CLOCK_ENABLE_STATUS_GFAP_54_CLOCK_ENABLE_STATUS_SHIFT 1
-
-/* CLKGEN :: GFAP_TOP_INST_CLOCK_ENABLE_STATUS :: GFAP_324_CLOCK_ENABLE_STATUS [00:00] */
-#define BCHP_CLKGEN_GFAP_TOP_INST_CLOCK_ENABLE_STATUS_GFAP_324_CLOCK_ENABLE_STATUS_MASK 0x00000001
-#define BCHP_CLKGEN_GFAP_TOP_INST_CLOCK_ENABLE_STATUS_GFAP_324_CLOCK_ENABLE_STATUS_SHIFT 0
-
-/***************************************************************************
- *GRAPHICS_INST_CLOCK_ENABLE - Graphics inst clock enable
- ***************************************************************************/
-/* CLKGEN :: GRAPHICS_INST_CLOCK_ENABLE :: reserved0 [31:01] */
-#define BCHP_CLKGEN_GRAPHICS_INST_CLOCK_ENABLE_reserved0_MASK 0xfffffffe
-#define BCHP_CLKGEN_GRAPHICS_INST_CLOCK_ENABLE_reserved0_SHIFT 1
-
-/* CLKGEN :: GRAPHICS_INST_CLOCK_ENABLE :: GFX_54_CLOCK_ENABLE [00:00] */
-#define BCHP_CLKGEN_GRAPHICS_INST_CLOCK_ENABLE_GFX_54_CLOCK_ENABLE_MASK 0x00000001
-#define BCHP_CLKGEN_GRAPHICS_INST_CLOCK_ENABLE_GFX_54_CLOCK_ENABLE_SHIFT 0
-#define BCHP_CLKGEN_GRAPHICS_INST_CLOCK_ENABLE_GFX_54_CLOCK_ENABLE_DEFAULT 0x00000001
-
-/***************************************************************************
- *GRAPHICS_INST_CLOCK_ENABLE0 - Graphics inst clock enable0
- ***************************************************************************/
-/* CLKGEN :: GRAPHICS_INST_CLOCK_ENABLE0 :: reserved0 [31:02] */
-#define BCHP_CLKGEN_GRAPHICS_INST_CLOCK_ENABLE0_reserved0_MASK 0xfffffffc
-#define BCHP_CLKGEN_GRAPHICS_INST_CLOCK_ENABLE0_reserved0_SHIFT 2
-
-/* CLKGEN :: GRAPHICS_INST_CLOCK_ENABLE0 :: GFX_M2MC0_SCB_CLOCK_ENABLE0 [01:01] */
-#define BCHP_CLKGEN_GRAPHICS_INST_CLOCK_ENABLE0_GFX_M2MC0_SCB_CLOCK_ENABLE0_MASK 0x00000002
-#define BCHP_CLKGEN_GRAPHICS_INST_CLOCK_ENABLE0_GFX_M2MC0_SCB_CLOCK_ENABLE0_SHIFT 1
-#define BCHP_CLKGEN_GRAPHICS_INST_CLOCK_ENABLE0_GFX_M2MC0_SCB_CLOCK_ENABLE0_DEFAULT 0x00000001
-
-/* CLKGEN :: GRAPHICS_INST_CLOCK_ENABLE0 :: GFX_M2MC0_GISB_CLOCK_ENABLE0 [00:00] */
-#define BCHP_CLKGEN_GRAPHICS_INST_CLOCK_ENABLE0_GFX_M2MC0_GISB_CLOCK_ENABLE0_MASK 0x00000001
-#define BCHP_CLKGEN_GRAPHICS_INST_CLOCK_ENABLE0_GFX_M2MC0_GISB_CLOCK_ENABLE0_SHIFT 0
-#define BCHP_CLKGEN_GRAPHICS_INST_CLOCK_ENABLE0_GFX_M2MC0_GISB_CLOCK_ENABLE0_DEFAULT 0x00000001
-
-/***************************************************************************
- *GRAPHICS_INST_CLOCK_ENABLE0_STATUS - Clock Enable Status
- ***************************************************************************/
-/* CLKGEN :: GRAPHICS_INST_CLOCK_ENABLE0_STATUS :: reserved0 [31:02] */
-#define BCHP_CLKGEN_GRAPHICS_INST_CLOCK_ENABLE0_STATUS_reserved0_MASK 0xfffffffc
-#define BCHP_CLKGEN_GRAPHICS_INST_CLOCK_ENABLE0_STATUS_reserved0_SHIFT 2
-
-/* CLKGEN :: GRAPHICS_INST_CLOCK_ENABLE0_STATUS :: GFX_M2MC0_SCB_CLOCK_ENABLE0_STATUS [01:01] */
-#define BCHP_CLKGEN_GRAPHICS_INST_CLOCK_ENABLE0_STATUS_GFX_M2MC0_SCB_CLOCK_ENABLE0_STATUS_MASK 0x00000002
-#define BCHP_CLKGEN_GRAPHICS_INST_CLOCK_ENABLE0_STATUS_GFX_M2MC0_SCB_CLOCK_ENABLE0_STATUS_SHIFT 1
-
-/* CLKGEN :: GRAPHICS_INST_CLOCK_ENABLE0_STATUS :: GFX_M2MC0_GISB_CLOCK_ENABLE0_STATUS [00:00] */
-#define BCHP_CLKGEN_GRAPHICS_INST_CLOCK_ENABLE0_STATUS_GFX_M2MC0_GISB_CLOCK_ENABLE0_STATUS_MASK 0x00000001
-#define BCHP_CLKGEN_GRAPHICS_INST_CLOCK_ENABLE0_STATUS_GFX_M2MC0_GISB_CLOCK_ENABLE0_STATUS_SHIFT 0
-
-/***************************************************************************
- *GRAPHICS_INST_CLOCK_ENABLE1 - Graphics inst clock enable1
- ***************************************************************************/
-/* CLKGEN :: GRAPHICS_INST_CLOCK_ENABLE1 :: reserved0 [31:02] */
-#define BCHP_CLKGEN_GRAPHICS_INST_CLOCK_ENABLE1_reserved0_MASK 0xfffffffc
-#define BCHP_CLKGEN_GRAPHICS_INST_CLOCK_ENABLE1_reserved0_SHIFT 2
-
-/* CLKGEN :: GRAPHICS_INST_CLOCK_ENABLE1 :: GFX_M2MC1_SCB_CLOCK_ENABLE1 [01:01] */
-#define BCHP_CLKGEN_GRAPHICS_INST_CLOCK_ENABLE1_GFX_M2MC1_SCB_CLOCK_ENABLE1_MASK 0x00000002
-#define BCHP_CLKGEN_GRAPHICS_INST_CLOCK_ENABLE1_GFX_M2MC1_SCB_CLOCK_ENABLE1_SHIFT 1
-#define BCHP_CLKGEN_GRAPHICS_INST_CLOCK_ENABLE1_GFX_M2MC1_SCB_CLOCK_ENABLE1_DEFAULT 0x00000001
-
-/* CLKGEN :: GRAPHICS_INST_CLOCK_ENABLE1 :: GFX_M2MC1_GISB_CLOCK_ENABLE1 [00:00] */
-#define BCHP_CLKGEN_GRAPHICS_INST_CLOCK_ENABLE1_GFX_M2MC1_GISB_CLOCK_ENABLE1_MASK 0x00000001
-#define BCHP_CLKGEN_GRAPHICS_INST_CLOCK_ENABLE1_GFX_M2MC1_GISB_CLOCK_ENABLE1_SHIFT 0
-#define BCHP_CLKGEN_GRAPHICS_INST_CLOCK_ENABLE1_GFX_M2MC1_GISB_CLOCK_ENABLE1_DEFAULT 0x00000001
-
-/***************************************************************************
- *GRAPHICS_INST_CLOCK_ENABLE1_STATUS - Clock Enable Status
- ***************************************************************************/
-/* CLKGEN :: GRAPHICS_INST_CLOCK_ENABLE1_STATUS :: reserved0 [31:02] */
-#define BCHP_CLKGEN_GRAPHICS_INST_CLOCK_ENABLE1_STATUS_reserved0_MASK 0xfffffffc
-#define BCHP_CLKGEN_GRAPHICS_INST_CLOCK_ENABLE1_STATUS_reserved0_SHIFT 2
-
-/* CLKGEN :: GRAPHICS_INST_CLOCK_ENABLE1_STATUS :: GFX_M2MC1_SCB_CLOCK_ENABLE1_STATUS [01:01] */
-#define BCHP_CLKGEN_GRAPHICS_INST_CLOCK_ENABLE1_STATUS_GFX_M2MC1_SCB_CLOCK_ENABLE1_STATUS_MASK 0x00000002
-#define BCHP_CLKGEN_GRAPHICS_INST_CLOCK_ENABLE1_STATUS_GFX_M2MC1_SCB_CLOCK_ENABLE1_STATUS_SHIFT 1
-
-/* CLKGEN :: GRAPHICS_INST_CLOCK_ENABLE1_STATUS :: GFX_M2MC1_GISB_CLOCK_ENABLE1_STATUS [00:00] */
-#define BCHP_CLKGEN_GRAPHICS_INST_CLOCK_ENABLE1_STATUS_GFX_M2MC1_GISB_CLOCK_ENABLE1_STATUS_MASK 0x00000001
-#define BCHP_CLKGEN_GRAPHICS_INST_CLOCK_ENABLE1_STATUS_GFX_M2MC1_GISB_CLOCK_ENABLE1_STATUS_SHIFT 0
-
-/***************************************************************************
- *GRAPHICS_INST_CLOCK_ENABLE_M2MC0 - Graphics inst clock enable m2mc0
- ***************************************************************************/
-/* CLKGEN :: GRAPHICS_INST_CLOCK_ENABLE_M2MC0 :: reserved0 [31:01] */
-#define BCHP_CLKGEN_GRAPHICS_INST_CLOCK_ENABLE_M2MC0_reserved0_MASK 0xfffffffe
-#define BCHP_CLKGEN_GRAPHICS_INST_CLOCK_ENABLE_M2MC0_reserved0_SHIFT 1
-
-/* CLKGEN :: GRAPHICS_INST_CLOCK_ENABLE_M2MC0 :: GFX_M2MC0_CLOCK_ENABLE_M2MC0 [00:00] */
-#define BCHP_CLKGEN_GRAPHICS_INST_CLOCK_ENABLE_M2MC0_GFX_M2MC0_CLOCK_ENABLE_M2MC0_MASK 0x00000001
-#define BCHP_CLKGEN_GRAPHICS_INST_CLOCK_ENABLE_M2MC0_GFX_M2MC0_CLOCK_ENABLE_M2MC0_SHIFT 0
-#define BCHP_CLKGEN_GRAPHICS_INST_CLOCK_ENABLE_M2MC0_GFX_M2MC0_CLOCK_ENABLE_M2MC0_DEFAULT 0x00000001
-
-/***************************************************************************
- *GRAPHICS_INST_CLOCK_ENABLE_M2MC0_STATUS - Clock Enable Status
- ***************************************************************************/
-/* CLKGEN :: GRAPHICS_INST_CLOCK_ENABLE_M2MC0_STATUS :: reserved0 [31:01] */
-#define BCHP_CLKGEN_GRAPHICS_INST_CLOCK_ENABLE_M2MC0_STATUS_reserved0_MASK 0xfffffffe
-#define BCHP_CLKGEN_GRAPHICS_INST_CLOCK_ENABLE_M2MC0_STATUS_reserved0_SHIFT 1
-
-/* CLKGEN :: GRAPHICS_INST_CLOCK_ENABLE_M2MC0_STATUS :: GFX_M2MC0_CLOCK_ENABLE_M2MC0_STATUS [00:00] */
-#define BCHP_CLKGEN_GRAPHICS_INST_CLOCK_ENABLE_M2MC0_STATUS_GFX_M2MC0_CLOCK_ENABLE_M2MC0_STATUS_MASK 0x00000001
-#define BCHP_CLKGEN_GRAPHICS_INST_CLOCK_ENABLE_M2MC0_STATUS_GFX_M2MC0_CLOCK_ENABLE_M2MC0_STATUS_SHIFT 0
-
-/***************************************************************************
- *GRAPHICS_INST_CLOCK_ENABLE_M2MC1 - Graphics inst clock enable m2mc1
- ***************************************************************************/
-/* CLKGEN :: GRAPHICS_INST_CLOCK_ENABLE_M2MC1 :: reserved0 [31:01] */
-#define BCHP_CLKGEN_GRAPHICS_INST_CLOCK_ENABLE_M2MC1_reserved0_MASK 0xfffffffe
-#define BCHP_CLKGEN_GRAPHICS_INST_CLOCK_ENABLE_M2MC1_reserved0_SHIFT 1
-
-/* CLKGEN :: GRAPHICS_INST_CLOCK_ENABLE_M2MC1 :: GFX_M2MC1_CLOCK_ENABLE_M2MC1 [00:00] */
-#define BCHP_CLKGEN_GRAPHICS_INST_CLOCK_ENABLE_M2MC1_GFX_M2MC1_CLOCK_ENABLE_M2MC1_MASK 0x00000001
-#define BCHP_CLKGEN_GRAPHICS_INST_CLOCK_ENABLE_M2MC1_GFX_M2MC1_CLOCK_ENABLE_M2MC1_SHIFT 0
-#define BCHP_CLKGEN_GRAPHICS_INST_CLOCK_ENABLE_M2MC1_GFX_M2MC1_CLOCK_ENABLE_M2MC1_DEFAULT 0x00000001
-
-/***************************************************************************
- *GRAPHICS_INST_CLOCK_ENABLE_M2MC1_STATUS - Clock Enable Status
- ***************************************************************************/
-/* CLKGEN :: GRAPHICS_INST_CLOCK_ENABLE_M2MC1_STATUS :: reserved0 [31:01] */
-#define BCHP_CLKGEN_GRAPHICS_INST_CLOCK_ENABLE_M2MC1_STATUS_reserved0_MASK 0xfffffffe
-#define BCHP_CLKGEN_GRAPHICS_INST_CLOCK_ENABLE_M2MC1_STATUS_reserved0_SHIFT 1
-
-/* CLKGEN :: GRAPHICS_INST_CLOCK_ENABLE_M2MC1_STATUS :: GFX_M2MC1_CLOCK_ENABLE_M2MC1_STATUS [00:00] */
-#define BCHP_CLKGEN_GRAPHICS_INST_CLOCK_ENABLE_M2MC1_STATUS_GFX_M2MC1_CLOCK_ENABLE_M2MC1_STATUS_MASK 0x00000001
-#define BCHP_CLKGEN_GRAPHICS_INST_CLOCK_ENABLE_M2MC1_STATUS_GFX_M2MC1_CLOCK_ENABLE_M2MC1_STATUS_SHIFT 0
-
-/***************************************************************************
- *GRAPHICS_INST_CLOCK_ENABLE_STATUS - Clock Enable Status
- ***************************************************************************/
-/* CLKGEN :: GRAPHICS_INST_CLOCK_ENABLE_STATUS :: reserved0 [31:01] */
-#define BCHP_CLKGEN_GRAPHICS_INST_CLOCK_ENABLE_STATUS_reserved0_MASK 0xfffffffe
-#define BCHP_CLKGEN_GRAPHICS_INST_CLOCK_ENABLE_STATUS_reserved0_SHIFT 1
-
-/* CLKGEN :: GRAPHICS_INST_CLOCK_ENABLE_STATUS :: GFX_54_CLOCK_ENABLE_STATUS [00:00] */
-#define BCHP_CLKGEN_GRAPHICS_INST_CLOCK_ENABLE_STATUS_GFX_54_CLOCK_ENABLE_STATUS_MASK 0x00000001
-#define BCHP_CLKGEN_GRAPHICS_INST_CLOCK_ENABLE_STATUS_GFX_54_CLOCK_ENABLE_STATUS_SHIFT 0
-
-/***************************************************************************
- *GRAPHICS_INST_OBSERVE_CLOCK - Graphics inst observe clock
- ***************************************************************************/
-/* CLKGEN :: GRAPHICS_INST_OBSERVE_CLOCK :: reserved0 [31:06] */
-#define BCHP_CLKGEN_GRAPHICS_INST_OBSERVE_CLOCK_reserved0_MASK 0xffffffc0
-#define BCHP_CLKGEN_GRAPHICS_INST_OBSERVE_CLOCK_reserved0_SHIFT 6
-
-/* CLKGEN :: GRAPHICS_INST_OBSERVE_CLOCK :: GFX_ENABLE_OBSERVE_CLOCK [05:05] */
-#define BCHP_CLKGEN_GRAPHICS_INST_OBSERVE_CLOCK_GFX_ENABLE_OBSERVE_CLOCK_MASK 0x00000020
-#define BCHP_CLKGEN_GRAPHICS_INST_OBSERVE_CLOCK_GFX_ENABLE_OBSERVE_CLOCK_SHIFT 5
-#define BCHP_CLKGEN_GRAPHICS_INST_OBSERVE_CLOCK_GFX_ENABLE_OBSERVE_CLOCK_DEFAULT 0x00000000
-
-/* CLKGEN :: GRAPHICS_INST_OBSERVE_CLOCK :: GFX_ENABLE_DIVIDER_OBSERVE_CLOCK [04:04] */
-#define BCHP_CLKGEN_GRAPHICS_INST_OBSERVE_CLOCK_GFX_ENABLE_DIVIDER_OBSERVE_CLOCK_MASK 0x00000010
-#define BCHP_CLKGEN_GRAPHICS_INST_OBSERVE_CLOCK_GFX_ENABLE_DIVIDER_OBSERVE_CLOCK_SHIFT 4
-#define BCHP_CLKGEN_GRAPHICS_INST_OBSERVE_CLOCK_GFX_ENABLE_DIVIDER_OBSERVE_CLOCK_DEFAULT 0x00000000
-
-/* CLKGEN :: GRAPHICS_INST_OBSERVE_CLOCK :: GFX_CONTROL_OBSERVE_CLOCK [03:00] */
-#define BCHP_CLKGEN_GRAPHICS_INST_OBSERVE_CLOCK_GFX_CONTROL_OBSERVE_CLOCK_MASK 0x0000000f
-#define BCHP_CLKGEN_GRAPHICS_INST_OBSERVE_CLOCK_GFX_CONTROL_OBSERVE_CLOCK_SHIFT 0
-#define BCHP_CLKGEN_GRAPHICS_INST_OBSERVE_CLOCK_GFX_CONTROL_OBSERVE_CLOCK_DEFAULT 0x00000000
-
-/***************************************************************************
- *HIF_INST_CLOCK_DISABLE - Disable HIF_INST's clocks
- ***************************************************************************/
-/* CLKGEN :: HIF_INST_CLOCK_DISABLE :: reserved0 [31:06] */
-#define BCHP_CLKGEN_HIF_INST_CLOCK_DISABLE_reserved0_MASK 0xffffffc0
-#define BCHP_CLKGEN_HIF_INST_CLOCK_DISABLE_reserved0_SHIFT 6
-
-/* CLKGEN :: HIF_INST_CLOCK_DISABLE :: DISABLE_PAD_OUTPUT_EBI_CLOCK [05:05] */
-#define BCHP_CLKGEN_HIF_INST_CLOCK_DISABLE_DISABLE_PAD_OUTPUT_EBI_CLOCK_MASK 0x00000020
-#define BCHP_CLKGEN_HIF_INST_CLOCK_DISABLE_DISABLE_PAD_OUTPUT_EBI_CLOCK_SHIFT 5
-#define BCHP_CLKGEN_HIF_INST_CLOCK_DISABLE_DISABLE_PAD_OUTPUT_EBI_CLOCK_DEFAULT 0x00000000
-
-/* CLKGEN :: HIF_INST_CLOCK_DISABLE :: DISABLE_NAND_DDR_CLOCK [04:04] */
-#define BCHP_CLKGEN_HIF_INST_CLOCK_DISABLE_DISABLE_NAND_DDR_CLOCK_MASK 0x00000010
-#define BCHP_CLKGEN_HIF_INST_CLOCK_DISABLE_DISABLE_NAND_DDR_CLOCK_SHIFT 4
-#define BCHP_CLKGEN_HIF_INST_CLOCK_DISABLE_DISABLE_NAND_DDR_CLOCK_DEFAULT 0x00000000
-
-/* CLKGEN :: HIF_INST_CLOCK_DISABLE :: DISABLE_HIF_SPI_CLOCK [03:03] */
-#define BCHP_CLKGEN_HIF_INST_CLOCK_DISABLE_DISABLE_HIF_SPI_CLOCK_MASK 0x00000008
-#define BCHP_CLKGEN_HIF_INST_CLOCK_DISABLE_DISABLE_HIF_SPI_CLOCK_SHIFT 3
-#define BCHP_CLKGEN_HIF_INST_CLOCK_DISABLE_DISABLE_HIF_SPI_CLOCK_DEFAULT 0x00000000
-
-/* CLKGEN :: HIF_INST_CLOCK_DISABLE :: DISABLE_HIF_SDIO_EMMC_CLOCK [02:02] */
-#define BCHP_CLKGEN_HIF_INST_CLOCK_DISABLE_DISABLE_HIF_SDIO_EMMC_CLOCK_MASK 0x00000004
-#define BCHP_CLKGEN_HIF_INST_CLOCK_DISABLE_DISABLE_HIF_SDIO_EMMC_CLOCK_SHIFT 2
-#define BCHP_CLKGEN_HIF_INST_CLOCK_DISABLE_DISABLE_HIF_SDIO_EMMC_CLOCK_DEFAULT 0x00000000
-
-/* CLKGEN :: HIF_INST_CLOCK_DISABLE :: DISABLE_HIF_SDIO_CARD_CLOCK [01:01] */
-#define BCHP_CLKGEN_HIF_INST_CLOCK_DISABLE_DISABLE_HIF_SDIO_CARD_CLOCK_MASK 0x00000002
-#define BCHP_CLKGEN_HIF_INST_CLOCK_DISABLE_DISABLE_HIF_SDIO_CARD_CLOCK_SHIFT 1
-#define BCHP_CLKGEN_HIF_INST_CLOCK_DISABLE_DISABLE_HIF_SDIO_CARD_CLOCK_DEFAULT 0x00000000
-
-/* CLKGEN :: HIF_INST_CLOCK_DISABLE :: DISABLE_HIF_ALWAYSON_CLOCK [00:00] */
-#define BCHP_CLKGEN_HIF_INST_CLOCK_DISABLE_DISABLE_HIF_ALWAYSON_CLOCK_MASK 0x00000001
-#define BCHP_CLKGEN_HIF_INST_CLOCK_DISABLE_DISABLE_HIF_ALWAYSON_CLOCK_SHIFT 0
-#define BCHP_CLKGEN_HIF_INST_CLOCK_DISABLE_DISABLE_HIF_ALWAYSON_CLOCK_DEFAULT 0x00000000
-
-/***************************************************************************
- *HIF_INST_CLOCK_DISABLE_STATUS - Clock Disable Status
- ***************************************************************************/
-/* CLKGEN :: HIF_INST_CLOCK_DISABLE_STATUS :: reserved0 [31:06] */
-#define BCHP_CLKGEN_HIF_INST_CLOCK_DISABLE_STATUS_reserved0_MASK 0xffffffc0
-#define BCHP_CLKGEN_HIF_INST_CLOCK_DISABLE_STATUS_reserved0_SHIFT 6
-
-/* CLKGEN :: HIF_INST_CLOCK_DISABLE_STATUS :: DISABLE_PAD_OUTPUT_EBI_CLOCK_STATUS [05:05] */
-#define BCHP_CLKGEN_HIF_INST_CLOCK_DISABLE_STATUS_DISABLE_PAD_OUTPUT_EBI_CLOCK_STATUS_MASK 0x00000020
-#define BCHP_CLKGEN_HIF_INST_CLOCK_DISABLE_STATUS_DISABLE_PAD_OUTPUT_EBI_CLOCK_STATUS_SHIFT 5
-
-/* CLKGEN :: HIF_INST_CLOCK_DISABLE_STATUS :: DISABLE_NAND_DDR_CLOCK_STATUS [04:04] */
-#define BCHP_CLKGEN_HIF_INST_CLOCK_DISABLE_STATUS_DISABLE_NAND_DDR_CLOCK_STATUS_MASK 0x00000010
-#define BCHP_CLKGEN_HIF_INST_CLOCK_DISABLE_STATUS_DISABLE_NAND_DDR_CLOCK_STATUS_SHIFT 4
-
-/* CLKGEN :: HIF_INST_CLOCK_DISABLE_STATUS :: DISABLE_HIF_SPI_CLOCK_STATUS [03:03] */
-#define BCHP_CLKGEN_HIF_INST_CLOCK_DISABLE_STATUS_DISABLE_HIF_SPI_CLOCK_STATUS_MASK 0x00000008
-#define BCHP_CLKGEN_HIF_INST_CLOCK_DISABLE_STATUS_DISABLE_HIF_SPI_CLOCK_STATUS_SHIFT 3
-
-/* CLKGEN :: HIF_INST_CLOCK_DISABLE_STATUS :: DISABLE_HIF_SDIO_EMMC_CLOCK_STATUS [02:02] */
-#define BCHP_CLKGEN_HIF_INST_CLOCK_DISABLE_STATUS_DISABLE_HIF_SDIO_EMMC_CLOCK_STATUS_MASK 0x00000004
-#define BCHP_CLKGEN_HIF_INST_CLOCK_DISABLE_STATUS_DISABLE_HIF_SDIO_EMMC_CLOCK_STATUS_SHIFT 2
-
-/* CLKGEN :: HIF_INST_CLOCK_DISABLE_STATUS :: DISABLE_HIF_SDIO_CARD_CLOCK_STATUS [01:01] */
-#define BCHP_CLKGEN_HIF_INST_CLOCK_DISABLE_STATUS_DISABLE_HIF_SDIO_CARD_CLOCK_STATUS_MASK 0x00000002
-#define BCHP_CLKGEN_HIF_INST_CLOCK_DISABLE_STATUS_DISABLE_HIF_SDIO_CARD_CLOCK_STATUS_SHIFT 1
-
-/* CLKGEN :: HIF_INST_CLOCK_DISABLE_STATUS :: DISABLE_HIF_ALWAYSON_CLOCK_STATUS [00:00] */
-#define BCHP_CLKGEN_HIF_INST_CLOCK_DISABLE_STATUS_DISABLE_HIF_ALWAYSON_CLOCK_STATUS_MASK 0x00000001
-#define BCHP_CLKGEN_HIF_INST_CLOCK_DISABLE_STATUS_DISABLE_HIF_ALWAYSON_CLOCK_STATUS_SHIFT 0
-
-/***************************************************************************
- *HIF_INST_CLOCK_ENABLE - Hif inst clock enable
- ***************************************************************************/
-/* CLKGEN :: HIF_INST_CLOCK_ENABLE :: reserved0 [31:01] */
-#define BCHP_CLKGEN_HIF_INST_CLOCK_ENABLE_reserved0_MASK 0xfffffffe
-#define BCHP_CLKGEN_HIF_INST_CLOCK_ENABLE_reserved0_SHIFT 1
-
-/* CLKGEN :: HIF_INST_CLOCK_ENABLE :: HIF_54_CLOCK_ENABLE [00:00] */
-#define BCHP_CLKGEN_HIF_INST_CLOCK_ENABLE_HIF_54_CLOCK_ENABLE_MASK 0x00000001
-#define BCHP_CLKGEN_HIF_INST_CLOCK_ENABLE_HIF_54_CLOCK_ENABLE_SHIFT 0
-#define BCHP_CLKGEN_HIF_INST_CLOCK_ENABLE_HIF_54_CLOCK_ENABLE_DEFAULT 0x00000001
-
-/***************************************************************************
- *HIF_INST_CLOCK_ENABLE_STATUS - Clock Enable Status
- ***************************************************************************/
-/* CLKGEN :: HIF_INST_CLOCK_ENABLE_STATUS :: reserved0 [31:01] */
-#define BCHP_CLKGEN_HIF_INST_CLOCK_ENABLE_STATUS_reserved0_MASK 0xfffffffe
-#define BCHP_CLKGEN_HIF_INST_CLOCK_ENABLE_STATUS_reserved0_SHIFT 1
-
-/* CLKGEN :: HIF_INST_CLOCK_ENABLE_STATUS :: HIF_54_CLOCK_ENABLE_STATUS [00:00] */
-#define BCHP_CLKGEN_HIF_INST_CLOCK_ENABLE_STATUS_HIF_54_CLOCK_ENABLE_STATUS_MASK 0x00000001
-#define BCHP_CLKGEN_HIF_INST_CLOCK_ENABLE_STATUS_HIF_54_CLOCK_ENABLE_STATUS_SHIFT 0
-
-/***************************************************************************
- *HIF_INST_OBSERVE_CLOCK - Hif inst observe clock
- ***************************************************************************/
-/* CLKGEN :: HIF_INST_OBSERVE_CLOCK :: reserved0 [31:06] */
-#define BCHP_CLKGEN_HIF_INST_OBSERVE_CLOCK_reserved0_MASK 0xffffffc0
-#define BCHP_CLKGEN_HIF_INST_OBSERVE_CLOCK_reserved0_SHIFT 6
-
-/* CLKGEN :: HIF_INST_OBSERVE_CLOCK :: HIF_ENABLE_OBSERVE_CLOCK [05:05] */
-#define BCHP_CLKGEN_HIF_INST_OBSERVE_CLOCK_HIF_ENABLE_OBSERVE_CLOCK_MASK 0x00000020
-#define BCHP_CLKGEN_HIF_INST_OBSERVE_CLOCK_HIF_ENABLE_OBSERVE_CLOCK_SHIFT 5
-#define BCHP_CLKGEN_HIF_INST_OBSERVE_CLOCK_HIF_ENABLE_OBSERVE_CLOCK_DEFAULT 0x00000000
-
-/* CLKGEN :: HIF_INST_OBSERVE_CLOCK :: HIF_ENABLE_DIVIDER_OBSERVE_CLOCK [04:04] */
-#define BCHP_CLKGEN_HIF_INST_OBSERVE_CLOCK_HIF_ENABLE_DIVIDER_OBSERVE_CLOCK_MASK 0x00000010
-#define BCHP_CLKGEN_HIF_INST_OBSERVE_CLOCK_HIF_ENABLE_DIVIDER_OBSERVE_CLOCK_SHIFT 4
-#define BCHP_CLKGEN_HIF_INST_OBSERVE_CLOCK_HIF_ENABLE_DIVIDER_OBSERVE_CLOCK_DEFAULT 0x00000000
-
-/* CLKGEN :: HIF_INST_OBSERVE_CLOCK :: HIF_CONTROL_OBSERVE_CLOCK [03:00] */
-#define BCHP_CLKGEN_HIF_INST_OBSERVE_CLOCK_HIF_CONTROL_OBSERVE_CLOCK_MASK 0x0000000f
-#define BCHP_CLKGEN_HIF_INST_OBSERVE_CLOCK_HIF_CONTROL_OBSERVE_CLOCK_SHIFT 0
-#define BCHP_CLKGEN_HIF_INST_OBSERVE_CLOCK_HIF_CONTROL_OBSERVE_CLOCK_DEFAULT 0x00000000
-
-/***************************************************************************
- *HVD0_TOP_INST_CLOCK_ENABLE - Hvd0 top inst clock enable
- ***************************************************************************/
-/* CLKGEN :: HVD0_TOP_INST_CLOCK_ENABLE :: reserved0 [31:05] */
-#define BCHP_CLKGEN_HVD0_TOP_INST_CLOCK_ENABLE_reserved0_MASK 0xffffffe0
-#define BCHP_CLKGEN_HVD0_TOP_INST_CLOCK_ENABLE_reserved0_SHIFT 5
-
-/* CLKGEN :: HVD0_TOP_INST_CLOCK_ENABLE :: HVD0_SCB_CLOCK_ENABLE [04:04] */
-#define BCHP_CLKGEN_HVD0_TOP_INST_CLOCK_ENABLE_HVD0_SCB_CLOCK_ENABLE_MASK 0x00000010
-#define BCHP_CLKGEN_HVD0_TOP_INST_CLOCK_ENABLE_HVD0_SCB_CLOCK_ENABLE_SHIFT 4
-#define BCHP_CLKGEN_HVD0_TOP_INST_CLOCK_ENABLE_HVD0_SCB_CLOCK_ENABLE_DEFAULT 0x00000001
-
-/* CLKGEN :: HVD0_TOP_INST_CLOCK_ENABLE :: HVD0_GISB_CLOCK_ENABLE [03:03] */
-#define BCHP_CLKGEN_HVD0_TOP_INST_CLOCK_ENABLE_HVD0_GISB_CLOCK_ENABLE_MASK 0x00000008
-#define BCHP_CLKGEN_HVD0_TOP_INST_CLOCK_ENABLE_HVD0_GISB_CLOCK_ENABLE_SHIFT 3
-#define BCHP_CLKGEN_HVD0_TOP_INST_CLOCK_ENABLE_HVD0_GISB_CLOCK_ENABLE_DEFAULT 0x00000001
-
-/* CLKGEN :: HVD0_TOP_INST_CLOCK_ENABLE :: HVD0_CPU_CLOCK_ENABLE [02:02] */
-#define BCHP_CLKGEN_HVD0_TOP_INST_CLOCK_ENABLE_HVD0_CPU_CLOCK_ENABLE_MASK 0x00000004
-#define BCHP_CLKGEN_HVD0_TOP_INST_CLOCK_ENABLE_HVD0_CPU_CLOCK_ENABLE_SHIFT 2
-#define BCHP_CLKGEN_HVD0_TOP_INST_CLOCK_ENABLE_HVD0_CPU_CLOCK_ENABLE_DEFAULT 0x00000001
-
-/* CLKGEN :: HVD0_TOP_INST_CLOCK_ENABLE :: HVD0_CORE_CLOCK_ENABLE [01:01] */
-#define BCHP_CLKGEN_HVD0_TOP_INST_CLOCK_ENABLE_HVD0_CORE_CLOCK_ENABLE_MASK 0x00000002
-#define BCHP_CLKGEN_HVD0_TOP_INST_CLOCK_ENABLE_HVD0_CORE_CLOCK_ENABLE_SHIFT 1
-#define BCHP_CLKGEN_HVD0_TOP_INST_CLOCK_ENABLE_HVD0_CORE_CLOCK_ENABLE_DEFAULT 0x00000001
-
-/* CLKGEN :: HVD0_TOP_INST_CLOCK_ENABLE :: HVD0_54_CLOCK_ENABLE [00:00] */
-#define BCHP_CLKGEN_HVD0_TOP_INST_CLOCK_ENABLE_HVD0_54_CLOCK_ENABLE_MASK 0x00000001
-#define BCHP_CLKGEN_HVD0_TOP_INST_CLOCK_ENABLE_HVD0_54_CLOCK_ENABLE_SHIFT 0
-#define BCHP_CLKGEN_HVD0_TOP_INST_CLOCK_ENABLE_HVD0_54_CLOCK_ENABLE_DEFAULT 0x00000001
-
-/***************************************************************************
- *HVD0_TOP_INST_CLOCK_ENABLE_STATUS - Clock Enable Status
- ***************************************************************************/
-/* CLKGEN :: HVD0_TOP_INST_CLOCK_ENABLE_STATUS :: reserved0 [31:05] */
-#define BCHP_CLKGEN_HVD0_TOP_INST_CLOCK_ENABLE_STATUS_reserved0_MASK 0xffffffe0
-#define BCHP_CLKGEN_HVD0_TOP_INST_CLOCK_ENABLE_STATUS_reserved0_SHIFT 5
-
-/* CLKGEN :: HVD0_TOP_INST_CLOCK_ENABLE_STATUS :: HVD0_SCB_CLOCK_ENABLE_STATUS [04:04] */
-#define BCHP_CLKGEN_HVD0_TOP_INST_CLOCK_ENABLE_STATUS_HVD0_SCB_CLOCK_ENABLE_STATUS_MASK 0x00000010
-#define BCHP_CLKGEN_HVD0_TOP_INST_CLOCK_ENABLE_STATUS_HVD0_SCB_CLOCK_ENABLE_STATUS_SHIFT 4
-
-/* CLKGEN :: HVD0_TOP_INST_CLOCK_ENABLE_STATUS :: HVD0_GISB_CLOCK_ENABLE_STATUS [03:03] */
-#define BCHP_CLKGEN_HVD0_TOP_INST_CLOCK_ENABLE_STATUS_HVD0_GISB_CLOCK_ENABLE_STATUS_MASK 0x00000008
-#define BCHP_CLKGEN_HVD0_TOP_INST_CLOCK_ENABLE_STATUS_HVD0_GISB_CLOCK_ENABLE_STATUS_SHIFT 3
-
-/* CLKGEN :: HVD0_TOP_INST_CLOCK_ENABLE_STATUS :: HVD0_CPU_CLOCK_ENABLE_STATUS [02:02] */
-#define BCHP_CLKGEN_HVD0_TOP_INST_CLOCK_ENABLE_STATUS_HVD0_CPU_CLOCK_ENABLE_STATUS_MASK 0x00000004
-#define BCHP_CLKGEN_HVD0_TOP_INST_CLOCK_ENABLE_STATUS_HVD0_CPU_CLOCK_ENABLE_STATUS_SHIFT 2
-
-/* CLKGEN :: HVD0_TOP_INST_CLOCK_ENABLE_STATUS :: HVD0_CORE_CLOCK_ENABLE_STATUS [01:01] */
-#define BCHP_CLKGEN_HVD0_TOP_INST_CLOCK_ENABLE_STATUS_HVD0_CORE_CLOCK_ENABLE_STATUS_MASK 0x00000002
-#define BCHP_CLKGEN_HVD0_TOP_INST_CLOCK_ENABLE_STATUS_HVD0_CORE_CLOCK_ENABLE_STATUS_SHIFT 1
-
-/* CLKGEN :: HVD0_TOP_INST_CLOCK_ENABLE_STATUS :: HVD0_54_CLOCK_ENABLE_STATUS [00:00] */
-#define BCHP_CLKGEN_HVD0_TOP_INST_CLOCK_ENABLE_STATUS_HVD0_54_CLOCK_ENABLE_STATUS_MASK 0x00000001
-#define BCHP_CLKGEN_HVD0_TOP_INST_CLOCK_ENABLE_STATUS_HVD0_54_CLOCK_ENABLE_STATUS_SHIFT 0
-
-/***************************************************************************
- *HVD0_TOP_INST_OBSERVE_CLOCK - Hvd0 top inst observe clock
- ***************************************************************************/
-/* CLKGEN :: HVD0_TOP_INST_OBSERVE_CLOCK :: reserved0 [31:06] */
-#define BCHP_CLKGEN_HVD0_TOP_INST_OBSERVE_CLOCK_reserved0_MASK 0xffffffc0
-#define BCHP_CLKGEN_HVD0_TOP_INST_OBSERVE_CLOCK_reserved0_SHIFT 6
-
-/* CLKGEN :: HVD0_TOP_INST_OBSERVE_CLOCK :: HVD0_ENABLE_OBSERVE_CLOCK [05:05] */
-#define BCHP_CLKGEN_HVD0_TOP_INST_OBSERVE_CLOCK_HVD0_ENABLE_OBSERVE_CLOCK_MASK 0x00000020
-#define BCHP_CLKGEN_HVD0_TOP_INST_OBSERVE_CLOCK_HVD0_ENABLE_OBSERVE_CLOCK_SHIFT 5
-#define BCHP_CLKGEN_HVD0_TOP_INST_OBSERVE_CLOCK_HVD0_ENABLE_OBSERVE_CLOCK_DEFAULT 0x00000000
-
-/* CLKGEN :: HVD0_TOP_INST_OBSERVE_CLOCK :: HVD0_ENABLE_DIVIDER_OBSERVE_CLOCK [04:04] */
-#define BCHP_CLKGEN_HVD0_TOP_INST_OBSERVE_CLOCK_HVD0_ENABLE_DIVIDER_OBSERVE_CLOCK_MASK 0x00000010
-#define BCHP_CLKGEN_HVD0_TOP_INST_OBSERVE_CLOCK_HVD0_ENABLE_DIVIDER_OBSERVE_CLOCK_SHIFT 4
-#define BCHP_CLKGEN_HVD0_TOP_INST_OBSERVE_CLOCK_HVD0_ENABLE_DIVIDER_OBSERVE_CLOCK_DEFAULT 0x00000000
-
-/* CLKGEN :: HVD0_TOP_INST_OBSERVE_CLOCK :: HVD0_CONTROL_OBSERVE_CLOCK [03:00] */
-#define BCHP_CLKGEN_HVD0_TOP_INST_OBSERVE_CLOCK_HVD0_CONTROL_OBSERVE_CLOCK_MASK 0x0000000f
-#define BCHP_CLKGEN_HVD0_TOP_INST_OBSERVE_CLOCK_HVD0_CONTROL_OBSERVE_CLOCK_SHIFT 0
-#define BCHP_CLKGEN_HVD0_TOP_INST_OBSERVE_CLOCK_HVD0_CONTROL_OBSERVE_CLOCK_DEFAULT 0x00000000
-
-/***************************************************************************
- *INTERNAL_MUX_SELECT - Mux selects for Internal clocks
- ***************************************************************************/
-/* CLKGEN :: INTERNAL_MUX_SELECT :: reserved0 [31:08] */
-#define BCHP_CLKGEN_INTERNAL_MUX_SELECT_reserved0_MASK 0xffffff00
-#define BCHP_CLKGEN_INTERNAL_MUX_SELECT_reserved0_SHIFT 8
-
-/* CLKGEN :: INTERNAL_MUX_SELECT :: PLLAUDIO2_REFERENCE_CLOCK [07:06] */
-#define BCHP_CLKGEN_INTERNAL_MUX_SELECT_PLLAUDIO2_REFERENCE_CLOCK_MASK 0x000000c0
-#define BCHP_CLKGEN_INTERNAL_MUX_SELECT_PLLAUDIO2_REFERENCE_CLOCK_SHIFT 6
-#define BCHP_CLKGEN_INTERNAL_MUX_SELECT_PLLAUDIO2_REFERENCE_CLOCK_DEFAULT 0x00000000
-
-/* CLKGEN :: INTERNAL_MUX_SELECT :: PLLAUDIO1_REFERENCE_CLOCK [05:04] */
-#define BCHP_CLKGEN_INTERNAL_MUX_SELECT_PLLAUDIO1_REFERENCE_CLOCK_MASK 0x00000030
-#define BCHP_CLKGEN_INTERNAL_MUX_SELECT_PLLAUDIO1_REFERENCE_CLOCK_SHIFT 4
-#define BCHP_CLKGEN_INTERNAL_MUX_SELECT_PLLAUDIO1_REFERENCE_CLOCK_DEFAULT 0x00000000
-
-/* CLKGEN :: INTERNAL_MUX_SELECT :: PLLAUDIO0_REFERENCE_CLOCK [03:02] */
-#define BCHP_CLKGEN_INTERNAL_MUX_SELECT_PLLAUDIO0_REFERENCE_CLOCK_MASK 0x0000000c
-#define BCHP_CLKGEN_INTERNAL_MUX_SELECT_PLLAUDIO0_REFERENCE_CLOCK_SHIFT 2
-#define BCHP_CLKGEN_INTERNAL_MUX_SELECT_PLLAUDIO0_REFERENCE_CLOCK_DEFAULT 0x00000000
-
-/* CLKGEN :: INTERNAL_MUX_SELECT :: DOS_SYSTEM_TP_CLOCK [01:01] */
-#define BCHP_CLKGEN_INTERNAL_MUX_SELECT_DOS_SYSTEM_TP_CLOCK_MASK 0x00000002
-#define BCHP_CLKGEN_INTERNAL_MUX_SELECT_DOS_SYSTEM_TP_CLOCK_SHIFT 1
-#define BCHP_CLKGEN_INTERNAL_MUX_SELECT_DOS_SYSTEM_TP_CLOCK_DEFAULT 0x00000000
-
-/* CLKGEN :: INTERNAL_MUX_SELECT :: DOS_SYSTEM_BPCM_CLOCK [00:00] */
-#define BCHP_CLKGEN_INTERNAL_MUX_SELECT_DOS_SYSTEM_BPCM_CLOCK_MASK 0x00000001
-#define BCHP_CLKGEN_INTERNAL_MUX_SELECT_DOS_SYSTEM_BPCM_CLOCK_SHIFT 0
-#define BCHP_CLKGEN_INTERNAL_MUX_SELECT_DOS_SYSTEM_BPCM_CLOCK_DEFAULT 0x00000000
-
-/***************************************************************************
- *ITU656_0_MUX_SELECT - Mux selects for itu656_0 clocks
- ***************************************************************************/
-/* CLKGEN :: ITU656_0_MUX_SELECT :: reserved0 [31:03] */
-#define BCHP_CLKGEN_ITU656_0_MUX_SELECT_reserved0_MASK 0xfffffff8
-#define BCHP_CLKGEN_ITU656_0_MUX_SELECT_reserved0_SHIFT 3
-
-/* CLKGEN :: ITU656_0_MUX_SELECT :: VEC_ITU656_0_CLOCK [02:01] */
-#define BCHP_CLKGEN_ITU656_0_MUX_SELECT_VEC_ITU656_0_CLOCK_MASK 0x00000006
-#define BCHP_CLKGEN_ITU656_0_MUX_SELECT_VEC_ITU656_0_CLOCK_SHIFT 1
-#define BCHP_CLKGEN_ITU656_0_MUX_SELECT_VEC_ITU656_0_CLOCK_DEFAULT 0x00000000
-
-/* CLKGEN :: ITU656_0_MUX_SELECT :: ENABLE_INVERT_VEC_ITU656_0_CLOCK [00:00] */
-#define BCHP_CLKGEN_ITU656_0_MUX_SELECT_ENABLE_INVERT_VEC_ITU656_0_CLOCK_MASK 0x00000001
-#define BCHP_CLKGEN_ITU656_0_MUX_SELECT_ENABLE_INVERT_VEC_ITU656_0_CLOCK_SHIFT 0
-#define BCHP_CLKGEN_ITU656_0_MUX_SELECT_ENABLE_INVERT_VEC_ITU656_0_CLOCK_DEFAULT 0x00000000
-
-/***************************************************************************
- *LEAP_TOP_INST_CLOCK_DISABLE - Disable LEAP_TOP_INST's clocks
- ***************************************************************************/
-/* CLKGEN :: LEAP_TOP_INST_CLOCK_DISABLE :: reserved0 [31:04] */
-#define BCHP_CLKGEN_LEAP_TOP_INST_CLOCK_DISABLE_reserved0_MASK 0xfffffff0
-#define BCHP_CLKGEN_LEAP_TOP_INST_CLOCK_DISABLE_reserved0_SHIFT 4
-
-/* CLKGEN :: LEAP_TOP_INST_CLOCK_DISABLE :: DISABLE_LEAP_27_UART_CLOCK [03:03] */
-#define BCHP_CLKGEN_LEAP_TOP_INST_CLOCK_DISABLE_DISABLE_LEAP_27_UART_CLOCK_MASK 0x00000008
-#define BCHP_CLKGEN_LEAP_TOP_INST_CLOCK_DISABLE_DISABLE_LEAP_27_UART_CLOCK_SHIFT 3
-#define BCHP_CLKGEN_LEAP_TOP_INST_CLOCK_DISABLE_DISABLE_LEAP_27_UART_CLOCK_DEFAULT 0x00000000
-
-/* CLKGEN :: LEAP_TOP_INST_CLOCK_DISABLE :: DISABLE_LEAP_216_CLOCK [02:02] */
-#define BCHP_CLKGEN_LEAP_TOP_INST_CLOCK_DISABLE_DISABLE_LEAP_216_CLOCK_MASK 0x00000004
-#define BCHP_CLKGEN_LEAP_TOP_INST_CLOCK_DISABLE_DISABLE_LEAP_216_CLOCK_SHIFT 2
-#define BCHP_CLKGEN_LEAP_TOP_INST_CLOCK_DISABLE_DISABLE_LEAP_216_CLOCK_DEFAULT 0x00000000
-
-/* CLKGEN :: LEAP_TOP_INST_CLOCK_DISABLE :: DISABLE_AVS_CLOCK [01:01] */
-#define BCHP_CLKGEN_LEAP_TOP_INST_CLOCK_DISABLE_DISABLE_AVS_CLOCK_MASK 0x00000002
-#define BCHP_CLKGEN_LEAP_TOP_INST_CLOCK_DISABLE_DISABLE_AVS_CLOCK_SHIFT 1
-#define BCHP_CLKGEN_LEAP_TOP_INST_CLOCK_DISABLE_DISABLE_AVS_CLOCK_DEFAULT 0x00000000
-
-/* CLKGEN :: LEAP_TOP_INST_CLOCK_DISABLE :: DISABLE_AVSTOP_27_UART_CLOCK [00:00] */
-#define BCHP_CLKGEN_LEAP_TOP_INST_CLOCK_DISABLE_DISABLE_AVSTOP_27_UART_CLOCK_MASK 0x00000001
-#define BCHP_CLKGEN_LEAP_TOP_INST_CLOCK_DISABLE_DISABLE_AVSTOP_27_UART_CLOCK_SHIFT 0
-#define BCHP_CLKGEN_LEAP_TOP_INST_CLOCK_DISABLE_DISABLE_AVSTOP_27_UART_CLOCK_DEFAULT 0x00000000
-
-/***************************************************************************
- *LEAP_TOP_INST_CLOCK_DISABLE_STATUS - Clock Disable Status
- ***************************************************************************/
-/* CLKGEN :: LEAP_TOP_INST_CLOCK_DISABLE_STATUS :: reserved0 [31:04] */
-#define BCHP_CLKGEN_LEAP_TOP_INST_CLOCK_DISABLE_STATUS_reserved0_MASK 0xfffffff0
-#define BCHP_CLKGEN_LEAP_TOP_INST_CLOCK_DISABLE_STATUS_reserved0_SHIFT 4
-
-/* CLKGEN :: LEAP_TOP_INST_CLOCK_DISABLE_STATUS :: DISABLE_LEAP_27_UART_CLOCK_STATUS [03:03] */
-#define BCHP_CLKGEN_LEAP_TOP_INST_CLOCK_DISABLE_STATUS_DISABLE_LEAP_27_UART_CLOCK_STATUS_MASK 0x00000008
-#define BCHP_CLKGEN_LEAP_TOP_INST_CLOCK_DISABLE_STATUS_DISABLE_LEAP_27_UART_CLOCK_STATUS_SHIFT 3
-
-/* CLKGEN :: LEAP_TOP_INST_CLOCK_DISABLE_STATUS :: DISABLE_LEAP_216_CLOCK_STATUS [02:02] */
-#define BCHP_CLKGEN_LEAP_TOP_INST_CLOCK_DISABLE_STATUS_DISABLE_LEAP_216_CLOCK_STATUS_MASK 0x00000004
-#define BCHP_CLKGEN_LEAP_TOP_INST_CLOCK_DISABLE_STATUS_DISABLE_LEAP_216_CLOCK_STATUS_SHIFT 2
-
-/* CLKGEN :: LEAP_TOP_INST_CLOCK_DISABLE_STATUS :: DISABLE_AVS_CLOCK_STATUS [01:01] */
-#define BCHP_CLKGEN_LEAP_TOP_INST_CLOCK_DISABLE_STATUS_DISABLE_AVS_CLOCK_STATUS_MASK 0x00000002
-#define BCHP_CLKGEN_LEAP_TOP_INST_CLOCK_DISABLE_STATUS_DISABLE_AVS_CLOCK_STATUS_SHIFT 1
-
-/* CLKGEN :: LEAP_TOP_INST_CLOCK_DISABLE_STATUS :: DISABLE_AVSTOP_27_UART_CLOCK_STATUS [00:00] */
-#define BCHP_CLKGEN_LEAP_TOP_INST_CLOCK_DISABLE_STATUS_DISABLE_AVSTOP_27_UART_CLOCK_STATUS_MASK 0x00000001
-#define BCHP_CLKGEN_LEAP_TOP_INST_CLOCK_DISABLE_STATUS_DISABLE_AVSTOP_27_UART_CLOCK_STATUS_SHIFT 0
-
-/***************************************************************************
- *LEAP_TOP_INST_CLOCK_ENABLE - Leap top inst clock enable
- ***************************************************************************/
-/* CLKGEN :: LEAP_TOP_INST_CLOCK_ENABLE :: reserved0 [31:04] */
-#define BCHP_CLKGEN_LEAP_TOP_INST_CLOCK_ENABLE_reserved0_MASK 0xfffffff0
-#define BCHP_CLKGEN_LEAP_TOP_INST_CLOCK_ENABLE_reserved0_SHIFT 4
-
-/* CLKGEN :: LEAP_TOP_INST_CLOCK_ENABLE :: LEAP_UNUSED_54_CLOCK_ENABLE [03:03] */
-#define BCHP_CLKGEN_LEAP_TOP_INST_CLOCK_ENABLE_LEAP_UNUSED_54_CLOCK_ENABLE_MASK 0x00000008
-#define BCHP_CLKGEN_LEAP_TOP_INST_CLOCK_ENABLE_LEAP_UNUSED_54_CLOCK_ENABLE_SHIFT 3
-#define BCHP_CLKGEN_LEAP_TOP_INST_CLOCK_ENABLE_LEAP_UNUSED_54_CLOCK_ENABLE_DEFAULT 0x00000001
-
-/* CLKGEN :: LEAP_TOP_INST_CLOCK_ENABLE :: LEAP_GISB_CLOCK_ENABLE [02:02] */
-#define BCHP_CLKGEN_LEAP_TOP_INST_CLOCK_ENABLE_LEAP_GISB_CLOCK_ENABLE_MASK 0x00000004
-#define BCHP_CLKGEN_LEAP_TOP_INST_CLOCK_ENABLE_LEAP_GISB_CLOCK_ENABLE_SHIFT 2
-#define BCHP_CLKGEN_LEAP_TOP_INST_CLOCK_ENABLE_LEAP_GISB_CLOCK_ENABLE_DEFAULT 0x00000001
-
-/* CLKGEN :: LEAP_TOP_INST_CLOCK_ENABLE :: LEAP_216_CLOCK_ENABLE [01:01] */
-#define BCHP_CLKGEN_LEAP_TOP_INST_CLOCK_ENABLE_LEAP_216_CLOCK_ENABLE_MASK 0x00000002
-#define BCHP_CLKGEN_LEAP_TOP_INST_CLOCK_ENABLE_LEAP_216_CLOCK_ENABLE_SHIFT 1
-#define BCHP_CLKGEN_LEAP_TOP_INST_CLOCK_ENABLE_LEAP_216_CLOCK_ENABLE_DEFAULT 0x00000001
-
-/* CLKGEN :: LEAP_TOP_INST_CLOCK_ENABLE :: LEAP_108_CLOCK_ENABLE [00:00] */
-#define BCHP_CLKGEN_LEAP_TOP_INST_CLOCK_ENABLE_LEAP_108_CLOCK_ENABLE_MASK 0x00000001
-#define BCHP_CLKGEN_LEAP_TOP_INST_CLOCK_ENABLE_LEAP_108_CLOCK_ENABLE_SHIFT 0
-#define BCHP_CLKGEN_LEAP_TOP_INST_CLOCK_ENABLE_LEAP_108_CLOCK_ENABLE_DEFAULT 0x00000001
-
-/***************************************************************************
- *LEAP_TOP_INST_CLOCK_ENABLE_STATUS - Clock Enable Status
- ***************************************************************************/
-/* CLKGEN :: LEAP_TOP_INST_CLOCK_ENABLE_STATUS :: reserved0 [31:04] */
-#define BCHP_CLKGEN_LEAP_TOP_INST_CLOCK_ENABLE_STATUS_reserved0_MASK 0xfffffff0
-#define BCHP_CLKGEN_LEAP_TOP_INST_CLOCK_ENABLE_STATUS_reserved0_SHIFT 4
-
-/* CLKGEN :: LEAP_TOP_INST_CLOCK_ENABLE_STATUS :: LEAP_UNUSED_54_CLOCK_ENABLE_STATUS [03:03] */
-#define BCHP_CLKGEN_LEAP_TOP_INST_CLOCK_ENABLE_STATUS_LEAP_UNUSED_54_CLOCK_ENABLE_STATUS_MASK 0x00000008
-#define BCHP_CLKGEN_LEAP_TOP_INST_CLOCK_ENABLE_STATUS_LEAP_UNUSED_54_CLOCK_ENABLE_STATUS_SHIFT 3
-
-/* CLKGEN :: LEAP_TOP_INST_CLOCK_ENABLE_STATUS :: LEAP_GISB_CLOCK_ENABLE_STATUS [02:02] */
-#define BCHP_CLKGEN_LEAP_TOP_INST_CLOCK_ENABLE_STATUS_LEAP_GISB_CLOCK_ENABLE_STATUS_MASK 0x00000004
-#define BCHP_CLKGEN_LEAP_TOP_INST_CLOCK_ENABLE_STATUS_LEAP_GISB_CLOCK_ENABLE_STATUS_SHIFT 2
-
-/* CLKGEN :: LEAP_TOP_INST_CLOCK_ENABLE_STATUS :: LEAP_216_CLOCK_ENABLE_STATUS [01:01] */
-#define BCHP_CLKGEN_LEAP_TOP_INST_CLOCK_ENABLE_STATUS_LEAP_216_CLOCK_ENABLE_STATUS_MASK 0x00000002
-#define BCHP_CLKGEN_LEAP_TOP_INST_CLOCK_ENABLE_STATUS_LEAP_216_CLOCK_ENABLE_STATUS_SHIFT 1
-
-/* CLKGEN :: LEAP_TOP_INST_CLOCK_ENABLE_STATUS :: LEAP_108_CLOCK_ENABLE_STATUS [00:00] */
-#define BCHP_CLKGEN_LEAP_TOP_INST_CLOCK_ENABLE_STATUS_LEAP_108_CLOCK_ENABLE_STATUS_MASK 0x00000001
-#define BCHP_CLKGEN_LEAP_TOP_INST_CLOCK_ENABLE_STATUS_LEAP_108_CLOCK_ENABLE_STATUS_SHIFT 0
-
-/***************************************************************************
- *LEAP_TOP_INST_OBSERVE_CLOCK - Leap top inst observe clock
- ***************************************************************************/
-/* CLKGEN :: LEAP_TOP_INST_OBSERVE_CLOCK :: reserved0 [31:06] */
-#define BCHP_CLKGEN_LEAP_TOP_INST_OBSERVE_CLOCK_reserved0_MASK 0xffffffc0
-#define BCHP_CLKGEN_LEAP_TOP_INST_OBSERVE_CLOCK_reserved0_SHIFT 6
-
-/* CLKGEN :: LEAP_TOP_INST_OBSERVE_CLOCK :: AVS_TOP_ENABLE_OBSERVE_CLOCK [05:05] */
-#define BCHP_CLKGEN_LEAP_TOP_INST_OBSERVE_CLOCK_AVS_TOP_ENABLE_OBSERVE_CLOCK_MASK 0x00000020
-#define BCHP_CLKGEN_LEAP_TOP_INST_OBSERVE_CLOCK_AVS_TOP_ENABLE_OBSERVE_CLOCK_SHIFT 5
-#define BCHP_CLKGEN_LEAP_TOP_INST_OBSERVE_CLOCK_AVS_TOP_ENABLE_OBSERVE_CLOCK_DEFAULT 0x00000000
-
-/* CLKGEN :: LEAP_TOP_INST_OBSERVE_CLOCK :: AVS_TOP_ENABLE_DIVIDER_OBSERVE_CLOCK [04:04] */
-#define BCHP_CLKGEN_LEAP_TOP_INST_OBSERVE_CLOCK_AVS_TOP_ENABLE_DIVIDER_OBSERVE_CLOCK_MASK 0x00000010
-#define BCHP_CLKGEN_LEAP_TOP_INST_OBSERVE_CLOCK_AVS_TOP_ENABLE_DIVIDER_OBSERVE_CLOCK_SHIFT 4
-#define BCHP_CLKGEN_LEAP_TOP_INST_OBSERVE_CLOCK_AVS_TOP_ENABLE_DIVIDER_OBSERVE_CLOCK_DEFAULT 0x00000000
-
-/* CLKGEN :: LEAP_TOP_INST_OBSERVE_CLOCK :: AVS_TOP_CONTROL_OBSERVE_CLOCK [03:00] */
-#define BCHP_CLKGEN_LEAP_TOP_INST_OBSERVE_CLOCK_AVS_TOP_CONTROL_OBSERVE_CLOCK_MASK 0x0000000f
-#define BCHP_CLKGEN_LEAP_TOP_INST_OBSERVE_CLOCK_AVS_TOP_CONTROL_OBSERVE_CLOCK_SHIFT 0
-#define BCHP_CLKGEN_LEAP_TOP_INST_OBSERVE_CLOCK_AVS_TOP_CONTROL_OBSERVE_CLOCK_DEFAULT 0x00000000
-
-/***************************************************************************
- *MEMSYS_32_WRAPPER_0_INST_CLOCK_ENABLE - Memsys 32 wrapper 0 inst clock enable
- ***************************************************************************/
-/* CLKGEN :: MEMSYS_32_WRAPPER_0_INST_CLOCK_ENABLE :: reserved0 [31:03] */
-#define BCHP_CLKGEN_MEMSYS_32_WRAPPER_0_INST_CLOCK_ENABLE_reserved0_MASK 0xfffffff8
-#define BCHP_CLKGEN_MEMSYS_32_WRAPPER_0_INST_CLOCK_ENABLE_reserved0_SHIFT 3
-
-/* CLKGEN :: MEMSYS_32_WRAPPER_0_INST_CLOCK_ENABLE :: MEMSYS0_SCB_CLOCK_ENABLE [02:02] */
-#define BCHP_CLKGEN_MEMSYS_32_WRAPPER_0_INST_CLOCK_ENABLE_MEMSYS0_SCB_CLOCK_ENABLE_MASK 0x00000004
-#define BCHP_CLKGEN_MEMSYS_32_WRAPPER_0_INST_CLOCK_ENABLE_MEMSYS0_SCB_CLOCK_ENABLE_SHIFT 2
-#define BCHP_CLKGEN_MEMSYS_32_WRAPPER_0_INST_CLOCK_ENABLE_MEMSYS0_SCB_CLOCK_ENABLE_DEFAULT 0x00000001
-
-/* CLKGEN :: MEMSYS_32_WRAPPER_0_INST_CLOCK_ENABLE :: MEMSYS0_GISB_CLOCK_ENABLE [01:01] */
-#define BCHP_CLKGEN_MEMSYS_32_WRAPPER_0_INST_CLOCK_ENABLE_MEMSYS0_GISB_CLOCK_ENABLE_MASK 0x00000002
-#define BCHP_CLKGEN_MEMSYS_32_WRAPPER_0_INST_CLOCK_ENABLE_MEMSYS0_GISB_CLOCK_ENABLE_SHIFT 1
-#define BCHP_CLKGEN_MEMSYS_32_WRAPPER_0_INST_CLOCK_ENABLE_MEMSYS0_GISB_CLOCK_ENABLE_DEFAULT 0x00000001
-
-/* CLKGEN :: MEMSYS_32_WRAPPER_0_INST_CLOCK_ENABLE :: MEMSYS0_54_CLOCK_ENABLE [00:00] */
-#define BCHP_CLKGEN_MEMSYS_32_WRAPPER_0_INST_CLOCK_ENABLE_MEMSYS0_54_CLOCK_ENABLE_MASK 0x00000001
-#define BCHP_CLKGEN_MEMSYS_32_WRAPPER_0_INST_CLOCK_ENABLE_MEMSYS0_54_CLOCK_ENABLE_SHIFT 0
-#define BCHP_CLKGEN_MEMSYS_32_WRAPPER_0_INST_CLOCK_ENABLE_MEMSYS0_54_CLOCK_ENABLE_DEFAULT 0x00000001
-
-/***************************************************************************
- *MEMSYS_32_WRAPPER_0_INST_CLOCK_ENABLE_STATUS - Clock Enable Status
- ***************************************************************************/
-/* CLKGEN :: MEMSYS_32_WRAPPER_0_INST_CLOCK_ENABLE_STATUS :: reserved0 [31:03] */
-#define BCHP_CLKGEN_MEMSYS_32_WRAPPER_0_INST_CLOCK_ENABLE_STATUS_reserved0_MASK 0xfffffff8
-#define BCHP_CLKGEN_MEMSYS_32_WRAPPER_0_INST_CLOCK_ENABLE_STATUS_reserved0_SHIFT 3
-
-/* CLKGEN :: MEMSYS_32_WRAPPER_0_INST_CLOCK_ENABLE_STATUS :: MEMSYS0_SCB_CLOCK_ENABLE_STATUS [02:02] */
-#define BCHP_CLKGEN_MEMSYS_32_WRAPPER_0_INST_CLOCK_ENABLE_STATUS_MEMSYS0_SCB_CLOCK_ENABLE_STATUS_MASK 0x00000004
-#define BCHP_CLKGEN_MEMSYS_32_WRAPPER_0_INST_CLOCK_ENABLE_STATUS_MEMSYS0_SCB_CLOCK_ENABLE_STATUS_SHIFT 2
-
-/* CLKGEN :: MEMSYS_32_WRAPPER_0_INST_CLOCK_ENABLE_STATUS :: MEMSYS0_GISB_CLOCK_ENABLE_STATUS [01:01] */
-#define BCHP_CLKGEN_MEMSYS_32_WRAPPER_0_INST_CLOCK_ENABLE_STATUS_MEMSYS0_GISB_CLOCK_ENABLE_STATUS_MASK 0x00000002
-#define BCHP_CLKGEN_MEMSYS_32_WRAPPER_0_INST_CLOCK_ENABLE_STATUS_MEMSYS0_GISB_CLOCK_ENABLE_STATUS_SHIFT 1
-
-/* CLKGEN :: MEMSYS_32_WRAPPER_0_INST_CLOCK_ENABLE_STATUS :: MEMSYS0_54_CLOCK_ENABLE_STATUS [00:00] */
-#define BCHP_CLKGEN_MEMSYS_32_WRAPPER_0_INST_CLOCK_ENABLE_STATUS_MEMSYS0_54_CLOCK_ENABLE_STATUS_MASK 0x00000001
-#define BCHP_CLKGEN_MEMSYS_32_WRAPPER_0_INST_CLOCK_ENABLE_STATUS_MEMSYS0_54_CLOCK_ENABLE_STATUS_SHIFT 0
-
-/***************************************************************************
- *MEMSYS_32_WRAPPER_0_INST_OBSERVE_CLOCK - Memsys 32 wrapper 0 inst observe clock
- ***************************************************************************/
-/* CLKGEN :: MEMSYS_32_WRAPPER_0_INST_OBSERVE_CLOCK :: reserved0 [31:06] */
-#define BCHP_CLKGEN_MEMSYS_32_WRAPPER_0_INST_OBSERVE_CLOCK_reserved0_MASK 0xffffffc0
-#define BCHP_CLKGEN_MEMSYS_32_WRAPPER_0_INST_OBSERVE_CLOCK_reserved0_SHIFT 6
-
-/* CLKGEN :: MEMSYS_32_WRAPPER_0_INST_OBSERVE_CLOCK :: MEMSYS0_ENABLE_OBSERVE_CLOCK [05:05] */
-#define BCHP_CLKGEN_MEMSYS_32_WRAPPER_0_INST_OBSERVE_CLOCK_MEMSYS0_ENABLE_OBSERVE_CLOCK_MASK 0x00000020
-#define BCHP_CLKGEN_MEMSYS_32_WRAPPER_0_INST_OBSERVE_CLOCK_MEMSYS0_ENABLE_OBSERVE_CLOCK_SHIFT 5
-#define BCHP_CLKGEN_MEMSYS_32_WRAPPER_0_INST_OBSERVE_CLOCK_MEMSYS0_ENABLE_OBSERVE_CLOCK_DEFAULT 0x00000000
-
-/* CLKGEN :: MEMSYS_32_WRAPPER_0_INST_OBSERVE_CLOCK :: MEMSYS0_ENABLE_DIVIDER_OBSERVE_CLOCK [04:04] */
-#define BCHP_CLKGEN_MEMSYS_32_WRAPPER_0_INST_OBSERVE_CLOCK_MEMSYS0_ENABLE_DIVIDER_OBSERVE_CLOCK_MASK 0x00000010
-#define BCHP_CLKGEN_MEMSYS_32_WRAPPER_0_INST_OBSERVE_CLOCK_MEMSYS0_ENABLE_DIVIDER_OBSERVE_CLOCK_SHIFT 4
-#define BCHP_CLKGEN_MEMSYS_32_WRAPPER_0_INST_OBSERVE_CLOCK_MEMSYS0_ENABLE_DIVIDER_OBSERVE_CLOCK_DEFAULT 0x00000000
-
-/* CLKGEN :: MEMSYS_32_WRAPPER_0_INST_OBSERVE_CLOCK :: MEMSYS0_CONTROL_OBSERVE_CLOCK [03:00] */
-#define BCHP_CLKGEN_MEMSYS_32_WRAPPER_0_INST_OBSERVE_CLOCK_MEMSYS0_CONTROL_OBSERVE_CLOCK_MASK 0x0000000f
-#define BCHP_CLKGEN_MEMSYS_32_WRAPPER_0_INST_OBSERVE_CLOCK_MEMSYS0_CONTROL_OBSERVE_CLOCK_SHIFT 0
-#define BCHP_CLKGEN_MEMSYS_32_WRAPPER_0_INST_OBSERVE_CLOCK_MEMSYS0_CONTROL_OBSERVE_CLOCK_DEFAULT 0x00000000
-
-/***************************************************************************
- *MEMSYS_32_WRAPPER_0_INST_STATUS - Memsys 32 wrapper 0 inst status
- ***************************************************************************/
-/* CLKGEN :: MEMSYS_32_WRAPPER_0_INST_STATUS :: reserved0 [31:01] */
-#define BCHP_CLKGEN_MEMSYS_32_WRAPPER_0_INST_STATUS_reserved0_MASK 0xfffffffe
-#define BCHP_CLKGEN_MEMSYS_32_WRAPPER_0_INST_STATUS_reserved0_SHIFT 1
-
-/* CLKGEN :: MEMSYS_32_WRAPPER_0_INST_STATUS :: MEMSYS0_PLL_LOCKED_STATUS [00:00] */
-#define BCHP_CLKGEN_MEMSYS_32_WRAPPER_0_INST_STATUS_MEMSYS0_PLL_LOCKED_STATUS_MASK 0x00000001
-#define BCHP_CLKGEN_MEMSYS_32_WRAPPER_0_INST_STATUS_MEMSYS0_PLL_LOCKED_STATUS_SHIFT 0
-
-/***************************************************************************
- *MEMSYS_32_WRAPPER_1_INST_CLOCK_ENABLE - Memsys 32 wrapper 1 inst clock enable
- ***************************************************************************/
-/* CLKGEN :: MEMSYS_32_WRAPPER_1_INST_CLOCK_ENABLE :: reserved0 [31:03] */
-#define BCHP_CLKGEN_MEMSYS_32_WRAPPER_1_INST_CLOCK_ENABLE_reserved0_MASK 0xfffffff8
-#define BCHP_CLKGEN_MEMSYS_32_WRAPPER_1_INST_CLOCK_ENABLE_reserved0_SHIFT 3
-
-/* CLKGEN :: MEMSYS_32_WRAPPER_1_INST_CLOCK_ENABLE :: MEMSYS1_SCB_CLOCK_ENABLE [02:02] */
-#define BCHP_CLKGEN_MEMSYS_32_WRAPPER_1_INST_CLOCK_ENABLE_MEMSYS1_SCB_CLOCK_ENABLE_MASK 0x00000004
-#define BCHP_CLKGEN_MEMSYS_32_WRAPPER_1_INST_CLOCK_ENABLE_MEMSYS1_SCB_CLOCK_ENABLE_SHIFT 2
-#define BCHP_CLKGEN_MEMSYS_32_WRAPPER_1_INST_CLOCK_ENABLE_MEMSYS1_SCB_CLOCK_ENABLE_DEFAULT 0x00000001
-
-/* CLKGEN :: MEMSYS_32_WRAPPER_1_INST_CLOCK_ENABLE :: MEMSYS1_GISB_CLOCK_ENABLE [01:01] */
-#define BCHP_CLKGEN_MEMSYS_32_WRAPPER_1_INST_CLOCK_ENABLE_MEMSYS1_GISB_CLOCK_ENABLE_MASK 0x00000002
-#define BCHP_CLKGEN_MEMSYS_32_WRAPPER_1_INST_CLOCK_ENABLE_MEMSYS1_GISB_CLOCK_ENABLE_SHIFT 1
-#define BCHP_CLKGEN_MEMSYS_32_WRAPPER_1_INST_CLOCK_ENABLE_MEMSYS1_GISB_CLOCK_ENABLE_DEFAULT 0x00000001
-
-/* CLKGEN :: MEMSYS_32_WRAPPER_1_INST_CLOCK_ENABLE :: MEMSYS1_54_CLOCK_ENABLE [00:00] */
-#define BCHP_CLKGEN_MEMSYS_32_WRAPPER_1_INST_CLOCK_ENABLE_MEMSYS1_54_CLOCK_ENABLE_MASK 0x00000001
-#define BCHP_CLKGEN_MEMSYS_32_WRAPPER_1_INST_CLOCK_ENABLE_MEMSYS1_54_CLOCK_ENABLE_SHIFT 0
-#define BCHP_CLKGEN_MEMSYS_32_WRAPPER_1_INST_CLOCK_ENABLE_MEMSYS1_54_CLOCK_ENABLE_DEFAULT 0x00000001
-
-/***************************************************************************
- *MEMSYS_32_WRAPPER_1_INST_CLOCK_ENABLE_STATUS - Clock Enable Status
- ***************************************************************************/
-/* CLKGEN :: MEMSYS_32_WRAPPER_1_INST_CLOCK_ENABLE_STATUS :: reserved0 [31:03] */
-#define BCHP_CLKGEN_MEMSYS_32_WRAPPER_1_INST_CLOCK_ENABLE_STATUS_reserved0_MASK 0xfffffff8
-#define BCHP_CLKGEN_MEMSYS_32_WRAPPER_1_INST_CLOCK_ENABLE_STATUS_reserved0_SHIFT 3
-
-/* CLKGEN :: MEMSYS_32_WRAPPER_1_INST_CLOCK_ENABLE_STATUS :: MEMSYS1_SCB_CLOCK_ENABLE_STATUS [02:02] */
-#define BCHP_CLKGEN_MEMSYS_32_WRAPPER_1_INST_CLOCK_ENABLE_STATUS_MEMSYS1_SCB_CLOCK_ENABLE_STATUS_MASK 0x00000004
-#define BCHP_CLKGEN_MEMSYS_32_WRAPPER_1_INST_CLOCK_ENABLE_STATUS_MEMSYS1_SCB_CLOCK_ENABLE_STATUS_SHIFT 2
-
-/* CLKGEN :: MEMSYS_32_WRAPPER_1_INST_CLOCK_ENABLE_STATUS :: MEMSYS1_GISB_CLOCK_ENABLE_STATUS [01:01] */
-#define BCHP_CLKGEN_MEMSYS_32_WRAPPER_1_INST_CLOCK_ENABLE_STATUS_MEMSYS1_GISB_CLOCK_ENABLE_STATUS_MASK 0x00000002
-#define BCHP_CLKGEN_MEMSYS_32_WRAPPER_1_INST_CLOCK_ENABLE_STATUS_MEMSYS1_GISB_CLOCK_ENABLE_STATUS_SHIFT 1
-
-/* CLKGEN :: MEMSYS_32_WRAPPER_1_INST_CLOCK_ENABLE_STATUS :: MEMSYS1_54_CLOCK_ENABLE_STATUS [00:00] */
-#define BCHP_CLKGEN_MEMSYS_32_WRAPPER_1_INST_CLOCK_ENABLE_STATUS_MEMSYS1_54_CLOCK_ENABLE_STATUS_MASK 0x00000001
-#define BCHP_CLKGEN_MEMSYS_32_WRAPPER_1_INST_CLOCK_ENABLE_STATUS_MEMSYS1_54_CLOCK_ENABLE_STATUS_SHIFT 0
-
-/***************************************************************************
- *MEMSYS_32_WRAPPER_1_INST_OBSERVE_CLOCK - Memsys 32 wrapper 1 inst observe clock
- ***************************************************************************/
-/* CLKGEN :: MEMSYS_32_WRAPPER_1_INST_OBSERVE_CLOCK :: reserved0 [31:06] */
-#define BCHP_CLKGEN_MEMSYS_32_WRAPPER_1_INST_OBSERVE_CLOCK_reserved0_MASK 0xffffffc0
-#define BCHP_CLKGEN_MEMSYS_32_WRAPPER_1_INST_OBSERVE_CLOCK_reserved0_SHIFT 6
-
-/* CLKGEN :: MEMSYS_32_WRAPPER_1_INST_OBSERVE_CLOCK :: MEMSYS1_ENABLE_OBSERVE_CLOCK [05:05] */
-#define BCHP_CLKGEN_MEMSYS_32_WRAPPER_1_INST_OBSERVE_CLOCK_MEMSYS1_ENABLE_OBSERVE_CLOCK_MASK 0x00000020
-#define BCHP_CLKGEN_MEMSYS_32_WRAPPER_1_INST_OBSERVE_CLOCK_MEMSYS1_ENABLE_OBSERVE_CLOCK_SHIFT 5
-#define BCHP_CLKGEN_MEMSYS_32_WRAPPER_1_INST_OBSERVE_CLOCK_MEMSYS1_ENABLE_OBSERVE_CLOCK_DEFAULT 0x00000000
-
-/* CLKGEN :: MEMSYS_32_WRAPPER_1_INST_OBSERVE_CLOCK :: MEMSYS1_ENABLE_DIVIDER_OBSERVE_CLOCK [04:04] */
-#define BCHP_CLKGEN_MEMSYS_32_WRAPPER_1_INST_OBSERVE_CLOCK_MEMSYS1_ENABLE_DIVIDER_OBSERVE_CLOCK_MASK 0x00000010
-#define BCHP_CLKGEN_MEMSYS_32_WRAPPER_1_INST_OBSERVE_CLOCK_MEMSYS1_ENABLE_DIVIDER_OBSERVE_CLOCK_SHIFT 4
-#define BCHP_CLKGEN_MEMSYS_32_WRAPPER_1_INST_OBSERVE_CLOCK_MEMSYS1_ENABLE_DIVIDER_OBSERVE_CLOCK_DEFAULT 0x00000000
-
-/* CLKGEN :: MEMSYS_32_WRAPPER_1_INST_OBSERVE_CLOCK :: MEMSYS1_CONTROL_OBSERVE_CLOCK [03:00] */
-#define BCHP_CLKGEN_MEMSYS_32_WRAPPER_1_INST_OBSERVE_CLOCK_MEMSYS1_CONTROL_OBSERVE_CLOCK_MASK 0x0000000f
-#define BCHP_CLKGEN_MEMSYS_32_WRAPPER_1_INST_OBSERVE_CLOCK_MEMSYS1_CONTROL_OBSERVE_CLOCK_SHIFT 0
-#define BCHP_CLKGEN_MEMSYS_32_WRAPPER_1_INST_OBSERVE_CLOCK_MEMSYS1_CONTROL_OBSERVE_CLOCK_DEFAULT 0x00000000
-
-/***************************************************************************
- *MEMSYS_32_WRAPPER_1_INST_STATUS - Memsys 32 wrapper 1 inst status
- ***************************************************************************/
-/* CLKGEN :: MEMSYS_32_WRAPPER_1_INST_STATUS :: reserved0 [31:01] */
-#define BCHP_CLKGEN_MEMSYS_32_WRAPPER_1_INST_STATUS_reserved0_MASK 0xfffffffe
-#define BCHP_CLKGEN_MEMSYS_32_WRAPPER_1_INST_STATUS_reserved0_SHIFT 1
-
-/* CLKGEN :: MEMSYS_32_WRAPPER_1_INST_STATUS :: MEMSYS1_PLL_LOCKED_STATUS [00:00] */
-#define BCHP_CLKGEN_MEMSYS_32_WRAPPER_1_INST_STATUS_MEMSYS1_PLL_LOCKED_STATUS_MASK 0x00000001
-#define BCHP_CLKGEN_MEMSYS_32_WRAPPER_1_INST_STATUS_MEMSYS1_PLL_LOCKED_STATUS_SHIFT 0
-
-/***************************************************************************
- *MOCAMAC_TOP_INST_CLOCK_ENABLE - Mocamac top inst clock enable
- ***************************************************************************/
-/* CLKGEN :: MOCAMAC_TOP_INST_CLOCK_ENABLE :: reserved0 [31:03] */
-#define BCHP_CLKGEN_MOCAMAC_TOP_INST_CLOCK_ENABLE_reserved0_MASK 0xfffffff8
-#define BCHP_CLKGEN_MOCAMAC_TOP_INST_CLOCK_ENABLE_reserved0_SHIFT 3
-
-/* CLKGEN :: MOCAMAC_TOP_INST_CLOCK_ENABLE :: MOCAMAC_SCB_CLOCK_ENABLE [02:02] */
-#define BCHP_CLKGEN_MOCAMAC_TOP_INST_CLOCK_ENABLE_MOCAMAC_SCB_CLOCK_ENABLE_MASK 0x00000004
-#define BCHP_CLKGEN_MOCAMAC_TOP_INST_CLOCK_ENABLE_MOCAMAC_SCB_CLOCK_ENABLE_SHIFT 2
-#define BCHP_CLKGEN_MOCAMAC_TOP_INST_CLOCK_ENABLE_MOCAMAC_SCB_CLOCK_ENABLE_DEFAULT 0x00000001
-
-/* CLKGEN :: MOCAMAC_TOP_INST_CLOCK_ENABLE :: MOCAMAC_GISB_CLOCK_ENABLE [01:01] */
-#define BCHP_CLKGEN_MOCAMAC_TOP_INST_CLOCK_ENABLE_MOCAMAC_GISB_CLOCK_ENABLE_MASK 0x00000002
-#define BCHP_CLKGEN_MOCAMAC_TOP_INST_CLOCK_ENABLE_MOCAMAC_GISB_CLOCK_ENABLE_SHIFT 1
-#define BCHP_CLKGEN_MOCAMAC_TOP_INST_CLOCK_ENABLE_MOCAMAC_GISB_CLOCK_ENABLE_DEFAULT 0x00000001
-
-/* CLKGEN :: MOCAMAC_TOP_INST_CLOCK_ENABLE :: MOCAMAC_54_CLOCK_ENABLE [00:00] */
-#define BCHP_CLKGEN_MOCAMAC_TOP_INST_CLOCK_ENABLE_MOCAMAC_54_CLOCK_ENABLE_MASK 0x00000001
-#define BCHP_CLKGEN_MOCAMAC_TOP_INST_CLOCK_ENABLE_MOCAMAC_54_CLOCK_ENABLE_SHIFT 0
-#define BCHP_CLKGEN_MOCAMAC_TOP_INST_CLOCK_ENABLE_MOCAMAC_54_CLOCK_ENABLE_DEFAULT 0x00000001
-
-/***************************************************************************
- *MOCAMAC_TOP_INST_CLOCK_ENABLE_STATUS - Clock Enable Status
- ***************************************************************************/
-/* CLKGEN :: MOCAMAC_TOP_INST_CLOCK_ENABLE_STATUS :: reserved0 [31:03] */
-#define BCHP_CLKGEN_MOCAMAC_TOP_INST_CLOCK_ENABLE_STATUS_reserved0_MASK 0xfffffff8
-#define BCHP_CLKGEN_MOCAMAC_TOP_INST_CLOCK_ENABLE_STATUS_reserved0_SHIFT 3
-
-/* CLKGEN :: MOCAMAC_TOP_INST_CLOCK_ENABLE_STATUS :: MOCAMAC_SCB_CLOCK_ENABLE_STATUS [02:02] */
-#define BCHP_CLKGEN_MOCAMAC_TOP_INST_CLOCK_ENABLE_STATUS_MOCAMAC_SCB_CLOCK_ENABLE_STATUS_MASK 0x00000004
-#define BCHP_CLKGEN_MOCAMAC_TOP_INST_CLOCK_ENABLE_STATUS_MOCAMAC_SCB_CLOCK_ENABLE_STATUS_SHIFT 2
-
-/* CLKGEN :: MOCAMAC_TOP_INST_CLOCK_ENABLE_STATUS :: MOCAMAC_GISB_CLOCK_ENABLE_STATUS [01:01] */
-#define BCHP_CLKGEN_MOCAMAC_TOP_INST_CLOCK_ENABLE_STATUS_MOCAMAC_GISB_CLOCK_ENABLE_STATUS_MASK 0x00000002
-#define BCHP_CLKGEN_MOCAMAC_TOP_INST_CLOCK_ENABLE_STATUS_MOCAMAC_GISB_CLOCK_ENABLE_STATUS_SHIFT 1
-
-/* CLKGEN :: MOCAMAC_TOP_INST_CLOCK_ENABLE_STATUS :: MOCAMAC_54_CLOCK_ENABLE_STATUS [00:00] */
-#define BCHP_CLKGEN_MOCAMAC_TOP_INST_CLOCK_ENABLE_STATUS_MOCAMAC_54_CLOCK_ENABLE_STATUS_MASK 0x00000001
-#define BCHP_CLKGEN_MOCAMAC_TOP_INST_CLOCK_ENABLE_STATUS_MOCAMAC_54_CLOCK_ENABLE_STATUS_SHIFT 0
-
-/***************************************************************************
- *MOCAMAC_TOP_INST_OBSERVE_CLOCK - Mocamac top inst observe clock
- ***************************************************************************/
-/* CLKGEN :: MOCAMAC_TOP_INST_OBSERVE_CLOCK :: reserved0 [31:06] */
-#define BCHP_CLKGEN_MOCAMAC_TOP_INST_OBSERVE_CLOCK_reserved0_MASK 0xffffffc0
-#define BCHP_CLKGEN_MOCAMAC_TOP_INST_OBSERVE_CLOCK_reserved0_SHIFT 6
-
-/* CLKGEN :: MOCAMAC_TOP_INST_OBSERVE_CLOCK :: MOCAMAC_ENABLE_OBSERVE_CLOCK [05:05] */
-#define BCHP_CLKGEN_MOCAMAC_TOP_INST_OBSERVE_CLOCK_MOCAMAC_ENABLE_OBSERVE_CLOCK_MASK 0x00000020
-#define BCHP_CLKGEN_MOCAMAC_TOP_INST_OBSERVE_CLOCK_MOCAMAC_ENABLE_OBSERVE_CLOCK_SHIFT 5
-#define BCHP_CLKGEN_MOCAMAC_TOP_INST_OBSERVE_CLOCK_MOCAMAC_ENABLE_OBSERVE_CLOCK_DEFAULT 0x00000000
-
-/* CLKGEN :: MOCAMAC_TOP_INST_OBSERVE_CLOCK :: MOCAMAC_ENABLE_DIVIDER_OBSERVE_CLOCK [04:04] */
-#define BCHP_CLKGEN_MOCAMAC_TOP_INST_OBSERVE_CLOCK_MOCAMAC_ENABLE_DIVIDER_OBSERVE_CLOCK_MASK 0x00000010
-#define BCHP_CLKGEN_MOCAMAC_TOP_INST_OBSERVE_CLOCK_MOCAMAC_ENABLE_DIVIDER_OBSERVE_CLOCK_SHIFT 4
-#define BCHP_CLKGEN_MOCAMAC_TOP_INST_OBSERVE_CLOCK_MOCAMAC_ENABLE_DIVIDER_OBSERVE_CLOCK_DEFAULT 0x00000000
-
-/* CLKGEN :: MOCAMAC_TOP_INST_OBSERVE_CLOCK :: MOCAMAC_CONTROL_OBSERVE_CLOCK [03:00] */
-#define BCHP_CLKGEN_MOCAMAC_TOP_INST_OBSERVE_CLOCK_MOCAMAC_CONTROL_OBSERVE_CLOCK_MASK 0x0000000f
-#define BCHP_CLKGEN_MOCAMAC_TOP_INST_OBSERVE_CLOCK_MOCAMAC_CONTROL_OBSERVE_CLOCK_SHIFT 0
-#define BCHP_CLKGEN_MOCAMAC_TOP_INST_OBSERVE_CLOCK_MOCAMAC_CONTROL_OBSERVE_CLOCK_DEFAULT 0x00000000
-
-/***************************************************************************
- *MOCAPHY_TOP_INST_CLOCK_ENABLE - Mocaphy top inst clock enable
- ***************************************************************************/
-/* CLKGEN :: MOCAPHY_TOP_INST_CLOCK_ENABLE :: reserved0 [31:02] */
-#define BCHP_CLKGEN_MOCAPHY_TOP_INST_CLOCK_ENABLE_reserved0_MASK 0xfffffffc
-#define BCHP_CLKGEN_MOCAPHY_TOP_INST_CLOCK_ENABLE_reserved0_SHIFT 2
-
-/* CLKGEN :: MOCAPHY_TOP_INST_CLOCK_ENABLE :: MOCAPHY_GISB_CLOCK_ENABLE [01:01] */
-#define BCHP_CLKGEN_MOCAPHY_TOP_INST_CLOCK_ENABLE_MOCAPHY_GISB_CLOCK_ENABLE_MASK 0x00000002
-#define BCHP_CLKGEN_MOCAPHY_TOP_INST_CLOCK_ENABLE_MOCAPHY_GISB_CLOCK_ENABLE_SHIFT 1
-#define BCHP_CLKGEN_MOCAPHY_TOP_INST_CLOCK_ENABLE_MOCAPHY_GISB_CLOCK_ENABLE_DEFAULT 0x00000001
-
-/* CLKGEN :: MOCAPHY_TOP_INST_CLOCK_ENABLE :: MOCAPHY_54_CLOCK_ENABLE [00:00] */
-#define BCHP_CLKGEN_MOCAPHY_TOP_INST_CLOCK_ENABLE_MOCAPHY_54_CLOCK_ENABLE_MASK 0x00000001
-#define BCHP_CLKGEN_MOCAPHY_TOP_INST_CLOCK_ENABLE_MOCAPHY_54_CLOCK_ENABLE_SHIFT 0
-#define BCHP_CLKGEN_MOCAPHY_TOP_INST_CLOCK_ENABLE_MOCAPHY_54_CLOCK_ENABLE_DEFAULT 0x00000001
-
-/***************************************************************************
- *MOCAPHY_TOP_INST_CLOCK_ENABLE_STATUS - Clock Enable Status
- ***************************************************************************/
-/* CLKGEN :: MOCAPHY_TOP_INST_CLOCK_ENABLE_STATUS :: reserved0 [31:02] */
-#define BCHP_CLKGEN_MOCAPHY_TOP_INST_CLOCK_ENABLE_STATUS_reserved0_MASK 0xfffffffc
-#define BCHP_CLKGEN_MOCAPHY_TOP_INST_CLOCK_ENABLE_STATUS_reserved0_SHIFT 2
-
-/* CLKGEN :: MOCAPHY_TOP_INST_CLOCK_ENABLE_STATUS :: MOCAPHY_GISB_CLOCK_ENABLE_STATUS [01:01] */
-#define BCHP_CLKGEN_MOCAPHY_TOP_INST_CLOCK_ENABLE_STATUS_MOCAPHY_GISB_CLOCK_ENABLE_STATUS_MASK 0x00000002
-#define BCHP_CLKGEN_MOCAPHY_TOP_INST_CLOCK_ENABLE_STATUS_MOCAPHY_GISB_CLOCK_ENABLE_STATUS_SHIFT 1
-
-/* CLKGEN :: MOCAPHY_TOP_INST_CLOCK_ENABLE_STATUS :: MOCAPHY_54_CLOCK_ENABLE_STATUS [00:00] */
-#define BCHP_CLKGEN_MOCAPHY_TOP_INST_CLOCK_ENABLE_STATUS_MOCAPHY_54_CLOCK_ENABLE_STATUS_MASK 0x00000001
-#define BCHP_CLKGEN_MOCAPHY_TOP_INST_CLOCK_ENABLE_STATUS_MOCAPHY_54_CLOCK_ENABLE_STATUS_SHIFT 0
-
-/***************************************************************************
- *MOCAPHY_TOP_INST_OBSERVE_CLOCK - Mocaphy top inst observe clock
- ***************************************************************************/
-/* CLKGEN :: MOCAPHY_TOP_INST_OBSERVE_CLOCK :: reserved0 [31:06] */
-#define BCHP_CLKGEN_MOCAPHY_TOP_INST_OBSERVE_CLOCK_reserved0_MASK 0xffffffc0
-#define BCHP_CLKGEN_MOCAPHY_TOP_INST_OBSERVE_CLOCK_reserved0_SHIFT 6
-
-/* CLKGEN :: MOCAPHY_TOP_INST_OBSERVE_CLOCK :: MOCAPHY_ENABLE_OBSERVE_CLOCK [05:05] */
-#define BCHP_CLKGEN_MOCAPHY_TOP_INST_OBSERVE_CLOCK_MOCAPHY_ENABLE_OBSERVE_CLOCK_MASK 0x00000020
-#define BCHP_CLKGEN_MOCAPHY_TOP_INST_OBSERVE_CLOCK_MOCAPHY_ENABLE_OBSERVE_CLOCK_SHIFT 5
-#define BCHP_CLKGEN_MOCAPHY_TOP_INST_OBSERVE_CLOCK_MOCAPHY_ENABLE_OBSERVE_CLOCK_DEFAULT 0x00000000
-
-/* CLKGEN :: MOCAPHY_TOP_INST_OBSERVE_CLOCK :: MOCAPHY_ENABLE_DIVIDER_OBSERVE_CLOCK [04:04] */
-#define BCHP_CLKGEN_MOCAPHY_TOP_INST_OBSERVE_CLOCK_MOCAPHY_ENABLE_DIVIDER_OBSERVE_CLOCK_MASK 0x00000010
-#define BCHP_CLKGEN_MOCAPHY_TOP_INST_OBSERVE_CLOCK_MOCAPHY_ENABLE_DIVIDER_OBSERVE_CLOCK_SHIFT 4
-#define BCHP_CLKGEN_MOCAPHY_TOP_INST_OBSERVE_CLOCK_MOCAPHY_ENABLE_DIVIDER_OBSERVE_CLOCK_DEFAULT 0x00000000
-
-/* CLKGEN :: MOCAPHY_TOP_INST_OBSERVE_CLOCK :: MOCAPHY_CONTROL_OBSERVE_CLOCK [03:00] */
-#define BCHP_CLKGEN_MOCAPHY_TOP_INST_OBSERVE_CLOCK_MOCAPHY_CONTROL_OBSERVE_CLOCK_MASK 0x0000000f
-#define BCHP_CLKGEN_MOCAPHY_TOP_INST_OBSERVE_CLOCK_MOCAPHY_CONTROL_OBSERVE_CLOCK_SHIFT 0
-#define BCHP_CLKGEN_MOCAPHY_TOP_INST_OBSERVE_CLOCK_MOCAPHY_CONTROL_OBSERVE_CLOCK_DEFAULT 0x00000000
-
-/***************************************************************************
- *MULTI_CLOCK_DISABLE - Disable MULTI's clocks
- ***************************************************************************/
-/* CLKGEN :: MULTI_CLOCK_DISABLE :: reserved0 [31:07] */
-#define BCHP_CLKGEN_MULTI_CLOCK_DISABLE_reserved0_MASK 0xffffff80
-#define BCHP_CLKGEN_MULTI_CLOCK_DISABLE_reserved0_SHIFT 7
-
-/* CLKGEN :: MULTI_CLOCK_DISABLE :: DISABLE_US_54_CLOCK [06:06] */
-#define BCHP_CLKGEN_MULTI_CLOCK_DISABLE_DISABLE_US_54_CLOCK_MASK 0x00000040
-#define BCHP_CLKGEN_MULTI_CLOCK_DISABLE_DISABLE_US_54_CLOCK_SHIFT 6
-#define BCHP_CLKGEN_MULTI_CLOCK_DISABLE_DISABLE_US_54_CLOCK_DEFAULT 0x00000000
-
-/* CLKGEN :: MULTI_CLOCK_DISABLE :: DISABLE_DOS_SYSTEM_UCB_DI_CLOCK [05:05] */
-#define BCHP_CLKGEN_MULTI_CLOCK_DISABLE_DISABLE_DOS_SYSTEM_UCB_DI_CLOCK_MASK 0x00000020
-#define BCHP_CLKGEN_MULTI_CLOCK_DISABLE_DISABLE_DOS_SYSTEM_UCB_DI_CLOCK_SHIFT 5
-#define BCHP_CLKGEN_MULTI_CLOCK_DISABLE_DISABLE_DOS_SYSTEM_UCB_DI_CLOCK_DEFAULT 0x00000000
-
-/* CLKGEN :: MULTI_CLOCK_DISABLE :: DISABLE_DOS_SYSTEM_UCB_CLOCK [04:04] */
-#define BCHP_CLKGEN_MULTI_CLOCK_DISABLE_DISABLE_DOS_SYSTEM_UCB_CLOCK_MASK 0x00000010
-#define BCHP_CLKGEN_MULTI_CLOCK_DISABLE_DISABLE_DOS_SYSTEM_UCB_CLOCK_SHIFT 4
-#define BCHP_CLKGEN_MULTI_CLOCK_DISABLE_DISABLE_DOS_SYSTEM_UCB_CLOCK_DEFAULT 0x00000000
-
-/* CLKGEN :: MULTI_CLOCK_DISABLE :: DISABLE_DOS_SYSTEM_TP_CLOCK [03:03] */
-#define BCHP_CLKGEN_MULTI_CLOCK_DISABLE_DISABLE_DOS_SYSTEM_TP_CLOCK_MASK 0x00000008
-#define BCHP_CLKGEN_MULTI_CLOCK_DISABLE_DISABLE_DOS_SYSTEM_TP_CLOCK_SHIFT 3
-#define BCHP_CLKGEN_MULTI_CLOCK_DISABLE_DISABLE_DOS_SYSTEM_TP_CLOCK_DEFAULT 0x00000000
-
-/* CLKGEN :: MULTI_CLOCK_DISABLE :: DISABLE_DOS_SYSTEM_SMISB_CLOCK [02:02] */
-#define BCHP_CLKGEN_MULTI_CLOCK_DISABLE_DISABLE_DOS_SYSTEM_SMISB_CLOCK_MASK 0x00000004
-#define BCHP_CLKGEN_MULTI_CLOCK_DISABLE_DISABLE_DOS_SYSTEM_SMISB_CLOCK_SHIFT 2
-#define BCHP_CLKGEN_MULTI_CLOCK_DISABLE_DISABLE_DOS_SYSTEM_SMISB_CLOCK_DEFAULT 0x00000000
-
-/* CLKGEN :: MULTI_CLOCK_DISABLE :: DISABLE_DOS_SYSTEM_REQ_CLOCK [01:01] */
-#define BCHP_CLKGEN_MULTI_CLOCK_DISABLE_DISABLE_DOS_SYSTEM_REQ_CLOCK_MASK 0x00000002
-#define BCHP_CLKGEN_MULTI_CLOCK_DISABLE_DISABLE_DOS_SYSTEM_REQ_CLOCK_SHIFT 1
-#define BCHP_CLKGEN_MULTI_CLOCK_DISABLE_DISABLE_DOS_SYSTEM_REQ_CLOCK_DEFAULT 0x00000000
-
-/* CLKGEN :: MULTI_CLOCK_DISABLE :: DISABLE_DOS_SYSTEM_BPCM_CLOCK [00:00] */
-#define BCHP_CLKGEN_MULTI_CLOCK_DISABLE_DISABLE_DOS_SYSTEM_BPCM_CLOCK_MASK 0x00000001
-#define BCHP_CLKGEN_MULTI_CLOCK_DISABLE_DISABLE_DOS_SYSTEM_BPCM_CLOCK_SHIFT 0
-#define BCHP_CLKGEN_MULTI_CLOCK_DISABLE_DISABLE_DOS_SYSTEM_BPCM_CLOCK_DEFAULT 0x00000000
-
-/***************************************************************************
- *MULTI_CLOCK_DISABLE_STATUS - Clock Disable Status
- ***************************************************************************/
-/* CLKGEN :: MULTI_CLOCK_DISABLE_STATUS :: reserved0 [31:07] */
-#define BCHP_CLKGEN_MULTI_CLOCK_DISABLE_STATUS_reserved0_MASK 0xffffff80
-#define BCHP_CLKGEN_MULTI_CLOCK_DISABLE_STATUS_reserved0_SHIFT 7
-
-/* CLKGEN :: MULTI_CLOCK_DISABLE_STATUS :: DISABLE_US_54_CLOCK_STATUS [06:06] */
-#define BCHP_CLKGEN_MULTI_CLOCK_DISABLE_STATUS_DISABLE_US_54_CLOCK_STATUS_MASK 0x00000040
-#define BCHP_CLKGEN_MULTI_CLOCK_DISABLE_STATUS_DISABLE_US_54_CLOCK_STATUS_SHIFT 6
-
-/* CLKGEN :: MULTI_CLOCK_DISABLE_STATUS :: DISABLE_DOS_SYSTEM_UCB_DI_CLOCK_STATUS [05:05] */
-#define BCHP_CLKGEN_MULTI_CLOCK_DISABLE_STATUS_DISABLE_DOS_SYSTEM_UCB_DI_CLOCK_STATUS_MASK 0x00000020
-#define BCHP_CLKGEN_MULTI_CLOCK_DISABLE_STATUS_DISABLE_DOS_SYSTEM_UCB_DI_CLOCK_STATUS_SHIFT 5
-
-/* CLKGEN :: MULTI_CLOCK_DISABLE_STATUS :: DISABLE_DOS_SYSTEM_UCB_CLOCK_STATUS [04:04] */
-#define BCHP_CLKGEN_MULTI_CLOCK_DISABLE_STATUS_DISABLE_DOS_SYSTEM_UCB_CLOCK_STATUS_MASK 0x00000010
-#define BCHP_CLKGEN_MULTI_CLOCK_DISABLE_STATUS_DISABLE_DOS_SYSTEM_UCB_CLOCK_STATUS_SHIFT 4
-
-/* CLKGEN :: MULTI_CLOCK_DISABLE_STATUS :: DISABLE_DOS_SYSTEM_TP_CLOCK_STATUS [03:03] */
-#define BCHP_CLKGEN_MULTI_CLOCK_DISABLE_STATUS_DISABLE_DOS_SYSTEM_TP_CLOCK_STATUS_MASK 0x00000008
-#define BCHP_CLKGEN_MULTI_CLOCK_DISABLE_STATUS_DISABLE_DOS_SYSTEM_TP_CLOCK_STATUS_SHIFT 3
-
-/* CLKGEN :: MULTI_CLOCK_DISABLE_STATUS :: DISABLE_DOS_SYSTEM_SMISB_CLOCK_STATUS [02:02] */
-#define BCHP_CLKGEN_MULTI_CLOCK_DISABLE_STATUS_DISABLE_DOS_SYSTEM_SMISB_CLOCK_STATUS_MASK 0x00000004
-#define BCHP_CLKGEN_MULTI_CLOCK_DISABLE_STATUS_DISABLE_DOS_SYSTEM_SMISB_CLOCK_STATUS_SHIFT 2
-
-/* CLKGEN :: MULTI_CLOCK_DISABLE_STATUS :: DISABLE_DOS_SYSTEM_REQ_CLOCK_STATUS [01:01] */
-#define BCHP_CLKGEN_MULTI_CLOCK_DISABLE_STATUS_DISABLE_DOS_SYSTEM_REQ_CLOCK_STATUS_MASK 0x00000002
-#define BCHP_CLKGEN_MULTI_CLOCK_DISABLE_STATUS_DISABLE_DOS_SYSTEM_REQ_CLOCK_STATUS_SHIFT 1
-
-/* CLKGEN :: MULTI_CLOCK_DISABLE_STATUS :: DISABLE_DOS_SYSTEM_BPCM_CLOCK_STATUS [00:00] */
-#define BCHP_CLKGEN_MULTI_CLOCK_DISABLE_STATUS_DISABLE_DOS_SYSTEM_BPCM_CLOCK_STATUS_MASK 0x00000001
-#define BCHP_CLKGEN_MULTI_CLOCK_DISABLE_STATUS_DISABLE_DOS_SYSTEM_BPCM_CLOCK_STATUS_SHIFT 0
-
-/***************************************************************************
- *PAD_CLK_OUT0_OBSERVATION - Select observation clk
- ***************************************************************************/
-/* CLKGEN :: PAD_CLK_OUT0_OBSERVATION :: reserved0 [31:09] */
-#define BCHP_CLKGEN_PAD_CLK_OUT0_OBSERVATION_reserved0_MASK 0xfffffe00
-#define BCHP_CLKGEN_PAD_CLK_OUT0_OBSERVATION_reserved0_SHIFT 9
-
-/* CLKGEN :: PAD_CLK_OUT0_OBSERVATION :: SELECT_OBSERVE_CLK [08:08] */
-#define BCHP_CLKGEN_PAD_CLK_OUT0_OBSERVATION_SELECT_OBSERVE_CLK_MASK 0x00000100
-#define BCHP_CLKGEN_PAD_CLK_OUT0_OBSERVATION_SELECT_OBSERVE_CLK_SHIFT 8
-#define BCHP_CLKGEN_PAD_CLK_OUT0_OBSERVATION_SELECT_OBSERVE_CLK_DEFAULT 0x00000000
-
-/* CLKGEN :: PAD_CLK_OUT0_OBSERVATION :: OBSERVE_MUX_SELECT [07:01] */
-#define BCHP_CLKGEN_PAD_CLK_OUT0_OBSERVATION_OBSERVE_MUX_SELECT_MASK 0x000000fe
-#define BCHP_CLKGEN_PAD_CLK_OUT0_OBSERVATION_OBSERVE_MUX_SELECT_SHIFT 1
-#define BCHP_CLKGEN_PAD_CLK_OUT0_OBSERVATION_OBSERVE_MUX_SELECT_DEFAULT 0x00000000
-
-/* CLKGEN :: PAD_CLK_OUT0_OBSERVATION :: OBSERVE_DIV_ENABLE [00:00] */
-#define BCHP_CLKGEN_PAD_CLK_OUT0_OBSERVATION_OBSERVE_DIV_ENABLE_MASK 0x00000001
-#define BCHP_CLKGEN_PAD_CLK_OUT0_OBSERVATION_OBSERVE_DIV_ENABLE_SHIFT 0
-#define BCHP_CLKGEN_PAD_CLK_OUT0_OBSERVATION_OBSERVE_DIV_ENABLE_DEFAULT 0x00000000
-
-/***************************************************************************
- *PAD_CLK_OUT1_OBSERVATION - Select observation clk
- ***************************************************************************/
-/* CLKGEN :: PAD_CLK_OUT1_OBSERVATION :: reserved0 [31:09] */
-#define BCHP_CLKGEN_PAD_CLK_OUT1_OBSERVATION_reserved0_MASK 0xfffffe00
-#define BCHP_CLKGEN_PAD_CLK_OUT1_OBSERVATION_reserved0_SHIFT 9
-
-/* CLKGEN :: PAD_CLK_OUT1_OBSERVATION :: SELECT_OBSERVE_CLK [08:08] */
-#define BCHP_CLKGEN_PAD_CLK_OUT1_OBSERVATION_SELECT_OBSERVE_CLK_MASK 0x00000100
-#define BCHP_CLKGEN_PAD_CLK_OUT1_OBSERVATION_SELECT_OBSERVE_CLK_SHIFT 8
-#define BCHP_CLKGEN_PAD_CLK_OUT1_OBSERVATION_SELECT_OBSERVE_CLK_DEFAULT 0x00000000
-
-/* CLKGEN :: PAD_CLK_OUT1_OBSERVATION :: OBSERVE_MUX_SELECT [07:01] */
-#define BCHP_CLKGEN_PAD_CLK_OUT1_OBSERVATION_OBSERVE_MUX_SELECT_MASK 0x000000fe
-#define BCHP_CLKGEN_PAD_CLK_OUT1_OBSERVATION_OBSERVE_MUX_SELECT_SHIFT 1
-#define BCHP_CLKGEN_PAD_CLK_OUT1_OBSERVATION_OBSERVE_MUX_SELECT_DEFAULT 0x00000000
-
-/* CLKGEN :: PAD_CLK_OUT1_OBSERVATION :: OBSERVE_DIV_ENABLE [00:00] */
-#define BCHP_CLKGEN_PAD_CLK_OUT1_OBSERVATION_OBSERVE_DIV_ENABLE_MASK 0x00000001
-#define BCHP_CLKGEN_PAD_CLK_OUT1_OBSERVATION_OBSERVE_DIV_ENABLE_SHIFT 0
-#define BCHP_CLKGEN_PAD_CLK_OUT1_OBSERVATION_OBSERVE_DIV_ENABLE_DEFAULT 0x00000000
-
-/***************************************************************************
- *PAD_CLOCK_DISABLE - Disable PAD's clocks
- ***************************************************************************/
-/* CLKGEN :: PAD_CLOCK_DISABLE :: reserved0 [31:02] */
-#define BCHP_CLKGEN_PAD_CLOCK_DISABLE_reserved0_MASK 0xfffffffc
-#define BCHP_CLKGEN_PAD_CLOCK_DISABLE_reserved0_SHIFT 2
-
-/* CLKGEN :: PAD_CLOCK_DISABLE :: DISABLE_PAD_OUTPUT_CLK_OUT1_CLOCK [01:01] */
-#define BCHP_CLKGEN_PAD_CLOCK_DISABLE_DISABLE_PAD_OUTPUT_CLK_OUT1_CLOCK_MASK 0x00000002
-#define BCHP_CLKGEN_PAD_CLOCK_DISABLE_DISABLE_PAD_OUTPUT_CLK_OUT1_CLOCK_SHIFT 1
-#define BCHP_CLKGEN_PAD_CLOCK_DISABLE_DISABLE_PAD_OUTPUT_CLK_OUT1_CLOCK_DEFAULT 0x00000000
-
-/* CLKGEN :: PAD_CLOCK_DISABLE :: DISABLE_PAD_OUTPUT_CLK_OUT0_CLOCK [00:00] */
-#define BCHP_CLKGEN_PAD_CLOCK_DISABLE_DISABLE_PAD_OUTPUT_CLK_OUT0_CLOCK_MASK 0x00000001
-#define BCHP_CLKGEN_PAD_CLOCK_DISABLE_DISABLE_PAD_OUTPUT_CLK_OUT0_CLOCK_SHIFT 0
-#define BCHP_CLKGEN_PAD_CLOCK_DISABLE_DISABLE_PAD_OUTPUT_CLK_OUT0_CLOCK_DEFAULT 0x00000000
-
-/***************************************************************************
- *PAD_CLOCK_DISABLE_STATUS - Clock Disable Status
- ***************************************************************************/
-/* CLKGEN :: PAD_CLOCK_DISABLE_STATUS :: reserved0 [31:02] */
-#define BCHP_CLKGEN_PAD_CLOCK_DISABLE_STATUS_reserved0_MASK 0xfffffffc
-#define BCHP_CLKGEN_PAD_CLOCK_DISABLE_STATUS_reserved0_SHIFT 2
-
-/* CLKGEN :: PAD_CLOCK_DISABLE_STATUS :: DISABLE_PAD_OUTPUT_CLK_OUT1_CLOCK_STATUS [01:01] */
-#define BCHP_CLKGEN_PAD_CLOCK_DISABLE_STATUS_DISABLE_PAD_OUTPUT_CLK_OUT1_CLOCK_STATUS_MASK 0x00000002
-#define BCHP_CLKGEN_PAD_CLOCK_DISABLE_STATUS_DISABLE_PAD_OUTPUT_CLK_OUT1_CLOCK_STATUS_SHIFT 1
-
-/* CLKGEN :: PAD_CLOCK_DISABLE_STATUS :: DISABLE_PAD_OUTPUT_CLK_OUT0_CLOCK_STATUS [00:00] */
-#define BCHP_CLKGEN_PAD_CLOCK_DISABLE_STATUS_DISABLE_PAD_OUTPUT_CLK_OUT0_CLOCK_STATUS_MASK 0x00000001
-#define BCHP_CLKGEN_PAD_CLOCK_DISABLE_STATUS_DISABLE_PAD_OUTPUT_CLK_OUT0_CLOCK_STATUS_SHIFT 0
-
-/***************************************************************************
- *PAD_MUX_SELECT - Mux selects for Pad clocks
- ***************************************************************************/
-/* CLKGEN :: PAD_MUX_SELECT :: reserved0 [31:03] */
-#define BCHP_CLKGEN_PAD_MUX_SELECT_reserved0_MASK 0xfffffff8
-#define BCHP_CLKGEN_PAD_MUX_SELECT_reserved0_SHIFT 3
-
-/* CLKGEN :: PAD_MUX_SELECT :: PAD_OUTPUT_SC_CLOCK [02:02] */
-#define BCHP_CLKGEN_PAD_MUX_SELECT_PAD_OUTPUT_SC_CLOCK_MASK 0x00000004
-#define BCHP_CLKGEN_PAD_MUX_SELECT_PAD_OUTPUT_SC_CLOCK_SHIFT 2
-#define BCHP_CLKGEN_PAD_MUX_SELECT_PAD_OUTPUT_SC_CLOCK_DEFAULT 0x00000000
-
-/* CLKGEN :: PAD_MUX_SELECT :: PAD_OUTPUT_CLK_OUT1_CLOCK [01:01] */
-#define BCHP_CLKGEN_PAD_MUX_SELECT_PAD_OUTPUT_CLK_OUT1_CLOCK_MASK 0x00000002
-#define BCHP_CLKGEN_PAD_MUX_SELECT_PAD_OUTPUT_CLK_OUT1_CLOCK_SHIFT 1
-#define BCHP_CLKGEN_PAD_MUX_SELECT_PAD_OUTPUT_CLK_OUT1_CLOCK_DEFAULT 0x00000000
-
-/* CLKGEN :: PAD_MUX_SELECT :: PAD_OUTPUT_CLK_OUT0_CLOCK [00:00] */
-#define BCHP_CLKGEN_PAD_MUX_SELECT_PAD_OUTPUT_CLK_OUT0_CLOCK_MASK 0x00000001
-#define BCHP_CLKGEN_PAD_MUX_SELECT_PAD_OUTPUT_CLK_OUT0_CLOCK_SHIFT 0
-#define BCHP_CLKGEN_PAD_MUX_SELECT_PAD_OUTPUT_CLK_OUT0_CLOCK_DEFAULT 0x00000000
-
-/***************************************************************************
- *PCIE_X2_TOP_INST_CLOCK_DISABLE - Disable PCIE_X2_TOP_INST's clocks
- ***************************************************************************/
-/* CLKGEN :: PCIE_X2_TOP_INST_CLOCK_DISABLE :: reserved0 [31:01] */
-#define BCHP_CLKGEN_PCIE_X2_TOP_INST_CLOCK_DISABLE_reserved0_MASK 0xfffffffe
-#define BCHP_CLKGEN_PCIE_X2_TOP_INST_CLOCK_DISABLE_reserved0_SHIFT 1
-
-/* CLKGEN :: PCIE_X2_TOP_INST_CLOCK_DISABLE :: DISABLE_PCIE_ALWAYSON_CLOCK [00:00] */
-#define BCHP_CLKGEN_PCIE_X2_TOP_INST_CLOCK_DISABLE_DISABLE_PCIE_ALWAYSON_CLOCK_MASK 0x00000001
-#define BCHP_CLKGEN_PCIE_X2_TOP_INST_CLOCK_DISABLE_DISABLE_PCIE_ALWAYSON_CLOCK_SHIFT 0
-#define BCHP_CLKGEN_PCIE_X2_TOP_INST_CLOCK_DISABLE_DISABLE_PCIE_ALWAYSON_CLOCK_DEFAULT 0x00000000
-
-/***************************************************************************
- *PCIE_X2_TOP_INST_CLOCK_DISABLE_STATUS - Clock Disable Status
- ***************************************************************************/
-/* CLKGEN :: PCIE_X2_TOP_INST_CLOCK_DISABLE_STATUS :: reserved0 [31:01] */
-#define BCHP_CLKGEN_PCIE_X2_TOP_INST_CLOCK_DISABLE_STATUS_reserved0_MASK 0xfffffffe
-#define BCHP_CLKGEN_PCIE_X2_TOP_INST_CLOCK_DISABLE_STATUS_reserved0_SHIFT 1
-
-/* CLKGEN :: PCIE_X2_TOP_INST_CLOCK_DISABLE_STATUS :: DISABLE_PCIE_ALWAYSON_CLOCK_STATUS [00:00] */
-#define BCHP_CLKGEN_PCIE_X2_TOP_INST_CLOCK_DISABLE_STATUS_DISABLE_PCIE_ALWAYSON_CLOCK_STATUS_MASK 0x00000001
-#define BCHP_CLKGEN_PCIE_X2_TOP_INST_CLOCK_DISABLE_STATUS_DISABLE_PCIE_ALWAYSON_CLOCK_STATUS_SHIFT 0
-
-/***************************************************************************
- *PCIE_X2_TOP_INST_CLOCK_ENABLE - Pcie x2 top inst clock enable
- ***************************************************************************/
-/* CLKGEN :: PCIE_X2_TOP_INST_CLOCK_ENABLE :: reserved0 [31:04] */
-#define BCHP_CLKGEN_PCIE_X2_TOP_INST_CLOCK_ENABLE_reserved0_MASK 0xfffffff0
-#define BCHP_CLKGEN_PCIE_X2_TOP_INST_CLOCK_ENABLE_reserved0_SHIFT 4
-
-/* CLKGEN :: PCIE_X2_TOP_INST_CLOCK_ENABLE :: PCIE_SCB_CLOCK_ENABLE [03:03] */
-#define BCHP_CLKGEN_PCIE_X2_TOP_INST_CLOCK_ENABLE_PCIE_SCB_CLOCK_ENABLE_MASK 0x00000008
-#define BCHP_CLKGEN_PCIE_X2_TOP_INST_CLOCK_ENABLE_PCIE_SCB_CLOCK_ENABLE_SHIFT 3
-#define BCHP_CLKGEN_PCIE_X2_TOP_INST_CLOCK_ENABLE_PCIE_SCB_CLOCK_ENABLE_DEFAULT 0x00000001
-
-/* CLKGEN :: PCIE_X2_TOP_INST_CLOCK_ENABLE :: PCIE_GISB_CLOCK_ENABLE [02:02] */
-#define BCHP_CLKGEN_PCIE_X2_TOP_INST_CLOCK_ENABLE_PCIE_GISB_CLOCK_ENABLE_MASK 0x00000004
-#define BCHP_CLKGEN_PCIE_X2_TOP_INST_CLOCK_ENABLE_PCIE_GISB_CLOCK_ENABLE_SHIFT 2
-#define BCHP_CLKGEN_PCIE_X2_TOP_INST_CLOCK_ENABLE_PCIE_GISB_CLOCK_ENABLE_DEFAULT 0x00000001
-
-/* CLKGEN :: PCIE_X2_TOP_INST_CLOCK_ENABLE :: PCIE_54_CLOCK_ENABLE [01:01] */
-#define BCHP_CLKGEN_PCIE_X2_TOP_INST_CLOCK_ENABLE_PCIE_54_CLOCK_ENABLE_MASK 0x00000002
-#define BCHP_CLKGEN_PCIE_X2_TOP_INST_CLOCK_ENABLE_PCIE_54_CLOCK_ENABLE_SHIFT 1
-#define BCHP_CLKGEN_PCIE_X2_TOP_INST_CLOCK_ENABLE_PCIE_54_CLOCK_ENABLE_DEFAULT 0x00000001
-
-/* CLKGEN :: PCIE_X2_TOP_INST_CLOCK_ENABLE :: PCIE_108_CLOCK_ENABLE [00:00] */
-#define BCHP_CLKGEN_PCIE_X2_TOP_INST_CLOCK_ENABLE_PCIE_108_CLOCK_ENABLE_MASK 0x00000001
-#define BCHP_CLKGEN_PCIE_X2_TOP_INST_CLOCK_ENABLE_PCIE_108_CLOCK_ENABLE_SHIFT 0
-#define BCHP_CLKGEN_PCIE_X2_TOP_INST_CLOCK_ENABLE_PCIE_108_CLOCK_ENABLE_DEFAULT 0x00000001
-
-/***************************************************************************
- *PCIE_X2_TOP_INST_CLOCK_ENABLE_STATUS - Clock Enable Status
- ***************************************************************************/
-/* CLKGEN :: PCIE_X2_TOP_INST_CLOCK_ENABLE_STATUS :: reserved0 [31:04] */
-#define BCHP_CLKGEN_PCIE_X2_TOP_INST_CLOCK_ENABLE_STATUS_reserved0_MASK 0xfffffff0
-#define BCHP_CLKGEN_PCIE_X2_TOP_INST_CLOCK_ENABLE_STATUS_reserved0_SHIFT 4
-
-/* CLKGEN :: PCIE_X2_TOP_INST_CLOCK_ENABLE_STATUS :: PCIE_SCB_CLOCK_ENABLE_STATUS [03:03] */
-#define BCHP_CLKGEN_PCIE_X2_TOP_INST_CLOCK_ENABLE_STATUS_PCIE_SCB_CLOCK_ENABLE_STATUS_MASK 0x00000008
-#define BCHP_CLKGEN_PCIE_X2_TOP_INST_CLOCK_ENABLE_STATUS_PCIE_SCB_CLOCK_ENABLE_STATUS_SHIFT 3
-
-/* CLKGEN :: PCIE_X2_TOP_INST_CLOCK_ENABLE_STATUS :: PCIE_GISB_CLOCK_ENABLE_STATUS [02:02] */
-#define BCHP_CLKGEN_PCIE_X2_TOP_INST_CLOCK_ENABLE_STATUS_PCIE_GISB_CLOCK_ENABLE_STATUS_MASK 0x00000004
-#define BCHP_CLKGEN_PCIE_X2_TOP_INST_CLOCK_ENABLE_STATUS_PCIE_GISB_CLOCK_ENABLE_STATUS_SHIFT 2
-
-/* CLKGEN :: PCIE_X2_TOP_INST_CLOCK_ENABLE_STATUS :: PCIE_54_CLOCK_ENABLE_STATUS [01:01] */
-#define BCHP_CLKGEN_PCIE_X2_TOP_INST_CLOCK_ENABLE_STATUS_PCIE_54_CLOCK_ENABLE_STATUS_MASK 0x00000002
-#define BCHP_CLKGEN_PCIE_X2_TOP_INST_CLOCK_ENABLE_STATUS_PCIE_54_CLOCK_ENABLE_STATUS_SHIFT 1
-
-/* CLKGEN :: PCIE_X2_TOP_INST_CLOCK_ENABLE_STATUS :: PCIE_108_CLOCK_ENABLE_STATUS [00:00] */
-#define BCHP_CLKGEN_PCIE_X2_TOP_INST_CLOCK_ENABLE_STATUS_PCIE_108_CLOCK_ENABLE_STATUS_MASK 0x00000001
-#define BCHP_CLKGEN_PCIE_X2_TOP_INST_CLOCK_ENABLE_STATUS_PCIE_108_CLOCK_ENABLE_STATUS_SHIFT 0
-
-/***************************************************************************
- *PCIE_X2_TOP_INST_OBSERVE_CLOCK - Pcie x2 top inst observe clock
- ***************************************************************************/
-/* CLKGEN :: PCIE_X2_TOP_INST_OBSERVE_CLOCK :: reserved0 [31:06] */
-#define BCHP_CLKGEN_PCIE_X2_TOP_INST_OBSERVE_CLOCK_reserved0_MASK 0xffffffc0
-#define BCHP_CLKGEN_PCIE_X2_TOP_INST_OBSERVE_CLOCK_reserved0_SHIFT 6
-
-/* CLKGEN :: PCIE_X2_TOP_INST_OBSERVE_CLOCK :: PCIE_ENABLE_OBSERVE_CLOCK [05:05] */
-#define BCHP_CLKGEN_PCIE_X2_TOP_INST_OBSERVE_CLOCK_PCIE_ENABLE_OBSERVE_CLOCK_MASK 0x00000020
-#define BCHP_CLKGEN_PCIE_X2_TOP_INST_OBSERVE_CLOCK_PCIE_ENABLE_OBSERVE_CLOCK_SHIFT 5
-#define BCHP_CLKGEN_PCIE_X2_TOP_INST_OBSERVE_CLOCK_PCIE_ENABLE_OBSERVE_CLOCK_DEFAULT 0x00000000
-
-/* CLKGEN :: PCIE_X2_TOP_INST_OBSERVE_CLOCK :: PCIE_ENABLE_DIVIDER_OBSERVE_CLOCK [04:04] */
-#define BCHP_CLKGEN_PCIE_X2_TOP_INST_OBSERVE_CLOCK_PCIE_ENABLE_DIVIDER_OBSERVE_CLOCK_MASK 0x00000010
-#define BCHP_CLKGEN_PCIE_X2_TOP_INST_OBSERVE_CLOCK_PCIE_ENABLE_DIVIDER_OBSERVE_CLOCK_SHIFT 4
-#define BCHP_CLKGEN_PCIE_X2_TOP_INST_OBSERVE_CLOCK_PCIE_ENABLE_DIVIDER_OBSERVE_CLOCK_DEFAULT 0x00000000
-
-/* CLKGEN :: PCIE_X2_TOP_INST_OBSERVE_CLOCK :: PCIE_CONTROL_OBSERVE_CLOCK [03:00] */
-#define BCHP_CLKGEN_PCIE_X2_TOP_INST_OBSERVE_CLOCK_PCIE_CONTROL_OBSERVE_CLOCK_MASK 0x0000000f
-#define BCHP_CLKGEN_PCIE_X2_TOP_INST_OBSERVE_CLOCK_PCIE_CONTROL_OBSERVE_CLOCK_SHIFT 0
-#define BCHP_CLKGEN_PCIE_X2_TOP_INST_OBSERVE_CLOCK_PCIE_CONTROL_OBSERVE_CLOCK_DEFAULT 0x00000000
-
-/***************************************************************************
- *PLL_AUDIO0_PLL_RESET_STATUS - PLL_AUDIO0 Reset Status
- ***************************************************************************/
-/* CLKGEN :: PLL_AUDIO0_PLL_RESET_STATUS :: reserved0 [31:02] */
-#define BCHP_CLKGEN_PLL_AUDIO0_PLL_RESET_STATUS_reserved0_MASK 0xfffffffc
-#define BCHP_CLKGEN_PLL_AUDIO0_PLL_RESET_STATUS_reserved0_SHIFT 2
-
-/* CLKGEN :: PLL_AUDIO0_PLL_RESET_STATUS :: PLL_DRESET_STATUS [01:01] */
-#define BCHP_CLKGEN_PLL_AUDIO0_PLL_RESET_STATUS_PLL_DRESET_STATUS_MASK 0x00000002
-#define BCHP_CLKGEN_PLL_AUDIO0_PLL_RESET_STATUS_PLL_DRESET_STATUS_SHIFT 1
-
-/* CLKGEN :: PLL_AUDIO0_PLL_RESET_STATUS :: PLL_ARESET_STATUS [00:00] */
-#define BCHP_CLKGEN_PLL_AUDIO0_PLL_RESET_STATUS_PLL_ARESET_STATUS_MASK 0x00000001
-#define BCHP_CLKGEN_PLL_AUDIO0_PLL_RESET_STATUS_PLL_ARESET_STATUS_SHIFT 0
-
-/***************************************************************************
- *PLL_AUDIO1_PLL_RESET_STATUS - PLL_AUDIO1 Reset Status
- ***************************************************************************/
-/* CLKGEN :: PLL_AUDIO1_PLL_RESET_STATUS :: reserved0 [31:02] */
-#define BCHP_CLKGEN_PLL_AUDIO1_PLL_RESET_STATUS_reserved0_MASK 0xfffffffc
-#define BCHP_CLKGEN_PLL_AUDIO1_PLL_RESET_STATUS_reserved0_SHIFT 2
-
-/* CLKGEN :: PLL_AUDIO1_PLL_RESET_STATUS :: PLL_DRESET_STATUS [01:01] */
-#define BCHP_CLKGEN_PLL_AUDIO1_PLL_RESET_STATUS_PLL_DRESET_STATUS_MASK 0x00000002
-#define BCHP_CLKGEN_PLL_AUDIO1_PLL_RESET_STATUS_PLL_DRESET_STATUS_SHIFT 1
-
-/* CLKGEN :: PLL_AUDIO1_PLL_RESET_STATUS :: PLL_ARESET_STATUS [00:00] */
-#define BCHP_CLKGEN_PLL_AUDIO1_PLL_RESET_STATUS_PLL_ARESET_STATUS_MASK 0x00000001
-#define BCHP_CLKGEN_PLL_AUDIO1_PLL_RESET_STATUS_PLL_ARESET_STATUS_SHIFT 0
-
-/***************************************************************************
- *PLL_AUDIO2_PLL_RESET_STATUS - PLL_AUDIO2 Reset Status
- ***************************************************************************/
-/* CLKGEN :: PLL_AUDIO2_PLL_RESET_STATUS :: reserved0 [31:02] */
-#define BCHP_CLKGEN_PLL_AUDIO2_PLL_RESET_STATUS_reserved0_MASK 0xfffffffc
-#define BCHP_CLKGEN_PLL_AUDIO2_PLL_RESET_STATUS_reserved0_SHIFT 2
-
-/* CLKGEN :: PLL_AUDIO2_PLL_RESET_STATUS :: PLL_DRESET_STATUS [01:01] */
-#define BCHP_CLKGEN_PLL_AUDIO2_PLL_RESET_STATUS_PLL_DRESET_STATUS_MASK 0x00000002
-#define BCHP_CLKGEN_PLL_AUDIO2_PLL_RESET_STATUS_PLL_DRESET_STATUS_SHIFT 1
-
-/* CLKGEN :: PLL_AUDIO2_PLL_RESET_STATUS :: PLL_ARESET_STATUS [00:00] */
-#define BCHP_CLKGEN_PLL_AUDIO2_PLL_RESET_STATUS_PLL_ARESET_STATUS_MASK 0x00000001
-#define BCHP_CLKGEN_PLL_AUDIO2_PLL_RESET_STATUS_PLL_ARESET_STATUS_SHIFT 0
-
-/***************************************************************************
- *PLL_AVD_PLL_RESET_STATUS - PLL_AVD Reset Status
- ***************************************************************************/
-/* CLKGEN :: PLL_AVD_PLL_RESET_STATUS :: reserved0 [31:02] */
-#define BCHP_CLKGEN_PLL_AVD_PLL_RESET_STATUS_reserved0_MASK 0xfffffffc
-#define BCHP_CLKGEN_PLL_AVD_PLL_RESET_STATUS_reserved0_SHIFT 2
-
-/* CLKGEN :: PLL_AVD_PLL_RESET_STATUS :: PLL_DRESET_STATUS [01:01] */
-#define BCHP_CLKGEN_PLL_AVD_PLL_RESET_STATUS_PLL_DRESET_STATUS_MASK 0x00000002
-#define BCHP_CLKGEN_PLL_AVD_PLL_RESET_STATUS_PLL_DRESET_STATUS_SHIFT 1
-
-/* CLKGEN :: PLL_AVD_PLL_RESET_STATUS :: PLL_ARESET_STATUS [00:00] */
-#define BCHP_CLKGEN_PLL_AVD_PLL_RESET_STATUS_PLL_ARESET_STATUS_MASK 0x00000001
-#define BCHP_CLKGEN_PLL_AVD_PLL_RESET_STATUS_PLL_ARESET_STATUS_SHIFT 0
-
-/***************************************************************************
- *PLL_AVD_RDB_MACRO_CTRL - PLL RDB Macro Disable
- ***************************************************************************/
-/* CLKGEN :: PLL_AVD_RDB_MACRO_CTRL :: reserved0 [31:04] */
-#define BCHP_CLKGEN_PLL_AVD_RDB_MACRO_CTRL_reserved0_MASK 0xfffffff0
-#define BCHP_CLKGEN_PLL_AVD_RDB_MACRO_CTRL_reserved0_SHIFT 4
-
-/* CLKGEN :: PLL_AVD_RDB_MACRO_CTRL :: PLL_AVD_OPTIONS_DISABLE_RDB_MACRO [03:03] */
-#define BCHP_CLKGEN_PLL_AVD_RDB_MACRO_CTRL_PLL_AVD_OPTIONS_DISABLE_RDB_MACRO_MASK 0x00000008
-#define BCHP_CLKGEN_PLL_AVD_RDB_MACRO_CTRL_PLL_AVD_OPTIONS_DISABLE_RDB_MACRO_SHIFT 3
-#define BCHP_CLKGEN_PLL_AVD_RDB_MACRO_CTRL_PLL_AVD_OPTIONS_DISABLE_RDB_MACRO_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_AVD_RDB_MACRO_CTRL :: OPTIONS [02:00] */
-#define BCHP_CLKGEN_PLL_AVD_RDB_MACRO_CTRL_OPTIONS_MASK 0x00000007
-#define BCHP_CLKGEN_PLL_AVD_RDB_MACRO_CTRL_OPTIONS_SHIFT 0
-#define BCHP_CLKGEN_PLL_AVD_RDB_MACRO_CTRL_OPTIONS_DEFAULT 0x00000000
-
-/***************************************************************************
- *PLL_CPU_CORE_GLITCHLESS_SWITCH_REQUEST - PLL_CPU_CORE Glitchless Clock Switching
- ***************************************************************************/
-/* CLKGEN :: PLL_CPU_CORE_GLITCHLESS_SWITCH_REQUEST :: reserved0 [31:09] */
-#define BCHP_CLKGEN_PLL_CPU_CORE_GLITCHLESS_SWITCH_REQUEST_reserved0_MASK 0xfffffe00
-#define BCHP_CLKGEN_PLL_CPU_CORE_GLITCHLESS_SWITCH_REQUEST_reserved0_SHIFT 9
-
-/* CLKGEN :: PLL_CPU_CORE_GLITCHLESS_SWITCH_REQUEST :: TRANSACTION_WAIT [08:01] */
-#define BCHP_CLKGEN_PLL_CPU_CORE_GLITCHLESS_SWITCH_REQUEST_TRANSACTION_WAIT_MASK 0x000001fe
-#define BCHP_CLKGEN_PLL_CPU_CORE_GLITCHLESS_SWITCH_REQUEST_TRANSACTION_WAIT_SHIFT 1
-#define BCHP_CLKGEN_PLL_CPU_CORE_GLITCHLESS_SWITCH_REQUEST_TRANSACTION_WAIT_DEFAULT 0x0000001f
-
-/* CLKGEN :: PLL_CPU_CORE_GLITCHLESS_SWITCH_REQUEST :: PLL_BYPASS_REQUEST [00:00] */
-#define BCHP_CLKGEN_PLL_CPU_CORE_GLITCHLESS_SWITCH_REQUEST_PLL_BYPASS_REQUEST_MASK 0x00000001
-#define BCHP_CLKGEN_PLL_CPU_CORE_GLITCHLESS_SWITCH_REQUEST_PLL_BYPASS_REQUEST_SHIFT 0
-#define BCHP_CLKGEN_PLL_CPU_CORE_GLITCHLESS_SWITCH_REQUEST_PLL_BYPASS_REQUEST_DEFAULT 0x00000000
-
-/***************************************************************************
- *PLL_CPU_CORE_GLITCHLESS_SWITCH_STATUS - PLL_CPU_CORE Glitchless Switching
- ***************************************************************************/
-/* CLKGEN :: PLL_CPU_CORE_GLITCHLESS_SWITCH_STATUS :: reserved0 [31:04] */
-#define BCHP_CLKGEN_PLL_CPU_CORE_GLITCHLESS_SWITCH_STATUS_reserved0_MASK 0xfffffff0
-#define BCHP_CLKGEN_PLL_CPU_CORE_GLITCHLESS_SWITCH_STATUS_reserved0_SHIFT 4
-
-/* CLKGEN :: PLL_CPU_CORE_GLITCHLESS_SWITCH_STATUS :: PLL_BYPASS_STATUS [03:00] */
-#define BCHP_CLKGEN_PLL_CPU_CORE_GLITCHLESS_SWITCH_STATUS_PLL_BYPASS_STATUS_MASK 0x0000000f
-#define BCHP_CLKGEN_PLL_CPU_CORE_GLITCHLESS_SWITCH_STATUS_PLL_BYPASS_STATUS_SHIFT 0
-
-/***************************************************************************
- *PLL_CPU_CORE_PLL_RESET_STATUS - PLL_CPU_CORE Reset Status
- ***************************************************************************/
-/* CLKGEN :: PLL_CPU_CORE_PLL_RESET_STATUS :: reserved0 [31:02] */
-#define BCHP_CLKGEN_PLL_CPU_CORE_PLL_RESET_STATUS_reserved0_MASK 0xfffffffc
-#define BCHP_CLKGEN_PLL_CPU_CORE_PLL_RESET_STATUS_reserved0_SHIFT 2
-
-/* CLKGEN :: PLL_CPU_CORE_PLL_RESET_STATUS :: PLL_DRESET_STATUS [01:01] */
-#define BCHP_CLKGEN_PLL_CPU_CORE_PLL_RESET_STATUS_PLL_DRESET_STATUS_MASK 0x00000002
-#define BCHP_CLKGEN_PLL_CPU_CORE_PLL_RESET_STATUS_PLL_DRESET_STATUS_SHIFT 1
-
-/* CLKGEN :: PLL_CPU_CORE_PLL_RESET_STATUS :: PLL_ARESET_STATUS [00:00] */
-#define BCHP_CLKGEN_PLL_CPU_CORE_PLL_RESET_STATUS_PLL_ARESET_STATUS_MASK 0x00000001
-#define BCHP_CLKGEN_PLL_CPU_CORE_PLL_RESET_STATUS_PLL_ARESET_STATUS_SHIFT 0
-
-/***************************************************************************
- *PLL_CPU_CORE_RDB_MACRO_CTRL - PLL RDB Macro Disable
- ***************************************************************************/
-/* CLKGEN :: PLL_CPU_CORE_RDB_MACRO_CTRL :: reserved0 [31:04] */
-#define BCHP_CLKGEN_PLL_CPU_CORE_RDB_MACRO_CTRL_reserved0_MASK 0xfffffff0
-#define BCHP_CLKGEN_PLL_CPU_CORE_RDB_MACRO_CTRL_reserved0_SHIFT 4
-
-/* CLKGEN :: PLL_CPU_CORE_RDB_MACRO_CTRL :: PLL_CPU_CORE_OPTIONS_DISABLE_RDB_MACRO [03:03] */
-#define BCHP_CLKGEN_PLL_CPU_CORE_RDB_MACRO_CTRL_PLL_CPU_CORE_OPTIONS_DISABLE_RDB_MACRO_MASK 0x00000008
-#define BCHP_CLKGEN_PLL_CPU_CORE_RDB_MACRO_CTRL_PLL_CPU_CORE_OPTIONS_DISABLE_RDB_MACRO_SHIFT 3
-#define BCHP_CLKGEN_PLL_CPU_CORE_RDB_MACRO_CTRL_PLL_CPU_CORE_OPTIONS_DISABLE_RDB_MACRO_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_CPU_CORE_RDB_MACRO_CTRL :: OPTIONS [02:00] */
-#define BCHP_CLKGEN_PLL_CPU_CORE_RDB_MACRO_CTRL_OPTIONS_MASK 0x00000007
-#define BCHP_CLKGEN_PLL_CPU_CORE_RDB_MACRO_CTRL_OPTIONS_SHIFT 0
-#define BCHP_CLKGEN_PLL_CPU_CORE_RDB_MACRO_CTRL_OPTIONS_DEFAULT 0x00000000
-
-/***************************************************************************
- *PLL_CPU_ROUTER_PLL_RESET_STATUS - PLL_CPU_ROUTER Reset Status
- ***************************************************************************/
-/* CLKGEN :: PLL_CPU_ROUTER_PLL_RESET_STATUS :: reserved0 [31:02] */
-#define BCHP_CLKGEN_PLL_CPU_ROUTER_PLL_RESET_STATUS_reserved0_MASK 0xfffffffc
-#define BCHP_CLKGEN_PLL_CPU_ROUTER_PLL_RESET_STATUS_reserved0_SHIFT 2
-
-/* CLKGEN :: PLL_CPU_ROUTER_PLL_RESET_STATUS :: PLL_DRESET_STATUS [01:01] */
-#define BCHP_CLKGEN_PLL_CPU_ROUTER_PLL_RESET_STATUS_PLL_DRESET_STATUS_MASK 0x00000002
-#define BCHP_CLKGEN_PLL_CPU_ROUTER_PLL_RESET_STATUS_PLL_DRESET_STATUS_SHIFT 1
-
-/* CLKGEN :: PLL_CPU_ROUTER_PLL_RESET_STATUS :: PLL_ARESET_STATUS [00:00] */
-#define BCHP_CLKGEN_PLL_CPU_ROUTER_PLL_RESET_STATUS_PLL_ARESET_STATUS_MASK 0x00000001
-#define BCHP_CLKGEN_PLL_CPU_ROUTER_PLL_RESET_STATUS_PLL_ARESET_STATUS_SHIFT 0
-
-/***************************************************************************
- *PLL_CPU_ROUTER_RDB_MACRO_CTRL - PLL RDB Macro Disable
- ***************************************************************************/
-/* CLKGEN :: PLL_CPU_ROUTER_RDB_MACRO_CTRL :: reserved0 [31:04] */
-#define BCHP_CLKGEN_PLL_CPU_ROUTER_RDB_MACRO_CTRL_reserved0_MASK 0xfffffff0
-#define BCHP_CLKGEN_PLL_CPU_ROUTER_RDB_MACRO_CTRL_reserved0_SHIFT 4
-
-/* CLKGEN :: PLL_CPU_ROUTER_RDB_MACRO_CTRL :: PLL_CPU_ROUTER_OPTIONS_DISABLE_RDB_MACRO [03:03] */
-#define BCHP_CLKGEN_PLL_CPU_ROUTER_RDB_MACRO_CTRL_PLL_CPU_ROUTER_OPTIONS_DISABLE_RDB_MACRO_MASK 0x00000008
-#define BCHP_CLKGEN_PLL_CPU_ROUTER_RDB_MACRO_CTRL_PLL_CPU_ROUTER_OPTIONS_DISABLE_RDB_MACRO_SHIFT 3
-#define BCHP_CLKGEN_PLL_CPU_ROUTER_RDB_MACRO_CTRL_PLL_CPU_ROUTER_OPTIONS_DISABLE_RDB_MACRO_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_CPU_ROUTER_RDB_MACRO_CTRL :: OPTIONS [02:00] */
-#define BCHP_CLKGEN_PLL_CPU_ROUTER_RDB_MACRO_CTRL_OPTIONS_MASK 0x00000007
-#define BCHP_CLKGEN_PLL_CPU_ROUTER_RDB_MACRO_CTRL_OPTIONS_SHIFT 0
-#define BCHP_CLKGEN_PLL_CPU_ROUTER_RDB_MACRO_CTRL_OPTIONS_DEFAULT 0x00000000
-
-/***************************************************************************
- *PLL_LC_PLL_RESET_STATUS - PLL_LC Reset Status
- ***************************************************************************/
-/* CLKGEN :: PLL_LC_PLL_RESET_STATUS :: reserved0 [31:02] */
-#define BCHP_CLKGEN_PLL_LC_PLL_RESET_STATUS_reserved0_MASK 0xfffffffc
-#define BCHP_CLKGEN_PLL_LC_PLL_RESET_STATUS_reserved0_SHIFT 2
-
-/* CLKGEN :: PLL_LC_PLL_RESET_STATUS :: PLL_DRESET_STATUS [01:01] */
-#define BCHP_CLKGEN_PLL_LC_PLL_RESET_STATUS_PLL_DRESET_STATUS_MASK 0x00000002
-#define BCHP_CLKGEN_PLL_LC_PLL_RESET_STATUS_PLL_DRESET_STATUS_SHIFT 1
-
-/* CLKGEN :: PLL_LC_PLL_RESET_STATUS :: PLL_ARESET_STATUS [00:00] */
-#define BCHP_CLKGEN_PLL_LC_PLL_RESET_STATUS_PLL_ARESET_STATUS_MASK 0x00000001
-#define BCHP_CLKGEN_PLL_LC_PLL_RESET_STATUS_PLL_ARESET_STATUS_SHIFT 0
-
-/***************************************************************************
- *PLL_LC_RDB_MACRO_CTRL - PLL RDB Macro Disable
- ***************************************************************************/
-/* CLKGEN :: PLL_LC_RDB_MACRO_CTRL :: reserved0 [31:02] */
-#define BCHP_CLKGEN_PLL_LC_RDB_MACRO_CTRL_reserved0_MASK 0xfffffffc
-#define BCHP_CLKGEN_PLL_LC_RDB_MACRO_CTRL_reserved0_SHIFT 2
-
-/* CLKGEN :: PLL_LC_RDB_MACRO_CTRL :: PLL_LC_CHANNEL0_FREQ_DISABLE_RDB_MACRO [01:01] */
-#define BCHP_CLKGEN_PLL_LC_RDB_MACRO_CTRL_PLL_LC_CHANNEL0_FREQ_DISABLE_RDB_MACRO_MASK 0x00000002
-#define BCHP_CLKGEN_PLL_LC_RDB_MACRO_CTRL_PLL_LC_CHANNEL0_FREQ_DISABLE_RDB_MACRO_SHIFT 1
-#define BCHP_CLKGEN_PLL_LC_RDB_MACRO_CTRL_PLL_LC_CHANNEL0_FREQ_DISABLE_RDB_MACRO_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_LC_RDB_MACRO_CTRL :: CHANNEL0_FREQ [00:00] */
-#define BCHP_CLKGEN_PLL_LC_RDB_MACRO_CTRL_CHANNEL0_FREQ_MASK 0x00000001
-#define BCHP_CLKGEN_PLL_LC_RDB_MACRO_CTRL_CHANNEL0_FREQ_SHIFT 0
-#define BCHP_CLKGEN_PLL_LC_RDB_MACRO_CTRL_CHANNEL0_FREQ_DEFAULT 0x00000000
-
-/***************************************************************************
- *PLL_MOCA_PLL_RESET_STATUS - PLL_MOCA Reset Status
- ***************************************************************************/
-/* CLKGEN :: PLL_MOCA_PLL_RESET_STATUS :: reserved0 [31:02] */
-#define BCHP_CLKGEN_PLL_MOCA_PLL_RESET_STATUS_reserved0_MASK 0xfffffffc
-#define BCHP_CLKGEN_PLL_MOCA_PLL_RESET_STATUS_reserved0_SHIFT 2
-
-/* CLKGEN :: PLL_MOCA_PLL_RESET_STATUS :: PLL_DRESET_STATUS [01:01] */
-#define BCHP_CLKGEN_PLL_MOCA_PLL_RESET_STATUS_PLL_DRESET_STATUS_MASK 0x00000002
-#define BCHP_CLKGEN_PLL_MOCA_PLL_RESET_STATUS_PLL_DRESET_STATUS_SHIFT 1
-
-/* CLKGEN :: PLL_MOCA_PLL_RESET_STATUS :: PLL_ARESET_STATUS [00:00] */
-#define BCHP_CLKGEN_PLL_MOCA_PLL_RESET_STATUS_PLL_ARESET_STATUS_MASK 0x00000001
-#define BCHP_CLKGEN_PLL_MOCA_PLL_RESET_STATUS_PLL_ARESET_STATUS_SHIFT 0
-
-/***************************************************************************
- *PLL_MOCA_RDB_MACRO_CTRL - PLL RDB Macro Disable
- ***************************************************************************/
-/* CLKGEN :: PLL_MOCA_RDB_MACRO_CTRL :: reserved0 [31:08] */
-#define BCHP_CLKGEN_PLL_MOCA_RDB_MACRO_CTRL_reserved0_MASK 0xffffff00
-#define BCHP_CLKGEN_PLL_MOCA_RDB_MACRO_CTRL_reserved0_SHIFT 8
-
-/* CLKGEN :: PLL_MOCA_RDB_MACRO_CTRL :: PLL_MOCA_CHANNEL3_FREQ_DISABLE_RDB_MACRO [07:07] */
-#define BCHP_CLKGEN_PLL_MOCA_RDB_MACRO_CTRL_PLL_MOCA_CHANNEL3_FREQ_DISABLE_RDB_MACRO_MASK 0x00000080
-#define BCHP_CLKGEN_PLL_MOCA_RDB_MACRO_CTRL_PLL_MOCA_CHANNEL3_FREQ_DISABLE_RDB_MACRO_SHIFT 7
-#define BCHP_CLKGEN_PLL_MOCA_RDB_MACRO_CTRL_PLL_MOCA_CHANNEL3_FREQ_DISABLE_RDB_MACRO_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_MOCA_RDB_MACRO_CTRL :: PLL_MOCA_CHANNEL1_FREQ_DISABLE_RDB_MACRO [06:06] */
-#define BCHP_CLKGEN_PLL_MOCA_RDB_MACRO_CTRL_PLL_MOCA_CHANNEL1_FREQ_DISABLE_RDB_MACRO_MASK 0x00000040
-#define BCHP_CLKGEN_PLL_MOCA_RDB_MACRO_CTRL_PLL_MOCA_CHANNEL1_FREQ_DISABLE_RDB_MACRO_SHIFT 6
-#define BCHP_CLKGEN_PLL_MOCA_RDB_MACRO_CTRL_PLL_MOCA_CHANNEL1_FREQ_DISABLE_RDB_MACRO_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_MOCA_RDB_MACRO_CTRL :: PLL_MOCA_CHANNEL0_FREQ_DISABLE_RDB_MACRO [05:05] */
-#define BCHP_CLKGEN_PLL_MOCA_RDB_MACRO_CTRL_PLL_MOCA_CHANNEL0_FREQ_DISABLE_RDB_MACRO_MASK 0x00000020
-#define BCHP_CLKGEN_PLL_MOCA_RDB_MACRO_CTRL_PLL_MOCA_CHANNEL0_FREQ_DISABLE_RDB_MACRO_SHIFT 5
-#define BCHP_CLKGEN_PLL_MOCA_RDB_MACRO_CTRL_PLL_MOCA_CHANNEL0_FREQ_DISABLE_RDB_MACRO_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_MOCA_RDB_MACRO_CTRL :: CHANNEL3_FREQ [04:04] */
-#define BCHP_CLKGEN_PLL_MOCA_RDB_MACRO_CTRL_CHANNEL3_FREQ_MASK 0x00000010
-#define BCHP_CLKGEN_PLL_MOCA_RDB_MACRO_CTRL_CHANNEL3_FREQ_SHIFT 4
-#define BCHP_CLKGEN_PLL_MOCA_RDB_MACRO_CTRL_CHANNEL3_FREQ_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_MOCA_RDB_MACRO_CTRL :: CHANNEL1_FREQ [03:02] */
-#define BCHP_CLKGEN_PLL_MOCA_RDB_MACRO_CTRL_CHANNEL1_FREQ_MASK 0x0000000c
-#define BCHP_CLKGEN_PLL_MOCA_RDB_MACRO_CTRL_CHANNEL1_FREQ_SHIFT 2
-#define BCHP_CLKGEN_PLL_MOCA_RDB_MACRO_CTRL_CHANNEL1_FREQ_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_MOCA_RDB_MACRO_CTRL :: CHANNEL0_FREQ [01:00] */
-#define BCHP_CLKGEN_PLL_MOCA_RDB_MACRO_CTRL_CHANNEL0_FREQ_MASK 0x00000003
-#define BCHP_CLKGEN_PLL_MOCA_RDB_MACRO_CTRL_CHANNEL0_FREQ_SHIFT 0
-#define BCHP_CLKGEN_PLL_MOCA_RDB_MACRO_CTRL_CHANNEL0_FREQ_DEFAULT 0x00000000
-
-/***************************************************************************
- *PLL_RAAGA_PLL_RESET_STATUS - PLL_RAAGA Reset Status
- ***************************************************************************/
-/* CLKGEN :: PLL_RAAGA_PLL_RESET_STATUS :: reserved0 [31:02] */
-#define BCHP_CLKGEN_PLL_RAAGA_PLL_RESET_STATUS_reserved0_MASK 0xfffffffc
-#define BCHP_CLKGEN_PLL_RAAGA_PLL_RESET_STATUS_reserved0_SHIFT 2
-
-/* CLKGEN :: PLL_RAAGA_PLL_RESET_STATUS :: PLL_DRESET_STATUS [01:01] */
-#define BCHP_CLKGEN_PLL_RAAGA_PLL_RESET_STATUS_PLL_DRESET_STATUS_MASK 0x00000002
-#define BCHP_CLKGEN_PLL_RAAGA_PLL_RESET_STATUS_PLL_DRESET_STATUS_SHIFT 1
-
-/* CLKGEN :: PLL_RAAGA_PLL_RESET_STATUS :: PLL_ARESET_STATUS [00:00] */
-#define BCHP_CLKGEN_PLL_RAAGA_PLL_RESET_STATUS_PLL_ARESET_STATUS_MASK 0x00000001
-#define BCHP_CLKGEN_PLL_RAAGA_PLL_RESET_STATUS_PLL_ARESET_STATUS_SHIFT 0
-
-/***************************************************************************
- *PLL_RAAGA_RDB_MACRO_CTRL - PLL RDB Macro Disable
- ***************************************************************************/
-/* CLKGEN :: PLL_RAAGA_RDB_MACRO_CTRL :: reserved0 [31:04] */
-#define BCHP_CLKGEN_PLL_RAAGA_RDB_MACRO_CTRL_reserved0_MASK 0xfffffff0
-#define BCHP_CLKGEN_PLL_RAAGA_RDB_MACRO_CTRL_reserved0_SHIFT 4
-
-/* CLKGEN :: PLL_RAAGA_RDB_MACRO_CTRL :: PLL_RAAGA_OPTIONS_DISABLE_RDB_MACRO [03:03] */
-#define BCHP_CLKGEN_PLL_RAAGA_RDB_MACRO_CTRL_PLL_RAAGA_OPTIONS_DISABLE_RDB_MACRO_MASK 0x00000008
-#define BCHP_CLKGEN_PLL_RAAGA_RDB_MACRO_CTRL_PLL_RAAGA_OPTIONS_DISABLE_RDB_MACRO_SHIFT 3
-#define BCHP_CLKGEN_PLL_RAAGA_RDB_MACRO_CTRL_PLL_RAAGA_OPTIONS_DISABLE_RDB_MACRO_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_RAAGA_RDB_MACRO_CTRL :: OPTIONS [02:00] */
-#define BCHP_CLKGEN_PLL_RAAGA_RDB_MACRO_CTRL_OPTIONS_MASK 0x00000007
-#define BCHP_CLKGEN_PLL_RAAGA_RDB_MACRO_CTRL_OPTIONS_SHIFT 0
-#define BCHP_CLKGEN_PLL_RAAGA_RDB_MACRO_CTRL_OPTIONS_DEFAULT 0x00000000
-
-/***************************************************************************
- *PLL_SC0_PLL_RESET_STATUS - PLL_SC0 Reset Status
- ***************************************************************************/
-/* CLKGEN :: PLL_SC0_PLL_RESET_STATUS :: reserved0 [31:02] */
-#define BCHP_CLKGEN_PLL_SC0_PLL_RESET_STATUS_reserved0_MASK 0xfffffffc
-#define BCHP_CLKGEN_PLL_SC0_PLL_RESET_STATUS_reserved0_SHIFT 2
-
-/* CLKGEN :: PLL_SC0_PLL_RESET_STATUS :: PLL_DRESET_STATUS [01:01] */
-#define BCHP_CLKGEN_PLL_SC0_PLL_RESET_STATUS_PLL_DRESET_STATUS_MASK 0x00000002
-#define BCHP_CLKGEN_PLL_SC0_PLL_RESET_STATUS_PLL_DRESET_STATUS_SHIFT 1
-
-/* CLKGEN :: PLL_SC0_PLL_RESET_STATUS :: PLL_ARESET_STATUS [00:00] */
-#define BCHP_CLKGEN_PLL_SC0_PLL_RESET_STATUS_PLL_ARESET_STATUS_MASK 0x00000001
-#define BCHP_CLKGEN_PLL_SC0_PLL_RESET_STATUS_PLL_ARESET_STATUS_SHIFT 0
-
-/***************************************************************************
- *PLL_SC0_RDB_MACRO_CTRL - PLL RDB Macro Disable
- ***************************************************************************/
-/* CLKGEN :: PLL_SC0_RDB_MACRO_CTRL :: reserved0 [31:05] */
-#define BCHP_CLKGEN_PLL_SC0_RDB_MACRO_CTRL_reserved0_MASK 0xffffffe0
-#define BCHP_CLKGEN_PLL_SC0_RDB_MACRO_CTRL_reserved0_SHIFT 5
-
-/* CLKGEN :: PLL_SC0_RDB_MACRO_CTRL :: PLL_SC0_OPTIONS_DISABLE_RDB_MACRO [04:04] */
-#define BCHP_CLKGEN_PLL_SC0_RDB_MACRO_CTRL_PLL_SC0_OPTIONS_DISABLE_RDB_MACRO_MASK 0x00000010
-#define BCHP_CLKGEN_PLL_SC0_RDB_MACRO_CTRL_PLL_SC0_OPTIONS_DISABLE_RDB_MACRO_SHIFT 4
-#define BCHP_CLKGEN_PLL_SC0_RDB_MACRO_CTRL_PLL_SC0_OPTIONS_DISABLE_RDB_MACRO_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_SC0_RDB_MACRO_CTRL :: OPTIONS [03:00] */
-#define BCHP_CLKGEN_PLL_SC0_RDB_MACRO_CTRL_OPTIONS_MASK 0x0000000f
-#define BCHP_CLKGEN_PLL_SC0_RDB_MACRO_CTRL_OPTIONS_SHIFT 0
-#define BCHP_CLKGEN_PLL_SC0_RDB_MACRO_CTRL_OPTIONS_DEFAULT 0x00000000
-
-/***************************************************************************
- *PLL_SC1_PLL_RESET_STATUS - PLL_SC1 Reset Status
- ***************************************************************************/
-/* CLKGEN :: PLL_SC1_PLL_RESET_STATUS :: reserved0 [31:02] */
-#define BCHP_CLKGEN_PLL_SC1_PLL_RESET_STATUS_reserved0_MASK 0xfffffffc
-#define BCHP_CLKGEN_PLL_SC1_PLL_RESET_STATUS_reserved0_SHIFT 2
-
-/* CLKGEN :: PLL_SC1_PLL_RESET_STATUS :: PLL_DRESET_STATUS [01:01] */
-#define BCHP_CLKGEN_PLL_SC1_PLL_RESET_STATUS_PLL_DRESET_STATUS_MASK 0x00000002
-#define BCHP_CLKGEN_PLL_SC1_PLL_RESET_STATUS_PLL_DRESET_STATUS_SHIFT 1
-
-/* CLKGEN :: PLL_SC1_PLL_RESET_STATUS :: PLL_ARESET_STATUS [00:00] */
-#define BCHP_CLKGEN_PLL_SC1_PLL_RESET_STATUS_PLL_ARESET_STATUS_MASK 0x00000001
-#define BCHP_CLKGEN_PLL_SC1_PLL_RESET_STATUS_PLL_ARESET_STATUS_SHIFT 0
-
-/***************************************************************************
- *PLL_SC1_RDB_MACRO_CTRL - PLL RDB Macro Disable
- ***************************************************************************/
-/* CLKGEN :: PLL_SC1_RDB_MACRO_CTRL :: reserved0 [31:05] */
-#define BCHP_CLKGEN_PLL_SC1_RDB_MACRO_CTRL_reserved0_MASK 0xffffffe0
-#define BCHP_CLKGEN_PLL_SC1_RDB_MACRO_CTRL_reserved0_SHIFT 5
-
-/* CLKGEN :: PLL_SC1_RDB_MACRO_CTRL :: PLL_SC1_OPTIONS_DISABLE_RDB_MACRO [04:04] */
-#define BCHP_CLKGEN_PLL_SC1_RDB_MACRO_CTRL_PLL_SC1_OPTIONS_DISABLE_RDB_MACRO_MASK 0x00000010
-#define BCHP_CLKGEN_PLL_SC1_RDB_MACRO_CTRL_PLL_SC1_OPTIONS_DISABLE_RDB_MACRO_SHIFT 4
-#define BCHP_CLKGEN_PLL_SC1_RDB_MACRO_CTRL_PLL_SC1_OPTIONS_DISABLE_RDB_MACRO_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_SC1_RDB_MACRO_CTRL :: OPTIONS [03:00] */
-#define BCHP_CLKGEN_PLL_SC1_RDB_MACRO_CTRL_OPTIONS_MASK 0x0000000f
-#define BCHP_CLKGEN_PLL_SC1_RDB_MACRO_CTRL_OPTIONS_SHIFT 0
-#define BCHP_CLKGEN_PLL_SC1_RDB_MACRO_CTRL_OPTIONS_DEFAULT 0x00000000
-
-/***************************************************************************
- *PLL_STRAP_OVERRIDE - Disable
- ***************************************************************************/
-/* CLKGEN :: PLL_STRAP_OVERRIDE :: reserved0 [31:02] */
-#define BCHP_CLKGEN_PLL_STRAP_OVERRIDE_reserved0_MASK 0xfffffffc
-#define BCHP_CLKGEN_PLL_STRAP_OVERRIDE_reserved0_SHIFT 2
-
-/* CLKGEN :: PLL_STRAP_OVERRIDE :: STRAP_HIFSPI_DISABLE [01:01] */
-#define BCHP_CLKGEN_PLL_STRAP_OVERRIDE_STRAP_HIFSPI_DISABLE_MASK 0x00000002
-#define BCHP_CLKGEN_PLL_STRAP_OVERRIDE_STRAP_HIFSPI_DISABLE_SHIFT 1
-#define BCHP_CLKGEN_PLL_STRAP_OVERRIDE_STRAP_HIFSPI_DISABLE_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_STRAP_OVERRIDE :: STRAP_FREQ_PLLMIPS_DISABLE [00:00] */
-#define BCHP_CLKGEN_PLL_STRAP_OVERRIDE_STRAP_FREQ_PLLMIPS_DISABLE_MASK 0x00000001
-#define BCHP_CLKGEN_PLL_STRAP_OVERRIDE_STRAP_FREQ_PLLMIPS_DISABLE_SHIFT 0
-#define BCHP_CLKGEN_PLL_STRAP_OVERRIDE_STRAP_FREQ_PLLMIPS_DISABLE_DEFAULT 0x00000000
-
-/***************************************************************************
- *PLL_SWITCH_PLL_RESET_STATUS - PLL_SWITCH Reset Status
- ***************************************************************************/
-/* CLKGEN :: PLL_SWITCH_PLL_RESET_STATUS :: reserved0 [31:02] */
-#define BCHP_CLKGEN_PLL_SWITCH_PLL_RESET_STATUS_reserved0_MASK 0xfffffffc
-#define BCHP_CLKGEN_PLL_SWITCH_PLL_RESET_STATUS_reserved0_SHIFT 2
-
-/* CLKGEN :: PLL_SWITCH_PLL_RESET_STATUS :: PLL_DRESET_STATUS [01:01] */
-#define BCHP_CLKGEN_PLL_SWITCH_PLL_RESET_STATUS_PLL_DRESET_STATUS_MASK 0x00000002
-#define BCHP_CLKGEN_PLL_SWITCH_PLL_RESET_STATUS_PLL_DRESET_STATUS_SHIFT 1
-
-/* CLKGEN :: PLL_SWITCH_PLL_RESET_STATUS :: PLL_ARESET_STATUS [00:00] */
-#define BCHP_CLKGEN_PLL_SWITCH_PLL_RESET_STATUS_PLL_ARESET_STATUS_MASK 0x00000001
-#define BCHP_CLKGEN_PLL_SWITCH_PLL_RESET_STATUS_PLL_ARESET_STATUS_SHIFT 0
-
-/***************************************************************************
- *PLL_SYS0_RDB_MACRO_CTRL - PLL RDB Macro Disable
- ***************************************************************************/
-/* CLKGEN :: PLL_SYS0_RDB_MACRO_CTRL :: reserved0 [31:03] */
-#define BCHP_CLKGEN_PLL_SYS0_RDB_MACRO_CTRL_reserved0_MASK 0xfffffff8
-#define BCHP_CLKGEN_PLL_SYS0_RDB_MACRO_CTRL_reserved0_SHIFT 3
-
-/* CLKGEN :: PLL_SYS0_RDB_MACRO_CTRL :: PLL_SYS0_CHANNEL1_FREQ_DISABLE_RDB_MACRO [02:02] */
-#define BCHP_CLKGEN_PLL_SYS0_RDB_MACRO_CTRL_PLL_SYS0_CHANNEL1_FREQ_DISABLE_RDB_MACRO_MASK 0x00000004
-#define BCHP_CLKGEN_PLL_SYS0_RDB_MACRO_CTRL_PLL_SYS0_CHANNEL1_FREQ_DISABLE_RDB_MACRO_SHIFT 2
-#define BCHP_CLKGEN_PLL_SYS0_RDB_MACRO_CTRL_PLL_SYS0_CHANNEL1_FREQ_DISABLE_RDB_MACRO_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_SYS0_RDB_MACRO_CTRL :: CHANNEL1_FREQ [01:00] */
-#define BCHP_CLKGEN_PLL_SYS0_RDB_MACRO_CTRL_CHANNEL1_FREQ_MASK 0x00000003
-#define BCHP_CLKGEN_PLL_SYS0_RDB_MACRO_CTRL_CHANNEL1_FREQ_SHIFT 0
-#define BCHP_CLKGEN_PLL_SYS0_RDB_MACRO_CTRL_CHANNEL1_FREQ_DEFAULT 0x00000000
-
-/***************************************************************************
- *PLL_VCXO0_PLL_RESET_STATUS - PLL_VCXO0 Reset Status
- ***************************************************************************/
-/* CLKGEN :: PLL_VCXO0_PLL_RESET_STATUS :: reserved0 [31:02] */
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_RESET_STATUS_reserved0_MASK 0xfffffffc
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_RESET_STATUS_reserved0_SHIFT 2
-
-/* CLKGEN :: PLL_VCXO0_PLL_RESET_STATUS :: PLL_DRESET_STATUS [01:01] */
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_RESET_STATUS_PLL_DRESET_STATUS_MASK 0x00000002
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_RESET_STATUS_PLL_DRESET_STATUS_SHIFT 1
-
-/* CLKGEN :: PLL_VCXO0_PLL_RESET_STATUS :: PLL_ARESET_STATUS [00:00] */
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_RESET_STATUS_PLL_ARESET_STATUS_MASK 0x00000001
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_RESET_STATUS_PLL_ARESET_STATUS_SHIFT 0
-
-/***************************************************************************
- *PLL_VCXO1_PLL_RESET_STATUS - PLL_VCXO1 Reset Status
- ***************************************************************************/
-/* CLKGEN :: PLL_VCXO1_PLL_RESET_STATUS :: reserved0 [31:02] */
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_RESET_STATUS_reserved0_MASK 0xfffffffc
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_RESET_STATUS_reserved0_SHIFT 2
-
-/* CLKGEN :: PLL_VCXO1_PLL_RESET_STATUS :: PLL_DRESET_STATUS [01:01] */
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_RESET_STATUS_PLL_DRESET_STATUS_MASK 0x00000002
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_RESET_STATUS_PLL_DRESET_STATUS_SHIFT 1
-
-/* CLKGEN :: PLL_VCXO1_PLL_RESET_STATUS :: PLL_ARESET_STATUS [00:00] */
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_RESET_STATUS_PLL_ARESET_STATUS_MASK 0x00000001
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_RESET_STATUS_PLL_ARESET_STATUS_SHIFT 0
-
-/***************************************************************************
- *PLL_VCXO2_PLL_RESET_STATUS - PLL_VCXO2 Reset Status
- ***************************************************************************/
-/* CLKGEN :: PLL_VCXO2_PLL_RESET_STATUS :: reserved0 [31:02] */
-#define BCHP_CLKGEN_PLL_VCXO2_PLL_RESET_STATUS_reserved0_MASK 0xfffffffc
-#define BCHP_CLKGEN_PLL_VCXO2_PLL_RESET_STATUS_reserved0_SHIFT 2
-
-/* CLKGEN :: PLL_VCXO2_PLL_RESET_STATUS :: PLL_DRESET_STATUS [01:01] */
-#define BCHP_CLKGEN_PLL_VCXO2_PLL_RESET_STATUS_PLL_DRESET_STATUS_MASK 0x00000002
-#define BCHP_CLKGEN_PLL_VCXO2_PLL_RESET_STATUS_PLL_DRESET_STATUS_SHIFT 1
-
-/* CLKGEN :: PLL_VCXO2_PLL_RESET_STATUS :: PLL_ARESET_STATUS [00:00] */
-#define BCHP_CLKGEN_PLL_VCXO2_PLL_RESET_STATUS_PLL_ARESET_STATUS_MASK 0x00000001
-#define BCHP_CLKGEN_PLL_VCXO2_PLL_RESET_STATUS_PLL_ARESET_STATUS_SHIFT 0
-
-/***************************************************************************
- *PLL_XPT_RDB_MACRO_CTRL - PLL RDB Macro Disable
- ***************************************************************************/
-/* CLKGEN :: PLL_XPT_RDB_MACRO_CTRL :: reserved0 [31:05] */
-#define BCHP_CLKGEN_PLL_XPT_RDB_MACRO_CTRL_reserved0_MASK 0xffffffe0
-#define BCHP_CLKGEN_PLL_XPT_RDB_MACRO_CTRL_reserved0_SHIFT 5
-
-/* CLKGEN :: PLL_XPT_RDB_MACRO_CTRL :: PLL_XPT_CHANNEL1_FREQ_DISABLE_RDB_MACRO [04:04] */
-#define BCHP_CLKGEN_PLL_XPT_RDB_MACRO_CTRL_PLL_XPT_CHANNEL1_FREQ_DISABLE_RDB_MACRO_MASK 0x00000010
-#define BCHP_CLKGEN_PLL_XPT_RDB_MACRO_CTRL_PLL_XPT_CHANNEL1_FREQ_DISABLE_RDB_MACRO_SHIFT 4
-#define BCHP_CLKGEN_PLL_XPT_RDB_MACRO_CTRL_PLL_XPT_CHANNEL1_FREQ_DISABLE_RDB_MACRO_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_XPT_RDB_MACRO_CTRL :: PLL_XPT_CHANNEL0_FREQ_DISABLE_RDB_MACRO [03:03] */
-#define BCHP_CLKGEN_PLL_XPT_RDB_MACRO_CTRL_PLL_XPT_CHANNEL0_FREQ_DISABLE_RDB_MACRO_MASK 0x00000008
-#define BCHP_CLKGEN_PLL_XPT_RDB_MACRO_CTRL_PLL_XPT_CHANNEL0_FREQ_DISABLE_RDB_MACRO_SHIFT 3
-#define BCHP_CLKGEN_PLL_XPT_RDB_MACRO_CTRL_PLL_XPT_CHANNEL0_FREQ_DISABLE_RDB_MACRO_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_XPT_RDB_MACRO_CTRL :: CHANNEL1_FREQ [02:02] */
-#define BCHP_CLKGEN_PLL_XPT_RDB_MACRO_CTRL_CHANNEL1_FREQ_MASK 0x00000004
-#define BCHP_CLKGEN_PLL_XPT_RDB_MACRO_CTRL_CHANNEL1_FREQ_SHIFT 2
-#define BCHP_CLKGEN_PLL_XPT_RDB_MACRO_CTRL_CHANNEL1_FREQ_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_XPT_RDB_MACRO_CTRL :: CHANNEL0_FREQ [01:00] */
-#define BCHP_CLKGEN_PLL_XPT_RDB_MACRO_CTRL_CHANNEL0_FREQ_MASK 0x00000003
-#define BCHP_CLKGEN_PLL_XPT_RDB_MACRO_CTRL_CHANNEL0_FREQ_SHIFT 0
-#define BCHP_CLKGEN_PLL_XPT_RDB_MACRO_CTRL_CHANNEL0_FREQ_DEFAULT 0x00000000
-
-/***************************************************************************
- *PM_CLOCK_Async_ALIVE_SEL - Select clocks that can stay alive during power management standby mode.
- ***************************************************************************/
-/* CLKGEN :: PM_CLOCK_Async_ALIVE_SEL :: reserved0 [31:01] */
-#define BCHP_CLKGEN_PM_CLOCK_Async_ALIVE_SEL_reserved0_MASK 0xfffffffe
-#define BCHP_CLKGEN_PM_CLOCK_Async_ALIVE_SEL_reserved0_SHIFT 1
-
-/* CLKGEN :: PM_CLOCK_Async_ALIVE_SEL :: CLOCK_Async_CG_XPT [00:00] */
-#define BCHP_CLKGEN_PM_CLOCK_Async_ALIVE_SEL_CLOCK_Async_CG_XPT_MASK 0x00000001
-#define BCHP_CLKGEN_PM_CLOCK_Async_ALIVE_SEL_CLOCK_Async_CG_XPT_SHIFT 0
-#define BCHP_CLKGEN_PM_CLOCK_Async_ALIVE_SEL_CLOCK_Async_CG_XPT_DEFAULT 0x00000000
-
-/***************************************************************************
- *PM_PLL_ALIVE_SEL - PLL Alive in Standby Mode
- ***************************************************************************/
-/* CLKGEN :: PM_PLL_ALIVE_SEL :: reserved0 [31:07] */
-#define BCHP_CLKGEN_PM_PLL_ALIVE_SEL_reserved0_MASK 0xffffff80
-#define BCHP_CLKGEN_PM_PLL_ALIVE_SEL_reserved0_SHIFT 7
-
-/* CLKGEN :: PM_PLL_ALIVE_SEL :: memsys1_PLL [06:06] */
-#define BCHP_CLKGEN_PM_PLL_ALIVE_SEL_memsys1_PLL_MASK 0x00000040
-#define BCHP_CLKGEN_PM_PLL_ALIVE_SEL_memsys1_PLL_SHIFT 6
-#define BCHP_CLKGEN_PM_PLL_ALIVE_SEL_memsys1_PLL_DEFAULT 0x00000000
-
-/* CLKGEN :: PM_PLL_ALIVE_SEL :: memsys0_PLL [05:05] */
-#define BCHP_CLKGEN_PM_PLL_ALIVE_SEL_memsys0_PLL_MASK 0x00000020
-#define BCHP_CLKGEN_PM_PLL_ALIVE_SEL_memsys0_PLL_SHIFT 5
-#define BCHP_CLKGEN_PM_PLL_ALIVE_SEL_memsys0_PLL_DEFAULT 0x00000000
-
-/* CLKGEN :: PM_PLL_ALIVE_SEL :: PLL_XPT [04:04] */
-#define BCHP_CLKGEN_PM_PLL_ALIVE_SEL_PLL_XPT_MASK 0x00000010
-#define BCHP_CLKGEN_PM_PLL_ALIVE_SEL_PLL_XPT_SHIFT 4
-#define BCHP_CLKGEN_PM_PLL_ALIVE_SEL_PLL_XPT_DEFAULT 0x00000000
-
-/* CLKGEN :: PM_PLL_ALIVE_SEL :: PLL_SYS0 [03:03] */
-#define BCHP_CLKGEN_PM_PLL_ALIVE_SEL_PLL_SYS0_MASK 0x00000008
-#define BCHP_CLKGEN_PM_PLL_ALIVE_SEL_PLL_SYS0_SHIFT 3
-#define BCHP_CLKGEN_PM_PLL_ALIVE_SEL_PLL_SYS0_DEFAULT 0x00000000
-
-/* CLKGEN :: PM_PLL_ALIVE_SEL :: PLL_CPU_CORE [02:02] */
-#define BCHP_CLKGEN_PM_PLL_ALIVE_SEL_PLL_CPU_CORE_MASK 0x00000004
-#define BCHP_CLKGEN_PM_PLL_ALIVE_SEL_PLL_CPU_CORE_SHIFT 2
-#define BCHP_CLKGEN_PM_PLL_ALIVE_SEL_PLL_CPU_CORE_DEFAULT 0x00000000
-
-/* CLKGEN :: PM_PLL_ALIVE_SEL :: DOCSIS_PLL_SYS1 [01:01] */
-#define BCHP_CLKGEN_PM_PLL_ALIVE_SEL_DOCSIS_PLL_SYS1_MASK 0x00000002
-#define BCHP_CLKGEN_PM_PLL_ALIVE_SEL_DOCSIS_PLL_SYS1_SHIFT 1
-#define BCHP_CLKGEN_PM_PLL_ALIVE_SEL_DOCSIS_PLL_SYS1_DEFAULT 0x00000000
-
-/* CLKGEN :: PM_PLL_ALIVE_SEL :: DOCSIS_PLL_SYS0 [00:00] */
-#define BCHP_CLKGEN_PM_PLL_ALIVE_SEL_DOCSIS_PLL_SYS0_MASK 0x00000001
-#define BCHP_CLKGEN_PM_PLL_ALIVE_SEL_DOCSIS_PLL_SYS0_SHIFT 0
-#define BCHP_CLKGEN_PM_PLL_ALIVE_SEL_DOCSIS_PLL_SYS0_DEFAULT 0x00000000
-
-/***************************************************************************
- *PM_PLL_LDO_POWERUP - Power management LDO PLL
- ***************************************************************************/
-/* CLKGEN :: PM_PLL_LDO_POWERUP :: reserved0 [31:15] */
-#define BCHP_CLKGEN_PM_PLL_LDO_POWERUP_reserved0_MASK 0xffff8000
-#define BCHP_CLKGEN_PM_PLL_LDO_POWERUP_reserved0_SHIFT 15
-
-/* CLKGEN :: PM_PLL_LDO_POWERUP :: ISO_CLOCK_PLL_VCXO2 [14:14] */
-#define BCHP_CLKGEN_PM_PLL_LDO_POWERUP_ISO_CLOCK_PLL_VCXO2_MASK 0x00004000
-#define BCHP_CLKGEN_PM_PLL_LDO_POWERUP_ISO_CLOCK_PLL_VCXO2_SHIFT 14
-#define BCHP_CLKGEN_PM_PLL_LDO_POWERUP_ISO_CLOCK_PLL_VCXO2_DEFAULT 0x00000001
-
-/* CLKGEN :: PM_PLL_LDO_POWERUP :: ISO_CLOCK_PLL_VCXO1 [13:13] */
-#define BCHP_CLKGEN_PM_PLL_LDO_POWERUP_ISO_CLOCK_PLL_VCXO1_MASK 0x00002000
-#define BCHP_CLKGEN_PM_PLL_LDO_POWERUP_ISO_CLOCK_PLL_VCXO1_SHIFT 13
-#define BCHP_CLKGEN_PM_PLL_LDO_POWERUP_ISO_CLOCK_PLL_VCXO1_DEFAULT 0x00000001
-
-/* CLKGEN :: PM_PLL_LDO_POWERUP :: ISO_CLOCK_PLL_VCXO0 [12:12] */
-#define BCHP_CLKGEN_PM_PLL_LDO_POWERUP_ISO_CLOCK_PLL_VCXO0_MASK 0x00001000
-#define BCHP_CLKGEN_PM_PLL_LDO_POWERUP_ISO_CLOCK_PLL_VCXO0_SHIFT 12
-#define BCHP_CLKGEN_PM_PLL_LDO_POWERUP_ISO_CLOCK_PLL_VCXO0_DEFAULT 0x00000001
-
-/* CLKGEN :: PM_PLL_LDO_POWERUP :: ISO_CLOCK_PLL_SWITCH [11:11] */
-#define BCHP_CLKGEN_PM_PLL_LDO_POWERUP_ISO_CLOCK_PLL_SWITCH_MASK 0x00000800
-#define BCHP_CLKGEN_PM_PLL_LDO_POWERUP_ISO_CLOCK_PLL_SWITCH_SHIFT 11
-#define BCHP_CLKGEN_PM_PLL_LDO_POWERUP_ISO_CLOCK_PLL_SWITCH_DEFAULT 0x00000001
-
-/* CLKGEN :: PM_PLL_LDO_POWERUP :: ISO_CLOCK_PLL_SC1 [10:10] */
-#define BCHP_CLKGEN_PM_PLL_LDO_POWERUP_ISO_CLOCK_PLL_SC1_MASK 0x00000400
-#define BCHP_CLKGEN_PM_PLL_LDO_POWERUP_ISO_CLOCK_PLL_SC1_SHIFT 10
-#define BCHP_CLKGEN_PM_PLL_LDO_POWERUP_ISO_CLOCK_PLL_SC1_DEFAULT 0x00000001
-
-/* CLKGEN :: PM_PLL_LDO_POWERUP :: ISO_CLOCK_PLL_SC0 [09:09] */
-#define BCHP_CLKGEN_PM_PLL_LDO_POWERUP_ISO_CLOCK_PLL_SC0_MASK 0x00000200
-#define BCHP_CLKGEN_PM_PLL_LDO_POWERUP_ISO_CLOCK_PLL_SC0_SHIFT 9
-#define BCHP_CLKGEN_PM_PLL_LDO_POWERUP_ISO_CLOCK_PLL_SC0_DEFAULT 0x00000001
-
-/* CLKGEN :: PM_PLL_LDO_POWERUP :: ISO_CLOCK_PLL_RAAGA [08:08] */
-#define BCHP_CLKGEN_PM_PLL_LDO_POWERUP_ISO_CLOCK_PLL_RAAGA_MASK 0x00000100
-#define BCHP_CLKGEN_PM_PLL_LDO_POWERUP_ISO_CLOCK_PLL_RAAGA_SHIFT 8
-#define BCHP_CLKGEN_PM_PLL_LDO_POWERUP_ISO_CLOCK_PLL_RAAGA_DEFAULT 0x00000001
-
-/* CLKGEN :: PM_PLL_LDO_POWERUP :: ISO_CLOCK_PLL_MOCA [07:07] */
-#define BCHP_CLKGEN_PM_PLL_LDO_POWERUP_ISO_CLOCK_PLL_MOCA_MASK 0x00000080
-#define BCHP_CLKGEN_PM_PLL_LDO_POWERUP_ISO_CLOCK_PLL_MOCA_SHIFT 7
-#define BCHP_CLKGEN_PM_PLL_LDO_POWERUP_ISO_CLOCK_PLL_MOCA_DEFAULT 0x00000001
-
-/* CLKGEN :: PM_PLL_LDO_POWERUP :: ISO_CLOCK_PLL_LC [06:06] */
-#define BCHP_CLKGEN_PM_PLL_LDO_POWERUP_ISO_CLOCK_PLL_LC_MASK 0x00000040
-#define BCHP_CLKGEN_PM_PLL_LDO_POWERUP_ISO_CLOCK_PLL_LC_SHIFT 6
-#define BCHP_CLKGEN_PM_PLL_LDO_POWERUP_ISO_CLOCK_PLL_LC_DEFAULT 0x00000001
-
-/* CLKGEN :: PM_PLL_LDO_POWERUP :: ISO_CLOCK_PLL_CPU_ROUTER [05:05] */
-#define BCHP_CLKGEN_PM_PLL_LDO_POWERUP_ISO_CLOCK_PLL_CPU_ROUTER_MASK 0x00000020
-#define BCHP_CLKGEN_PM_PLL_LDO_POWERUP_ISO_CLOCK_PLL_CPU_ROUTER_SHIFT 5
-#define BCHP_CLKGEN_PM_PLL_LDO_POWERUP_ISO_CLOCK_PLL_CPU_ROUTER_DEFAULT 0x00000001
-
-/* CLKGEN :: PM_PLL_LDO_POWERUP :: ISO_CLOCK_PLL_AVD [04:04] */
-#define BCHP_CLKGEN_PM_PLL_LDO_POWERUP_ISO_CLOCK_PLL_AVD_MASK 0x00000010
-#define BCHP_CLKGEN_PM_PLL_LDO_POWERUP_ISO_CLOCK_PLL_AVD_SHIFT 4
-#define BCHP_CLKGEN_PM_PLL_LDO_POWERUP_ISO_CLOCK_PLL_AVD_DEFAULT 0x00000001
-
-/* CLKGEN :: PM_PLL_LDO_POWERUP :: ISO_CLOCK_PLL_AUDIO2 [03:03] */
-#define BCHP_CLKGEN_PM_PLL_LDO_POWERUP_ISO_CLOCK_PLL_AUDIO2_MASK 0x00000008
-#define BCHP_CLKGEN_PM_PLL_LDO_POWERUP_ISO_CLOCK_PLL_AUDIO2_SHIFT 3
-#define BCHP_CLKGEN_PM_PLL_LDO_POWERUP_ISO_CLOCK_PLL_AUDIO2_DEFAULT 0x00000001
-
-/* CLKGEN :: PM_PLL_LDO_POWERUP :: ISO_CLOCK_PLL_AUDIO1 [02:02] */
-#define BCHP_CLKGEN_PM_PLL_LDO_POWERUP_ISO_CLOCK_PLL_AUDIO1_MASK 0x00000004
-#define BCHP_CLKGEN_PM_PLL_LDO_POWERUP_ISO_CLOCK_PLL_AUDIO1_SHIFT 2
-#define BCHP_CLKGEN_PM_PLL_LDO_POWERUP_ISO_CLOCK_PLL_AUDIO1_DEFAULT 0x00000001
-
-/* CLKGEN :: PM_PLL_LDO_POWERUP :: ISO_CLOCK_PLL_AUDIO0 [01:01] */
-#define BCHP_CLKGEN_PM_PLL_LDO_POWERUP_ISO_CLOCK_PLL_AUDIO0_MASK 0x00000002
-#define BCHP_CLKGEN_PM_PLL_LDO_POWERUP_ISO_CLOCK_PLL_AUDIO0_SHIFT 1
-#define BCHP_CLKGEN_PM_PLL_LDO_POWERUP_ISO_CLOCK_PLL_AUDIO0_DEFAULT 0x00000001
-
-/* CLKGEN :: PM_PLL_LDO_POWERUP :: ISO_CLOCK_DOCSIS_PLL_SYS2 [00:00] */
-#define BCHP_CLKGEN_PM_PLL_LDO_POWERUP_ISO_CLOCK_DOCSIS_PLL_SYS2_MASK 0x00000001
-#define BCHP_CLKGEN_PM_PLL_LDO_POWERUP_ISO_CLOCK_DOCSIS_PLL_SYS2_SHIFT 0
-#define BCHP_CLKGEN_PM_PLL_LDO_POWERUP_ISO_CLOCK_DOCSIS_PLL_SYS2_DEFAULT 0x00000001
-
-/***************************************************************************
- *PROD_OTP_INST_CLOCK_DISABLE - Disable PROD_OTP_INST's clocks
- ***************************************************************************/
-/* CLKGEN :: PROD_OTP_INST_CLOCK_DISABLE :: reserved0 [31:02] */
-#define BCHP_CLKGEN_PROD_OTP_INST_CLOCK_DISABLE_reserved0_MASK 0xfffffffc
-#define BCHP_CLKGEN_PROD_OTP_INST_CLOCK_DISABLE_reserved0_SHIFT 2
-
-/* CLKGEN :: PROD_OTP_INST_CLOCK_DISABLE :: DISABLE_POTP_JTAGOTP_CLOCK [01:01] */
-#define BCHP_CLKGEN_PROD_OTP_INST_CLOCK_DISABLE_DISABLE_POTP_JTAGOTP_CLOCK_MASK 0x00000002
-#define BCHP_CLKGEN_PROD_OTP_INST_CLOCK_DISABLE_DISABLE_POTP_JTAGOTP_CLOCK_SHIFT 1
-#define BCHP_CLKGEN_PROD_OTP_INST_CLOCK_DISABLE_DISABLE_POTP_JTAGOTP_CLOCK_DEFAULT 0x00000000
-
-/* CLKGEN :: PROD_OTP_INST_CLOCK_DISABLE :: DISABLE_POTP_ALWAYSON_CLOCK [00:00] */
-#define BCHP_CLKGEN_PROD_OTP_INST_CLOCK_DISABLE_DISABLE_POTP_ALWAYSON_CLOCK_MASK 0x00000001
-#define BCHP_CLKGEN_PROD_OTP_INST_CLOCK_DISABLE_DISABLE_POTP_ALWAYSON_CLOCK_SHIFT 0
-#define BCHP_CLKGEN_PROD_OTP_INST_CLOCK_DISABLE_DISABLE_POTP_ALWAYSON_CLOCK_DEFAULT 0x00000000
-
-/***************************************************************************
- *PROD_OTP_INST_CLOCK_DISABLE_STATUS - Clock Disable Status
- ***************************************************************************/
-/* CLKGEN :: PROD_OTP_INST_CLOCK_DISABLE_STATUS :: reserved0 [31:02] */
-#define BCHP_CLKGEN_PROD_OTP_INST_CLOCK_DISABLE_STATUS_reserved0_MASK 0xfffffffc
-#define BCHP_CLKGEN_PROD_OTP_INST_CLOCK_DISABLE_STATUS_reserved0_SHIFT 2
-
-/* CLKGEN :: PROD_OTP_INST_CLOCK_DISABLE_STATUS :: DISABLE_POTP_JTAGOTP_CLOCK_STATUS [01:01] */
-#define BCHP_CLKGEN_PROD_OTP_INST_CLOCK_DISABLE_STATUS_DISABLE_POTP_JTAGOTP_CLOCK_STATUS_MASK 0x00000002
-#define BCHP_CLKGEN_PROD_OTP_INST_CLOCK_DISABLE_STATUS_DISABLE_POTP_JTAGOTP_CLOCK_STATUS_SHIFT 1
-
-/* CLKGEN :: PROD_OTP_INST_CLOCK_DISABLE_STATUS :: DISABLE_POTP_ALWAYSON_CLOCK_STATUS [00:00] */
-#define BCHP_CLKGEN_PROD_OTP_INST_CLOCK_DISABLE_STATUS_DISABLE_POTP_ALWAYSON_CLOCK_STATUS_MASK 0x00000001
-#define BCHP_CLKGEN_PROD_OTP_INST_CLOCK_DISABLE_STATUS_DISABLE_POTP_ALWAYSON_CLOCK_STATUS_SHIFT 0
-
-/***************************************************************************
- *PROD_OTP_INST_CLOCK_ENABLE - Prod otp inst clock enable
- ***************************************************************************/
-/* CLKGEN :: PROD_OTP_INST_CLOCK_ENABLE :: reserved0 [31:02] */
-#define BCHP_CLKGEN_PROD_OTP_INST_CLOCK_ENABLE_reserved0_MASK 0xfffffffc
-#define BCHP_CLKGEN_PROD_OTP_INST_CLOCK_ENABLE_reserved0_SHIFT 2
-
-/* CLKGEN :: PROD_OTP_INST_CLOCK_ENABLE :: POTP_GISB_CLOCK_ENABLE [01:01] */
-#define BCHP_CLKGEN_PROD_OTP_INST_CLOCK_ENABLE_POTP_GISB_CLOCK_ENABLE_MASK 0x00000002
-#define BCHP_CLKGEN_PROD_OTP_INST_CLOCK_ENABLE_POTP_GISB_CLOCK_ENABLE_SHIFT 1
-#define BCHP_CLKGEN_PROD_OTP_INST_CLOCK_ENABLE_POTP_GISB_CLOCK_ENABLE_DEFAULT 0x00000001
-
-/* CLKGEN :: PROD_OTP_INST_CLOCK_ENABLE :: POTP_54_CLOCK_ENABLE [00:00] */
-#define BCHP_CLKGEN_PROD_OTP_INST_CLOCK_ENABLE_POTP_54_CLOCK_ENABLE_MASK 0x00000001
-#define BCHP_CLKGEN_PROD_OTP_INST_CLOCK_ENABLE_POTP_54_CLOCK_ENABLE_SHIFT 0
-#define BCHP_CLKGEN_PROD_OTP_INST_CLOCK_ENABLE_POTP_54_CLOCK_ENABLE_DEFAULT 0x00000001
-
-/***************************************************************************
- *PROD_OTP_INST_CLOCK_ENABLE_STATUS - Clock Enable Status
- ***************************************************************************/
-/* CLKGEN :: PROD_OTP_INST_CLOCK_ENABLE_STATUS :: reserved0 [31:02] */
-#define BCHP_CLKGEN_PROD_OTP_INST_CLOCK_ENABLE_STATUS_reserved0_MASK 0xfffffffc
-#define BCHP_CLKGEN_PROD_OTP_INST_CLOCK_ENABLE_STATUS_reserved0_SHIFT 2
-
-/* CLKGEN :: PROD_OTP_INST_CLOCK_ENABLE_STATUS :: POTP_GISB_CLOCK_ENABLE_STATUS [01:01] */
-#define BCHP_CLKGEN_PROD_OTP_INST_CLOCK_ENABLE_STATUS_POTP_GISB_CLOCK_ENABLE_STATUS_MASK 0x00000002
-#define BCHP_CLKGEN_PROD_OTP_INST_CLOCK_ENABLE_STATUS_POTP_GISB_CLOCK_ENABLE_STATUS_SHIFT 1
-
-/* CLKGEN :: PROD_OTP_INST_CLOCK_ENABLE_STATUS :: POTP_54_CLOCK_ENABLE_STATUS [00:00] */
-#define BCHP_CLKGEN_PROD_OTP_INST_CLOCK_ENABLE_STATUS_POTP_54_CLOCK_ENABLE_STATUS_MASK 0x00000001
-#define BCHP_CLKGEN_PROD_OTP_INST_CLOCK_ENABLE_STATUS_POTP_54_CLOCK_ENABLE_STATUS_SHIFT 0
-
-/***************************************************************************
- *RAAGA_DSP_TOP_0_INST_CLOCK_ENABLE - Raaga dsp top 0 inst clock enable
- ***************************************************************************/
-/* CLKGEN :: RAAGA_DSP_TOP_0_INST_CLOCK_ENABLE :: reserved0 [31:05] */
-#define BCHP_CLKGEN_RAAGA_DSP_TOP_0_INST_CLOCK_ENABLE_reserved0_MASK 0xffffffe0
-#define BCHP_CLKGEN_RAAGA_DSP_TOP_0_INST_CLOCK_ENABLE_reserved0_SHIFT 5
-
-/* CLKGEN :: RAAGA_DSP_TOP_0_INST_CLOCK_ENABLE :: RAAGA0_SCB_CLOCK_ENABLE [04:04] */
-#define BCHP_CLKGEN_RAAGA_DSP_TOP_0_INST_CLOCK_ENABLE_RAAGA0_SCB_CLOCK_ENABLE_MASK 0x00000010
-#define BCHP_CLKGEN_RAAGA_DSP_TOP_0_INST_CLOCK_ENABLE_RAAGA0_SCB_CLOCK_ENABLE_SHIFT 4
-#define BCHP_CLKGEN_RAAGA_DSP_TOP_0_INST_CLOCK_ENABLE_RAAGA0_SCB_CLOCK_ENABLE_DEFAULT 0x00000001
-
-/* CLKGEN :: RAAGA_DSP_TOP_0_INST_CLOCK_ENABLE :: RAAGA0_GISB_CLOCK_ENABLE [03:03] */
-#define BCHP_CLKGEN_RAAGA_DSP_TOP_0_INST_CLOCK_ENABLE_RAAGA0_GISB_CLOCK_ENABLE_MASK 0x00000008
-#define BCHP_CLKGEN_RAAGA_DSP_TOP_0_INST_CLOCK_ENABLE_RAAGA0_GISB_CLOCK_ENABLE_SHIFT 3
-#define BCHP_CLKGEN_RAAGA_DSP_TOP_0_INST_CLOCK_ENABLE_RAAGA0_GISB_CLOCK_ENABLE_DEFAULT 0x00000001
-
-/* CLKGEN :: RAAGA_DSP_TOP_0_INST_CLOCK_ENABLE :: RAAGA0_DSP_CLOCK_ENABLE [02:02] */
-#define BCHP_CLKGEN_RAAGA_DSP_TOP_0_INST_CLOCK_ENABLE_RAAGA0_DSP_CLOCK_ENABLE_MASK 0x00000004
-#define BCHP_CLKGEN_RAAGA_DSP_TOP_0_INST_CLOCK_ENABLE_RAAGA0_DSP_CLOCK_ENABLE_SHIFT 2
-#define BCHP_CLKGEN_RAAGA_DSP_TOP_0_INST_CLOCK_ENABLE_RAAGA0_DSP_CLOCK_ENABLE_DEFAULT 0x00000001
-
-/* CLKGEN :: RAAGA_DSP_TOP_0_INST_CLOCK_ENABLE :: RAAGA0_54_CLOCK_ENABLE [01:01] */
-#define BCHP_CLKGEN_RAAGA_DSP_TOP_0_INST_CLOCK_ENABLE_RAAGA0_54_CLOCK_ENABLE_MASK 0x00000002
-#define BCHP_CLKGEN_RAAGA_DSP_TOP_0_INST_CLOCK_ENABLE_RAAGA0_54_CLOCK_ENABLE_SHIFT 1
-#define BCHP_CLKGEN_RAAGA_DSP_TOP_0_INST_CLOCK_ENABLE_RAAGA0_54_CLOCK_ENABLE_DEFAULT 0x00000001
-
-/* CLKGEN :: RAAGA_DSP_TOP_0_INST_CLOCK_ENABLE :: RAAGA0_108_CLOCK_ENABLE [00:00] */
-#define BCHP_CLKGEN_RAAGA_DSP_TOP_0_INST_CLOCK_ENABLE_RAAGA0_108_CLOCK_ENABLE_MASK 0x00000001
-#define BCHP_CLKGEN_RAAGA_DSP_TOP_0_INST_CLOCK_ENABLE_RAAGA0_108_CLOCK_ENABLE_SHIFT 0
-#define BCHP_CLKGEN_RAAGA_DSP_TOP_0_INST_CLOCK_ENABLE_RAAGA0_108_CLOCK_ENABLE_DEFAULT 0x00000001
-
-/***************************************************************************
- *RAAGA_DSP_TOP_0_INST_CLOCK_ENABLE_STATUS - Clock Enable Status
- ***************************************************************************/
-/* CLKGEN :: RAAGA_DSP_TOP_0_INST_CLOCK_ENABLE_STATUS :: reserved0 [31:05] */
-#define BCHP_CLKGEN_RAAGA_DSP_TOP_0_INST_CLOCK_ENABLE_STATUS_reserved0_MASK 0xffffffe0
-#define BCHP_CLKGEN_RAAGA_DSP_TOP_0_INST_CLOCK_ENABLE_STATUS_reserved0_SHIFT 5
-
-/* CLKGEN :: RAAGA_DSP_TOP_0_INST_CLOCK_ENABLE_STATUS :: RAAGA0_SCB_CLOCK_ENABLE_STATUS [04:04] */
-#define BCHP_CLKGEN_RAAGA_DSP_TOP_0_INST_CLOCK_ENABLE_STATUS_RAAGA0_SCB_CLOCK_ENABLE_STATUS_MASK 0x00000010
-#define BCHP_CLKGEN_RAAGA_DSP_TOP_0_INST_CLOCK_ENABLE_STATUS_RAAGA0_SCB_CLOCK_ENABLE_STATUS_SHIFT 4
-
-/* CLKGEN :: RAAGA_DSP_TOP_0_INST_CLOCK_ENABLE_STATUS :: RAAGA0_GISB_CLOCK_ENABLE_STATUS [03:03] */
-#define BCHP_CLKGEN_RAAGA_DSP_TOP_0_INST_CLOCK_ENABLE_STATUS_RAAGA0_GISB_CLOCK_ENABLE_STATUS_MASK 0x00000008
-#define BCHP_CLKGEN_RAAGA_DSP_TOP_0_INST_CLOCK_ENABLE_STATUS_RAAGA0_GISB_CLOCK_ENABLE_STATUS_SHIFT 3
-
-/* CLKGEN :: RAAGA_DSP_TOP_0_INST_CLOCK_ENABLE_STATUS :: RAAGA0_DSP_CLOCK_ENABLE_STATUS [02:02] */
-#define BCHP_CLKGEN_RAAGA_DSP_TOP_0_INST_CLOCK_ENABLE_STATUS_RAAGA0_DSP_CLOCK_ENABLE_STATUS_MASK 0x00000004
-#define BCHP_CLKGEN_RAAGA_DSP_TOP_0_INST_CLOCK_ENABLE_STATUS_RAAGA0_DSP_CLOCK_ENABLE_STATUS_SHIFT 2
-
-/* CLKGEN :: RAAGA_DSP_TOP_0_INST_CLOCK_ENABLE_STATUS :: RAAGA0_54_CLOCK_ENABLE_STATUS [01:01] */
-#define BCHP_CLKGEN_RAAGA_DSP_TOP_0_INST_CLOCK_ENABLE_STATUS_RAAGA0_54_CLOCK_ENABLE_STATUS_MASK 0x00000002
-#define BCHP_CLKGEN_RAAGA_DSP_TOP_0_INST_CLOCK_ENABLE_STATUS_RAAGA0_54_CLOCK_ENABLE_STATUS_SHIFT 1
-
-/* CLKGEN :: RAAGA_DSP_TOP_0_INST_CLOCK_ENABLE_STATUS :: RAAGA0_108_CLOCK_ENABLE_STATUS [00:00] */
-#define BCHP_CLKGEN_RAAGA_DSP_TOP_0_INST_CLOCK_ENABLE_STATUS_RAAGA0_108_CLOCK_ENABLE_STATUS_MASK 0x00000001
-#define BCHP_CLKGEN_RAAGA_DSP_TOP_0_INST_CLOCK_ENABLE_STATUS_RAAGA0_108_CLOCK_ENABLE_STATUS_SHIFT 0
-
-/***************************************************************************
- *RAAGA_DSP_TOP_0_INST_OBSERVE_CLOCK - Raaga dsp top 0 inst observe clock
- ***************************************************************************/
-/* CLKGEN :: RAAGA_DSP_TOP_0_INST_OBSERVE_CLOCK :: reserved0 [31:02] */
-#define BCHP_CLKGEN_RAAGA_DSP_TOP_0_INST_OBSERVE_CLOCK_reserved0_MASK 0xfffffffc
-#define BCHP_CLKGEN_RAAGA_DSP_TOP_0_INST_OBSERVE_CLOCK_reserved0_SHIFT 2
-
-/* CLKGEN :: RAAGA_DSP_TOP_0_INST_OBSERVE_CLOCK :: RAAGA0_ENABLE_OBSERVE_CLOCK [01:01] */
-#define BCHP_CLKGEN_RAAGA_DSP_TOP_0_INST_OBSERVE_CLOCK_RAAGA0_ENABLE_OBSERVE_CLOCK_MASK 0x00000002
-#define BCHP_CLKGEN_RAAGA_DSP_TOP_0_INST_OBSERVE_CLOCK_RAAGA0_ENABLE_OBSERVE_CLOCK_SHIFT 1
-#define BCHP_CLKGEN_RAAGA_DSP_TOP_0_INST_OBSERVE_CLOCK_RAAGA0_ENABLE_OBSERVE_CLOCK_DEFAULT 0x00000000
-
-/* CLKGEN :: RAAGA_DSP_TOP_0_INST_OBSERVE_CLOCK :: RAAGA0_ENABLE_DIVIDER_OBSERVE_CLOCK [00:00] */
-#define BCHP_CLKGEN_RAAGA_DSP_TOP_0_INST_OBSERVE_CLOCK_RAAGA0_ENABLE_DIVIDER_OBSERVE_CLOCK_MASK 0x00000001
-#define BCHP_CLKGEN_RAAGA_DSP_TOP_0_INST_OBSERVE_CLOCK_RAAGA0_ENABLE_DIVIDER_OBSERVE_CLOCK_SHIFT 0
-#define BCHP_CLKGEN_RAAGA_DSP_TOP_0_INST_OBSERVE_CLOCK_RAAGA0_ENABLE_DIVIDER_OBSERVE_CLOCK_DEFAULT 0x00000000
-
-/***************************************************************************
- *RAAGA_DSP_TOP_1_INST_CLOCK_ENABLE - Raaga dsp top 1 inst clock enable
- ***************************************************************************/
-/* CLKGEN :: RAAGA_DSP_TOP_1_INST_CLOCK_ENABLE :: reserved0 [31:05] */
-#define BCHP_CLKGEN_RAAGA_DSP_TOP_1_INST_CLOCK_ENABLE_reserved0_MASK 0xffffffe0
-#define BCHP_CLKGEN_RAAGA_DSP_TOP_1_INST_CLOCK_ENABLE_reserved0_SHIFT 5
-
-/* CLKGEN :: RAAGA_DSP_TOP_1_INST_CLOCK_ENABLE :: RAAGA1_SCB_CLOCK_ENABLE [04:04] */
-#define BCHP_CLKGEN_RAAGA_DSP_TOP_1_INST_CLOCK_ENABLE_RAAGA1_SCB_CLOCK_ENABLE_MASK 0x00000010
-#define BCHP_CLKGEN_RAAGA_DSP_TOP_1_INST_CLOCK_ENABLE_RAAGA1_SCB_CLOCK_ENABLE_SHIFT 4
-#define BCHP_CLKGEN_RAAGA_DSP_TOP_1_INST_CLOCK_ENABLE_RAAGA1_SCB_CLOCK_ENABLE_DEFAULT 0x00000001
-
-/* CLKGEN :: RAAGA_DSP_TOP_1_INST_CLOCK_ENABLE :: RAAGA1_GISB_CLOCK_ENABLE [03:03] */
-#define BCHP_CLKGEN_RAAGA_DSP_TOP_1_INST_CLOCK_ENABLE_RAAGA1_GISB_CLOCK_ENABLE_MASK 0x00000008
-#define BCHP_CLKGEN_RAAGA_DSP_TOP_1_INST_CLOCK_ENABLE_RAAGA1_GISB_CLOCK_ENABLE_SHIFT 3
-#define BCHP_CLKGEN_RAAGA_DSP_TOP_1_INST_CLOCK_ENABLE_RAAGA1_GISB_CLOCK_ENABLE_DEFAULT 0x00000001
-
-/* CLKGEN :: RAAGA_DSP_TOP_1_INST_CLOCK_ENABLE :: RAAGA1_DSP_CLOCK_ENABLE [02:02] */
-#define BCHP_CLKGEN_RAAGA_DSP_TOP_1_INST_CLOCK_ENABLE_RAAGA1_DSP_CLOCK_ENABLE_MASK 0x00000004
-#define BCHP_CLKGEN_RAAGA_DSP_TOP_1_INST_CLOCK_ENABLE_RAAGA1_DSP_CLOCK_ENABLE_SHIFT 2
-#define BCHP_CLKGEN_RAAGA_DSP_TOP_1_INST_CLOCK_ENABLE_RAAGA1_DSP_CLOCK_ENABLE_DEFAULT 0x00000001
-
-/* CLKGEN :: RAAGA_DSP_TOP_1_INST_CLOCK_ENABLE :: RAAGA1_54_CLOCK_ENABLE [01:01] */
-#define BCHP_CLKGEN_RAAGA_DSP_TOP_1_INST_CLOCK_ENABLE_RAAGA1_54_CLOCK_ENABLE_MASK 0x00000002
-#define BCHP_CLKGEN_RAAGA_DSP_TOP_1_INST_CLOCK_ENABLE_RAAGA1_54_CLOCK_ENABLE_SHIFT 1
-#define BCHP_CLKGEN_RAAGA_DSP_TOP_1_INST_CLOCK_ENABLE_RAAGA1_54_CLOCK_ENABLE_DEFAULT 0x00000001
-
-/* CLKGEN :: RAAGA_DSP_TOP_1_INST_CLOCK_ENABLE :: RAAGA1_108_CLOCK_ENABLE [00:00] */
-#define BCHP_CLKGEN_RAAGA_DSP_TOP_1_INST_CLOCK_ENABLE_RAAGA1_108_CLOCK_ENABLE_MASK 0x00000001
-#define BCHP_CLKGEN_RAAGA_DSP_TOP_1_INST_CLOCK_ENABLE_RAAGA1_108_CLOCK_ENABLE_SHIFT 0
-#define BCHP_CLKGEN_RAAGA_DSP_TOP_1_INST_CLOCK_ENABLE_RAAGA1_108_CLOCK_ENABLE_DEFAULT 0x00000001
-
-/***************************************************************************
- *RAAGA_DSP_TOP_1_INST_CLOCK_ENABLE_STATUS - Clock Enable Status
- ***************************************************************************/
-/* CLKGEN :: RAAGA_DSP_TOP_1_INST_CLOCK_ENABLE_STATUS :: reserved0 [31:05] */
-#define BCHP_CLKGEN_RAAGA_DSP_TOP_1_INST_CLOCK_ENABLE_STATUS_reserved0_MASK 0xffffffe0
-#define BCHP_CLKGEN_RAAGA_DSP_TOP_1_INST_CLOCK_ENABLE_STATUS_reserved0_SHIFT 5
-
-/* CLKGEN :: RAAGA_DSP_TOP_1_INST_CLOCK_ENABLE_STATUS :: RAAGA1_SCB_CLOCK_ENABLE_STATUS [04:04] */
-#define BCHP_CLKGEN_RAAGA_DSP_TOP_1_INST_CLOCK_ENABLE_STATUS_RAAGA1_SCB_CLOCK_ENABLE_STATUS_MASK 0x00000010
-#define BCHP_CLKGEN_RAAGA_DSP_TOP_1_INST_CLOCK_ENABLE_STATUS_RAAGA1_SCB_CLOCK_ENABLE_STATUS_SHIFT 4
-
-/* CLKGEN :: RAAGA_DSP_TOP_1_INST_CLOCK_ENABLE_STATUS :: RAAGA1_GISB_CLOCK_ENABLE_STATUS [03:03] */
-#define BCHP_CLKGEN_RAAGA_DSP_TOP_1_INST_CLOCK_ENABLE_STATUS_RAAGA1_GISB_CLOCK_ENABLE_STATUS_MASK 0x00000008
-#define BCHP_CLKGEN_RAAGA_DSP_TOP_1_INST_CLOCK_ENABLE_STATUS_RAAGA1_GISB_CLOCK_ENABLE_STATUS_SHIFT 3
-
-/* CLKGEN :: RAAGA_DSP_TOP_1_INST_CLOCK_ENABLE_STATUS :: RAAGA1_DSP_CLOCK_ENABLE_STATUS [02:02] */
-#define BCHP_CLKGEN_RAAGA_DSP_TOP_1_INST_CLOCK_ENABLE_STATUS_RAAGA1_DSP_CLOCK_ENABLE_STATUS_MASK 0x00000004
-#define BCHP_CLKGEN_RAAGA_DSP_TOP_1_INST_CLOCK_ENABLE_STATUS_RAAGA1_DSP_CLOCK_ENABLE_STATUS_SHIFT 2
-
-/* CLKGEN :: RAAGA_DSP_TOP_1_INST_CLOCK_ENABLE_STATUS :: RAAGA1_54_CLOCK_ENABLE_STATUS [01:01] */
-#define BCHP_CLKGEN_RAAGA_DSP_TOP_1_INST_CLOCK_ENABLE_STATUS_RAAGA1_54_CLOCK_ENABLE_STATUS_MASK 0x00000002
-#define BCHP_CLKGEN_RAAGA_DSP_TOP_1_INST_CLOCK_ENABLE_STATUS_RAAGA1_54_CLOCK_ENABLE_STATUS_SHIFT 1
-
-/* CLKGEN :: RAAGA_DSP_TOP_1_INST_CLOCK_ENABLE_STATUS :: RAAGA1_108_CLOCK_ENABLE_STATUS [00:00] */
-#define BCHP_CLKGEN_RAAGA_DSP_TOP_1_INST_CLOCK_ENABLE_STATUS_RAAGA1_108_CLOCK_ENABLE_STATUS_MASK 0x00000001
-#define BCHP_CLKGEN_RAAGA_DSP_TOP_1_INST_CLOCK_ENABLE_STATUS_RAAGA1_108_CLOCK_ENABLE_STATUS_SHIFT 0
-
-/***************************************************************************
- *RAAGA_DSP_TOP_1_INST_OBSERVE_CLOCK - Raaga dsp top 1 inst observe clock
- ***************************************************************************/
-/* CLKGEN :: RAAGA_DSP_TOP_1_INST_OBSERVE_CLOCK :: reserved0 [31:02] */
-#define BCHP_CLKGEN_RAAGA_DSP_TOP_1_INST_OBSERVE_CLOCK_reserved0_MASK 0xfffffffc
-#define BCHP_CLKGEN_RAAGA_DSP_TOP_1_INST_OBSERVE_CLOCK_reserved0_SHIFT 2
-
-/* CLKGEN :: RAAGA_DSP_TOP_1_INST_OBSERVE_CLOCK :: RAAGA1_ENABLE_OBSERVE_CLOCK [01:01] */
-#define BCHP_CLKGEN_RAAGA_DSP_TOP_1_INST_OBSERVE_CLOCK_RAAGA1_ENABLE_OBSERVE_CLOCK_MASK 0x00000002
-#define BCHP_CLKGEN_RAAGA_DSP_TOP_1_INST_OBSERVE_CLOCK_RAAGA1_ENABLE_OBSERVE_CLOCK_SHIFT 1
-#define BCHP_CLKGEN_RAAGA_DSP_TOP_1_INST_OBSERVE_CLOCK_RAAGA1_ENABLE_OBSERVE_CLOCK_DEFAULT 0x00000000
-
-/* CLKGEN :: RAAGA_DSP_TOP_1_INST_OBSERVE_CLOCK :: RAAGA1_ENABLE_DIVIDER_OBSERVE_CLOCK [00:00] */
-#define BCHP_CLKGEN_RAAGA_DSP_TOP_1_INST_OBSERVE_CLOCK_RAAGA1_ENABLE_DIVIDER_OBSERVE_CLOCK_MASK 0x00000001
-#define BCHP_CLKGEN_RAAGA_DSP_TOP_1_INST_OBSERVE_CLOCK_RAAGA1_ENABLE_DIVIDER_OBSERVE_CLOCK_SHIFT 0
-#define BCHP_CLKGEN_RAAGA_DSP_TOP_1_INST_OBSERVE_CLOCK_RAAGA1_ENABLE_DIVIDER_OBSERVE_CLOCK_DEFAULT 0x00000000
-
-/***************************************************************************
- *RFM_TOP_INST_CLOCK_ENABLE - Rfm top inst clock enable
- ***************************************************************************/
-/* CLKGEN :: RFM_TOP_INST_CLOCK_ENABLE :: reserved0 [31:03] */
-#define BCHP_CLKGEN_RFM_TOP_INST_CLOCK_ENABLE_reserved0_MASK 0xfffffff8
-#define BCHP_CLKGEN_RFM_TOP_INST_CLOCK_ENABLE_reserved0_SHIFT 3
-
-/* CLKGEN :: RFM_TOP_INST_CLOCK_ENABLE :: RFM_GISB_CLOCK_ENABLE [02:02] */
-#define BCHP_CLKGEN_RFM_TOP_INST_CLOCK_ENABLE_RFM_GISB_CLOCK_ENABLE_MASK 0x00000004
-#define BCHP_CLKGEN_RFM_TOP_INST_CLOCK_ENABLE_RFM_GISB_CLOCK_ENABLE_SHIFT 2
-#define BCHP_CLKGEN_RFM_TOP_INST_CLOCK_ENABLE_RFM_GISB_CLOCK_ENABLE_DEFAULT 0x00000001
-
-/* CLKGEN :: RFM_TOP_INST_CLOCK_ENABLE :: RFM_54_CLOCK_ENABLE [01:01] */
-#define BCHP_CLKGEN_RFM_TOP_INST_CLOCK_ENABLE_RFM_54_CLOCK_ENABLE_MASK 0x00000002
-#define BCHP_CLKGEN_RFM_TOP_INST_CLOCK_ENABLE_RFM_54_CLOCK_ENABLE_SHIFT 1
-#define BCHP_CLKGEN_RFM_TOP_INST_CLOCK_ENABLE_RFM_54_CLOCK_ENABLE_DEFAULT 0x00000001
-
-/* CLKGEN :: RFM_TOP_INST_CLOCK_ENABLE :: RFM_108_CLOCK_ENABLE [00:00] */
-#define BCHP_CLKGEN_RFM_TOP_INST_CLOCK_ENABLE_RFM_108_CLOCK_ENABLE_MASK 0x00000001
-#define BCHP_CLKGEN_RFM_TOP_INST_CLOCK_ENABLE_RFM_108_CLOCK_ENABLE_SHIFT 0
-#define BCHP_CLKGEN_RFM_TOP_INST_CLOCK_ENABLE_RFM_108_CLOCK_ENABLE_DEFAULT 0x00000001
-
-/***************************************************************************
- *RFM_TOP_INST_CLOCK_ENABLE_STATUS - Clock Enable Status
- ***************************************************************************/
-/* CLKGEN :: RFM_TOP_INST_CLOCK_ENABLE_STATUS :: reserved0 [31:03] */
-#define BCHP_CLKGEN_RFM_TOP_INST_CLOCK_ENABLE_STATUS_reserved0_MASK 0xfffffff8
-#define BCHP_CLKGEN_RFM_TOP_INST_CLOCK_ENABLE_STATUS_reserved0_SHIFT 3
-
-/* CLKGEN :: RFM_TOP_INST_CLOCK_ENABLE_STATUS :: RFM_GISB_CLOCK_ENABLE_STATUS [02:02] */
-#define BCHP_CLKGEN_RFM_TOP_INST_CLOCK_ENABLE_STATUS_RFM_GISB_CLOCK_ENABLE_STATUS_MASK 0x00000004
-#define BCHP_CLKGEN_RFM_TOP_INST_CLOCK_ENABLE_STATUS_RFM_GISB_CLOCK_ENABLE_STATUS_SHIFT 2
-
-/* CLKGEN :: RFM_TOP_INST_CLOCK_ENABLE_STATUS :: RFM_54_CLOCK_ENABLE_STATUS [01:01] */
-#define BCHP_CLKGEN_RFM_TOP_INST_CLOCK_ENABLE_STATUS_RFM_54_CLOCK_ENABLE_STATUS_MASK 0x00000002
-#define BCHP_CLKGEN_RFM_TOP_INST_CLOCK_ENABLE_STATUS_RFM_54_CLOCK_ENABLE_STATUS_SHIFT 1
-
-/* CLKGEN :: RFM_TOP_INST_CLOCK_ENABLE_STATUS :: RFM_108_CLOCK_ENABLE_STATUS [00:00] */
-#define BCHP_CLKGEN_RFM_TOP_INST_CLOCK_ENABLE_STATUS_RFM_108_CLOCK_ENABLE_STATUS_MASK 0x00000001
-#define BCHP_CLKGEN_RFM_TOP_INST_CLOCK_ENABLE_STATUS_RFM_108_CLOCK_ENABLE_STATUS_SHIFT 0
-
-/***************************************************************************
- *RFM_TOP_INST_OBSERVE_CLOCK - Rfm top inst observe clock
- ***************************************************************************/
-/* CLKGEN :: RFM_TOP_INST_OBSERVE_CLOCK :: reserved0 [31:06] */
-#define BCHP_CLKGEN_RFM_TOP_INST_OBSERVE_CLOCK_reserved0_MASK 0xffffffc0
-#define BCHP_CLKGEN_RFM_TOP_INST_OBSERVE_CLOCK_reserved0_SHIFT 6
-
-/* CLKGEN :: RFM_TOP_INST_OBSERVE_CLOCK :: RFM_ENABLE_OBSERVE_CLOCK [05:05] */
-#define BCHP_CLKGEN_RFM_TOP_INST_OBSERVE_CLOCK_RFM_ENABLE_OBSERVE_CLOCK_MASK 0x00000020
-#define BCHP_CLKGEN_RFM_TOP_INST_OBSERVE_CLOCK_RFM_ENABLE_OBSERVE_CLOCK_SHIFT 5
-#define BCHP_CLKGEN_RFM_TOP_INST_OBSERVE_CLOCK_RFM_ENABLE_OBSERVE_CLOCK_DEFAULT 0x00000000
-
-/* CLKGEN :: RFM_TOP_INST_OBSERVE_CLOCK :: RFM_ENABLE_DIVIDER_OBSERVE_CLOCK [04:04] */
-#define BCHP_CLKGEN_RFM_TOP_INST_OBSERVE_CLOCK_RFM_ENABLE_DIVIDER_OBSERVE_CLOCK_MASK 0x00000010
-#define BCHP_CLKGEN_RFM_TOP_INST_OBSERVE_CLOCK_RFM_ENABLE_DIVIDER_OBSERVE_CLOCK_SHIFT 4
-#define BCHP_CLKGEN_RFM_TOP_INST_OBSERVE_CLOCK_RFM_ENABLE_DIVIDER_OBSERVE_CLOCK_DEFAULT 0x00000000
-
-/* CLKGEN :: RFM_TOP_INST_OBSERVE_CLOCK :: RFM_CONTROL_OBSERVE_CLOCK [03:00] */
-#define BCHP_CLKGEN_RFM_TOP_INST_OBSERVE_CLOCK_RFM_CONTROL_OBSERVE_CLOCK_MASK 0x0000000f
-#define BCHP_CLKGEN_RFM_TOP_INST_OBSERVE_CLOCK_RFM_CONTROL_OBSERVE_CLOCK_SHIFT 0
-#define BCHP_CLKGEN_RFM_TOP_INST_OBSERVE_CLOCK_RFM_CONTROL_OBSERVE_CLOCK_DEFAULT 0x00000000
-
-/***************************************************************************
- *SATA3_TOP_INST_CLOCK_DISABLE - Disable SATA3_TOP_INST's clocks
- ***************************************************************************/
-/* CLKGEN :: SATA3_TOP_INST_CLOCK_DISABLE :: reserved0 [31:01] */
-#define BCHP_CLKGEN_SATA3_TOP_INST_CLOCK_DISABLE_reserved0_MASK 0xfffffffe
-#define BCHP_CLKGEN_SATA3_TOP_INST_CLOCK_DISABLE_reserved0_SHIFT 1
-
-/* CLKGEN :: SATA3_TOP_INST_CLOCK_DISABLE :: DISABLE_SATA3_AT_SPEED_SCAN_CLOCK [00:00] */
-#define BCHP_CLKGEN_SATA3_TOP_INST_CLOCK_DISABLE_DISABLE_SATA3_AT_SPEED_SCAN_CLOCK_MASK 0x00000001
-#define BCHP_CLKGEN_SATA3_TOP_INST_CLOCK_DISABLE_DISABLE_SATA3_AT_SPEED_SCAN_CLOCK_SHIFT 0
-#define BCHP_CLKGEN_SATA3_TOP_INST_CLOCK_DISABLE_DISABLE_SATA3_AT_SPEED_SCAN_CLOCK_DEFAULT 0x00000000
-
-/***************************************************************************
- *SATA3_TOP_INST_CLOCK_DISABLE_STATUS - Clock Disable Status
- ***************************************************************************/
-/* CLKGEN :: SATA3_TOP_INST_CLOCK_DISABLE_STATUS :: reserved0 [31:01] */
-#define BCHP_CLKGEN_SATA3_TOP_INST_CLOCK_DISABLE_STATUS_reserved0_MASK 0xfffffffe
-#define BCHP_CLKGEN_SATA3_TOP_INST_CLOCK_DISABLE_STATUS_reserved0_SHIFT 1
-
-/* CLKGEN :: SATA3_TOP_INST_CLOCK_DISABLE_STATUS :: DISABLE_SATA3_AT_SPEED_SCAN_CLOCK_STATUS [00:00] */
-#define BCHP_CLKGEN_SATA3_TOP_INST_CLOCK_DISABLE_STATUS_DISABLE_SATA3_AT_SPEED_SCAN_CLOCK_STATUS_MASK 0x00000001
-#define BCHP_CLKGEN_SATA3_TOP_INST_CLOCK_DISABLE_STATUS_DISABLE_SATA3_AT_SPEED_SCAN_CLOCK_STATUS_SHIFT 0
-
-/***************************************************************************
- *SATA3_TOP_INST_CLOCK_ENABLE - Sata3 top inst clock enable
- ***************************************************************************/
-/* CLKGEN :: SATA3_TOP_INST_CLOCK_ENABLE :: reserved0 [31:03] */
-#define BCHP_CLKGEN_SATA3_TOP_INST_CLOCK_ENABLE_reserved0_MASK 0xfffffff8
-#define BCHP_CLKGEN_SATA3_TOP_INST_CLOCK_ENABLE_reserved0_SHIFT 3
-
-/* CLKGEN :: SATA3_TOP_INST_CLOCK_ENABLE :: SATA3_SCB_CLOCK_ENABLE [02:02] */
-#define BCHP_CLKGEN_SATA3_TOP_INST_CLOCK_ENABLE_SATA3_SCB_CLOCK_ENABLE_MASK 0x00000004
-#define BCHP_CLKGEN_SATA3_TOP_INST_CLOCK_ENABLE_SATA3_SCB_CLOCK_ENABLE_SHIFT 2
-#define BCHP_CLKGEN_SATA3_TOP_INST_CLOCK_ENABLE_SATA3_SCB_CLOCK_ENABLE_DEFAULT 0x00000001
-
-/* CLKGEN :: SATA3_TOP_INST_CLOCK_ENABLE :: SATA3_GISB_CLOCK_ENABLE [01:01] */
-#define BCHP_CLKGEN_SATA3_TOP_INST_CLOCK_ENABLE_SATA3_GISB_CLOCK_ENABLE_MASK 0x00000002
-#define BCHP_CLKGEN_SATA3_TOP_INST_CLOCK_ENABLE_SATA3_GISB_CLOCK_ENABLE_SHIFT 1
-#define BCHP_CLKGEN_SATA3_TOP_INST_CLOCK_ENABLE_SATA3_GISB_CLOCK_ENABLE_DEFAULT 0x00000001
-
-/* CLKGEN :: SATA3_TOP_INST_CLOCK_ENABLE :: SATA3_54_CLOCK_ENABLE [00:00] */
-#define BCHP_CLKGEN_SATA3_TOP_INST_CLOCK_ENABLE_SATA3_54_CLOCK_ENABLE_MASK 0x00000001
-#define BCHP_CLKGEN_SATA3_TOP_INST_CLOCK_ENABLE_SATA3_54_CLOCK_ENABLE_SHIFT 0
-#define BCHP_CLKGEN_SATA3_TOP_INST_CLOCK_ENABLE_SATA3_54_CLOCK_ENABLE_DEFAULT 0x00000001
-
-/***************************************************************************
- *SATA3_TOP_INST_CLOCK_ENABLE_STATUS - Clock Enable Status
- ***************************************************************************/
-/* CLKGEN :: SATA3_TOP_INST_CLOCK_ENABLE_STATUS :: reserved0 [31:03] */
-#define BCHP_CLKGEN_SATA3_TOP_INST_CLOCK_ENABLE_STATUS_reserved0_MASK 0xfffffff8
-#define BCHP_CLKGEN_SATA3_TOP_INST_CLOCK_ENABLE_STATUS_reserved0_SHIFT 3
-
-/* CLKGEN :: SATA3_TOP_INST_CLOCK_ENABLE_STATUS :: SATA3_SCB_CLOCK_ENABLE_STATUS [02:02] */
-#define BCHP_CLKGEN_SATA3_TOP_INST_CLOCK_ENABLE_STATUS_SATA3_SCB_CLOCK_ENABLE_STATUS_MASK 0x00000004
-#define BCHP_CLKGEN_SATA3_TOP_INST_CLOCK_ENABLE_STATUS_SATA3_SCB_CLOCK_ENABLE_STATUS_SHIFT 2
-
-/* CLKGEN :: SATA3_TOP_INST_CLOCK_ENABLE_STATUS :: SATA3_GISB_CLOCK_ENABLE_STATUS [01:01] */
-#define BCHP_CLKGEN_SATA3_TOP_INST_CLOCK_ENABLE_STATUS_SATA3_GISB_CLOCK_ENABLE_STATUS_MASK 0x00000002
-#define BCHP_CLKGEN_SATA3_TOP_INST_CLOCK_ENABLE_STATUS_SATA3_GISB_CLOCK_ENABLE_STATUS_SHIFT 1
-
-/* CLKGEN :: SATA3_TOP_INST_CLOCK_ENABLE_STATUS :: SATA3_54_CLOCK_ENABLE_STATUS [00:00] */
-#define BCHP_CLKGEN_SATA3_TOP_INST_CLOCK_ENABLE_STATUS_SATA3_54_CLOCK_ENABLE_STATUS_MASK 0x00000001
-#define BCHP_CLKGEN_SATA3_TOP_INST_CLOCK_ENABLE_STATUS_SATA3_54_CLOCK_ENABLE_STATUS_SHIFT 0
-
-/***************************************************************************
- *SATA3_TOP_INST_CLOCK_SELECT - Sata3 top inst clock select
- ***************************************************************************/
-/* CLKGEN :: SATA3_TOP_INST_CLOCK_SELECT :: reserved0 [31:03] */
-#define BCHP_CLKGEN_SATA3_TOP_INST_CLOCK_SELECT_reserved0_MASK 0xfffffff8
-#define BCHP_CLKGEN_SATA3_TOP_INST_CLOCK_SELECT_reserved0_SHIFT 3
-
-/* CLKGEN :: SATA3_TOP_INST_CLOCK_SELECT :: SATA3_REF_CLOCK_SELECT [02:00] */
-#define BCHP_CLKGEN_SATA3_TOP_INST_CLOCK_SELECT_SATA3_REF_CLOCK_SELECT_MASK 0x00000007
-#define BCHP_CLKGEN_SATA3_TOP_INST_CLOCK_SELECT_SATA3_REF_CLOCK_SELECT_SHIFT 0
-#define BCHP_CLKGEN_SATA3_TOP_INST_CLOCK_SELECT_SATA3_REF_CLOCK_SELECT_DEFAULT 0x00000000
-
-/***************************************************************************
- *SATA3_TOP_INST_OBSERVE_CLOCK - Sata3 top inst observe clock
- ***************************************************************************/
-/* CLKGEN :: SATA3_TOP_INST_OBSERVE_CLOCK :: reserved0 [31:06] */
-#define BCHP_CLKGEN_SATA3_TOP_INST_OBSERVE_CLOCK_reserved0_MASK 0xffffffc0
-#define BCHP_CLKGEN_SATA3_TOP_INST_OBSERVE_CLOCK_reserved0_SHIFT 6
-
-/* CLKGEN :: SATA3_TOP_INST_OBSERVE_CLOCK :: SATA3_ENABLE_OBSERVE_CLOCK [05:05] */
-#define BCHP_CLKGEN_SATA3_TOP_INST_OBSERVE_CLOCK_SATA3_ENABLE_OBSERVE_CLOCK_MASK 0x00000020
-#define BCHP_CLKGEN_SATA3_TOP_INST_OBSERVE_CLOCK_SATA3_ENABLE_OBSERVE_CLOCK_SHIFT 5
-#define BCHP_CLKGEN_SATA3_TOP_INST_OBSERVE_CLOCK_SATA3_ENABLE_OBSERVE_CLOCK_DEFAULT 0x00000000
-
-/* CLKGEN :: SATA3_TOP_INST_OBSERVE_CLOCK :: SATA3_ENABLE_DIVIDER_OBSERVE_CLOCK [04:04] */
-#define BCHP_CLKGEN_SATA3_TOP_INST_OBSERVE_CLOCK_SATA3_ENABLE_DIVIDER_OBSERVE_CLOCK_MASK 0x00000010
-#define BCHP_CLKGEN_SATA3_TOP_INST_OBSERVE_CLOCK_SATA3_ENABLE_DIVIDER_OBSERVE_CLOCK_SHIFT 4
-#define BCHP_CLKGEN_SATA3_TOP_INST_OBSERVE_CLOCK_SATA3_ENABLE_DIVIDER_OBSERVE_CLOCK_DEFAULT 0x00000000
-
-/* CLKGEN :: SATA3_TOP_INST_OBSERVE_CLOCK :: SATA3_CONTROL_OBSERVE_CLOCK [03:00] */
-#define BCHP_CLKGEN_SATA3_TOP_INST_OBSERVE_CLOCK_SATA3_CONTROL_OBSERVE_CLOCK_MASK 0x0000000f
-#define BCHP_CLKGEN_SATA3_TOP_INST_OBSERVE_CLOCK_SATA3_CONTROL_OBSERVE_CLOCK_SHIFT 0
-#define BCHP_CLKGEN_SATA3_TOP_INST_OBSERVE_CLOCK_SATA3_CONTROL_OBSERVE_CLOCK_DEFAULT 0x00000000
-
-/***************************************************************************
- *SECTOP_INST_CLOCK_ENABLE - Sectop inst clock enable
- ***************************************************************************/
-/* CLKGEN :: SECTOP_INST_CLOCK_ENABLE :: reserved0 [31:02] */
-#define BCHP_CLKGEN_SECTOP_INST_CLOCK_ENABLE_reserved0_MASK 0xfffffffc
-#define BCHP_CLKGEN_SECTOP_INST_CLOCK_ENABLE_reserved0_SHIFT 2
-
-/* CLKGEN :: SECTOP_INST_CLOCK_ENABLE :: SECTOP_54_CLOCK_ENABLE [01:01] */
-#define BCHP_CLKGEN_SECTOP_INST_CLOCK_ENABLE_SECTOP_54_CLOCK_ENABLE_MASK 0x00000002
-#define BCHP_CLKGEN_SECTOP_INST_CLOCK_ENABLE_SECTOP_54_CLOCK_ENABLE_SHIFT 1
-#define BCHP_CLKGEN_SECTOP_INST_CLOCK_ENABLE_SECTOP_54_CLOCK_ENABLE_DEFAULT 0x00000001
-
-/* CLKGEN :: SECTOP_INST_CLOCK_ENABLE :: SECTOP_27_CLOCK_ENABLE [00:00] */
-#define BCHP_CLKGEN_SECTOP_INST_CLOCK_ENABLE_SECTOP_27_CLOCK_ENABLE_MASK 0x00000001
-#define BCHP_CLKGEN_SECTOP_INST_CLOCK_ENABLE_SECTOP_27_CLOCK_ENABLE_SHIFT 0
-#define BCHP_CLKGEN_SECTOP_INST_CLOCK_ENABLE_SECTOP_27_CLOCK_ENABLE_DEFAULT 0x00000001
-
-/***************************************************************************
- *SECTOP_INST_CLOCK_ENABLE_STATUS - Clock Enable Status
- ***************************************************************************/
-/* CLKGEN :: SECTOP_INST_CLOCK_ENABLE_STATUS :: reserved0 [31:02] */
-#define BCHP_CLKGEN_SECTOP_INST_CLOCK_ENABLE_STATUS_reserved0_MASK 0xfffffffc
-#define BCHP_CLKGEN_SECTOP_INST_CLOCK_ENABLE_STATUS_reserved0_SHIFT 2
-
-/* CLKGEN :: SECTOP_INST_CLOCK_ENABLE_STATUS :: SECTOP_54_CLOCK_ENABLE_STATUS [01:01] */
-#define BCHP_CLKGEN_SECTOP_INST_CLOCK_ENABLE_STATUS_SECTOP_54_CLOCK_ENABLE_STATUS_MASK 0x00000002
-#define BCHP_CLKGEN_SECTOP_INST_CLOCK_ENABLE_STATUS_SECTOP_54_CLOCK_ENABLE_STATUS_SHIFT 1
-
-/* CLKGEN :: SECTOP_INST_CLOCK_ENABLE_STATUS :: SECTOP_27_CLOCK_ENABLE_STATUS [00:00] */
-#define BCHP_CLKGEN_SECTOP_INST_CLOCK_ENABLE_STATUS_SECTOP_27_CLOCK_ENABLE_STATUS_MASK 0x00000001
-#define BCHP_CLKGEN_SECTOP_INST_CLOCK_ENABLE_STATUS_SECTOP_27_CLOCK_ENABLE_STATUS_SHIFT 0
-
-/***************************************************************************
- *SECTOP_INST_OBSERVE_CLOCK - Sectop inst observe clock
- ***************************************************************************/
-/* CLKGEN :: SECTOP_INST_OBSERVE_CLOCK :: reserved0 [31:06] */
-#define BCHP_CLKGEN_SECTOP_INST_OBSERVE_CLOCK_reserved0_MASK 0xffffffc0
-#define BCHP_CLKGEN_SECTOP_INST_OBSERVE_CLOCK_reserved0_SHIFT 6
-
-/* CLKGEN :: SECTOP_INST_OBSERVE_CLOCK :: SECTOP_ENABLE_OBSERVE_CLOCK [05:05] */
-#define BCHP_CLKGEN_SECTOP_INST_OBSERVE_CLOCK_SECTOP_ENABLE_OBSERVE_CLOCK_MASK 0x00000020
-#define BCHP_CLKGEN_SECTOP_INST_OBSERVE_CLOCK_SECTOP_ENABLE_OBSERVE_CLOCK_SHIFT 5
-#define BCHP_CLKGEN_SECTOP_INST_OBSERVE_CLOCK_SECTOP_ENABLE_OBSERVE_CLOCK_DEFAULT 0x00000000
-
-/* CLKGEN :: SECTOP_INST_OBSERVE_CLOCK :: SECTOP_ENABLE_DIVIDER_OBSERVE_CLOCK [04:04] */
-#define BCHP_CLKGEN_SECTOP_INST_OBSERVE_CLOCK_SECTOP_ENABLE_DIVIDER_OBSERVE_CLOCK_MASK 0x00000010
-#define BCHP_CLKGEN_SECTOP_INST_OBSERVE_CLOCK_SECTOP_ENABLE_DIVIDER_OBSERVE_CLOCK_SHIFT 4
-#define BCHP_CLKGEN_SECTOP_INST_OBSERVE_CLOCK_SECTOP_ENABLE_DIVIDER_OBSERVE_CLOCK_DEFAULT 0x00000000
-
-/* CLKGEN :: SECTOP_INST_OBSERVE_CLOCK :: SECTOP_CONTROL_OBSERVE_CLOCK [03:00] */
-#define BCHP_CLKGEN_SECTOP_INST_OBSERVE_CLOCK_SECTOP_CONTROL_OBSERVE_CLOCK_MASK 0x0000000f
-#define BCHP_CLKGEN_SECTOP_INST_OBSERVE_CLOCK_SECTOP_CONTROL_OBSERVE_CLOCK_SHIFT 0
-#define BCHP_CLKGEN_SECTOP_INST_OBSERVE_CLOCK_SECTOP_CONTROL_OBSERVE_CLOCK_DEFAULT 0x00000000
-
-/***************************************************************************
- *SMARTCARD_MUX_SELECT - Mux selects for Smartcard clocks
- ***************************************************************************/
-/* CLKGEN :: SMARTCARD_MUX_SELECT :: reserved0 [31:02] */
-#define BCHP_CLKGEN_SMARTCARD_MUX_SELECT_reserved0_MASK 0xfffffffc
-#define BCHP_CLKGEN_SMARTCARD_MUX_SELECT_reserved0_SHIFT 2
-
-/* CLKGEN :: SMARTCARD_MUX_SELECT :: SC1_CLOCK [01:01] */
-#define BCHP_CLKGEN_SMARTCARD_MUX_SELECT_SC1_CLOCK_MASK 0x00000002
-#define BCHP_CLKGEN_SMARTCARD_MUX_SELECT_SC1_CLOCK_SHIFT 1
-#define BCHP_CLKGEN_SMARTCARD_MUX_SELECT_SC1_CLOCK_DEFAULT 0x00000000
-
-/* CLKGEN :: SMARTCARD_MUX_SELECT :: SC0_CLOCK [00:00] */
-#define BCHP_CLKGEN_SMARTCARD_MUX_SELECT_SC0_CLOCK_MASK 0x00000001
-#define BCHP_CLKGEN_SMARTCARD_MUX_SELECT_SC0_CLOCK_SHIFT 0
-#define BCHP_CLKGEN_SMARTCARD_MUX_SELECT_SC0_CLOCK_DEFAULT 0x00000000
-
-/***************************************************************************
- *SPARE - Spares
- ***************************************************************************/
-/* CLKGEN :: SPARE :: SPARE_RESET_LOW [31:12] */
-#define BCHP_CLKGEN_SPARE_SPARE_RESET_LOW_MASK 0xfffff000
-#define BCHP_CLKGEN_SPARE_SPARE_RESET_LOW_SHIFT 12
-#define BCHP_CLKGEN_SPARE_SPARE_RESET_LOW_DEFAULT 0x00000000
-
-/* CLKGEN :: SPARE :: SPARE_RESET_HIGH [11:00] */
-#define BCHP_CLKGEN_SPARE_SPARE_RESET_HIGH_MASK 0x00000fff
-#define BCHP_CLKGEN_SPARE_SPARE_RESET_HIGH_SHIFT 0
-#define BCHP_CLKGEN_SPARE_SPARE_RESET_HIGH_DEFAULT 0x00000000
-
-/***************************************************************************
- *SWITCH_TOP_INST_CLOCK_DISABLE - Disable SWITCH_TOP_INST's clocks
- ***************************************************************************/
-/* CLKGEN :: SWITCH_TOP_INST_CLOCK_DISABLE :: reserved0 [31:03] */
-#define BCHP_CLKGEN_SWITCH_TOP_INST_CLOCK_DISABLE_reserved0_MASK 0xfffffff8
-#define BCHP_CLKGEN_SWITCH_TOP_INST_CLOCK_DISABLE_reserved0_SHIFT 3
-
-/* CLKGEN :: SWITCH_TOP_INST_CLOCK_DISABLE :: DISABLE_EGPHY_25_CLOCK [02:02] */
-#define BCHP_CLKGEN_SWITCH_TOP_INST_CLOCK_DISABLE_DISABLE_EGPHY_25_CLOCK_MASK 0x00000004
-#define BCHP_CLKGEN_SWITCH_TOP_INST_CLOCK_DISABLE_DISABLE_EGPHY_25_CLOCK_SHIFT 2
-#define BCHP_CLKGEN_SWITCH_TOP_INST_CLOCK_DISABLE_DISABLE_EGPHY_25_CLOCK_DEFAULT 0x00000000
-
-/* CLKGEN :: SWITCH_TOP_INST_CLOCK_DISABLE :: DISABLE_EGPHY_200_CLOCK [01:01] */
-#define BCHP_CLKGEN_SWITCH_TOP_INST_CLOCK_DISABLE_DISABLE_EGPHY_200_CLOCK_MASK 0x00000002
-#define BCHP_CLKGEN_SWITCH_TOP_INST_CLOCK_DISABLE_DISABLE_EGPHY_200_CLOCK_SHIFT 1
-#define BCHP_CLKGEN_SWITCH_TOP_INST_CLOCK_DISABLE_DISABLE_EGPHY_200_CLOCK_DEFAULT 0x00000000
-
-/* CLKGEN :: SWITCH_TOP_INST_CLOCK_DISABLE :: DISABLE_EGPHY_125_CLOCK [00:00] */
-#define BCHP_CLKGEN_SWITCH_TOP_INST_CLOCK_DISABLE_DISABLE_EGPHY_125_CLOCK_MASK 0x00000001
-#define BCHP_CLKGEN_SWITCH_TOP_INST_CLOCK_DISABLE_DISABLE_EGPHY_125_CLOCK_SHIFT 0
-#define BCHP_CLKGEN_SWITCH_TOP_INST_CLOCK_DISABLE_DISABLE_EGPHY_125_CLOCK_DEFAULT 0x00000000
-
-/***************************************************************************
- *SWITCH_TOP_INST_CLOCK_DISABLE_STATUS - Clock Disable Status
- ***************************************************************************/
-/* CLKGEN :: SWITCH_TOP_INST_CLOCK_DISABLE_STATUS :: reserved0 [31:03] */
-#define BCHP_CLKGEN_SWITCH_TOP_INST_CLOCK_DISABLE_STATUS_reserved0_MASK 0xfffffff8
-#define BCHP_CLKGEN_SWITCH_TOP_INST_CLOCK_DISABLE_STATUS_reserved0_SHIFT 3
-
-/* CLKGEN :: SWITCH_TOP_INST_CLOCK_DISABLE_STATUS :: DISABLE_EGPHY_25_CLOCK_STATUS [02:02] */
-#define BCHP_CLKGEN_SWITCH_TOP_INST_CLOCK_DISABLE_STATUS_DISABLE_EGPHY_25_CLOCK_STATUS_MASK 0x00000004
-#define BCHP_CLKGEN_SWITCH_TOP_INST_CLOCK_DISABLE_STATUS_DISABLE_EGPHY_25_CLOCK_STATUS_SHIFT 2
-
-/* CLKGEN :: SWITCH_TOP_INST_CLOCK_DISABLE_STATUS :: DISABLE_EGPHY_200_CLOCK_STATUS [01:01] */
-#define BCHP_CLKGEN_SWITCH_TOP_INST_CLOCK_DISABLE_STATUS_DISABLE_EGPHY_200_CLOCK_STATUS_MASK 0x00000002
-#define BCHP_CLKGEN_SWITCH_TOP_INST_CLOCK_DISABLE_STATUS_DISABLE_EGPHY_200_CLOCK_STATUS_SHIFT 1
-
-/* CLKGEN :: SWITCH_TOP_INST_CLOCK_DISABLE_STATUS :: DISABLE_EGPHY_125_CLOCK_STATUS [00:00] */
-#define BCHP_CLKGEN_SWITCH_TOP_INST_CLOCK_DISABLE_STATUS_DISABLE_EGPHY_125_CLOCK_STATUS_MASK 0x00000001
-#define BCHP_CLKGEN_SWITCH_TOP_INST_CLOCK_DISABLE_STATUS_DISABLE_EGPHY_125_CLOCK_STATUS_SHIFT 0
-
-/***************************************************************************
- *SWITCH_TOP_INST_CLOCK_ENABLE - Switch top inst clock enable
- ***************************************************************************/
-/* CLKGEN :: SWITCH_TOP_INST_CLOCK_ENABLE :: reserved0 [31:06] */
-#define BCHP_CLKGEN_SWITCH_TOP_INST_CLOCK_ENABLE_reserved0_MASK 0xffffffc0
-#define BCHP_CLKGEN_SWITCH_TOP_INST_CLOCK_ENABLE_reserved0_SHIFT 6
-
-/* CLKGEN :: SWITCH_TOP_INST_CLOCK_ENABLE :: SWCH_SYS_CLOCK_ENABLE [05:05] */
-#define BCHP_CLKGEN_SWITCH_TOP_INST_CLOCK_ENABLE_SWCH_SYS_CLOCK_ENABLE_MASK 0x00000020
-#define BCHP_CLKGEN_SWITCH_TOP_INST_CLOCK_ENABLE_SWCH_SYS_CLOCK_ENABLE_SHIFT 5
-#define BCHP_CLKGEN_SWITCH_TOP_INST_CLOCK_ENABLE_SWCH_SYS_CLOCK_ENABLE_DEFAULT 0x00000001
-
-/* CLKGEN :: SWITCH_TOP_INST_CLOCK_ENABLE :: SWCH_SCB_CLOCK_ENABLE [04:04] */
-#define BCHP_CLKGEN_SWITCH_TOP_INST_CLOCK_ENABLE_SWCH_SCB_CLOCK_ENABLE_MASK 0x00000010
-#define BCHP_CLKGEN_SWITCH_TOP_INST_CLOCK_ENABLE_SWCH_SCB_CLOCK_ENABLE_SHIFT 4
-#define BCHP_CLKGEN_SWITCH_TOP_INST_CLOCK_ENABLE_SWCH_SCB_CLOCK_ENABLE_DEFAULT 0x00000001
-
-/* CLKGEN :: SWITCH_TOP_INST_CLOCK_ENABLE :: SWCH_RGMII_250_CLOCK_ENABLE [03:03] */
-#define BCHP_CLKGEN_SWITCH_TOP_INST_CLOCK_ENABLE_SWCH_RGMII_250_CLOCK_ENABLE_MASK 0x00000008
-#define BCHP_CLKGEN_SWITCH_TOP_INST_CLOCK_ENABLE_SWCH_RGMII_250_CLOCK_ENABLE_SHIFT 3
-#define BCHP_CLKGEN_SWITCH_TOP_INST_CLOCK_ENABLE_SWCH_RGMII_250_CLOCK_ENABLE_DEFAULT 0x00000001
-
-/* CLKGEN :: SWITCH_TOP_INST_CLOCK_ENABLE :: SWCH_54_CLOCK_ENABLE [02:02] */
-#define BCHP_CLKGEN_SWITCH_TOP_INST_CLOCK_ENABLE_SWCH_54_CLOCK_ENABLE_MASK 0x00000004
-#define BCHP_CLKGEN_SWITCH_TOP_INST_CLOCK_ENABLE_SWCH_54_CLOCK_ENABLE_SHIFT 2
-#define BCHP_CLKGEN_SWITCH_TOP_INST_CLOCK_ENABLE_SWCH_54_CLOCK_ENABLE_DEFAULT 0x00000001
-
-/* CLKGEN :: SWITCH_TOP_INST_CLOCK_ENABLE :: SWCH_250_CLOCK_ENABLE [01:01] */
-#define BCHP_CLKGEN_SWITCH_TOP_INST_CLOCK_ENABLE_SWCH_250_CLOCK_ENABLE_MASK 0x00000002
-#define BCHP_CLKGEN_SWITCH_TOP_INST_CLOCK_ENABLE_SWCH_250_CLOCK_ENABLE_SHIFT 1
-#define BCHP_CLKGEN_SWITCH_TOP_INST_CLOCK_ENABLE_SWCH_250_CLOCK_ENABLE_DEFAULT 0x00000001
-
-/* CLKGEN :: SWITCH_TOP_INST_CLOCK_ENABLE :: SWCH_108_CLOCK_ENABLE [00:00] */
-#define BCHP_CLKGEN_SWITCH_TOP_INST_CLOCK_ENABLE_SWCH_108_CLOCK_ENABLE_MASK 0x00000001
-#define BCHP_CLKGEN_SWITCH_TOP_INST_CLOCK_ENABLE_SWCH_108_CLOCK_ENABLE_SHIFT 0
-#define BCHP_CLKGEN_SWITCH_TOP_INST_CLOCK_ENABLE_SWCH_108_CLOCK_ENABLE_DEFAULT 0x00000001
-
-/***************************************************************************
- *SWITCH_TOP_INST_CLOCK_ENABLE_STATUS - Clock Enable Status
- ***************************************************************************/
-/* CLKGEN :: SWITCH_TOP_INST_CLOCK_ENABLE_STATUS :: reserved0 [31:06] */
-#define BCHP_CLKGEN_SWITCH_TOP_INST_CLOCK_ENABLE_STATUS_reserved0_MASK 0xffffffc0
-#define BCHP_CLKGEN_SWITCH_TOP_INST_CLOCK_ENABLE_STATUS_reserved0_SHIFT 6
-
-/* CLKGEN :: SWITCH_TOP_INST_CLOCK_ENABLE_STATUS :: SWCH_SYS_CLOCK_ENABLE_STATUS [05:05] */
-#define BCHP_CLKGEN_SWITCH_TOP_INST_CLOCK_ENABLE_STATUS_SWCH_SYS_CLOCK_ENABLE_STATUS_MASK 0x00000020
-#define BCHP_CLKGEN_SWITCH_TOP_INST_CLOCK_ENABLE_STATUS_SWCH_SYS_CLOCK_ENABLE_STATUS_SHIFT 5
-
-/* CLKGEN :: SWITCH_TOP_INST_CLOCK_ENABLE_STATUS :: SWCH_SCB_CLOCK_ENABLE_STATUS [04:04] */
-#define BCHP_CLKGEN_SWITCH_TOP_INST_CLOCK_ENABLE_STATUS_SWCH_SCB_CLOCK_ENABLE_STATUS_MASK 0x00000010
-#define BCHP_CLKGEN_SWITCH_TOP_INST_CLOCK_ENABLE_STATUS_SWCH_SCB_CLOCK_ENABLE_STATUS_SHIFT 4
-
-/* CLKGEN :: SWITCH_TOP_INST_CLOCK_ENABLE_STATUS :: SWCH_RGMII_250_CLOCK_ENABLE_STATUS [03:03] */
-#define BCHP_CLKGEN_SWITCH_TOP_INST_CLOCK_ENABLE_STATUS_SWCH_RGMII_250_CLOCK_ENABLE_STATUS_MASK 0x00000008
-#define BCHP_CLKGEN_SWITCH_TOP_INST_CLOCK_ENABLE_STATUS_SWCH_RGMII_250_CLOCK_ENABLE_STATUS_SHIFT 3
-
-/* CLKGEN :: SWITCH_TOP_INST_CLOCK_ENABLE_STATUS :: SWCH_54_CLOCK_ENABLE_STATUS [02:02] */
-#define BCHP_CLKGEN_SWITCH_TOP_INST_CLOCK_ENABLE_STATUS_SWCH_54_CLOCK_ENABLE_STATUS_MASK 0x00000004
-#define BCHP_CLKGEN_SWITCH_TOP_INST_CLOCK_ENABLE_STATUS_SWCH_54_CLOCK_ENABLE_STATUS_SHIFT 2
-
-/* CLKGEN :: SWITCH_TOP_INST_CLOCK_ENABLE_STATUS :: SWCH_250_CLOCK_ENABLE_STATUS [01:01] */
-#define BCHP_CLKGEN_SWITCH_TOP_INST_CLOCK_ENABLE_STATUS_SWCH_250_CLOCK_ENABLE_STATUS_MASK 0x00000002
-#define BCHP_CLKGEN_SWITCH_TOP_INST_CLOCK_ENABLE_STATUS_SWCH_250_CLOCK_ENABLE_STATUS_SHIFT 1
-
-/* CLKGEN :: SWITCH_TOP_INST_CLOCK_ENABLE_STATUS :: SWCH_108_CLOCK_ENABLE_STATUS [00:00] */
-#define BCHP_CLKGEN_SWITCH_TOP_INST_CLOCK_ENABLE_STATUS_SWCH_108_CLOCK_ENABLE_STATUS_MASK 0x00000001
-#define BCHP_CLKGEN_SWITCH_TOP_INST_CLOCK_ENABLE_STATUS_SWCH_108_CLOCK_ENABLE_STATUS_SHIFT 0
-
-/***************************************************************************
- *SWITCH_TOP_INST_OBSERVE_CLOCK - Switch top inst observe clock
- ***************************************************************************/
-/* CLKGEN :: SWITCH_TOP_INST_OBSERVE_CLOCK :: reserved0 [31:06] */
-#define BCHP_CLKGEN_SWITCH_TOP_INST_OBSERVE_CLOCK_reserved0_MASK 0xffffffc0
-#define BCHP_CLKGEN_SWITCH_TOP_INST_OBSERVE_CLOCK_reserved0_SHIFT 6
-
-/* CLKGEN :: SWITCH_TOP_INST_OBSERVE_CLOCK :: SWCH_ENABLE_OBSERVE_CLOCK [05:05] */
-#define BCHP_CLKGEN_SWITCH_TOP_INST_OBSERVE_CLOCK_SWCH_ENABLE_OBSERVE_CLOCK_MASK 0x00000020
-#define BCHP_CLKGEN_SWITCH_TOP_INST_OBSERVE_CLOCK_SWCH_ENABLE_OBSERVE_CLOCK_SHIFT 5
-#define BCHP_CLKGEN_SWITCH_TOP_INST_OBSERVE_CLOCK_SWCH_ENABLE_OBSERVE_CLOCK_DEFAULT 0x00000000
-
-/* CLKGEN :: SWITCH_TOP_INST_OBSERVE_CLOCK :: SWCH_ENABLE_DIVIDER_OBSERVE_CLOCK [04:04] */
-#define BCHP_CLKGEN_SWITCH_TOP_INST_OBSERVE_CLOCK_SWCH_ENABLE_DIVIDER_OBSERVE_CLOCK_MASK 0x00000010
-#define BCHP_CLKGEN_SWITCH_TOP_INST_OBSERVE_CLOCK_SWCH_ENABLE_DIVIDER_OBSERVE_CLOCK_SHIFT 4
-#define BCHP_CLKGEN_SWITCH_TOP_INST_OBSERVE_CLOCK_SWCH_ENABLE_DIVIDER_OBSERVE_CLOCK_DEFAULT 0x00000000
-
-/* CLKGEN :: SWITCH_TOP_INST_OBSERVE_CLOCK :: SWCH_CONTROL_OBSERVE_CLOCK [03:00] */
-#define BCHP_CLKGEN_SWITCH_TOP_INST_OBSERVE_CLOCK_SWCH_CONTROL_OBSERVE_CLOCK_MASK 0x0000000f
-#define BCHP_CLKGEN_SWITCH_TOP_INST_OBSERVE_CLOCK_SWCH_CONTROL_OBSERVE_CLOCK_SHIFT 0
-#define BCHP_CLKGEN_SWITCH_TOP_INST_OBSERVE_CLOCK_SWCH_CONTROL_OBSERVE_CLOCK_DEFAULT 0x00000000
-
-/***************************************************************************
- *SYS_CTRL_INST_CLOCK_DISABLE - Disable SYS_CTRL_INST's clocks
- ***************************************************************************/
-/* CLKGEN :: SYS_CTRL_INST_CLOCK_DISABLE :: reserved0 [31:03] */
-#define BCHP_CLKGEN_SYS_CTRL_INST_CLOCK_DISABLE_reserved0_MASK 0xfffffff8
-#define BCHP_CLKGEN_SYS_CTRL_INST_CLOCK_DISABLE_reserved0_SHIFT 3
-
-/* CLKGEN :: SYS_CTRL_INST_CLOCK_DISABLE :: DISABLE_SYSCTRL_UPG_CLOCK [02:02] */
-#define BCHP_CLKGEN_SYS_CTRL_INST_CLOCK_DISABLE_DISABLE_SYSCTRL_UPG_CLOCK_MASK 0x00000004
-#define BCHP_CLKGEN_SYS_CTRL_INST_CLOCK_DISABLE_DISABLE_SYSCTRL_UPG_CLOCK_SHIFT 2
-#define BCHP_CLKGEN_SYS_CTRL_INST_CLOCK_DISABLE_DISABLE_SYSCTRL_UPG_CLOCK_DEFAULT 0x00000000
-
-/* CLKGEN :: SYS_CTRL_INST_CLOCK_DISABLE :: DISABLE_SC1_CLOCK [01:01] */
-#define BCHP_CLKGEN_SYS_CTRL_INST_CLOCK_DISABLE_DISABLE_SC1_CLOCK_MASK 0x00000002
-#define BCHP_CLKGEN_SYS_CTRL_INST_CLOCK_DISABLE_DISABLE_SC1_CLOCK_SHIFT 1
-#define BCHP_CLKGEN_SYS_CTRL_INST_CLOCK_DISABLE_DISABLE_SC1_CLOCK_DEFAULT 0x00000000
-
-/* CLKGEN :: SYS_CTRL_INST_CLOCK_DISABLE :: DISABLE_SC0_CLOCK [00:00] */
-#define BCHP_CLKGEN_SYS_CTRL_INST_CLOCK_DISABLE_DISABLE_SC0_CLOCK_MASK 0x00000001
-#define BCHP_CLKGEN_SYS_CTRL_INST_CLOCK_DISABLE_DISABLE_SC0_CLOCK_SHIFT 0
-#define BCHP_CLKGEN_SYS_CTRL_INST_CLOCK_DISABLE_DISABLE_SC0_CLOCK_DEFAULT 0x00000000
-
-/***************************************************************************
- *SYS_CTRL_INST_CLOCK_DISABLE_STATUS - Clock Disable Status
- ***************************************************************************/
-/* CLKGEN :: SYS_CTRL_INST_CLOCK_DISABLE_STATUS :: reserved0 [31:03] */
-#define BCHP_CLKGEN_SYS_CTRL_INST_CLOCK_DISABLE_STATUS_reserved0_MASK 0xfffffff8
-#define BCHP_CLKGEN_SYS_CTRL_INST_CLOCK_DISABLE_STATUS_reserved0_SHIFT 3
-
-/* CLKGEN :: SYS_CTRL_INST_CLOCK_DISABLE_STATUS :: DISABLE_SYSCTRL_UPG_CLOCK_STATUS [02:02] */
-#define BCHP_CLKGEN_SYS_CTRL_INST_CLOCK_DISABLE_STATUS_DISABLE_SYSCTRL_UPG_CLOCK_STATUS_MASK 0x00000004
-#define BCHP_CLKGEN_SYS_CTRL_INST_CLOCK_DISABLE_STATUS_DISABLE_SYSCTRL_UPG_CLOCK_STATUS_SHIFT 2
-
-/* CLKGEN :: SYS_CTRL_INST_CLOCK_DISABLE_STATUS :: DISABLE_SC1_CLOCK_STATUS [01:01] */
-#define BCHP_CLKGEN_SYS_CTRL_INST_CLOCK_DISABLE_STATUS_DISABLE_SC1_CLOCK_STATUS_MASK 0x00000002
-#define BCHP_CLKGEN_SYS_CTRL_INST_CLOCK_DISABLE_STATUS_DISABLE_SC1_CLOCK_STATUS_SHIFT 1
-
-/* CLKGEN :: SYS_CTRL_INST_CLOCK_DISABLE_STATUS :: DISABLE_SC0_CLOCK_STATUS [00:00] */
-#define BCHP_CLKGEN_SYS_CTRL_INST_CLOCK_DISABLE_STATUS_DISABLE_SC0_CLOCK_STATUS_MASK 0x00000001
-#define BCHP_CLKGEN_SYS_CTRL_INST_CLOCK_DISABLE_STATUS_DISABLE_SC0_CLOCK_STATUS_SHIFT 0
-
-/***************************************************************************
- *TESTPORT - Special Testport Controls
- ***************************************************************************/
-/* CLKGEN :: TESTPORT :: reserved0 [31:05] */
-#define BCHP_CLKGEN_TESTPORT_reserved0_MASK 0xffffffe0
-#define BCHP_CLKGEN_TESTPORT_reserved0_SHIFT 5
-
-/* CLKGEN :: TESTPORT :: PLL_TEST_STATUS_SELECT [04:00] */
-#define BCHP_CLKGEN_TESTPORT_PLL_TEST_STATUS_SELECT_MASK 0x0000001f
-#define BCHP_CLKGEN_TESTPORT_PLL_TEST_STATUS_SELECT_SHIFT 0
-#define BCHP_CLKGEN_TESTPORT_PLL_TEST_STATUS_SELECT_DEFAULT 0x00000000
-
-/***************************************************************************
- *UBUS_MOD_PERIPH_FPM_INST_CLOCK_DISABLE - Disable UBUS_MOD_PERIPH_FPM_INST's clocks
- ***************************************************************************/
-/* CLKGEN :: UBUS_MOD_PERIPH_FPM_INST_CLOCK_DISABLE :: reserved0 [31:06] */
-#define BCHP_CLKGEN_UBUS_MOD_PERIPH_FPM_INST_CLOCK_DISABLE_reserved0_MASK 0xffffffc0
-#define BCHP_CLKGEN_UBUS_MOD_PERIPH_FPM_INST_CLOCK_DISABLE_reserved0_SHIFT 6
-
-/* CLKGEN :: UBUS_MOD_PERIPH_FPM_INST_CLOCK_DISABLE :: DISABLE_SYSTEM_27_CLOCK [05:05] */
-#define BCHP_CLKGEN_UBUS_MOD_PERIPH_FPM_INST_CLOCK_DISABLE_DISABLE_SYSTEM_27_CLOCK_MASK 0x00000020
-#define BCHP_CLKGEN_UBUS_MOD_PERIPH_FPM_INST_CLOCK_DISABLE_DISABLE_SYSTEM_27_CLOCK_SHIFT 5
-#define BCHP_CLKGEN_UBUS_MOD_PERIPH_FPM_INST_CLOCK_DISABLE_DISABLE_SYSTEM_27_CLOCK_DEFAULT 0x00000000
-
-/* CLKGEN :: UBUS_MOD_PERIPH_FPM_INST_CLOCK_DISABLE :: DISABLE_PER_XTAL_CLOCK [04:04] */
-#define BCHP_CLKGEN_UBUS_MOD_PERIPH_FPM_INST_CLOCK_DISABLE_DISABLE_PER_XTAL_CLOCK_MASK 0x00000010
-#define BCHP_CLKGEN_UBUS_MOD_PERIPH_FPM_INST_CLOCK_DISABLE_DISABLE_PER_XTAL_CLOCK_SHIFT 4
-#define BCHP_CLKGEN_UBUS_MOD_PERIPH_FPM_INST_CLOCK_DISABLE_DISABLE_PER_XTAL_CLOCK_DEFAULT 0x00000000
-
-/* CLKGEN :: UBUS_MOD_PERIPH_FPM_INST_CLOCK_DISABLE :: DISABLE_PER_SPIM_100_CLOCK [03:03] */
-#define BCHP_CLKGEN_UBUS_MOD_PERIPH_FPM_INST_CLOCK_DISABLE_DISABLE_PER_SPIM_100_CLOCK_MASK 0x00000008
-#define BCHP_CLKGEN_UBUS_MOD_PERIPH_FPM_INST_CLOCK_DISABLE_DISABLE_PER_SPIM_100_CLOCK_SHIFT 3
-#define BCHP_CLKGEN_UBUS_MOD_PERIPH_FPM_INST_CLOCK_DISABLE_DISABLE_PER_SPIM_100_CLOCK_DEFAULT 0x00000000
-
-/* CLKGEN :: UBUS_MOD_PERIPH_FPM_INST_CLOCK_DISABLE :: DISABLE_PER_HSPI_CLOCK [02:02] */
-#define BCHP_CLKGEN_UBUS_MOD_PERIPH_FPM_INST_CLOCK_DISABLE_DISABLE_PER_HSPI_CLOCK_MASK 0x00000004
-#define BCHP_CLKGEN_UBUS_MOD_PERIPH_FPM_INST_CLOCK_DISABLE_DISABLE_PER_HSPI_CLOCK_SHIFT 2
-#define BCHP_CLKGEN_UBUS_MOD_PERIPH_FPM_INST_CLOCK_DISABLE_DISABLE_PER_HSPI_CLOCK_DEFAULT 0x00000000
-
-/* CLKGEN :: UBUS_MOD_PERIPH_FPM_INST_CLOCK_DISABLE :: DISABLE_PER_DEV_216_CLOCK [01:01] */
-#define BCHP_CLKGEN_UBUS_MOD_PERIPH_FPM_INST_CLOCK_DISABLE_DISABLE_PER_DEV_216_CLOCK_MASK 0x00000002
-#define BCHP_CLKGEN_UBUS_MOD_PERIPH_FPM_INST_CLOCK_DISABLE_DISABLE_PER_DEV_216_CLOCK_SHIFT 1
-#define BCHP_CLKGEN_UBUS_MOD_PERIPH_FPM_INST_CLOCK_DISABLE_DISABLE_PER_DEV_216_CLOCK_DEFAULT 0x00000000
-
-/* CLKGEN :: UBUS_MOD_PERIPH_FPM_INST_CLOCK_DISABLE :: DISABLE_FPM_DEV_216_CLOCK [00:00] */
-#define BCHP_CLKGEN_UBUS_MOD_PERIPH_FPM_INST_CLOCK_DISABLE_DISABLE_FPM_DEV_216_CLOCK_MASK 0x00000001
-#define BCHP_CLKGEN_UBUS_MOD_PERIPH_FPM_INST_CLOCK_DISABLE_DISABLE_FPM_DEV_216_CLOCK_SHIFT 0
-#define BCHP_CLKGEN_UBUS_MOD_PERIPH_FPM_INST_CLOCK_DISABLE_DISABLE_FPM_DEV_216_CLOCK_DEFAULT 0x00000000
-
-/***************************************************************************
- *UBUS_MOD_PERIPH_FPM_INST_CLOCK_DISABLE_STATUS - Clock Disable Status
- ***************************************************************************/
-/* CLKGEN :: UBUS_MOD_PERIPH_FPM_INST_CLOCK_DISABLE_STATUS :: reserved0 [31:06] */
-#define BCHP_CLKGEN_UBUS_MOD_PERIPH_FPM_INST_CLOCK_DISABLE_STATUS_reserved0_MASK 0xffffffc0
-#define BCHP_CLKGEN_UBUS_MOD_PERIPH_FPM_INST_CLOCK_DISABLE_STATUS_reserved0_SHIFT 6
-
-/* CLKGEN :: UBUS_MOD_PERIPH_FPM_INST_CLOCK_DISABLE_STATUS :: DISABLE_SYSTEM_27_CLOCK_STATUS [05:05] */
-#define BCHP_CLKGEN_UBUS_MOD_PERIPH_FPM_INST_CLOCK_DISABLE_STATUS_DISABLE_SYSTEM_27_CLOCK_STATUS_MASK 0x00000020
-#define BCHP_CLKGEN_UBUS_MOD_PERIPH_FPM_INST_CLOCK_DISABLE_STATUS_DISABLE_SYSTEM_27_CLOCK_STATUS_SHIFT 5
-
-/* CLKGEN :: UBUS_MOD_PERIPH_FPM_INST_CLOCK_DISABLE_STATUS :: DISABLE_PER_XTAL_CLOCK_STATUS [04:04] */
-#define BCHP_CLKGEN_UBUS_MOD_PERIPH_FPM_INST_CLOCK_DISABLE_STATUS_DISABLE_PER_XTAL_CLOCK_STATUS_MASK 0x00000010
-#define BCHP_CLKGEN_UBUS_MOD_PERIPH_FPM_INST_CLOCK_DISABLE_STATUS_DISABLE_PER_XTAL_CLOCK_STATUS_SHIFT 4
-
-/* CLKGEN :: UBUS_MOD_PERIPH_FPM_INST_CLOCK_DISABLE_STATUS :: DISABLE_PER_SPIM_100_CLOCK_STATUS [03:03] */
-#define BCHP_CLKGEN_UBUS_MOD_PERIPH_FPM_INST_CLOCK_DISABLE_STATUS_DISABLE_PER_SPIM_100_CLOCK_STATUS_MASK 0x00000008
-#define BCHP_CLKGEN_UBUS_MOD_PERIPH_FPM_INST_CLOCK_DISABLE_STATUS_DISABLE_PER_SPIM_100_CLOCK_STATUS_SHIFT 3
-
-/* CLKGEN :: UBUS_MOD_PERIPH_FPM_INST_CLOCK_DISABLE_STATUS :: DISABLE_PER_HSPI_CLOCK_STATUS [02:02] */
-#define BCHP_CLKGEN_UBUS_MOD_PERIPH_FPM_INST_CLOCK_DISABLE_STATUS_DISABLE_PER_HSPI_CLOCK_STATUS_MASK 0x00000004
-#define BCHP_CLKGEN_UBUS_MOD_PERIPH_FPM_INST_CLOCK_DISABLE_STATUS_DISABLE_PER_HSPI_CLOCK_STATUS_SHIFT 2
-
-/* CLKGEN :: UBUS_MOD_PERIPH_FPM_INST_CLOCK_DISABLE_STATUS :: DISABLE_PER_DEV_216_CLOCK_STATUS [01:01] */
-#define BCHP_CLKGEN_UBUS_MOD_PERIPH_FPM_INST_CLOCK_DISABLE_STATUS_DISABLE_PER_DEV_216_CLOCK_STATUS_MASK 0x00000002
-#define BCHP_CLKGEN_UBUS_MOD_PERIPH_FPM_INST_CLOCK_DISABLE_STATUS_DISABLE_PER_DEV_216_CLOCK_STATUS_SHIFT 1
-
-/* CLKGEN :: UBUS_MOD_PERIPH_FPM_INST_CLOCK_DISABLE_STATUS :: DISABLE_FPM_DEV_216_CLOCK_STATUS [00:00] */
-#define BCHP_CLKGEN_UBUS_MOD_PERIPH_FPM_INST_CLOCK_DISABLE_STATUS_DISABLE_FPM_DEV_216_CLOCK_STATUS_MASK 0x00000001
-#define BCHP_CLKGEN_UBUS_MOD_PERIPH_FPM_INST_CLOCK_DISABLE_STATUS_DISABLE_FPM_DEV_216_CLOCK_STATUS_SHIFT 0
-
-/***************************************************************************
- *UBUS_MOD_PERIPH_FPM_INST_CLOCK_ENABLE - Ubus mod periph fpm inst clock enable
- ***************************************************************************/
-/* CLKGEN :: UBUS_MOD_PERIPH_FPM_INST_CLOCK_ENABLE :: reserved0 [31:03] */
-#define BCHP_CLKGEN_UBUS_MOD_PERIPH_FPM_INST_CLOCK_ENABLE_reserved0_MASK 0xfffffff8
-#define BCHP_CLKGEN_UBUS_MOD_PERIPH_FPM_INST_CLOCK_ENABLE_reserved0_SHIFT 3
-
-/* CLKGEN :: UBUS_MOD_PERIPH_FPM_INST_CLOCK_ENABLE :: PER_GISB_CLOCK_ENABLE [02:02] */
-#define BCHP_CLKGEN_UBUS_MOD_PERIPH_FPM_INST_CLOCK_ENABLE_PER_GISB_CLOCK_ENABLE_MASK 0x00000004
-#define BCHP_CLKGEN_UBUS_MOD_PERIPH_FPM_INST_CLOCK_ENABLE_PER_GISB_CLOCK_ENABLE_SHIFT 2
-#define BCHP_CLKGEN_UBUS_MOD_PERIPH_FPM_INST_CLOCK_ENABLE_PER_GISB_CLOCK_ENABLE_DEFAULT 0x00000001
-
-/* CLKGEN :: UBUS_MOD_PERIPH_FPM_INST_CLOCK_ENABLE :: PER_GISB_2ND_CLOCK_ENABLE [01:01] */
-#define BCHP_CLKGEN_UBUS_MOD_PERIPH_FPM_INST_CLOCK_ENABLE_PER_GISB_2ND_CLOCK_ENABLE_MASK 0x00000002
-#define BCHP_CLKGEN_UBUS_MOD_PERIPH_FPM_INST_CLOCK_ENABLE_PER_GISB_2ND_CLOCK_ENABLE_SHIFT 1
-#define BCHP_CLKGEN_UBUS_MOD_PERIPH_FPM_INST_CLOCK_ENABLE_PER_GISB_2ND_CLOCK_ENABLE_DEFAULT 0x00000001
-
-/* CLKGEN :: UBUS_MOD_PERIPH_FPM_INST_CLOCK_ENABLE :: PER_54_CLOCK_ENABLE [00:00] */
-#define BCHP_CLKGEN_UBUS_MOD_PERIPH_FPM_INST_CLOCK_ENABLE_PER_54_CLOCK_ENABLE_MASK 0x00000001
-#define BCHP_CLKGEN_UBUS_MOD_PERIPH_FPM_INST_CLOCK_ENABLE_PER_54_CLOCK_ENABLE_SHIFT 0
-#define BCHP_CLKGEN_UBUS_MOD_PERIPH_FPM_INST_CLOCK_ENABLE_PER_54_CLOCK_ENABLE_DEFAULT 0x00000001
-
-/***************************************************************************
- *UBUS_MOD_PERIPH_FPM_INST_CLOCK_ENABLE_STATUS - Clock Enable Status
- ***************************************************************************/
-/* CLKGEN :: UBUS_MOD_PERIPH_FPM_INST_CLOCK_ENABLE_STATUS :: reserved0 [31:03] */
-#define BCHP_CLKGEN_UBUS_MOD_PERIPH_FPM_INST_CLOCK_ENABLE_STATUS_reserved0_MASK 0xfffffff8
-#define BCHP_CLKGEN_UBUS_MOD_PERIPH_FPM_INST_CLOCK_ENABLE_STATUS_reserved0_SHIFT 3
-
-/* CLKGEN :: UBUS_MOD_PERIPH_FPM_INST_CLOCK_ENABLE_STATUS :: PER_GISB_CLOCK_ENABLE_STATUS [02:02] */
-#define BCHP_CLKGEN_UBUS_MOD_PERIPH_FPM_INST_CLOCK_ENABLE_STATUS_PER_GISB_CLOCK_ENABLE_STATUS_MASK 0x00000004
-#define BCHP_CLKGEN_UBUS_MOD_PERIPH_FPM_INST_CLOCK_ENABLE_STATUS_PER_GISB_CLOCK_ENABLE_STATUS_SHIFT 2
-
-/* CLKGEN :: UBUS_MOD_PERIPH_FPM_INST_CLOCK_ENABLE_STATUS :: PER_GISB_2ND_CLOCK_ENABLE_STATUS [01:01] */
-#define BCHP_CLKGEN_UBUS_MOD_PERIPH_FPM_INST_CLOCK_ENABLE_STATUS_PER_GISB_2ND_CLOCK_ENABLE_STATUS_MASK 0x00000002
-#define BCHP_CLKGEN_UBUS_MOD_PERIPH_FPM_INST_CLOCK_ENABLE_STATUS_PER_GISB_2ND_CLOCK_ENABLE_STATUS_SHIFT 1
-
-/* CLKGEN :: UBUS_MOD_PERIPH_FPM_INST_CLOCK_ENABLE_STATUS :: PER_54_CLOCK_ENABLE_STATUS [00:00] */
-#define BCHP_CLKGEN_UBUS_MOD_PERIPH_FPM_INST_CLOCK_ENABLE_STATUS_PER_54_CLOCK_ENABLE_STATUS_MASK 0x00000001
-#define BCHP_CLKGEN_UBUS_MOD_PERIPH_FPM_INST_CLOCK_ENABLE_STATUS_PER_54_CLOCK_ENABLE_STATUS_SHIFT 0
-
-/***************************************************************************
- *UNIMAC_MBDMA_TOP_ROUTER_1_INST_CLOCK_DISABLE - Disable UNIMAC_MBDMA_TOP_ROUTER_1_INST's clocks
- ***************************************************************************/
-/* CLKGEN :: UNIMAC_MBDMA_TOP_ROUTER_1_INST_CLOCK_DISABLE :: reserved0 [31:02] */
-#define BCHP_CLKGEN_UNIMAC_MBDMA_TOP_ROUTER_1_INST_CLOCK_DISABLE_reserved0_MASK 0xfffffffc
-#define BCHP_CLKGEN_UNIMAC_MBDMA_TOP_ROUTER_1_INST_CLOCK_DISABLE_reserved0_SHIFT 2
-
-/* CLKGEN :: UNIMAC_MBDMA_TOP_ROUTER_1_INST_CLOCK_DISABLE :: DISABLE_UNIMAC_250_CLOCK [01:01] */
-#define BCHP_CLKGEN_UNIMAC_MBDMA_TOP_ROUTER_1_INST_CLOCK_DISABLE_DISABLE_UNIMAC_250_CLOCK_MASK 0x00000002
-#define BCHP_CLKGEN_UNIMAC_MBDMA_TOP_ROUTER_1_INST_CLOCK_DISABLE_DISABLE_UNIMAC_250_CLOCK_SHIFT 1
-#define BCHP_CLKGEN_UNIMAC_MBDMA_TOP_ROUTER_1_INST_CLOCK_DISABLE_DISABLE_UNIMAC_250_CLOCK_DEFAULT 0x00000000
-
-/* CLKGEN :: UNIMAC_MBDMA_TOP_ROUTER_1_INST_CLOCK_DISABLE :: DISABLE_UNIMAC_108_CLOCK [00:00] */
-#define BCHP_CLKGEN_UNIMAC_MBDMA_TOP_ROUTER_1_INST_CLOCK_DISABLE_DISABLE_UNIMAC_108_CLOCK_MASK 0x00000001
-#define BCHP_CLKGEN_UNIMAC_MBDMA_TOP_ROUTER_1_INST_CLOCK_DISABLE_DISABLE_UNIMAC_108_CLOCK_SHIFT 0
-#define BCHP_CLKGEN_UNIMAC_MBDMA_TOP_ROUTER_1_INST_CLOCK_DISABLE_DISABLE_UNIMAC_108_CLOCK_DEFAULT 0x00000000
-
-/***************************************************************************
- *UNIMAC_MBDMA_TOP_ROUTER_1_INST_CLOCK_DISABLE_STATUS - Clock Disable Status
- ***************************************************************************/
-/* CLKGEN :: UNIMAC_MBDMA_TOP_ROUTER_1_INST_CLOCK_DISABLE_STATUS :: reserved0 [31:02] */
-#define BCHP_CLKGEN_UNIMAC_MBDMA_TOP_ROUTER_1_INST_CLOCK_DISABLE_STATUS_reserved0_MASK 0xfffffffc
-#define BCHP_CLKGEN_UNIMAC_MBDMA_TOP_ROUTER_1_INST_CLOCK_DISABLE_STATUS_reserved0_SHIFT 2
-
-/* CLKGEN :: UNIMAC_MBDMA_TOP_ROUTER_1_INST_CLOCK_DISABLE_STATUS :: DISABLE_UNIMAC_250_CLOCK_STATUS [01:01] */
-#define BCHP_CLKGEN_UNIMAC_MBDMA_TOP_ROUTER_1_INST_CLOCK_DISABLE_STATUS_DISABLE_UNIMAC_250_CLOCK_STATUS_MASK 0x00000002
-#define BCHP_CLKGEN_UNIMAC_MBDMA_TOP_ROUTER_1_INST_CLOCK_DISABLE_STATUS_DISABLE_UNIMAC_250_CLOCK_STATUS_SHIFT 1
-
-/* CLKGEN :: UNIMAC_MBDMA_TOP_ROUTER_1_INST_CLOCK_DISABLE_STATUS :: DISABLE_UNIMAC_108_CLOCK_STATUS [00:00] */
-#define BCHP_CLKGEN_UNIMAC_MBDMA_TOP_ROUTER_1_INST_CLOCK_DISABLE_STATUS_DISABLE_UNIMAC_108_CLOCK_STATUS_MASK 0x00000001
-#define BCHP_CLKGEN_UNIMAC_MBDMA_TOP_ROUTER_1_INST_CLOCK_DISABLE_STATUS_DISABLE_UNIMAC_108_CLOCK_STATUS_SHIFT 0
-
-/***************************************************************************
- *UNIMAC_MBDMA_TOP_ROUTER_1_INST_CLOCK_ENABLE - Unimac mbdma top router 1 inst clock enable
- ***************************************************************************/
-/* CLKGEN :: UNIMAC_MBDMA_TOP_ROUTER_1_INST_CLOCK_ENABLE :: reserved0 [31:02] */
-#define BCHP_CLKGEN_UNIMAC_MBDMA_TOP_ROUTER_1_INST_CLOCK_ENABLE_reserved0_MASK 0xfffffffc
-#define BCHP_CLKGEN_UNIMAC_MBDMA_TOP_ROUTER_1_INST_CLOCK_ENABLE_reserved0_SHIFT 2
-
-/* CLKGEN :: UNIMAC_MBDMA_TOP_ROUTER_1_INST_CLOCK_ENABLE :: UNIMAC_H2_SCB_CLOCK_ENABLE [01:01] */
-#define BCHP_CLKGEN_UNIMAC_MBDMA_TOP_ROUTER_1_INST_CLOCK_ENABLE_UNIMAC_H2_SCB_CLOCK_ENABLE_MASK 0x00000002
-#define BCHP_CLKGEN_UNIMAC_MBDMA_TOP_ROUTER_1_INST_CLOCK_ENABLE_UNIMAC_H2_SCB_CLOCK_ENABLE_SHIFT 1
-#define BCHP_CLKGEN_UNIMAC_MBDMA_TOP_ROUTER_1_INST_CLOCK_ENABLE_UNIMAC_H2_SCB_CLOCK_ENABLE_DEFAULT 0x00000001
-
-/* CLKGEN :: UNIMAC_MBDMA_TOP_ROUTER_1_INST_CLOCK_ENABLE :: UNIMAC_H2_54_CLOCK_ENABLE [00:00] */
-#define BCHP_CLKGEN_UNIMAC_MBDMA_TOP_ROUTER_1_INST_CLOCK_ENABLE_UNIMAC_H2_54_CLOCK_ENABLE_MASK 0x00000001
-#define BCHP_CLKGEN_UNIMAC_MBDMA_TOP_ROUTER_1_INST_CLOCK_ENABLE_UNIMAC_H2_54_CLOCK_ENABLE_SHIFT 0
-#define BCHP_CLKGEN_UNIMAC_MBDMA_TOP_ROUTER_1_INST_CLOCK_ENABLE_UNIMAC_H2_54_CLOCK_ENABLE_DEFAULT 0x00000001
-
-/***************************************************************************
- *UNIMAC_MBDMA_TOP_ROUTER_1_INST_CLOCK_ENABLE_STATUS - Clock Enable Status
- ***************************************************************************/
-/* CLKGEN :: UNIMAC_MBDMA_TOP_ROUTER_1_INST_CLOCK_ENABLE_STATUS :: reserved0 [31:02] */
-#define BCHP_CLKGEN_UNIMAC_MBDMA_TOP_ROUTER_1_INST_CLOCK_ENABLE_STATUS_reserved0_MASK 0xfffffffc
-#define BCHP_CLKGEN_UNIMAC_MBDMA_TOP_ROUTER_1_INST_CLOCK_ENABLE_STATUS_reserved0_SHIFT 2
-
-/* CLKGEN :: UNIMAC_MBDMA_TOP_ROUTER_1_INST_CLOCK_ENABLE_STATUS :: UNIMAC_H2_SCB_CLOCK_ENABLE_STATUS [01:01] */
-#define BCHP_CLKGEN_UNIMAC_MBDMA_TOP_ROUTER_1_INST_CLOCK_ENABLE_STATUS_UNIMAC_H2_SCB_CLOCK_ENABLE_STATUS_MASK 0x00000002
-#define BCHP_CLKGEN_UNIMAC_MBDMA_TOP_ROUTER_1_INST_CLOCK_ENABLE_STATUS_UNIMAC_H2_SCB_CLOCK_ENABLE_STATUS_SHIFT 1
-
-/* CLKGEN :: UNIMAC_MBDMA_TOP_ROUTER_1_INST_CLOCK_ENABLE_STATUS :: UNIMAC_H2_54_CLOCK_ENABLE_STATUS [00:00] */
-#define BCHP_CLKGEN_UNIMAC_MBDMA_TOP_ROUTER_1_INST_CLOCK_ENABLE_STATUS_UNIMAC_H2_54_CLOCK_ENABLE_STATUS_MASK 0x00000001
-#define BCHP_CLKGEN_UNIMAC_MBDMA_TOP_ROUTER_1_INST_CLOCK_ENABLE_STATUS_UNIMAC_H2_54_CLOCK_ENABLE_STATUS_SHIFT 0
-
-/***************************************************************************
- *UNIMAC_MBDMA_TOP_ROUTER_INST_CLOCK_DISABLE - Disable UNIMAC_MBDMA_TOP_ROUTER_INST's clocks
- ***************************************************************************/
-/* CLKGEN :: UNIMAC_MBDMA_TOP_ROUTER_INST_CLOCK_DISABLE :: reserved0 [31:02] */
-#define BCHP_CLKGEN_UNIMAC_MBDMA_TOP_ROUTER_INST_CLOCK_DISABLE_reserved0_MASK 0xfffffffc
-#define BCHP_CLKGEN_UNIMAC_MBDMA_TOP_ROUTER_INST_CLOCK_DISABLE_reserved0_SHIFT 2
-
-/* CLKGEN :: UNIMAC_MBDMA_TOP_ROUTER_INST_CLOCK_DISABLE :: DISABLE_UNIMAC_250_CLOCK [01:01] */
-#define BCHP_CLKGEN_UNIMAC_MBDMA_TOP_ROUTER_INST_CLOCK_DISABLE_DISABLE_UNIMAC_250_CLOCK_MASK 0x00000002
-#define BCHP_CLKGEN_UNIMAC_MBDMA_TOP_ROUTER_INST_CLOCK_DISABLE_DISABLE_UNIMAC_250_CLOCK_SHIFT 1
-#define BCHP_CLKGEN_UNIMAC_MBDMA_TOP_ROUTER_INST_CLOCK_DISABLE_DISABLE_UNIMAC_250_CLOCK_DEFAULT 0x00000000
-
-/* CLKGEN :: UNIMAC_MBDMA_TOP_ROUTER_INST_CLOCK_DISABLE :: DISABLE_UNIMAC_108_CLOCK [00:00] */
-#define BCHP_CLKGEN_UNIMAC_MBDMA_TOP_ROUTER_INST_CLOCK_DISABLE_DISABLE_UNIMAC_108_CLOCK_MASK 0x00000001
-#define BCHP_CLKGEN_UNIMAC_MBDMA_TOP_ROUTER_INST_CLOCK_DISABLE_DISABLE_UNIMAC_108_CLOCK_SHIFT 0
-#define BCHP_CLKGEN_UNIMAC_MBDMA_TOP_ROUTER_INST_CLOCK_DISABLE_DISABLE_UNIMAC_108_CLOCK_DEFAULT 0x00000000
-
-/***************************************************************************
- *UNIMAC_MBDMA_TOP_ROUTER_INST_CLOCK_DISABLE_STATUS - Clock Disable Status
- ***************************************************************************/
-/* CLKGEN :: UNIMAC_MBDMA_TOP_ROUTER_INST_CLOCK_DISABLE_STATUS :: reserved0 [31:02] */
-#define BCHP_CLKGEN_UNIMAC_MBDMA_TOP_ROUTER_INST_CLOCK_DISABLE_STATUS_reserved0_MASK 0xfffffffc
-#define BCHP_CLKGEN_UNIMAC_MBDMA_TOP_ROUTER_INST_CLOCK_DISABLE_STATUS_reserved0_SHIFT 2
-
-/* CLKGEN :: UNIMAC_MBDMA_TOP_ROUTER_INST_CLOCK_DISABLE_STATUS :: DISABLE_UNIMAC_250_CLOCK_STATUS [01:01] */
-#define BCHP_CLKGEN_UNIMAC_MBDMA_TOP_ROUTER_INST_CLOCK_DISABLE_STATUS_DISABLE_UNIMAC_250_CLOCK_STATUS_MASK 0x00000002
-#define BCHP_CLKGEN_UNIMAC_MBDMA_TOP_ROUTER_INST_CLOCK_DISABLE_STATUS_DISABLE_UNIMAC_250_CLOCK_STATUS_SHIFT 1
-
-/* CLKGEN :: UNIMAC_MBDMA_TOP_ROUTER_INST_CLOCK_DISABLE_STATUS :: DISABLE_UNIMAC_108_CLOCK_STATUS [00:00] */
-#define BCHP_CLKGEN_UNIMAC_MBDMA_TOP_ROUTER_INST_CLOCK_DISABLE_STATUS_DISABLE_UNIMAC_108_CLOCK_STATUS_MASK 0x00000001
-#define BCHP_CLKGEN_UNIMAC_MBDMA_TOP_ROUTER_INST_CLOCK_DISABLE_STATUS_DISABLE_UNIMAC_108_CLOCK_STATUS_SHIFT 0
-
-/***************************************************************************
- *UNIMAC_MBDMA_TOP_ROUTER_INST_CLOCK_ENABLE - Unimac mbdma top router inst clock enable
- ***************************************************************************/
-/* CLKGEN :: UNIMAC_MBDMA_TOP_ROUTER_INST_CLOCK_ENABLE :: reserved0 [31:02] */
-#define BCHP_CLKGEN_UNIMAC_MBDMA_TOP_ROUTER_INST_CLOCK_ENABLE_reserved0_MASK 0xfffffffc
-#define BCHP_CLKGEN_UNIMAC_MBDMA_TOP_ROUTER_INST_CLOCK_ENABLE_reserved0_SHIFT 2
-
-/* CLKGEN :: UNIMAC_MBDMA_TOP_ROUTER_INST_CLOCK_ENABLE :: UNIMAC_H1_SCB_CLOCK_ENABLE [01:01] */
-#define BCHP_CLKGEN_UNIMAC_MBDMA_TOP_ROUTER_INST_CLOCK_ENABLE_UNIMAC_H1_SCB_CLOCK_ENABLE_MASK 0x00000002
-#define BCHP_CLKGEN_UNIMAC_MBDMA_TOP_ROUTER_INST_CLOCK_ENABLE_UNIMAC_H1_SCB_CLOCK_ENABLE_SHIFT 1
-#define BCHP_CLKGEN_UNIMAC_MBDMA_TOP_ROUTER_INST_CLOCK_ENABLE_UNIMAC_H1_SCB_CLOCK_ENABLE_DEFAULT 0x00000001
-
-/* CLKGEN :: UNIMAC_MBDMA_TOP_ROUTER_INST_CLOCK_ENABLE :: UNIMAC_H1_54_CLOCK_ENABLE [00:00] */
-#define BCHP_CLKGEN_UNIMAC_MBDMA_TOP_ROUTER_INST_CLOCK_ENABLE_UNIMAC_H1_54_CLOCK_ENABLE_MASK 0x00000001
-#define BCHP_CLKGEN_UNIMAC_MBDMA_TOP_ROUTER_INST_CLOCK_ENABLE_UNIMAC_H1_54_CLOCK_ENABLE_SHIFT 0
-#define BCHP_CLKGEN_UNIMAC_MBDMA_TOP_ROUTER_INST_CLOCK_ENABLE_UNIMAC_H1_54_CLOCK_ENABLE_DEFAULT 0x00000001
-
-/***************************************************************************
- *UNIMAC_MBDMA_TOP_ROUTER_INST_CLOCK_ENABLE_STATUS - Clock Enable Status
- ***************************************************************************/
-/* CLKGEN :: UNIMAC_MBDMA_TOP_ROUTER_INST_CLOCK_ENABLE_STATUS :: reserved0 [31:02] */
-#define BCHP_CLKGEN_UNIMAC_MBDMA_TOP_ROUTER_INST_CLOCK_ENABLE_STATUS_reserved0_MASK 0xfffffffc
-#define BCHP_CLKGEN_UNIMAC_MBDMA_TOP_ROUTER_INST_CLOCK_ENABLE_STATUS_reserved0_SHIFT 2
-
-/* CLKGEN :: UNIMAC_MBDMA_TOP_ROUTER_INST_CLOCK_ENABLE_STATUS :: UNIMAC_H1_SCB_CLOCK_ENABLE_STATUS [01:01] */
-#define BCHP_CLKGEN_UNIMAC_MBDMA_TOP_ROUTER_INST_CLOCK_ENABLE_STATUS_UNIMAC_H1_SCB_CLOCK_ENABLE_STATUS_MASK 0x00000002
-#define BCHP_CLKGEN_UNIMAC_MBDMA_TOP_ROUTER_INST_CLOCK_ENABLE_STATUS_UNIMAC_H1_SCB_CLOCK_ENABLE_STATUS_SHIFT 1
-
-/* CLKGEN :: UNIMAC_MBDMA_TOP_ROUTER_INST_CLOCK_ENABLE_STATUS :: UNIMAC_H1_54_CLOCK_ENABLE_STATUS [00:00] */
-#define BCHP_CLKGEN_UNIMAC_MBDMA_TOP_ROUTER_INST_CLOCK_ENABLE_STATUS_UNIMAC_H1_54_CLOCK_ENABLE_STATUS_MASK 0x00000001
-#define BCHP_CLKGEN_UNIMAC_MBDMA_TOP_ROUTER_INST_CLOCK_ENABLE_STATUS_UNIMAC_H1_54_CLOCK_ENABLE_STATUS_SHIFT 0
-
-/***************************************************************************
- *UNIMAC_MBDMA_TOP_STB_INST_CLOCK_DISABLE - Disable UNIMAC_MBDMA_TOP_STB_INST's clocks
- ***************************************************************************/
-/* CLKGEN :: UNIMAC_MBDMA_TOP_STB_INST_CLOCK_DISABLE :: reserved0 [31:02] */
-#define BCHP_CLKGEN_UNIMAC_MBDMA_TOP_STB_INST_CLOCK_DISABLE_reserved0_MASK 0xfffffffc
-#define BCHP_CLKGEN_UNIMAC_MBDMA_TOP_STB_INST_CLOCK_DISABLE_reserved0_SHIFT 2
-
-/* CLKGEN :: UNIMAC_MBDMA_TOP_STB_INST_CLOCK_DISABLE :: DISABLE_UNIMAC_250_CLOCK [01:01] */
-#define BCHP_CLKGEN_UNIMAC_MBDMA_TOP_STB_INST_CLOCK_DISABLE_DISABLE_UNIMAC_250_CLOCK_MASK 0x00000002
-#define BCHP_CLKGEN_UNIMAC_MBDMA_TOP_STB_INST_CLOCK_DISABLE_DISABLE_UNIMAC_250_CLOCK_SHIFT 1
-#define BCHP_CLKGEN_UNIMAC_MBDMA_TOP_STB_INST_CLOCK_DISABLE_DISABLE_UNIMAC_250_CLOCK_DEFAULT 0x00000000
-
-/* CLKGEN :: UNIMAC_MBDMA_TOP_STB_INST_CLOCK_DISABLE :: DISABLE_UNIMAC_108_CLOCK [00:00] */
-#define BCHP_CLKGEN_UNIMAC_MBDMA_TOP_STB_INST_CLOCK_DISABLE_DISABLE_UNIMAC_108_CLOCK_MASK 0x00000001
-#define BCHP_CLKGEN_UNIMAC_MBDMA_TOP_STB_INST_CLOCK_DISABLE_DISABLE_UNIMAC_108_CLOCK_SHIFT 0
-#define BCHP_CLKGEN_UNIMAC_MBDMA_TOP_STB_INST_CLOCK_DISABLE_DISABLE_UNIMAC_108_CLOCK_DEFAULT 0x00000000
-
-/***************************************************************************
- *UNIMAC_MBDMA_TOP_STB_INST_CLOCK_DISABLE_STATUS - Clock Disable Status
- ***************************************************************************/
-/* CLKGEN :: UNIMAC_MBDMA_TOP_STB_INST_CLOCK_DISABLE_STATUS :: reserved0 [31:02] */
-#define BCHP_CLKGEN_UNIMAC_MBDMA_TOP_STB_INST_CLOCK_DISABLE_STATUS_reserved0_MASK 0xfffffffc
-#define BCHP_CLKGEN_UNIMAC_MBDMA_TOP_STB_INST_CLOCK_DISABLE_STATUS_reserved0_SHIFT 2
-
-/* CLKGEN :: UNIMAC_MBDMA_TOP_STB_INST_CLOCK_DISABLE_STATUS :: DISABLE_UNIMAC_250_CLOCK_STATUS [01:01] */
-#define BCHP_CLKGEN_UNIMAC_MBDMA_TOP_STB_INST_CLOCK_DISABLE_STATUS_DISABLE_UNIMAC_250_CLOCK_STATUS_MASK 0x00000002
-#define BCHP_CLKGEN_UNIMAC_MBDMA_TOP_STB_INST_CLOCK_DISABLE_STATUS_DISABLE_UNIMAC_250_CLOCK_STATUS_SHIFT 1
-
-/* CLKGEN :: UNIMAC_MBDMA_TOP_STB_INST_CLOCK_DISABLE_STATUS :: DISABLE_UNIMAC_108_CLOCK_STATUS [00:00] */
-#define BCHP_CLKGEN_UNIMAC_MBDMA_TOP_STB_INST_CLOCK_DISABLE_STATUS_DISABLE_UNIMAC_108_CLOCK_STATUS_MASK 0x00000001
-#define BCHP_CLKGEN_UNIMAC_MBDMA_TOP_STB_INST_CLOCK_DISABLE_STATUS_DISABLE_UNIMAC_108_CLOCK_STATUS_SHIFT 0
-
-/***************************************************************************
- *UNIMAC_MBDMA_TOP_STB_INST_CLOCK_ENABLE - Unimac mbdma top stb inst clock enable
- ***************************************************************************/
-/* CLKGEN :: UNIMAC_MBDMA_TOP_STB_INST_CLOCK_ENABLE :: reserved0 [31:02] */
-#define BCHP_CLKGEN_UNIMAC_MBDMA_TOP_STB_INST_CLOCK_ENABLE_reserved0_MASK 0xfffffffc
-#define BCHP_CLKGEN_UNIMAC_MBDMA_TOP_STB_INST_CLOCK_ENABLE_reserved0_SHIFT 2
-
-/* CLKGEN :: UNIMAC_MBDMA_TOP_STB_INST_CLOCK_ENABLE :: UNIMAC_H_SCB_CLOCK_ENABLE [01:01] */
-#define BCHP_CLKGEN_UNIMAC_MBDMA_TOP_STB_INST_CLOCK_ENABLE_UNIMAC_H_SCB_CLOCK_ENABLE_MASK 0x00000002
-#define BCHP_CLKGEN_UNIMAC_MBDMA_TOP_STB_INST_CLOCK_ENABLE_UNIMAC_H_SCB_CLOCK_ENABLE_SHIFT 1
-#define BCHP_CLKGEN_UNIMAC_MBDMA_TOP_STB_INST_CLOCK_ENABLE_UNIMAC_H_SCB_CLOCK_ENABLE_DEFAULT 0x00000001
-
-/* CLKGEN :: UNIMAC_MBDMA_TOP_STB_INST_CLOCK_ENABLE :: UNIMAC_H_54_CLOCK_ENABLE [00:00] */
-#define BCHP_CLKGEN_UNIMAC_MBDMA_TOP_STB_INST_CLOCK_ENABLE_UNIMAC_H_54_CLOCK_ENABLE_MASK 0x00000001
-#define BCHP_CLKGEN_UNIMAC_MBDMA_TOP_STB_INST_CLOCK_ENABLE_UNIMAC_H_54_CLOCK_ENABLE_SHIFT 0
-#define BCHP_CLKGEN_UNIMAC_MBDMA_TOP_STB_INST_CLOCK_ENABLE_UNIMAC_H_54_CLOCK_ENABLE_DEFAULT 0x00000001
-
-/***************************************************************************
- *UNIMAC_MBDMA_TOP_STB_INST_CLOCK_ENABLE_STATUS - Clock Enable Status
- ***************************************************************************/
-/* CLKGEN :: UNIMAC_MBDMA_TOP_STB_INST_CLOCK_ENABLE_STATUS :: reserved0 [31:02] */
-#define BCHP_CLKGEN_UNIMAC_MBDMA_TOP_STB_INST_CLOCK_ENABLE_STATUS_reserved0_MASK 0xfffffffc
-#define BCHP_CLKGEN_UNIMAC_MBDMA_TOP_STB_INST_CLOCK_ENABLE_STATUS_reserved0_SHIFT 2
-
-/* CLKGEN :: UNIMAC_MBDMA_TOP_STB_INST_CLOCK_ENABLE_STATUS :: UNIMAC_H_SCB_CLOCK_ENABLE_STATUS [01:01] */
-#define BCHP_CLKGEN_UNIMAC_MBDMA_TOP_STB_INST_CLOCK_ENABLE_STATUS_UNIMAC_H_SCB_CLOCK_ENABLE_STATUS_MASK 0x00000002
-#define BCHP_CLKGEN_UNIMAC_MBDMA_TOP_STB_INST_CLOCK_ENABLE_STATUS_UNIMAC_H_SCB_CLOCK_ENABLE_STATUS_SHIFT 1
-
-/* CLKGEN :: UNIMAC_MBDMA_TOP_STB_INST_CLOCK_ENABLE_STATUS :: UNIMAC_H_54_CLOCK_ENABLE_STATUS [00:00] */
-#define BCHP_CLKGEN_UNIMAC_MBDMA_TOP_STB_INST_CLOCK_ENABLE_STATUS_UNIMAC_H_54_CLOCK_ENABLE_STATUS_MASK 0x00000001
-#define BCHP_CLKGEN_UNIMAC_MBDMA_TOP_STB_INST_CLOCK_ENABLE_STATUS_UNIMAC_H_54_CLOCK_ENABLE_STATUS_SHIFT 0
-
-/***************************************************************************
- *UNIMAC_MBDMA_TOP_WAN_INST_CLOCK_DISABLE - Disable UNIMAC_MBDMA_TOP_WAN_INST's clocks
- ***************************************************************************/
-/* CLKGEN :: UNIMAC_MBDMA_TOP_WAN_INST_CLOCK_DISABLE :: reserved0 [31:02] */
-#define BCHP_CLKGEN_UNIMAC_MBDMA_TOP_WAN_INST_CLOCK_DISABLE_reserved0_MASK 0xfffffffc
-#define BCHP_CLKGEN_UNIMAC_MBDMA_TOP_WAN_INST_CLOCK_DISABLE_reserved0_SHIFT 2
-
-/* CLKGEN :: UNIMAC_MBDMA_TOP_WAN_INST_CLOCK_DISABLE :: DISABLE_UNIMAC_250_CLOCK [01:01] */
-#define BCHP_CLKGEN_UNIMAC_MBDMA_TOP_WAN_INST_CLOCK_DISABLE_DISABLE_UNIMAC_250_CLOCK_MASK 0x00000002
-#define BCHP_CLKGEN_UNIMAC_MBDMA_TOP_WAN_INST_CLOCK_DISABLE_DISABLE_UNIMAC_250_CLOCK_SHIFT 1
-#define BCHP_CLKGEN_UNIMAC_MBDMA_TOP_WAN_INST_CLOCK_DISABLE_DISABLE_UNIMAC_250_CLOCK_DEFAULT 0x00000000
-
-/* CLKGEN :: UNIMAC_MBDMA_TOP_WAN_INST_CLOCK_DISABLE :: DISABLE_UNIMAC_108_CLOCK [00:00] */
-#define BCHP_CLKGEN_UNIMAC_MBDMA_TOP_WAN_INST_CLOCK_DISABLE_DISABLE_UNIMAC_108_CLOCK_MASK 0x00000001
-#define BCHP_CLKGEN_UNIMAC_MBDMA_TOP_WAN_INST_CLOCK_DISABLE_DISABLE_UNIMAC_108_CLOCK_SHIFT 0
-#define BCHP_CLKGEN_UNIMAC_MBDMA_TOP_WAN_INST_CLOCK_DISABLE_DISABLE_UNIMAC_108_CLOCK_DEFAULT 0x00000000
-
-/***************************************************************************
- *UNIMAC_MBDMA_TOP_WAN_INST_CLOCK_DISABLE_STATUS - Clock Disable Status
- ***************************************************************************/
-/* CLKGEN :: UNIMAC_MBDMA_TOP_WAN_INST_CLOCK_DISABLE_STATUS :: reserved0 [31:02] */
-#define BCHP_CLKGEN_UNIMAC_MBDMA_TOP_WAN_INST_CLOCK_DISABLE_STATUS_reserved0_MASK 0xfffffffc
-#define BCHP_CLKGEN_UNIMAC_MBDMA_TOP_WAN_INST_CLOCK_DISABLE_STATUS_reserved0_SHIFT 2
-
-/* CLKGEN :: UNIMAC_MBDMA_TOP_WAN_INST_CLOCK_DISABLE_STATUS :: DISABLE_UNIMAC_250_CLOCK_STATUS [01:01] */
-#define BCHP_CLKGEN_UNIMAC_MBDMA_TOP_WAN_INST_CLOCK_DISABLE_STATUS_DISABLE_UNIMAC_250_CLOCK_STATUS_MASK 0x00000002
-#define BCHP_CLKGEN_UNIMAC_MBDMA_TOP_WAN_INST_CLOCK_DISABLE_STATUS_DISABLE_UNIMAC_250_CLOCK_STATUS_SHIFT 1
-
-/* CLKGEN :: UNIMAC_MBDMA_TOP_WAN_INST_CLOCK_DISABLE_STATUS :: DISABLE_UNIMAC_108_CLOCK_STATUS [00:00] */
-#define BCHP_CLKGEN_UNIMAC_MBDMA_TOP_WAN_INST_CLOCK_DISABLE_STATUS_DISABLE_UNIMAC_108_CLOCK_STATUS_MASK 0x00000001
-#define BCHP_CLKGEN_UNIMAC_MBDMA_TOP_WAN_INST_CLOCK_DISABLE_STATUS_DISABLE_UNIMAC_108_CLOCK_STATUS_SHIFT 0
-
-/***************************************************************************
- *UNIMAC_MBDMA_TOP_WAN_INST_CLOCK_ENABLE - Unimac mbdma top wan inst clock enable
- ***************************************************************************/
-/* CLKGEN :: UNIMAC_MBDMA_TOP_WAN_INST_CLOCK_ENABLE :: reserved0 [31:02] */
-#define BCHP_CLKGEN_UNIMAC_MBDMA_TOP_WAN_INST_CLOCK_ENABLE_reserved0_MASK 0xfffffffc
-#define BCHP_CLKGEN_UNIMAC_MBDMA_TOP_WAN_INST_CLOCK_ENABLE_reserved0_SHIFT 2
-
-/* CLKGEN :: UNIMAC_MBDMA_TOP_WAN_INST_CLOCK_ENABLE :: UNIMAC_SCB_CLOCK_ENABLE [01:01] */
-#define BCHP_CLKGEN_UNIMAC_MBDMA_TOP_WAN_INST_CLOCK_ENABLE_UNIMAC_SCB_CLOCK_ENABLE_MASK 0x00000002
-#define BCHP_CLKGEN_UNIMAC_MBDMA_TOP_WAN_INST_CLOCK_ENABLE_UNIMAC_SCB_CLOCK_ENABLE_SHIFT 1
-#define BCHP_CLKGEN_UNIMAC_MBDMA_TOP_WAN_INST_CLOCK_ENABLE_UNIMAC_SCB_CLOCK_ENABLE_DEFAULT 0x00000001
-
-/* CLKGEN :: UNIMAC_MBDMA_TOP_WAN_INST_CLOCK_ENABLE :: UNIMAC_54_CLOCK_ENABLE [00:00] */
-#define BCHP_CLKGEN_UNIMAC_MBDMA_TOP_WAN_INST_CLOCK_ENABLE_UNIMAC_54_CLOCK_ENABLE_MASK 0x00000001
-#define BCHP_CLKGEN_UNIMAC_MBDMA_TOP_WAN_INST_CLOCK_ENABLE_UNIMAC_54_CLOCK_ENABLE_SHIFT 0
-#define BCHP_CLKGEN_UNIMAC_MBDMA_TOP_WAN_INST_CLOCK_ENABLE_UNIMAC_54_CLOCK_ENABLE_DEFAULT 0x00000001
-
-/***************************************************************************
- *UNIMAC_MBDMA_TOP_WAN_INST_CLOCK_ENABLE_STATUS - Clock Enable Status
- ***************************************************************************/
-/* CLKGEN :: UNIMAC_MBDMA_TOP_WAN_INST_CLOCK_ENABLE_STATUS :: reserved0 [31:02] */
-#define BCHP_CLKGEN_UNIMAC_MBDMA_TOP_WAN_INST_CLOCK_ENABLE_STATUS_reserved0_MASK 0xfffffffc
-#define BCHP_CLKGEN_UNIMAC_MBDMA_TOP_WAN_INST_CLOCK_ENABLE_STATUS_reserved0_SHIFT 2
-
-/* CLKGEN :: UNIMAC_MBDMA_TOP_WAN_INST_CLOCK_ENABLE_STATUS :: UNIMAC_SCB_CLOCK_ENABLE_STATUS [01:01] */
-#define BCHP_CLKGEN_UNIMAC_MBDMA_TOP_WAN_INST_CLOCK_ENABLE_STATUS_UNIMAC_SCB_CLOCK_ENABLE_STATUS_MASK 0x00000002
-#define BCHP_CLKGEN_UNIMAC_MBDMA_TOP_WAN_INST_CLOCK_ENABLE_STATUS_UNIMAC_SCB_CLOCK_ENABLE_STATUS_SHIFT 1
-
-/* CLKGEN :: UNIMAC_MBDMA_TOP_WAN_INST_CLOCK_ENABLE_STATUS :: UNIMAC_54_CLOCK_ENABLE_STATUS [00:00] */
-#define BCHP_CLKGEN_UNIMAC_MBDMA_TOP_WAN_INST_CLOCK_ENABLE_STATUS_UNIMAC_54_CLOCK_ENABLE_STATUS_MASK 0x00000001
-#define BCHP_CLKGEN_UNIMAC_MBDMA_TOP_WAN_INST_CLOCK_ENABLE_STATUS_UNIMAC_54_CLOCK_ENABLE_STATUS_SHIFT 0
-
-/***************************************************************************
- *USB0_TOP_INST_CLOCK_DISABLE - Disable USB0_TOP_INST's clocks
- ***************************************************************************/
-/* CLKGEN :: USB0_TOP_INST_CLOCK_DISABLE :: reserved0 [31:02] */
-#define BCHP_CLKGEN_USB0_TOP_INST_CLOCK_DISABLE_reserved0_MASK 0xfffffffc
-#define BCHP_CLKGEN_USB0_TOP_INST_CLOCK_DISABLE_reserved0_SHIFT 2
-
-/* CLKGEN :: USB0_TOP_INST_CLOCK_DISABLE :: DISABLE_USB0_FREERUN_CLOCK [01:01] */
-#define BCHP_CLKGEN_USB0_TOP_INST_CLOCK_DISABLE_DISABLE_USB0_FREERUN_CLOCK_MASK 0x00000002
-#define BCHP_CLKGEN_USB0_TOP_INST_CLOCK_DISABLE_DISABLE_USB0_FREERUN_CLOCK_SHIFT 1
-#define BCHP_CLKGEN_USB0_TOP_INST_CLOCK_DISABLE_DISABLE_USB0_FREERUN_CLOCK_DEFAULT 0x00000000
-
-/* CLKGEN :: USB0_TOP_INST_CLOCK_DISABLE :: DISABLE_USB0_54_MDIO_CLOCK [00:00] */
-#define BCHP_CLKGEN_USB0_TOP_INST_CLOCK_DISABLE_DISABLE_USB0_54_MDIO_CLOCK_MASK 0x00000001
-#define BCHP_CLKGEN_USB0_TOP_INST_CLOCK_DISABLE_DISABLE_USB0_54_MDIO_CLOCK_SHIFT 0
-#define BCHP_CLKGEN_USB0_TOP_INST_CLOCK_DISABLE_DISABLE_USB0_54_MDIO_CLOCK_DEFAULT 0x00000000
-
-/***************************************************************************
- *USB0_TOP_INST_CLOCK_DISABLE_STATUS - Clock Disable Status
- ***************************************************************************/
-/* CLKGEN :: USB0_TOP_INST_CLOCK_DISABLE_STATUS :: reserved0 [31:02] */
-#define BCHP_CLKGEN_USB0_TOP_INST_CLOCK_DISABLE_STATUS_reserved0_MASK 0xfffffffc
-#define BCHP_CLKGEN_USB0_TOP_INST_CLOCK_DISABLE_STATUS_reserved0_SHIFT 2
-
-/* CLKGEN :: USB0_TOP_INST_CLOCK_DISABLE_STATUS :: DISABLE_USB0_FREERUN_CLOCK_STATUS [01:01] */
-#define BCHP_CLKGEN_USB0_TOP_INST_CLOCK_DISABLE_STATUS_DISABLE_USB0_FREERUN_CLOCK_STATUS_MASK 0x00000002
-#define BCHP_CLKGEN_USB0_TOP_INST_CLOCK_DISABLE_STATUS_DISABLE_USB0_FREERUN_CLOCK_STATUS_SHIFT 1
-
-/* CLKGEN :: USB0_TOP_INST_CLOCK_DISABLE_STATUS :: DISABLE_USB0_54_MDIO_CLOCK_STATUS [00:00] */
-#define BCHP_CLKGEN_USB0_TOP_INST_CLOCK_DISABLE_STATUS_DISABLE_USB0_54_MDIO_CLOCK_STATUS_MASK 0x00000001
-#define BCHP_CLKGEN_USB0_TOP_INST_CLOCK_DISABLE_STATUS_DISABLE_USB0_54_MDIO_CLOCK_STATUS_SHIFT 0
-
-/***************************************************************************
- *USB0_TOP_INST_CLOCK_ENABLE - Usb0 top inst clock enable
- ***************************************************************************/
-/* CLKGEN :: USB0_TOP_INST_CLOCK_ENABLE :: reserved0 [31:03] */
-#define BCHP_CLKGEN_USB0_TOP_INST_CLOCK_ENABLE_reserved0_MASK 0xfffffff8
-#define BCHP_CLKGEN_USB0_TOP_INST_CLOCK_ENABLE_reserved0_SHIFT 3
-
-/* CLKGEN :: USB0_TOP_INST_CLOCK_ENABLE :: USB0_SCB_CLOCK_ENABLE [02:02] */
-#define BCHP_CLKGEN_USB0_TOP_INST_CLOCK_ENABLE_USB0_SCB_CLOCK_ENABLE_MASK 0x00000004
-#define BCHP_CLKGEN_USB0_TOP_INST_CLOCK_ENABLE_USB0_SCB_CLOCK_ENABLE_SHIFT 2
-#define BCHP_CLKGEN_USB0_TOP_INST_CLOCK_ENABLE_USB0_SCB_CLOCK_ENABLE_DEFAULT 0x00000001
-
-/* CLKGEN :: USB0_TOP_INST_CLOCK_ENABLE :: USB0_GISB_CLOCK_ENABLE [01:01] */
-#define BCHP_CLKGEN_USB0_TOP_INST_CLOCK_ENABLE_USB0_GISB_CLOCK_ENABLE_MASK 0x00000002
-#define BCHP_CLKGEN_USB0_TOP_INST_CLOCK_ENABLE_USB0_GISB_CLOCK_ENABLE_SHIFT 1
-#define BCHP_CLKGEN_USB0_TOP_INST_CLOCK_ENABLE_USB0_GISB_CLOCK_ENABLE_DEFAULT 0x00000001
-
-/* CLKGEN :: USB0_TOP_INST_CLOCK_ENABLE :: USB0_54_CLOCK_ENABLE [00:00] */
-#define BCHP_CLKGEN_USB0_TOP_INST_CLOCK_ENABLE_USB0_54_CLOCK_ENABLE_MASK 0x00000001
-#define BCHP_CLKGEN_USB0_TOP_INST_CLOCK_ENABLE_USB0_54_CLOCK_ENABLE_SHIFT 0
-#define BCHP_CLKGEN_USB0_TOP_INST_CLOCK_ENABLE_USB0_54_CLOCK_ENABLE_DEFAULT 0x00000001
-
-/***************************************************************************
- *USB0_TOP_INST_CLOCK_ENABLE_AHB - Usb0 top inst clock enable ahb
- ***************************************************************************/
-/* CLKGEN :: USB0_TOP_INST_CLOCK_ENABLE_AHB :: reserved0 [31:01] */
-#define BCHP_CLKGEN_USB0_TOP_INST_CLOCK_ENABLE_AHB_reserved0_MASK 0xfffffffe
-#define BCHP_CLKGEN_USB0_TOP_INST_CLOCK_ENABLE_AHB_reserved0_SHIFT 1
-
-/* CLKGEN :: USB0_TOP_INST_CLOCK_ENABLE_AHB :: USB0_108_CLOCK_ENABLE_AHB [00:00] */
-#define BCHP_CLKGEN_USB0_TOP_INST_CLOCK_ENABLE_AHB_USB0_108_CLOCK_ENABLE_AHB_MASK 0x00000001
-#define BCHP_CLKGEN_USB0_TOP_INST_CLOCK_ENABLE_AHB_USB0_108_CLOCK_ENABLE_AHB_SHIFT 0
-#define BCHP_CLKGEN_USB0_TOP_INST_CLOCK_ENABLE_AHB_USB0_108_CLOCK_ENABLE_AHB_DEFAULT 0x00000001
-
-/***************************************************************************
- *USB0_TOP_INST_CLOCK_ENABLE_AHB_STATUS - Clock Enable Status
- ***************************************************************************/
-/* CLKGEN :: USB0_TOP_INST_CLOCK_ENABLE_AHB_STATUS :: reserved0 [31:01] */
-#define BCHP_CLKGEN_USB0_TOP_INST_CLOCK_ENABLE_AHB_STATUS_reserved0_MASK 0xfffffffe
-#define BCHP_CLKGEN_USB0_TOP_INST_CLOCK_ENABLE_AHB_STATUS_reserved0_SHIFT 1
-
-/* CLKGEN :: USB0_TOP_INST_CLOCK_ENABLE_AHB_STATUS :: USB0_108_CLOCK_ENABLE_AHB_STATUS [00:00] */
-#define BCHP_CLKGEN_USB0_TOP_INST_CLOCK_ENABLE_AHB_STATUS_USB0_108_CLOCK_ENABLE_AHB_STATUS_MASK 0x00000001
-#define BCHP_CLKGEN_USB0_TOP_INST_CLOCK_ENABLE_AHB_STATUS_USB0_108_CLOCK_ENABLE_AHB_STATUS_SHIFT 0
-
-/***************************************************************************
- *USB0_TOP_INST_CLOCK_ENABLE_AXI - Usb0 top inst clock enable axi
- ***************************************************************************/
-/* CLKGEN :: USB0_TOP_INST_CLOCK_ENABLE_AXI :: reserved0 [31:01] */
-#define BCHP_CLKGEN_USB0_TOP_INST_CLOCK_ENABLE_AXI_reserved0_MASK 0xfffffffe
-#define BCHP_CLKGEN_USB0_TOP_INST_CLOCK_ENABLE_AXI_reserved0_SHIFT 1
-
-/* CLKGEN :: USB0_TOP_INST_CLOCK_ENABLE_AXI :: USB0_108_CLOCK_ENABLE_AXI [00:00] */
-#define BCHP_CLKGEN_USB0_TOP_INST_CLOCK_ENABLE_AXI_USB0_108_CLOCK_ENABLE_AXI_MASK 0x00000001
-#define BCHP_CLKGEN_USB0_TOP_INST_CLOCK_ENABLE_AXI_USB0_108_CLOCK_ENABLE_AXI_SHIFT 0
-#define BCHP_CLKGEN_USB0_TOP_INST_CLOCK_ENABLE_AXI_USB0_108_CLOCK_ENABLE_AXI_DEFAULT 0x00000001
-
-/***************************************************************************
- *USB0_TOP_INST_CLOCK_ENABLE_AXI_STATUS - Clock Enable Status
- ***************************************************************************/
-/* CLKGEN :: USB0_TOP_INST_CLOCK_ENABLE_AXI_STATUS :: reserved0 [31:01] */
-#define BCHP_CLKGEN_USB0_TOP_INST_CLOCK_ENABLE_AXI_STATUS_reserved0_MASK 0xfffffffe
-#define BCHP_CLKGEN_USB0_TOP_INST_CLOCK_ENABLE_AXI_STATUS_reserved0_SHIFT 1
-
-/* CLKGEN :: USB0_TOP_INST_CLOCK_ENABLE_AXI_STATUS :: USB0_108_CLOCK_ENABLE_AXI_STATUS [00:00] */
-#define BCHP_CLKGEN_USB0_TOP_INST_CLOCK_ENABLE_AXI_STATUS_USB0_108_CLOCK_ENABLE_AXI_STATUS_MASK 0x00000001
-#define BCHP_CLKGEN_USB0_TOP_INST_CLOCK_ENABLE_AXI_STATUS_USB0_108_CLOCK_ENABLE_AXI_STATUS_SHIFT 0
-
-/***************************************************************************
- *USB0_TOP_INST_CLOCK_ENABLE_STATUS - Clock Enable Status
- ***************************************************************************/
-/* CLKGEN :: USB0_TOP_INST_CLOCK_ENABLE_STATUS :: reserved0 [31:03] */
-#define BCHP_CLKGEN_USB0_TOP_INST_CLOCK_ENABLE_STATUS_reserved0_MASK 0xfffffff8
-#define BCHP_CLKGEN_USB0_TOP_INST_CLOCK_ENABLE_STATUS_reserved0_SHIFT 3
-
-/* CLKGEN :: USB0_TOP_INST_CLOCK_ENABLE_STATUS :: USB0_SCB_CLOCK_ENABLE_STATUS [02:02] */
-#define BCHP_CLKGEN_USB0_TOP_INST_CLOCK_ENABLE_STATUS_USB0_SCB_CLOCK_ENABLE_STATUS_MASK 0x00000004
-#define BCHP_CLKGEN_USB0_TOP_INST_CLOCK_ENABLE_STATUS_USB0_SCB_CLOCK_ENABLE_STATUS_SHIFT 2
-
-/* CLKGEN :: USB0_TOP_INST_CLOCK_ENABLE_STATUS :: USB0_GISB_CLOCK_ENABLE_STATUS [01:01] */
-#define BCHP_CLKGEN_USB0_TOP_INST_CLOCK_ENABLE_STATUS_USB0_GISB_CLOCK_ENABLE_STATUS_MASK 0x00000002
-#define BCHP_CLKGEN_USB0_TOP_INST_CLOCK_ENABLE_STATUS_USB0_GISB_CLOCK_ENABLE_STATUS_SHIFT 1
-
-/* CLKGEN :: USB0_TOP_INST_CLOCK_ENABLE_STATUS :: USB0_54_CLOCK_ENABLE_STATUS [00:00] */
-#define BCHP_CLKGEN_USB0_TOP_INST_CLOCK_ENABLE_STATUS_USB0_54_CLOCK_ENABLE_STATUS_MASK 0x00000001
-#define BCHP_CLKGEN_USB0_TOP_INST_CLOCK_ENABLE_STATUS_USB0_54_CLOCK_ENABLE_STATUS_SHIFT 0
-
-/***************************************************************************
- *USB0_TOP_INST_OBSERVE_CLOCK - Usb0 top inst observe clock
- ***************************************************************************/
-/* CLKGEN :: USB0_TOP_INST_OBSERVE_CLOCK :: reserved0 [31:06] */
-#define BCHP_CLKGEN_USB0_TOP_INST_OBSERVE_CLOCK_reserved0_MASK 0xffffffc0
-#define BCHP_CLKGEN_USB0_TOP_INST_OBSERVE_CLOCK_reserved0_SHIFT 6
-
-/* CLKGEN :: USB0_TOP_INST_OBSERVE_CLOCK :: USB0_ENABLE_OBSERVE_CLOCK [05:05] */
-#define BCHP_CLKGEN_USB0_TOP_INST_OBSERVE_CLOCK_USB0_ENABLE_OBSERVE_CLOCK_MASK 0x00000020
-#define BCHP_CLKGEN_USB0_TOP_INST_OBSERVE_CLOCK_USB0_ENABLE_OBSERVE_CLOCK_SHIFT 5
-#define BCHP_CLKGEN_USB0_TOP_INST_OBSERVE_CLOCK_USB0_ENABLE_OBSERVE_CLOCK_DEFAULT 0x00000000
-
-/* CLKGEN :: USB0_TOP_INST_OBSERVE_CLOCK :: USB0_ENABLE_DIVIDER_OBSERVE_CLOCK [04:04] */
-#define BCHP_CLKGEN_USB0_TOP_INST_OBSERVE_CLOCK_USB0_ENABLE_DIVIDER_OBSERVE_CLOCK_MASK 0x00000010
-#define BCHP_CLKGEN_USB0_TOP_INST_OBSERVE_CLOCK_USB0_ENABLE_DIVIDER_OBSERVE_CLOCK_SHIFT 4
-#define BCHP_CLKGEN_USB0_TOP_INST_OBSERVE_CLOCK_USB0_ENABLE_DIVIDER_OBSERVE_CLOCK_DEFAULT 0x00000000
-
-/* CLKGEN :: USB0_TOP_INST_OBSERVE_CLOCK :: USB0_CONTROL_OBSERVE_CLOCK [03:00] */
-#define BCHP_CLKGEN_USB0_TOP_INST_OBSERVE_CLOCK_USB0_CONTROL_OBSERVE_CLOCK_MASK 0x0000000f
-#define BCHP_CLKGEN_USB0_TOP_INST_OBSERVE_CLOCK_USB0_CONTROL_OBSERVE_CLOCK_SHIFT 0
-#define BCHP_CLKGEN_USB0_TOP_INST_OBSERVE_CLOCK_USB0_CONTROL_OBSERVE_CLOCK_DEFAULT 0x00000000
-
-/***************************************************************************
- *USMAC_TC8X_DAVIC_TOP_INST_CLOCK_DISABLE - Disable USMAC_TC8X_DAVIC_TOP_INST's clocks
- ***************************************************************************/
-/* CLKGEN :: USMAC_TC8X_DAVIC_TOP_INST_CLOCK_DISABLE :: reserved0 [31:03] */
-#define BCHP_CLKGEN_USMAC_TC8X_DAVIC_TOP_INST_CLOCK_DISABLE_reserved0_MASK 0xfffffff8
-#define BCHP_CLKGEN_USMAC_TC8X_DAVIC_TOP_INST_CLOCK_DISABLE_reserved0_SHIFT 3
-
-/* CLKGEN :: USMAC_TC8X_DAVIC_TOP_INST_CLOCK_DISABLE :: DISABLE_USMAC_TX_CLOCK [02:02] */
-#define BCHP_CLKGEN_USMAC_TC8X_DAVIC_TOP_INST_CLOCK_DISABLE_DISABLE_USMAC_TX_CLOCK_MASK 0x00000004
-#define BCHP_CLKGEN_USMAC_TC8X_DAVIC_TOP_INST_CLOCK_DISABLE_DISABLE_USMAC_TX_CLOCK_SHIFT 2
-#define BCHP_CLKGEN_USMAC_TC8X_DAVIC_TOP_INST_CLOCK_DISABLE_DISABLE_USMAC_TX_CLOCK_DEFAULT 0x00000000
-
-/* CLKGEN :: USMAC_TC8X_DAVIC_TOP_INST_CLOCK_DISABLE :: DISABLE_USMAC_RX_CLOCK [01:01] */
-#define BCHP_CLKGEN_USMAC_TC8X_DAVIC_TOP_INST_CLOCK_DISABLE_DISABLE_USMAC_RX_CLOCK_MASK 0x00000002
-#define BCHP_CLKGEN_USMAC_TC8X_DAVIC_TOP_INST_CLOCK_DISABLE_DISABLE_USMAC_RX_CLOCK_SHIFT 1
-#define BCHP_CLKGEN_USMAC_TC8X_DAVIC_TOP_INST_CLOCK_DISABLE_DISABLE_USMAC_RX_CLOCK_DEFAULT 0x00000000
-
-/* CLKGEN :: USMAC_TC8X_DAVIC_TOP_INST_CLOCK_DISABLE :: DISABLE_USMAC_216_CLOCK [00:00] */
-#define BCHP_CLKGEN_USMAC_TC8X_DAVIC_TOP_INST_CLOCK_DISABLE_DISABLE_USMAC_216_CLOCK_MASK 0x00000001
-#define BCHP_CLKGEN_USMAC_TC8X_DAVIC_TOP_INST_CLOCK_DISABLE_DISABLE_USMAC_216_CLOCK_SHIFT 0
-#define BCHP_CLKGEN_USMAC_TC8X_DAVIC_TOP_INST_CLOCK_DISABLE_DISABLE_USMAC_216_CLOCK_DEFAULT 0x00000000
-
-/***************************************************************************
- *USMAC_TC8X_DAVIC_TOP_INST_CLOCK_DISABLE_STATUS - Clock Disable Status
- ***************************************************************************/
-/* CLKGEN :: USMAC_TC8X_DAVIC_TOP_INST_CLOCK_DISABLE_STATUS :: reserved0 [31:03] */
-#define BCHP_CLKGEN_USMAC_TC8X_DAVIC_TOP_INST_CLOCK_DISABLE_STATUS_reserved0_MASK 0xfffffff8
-#define BCHP_CLKGEN_USMAC_TC8X_DAVIC_TOP_INST_CLOCK_DISABLE_STATUS_reserved0_SHIFT 3
-
-/* CLKGEN :: USMAC_TC8X_DAVIC_TOP_INST_CLOCK_DISABLE_STATUS :: DISABLE_USMAC_TX_CLOCK_STATUS [02:02] */
-#define BCHP_CLKGEN_USMAC_TC8X_DAVIC_TOP_INST_CLOCK_DISABLE_STATUS_DISABLE_USMAC_TX_CLOCK_STATUS_MASK 0x00000004
-#define BCHP_CLKGEN_USMAC_TC8X_DAVIC_TOP_INST_CLOCK_DISABLE_STATUS_DISABLE_USMAC_TX_CLOCK_STATUS_SHIFT 2
-
-/* CLKGEN :: USMAC_TC8X_DAVIC_TOP_INST_CLOCK_DISABLE_STATUS :: DISABLE_USMAC_RX_CLOCK_STATUS [01:01] */
-#define BCHP_CLKGEN_USMAC_TC8X_DAVIC_TOP_INST_CLOCK_DISABLE_STATUS_DISABLE_USMAC_RX_CLOCK_STATUS_MASK 0x00000002
-#define BCHP_CLKGEN_USMAC_TC8X_DAVIC_TOP_INST_CLOCK_DISABLE_STATUS_DISABLE_USMAC_RX_CLOCK_STATUS_SHIFT 1
-
-/* CLKGEN :: USMAC_TC8X_DAVIC_TOP_INST_CLOCK_DISABLE_STATUS :: DISABLE_USMAC_216_CLOCK_STATUS [00:00] */
-#define BCHP_CLKGEN_USMAC_TC8X_DAVIC_TOP_INST_CLOCK_DISABLE_STATUS_DISABLE_USMAC_216_CLOCK_STATUS_MASK 0x00000001
-#define BCHP_CLKGEN_USMAC_TC8X_DAVIC_TOP_INST_CLOCK_DISABLE_STATUS_DISABLE_USMAC_216_CLOCK_STATUS_SHIFT 0
-
-/***************************************************************************
- *USMAC_TC8X_DAVIC_TOP_INST_CLOCK_ENABLE - Usmac tc8x davic top inst clock enable
- ***************************************************************************/
-/* CLKGEN :: USMAC_TC8X_DAVIC_TOP_INST_CLOCK_ENABLE :: reserved0 [31:01] */
-#define BCHP_CLKGEN_USMAC_TC8X_DAVIC_TOP_INST_CLOCK_ENABLE_reserved0_MASK 0xfffffffe
-#define BCHP_CLKGEN_USMAC_TC8X_DAVIC_TOP_INST_CLOCK_ENABLE_reserved0_SHIFT 1
-
-/* CLKGEN :: USMAC_TC8X_DAVIC_TOP_INST_CLOCK_ENABLE :: USMAC_54_CLOCK_ENABLE [00:00] */
-#define BCHP_CLKGEN_USMAC_TC8X_DAVIC_TOP_INST_CLOCK_ENABLE_USMAC_54_CLOCK_ENABLE_MASK 0x00000001
-#define BCHP_CLKGEN_USMAC_TC8X_DAVIC_TOP_INST_CLOCK_ENABLE_USMAC_54_CLOCK_ENABLE_SHIFT 0
-#define BCHP_CLKGEN_USMAC_TC8X_DAVIC_TOP_INST_CLOCK_ENABLE_USMAC_54_CLOCK_ENABLE_DEFAULT 0x00000001
-
-/***************************************************************************
- *USMAC_TC8X_DAVIC_TOP_INST_CLOCK_ENABLE_STATUS - Clock Enable Status
- ***************************************************************************/
-/* CLKGEN :: USMAC_TC8X_DAVIC_TOP_INST_CLOCK_ENABLE_STATUS :: reserved0 [31:01] */
-#define BCHP_CLKGEN_USMAC_TC8X_DAVIC_TOP_INST_CLOCK_ENABLE_STATUS_reserved0_MASK 0xfffffffe
-#define BCHP_CLKGEN_USMAC_TC8X_DAVIC_TOP_INST_CLOCK_ENABLE_STATUS_reserved0_SHIFT 1
-
-/* CLKGEN :: USMAC_TC8X_DAVIC_TOP_INST_CLOCK_ENABLE_STATUS :: USMAC_54_CLOCK_ENABLE_STATUS [00:00] */
-#define BCHP_CLKGEN_USMAC_TC8X_DAVIC_TOP_INST_CLOCK_ENABLE_STATUS_USMAC_54_CLOCK_ENABLE_STATUS_MASK 0x00000001
-#define BCHP_CLKGEN_USMAC_TC8X_DAVIC_TOP_INST_CLOCK_ENABLE_STATUS_USMAC_54_CLOCK_ENABLE_STATUS_SHIFT 0
-
-/***************************************************************************
- *US_TOP_INST_CLOCK_ENABLE - Us top inst clock enable
- ***************************************************************************/
-/* CLKGEN :: US_TOP_INST_CLOCK_ENABLE :: reserved0 [31:01] */
-#define BCHP_CLKGEN_US_TOP_INST_CLOCK_ENABLE_reserved0_MASK 0xfffffffe
-#define BCHP_CLKGEN_US_TOP_INST_CLOCK_ENABLE_reserved0_SHIFT 1
-
-/* CLKGEN :: US_TOP_INST_CLOCK_ENABLE :: US_54_CLOCK_ENABLE [00:00] */
-#define BCHP_CLKGEN_US_TOP_INST_CLOCK_ENABLE_US_54_CLOCK_ENABLE_MASK 0x00000001
-#define BCHP_CLKGEN_US_TOP_INST_CLOCK_ENABLE_US_54_CLOCK_ENABLE_SHIFT 0
-#define BCHP_CLKGEN_US_TOP_INST_CLOCK_ENABLE_US_54_CLOCK_ENABLE_DEFAULT 0x00000001
-
-/***************************************************************************
- *US_TOP_INST_CLOCK_ENABLE_STATUS - Clock Enable Status
- ***************************************************************************/
-/* CLKGEN :: US_TOP_INST_CLOCK_ENABLE_STATUS :: reserved0 [31:01] */
-#define BCHP_CLKGEN_US_TOP_INST_CLOCK_ENABLE_STATUS_reserved0_MASK 0xfffffffe
-#define BCHP_CLKGEN_US_TOP_INST_CLOCK_ENABLE_STATUS_reserved0_SHIFT 1
-
-/* CLKGEN :: US_TOP_INST_CLOCK_ENABLE_STATUS :: US_54_CLOCK_ENABLE_STATUS [00:00] */
-#define BCHP_CLKGEN_US_TOP_INST_CLOCK_ENABLE_STATUS_US_54_CLOCK_ENABLE_STATUS_MASK 0x00000001
-#define BCHP_CLKGEN_US_TOP_INST_CLOCK_ENABLE_STATUS_US_54_CLOCK_ENABLE_STATUS_SHIFT 0
-
-/***************************************************************************
- *UTP_CRYPTO_SEGDMA_TOP_INST_CLOCK_DISABLE - Disable UTP_CRYPTO_SEGDMA_TOP_INST's clocks
- ***************************************************************************/
-/* CLKGEN :: UTP_CRYPTO_SEGDMA_TOP_INST_CLOCK_DISABLE :: reserved0 [31:04] */
-#define BCHP_CLKGEN_UTP_CRYPTO_SEGDMA_TOP_INST_CLOCK_DISABLE_reserved0_MASK 0xfffffff0
-#define BCHP_CLKGEN_UTP_CRYPTO_SEGDMA_TOP_INST_CLOCK_DISABLE_reserved0_SHIFT 4
-
-/* CLKGEN :: UTP_CRYPTO_SEGDMA_TOP_INST_CLOCK_DISABLE :: DISABLE_UTP_USM_54_CLOCK [03:03] */
-#define BCHP_CLKGEN_UTP_CRYPTO_SEGDMA_TOP_INST_CLOCK_DISABLE_DISABLE_UTP_USM_54_CLOCK_MASK 0x00000008
-#define BCHP_CLKGEN_UTP_CRYPTO_SEGDMA_TOP_INST_CLOCK_DISABLE_DISABLE_UTP_USM_54_CLOCK_SHIFT 3
-#define BCHP_CLKGEN_UTP_CRYPTO_SEGDMA_TOP_INST_CLOCK_DISABLE_DISABLE_UTP_USM_54_CLOCK_DEFAULT 0x00000000
-
-/* CLKGEN :: UTP_CRYPTO_SEGDMA_TOP_INST_CLOCK_DISABLE :: DISABLE_UTP_278_CLOCK [02:02] */
-#define BCHP_CLKGEN_UTP_CRYPTO_SEGDMA_TOP_INST_CLOCK_DISABLE_DISABLE_UTP_278_CLOCK_MASK 0x00000004
-#define BCHP_CLKGEN_UTP_CRYPTO_SEGDMA_TOP_INST_CLOCK_DISABLE_DISABLE_UTP_278_CLOCK_SHIFT 2
-#define BCHP_CLKGEN_UTP_CRYPTO_SEGDMA_TOP_INST_CLOCK_DISABLE_DISABLE_UTP_278_CLOCK_DEFAULT 0x00000000
-
-/* CLKGEN :: UTP_CRYPTO_SEGDMA_TOP_INST_CLOCK_DISABLE :: DISABLE_UTP_25_CLOCK [01:01] */
-#define BCHP_CLKGEN_UTP_CRYPTO_SEGDMA_TOP_INST_CLOCK_DISABLE_DISABLE_UTP_25_CLOCK_MASK 0x00000002
-#define BCHP_CLKGEN_UTP_CRYPTO_SEGDMA_TOP_INST_CLOCK_DISABLE_DISABLE_UTP_25_CLOCK_SHIFT 1
-#define BCHP_CLKGEN_UTP_CRYPTO_SEGDMA_TOP_INST_CLOCK_DISABLE_DISABLE_UTP_25_CLOCK_DEFAULT 0x00000000
-
-/* CLKGEN :: UTP_CRYPTO_SEGDMA_TOP_INST_CLOCK_DISABLE :: DISABLE_CG_TCK_SCAN_CLOCK [00:00] */
-#define BCHP_CLKGEN_UTP_CRYPTO_SEGDMA_TOP_INST_CLOCK_DISABLE_DISABLE_CG_TCK_SCAN_CLOCK_MASK 0x00000001
-#define BCHP_CLKGEN_UTP_CRYPTO_SEGDMA_TOP_INST_CLOCK_DISABLE_DISABLE_CG_TCK_SCAN_CLOCK_SHIFT 0
-#define BCHP_CLKGEN_UTP_CRYPTO_SEGDMA_TOP_INST_CLOCK_DISABLE_DISABLE_CG_TCK_SCAN_CLOCK_DEFAULT 0x00000000
-
-/***************************************************************************
- *UTP_CRYPTO_SEGDMA_TOP_INST_CLOCK_DISABLE_STATUS - Clock Disable Status
- ***************************************************************************/
-/* CLKGEN :: UTP_CRYPTO_SEGDMA_TOP_INST_CLOCK_DISABLE_STATUS :: reserved0 [31:04] */
-#define BCHP_CLKGEN_UTP_CRYPTO_SEGDMA_TOP_INST_CLOCK_DISABLE_STATUS_reserved0_MASK 0xfffffff0
-#define BCHP_CLKGEN_UTP_CRYPTO_SEGDMA_TOP_INST_CLOCK_DISABLE_STATUS_reserved0_SHIFT 4
-
-/* CLKGEN :: UTP_CRYPTO_SEGDMA_TOP_INST_CLOCK_DISABLE_STATUS :: DISABLE_UTP_USM_54_CLOCK_STATUS [03:03] */
-#define BCHP_CLKGEN_UTP_CRYPTO_SEGDMA_TOP_INST_CLOCK_DISABLE_STATUS_DISABLE_UTP_USM_54_CLOCK_STATUS_MASK 0x00000008
-#define BCHP_CLKGEN_UTP_CRYPTO_SEGDMA_TOP_INST_CLOCK_DISABLE_STATUS_DISABLE_UTP_USM_54_CLOCK_STATUS_SHIFT 3
-
-/* CLKGEN :: UTP_CRYPTO_SEGDMA_TOP_INST_CLOCK_DISABLE_STATUS :: DISABLE_UTP_278_CLOCK_STATUS [02:02] */
-#define BCHP_CLKGEN_UTP_CRYPTO_SEGDMA_TOP_INST_CLOCK_DISABLE_STATUS_DISABLE_UTP_278_CLOCK_STATUS_MASK 0x00000004
-#define BCHP_CLKGEN_UTP_CRYPTO_SEGDMA_TOP_INST_CLOCK_DISABLE_STATUS_DISABLE_UTP_278_CLOCK_STATUS_SHIFT 2
-
-/* CLKGEN :: UTP_CRYPTO_SEGDMA_TOP_INST_CLOCK_DISABLE_STATUS :: DISABLE_UTP_25_CLOCK_STATUS [01:01] */
-#define BCHP_CLKGEN_UTP_CRYPTO_SEGDMA_TOP_INST_CLOCK_DISABLE_STATUS_DISABLE_UTP_25_CLOCK_STATUS_MASK 0x00000002
-#define BCHP_CLKGEN_UTP_CRYPTO_SEGDMA_TOP_INST_CLOCK_DISABLE_STATUS_DISABLE_UTP_25_CLOCK_STATUS_SHIFT 1
-
-/* CLKGEN :: UTP_CRYPTO_SEGDMA_TOP_INST_CLOCK_DISABLE_STATUS :: DISABLE_CG_TCK_SCAN_CLOCK_STATUS [00:00] */
-#define BCHP_CLKGEN_UTP_CRYPTO_SEGDMA_TOP_INST_CLOCK_DISABLE_STATUS_DISABLE_CG_TCK_SCAN_CLOCK_STATUS_MASK 0x00000001
-#define BCHP_CLKGEN_UTP_CRYPTO_SEGDMA_TOP_INST_CLOCK_DISABLE_STATUS_DISABLE_CG_TCK_SCAN_CLOCK_STATUS_SHIFT 0
-
-/***************************************************************************
- *UTP_CRYPTO_SEGDMA_TOP_INST_CLOCK_ENABLE - Utp crypto segdma top inst clock enable
- ***************************************************************************/
-/* CLKGEN :: UTP_CRYPTO_SEGDMA_TOP_INST_CLOCK_ENABLE :: reserved0 [31:01] */
-#define BCHP_CLKGEN_UTP_CRYPTO_SEGDMA_TOP_INST_CLOCK_ENABLE_reserved0_MASK 0xfffffffe
-#define BCHP_CLKGEN_UTP_CRYPTO_SEGDMA_TOP_INST_CLOCK_ENABLE_reserved0_SHIFT 1
-
-/* CLKGEN :: UTP_CRYPTO_SEGDMA_TOP_INST_CLOCK_ENABLE :: UTP_54_CLOCK_ENABLE [00:00] */
-#define BCHP_CLKGEN_UTP_CRYPTO_SEGDMA_TOP_INST_CLOCK_ENABLE_UTP_54_CLOCK_ENABLE_MASK 0x00000001
-#define BCHP_CLKGEN_UTP_CRYPTO_SEGDMA_TOP_INST_CLOCK_ENABLE_UTP_54_CLOCK_ENABLE_SHIFT 0
-#define BCHP_CLKGEN_UTP_CRYPTO_SEGDMA_TOP_INST_CLOCK_ENABLE_UTP_54_CLOCK_ENABLE_DEFAULT 0x00000001
-
-/***************************************************************************
- *UTP_CRYPTO_SEGDMA_TOP_INST_CLOCK_ENABLE_STATUS - Clock Enable Status
- ***************************************************************************/
-/* CLKGEN :: UTP_CRYPTO_SEGDMA_TOP_INST_CLOCK_ENABLE_STATUS :: reserved0 [31:01] */
-#define BCHP_CLKGEN_UTP_CRYPTO_SEGDMA_TOP_INST_CLOCK_ENABLE_STATUS_reserved0_MASK 0xfffffffe
-#define BCHP_CLKGEN_UTP_CRYPTO_SEGDMA_TOP_INST_CLOCK_ENABLE_STATUS_reserved0_SHIFT 1
-
-/* CLKGEN :: UTP_CRYPTO_SEGDMA_TOP_INST_CLOCK_ENABLE_STATUS :: UTP_54_CLOCK_ENABLE_STATUS [00:00] */
-#define BCHP_CLKGEN_UTP_CRYPTO_SEGDMA_TOP_INST_CLOCK_ENABLE_STATUS_UTP_54_CLOCK_ENABLE_STATUS_MASK 0x00000001
-#define BCHP_CLKGEN_UTP_CRYPTO_SEGDMA_TOP_INST_CLOCK_ENABLE_STATUS_UTP_54_CLOCK_ENABLE_STATUS_SHIFT 0
-
-/***************************************************************************
- *V3D_TOP_INST_CLOCK_ENABLE - V3d top inst clock enable
- ***************************************************************************/
-/* CLKGEN :: V3D_TOP_INST_CLOCK_ENABLE :: reserved0 [31:04] */
-#define BCHP_CLKGEN_V3D_TOP_INST_CLOCK_ENABLE_reserved0_MASK 0xfffffff0
-#define BCHP_CLKGEN_V3D_TOP_INST_CLOCK_ENABLE_reserved0_SHIFT 4
-
-/* CLKGEN :: V3D_TOP_INST_CLOCK_ENABLE :: V3D_SCB_CLOCK_ENABLE [03:03] */
-#define BCHP_CLKGEN_V3D_TOP_INST_CLOCK_ENABLE_V3D_SCB_CLOCK_ENABLE_MASK 0x00000008
-#define BCHP_CLKGEN_V3D_TOP_INST_CLOCK_ENABLE_V3D_SCB_CLOCK_ENABLE_SHIFT 3
-#define BCHP_CLKGEN_V3D_TOP_INST_CLOCK_ENABLE_V3D_SCB_CLOCK_ENABLE_DEFAULT 0x00000001
-
-/* CLKGEN :: V3D_TOP_INST_CLOCK_ENABLE :: V3D_GISB_CLOCK_ENABLE [02:02] */
-#define BCHP_CLKGEN_V3D_TOP_INST_CLOCK_ENABLE_V3D_GISB_CLOCK_ENABLE_MASK 0x00000004
-#define BCHP_CLKGEN_V3D_TOP_INST_CLOCK_ENABLE_V3D_GISB_CLOCK_ENABLE_SHIFT 2
-#define BCHP_CLKGEN_V3D_TOP_INST_CLOCK_ENABLE_V3D_GISB_CLOCK_ENABLE_DEFAULT 0x00000001
-
-/* CLKGEN :: V3D_TOP_INST_CLOCK_ENABLE :: V3D_CLOCK_ENABLE [01:01] */
-#define BCHP_CLKGEN_V3D_TOP_INST_CLOCK_ENABLE_V3D_CLOCK_ENABLE_MASK 0x00000002
-#define BCHP_CLKGEN_V3D_TOP_INST_CLOCK_ENABLE_V3D_CLOCK_ENABLE_SHIFT 1
-#define BCHP_CLKGEN_V3D_TOP_INST_CLOCK_ENABLE_V3D_CLOCK_ENABLE_DEFAULT 0x00000001
-
-/* CLKGEN :: V3D_TOP_INST_CLOCK_ENABLE :: V3D_54_CLOCK_ENABLE [00:00] */
-#define BCHP_CLKGEN_V3D_TOP_INST_CLOCK_ENABLE_V3D_54_CLOCK_ENABLE_MASK 0x00000001
-#define BCHP_CLKGEN_V3D_TOP_INST_CLOCK_ENABLE_V3D_54_CLOCK_ENABLE_SHIFT 0
-#define BCHP_CLKGEN_V3D_TOP_INST_CLOCK_ENABLE_V3D_54_CLOCK_ENABLE_DEFAULT 0x00000001
-
-/***************************************************************************
- *V3D_TOP_INST_CLOCK_ENABLE_STATUS - Clock Enable Status
- ***************************************************************************/
-/* CLKGEN :: V3D_TOP_INST_CLOCK_ENABLE_STATUS :: reserved0 [31:04] */
-#define BCHP_CLKGEN_V3D_TOP_INST_CLOCK_ENABLE_STATUS_reserved0_MASK 0xfffffff0
-#define BCHP_CLKGEN_V3D_TOP_INST_CLOCK_ENABLE_STATUS_reserved0_SHIFT 4
-
-/* CLKGEN :: V3D_TOP_INST_CLOCK_ENABLE_STATUS :: V3D_SCB_CLOCK_ENABLE_STATUS [03:03] */
-#define BCHP_CLKGEN_V3D_TOP_INST_CLOCK_ENABLE_STATUS_V3D_SCB_CLOCK_ENABLE_STATUS_MASK 0x00000008
-#define BCHP_CLKGEN_V3D_TOP_INST_CLOCK_ENABLE_STATUS_V3D_SCB_CLOCK_ENABLE_STATUS_SHIFT 3
-
-/* CLKGEN :: V3D_TOP_INST_CLOCK_ENABLE_STATUS :: V3D_GISB_CLOCK_ENABLE_STATUS [02:02] */
-#define BCHP_CLKGEN_V3D_TOP_INST_CLOCK_ENABLE_STATUS_V3D_GISB_CLOCK_ENABLE_STATUS_MASK 0x00000004
-#define BCHP_CLKGEN_V3D_TOP_INST_CLOCK_ENABLE_STATUS_V3D_GISB_CLOCK_ENABLE_STATUS_SHIFT 2
-
-/* CLKGEN :: V3D_TOP_INST_CLOCK_ENABLE_STATUS :: V3D_CLOCK_ENABLE_STATUS [01:01] */
-#define BCHP_CLKGEN_V3D_TOP_INST_CLOCK_ENABLE_STATUS_V3D_CLOCK_ENABLE_STATUS_MASK 0x00000002
-#define BCHP_CLKGEN_V3D_TOP_INST_CLOCK_ENABLE_STATUS_V3D_CLOCK_ENABLE_STATUS_SHIFT 1
-
-/* CLKGEN :: V3D_TOP_INST_CLOCK_ENABLE_STATUS :: V3D_54_CLOCK_ENABLE_STATUS [00:00] */
-#define BCHP_CLKGEN_V3D_TOP_INST_CLOCK_ENABLE_STATUS_V3D_54_CLOCK_ENABLE_STATUS_MASK 0x00000001
-#define BCHP_CLKGEN_V3D_TOP_INST_CLOCK_ENABLE_STATUS_V3D_54_CLOCK_ENABLE_STATUS_SHIFT 0
-
-/***************************************************************************
- *VEC_AIO_TOP_INST_CLOCK_DISABLE - Disable VEC_AIO_TOP_INST's clocks
- ***************************************************************************/
-/* CLKGEN :: VEC_AIO_TOP_INST_CLOCK_DISABLE :: reserved0 [31:05] */
-#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_DISABLE_reserved0_MASK 0xffffffe0
-#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_DISABLE_reserved0_SHIFT 5
-
-/* CLKGEN :: VEC_AIO_TOP_INST_CLOCK_DISABLE :: DISABLE_VEC_ITU656_0_CLOCK [04:04] */
-#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_DISABLE_DISABLE_VEC_ITU656_0_CLOCK_MASK 0x00000010
-#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_DISABLE_DISABLE_VEC_ITU656_0_CLOCK_SHIFT 4
-#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_DISABLE_DISABLE_VEC_ITU656_0_CLOCK_DEFAULT 0x00000000
-
-/* CLKGEN :: VEC_AIO_TOP_INST_CLOCK_DISABLE :: DISABLE_VEC_DACADC_CLOCK [03:03] */
-#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_DISABLE_DISABLE_VEC_DACADC_CLOCK_MASK 0x00000008
-#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_DISABLE_DISABLE_VEC_DACADC_CLOCK_SHIFT 3
-#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_DISABLE_DISABLE_VEC_DACADC_CLOCK_DEFAULT 0x00000000
-
-/* CLKGEN :: VEC_AIO_TOP_INST_CLOCK_DISABLE :: DISABLE_AUDIO_DAC_DSM_DEM_DIV8_CLOCK [02:02] */
-#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_DISABLE_DISABLE_AUDIO_DAC_DSM_DEM_DIV8_CLOCK_MASK 0x00000004
-#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_DISABLE_DISABLE_AUDIO_DAC_DSM_DEM_DIV8_CLOCK_SHIFT 2
-#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_DISABLE_DISABLE_AUDIO_DAC_DSM_DEM_DIV8_CLOCK_DEFAULT 0x00000000
-
-/* CLKGEN :: VEC_AIO_TOP_INST_CLOCK_DISABLE :: DISABLE_AUDIO_DAC_DSM_DEM_DIV2_CLOCK [01:01] */
-#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_DISABLE_DISABLE_AUDIO_DAC_DSM_DEM_DIV2_CLOCK_MASK 0x00000002
-#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_DISABLE_DISABLE_AUDIO_DAC_DSM_DEM_DIV2_CLOCK_SHIFT 1
-#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_DISABLE_DISABLE_AUDIO_DAC_DSM_DEM_DIV2_CLOCK_DEFAULT 0x00000000
-
-/* CLKGEN :: VEC_AIO_TOP_INST_CLOCK_DISABLE :: DISABLE_AUDIO_DAC_DSM_DEM_27_CLOCK [00:00] */
-#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_DISABLE_DISABLE_AUDIO_DAC_DSM_DEM_27_CLOCK_MASK 0x00000001
-#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_DISABLE_DISABLE_AUDIO_DAC_DSM_DEM_27_CLOCK_SHIFT 0
-#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_DISABLE_DISABLE_AUDIO_DAC_DSM_DEM_27_CLOCK_DEFAULT 0x00000000
-
-/***************************************************************************
- *VEC_AIO_TOP_INST_CLOCK_DISABLE_STATUS - Clock Disable Status
- ***************************************************************************/
-/* CLKGEN :: VEC_AIO_TOP_INST_CLOCK_DISABLE_STATUS :: reserved0 [31:05] */
-#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_DISABLE_STATUS_reserved0_MASK 0xffffffe0
-#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_DISABLE_STATUS_reserved0_SHIFT 5
-
-/* CLKGEN :: VEC_AIO_TOP_INST_CLOCK_DISABLE_STATUS :: DISABLE_VEC_ITU656_0_CLOCK_STATUS [04:04] */
-#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_DISABLE_STATUS_DISABLE_VEC_ITU656_0_CLOCK_STATUS_MASK 0x00000010
-#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_DISABLE_STATUS_DISABLE_VEC_ITU656_0_CLOCK_STATUS_SHIFT 4
-
-/* CLKGEN :: VEC_AIO_TOP_INST_CLOCK_DISABLE_STATUS :: DISABLE_VEC_DACADC_CLOCK_STATUS [03:03] */
-#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_DISABLE_STATUS_DISABLE_VEC_DACADC_CLOCK_STATUS_MASK 0x00000008
-#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_DISABLE_STATUS_DISABLE_VEC_DACADC_CLOCK_STATUS_SHIFT 3
-
-/* CLKGEN :: VEC_AIO_TOP_INST_CLOCK_DISABLE_STATUS :: DISABLE_AUDIO_DAC_DSM_DEM_DIV8_CLOCK_STATUS [02:02] */
-#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_DISABLE_STATUS_DISABLE_AUDIO_DAC_DSM_DEM_DIV8_CLOCK_STATUS_MASK 0x00000004
-#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_DISABLE_STATUS_DISABLE_AUDIO_DAC_DSM_DEM_DIV8_CLOCK_STATUS_SHIFT 2
-
-/* CLKGEN :: VEC_AIO_TOP_INST_CLOCK_DISABLE_STATUS :: DISABLE_AUDIO_DAC_DSM_DEM_DIV2_CLOCK_STATUS [01:01] */
-#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_DISABLE_STATUS_DISABLE_AUDIO_DAC_DSM_DEM_DIV2_CLOCK_STATUS_MASK 0x00000002
-#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_DISABLE_STATUS_DISABLE_AUDIO_DAC_DSM_DEM_DIV2_CLOCK_STATUS_SHIFT 1
-
-/* CLKGEN :: VEC_AIO_TOP_INST_CLOCK_DISABLE_STATUS :: DISABLE_AUDIO_DAC_DSM_DEM_27_CLOCK_STATUS [00:00] */
-#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_DISABLE_STATUS_DISABLE_AUDIO_DAC_DSM_DEM_27_CLOCK_STATUS_MASK 0x00000001
-#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_DISABLE_STATUS_DISABLE_AUDIO_DAC_DSM_DEM_27_CLOCK_STATUS_SHIFT 0
-
-/***************************************************************************
- *VEC_AIO_TOP_INST_CLOCK_ENABLE - Vec aio top inst clock enable
- ***************************************************************************/
-/* CLKGEN :: VEC_AIO_TOP_INST_CLOCK_ENABLE :: reserved0 [31:09] */
-#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_reserved0_MASK 0xfffffe00
-#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_reserved0_SHIFT 9
-
-/* CLKGEN :: VEC_AIO_TOP_INST_CLOCK_ENABLE :: VEC_SCB_CLOCK_ENABLE [08:08] */
-#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC_SCB_CLOCK_ENABLE_MASK 0x00000100
-#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC_SCB_CLOCK_ENABLE_SHIFT 8
-#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC_SCB_CLOCK_ENABLE_DEFAULT 0x00000001
-
-/* CLKGEN :: VEC_AIO_TOP_INST_CLOCK_ENABLE :: VEC_QDAC_BVB_CLOCK_ENABLE [07:07] */
-#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC_QDAC_BVB_CLOCK_ENABLE_MASK 0x00000080
-#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC_QDAC_BVB_CLOCK_ENABLE_SHIFT 7
-#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC_QDAC_BVB_CLOCK_ENABLE_DEFAULT 0x00000001
-
-/* CLKGEN :: VEC_AIO_TOP_INST_CLOCK_ENABLE :: VEC_BVB_CLOCK_ENABLE [06:06] */
-#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC_BVB_CLOCK_ENABLE_MASK 0x00000040
-#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC_BVB_CLOCK_ENABLE_SHIFT 6
-#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC_BVB_CLOCK_ENABLE_DEFAULT 0x00000001
-
-/* CLKGEN :: VEC_AIO_TOP_INST_CLOCK_ENABLE :: VEC_AIO_54_CLOCK_ENABLE [05:05] */
-#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC_AIO_54_CLOCK_ENABLE_MASK 0x00000020
-#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC_AIO_54_CLOCK_ENABLE_SHIFT 5
-#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC_AIO_54_CLOCK_ENABLE_DEFAULT 0x00000001
-
-/* CLKGEN :: VEC_AIO_TOP_INST_CLOCK_ENABLE :: VEC_324_CLOCK_ENABLE [04:04] */
-#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC_324_CLOCK_ENABLE_MASK 0x00000010
-#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC_324_CLOCK_ENABLE_SHIFT 4
-#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC_324_CLOCK_ENABLE_DEFAULT 0x00000001
-
-/* CLKGEN :: VEC_AIO_TOP_INST_CLOCK_ENABLE :: VEC_108_CLOCK_ENABLE [03:03] */
-#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC_108_CLOCK_ENABLE_MASK 0x00000008
-#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC_108_CLOCK_ENABLE_SHIFT 3
-#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC_108_CLOCK_ENABLE_DEFAULT 0x00000001
-
-/* CLKGEN :: VEC_AIO_TOP_INST_CLOCK_ENABLE :: AIO_ALTERNATE_SCB_CLOCK_ENABLE [02:02] */
-#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_AIO_ALTERNATE_SCB_CLOCK_ENABLE_MASK 0x00000004
-#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_AIO_ALTERNATE_SCB_CLOCK_ENABLE_SHIFT 2
-#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_AIO_ALTERNATE_SCB_CLOCK_ENABLE_DEFAULT 0x00000001
-
-/* CLKGEN :: VEC_AIO_TOP_INST_CLOCK_ENABLE :: AIO_ALTERNATE_108_3_CLOCK_ENABLE [01:01] */
-#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_AIO_ALTERNATE_108_3_CLOCK_ENABLE_MASK 0x00000002
-#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_AIO_ALTERNATE_108_3_CLOCK_ENABLE_SHIFT 1
-#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_AIO_ALTERNATE_108_3_CLOCK_ENABLE_DEFAULT 0x00000001
-
-/* CLKGEN :: VEC_AIO_TOP_INST_CLOCK_ENABLE :: AIO_ALTERNATE_108_2_CLOCK_ENABLE [00:00] */
-#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_AIO_ALTERNATE_108_2_CLOCK_ENABLE_MASK 0x00000001
-#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_AIO_ALTERNATE_108_2_CLOCK_ENABLE_SHIFT 0
-#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_AIO_ALTERNATE_108_2_CLOCK_ENABLE_DEFAULT 0x00000001
-
-/***************************************************************************
- *VEC_AIO_TOP_INST_CLOCK_ENABLE_STATUS - Clock Enable Status
- ***************************************************************************/
-/* CLKGEN :: VEC_AIO_TOP_INST_CLOCK_ENABLE_STATUS :: reserved0 [31:09] */
-#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_STATUS_reserved0_MASK 0xfffffe00
-#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_STATUS_reserved0_SHIFT 9
-
-/* CLKGEN :: VEC_AIO_TOP_INST_CLOCK_ENABLE_STATUS :: VEC_SCB_CLOCK_ENABLE_STATUS [08:08] */
-#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_STATUS_VEC_SCB_CLOCK_ENABLE_STATUS_MASK 0x00000100
-#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_STATUS_VEC_SCB_CLOCK_ENABLE_STATUS_SHIFT 8
-
-/* CLKGEN :: VEC_AIO_TOP_INST_CLOCK_ENABLE_STATUS :: VEC_QDAC_BVB_CLOCK_ENABLE_STATUS [07:07] */
-#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_STATUS_VEC_QDAC_BVB_CLOCK_ENABLE_STATUS_MASK 0x00000080
-#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_STATUS_VEC_QDAC_BVB_CLOCK_ENABLE_STATUS_SHIFT 7
-
-/* CLKGEN :: VEC_AIO_TOP_INST_CLOCK_ENABLE_STATUS :: VEC_BVB_CLOCK_ENABLE_STATUS [06:06] */
-#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_STATUS_VEC_BVB_CLOCK_ENABLE_STATUS_MASK 0x00000040
-#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_STATUS_VEC_BVB_CLOCK_ENABLE_STATUS_SHIFT 6
-
-/* CLKGEN :: VEC_AIO_TOP_INST_CLOCK_ENABLE_STATUS :: VEC_AIO_54_CLOCK_ENABLE_STATUS [05:05] */
-#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_STATUS_VEC_AIO_54_CLOCK_ENABLE_STATUS_MASK 0x00000020
-#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_STATUS_VEC_AIO_54_CLOCK_ENABLE_STATUS_SHIFT 5
-
-/* CLKGEN :: VEC_AIO_TOP_INST_CLOCK_ENABLE_STATUS :: VEC_324_CLOCK_ENABLE_STATUS [04:04] */
-#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_STATUS_VEC_324_CLOCK_ENABLE_STATUS_MASK 0x00000010
-#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_STATUS_VEC_324_CLOCK_ENABLE_STATUS_SHIFT 4
-
-/* CLKGEN :: VEC_AIO_TOP_INST_CLOCK_ENABLE_STATUS :: VEC_108_CLOCK_ENABLE_STATUS [03:03] */
-#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_STATUS_VEC_108_CLOCK_ENABLE_STATUS_MASK 0x00000008
-#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_STATUS_VEC_108_CLOCK_ENABLE_STATUS_SHIFT 3
-
-/* CLKGEN :: VEC_AIO_TOP_INST_CLOCK_ENABLE_STATUS :: AIO_ALTERNATE_SCB_CLOCK_ENABLE_STATUS [02:02] */
-#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_STATUS_AIO_ALTERNATE_SCB_CLOCK_ENABLE_STATUS_MASK 0x00000004
-#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_STATUS_AIO_ALTERNATE_SCB_CLOCK_ENABLE_STATUS_SHIFT 2
-
-/* CLKGEN :: VEC_AIO_TOP_INST_CLOCK_ENABLE_STATUS :: AIO_ALTERNATE_108_3_CLOCK_ENABLE_STATUS [01:01] */
-#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_STATUS_AIO_ALTERNATE_108_3_CLOCK_ENABLE_STATUS_MASK 0x00000002
-#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_STATUS_AIO_ALTERNATE_108_3_CLOCK_ENABLE_STATUS_SHIFT 1
-
-/* CLKGEN :: VEC_AIO_TOP_INST_CLOCK_ENABLE_STATUS :: AIO_ALTERNATE_108_2_CLOCK_ENABLE_STATUS [00:00] */
-#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_STATUS_AIO_ALTERNATE_108_2_CLOCK_ENABLE_STATUS_MASK 0x00000001
-#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_STATUS_AIO_ALTERNATE_108_2_CLOCK_ENABLE_STATUS_SHIFT 0
-
-/***************************************************************************
- *VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC_QDAC_INTF - Vec aio top inst clock enable vec qdac intf
- ***************************************************************************/
-/* CLKGEN :: VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC_QDAC_INTF :: reserved0 [31:01] */
-#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC_QDAC_INTF_reserved0_MASK 0xfffffffe
-#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC_QDAC_INTF_reserved0_SHIFT 1
-
-/* CLKGEN :: VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC_QDAC_INTF :: VEC_ALTERNATE_BVB_CLOCK_ENABLE_VEC_QDAC_INTF [00:00] */
-#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC_QDAC_INTF_VEC_ALTERNATE_BVB_CLOCK_ENABLE_VEC_QDAC_INTF_MASK 0x00000001
-#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC_QDAC_INTF_VEC_ALTERNATE_BVB_CLOCK_ENABLE_VEC_QDAC_INTF_SHIFT 0
-#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC_QDAC_INTF_VEC_ALTERNATE_BVB_CLOCK_ENABLE_VEC_QDAC_INTF_DEFAULT 0x00000001
-
-/***************************************************************************
- *VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC_QDAC_INTF_STATUS - Clock Enable Status
- ***************************************************************************/
-/* CLKGEN :: VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC_QDAC_INTF_STATUS :: reserved0 [31:01] */
-#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC_QDAC_INTF_STATUS_reserved0_MASK 0xfffffffe
-#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC_QDAC_INTF_STATUS_reserved0_SHIFT 1
-
-/* CLKGEN :: VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC_QDAC_INTF_STATUS :: VEC_ALTERNATE_BVB_CLOCK_ENABLE_VEC_QDAC_INTF_STATUS [00:00] */
-#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC_QDAC_INTF_STATUS_VEC_ALTERNATE_BVB_CLOCK_ENABLE_VEC_QDAC_INTF_STATUS_MASK 0x00000001
-#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC_QDAC_INTF_STATUS_VEC_ALTERNATE_BVB_CLOCK_ENABLE_VEC_QDAC_INTF_STATUS_SHIFT 0
-
-/***************************************************************************
- *VEC_AIO_TOP_INST_OBSERVE_CLOCK - Vec aio top inst observe clock
- ***************************************************************************/
-/* CLKGEN :: VEC_AIO_TOP_INST_OBSERVE_CLOCK :: reserved0 [31:12] */
-#define BCHP_CLKGEN_VEC_AIO_TOP_INST_OBSERVE_CLOCK_reserved0_MASK 0xfffff000
-#define BCHP_CLKGEN_VEC_AIO_TOP_INST_OBSERVE_CLOCK_reserved0_SHIFT 12
-
-/* CLKGEN :: VEC_AIO_TOP_INST_OBSERVE_CLOCK :: VEC_ENABLE_OBSERVE_CLOCK [11:11] */
-#define BCHP_CLKGEN_VEC_AIO_TOP_INST_OBSERVE_CLOCK_VEC_ENABLE_OBSERVE_CLOCK_MASK 0x00000800
-#define BCHP_CLKGEN_VEC_AIO_TOP_INST_OBSERVE_CLOCK_VEC_ENABLE_OBSERVE_CLOCK_SHIFT 11
-#define BCHP_CLKGEN_VEC_AIO_TOP_INST_OBSERVE_CLOCK_VEC_ENABLE_OBSERVE_CLOCK_DEFAULT 0x00000000
-
-/* CLKGEN :: VEC_AIO_TOP_INST_OBSERVE_CLOCK :: VEC_ENABLE_DIVIDER_OBSERVE_CLOCK [10:10] */
-#define BCHP_CLKGEN_VEC_AIO_TOP_INST_OBSERVE_CLOCK_VEC_ENABLE_DIVIDER_OBSERVE_CLOCK_MASK 0x00000400
-#define BCHP_CLKGEN_VEC_AIO_TOP_INST_OBSERVE_CLOCK_VEC_ENABLE_DIVIDER_OBSERVE_CLOCK_SHIFT 10
-#define BCHP_CLKGEN_VEC_AIO_TOP_INST_OBSERVE_CLOCK_VEC_ENABLE_DIVIDER_OBSERVE_CLOCK_DEFAULT 0x00000000
-
-/* CLKGEN :: VEC_AIO_TOP_INST_OBSERVE_CLOCK :: VEC_CONTROL_OBSERVE_CLOCK [09:06] */
-#define BCHP_CLKGEN_VEC_AIO_TOP_INST_OBSERVE_CLOCK_VEC_CONTROL_OBSERVE_CLOCK_MASK 0x000003c0
-#define BCHP_CLKGEN_VEC_AIO_TOP_INST_OBSERVE_CLOCK_VEC_CONTROL_OBSERVE_CLOCK_SHIFT 6
-#define BCHP_CLKGEN_VEC_AIO_TOP_INST_OBSERVE_CLOCK_VEC_CONTROL_OBSERVE_CLOCK_DEFAULT 0x00000000
-
-/* CLKGEN :: VEC_AIO_TOP_INST_OBSERVE_CLOCK :: AIO_ENABLE_OBSERVE_CLOCK [05:05] */
-#define BCHP_CLKGEN_VEC_AIO_TOP_INST_OBSERVE_CLOCK_AIO_ENABLE_OBSERVE_CLOCK_MASK 0x00000020
-#define BCHP_CLKGEN_VEC_AIO_TOP_INST_OBSERVE_CLOCK_AIO_ENABLE_OBSERVE_CLOCK_SHIFT 5
-#define BCHP_CLKGEN_VEC_AIO_TOP_INST_OBSERVE_CLOCK_AIO_ENABLE_OBSERVE_CLOCK_DEFAULT 0x00000000
-
-/* CLKGEN :: VEC_AIO_TOP_INST_OBSERVE_CLOCK :: AIO_ENABLE_DIVIDER_OBSERVE_CLOCK [04:04] */
-#define BCHP_CLKGEN_VEC_AIO_TOP_INST_OBSERVE_CLOCK_AIO_ENABLE_DIVIDER_OBSERVE_CLOCK_MASK 0x00000010
-#define BCHP_CLKGEN_VEC_AIO_TOP_INST_OBSERVE_CLOCK_AIO_ENABLE_DIVIDER_OBSERVE_CLOCK_SHIFT 4
-#define BCHP_CLKGEN_VEC_AIO_TOP_INST_OBSERVE_CLOCK_AIO_ENABLE_DIVIDER_OBSERVE_CLOCK_DEFAULT 0x00000000
-
-/* CLKGEN :: VEC_AIO_TOP_INST_OBSERVE_CLOCK :: AIO_CONTROL_OBSERVE_CLOCK [03:00] */
-#define BCHP_CLKGEN_VEC_AIO_TOP_INST_OBSERVE_CLOCK_AIO_CONTROL_OBSERVE_CLOCK_MASK 0x0000000f
-#define BCHP_CLKGEN_VEC_AIO_TOP_INST_OBSERVE_CLOCK_AIO_CONTROL_OBSERVE_CLOCK_SHIFT 0
-#define BCHP_CLKGEN_VEC_AIO_TOP_INST_OBSERVE_CLOCK_AIO_CONTROL_OBSERVE_CLOCK_DEFAULT 0x00000000
-
-/***************************************************************************
- *VICE2_0_INST_CLOCK_ENABLE - Vice2 0 inst clock enable
- ***************************************************************************/
-/* CLKGEN :: VICE2_0_INST_CLOCK_ENABLE :: reserved0 [31:06] */
-#define BCHP_CLKGEN_VICE2_0_INST_CLOCK_ENABLE_reserved0_MASK 0xffffffc0
-#define BCHP_CLKGEN_VICE2_0_INST_CLOCK_ENABLE_reserved0_SHIFT 6
-
-/* CLKGEN :: VICE2_0_INST_CLOCK_ENABLE :: VICE2_0_SCB_CLOCK_ENABLE [05:05] */
-#define BCHP_CLKGEN_VICE2_0_INST_CLOCK_ENABLE_VICE2_0_SCB_CLOCK_ENABLE_MASK 0x00000020
-#define BCHP_CLKGEN_VICE2_0_INST_CLOCK_ENABLE_VICE2_0_SCB_CLOCK_ENABLE_SHIFT 5
-#define BCHP_CLKGEN_VICE2_0_INST_CLOCK_ENABLE_VICE2_0_SCB_CLOCK_ENABLE_DEFAULT 0x00000001
-
-/* CLKGEN :: VICE2_0_INST_CLOCK_ENABLE :: VICE2_0_GISB_CLOCK_ENABLE [04:04] */
-#define BCHP_CLKGEN_VICE2_0_INST_CLOCK_ENABLE_VICE2_0_GISB_CLOCK_ENABLE_MASK 0x00000010
-#define BCHP_CLKGEN_VICE2_0_INST_CLOCK_ENABLE_VICE2_0_GISB_CLOCK_ENABLE_SHIFT 4
-#define BCHP_CLKGEN_VICE2_0_INST_CLOCK_ENABLE_VICE2_0_GISB_CLOCK_ENABLE_DEFAULT 0x00000001
-
-/* CLKGEN :: VICE2_0_INST_CLOCK_ENABLE :: VICE2_0_CORE_CLOCK_ENABLE [03:03] */
-#define BCHP_CLKGEN_VICE2_0_INST_CLOCK_ENABLE_VICE2_0_CORE_CLOCK_ENABLE_MASK 0x00000008
-#define BCHP_CLKGEN_VICE2_0_INST_CLOCK_ENABLE_VICE2_0_CORE_CLOCK_ENABLE_SHIFT 3
-#define BCHP_CLKGEN_VICE2_0_INST_CLOCK_ENABLE_VICE2_0_CORE_CLOCK_ENABLE_DEFAULT 0x00000001
-
-/* CLKGEN :: VICE2_0_INST_CLOCK_ENABLE :: VICE2_0_BVB_CLOCK_ENABLE [02:02] */
-#define BCHP_CLKGEN_VICE2_0_INST_CLOCK_ENABLE_VICE2_0_BVB_CLOCK_ENABLE_MASK 0x00000004
-#define BCHP_CLKGEN_VICE2_0_INST_CLOCK_ENABLE_VICE2_0_BVB_CLOCK_ENABLE_SHIFT 2
-#define BCHP_CLKGEN_VICE2_0_INST_CLOCK_ENABLE_VICE2_0_BVB_CLOCK_ENABLE_DEFAULT 0x00000001
-
-/* CLKGEN :: VICE2_0_INST_CLOCK_ENABLE :: VICE2_0_54_CLOCK_ENABLE [01:01] */
-#define BCHP_CLKGEN_VICE2_0_INST_CLOCK_ENABLE_VICE2_0_54_CLOCK_ENABLE_MASK 0x00000002
-#define BCHP_CLKGEN_VICE2_0_INST_CLOCK_ENABLE_VICE2_0_54_CLOCK_ENABLE_SHIFT 1
-#define BCHP_CLKGEN_VICE2_0_INST_CLOCK_ENABLE_VICE2_0_54_CLOCK_ENABLE_DEFAULT 0x00000001
-
-/* CLKGEN :: VICE2_0_INST_CLOCK_ENABLE :: VICE2_0_108_CLOCK_ENABLE [00:00] */
-#define BCHP_CLKGEN_VICE2_0_INST_CLOCK_ENABLE_VICE2_0_108_CLOCK_ENABLE_MASK 0x00000001
-#define BCHP_CLKGEN_VICE2_0_INST_CLOCK_ENABLE_VICE2_0_108_CLOCK_ENABLE_SHIFT 0
-#define BCHP_CLKGEN_VICE2_0_INST_CLOCK_ENABLE_VICE2_0_108_CLOCK_ENABLE_DEFAULT 0x00000001
-
-/***************************************************************************
- *VICE2_0_INST_CLOCK_ENABLE_STATUS - Clock Enable Status
- ***************************************************************************/
-/* CLKGEN :: VICE2_0_INST_CLOCK_ENABLE_STATUS :: reserved0 [31:06] */
-#define BCHP_CLKGEN_VICE2_0_INST_CLOCK_ENABLE_STATUS_reserved0_MASK 0xffffffc0
-#define BCHP_CLKGEN_VICE2_0_INST_CLOCK_ENABLE_STATUS_reserved0_SHIFT 6
-
-/* CLKGEN :: VICE2_0_INST_CLOCK_ENABLE_STATUS :: VICE2_0_SCB_CLOCK_ENABLE_STATUS [05:05] */
-#define BCHP_CLKGEN_VICE2_0_INST_CLOCK_ENABLE_STATUS_VICE2_0_SCB_CLOCK_ENABLE_STATUS_MASK 0x00000020
-#define BCHP_CLKGEN_VICE2_0_INST_CLOCK_ENABLE_STATUS_VICE2_0_SCB_CLOCK_ENABLE_STATUS_SHIFT 5
-
-/* CLKGEN :: VICE2_0_INST_CLOCK_ENABLE_STATUS :: VICE2_0_GISB_CLOCK_ENABLE_STATUS [04:04] */
-#define BCHP_CLKGEN_VICE2_0_INST_CLOCK_ENABLE_STATUS_VICE2_0_GISB_CLOCK_ENABLE_STATUS_MASK 0x00000010
-#define BCHP_CLKGEN_VICE2_0_INST_CLOCK_ENABLE_STATUS_VICE2_0_GISB_CLOCK_ENABLE_STATUS_SHIFT 4
-
-/* CLKGEN :: VICE2_0_INST_CLOCK_ENABLE_STATUS :: VICE2_0_CORE_CLOCK_ENABLE_STATUS [03:03] */
-#define BCHP_CLKGEN_VICE2_0_INST_CLOCK_ENABLE_STATUS_VICE2_0_CORE_CLOCK_ENABLE_STATUS_MASK 0x00000008
-#define BCHP_CLKGEN_VICE2_0_INST_CLOCK_ENABLE_STATUS_VICE2_0_CORE_CLOCK_ENABLE_STATUS_SHIFT 3
-
-/* CLKGEN :: VICE2_0_INST_CLOCK_ENABLE_STATUS :: VICE2_0_BVB_CLOCK_ENABLE_STATUS [02:02] */
-#define BCHP_CLKGEN_VICE2_0_INST_CLOCK_ENABLE_STATUS_VICE2_0_BVB_CLOCK_ENABLE_STATUS_MASK 0x00000004
-#define BCHP_CLKGEN_VICE2_0_INST_CLOCK_ENABLE_STATUS_VICE2_0_BVB_CLOCK_ENABLE_STATUS_SHIFT 2
-
-/* CLKGEN :: VICE2_0_INST_CLOCK_ENABLE_STATUS :: VICE2_0_54_CLOCK_ENABLE_STATUS [01:01] */
-#define BCHP_CLKGEN_VICE2_0_INST_CLOCK_ENABLE_STATUS_VICE2_0_54_CLOCK_ENABLE_STATUS_MASK 0x00000002
-#define BCHP_CLKGEN_VICE2_0_INST_CLOCK_ENABLE_STATUS_VICE2_0_54_CLOCK_ENABLE_STATUS_SHIFT 1
-
-/* CLKGEN :: VICE2_0_INST_CLOCK_ENABLE_STATUS :: VICE2_0_108_CLOCK_ENABLE_STATUS [00:00] */
-#define BCHP_CLKGEN_VICE2_0_INST_CLOCK_ENABLE_STATUS_VICE2_0_108_CLOCK_ENABLE_STATUS_MASK 0x00000001
-#define BCHP_CLKGEN_VICE2_0_INST_CLOCK_ENABLE_STATUS_VICE2_0_108_CLOCK_ENABLE_STATUS_SHIFT 0
-
-/***************************************************************************
- *VICE2_1_INST_CLOCK_ENABLE - Vice2 1 inst clock enable
- ***************************************************************************/
-/* CLKGEN :: VICE2_1_INST_CLOCK_ENABLE :: reserved0 [31:06] */
-#define BCHP_CLKGEN_VICE2_1_INST_CLOCK_ENABLE_reserved0_MASK 0xffffffc0
-#define BCHP_CLKGEN_VICE2_1_INST_CLOCK_ENABLE_reserved0_SHIFT 6
-
-/* CLKGEN :: VICE2_1_INST_CLOCK_ENABLE :: VICE2_1_SCB_CLOCK_ENABLE [05:05] */
-#define BCHP_CLKGEN_VICE2_1_INST_CLOCK_ENABLE_VICE2_1_SCB_CLOCK_ENABLE_MASK 0x00000020
-#define BCHP_CLKGEN_VICE2_1_INST_CLOCK_ENABLE_VICE2_1_SCB_CLOCK_ENABLE_SHIFT 5
-#define BCHP_CLKGEN_VICE2_1_INST_CLOCK_ENABLE_VICE2_1_SCB_CLOCK_ENABLE_DEFAULT 0x00000001
-
-/* CLKGEN :: VICE2_1_INST_CLOCK_ENABLE :: VICE2_1_GISB_CLOCK_ENABLE [04:04] */
-#define BCHP_CLKGEN_VICE2_1_INST_CLOCK_ENABLE_VICE2_1_GISB_CLOCK_ENABLE_MASK 0x00000010
-#define BCHP_CLKGEN_VICE2_1_INST_CLOCK_ENABLE_VICE2_1_GISB_CLOCK_ENABLE_SHIFT 4
-#define BCHP_CLKGEN_VICE2_1_INST_CLOCK_ENABLE_VICE2_1_GISB_CLOCK_ENABLE_DEFAULT 0x00000001
-
-/* CLKGEN :: VICE2_1_INST_CLOCK_ENABLE :: VICE2_1_CORE_CLOCK_ENABLE [03:03] */
-#define BCHP_CLKGEN_VICE2_1_INST_CLOCK_ENABLE_VICE2_1_CORE_CLOCK_ENABLE_MASK 0x00000008
-#define BCHP_CLKGEN_VICE2_1_INST_CLOCK_ENABLE_VICE2_1_CORE_CLOCK_ENABLE_SHIFT 3
-#define BCHP_CLKGEN_VICE2_1_INST_CLOCK_ENABLE_VICE2_1_CORE_CLOCK_ENABLE_DEFAULT 0x00000001
-
-/* CLKGEN :: VICE2_1_INST_CLOCK_ENABLE :: VICE2_1_BVB_CLOCK_ENABLE [02:02] */
-#define BCHP_CLKGEN_VICE2_1_INST_CLOCK_ENABLE_VICE2_1_BVB_CLOCK_ENABLE_MASK 0x00000004
-#define BCHP_CLKGEN_VICE2_1_INST_CLOCK_ENABLE_VICE2_1_BVB_CLOCK_ENABLE_SHIFT 2
-#define BCHP_CLKGEN_VICE2_1_INST_CLOCK_ENABLE_VICE2_1_BVB_CLOCK_ENABLE_DEFAULT 0x00000001
-
-/* CLKGEN :: VICE2_1_INST_CLOCK_ENABLE :: VICE2_1_54_CLOCK_ENABLE [01:01] */
-#define BCHP_CLKGEN_VICE2_1_INST_CLOCK_ENABLE_VICE2_1_54_CLOCK_ENABLE_MASK 0x00000002
-#define BCHP_CLKGEN_VICE2_1_INST_CLOCK_ENABLE_VICE2_1_54_CLOCK_ENABLE_SHIFT 1
-#define BCHP_CLKGEN_VICE2_1_INST_CLOCK_ENABLE_VICE2_1_54_CLOCK_ENABLE_DEFAULT 0x00000001
-
-/* CLKGEN :: VICE2_1_INST_CLOCK_ENABLE :: VICE2_1_108_CLOCK_ENABLE [00:00] */
-#define BCHP_CLKGEN_VICE2_1_INST_CLOCK_ENABLE_VICE2_1_108_CLOCK_ENABLE_MASK 0x00000001
-#define BCHP_CLKGEN_VICE2_1_INST_CLOCK_ENABLE_VICE2_1_108_CLOCK_ENABLE_SHIFT 0
-#define BCHP_CLKGEN_VICE2_1_INST_CLOCK_ENABLE_VICE2_1_108_CLOCK_ENABLE_DEFAULT 0x00000001
-
-/***************************************************************************
- *VICE2_1_INST_CLOCK_ENABLE_STATUS - Clock Enable Status
- ***************************************************************************/
-/* CLKGEN :: VICE2_1_INST_CLOCK_ENABLE_STATUS :: reserved0 [31:06] */
-#define BCHP_CLKGEN_VICE2_1_INST_CLOCK_ENABLE_STATUS_reserved0_MASK 0xffffffc0
-#define BCHP_CLKGEN_VICE2_1_INST_CLOCK_ENABLE_STATUS_reserved0_SHIFT 6
-
-/* CLKGEN :: VICE2_1_INST_CLOCK_ENABLE_STATUS :: VICE2_1_SCB_CLOCK_ENABLE_STATUS [05:05] */
-#define BCHP_CLKGEN_VICE2_1_INST_CLOCK_ENABLE_STATUS_VICE2_1_SCB_CLOCK_ENABLE_STATUS_MASK 0x00000020
-#define BCHP_CLKGEN_VICE2_1_INST_CLOCK_ENABLE_STATUS_VICE2_1_SCB_CLOCK_ENABLE_STATUS_SHIFT 5
-
-/* CLKGEN :: VICE2_1_INST_CLOCK_ENABLE_STATUS :: VICE2_1_GISB_CLOCK_ENABLE_STATUS [04:04] */
-#define BCHP_CLKGEN_VICE2_1_INST_CLOCK_ENABLE_STATUS_VICE2_1_GISB_CLOCK_ENABLE_STATUS_MASK 0x00000010
-#define BCHP_CLKGEN_VICE2_1_INST_CLOCK_ENABLE_STATUS_VICE2_1_GISB_CLOCK_ENABLE_STATUS_SHIFT 4
-
-/* CLKGEN :: VICE2_1_INST_CLOCK_ENABLE_STATUS :: VICE2_1_CORE_CLOCK_ENABLE_STATUS [03:03] */
-#define BCHP_CLKGEN_VICE2_1_INST_CLOCK_ENABLE_STATUS_VICE2_1_CORE_CLOCK_ENABLE_STATUS_MASK 0x00000008
-#define BCHP_CLKGEN_VICE2_1_INST_CLOCK_ENABLE_STATUS_VICE2_1_CORE_CLOCK_ENABLE_STATUS_SHIFT 3
-
-/* CLKGEN :: VICE2_1_INST_CLOCK_ENABLE_STATUS :: VICE2_1_BVB_CLOCK_ENABLE_STATUS [02:02] */
-#define BCHP_CLKGEN_VICE2_1_INST_CLOCK_ENABLE_STATUS_VICE2_1_BVB_CLOCK_ENABLE_STATUS_MASK 0x00000004
-#define BCHP_CLKGEN_VICE2_1_INST_CLOCK_ENABLE_STATUS_VICE2_1_BVB_CLOCK_ENABLE_STATUS_SHIFT 2
-
-/* CLKGEN :: VICE2_1_INST_CLOCK_ENABLE_STATUS :: VICE2_1_54_CLOCK_ENABLE_STATUS [01:01] */
-#define BCHP_CLKGEN_VICE2_1_INST_CLOCK_ENABLE_STATUS_VICE2_1_54_CLOCK_ENABLE_STATUS_MASK 0x00000002
-#define BCHP_CLKGEN_VICE2_1_INST_CLOCK_ENABLE_STATUS_VICE2_1_54_CLOCK_ENABLE_STATUS_SHIFT 1
-
-/* CLKGEN :: VICE2_1_INST_CLOCK_ENABLE_STATUS :: VICE2_1_108_CLOCK_ENABLE_STATUS [00:00] */
-#define BCHP_CLKGEN_VICE2_1_INST_CLOCK_ENABLE_STATUS_VICE2_1_108_CLOCK_ENABLE_STATUS_MASK 0x00000001
-#define BCHP_CLKGEN_VICE2_1_INST_CLOCK_ENABLE_STATUS_VICE2_1_108_CLOCK_ENABLE_STATUS_SHIFT 0
-
-#endif /* #ifndef BCHP_CLKGEN_H__ */
-
-/* End of File */
diff --git a/include/linux/brcmstb/7145a0/bchp_common.h b/include/linux/brcmstb/7145a0/bchp_common.h
deleted file mode 100644
index 3ff5906..0000000
--- a/include/linux/brcmstb/7145a0/bchp_common.h
+++ /dev/null
@@ -1,6163 +0,0 @@
-/***************************************************************************
- * Copyright (c) 1999-2014, Broadcom Corporation
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
- *
- * Module Description:
- * DO NOT EDIT THIS FILE DIRECTLY
- *
- * This module was generated magically with RDB from a source description
- * file. You must edit the source file for changes to be made to this file.
- *
- *
- * Date: Generated on Wed Sep 3 13:17:00 2014
- * Full Compile MD5 Checksum a8ee62ccf9dde43435c825f266da463d
- * (minus title and desc)
- * MD5 Checksum e373b364a1742e13a0f9eb15fd8aa94f
- *
- * Compiled with: RDB Utility combo_header.pl
- * RDB Parser 3.0
- * unknown unknown
- * Perl Interpreter 5.008005
- * Operating System linux
- *
- * Revision History:
- *
- * $brcm_Log: $
- *
- ***************************************************************************/
-
-#ifndef BCHP_COMMON_H__
-#define BCHP_COMMON_H__
-
-/**
- * m = memory, c = core, r = register, f = field, d = data.
- */
-#if !defined(GET_FIELD) && !defined(SET_FIELD)
-#define BRCM_MASK(c,r,f) c##_##r##_##f##_MASK
-#define BRCM_SHIFT(c,r,f) c##_##r##_##f##_SHIFT
-
-#define GET_FIELD(m,c,r,f) \
-((((m) & BRCM_MASK(c,r,f)) >> BRCM_SHIFT(c,r,f)))
-
-#define SET_FIELD(m,c,r,f,d) \
-((m) = (((m) & ~BRCM_MASK(c,r,f)) | ((((d)) << BRCM_SHIFT(c,r,f)) & BRCM_MASK(c,r,f))))
-
-#define SET_TYPE_FIELD(m,c,r,f,d) SET_FIELD(m,c,r,f,c##_##d)
-#define SET_NAME_FIELD(m,c,r,f,d) SET_FIELD(m,c,r,f,c##_##r##_##f##_##d)
-#define SET_VALUE_FIELD(m,c,r,f,d) SET_FIELD(m,c,r,f,d)
-
-#endif /* GET & SET */
-
-/***************************************************************************
- *BCM7145_A0
- ***************************************************************************/
-#define BCHP_PHYSICAL_OFFSET 0xd0000000
-#define BCHP_REGISTER_START 0x00400000 /* MBDMA_UNI3 is first */
-#define BCHP_REGISTER_END 0x20d3c000 /* RAAGA_DSP_MEM_SUBSYSTEM_1 is last */
-#define BCHP_REGISTER_SIZE 0x0824f000 /* Number of registers */
-
-/****************************************************************************
- * Core instance register start address.
- ***************************************************************************/
-#define BCHP_MBDMA_UNI3_REG_START 0x00400000
-#define BCHP_MBDMA_UNI3_REG_END 0x00400508
-#define BCHP_UNIMAC_INTERFACE0_UNI3_REG_START 0x00400600
-#define BCHP_UNIMAC_INTERFACE0_UNI3_REG_END 0x00400710
-#define BCHP_UNIMAC_CORE0_UNI3_REG_START 0x00400800
-#define BCHP_UNIMAC_CORE0_UNI3_REG_END 0x00400b64
-#define BCHP_MIB0_UNI3_REG_START 0x00400c00
-#define BCHP_MIB0_UNI3_REG_END 0x00400cf4
-#define BCHP_HFB0_UNI3_REG_START 0x00401000
-#define BCHP_HFB0_UNI3_REG_END 0x00401ffc
-#define BCHP_DAVICMAC_DAV_REG_START 0x00600000
-#define BCHP_DAVICMAC_DAV_REG_END 0x0060041c
-#define BCHP_DAVIC_DMA_CTRL_DAV_REG_START 0x00600800
-#define BCHP_DAVIC_DMA_CTRL_DAV_REG_END 0x00600844
-#define BCHP_DAVIC_DMA_CH1_DAV_REG_START 0x00600900
-#define BCHP_DAVIC_DMA_CH1_DAV_REG_END 0x0060090c
-#define BCHP_DAVIC_DMA_CH2_DAV_REG_START 0x00600910
-#define BCHP_DAVIC_DMA_CH2_DAV_REG_END 0x0060091c
-#define BCHP_DAVIC_DMA_CH3_DAV_REG_START 0x00600920
-#define BCHP_DAVIC_DMA_CH3_DAV_REG_END 0x0060092c
-#define BCHP_DAVIC_DMA_CH4_DAV_REG_START 0x00600930
-#define BCHP_DAVIC_DMA_CH4_DAV_REG_END 0x0060093c
-#define BCHP_DAVIC_DMA_CH5_DAV_REG_START 0x00600940
-#define BCHP_DAVIC_DMA_CH5_DAV_REG_END 0x0060094c
-#define BCHP_DAVIC_DMA_CH6_DAV_REG_START 0x00600950
-#define BCHP_DAVIC_DMA_CH6_DAV_REG_END 0x0060095c
-#define BCHP_DAVIC_DMA_CH7_DAV_REG_START 0x00600960
-#define BCHP_DAVIC_DMA_CH7_DAV_REG_END 0x0060096c
-#define BCHP_DAVIC_DMA_CH8_DAV_REG_START 0x00600970
-#define BCHP_DAVIC_DMA_CH8_DAV_REG_END 0x0060097c
-#define BCHP_DAVIC_DMA_CH9_DAV_REG_START 0x00600980
-#define BCHP_DAVIC_DMA_CH9_DAV_REG_END 0x0060098c
-#define BCHP_DAVIC_DMA_CH10_DAV_REG_START 0x00600990
-#define BCHP_DAVIC_DMA_CH10_DAV_REG_END 0x0060099c
-#define BCHP_DAVIC_DMA_CH1_STATE_DAV_REG_START 0x00600a00
-#define BCHP_DAVIC_DMA_CH1_STATE_DAV_REG_END 0x00600a0c
-#define BCHP_DAVIC_DMA_CH2_STATE_DAV_REG_START 0x00600a10
-#define BCHP_DAVIC_DMA_CH2_STATE_DAV_REG_END 0x00600a1c
-#define BCHP_DAVIC_DMA_CH3_STATE_DAV_REG_START 0x00600a20
-#define BCHP_DAVIC_DMA_CH3_STATE_DAV_REG_END 0x00600a2c
-#define BCHP_DAVIC_DMA_CH4_STATE_DAV_REG_START 0x00600a30
-#define BCHP_DAVIC_DMA_CH4_STATE_DAV_REG_END 0x00600a3c
-#define BCHP_DAVIC_DMA_CH5_STATE_DAV_REG_START 0x00600a40
-#define BCHP_DAVIC_DMA_CH5_STATE_DAV_REG_END 0x00600a4c
-#define BCHP_DAVIC_DMA_CH6_STATE_DAV_REG_START 0x00600a50
-#define BCHP_DAVIC_DMA_CH6_STATE_DAV_REG_END 0x00600a5c
-#define BCHP_DAVIC_DMA_CH7_STATE_DAV_REG_START 0x00600a60
-#define BCHP_DAVIC_DMA_CH7_STATE_DAV_REG_END 0x00600a6c
-#define BCHP_DAVIC_DMA_CH8_STATE_DAV_REG_START 0x00600a70
-#define BCHP_DAVIC_DMA_CH8_STATE_DAV_REG_END 0x00600a7c
-#define BCHP_DAVIC_DMA_CH9_STATE_DAV_REG_START 0x00600a80
-#define BCHP_DAVIC_DMA_CH9_STATE_DAV_REG_END 0x00600a8c
-#define BCHP_DAVIC_DMA_CH10_STATE_DAV_REG_START 0x00600a90
-#define BCHP_DAVIC_DMA_CH10_STATE_DAV_REG_END 0x00600a9c
-#define BCHP_BaseReserved_UTP_REG_START 0x00a00000
-#define BCHP_BaseReserved_UTP_REG_END 0x00a00000
-#define BCHP_Control_UTP_REG_START 0x00a01000
-#define BCHP_Control_UTP_REG_END 0x00a010fc
-#define BCHP_OutgoingMessageFIFO_UTP_REG_START 0x00a01100
-#define BCHP_OutgoingMessageFIFO_UTP_REG_END 0x00a0117c
-#define BCHP_IncomingMessageFIFO_UTP_REG_START 0x00a01200
-#define BCHP_IncomingMessageFIFO_UTP_REG_END 0x00a0127c
-#define BCHP_DMA0_UTP_REG_START 0x00a01300
-#define BCHP_DMA0_UTP_REG_END 0x00a0131c
-#define BCHP_DMA1_UTP_REG_START 0x00a01320
-#define BCHP_DMA1_UTP_REG_END 0x00a0133c
-#define BCHP_Token_UTP_REG_START 0x00a01400
-#define BCHP_Token_UTP_REG_END 0x00a0141c
-#define BCHP_PerfPower_UTP_REG_START 0x00a01600
-#define BCHP_PerfPower_UTP_REG_END 0x00a01640
-#define BCHP_MessageID_UTP_REG_START 0x00a01700
-#define BCHP_MessageID_UTP_REG_END 0x00a0177c
-#define BCHP_DQM_UTP_REG_START 0x00a01800
-#define BCHP_DQM_UTP_REG_END 0x00a01848
-#define BCHP_HWCounters_UTP_REG_START 0x00a01900
-#define BCHP_HWCounters_UTP_REG_END 0x00a01944
-#define BCHP_QUEUE_0_CNTRL_UTP_REG_START 0x00a01a00
-#define BCHP_QUEUE_0_CNTRL_UTP_REG_END 0x00a01a0c
-#define BCHP_QUEUE_1_CNTRL_UTP_REG_START 0x00a01a10
-#define BCHP_QUEUE_1_CNTRL_UTP_REG_END 0x00a01a1c
-#define BCHP_QUEUE_2_CNTRL_UTP_REG_START 0x00a01a20
-#define BCHP_QUEUE_2_CNTRL_UTP_REG_END 0x00a01a2c
-#define BCHP_QUEUE_3_CNTRL_UTP_REG_START 0x00a01a30
-#define BCHP_QUEUE_3_CNTRL_UTP_REG_END 0x00a01a3c
-#define BCHP_QUEUE_4_CNTRL_UTP_REG_START 0x00a01a40
-#define BCHP_QUEUE_4_CNTRL_UTP_REG_END 0x00a01a4c
-#define BCHP_QUEUE_5_CNTRL_UTP_REG_START 0x00a01a50
-#define BCHP_QUEUE_5_CNTRL_UTP_REG_END 0x00a01a5c
-#define BCHP_QUEUE_6_CNTRL_UTP_REG_START 0x00a01a60
-#define BCHP_QUEUE_6_CNTRL_UTP_REG_END 0x00a01a6c
-#define BCHP_QUEUE_7_CNTRL_UTP_REG_START 0x00a01a70
-#define BCHP_QUEUE_7_CNTRL_UTP_REG_END 0x00a01a7c
-#define BCHP_QUEUE_8_CNTRL_UTP_REG_START 0x00a01a80
-#define BCHP_QUEUE_8_CNTRL_UTP_REG_END 0x00a01a8c
-#define BCHP_QUEUE_9_CNTRL_UTP_REG_START 0x00a01a90
-#define BCHP_QUEUE_9_CNTRL_UTP_REG_END 0x00a01a9c
-#define BCHP_QUEUE_10_CNTRL_UTP_REG_START 0x00a01aa0
-#define BCHP_QUEUE_10_CNTRL_UTP_REG_END 0x00a01aac
-#define BCHP_QUEUE_11_CNTRL_UTP_REG_START 0x00a01ab0
-#define BCHP_QUEUE_11_CNTRL_UTP_REG_END 0x00a01abc
-#define BCHP_QUEUE_12_CNTRL_UTP_REG_START 0x00a01ac0
-#define BCHP_QUEUE_12_CNTRL_UTP_REG_END 0x00a01acc
-#define BCHP_QUEUE_13_CNTRL_UTP_REG_START 0x00a01ad0
-#define BCHP_QUEUE_13_CNTRL_UTP_REG_END 0x00a01adc
-#define BCHP_QUEUE_14_CNTRL_UTP_REG_START 0x00a01ae0
-#define BCHP_QUEUE_14_CNTRL_UTP_REG_END 0x00a01aec
-#define BCHP_QUEUE_15_CNTRL_UTP_REG_START 0x00a01af0
-#define BCHP_QUEUE_15_CNTRL_UTP_REG_END 0x00a01afc
-#define BCHP_QUEUE_16_CNTRL_UTP_REG_START 0x00a01b00
-#define BCHP_QUEUE_16_CNTRL_UTP_REG_END 0x00a01b0c
-#define BCHP_QUEUE_17_CNTRL_UTP_REG_START 0x00a01b10
-#define BCHP_QUEUE_17_CNTRL_UTP_REG_END 0x00a01b1c
-#define BCHP_QUEUE_18_CNTRL_UTP_REG_START 0x00a01b20
-#define BCHP_QUEUE_18_CNTRL_UTP_REG_END 0x00a01b2c
-#define BCHP_QUEUE_19_CNTRL_UTP_REG_START 0x00a01b30
-#define BCHP_QUEUE_19_CNTRL_UTP_REG_END 0x00a01b3c
-#define BCHP_QUEUE_20_CNTRL_UTP_REG_START 0x00a01b40
-#define BCHP_QUEUE_20_CNTRL_UTP_REG_END 0x00a01b4c
-#define BCHP_QUEUE_21_CNTRL_UTP_REG_START 0x00a01b50
-#define BCHP_QUEUE_21_CNTRL_UTP_REG_END 0x00a01b5c
-#define BCHP_QUEUE_22_CNTRL_UTP_REG_START 0x00a01b60
-#define BCHP_QUEUE_22_CNTRL_UTP_REG_END 0x00a01b6c
-#define BCHP_QUEUE_23_CNTRL_UTP_REG_START 0x00a01b70
-#define BCHP_QUEUE_23_CNTRL_UTP_REG_END 0x00a01b7c
-#define BCHP_QUEUE_24_CNTRL_UTP_REG_START 0x00a01b80
-#define BCHP_QUEUE_24_CNTRL_UTP_REG_END 0x00a01b8c
-#define BCHP_QUEUE_25_CNTRL_UTP_REG_START 0x00a01b90
-#define BCHP_QUEUE_25_CNTRL_UTP_REG_END 0x00a01b9c
-#define BCHP_QUEUE_26_CNTRL_UTP_REG_START 0x00a01ba0
-#define BCHP_QUEUE_26_CNTRL_UTP_REG_END 0x00a01bac
-#define BCHP_QUEUE_27_CNTRL_UTP_REG_START 0x00a01bb0
-#define BCHP_QUEUE_27_CNTRL_UTP_REG_END 0x00a01bbc
-#define BCHP_QUEUE_28_CNTRL_UTP_REG_START 0x00a01bc0
-#define BCHP_QUEUE_28_CNTRL_UTP_REG_END 0x00a01bcc
-#define BCHP_QUEUE_29_CNTRL_UTP_REG_START 0x00a01bd0
-#define BCHP_QUEUE_29_CNTRL_UTP_REG_END 0x00a01bdc
-#define BCHP_QUEUE_30_CNTRL_UTP_REG_START 0x00a01be0
-#define BCHP_QUEUE_30_CNTRL_UTP_REG_END 0x00a01bec
-#define BCHP_QUEUE_31_CNTRL_UTP_REG_START 0x00a01bf0
-#define BCHP_QUEUE_31_CNTRL_UTP_REG_END 0x00a01bfc
-#define BCHP_QUEUE_0_DATA_UTP_REG_START 0x00a01c00
-#define BCHP_QUEUE_0_DATA_UTP_REG_END 0x00a01c0c
-#define BCHP_QUEUE_1_DATA_UTP_REG_START 0x00a01c10
-#define BCHP_QUEUE_1_DATA_UTP_REG_END 0x00a01c1c
-#define BCHP_QUEUE_2_DATA_UTP_REG_START 0x00a01c20
-#define BCHP_QUEUE_2_DATA_UTP_REG_END 0x00a01c2c
-#define BCHP_QUEUE_3_DATA_UTP_REG_START 0x00a01c30
-#define BCHP_QUEUE_3_DATA_UTP_REG_END 0x00a01c3c
-#define BCHP_QUEUE_4_DATA_UTP_REG_START 0x00a01c40
-#define BCHP_QUEUE_4_DATA_UTP_REG_END 0x00a01c4c
-#define BCHP_QUEUE_5_DATA_UTP_REG_START 0x00a01c50
-#define BCHP_QUEUE_5_DATA_UTP_REG_END 0x00a01c5c
-#define BCHP_QUEUE_6_DATA_UTP_REG_START 0x00a01c60
-#define BCHP_QUEUE_6_DATA_UTP_REG_END 0x00a01c6c
-#define BCHP_QUEUE_7_DATA_UTP_REG_START 0x00a01c70
-#define BCHP_QUEUE_7_DATA_UTP_REG_END 0x00a01c7c
-#define BCHP_QUEUE_8_DATA_UTP_REG_START 0x00a01c80
-#define BCHP_QUEUE_8_DATA_UTP_REG_END 0x00a01c8c
-#define BCHP_QUEUE_9_DATA_UTP_REG_START 0x00a01c90
-#define BCHP_QUEUE_9_DATA_UTP_REG_END 0x00a01c9c
-#define BCHP_QUEUE_10_DATA_UTP_REG_START 0x00a01ca0
-#define BCHP_QUEUE_10_DATA_UTP_REG_END 0x00a01cac
-#define BCHP_QUEUE_11_DATA_UTP_REG_START 0x00a01cb0
-#define BCHP_QUEUE_11_DATA_UTP_REG_END 0x00a01cbc
-#define BCHP_QUEUE_12_DATA_UTP_REG_START 0x00a01cc0
-#define BCHP_QUEUE_12_DATA_UTP_REG_END 0x00a01ccc
-#define BCHP_QUEUE_13_DATA_UTP_REG_START 0x00a01cd0
-#define BCHP_QUEUE_13_DATA_UTP_REG_END 0x00a01cdc
-#define BCHP_QUEUE_14_DATA_UTP_REG_START 0x00a01ce0
-#define BCHP_QUEUE_14_DATA_UTP_REG_END 0x00a01cec
-#define BCHP_QUEUE_15_DATA_UTP_REG_START 0x00a01cf0
-#define BCHP_QUEUE_15_DATA_UTP_REG_END 0x00a01cfc
-#define BCHP_QUEUE_16_DATA_UTP_REG_START 0x00a01d00
-#define BCHP_QUEUE_16_DATA_UTP_REG_END 0x00a01d0c
-#define BCHP_QUEUE_17_DATA_UTP_REG_START 0x00a01d10
-#define BCHP_QUEUE_17_DATA_UTP_REG_END 0x00a01d1c
-#define BCHP_QUEUE_18_DATA_UTP_REG_START 0x00a01d20
-#define BCHP_QUEUE_18_DATA_UTP_REG_END 0x00a01d2c
-#define BCHP_QUEUE_19_DATA_UTP_REG_START 0x00a01d30
-#define BCHP_QUEUE_19_DATA_UTP_REG_END 0x00a01d3c
-#define BCHP_QUEUE_20_DATA_UTP_REG_START 0x00a01d40
-#define BCHP_QUEUE_20_DATA_UTP_REG_END 0x00a01d4c
-#define BCHP_QUEUE_21_DATA_UTP_REG_START 0x00a01d50
-#define BCHP_QUEUE_21_DATA_UTP_REG_END 0x00a01d5c
-#define BCHP_QUEUE_22_DATA_UTP_REG_START 0x00a01d60
-#define BCHP_QUEUE_22_DATA_UTP_REG_END 0x00a01d6c
-#define BCHP_QUEUE_23_DATA_UTP_REG_START 0x00a01d70
-#define BCHP_QUEUE_23_DATA_UTP_REG_END 0x00a01d7c
-#define BCHP_QUEUE_24_DATA_UTP_REG_START 0x00a01d80
-#define BCHP_QUEUE_24_DATA_UTP_REG_END 0x00a01d8c
-#define BCHP_QUEUE_25_DATA_UTP_REG_START 0x00a01d90
-#define BCHP_QUEUE_25_DATA_UTP_REG_END 0x00a01d9c
-#define BCHP_QUEUE_26_DATA_UTP_REG_START 0x00a01da0
-#define BCHP_QUEUE_26_DATA_UTP_REG_END 0x00a01dac
-#define BCHP_QUEUE_27_DATA_UTP_REG_START 0x00a01db0
-#define BCHP_QUEUE_27_DATA_UTP_REG_END 0x00a01dbc
-#define BCHP_QUEUE_28_DATA_UTP_REG_START 0x00a01dc0
-#define BCHP_QUEUE_28_DATA_UTP_REG_END 0x00a01dcc
-#define BCHP_QUEUE_29_DATA_UTP_REG_START 0x00a01dd0
-#define BCHP_QUEUE_29_DATA_UTP_REG_END 0x00a01ddc
-#define BCHP_QUEUE_30_DATA_UTP_REG_START 0x00a01de0
-#define BCHP_QUEUE_30_DATA_UTP_REG_END 0x00a01dec
-#define BCHP_QUEUE_31_DATA_UTP_REG_START 0x00a01df0
-#define BCHP_QUEUE_31_DATA_UTP_REG_END 0x00a01dfc
-#define BCHP_QUEUE_STATUS_UTP_REG_START 0x00a01f00
-#define BCHP_QUEUE_STATUS_UTP_REG_END 0x00a01f7c
-#define BCHP_QUEUE_MIB_UTP_REG_START 0x00a02000
-#define BCHP_QUEUE_MIB_UTP_REG_END 0x00a0217c
-#define BCHP_DQM_LITE_UTP_REG_START 0x00a02200
-#define BCHP_DQM_LITE_UTP_REG_END 0x00a02248
-#define BCHP_QUEUE_0_CNTRL_LITE_UTP_REG_START 0x00a02400
-#define BCHP_QUEUE_0_CNTRL_LITE_UTP_REG_END 0x00a0240c
-#define BCHP_QUEUE_1_CNTRL_LITE_UTP_REG_START 0x00a02410
-#define BCHP_QUEUE_1_CNTRL_LITE_UTP_REG_END 0x00a0241c
-#define BCHP_QUEUE_2_CNTRL_LITE_UTP_REG_START 0x00a02420
-#define BCHP_QUEUE_2_CNTRL_LITE_UTP_REG_END 0x00a0242c
-#define BCHP_QUEUE_3_CNTRL_LITE_UTP_REG_START 0x00a02430
-#define BCHP_QUEUE_3_CNTRL_LITE_UTP_REG_END 0x00a0243c
-#define BCHP_QUEUE_4_CNTRL_LITE_UTP_REG_START 0x00a02440
-#define BCHP_QUEUE_4_CNTRL_LITE_UTP_REG_END 0x00a0244c
-#define BCHP_QUEUE_5_CNTRL_LITE_UTP_REG_START 0x00a02450
-#define BCHP_QUEUE_5_CNTRL_LITE_UTP_REG_END 0x00a0245c
-#define BCHP_QUEUE_6_CNTRL_LITE_UTP_REG_START 0x00a02460
-#define BCHP_QUEUE_6_CNTRL_LITE_UTP_REG_END 0x00a0246c
-#define BCHP_QUEUE_7_CNTRL_LITE_UTP_REG_START 0x00a02470
-#define BCHP_QUEUE_7_CNTRL_LITE_UTP_REG_END 0x00a0247c
-#define BCHP_QUEUE_8_CNTRL_LITE_UTP_REG_START 0x00a02480
-#define BCHP_QUEUE_8_CNTRL_LITE_UTP_REG_END 0x00a0248c
-#define BCHP_QUEUE_9_CNTRL_LITE_UTP_REG_START 0x00a02490
-#define BCHP_QUEUE_9_CNTRL_LITE_UTP_REG_END 0x00a0249c
-#define BCHP_QUEUE_10_CNTRL_LITE_UTP_REG_START 0x00a024a0
-#define BCHP_QUEUE_10_CNTRL_LITE_UTP_REG_END 0x00a024ac
-#define BCHP_QUEUE_11_CNTRL_LITE_UTP_REG_START 0x00a024b0
-#define BCHP_QUEUE_11_CNTRL_LITE_UTP_REG_END 0x00a024bc
-#define BCHP_QUEUE_12_CNTRL_LITE_UTP_REG_START 0x00a024c0
-#define BCHP_QUEUE_12_CNTRL_LITE_UTP_REG_END 0x00a024cc
-#define BCHP_QUEUE_13_CNTRL_LITE_UTP_REG_START 0x00a024d0
-#define BCHP_QUEUE_13_CNTRL_LITE_UTP_REG_END 0x00a024dc
-#define BCHP_QUEUE_14_CNTRL_LITE_UTP_REG_START 0x00a024e0
-#define BCHP_QUEUE_14_CNTRL_LITE_UTP_REG_END 0x00a024ec
-#define BCHP_QUEUE_15_CNTRL_LITE_UTP_REG_START 0x00a024f0
-#define BCHP_QUEUE_15_CNTRL_LITE_UTP_REG_END 0x00a024fc
-#define BCHP_QUEUE_0_DATA_LITE_UTP_REG_START 0x00a02600
-#define BCHP_QUEUE_0_DATA_LITE_UTP_REG_END 0x00a0260c
-#define BCHP_QUEUE_1_DATA_LITE_UTP_REG_START 0x00a02610
-#define BCHP_QUEUE_1_DATA_LITE_UTP_REG_END 0x00a0261c
-#define BCHP_QUEUE_2_DATA_LITE_UTP_REG_START 0x00a02620
-#define BCHP_QUEUE_2_DATA_LITE_UTP_REG_END 0x00a0262c
-#define BCHP_QUEUE_3_DATA_LITE_UTP_REG_START 0x00a02630
-#define BCHP_QUEUE_3_DATA_LITE_UTP_REG_END 0x00a0263c
-#define BCHP_QUEUE_4_DATA_LITE_UTP_REG_START 0x00a02640
-#define BCHP_QUEUE_4_DATA_LITE_UTP_REG_END 0x00a0264c
-#define BCHP_QUEUE_5_DATA_LITE_UTP_REG_START 0x00a02650
-#define BCHP_QUEUE_5_DATA_LITE_UTP_REG_END 0x00a0265c
-#define BCHP_QUEUE_6_DATA_LITE_UTP_REG_START 0x00a02660
-#define BCHP_QUEUE_6_DATA_LITE_UTP_REG_END 0x00a0266c
-#define BCHP_QUEUE_7_DATA_LITE_UTP_REG_START 0x00a02670
-#define BCHP_QUEUE_7_DATA_LITE_UTP_REG_END 0x00a0267c
-#define BCHP_QUEUE_8_DATA_LITE_UTP_REG_START 0x00a02680
-#define BCHP_QUEUE_8_DATA_LITE_UTP_REG_END 0x00a0268c
-#define BCHP_QUEUE_9_DATA_LITE_UTP_REG_START 0x00a02690
-#define BCHP_QUEUE_9_DATA_LITE_UTP_REG_END 0x00a0269c
-#define BCHP_QUEUE_10_DATA_LITE_UTP_REG_START 0x00a026a0
-#define BCHP_QUEUE_10_DATA_LITE_UTP_REG_END 0x00a026ac
-#define BCHP_QUEUE_11_DATA_LITE_UTP_REG_START 0x00a026b0
-#define BCHP_QUEUE_11_DATA_LITE_UTP_REG_END 0x00a026bc
-#define BCHP_QUEUE_12_DATA_LITE_UTP_REG_START 0x00a026c0
-#define BCHP_QUEUE_12_DATA_LITE_UTP_REG_END 0x00a026cc
-#define BCHP_QUEUE_13_DATA_LITE_UTP_REG_START 0x00a026d0
-#define BCHP_QUEUE_13_DATA_LITE_UTP_REG_END 0x00a026dc
-#define BCHP_QUEUE_14_DATA_LITE_UTP_REG_START 0x00a026e0
-#define BCHP_QUEUE_14_DATA_LITE_UTP_REG_END 0x00a026ec
-#define BCHP_QUEUE_15_DATA_LITE_UTP_REG_START 0x00a026f0
-#define BCHP_QUEUE_15_DATA_LITE_UTP_REG_END 0x00a026fc
-#define BCHP_QUEUE_STATUS_LITE_UTP_REG_START 0x00a02900
-#define BCHP_QUEUE_STATUS_LITE_UTP_REG_END 0x00a0293c
-#define BCHP_QUEUE_MIB_LITE_UTP_REG_START 0x00a02a00
-#define BCHP_QUEUE_MIB_LITE_UTP_REG_END 0x00a02b3c
-#define BCHP_SharedMem_UTP_REG_START 0x00a04000
-#define BCHP_SharedMem_UTP_REG_END 0x00a0fffc
-#define BCHP_Memory_UTP_REG_START 0x00a14000
-#define BCHP_Memory_UTP_REG_END 0x00a17ffc
-#define BCHP_QListMem_UTP_REG_START 0x00a40000
-#define BCHP_QListMem_UTP_REG_END 0x00a43ffc
-#define BCHP_QueueListConfig_UTP_REG_START 0x00a45000
-#define BCHP_QueueListConfig_UTP_REG_END 0x00a4521c
-#define BCHP_QiThreshold_UTP_REG_START 0x00a45400
-#define BCHP_QiThreshold_UTP_REG_END 0x00a4547c
-#define BCHP_AckCelMaxCnt_UTP_REG_START 0x00a45500
-#define BCHP_AckCelMaxCnt_UTP_REG_END 0x00a4553c
-#define BCHP_MIBs_UTP_REG_START 0x00a45600
-#define BCHP_MIBs_UTP_REG_END 0x00a45618
-#define BCHP_UTPIncomingMessageFIFO_UTP_REG_START 0x00a45700
-#define BCHP_UTPIncomingMessageFIFO_UTP_REG_END 0x00a45740
-#define BCHP_QueueListHeadTail_UTP_REG_START 0x00a45800
-#define BCHP_QueueListHeadTail_UTP_REG_END 0x00a458fc
-#define BCHP_TokenInsertion_UTP_REG_START 0x00a45a00
-#define BCHP_TokenInsertion_UTP_REG_END 0x00a45a1c
-#define BCHP_TokenDeletion_UTP_REG_START 0x00a45a20
-#define BCHP_TokenDeletion_UTP_REG_END 0x00a45a30
-#define BCHP_TamMisc_UTP_REG_START 0x00a45a40
-#define BCHP_TamMisc_UTP_REG_END 0x00a45a8c
-#define BCHP_QueueAvailSize_UTP_REG_START 0x00a45b00
-#define BCHP_QueueAvailSize_UTP_REG_END 0x00a45bfc
-#define BCHP_UTPMaxRate_FLOW0_UTP_REG_START 0x00a45c00
-#define BCHP_UTPMaxRate_FLOW0_UTP_REG_END 0x00a45c0c
-#define BCHP_UTPMaxRate_FLOW1_UTP_REG_START 0x00a45c10
-#define BCHP_UTPMaxRate_FLOW1_UTP_REG_END 0x00a45c1c
-#define BCHP_UTPMaxRate_FLOW2_UTP_REG_START 0x00a45c20
-#define BCHP_UTPMaxRate_FLOW2_UTP_REG_END 0x00a45c2c
-#define BCHP_UTPMaxRate_FLOW3_UTP_REG_START 0x00a45c30
-#define BCHP_UTPMaxRate_FLOW3_UTP_REG_END 0x00a45c3c
-#define BCHP_UTPMaxRate_FLOW4_UTP_REG_START 0x00a45c40
-#define BCHP_UTPMaxRate_FLOW4_UTP_REG_END 0x00a45c4c
-#define BCHP_UTPMaxRate_FLOW5_UTP_REG_START 0x00a45c50
-#define BCHP_UTPMaxRate_FLOW5_UTP_REG_END 0x00a45c5c
-#define BCHP_UTPMaxRate_FLOW6_UTP_REG_START 0x00a45c60
-#define BCHP_UTPMaxRate_FLOW6_UTP_REG_END 0x00a45c6c
-#define BCHP_UTPMaxRate_FLOW7_UTP_REG_START 0x00a45c70
-#define BCHP_UTPMaxRate_FLOW7_UTP_REG_END 0x00a45c7c
-#define BCHP_UTPMaxRate_FLOW8_UTP_REG_START 0x00a45c80
-#define BCHP_UTPMaxRate_FLOW8_UTP_REG_END 0x00a45c8c
-#define BCHP_UTPMaxRate_FLOW9_UTP_REG_START 0x00a45c90
-#define BCHP_UTPMaxRate_FLOW9_UTP_REG_END 0x00a45c9c
-#define BCHP_UTPMaxRate_FLOW10_UTP_REG_START 0x00a45ca0
-#define BCHP_UTPMaxRate_FLOW10_UTP_REG_END 0x00a45cac
-#define BCHP_UTPMaxRate_FLOW11_UTP_REG_START 0x00a45cb0
-#define BCHP_UTPMaxRate_FLOW11_UTP_REG_END 0x00a45cbc
-#define BCHP_UTPMaxRate_FLOW12_UTP_REG_START 0x00a45cc0
-#define BCHP_UTPMaxRate_FLOW12_UTP_REG_END 0x00a45ccc
-#define BCHP_UTPMaxRate_FLOW13_UTP_REG_START 0x00a45cd0
-#define BCHP_UTPMaxRate_FLOW13_UTP_REG_END 0x00a45cdc
-#define BCHP_UTPMaxRate_FLOW14_UTP_REG_START 0x00a45ce0
-#define BCHP_UTPMaxRate_FLOW14_UTP_REG_END 0x00a45cec
-#define BCHP_UTPMaxRate_FLOW15_UTP_REG_START 0x00a45cf0
-#define BCHP_UTPMaxRate_FLOW15_UTP_REG_END 0x00a45cfc
-#define BCHP_UTPPeakRate_FLOW0_UTP_REG_START 0x00a45d00
-#define BCHP_UTPPeakRate_FLOW0_UTP_REG_END 0x00a45d0c
-#define BCHP_UTPPeakRate_FLOW1_UTP_REG_START 0x00a45d10
-#define BCHP_UTPPeakRate_FLOW1_UTP_REG_END 0x00a45d1c
-#define BCHP_UTPPeakRate_FLOW2_UTP_REG_START 0x00a45d20
-#define BCHP_UTPPeakRate_FLOW2_UTP_REG_END 0x00a45d2c
-#define BCHP_UTPPeakRate_FLOW3_UTP_REG_START 0x00a45d30
-#define BCHP_UTPPeakRate_FLOW3_UTP_REG_END 0x00a45d3c
-#define BCHP_UTPPeakRate_FLOW4_UTP_REG_START 0x00a45d40
-#define BCHP_UTPPeakRate_FLOW4_UTP_REG_END 0x00a45d4c
-#define BCHP_UTPPeakRate_FLOW5_UTP_REG_START 0x00a45d50
-#define BCHP_UTPPeakRate_FLOW5_UTP_REG_END 0x00a45d5c
-#define BCHP_UTPPeakRate_FLOW6_UTP_REG_START 0x00a45d60
-#define BCHP_UTPPeakRate_FLOW6_UTP_REG_END 0x00a45d6c
-#define BCHP_UTPPeakRate_FLOW7_UTP_REG_START 0x00a45d70
-#define BCHP_UTPPeakRate_FLOW7_UTP_REG_END 0x00a45d7c
-#define BCHP_UTPPeakRate_FLOW8_UTP_REG_START 0x00a45d80
-#define BCHP_UTPPeakRate_FLOW8_UTP_REG_END 0x00a45d8c
-#define BCHP_UTPPeakRate_FLOW9_UTP_REG_START 0x00a45d90
-#define BCHP_UTPPeakRate_FLOW9_UTP_REG_END 0x00a45d9c
-#define BCHP_UTPPeakRate_FLOW10_UTP_REG_START 0x00a45da0
-#define BCHP_UTPPeakRate_FLOW10_UTP_REG_END 0x00a45dac
-#define BCHP_UTPPeakRate_FLOW11_UTP_REG_START 0x00a45db0
-#define BCHP_UTPPeakRate_FLOW11_UTP_REG_END 0x00a45dbc
-#define BCHP_UTPPeakRate_FLOW12_UTP_REG_START 0x00a45dc0
-#define BCHP_UTPPeakRate_FLOW12_UTP_REG_END 0x00a45dcc
-#define BCHP_UTPPeakRate_FLOW13_UTP_REG_START 0x00a45dd0
-#define BCHP_UTPPeakRate_FLOW13_UTP_REG_END 0x00a45ddc
-#define BCHP_UTPPeakRate_FLOW14_UTP_REG_START 0x00a45de0
-#define BCHP_UTPPeakRate_FLOW14_UTP_REG_END 0x00a45dec
-#define BCHP_UTPPeakRate_FLOW15_UTP_REG_START 0x00a45df0
-#define BCHP_UTPPeakRate_FLOW15_UTP_REG_END 0x00a45dfc
-#define BCHP_UTPTimer_0_UTP_REG_START 0x00a45e00
-#define BCHP_UTPTimer_0_UTP_REG_END 0x00a45e04
-#define BCHP_UTPTimer_1_UTP_REG_START 0x00a45e08
-#define BCHP_UTPTimer_1_UTP_REG_END 0x00a45e0c
-#define BCHP_UTPTimer_2_UTP_REG_START 0x00a45e10
-#define BCHP_UTPTimer_2_UTP_REG_END 0x00a45e14
-#define BCHP_UTPTimer_3_UTP_REG_START 0x00a45e18
-#define BCHP_UTPTimer_3_UTP_REG_END 0x00a45e1c
-#define BCHP_UTPTimer_4_UTP_REG_START 0x00a45e20
-#define BCHP_UTPTimer_4_UTP_REG_END 0x00a45e24
-#define BCHP_UTPTimer_5_UTP_REG_START 0x00a45e28
-#define BCHP_UTPTimer_5_UTP_REG_END 0x00a45e2c
-#define BCHP_UTPTimer_6_UTP_REG_START 0x00a45e30
-#define BCHP_UTPTimer_6_UTP_REG_END 0x00a45e34
-#define BCHP_UTPTimer_7_UTP_REG_START 0x00a45e38
-#define BCHP_UTPTimer_7_UTP_REG_END 0x00a45e3c
-#define BCHP_UTPTimer_8_UTP_REG_START 0x00a45e40
-#define BCHP_UTPTimer_8_UTP_REG_END 0x00a45e44
-#define BCHP_UTPTimer_9_UTP_REG_START 0x00a45e48
-#define BCHP_UTPTimer_9_UTP_REG_END 0x00a45e4c
-#define BCHP_UTPTimer_10_UTP_REG_START 0x00a45e50
-#define BCHP_UTPTimer_10_UTP_REG_END 0x00a45e54
-#define BCHP_UTPTimer_11_UTP_REG_START 0x00a45e58
-#define BCHP_UTPTimer_11_UTP_REG_END 0x00a45e5c
-#define BCHP_UTPTimer_12_UTP_REG_START 0x00a45e60
-#define BCHP_UTPTimer_12_UTP_REG_END 0x00a45e64
-#define BCHP_UTPTimer_13_UTP_REG_START 0x00a45e68
-#define BCHP_UTPTimer_13_UTP_REG_END 0x00a45e6c
-#define BCHP_UTPTimer_14_UTP_REG_START 0x00a45e70
-#define BCHP_UTPTimer_14_UTP_REG_END 0x00a45e74
-#define BCHP_UTPTimer_15_UTP_REG_START 0x00a45e78
-#define BCHP_UTPTimer_15_UTP_REG_END 0x00a45e7c
-#define BCHP_UTPTimer_16_UTP_REG_START 0x00a45e80
-#define BCHP_UTPTimer_16_UTP_REG_END 0x00a45e84
-#define BCHP_UTPBytesSent_FLOW0_UTP_REG_START 0x00a45f80
-#define BCHP_UTPBytesSent_FLOW0_UTP_REG_END 0x00a45f84
-#define BCHP_UTPBytesSent_FLOW1_UTP_REG_START 0x00a45f88
-#define BCHP_UTPBytesSent_FLOW1_UTP_REG_END 0x00a45f8c
-#define BCHP_UTPBytesSent_FLOW2_UTP_REG_START 0x00a45f90
-#define BCHP_UTPBytesSent_FLOW2_UTP_REG_END 0x00a45f94
-#define BCHP_UTPBytesSent_FLOW3_UTP_REG_START 0x00a45f98
-#define BCHP_UTPBytesSent_FLOW3_UTP_REG_END 0x00a45f9c
-#define BCHP_UTPBytesSent_FLOW4_UTP_REG_START 0x00a45fa0
-#define BCHP_UTPBytesSent_FLOW4_UTP_REG_END 0x00a45fa4
-#define BCHP_UTPBytesSent_FLOW5_UTP_REG_START 0x00a45fa8
-#define BCHP_UTPBytesSent_FLOW5_UTP_REG_END 0x00a45fac
-#define BCHP_UTPBytesSent_FLOW6_UTP_REG_START 0x00a45fb0
-#define BCHP_UTPBytesSent_FLOW6_UTP_REG_END 0x00a45fb4
-#define BCHP_UTPBytesSent_FLOW7_UTP_REG_START 0x00a45fb8
-#define BCHP_UTPBytesSent_FLOW7_UTP_REG_END 0x00a45fbc
-#define BCHP_UTPBytesSent_FLOW8_UTP_REG_START 0x00a45fc0
-#define BCHP_UTPBytesSent_FLOW8_UTP_REG_END 0x00a45fc4
-#define BCHP_UTPBytesSent_FLOW9_UTP_REG_START 0x00a45fc8
-#define BCHP_UTPBytesSent_FLOW9_UTP_REG_END 0x00a45fcc
-#define BCHP_UTPBytesSent_FLOW10_UTP_REG_START 0x00a45fd0
-#define BCHP_UTPBytesSent_FLOW10_UTP_REG_END 0x00a45fd4
-#define BCHP_UTPBytesSent_FLOW11_UTP_REG_START 0x00a45fd8
-#define BCHP_UTPBytesSent_FLOW11_UTP_REG_END 0x00a45fdc
-#define BCHP_UTPBytesSent_FLOW12_UTP_REG_START 0x00a45fe0
-#define BCHP_UTPBytesSent_FLOW12_UTP_REG_END 0x00a45fe4
-#define BCHP_UTPBytesSent_FLOW13_UTP_REG_START 0x00a45fe8
-#define BCHP_UTPBytesSent_FLOW13_UTP_REG_END 0x00a45fec
-#define BCHP_UTPBytesSent_FLOW14_UTP_REG_START 0x00a45ff0
-#define BCHP_UTPBytesSent_FLOW14_UTP_REG_END 0x00a45ff4
-#define BCHP_UTPBytesSent_FLOW15_UTP_REG_START 0x00a45ff8
-#define BCHP_UTPBytesSent_FLOW15_UTP_REG_END 0x00a45ffc
-#define BCHP_UTPTokensInserted0_UTP_REG_START 0x00a46000
-#define BCHP_UTPTokensInserted0_UTP_REG_END 0x00a46004
-#define BCHP_UTPTokensInserted1_UTP_REG_START 0x00a46008
-#define BCHP_UTPTokensInserted1_UTP_REG_END 0x00a4600c
-#define BCHP_UTPTokensInserted2_UTP_REG_START 0x00a46010
-#define BCHP_UTPTokensInserted2_UTP_REG_END 0x00a46014
-#define BCHP_UTPTokensInserted3_UTP_REG_START 0x00a46018
-#define BCHP_UTPTokensInserted3_UTP_REG_END 0x00a4601c
-#define BCHP_UTPTokensInserted4_UTP_REG_START 0x00a46020
-#define BCHP_UTPTokensInserted4_UTP_REG_END 0x00a46024
-#define BCHP_UTPTokensInserted5_UTP_REG_START 0x00a46028
-#define BCHP_UTPTokensInserted5_UTP_REG_END 0x00a4602c
-#define BCHP_UTPTokensInserted6_UTP_REG_START 0x00a46030
-#define BCHP_UTPTokensInserted6_UTP_REG_END 0x00a46034
-#define BCHP_UTPTokensInserted7_UTP_REG_START 0x00a46038
-#define BCHP_UTPTokensInserted7_UTP_REG_END 0x00a4603c
-#define BCHP_UTPTokensInserted8_UTP_REG_START 0x00a46040
-#define BCHP_UTPTokensInserted8_UTP_REG_END 0x00a46044
-#define BCHP_UTPTokensInserted9_UTP_REG_START 0x00a46048
-#define BCHP_UTPTokensInserted9_UTP_REG_END 0x00a4604c
-#define BCHP_UTPTokensInserted10_UTP_REG_START 0x00a46050
-#define BCHP_UTPTokensInserted10_UTP_REG_END 0x00a46054
-#define BCHP_UTPTokensInserted11_UTP_REG_START 0x00a46058
-#define BCHP_UTPTokensInserted11_UTP_REG_END 0x00a4605c
-#define BCHP_UTPTokensInserted12_UTP_REG_START 0x00a46060
-#define BCHP_UTPTokensInserted12_UTP_REG_END 0x00a46064
-#define BCHP_UTPTokensInserted13_UTP_REG_START 0x00a46068
-#define BCHP_UTPTokensInserted13_UTP_REG_END 0x00a4606c
-#define BCHP_UTPTokensInserted14_UTP_REG_START 0x00a46070
-#define BCHP_UTPTokensInserted14_UTP_REG_END 0x00a46074
-#define BCHP_UTPTokensInserted15_UTP_REG_START 0x00a46078
-#define BCHP_UTPTokensInserted15_UTP_REG_END 0x00a4607c
-#define BCHP_UTPTokensInserted16_UTP_REG_START 0x00a46080
-#define BCHP_UTPTokensInserted16_UTP_REG_END 0x00a46084
-#define BCHP_UTPTokensInserted17_UTP_REG_START 0x00a46088
-#define BCHP_UTPTokensInserted17_UTP_REG_END 0x00a4608c
-#define BCHP_UTPTokensInserted18_UTP_REG_START 0x00a46090
-#define BCHP_UTPTokensInserted18_UTP_REG_END 0x00a46094
-#define BCHP_UTPTokensInserted19_UTP_REG_START 0x00a46098
-#define BCHP_UTPTokensInserted19_UTP_REG_END 0x00a4609c
-#define BCHP_UTPTokensInserted20_UTP_REG_START 0x00a460a0
-#define BCHP_UTPTokensInserted20_UTP_REG_END 0x00a460a4
-#define BCHP_UTPTokensInserted21_UTP_REG_START 0x00a460a8
-#define BCHP_UTPTokensInserted21_UTP_REG_END 0x00a460ac
-#define BCHP_UTPTokensInserted22_UTP_REG_START 0x00a460b0
-#define BCHP_UTPTokensInserted22_UTP_REG_END 0x00a460b4
-#define BCHP_UTPTokensInserted23_UTP_REG_START 0x00a460b8
-#define BCHP_UTPTokensInserted23_UTP_REG_END 0x00a460bc
-#define BCHP_UTPTokensInserted24_UTP_REG_START 0x00a460c0
-#define BCHP_UTPTokensInserted24_UTP_REG_END 0x00a460c4
-#define BCHP_UTPTokensInserted25_UTP_REG_START 0x00a460c8
-#define BCHP_UTPTokensInserted25_UTP_REG_END 0x00a460cc
-#define BCHP_UTPTokensInserted26_UTP_REG_START 0x00a460d0
-#define BCHP_UTPTokensInserted26_UTP_REG_END 0x00a460d4
-#define BCHP_UTPTokensInserted27_UTP_REG_START 0x00a460d8
-#define BCHP_UTPTokensInserted27_UTP_REG_END 0x00a460dc
-#define BCHP_UTPTokensInserted28_UTP_REG_START 0x00a460e0
-#define BCHP_UTPTokensInserted28_UTP_REG_END 0x00a460e4
-#define BCHP_UTPTokensInserted29_UTP_REG_START 0x00a460e8
-#define BCHP_UTPTokensInserted29_UTP_REG_END 0x00a460ec
-#define BCHP_UTPTokensInserted30_UTP_REG_START 0x00a460f0
-#define BCHP_UTPTokensInserted30_UTP_REG_END 0x00a460f4
-#define BCHP_UTPTokensInserted31_UTP_REG_START 0x00a460f8
-#define BCHP_UTPTokensInserted31_UTP_REG_END 0x00a460fc
-#define BCHP_UTPTokensDeleted_UTP_REG_START 0x00a46100
-#define BCHP_UTPTokensDeleted_UTP_REG_END 0x00a4617c
-#define BCHP_UTPTokensReplaced_UTP_REG_START 0x00a46180
-#define BCHP_UTPTokensReplaced_UTP_REG_END 0x00a461fc
-#define BCHP_IncMsgFifoCntr_UTP_REG_START 0x00a46200
-#define BCHP_IncMsgFifoCntr_UTP_REG_END 0x00a4627c
-#define BCHP_UTPAutoDelete_UTP_REG_START 0x00a46400
-#define BCHP_UTPAutoDelete_UTP_REG_END 0x00a4640c
-#define BCHP_TokenMem_UTP_REG_START 0x00a50000
-#define BCHP_TokenMem_UTP_REG_END 0x00a5fffc
-#define BCHP_SEGDMA_CONFIG_UTP_REG_START 0x00a80000
-#define BCHP_SEGDMA_CONFIG_UTP_REG_END 0x00a8003c
-#define BCHP_SEGDMA_IRQ_HOST_UTP_REG_START 0x00a80100
-#define BCHP_SEGDMA_IRQ_HOST_UTP_REG_END 0x00a8013c
-#define BCHP_SEGDMA_IRQ_UTP_UTP_REG_START 0x00a80200
-#define BCHP_SEGDMA_IRQ_UTP_UTP_REG_END 0x00a8023c
-#define BCHP_SEGDMA_STAT_UTP_REG_START 0x00a80300
-#define BCHP_SEGDMA_STAT_UTP_REG_END 0x00a8038c
-#define BCHP_SEGDMA_TEST_UTP_REG_START 0x00a80400
-#define BCHP_SEGDMA_TEST_UTP_REG_END 0x00a8045c
-#define BCHP_SEGDMA_CHAN0_UTP_REG_START 0x00a81000
-#define BCHP_SEGDMA_CHAN0_UTP_REG_END 0x00a8103c
-#define BCHP_SEGDMA_CHAN1_UTP_REG_START 0x00a81100
-#define BCHP_SEGDMA_CHAN1_UTP_REG_END 0x00a8113c
-#define BCHP_SEGDMA_CHAN2_UTP_REG_START 0x00a81200
-#define BCHP_SEGDMA_CHAN2_UTP_REG_END 0x00a8123c
-#define BCHP_SEGDMA_CHAN3_UTP_REG_START 0x00a81300
-#define BCHP_SEGDMA_CHAN3_UTP_REG_END 0x00a8133c
-#define BCHP_SEGDMA_CHAN4_UTP_REG_START 0x00a81400
-#define BCHP_SEGDMA_CHAN4_UTP_REG_END 0x00a8143c
-#define BCHP_SEGDMA_CHAN5_UTP_REG_START 0x00a81500
-#define BCHP_SEGDMA_CHAN5_UTP_REG_END 0x00a8153c
-#define BCHP_SEGDMA_CHAN6_UTP_REG_START 0x00a81600
-#define BCHP_SEGDMA_CHAN6_UTP_REG_END 0x00a8163c
-#define BCHP_SEGDMA_CHAN7_UTP_REG_START 0x00a81700
-#define BCHP_SEGDMA_CHAN7_UTP_REG_END 0x00a8173c
-#define BCHP_SEGDMA_FLOW0_UTP_REG_START 0x00a82000
-#define BCHP_SEGDMA_FLOW0_UTP_REG_END 0x00a8207c
-#define BCHP_SEGDMA_FLOW1_UTP_REG_START 0x00a82100
-#define BCHP_SEGDMA_FLOW1_UTP_REG_END 0x00a8217c
-#define BCHP_SEGDMA_FLOW2_UTP_REG_START 0x00a82200
-#define BCHP_SEGDMA_FLOW2_UTP_REG_END 0x00a8227c
-#define BCHP_SEGDMA_FLOW3_UTP_REG_START 0x00a82300
-#define BCHP_SEGDMA_FLOW3_UTP_REG_END 0x00a8237c
-#define BCHP_SEGDMA_FLOW4_UTP_REG_START 0x00a82400
-#define BCHP_SEGDMA_FLOW4_UTP_REG_END 0x00a8247c
-#define BCHP_SEGDMA_FLOW5_UTP_REG_START 0x00a82500
-#define BCHP_SEGDMA_FLOW5_UTP_REG_END 0x00a8257c
-#define BCHP_SEGDMA_FLOW6_UTP_REG_START 0x00a82600
-#define BCHP_SEGDMA_FLOW6_UTP_REG_END 0x00a8267c
-#define BCHP_SEGDMA_FLOW7_UTP_REG_START 0x00a82700
-#define BCHP_SEGDMA_FLOW7_UTP_REG_END 0x00a8277c
-#define BCHP_SEGDMA_FLOW8_UTP_REG_START 0x00a82800
-#define BCHP_SEGDMA_FLOW8_UTP_REG_END 0x00a8287c
-#define BCHP_SEGDMA_FLOW9_UTP_REG_START 0x00a82900
-#define BCHP_SEGDMA_FLOW9_UTP_REG_END 0x00a8297c
-#define BCHP_SEGDMA_FLOW10_UTP_REG_START 0x00a82a00
-#define BCHP_SEGDMA_FLOW10_UTP_REG_END 0x00a82a7c
-#define BCHP_SEGDMA_FLOW11_UTP_REG_START 0x00a82b00
-#define BCHP_SEGDMA_FLOW11_UTP_REG_END 0x00a82b7c
-#define BCHP_SEGDMA_FLOW12_UTP_REG_START 0x00a82c00
-#define BCHP_SEGDMA_FLOW12_UTP_REG_END 0x00a82c7c
-#define BCHP_SEGDMA_FLOW13_UTP_REG_START 0x00a82d00
-#define BCHP_SEGDMA_FLOW13_UTP_REG_END 0x00a82d7c
-#define BCHP_SEGDMA_FLOW14_UTP_REG_START 0x00a82e00
-#define BCHP_SEGDMA_FLOW14_UTP_REG_END 0x00a82e7c
-#define BCHP_SEGDMA_FLOW15_UTP_REG_START 0x00a82f00
-#define BCHP_SEGDMA_FLOW15_UTP_REG_END 0x00a82f7c
-#define BCHP_SEGDMA_FLOW16_UTP_REG_START 0x00a83000
-#define BCHP_SEGDMA_FLOW16_UTP_REG_END 0x00a8307c
-#define BCHP_SEGDMA_FLOW17_UTP_REG_START 0x00a83100
-#define BCHP_SEGDMA_FLOW17_UTP_REG_END 0x00a8317c
-#define BCHP_SEGDMA_FLOW18_UTP_REG_START 0x00a83200
-#define BCHP_SEGDMA_FLOW18_UTP_REG_END 0x00a8327c
-#define BCHP_SEGDMA_FLOW19_UTP_REG_START 0x00a83300
-#define BCHP_SEGDMA_FLOW19_UTP_REG_END 0x00a8337c
-#define BCHP_SEGDMA_FLOW20_UTP_REG_START 0x00a83400
-#define BCHP_SEGDMA_FLOW20_UTP_REG_END 0x00a8347c
-#define BCHP_SEGDMA_FLOW21_UTP_REG_START 0x00a83500
-#define BCHP_SEGDMA_FLOW21_UTP_REG_END 0x00a8357c
-#define BCHP_SEGDMA_FLOW22_UTP_REG_START 0x00a83600
-#define BCHP_SEGDMA_FLOW22_UTP_REG_END 0x00a8367c
-#define BCHP_SEGDMA_FLOW23_UTP_REG_START 0x00a83700
-#define BCHP_SEGDMA_FLOW23_UTP_REG_END 0x00a8377c
-#define BCHP_SEGDMA_FLOW24_UTP_REG_START 0x00a83800
-#define BCHP_SEGDMA_FLOW24_UTP_REG_END 0x00a8387c
-#define BCHP_SEGDMA_FLOW25_UTP_REG_START 0x00a83900
-#define BCHP_SEGDMA_FLOW25_UTP_REG_END 0x00a8397c
-#define BCHP_SEGDMA_FLOW26_UTP_REG_START 0x00a83a00
-#define BCHP_SEGDMA_FLOW26_UTP_REG_END 0x00a83a7c
-#define BCHP_SEGDMA_FLOW27_UTP_REG_START 0x00a83b00
-#define BCHP_SEGDMA_FLOW27_UTP_REG_END 0x00a83b7c
-#define BCHP_SEGDMA_FLOW28_UTP_REG_START 0x00a83c00
-#define BCHP_SEGDMA_FLOW28_UTP_REG_END 0x00a83c7c
-#define BCHP_SEGDMA_FLOW29_UTP_REG_START 0x00a83d00
-#define BCHP_SEGDMA_FLOW29_UTP_REG_END 0x00a83d7c
-#define BCHP_SEGDMA_FLOW30_UTP_REG_START 0x00a83e00
-#define BCHP_SEGDMA_FLOW30_UTP_REG_END 0x00a83e7c
-#define BCHP_SEGDMA_FLOW31_UTP_REG_START 0x00a83f00
-#define BCHP_SEGDMA_FLOW31_UTP_REG_END 0x00a83f7c
-#define BCHP_CRYPTO_UTP_REG_START 0x00a90000
-#define BCHP_CRYPTO_UTP_REG_END 0x00a9d000
-#define BCHP_LEGACY_MAC_USM20_REG_START 0x00e00000
-#define BCHP_LEGACY_MAC_USM20_REG_END 0x00e00a00
-#define BCHP_ChannelRegs_USM30_REG_START 0x00e04000
-#define BCHP_ChannelRegs_USM30_REG_END 0x00e0427c
-#define BCHP_ChannelQueRegs_USM30_REG_START 0x00e04300
-#define BCHP_ChannelQueRegs_USM30_REG_END 0x00e043ab
-#define BCHP_QueueRegs_USM30_REG_START 0x00e04400
-#define BCHP_QueueRegs_USM30_REG_END 0x00e047fc
-#define BCHP_SIDRegs_USM30_REG_START 0x00e04800
-#define BCHP_SIDRegs_USM30_REG_END 0x00e04bfe
-#define BCHP_GroupSIDRegs_USM30_REG_START 0x00e04c00
-#define BCHP_GroupSIDRegs_USM30_REG_END 0x00e04c1e
-#define BCHP_CalcPhyRegs_USM30_REG_START 0x00e05600
-#define BCHP_CalcPhyRegs_USM30_REG_END 0x00e05634
-#define BCHP_SimControlRegs_USM30_REG_START 0x00e05800
-#define BCHP_SimControlRegs_USM30_REG_END 0x00e0587c
-#define BCHP_InterruptRegs_USM30_REG_START 0x00e05900
-#define BCHP_InterruptRegs_USM30_REG_END 0x00e05997
-#define BCHP_MiscRegs_USM30_REG_START 0x00e05a00
-#define BCHP_MiscRegs_USM30_REG_END 0x00e05acc
-#define BCHP_QueueRegs_ReadOnly_USM30_REG_START 0x00e05c00
-#define BCHP_QueueRegs_ReadOnly_USM30_REG_END 0x00e05ff0
-#define BCHP_MIBCountersRegs_USM30_REG_START 0x00e06000
-#define BCHP_MIBCountersRegs_USM30_REG_END 0x00e065fc
-#define BCHP_FlowDiagMIBCountersRegs_USM30_REG_START 0x00e06800
-#define BCHP_FlowDiagMIBCountersRegs_USM30_REG_END 0x00e068fc
-#define BCHP_DiagConfigRegs_USM30_REG_START 0x00e07000
-#define BCHP_DiagConfigRegs_USM30_REG_END 0x00e0704c
-#define BCHP_DiagMsgRegs_USM30_REG_START 0x00e07400
-#define BCHP_DiagMsgRegs_USM30_REG_END 0x00e0743c
-#define BCHP_TC_0_REG_START 0x00e08000
-#define BCHP_TC_0_REG_END 0x00e080c0
-#define BCHP_TC_BANK0_0_REG_START 0x00e08100
-#define BCHP_TC_BANK0_0_REG_END 0x00e0811c
-#define BCHP_TC_BANK1_0_REG_START 0x00e08120
-#define BCHP_TC_BANK1_0_REG_END 0x00e0813c
-#define BCHP_TC_BANK2_0_REG_START 0x00e08140
-#define BCHP_TC_BANK2_0_REG_END 0x00e0815c
-#define BCHP_TC_BANK3_0_REG_START 0x00e08160
-#define BCHP_TC_BANK3_0_REG_END 0x00e0817c
-#define BCHP_TC_BANK4_0_REG_START 0x00e08180
-#define BCHP_TC_BANK4_0_REG_END 0x00e0819c
-#define BCHP_TC_BANK5_0_REG_START 0x00e081a0
-#define BCHP_TC_BANK5_0_REG_END 0x00e081bc
-#define BCHP_TC_BANK6_0_REG_START 0x00e081c0
-#define BCHP_TC_BANK6_0_REG_END 0x00e081dc
-#define BCHP_TC_BANK7_0_REG_START 0x00e081e0
-#define BCHP_TC_BANK7_0_REG_END 0x00e081fc
-#define BCHP_TC_BANK8_0_REG_START 0x00e08200
-#define BCHP_TC_BANK8_0_REG_END 0x00e0821c
-#define BCHP_TC_AUX_0_REG_START 0x00e08300
-#define BCHP_TC_AUX_0_REG_END 0x00e08394
-#define BCHP_TC_PRMBL_0_REG_START 0x00e08400
-#define BCHP_TC_PRMBL_0_REG_END 0x00e084bc
-#define BCHP_TC_AUX_EXT_0_REG_START 0x00e084f0
-#define BCHP_TC_AUX_EXT_0_REG_END 0x00e084f4
-#define BCHP_TC_1_REG_START 0x00e09000
-#define BCHP_TC_1_REG_END 0x00e090c0
-#define BCHP_TC_BANK0_1_REG_START 0x00e09100
-#define BCHP_TC_BANK0_1_REG_END 0x00e0911c
-#define BCHP_TC_BANK1_1_REG_START 0x00e09120
-#define BCHP_TC_BANK1_1_REG_END 0x00e0913c
-#define BCHP_TC_BANK2_1_REG_START 0x00e09140
-#define BCHP_TC_BANK2_1_REG_END 0x00e0915c
-#define BCHP_TC_BANK3_1_REG_START 0x00e09160
-#define BCHP_TC_BANK3_1_REG_END 0x00e0917c
-#define BCHP_TC_BANK4_1_REG_START 0x00e09180
-#define BCHP_TC_BANK4_1_REG_END 0x00e0919c
-#define BCHP_TC_BANK5_1_REG_START 0x00e091a0
-#define BCHP_TC_BANK5_1_REG_END 0x00e091bc
-#define BCHP_TC_BANK6_1_REG_START 0x00e091c0
-#define BCHP_TC_BANK6_1_REG_END 0x00e091dc
-#define BCHP_TC_BANK7_1_REG_START 0x00e091e0
-#define BCHP_TC_BANK7_1_REG_END 0x00e091fc
-#define BCHP_TC_BANK8_1_REG_START 0x00e09200
-#define BCHP_TC_BANK8_1_REG_END 0x00e0921c
-#define BCHP_TC_AUX_1_REG_START 0x00e09300
-#define BCHP_TC_AUX_1_REG_END 0x00e09394
-#define BCHP_TC_PRMBL_1_REG_START 0x00e09400
-#define BCHP_TC_PRMBL_1_REG_END 0x00e094bc
-#define BCHP_TC_AUX_EXT_1_REG_START 0x00e094f0
-#define BCHP_TC_AUX_EXT_1_REG_END 0x00e094f4
-#define BCHP_TC_2_REG_START 0x00e0a000
-#define BCHP_TC_2_REG_END 0x00e0a0c0
-#define BCHP_TC_BANK0_2_REG_START 0x00e0a100
-#define BCHP_TC_BANK0_2_REG_END 0x00e0a11c
-#define BCHP_TC_BANK1_2_REG_START 0x00e0a120
-#define BCHP_TC_BANK1_2_REG_END 0x00e0a13c
-#define BCHP_TC_BANK2_2_REG_START 0x00e0a140
-#define BCHP_TC_BANK2_2_REG_END 0x00e0a15c
-#define BCHP_TC_BANK3_2_REG_START 0x00e0a160
-#define BCHP_TC_BANK3_2_REG_END 0x00e0a17c
-#define BCHP_TC_BANK4_2_REG_START 0x00e0a180
-#define BCHP_TC_BANK4_2_REG_END 0x00e0a19c
-#define BCHP_TC_BANK5_2_REG_START 0x00e0a1a0
-#define BCHP_TC_BANK5_2_REG_END 0x00e0a1bc
-#define BCHP_TC_BANK6_2_REG_START 0x00e0a1c0
-#define BCHP_TC_BANK6_2_REG_END 0x00e0a1dc
-#define BCHP_TC_BANK7_2_REG_START 0x00e0a1e0
-#define BCHP_TC_BANK7_2_REG_END 0x00e0a1fc
-#define BCHP_TC_BANK8_2_REG_START 0x00e0a200
-#define BCHP_TC_BANK8_2_REG_END 0x00e0a21c
-#define BCHP_TC_AUX_2_REG_START 0x00e0a300
-#define BCHP_TC_AUX_2_REG_END 0x00e0a394
-#define BCHP_TC_PRMBL_2_REG_START 0x00e0a400
-#define BCHP_TC_PRMBL_2_REG_END 0x00e0a4bc
-#define BCHP_TC_AUX_EXT_2_REG_START 0x00e0a4f0
-#define BCHP_TC_AUX_EXT_2_REG_END 0x00e0a4f4
-#define BCHP_TC_3_REG_START 0x00e0b000
-#define BCHP_TC_3_REG_END 0x00e0b0c0
-#define BCHP_TC_BANK0_3_REG_START 0x00e0b100
-#define BCHP_TC_BANK0_3_REG_END 0x00e0b11c
-#define BCHP_TC_BANK1_3_REG_START 0x00e0b120
-#define BCHP_TC_BANK1_3_REG_END 0x00e0b13c
-#define BCHP_TC_BANK2_3_REG_START 0x00e0b140
-#define BCHP_TC_BANK2_3_REG_END 0x00e0b15c
-#define BCHP_TC_BANK3_3_REG_START 0x00e0b160
-#define BCHP_TC_BANK3_3_REG_END 0x00e0b17c
-#define BCHP_TC_BANK4_3_REG_START 0x00e0b180
-#define BCHP_TC_BANK4_3_REG_END 0x00e0b19c
-#define BCHP_TC_BANK5_3_REG_START 0x00e0b1a0
-#define BCHP_TC_BANK5_3_REG_END 0x00e0b1bc
-#define BCHP_TC_BANK6_3_REG_START 0x00e0b1c0
-#define BCHP_TC_BANK6_3_REG_END 0x00e0b1dc
-#define BCHP_TC_BANK7_3_REG_START 0x00e0b1e0
-#define BCHP_TC_BANK7_3_REG_END 0x00e0b1fc
-#define BCHP_TC_BANK8_3_REG_START 0x00e0b200
-#define BCHP_TC_BANK8_3_REG_END 0x00e0b21c
-#define BCHP_TC_AUX_3_REG_START 0x00e0b300
-#define BCHP_TC_AUX_3_REG_END 0x00e0b394
-#define BCHP_TC_PRMBL_3_REG_START 0x00e0b400
-#define BCHP_TC_PRMBL_3_REG_END 0x00e0b4bc
-#define BCHP_TC_AUX_EXT_3_REG_START 0x00e0b4f0
-#define BCHP_TC_AUX_EXT_3_REG_END 0x00e0b4f4
-#define BCHP_TC_4_REG_START 0x00e0c000
-#define BCHP_TC_4_REG_END 0x00e0c0c0
-#define BCHP_TC_BANK0_4_REG_START 0x00e0c100
-#define BCHP_TC_BANK0_4_REG_END 0x00e0c11c
-#define BCHP_TC_BANK1_4_REG_START 0x00e0c120
-#define BCHP_TC_BANK1_4_REG_END 0x00e0c13c
-#define BCHP_TC_BANK2_4_REG_START 0x00e0c140
-#define BCHP_TC_BANK2_4_REG_END 0x00e0c15c
-#define BCHP_TC_BANK3_4_REG_START 0x00e0c160
-#define BCHP_TC_BANK3_4_REG_END 0x00e0c17c
-#define BCHP_TC_BANK4_4_REG_START 0x00e0c180
-#define BCHP_TC_BANK4_4_REG_END 0x00e0c19c
-#define BCHP_TC_BANK5_4_REG_START 0x00e0c1a0
-#define BCHP_TC_BANK5_4_REG_END 0x00e0c1bc
-#define BCHP_TC_BANK6_4_REG_START 0x00e0c1c0
-#define BCHP_TC_BANK6_4_REG_END 0x00e0c1dc
-#define BCHP_TC_BANK7_4_REG_START 0x00e0c1e0
-#define BCHP_TC_BANK7_4_REG_END 0x00e0c1fc
-#define BCHP_TC_BANK8_4_REG_START 0x00e0c200
-#define BCHP_TC_BANK8_4_REG_END 0x00e0c21c
-#define BCHP_TC_AUX_4_REG_START 0x00e0c300
-#define BCHP_TC_AUX_4_REG_END 0x00e0c394
-#define BCHP_TC_PRMBL_4_REG_START 0x00e0c400
-#define BCHP_TC_PRMBL_4_REG_END 0x00e0c4bc
-#define BCHP_TC_AUX_EXT_4_REG_START 0x00e0c4f0
-#define BCHP_TC_AUX_EXT_4_REG_END 0x00e0c4f4
-#define BCHP_TC_5_REG_START 0x00e0d000
-#define BCHP_TC_5_REG_END 0x00e0d0c0
-#define BCHP_TC_BANK0_5_REG_START 0x00e0d100
-#define BCHP_TC_BANK0_5_REG_END 0x00e0d11c
-#define BCHP_TC_BANK1_5_REG_START 0x00e0d120
-#define BCHP_TC_BANK1_5_REG_END 0x00e0d13c
-#define BCHP_TC_BANK2_5_REG_START 0x00e0d140
-#define BCHP_TC_BANK2_5_REG_END 0x00e0d15c
-#define BCHP_TC_BANK3_5_REG_START 0x00e0d160
-#define BCHP_TC_BANK3_5_REG_END 0x00e0d17c
-#define BCHP_TC_BANK4_5_REG_START 0x00e0d180
-#define BCHP_TC_BANK4_5_REG_END 0x00e0d19c
-#define BCHP_TC_BANK5_5_REG_START 0x00e0d1a0
-#define BCHP_TC_BANK5_5_REG_END 0x00e0d1bc
-#define BCHP_TC_BANK6_5_REG_START 0x00e0d1c0
-#define BCHP_TC_BANK6_5_REG_END 0x00e0d1dc
-#define BCHP_TC_BANK7_5_REG_START 0x00e0d1e0
-#define BCHP_TC_BANK7_5_REG_END 0x00e0d1fc
-#define BCHP_TC_BANK8_5_REG_START 0x00e0d200
-#define BCHP_TC_BANK8_5_REG_END 0x00e0d21c
-#define BCHP_TC_AUX_5_REG_START 0x00e0d300
-#define BCHP_TC_AUX_5_REG_END 0x00e0d394
-#define BCHP_TC_PRMBL_5_REG_START 0x00e0d400
-#define BCHP_TC_PRMBL_5_REG_END 0x00e0d4bc
-#define BCHP_TC_AUX_EXT_5_REG_START 0x00e0d4f0
-#define BCHP_TC_AUX_EXT_5_REG_END 0x00e0d4f4
-#define BCHP_TC_6_REG_START 0x00e0e000
-#define BCHP_TC_6_REG_END 0x00e0e0c0
-#define BCHP_TC_BANK0_6_REG_START 0x00e0e100
-#define BCHP_TC_BANK0_6_REG_END 0x00e0e11c
-#define BCHP_TC_BANK1_6_REG_START 0x00e0e120
-#define BCHP_TC_BANK1_6_REG_END 0x00e0e13c
-#define BCHP_TC_BANK2_6_REG_START 0x00e0e140
-#define BCHP_TC_BANK2_6_REG_END 0x00e0e15c
-#define BCHP_TC_BANK3_6_REG_START 0x00e0e160
-#define BCHP_TC_BANK3_6_REG_END 0x00e0e17c
-#define BCHP_TC_BANK4_6_REG_START 0x00e0e180
-#define BCHP_TC_BANK4_6_REG_END 0x00e0e19c
-#define BCHP_TC_BANK5_6_REG_START 0x00e0e1a0
-#define BCHP_TC_BANK5_6_REG_END 0x00e0e1bc
-#define BCHP_TC_BANK6_6_REG_START 0x00e0e1c0
-#define BCHP_TC_BANK6_6_REG_END 0x00e0e1dc
-#define BCHP_TC_BANK7_6_REG_START 0x00e0e1e0
-#define BCHP_TC_BANK7_6_REG_END 0x00e0e1fc
-#define BCHP_TC_BANK8_6_REG_START 0x00e0e200
-#define BCHP_TC_BANK8_6_REG_END 0x00e0e21c
-#define BCHP_TC_AUX_6_REG_START 0x00e0e300
-#define BCHP_TC_AUX_6_REG_END 0x00e0e394
-#define BCHP_TC_PRMBL_6_REG_START 0x00e0e400
-#define BCHP_TC_PRMBL_6_REG_END 0x00e0e4bc
-#define BCHP_TC_AUX_EXT_6_REG_START 0x00e0e4f0
-#define BCHP_TC_AUX_EXT_6_REG_END 0x00e0e4f4
-#define BCHP_TC_7_REG_START 0x00e0f000
-#define BCHP_TC_7_REG_END 0x00e0f0c0
-#define BCHP_TC_BANK0_7_REG_START 0x00e0f100
-#define BCHP_TC_BANK0_7_REG_END 0x00e0f11c
-#define BCHP_TC_BANK1_7_REG_START 0x00e0f120
-#define BCHP_TC_BANK1_7_REG_END 0x00e0f13c
-#define BCHP_TC_BANK2_7_REG_START 0x00e0f140
-#define BCHP_TC_BANK2_7_REG_END 0x00e0f15c
-#define BCHP_TC_BANK3_7_REG_START 0x00e0f160
-#define BCHP_TC_BANK3_7_REG_END 0x00e0f17c
-#define BCHP_TC_BANK4_7_REG_START 0x00e0f180
-#define BCHP_TC_BANK4_7_REG_END 0x00e0f19c
-#define BCHP_TC_BANK5_7_REG_START 0x00e0f1a0
-#define BCHP_TC_BANK5_7_REG_END 0x00e0f1bc
-#define BCHP_TC_BANK6_7_REG_START 0x00e0f1c0
-#define BCHP_TC_BANK6_7_REG_END 0x00e0f1dc
-#define BCHP_TC_BANK7_7_REG_START 0x00e0f1e0
-#define BCHP_TC_BANK7_7_REG_END 0x00e0f1fc
-#define BCHP_TC_BANK8_7_REG_START 0x00e0f200
-#define BCHP_TC_BANK8_7_REG_END 0x00e0f21c
-#define BCHP_TC_AUX_7_REG_START 0x00e0f300
-#define BCHP_TC_AUX_7_REG_END 0x00e0f394
-#define BCHP_TC_PRMBL_7_REG_START 0x00e0f400
-#define BCHP_TC_PRMBL_7_REG_END 0x00e0f4bc
-#define BCHP_TC_AUX_EXT_7_REG_START 0x00e0f4f0
-#define BCHP_TC_AUX_EXT_7_REG_END 0x00e0f4f4
-#define BCHP_US_TOP_REG_START 0x00e10000
-#define BCHP_US_TOP_REG_END 0x00e103fc
-#define BCHP_US_MBSC_REG_START 0x00e10400
-#define BCHP_US_MBSC_REG_END 0x00e1047c
-#define BCHP_US_RF_CLIP_REG_START 0x00e10800
-#define BCHP_US_RF_CLIP_REG_END 0x00e10bfc
-#define BCHP_US_PDAC0_REG_START 0x00e10c00
-#define BCHP_US_PDAC0_REG_END 0x00e10c7c
-#define BCHP_US_PDAC1_REG_START 0x00e10c80
-#define BCHP_US_PDAC1_REG_END 0x00e10cfc
-#define BCHP_US_PDAC2_REG_START 0x00e10d00
-#define BCHP_US_PDAC2_REG_END 0x00e10d7c
-#define BCHP_US_PDAC3_REG_START 0x00e10d80
-#define BCHP_US_PDAC3_REG_END 0x00e10dfc
-#define BCHP_US_CORE0_REG_START 0x00e11000
-#define BCHP_US_CORE0_REG_END 0x00e113fc
-#define BCHP_US_CORE1_REG_START 0x00e11400
-#define BCHP_US_CORE1_REG_END 0x00e117fc
-#define BCHP_US_CORE2_REG_START 0x00e11800
-#define BCHP_US_CORE2_REG_END 0x00e11bfc
-#define BCHP_US_CORE3_REG_START 0x00e11c00
-#define BCHP_US_CORE3_REG_END 0x00e11ffc
-#define BCHP_US_CORE4_REG_START 0x00e12000
-#define BCHP_US_CORE4_REG_END 0x00e123fc
-#define BCHP_US_CORE5_REG_START 0x00e12400
-#define BCHP_US_CORE5_REG_END 0x00e127fc
-#define BCHP_US_CORE6_REG_START 0x00e12800
-#define BCHP_US_CORE6_REG_END 0x00e12bfc
-#define BCHP_US_CORE7_REG_START 0x00e12c00
-#define BCHP_US_CORE7_REG_END 0x00e12ffc
-#define BCHP_BaseReserved_DTP_REG_START 0x01000000
-#define BCHP_BaseReserved_DTP_REG_END 0x01000000
-#define BCHP_Control_DTP_REG_START 0x01001000
-#define BCHP_Control_DTP_REG_END 0x010010fc
-#define BCHP_OutgoingMessageFIFO_DTP_REG_START 0x01001100
-#define BCHP_OutgoingMessageFIFO_DTP_REG_END 0x0100117c
-#define BCHP_IncomingMessageFIFO_DTP_REG_START 0x01001200
-#define BCHP_IncomingMessageFIFO_DTP_REG_END 0x0100127c
-#define BCHP_DMA0_DTP_REG_START 0x01001300
-#define BCHP_DMA0_DTP_REG_END 0x0100131c
-#define BCHP_DMA1_DTP_REG_START 0x01001320
-#define BCHP_DMA1_DTP_REG_END 0x0100133c
-#define BCHP_Token_DTP_REG_START 0x01001400
-#define BCHP_Token_DTP_REG_END 0x0100141c
-#define BCHP_PerfPower_DTP_REG_START 0x01001600
-#define BCHP_PerfPower_DTP_REG_END 0x01001640
-#define BCHP_MessageID_DTP_REG_START 0x01001700
-#define BCHP_MessageID_DTP_REG_END 0x0100177c
-#define BCHP_DQM_DTP_REG_START 0x01001800
-#define BCHP_DQM_DTP_REG_END 0x01001848
-#define BCHP_HWCounters_DTP_REG_START 0x01001900
-#define BCHP_HWCounters_DTP_REG_END 0x01001944
-#define BCHP_QUEUE_0_CNTRL_DTP_REG_START 0x01001a00
-#define BCHP_QUEUE_0_CNTRL_DTP_REG_END 0x01001a0c
-#define BCHP_QUEUE_1_CNTRL_DTP_REG_START 0x01001a10
-#define BCHP_QUEUE_1_CNTRL_DTP_REG_END 0x01001a1c
-#define BCHP_QUEUE_2_CNTRL_DTP_REG_START 0x01001a20
-#define BCHP_QUEUE_2_CNTRL_DTP_REG_END 0x01001a2c
-#define BCHP_QUEUE_3_CNTRL_DTP_REG_START 0x01001a30
-#define BCHP_QUEUE_3_CNTRL_DTP_REG_END 0x01001a3c
-#define BCHP_QUEUE_4_CNTRL_DTP_REG_START 0x01001a40
-#define BCHP_QUEUE_4_CNTRL_DTP_REG_END 0x01001a4c
-#define BCHP_QUEUE_5_CNTRL_DTP_REG_START 0x01001a50
-#define BCHP_QUEUE_5_CNTRL_DTP_REG_END 0x01001a5c
-#define BCHP_QUEUE_6_CNTRL_DTP_REG_START 0x01001a60
-#define BCHP_QUEUE_6_CNTRL_DTP_REG_END 0x01001a6c
-#define BCHP_QUEUE_7_CNTRL_DTP_REG_START 0x01001a70
-#define BCHP_QUEUE_7_CNTRL_DTP_REG_END 0x01001a7c
-#define BCHP_QUEUE_8_CNTRL_DTP_REG_START 0x01001a80
-#define BCHP_QUEUE_8_CNTRL_DTP_REG_END 0x01001a8c
-#define BCHP_QUEUE_9_CNTRL_DTP_REG_START 0x01001a90
-#define BCHP_QUEUE_9_CNTRL_DTP_REG_END 0x01001a9c
-#define BCHP_QUEUE_10_CNTRL_DTP_REG_START 0x01001aa0
-#define BCHP_QUEUE_10_CNTRL_DTP_REG_END 0x01001aac
-#define BCHP_QUEUE_11_CNTRL_DTP_REG_START 0x01001ab0
-#define BCHP_QUEUE_11_CNTRL_DTP_REG_END 0x01001abc
-#define BCHP_QUEUE_12_CNTRL_DTP_REG_START 0x01001ac0
-#define BCHP_QUEUE_12_CNTRL_DTP_REG_END 0x01001acc
-#define BCHP_QUEUE_13_CNTRL_DTP_REG_START 0x01001ad0
-#define BCHP_QUEUE_13_CNTRL_DTP_REG_END 0x01001adc
-#define BCHP_QUEUE_14_CNTRL_DTP_REG_START 0x01001ae0
-#define BCHP_QUEUE_14_CNTRL_DTP_REG_END 0x01001aec
-#define BCHP_QUEUE_15_CNTRL_DTP_REG_START 0x01001af0
-#define BCHP_QUEUE_15_CNTRL_DTP_REG_END 0x01001afc
-#define BCHP_QUEUE_16_CNTRL_DTP_REG_START 0x01001b00
-#define BCHP_QUEUE_16_CNTRL_DTP_REG_END 0x01001b0c
-#define BCHP_QUEUE_17_CNTRL_DTP_REG_START 0x01001b10
-#define BCHP_QUEUE_17_CNTRL_DTP_REG_END 0x01001b1c
-#define BCHP_QUEUE_18_CNTRL_DTP_REG_START 0x01001b20
-#define BCHP_QUEUE_18_CNTRL_DTP_REG_END 0x01001b2c
-#define BCHP_QUEUE_19_CNTRL_DTP_REG_START 0x01001b30
-#define BCHP_QUEUE_19_CNTRL_DTP_REG_END 0x01001b3c
-#define BCHP_QUEUE_20_CNTRL_DTP_REG_START 0x01001b40
-#define BCHP_QUEUE_20_CNTRL_DTP_REG_END 0x01001b4c
-#define BCHP_QUEUE_21_CNTRL_DTP_REG_START 0x01001b50
-#define BCHP_QUEUE_21_CNTRL_DTP_REG_END 0x01001b5c
-#define BCHP_QUEUE_22_CNTRL_DTP_REG_START 0x01001b60
-#define BCHP_QUEUE_22_CNTRL_DTP_REG_END 0x01001b6c
-#define BCHP_QUEUE_23_CNTRL_DTP_REG_START 0x01001b70
-#define BCHP_QUEUE_23_CNTRL_DTP_REG_END 0x01001b7c
-#define BCHP_QUEUE_24_CNTRL_DTP_REG_START 0x01001b80
-#define BCHP_QUEUE_24_CNTRL_DTP_REG_END 0x01001b8c
-#define BCHP_QUEUE_25_CNTRL_DTP_REG_START 0x01001b90
-#define BCHP_QUEUE_25_CNTRL_DTP_REG_END 0x01001b9c
-#define BCHP_QUEUE_26_CNTRL_DTP_REG_START 0x01001ba0
-#define BCHP_QUEUE_26_CNTRL_DTP_REG_END 0x01001bac
-#define BCHP_QUEUE_27_CNTRL_DTP_REG_START 0x01001bb0
-#define BCHP_QUEUE_27_CNTRL_DTP_REG_END 0x01001bbc
-#define BCHP_QUEUE_28_CNTRL_DTP_REG_START 0x01001bc0
-#define BCHP_QUEUE_28_CNTRL_DTP_REG_END 0x01001bcc
-#define BCHP_QUEUE_29_CNTRL_DTP_REG_START 0x01001bd0
-#define BCHP_QUEUE_29_CNTRL_DTP_REG_END 0x01001bdc
-#define BCHP_QUEUE_30_CNTRL_DTP_REG_START 0x01001be0
-#define BCHP_QUEUE_30_CNTRL_DTP_REG_END 0x01001bec
-#define BCHP_QUEUE_31_CNTRL_DTP_REG_START 0x01001bf0
-#define BCHP_QUEUE_31_CNTRL_DTP_REG_END 0x01001bfc
-#define BCHP_QUEUE_0_DATA_DTP_REG_START 0x01001c00
-#define BCHP_QUEUE_0_DATA_DTP_REG_END 0x01001c0c
-#define BCHP_QUEUE_1_DATA_DTP_REG_START 0x01001c10
-#define BCHP_QUEUE_1_DATA_DTP_REG_END 0x01001c1c
-#define BCHP_QUEUE_2_DATA_DTP_REG_START 0x01001c20
-#define BCHP_QUEUE_2_DATA_DTP_REG_END 0x01001c2c
-#define BCHP_QUEUE_3_DATA_DTP_REG_START 0x01001c30
-#define BCHP_QUEUE_3_DATA_DTP_REG_END 0x01001c3c
-#define BCHP_QUEUE_4_DATA_DTP_REG_START 0x01001c40
-#define BCHP_QUEUE_4_DATA_DTP_REG_END 0x01001c4c
-#define BCHP_QUEUE_5_DATA_DTP_REG_START 0x01001c50
-#define BCHP_QUEUE_5_DATA_DTP_REG_END 0x01001c5c
-#define BCHP_QUEUE_6_DATA_DTP_REG_START 0x01001c60
-#define BCHP_QUEUE_6_DATA_DTP_REG_END 0x01001c6c
-#define BCHP_QUEUE_7_DATA_DTP_REG_START 0x01001c70
-#define BCHP_QUEUE_7_DATA_DTP_REG_END 0x01001c7c
-#define BCHP_QUEUE_8_DATA_DTP_REG_START 0x01001c80
-#define BCHP_QUEUE_8_DATA_DTP_REG_END 0x01001c8c
-#define BCHP_QUEUE_9_DATA_DTP_REG_START 0x01001c90
-#define BCHP_QUEUE_9_DATA_DTP_REG_END 0x01001c9c
-#define BCHP_QUEUE_10_DATA_DTP_REG_START 0x01001ca0
-#define BCHP_QUEUE_10_DATA_DTP_REG_END 0x01001cac
-#define BCHP_QUEUE_11_DATA_DTP_REG_START 0x01001cb0
-#define BCHP_QUEUE_11_DATA_DTP_REG_END 0x01001cbc
-#define BCHP_QUEUE_12_DATA_DTP_REG_START 0x01001cc0
-#define BCHP_QUEUE_12_DATA_DTP_REG_END 0x01001ccc
-#define BCHP_QUEUE_13_DATA_DTP_REG_START 0x01001cd0
-#define BCHP_QUEUE_13_DATA_DTP_REG_END 0x01001cdc
-#define BCHP_QUEUE_14_DATA_DTP_REG_START 0x01001ce0
-#define BCHP_QUEUE_14_DATA_DTP_REG_END 0x01001cec
-#define BCHP_QUEUE_15_DATA_DTP_REG_START 0x01001cf0
-#define BCHP_QUEUE_15_DATA_DTP_REG_END 0x01001cfc
-#define BCHP_QUEUE_16_DATA_DTP_REG_START 0x01001d00
-#define BCHP_QUEUE_16_DATA_DTP_REG_END 0x01001d0c
-#define BCHP_QUEUE_17_DATA_DTP_REG_START 0x01001d10
-#define BCHP_QUEUE_17_DATA_DTP_REG_END 0x01001d1c
-#define BCHP_QUEUE_18_DATA_DTP_REG_START 0x01001d20
-#define BCHP_QUEUE_18_DATA_DTP_REG_END 0x01001d2c
-#define BCHP_QUEUE_19_DATA_DTP_REG_START 0x01001d30
-#define BCHP_QUEUE_19_DATA_DTP_REG_END 0x01001d3c
-#define BCHP_QUEUE_20_DATA_DTP_REG_START 0x01001d40
-#define BCHP_QUEUE_20_DATA_DTP_REG_END 0x01001d4c
-#define BCHP_QUEUE_21_DATA_DTP_REG_START 0x01001d50
-#define BCHP_QUEUE_21_DATA_DTP_REG_END 0x01001d5c
-#define BCHP_QUEUE_22_DATA_DTP_REG_START 0x01001d60
-#define BCHP_QUEUE_22_DATA_DTP_REG_END 0x01001d6c
-#define BCHP_QUEUE_23_DATA_DTP_REG_START 0x01001d70
-#define BCHP_QUEUE_23_DATA_DTP_REG_END 0x01001d7c
-#define BCHP_QUEUE_24_DATA_DTP_REG_START 0x01001d80
-#define BCHP_QUEUE_24_DATA_DTP_REG_END 0x01001d8c
-#define BCHP_QUEUE_25_DATA_DTP_REG_START 0x01001d90
-#define BCHP_QUEUE_25_DATA_DTP_REG_END 0x01001d9c
-#define BCHP_QUEUE_26_DATA_DTP_REG_START 0x01001da0
-#define BCHP_QUEUE_26_DATA_DTP_REG_END 0x01001dac
-#define BCHP_QUEUE_27_DATA_DTP_REG_START 0x01001db0
-#define BCHP_QUEUE_27_DATA_DTP_REG_END 0x01001dbc
-#define BCHP_QUEUE_28_DATA_DTP_REG_START 0x01001dc0
-#define BCHP_QUEUE_28_DATA_DTP_REG_END 0x01001dcc
-#define BCHP_QUEUE_29_DATA_DTP_REG_START 0x01001dd0
-#define BCHP_QUEUE_29_DATA_DTP_REG_END 0x01001ddc
-#define BCHP_QUEUE_30_DATA_DTP_REG_START 0x01001de0
-#define BCHP_QUEUE_30_DATA_DTP_REG_END 0x01001dec
-#define BCHP_QUEUE_31_DATA_DTP_REG_START 0x01001df0
-#define BCHP_QUEUE_31_DATA_DTP_REG_END 0x01001dfc
-#define BCHP_QUEUE_STATUS_DTP_REG_START 0x01001f00
-#define BCHP_QUEUE_STATUS_DTP_REG_END 0x01001f7c
-#define BCHP_QUEUE_MIB_DTP_REG_START 0x01002000
-#define BCHP_QUEUE_MIB_DTP_REG_END 0x0100217c
-#define BCHP_QUEUE_TIMER_DTP_REG_START 0x01002c00
-#define BCHP_QUEUE_TIMER_DTP_REG_END 0x01002cfc
-#define BCHP_SharedMem_DTP_REG_START 0x01004000
-#define BCHP_SharedMem_DTP_REG_END 0x0100fffc
-#define BCHP_DSRM_DTP_REG_START 0x01040000
-#define BCHP_DSRM_DTP_REG_END 0x010406ec
-#define BCHP_DSRM_TAG_CACHE_MEM_DTP_REG_START 0x01040700
-#define BCHP_DSRM_TAG_CACHE_MEM_DTP_REG_END 0x010407fc
-#define BCHP_DSRM_STATE_MEM_DTP_REG_START 0x01041000
-#define BCHP_DSRM_STATE_MEM_DTP_REG_END 0x010417fc
-#define BCHP_DSRM_STATS_MEM_DTP_REG_START 0x01042000
-#define BCHP_DSRM_STATS_MEM_DTP_REG_END 0x01042ffc
-#define BCHP_DSRM_TMOUT_MEM_DTP_REG_START 0x01043000
-#define BCHP_DSRM_TMOUT_MEM_DTP_REG_END 0x01043ffc
-#define BCHP_DSRM_TAG_MEM_DTP_REG_START 0x01044000
-#define BCHP_DSRM_TAG_MEM_DTP_REG_END 0x01045ffc
-#define BCHP_DSRM_RLD_MEM_DTP_REG_START 0x01046000
-#define BCHP_DSRM_RLD_MEM_DTP_REG_END 0x01046ffc
-#define BCHP_DSRM_FREE_CLSTR_MEM_DTP_REG_START 0x01047000
-#define BCHP_DSRM_FREE_CLSTR_MEM_DTP_REG_END 0x010473fc
-#define BCHP_DSRM_CLSTR_MEM_DTP_REG_START 0x01050000
-#define BCHP_DSRM_CLSTR_MEM_DTP_REG_END 0x01057ffc
-#define BCHP_DSRM_SPARSE_ARY_MEM_DTP_REG_START 0x01080000
-#define BCHP_DSRM_SPARSE_ARY_MEM_DTP_REG_END 0x010bfffc
-#define BCHP_DSRM_SPARSE_ARY_AUX_MEM_DTP_REG_START 0x010c0000
-#define BCHP_DSRM_SPARSE_ARY_AUX_MEM_DTP_REG_END 0x010ffffc
-#define BCHP_BaseReserved_DFAP_REG_START 0x01200000
-#define BCHP_BaseReserved_DFAP_REG_END 0x01200000
-#define BCHP_Control_DFAP_REG_START 0x01201000
-#define BCHP_Control_DFAP_REG_END 0x012010fc
-#define BCHP_OutgoingMessageFIFO_DFAP_REG_START 0x01201100
-#define BCHP_OutgoingMessageFIFO_DFAP_REG_END 0x0120117c
-#define BCHP_IncomingMessageFIFO_DFAP_REG_START 0x01201200
-#define BCHP_IncomingMessageFIFO_DFAP_REG_END 0x0120127c
-#define BCHP_DMA0_DFAP_REG_START 0x01201300
-#define BCHP_DMA0_DFAP_REG_END 0x0120131c
-#define BCHP_DMA1_DFAP_REG_START 0x01201320
-#define BCHP_DMA1_DFAP_REG_END 0x0120133c
-#define BCHP_Token_DFAP_REG_START 0x01201400
-#define BCHP_Token_DFAP_REG_END 0x0120141c
-#define BCHP_PerfPower_DFAP_REG_START 0x01201600
-#define BCHP_PerfPower_DFAP_REG_END 0x01201640
-#define BCHP_MessageID_DFAP_REG_START 0x01201700
-#define BCHP_MessageID_DFAP_REG_END 0x0120177c
-#define BCHP_DQM_DFAP_REG_START 0x01201800
-#define BCHP_DQM_DFAP_REG_END 0x01201848
-#define BCHP_HWCounters_DFAP_REG_START 0x01201900
-#define BCHP_HWCounters_DFAP_REG_END 0x01201944
-#define BCHP_QUEUE_0_CNTRL_DFAP_REG_START 0x01201a00
-#define BCHP_QUEUE_0_CNTRL_DFAP_REG_END 0x01201a0c
-#define BCHP_QUEUE_1_CNTRL_DFAP_REG_START 0x01201a10
-#define BCHP_QUEUE_1_CNTRL_DFAP_REG_END 0x01201a1c
-#define BCHP_QUEUE_2_CNTRL_DFAP_REG_START 0x01201a20
-#define BCHP_QUEUE_2_CNTRL_DFAP_REG_END 0x01201a2c
-#define BCHP_QUEUE_3_CNTRL_DFAP_REG_START 0x01201a30
-#define BCHP_QUEUE_3_CNTRL_DFAP_REG_END 0x01201a3c
-#define BCHP_QUEUE_4_CNTRL_DFAP_REG_START 0x01201a40
-#define BCHP_QUEUE_4_CNTRL_DFAP_REG_END 0x01201a4c
-#define BCHP_QUEUE_5_CNTRL_DFAP_REG_START 0x01201a50
-#define BCHP_QUEUE_5_CNTRL_DFAP_REG_END 0x01201a5c
-#define BCHP_QUEUE_6_CNTRL_DFAP_REG_START 0x01201a60
-#define BCHP_QUEUE_6_CNTRL_DFAP_REG_END 0x01201a6c
-#define BCHP_QUEUE_7_CNTRL_DFAP_REG_START 0x01201a70
-#define BCHP_QUEUE_7_CNTRL_DFAP_REG_END 0x01201a7c
-#define BCHP_QUEUE_8_CNTRL_DFAP_REG_START 0x01201a80
-#define BCHP_QUEUE_8_CNTRL_DFAP_REG_END 0x01201a8c
-#define BCHP_QUEUE_9_CNTRL_DFAP_REG_START 0x01201a90
-#define BCHP_QUEUE_9_CNTRL_DFAP_REG_END 0x01201a9c
-#define BCHP_QUEUE_10_CNTRL_DFAP_REG_START 0x01201aa0
-#define BCHP_QUEUE_10_CNTRL_DFAP_REG_END 0x01201aac
-#define BCHP_QUEUE_11_CNTRL_DFAP_REG_START 0x01201ab0
-#define BCHP_QUEUE_11_CNTRL_DFAP_REG_END 0x01201abc
-#define BCHP_QUEUE_12_CNTRL_DFAP_REG_START 0x01201ac0
-#define BCHP_QUEUE_12_CNTRL_DFAP_REG_END 0x01201acc
-#define BCHP_QUEUE_13_CNTRL_DFAP_REG_START 0x01201ad0
-#define BCHP_QUEUE_13_CNTRL_DFAP_REG_END 0x01201adc
-#define BCHP_QUEUE_14_CNTRL_DFAP_REG_START 0x01201ae0
-#define BCHP_QUEUE_14_CNTRL_DFAP_REG_END 0x01201aec
-#define BCHP_QUEUE_15_CNTRL_DFAP_REG_START 0x01201af0
-#define BCHP_QUEUE_15_CNTRL_DFAP_REG_END 0x01201afc
-#define BCHP_QUEUE_16_CNTRL_DFAP_REG_START 0x01201b00
-#define BCHP_QUEUE_16_CNTRL_DFAP_REG_END 0x01201b0c
-#define BCHP_QUEUE_17_CNTRL_DFAP_REG_START 0x01201b10
-#define BCHP_QUEUE_17_CNTRL_DFAP_REG_END 0x01201b1c
-#define BCHP_QUEUE_18_CNTRL_DFAP_REG_START 0x01201b20
-#define BCHP_QUEUE_18_CNTRL_DFAP_REG_END 0x01201b2c
-#define BCHP_QUEUE_19_CNTRL_DFAP_REG_START 0x01201b30
-#define BCHP_QUEUE_19_CNTRL_DFAP_REG_END 0x01201b3c
-#define BCHP_QUEUE_20_CNTRL_DFAP_REG_START 0x01201b40
-#define BCHP_QUEUE_20_CNTRL_DFAP_REG_END 0x01201b4c
-#define BCHP_QUEUE_21_CNTRL_DFAP_REG_START 0x01201b50
-#define BCHP_QUEUE_21_CNTRL_DFAP_REG_END 0x01201b5c
-#define BCHP_QUEUE_22_CNTRL_DFAP_REG_START 0x01201b60
-#define BCHP_QUEUE_22_CNTRL_DFAP_REG_END 0x01201b6c
-#define BCHP_QUEUE_23_CNTRL_DFAP_REG_START 0x01201b70
-#define BCHP_QUEUE_23_CNTRL_DFAP_REG_END 0x01201b7c
-#define BCHP_QUEUE_24_CNTRL_DFAP_REG_START 0x01201b80
-#define BCHP_QUEUE_24_CNTRL_DFAP_REG_END 0x01201b8c
-#define BCHP_QUEUE_25_CNTRL_DFAP_REG_START 0x01201b90
-#define BCHP_QUEUE_25_CNTRL_DFAP_REG_END 0x01201b9c
-#define BCHP_QUEUE_26_CNTRL_DFAP_REG_START 0x01201ba0
-#define BCHP_QUEUE_26_CNTRL_DFAP_REG_END 0x01201bac
-#define BCHP_QUEUE_27_CNTRL_DFAP_REG_START 0x01201bb0
-#define BCHP_QUEUE_27_CNTRL_DFAP_REG_END 0x01201bbc
-#define BCHP_QUEUE_28_CNTRL_DFAP_REG_START 0x01201bc0
-#define BCHP_QUEUE_28_CNTRL_DFAP_REG_END 0x01201bcc
-#define BCHP_QUEUE_29_CNTRL_DFAP_REG_START 0x01201bd0
-#define BCHP_QUEUE_29_CNTRL_DFAP_REG_END 0x01201bdc
-#define BCHP_QUEUE_30_CNTRL_DFAP_REG_START 0x01201be0
-#define BCHP_QUEUE_30_CNTRL_DFAP_REG_END 0x01201bec
-#define BCHP_QUEUE_31_CNTRL_DFAP_REG_START 0x01201bf0
-#define BCHP_QUEUE_31_CNTRL_DFAP_REG_END 0x01201bfc
-#define BCHP_QUEUE_0_DATA_DFAP_REG_START 0x01201c00
-#define BCHP_QUEUE_0_DATA_DFAP_REG_END 0x01201c0c
-#define BCHP_QUEUE_1_DATA_DFAP_REG_START 0x01201c10
-#define BCHP_QUEUE_1_DATA_DFAP_REG_END 0x01201c1c
-#define BCHP_QUEUE_2_DATA_DFAP_REG_START 0x01201c20
-#define BCHP_QUEUE_2_DATA_DFAP_REG_END 0x01201c2c
-#define BCHP_QUEUE_3_DATA_DFAP_REG_START 0x01201c30
-#define BCHP_QUEUE_3_DATA_DFAP_REG_END 0x01201c3c
-#define BCHP_QUEUE_4_DATA_DFAP_REG_START 0x01201c40
-#define BCHP_QUEUE_4_DATA_DFAP_REG_END 0x01201c4c
-#define BCHP_QUEUE_5_DATA_DFAP_REG_START 0x01201c50
-#define BCHP_QUEUE_5_DATA_DFAP_REG_END 0x01201c5c
-#define BCHP_QUEUE_6_DATA_DFAP_REG_START 0x01201c60
-#define BCHP_QUEUE_6_DATA_DFAP_REG_END 0x01201c6c
-#define BCHP_QUEUE_7_DATA_DFAP_REG_START 0x01201c70
-#define BCHP_QUEUE_7_DATA_DFAP_REG_END 0x01201c7c
-#define BCHP_QUEUE_8_DATA_DFAP_REG_START 0x01201c80
-#define BCHP_QUEUE_8_DATA_DFAP_REG_END 0x01201c8c
-#define BCHP_QUEUE_9_DATA_DFAP_REG_START 0x01201c90
-#define BCHP_QUEUE_9_DATA_DFAP_REG_END 0x01201c9c
-#define BCHP_QUEUE_10_DATA_DFAP_REG_START 0x01201ca0
-#define BCHP_QUEUE_10_DATA_DFAP_REG_END 0x01201cac
-#define BCHP_QUEUE_11_DATA_DFAP_REG_START 0x01201cb0
-#define BCHP_QUEUE_11_DATA_DFAP_REG_END 0x01201cbc
-#define BCHP_QUEUE_12_DATA_DFAP_REG_START 0x01201cc0
-#define BCHP_QUEUE_12_DATA_DFAP_REG_END 0x01201ccc
-#define BCHP_QUEUE_13_DATA_DFAP_REG_START 0x01201cd0
-#define BCHP_QUEUE_13_DATA_DFAP_REG_END 0x01201cdc
-#define BCHP_QUEUE_14_DATA_DFAP_REG_START 0x01201ce0
-#define BCHP_QUEUE_14_DATA_DFAP_REG_END 0x01201cec
-#define BCHP_QUEUE_15_DATA_DFAP_REG_START 0x01201cf0
-#define BCHP_QUEUE_15_DATA_DFAP_REG_END 0x01201cfc
-#define BCHP_QUEUE_16_DATA_DFAP_REG_START 0x01201d00
-#define BCHP_QUEUE_16_DATA_DFAP_REG_END 0x01201d0c
-#define BCHP_QUEUE_17_DATA_DFAP_REG_START 0x01201d10
-#define BCHP_QUEUE_17_DATA_DFAP_REG_END 0x01201d1c
-#define BCHP_QUEUE_18_DATA_DFAP_REG_START 0x01201d20
-#define BCHP_QUEUE_18_DATA_DFAP_REG_END 0x01201d2c
-#define BCHP_QUEUE_19_DATA_DFAP_REG_START 0x01201d30
-#define BCHP_QUEUE_19_DATA_DFAP_REG_END 0x01201d3c
-#define BCHP_QUEUE_20_DATA_DFAP_REG_START 0x01201d40
-#define BCHP_QUEUE_20_DATA_DFAP_REG_END 0x01201d4c
-#define BCHP_QUEUE_21_DATA_DFAP_REG_START 0x01201d50
-#define BCHP_QUEUE_21_DATA_DFAP_REG_END 0x01201d5c
-#define BCHP_QUEUE_22_DATA_DFAP_REG_START 0x01201d60
-#define BCHP_QUEUE_22_DATA_DFAP_REG_END 0x01201d6c
-#define BCHP_QUEUE_23_DATA_DFAP_REG_START 0x01201d70
-#define BCHP_QUEUE_23_DATA_DFAP_REG_END 0x01201d7c
-#define BCHP_QUEUE_24_DATA_DFAP_REG_START 0x01201d80
-#define BCHP_QUEUE_24_DATA_DFAP_REG_END 0x01201d8c
-#define BCHP_QUEUE_25_DATA_DFAP_REG_START 0x01201d90
-#define BCHP_QUEUE_25_DATA_DFAP_REG_END 0x01201d9c
-#define BCHP_QUEUE_26_DATA_DFAP_REG_START 0x01201da0
-#define BCHP_QUEUE_26_DATA_DFAP_REG_END 0x01201dac
-#define BCHP_QUEUE_27_DATA_DFAP_REG_START 0x01201db0
-#define BCHP_QUEUE_27_DATA_DFAP_REG_END 0x01201dbc
-#define BCHP_QUEUE_28_DATA_DFAP_REG_START 0x01201dc0
-#define BCHP_QUEUE_28_DATA_DFAP_REG_END 0x01201dcc
-#define BCHP_QUEUE_29_DATA_DFAP_REG_START 0x01201dd0
-#define BCHP_QUEUE_29_DATA_DFAP_REG_END 0x01201ddc
-#define BCHP_QUEUE_30_DATA_DFAP_REG_START 0x01201de0
-#define BCHP_QUEUE_30_DATA_DFAP_REG_END 0x01201dec
-#define BCHP_QUEUE_31_DATA_DFAP_REG_START 0x01201df0
-#define BCHP_QUEUE_31_DATA_DFAP_REG_END 0x01201dfc
-#define BCHP_QUEUE_STATUS_DFAP_REG_START 0x01201f00
-#define BCHP_QUEUE_STATUS_DFAP_REG_END 0x01201f7c
-#define BCHP_QUEUE_MIB_DFAP_REG_START 0x01202000
-#define BCHP_QUEUE_MIB_DFAP_REG_END 0x0120217c
-#define BCHP_QUEUE_TIMER_DFAP_REG_START 0x01202c00
-#define BCHP_QUEUE_TIMER_DFAP_REG_END 0x01202cfc
-#define BCHP_SharedMem_DFAP_REG_START 0x01204000
-#define BCHP_SharedMem_DFAP_REG_END 0x0120fffc
-#define BCHP_Memory_DFAP_REG_START 0x01210000
-#define BCHP_Memory_DFAP_REG_END 0x01217ffc
-#define BCHP_DPE_BASIC_DFAP_REG_START 0x01300000
-#define BCHP_DPE_BASIC_DFAP_REG_END 0x01300094
-#define BCHP_DPE_MPEG_DFAP_REG_START 0x01300200
-#define BCHP_DPE_MPEG_DFAP_REG_END 0x0130034c
-#define BCHP_DPE_HW_DFAP_REG_START 0x01300400
-#define BCHP_DPE_HW_DFAP_REG_END 0x01300f3c
-#define BCHP_FFE_N_0_DFAP_REG_START 0x01350000
-#define BCHP_FFE_N_0_DFAP_REG_END 0x013503fc
-#define BCHP_FFE_P_0_DFAP_REG_START 0x01351000
-#define BCHP_FFE_P_0_DFAP_REG_END 0x013517fc
-#define BCHP_FFE_I_0_DFAP_REG_START 0x01354000
-#define BCHP_FFE_I_0_DFAP_REG_END 0x01357ffc
-#define BCHP_FFE_N_1_DFAP_REG_START 0x01370000
-#define BCHP_FFE_N_1_DFAP_REG_END 0x013703fc
-#define BCHP_FFE_P_1_DFAP_REG_START 0x01371000
-#define BCHP_FFE_P_1_DFAP_REG_END 0x013717fc
-#define BCHP_FFE_I_1_DFAP_REG_START 0x01374000
-#define BCHP_FFE_I_1_DFAP_REG_END 0x01377ffc
-#define BCHP_DOWNSTREAM_0_REG_START 0x01400000
-#define BCHP_DOWNSTREAM_0_REG_END 0x01405b7f
-#define BCHP_DOWNSTREAM_1_REG_START 0x01600000
-#define BCHP_DOWNSTREAM_1_REG_END 0x01605b7f
-#define BCHP_DOWNSTREAM_2_REG_START 0x01800000
-#define BCHP_DOWNSTREAM_2_REG_END 0x01805b7f
-#define BCHP_DOWNSTREAM_3_REG_START 0x01a00000
-#define BCHP_DOWNSTREAM_3_REG_END 0x01a05b7f
-#define BCHP_APM_BASE_APM_REG_START 0x01c00000
-#define BCHP_APM_BASE_APM_REG_END 0x01c001f8
-#define BCHP_APM_PCM_APM_REG_START 0x01c00200
-#define BCHP_APM_PCM_APM_REG_END 0x01c0027c
-#define BCHP_HVG_BASE_APM_REG_START 0x01c00300
-#define BCHP_HVG_BASE_APM_REG_END 0x01c00460
-#define BCHP_APM_DMA_CTRL_APM_REG_START 0x01c00800
-#define BCHP_APM_DMA_CTRL_APM_REG_END 0x01c00844
-#define BCHP_APM_DMA_CH1_APM_REG_START 0x01c00a00
-#define BCHP_APM_DMA_CH1_APM_REG_END 0x01c00a0c
-#define BCHP_APM_DMA_CH2_APM_REG_START 0x01c00a10
-#define BCHP_APM_DMA_CH2_APM_REG_END 0x01c00a1c
-#define BCHP_APM_DMA_CH3_APM_REG_START 0x01c00a20
-#define BCHP_APM_DMA_CH3_APM_REG_END 0x01c00a2c
-#define BCHP_APM_DMA_CH4_APM_REG_START 0x01c00a30
-#define BCHP_APM_DMA_CH4_APM_REG_END 0x01c00a3c
-#define BCHP_APM_DMA_CH5_APM_REG_START 0x01c00a40
-#define BCHP_APM_DMA_CH5_APM_REG_END 0x01c00a4c
-#define BCHP_APM_DMA_CH6_APM_REG_START 0x01c00a50
-#define BCHP_APM_DMA_CH6_APM_REG_END 0x01c00a5c
-#define BCHP_APM_DMA_CH1_STATE_APM_REG_START 0x01c00c00
-#define BCHP_APM_DMA_CH1_STATE_APM_REG_END 0x01c00c0c
-#define BCHP_APM_DMA_CH2_STATE_APM_REG_START 0x01c00c10
-#define BCHP_APM_DMA_CH2_STATE_APM_REG_END 0x01c00c1c
-#define BCHP_APM_DMA_CH3_STATE_APM_REG_START 0x01c00c20
-#define BCHP_APM_DMA_CH3_STATE_APM_REG_END 0x01c00c2c
-#define BCHP_APM_DMA_CH4_STATE_APM_REG_START 0x01c00c30
-#define BCHP_APM_DMA_CH4_STATE_APM_REG_END 0x01c00c3c
-#define BCHP_APM_DMA_CH5_STATE_APM_REG_START 0x01c00c40
-#define BCHP_APM_DMA_CH5_STATE_APM_REG_END 0x01c00c4c
-#define BCHP_APM_DMA_CH6_STATE_APM_REG_START 0x01c00c50
-#define BCHP_APM_DMA_CH6_STATE_APM_REG_END 0x01c00c5c
-#define BCHP_BMU_DMEM_BMU_REG_START 0x01c01000
-#define BCHP_BMU_DMEM_BMU_REG_END 0x01c013fc
-#define BCHP_BMU_SMEM_BMU_REG_START 0x01c01400
-#define BCHP_BMU_SMEM_BMU_REG_END 0x01c015fc
-#define BCHP_BMU_LS_BMU_REG_START 0x01c01800
-#define BCHP_BMU_LS_BMU_REG_END 0x01c0191c
-#define BCHP_BMU_CP_BMU_REG_START 0x01c01c00
-#define BCHP_BMU_CP_BMU_REG_END 0x01c01d0c
-#define BCHP_PICO_IMEM_PICO_REG_START 0x01c10000
-#define BCHP_PICO_IMEM_PICO_REG_END 0x01c127fc
-#define BCHP_DECT_AHB_DCT_REG_START 0x01e00000
-#define BCHP_DECT_AHB_DCT_REG_END 0x01e07f80
-#define BCHP_DECT_SHM_DCT_REG_START 0x01e10000
-#define BCHP_DECT_SHM_DCT_REG_END 0x01e100ac
-#define BCHP_DECT_APB_DCT_REG_START 0x01e10800
-#define BCHP_DECT_APB_DCT_REG_END 0x01e10802
-#define BCHP_LEAP_ROM_REG_START 0x02060000
-#define BCHP_LEAP_ROM_REG_END 0x02067ffc
-#define BCHP_LEAP_CPU_CORE_REGS_REG_START 0x02080000
-#define BCHP_LEAP_CPU_CORE_REGS_REG_END 0x020800fc
-#define BCHP_LEAP_CPU_AUX_REGS_REG_START 0x020a0000
-#define BCHP_LEAP_CPU_AUX_REGS_REG_END 0x020a1058
-#define BCHP_LEAP_UART_REG_START 0x020a9000
-#define BCHP_LEAP_UART_REG_END 0x020a9ffc
-#define BCHP_LEAP_WDG_REG_START 0x020aa000
-#define BCHP_LEAP_WDG_REG_END 0x020aaffc
-#define BCHP_LEAP_CTRL_REG_START 0x02100000
-#define BCHP_LEAP_CTRL_REG_END 0x021001fc
-#define BCHP_LEAP_L1_REG_START 0x02100200
-#define BCHP_LEAP_L1_REG_END 0x02100218
-#define BCHP_LEAP_L2_REG_START 0x02100300
-#define BCHP_LEAP_L2_REG_END 0x02100314
-#define BCHP_LEAP_HOST_L1_REG_START 0x02100400
-#define BCHP_LEAP_HOST_L1_REG_END 0x02100418
-#define BCHP_LEAP_HOST_L2_REG_START 0x02100500
-#define BCHP_LEAP_HOST_L2_REG_END 0x02100514
-#define BCHP_LEAP_ROM_PATCH_REG_START 0x02100a00
-#define BCHP_LEAP_ROM_PATCH_REG_END 0x02100a3c
-#define BCHP_DS_WFE_MICRO_REG_START 0x02200000
-#define BCHP_DS_WFE_MICRO_REG_END 0x02200074
-#define BCHP_DS_WFE_FS_REG_START 0x02201400
-#define BCHP_DS_WFE_FS_REG_END 0x02201444
-#define BCHP_DS_WFE_FC_A_REG_START 0x02201800
-#define BCHP_DS_WFE_FC_A_REG_END 0x02201844
-#define BCHP_DS_WFE_FC_B_REG_START 0x02201c00
-#define BCHP_DS_WFE_FC_B_REG_END 0x02201c44
-#define BCHP_DS_WFE_CZ_0_REG_START 0x02202000
-#define BCHP_DS_WFE_CZ_0_REG_END 0x02202010
-#define BCHP_DS_WFE_CZ_1_REG_START 0x02202400
-#define BCHP_DS_WFE_CZ_1_REG_END 0x02202410
-#define BCHP_DS_WFE_CZ_2_REG_START 0x02202800
-#define BCHP_DS_WFE_CZ_2_REG_END 0x02202810
-#define BCHP_DS_WFE_CZ_3_REG_START 0x02202c00
-#define BCHP_DS_WFE_CZ_3_REG_END 0x02202c10
-#define BCHP_DS_WFE_CZ_4_REG_START 0x02203000
-#define BCHP_DS_WFE_CZ_4_REG_END 0x02203010
-#define BCHP_DS_WFE_CZ_5_REG_START 0x02203400
-#define BCHP_DS_WFE_CZ_5_REG_END 0x02203410
-#define BCHP_DS_WFE_CZ_6_REG_START 0x02203800
-#define BCHP_DS_WFE_CZ_6_REG_END 0x02203810
-#define BCHP_DS_WFE_CZ_7_REG_START 0x02203c00
-#define BCHP_DS_WFE_CZ_7_REG_END 0x02203c10
-#define BCHP_DS_WFE_CZ_8_REG_START 0x02204000
-#define BCHP_DS_WFE_CZ_8_REG_END 0x02204010
-#define BCHP_DS_WFE_CZ_9_REG_START 0x02204400
-#define BCHP_DS_WFE_CZ_9_REG_END 0x02204410
-#define BCHP_DS_WFE_CZ_10_REG_START 0x02204800
-#define BCHP_DS_WFE_CZ_10_REG_END 0x02204810
-#define BCHP_DS_WFE_CZ_11_REG_START 0x02204c00
-#define BCHP_DS_WFE_CZ_11_REG_END 0x02204c10
-#define BCHP_DS_WFE_CZ_12_REG_START 0x02205000
-#define BCHP_DS_WFE_CZ_12_REG_END 0x02205010
-#define BCHP_DS_WFE_CZ_13_REG_START 0x02205400
-#define BCHP_DS_WFE_CZ_13_REG_END 0x02205410
-#define BCHP_DS_WFE_CZ_14_REG_START 0x02205800
-#define BCHP_DS_WFE_CZ_14_REG_END 0x02205810
-#define BCHP_DS_WFE_CZ_15_REG_START 0x02205c00
-#define BCHP_DS_WFE_CZ_15_REG_END 0x02205c10
-#define BCHP_DS_WFE_CZ_16_REG_START 0x02206000
-#define BCHP_DS_WFE_CZ_16_REG_END 0x02206010
-#define BCHP_DS_WFE_CZ_17_REG_START 0x02206400
-#define BCHP_DS_WFE_CZ_17_REG_END 0x02206410
-#define BCHP_DS_WFE_CZ_18_REG_START 0x02206800
-#define BCHP_DS_WFE_CZ_18_REG_END 0x02206810
-#define BCHP_DS_WFE_CZ_19_REG_START 0x02206c00
-#define BCHP_DS_WFE_CZ_19_REG_END 0x02206c10
-#define BCHP_DS_WFE_CZ_20_REG_START 0x02207000
-#define BCHP_DS_WFE_CZ_20_REG_END 0x02207010
-#define BCHP_DS_WFE_CZ_21_REG_START 0x02207400
-#define BCHP_DS_WFE_CZ_21_REG_END 0x02207410
-#define BCHP_DS_WFE_CZ_22_REG_START 0x02207800
-#define BCHP_DS_WFE_CZ_22_REG_END 0x02207810
-#define BCHP_DS_WFE_CZ_23_REG_START 0x02207c00
-#define BCHP_DS_WFE_CZ_23_REG_END 0x02207c10
-#define BCHP_DS_WFE_CZ_24_REG_START 0x02208000
-#define BCHP_DS_WFE_CZ_24_REG_END 0x02208010
-#define BCHP_DS_WFE_CZ_25_REG_START 0x02208400
-#define BCHP_DS_WFE_CZ_25_REG_END 0x02208410
-#define BCHP_DS_WFE_CZ_26_REG_START 0x02208800
-#define BCHP_DS_WFE_CZ_26_REG_END 0x02208810
-#define BCHP_DS_WFE_CZ_27_REG_START 0x02208c00
-#define BCHP_DS_WFE_CZ_27_REG_END 0x02208c10
-#define BCHP_DS_WFE_CZ_28_REG_START 0x02209000
-#define BCHP_DS_WFE_CZ_28_REG_END 0x02209010
-#define BCHP_DS_WFE_CZ_29_REG_START 0x02209400
-#define BCHP_DS_WFE_CZ_29_REG_END 0x02209410
-#define BCHP_DS_WFE_CZ_30_REG_START 0x02209800
-#define BCHP_DS_WFE_CZ_30_REG_END 0x02209810
-#define BCHP_DS_WFE_CZ_31_REG_START 0x02209c00
-#define BCHP_DS_WFE_CZ_31_REG_END 0x02209c10
-#define BCHP_DS_WFE_CZ_32_REG_START 0x0220a000
-#define BCHP_DS_WFE_CZ_32_REG_END 0x0220a010
-#define BCHP_DS_WFE_CZ_33_REG_START 0x0220a400
-#define BCHP_DS_WFE_CZ_33_REG_END 0x0220a410
-#define BCHP_AIF_WB_DS_CORE_REG_START 0x0220e000
-#define BCHP_AIF_WB_DS_CORE_REG_END 0x0220e21c
-#define BCHP_AIF_WB_DS_ANA_REG_START 0x0220e300
-#define BCHP_AIF_WB_DS_ANA_REG_END 0x0220e39c
-#define BCHP_AIF_MDAC_CAL_CORE_REG_START 0x0220e400
-#define BCHP_AIF_MDAC_CAL_CORE_REG_END 0x0220e4f0
-#define BCHP_OOB_REG_START 0x02220000
-#define BCHP_OOB_REG_END 0x022201f8
-#define BCHP_DS_TOPM_REG_START 0x02222000
-#define BCHP_DS_TOPM_REG_END 0x02222068
-#define BCHP_DS_TOPS_REG_START 0x02223000
-#define BCHP_DS_TOPS_REG_END 0x0222309c
-#define BCHP_DS_REG_START 0x02224000
-#define BCHP_DS_REG_END 0x0222509c
-#define BCHP_DS_1_REG_START 0x02226000
-#define BCHP_DS_1_REG_END 0x0222709c
-#define BCHP_DS_2_REG_START 0x02228000
-#define BCHP_DS_2_REG_END 0x0222909c
-#define BCHP_DS_3_REG_START 0x0222a000
-#define BCHP_DS_3_REG_END 0x0222b09c
-#define BCHP_DS_4_REG_START 0x0222c000
-#define BCHP_DS_4_REG_END 0x0222d09c
-#define BCHP_DS_5_REG_START 0x0222e000
-#define BCHP_DS_5_REG_END 0x0222f09c
-#define BCHP_DS_6_REG_START 0x02230000
-#define BCHP_DS_6_REG_END 0x0223109c
-#define BCHP_DS_7_REG_START 0x02232000
-#define BCHP_DS_7_REG_END 0x0223309c
-#define BCHP_DS_B_TOPM_REG_START 0x02242000
-#define BCHP_DS_B_TOPM_REG_END 0x02242068
-#define BCHP_DS_B_TOPS_REG_START 0x02243000
-#define BCHP_DS_B_TOPS_REG_END 0x0224309c
-#define BCHP_DS_8_REG_START 0x02244000
-#define BCHP_DS_8_REG_END 0x0224509c
-#define BCHP_DS_9_REG_START 0x02246000
-#define BCHP_DS_9_REG_END 0x0224709c
-#define BCHP_DS_10_REG_START 0x02248000
-#define BCHP_DS_10_REG_END 0x0224909c
-#define BCHP_DS_11_REG_START 0x0224a000
-#define BCHP_DS_11_REG_END 0x0224b09c
-#define BCHP_DS_12_REG_START 0x0224c000
-#define BCHP_DS_12_REG_END 0x0224d09c
-#define BCHP_DS_13_REG_START 0x0224e000
-#define BCHP_DS_13_REG_END 0x0224f09c
-#define BCHP_DS_14_REG_START 0x02250000
-#define BCHP_DS_14_REG_END 0x0225109c
-#define BCHP_DS_15_REG_START 0x02252000
-#define BCHP_DS_15_REG_END 0x0225309c
-#define BCHP_DS_C_TOPM_REG_START 0x02262000
-#define BCHP_DS_C_TOPM_REG_END 0x02262068
-#define BCHP_DS_C_TOPS_REG_START 0x02263000
-#define BCHP_DS_C_TOPS_REG_END 0x0226309c
-#define BCHP_DS_16_REG_START 0x02264000
-#define BCHP_DS_16_REG_END 0x0226509c
-#define BCHP_DS_17_REG_START 0x02266000
-#define BCHP_DS_17_REG_END 0x0226709c
-#define BCHP_DS_18_REG_START 0x02268000
-#define BCHP_DS_18_REG_END 0x0226909c
-#define BCHP_DS_19_REG_START 0x0226a000
-#define BCHP_DS_19_REG_END 0x0226b09c
-#define BCHP_DS_20_REG_START 0x0226c000
-#define BCHP_DS_20_REG_END 0x0226d09c
-#define BCHP_DS_21_REG_START 0x0226e000
-#define BCHP_DS_21_REG_END 0x0226f09c
-#define BCHP_DS_22_REG_START 0x02270000
-#define BCHP_DS_22_REG_END 0x0227109c
-#define BCHP_DS_23_REG_START 0x02272000
-#define BCHP_DS_23_REG_END 0x0227309c
-#define BCHP_DS_D_TOPM_REG_START 0x02282000
-#define BCHP_DS_D_TOPM_REG_END 0x02282068
-#define BCHP_DS_D_TOPS_REG_START 0x02283000
-#define BCHP_DS_D_TOPS_REG_END 0x0228309c
-#define BCHP_DS_24_REG_START 0x02284000
-#define BCHP_DS_24_REG_END 0x0228509c
-#define BCHP_DS_25_REG_START 0x02286000
-#define BCHP_DS_25_REG_END 0x0228709c
-#define BCHP_DS_26_REG_START 0x02288000
-#define BCHP_DS_26_REG_END 0x0228909c
-#define BCHP_DS_27_REG_START 0x0228a000
-#define BCHP_DS_27_REG_END 0x0228b09c
-#define BCHP_DS_28_REG_START 0x0228c000
-#define BCHP_DS_28_REG_END 0x0228d09c
-#define BCHP_DS_29_REG_START 0x0228e000
-#define BCHP_DS_29_REG_END 0x0228f09c
-#define BCHP_DS_30_REG_START 0x02290000
-#define BCHP_DS_30_REG_END 0x0229109c
-#define BCHP_DS_31_REG_START 0x02292000
-#define BCHP_DS_31_REG_END 0x0229309c
-#define BCHP_CM_TOP_CTRL_REG_START 0x03800000
-#define BCHP_CM_TOP_CTRL_REG_END 0x03800370
-#define BCHP_CM_AON_CTRL_REG_START 0x03801000
-#define BCHP_CM_AON_CTRL_REG_END 0x03801008
-#define BCHP_RG_TOP_CTRL_REG_START 0x03802000
-#define BCHP_RG_TOP_CTRL_REG_END 0x03802048
-#define BCHP_UART_REG_START 0x03802800
-#define BCHP_UART_REG_END 0x0380281c
-#define BCHP_PROD_OTP_GRB_UB_REG_START 0x03810000
-#define BCHP_PROD_OTP_GRB_UB_REG_END 0x0381000c
-#define BCHP_JTAG_OTP_UB_REG_START 0x03810100
-#define BCHP_JTAG_OTP_UB_REG_END 0x03810158
-#define BCHP_CPU_COMM_REGS_CPUC_REG_START 0x038f0000
-#define BCHP_CPU_COMM_REGS_CPUC_REG_END 0x038f007c
-#define BCHP_MBOX_CPUC_REG_START 0x038f0080
-#define BCHP_MBOX_CPUC_REG_END 0x038f00fc
-#define BCHP_HW_COUNTER_CPUC_REG_START 0x038f0100
-#define BCHP_HW_COUNTER_CPUC_REG_END 0x038f0184
-#define BCHP_BTM_CPUC_REG_START 0x038f0200
-#define BCHP_BTM_CPUC_REG_END 0x038f023c
-#define BCHP_DQM_MDMA_CPUC_REG_START 0x038f0280
-#define BCHP_DQM_MDMA_CPUC_REG_END 0x038f037c
-#define BCHP_DQM_CPUC_REG_START 0x038f0380
-#define BCHP_DQM_CPUC_REG_END 0x038f03f0
-#define BCHP_CPU_COMM_QUEUE_0_CNTRL_CPUC_REG_START 0x038f0400
-#define BCHP_CPU_COMM_QUEUE_0_CNTRL_CPUC_REG_END 0x038f040c
-#define BCHP_CPU_COMM_QUEUE_1_CNTRL_CPUC_REG_START 0x038f0410
-#define BCHP_CPU_COMM_QUEUE_1_CNTRL_CPUC_REG_END 0x038f041c
-#define BCHP_CPU_COMM_QUEUE_2_CNTRL_CPUC_REG_START 0x038f0420
-#define BCHP_CPU_COMM_QUEUE_2_CNTRL_CPUC_REG_END 0x038f042c
-#define BCHP_CPU_COMM_QUEUE_3_CNTRL_CPUC_REG_START 0x038f0430
-#define BCHP_CPU_COMM_QUEUE_3_CNTRL_CPUC_REG_END 0x038f043c
-#define BCHP_CPU_COMM_QUEUE_4_CNTRL_CPUC_REG_START 0x038f0440
-#define BCHP_CPU_COMM_QUEUE_4_CNTRL_CPUC_REG_END 0x038f044c
-#define BCHP_CPU_COMM_QUEUE_5_CNTRL_CPUC_REG_START 0x038f0450
-#define BCHP_CPU_COMM_QUEUE_5_CNTRL_CPUC_REG_END 0x038f045c
-#define BCHP_CPU_COMM_QUEUE_6_CNTRL_CPUC_REG_START 0x038f0460
-#define BCHP_CPU_COMM_QUEUE_6_CNTRL_CPUC_REG_END 0x038f046c
-#define BCHP_CPU_COMM_QUEUE_7_CNTRL_CPUC_REG_START 0x038f0470
-#define BCHP_CPU_COMM_QUEUE_7_CNTRL_CPUC_REG_END 0x038f047c
-#define BCHP_CPU_COMM_QUEUE_8_CNTRL_CPUC_REG_START 0x038f0480
-#define BCHP_CPU_COMM_QUEUE_8_CNTRL_CPUC_REG_END 0x038f048c
-#define BCHP_CPU_COMM_QUEUE_9_CNTRL_CPUC_REG_START 0x038f0490
-#define BCHP_CPU_COMM_QUEUE_9_CNTRL_CPUC_REG_END 0x038f049c
-#define BCHP_CPU_COMM_QUEUE_10_CNTRL_CPUC_REG_START 0x038f04a0
-#define BCHP_CPU_COMM_QUEUE_10_CNTRL_CPUC_REG_END 0x038f04ac
-#define BCHP_CPU_COMM_QUEUE_11_CNTRL_CPUC_REG_START 0x038f04b0
-#define BCHP_CPU_COMM_QUEUE_11_CNTRL_CPUC_REG_END 0x038f04bc
-#define BCHP_CPU_COMM_QUEUE_12_CNTRL_CPUC_REG_START 0x038f04c0
-#define BCHP_CPU_COMM_QUEUE_12_CNTRL_CPUC_REG_END 0x038f04cc
-#define BCHP_CPU_COMM_QUEUE_13_CNTRL_CPUC_REG_START 0x038f04d0
-#define BCHP_CPU_COMM_QUEUE_13_CNTRL_CPUC_REG_END 0x038f04dc
-#define BCHP_CPU_COMM_QUEUE_14_CNTRL_CPUC_REG_START 0x038f04e0
-#define BCHP_CPU_COMM_QUEUE_14_CNTRL_CPUC_REG_END 0x038f04ec
-#define BCHP_CPU_COMM_QUEUE_15_CNTRL_CPUC_REG_START 0x038f04f0
-#define BCHP_CPU_COMM_QUEUE_15_CNTRL_CPUC_REG_END 0x038f04fc
-#define BCHP_CPU_COMM_QUEUE_16_CNTRL_CPUC_REG_START 0x038f0500
-#define BCHP_CPU_COMM_QUEUE_16_CNTRL_CPUC_REG_END 0x038f050c
-#define BCHP_CPU_COMM_QUEUE_17_CNTRL_CPUC_REG_START 0x038f0510
-#define BCHP_CPU_COMM_QUEUE_17_CNTRL_CPUC_REG_END 0x038f051c
-#define BCHP_CPU_COMM_QUEUE_18_CNTRL_CPUC_REG_START 0x038f0520
-#define BCHP_CPU_COMM_QUEUE_18_CNTRL_CPUC_REG_END 0x038f052c
-#define BCHP_CPU_COMM_QUEUE_19_CNTRL_CPUC_REG_START 0x038f0530
-#define BCHP_CPU_COMM_QUEUE_19_CNTRL_CPUC_REG_END 0x038f053c
-#define BCHP_CPU_COMM_QUEUE_20_CNTRL_CPUC_REG_START 0x038f0540
-#define BCHP_CPU_COMM_QUEUE_20_CNTRL_CPUC_REG_END 0x038f054c
-#define BCHP_CPU_COMM_QUEUE_21_CNTRL_CPUC_REG_START 0x038f0550
-#define BCHP_CPU_COMM_QUEUE_21_CNTRL_CPUC_REG_END 0x038f055c
-#define BCHP_CPU_COMM_QUEUE_22_CNTRL_CPUC_REG_START 0x038f0560
-#define BCHP_CPU_COMM_QUEUE_22_CNTRL_CPUC_REG_END 0x038f056c
-#define BCHP_CPU_COMM_QUEUE_23_CNTRL_CPUC_REG_START 0x038f0570
-#define BCHP_CPU_COMM_QUEUE_23_CNTRL_CPUC_REG_END 0x038f057c
-#define BCHP_CPU_COMM_QUEUE_24_CNTRL_CPUC_REG_START 0x038f0580
-#define BCHP_CPU_COMM_QUEUE_24_CNTRL_CPUC_REG_END 0x038f058c
-#define BCHP_CPU_COMM_QUEUE_25_CNTRL_CPUC_REG_START 0x038f0590
-#define BCHP_CPU_COMM_QUEUE_25_CNTRL_CPUC_REG_END 0x038f059c
-#define BCHP_CPU_COMM_QUEUE_26_CNTRL_CPUC_REG_START 0x038f05a0
-#define BCHP_CPU_COMM_QUEUE_26_CNTRL_CPUC_REG_END 0x038f05ac
-#define BCHP_CPU_COMM_QUEUE_27_CNTRL_CPUC_REG_START 0x038f05b0
-#define BCHP_CPU_COMM_QUEUE_27_CNTRL_CPUC_REG_END 0x038f05bc
-#define BCHP_CPU_COMM_QUEUE_28_CNTRL_CPUC_REG_START 0x038f05c0
-#define BCHP_CPU_COMM_QUEUE_28_CNTRL_CPUC_REG_END 0x038f05cc
-#define BCHP_CPU_COMM_QUEUE_29_CNTRL_CPUC_REG_START 0x038f05d0
-#define BCHP_CPU_COMM_QUEUE_29_CNTRL_CPUC_REG_END 0x038f05dc
-#define BCHP_CPU_COMM_QUEUE_30_CNTRL_CPUC_REG_START 0x038f05e0
-#define BCHP_CPU_COMM_QUEUE_30_CNTRL_CPUC_REG_END 0x038f05ec
-#define BCHP_CPU_COMM_QUEUE_31_CNTRL_CPUC_REG_START 0x038f05f0
-#define BCHP_CPU_COMM_QUEUE_31_CNTRL_CPUC_REG_END 0x038f05fc
-#define BCHP_CPU_COMM_QUEUE_0_DATA_CPUC_REG_START 0x038f0800
-#define BCHP_CPU_COMM_QUEUE_0_DATA_CPUC_REG_END 0x038f080c
-#define BCHP_CPU_COMM_QUEUE_1_DATA_CPUC_REG_START 0x038f0810
-#define BCHP_CPU_COMM_QUEUE_1_DATA_CPUC_REG_END 0x038f081c
-#define BCHP_CPU_COMM_QUEUE_2_DATA_CPUC_REG_START 0x038f0820
-#define BCHP_CPU_COMM_QUEUE_2_DATA_CPUC_REG_END 0x038f082c
-#define BCHP_CPU_COMM_QUEUE_3_DATA_CPUC_REG_START 0x038f0830
-#define BCHP_CPU_COMM_QUEUE_3_DATA_CPUC_REG_END 0x038f083c
-#define BCHP_CPU_COMM_QUEUE_4_DATA_CPUC_REG_START 0x038f0840
-#define BCHP_CPU_COMM_QUEUE_4_DATA_CPUC_REG_END 0x038f084c
-#define BCHP_CPU_COMM_QUEUE_5_DATA_CPUC_REG_START 0x038f0850
-#define BCHP_CPU_COMM_QUEUE_5_DATA_CPUC_REG_END 0x038f085c
-#define BCHP_CPU_COMM_QUEUE_6_DATA_CPUC_REG_START 0x038f0860
-#define BCHP_CPU_COMM_QUEUE_6_DATA_CPUC_REG_END 0x038f086c
-#define BCHP_CPU_COMM_QUEUE_7_DATA_CPUC_REG_START 0x038f0870
-#define BCHP_CPU_COMM_QUEUE_7_DATA_CPUC_REG_END 0x038f087c
-#define BCHP_CPU_COMM_QUEUE_8_DATA_CPUC_REG_START 0x038f0880
-#define BCHP_CPU_COMM_QUEUE_8_DATA_CPUC_REG_END 0x038f088c
-#define BCHP_CPU_COMM_QUEUE_9_DATA_CPUC_REG_START 0x038f0890
-#define BCHP_CPU_COMM_QUEUE_9_DATA_CPUC_REG_END 0x038f089c
-#define BCHP_CPU_COMM_QUEUE_10_DATA_CPUC_REG_START 0x038f08a0
-#define BCHP_CPU_COMM_QUEUE_10_DATA_CPUC_REG_END 0x038f08ac
-#define BCHP_CPU_COMM_QUEUE_11_DATA_CPUC_REG_START 0x038f08b0
-#define BCHP_CPU_COMM_QUEUE_11_DATA_CPUC_REG_END 0x038f08bc
-#define BCHP_CPU_COMM_QUEUE_12_DATA_CPUC_REG_START 0x038f08c0
-#define BCHP_CPU_COMM_QUEUE_12_DATA_CPUC_REG_END 0x038f08cc
-#define BCHP_CPU_COMM_QUEUE_13_DATA_CPUC_REG_START 0x038f08d0
-#define BCHP_CPU_COMM_QUEUE_13_DATA_CPUC_REG_END 0x038f08dc
-#define BCHP_CPU_COMM_QUEUE_14_DATA_CPUC_REG_START 0x038f08e0
-#define BCHP_CPU_COMM_QUEUE_14_DATA_CPUC_REG_END 0x038f08ec
-#define BCHP_CPU_COMM_QUEUE_15_DATA_CPUC_REG_START 0x038f08f0
-#define BCHP_CPU_COMM_QUEUE_15_DATA_CPUC_REG_END 0x038f08fc
-#define BCHP_CPU_COMM_QUEUE_16_DATA_CPUC_REG_START 0x038f0900
-#define BCHP_CPU_COMM_QUEUE_16_DATA_CPUC_REG_END 0x038f090c
-#define BCHP_CPU_COMM_QUEUE_17_DATA_CPUC_REG_START 0x038f0910
-#define BCHP_CPU_COMM_QUEUE_17_DATA_CPUC_REG_END 0x038f091c
-#define BCHP_CPU_COMM_QUEUE_18_DATA_CPUC_REG_START 0x038f0920
-#define BCHP_CPU_COMM_QUEUE_18_DATA_CPUC_REG_END 0x038f092c
-#define BCHP_CPU_COMM_QUEUE_19_DATA_CPUC_REG_START 0x038f0930
-#define BCHP_CPU_COMM_QUEUE_19_DATA_CPUC_REG_END 0x038f093c
-#define BCHP_CPU_COMM_QUEUE_20_DATA_CPUC_REG_START 0x038f0940
-#define BCHP_CPU_COMM_QUEUE_20_DATA_CPUC_REG_END 0x038f094c
-#define BCHP_CPU_COMM_QUEUE_21_DATA_CPUC_REG_START 0x038f0950
-#define BCHP_CPU_COMM_QUEUE_21_DATA_CPUC_REG_END 0x038f095c
-#define BCHP_CPU_COMM_QUEUE_22_DATA_CPUC_REG_START 0x038f0960
-#define BCHP_CPU_COMM_QUEUE_22_DATA_CPUC_REG_END 0x038f096c
-#define BCHP_CPU_COMM_QUEUE_23_DATA_CPUC_REG_START 0x038f0970
-#define BCHP_CPU_COMM_QUEUE_23_DATA_CPUC_REG_END 0x038f097c
-#define BCHP_CPU_COMM_QUEUE_24_DATA_CPUC_REG_START 0x038f0980
-#define BCHP_CPU_COMM_QUEUE_24_DATA_CPUC_REG_END 0x038f098c
-#define BCHP_CPU_COMM_QUEUE_25_DATA_CPUC_REG_START 0x038f0990
-#define BCHP_CPU_COMM_QUEUE_25_DATA_CPUC_REG_END 0x038f099c
-#define BCHP_CPU_COMM_QUEUE_26_DATA_CPUC_REG_START 0x038f09a0
-#define BCHP_CPU_COMM_QUEUE_26_DATA_CPUC_REG_END 0x038f09ac
-#define BCHP_CPU_COMM_QUEUE_27_DATA_CPUC_REG_START 0x038f09b0
-#define BCHP_CPU_COMM_QUEUE_27_DATA_CPUC_REG_END 0x038f09bc
-#define BCHP_CPU_COMM_QUEUE_28_DATA_CPUC_REG_START 0x038f09c0
-#define BCHP_CPU_COMM_QUEUE_28_DATA_CPUC_REG_END 0x038f09cc
-#define BCHP_CPU_COMM_QUEUE_29_DATA_CPUC_REG_START 0x038f09d0
-#define BCHP_CPU_COMM_QUEUE_29_DATA_CPUC_REG_END 0x038f09dc
-#define BCHP_CPU_COMM_QUEUE_30_DATA_CPUC_REG_START 0x038f09e0
-#define BCHP_CPU_COMM_QUEUE_30_DATA_CPUC_REG_END 0x038f09ec
-#define BCHP_CPU_COMM_QUEUE_31_DATA_CPUC_REG_START 0x038f09f0
-#define BCHP_CPU_COMM_QUEUE_31_DATA_CPUC_REG_END 0x038f09fc
-#define BCHP_DQMQSTS_CPUC_REG_START 0x038f0b00
-#define BCHP_DQMQSTS_CPUC_REG_END 0x038f0b7c
-#define BCHP_DQMQMIB_CPUC_REG_START 0x038f0c00
-#define BCHP_DQMQMIB_CPUC_REG_END 0x038f0d7c
-#define BCHP_SharedMem_CPUC_REG_START 0x038f4000
-#define BCHP_SharedMem_CPUC_REG_END 0x038f7ffc
-#define BCHP_FPM_CTRL_FPM_REG_START 0x03a00000
-#define BCHP_FPM_CTRL_FPM_REG_END 0x03a00120
-#define BCHP_FPM_POOL_FPM_REG_START 0x03a00200
-#define BCHP_FPM_POOL_FPM_REG_END 0x03a00224
-#define BCHP_FPM_SEARCH_FPM_REG_START 0x03a04000
-#define BCHP_FPM_SEARCH_FPM_REG_END 0x03a048b8
-#define BCHP_FPM_MULTI_FPM_REG_START 0x03a10000
-#define BCHP_FPM_MULTI_FPM_REG_END 0x03a13ff8
-#define BCHP_INT_PER_REG_START 0x03c00000
-#define BCHP_INT_PER_REG_END 0x03c000bc
-#define BCHP_PERIPH_TIMER_PER_REG_START 0x03c000c0
-#define BCHP_PERIPH_TIMER_PER_REG_END 0x03c000ec
-#define BCHP_GPIO_PER_REG_START 0x03c00100
-#define BCHP_GPIO_PER_REG_END 0x03c002ac
-#define BCHP_INT_EXT_PER_REG_START 0x03c00300
-#define BCHP_INT_EXT_PER_REG_END 0x03c00358
-#define BCHP_Dbg_PER_REG_START 0x03c003e0
-#define BCHP_Dbg_PER_REG_END 0x03c003f4
-#define BCHP_PER_SEC_TOP_PER_REG_START 0x03c00400
-#define BCHP_PER_SEC_TOP_PER_REG_END 0x03c00420
-#define BCHP_UART0_PER_REG_START 0x03c00500
-#define BCHP_UART0_PER_REG_END 0x03c00514
-#define BCHP_UART1_PER_REG_START 0x03c00520
-#define BCHP_UART1_PER_REG_END 0x03c00534
-#define BCHP_I2C_DUAL_CORE1_PER_REG_START 0x03c00800
-#define BCHP_I2C_DUAL_CORE1_PER_REG_END 0x03c00854
-#define BCHP_I2C_DUAL_CORE2_PER_REG_START 0x03c00900
-#define BCHP_I2C_DUAL_CORE2_PER_REG_END 0x03c00954
-#define BCHP_LED_PER_REG_START 0x03c00f00
-#define BCHP_LED_PER_REG_END 0x03c00f18
-#define BCHP_GLOBALCNTRL_PER_REG_START 0x03c01000
-#define BCHP_GLOBALCNTRL_PER_REG_END 0x03c01018
-#define BCHP_PINGPONG_0_PER_REG_START 0x03c01080
-#define BCHP_PINGPONG_0_PER_REG_END 0x03c010bc
-#define BCHP_PINGPONG_1_PER_REG_START 0x03c010c0
-#define BCHP_PINGPONG_1_PER_REG_END 0x03c010fc
-#define BCHP_PROFILE_0_PER_REG_START 0x03c01100
-#define BCHP_PROFILE_0_PER_REG_END 0x03c0111c
-#define BCHP_PROFILE_1_PER_REG_START 0x03c01120
-#define BCHP_PROFILE_1_PER_REG_END 0x03c0113c
-#define BCHP_PROFILE_2_PER_REG_START 0x03c01140
-#define BCHP_PROFILE_2_PER_REG_END 0x03c0115c
-#define BCHP_PROFILE_3_PER_REG_START 0x03c01160
-#define BCHP_PROFILE_3_PER_REG_END 0x03c0117c
-#define BCHP_PROFILE_4_PER_REG_START 0x03c01180
-#define BCHP_PROFILE_4_PER_REG_END 0x03c0119c
-#define BCHP_PROFILE_5_PER_REG_START 0x03c011a0
-#define BCHP_PROFILE_5_PER_REG_END 0x03c011bc
-#define BCHP_PROFILE_6_PER_REG_START 0x03c011c0
-#define BCHP_PROFILE_6_PER_REG_END 0x03c011dc
-#define BCHP_PROFILE_7_PER_REG_START 0x03c011e0
-#define BCHP_PROFILE_7_PER_REG_END 0x03c011fc
-#define BCHP_FIFO_0_PER_REG_START 0x03c01200
-#define BCHP_FIFO_0_PER_REG_END 0x03c013ff
-#define BCHP_FIFO_1_PER_REG_START 0x03c01400
-#define BCHP_FIFO_1_PER_REG_END 0x03c015ff
-#define BCHP_PMB_MASTER_PER_REG_START 0x03c03000
-#define BCHP_PMB_MASTER_PER_REG_END 0x03c0300c
-#define BCHP_BPCM_DTP_PER_REG_START 0x03c03100
-#define BCHP_BPCM_DTP_PER_REG_END 0x03c0314c
-#define BCHP_BPCM_DFAP_PER_REG_START 0x03c07100
-#define BCHP_BPCM_DFAP_PER_REG_END 0x03c0714c
-#define BCHP_BPCM_DSMAC_PER_REG_START 0x03c0b100
-#define BCHP_BPCM_DSMAC_PER_REG_END 0x03c0b14c
-#define BCHP_BPCM_UTP_CRYPTO_SEGDMA_PER_REG_START 0x03c0f100
-#define BCHP_BPCM_UTP_CRYPTO_SEGDMA_PER_REG_END 0x03c0f14c
-#define BCHP_BPCM_PERIPH_PER_REG_START 0x03c13100
-#define BCHP_BPCM_PERIPH_PER_REG_END 0x03c1314c
-#define BCHP_BPCM_FPM_PER_REG_START 0x03c17100
-#define BCHP_BPCM_FPM_PER_REG_END 0x03c1714c
-#define BCHP_BPCM_UGB_PER_REG_START 0x03c1b100
-#define BCHP_BPCM_UGB_PER_REG_END 0x03c1b14c
-#define BCHP_BPCM_DECT_PER_REG_START 0x03c1f100
-#define BCHP_BPCM_DECT_PER_REG_END 0x03c1f14c
-#define BCHP_BPCM_APM_TOP_PER_REG_START 0x03c23100
-#define BCHP_BPCM_APM_TOP_PER_REG_END 0x03c2314c
-#define BCHP_BPCM_UNIMAC_MBDMA_PER_REG_START 0x03c27100
-#define BCHP_BPCM_UNIMAC_MBDMA_PER_REG_END 0x03c2714c
-#define BCHP_BPCM_USM_PER_REG_START 0x03c2b100
-#define BCHP_BPCM_USM_PER_REG_END 0x03c2b14c
-#define BCHP_BPCM_TC8X_PER_REG_START 0x03c2f100
-#define BCHP_BPCM_TC8X_PER_REG_END 0x03c2f14c
-#define BCHP_BPCM_DAV_PER_REG_START 0x03c33100
-#define BCHP_BPCM_DAV_PER_REG_END 0x03c3314c
-#define BCHP_BPCM_MIPS_PER_REG_START 0x03c37100
-#define BCHP_BPCM_MIPS_PER_REG_END 0x03c3714c
-#define BCHP_BPCM_DS_WFE_TOP_PER_REG_START 0x03c3b100
-#define BCHP_BPCM_DS_WFE_TOP_PER_REG_END 0x03c3b14c
-#define BCHP_BPCM_DS_TOPA_PER_REG_START 0x03c3f100
-#define BCHP_BPCM_DS_TOPA_PER_REG_END 0x03c3f14c
-#define BCHP_BPCM_DS_TOPB_PER_REG_START 0x03c43100
-#define BCHP_BPCM_DS_TOPB_PER_REG_END 0x03c4314c
-#define BCHP_BPCM_DS_TOPC_PER_REG_START 0x03c47100
-#define BCHP_BPCM_DS_TOPC_PER_REG_END 0x03c4714c
-#define BCHP_BPCM_DS_TOPD_PER_REG_START 0x03c4b100
-#define BCHP_BPCM_DS_TOPD_PER_REG_END 0x03c4b14c
-#define BCHP_BPCM_US_TOP_PER_REG_START 0x03c4f100
-#define BCHP_BPCM_US_TOP_PER_REG_END 0x03c4f14c
-#define BCHP_BPCM_LEAP_TOP_PER_REG_START 0x03c53100
-#define BCHP_BPCM_LEAP_TOP_PER_REG_END 0x03c5314c
-#define BCHP_ERRORPORT_PERIPH_REG_START 0x03e00000
-#define BCHP_ERRORPORT_PERIPH_REG_END 0x03e00034
-#define BCHP_REQA0_PERIPH_REG_START 0x03e08000
-#define BCHP_REQA0_PERIPH_REG_END 0x03e0808c
-#define BCHP_REPA0_PERIPH_REG_START 0x03e08100
-#define BCHP_REPA0_PERIPH_REG_END 0x03e0818c
-#define BCHP_REQA1_PERIPH_REG_START 0x03e09000
-#define BCHP_REQA1_PERIPH_REG_END 0x03e0908c
-#define BCHP_REPA1_PERIPH_REG_START 0x03e09100
-#define BCHP_REPA1_PERIPH_REG_END 0x03e0918c
-#define BCHP_REQB0_PERIPH_REG_START 0x03e0a000
-#define BCHP_REQB0_PERIPH_REG_END 0x03e0a08c
-#define BCHP_REPB0_PERIPH_REG_START 0x03e0a100
-#define BCHP_REPB0_PERIPH_REG_END 0x03e0a18c
-#define BCHP_REQB1_PERIPH_REG_START 0x03e0b000
-#define BCHP_REQB1_PERIPH_REG_END 0x03e0b08c
-#define BCHP_REPB1_PERIPH_REG_START 0x03e0b100
-#define BCHP_REPB1_PERIPH_REG_END 0x03e0b18c
-#define BCHP_REQC0_PERIPH_REG_START 0x03e0c000
-#define BCHP_REQC0_PERIPH_REG_END 0x03e0c08c
-#define BCHP_REPC0_PERIPH_REG_START 0x03e0c100
-#define BCHP_REPC0_PERIPH_REG_END 0x03e0c18c
-#define BCHP_BaseReserved_GFAP_REG_START 0x04600000
-#define BCHP_BaseReserved_GFAP_REG_END 0x04600000
-#define BCHP_Control_GFAP_REG_START 0x04601000
-#define BCHP_Control_GFAP_REG_END 0x046010fc
-#define BCHP_OutgoingMessageFIFO_GFAP_REG_START 0x04601100
-#define BCHP_OutgoingMessageFIFO_GFAP_REG_END 0x0460117c
-#define BCHP_IncomingMessageFIFO_GFAP_REG_START 0x04601200
-#define BCHP_IncomingMessageFIFO_GFAP_REG_END 0x0460127c
-#define BCHP_DMA0_GFAP_REG_START 0x04601300
-#define BCHP_DMA0_GFAP_REG_END 0x0460131c
-#define BCHP_DMA1_GFAP_REG_START 0x04601320
-#define BCHP_DMA1_GFAP_REG_END 0x0460133c
-#define BCHP_DMAHI0_GFAP_REG_START 0x04601340
-#define BCHP_DMAHI0_GFAP_REG_END 0x0460134c
-#define BCHP_DMAHI1_GFAP_REG_START 0x04601350
-#define BCHP_DMAHI1_GFAP_REG_END 0x0460135c
-#define BCHP_Token_GFAP_REG_START 0x04601400
-#define BCHP_Token_GFAP_REG_END 0x0460141c
-#define BCHP_PerfPower_GFAP_REG_START 0x04601600
-#define BCHP_PerfPower_GFAP_REG_END 0x04601640
-#define BCHP_MessageID_GFAP_REG_START 0x04601700
-#define BCHP_MessageID_GFAP_REG_END 0x0460177c
-#define BCHP_DQM_GFAP_REG_START 0x04601800
-#define BCHP_DQM_GFAP_REG_END 0x04601848
-#define BCHP_HWCounters_GFAP_REG_START 0x04601900
-#define BCHP_HWCounters_GFAP_REG_END 0x04601944
-#define BCHP_QUEUE_0_CNTRL_GFAP_REG_START 0x04601a00
-#define BCHP_QUEUE_0_CNTRL_GFAP_REG_END 0x04601a0c
-#define BCHP_QUEUE_1_CNTRL_GFAP_REG_START 0x04601a10
-#define BCHP_QUEUE_1_CNTRL_GFAP_REG_END 0x04601a1c
-#define BCHP_QUEUE_2_CNTRL_GFAP_REG_START 0x04601a20
-#define BCHP_QUEUE_2_CNTRL_GFAP_REG_END 0x04601a2c
-#define BCHP_QUEUE_3_CNTRL_GFAP_REG_START 0x04601a30
-#define BCHP_QUEUE_3_CNTRL_GFAP_REG_END 0x04601a3c
-#define BCHP_QUEUE_4_CNTRL_GFAP_REG_START 0x04601a40
-#define BCHP_QUEUE_4_CNTRL_GFAP_REG_END 0x04601a4c
-#define BCHP_QUEUE_5_CNTRL_GFAP_REG_START 0x04601a50
-#define BCHP_QUEUE_5_CNTRL_GFAP_REG_END 0x04601a5c
-#define BCHP_QUEUE_6_CNTRL_GFAP_REG_START 0x04601a60
-#define BCHP_QUEUE_6_CNTRL_GFAP_REG_END 0x04601a6c
-#define BCHP_QUEUE_7_CNTRL_GFAP_REG_START 0x04601a70
-#define BCHP_QUEUE_7_CNTRL_GFAP_REG_END 0x04601a7c
-#define BCHP_QUEUE_8_CNTRL_GFAP_REG_START 0x04601a80
-#define BCHP_QUEUE_8_CNTRL_GFAP_REG_END 0x04601a8c
-#define BCHP_QUEUE_9_CNTRL_GFAP_REG_START 0x04601a90
-#define BCHP_QUEUE_9_CNTRL_GFAP_REG_END 0x04601a9c
-#define BCHP_QUEUE_10_CNTRL_GFAP_REG_START 0x04601aa0
-#define BCHP_QUEUE_10_CNTRL_GFAP_REG_END 0x04601aac
-#define BCHP_QUEUE_11_CNTRL_GFAP_REG_START 0x04601ab0
-#define BCHP_QUEUE_11_CNTRL_GFAP_REG_END 0x04601abc
-#define BCHP_QUEUE_12_CNTRL_GFAP_REG_START 0x04601ac0
-#define BCHP_QUEUE_12_CNTRL_GFAP_REG_END 0x04601acc
-#define BCHP_QUEUE_13_CNTRL_GFAP_REG_START 0x04601ad0
-#define BCHP_QUEUE_13_CNTRL_GFAP_REG_END 0x04601adc
-#define BCHP_QUEUE_14_CNTRL_GFAP_REG_START 0x04601ae0
-#define BCHP_QUEUE_14_CNTRL_GFAP_REG_END 0x04601aec
-#define BCHP_QUEUE_15_CNTRL_GFAP_REG_START 0x04601af0
-#define BCHP_QUEUE_15_CNTRL_GFAP_REG_END 0x04601afc
-#define BCHP_QUEUE_16_CNTRL_GFAP_REG_START 0x04601b00
-#define BCHP_QUEUE_16_CNTRL_GFAP_REG_END 0x04601b0c
-#define BCHP_QUEUE_17_CNTRL_GFAP_REG_START 0x04601b10
-#define BCHP_QUEUE_17_CNTRL_GFAP_REG_END 0x04601b1c
-#define BCHP_QUEUE_18_CNTRL_GFAP_REG_START 0x04601b20
-#define BCHP_QUEUE_18_CNTRL_GFAP_REG_END 0x04601b2c
-#define BCHP_QUEUE_19_CNTRL_GFAP_REG_START 0x04601b30
-#define BCHP_QUEUE_19_CNTRL_GFAP_REG_END 0x04601b3c
-#define BCHP_QUEUE_20_CNTRL_GFAP_REG_START 0x04601b40
-#define BCHP_QUEUE_20_CNTRL_GFAP_REG_END 0x04601b4c
-#define BCHP_QUEUE_21_CNTRL_GFAP_REG_START 0x04601b50
-#define BCHP_QUEUE_21_CNTRL_GFAP_REG_END 0x04601b5c
-#define BCHP_QUEUE_22_CNTRL_GFAP_REG_START 0x04601b60
-#define BCHP_QUEUE_22_CNTRL_GFAP_REG_END 0x04601b6c
-#define BCHP_QUEUE_23_CNTRL_GFAP_REG_START 0x04601b70
-#define BCHP_QUEUE_23_CNTRL_GFAP_REG_END 0x04601b7c
-#define BCHP_QUEUE_24_CNTRL_GFAP_REG_START 0x04601b80
-#define BCHP_QUEUE_24_CNTRL_GFAP_REG_END 0x04601b8c
-#define BCHP_QUEUE_25_CNTRL_GFAP_REG_START 0x04601b90
-#define BCHP_QUEUE_25_CNTRL_GFAP_REG_END 0x04601b9c
-#define BCHP_QUEUE_26_CNTRL_GFAP_REG_START 0x04601ba0
-#define BCHP_QUEUE_26_CNTRL_GFAP_REG_END 0x04601bac
-#define BCHP_QUEUE_27_CNTRL_GFAP_REG_START 0x04601bb0
-#define BCHP_QUEUE_27_CNTRL_GFAP_REG_END 0x04601bbc
-#define BCHP_QUEUE_28_CNTRL_GFAP_REG_START 0x04601bc0
-#define BCHP_QUEUE_28_CNTRL_GFAP_REG_END 0x04601bcc
-#define BCHP_QUEUE_29_CNTRL_GFAP_REG_START 0x04601bd0
-#define BCHP_QUEUE_29_CNTRL_GFAP_REG_END 0x04601bdc
-#define BCHP_QUEUE_30_CNTRL_GFAP_REG_START 0x04601be0
-#define BCHP_QUEUE_30_CNTRL_GFAP_REG_END 0x04601bec
-#define BCHP_QUEUE_31_CNTRL_GFAP_REG_START 0x04601bf0
-#define BCHP_QUEUE_31_CNTRL_GFAP_REG_END 0x04601bfc
-#define BCHP_QUEUE_0_DATA_GFAP_REG_START 0x04601c00
-#define BCHP_QUEUE_0_DATA_GFAP_REG_END 0x04601c0c
-#define BCHP_QUEUE_1_DATA_GFAP_REG_START 0x04601c10
-#define BCHP_QUEUE_1_DATA_GFAP_REG_END 0x04601c1c
-#define BCHP_QUEUE_2_DATA_GFAP_REG_START 0x04601c20
-#define BCHP_QUEUE_2_DATA_GFAP_REG_END 0x04601c2c
-#define BCHP_QUEUE_3_DATA_GFAP_REG_START 0x04601c30
-#define BCHP_QUEUE_3_DATA_GFAP_REG_END 0x04601c3c
-#define BCHP_QUEUE_4_DATA_GFAP_REG_START 0x04601c40
-#define BCHP_QUEUE_4_DATA_GFAP_REG_END 0x04601c4c
-#define BCHP_QUEUE_5_DATA_GFAP_REG_START 0x04601c50
-#define BCHP_QUEUE_5_DATA_GFAP_REG_END 0x04601c5c
-#define BCHP_QUEUE_6_DATA_GFAP_REG_START 0x04601c60
-#define BCHP_QUEUE_6_DATA_GFAP_REG_END 0x04601c6c
-#define BCHP_QUEUE_7_DATA_GFAP_REG_START 0x04601c70
-#define BCHP_QUEUE_7_DATA_GFAP_REG_END 0x04601c7c
-#define BCHP_QUEUE_8_DATA_GFAP_REG_START 0x04601c80
-#define BCHP_QUEUE_8_DATA_GFAP_REG_END 0x04601c8c
-#define BCHP_QUEUE_9_DATA_GFAP_REG_START 0x04601c90
-#define BCHP_QUEUE_9_DATA_GFAP_REG_END 0x04601c9c
-#define BCHP_QUEUE_10_DATA_GFAP_REG_START 0x04601ca0
-#define BCHP_QUEUE_10_DATA_GFAP_REG_END 0x04601cac
-#define BCHP_QUEUE_11_DATA_GFAP_REG_START 0x04601cb0
-#define BCHP_QUEUE_11_DATA_GFAP_REG_END 0x04601cbc
-#define BCHP_QUEUE_12_DATA_GFAP_REG_START 0x04601cc0
-#define BCHP_QUEUE_12_DATA_GFAP_REG_END 0x04601ccc
-#define BCHP_QUEUE_13_DATA_GFAP_REG_START 0x04601cd0
-#define BCHP_QUEUE_13_DATA_GFAP_REG_END 0x04601cdc
-#define BCHP_QUEUE_14_DATA_GFAP_REG_START 0x04601ce0
-#define BCHP_QUEUE_14_DATA_GFAP_REG_END 0x04601cec
-#define BCHP_QUEUE_15_DATA_GFAP_REG_START 0x04601cf0
-#define BCHP_QUEUE_15_DATA_GFAP_REG_END 0x04601cfc
-#define BCHP_QUEUE_16_DATA_GFAP_REG_START 0x04601d00
-#define BCHP_QUEUE_16_DATA_GFAP_REG_END 0x04601d0c
-#define BCHP_QUEUE_17_DATA_GFAP_REG_START 0x04601d10
-#define BCHP_QUEUE_17_DATA_GFAP_REG_END 0x04601d1c
-#define BCHP_QUEUE_18_DATA_GFAP_REG_START 0x04601d20
-#define BCHP_QUEUE_18_DATA_GFAP_REG_END 0x04601d2c
-#define BCHP_QUEUE_19_DATA_GFAP_REG_START 0x04601d30
-#define BCHP_QUEUE_19_DATA_GFAP_REG_END 0x04601d3c
-#define BCHP_QUEUE_20_DATA_GFAP_REG_START 0x04601d40
-#define BCHP_QUEUE_20_DATA_GFAP_REG_END 0x04601d4c
-#define BCHP_QUEUE_21_DATA_GFAP_REG_START 0x04601d50
-#define BCHP_QUEUE_21_DATA_GFAP_REG_END 0x04601d5c
-#define BCHP_QUEUE_22_DATA_GFAP_REG_START 0x04601d60
-#define BCHP_QUEUE_22_DATA_GFAP_REG_END 0x04601d6c
-#define BCHP_QUEUE_23_DATA_GFAP_REG_START 0x04601d70
-#define BCHP_QUEUE_23_DATA_GFAP_REG_END 0x04601d7c
-#define BCHP_QUEUE_24_DATA_GFAP_REG_START 0x04601d80
-#define BCHP_QUEUE_24_DATA_GFAP_REG_END 0x04601d8c
-#define BCHP_QUEUE_25_DATA_GFAP_REG_START 0x04601d90
-#define BCHP_QUEUE_25_DATA_GFAP_REG_END 0x04601d9c
-#define BCHP_QUEUE_26_DATA_GFAP_REG_START 0x04601da0
-#define BCHP_QUEUE_26_DATA_GFAP_REG_END 0x04601dac
-#define BCHP_QUEUE_27_DATA_GFAP_REG_START 0x04601db0
-#define BCHP_QUEUE_27_DATA_GFAP_REG_END 0x04601dbc
-#define BCHP_QUEUE_28_DATA_GFAP_REG_START 0x04601dc0
-#define BCHP_QUEUE_28_DATA_GFAP_REG_END 0x04601dcc
-#define BCHP_QUEUE_29_DATA_GFAP_REG_START 0x04601dd0
-#define BCHP_QUEUE_29_DATA_GFAP_REG_END 0x04601ddc
-#define BCHP_QUEUE_30_DATA_GFAP_REG_START 0x04601de0
-#define BCHP_QUEUE_30_DATA_GFAP_REG_END 0x04601dec
-#define BCHP_QUEUE_31_DATA_GFAP_REG_START 0x04601df0
-#define BCHP_QUEUE_31_DATA_GFAP_REG_END 0x04601dfc
-#define BCHP_QUEUE_STATUS_GFAP_REG_START 0x04601f00
-#define BCHP_QUEUE_STATUS_GFAP_REG_END 0x04601f7c
-#define BCHP_QUEUE_MIB_GFAP_REG_START 0x04602000
-#define BCHP_QUEUE_MIB_GFAP_REG_END 0x0460217c
-#define BCHP_DQM_64_GFAP_REG_START 0x04602200
-#define BCHP_DQM_64_GFAP_REG_END 0x04602248
-#define BCHP_QUEUE_0_CNTRL_64_GFAP_REG_START 0x04602400
-#define BCHP_QUEUE_0_CNTRL_64_GFAP_REG_END 0x0460240c
-#define BCHP_QUEUE_1_CNTRL_64_GFAP_REG_START 0x04602410
-#define BCHP_QUEUE_1_CNTRL_64_GFAP_REG_END 0x0460241c
-#define BCHP_QUEUE_2_CNTRL_64_GFAP_REG_START 0x04602420
-#define BCHP_QUEUE_2_CNTRL_64_GFAP_REG_END 0x0460242c
-#define BCHP_QUEUE_3_CNTRL_64_GFAP_REG_START 0x04602430
-#define BCHP_QUEUE_3_CNTRL_64_GFAP_REG_END 0x0460243c
-#define BCHP_QUEUE_4_CNTRL_64_GFAP_REG_START 0x04602440
-#define BCHP_QUEUE_4_CNTRL_64_GFAP_REG_END 0x0460244c
-#define BCHP_QUEUE_5_CNTRL_64_GFAP_REG_START 0x04602450
-#define BCHP_QUEUE_5_CNTRL_64_GFAP_REG_END 0x0460245c
-#define BCHP_QUEUE_6_CNTRL_64_GFAP_REG_START 0x04602460
-#define BCHP_QUEUE_6_CNTRL_64_GFAP_REG_END 0x0460246c
-#define BCHP_QUEUE_7_CNTRL_64_GFAP_REG_START 0x04602470
-#define BCHP_QUEUE_7_CNTRL_64_GFAP_REG_END 0x0460247c
-#define BCHP_QUEUE_8_CNTRL_64_GFAP_REG_START 0x04602480
-#define BCHP_QUEUE_8_CNTRL_64_GFAP_REG_END 0x0460248c
-#define BCHP_QUEUE_9_CNTRL_64_GFAP_REG_START 0x04602490
-#define BCHP_QUEUE_9_CNTRL_64_GFAP_REG_END 0x0460249c
-#define BCHP_QUEUE_10_CNTRL_64_GFAP_REG_START 0x046024a0
-#define BCHP_QUEUE_10_CNTRL_64_GFAP_REG_END 0x046024ac
-#define BCHP_QUEUE_11_CNTRL_64_GFAP_REG_START 0x046024b0
-#define BCHP_QUEUE_11_CNTRL_64_GFAP_REG_END 0x046024bc
-#define BCHP_QUEUE_12_CNTRL_64_GFAP_REG_START 0x046024c0
-#define BCHP_QUEUE_12_CNTRL_64_GFAP_REG_END 0x046024cc
-#define BCHP_QUEUE_13_CNTRL_64_GFAP_REG_START 0x046024d0
-#define BCHP_QUEUE_13_CNTRL_64_GFAP_REG_END 0x046024dc
-#define BCHP_QUEUE_14_CNTRL_64_GFAP_REG_START 0x046024e0
-#define BCHP_QUEUE_14_CNTRL_64_GFAP_REG_END 0x046024ec
-#define BCHP_QUEUE_15_CNTRL_64_GFAP_REG_START 0x046024f0
-#define BCHP_QUEUE_15_CNTRL_64_GFAP_REG_END 0x046024fc
-#define BCHP_QUEUE_16_CNTRL_64_GFAP_REG_START 0x04602500
-#define BCHP_QUEUE_16_CNTRL_64_GFAP_REG_END 0x0460250c
-#define BCHP_QUEUE_17_CNTRL_64_GFAP_REG_START 0x04602510
-#define BCHP_QUEUE_17_CNTRL_64_GFAP_REG_END 0x0460251c
-#define BCHP_QUEUE_18_CNTRL_64_GFAP_REG_START 0x04602520
-#define BCHP_QUEUE_18_CNTRL_64_GFAP_REG_END 0x0460252c
-#define BCHP_QUEUE_19_CNTRL_64_GFAP_REG_START 0x04602530
-#define BCHP_QUEUE_19_CNTRL_64_GFAP_REG_END 0x0460253c
-#define BCHP_QUEUE_20_CNTRL_64_GFAP_REG_START 0x04602540
-#define BCHP_QUEUE_20_CNTRL_64_GFAP_REG_END 0x0460254c
-#define BCHP_QUEUE_21_CNTRL_64_GFAP_REG_START 0x04602550
-#define BCHP_QUEUE_21_CNTRL_64_GFAP_REG_END 0x0460255c
-#define BCHP_QUEUE_22_CNTRL_64_GFAP_REG_START 0x04602560
-#define BCHP_QUEUE_22_CNTRL_64_GFAP_REG_END 0x0460256c
-#define BCHP_QUEUE_23_CNTRL_64_GFAP_REG_START 0x04602570
-#define BCHP_QUEUE_23_CNTRL_64_GFAP_REG_END 0x0460257c
-#define BCHP_QUEUE_24_CNTRL_64_GFAP_REG_START 0x04602580
-#define BCHP_QUEUE_24_CNTRL_64_GFAP_REG_END 0x0460258c
-#define BCHP_QUEUE_25_CNTRL_64_GFAP_REG_START 0x04602590
-#define BCHP_QUEUE_25_CNTRL_64_GFAP_REG_END 0x0460259c
-#define BCHP_QUEUE_26_CNTRL_64_GFAP_REG_START 0x046025a0
-#define BCHP_QUEUE_26_CNTRL_64_GFAP_REG_END 0x046025ac
-#define BCHP_QUEUE_27_CNTRL_64_GFAP_REG_START 0x046025b0
-#define BCHP_QUEUE_27_CNTRL_64_GFAP_REG_END 0x046025bc
-#define BCHP_QUEUE_28_CNTRL_64_GFAP_REG_START 0x046025c0
-#define BCHP_QUEUE_28_CNTRL_64_GFAP_REG_END 0x046025cc
-#define BCHP_QUEUE_29_CNTRL_64_GFAP_REG_START 0x046025d0
-#define BCHP_QUEUE_29_CNTRL_64_GFAP_REG_END 0x046025dc
-#define BCHP_QUEUE_30_CNTRL_64_GFAP_REG_START 0x046025e0
-#define BCHP_QUEUE_30_CNTRL_64_GFAP_REG_END 0x046025ec
-#define BCHP_QUEUE_31_CNTRL_64_GFAP_REG_START 0x046025f0
-#define BCHP_QUEUE_31_CNTRL_64_GFAP_REG_END 0x046025fc
-#define BCHP_QUEUE_0_DATA_64_GFAP_REG_START 0x04602600
-#define BCHP_QUEUE_0_DATA_64_GFAP_REG_END 0x0460260c
-#define BCHP_QUEUE_1_DATA_64_GFAP_REG_START 0x04602610
-#define BCHP_QUEUE_1_DATA_64_GFAP_REG_END 0x0460261c
-#define BCHP_QUEUE_2_DATA_64_GFAP_REG_START 0x04602620
-#define BCHP_QUEUE_2_DATA_64_GFAP_REG_END 0x0460262c
-#define BCHP_QUEUE_3_DATA_64_GFAP_REG_START 0x04602630
-#define BCHP_QUEUE_3_DATA_64_GFAP_REG_END 0x0460263c
-#define BCHP_QUEUE_4_DATA_64_GFAP_REG_START 0x04602640
-#define BCHP_QUEUE_4_DATA_64_GFAP_REG_END 0x0460264c
-#define BCHP_QUEUE_5_DATA_64_GFAP_REG_START 0x04602650
-#define BCHP_QUEUE_5_DATA_64_GFAP_REG_END 0x0460265c
-#define BCHP_QUEUE_6_DATA_64_GFAP_REG_START 0x04602660
-#define BCHP_QUEUE_6_DATA_64_GFAP_REG_END 0x0460266c
-#define BCHP_QUEUE_7_DATA_64_GFAP_REG_START 0x04602670
-#define BCHP_QUEUE_7_DATA_64_GFAP_REG_END 0x0460267c
-#define BCHP_QUEUE_8_DATA_64_GFAP_REG_START 0x04602680
-#define BCHP_QUEUE_8_DATA_64_GFAP_REG_END 0x0460268c
-#define BCHP_QUEUE_9_DATA_64_GFAP_REG_START 0x04602690
-#define BCHP_QUEUE_9_DATA_64_GFAP_REG_END 0x0460269c
-#define BCHP_QUEUE_10_DATA_64_GFAP_REG_START 0x046026a0
-#define BCHP_QUEUE_10_DATA_64_GFAP_REG_END 0x046026ac
-#define BCHP_QUEUE_11_DATA_64_GFAP_REG_START 0x046026b0
-#define BCHP_QUEUE_11_DATA_64_GFAP_REG_END 0x046026bc
-#define BCHP_QUEUE_12_DATA_64_GFAP_REG_START 0x046026c0
-#define BCHP_QUEUE_12_DATA_64_GFAP_REG_END 0x046026cc
-#define BCHP_QUEUE_13_DATA_64_GFAP_REG_START 0x046026d0
-#define BCHP_QUEUE_13_DATA_64_GFAP_REG_END 0x046026dc
-#define BCHP_QUEUE_14_DATA_64_GFAP_REG_START 0x046026e0
-#define BCHP_QUEUE_14_DATA_64_GFAP_REG_END 0x046026ec
-#define BCHP_QUEUE_15_DATA_64_GFAP_REG_START 0x046026f0
-#define BCHP_QUEUE_15_DATA_64_GFAP_REG_END 0x046026fc
-#define BCHP_QUEUE_16_DATA_64_GFAP_REG_START 0x04602700
-#define BCHP_QUEUE_16_DATA_64_GFAP_REG_END 0x0460270c
-#define BCHP_QUEUE_17_DATA_64_GFAP_REG_START 0x04602710
-#define BCHP_QUEUE_17_DATA_64_GFAP_REG_END 0x0460271c
-#define BCHP_QUEUE_18_DATA_64_GFAP_REG_START 0x04602720
-#define BCHP_QUEUE_18_DATA_64_GFAP_REG_END 0x0460272c
-#define BCHP_QUEUE_19_DATA_64_GFAP_REG_START 0x04602730
-#define BCHP_QUEUE_19_DATA_64_GFAP_REG_END 0x0460273c
-#define BCHP_QUEUE_20_DATA_64_GFAP_REG_START 0x04602740
-#define BCHP_QUEUE_20_DATA_64_GFAP_REG_END 0x0460274c
-#define BCHP_QUEUE_21_DATA_64_GFAP_REG_START 0x04602750
-#define BCHP_QUEUE_21_DATA_64_GFAP_REG_END 0x0460275c
-#define BCHP_QUEUE_22_DATA_64_GFAP_REG_START 0x04602760
-#define BCHP_QUEUE_22_DATA_64_GFAP_REG_END 0x0460276c
-#define BCHP_QUEUE_23_DATA_64_GFAP_REG_START 0x04602770
-#define BCHP_QUEUE_23_DATA_64_GFAP_REG_END 0x0460277c
-#define BCHP_QUEUE_24_DATA_64_GFAP_REG_START 0x04602780
-#define BCHP_QUEUE_24_DATA_64_GFAP_REG_END 0x0460278c
-#define BCHP_QUEUE_25_DATA_64_GFAP_REG_START 0x04602790
-#define BCHP_QUEUE_25_DATA_64_GFAP_REG_END 0x0460279c
-#define BCHP_QUEUE_26_DATA_64_GFAP_REG_START 0x046027a0
-#define BCHP_QUEUE_26_DATA_64_GFAP_REG_END 0x046027ac
-#define BCHP_QUEUE_27_DATA_64_GFAP_REG_START 0x046027b0
-#define BCHP_QUEUE_27_DATA_64_GFAP_REG_END 0x046027bc
-#define BCHP_QUEUE_28_DATA_64_GFAP_REG_START 0x046027c0
-#define BCHP_QUEUE_28_DATA_64_GFAP_REG_END 0x046027cc
-#define BCHP_QUEUE_29_DATA_64_GFAP_REG_START 0x046027d0
-#define BCHP_QUEUE_29_DATA_64_GFAP_REG_END 0x046027dc
-#define BCHP_QUEUE_30_DATA_64_GFAP_REG_START 0x046027e0
-#define BCHP_QUEUE_30_DATA_64_GFAP_REG_END 0x046027ec
-#define BCHP_QUEUE_31_DATA_64_GFAP_REG_START 0x046027f0
-#define BCHP_QUEUE_31_DATA_64_GFAP_REG_END 0x046027fc
-#define BCHP_QUEUE_STATUS_64_GFAP_REG_START 0x04602900
-#define BCHP_QUEUE_STATUS_64_GFAP_REG_END 0x0460297c
-#define BCHP_QUEUE_MIB_64_GFAP_REG_START 0x04602a00
-#define BCHP_QUEUE_MIB_64_GFAP_REG_END 0x04602b7c
-#define BCHP_QUEUE_TIMER_GFAP_REG_START 0x04602c00
-#define BCHP_QUEUE_TIMER_GFAP_REG_END 0x04602cfc
-#define BCHP_QUEUE_TIMER_64_GFAP_REG_START 0x04602d00
-#define BCHP_QUEUE_TIMER_64_GFAP_REG_END 0x04602dfc
-#define BCHP_OL_QUEUE_0_CNTRL_GFAP_REG_START 0x04603000
-#define BCHP_OL_QUEUE_0_CNTRL_GFAP_REG_END 0x04603010
-#define BCHP_OL_QUEUE_1_CNTRL_GFAP_REG_START 0x04603020
-#define BCHP_OL_QUEUE_1_CNTRL_GFAP_REG_END 0x04603030
-#define BCHP_OL_QUEUE_2_CNTRL_GFAP_REG_START 0x04603040
-#define BCHP_OL_QUEUE_2_CNTRL_GFAP_REG_END 0x04603050
-#define BCHP_OL_QUEUE_3_CNTRL_GFAP_REG_START 0x04603060
-#define BCHP_OL_QUEUE_3_CNTRL_GFAP_REG_END 0x04603070
-#define BCHP_OL_QUEUE_4_CNTRL_GFAP_REG_START 0x04603080
-#define BCHP_OL_QUEUE_4_CNTRL_GFAP_REG_END 0x04603090
-#define BCHP_OL_QUEUE_5_CNTRL_GFAP_REG_START 0x046030a0
-#define BCHP_OL_QUEUE_5_CNTRL_GFAP_REG_END 0x046030b0
-#define BCHP_OL_QUEUE_6_CNTRL_GFAP_REG_START 0x046030c0
-#define BCHP_OL_QUEUE_6_CNTRL_GFAP_REG_END 0x046030d0
-#define BCHP_OL_QUEUE_7_CNTRL_GFAP_REG_START 0x046030e0
-#define BCHP_OL_QUEUE_7_CNTRL_GFAP_REG_END 0x046030f0
-#define BCHP_OL_QUEUE_8_CNTRL_GFAP_REG_START 0x04603100
-#define BCHP_OL_QUEUE_8_CNTRL_GFAP_REG_END 0x04603110
-#define BCHP_OL_QUEUE_9_CNTRL_GFAP_REG_START 0x04603120
-#define BCHP_OL_QUEUE_9_CNTRL_GFAP_REG_END 0x04603130
-#define BCHP_OL_QUEUE_10_CNTRL_GFAP_REG_START 0x04603140
-#define BCHP_OL_QUEUE_10_CNTRL_GFAP_REG_END 0x04603150
-#define BCHP_OL_QUEUE_11_CNTRL_GFAP_REG_START 0x04603160
-#define BCHP_OL_QUEUE_11_CNTRL_GFAP_REG_END 0x04603170
-#define BCHP_OL_QUEUE_12_CNTRL_GFAP_REG_START 0x04603180
-#define BCHP_OL_QUEUE_12_CNTRL_GFAP_REG_END 0x04603190
-#define BCHP_OL_QUEUE_13_CNTRL_GFAP_REG_START 0x046031a0
-#define BCHP_OL_QUEUE_13_CNTRL_GFAP_REG_END 0x046031b0
-#define BCHP_OL_QUEUE_14_CNTRL_GFAP_REG_START 0x046031c0
-#define BCHP_OL_QUEUE_14_CNTRL_GFAP_REG_END 0x046031d0
-#define BCHP_OL_QUEUE_15_CNTRL_GFAP_REG_START 0x046031e0
-#define BCHP_OL_QUEUE_15_CNTRL_GFAP_REG_END 0x046031f0
-#define BCHP_OL_QUEUE_16_CNTRL_GFAP_REG_START 0x04603200
-#define BCHP_OL_QUEUE_16_CNTRL_GFAP_REG_END 0x04603210
-#define BCHP_OL_QUEUE_17_CNTRL_GFAP_REG_START 0x04603220
-#define BCHP_OL_QUEUE_17_CNTRL_GFAP_REG_END 0x04603230
-#define BCHP_OL_QUEUE_18_CNTRL_GFAP_REG_START 0x04603240
-#define BCHP_OL_QUEUE_18_CNTRL_GFAP_REG_END 0x04603250
-#define BCHP_OL_QUEUE_19_CNTRL_GFAP_REG_START 0x04603260
-#define BCHP_OL_QUEUE_19_CNTRL_GFAP_REG_END 0x04603270
-#define BCHP_OL_QUEUE_20_CNTRL_GFAP_REG_START 0x04603280
-#define BCHP_OL_QUEUE_20_CNTRL_GFAP_REG_END 0x04603290
-#define BCHP_OL_QUEUE_21_CNTRL_GFAP_REG_START 0x046032a0
-#define BCHP_OL_QUEUE_21_CNTRL_GFAP_REG_END 0x046032b0
-#define BCHP_OL_QUEUE_22_CNTRL_GFAP_REG_START 0x046032c0
-#define BCHP_OL_QUEUE_22_CNTRL_GFAP_REG_END 0x046032d0
-#define BCHP_OL_QUEUE_23_CNTRL_GFAP_REG_START 0x046032e0
-#define BCHP_OL_QUEUE_23_CNTRL_GFAP_REG_END 0x046032f0
-#define BCHP_OL_QUEUE_24_CNTRL_GFAP_REG_START 0x04603300
-#define BCHP_OL_QUEUE_24_CNTRL_GFAP_REG_END 0x04603310
-#define BCHP_OL_QUEUE_25_CNTRL_GFAP_REG_START 0x04603320
-#define BCHP_OL_QUEUE_25_CNTRL_GFAP_REG_END 0x04603330
-#define BCHP_OL_QUEUE_26_CNTRL_GFAP_REG_START 0x04603340
-#define BCHP_OL_QUEUE_26_CNTRL_GFAP_REG_END 0x04603350
-#define BCHP_OL_QUEUE_27_CNTRL_GFAP_REG_START 0x04603360
-#define BCHP_OL_QUEUE_27_CNTRL_GFAP_REG_END 0x04603370
-#define BCHP_OL_QUEUE_28_CNTRL_GFAP_REG_START 0x04603380
-#define BCHP_OL_QUEUE_28_CNTRL_GFAP_REG_END 0x04603390
-#define BCHP_OL_QUEUE_29_CNTRL_GFAP_REG_START 0x046033a0
-#define BCHP_OL_QUEUE_29_CNTRL_GFAP_REG_END 0x046033b0
-#define BCHP_OL_QUEUE_30_CNTRL_GFAP_REG_START 0x046033c0
-#define BCHP_OL_QUEUE_30_CNTRL_GFAP_REG_END 0x046033d0
-#define BCHP_OL_QUEUE_31_CNTRL_GFAP_REG_START 0x046033e0
-#define BCHP_OL_QUEUE_31_CNTRL_GFAP_REG_END 0x046033f0
-#define BCHP_OL_QUEUE_0_DATA_GFAP_REG_START 0x04603800
-#define BCHP_OL_QUEUE_0_DATA_GFAP_REG_END 0x0460381c
-#define BCHP_OL_QUEUE_1_DATA_GFAP_REG_START 0x04603820
-#define BCHP_OL_QUEUE_1_DATA_GFAP_REG_END 0x0460383c
-#define BCHP_OL_QUEUE_2_DATA_GFAP_REG_START 0x04603840
-#define BCHP_OL_QUEUE_2_DATA_GFAP_REG_END 0x0460385c
-#define BCHP_OL_QUEUE_3_DATA_GFAP_REG_START 0x04603860
-#define BCHP_OL_QUEUE_3_DATA_GFAP_REG_END 0x0460387c
-#define BCHP_OL_QUEUE_4_DATA_GFAP_REG_START 0x04603880
-#define BCHP_OL_QUEUE_4_DATA_GFAP_REG_END 0x0460389c
-#define BCHP_OL_QUEUE_5_DATA_GFAP_REG_START 0x046038a0
-#define BCHP_OL_QUEUE_5_DATA_GFAP_REG_END 0x046038bc
-#define BCHP_OL_QUEUE_6_DATA_GFAP_REG_START 0x046038c0
-#define BCHP_OL_QUEUE_6_DATA_GFAP_REG_END 0x046038dc
-#define BCHP_OL_QUEUE_7_DATA_GFAP_REG_START 0x046038e0
-#define BCHP_OL_QUEUE_7_DATA_GFAP_REG_END 0x046038fc
-#define BCHP_OL_QUEUE_8_DATA_GFAP_REG_START 0x04603900
-#define BCHP_OL_QUEUE_8_DATA_GFAP_REG_END 0x0460391c
-#define BCHP_OL_QUEUE_9_DATA_GFAP_REG_START 0x04603920
-#define BCHP_OL_QUEUE_9_DATA_GFAP_REG_END 0x0460393c
-#define BCHP_OL_QUEUE_10_DATA_GFAP_REG_START 0x04603940
-#define BCHP_OL_QUEUE_10_DATA_GFAP_REG_END 0x0460395c
-#define BCHP_OL_QUEUE_11_DATA_GFAP_REG_START 0x04603960
-#define BCHP_OL_QUEUE_11_DATA_GFAP_REG_END 0x0460397c
-#define BCHP_OL_QUEUE_12_DATA_GFAP_REG_START 0x04603980
-#define BCHP_OL_QUEUE_12_DATA_GFAP_REG_END 0x0460399c
-#define BCHP_OL_QUEUE_13_DATA_GFAP_REG_START 0x046039a0
-#define BCHP_OL_QUEUE_13_DATA_GFAP_REG_END 0x046039bc
-#define BCHP_OL_QUEUE_14_DATA_GFAP_REG_START 0x046039c0
-#define BCHP_OL_QUEUE_14_DATA_GFAP_REG_END 0x046039dc
-#define BCHP_OL_QUEUE_15_DATA_GFAP_REG_START 0x046039e0
-#define BCHP_OL_QUEUE_15_DATA_GFAP_REG_END 0x046039fc
-#define BCHP_OL_QUEUE_16_DATA_GFAP_REG_START 0x04603a00
-#define BCHP_OL_QUEUE_16_DATA_GFAP_REG_END 0x04603a1c
-#define BCHP_OL_QUEUE_17_DATA_GFAP_REG_START 0x04603a20
-#define BCHP_OL_QUEUE_17_DATA_GFAP_REG_END 0x04603a3c
-#define BCHP_OL_QUEUE_18_DATA_GFAP_REG_START 0x04603a40
-#define BCHP_OL_QUEUE_18_DATA_GFAP_REG_END 0x04603a5c
-#define BCHP_OL_QUEUE_19_DATA_GFAP_REG_START 0x04603a60
-#define BCHP_OL_QUEUE_19_DATA_GFAP_REG_END 0x04603a7c
-#define BCHP_OL_QUEUE_20_DATA_GFAP_REG_START 0x04603a80
-#define BCHP_OL_QUEUE_20_DATA_GFAP_REG_END 0x04603a9c
-#define BCHP_OL_QUEUE_21_DATA_GFAP_REG_START 0x04603aa0
-#define BCHP_OL_QUEUE_21_DATA_GFAP_REG_END 0x04603abc
-#define BCHP_OL_QUEUE_22_DATA_GFAP_REG_START 0x04603ac0
-#define BCHP_OL_QUEUE_22_DATA_GFAP_REG_END 0x04603adc
-#define BCHP_OL_QUEUE_23_DATA_GFAP_REG_START 0x04603ae0
-#define BCHP_OL_QUEUE_23_DATA_GFAP_REG_END 0x04603afc
-#define BCHP_OL_QUEUE_24_DATA_GFAP_REG_START 0x04603b00
-#define BCHP_OL_QUEUE_24_DATA_GFAP_REG_END 0x04603b1c
-#define BCHP_OL_QUEUE_25_DATA_GFAP_REG_START 0x04603b20
-#define BCHP_OL_QUEUE_25_DATA_GFAP_REG_END 0x04603b3c
-#define BCHP_OL_QUEUE_26_DATA_GFAP_REG_START 0x04603b40
-#define BCHP_OL_QUEUE_26_DATA_GFAP_REG_END 0x04603b5c
-#define BCHP_OL_QUEUE_27_DATA_GFAP_REG_START 0x04603b60
-#define BCHP_OL_QUEUE_27_DATA_GFAP_REG_END 0x04603b7c
-#define BCHP_OL_QUEUE_28_DATA_GFAP_REG_START 0x04603b80
-#define BCHP_OL_QUEUE_28_DATA_GFAP_REG_END 0x04603b9c
-#define BCHP_OL_QUEUE_29_DATA_GFAP_REG_START 0x04603ba0
-#define BCHP_OL_QUEUE_29_DATA_GFAP_REG_END 0x04603bbc
-#define BCHP_OL_QUEUE_30_DATA_GFAP_REG_START 0x04603bc0
-#define BCHP_OL_QUEUE_30_DATA_GFAP_REG_END 0x04603bdc
-#define BCHP_OL_QUEUE_31_DATA_GFAP_REG_START 0x04603be0
-#define BCHP_OL_QUEUE_31_DATA_GFAP_REG_END 0x04603bfc
-#define BCHP_SharedMem_GFAP_REG_START 0x04604000
-#define BCHP_SharedMem_GFAP_REG_END 0x0460fffc
-#define BCHP_Memory_GFAP_REG_START 0x04610000
-#define BCHP_Memory_GFAP_REG_END 0x04617ffc
-#define BCHP_DPE_BASIC_GFAP_REG_START 0x04700000
-#define BCHP_DPE_BASIC_GFAP_REG_END 0x04700094
-#define BCHP_DPE_MPEG_GFAP_REG_START 0x04700200
-#define BCHP_DPE_MPEG_GFAP_REG_END 0x0470034c
-#define BCHP_DPE_HW_GFAP_REG_START 0x04700400
-#define BCHP_DPE_HW_GFAP_REG_END 0x04700f3c
-#define BCHP_NATC_REG_GFAP_REG_START 0x04701000
-#define BCHP_NATC_REG_GFAP_REG_END 0x04701164
-#define BCHP_NATC_SMEM_GFAP_REG_START 0x04707000
-#define BCHP_NATC_SMEM_GFAP_REG_END 0x04707ffc
-#define BCHP_NATC_MEM_GFAP_REG_START 0x04708000
-#define BCHP_NATC_MEM_GFAP_REG_END 0x0470fffc
-#define BCHP_FFE_N_0_GFAP_REG_START 0x04750000
-#define BCHP_FFE_N_0_GFAP_REG_END 0x047503fc
-#define BCHP_FFE_P_0_GFAP_REG_START 0x04751000
-#define BCHP_FFE_P_0_GFAP_REG_END 0x047517fc
-#define BCHP_FFE_I_0_GFAP_REG_START 0x04754000
-#define BCHP_FFE_I_0_GFAP_REG_END 0x04757ffc
-#define BCHP_FFE_N_1_GFAP_REG_START 0x04770000
-#define BCHP_FFE_N_1_GFAP_REG_END 0x047703fc
-#define BCHP_FFE_P_1_GFAP_REG_START 0x04771000
-#define BCHP_FFE_P_1_GFAP_REG_END 0x047717fc
-#define BCHP_FFE_I_1_GFAP_REG_START 0x04774000
-#define BCHP_FFE_I_1_GFAP_REG_END 0x04777ffc
-#define BCHP_FFE_N_2_GFAP_REG_START 0x04790000
-#define BCHP_FFE_N_2_GFAP_REG_END 0x047903fc
-#define BCHP_FFE_P_2_GFAP_REG_START 0x04791000
-#define BCHP_FFE_P_2_GFAP_REG_END 0x047917fc
-#define BCHP_FFE_I_2_GFAP_REG_START 0x04794000
-#define BCHP_FFE_I_2_GFAP_REG_END 0x04797ffc
-#define BCHP_FFE_N_3_GFAP_REG_START 0x047b0000
-#define BCHP_FFE_N_3_GFAP_REG_END 0x047b03fc
-#define BCHP_FFE_P_3_GFAP_REG_START 0x047b1000
-#define BCHP_FFE_P_3_GFAP_REG_END 0x047b17fc
-#define BCHP_FFE_I_3_GFAP_REG_START 0x047b4000
-#define BCHP_FFE_I_3_GFAP_REG_END 0x047b7ffc
-#define BCHP_MBDMA_UNI1_REG_START 0x04800000
-#define BCHP_MBDMA_UNI1_REG_END 0x04800508
-#define BCHP_UNIMAC_INTERFACE0_UNI1_REG_START 0x04800600
-#define BCHP_UNIMAC_INTERFACE0_UNI1_REG_END 0x04800710
-#define BCHP_UNIMAC_CORE0_UNI1_REG_START 0x04800800
-#define BCHP_UNIMAC_CORE0_UNI1_REG_END 0x04800b64
-#define BCHP_MIB0_UNI1_REG_START 0x04800c00
-#define BCHP_MIB0_UNI1_REG_END 0x04800cf4
-#define BCHP_HFB0_UNI1_REG_START 0x04801000
-#define BCHP_HFB0_UNI1_REG_END 0x04801ffc
-#define BCHP_MBDMA_UNI0_REG_START 0x04a00000
-#define BCHP_MBDMA_UNI0_REG_END 0x04a00508
-#define BCHP_UNIMAC_INTERFACE0_UNI0_REG_START 0x04a00600
-#define BCHP_UNIMAC_INTERFACE0_UNI0_REG_END 0x04a00710
-#define BCHP_UNIMAC_CORE0_UNI0_REG_START 0x04a00800
-#define BCHP_UNIMAC_CORE0_UNI0_REG_END 0x04a00b64
-#define BCHP_MIB0_UNI0_REG_START 0x04a00c00
-#define BCHP_MIB0_UNI0_REG_END 0x04a00cf4
-#define BCHP_HFB0_UNI0_REG_START 0x04a01000
-#define BCHP_HFB0_UNI0_REG_END 0x04a01ffc
-#define BCHP_MBDMA_UNI2_REG_START 0x04c00000
-#define BCHP_MBDMA_UNI2_REG_END 0x04c00508
-#define BCHP_UNIMAC_INTERFACE0_UNI2_REG_START 0x04c00600
-#define BCHP_UNIMAC_INTERFACE0_UNI2_REG_END 0x04c00710
-#define BCHP_UNIMAC_CORE0_UNI2_REG_START 0x04c00800
-#define BCHP_UNIMAC_CORE0_UNI2_REG_END 0x04c00b64
-#define BCHP_MIB0_UNI2_REG_START 0x04c00c00
-#define BCHP_MIB0_UNI2_REG_END 0x04c00cf4
-#define BCHP_HFB0_UNI2_REG_START 0x04c01000
-#define BCHP_HFB0_UNI2_REG_END 0x04c01ffc
-#define BCHP_SWITCH_CORE_REG_START 0x04e00000
-#define BCHP_SWITCH_CORE_REG_END 0x04e3fffc
-#define BCHP_SWITCH_REG_REG_START 0x04e40000
-#define BCHP_SWITCH_REG_REG_END 0x04e400b8
-#define BCHP_SWITCH_INDIR_RW_REG_START 0x04e40300
-#define BCHP_SWITCH_INDIR_RW_REG_END 0x04e40314
-#define BCHP_SWITCH_INTRL2_0_REG_START 0x04e40340
-#define BCHP_SWITCH_INTRL2_0_REG_END 0x04e4036c
-#define BCHP_SWITCH_INTRL2_1_REG_START 0x04e40380
-#define BCHP_SWITCH_INTRL2_1_REG_END 0x04e403ac
-#define BCHP_SWITCH_MDIO_REG_START 0x04e403c0
-#define BCHP_SWITCH_MDIO_REG_END 0x04e403c4
-#define BCHP_SWITCH_FCB_REG_START 0x04e40400
-#define BCHP_SWITCH_FCB_REG_END 0x04e4042c
-#define BCHP_SWITCH_ACB_REG_START 0x04e40600
-#define BCHP_SWITCH_ACB_REG_END 0x04e40704
-#define BCHP_PCIE_0_RC_CFG_TYPE1_REG_START 0x07800000
-#define BCHP_PCIE_0_RC_CFG_TYPE1_REG_END 0x0780003c
-#define BCHP_PCIE_0_RC_CFG_PM_REG_START 0x07800048
-#define BCHP_PCIE_0_RC_CFG_PM_REG_END 0x0780004c
-#define BCHP_PCIE_0_RC_CFG_PCIE_REG_START 0x078000ac
-#define BCHP_PCIE_0_RC_CFG_PCIE_REG_END 0x078000e4
-#define BCHP_PCIE_0_RC_CFG_AER_REG_START 0x07800100
-#define BCHP_PCIE_0_RC_CFG_AER_REG_END 0x07800134
-#define BCHP_PCIE_0_RC_CFG_VC_REG_START 0x07800160
-#define BCHP_PCIE_0_RC_CFG_VC_REG_END 0x07800178
-#define BCHP_PCIE_0_RC_CFG_VENDOR_REG_START 0x07800180
-#define BCHP_PCIE_0_RC_CFG_VENDOR_REG_END 0x078001a4
-#define BCHP_PCIE_0_RC_CFG_PRIV0_REG_START 0x07800404
-#define BCHP_PCIE_0_RC_CFG_PRIV0_REG_END 0x07800418
-#define BCHP_PCIE_0_RC_CFG_PRIV1_REG_START 0x07800428
-#define BCHP_PCIE_0_RC_CFG_PRIV1_REG_END 0x07800630
-#define BCHP_PCIE_0_RC_TL_REG_START 0x07800800
-#define BCHP_PCIE_0_RC_TL_REG_END 0x07800998
-#define BCHP_PCIE_0_RC_DL_REG_START 0x07801000
-#define BCHP_PCIE_0_RC_DL_REG_END 0x07801424
-#define BCHP_PCIE_0_RC_PL_REG_START 0x07801800
-#define BCHP_PCIE_0_RC_PL_REG_END 0x07801e1c
-#define BCHP_PCIE_0_EP_CFG_TYPE0_REG_START 0x07802000
-#define BCHP_PCIE_0_EP_CFG_TYPE0_REG_END 0x0780203c
-#define BCHP_PCIE_0_EP_CFG_PM_REG_START 0x07802048
-#define BCHP_PCIE_0_EP_CFG_PM_REG_END 0x0780204c
-#define BCHP_PCIE_0_EP_CFG_VPD_REG_START 0x07802050
-#define BCHP_PCIE_0_EP_CFG_VPD_REG_END 0x07802054
-#define BCHP_PCIE_0_EP_CFG_MSI_REG_START 0x07802058
-#define BCHP_PCIE_0_EP_CFG_MSI_REG_END 0x07802064
-#define BCHP_PCIE_0_EP_CFG_MSIX_REG_START 0x078020a0
-#define BCHP_PCIE_0_EP_CFG_MSIX_REG_END 0x078020a8
-#define BCHP_PCIE_0_EP_CFG_PCIE_REG_START 0x078020ac
-#define BCHP_PCIE_0_EP_CFG_PCIE_REG_END 0x078020e4
-#define BCHP_PCIE_0_EP_CFG_AER_REG_START 0x07802100
-#define BCHP_PCIE_0_EP_CFG_AER_REG_END 0x07802134
-#define BCHP_PCIE_0_EP_CFG_DEV_REG_START 0x0780213c
-#define BCHP_PCIE_0_EP_CFG_DEV_REG_END 0x07802144
-#define BCHP_PCIE_0_EP_CFG_PB_REG_START 0x07802150
-#define BCHP_PCIE_0_EP_CFG_PB_REG_END 0x0780215c
-#define BCHP_PCIE_0_EP_CFG_VC_REG_START 0x07802160
-#define BCHP_PCIE_0_EP_CFG_VC_REG_END 0x07802178
-#define BCHP_PCIE_0_EP_CFG_VENDOR_REG_START 0x07802180
-#define BCHP_PCIE_0_EP_CFG_VENDOR_REG_END 0x078021a4
-#define BCHP_PCIE_0_EP_CFG_PRIV0_REG_START 0x07802404
-#define BCHP_PCIE_0_EP_CFG_PRIV0_REG_END 0x07802418
-#define BCHP_PCIE_0_EP_CFG_PRIV1_REG_START 0x07802428
-#define BCHP_PCIE_0_EP_CFG_PRIV1_REG_END 0x07802630
-#define BCHP_PCIE_0_EP_TL_REG_START 0x07802800
-#define BCHP_PCIE_0_EP_TL_REG_END 0x07802998
-#define BCHP_PCIE_0_EP_DL_REG_START 0x07803000
-#define BCHP_PCIE_0_EP_DL_REG_END 0x07803424
-#define BCHP_PCIE_0_EP_PL_REG_START 0x07803800
-#define BCHP_PCIE_0_EP_PL_REG_END 0x07803e1c
-#define BCHP_PCIE_0_MISC_REG_START 0x07804000
-#define BCHP_PCIE_0_MISC_REG_END 0x078040c4
-#define BCHP_PCIE_0_MISC_PERST_REG_START 0x07804100
-#define BCHP_PCIE_0_MISC_PERST_REG_END 0x07804104
-#define BCHP_PCIE_0_MISC_HARD_REG_START 0x07804200
-#define BCHP_PCIE_0_MISC_HARD_REG_END 0x07804204
-#define BCHP_PCIE_0_INTR2_REG_START 0x07804300
-#define BCHP_PCIE_0_INTR2_REG_END 0x0780432c
-#define BCHP_PCIE_0_DMA_REG_START 0x07804400
-#define BCHP_PCIE_0_DMA_REG_END 0x0780446c
-#define BCHP_PCIE_0_EXT_CFG_REG_START 0x07808000
-#define BCHP_PCIE_0_EXT_CFG_REG_END 0x07809008
-#define BCHP_PCIE_0_RGR1_REG_START 0x07809200
-#define BCHP_PCIE_0_RGR1_REG_END 0x07809210
-#define BCHP_PCIE_0_RG_REG_START 0x07809300
-#define BCHP_PCIE_0_RG_REG_END 0x0780930c
-#define BCHP_PCIE_1_RC_CFG_TYPE1_REG_START 0x07a00000
-#define BCHP_PCIE_1_RC_CFG_TYPE1_REG_END 0x07a0003c
-#define BCHP_PCIE_1_RC_CFG_PM_REG_START 0x07a00048
-#define BCHP_PCIE_1_RC_CFG_PM_REG_END 0x07a0004c
-#define BCHP_PCIE_1_RC_CFG_PCIE_REG_START 0x07a000ac
-#define BCHP_PCIE_1_RC_CFG_PCIE_REG_END 0x07a000e4
-#define BCHP_PCIE_1_RC_CFG_AER_REG_START 0x07a00100
-#define BCHP_PCIE_1_RC_CFG_AER_REG_END 0x07a00134
-#define BCHP_PCIE_1_RC_CFG_VC_REG_START 0x07a00160
-#define BCHP_PCIE_1_RC_CFG_VC_REG_END 0x07a00178
-#define BCHP_PCIE_1_RC_CFG_VENDOR_REG_START 0x07a00180
-#define BCHP_PCIE_1_RC_CFG_VENDOR_REG_END 0x07a001a4
-#define BCHP_PCIE_1_RC_CFG_PRIV0_REG_START 0x07a00404
-#define BCHP_PCIE_1_RC_CFG_PRIV0_REG_END 0x07a00418
-#define BCHP_PCIE_1_RC_CFG_PRIV1_REG_START 0x07a00428
-#define BCHP_PCIE_1_RC_CFG_PRIV1_REG_END 0x07a00630
-#define BCHP_PCIE_1_RC_TL_REG_START 0x07a00800
-#define BCHP_PCIE_1_RC_TL_REG_END 0x07a00998
-#define BCHP_PCIE_1_RC_DL_REG_START 0x07a01000
-#define BCHP_PCIE_1_RC_DL_REG_END 0x07a01424
-#define BCHP_PCIE_1_RC_PL_REG_START 0x07a01800
-#define BCHP_PCIE_1_RC_PL_REG_END 0x07a01e1c
-#define BCHP_PCIE_1_EP_CFG_TYPE0_REG_START 0x07a02000
-#define BCHP_PCIE_1_EP_CFG_TYPE0_REG_END 0x07a0203c
-#define BCHP_PCIE_1_EP_CFG_PM_REG_START 0x07a02048
-#define BCHP_PCIE_1_EP_CFG_PM_REG_END 0x07a0204c
-#define BCHP_PCIE_1_EP_CFG_VPD_REG_START 0x07a02050
-#define BCHP_PCIE_1_EP_CFG_VPD_REG_END 0x07a02054
-#define BCHP_PCIE_1_EP_CFG_MSI_REG_START 0x07a02058
-#define BCHP_PCIE_1_EP_CFG_MSI_REG_END 0x07a02064
-#define BCHP_PCIE_1_EP_CFG_MSIX_REG_START 0x07a020a0
-#define BCHP_PCIE_1_EP_CFG_MSIX_REG_END 0x07a020a8
-#define BCHP_PCIE_1_EP_CFG_PCIE_REG_START 0x07a020ac
-#define BCHP_PCIE_1_EP_CFG_PCIE_REG_END 0x07a020e4
-#define BCHP_PCIE_1_EP_CFG_AER_REG_START 0x07a02100
-#define BCHP_PCIE_1_EP_CFG_AER_REG_END 0x07a02134
-#define BCHP_PCIE_1_EP_CFG_DEV_REG_START 0x07a0213c
-#define BCHP_PCIE_1_EP_CFG_DEV_REG_END 0x07a02144
-#define BCHP_PCIE_1_EP_CFG_PB_REG_START 0x07a02150
-#define BCHP_PCIE_1_EP_CFG_PB_REG_END 0x07a0215c
-#define BCHP_PCIE_1_EP_CFG_VC_REG_START 0x07a02160
-#define BCHP_PCIE_1_EP_CFG_VC_REG_END 0x07a02178
-#define BCHP_PCIE_1_EP_CFG_VENDOR_REG_START 0x07a02180
-#define BCHP_PCIE_1_EP_CFG_VENDOR_REG_END 0x07a021a4
-#define BCHP_PCIE_1_EP_CFG_PRIV0_REG_START 0x07a02404
-#define BCHP_PCIE_1_EP_CFG_PRIV0_REG_END 0x07a02418
-#define BCHP_PCIE_1_EP_CFG_PRIV1_REG_START 0x07a02428
-#define BCHP_PCIE_1_EP_CFG_PRIV1_REG_END 0x07a02630
-#define BCHP_PCIE_1_EP_TL_REG_START 0x07a02800
-#define BCHP_PCIE_1_EP_TL_REG_END 0x07a02998
-#define BCHP_PCIE_1_EP_DL_REG_START 0x07a03000
-#define BCHP_PCIE_1_EP_DL_REG_END 0x07a03424
-#define BCHP_PCIE_1_EP_PL_REG_START 0x07a03800
-#define BCHP_PCIE_1_EP_PL_REG_END 0x07a03e1c
-#define BCHP_PCIE_1_MISC_REG_START 0x07a04000
-#define BCHP_PCIE_1_MISC_REG_END 0x07a040c4
-#define BCHP_PCIE_1_MISC_PERST_REG_START 0x07a04100
-#define BCHP_PCIE_1_MISC_PERST_REG_END 0x07a04104
-#define BCHP_PCIE_1_MISC_HARD_REG_START 0x07a04200
-#define BCHP_PCIE_1_MISC_HARD_REG_END 0x07a04204
-#define BCHP_PCIE_1_INTR2_REG_START 0x07a04300
-#define BCHP_PCIE_1_INTR2_REG_END 0x07a0432c
-#define BCHP_PCIE_1_DMA_REG_START 0x07a04400
-#define BCHP_PCIE_1_DMA_REG_END 0x07a0446c
-#define BCHP_PCIE_1_EXT_CFG_REG_START 0x07a08000
-#define BCHP_PCIE_1_EXT_CFG_REG_END 0x07a09008
-#define BCHP_PCIE_1_RGR1_REG_START 0x07a09200
-#define BCHP_PCIE_1_RGR1_REG_END 0x07a09210
-#define BCHP_PCIE_1_RG_REG_START 0x07a09300
-#define BCHP_PCIE_1_RG_REG_END 0x07a0930c
-#define BCHP_DATA_MEM_REG_START 0x07c00000
-#define BCHP_DATA_MEM_REG_END 0x07c47ffc
-#define BCHP_CNTL_MEM_REG_START 0x07d20000
-#define BCHP_CNTL_MEM_REG_END 0x07d67ffc
-#define BCHP_DMA_AHB_ECL_CMD_SCH0_REG_START 0x07dc0000
-#define BCHP_DMA_AHB_ECL_CMD_SCH0_REG_END 0x07dc0000
-#define BCHP_DMA_AHB_ECL_CMD_SCH1_REG_START 0x07dc0010
-#define BCHP_DMA_AHB_ECL_CMD_SCH1_REG_END 0x07dc0010
-#define BCHP_DMA_AHB_ECL_CMD_SCH2_REG_START 0x07dc0020
-#define BCHP_DMA_AHB_ECL_CMD_SCH2_REG_END 0x07dc0020
-#define BCHP_DMA_AHB_ECL_CMD_SCH3_REG_START 0x07dc0030
-#define BCHP_DMA_AHB_ECL_CMD_SCH3_REG_END 0x07dc0030
-#define BCHP_DMA_AHB_ECL_CMD_SCH4_REG_START 0x07dc0040
-#define BCHP_DMA_AHB_ECL_CMD_SCH4_REG_END 0x07dc0040
-#define BCHP_DMA_AHB_ECL_CMD_SCH5_REG_START 0x07dc0050
-#define BCHP_DMA_AHB_ECL_CMD_SCH5_REG_END 0x07dc0050
-#define BCHP_DMA_AHB_ECL_CMD_SCH6_REG_START 0x07dc0060
-#define BCHP_DMA_AHB_ECL_CMD_SCH6_REG_END 0x07dc0060
-#define BCHP_DMA_AHB_ECL_CMD_SCH7_REG_START 0x07dc0070
-#define BCHP_DMA_AHB_ECL_CMD_SCH7_REG_END 0x07dc0070
-#define BCHP_DMA_AHB_ECL_CMD_SCH8_REG_START 0x07dc0080
-#define BCHP_DMA_AHB_ECL_CMD_SCH8_REG_END 0x07dc0080
-#define BCHP_DMA_AHB_ECL_CMD_SCH9_REG_START 0x07dc0090
-#define BCHP_DMA_AHB_ECL_CMD_SCH9_REG_END 0x07dc0090
-#define BCHP_DMA_AHB_ECL_CMD_SCH10_REG_START 0x07dc00a0
-#define BCHP_DMA_AHB_ECL_CMD_SCH10_REG_END 0x07dc00a0
-#define BCHP_DMA_AHB_ECL_CMD_SCH11_REG_START 0x07dc00b0
-#define BCHP_DMA_AHB_ECL_CMD_SCH11_REG_END 0x07dc00b0
-#define BCHP_DMA_AHB_ECL_CMD_SCH12_REG_START 0x07dc00c0
-#define BCHP_DMA_AHB_ECL_CMD_SCH12_REG_END 0x07dc00c0
-#define BCHP_DMA_AHB_ECL_CMD_SCH13_REG_START 0x07dc00d0
-#define BCHP_DMA_AHB_ECL_CMD_SCH13_REG_END 0x07dc00d0
-#define BCHP_DMA_AHB_ECL_CMD_SCH14_REG_START 0x07dc00e0
-#define BCHP_DMA_AHB_ECL_CMD_SCH14_REG_END 0x07dc00e0
-#define BCHP_DMA_AHB_ECL_CMD_SCH15_REG_START 0x07dc00f0
-#define BCHP_DMA_AHB_ECL_CMD_SCH15_REG_END 0x07dc00f0
-#define BCHP_DMA_AHB_ECL_CMD_SCH16_REG_START 0x07dc0100
-#define BCHP_DMA_AHB_ECL_CMD_SCH16_REG_END 0x07dc0100
-#define BCHP_DMA_AHB_ECL_CMD_SCH17_REG_START 0x07dc0110
-#define BCHP_DMA_AHB_ECL_CMD_SCH17_REG_END 0x07dc0110
-#define BCHP_DMA_AHB_ECL_CMD_SCH18_REG_START 0x07dc0120
-#define BCHP_DMA_AHB_ECL_CMD_SCH18_REG_END 0x07dc0120
-#define BCHP_DMA_AHB_ECL_CMD_SCH19_REG_START 0x07dc0130
-#define BCHP_DMA_AHB_ECL_CMD_SCH19_REG_END 0x07dc0130
-#define BCHP_DMA_AHB_ECL_CMD_RX_REG_START 0x07dc0800
-#define BCHP_DMA_AHB_ECL_CMD_RX_REG_END 0x07dc0800
-#define BCHP_DMA_AHB_CMD_RX_SCH0_REG_START 0x07dc4000
-#define BCHP_DMA_AHB_CMD_RX_SCH0_REG_END 0x07dc4000
-#define BCHP_DMA_AHB_CMD_RX_SCH1_REG_START 0x07dc4010
-#define BCHP_DMA_AHB_CMD_RX_SCH1_REG_END 0x07dc4010
-#define BCHP_DMA_AHB_CMD_RX_SCH2_REG_START 0x07dc4020
-#define BCHP_DMA_AHB_CMD_RX_SCH2_REG_END 0x07dc4020
-#define BCHP_DMA_AHB_CMD_RX_SCH3_REG_START 0x07dc4030
-#define BCHP_DMA_AHB_CMD_RX_SCH3_REG_END 0x07dc4030
-#define BCHP_DMA_AHB_CMD_RX_SCH4_REG_START 0x07dc4040
-#define BCHP_DMA_AHB_CMD_RX_SCH4_REG_END 0x07dc4040
-#define BCHP_DMA_AHB_CMD_RX_SCH5_REG_START 0x07dc4050
-#define BCHP_DMA_AHB_CMD_RX_SCH5_REG_END 0x07dc4050
-#define BCHP_DMA_AHB_CMD_RX_SCH6_REG_START 0x07dc4060
-#define BCHP_DMA_AHB_CMD_RX_SCH6_REG_END 0x07dc4060
-#define BCHP_DMA_AHB_CMD_RX_SCH7_REG_START 0x07dc4070
-#define BCHP_DMA_AHB_CMD_RX_SCH7_REG_END 0x07dc4070
-#define BCHP_DMA_AHB_CMD_RX_SCH8_REG_START 0x07dc4080
-#define BCHP_DMA_AHB_CMD_RX_SCH8_REG_END 0x07dc4080
-#define BCHP_DMA_AHB_CMD_RX_SCH9_REG_START 0x07dc4090
-#define BCHP_DMA_AHB_CMD_RX_SCH9_REG_END 0x07dc4090
-#define BCHP_DMA_AHB_CMD_RX_SCH10_REG_START 0x07dc40a0
-#define BCHP_DMA_AHB_CMD_RX_SCH10_REG_END 0x07dc40a0
-#define BCHP_DMA_AHB_CMD_RX_SCH11_REG_START 0x07dc40b0
-#define BCHP_DMA_AHB_CMD_RX_SCH11_REG_END 0x07dc40b0
-#define BCHP_DMA_AHB_CMD_RX_SCH12_REG_START 0x07dc40c0
-#define BCHP_DMA_AHB_CMD_RX_SCH12_REG_END 0x07dc40c0
-#define BCHP_DMA_AHB_CMD_RX_SCH13_REG_START 0x07dc40d0
-#define BCHP_DMA_AHB_CMD_RX_SCH13_REG_END 0x07dc40d0
-#define BCHP_DMA_AHB_CMD_RX_SCH14_REG_START 0x07dc40e0
-#define BCHP_DMA_AHB_CMD_RX_SCH14_REG_END 0x07dc40e0
-#define BCHP_DMA_AHB_CMD_RX_SCH15_REG_START 0x07dc40f0
-#define BCHP_DMA_AHB_CMD_RX_SCH15_REG_END 0x07dc40f0
-#define BCHP_DMA_AHB_CMD_RX_SCH16_REG_START 0x07dc4100
-#define BCHP_DMA_AHB_CMD_RX_SCH16_REG_END 0x07dc4100
-#define BCHP_DMA_AHB_CMD_RX_SCH17_REG_START 0x07dc4110
-#define BCHP_DMA_AHB_CMD_RX_SCH17_REG_END 0x07dc4110
-#define BCHP_DMA_AHB_CMD_RX_SCH18_REG_START 0x07dc4120
-#define BCHP_DMA_AHB_CMD_RX_SCH18_REG_END 0x07dc4120
-#define BCHP_DMA_AHB_CMD_RX_SCH19_REG_START 0x07dc4130
-#define BCHP_DMA_AHB_CMD_RX_SCH19_REG_END 0x07dc4130
-#define BCHP_DMA_AHB_CMD_RES0_SCH0_REG_START 0x07dc4200
-#define BCHP_DMA_AHB_CMD_RES0_SCH0_REG_END 0x07dc4200
-#define BCHP_DMA_AHB_CMD_RES0_SCH1_REG_START 0x07dc4210
-#define BCHP_DMA_AHB_CMD_RES0_SCH1_REG_END 0x07dc4210
-#define BCHP_DMA_AHB_CMD_RES0_SCH2_REG_START 0x07dc4220
-#define BCHP_DMA_AHB_CMD_RES0_SCH2_REG_END 0x07dc4220
-#define BCHP_DMA_AHB_CMD_RES0_SCH3_REG_START 0x07dc4230
-#define BCHP_DMA_AHB_CMD_RES0_SCH3_REG_END 0x07dc4230
-#define BCHP_DMA_AHB_CMD_RES0_SCH4_REG_START 0x07dc4240
-#define BCHP_DMA_AHB_CMD_RES0_SCH4_REG_END 0x07dc4240
-#define BCHP_DMA_AHB_CMD_RES0_SCH5_REG_START 0x07dc4250
-#define BCHP_DMA_AHB_CMD_RES0_SCH5_REG_END 0x07dc4250
-#define BCHP_DMA_AHB_CMD_RES0_SCH6_REG_START 0x07dc4260
-#define BCHP_DMA_AHB_CMD_RES0_SCH6_REG_END 0x07dc4260
-#define BCHP_DMA_AHB_CMD_RES0_SCH7_REG_START 0x07dc4270
-#define BCHP_DMA_AHB_CMD_RES0_SCH7_REG_END 0x07dc4270
-#define BCHP_DMA_AHB_CMD_TX0_REG_START 0x07dc4800
-#define BCHP_DMA_AHB_CMD_TX0_REG_END 0x07dc4800
-#define BCHP_DMA_AHB_CMD_TX1_REG_START 0x07dc4a00
-#define BCHP_DMA_AHB_CMD_TX1_REG_END 0x07dc4a00
-#define BCHP_DMA_AHB_CMD_CONF0_REG_START 0x07dc4c00
-#define BCHP_DMA_AHB_CMD_CONF0_REG_END 0x07dc4c00
-#define BCHP_MAC_AHB_REG_START 0x07dc5000
-#define BCHP_MAC_AHB_REG_END 0x07dc500c
-#define BCHP_LLM_AHB_REG_START 0x07dc8000
-#define BCHP_LLM_AHB_REG_END 0x07dc805c
-#define BCHP_PHY_REG_START 0x07de0000
-#define BCHP_PHY_REG_END 0x07de47fc
-#define BCHP_ECL_REG_START 0x07de8000
-#define BCHP_ECL_REG_END 0x07dec940
-#define BCHP_DMA_IO2MEM_CH_ECL_TX_Global_REG_START 0x07ded000
-#define BCHP_DMA_IO2MEM_CH_ECL_TX_Global_REG_END 0x07ded014
-#define BCHP_DMA_IO2MEM_SUBCH_ECL_TX_SUBCH0_REG_START 0x07ded040
-#define BCHP_DMA_IO2MEM_SUBCH_ECL_TX_SUBCH0_REG_END 0x07ded06c
-#define BCHP_DMA_IO2MEM_SUBCH_ECL_TX_SUBCH1_REG_START 0x07ded080
-#define BCHP_DMA_IO2MEM_SUBCH_ECL_TX_SUBCH1_REG_END 0x07ded0ac
-#define BCHP_DMA_IO2MEM_SUBCH_ECL_TX_SUBCH2_REG_START 0x07ded0c0
-#define BCHP_DMA_IO2MEM_SUBCH_ECL_TX_SUBCH2_REG_END 0x07ded0ec
-#define BCHP_DMA_IO2MEM_SUBCH_ECL_TX_SUBCH3_REG_START 0x07ded100
-#define BCHP_DMA_IO2MEM_SUBCH_ECL_TX_SUBCH3_REG_END 0x07ded12c
-#define BCHP_DMA_IO2MEM_SUBCH_ECL_TX_SUBCH4_REG_START 0x07ded140
-#define BCHP_DMA_IO2MEM_SUBCH_ECL_TX_SUBCH4_REG_END 0x07ded16c
-#define BCHP_DMA_IO2MEM_SUBCH_ECL_TX_SUBCH5_REG_START 0x07ded180
-#define BCHP_DMA_IO2MEM_SUBCH_ECL_TX_SUBCH5_REG_END 0x07ded1ac
-#define BCHP_DMA_IO2MEM_SUBCH_ECL_TX_SUBCH6_REG_START 0x07ded1c0
-#define BCHP_DMA_IO2MEM_SUBCH_ECL_TX_SUBCH6_REG_END 0x07ded1ec
-#define BCHP_DMA_IO2MEM_SUBCH_ECL_TX_SUBCH7_REG_START 0x07ded200
-#define BCHP_DMA_IO2MEM_SUBCH_ECL_TX_SUBCH7_REG_END 0x07ded22c
-#define BCHP_DMA_IO2MEM_SUBCH_ECL_TX_SUBCH8_REG_START 0x07ded240
-#define BCHP_DMA_IO2MEM_SUBCH_ECL_TX_SUBCH8_REG_END 0x07ded26c
-#define BCHP_DMA_IO2MEM_SUBCH_ECL_TX_SUBCH9_REG_START 0x07ded280
-#define BCHP_DMA_IO2MEM_SUBCH_ECL_TX_SUBCH9_REG_END 0x07ded2ac
-#define BCHP_DMA_IO2MEM_SUBCH_ECL_TX_SUBCH10_REG_START 0x07ded2c0
-#define BCHP_DMA_IO2MEM_SUBCH_ECL_TX_SUBCH10_REG_END 0x07ded2ec
-#define BCHP_DMA_IO2MEM_SUBCH_ECL_TX_SUBCH11_REG_START 0x07ded300
-#define BCHP_DMA_IO2MEM_SUBCH_ECL_TX_SUBCH11_REG_END 0x07ded32c
-#define BCHP_DMA_IO2MEM_SUBCH_ECL_TX_SUBCH12_REG_START 0x07ded340
-#define BCHP_DMA_IO2MEM_SUBCH_ECL_TX_SUBCH12_REG_END 0x07ded36c
-#define BCHP_DMA_IO2MEM_SUBCH_ECL_TX_SUBCH13_REG_START 0x07ded380
-#define BCHP_DMA_IO2MEM_SUBCH_ECL_TX_SUBCH13_REG_END 0x07ded3ac
-#define BCHP_DMA_IO2MEM_SUBCH_ECL_TX_SUBCH14_REG_START 0x07ded3c0
-#define BCHP_DMA_IO2MEM_SUBCH_ECL_TX_SUBCH14_REG_END 0x07ded3ec
-#define BCHP_DMA_IO2MEM_SUBCH_ECL_TX_SUBCH15_REG_START 0x07ded400
-#define BCHP_DMA_IO2MEM_SUBCH_ECL_TX_SUBCH15_REG_END 0x07ded42c
-#define BCHP_DMA_IO2MEM_SUBCH_ECL_TX_SUBCH16_REG_START 0x07ded440
-#define BCHP_DMA_IO2MEM_SUBCH_ECL_TX_SUBCH16_REG_END 0x07ded46c
-#define BCHP_DMA_IO2MEM_SUBCH_ECL_TX_SUBCH17_REG_START 0x07ded480
-#define BCHP_DMA_IO2MEM_SUBCH_ECL_TX_SUBCH17_REG_END 0x07ded4ac
-#define BCHP_DMA_IO2MEM_SUBCH_ECL_TX_SUBCH18_REG_START 0x07ded4c0
-#define BCHP_DMA_IO2MEM_SUBCH_ECL_TX_SUBCH18_REG_END 0x07ded4ec
-#define BCHP_DMA_IO2MEM_SUBCH_ECL_TX_SUBCH19_REG_START 0x07ded500
-#define BCHP_DMA_IO2MEM_SUBCH_ECL_TX_SUBCH19_REG_END 0x07ded52c
-#define BCHP_DMA_MEM2IO_CH_ECL_RX_REG_START 0x07ded800
-#define BCHP_DMA_MEM2IO_CH_ECL_RX_REG_END 0x07ded828
-#define BCHP_GMII_REG_START 0x07dedc00
-#define BCHP_GMII_REG_END 0x07dedc58
-#define BCHP_MAC_APB_REG_START 0x07df0000
-#define BCHP_MAC_APB_REG_END 0x07df14fc
-#define BCHP_DMA_IO2MEM_CH_MAC_RX_Global_REG_START 0x07df4000
-#define BCHP_DMA_IO2MEM_CH_MAC_RX_Global_REG_END 0x07df4014
-#define BCHP_DMA_IO2MEM_SUBCH_MAC_RX_SUBCH0_REG_START 0x07df4040
-#define BCHP_DMA_IO2MEM_SUBCH_MAC_RX_SUBCH0_REG_END 0x07df406c
-#define BCHP_DMA_IO2MEM_SUBCH_MAC_RX_SUBCH1_REG_START 0x07df4080
-#define BCHP_DMA_IO2MEM_SUBCH_MAC_RX_SUBCH1_REG_END 0x07df40ac
-#define BCHP_DMA_IO2MEM_SUBCH_MAC_RX_SUBCH2_REG_START 0x07df40c0
-#define BCHP_DMA_IO2MEM_SUBCH_MAC_RX_SUBCH2_REG_END 0x07df40ec
-#define BCHP_DMA_IO2MEM_SUBCH_MAC_RX_SUBCH3_REG_START 0x07df4100
-#define BCHP_DMA_IO2MEM_SUBCH_MAC_RX_SUBCH3_REG_END 0x07df412c
-#define BCHP_DMA_IO2MEM_SUBCH_MAC_RX_SUBCH4_REG_START 0x07df4140
-#define BCHP_DMA_IO2MEM_SUBCH_MAC_RX_SUBCH4_REG_END 0x07df416c
-#define BCHP_DMA_IO2MEM_SUBCH_MAC_RX_SUBCH5_REG_START 0x07df4180
-#define BCHP_DMA_IO2MEM_SUBCH_MAC_RX_SUBCH5_REG_END 0x07df41ac
-#define BCHP_DMA_IO2MEM_SUBCH_MAC_RX_SUBCH6_REG_START 0x07df41c0
-#define BCHP_DMA_IO2MEM_SUBCH_MAC_RX_SUBCH6_REG_END 0x07df41ec
-#define BCHP_DMA_IO2MEM_SUBCH_MAC_RX_SUBCH7_REG_START 0x07df4200
-#define BCHP_DMA_IO2MEM_SUBCH_MAC_RX_SUBCH7_REG_END 0x07df422c
-#define BCHP_DMA_IO2MEM_SUBCH_MAC_RX_SUBCH8_REG_START 0x07df4240
-#define BCHP_DMA_IO2MEM_SUBCH_MAC_RX_SUBCH8_REG_END 0x07df426c
-#define BCHP_DMA_IO2MEM_SUBCH_MAC_RX_SUBCH9_REG_START 0x07df4280
-#define BCHP_DMA_IO2MEM_SUBCH_MAC_RX_SUBCH9_REG_END 0x07df42ac
-#define BCHP_DMA_IO2MEM_SUBCH_MAC_RX_SUBCH10_REG_START 0x07df42c0
-#define BCHP_DMA_IO2MEM_SUBCH_MAC_RX_SUBCH10_REG_END 0x07df42ec
-#define BCHP_DMA_IO2MEM_SUBCH_MAC_RX_SUBCH11_REG_START 0x07df4300
-#define BCHP_DMA_IO2MEM_SUBCH_MAC_RX_SUBCH11_REG_END 0x07df432c
-#define BCHP_DMA_IO2MEM_SUBCH_MAC_RX_SUBCH12_REG_START 0x07df4340
-#define BCHP_DMA_IO2MEM_SUBCH_MAC_RX_SUBCH12_REG_END 0x07df436c
-#define BCHP_DMA_IO2MEM_SUBCH_MAC_RX_SUBCH13_REG_START 0x07df4380
-#define BCHP_DMA_IO2MEM_SUBCH_MAC_RX_SUBCH13_REG_END 0x07df43ac
-#define BCHP_DMA_IO2MEM_SUBCH_MAC_RX_SUBCH14_REG_START 0x07df43c0
-#define BCHP_DMA_IO2MEM_SUBCH_MAC_RX_SUBCH14_REG_END 0x07df43ec
-#define BCHP_DMA_IO2MEM_SUBCH_MAC_RX_SUBCH15_REG_START 0x07df4400
-#define BCHP_DMA_IO2MEM_SUBCH_MAC_RX_SUBCH15_REG_END 0x07df442c
-#define BCHP_DMA_IO2MEM_SUBCH_MAC_RX_SUBCH16_REG_START 0x07df4440
-#define BCHP_DMA_IO2MEM_SUBCH_MAC_RX_SUBCH16_REG_END 0x07df446c
-#define BCHP_DMA_IO2MEM_SUBCH_MAC_RX_SUBCH17_REG_START 0x07df4480
-#define BCHP_DMA_IO2MEM_SUBCH_MAC_RX_SUBCH17_REG_END 0x07df44ac
-#define BCHP_DMA_IO2MEM_SUBCH_MAC_RX_SUBCH18_REG_START 0x07df44c0
-#define BCHP_DMA_IO2MEM_SUBCH_MAC_RX_SUBCH18_REG_END 0x07df44ec
-#define BCHP_DMA_IO2MEM_SUBCH_MAC_RX_SUBCH19_REG_START 0x07df4500
-#define BCHP_DMA_IO2MEM_SUBCH_MAC_RX_SUBCH19_REG_END 0x07df452c
-#define BCHP_DMA_IO2MEM_CH_PHY0_Global_REG_START 0x07df4800
-#define BCHP_DMA_IO2MEM_CH_PHY0_Global_REG_END 0x07df4814
-#define BCHP_DMA_IO2MEM_SUBCH_PHY0_SUBCH0_REG_START 0x07df4840
-#define BCHP_DMA_IO2MEM_SUBCH_PHY0_SUBCH0_REG_END 0x07df486c
-#define BCHP_DMA_IO2MEM_SUBCH_PHY0_SUBCH1_REG_START 0x07df4880
-#define BCHP_DMA_IO2MEM_SUBCH_PHY0_SUBCH1_REG_END 0x07df48ac
-#define BCHP_DMA_IO2MEM_SUBCH_PHY0_SUBCH2_REG_START 0x07df48c0
-#define BCHP_DMA_IO2MEM_SUBCH_PHY0_SUBCH2_REG_END 0x07df48ec
-#define BCHP_DMA_IO2MEM_SUBCH_PHY0_SUBCH3_REG_START 0x07df4900
-#define BCHP_DMA_IO2MEM_SUBCH_PHY0_SUBCH3_REG_END 0x07df492c
-#define BCHP_DMA_IO2MEM_SUBCH_PHY0_SUBCH4_REG_START 0x07df4940
-#define BCHP_DMA_IO2MEM_SUBCH_PHY0_SUBCH4_REG_END 0x07df496c
-#define BCHP_DMA_IO2MEM_SUBCH_PHY0_SUBCH5_REG_START 0x07df4980
-#define BCHP_DMA_IO2MEM_SUBCH_PHY0_SUBCH5_REG_END 0x07df49ac
-#define BCHP_DMA_IO2MEM_SUBCH_PHY0_SUBCH6_REG_START 0x07df49c0
-#define BCHP_DMA_IO2MEM_SUBCH_PHY0_SUBCH6_REG_END 0x07df49ec
-#define BCHP_DMA_IO2MEM_SUBCH_PHY0_SUBCH7_REG_START 0x07df4a00
-#define BCHP_DMA_IO2MEM_SUBCH_PHY0_SUBCH7_REG_END 0x07df4a2c
-#define BCHP_DMA_MEM2IO_CH_MAC_TX0_REG_START 0x07df6000
-#define BCHP_DMA_MEM2IO_CH_MAC_TX0_REG_END 0x07df6028
-#define BCHP_DMA_MEM2IO_CH_MAC_TX1_REG_START 0x07df6400
-#define BCHP_DMA_MEM2IO_CH_MAC_TX1_REG_END 0x07df6428
-#define BCHP_DMA_MEM2IO_CH_PHY0_CONFIG_REG_START 0x07df6800
-#define BCHP_DMA_MEM2IO_CH_PHY0_CONFIG_REG_END 0x07df6828
-#define BCHP_MOCA_INTC_L2_HI_REG_START 0x07df8000
-#define BCHP_MOCA_INTC_L2_HI_REG_END 0x07df8584
-#define BCHP_MOCA_INTC_L2_LO_REG_START 0x07df8800
-#define BCHP_MOCA_INTC_L2_LO_REG_END 0x07df8d84
-#define BCHP_LLM_APB_REG_START 0x07dfc000
-#define BCHP_LLM_APB_REG_END 0x07dfd00c
-#define BCHP_TRX_REG_START 0x07dfe000
-#define BCHP_TRX_REG_END 0x07dfe1fc
-#define BCHP_MOCA_TIMER_REG_START 0x07dfe400
-#define BCHP_MOCA_TIMER_REG_END 0x07dfe4ec
-#define BCHP_MOCA_GPIO_REG_START 0x07dfe800
-#define BCHP_MOCA_GPIO_REG_END 0x07dfe818
-#define BCHP_EXTRAS_REG_START 0x07dfec00
-#define BCHP_EXTRAS_REG_END 0x07dfed18
-#define BCHP_MOCA_BSC_REG_START 0x07dff000
-#define BCHP_MOCA_BSC_REG_END 0x07dff058
-#define BCHP_MOCA_HOSTM2M_REG_START 0x07dffc00
-#define BCHP_MOCA_HOSTM2M_REG_END 0x07dffc14
-#define BCHP_AHB_M2M_DMA_REG_START 0x07dffc20
-#define BCHP_AHB_M2M_DMA_REG_END 0x07dffc2c
-#define BCHP_MOCA_L2_REG_START 0x07dffc40
-#define BCHP_MOCA_L2_REG_END 0x07dffc6c
-#define BCHP_MOCA_GR_BRIDGE_REG_START 0x07dffc80
-#define BCHP_MOCA_GR_BRIDGE_REG_END 0x07dffc8c
-#define BCHP_MOCA_HOSTMISC_REG_START 0x07dffd00
-#define BCHP_MOCA_HOSTMISC_REG_END 0x07dffd9c
-#define BCHP_ERRORPORT_G2U_REG_START 0x07e00000
-#define BCHP_ERRORPORT_G2U_REG_END 0x07e00034
-#define BCHP_REQA0_G2U_REG_START 0x07e08000
-#define BCHP_REQA0_G2U_REG_END 0x07e0808c
-#define BCHP_REPA0_G2U_REG_START 0x07e08100
-#define BCHP_REPA0_G2U_REG_END 0x07e0818c
-#define BCHP_REQA1_G2U_REG_START 0x07e09000
-#define BCHP_REQA1_G2U_REG_END 0x07e0908c
-#define BCHP_REPA1_G2U_REG_START 0x07e09100
-#define BCHP_REPA1_G2U_REG_END 0x07e0918c
-#define BCHP_HEVD_OL_CPU_REGS_0_REG_START 0x20000000
-#define BCHP_HEVD_OL_CPU_REGS_0_REG_END 0x20000108
-#define BCHP_HEVD_OL_CPU_DMA_0_REG_START 0x20000400
-#define BCHP_HEVD_OL_CPU_DMA_0_REG_END 0x20000440
-#define BCHP_HEVD_OL_CPU_DEBUG_0_REG_START 0x20000800
-#define BCHP_HEVD_OL_CPU_DEBUG_0_REG_END 0x20000ffc
-#define BCHP_HEVD_OL_SINT_0_REG_START 0x20001000
-#define BCHP_HEVD_OL_SINT_0_REG_END 0x20001028
-#define BCHP_HEVD_OL_LDST_0_REG_START 0x20008000
-#define BCHP_HEVD_OL_LDST_0_REG_END 0x2000fffc
-#define BCHP_REG_CABAC2BINS_0_REG_START 0x20010b00
-#define BCHP_REG_CABAC2BINS_0_REG_END 0x20010bfc
-#define BCHP_REG_CABAC2BINS2_0_REG_START 0x20012400
-#define BCHP_REG_CABAC2BINS2_0_REG_END 0x200127fc
-#define BCHP_HEVD_CABAC_0_REG_START 0x20013000
-#define BCHP_HEVD_CABAC_0_REG_END 0x200130bc
-#define BCHP_HEVD_OL_CTL_0_REG_START 0x20014000
-#define BCHP_HEVD_OL_CTL_0_REG_END 0x200151fc
-#define BCHP_DECODE_MAIN_0_REG_START 0x20020100
-#define BCHP_DECODE_MAIN_0_REG_END 0x200201fc
-#define BCHP_DECODE_MCOM_0_REG_START 0x20020300
-#define BCHP_DECODE_MCOM_0_REG_END 0x2002031c
-#define BCHP_DECODE_SPRE_0_REG_START 0x20020320
-#define BCHP_DECODE_SPRE_0_REG_END 0x2002033c
-#define BCHP_DECODE_WPRD_0_REG_START 0x20020340
-#define BCHP_DECODE_WPRD_0_REG_END 0x2002035c
-#define BCHP_DECODE_DQNT_0_REG_START 0x20020400
-#define BCHP_DECODE_DQNT_0_REG_END 0x2002045c
-#define BCHP_DECODE_DQNT_8X8_0_REG_START 0x20020500
-#define BCHP_DECODE_DQNT_8X8_0_REG_END 0x2002057c
-#define BCHP_DECODE_VP8_XFRM_0_REG_START 0x20020600
-#define BCHP_DECODE_VP8_XFRM_0_REG_END 0x2002060c
-#define BCHP_DECODE_VP6_DCP_0_REG_START 0x20020620
-#define BCHP_DECODE_VP6_DCP_0_REG_END 0x2002062c
-#define BCHP_DECODE_XFRM_0_REG_START 0x20020700
-#define BCHP_DECODE_XFRM_0_REG_END 0x2002071c
-#define BCHP_DECODE_DBLK_0_REG_START 0x20020720
-#define BCHP_DECODE_DBLK_0_REG_END 0x2002073c
-#define BCHP_DECODE_MB_0_REG_START 0x20020740
-#define BCHP_DECODE_MB_0_REG_END 0x2002075c
-#define BCHP_DECODE_SINT_0_REG_START 0x20020c00
-#define BCHP_DECODE_SINT_0_REG_END 0x20020dfc
-#define BCHP_DECODE_RVC_0_REG_START 0x20020e00
-#define BCHP_DECODE_RVC_0_REG_END 0x20020efc
-#define BCHP_DECODE_WPTBL_0_REG_START 0x20023000
-#define BCHP_DECODE_WPTBL_0_REG_END 0x200231fc
-#define BCHP_HEVD_BE_GLOBAL_0_REG_START 0x20024000
-#define BCHP_HEVD_BE_GLOBAL_0_REG_END 0x20024030
-#define BCHP_HEVD_IXFORM_0_REG_START 0x20024100
-#define BCHP_HEVD_IXFORM_0_REG_END 0x200241fc
-#define BCHP_HEVD_MCOMP_0_REG_START 0x20024200
-#define BCHP_HEVD_MCOMP_0_REG_END 0x200242fc
-#define BCHP_HEVD_SPRED_0_REG_START 0x20024300
-#define BCHP_HEVD_SPRED_0_REG_END 0x200243f0
-#define BCHP_HEVD_FILTER_0_REG_START 0x20024400
-#define BCHP_HEVD_FILTER_0_REG_END 0x200244fc
-#define BCHP_HEVD_OUTPUT_0_REG_START 0x20024500
-#define BCHP_HEVD_OUTPUT_0_REG_END 0x200245fc
-#define BCHP_HEVD_MARKER_0_REG_START 0x20024f00
-#define BCHP_HEVD_MARKER_0_REG_END 0x20024f7c
-#define BCHP_HEVD_FE_CTRL_0_REG_START 0x20025000
-#define BCHP_HEVD_FE_CTRL_0_REG_END 0x20025034
-#define BCHP_HEVD_STRM_IN_0_REG_START 0x20025100
-#define BCHP_HEVD_STRM_IN_0_REG_END 0x20025118
-#define BCHP_HEVD_CMDBUS_XMIT_0_REG_START 0x20025200
-#define BCHP_HEVD_CMDBUS_XMIT_0_REG_END 0x20025210
-#define BCHP_HEVD_VECGEN_0_REG_START 0x20025400
-#define BCHP_HEVD_VECGEN_0_REG_END 0x2002568c
-#define BCHP_DCD_PIPE_CTL_0_REG_START 0x20026000
-#define BCHP_DCD_PIPE_CTL_0_REG_END 0x20026404
-#define BCHP_HEVD_PCACHE_0_REG_START 0x20026800
-#define BCHP_HEVD_PCACHE_0_REG_END 0x20026834
-#define BCHP_HEVD_PFRI_0_REG_START 0x20026a00
-#define BCHP_HEVD_PFRI_0_REG_END 0x20026b58
-#define BCHP_RVC_0_REG_START 0x20026c00
-#define BCHP_RVC_0_REG_END 0x20026c20
-#define BCHP_ILS_REGS_0_REG_START 0x20027000
-#define BCHP_ILS_REGS_0_REG_END 0x200270fc
-#define BCHP_ILS_SCALE_ADDR_0_REG_START 0x20027100
-#define BCHP_ILS_SCALE_ADDR_0_REG_END 0x2002710c
-#define BCHP_ILS_SPSCALE_FILL_0_REG_START 0x20027180
-#define BCHP_ILS_SPSCALE_FILL_0_REG_END 0x20027184
-#define BCHP_ILS_MVSCALE_0_REG_START 0x20027200
-#define BCHP_ILS_MVSCALE_0_REG_END 0x2002738c
-#define BCHP_ILB_REGS_0_REG_START 0x20027400
-#define BCHP_ILB_REGS_0_REG_END 0x20027410
-#define BCHP_BLD_DECODE_MAIN_0_REG_START 0x20028100
-#define BCHP_BLD_DECODE_MAIN_0_REG_END 0x200281fc
-#define BCHP_BLD_DECODE_MCOM_0_REG_START 0x20028300
-#define BCHP_BLD_DECODE_MCOM_0_REG_END 0x2002831c
-#define BCHP_BLD_DECODE_SPRE_0_REG_START 0x20028320
-#define BCHP_BLD_DECODE_SPRE_0_REG_END 0x2002833c
-#define BCHP_BLD_DECODE_DQNT_0_REG_START 0x20028400
-#define BCHP_BLD_DECODE_DQNT_0_REG_END 0x2002845c
-#define BCHP_BLD_DECODE_DQNT_8X8_0_REG_START 0x20028500
-#define BCHP_BLD_DECODE_DQNT_8X8_0_REG_END 0x2002857c
-#define BCHP_BLD_DECODE_XFRM_0_REG_START 0x20028700
-#define BCHP_BLD_DECODE_XFRM_0_REG_END 0x2002871c
-#define BCHP_BLD_DECODE_DBLK_0_REG_START 0x20028720
-#define BCHP_BLD_DECODE_DBLK_0_REG_END 0x2002873c
-#define BCHP_BLD_DECODE_MB_0_REG_START 0x20028740
-#define BCHP_BLD_DECODE_MB_0_REG_END 0x2002875c
-#define BCHP_BLD_DECODE_SINT_0_REG_START 0x20028c00
-#define BCHP_BLD_DECODE_SINT_0_REG_END 0x20028dfc
-#define BCHP_BLD_DECODE_RVC_0_REG_START 0x20028e00
-#define BCHP_BLD_DECODE_RVC_0_REG_END 0x20028efc
-#define BCHP_BLD_BL_CPU_REGS_0_REG_START 0x2002c000
-#define BCHP_BLD_BL_CPU_REGS_0_REG_END 0x2002c108
-#define BCHP_BLD_BL_CPU_DMA_0_REG_START 0x2002c400
-#define BCHP_BLD_BL_CPU_DMA_0_REG_END 0x2002c440
-#define BCHP_BLD_BL_CPU_DEBUG_0_REG_START 0x2002c800
-#define BCHP_BLD_BL_CPU_DEBUG_0_REG_END 0x2002cffc
-#define BCHP_BLD_DECODE_IP_SHIM_0_REG_START 0x2002d000
-#define BCHP_BLD_DECODE_IP_SHIM_0_REG_END 0x2002d090
-#define BCHP_HEVD_IL_CPU_REGS_0_REG_START 0x20030000
-#define BCHP_HEVD_IL_CPU_REGS_0_REG_END 0x20030108
-#define BCHP_HEVD_IL_CPU_DMA_0_REG_START 0x20030400
-#define BCHP_HEVD_IL_CPU_DMA_0_REG_END 0x20030440
-#define BCHP_HEVD_IL_CPU_DEBUG_0_REG_START 0x20030800
-#define BCHP_HEVD_IL_CPU_DEBUG_0_REG_END 0x20030ffc
-#define BCHP_HEVD_IL_SLICE_DMA_0_REG_START 0x20031000
-#define BCHP_HEVD_IL_SLICE_DMA_0_REG_END 0x2003100c
-#define BCHP_HEVD_IL_LDST_0_REG_START 0x20034000
-#define BCHP_HEVD_IL_LDST_0_REG_END 0x20037ffc
-#define BCHP_SHVD_INTR2_0_REG_START 0x20080000
-#define BCHP_SHVD_INTR2_0_REG_END 0x2008002c
-#define BCHP_SHVD_RGR_0_REG_START 0x20080400
-#define BCHP_SHVD_RGR_0_REG_END 0x20080410
-#define BCHP_VICH_0_REG_START 0x200a0000
-#define BCHP_VICH_0_REG_END 0x200a008b
-#define BCHP_HEVD_OL_CPU_REGS_1_REG_START 0x20100000
-#define BCHP_HEVD_OL_CPU_REGS_1_REG_END 0x20100108
-#define BCHP_HEVD_OL_CPU_DMA_1_REG_START 0x20100400
-#define BCHP_HEVD_OL_CPU_DMA_1_REG_END 0x20100440
-#define BCHP_HEVD_OL_CPU_DEBUG_1_REG_START 0x20100800
-#define BCHP_HEVD_OL_CPU_DEBUG_1_REG_END 0x20100ffc
-#define BCHP_HEVD_OL_SINT_1_REG_START 0x20101000
-#define BCHP_HEVD_OL_SINT_1_REG_END 0x20101028
-#define BCHP_HEVD_OL_LDST_1_REG_START 0x20108000
-#define BCHP_HEVD_OL_LDST_1_REG_END 0x2010fffc
-#define BCHP_REG_CABAC2BINS_1_REG_START 0x20110b00
-#define BCHP_REG_CABAC2BINS_1_REG_END 0x20110bfc
-#define BCHP_REG_CABAC2BINS2_1_REG_START 0x20112400
-#define BCHP_REG_CABAC2BINS2_1_REG_END 0x201127fc
-#define BCHP_HEVD_CABAC_1_REG_START 0x20113000
-#define BCHP_HEVD_CABAC_1_REG_END 0x201130bc
-#define BCHP_HEVD_OL_CTL_1_REG_START 0x20114000
-#define BCHP_HEVD_OL_CTL_1_REG_END 0x201151fc
-#define BCHP_DECODE_MAIN_1_REG_START 0x20120100
-#define BCHP_DECODE_MAIN_1_REG_END 0x201201fc
-#define BCHP_DECODE_MCOM_1_REG_START 0x20120300
-#define BCHP_DECODE_MCOM_1_REG_END 0x2012031c
-#define BCHP_DECODE_SPRE_1_REG_START 0x20120320
-#define BCHP_DECODE_SPRE_1_REG_END 0x2012033c
-#define BCHP_DECODE_WPRD_1_REG_START 0x20120340
-#define BCHP_DECODE_WPRD_1_REG_END 0x2012035c
-#define BCHP_DECODE_DQNT_1_REG_START 0x20120400
-#define BCHP_DECODE_DQNT_1_REG_END 0x2012045c
-#define BCHP_DECODE_DQNT_8X8_1_REG_START 0x20120500
-#define BCHP_DECODE_DQNT_8X8_1_REG_END 0x2012057c
-#define BCHP_DECODE_VP8_XFRM_1_REG_START 0x20120600
-#define BCHP_DECODE_VP8_XFRM_1_REG_END 0x2012060c
-#define BCHP_DECODE_VP6_DCP_1_REG_START 0x20120620
-#define BCHP_DECODE_VP6_DCP_1_REG_END 0x2012062c
-#define BCHP_DECODE_XFRM_1_REG_START 0x20120700
-#define BCHP_DECODE_XFRM_1_REG_END 0x2012071c
-#define BCHP_DECODE_DBLK_1_REG_START 0x20120720
-#define BCHP_DECODE_DBLK_1_REG_END 0x2012073c
-#define BCHP_DECODE_MB_1_REG_START 0x20120740
-#define BCHP_DECODE_MB_1_REG_END 0x2012075c
-#define BCHP_DECODE_SINT_1_REG_START 0x20120c00
-#define BCHP_DECODE_SINT_1_REG_END 0x20120dfc
-#define BCHP_DECODE_RVC_1_REG_START 0x20120e00
-#define BCHP_DECODE_RVC_1_REG_END 0x20120efc
-#define BCHP_DECODE_WPTBL_1_REG_START 0x20123000
-#define BCHP_DECODE_WPTBL_1_REG_END 0x201231fc
-#define BCHP_HEVD_BE_GLOBAL_1_REG_START 0x20124000
-#define BCHP_HEVD_BE_GLOBAL_1_REG_END 0x20124030
-#define BCHP_HEVD_IXFORM_1_REG_START 0x20124100
-#define BCHP_HEVD_IXFORM_1_REG_END 0x201241fc
-#define BCHP_HEVD_MCOMP_1_REG_START 0x20124200
-#define BCHP_HEVD_MCOMP_1_REG_END 0x201242fc
-#define BCHP_HEVD_SPRED_1_REG_START 0x20124300
-#define BCHP_HEVD_SPRED_1_REG_END 0x201243f0
-#define BCHP_HEVD_FILTER_1_REG_START 0x20124400
-#define BCHP_HEVD_FILTER_1_REG_END 0x201244fc
-#define BCHP_HEVD_OUTPUT_1_REG_START 0x20124500
-#define BCHP_HEVD_OUTPUT_1_REG_END 0x201245fc
-#define BCHP_HEVD_MARKER_1_REG_START 0x20124f00
-#define BCHP_HEVD_MARKER_1_REG_END 0x20124f7c
-#define BCHP_HEVD_FE_CTRL_1_REG_START 0x20125000
-#define BCHP_HEVD_FE_CTRL_1_REG_END 0x20125034
-#define BCHP_HEVD_STRM_IN_1_REG_START 0x20125100
-#define BCHP_HEVD_STRM_IN_1_REG_END 0x20125118
-#define BCHP_HEVD_CMDBUS_XMIT_1_REG_START 0x20125200
-#define BCHP_HEVD_CMDBUS_XMIT_1_REG_END 0x20125210
-#define BCHP_HEVD_VECGEN_1_REG_START 0x20125400
-#define BCHP_HEVD_VECGEN_1_REG_END 0x2012568c
-#define BCHP_DCD_PIPE_CTL_1_REG_START 0x20126000
-#define BCHP_DCD_PIPE_CTL_1_REG_END 0x20126404
-#define BCHP_HEVD_PCACHE_1_REG_START 0x20126800
-#define BCHP_HEVD_PCACHE_1_REG_END 0x20126834
-#define BCHP_HEVD_PFRI_1_REG_START 0x20126a00
-#define BCHP_HEVD_PFRI_1_REG_END 0x20126b58
-#define BCHP_RVC_1_REG_START 0x20126c00
-#define BCHP_RVC_1_REG_END 0x20126c20
-#define BCHP_ILS_REGS_1_REG_START 0x20127000
-#define BCHP_ILS_REGS_1_REG_END 0x201270fc
-#define BCHP_ILS_SCALE_ADDR_1_REG_START 0x20127100
-#define BCHP_ILS_SCALE_ADDR_1_REG_END 0x2012710c
-#define BCHP_ILS_SPSCALE_FILL_1_REG_START 0x20127180
-#define BCHP_ILS_SPSCALE_FILL_1_REG_END 0x20127184
-#define BCHP_ILS_MVSCALE_1_REG_START 0x20127200
-#define BCHP_ILS_MVSCALE_1_REG_END 0x2012738c
-#define BCHP_ILB_REGS_1_REG_START 0x20127400
-#define BCHP_ILB_REGS_1_REG_END 0x20127410
-#define BCHP_BLD_DECODE_MAIN_1_REG_START 0x20128100
-#define BCHP_BLD_DECODE_MAIN_1_REG_END 0x201281fc
-#define BCHP_BLD_DECODE_MCOM_1_REG_START 0x20128300
-#define BCHP_BLD_DECODE_MCOM_1_REG_END 0x2012831c
-#define BCHP_BLD_DECODE_SPRE_1_REG_START 0x20128320
-#define BCHP_BLD_DECODE_SPRE_1_REG_END 0x2012833c
-#define BCHP_BLD_DECODE_DQNT_1_REG_START 0x20128400
-#define BCHP_BLD_DECODE_DQNT_1_REG_END 0x2012845c
-#define BCHP_BLD_DECODE_DQNT_8X8_1_REG_START 0x20128500
-#define BCHP_BLD_DECODE_DQNT_8X8_1_REG_END 0x2012857c
-#define BCHP_BLD_DECODE_XFRM_1_REG_START 0x20128700
-#define BCHP_BLD_DECODE_XFRM_1_REG_END 0x2012871c
-#define BCHP_BLD_DECODE_DBLK_1_REG_START 0x20128720
-#define BCHP_BLD_DECODE_DBLK_1_REG_END 0x2012873c
-#define BCHP_BLD_DECODE_MB_1_REG_START 0x20128740
-#define BCHP_BLD_DECODE_MB_1_REG_END 0x2012875c
-#define BCHP_BLD_DECODE_SINT_1_REG_START 0x20128c00
-#define BCHP_BLD_DECODE_SINT_1_REG_END 0x20128dfc
-#define BCHP_BLD_DECODE_RVC_1_REG_START 0x20128e00
-#define BCHP_BLD_DECODE_RVC_1_REG_END 0x20128efc
-#define BCHP_BLD_BL_CPU_REGS_1_REG_START 0x2012c000
-#define BCHP_BLD_BL_CPU_REGS_1_REG_END 0x2012c108
-#define BCHP_BLD_BL_CPU_DMA_1_REG_START 0x2012c400
-#define BCHP_BLD_BL_CPU_DMA_1_REG_END 0x2012c440
-#define BCHP_BLD_BL_CPU_DEBUG_1_REG_START 0x2012c800
-#define BCHP_BLD_BL_CPU_DEBUG_1_REG_END 0x2012cffc
-#define BCHP_BLD_DECODE_IP_SHIM_1_REG_START 0x2012d000
-#define BCHP_BLD_DECODE_IP_SHIM_1_REG_END 0x2012d090
-#define BCHP_HEVD_IL_CPU_REGS_1_REG_START 0x20130000
-#define BCHP_HEVD_IL_CPU_REGS_1_REG_END 0x20130108
-#define BCHP_HEVD_IL_CPU_DMA_1_REG_START 0x20130400
-#define BCHP_HEVD_IL_CPU_DMA_1_REG_END 0x20130440
-#define BCHP_HEVD_IL_CPU_DEBUG_1_REG_START 0x20130800
-#define BCHP_HEVD_IL_CPU_DEBUG_1_REG_END 0x20130ffc
-#define BCHP_HEVD_IL_SLICE_DMA_1_REG_START 0x20131000
-#define BCHP_HEVD_IL_SLICE_DMA_1_REG_END 0x2013100c
-#define BCHP_HEVD_IL_LDST_1_REG_START 0x20134000
-#define BCHP_HEVD_IL_LDST_1_REG_END 0x20137ffc
-#define BCHP_SHVD_INTR2_1_REG_START 0x20180000
-#define BCHP_SHVD_INTR2_1_REG_END 0x2018002c
-#define BCHP_SHVD_RGR_1_REG_START 0x20180400
-#define BCHP_SHVD_RGR_1_REG_END 0x20180410
-#define BCHP_VICH_1_REG_START 0x201a0000
-#define BCHP_VICH_1_REG_END 0x201a008b
-#define BCHP_SCPU_LOCALRAM_REG_START 0x20300000
-#define BCHP_SCPU_LOCALRAM_REG_END 0x20307ffc
-#define BCHP_SCPU_GLOBALRAM_REG_START 0x20308000
-#define BCHP_SCPU_GLOBALRAM_REG_END 0x203083fc
-#define BCHP_SCPU_MISB_BRIDGE_REG_START 0x20308400
-#define BCHP_SCPU_MISB_BRIDGE_REG_END 0x20308410
-#define BCHP_SCPU_RGR_BRIDGE_REG_START 0x20308420
-#define BCHP_SCPU_RGR_BRIDGE_REG_END 0x20308430
-#define BCHP_SCPU_INTR1_REG_START 0x20308440
-#define BCHP_SCPU_INTR1_REG_END 0x20308458
-#define BCHP_INTERNAL_INTR2_REG_START 0x20308480
-#define BCHP_INTERNAL_INTR2_REG_END 0x203084ac
-#define BCHP_BSP_IPI_INTR2_REG_START 0x203084c0
-#define BCHP_BSP_IPI_INTR2_REG_END 0x203084ec
-#define BCHP_CPU_IPI_INTR2_REG_START 0x20308500
-#define BCHP_CPU_IPI_INTR2_REG_END 0x2030852c
-#define BCHP_SCPU_HOST_INTR2_REG_START 0x20308540
-#define BCHP_SCPU_HOST_INTR2_REG_END 0x2030856c
-#define BCHP_SCPU_TOP_CTRL_REG_START 0x20308580
-#define BCHP_SCPU_TOP_CTRL_REG_END 0x20308588
-#define BCHP_SCPU_SEC_TIME_REG_START 0x203085a0
-#define BCHP_SCPU_SEC_TIME_REG_END 0x203085b4
-#define BCHP_SCPU_PM_REG_START 0x20308980
-#define BCHP_SCPU_PM_REG_END 0x20308988
-#define BCHP_SCPU_TIMER_REG_START 0x20308e80
-#define BCHP_SCPU_TIMER_REG_END 0x20308ebc
-#define BCHP_S_SCPU_REG_START 0x20310000
-#define BCHP_S_SCPU_REG_END 0x2031bffc
-#define BCHP_BSP_CMDBUF_REG_START 0x20329800
-#define BCHP_BSP_CMDBUF_REG_END 0x20329ffc
-#define BCHP_BSP_GLB_CONTROL_REG_START 0x2032b000
-#define BCHP_BSP_GLB_CONTROL_REG_END 0x2032b0b0
-#define BCHP_BSP_PKL_REG_START 0x2032b300
-#define BCHP_BSP_PKL_REG_END 0x2032b37c
-#define BCHP_BSP_CONTROL_INTR2_REG_START 0x2032b800
-#define BCHP_BSP_CONTROL_INTR2_REG_END 0x2032b82c
-#define BCHP_BSP_VISTA_GENACC_REG_START 0x2032b900
-#define BCHP_BSP_VISTA_GENACC_REG_END 0x2032b9fc
-#define BCHP_BSP_VISTA_GENACC2_REG_START 0x2032ba00
-#define BCHP_BSP_VISTA_GENACC2_REG_END 0x2032bafc
-#define BCHP_BSP_OTP_SCRATCH_REG_START 0x2032c000
-#define BCHP_BSP_OTP_SCRATCH_REG_END 0x2032dffc
-#define BCHP_XPT_SECURITY_REG_START 0x20360000
-#define BCHP_XPT_SECURITY_REG_END 0x2037fffc
-#define BCHP_SECTOP_GRB_REG_START 0x20380000
-#define BCHP_SECTOP_GRB_REG_END 0x2038000c
-#define BCHP_XPT_SECURITY_NS_REG_START 0x20380200
-#define BCHP_XPT_SECURITY_NS_REG_END 0x20380224
-#define BCHP_MEMC_GEN_0_REG_START 0x203b0000
-#define BCHP_MEMC_GEN_0_REG_END 0x203b0410
-#define BCHP_MEMC_EDIS_0_0_REG_START 0x203b0800
-#define BCHP_MEMC_EDIS_0_0_REG_END 0x203b08fc
-#define BCHP_MEMC_EDIS_0_1_REG_START 0x203b0a00
-#define BCHP_MEMC_EDIS_0_1_REG_END 0x203b0afc
-#define BCHP_MEMC_ARC_0_REG_START 0x203b0c00
-#define BCHP_MEMC_ARC_0_REG_END 0x203b0f74
-#define BCHP_MEMC_ARB_0_REG_START 0x203b1000
-#define BCHP_MEMC_ARB_0_REG_END 0x203b14a8
-#define BCHP_MEMC_DDR_0_REG_START 0x203b2000
-#define BCHP_MEMC_DDR_0_REG_END 0x203b27fc
-#define BCHP_MEMC_L2_0_0_REG_START 0x203b3000
-#define BCHP_MEMC_L2_0_0_REG_END 0x203b3044
-#define BCHP_MEMC_L2_0_1_REG_START 0x203b3200
-#define BCHP_MEMC_L2_0_1_REG_END 0x203b3244
-#define BCHP_MEMC_L2_0_2_REG_START 0x203b3400
-#define BCHP_MEMC_L2_0_2_REG_END 0x203b3444
-#define BCHP_MEMC_TRACELOG_0_0_REG_START 0x203b3800
-#define BCHP_MEMC_TRACELOG_0_0_REG_END 0x203b39fc
-#define BCHP_MEMC_SENTINEL_0_0_REG_START 0x203b3c00
-#define BCHP_MEMC_SENTINEL_0_0_REG_END 0x203b3ffc
-#define BCHP_MEMC_RGRB_0_REG_START 0x203b4000
-#define BCHP_MEMC_RGRB_0_REG_END 0x203b4010
-#define BCHP_MEMC_MISC_0_REG_START 0x203b5000
-#define BCHP_MEMC_MISC_0_REG_END 0x203b5010
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_REG_START 0x203b6000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_REG_END 0x203b6248
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_REG_START 0x203b6400
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_REG_END 0x203b6514
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_REG_START 0x203b6600
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_REG_END 0x203b6714
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_REG_START 0x203b6800
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_REG_END 0x203b6914
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_REG_START 0x203b6a00
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_REG_END 0x203b6b14
-#define BCHP_DDR34_PHY_ECC_LANE_0_REG_START 0x203b6c00
-#define BCHP_DDR34_PHY_ECC_LANE_0_REG_END 0x203b6d14
-#define BCHP_SHIMPHY_ADDR_CNTL_0_REG_START 0x203b8000
-#define BCHP_SHIMPHY_ADDR_CNTL_0_REG_END 0x203b80b4
-#define BCHP_MEMC_UBUS_0_REG_START 0x203b9000
-#define BCHP_MEMC_UBUS_0_REG_END 0x203b94cc
-#define BCHP_MEMC_ATW_UBUS_0_REG_START 0x203b9800
-#define BCHP_MEMC_ATW_UBUS_0_REG_END 0x203b99e0
-#define BCHP_S_MEMC_0_REG_START 0x203bc000
-#define BCHP_S_MEMC_0_REG_END 0x203bc5b0
-#define BCHP_MEMC_SECURE_UBUS_0_REG_START 0x203bd000
-#define BCHP_MEMC_SECURE_UBUS_0_REG_END 0x203bd434
-#define BCHP_MEMC_GEN_1_REG_START 0x203c0000
-#define BCHP_MEMC_GEN_1_REG_END 0x203c0410
-#define BCHP_MEMC_EDIS_1_0_REG_START 0x203c0800
-#define BCHP_MEMC_EDIS_1_0_REG_END 0x203c08fc
-#define BCHP_MEMC_EDIS_1_1_REG_START 0x203c0a00
-#define BCHP_MEMC_EDIS_1_1_REG_END 0x203c0afc
-#define BCHP_MEMC_ARC_1_REG_START 0x203c0c00
-#define BCHP_MEMC_ARC_1_REG_END 0x203c0f74
-#define BCHP_MEMC_ARB_1_REG_START 0x203c1000
-#define BCHP_MEMC_ARB_1_REG_END 0x203c14a8
-#define BCHP_MEMC_DDR_1_REG_START 0x203c2000
-#define BCHP_MEMC_DDR_1_REG_END 0x203c27fc
-#define BCHP_MEMC_L2_1_0_REG_START 0x203c3000
-#define BCHP_MEMC_L2_1_0_REG_END 0x203c3044
-#define BCHP_MEMC_L2_1_1_REG_START 0x203c3200
-#define BCHP_MEMC_L2_1_1_REG_END 0x203c3244
-#define BCHP_MEMC_L2_1_2_REG_START 0x203c3400
-#define BCHP_MEMC_L2_1_2_REG_END 0x203c3444
-#define BCHP_MEMC_TRACELOG_0_1_REG_START 0x203c3800
-#define BCHP_MEMC_TRACELOG_0_1_REG_END 0x203c39fc
-#define BCHP_MEMC_SENTINEL_0_1_REG_START 0x203c3c00
-#define BCHP_MEMC_SENTINEL_0_1_REG_END 0x203c3ffc
-#define BCHP_MEMC_RGRB_1_REG_START 0x203c4000
-#define BCHP_MEMC_RGRB_1_REG_END 0x203c4010
-#define BCHP_MEMC_MISC_1_REG_START 0x203c5000
-#define BCHP_MEMC_MISC_1_REG_END 0x203c5010
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_REG_START 0x203c6000
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_REG_END 0x203c6248
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_REG_START 0x203c6400
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_REG_END 0x203c6514
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_REG_START 0x203c6600
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_REG_END 0x203c6714
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_REG_START 0x203c6800
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_REG_END 0x203c6914
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_REG_START 0x203c6a00
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_REG_END 0x203c6b14
-#define BCHP_DDR34_PHY_ECC_LANE_1_REG_START 0x203c6c00
-#define BCHP_DDR34_PHY_ECC_LANE_1_REG_END 0x203c6d14
-#define BCHP_SHIMPHY_ADDR_CNTL_1_REG_START 0x203c8000
-#define BCHP_SHIMPHY_ADDR_CNTL_1_REG_END 0x203c80b4
-#define BCHP_MEMC_UBUS_1_REG_START 0x203c9000
-#define BCHP_MEMC_UBUS_1_REG_END 0x203c94cc
-#define BCHP_MEMC_ATW_UBUS_1_REG_START 0x203c9800
-#define BCHP_MEMC_ATW_UBUS_1_REG_END 0x203c99e0
-#define BCHP_S_MEMC_1_REG_START 0x203cc000
-#define BCHP_S_MEMC_1_REG_END 0x203cc5b0
-#define BCHP_MEMC_SECURE_UBUS_1_REG_START 0x203cd000
-#define BCHP_MEMC_SECURE_UBUS_1_REG_END 0x203cd434
-#define BCHP_SDIO_0_HOST_REG_START 0x203d0000
-#define BCHP_SDIO_0_HOST_REG_END 0x203d00fc
-#define BCHP_SDIO_0_CFG_REG_START 0x203d0100
-#define BCHP_SDIO_0_CFG_REG_END 0x203d01fc
-#define BCHP_SDIO_1_HOST_REG_START 0x203d0200
-#define BCHP_SDIO_1_HOST_REG_END 0x203d02fc
-#define BCHP_SDIO_1_CFG_REG_START 0x203d0300
-#define BCHP_SDIO_1_CFG_REG_END 0x203d03fc
-#define BCHP_SDIO_1_BOOT_REG_START 0x203d0400
-#define BCHP_SDIO_1_BOOT_REG_END 0x203d043c
-#define BCHP_EBI_REG_START 0x203d0800
-#define BCHP_EBI_REG_END 0x203d0bfc
-#define BCHP_HIF_INTR2_REG_START 0x203d1000
-#define BCHP_HIF_INTR2_REG_END 0x203d102c
-#define BCHP_IPI0_INTR2_REG_START 0x203d1100
-#define BCHP_IPI0_INTR2_REG_END 0x203d112c
-#define BCHP_HIF_CPU_INTR1_REG_START 0x203d1500
-#define BCHP_HIF_CPU_INTR1_REG_END 0x203d153c
-#define BCHP_HIF_RGR2_REG_START 0x203d1700
-#define BCHP_HIF_RGR2_REG_END 0x203d1710
-#define BCHP_HIF_SPI_INTR2_REG_START 0x203d1a00
-#define BCHP_HIF_SPI_INTR2_REG_END 0x203d1a2c
-#define BCHP_HIF_TOP_CTRL_REG_START 0x203d2000
-#define BCHP_HIF_TOP_CTRL_REG_END 0x203d2038
-#define BCHP_ROUTER_HIF_L1_MASK_REG_START 0x203d2100
-#define BCHP_ROUTER_HIF_L1_MASK_REG_END 0x203d210c
-#define BCHP_HIF_CPUBIUARCH_REG_START 0x203d2200
-#define BCHP_HIF_CPUBIUARCH_REG_END 0x203d23fc
-#define BCHP_HIF_CPUBIUCTRL_REG_START 0x203d2400
-#define BCHP_HIF_CPUBIUCTRL_REG_END 0x203d27fc
-#define BCHP_NAND_REG_START 0x203d2800
-#define BCHP_NAND_REG_END 0x203d2dfc
-#define BCHP_FLASH_DMA_REG_START 0x203d3000
-#define BCHP_FLASH_DMA_REG_END 0x203d3028
-#define BCHP_BSPI_REG_START 0x203d3200
-#define BCHP_BSPI_REG_END 0x203d324c
-#define BCHP_BSPI_RAF_REG_START 0x203d3300
-#define BCHP_BSPI_RAF_REG_END 0x203d3320
-#define BCHP_HIF_MSPI_REG_START 0x203d3400
-#define BCHP_HIF_MSPI_REG_END 0x203d3584
-#define BCHP_BOOTSRAM_SECURE_REG_START 0x203e0000
-#define BCHP_BOOTSRAM_SECURE_REG_END 0x203efffc
-#define BCHP_ITCH0_REG_START 0x203f0000
-#define BCHP_ITCH0_REG_END 0x203f0000
-#define BCHP_HIF_SECURE_CTRL_REG_START 0x203f0400
-#define BCHP_HIF_SECURE_CTRL_REG_END 0x203f0400
-#define BCHP_HIF_SECURE_BSPI_REG_START 0x203f0500
-#define BCHP_HIF_SECURE_BSPI_REG_END 0x203f0500
-#define BCHP_HIF_SECURE_LR_SPI_REG_START 0x203f0600
-#define BCHP_HIF_SECURE_LR_SPI_REG_END 0x203f0600
-#define BCHP_NAND_SECURE_REG_START 0x203f0800
-#define BCHP_NAND_SECURE_REG_END 0x203f0800
-#define BCHP_HIF_SECURE_INDIRECT_MSPI_PIPE_REG_START 0x203f0c00
-#define BCHP_HIF_SECURE_INDIRECT_MSPI_PIPE_REG_END 0x203f0c00
-#define BCHP_CPUBIUARCH_SECURE_REG_START 0x203f0e00
-#define BCHP_CPUBIUARCH_SECURE_REG_END 0x203f0ffc
-#define BCHP_HIF_CONTINUATION_SECURE_REG_START 0x203f1000
-#define BCHP_HIF_CONTINUATION_SECURE_REG_END 0x203f1000
-#define BCHP_SUN_GISB_ARB_REG_START 0x20400000
-#define BCHP_SUN_GISB_ARB_REG_END 0x204007fc
-#define BCHP_SUN_GR_REG_START 0x20401000
-#define BCHP_SUN_GR_REG_END 0x2040100c
-#define BCHP_SSP_RG_REG_START 0x20401200
-#define BCHP_SSP_RG_REG_END 0x2040120c
-#define BCHP_SUN_RG_REG_START 0x20401400
-#define BCHP_SUN_RG_REG_END 0x2040140c
-#define BCHP_TPCAP_REG_START 0x20401800
-#define BCHP_TPCAP_REG_END 0x2040189c
-#define BCHP_SUN_L2_REG_START 0x20403000
-#define BCHP_SUN_L2_REG_END 0x20403044
-#define BCHP_SUN_TOP_CTRL_REG_START 0x20404000
-#define BCHP_SUN_TOP_CTRL_REG_END 0x20404518
-#define BCHP_IRB_REG_START 0x20406000
-#define BCHP_IRB_REG_END 0x20406138
-#define BCHP_GIO_REG_START 0x20406200
-#define BCHP_GIO_REG_END 0x2040629c
-#define BCHP_TIMER_REG_START 0x20406300
-#define BCHP_TIMER_REG_END 0x2040633c
-#define BCHP_BSCA_REG_START 0x20406400
-#define BCHP_BSCA_REG_END 0x20406454
-#define BCHP_BSCD_REG_START 0x20406500
-#define BCHP_BSCD_REG_END 0x20406554
-#define BCHP_BSCE_REG_START 0x20406600
-#define BCHP_BSCE_REG_END 0x20406654
-#define BCHP_PWM_REG_START 0x20406700
-#define BCHP_PWM_REG_END 0x20406724
-#define BCHP_PWMB_REG_START 0x20406780
-#define BCHP_PWMB_REG_END 0x204067a4
-#define BCHP_IRQ1_REG_START 0x20406800
-#define BCHP_IRQ1_REG_END 0x20406804
-#define BCHP_IRQ0_REG_START 0x20406840
-#define BCHP_IRQ0_REG_END 0x20406844
-#define BCHP_PM_REG_START 0x20406880
-#define BCHP_PM_REG_END 0x20406888
-#define BCHP_UARTA_REG_START 0x20406c00
-#define BCHP_UARTA_REG_END 0x20406c1c
-#define BCHP_UARTB_REG_START 0x20406c40
-#define BCHP_UARTB_REG_END 0x20406c5c
-#define BCHP_UARTC_REG_START 0x20406c80
-#define BCHP_UARTC_REG_END 0x20406c9c
-#define BCHP_SCA_REG_START 0x20407000
-#define BCHP_SCA_REG_END 0x204070bc
-#define BCHP_SCB_REG_START 0x20407100
-#define BCHP_SCB_REG_END 0x204071bc
-#define BCHP_SCIRQ1_REG_START 0x20407200
-#define BCHP_SCIRQ1_REG_END 0x20407204
-#define BCHP_SCIRQ0_REG_START 0x20407240
-#define BCHP_SCIRQ0_REG_END 0x20407244
-#define BCHP_SCIRQ_SCPU_REG_START 0x20407280
-#define BCHP_SCIRQ_SCPU_REG_END 0x20407284
-#define BCHP_CTK_REG_START 0x20407400
-#define BCHP_CTK_REG_END 0x20407578
-#define BCHP_MCIF_INTR2_REG_START 0x20407600
-#define BCHP_MCIF_INTR2_REG_END 0x20407644
-#define BCHP_MCIF_REG_START 0x20407680
-#define BCHP_MCIF_REG_END 0x204076a8
-#define BCHP_UPG_AUX_INTR2_REG_START 0x204076c0
-#define BCHP_UPG_AUX_INTR2_REG_END 0x204076ec
-#define BCHP_UPG_UART_DMA_REG_START 0x20407800
-#define BCHP_UPG_UART_DMA_REG_END 0x20407830
-#define BCHP_AON_CTRL_REG_START 0x20410000
-#define BCHP_AON_CTRL_REG_END 0x204103fc
-#define BCHP_AON_L2_REG_START 0x20410400
-#define BCHP_AON_L2_REG_END 0x2041042c
-#define BCHP_AON_PM_L2_REG_START 0x20410440
-#define BCHP_AON_PM_L2_REG_END 0x2041046c
-#define BCHP_AON_PM_BBM_L2_REG_START 0x20410480
-#define BCHP_AON_PM_BBM_L2_REG_END 0x204104ac
-#define BCHP_AON_PIN_CTRL_REG_START 0x20410500
-#define BCHP_AON_PIN_CTRL_REG_END 0x20410518
-#define BCHP_AON_HDMI_TX_REG_START 0x20410600
-#define BCHP_AON_HDMI_TX_REG_END 0x20410698
-#define BCHP_AON_HDMI_RX_REG_START 0x20410800
-#define BCHP_AON_HDMI_RX_REG_END 0x20410900
-#define BCHP_MSPI_REG_START 0x20411000
-#define BCHP_MSPI_REG_END 0x2041117c
-#define BCHP_GIO_AON_REG_START 0x20411200
-#define BCHP_GIO_AON_REG_END 0x2041123c
-#define BCHP_LDK_REG_START 0x20411300
-#define BCHP_LDK_REG_END 0x20411344
-#define BCHP_BSCB_REG_START 0x20411380
-#define BCHP_BSCB_REG_END 0x204113d4
-#define BCHP_BSCC_REG_START 0x20411400
-#define BCHP_BSCC_REG_END 0x20411454
-#define BCHP_IRQ1_AON_REG_START 0x20411480
-#define BCHP_IRQ1_AON_REG_END 0x20411484
-#define BCHP_IRQ0_AON_REG_START 0x204114c0
-#define BCHP_IRQ0_AON_REG_END 0x204114c4
-#define BCHP_ICAP_REG_START 0x20411500
-#define BCHP_ICAP_REG_END 0x2041153c
-#define BCHP_PM_AON_REG_START 0x20411540
-#define BCHP_PM_AON_REG_END 0x20411548
-#define BCHP_KBD1_REG_START 0x20411580
-#define BCHP_KBD1_REG_END 0x204115bc
-#define BCHP_KBD2_REG_START 0x204115c0
-#define BCHP_KBD2_REG_END 0x204115fc
-#define BCHP_KBD3_REG_START 0x20411600
-#define BCHP_KBD3_REG_END 0x2041163c
-#define BCHP_UPG_AUX_AON_INTR2_REG_START 0x20411800
-#define BCHP_UPG_AUX_AON_INTR2_REG_END 0x2041182c
-#define BCHP_WKTMR_REG_START 0x20411880
-#define BCHP_WKTMR_REG_END 0x20411890
-#define BCHP_BICAP_REG_START 0x204118c0
-#define BCHP_BICAP_REG_END 0x204118f8
-#define BCHP_CNTControlBase_REG_START 0x20414000
-#define BCHP_CNTControlBase_REG_END 0x20414ffc
-#define BCHP_CNTReadBase_REG_START 0x20416000
-#define BCHP_CNTReadBase_REG_END 0x20416ffc
-#define BCHP_AVS_CPU_PROG_MEM_REG_START 0x20420000
-#define BCHP_AVS_CPU_PROG_MEM_REG_END 0x20422ffc
-#define BCHP_AVS_CPU_DATA_MEM_REG_START 0x20424000
-#define BCHP_AVS_CPU_DATA_MEM_REG_END 0x20424bfc
-#define BCHP_AVS_CPU_CORE_REGS_REG_START 0x20428000
-#define BCHP_AVS_CPU_CORE_REGS_REG_END 0x204280fc
-#define BCHP_AVS_CPU_AUX_REGS_REG_START 0x2042a000
-#define BCHP_AVS_CPU_AUX_REGS_REG_END 0x2042b058
-#define BCHP_AVS_UART_REG_START 0x20430000
-#define BCHP_AVS_UART_REG_END 0x20430ffc
-#define BCHP_AVS_CPU_L2_REG_START 0x20431100
-#define BCHP_AVS_CPU_L2_REG_END 0x2043112c
-#define BCHP_AVS_HOST_L2_REG_START 0x20431200
-#define BCHP_AVS_HOST_L2_REG_END 0x2043122c
-#define BCHP_AVS_CPU_CTRL_REG_START 0x20431300
-#define BCHP_AVS_CPU_CTRL_REG_END 0x20431330
-#define BCHP_AVS_BSTI_REG_START 0x20431400
-#define BCHP_AVS_BSTI_REG_END 0x20431404
-#define BCHP_AVS_TOP_CTRL_REG_START 0x20431500
-#define BCHP_AVS_TOP_CTRL_REG_END 0x204315d0
-#define BCHP_AVS_HW_MNTR_1_REG_START 0x20432000
-#define BCHP_AVS_HW_MNTR_1_REG_END 0x204320c8
-#define BCHP_AVS_PVT_MNTR_CONFIG_1_REG_START 0x20432100
-#define BCHP_AVS_PVT_MNTR_CONFIG_1_REG_END 0x20432124
-#define BCHP_AVS_RO_REGISTERS_0_1_REG_START 0x20432200
-#define BCHP_AVS_RO_REGISTERS_0_1_REG_END 0x204322e0
-#define BCHP_AVS_RO_REGISTERS_1_1_REG_START 0x20432800
-#define BCHP_AVS_RO_REGISTERS_1_1_REG_END 0x20432934
-#define BCHP_AVS_ROSC_THRESHOLD_1_1_REG_START 0x20432d00
-#define BCHP_AVS_ROSC_THRESHOLD_1_1_REG_END 0x20432dfc
-#define BCHP_AVS_ROSC_THRESHOLD_2_1_REG_START 0x20432e00
-#define BCHP_AVS_ROSC_THRESHOLD_2_1_REG_END 0x20432efc
-#define BCHP_AVS_HW_MNTR_2_REG_START 0x20434000
-#define BCHP_AVS_HW_MNTR_2_REG_END 0x204340c8
-#define BCHP_AVS_PVT_MNTR_CONFIG_2_REG_START 0x20434100
-#define BCHP_AVS_PVT_MNTR_CONFIG_2_REG_END 0x20434124
-#define BCHP_AVS_RO_REGISTERS_0_2_REG_START 0x20434200
-#define BCHP_AVS_RO_REGISTERS_0_2_REG_END 0x204342e0
-#define BCHP_AVS_RO_REGISTERS_1_2_REG_START 0x20434800
-#define BCHP_AVS_RO_REGISTERS_1_2_REG_END 0x20434934
-#define BCHP_AVS_ROSC_THRESHOLD_1_2_REG_START 0x20434d00
-#define BCHP_AVS_ROSC_THRESHOLD_1_2_REG_END 0x20434dfc
-#define BCHP_AVS_ROSC_THRESHOLD_2_2_REG_START 0x20434e00
-#define BCHP_AVS_ROSC_THRESHOLD_2_2_REG_END 0x20434efc
-#define BCHP_AVS_PMB_S_000_REG_START 0x20438000
-#define BCHP_AVS_PMB_S_000_REG_END 0x20438024
-#define BCHP_AVS_PMB_S_001_REG_START 0x20438040
-#define BCHP_AVS_PMB_S_001_REG_END 0x20438064
-#define BCHP_AVS_PMB_S_002_REG_START 0x20438080
-#define BCHP_AVS_PMB_S_002_REG_END 0x204380a4
-#define BCHP_AVS_PMB_S_003_REG_START 0x204380c0
-#define BCHP_AVS_PMB_S_003_REG_END 0x204380e4
-#define BCHP_AVS_PMB_S_004_REG_START 0x20438100
-#define BCHP_AVS_PMB_S_004_REG_END 0x20438124
-#define BCHP_AVS_PMB_S_005_REG_START 0x20438140
-#define BCHP_AVS_PMB_S_005_REG_END 0x20438164
-#define BCHP_AVS_PMB_S_006_REG_START 0x20438180
-#define BCHP_AVS_PMB_S_006_REG_END 0x204381a4
-#define BCHP_AVS_PMB_S_007_REG_START 0x204381c0
-#define BCHP_AVS_PMB_S_007_REG_END 0x204381e4
-#define BCHP_AVS_PMB_S_008_REG_START 0x20438200
-#define BCHP_AVS_PMB_S_008_REG_END 0x20438224
-#define BCHP_AVS_PMB_S_009_REG_START 0x20438240
-#define BCHP_AVS_PMB_S_009_REG_END 0x20438264
-#define BCHP_AVS_PMB_S_010_REG_START 0x20438280
-#define BCHP_AVS_PMB_S_010_REG_END 0x204382a4
-#define BCHP_AVS_PMB_S_011_REG_START 0x204382c0
-#define BCHP_AVS_PMB_S_011_REG_END 0x204382e4
-#define BCHP_AVS_PMB_S_012_REG_START 0x20438300
-#define BCHP_AVS_PMB_S_012_REG_END 0x20438324
-#define BCHP_AVS_PMB_S_013_REG_START 0x20438340
-#define BCHP_AVS_PMB_S_013_REG_END 0x20438364
-#define BCHP_AVS_PMB_S_014_REG_START 0x20438380
-#define BCHP_AVS_PMB_S_014_REG_END 0x204383a4
-#define BCHP_AVS_PMB_S_015_REG_START 0x204383c0
-#define BCHP_AVS_PMB_S_015_REG_END 0x204383e4
-#define BCHP_AVS_PMB_S_016_REG_START 0x20438400
-#define BCHP_AVS_PMB_S_016_REG_END 0x20438424
-#define BCHP_AVS_PMB_S_017_REG_START 0x20438440
-#define BCHP_AVS_PMB_S_017_REG_END 0x20438464
-#define BCHP_AVS_PMB_S_018_REG_START 0x20438480
-#define BCHP_AVS_PMB_S_018_REG_END 0x204384a4
-#define BCHP_AVS_PMB_S_019_REG_START 0x204384c0
-#define BCHP_AVS_PMB_S_019_REG_END 0x204384e4
-#define BCHP_AVS_PMB_S_020_REG_START 0x20438500
-#define BCHP_AVS_PMB_S_020_REG_END 0x20438524
-#define BCHP_AVS_PMB_S_021_REG_START 0x20438540
-#define BCHP_AVS_PMB_S_021_REG_END 0x20438564
-#define BCHP_AVS_PMB_S_022_REG_START 0x20438580
-#define BCHP_AVS_PMB_S_022_REG_END 0x204385a4
-#define BCHP_AVS_PMB_S_023_REG_START 0x204385c0
-#define BCHP_AVS_PMB_S_023_REG_END 0x204385e4
-#define BCHP_AVS_PMB_S_024_REG_START 0x20438600
-#define BCHP_AVS_PMB_S_024_REG_END 0x20438624
-#define BCHP_AVS_PMB_S_025_REG_START 0x20438640
-#define BCHP_AVS_PMB_S_025_REG_END 0x20438664
-#define BCHP_AVS_PMB_S_026_REG_START 0x20438680
-#define BCHP_AVS_PMB_S_026_REG_END 0x204386a4
-#define BCHP_AVS_PMB_S_027_REG_START 0x204386c0
-#define BCHP_AVS_PMB_S_027_REG_END 0x204386e4
-#define BCHP_AVS_PMB_S_028_REG_START 0x20438700
-#define BCHP_AVS_PMB_S_028_REG_END 0x20438724
-#define BCHP_AVS_PMB_S_029_REG_START 0x20438740
-#define BCHP_AVS_PMB_S_029_REG_END 0x20438764
-#define BCHP_AVS_PMB_S_030_REG_START 0x20438780
-#define BCHP_AVS_PMB_S_030_REG_END 0x204387a4
-#define BCHP_AVS_PMB_S_031_REG_START 0x204387c0
-#define BCHP_AVS_PMB_S_031_REG_END 0x204387e4
-#define BCHP_AVS_PMB_S_032_REG_START 0x20438800
-#define BCHP_AVS_PMB_S_032_REG_END 0x20438824
-#define BCHP_AVS_PMB_S_033_REG_START 0x20438840
-#define BCHP_AVS_PMB_S_033_REG_END 0x20438864
-#define BCHP_AVS_PMB_S_034_REG_START 0x20438880
-#define BCHP_AVS_PMB_S_034_REG_END 0x204388a4
-#define BCHP_AVS_PMB_REGISTERS_REG_START 0x2043a000
-#define BCHP_AVS_PMB_REGISTERS_REG_END 0x2043a008
-#define BCHP_SYS_GISB_ARB_SEC_REG_START 0x20440000
-#define BCHP_SYS_GISB_ARB_SEC_REG_END 0x204407fc
-#define BCHP_SYS_TOP_CTRL_SEC_REG_START 0x20440800
-#define BCHP_SYS_TOP_CTRL_SEC_REG_END 0x20440804
-#define BCHP_AON_CTRL_SECURE_REG_START 0x20440900
-#define BCHP_AON_CTRL_SECURE_REG_END 0x2044097c
-#define BCHP_AVS_RANGE_BLOCKER_REG_START 0x20440a00
-#define BCHP_AVS_RANGE_BLOCKER_REG_END 0x20440a54
-#define BCHP_ROUTER_HIF_RGR_REG_START 0x20442000
-#define BCHP_ROUTER_HIF_RGR_REG_END 0x20442010
-#define BCHP_ROUTER_HIF_INTR2_REG_START 0x20442100
-#define BCHP_ROUTER_HIF_INTR2_REG_END 0x2044212c
-#define BCHP_ROUTER_HIF_IPI0_INTR2_REG_START 0x20442200
-#define BCHP_ROUTER_HIF_IPI0_INTR2_REG_END 0x2044222c
-#define BCHP_ROUTER_HIF_STB_IPI0_INTR2_REG_START 0x20442300
-#define BCHP_ROUTER_HIF_STB_IPI0_INTR2_REG_END 0x2044232c
-#define BCHP_ROUTER_HIF_CPU_INTR1_REG_START 0x20442400
-#define BCHP_ROUTER_HIF_CPU_INTR1_REG_END 0x2044243c
-#define BCHP_PCI_PCIE_INTR1_REG_START 0x20442500
-#define BCHP_PCI_PCIE_INTR1_REG_END 0x2044253c
-#define BCHP_ROUTER_CPUBIUARCH_REG_START 0x20442600
-#define BCHP_ROUTER_CPUBIUARCH_REG_END 0x204427fc
-#define BCHP_ROUTER_CPUBIUCTRL_REG_START 0x20442800
-#define BCHP_ROUTER_CPUBIUCTRL_REG_END 0x20442bfc
-#define BCHP_ROUTER_HIF_SCRATCH_REG_START 0x20442c00
-#define BCHP_ROUTER_HIF_SCRATCH_REG_END 0x20442c1c
-#define BCHP_ROUTER_HIF_TIMER_REG_START 0x20442d00
-#define BCHP_ROUTER_HIF_TIMER_REG_END 0x20442d3c
-#define BCHP_RG_PM_REG_START 0x20442e00
-#define BCHP_RG_PM_REG_END 0x20442e1c
-#define BCHP_PMBM_REG_START 0x20442f00
-#define BCHP_PMBM_REG_END 0x20442f0c
-#define BCHP_HIF_CONTINUATION_REG_START 0x20450000
-#define BCHP_HIF_CONTINUATION_REG_END 0x204500fc
-#define BCHP_RFM_SYSCLK_REG_START 0x2045a000
-#define BCHP_RFM_SYSCLK_REG_END 0x2045a124
-#define BCHP_RFM_CLK27_REG_START 0x2045a000
-#define BCHP_RFM_CLK27_REG_END 0x2045a470
-#define BCHP_RFM_L2_REG_START 0x2045ac00
-#define BCHP_RFM_L2_REG_END 0x2045ac2c
-#define BCHP_RFM_GRB_REG_START 0x2045b000
-#define BCHP_RFM_GRB_REG_END 0x2045b00c
-#define BCHP_PCIE_GISB_0_RC_CFG_TYPE1_REG_START 0x20460000
-#define BCHP_PCIE_GISB_0_RC_CFG_TYPE1_REG_END 0x2046003c
-#define BCHP_PCIE_GISB_0_RC_CFG_PM_REG_START 0x20460048
-#define BCHP_PCIE_GISB_0_RC_CFG_PM_REG_END 0x2046004c
-#define BCHP_PCIE_GISB_0_RC_CFG_PCIE_REG_START 0x204600ac
-#define BCHP_PCIE_GISB_0_RC_CFG_PCIE_REG_END 0x204600e4
-#define BCHP_PCIE_GISB_0_RC_CFG_AER_REG_START 0x20460100
-#define BCHP_PCIE_GISB_0_RC_CFG_AER_REG_END 0x20460134
-#define BCHP_PCIE_GISB_0_RC_CFG_VC_REG_START 0x20460160
-#define BCHP_PCIE_GISB_0_RC_CFG_VC_REG_END 0x20460178
-#define BCHP_PCIE_GISB_0_RC_CFG_VENDOR_REG_START 0x20460180
-#define BCHP_PCIE_GISB_0_RC_CFG_VENDOR_REG_END 0x204601a4
-#define BCHP_PCIE_GISB_0_RC_CFG_PRIV0_REG_START 0x20460404
-#define BCHP_PCIE_GISB_0_RC_CFG_PRIV0_REG_END 0x20460418
-#define BCHP_PCIE_GISB_0_RC_CFG_PRIV1_REG_START 0x20460428
-#define BCHP_PCIE_GISB_0_RC_CFG_PRIV1_REG_END 0x20460630
-#define BCHP_PCIE_GISB_0_RC_TL_REG_START 0x20460800
-#define BCHP_PCIE_GISB_0_RC_TL_REG_END 0x20460998
-#define BCHP_PCIE_GISB_0_RC_DL_REG_START 0x20461000
-#define BCHP_PCIE_GISB_0_RC_DL_REG_END 0x20461424
-#define BCHP_PCIE_GISB_0_RC_PL_REG_START 0x20461800
-#define BCHP_PCIE_GISB_0_RC_PL_REG_END 0x20461e1c
-#define BCHP_PCIE_GISB_0_EP_CFG_TYPE0_REG_START 0x20462000
-#define BCHP_PCIE_GISB_0_EP_CFG_TYPE0_REG_END 0x2046203c
-#define BCHP_PCIE_GISB_0_EP_CFG_PM_REG_START 0x20462048
-#define BCHP_PCIE_GISB_0_EP_CFG_PM_REG_END 0x2046204c
-#define BCHP_PCIE_GISB_0_EP_CFG_VPD_REG_START 0x20462050
-#define BCHP_PCIE_GISB_0_EP_CFG_VPD_REG_END 0x20462054
-#define BCHP_PCIE_GISB_0_EP_CFG_MSI_REG_START 0x20462058
-#define BCHP_PCIE_GISB_0_EP_CFG_MSI_REG_END 0x20462064
-#define BCHP_PCIE_GISB_0_EP_CFG_MSIX_REG_START 0x204620a0
-#define BCHP_PCIE_GISB_0_EP_CFG_MSIX_REG_END 0x204620a8
-#define BCHP_PCIE_GISB_0_EP_CFG_PCIE_REG_START 0x204620ac
-#define BCHP_PCIE_GISB_0_EP_CFG_PCIE_REG_END 0x204620e4
-#define BCHP_PCIE_GISB_0_EP_CFG_AER_REG_START 0x20462100
-#define BCHP_PCIE_GISB_0_EP_CFG_AER_REG_END 0x20462134
-#define BCHP_PCIE_GISB_0_EP_CFG_DEV_REG_START 0x2046213c
-#define BCHP_PCIE_GISB_0_EP_CFG_DEV_REG_END 0x20462144
-#define BCHP_PCIE_GISB_0_EP_CFG_PB_REG_START 0x20462150
-#define BCHP_PCIE_GISB_0_EP_CFG_PB_REG_END 0x2046215c
-#define BCHP_PCIE_GISB_0_EP_CFG_VC_REG_START 0x20462160
-#define BCHP_PCIE_GISB_0_EP_CFG_VC_REG_END 0x20462178
-#define BCHP_PCIE_GISB_0_EP_CFG_VENDOR_REG_START 0x20462180
-#define BCHP_PCIE_GISB_0_EP_CFG_VENDOR_REG_END 0x204621a4
-#define BCHP_PCIE_GISB_0_EP_CFG_PRIV0_REG_START 0x20462404
-#define BCHP_PCIE_GISB_0_EP_CFG_PRIV0_REG_END 0x20462418
-#define BCHP_PCIE_GISB_0_EP_CFG_PRIV1_REG_START 0x20462428
-#define BCHP_PCIE_GISB_0_EP_CFG_PRIV1_REG_END 0x20462630
-#define BCHP_PCIE_GISB_0_EP_TL_REG_START 0x20462800
-#define BCHP_PCIE_GISB_0_EP_TL_REG_END 0x20462998
-#define BCHP_PCIE_GISB_0_EP_DL_REG_START 0x20463000
-#define BCHP_PCIE_GISB_0_EP_DL_REG_END 0x20463424
-#define BCHP_PCIE_GISB_0_EP_PL_REG_START 0x20463800
-#define BCHP_PCIE_GISB_0_EP_PL_REG_END 0x20463e1c
-#define BCHP_PCIE_GISB_0_MISC_REG_START 0x20464000
-#define BCHP_PCIE_GISB_0_MISC_REG_END 0x204640c4
-#define BCHP_PCIE_GISB_0_MISC_PERST_REG_START 0x20464100
-#define BCHP_PCIE_GISB_0_MISC_PERST_REG_END 0x20464104
-#define BCHP_PCIE_GISB_0_MISC_HARD_REG_START 0x20464200
-#define BCHP_PCIE_GISB_0_MISC_HARD_REG_END 0x20464204
-#define BCHP_PCIE_GISB_0_INTR2_REG_START 0x20464300
-#define BCHP_PCIE_GISB_0_INTR2_REG_END 0x2046432c
-#define BCHP_PCIE_GISB_0_DMA_REG_START 0x20464400
-#define BCHP_PCIE_GISB_0_DMA_REG_END 0x2046446c
-#define BCHP_PCIE_GISB_0_EXT_CFG_REG_START 0x20468000
-#define BCHP_PCIE_GISB_0_EXT_CFG_REG_END 0x20469008
-#define BCHP_PCIE_GISB_0_RGR1_REG_START 0x20469200
-#define BCHP_PCIE_GISB_0_RGR1_REG_END 0x20469210
-#define BCHP_PCIE_GISB_0_RG_REG_START 0x20469300
-#define BCHP_PCIE_GISB_0_RG_REG_END 0x2046930c
-#define BCHP_PCIE_GISB_1_RC_CFG_TYPE1_REG_START 0x20470000
-#define BCHP_PCIE_GISB_1_RC_CFG_TYPE1_REG_END 0x2047003c
-#define BCHP_PCIE_GISB_1_RC_CFG_PM_REG_START 0x20470048
-#define BCHP_PCIE_GISB_1_RC_CFG_PM_REG_END 0x2047004c
-#define BCHP_PCIE_GISB_1_RC_CFG_PCIE_REG_START 0x204700ac
-#define BCHP_PCIE_GISB_1_RC_CFG_PCIE_REG_END 0x204700e4
-#define BCHP_PCIE_GISB_1_RC_CFG_AER_REG_START 0x20470100
-#define BCHP_PCIE_GISB_1_RC_CFG_AER_REG_END 0x20470134
-#define BCHP_PCIE_GISB_1_RC_CFG_VC_REG_START 0x20470160
-#define BCHP_PCIE_GISB_1_RC_CFG_VC_REG_END 0x20470178
-#define BCHP_PCIE_GISB_1_RC_CFG_VENDOR_REG_START 0x20470180
-#define BCHP_PCIE_GISB_1_RC_CFG_VENDOR_REG_END 0x204701a4
-#define BCHP_PCIE_GISB_1_RC_CFG_PRIV0_REG_START 0x20470404
-#define BCHP_PCIE_GISB_1_RC_CFG_PRIV0_REG_END 0x20470418
-#define BCHP_PCIE_GISB_1_RC_CFG_PRIV1_REG_START 0x20470428
-#define BCHP_PCIE_GISB_1_RC_CFG_PRIV1_REG_END 0x20470630
-#define BCHP_PCIE_GISB_1_RC_TL_REG_START 0x20470800
-#define BCHP_PCIE_GISB_1_RC_TL_REG_END 0x20470998
-#define BCHP_PCIE_GISB_1_RC_DL_REG_START 0x20471000
-#define BCHP_PCIE_GISB_1_RC_DL_REG_END 0x20471424
-#define BCHP_PCIE_GISB_1_RC_PL_REG_START 0x20471800
-#define BCHP_PCIE_GISB_1_RC_PL_REG_END 0x20471e1c
-#define BCHP_PCIE_GISB_1_EP_CFG_TYPE0_REG_START 0x20472000
-#define BCHP_PCIE_GISB_1_EP_CFG_TYPE0_REG_END 0x2047203c
-#define BCHP_PCIE_GISB_1_EP_CFG_PM_REG_START 0x20472048
-#define BCHP_PCIE_GISB_1_EP_CFG_PM_REG_END 0x2047204c
-#define BCHP_PCIE_GISB_1_EP_CFG_VPD_REG_START 0x20472050
-#define BCHP_PCIE_GISB_1_EP_CFG_VPD_REG_END 0x20472054
-#define BCHP_PCIE_GISB_1_EP_CFG_MSI_REG_START 0x20472058
-#define BCHP_PCIE_GISB_1_EP_CFG_MSI_REG_END 0x20472064
-#define BCHP_PCIE_GISB_1_EP_CFG_MSIX_REG_START 0x204720a0
-#define BCHP_PCIE_GISB_1_EP_CFG_MSIX_REG_END 0x204720a8
-#define BCHP_PCIE_GISB_1_EP_CFG_PCIE_REG_START 0x204720ac
-#define BCHP_PCIE_GISB_1_EP_CFG_PCIE_REG_END 0x204720e4
-#define BCHP_PCIE_GISB_1_EP_CFG_AER_REG_START 0x20472100
-#define BCHP_PCIE_GISB_1_EP_CFG_AER_REG_END 0x20472134
-#define BCHP_PCIE_GISB_1_EP_CFG_DEV_REG_START 0x2047213c
-#define BCHP_PCIE_GISB_1_EP_CFG_DEV_REG_END 0x20472144
-#define BCHP_PCIE_GISB_1_EP_CFG_PB_REG_START 0x20472150
-#define BCHP_PCIE_GISB_1_EP_CFG_PB_REG_END 0x2047215c
-#define BCHP_PCIE_GISB_1_EP_CFG_VC_REG_START 0x20472160
-#define BCHP_PCIE_GISB_1_EP_CFG_VC_REG_END 0x20472178
-#define BCHP_PCIE_GISB_1_EP_CFG_VENDOR_REG_START 0x20472180
-#define BCHP_PCIE_GISB_1_EP_CFG_VENDOR_REG_END 0x204721a4
-#define BCHP_PCIE_GISB_1_EP_CFG_PRIV0_REG_START 0x20472404
-#define BCHP_PCIE_GISB_1_EP_CFG_PRIV0_REG_END 0x20472418
-#define BCHP_PCIE_GISB_1_EP_CFG_PRIV1_REG_START 0x20472428
-#define BCHP_PCIE_GISB_1_EP_CFG_PRIV1_REG_END 0x20472630
-#define BCHP_PCIE_GISB_1_EP_TL_REG_START 0x20472800
-#define BCHP_PCIE_GISB_1_EP_TL_REG_END 0x20472998
-#define BCHP_PCIE_GISB_1_EP_DL_REG_START 0x20473000
-#define BCHP_PCIE_GISB_1_EP_DL_REG_END 0x20473424
-#define BCHP_PCIE_GISB_1_EP_PL_REG_START 0x20473800
-#define BCHP_PCIE_GISB_1_EP_PL_REG_END 0x20473e1c
-#define BCHP_PCIE_GISB_1_MISC_REG_START 0x20474000
-#define BCHP_PCIE_GISB_1_MISC_REG_END 0x204740c4
-#define BCHP_PCIE_GISB_1_MISC_PERST_REG_START 0x20474100
-#define BCHP_PCIE_GISB_1_MISC_PERST_REG_END 0x20474104
-#define BCHP_PCIE_GISB_1_MISC_HARD_REG_START 0x20474200
-#define BCHP_PCIE_GISB_1_MISC_HARD_REG_END 0x20474204
-#define BCHP_PCIE_GISB_1_INTR2_REG_START 0x20474300
-#define BCHP_PCIE_GISB_1_INTR2_REG_END 0x2047432c
-#define BCHP_PCIE_GISB_1_DMA_REG_START 0x20474400
-#define BCHP_PCIE_GISB_1_DMA_REG_END 0x2047446c
-#define BCHP_PCIE_GISB_1_EXT_CFG_REG_START 0x20478000
-#define BCHP_PCIE_GISB_1_EXT_CFG_REG_END 0x20479008
-#define BCHP_PCIE_GISB_1_RGR1_REG_START 0x20479200
-#define BCHP_PCIE_GISB_1_RGR1_REG_END 0x20479210
-#define BCHP_PCIE_GISB_1_RG_REG_START 0x20479300
-#define BCHP_PCIE_GISB_1_RG_REG_END 0x2047930c
-#define BCHP_G2U_REGS_REG_START 0x2047a000
-#define BCHP_G2U_REGS_REG_END 0x2047a030
-#define BCHP_CLKGEN_REG_START 0x20480000
-#define BCHP_CLKGEN_REG_END 0x204808bc
-#define BCHP_VCXO_0_RM_REG_START 0x20482800
-#define BCHP_VCXO_0_RM_REG_END 0x2048282c
-#define BCHP_VCXO_1_RM_REG_START 0x20482880
-#define BCHP_VCXO_1_RM_REG_END 0x204828ac
-#define BCHP_VCXO_2_RM_REG_START 0x20482900
-#define BCHP_VCXO_2_RM_REG_END 0x2048292c
-#define BCHP_CLKGEN_GR_REG_START 0x20483000
-#define BCHP_CLKGEN_GR_REG_END 0x2048300c
-#define BCHP_PROD_OTP_GRB_REG_START 0x204e6000
-#define BCHP_PROD_OTP_GRB_REG_END 0x204e600c
-#define BCHP_JTAG_OTP_REG_START 0x204e6100
-#define BCHP_JTAG_OTP_REG_END 0x204e6158
-#define BCHP_MFD_0_REG_START 0x20600000
-#define BCHP_MFD_0_REG_END 0x20600264
-#define BCHP_MFD_1_REG_START 0x20600400
-#define BCHP_MFD_1_REG_END 0x206005fc
-#define BCHP_MFD_2_REG_START 0x20600800
-#define BCHP_MFD_2_REG_END 0x206009fc
-#define BCHP_MFD_3_REG_START 0x20600c00
-#define BCHP_MFD_3_REG_END 0x20600dfc
-#define BCHP_VFD_0_REG_START 0x20602000
-#define BCHP_VFD_0_REG_END 0x206021fc
-#define BCHP_VFD_1_REG_START 0x20602200
-#define BCHP_VFD_1_REG_END 0x206023fc
-#define BCHP_VFD_2_REG_START 0x20602400
-#define BCHP_VFD_2_REG_END 0x206025fc
-#define BCHP_VFD_3_REG_START 0x20602600
-#define BCHP_VFD_3_REG_END 0x206027fc
-#define BCHP_VFD_4_REG_START 0x20602800
-#define BCHP_VFD_4_REG_END 0x206029fc
-#define BCHP_VFD_5_REG_START 0x20602a00
-#define BCHP_VFD_5_REG_END 0x20602bfc
-#define BCHP_VFD_6_REG_START 0x20602c00
-#define BCHP_VFD_6_REG_END 0x20602dfc
-#define BCHP_VFD_7_REG_START 0x20602e00
-#define BCHP_VFD_7_REG_END 0x20602ffc
-#define BCHP_RDC_REG_START 0x20603000
-#define BCHP_RDC_REG_END 0x20603cfc
-#define BCHP_BVNF_INTR2_0_REG_START 0x20604000
-#define BCHP_BVNF_INTR2_0_REG_END 0x2060402c
-#define BCHP_BVNF_INTR2_1_REG_START 0x20604100
-#define BCHP_BVNF_INTR2_1_REG_END 0x2060412c
-#define BCHP_BVNF_INTR2_3_REG_START 0x20604300
-#define BCHP_BVNF_INTR2_3_REG_END 0x2060432c
-#define BCHP_BVNF_INTR2_4_REG_START 0x20604400
-#define BCHP_BVNF_INTR2_4_REG_END 0x2060442c
-#define BCHP_BVNF_INTR2_5_REG_START 0x20604500
-#define BCHP_BVNF_INTR2_5_REG_END 0x2060452c
-#define BCHP_BVNF_INTR2_6_REG_START 0x20604600
-#define BCHP_BVNF_INTR2_6_REG_END 0x2060462c
-#define BCHP_BVNF_INTR2_7_REG_START 0x20604700
-#define BCHP_BVNF_INTR2_7_REG_END 0x2060472c
-#define BCHP_BVNF_INTR2_9_REG_START 0x20604900
-#define BCHP_BVNF_INTR2_9_REG_END 0x2060492c
-#define BCHP_BVNF_INTR2_12_REG_START 0x20604c00
-#define BCHP_BVNF_INTR2_12_REG_END 0x20604c2c
-#define BCHP_BVNF_INTR2_15_REG_START 0x20604f00
-#define BCHP_BVNF_INTR2_15_REG_END 0x20604f2c
-#define BCHP_FMISC_REG_START 0x20605000
-#define BCHP_FMISC_REG_END 0x20605020
-#define BCHP_SCL_0_REG_START 0x20620000
-#define BCHP_SCL_0_REG_END 0x206203fc
-#define BCHP_SCL_1_REG_START 0x20620400
-#define BCHP_SCL_1_REG_END 0x206207fc
-#define BCHP_SCL_2_REG_START 0x20620800
-#define BCHP_SCL_2_REG_END 0x20620bfc
-#define BCHP_SCL_3_REG_START 0x20620c00
-#define BCHP_SCL_3_REG_END 0x20620ffc
-#define BCHP_SCL_4_REG_START 0x20621000
-#define BCHP_SCL_4_REG_END 0x206213fc
-#define BCHP_SCL_5_REG_START 0x20621400
-#define BCHP_SCL_5_REG_END 0x206217fc
-#define BCHP_SCL_6_REG_START 0x20621800
-#define BCHP_SCL_6_REG_END 0x20621bfc
-#define BCHP_SCL_7_REG_START 0x20621c00
-#define BCHP_SCL_7_REG_END 0x20621ffc
-#define BCHP_VNET_F_REG_START 0x20622000
-#define BCHP_VNET_F_REG_END 0x206221fc
-#define BCHP_VNET_B_REG_START 0x20622200
-#define BCHP_VNET_B_REG_END 0x206223fc
-#define BCHP_MMISC_REG_START 0x20622800
-#define BCHP_MMISC_REG_END 0x20622820
-#define BCHP_LBOX_0_REG_START 0x20624000
-#define BCHP_LBOX_0_REG_END 0x20624070
-#define BCHP_LBOX_1_REG_START 0x20624200
-#define BCHP_LBOX_1_REG_END 0x20624270
-#define BCHP_LBOX_2_REG_START 0x20624400
-#define BCHP_LBOX_2_REG_END 0x20624470
-#define BCHP_LBOX_3_REG_START 0x20624600
-#define BCHP_LBOX_3_REG_END 0x20624670
-#define BCHP_DNR_0_REG_START 0x20626000
-#define BCHP_DNR_0_REG_END 0x206260a4
-#define BCHP_DNR_1_REG_START 0x20626200
-#define BCHP_DNR_1_REG_END 0x206262a4
-#define BCHP_DNR_2_REG_START 0x20626400
-#define BCHP_DNR_2_REG_END 0x206264a4
-#define BCHP_DNR_3_REG_START 0x20626600
-#define BCHP_DNR_3_REG_END 0x206266a4
-#define BCHP_BVNM_INTR2_0_REG_START 0x20627000
-#define BCHP_BVNM_INTR2_0_REG_END 0x2062702c
-#define BCHP_BVNM_INTR2_1_REG_START 0x20627100
-#define BCHP_BVNM_INTR2_1_REG_END 0x2062712c
-#define BCHP_CAP_0_REG_START 0x20640000
-#define BCHP_CAP_0_REG_END 0x2064007c
-#define BCHP_CAP_1_REG_START 0x20640200
-#define BCHP_CAP_1_REG_END 0x2064027c
-#define BCHP_CAP_2_REG_START 0x20640400
-#define BCHP_CAP_2_REG_END 0x2064047c
-#define BCHP_CAP_3_REG_START 0x20640600
-#define BCHP_CAP_3_REG_END 0x2064067c
-#define BCHP_CAP_4_REG_START 0x20640800
-#define BCHP_CAP_4_REG_END 0x2064087c
-#define BCHP_CAP_5_REG_START 0x20640a00
-#define BCHP_CAP_5_REG_END 0x20640a7c
-#define BCHP_CAP_6_REG_START 0x20640c00
-#define BCHP_CAP_6_REG_END 0x20640c7c
-#define BCHP_CAP_7_REG_START 0x20640e00
-#define BCHP_CAP_7_REG_END 0x20640e7c
-#define BCHP_GFD_0_REG_START 0x20641000
-#define BCHP_GFD_0_REG_END 0x2064122c
-#define BCHP_GFD_1_REG_START 0x20641400
-#define BCHP_GFD_1_REG_END 0x2064162c
-#define BCHP_GFD_2_REG_START 0x20641800
-#define BCHP_GFD_2_REG_END 0x20641a2c
-#define BCHP_GFD_3_REG_START 0x20641c00
-#define BCHP_GFD_3_REG_END 0x20641e2c
-#define BCHP_GFD_4_REG_START 0x20642000
-#define BCHP_GFD_4_REG_END 0x2064222c
-#define BCHP_GFD_5_REG_START 0x20642400
-#define BCHP_GFD_5_REG_END 0x2064262c
-#define BCHP_CMP_0_REG_START 0x20643000
-#define BCHP_CMP_0_REG_END 0x206434b4
-#define BCHP_CMP_1_REG_START 0x20643800
-#define BCHP_CMP_1_REG_END 0x20643cb4
-#define BCHP_CMP_2_REG_START 0x20644000
-#define BCHP_CMP_2_REG_END 0x20644264
-#define BCHP_CMP_3_REG_START 0x20644400
-#define BCHP_CMP_3_REG_END 0x20644664
-#define BCHP_CMP_4_REG_START 0x20644800
-#define BCHP_CMP_4_REG_END 0x20644a64
-#define BCHP_CMP_5_REG_START 0x20644c00
-#define BCHP_CMP_5_REG_END 0x20644e64
-#define BCHP_TNT_CMP_0_V0_REG_START 0x20645800
-#define BCHP_TNT_CMP_0_V0_REG_END 0x206458a4
-#define BCHP_MASK_0_REG_START 0x20645c00
-#define BCHP_MASK_0_REG_END 0x20645c20
-#define BCHP_PEP_CMP_0_V0_REG_START 0x20646000
-#define BCHP_PEP_CMP_0_V0_REG_END 0x20647484
-#define BCHP_BVNB_INTR2_REG_START 0x20648000
-#define BCHP_BVNB_INTR2_REG_END 0x2064802c
-#define BCHP_BMISC_REG_START 0x20648400
-#define BCHP_BMISC_REG_END 0x20648420
-#define BCHP_MVP_TOP_0_REG_START 0x20660000
-#define BCHP_MVP_TOP_0_REG_END 0x2066002c
-#define BCHP_SIOB_0_REG_START 0x20660200
-#define BCHP_SIOB_0_REG_END 0x206602fc
-#define BCHP_HSCL_0_REG_START 0x20660400
-#define BCHP_HSCL_0_REG_END 0x206607fc
-#define BCHP_HD_ANR_MCTF_0_REG_START 0x20661000
-#define BCHP_HD_ANR_MCTF_0_REG_END 0x2066127c
-#define BCHP_HD_ANR_AND_0_REG_START 0x20661800
-#define BCHP_HD_ANR_AND_0_REG_END 0x20661888
-#define BCHP_MDI_TOP_0_REG_START 0x20662000
-#define BCHP_MDI_TOP_0_REG_END 0x206620fc
-#define BCHP_MDI_FCB_0_REG_START 0x20662400
-#define BCHP_MDI_FCB_0_REG_END 0x206627fc
-#define BCHP_MDI_PPB_0_REG_START 0x20662800
-#define BCHP_MDI_PPB_0_REG_END 0x20662bfc
-#define BCHP_MDI_FCN_0_REG_START 0x20662c00
-#define BCHP_MDI_FCN_0_REG_END 0x20662ffc
-#define BCHP_MVP_TOP_1_REG_START 0x20670000
-#define BCHP_MVP_TOP_1_REG_END 0x2067002c
-#define BCHP_SIOB_1_REG_START 0x20670200
-#define BCHP_SIOB_1_REG_END 0x206702fc
-#define BCHP_HSCL_1_REG_START 0x20670400
-#define BCHP_HSCL_1_REG_END 0x206707fc
-#define BCHP_MDI_TOP_1_REG_START 0x20672000
-#define BCHP_MDI_TOP_1_REG_END 0x206720fc
-#define BCHP_MDI_PPB_1_REG_START 0x20672800
-#define BCHP_MDI_PPB_1_REG_END 0x20672bfc
-#define BCHP_MDI_FCN_1_REG_START 0x20672c00
-#define BCHP_MDI_FCN_1_REG_END 0x20672ffc
-#define BCHP_MVP_TOP_2_REG_START 0x20680000
-#define BCHP_MVP_TOP_2_REG_END 0x2068002c
-#define BCHP_SIOB_2_REG_START 0x20680200
-#define BCHP_SIOB_2_REG_END 0x206802fc
-#define BCHP_HSCL_2_REG_START 0x20680400
-#define BCHP_HSCL_2_REG_END 0x206807fc
-#define BCHP_MDI_TOP_2_REG_START 0x20682000
-#define BCHP_MDI_TOP_2_REG_END 0x206820fc
-#define BCHP_MDI_PPB_2_REG_START 0x20682800
-#define BCHP_MDI_PPB_2_REG_END 0x20682bfc
-#define BCHP_MDI_FCN_2_REG_START 0x20682c00
-#define BCHP_MDI_FCN_2_REG_END 0x20682ffc
-#define BCHP_MVP_TOP_3_REG_START 0x20690000
-#define BCHP_MVP_TOP_3_REG_END 0x2069002c
-#define BCHP_SIOB_3_REG_START 0x20690200
-#define BCHP_SIOB_3_REG_END 0x206902fc
-#define BCHP_HSCL_3_REG_START 0x20690400
-#define BCHP_HSCL_3_REG_END 0x206907fc
-#define BCHP_MDI_TOP_3_REG_START 0x20692000
-#define BCHP_MDI_TOP_3_REG_END 0x206920fc
-#define BCHP_MDI_PPB_3_REG_START 0x20692800
-#define BCHP_MDI_PPB_3_REG_END 0x20692bfc
-#define BCHP_MDI_FCN_3_REG_START 0x20692c00
-#define BCHP_MDI_FCN_3_REG_END 0x20692ffc
-#define BCHP_MVP_TOP_4_REG_START 0x206a0000
-#define BCHP_MVP_TOP_4_REG_END 0x206a002c
-#define BCHP_SIOB_4_REG_START 0x206a0200
-#define BCHP_SIOB_4_REG_END 0x206a02fc
-#define BCHP_HSCL_4_REG_START 0x206a0400
-#define BCHP_HSCL_4_REG_END 0x206a07fc
-#define BCHP_MDI_TOP_4_REG_START 0x206a2000
-#define BCHP_MDI_TOP_4_REG_END 0x206a20fc
-#define BCHP_MDI_PPB_4_REG_START 0x206a2800
-#define BCHP_MDI_PPB_4_REG_END 0x206a2bfc
-#define BCHP_MDI_FCN_4_REG_START 0x206a2c00
-#define BCHP_MDI_FCN_4_REG_END 0x206a2ffc
-#define BCHP_MISC_REG_START 0x206b0000
-#define BCHP_MISC_REG_END 0x206b00a8
-#define BCHP_IT_0_REG_START 0x206b1000
-#define BCHP_IT_0_REG_END 0x206b17fc
-#define BCHP_IT_1_REG_START 0x206b2000
-#define BCHP_IT_1_REG_END 0x206b27fc
-#define BCHP_VF_0_REG_START 0x206b3000
-#define BCHP_VF_0_REG_END 0x206b3134
-#define BCHP_VF_1_REG_START 0x206b3200
-#define BCHP_VF_1_REG_END 0x206b3334
-#define BCHP_SECAM_0_REG_START 0x206b3400
-#define BCHP_SECAM_0_REG_END 0x206b3414
-#define BCHP_SM_0_REG_START 0x206b3480
-#define BCHP_SM_0_REG_END 0x206b34ac
-#define BCHP_SDSRC_0_REG_START 0x206b3500
-#define BCHP_SDSRC_0_REG_END 0x206b350c
-#define BCHP_HDSRC_0_REG_START 0x206b3520
-#define BCHP_HDSRC_0_REG_END 0x206b353c
-#define BCHP_CSC_0_REG_START 0x206b3580
-#define BCHP_CSC_0_REG_END 0x206b35b0
-#define BCHP_CSC_1_REG_START 0x206b3600
-#define BCHP_CSC_1_REG_END 0x206b3630
-#define BCHP_RM_0_REG_START 0x206b3680
-#define BCHP_RM_0_REG_END 0x206b36a4
-#define BCHP_RM_1_REG_START 0x206b36c0
-#define BCHP_RM_1_REG_END 0x206b36e4
-#define BCHP_ANA_DEBUG_0_REG_START 0x206b3700
-#define BCHP_ANA_DEBUG_0_REG_END 0x206b3744
-#define BCHP_DTRAM_0_REG_START 0x206b3800
-#define BCHP_DTRAM_0_REG_END 0x206b3e7c
-#define BCHP_DVI_DTG_0_REG_START 0x206b4000
-#define BCHP_DVI_DTG_0_REG_END 0x206b4178
-#define BCHP_DVI_DTG_RM_0_REG_START 0x206b4800
-#define BCHP_DVI_DTG_RM_0_REG_END 0x206b4824
-#define BCHP_DVI_CSC_0_REG_START 0x206b4900
-#define BCHP_DVI_CSC_0_REG_END 0x206b4930
-#define BCHP_DVI_DVF_0_REG_START 0x206b4a00
-#define BCHP_DVI_DVF_0_REG_END 0x206b4a18
-#define BCHP_DVI_DEBUG_0_REG_START 0x206b4b00
-#define BCHP_DVI_DEBUG_0_REG_END 0x206b4b44
-#define BCHP_ITU656_DTG_0_REG_START 0x206b5000
-#define BCHP_ITU656_DTG_0_REG_END 0x206b5178
-#define BCHP_ITU656_CSC_0_REG_START 0x206b5200
-#define BCHP_ITU656_CSC_0_REG_END 0x206b5230
-#define BCHP_ITU656_DVF_0_REG_START 0x206b5300
-#define BCHP_ITU656_DVF_0_REG_END 0x206b5318
-#define BCHP_ITU656_0_REG_START 0x206b5400
-#define BCHP_ITU656_0_REG_END 0x206b5420
-#define BCHP_VEC_CFG_REG_START 0x206b5800
-#define BCHP_VEC_CFG_REG_END 0x206b5984
-#define BCHP_VIDEO_ENC_INTR2_REG_START 0x206b5c00
-#define BCHP_VIDEO_ENC_INTR2_REG_END 0x206b5c2c
-#define BCHP_VIDEO_ENC_TPG_0_REG_START 0x206b5d00
-#define BCHP_VIDEO_ENC_TPG_0_REG_END 0x206b5d18
-#define BCHP_VIDEO_ENC_STG_0_REG_START 0x206b5e00
-#define BCHP_VIDEO_ENC_STG_0_REG_END 0x206b5e48
-#define BCHP_VIDEO_ENC_STG_1_REG_START 0x206b5f00
-#define BCHP_VIDEO_ENC_STG_1_REG_END 0x206b5f48
-#define BCHP_VIDEO_ENC_STG_2_REG_START 0x206b6000
-#define BCHP_VIDEO_ENC_STG_2_REG_END 0x206b6048
-#define BCHP_VIDEO_ENC_STG_3_REG_START 0x206b6100
-#define BCHP_VIDEO_ENC_STG_3_REG_END 0x206b6148
-#define BCHP_DSCL_0_REG_START 0x206b6800
-#define BCHP_DSCL_0_REG_END 0x206b6bfc
-#define BCHP_VIDEO_ENC_DECIM_0_REG_START 0x206b7000
-#define BCHP_VIDEO_ENC_DECIM_0_REG_END 0x206b7008
-#define BCHP_DVP_TVG_0_REG_START 0x206b7100
-#define BCHP_DVP_TVG_0_REG_END 0x206b7188
-#define BCHP_VBI_ENC_REG_START 0x206b8000
-#define BCHP_VBI_ENC_REG_END 0x206b8074
-#define BCHP_CCE_0_REG_START 0x206b8400
-#define BCHP_CCE_0_REG_END 0x206b8458
-#define BCHP_CCE_1_REG_START 0x206b8500
-#define BCHP_CCE_1_REG_END 0x206b8558
-#define BCHP_WSE_0_REG_START 0x206b8600
-#define BCHP_WSE_0_REG_END 0x206b8614
-#define BCHP_WSE_1_REG_START 0x206b8700
-#define BCHP_WSE_1_REG_END 0x206b8714
-#define BCHP_CGMSAE_0_REG_START 0x206b8800
-#define BCHP_CGMSAE_0_REG_END 0x206b8858
-#define BCHP_CGMSAE_1_REG_START 0x206b8900
-#define BCHP_CGMSAE_1_REG_END 0x206b8958
-#define BCHP_TTE_0_REG_START 0x206b8a00
-#define BCHP_TTE_0_REG_END 0x206b8a28
-#define BCHP_TTE_1_REG_START 0x206b8b00
-#define BCHP_TTE_1_REG_END 0x206b8b28
-#define BCHP_GSE_0_REG_START 0x206b8c00
-#define BCHP_GSE_0_REG_END 0x206b8c80
-#define BCHP_GSE_1_REG_START 0x206b8d00
-#define BCHP_GSE_1_REG_END 0x206b8d80
-#define BCHP_AMOLE_0_REG_START 0x206b8e00
-#define BCHP_AMOLE_0_REG_END 0x206b8e8c
-#define BCHP_AMOLE_1_REG_START 0x206b8f00
-#define BCHP_AMOLE_1_REG_END 0x206b8f8c
-#define BCHP_CCE_ANCIL_0_REG_START 0x206b9000
-#define BCHP_CCE_ANCIL_0_REG_END 0x206b9054
-#define BCHP_WSE_ANCIL_0_REG_START 0x206b9100
-#define BCHP_WSE_ANCIL_0_REG_END 0x206b910c
-#define BCHP_TTE_ANCIL_0_REG_START 0x206b9200
-#define BCHP_TTE_ANCIL_0_REG_END 0x206b9228
-#define BCHP_GSE_ANCIL_0_REG_START 0x206b9300
-#define BCHP_GSE_ANCIL_0_REG_END 0x206b9380
-#define BCHP_AMOLE_ANCIL_0_REG_START 0x206b9400
-#define BCHP_AMOLE_ANCIL_0_REG_END 0x206b948c
-#define BCHP_ANCI656_ANCIL_0_REG_START 0x206b9500
-#define BCHP_ANCI656_ANCIL_0_REG_END 0x206b9524
-#define BCHP_DVP_HR_REG_START 0x206c0000
-#define BCHP_DVP_HR_REG_END 0x206c03fc
-#define BCHP_DVP_HR_INTR2_REG_START 0x206c0400
-#define BCHP_DVP_HR_INTR2_REG_END 0x206c042c
-#define BCHP_DVP_HR_KEY_RAM_REG_START 0x206c0600
-#define BCHP_DVP_HR_KEY_RAM_REG_END 0x206c0614
-#define BCHP_HDMI_RX_FE_SHARED_REG_START 0x206c0800
-#define BCHP_HDMI_RX_FE_SHARED_REG_END 0x206c090c
-#define BCHP_HDMI_RX_SHARED_REG_START 0x206c0c00
-#define BCHP_HDMI_RX_SHARED_REG_END 0x206c0c24
-#define BCHP_HDMI_RX_FE_0_REG_START 0x206c1000
-#define BCHP_HDMI_RX_FE_0_REG_END 0x206c11fc
-#define BCHP_HDMI_RX_EQ_0_REG_START 0x206c1200
-#define BCHP_HDMI_RX_EQ_0_REG_END 0x206c13fc
-#define BCHP_HDMI_RX_0_REG_START 0x206c2000
-#define BCHP_HDMI_RX_0_REG_END 0x206c27bc
-#define BCHP_HDMI_RX_INTR2_0_REG_START 0x206c27c0
-#define BCHP_HDMI_RX_INTR2_0_REG_END 0x206c27ec
-#define BCHP_HD_DVI_0_REG_START 0x206c4000
-#define BCHP_HD_DVI_0_REG_END 0x206c41fc
-#define BCHP_DVP_HR_TMR_REG_START 0x206c4cc0
-#define BCHP_DVP_HR_TMR_REG_END 0x206c4cfc
-#define BCHP_DVP_HT_REG_START 0x206c8000
-#define BCHP_DVP_HT_REG_END 0x206c8118
-#define BCHP_HDMI_REG_START 0x206c8800
-#define BCHP_HDMI_REG_END 0x206c8994
-#define BCHP_HDMI_TX_PHY_REG_START 0x206c8a80
-#define BCHP_HDMI_TX_PHY_REG_END 0x206c8ae0
-#define BCHP_HDMI_RM_REG_START 0x206c8b00
-#define BCHP_HDMI_RM_REG_END 0x206c8b2c
-#define BCHP_HDMI_TX_INTR2_REG_START 0x206c8b40
-#define BCHP_HDMI_TX_INTR2_REG_END 0x206c8b6c
-#define BCHP_HDMI_RAM_REG_START 0x206c8c00
-#define BCHP_HDMI_RAM_REG_END 0x206c8dfc
-#define BCHP_BVN_RGR_REG_START 0x206ce000
-#define BCHP_BVN_RGR_REG_END 0x206ce010
-#define BCHP_VICE2_CME_0_0_REG_START 0x20700800
-#define BCHP_VICE2_CME_0_0_REG_END 0x207008a0
-#define BCHP_VICE2_FME_0_0_REG_START 0x20700c00
-#define BCHP_VICE2_FME_0_0_REG_END 0x20700c88
-#define BCHP_VICE2_MC_0_0_REG_START 0x20701000
-#define BCHP_VICE2_MC_0_0_REG_END 0x2070108c
-#define BCHP_VICE2_MAU_0_0_REG_START 0x20701400
-#define BCHP_VICE2_MAU_0_0_REG_END 0x20701510
-#define BCHP_VICE2_IMD_0_0_REG_START 0x20701800
-#define BCHP_VICE2_IMD_0_0_REG_END 0x2070187c
-#define BCHP_VICE2_CABAC_0_0_REG_START 0x20701c00
-#define BCHP_VICE2_CABAC_0_0_REG_END 0x20701dec
-#define BCHP_VICE2_HA_0_0_REG_START 0x20702000
-#define BCHP_VICE2_HA_0_0_REG_END 0x2070208c
-#define BCHP_VICE2_SG_0_0_REG_START 0x20702400
-#define BCHP_VICE2_SG_0_0_REG_END 0x207024ac
-#define BCHP_VICE2_DBLK_0_0_REG_START 0x20702800
-#define BCHP_VICE2_DBLK_0_0_REG_END 0x2070288c
-#define BCHP_VICE2_VIP_0_0_REG_START 0x20703000
-#define BCHP_VICE2_VIP_0_0_REG_END 0x20703224
-#define BCHP_VICE2_VIP1_0_0_REG_START 0x20703800
-#define BCHP_VICE2_VIP1_0_0_REG_END 0x20703a24
-#define BCHP_VICE2_XQ_0_0_REG_START 0x20704000
-#define BCHP_VICE2_XQ_0_0_REG_END 0x207054c8
-#define BCHP_VICE2_ARCSS_ESS_ADI_0_0_REG_START 0x20718000
-#define BCHP_VICE2_ARCSS_ESS_ADI_0_0_REG_END 0x207182b4
-#define BCHP_VICE2_ARCSS_ESS_CTRL_0_0_REG_START 0x20720000
-#define BCHP_VICE2_ARCSS_ESS_CTRL_0_0_REG_END 0x207200a4
-#define BCHP_VICE2_ARCSS_ESS_FLAG_INTR2_0_0_REG_START 0x20720400
-#define BCHP_VICE2_ARCSS_ESS_FLAG_INTR2_0_0_REG_END 0x2072042c
-#define BCHP_VICE2_ARCSS_ESS_P1_INTR2_0_0_REG_START 0x20720600
-#define BCHP_VICE2_ARCSS_ESS_P1_INTR2_0_0_REG_END 0x2072062c
-#define BCHP_VICE2_ARCSS_ESS_HOSTIF_0_0_REG_START 0x20722000
-#define BCHP_VICE2_ARCSS_ESS_HOSTIF_0_0_REG_END 0x207233fc
-#define BCHP_VICE2_ARCSS_ESS_DCCM_0_0_REG_START 0x20730000
-#define BCHP_VICE2_ARCSS_ESS_DCCM_0_0_REG_END 0x2073fffc
-#define BCHP_VICE2_ARCSS_ESS_ADI_1_0_REG_START 0x20758000
-#define BCHP_VICE2_ARCSS_ESS_ADI_1_0_REG_END 0x207582a8
-#define BCHP_VICE2_ARCSS_ESS_CTRL_1_0_REG_START 0x20760000
-#define BCHP_VICE2_ARCSS_ESS_CTRL_1_0_REG_END 0x207600a4
-#define BCHP_VICE2_ARCSS_ESS_FLAG_INTR2_1_0_REG_START 0x20760400
-#define BCHP_VICE2_ARCSS_ESS_FLAG_INTR2_1_0_REG_END 0x2076042c
-#define BCHP_VICE2_ARCSS_ESS_P1_INTR2_1_0_REG_START 0x20760600
-#define BCHP_VICE2_ARCSS_ESS_P1_INTR2_1_0_REG_END 0x2076062c
-#define BCHP_VICE2_ARCSS_ESS_HOSTIF_1_0_REG_START 0x20762000
-#define BCHP_VICE2_ARCSS_ESS_HOSTIF_1_0_REG_END 0x207633fc
-#define BCHP_VICE2_ARCSS_ESS_DCCM_1_0_REG_START 0x20770000
-#define BCHP_VICE2_ARCSS_ESS_DCCM_1_0_REG_END 0x2077fffc
-#define BCHP_VICE2_RGR_0_REG_START 0x20780000
-#define BCHP_VICE2_RGR_0_REG_END 0x2078000c
-#define BCHP_VICE2_MISC_0_REG_START 0x20781000
-#define BCHP_VICE2_MISC_0_REG_END 0x2078102c
-#define BCHP_VICE2_L2_0_REG_START 0x20781100
-#define BCHP_VICE2_L2_0_REG_END 0x2078112c
-#define BCHP_VICE2_ARCSS_MISC_0_REG_START 0x20782000
-#define BCHP_VICE2_ARCSS_MISC_0_REG_END 0x207820b8
-#define BCHP_VICE2_CME_0_1_REG_START 0x20800800
-#define BCHP_VICE2_CME_0_1_REG_END 0x208008a0
-#define BCHP_VICE2_FME_0_1_REG_START 0x20800c00
-#define BCHP_VICE2_FME_0_1_REG_END 0x20800c88
-#define BCHP_VICE2_MC_0_1_REG_START 0x20801000
-#define BCHP_VICE2_MC_0_1_REG_END 0x2080108c
-#define BCHP_VICE2_MAU_0_1_REG_START 0x20801400
-#define BCHP_VICE2_MAU_0_1_REG_END 0x20801510
-#define BCHP_VICE2_IMD_0_1_REG_START 0x20801800
-#define BCHP_VICE2_IMD_0_1_REG_END 0x2080187c
-#define BCHP_VICE2_CABAC_0_1_REG_START 0x20801c00
-#define BCHP_VICE2_CABAC_0_1_REG_END 0x20801dec
-#define BCHP_VICE2_HA_0_1_REG_START 0x20802000
-#define BCHP_VICE2_HA_0_1_REG_END 0x2080208c
-#define BCHP_VICE2_SG_0_1_REG_START 0x20802400
-#define BCHP_VICE2_SG_0_1_REG_END 0x208024ac
-#define BCHP_VICE2_DBLK_0_1_REG_START 0x20802800
-#define BCHP_VICE2_DBLK_0_1_REG_END 0x2080288c
-#define BCHP_VICE2_VIP_0_1_REG_START 0x20803000
-#define BCHP_VICE2_VIP_0_1_REG_END 0x20803224
-#define BCHP_VICE2_VIP1_0_1_REG_START 0x20803800
-#define BCHP_VICE2_VIP1_0_1_REG_END 0x20803a24
-#define BCHP_VICE2_XQ_0_1_REG_START 0x20804000
-#define BCHP_VICE2_XQ_0_1_REG_END 0x208054c8
-#define BCHP_VICE2_ARCSS_ESS_ADI_0_1_REG_START 0x20818000
-#define BCHP_VICE2_ARCSS_ESS_ADI_0_1_REG_END 0x208182b4
-#define BCHP_VICE2_ARCSS_ESS_CTRL_0_1_REG_START 0x20820000
-#define BCHP_VICE2_ARCSS_ESS_CTRL_0_1_REG_END 0x208200a4
-#define BCHP_VICE2_ARCSS_ESS_FLAG_INTR2_0_1_REG_START 0x20820400
-#define BCHP_VICE2_ARCSS_ESS_FLAG_INTR2_0_1_REG_END 0x2082042c
-#define BCHP_VICE2_ARCSS_ESS_P1_INTR2_0_1_REG_START 0x20820600
-#define BCHP_VICE2_ARCSS_ESS_P1_INTR2_0_1_REG_END 0x2082062c
-#define BCHP_VICE2_ARCSS_ESS_HOSTIF_0_1_REG_START 0x20822000
-#define BCHP_VICE2_ARCSS_ESS_HOSTIF_0_1_REG_END 0x208233fc
-#define BCHP_VICE2_ARCSS_ESS_DCCM_0_1_REG_START 0x20830000
-#define BCHP_VICE2_ARCSS_ESS_DCCM_0_1_REG_END 0x2083fffc
-#define BCHP_VICE2_ARCSS_ESS_ADI_1_1_REG_START 0x20858000
-#define BCHP_VICE2_ARCSS_ESS_ADI_1_1_REG_END 0x208582a8
-#define BCHP_VICE2_ARCSS_ESS_CTRL_1_1_REG_START 0x20860000
-#define BCHP_VICE2_ARCSS_ESS_CTRL_1_1_REG_END 0x208600a4
-#define BCHP_VICE2_ARCSS_ESS_FLAG_INTR2_1_1_REG_START 0x20860400
-#define BCHP_VICE2_ARCSS_ESS_FLAG_INTR2_1_1_REG_END 0x2086042c
-#define BCHP_VICE2_ARCSS_ESS_P1_INTR2_1_1_REG_START 0x20860600
-#define BCHP_VICE2_ARCSS_ESS_P1_INTR2_1_1_REG_END 0x2086062c
-#define BCHP_VICE2_ARCSS_ESS_HOSTIF_1_1_REG_START 0x20862000
-#define BCHP_VICE2_ARCSS_ESS_HOSTIF_1_1_REG_END 0x208633fc
-#define BCHP_VICE2_ARCSS_ESS_DCCM_1_1_REG_START 0x20870000
-#define BCHP_VICE2_ARCSS_ESS_DCCM_1_1_REG_END 0x2087fffc
-#define BCHP_VICE2_RGR_1_REG_START 0x20880000
-#define BCHP_VICE2_RGR_1_REG_END 0x2088000c
-#define BCHP_VICE2_MISC_1_REG_START 0x20881000
-#define BCHP_VICE2_MISC_1_REG_END 0x2088102c
-#define BCHP_VICE2_L2_1_REG_START 0x20881100
-#define BCHP_VICE2_L2_1_REG_END 0x2088112c
-#define BCHP_VICE2_ARCSS_MISC_1_REG_START 0x20882000
-#define BCHP_VICE2_ARCSS_MISC_1_REG_END 0x208820b8
-#define BCHP_VICE2_SEC_CTRL_0_REG_START 0x20900000
-#define BCHP_VICE2_SEC_CTRL_0_REG_END 0x20900080
-#define BCHP_VICE2_SEC_CTRL_1_REG_START 0x20901000
-#define BCHP_VICE2_SEC_CTRL_1_REG_END 0x20901080
-#define BCHP_SATA_GRB_REG_START 0x20910000
-#define BCHP_SATA_GRB_REG_END 0x2091000c
-#define BCHP_SATA_TOP_CTRL_REG_START 0x20910040
-#define BCHP_SATA_TOP_CTRL_REG_END 0x20910060
-#define BCHP_SATA3_INTR2_REG_START 0x20910080
-#define BCHP_SATA3_INTR2_REG_END 0x209100ac
-#define BCHP_PORT0_SATA3_PCB_REG_START 0x20910100
-#define BCHP_PORT0_SATA3_PCB_REG_END 0x20910ffc
-#define BCHP_PORT1_SATA3_PCB_REG_START 0x20911100
-#define BCHP_PORT1_SATA3_PCB_REG_END 0x20911ffc
-#define BCHP_SATA_AHCI_GHC_REG_START 0x20912000
-#define BCHP_SATA_AHCI_GHC_REG_END 0x20912028
-#define BCHP_SATA_GLOBAL_RESERVED_REG_START 0x2091202c
-#define BCHP_SATA_GLOBAL_RESERVED_REG_END 0x2091209c
-#define BCHP_SATA_PORT0_AHCI_S1_REG_START 0x20912100
-#define BCHP_SATA_PORT0_AHCI_S1_REG_END 0x2091211c
-#define BCHP_SATA_PORT0_AHCI_S2_REG_START 0x20912120
-#define BCHP_SATA_PORT0_AHCI_S2_REG_END 0x20912134
-#define BCHP_SATA_PORT0_AHCI_S3_REG_START 0x20912138
-#define BCHP_SATA_PORT0_AHCI_S3_REG_END 0x2091217c
-#define BCHP_SATA_PORT1_AHCI_S1_REG_START 0x20912180
-#define BCHP_SATA_PORT1_AHCI_S1_REG_END 0x2091219c
-#define BCHP_SATA_PORT1_AHCI_S2_REG_START 0x209121a0
-#define BCHP_SATA_PORT1_AHCI_S2_REG_END 0x209121b4
-#define BCHP_SATA_PORT1_AHCI_S3_REG_START 0x209121b8
-#define BCHP_SATA_PORT1_AHCI_S3_REG_END 0x209121fc
-#define BCHP_SATA_AHCI_PCICFG_REG_START 0x20912600
-#define BCHP_SATA_AHCI_PCICFG_REG_END 0x20912664
-#define BCHP_SATA_PORT0_CTRL_REG_START 0x20912700
-#define BCHP_SATA_PORT0_CTRL_REG_END 0x20912730
-#define BCHP_SATA_PORT0_CJPAT_REG_START 0x20912740
-#define BCHP_SATA_PORT0_CJPAT_REG_END 0x20912764
-#define BCHP_SATA_PORT1_CTRL_REG_START 0x20912780
-#define BCHP_SATA_PORT1_CTRL_REG_END 0x209127b0
-#define BCHP_SATA_PORT1_CJPAT_REG_START 0x209127c0
-#define BCHP_SATA_PORT1_CJPAT_REG_END 0x209127e4
-#define BCHP_SATA_LEG_PCICFG_REG_START 0x20912800
-#define BCHP_SATA_LEG_PCICFG_REG_END 0x20912880
-#define BCHP_SATA_PORT0_LEG_S1_REG_START 0x20912900
-#define BCHP_SATA_PORT0_LEG_S1_REG_END 0x20912934
-#define BCHP_SATA_PORT0_LEG_S2_REG_START 0x20912940
-#define BCHP_SATA_PORT0_LEG_S2_REG_END 0x20912954
-#define BCHP_SATA_PORT0_LEG_S3_REG_START 0x20912958
-#define BCHP_SATA_PORT0_LEG_S3_REG_END 0x20912998
-#define BCHP_SATA_PORT1_LEG_S1_REG_START 0x20912a00
-#define BCHP_SATA_PORT1_LEG_S1_REG_END 0x20912a34
-#define BCHP_SATA_PORT1_LEG_S2_REG_START 0x20912a40
-#define BCHP_SATA_PORT1_LEG_S2_REG_END 0x20912a54
-#define BCHP_SATA_PORT1_LEG_S3_REG_START 0x20912a58
-#define BCHP_SATA_PORT1_LEG_S3_REG_END 0x20912a98
-#define BCHP_USB_CAPS_REG_START 0x20930000
-#define BCHP_USB_CAPS_REG_END 0x2093002c
-#define BCHP_USB_GR_BRIDGE_REG_START 0x20930100
-#define BCHP_USB_GR_BRIDGE_REG_END 0x2093010c
-#define BCHP_USB_INTR2_REG_START 0x20930180
-#define BCHP_USB_INTR2_REG_END 0x209301ac
-#define BCHP_USB_CTRL_REG_START 0x20930200
-#define BCHP_USB_CTRL_REG_END 0x20930274
-#define BCHP_USB_EHCI_REG_START 0x20930300
-#define BCHP_USB_EHCI_REG_END 0x209303a4
-#define BCHP_USB_OHCI_REG_START 0x20930400
-#define BCHP_USB_OHCI_REG_END 0x20930454
-#define BCHP_USB_EHCI1_REG_START 0x20930500
-#define BCHP_USB_EHCI1_REG_END 0x209305a4
-#define BCHP_USB_OHCI1_REG_START 0x20930600
-#define BCHP_USB_OHCI1_REG_END 0x20930654
-#define BCHP_USB_XHCI_REG_START 0x20931000
-#define BCHP_USB_XHCI_REG_END 0x209318c4
-#define BCHP_USB_XHCI_EC_REG_START 0x20931940
-#define BCHP_USB_XHCI_EC_REG_END 0x20931fc0
-#define BCHP_XPT_BUS_IF_SUB_MODULE_SOFT_INIT_DONE_INTR2_REG_START 0x20a00000
-#define BCHP_XPT_BUS_IF_SUB_MODULE_SOFT_INIT_DONE_INTR2_REG_END 0x20a0002c
-#define BCHP_XPT_BUS_IF_REG_START 0x20a00080
-#define BCHP_XPT_BUS_IF_REG_END 0x20a000fc
-#define BCHP_XPT_XMEMIF_REG_START 0x20a00100
-#define BCHP_XPT_XMEMIF_REG_END 0x20a0019c
-#define BCHP_XPT_PMU_REG_START 0x20a00200
-#define BCHP_XPT_PMU_REG_END 0x20a00214
-#define BCHP_XPT_GR_REG_START 0x20a00300
-#define BCHP_XPT_GR_REG_END 0x20a0030c
-#define BCHP_XPT_RMX0_IO_REG_START 0x20a00400
-#define BCHP_XPT_RMX0_IO_REG_END 0x20a00420
-#define BCHP_XPT_RMX1_IO_REG_START 0x20a00500
-#define BCHP_XPT_RMX1_IO_REG_END 0x20a00520
-#define BCHP_XPT_WAKEUP_REG_START 0x20a01000
-#define BCHP_XPT_WAKEUP_REG_END 0x20a01fbc
-#define BCHP_XPT_DPCR0_REG_START 0x20a02000
-#define BCHP_XPT_DPCR0_REG_END 0x20a02074
-#define BCHP_XPT_DPCR1_REG_START 0x20a02080
-#define BCHP_XPT_DPCR1_REG_END 0x20a020f4
-#define BCHP_XPT_DPCR2_REG_START 0x20a02100
-#define BCHP_XPT_DPCR2_REG_END 0x20a02174
-#define BCHP_XPT_DPCR3_REG_START 0x20a02180
-#define BCHP_XPT_DPCR3_REG_END 0x20a021f4
-#define BCHP_XPT_DPCR4_REG_START 0x20a02200
-#define BCHP_XPT_DPCR4_REG_END 0x20a02274
-#define BCHP_XPT_DPCR5_REG_START 0x20a02280
-#define BCHP_XPT_DPCR5_REG_END 0x20a022f4
-#define BCHP_XPT_DPCR6_REG_START 0x20a02300
-#define BCHP_XPT_DPCR6_REG_END 0x20a02374
-#define BCHP_XPT_DPCR7_REG_START 0x20a02380
-#define BCHP_XPT_DPCR7_REG_END 0x20a023f4
-#define BCHP_XPT_DPCR8_REG_START 0x20a02400
-#define BCHP_XPT_DPCR8_REG_END 0x20a02474
-#define BCHP_XPT_DPCR9_REG_START 0x20a02480
-#define BCHP_XPT_DPCR9_REG_END 0x20a024f4
-#define BCHP_XPT_DPCR10_REG_START 0x20a02500
-#define BCHP_XPT_DPCR10_REG_END 0x20a02574
-#define BCHP_XPT_DPCR11_REG_START 0x20a02580
-#define BCHP_XPT_DPCR11_REG_END 0x20a025f4
-#define BCHP_XPT_DPCR12_REG_START 0x20a02600
-#define BCHP_XPT_DPCR12_REG_END 0x20a02674
-#define BCHP_XPT_DPCR13_REG_START 0x20a02680
-#define BCHP_XPT_DPCR13_REG_END 0x20a026f4
-#define BCHP_XPT_DPCR_PP_REG_START 0x20a02800
-#define BCHP_XPT_DPCR_PP_REG_END 0x20a02804
-#define BCHP_XPT_PSUB_REG_START 0x20a02a00
-#define BCHP_XPT_PSUB_REG_END 0x20a02b88
-#define BCHP_XPT_MPOD_REG_START 0x20a02c00
-#define BCHP_XPT_MPOD_REG_END 0x20a02c20
-#define BCHP_XPT_RMX0_REG_START 0x20a02d00
-#define BCHP_XPT_RMX0_REG_END 0x20a02d08
-#define BCHP_XPT_RMX1_REG_START 0x20a02e00
-#define BCHP_XPT_RMX1_REG_END 0x20a02e08
-#define BCHP_XPT_RSBUFF_REG_START 0x20a03000
-#define BCHP_XPT_RSBUFF_REG_END 0x20a03e6c
-#define BCHP_XPT_XCBUFF_REG_START 0x20a04000
-#define BCHP_XPT_XCBUFF_REG_END 0x20a05ce0
-#define BCHP_XPT_PCROFFSET_REG_START 0x20a08000
-#define BCHP_XPT_PCROFFSET_REG_END 0x20a0aafc
-#define BCHP_XPT_FULL_PID_PARSER_REG_START 0x20a10000
-#define BCHP_XPT_FULL_PID_PARSER_REG_END 0x20a14050
-#define BCHP_XPT_FE_REG_START 0x20a20000
-#define BCHP_XPT_FE_REG_END 0x20a25ffc
-#define BCHP_XPT_MSG_REG_START 0x20a30000
-#define BCHP_XPT_MSG_REG_END 0x20a3ca18
-#define BCHP_XPT_RAVE_REG_START 0x20a40000
-#define BCHP_XPT_RAVE_REG_END 0x20a4d6f4
-#define BCHP_XPT_RAVE_TO_SCPU_L2_INTR_0_31_REG_START 0x20a4ff80
-#define BCHP_XPT_RAVE_TO_SCPU_L2_INTR_0_31_REG_END 0x20a4ffac
-#define BCHP_XPT_RAVE_TO_SCPU_L2_INTR_32_47_REG_START 0x20a4ffc0
-#define BCHP_XPT_RAVE_TO_SCPU_L2_INTR_32_47_REG_END 0x20a4ffec
-#define BCHP_XPT_MEMDMA_MCPB_CPU_INTR_AGGREGATOR_REG_START 0x20a60000
-#define BCHP_XPT_MEMDMA_MCPB_CPU_INTR_AGGREGATOR_REG_END 0x20a6001c
-#define BCHP_XPT_MEMDMA_MCPB_PCI_INTR_AGGREGATOR_REG_START 0x20a60020
-#define BCHP_XPT_MEMDMA_MCPB_PCI_INTR_AGGREGATOR_REG_END 0x20a6003c
-#define BCHP_XPT_MEMDMA_MCPB_DESC_DONE_INTR_L2_REG_START 0x20a60040
-#define BCHP_XPT_MEMDMA_MCPB_DESC_DONE_INTR_L2_REG_END 0x20a6006c
-#define BCHP_XPT_MEMDMA_MCPB_MISC_FALSE_WAKE_INTR_L2_REG_START 0x20a60080
-#define BCHP_XPT_MEMDMA_MCPB_MISC_FALSE_WAKE_INTR_L2_REG_END 0x20a600ac
-#define BCHP_XPT_MEMDMA_MCPB_MISC_OOS_INTR_L2_REG_START 0x20a600c0
-#define BCHP_XPT_MEMDMA_MCPB_MISC_OOS_INTR_L2_REG_END 0x20a600ec
-#define BCHP_XPT_MEMDMA_MCPB_MISC_TS_PARITY_ERR_INTR_L2_REG_START 0x20a60100
-#define BCHP_XPT_MEMDMA_MCPB_MISC_TS_PARITY_ERR_INTR_L2_REG_END 0x20a6012c
-#define BCHP_XPT_MEMDMA_MCPB_MISC_TEI_INTR_L2_REG_START 0x20a60140
-#define BCHP_XPT_MEMDMA_MCPB_MISC_TEI_INTR_L2_REG_END 0x20a6016c
-#define BCHP_XPT_MEMDMA_MCPB_MISC_ASF_LEN_ERR_INTR_L2_REG_START 0x20a60180
-#define BCHP_XPT_MEMDMA_MCPB_MISC_ASF_LEN_ERR_INTR_L2_REG_END 0x20a601ac
-#define BCHP_XPT_MEMDMA_MCPB_MISC_ASF_FATAL_ERR_INTR_L2_REG_START 0x20a601c0
-#define BCHP_XPT_MEMDMA_MCPB_MISC_ASF_FATAL_ERR_INTR_L2_REG_END 0x20a601ec
-#define BCHP_XPT_MEMDMA_MCPB_MISC_ASF_COMPRESSED_DATA_RECEIVED_INTR_L2_REG_START 0x20a60200
-#define BCHP_XPT_MEMDMA_MCPB_MISC_ASF_COMPRESSED_DATA_RECEIVED_INTR_L2_REG_END 0x20a6022c
-#define BCHP_XPT_MEMDMA_MCPB_MISC_ASF_PROTOCOL_ERR_INTR_L2_REG_START 0x20a60240
-#define BCHP_XPT_MEMDMA_MCPB_MISC_ASF_PROTOCOL_ERR_INTR_L2_REG_END 0x20a6026c
-#define BCHP_XPT_MEMDMA_MCPB_MISC_ASF_PADDING_LEN_ERR_INTR_L2_REG_START 0x20a60280
-#define BCHP_XPT_MEMDMA_MCPB_MISC_ASF_PADDING_LEN_ERR_INTR_L2_REG_END 0x20a602ac
-#define BCHP_XPT_MEMDMA_MCPB_MISC_TS_RANGE_ERR_INTR_L2_REG_START 0x20a602c0
-#define BCHP_XPT_MEMDMA_MCPB_MISC_TS_RANGE_ERR_INTR_L2_REG_END 0x20a602ec
-#define BCHP_XPT_MEMDMA_MCPB_MISC_PES_NEXT_TS_RANGE_ERR_INTR_L2_REG_START 0x20a60300
-#define BCHP_XPT_MEMDMA_MCPB_MISC_PES_NEXT_TS_RANGE_ERR_INTR_L2_REG_END 0x20a6032c
-#define BCHP_XPT_MEMDMA_MCPB_MISC_PAUSE_AT_DESC_READ_INTR_L2_REG_START 0x20a60340
-#define BCHP_XPT_MEMDMA_MCPB_MISC_PAUSE_AT_DESC_READ_INTR_L2_REG_END 0x20a6036c
-#define BCHP_XPT_MEMDMA_MCPB_MISC_PAUSE_AT_DESC_END_INTR_L2_REG_START 0x20a60380
-#define BCHP_XPT_MEMDMA_MCPB_MISC_PAUSE_AT_DESC_END_INTR_L2_REG_END 0x20a603ac
-#define BCHP_XPT_MEMDMA_MCPB_MISC_PAUSE_AFTER_GROUP_PACKETS_INTR_L2_REG_START 0x20a603c0
-#define BCHP_XPT_MEMDMA_MCPB_MISC_PAUSE_AFTER_GROUP_PACKETS_INTR_L2_REG_END 0x20a603ec
-#define BCHP_XPT_MEMDMA_MCPB_MISC_DESC_TAGID_MISMATCH_INTR_L2_REG_START 0x20a60400
-#define BCHP_XPT_MEMDMA_MCPB_MISC_DESC_TAGID_MISMATCH_INTR_L2_REG_END 0x20a6042c
-#define BCHP_XPT_MEMDMA_MCPB_MISC_DATA_TAGID_MISMATCH_INTR_L2_REG_START 0x20a60440
-#define BCHP_XPT_MEMDMA_MCPB_MISC_DATA_TAGID_MISMATCH_INTR_L2_REG_END 0x20a6046c
-#define BCHP_XPT_MEMDMA_MCPB_MISC_CRC_COMPARE_ERROR_INTR_L2_REG_START 0x20a60480
-#define BCHP_XPT_MEMDMA_MCPB_MISC_CRC_COMPARE_ERROR_INTR_L2_REG_END 0x20a604ac
-#define BCHP_XPT_MEMDMA_MCPB_REG_START 0x20a60800
-#define BCHP_XPT_MEMDMA_MCPB_REG_END 0x20a60b4c
-#define BCHP_XPT_MEMDMA_MCPB_CH0_REG_START 0x20a60c00
-#define BCHP_XPT_MEMDMA_MCPB_CH0_REG_END 0x20a60d48
-#define BCHP_XPT_MEMDMA_MCPB_CH1_REG_START 0x20a60e00
-#define BCHP_XPT_MEMDMA_MCPB_CH1_REG_END 0x20a60f48
-#define BCHP_XPT_MEMDMA_MCPB_CH2_REG_START 0x20a61000
-#define BCHP_XPT_MEMDMA_MCPB_CH2_REG_END 0x20a61148
-#define BCHP_XPT_MEMDMA_MCPB_CH3_REG_START 0x20a61200
-#define BCHP_XPT_MEMDMA_MCPB_CH3_REG_END 0x20a61348
-#define BCHP_XPT_MEMDMA_MCPB_CH4_REG_START 0x20a61400
-#define BCHP_XPT_MEMDMA_MCPB_CH4_REG_END 0x20a61548
-#define BCHP_XPT_MEMDMA_MCPB_CH5_REG_START 0x20a61600
-#define BCHP_XPT_MEMDMA_MCPB_CH5_REG_END 0x20a61748
-#define BCHP_XPT_MEMDMA_MCPB_CH6_REG_START 0x20a61800
-#define BCHP_XPT_MEMDMA_MCPB_CH6_REG_END 0x20a61948
-#define BCHP_XPT_MEMDMA_MCPB_CH7_REG_START 0x20a61a00
-#define BCHP_XPT_MEMDMA_MCPB_CH7_REG_END 0x20a61b48
-#define BCHP_XPT_MEMDMA_MCPB_CH8_REG_START 0x20a61c00
-#define BCHP_XPT_MEMDMA_MCPB_CH8_REG_END 0x20a61d48
-#define BCHP_XPT_MEMDMA_MCPB_CH9_REG_START 0x20a61e00
-#define BCHP_XPT_MEMDMA_MCPB_CH9_REG_END 0x20a61f48
-#define BCHP_XPT_MEMDMA_MCPB_CH10_REG_START 0x20a62000
-#define BCHP_XPT_MEMDMA_MCPB_CH10_REG_END 0x20a62148
-#define BCHP_XPT_MEMDMA_MCPB_CH11_REG_START 0x20a62200
-#define BCHP_XPT_MEMDMA_MCPB_CH11_REG_END 0x20a62348
-#define BCHP_XPT_MEMDMA_MCPB_CH12_REG_START 0x20a62400
-#define BCHP_XPT_MEMDMA_MCPB_CH12_REG_END 0x20a62548
-#define BCHP_XPT_MEMDMA_MCPB_CH13_REG_START 0x20a62600
-#define BCHP_XPT_MEMDMA_MCPB_CH13_REG_END 0x20a62748
-#define BCHP_XPT_MEMDMA_MCPB_CH14_REG_START 0x20a62800
-#define BCHP_XPT_MEMDMA_MCPB_CH14_REG_END 0x20a62948
-#define BCHP_XPT_MEMDMA_MCPB_CH15_REG_START 0x20a62a00
-#define BCHP_XPT_MEMDMA_MCPB_CH15_REG_END 0x20a62b48
-#define BCHP_XPT_MEMDMA_MCPB_CH16_REG_START 0x20a62c00
-#define BCHP_XPT_MEMDMA_MCPB_CH16_REG_END 0x20a62d48
-#define BCHP_XPT_MEMDMA_MCPB_CH17_REG_START 0x20a62e00
-#define BCHP_XPT_MEMDMA_MCPB_CH17_REG_END 0x20a62f48
-#define BCHP_XPT_MEMDMA_MCPB_CH18_REG_START 0x20a63000
-#define BCHP_XPT_MEMDMA_MCPB_CH18_REG_END 0x20a63148
-#define BCHP_XPT_MEMDMA_MCPB_CH19_REG_START 0x20a63200
-#define BCHP_XPT_MEMDMA_MCPB_CH19_REG_END 0x20a63348
-#define BCHP_XPT_MEMDMA_MCPB_CH20_REG_START 0x20a63400
-#define BCHP_XPT_MEMDMA_MCPB_CH20_REG_END 0x20a63548
-#define BCHP_XPT_MEMDMA_MCPB_CH21_REG_START 0x20a63600
-#define BCHP_XPT_MEMDMA_MCPB_CH21_REG_END 0x20a63748
-#define BCHP_XPT_MEMDMA_MCPB_CH22_REG_START 0x20a63800
-#define BCHP_XPT_MEMDMA_MCPB_CH22_REG_END 0x20a63948
-#define BCHP_XPT_MEMDMA_MCPB_CH23_REG_START 0x20a63a00
-#define BCHP_XPT_MEMDMA_MCPB_CH23_REG_END 0x20a63b48
-#define BCHP_XPT_MEMDMA_MCPB_CH24_REG_START 0x20a63c00
-#define BCHP_XPT_MEMDMA_MCPB_CH24_REG_END 0x20a63d48
-#define BCHP_XPT_MEMDMA_MCPB_CH25_REG_START 0x20a63e00
-#define BCHP_XPT_MEMDMA_MCPB_CH25_REG_END 0x20a63f48
-#define BCHP_XPT_MEMDMA_MCPB_CH26_REG_START 0x20a64000
-#define BCHP_XPT_MEMDMA_MCPB_CH26_REG_END 0x20a64148
-#define BCHP_XPT_MEMDMA_MCPB_CH27_REG_START 0x20a64200
-#define BCHP_XPT_MEMDMA_MCPB_CH27_REG_END 0x20a64348
-#define BCHP_XPT_MEMDMA_MCPB_CH28_REG_START 0x20a64400
-#define BCHP_XPT_MEMDMA_MCPB_CH28_REG_END 0x20a64548
-#define BCHP_XPT_MEMDMA_MCPB_CH29_REG_START 0x20a64600
-#define BCHP_XPT_MEMDMA_MCPB_CH29_REG_END 0x20a64748
-#define BCHP_XPT_MEMDMA_MCPB_CH30_REG_START 0x20a64800
-#define BCHP_XPT_MEMDMA_MCPB_CH30_REG_END 0x20a64948
-#define BCHP_XPT_MEMDMA_MCPB_CH31_REG_START 0x20a64a00
-#define BCHP_XPT_MEMDMA_MCPB_CH31_REG_END 0x20a64b48
-#define BCHP_XPT_WDMA_PCI_INTR_AGGREGATOR_REG_START 0x20a68000
-#define BCHP_XPT_WDMA_PCI_INTR_AGGREGATOR_REG_END 0x20a6801c
-#define BCHP_XPT_WDMA_CPU_INTR_AGGREGATOR_REG_START 0x20a68020
-#define BCHP_XPT_WDMA_CPU_INTR_AGGREGATOR_REG_END 0x20a6803c
-#define BCHP_XPT_WDMA_BTP_INTR_L2_REG_START 0x20a68040
-#define BCHP_XPT_WDMA_BTP_INTR_L2_REG_END 0x20a6806c
-#define BCHP_XPT_WDMA_OVERFLOW_INTR_L2_REG_START 0x20a68080
-#define BCHP_XPT_WDMA_OVERFLOW_INTR_L2_REG_END 0x20a680ac
-#define BCHP_XPT_WDMA_DESC_DONE_INTR_L2_REG_START 0x20a680c0
-#define BCHP_XPT_WDMA_DESC_DONE_INTR_L2_REG_END 0x20a680ec
-#define BCHP_XPT_WDMA_REGS_REG_START 0x20a69000
-#define BCHP_XPT_WDMA_REGS_REG_END 0x20a69088
-#define BCHP_XPT_WDMA_RAMS_REG_START 0x20a6a000
-#define BCHP_XPT_WDMA_RAMS_REG_END 0x20a6bffc
-#define BCHP_XPT_MEMDMA_XMEMIF_REG_START 0x20a6ff00
-#define BCHP_XPT_MEMDMA_XMEMIF_REG_END 0x20a6ff9c
-#define BCHP_XPT_MCPB_CPU_INTR_AGGREGATOR_REG_START 0x20a70000
-#define BCHP_XPT_MCPB_CPU_INTR_AGGREGATOR_REG_END 0x20a7001c
-#define BCHP_XPT_MCPB_PCI_INTR_AGGREGATOR_REG_START 0x20a70020
-#define BCHP_XPT_MCPB_PCI_INTR_AGGREGATOR_REG_END 0x20a7003c
-#define BCHP_XPT_MCPB_DESC_DONE_INTR_L2_REG_START 0x20a70040
-#define BCHP_XPT_MCPB_DESC_DONE_INTR_L2_REG_END 0x20a7006c
-#define BCHP_XPT_MCPB_MISC_FALSE_WAKE_INTR_L2_REG_START 0x20a70080
-#define BCHP_XPT_MCPB_MISC_FALSE_WAKE_INTR_L2_REG_END 0x20a700ac
-#define BCHP_XPT_MCPB_MISC_OOS_INTR_L2_REG_START 0x20a700c0
-#define BCHP_XPT_MCPB_MISC_OOS_INTR_L2_REG_END 0x20a700ec
-#define BCHP_XPT_MCPB_MISC_TS_PARITY_ERR_INTR_L2_REG_START 0x20a70100
-#define BCHP_XPT_MCPB_MISC_TS_PARITY_ERR_INTR_L2_REG_END 0x20a7012c
-#define BCHP_XPT_MCPB_MISC_TEI_INTR_L2_REG_START 0x20a70140
-#define BCHP_XPT_MCPB_MISC_TEI_INTR_L2_REG_END 0x20a7016c
-#define BCHP_XPT_MCPB_MISC_ASF_LEN_ERR_INTR_L2_REG_START 0x20a70180
-#define BCHP_XPT_MCPB_MISC_ASF_LEN_ERR_INTR_L2_REG_END 0x20a701ac
-#define BCHP_XPT_MCPB_MISC_ASF_FATAL_ERR_INTR_L2_REG_START 0x20a701c0
-#define BCHP_XPT_MCPB_MISC_ASF_FATAL_ERR_INTR_L2_REG_END 0x20a701ec
-#define BCHP_XPT_MCPB_MISC_ASF_COMPRESSED_DATA_RECEIVED_INTR_L2_REG_START 0x20a70200
-#define BCHP_XPT_MCPB_MISC_ASF_COMPRESSED_DATA_RECEIVED_INTR_L2_REG_END 0x20a7022c
-#define BCHP_XPT_MCPB_MISC_ASF_PROTOCOL_ERR_INTR_L2_REG_START 0x20a70240
-#define BCHP_XPT_MCPB_MISC_ASF_PROTOCOL_ERR_INTR_L2_REG_END 0x20a7026c
-#define BCHP_XPT_MCPB_MISC_ASF_PADDING_LEN_ERR_INTR_L2_REG_START 0x20a70280
-#define BCHP_XPT_MCPB_MISC_ASF_PADDING_LEN_ERR_INTR_L2_REG_END 0x20a702ac
-#define BCHP_XPT_MCPB_MISC_TS_RANGE_ERR_INTR_L2_REG_START 0x20a702c0
-#define BCHP_XPT_MCPB_MISC_TS_RANGE_ERR_INTR_L2_REG_END 0x20a702ec
-#define BCHP_XPT_MCPB_MISC_PES_NEXT_TS_RANGE_ERR_INTR_L2_REG_START 0x20a70300
-#define BCHP_XPT_MCPB_MISC_PES_NEXT_TS_RANGE_ERR_INTR_L2_REG_END 0x20a7032c
-#define BCHP_XPT_MCPB_MISC_PAUSE_AT_DESC_READ_INTR_L2_REG_START 0x20a70340
-#define BCHP_XPT_MCPB_MISC_PAUSE_AT_DESC_READ_INTR_L2_REG_END 0x20a7036c
-#define BCHP_XPT_MCPB_MISC_PAUSE_AT_DESC_END_INTR_L2_REG_START 0x20a70380
-#define BCHP_XPT_MCPB_MISC_PAUSE_AT_DESC_END_INTR_L2_REG_END 0x20a703ac
-#define BCHP_XPT_MCPB_MISC_PAUSE_AFTER_GROUP_PACKETS_INTR_L2_REG_START 0x20a703c0
-#define BCHP_XPT_MCPB_MISC_PAUSE_AFTER_GROUP_PACKETS_INTR_L2_REG_END 0x20a703ec
-#define BCHP_XPT_MCPB_MISC_DESC_TAGID_MISMATCH_INTR_L2_REG_START 0x20a70400
-#define BCHP_XPT_MCPB_MISC_DESC_TAGID_MISMATCH_INTR_L2_REG_END 0x20a7042c
-#define BCHP_XPT_MCPB_MISC_DATA_TAGID_MISMATCH_INTR_L2_REG_START 0x20a70440
-#define BCHP_XPT_MCPB_MISC_DATA_TAGID_MISMATCH_INTR_L2_REG_END 0x20a7046c
-#define BCHP_XPT_MCPB_MISC_CRC_COMPARE_ERROR_INTR_L2_REG_START 0x20a70480
-#define BCHP_XPT_MCPB_MISC_CRC_COMPARE_ERROR_INTR_L2_REG_END 0x20a704ac
-#define BCHP_XPT_MCPB_REG_START 0x20a70800
-#define BCHP_XPT_MCPB_REG_END 0x20a70b4c
-#define BCHP_XPT_MCPB_CH0_REG_START 0x20a70c00
-#define BCHP_XPT_MCPB_CH0_REG_END 0x20a70d48
-#define BCHP_XPT_MCPB_CH1_REG_START 0x20a70e00
-#define BCHP_XPT_MCPB_CH1_REG_END 0x20a70f48
-#define BCHP_XPT_MCPB_CH2_REG_START 0x20a71000
-#define BCHP_XPT_MCPB_CH2_REG_END 0x20a71148
-#define BCHP_XPT_MCPB_CH3_REG_START 0x20a71200
-#define BCHP_XPT_MCPB_CH3_REG_END 0x20a71348
-#define BCHP_XPT_MCPB_CH4_REG_START 0x20a71400
-#define BCHP_XPT_MCPB_CH4_REG_END 0x20a71548
-#define BCHP_XPT_MCPB_CH5_REG_START 0x20a71600
-#define BCHP_XPT_MCPB_CH5_REG_END 0x20a71748
-#define BCHP_XPT_MCPB_CH6_REG_START 0x20a71800
-#define BCHP_XPT_MCPB_CH6_REG_END 0x20a71948
-#define BCHP_XPT_MCPB_CH7_REG_START 0x20a71a00
-#define BCHP_XPT_MCPB_CH7_REG_END 0x20a71b48
-#define BCHP_XPT_MCPB_CH8_REG_START 0x20a71c00
-#define BCHP_XPT_MCPB_CH8_REG_END 0x20a71d48
-#define BCHP_XPT_MCPB_CH9_REG_START 0x20a71e00
-#define BCHP_XPT_MCPB_CH9_REG_END 0x20a71f48
-#define BCHP_XPT_MCPB_CH10_REG_START 0x20a72000
-#define BCHP_XPT_MCPB_CH10_REG_END 0x20a72148
-#define BCHP_XPT_MCPB_CH11_REG_START 0x20a72200
-#define BCHP_XPT_MCPB_CH11_REG_END 0x20a72348
-#define BCHP_XPT_MCPB_CH12_REG_START 0x20a72400
-#define BCHP_XPT_MCPB_CH12_REG_END 0x20a72548
-#define BCHP_XPT_MCPB_CH13_REG_START 0x20a72600
-#define BCHP_XPT_MCPB_CH13_REG_END 0x20a72748
-#define BCHP_XPT_MCPB_CH14_REG_START 0x20a72800
-#define BCHP_XPT_MCPB_CH14_REG_END 0x20a72948
-#define BCHP_XPT_MCPB_CH15_REG_START 0x20a72a00
-#define BCHP_XPT_MCPB_CH15_REG_END 0x20a72b48
-#define BCHP_XPT_MCPB_CH16_REG_START 0x20a72c00
-#define BCHP_XPT_MCPB_CH16_REG_END 0x20a72d48
-#define BCHP_XPT_MCPB_CH17_REG_START 0x20a72e00
-#define BCHP_XPT_MCPB_CH17_REG_END 0x20a72f48
-#define BCHP_XPT_MCPB_CH18_REG_START 0x20a73000
-#define BCHP_XPT_MCPB_CH18_REG_END 0x20a73148
-#define BCHP_XPT_MCPB_CH19_REG_START 0x20a73200
-#define BCHP_XPT_MCPB_CH19_REG_END 0x20a73348
-#define BCHP_XPT_MCPB_CH20_REG_START 0x20a73400
-#define BCHP_XPT_MCPB_CH20_REG_END 0x20a73548
-#define BCHP_XPT_MCPB_CH21_REG_START 0x20a73600
-#define BCHP_XPT_MCPB_CH21_REG_END 0x20a73748
-#define BCHP_XPT_MCPB_CH22_REG_START 0x20a73800
-#define BCHP_XPT_MCPB_CH22_REG_END 0x20a73948
-#define BCHP_XPT_MCPB_CH23_REG_START 0x20a73a00
-#define BCHP_XPT_MCPB_CH23_REG_END 0x20a73b48
-#define BCHP_XPT_MCPB_CH24_REG_START 0x20a73c00
-#define BCHP_XPT_MCPB_CH24_REG_END 0x20a73d48
-#define BCHP_XPT_MCPB_CH25_REG_START 0x20a73e00
-#define BCHP_XPT_MCPB_CH25_REG_END 0x20a73f48
-#define BCHP_XPT_MCPB_CH26_REG_START 0x20a74000
-#define BCHP_XPT_MCPB_CH26_REG_END 0x20a74148
-#define BCHP_XPT_MCPB_CH27_REG_START 0x20a74200
-#define BCHP_XPT_MCPB_CH27_REG_END 0x20a74348
-#define BCHP_XPT_MCPB_CH28_REG_START 0x20a74400
-#define BCHP_XPT_MCPB_CH28_REG_END 0x20a74548
-#define BCHP_XPT_MCPB_CH29_REG_START 0x20a74600
-#define BCHP_XPT_MCPB_CH29_REG_END 0x20a74748
-#define BCHP_XPT_MCPB_CH30_REG_START 0x20a74800
-#define BCHP_XPT_MCPB_CH30_REG_END 0x20a74948
-#define BCHP_XPT_MCPB_CH31_REG_START 0x20a74a00
-#define BCHP_XPT_MCPB_CH31_REG_END 0x20a74b48
-#define BCHP_XPT_XPU_REG_START 0x20a78000
-#define BCHP_XPT_XPU_REG_END 0x20a7c7fc
-#define BCHP_XPT_SECURE_BUS_IF_REG_START 0x20a7f000
-#define BCHP_XPT_SECURE_BUS_IF_REG_END 0x20a7f000
-#define BCHP_SID_REG_START 0x20bc0100
-#define BCHP_SID_REG_END 0x20bc019c
-#define BCHP_SID_RLE_REG_START 0x20bc0300
-#define BCHP_SID_RLE_REG_END 0x20bc039c
-#define BCHP_SID_DQ_REG_START 0x20bc0400
-#define BCHP_SID_DQ_REG_END 0x20bc04bc
-#define BCHP_SID_STRM_REG_START 0x20bc0800
-#define BCHP_SID_STRM_REG_END 0x20bc087c
-#define BCHP_SID_OUTPUT_REG_START 0x20bc0c00
-#define BCHP_SID_OUTPUT_REG_END 0x20bc0c40
-#define BCHP_SID_ARC_REG_START 0x20bc0f00
-#define BCHP_SID_ARC_REG_END 0x20bc0f3c
-#define BCHP_SID_ARCDMA_REG_START 0x20bc1800
-#define BCHP_SID_ARCDMA_REG_END 0x20bc1840
-#define BCHP_SID_DMARAM_REG_START 0x20bc1a00
-#define BCHP_SID_DMARAM_REG_END 0x20bc1bfc
-#define BCHP_SID_PEEK_BITS_REG_START 0x20bc2b00
-#define BCHP_SID_PEEK_BITS_REG_END 0x20bc2b3c
-#define BCHP_SID_EXTRACT_BITS_REG_START 0x20bc2b40
-#define BCHP_SID_EXTRACT_BITS_REG_END 0x20bc2b7c
-#define BCHP_SID_HUFF_SYMB_REG_START 0x20bc3000
-#define BCHP_SID_HUFF_SYMB_REG_END 0x20bc37fc
-#define BCHP_SID_HUFF_CODE_REG_START 0x20bc3900
-#define BCHP_SID_HUFF_CODE_REG_END 0x20bc39fc
-#define BCHP_SID_SYMB_REG_START 0x20bc3a00
-#define BCHP_SID_SYMB_REG_END 0x20bc3a10
-#define BCHP_SID_SYMB_JPEG_REG_START 0x20bc3a80
-#define BCHP_SID_SYMB_JPEG_REG_END 0x20bc3a8c
-#define BCHP_SID_BIGRAM_REG_START 0x20bc8000
-#define BCHP_SID_BIGRAM_REG_END 0x20bcfffc
-#define BCHP_SID_ARC_DBG_REG_START 0x20bd1000
-#define BCHP_SID_ARC_DBG_REG_END 0x20bd1010
-#define BCHP_SID_ARC_CORE_REG_START 0x20bd5000
-#define BCHP_SID_ARC_CORE_REG_END 0x20bd5014
-#define BCHP_SID_GR_REG_START 0x20be0000
-#define BCHP_SID_GR_REG_END 0x20be000c
-#define BCHP_SID_L2_REG_START 0x20be0100
-#define BCHP_SID_L2_REG_END 0x20be012c
-#define BCHP_SICH_REG_START 0x20be2000
-#define BCHP_SICH_REG_END 0x20be203c
-#define BCHP_M2MC_REG_START 0x20be4000
-#define BCHP_M2MC_REG_END 0x20be47fc
-#define BCHP_M2MC_L2_REG_START 0x20be5000
-#define BCHP_M2MC_L2_REG_END 0x20be502c
-#define BCHP_M2MC_GR_REG_START 0x20be5800
-#define BCHP_M2MC_GR_REG_END 0x20be580c
-#define BCHP_M2MC1_REG_START 0x20be6000
-#define BCHP_M2MC1_REG_END 0x20be67fc
-#define BCHP_M2MC1_L2_REG_START 0x20be7000
-#define BCHP_M2MC1_L2_REG_END 0x20be702c
-#define BCHP_M2MC1_GR_REG_START 0x20be7800
-#define BCHP_M2MC1_GR_REG_END 0x20be780c
-#define BCHP_V3D_CTL_REG_START 0x20bea000
-#define BCHP_V3D_CTL_REG_END 0x20bea040
-#define BCHP_V3D_CLE_REG_START 0x20bea100
-#define BCHP_V3D_CLE_REG_END 0x20bea138
-#define BCHP_V3D_PTB_REG_START 0x20bea300
-#define BCHP_V3D_PTB_REG_END 0x20bea310
-#define BCHP_V3D_QPS_REG_START 0x20bea400
-#define BCHP_V3D_QPS_REG_END 0x20bea43c
-#define BCHP_V3D_VPM_REG_START 0x20bea500
-#define BCHP_V3D_VPM_REG_END 0x20bea504
-#define BCHP_V3D_PCTR_REG_START 0x20bea600
-#define BCHP_V3D_PCTR_REG_END 0x20bea6fc
-#define BCHP_V3D_TOP_GR_BRIDGE_REG_START 0x20bea800
-#define BCHP_V3D_TOP_GR_BRIDGE_REG_END 0x20bea80c
-#define BCHP_V3D_GCA_REG_START 0x20beaa00
-#define BCHP_V3D_GCA_REG_END 0x20beaa58
-#define BCHP_V3D_DBG_REG_START 0x20beae00
-#define BCHP_V3D_DBG_REG_END 0x20beaf20
-#define BCHP_RAAGA_DSP_SEC0_REG_START 0x20bf0000
-#define BCHP_RAAGA_DSP_SEC0_REG_END 0x20bf0000
-#define BCHP_RAAGA_DSP_SEC0_1_REG_START 0x20bf1000
-#define BCHP_RAAGA_DSP_SEC0_1_REG_END 0x20bf1000
-#define BCHP_RAAGA_DSP_RGR_REG_START 0x20c00000
-#define BCHP_RAAGA_DSP_RGR_REG_END 0x20c00008
-#define BCHP_RAAGA_DSP_MISC_REG_START 0x20c20000
-#define BCHP_RAAGA_DSP_MISC_REG_END 0x20c2044c
-#define BCHP_RAAGA_DSP_TIMERS_REG_START 0x20c21000
-#define BCHP_RAAGA_DSP_TIMERS_REG_END 0x20c21058
-#define BCHP_RAAGA_DSP_PERI_DBG_CTRL_REG_START 0x20c21080
-#define BCHP_RAAGA_DSP_PERI_DBG_CTRL_REG_END 0x20c2109c
-#define BCHP_RAAGA_DSP_PERI_SW_REG_START 0x20c21100
-#define BCHP_RAAGA_DSP_PERI_SW_REG_END 0x20c21154
-#define BCHP_RAAGA_DSP_DMA_REG_START 0x20c21400
-#define BCHP_RAAGA_DSP_DMA_REG_END 0x20c21664
-#define BCHP_RAAGA_DSP_ESR_SI_REG_START 0x20c22000
-#define BCHP_RAAGA_DSP_ESR_SI_REG_END 0x20c22014
-#define BCHP_RAAGA_DSP_INTH_REG_START 0x20c22200
-#define BCHP_RAAGA_DSP_INTH_REG_END 0x20c2222c
-#define BCHP_RAAGA_DSP_FW_INTH_REG_START 0x20c22400
-#define BCHP_RAAGA_DSP_FW_INTH_REG_END 0x20c2242c
-#define BCHP_RAAGA_DSP_FW_CFG_REG_START 0x20c23000
-#define BCHP_RAAGA_DSP_FW_CFG_REG_END 0x20c2357c
-#define BCHP_RAAGA_DSP_MEM_SUBSYSTEM_REG_START 0x20c30000
-#define BCHP_RAAGA_DSP_MEM_SUBSYSTEM_REG_END 0x20c3bffc
-#define BCHP_AUD_MISC_REG_START 0x20c80000
-#define BCHP_AUD_MISC_REG_END 0x20c80118
-#define BCHP_AUD_INTH_REG_START 0x20c80800
-#define BCHP_AUD_INTH_REG_END 0x20c8082c
-#define BCHP_AUD_FMM_BF_CTRL_REG_START 0x20ca0000
-#define BCHP_AUD_FMM_BF_CTRL_REG_END 0x20ca0d3c
-#define BCHP_AUD_FMM_BF_ESR_REG_START 0x20ca1000
-#define BCHP_AUD_FMM_BF_ESR_REG_END 0x20ca1074
-#define BCHP_AUD_FMM_SRC_CTRL0_REG_START 0x20ca2000
-#define BCHP_AUD_FMM_SRC_CTRL0_REG_END 0x20ca2bfc
-#define BCHP_AUD_FMM_SRC_ESR0_REG_START 0x20ca3000
-#define BCHP_AUD_FMM_SRC_ESR0_REG_END 0x20ca3014
-#define BCHP_AUD_FMM_DP_CTRL0_REG_START 0x20ca4000
-#define BCHP_AUD_FMM_DP_CTRL0_REG_END 0x20ca612c
-#define BCHP_AUD_FMM_DP_ESR0_REG_START 0x20ca7c00
-#define BCHP_AUD_FMM_DP_ESR0_REG_END 0x20ca7c2c
-#define BCHP_AUD_FMM_IOP_OUT_I2S_STEREO_0_REG_START 0x20cb0000
-#define BCHP_AUD_FMM_IOP_OUT_I2S_STEREO_0_REG_END 0x20cb0084
-#define BCHP_AUD_FMM_IOP_OUT_I2S_STEREO_1_REG_START 0x20cb0100
-#define BCHP_AUD_FMM_IOP_OUT_I2S_STEREO_1_REG_END 0x20cb0184
-#define BCHP_AUD_FMM_IOP_OUT_SPDIF_0_REG_START 0x20cb0200
-#define BCHP_AUD_FMM_IOP_OUT_SPDIF_0_REG_END 0x20cb0284
-#define BCHP_AUD_FMM_IOP_OUT_MAI_0_REG_START 0x20cb0300
-#define BCHP_AUD_FMM_IOP_OUT_MAI_0_REG_END 0x20cb0384
-#define BCHP_HIFIDAC_CTRL_0_REG_START 0x20cb0800
-#define BCHP_HIFIDAC_CTRL_0_REG_END 0x20cb09fc
-#define BCHP_HIFIDAC_RM_0_REG_START 0x20cb0a00
-#define BCHP_HIFIDAC_RM_0_REG_END 0x20cb0a24
-#define BCHP_HIFIDAC_ESR_0_REG_START 0x20cb0b00
-#define BCHP_HIFIDAC_ESR_0_REG_END 0x20cb0b14
-#define BCHP_AUD_FMM_IOP_OUT_DAC_CTRL_0_REG_START 0x20cb0c00
-#define BCHP_AUD_FMM_IOP_OUT_DAC_CTRL_0_REG_END 0x20cb0c94
-#define BCHP_AUD_FMM_IOP_PLL_0_REG_START 0x20cb0d00
-#define BCHP_AUD_FMM_IOP_PLL_0_REG_END 0x20cb0d58
-#define BCHP_AUD_FMM_IOP_PLL_1_REG_START 0x20cb0e00
-#define BCHP_AUD_FMM_IOP_PLL_1_REG_END 0x20cb0e58
-#define BCHP_AUD_FMM_IOP_PLL_2_REG_START 0x20cb0f00
-#define BCHP_AUD_FMM_IOP_PLL_2_REG_END 0x20cb0f58
-#define BCHP_AUD_FMM_IOP_NCO_0_REG_START 0x20cb1000
-#define BCHP_AUD_FMM_IOP_NCO_0_REG_END 0x20cb1024
-#define BCHP_AUD_FMM_IOP_NCO_1_REG_START 0x20cb1100
-#define BCHP_AUD_FMM_IOP_NCO_1_REG_END 0x20cb1124
-#define BCHP_AUD_FMM_IOP_NCO_2_REG_START 0x20cb1200
-#define BCHP_AUD_FMM_IOP_NCO_2_REG_END 0x20cb1224
-#define BCHP_AUD_FMM_IOP_NCO_3_REG_START 0x20cb1300
-#define BCHP_AUD_FMM_IOP_NCO_3_REG_END 0x20cb1324
-#define BCHP_AUD_FMM_IOP_NCO_4_REG_START 0x20cb1400
-#define BCHP_AUD_FMM_IOP_NCO_4_REG_END 0x20cb1424
-#define BCHP_AUD_FMM_IOP_LOOPBACK_0_REG_START 0x20cb1600
-#define BCHP_AUD_FMM_IOP_LOOPBACK_0_REG_END 0x20cb1724
-#define BCHP_AUD_FMM_IOP_DUMMYSINK_0_REG_START 0x20cb1800
-#define BCHP_AUD_FMM_IOP_DUMMYSINK_0_REG_END 0x20cb1854
-#define BCHP_AUD_FMM_IOP_IN_SPDIF_0_REG_START 0x20cb2000
-#define BCHP_AUD_FMM_IOP_IN_SPDIF_0_REG_END 0x20cb20fc
-#define BCHP_AUD_FMM_IOP_IN_HDMI_0_REG_START 0x20cb2800
-#define BCHP_AUD_FMM_IOP_IN_HDMI_0_REG_END 0x20cb28ac
-#define BCHP_AUD_FMM_IOP_IN_I2S_STEREO_0_REG_START 0x20cb3000
-#define BCHP_AUD_FMM_IOP_IN_I2S_STEREO_0_REG_END 0x20cb3064
-#define BCHP_AUD_FMM_IOP_ATTG_0_REG_START 0x20cb3100
-#define BCHP_AUD_FMM_IOP_ATTG_0_REG_END 0x20cb3164
-#define BCHP_AUD_FMM_IOP_OUT_MS_STRM_CFG_0_REG_START 0x20cb4000
-#define BCHP_AUD_FMM_IOP_OUT_MS_STRM_CFG_0_REG_END 0x20cb41fc
-#define BCHP_AUD_FMM_IOP_OUT_MS_STRM_ESR_0_REG_START 0x20cb4400
-#define BCHP_AUD_FMM_IOP_OUT_MS_STRM_ESR_0_REG_END 0x20cb4414
-#define BCHP_AUD_FMM_IOP_OUT_MS_CTRL_0_REG_START 0x20cb6000
-#define BCHP_AUD_FMM_IOP_OUT_MS_CTRL_0_REG_END 0x20cb7bfc
-#define BCHP_AUD_FMM_IOP_OUT_MS_ESR_0_REG_START 0x20cb7d00
-#define BCHP_AUD_FMM_IOP_OUT_MS_ESR_0_REG_END 0x20cb7d14
-#define BCHP_AUD_FMM_IOP_MISC_REG_START 0x20cb8100
-#define BCHP_AUD_FMM_IOP_MISC_REG_END 0x20cb8154
-#define BCHP_RAAGA_DSP_RGR_1_REG_START 0x20d00000
-#define BCHP_RAAGA_DSP_RGR_1_REG_END 0x20d00008
-#define BCHP_RAAGA_DSP_MISC_1_REG_START 0x20d20000
-#define BCHP_RAAGA_DSP_MISC_1_REG_END 0x20d2044c
-#define BCHP_RAAGA_DSP_TIMERS_1_REG_START 0x20d21000
-#define BCHP_RAAGA_DSP_TIMERS_1_REG_END 0x20d21058
-#define BCHP_RAAGA_DSP_PERI_DBG_CTRL_1_REG_START 0x20d21080
-#define BCHP_RAAGA_DSP_PERI_DBG_CTRL_1_REG_END 0x20d2109c
-#define BCHP_RAAGA_DSP_PERI_SW_1_REG_START 0x20d21100
-#define BCHP_RAAGA_DSP_PERI_SW_1_REG_END 0x20d21154
-#define BCHP_RAAGA_DSP_DMA_1_REG_START 0x20d21400
-#define BCHP_RAAGA_DSP_DMA_1_REG_END 0x20d21664
-#define BCHP_RAAGA_DSP_ESR_SI_1_REG_START 0x20d22000
-#define BCHP_RAAGA_DSP_ESR_SI_1_REG_END 0x20d22014
-#define BCHP_RAAGA_DSP_INTH_1_REG_START 0x20d22200
-#define BCHP_RAAGA_DSP_INTH_1_REG_END 0x20d2222c
-#define BCHP_RAAGA_DSP_FW_INTH_1_REG_START 0x20d22400
-#define BCHP_RAAGA_DSP_FW_INTH_1_REG_END 0x20d2242c
-#define BCHP_RAAGA_DSP_FW_CFG_1_REG_START 0x20d23000
-#define BCHP_RAAGA_DSP_FW_CFG_1_REG_END 0x20d2357c
-#define BCHP_RAAGA_DSP_MEM_SUBSYSTEM_1_REG_START 0x20d30000
-#define BCHP_RAAGA_DSP_MEM_SUBSYSTEM_1_REG_END 0x20d3bffc
-
-
-/***************************************************************************
- *AUD_FMM_MS_CTRL
- ***************************************************************************/
-/***************************************************************************
- *ABSTRACT_01_MICRO_SEQUENCER_CONTROL - Process to initialize and enable microsequencer
- ***************************************************************************/
-/* AUD_FMM_MS_CTRL :: ABSTRACT_01_MICRO_SEQUENCER_CONTROL :: NULL [31:00] */
-#define BCHP_AUD_FMM_MS_CTRL_ABSTRACT_01_MICRO_SEQUENCER_CONTROL_NULL_MASK 0xffffffff
-#define BCHP_AUD_FMM_MS_CTRL_ABSTRACT_01_MICRO_SEQUENCER_CONTROL_NULL_SHIFT 0
-
-/***************************************************************************
- *ABSTRACT_02_CHANNEL_STATUS - How to control channel status bits
- ***************************************************************************/
-/* AUD_FMM_MS_CTRL :: ABSTRACT_02_CHANNEL_STATUS :: NULL [31:00] */
-#define BCHP_AUD_FMM_MS_CTRL_ABSTRACT_02_CHANNEL_STATUS_NULL_MASK 0xffffffff
-#define BCHP_AUD_FMM_MS_CTRL_ABSTRACT_02_CHANNEL_STATUS_NULL_SHIFT 0
-
-/***************************************************************************
- *AUD_FMM_OP_CTRL
- ***************************************************************************/
-/***************************************************************************
- *ABSTRACT_01_MULTICHANNEL_MAI - Transmitting 6- and 8-channel MAI
- ***************************************************************************/
-/* AUD_FMM_OP_CTRL :: ABSTRACT_01_MULTICHANNEL_MAI :: MORE_INFORMATION [31:00] */
-#define BCHP_AUD_FMM_OP_CTRL_ABSTRACT_01_MULTICHANNEL_MAI_MORE_INFORMATION_MASK 0xffffffff
-#define BCHP_AUD_FMM_OP_CTRL_ABSTRACT_01_MULTICHANNEL_MAI_MORE_INFORMATION_SHIFT 0
-
-/***************************************************************************
- *BVN_MVFD_MFD
- ***************************************************************************/
-/***************************************************************************
- *DRAM_DATA_STRUCTURE - DRAM Data Structure
- ***************************************************************************/
-/* BVN_MVFD_MFD :: DRAM_DATA_STRUCTURE :: DRAM_DATA_STRUCTURE [31:00] */
-#define BCHP_BVN_MVFD_MFD_DRAM_DATA_STRUCTURE_DRAM_DATA_STRUCTURE_MASK 0xffffffff
-#define BCHP_BVN_MVFD_MFD_DRAM_DATA_STRUCTURE_DRAM_DATA_STRUCTURE_SHIFT 0
-
-/***************************************************************************
- *BVN_MVFD_MFD1
- ***************************************************************************/
-/***************************************************************************
- *DRAM_DATA_STRUCTURE - DRAM Data Structure
- ***************************************************************************/
-/* BVN_MVFD_MFD1 :: DRAM_DATA_STRUCTURE :: DRAM_DATA_STRUCTURE [31:00] */
-#define BCHP_BVN_MVFD_MFD1_DRAM_DATA_STRUCTURE_DRAM_DATA_STRUCTURE_MASK 0xffffffff
-#define BCHP_BVN_MVFD_MFD1_DRAM_DATA_STRUCTURE_DRAM_DATA_STRUCTURE_SHIFT 0
-
-/***************************************************************************
- *BVN_MVFD_VFD
- ***************************************************************************/
-/***************************************************************************
- *DRAM_DATA_STRUCTURE - DRAM Data Structure
- ***************************************************************************/
-/* BVN_MVFD_VFD :: DRAM_DATA_STRUCTURE :: DRAM_DATA_STRUCTURE [31:00] */
-#define BCHP_BVN_MVFD_VFD_DRAM_DATA_STRUCTURE_DRAM_DATA_STRUCTURE_MASK 0xffffffff
-#define BCHP_BVN_MVFD_VFD_DRAM_DATA_STRUCTURE_DRAM_DATA_STRUCTURE_SHIFT 0
-
-/***************************************************************************
- *GFD
- ***************************************************************************/
-/***************************************************************************
- *DRAM_DATA_STRUCTURE - DRAM Data Structure
- ***************************************************************************/
-/* GFD :: DRAM_DATA_STRUCTURE :: DRAM_DATA_STRUCTURE [31:00] */
-#define BCHP_GFD_DRAM_DATA_STRUCTURE_DRAM_DATA_STRUCTURE_MASK 0xffffffff
-#define BCHP_GFD_DRAM_DATA_STRUCTURE_DRAM_DATA_STRUCTURE_SHIFT 0
-
-/***************************************************************************
- *GFD_1
- ***************************************************************************/
-/***************************************************************************
- *DRAM_DATA_STRUCTURE - DRAM Data Structure
- ***************************************************************************/
-/* GFD_1 :: DRAM_DATA_STRUCTURE :: DRAM_DATA_STRUCTURE [31:00] */
-#define BCHP_GFD_1_DRAM_DATA_STRUCTURE_DRAM_DATA_STRUCTURE_MASK 0xffffffff
-#define BCHP_GFD_1_DRAM_DATA_STRUCTURE_DRAM_DATA_STRUCTURE_SHIFT 0
-
-/***************************************************************************
- *HIFIDAC_CTRL
- ***************************************************************************/
-/***************************************************************************
- *ABSTRACT_01_COMING_OUT_OF_RESET - Process to come out of reset
- ***************************************************************************/
-/* HIFIDAC_CTRL :: ABSTRACT_01_COMING_OUT_OF_RESET :: MORE_INFORMATION [31:00] */
-#define BCHP_HIFIDAC_CTRL_ABSTRACT_01_COMING_OUT_OF_RESET_MORE_INFORMATION_MASK 0xffffffff
-#define BCHP_HIFIDAC_CTRL_ABSTRACT_01_COMING_OUT_OF_RESET_MORE_INFORMATION_SHIFT 0
-
-/***************************************************************************
- *ABSTRACT_02_MUTE_USAGE - Mute usage
- ***************************************************************************/
-/* HIFIDAC_CTRL :: ABSTRACT_02_MUTE_USAGE :: MORE_INFORMATION [31:00] */
-#define BCHP_HIFIDAC_CTRL_ABSTRACT_02_MUTE_USAGE_MORE_INFORMATION_MASK 0xffffffff
-#define BCHP_HIFIDAC_CTRL_ABSTRACT_02_MUTE_USAGE_MORE_INFORMATION_SHIFT 0
-
-/***************************************************************************
- *ABSTRACT_03_SAMPLE_RATE_CHANGE - Process to effect a sample rate change
- ***************************************************************************/
-/* HIFIDAC_CTRL :: ABSTRACT_03_SAMPLE_RATE_CHANGE :: MORE_INFORMATION [31:00] */
-#define BCHP_HIFIDAC_CTRL_ABSTRACT_03_SAMPLE_RATE_CHANGE_MORE_INFORMATION_MASK 0xffffffff
-#define BCHP_HIFIDAC_CTRL_ABSTRACT_03_SAMPLE_RATE_CHANGE_MORE_INFORMATION_SHIFT 0
-
-/***************************************************************************
- *M2MC
- ***************************************************************************/
-/***************************************************************************
- *TYPE_CLUT_COLOR_DATA - color data for color look up table
- ***************************************************************************/
-/* M2MC :: TYPE_CLUT_COLOR_DATA :: ALPHA [31:24] */
-#define BCHP_M2MC_TYPE_CLUT_COLOR_DATA_ALPHA_MASK 0xff000000
-#define BCHP_M2MC_TYPE_CLUT_COLOR_DATA_ALPHA_SHIFT 24
-
-/* M2MC :: TYPE_CLUT_COLOR_DATA :: RED [23:16] */
-#define BCHP_M2MC_TYPE_CLUT_COLOR_DATA_RED_MASK 0x00ff0000
-#define BCHP_M2MC_TYPE_CLUT_COLOR_DATA_RED_SHIFT 16
-
-/* M2MC :: TYPE_CLUT_COLOR_DATA :: GREEN [15:08] */
-#define BCHP_M2MC_TYPE_CLUT_COLOR_DATA_GREEN_MASK 0x0000ff00
-#define BCHP_M2MC_TYPE_CLUT_COLOR_DATA_GREEN_SHIFT 8
-
-/* M2MC :: TYPE_CLUT_COLOR_DATA :: BLUE [07:00] */
-#define BCHP_M2MC_TYPE_CLUT_COLOR_DATA_BLUE_MASK 0x000000ff
-#define BCHP_M2MC_TYPE_CLUT_COLOR_DATA_BLUE_SHIFT 0
-
-/***************************************************************************
- *LIST_PACKET_ABSTRACT - Linked-List Packet Abstract
- ***************************************************************************/
-/* M2MC :: LIST_PACKET_ABSTRACT :: PACKET_FORMAT [31:00] */
-#define BCHP_M2MC_LIST_PACKET_ABSTRACT_PACKET_FORMAT_MASK 0xffffffff
-#define BCHP_M2MC_LIST_PACKET_ABSTRACT_PACKET_FORMAT_SHIFT 0
-
-/***************************************************************************
- *LIST_PACKET_HEADER_0 - Linked-List Packet Header Word 0
- ***************************************************************************/
-/* M2MC :: LIST_PACKET_HEADER_0 :: reserved0 [31:28] */
-#define BCHP_M2MC_LIST_PACKET_HEADER_0_reserved0_MASK 0xf0000000
-#define BCHP_M2MC_LIST_PACKET_HEADER_0_reserved0_SHIFT 28
-
-/* M2MC :: LIST_PACKET_HEADER_0 :: NEXT_PKT_ADDR [27:05] */
-#define BCHP_M2MC_LIST_PACKET_HEADER_0_NEXT_PKT_ADDR_MASK 0x0fffffe0
-#define BCHP_M2MC_LIST_PACKET_HEADER_0_NEXT_PKT_ADDR_SHIFT 5
-
-/* M2MC :: LIST_PACKET_HEADER_0 :: reserved1 [04:01] */
-#define BCHP_M2MC_LIST_PACKET_HEADER_0_reserved1_MASK 0x0000001e
-#define BCHP_M2MC_LIST_PACKET_HEADER_0_reserved1_SHIFT 1
-
-/* M2MC :: LIST_PACKET_HEADER_0 :: LAST_PKT_IND [00:00] */
-#define BCHP_M2MC_LIST_PACKET_HEADER_0_LAST_PKT_IND_MASK 0x00000001
-#define BCHP_M2MC_LIST_PACKET_HEADER_0_LAST_PKT_IND_SHIFT 0
-#define BCHP_M2MC_LIST_PACKET_HEADER_0_LAST_PKT_IND_NextPktValid 0
-#define BCHP_M2MC_LIST_PACKET_HEADER_0_LAST_PKT_IND_NextPktInvalid 1
-
-/***************************************************************************
- *LIST_PACKET_HEADER_1 - Linked-List Packet Header Word 1
- ***************************************************************************/
-/* M2MC :: LIST_PACKET_HEADER_1 :: reserved0 [31:15] */
-#define BCHP_M2MC_LIST_PACKET_HEADER_1_reserved0_MASK 0xffff8000
-#define BCHP_M2MC_LIST_PACKET_HEADER_1_reserved0_SHIFT 15
-
-/* M2MC :: LIST_PACKET_HEADER_1 :: SRC_FEEDER_GRP_CNTRL [14:14] */
-#define BCHP_M2MC_LIST_PACKET_HEADER_1_SRC_FEEDER_GRP_CNTRL_MASK 0x00004000
-#define BCHP_M2MC_LIST_PACKET_HEADER_1_SRC_FEEDER_GRP_CNTRL_SHIFT 14
-#define BCHP_M2MC_LIST_PACKET_HEADER_1_SRC_FEEDER_GRP_CNTRL_GRP_ENABLE 1
-#define BCHP_M2MC_LIST_PACKET_HEADER_1_SRC_FEEDER_GRP_CNTRL_GRP_DISABLE 0
-
-/* M2MC :: LIST_PACKET_HEADER_1 :: DST_FEEDER_GRP_CNTRL [13:13] */
-#define BCHP_M2MC_LIST_PACKET_HEADER_1_DST_FEEDER_GRP_CNTRL_MASK 0x00002000
-#define BCHP_M2MC_LIST_PACKET_HEADER_1_DST_FEEDER_GRP_CNTRL_SHIFT 13
-#define BCHP_M2MC_LIST_PACKET_HEADER_1_DST_FEEDER_GRP_CNTRL_GRP_ENABLE 1
-#define BCHP_M2MC_LIST_PACKET_HEADER_1_DST_FEEDER_GRP_CNTRL_GRP_DISABLE 0
-
-/* M2MC :: LIST_PACKET_HEADER_1 :: OUTPUT_FEEDER_GRP_CNTRL [12:12] */
-#define BCHP_M2MC_LIST_PACKET_HEADER_1_OUTPUT_FEEDER_GRP_CNTRL_MASK 0x00001000
-#define BCHP_M2MC_LIST_PACKET_HEADER_1_OUTPUT_FEEDER_GRP_CNTRL_SHIFT 12
-#define BCHP_M2MC_LIST_PACKET_HEADER_1_OUTPUT_FEEDER_GRP_CNTRL_GRP_ENABLE 1
-#define BCHP_M2MC_LIST_PACKET_HEADER_1_OUTPUT_FEEDER_GRP_CNTRL_GRP_DISABLE 0
-
-/* M2MC :: LIST_PACKET_HEADER_1 :: BLIT_GRP_CNTRL [11:11] */
-#define BCHP_M2MC_LIST_PACKET_HEADER_1_BLIT_GRP_CNTRL_MASK 0x00000800
-#define BCHP_M2MC_LIST_PACKET_HEADER_1_BLIT_GRP_CNTRL_SHIFT 11
-#define BCHP_M2MC_LIST_PACKET_HEADER_1_BLIT_GRP_CNTRL_GRP_ENABLE 1
-#define BCHP_M2MC_LIST_PACKET_HEADER_1_BLIT_GRP_CNTRL_GRP_DISABLE 0
-
-/* M2MC :: LIST_PACKET_HEADER_1 :: SCALE_PARAM_GRP_CNTRL [10:10] */
-#define BCHP_M2MC_LIST_PACKET_HEADER_1_SCALE_PARAM_GRP_CNTRL_MASK 0x00000400
-#define BCHP_M2MC_LIST_PACKET_HEADER_1_SCALE_PARAM_GRP_CNTRL_SHIFT 10
-#define BCHP_M2MC_LIST_PACKET_HEADER_1_SCALE_PARAM_GRP_CNTRL_GRP_ENABLE 1
-#define BCHP_M2MC_LIST_PACKET_HEADER_1_SCALE_PARAM_GRP_CNTRL_GRP_DISABLE 0
-
-/* M2MC :: LIST_PACKET_HEADER_1 :: BLEND_PARAM_GRP_CNTRL [09:09] */
-#define BCHP_M2MC_LIST_PACKET_HEADER_1_BLEND_PARAM_GRP_CNTRL_MASK 0x00000200
-#define BCHP_M2MC_LIST_PACKET_HEADER_1_BLEND_PARAM_GRP_CNTRL_SHIFT 9
-#define BCHP_M2MC_LIST_PACKET_HEADER_1_BLEND_PARAM_GRP_CNTRL_GRP_ENABLE 1
-#define BCHP_M2MC_LIST_PACKET_HEADER_1_BLEND_PARAM_GRP_CNTRL_GRP_DISABLE 0
-
-/* M2MC :: LIST_PACKET_HEADER_1 :: ROP_GRP_CNTRL [08:08] */
-#define BCHP_M2MC_LIST_PACKET_HEADER_1_ROP_GRP_CNTRL_MASK 0x00000100
-#define BCHP_M2MC_LIST_PACKET_HEADER_1_ROP_GRP_CNTRL_SHIFT 8
-#define BCHP_M2MC_LIST_PACKET_HEADER_1_ROP_GRP_CNTRL_GRP_ENABLE 1
-#define BCHP_M2MC_LIST_PACKET_HEADER_1_ROP_GRP_CNTRL_GRP_DISABLE 0
-
-/* M2MC :: LIST_PACKET_HEADER_1 :: SRC_COLOR_KEY_GRP_CNTRL [07:07] */
-#define BCHP_M2MC_LIST_PACKET_HEADER_1_SRC_COLOR_KEY_GRP_CNTRL_MASK 0x00000080
-#define BCHP_M2MC_LIST_PACKET_HEADER_1_SRC_COLOR_KEY_GRP_CNTRL_SHIFT 7
-#define BCHP_M2MC_LIST_PACKET_HEADER_1_SRC_COLOR_KEY_GRP_CNTRL_GRP_ENABLE 1
-#define BCHP_M2MC_LIST_PACKET_HEADER_1_SRC_COLOR_KEY_GRP_CNTRL_GRP_DISABLE 0
-
-/* M2MC :: LIST_PACKET_HEADER_1 :: DST_COLOR_KEY_GRP_CNTRL [06:06] */
-#define BCHP_M2MC_LIST_PACKET_HEADER_1_DST_COLOR_KEY_GRP_CNTRL_MASK 0x00000040
-#define BCHP_M2MC_LIST_PACKET_HEADER_1_DST_COLOR_KEY_GRP_CNTRL_SHIFT 6
-#define BCHP_M2MC_LIST_PACKET_HEADER_1_DST_COLOR_KEY_GRP_CNTRL_GRP_ENABLE 1
-#define BCHP_M2MC_LIST_PACKET_HEADER_1_DST_COLOR_KEY_GRP_CNTRL_GRP_DISABLE 0
-
-/* M2MC :: LIST_PACKET_HEADER_1 :: SCALE_COEF_GRP_CNTRL [05:05] */
-#define BCHP_M2MC_LIST_PACKET_HEADER_1_SCALE_COEF_GRP_CNTRL_MASK 0x00000020
-#define BCHP_M2MC_LIST_PACKET_HEADER_1_SCALE_COEF_GRP_CNTRL_SHIFT 5
-#define BCHP_M2MC_LIST_PACKET_HEADER_1_SCALE_COEF_GRP_CNTRL_GRP_ENABLE 1
-#define BCHP_M2MC_LIST_PACKET_HEADER_1_SCALE_COEF_GRP_CNTRL_GRP_DISABLE 0
-
-/* M2MC :: LIST_PACKET_HEADER_1 :: SRC_COLOR_MATRIX_GRP_CNTRL [04:04] */
-#define BCHP_M2MC_LIST_PACKET_HEADER_1_SRC_COLOR_MATRIX_GRP_CNTRL_MASK 0x00000010
-#define BCHP_M2MC_LIST_PACKET_HEADER_1_SRC_COLOR_MATRIX_GRP_CNTRL_SHIFT 4
-#define BCHP_M2MC_LIST_PACKET_HEADER_1_SRC_COLOR_MATRIX_GRP_CNTRL_GRP_ENABLE 1
-#define BCHP_M2MC_LIST_PACKET_HEADER_1_SRC_COLOR_MATRIX_GRP_CNTRL_GRP_DISABLE 0
-
-/* M2MC :: LIST_PACKET_HEADER_1 :: DST_COLOR_MATRIX_GRP_CNTRL [03:03] */
-#define BCHP_M2MC_LIST_PACKET_HEADER_1_DST_COLOR_MATRIX_GRP_CNTRL_MASK 0x00000008
-#define BCHP_M2MC_LIST_PACKET_HEADER_1_DST_COLOR_MATRIX_GRP_CNTRL_SHIFT 3
-#define BCHP_M2MC_LIST_PACKET_HEADER_1_DST_COLOR_MATRIX_GRP_CNTRL_GRP_ENABLE 1
-#define BCHP_M2MC_LIST_PACKET_HEADER_1_DST_COLOR_MATRIX_GRP_CNTRL_GRP_DISABLE 0
-
-/* M2MC :: LIST_PACKET_HEADER_1 :: OUTPUT_COLOR_MATRIX_GRP_CNTRL [02:02] */
-#define BCHP_M2MC_LIST_PACKET_HEADER_1_OUTPUT_COLOR_MATRIX_GRP_CNTRL_MASK 0x00000004
-#define BCHP_M2MC_LIST_PACKET_HEADER_1_OUTPUT_COLOR_MATRIX_GRP_CNTRL_SHIFT 2
-#define BCHP_M2MC_LIST_PACKET_HEADER_1_OUTPUT_COLOR_MATRIX_GRP_CNTRL_GRP_ENABLE 1
-#define BCHP_M2MC_LIST_PACKET_HEADER_1_OUTPUT_COLOR_MATRIX_GRP_CNTRL_GRP_DISABLE 0
-
-/* M2MC :: LIST_PACKET_HEADER_1 :: SRC_CLUT_GRP_CNTRL [01:01] */
-#define BCHP_M2MC_LIST_PACKET_HEADER_1_SRC_CLUT_GRP_CNTRL_MASK 0x00000002
-#define BCHP_M2MC_LIST_PACKET_HEADER_1_SRC_CLUT_GRP_CNTRL_SHIFT 1
-#define BCHP_M2MC_LIST_PACKET_HEADER_1_SRC_CLUT_GRP_CNTRL_GRP_ENABLE 1
-#define BCHP_M2MC_LIST_PACKET_HEADER_1_SRC_CLUT_GRP_CNTRL_GRP_DISABLE 0
-
-/* M2MC :: LIST_PACKET_HEADER_1 :: DST_CLUT_GRP_CNTRL [00:00] */
-#define BCHP_M2MC_LIST_PACKET_HEADER_1_DST_CLUT_GRP_CNTRL_MASK 0x00000001
-#define BCHP_M2MC_LIST_PACKET_HEADER_1_DST_CLUT_GRP_CNTRL_SHIFT 0
-#define BCHP_M2MC_LIST_PACKET_HEADER_1_DST_CLUT_GRP_CNTRL_GRP_ENABLE 1
-#define BCHP_M2MC_LIST_PACKET_HEADER_1_DST_CLUT_GRP_CNTRL_GRP_DISABLE 0
-
-/***************************************************************************
- *LIST_PKT_00_SRC_FEEDER_N - Linked-List Packet Word N for group SRC_FEEDER
- ***************************************************************************/
-/* M2MC :: LIST_PKT_00_SRC_FEEDER_N :: REGISTER_CONTENTS [31:00] */
-#define BCHP_M2MC_LIST_PKT_00_SRC_FEEDER_N_REGISTER_CONTENTS_MASK 0xffffffff
-#define BCHP_M2MC_LIST_PKT_00_SRC_FEEDER_N_REGISTER_CONTENTS_SHIFT 0
-
-/***************************************************************************
- *LIST_PKT_01_DST_FEEDER_N - Linked-List Packet Word N for group DST_FEEDER
- ***************************************************************************/
-/* M2MC :: LIST_PKT_01_DST_FEEDER_N :: REGISTER_CONTENTS [31:00] */
-#define BCHP_M2MC_LIST_PKT_01_DST_FEEDER_N_REGISTER_CONTENTS_MASK 0xffffffff
-#define BCHP_M2MC_LIST_PKT_01_DST_FEEDER_N_REGISTER_CONTENTS_SHIFT 0
-
-/***************************************************************************
- *LIST_PKT_02_OUTPUT_FEEDER_N - Linked-List Packet Word N for group OUTPUT_FEEDER
- ***************************************************************************/
-/* M2MC :: LIST_PKT_02_OUTPUT_FEEDER_N :: REGISTER_CONTENTS [31:00] */
-#define BCHP_M2MC_LIST_PKT_02_OUTPUT_FEEDER_N_REGISTER_CONTENTS_MASK 0xffffffff
-#define BCHP_M2MC_LIST_PKT_02_OUTPUT_FEEDER_N_REGISTER_CONTENTS_SHIFT 0
-
-/***************************************************************************
- *LIST_PKT_03_BLIT_N - Linked-List Packet Word N for group BLIT
- ***************************************************************************/
-/* M2MC :: LIST_PKT_03_BLIT_N :: REGISTER_CONTENTS [31:00] */
-#define BCHP_M2MC_LIST_PKT_03_BLIT_N_REGISTER_CONTENTS_MASK 0xffffffff
-#define BCHP_M2MC_LIST_PKT_03_BLIT_N_REGISTER_CONTENTS_SHIFT 0
-
-/***************************************************************************
- *LIST_PKT_04_SCALE_PARAM_N - Linked-List Packet Word N for group SCALE_PARAM
- ***************************************************************************/
-/* M2MC :: LIST_PKT_04_SCALE_PARAM_N :: REGISTER_CONTENTS [31:00] */
-#define BCHP_M2MC_LIST_PKT_04_SCALE_PARAM_N_REGISTER_CONTENTS_MASK 0xffffffff
-#define BCHP_M2MC_LIST_PKT_04_SCALE_PARAM_N_REGISTER_CONTENTS_SHIFT 0
-
-/***************************************************************************
- *LIST_PKT_05_BLEND_PARAM_N - Linked-List Packet Word N for group BLEND_PARAM
- ***************************************************************************/
-/* M2MC :: LIST_PKT_05_BLEND_PARAM_N :: REGISTER_CONTENTS [31:00] */
-#define BCHP_M2MC_LIST_PKT_05_BLEND_PARAM_N_REGISTER_CONTENTS_MASK 0xffffffff
-#define BCHP_M2MC_LIST_PKT_05_BLEND_PARAM_N_REGISTER_CONTENTS_SHIFT 0
-
-/***************************************************************************
- *LIST_PKT_06_ROP_N - Linked-List Packet Word N for group ROP
- ***************************************************************************/
-/* M2MC :: LIST_PKT_06_ROP_N :: REGISTER_CONTENTS [31:00] */
-#define BCHP_M2MC_LIST_PKT_06_ROP_N_REGISTER_CONTENTS_MASK 0xffffffff
-#define BCHP_M2MC_LIST_PKT_06_ROP_N_REGISTER_CONTENTS_SHIFT 0
-
-/***************************************************************************
- *LIST_PKT_07_SRC_COLOR_KEY_N - Linked-List Packet Word N for group SRC_COLOR_KEY
- ***************************************************************************/
-/* M2MC :: LIST_PKT_07_SRC_COLOR_KEY_N :: REGISTER_CONTENTS [31:00] */
-#define BCHP_M2MC_LIST_PKT_07_SRC_COLOR_KEY_N_REGISTER_CONTENTS_MASK 0xffffffff
-#define BCHP_M2MC_LIST_PKT_07_SRC_COLOR_KEY_N_REGISTER_CONTENTS_SHIFT 0
-
-/***************************************************************************
- *LIST_PKT_08_DST_COLOR_KEY_N - Linked-List Packet Word N for group DST_COLOR_KEY
- ***************************************************************************/
-/* M2MC :: LIST_PKT_08_DST_COLOR_KEY_N :: REGISTER_CONTENTS [31:00] */
-#define BCHP_M2MC_LIST_PKT_08_DST_COLOR_KEY_N_REGISTER_CONTENTS_MASK 0xffffffff
-#define BCHP_M2MC_LIST_PKT_08_DST_COLOR_KEY_N_REGISTER_CONTENTS_SHIFT 0
-
-/***************************************************************************
- *LIST_PKT_09_SCALE_COEF_N - Linked-List Packet Word N for group SCALE_COEF
- ***************************************************************************/
-/* M2MC :: LIST_PKT_09_SCALE_COEF_N :: REGISTER_CONTENTS [31:00] */
-#define BCHP_M2MC_LIST_PKT_09_SCALE_COEF_N_REGISTER_CONTENTS_MASK 0xffffffff
-#define BCHP_M2MC_LIST_PKT_09_SCALE_COEF_N_REGISTER_CONTENTS_SHIFT 0
-
-/***************************************************************************
- *LIST_PKT_10_SRC_COLOR_MATRIX_N - Linked-List Packet Word N for group SRC_COLOR_MATRIX
- ***************************************************************************/
-/* M2MC :: LIST_PKT_10_SRC_COLOR_MATRIX_N :: REGISTER_CONTENTS [31:00] */
-#define BCHP_M2MC_LIST_PKT_10_SRC_COLOR_MATRIX_N_REGISTER_CONTENTS_MASK 0xffffffff
-#define BCHP_M2MC_LIST_PKT_10_SRC_COLOR_MATRIX_N_REGISTER_CONTENTS_SHIFT 0
-
-/***************************************************************************
- *LIST_PKT_11_SRC_CLUT - Linked-List Packet Word for group SRC_CLUT
- ***************************************************************************/
-/* M2MC :: LIST_PKT_11_SRC_CLUT :: reserved0 [31:29] */
-#define BCHP_M2MC_LIST_PKT_11_SRC_CLUT_reserved0_MASK 0xe0000000
-#define BCHP_M2MC_LIST_PKT_11_SRC_CLUT_reserved0_SHIFT 29
-
-/* M2MC :: LIST_PKT_11_SRC_CLUT :: REGISTER_CONTENTS [28:00] */
-#define BCHP_M2MC_LIST_PKT_11_SRC_CLUT_REGISTER_CONTENTS_MASK 0x1fffffff
-#define BCHP_M2MC_LIST_PKT_11_SRC_CLUT_REGISTER_CONTENTS_SHIFT 0
-
-/***************************************************************************
- *PCIE_DMA
- ***************************************************************************/
-/***************************************************************************
- *DESC_WORD0 - PCIE DMA Descriptor Word 0
- ***************************************************************************/
-/* PCIE_DMA :: DESC_WORD0 :: MEMORY_ADDRESS [31:00] */
-#define BCHP_PCIE_DMA_DESC_WORD0_MEMORY_ADDRESS_MASK 0xffffffff
-#define BCHP_PCIE_DMA_DESC_WORD0_MEMORY_ADDRESS_SHIFT 0
-
-/***************************************************************************
- *DESC_WORD1 - PCIE DMA Descriptor Word 1
- ***************************************************************************/
-/* PCIE_DMA :: DESC_WORD1 :: PCIE_ADDRESS_LO [31:00] */
-#define BCHP_PCIE_DMA_DESC_WORD1_PCIE_ADDRESS_LO_MASK 0xffffffff
-#define BCHP_PCIE_DMA_DESC_WORD1_PCIE_ADDRESS_LO_SHIFT 0
-
-/***************************************************************************
- *DESC_WORD2 - PCIE DMA Descriptor Word 2
- ***************************************************************************/
-/* PCIE_DMA :: DESC_WORD2 :: PCIE_ADDRESS_HI [31:00] */
-#define BCHP_PCIE_DMA_DESC_WORD2_PCIE_ADDRESS_HI_MASK 0xffffffff
-#define BCHP_PCIE_DMA_DESC_WORD2_PCIE_ADDRESS_HI_SHIFT 0
-
-/***************************************************************************
- *DESC_WORD3 - PCIE DMA Descriptor Word 3
- ***************************************************************************/
-/* PCIE_DMA :: DESC_WORD3 :: INTERRUPT_ENABLE [31:31] */
-#define BCHP_PCIE_DMA_DESC_WORD3_INTERRUPT_ENABLE_MASK 0x80000000
-#define BCHP_PCIE_DMA_DESC_WORD3_INTERRUPT_ENABLE_SHIFT 31
-
-/* PCIE_DMA :: DESC_WORD3 :: reserved0 [30:25] */
-#define BCHP_PCIE_DMA_DESC_WORD3_reserved0_MASK 0x7e000000
-#define BCHP_PCIE_DMA_DESC_WORD3_reserved0_SHIFT 25
-
-/* PCIE_DMA :: DESC_WORD3 :: DMA_TRANSFER_SIZE [24:00] */
-#define BCHP_PCIE_DMA_DESC_WORD3_DMA_TRANSFER_SIZE_MASK 0x01ffffff
-#define BCHP_PCIE_DMA_DESC_WORD3_DMA_TRANSFER_SIZE_SHIFT 0
-
-/***************************************************************************
- *DESC_WORD4 - PCIE DMA Descriptor Word 4
- ***************************************************************************/
-/* PCIE_DMA :: DESC_WORD4 :: LAST_RECORD_INDICATOR [31:31] */
-#define BCHP_PCIE_DMA_DESC_WORD4_LAST_RECORD_INDICATOR_MASK 0x80000000
-#define BCHP_PCIE_DMA_DESC_WORD4_LAST_RECORD_INDICATOR_SHIFT 31
-
-/* PCIE_DMA :: DESC_WORD4 :: DMA_DIRECTION [30:30] */
-#define BCHP_PCIE_DMA_DESC_WORD4_DMA_DIRECTION_MASK 0x40000000
-#define BCHP_PCIE_DMA_DESC_WORD4_DMA_DIRECTION_SHIFT 30
-#define BCHP_PCIE_DMA_DESC_WORD4_DMA_DIRECTION_PCIE_TO_MEMORY 1
-#define BCHP_PCIE_DMA_DESC_WORD4_DMA_DIRECTION_MEMORY_TO_PCIE 0
-
-/* PCIE_DMA :: DESC_WORD4 :: reserved0 [29:03] */
-#define BCHP_PCIE_DMA_DESC_WORD4_reserved0_MASK 0x3ffffff8
-#define BCHP_PCIE_DMA_DESC_WORD4_reserved0_SHIFT 3
-
-/* PCIE_DMA :: DESC_WORD4 :: DESC_CONTIGUOUS [02:02] */
-#define BCHP_PCIE_DMA_DESC_WORD4_DESC_CONTIGUOUS_MASK 0x00000004
-#define BCHP_PCIE_DMA_DESC_WORD4_DESC_CONTIGUOUS_SHIFT 2
-
-/* PCIE_DMA :: DESC_WORD4 :: ENDIAN_XLATE_MODE [01:00] */
-#define BCHP_PCIE_DMA_DESC_WORD4_ENDIAN_XLATE_MODE_MASK 0x00000003
-#define BCHP_PCIE_DMA_DESC_WORD4_ENDIAN_XLATE_MODE_SHIFT 0
-#define BCHP_PCIE_DMA_DESC_WORD4_ENDIAN_XLATE_MODE_NO_SWAP 0
-#define BCHP_PCIE_DMA_DESC_WORD4_ENDIAN_XLATE_MODE_SWAP_16_IN_32 1
-#define BCHP_PCIE_DMA_DESC_WORD4_ENDIAN_XLATE_MODE_SWAP_32 2
-#define BCHP_PCIE_DMA_DESC_WORD4_ENDIAN_XLATE_MODE_reserved 3
-
-/***************************************************************************
- *DESC_WORD5 - PCIE DMA Descriptor Word 5
- ***************************************************************************/
-/* PCIE_DMA :: DESC_WORD5 :: NEXT_DESC_ADDRESS_LO [31:05] */
-#define BCHP_PCIE_DMA_DESC_WORD5_NEXT_DESC_ADDRESS_LO_MASK 0xffffffe0
-#define BCHP_PCIE_DMA_DESC_WORD5_NEXT_DESC_ADDRESS_LO_SHIFT 5
-
-/* PCIE_DMA :: DESC_WORD5 :: reserved0 [04:00] */
-#define BCHP_PCIE_DMA_DESC_WORD5_reserved0_MASK 0x0000001f
-#define BCHP_PCIE_DMA_DESC_WORD5_reserved0_SHIFT 0
-
-/***************************************************************************
- *DESC_WORD6 - PCIE DMA Descriptor Word 6
- ***************************************************************************/
-/* PCIE_DMA :: DESC_WORD6 :: NEXT_DESC_ADDRESS_HI [31:00] */
-#define BCHP_PCIE_DMA_DESC_WORD6_NEXT_DESC_ADDRESS_HI_MASK 0xffffffff
-#define BCHP_PCIE_DMA_DESC_WORD6_NEXT_DESC_ADDRESS_HI_SHIFT 0
-
-/***************************************************************************
- *DESC_WORD7 - PCIE DMA Descriptor Word 7
- ***************************************************************************/
-/* PCIE_DMA :: DESC_WORD7 :: reserved0 [31:08] */
-#define BCHP_PCIE_DMA_DESC_WORD7_reserved0_MASK 0xffffff00
-#define BCHP_PCIE_DMA_DESC_WORD7_reserved0_SHIFT 8
-
-/* PCIE_DMA :: DESC_WORD7 :: MEMORY_ADDRESS_HI [07:00] */
-#define BCHP_PCIE_DMA_DESC_WORD7_MEMORY_ADDRESS_HI_MASK 0x000000ff
-#define BCHP_PCIE_DMA_DESC_WORD7_MEMORY_ADDRESS_HI_SHIFT 0
-
-/***************************************************************************
- *RAAGA_REGSET_DSP_CFG
- ***************************************************************************/
-/***************************************************************************
- *AC3_UPS_WORD_00 - AC3 User Parameters Structure Word 0 - DYNRNGSCALEHI
- ***************************************************************************/
-/* RAAGA_REGSET_DSP_CFG :: AC3_UPS_WORD_00 :: DYNRNGSCALEHI [15:00] */
-#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_00_DYNRNGSCALEHI_MASK 0xffff
-#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_00_DYNRNGSCALEHI_SHIFT 0
-#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_00_DYNRNGSCALEHI_No_compression 0
-#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_00_DYNRNGSCALEHI_Full_compression 32767
-
-/***************************************************************************
- *AC3_UPS_WORD_01 - AC3 User Parameters Structure Word 1 - DYNRNGSCALELOW
- ***************************************************************************/
-/* RAAGA_REGSET_DSP_CFG :: AC3_UPS_WORD_01 :: DYNRNGSCALELOW [15:00] */
-#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_01_DYNRNGSCALELOW_MASK 0xffff
-#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_01_DYNRNGSCALELOW_SHIFT 0
-#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_01_DYNRNGSCALELOW_No_compression 0
-#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_01_DYNRNGSCALELOW_Full_compression 32767
-
-/***************************************************************************
- *AC3_UPS_WORD_02 - AC3 User Parameters Structure Word 2 - PCMSCALEFAC
- ***************************************************************************/
-/* RAAGA_REGSET_DSP_CFG :: AC3_UPS_WORD_02 :: PCMSCALEFAC [15:00] */
-#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_02_PCMSCALEFAC_MASK 0xffff
-#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_02_PCMSCALEFAC_SHIFT 0
-#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_02_PCMSCALEFAC_Full_scale 32767
-#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_02_PCMSCALEFAC_Mute 0
-
-/***************************************************************************
- *AC3_UPS_WORD_03 - AC3 User Parameters Structure Word 3 - COMPMODE
- ***************************************************************************/
-/* RAAGA_REGSET_DSP_CFG :: AC3_UPS_WORD_03 :: COMPMODE [15:00] */
-#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_03_COMPMODE_MASK 0xffff
-#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_03_COMPMODE_SHIFT 0
-#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_03_COMPMODE_Comp_custom_a 0
-#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_03_COMPMODE_Comp_custom_d 1
-#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_03_COMPMODE_Comp_line 2
-#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_03_COMPMODE_Comp_rf 3
-
-/***************************************************************************
- *AC3_UPS_WORD_04 - AC3 User Parameters Structure Word 4 - DUALMONOMODE
- ***************************************************************************/
-/* RAAGA_REGSET_DSP_CFG :: AC3_UPS_WORD_04 :: DUALMONOMODE [15:00] */
-#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_04_DUALMONOMODE_MASK 0xffff
-#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_04_DUALMONOMODE_SHIFT 0
-#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_04_DUALMONOMODE_Pass_through 0
-#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_04_DUALMONOMODE_Left_mono 1
-#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_04_DUALMONOMODE_Right_mono 2
-#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_04_DUALMONOMODE_True_mono 3
-
-/***************************************************************************
- *AC3_UPS_WORD_05 - AC3 User Parameters Structure Word 5 - OUTPUTMODE
- ***************************************************************************/
-/* RAAGA_REGSET_DSP_CFG :: AC3_UPS_WORD_05 :: OUTPUTMODE [15:00] */
-#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_05_OUTPUTMODE_MASK 0xffff
-#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_05_OUTPUTMODE_SHIFT 0
-#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_05_OUTPUTMODE_Mode11 0
-#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_05_OUTPUTMODE_Mode10 1
-#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_05_OUTPUTMODE_Mode20 2
-#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_05_OUTPUTMODE_Mode30 3
-#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_05_OUTPUTMODE_Mode21 4
-#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_05_OUTPUTMODE_Mode31 5
-#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_05_OUTPUTMODE_Mode22 6
-#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_05_OUTPUTMODE_Mode32 7
-
-/***************************************************************************
- *AC3_UPS_WORD_06 - AC3 User Parameters Structure Word 6 - OUTLFEON
- ***************************************************************************/
-/* RAAGA_REGSET_DSP_CFG :: AC3_UPS_WORD_06 :: OUTLFEON [15:00] */
-#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_06_OUTLFEON_MASK 0xffff
-#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_06_OUTLFEON_SHIFT 0
-#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_06_OUTLFEON_Off 0
-#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_06_OUTLFEON_On 1
-
-/***************************************************************************
- *AC3_UPS_WORD_07 - AC3 User Parameters Structure Word 7 - KCAPABLEMODE
- ***************************************************************************/
-/* RAAGA_REGSET_DSP_CFG :: AC3_UPS_WORD_07 :: KCAPABLEMODE [15:00] */
-#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_07_KCAPABLEMODE_MASK 0xffff
-#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_07_KCAPABLEMODE_SHIFT 0
-#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_07_KCAPABLEMODE_No_vocal_channels 0
-#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_07_KCAPABLEMODE_Vocal_channel_V1 1
-#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_07_KCAPABLEMODE_Vocal_channel_V2 2
-#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_07_KCAPABLEMODE_Both_vocal_channels 3
-
-/***************************************************************************
- *AC3_UPS_WORD_08 - AC3 User Parameters Structure Word 8 - KARAOKE_PARAMETER_FLAG
- ***************************************************************************/
-/* RAAGA_REGSET_DSP_CFG :: AC3_UPS_WORD_08 :: KARAOKE_PARAMETER_FLAG [15:00] */
-#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_08_KARAOKE_PARAMETER_FLAG_MASK 0xffff
-#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_08_KARAOKE_PARAMETER_FLAG_SHIFT 0
-#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_08_KARAOKE_PARAMETER_FLAG_Off 0
-#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_08_KARAOKE_PARAMETER_FLAG_On 1
-
-/***************************************************************************
- *AC3_UPS_WORD_09 - AC3 User Parameters Structure Word 9 - KARAOKE_V1_LEVEL
- ***************************************************************************/
-/* RAAGA_REGSET_DSP_CFG :: AC3_UPS_WORD_09 :: KARAOKE_V1_LEVEL [15:00] */
-#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_09_KARAOKE_V1_LEVEL_MASK 0xffff
-#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_09_KARAOKE_V1_LEVEL_SHIFT 0
-#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_09_KARAOKE_V1_LEVEL_Full_scale 32767
-#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_09_KARAOKE_V1_LEVEL_Mute 0
-
-/***************************************************************************
- *AC3_UPS_WORD_10 - AC3 User Parameters Structure Word 10 - KARAOKE_V1_PAN
- ***************************************************************************/
-/* RAAGA_REGSET_DSP_CFG :: AC3_UPS_WORD_10 :: KARAOKE_V1_PAN [15:00] */
-#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_10_KARAOKE_V1_PAN_MASK 0xffff
-#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_10_KARAOKE_V1_PAN_SHIFT 0
-#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_10_KARAOKE_V1_PAN_Hard_left 32767
-#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_10_KARAOKE_V1_PAN_Middle 0
-#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_10_KARAOKE_V1_PAN_Hard_right 32768
-
-/***************************************************************************
- *AC3_UPS_WORD_11 - AC3 User Parameters Structure Word 11 - KARAOKE_V2_LEVEL
- ***************************************************************************/
-/* RAAGA_REGSET_DSP_CFG :: AC3_UPS_WORD_11 :: KARAOKE_V2_LEVEL [15:00] */
-#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_11_KARAOKE_V2_LEVEL_MASK 0xffff
-#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_11_KARAOKE_V2_LEVEL_SHIFT 0
-#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_11_KARAOKE_V2_LEVEL_Full_scale 32767
-#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_11_KARAOKE_V2_LEVEL_Mute 0
-
-/***************************************************************************
- *AC3_UPS_WORD_12 - AC3 User Parameters Structure Word 12 - KARAOKE_V2_PAN
- ***************************************************************************/
-/* RAAGA_REGSET_DSP_CFG :: AC3_UPS_WORD_12 :: KARAOKE_V2_PAN [15:00] */
-#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_12_KARAOKE_V2_PAN_MASK 0xffff
-#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_12_KARAOKE_V2_PAN_SHIFT 0
-#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_12_KARAOKE_V2_PAN_Hard_left 32767
-#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_12_KARAOKE_V2_PAN_Middle 0
-#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_12_KARAOKE_V2_PAN_Hard_right 32768
-
-/***************************************************************************
- *AC3_UPS_WORD_13 - AC3 User Parameters Structure Word 13 - KARAOKE_GM_LEVEL
- ***************************************************************************/
-/* RAAGA_REGSET_DSP_CFG :: AC3_UPS_WORD_13 :: KARAOKE_GM_LEVEL [15:00] */
-#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_13_KARAOKE_GM_LEVEL_MASK 0xffff
-#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_13_KARAOKE_GM_LEVEL_SHIFT 0
-#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_13_KARAOKE_GM_LEVEL_Full_scale 32767
-#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_13_KARAOKE_GM_LEVEL_Mute 0
-
-/***************************************************************************
- *AC3_UPS_WORD_14 - AC3 User Parameters Structure Word 14 - KARAOKE_GM_PAN
- ***************************************************************************/
-/* RAAGA_REGSET_DSP_CFG :: AC3_UPS_WORD_14 :: KARAOKE_GM_PAN [15:00] */
-#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_14_KARAOKE_GM_PAN_MASK 0xffff
-#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_14_KARAOKE_GM_PAN_SHIFT 0
-#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_14_KARAOKE_GM_PAN_Hard_left 32767
-#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_14_KARAOKE_GM_PAN_Middle 0
-#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_14_KARAOKE_GM_PAN_Hard_right 32768
-
-/***************************************************************************
- *AC3_UPS_WORD_15 - AC3 User Parameters Structure Word 15 - STEREO_MOD
- ***************************************************************************/
-/* RAAGA_REGSET_DSP_CFG :: AC3_UPS_WORD_15 :: STEREO_MOD [15:00] */
-#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_15_STEREO_MOD_MASK 0xffff
-#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_15_STEREO_MOD_SHIFT 0
-#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_15_STEREO_MOD_Auto 0
-#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_15_STEREO_MOD_LtRt 1
-#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_15_STEREO_MOD_LoRo 2
-
-/***************************************************************************
- *AC3_UPS_WORD_16 - AC3 User Parameters Structure Word 16 - USER_DOWNMIX_FLAG
- ***************************************************************************/
-/* RAAGA_REGSET_DSP_CFG :: AC3_UPS_WORD_16 :: USER_DOWNMIX_FLAG [15:00] */
-#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_16_USER_DOWNMIX_FLAG_MASK 0xffff
-#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_16_USER_DOWNMIX_FLAG_SHIFT 0
-#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_16_USER_DOWNMIX_FLAG_Off 0
-#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_16_USER_DOWNMIX_FLAG_On 1
-
-/***************************************************************************
- *AC3_UPS_WORD_17_TO_52 - AC3 User Parameters Structure Word 17 to 52 - DRAM_USER_DEFINED_DNMX_COEFFS
- ***************************************************************************/
-/* RAAGA_REGSET_DSP_CFG :: AC3_UPS_WORD_17_TO_52 :: DRAM_USER_DEFINED_DNMX_COEFFS [15:00] */
-#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_17_TO_52_DRAM_USER_DEFINED_DNMX_COEFFS_MASK 0xffff
-#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_17_TO_52_DRAM_USER_DEFINED_DNMX_COEFFS_SHIFT 0
-#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_17_TO_52_DRAM_USER_DEFINED_DNMX_COEFFS_Full_scale 32767
-#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_17_TO_52_DRAM_USER_DEFINED_DNMX_COEFFS_Mute 0
-
-/***************************************************************************
- *AC3_UPS_WORD_53 - AC3 User Parameters Structure Word 53 - DUMMY
- ***************************************************************************/
-/* RAAGA_REGSET_DSP_CFG :: AC3_UPS_WORD_53 :: DUMMY [15:00] */
-#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_53_DUMMY_MASK 0xffff
-#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_53_DUMMY_SHIFT 0
-
-/***************************************************************************
- *AC3_PLUS_UPS_WORD_00 - AC3 Plus User Parameters Structure Word 0 - COMPMODE
- ***************************************************************************/
-/* RAAGA_REGSET_DSP_CFG :: AC3_PLUS_UPS_WORD_00 :: COMPMODE [31:00] */
-#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_00_COMPMODE_MASK 0xffffffff
-#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_00_COMPMODE_SHIFT 0
-
-/***************************************************************************
- *AC3_PLUS_UPS_WORD_01 - AC3 Plus User Parameters Structure Word 1 - PCMSCALE
- ***************************************************************************/
-/* RAAGA_REGSET_DSP_CFG :: AC3_PLUS_UPS_WORD_01 :: PCMSCALE [31:00] */
-#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_01_PCMSCALE_MASK 0xffffffff
-#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_01_PCMSCALE_SHIFT 0
-#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_01_PCMSCALE_Full_scale 2147483647
-#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_01_PCMSCALE_Mute 0
-
-/***************************************************************************
- *AC3_PLUS_UPS_WORD_02 - AC3 Plus User Parameters Structure Word 2 - DYNSCALEHIGH
- ***************************************************************************/
-/* RAAGA_REGSET_DSP_CFG :: AC3_PLUS_UPS_WORD_02 :: DYNSCALEHIGH [31:00] */
-#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_02_DYNSCALEHIGH_MASK 0xffffffff
-#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_02_DYNSCALEHIGH_SHIFT 0
-
-/***************************************************************************
- *AC3_PLUS_UPS_WORD_03 - AC3 Plus User Parameters Structure Word 3 - DYNSCALELOW
- ***************************************************************************/
-/* RAAGA_REGSET_DSP_CFG :: AC3_PLUS_UPS_WORD_03 :: DYNSCALELOW [31:00] */
-#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_03_DYNSCALELOW_MASK 0xffffffff
-#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_03_DYNSCALELOW_SHIFT 0
-
-/***************************************************************************
- *AC3_PLUS_UPS_WORD_04 - AC3 Plus User Parameters Structure Word 4 - OUTLFE
- ***************************************************************************/
-/* RAAGA_REGSET_DSP_CFG :: AC3_PLUS_UPS_WORD_04 :: OUTLFE [31:00] */
-#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_04_OUTLFE_MASK 0xffffffff
-#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_04_OUTLFE_SHIFT 0
-
-/***************************************************************************
- *AC3_PLUS_UPS_WORD_05 - AC3 Plus User Parameters Structure Word 5 - OUTMODE
- ***************************************************************************/
-/* RAAGA_REGSET_DSP_CFG :: AC3_PLUS_UPS_WORD_05 :: OUTMODE [31:00] */
-#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_05_OUTMODE_MASK 0xffffffff
-#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_05_OUTMODE_SHIFT 0
-
-/***************************************************************************
- *AC3_PLUS_UPS_WORD_06 - AC3 Plus User Parameters Structure Word 6 - STEREOMODE
- ***************************************************************************/
-/* RAAGA_REGSET_DSP_CFG :: AC3_PLUS_UPS_WORD_06 :: STEREOMODE [31:00] */
-#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_06_STEREOMODE_MASK 0xffffffff
-#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_06_STEREOMODE_SHIFT 0
-
-/***************************************************************************
- *AC3_PLUS_UPS_WORD_07 - AC3 Plus User Parameters Structure Word 7 - DUALMODE
- ***************************************************************************/
-/* RAAGA_REGSET_DSP_CFG :: AC3_PLUS_UPS_WORD_07 :: DUALMODE [31:00] */
-#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_07_DUALMODE_MASK 0xffffffff
-#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_07_DUALMODE_SHIFT 0
-
-/***************************************************************************
- *AC3_PLUS_UPS_WORD_08 - AC3 Plus User Parameters Structure Word 8 - KMODE
- ***************************************************************************/
-/* RAAGA_REGSET_DSP_CFG :: AC3_PLUS_UPS_WORD_08 :: KMODE [31:00] */
-#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_08_KMODE_MASK 0xffffffff
-#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_08_KMODE_SHIFT 0
-#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_08_KMODE_NO_VOCALS 0
-#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_08_KMODE_GBL_VOCAL1 1
-#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_08_KMODE_GBL_VOCAL2 2
-#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_08_KMODE_GBL_BOTH_VOCALS 3
-
-/***************************************************************************
- *AC3_PLUS_UPS_WORD_09 - AC3 Plus User Parameters Structure Word 9 - EXTDNMIX_ENABLED
- ***************************************************************************/
-/* RAAGA_REGSET_DSP_CFG :: AC3_PLUS_UPS_WORD_09 :: EXTDNMIX_ENABLED [31:00] */
-#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_09_EXTDNMIX_ENABLED_MASK 0xffffffff
-#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_09_EXTDNMIX_ENABLED_SHIFT 0
-
-/***************************************************************************
- *AC3_PLUS_UPS_WORD_10_TO_45 - AC3 Plus User Parameters Structure Word 10 to 45 - EXTDNMIXTAB
- ***************************************************************************/
-/* RAAGA_REGSET_DSP_CFG :: AC3_PLUS_UPS_WORD_10_TO_45 :: EXTDNMIXTAB [31:00] */
-#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_10_TO_45_EXTDNMIXTAB_MASK 0xffffffff
-#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_10_TO_45_EXTDNMIXTAB_SHIFT 0
-#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_10_TO_45_EXTDNMIXTAB_Full_scale 2147483647
-#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_10_TO_45_EXTDNMIXTAB_Mute 0
-
-/***************************************************************************
- *AC3_PLUS_UPS_WORD_46 - AC3 Plus User Parameters Structure Word 46 - EXTKARAOKE_ENABLED
- ***************************************************************************/
-/* RAAGA_REGSET_DSP_CFG :: AC3_PLUS_UPS_WORD_46 :: EXTKARAOKE_ENABLED [31:00] */
-#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_46_EXTKARAOKE_ENABLED_MASK 0xffffffff
-#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_46_EXTKARAOKE_ENABLED_SHIFT 0
-
-/***************************************************************************
- *AC3_PLUS_UPS_WORD_47 - AC3 Plus User Parameters Structure Word 47 - EXT_V1_LEVEL
- ***************************************************************************/
-/* RAAGA_REGSET_DSP_CFG :: AC3_PLUS_UPS_WORD_47 :: EXT_V1_LEVEL [31:00] */
-#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_47_EXT_V1_LEVEL_MASK 0xffffffff
-#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_47_EXT_V1_LEVEL_SHIFT 0
-#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_47_EXT_V1_LEVEL_Full_scale 2147483647
-#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_47_EXT_V1_LEVEL_Mute 0
-
-/***************************************************************************
- *AC3_PLUS_UPS_WORD_48 - AC3 Plus User Parameters Structure Word 48 - EXT_V1_PAN
- ***************************************************************************/
-/* RAAGA_REGSET_DSP_CFG :: AC3_PLUS_UPS_WORD_48 :: EXT_V1_PAN [31:00] */
-#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_48_EXT_V1_PAN_MASK 0xffffffff
-#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_48_EXT_V1_PAN_SHIFT 0
-#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_48_EXT_V1_PAN_Hard_left 2147483647
-#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_48_EXT_V1_PAN_Middle 0
-#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_48_EXT_V1_PAN_Hard_right -2147483648
-
-/***************************************************************************
- *AC3_PLUS_UPS_WORD_49 - AC3 Plus User Parameters Structure Word 49 - EXT_V2_LEVEL
- ***************************************************************************/
-/* RAAGA_REGSET_DSP_CFG :: AC3_PLUS_UPS_WORD_49 :: EXT_V2_LEVEL [31:00] */
-#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_49_EXT_V2_LEVEL_MASK 0xffffffff
-#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_49_EXT_V2_LEVEL_SHIFT 0
-#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_49_EXT_V2_LEVEL_Full_scale 2147483647
-#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_49_EXT_V2_LEVEL_Mute 0
-
-/***************************************************************************
- *AC3_PLUS_UPS_WORD_50 - AC3 Plus User Parameters Structure Word 50 - EXT_V2_PAN
- ***************************************************************************/
-/* RAAGA_REGSET_DSP_CFG :: AC3_PLUS_UPS_WORD_50 :: EXT_V2_PAN [31:00] */
-#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_50_EXT_V2_PAN_MASK 0xffffffff
-#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_50_EXT_V2_PAN_SHIFT 0
-#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_50_EXT_V2_PAN_Hard_left 2147483647
-#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_50_EXT_V2_PAN_Middle 0
-#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_50_EXT_V2_PAN_Hard_right -2147483648
-
-/***************************************************************************
- *AC3_PLUS_UPS_WORD_51 - AC3 Plus User Parameters Structure Word 51 - EXT_GM_LEVEL
- ***************************************************************************/
-/* RAAGA_REGSET_DSP_CFG :: AC3_PLUS_UPS_WORD_51 :: EXT_GM_LEVEL [31:00] */
-#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_51_EXT_GM_LEVEL_MASK 0xffffffff
-#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_51_EXT_GM_LEVEL_SHIFT 0
-#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_51_EXT_GM_LEVEL_Full_scale 2147483647
-#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_51_EXT_GM_LEVEL_Mute 0
-
-/***************************************************************************
- *AC3_PLUS_UPS_WORD_52 - AC3 Plus User Parameters Structure Word 52 - EXT_GM_PAN
- ***************************************************************************/
-/* RAAGA_REGSET_DSP_CFG :: AC3_PLUS_UPS_WORD_52 :: EXT_GM_PAN [31:00] */
-#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_52_EXT_GM_PAN_MASK 0xffffffff
-#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_52_EXT_GM_PAN_SHIFT 0
-#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_52_EXT_GM_PAN_Hard_left 2147483647
-#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_52_EXT_GM_PAN_Middle 0
-#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_52_EXT_GM_PAN_Hard_right -2147483648
-
-/***************************************************************************
- *AAC_UPS_WORD_00 - AAC User Parameters Structure Word 0 - XPT_FORMAT
- ***************************************************************************/
-/* RAAGA_REGSET_DSP_CFG :: AAC_UPS_WORD_00 :: XPT_FORMAT [31:00] */
-#define BCHP_RAAGA_REGSET_DSP_CFG_AAC_UPS_WORD_00_XPT_FORMAT_MASK 0xffffffff
-#define BCHP_RAAGA_REGSET_DSP_CFG_AAC_UPS_WORD_00_XPT_FORMAT_SHIFT 0
-
-/***************************************************************************
- *AAC_UPS_WORD_01 - AAC User Parameters Structure Word 1 - DRC_GAIN_CONTROL_COMPRESS
- ***************************************************************************/
-/* RAAGA_REGSET_DSP_CFG :: AAC_UPS_WORD_01 :: DRC_GAIN_CONTROL_COMPRESS [31:00] */
-#define BCHP_RAAGA_REGSET_DSP_CFG_AAC_UPS_WORD_01_DRC_GAIN_CONTROL_COMPRESS_MASK 0xffffffff
-#define BCHP_RAAGA_REGSET_DSP_CFG_AAC_UPS_WORD_01_DRC_GAIN_CONTROL_COMPRESS_SHIFT 0
-
-/***************************************************************************
- *AAC_UPS_WORD_02 - AAC User Parameters Structure Word 2 - DRC_GAIN_CONTROL_BOOST
- ***************************************************************************/
-/* RAAGA_REGSET_DSP_CFG :: AAC_UPS_WORD_02 :: DRC_GAIN_CONTROL_BOOST [31:00] */
-#define BCHP_RAAGA_REGSET_DSP_CFG_AAC_UPS_WORD_02_DRC_GAIN_CONTROL_BOOST_MASK 0xffffffff
-#define BCHP_RAAGA_REGSET_DSP_CFG_AAC_UPS_WORD_02_DRC_GAIN_CONTROL_BOOST_SHIFT 0
-
-/***************************************************************************
- *AAC_UPS_WORD_03 - AAC User Parameters Structure Word 3 - DRC_TARGET_LEVEL
- ***************************************************************************/
-/* RAAGA_REGSET_DSP_CFG :: AAC_UPS_WORD_03 :: DRC_TARGET_LEVEL [31:00] */
-#define BCHP_RAAGA_REGSET_DSP_CFG_AAC_UPS_WORD_03_DRC_TARGET_LEVEL_MASK 0xffffffff
-#define BCHP_RAAGA_REGSET_DSP_CFG_AAC_UPS_WORD_03_DRC_TARGET_LEVEL_SHIFT 0
-
-/***************************************************************************
- *AAC_UPS_WORD_04 - AAC User Parameters Structure Word 4 - DOWNMIX_TYPE
- ***************************************************************************/
-/* RAAGA_REGSET_DSP_CFG :: AAC_UPS_WORD_04 :: DOWNMIX_TYPE [31:00] */
-#define BCHP_RAAGA_REGSET_DSP_CFG_AAC_UPS_WORD_04_DOWNMIX_TYPE_MASK 0xffffffff
-#define BCHP_RAAGA_REGSET_DSP_CFG_AAC_UPS_WORD_04_DOWNMIX_TYPE_SHIFT 0
-
-/***************************************************************************
- *AAC_UPS_WORD_05 - AAC User Parameters Structure Word 5 - OUTMODE
- ***************************************************************************/
-/* RAAGA_REGSET_DSP_CFG :: AAC_UPS_WORD_05 :: OUTMODE [31:00] */
-#define BCHP_RAAGA_REGSET_DSP_CFG_AAC_UPS_WORD_05_OUTMODE_MASK 0xffffffff
-#define BCHP_RAAGA_REGSET_DSP_CFG_AAC_UPS_WORD_05_OUTMODE_SHIFT 0
-#define BCHP_RAAGA_REGSET_DSP_CFG_AAC_UPS_WORD_05_OUTMODE_Stereo 2
-#define BCHP_RAAGA_REGSET_DSP_CFG_AAC_UPS_WORD_05_OUTMODE_Mono 1
-
-/***************************************************************************
- *AAC_UPS_WORD_06 - AAC User Parameters Structure Word 6 - DUALMODE
- ***************************************************************************/
-/* RAAGA_REGSET_DSP_CFG :: AAC_UPS_WORD_06 :: DUALMODE [31:00] */
-#define BCHP_RAAGA_REGSET_DSP_CFG_AAC_UPS_WORD_06_DUALMODE_MASK 0xffffffff
-#define BCHP_RAAGA_REGSET_DSP_CFG_AAC_UPS_WORD_06_DUALMODE_SHIFT 0
-#define BCHP_RAAGA_REGSET_DSP_CFG_AAC_UPS_WORD_06_DUALMODE_Left_mono 0
-#define BCHP_RAAGA_REGSET_DSP_CFG_AAC_UPS_WORD_06_DUALMODE_Right_mono 1
-#define BCHP_RAAGA_REGSET_DSP_CFG_AAC_UPS_WORD_06_DUALMODE_Dual_stereo 2
-#define BCHP_RAAGA_REGSET_DSP_CFG_AAC_UPS_WORD_06_DUALMODE_Dual_mixmono 3
-
-/***************************************************************************
- *DTS_CORE_UPS_WORD_00 - DTS Core User Parameters Structure Word 0 - OUTMODE
- ***************************************************************************/
-/* RAAGA_REGSET_DSP_CFG :: DTS_CORE_UPS_WORD_00 :: OUTMODE [31:00] */
-#define BCHP_RAAGA_REGSET_DSP_CFG_DTS_CORE_UPS_WORD_00_OUTMODE_MASK 0xffffffff
-#define BCHP_RAAGA_REGSET_DSP_CFG_DTS_CORE_UPS_WORD_00_OUTMODE_SHIFT 0
-#define BCHP_RAAGA_REGSET_DSP_CFG_DTS_CORE_UPS_WORD_00_OUTMODE_Stereo 0
-#define BCHP_RAAGA_REGSET_DSP_CFG_DTS_CORE_UPS_WORD_00_OUTMODE_Mono 1
-
-/***************************************************************************
- *DTS_CORE_UPS_WORD_01 - DTS Core User Parameters Structure Word 1 - OUTLFE
- ***************************************************************************/
-/* RAAGA_REGSET_DSP_CFG :: DTS_CORE_UPS_WORD_01 :: OUTLFE [31:00] */
-#define BCHP_RAAGA_REGSET_DSP_CFG_DTS_CORE_UPS_WORD_01_OUTLFE_MASK 0xffffffff
-#define BCHP_RAAGA_REGSET_DSP_CFG_DTS_CORE_UPS_WORD_01_OUTLFE_SHIFT 0
-
-/***************************************************************************
- *DTS_CORE_UPS_WORD_02 - DTS Core User Parameters Structure Word 2 - DUALMODE
- ***************************************************************************/
-/* RAAGA_REGSET_DSP_CFG :: DTS_CORE_UPS_WORD_02 :: DUALMODE [31:00] */
-#define BCHP_RAAGA_REGSET_DSP_CFG_DTS_CORE_UPS_WORD_02_DUALMODE_MASK 0xffffffff
-#define BCHP_RAAGA_REGSET_DSP_CFG_DTS_CORE_UPS_WORD_02_DUALMODE_SHIFT 0
-#define BCHP_RAAGA_REGSET_DSP_CFG_DTS_CORE_UPS_WORD_02_DUALMODE_Dual_stereo 0
-#define BCHP_RAAGA_REGSET_DSP_CFG_DTS_CORE_UPS_WORD_02_DUALMODE_Dual_leftmono 1
-#define BCHP_RAAGA_REGSET_DSP_CFG_DTS_CORE_UPS_WORD_02_DUALMODE_Dual_rghtmono 2
-#define BCHP_RAAGA_REGSET_DSP_CFG_DTS_CORE_UPS_WORD_02_DUALMODE_Dual_mixmono 3
-
-/***************************************************************************
- *DTS_CORE_UPS_WORD_03 - DTS Core User Parameters Structure Word 3 - STEREOMODE
- ***************************************************************************/
-/* RAAGA_REGSET_DSP_CFG :: DTS_CORE_UPS_WORD_03 :: STEREOMODE [31:00] */
-#define BCHP_RAAGA_REGSET_DSP_CFG_DTS_CORE_UPS_WORD_03_STEREOMODE_MASK 0xffffffff
-#define BCHP_RAAGA_REGSET_DSP_CFG_DTS_CORE_UPS_WORD_03_STEREOMODE_SHIFT 0
-#define BCHP_RAAGA_REGSET_DSP_CFG_DTS_CORE_UPS_WORD_03_STEREOMODE_Stereomode_auto 0
-#define BCHP_RAAGA_REGSET_DSP_CFG_DTS_CORE_UPS_WORD_03_STEREOMODE_Stereodmix_LTRT 1
-#define BCHP_RAAGA_REGSET_DSP_CFG_DTS_CORE_UPS_WORD_03_STEREOMODE_Stereodmix_LORO 2
-
-/***************************************************************************
- *DTS_CORE_UPS_WORD_04 - DTS Core User Parameters Structure Word 4 - EXTDNMIX_ENABLED
- ***************************************************************************/
-/* RAAGA_REGSET_DSP_CFG :: DTS_CORE_UPS_WORD_04 :: EXTDNMIX_ENABLED [31:00] */
-#define BCHP_RAAGA_REGSET_DSP_CFG_DTS_CORE_UPS_WORD_04_EXTDNMIX_ENABLED_MASK 0xffffffff
-#define BCHP_RAAGA_REGSET_DSP_CFG_DTS_CORE_UPS_WORD_04_EXTDNMIX_ENABLED_SHIFT 0
-
-/***************************************************************************
- *DTS_CORE_UPS_WORD_05_TO_40 - DTS Core User Parameters Structure Word 5 to 40 - EXTDNMIXTAB
- ***************************************************************************/
-/* RAAGA_REGSET_DSP_CFG :: DTS_CORE_UPS_WORD_05_TO_40 :: EXTDNMIXTAB [31:00] */
-#define BCHP_RAAGA_REGSET_DSP_CFG_DTS_CORE_UPS_WORD_05_TO_40_EXTDNMIXTAB_MASK 0xffffffff
-#define BCHP_RAAGA_REGSET_DSP_CFG_DTS_CORE_UPS_WORD_05_TO_40_EXTDNMIXTAB_SHIFT 0
-#define BCHP_RAAGA_REGSET_DSP_CFG_DTS_CORE_UPS_WORD_05_TO_40_EXTDNMIXTAB_Full_scale 2147483647
-#define BCHP_RAAGA_REGSET_DSP_CFG_DTS_CORE_UPS_WORD_05_TO_40_EXTDNMIXTAB_Mute 0
-
-/***************************************************************************
- *LPCM_UPS_WORD_00 - LPCM User Parameters Structure Word 0 - EXTDNMIX_ENABLED
- ***************************************************************************/
-/* RAAGA_REGSET_DSP_CFG :: LPCM_UPS_WORD_00 :: EXTDNMIX_ENABLED [31:00] */
-#define BCHP_RAAGA_REGSET_DSP_CFG_LPCM_UPS_WORD_00_EXTDNMIX_ENABLED_MASK 0xffffffff
-#define BCHP_RAAGA_REGSET_DSP_CFG_LPCM_UPS_WORD_00_EXTDNMIX_ENABLED_SHIFT 0
-
-/***************************************************************************
- *LPCM_UPS_WORD_01_TO_16 - LPCM User Parameters Structure Word 1 to 16 - EXTDNMIXTAB
- ***************************************************************************/
-/* RAAGA_REGSET_DSP_CFG :: LPCM_UPS_WORD_01_TO_16 :: EXTDNMIXTAB [31:00] */
-#define BCHP_RAAGA_REGSET_DSP_CFG_LPCM_UPS_WORD_01_TO_16_EXTDNMIXTAB_MASK 0xffffffff
-#define BCHP_RAAGA_REGSET_DSP_CFG_LPCM_UPS_WORD_01_TO_16_EXTDNMIXTAB_SHIFT 0
-#define BCHP_RAAGA_REGSET_DSP_CFG_LPCM_UPS_WORD_01_TO_16_EXTDNMIXTAB_Full_scale 2147483647
-#define BCHP_RAAGA_REGSET_DSP_CFG_LPCM_UPS_WORD_01_TO_16_EXTDNMIXTAB_Mute 0
-
-/***************************************************************************
- *MPEG_UPS_WORD_00 - MPEG User Parameters Structure Word 0 - OUTMODE
- ***************************************************************************/
-/* RAAGA_REGSET_DSP_CFG :: MPEG_UPS_WORD_00 :: OUTMODE [31:00] */
-#define BCHP_RAAGA_REGSET_DSP_CFG_MPEG_UPS_WORD_00_OUTMODE_MASK 0xffffffff
-#define BCHP_RAAGA_REGSET_DSP_CFG_MPEG_UPS_WORD_00_OUTMODE_SHIFT 0
-#define BCHP_RAAGA_REGSET_DSP_CFG_MPEG_UPS_WORD_00_OUTMODE_Stereo 0
-#define BCHP_RAAGA_REGSET_DSP_CFG_MPEG_UPS_WORD_00_OUTMODE_Mono 1
-
-/***************************************************************************
- *MPEG_UPS_WORD_01 - MPEG User Parameters Structure Word 1 - DUALMODE
- ***************************************************************************/
-/* RAAGA_REGSET_DSP_CFG :: MPEG_UPS_WORD_01 :: DUALMODE [31:00] */
-#define BCHP_RAAGA_REGSET_DSP_CFG_MPEG_UPS_WORD_01_DUALMODE_MASK 0xffffffff
-#define BCHP_RAAGA_REGSET_DSP_CFG_MPEG_UPS_WORD_01_DUALMODE_SHIFT 0
-#define BCHP_RAAGA_REGSET_DSP_CFG_MPEG_UPS_WORD_01_DUALMODE_Left_mono 0
-#define BCHP_RAAGA_REGSET_DSP_CFG_MPEG_UPS_WORD_01_DUALMODE_Right_mono 1
-#define BCHP_RAAGA_REGSET_DSP_CFG_MPEG_UPS_WORD_01_DUALMODE_Dual_stereo 2
-#define BCHP_RAAGA_REGSET_DSP_CFG_MPEG_UPS_WORD_01_DUALMODE_Dual_mixmono 3
-
-/***************************************************************************
- *RDC
- ***************************************************************************/
-/***************************************************************************
- *RUL - RUL Command.
- ***************************************************************************/
-/* RDC :: RUL :: opcode [31:24] */
-#define BCHP_RDC_RUL_opcode_MASK 0xff000000
-#define BCHP_RDC_RUL_opcode_SHIFT 24
-#define BCHP_RDC_RUL_opcode_NOP 0
-#define BCHP_RDC_RUL_opcode_REG_WRITE_IMM 1
-#define BCHP_RDC_RUL_opcode_REG_WRITE 2
-#define BCHP_RDC_RUL_opcode_REG_READ 3
-#define BCHP_RDC_RUL_opcode_LOAD_IMM 4
-#define BCHP_RDC_RUL_opcode_WINDOW_WRITE 5
-#define BCHP_RDC_RUL_opcode_BLOCK_WRITE 6
-#define BCHP_RDC_RUL_opcode_WINDOW_COPY 7
-#define BCHP_RDC_RUL_opcode_BLOCK_COPY 8
-#define BCHP_RDC_RUL_opcode_WINDOW_TO_BLOCK 9
-#define BCHP_RDC_RUL_opcode_BLOCK_TO_WINDOW 10
-#define BCHP_RDC_RUL_opcode_AND 11
-#define BCHP_RDC_RUL_opcode_AND_IMM 12
-#define BCHP_RDC_RUL_opcode_OR 13
-#define BCHP_RDC_RUL_opcode_OR_IMM 14
-#define BCHP_RDC_RUL_opcode_XOR 15
-#define BCHP_RDC_RUL_opcode_XOR_IMM 16
-#define BCHP_RDC_RUL_opcode_NOT 17
-#define BCHP_RDC_RUL_opcode_ROTATE_RIGHT 18
-#define BCHP_RDC_RUL_opcode_SUM 19
-#define BCHP_RDC_RUL_opcode_SUM_IMM 20
-#define BCHP_RDC_RUL_opcode_COND_SKIP 21
-#define BCHP_RDC_RUL_opcode_SKIP 22
-#define BCHP_RDC_RUL_opcode_EXIT 23
-#define BCHP_RDC_RUL_opcode_WAIT_EOP 24
-#define BCHP_RDC_RUL_opcode_PLACEHOLDER 255
-
-/* RDC :: RUL :: reserved0 [23:23] */
-#define BCHP_RDC_RUL_reserved0_MASK 0x00800000
-#define BCHP_RDC_RUL_reserved0_SHIFT 23
-
-/* union - case rdc_args [22:00] */
-/* RDC :: RUL :: rdc_args :: rotation [22:18] */
-#define BCHP_RDC_RUL_rdc_args_rotation_MASK 0x007c0000
-#define BCHP_RDC_RUL_rdc_args_rotation_SHIFT 18
-
-/* RDC :: RUL :: rdc_args :: src1 [17:12] */
-#define BCHP_RDC_RUL_rdc_args_src1_MASK 0x0003f000
-#define BCHP_RDC_RUL_rdc_args_src1_SHIFT 12
-
-/* RDC :: RUL :: rdc_args :: src2 [11:06] */
-#define BCHP_RDC_RUL_rdc_args_src2_MASK 0x00000fc0
-#define BCHP_RDC_RUL_rdc_args_src2_SHIFT 6
-
-/* RDC :: RUL :: rdc_args :: dest [05:00] */
-#define BCHP_RDC_RUL_rdc_args_dest_MASK 0x0000003f
-#define BCHP_RDC_RUL_rdc_args_dest_SHIFT 0
-
-/* union - case reg_args [22:00] */
-/* RDC :: RUL :: reg_args :: rotation [22:18] */
-#define BCHP_RDC_RUL_reg_args_rotation_MASK 0x007c0000
-#define BCHP_RDC_RUL_reg_args_rotation_SHIFT 18
-
-/* RDC :: RUL :: reg_args :: src1 [17:12] */
-#define BCHP_RDC_RUL_reg_args_src1_MASK 0x0003f000
-#define BCHP_RDC_RUL_reg_args_src1_SHIFT 12
-
-/* RDC :: RUL :: reg_args :: count [11:00] */
-#define BCHP_RDC_RUL_reg_args_count_MASK 0x00000fff
-#define BCHP_RDC_RUL_reg_args_count_SHIFT 0
-
-/* union - case eop_args [22:00] */
-/* RDC :: RUL :: eop_args :: reserved0 [22:08] */
-#define BCHP_RDC_RUL_eop_args_reserved0_MASK 0x007fff00
-#define BCHP_RDC_RUL_eop_args_reserved0_SHIFT 8
-
-/* RDC :: RUL :: eop_args :: eop [07:00] */
-#define BCHP_RDC_RUL_eop_args_eop_MASK 0x000000ff
-#define BCHP_RDC_RUL_eop_args_eop_SHIFT 0
-
-/***************************************************************************
- *EOP_ID_256 - EOP_ID
- ***************************************************************************/
-/* RDC :: EOP_ID_256 :: eop_id [255:00] */
-#define BCHP_RDC_EOP_ID_256_eop_id_MASK 0x00000000000000000000000000000000000000000000000000000000ffffffff
-#define BCHP_RDC_EOP_ID_256_eop_id_SHIFT 0
-#define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_scl_0 0
-#define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_scl_1 1
-#define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_scl_2 2
-#define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_scl_3 3
-#define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_scl_4 4
-#define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_scl_5 5
-#define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_scl_6 6
-#define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_scl_7 7
-#define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_mvp_0 8
-#define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_mvp_1 9
-#define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_mvp_2 10
-#define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_mvp_3 11
-#define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_mvp_4 12
-#define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_mvp_5 13
-#define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_mvp_6 14
-#define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_mvp_7 15
-#define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_dnr_0 16
-#define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_dnr_1 17
-#define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_dnr_2 18
-#define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_dnr_3 19
-#define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_dnr_4 20
-#define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_dnr_5 21
-#define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_dnr_6 22
-#define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_dnr_7 23
-#define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_lbox_0 24
-#define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_lbox_1 25
-#define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_lbox_2 26
-#define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_lbox_3 27
-#define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_lbox_4 28
-#define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_lbox_5 29
-#define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_lbox_6 30
-#define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_pfa_0 31
-#define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_null_0 32
-#define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_null_1 33
-#define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_null_2 34
-#define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_null_3 35
-#define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_null_4 36
-#define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_null_5 37
-#define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_null_6 38
-#define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_null_7 39
-#define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_nvp_0 40
-#define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_s3dh_0 41
-#define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_v0_be 42
-#define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_reserved_0 43
-#define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_reserved_1 44
-#define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_reserved_2 45
-#define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_reserved_3 46
-#define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_reserved_4 47
-#define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_fch_0 48
-#define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_fch_1 49
-#define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_fch_2 50
-#define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_fch_3 51
-#define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_fch_4 52
-#define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_fch_5 53
-#define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_fch_6 54
-#define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_fch_7 55
-#define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_fch_8 56
-#define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_fch_9 57
-#define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_fch_10 58
-#define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_fch_11 59
-#define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_fch_12 60
-#define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_fch_13 61
-#define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_reserved_7 62
-#define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_reserved_8 63
-#define BCHP_RDC_EOP_ID_256_eop_id_mfd_0 64
-#define BCHP_RDC_EOP_ID_256_eop_id_mfd_1 65
-#define BCHP_RDC_EOP_ID_256_eop_id_mfd_2 66
-#define BCHP_RDC_EOP_ID_256_eop_id_mfd_3 67
-#define BCHP_RDC_EOP_ID_256_eop_id_mfd_4 68
-#define BCHP_RDC_EOP_ID_256_eop_id_mfd_5 69
-#define BCHP_RDC_EOP_ID_256_eop_id_mfd_6 70
-#define BCHP_RDC_EOP_ID_256_eop_id_mfd_7 71
-#define BCHP_RDC_EOP_ID_256_eop_id_vfd_0 72
-#define BCHP_RDC_EOP_ID_256_eop_id_vfd_1 73
-#define BCHP_RDC_EOP_ID_256_eop_id_vfd_2 74
-#define BCHP_RDC_EOP_ID_256_eop_id_vfd_3 75
-#define BCHP_RDC_EOP_ID_256_eop_id_vfd_4 76
-#define BCHP_RDC_EOP_ID_256_eop_id_vfd_5 77
-#define BCHP_RDC_EOP_ID_256_eop_id_vfd_6 78
-#define BCHP_RDC_EOP_ID_256_eop_id_vfd_7 79
-#define BCHP_RDC_EOP_ID_256_eop_id_cap_0 80
-#define BCHP_RDC_EOP_ID_256_eop_id_cap_1 81
-#define BCHP_RDC_EOP_ID_256_eop_id_cap_2 82
-#define BCHP_RDC_EOP_ID_256_eop_id_cap_3 83
-#define BCHP_RDC_EOP_ID_256_eop_id_cap_4 84
-#define BCHP_RDC_EOP_ID_256_eop_id_cap_5 85
-#define BCHP_RDC_EOP_ID_256_eop_id_cap_6 86
-#define BCHP_RDC_EOP_ID_256_eop_id_cap_7 87
-#define BCHP_RDC_EOP_ID_256_eop_id_gfd_0 88
-#define BCHP_RDC_EOP_ID_256_eop_id_gfd_1 89
-#define BCHP_RDC_EOP_ID_256_eop_id_gfd_2 90
-#define BCHP_RDC_EOP_ID_256_eop_id_gfd_3 91
-#define BCHP_RDC_EOP_ID_256_eop_id_gfd_4 92
-#define BCHP_RDC_EOP_ID_256_eop_id_gfd_5 93
-#define BCHP_RDC_EOP_ID_256_eop_id_gfd_6 94
-#define BCHP_RDC_EOP_ID_256_eop_id_gfd_7 95
-#define BCHP_RDC_EOP_ID_256_eop_id_scl_0 96
-#define BCHP_RDC_EOP_ID_256_eop_id_scl_1 97
-#define BCHP_RDC_EOP_ID_256_eop_id_scl_2 98
-#define BCHP_RDC_EOP_ID_256_eop_id_scl_3 99
-#define BCHP_RDC_EOP_ID_256_eop_id_scl_4 100
-#define BCHP_RDC_EOP_ID_256_eop_id_scl_5 101
-#define BCHP_RDC_EOP_ID_256_eop_id_scl_6 102
-#define BCHP_RDC_EOP_ID_256_eop_id_scl_7 103
-#define BCHP_RDC_EOP_ID_256_eop_id_hscl_0 104
-#define BCHP_RDC_EOP_ID_256_eop_id_hscl_1 105
-#define BCHP_RDC_EOP_ID_256_eop_id_hscl_2 106
-#define BCHP_RDC_EOP_ID_256_eop_id_hscl_3 107
-#define BCHP_RDC_EOP_ID_256_eop_id_hscl_4 108
-#define BCHP_RDC_EOP_ID_256_eop_id_hscl_5 109
-#define BCHP_RDC_EOP_ID_256_eop_id_hscl_6 110
-#define BCHP_RDC_EOP_ID_256_eop_id_hscl_7 111
-#define BCHP_RDC_EOP_ID_256_eop_id_mvp_0 112
-#define BCHP_RDC_EOP_ID_256_eop_id_mvp_1 113
-#define BCHP_RDC_EOP_ID_256_eop_id_mvp_2 114
-#define BCHP_RDC_EOP_ID_256_eop_id_mvp_3 115
-#define BCHP_RDC_EOP_ID_256_eop_id_mvp_4 116
-#define BCHP_RDC_EOP_ID_256_eop_id_mvp_5 117
-#define BCHP_RDC_EOP_ID_256_eop_id_mvp_6 118
-#define BCHP_RDC_EOP_ID_256_eop_id_mvp_7 119
-#define BCHP_RDC_EOP_ID_256_eop_id_dnr_0 120
-#define BCHP_RDC_EOP_ID_256_eop_id_dnr_1 121
-#define BCHP_RDC_EOP_ID_256_eop_id_dnr_2 122
-#define BCHP_RDC_EOP_ID_256_eop_id_dnr_3 123
-#define BCHP_RDC_EOP_ID_256_eop_id_dnr_4 124
-#define BCHP_RDC_EOP_ID_256_eop_id_dnr_5 125
-#define BCHP_RDC_EOP_ID_256_eop_id_dnr_6 126
-#define BCHP_RDC_EOP_ID_256_eop_id_dnr_7 127
-#define BCHP_RDC_EOP_ID_256_eop_id_cmp_0 128
-#define BCHP_RDC_EOP_ID_256_eop_id_cmp_1 129
-#define BCHP_RDC_EOP_ID_256_eop_id_cmp_2 130
-#define BCHP_RDC_EOP_ID_256_eop_id_cmp_3 131
-#define BCHP_RDC_EOP_ID_256_eop_id_cmp_4 132
-#define BCHP_RDC_EOP_ID_256_eop_id_cmp_5 133
-#define BCHP_RDC_EOP_ID_256_eop_id_cmp_6 134
-#define BCHP_RDC_EOP_ID_256_eop_id_cmp_7 135
-#define BCHP_RDC_EOP_ID_256_eop_id_hd_dvi_0 136
-#define BCHP_RDC_EOP_ID_256_eop_id_hd_dvi_1 137
-#define BCHP_RDC_EOP_ID_256_eop_id_hd_dvi_2 138
-#define BCHP_RDC_EOP_ID_256_eop_id_hd_dvi_3 139
-#define BCHP_RDC_EOP_ID_256_eop_id_hd_dvi_4 140
-#define BCHP_RDC_EOP_ID_256_eop_id_hd_dvi_5 141
-#define BCHP_RDC_EOP_ID_256_eop_id_hd_dvi_6 142
-#define BCHP_RDC_EOP_ID_256_eop_id_tpg_0 143
-#define BCHP_RDC_EOP_ID_256_eop_id_vec_0 144
-#define BCHP_RDC_EOP_ID_256_eop_id_vec_1 145
-#define BCHP_RDC_EOP_ID_256_eop_id_vec_2 146
-#define BCHP_RDC_EOP_ID_256_eop_id_vec_3 147
-#define BCHP_RDC_EOP_ID_256_eop_id_vec_4 148
-#define BCHP_RDC_EOP_ID_256_eop_id_vec_5 149
-#define BCHP_RDC_EOP_ID_256_eop_id_vec_6 150
-#define BCHP_RDC_EOP_ID_256_eop_id_vec_7 151
-#define BCHP_RDC_EOP_ID_256_eop_id_lbox_0 152
-#define BCHP_RDC_EOP_ID_256_eop_id_lbox_1 153
-#define BCHP_RDC_EOP_ID_256_eop_id_lbox_2 154
-#define BCHP_RDC_EOP_ID_256_eop_id_lbox_3 155
-#define BCHP_RDC_EOP_ID_256_eop_id_lbox_4 156
-#define BCHP_RDC_EOP_ID_256_eop_id_lbox_5 157
-#define BCHP_RDC_EOP_ID_256_eop_id_lbox_6 158
-#define BCHP_RDC_EOP_ID_256_eop_id_pfa_0 159
-#define BCHP_RDC_EOP_ID_256_eop_id_crc_0 160
-#define BCHP_RDC_EOP_ID_256_eop_id_crc_1 161
-#define BCHP_RDC_EOP_ID_256_eop_id_crc_2 162
-#define BCHP_RDC_EOP_ID_256_eop_id_crc_3 163
-#define BCHP_RDC_EOP_ID_256_eop_id_hist_0 164
-#define BCHP_RDC_EOP_ID_256_eop_id_hist_1 165
-#define BCHP_RDC_EOP_ID_256_eop_id_psm_0 166
-#define BCHP_RDC_EOP_ID_256_eop_id_plm_0 167
-#define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_cap_0 168
-#define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_cap_1 169
-#define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_cap_2 170
-#define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_cap_3 171
-#define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_cap_4 172
-#define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_cap_5 173
-#define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_cap_6 174
-#define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_cap_7 175
-#define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_crc_0 176
-#define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_crc_1 177
-#define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_crc_2 178
-#define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_crc_3 179
-#define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_hist_0 180
-#define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_hist_1 181
-#define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_psm_0 182
-#define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_plm_0 183
-#define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_cmp_0_v0 184
-#define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_cmp_1_v0 185
-#define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_cmp_2_v0 186
-#define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_cmp_3_v0 187
-#define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_cmp_4_v0 188
-#define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_cmp_5_v0 189
-#define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_cmp_6_v0 190
-#define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_cmp_7_v0 191
-#define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_cmp_0_v1 192
-#define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_cmp_1_v1 193
-#define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_cmp_2_v1 194
-#define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_cmp_3_v1 195
-#define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_cmp_4_v1 196
-#define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_cmp_5_v1 197
-#define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_cmp_6_v1 198
-#define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_cmp_7_v1 199
-#define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_null_0 200
-#define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_null_1 201
-#define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_null_2 202
-#define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_null_3 203
-#define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_null_4 204
-#define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_null_5 205
-#define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_null_6 206
-#define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_null_7 207
-#define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_b3dc_0 208
-#define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_frc_0 209
-#define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_reserved_0 210
-#define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_reserved_1 211
-#define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_reserved_2 212
-#define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_reserved_3 213
-#define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_reserved_4 214
-#define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_reserved_5 215
-#define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_loopback_0 216
-#define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_loopback_1 217
-#define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_loopback_2 218
-#define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_loopback_3 219
-#define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_loopback_4 220
-#define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_loopback_5 221
-#define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_loopback_6 222
-#define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_loopback_7 223
-#define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_loopback_8 224
-#define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_loopback_9 225
-#define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_loopback_10 226
-#define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_loopback_11 227
-#define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_reserved_6 228
-#define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_reserved_7 229
-#define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_reserved_8 230
-#define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_reserved_9 231
-#define BCHP_RDC_EOP_ID_256_eop_id_nvp_0 232
-#define BCHP_RDC_EOP_ID_256_eop_id_s3dh_0 233
-#define BCHP_RDC_EOP_ID_256_eop_id_v0_be 234
-#define BCHP_RDC_EOP_ID_256_eop_id_reserved_0 235
-#define BCHP_RDC_EOP_ID_256_eop_id_reserved_1 236
-#define BCHP_RDC_EOP_ID_256_eop_id_reserved_2 237
-#define BCHP_RDC_EOP_ID_256_eop_id_reserved_3 238
-#define BCHP_RDC_EOP_ID_256_eop_id_reserved_4 239
-#define BCHP_RDC_EOP_ID_256_eop_id_b3dc_0 240
-#define BCHP_RDC_EOP_ID_256_eop_id_frc_0 241
-#define BCHP_RDC_EOP_ID_256_eop_id_pdpf_0 242
-#define BCHP_RDC_EOP_ID_256_eop_id_pdpb_0 243
-#define BCHP_RDC_EOP_ID_256_eop_id_reserved_5 244
-#define BCHP_RDC_EOP_ID_256_eop_id_reserved_6 245
-#define BCHP_RDC_EOP_ID_256_eop_id_reserved_7 246
-#define BCHP_RDC_EOP_ID_256_eop_id_reserved_8 247
-#define BCHP_RDC_EOP_ID_256_eop_id_reserved_9 248
-#define BCHP_RDC_EOP_ID_256_eop_id_reserved_10 249
-#define BCHP_RDC_EOP_ID_256_eop_id_reserved_11 250
-#define BCHP_RDC_EOP_ID_256_eop_id_reserved_12 251
-#define BCHP_RDC_EOP_ID_256_eop_id_reserved_13 252
-#define BCHP_RDC_EOP_ID_256_eop_id_reserved_14 253
-#define BCHP_RDC_EOP_ID_256_eop_id_reserved_15 254
-#define BCHP_RDC_EOP_ID_256_eop_id_reserved_16 255
-
-/***************************************************************************
- *SPDIF_RCVR_CTRL
- ***************************************************************************/
-/***************************************************************************
- *ABSTRACT_INTERRUPT_HANDLING - Interrupt Handling
- ***************************************************************************/
-/* SPDIF_RCVR_CTRL :: ABSTRACT_INTERRUPT_HANDLING :: MORE_INFORMATION [31:00] */
-#define BCHP_SPDIF_RCVR_CTRL_ABSTRACT_INTERRUPT_HANDLING_MORE_INFORMATION_MASK 0xffffffff
-#define BCHP_SPDIF_RCVR_CTRL_ABSTRACT_INTERRUPT_HANDLING_MORE_INFORMATION_SHIFT 0
-
-/***************************************************************************
- *VICE2_REGSET_MISC
- ***************************************************************************/
-/***************************************************************************
- *DCCM - registers interface address offset in DCCM.
- ***************************************************************************/
-/* VICE2_REGSET_MISC :: DCCM :: INTERFACE [31:16] */
-#define BCHP_VICE2_REGSET_MISC_DCCM_INTERFACE_MASK 0xffff0000
-#define BCHP_VICE2_REGSET_MISC_DCCM_INTERFACE_SHIFT 16
-#define BCHP_VICE2_REGSET_MISC_DCCM_INTERFACE_HOST2VICE_OFFSET 0
-#define BCHP_VICE2_REGSET_MISC_DCCM_INTERFACE_VICE2HOST_OFFSET 4
-#define BCHP_VICE2_REGSET_MISC_DCCM_INTERFACE_BVN2VICE_OFFSET 8
-#define BCHP_VICE2_REGSET_MISC_DCCM_INTERFACE_MBOX_0_START 16
-#define BCHP_VICE2_REGSET_MISC_DCCM_INTERFACE_MBOX_1_START 40
-
-/* VICE2_REGSET_MISC :: DCCM :: REVISION [15:00] */
-#define BCHP_VICE2_REGSET_MISC_DCCM_REVISION_MASK 0x0000ffff
-#define BCHP_VICE2_REGSET_MISC_DCCM_REVISION_SHIFT 0
-#define BCHP_VICE2_REGSET_MISC_DCCM_REVISION_ID 1
-
-/***************************************************************************
- *MBOX - MBOX registers interface address offset.
- ***************************************************************************/
-/* VICE2_REGSET_MISC :: MBOX :: INTERFACE [31:16] */
-#define BCHP_VICE2_REGSET_MISC_MBOX_INTERFACE_MASK 0xffff0000
-#define BCHP_VICE2_REGSET_MISC_MBOX_INTERFACE_SHIFT 16
-#define BCHP_VICE2_REGSET_MISC_MBOX_INTERFACE_DWORD_00_BVB_PIC_SIZE_OFFSET 0
-#define BCHP_VICE2_REGSET_MISC_MBOX_INTERFACE_DWORD_01_SAMPLE_ASPECT_RATIO_OFFSET 4
-#define BCHP_VICE2_REGSET_MISC_MBOX_INTERFACE_DWORD_02_PIC_INFO_OFFSET 8
-#define BCHP_VICE2_REGSET_MISC_MBOX_INTERFACE_DWORD_03_ORIGINAL_PTS_OFFSET 12
-#define BCHP_VICE2_REGSET_MISC_MBOX_INTERFACE_DWORD_04_STG_PICTURE_ID_OFFSET 16
-#define BCHP_VICE2_REGSET_MISC_MBOX_INTERFACE_DWORD_05_BARDATA_INFO_OFFSET 20
-#define BCHP_VICE2_REGSET_MISC_MBOX_INTERFACE_SIZE 6
-
-/* VICE2_REGSET_MISC :: MBOX :: MAJORREVISION [15:08] */
-#define BCHP_VICE2_REGSET_MISC_MBOX_MAJORREVISION_MASK 0x0000ff00
-#define BCHP_VICE2_REGSET_MISC_MBOX_MAJORREVISION_SHIFT 8
-#define BCHP_VICE2_REGSET_MISC_MBOX_MAJORREVISION_ID 1
-
-/* VICE2_REGSET_MISC :: MBOX :: MINORREVISION [07:00] */
-#define BCHP_VICE2_REGSET_MISC_MBOX_MINORREVISION_MASK 0x000000ff
-#define BCHP_VICE2_REGSET_MISC_MBOX_MINORREVISION_SHIFT 0
-#define BCHP_VICE2_REGSET_MISC_MBOX_MINORREVISION_ID 0
-
-/***************************************************************************
- *DWORD_00_BVB_PIC_SIZE - BVB Picture Size
- ***************************************************************************/
-/* VICE2_REGSET_MISC :: DWORD_00_BVB_PIC_SIZE :: H_SIZE [31:16] */
-#define BCHP_VICE2_REGSET_MISC_DWORD_00_BVB_PIC_SIZE_H_SIZE_MASK 0xffff0000
-#define BCHP_VICE2_REGSET_MISC_DWORD_00_BVB_PIC_SIZE_H_SIZE_SHIFT 16
-
-/* VICE2_REGSET_MISC :: DWORD_00_BVB_PIC_SIZE :: V_SIZE [15:00] */
-#define BCHP_VICE2_REGSET_MISC_DWORD_00_BVB_PIC_SIZE_V_SIZE_MASK 0x0000ffff
-#define BCHP_VICE2_REGSET_MISC_DWORD_00_BVB_PIC_SIZE_V_SIZE_SHIFT 0
-
-/***************************************************************************
- *DWORD_01_SAMPLE_ASPECT_RATIO - Sample Aspect Ratio
- ***************************************************************************/
-/* VICE2_REGSET_MISC :: DWORD_01_SAMPLE_ASPECT_RATIO :: H_SIZE [31:16] */
-#define BCHP_VICE2_REGSET_MISC_DWORD_01_SAMPLE_ASPECT_RATIO_H_SIZE_MASK 0xffff0000
-#define BCHP_VICE2_REGSET_MISC_DWORD_01_SAMPLE_ASPECT_RATIO_H_SIZE_SHIFT 16
-
-/* VICE2_REGSET_MISC :: DWORD_01_SAMPLE_ASPECT_RATIO :: V_SIZE [15:00] */
-#define BCHP_VICE2_REGSET_MISC_DWORD_01_SAMPLE_ASPECT_RATIO_V_SIZE_MASK 0x0000ffff
-#define BCHP_VICE2_REGSET_MISC_DWORD_01_SAMPLE_ASPECT_RATIO_V_SIZE_SHIFT 0
-
-/***************************************************************************
- *DWORD_02_PIC_INFO - Picture Information
- ***************************************************************************/
-/* VICE2_REGSET_MISC :: DWORD_02_PIC_INFO :: FRAME_RATE [31:16] */
-#define BCHP_VICE2_REGSET_MISC_DWORD_02_PIC_INFO_FRAME_RATE_MASK 0xffff0000
-#define BCHP_VICE2_REGSET_MISC_DWORD_02_PIC_INFO_FRAME_RATE_SHIFT 16
-
-/* VICE2_REGSET_MISC :: DWORD_02_PIC_INFO :: SRC_PIC_TYPE [15:12] */
-#define BCHP_VICE2_REGSET_MISC_DWORD_02_PIC_INFO_SRC_PIC_TYPE_MASK 0x0000f000
-#define BCHP_VICE2_REGSET_MISC_DWORD_02_PIC_INFO_SRC_PIC_TYPE_SHIFT 12
-#define BCHP_VICE2_REGSET_MISC_DWORD_02_PIC_INFO_SRC_PIC_TYPE_UNKNOWN 0
-#define BCHP_VICE2_REGSET_MISC_DWORD_02_PIC_INFO_SRC_PIC_TYPE_I 1
-#define BCHP_VICE2_REGSET_MISC_DWORD_02_PIC_INFO_SRC_PIC_TYPE_P 2
-#define BCHP_VICE2_REGSET_MISC_DWORD_02_PIC_INFO_SRC_PIC_TYPE_B 3
-
-/* VICE2_REGSET_MISC :: DWORD_02_PIC_INFO :: POLARITY [11:10] */
-#define BCHP_VICE2_REGSET_MISC_DWORD_02_PIC_INFO_POLARITY_MASK 0x00000c00
-#define BCHP_VICE2_REGSET_MISC_DWORD_02_PIC_INFO_POLARITY_SHIFT 10
-#define BCHP_VICE2_REGSET_MISC_DWORD_02_PIC_INFO_POLARITY_TOP 0
-#define BCHP_VICE2_REGSET_MISC_DWORD_02_PIC_INFO_POLARITY_BOT 1
-#define BCHP_VICE2_REGSET_MISC_DWORD_02_PIC_INFO_POLARITY_FRAME 2
-
-/* VICE2_REGSET_MISC :: DWORD_02_PIC_INFO :: REPEAT [09:09] */
-#define BCHP_VICE2_REGSET_MISC_DWORD_02_PIC_INFO_REPEAT_MASK 0x00000200
-#define BCHP_VICE2_REGSET_MISC_DWORD_02_PIC_INFO_REPEAT_SHIFT 9
-#define BCHP_VICE2_REGSET_MISC_DWORD_02_PIC_INFO_REPEAT_DISABLE 0
-#define BCHP_VICE2_REGSET_MISC_DWORD_02_PIC_INFO_REPEAT_ENABLE 1
-
-/* VICE2_REGSET_MISC :: DWORD_02_PIC_INFO :: IGNORE [08:08] */
-#define BCHP_VICE2_REGSET_MISC_DWORD_02_PIC_INFO_IGNORE_MASK 0x00000100
-#define BCHP_VICE2_REGSET_MISC_DWORD_02_PIC_INFO_IGNORE_SHIFT 8
-#define BCHP_VICE2_REGSET_MISC_DWORD_02_PIC_INFO_IGNORE_DISABLE 0
-#define BCHP_VICE2_REGSET_MISC_DWORD_02_PIC_INFO_IGNORE_ENABLE 1
-
-/* VICE2_REGSET_MISC :: DWORD_02_PIC_INFO :: LAST [07:07] */
-#define BCHP_VICE2_REGSET_MISC_DWORD_02_PIC_INFO_LAST_MASK 0x00000080
-#define BCHP_VICE2_REGSET_MISC_DWORD_02_PIC_INFO_LAST_SHIFT 7
-#define BCHP_VICE2_REGSET_MISC_DWORD_02_PIC_INFO_LAST_FALSE 0
-#define BCHP_VICE2_REGSET_MISC_DWORD_02_PIC_INFO_LAST_TRUE 1
-
-/* VICE2_REGSET_MISC :: DWORD_02_PIC_INFO :: CHANNELCHANGE [06:06] */
-#define BCHP_VICE2_REGSET_MISC_DWORD_02_PIC_INFO_CHANNELCHANGE_MASK 0x00000040
-#define BCHP_VICE2_REGSET_MISC_DWORD_02_PIC_INFO_CHANNELCHANGE_SHIFT 6
-#define BCHP_VICE2_REGSET_MISC_DWORD_02_PIC_INFO_CHANNELCHANGE_FALSE 0
-#define BCHP_VICE2_REGSET_MISC_DWORD_02_PIC_INFO_CHANNELCHANGE_TRUE 1
-
-/* VICE2_REGSET_MISC :: DWORD_02_PIC_INFO :: reserved0 [05:05] */
-#define BCHP_VICE2_REGSET_MISC_DWORD_02_PIC_INFO_reserved0_MASK 0x00000020
-#define BCHP_VICE2_REGSET_MISC_DWORD_02_PIC_INFO_reserved0_SHIFT 5
-
-/* VICE2_REGSET_MISC :: DWORD_02_PIC_INFO :: ACTIVEFORMATDATA [04:04] */
-#define BCHP_VICE2_REGSET_MISC_DWORD_02_PIC_INFO_ACTIVEFORMATDATA_MASK 0x00000010
-#define BCHP_VICE2_REGSET_MISC_DWORD_02_PIC_INFO_ACTIVEFORMATDATA_SHIFT 4
-#define BCHP_VICE2_REGSET_MISC_DWORD_02_PIC_INFO_ACTIVEFORMATDATA_FALSE 0
-#define BCHP_VICE2_REGSET_MISC_DWORD_02_PIC_INFO_ACTIVEFORMATDATA_TRUE 1
-
-/* VICE2_REGSET_MISC :: DWORD_02_PIC_INFO :: ACTIVEFORMATDATAMODE [03:00] */
-#define BCHP_VICE2_REGSET_MISC_DWORD_02_PIC_INFO_ACTIVEFORMATDATAMODE_MASK 0x0000000f
-#define BCHP_VICE2_REGSET_MISC_DWORD_02_PIC_INFO_ACTIVEFORMATDATAMODE_SHIFT 0
-
-/***************************************************************************
- *DWORD_03_ORIGINAL_PTS - Source PTS Value
- ***************************************************************************/
-/* VICE2_REGSET_MISC :: DWORD_03_ORIGINAL_PTS :: VAL [31:00] */
-#define BCHP_VICE2_REGSET_MISC_DWORD_03_ORIGINAL_PTS_VAL_MASK 0xffffffff
-#define BCHP_VICE2_REGSET_MISC_DWORD_03_ORIGINAL_PTS_VAL_SHIFT 0
-
-/***************************************************************************
- *DWORD_04_STG_PICTURE_ID - STG Picture ID
- ***************************************************************************/
-/* VICE2_REGSET_MISC :: DWORD_04_STG_PICTURE_ID :: VAL [31:00] */
-#define BCHP_VICE2_REGSET_MISC_DWORD_04_STG_PICTURE_ID_VAL_MASK 0xffffffff
-#define BCHP_VICE2_REGSET_MISC_DWORD_04_STG_PICTURE_ID_VAL_SHIFT 0
-
-/***************************************************************************
- *DWORD_05_BARDATA_INFO - bar data Information
- ***************************************************************************/
-/* VICE2_REGSET_MISC :: DWORD_05_BARDATA_INFO :: reserved0 [31:30] */
-#define BCHP_VICE2_REGSET_MISC_DWORD_05_BARDATA_INFO_reserved0_MASK 0xc0000000
-#define BCHP_VICE2_REGSET_MISC_DWORD_05_BARDATA_INFO_reserved0_SHIFT 30
-
-/* VICE2_REGSET_MISC :: DWORD_05_BARDATA_INFO :: TOPLEFTBARVALUE [29:16] */
-#define BCHP_VICE2_REGSET_MISC_DWORD_05_BARDATA_INFO_TOPLEFTBARVALUE_MASK 0x3fff0000
-#define BCHP_VICE2_REGSET_MISC_DWORD_05_BARDATA_INFO_TOPLEFTBARVALUE_SHIFT 16
-
-/* VICE2_REGSET_MISC :: DWORD_05_BARDATA_INFO :: BARDATATYPE [15:14] */
-#define BCHP_VICE2_REGSET_MISC_DWORD_05_BARDATA_INFO_BARDATATYPE_MASK 0x0000c000
-#define BCHP_VICE2_REGSET_MISC_DWORD_05_BARDATA_INFO_BARDATATYPE_SHIFT 14
-#define BCHP_VICE2_REGSET_MISC_DWORD_05_BARDATA_INFO_BARDATATYPE_invalidBarData 0
-#define BCHP_VICE2_REGSET_MISC_DWORD_05_BARDATA_INFO_BARDATATYPE_TopBottom 1
-#define BCHP_VICE2_REGSET_MISC_DWORD_05_BARDATA_INFO_BARDATATYPE_LeftRight 2
-#define BCHP_VICE2_REGSET_MISC_DWORD_05_BARDATA_INFO_BARDATATYPE_reserved 3
-
-/* VICE2_REGSET_MISC :: DWORD_05_BARDATA_INFO :: BOTRIGHTBARVALUE [13:00] */
-#define BCHP_VICE2_REGSET_MISC_DWORD_05_BARDATA_INFO_BOTRIGHTBARVALUE_MASK 0x00003fff
-#define BCHP_VICE2_REGSET_MISC_DWORD_05_BARDATA_INFO_BOTRIGHTBARVALUE_SHIFT 0
-
-/***************************************************************************
- *XPT_RAVE
- ***************************************************************************/
-/***************************************************************************
- *NOTEA_CONTEXT_SETUP_EXAMPLES - Context Setup Examples
- ***************************************************************************/
-/* XPT_RAVE :: NOTEA_CONTEXT_SETUP_EXAMPLES :: CONTEXT_EXAMPLES [31:00] */
-#define BCHP_XPT_RAVE_NOTEA_CONTEXT_SETUP_EXAMPLES_CONTEXT_EXAMPLES_MASK 0xffffffff
-#define BCHP_XPT_RAVE_NOTEA_CONTEXT_SETUP_EXAMPLES_CONTEXT_EXAMPLES_SHIFT 0
-
-/***************************************************************************
- *NOTEB_STREAM_TYPE_SETUP - Stream Type Setup
- ***************************************************************************/
-/* XPT_RAVE :: NOTEB_STREAM_TYPE_SETUP :: STREAM_TYPE_SETUP [31:00] */
-#define BCHP_XPT_RAVE_NOTEB_STREAM_TYPE_SETUP_STREAM_TYPE_SETUP_MASK 0xffffffff
-#define BCHP_XPT_RAVE_NOTEB_STREAM_TYPE_SETUP_STREAM_TYPE_SETUP_SHIFT 0
-
-/***************************************************************************
- *NOTEC_PES_LAYER_SELECTION - PES Layer Selection
- ***************************************************************************/
-/* XPT_RAVE :: NOTEC_PES_LAYER_SELECTION :: PES_LAYER_SELECTION [31:00] */
-#define BCHP_XPT_RAVE_NOTEC_PES_LAYER_SELECTION_PES_LAYER_SELECTION_MASK 0xffffffff
-#define BCHP_XPT_RAVE_NOTEC_PES_LAYER_SELECTION_PES_LAYER_SELECTION_SHIFT 0
-
-/***************************************************************************
- *NOTED_ES_FORMAT_SELECTION_GENERAL - ES Format Selection - general
- ***************************************************************************/
-/* XPT_RAVE :: NOTED_ES_FORMAT_SELECTION_GENERAL :: GENERAL_ES_FORMAT_SELECTION [31:00] */
-#define BCHP_XPT_RAVE_NOTED_ES_FORMAT_SELECTION_GENERAL_GENERAL_ES_FORMAT_SELECTION_MASK 0xffffffff
-#define BCHP_XPT_RAVE_NOTED_ES_FORMAT_SELECTION_GENERAL_GENERAL_ES_FORMAT_SELECTION_SHIFT 0
-
-/***************************************************************************
- *NOTEE_MPEG2_VIDEO_ES_SETUP - ES Setup - MPEG2 Video
- ***************************************************************************/
-/* XPT_RAVE :: NOTEE_MPEG2_VIDEO_ES_SETUP :: MPEG2_VIDEO_ES_FORMAT [31:00] */
-#define BCHP_XPT_RAVE_NOTEE_MPEG2_VIDEO_ES_SETUP_MPEG2_VIDEO_ES_FORMAT_MASK 0xffffffff
-#define BCHP_XPT_RAVE_NOTEE_MPEG2_VIDEO_ES_SETUP_MPEG2_VIDEO_ES_FORMAT_SHIFT 0
-
-/***************************************************************************
- *NOTEF_AVC_VC1_VIDEO_ES_SETUP - ES Setup - AVC and VC1 Video
- ***************************************************************************/
-/* XPT_RAVE :: NOTEF_AVC_VC1_VIDEO_ES_SETUP :: AVC_VC1_VIDEO_ES_FORMAT [31:00] */
-#define BCHP_XPT_RAVE_NOTEF_AVC_VC1_VIDEO_ES_SETUP_AVC_VC1_VIDEO_ES_FORMAT_MASK 0xffffffff
-#define BCHP_XPT_RAVE_NOTEF_AVC_VC1_VIDEO_ES_SETUP_AVC_VC1_VIDEO_ES_FORMAT_SHIFT 0
-
-/***************************************************************************
- *NOTEG_MPEG_AUDIO_ES_SETUP - ES Setup - MPEG Audio
- ***************************************************************************/
-/* XPT_RAVE :: NOTEG_MPEG_AUDIO_ES_SETUP :: AUDIO_MPEG_ES_FORMAT [31:00] */
-#define BCHP_XPT_RAVE_NOTEG_MPEG_AUDIO_ES_SETUP_AUDIO_MPEG_ES_FORMAT_MASK 0xffffffff
-#define BCHP_XPT_RAVE_NOTEG_MPEG_AUDIO_ES_SETUP_AUDIO_MPEG_ES_FORMAT_SHIFT 0
-
-/***************************************************************************
- *NOTEH_AAC_AUDIO_ES_SETUP - ES Setup - AAC Audio
- ***************************************************************************/
-/* XPT_RAVE :: NOTEH_AAC_AUDIO_ES_SETUP :: AUDIO_AAC_ES_FORMAT [31:00] */
-#define BCHP_XPT_RAVE_NOTEH_AAC_AUDIO_ES_SETUP_AUDIO_AAC_ES_FORMAT_MASK 0xffffffff
-#define BCHP_XPT_RAVE_NOTEH_AAC_AUDIO_ES_SETUP_AUDIO_AAC_ES_FORMAT_SHIFT 0
-
-/***************************************************************************
- *NOTEH_AC3_AUDIO_ES_SETUP - ES Setup - AC3 Audio
- ***************************************************************************/
-/* XPT_RAVE :: NOTEH_AC3_AUDIO_ES_SETUP :: AUDIO_AC3_ES_FORMAT [31:00] */
-#define BCHP_XPT_RAVE_NOTEH_AC3_AUDIO_ES_SETUP_AUDIO_AC3_ES_FORMAT_MASK 0xffffffff
-#define BCHP_XPT_RAVE_NOTEH_AC3_AUDIO_ES_SETUP_AUDIO_AC3_ES_FORMAT_SHIFT 0
-
-/***************************************************************************
- *NOTEJ_ENHANCED_AC3_AUDIO_ES_SETUP - ES Setup - AC3 Audio
- ***************************************************************************/
-/* XPT_RAVE :: NOTEJ_ENHANCED_AC3_AUDIO_ES_SETUP :: AUDIO_ENHANCED_AC3_ES_FORMAT [31:00] */
-#define BCHP_XPT_RAVE_NOTEJ_ENHANCED_AC3_AUDIO_ES_SETUP_AUDIO_ENHANCED_AC3_ES_FORMAT_MASK 0xffffffff
-#define BCHP_XPT_RAVE_NOTEJ_ENHANCED_AC3_AUDIO_ES_SETUP_AUDIO_ENHANCED_AC3_ES_FORMAT_SHIFT 0
-
-/***************************************************************************
- *NOTEK_AAC_HE_AUDIO_ES_SETUP - ES Setup - AAC HE Audio
- ***************************************************************************/
-/* XPT_RAVE :: NOTEK_AAC_HE_AUDIO_ES_SETUP :: AUDIO_AAC_HE_ES_FORMAT [31:00] */
-#define BCHP_XPT_RAVE_NOTEK_AAC_HE_AUDIO_ES_SETUP_AUDIO_AAC_HE_ES_FORMAT_MASK 0xffffffff
-#define BCHP_XPT_RAVE_NOTEK_AAC_HE_AUDIO_ES_SETUP_AUDIO_AAC_HE_ES_FORMAT_SHIFT 0
-
-#endif /* #ifndef BCHP_COMMON_H__ */
-
-/* End of File */
diff --git a/include/linux/brcmstb/7145a0/bchp_ddr34_phy_byte_lane_0_0.h b/include/linux/brcmstb/7145a0/bchp_ddr34_phy_byte_lane_0_0.h
deleted file mode 100644
index 2e0d236..0000000
--- a/include/linux/brcmstb/7145a0/bchp_ddr34_phy_byte_lane_0_0.h
+++ /dev/null
@@ -1,2101 +0,0 @@
-/***************************************************************************
- * Copyright (c) 1999-2014, Broadcom Corporation
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
- *
- * Module Description:
- * DO NOT EDIT THIS FILE DIRECTLY
- *
- * This module was generated magically with RDB from a source description
- * file. You must edit the source file for changes to be made to this file.
- *
- *
- * Date: Generated on Wed Sep 3 13:17:34 2014
- * Full Compile MD5 Checksum a8ee62ccf9dde43435c825f266da463d
- * (minus title and desc)
- * MD5 Checksum e373b364a1742e13a0f9eb15fd8aa94f
- *
- * Compiled with: RDB Utility combo_header.pl
- * RDB Parser 3.0
- * unknown unknown
- * Perl Interpreter 5.008005
- * Operating System linux
- *
- * Revision History:
- *
- * $brcm_Log: $
- *
- ***************************************************************************/
-
-#ifndef BCHP_DDR34_PHY_BYTE_LANE_0_0_H__
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_H__
-
-/***************************************************************************
- *DDR34_PHY_BYTE_LANE_0_0 - DDR34 Byte Lane #0 control registers
- ***************************************************************************/
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQS_P 0x203b6400 /* Write channel DQS-P VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQS_N 0x203b6404 /* Write channel DQS-N VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ0 0x203b6408 /* Write channel DQ0 VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ1 0x203b640c /* Write channel DQ1 VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ2 0x203b6410 /* Write channel DQ2 VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ3 0x203b6414 /* Write channel DQ3 VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ4 0x203b6418 /* Write channel DQ4 VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ5 0x203b641c /* Write channel DQ5 VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ6 0x203b6420 /* Write channel DQ6 VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ7 0x203b6424 /* Write channel DQ7 VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DM 0x203b6428 /* Write channel DM VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_EDC 0x203b642c /* Write channel EDC VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQSP 0x203b6430 /* Read channel DQSP VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQSN 0x203b6434 /* Read channel DQSP VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ0P 0x203b6438 /* Read channel DQ0-P VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ0N 0x203b643c /* Read channel DQ0-N VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ1P 0x203b6440 /* Read channel DQ1-P VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ1N 0x203b6444 /* Read channel DQ1-N VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ2P 0x203b6448 /* Read channel DQ2-P VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ2N 0x203b644c /* Read channel DQ2-N VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ3P 0x203b6450 /* Read channel DQ3-P VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ3N 0x203b6454 /* Read channel DQ3-N VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ4P 0x203b6458 /* Read channel DQ4-P VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ4N 0x203b645c /* Read channel DQ4-N VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ5P 0x203b6460 /* Read channel DQ5-P VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ5N 0x203b6464 /* Read channel DQ5-N VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ6P 0x203b6468 /* Read channel DQ6-P VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ6N 0x203b646c /* Read channel DQ6-N VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ7P 0x203b6470 /* Read channel DQ7-P VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ7N 0x203b6474 /* Read channel DQ7-N VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DMP 0x203b6478 /* Read channel DM-P VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DMN 0x203b647c /* Read channel DM-N VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_EDCP 0x203b6480 /* Read channel EDC-P VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_EDCN 0x203b6484 /* Read channel EDC-N VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_EN_CS0 0x203b6488 /* Read channel CS_N[0] read enable VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_EN_CS1 0x203b648c /* Read channel CS_N[1] read enable VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CLK_CONTROL 0x203b6490 /* DDR interface signal Write Leveling CLK VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_LDE_CONTROL 0x203b6494 /* DDR interface signal Write Leveling Capture Enable VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_RD_EN_DLY_CYC 0x203b64a0 /* Read enable bit-clock cycle delay control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_WR_CHAN_DLY_CYC 0x203b64a4 /* Write leveling bit-clock cycle delay control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_READ_CONTROL 0x203b64b0 /* Read channel datapath control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_READ_FIFO_ADDR 0x203b64b4 /* Read fifo addresss pointer register */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_READ_FIFO_DATA 0x203b64b8 /* Read fifo data register */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_READ_FIFO_DM_DBI 0x203b64bc /* Read fifo dm/dbi register */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_READ_FIFO_STATUS 0x203b64c0 /* Read fifo status register */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_READ_FIFO_CLEAR 0x203b64c4 /* Read fifo status clear register */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_IDLE_PAD_CONTROL 0x203b64c8 /* Idle mode SSTL pad control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_DRIVE_PAD_CTL 0x203b64cc /* SSTL pad drive characteristics control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_RD_EN_DRIVE_PAD_CTL 0x203b64d0 /* SSTL read enable pad drive characteristics control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_STATIC_PAD_CTL 0x203b64d4 /* pad rx and tx characteristics control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_WR_PREAMBLE_MODE 0x203b64d8 /* Write cycle preamble control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_ODT_CONTROL 0x203b64e0 /* Read channel ODT control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_DPD_CONTROL 0x203b64f0 /* GDDR5M EDC digital phase detector control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_DPD_STATUS 0x203b64f4 /* GDDR5M EDC digital phase detector status register */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_DPD_OUT_CONTROL 0x203b64f8 /* GDDR5M EDC digital phase detector output signal control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_DPD_OUT_STATUS 0x203b64fc /* GDDR5M EDC digital phase detector output signal status register */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_DPD_OUT_STATUS_CLEAR 0x203b6500 /* GDDR5M EDC digital phase detector output signal status clear register */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_CRC_CONTROL 0x203b6504 /* GDDR5M EDC signal path CRC control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_CRC_STATUS 0x203b6508 /* GDDR5M EDC signal path CRC status register */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_CRC_COUNT 0x203b650c /* GDDR5M EDC signal path CRC counter register */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_CRC_STATUS_CLEAR 0x203b6510 /* GDDR5M EDC signal path CRC counter register */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_BL_SPARE_REG 0x203b6514 /* Byte-Lane Spare register */
-
-/***************************************************************************
- *VDL_CONTROL_WR_DQS_P - Write channel DQS-P VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_WR_DQS_P :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQS_P_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQS_P_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQS_P_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_WR_DQS_P :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQS_P_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQS_P_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_WR_DQS_P :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQS_P_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQS_P_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQS_P_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_WR_DQS_P :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQS_P_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQS_P_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_WR_DQS_P :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQS_P_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQS_P_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQS_P_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_WR_DQS_P :: reserved2 [11:09] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQS_P_reserved2_MASK 0x00000e00
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQS_P_reserved2_SHIFT 9
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_WR_DQS_P :: VDL_STEP [08:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQS_P_VDL_STEP_MASK 0x000001ff
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQS_P_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQS_P_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_WR_DQS_N - Write channel DQS-N VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_WR_DQS_N :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQS_N_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQS_N_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQS_N_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_WR_DQS_N :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQS_N_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQS_N_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_WR_DQS_N :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQS_N_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQS_N_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQS_N_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_WR_DQS_N :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQS_N_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQS_N_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_WR_DQS_N :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQS_N_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQS_N_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQS_N_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_WR_DQS_N :: reserved2 [11:09] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQS_N_reserved2_MASK 0x00000e00
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQS_N_reserved2_SHIFT 9
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_WR_DQS_N :: VDL_STEP [08:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQS_N_VDL_STEP_MASK 0x000001ff
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQS_N_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQS_N_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_WR_DQ0 - Write channel DQ0 VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_WR_DQ0 :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ0_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ0_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ0_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_WR_DQ0 :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ0_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ0_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_WR_DQ0 :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ0_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ0_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ0_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_WR_DQ0 :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ0_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ0_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_WR_DQ0 :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ0_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ0_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ0_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_WR_DQ0 :: reserved2 [11:09] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ0_reserved2_MASK 0x00000e00
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ0_reserved2_SHIFT 9
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_WR_DQ0 :: VDL_STEP [08:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ0_VDL_STEP_MASK 0x000001ff
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ0_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ0_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_WR_DQ1 - Write channel DQ1 VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_WR_DQ1 :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ1_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ1_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ1_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_WR_DQ1 :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ1_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ1_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_WR_DQ1 :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ1_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ1_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ1_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_WR_DQ1 :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ1_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ1_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_WR_DQ1 :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ1_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ1_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ1_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_WR_DQ1 :: reserved2 [11:09] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ1_reserved2_MASK 0x00000e00
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ1_reserved2_SHIFT 9
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_WR_DQ1 :: VDL_STEP [08:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ1_VDL_STEP_MASK 0x000001ff
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ1_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ1_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_WR_DQ2 - Write channel DQ2 VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_WR_DQ2 :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ2_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ2_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ2_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_WR_DQ2 :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ2_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ2_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_WR_DQ2 :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ2_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ2_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ2_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_WR_DQ2 :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ2_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ2_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_WR_DQ2 :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ2_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ2_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ2_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_WR_DQ2 :: reserved2 [11:09] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ2_reserved2_MASK 0x00000e00
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ2_reserved2_SHIFT 9
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_WR_DQ2 :: VDL_STEP [08:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ2_VDL_STEP_MASK 0x000001ff
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ2_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ2_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_WR_DQ3 - Write channel DQ3 VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_WR_DQ3 :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ3_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ3_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ3_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_WR_DQ3 :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ3_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ3_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_WR_DQ3 :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ3_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ3_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ3_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_WR_DQ3 :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ3_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ3_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_WR_DQ3 :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ3_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ3_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ3_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_WR_DQ3 :: reserved2 [11:09] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ3_reserved2_MASK 0x00000e00
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ3_reserved2_SHIFT 9
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_WR_DQ3 :: VDL_STEP [08:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ3_VDL_STEP_MASK 0x000001ff
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ3_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ3_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_WR_DQ4 - Write channel DQ4 VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_WR_DQ4 :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ4_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ4_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ4_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_WR_DQ4 :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ4_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ4_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_WR_DQ4 :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ4_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ4_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ4_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_WR_DQ4 :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ4_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ4_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_WR_DQ4 :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ4_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ4_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ4_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_WR_DQ4 :: reserved2 [11:09] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ4_reserved2_MASK 0x00000e00
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ4_reserved2_SHIFT 9
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_WR_DQ4 :: VDL_STEP [08:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ4_VDL_STEP_MASK 0x000001ff
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ4_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ4_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_WR_DQ5 - Write channel DQ5 VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_WR_DQ5 :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ5_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ5_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ5_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_WR_DQ5 :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ5_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ5_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_WR_DQ5 :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ5_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ5_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ5_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_WR_DQ5 :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ5_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ5_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_WR_DQ5 :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ5_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ5_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ5_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_WR_DQ5 :: reserved2 [11:09] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ5_reserved2_MASK 0x00000e00
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ5_reserved2_SHIFT 9
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_WR_DQ5 :: VDL_STEP [08:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ5_VDL_STEP_MASK 0x000001ff
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ5_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ5_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_WR_DQ6 - Write channel DQ6 VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_WR_DQ6 :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ6_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ6_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ6_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_WR_DQ6 :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ6_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ6_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_WR_DQ6 :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ6_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ6_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ6_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_WR_DQ6 :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ6_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ6_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_WR_DQ6 :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ6_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ6_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ6_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_WR_DQ6 :: reserved2 [11:09] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ6_reserved2_MASK 0x00000e00
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ6_reserved2_SHIFT 9
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_WR_DQ6 :: VDL_STEP [08:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ6_VDL_STEP_MASK 0x000001ff
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ6_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ6_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_WR_DQ7 - Write channel DQ7 VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_WR_DQ7 :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ7_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ7_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ7_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_WR_DQ7 :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ7_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ7_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_WR_DQ7 :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ7_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ7_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ7_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_WR_DQ7 :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ7_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ7_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_WR_DQ7 :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ7_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ7_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ7_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_WR_DQ7 :: reserved2 [11:09] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ7_reserved2_MASK 0x00000e00
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ7_reserved2_SHIFT 9
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_WR_DQ7 :: VDL_STEP [08:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ7_VDL_STEP_MASK 0x000001ff
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ7_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ7_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_WR_DM - Write channel DM VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_WR_DM :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DM_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DM_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DM_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_WR_DM :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DM_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DM_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_WR_DM :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DM_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DM_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DM_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_WR_DM :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DM_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DM_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_WR_DM :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DM_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DM_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DM_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_WR_DM :: reserved2 [11:09] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DM_reserved2_MASK 0x00000e00
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DM_reserved2_SHIFT 9
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_WR_DM :: VDL_STEP [08:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DM_VDL_STEP_MASK 0x000001ff
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DM_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DM_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_WR_EDC - Write channel EDC VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_WR_EDC :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_EDC_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_EDC_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_EDC_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_WR_EDC :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_EDC_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_EDC_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_WR_EDC :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_EDC_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_EDC_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_EDC_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_WR_EDC :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_EDC_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_EDC_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_WR_EDC :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_EDC_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_EDC_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_EDC_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_WR_EDC :: reserved2 [11:09] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_EDC_reserved2_MASK 0x00000e00
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_EDC_reserved2_SHIFT 9
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_WR_EDC :: VDL_STEP [08:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_EDC_VDL_STEP_MASK 0x000001ff
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_EDC_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_EDC_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_RD_DQSP - Read channel DQSP VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQSP :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQSP_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQSP_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQSP_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQSP :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQSP_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQSP_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQSP :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQSP_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQSP_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQSP_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQSP :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQSP_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQSP_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQSP :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQSP_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQSP_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQSP_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQSP :: reserved2 [11:08] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQSP_reserved2_MASK 0x00000f00
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQSP_reserved2_SHIFT 8
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQSP :: VDL_STEP [07:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQSP_VDL_STEP_MASK 0x000000ff
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQSP_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQSP_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_RD_DQSN - Read channel DQSP VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQSN :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQSN_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQSN_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQSN_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQSN :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQSN_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQSN_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQSN :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQSN_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQSN_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQSN_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQSN :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQSN_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQSN_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQSN :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQSN_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQSN_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQSN_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQSN :: reserved2 [11:08] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQSN_reserved2_MASK 0x00000f00
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQSN_reserved2_SHIFT 8
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQSN :: VDL_STEP [07:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQSN_VDL_STEP_MASK 0x000000ff
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQSN_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQSN_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_RD_DQ0P - Read channel DQ0-P VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQ0P :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ0P_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ0P_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ0P_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQ0P :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ0P_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ0P_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQ0P :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ0P_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ0P_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ0P_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQ0P :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ0P_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ0P_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQ0P :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ0P_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ0P_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ0P_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQ0P :: reserved2 [11:08] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ0P_reserved2_MASK 0x00000f00
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ0P_reserved2_SHIFT 8
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQ0P :: VDL_STEP [07:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ0P_VDL_STEP_MASK 0x000000ff
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ0P_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ0P_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_RD_DQ0N - Read channel DQ0-N VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQ0N :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ0N_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ0N_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ0N_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQ0N :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ0N_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ0N_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQ0N :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ0N_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ0N_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ0N_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQ0N :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ0N_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ0N_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQ0N :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ0N_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ0N_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ0N_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQ0N :: reserved2 [11:08] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ0N_reserved2_MASK 0x00000f00
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ0N_reserved2_SHIFT 8
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQ0N :: VDL_STEP [07:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ0N_VDL_STEP_MASK 0x000000ff
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ0N_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ0N_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_RD_DQ1P - Read channel DQ1-P VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQ1P :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ1P_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ1P_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ1P_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQ1P :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ1P_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ1P_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQ1P :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ1P_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ1P_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ1P_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQ1P :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ1P_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ1P_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQ1P :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ1P_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ1P_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ1P_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQ1P :: reserved2 [11:08] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ1P_reserved2_MASK 0x00000f00
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ1P_reserved2_SHIFT 8
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQ1P :: VDL_STEP [07:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ1P_VDL_STEP_MASK 0x000000ff
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ1P_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ1P_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_RD_DQ1N - Read channel DQ1-N VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQ1N :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ1N_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ1N_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ1N_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQ1N :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ1N_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ1N_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQ1N :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ1N_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ1N_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ1N_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQ1N :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ1N_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ1N_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQ1N :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ1N_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ1N_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ1N_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQ1N :: reserved2 [11:08] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ1N_reserved2_MASK 0x00000f00
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ1N_reserved2_SHIFT 8
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQ1N :: VDL_STEP [07:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ1N_VDL_STEP_MASK 0x000000ff
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ1N_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ1N_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_RD_DQ2P - Read channel DQ2-P VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQ2P :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ2P_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ2P_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ2P_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQ2P :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ2P_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ2P_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQ2P :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ2P_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ2P_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ2P_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQ2P :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ2P_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ2P_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQ2P :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ2P_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ2P_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ2P_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQ2P :: reserved2 [11:08] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ2P_reserved2_MASK 0x00000f00
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ2P_reserved2_SHIFT 8
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQ2P :: VDL_STEP [07:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ2P_VDL_STEP_MASK 0x000000ff
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ2P_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ2P_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_RD_DQ2N - Read channel DQ2-N VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQ2N :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ2N_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ2N_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ2N_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQ2N :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ2N_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ2N_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQ2N :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ2N_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ2N_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ2N_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQ2N :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ2N_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ2N_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQ2N :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ2N_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ2N_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ2N_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQ2N :: reserved2 [11:08] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ2N_reserved2_MASK 0x00000f00
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ2N_reserved2_SHIFT 8
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQ2N :: VDL_STEP [07:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ2N_VDL_STEP_MASK 0x000000ff
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ2N_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ2N_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_RD_DQ3P - Read channel DQ3-P VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQ3P :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ3P_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ3P_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ3P_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQ3P :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ3P_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ3P_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQ3P :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ3P_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ3P_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ3P_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQ3P :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ3P_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ3P_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQ3P :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ3P_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ3P_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ3P_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQ3P :: reserved2 [11:08] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ3P_reserved2_MASK 0x00000f00
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ3P_reserved2_SHIFT 8
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQ3P :: VDL_STEP [07:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ3P_VDL_STEP_MASK 0x000000ff
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ3P_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ3P_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_RD_DQ3N - Read channel DQ3-N VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQ3N :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ3N_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ3N_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ3N_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQ3N :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ3N_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ3N_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQ3N :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ3N_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ3N_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ3N_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQ3N :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ3N_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ3N_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQ3N :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ3N_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ3N_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ3N_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQ3N :: reserved2 [11:08] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ3N_reserved2_MASK 0x00000f00
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ3N_reserved2_SHIFT 8
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQ3N :: VDL_STEP [07:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ3N_VDL_STEP_MASK 0x000000ff
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ3N_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ3N_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_RD_DQ4P - Read channel DQ4-P VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQ4P :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ4P_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ4P_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ4P_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQ4P :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ4P_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ4P_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQ4P :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ4P_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ4P_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ4P_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQ4P :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ4P_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ4P_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQ4P :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ4P_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ4P_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ4P_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQ4P :: reserved2 [11:08] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ4P_reserved2_MASK 0x00000f00
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ4P_reserved2_SHIFT 8
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQ4P :: VDL_STEP [07:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ4P_VDL_STEP_MASK 0x000000ff
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ4P_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ4P_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_RD_DQ4N - Read channel DQ4-N VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQ4N :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ4N_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ4N_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ4N_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQ4N :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ4N_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ4N_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQ4N :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ4N_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ4N_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ4N_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQ4N :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ4N_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ4N_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQ4N :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ4N_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ4N_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ4N_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQ4N :: reserved2 [11:08] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ4N_reserved2_MASK 0x00000f00
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ4N_reserved2_SHIFT 8
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQ4N :: VDL_STEP [07:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ4N_VDL_STEP_MASK 0x000000ff
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ4N_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ4N_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_RD_DQ5P - Read channel DQ5-P VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQ5P :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ5P_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ5P_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ5P_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQ5P :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ5P_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ5P_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQ5P :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ5P_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ5P_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ5P_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQ5P :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ5P_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ5P_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQ5P :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ5P_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ5P_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ5P_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQ5P :: reserved2 [11:08] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ5P_reserved2_MASK 0x00000f00
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ5P_reserved2_SHIFT 8
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQ5P :: VDL_STEP [07:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ5P_VDL_STEP_MASK 0x000000ff
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ5P_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ5P_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_RD_DQ5N - Read channel DQ5-N VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQ5N :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ5N_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ5N_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ5N_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQ5N :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ5N_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ5N_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQ5N :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ5N_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ5N_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ5N_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQ5N :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ5N_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ5N_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQ5N :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ5N_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ5N_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ5N_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQ5N :: reserved2 [11:08] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ5N_reserved2_MASK 0x00000f00
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ5N_reserved2_SHIFT 8
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQ5N :: VDL_STEP [07:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ5N_VDL_STEP_MASK 0x000000ff
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ5N_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ5N_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_RD_DQ6P - Read channel DQ6-P VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQ6P :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ6P_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ6P_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ6P_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQ6P :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ6P_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ6P_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQ6P :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ6P_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ6P_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ6P_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQ6P :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ6P_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ6P_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQ6P :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ6P_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ6P_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ6P_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQ6P :: reserved2 [11:08] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ6P_reserved2_MASK 0x00000f00
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ6P_reserved2_SHIFT 8
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQ6P :: VDL_STEP [07:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ6P_VDL_STEP_MASK 0x000000ff
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ6P_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ6P_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_RD_DQ6N - Read channel DQ6-N VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQ6N :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ6N_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ6N_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ6N_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQ6N :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ6N_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ6N_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQ6N :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ6N_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ6N_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ6N_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQ6N :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ6N_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ6N_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQ6N :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ6N_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ6N_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ6N_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQ6N :: reserved2 [11:08] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ6N_reserved2_MASK 0x00000f00
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ6N_reserved2_SHIFT 8
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQ6N :: VDL_STEP [07:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ6N_VDL_STEP_MASK 0x000000ff
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ6N_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ6N_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_RD_DQ7P - Read channel DQ7-P VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQ7P :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ7P_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ7P_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ7P_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQ7P :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ7P_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ7P_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQ7P :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ7P_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ7P_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ7P_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQ7P :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ7P_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ7P_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQ7P :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ7P_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ7P_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ7P_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQ7P :: reserved2 [11:08] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ7P_reserved2_MASK 0x00000f00
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ7P_reserved2_SHIFT 8
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQ7P :: VDL_STEP [07:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ7P_VDL_STEP_MASK 0x000000ff
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ7P_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ7P_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_RD_DQ7N - Read channel DQ7-N VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQ7N :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ7N_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ7N_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ7N_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQ7N :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ7N_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ7N_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQ7N :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ7N_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ7N_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ7N_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQ7N :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ7N_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ7N_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQ7N :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ7N_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ7N_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ7N_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQ7N :: reserved2 [11:08] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ7N_reserved2_MASK 0x00000f00
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ7N_reserved2_SHIFT 8
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQ7N :: VDL_STEP [07:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ7N_VDL_STEP_MASK 0x000000ff
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ7N_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ7N_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_RD_DMP - Read channel DM-P VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DMP :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DMP_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DMP_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DMP_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DMP :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DMP_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DMP_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DMP :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DMP_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DMP_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DMP_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DMP :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DMP_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DMP_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DMP :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DMP_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DMP_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DMP_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DMP :: reserved2 [11:08] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DMP_reserved2_MASK 0x00000f00
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DMP_reserved2_SHIFT 8
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DMP :: VDL_STEP [07:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DMP_VDL_STEP_MASK 0x000000ff
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DMP_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DMP_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_RD_DMN - Read channel DM-N VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DMN :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DMN_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DMN_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DMN_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DMN :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DMN_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DMN_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DMN :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DMN_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DMN_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DMN_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DMN :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DMN_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DMN_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DMN :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DMN_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DMN_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DMN_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DMN :: reserved2 [11:08] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DMN_reserved2_MASK 0x00000f00
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DMN_reserved2_SHIFT 8
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DMN :: VDL_STEP [07:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DMN_VDL_STEP_MASK 0x000000ff
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DMN_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DMN_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_RD_EDCP - Read channel EDC-P VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_EDCP :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_EDCP_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_EDCP_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_EDCP_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_EDCP :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_EDCP_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_EDCP_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_EDCP :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_EDCP_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_EDCP_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_EDCP_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_EDCP :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_EDCP_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_EDCP_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_EDCP :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_EDCP_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_EDCP_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_EDCP_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_EDCP :: reserved2 [11:08] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_EDCP_reserved2_MASK 0x00000f00
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_EDCP_reserved2_SHIFT 8
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_EDCP :: VDL_STEP [07:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_EDCP_VDL_STEP_MASK 0x000000ff
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_EDCP_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_EDCP_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_RD_EDCN - Read channel EDC-N VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_EDCN :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_EDCN_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_EDCN_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_EDCN_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_EDCN :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_EDCN_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_EDCN_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_EDCN :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_EDCN_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_EDCN_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_EDCN_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_EDCN :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_EDCN_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_EDCN_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_EDCN :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_EDCN_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_EDCN_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_EDCN_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_EDCN :: reserved2 [11:08] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_EDCN_reserved2_MASK 0x00000f00
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_EDCN_reserved2_SHIFT 8
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_EDCN :: VDL_STEP [07:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_EDCN_VDL_STEP_MASK 0x000000ff
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_EDCN_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_EDCN_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_RD_EN_CS0 - Read channel CS_N[0] read enable VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_EN_CS0 :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_EN_CS0_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_EN_CS0_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_EN_CS0_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_EN_CS0 :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_EN_CS0_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_EN_CS0_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_EN_CS0 :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_EN_CS0_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_EN_CS0_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_EN_CS0_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_EN_CS0 :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_EN_CS0_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_EN_CS0_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_EN_CS0 :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_EN_CS0_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_EN_CS0_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_EN_CS0_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_EN_CS0 :: reserved2 [11:08] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_EN_CS0_reserved2_MASK 0x00000f00
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_EN_CS0_reserved2_SHIFT 8
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_EN_CS0 :: VDL_STEP [07:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_EN_CS0_VDL_STEP_MASK 0x000000ff
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_EN_CS0_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_EN_CS0_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_RD_EN_CS1 - Read channel CS_N[1] read enable VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_EN_CS1 :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_EN_CS1_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_EN_CS1_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_EN_CS1_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_EN_CS1 :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_EN_CS1_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_EN_CS1_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_EN_CS1 :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_EN_CS1_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_EN_CS1_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_EN_CS1_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_EN_CS1 :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_EN_CS1_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_EN_CS1_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_EN_CS1 :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_EN_CS1_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_EN_CS1_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_EN_CS1_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_EN_CS1 :: reserved2 [11:08] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_EN_CS1_reserved2_MASK 0x00000f00
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_EN_CS1_reserved2_SHIFT 8
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_EN_CS1 :: VDL_STEP [07:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_EN_CS1_VDL_STEP_MASK 0x000000ff
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_EN_CS1_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_EN_CS1_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CLK_CONTROL - DDR interface signal Write Leveling CLK VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CLK_CONTROL :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CLK_CONTROL_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CLK_CONTROL_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CLK_CONTROL_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CLK_CONTROL :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CLK_CONTROL_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CLK_CONTROL_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CLK_CONTROL :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CLK_CONTROL_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CLK_CONTROL_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CLK_CONTROL_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CLK_CONTROL :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CLK_CONTROL_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CLK_CONTROL_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CLK_CONTROL :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CLK_CONTROL_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CLK_CONTROL_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CLK_CONTROL_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CLK_CONTROL :: reserved2 [11:09] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CLK_CONTROL_reserved2_MASK 0x00000e00
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CLK_CONTROL_reserved2_SHIFT 9
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CLK_CONTROL :: VDL_STEP [08:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CLK_CONTROL_VDL_STEP_MASK 0x000001ff
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CLK_CONTROL_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CLK_CONTROL_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_LDE_CONTROL - DDR interface signal Write Leveling Capture Enable VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_LDE_CONTROL :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_LDE_CONTROL_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_LDE_CONTROL_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_LDE_CONTROL_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_LDE_CONTROL :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_LDE_CONTROL_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_LDE_CONTROL_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_LDE_CONTROL :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_LDE_CONTROL_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_LDE_CONTROL_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_LDE_CONTROL_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_LDE_CONTROL :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_LDE_CONTROL_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_LDE_CONTROL_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_LDE_CONTROL :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_LDE_CONTROL_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_LDE_CONTROL_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_LDE_CONTROL_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_LDE_CONTROL :: reserved2 [11:09] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_LDE_CONTROL_reserved2_MASK 0x00000e00
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_LDE_CONTROL_reserved2_SHIFT 9
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_LDE_CONTROL :: VDL_STEP [08:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_LDE_CONTROL_VDL_STEP_MASK 0x000001ff
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_LDE_CONTROL_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_LDE_CONTROL_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *RD_EN_DLY_CYC - Read enable bit-clock cycle delay control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_0_0 :: RD_EN_DLY_CYC :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_RD_EN_DLY_CYC_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_RD_EN_DLY_CYC_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_RD_EN_DLY_CYC_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: RD_EN_DLY_CYC :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_RD_EN_DLY_CYC_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_RD_EN_DLY_CYC_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: RD_EN_DLY_CYC :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_RD_EN_DLY_CYC_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_RD_EN_DLY_CYC_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_RD_EN_DLY_CYC_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: RD_EN_DLY_CYC :: reserved1 [15:08] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_RD_EN_DLY_CYC_reserved1_MASK 0x0000ff00
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_RD_EN_DLY_CYC_reserved1_SHIFT 8
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: RD_EN_DLY_CYC :: CS1_CYCLES [07:04] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_RD_EN_DLY_CYC_CS1_CYCLES_MASK 0x000000f0
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_RD_EN_DLY_CYC_CS1_CYCLES_SHIFT 4
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_RD_EN_DLY_CYC_CS1_CYCLES_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: RD_EN_DLY_CYC :: CS0_CYCLES [03:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_RD_EN_DLY_CYC_CS0_CYCLES_MASK 0x0000000f
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_RD_EN_DLY_CYC_CS0_CYCLES_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_RD_EN_DLY_CYC_CS0_CYCLES_DEFAULT 0x00000000
-
-/***************************************************************************
- *WR_CHAN_DLY_CYC - Write leveling bit-clock cycle delay control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_0_0 :: WR_CHAN_DLY_CYC :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_WR_CHAN_DLY_CYC_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_WR_CHAN_DLY_CYC_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_WR_CHAN_DLY_CYC_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: WR_CHAN_DLY_CYC :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_WR_CHAN_DLY_CYC_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_WR_CHAN_DLY_CYC_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: WR_CHAN_DLY_CYC :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_WR_CHAN_DLY_CYC_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_WR_CHAN_DLY_CYC_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_WR_CHAN_DLY_CYC_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: WR_CHAN_DLY_CYC :: reserved1 [15:03] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_WR_CHAN_DLY_CYC_reserved1_MASK 0x0000fff8
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_WR_CHAN_DLY_CYC_reserved1_SHIFT 3
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: WR_CHAN_DLY_CYC :: CYCLES [02:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_WR_CHAN_DLY_CYC_CYCLES_MASK 0x00000007
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_WR_CHAN_DLY_CYC_CYCLES_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_WR_CHAN_DLY_CYC_CYCLES_DEFAULT 0x00000000
-
-/***************************************************************************
- *READ_CONTROL - Read channel datapath control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_0_0 :: READ_CONTROL :: reserved0 [31:05] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_READ_CONTROL_reserved0_MASK 0xffffffe0
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_READ_CONTROL_reserved0_SHIFT 5
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: READ_CONTROL :: MODE [04:04] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_READ_CONTROL_MODE_MASK 0x00000010
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_READ_CONTROL_MODE_SHIFT 4
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_READ_CONTROL_MODE_DEFAULT 0x00000001
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: READ_CONTROL :: reserved1 [03:03] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_READ_CONTROL_reserved1_MASK 0x00000008
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_READ_CONTROL_reserved1_SHIFT 3
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: READ_CONTROL :: RD_DATA_DLY [02:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_READ_CONTROL_RD_DATA_DLY_MASK 0x00000007
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_READ_CONTROL_RD_DATA_DLY_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_READ_CONTROL_RD_DATA_DLY_DEFAULT 0x00000007
-
-/***************************************************************************
- *READ_FIFO_ADDR - Read fifo addresss pointer register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_0_0 :: READ_FIFO_ADDR :: reserved0 [31:03] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_READ_FIFO_ADDR_reserved0_MASK 0xfffffff8
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_READ_FIFO_ADDR_reserved0_SHIFT 3
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: READ_FIFO_ADDR :: ADDR [02:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_READ_FIFO_ADDR_ADDR_MASK 0x00000007
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_READ_FIFO_ADDR_ADDR_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_READ_FIFO_ADDR_ADDR_DEFAULT 0x00000000
-
-/***************************************************************************
- *READ_FIFO_DATA - Read fifo data register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_0_0 :: READ_FIFO_DATA :: DATA [31:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_READ_FIFO_DATA_DATA_MASK 0xffffffff
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_READ_FIFO_DATA_DATA_SHIFT 0
-
-/***************************************************************************
- *READ_FIFO_DM_DBI - Read fifo dm/dbi register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_0_0 :: READ_FIFO_DM_DBI :: reserved0 [31:04] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_READ_FIFO_DM_DBI_reserved0_MASK 0xfffffff0
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_READ_FIFO_DM_DBI_reserved0_SHIFT 4
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: READ_FIFO_DM_DBI :: DM_DBI [03:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_READ_FIFO_DM_DBI_DM_DBI_MASK 0x0000000f
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_READ_FIFO_DM_DBI_DM_DBI_SHIFT 0
-
-/***************************************************************************
- *READ_FIFO_STATUS - Read fifo status register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_0_0 :: READ_FIFO_STATUS :: reserved0 [31:02] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_READ_FIFO_STATUS_reserved0_MASK 0xfffffffc
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_READ_FIFO_STATUS_reserved0_SHIFT 2
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: READ_FIFO_STATUS :: OVERFLOW [01:01] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_READ_FIFO_STATUS_OVERFLOW_MASK 0x00000002
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_READ_FIFO_STATUS_OVERFLOW_SHIFT 1
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_READ_FIFO_STATUS_OVERFLOW_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: READ_FIFO_STATUS :: UNDERFLOW [00:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_READ_FIFO_STATUS_UNDERFLOW_MASK 0x00000001
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_READ_FIFO_STATUS_UNDERFLOW_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_READ_FIFO_STATUS_UNDERFLOW_DEFAULT 0x00000000
-
-/***************************************************************************
- *READ_FIFO_CLEAR - Read fifo status clear register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_0_0 :: READ_FIFO_CLEAR :: reserved0 [31:01] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_READ_FIFO_CLEAR_reserved0_MASK 0xfffffffe
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_READ_FIFO_CLEAR_reserved0_SHIFT 1
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: READ_FIFO_CLEAR :: CLEAR [00:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_READ_FIFO_CLEAR_CLEAR_MASK 0x00000001
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_READ_FIFO_CLEAR_CLEAR_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_READ_FIFO_CLEAR_CLEAR_DEFAULT 0x00000000
-
-/***************************************************************************
- *IDLE_PAD_CONTROL - Idle mode SSTL pad control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_0_0 :: IDLE_PAD_CONTROL :: IDLE [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_IDLE_PAD_CONTROL_IDLE_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_IDLE_PAD_CONTROL_IDLE_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_IDLE_PAD_CONTROL_IDLE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: IDLE_PAD_CONTROL :: reserved0 [30:20] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_IDLE_PAD_CONTROL_reserved0_MASK 0x7ff00000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_IDLE_PAD_CONTROL_reserved0_SHIFT 20
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: IDLE_PAD_CONTROL :: AUTO_DQ_RXENB_MODE [19:18] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_IDLE_PAD_CONTROL_AUTO_DQ_RXENB_MODE_MASK 0x000c0000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_IDLE_PAD_CONTROL_AUTO_DQ_RXENB_MODE_SHIFT 18
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_IDLE_PAD_CONTROL_AUTO_DQ_RXENB_MODE_DEFAULT 0x00000001
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: IDLE_PAD_CONTROL :: AUTO_DQ_IDDQ_MODE [17:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_IDLE_PAD_CONTROL_AUTO_DQ_IDDQ_MODE_MASK 0x00030000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_IDLE_PAD_CONTROL_AUTO_DQ_IDDQ_MODE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_IDLE_PAD_CONTROL_AUTO_DQ_IDDQ_MODE_DEFAULT 0x00000001
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: IDLE_PAD_CONTROL :: reserved_for_padding1 [15:15] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_IDLE_PAD_CONTROL_reserved_for_padding1_MASK 0x00008000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_IDLE_PAD_CONTROL_reserved_for_padding1_SHIFT 15
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: IDLE_PAD_CONTROL :: IO_IDLE_ENABLE [14:04] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_IDLE_PAD_CONTROL_IO_IDLE_ENABLE_MASK 0x00007ff0
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_IDLE_PAD_CONTROL_IO_IDLE_ENABLE_SHIFT 4
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_IDLE_PAD_CONTROL_IO_IDLE_ENABLE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: IDLE_PAD_CONTROL :: RXENB [03:03] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_IDLE_PAD_CONTROL_RXENB_MASK 0x00000008
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_IDLE_PAD_CONTROL_RXENB_SHIFT 3
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_IDLE_PAD_CONTROL_RXENB_DEFAULT 0x00000001
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: IDLE_PAD_CONTROL :: IDDQ [02:02] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_IDLE_PAD_CONTROL_IDDQ_MASK 0x00000004
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_IDLE_PAD_CONTROL_IDDQ_SHIFT 2
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_IDLE_PAD_CONTROL_IDDQ_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: IDLE_PAD_CONTROL :: DOUT_N [01:01] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_IDLE_PAD_CONTROL_DOUT_N_MASK 0x00000002
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_IDLE_PAD_CONTROL_DOUT_N_SHIFT 1
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: IDLE_PAD_CONTROL :: DOUT_P [00:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_IDLE_PAD_CONTROL_DOUT_P_MASK 0x00000001
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_IDLE_PAD_CONTROL_DOUT_P_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_IDLE_PAD_CONTROL_DOUT_P_DEFAULT 0x00000000
-
-/***************************************************************************
- *DRIVE_PAD_CTL - SSTL pad drive characteristics control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_0_0 :: DRIVE_PAD_CTL :: reserved0 [31:30] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_DRIVE_PAD_CTL_reserved0_MASK 0xc0000000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_DRIVE_PAD_CTL_reserved0_SHIFT 30
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: DRIVE_PAD_CTL :: BL_PD_IDLE_STRENGTH [29:25] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_DRIVE_PAD_CTL_BL_PD_IDLE_STRENGTH_MASK 0x3e000000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_DRIVE_PAD_CTL_BL_PD_IDLE_STRENGTH_SHIFT 25
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_DRIVE_PAD_CTL_BL_PD_IDLE_STRENGTH_DEFAULT 0x0000001f
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: DRIVE_PAD_CTL :: BL_ND_IDLE_STRENGTH [24:20] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_DRIVE_PAD_CTL_BL_ND_IDLE_STRENGTH_MASK 0x01f00000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_DRIVE_PAD_CTL_BL_ND_IDLE_STRENGTH_SHIFT 20
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_DRIVE_PAD_CTL_BL_ND_IDLE_STRENGTH_DEFAULT 0x0000001f
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: DRIVE_PAD_CTL :: BL_PD_TERM_STRENGTH [19:15] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_DRIVE_PAD_CTL_BL_PD_TERM_STRENGTH_MASK 0x000f8000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_DRIVE_PAD_CTL_BL_PD_TERM_STRENGTH_SHIFT 15
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_DRIVE_PAD_CTL_BL_PD_TERM_STRENGTH_DEFAULT 0x00000008
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: DRIVE_PAD_CTL :: BL_ND_TERM_STRENGTH [14:10] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_DRIVE_PAD_CTL_BL_ND_TERM_STRENGTH_MASK 0x00007c00
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_DRIVE_PAD_CTL_BL_ND_TERM_STRENGTH_SHIFT 10
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_DRIVE_PAD_CTL_BL_ND_TERM_STRENGTH_DEFAULT 0x00000008
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: DRIVE_PAD_CTL :: BL_PD_STRENGTH [09:05] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_DRIVE_PAD_CTL_BL_PD_STRENGTH_MASK 0x000003e0
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_DRIVE_PAD_CTL_BL_PD_STRENGTH_SHIFT 5
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_DRIVE_PAD_CTL_BL_PD_STRENGTH_DEFAULT 0x0000001f
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: DRIVE_PAD_CTL :: BL_ND_STRENGTH [04:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_DRIVE_PAD_CTL_BL_ND_STRENGTH_MASK 0x0000001f
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_DRIVE_PAD_CTL_BL_ND_STRENGTH_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_DRIVE_PAD_CTL_BL_ND_STRENGTH_DEFAULT 0x0000001f
-
-/***************************************************************************
- *RD_EN_DRIVE_PAD_CTL - SSTL read enable pad drive characteristics control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_0_0 :: RD_EN_DRIVE_PAD_CTL :: reserved0 [31:20] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_RD_EN_DRIVE_PAD_CTL_reserved0_MASK 0xfff00000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_RD_EN_DRIVE_PAD_CTL_reserved0_SHIFT 20
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: RD_EN_DRIVE_PAD_CTL :: EDC_RD_EN_PD_STRENGTH [19:15] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_RD_EN_DRIVE_PAD_CTL_EDC_RD_EN_PD_STRENGTH_MASK 0x000f8000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_RD_EN_DRIVE_PAD_CTL_EDC_RD_EN_PD_STRENGTH_SHIFT 15
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_RD_EN_DRIVE_PAD_CTL_EDC_RD_EN_PD_STRENGTH_DEFAULT 0x0000001f
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: RD_EN_DRIVE_PAD_CTL :: EDC_RD_EN_ND_STRENGTH [14:10] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_RD_EN_DRIVE_PAD_CTL_EDC_RD_EN_ND_STRENGTH_MASK 0x00007c00
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_RD_EN_DRIVE_PAD_CTL_EDC_RD_EN_ND_STRENGTH_SHIFT 10
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_RD_EN_DRIVE_PAD_CTL_EDC_RD_EN_ND_STRENGTH_DEFAULT 0x0000001f
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: RD_EN_DRIVE_PAD_CTL :: BL_RD_EN_PD_STRENGTH [09:05] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_RD_EN_DRIVE_PAD_CTL_BL_RD_EN_PD_STRENGTH_MASK 0x000003e0
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_RD_EN_DRIVE_PAD_CTL_BL_RD_EN_PD_STRENGTH_SHIFT 5
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_RD_EN_DRIVE_PAD_CTL_BL_RD_EN_PD_STRENGTH_DEFAULT 0x0000001f
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: RD_EN_DRIVE_PAD_CTL :: BL_RD_EN_ND_STRENGTH [04:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_RD_EN_DRIVE_PAD_CTL_BL_RD_EN_ND_STRENGTH_MASK 0x0000001f
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_RD_EN_DRIVE_PAD_CTL_BL_RD_EN_ND_STRENGTH_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_RD_EN_DRIVE_PAD_CTL_BL_RD_EN_ND_STRENGTH_DEFAULT 0x0000001f
-
-/***************************************************************************
- *STATIC_PAD_CTL - pad rx and tx characteristics control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_0_0 :: STATIC_PAD_CTL :: reserved0 [31:21] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_STATIC_PAD_CTL_reserved0_MASK 0xffe00000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_STATIC_PAD_CTL_reserved0_SHIFT 21
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: STATIC_PAD_CTL :: DQS_MODE [20:20] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_STATIC_PAD_CTL_DQS_MODE_MASK 0x00100000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_STATIC_PAD_CTL_DQS_MODE_SHIFT 20
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_STATIC_PAD_CTL_DQS_MODE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: STATIC_PAD_CTL :: reserved1 [19:18] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_STATIC_PAD_CTL_reserved1_MASK 0x000c0000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_STATIC_PAD_CTL_reserved1_SHIFT 18
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: STATIC_PAD_CTL :: EDC_MODE [17:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_STATIC_PAD_CTL_EDC_MODE_MASK 0x00030000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_STATIC_PAD_CTL_EDC_MODE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_STATIC_PAD_CTL_EDC_MODE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: STATIC_PAD_CTL :: reserved2 [15:15] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_STATIC_PAD_CTL_reserved2_MASK 0x00008000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_STATIC_PAD_CTL_reserved2_SHIFT 15
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: STATIC_PAD_CTL :: WDBI_ENABLE [14:14] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_STATIC_PAD_CTL_WDBI_ENABLE_MASK 0x00004000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_STATIC_PAD_CTL_WDBI_ENABLE_SHIFT 14
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_STATIC_PAD_CTL_WDBI_ENABLE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: STATIC_PAD_CTL :: RDBI_ENABLE [13:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_STATIC_PAD_CTL_RDBI_ENABLE_MASK 0x00002000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_STATIC_PAD_CTL_RDBI_ENABLE_SHIFT 13
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_STATIC_PAD_CTL_RDBI_ENABLE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: STATIC_PAD_CTL :: DM_MODE [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_STATIC_PAD_CTL_DM_MODE_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_STATIC_PAD_CTL_DM_MODE_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_STATIC_PAD_CTL_DM_MODE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: STATIC_PAD_CTL :: reserved3 [11:11] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_STATIC_PAD_CTL_reserved3_MASK 0x00000800
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_STATIC_PAD_CTL_reserved3_SHIFT 11
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: STATIC_PAD_CTL :: DQS_TX_PAUSE [10:10] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_STATIC_PAD_CTL_DQS_TX_PAUSE_MASK 0x00000400
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_STATIC_PAD_CTL_DQS_TX_PAUSE_SHIFT 10
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_STATIC_PAD_CTL_DQS_TX_PAUSE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: STATIC_PAD_CTL :: DQS_TX_DIS [09:09] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_STATIC_PAD_CTL_DQS_TX_DIS_MASK 0x00000200
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_STATIC_PAD_CTL_DQS_TX_DIS_SHIFT 9
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_STATIC_PAD_CTL_DQS_TX_DIS_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: STATIC_PAD_CTL :: reserved4 [08:08] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_STATIC_PAD_CTL_reserved4_MASK 0x00000100
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_STATIC_PAD_CTL_reserved4_SHIFT 8
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: STATIC_PAD_CTL :: TX_MODE [07:04] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_STATIC_PAD_CTL_TX_MODE_MASK 0x000000f0
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_STATIC_PAD_CTL_TX_MODE_SHIFT 4
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_STATIC_PAD_CTL_TX_MODE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: STATIC_PAD_CTL :: reserved5 [03:03] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_STATIC_PAD_CTL_reserved5_MASK 0x00000008
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_STATIC_PAD_CTL_reserved5_SHIFT 3
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: STATIC_PAD_CTL :: RX_MODE [02:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_STATIC_PAD_CTL_RX_MODE_MASK 0x00000007
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_STATIC_PAD_CTL_RX_MODE_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_STATIC_PAD_CTL_RX_MODE_DEFAULT 0x00000000
-
-/***************************************************************************
- *WR_PREAMBLE_MODE - Write cycle preamble control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_0_0 :: WR_PREAMBLE_MODE :: reserved0 [31:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_WR_PREAMBLE_MODE_reserved0_MASK 0xffff0000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_WR_PREAMBLE_MODE_reserved0_SHIFT 16
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: WR_PREAMBLE_MODE :: DQ_POSTAM_BITS [15:14] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_WR_PREAMBLE_MODE_DQ_POSTAM_BITS_MASK 0x0000c000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_WR_PREAMBLE_MODE_DQ_POSTAM_BITS_SHIFT 14
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_WR_PREAMBLE_MODE_DQ_POSTAM_BITS_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: WR_PREAMBLE_MODE :: DQ_PREAM_BITS [13:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_WR_PREAMBLE_MODE_DQ_PREAM_BITS_MASK 0x00003000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_WR_PREAMBLE_MODE_DQ_PREAM_BITS_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_WR_PREAMBLE_MODE_DQ_PREAM_BITS_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: WR_PREAMBLE_MODE :: DQS [11:08] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_WR_PREAMBLE_MODE_DQS_MASK 0x00000f00
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_WR_PREAMBLE_MODE_DQS_SHIFT 8
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_WR_PREAMBLE_MODE_DQS_DEFAULT 0x0000000e
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: WR_PREAMBLE_MODE :: reserved1 [07:05] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_WR_PREAMBLE_MODE_reserved1_MASK 0x000000e0
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_WR_PREAMBLE_MODE_reserved1_SHIFT 5
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: WR_PREAMBLE_MODE :: DQS_POSTAM_BITS [04:03] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_WR_PREAMBLE_MODE_DQS_POSTAM_BITS_MASK 0x00000018
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_WR_PREAMBLE_MODE_DQS_POSTAM_BITS_SHIFT 3
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_WR_PREAMBLE_MODE_DQS_POSTAM_BITS_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: WR_PREAMBLE_MODE :: DQS_PREAM_BITS [02:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_WR_PREAMBLE_MODE_DQS_PREAM_BITS_MASK 0x00000007
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_WR_PREAMBLE_MODE_DQS_PREAM_BITS_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_WR_PREAMBLE_MODE_DQS_PREAM_BITS_DEFAULT 0x00000002
-
-/***************************************************************************
- *ODT_CONTROL - Read channel ODT control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_0_0 :: ODT_CONTROL :: reserved_for_padding0 [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_ODT_CONTROL_reserved_for_padding0_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_ODT_CONTROL_reserved_for_padding0_SHIFT 31
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: ODT_CONTROL :: reserved1 [30:10] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_ODT_CONTROL_reserved1_MASK 0x7ffffc00
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_ODT_CONTROL_reserved1_SHIFT 10
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: ODT_CONTROL :: ODT_ENABLE [09:09] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_ODT_CONTROL_ODT_ENABLE_MASK 0x00000200
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_ODT_CONTROL_ODT_ENABLE_SHIFT 9
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_ODT_CONTROL_ODT_ENABLE_DEFAULT 0x00000001
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: ODT_CONTROL :: ODT_DELAY [08:06] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_ODT_CONTROL_ODT_DELAY_MASK 0x000001c0
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_ODT_CONTROL_ODT_DELAY_SHIFT 6
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_ODT_CONTROL_ODT_DELAY_DEFAULT 0x00000001
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: ODT_CONTROL :: ODT_POST_LENGTH [05:03] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_ODT_CONTROL_ODT_POST_LENGTH_MASK 0x00000038
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_ODT_CONTROL_ODT_POST_LENGTH_SHIFT 3
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_ODT_CONTROL_ODT_POST_LENGTH_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: ODT_CONTROL :: ODT_PRE_LENGTH [02:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_ODT_CONTROL_ODT_PRE_LENGTH_MASK 0x00000007
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_ODT_CONTROL_ODT_PRE_LENGTH_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_ODT_CONTROL_ODT_PRE_LENGTH_DEFAULT 0x00000003
-
-/***************************************************************************
- *EDC_DPD_CONTROL - GDDR5M EDC digital phase detector control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_0_0 :: EDC_DPD_CONTROL :: reserved0 [31:06] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_DPD_CONTROL_reserved0_MASK 0xffffffc0
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_DPD_CONTROL_reserved0_SHIFT 6
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: EDC_DPD_CONTROL :: DQS_PHASE_OVERRIDE_VALUE [05:05] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_DPD_CONTROL_DQS_PHASE_OVERRIDE_VALUE_MASK 0x00000020
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_DPD_CONTROL_DQS_PHASE_OVERRIDE_VALUE_SHIFT 5
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_DPD_CONTROL_DQS_PHASE_OVERRIDE_VALUE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: EDC_DPD_CONTROL :: DQS_PHASE_OVERRIDE_ENABLE [04:04] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_DPD_CONTROL_DQS_PHASE_OVERRIDE_ENABLE_MASK 0x00000010
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_DPD_CONTROL_DQS_PHASE_OVERRIDE_ENABLE_SHIFT 4
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_DPD_CONTROL_DQS_PHASE_OVERRIDE_ENABLE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: EDC_DPD_CONTROL :: SET_ADJ_EN [03:03] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_DPD_CONTROL_SET_ADJ_EN_MASK 0x00000008
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_DPD_CONTROL_SET_ADJ_EN_SHIFT 3
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_DPD_CONTROL_SET_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: EDC_DPD_CONTROL :: UPDATE [02:02] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_DPD_CONTROL_UPDATE_MASK 0x00000004
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_DPD_CONTROL_UPDATE_SHIFT 2
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_DPD_CONTROL_UPDATE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: EDC_DPD_CONTROL :: MONITOR [01:01] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_DPD_CONTROL_MONITOR_MASK 0x00000002
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_DPD_CONTROL_MONITOR_SHIFT 1
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_DPD_CONTROL_MONITOR_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: EDC_DPD_CONTROL :: INIT [00:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_DPD_CONTROL_INIT_MASK 0x00000001
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_DPD_CONTROL_INIT_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_DPD_CONTROL_INIT_DEFAULT 0x00000000
-
-/***************************************************************************
- *EDC_DPD_STATUS - GDDR5M EDC digital phase detector status register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_0_0 :: EDC_DPD_STATUS :: reserved0 [31:25] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_DPD_STATUS_reserved0_MASK 0xfe000000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_DPD_STATUS_reserved0_SHIFT 25
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: EDC_DPD_STATUS :: CURRENT_DQS_PHASE [24:24] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_DPD_STATUS_CURRENT_DQS_PHASE_MASK 0x01000000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_DPD_STATUS_CURRENT_DQS_PHASE_SHIFT 24
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_DPD_STATUS_CURRENT_DQS_PHASE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: EDC_DPD_STATUS :: CURRENT_VDL_SETTING [23:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_DPD_STATUS_CURRENT_VDL_SETTING_MASK 0x00ff0000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_DPD_STATUS_CURRENT_VDL_SETTING_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_DPD_STATUS_CURRENT_VDL_SETTING_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: EDC_DPD_STATUS :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_DPD_STATUS_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_DPD_STATUS_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: EDC_DPD_STATUS :: INIT_DQS_PHASE [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_DPD_STATUS_INIT_DQS_PHASE_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_DPD_STATUS_INIT_DQS_PHASE_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_DPD_STATUS_INIT_DQS_PHASE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: EDC_DPD_STATUS :: INIT_VDL_SETTING [11:04] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_DPD_STATUS_INIT_VDL_SETTING_MASK 0x00000ff0
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_DPD_STATUS_INIT_VDL_SETTING_SHIFT 4
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_DPD_STATUS_INIT_VDL_SETTING_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: EDC_DPD_STATUS :: EDGE_ERROR [03:03] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_DPD_STATUS_EDGE_ERROR_MASK 0x00000008
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_DPD_STATUS_EDGE_ERROR_SHIFT 3
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_DPD_STATUS_EDGE_ERROR_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: EDC_DPD_STATUS :: MONITOR_BUSY [02:02] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_DPD_STATUS_MONITOR_BUSY_MASK 0x00000004
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_DPD_STATUS_MONITOR_BUSY_SHIFT 2
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_DPD_STATUS_MONITOR_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: EDC_DPD_STATUS :: INIT_BUSY [01:01] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_DPD_STATUS_INIT_BUSY_MASK 0x00000002
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_DPD_STATUS_INIT_BUSY_SHIFT 1
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_DPD_STATUS_INIT_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: EDC_DPD_STATUS :: INIT_DONE [00:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_DPD_STATUS_INIT_DONE_MASK 0x00000001
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_DPD_STATUS_INIT_DONE_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_DPD_STATUS_INIT_DONE_DEFAULT 0x00000000
-
-/***************************************************************************
- *EDC_DPD_OUT_CONTROL - GDDR5M EDC digital phase detector output signal control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_0_0 :: EDC_DPD_OUT_CONTROL :: reserved0 [31:20] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_DPD_OUT_CONTROL_reserved0_MASK 0xfff00000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_DPD_OUT_CONTROL_reserved0_SHIFT 20
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: EDC_DPD_OUT_CONTROL :: LOWER_LIMIT [19:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_DPD_OUT_CONTROL_LOWER_LIMIT_MASK 0x000ff000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_DPD_OUT_CONTROL_LOWER_LIMIT_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_DPD_OUT_CONTROL_LOWER_LIMIT_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: EDC_DPD_OUT_CONTROL :: UPPER_LIMIT [11:04] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_DPD_OUT_CONTROL_UPPER_LIMIT_MASK 0x00000ff0
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_DPD_OUT_CONTROL_UPPER_LIMIT_SHIFT 4
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_DPD_OUT_CONTROL_UPPER_LIMIT_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: EDC_DPD_OUT_CONTROL :: reserved1 [03:01] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_DPD_OUT_CONTROL_reserved1_MASK 0x0000000e
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_DPD_OUT_CONTROL_reserved1_SHIFT 1
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: EDC_DPD_OUT_CONTROL :: ENABLE [00:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_DPD_OUT_CONTROL_ENABLE_MASK 0x00000001
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_DPD_OUT_CONTROL_ENABLE_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_DPD_OUT_CONTROL_ENABLE_DEFAULT 0x00000000
-
-/***************************************************************************
- *EDC_DPD_OUT_STATUS - GDDR5M EDC digital phase detector output signal status register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_0_0 :: EDC_DPD_OUT_STATUS :: reserved0 [31:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_DPD_OUT_STATUS_reserved0_MASK 0xfffff000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_DPD_OUT_STATUS_reserved0_SHIFT 12
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: EDC_DPD_OUT_STATUS :: VDL_SETTING [11:04] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_DPD_OUT_STATUS_VDL_SETTING_MASK 0x00000ff0
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_DPD_OUT_STATUS_VDL_SETTING_SHIFT 4
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_DPD_OUT_STATUS_VDL_SETTING_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: EDC_DPD_OUT_STATUS :: reserved1 [03:01] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_DPD_OUT_STATUS_reserved1_MASK 0x0000000e
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_DPD_OUT_STATUS_reserved1_SHIFT 1
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: EDC_DPD_OUT_STATUS :: VALID [00:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_DPD_OUT_STATUS_VALID_MASK 0x00000001
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_DPD_OUT_STATUS_VALID_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_DPD_OUT_STATUS_VALID_DEFAULT 0x00000000
-
-/***************************************************************************
- *EDC_DPD_OUT_STATUS_CLEAR - GDDR5M EDC digital phase detector output signal status clear register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_0_0 :: EDC_DPD_OUT_STATUS_CLEAR :: reserved0 [31:01] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_DPD_OUT_STATUS_CLEAR_reserved0_MASK 0xfffffffe
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_DPD_OUT_STATUS_CLEAR_reserved0_SHIFT 1
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: EDC_DPD_OUT_STATUS_CLEAR :: CLEAR [00:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_DPD_OUT_STATUS_CLEAR_CLEAR_MASK 0x00000001
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_DPD_OUT_STATUS_CLEAR_CLEAR_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_DPD_OUT_STATUS_CLEAR_CLEAR_DEFAULT 0x00000000
-
-/***************************************************************************
- *EDC_CRC_CONTROL - GDDR5M EDC signal path CRC control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_0_0 :: EDC_CRC_CONTROL :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_CRC_CONTROL_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_CRC_CONTROL_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_CRC_CONTROL_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: EDC_CRC_CONTROL :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_CRC_CONTROL_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_CRC_CONTROL_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: EDC_CRC_CONTROL :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_CRC_CONTROL_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_CRC_CONTROL_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_CRC_CONTROL_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: EDC_CRC_CONTROL :: reserved1 [15:11] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_CRC_CONTROL_reserved1_MASK 0x0000f800
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_CRC_CONTROL_reserved1_SHIFT 11
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: EDC_CRC_CONTROL :: CRCWL [10:08] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_CRC_CONTROL_CRCWL_MASK 0x00000700
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_CRC_CONTROL_CRCWL_SHIFT 8
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_CRC_CONTROL_CRCWL_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: EDC_CRC_CONTROL :: reserved2 [07:06] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_CRC_CONTROL_reserved2_MASK 0x000000c0
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_CRC_CONTROL_reserved2_SHIFT 6
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: EDC_CRC_CONTROL :: CRCRL [05:04] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_CRC_CONTROL_CRCRL_MASK 0x00000030
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_CRC_CONTROL_CRCRL_SHIFT 4
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_CRC_CONTROL_CRCRL_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: EDC_CRC_CONTROL :: reserved3 [03:03] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_CRC_CONTROL_reserved3_MASK 0x00000008
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_CRC_CONTROL_reserved3_SHIFT 3
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: EDC_CRC_CONTROL :: COUNT_MODE [02:02] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_CRC_CONTROL_COUNT_MODE_MASK 0x00000004
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_CRC_CONTROL_COUNT_MODE_SHIFT 2
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_CRC_CONTROL_COUNT_MODE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: EDC_CRC_CONTROL :: ENABLE_WR [01:01] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_CRC_CONTROL_ENABLE_WR_MASK 0x00000002
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_CRC_CONTROL_ENABLE_WR_SHIFT 1
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_CRC_CONTROL_ENABLE_WR_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: EDC_CRC_CONTROL :: ENABLE_RD [00:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_CRC_CONTROL_ENABLE_RD_MASK 0x00000001
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_CRC_CONTROL_ENABLE_RD_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_CRC_CONTROL_ENABLE_RD_DEFAULT 0x00000000
-
-/***************************************************************************
- *EDC_CRC_STATUS - GDDR5M EDC signal path CRC status register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_0_0 :: EDC_CRC_STATUS :: reserved0 [31:04] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_CRC_STATUS_reserved0_MASK 0xfffffff0
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_CRC_STATUS_reserved0_SHIFT 4
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: EDC_CRC_STATUS :: WR_FAIL [03:03] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_CRC_STATUS_WR_FAIL_MASK 0x00000008
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_CRC_STATUS_WR_FAIL_SHIFT 3
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_CRC_STATUS_WR_FAIL_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: EDC_CRC_STATUS :: WR_PASS [02:02] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_CRC_STATUS_WR_PASS_MASK 0x00000004
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_CRC_STATUS_WR_PASS_SHIFT 2
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_CRC_STATUS_WR_PASS_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: EDC_CRC_STATUS :: RD_FAIL [01:01] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_CRC_STATUS_RD_FAIL_MASK 0x00000002
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_CRC_STATUS_RD_FAIL_SHIFT 1
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_CRC_STATUS_RD_FAIL_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: EDC_CRC_STATUS :: RD_PASS [00:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_CRC_STATUS_RD_PASS_MASK 0x00000001
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_CRC_STATUS_RD_PASS_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_CRC_STATUS_RD_PASS_DEFAULT 0x00000000
-
-/***************************************************************************
- *EDC_CRC_COUNT - GDDR5M EDC signal path CRC counter register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_0_0 :: EDC_CRC_COUNT :: reserved0 [31:28] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_CRC_COUNT_reserved0_MASK 0xf0000000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_CRC_COUNT_reserved0_SHIFT 28
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: EDC_CRC_COUNT :: WR_COUNT [27:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_CRC_COUNT_WR_COUNT_MASK 0x0fff0000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_CRC_COUNT_WR_COUNT_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_CRC_COUNT_WR_COUNT_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: EDC_CRC_COUNT :: reserved1 [15:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_CRC_COUNT_reserved1_MASK 0x0000f000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_CRC_COUNT_reserved1_SHIFT 12
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: EDC_CRC_COUNT :: RD_COUNT [11:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_CRC_COUNT_RD_COUNT_MASK 0x00000fff
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_CRC_COUNT_RD_COUNT_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_CRC_COUNT_RD_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *EDC_CRC_STATUS_CLEAR - GDDR5M EDC signal path CRC counter register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_0_0 :: EDC_CRC_STATUS_CLEAR :: reserved0 [31:01] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_CRC_STATUS_CLEAR_reserved0_MASK 0xfffffffe
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_CRC_STATUS_CLEAR_reserved0_SHIFT 1
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: EDC_CRC_STATUS_CLEAR :: CLEAR [00:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_CRC_STATUS_CLEAR_CLEAR_MASK 0x00000001
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_CRC_STATUS_CLEAR_CLEAR_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_CRC_STATUS_CLEAR_CLEAR_DEFAULT 0x00000000
-
-/***************************************************************************
- *BL_SPARE_REG - Byte-Lane Spare register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_0_0 :: BL_SPARE_REG :: reserved_for_eco0 [31:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_BL_SPARE_REG_reserved_for_eco0_MASK 0xffffffff
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_BL_SPARE_REG_reserved_for_eco0_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_BL_SPARE_REG_reserved_for_eco0_DEFAULT 0x00000000
-
-#endif /* #ifndef BCHP_DDR34_PHY_BYTE_LANE_0_0_H__ */
-
-/* End of File */
diff --git a/include/linux/brcmstb/7145a0/bchp_ddr34_phy_byte_lane_0_1.h b/include/linux/brcmstb/7145a0/bchp_ddr34_phy_byte_lane_0_1.h
deleted file mode 100644
index a7d250d..0000000
--- a/include/linux/brcmstb/7145a0/bchp_ddr34_phy_byte_lane_0_1.h
+++ /dev/null
@@ -1,2101 +0,0 @@
-/***************************************************************************
- * Copyright (c) 1999-2014, Broadcom Corporation
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
- *
- * Module Description:
- * DO NOT EDIT THIS FILE DIRECTLY
- *
- * This module was generated magically with RDB from a source description
- * file. You must edit the source file for changes to be made to this file.
- *
- *
- * Date: Generated on Wed Sep 3 13:17:35 2014
- * Full Compile MD5 Checksum a8ee62ccf9dde43435c825f266da463d
- * (minus title and desc)
- * MD5 Checksum e373b364a1742e13a0f9eb15fd8aa94f
- *
- * Compiled with: RDB Utility combo_header.pl
- * RDB Parser 3.0
- * unknown unknown
- * Perl Interpreter 5.008005
- * Operating System linux
- *
- * Revision History:
- *
- * $brcm_Log: $
- *
- ***************************************************************************/
-
-#ifndef BCHP_DDR34_PHY_BYTE_LANE_0_1_H__
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_H__
-
-/***************************************************************************
- *DDR34_PHY_BYTE_LANE_0_1 - DDR34 Byte Lane #0 control registers
- ***************************************************************************/
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_WR_DQS_P 0x203c6400 /* Write channel DQS-P VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_WR_DQS_N 0x203c6404 /* Write channel DQS-N VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_WR_DQ0 0x203c6408 /* Write channel DQ0 VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_WR_DQ1 0x203c640c /* Write channel DQ1 VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_WR_DQ2 0x203c6410 /* Write channel DQ2 VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_WR_DQ3 0x203c6414 /* Write channel DQ3 VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_WR_DQ4 0x203c6418 /* Write channel DQ4 VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_WR_DQ5 0x203c641c /* Write channel DQ5 VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_WR_DQ6 0x203c6420 /* Write channel DQ6 VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_WR_DQ7 0x203c6424 /* Write channel DQ7 VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_WR_DM 0x203c6428 /* Write channel DM VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_WR_EDC 0x203c642c /* Write channel EDC VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQSP 0x203c6430 /* Read channel DQSP VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQSN 0x203c6434 /* Read channel DQSP VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ0P 0x203c6438 /* Read channel DQ0-P VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ0N 0x203c643c /* Read channel DQ0-N VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ1P 0x203c6440 /* Read channel DQ1-P VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ1N 0x203c6444 /* Read channel DQ1-N VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ2P 0x203c6448 /* Read channel DQ2-P VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ2N 0x203c644c /* Read channel DQ2-N VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ3P 0x203c6450 /* Read channel DQ3-P VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ3N 0x203c6454 /* Read channel DQ3-N VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ4P 0x203c6458 /* Read channel DQ4-P VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ4N 0x203c645c /* Read channel DQ4-N VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ5P 0x203c6460 /* Read channel DQ5-P VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ5N 0x203c6464 /* Read channel DQ5-N VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ6P 0x203c6468 /* Read channel DQ6-P VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ6N 0x203c646c /* Read channel DQ6-N VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ7P 0x203c6470 /* Read channel DQ7-P VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ7N 0x203c6474 /* Read channel DQ7-N VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DMP 0x203c6478 /* Read channel DM-P VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DMN 0x203c647c /* Read channel DM-N VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_EDCP 0x203c6480 /* Read channel EDC-P VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_EDCN 0x203c6484 /* Read channel EDC-N VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_EN_CS0 0x203c6488 /* Read channel CS_N[0] read enable VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_EN_CS1 0x203c648c /* Read channel CS_N[1] read enable VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CLK_CONTROL 0x203c6490 /* DDR interface signal Write Leveling CLK VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_LDE_CONTROL 0x203c6494 /* DDR interface signal Write Leveling Capture Enable VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_RD_EN_DLY_CYC 0x203c64a0 /* Read enable bit-clock cycle delay control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_WR_CHAN_DLY_CYC 0x203c64a4 /* Write leveling bit-clock cycle delay control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_READ_CONTROL 0x203c64b0 /* Read channel datapath control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_READ_FIFO_ADDR 0x203c64b4 /* Read fifo addresss pointer register */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_READ_FIFO_DATA 0x203c64b8 /* Read fifo data register */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_READ_FIFO_DM_DBI 0x203c64bc /* Read fifo dm/dbi register */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_READ_FIFO_STATUS 0x203c64c0 /* Read fifo status register */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_READ_FIFO_CLEAR 0x203c64c4 /* Read fifo status clear register */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_IDLE_PAD_CONTROL 0x203c64c8 /* Idle mode SSTL pad control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_DRIVE_PAD_CTL 0x203c64cc /* SSTL pad drive characteristics control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_RD_EN_DRIVE_PAD_CTL 0x203c64d0 /* SSTL read enable pad drive characteristics control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_STATIC_PAD_CTL 0x203c64d4 /* pad rx and tx characteristics control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_WR_PREAMBLE_MODE 0x203c64d8 /* Write cycle preamble control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_ODT_CONTROL 0x203c64e0 /* Read channel ODT control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_EDC_DPD_CONTROL 0x203c64f0 /* GDDR5M EDC digital phase detector control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_EDC_DPD_STATUS 0x203c64f4 /* GDDR5M EDC digital phase detector status register */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_EDC_DPD_OUT_CONTROL 0x203c64f8 /* GDDR5M EDC digital phase detector output signal control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_EDC_DPD_OUT_STATUS 0x203c64fc /* GDDR5M EDC digital phase detector output signal status register */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_EDC_DPD_OUT_STATUS_CLEAR 0x203c6500 /* GDDR5M EDC digital phase detector output signal status clear register */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_EDC_CRC_CONTROL 0x203c6504 /* GDDR5M EDC signal path CRC control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_EDC_CRC_STATUS 0x203c6508 /* GDDR5M EDC signal path CRC status register */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_EDC_CRC_COUNT 0x203c650c /* GDDR5M EDC signal path CRC counter register */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_EDC_CRC_STATUS_CLEAR 0x203c6510 /* GDDR5M EDC signal path CRC counter register */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_BL_SPARE_REG 0x203c6514 /* Byte-Lane Spare register */
-
-/***************************************************************************
- *VDL_CONTROL_WR_DQS_P - Write channel DQS-P VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_0_1 :: VDL_CONTROL_WR_DQS_P :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_WR_DQS_P_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_WR_DQS_P_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_WR_DQS_P_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_1 :: VDL_CONTROL_WR_DQS_P :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_WR_DQS_P_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_WR_DQS_P_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_0_1 :: VDL_CONTROL_WR_DQS_P :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_WR_DQS_P_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_WR_DQS_P_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_WR_DQS_P_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_1 :: VDL_CONTROL_WR_DQS_P :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_WR_DQS_P_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_WR_DQS_P_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_0_1 :: VDL_CONTROL_WR_DQS_P :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_WR_DQS_P_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_WR_DQS_P_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_WR_DQS_P_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_1 :: VDL_CONTROL_WR_DQS_P :: reserved2 [11:09] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_WR_DQS_P_reserved2_MASK 0x00000e00
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_WR_DQS_P_reserved2_SHIFT 9
-
-/* DDR34_PHY_BYTE_LANE_0_1 :: VDL_CONTROL_WR_DQS_P :: VDL_STEP [08:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_WR_DQS_P_VDL_STEP_MASK 0x000001ff
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_WR_DQS_P_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_WR_DQS_P_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_WR_DQS_N - Write channel DQS-N VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_0_1 :: VDL_CONTROL_WR_DQS_N :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_WR_DQS_N_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_WR_DQS_N_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_WR_DQS_N_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_1 :: VDL_CONTROL_WR_DQS_N :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_WR_DQS_N_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_WR_DQS_N_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_0_1 :: VDL_CONTROL_WR_DQS_N :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_WR_DQS_N_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_WR_DQS_N_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_WR_DQS_N_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_1 :: VDL_CONTROL_WR_DQS_N :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_WR_DQS_N_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_WR_DQS_N_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_0_1 :: VDL_CONTROL_WR_DQS_N :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_WR_DQS_N_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_WR_DQS_N_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_WR_DQS_N_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_1 :: VDL_CONTROL_WR_DQS_N :: reserved2 [11:09] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_WR_DQS_N_reserved2_MASK 0x00000e00
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_WR_DQS_N_reserved2_SHIFT 9
-
-/* DDR34_PHY_BYTE_LANE_0_1 :: VDL_CONTROL_WR_DQS_N :: VDL_STEP [08:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_WR_DQS_N_VDL_STEP_MASK 0x000001ff
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_WR_DQS_N_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_WR_DQS_N_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_WR_DQ0 - Write channel DQ0 VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_0_1 :: VDL_CONTROL_WR_DQ0 :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_WR_DQ0_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_WR_DQ0_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_WR_DQ0_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_1 :: VDL_CONTROL_WR_DQ0 :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_WR_DQ0_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_WR_DQ0_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_0_1 :: VDL_CONTROL_WR_DQ0 :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_WR_DQ0_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_WR_DQ0_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_WR_DQ0_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_1 :: VDL_CONTROL_WR_DQ0 :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_WR_DQ0_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_WR_DQ0_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_0_1 :: VDL_CONTROL_WR_DQ0 :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_WR_DQ0_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_WR_DQ0_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_WR_DQ0_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_1 :: VDL_CONTROL_WR_DQ0 :: reserved2 [11:09] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_WR_DQ0_reserved2_MASK 0x00000e00
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_WR_DQ0_reserved2_SHIFT 9
-
-/* DDR34_PHY_BYTE_LANE_0_1 :: VDL_CONTROL_WR_DQ0 :: VDL_STEP [08:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_WR_DQ0_VDL_STEP_MASK 0x000001ff
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_WR_DQ0_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_WR_DQ0_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_WR_DQ1 - Write channel DQ1 VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_0_1 :: VDL_CONTROL_WR_DQ1 :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_WR_DQ1_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_WR_DQ1_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_WR_DQ1_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_1 :: VDL_CONTROL_WR_DQ1 :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_WR_DQ1_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_WR_DQ1_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_0_1 :: VDL_CONTROL_WR_DQ1 :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_WR_DQ1_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_WR_DQ1_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_WR_DQ1_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_1 :: VDL_CONTROL_WR_DQ1 :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_WR_DQ1_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_WR_DQ1_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_0_1 :: VDL_CONTROL_WR_DQ1 :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_WR_DQ1_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_WR_DQ1_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_WR_DQ1_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_1 :: VDL_CONTROL_WR_DQ1 :: reserved2 [11:09] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_WR_DQ1_reserved2_MASK 0x00000e00
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_WR_DQ1_reserved2_SHIFT 9
-
-/* DDR34_PHY_BYTE_LANE_0_1 :: VDL_CONTROL_WR_DQ1 :: VDL_STEP [08:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_WR_DQ1_VDL_STEP_MASK 0x000001ff
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_WR_DQ1_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_WR_DQ1_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_WR_DQ2 - Write channel DQ2 VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_0_1 :: VDL_CONTROL_WR_DQ2 :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_WR_DQ2_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_WR_DQ2_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_WR_DQ2_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_1 :: VDL_CONTROL_WR_DQ2 :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_WR_DQ2_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_WR_DQ2_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_0_1 :: VDL_CONTROL_WR_DQ2 :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_WR_DQ2_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_WR_DQ2_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_WR_DQ2_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_1 :: VDL_CONTROL_WR_DQ2 :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_WR_DQ2_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_WR_DQ2_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_0_1 :: VDL_CONTROL_WR_DQ2 :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_WR_DQ2_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_WR_DQ2_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_WR_DQ2_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_1 :: VDL_CONTROL_WR_DQ2 :: reserved2 [11:09] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_WR_DQ2_reserved2_MASK 0x00000e00
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_WR_DQ2_reserved2_SHIFT 9
-
-/* DDR34_PHY_BYTE_LANE_0_1 :: VDL_CONTROL_WR_DQ2 :: VDL_STEP [08:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_WR_DQ2_VDL_STEP_MASK 0x000001ff
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_WR_DQ2_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_WR_DQ2_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_WR_DQ3 - Write channel DQ3 VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_0_1 :: VDL_CONTROL_WR_DQ3 :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_WR_DQ3_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_WR_DQ3_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_WR_DQ3_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_1 :: VDL_CONTROL_WR_DQ3 :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_WR_DQ3_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_WR_DQ3_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_0_1 :: VDL_CONTROL_WR_DQ3 :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_WR_DQ3_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_WR_DQ3_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_WR_DQ3_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_1 :: VDL_CONTROL_WR_DQ3 :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_WR_DQ3_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_WR_DQ3_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_0_1 :: VDL_CONTROL_WR_DQ3 :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_WR_DQ3_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_WR_DQ3_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_WR_DQ3_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_1 :: VDL_CONTROL_WR_DQ3 :: reserved2 [11:09] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_WR_DQ3_reserved2_MASK 0x00000e00
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_WR_DQ3_reserved2_SHIFT 9
-
-/* DDR34_PHY_BYTE_LANE_0_1 :: VDL_CONTROL_WR_DQ3 :: VDL_STEP [08:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_WR_DQ3_VDL_STEP_MASK 0x000001ff
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_WR_DQ3_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_WR_DQ3_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_WR_DQ4 - Write channel DQ4 VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_0_1 :: VDL_CONTROL_WR_DQ4 :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_WR_DQ4_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_WR_DQ4_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_WR_DQ4_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_1 :: VDL_CONTROL_WR_DQ4 :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_WR_DQ4_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_WR_DQ4_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_0_1 :: VDL_CONTROL_WR_DQ4 :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_WR_DQ4_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_WR_DQ4_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_WR_DQ4_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_1 :: VDL_CONTROL_WR_DQ4 :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_WR_DQ4_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_WR_DQ4_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_0_1 :: VDL_CONTROL_WR_DQ4 :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_WR_DQ4_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_WR_DQ4_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_WR_DQ4_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_1 :: VDL_CONTROL_WR_DQ4 :: reserved2 [11:09] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_WR_DQ4_reserved2_MASK 0x00000e00
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_WR_DQ4_reserved2_SHIFT 9
-
-/* DDR34_PHY_BYTE_LANE_0_1 :: VDL_CONTROL_WR_DQ4 :: VDL_STEP [08:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_WR_DQ4_VDL_STEP_MASK 0x000001ff
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_WR_DQ4_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_WR_DQ4_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_WR_DQ5 - Write channel DQ5 VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_0_1 :: VDL_CONTROL_WR_DQ5 :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_WR_DQ5_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_WR_DQ5_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_WR_DQ5_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_1 :: VDL_CONTROL_WR_DQ5 :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_WR_DQ5_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_WR_DQ5_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_0_1 :: VDL_CONTROL_WR_DQ5 :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_WR_DQ5_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_WR_DQ5_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_WR_DQ5_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_1 :: VDL_CONTROL_WR_DQ5 :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_WR_DQ5_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_WR_DQ5_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_0_1 :: VDL_CONTROL_WR_DQ5 :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_WR_DQ5_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_WR_DQ5_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_WR_DQ5_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_1 :: VDL_CONTROL_WR_DQ5 :: reserved2 [11:09] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_WR_DQ5_reserved2_MASK 0x00000e00
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_WR_DQ5_reserved2_SHIFT 9
-
-/* DDR34_PHY_BYTE_LANE_0_1 :: VDL_CONTROL_WR_DQ5 :: VDL_STEP [08:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_WR_DQ5_VDL_STEP_MASK 0x000001ff
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_WR_DQ5_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_WR_DQ5_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_WR_DQ6 - Write channel DQ6 VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_0_1 :: VDL_CONTROL_WR_DQ6 :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_WR_DQ6_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_WR_DQ6_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_WR_DQ6_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_1 :: VDL_CONTROL_WR_DQ6 :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_WR_DQ6_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_WR_DQ6_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_0_1 :: VDL_CONTROL_WR_DQ6 :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_WR_DQ6_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_WR_DQ6_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_WR_DQ6_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_1 :: VDL_CONTROL_WR_DQ6 :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_WR_DQ6_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_WR_DQ6_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_0_1 :: VDL_CONTROL_WR_DQ6 :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_WR_DQ6_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_WR_DQ6_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_WR_DQ6_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_1 :: VDL_CONTROL_WR_DQ6 :: reserved2 [11:09] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_WR_DQ6_reserved2_MASK 0x00000e00
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_WR_DQ6_reserved2_SHIFT 9
-
-/* DDR34_PHY_BYTE_LANE_0_1 :: VDL_CONTROL_WR_DQ6 :: VDL_STEP [08:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_WR_DQ6_VDL_STEP_MASK 0x000001ff
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_WR_DQ6_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_WR_DQ6_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_WR_DQ7 - Write channel DQ7 VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_0_1 :: VDL_CONTROL_WR_DQ7 :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_WR_DQ7_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_WR_DQ7_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_WR_DQ7_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_1 :: VDL_CONTROL_WR_DQ7 :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_WR_DQ7_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_WR_DQ7_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_0_1 :: VDL_CONTROL_WR_DQ7 :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_WR_DQ7_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_WR_DQ7_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_WR_DQ7_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_1 :: VDL_CONTROL_WR_DQ7 :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_WR_DQ7_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_WR_DQ7_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_0_1 :: VDL_CONTROL_WR_DQ7 :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_WR_DQ7_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_WR_DQ7_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_WR_DQ7_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_1 :: VDL_CONTROL_WR_DQ7 :: reserved2 [11:09] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_WR_DQ7_reserved2_MASK 0x00000e00
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_WR_DQ7_reserved2_SHIFT 9
-
-/* DDR34_PHY_BYTE_LANE_0_1 :: VDL_CONTROL_WR_DQ7 :: VDL_STEP [08:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_WR_DQ7_VDL_STEP_MASK 0x000001ff
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_WR_DQ7_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_WR_DQ7_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_WR_DM - Write channel DM VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_0_1 :: VDL_CONTROL_WR_DM :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_WR_DM_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_WR_DM_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_WR_DM_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_1 :: VDL_CONTROL_WR_DM :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_WR_DM_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_WR_DM_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_0_1 :: VDL_CONTROL_WR_DM :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_WR_DM_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_WR_DM_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_WR_DM_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_1 :: VDL_CONTROL_WR_DM :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_WR_DM_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_WR_DM_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_0_1 :: VDL_CONTROL_WR_DM :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_WR_DM_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_WR_DM_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_WR_DM_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_1 :: VDL_CONTROL_WR_DM :: reserved2 [11:09] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_WR_DM_reserved2_MASK 0x00000e00
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_WR_DM_reserved2_SHIFT 9
-
-/* DDR34_PHY_BYTE_LANE_0_1 :: VDL_CONTROL_WR_DM :: VDL_STEP [08:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_WR_DM_VDL_STEP_MASK 0x000001ff
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_WR_DM_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_WR_DM_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_WR_EDC - Write channel EDC VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_0_1 :: VDL_CONTROL_WR_EDC :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_WR_EDC_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_WR_EDC_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_WR_EDC_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_1 :: VDL_CONTROL_WR_EDC :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_WR_EDC_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_WR_EDC_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_0_1 :: VDL_CONTROL_WR_EDC :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_WR_EDC_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_WR_EDC_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_WR_EDC_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_1 :: VDL_CONTROL_WR_EDC :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_WR_EDC_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_WR_EDC_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_0_1 :: VDL_CONTROL_WR_EDC :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_WR_EDC_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_WR_EDC_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_WR_EDC_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_1 :: VDL_CONTROL_WR_EDC :: reserved2 [11:09] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_WR_EDC_reserved2_MASK 0x00000e00
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_WR_EDC_reserved2_SHIFT 9
-
-/* DDR34_PHY_BYTE_LANE_0_1 :: VDL_CONTROL_WR_EDC :: VDL_STEP [08:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_WR_EDC_VDL_STEP_MASK 0x000001ff
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_WR_EDC_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_WR_EDC_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_RD_DQSP - Read channel DQSP VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_0_1 :: VDL_CONTROL_RD_DQSP :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQSP_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQSP_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQSP_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_1 :: VDL_CONTROL_RD_DQSP :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQSP_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQSP_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_0_1 :: VDL_CONTROL_RD_DQSP :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQSP_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQSP_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQSP_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_1 :: VDL_CONTROL_RD_DQSP :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQSP_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQSP_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_0_1 :: VDL_CONTROL_RD_DQSP :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQSP_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQSP_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQSP_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_1 :: VDL_CONTROL_RD_DQSP :: reserved2 [11:08] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQSP_reserved2_MASK 0x00000f00
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQSP_reserved2_SHIFT 8
-
-/* DDR34_PHY_BYTE_LANE_0_1 :: VDL_CONTROL_RD_DQSP :: VDL_STEP [07:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQSP_VDL_STEP_MASK 0x000000ff
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQSP_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQSP_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_RD_DQSN - Read channel DQSP VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_0_1 :: VDL_CONTROL_RD_DQSN :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQSN_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQSN_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQSN_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_1 :: VDL_CONTROL_RD_DQSN :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQSN_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQSN_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_0_1 :: VDL_CONTROL_RD_DQSN :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQSN_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQSN_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQSN_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_1 :: VDL_CONTROL_RD_DQSN :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQSN_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQSN_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_0_1 :: VDL_CONTROL_RD_DQSN :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQSN_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQSN_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQSN_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_1 :: VDL_CONTROL_RD_DQSN :: reserved2 [11:08] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQSN_reserved2_MASK 0x00000f00
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQSN_reserved2_SHIFT 8
-
-/* DDR34_PHY_BYTE_LANE_0_1 :: VDL_CONTROL_RD_DQSN :: VDL_STEP [07:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQSN_VDL_STEP_MASK 0x000000ff
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQSN_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQSN_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_RD_DQ0P - Read channel DQ0-P VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_0_1 :: VDL_CONTROL_RD_DQ0P :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ0P_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ0P_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ0P_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_1 :: VDL_CONTROL_RD_DQ0P :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ0P_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ0P_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_0_1 :: VDL_CONTROL_RD_DQ0P :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ0P_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ0P_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ0P_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_1 :: VDL_CONTROL_RD_DQ0P :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ0P_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ0P_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_0_1 :: VDL_CONTROL_RD_DQ0P :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ0P_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ0P_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ0P_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_1 :: VDL_CONTROL_RD_DQ0P :: reserved2 [11:08] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ0P_reserved2_MASK 0x00000f00
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ0P_reserved2_SHIFT 8
-
-/* DDR34_PHY_BYTE_LANE_0_1 :: VDL_CONTROL_RD_DQ0P :: VDL_STEP [07:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ0P_VDL_STEP_MASK 0x000000ff
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ0P_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ0P_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_RD_DQ0N - Read channel DQ0-N VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_0_1 :: VDL_CONTROL_RD_DQ0N :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ0N_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ0N_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ0N_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_1 :: VDL_CONTROL_RD_DQ0N :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ0N_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ0N_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_0_1 :: VDL_CONTROL_RD_DQ0N :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ0N_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ0N_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ0N_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_1 :: VDL_CONTROL_RD_DQ0N :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ0N_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ0N_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_0_1 :: VDL_CONTROL_RD_DQ0N :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ0N_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ0N_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ0N_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_1 :: VDL_CONTROL_RD_DQ0N :: reserved2 [11:08] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ0N_reserved2_MASK 0x00000f00
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ0N_reserved2_SHIFT 8
-
-/* DDR34_PHY_BYTE_LANE_0_1 :: VDL_CONTROL_RD_DQ0N :: VDL_STEP [07:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ0N_VDL_STEP_MASK 0x000000ff
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ0N_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ0N_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_RD_DQ1P - Read channel DQ1-P VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_0_1 :: VDL_CONTROL_RD_DQ1P :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ1P_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ1P_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ1P_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_1 :: VDL_CONTROL_RD_DQ1P :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ1P_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ1P_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_0_1 :: VDL_CONTROL_RD_DQ1P :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ1P_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ1P_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ1P_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_1 :: VDL_CONTROL_RD_DQ1P :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ1P_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ1P_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_0_1 :: VDL_CONTROL_RD_DQ1P :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ1P_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ1P_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ1P_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_1 :: VDL_CONTROL_RD_DQ1P :: reserved2 [11:08] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ1P_reserved2_MASK 0x00000f00
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ1P_reserved2_SHIFT 8
-
-/* DDR34_PHY_BYTE_LANE_0_1 :: VDL_CONTROL_RD_DQ1P :: VDL_STEP [07:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ1P_VDL_STEP_MASK 0x000000ff
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ1P_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ1P_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_RD_DQ1N - Read channel DQ1-N VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_0_1 :: VDL_CONTROL_RD_DQ1N :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ1N_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ1N_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ1N_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_1 :: VDL_CONTROL_RD_DQ1N :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ1N_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ1N_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_0_1 :: VDL_CONTROL_RD_DQ1N :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ1N_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ1N_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ1N_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_1 :: VDL_CONTROL_RD_DQ1N :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ1N_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ1N_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_0_1 :: VDL_CONTROL_RD_DQ1N :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ1N_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ1N_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ1N_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_1 :: VDL_CONTROL_RD_DQ1N :: reserved2 [11:08] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ1N_reserved2_MASK 0x00000f00
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ1N_reserved2_SHIFT 8
-
-/* DDR34_PHY_BYTE_LANE_0_1 :: VDL_CONTROL_RD_DQ1N :: VDL_STEP [07:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ1N_VDL_STEP_MASK 0x000000ff
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ1N_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ1N_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_RD_DQ2P - Read channel DQ2-P VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_0_1 :: VDL_CONTROL_RD_DQ2P :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ2P_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ2P_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ2P_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_1 :: VDL_CONTROL_RD_DQ2P :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ2P_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ2P_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_0_1 :: VDL_CONTROL_RD_DQ2P :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ2P_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ2P_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ2P_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_1 :: VDL_CONTROL_RD_DQ2P :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ2P_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ2P_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_0_1 :: VDL_CONTROL_RD_DQ2P :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ2P_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ2P_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ2P_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_1 :: VDL_CONTROL_RD_DQ2P :: reserved2 [11:08] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ2P_reserved2_MASK 0x00000f00
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ2P_reserved2_SHIFT 8
-
-/* DDR34_PHY_BYTE_LANE_0_1 :: VDL_CONTROL_RD_DQ2P :: VDL_STEP [07:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ2P_VDL_STEP_MASK 0x000000ff
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ2P_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ2P_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_RD_DQ2N - Read channel DQ2-N VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_0_1 :: VDL_CONTROL_RD_DQ2N :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ2N_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ2N_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ2N_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_1 :: VDL_CONTROL_RD_DQ2N :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ2N_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ2N_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_0_1 :: VDL_CONTROL_RD_DQ2N :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ2N_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ2N_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ2N_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_1 :: VDL_CONTROL_RD_DQ2N :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ2N_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ2N_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_0_1 :: VDL_CONTROL_RD_DQ2N :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ2N_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ2N_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ2N_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_1 :: VDL_CONTROL_RD_DQ2N :: reserved2 [11:08] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ2N_reserved2_MASK 0x00000f00
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ2N_reserved2_SHIFT 8
-
-/* DDR34_PHY_BYTE_LANE_0_1 :: VDL_CONTROL_RD_DQ2N :: VDL_STEP [07:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ2N_VDL_STEP_MASK 0x000000ff
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ2N_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ2N_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_RD_DQ3P - Read channel DQ3-P VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_0_1 :: VDL_CONTROL_RD_DQ3P :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ3P_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ3P_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ3P_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_1 :: VDL_CONTROL_RD_DQ3P :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ3P_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ3P_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_0_1 :: VDL_CONTROL_RD_DQ3P :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ3P_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ3P_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ3P_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_1 :: VDL_CONTROL_RD_DQ3P :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ3P_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ3P_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_0_1 :: VDL_CONTROL_RD_DQ3P :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ3P_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ3P_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ3P_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_1 :: VDL_CONTROL_RD_DQ3P :: reserved2 [11:08] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ3P_reserved2_MASK 0x00000f00
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ3P_reserved2_SHIFT 8
-
-/* DDR34_PHY_BYTE_LANE_0_1 :: VDL_CONTROL_RD_DQ3P :: VDL_STEP [07:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ3P_VDL_STEP_MASK 0x000000ff
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ3P_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ3P_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_RD_DQ3N - Read channel DQ3-N VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_0_1 :: VDL_CONTROL_RD_DQ3N :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ3N_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ3N_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ3N_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_1 :: VDL_CONTROL_RD_DQ3N :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ3N_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ3N_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_0_1 :: VDL_CONTROL_RD_DQ3N :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ3N_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ3N_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ3N_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_1 :: VDL_CONTROL_RD_DQ3N :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ3N_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ3N_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_0_1 :: VDL_CONTROL_RD_DQ3N :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ3N_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ3N_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ3N_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_1 :: VDL_CONTROL_RD_DQ3N :: reserved2 [11:08] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ3N_reserved2_MASK 0x00000f00
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ3N_reserved2_SHIFT 8
-
-/* DDR34_PHY_BYTE_LANE_0_1 :: VDL_CONTROL_RD_DQ3N :: VDL_STEP [07:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ3N_VDL_STEP_MASK 0x000000ff
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ3N_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ3N_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_RD_DQ4P - Read channel DQ4-P VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_0_1 :: VDL_CONTROL_RD_DQ4P :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ4P_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ4P_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ4P_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_1 :: VDL_CONTROL_RD_DQ4P :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ4P_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ4P_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_0_1 :: VDL_CONTROL_RD_DQ4P :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ4P_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ4P_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ4P_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_1 :: VDL_CONTROL_RD_DQ4P :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ4P_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ4P_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_0_1 :: VDL_CONTROL_RD_DQ4P :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ4P_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ4P_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ4P_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_1 :: VDL_CONTROL_RD_DQ4P :: reserved2 [11:08] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ4P_reserved2_MASK 0x00000f00
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ4P_reserved2_SHIFT 8
-
-/* DDR34_PHY_BYTE_LANE_0_1 :: VDL_CONTROL_RD_DQ4P :: VDL_STEP [07:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ4P_VDL_STEP_MASK 0x000000ff
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ4P_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ4P_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_RD_DQ4N - Read channel DQ4-N VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_0_1 :: VDL_CONTROL_RD_DQ4N :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ4N_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ4N_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ4N_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_1 :: VDL_CONTROL_RD_DQ4N :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ4N_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ4N_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_0_1 :: VDL_CONTROL_RD_DQ4N :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ4N_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ4N_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ4N_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_1 :: VDL_CONTROL_RD_DQ4N :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ4N_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ4N_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_0_1 :: VDL_CONTROL_RD_DQ4N :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ4N_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ4N_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ4N_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_1 :: VDL_CONTROL_RD_DQ4N :: reserved2 [11:08] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ4N_reserved2_MASK 0x00000f00
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ4N_reserved2_SHIFT 8
-
-/* DDR34_PHY_BYTE_LANE_0_1 :: VDL_CONTROL_RD_DQ4N :: VDL_STEP [07:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ4N_VDL_STEP_MASK 0x000000ff
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ4N_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ4N_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_RD_DQ5P - Read channel DQ5-P VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_0_1 :: VDL_CONTROL_RD_DQ5P :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ5P_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ5P_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ5P_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_1 :: VDL_CONTROL_RD_DQ5P :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ5P_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ5P_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_0_1 :: VDL_CONTROL_RD_DQ5P :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ5P_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ5P_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ5P_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_1 :: VDL_CONTROL_RD_DQ5P :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ5P_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ5P_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_0_1 :: VDL_CONTROL_RD_DQ5P :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ5P_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ5P_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ5P_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_1 :: VDL_CONTROL_RD_DQ5P :: reserved2 [11:08] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ5P_reserved2_MASK 0x00000f00
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ5P_reserved2_SHIFT 8
-
-/* DDR34_PHY_BYTE_LANE_0_1 :: VDL_CONTROL_RD_DQ5P :: VDL_STEP [07:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ5P_VDL_STEP_MASK 0x000000ff
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ5P_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ5P_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_RD_DQ5N - Read channel DQ5-N VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_0_1 :: VDL_CONTROL_RD_DQ5N :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ5N_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ5N_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ5N_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_1 :: VDL_CONTROL_RD_DQ5N :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ5N_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ5N_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_0_1 :: VDL_CONTROL_RD_DQ5N :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ5N_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ5N_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ5N_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_1 :: VDL_CONTROL_RD_DQ5N :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ5N_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ5N_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_0_1 :: VDL_CONTROL_RD_DQ5N :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ5N_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ5N_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ5N_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_1 :: VDL_CONTROL_RD_DQ5N :: reserved2 [11:08] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ5N_reserved2_MASK 0x00000f00
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ5N_reserved2_SHIFT 8
-
-/* DDR34_PHY_BYTE_LANE_0_1 :: VDL_CONTROL_RD_DQ5N :: VDL_STEP [07:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ5N_VDL_STEP_MASK 0x000000ff
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ5N_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ5N_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_RD_DQ6P - Read channel DQ6-P VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_0_1 :: VDL_CONTROL_RD_DQ6P :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ6P_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ6P_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ6P_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_1 :: VDL_CONTROL_RD_DQ6P :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ6P_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ6P_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_0_1 :: VDL_CONTROL_RD_DQ6P :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ6P_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ6P_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ6P_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_1 :: VDL_CONTROL_RD_DQ6P :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ6P_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ6P_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_0_1 :: VDL_CONTROL_RD_DQ6P :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ6P_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ6P_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ6P_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_1 :: VDL_CONTROL_RD_DQ6P :: reserved2 [11:08] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ6P_reserved2_MASK 0x00000f00
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ6P_reserved2_SHIFT 8
-
-/* DDR34_PHY_BYTE_LANE_0_1 :: VDL_CONTROL_RD_DQ6P :: VDL_STEP [07:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ6P_VDL_STEP_MASK 0x000000ff
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ6P_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ6P_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_RD_DQ6N - Read channel DQ6-N VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_0_1 :: VDL_CONTROL_RD_DQ6N :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ6N_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ6N_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ6N_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_1 :: VDL_CONTROL_RD_DQ6N :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ6N_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ6N_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_0_1 :: VDL_CONTROL_RD_DQ6N :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ6N_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ6N_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ6N_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_1 :: VDL_CONTROL_RD_DQ6N :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ6N_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ6N_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_0_1 :: VDL_CONTROL_RD_DQ6N :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ6N_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ6N_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ6N_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_1 :: VDL_CONTROL_RD_DQ6N :: reserved2 [11:08] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ6N_reserved2_MASK 0x00000f00
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ6N_reserved2_SHIFT 8
-
-/* DDR34_PHY_BYTE_LANE_0_1 :: VDL_CONTROL_RD_DQ6N :: VDL_STEP [07:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ6N_VDL_STEP_MASK 0x000000ff
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ6N_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ6N_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_RD_DQ7P - Read channel DQ7-P VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_0_1 :: VDL_CONTROL_RD_DQ7P :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ7P_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ7P_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ7P_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_1 :: VDL_CONTROL_RD_DQ7P :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ7P_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ7P_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_0_1 :: VDL_CONTROL_RD_DQ7P :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ7P_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ7P_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ7P_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_1 :: VDL_CONTROL_RD_DQ7P :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ7P_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ7P_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_0_1 :: VDL_CONTROL_RD_DQ7P :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ7P_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ7P_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ7P_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_1 :: VDL_CONTROL_RD_DQ7P :: reserved2 [11:08] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ7P_reserved2_MASK 0x00000f00
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ7P_reserved2_SHIFT 8
-
-/* DDR34_PHY_BYTE_LANE_0_1 :: VDL_CONTROL_RD_DQ7P :: VDL_STEP [07:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ7P_VDL_STEP_MASK 0x000000ff
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ7P_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ7P_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_RD_DQ7N - Read channel DQ7-N VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_0_1 :: VDL_CONTROL_RD_DQ7N :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ7N_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ7N_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ7N_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_1 :: VDL_CONTROL_RD_DQ7N :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ7N_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ7N_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_0_1 :: VDL_CONTROL_RD_DQ7N :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ7N_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ7N_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ7N_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_1 :: VDL_CONTROL_RD_DQ7N :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ7N_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ7N_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_0_1 :: VDL_CONTROL_RD_DQ7N :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ7N_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ7N_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ7N_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_1 :: VDL_CONTROL_RD_DQ7N :: reserved2 [11:08] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ7N_reserved2_MASK 0x00000f00
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ7N_reserved2_SHIFT 8
-
-/* DDR34_PHY_BYTE_LANE_0_1 :: VDL_CONTROL_RD_DQ7N :: VDL_STEP [07:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ7N_VDL_STEP_MASK 0x000000ff
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ7N_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ7N_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_RD_DMP - Read channel DM-P VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_0_1 :: VDL_CONTROL_RD_DMP :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DMP_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DMP_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DMP_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_1 :: VDL_CONTROL_RD_DMP :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DMP_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DMP_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_0_1 :: VDL_CONTROL_RD_DMP :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DMP_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DMP_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DMP_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_1 :: VDL_CONTROL_RD_DMP :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DMP_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DMP_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_0_1 :: VDL_CONTROL_RD_DMP :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DMP_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DMP_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DMP_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_1 :: VDL_CONTROL_RD_DMP :: reserved2 [11:08] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DMP_reserved2_MASK 0x00000f00
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DMP_reserved2_SHIFT 8
-
-/* DDR34_PHY_BYTE_LANE_0_1 :: VDL_CONTROL_RD_DMP :: VDL_STEP [07:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DMP_VDL_STEP_MASK 0x000000ff
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DMP_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DMP_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_RD_DMN - Read channel DM-N VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_0_1 :: VDL_CONTROL_RD_DMN :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DMN_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DMN_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DMN_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_1 :: VDL_CONTROL_RD_DMN :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DMN_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DMN_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_0_1 :: VDL_CONTROL_RD_DMN :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DMN_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DMN_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DMN_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_1 :: VDL_CONTROL_RD_DMN :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DMN_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DMN_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_0_1 :: VDL_CONTROL_RD_DMN :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DMN_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DMN_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DMN_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_1 :: VDL_CONTROL_RD_DMN :: reserved2 [11:08] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DMN_reserved2_MASK 0x00000f00
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DMN_reserved2_SHIFT 8
-
-/* DDR34_PHY_BYTE_LANE_0_1 :: VDL_CONTROL_RD_DMN :: VDL_STEP [07:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DMN_VDL_STEP_MASK 0x000000ff
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DMN_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DMN_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_RD_EDCP - Read channel EDC-P VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_0_1 :: VDL_CONTROL_RD_EDCP :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_EDCP_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_EDCP_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_EDCP_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_1 :: VDL_CONTROL_RD_EDCP :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_EDCP_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_EDCP_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_0_1 :: VDL_CONTROL_RD_EDCP :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_EDCP_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_EDCP_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_EDCP_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_1 :: VDL_CONTROL_RD_EDCP :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_EDCP_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_EDCP_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_0_1 :: VDL_CONTROL_RD_EDCP :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_EDCP_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_EDCP_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_EDCP_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_1 :: VDL_CONTROL_RD_EDCP :: reserved2 [11:08] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_EDCP_reserved2_MASK 0x00000f00
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_EDCP_reserved2_SHIFT 8
-
-/* DDR34_PHY_BYTE_LANE_0_1 :: VDL_CONTROL_RD_EDCP :: VDL_STEP [07:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_EDCP_VDL_STEP_MASK 0x000000ff
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_EDCP_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_EDCP_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_RD_EDCN - Read channel EDC-N VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_0_1 :: VDL_CONTROL_RD_EDCN :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_EDCN_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_EDCN_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_EDCN_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_1 :: VDL_CONTROL_RD_EDCN :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_EDCN_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_EDCN_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_0_1 :: VDL_CONTROL_RD_EDCN :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_EDCN_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_EDCN_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_EDCN_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_1 :: VDL_CONTROL_RD_EDCN :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_EDCN_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_EDCN_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_0_1 :: VDL_CONTROL_RD_EDCN :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_EDCN_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_EDCN_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_EDCN_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_1 :: VDL_CONTROL_RD_EDCN :: reserved2 [11:08] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_EDCN_reserved2_MASK 0x00000f00
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_EDCN_reserved2_SHIFT 8
-
-/* DDR34_PHY_BYTE_LANE_0_1 :: VDL_CONTROL_RD_EDCN :: VDL_STEP [07:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_EDCN_VDL_STEP_MASK 0x000000ff
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_EDCN_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_EDCN_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_RD_EN_CS0 - Read channel CS_N[0] read enable VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_0_1 :: VDL_CONTROL_RD_EN_CS0 :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_EN_CS0_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_EN_CS0_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_EN_CS0_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_1 :: VDL_CONTROL_RD_EN_CS0 :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_EN_CS0_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_EN_CS0_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_0_1 :: VDL_CONTROL_RD_EN_CS0 :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_EN_CS0_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_EN_CS0_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_EN_CS0_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_1 :: VDL_CONTROL_RD_EN_CS0 :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_EN_CS0_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_EN_CS0_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_0_1 :: VDL_CONTROL_RD_EN_CS0 :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_EN_CS0_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_EN_CS0_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_EN_CS0_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_1 :: VDL_CONTROL_RD_EN_CS0 :: reserved2 [11:08] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_EN_CS0_reserved2_MASK 0x00000f00
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_EN_CS0_reserved2_SHIFT 8
-
-/* DDR34_PHY_BYTE_LANE_0_1 :: VDL_CONTROL_RD_EN_CS0 :: VDL_STEP [07:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_EN_CS0_VDL_STEP_MASK 0x000000ff
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_EN_CS0_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_EN_CS0_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_RD_EN_CS1 - Read channel CS_N[1] read enable VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_0_1 :: VDL_CONTROL_RD_EN_CS1 :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_EN_CS1_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_EN_CS1_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_EN_CS1_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_1 :: VDL_CONTROL_RD_EN_CS1 :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_EN_CS1_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_EN_CS1_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_0_1 :: VDL_CONTROL_RD_EN_CS1 :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_EN_CS1_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_EN_CS1_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_EN_CS1_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_1 :: VDL_CONTROL_RD_EN_CS1 :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_EN_CS1_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_EN_CS1_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_0_1 :: VDL_CONTROL_RD_EN_CS1 :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_EN_CS1_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_EN_CS1_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_EN_CS1_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_1 :: VDL_CONTROL_RD_EN_CS1 :: reserved2 [11:08] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_EN_CS1_reserved2_MASK 0x00000f00
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_EN_CS1_reserved2_SHIFT 8
-
-/* DDR34_PHY_BYTE_LANE_0_1 :: VDL_CONTROL_RD_EN_CS1 :: VDL_STEP [07:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_EN_CS1_VDL_STEP_MASK 0x000000ff
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_EN_CS1_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_EN_CS1_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CLK_CONTROL - DDR interface signal Write Leveling CLK VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_0_1 :: VDL_CLK_CONTROL :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CLK_CONTROL_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CLK_CONTROL_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CLK_CONTROL_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_1 :: VDL_CLK_CONTROL :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CLK_CONTROL_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CLK_CONTROL_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_0_1 :: VDL_CLK_CONTROL :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CLK_CONTROL_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CLK_CONTROL_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CLK_CONTROL_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_1 :: VDL_CLK_CONTROL :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CLK_CONTROL_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CLK_CONTROL_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_0_1 :: VDL_CLK_CONTROL :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CLK_CONTROL_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CLK_CONTROL_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CLK_CONTROL_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_1 :: VDL_CLK_CONTROL :: reserved2 [11:09] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CLK_CONTROL_reserved2_MASK 0x00000e00
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CLK_CONTROL_reserved2_SHIFT 9
-
-/* DDR34_PHY_BYTE_LANE_0_1 :: VDL_CLK_CONTROL :: VDL_STEP [08:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CLK_CONTROL_VDL_STEP_MASK 0x000001ff
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CLK_CONTROL_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CLK_CONTROL_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_LDE_CONTROL - DDR interface signal Write Leveling Capture Enable VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_0_1 :: VDL_LDE_CONTROL :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_LDE_CONTROL_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_LDE_CONTROL_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_LDE_CONTROL_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_1 :: VDL_LDE_CONTROL :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_LDE_CONTROL_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_LDE_CONTROL_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_0_1 :: VDL_LDE_CONTROL :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_LDE_CONTROL_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_LDE_CONTROL_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_LDE_CONTROL_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_1 :: VDL_LDE_CONTROL :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_LDE_CONTROL_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_LDE_CONTROL_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_0_1 :: VDL_LDE_CONTROL :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_LDE_CONTROL_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_LDE_CONTROL_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_LDE_CONTROL_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_1 :: VDL_LDE_CONTROL :: reserved2 [11:09] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_LDE_CONTROL_reserved2_MASK 0x00000e00
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_LDE_CONTROL_reserved2_SHIFT 9
-
-/* DDR34_PHY_BYTE_LANE_0_1 :: VDL_LDE_CONTROL :: VDL_STEP [08:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_LDE_CONTROL_VDL_STEP_MASK 0x000001ff
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_LDE_CONTROL_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_LDE_CONTROL_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *RD_EN_DLY_CYC - Read enable bit-clock cycle delay control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_0_1 :: RD_EN_DLY_CYC :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_RD_EN_DLY_CYC_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_RD_EN_DLY_CYC_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_RD_EN_DLY_CYC_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_1 :: RD_EN_DLY_CYC :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_RD_EN_DLY_CYC_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_RD_EN_DLY_CYC_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_0_1 :: RD_EN_DLY_CYC :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_RD_EN_DLY_CYC_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_RD_EN_DLY_CYC_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_RD_EN_DLY_CYC_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_1 :: RD_EN_DLY_CYC :: reserved1 [15:08] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_RD_EN_DLY_CYC_reserved1_MASK 0x0000ff00
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_RD_EN_DLY_CYC_reserved1_SHIFT 8
-
-/* DDR34_PHY_BYTE_LANE_0_1 :: RD_EN_DLY_CYC :: CS1_CYCLES [07:04] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_RD_EN_DLY_CYC_CS1_CYCLES_MASK 0x000000f0
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_RD_EN_DLY_CYC_CS1_CYCLES_SHIFT 4
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_RD_EN_DLY_CYC_CS1_CYCLES_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_1 :: RD_EN_DLY_CYC :: CS0_CYCLES [03:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_RD_EN_DLY_CYC_CS0_CYCLES_MASK 0x0000000f
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_RD_EN_DLY_CYC_CS0_CYCLES_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_RD_EN_DLY_CYC_CS0_CYCLES_DEFAULT 0x00000000
-
-/***************************************************************************
- *WR_CHAN_DLY_CYC - Write leveling bit-clock cycle delay control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_0_1 :: WR_CHAN_DLY_CYC :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_WR_CHAN_DLY_CYC_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_WR_CHAN_DLY_CYC_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_WR_CHAN_DLY_CYC_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_1 :: WR_CHAN_DLY_CYC :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_WR_CHAN_DLY_CYC_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_WR_CHAN_DLY_CYC_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_0_1 :: WR_CHAN_DLY_CYC :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_WR_CHAN_DLY_CYC_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_WR_CHAN_DLY_CYC_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_WR_CHAN_DLY_CYC_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_1 :: WR_CHAN_DLY_CYC :: reserved1 [15:03] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_WR_CHAN_DLY_CYC_reserved1_MASK 0x0000fff8
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_WR_CHAN_DLY_CYC_reserved1_SHIFT 3
-
-/* DDR34_PHY_BYTE_LANE_0_1 :: WR_CHAN_DLY_CYC :: CYCLES [02:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_WR_CHAN_DLY_CYC_CYCLES_MASK 0x00000007
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_WR_CHAN_DLY_CYC_CYCLES_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_WR_CHAN_DLY_CYC_CYCLES_DEFAULT 0x00000000
-
-/***************************************************************************
- *READ_CONTROL - Read channel datapath control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_0_1 :: READ_CONTROL :: reserved0 [31:05] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_READ_CONTROL_reserved0_MASK 0xffffffe0
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_READ_CONTROL_reserved0_SHIFT 5
-
-/* DDR34_PHY_BYTE_LANE_0_1 :: READ_CONTROL :: MODE [04:04] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_READ_CONTROL_MODE_MASK 0x00000010
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_READ_CONTROL_MODE_SHIFT 4
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_READ_CONTROL_MODE_DEFAULT 0x00000001
-
-/* DDR34_PHY_BYTE_LANE_0_1 :: READ_CONTROL :: reserved1 [03:03] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_READ_CONTROL_reserved1_MASK 0x00000008
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_READ_CONTROL_reserved1_SHIFT 3
-
-/* DDR34_PHY_BYTE_LANE_0_1 :: READ_CONTROL :: RD_DATA_DLY [02:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_READ_CONTROL_RD_DATA_DLY_MASK 0x00000007
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_READ_CONTROL_RD_DATA_DLY_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_READ_CONTROL_RD_DATA_DLY_DEFAULT 0x00000007
-
-/***************************************************************************
- *READ_FIFO_ADDR - Read fifo addresss pointer register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_0_1 :: READ_FIFO_ADDR :: reserved0 [31:03] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_READ_FIFO_ADDR_reserved0_MASK 0xfffffff8
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_READ_FIFO_ADDR_reserved0_SHIFT 3
-
-/* DDR34_PHY_BYTE_LANE_0_1 :: READ_FIFO_ADDR :: ADDR [02:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_READ_FIFO_ADDR_ADDR_MASK 0x00000007
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_READ_FIFO_ADDR_ADDR_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_READ_FIFO_ADDR_ADDR_DEFAULT 0x00000000
-
-/***************************************************************************
- *READ_FIFO_DATA - Read fifo data register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_0_1 :: READ_FIFO_DATA :: DATA [31:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_READ_FIFO_DATA_DATA_MASK 0xffffffff
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_READ_FIFO_DATA_DATA_SHIFT 0
-
-/***************************************************************************
- *READ_FIFO_DM_DBI - Read fifo dm/dbi register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_0_1 :: READ_FIFO_DM_DBI :: reserved0 [31:04] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_READ_FIFO_DM_DBI_reserved0_MASK 0xfffffff0
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_READ_FIFO_DM_DBI_reserved0_SHIFT 4
-
-/* DDR34_PHY_BYTE_LANE_0_1 :: READ_FIFO_DM_DBI :: DM_DBI [03:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_READ_FIFO_DM_DBI_DM_DBI_MASK 0x0000000f
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_READ_FIFO_DM_DBI_DM_DBI_SHIFT 0
-
-/***************************************************************************
- *READ_FIFO_STATUS - Read fifo status register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_0_1 :: READ_FIFO_STATUS :: reserved0 [31:02] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_READ_FIFO_STATUS_reserved0_MASK 0xfffffffc
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_READ_FIFO_STATUS_reserved0_SHIFT 2
-
-/* DDR34_PHY_BYTE_LANE_0_1 :: READ_FIFO_STATUS :: OVERFLOW [01:01] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_READ_FIFO_STATUS_OVERFLOW_MASK 0x00000002
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_READ_FIFO_STATUS_OVERFLOW_SHIFT 1
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_READ_FIFO_STATUS_OVERFLOW_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_1 :: READ_FIFO_STATUS :: UNDERFLOW [00:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_READ_FIFO_STATUS_UNDERFLOW_MASK 0x00000001
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_READ_FIFO_STATUS_UNDERFLOW_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_READ_FIFO_STATUS_UNDERFLOW_DEFAULT 0x00000000
-
-/***************************************************************************
- *READ_FIFO_CLEAR - Read fifo status clear register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_0_1 :: READ_FIFO_CLEAR :: reserved0 [31:01] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_READ_FIFO_CLEAR_reserved0_MASK 0xfffffffe
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_READ_FIFO_CLEAR_reserved0_SHIFT 1
-
-/* DDR34_PHY_BYTE_LANE_0_1 :: READ_FIFO_CLEAR :: CLEAR [00:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_READ_FIFO_CLEAR_CLEAR_MASK 0x00000001
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_READ_FIFO_CLEAR_CLEAR_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_READ_FIFO_CLEAR_CLEAR_DEFAULT 0x00000000
-
-/***************************************************************************
- *IDLE_PAD_CONTROL - Idle mode SSTL pad control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_0_1 :: IDLE_PAD_CONTROL :: IDLE [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_IDLE_PAD_CONTROL_IDLE_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_IDLE_PAD_CONTROL_IDLE_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_IDLE_PAD_CONTROL_IDLE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_1 :: IDLE_PAD_CONTROL :: reserved0 [30:20] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_IDLE_PAD_CONTROL_reserved0_MASK 0x7ff00000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_IDLE_PAD_CONTROL_reserved0_SHIFT 20
-
-/* DDR34_PHY_BYTE_LANE_0_1 :: IDLE_PAD_CONTROL :: AUTO_DQ_RXENB_MODE [19:18] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_IDLE_PAD_CONTROL_AUTO_DQ_RXENB_MODE_MASK 0x000c0000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_IDLE_PAD_CONTROL_AUTO_DQ_RXENB_MODE_SHIFT 18
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_IDLE_PAD_CONTROL_AUTO_DQ_RXENB_MODE_DEFAULT 0x00000001
-
-/* DDR34_PHY_BYTE_LANE_0_1 :: IDLE_PAD_CONTROL :: AUTO_DQ_IDDQ_MODE [17:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_IDLE_PAD_CONTROL_AUTO_DQ_IDDQ_MODE_MASK 0x00030000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_IDLE_PAD_CONTROL_AUTO_DQ_IDDQ_MODE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_IDLE_PAD_CONTROL_AUTO_DQ_IDDQ_MODE_DEFAULT 0x00000001
-
-/* DDR34_PHY_BYTE_LANE_0_1 :: IDLE_PAD_CONTROL :: reserved_for_padding1 [15:15] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_IDLE_PAD_CONTROL_reserved_for_padding1_MASK 0x00008000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_IDLE_PAD_CONTROL_reserved_for_padding1_SHIFT 15
-
-/* DDR34_PHY_BYTE_LANE_0_1 :: IDLE_PAD_CONTROL :: IO_IDLE_ENABLE [14:04] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_IDLE_PAD_CONTROL_IO_IDLE_ENABLE_MASK 0x00007ff0
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_IDLE_PAD_CONTROL_IO_IDLE_ENABLE_SHIFT 4
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_IDLE_PAD_CONTROL_IO_IDLE_ENABLE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_1 :: IDLE_PAD_CONTROL :: RXENB [03:03] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_IDLE_PAD_CONTROL_RXENB_MASK 0x00000008
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_IDLE_PAD_CONTROL_RXENB_SHIFT 3
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_IDLE_PAD_CONTROL_RXENB_DEFAULT 0x00000001
-
-/* DDR34_PHY_BYTE_LANE_0_1 :: IDLE_PAD_CONTROL :: IDDQ [02:02] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_IDLE_PAD_CONTROL_IDDQ_MASK 0x00000004
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_IDLE_PAD_CONTROL_IDDQ_SHIFT 2
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_IDLE_PAD_CONTROL_IDDQ_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_1 :: IDLE_PAD_CONTROL :: DOUT_N [01:01] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_IDLE_PAD_CONTROL_DOUT_N_MASK 0x00000002
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_IDLE_PAD_CONTROL_DOUT_N_SHIFT 1
-
-/* DDR34_PHY_BYTE_LANE_0_1 :: IDLE_PAD_CONTROL :: DOUT_P [00:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_IDLE_PAD_CONTROL_DOUT_P_MASK 0x00000001
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_IDLE_PAD_CONTROL_DOUT_P_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_IDLE_PAD_CONTROL_DOUT_P_DEFAULT 0x00000000
-
-/***************************************************************************
- *DRIVE_PAD_CTL - SSTL pad drive characteristics control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_0_1 :: DRIVE_PAD_CTL :: reserved0 [31:30] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_DRIVE_PAD_CTL_reserved0_MASK 0xc0000000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_DRIVE_PAD_CTL_reserved0_SHIFT 30
-
-/* DDR34_PHY_BYTE_LANE_0_1 :: DRIVE_PAD_CTL :: BL_PD_IDLE_STRENGTH [29:25] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_DRIVE_PAD_CTL_BL_PD_IDLE_STRENGTH_MASK 0x3e000000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_DRIVE_PAD_CTL_BL_PD_IDLE_STRENGTH_SHIFT 25
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_DRIVE_PAD_CTL_BL_PD_IDLE_STRENGTH_DEFAULT 0x0000001f
-
-/* DDR34_PHY_BYTE_LANE_0_1 :: DRIVE_PAD_CTL :: BL_ND_IDLE_STRENGTH [24:20] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_DRIVE_PAD_CTL_BL_ND_IDLE_STRENGTH_MASK 0x01f00000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_DRIVE_PAD_CTL_BL_ND_IDLE_STRENGTH_SHIFT 20
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_DRIVE_PAD_CTL_BL_ND_IDLE_STRENGTH_DEFAULT 0x0000001f
-
-/* DDR34_PHY_BYTE_LANE_0_1 :: DRIVE_PAD_CTL :: BL_PD_TERM_STRENGTH [19:15] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_DRIVE_PAD_CTL_BL_PD_TERM_STRENGTH_MASK 0x000f8000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_DRIVE_PAD_CTL_BL_PD_TERM_STRENGTH_SHIFT 15
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_DRIVE_PAD_CTL_BL_PD_TERM_STRENGTH_DEFAULT 0x00000008
-
-/* DDR34_PHY_BYTE_LANE_0_1 :: DRIVE_PAD_CTL :: BL_ND_TERM_STRENGTH [14:10] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_DRIVE_PAD_CTL_BL_ND_TERM_STRENGTH_MASK 0x00007c00
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_DRIVE_PAD_CTL_BL_ND_TERM_STRENGTH_SHIFT 10
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_DRIVE_PAD_CTL_BL_ND_TERM_STRENGTH_DEFAULT 0x00000008
-
-/* DDR34_PHY_BYTE_LANE_0_1 :: DRIVE_PAD_CTL :: BL_PD_STRENGTH [09:05] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_DRIVE_PAD_CTL_BL_PD_STRENGTH_MASK 0x000003e0
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_DRIVE_PAD_CTL_BL_PD_STRENGTH_SHIFT 5
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_DRIVE_PAD_CTL_BL_PD_STRENGTH_DEFAULT 0x0000001f
-
-/* DDR34_PHY_BYTE_LANE_0_1 :: DRIVE_PAD_CTL :: BL_ND_STRENGTH [04:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_DRIVE_PAD_CTL_BL_ND_STRENGTH_MASK 0x0000001f
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_DRIVE_PAD_CTL_BL_ND_STRENGTH_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_DRIVE_PAD_CTL_BL_ND_STRENGTH_DEFAULT 0x0000001f
-
-/***************************************************************************
- *RD_EN_DRIVE_PAD_CTL - SSTL read enable pad drive characteristics control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_0_1 :: RD_EN_DRIVE_PAD_CTL :: reserved0 [31:20] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_RD_EN_DRIVE_PAD_CTL_reserved0_MASK 0xfff00000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_RD_EN_DRIVE_PAD_CTL_reserved0_SHIFT 20
-
-/* DDR34_PHY_BYTE_LANE_0_1 :: RD_EN_DRIVE_PAD_CTL :: EDC_RD_EN_PD_STRENGTH [19:15] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_RD_EN_DRIVE_PAD_CTL_EDC_RD_EN_PD_STRENGTH_MASK 0x000f8000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_RD_EN_DRIVE_PAD_CTL_EDC_RD_EN_PD_STRENGTH_SHIFT 15
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_RD_EN_DRIVE_PAD_CTL_EDC_RD_EN_PD_STRENGTH_DEFAULT 0x0000001f
-
-/* DDR34_PHY_BYTE_LANE_0_1 :: RD_EN_DRIVE_PAD_CTL :: EDC_RD_EN_ND_STRENGTH [14:10] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_RD_EN_DRIVE_PAD_CTL_EDC_RD_EN_ND_STRENGTH_MASK 0x00007c00
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_RD_EN_DRIVE_PAD_CTL_EDC_RD_EN_ND_STRENGTH_SHIFT 10
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_RD_EN_DRIVE_PAD_CTL_EDC_RD_EN_ND_STRENGTH_DEFAULT 0x0000001f
-
-/* DDR34_PHY_BYTE_LANE_0_1 :: RD_EN_DRIVE_PAD_CTL :: BL_RD_EN_PD_STRENGTH [09:05] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_RD_EN_DRIVE_PAD_CTL_BL_RD_EN_PD_STRENGTH_MASK 0x000003e0
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_RD_EN_DRIVE_PAD_CTL_BL_RD_EN_PD_STRENGTH_SHIFT 5
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_RD_EN_DRIVE_PAD_CTL_BL_RD_EN_PD_STRENGTH_DEFAULT 0x0000001f
-
-/* DDR34_PHY_BYTE_LANE_0_1 :: RD_EN_DRIVE_PAD_CTL :: BL_RD_EN_ND_STRENGTH [04:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_RD_EN_DRIVE_PAD_CTL_BL_RD_EN_ND_STRENGTH_MASK 0x0000001f
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_RD_EN_DRIVE_PAD_CTL_BL_RD_EN_ND_STRENGTH_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_RD_EN_DRIVE_PAD_CTL_BL_RD_EN_ND_STRENGTH_DEFAULT 0x0000001f
-
-/***************************************************************************
- *STATIC_PAD_CTL - pad rx and tx characteristics control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_0_1 :: STATIC_PAD_CTL :: reserved0 [31:21] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_STATIC_PAD_CTL_reserved0_MASK 0xffe00000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_STATIC_PAD_CTL_reserved0_SHIFT 21
-
-/* DDR34_PHY_BYTE_LANE_0_1 :: STATIC_PAD_CTL :: DQS_MODE [20:20] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_STATIC_PAD_CTL_DQS_MODE_MASK 0x00100000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_STATIC_PAD_CTL_DQS_MODE_SHIFT 20
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_STATIC_PAD_CTL_DQS_MODE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_1 :: STATIC_PAD_CTL :: reserved1 [19:18] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_STATIC_PAD_CTL_reserved1_MASK 0x000c0000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_STATIC_PAD_CTL_reserved1_SHIFT 18
-
-/* DDR34_PHY_BYTE_LANE_0_1 :: STATIC_PAD_CTL :: EDC_MODE [17:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_STATIC_PAD_CTL_EDC_MODE_MASK 0x00030000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_STATIC_PAD_CTL_EDC_MODE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_STATIC_PAD_CTL_EDC_MODE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_1 :: STATIC_PAD_CTL :: reserved2 [15:15] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_STATIC_PAD_CTL_reserved2_MASK 0x00008000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_STATIC_PAD_CTL_reserved2_SHIFT 15
-
-/* DDR34_PHY_BYTE_LANE_0_1 :: STATIC_PAD_CTL :: WDBI_ENABLE [14:14] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_STATIC_PAD_CTL_WDBI_ENABLE_MASK 0x00004000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_STATIC_PAD_CTL_WDBI_ENABLE_SHIFT 14
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_STATIC_PAD_CTL_WDBI_ENABLE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_1 :: STATIC_PAD_CTL :: RDBI_ENABLE [13:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_STATIC_PAD_CTL_RDBI_ENABLE_MASK 0x00002000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_STATIC_PAD_CTL_RDBI_ENABLE_SHIFT 13
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_STATIC_PAD_CTL_RDBI_ENABLE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_1 :: STATIC_PAD_CTL :: DM_MODE [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_STATIC_PAD_CTL_DM_MODE_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_STATIC_PAD_CTL_DM_MODE_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_STATIC_PAD_CTL_DM_MODE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_1 :: STATIC_PAD_CTL :: reserved3 [11:11] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_STATIC_PAD_CTL_reserved3_MASK 0x00000800
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_STATIC_PAD_CTL_reserved3_SHIFT 11
-
-/* DDR34_PHY_BYTE_LANE_0_1 :: STATIC_PAD_CTL :: DQS_TX_PAUSE [10:10] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_STATIC_PAD_CTL_DQS_TX_PAUSE_MASK 0x00000400
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_STATIC_PAD_CTL_DQS_TX_PAUSE_SHIFT 10
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_STATIC_PAD_CTL_DQS_TX_PAUSE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_1 :: STATIC_PAD_CTL :: DQS_TX_DIS [09:09] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_STATIC_PAD_CTL_DQS_TX_DIS_MASK 0x00000200
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_STATIC_PAD_CTL_DQS_TX_DIS_SHIFT 9
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_STATIC_PAD_CTL_DQS_TX_DIS_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_1 :: STATIC_PAD_CTL :: reserved4 [08:08] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_STATIC_PAD_CTL_reserved4_MASK 0x00000100
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_STATIC_PAD_CTL_reserved4_SHIFT 8
-
-/* DDR34_PHY_BYTE_LANE_0_1 :: STATIC_PAD_CTL :: TX_MODE [07:04] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_STATIC_PAD_CTL_TX_MODE_MASK 0x000000f0
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_STATIC_PAD_CTL_TX_MODE_SHIFT 4
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_STATIC_PAD_CTL_TX_MODE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_1 :: STATIC_PAD_CTL :: reserved5 [03:03] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_STATIC_PAD_CTL_reserved5_MASK 0x00000008
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_STATIC_PAD_CTL_reserved5_SHIFT 3
-
-/* DDR34_PHY_BYTE_LANE_0_1 :: STATIC_PAD_CTL :: RX_MODE [02:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_STATIC_PAD_CTL_RX_MODE_MASK 0x00000007
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_STATIC_PAD_CTL_RX_MODE_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_STATIC_PAD_CTL_RX_MODE_DEFAULT 0x00000000
-
-/***************************************************************************
- *WR_PREAMBLE_MODE - Write cycle preamble control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_0_1 :: WR_PREAMBLE_MODE :: reserved0 [31:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_WR_PREAMBLE_MODE_reserved0_MASK 0xffff0000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_WR_PREAMBLE_MODE_reserved0_SHIFT 16
-
-/* DDR34_PHY_BYTE_LANE_0_1 :: WR_PREAMBLE_MODE :: DQ_POSTAM_BITS [15:14] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_WR_PREAMBLE_MODE_DQ_POSTAM_BITS_MASK 0x0000c000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_WR_PREAMBLE_MODE_DQ_POSTAM_BITS_SHIFT 14
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_WR_PREAMBLE_MODE_DQ_POSTAM_BITS_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_1 :: WR_PREAMBLE_MODE :: DQ_PREAM_BITS [13:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_WR_PREAMBLE_MODE_DQ_PREAM_BITS_MASK 0x00003000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_WR_PREAMBLE_MODE_DQ_PREAM_BITS_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_WR_PREAMBLE_MODE_DQ_PREAM_BITS_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_1 :: WR_PREAMBLE_MODE :: DQS [11:08] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_WR_PREAMBLE_MODE_DQS_MASK 0x00000f00
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_WR_PREAMBLE_MODE_DQS_SHIFT 8
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_WR_PREAMBLE_MODE_DQS_DEFAULT 0x0000000e
-
-/* DDR34_PHY_BYTE_LANE_0_1 :: WR_PREAMBLE_MODE :: reserved1 [07:05] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_WR_PREAMBLE_MODE_reserved1_MASK 0x000000e0
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_WR_PREAMBLE_MODE_reserved1_SHIFT 5
-
-/* DDR34_PHY_BYTE_LANE_0_1 :: WR_PREAMBLE_MODE :: DQS_POSTAM_BITS [04:03] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_WR_PREAMBLE_MODE_DQS_POSTAM_BITS_MASK 0x00000018
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_WR_PREAMBLE_MODE_DQS_POSTAM_BITS_SHIFT 3
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_WR_PREAMBLE_MODE_DQS_POSTAM_BITS_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_1 :: WR_PREAMBLE_MODE :: DQS_PREAM_BITS [02:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_WR_PREAMBLE_MODE_DQS_PREAM_BITS_MASK 0x00000007
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_WR_PREAMBLE_MODE_DQS_PREAM_BITS_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_WR_PREAMBLE_MODE_DQS_PREAM_BITS_DEFAULT 0x00000002
-
-/***************************************************************************
- *ODT_CONTROL - Read channel ODT control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_0_1 :: ODT_CONTROL :: reserved_for_padding0 [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_ODT_CONTROL_reserved_for_padding0_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_ODT_CONTROL_reserved_for_padding0_SHIFT 31
-
-/* DDR34_PHY_BYTE_LANE_0_1 :: ODT_CONTROL :: reserved1 [30:10] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_ODT_CONTROL_reserved1_MASK 0x7ffffc00
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_ODT_CONTROL_reserved1_SHIFT 10
-
-/* DDR34_PHY_BYTE_LANE_0_1 :: ODT_CONTROL :: ODT_ENABLE [09:09] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_ODT_CONTROL_ODT_ENABLE_MASK 0x00000200
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_ODT_CONTROL_ODT_ENABLE_SHIFT 9
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_ODT_CONTROL_ODT_ENABLE_DEFAULT 0x00000001
-
-/* DDR34_PHY_BYTE_LANE_0_1 :: ODT_CONTROL :: ODT_DELAY [08:06] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_ODT_CONTROL_ODT_DELAY_MASK 0x000001c0
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_ODT_CONTROL_ODT_DELAY_SHIFT 6
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_ODT_CONTROL_ODT_DELAY_DEFAULT 0x00000001
-
-/* DDR34_PHY_BYTE_LANE_0_1 :: ODT_CONTROL :: ODT_POST_LENGTH [05:03] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_ODT_CONTROL_ODT_POST_LENGTH_MASK 0x00000038
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_ODT_CONTROL_ODT_POST_LENGTH_SHIFT 3
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_ODT_CONTROL_ODT_POST_LENGTH_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_1 :: ODT_CONTROL :: ODT_PRE_LENGTH [02:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_ODT_CONTROL_ODT_PRE_LENGTH_MASK 0x00000007
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_ODT_CONTROL_ODT_PRE_LENGTH_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_ODT_CONTROL_ODT_PRE_LENGTH_DEFAULT 0x00000003
-
-/***************************************************************************
- *EDC_DPD_CONTROL - GDDR5M EDC digital phase detector control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_0_1 :: EDC_DPD_CONTROL :: reserved0 [31:06] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_EDC_DPD_CONTROL_reserved0_MASK 0xffffffc0
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_EDC_DPD_CONTROL_reserved0_SHIFT 6
-
-/* DDR34_PHY_BYTE_LANE_0_1 :: EDC_DPD_CONTROL :: DQS_PHASE_OVERRIDE_VALUE [05:05] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_EDC_DPD_CONTROL_DQS_PHASE_OVERRIDE_VALUE_MASK 0x00000020
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_EDC_DPD_CONTROL_DQS_PHASE_OVERRIDE_VALUE_SHIFT 5
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_EDC_DPD_CONTROL_DQS_PHASE_OVERRIDE_VALUE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_1 :: EDC_DPD_CONTROL :: DQS_PHASE_OVERRIDE_ENABLE [04:04] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_EDC_DPD_CONTROL_DQS_PHASE_OVERRIDE_ENABLE_MASK 0x00000010
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_EDC_DPD_CONTROL_DQS_PHASE_OVERRIDE_ENABLE_SHIFT 4
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_EDC_DPD_CONTROL_DQS_PHASE_OVERRIDE_ENABLE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_1 :: EDC_DPD_CONTROL :: SET_ADJ_EN [03:03] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_EDC_DPD_CONTROL_SET_ADJ_EN_MASK 0x00000008
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_EDC_DPD_CONTROL_SET_ADJ_EN_SHIFT 3
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_EDC_DPD_CONTROL_SET_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_1 :: EDC_DPD_CONTROL :: UPDATE [02:02] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_EDC_DPD_CONTROL_UPDATE_MASK 0x00000004
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_EDC_DPD_CONTROL_UPDATE_SHIFT 2
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_EDC_DPD_CONTROL_UPDATE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_1 :: EDC_DPD_CONTROL :: MONITOR [01:01] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_EDC_DPD_CONTROL_MONITOR_MASK 0x00000002
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_EDC_DPD_CONTROL_MONITOR_SHIFT 1
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_EDC_DPD_CONTROL_MONITOR_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_1 :: EDC_DPD_CONTROL :: INIT [00:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_EDC_DPD_CONTROL_INIT_MASK 0x00000001
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_EDC_DPD_CONTROL_INIT_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_EDC_DPD_CONTROL_INIT_DEFAULT 0x00000000
-
-/***************************************************************************
- *EDC_DPD_STATUS - GDDR5M EDC digital phase detector status register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_0_1 :: EDC_DPD_STATUS :: reserved0 [31:25] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_EDC_DPD_STATUS_reserved0_MASK 0xfe000000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_EDC_DPD_STATUS_reserved0_SHIFT 25
-
-/* DDR34_PHY_BYTE_LANE_0_1 :: EDC_DPD_STATUS :: CURRENT_DQS_PHASE [24:24] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_EDC_DPD_STATUS_CURRENT_DQS_PHASE_MASK 0x01000000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_EDC_DPD_STATUS_CURRENT_DQS_PHASE_SHIFT 24
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_EDC_DPD_STATUS_CURRENT_DQS_PHASE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_1 :: EDC_DPD_STATUS :: CURRENT_VDL_SETTING [23:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_EDC_DPD_STATUS_CURRENT_VDL_SETTING_MASK 0x00ff0000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_EDC_DPD_STATUS_CURRENT_VDL_SETTING_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_EDC_DPD_STATUS_CURRENT_VDL_SETTING_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_1 :: EDC_DPD_STATUS :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_EDC_DPD_STATUS_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_EDC_DPD_STATUS_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_0_1 :: EDC_DPD_STATUS :: INIT_DQS_PHASE [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_EDC_DPD_STATUS_INIT_DQS_PHASE_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_EDC_DPD_STATUS_INIT_DQS_PHASE_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_EDC_DPD_STATUS_INIT_DQS_PHASE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_1 :: EDC_DPD_STATUS :: INIT_VDL_SETTING [11:04] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_EDC_DPD_STATUS_INIT_VDL_SETTING_MASK 0x00000ff0
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_EDC_DPD_STATUS_INIT_VDL_SETTING_SHIFT 4
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_EDC_DPD_STATUS_INIT_VDL_SETTING_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_1 :: EDC_DPD_STATUS :: EDGE_ERROR [03:03] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_EDC_DPD_STATUS_EDGE_ERROR_MASK 0x00000008
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_EDC_DPD_STATUS_EDGE_ERROR_SHIFT 3
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_EDC_DPD_STATUS_EDGE_ERROR_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_1 :: EDC_DPD_STATUS :: MONITOR_BUSY [02:02] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_EDC_DPD_STATUS_MONITOR_BUSY_MASK 0x00000004
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_EDC_DPD_STATUS_MONITOR_BUSY_SHIFT 2
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_EDC_DPD_STATUS_MONITOR_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_1 :: EDC_DPD_STATUS :: INIT_BUSY [01:01] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_EDC_DPD_STATUS_INIT_BUSY_MASK 0x00000002
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_EDC_DPD_STATUS_INIT_BUSY_SHIFT 1
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_EDC_DPD_STATUS_INIT_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_1 :: EDC_DPD_STATUS :: INIT_DONE [00:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_EDC_DPD_STATUS_INIT_DONE_MASK 0x00000001
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_EDC_DPD_STATUS_INIT_DONE_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_EDC_DPD_STATUS_INIT_DONE_DEFAULT 0x00000000
-
-/***************************************************************************
- *EDC_DPD_OUT_CONTROL - GDDR5M EDC digital phase detector output signal control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_0_1 :: EDC_DPD_OUT_CONTROL :: reserved0 [31:20] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_EDC_DPD_OUT_CONTROL_reserved0_MASK 0xfff00000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_EDC_DPD_OUT_CONTROL_reserved0_SHIFT 20
-
-/* DDR34_PHY_BYTE_LANE_0_1 :: EDC_DPD_OUT_CONTROL :: LOWER_LIMIT [19:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_EDC_DPD_OUT_CONTROL_LOWER_LIMIT_MASK 0x000ff000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_EDC_DPD_OUT_CONTROL_LOWER_LIMIT_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_EDC_DPD_OUT_CONTROL_LOWER_LIMIT_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_1 :: EDC_DPD_OUT_CONTROL :: UPPER_LIMIT [11:04] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_EDC_DPD_OUT_CONTROL_UPPER_LIMIT_MASK 0x00000ff0
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_EDC_DPD_OUT_CONTROL_UPPER_LIMIT_SHIFT 4
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_EDC_DPD_OUT_CONTROL_UPPER_LIMIT_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_1 :: EDC_DPD_OUT_CONTROL :: reserved1 [03:01] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_EDC_DPD_OUT_CONTROL_reserved1_MASK 0x0000000e
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_EDC_DPD_OUT_CONTROL_reserved1_SHIFT 1
-
-/* DDR34_PHY_BYTE_LANE_0_1 :: EDC_DPD_OUT_CONTROL :: ENABLE [00:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_EDC_DPD_OUT_CONTROL_ENABLE_MASK 0x00000001
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_EDC_DPD_OUT_CONTROL_ENABLE_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_EDC_DPD_OUT_CONTROL_ENABLE_DEFAULT 0x00000000
-
-/***************************************************************************
- *EDC_DPD_OUT_STATUS - GDDR5M EDC digital phase detector output signal status register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_0_1 :: EDC_DPD_OUT_STATUS :: reserved0 [31:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_EDC_DPD_OUT_STATUS_reserved0_MASK 0xfffff000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_EDC_DPD_OUT_STATUS_reserved0_SHIFT 12
-
-/* DDR34_PHY_BYTE_LANE_0_1 :: EDC_DPD_OUT_STATUS :: VDL_SETTING [11:04] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_EDC_DPD_OUT_STATUS_VDL_SETTING_MASK 0x00000ff0
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_EDC_DPD_OUT_STATUS_VDL_SETTING_SHIFT 4
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_EDC_DPD_OUT_STATUS_VDL_SETTING_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_1 :: EDC_DPD_OUT_STATUS :: reserved1 [03:01] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_EDC_DPD_OUT_STATUS_reserved1_MASK 0x0000000e
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_EDC_DPD_OUT_STATUS_reserved1_SHIFT 1
-
-/* DDR34_PHY_BYTE_LANE_0_1 :: EDC_DPD_OUT_STATUS :: VALID [00:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_EDC_DPD_OUT_STATUS_VALID_MASK 0x00000001
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_EDC_DPD_OUT_STATUS_VALID_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_EDC_DPD_OUT_STATUS_VALID_DEFAULT 0x00000000
-
-/***************************************************************************
- *EDC_DPD_OUT_STATUS_CLEAR - GDDR5M EDC digital phase detector output signal status clear register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_0_1 :: EDC_DPD_OUT_STATUS_CLEAR :: reserved0 [31:01] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_EDC_DPD_OUT_STATUS_CLEAR_reserved0_MASK 0xfffffffe
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_EDC_DPD_OUT_STATUS_CLEAR_reserved0_SHIFT 1
-
-/* DDR34_PHY_BYTE_LANE_0_1 :: EDC_DPD_OUT_STATUS_CLEAR :: CLEAR [00:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_EDC_DPD_OUT_STATUS_CLEAR_CLEAR_MASK 0x00000001
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_EDC_DPD_OUT_STATUS_CLEAR_CLEAR_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_EDC_DPD_OUT_STATUS_CLEAR_CLEAR_DEFAULT 0x00000000
-
-/***************************************************************************
- *EDC_CRC_CONTROL - GDDR5M EDC signal path CRC control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_0_1 :: EDC_CRC_CONTROL :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_EDC_CRC_CONTROL_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_EDC_CRC_CONTROL_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_EDC_CRC_CONTROL_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_1 :: EDC_CRC_CONTROL :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_EDC_CRC_CONTROL_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_EDC_CRC_CONTROL_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_0_1 :: EDC_CRC_CONTROL :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_EDC_CRC_CONTROL_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_EDC_CRC_CONTROL_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_EDC_CRC_CONTROL_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_1 :: EDC_CRC_CONTROL :: reserved1 [15:11] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_EDC_CRC_CONTROL_reserved1_MASK 0x0000f800
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_EDC_CRC_CONTROL_reserved1_SHIFT 11
-
-/* DDR34_PHY_BYTE_LANE_0_1 :: EDC_CRC_CONTROL :: CRCWL [10:08] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_EDC_CRC_CONTROL_CRCWL_MASK 0x00000700
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_EDC_CRC_CONTROL_CRCWL_SHIFT 8
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_EDC_CRC_CONTROL_CRCWL_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_1 :: EDC_CRC_CONTROL :: reserved2 [07:06] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_EDC_CRC_CONTROL_reserved2_MASK 0x000000c0
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_EDC_CRC_CONTROL_reserved2_SHIFT 6
-
-/* DDR34_PHY_BYTE_LANE_0_1 :: EDC_CRC_CONTROL :: CRCRL [05:04] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_EDC_CRC_CONTROL_CRCRL_MASK 0x00000030
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_EDC_CRC_CONTROL_CRCRL_SHIFT 4
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_EDC_CRC_CONTROL_CRCRL_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_1 :: EDC_CRC_CONTROL :: reserved3 [03:03] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_EDC_CRC_CONTROL_reserved3_MASK 0x00000008
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_EDC_CRC_CONTROL_reserved3_SHIFT 3
-
-/* DDR34_PHY_BYTE_LANE_0_1 :: EDC_CRC_CONTROL :: COUNT_MODE [02:02] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_EDC_CRC_CONTROL_COUNT_MODE_MASK 0x00000004
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_EDC_CRC_CONTROL_COUNT_MODE_SHIFT 2
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_EDC_CRC_CONTROL_COUNT_MODE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_1 :: EDC_CRC_CONTROL :: ENABLE_WR [01:01] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_EDC_CRC_CONTROL_ENABLE_WR_MASK 0x00000002
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_EDC_CRC_CONTROL_ENABLE_WR_SHIFT 1
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_EDC_CRC_CONTROL_ENABLE_WR_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_1 :: EDC_CRC_CONTROL :: ENABLE_RD [00:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_EDC_CRC_CONTROL_ENABLE_RD_MASK 0x00000001
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_EDC_CRC_CONTROL_ENABLE_RD_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_EDC_CRC_CONTROL_ENABLE_RD_DEFAULT 0x00000000
-
-/***************************************************************************
- *EDC_CRC_STATUS - GDDR5M EDC signal path CRC status register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_0_1 :: EDC_CRC_STATUS :: reserved0 [31:04] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_EDC_CRC_STATUS_reserved0_MASK 0xfffffff0
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_EDC_CRC_STATUS_reserved0_SHIFT 4
-
-/* DDR34_PHY_BYTE_LANE_0_1 :: EDC_CRC_STATUS :: WR_FAIL [03:03] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_EDC_CRC_STATUS_WR_FAIL_MASK 0x00000008
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_EDC_CRC_STATUS_WR_FAIL_SHIFT 3
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_EDC_CRC_STATUS_WR_FAIL_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_1 :: EDC_CRC_STATUS :: WR_PASS [02:02] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_EDC_CRC_STATUS_WR_PASS_MASK 0x00000004
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_EDC_CRC_STATUS_WR_PASS_SHIFT 2
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_EDC_CRC_STATUS_WR_PASS_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_1 :: EDC_CRC_STATUS :: RD_FAIL [01:01] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_EDC_CRC_STATUS_RD_FAIL_MASK 0x00000002
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_EDC_CRC_STATUS_RD_FAIL_SHIFT 1
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_EDC_CRC_STATUS_RD_FAIL_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_1 :: EDC_CRC_STATUS :: RD_PASS [00:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_EDC_CRC_STATUS_RD_PASS_MASK 0x00000001
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_EDC_CRC_STATUS_RD_PASS_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_EDC_CRC_STATUS_RD_PASS_DEFAULT 0x00000000
-
-/***************************************************************************
- *EDC_CRC_COUNT - GDDR5M EDC signal path CRC counter register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_0_1 :: EDC_CRC_COUNT :: reserved0 [31:28] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_EDC_CRC_COUNT_reserved0_MASK 0xf0000000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_EDC_CRC_COUNT_reserved0_SHIFT 28
-
-/* DDR34_PHY_BYTE_LANE_0_1 :: EDC_CRC_COUNT :: WR_COUNT [27:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_EDC_CRC_COUNT_WR_COUNT_MASK 0x0fff0000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_EDC_CRC_COUNT_WR_COUNT_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_EDC_CRC_COUNT_WR_COUNT_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_1 :: EDC_CRC_COUNT :: reserved1 [15:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_EDC_CRC_COUNT_reserved1_MASK 0x0000f000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_EDC_CRC_COUNT_reserved1_SHIFT 12
-
-/* DDR34_PHY_BYTE_LANE_0_1 :: EDC_CRC_COUNT :: RD_COUNT [11:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_EDC_CRC_COUNT_RD_COUNT_MASK 0x00000fff
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_EDC_CRC_COUNT_RD_COUNT_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_EDC_CRC_COUNT_RD_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *EDC_CRC_STATUS_CLEAR - GDDR5M EDC signal path CRC counter register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_0_1 :: EDC_CRC_STATUS_CLEAR :: reserved0 [31:01] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_EDC_CRC_STATUS_CLEAR_reserved0_MASK 0xfffffffe
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_EDC_CRC_STATUS_CLEAR_reserved0_SHIFT 1
-
-/* DDR34_PHY_BYTE_LANE_0_1 :: EDC_CRC_STATUS_CLEAR :: CLEAR [00:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_EDC_CRC_STATUS_CLEAR_CLEAR_MASK 0x00000001
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_EDC_CRC_STATUS_CLEAR_CLEAR_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_EDC_CRC_STATUS_CLEAR_CLEAR_DEFAULT 0x00000000
-
-/***************************************************************************
- *BL_SPARE_REG - Byte-Lane Spare register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_0_1 :: BL_SPARE_REG :: reserved_for_eco0 [31:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_BL_SPARE_REG_reserved_for_eco0_MASK 0xffffffff
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_BL_SPARE_REG_reserved_for_eco0_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_BL_SPARE_REG_reserved_for_eco0_DEFAULT 0x00000000
-
-#endif /* #ifndef BCHP_DDR34_PHY_BYTE_LANE_0_1_H__ */
-
-/* End of File */
diff --git a/include/linux/brcmstb/7145a0/bchp_ddr34_phy_byte_lane_1_0.h b/include/linux/brcmstb/7145a0/bchp_ddr34_phy_byte_lane_1_0.h
deleted file mode 100644
index aba23fa..0000000
--- a/include/linux/brcmstb/7145a0/bchp_ddr34_phy_byte_lane_1_0.h
+++ /dev/null
@@ -1,2101 +0,0 @@
-/***************************************************************************
- * Copyright (c) 1999-2014, Broadcom Corporation
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
- *
- * Module Description:
- * DO NOT EDIT THIS FILE DIRECTLY
- *
- * This module was generated magically with RDB from a source description
- * file. You must edit the source file for changes to be made to this file.
- *
- *
- * Date: Generated on Wed Sep 3 13:17:35 2014
- * Full Compile MD5 Checksum a8ee62ccf9dde43435c825f266da463d
- * (minus title and desc)
- * MD5 Checksum e373b364a1742e13a0f9eb15fd8aa94f
- *
- * Compiled with: RDB Utility combo_header.pl
- * RDB Parser 3.0
- * unknown unknown
- * Perl Interpreter 5.008005
- * Operating System linux
- *
- * Revision History:
- *
- * $brcm_Log: $
- *
- ***************************************************************************/
-
-#ifndef BCHP_DDR34_PHY_BYTE_LANE_1_0_H__
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_H__
-
-/***************************************************************************
- *DDR34_PHY_BYTE_LANE_1_0 - DDR34 Byte Lane #1 control registers
- ***************************************************************************/
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQS_P 0x203b6600 /* Write channel DQS-P VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQS_N 0x203b6604 /* Write channel DQS-N VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ0 0x203b6608 /* Write channel DQ0 VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ1 0x203b660c /* Write channel DQ1 VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ2 0x203b6610 /* Write channel DQ2 VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ3 0x203b6614 /* Write channel DQ3 VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ4 0x203b6618 /* Write channel DQ4 VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ5 0x203b661c /* Write channel DQ5 VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ6 0x203b6620 /* Write channel DQ6 VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ7 0x203b6624 /* Write channel DQ7 VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DM 0x203b6628 /* Write channel DM VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_EDC 0x203b662c /* Write channel EDC VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQSP 0x203b6630 /* Read channel DQSP VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQSN 0x203b6634 /* Read channel DQSP VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ0P 0x203b6638 /* Read channel DQ0-P VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ0N 0x203b663c /* Read channel DQ0-N VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ1P 0x203b6640 /* Read channel DQ1-P VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ1N 0x203b6644 /* Read channel DQ1-N VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ2P 0x203b6648 /* Read channel DQ2-P VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ2N 0x203b664c /* Read channel DQ2-N VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ3P 0x203b6650 /* Read channel DQ3-P VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ3N 0x203b6654 /* Read channel DQ3-N VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ4P 0x203b6658 /* Read channel DQ4-P VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ4N 0x203b665c /* Read channel DQ4-N VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ5P 0x203b6660 /* Read channel DQ5-P VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ5N 0x203b6664 /* Read channel DQ5-N VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ6P 0x203b6668 /* Read channel DQ6-P VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ6N 0x203b666c /* Read channel DQ6-N VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ7P 0x203b6670 /* Read channel DQ7-P VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ7N 0x203b6674 /* Read channel DQ7-N VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DMP 0x203b6678 /* Read channel DM-P VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DMN 0x203b667c /* Read channel DM-N VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_EDCP 0x203b6680 /* Read channel EDC-P VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_EDCN 0x203b6684 /* Read channel EDC-N VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_EN_CS0 0x203b6688 /* Read channel CS_N[0] read enable VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_EN_CS1 0x203b668c /* Read channel CS_N[1] read enable VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CLK_CONTROL 0x203b6690 /* DDR interface signal Write Leveling CLK VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_LDE_CONTROL 0x203b6694 /* DDR interface signal Write Leveling Capture Enable VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_RD_EN_DLY_CYC 0x203b66a0 /* Read enable bit-clock cycle delay control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_WR_CHAN_DLY_CYC 0x203b66a4 /* Write leveling bit-clock cycle delay control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_READ_CONTROL 0x203b66b0 /* Read channel datapath control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_READ_FIFO_ADDR 0x203b66b4 /* Read fifo addresss pointer register */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_READ_FIFO_DATA 0x203b66b8 /* Read fifo data register */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_READ_FIFO_DM_DBI 0x203b66bc /* Read fifo dm/dbi register */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_READ_FIFO_STATUS 0x203b66c0 /* Read fifo status register */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_READ_FIFO_CLEAR 0x203b66c4 /* Read fifo status clear register */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_IDLE_PAD_CONTROL 0x203b66c8 /* Idle mode SSTL pad control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_DRIVE_PAD_CTL 0x203b66cc /* SSTL pad drive characteristics control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_RD_EN_DRIVE_PAD_CTL 0x203b66d0 /* SSTL read enable pad drive characteristics control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_STATIC_PAD_CTL 0x203b66d4 /* pad rx and tx characteristics control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_WR_PREAMBLE_MODE 0x203b66d8 /* Write cycle preamble control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_ODT_CONTROL 0x203b66e0 /* Read channel ODT control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_DPD_CONTROL 0x203b66f0 /* GDDR5M EDC digital phase detector control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_DPD_STATUS 0x203b66f4 /* GDDR5M EDC digital phase detector status register */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_DPD_OUT_CONTROL 0x203b66f8 /* GDDR5M EDC digital phase detector output signal control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_DPD_OUT_STATUS 0x203b66fc /* GDDR5M EDC digital phase detector output signal status register */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_DPD_OUT_STATUS_CLEAR 0x203b6700 /* GDDR5M EDC digital phase detector output signal status clear register */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_CRC_CONTROL 0x203b6704 /* GDDR5M EDC signal path CRC control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_CRC_STATUS 0x203b6708 /* GDDR5M EDC signal path CRC status register */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_CRC_COUNT 0x203b670c /* GDDR5M EDC signal path CRC counter register */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_CRC_STATUS_CLEAR 0x203b6710 /* GDDR5M EDC signal path CRC counter register */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_BL_SPARE_REG 0x203b6714 /* Byte-Lane Spare register */
-
-/***************************************************************************
- *VDL_CONTROL_WR_DQS_P - Write channel DQS-P VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_WR_DQS_P :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQS_P_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQS_P_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQS_P_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_WR_DQS_P :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQS_P_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQS_P_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_WR_DQS_P :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQS_P_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQS_P_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQS_P_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_WR_DQS_P :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQS_P_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQS_P_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_WR_DQS_P :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQS_P_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQS_P_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQS_P_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_WR_DQS_P :: reserved2 [11:09] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQS_P_reserved2_MASK 0x00000e00
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQS_P_reserved2_SHIFT 9
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_WR_DQS_P :: VDL_STEP [08:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQS_P_VDL_STEP_MASK 0x000001ff
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQS_P_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQS_P_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_WR_DQS_N - Write channel DQS-N VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_WR_DQS_N :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQS_N_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQS_N_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQS_N_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_WR_DQS_N :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQS_N_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQS_N_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_WR_DQS_N :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQS_N_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQS_N_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQS_N_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_WR_DQS_N :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQS_N_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQS_N_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_WR_DQS_N :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQS_N_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQS_N_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQS_N_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_WR_DQS_N :: reserved2 [11:09] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQS_N_reserved2_MASK 0x00000e00
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQS_N_reserved2_SHIFT 9
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_WR_DQS_N :: VDL_STEP [08:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQS_N_VDL_STEP_MASK 0x000001ff
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQS_N_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQS_N_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_WR_DQ0 - Write channel DQ0 VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_WR_DQ0 :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ0_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ0_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ0_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_WR_DQ0 :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ0_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ0_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_WR_DQ0 :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ0_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ0_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ0_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_WR_DQ0 :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ0_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ0_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_WR_DQ0 :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ0_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ0_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ0_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_WR_DQ0 :: reserved2 [11:09] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ0_reserved2_MASK 0x00000e00
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ0_reserved2_SHIFT 9
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_WR_DQ0 :: VDL_STEP [08:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ0_VDL_STEP_MASK 0x000001ff
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ0_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ0_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_WR_DQ1 - Write channel DQ1 VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_WR_DQ1 :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ1_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ1_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ1_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_WR_DQ1 :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ1_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ1_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_WR_DQ1 :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ1_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ1_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ1_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_WR_DQ1 :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ1_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ1_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_WR_DQ1 :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ1_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ1_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ1_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_WR_DQ1 :: reserved2 [11:09] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ1_reserved2_MASK 0x00000e00
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ1_reserved2_SHIFT 9
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_WR_DQ1 :: VDL_STEP [08:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ1_VDL_STEP_MASK 0x000001ff
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ1_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ1_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_WR_DQ2 - Write channel DQ2 VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_WR_DQ2 :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ2_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ2_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ2_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_WR_DQ2 :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ2_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ2_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_WR_DQ2 :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ2_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ2_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ2_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_WR_DQ2 :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ2_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ2_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_WR_DQ2 :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ2_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ2_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ2_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_WR_DQ2 :: reserved2 [11:09] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ2_reserved2_MASK 0x00000e00
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ2_reserved2_SHIFT 9
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_WR_DQ2 :: VDL_STEP [08:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ2_VDL_STEP_MASK 0x000001ff
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ2_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ2_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_WR_DQ3 - Write channel DQ3 VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_WR_DQ3 :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ3_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ3_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ3_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_WR_DQ3 :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ3_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ3_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_WR_DQ3 :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ3_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ3_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ3_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_WR_DQ3 :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ3_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ3_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_WR_DQ3 :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ3_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ3_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ3_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_WR_DQ3 :: reserved2 [11:09] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ3_reserved2_MASK 0x00000e00
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ3_reserved2_SHIFT 9
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_WR_DQ3 :: VDL_STEP [08:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ3_VDL_STEP_MASK 0x000001ff
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ3_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ3_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_WR_DQ4 - Write channel DQ4 VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_WR_DQ4 :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ4_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ4_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ4_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_WR_DQ4 :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ4_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ4_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_WR_DQ4 :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ4_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ4_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ4_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_WR_DQ4 :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ4_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ4_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_WR_DQ4 :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ4_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ4_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ4_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_WR_DQ4 :: reserved2 [11:09] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ4_reserved2_MASK 0x00000e00
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ4_reserved2_SHIFT 9
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_WR_DQ4 :: VDL_STEP [08:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ4_VDL_STEP_MASK 0x000001ff
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ4_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ4_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_WR_DQ5 - Write channel DQ5 VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_WR_DQ5 :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ5_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ5_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ5_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_WR_DQ5 :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ5_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ5_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_WR_DQ5 :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ5_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ5_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ5_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_WR_DQ5 :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ5_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ5_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_WR_DQ5 :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ5_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ5_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ5_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_WR_DQ5 :: reserved2 [11:09] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ5_reserved2_MASK 0x00000e00
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ5_reserved2_SHIFT 9
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_WR_DQ5 :: VDL_STEP [08:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ5_VDL_STEP_MASK 0x000001ff
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ5_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ5_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_WR_DQ6 - Write channel DQ6 VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_WR_DQ6 :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ6_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ6_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ6_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_WR_DQ6 :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ6_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ6_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_WR_DQ6 :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ6_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ6_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ6_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_WR_DQ6 :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ6_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ6_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_WR_DQ6 :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ6_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ6_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ6_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_WR_DQ6 :: reserved2 [11:09] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ6_reserved2_MASK 0x00000e00
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ6_reserved2_SHIFT 9
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_WR_DQ6 :: VDL_STEP [08:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ6_VDL_STEP_MASK 0x000001ff
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ6_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ6_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_WR_DQ7 - Write channel DQ7 VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_WR_DQ7 :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ7_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ7_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ7_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_WR_DQ7 :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ7_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ7_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_WR_DQ7 :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ7_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ7_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ7_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_WR_DQ7 :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ7_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ7_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_WR_DQ7 :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ7_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ7_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ7_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_WR_DQ7 :: reserved2 [11:09] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ7_reserved2_MASK 0x00000e00
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ7_reserved2_SHIFT 9
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_WR_DQ7 :: VDL_STEP [08:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ7_VDL_STEP_MASK 0x000001ff
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ7_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ7_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_WR_DM - Write channel DM VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_WR_DM :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DM_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DM_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DM_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_WR_DM :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DM_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DM_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_WR_DM :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DM_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DM_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DM_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_WR_DM :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DM_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DM_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_WR_DM :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DM_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DM_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DM_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_WR_DM :: reserved2 [11:09] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DM_reserved2_MASK 0x00000e00
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DM_reserved2_SHIFT 9
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_WR_DM :: VDL_STEP [08:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DM_VDL_STEP_MASK 0x000001ff
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DM_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DM_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_WR_EDC - Write channel EDC VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_WR_EDC :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_EDC_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_EDC_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_EDC_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_WR_EDC :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_EDC_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_EDC_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_WR_EDC :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_EDC_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_EDC_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_EDC_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_WR_EDC :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_EDC_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_EDC_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_WR_EDC :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_EDC_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_EDC_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_EDC_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_WR_EDC :: reserved2 [11:09] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_EDC_reserved2_MASK 0x00000e00
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_EDC_reserved2_SHIFT 9
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_WR_EDC :: VDL_STEP [08:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_EDC_VDL_STEP_MASK 0x000001ff
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_EDC_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_EDC_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_RD_DQSP - Read channel DQSP VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_DQSP :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQSP_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQSP_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQSP_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_DQSP :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQSP_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQSP_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_DQSP :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQSP_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQSP_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQSP_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_DQSP :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQSP_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQSP_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_DQSP :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQSP_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQSP_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQSP_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_DQSP :: reserved2 [11:08] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQSP_reserved2_MASK 0x00000f00
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQSP_reserved2_SHIFT 8
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_DQSP :: VDL_STEP [07:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQSP_VDL_STEP_MASK 0x000000ff
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQSP_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQSP_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_RD_DQSN - Read channel DQSP VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_DQSN :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQSN_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQSN_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQSN_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_DQSN :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQSN_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQSN_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_DQSN :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQSN_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQSN_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQSN_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_DQSN :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQSN_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQSN_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_DQSN :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQSN_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQSN_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQSN_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_DQSN :: reserved2 [11:08] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQSN_reserved2_MASK 0x00000f00
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQSN_reserved2_SHIFT 8
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_DQSN :: VDL_STEP [07:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQSN_VDL_STEP_MASK 0x000000ff
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQSN_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQSN_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_RD_DQ0P - Read channel DQ0-P VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_DQ0P :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ0P_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ0P_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ0P_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_DQ0P :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ0P_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ0P_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_DQ0P :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ0P_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ0P_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ0P_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_DQ0P :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ0P_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ0P_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_DQ0P :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ0P_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ0P_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ0P_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_DQ0P :: reserved2 [11:08] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ0P_reserved2_MASK 0x00000f00
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ0P_reserved2_SHIFT 8
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_DQ0P :: VDL_STEP [07:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ0P_VDL_STEP_MASK 0x000000ff
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ0P_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ0P_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_RD_DQ0N - Read channel DQ0-N VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_DQ0N :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ0N_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ0N_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ0N_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_DQ0N :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ0N_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ0N_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_DQ0N :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ0N_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ0N_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ0N_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_DQ0N :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ0N_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ0N_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_DQ0N :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ0N_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ0N_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ0N_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_DQ0N :: reserved2 [11:08] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ0N_reserved2_MASK 0x00000f00
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ0N_reserved2_SHIFT 8
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_DQ0N :: VDL_STEP [07:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ0N_VDL_STEP_MASK 0x000000ff
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ0N_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ0N_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_RD_DQ1P - Read channel DQ1-P VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_DQ1P :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ1P_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ1P_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ1P_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_DQ1P :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ1P_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ1P_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_DQ1P :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ1P_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ1P_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ1P_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_DQ1P :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ1P_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ1P_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_DQ1P :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ1P_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ1P_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ1P_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_DQ1P :: reserved2 [11:08] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ1P_reserved2_MASK 0x00000f00
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ1P_reserved2_SHIFT 8
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_DQ1P :: VDL_STEP [07:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ1P_VDL_STEP_MASK 0x000000ff
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ1P_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ1P_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_RD_DQ1N - Read channel DQ1-N VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_DQ1N :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ1N_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ1N_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ1N_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_DQ1N :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ1N_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ1N_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_DQ1N :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ1N_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ1N_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ1N_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_DQ1N :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ1N_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ1N_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_DQ1N :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ1N_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ1N_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ1N_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_DQ1N :: reserved2 [11:08] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ1N_reserved2_MASK 0x00000f00
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ1N_reserved2_SHIFT 8
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_DQ1N :: VDL_STEP [07:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ1N_VDL_STEP_MASK 0x000000ff
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ1N_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ1N_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_RD_DQ2P - Read channel DQ2-P VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_DQ2P :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ2P_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ2P_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ2P_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_DQ2P :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ2P_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ2P_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_DQ2P :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ2P_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ2P_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ2P_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_DQ2P :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ2P_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ2P_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_DQ2P :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ2P_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ2P_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ2P_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_DQ2P :: reserved2 [11:08] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ2P_reserved2_MASK 0x00000f00
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ2P_reserved2_SHIFT 8
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_DQ2P :: VDL_STEP [07:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ2P_VDL_STEP_MASK 0x000000ff
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ2P_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ2P_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_RD_DQ2N - Read channel DQ2-N VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_DQ2N :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ2N_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ2N_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ2N_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_DQ2N :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ2N_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ2N_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_DQ2N :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ2N_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ2N_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ2N_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_DQ2N :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ2N_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ2N_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_DQ2N :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ2N_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ2N_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ2N_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_DQ2N :: reserved2 [11:08] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ2N_reserved2_MASK 0x00000f00
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ2N_reserved2_SHIFT 8
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_DQ2N :: VDL_STEP [07:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ2N_VDL_STEP_MASK 0x000000ff
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ2N_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ2N_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_RD_DQ3P - Read channel DQ3-P VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_DQ3P :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ3P_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ3P_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ3P_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_DQ3P :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ3P_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ3P_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_DQ3P :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ3P_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ3P_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ3P_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_DQ3P :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ3P_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ3P_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_DQ3P :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ3P_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ3P_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ3P_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_DQ3P :: reserved2 [11:08] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ3P_reserved2_MASK 0x00000f00
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ3P_reserved2_SHIFT 8
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_DQ3P :: VDL_STEP [07:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ3P_VDL_STEP_MASK 0x000000ff
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ3P_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ3P_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_RD_DQ3N - Read channel DQ3-N VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_DQ3N :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ3N_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ3N_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ3N_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_DQ3N :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ3N_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ3N_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_DQ3N :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ3N_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ3N_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ3N_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_DQ3N :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ3N_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ3N_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_DQ3N :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ3N_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ3N_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ3N_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_DQ3N :: reserved2 [11:08] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ3N_reserved2_MASK 0x00000f00
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ3N_reserved2_SHIFT 8
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_DQ3N :: VDL_STEP [07:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ3N_VDL_STEP_MASK 0x000000ff
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ3N_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ3N_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_RD_DQ4P - Read channel DQ4-P VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_DQ4P :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ4P_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ4P_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ4P_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_DQ4P :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ4P_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ4P_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_DQ4P :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ4P_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ4P_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ4P_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_DQ4P :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ4P_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ4P_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_DQ4P :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ4P_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ4P_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ4P_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_DQ4P :: reserved2 [11:08] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ4P_reserved2_MASK 0x00000f00
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ4P_reserved2_SHIFT 8
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_DQ4P :: VDL_STEP [07:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ4P_VDL_STEP_MASK 0x000000ff
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ4P_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ4P_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_RD_DQ4N - Read channel DQ4-N VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_DQ4N :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ4N_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ4N_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ4N_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_DQ4N :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ4N_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ4N_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_DQ4N :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ4N_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ4N_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ4N_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_DQ4N :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ4N_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ4N_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_DQ4N :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ4N_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ4N_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ4N_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_DQ4N :: reserved2 [11:08] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ4N_reserved2_MASK 0x00000f00
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ4N_reserved2_SHIFT 8
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_DQ4N :: VDL_STEP [07:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ4N_VDL_STEP_MASK 0x000000ff
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ4N_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ4N_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_RD_DQ5P - Read channel DQ5-P VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_DQ5P :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ5P_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ5P_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ5P_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_DQ5P :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ5P_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ5P_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_DQ5P :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ5P_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ5P_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ5P_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_DQ5P :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ5P_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ5P_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_DQ5P :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ5P_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ5P_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ5P_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_DQ5P :: reserved2 [11:08] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ5P_reserved2_MASK 0x00000f00
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ5P_reserved2_SHIFT 8
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_DQ5P :: VDL_STEP [07:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ5P_VDL_STEP_MASK 0x000000ff
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ5P_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ5P_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_RD_DQ5N - Read channel DQ5-N VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_DQ5N :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ5N_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ5N_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ5N_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_DQ5N :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ5N_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ5N_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_DQ5N :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ5N_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ5N_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ5N_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_DQ5N :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ5N_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ5N_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_DQ5N :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ5N_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ5N_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ5N_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_DQ5N :: reserved2 [11:08] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ5N_reserved2_MASK 0x00000f00
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ5N_reserved2_SHIFT 8
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_DQ5N :: VDL_STEP [07:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ5N_VDL_STEP_MASK 0x000000ff
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ5N_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ5N_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_RD_DQ6P - Read channel DQ6-P VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_DQ6P :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ6P_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ6P_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ6P_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_DQ6P :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ6P_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ6P_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_DQ6P :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ6P_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ6P_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ6P_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_DQ6P :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ6P_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ6P_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_DQ6P :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ6P_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ6P_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ6P_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_DQ6P :: reserved2 [11:08] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ6P_reserved2_MASK 0x00000f00
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ6P_reserved2_SHIFT 8
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_DQ6P :: VDL_STEP [07:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ6P_VDL_STEP_MASK 0x000000ff
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ6P_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ6P_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_RD_DQ6N - Read channel DQ6-N VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_DQ6N :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ6N_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ6N_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ6N_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_DQ6N :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ6N_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ6N_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_DQ6N :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ6N_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ6N_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ6N_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_DQ6N :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ6N_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ6N_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_DQ6N :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ6N_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ6N_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ6N_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_DQ6N :: reserved2 [11:08] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ6N_reserved2_MASK 0x00000f00
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ6N_reserved2_SHIFT 8
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_DQ6N :: VDL_STEP [07:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ6N_VDL_STEP_MASK 0x000000ff
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ6N_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ6N_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_RD_DQ7P - Read channel DQ7-P VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_DQ7P :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ7P_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ7P_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ7P_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_DQ7P :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ7P_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ7P_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_DQ7P :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ7P_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ7P_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ7P_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_DQ7P :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ7P_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ7P_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_DQ7P :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ7P_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ7P_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ7P_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_DQ7P :: reserved2 [11:08] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ7P_reserved2_MASK 0x00000f00
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ7P_reserved2_SHIFT 8
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_DQ7P :: VDL_STEP [07:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ7P_VDL_STEP_MASK 0x000000ff
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ7P_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ7P_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_RD_DQ7N - Read channel DQ7-N VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_DQ7N :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ7N_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ7N_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ7N_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_DQ7N :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ7N_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ7N_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_DQ7N :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ7N_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ7N_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ7N_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_DQ7N :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ7N_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ7N_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_DQ7N :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ7N_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ7N_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ7N_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_DQ7N :: reserved2 [11:08] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ7N_reserved2_MASK 0x00000f00
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ7N_reserved2_SHIFT 8
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_DQ7N :: VDL_STEP [07:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ7N_VDL_STEP_MASK 0x000000ff
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ7N_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ7N_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_RD_DMP - Read channel DM-P VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_DMP :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DMP_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DMP_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DMP_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_DMP :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DMP_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DMP_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_DMP :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DMP_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DMP_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DMP_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_DMP :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DMP_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DMP_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_DMP :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DMP_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DMP_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DMP_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_DMP :: reserved2 [11:08] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DMP_reserved2_MASK 0x00000f00
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DMP_reserved2_SHIFT 8
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_DMP :: VDL_STEP [07:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DMP_VDL_STEP_MASK 0x000000ff
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DMP_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DMP_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_RD_DMN - Read channel DM-N VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_DMN :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DMN_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DMN_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DMN_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_DMN :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DMN_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DMN_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_DMN :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DMN_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DMN_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DMN_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_DMN :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DMN_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DMN_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_DMN :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DMN_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DMN_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DMN_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_DMN :: reserved2 [11:08] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DMN_reserved2_MASK 0x00000f00
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DMN_reserved2_SHIFT 8
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_DMN :: VDL_STEP [07:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DMN_VDL_STEP_MASK 0x000000ff
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DMN_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DMN_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_RD_EDCP - Read channel EDC-P VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_EDCP :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_EDCP_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_EDCP_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_EDCP_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_EDCP :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_EDCP_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_EDCP_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_EDCP :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_EDCP_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_EDCP_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_EDCP_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_EDCP :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_EDCP_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_EDCP_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_EDCP :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_EDCP_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_EDCP_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_EDCP_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_EDCP :: reserved2 [11:08] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_EDCP_reserved2_MASK 0x00000f00
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_EDCP_reserved2_SHIFT 8
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_EDCP :: VDL_STEP [07:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_EDCP_VDL_STEP_MASK 0x000000ff
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_EDCP_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_EDCP_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_RD_EDCN - Read channel EDC-N VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_EDCN :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_EDCN_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_EDCN_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_EDCN_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_EDCN :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_EDCN_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_EDCN_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_EDCN :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_EDCN_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_EDCN_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_EDCN_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_EDCN :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_EDCN_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_EDCN_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_EDCN :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_EDCN_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_EDCN_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_EDCN_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_EDCN :: reserved2 [11:08] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_EDCN_reserved2_MASK 0x00000f00
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_EDCN_reserved2_SHIFT 8
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_EDCN :: VDL_STEP [07:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_EDCN_VDL_STEP_MASK 0x000000ff
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_EDCN_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_EDCN_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_RD_EN_CS0 - Read channel CS_N[0] read enable VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_EN_CS0 :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_EN_CS0_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_EN_CS0_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_EN_CS0_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_EN_CS0 :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_EN_CS0_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_EN_CS0_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_EN_CS0 :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_EN_CS0_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_EN_CS0_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_EN_CS0_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_EN_CS0 :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_EN_CS0_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_EN_CS0_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_EN_CS0 :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_EN_CS0_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_EN_CS0_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_EN_CS0_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_EN_CS0 :: reserved2 [11:08] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_EN_CS0_reserved2_MASK 0x00000f00
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_EN_CS0_reserved2_SHIFT 8
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_EN_CS0 :: VDL_STEP [07:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_EN_CS0_VDL_STEP_MASK 0x000000ff
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_EN_CS0_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_EN_CS0_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_RD_EN_CS1 - Read channel CS_N[1] read enable VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_EN_CS1 :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_EN_CS1_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_EN_CS1_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_EN_CS1_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_EN_CS1 :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_EN_CS1_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_EN_CS1_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_EN_CS1 :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_EN_CS1_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_EN_CS1_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_EN_CS1_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_EN_CS1 :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_EN_CS1_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_EN_CS1_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_EN_CS1 :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_EN_CS1_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_EN_CS1_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_EN_CS1_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_EN_CS1 :: reserved2 [11:08] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_EN_CS1_reserved2_MASK 0x00000f00
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_EN_CS1_reserved2_SHIFT 8
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_EN_CS1 :: VDL_STEP [07:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_EN_CS1_VDL_STEP_MASK 0x000000ff
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_EN_CS1_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_EN_CS1_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CLK_CONTROL - DDR interface signal Write Leveling CLK VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CLK_CONTROL :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CLK_CONTROL_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CLK_CONTROL_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CLK_CONTROL_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CLK_CONTROL :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CLK_CONTROL_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CLK_CONTROL_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CLK_CONTROL :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CLK_CONTROL_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CLK_CONTROL_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CLK_CONTROL_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CLK_CONTROL :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CLK_CONTROL_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CLK_CONTROL_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CLK_CONTROL :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CLK_CONTROL_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CLK_CONTROL_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CLK_CONTROL_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CLK_CONTROL :: reserved2 [11:09] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CLK_CONTROL_reserved2_MASK 0x00000e00
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CLK_CONTROL_reserved2_SHIFT 9
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CLK_CONTROL :: VDL_STEP [08:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CLK_CONTROL_VDL_STEP_MASK 0x000001ff
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CLK_CONTROL_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CLK_CONTROL_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_LDE_CONTROL - DDR interface signal Write Leveling Capture Enable VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_LDE_CONTROL :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_LDE_CONTROL_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_LDE_CONTROL_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_LDE_CONTROL_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_LDE_CONTROL :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_LDE_CONTROL_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_LDE_CONTROL_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_LDE_CONTROL :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_LDE_CONTROL_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_LDE_CONTROL_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_LDE_CONTROL_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_LDE_CONTROL :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_LDE_CONTROL_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_LDE_CONTROL_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_LDE_CONTROL :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_LDE_CONTROL_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_LDE_CONTROL_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_LDE_CONTROL_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_LDE_CONTROL :: reserved2 [11:09] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_LDE_CONTROL_reserved2_MASK 0x00000e00
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_LDE_CONTROL_reserved2_SHIFT 9
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_LDE_CONTROL :: VDL_STEP [08:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_LDE_CONTROL_VDL_STEP_MASK 0x000001ff
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_LDE_CONTROL_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_LDE_CONTROL_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *RD_EN_DLY_CYC - Read enable bit-clock cycle delay control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_1_0 :: RD_EN_DLY_CYC :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_RD_EN_DLY_CYC_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_RD_EN_DLY_CYC_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_RD_EN_DLY_CYC_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: RD_EN_DLY_CYC :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_RD_EN_DLY_CYC_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_RD_EN_DLY_CYC_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: RD_EN_DLY_CYC :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_RD_EN_DLY_CYC_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_RD_EN_DLY_CYC_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_RD_EN_DLY_CYC_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: RD_EN_DLY_CYC :: reserved1 [15:08] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_RD_EN_DLY_CYC_reserved1_MASK 0x0000ff00
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_RD_EN_DLY_CYC_reserved1_SHIFT 8
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: RD_EN_DLY_CYC :: CS1_CYCLES [07:04] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_RD_EN_DLY_CYC_CS1_CYCLES_MASK 0x000000f0
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_RD_EN_DLY_CYC_CS1_CYCLES_SHIFT 4
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_RD_EN_DLY_CYC_CS1_CYCLES_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: RD_EN_DLY_CYC :: CS0_CYCLES [03:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_RD_EN_DLY_CYC_CS0_CYCLES_MASK 0x0000000f
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_RD_EN_DLY_CYC_CS0_CYCLES_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_RD_EN_DLY_CYC_CS0_CYCLES_DEFAULT 0x00000000
-
-/***************************************************************************
- *WR_CHAN_DLY_CYC - Write leveling bit-clock cycle delay control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_1_0 :: WR_CHAN_DLY_CYC :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_WR_CHAN_DLY_CYC_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_WR_CHAN_DLY_CYC_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_WR_CHAN_DLY_CYC_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: WR_CHAN_DLY_CYC :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_WR_CHAN_DLY_CYC_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_WR_CHAN_DLY_CYC_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: WR_CHAN_DLY_CYC :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_WR_CHAN_DLY_CYC_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_WR_CHAN_DLY_CYC_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_WR_CHAN_DLY_CYC_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: WR_CHAN_DLY_CYC :: reserved1 [15:03] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_WR_CHAN_DLY_CYC_reserved1_MASK 0x0000fff8
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_WR_CHAN_DLY_CYC_reserved1_SHIFT 3
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: WR_CHAN_DLY_CYC :: CYCLES [02:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_WR_CHAN_DLY_CYC_CYCLES_MASK 0x00000007
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_WR_CHAN_DLY_CYC_CYCLES_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_WR_CHAN_DLY_CYC_CYCLES_DEFAULT 0x00000000
-
-/***************************************************************************
- *READ_CONTROL - Read channel datapath control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_1_0 :: READ_CONTROL :: reserved0 [31:05] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_READ_CONTROL_reserved0_MASK 0xffffffe0
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_READ_CONTROL_reserved0_SHIFT 5
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: READ_CONTROL :: MODE [04:04] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_READ_CONTROL_MODE_MASK 0x00000010
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_READ_CONTROL_MODE_SHIFT 4
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_READ_CONTROL_MODE_DEFAULT 0x00000001
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: READ_CONTROL :: reserved1 [03:03] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_READ_CONTROL_reserved1_MASK 0x00000008
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_READ_CONTROL_reserved1_SHIFT 3
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: READ_CONTROL :: RD_DATA_DLY [02:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_READ_CONTROL_RD_DATA_DLY_MASK 0x00000007
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_READ_CONTROL_RD_DATA_DLY_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_READ_CONTROL_RD_DATA_DLY_DEFAULT 0x00000007
-
-/***************************************************************************
- *READ_FIFO_ADDR - Read fifo addresss pointer register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_1_0 :: READ_FIFO_ADDR :: reserved0 [31:03] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_READ_FIFO_ADDR_reserved0_MASK 0xfffffff8
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_READ_FIFO_ADDR_reserved0_SHIFT 3
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: READ_FIFO_ADDR :: ADDR [02:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_READ_FIFO_ADDR_ADDR_MASK 0x00000007
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_READ_FIFO_ADDR_ADDR_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_READ_FIFO_ADDR_ADDR_DEFAULT 0x00000000
-
-/***************************************************************************
- *READ_FIFO_DATA - Read fifo data register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_1_0 :: READ_FIFO_DATA :: DATA [31:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_READ_FIFO_DATA_DATA_MASK 0xffffffff
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_READ_FIFO_DATA_DATA_SHIFT 0
-
-/***************************************************************************
- *READ_FIFO_DM_DBI - Read fifo dm/dbi register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_1_0 :: READ_FIFO_DM_DBI :: reserved0 [31:04] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_READ_FIFO_DM_DBI_reserved0_MASK 0xfffffff0
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_READ_FIFO_DM_DBI_reserved0_SHIFT 4
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: READ_FIFO_DM_DBI :: DM_DBI [03:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_READ_FIFO_DM_DBI_DM_DBI_MASK 0x0000000f
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_READ_FIFO_DM_DBI_DM_DBI_SHIFT 0
-
-/***************************************************************************
- *READ_FIFO_STATUS - Read fifo status register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_1_0 :: READ_FIFO_STATUS :: reserved0 [31:02] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_READ_FIFO_STATUS_reserved0_MASK 0xfffffffc
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_READ_FIFO_STATUS_reserved0_SHIFT 2
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: READ_FIFO_STATUS :: OVERFLOW [01:01] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_READ_FIFO_STATUS_OVERFLOW_MASK 0x00000002
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_READ_FIFO_STATUS_OVERFLOW_SHIFT 1
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_READ_FIFO_STATUS_OVERFLOW_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: READ_FIFO_STATUS :: UNDERFLOW [00:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_READ_FIFO_STATUS_UNDERFLOW_MASK 0x00000001
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_READ_FIFO_STATUS_UNDERFLOW_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_READ_FIFO_STATUS_UNDERFLOW_DEFAULT 0x00000000
-
-/***************************************************************************
- *READ_FIFO_CLEAR - Read fifo status clear register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_1_0 :: READ_FIFO_CLEAR :: reserved0 [31:01] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_READ_FIFO_CLEAR_reserved0_MASK 0xfffffffe
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_READ_FIFO_CLEAR_reserved0_SHIFT 1
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: READ_FIFO_CLEAR :: CLEAR [00:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_READ_FIFO_CLEAR_CLEAR_MASK 0x00000001
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_READ_FIFO_CLEAR_CLEAR_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_READ_FIFO_CLEAR_CLEAR_DEFAULT 0x00000000
-
-/***************************************************************************
- *IDLE_PAD_CONTROL - Idle mode SSTL pad control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_1_0 :: IDLE_PAD_CONTROL :: IDLE [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_IDLE_PAD_CONTROL_IDLE_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_IDLE_PAD_CONTROL_IDLE_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_IDLE_PAD_CONTROL_IDLE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: IDLE_PAD_CONTROL :: reserved0 [30:20] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_IDLE_PAD_CONTROL_reserved0_MASK 0x7ff00000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_IDLE_PAD_CONTROL_reserved0_SHIFT 20
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: IDLE_PAD_CONTROL :: AUTO_DQ_RXENB_MODE [19:18] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_IDLE_PAD_CONTROL_AUTO_DQ_RXENB_MODE_MASK 0x000c0000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_IDLE_PAD_CONTROL_AUTO_DQ_RXENB_MODE_SHIFT 18
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_IDLE_PAD_CONTROL_AUTO_DQ_RXENB_MODE_DEFAULT 0x00000001
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: IDLE_PAD_CONTROL :: AUTO_DQ_IDDQ_MODE [17:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_IDLE_PAD_CONTROL_AUTO_DQ_IDDQ_MODE_MASK 0x00030000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_IDLE_PAD_CONTROL_AUTO_DQ_IDDQ_MODE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_IDLE_PAD_CONTROL_AUTO_DQ_IDDQ_MODE_DEFAULT 0x00000001
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: IDLE_PAD_CONTROL :: reserved_for_padding1 [15:15] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_IDLE_PAD_CONTROL_reserved_for_padding1_MASK 0x00008000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_IDLE_PAD_CONTROL_reserved_for_padding1_SHIFT 15
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: IDLE_PAD_CONTROL :: IO_IDLE_ENABLE [14:04] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_IDLE_PAD_CONTROL_IO_IDLE_ENABLE_MASK 0x00007ff0
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_IDLE_PAD_CONTROL_IO_IDLE_ENABLE_SHIFT 4
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_IDLE_PAD_CONTROL_IO_IDLE_ENABLE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: IDLE_PAD_CONTROL :: RXENB [03:03] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_IDLE_PAD_CONTROL_RXENB_MASK 0x00000008
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_IDLE_PAD_CONTROL_RXENB_SHIFT 3
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_IDLE_PAD_CONTROL_RXENB_DEFAULT 0x00000001
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: IDLE_PAD_CONTROL :: IDDQ [02:02] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_IDLE_PAD_CONTROL_IDDQ_MASK 0x00000004
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_IDLE_PAD_CONTROL_IDDQ_SHIFT 2
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_IDLE_PAD_CONTROL_IDDQ_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: IDLE_PAD_CONTROL :: DOUT_N [01:01] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_IDLE_PAD_CONTROL_DOUT_N_MASK 0x00000002
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_IDLE_PAD_CONTROL_DOUT_N_SHIFT 1
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: IDLE_PAD_CONTROL :: DOUT_P [00:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_IDLE_PAD_CONTROL_DOUT_P_MASK 0x00000001
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_IDLE_PAD_CONTROL_DOUT_P_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_IDLE_PAD_CONTROL_DOUT_P_DEFAULT 0x00000000
-
-/***************************************************************************
- *DRIVE_PAD_CTL - SSTL pad drive characteristics control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_1_0 :: DRIVE_PAD_CTL :: reserved0 [31:30] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_DRIVE_PAD_CTL_reserved0_MASK 0xc0000000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_DRIVE_PAD_CTL_reserved0_SHIFT 30
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: DRIVE_PAD_CTL :: BL_PD_IDLE_STRENGTH [29:25] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_DRIVE_PAD_CTL_BL_PD_IDLE_STRENGTH_MASK 0x3e000000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_DRIVE_PAD_CTL_BL_PD_IDLE_STRENGTH_SHIFT 25
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_DRIVE_PAD_CTL_BL_PD_IDLE_STRENGTH_DEFAULT 0x0000001f
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: DRIVE_PAD_CTL :: BL_ND_IDLE_STRENGTH [24:20] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_DRIVE_PAD_CTL_BL_ND_IDLE_STRENGTH_MASK 0x01f00000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_DRIVE_PAD_CTL_BL_ND_IDLE_STRENGTH_SHIFT 20
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_DRIVE_PAD_CTL_BL_ND_IDLE_STRENGTH_DEFAULT 0x0000001f
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: DRIVE_PAD_CTL :: BL_PD_TERM_STRENGTH [19:15] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_DRIVE_PAD_CTL_BL_PD_TERM_STRENGTH_MASK 0x000f8000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_DRIVE_PAD_CTL_BL_PD_TERM_STRENGTH_SHIFT 15
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_DRIVE_PAD_CTL_BL_PD_TERM_STRENGTH_DEFAULT 0x00000008
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: DRIVE_PAD_CTL :: BL_ND_TERM_STRENGTH [14:10] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_DRIVE_PAD_CTL_BL_ND_TERM_STRENGTH_MASK 0x00007c00
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_DRIVE_PAD_CTL_BL_ND_TERM_STRENGTH_SHIFT 10
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_DRIVE_PAD_CTL_BL_ND_TERM_STRENGTH_DEFAULT 0x00000008
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: DRIVE_PAD_CTL :: BL_PD_STRENGTH [09:05] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_DRIVE_PAD_CTL_BL_PD_STRENGTH_MASK 0x000003e0
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_DRIVE_PAD_CTL_BL_PD_STRENGTH_SHIFT 5
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_DRIVE_PAD_CTL_BL_PD_STRENGTH_DEFAULT 0x0000001f
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: DRIVE_PAD_CTL :: BL_ND_STRENGTH [04:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_DRIVE_PAD_CTL_BL_ND_STRENGTH_MASK 0x0000001f
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_DRIVE_PAD_CTL_BL_ND_STRENGTH_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_DRIVE_PAD_CTL_BL_ND_STRENGTH_DEFAULT 0x0000001f
-
-/***************************************************************************
- *RD_EN_DRIVE_PAD_CTL - SSTL read enable pad drive characteristics control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_1_0 :: RD_EN_DRIVE_PAD_CTL :: reserved0 [31:20] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_RD_EN_DRIVE_PAD_CTL_reserved0_MASK 0xfff00000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_RD_EN_DRIVE_PAD_CTL_reserved0_SHIFT 20
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: RD_EN_DRIVE_PAD_CTL :: EDC_RD_EN_PD_STRENGTH [19:15] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_RD_EN_DRIVE_PAD_CTL_EDC_RD_EN_PD_STRENGTH_MASK 0x000f8000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_RD_EN_DRIVE_PAD_CTL_EDC_RD_EN_PD_STRENGTH_SHIFT 15
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_RD_EN_DRIVE_PAD_CTL_EDC_RD_EN_PD_STRENGTH_DEFAULT 0x0000001f
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: RD_EN_DRIVE_PAD_CTL :: EDC_RD_EN_ND_STRENGTH [14:10] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_RD_EN_DRIVE_PAD_CTL_EDC_RD_EN_ND_STRENGTH_MASK 0x00007c00
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_RD_EN_DRIVE_PAD_CTL_EDC_RD_EN_ND_STRENGTH_SHIFT 10
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_RD_EN_DRIVE_PAD_CTL_EDC_RD_EN_ND_STRENGTH_DEFAULT 0x0000001f
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: RD_EN_DRIVE_PAD_CTL :: BL_RD_EN_PD_STRENGTH [09:05] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_RD_EN_DRIVE_PAD_CTL_BL_RD_EN_PD_STRENGTH_MASK 0x000003e0
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_RD_EN_DRIVE_PAD_CTL_BL_RD_EN_PD_STRENGTH_SHIFT 5
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_RD_EN_DRIVE_PAD_CTL_BL_RD_EN_PD_STRENGTH_DEFAULT 0x0000001f
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: RD_EN_DRIVE_PAD_CTL :: BL_RD_EN_ND_STRENGTH [04:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_RD_EN_DRIVE_PAD_CTL_BL_RD_EN_ND_STRENGTH_MASK 0x0000001f
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_RD_EN_DRIVE_PAD_CTL_BL_RD_EN_ND_STRENGTH_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_RD_EN_DRIVE_PAD_CTL_BL_RD_EN_ND_STRENGTH_DEFAULT 0x0000001f
-
-/***************************************************************************
- *STATIC_PAD_CTL - pad rx and tx characteristics control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_1_0 :: STATIC_PAD_CTL :: reserved0 [31:21] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_STATIC_PAD_CTL_reserved0_MASK 0xffe00000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_STATIC_PAD_CTL_reserved0_SHIFT 21
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: STATIC_PAD_CTL :: DQS_MODE [20:20] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_STATIC_PAD_CTL_DQS_MODE_MASK 0x00100000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_STATIC_PAD_CTL_DQS_MODE_SHIFT 20
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_STATIC_PAD_CTL_DQS_MODE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: STATIC_PAD_CTL :: reserved1 [19:18] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_STATIC_PAD_CTL_reserved1_MASK 0x000c0000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_STATIC_PAD_CTL_reserved1_SHIFT 18
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: STATIC_PAD_CTL :: EDC_MODE [17:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_STATIC_PAD_CTL_EDC_MODE_MASK 0x00030000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_STATIC_PAD_CTL_EDC_MODE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_STATIC_PAD_CTL_EDC_MODE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: STATIC_PAD_CTL :: reserved2 [15:15] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_STATIC_PAD_CTL_reserved2_MASK 0x00008000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_STATIC_PAD_CTL_reserved2_SHIFT 15
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: STATIC_PAD_CTL :: WDBI_ENABLE [14:14] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_STATIC_PAD_CTL_WDBI_ENABLE_MASK 0x00004000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_STATIC_PAD_CTL_WDBI_ENABLE_SHIFT 14
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_STATIC_PAD_CTL_WDBI_ENABLE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: STATIC_PAD_CTL :: RDBI_ENABLE [13:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_STATIC_PAD_CTL_RDBI_ENABLE_MASK 0x00002000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_STATIC_PAD_CTL_RDBI_ENABLE_SHIFT 13
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_STATIC_PAD_CTL_RDBI_ENABLE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: STATIC_PAD_CTL :: DM_MODE [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_STATIC_PAD_CTL_DM_MODE_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_STATIC_PAD_CTL_DM_MODE_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_STATIC_PAD_CTL_DM_MODE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: STATIC_PAD_CTL :: reserved3 [11:11] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_STATIC_PAD_CTL_reserved3_MASK 0x00000800
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_STATIC_PAD_CTL_reserved3_SHIFT 11
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: STATIC_PAD_CTL :: DQS_TX_PAUSE [10:10] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_STATIC_PAD_CTL_DQS_TX_PAUSE_MASK 0x00000400
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_STATIC_PAD_CTL_DQS_TX_PAUSE_SHIFT 10
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_STATIC_PAD_CTL_DQS_TX_PAUSE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: STATIC_PAD_CTL :: DQS_TX_DIS [09:09] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_STATIC_PAD_CTL_DQS_TX_DIS_MASK 0x00000200
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_STATIC_PAD_CTL_DQS_TX_DIS_SHIFT 9
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_STATIC_PAD_CTL_DQS_TX_DIS_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: STATIC_PAD_CTL :: reserved4 [08:08] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_STATIC_PAD_CTL_reserved4_MASK 0x00000100
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_STATIC_PAD_CTL_reserved4_SHIFT 8
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: STATIC_PAD_CTL :: TX_MODE [07:04] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_STATIC_PAD_CTL_TX_MODE_MASK 0x000000f0
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_STATIC_PAD_CTL_TX_MODE_SHIFT 4
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_STATIC_PAD_CTL_TX_MODE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: STATIC_PAD_CTL :: reserved5 [03:03] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_STATIC_PAD_CTL_reserved5_MASK 0x00000008
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_STATIC_PAD_CTL_reserved5_SHIFT 3
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: STATIC_PAD_CTL :: RX_MODE [02:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_STATIC_PAD_CTL_RX_MODE_MASK 0x00000007
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_STATIC_PAD_CTL_RX_MODE_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_STATIC_PAD_CTL_RX_MODE_DEFAULT 0x00000000
-
-/***************************************************************************
- *WR_PREAMBLE_MODE - Write cycle preamble control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_1_0 :: WR_PREAMBLE_MODE :: reserved0 [31:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_WR_PREAMBLE_MODE_reserved0_MASK 0xffff0000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_WR_PREAMBLE_MODE_reserved0_SHIFT 16
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: WR_PREAMBLE_MODE :: DQ_POSTAM_BITS [15:14] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_WR_PREAMBLE_MODE_DQ_POSTAM_BITS_MASK 0x0000c000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_WR_PREAMBLE_MODE_DQ_POSTAM_BITS_SHIFT 14
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_WR_PREAMBLE_MODE_DQ_POSTAM_BITS_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: WR_PREAMBLE_MODE :: DQ_PREAM_BITS [13:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_WR_PREAMBLE_MODE_DQ_PREAM_BITS_MASK 0x00003000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_WR_PREAMBLE_MODE_DQ_PREAM_BITS_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_WR_PREAMBLE_MODE_DQ_PREAM_BITS_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: WR_PREAMBLE_MODE :: DQS [11:08] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_WR_PREAMBLE_MODE_DQS_MASK 0x00000f00
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_WR_PREAMBLE_MODE_DQS_SHIFT 8
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_WR_PREAMBLE_MODE_DQS_DEFAULT 0x0000000e
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: WR_PREAMBLE_MODE :: reserved1 [07:05] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_WR_PREAMBLE_MODE_reserved1_MASK 0x000000e0
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_WR_PREAMBLE_MODE_reserved1_SHIFT 5
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: WR_PREAMBLE_MODE :: DQS_POSTAM_BITS [04:03] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_WR_PREAMBLE_MODE_DQS_POSTAM_BITS_MASK 0x00000018
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_WR_PREAMBLE_MODE_DQS_POSTAM_BITS_SHIFT 3
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_WR_PREAMBLE_MODE_DQS_POSTAM_BITS_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: WR_PREAMBLE_MODE :: DQS_PREAM_BITS [02:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_WR_PREAMBLE_MODE_DQS_PREAM_BITS_MASK 0x00000007
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_WR_PREAMBLE_MODE_DQS_PREAM_BITS_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_WR_PREAMBLE_MODE_DQS_PREAM_BITS_DEFAULT 0x00000002
-
-/***************************************************************************
- *ODT_CONTROL - Read channel ODT control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_1_0 :: ODT_CONTROL :: reserved_for_padding0 [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_ODT_CONTROL_reserved_for_padding0_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_ODT_CONTROL_reserved_for_padding0_SHIFT 31
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: ODT_CONTROL :: reserved1 [30:10] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_ODT_CONTROL_reserved1_MASK 0x7ffffc00
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_ODT_CONTROL_reserved1_SHIFT 10
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: ODT_CONTROL :: ODT_ENABLE [09:09] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_ODT_CONTROL_ODT_ENABLE_MASK 0x00000200
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_ODT_CONTROL_ODT_ENABLE_SHIFT 9
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_ODT_CONTROL_ODT_ENABLE_DEFAULT 0x00000001
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: ODT_CONTROL :: ODT_DELAY [08:06] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_ODT_CONTROL_ODT_DELAY_MASK 0x000001c0
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_ODT_CONTROL_ODT_DELAY_SHIFT 6
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_ODT_CONTROL_ODT_DELAY_DEFAULT 0x00000001
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: ODT_CONTROL :: ODT_POST_LENGTH [05:03] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_ODT_CONTROL_ODT_POST_LENGTH_MASK 0x00000038
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_ODT_CONTROL_ODT_POST_LENGTH_SHIFT 3
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_ODT_CONTROL_ODT_POST_LENGTH_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: ODT_CONTROL :: ODT_PRE_LENGTH [02:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_ODT_CONTROL_ODT_PRE_LENGTH_MASK 0x00000007
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_ODT_CONTROL_ODT_PRE_LENGTH_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_ODT_CONTROL_ODT_PRE_LENGTH_DEFAULT 0x00000003
-
-/***************************************************************************
- *EDC_DPD_CONTROL - GDDR5M EDC digital phase detector control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_1_0 :: EDC_DPD_CONTROL :: reserved0 [31:06] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_DPD_CONTROL_reserved0_MASK 0xffffffc0
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_DPD_CONTROL_reserved0_SHIFT 6
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: EDC_DPD_CONTROL :: DQS_PHASE_OVERRIDE_VALUE [05:05] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_DPD_CONTROL_DQS_PHASE_OVERRIDE_VALUE_MASK 0x00000020
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_DPD_CONTROL_DQS_PHASE_OVERRIDE_VALUE_SHIFT 5
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_DPD_CONTROL_DQS_PHASE_OVERRIDE_VALUE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: EDC_DPD_CONTROL :: DQS_PHASE_OVERRIDE_ENABLE [04:04] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_DPD_CONTROL_DQS_PHASE_OVERRIDE_ENABLE_MASK 0x00000010
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_DPD_CONTROL_DQS_PHASE_OVERRIDE_ENABLE_SHIFT 4
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_DPD_CONTROL_DQS_PHASE_OVERRIDE_ENABLE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: EDC_DPD_CONTROL :: SET_ADJ_EN [03:03] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_DPD_CONTROL_SET_ADJ_EN_MASK 0x00000008
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_DPD_CONTROL_SET_ADJ_EN_SHIFT 3
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_DPD_CONTROL_SET_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: EDC_DPD_CONTROL :: UPDATE [02:02] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_DPD_CONTROL_UPDATE_MASK 0x00000004
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_DPD_CONTROL_UPDATE_SHIFT 2
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_DPD_CONTROL_UPDATE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: EDC_DPD_CONTROL :: MONITOR [01:01] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_DPD_CONTROL_MONITOR_MASK 0x00000002
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_DPD_CONTROL_MONITOR_SHIFT 1
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_DPD_CONTROL_MONITOR_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: EDC_DPD_CONTROL :: INIT [00:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_DPD_CONTROL_INIT_MASK 0x00000001
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_DPD_CONTROL_INIT_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_DPD_CONTROL_INIT_DEFAULT 0x00000000
-
-/***************************************************************************
- *EDC_DPD_STATUS - GDDR5M EDC digital phase detector status register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_1_0 :: EDC_DPD_STATUS :: reserved0 [31:25] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_DPD_STATUS_reserved0_MASK 0xfe000000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_DPD_STATUS_reserved0_SHIFT 25
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: EDC_DPD_STATUS :: CURRENT_DQS_PHASE [24:24] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_DPD_STATUS_CURRENT_DQS_PHASE_MASK 0x01000000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_DPD_STATUS_CURRENT_DQS_PHASE_SHIFT 24
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_DPD_STATUS_CURRENT_DQS_PHASE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: EDC_DPD_STATUS :: CURRENT_VDL_SETTING [23:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_DPD_STATUS_CURRENT_VDL_SETTING_MASK 0x00ff0000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_DPD_STATUS_CURRENT_VDL_SETTING_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_DPD_STATUS_CURRENT_VDL_SETTING_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: EDC_DPD_STATUS :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_DPD_STATUS_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_DPD_STATUS_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: EDC_DPD_STATUS :: INIT_DQS_PHASE [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_DPD_STATUS_INIT_DQS_PHASE_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_DPD_STATUS_INIT_DQS_PHASE_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_DPD_STATUS_INIT_DQS_PHASE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: EDC_DPD_STATUS :: INIT_VDL_SETTING [11:04] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_DPD_STATUS_INIT_VDL_SETTING_MASK 0x00000ff0
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_DPD_STATUS_INIT_VDL_SETTING_SHIFT 4
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_DPD_STATUS_INIT_VDL_SETTING_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: EDC_DPD_STATUS :: EDGE_ERROR [03:03] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_DPD_STATUS_EDGE_ERROR_MASK 0x00000008
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_DPD_STATUS_EDGE_ERROR_SHIFT 3
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_DPD_STATUS_EDGE_ERROR_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: EDC_DPD_STATUS :: MONITOR_BUSY [02:02] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_DPD_STATUS_MONITOR_BUSY_MASK 0x00000004
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_DPD_STATUS_MONITOR_BUSY_SHIFT 2
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_DPD_STATUS_MONITOR_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: EDC_DPD_STATUS :: INIT_BUSY [01:01] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_DPD_STATUS_INIT_BUSY_MASK 0x00000002
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_DPD_STATUS_INIT_BUSY_SHIFT 1
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_DPD_STATUS_INIT_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: EDC_DPD_STATUS :: INIT_DONE [00:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_DPD_STATUS_INIT_DONE_MASK 0x00000001
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_DPD_STATUS_INIT_DONE_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_DPD_STATUS_INIT_DONE_DEFAULT 0x00000000
-
-/***************************************************************************
- *EDC_DPD_OUT_CONTROL - GDDR5M EDC digital phase detector output signal control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_1_0 :: EDC_DPD_OUT_CONTROL :: reserved0 [31:20] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_DPD_OUT_CONTROL_reserved0_MASK 0xfff00000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_DPD_OUT_CONTROL_reserved0_SHIFT 20
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: EDC_DPD_OUT_CONTROL :: LOWER_LIMIT [19:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_DPD_OUT_CONTROL_LOWER_LIMIT_MASK 0x000ff000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_DPD_OUT_CONTROL_LOWER_LIMIT_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_DPD_OUT_CONTROL_LOWER_LIMIT_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: EDC_DPD_OUT_CONTROL :: UPPER_LIMIT [11:04] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_DPD_OUT_CONTROL_UPPER_LIMIT_MASK 0x00000ff0
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_DPD_OUT_CONTROL_UPPER_LIMIT_SHIFT 4
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_DPD_OUT_CONTROL_UPPER_LIMIT_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: EDC_DPD_OUT_CONTROL :: reserved1 [03:01] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_DPD_OUT_CONTROL_reserved1_MASK 0x0000000e
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_DPD_OUT_CONTROL_reserved1_SHIFT 1
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: EDC_DPD_OUT_CONTROL :: ENABLE [00:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_DPD_OUT_CONTROL_ENABLE_MASK 0x00000001
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_DPD_OUT_CONTROL_ENABLE_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_DPD_OUT_CONTROL_ENABLE_DEFAULT 0x00000000
-
-/***************************************************************************
- *EDC_DPD_OUT_STATUS - GDDR5M EDC digital phase detector output signal status register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_1_0 :: EDC_DPD_OUT_STATUS :: reserved0 [31:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_DPD_OUT_STATUS_reserved0_MASK 0xfffff000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_DPD_OUT_STATUS_reserved0_SHIFT 12
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: EDC_DPD_OUT_STATUS :: VDL_SETTING [11:04] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_DPD_OUT_STATUS_VDL_SETTING_MASK 0x00000ff0
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_DPD_OUT_STATUS_VDL_SETTING_SHIFT 4
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_DPD_OUT_STATUS_VDL_SETTING_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: EDC_DPD_OUT_STATUS :: reserved1 [03:01] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_DPD_OUT_STATUS_reserved1_MASK 0x0000000e
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_DPD_OUT_STATUS_reserved1_SHIFT 1
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: EDC_DPD_OUT_STATUS :: VALID [00:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_DPD_OUT_STATUS_VALID_MASK 0x00000001
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_DPD_OUT_STATUS_VALID_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_DPD_OUT_STATUS_VALID_DEFAULT 0x00000000
-
-/***************************************************************************
- *EDC_DPD_OUT_STATUS_CLEAR - GDDR5M EDC digital phase detector output signal status clear register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_1_0 :: EDC_DPD_OUT_STATUS_CLEAR :: reserved0 [31:01] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_DPD_OUT_STATUS_CLEAR_reserved0_MASK 0xfffffffe
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_DPD_OUT_STATUS_CLEAR_reserved0_SHIFT 1
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: EDC_DPD_OUT_STATUS_CLEAR :: CLEAR [00:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_DPD_OUT_STATUS_CLEAR_CLEAR_MASK 0x00000001
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_DPD_OUT_STATUS_CLEAR_CLEAR_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_DPD_OUT_STATUS_CLEAR_CLEAR_DEFAULT 0x00000000
-
-/***************************************************************************
- *EDC_CRC_CONTROL - GDDR5M EDC signal path CRC control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_1_0 :: EDC_CRC_CONTROL :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_CRC_CONTROL_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_CRC_CONTROL_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_CRC_CONTROL_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: EDC_CRC_CONTROL :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_CRC_CONTROL_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_CRC_CONTROL_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: EDC_CRC_CONTROL :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_CRC_CONTROL_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_CRC_CONTROL_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_CRC_CONTROL_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: EDC_CRC_CONTROL :: reserved1 [15:11] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_CRC_CONTROL_reserved1_MASK 0x0000f800
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_CRC_CONTROL_reserved1_SHIFT 11
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: EDC_CRC_CONTROL :: CRCWL [10:08] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_CRC_CONTROL_CRCWL_MASK 0x00000700
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_CRC_CONTROL_CRCWL_SHIFT 8
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_CRC_CONTROL_CRCWL_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: EDC_CRC_CONTROL :: reserved2 [07:06] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_CRC_CONTROL_reserved2_MASK 0x000000c0
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_CRC_CONTROL_reserved2_SHIFT 6
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: EDC_CRC_CONTROL :: CRCRL [05:04] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_CRC_CONTROL_CRCRL_MASK 0x00000030
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_CRC_CONTROL_CRCRL_SHIFT 4
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_CRC_CONTROL_CRCRL_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: EDC_CRC_CONTROL :: reserved3 [03:03] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_CRC_CONTROL_reserved3_MASK 0x00000008
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_CRC_CONTROL_reserved3_SHIFT 3
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: EDC_CRC_CONTROL :: COUNT_MODE [02:02] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_CRC_CONTROL_COUNT_MODE_MASK 0x00000004
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_CRC_CONTROL_COUNT_MODE_SHIFT 2
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_CRC_CONTROL_COUNT_MODE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: EDC_CRC_CONTROL :: ENABLE_WR [01:01] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_CRC_CONTROL_ENABLE_WR_MASK 0x00000002
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_CRC_CONTROL_ENABLE_WR_SHIFT 1
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_CRC_CONTROL_ENABLE_WR_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: EDC_CRC_CONTROL :: ENABLE_RD [00:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_CRC_CONTROL_ENABLE_RD_MASK 0x00000001
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_CRC_CONTROL_ENABLE_RD_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_CRC_CONTROL_ENABLE_RD_DEFAULT 0x00000000
-
-/***************************************************************************
- *EDC_CRC_STATUS - GDDR5M EDC signal path CRC status register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_1_0 :: EDC_CRC_STATUS :: reserved0 [31:04] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_CRC_STATUS_reserved0_MASK 0xfffffff0
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_CRC_STATUS_reserved0_SHIFT 4
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: EDC_CRC_STATUS :: WR_FAIL [03:03] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_CRC_STATUS_WR_FAIL_MASK 0x00000008
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_CRC_STATUS_WR_FAIL_SHIFT 3
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_CRC_STATUS_WR_FAIL_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: EDC_CRC_STATUS :: WR_PASS [02:02] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_CRC_STATUS_WR_PASS_MASK 0x00000004
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_CRC_STATUS_WR_PASS_SHIFT 2
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_CRC_STATUS_WR_PASS_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: EDC_CRC_STATUS :: RD_FAIL [01:01] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_CRC_STATUS_RD_FAIL_MASK 0x00000002
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_CRC_STATUS_RD_FAIL_SHIFT 1
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_CRC_STATUS_RD_FAIL_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: EDC_CRC_STATUS :: RD_PASS [00:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_CRC_STATUS_RD_PASS_MASK 0x00000001
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_CRC_STATUS_RD_PASS_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_CRC_STATUS_RD_PASS_DEFAULT 0x00000000
-
-/***************************************************************************
- *EDC_CRC_COUNT - GDDR5M EDC signal path CRC counter register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_1_0 :: EDC_CRC_COUNT :: reserved0 [31:28] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_CRC_COUNT_reserved0_MASK 0xf0000000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_CRC_COUNT_reserved0_SHIFT 28
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: EDC_CRC_COUNT :: WR_COUNT [27:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_CRC_COUNT_WR_COUNT_MASK 0x0fff0000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_CRC_COUNT_WR_COUNT_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_CRC_COUNT_WR_COUNT_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: EDC_CRC_COUNT :: reserved1 [15:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_CRC_COUNT_reserved1_MASK 0x0000f000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_CRC_COUNT_reserved1_SHIFT 12
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: EDC_CRC_COUNT :: RD_COUNT [11:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_CRC_COUNT_RD_COUNT_MASK 0x00000fff
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_CRC_COUNT_RD_COUNT_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_CRC_COUNT_RD_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *EDC_CRC_STATUS_CLEAR - GDDR5M EDC signal path CRC counter register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_1_0 :: EDC_CRC_STATUS_CLEAR :: reserved0 [31:01] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_CRC_STATUS_CLEAR_reserved0_MASK 0xfffffffe
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_CRC_STATUS_CLEAR_reserved0_SHIFT 1
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: EDC_CRC_STATUS_CLEAR :: CLEAR [00:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_CRC_STATUS_CLEAR_CLEAR_MASK 0x00000001
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_CRC_STATUS_CLEAR_CLEAR_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_CRC_STATUS_CLEAR_CLEAR_DEFAULT 0x00000000
-
-/***************************************************************************
- *BL_SPARE_REG - Byte-Lane Spare register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_1_0 :: BL_SPARE_REG :: reserved_for_eco0 [31:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_BL_SPARE_REG_reserved_for_eco0_MASK 0xffffffff
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_BL_SPARE_REG_reserved_for_eco0_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_BL_SPARE_REG_reserved_for_eco0_DEFAULT 0x00000000
-
-#endif /* #ifndef BCHP_DDR34_PHY_BYTE_LANE_1_0_H__ */
-
-/* End of File */
diff --git a/include/linux/brcmstb/7145a0/bchp_ddr34_phy_byte_lane_1_1.h b/include/linux/brcmstb/7145a0/bchp_ddr34_phy_byte_lane_1_1.h
deleted file mode 100644
index 7b8a59f..0000000
--- a/include/linux/brcmstb/7145a0/bchp_ddr34_phy_byte_lane_1_1.h
+++ /dev/null
@@ -1,2101 +0,0 @@
-/***************************************************************************
- * Copyright (c) 1999-2014, Broadcom Corporation
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
- *
- * Module Description:
- * DO NOT EDIT THIS FILE DIRECTLY
- *
- * This module was generated magically with RDB from a source description
- * file. You must edit the source file for changes to be made to this file.
- *
- *
- * Date: Generated on Wed Sep 3 13:17:41 2014
- * Full Compile MD5 Checksum a8ee62ccf9dde43435c825f266da463d
- * (minus title and desc)
- * MD5 Checksum e373b364a1742e13a0f9eb15fd8aa94f
- *
- * Compiled with: RDB Utility combo_header.pl
- * RDB Parser 3.0
- * unknown unknown
- * Perl Interpreter 5.008005
- * Operating System linux
- *
- * Revision History:
- *
- * $brcm_Log: $
- *
- ***************************************************************************/
-
-#ifndef BCHP_DDR34_PHY_BYTE_LANE_1_1_H__
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_H__
-
-/***************************************************************************
- *DDR34_PHY_BYTE_LANE_1_1 - DDR34 Byte Lane #1 control registers
- ***************************************************************************/
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_WR_DQS_P 0x203c6600 /* Write channel DQS-P VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_WR_DQS_N 0x203c6604 /* Write channel DQS-N VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_WR_DQ0 0x203c6608 /* Write channel DQ0 VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_WR_DQ1 0x203c660c /* Write channel DQ1 VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_WR_DQ2 0x203c6610 /* Write channel DQ2 VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_WR_DQ3 0x203c6614 /* Write channel DQ3 VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_WR_DQ4 0x203c6618 /* Write channel DQ4 VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_WR_DQ5 0x203c661c /* Write channel DQ5 VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_WR_DQ6 0x203c6620 /* Write channel DQ6 VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_WR_DQ7 0x203c6624 /* Write channel DQ7 VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_WR_DM 0x203c6628 /* Write channel DM VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_WR_EDC 0x203c662c /* Write channel EDC VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQSP 0x203c6630 /* Read channel DQSP VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQSN 0x203c6634 /* Read channel DQSP VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ0P 0x203c6638 /* Read channel DQ0-P VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ0N 0x203c663c /* Read channel DQ0-N VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ1P 0x203c6640 /* Read channel DQ1-P VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ1N 0x203c6644 /* Read channel DQ1-N VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ2P 0x203c6648 /* Read channel DQ2-P VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ2N 0x203c664c /* Read channel DQ2-N VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ3P 0x203c6650 /* Read channel DQ3-P VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ3N 0x203c6654 /* Read channel DQ3-N VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ4P 0x203c6658 /* Read channel DQ4-P VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ4N 0x203c665c /* Read channel DQ4-N VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ5P 0x203c6660 /* Read channel DQ5-P VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ5N 0x203c6664 /* Read channel DQ5-N VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ6P 0x203c6668 /* Read channel DQ6-P VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ6N 0x203c666c /* Read channel DQ6-N VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ7P 0x203c6670 /* Read channel DQ7-P VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ7N 0x203c6674 /* Read channel DQ7-N VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DMP 0x203c6678 /* Read channel DM-P VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DMN 0x203c667c /* Read channel DM-N VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_EDCP 0x203c6680 /* Read channel EDC-P VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_EDCN 0x203c6684 /* Read channel EDC-N VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_EN_CS0 0x203c6688 /* Read channel CS_N[0] read enable VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_EN_CS1 0x203c668c /* Read channel CS_N[1] read enable VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CLK_CONTROL 0x203c6690 /* DDR interface signal Write Leveling CLK VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_LDE_CONTROL 0x203c6694 /* DDR interface signal Write Leveling Capture Enable VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_RD_EN_DLY_CYC 0x203c66a0 /* Read enable bit-clock cycle delay control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_WR_CHAN_DLY_CYC 0x203c66a4 /* Write leveling bit-clock cycle delay control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_READ_CONTROL 0x203c66b0 /* Read channel datapath control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_READ_FIFO_ADDR 0x203c66b4 /* Read fifo addresss pointer register */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_READ_FIFO_DATA 0x203c66b8 /* Read fifo data register */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_READ_FIFO_DM_DBI 0x203c66bc /* Read fifo dm/dbi register */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_READ_FIFO_STATUS 0x203c66c0 /* Read fifo status register */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_READ_FIFO_CLEAR 0x203c66c4 /* Read fifo status clear register */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_IDLE_PAD_CONTROL 0x203c66c8 /* Idle mode SSTL pad control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_DRIVE_PAD_CTL 0x203c66cc /* SSTL pad drive characteristics control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_RD_EN_DRIVE_PAD_CTL 0x203c66d0 /* SSTL read enable pad drive characteristics control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_STATIC_PAD_CTL 0x203c66d4 /* pad rx and tx characteristics control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_WR_PREAMBLE_MODE 0x203c66d8 /* Write cycle preamble control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_ODT_CONTROL 0x203c66e0 /* Read channel ODT control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_EDC_DPD_CONTROL 0x203c66f0 /* GDDR5M EDC digital phase detector control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_EDC_DPD_STATUS 0x203c66f4 /* GDDR5M EDC digital phase detector status register */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_EDC_DPD_OUT_CONTROL 0x203c66f8 /* GDDR5M EDC digital phase detector output signal control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_EDC_DPD_OUT_STATUS 0x203c66fc /* GDDR5M EDC digital phase detector output signal status register */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_EDC_DPD_OUT_STATUS_CLEAR 0x203c6700 /* GDDR5M EDC digital phase detector output signal status clear register */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_EDC_CRC_CONTROL 0x203c6704 /* GDDR5M EDC signal path CRC control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_EDC_CRC_STATUS 0x203c6708 /* GDDR5M EDC signal path CRC status register */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_EDC_CRC_COUNT 0x203c670c /* GDDR5M EDC signal path CRC counter register */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_EDC_CRC_STATUS_CLEAR 0x203c6710 /* GDDR5M EDC signal path CRC counter register */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_BL_SPARE_REG 0x203c6714 /* Byte-Lane Spare register */
-
-/***************************************************************************
- *VDL_CONTROL_WR_DQS_P - Write channel DQS-P VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_1_1 :: VDL_CONTROL_WR_DQS_P :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_WR_DQS_P_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_WR_DQS_P_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_WR_DQS_P_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_1 :: VDL_CONTROL_WR_DQS_P :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_WR_DQS_P_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_WR_DQS_P_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_1_1 :: VDL_CONTROL_WR_DQS_P :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_WR_DQS_P_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_WR_DQS_P_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_WR_DQS_P_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_1 :: VDL_CONTROL_WR_DQS_P :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_WR_DQS_P_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_WR_DQS_P_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_1_1 :: VDL_CONTROL_WR_DQS_P :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_WR_DQS_P_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_WR_DQS_P_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_WR_DQS_P_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_1 :: VDL_CONTROL_WR_DQS_P :: reserved2 [11:09] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_WR_DQS_P_reserved2_MASK 0x00000e00
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_WR_DQS_P_reserved2_SHIFT 9
-
-/* DDR34_PHY_BYTE_LANE_1_1 :: VDL_CONTROL_WR_DQS_P :: VDL_STEP [08:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_WR_DQS_P_VDL_STEP_MASK 0x000001ff
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_WR_DQS_P_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_WR_DQS_P_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_WR_DQS_N - Write channel DQS-N VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_1_1 :: VDL_CONTROL_WR_DQS_N :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_WR_DQS_N_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_WR_DQS_N_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_WR_DQS_N_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_1 :: VDL_CONTROL_WR_DQS_N :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_WR_DQS_N_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_WR_DQS_N_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_1_1 :: VDL_CONTROL_WR_DQS_N :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_WR_DQS_N_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_WR_DQS_N_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_WR_DQS_N_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_1 :: VDL_CONTROL_WR_DQS_N :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_WR_DQS_N_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_WR_DQS_N_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_1_1 :: VDL_CONTROL_WR_DQS_N :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_WR_DQS_N_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_WR_DQS_N_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_WR_DQS_N_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_1 :: VDL_CONTROL_WR_DQS_N :: reserved2 [11:09] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_WR_DQS_N_reserved2_MASK 0x00000e00
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_WR_DQS_N_reserved2_SHIFT 9
-
-/* DDR34_PHY_BYTE_LANE_1_1 :: VDL_CONTROL_WR_DQS_N :: VDL_STEP [08:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_WR_DQS_N_VDL_STEP_MASK 0x000001ff
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_WR_DQS_N_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_WR_DQS_N_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_WR_DQ0 - Write channel DQ0 VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_1_1 :: VDL_CONTROL_WR_DQ0 :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_WR_DQ0_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_WR_DQ0_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_WR_DQ0_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_1 :: VDL_CONTROL_WR_DQ0 :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_WR_DQ0_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_WR_DQ0_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_1_1 :: VDL_CONTROL_WR_DQ0 :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_WR_DQ0_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_WR_DQ0_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_WR_DQ0_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_1 :: VDL_CONTROL_WR_DQ0 :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_WR_DQ0_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_WR_DQ0_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_1_1 :: VDL_CONTROL_WR_DQ0 :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_WR_DQ0_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_WR_DQ0_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_WR_DQ0_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_1 :: VDL_CONTROL_WR_DQ0 :: reserved2 [11:09] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_WR_DQ0_reserved2_MASK 0x00000e00
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_WR_DQ0_reserved2_SHIFT 9
-
-/* DDR34_PHY_BYTE_LANE_1_1 :: VDL_CONTROL_WR_DQ0 :: VDL_STEP [08:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_WR_DQ0_VDL_STEP_MASK 0x000001ff
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_WR_DQ0_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_WR_DQ0_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_WR_DQ1 - Write channel DQ1 VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_1_1 :: VDL_CONTROL_WR_DQ1 :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_WR_DQ1_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_WR_DQ1_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_WR_DQ1_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_1 :: VDL_CONTROL_WR_DQ1 :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_WR_DQ1_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_WR_DQ1_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_1_1 :: VDL_CONTROL_WR_DQ1 :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_WR_DQ1_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_WR_DQ1_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_WR_DQ1_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_1 :: VDL_CONTROL_WR_DQ1 :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_WR_DQ1_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_WR_DQ1_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_1_1 :: VDL_CONTROL_WR_DQ1 :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_WR_DQ1_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_WR_DQ1_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_WR_DQ1_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_1 :: VDL_CONTROL_WR_DQ1 :: reserved2 [11:09] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_WR_DQ1_reserved2_MASK 0x00000e00
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_WR_DQ1_reserved2_SHIFT 9
-
-/* DDR34_PHY_BYTE_LANE_1_1 :: VDL_CONTROL_WR_DQ1 :: VDL_STEP [08:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_WR_DQ1_VDL_STEP_MASK 0x000001ff
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_WR_DQ1_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_WR_DQ1_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_WR_DQ2 - Write channel DQ2 VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_1_1 :: VDL_CONTROL_WR_DQ2 :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_WR_DQ2_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_WR_DQ2_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_WR_DQ2_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_1 :: VDL_CONTROL_WR_DQ2 :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_WR_DQ2_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_WR_DQ2_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_1_1 :: VDL_CONTROL_WR_DQ2 :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_WR_DQ2_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_WR_DQ2_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_WR_DQ2_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_1 :: VDL_CONTROL_WR_DQ2 :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_WR_DQ2_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_WR_DQ2_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_1_1 :: VDL_CONTROL_WR_DQ2 :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_WR_DQ2_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_WR_DQ2_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_WR_DQ2_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_1 :: VDL_CONTROL_WR_DQ2 :: reserved2 [11:09] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_WR_DQ2_reserved2_MASK 0x00000e00
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_WR_DQ2_reserved2_SHIFT 9
-
-/* DDR34_PHY_BYTE_LANE_1_1 :: VDL_CONTROL_WR_DQ2 :: VDL_STEP [08:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_WR_DQ2_VDL_STEP_MASK 0x000001ff
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_WR_DQ2_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_WR_DQ2_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_WR_DQ3 - Write channel DQ3 VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_1_1 :: VDL_CONTROL_WR_DQ3 :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_WR_DQ3_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_WR_DQ3_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_WR_DQ3_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_1 :: VDL_CONTROL_WR_DQ3 :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_WR_DQ3_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_WR_DQ3_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_1_1 :: VDL_CONTROL_WR_DQ3 :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_WR_DQ3_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_WR_DQ3_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_WR_DQ3_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_1 :: VDL_CONTROL_WR_DQ3 :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_WR_DQ3_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_WR_DQ3_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_1_1 :: VDL_CONTROL_WR_DQ3 :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_WR_DQ3_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_WR_DQ3_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_WR_DQ3_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_1 :: VDL_CONTROL_WR_DQ3 :: reserved2 [11:09] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_WR_DQ3_reserved2_MASK 0x00000e00
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_WR_DQ3_reserved2_SHIFT 9
-
-/* DDR34_PHY_BYTE_LANE_1_1 :: VDL_CONTROL_WR_DQ3 :: VDL_STEP [08:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_WR_DQ3_VDL_STEP_MASK 0x000001ff
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_WR_DQ3_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_WR_DQ3_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_WR_DQ4 - Write channel DQ4 VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_1_1 :: VDL_CONTROL_WR_DQ4 :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_WR_DQ4_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_WR_DQ4_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_WR_DQ4_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_1 :: VDL_CONTROL_WR_DQ4 :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_WR_DQ4_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_WR_DQ4_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_1_1 :: VDL_CONTROL_WR_DQ4 :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_WR_DQ4_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_WR_DQ4_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_WR_DQ4_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_1 :: VDL_CONTROL_WR_DQ4 :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_WR_DQ4_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_WR_DQ4_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_1_1 :: VDL_CONTROL_WR_DQ4 :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_WR_DQ4_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_WR_DQ4_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_WR_DQ4_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_1 :: VDL_CONTROL_WR_DQ4 :: reserved2 [11:09] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_WR_DQ4_reserved2_MASK 0x00000e00
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_WR_DQ4_reserved2_SHIFT 9
-
-/* DDR34_PHY_BYTE_LANE_1_1 :: VDL_CONTROL_WR_DQ4 :: VDL_STEP [08:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_WR_DQ4_VDL_STEP_MASK 0x000001ff
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_WR_DQ4_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_WR_DQ4_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_WR_DQ5 - Write channel DQ5 VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_1_1 :: VDL_CONTROL_WR_DQ5 :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_WR_DQ5_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_WR_DQ5_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_WR_DQ5_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_1 :: VDL_CONTROL_WR_DQ5 :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_WR_DQ5_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_WR_DQ5_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_1_1 :: VDL_CONTROL_WR_DQ5 :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_WR_DQ5_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_WR_DQ5_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_WR_DQ5_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_1 :: VDL_CONTROL_WR_DQ5 :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_WR_DQ5_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_WR_DQ5_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_1_1 :: VDL_CONTROL_WR_DQ5 :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_WR_DQ5_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_WR_DQ5_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_WR_DQ5_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_1 :: VDL_CONTROL_WR_DQ5 :: reserved2 [11:09] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_WR_DQ5_reserved2_MASK 0x00000e00
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_WR_DQ5_reserved2_SHIFT 9
-
-/* DDR34_PHY_BYTE_LANE_1_1 :: VDL_CONTROL_WR_DQ5 :: VDL_STEP [08:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_WR_DQ5_VDL_STEP_MASK 0x000001ff
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_WR_DQ5_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_WR_DQ5_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_WR_DQ6 - Write channel DQ6 VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_1_1 :: VDL_CONTROL_WR_DQ6 :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_WR_DQ6_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_WR_DQ6_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_WR_DQ6_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_1 :: VDL_CONTROL_WR_DQ6 :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_WR_DQ6_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_WR_DQ6_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_1_1 :: VDL_CONTROL_WR_DQ6 :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_WR_DQ6_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_WR_DQ6_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_WR_DQ6_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_1 :: VDL_CONTROL_WR_DQ6 :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_WR_DQ6_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_WR_DQ6_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_1_1 :: VDL_CONTROL_WR_DQ6 :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_WR_DQ6_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_WR_DQ6_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_WR_DQ6_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_1 :: VDL_CONTROL_WR_DQ6 :: reserved2 [11:09] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_WR_DQ6_reserved2_MASK 0x00000e00
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_WR_DQ6_reserved2_SHIFT 9
-
-/* DDR34_PHY_BYTE_LANE_1_1 :: VDL_CONTROL_WR_DQ6 :: VDL_STEP [08:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_WR_DQ6_VDL_STEP_MASK 0x000001ff
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_WR_DQ6_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_WR_DQ6_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_WR_DQ7 - Write channel DQ7 VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_1_1 :: VDL_CONTROL_WR_DQ7 :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_WR_DQ7_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_WR_DQ7_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_WR_DQ7_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_1 :: VDL_CONTROL_WR_DQ7 :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_WR_DQ7_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_WR_DQ7_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_1_1 :: VDL_CONTROL_WR_DQ7 :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_WR_DQ7_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_WR_DQ7_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_WR_DQ7_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_1 :: VDL_CONTROL_WR_DQ7 :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_WR_DQ7_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_WR_DQ7_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_1_1 :: VDL_CONTROL_WR_DQ7 :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_WR_DQ7_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_WR_DQ7_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_WR_DQ7_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_1 :: VDL_CONTROL_WR_DQ7 :: reserved2 [11:09] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_WR_DQ7_reserved2_MASK 0x00000e00
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_WR_DQ7_reserved2_SHIFT 9
-
-/* DDR34_PHY_BYTE_LANE_1_1 :: VDL_CONTROL_WR_DQ7 :: VDL_STEP [08:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_WR_DQ7_VDL_STEP_MASK 0x000001ff
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_WR_DQ7_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_WR_DQ7_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_WR_DM - Write channel DM VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_1_1 :: VDL_CONTROL_WR_DM :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_WR_DM_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_WR_DM_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_WR_DM_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_1 :: VDL_CONTROL_WR_DM :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_WR_DM_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_WR_DM_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_1_1 :: VDL_CONTROL_WR_DM :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_WR_DM_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_WR_DM_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_WR_DM_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_1 :: VDL_CONTROL_WR_DM :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_WR_DM_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_WR_DM_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_1_1 :: VDL_CONTROL_WR_DM :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_WR_DM_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_WR_DM_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_WR_DM_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_1 :: VDL_CONTROL_WR_DM :: reserved2 [11:09] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_WR_DM_reserved2_MASK 0x00000e00
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_WR_DM_reserved2_SHIFT 9
-
-/* DDR34_PHY_BYTE_LANE_1_1 :: VDL_CONTROL_WR_DM :: VDL_STEP [08:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_WR_DM_VDL_STEP_MASK 0x000001ff
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_WR_DM_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_WR_DM_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_WR_EDC - Write channel EDC VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_1_1 :: VDL_CONTROL_WR_EDC :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_WR_EDC_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_WR_EDC_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_WR_EDC_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_1 :: VDL_CONTROL_WR_EDC :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_WR_EDC_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_WR_EDC_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_1_1 :: VDL_CONTROL_WR_EDC :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_WR_EDC_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_WR_EDC_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_WR_EDC_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_1 :: VDL_CONTROL_WR_EDC :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_WR_EDC_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_WR_EDC_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_1_1 :: VDL_CONTROL_WR_EDC :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_WR_EDC_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_WR_EDC_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_WR_EDC_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_1 :: VDL_CONTROL_WR_EDC :: reserved2 [11:09] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_WR_EDC_reserved2_MASK 0x00000e00
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_WR_EDC_reserved2_SHIFT 9
-
-/* DDR34_PHY_BYTE_LANE_1_1 :: VDL_CONTROL_WR_EDC :: VDL_STEP [08:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_WR_EDC_VDL_STEP_MASK 0x000001ff
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_WR_EDC_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_WR_EDC_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_RD_DQSP - Read channel DQSP VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_1_1 :: VDL_CONTROL_RD_DQSP :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQSP_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQSP_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQSP_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_1 :: VDL_CONTROL_RD_DQSP :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQSP_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQSP_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_1_1 :: VDL_CONTROL_RD_DQSP :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQSP_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQSP_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQSP_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_1 :: VDL_CONTROL_RD_DQSP :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQSP_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQSP_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_1_1 :: VDL_CONTROL_RD_DQSP :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQSP_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQSP_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQSP_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_1 :: VDL_CONTROL_RD_DQSP :: reserved2 [11:08] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQSP_reserved2_MASK 0x00000f00
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQSP_reserved2_SHIFT 8
-
-/* DDR34_PHY_BYTE_LANE_1_1 :: VDL_CONTROL_RD_DQSP :: VDL_STEP [07:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQSP_VDL_STEP_MASK 0x000000ff
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQSP_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQSP_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_RD_DQSN - Read channel DQSP VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_1_1 :: VDL_CONTROL_RD_DQSN :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQSN_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQSN_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQSN_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_1 :: VDL_CONTROL_RD_DQSN :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQSN_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQSN_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_1_1 :: VDL_CONTROL_RD_DQSN :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQSN_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQSN_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQSN_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_1 :: VDL_CONTROL_RD_DQSN :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQSN_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQSN_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_1_1 :: VDL_CONTROL_RD_DQSN :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQSN_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQSN_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQSN_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_1 :: VDL_CONTROL_RD_DQSN :: reserved2 [11:08] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQSN_reserved2_MASK 0x00000f00
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQSN_reserved2_SHIFT 8
-
-/* DDR34_PHY_BYTE_LANE_1_1 :: VDL_CONTROL_RD_DQSN :: VDL_STEP [07:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQSN_VDL_STEP_MASK 0x000000ff
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQSN_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQSN_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_RD_DQ0P - Read channel DQ0-P VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_1_1 :: VDL_CONTROL_RD_DQ0P :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ0P_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ0P_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ0P_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_1 :: VDL_CONTROL_RD_DQ0P :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ0P_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ0P_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_1_1 :: VDL_CONTROL_RD_DQ0P :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ0P_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ0P_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ0P_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_1 :: VDL_CONTROL_RD_DQ0P :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ0P_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ0P_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_1_1 :: VDL_CONTROL_RD_DQ0P :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ0P_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ0P_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ0P_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_1 :: VDL_CONTROL_RD_DQ0P :: reserved2 [11:08] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ0P_reserved2_MASK 0x00000f00
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ0P_reserved2_SHIFT 8
-
-/* DDR34_PHY_BYTE_LANE_1_1 :: VDL_CONTROL_RD_DQ0P :: VDL_STEP [07:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ0P_VDL_STEP_MASK 0x000000ff
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ0P_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ0P_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_RD_DQ0N - Read channel DQ0-N VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_1_1 :: VDL_CONTROL_RD_DQ0N :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ0N_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ0N_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ0N_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_1 :: VDL_CONTROL_RD_DQ0N :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ0N_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ0N_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_1_1 :: VDL_CONTROL_RD_DQ0N :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ0N_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ0N_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ0N_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_1 :: VDL_CONTROL_RD_DQ0N :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ0N_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ0N_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_1_1 :: VDL_CONTROL_RD_DQ0N :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ0N_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ0N_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ0N_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_1 :: VDL_CONTROL_RD_DQ0N :: reserved2 [11:08] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ0N_reserved2_MASK 0x00000f00
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ0N_reserved2_SHIFT 8
-
-/* DDR34_PHY_BYTE_LANE_1_1 :: VDL_CONTROL_RD_DQ0N :: VDL_STEP [07:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ0N_VDL_STEP_MASK 0x000000ff
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ0N_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ0N_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_RD_DQ1P - Read channel DQ1-P VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_1_1 :: VDL_CONTROL_RD_DQ1P :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ1P_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ1P_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ1P_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_1 :: VDL_CONTROL_RD_DQ1P :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ1P_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ1P_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_1_1 :: VDL_CONTROL_RD_DQ1P :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ1P_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ1P_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ1P_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_1 :: VDL_CONTROL_RD_DQ1P :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ1P_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ1P_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_1_1 :: VDL_CONTROL_RD_DQ1P :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ1P_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ1P_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ1P_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_1 :: VDL_CONTROL_RD_DQ1P :: reserved2 [11:08] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ1P_reserved2_MASK 0x00000f00
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ1P_reserved2_SHIFT 8
-
-/* DDR34_PHY_BYTE_LANE_1_1 :: VDL_CONTROL_RD_DQ1P :: VDL_STEP [07:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ1P_VDL_STEP_MASK 0x000000ff
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ1P_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ1P_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_RD_DQ1N - Read channel DQ1-N VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_1_1 :: VDL_CONTROL_RD_DQ1N :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ1N_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ1N_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ1N_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_1 :: VDL_CONTROL_RD_DQ1N :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ1N_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ1N_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_1_1 :: VDL_CONTROL_RD_DQ1N :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ1N_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ1N_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ1N_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_1 :: VDL_CONTROL_RD_DQ1N :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ1N_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ1N_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_1_1 :: VDL_CONTROL_RD_DQ1N :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ1N_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ1N_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ1N_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_1 :: VDL_CONTROL_RD_DQ1N :: reserved2 [11:08] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ1N_reserved2_MASK 0x00000f00
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ1N_reserved2_SHIFT 8
-
-/* DDR34_PHY_BYTE_LANE_1_1 :: VDL_CONTROL_RD_DQ1N :: VDL_STEP [07:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ1N_VDL_STEP_MASK 0x000000ff
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ1N_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ1N_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_RD_DQ2P - Read channel DQ2-P VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_1_1 :: VDL_CONTROL_RD_DQ2P :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ2P_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ2P_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ2P_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_1 :: VDL_CONTROL_RD_DQ2P :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ2P_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ2P_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_1_1 :: VDL_CONTROL_RD_DQ2P :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ2P_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ2P_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ2P_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_1 :: VDL_CONTROL_RD_DQ2P :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ2P_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ2P_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_1_1 :: VDL_CONTROL_RD_DQ2P :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ2P_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ2P_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ2P_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_1 :: VDL_CONTROL_RD_DQ2P :: reserved2 [11:08] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ2P_reserved2_MASK 0x00000f00
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ2P_reserved2_SHIFT 8
-
-/* DDR34_PHY_BYTE_LANE_1_1 :: VDL_CONTROL_RD_DQ2P :: VDL_STEP [07:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ2P_VDL_STEP_MASK 0x000000ff
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ2P_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ2P_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_RD_DQ2N - Read channel DQ2-N VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_1_1 :: VDL_CONTROL_RD_DQ2N :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ2N_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ2N_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ2N_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_1 :: VDL_CONTROL_RD_DQ2N :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ2N_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ2N_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_1_1 :: VDL_CONTROL_RD_DQ2N :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ2N_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ2N_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ2N_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_1 :: VDL_CONTROL_RD_DQ2N :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ2N_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ2N_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_1_1 :: VDL_CONTROL_RD_DQ2N :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ2N_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ2N_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ2N_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_1 :: VDL_CONTROL_RD_DQ2N :: reserved2 [11:08] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ2N_reserved2_MASK 0x00000f00
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ2N_reserved2_SHIFT 8
-
-/* DDR34_PHY_BYTE_LANE_1_1 :: VDL_CONTROL_RD_DQ2N :: VDL_STEP [07:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ2N_VDL_STEP_MASK 0x000000ff
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ2N_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ2N_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_RD_DQ3P - Read channel DQ3-P VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_1_1 :: VDL_CONTROL_RD_DQ3P :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ3P_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ3P_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ3P_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_1 :: VDL_CONTROL_RD_DQ3P :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ3P_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ3P_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_1_1 :: VDL_CONTROL_RD_DQ3P :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ3P_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ3P_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ3P_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_1 :: VDL_CONTROL_RD_DQ3P :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ3P_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ3P_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_1_1 :: VDL_CONTROL_RD_DQ3P :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ3P_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ3P_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ3P_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_1 :: VDL_CONTROL_RD_DQ3P :: reserved2 [11:08] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ3P_reserved2_MASK 0x00000f00
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ3P_reserved2_SHIFT 8
-
-/* DDR34_PHY_BYTE_LANE_1_1 :: VDL_CONTROL_RD_DQ3P :: VDL_STEP [07:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ3P_VDL_STEP_MASK 0x000000ff
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ3P_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ3P_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_RD_DQ3N - Read channel DQ3-N VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_1_1 :: VDL_CONTROL_RD_DQ3N :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ3N_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ3N_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ3N_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_1 :: VDL_CONTROL_RD_DQ3N :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ3N_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ3N_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_1_1 :: VDL_CONTROL_RD_DQ3N :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ3N_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ3N_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ3N_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_1 :: VDL_CONTROL_RD_DQ3N :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ3N_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ3N_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_1_1 :: VDL_CONTROL_RD_DQ3N :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ3N_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ3N_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ3N_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_1 :: VDL_CONTROL_RD_DQ3N :: reserved2 [11:08] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ3N_reserved2_MASK 0x00000f00
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ3N_reserved2_SHIFT 8
-
-/* DDR34_PHY_BYTE_LANE_1_1 :: VDL_CONTROL_RD_DQ3N :: VDL_STEP [07:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ3N_VDL_STEP_MASK 0x000000ff
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ3N_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ3N_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_RD_DQ4P - Read channel DQ4-P VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_1_1 :: VDL_CONTROL_RD_DQ4P :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ4P_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ4P_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ4P_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_1 :: VDL_CONTROL_RD_DQ4P :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ4P_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ4P_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_1_1 :: VDL_CONTROL_RD_DQ4P :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ4P_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ4P_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ4P_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_1 :: VDL_CONTROL_RD_DQ4P :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ4P_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ4P_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_1_1 :: VDL_CONTROL_RD_DQ4P :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ4P_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ4P_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ4P_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_1 :: VDL_CONTROL_RD_DQ4P :: reserved2 [11:08] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ4P_reserved2_MASK 0x00000f00
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ4P_reserved2_SHIFT 8
-
-/* DDR34_PHY_BYTE_LANE_1_1 :: VDL_CONTROL_RD_DQ4P :: VDL_STEP [07:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ4P_VDL_STEP_MASK 0x000000ff
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ4P_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ4P_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_RD_DQ4N - Read channel DQ4-N VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_1_1 :: VDL_CONTROL_RD_DQ4N :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ4N_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ4N_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ4N_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_1 :: VDL_CONTROL_RD_DQ4N :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ4N_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ4N_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_1_1 :: VDL_CONTROL_RD_DQ4N :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ4N_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ4N_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ4N_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_1 :: VDL_CONTROL_RD_DQ4N :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ4N_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ4N_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_1_1 :: VDL_CONTROL_RD_DQ4N :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ4N_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ4N_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ4N_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_1 :: VDL_CONTROL_RD_DQ4N :: reserved2 [11:08] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ4N_reserved2_MASK 0x00000f00
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ4N_reserved2_SHIFT 8
-
-/* DDR34_PHY_BYTE_LANE_1_1 :: VDL_CONTROL_RD_DQ4N :: VDL_STEP [07:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ4N_VDL_STEP_MASK 0x000000ff
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ4N_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ4N_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_RD_DQ5P - Read channel DQ5-P VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_1_1 :: VDL_CONTROL_RD_DQ5P :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ5P_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ5P_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ5P_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_1 :: VDL_CONTROL_RD_DQ5P :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ5P_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ5P_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_1_1 :: VDL_CONTROL_RD_DQ5P :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ5P_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ5P_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ5P_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_1 :: VDL_CONTROL_RD_DQ5P :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ5P_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ5P_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_1_1 :: VDL_CONTROL_RD_DQ5P :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ5P_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ5P_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ5P_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_1 :: VDL_CONTROL_RD_DQ5P :: reserved2 [11:08] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ5P_reserved2_MASK 0x00000f00
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ5P_reserved2_SHIFT 8
-
-/* DDR34_PHY_BYTE_LANE_1_1 :: VDL_CONTROL_RD_DQ5P :: VDL_STEP [07:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ5P_VDL_STEP_MASK 0x000000ff
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ5P_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ5P_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_RD_DQ5N - Read channel DQ5-N VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_1_1 :: VDL_CONTROL_RD_DQ5N :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ5N_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ5N_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ5N_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_1 :: VDL_CONTROL_RD_DQ5N :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ5N_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ5N_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_1_1 :: VDL_CONTROL_RD_DQ5N :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ5N_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ5N_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ5N_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_1 :: VDL_CONTROL_RD_DQ5N :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ5N_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ5N_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_1_1 :: VDL_CONTROL_RD_DQ5N :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ5N_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ5N_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ5N_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_1 :: VDL_CONTROL_RD_DQ5N :: reserved2 [11:08] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ5N_reserved2_MASK 0x00000f00
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ5N_reserved2_SHIFT 8
-
-/* DDR34_PHY_BYTE_LANE_1_1 :: VDL_CONTROL_RD_DQ5N :: VDL_STEP [07:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ5N_VDL_STEP_MASK 0x000000ff
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ5N_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ5N_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_RD_DQ6P - Read channel DQ6-P VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_1_1 :: VDL_CONTROL_RD_DQ6P :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ6P_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ6P_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ6P_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_1 :: VDL_CONTROL_RD_DQ6P :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ6P_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ6P_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_1_1 :: VDL_CONTROL_RD_DQ6P :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ6P_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ6P_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ6P_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_1 :: VDL_CONTROL_RD_DQ6P :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ6P_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ6P_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_1_1 :: VDL_CONTROL_RD_DQ6P :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ6P_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ6P_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ6P_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_1 :: VDL_CONTROL_RD_DQ6P :: reserved2 [11:08] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ6P_reserved2_MASK 0x00000f00
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ6P_reserved2_SHIFT 8
-
-/* DDR34_PHY_BYTE_LANE_1_1 :: VDL_CONTROL_RD_DQ6P :: VDL_STEP [07:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ6P_VDL_STEP_MASK 0x000000ff
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ6P_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ6P_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_RD_DQ6N - Read channel DQ6-N VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_1_1 :: VDL_CONTROL_RD_DQ6N :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ6N_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ6N_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ6N_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_1 :: VDL_CONTROL_RD_DQ6N :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ6N_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ6N_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_1_1 :: VDL_CONTROL_RD_DQ6N :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ6N_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ6N_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ6N_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_1 :: VDL_CONTROL_RD_DQ6N :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ6N_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ6N_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_1_1 :: VDL_CONTROL_RD_DQ6N :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ6N_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ6N_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ6N_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_1 :: VDL_CONTROL_RD_DQ6N :: reserved2 [11:08] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ6N_reserved2_MASK 0x00000f00
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ6N_reserved2_SHIFT 8
-
-/* DDR34_PHY_BYTE_LANE_1_1 :: VDL_CONTROL_RD_DQ6N :: VDL_STEP [07:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ6N_VDL_STEP_MASK 0x000000ff
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ6N_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ6N_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_RD_DQ7P - Read channel DQ7-P VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_1_1 :: VDL_CONTROL_RD_DQ7P :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ7P_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ7P_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ7P_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_1 :: VDL_CONTROL_RD_DQ7P :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ7P_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ7P_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_1_1 :: VDL_CONTROL_RD_DQ7P :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ7P_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ7P_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ7P_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_1 :: VDL_CONTROL_RD_DQ7P :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ7P_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ7P_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_1_1 :: VDL_CONTROL_RD_DQ7P :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ7P_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ7P_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ7P_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_1 :: VDL_CONTROL_RD_DQ7P :: reserved2 [11:08] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ7P_reserved2_MASK 0x00000f00
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ7P_reserved2_SHIFT 8
-
-/* DDR34_PHY_BYTE_LANE_1_1 :: VDL_CONTROL_RD_DQ7P :: VDL_STEP [07:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ7P_VDL_STEP_MASK 0x000000ff
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ7P_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ7P_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_RD_DQ7N - Read channel DQ7-N VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_1_1 :: VDL_CONTROL_RD_DQ7N :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ7N_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ7N_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ7N_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_1 :: VDL_CONTROL_RD_DQ7N :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ7N_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ7N_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_1_1 :: VDL_CONTROL_RD_DQ7N :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ7N_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ7N_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ7N_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_1 :: VDL_CONTROL_RD_DQ7N :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ7N_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ7N_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_1_1 :: VDL_CONTROL_RD_DQ7N :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ7N_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ7N_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ7N_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_1 :: VDL_CONTROL_RD_DQ7N :: reserved2 [11:08] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ7N_reserved2_MASK 0x00000f00
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ7N_reserved2_SHIFT 8
-
-/* DDR34_PHY_BYTE_LANE_1_1 :: VDL_CONTROL_RD_DQ7N :: VDL_STEP [07:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ7N_VDL_STEP_MASK 0x000000ff
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ7N_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ7N_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_RD_DMP - Read channel DM-P VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_1_1 :: VDL_CONTROL_RD_DMP :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DMP_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DMP_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DMP_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_1 :: VDL_CONTROL_RD_DMP :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DMP_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DMP_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_1_1 :: VDL_CONTROL_RD_DMP :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DMP_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DMP_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DMP_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_1 :: VDL_CONTROL_RD_DMP :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DMP_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DMP_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_1_1 :: VDL_CONTROL_RD_DMP :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DMP_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DMP_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DMP_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_1 :: VDL_CONTROL_RD_DMP :: reserved2 [11:08] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DMP_reserved2_MASK 0x00000f00
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DMP_reserved2_SHIFT 8
-
-/* DDR34_PHY_BYTE_LANE_1_1 :: VDL_CONTROL_RD_DMP :: VDL_STEP [07:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DMP_VDL_STEP_MASK 0x000000ff
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DMP_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DMP_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_RD_DMN - Read channel DM-N VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_1_1 :: VDL_CONTROL_RD_DMN :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DMN_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DMN_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DMN_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_1 :: VDL_CONTROL_RD_DMN :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DMN_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DMN_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_1_1 :: VDL_CONTROL_RD_DMN :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DMN_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DMN_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DMN_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_1 :: VDL_CONTROL_RD_DMN :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DMN_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DMN_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_1_1 :: VDL_CONTROL_RD_DMN :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DMN_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DMN_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DMN_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_1 :: VDL_CONTROL_RD_DMN :: reserved2 [11:08] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DMN_reserved2_MASK 0x00000f00
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DMN_reserved2_SHIFT 8
-
-/* DDR34_PHY_BYTE_LANE_1_1 :: VDL_CONTROL_RD_DMN :: VDL_STEP [07:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DMN_VDL_STEP_MASK 0x000000ff
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DMN_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DMN_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_RD_EDCP - Read channel EDC-P VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_1_1 :: VDL_CONTROL_RD_EDCP :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_EDCP_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_EDCP_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_EDCP_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_1 :: VDL_CONTROL_RD_EDCP :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_EDCP_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_EDCP_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_1_1 :: VDL_CONTROL_RD_EDCP :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_EDCP_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_EDCP_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_EDCP_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_1 :: VDL_CONTROL_RD_EDCP :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_EDCP_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_EDCP_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_1_1 :: VDL_CONTROL_RD_EDCP :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_EDCP_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_EDCP_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_EDCP_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_1 :: VDL_CONTROL_RD_EDCP :: reserved2 [11:08] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_EDCP_reserved2_MASK 0x00000f00
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_EDCP_reserved2_SHIFT 8
-
-/* DDR34_PHY_BYTE_LANE_1_1 :: VDL_CONTROL_RD_EDCP :: VDL_STEP [07:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_EDCP_VDL_STEP_MASK 0x000000ff
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_EDCP_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_EDCP_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_RD_EDCN - Read channel EDC-N VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_1_1 :: VDL_CONTROL_RD_EDCN :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_EDCN_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_EDCN_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_EDCN_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_1 :: VDL_CONTROL_RD_EDCN :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_EDCN_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_EDCN_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_1_1 :: VDL_CONTROL_RD_EDCN :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_EDCN_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_EDCN_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_EDCN_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_1 :: VDL_CONTROL_RD_EDCN :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_EDCN_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_EDCN_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_1_1 :: VDL_CONTROL_RD_EDCN :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_EDCN_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_EDCN_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_EDCN_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_1 :: VDL_CONTROL_RD_EDCN :: reserved2 [11:08] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_EDCN_reserved2_MASK 0x00000f00
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_EDCN_reserved2_SHIFT 8
-
-/* DDR34_PHY_BYTE_LANE_1_1 :: VDL_CONTROL_RD_EDCN :: VDL_STEP [07:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_EDCN_VDL_STEP_MASK 0x000000ff
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_EDCN_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_EDCN_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_RD_EN_CS0 - Read channel CS_N[0] read enable VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_1_1 :: VDL_CONTROL_RD_EN_CS0 :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_EN_CS0_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_EN_CS0_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_EN_CS0_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_1 :: VDL_CONTROL_RD_EN_CS0 :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_EN_CS0_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_EN_CS0_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_1_1 :: VDL_CONTROL_RD_EN_CS0 :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_EN_CS0_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_EN_CS0_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_EN_CS0_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_1 :: VDL_CONTROL_RD_EN_CS0 :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_EN_CS0_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_EN_CS0_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_1_1 :: VDL_CONTROL_RD_EN_CS0 :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_EN_CS0_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_EN_CS0_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_EN_CS0_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_1 :: VDL_CONTROL_RD_EN_CS0 :: reserved2 [11:08] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_EN_CS0_reserved2_MASK 0x00000f00
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_EN_CS0_reserved2_SHIFT 8
-
-/* DDR34_PHY_BYTE_LANE_1_1 :: VDL_CONTROL_RD_EN_CS0 :: VDL_STEP [07:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_EN_CS0_VDL_STEP_MASK 0x000000ff
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_EN_CS0_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_EN_CS0_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_RD_EN_CS1 - Read channel CS_N[1] read enable VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_1_1 :: VDL_CONTROL_RD_EN_CS1 :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_EN_CS1_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_EN_CS1_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_EN_CS1_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_1 :: VDL_CONTROL_RD_EN_CS1 :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_EN_CS1_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_EN_CS1_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_1_1 :: VDL_CONTROL_RD_EN_CS1 :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_EN_CS1_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_EN_CS1_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_EN_CS1_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_1 :: VDL_CONTROL_RD_EN_CS1 :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_EN_CS1_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_EN_CS1_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_1_1 :: VDL_CONTROL_RD_EN_CS1 :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_EN_CS1_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_EN_CS1_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_EN_CS1_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_1 :: VDL_CONTROL_RD_EN_CS1 :: reserved2 [11:08] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_EN_CS1_reserved2_MASK 0x00000f00
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_EN_CS1_reserved2_SHIFT 8
-
-/* DDR34_PHY_BYTE_LANE_1_1 :: VDL_CONTROL_RD_EN_CS1 :: VDL_STEP [07:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_EN_CS1_VDL_STEP_MASK 0x000000ff
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_EN_CS1_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_EN_CS1_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CLK_CONTROL - DDR interface signal Write Leveling CLK VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_1_1 :: VDL_CLK_CONTROL :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CLK_CONTROL_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CLK_CONTROL_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CLK_CONTROL_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_1 :: VDL_CLK_CONTROL :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CLK_CONTROL_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CLK_CONTROL_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_1_1 :: VDL_CLK_CONTROL :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CLK_CONTROL_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CLK_CONTROL_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CLK_CONTROL_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_1 :: VDL_CLK_CONTROL :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CLK_CONTROL_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CLK_CONTROL_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_1_1 :: VDL_CLK_CONTROL :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CLK_CONTROL_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CLK_CONTROL_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CLK_CONTROL_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_1 :: VDL_CLK_CONTROL :: reserved2 [11:09] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CLK_CONTROL_reserved2_MASK 0x00000e00
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CLK_CONTROL_reserved2_SHIFT 9
-
-/* DDR34_PHY_BYTE_LANE_1_1 :: VDL_CLK_CONTROL :: VDL_STEP [08:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CLK_CONTROL_VDL_STEP_MASK 0x000001ff
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CLK_CONTROL_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CLK_CONTROL_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_LDE_CONTROL - DDR interface signal Write Leveling Capture Enable VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_1_1 :: VDL_LDE_CONTROL :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_LDE_CONTROL_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_LDE_CONTROL_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_LDE_CONTROL_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_1 :: VDL_LDE_CONTROL :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_LDE_CONTROL_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_LDE_CONTROL_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_1_1 :: VDL_LDE_CONTROL :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_LDE_CONTROL_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_LDE_CONTROL_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_LDE_CONTROL_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_1 :: VDL_LDE_CONTROL :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_LDE_CONTROL_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_LDE_CONTROL_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_1_1 :: VDL_LDE_CONTROL :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_LDE_CONTROL_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_LDE_CONTROL_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_LDE_CONTROL_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_1 :: VDL_LDE_CONTROL :: reserved2 [11:09] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_LDE_CONTROL_reserved2_MASK 0x00000e00
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_LDE_CONTROL_reserved2_SHIFT 9
-
-/* DDR34_PHY_BYTE_LANE_1_1 :: VDL_LDE_CONTROL :: VDL_STEP [08:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_LDE_CONTROL_VDL_STEP_MASK 0x000001ff
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_LDE_CONTROL_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_LDE_CONTROL_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *RD_EN_DLY_CYC - Read enable bit-clock cycle delay control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_1_1 :: RD_EN_DLY_CYC :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_RD_EN_DLY_CYC_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_RD_EN_DLY_CYC_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_RD_EN_DLY_CYC_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_1 :: RD_EN_DLY_CYC :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_RD_EN_DLY_CYC_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_RD_EN_DLY_CYC_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_1_1 :: RD_EN_DLY_CYC :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_RD_EN_DLY_CYC_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_RD_EN_DLY_CYC_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_RD_EN_DLY_CYC_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_1 :: RD_EN_DLY_CYC :: reserved1 [15:08] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_RD_EN_DLY_CYC_reserved1_MASK 0x0000ff00
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_RD_EN_DLY_CYC_reserved1_SHIFT 8
-
-/* DDR34_PHY_BYTE_LANE_1_1 :: RD_EN_DLY_CYC :: CS1_CYCLES [07:04] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_RD_EN_DLY_CYC_CS1_CYCLES_MASK 0x000000f0
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_RD_EN_DLY_CYC_CS1_CYCLES_SHIFT 4
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_RD_EN_DLY_CYC_CS1_CYCLES_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_1 :: RD_EN_DLY_CYC :: CS0_CYCLES [03:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_RD_EN_DLY_CYC_CS0_CYCLES_MASK 0x0000000f
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_RD_EN_DLY_CYC_CS0_CYCLES_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_RD_EN_DLY_CYC_CS0_CYCLES_DEFAULT 0x00000000
-
-/***************************************************************************
- *WR_CHAN_DLY_CYC - Write leveling bit-clock cycle delay control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_1_1 :: WR_CHAN_DLY_CYC :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_WR_CHAN_DLY_CYC_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_WR_CHAN_DLY_CYC_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_WR_CHAN_DLY_CYC_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_1 :: WR_CHAN_DLY_CYC :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_WR_CHAN_DLY_CYC_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_WR_CHAN_DLY_CYC_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_1_1 :: WR_CHAN_DLY_CYC :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_WR_CHAN_DLY_CYC_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_WR_CHAN_DLY_CYC_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_WR_CHAN_DLY_CYC_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_1 :: WR_CHAN_DLY_CYC :: reserved1 [15:03] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_WR_CHAN_DLY_CYC_reserved1_MASK 0x0000fff8
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_WR_CHAN_DLY_CYC_reserved1_SHIFT 3
-
-/* DDR34_PHY_BYTE_LANE_1_1 :: WR_CHAN_DLY_CYC :: CYCLES [02:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_WR_CHAN_DLY_CYC_CYCLES_MASK 0x00000007
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_WR_CHAN_DLY_CYC_CYCLES_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_WR_CHAN_DLY_CYC_CYCLES_DEFAULT 0x00000000
-
-/***************************************************************************
- *READ_CONTROL - Read channel datapath control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_1_1 :: READ_CONTROL :: reserved0 [31:05] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_READ_CONTROL_reserved0_MASK 0xffffffe0
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_READ_CONTROL_reserved0_SHIFT 5
-
-/* DDR34_PHY_BYTE_LANE_1_1 :: READ_CONTROL :: MODE [04:04] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_READ_CONTROL_MODE_MASK 0x00000010
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_READ_CONTROL_MODE_SHIFT 4
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_READ_CONTROL_MODE_DEFAULT 0x00000001
-
-/* DDR34_PHY_BYTE_LANE_1_1 :: READ_CONTROL :: reserved1 [03:03] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_READ_CONTROL_reserved1_MASK 0x00000008
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_READ_CONTROL_reserved1_SHIFT 3
-
-/* DDR34_PHY_BYTE_LANE_1_1 :: READ_CONTROL :: RD_DATA_DLY [02:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_READ_CONTROL_RD_DATA_DLY_MASK 0x00000007
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_READ_CONTROL_RD_DATA_DLY_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_READ_CONTROL_RD_DATA_DLY_DEFAULT 0x00000007
-
-/***************************************************************************
- *READ_FIFO_ADDR - Read fifo addresss pointer register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_1_1 :: READ_FIFO_ADDR :: reserved0 [31:03] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_READ_FIFO_ADDR_reserved0_MASK 0xfffffff8
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_READ_FIFO_ADDR_reserved0_SHIFT 3
-
-/* DDR34_PHY_BYTE_LANE_1_1 :: READ_FIFO_ADDR :: ADDR [02:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_READ_FIFO_ADDR_ADDR_MASK 0x00000007
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_READ_FIFO_ADDR_ADDR_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_READ_FIFO_ADDR_ADDR_DEFAULT 0x00000000
-
-/***************************************************************************
- *READ_FIFO_DATA - Read fifo data register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_1_1 :: READ_FIFO_DATA :: DATA [31:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_READ_FIFO_DATA_DATA_MASK 0xffffffff
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_READ_FIFO_DATA_DATA_SHIFT 0
-
-/***************************************************************************
- *READ_FIFO_DM_DBI - Read fifo dm/dbi register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_1_1 :: READ_FIFO_DM_DBI :: reserved0 [31:04] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_READ_FIFO_DM_DBI_reserved0_MASK 0xfffffff0
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_READ_FIFO_DM_DBI_reserved0_SHIFT 4
-
-/* DDR34_PHY_BYTE_LANE_1_1 :: READ_FIFO_DM_DBI :: DM_DBI [03:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_READ_FIFO_DM_DBI_DM_DBI_MASK 0x0000000f
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_READ_FIFO_DM_DBI_DM_DBI_SHIFT 0
-
-/***************************************************************************
- *READ_FIFO_STATUS - Read fifo status register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_1_1 :: READ_FIFO_STATUS :: reserved0 [31:02] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_READ_FIFO_STATUS_reserved0_MASK 0xfffffffc
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_READ_FIFO_STATUS_reserved0_SHIFT 2
-
-/* DDR34_PHY_BYTE_LANE_1_1 :: READ_FIFO_STATUS :: OVERFLOW [01:01] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_READ_FIFO_STATUS_OVERFLOW_MASK 0x00000002
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_READ_FIFO_STATUS_OVERFLOW_SHIFT 1
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_READ_FIFO_STATUS_OVERFLOW_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_1 :: READ_FIFO_STATUS :: UNDERFLOW [00:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_READ_FIFO_STATUS_UNDERFLOW_MASK 0x00000001
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_READ_FIFO_STATUS_UNDERFLOW_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_READ_FIFO_STATUS_UNDERFLOW_DEFAULT 0x00000000
-
-/***************************************************************************
- *READ_FIFO_CLEAR - Read fifo status clear register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_1_1 :: READ_FIFO_CLEAR :: reserved0 [31:01] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_READ_FIFO_CLEAR_reserved0_MASK 0xfffffffe
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_READ_FIFO_CLEAR_reserved0_SHIFT 1
-
-/* DDR34_PHY_BYTE_LANE_1_1 :: READ_FIFO_CLEAR :: CLEAR [00:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_READ_FIFO_CLEAR_CLEAR_MASK 0x00000001
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_READ_FIFO_CLEAR_CLEAR_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_READ_FIFO_CLEAR_CLEAR_DEFAULT 0x00000000
-
-/***************************************************************************
- *IDLE_PAD_CONTROL - Idle mode SSTL pad control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_1_1 :: IDLE_PAD_CONTROL :: IDLE [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_IDLE_PAD_CONTROL_IDLE_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_IDLE_PAD_CONTROL_IDLE_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_IDLE_PAD_CONTROL_IDLE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_1 :: IDLE_PAD_CONTROL :: reserved0 [30:20] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_IDLE_PAD_CONTROL_reserved0_MASK 0x7ff00000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_IDLE_PAD_CONTROL_reserved0_SHIFT 20
-
-/* DDR34_PHY_BYTE_LANE_1_1 :: IDLE_PAD_CONTROL :: AUTO_DQ_RXENB_MODE [19:18] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_IDLE_PAD_CONTROL_AUTO_DQ_RXENB_MODE_MASK 0x000c0000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_IDLE_PAD_CONTROL_AUTO_DQ_RXENB_MODE_SHIFT 18
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_IDLE_PAD_CONTROL_AUTO_DQ_RXENB_MODE_DEFAULT 0x00000001
-
-/* DDR34_PHY_BYTE_LANE_1_1 :: IDLE_PAD_CONTROL :: AUTO_DQ_IDDQ_MODE [17:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_IDLE_PAD_CONTROL_AUTO_DQ_IDDQ_MODE_MASK 0x00030000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_IDLE_PAD_CONTROL_AUTO_DQ_IDDQ_MODE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_IDLE_PAD_CONTROL_AUTO_DQ_IDDQ_MODE_DEFAULT 0x00000001
-
-/* DDR34_PHY_BYTE_LANE_1_1 :: IDLE_PAD_CONTROL :: reserved_for_padding1 [15:15] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_IDLE_PAD_CONTROL_reserved_for_padding1_MASK 0x00008000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_IDLE_PAD_CONTROL_reserved_for_padding1_SHIFT 15
-
-/* DDR34_PHY_BYTE_LANE_1_1 :: IDLE_PAD_CONTROL :: IO_IDLE_ENABLE [14:04] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_IDLE_PAD_CONTROL_IO_IDLE_ENABLE_MASK 0x00007ff0
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_IDLE_PAD_CONTROL_IO_IDLE_ENABLE_SHIFT 4
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_IDLE_PAD_CONTROL_IO_IDLE_ENABLE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_1 :: IDLE_PAD_CONTROL :: RXENB [03:03] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_IDLE_PAD_CONTROL_RXENB_MASK 0x00000008
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_IDLE_PAD_CONTROL_RXENB_SHIFT 3
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_IDLE_PAD_CONTROL_RXENB_DEFAULT 0x00000001
-
-/* DDR34_PHY_BYTE_LANE_1_1 :: IDLE_PAD_CONTROL :: IDDQ [02:02] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_IDLE_PAD_CONTROL_IDDQ_MASK 0x00000004
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_IDLE_PAD_CONTROL_IDDQ_SHIFT 2
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_IDLE_PAD_CONTROL_IDDQ_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_1 :: IDLE_PAD_CONTROL :: DOUT_N [01:01] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_IDLE_PAD_CONTROL_DOUT_N_MASK 0x00000002
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_IDLE_PAD_CONTROL_DOUT_N_SHIFT 1
-
-/* DDR34_PHY_BYTE_LANE_1_1 :: IDLE_PAD_CONTROL :: DOUT_P [00:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_IDLE_PAD_CONTROL_DOUT_P_MASK 0x00000001
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_IDLE_PAD_CONTROL_DOUT_P_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_IDLE_PAD_CONTROL_DOUT_P_DEFAULT 0x00000000
-
-/***************************************************************************
- *DRIVE_PAD_CTL - SSTL pad drive characteristics control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_1_1 :: DRIVE_PAD_CTL :: reserved0 [31:30] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_DRIVE_PAD_CTL_reserved0_MASK 0xc0000000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_DRIVE_PAD_CTL_reserved0_SHIFT 30
-
-/* DDR34_PHY_BYTE_LANE_1_1 :: DRIVE_PAD_CTL :: BL_PD_IDLE_STRENGTH [29:25] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_DRIVE_PAD_CTL_BL_PD_IDLE_STRENGTH_MASK 0x3e000000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_DRIVE_PAD_CTL_BL_PD_IDLE_STRENGTH_SHIFT 25
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_DRIVE_PAD_CTL_BL_PD_IDLE_STRENGTH_DEFAULT 0x0000001f
-
-/* DDR34_PHY_BYTE_LANE_1_1 :: DRIVE_PAD_CTL :: BL_ND_IDLE_STRENGTH [24:20] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_DRIVE_PAD_CTL_BL_ND_IDLE_STRENGTH_MASK 0x01f00000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_DRIVE_PAD_CTL_BL_ND_IDLE_STRENGTH_SHIFT 20
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_DRIVE_PAD_CTL_BL_ND_IDLE_STRENGTH_DEFAULT 0x0000001f
-
-/* DDR34_PHY_BYTE_LANE_1_1 :: DRIVE_PAD_CTL :: BL_PD_TERM_STRENGTH [19:15] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_DRIVE_PAD_CTL_BL_PD_TERM_STRENGTH_MASK 0x000f8000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_DRIVE_PAD_CTL_BL_PD_TERM_STRENGTH_SHIFT 15
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_DRIVE_PAD_CTL_BL_PD_TERM_STRENGTH_DEFAULT 0x00000008
-
-/* DDR34_PHY_BYTE_LANE_1_1 :: DRIVE_PAD_CTL :: BL_ND_TERM_STRENGTH [14:10] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_DRIVE_PAD_CTL_BL_ND_TERM_STRENGTH_MASK 0x00007c00
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_DRIVE_PAD_CTL_BL_ND_TERM_STRENGTH_SHIFT 10
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_DRIVE_PAD_CTL_BL_ND_TERM_STRENGTH_DEFAULT 0x00000008
-
-/* DDR34_PHY_BYTE_LANE_1_1 :: DRIVE_PAD_CTL :: BL_PD_STRENGTH [09:05] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_DRIVE_PAD_CTL_BL_PD_STRENGTH_MASK 0x000003e0
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_DRIVE_PAD_CTL_BL_PD_STRENGTH_SHIFT 5
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_DRIVE_PAD_CTL_BL_PD_STRENGTH_DEFAULT 0x0000001f
-
-/* DDR34_PHY_BYTE_LANE_1_1 :: DRIVE_PAD_CTL :: BL_ND_STRENGTH [04:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_DRIVE_PAD_CTL_BL_ND_STRENGTH_MASK 0x0000001f
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_DRIVE_PAD_CTL_BL_ND_STRENGTH_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_DRIVE_PAD_CTL_BL_ND_STRENGTH_DEFAULT 0x0000001f
-
-/***************************************************************************
- *RD_EN_DRIVE_PAD_CTL - SSTL read enable pad drive characteristics control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_1_1 :: RD_EN_DRIVE_PAD_CTL :: reserved0 [31:20] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_RD_EN_DRIVE_PAD_CTL_reserved0_MASK 0xfff00000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_RD_EN_DRIVE_PAD_CTL_reserved0_SHIFT 20
-
-/* DDR34_PHY_BYTE_LANE_1_1 :: RD_EN_DRIVE_PAD_CTL :: EDC_RD_EN_PD_STRENGTH [19:15] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_RD_EN_DRIVE_PAD_CTL_EDC_RD_EN_PD_STRENGTH_MASK 0x000f8000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_RD_EN_DRIVE_PAD_CTL_EDC_RD_EN_PD_STRENGTH_SHIFT 15
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_RD_EN_DRIVE_PAD_CTL_EDC_RD_EN_PD_STRENGTH_DEFAULT 0x0000001f
-
-/* DDR34_PHY_BYTE_LANE_1_1 :: RD_EN_DRIVE_PAD_CTL :: EDC_RD_EN_ND_STRENGTH [14:10] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_RD_EN_DRIVE_PAD_CTL_EDC_RD_EN_ND_STRENGTH_MASK 0x00007c00
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_RD_EN_DRIVE_PAD_CTL_EDC_RD_EN_ND_STRENGTH_SHIFT 10
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_RD_EN_DRIVE_PAD_CTL_EDC_RD_EN_ND_STRENGTH_DEFAULT 0x0000001f
-
-/* DDR34_PHY_BYTE_LANE_1_1 :: RD_EN_DRIVE_PAD_CTL :: BL_RD_EN_PD_STRENGTH [09:05] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_RD_EN_DRIVE_PAD_CTL_BL_RD_EN_PD_STRENGTH_MASK 0x000003e0
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_RD_EN_DRIVE_PAD_CTL_BL_RD_EN_PD_STRENGTH_SHIFT 5
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_RD_EN_DRIVE_PAD_CTL_BL_RD_EN_PD_STRENGTH_DEFAULT 0x0000001f
-
-/* DDR34_PHY_BYTE_LANE_1_1 :: RD_EN_DRIVE_PAD_CTL :: BL_RD_EN_ND_STRENGTH [04:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_RD_EN_DRIVE_PAD_CTL_BL_RD_EN_ND_STRENGTH_MASK 0x0000001f
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_RD_EN_DRIVE_PAD_CTL_BL_RD_EN_ND_STRENGTH_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_RD_EN_DRIVE_PAD_CTL_BL_RD_EN_ND_STRENGTH_DEFAULT 0x0000001f
-
-/***************************************************************************
- *STATIC_PAD_CTL - pad rx and tx characteristics control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_1_1 :: STATIC_PAD_CTL :: reserved0 [31:21] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_STATIC_PAD_CTL_reserved0_MASK 0xffe00000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_STATIC_PAD_CTL_reserved0_SHIFT 21
-
-/* DDR34_PHY_BYTE_LANE_1_1 :: STATIC_PAD_CTL :: DQS_MODE [20:20] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_STATIC_PAD_CTL_DQS_MODE_MASK 0x00100000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_STATIC_PAD_CTL_DQS_MODE_SHIFT 20
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_STATIC_PAD_CTL_DQS_MODE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_1 :: STATIC_PAD_CTL :: reserved1 [19:18] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_STATIC_PAD_CTL_reserved1_MASK 0x000c0000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_STATIC_PAD_CTL_reserved1_SHIFT 18
-
-/* DDR34_PHY_BYTE_LANE_1_1 :: STATIC_PAD_CTL :: EDC_MODE [17:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_STATIC_PAD_CTL_EDC_MODE_MASK 0x00030000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_STATIC_PAD_CTL_EDC_MODE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_STATIC_PAD_CTL_EDC_MODE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_1 :: STATIC_PAD_CTL :: reserved2 [15:15] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_STATIC_PAD_CTL_reserved2_MASK 0x00008000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_STATIC_PAD_CTL_reserved2_SHIFT 15
-
-/* DDR34_PHY_BYTE_LANE_1_1 :: STATIC_PAD_CTL :: WDBI_ENABLE [14:14] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_STATIC_PAD_CTL_WDBI_ENABLE_MASK 0x00004000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_STATIC_PAD_CTL_WDBI_ENABLE_SHIFT 14
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_STATIC_PAD_CTL_WDBI_ENABLE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_1 :: STATIC_PAD_CTL :: RDBI_ENABLE [13:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_STATIC_PAD_CTL_RDBI_ENABLE_MASK 0x00002000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_STATIC_PAD_CTL_RDBI_ENABLE_SHIFT 13
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_STATIC_PAD_CTL_RDBI_ENABLE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_1 :: STATIC_PAD_CTL :: DM_MODE [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_STATIC_PAD_CTL_DM_MODE_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_STATIC_PAD_CTL_DM_MODE_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_STATIC_PAD_CTL_DM_MODE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_1 :: STATIC_PAD_CTL :: reserved3 [11:11] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_STATIC_PAD_CTL_reserved3_MASK 0x00000800
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_STATIC_PAD_CTL_reserved3_SHIFT 11
-
-/* DDR34_PHY_BYTE_LANE_1_1 :: STATIC_PAD_CTL :: DQS_TX_PAUSE [10:10] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_STATIC_PAD_CTL_DQS_TX_PAUSE_MASK 0x00000400
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_STATIC_PAD_CTL_DQS_TX_PAUSE_SHIFT 10
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_STATIC_PAD_CTL_DQS_TX_PAUSE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_1 :: STATIC_PAD_CTL :: DQS_TX_DIS [09:09] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_STATIC_PAD_CTL_DQS_TX_DIS_MASK 0x00000200
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_STATIC_PAD_CTL_DQS_TX_DIS_SHIFT 9
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_STATIC_PAD_CTL_DQS_TX_DIS_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_1 :: STATIC_PAD_CTL :: reserved4 [08:08] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_STATIC_PAD_CTL_reserved4_MASK 0x00000100
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_STATIC_PAD_CTL_reserved4_SHIFT 8
-
-/* DDR34_PHY_BYTE_LANE_1_1 :: STATIC_PAD_CTL :: TX_MODE [07:04] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_STATIC_PAD_CTL_TX_MODE_MASK 0x000000f0
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_STATIC_PAD_CTL_TX_MODE_SHIFT 4
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_STATIC_PAD_CTL_TX_MODE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_1 :: STATIC_PAD_CTL :: reserved5 [03:03] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_STATIC_PAD_CTL_reserved5_MASK 0x00000008
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_STATIC_PAD_CTL_reserved5_SHIFT 3
-
-/* DDR34_PHY_BYTE_LANE_1_1 :: STATIC_PAD_CTL :: RX_MODE [02:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_STATIC_PAD_CTL_RX_MODE_MASK 0x00000007
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_STATIC_PAD_CTL_RX_MODE_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_STATIC_PAD_CTL_RX_MODE_DEFAULT 0x00000000
-
-/***************************************************************************
- *WR_PREAMBLE_MODE - Write cycle preamble control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_1_1 :: WR_PREAMBLE_MODE :: reserved0 [31:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_WR_PREAMBLE_MODE_reserved0_MASK 0xffff0000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_WR_PREAMBLE_MODE_reserved0_SHIFT 16
-
-/* DDR34_PHY_BYTE_LANE_1_1 :: WR_PREAMBLE_MODE :: DQ_POSTAM_BITS [15:14] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_WR_PREAMBLE_MODE_DQ_POSTAM_BITS_MASK 0x0000c000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_WR_PREAMBLE_MODE_DQ_POSTAM_BITS_SHIFT 14
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_WR_PREAMBLE_MODE_DQ_POSTAM_BITS_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_1 :: WR_PREAMBLE_MODE :: DQ_PREAM_BITS [13:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_WR_PREAMBLE_MODE_DQ_PREAM_BITS_MASK 0x00003000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_WR_PREAMBLE_MODE_DQ_PREAM_BITS_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_WR_PREAMBLE_MODE_DQ_PREAM_BITS_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_1 :: WR_PREAMBLE_MODE :: DQS [11:08] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_WR_PREAMBLE_MODE_DQS_MASK 0x00000f00
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_WR_PREAMBLE_MODE_DQS_SHIFT 8
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_WR_PREAMBLE_MODE_DQS_DEFAULT 0x0000000e
-
-/* DDR34_PHY_BYTE_LANE_1_1 :: WR_PREAMBLE_MODE :: reserved1 [07:05] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_WR_PREAMBLE_MODE_reserved1_MASK 0x000000e0
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_WR_PREAMBLE_MODE_reserved1_SHIFT 5
-
-/* DDR34_PHY_BYTE_LANE_1_1 :: WR_PREAMBLE_MODE :: DQS_POSTAM_BITS [04:03] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_WR_PREAMBLE_MODE_DQS_POSTAM_BITS_MASK 0x00000018
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_WR_PREAMBLE_MODE_DQS_POSTAM_BITS_SHIFT 3
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_WR_PREAMBLE_MODE_DQS_POSTAM_BITS_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_1 :: WR_PREAMBLE_MODE :: DQS_PREAM_BITS [02:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_WR_PREAMBLE_MODE_DQS_PREAM_BITS_MASK 0x00000007
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_WR_PREAMBLE_MODE_DQS_PREAM_BITS_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_WR_PREAMBLE_MODE_DQS_PREAM_BITS_DEFAULT 0x00000002
-
-/***************************************************************************
- *ODT_CONTROL - Read channel ODT control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_1_1 :: ODT_CONTROL :: reserved_for_padding0 [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_ODT_CONTROL_reserved_for_padding0_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_ODT_CONTROL_reserved_for_padding0_SHIFT 31
-
-/* DDR34_PHY_BYTE_LANE_1_1 :: ODT_CONTROL :: reserved1 [30:10] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_ODT_CONTROL_reserved1_MASK 0x7ffffc00
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_ODT_CONTROL_reserved1_SHIFT 10
-
-/* DDR34_PHY_BYTE_LANE_1_1 :: ODT_CONTROL :: ODT_ENABLE [09:09] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_ODT_CONTROL_ODT_ENABLE_MASK 0x00000200
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_ODT_CONTROL_ODT_ENABLE_SHIFT 9
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_ODT_CONTROL_ODT_ENABLE_DEFAULT 0x00000001
-
-/* DDR34_PHY_BYTE_LANE_1_1 :: ODT_CONTROL :: ODT_DELAY [08:06] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_ODT_CONTROL_ODT_DELAY_MASK 0x000001c0
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_ODT_CONTROL_ODT_DELAY_SHIFT 6
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_ODT_CONTROL_ODT_DELAY_DEFAULT 0x00000001
-
-/* DDR34_PHY_BYTE_LANE_1_1 :: ODT_CONTROL :: ODT_POST_LENGTH [05:03] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_ODT_CONTROL_ODT_POST_LENGTH_MASK 0x00000038
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_ODT_CONTROL_ODT_POST_LENGTH_SHIFT 3
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_ODT_CONTROL_ODT_POST_LENGTH_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_1 :: ODT_CONTROL :: ODT_PRE_LENGTH [02:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_ODT_CONTROL_ODT_PRE_LENGTH_MASK 0x00000007
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_ODT_CONTROL_ODT_PRE_LENGTH_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_ODT_CONTROL_ODT_PRE_LENGTH_DEFAULT 0x00000003
-
-/***************************************************************************
- *EDC_DPD_CONTROL - GDDR5M EDC digital phase detector control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_1_1 :: EDC_DPD_CONTROL :: reserved0 [31:06] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_EDC_DPD_CONTROL_reserved0_MASK 0xffffffc0
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_EDC_DPD_CONTROL_reserved0_SHIFT 6
-
-/* DDR34_PHY_BYTE_LANE_1_1 :: EDC_DPD_CONTROL :: DQS_PHASE_OVERRIDE_VALUE [05:05] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_EDC_DPD_CONTROL_DQS_PHASE_OVERRIDE_VALUE_MASK 0x00000020
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_EDC_DPD_CONTROL_DQS_PHASE_OVERRIDE_VALUE_SHIFT 5
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_EDC_DPD_CONTROL_DQS_PHASE_OVERRIDE_VALUE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_1 :: EDC_DPD_CONTROL :: DQS_PHASE_OVERRIDE_ENABLE [04:04] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_EDC_DPD_CONTROL_DQS_PHASE_OVERRIDE_ENABLE_MASK 0x00000010
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_EDC_DPD_CONTROL_DQS_PHASE_OVERRIDE_ENABLE_SHIFT 4
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_EDC_DPD_CONTROL_DQS_PHASE_OVERRIDE_ENABLE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_1 :: EDC_DPD_CONTROL :: SET_ADJ_EN [03:03] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_EDC_DPD_CONTROL_SET_ADJ_EN_MASK 0x00000008
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_EDC_DPD_CONTROL_SET_ADJ_EN_SHIFT 3
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_EDC_DPD_CONTROL_SET_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_1 :: EDC_DPD_CONTROL :: UPDATE [02:02] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_EDC_DPD_CONTROL_UPDATE_MASK 0x00000004
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_EDC_DPD_CONTROL_UPDATE_SHIFT 2
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_EDC_DPD_CONTROL_UPDATE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_1 :: EDC_DPD_CONTROL :: MONITOR [01:01] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_EDC_DPD_CONTROL_MONITOR_MASK 0x00000002
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_EDC_DPD_CONTROL_MONITOR_SHIFT 1
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_EDC_DPD_CONTROL_MONITOR_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_1 :: EDC_DPD_CONTROL :: INIT [00:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_EDC_DPD_CONTROL_INIT_MASK 0x00000001
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_EDC_DPD_CONTROL_INIT_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_EDC_DPD_CONTROL_INIT_DEFAULT 0x00000000
-
-/***************************************************************************
- *EDC_DPD_STATUS - GDDR5M EDC digital phase detector status register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_1_1 :: EDC_DPD_STATUS :: reserved0 [31:25] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_EDC_DPD_STATUS_reserved0_MASK 0xfe000000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_EDC_DPD_STATUS_reserved0_SHIFT 25
-
-/* DDR34_PHY_BYTE_LANE_1_1 :: EDC_DPD_STATUS :: CURRENT_DQS_PHASE [24:24] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_EDC_DPD_STATUS_CURRENT_DQS_PHASE_MASK 0x01000000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_EDC_DPD_STATUS_CURRENT_DQS_PHASE_SHIFT 24
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_EDC_DPD_STATUS_CURRENT_DQS_PHASE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_1 :: EDC_DPD_STATUS :: CURRENT_VDL_SETTING [23:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_EDC_DPD_STATUS_CURRENT_VDL_SETTING_MASK 0x00ff0000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_EDC_DPD_STATUS_CURRENT_VDL_SETTING_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_EDC_DPD_STATUS_CURRENT_VDL_SETTING_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_1 :: EDC_DPD_STATUS :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_EDC_DPD_STATUS_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_EDC_DPD_STATUS_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_1_1 :: EDC_DPD_STATUS :: INIT_DQS_PHASE [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_EDC_DPD_STATUS_INIT_DQS_PHASE_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_EDC_DPD_STATUS_INIT_DQS_PHASE_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_EDC_DPD_STATUS_INIT_DQS_PHASE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_1 :: EDC_DPD_STATUS :: INIT_VDL_SETTING [11:04] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_EDC_DPD_STATUS_INIT_VDL_SETTING_MASK 0x00000ff0
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_EDC_DPD_STATUS_INIT_VDL_SETTING_SHIFT 4
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_EDC_DPD_STATUS_INIT_VDL_SETTING_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_1 :: EDC_DPD_STATUS :: EDGE_ERROR [03:03] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_EDC_DPD_STATUS_EDGE_ERROR_MASK 0x00000008
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_EDC_DPD_STATUS_EDGE_ERROR_SHIFT 3
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_EDC_DPD_STATUS_EDGE_ERROR_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_1 :: EDC_DPD_STATUS :: MONITOR_BUSY [02:02] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_EDC_DPD_STATUS_MONITOR_BUSY_MASK 0x00000004
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_EDC_DPD_STATUS_MONITOR_BUSY_SHIFT 2
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_EDC_DPD_STATUS_MONITOR_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_1 :: EDC_DPD_STATUS :: INIT_BUSY [01:01] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_EDC_DPD_STATUS_INIT_BUSY_MASK 0x00000002
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_EDC_DPD_STATUS_INIT_BUSY_SHIFT 1
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_EDC_DPD_STATUS_INIT_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_1 :: EDC_DPD_STATUS :: INIT_DONE [00:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_EDC_DPD_STATUS_INIT_DONE_MASK 0x00000001
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_EDC_DPD_STATUS_INIT_DONE_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_EDC_DPD_STATUS_INIT_DONE_DEFAULT 0x00000000
-
-/***************************************************************************
- *EDC_DPD_OUT_CONTROL - GDDR5M EDC digital phase detector output signal control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_1_1 :: EDC_DPD_OUT_CONTROL :: reserved0 [31:20] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_EDC_DPD_OUT_CONTROL_reserved0_MASK 0xfff00000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_EDC_DPD_OUT_CONTROL_reserved0_SHIFT 20
-
-/* DDR34_PHY_BYTE_LANE_1_1 :: EDC_DPD_OUT_CONTROL :: LOWER_LIMIT [19:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_EDC_DPD_OUT_CONTROL_LOWER_LIMIT_MASK 0x000ff000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_EDC_DPD_OUT_CONTROL_LOWER_LIMIT_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_EDC_DPD_OUT_CONTROL_LOWER_LIMIT_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_1 :: EDC_DPD_OUT_CONTROL :: UPPER_LIMIT [11:04] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_EDC_DPD_OUT_CONTROL_UPPER_LIMIT_MASK 0x00000ff0
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_EDC_DPD_OUT_CONTROL_UPPER_LIMIT_SHIFT 4
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_EDC_DPD_OUT_CONTROL_UPPER_LIMIT_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_1 :: EDC_DPD_OUT_CONTROL :: reserved1 [03:01] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_EDC_DPD_OUT_CONTROL_reserved1_MASK 0x0000000e
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_EDC_DPD_OUT_CONTROL_reserved1_SHIFT 1
-
-/* DDR34_PHY_BYTE_LANE_1_1 :: EDC_DPD_OUT_CONTROL :: ENABLE [00:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_EDC_DPD_OUT_CONTROL_ENABLE_MASK 0x00000001
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_EDC_DPD_OUT_CONTROL_ENABLE_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_EDC_DPD_OUT_CONTROL_ENABLE_DEFAULT 0x00000000
-
-/***************************************************************************
- *EDC_DPD_OUT_STATUS - GDDR5M EDC digital phase detector output signal status register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_1_1 :: EDC_DPD_OUT_STATUS :: reserved0 [31:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_EDC_DPD_OUT_STATUS_reserved0_MASK 0xfffff000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_EDC_DPD_OUT_STATUS_reserved0_SHIFT 12
-
-/* DDR34_PHY_BYTE_LANE_1_1 :: EDC_DPD_OUT_STATUS :: VDL_SETTING [11:04] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_EDC_DPD_OUT_STATUS_VDL_SETTING_MASK 0x00000ff0
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_EDC_DPD_OUT_STATUS_VDL_SETTING_SHIFT 4
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_EDC_DPD_OUT_STATUS_VDL_SETTING_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_1 :: EDC_DPD_OUT_STATUS :: reserved1 [03:01] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_EDC_DPD_OUT_STATUS_reserved1_MASK 0x0000000e
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_EDC_DPD_OUT_STATUS_reserved1_SHIFT 1
-
-/* DDR34_PHY_BYTE_LANE_1_1 :: EDC_DPD_OUT_STATUS :: VALID [00:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_EDC_DPD_OUT_STATUS_VALID_MASK 0x00000001
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_EDC_DPD_OUT_STATUS_VALID_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_EDC_DPD_OUT_STATUS_VALID_DEFAULT 0x00000000
-
-/***************************************************************************
- *EDC_DPD_OUT_STATUS_CLEAR - GDDR5M EDC digital phase detector output signal status clear register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_1_1 :: EDC_DPD_OUT_STATUS_CLEAR :: reserved0 [31:01] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_EDC_DPD_OUT_STATUS_CLEAR_reserved0_MASK 0xfffffffe
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_EDC_DPD_OUT_STATUS_CLEAR_reserved0_SHIFT 1
-
-/* DDR34_PHY_BYTE_LANE_1_1 :: EDC_DPD_OUT_STATUS_CLEAR :: CLEAR [00:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_EDC_DPD_OUT_STATUS_CLEAR_CLEAR_MASK 0x00000001
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_EDC_DPD_OUT_STATUS_CLEAR_CLEAR_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_EDC_DPD_OUT_STATUS_CLEAR_CLEAR_DEFAULT 0x00000000
-
-/***************************************************************************
- *EDC_CRC_CONTROL - GDDR5M EDC signal path CRC control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_1_1 :: EDC_CRC_CONTROL :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_EDC_CRC_CONTROL_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_EDC_CRC_CONTROL_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_EDC_CRC_CONTROL_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_1 :: EDC_CRC_CONTROL :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_EDC_CRC_CONTROL_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_EDC_CRC_CONTROL_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_1_1 :: EDC_CRC_CONTROL :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_EDC_CRC_CONTROL_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_EDC_CRC_CONTROL_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_EDC_CRC_CONTROL_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_1 :: EDC_CRC_CONTROL :: reserved1 [15:11] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_EDC_CRC_CONTROL_reserved1_MASK 0x0000f800
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_EDC_CRC_CONTROL_reserved1_SHIFT 11
-
-/* DDR34_PHY_BYTE_LANE_1_1 :: EDC_CRC_CONTROL :: CRCWL [10:08] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_EDC_CRC_CONTROL_CRCWL_MASK 0x00000700
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_EDC_CRC_CONTROL_CRCWL_SHIFT 8
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_EDC_CRC_CONTROL_CRCWL_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_1 :: EDC_CRC_CONTROL :: reserved2 [07:06] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_EDC_CRC_CONTROL_reserved2_MASK 0x000000c0
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_EDC_CRC_CONTROL_reserved2_SHIFT 6
-
-/* DDR34_PHY_BYTE_LANE_1_1 :: EDC_CRC_CONTROL :: CRCRL [05:04] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_EDC_CRC_CONTROL_CRCRL_MASK 0x00000030
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_EDC_CRC_CONTROL_CRCRL_SHIFT 4
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_EDC_CRC_CONTROL_CRCRL_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_1 :: EDC_CRC_CONTROL :: reserved3 [03:03] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_EDC_CRC_CONTROL_reserved3_MASK 0x00000008
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_EDC_CRC_CONTROL_reserved3_SHIFT 3
-
-/* DDR34_PHY_BYTE_LANE_1_1 :: EDC_CRC_CONTROL :: COUNT_MODE [02:02] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_EDC_CRC_CONTROL_COUNT_MODE_MASK 0x00000004
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_EDC_CRC_CONTROL_COUNT_MODE_SHIFT 2
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_EDC_CRC_CONTROL_COUNT_MODE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_1 :: EDC_CRC_CONTROL :: ENABLE_WR [01:01] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_EDC_CRC_CONTROL_ENABLE_WR_MASK 0x00000002
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_EDC_CRC_CONTROL_ENABLE_WR_SHIFT 1
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_EDC_CRC_CONTROL_ENABLE_WR_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_1 :: EDC_CRC_CONTROL :: ENABLE_RD [00:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_EDC_CRC_CONTROL_ENABLE_RD_MASK 0x00000001
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_EDC_CRC_CONTROL_ENABLE_RD_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_EDC_CRC_CONTROL_ENABLE_RD_DEFAULT 0x00000000
-
-/***************************************************************************
- *EDC_CRC_STATUS - GDDR5M EDC signal path CRC status register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_1_1 :: EDC_CRC_STATUS :: reserved0 [31:04] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_EDC_CRC_STATUS_reserved0_MASK 0xfffffff0
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_EDC_CRC_STATUS_reserved0_SHIFT 4
-
-/* DDR34_PHY_BYTE_LANE_1_1 :: EDC_CRC_STATUS :: WR_FAIL [03:03] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_EDC_CRC_STATUS_WR_FAIL_MASK 0x00000008
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_EDC_CRC_STATUS_WR_FAIL_SHIFT 3
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_EDC_CRC_STATUS_WR_FAIL_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_1 :: EDC_CRC_STATUS :: WR_PASS [02:02] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_EDC_CRC_STATUS_WR_PASS_MASK 0x00000004
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_EDC_CRC_STATUS_WR_PASS_SHIFT 2
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_EDC_CRC_STATUS_WR_PASS_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_1 :: EDC_CRC_STATUS :: RD_FAIL [01:01] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_EDC_CRC_STATUS_RD_FAIL_MASK 0x00000002
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_EDC_CRC_STATUS_RD_FAIL_SHIFT 1
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_EDC_CRC_STATUS_RD_FAIL_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_1 :: EDC_CRC_STATUS :: RD_PASS [00:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_EDC_CRC_STATUS_RD_PASS_MASK 0x00000001
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_EDC_CRC_STATUS_RD_PASS_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_EDC_CRC_STATUS_RD_PASS_DEFAULT 0x00000000
-
-/***************************************************************************
- *EDC_CRC_COUNT - GDDR5M EDC signal path CRC counter register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_1_1 :: EDC_CRC_COUNT :: reserved0 [31:28] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_EDC_CRC_COUNT_reserved0_MASK 0xf0000000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_EDC_CRC_COUNT_reserved0_SHIFT 28
-
-/* DDR34_PHY_BYTE_LANE_1_1 :: EDC_CRC_COUNT :: WR_COUNT [27:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_EDC_CRC_COUNT_WR_COUNT_MASK 0x0fff0000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_EDC_CRC_COUNT_WR_COUNT_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_EDC_CRC_COUNT_WR_COUNT_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_1 :: EDC_CRC_COUNT :: reserved1 [15:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_EDC_CRC_COUNT_reserved1_MASK 0x0000f000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_EDC_CRC_COUNT_reserved1_SHIFT 12
-
-/* DDR34_PHY_BYTE_LANE_1_1 :: EDC_CRC_COUNT :: RD_COUNT [11:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_EDC_CRC_COUNT_RD_COUNT_MASK 0x00000fff
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_EDC_CRC_COUNT_RD_COUNT_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_EDC_CRC_COUNT_RD_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *EDC_CRC_STATUS_CLEAR - GDDR5M EDC signal path CRC counter register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_1_1 :: EDC_CRC_STATUS_CLEAR :: reserved0 [31:01] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_EDC_CRC_STATUS_CLEAR_reserved0_MASK 0xfffffffe
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_EDC_CRC_STATUS_CLEAR_reserved0_SHIFT 1
-
-/* DDR34_PHY_BYTE_LANE_1_1 :: EDC_CRC_STATUS_CLEAR :: CLEAR [00:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_EDC_CRC_STATUS_CLEAR_CLEAR_MASK 0x00000001
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_EDC_CRC_STATUS_CLEAR_CLEAR_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_EDC_CRC_STATUS_CLEAR_CLEAR_DEFAULT 0x00000000
-
-/***************************************************************************
- *BL_SPARE_REG - Byte-Lane Spare register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_1_1 :: BL_SPARE_REG :: reserved_for_eco0 [31:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_BL_SPARE_REG_reserved_for_eco0_MASK 0xffffffff
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_BL_SPARE_REG_reserved_for_eco0_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_BL_SPARE_REG_reserved_for_eco0_DEFAULT 0x00000000
-
-#endif /* #ifndef BCHP_DDR34_PHY_BYTE_LANE_1_1_H__ */
-
-/* End of File */
diff --git a/include/linux/brcmstb/7145a0/bchp_ddr34_phy_byte_lane_2_0.h b/include/linux/brcmstb/7145a0/bchp_ddr34_phy_byte_lane_2_0.h
deleted file mode 100644
index 658bbdb..0000000
--- a/include/linux/brcmstb/7145a0/bchp_ddr34_phy_byte_lane_2_0.h
+++ /dev/null
@@ -1,2101 +0,0 @@
-/***************************************************************************
- * Copyright (c) 1999-2014, Broadcom Corporation
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
- *
- * Module Description:
- * DO NOT EDIT THIS FILE DIRECTLY
- *
- * This module was generated magically with RDB from a source description
- * file. You must edit the source file for changes to be made to this file.
- *
- *
- * Date: Generated on Wed Sep 3 13:17:35 2014
- * Full Compile MD5 Checksum a8ee62ccf9dde43435c825f266da463d
- * (minus title and desc)
- * MD5 Checksum e373b364a1742e13a0f9eb15fd8aa94f
- *
- * Compiled with: RDB Utility combo_header.pl
- * RDB Parser 3.0
- * unknown unknown
- * Perl Interpreter 5.008005
- * Operating System linux
- *
- * Revision History:
- *
- * $brcm_Log: $
- *
- ***************************************************************************/
-
-#ifndef BCHP_DDR34_PHY_BYTE_LANE_2_0_H__
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_H__
-
-/***************************************************************************
- *DDR34_PHY_BYTE_LANE_2_0 - DDR34 Byte Lane #2 control registers
- ***************************************************************************/
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQS_P 0x203b6800 /* Write channel DQS-P VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQS_N 0x203b6804 /* Write channel DQS-N VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ0 0x203b6808 /* Write channel DQ0 VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ1 0x203b680c /* Write channel DQ1 VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ2 0x203b6810 /* Write channel DQ2 VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ3 0x203b6814 /* Write channel DQ3 VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ4 0x203b6818 /* Write channel DQ4 VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ5 0x203b681c /* Write channel DQ5 VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ6 0x203b6820 /* Write channel DQ6 VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ7 0x203b6824 /* Write channel DQ7 VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DM 0x203b6828 /* Write channel DM VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_EDC 0x203b682c /* Write channel EDC VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQSP 0x203b6830 /* Read channel DQSP VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQSN 0x203b6834 /* Read channel DQSP VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ0P 0x203b6838 /* Read channel DQ0-P VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ0N 0x203b683c /* Read channel DQ0-N VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ1P 0x203b6840 /* Read channel DQ1-P VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ1N 0x203b6844 /* Read channel DQ1-N VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ2P 0x203b6848 /* Read channel DQ2-P VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ2N 0x203b684c /* Read channel DQ2-N VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ3P 0x203b6850 /* Read channel DQ3-P VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ3N 0x203b6854 /* Read channel DQ3-N VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ4P 0x203b6858 /* Read channel DQ4-P VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ4N 0x203b685c /* Read channel DQ4-N VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ5P 0x203b6860 /* Read channel DQ5-P VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ5N 0x203b6864 /* Read channel DQ5-N VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ6P 0x203b6868 /* Read channel DQ6-P VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ6N 0x203b686c /* Read channel DQ6-N VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ7P 0x203b6870 /* Read channel DQ7-P VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ7N 0x203b6874 /* Read channel DQ7-N VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DMP 0x203b6878 /* Read channel DM-P VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DMN 0x203b687c /* Read channel DM-N VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_EDCP 0x203b6880 /* Read channel EDC-P VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_EDCN 0x203b6884 /* Read channel EDC-N VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_EN_CS0 0x203b6888 /* Read channel CS_N[0] read enable VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_EN_CS1 0x203b688c /* Read channel CS_N[1] read enable VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CLK_CONTROL 0x203b6890 /* DDR interface signal Write Leveling CLK VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_LDE_CONTROL 0x203b6894 /* DDR interface signal Write Leveling Capture Enable VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_RD_EN_DLY_CYC 0x203b68a0 /* Read enable bit-clock cycle delay control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_WR_CHAN_DLY_CYC 0x203b68a4 /* Write leveling bit-clock cycle delay control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_READ_CONTROL 0x203b68b0 /* Read channel datapath control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_READ_FIFO_ADDR 0x203b68b4 /* Read fifo addresss pointer register */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_READ_FIFO_DATA 0x203b68b8 /* Read fifo data register */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_READ_FIFO_DM_DBI 0x203b68bc /* Read fifo dm/dbi register */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_READ_FIFO_STATUS 0x203b68c0 /* Read fifo status register */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_READ_FIFO_CLEAR 0x203b68c4 /* Read fifo status clear register */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_IDLE_PAD_CONTROL 0x203b68c8 /* Idle mode SSTL pad control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_DRIVE_PAD_CTL 0x203b68cc /* SSTL pad drive characteristics control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_RD_EN_DRIVE_PAD_CTL 0x203b68d0 /* SSTL read enable pad drive characteristics control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_STATIC_PAD_CTL 0x203b68d4 /* pad rx and tx characteristics control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_WR_PREAMBLE_MODE 0x203b68d8 /* Write cycle preamble control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_ODT_CONTROL 0x203b68e0 /* Read channel ODT control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_DPD_CONTROL 0x203b68f0 /* GDDR5M EDC digital phase detector control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_DPD_STATUS 0x203b68f4 /* GDDR5M EDC digital phase detector status register */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_DPD_OUT_CONTROL 0x203b68f8 /* GDDR5M EDC digital phase detector output signal control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_DPD_OUT_STATUS 0x203b68fc /* GDDR5M EDC digital phase detector output signal status register */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_DPD_OUT_STATUS_CLEAR 0x203b6900 /* GDDR5M EDC digital phase detector output signal status clear register */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_CRC_CONTROL 0x203b6904 /* GDDR5M EDC signal path CRC control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_CRC_STATUS 0x203b6908 /* GDDR5M EDC signal path CRC status register */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_CRC_COUNT 0x203b690c /* GDDR5M EDC signal path CRC counter register */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_CRC_STATUS_CLEAR 0x203b6910 /* GDDR5M EDC signal path CRC counter register */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_BL_SPARE_REG 0x203b6914 /* Byte-Lane Spare register */
-
-/***************************************************************************
- *VDL_CONTROL_WR_DQS_P - Write channel DQS-P VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_WR_DQS_P :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQS_P_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQS_P_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQS_P_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_WR_DQS_P :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQS_P_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQS_P_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_WR_DQS_P :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQS_P_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQS_P_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQS_P_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_WR_DQS_P :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQS_P_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQS_P_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_WR_DQS_P :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQS_P_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQS_P_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQS_P_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_WR_DQS_P :: reserved2 [11:09] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQS_P_reserved2_MASK 0x00000e00
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQS_P_reserved2_SHIFT 9
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_WR_DQS_P :: VDL_STEP [08:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQS_P_VDL_STEP_MASK 0x000001ff
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQS_P_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQS_P_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_WR_DQS_N - Write channel DQS-N VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_WR_DQS_N :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQS_N_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQS_N_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQS_N_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_WR_DQS_N :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQS_N_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQS_N_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_WR_DQS_N :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQS_N_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQS_N_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQS_N_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_WR_DQS_N :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQS_N_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQS_N_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_WR_DQS_N :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQS_N_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQS_N_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQS_N_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_WR_DQS_N :: reserved2 [11:09] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQS_N_reserved2_MASK 0x00000e00
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQS_N_reserved2_SHIFT 9
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_WR_DQS_N :: VDL_STEP [08:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQS_N_VDL_STEP_MASK 0x000001ff
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQS_N_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQS_N_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_WR_DQ0 - Write channel DQ0 VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_WR_DQ0 :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ0_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ0_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ0_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_WR_DQ0 :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ0_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ0_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_WR_DQ0 :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ0_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ0_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ0_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_WR_DQ0 :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ0_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ0_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_WR_DQ0 :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ0_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ0_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ0_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_WR_DQ0 :: reserved2 [11:09] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ0_reserved2_MASK 0x00000e00
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ0_reserved2_SHIFT 9
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_WR_DQ0 :: VDL_STEP [08:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ0_VDL_STEP_MASK 0x000001ff
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ0_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ0_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_WR_DQ1 - Write channel DQ1 VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_WR_DQ1 :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ1_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ1_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ1_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_WR_DQ1 :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ1_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ1_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_WR_DQ1 :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ1_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ1_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ1_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_WR_DQ1 :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ1_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ1_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_WR_DQ1 :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ1_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ1_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ1_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_WR_DQ1 :: reserved2 [11:09] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ1_reserved2_MASK 0x00000e00
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ1_reserved2_SHIFT 9
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_WR_DQ1 :: VDL_STEP [08:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ1_VDL_STEP_MASK 0x000001ff
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ1_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ1_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_WR_DQ2 - Write channel DQ2 VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_WR_DQ2 :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ2_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ2_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ2_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_WR_DQ2 :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ2_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ2_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_WR_DQ2 :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ2_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ2_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ2_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_WR_DQ2 :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ2_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ2_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_WR_DQ2 :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ2_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ2_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ2_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_WR_DQ2 :: reserved2 [11:09] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ2_reserved2_MASK 0x00000e00
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ2_reserved2_SHIFT 9
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_WR_DQ2 :: VDL_STEP [08:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ2_VDL_STEP_MASK 0x000001ff
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ2_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ2_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_WR_DQ3 - Write channel DQ3 VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_WR_DQ3 :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ3_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ3_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ3_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_WR_DQ3 :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ3_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ3_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_WR_DQ3 :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ3_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ3_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ3_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_WR_DQ3 :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ3_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ3_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_WR_DQ3 :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ3_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ3_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ3_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_WR_DQ3 :: reserved2 [11:09] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ3_reserved2_MASK 0x00000e00
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ3_reserved2_SHIFT 9
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_WR_DQ3 :: VDL_STEP [08:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ3_VDL_STEP_MASK 0x000001ff
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ3_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ3_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_WR_DQ4 - Write channel DQ4 VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_WR_DQ4 :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ4_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ4_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ4_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_WR_DQ4 :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ4_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ4_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_WR_DQ4 :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ4_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ4_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ4_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_WR_DQ4 :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ4_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ4_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_WR_DQ4 :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ4_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ4_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ4_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_WR_DQ4 :: reserved2 [11:09] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ4_reserved2_MASK 0x00000e00
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ4_reserved2_SHIFT 9
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_WR_DQ4 :: VDL_STEP [08:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ4_VDL_STEP_MASK 0x000001ff
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ4_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ4_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_WR_DQ5 - Write channel DQ5 VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_WR_DQ5 :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ5_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ5_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ5_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_WR_DQ5 :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ5_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ5_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_WR_DQ5 :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ5_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ5_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ5_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_WR_DQ5 :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ5_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ5_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_WR_DQ5 :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ5_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ5_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ5_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_WR_DQ5 :: reserved2 [11:09] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ5_reserved2_MASK 0x00000e00
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ5_reserved2_SHIFT 9
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_WR_DQ5 :: VDL_STEP [08:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ5_VDL_STEP_MASK 0x000001ff
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ5_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ5_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_WR_DQ6 - Write channel DQ6 VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_WR_DQ6 :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ6_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ6_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ6_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_WR_DQ6 :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ6_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ6_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_WR_DQ6 :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ6_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ6_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ6_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_WR_DQ6 :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ6_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ6_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_WR_DQ6 :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ6_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ6_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ6_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_WR_DQ6 :: reserved2 [11:09] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ6_reserved2_MASK 0x00000e00
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ6_reserved2_SHIFT 9
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_WR_DQ6 :: VDL_STEP [08:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ6_VDL_STEP_MASK 0x000001ff
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ6_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ6_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_WR_DQ7 - Write channel DQ7 VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_WR_DQ7 :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ7_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ7_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ7_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_WR_DQ7 :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ7_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ7_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_WR_DQ7 :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ7_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ7_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ7_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_WR_DQ7 :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ7_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ7_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_WR_DQ7 :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ7_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ7_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ7_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_WR_DQ7 :: reserved2 [11:09] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ7_reserved2_MASK 0x00000e00
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ7_reserved2_SHIFT 9
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_WR_DQ7 :: VDL_STEP [08:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ7_VDL_STEP_MASK 0x000001ff
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ7_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ7_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_WR_DM - Write channel DM VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_WR_DM :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DM_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DM_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DM_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_WR_DM :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DM_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DM_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_WR_DM :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DM_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DM_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DM_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_WR_DM :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DM_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DM_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_WR_DM :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DM_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DM_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DM_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_WR_DM :: reserved2 [11:09] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DM_reserved2_MASK 0x00000e00
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DM_reserved2_SHIFT 9
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_WR_DM :: VDL_STEP [08:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DM_VDL_STEP_MASK 0x000001ff
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DM_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DM_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_WR_EDC - Write channel EDC VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_WR_EDC :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_EDC_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_EDC_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_EDC_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_WR_EDC :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_EDC_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_EDC_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_WR_EDC :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_EDC_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_EDC_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_EDC_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_WR_EDC :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_EDC_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_EDC_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_WR_EDC :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_EDC_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_EDC_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_EDC_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_WR_EDC :: reserved2 [11:09] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_EDC_reserved2_MASK 0x00000e00
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_EDC_reserved2_SHIFT 9
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_WR_EDC :: VDL_STEP [08:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_EDC_VDL_STEP_MASK 0x000001ff
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_EDC_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_EDC_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_RD_DQSP - Read channel DQSP VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQSP :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQSP_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQSP_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQSP_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQSP :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQSP_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQSP_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQSP :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQSP_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQSP_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQSP_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQSP :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQSP_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQSP_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQSP :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQSP_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQSP_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQSP_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQSP :: reserved2 [11:08] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQSP_reserved2_MASK 0x00000f00
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQSP_reserved2_SHIFT 8
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQSP :: VDL_STEP [07:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQSP_VDL_STEP_MASK 0x000000ff
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQSP_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQSP_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_RD_DQSN - Read channel DQSP VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQSN :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQSN_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQSN_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQSN_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQSN :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQSN_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQSN_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQSN :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQSN_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQSN_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQSN_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQSN :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQSN_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQSN_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQSN :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQSN_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQSN_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQSN_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQSN :: reserved2 [11:08] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQSN_reserved2_MASK 0x00000f00
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQSN_reserved2_SHIFT 8
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQSN :: VDL_STEP [07:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQSN_VDL_STEP_MASK 0x000000ff
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQSN_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQSN_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_RD_DQ0P - Read channel DQ0-P VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQ0P :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ0P_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ0P_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ0P_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQ0P :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ0P_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ0P_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQ0P :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ0P_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ0P_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ0P_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQ0P :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ0P_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ0P_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQ0P :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ0P_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ0P_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ0P_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQ0P :: reserved2 [11:08] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ0P_reserved2_MASK 0x00000f00
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ0P_reserved2_SHIFT 8
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQ0P :: VDL_STEP [07:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ0P_VDL_STEP_MASK 0x000000ff
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ0P_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ0P_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_RD_DQ0N - Read channel DQ0-N VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQ0N :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ0N_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ0N_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ0N_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQ0N :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ0N_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ0N_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQ0N :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ0N_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ0N_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ0N_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQ0N :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ0N_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ0N_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQ0N :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ0N_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ0N_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ0N_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQ0N :: reserved2 [11:08] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ0N_reserved2_MASK 0x00000f00
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ0N_reserved2_SHIFT 8
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQ0N :: VDL_STEP [07:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ0N_VDL_STEP_MASK 0x000000ff
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ0N_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ0N_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_RD_DQ1P - Read channel DQ1-P VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQ1P :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ1P_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ1P_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ1P_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQ1P :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ1P_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ1P_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQ1P :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ1P_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ1P_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ1P_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQ1P :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ1P_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ1P_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQ1P :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ1P_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ1P_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ1P_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQ1P :: reserved2 [11:08] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ1P_reserved2_MASK 0x00000f00
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ1P_reserved2_SHIFT 8
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQ1P :: VDL_STEP [07:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ1P_VDL_STEP_MASK 0x000000ff
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ1P_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ1P_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_RD_DQ1N - Read channel DQ1-N VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQ1N :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ1N_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ1N_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ1N_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQ1N :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ1N_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ1N_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQ1N :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ1N_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ1N_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ1N_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQ1N :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ1N_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ1N_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQ1N :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ1N_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ1N_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ1N_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQ1N :: reserved2 [11:08] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ1N_reserved2_MASK 0x00000f00
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ1N_reserved2_SHIFT 8
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQ1N :: VDL_STEP [07:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ1N_VDL_STEP_MASK 0x000000ff
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ1N_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ1N_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_RD_DQ2P - Read channel DQ2-P VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQ2P :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ2P_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ2P_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ2P_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQ2P :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ2P_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ2P_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQ2P :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ2P_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ2P_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ2P_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQ2P :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ2P_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ2P_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQ2P :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ2P_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ2P_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ2P_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQ2P :: reserved2 [11:08] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ2P_reserved2_MASK 0x00000f00
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ2P_reserved2_SHIFT 8
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQ2P :: VDL_STEP [07:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ2P_VDL_STEP_MASK 0x000000ff
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ2P_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ2P_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_RD_DQ2N - Read channel DQ2-N VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQ2N :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ2N_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ2N_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ2N_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQ2N :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ2N_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ2N_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQ2N :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ2N_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ2N_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ2N_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQ2N :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ2N_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ2N_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQ2N :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ2N_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ2N_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ2N_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQ2N :: reserved2 [11:08] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ2N_reserved2_MASK 0x00000f00
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ2N_reserved2_SHIFT 8
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQ2N :: VDL_STEP [07:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ2N_VDL_STEP_MASK 0x000000ff
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ2N_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ2N_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_RD_DQ3P - Read channel DQ3-P VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQ3P :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ3P_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ3P_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ3P_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQ3P :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ3P_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ3P_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQ3P :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ3P_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ3P_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ3P_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQ3P :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ3P_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ3P_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQ3P :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ3P_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ3P_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ3P_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQ3P :: reserved2 [11:08] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ3P_reserved2_MASK 0x00000f00
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ3P_reserved2_SHIFT 8
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQ3P :: VDL_STEP [07:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ3P_VDL_STEP_MASK 0x000000ff
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ3P_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ3P_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_RD_DQ3N - Read channel DQ3-N VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQ3N :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ3N_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ3N_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ3N_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQ3N :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ3N_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ3N_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQ3N :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ3N_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ3N_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ3N_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQ3N :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ3N_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ3N_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQ3N :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ3N_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ3N_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ3N_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQ3N :: reserved2 [11:08] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ3N_reserved2_MASK 0x00000f00
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ3N_reserved2_SHIFT 8
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQ3N :: VDL_STEP [07:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ3N_VDL_STEP_MASK 0x000000ff
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ3N_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ3N_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_RD_DQ4P - Read channel DQ4-P VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQ4P :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ4P_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ4P_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ4P_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQ4P :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ4P_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ4P_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQ4P :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ4P_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ4P_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ4P_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQ4P :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ4P_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ4P_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQ4P :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ4P_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ4P_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ4P_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQ4P :: reserved2 [11:08] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ4P_reserved2_MASK 0x00000f00
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ4P_reserved2_SHIFT 8
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQ4P :: VDL_STEP [07:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ4P_VDL_STEP_MASK 0x000000ff
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ4P_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ4P_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_RD_DQ4N - Read channel DQ4-N VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQ4N :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ4N_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ4N_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ4N_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQ4N :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ4N_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ4N_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQ4N :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ4N_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ4N_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ4N_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQ4N :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ4N_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ4N_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQ4N :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ4N_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ4N_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ4N_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQ4N :: reserved2 [11:08] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ4N_reserved2_MASK 0x00000f00
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ4N_reserved2_SHIFT 8
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQ4N :: VDL_STEP [07:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ4N_VDL_STEP_MASK 0x000000ff
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ4N_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ4N_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_RD_DQ5P - Read channel DQ5-P VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQ5P :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ5P_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ5P_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ5P_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQ5P :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ5P_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ5P_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQ5P :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ5P_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ5P_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ5P_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQ5P :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ5P_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ5P_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQ5P :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ5P_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ5P_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ5P_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQ5P :: reserved2 [11:08] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ5P_reserved2_MASK 0x00000f00
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ5P_reserved2_SHIFT 8
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQ5P :: VDL_STEP [07:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ5P_VDL_STEP_MASK 0x000000ff
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ5P_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ5P_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_RD_DQ5N - Read channel DQ5-N VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQ5N :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ5N_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ5N_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ5N_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQ5N :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ5N_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ5N_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQ5N :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ5N_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ5N_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ5N_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQ5N :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ5N_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ5N_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQ5N :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ5N_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ5N_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ5N_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQ5N :: reserved2 [11:08] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ5N_reserved2_MASK 0x00000f00
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ5N_reserved2_SHIFT 8
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQ5N :: VDL_STEP [07:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ5N_VDL_STEP_MASK 0x000000ff
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ5N_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ5N_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_RD_DQ6P - Read channel DQ6-P VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQ6P :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ6P_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ6P_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ6P_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQ6P :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ6P_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ6P_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQ6P :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ6P_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ6P_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ6P_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQ6P :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ6P_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ6P_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQ6P :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ6P_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ6P_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ6P_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQ6P :: reserved2 [11:08] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ6P_reserved2_MASK 0x00000f00
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ6P_reserved2_SHIFT 8
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQ6P :: VDL_STEP [07:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ6P_VDL_STEP_MASK 0x000000ff
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ6P_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ6P_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_RD_DQ6N - Read channel DQ6-N VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQ6N :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ6N_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ6N_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ6N_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQ6N :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ6N_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ6N_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQ6N :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ6N_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ6N_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ6N_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQ6N :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ6N_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ6N_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQ6N :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ6N_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ6N_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ6N_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQ6N :: reserved2 [11:08] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ6N_reserved2_MASK 0x00000f00
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ6N_reserved2_SHIFT 8
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQ6N :: VDL_STEP [07:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ6N_VDL_STEP_MASK 0x000000ff
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ6N_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ6N_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_RD_DQ7P - Read channel DQ7-P VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQ7P :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ7P_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ7P_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ7P_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQ7P :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ7P_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ7P_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQ7P :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ7P_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ7P_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ7P_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQ7P :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ7P_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ7P_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQ7P :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ7P_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ7P_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ7P_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQ7P :: reserved2 [11:08] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ7P_reserved2_MASK 0x00000f00
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ7P_reserved2_SHIFT 8
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQ7P :: VDL_STEP [07:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ7P_VDL_STEP_MASK 0x000000ff
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ7P_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ7P_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_RD_DQ7N - Read channel DQ7-N VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQ7N :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ7N_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ7N_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ7N_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQ7N :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ7N_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ7N_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQ7N :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ7N_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ7N_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ7N_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQ7N :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ7N_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ7N_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQ7N :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ7N_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ7N_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ7N_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQ7N :: reserved2 [11:08] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ7N_reserved2_MASK 0x00000f00
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ7N_reserved2_SHIFT 8
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQ7N :: VDL_STEP [07:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ7N_VDL_STEP_MASK 0x000000ff
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ7N_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ7N_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_RD_DMP - Read channel DM-P VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DMP :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DMP_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DMP_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DMP_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DMP :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DMP_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DMP_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DMP :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DMP_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DMP_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DMP_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DMP :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DMP_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DMP_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DMP :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DMP_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DMP_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DMP_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DMP :: reserved2 [11:08] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DMP_reserved2_MASK 0x00000f00
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DMP_reserved2_SHIFT 8
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DMP :: VDL_STEP [07:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DMP_VDL_STEP_MASK 0x000000ff
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DMP_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DMP_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_RD_DMN - Read channel DM-N VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DMN :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DMN_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DMN_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DMN_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DMN :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DMN_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DMN_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DMN :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DMN_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DMN_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DMN_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DMN :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DMN_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DMN_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DMN :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DMN_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DMN_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DMN_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DMN :: reserved2 [11:08] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DMN_reserved2_MASK 0x00000f00
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DMN_reserved2_SHIFT 8
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DMN :: VDL_STEP [07:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DMN_VDL_STEP_MASK 0x000000ff
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DMN_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DMN_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_RD_EDCP - Read channel EDC-P VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_EDCP :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_EDCP_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_EDCP_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_EDCP_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_EDCP :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_EDCP_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_EDCP_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_EDCP :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_EDCP_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_EDCP_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_EDCP_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_EDCP :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_EDCP_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_EDCP_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_EDCP :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_EDCP_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_EDCP_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_EDCP_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_EDCP :: reserved2 [11:08] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_EDCP_reserved2_MASK 0x00000f00
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_EDCP_reserved2_SHIFT 8
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_EDCP :: VDL_STEP [07:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_EDCP_VDL_STEP_MASK 0x000000ff
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_EDCP_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_EDCP_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_RD_EDCN - Read channel EDC-N VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_EDCN :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_EDCN_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_EDCN_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_EDCN_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_EDCN :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_EDCN_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_EDCN_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_EDCN :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_EDCN_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_EDCN_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_EDCN_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_EDCN :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_EDCN_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_EDCN_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_EDCN :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_EDCN_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_EDCN_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_EDCN_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_EDCN :: reserved2 [11:08] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_EDCN_reserved2_MASK 0x00000f00
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_EDCN_reserved2_SHIFT 8
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_EDCN :: VDL_STEP [07:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_EDCN_VDL_STEP_MASK 0x000000ff
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_EDCN_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_EDCN_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_RD_EN_CS0 - Read channel CS_N[0] read enable VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_EN_CS0 :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_EN_CS0_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_EN_CS0_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_EN_CS0_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_EN_CS0 :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_EN_CS0_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_EN_CS0_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_EN_CS0 :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_EN_CS0_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_EN_CS0_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_EN_CS0_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_EN_CS0 :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_EN_CS0_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_EN_CS0_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_EN_CS0 :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_EN_CS0_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_EN_CS0_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_EN_CS0_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_EN_CS0 :: reserved2 [11:08] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_EN_CS0_reserved2_MASK 0x00000f00
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_EN_CS0_reserved2_SHIFT 8
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_EN_CS0 :: VDL_STEP [07:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_EN_CS0_VDL_STEP_MASK 0x000000ff
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_EN_CS0_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_EN_CS0_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_RD_EN_CS1 - Read channel CS_N[1] read enable VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_EN_CS1 :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_EN_CS1_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_EN_CS1_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_EN_CS1_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_EN_CS1 :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_EN_CS1_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_EN_CS1_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_EN_CS1 :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_EN_CS1_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_EN_CS1_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_EN_CS1_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_EN_CS1 :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_EN_CS1_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_EN_CS1_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_EN_CS1 :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_EN_CS1_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_EN_CS1_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_EN_CS1_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_EN_CS1 :: reserved2 [11:08] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_EN_CS1_reserved2_MASK 0x00000f00
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_EN_CS1_reserved2_SHIFT 8
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_EN_CS1 :: VDL_STEP [07:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_EN_CS1_VDL_STEP_MASK 0x000000ff
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_EN_CS1_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_EN_CS1_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CLK_CONTROL - DDR interface signal Write Leveling CLK VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CLK_CONTROL :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CLK_CONTROL_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CLK_CONTROL_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CLK_CONTROL_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CLK_CONTROL :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CLK_CONTROL_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CLK_CONTROL_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CLK_CONTROL :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CLK_CONTROL_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CLK_CONTROL_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CLK_CONTROL_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CLK_CONTROL :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CLK_CONTROL_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CLK_CONTROL_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CLK_CONTROL :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CLK_CONTROL_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CLK_CONTROL_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CLK_CONTROL_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CLK_CONTROL :: reserved2 [11:09] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CLK_CONTROL_reserved2_MASK 0x00000e00
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CLK_CONTROL_reserved2_SHIFT 9
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CLK_CONTROL :: VDL_STEP [08:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CLK_CONTROL_VDL_STEP_MASK 0x000001ff
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CLK_CONTROL_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CLK_CONTROL_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_LDE_CONTROL - DDR interface signal Write Leveling Capture Enable VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_LDE_CONTROL :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_LDE_CONTROL_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_LDE_CONTROL_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_LDE_CONTROL_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_LDE_CONTROL :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_LDE_CONTROL_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_LDE_CONTROL_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_LDE_CONTROL :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_LDE_CONTROL_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_LDE_CONTROL_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_LDE_CONTROL_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_LDE_CONTROL :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_LDE_CONTROL_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_LDE_CONTROL_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_LDE_CONTROL :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_LDE_CONTROL_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_LDE_CONTROL_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_LDE_CONTROL_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_LDE_CONTROL :: reserved2 [11:09] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_LDE_CONTROL_reserved2_MASK 0x00000e00
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_LDE_CONTROL_reserved2_SHIFT 9
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_LDE_CONTROL :: VDL_STEP [08:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_LDE_CONTROL_VDL_STEP_MASK 0x000001ff
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_LDE_CONTROL_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_LDE_CONTROL_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *RD_EN_DLY_CYC - Read enable bit-clock cycle delay control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_2_0 :: RD_EN_DLY_CYC :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_RD_EN_DLY_CYC_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_RD_EN_DLY_CYC_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_RD_EN_DLY_CYC_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: RD_EN_DLY_CYC :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_RD_EN_DLY_CYC_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_RD_EN_DLY_CYC_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: RD_EN_DLY_CYC :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_RD_EN_DLY_CYC_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_RD_EN_DLY_CYC_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_RD_EN_DLY_CYC_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: RD_EN_DLY_CYC :: reserved1 [15:08] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_RD_EN_DLY_CYC_reserved1_MASK 0x0000ff00
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_RD_EN_DLY_CYC_reserved1_SHIFT 8
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: RD_EN_DLY_CYC :: CS1_CYCLES [07:04] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_RD_EN_DLY_CYC_CS1_CYCLES_MASK 0x000000f0
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_RD_EN_DLY_CYC_CS1_CYCLES_SHIFT 4
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_RD_EN_DLY_CYC_CS1_CYCLES_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: RD_EN_DLY_CYC :: CS0_CYCLES [03:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_RD_EN_DLY_CYC_CS0_CYCLES_MASK 0x0000000f
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_RD_EN_DLY_CYC_CS0_CYCLES_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_RD_EN_DLY_CYC_CS0_CYCLES_DEFAULT 0x00000000
-
-/***************************************************************************
- *WR_CHAN_DLY_CYC - Write leveling bit-clock cycle delay control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_2_0 :: WR_CHAN_DLY_CYC :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_WR_CHAN_DLY_CYC_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_WR_CHAN_DLY_CYC_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_WR_CHAN_DLY_CYC_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: WR_CHAN_DLY_CYC :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_WR_CHAN_DLY_CYC_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_WR_CHAN_DLY_CYC_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: WR_CHAN_DLY_CYC :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_WR_CHAN_DLY_CYC_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_WR_CHAN_DLY_CYC_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_WR_CHAN_DLY_CYC_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: WR_CHAN_DLY_CYC :: reserved1 [15:03] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_WR_CHAN_DLY_CYC_reserved1_MASK 0x0000fff8
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_WR_CHAN_DLY_CYC_reserved1_SHIFT 3
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: WR_CHAN_DLY_CYC :: CYCLES [02:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_WR_CHAN_DLY_CYC_CYCLES_MASK 0x00000007
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_WR_CHAN_DLY_CYC_CYCLES_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_WR_CHAN_DLY_CYC_CYCLES_DEFAULT 0x00000000
-
-/***************************************************************************
- *READ_CONTROL - Read channel datapath control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_2_0 :: READ_CONTROL :: reserved0 [31:05] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_READ_CONTROL_reserved0_MASK 0xffffffe0
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_READ_CONTROL_reserved0_SHIFT 5
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: READ_CONTROL :: MODE [04:04] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_READ_CONTROL_MODE_MASK 0x00000010
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_READ_CONTROL_MODE_SHIFT 4
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_READ_CONTROL_MODE_DEFAULT 0x00000001
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: READ_CONTROL :: reserved1 [03:03] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_READ_CONTROL_reserved1_MASK 0x00000008
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_READ_CONTROL_reserved1_SHIFT 3
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: READ_CONTROL :: RD_DATA_DLY [02:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_READ_CONTROL_RD_DATA_DLY_MASK 0x00000007
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_READ_CONTROL_RD_DATA_DLY_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_READ_CONTROL_RD_DATA_DLY_DEFAULT 0x00000007
-
-/***************************************************************************
- *READ_FIFO_ADDR - Read fifo addresss pointer register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_2_0 :: READ_FIFO_ADDR :: reserved0 [31:03] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_READ_FIFO_ADDR_reserved0_MASK 0xfffffff8
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_READ_FIFO_ADDR_reserved0_SHIFT 3
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: READ_FIFO_ADDR :: ADDR [02:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_READ_FIFO_ADDR_ADDR_MASK 0x00000007
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_READ_FIFO_ADDR_ADDR_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_READ_FIFO_ADDR_ADDR_DEFAULT 0x00000000
-
-/***************************************************************************
- *READ_FIFO_DATA - Read fifo data register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_2_0 :: READ_FIFO_DATA :: DATA [31:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_READ_FIFO_DATA_DATA_MASK 0xffffffff
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_READ_FIFO_DATA_DATA_SHIFT 0
-
-/***************************************************************************
- *READ_FIFO_DM_DBI - Read fifo dm/dbi register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_2_0 :: READ_FIFO_DM_DBI :: reserved0 [31:04] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_READ_FIFO_DM_DBI_reserved0_MASK 0xfffffff0
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_READ_FIFO_DM_DBI_reserved0_SHIFT 4
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: READ_FIFO_DM_DBI :: DM_DBI [03:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_READ_FIFO_DM_DBI_DM_DBI_MASK 0x0000000f
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_READ_FIFO_DM_DBI_DM_DBI_SHIFT 0
-
-/***************************************************************************
- *READ_FIFO_STATUS - Read fifo status register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_2_0 :: READ_FIFO_STATUS :: reserved0 [31:02] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_READ_FIFO_STATUS_reserved0_MASK 0xfffffffc
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_READ_FIFO_STATUS_reserved0_SHIFT 2
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: READ_FIFO_STATUS :: OVERFLOW [01:01] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_READ_FIFO_STATUS_OVERFLOW_MASK 0x00000002
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_READ_FIFO_STATUS_OVERFLOW_SHIFT 1
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_READ_FIFO_STATUS_OVERFLOW_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: READ_FIFO_STATUS :: UNDERFLOW [00:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_READ_FIFO_STATUS_UNDERFLOW_MASK 0x00000001
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_READ_FIFO_STATUS_UNDERFLOW_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_READ_FIFO_STATUS_UNDERFLOW_DEFAULT 0x00000000
-
-/***************************************************************************
- *READ_FIFO_CLEAR - Read fifo status clear register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_2_0 :: READ_FIFO_CLEAR :: reserved0 [31:01] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_READ_FIFO_CLEAR_reserved0_MASK 0xfffffffe
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_READ_FIFO_CLEAR_reserved0_SHIFT 1
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: READ_FIFO_CLEAR :: CLEAR [00:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_READ_FIFO_CLEAR_CLEAR_MASK 0x00000001
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_READ_FIFO_CLEAR_CLEAR_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_READ_FIFO_CLEAR_CLEAR_DEFAULT 0x00000000
-
-/***************************************************************************
- *IDLE_PAD_CONTROL - Idle mode SSTL pad control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_2_0 :: IDLE_PAD_CONTROL :: IDLE [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_IDLE_PAD_CONTROL_IDLE_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_IDLE_PAD_CONTROL_IDLE_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_IDLE_PAD_CONTROL_IDLE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: IDLE_PAD_CONTROL :: reserved0 [30:20] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_IDLE_PAD_CONTROL_reserved0_MASK 0x7ff00000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_IDLE_PAD_CONTROL_reserved0_SHIFT 20
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: IDLE_PAD_CONTROL :: AUTO_DQ_RXENB_MODE [19:18] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_IDLE_PAD_CONTROL_AUTO_DQ_RXENB_MODE_MASK 0x000c0000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_IDLE_PAD_CONTROL_AUTO_DQ_RXENB_MODE_SHIFT 18
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_IDLE_PAD_CONTROL_AUTO_DQ_RXENB_MODE_DEFAULT 0x00000001
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: IDLE_PAD_CONTROL :: AUTO_DQ_IDDQ_MODE [17:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_IDLE_PAD_CONTROL_AUTO_DQ_IDDQ_MODE_MASK 0x00030000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_IDLE_PAD_CONTROL_AUTO_DQ_IDDQ_MODE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_IDLE_PAD_CONTROL_AUTO_DQ_IDDQ_MODE_DEFAULT 0x00000001
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: IDLE_PAD_CONTROL :: reserved_for_padding1 [15:15] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_IDLE_PAD_CONTROL_reserved_for_padding1_MASK 0x00008000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_IDLE_PAD_CONTROL_reserved_for_padding1_SHIFT 15
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: IDLE_PAD_CONTROL :: IO_IDLE_ENABLE [14:04] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_IDLE_PAD_CONTROL_IO_IDLE_ENABLE_MASK 0x00007ff0
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_IDLE_PAD_CONTROL_IO_IDLE_ENABLE_SHIFT 4
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_IDLE_PAD_CONTROL_IO_IDLE_ENABLE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: IDLE_PAD_CONTROL :: RXENB [03:03] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_IDLE_PAD_CONTROL_RXENB_MASK 0x00000008
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_IDLE_PAD_CONTROL_RXENB_SHIFT 3
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_IDLE_PAD_CONTROL_RXENB_DEFAULT 0x00000001
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: IDLE_PAD_CONTROL :: IDDQ [02:02] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_IDLE_PAD_CONTROL_IDDQ_MASK 0x00000004
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_IDLE_PAD_CONTROL_IDDQ_SHIFT 2
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_IDLE_PAD_CONTROL_IDDQ_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: IDLE_PAD_CONTROL :: DOUT_N [01:01] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_IDLE_PAD_CONTROL_DOUT_N_MASK 0x00000002
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_IDLE_PAD_CONTROL_DOUT_N_SHIFT 1
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: IDLE_PAD_CONTROL :: DOUT_P [00:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_IDLE_PAD_CONTROL_DOUT_P_MASK 0x00000001
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_IDLE_PAD_CONTROL_DOUT_P_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_IDLE_PAD_CONTROL_DOUT_P_DEFAULT 0x00000000
-
-/***************************************************************************
- *DRIVE_PAD_CTL - SSTL pad drive characteristics control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_2_0 :: DRIVE_PAD_CTL :: reserved0 [31:30] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_DRIVE_PAD_CTL_reserved0_MASK 0xc0000000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_DRIVE_PAD_CTL_reserved0_SHIFT 30
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: DRIVE_PAD_CTL :: BL_PD_IDLE_STRENGTH [29:25] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_DRIVE_PAD_CTL_BL_PD_IDLE_STRENGTH_MASK 0x3e000000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_DRIVE_PAD_CTL_BL_PD_IDLE_STRENGTH_SHIFT 25
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_DRIVE_PAD_CTL_BL_PD_IDLE_STRENGTH_DEFAULT 0x0000001f
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: DRIVE_PAD_CTL :: BL_ND_IDLE_STRENGTH [24:20] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_DRIVE_PAD_CTL_BL_ND_IDLE_STRENGTH_MASK 0x01f00000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_DRIVE_PAD_CTL_BL_ND_IDLE_STRENGTH_SHIFT 20
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_DRIVE_PAD_CTL_BL_ND_IDLE_STRENGTH_DEFAULT 0x0000001f
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: DRIVE_PAD_CTL :: BL_PD_TERM_STRENGTH [19:15] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_DRIVE_PAD_CTL_BL_PD_TERM_STRENGTH_MASK 0x000f8000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_DRIVE_PAD_CTL_BL_PD_TERM_STRENGTH_SHIFT 15
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_DRIVE_PAD_CTL_BL_PD_TERM_STRENGTH_DEFAULT 0x00000008
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: DRIVE_PAD_CTL :: BL_ND_TERM_STRENGTH [14:10] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_DRIVE_PAD_CTL_BL_ND_TERM_STRENGTH_MASK 0x00007c00
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_DRIVE_PAD_CTL_BL_ND_TERM_STRENGTH_SHIFT 10
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_DRIVE_PAD_CTL_BL_ND_TERM_STRENGTH_DEFAULT 0x00000008
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: DRIVE_PAD_CTL :: BL_PD_STRENGTH [09:05] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_DRIVE_PAD_CTL_BL_PD_STRENGTH_MASK 0x000003e0
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_DRIVE_PAD_CTL_BL_PD_STRENGTH_SHIFT 5
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_DRIVE_PAD_CTL_BL_PD_STRENGTH_DEFAULT 0x0000001f
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: DRIVE_PAD_CTL :: BL_ND_STRENGTH [04:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_DRIVE_PAD_CTL_BL_ND_STRENGTH_MASK 0x0000001f
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_DRIVE_PAD_CTL_BL_ND_STRENGTH_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_DRIVE_PAD_CTL_BL_ND_STRENGTH_DEFAULT 0x0000001f
-
-/***************************************************************************
- *RD_EN_DRIVE_PAD_CTL - SSTL read enable pad drive characteristics control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_2_0 :: RD_EN_DRIVE_PAD_CTL :: reserved0 [31:20] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_RD_EN_DRIVE_PAD_CTL_reserved0_MASK 0xfff00000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_RD_EN_DRIVE_PAD_CTL_reserved0_SHIFT 20
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: RD_EN_DRIVE_PAD_CTL :: EDC_RD_EN_PD_STRENGTH [19:15] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_RD_EN_DRIVE_PAD_CTL_EDC_RD_EN_PD_STRENGTH_MASK 0x000f8000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_RD_EN_DRIVE_PAD_CTL_EDC_RD_EN_PD_STRENGTH_SHIFT 15
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_RD_EN_DRIVE_PAD_CTL_EDC_RD_EN_PD_STRENGTH_DEFAULT 0x0000001f
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: RD_EN_DRIVE_PAD_CTL :: EDC_RD_EN_ND_STRENGTH [14:10] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_RD_EN_DRIVE_PAD_CTL_EDC_RD_EN_ND_STRENGTH_MASK 0x00007c00
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_RD_EN_DRIVE_PAD_CTL_EDC_RD_EN_ND_STRENGTH_SHIFT 10
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_RD_EN_DRIVE_PAD_CTL_EDC_RD_EN_ND_STRENGTH_DEFAULT 0x0000001f
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: RD_EN_DRIVE_PAD_CTL :: BL_RD_EN_PD_STRENGTH [09:05] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_RD_EN_DRIVE_PAD_CTL_BL_RD_EN_PD_STRENGTH_MASK 0x000003e0
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_RD_EN_DRIVE_PAD_CTL_BL_RD_EN_PD_STRENGTH_SHIFT 5
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_RD_EN_DRIVE_PAD_CTL_BL_RD_EN_PD_STRENGTH_DEFAULT 0x0000001f
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: RD_EN_DRIVE_PAD_CTL :: BL_RD_EN_ND_STRENGTH [04:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_RD_EN_DRIVE_PAD_CTL_BL_RD_EN_ND_STRENGTH_MASK 0x0000001f
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_RD_EN_DRIVE_PAD_CTL_BL_RD_EN_ND_STRENGTH_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_RD_EN_DRIVE_PAD_CTL_BL_RD_EN_ND_STRENGTH_DEFAULT 0x0000001f
-
-/***************************************************************************
- *STATIC_PAD_CTL - pad rx and tx characteristics control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_2_0 :: STATIC_PAD_CTL :: reserved0 [31:21] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_STATIC_PAD_CTL_reserved0_MASK 0xffe00000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_STATIC_PAD_CTL_reserved0_SHIFT 21
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: STATIC_PAD_CTL :: DQS_MODE [20:20] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_STATIC_PAD_CTL_DQS_MODE_MASK 0x00100000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_STATIC_PAD_CTL_DQS_MODE_SHIFT 20
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_STATIC_PAD_CTL_DQS_MODE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: STATIC_PAD_CTL :: reserved1 [19:18] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_STATIC_PAD_CTL_reserved1_MASK 0x000c0000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_STATIC_PAD_CTL_reserved1_SHIFT 18
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: STATIC_PAD_CTL :: EDC_MODE [17:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_STATIC_PAD_CTL_EDC_MODE_MASK 0x00030000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_STATIC_PAD_CTL_EDC_MODE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_STATIC_PAD_CTL_EDC_MODE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: STATIC_PAD_CTL :: reserved2 [15:15] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_STATIC_PAD_CTL_reserved2_MASK 0x00008000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_STATIC_PAD_CTL_reserved2_SHIFT 15
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: STATIC_PAD_CTL :: WDBI_ENABLE [14:14] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_STATIC_PAD_CTL_WDBI_ENABLE_MASK 0x00004000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_STATIC_PAD_CTL_WDBI_ENABLE_SHIFT 14
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_STATIC_PAD_CTL_WDBI_ENABLE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: STATIC_PAD_CTL :: RDBI_ENABLE [13:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_STATIC_PAD_CTL_RDBI_ENABLE_MASK 0x00002000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_STATIC_PAD_CTL_RDBI_ENABLE_SHIFT 13
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_STATIC_PAD_CTL_RDBI_ENABLE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: STATIC_PAD_CTL :: DM_MODE [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_STATIC_PAD_CTL_DM_MODE_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_STATIC_PAD_CTL_DM_MODE_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_STATIC_PAD_CTL_DM_MODE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: STATIC_PAD_CTL :: reserved3 [11:11] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_STATIC_PAD_CTL_reserved3_MASK 0x00000800
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_STATIC_PAD_CTL_reserved3_SHIFT 11
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: STATIC_PAD_CTL :: DQS_TX_PAUSE [10:10] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_STATIC_PAD_CTL_DQS_TX_PAUSE_MASK 0x00000400
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_STATIC_PAD_CTL_DQS_TX_PAUSE_SHIFT 10
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_STATIC_PAD_CTL_DQS_TX_PAUSE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: STATIC_PAD_CTL :: DQS_TX_DIS [09:09] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_STATIC_PAD_CTL_DQS_TX_DIS_MASK 0x00000200
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_STATIC_PAD_CTL_DQS_TX_DIS_SHIFT 9
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_STATIC_PAD_CTL_DQS_TX_DIS_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: STATIC_PAD_CTL :: reserved4 [08:08] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_STATIC_PAD_CTL_reserved4_MASK 0x00000100
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_STATIC_PAD_CTL_reserved4_SHIFT 8
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: STATIC_PAD_CTL :: TX_MODE [07:04] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_STATIC_PAD_CTL_TX_MODE_MASK 0x000000f0
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_STATIC_PAD_CTL_TX_MODE_SHIFT 4
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_STATIC_PAD_CTL_TX_MODE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: STATIC_PAD_CTL :: reserved5 [03:03] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_STATIC_PAD_CTL_reserved5_MASK 0x00000008
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_STATIC_PAD_CTL_reserved5_SHIFT 3
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: STATIC_PAD_CTL :: RX_MODE [02:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_STATIC_PAD_CTL_RX_MODE_MASK 0x00000007
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_STATIC_PAD_CTL_RX_MODE_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_STATIC_PAD_CTL_RX_MODE_DEFAULT 0x00000000
-
-/***************************************************************************
- *WR_PREAMBLE_MODE - Write cycle preamble control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_2_0 :: WR_PREAMBLE_MODE :: reserved0 [31:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_WR_PREAMBLE_MODE_reserved0_MASK 0xffff0000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_WR_PREAMBLE_MODE_reserved0_SHIFT 16
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: WR_PREAMBLE_MODE :: DQ_POSTAM_BITS [15:14] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_WR_PREAMBLE_MODE_DQ_POSTAM_BITS_MASK 0x0000c000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_WR_PREAMBLE_MODE_DQ_POSTAM_BITS_SHIFT 14
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_WR_PREAMBLE_MODE_DQ_POSTAM_BITS_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: WR_PREAMBLE_MODE :: DQ_PREAM_BITS [13:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_WR_PREAMBLE_MODE_DQ_PREAM_BITS_MASK 0x00003000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_WR_PREAMBLE_MODE_DQ_PREAM_BITS_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_WR_PREAMBLE_MODE_DQ_PREAM_BITS_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: WR_PREAMBLE_MODE :: DQS [11:08] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_WR_PREAMBLE_MODE_DQS_MASK 0x00000f00
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_WR_PREAMBLE_MODE_DQS_SHIFT 8
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_WR_PREAMBLE_MODE_DQS_DEFAULT 0x0000000e
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: WR_PREAMBLE_MODE :: reserved1 [07:05] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_WR_PREAMBLE_MODE_reserved1_MASK 0x000000e0
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_WR_PREAMBLE_MODE_reserved1_SHIFT 5
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: WR_PREAMBLE_MODE :: DQS_POSTAM_BITS [04:03] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_WR_PREAMBLE_MODE_DQS_POSTAM_BITS_MASK 0x00000018
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_WR_PREAMBLE_MODE_DQS_POSTAM_BITS_SHIFT 3
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_WR_PREAMBLE_MODE_DQS_POSTAM_BITS_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: WR_PREAMBLE_MODE :: DQS_PREAM_BITS [02:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_WR_PREAMBLE_MODE_DQS_PREAM_BITS_MASK 0x00000007
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_WR_PREAMBLE_MODE_DQS_PREAM_BITS_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_WR_PREAMBLE_MODE_DQS_PREAM_BITS_DEFAULT 0x00000002
-
-/***************************************************************************
- *ODT_CONTROL - Read channel ODT control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_2_0 :: ODT_CONTROL :: reserved_for_padding0 [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_ODT_CONTROL_reserved_for_padding0_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_ODT_CONTROL_reserved_for_padding0_SHIFT 31
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: ODT_CONTROL :: reserved1 [30:10] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_ODT_CONTROL_reserved1_MASK 0x7ffffc00
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_ODT_CONTROL_reserved1_SHIFT 10
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: ODT_CONTROL :: ODT_ENABLE [09:09] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_ODT_CONTROL_ODT_ENABLE_MASK 0x00000200
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_ODT_CONTROL_ODT_ENABLE_SHIFT 9
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_ODT_CONTROL_ODT_ENABLE_DEFAULT 0x00000001
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: ODT_CONTROL :: ODT_DELAY [08:06] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_ODT_CONTROL_ODT_DELAY_MASK 0x000001c0
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_ODT_CONTROL_ODT_DELAY_SHIFT 6
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_ODT_CONTROL_ODT_DELAY_DEFAULT 0x00000001
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: ODT_CONTROL :: ODT_POST_LENGTH [05:03] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_ODT_CONTROL_ODT_POST_LENGTH_MASK 0x00000038
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_ODT_CONTROL_ODT_POST_LENGTH_SHIFT 3
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_ODT_CONTROL_ODT_POST_LENGTH_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: ODT_CONTROL :: ODT_PRE_LENGTH [02:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_ODT_CONTROL_ODT_PRE_LENGTH_MASK 0x00000007
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_ODT_CONTROL_ODT_PRE_LENGTH_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_ODT_CONTROL_ODT_PRE_LENGTH_DEFAULT 0x00000003
-
-/***************************************************************************
- *EDC_DPD_CONTROL - GDDR5M EDC digital phase detector control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_2_0 :: EDC_DPD_CONTROL :: reserved0 [31:06] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_DPD_CONTROL_reserved0_MASK 0xffffffc0
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_DPD_CONTROL_reserved0_SHIFT 6
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: EDC_DPD_CONTROL :: DQS_PHASE_OVERRIDE_VALUE [05:05] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_DPD_CONTROL_DQS_PHASE_OVERRIDE_VALUE_MASK 0x00000020
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_DPD_CONTROL_DQS_PHASE_OVERRIDE_VALUE_SHIFT 5
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_DPD_CONTROL_DQS_PHASE_OVERRIDE_VALUE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: EDC_DPD_CONTROL :: DQS_PHASE_OVERRIDE_ENABLE [04:04] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_DPD_CONTROL_DQS_PHASE_OVERRIDE_ENABLE_MASK 0x00000010
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_DPD_CONTROL_DQS_PHASE_OVERRIDE_ENABLE_SHIFT 4
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_DPD_CONTROL_DQS_PHASE_OVERRIDE_ENABLE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: EDC_DPD_CONTROL :: SET_ADJ_EN [03:03] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_DPD_CONTROL_SET_ADJ_EN_MASK 0x00000008
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_DPD_CONTROL_SET_ADJ_EN_SHIFT 3
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_DPD_CONTROL_SET_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: EDC_DPD_CONTROL :: UPDATE [02:02] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_DPD_CONTROL_UPDATE_MASK 0x00000004
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_DPD_CONTROL_UPDATE_SHIFT 2
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_DPD_CONTROL_UPDATE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: EDC_DPD_CONTROL :: MONITOR [01:01] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_DPD_CONTROL_MONITOR_MASK 0x00000002
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_DPD_CONTROL_MONITOR_SHIFT 1
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_DPD_CONTROL_MONITOR_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: EDC_DPD_CONTROL :: INIT [00:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_DPD_CONTROL_INIT_MASK 0x00000001
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_DPD_CONTROL_INIT_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_DPD_CONTROL_INIT_DEFAULT 0x00000000
-
-/***************************************************************************
- *EDC_DPD_STATUS - GDDR5M EDC digital phase detector status register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_2_0 :: EDC_DPD_STATUS :: reserved0 [31:25] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_DPD_STATUS_reserved0_MASK 0xfe000000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_DPD_STATUS_reserved0_SHIFT 25
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: EDC_DPD_STATUS :: CURRENT_DQS_PHASE [24:24] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_DPD_STATUS_CURRENT_DQS_PHASE_MASK 0x01000000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_DPD_STATUS_CURRENT_DQS_PHASE_SHIFT 24
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_DPD_STATUS_CURRENT_DQS_PHASE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: EDC_DPD_STATUS :: CURRENT_VDL_SETTING [23:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_DPD_STATUS_CURRENT_VDL_SETTING_MASK 0x00ff0000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_DPD_STATUS_CURRENT_VDL_SETTING_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_DPD_STATUS_CURRENT_VDL_SETTING_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: EDC_DPD_STATUS :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_DPD_STATUS_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_DPD_STATUS_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: EDC_DPD_STATUS :: INIT_DQS_PHASE [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_DPD_STATUS_INIT_DQS_PHASE_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_DPD_STATUS_INIT_DQS_PHASE_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_DPD_STATUS_INIT_DQS_PHASE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: EDC_DPD_STATUS :: INIT_VDL_SETTING [11:04] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_DPD_STATUS_INIT_VDL_SETTING_MASK 0x00000ff0
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_DPD_STATUS_INIT_VDL_SETTING_SHIFT 4
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_DPD_STATUS_INIT_VDL_SETTING_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: EDC_DPD_STATUS :: EDGE_ERROR [03:03] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_DPD_STATUS_EDGE_ERROR_MASK 0x00000008
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_DPD_STATUS_EDGE_ERROR_SHIFT 3
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_DPD_STATUS_EDGE_ERROR_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: EDC_DPD_STATUS :: MONITOR_BUSY [02:02] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_DPD_STATUS_MONITOR_BUSY_MASK 0x00000004
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_DPD_STATUS_MONITOR_BUSY_SHIFT 2
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_DPD_STATUS_MONITOR_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: EDC_DPD_STATUS :: INIT_BUSY [01:01] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_DPD_STATUS_INIT_BUSY_MASK 0x00000002
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_DPD_STATUS_INIT_BUSY_SHIFT 1
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_DPD_STATUS_INIT_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: EDC_DPD_STATUS :: INIT_DONE [00:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_DPD_STATUS_INIT_DONE_MASK 0x00000001
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_DPD_STATUS_INIT_DONE_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_DPD_STATUS_INIT_DONE_DEFAULT 0x00000000
-
-/***************************************************************************
- *EDC_DPD_OUT_CONTROL - GDDR5M EDC digital phase detector output signal control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_2_0 :: EDC_DPD_OUT_CONTROL :: reserved0 [31:20] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_DPD_OUT_CONTROL_reserved0_MASK 0xfff00000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_DPD_OUT_CONTROL_reserved0_SHIFT 20
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: EDC_DPD_OUT_CONTROL :: LOWER_LIMIT [19:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_DPD_OUT_CONTROL_LOWER_LIMIT_MASK 0x000ff000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_DPD_OUT_CONTROL_LOWER_LIMIT_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_DPD_OUT_CONTROL_LOWER_LIMIT_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: EDC_DPD_OUT_CONTROL :: UPPER_LIMIT [11:04] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_DPD_OUT_CONTROL_UPPER_LIMIT_MASK 0x00000ff0
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_DPD_OUT_CONTROL_UPPER_LIMIT_SHIFT 4
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_DPD_OUT_CONTROL_UPPER_LIMIT_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: EDC_DPD_OUT_CONTROL :: reserved1 [03:01] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_DPD_OUT_CONTROL_reserved1_MASK 0x0000000e
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_DPD_OUT_CONTROL_reserved1_SHIFT 1
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: EDC_DPD_OUT_CONTROL :: ENABLE [00:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_DPD_OUT_CONTROL_ENABLE_MASK 0x00000001
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_DPD_OUT_CONTROL_ENABLE_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_DPD_OUT_CONTROL_ENABLE_DEFAULT 0x00000000
-
-/***************************************************************************
- *EDC_DPD_OUT_STATUS - GDDR5M EDC digital phase detector output signal status register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_2_0 :: EDC_DPD_OUT_STATUS :: reserved0 [31:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_DPD_OUT_STATUS_reserved0_MASK 0xfffff000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_DPD_OUT_STATUS_reserved0_SHIFT 12
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: EDC_DPD_OUT_STATUS :: VDL_SETTING [11:04] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_DPD_OUT_STATUS_VDL_SETTING_MASK 0x00000ff0
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_DPD_OUT_STATUS_VDL_SETTING_SHIFT 4
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_DPD_OUT_STATUS_VDL_SETTING_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: EDC_DPD_OUT_STATUS :: reserved1 [03:01] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_DPD_OUT_STATUS_reserved1_MASK 0x0000000e
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_DPD_OUT_STATUS_reserved1_SHIFT 1
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: EDC_DPD_OUT_STATUS :: VALID [00:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_DPD_OUT_STATUS_VALID_MASK 0x00000001
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_DPD_OUT_STATUS_VALID_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_DPD_OUT_STATUS_VALID_DEFAULT 0x00000000
-
-/***************************************************************************
- *EDC_DPD_OUT_STATUS_CLEAR - GDDR5M EDC digital phase detector output signal status clear register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_2_0 :: EDC_DPD_OUT_STATUS_CLEAR :: reserved0 [31:01] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_DPD_OUT_STATUS_CLEAR_reserved0_MASK 0xfffffffe
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_DPD_OUT_STATUS_CLEAR_reserved0_SHIFT 1
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: EDC_DPD_OUT_STATUS_CLEAR :: CLEAR [00:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_DPD_OUT_STATUS_CLEAR_CLEAR_MASK 0x00000001
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_DPD_OUT_STATUS_CLEAR_CLEAR_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_DPD_OUT_STATUS_CLEAR_CLEAR_DEFAULT 0x00000000
-
-/***************************************************************************
- *EDC_CRC_CONTROL - GDDR5M EDC signal path CRC control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_2_0 :: EDC_CRC_CONTROL :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_CRC_CONTROL_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_CRC_CONTROL_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_CRC_CONTROL_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: EDC_CRC_CONTROL :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_CRC_CONTROL_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_CRC_CONTROL_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: EDC_CRC_CONTROL :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_CRC_CONTROL_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_CRC_CONTROL_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_CRC_CONTROL_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: EDC_CRC_CONTROL :: reserved1 [15:11] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_CRC_CONTROL_reserved1_MASK 0x0000f800
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_CRC_CONTROL_reserved1_SHIFT 11
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: EDC_CRC_CONTROL :: CRCWL [10:08] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_CRC_CONTROL_CRCWL_MASK 0x00000700
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_CRC_CONTROL_CRCWL_SHIFT 8
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_CRC_CONTROL_CRCWL_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: EDC_CRC_CONTROL :: reserved2 [07:06] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_CRC_CONTROL_reserved2_MASK 0x000000c0
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_CRC_CONTROL_reserved2_SHIFT 6
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: EDC_CRC_CONTROL :: CRCRL [05:04] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_CRC_CONTROL_CRCRL_MASK 0x00000030
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_CRC_CONTROL_CRCRL_SHIFT 4
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_CRC_CONTROL_CRCRL_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: EDC_CRC_CONTROL :: reserved3 [03:03] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_CRC_CONTROL_reserved3_MASK 0x00000008
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_CRC_CONTROL_reserved3_SHIFT 3
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: EDC_CRC_CONTROL :: COUNT_MODE [02:02] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_CRC_CONTROL_COUNT_MODE_MASK 0x00000004
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_CRC_CONTROL_COUNT_MODE_SHIFT 2
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_CRC_CONTROL_COUNT_MODE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: EDC_CRC_CONTROL :: ENABLE_WR [01:01] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_CRC_CONTROL_ENABLE_WR_MASK 0x00000002
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_CRC_CONTROL_ENABLE_WR_SHIFT 1
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_CRC_CONTROL_ENABLE_WR_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: EDC_CRC_CONTROL :: ENABLE_RD [00:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_CRC_CONTROL_ENABLE_RD_MASK 0x00000001
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_CRC_CONTROL_ENABLE_RD_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_CRC_CONTROL_ENABLE_RD_DEFAULT 0x00000000
-
-/***************************************************************************
- *EDC_CRC_STATUS - GDDR5M EDC signal path CRC status register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_2_0 :: EDC_CRC_STATUS :: reserved0 [31:04] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_CRC_STATUS_reserved0_MASK 0xfffffff0
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_CRC_STATUS_reserved0_SHIFT 4
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: EDC_CRC_STATUS :: WR_FAIL [03:03] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_CRC_STATUS_WR_FAIL_MASK 0x00000008
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_CRC_STATUS_WR_FAIL_SHIFT 3
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_CRC_STATUS_WR_FAIL_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: EDC_CRC_STATUS :: WR_PASS [02:02] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_CRC_STATUS_WR_PASS_MASK 0x00000004
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_CRC_STATUS_WR_PASS_SHIFT 2
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_CRC_STATUS_WR_PASS_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: EDC_CRC_STATUS :: RD_FAIL [01:01] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_CRC_STATUS_RD_FAIL_MASK 0x00000002
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_CRC_STATUS_RD_FAIL_SHIFT 1
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_CRC_STATUS_RD_FAIL_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: EDC_CRC_STATUS :: RD_PASS [00:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_CRC_STATUS_RD_PASS_MASK 0x00000001
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_CRC_STATUS_RD_PASS_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_CRC_STATUS_RD_PASS_DEFAULT 0x00000000
-
-/***************************************************************************
- *EDC_CRC_COUNT - GDDR5M EDC signal path CRC counter register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_2_0 :: EDC_CRC_COUNT :: reserved0 [31:28] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_CRC_COUNT_reserved0_MASK 0xf0000000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_CRC_COUNT_reserved0_SHIFT 28
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: EDC_CRC_COUNT :: WR_COUNT [27:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_CRC_COUNT_WR_COUNT_MASK 0x0fff0000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_CRC_COUNT_WR_COUNT_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_CRC_COUNT_WR_COUNT_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: EDC_CRC_COUNT :: reserved1 [15:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_CRC_COUNT_reserved1_MASK 0x0000f000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_CRC_COUNT_reserved1_SHIFT 12
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: EDC_CRC_COUNT :: RD_COUNT [11:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_CRC_COUNT_RD_COUNT_MASK 0x00000fff
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_CRC_COUNT_RD_COUNT_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_CRC_COUNT_RD_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *EDC_CRC_STATUS_CLEAR - GDDR5M EDC signal path CRC counter register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_2_0 :: EDC_CRC_STATUS_CLEAR :: reserved0 [31:01] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_CRC_STATUS_CLEAR_reserved0_MASK 0xfffffffe
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_CRC_STATUS_CLEAR_reserved0_SHIFT 1
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: EDC_CRC_STATUS_CLEAR :: CLEAR [00:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_CRC_STATUS_CLEAR_CLEAR_MASK 0x00000001
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_CRC_STATUS_CLEAR_CLEAR_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_CRC_STATUS_CLEAR_CLEAR_DEFAULT 0x00000000
-
-/***************************************************************************
- *BL_SPARE_REG - Byte-Lane Spare register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_2_0 :: BL_SPARE_REG :: reserved_for_eco0 [31:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_BL_SPARE_REG_reserved_for_eco0_MASK 0xffffffff
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_BL_SPARE_REG_reserved_for_eco0_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_BL_SPARE_REG_reserved_for_eco0_DEFAULT 0x00000000
-
-#endif /* #ifndef BCHP_DDR34_PHY_BYTE_LANE_2_0_H__ */
-
-/* End of File */
diff --git a/include/linux/brcmstb/7145a0/bchp_ddr34_phy_byte_lane_2_1.h b/include/linux/brcmstb/7145a0/bchp_ddr34_phy_byte_lane_2_1.h
deleted file mode 100644
index 9197232..0000000
--- a/include/linux/brcmstb/7145a0/bchp_ddr34_phy_byte_lane_2_1.h
+++ /dev/null
@@ -1,2101 +0,0 @@
-/***************************************************************************
- * Copyright (c) 1999-2014, Broadcom Corporation
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
- *
- * Module Description:
- * DO NOT EDIT THIS FILE DIRECTLY
- *
- * This module was generated magically with RDB from a source description
- * file. You must edit the source file for changes to be made to this file.
- *
- *
- * Date: Generated on Wed Sep 3 13:17:40 2014
- * Full Compile MD5 Checksum a8ee62ccf9dde43435c825f266da463d
- * (minus title and desc)
- * MD5 Checksum e373b364a1742e13a0f9eb15fd8aa94f
- *
- * Compiled with: RDB Utility combo_header.pl
- * RDB Parser 3.0
- * unknown unknown
- * Perl Interpreter 5.008005
- * Operating System linux
- *
- * Revision History:
- *
- * $brcm_Log: $
- *
- ***************************************************************************/
-
-#ifndef BCHP_DDR34_PHY_BYTE_LANE_2_1_H__
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_H__
-
-/***************************************************************************
- *DDR34_PHY_BYTE_LANE_2_1 - DDR34 Byte Lane #2 control registers
- ***************************************************************************/
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_WR_DQS_P 0x203c6800 /* Write channel DQS-P VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_WR_DQS_N 0x203c6804 /* Write channel DQS-N VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_WR_DQ0 0x203c6808 /* Write channel DQ0 VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_WR_DQ1 0x203c680c /* Write channel DQ1 VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_WR_DQ2 0x203c6810 /* Write channel DQ2 VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_WR_DQ3 0x203c6814 /* Write channel DQ3 VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_WR_DQ4 0x203c6818 /* Write channel DQ4 VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_WR_DQ5 0x203c681c /* Write channel DQ5 VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_WR_DQ6 0x203c6820 /* Write channel DQ6 VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_WR_DQ7 0x203c6824 /* Write channel DQ7 VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_WR_DM 0x203c6828 /* Write channel DM VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_WR_EDC 0x203c682c /* Write channel EDC VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQSP 0x203c6830 /* Read channel DQSP VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQSN 0x203c6834 /* Read channel DQSP VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ0P 0x203c6838 /* Read channel DQ0-P VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ0N 0x203c683c /* Read channel DQ0-N VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ1P 0x203c6840 /* Read channel DQ1-P VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ1N 0x203c6844 /* Read channel DQ1-N VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ2P 0x203c6848 /* Read channel DQ2-P VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ2N 0x203c684c /* Read channel DQ2-N VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ3P 0x203c6850 /* Read channel DQ3-P VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ3N 0x203c6854 /* Read channel DQ3-N VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ4P 0x203c6858 /* Read channel DQ4-P VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ4N 0x203c685c /* Read channel DQ4-N VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ5P 0x203c6860 /* Read channel DQ5-P VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ5N 0x203c6864 /* Read channel DQ5-N VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ6P 0x203c6868 /* Read channel DQ6-P VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ6N 0x203c686c /* Read channel DQ6-N VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ7P 0x203c6870 /* Read channel DQ7-P VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ7N 0x203c6874 /* Read channel DQ7-N VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DMP 0x203c6878 /* Read channel DM-P VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DMN 0x203c687c /* Read channel DM-N VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_EDCP 0x203c6880 /* Read channel EDC-P VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_EDCN 0x203c6884 /* Read channel EDC-N VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_EN_CS0 0x203c6888 /* Read channel CS_N[0] read enable VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_EN_CS1 0x203c688c /* Read channel CS_N[1] read enable VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CLK_CONTROL 0x203c6890 /* DDR interface signal Write Leveling CLK VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_LDE_CONTROL 0x203c6894 /* DDR interface signal Write Leveling Capture Enable VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_RD_EN_DLY_CYC 0x203c68a0 /* Read enable bit-clock cycle delay control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_WR_CHAN_DLY_CYC 0x203c68a4 /* Write leveling bit-clock cycle delay control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_READ_CONTROL 0x203c68b0 /* Read channel datapath control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_READ_FIFO_ADDR 0x203c68b4 /* Read fifo addresss pointer register */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_READ_FIFO_DATA 0x203c68b8 /* Read fifo data register */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_READ_FIFO_DM_DBI 0x203c68bc /* Read fifo dm/dbi register */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_READ_FIFO_STATUS 0x203c68c0 /* Read fifo status register */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_READ_FIFO_CLEAR 0x203c68c4 /* Read fifo status clear register */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_IDLE_PAD_CONTROL 0x203c68c8 /* Idle mode SSTL pad control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_DRIVE_PAD_CTL 0x203c68cc /* SSTL pad drive characteristics control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_RD_EN_DRIVE_PAD_CTL 0x203c68d0 /* SSTL read enable pad drive characteristics control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_STATIC_PAD_CTL 0x203c68d4 /* pad rx and tx characteristics control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_WR_PREAMBLE_MODE 0x203c68d8 /* Write cycle preamble control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_ODT_CONTROL 0x203c68e0 /* Read channel ODT control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_EDC_DPD_CONTROL 0x203c68f0 /* GDDR5M EDC digital phase detector control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_EDC_DPD_STATUS 0x203c68f4 /* GDDR5M EDC digital phase detector status register */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_EDC_DPD_OUT_CONTROL 0x203c68f8 /* GDDR5M EDC digital phase detector output signal control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_EDC_DPD_OUT_STATUS 0x203c68fc /* GDDR5M EDC digital phase detector output signal status register */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_EDC_DPD_OUT_STATUS_CLEAR 0x203c6900 /* GDDR5M EDC digital phase detector output signal status clear register */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_EDC_CRC_CONTROL 0x203c6904 /* GDDR5M EDC signal path CRC control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_EDC_CRC_STATUS 0x203c6908 /* GDDR5M EDC signal path CRC status register */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_EDC_CRC_COUNT 0x203c690c /* GDDR5M EDC signal path CRC counter register */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_EDC_CRC_STATUS_CLEAR 0x203c6910 /* GDDR5M EDC signal path CRC counter register */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_BL_SPARE_REG 0x203c6914 /* Byte-Lane Spare register */
-
-/***************************************************************************
- *VDL_CONTROL_WR_DQS_P - Write channel DQS-P VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_2_1 :: VDL_CONTROL_WR_DQS_P :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_WR_DQS_P_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_WR_DQS_P_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_WR_DQS_P_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_1 :: VDL_CONTROL_WR_DQS_P :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_WR_DQS_P_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_WR_DQS_P_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_2_1 :: VDL_CONTROL_WR_DQS_P :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_WR_DQS_P_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_WR_DQS_P_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_WR_DQS_P_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_1 :: VDL_CONTROL_WR_DQS_P :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_WR_DQS_P_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_WR_DQS_P_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_2_1 :: VDL_CONTROL_WR_DQS_P :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_WR_DQS_P_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_WR_DQS_P_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_WR_DQS_P_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_1 :: VDL_CONTROL_WR_DQS_P :: reserved2 [11:09] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_WR_DQS_P_reserved2_MASK 0x00000e00
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_WR_DQS_P_reserved2_SHIFT 9
-
-/* DDR34_PHY_BYTE_LANE_2_1 :: VDL_CONTROL_WR_DQS_P :: VDL_STEP [08:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_WR_DQS_P_VDL_STEP_MASK 0x000001ff
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_WR_DQS_P_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_WR_DQS_P_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_WR_DQS_N - Write channel DQS-N VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_2_1 :: VDL_CONTROL_WR_DQS_N :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_WR_DQS_N_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_WR_DQS_N_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_WR_DQS_N_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_1 :: VDL_CONTROL_WR_DQS_N :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_WR_DQS_N_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_WR_DQS_N_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_2_1 :: VDL_CONTROL_WR_DQS_N :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_WR_DQS_N_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_WR_DQS_N_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_WR_DQS_N_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_1 :: VDL_CONTROL_WR_DQS_N :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_WR_DQS_N_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_WR_DQS_N_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_2_1 :: VDL_CONTROL_WR_DQS_N :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_WR_DQS_N_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_WR_DQS_N_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_WR_DQS_N_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_1 :: VDL_CONTROL_WR_DQS_N :: reserved2 [11:09] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_WR_DQS_N_reserved2_MASK 0x00000e00
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_WR_DQS_N_reserved2_SHIFT 9
-
-/* DDR34_PHY_BYTE_LANE_2_1 :: VDL_CONTROL_WR_DQS_N :: VDL_STEP [08:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_WR_DQS_N_VDL_STEP_MASK 0x000001ff
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_WR_DQS_N_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_WR_DQS_N_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_WR_DQ0 - Write channel DQ0 VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_2_1 :: VDL_CONTROL_WR_DQ0 :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_WR_DQ0_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_WR_DQ0_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_WR_DQ0_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_1 :: VDL_CONTROL_WR_DQ0 :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_WR_DQ0_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_WR_DQ0_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_2_1 :: VDL_CONTROL_WR_DQ0 :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_WR_DQ0_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_WR_DQ0_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_WR_DQ0_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_1 :: VDL_CONTROL_WR_DQ0 :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_WR_DQ0_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_WR_DQ0_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_2_1 :: VDL_CONTROL_WR_DQ0 :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_WR_DQ0_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_WR_DQ0_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_WR_DQ0_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_1 :: VDL_CONTROL_WR_DQ0 :: reserved2 [11:09] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_WR_DQ0_reserved2_MASK 0x00000e00
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_WR_DQ0_reserved2_SHIFT 9
-
-/* DDR34_PHY_BYTE_LANE_2_1 :: VDL_CONTROL_WR_DQ0 :: VDL_STEP [08:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_WR_DQ0_VDL_STEP_MASK 0x000001ff
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_WR_DQ0_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_WR_DQ0_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_WR_DQ1 - Write channel DQ1 VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_2_1 :: VDL_CONTROL_WR_DQ1 :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_WR_DQ1_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_WR_DQ1_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_WR_DQ1_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_1 :: VDL_CONTROL_WR_DQ1 :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_WR_DQ1_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_WR_DQ1_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_2_1 :: VDL_CONTROL_WR_DQ1 :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_WR_DQ1_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_WR_DQ1_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_WR_DQ1_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_1 :: VDL_CONTROL_WR_DQ1 :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_WR_DQ1_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_WR_DQ1_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_2_1 :: VDL_CONTROL_WR_DQ1 :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_WR_DQ1_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_WR_DQ1_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_WR_DQ1_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_1 :: VDL_CONTROL_WR_DQ1 :: reserved2 [11:09] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_WR_DQ1_reserved2_MASK 0x00000e00
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_WR_DQ1_reserved2_SHIFT 9
-
-/* DDR34_PHY_BYTE_LANE_2_1 :: VDL_CONTROL_WR_DQ1 :: VDL_STEP [08:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_WR_DQ1_VDL_STEP_MASK 0x000001ff
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_WR_DQ1_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_WR_DQ1_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_WR_DQ2 - Write channel DQ2 VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_2_1 :: VDL_CONTROL_WR_DQ2 :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_WR_DQ2_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_WR_DQ2_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_WR_DQ2_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_1 :: VDL_CONTROL_WR_DQ2 :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_WR_DQ2_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_WR_DQ2_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_2_1 :: VDL_CONTROL_WR_DQ2 :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_WR_DQ2_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_WR_DQ2_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_WR_DQ2_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_1 :: VDL_CONTROL_WR_DQ2 :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_WR_DQ2_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_WR_DQ2_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_2_1 :: VDL_CONTROL_WR_DQ2 :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_WR_DQ2_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_WR_DQ2_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_WR_DQ2_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_1 :: VDL_CONTROL_WR_DQ2 :: reserved2 [11:09] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_WR_DQ2_reserved2_MASK 0x00000e00
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_WR_DQ2_reserved2_SHIFT 9
-
-/* DDR34_PHY_BYTE_LANE_2_1 :: VDL_CONTROL_WR_DQ2 :: VDL_STEP [08:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_WR_DQ2_VDL_STEP_MASK 0x000001ff
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_WR_DQ2_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_WR_DQ2_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_WR_DQ3 - Write channel DQ3 VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_2_1 :: VDL_CONTROL_WR_DQ3 :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_WR_DQ3_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_WR_DQ3_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_WR_DQ3_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_1 :: VDL_CONTROL_WR_DQ3 :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_WR_DQ3_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_WR_DQ3_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_2_1 :: VDL_CONTROL_WR_DQ3 :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_WR_DQ3_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_WR_DQ3_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_WR_DQ3_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_1 :: VDL_CONTROL_WR_DQ3 :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_WR_DQ3_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_WR_DQ3_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_2_1 :: VDL_CONTROL_WR_DQ3 :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_WR_DQ3_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_WR_DQ3_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_WR_DQ3_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_1 :: VDL_CONTROL_WR_DQ3 :: reserved2 [11:09] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_WR_DQ3_reserved2_MASK 0x00000e00
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_WR_DQ3_reserved2_SHIFT 9
-
-/* DDR34_PHY_BYTE_LANE_2_1 :: VDL_CONTROL_WR_DQ3 :: VDL_STEP [08:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_WR_DQ3_VDL_STEP_MASK 0x000001ff
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_WR_DQ3_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_WR_DQ3_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_WR_DQ4 - Write channel DQ4 VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_2_1 :: VDL_CONTROL_WR_DQ4 :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_WR_DQ4_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_WR_DQ4_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_WR_DQ4_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_1 :: VDL_CONTROL_WR_DQ4 :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_WR_DQ4_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_WR_DQ4_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_2_1 :: VDL_CONTROL_WR_DQ4 :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_WR_DQ4_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_WR_DQ4_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_WR_DQ4_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_1 :: VDL_CONTROL_WR_DQ4 :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_WR_DQ4_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_WR_DQ4_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_2_1 :: VDL_CONTROL_WR_DQ4 :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_WR_DQ4_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_WR_DQ4_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_WR_DQ4_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_1 :: VDL_CONTROL_WR_DQ4 :: reserved2 [11:09] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_WR_DQ4_reserved2_MASK 0x00000e00
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_WR_DQ4_reserved2_SHIFT 9
-
-/* DDR34_PHY_BYTE_LANE_2_1 :: VDL_CONTROL_WR_DQ4 :: VDL_STEP [08:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_WR_DQ4_VDL_STEP_MASK 0x000001ff
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_WR_DQ4_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_WR_DQ4_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_WR_DQ5 - Write channel DQ5 VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_2_1 :: VDL_CONTROL_WR_DQ5 :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_WR_DQ5_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_WR_DQ5_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_WR_DQ5_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_1 :: VDL_CONTROL_WR_DQ5 :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_WR_DQ5_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_WR_DQ5_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_2_1 :: VDL_CONTROL_WR_DQ5 :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_WR_DQ5_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_WR_DQ5_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_WR_DQ5_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_1 :: VDL_CONTROL_WR_DQ5 :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_WR_DQ5_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_WR_DQ5_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_2_1 :: VDL_CONTROL_WR_DQ5 :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_WR_DQ5_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_WR_DQ5_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_WR_DQ5_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_1 :: VDL_CONTROL_WR_DQ5 :: reserved2 [11:09] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_WR_DQ5_reserved2_MASK 0x00000e00
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_WR_DQ5_reserved2_SHIFT 9
-
-/* DDR34_PHY_BYTE_LANE_2_1 :: VDL_CONTROL_WR_DQ5 :: VDL_STEP [08:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_WR_DQ5_VDL_STEP_MASK 0x000001ff
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_WR_DQ5_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_WR_DQ5_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_WR_DQ6 - Write channel DQ6 VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_2_1 :: VDL_CONTROL_WR_DQ6 :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_WR_DQ6_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_WR_DQ6_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_WR_DQ6_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_1 :: VDL_CONTROL_WR_DQ6 :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_WR_DQ6_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_WR_DQ6_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_2_1 :: VDL_CONTROL_WR_DQ6 :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_WR_DQ6_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_WR_DQ6_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_WR_DQ6_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_1 :: VDL_CONTROL_WR_DQ6 :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_WR_DQ6_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_WR_DQ6_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_2_1 :: VDL_CONTROL_WR_DQ6 :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_WR_DQ6_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_WR_DQ6_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_WR_DQ6_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_1 :: VDL_CONTROL_WR_DQ6 :: reserved2 [11:09] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_WR_DQ6_reserved2_MASK 0x00000e00
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_WR_DQ6_reserved2_SHIFT 9
-
-/* DDR34_PHY_BYTE_LANE_2_1 :: VDL_CONTROL_WR_DQ6 :: VDL_STEP [08:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_WR_DQ6_VDL_STEP_MASK 0x000001ff
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_WR_DQ6_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_WR_DQ6_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_WR_DQ7 - Write channel DQ7 VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_2_1 :: VDL_CONTROL_WR_DQ7 :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_WR_DQ7_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_WR_DQ7_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_WR_DQ7_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_1 :: VDL_CONTROL_WR_DQ7 :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_WR_DQ7_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_WR_DQ7_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_2_1 :: VDL_CONTROL_WR_DQ7 :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_WR_DQ7_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_WR_DQ7_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_WR_DQ7_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_1 :: VDL_CONTROL_WR_DQ7 :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_WR_DQ7_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_WR_DQ7_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_2_1 :: VDL_CONTROL_WR_DQ7 :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_WR_DQ7_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_WR_DQ7_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_WR_DQ7_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_1 :: VDL_CONTROL_WR_DQ7 :: reserved2 [11:09] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_WR_DQ7_reserved2_MASK 0x00000e00
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_WR_DQ7_reserved2_SHIFT 9
-
-/* DDR34_PHY_BYTE_LANE_2_1 :: VDL_CONTROL_WR_DQ7 :: VDL_STEP [08:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_WR_DQ7_VDL_STEP_MASK 0x000001ff
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_WR_DQ7_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_WR_DQ7_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_WR_DM - Write channel DM VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_2_1 :: VDL_CONTROL_WR_DM :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_WR_DM_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_WR_DM_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_WR_DM_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_1 :: VDL_CONTROL_WR_DM :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_WR_DM_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_WR_DM_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_2_1 :: VDL_CONTROL_WR_DM :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_WR_DM_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_WR_DM_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_WR_DM_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_1 :: VDL_CONTROL_WR_DM :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_WR_DM_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_WR_DM_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_2_1 :: VDL_CONTROL_WR_DM :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_WR_DM_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_WR_DM_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_WR_DM_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_1 :: VDL_CONTROL_WR_DM :: reserved2 [11:09] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_WR_DM_reserved2_MASK 0x00000e00
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_WR_DM_reserved2_SHIFT 9
-
-/* DDR34_PHY_BYTE_LANE_2_1 :: VDL_CONTROL_WR_DM :: VDL_STEP [08:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_WR_DM_VDL_STEP_MASK 0x000001ff
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_WR_DM_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_WR_DM_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_WR_EDC - Write channel EDC VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_2_1 :: VDL_CONTROL_WR_EDC :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_WR_EDC_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_WR_EDC_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_WR_EDC_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_1 :: VDL_CONTROL_WR_EDC :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_WR_EDC_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_WR_EDC_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_2_1 :: VDL_CONTROL_WR_EDC :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_WR_EDC_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_WR_EDC_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_WR_EDC_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_1 :: VDL_CONTROL_WR_EDC :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_WR_EDC_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_WR_EDC_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_2_1 :: VDL_CONTROL_WR_EDC :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_WR_EDC_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_WR_EDC_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_WR_EDC_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_1 :: VDL_CONTROL_WR_EDC :: reserved2 [11:09] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_WR_EDC_reserved2_MASK 0x00000e00
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_WR_EDC_reserved2_SHIFT 9
-
-/* DDR34_PHY_BYTE_LANE_2_1 :: VDL_CONTROL_WR_EDC :: VDL_STEP [08:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_WR_EDC_VDL_STEP_MASK 0x000001ff
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_WR_EDC_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_WR_EDC_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_RD_DQSP - Read channel DQSP VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_2_1 :: VDL_CONTROL_RD_DQSP :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQSP_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQSP_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQSP_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_1 :: VDL_CONTROL_RD_DQSP :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQSP_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQSP_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_2_1 :: VDL_CONTROL_RD_DQSP :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQSP_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQSP_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQSP_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_1 :: VDL_CONTROL_RD_DQSP :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQSP_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQSP_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_2_1 :: VDL_CONTROL_RD_DQSP :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQSP_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQSP_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQSP_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_1 :: VDL_CONTROL_RD_DQSP :: reserved2 [11:08] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQSP_reserved2_MASK 0x00000f00
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQSP_reserved2_SHIFT 8
-
-/* DDR34_PHY_BYTE_LANE_2_1 :: VDL_CONTROL_RD_DQSP :: VDL_STEP [07:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQSP_VDL_STEP_MASK 0x000000ff
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQSP_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQSP_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_RD_DQSN - Read channel DQSP VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_2_1 :: VDL_CONTROL_RD_DQSN :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQSN_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQSN_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQSN_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_1 :: VDL_CONTROL_RD_DQSN :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQSN_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQSN_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_2_1 :: VDL_CONTROL_RD_DQSN :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQSN_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQSN_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQSN_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_1 :: VDL_CONTROL_RD_DQSN :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQSN_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQSN_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_2_1 :: VDL_CONTROL_RD_DQSN :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQSN_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQSN_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQSN_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_1 :: VDL_CONTROL_RD_DQSN :: reserved2 [11:08] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQSN_reserved2_MASK 0x00000f00
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQSN_reserved2_SHIFT 8
-
-/* DDR34_PHY_BYTE_LANE_2_1 :: VDL_CONTROL_RD_DQSN :: VDL_STEP [07:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQSN_VDL_STEP_MASK 0x000000ff
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQSN_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQSN_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_RD_DQ0P - Read channel DQ0-P VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_2_1 :: VDL_CONTROL_RD_DQ0P :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ0P_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ0P_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ0P_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_1 :: VDL_CONTROL_RD_DQ0P :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ0P_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ0P_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_2_1 :: VDL_CONTROL_RD_DQ0P :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ0P_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ0P_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ0P_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_1 :: VDL_CONTROL_RD_DQ0P :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ0P_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ0P_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_2_1 :: VDL_CONTROL_RD_DQ0P :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ0P_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ0P_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ0P_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_1 :: VDL_CONTROL_RD_DQ0P :: reserved2 [11:08] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ0P_reserved2_MASK 0x00000f00
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ0P_reserved2_SHIFT 8
-
-/* DDR34_PHY_BYTE_LANE_2_1 :: VDL_CONTROL_RD_DQ0P :: VDL_STEP [07:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ0P_VDL_STEP_MASK 0x000000ff
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ0P_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ0P_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_RD_DQ0N - Read channel DQ0-N VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_2_1 :: VDL_CONTROL_RD_DQ0N :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ0N_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ0N_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ0N_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_1 :: VDL_CONTROL_RD_DQ0N :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ0N_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ0N_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_2_1 :: VDL_CONTROL_RD_DQ0N :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ0N_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ0N_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ0N_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_1 :: VDL_CONTROL_RD_DQ0N :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ0N_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ0N_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_2_1 :: VDL_CONTROL_RD_DQ0N :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ0N_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ0N_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ0N_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_1 :: VDL_CONTROL_RD_DQ0N :: reserved2 [11:08] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ0N_reserved2_MASK 0x00000f00
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ0N_reserved2_SHIFT 8
-
-/* DDR34_PHY_BYTE_LANE_2_1 :: VDL_CONTROL_RD_DQ0N :: VDL_STEP [07:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ0N_VDL_STEP_MASK 0x000000ff
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ0N_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ0N_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_RD_DQ1P - Read channel DQ1-P VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_2_1 :: VDL_CONTROL_RD_DQ1P :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ1P_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ1P_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ1P_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_1 :: VDL_CONTROL_RD_DQ1P :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ1P_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ1P_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_2_1 :: VDL_CONTROL_RD_DQ1P :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ1P_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ1P_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ1P_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_1 :: VDL_CONTROL_RD_DQ1P :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ1P_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ1P_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_2_1 :: VDL_CONTROL_RD_DQ1P :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ1P_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ1P_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ1P_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_1 :: VDL_CONTROL_RD_DQ1P :: reserved2 [11:08] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ1P_reserved2_MASK 0x00000f00
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ1P_reserved2_SHIFT 8
-
-/* DDR34_PHY_BYTE_LANE_2_1 :: VDL_CONTROL_RD_DQ1P :: VDL_STEP [07:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ1P_VDL_STEP_MASK 0x000000ff
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ1P_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ1P_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_RD_DQ1N - Read channel DQ1-N VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_2_1 :: VDL_CONTROL_RD_DQ1N :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ1N_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ1N_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ1N_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_1 :: VDL_CONTROL_RD_DQ1N :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ1N_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ1N_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_2_1 :: VDL_CONTROL_RD_DQ1N :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ1N_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ1N_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ1N_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_1 :: VDL_CONTROL_RD_DQ1N :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ1N_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ1N_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_2_1 :: VDL_CONTROL_RD_DQ1N :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ1N_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ1N_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ1N_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_1 :: VDL_CONTROL_RD_DQ1N :: reserved2 [11:08] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ1N_reserved2_MASK 0x00000f00
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ1N_reserved2_SHIFT 8
-
-/* DDR34_PHY_BYTE_LANE_2_1 :: VDL_CONTROL_RD_DQ1N :: VDL_STEP [07:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ1N_VDL_STEP_MASK 0x000000ff
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ1N_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ1N_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_RD_DQ2P - Read channel DQ2-P VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_2_1 :: VDL_CONTROL_RD_DQ2P :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ2P_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ2P_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ2P_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_1 :: VDL_CONTROL_RD_DQ2P :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ2P_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ2P_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_2_1 :: VDL_CONTROL_RD_DQ2P :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ2P_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ2P_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ2P_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_1 :: VDL_CONTROL_RD_DQ2P :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ2P_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ2P_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_2_1 :: VDL_CONTROL_RD_DQ2P :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ2P_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ2P_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ2P_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_1 :: VDL_CONTROL_RD_DQ2P :: reserved2 [11:08] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ2P_reserved2_MASK 0x00000f00
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ2P_reserved2_SHIFT 8
-
-/* DDR34_PHY_BYTE_LANE_2_1 :: VDL_CONTROL_RD_DQ2P :: VDL_STEP [07:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ2P_VDL_STEP_MASK 0x000000ff
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ2P_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ2P_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_RD_DQ2N - Read channel DQ2-N VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_2_1 :: VDL_CONTROL_RD_DQ2N :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ2N_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ2N_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ2N_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_1 :: VDL_CONTROL_RD_DQ2N :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ2N_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ2N_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_2_1 :: VDL_CONTROL_RD_DQ2N :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ2N_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ2N_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ2N_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_1 :: VDL_CONTROL_RD_DQ2N :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ2N_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ2N_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_2_1 :: VDL_CONTROL_RD_DQ2N :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ2N_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ2N_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ2N_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_1 :: VDL_CONTROL_RD_DQ2N :: reserved2 [11:08] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ2N_reserved2_MASK 0x00000f00
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ2N_reserved2_SHIFT 8
-
-/* DDR34_PHY_BYTE_LANE_2_1 :: VDL_CONTROL_RD_DQ2N :: VDL_STEP [07:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ2N_VDL_STEP_MASK 0x000000ff
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ2N_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ2N_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_RD_DQ3P - Read channel DQ3-P VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_2_1 :: VDL_CONTROL_RD_DQ3P :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ3P_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ3P_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ3P_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_1 :: VDL_CONTROL_RD_DQ3P :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ3P_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ3P_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_2_1 :: VDL_CONTROL_RD_DQ3P :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ3P_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ3P_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ3P_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_1 :: VDL_CONTROL_RD_DQ3P :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ3P_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ3P_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_2_1 :: VDL_CONTROL_RD_DQ3P :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ3P_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ3P_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ3P_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_1 :: VDL_CONTROL_RD_DQ3P :: reserved2 [11:08] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ3P_reserved2_MASK 0x00000f00
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ3P_reserved2_SHIFT 8
-
-/* DDR34_PHY_BYTE_LANE_2_1 :: VDL_CONTROL_RD_DQ3P :: VDL_STEP [07:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ3P_VDL_STEP_MASK 0x000000ff
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ3P_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ3P_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_RD_DQ3N - Read channel DQ3-N VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_2_1 :: VDL_CONTROL_RD_DQ3N :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ3N_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ3N_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ3N_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_1 :: VDL_CONTROL_RD_DQ3N :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ3N_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ3N_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_2_1 :: VDL_CONTROL_RD_DQ3N :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ3N_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ3N_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ3N_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_1 :: VDL_CONTROL_RD_DQ3N :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ3N_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ3N_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_2_1 :: VDL_CONTROL_RD_DQ3N :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ3N_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ3N_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ3N_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_1 :: VDL_CONTROL_RD_DQ3N :: reserved2 [11:08] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ3N_reserved2_MASK 0x00000f00
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ3N_reserved2_SHIFT 8
-
-/* DDR34_PHY_BYTE_LANE_2_1 :: VDL_CONTROL_RD_DQ3N :: VDL_STEP [07:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ3N_VDL_STEP_MASK 0x000000ff
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ3N_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ3N_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_RD_DQ4P - Read channel DQ4-P VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_2_1 :: VDL_CONTROL_RD_DQ4P :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ4P_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ4P_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ4P_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_1 :: VDL_CONTROL_RD_DQ4P :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ4P_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ4P_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_2_1 :: VDL_CONTROL_RD_DQ4P :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ4P_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ4P_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ4P_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_1 :: VDL_CONTROL_RD_DQ4P :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ4P_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ4P_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_2_1 :: VDL_CONTROL_RD_DQ4P :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ4P_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ4P_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ4P_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_1 :: VDL_CONTROL_RD_DQ4P :: reserved2 [11:08] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ4P_reserved2_MASK 0x00000f00
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ4P_reserved2_SHIFT 8
-
-/* DDR34_PHY_BYTE_LANE_2_1 :: VDL_CONTROL_RD_DQ4P :: VDL_STEP [07:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ4P_VDL_STEP_MASK 0x000000ff
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ4P_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ4P_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_RD_DQ4N - Read channel DQ4-N VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_2_1 :: VDL_CONTROL_RD_DQ4N :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ4N_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ4N_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ4N_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_1 :: VDL_CONTROL_RD_DQ4N :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ4N_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ4N_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_2_1 :: VDL_CONTROL_RD_DQ4N :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ4N_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ4N_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ4N_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_1 :: VDL_CONTROL_RD_DQ4N :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ4N_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ4N_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_2_1 :: VDL_CONTROL_RD_DQ4N :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ4N_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ4N_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ4N_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_1 :: VDL_CONTROL_RD_DQ4N :: reserved2 [11:08] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ4N_reserved2_MASK 0x00000f00
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ4N_reserved2_SHIFT 8
-
-/* DDR34_PHY_BYTE_LANE_2_1 :: VDL_CONTROL_RD_DQ4N :: VDL_STEP [07:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ4N_VDL_STEP_MASK 0x000000ff
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ4N_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ4N_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_RD_DQ5P - Read channel DQ5-P VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_2_1 :: VDL_CONTROL_RD_DQ5P :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ5P_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ5P_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ5P_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_1 :: VDL_CONTROL_RD_DQ5P :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ5P_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ5P_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_2_1 :: VDL_CONTROL_RD_DQ5P :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ5P_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ5P_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ5P_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_1 :: VDL_CONTROL_RD_DQ5P :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ5P_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ5P_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_2_1 :: VDL_CONTROL_RD_DQ5P :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ5P_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ5P_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ5P_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_1 :: VDL_CONTROL_RD_DQ5P :: reserved2 [11:08] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ5P_reserved2_MASK 0x00000f00
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ5P_reserved2_SHIFT 8
-
-/* DDR34_PHY_BYTE_LANE_2_1 :: VDL_CONTROL_RD_DQ5P :: VDL_STEP [07:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ5P_VDL_STEP_MASK 0x000000ff
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ5P_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ5P_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_RD_DQ5N - Read channel DQ5-N VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_2_1 :: VDL_CONTROL_RD_DQ5N :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ5N_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ5N_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ5N_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_1 :: VDL_CONTROL_RD_DQ5N :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ5N_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ5N_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_2_1 :: VDL_CONTROL_RD_DQ5N :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ5N_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ5N_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ5N_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_1 :: VDL_CONTROL_RD_DQ5N :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ5N_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ5N_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_2_1 :: VDL_CONTROL_RD_DQ5N :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ5N_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ5N_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ5N_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_1 :: VDL_CONTROL_RD_DQ5N :: reserved2 [11:08] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ5N_reserved2_MASK 0x00000f00
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ5N_reserved2_SHIFT 8
-
-/* DDR34_PHY_BYTE_LANE_2_1 :: VDL_CONTROL_RD_DQ5N :: VDL_STEP [07:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ5N_VDL_STEP_MASK 0x000000ff
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ5N_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ5N_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_RD_DQ6P - Read channel DQ6-P VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_2_1 :: VDL_CONTROL_RD_DQ6P :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ6P_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ6P_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ6P_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_1 :: VDL_CONTROL_RD_DQ6P :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ6P_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ6P_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_2_1 :: VDL_CONTROL_RD_DQ6P :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ6P_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ6P_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ6P_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_1 :: VDL_CONTROL_RD_DQ6P :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ6P_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ6P_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_2_1 :: VDL_CONTROL_RD_DQ6P :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ6P_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ6P_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ6P_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_1 :: VDL_CONTROL_RD_DQ6P :: reserved2 [11:08] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ6P_reserved2_MASK 0x00000f00
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ6P_reserved2_SHIFT 8
-
-/* DDR34_PHY_BYTE_LANE_2_1 :: VDL_CONTROL_RD_DQ6P :: VDL_STEP [07:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ6P_VDL_STEP_MASK 0x000000ff
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ6P_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ6P_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_RD_DQ6N - Read channel DQ6-N VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_2_1 :: VDL_CONTROL_RD_DQ6N :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ6N_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ6N_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ6N_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_1 :: VDL_CONTROL_RD_DQ6N :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ6N_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ6N_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_2_1 :: VDL_CONTROL_RD_DQ6N :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ6N_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ6N_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ6N_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_1 :: VDL_CONTROL_RD_DQ6N :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ6N_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ6N_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_2_1 :: VDL_CONTROL_RD_DQ6N :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ6N_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ6N_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ6N_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_1 :: VDL_CONTROL_RD_DQ6N :: reserved2 [11:08] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ6N_reserved2_MASK 0x00000f00
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ6N_reserved2_SHIFT 8
-
-/* DDR34_PHY_BYTE_LANE_2_1 :: VDL_CONTROL_RD_DQ6N :: VDL_STEP [07:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ6N_VDL_STEP_MASK 0x000000ff
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ6N_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ6N_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_RD_DQ7P - Read channel DQ7-P VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_2_1 :: VDL_CONTROL_RD_DQ7P :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ7P_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ7P_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ7P_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_1 :: VDL_CONTROL_RD_DQ7P :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ7P_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ7P_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_2_1 :: VDL_CONTROL_RD_DQ7P :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ7P_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ7P_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ7P_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_1 :: VDL_CONTROL_RD_DQ7P :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ7P_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ7P_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_2_1 :: VDL_CONTROL_RD_DQ7P :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ7P_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ7P_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ7P_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_1 :: VDL_CONTROL_RD_DQ7P :: reserved2 [11:08] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ7P_reserved2_MASK 0x00000f00
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ7P_reserved2_SHIFT 8
-
-/* DDR34_PHY_BYTE_LANE_2_1 :: VDL_CONTROL_RD_DQ7P :: VDL_STEP [07:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ7P_VDL_STEP_MASK 0x000000ff
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ7P_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ7P_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_RD_DQ7N - Read channel DQ7-N VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_2_1 :: VDL_CONTROL_RD_DQ7N :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ7N_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ7N_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ7N_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_1 :: VDL_CONTROL_RD_DQ7N :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ7N_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ7N_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_2_1 :: VDL_CONTROL_RD_DQ7N :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ7N_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ7N_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ7N_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_1 :: VDL_CONTROL_RD_DQ7N :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ7N_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ7N_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_2_1 :: VDL_CONTROL_RD_DQ7N :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ7N_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ7N_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ7N_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_1 :: VDL_CONTROL_RD_DQ7N :: reserved2 [11:08] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ7N_reserved2_MASK 0x00000f00
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ7N_reserved2_SHIFT 8
-
-/* DDR34_PHY_BYTE_LANE_2_1 :: VDL_CONTROL_RD_DQ7N :: VDL_STEP [07:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ7N_VDL_STEP_MASK 0x000000ff
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ7N_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ7N_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_RD_DMP - Read channel DM-P VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_2_1 :: VDL_CONTROL_RD_DMP :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DMP_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DMP_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DMP_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_1 :: VDL_CONTROL_RD_DMP :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DMP_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DMP_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_2_1 :: VDL_CONTROL_RD_DMP :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DMP_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DMP_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DMP_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_1 :: VDL_CONTROL_RD_DMP :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DMP_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DMP_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_2_1 :: VDL_CONTROL_RD_DMP :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DMP_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DMP_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DMP_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_1 :: VDL_CONTROL_RD_DMP :: reserved2 [11:08] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DMP_reserved2_MASK 0x00000f00
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DMP_reserved2_SHIFT 8
-
-/* DDR34_PHY_BYTE_LANE_2_1 :: VDL_CONTROL_RD_DMP :: VDL_STEP [07:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DMP_VDL_STEP_MASK 0x000000ff
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DMP_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DMP_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_RD_DMN - Read channel DM-N VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_2_1 :: VDL_CONTROL_RD_DMN :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DMN_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DMN_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DMN_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_1 :: VDL_CONTROL_RD_DMN :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DMN_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DMN_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_2_1 :: VDL_CONTROL_RD_DMN :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DMN_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DMN_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DMN_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_1 :: VDL_CONTROL_RD_DMN :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DMN_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DMN_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_2_1 :: VDL_CONTROL_RD_DMN :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DMN_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DMN_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DMN_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_1 :: VDL_CONTROL_RD_DMN :: reserved2 [11:08] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DMN_reserved2_MASK 0x00000f00
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DMN_reserved2_SHIFT 8
-
-/* DDR34_PHY_BYTE_LANE_2_1 :: VDL_CONTROL_RD_DMN :: VDL_STEP [07:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DMN_VDL_STEP_MASK 0x000000ff
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DMN_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DMN_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_RD_EDCP - Read channel EDC-P VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_2_1 :: VDL_CONTROL_RD_EDCP :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_EDCP_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_EDCP_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_EDCP_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_1 :: VDL_CONTROL_RD_EDCP :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_EDCP_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_EDCP_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_2_1 :: VDL_CONTROL_RD_EDCP :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_EDCP_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_EDCP_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_EDCP_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_1 :: VDL_CONTROL_RD_EDCP :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_EDCP_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_EDCP_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_2_1 :: VDL_CONTROL_RD_EDCP :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_EDCP_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_EDCP_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_EDCP_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_1 :: VDL_CONTROL_RD_EDCP :: reserved2 [11:08] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_EDCP_reserved2_MASK 0x00000f00
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_EDCP_reserved2_SHIFT 8
-
-/* DDR34_PHY_BYTE_LANE_2_1 :: VDL_CONTROL_RD_EDCP :: VDL_STEP [07:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_EDCP_VDL_STEP_MASK 0x000000ff
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_EDCP_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_EDCP_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_RD_EDCN - Read channel EDC-N VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_2_1 :: VDL_CONTROL_RD_EDCN :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_EDCN_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_EDCN_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_EDCN_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_1 :: VDL_CONTROL_RD_EDCN :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_EDCN_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_EDCN_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_2_1 :: VDL_CONTROL_RD_EDCN :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_EDCN_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_EDCN_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_EDCN_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_1 :: VDL_CONTROL_RD_EDCN :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_EDCN_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_EDCN_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_2_1 :: VDL_CONTROL_RD_EDCN :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_EDCN_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_EDCN_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_EDCN_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_1 :: VDL_CONTROL_RD_EDCN :: reserved2 [11:08] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_EDCN_reserved2_MASK 0x00000f00
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_EDCN_reserved2_SHIFT 8
-
-/* DDR34_PHY_BYTE_LANE_2_1 :: VDL_CONTROL_RD_EDCN :: VDL_STEP [07:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_EDCN_VDL_STEP_MASK 0x000000ff
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_EDCN_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_EDCN_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_RD_EN_CS0 - Read channel CS_N[0] read enable VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_2_1 :: VDL_CONTROL_RD_EN_CS0 :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_EN_CS0_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_EN_CS0_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_EN_CS0_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_1 :: VDL_CONTROL_RD_EN_CS0 :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_EN_CS0_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_EN_CS0_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_2_1 :: VDL_CONTROL_RD_EN_CS0 :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_EN_CS0_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_EN_CS0_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_EN_CS0_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_1 :: VDL_CONTROL_RD_EN_CS0 :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_EN_CS0_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_EN_CS0_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_2_1 :: VDL_CONTROL_RD_EN_CS0 :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_EN_CS0_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_EN_CS0_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_EN_CS0_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_1 :: VDL_CONTROL_RD_EN_CS0 :: reserved2 [11:08] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_EN_CS0_reserved2_MASK 0x00000f00
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_EN_CS0_reserved2_SHIFT 8
-
-/* DDR34_PHY_BYTE_LANE_2_1 :: VDL_CONTROL_RD_EN_CS0 :: VDL_STEP [07:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_EN_CS0_VDL_STEP_MASK 0x000000ff
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_EN_CS0_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_EN_CS0_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_RD_EN_CS1 - Read channel CS_N[1] read enable VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_2_1 :: VDL_CONTROL_RD_EN_CS1 :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_EN_CS1_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_EN_CS1_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_EN_CS1_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_1 :: VDL_CONTROL_RD_EN_CS1 :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_EN_CS1_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_EN_CS1_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_2_1 :: VDL_CONTROL_RD_EN_CS1 :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_EN_CS1_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_EN_CS1_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_EN_CS1_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_1 :: VDL_CONTROL_RD_EN_CS1 :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_EN_CS1_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_EN_CS1_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_2_1 :: VDL_CONTROL_RD_EN_CS1 :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_EN_CS1_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_EN_CS1_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_EN_CS1_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_1 :: VDL_CONTROL_RD_EN_CS1 :: reserved2 [11:08] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_EN_CS1_reserved2_MASK 0x00000f00
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_EN_CS1_reserved2_SHIFT 8
-
-/* DDR34_PHY_BYTE_LANE_2_1 :: VDL_CONTROL_RD_EN_CS1 :: VDL_STEP [07:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_EN_CS1_VDL_STEP_MASK 0x000000ff
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_EN_CS1_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_EN_CS1_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CLK_CONTROL - DDR interface signal Write Leveling CLK VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_2_1 :: VDL_CLK_CONTROL :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CLK_CONTROL_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CLK_CONTROL_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CLK_CONTROL_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_1 :: VDL_CLK_CONTROL :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CLK_CONTROL_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CLK_CONTROL_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_2_1 :: VDL_CLK_CONTROL :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CLK_CONTROL_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CLK_CONTROL_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CLK_CONTROL_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_1 :: VDL_CLK_CONTROL :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CLK_CONTROL_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CLK_CONTROL_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_2_1 :: VDL_CLK_CONTROL :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CLK_CONTROL_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CLK_CONTROL_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CLK_CONTROL_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_1 :: VDL_CLK_CONTROL :: reserved2 [11:09] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CLK_CONTROL_reserved2_MASK 0x00000e00
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CLK_CONTROL_reserved2_SHIFT 9
-
-/* DDR34_PHY_BYTE_LANE_2_1 :: VDL_CLK_CONTROL :: VDL_STEP [08:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CLK_CONTROL_VDL_STEP_MASK 0x000001ff
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CLK_CONTROL_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CLK_CONTROL_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_LDE_CONTROL - DDR interface signal Write Leveling Capture Enable VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_2_1 :: VDL_LDE_CONTROL :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_LDE_CONTROL_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_LDE_CONTROL_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_LDE_CONTROL_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_1 :: VDL_LDE_CONTROL :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_LDE_CONTROL_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_LDE_CONTROL_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_2_1 :: VDL_LDE_CONTROL :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_LDE_CONTROL_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_LDE_CONTROL_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_LDE_CONTROL_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_1 :: VDL_LDE_CONTROL :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_LDE_CONTROL_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_LDE_CONTROL_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_2_1 :: VDL_LDE_CONTROL :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_LDE_CONTROL_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_LDE_CONTROL_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_LDE_CONTROL_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_1 :: VDL_LDE_CONTROL :: reserved2 [11:09] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_LDE_CONTROL_reserved2_MASK 0x00000e00
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_LDE_CONTROL_reserved2_SHIFT 9
-
-/* DDR34_PHY_BYTE_LANE_2_1 :: VDL_LDE_CONTROL :: VDL_STEP [08:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_LDE_CONTROL_VDL_STEP_MASK 0x000001ff
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_LDE_CONTROL_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_LDE_CONTROL_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *RD_EN_DLY_CYC - Read enable bit-clock cycle delay control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_2_1 :: RD_EN_DLY_CYC :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_RD_EN_DLY_CYC_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_RD_EN_DLY_CYC_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_RD_EN_DLY_CYC_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_1 :: RD_EN_DLY_CYC :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_RD_EN_DLY_CYC_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_RD_EN_DLY_CYC_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_2_1 :: RD_EN_DLY_CYC :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_RD_EN_DLY_CYC_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_RD_EN_DLY_CYC_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_RD_EN_DLY_CYC_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_1 :: RD_EN_DLY_CYC :: reserved1 [15:08] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_RD_EN_DLY_CYC_reserved1_MASK 0x0000ff00
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_RD_EN_DLY_CYC_reserved1_SHIFT 8
-
-/* DDR34_PHY_BYTE_LANE_2_1 :: RD_EN_DLY_CYC :: CS1_CYCLES [07:04] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_RD_EN_DLY_CYC_CS1_CYCLES_MASK 0x000000f0
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_RD_EN_DLY_CYC_CS1_CYCLES_SHIFT 4
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_RD_EN_DLY_CYC_CS1_CYCLES_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_1 :: RD_EN_DLY_CYC :: CS0_CYCLES [03:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_RD_EN_DLY_CYC_CS0_CYCLES_MASK 0x0000000f
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_RD_EN_DLY_CYC_CS0_CYCLES_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_RD_EN_DLY_CYC_CS0_CYCLES_DEFAULT 0x00000000
-
-/***************************************************************************
- *WR_CHAN_DLY_CYC - Write leveling bit-clock cycle delay control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_2_1 :: WR_CHAN_DLY_CYC :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_WR_CHAN_DLY_CYC_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_WR_CHAN_DLY_CYC_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_WR_CHAN_DLY_CYC_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_1 :: WR_CHAN_DLY_CYC :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_WR_CHAN_DLY_CYC_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_WR_CHAN_DLY_CYC_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_2_1 :: WR_CHAN_DLY_CYC :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_WR_CHAN_DLY_CYC_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_WR_CHAN_DLY_CYC_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_WR_CHAN_DLY_CYC_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_1 :: WR_CHAN_DLY_CYC :: reserved1 [15:03] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_WR_CHAN_DLY_CYC_reserved1_MASK 0x0000fff8
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_WR_CHAN_DLY_CYC_reserved1_SHIFT 3
-
-/* DDR34_PHY_BYTE_LANE_2_1 :: WR_CHAN_DLY_CYC :: CYCLES [02:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_WR_CHAN_DLY_CYC_CYCLES_MASK 0x00000007
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_WR_CHAN_DLY_CYC_CYCLES_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_WR_CHAN_DLY_CYC_CYCLES_DEFAULT 0x00000000
-
-/***************************************************************************
- *READ_CONTROL - Read channel datapath control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_2_1 :: READ_CONTROL :: reserved0 [31:05] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_READ_CONTROL_reserved0_MASK 0xffffffe0
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_READ_CONTROL_reserved0_SHIFT 5
-
-/* DDR34_PHY_BYTE_LANE_2_1 :: READ_CONTROL :: MODE [04:04] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_READ_CONTROL_MODE_MASK 0x00000010
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_READ_CONTROL_MODE_SHIFT 4
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_READ_CONTROL_MODE_DEFAULT 0x00000001
-
-/* DDR34_PHY_BYTE_LANE_2_1 :: READ_CONTROL :: reserved1 [03:03] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_READ_CONTROL_reserved1_MASK 0x00000008
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_READ_CONTROL_reserved1_SHIFT 3
-
-/* DDR34_PHY_BYTE_LANE_2_1 :: READ_CONTROL :: RD_DATA_DLY [02:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_READ_CONTROL_RD_DATA_DLY_MASK 0x00000007
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_READ_CONTROL_RD_DATA_DLY_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_READ_CONTROL_RD_DATA_DLY_DEFAULT 0x00000007
-
-/***************************************************************************
- *READ_FIFO_ADDR - Read fifo addresss pointer register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_2_1 :: READ_FIFO_ADDR :: reserved0 [31:03] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_READ_FIFO_ADDR_reserved0_MASK 0xfffffff8
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_READ_FIFO_ADDR_reserved0_SHIFT 3
-
-/* DDR34_PHY_BYTE_LANE_2_1 :: READ_FIFO_ADDR :: ADDR [02:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_READ_FIFO_ADDR_ADDR_MASK 0x00000007
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_READ_FIFO_ADDR_ADDR_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_READ_FIFO_ADDR_ADDR_DEFAULT 0x00000000
-
-/***************************************************************************
- *READ_FIFO_DATA - Read fifo data register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_2_1 :: READ_FIFO_DATA :: DATA [31:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_READ_FIFO_DATA_DATA_MASK 0xffffffff
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_READ_FIFO_DATA_DATA_SHIFT 0
-
-/***************************************************************************
- *READ_FIFO_DM_DBI - Read fifo dm/dbi register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_2_1 :: READ_FIFO_DM_DBI :: reserved0 [31:04] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_READ_FIFO_DM_DBI_reserved0_MASK 0xfffffff0
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_READ_FIFO_DM_DBI_reserved0_SHIFT 4
-
-/* DDR34_PHY_BYTE_LANE_2_1 :: READ_FIFO_DM_DBI :: DM_DBI [03:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_READ_FIFO_DM_DBI_DM_DBI_MASK 0x0000000f
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_READ_FIFO_DM_DBI_DM_DBI_SHIFT 0
-
-/***************************************************************************
- *READ_FIFO_STATUS - Read fifo status register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_2_1 :: READ_FIFO_STATUS :: reserved0 [31:02] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_READ_FIFO_STATUS_reserved0_MASK 0xfffffffc
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_READ_FIFO_STATUS_reserved0_SHIFT 2
-
-/* DDR34_PHY_BYTE_LANE_2_1 :: READ_FIFO_STATUS :: OVERFLOW [01:01] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_READ_FIFO_STATUS_OVERFLOW_MASK 0x00000002
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_READ_FIFO_STATUS_OVERFLOW_SHIFT 1
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_READ_FIFO_STATUS_OVERFLOW_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_1 :: READ_FIFO_STATUS :: UNDERFLOW [00:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_READ_FIFO_STATUS_UNDERFLOW_MASK 0x00000001
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_READ_FIFO_STATUS_UNDERFLOW_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_READ_FIFO_STATUS_UNDERFLOW_DEFAULT 0x00000000
-
-/***************************************************************************
- *READ_FIFO_CLEAR - Read fifo status clear register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_2_1 :: READ_FIFO_CLEAR :: reserved0 [31:01] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_READ_FIFO_CLEAR_reserved0_MASK 0xfffffffe
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_READ_FIFO_CLEAR_reserved0_SHIFT 1
-
-/* DDR34_PHY_BYTE_LANE_2_1 :: READ_FIFO_CLEAR :: CLEAR [00:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_READ_FIFO_CLEAR_CLEAR_MASK 0x00000001
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_READ_FIFO_CLEAR_CLEAR_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_READ_FIFO_CLEAR_CLEAR_DEFAULT 0x00000000
-
-/***************************************************************************
- *IDLE_PAD_CONTROL - Idle mode SSTL pad control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_2_1 :: IDLE_PAD_CONTROL :: IDLE [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_IDLE_PAD_CONTROL_IDLE_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_IDLE_PAD_CONTROL_IDLE_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_IDLE_PAD_CONTROL_IDLE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_1 :: IDLE_PAD_CONTROL :: reserved0 [30:20] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_IDLE_PAD_CONTROL_reserved0_MASK 0x7ff00000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_IDLE_PAD_CONTROL_reserved0_SHIFT 20
-
-/* DDR34_PHY_BYTE_LANE_2_1 :: IDLE_PAD_CONTROL :: AUTO_DQ_RXENB_MODE [19:18] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_IDLE_PAD_CONTROL_AUTO_DQ_RXENB_MODE_MASK 0x000c0000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_IDLE_PAD_CONTROL_AUTO_DQ_RXENB_MODE_SHIFT 18
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_IDLE_PAD_CONTROL_AUTO_DQ_RXENB_MODE_DEFAULT 0x00000001
-
-/* DDR34_PHY_BYTE_LANE_2_1 :: IDLE_PAD_CONTROL :: AUTO_DQ_IDDQ_MODE [17:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_IDLE_PAD_CONTROL_AUTO_DQ_IDDQ_MODE_MASK 0x00030000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_IDLE_PAD_CONTROL_AUTO_DQ_IDDQ_MODE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_IDLE_PAD_CONTROL_AUTO_DQ_IDDQ_MODE_DEFAULT 0x00000001
-
-/* DDR34_PHY_BYTE_LANE_2_1 :: IDLE_PAD_CONTROL :: reserved_for_padding1 [15:15] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_IDLE_PAD_CONTROL_reserved_for_padding1_MASK 0x00008000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_IDLE_PAD_CONTROL_reserved_for_padding1_SHIFT 15
-
-/* DDR34_PHY_BYTE_LANE_2_1 :: IDLE_PAD_CONTROL :: IO_IDLE_ENABLE [14:04] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_IDLE_PAD_CONTROL_IO_IDLE_ENABLE_MASK 0x00007ff0
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_IDLE_PAD_CONTROL_IO_IDLE_ENABLE_SHIFT 4
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_IDLE_PAD_CONTROL_IO_IDLE_ENABLE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_1 :: IDLE_PAD_CONTROL :: RXENB [03:03] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_IDLE_PAD_CONTROL_RXENB_MASK 0x00000008
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_IDLE_PAD_CONTROL_RXENB_SHIFT 3
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_IDLE_PAD_CONTROL_RXENB_DEFAULT 0x00000001
-
-/* DDR34_PHY_BYTE_LANE_2_1 :: IDLE_PAD_CONTROL :: IDDQ [02:02] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_IDLE_PAD_CONTROL_IDDQ_MASK 0x00000004
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_IDLE_PAD_CONTROL_IDDQ_SHIFT 2
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_IDLE_PAD_CONTROL_IDDQ_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_1 :: IDLE_PAD_CONTROL :: DOUT_N [01:01] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_IDLE_PAD_CONTROL_DOUT_N_MASK 0x00000002
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_IDLE_PAD_CONTROL_DOUT_N_SHIFT 1
-
-/* DDR34_PHY_BYTE_LANE_2_1 :: IDLE_PAD_CONTROL :: DOUT_P [00:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_IDLE_PAD_CONTROL_DOUT_P_MASK 0x00000001
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_IDLE_PAD_CONTROL_DOUT_P_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_IDLE_PAD_CONTROL_DOUT_P_DEFAULT 0x00000000
-
-/***************************************************************************
- *DRIVE_PAD_CTL - SSTL pad drive characteristics control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_2_1 :: DRIVE_PAD_CTL :: reserved0 [31:30] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_DRIVE_PAD_CTL_reserved0_MASK 0xc0000000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_DRIVE_PAD_CTL_reserved0_SHIFT 30
-
-/* DDR34_PHY_BYTE_LANE_2_1 :: DRIVE_PAD_CTL :: BL_PD_IDLE_STRENGTH [29:25] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_DRIVE_PAD_CTL_BL_PD_IDLE_STRENGTH_MASK 0x3e000000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_DRIVE_PAD_CTL_BL_PD_IDLE_STRENGTH_SHIFT 25
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_DRIVE_PAD_CTL_BL_PD_IDLE_STRENGTH_DEFAULT 0x0000001f
-
-/* DDR34_PHY_BYTE_LANE_2_1 :: DRIVE_PAD_CTL :: BL_ND_IDLE_STRENGTH [24:20] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_DRIVE_PAD_CTL_BL_ND_IDLE_STRENGTH_MASK 0x01f00000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_DRIVE_PAD_CTL_BL_ND_IDLE_STRENGTH_SHIFT 20
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_DRIVE_PAD_CTL_BL_ND_IDLE_STRENGTH_DEFAULT 0x0000001f
-
-/* DDR34_PHY_BYTE_LANE_2_1 :: DRIVE_PAD_CTL :: BL_PD_TERM_STRENGTH [19:15] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_DRIVE_PAD_CTL_BL_PD_TERM_STRENGTH_MASK 0x000f8000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_DRIVE_PAD_CTL_BL_PD_TERM_STRENGTH_SHIFT 15
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_DRIVE_PAD_CTL_BL_PD_TERM_STRENGTH_DEFAULT 0x00000008
-
-/* DDR34_PHY_BYTE_LANE_2_1 :: DRIVE_PAD_CTL :: BL_ND_TERM_STRENGTH [14:10] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_DRIVE_PAD_CTL_BL_ND_TERM_STRENGTH_MASK 0x00007c00
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_DRIVE_PAD_CTL_BL_ND_TERM_STRENGTH_SHIFT 10
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_DRIVE_PAD_CTL_BL_ND_TERM_STRENGTH_DEFAULT 0x00000008
-
-/* DDR34_PHY_BYTE_LANE_2_1 :: DRIVE_PAD_CTL :: BL_PD_STRENGTH [09:05] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_DRIVE_PAD_CTL_BL_PD_STRENGTH_MASK 0x000003e0
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_DRIVE_PAD_CTL_BL_PD_STRENGTH_SHIFT 5
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_DRIVE_PAD_CTL_BL_PD_STRENGTH_DEFAULT 0x0000001f
-
-/* DDR34_PHY_BYTE_LANE_2_1 :: DRIVE_PAD_CTL :: BL_ND_STRENGTH [04:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_DRIVE_PAD_CTL_BL_ND_STRENGTH_MASK 0x0000001f
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_DRIVE_PAD_CTL_BL_ND_STRENGTH_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_DRIVE_PAD_CTL_BL_ND_STRENGTH_DEFAULT 0x0000001f
-
-/***************************************************************************
- *RD_EN_DRIVE_PAD_CTL - SSTL read enable pad drive characteristics control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_2_1 :: RD_EN_DRIVE_PAD_CTL :: reserved0 [31:20] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_RD_EN_DRIVE_PAD_CTL_reserved0_MASK 0xfff00000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_RD_EN_DRIVE_PAD_CTL_reserved0_SHIFT 20
-
-/* DDR34_PHY_BYTE_LANE_2_1 :: RD_EN_DRIVE_PAD_CTL :: EDC_RD_EN_PD_STRENGTH [19:15] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_RD_EN_DRIVE_PAD_CTL_EDC_RD_EN_PD_STRENGTH_MASK 0x000f8000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_RD_EN_DRIVE_PAD_CTL_EDC_RD_EN_PD_STRENGTH_SHIFT 15
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_RD_EN_DRIVE_PAD_CTL_EDC_RD_EN_PD_STRENGTH_DEFAULT 0x0000001f
-
-/* DDR34_PHY_BYTE_LANE_2_1 :: RD_EN_DRIVE_PAD_CTL :: EDC_RD_EN_ND_STRENGTH [14:10] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_RD_EN_DRIVE_PAD_CTL_EDC_RD_EN_ND_STRENGTH_MASK 0x00007c00
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_RD_EN_DRIVE_PAD_CTL_EDC_RD_EN_ND_STRENGTH_SHIFT 10
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_RD_EN_DRIVE_PAD_CTL_EDC_RD_EN_ND_STRENGTH_DEFAULT 0x0000001f
-
-/* DDR34_PHY_BYTE_LANE_2_1 :: RD_EN_DRIVE_PAD_CTL :: BL_RD_EN_PD_STRENGTH [09:05] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_RD_EN_DRIVE_PAD_CTL_BL_RD_EN_PD_STRENGTH_MASK 0x000003e0
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_RD_EN_DRIVE_PAD_CTL_BL_RD_EN_PD_STRENGTH_SHIFT 5
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_RD_EN_DRIVE_PAD_CTL_BL_RD_EN_PD_STRENGTH_DEFAULT 0x0000001f
-
-/* DDR34_PHY_BYTE_LANE_2_1 :: RD_EN_DRIVE_PAD_CTL :: BL_RD_EN_ND_STRENGTH [04:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_RD_EN_DRIVE_PAD_CTL_BL_RD_EN_ND_STRENGTH_MASK 0x0000001f
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_RD_EN_DRIVE_PAD_CTL_BL_RD_EN_ND_STRENGTH_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_RD_EN_DRIVE_PAD_CTL_BL_RD_EN_ND_STRENGTH_DEFAULT 0x0000001f
-
-/***************************************************************************
- *STATIC_PAD_CTL - pad rx and tx characteristics control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_2_1 :: STATIC_PAD_CTL :: reserved0 [31:21] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_STATIC_PAD_CTL_reserved0_MASK 0xffe00000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_STATIC_PAD_CTL_reserved0_SHIFT 21
-
-/* DDR34_PHY_BYTE_LANE_2_1 :: STATIC_PAD_CTL :: DQS_MODE [20:20] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_STATIC_PAD_CTL_DQS_MODE_MASK 0x00100000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_STATIC_PAD_CTL_DQS_MODE_SHIFT 20
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_STATIC_PAD_CTL_DQS_MODE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_1 :: STATIC_PAD_CTL :: reserved1 [19:18] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_STATIC_PAD_CTL_reserved1_MASK 0x000c0000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_STATIC_PAD_CTL_reserved1_SHIFT 18
-
-/* DDR34_PHY_BYTE_LANE_2_1 :: STATIC_PAD_CTL :: EDC_MODE [17:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_STATIC_PAD_CTL_EDC_MODE_MASK 0x00030000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_STATIC_PAD_CTL_EDC_MODE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_STATIC_PAD_CTL_EDC_MODE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_1 :: STATIC_PAD_CTL :: reserved2 [15:15] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_STATIC_PAD_CTL_reserved2_MASK 0x00008000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_STATIC_PAD_CTL_reserved2_SHIFT 15
-
-/* DDR34_PHY_BYTE_LANE_2_1 :: STATIC_PAD_CTL :: WDBI_ENABLE [14:14] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_STATIC_PAD_CTL_WDBI_ENABLE_MASK 0x00004000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_STATIC_PAD_CTL_WDBI_ENABLE_SHIFT 14
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_STATIC_PAD_CTL_WDBI_ENABLE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_1 :: STATIC_PAD_CTL :: RDBI_ENABLE [13:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_STATIC_PAD_CTL_RDBI_ENABLE_MASK 0x00002000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_STATIC_PAD_CTL_RDBI_ENABLE_SHIFT 13
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_STATIC_PAD_CTL_RDBI_ENABLE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_1 :: STATIC_PAD_CTL :: DM_MODE [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_STATIC_PAD_CTL_DM_MODE_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_STATIC_PAD_CTL_DM_MODE_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_STATIC_PAD_CTL_DM_MODE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_1 :: STATIC_PAD_CTL :: reserved3 [11:11] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_STATIC_PAD_CTL_reserved3_MASK 0x00000800
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_STATIC_PAD_CTL_reserved3_SHIFT 11
-
-/* DDR34_PHY_BYTE_LANE_2_1 :: STATIC_PAD_CTL :: DQS_TX_PAUSE [10:10] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_STATIC_PAD_CTL_DQS_TX_PAUSE_MASK 0x00000400
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_STATIC_PAD_CTL_DQS_TX_PAUSE_SHIFT 10
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_STATIC_PAD_CTL_DQS_TX_PAUSE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_1 :: STATIC_PAD_CTL :: DQS_TX_DIS [09:09] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_STATIC_PAD_CTL_DQS_TX_DIS_MASK 0x00000200
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_STATIC_PAD_CTL_DQS_TX_DIS_SHIFT 9
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_STATIC_PAD_CTL_DQS_TX_DIS_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_1 :: STATIC_PAD_CTL :: reserved4 [08:08] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_STATIC_PAD_CTL_reserved4_MASK 0x00000100
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_STATIC_PAD_CTL_reserved4_SHIFT 8
-
-/* DDR34_PHY_BYTE_LANE_2_1 :: STATIC_PAD_CTL :: TX_MODE [07:04] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_STATIC_PAD_CTL_TX_MODE_MASK 0x000000f0
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_STATIC_PAD_CTL_TX_MODE_SHIFT 4
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_STATIC_PAD_CTL_TX_MODE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_1 :: STATIC_PAD_CTL :: reserved5 [03:03] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_STATIC_PAD_CTL_reserved5_MASK 0x00000008
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_STATIC_PAD_CTL_reserved5_SHIFT 3
-
-/* DDR34_PHY_BYTE_LANE_2_1 :: STATIC_PAD_CTL :: RX_MODE [02:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_STATIC_PAD_CTL_RX_MODE_MASK 0x00000007
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_STATIC_PAD_CTL_RX_MODE_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_STATIC_PAD_CTL_RX_MODE_DEFAULT 0x00000000
-
-/***************************************************************************
- *WR_PREAMBLE_MODE - Write cycle preamble control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_2_1 :: WR_PREAMBLE_MODE :: reserved0 [31:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_WR_PREAMBLE_MODE_reserved0_MASK 0xffff0000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_WR_PREAMBLE_MODE_reserved0_SHIFT 16
-
-/* DDR34_PHY_BYTE_LANE_2_1 :: WR_PREAMBLE_MODE :: DQ_POSTAM_BITS [15:14] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_WR_PREAMBLE_MODE_DQ_POSTAM_BITS_MASK 0x0000c000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_WR_PREAMBLE_MODE_DQ_POSTAM_BITS_SHIFT 14
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_WR_PREAMBLE_MODE_DQ_POSTAM_BITS_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_1 :: WR_PREAMBLE_MODE :: DQ_PREAM_BITS [13:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_WR_PREAMBLE_MODE_DQ_PREAM_BITS_MASK 0x00003000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_WR_PREAMBLE_MODE_DQ_PREAM_BITS_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_WR_PREAMBLE_MODE_DQ_PREAM_BITS_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_1 :: WR_PREAMBLE_MODE :: DQS [11:08] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_WR_PREAMBLE_MODE_DQS_MASK 0x00000f00
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_WR_PREAMBLE_MODE_DQS_SHIFT 8
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_WR_PREAMBLE_MODE_DQS_DEFAULT 0x0000000e
-
-/* DDR34_PHY_BYTE_LANE_2_1 :: WR_PREAMBLE_MODE :: reserved1 [07:05] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_WR_PREAMBLE_MODE_reserved1_MASK 0x000000e0
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_WR_PREAMBLE_MODE_reserved1_SHIFT 5
-
-/* DDR34_PHY_BYTE_LANE_2_1 :: WR_PREAMBLE_MODE :: DQS_POSTAM_BITS [04:03] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_WR_PREAMBLE_MODE_DQS_POSTAM_BITS_MASK 0x00000018
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_WR_PREAMBLE_MODE_DQS_POSTAM_BITS_SHIFT 3
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_WR_PREAMBLE_MODE_DQS_POSTAM_BITS_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_1 :: WR_PREAMBLE_MODE :: DQS_PREAM_BITS [02:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_WR_PREAMBLE_MODE_DQS_PREAM_BITS_MASK 0x00000007
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_WR_PREAMBLE_MODE_DQS_PREAM_BITS_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_WR_PREAMBLE_MODE_DQS_PREAM_BITS_DEFAULT 0x00000002
-
-/***************************************************************************
- *ODT_CONTROL - Read channel ODT control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_2_1 :: ODT_CONTROL :: reserved_for_padding0 [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_ODT_CONTROL_reserved_for_padding0_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_ODT_CONTROL_reserved_for_padding0_SHIFT 31
-
-/* DDR34_PHY_BYTE_LANE_2_1 :: ODT_CONTROL :: reserved1 [30:10] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_ODT_CONTROL_reserved1_MASK 0x7ffffc00
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_ODT_CONTROL_reserved1_SHIFT 10
-
-/* DDR34_PHY_BYTE_LANE_2_1 :: ODT_CONTROL :: ODT_ENABLE [09:09] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_ODT_CONTROL_ODT_ENABLE_MASK 0x00000200
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_ODT_CONTROL_ODT_ENABLE_SHIFT 9
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_ODT_CONTROL_ODT_ENABLE_DEFAULT 0x00000001
-
-/* DDR34_PHY_BYTE_LANE_2_1 :: ODT_CONTROL :: ODT_DELAY [08:06] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_ODT_CONTROL_ODT_DELAY_MASK 0x000001c0
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_ODT_CONTROL_ODT_DELAY_SHIFT 6
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_ODT_CONTROL_ODT_DELAY_DEFAULT 0x00000001
-
-/* DDR34_PHY_BYTE_LANE_2_1 :: ODT_CONTROL :: ODT_POST_LENGTH [05:03] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_ODT_CONTROL_ODT_POST_LENGTH_MASK 0x00000038
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_ODT_CONTROL_ODT_POST_LENGTH_SHIFT 3
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_ODT_CONTROL_ODT_POST_LENGTH_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_1 :: ODT_CONTROL :: ODT_PRE_LENGTH [02:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_ODT_CONTROL_ODT_PRE_LENGTH_MASK 0x00000007
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_ODT_CONTROL_ODT_PRE_LENGTH_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_ODT_CONTROL_ODT_PRE_LENGTH_DEFAULT 0x00000003
-
-/***************************************************************************
- *EDC_DPD_CONTROL - GDDR5M EDC digital phase detector control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_2_1 :: EDC_DPD_CONTROL :: reserved0 [31:06] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_EDC_DPD_CONTROL_reserved0_MASK 0xffffffc0
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_EDC_DPD_CONTROL_reserved0_SHIFT 6
-
-/* DDR34_PHY_BYTE_LANE_2_1 :: EDC_DPD_CONTROL :: DQS_PHASE_OVERRIDE_VALUE [05:05] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_EDC_DPD_CONTROL_DQS_PHASE_OVERRIDE_VALUE_MASK 0x00000020
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_EDC_DPD_CONTROL_DQS_PHASE_OVERRIDE_VALUE_SHIFT 5
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_EDC_DPD_CONTROL_DQS_PHASE_OVERRIDE_VALUE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_1 :: EDC_DPD_CONTROL :: DQS_PHASE_OVERRIDE_ENABLE [04:04] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_EDC_DPD_CONTROL_DQS_PHASE_OVERRIDE_ENABLE_MASK 0x00000010
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_EDC_DPD_CONTROL_DQS_PHASE_OVERRIDE_ENABLE_SHIFT 4
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_EDC_DPD_CONTROL_DQS_PHASE_OVERRIDE_ENABLE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_1 :: EDC_DPD_CONTROL :: SET_ADJ_EN [03:03] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_EDC_DPD_CONTROL_SET_ADJ_EN_MASK 0x00000008
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_EDC_DPD_CONTROL_SET_ADJ_EN_SHIFT 3
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_EDC_DPD_CONTROL_SET_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_1 :: EDC_DPD_CONTROL :: UPDATE [02:02] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_EDC_DPD_CONTROL_UPDATE_MASK 0x00000004
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_EDC_DPD_CONTROL_UPDATE_SHIFT 2
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_EDC_DPD_CONTROL_UPDATE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_1 :: EDC_DPD_CONTROL :: MONITOR [01:01] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_EDC_DPD_CONTROL_MONITOR_MASK 0x00000002
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_EDC_DPD_CONTROL_MONITOR_SHIFT 1
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_EDC_DPD_CONTROL_MONITOR_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_1 :: EDC_DPD_CONTROL :: INIT [00:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_EDC_DPD_CONTROL_INIT_MASK 0x00000001
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_EDC_DPD_CONTROL_INIT_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_EDC_DPD_CONTROL_INIT_DEFAULT 0x00000000
-
-/***************************************************************************
- *EDC_DPD_STATUS - GDDR5M EDC digital phase detector status register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_2_1 :: EDC_DPD_STATUS :: reserved0 [31:25] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_EDC_DPD_STATUS_reserved0_MASK 0xfe000000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_EDC_DPD_STATUS_reserved0_SHIFT 25
-
-/* DDR34_PHY_BYTE_LANE_2_1 :: EDC_DPD_STATUS :: CURRENT_DQS_PHASE [24:24] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_EDC_DPD_STATUS_CURRENT_DQS_PHASE_MASK 0x01000000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_EDC_DPD_STATUS_CURRENT_DQS_PHASE_SHIFT 24
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_EDC_DPD_STATUS_CURRENT_DQS_PHASE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_1 :: EDC_DPD_STATUS :: CURRENT_VDL_SETTING [23:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_EDC_DPD_STATUS_CURRENT_VDL_SETTING_MASK 0x00ff0000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_EDC_DPD_STATUS_CURRENT_VDL_SETTING_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_EDC_DPD_STATUS_CURRENT_VDL_SETTING_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_1 :: EDC_DPD_STATUS :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_EDC_DPD_STATUS_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_EDC_DPD_STATUS_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_2_1 :: EDC_DPD_STATUS :: INIT_DQS_PHASE [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_EDC_DPD_STATUS_INIT_DQS_PHASE_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_EDC_DPD_STATUS_INIT_DQS_PHASE_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_EDC_DPD_STATUS_INIT_DQS_PHASE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_1 :: EDC_DPD_STATUS :: INIT_VDL_SETTING [11:04] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_EDC_DPD_STATUS_INIT_VDL_SETTING_MASK 0x00000ff0
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_EDC_DPD_STATUS_INIT_VDL_SETTING_SHIFT 4
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_EDC_DPD_STATUS_INIT_VDL_SETTING_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_1 :: EDC_DPD_STATUS :: EDGE_ERROR [03:03] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_EDC_DPD_STATUS_EDGE_ERROR_MASK 0x00000008
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_EDC_DPD_STATUS_EDGE_ERROR_SHIFT 3
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_EDC_DPD_STATUS_EDGE_ERROR_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_1 :: EDC_DPD_STATUS :: MONITOR_BUSY [02:02] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_EDC_DPD_STATUS_MONITOR_BUSY_MASK 0x00000004
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_EDC_DPD_STATUS_MONITOR_BUSY_SHIFT 2
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_EDC_DPD_STATUS_MONITOR_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_1 :: EDC_DPD_STATUS :: INIT_BUSY [01:01] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_EDC_DPD_STATUS_INIT_BUSY_MASK 0x00000002
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_EDC_DPD_STATUS_INIT_BUSY_SHIFT 1
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_EDC_DPD_STATUS_INIT_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_1 :: EDC_DPD_STATUS :: INIT_DONE [00:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_EDC_DPD_STATUS_INIT_DONE_MASK 0x00000001
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_EDC_DPD_STATUS_INIT_DONE_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_EDC_DPD_STATUS_INIT_DONE_DEFAULT 0x00000000
-
-/***************************************************************************
- *EDC_DPD_OUT_CONTROL - GDDR5M EDC digital phase detector output signal control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_2_1 :: EDC_DPD_OUT_CONTROL :: reserved0 [31:20] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_EDC_DPD_OUT_CONTROL_reserved0_MASK 0xfff00000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_EDC_DPD_OUT_CONTROL_reserved0_SHIFT 20
-
-/* DDR34_PHY_BYTE_LANE_2_1 :: EDC_DPD_OUT_CONTROL :: LOWER_LIMIT [19:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_EDC_DPD_OUT_CONTROL_LOWER_LIMIT_MASK 0x000ff000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_EDC_DPD_OUT_CONTROL_LOWER_LIMIT_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_EDC_DPD_OUT_CONTROL_LOWER_LIMIT_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_1 :: EDC_DPD_OUT_CONTROL :: UPPER_LIMIT [11:04] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_EDC_DPD_OUT_CONTROL_UPPER_LIMIT_MASK 0x00000ff0
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_EDC_DPD_OUT_CONTROL_UPPER_LIMIT_SHIFT 4
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_EDC_DPD_OUT_CONTROL_UPPER_LIMIT_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_1 :: EDC_DPD_OUT_CONTROL :: reserved1 [03:01] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_EDC_DPD_OUT_CONTROL_reserved1_MASK 0x0000000e
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_EDC_DPD_OUT_CONTROL_reserved1_SHIFT 1
-
-/* DDR34_PHY_BYTE_LANE_2_1 :: EDC_DPD_OUT_CONTROL :: ENABLE [00:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_EDC_DPD_OUT_CONTROL_ENABLE_MASK 0x00000001
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_EDC_DPD_OUT_CONTROL_ENABLE_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_EDC_DPD_OUT_CONTROL_ENABLE_DEFAULT 0x00000000
-
-/***************************************************************************
- *EDC_DPD_OUT_STATUS - GDDR5M EDC digital phase detector output signal status register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_2_1 :: EDC_DPD_OUT_STATUS :: reserved0 [31:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_EDC_DPD_OUT_STATUS_reserved0_MASK 0xfffff000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_EDC_DPD_OUT_STATUS_reserved0_SHIFT 12
-
-/* DDR34_PHY_BYTE_LANE_2_1 :: EDC_DPD_OUT_STATUS :: VDL_SETTING [11:04] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_EDC_DPD_OUT_STATUS_VDL_SETTING_MASK 0x00000ff0
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_EDC_DPD_OUT_STATUS_VDL_SETTING_SHIFT 4
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_EDC_DPD_OUT_STATUS_VDL_SETTING_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_1 :: EDC_DPD_OUT_STATUS :: reserved1 [03:01] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_EDC_DPD_OUT_STATUS_reserved1_MASK 0x0000000e
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_EDC_DPD_OUT_STATUS_reserved1_SHIFT 1
-
-/* DDR34_PHY_BYTE_LANE_2_1 :: EDC_DPD_OUT_STATUS :: VALID [00:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_EDC_DPD_OUT_STATUS_VALID_MASK 0x00000001
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_EDC_DPD_OUT_STATUS_VALID_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_EDC_DPD_OUT_STATUS_VALID_DEFAULT 0x00000000
-
-/***************************************************************************
- *EDC_DPD_OUT_STATUS_CLEAR - GDDR5M EDC digital phase detector output signal status clear register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_2_1 :: EDC_DPD_OUT_STATUS_CLEAR :: reserved0 [31:01] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_EDC_DPD_OUT_STATUS_CLEAR_reserved0_MASK 0xfffffffe
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_EDC_DPD_OUT_STATUS_CLEAR_reserved0_SHIFT 1
-
-/* DDR34_PHY_BYTE_LANE_2_1 :: EDC_DPD_OUT_STATUS_CLEAR :: CLEAR [00:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_EDC_DPD_OUT_STATUS_CLEAR_CLEAR_MASK 0x00000001
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_EDC_DPD_OUT_STATUS_CLEAR_CLEAR_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_EDC_DPD_OUT_STATUS_CLEAR_CLEAR_DEFAULT 0x00000000
-
-/***************************************************************************
- *EDC_CRC_CONTROL - GDDR5M EDC signal path CRC control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_2_1 :: EDC_CRC_CONTROL :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_EDC_CRC_CONTROL_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_EDC_CRC_CONTROL_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_EDC_CRC_CONTROL_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_1 :: EDC_CRC_CONTROL :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_EDC_CRC_CONTROL_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_EDC_CRC_CONTROL_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_2_1 :: EDC_CRC_CONTROL :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_EDC_CRC_CONTROL_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_EDC_CRC_CONTROL_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_EDC_CRC_CONTROL_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_1 :: EDC_CRC_CONTROL :: reserved1 [15:11] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_EDC_CRC_CONTROL_reserved1_MASK 0x0000f800
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_EDC_CRC_CONTROL_reserved1_SHIFT 11
-
-/* DDR34_PHY_BYTE_LANE_2_1 :: EDC_CRC_CONTROL :: CRCWL [10:08] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_EDC_CRC_CONTROL_CRCWL_MASK 0x00000700
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_EDC_CRC_CONTROL_CRCWL_SHIFT 8
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_EDC_CRC_CONTROL_CRCWL_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_1 :: EDC_CRC_CONTROL :: reserved2 [07:06] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_EDC_CRC_CONTROL_reserved2_MASK 0x000000c0
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_EDC_CRC_CONTROL_reserved2_SHIFT 6
-
-/* DDR34_PHY_BYTE_LANE_2_1 :: EDC_CRC_CONTROL :: CRCRL [05:04] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_EDC_CRC_CONTROL_CRCRL_MASK 0x00000030
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_EDC_CRC_CONTROL_CRCRL_SHIFT 4
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_EDC_CRC_CONTROL_CRCRL_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_1 :: EDC_CRC_CONTROL :: reserved3 [03:03] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_EDC_CRC_CONTROL_reserved3_MASK 0x00000008
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_EDC_CRC_CONTROL_reserved3_SHIFT 3
-
-/* DDR34_PHY_BYTE_LANE_2_1 :: EDC_CRC_CONTROL :: COUNT_MODE [02:02] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_EDC_CRC_CONTROL_COUNT_MODE_MASK 0x00000004
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_EDC_CRC_CONTROL_COUNT_MODE_SHIFT 2
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_EDC_CRC_CONTROL_COUNT_MODE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_1 :: EDC_CRC_CONTROL :: ENABLE_WR [01:01] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_EDC_CRC_CONTROL_ENABLE_WR_MASK 0x00000002
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_EDC_CRC_CONTROL_ENABLE_WR_SHIFT 1
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_EDC_CRC_CONTROL_ENABLE_WR_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_1 :: EDC_CRC_CONTROL :: ENABLE_RD [00:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_EDC_CRC_CONTROL_ENABLE_RD_MASK 0x00000001
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_EDC_CRC_CONTROL_ENABLE_RD_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_EDC_CRC_CONTROL_ENABLE_RD_DEFAULT 0x00000000
-
-/***************************************************************************
- *EDC_CRC_STATUS - GDDR5M EDC signal path CRC status register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_2_1 :: EDC_CRC_STATUS :: reserved0 [31:04] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_EDC_CRC_STATUS_reserved0_MASK 0xfffffff0
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_EDC_CRC_STATUS_reserved0_SHIFT 4
-
-/* DDR34_PHY_BYTE_LANE_2_1 :: EDC_CRC_STATUS :: WR_FAIL [03:03] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_EDC_CRC_STATUS_WR_FAIL_MASK 0x00000008
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_EDC_CRC_STATUS_WR_FAIL_SHIFT 3
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_EDC_CRC_STATUS_WR_FAIL_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_1 :: EDC_CRC_STATUS :: WR_PASS [02:02] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_EDC_CRC_STATUS_WR_PASS_MASK 0x00000004
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_EDC_CRC_STATUS_WR_PASS_SHIFT 2
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_EDC_CRC_STATUS_WR_PASS_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_1 :: EDC_CRC_STATUS :: RD_FAIL [01:01] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_EDC_CRC_STATUS_RD_FAIL_MASK 0x00000002
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_EDC_CRC_STATUS_RD_FAIL_SHIFT 1
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_EDC_CRC_STATUS_RD_FAIL_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_1 :: EDC_CRC_STATUS :: RD_PASS [00:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_EDC_CRC_STATUS_RD_PASS_MASK 0x00000001
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_EDC_CRC_STATUS_RD_PASS_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_EDC_CRC_STATUS_RD_PASS_DEFAULT 0x00000000
-
-/***************************************************************************
- *EDC_CRC_COUNT - GDDR5M EDC signal path CRC counter register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_2_1 :: EDC_CRC_COUNT :: reserved0 [31:28] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_EDC_CRC_COUNT_reserved0_MASK 0xf0000000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_EDC_CRC_COUNT_reserved0_SHIFT 28
-
-/* DDR34_PHY_BYTE_LANE_2_1 :: EDC_CRC_COUNT :: WR_COUNT [27:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_EDC_CRC_COUNT_WR_COUNT_MASK 0x0fff0000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_EDC_CRC_COUNT_WR_COUNT_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_EDC_CRC_COUNT_WR_COUNT_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_1 :: EDC_CRC_COUNT :: reserved1 [15:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_EDC_CRC_COUNT_reserved1_MASK 0x0000f000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_EDC_CRC_COUNT_reserved1_SHIFT 12
-
-/* DDR34_PHY_BYTE_LANE_2_1 :: EDC_CRC_COUNT :: RD_COUNT [11:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_EDC_CRC_COUNT_RD_COUNT_MASK 0x00000fff
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_EDC_CRC_COUNT_RD_COUNT_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_EDC_CRC_COUNT_RD_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *EDC_CRC_STATUS_CLEAR - GDDR5M EDC signal path CRC counter register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_2_1 :: EDC_CRC_STATUS_CLEAR :: reserved0 [31:01] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_EDC_CRC_STATUS_CLEAR_reserved0_MASK 0xfffffffe
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_EDC_CRC_STATUS_CLEAR_reserved0_SHIFT 1
-
-/* DDR34_PHY_BYTE_LANE_2_1 :: EDC_CRC_STATUS_CLEAR :: CLEAR [00:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_EDC_CRC_STATUS_CLEAR_CLEAR_MASK 0x00000001
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_EDC_CRC_STATUS_CLEAR_CLEAR_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_EDC_CRC_STATUS_CLEAR_CLEAR_DEFAULT 0x00000000
-
-/***************************************************************************
- *BL_SPARE_REG - Byte-Lane Spare register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_2_1 :: BL_SPARE_REG :: reserved_for_eco0 [31:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_BL_SPARE_REG_reserved_for_eco0_MASK 0xffffffff
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_BL_SPARE_REG_reserved_for_eco0_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_BL_SPARE_REG_reserved_for_eco0_DEFAULT 0x00000000
-
-#endif /* #ifndef BCHP_DDR34_PHY_BYTE_LANE_2_1_H__ */
-
-/* End of File */
diff --git a/include/linux/brcmstb/7145a0/bchp_ddr34_phy_byte_lane_3_0.h b/include/linux/brcmstb/7145a0/bchp_ddr34_phy_byte_lane_3_0.h
deleted file mode 100644
index fc54114..0000000
--- a/include/linux/brcmstb/7145a0/bchp_ddr34_phy_byte_lane_3_0.h
+++ /dev/null
@@ -1,2101 +0,0 @@
-/***************************************************************************
- * Copyright (c) 1999-2014, Broadcom Corporation
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
- *
- * Module Description:
- * DO NOT EDIT THIS FILE DIRECTLY
- *
- * This module was generated magically with RDB from a source description
- * file. You must edit the source file for changes to be made to this file.
- *
- *
- * Date: Generated on Wed Sep 3 13:17:34 2014
- * Full Compile MD5 Checksum a8ee62ccf9dde43435c825f266da463d
- * (minus title and desc)
- * MD5 Checksum e373b364a1742e13a0f9eb15fd8aa94f
- *
- * Compiled with: RDB Utility combo_header.pl
- * RDB Parser 3.0
- * unknown unknown
- * Perl Interpreter 5.008005
- * Operating System linux
- *
- * Revision History:
- *
- * $brcm_Log: $
- *
- ***************************************************************************/
-
-#ifndef BCHP_DDR34_PHY_BYTE_LANE_3_0_H__
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_H__
-
-/***************************************************************************
- *DDR34_PHY_BYTE_LANE_3_0 - DDR34 Byte Lane #3 control registers
- ***************************************************************************/
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQS_P 0x203b6a00 /* Write channel DQS-P VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQS_N 0x203b6a04 /* Write channel DQS-N VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ0 0x203b6a08 /* Write channel DQ0 VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ1 0x203b6a0c /* Write channel DQ1 VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ2 0x203b6a10 /* Write channel DQ2 VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ3 0x203b6a14 /* Write channel DQ3 VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ4 0x203b6a18 /* Write channel DQ4 VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ5 0x203b6a1c /* Write channel DQ5 VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ6 0x203b6a20 /* Write channel DQ6 VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ7 0x203b6a24 /* Write channel DQ7 VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DM 0x203b6a28 /* Write channel DM VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_EDC 0x203b6a2c /* Write channel EDC VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQSP 0x203b6a30 /* Read channel DQSP VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQSN 0x203b6a34 /* Read channel DQSP VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ0P 0x203b6a38 /* Read channel DQ0-P VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ0N 0x203b6a3c /* Read channel DQ0-N VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ1P 0x203b6a40 /* Read channel DQ1-P VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ1N 0x203b6a44 /* Read channel DQ1-N VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ2P 0x203b6a48 /* Read channel DQ2-P VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ2N 0x203b6a4c /* Read channel DQ2-N VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ3P 0x203b6a50 /* Read channel DQ3-P VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ3N 0x203b6a54 /* Read channel DQ3-N VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ4P 0x203b6a58 /* Read channel DQ4-P VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ4N 0x203b6a5c /* Read channel DQ4-N VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ5P 0x203b6a60 /* Read channel DQ5-P VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ5N 0x203b6a64 /* Read channel DQ5-N VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ6P 0x203b6a68 /* Read channel DQ6-P VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ6N 0x203b6a6c /* Read channel DQ6-N VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ7P 0x203b6a70 /* Read channel DQ7-P VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ7N 0x203b6a74 /* Read channel DQ7-N VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DMP 0x203b6a78 /* Read channel DM-P VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DMN 0x203b6a7c /* Read channel DM-N VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_EDCP 0x203b6a80 /* Read channel EDC-P VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_EDCN 0x203b6a84 /* Read channel EDC-N VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_EN_CS0 0x203b6a88 /* Read channel CS_N[0] read enable VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_EN_CS1 0x203b6a8c /* Read channel CS_N[1] read enable VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CLK_CONTROL 0x203b6a90 /* DDR interface signal Write Leveling CLK VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_LDE_CONTROL 0x203b6a94 /* DDR interface signal Write Leveling Capture Enable VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_RD_EN_DLY_CYC 0x203b6aa0 /* Read enable bit-clock cycle delay control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_WR_CHAN_DLY_CYC 0x203b6aa4 /* Write leveling bit-clock cycle delay control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_READ_CONTROL 0x203b6ab0 /* Read channel datapath control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_READ_FIFO_ADDR 0x203b6ab4 /* Read fifo addresss pointer register */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_READ_FIFO_DATA 0x203b6ab8 /* Read fifo data register */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_READ_FIFO_DM_DBI 0x203b6abc /* Read fifo dm/dbi register */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_READ_FIFO_STATUS 0x203b6ac0 /* Read fifo status register */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_READ_FIFO_CLEAR 0x203b6ac4 /* Read fifo status clear register */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_IDLE_PAD_CONTROL 0x203b6ac8 /* Idle mode SSTL pad control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_DRIVE_PAD_CTL 0x203b6acc /* SSTL pad drive characteristics control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_RD_EN_DRIVE_PAD_CTL 0x203b6ad0 /* SSTL read enable pad drive characteristics control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_STATIC_PAD_CTL 0x203b6ad4 /* pad rx and tx characteristics control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_WR_PREAMBLE_MODE 0x203b6ad8 /* Write cycle preamble control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_ODT_CONTROL 0x203b6ae0 /* Read channel ODT control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_DPD_CONTROL 0x203b6af0 /* GDDR5M EDC digital phase detector control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_DPD_STATUS 0x203b6af4 /* GDDR5M EDC digital phase detector status register */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_DPD_OUT_CONTROL 0x203b6af8 /* GDDR5M EDC digital phase detector output signal control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_DPD_OUT_STATUS 0x203b6afc /* GDDR5M EDC digital phase detector output signal status register */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_DPD_OUT_STATUS_CLEAR 0x203b6b00 /* GDDR5M EDC digital phase detector output signal status clear register */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_CRC_CONTROL 0x203b6b04 /* GDDR5M EDC signal path CRC control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_CRC_STATUS 0x203b6b08 /* GDDR5M EDC signal path CRC status register */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_CRC_COUNT 0x203b6b0c /* GDDR5M EDC signal path CRC counter register */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_CRC_STATUS_CLEAR 0x203b6b10 /* GDDR5M EDC signal path CRC counter register */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_BL_SPARE_REG 0x203b6b14 /* Byte-Lane Spare register */
-
-/***************************************************************************
- *VDL_CONTROL_WR_DQS_P - Write channel DQS-P VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_WR_DQS_P :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQS_P_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQS_P_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQS_P_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_WR_DQS_P :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQS_P_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQS_P_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_WR_DQS_P :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQS_P_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQS_P_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQS_P_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_WR_DQS_P :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQS_P_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQS_P_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_WR_DQS_P :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQS_P_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQS_P_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQS_P_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_WR_DQS_P :: reserved2 [11:09] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQS_P_reserved2_MASK 0x00000e00
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQS_P_reserved2_SHIFT 9
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_WR_DQS_P :: VDL_STEP [08:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQS_P_VDL_STEP_MASK 0x000001ff
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQS_P_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQS_P_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_WR_DQS_N - Write channel DQS-N VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_WR_DQS_N :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQS_N_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQS_N_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQS_N_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_WR_DQS_N :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQS_N_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQS_N_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_WR_DQS_N :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQS_N_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQS_N_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQS_N_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_WR_DQS_N :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQS_N_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQS_N_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_WR_DQS_N :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQS_N_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQS_N_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQS_N_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_WR_DQS_N :: reserved2 [11:09] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQS_N_reserved2_MASK 0x00000e00
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQS_N_reserved2_SHIFT 9
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_WR_DQS_N :: VDL_STEP [08:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQS_N_VDL_STEP_MASK 0x000001ff
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQS_N_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQS_N_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_WR_DQ0 - Write channel DQ0 VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_WR_DQ0 :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ0_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ0_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ0_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_WR_DQ0 :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ0_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ0_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_WR_DQ0 :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ0_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ0_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ0_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_WR_DQ0 :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ0_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ0_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_WR_DQ0 :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ0_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ0_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ0_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_WR_DQ0 :: reserved2 [11:09] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ0_reserved2_MASK 0x00000e00
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ0_reserved2_SHIFT 9
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_WR_DQ0 :: VDL_STEP [08:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ0_VDL_STEP_MASK 0x000001ff
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ0_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ0_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_WR_DQ1 - Write channel DQ1 VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_WR_DQ1 :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ1_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ1_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ1_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_WR_DQ1 :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ1_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ1_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_WR_DQ1 :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ1_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ1_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ1_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_WR_DQ1 :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ1_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ1_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_WR_DQ1 :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ1_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ1_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ1_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_WR_DQ1 :: reserved2 [11:09] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ1_reserved2_MASK 0x00000e00
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ1_reserved2_SHIFT 9
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_WR_DQ1 :: VDL_STEP [08:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ1_VDL_STEP_MASK 0x000001ff
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ1_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ1_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_WR_DQ2 - Write channel DQ2 VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_WR_DQ2 :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ2_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ2_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ2_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_WR_DQ2 :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ2_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ2_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_WR_DQ2 :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ2_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ2_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ2_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_WR_DQ2 :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ2_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ2_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_WR_DQ2 :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ2_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ2_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ2_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_WR_DQ2 :: reserved2 [11:09] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ2_reserved2_MASK 0x00000e00
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ2_reserved2_SHIFT 9
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_WR_DQ2 :: VDL_STEP [08:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ2_VDL_STEP_MASK 0x000001ff
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ2_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ2_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_WR_DQ3 - Write channel DQ3 VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_WR_DQ3 :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ3_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ3_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ3_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_WR_DQ3 :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ3_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ3_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_WR_DQ3 :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ3_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ3_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ3_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_WR_DQ3 :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ3_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ3_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_WR_DQ3 :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ3_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ3_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ3_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_WR_DQ3 :: reserved2 [11:09] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ3_reserved2_MASK 0x00000e00
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ3_reserved2_SHIFT 9
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_WR_DQ3 :: VDL_STEP [08:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ3_VDL_STEP_MASK 0x000001ff
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ3_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ3_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_WR_DQ4 - Write channel DQ4 VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_WR_DQ4 :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ4_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ4_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ4_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_WR_DQ4 :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ4_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ4_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_WR_DQ4 :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ4_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ4_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ4_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_WR_DQ4 :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ4_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ4_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_WR_DQ4 :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ4_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ4_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ4_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_WR_DQ4 :: reserved2 [11:09] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ4_reserved2_MASK 0x00000e00
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ4_reserved2_SHIFT 9
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_WR_DQ4 :: VDL_STEP [08:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ4_VDL_STEP_MASK 0x000001ff
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ4_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ4_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_WR_DQ5 - Write channel DQ5 VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_WR_DQ5 :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ5_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ5_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ5_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_WR_DQ5 :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ5_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ5_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_WR_DQ5 :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ5_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ5_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ5_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_WR_DQ5 :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ5_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ5_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_WR_DQ5 :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ5_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ5_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ5_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_WR_DQ5 :: reserved2 [11:09] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ5_reserved2_MASK 0x00000e00
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ5_reserved2_SHIFT 9
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_WR_DQ5 :: VDL_STEP [08:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ5_VDL_STEP_MASK 0x000001ff
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ5_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ5_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_WR_DQ6 - Write channel DQ6 VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_WR_DQ6 :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ6_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ6_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ6_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_WR_DQ6 :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ6_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ6_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_WR_DQ6 :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ6_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ6_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ6_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_WR_DQ6 :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ6_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ6_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_WR_DQ6 :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ6_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ6_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ6_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_WR_DQ6 :: reserved2 [11:09] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ6_reserved2_MASK 0x00000e00
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ6_reserved2_SHIFT 9
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_WR_DQ6 :: VDL_STEP [08:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ6_VDL_STEP_MASK 0x000001ff
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ6_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ6_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_WR_DQ7 - Write channel DQ7 VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_WR_DQ7 :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ7_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ7_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ7_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_WR_DQ7 :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ7_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ7_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_WR_DQ7 :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ7_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ7_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ7_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_WR_DQ7 :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ7_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ7_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_WR_DQ7 :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ7_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ7_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ7_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_WR_DQ7 :: reserved2 [11:09] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ7_reserved2_MASK 0x00000e00
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ7_reserved2_SHIFT 9
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_WR_DQ7 :: VDL_STEP [08:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ7_VDL_STEP_MASK 0x000001ff
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ7_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ7_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_WR_DM - Write channel DM VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_WR_DM :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DM_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DM_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DM_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_WR_DM :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DM_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DM_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_WR_DM :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DM_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DM_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DM_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_WR_DM :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DM_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DM_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_WR_DM :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DM_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DM_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DM_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_WR_DM :: reserved2 [11:09] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DM_reserved2_MASK 0x00000e00
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DM_reserved2_SHIFT 9
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_WR_DM :: VDL_STEP [08:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DM_VDL_STEP_MASK 0x000001ff
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DM_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DM_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_WR_EDC - Write channel EDC VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_WR_EDC :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_EDC_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_EDC_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_EDC_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_WR_EDC :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_EDC_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_EDC_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_WR_EDC :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_EDC_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_EDC_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_EDC_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_WR_EDC :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_EDC_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_EDC_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_WR_EDC :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_EDC_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_EDC_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_EDC_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_WR_EDC :: reserved2 [11:09] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_EDC_reserved2_MASK 0x00000e00
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_EDC_reserved2_SHIFT 9
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_WR_EDC :: VDL_STEP [08:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_EDC_VDL_STEP_MASK 0x000001ff
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_EDC_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_EDC_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_RD_DQSP - Read channel DQSP VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_DQSP :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQSP_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQSP_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQSP_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_DQSP :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQSP_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQSP_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_DQSP :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQSP_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQSP_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQSP_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_DQSP :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQSP_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQSP_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_DQSP :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQSP_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQSP_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQSP_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_DQSP :: reserved2 [11:08] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQSP_reserved2_MASK 0x00000f00
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQSP_reserved2_SHIFT 8
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_DQSP :: VDL_STEP [07:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQSP_VDL_STEP_MASK 0x000000ff
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQSP_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQSP_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_RD_DQSN - Read channel DQSP VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_DQSN :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQSN_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQSN_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQSN_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_DQSN :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQSN_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQSN_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_DQSN :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQSN_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQSN_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQSN_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_DQSN :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQSN_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQSN_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_DQSN :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQSN_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQSN_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQSN_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_DQSN :: reserved2 [11:08] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQSN_reserved2_MASK 0x00000f00
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQSN_reserved2_SHIFT 8
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_DQSN :: VDL_STEP [07:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQSN_VDL_STEP_MASK 0x000000ff
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQSN_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQSN_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_RD_DQ0P - Read channel DQ0-P VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_DQ0P :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ0P_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ0P_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ0P_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_DQ0P :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ0P_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ0P_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_DQ0P :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ0P_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ0P_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ0P_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_DQ0P :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ0P_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ0P_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_DQ0P :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ0P_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ0P_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ0P_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_DQ0P :: reserved2 [11:08] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ0P_reserved2_MASK 0x00000f00
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ0P_reserved2_SHIFT 8
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_DQ0P :: VDL_STEP [07:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ0P_VDL_STEP_MASK 0x000000ff
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ0P_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ0P_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_RD_DQ0N - Read channel DQ0-N VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_DQ0N :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ0N_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ0N_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ0N_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_DQ0N :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ0N_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ0N_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_DQ0N :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ0N_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ0N_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ0N_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_DQ0N :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ0N_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ0N_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_DQ0N :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ0N_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ0N_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ0N_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_DQ0N :: reserved2 [11:08] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ0N_reserved2_MASK 0x00000f00
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ0N_reserved2_SHIFT 8
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_DQ0N :: VDL_STEP [07:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ0N_VDL_STEP_MASK 0x000000ff
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ0N_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ0N_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_RD_DQ1P - Read channel DQ1-P VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_DQ1P :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ1P_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ1P_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ1P_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_DQ1P :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ1P_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ1P_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_DQ1P :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ1P_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ1P_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ1P_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_DQ1P :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ1P_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ1P_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_DQ1P :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ1P_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ1P_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ1P_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_DQ1P :: reserved2 [11:08] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ1P_reserved2_MASK 0x00000f00
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ1P_reserved2_SHIFT 8
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_DQ1P :: VDL_STEP [07:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ1P_VDL_STEP_MASK 0x000000ff
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ1P_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ1P_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_RD_DQ1N - Read channel DQ1-N VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_DQ1N :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ1N_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ1N_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ1N_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_DQ1N :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ1N_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ1N_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_DQ1N :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ1N_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ1N_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ1N_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_DQ1N :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ1N_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ1N_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_DQ1N :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ1N_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ1N_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ1N_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_DQ1N :: reserved2 [11:08] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ1N_reserved2_MASK 0x00000f00
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ1N_reserved2_SHIFT 8
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_DQ1N :: VDL_STEP [07:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ1N_VDL_STEP_MASK 0x000000ff
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ1N_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ1N_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_RD_DQ2P - Read channel DQ2-P VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_DQ2P :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ2P_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ2P_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ2P_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_DQ2P :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ2P_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ2P_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_DQ2P :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ2P_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ2P_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ2P_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_DQ2P :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ2P_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ2P_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_DQ2P :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ2P_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ2P_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ2P_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_DQ2P :: reserved2 [11:08] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ2P_reserved2_MASK 0x00000f00
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ2P_reserved2_SHIFT 8
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_DQ2P :: VDL_STEP [07:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ2P_VDL_STEP_MASK 0x000000ff
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ2P_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ2P_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_RD_DQ2N - Read channel DQ2-N VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_DQ2N :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ2N_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ2N_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ2N_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_DQ2N :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ2N_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ2N_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_DQ2N :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ2N_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ2N_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ2N_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_DQ2N :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ2N_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ2N_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_DQ2N :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ2N_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ2N_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ2N_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_DQ2N :: reserved2 [11:08] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ2N_reserved2_MASK 0x00000f00
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ2N_reserved2_SHIFT 8
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_DQ2N :: VDL_STEP [07:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ2N_VDL_STEP_MASK 0x000000ff
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ2N_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ2N_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_RD_DQ3P - Read channel DQ3-P VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_DQ3P :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ3P_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ3P_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ3P_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_DQ3P :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ3P_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ3P_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_DQ3P :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ3P_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ3P_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ3P_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_DQ3P :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ3P_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ3P_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_DQ3P :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ3P_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ3P_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ3P_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_DQ3P :: reserved2 [11:08] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ3P_reserved2_MASK 0x00000f00
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ3P_reserved2_SHIFT 8
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_DQ3P :: VDL_STEP [07:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ3P_VDL_STEP_MASK 0x000000ff
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ3P_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ3P_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_RD_DQ3N - Read channel DQ3-N VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_DQ3N :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ3N_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ3N_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ3N_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_DQ3N :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ3N_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ3N_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_DQ3N :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ3N_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ3N_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ3N_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_DQ3N :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ3N_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ3N_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_DQ3N :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ3N_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ3N_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ3N_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_DQ3N :: reserved2 [11:08] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ3N_reserved2_MASK 0x00000f00
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ3N_reserved2_SHIFT 8
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_DQ3N :: VDL_STEP [07:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ3N_VDL_STEP_MASK 0x000000ff
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ3N_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ3N_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_RD_DQ4P - Read channel DQ4-P VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_DQ4P :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ4P_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ4P_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ4P_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_DQ4P :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ4P_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ4P_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_DQ4P :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ4P_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ4P_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ4P_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_DQ4P :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ4P_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ4P_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_DQ4P :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ4P_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ4P_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ4P_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_DQ4P :: reserved2 [11:08] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ4P_reserved2_MASK 0x00000f00
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ4P_reserved2_SHIFT 8
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_DQ4P :: VDL_STEP [07:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ4P_VDL_STEP_MASK 0x000000ff
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ4P_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ4P_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_RD_DQ4N - Read channel DQ4-N VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_DQ4N :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ4N_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ4N_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ4N_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_DQ4N :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ4N_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ4N_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_DQ4N :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ4N_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ4N_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ4N_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_DQ4N :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ4N_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ4N_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_DQ4N :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ4N_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ4N_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ4N_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_DQ4N :: reserved2 [11:08] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ4N_reserved2_MASK 0x00000f00
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ4N_reserved2_SHIFT 8
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_DQ4N :: VDL_STEP [07:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ4N_VDL_STEP_MASK 0x000000ff
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ4N_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ4N_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_RD_DQ5P - Read channel DQ5-P VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_DQ5P :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ5P_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ5P_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ5P_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_DQ5P :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ5P_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ5P_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_DQ5P :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ5P_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ5P_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ5P_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_DQ5P :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ5P_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ5P_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_DQ5P :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ5P_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ5P_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ5P_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_DQ5P :: reserved2 [11:08] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ5P_reserved2_MASK 0x00000f00
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ5P_reserved2_SHIFT 8
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_DQ5P :: VDL_STEP [07:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ5P_VDL_STEP_MASK 0x000000ff
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ5P_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ5P_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_RD_DQ5N - Read channel DQ5-N VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_DQ5N :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ5N_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ5N_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ5N_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_DQ5N :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ5N_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ5N_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_DQ5N :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ5N_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ5N_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ5N_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_DQ5N :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ5N_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ5N_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_DQ5N :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ5N_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ5N_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ5N_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_DQ5N :: reserved2 [11:08] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ5N_reserved2_MASK 0x00000f00
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ5N_reserved2_SHIFT 8
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_DQ5N :: VDL_STEP [07:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ5N_VDL_STEP_MASK 0x000000ff
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ5N_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ5N_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_RD_DQ6P - Read channel DQ6-P VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_DQ6P :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ6P_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ6P_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ6P_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_DQ6P :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ6P_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ6P_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_DQ6P :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ6P_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ6P_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ6P_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_DQ6P :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ6P_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ6P_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_DQ6P :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ6P_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ6P_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ6P_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_DQ6P :: reserved2 [11:08] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ6P_reserved2_MASK 0x00000f00
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ6P_reserved2_SHIFT 8
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_DQ6P :: VDL_STEP [07:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ6P_VDL_STEP_MASK 0x000000ff
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ6P_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ6P_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_RD_DQ6N - Read channel DQ6-N VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_DQ6N :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ6N_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ6N_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ6N_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_DQ6N :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ6N_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ6N_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_DQ6N :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ6N_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ6N_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ6N_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_DQ6N :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ6N_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ6N_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_DQ6N :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ6N_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ6N_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ6N_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_DQ6N :: reserved2 [11:08] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ6N_reserved2_MASK 0x00000f00
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ6N_reserved2_SHIFT 8
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_DQ6N :: VDL_STEP [07:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ6N_VDL_STEP_MASK 0x000000ff
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ6N_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ6N_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_RD_DQ7P - Read channel DQ7-P VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_DQ7P :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ7P_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ7P_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ7P_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_DQ7P :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ7P_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ7P_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_DQ7P :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ7P_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ7P_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ7P_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_DQ7P :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ7P_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ7P_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_DQ7P :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ7P_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ7P_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ7P_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_DQ7P :: reserved2 [11:08] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ7P_reserved2_MASK 0x00000f00
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ7P_reserved2_SHIFT 8
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_DQ7P :: VDL_STEP [07:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ7P_VDL_STEP_MASK 0x000000ff
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ7P_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ7P_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_RD_DQ7N - Read channel DQ7-N VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_DQ7N :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ7N_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ7N_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ7N_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_DQ7N :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ7N_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ7N_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_DQ7N :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ7N_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ7N_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ7N_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_DQ7N :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ7N_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ7N_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_DQ7N :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ7N_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ7N_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ7N_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_DQ7N :: reserved2 [11:08] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ7N_reserved2_MASK 0x00000f00
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ7N_reserved2_SHIFT 8
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_DQ7N :: VDL_STEP [07:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ7N_VDL_STEP_MASK 0x000000ff
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ7N_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ7N_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_RD_DMP - Read channel DM-P VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_DMP :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DMP_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DMP_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DMP_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_DMP :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DMP_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DMP_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_DMP :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DMP_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DMP_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DMP_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_DMP :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DMP_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DMP_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_DMP :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DMP_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DMP_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DMP_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_DMP :: reserved2 [11:08] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DMP_reserved2_MASK 0x00000f00
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DMP_reserved2_SHIFT 8
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_DMP :: VDL_STEP [07:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DMP_VDL_STEP_MASK 0x000000ff
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DMP_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DMP_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_RD_DMN - Read channel DM-N VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_DMN :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DMN_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DMN_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DMN_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_DMN :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DMN_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DMN_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_DMN :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DMN_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DMN_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DMN_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_DMN :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DMN_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DMN_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_DMN :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DMN_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DMN_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DMN_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_DMN :: reserved2 [11:08] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DMN_reserved2_MASK 0x00000f00
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DMN_reserved2_SHIFT 8
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_DMN :: VDL_STEP [07:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DMN_VDL_STEP_MASK 0x000000ff
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DMN_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DMN_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_RD_EDCP - Read channel EDC-P VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_EDCP :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_EDCP_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_EDCP_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_EDCP_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_EDCP :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_EDCP_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_EDCP_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_EDCP :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_EDCP_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_EDCP_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_EDCP_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_EDCP :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_EDCP_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_EDCP_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_EDCP :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_EDCP_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_EDCP_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_EDCP_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_EDCP :: reserved2 [11:08] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_EDCP_reserved2_MASK 0x00000f00
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_EDCP_reserved2_SHIFT 8
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_EDCP :: VDL_STEP [07:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_EDCP_VDL_STEP_MASK 0x000000ff
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_EDCP_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_EDCP_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_RD_EDCN - Read channel EDC-N VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_EDCN :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_EDCN_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_EDCN_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_EDCN_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_EDCN :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_EDCN_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_EDCN_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_EDCN :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_EDCN_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_EDCN_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_EDCN_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_EDCN :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_EDCN_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_EDCN_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_EDCN :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_EDCN_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_EDCN_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_EDCN_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_EDCN :: reserved2 [11:08] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_EDCN_reserved2_MASK 0x00000f00
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_EDCN_reserved2_SHIFT 8
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_EDCN :: VDL_STEP [07:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_EDCN_VDL_STEP_MASK 0x000000ff
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_EDCN_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_EDCN_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_RD_EN_CS0 - Read channel CS_N[0] read enable VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_EN_CS0 :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_EN_CS0_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_EN_CS0_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_EN_CS0_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_EN_CS0 :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_EN_CS0_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_EN_CS0_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_EN_CS0 :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_EN_CS0_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_EN_CS0_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_EN_CS0_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_EN_CS0 :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_EN_CS0_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_EN_CS0_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_EN_CS0 :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_EN_CS0_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_EN_CS0_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_EN_CS0_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_EN_CS0 :: reserved2 [11:08] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_EN_CS0_reserved2_MASK 0x00000f00
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_EN_CS0_reserved2_SHIFT 8
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_EN_CS0 :: VDL_STEP [07:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_EN_CS0_VDL_STEP_MASK 0x000000ff
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_EN_CS0_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_EN_CS0_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_RD_EN_CS1 - Read channel CS_N[1] read enable VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_EN_CS1 :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_EN_CS1_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_EN_CS1_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_EN_CS1_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_EN_CS1 :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_EN_CS1_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_EN_CS1_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_EN_CS1 :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_EN_CS1_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_EN_CS1_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_EN_CS1_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_EN_CS1 :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_EN_CS1_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_EN_CS1_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_EN_CS1 :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_EN_CS1_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_EN_CS1_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_EN_CS1_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_EN_CS1 :: reserved2 [11:08] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_EN_CS1_reserved2_MASK 0x00000f00
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_EN_CS1_reserved2_SHIFT 8
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_EN_CS1 :: VDL_STEP [07:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_EN_CS1_VDL_STEP_MASK 0x000000ff
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_EN_CS1_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_EN_CS1_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CLK_CONTROL - DDR interface signal Write Leveling CLK VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CLK_CONTROL :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CLK_CONTROL_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CLK_CONTROL_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CLK_CONTROL_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CLK_CONTROL :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CLK_CONTROL_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CLK_CONTROL_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CLK_CONTROL :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CLK_CONTROL_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CLK_CONTROL_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CLK_CONTROL_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CLK_CONTROL :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CLK_CONTROL_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CLK_CONTROL_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CLK_CONTROL :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CLK_CONTROL_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CLK_CONTROL_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CLK_CONTROL_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CLK_CONTROL :: reserved2 [11:09] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CLK_CONTROL_reserved2_MASK 0x00000e00
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CLK_CONTROL_reserved2_SHIFT 9
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CLK_CONTROL :: VDL_STEP [08:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CLK_CONTROL_VDL_STEP_MASK 0x000001ff
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CLK_CONTROL_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CLK_CONTROL_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_LDE_CONTROL - DDR interface signal Write Leveling Capture Enable VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_LDE_CONTROL :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_LDE_CONTROL_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_LDE_CONTROL_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_LDE_CONTROL_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_LDE_CONTROL :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_LDE_CONTROL_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_LDE_CONTROL_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_LDE_CONTROL :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_LDE_CONTROL_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_LDE_CONTROL_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_LDE_CONTROL_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_LDE_CONTROL :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_LDE_CONTROL_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_LDE_CONTROL_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_LDE_CONTROL :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_LDE_CONTROL_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_LDE_CONTROL_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_LDE_CONTROL_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_LDE_CONTROL :: reserved2 [11:09] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_LDE_CONTROL_reserved2_MASK 0x00000e00
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_LDE_CONTROL_reserved2_SHIFT 9
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_LDE_CONTROL :: VDL_STEP [08:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_LDE_CONTROL_VDL_STEP_MASK 0x000001ff
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_LDE_CONTROL_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_LDE_CONTROL_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *RD_EN_DLY_CYC - Read enable bit-clock cycle delay control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_3_0 :: RD_EN_DLY_CYC :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_RD_EN_DLY_CYC_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_RD_EN_DLY_CYC_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_RD_EN_DLY_CYC_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: RD_EN_DLY_CYC :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_RD_EN_DLY_CYC_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_RD_EN_DLY_CYC_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: RD_EN_DLY_CYC :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_RD_EN_DLY_CYC_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_RD_EN_DLY_CYC_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_RD_EN_DLY_CYC_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: RD_EN_DLY_CYC :: reserved1 [15:08] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_RD_EN_DLY_CYC_reserved1_MASK 0x0000ff00
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_RD_EN_DLY_CYC_reserved1_SHIFT 8
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: RD_EN_DLY_CYC :: CS1_CYCLES [07:04] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_RD_EN_DLY_CYC_CS1_CYCLES_MASK 0x000000f0
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_RD_EN_DLY_CYC_CS1_CYCLES_SHIFT 4
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_RD_EN_DLY_CYC_CS1_CYCLES_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: RD_EN_DLY_CYC :: CS0_CYCLES [03:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_RD_EN_DLY_CYC_CS0_CYCLES_MASK 0x0000000f
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_RD_EN_DLY_CYC_CS0_CYCLES_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_RD_EN_DLY_CYC_CS0_CYCLES_DEFAULT 0x00000000
-
-/***************************************************************************
- *WR_CHAN_DLY_CYC - Write leveling bit-clock cycle delay control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_3_0 :: WR_CHAN_DLY_CYC :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_WR_CHAN_DLY_CYC_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_WR_CHAN_DLY_CYC_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_WR_CHAN_DLY_CYC_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: WR_CHAN_DLY_CYC :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_WR_CHAN_DLY_CYC_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_WR_CHAN_DLY_CYC_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: WR_CHAN_DLY_CYC :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_WR_CHAN_DLY_CYC_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_WR_CHAN_DLY_CYC_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_WR_CHAN_DLY_CYC_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: WR_CHAN_DLY_CYC :: reserved1 [15:03] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_WR_CHAN_DLY_CYC_reserved1_MASK 0x0000fff8
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_WR_CHAN_DLY_CYC_reserved1_SHIFT 3
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: WR_CHAN_DLY_CYC :: CYCLES [02:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_WR_CHAN_DLY_CYC_CYCLES_MASK 0x00000007
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_WR_CHAN_DLY_CYC_CYCLES_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_WR_CHAN_DLY_CYC_CYCLES_DEFAULT 0x00000000
-
-/***************************************************************************
- *READ_CONTROL - Read channel datapath control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_3_0 :: READ_CONTROL :: reserved0 [31:05] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_READ_CONTROL_reserved0_MASK 0xffffffe0
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_READ_CONTROL_reserved0_SHIFT 5
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: READ_CONTROL :: MODE [04:04] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_READ_CONTROL_MODE_MASK 0x00000010
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_READ_CONTROL_MODE_SHIFT 4
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_READ_CONTROL_MODE_DEFAULT 0x00000001
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: READ_CONTROL :: reserved1 [03:03] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_READ_CONTROL_reserved1_MASK 0x00000008
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_READ_CONTROL_reserved1_SHIFT 3
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: READ_CONTROL :: RD_DATA_DLY [02:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_READ_CONTROL_RD_DATA_DLY_MASK 0x00000007
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_READ_CONTROL_RD_DATA_DLY_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_READ_CONTROL_RD_DATA_DLY_DEFAULT 0x00000007
-
-/***************************************************************************
- *READ_FIFO_ADDR - Read fifo addresss pointer register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_3_0 :: READ_FIFO_ADDR :: reserved0 [31:03] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_READ_FIFO_ADDR_reserved0_MASK 0xfffffff8
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_READ_FIFO_ADDR_reserved0_SHIFT 3
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: READ_FIFO_ADDR :: ADDR [02:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_READ_FIFO_ADDR_ADDR_MASK 0x00000007
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_READ_FIFO_ADDR_ADDR_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_READ_FIFO_ADDR_ADDR_DEFAULT 0x00000000
-
-/***************************************************************************
- *READ_FIFO_DATA - Read fifo data register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_3_0 :: READ_FIFO_DATA :: DATA [31:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_READ_FIFO_DATA_DATA_MASK 0xffffffff
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_READ_FIFO_DATA_DATA_SHIFT 0
-
-/***************************************************************************
- *READ_FIFO_DM_DBI - Read fifo dm/dbi register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_3_0 :: READ_FIFO_DM_DBI :: reserved0 [31:04] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_READ_FIFO_DM_DBI_reserved0_MASK 0xfffffff0
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_READ_FIFO_DM_DBI_reserved0_SHIFT 4
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: READ_FIFO_DM_DBI :: DM_DBI [03:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_READ_FIFO_DM_DBI_DM_DBI_MASK 0x0000000f
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_READ_FIFO_DM_DBI_DM_DBI_SHIFT 0
-
-/***************************************************************************
- *READ_FIFO_STATUS - Read fifo status register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_3_0 :: READ_FIFO_STATUS :: reserved0 [31:02] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_READ_FIFO_STATUS_reserved0_MASK 0xfffffffc
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_READ_FIFO_STATUS_reserved0_SHIFT 2
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: READ_FIFO_STATUS :: OVERFLOW [01:01] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_READ_FIFO_STATUS_OVERFLOW_MASK 0x00000002
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_READ_FIFO_STATUS_OVERFLOW_SHIFT 1
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_READ_FIFO_STATUS_OVERFLOW_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: READ_FIFO_STATUS :: UNDERFLOW [00:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_READ_FIFO_STATUS_UNDERFLOW_MASK 0x00000001
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_READ_FIFO_STATUS_UNDERFLOW_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_READ_FIFO_STATUS_UNDERFLOW_DEFAULT 0x00000000
-
-/***************************************************************************
- *READ_FIFO_CLEAR - Read fifo status clear register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_3_0 :: READ_FIFO_CLEAR :: reserved0 [31:01] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_READ_FIFO_CLEAR_reserved0_MASK 0xfffffffe
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_READ_FIFO_CLEAR_reserved0_SHIFT 1
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: READ_FIFO_CLEAR :: CLEAR [00:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_READ_FIFO_CLEAR_CLEAR_MASK 0x00000001
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_READ_FIFO_CLEAR_CLEAR_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_READ_FIFO_CLEAR_CLEAR_DEFAULT 0x00000000
-
-/***************************************************************************
- *IDLE_PAD_CONTROL - Idle mode SSTL pad control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_3_0 :: IDLE_PAD_CONTROL :: IDLE [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_IDLE_PAD_CONTROL_IDLE_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_IDLE_PAD_CONTROL_IDLE_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_IDLE_PAD_CONTROL_IDLE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: IDLE_PAD_CONTROL :: reserved0 [30:20] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_IDLE_PAD_CONTROL_reserved0_MASK 0x7ff00000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_IDLE_PAD_CONTROL_reserved0_SHIFT 20
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: IDLE_PAD_CONTROL :: AUTO_DQ_RXENB_MODE [19:18] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_IDLE_PAD_CONTROL_AUTO_DQ_RXENB_MODE_MASK 0x000c0000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_IDLE_PAD_CONTROL_AUTO_DQ_RXENB_MODE_SHIFT 18
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_IDLE_PAD_CONTROL_AUTO_DQ_RXENB_MODE_DEFAULT 0x00000001
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: IDLE_PAD_CONTROL :: AUTO_DQ_IDDQ_MODE [17:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_IDLE_PAD_CONTROL_AUTO_DQ_IDDQ_MODE_MASK 0x00030000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_IDLE_PAD_CONTROL_AUTO_DQ_IDDQ_MODE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_IDLE_PAD_CONTROL_AUTO_DQ_IDDQ_MODE_DEFAULT 0x00000001
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: IDLE_PAD_CONTROL :: reserved_for_padding1 [15:15] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_IDLE_PAD_CONTROL_reserved_for_padding1_MASK 0x00008000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_IDLE_PAD_CONTROL_reserved_for_padding1_SHIFT 15
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: IDLE_PAD_CONTROL :: IO_IDLE_ENABLE [14:04] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_IDLE_PAD_CONTROL_IO_IDLE_ENABLE_MASK 0x00007ff0
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_IDLE_PAD_CONTROL_IO_IDLE_ENABLE_SHIFT 4
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_IDLE_PAD_CONTROL_IO_IDLE_ENABLE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: IDLE_PAD_CONTROL :: RXENB [03:03] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_IDLE_PAD_CONTROL_RXENB_MASK 0x00000008
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_IDLE_PAD_CONTROL_RXENB_SHIFT 3
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_IDLE_PAD_CONTROL_RXENB_DEFAULT 0x00000001
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: IDLE_PAD_CONTROL :: IDDQ [02:02] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_IDLE_PAD_CONTROL_IDDQ_MASK 0x00000004
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_IDLE_PAD_CONTROL_IDDQ_SHIFT 2
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_IDLE_PAD_CONTROL_IDDQ_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: IDLE_PAD_CONTROL :: DOUT_N [01:01] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_IDLE_PAD_CONTROL_DOUT_N_MASK 0x00000002
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_IDLE_PAD_CONTROL_DOUT_N_SHIFT 1
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: IDLE_PAD_CONTROL :: DOUT_P [00:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_IDLE_PAD_CONTROL_DOUT_P_MASK 0x00000001
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_IDLE_PAD_CONTROL_DOUT_P_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_IDLE_PAD_CONTROL_DOUT_P_DEFAULT 0x00000000
-
-/***************************************************************************
- *DRIVE_PAD_CTL - SSTL pad drive characteristics control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_3_0 :: DRIVE_PAD_CTL :: reserved0 [31:30] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_DRIVE_PAD_CTL_reserved0_MASK 0xc0000000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_DRIVE_PAD_CTL_reserved0_SHIFT 30
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: DRIVE_PAD_CTL :: BL_PD_IDLE_STRENGTH [29:25] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_DRIVE_PAD_CTL_BL_PD_IDLE_STRENGTH_MASK 0x3e000000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_DRIVE_PAD_CTL_BL_PD_IDLE_STRENGTH_SHIFT 25
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_DRIVE_PAD_CTL_BL_PD_IDLE_STRENGTH_DEFAULT 0x0000001f
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: DRIVE_PAD_CTL :: BL_ND_IDLE_STRENGTH [24:20] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_DRIVE_PAD_CTL_BL_ND_IDLE_STRENGTH_MASK 0x01f00000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_DRIVE_PAD_CTL_BL_ND_IDLE_STRENGTH_SHIFT 20
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_DRIVE_PAD_CTL_BL_ND_IDLE_STRENGTH_DEFAULT 0x0000001f
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: DRIVE_PAD_CTL :: BL_PD_TERM_STRENGTH [19:15] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_DRIVE_PAD_CTL_BL_PD_TERM_STRENGTH_MASK 0x000f8000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_DRIVE_PAD_CTL_BL_PD_TERM_STRENGTH_SHIFT 15
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_DRIVE_PAD_CTL_BL_PD_TERM_STRENGTH_DEFAULT 0x00000008
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: DRIVE_PAD_CTL :: BL_ND_TERM_STRENGTH [14:10] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_DRIVE_PAD_CTL_BL_ND_TERM_STRENGTH_MASK 0x00007c00
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_DRIVE_PAD_CTL_BL_ND_TERM_STRENGTH_SHIFT 10
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_DRIVE_PAD_CTL_BL_ND_TERM_STRENGTH_DEFAULT 0x00000008
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: DRIVE_PAD_CTL :: BL_PD_STRENGTH [09:05] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_DRIVE_PAD_CTL_BL_PD_STRENGTH_MASK 0x000003e0
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_DRIVE_PAD_CTL_BL_PD_STRENGTH_SHIFT 5
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_DRIVE_PAD_CTL_BL_PD_STRENGTH_DEFAULT 0x0000001f
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: DRIVE_PAD_CTL :: BL_ND_STRENGTH [04:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_DRIVE_PAD_CTL_BL_ND_STRENGTH_MASK 0x0000001f
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_DRIVE_PAD_CTL_BL_ND_STRENGTH_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_DRIVE_PAD_CTL_BL_ND_STRENGTH_DEFAULT 0x0000001f
-
-/***************************************************************************
- *RD_EN_DRIVE_PAD_CTL - SSTL read enable pad drive characteristics control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_3_0 :: RD_EN_DRIVE_PAD_CTL :: reserved0 [31:20] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_RD_EN_DRIVE_PAD_CTL_reserved0_MASK 0xfff00000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_RD_EN_DRIVE_PAD_CTL_reserved0_SHIFT 20
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: RD_EN_DRIVE_PAD_CTL :: EDC_RD_EN_PD_STRENGTH [19:15] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_RD_EN_DRIVE_PAD_CTL_EDC_RD_EN_PD_STRENGTH_MASK 0x000f8000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_RD_EN_DRIVE_PAD_CTL_EDC_RD_EN_PD_STRENGTH_SHIFT 15
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_RD_EN_DRIVE_PAD_CTL_EDC_RD_EN_PD_STRENGTH_DEFAULT 0x0000001f
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: RD_EN_DRIVE_PAD_CTL :: EDC_RD_EN_ND_STRENGTH [14:10] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_RD_EN_DRIVE_PAD_CTL_EDC_RD_EN_ND_STRENGTH_MASK 0x00007c00
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_RD_EN_DRIVE_PAD_CTL_EDC_RD_EN_ND_STRENGTH_SHIFT 10
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_RD_EN_DRIVE_PAD_CTL_EDC_RD_EN_ND_STRENGTH_DEFAULT 0x0000001f
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: RD_EN_DRIVE_PAD_CTL :: BL_RD_EN_PD_STRENGTH [09:05] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_RD_EN_DRIVE_PAD_CTL_BL_RD_EN_PD_STRENGTH_MASK 0x000003e0
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_RD_EN_DRIVE_PAD_CTL_BL_RD_EN_PD_STRENGTH_SHIFT 5
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_RD_EN_DRIVE_PAD_CTL_BL_RD_EN_PD_STRENGTH_DEFAULT 0x0000001f
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: RD_EN_DRIVE_PAD_CTL :: BL_RD_EN_ND_STRENGTH [04:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_RD_EN_DRIVE_PAD_CTL_BL_RD_EN_ND_STRENGTH_MASK 0x0000001f
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_RD_EN_DRIVE_PAD_CTL_BL_RD_EN_ND_STRENGTH_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_RD_EN_DRIVE_PAD_CTL_BL_RD_EN_ND_STRENGTH_DEFAULT 0x0000001f
-
-/***************************************************************************
- *STATIC_PAD_CTL - pad rx and tx characteristics control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_3_0 :: STATIC_PAD_CTL :: reserved0 [31:21] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_STATIC_PAD_CTL_reserved0_MASK 0xffe00000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_STATIC_PAD_CTL_reserved0_SHIFT 21
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: STATIC_PAD_CTL :: DQS_MODE [20:20] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_STATIC_PAD_CTL_DQS_MODE_MASK 0x00100000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_STATIC_PAD_CTL_DQS_MODE_SHIFT 20
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_STATIC_PAD_CTL_DQS_MODE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: STATIC_PAD_CTL :: reserved1 [19:18] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_STATIC_PAD_CTL_reserved1_MASK 0x000c0000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_STATIC_PAD_CTL_reserved1_SHIFT 18
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: STATIC_PAD_CTL :: EDC_MODE [17:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_STATIC_PAD_CTL_EDC_MODE_MASK 0x00030000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_STATIC_PAD_CTL_EDC_MODE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_STATIC_PAD_CTL_EDC_MODE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: STATIC_PAD_CTL :: reserved2 [15:15] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_STATIC_PAD_CTL_reserved2_MASK 0x00008000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_STATIC_PAD_CTL_reserved2_SHIFT 15
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: STATIC_PAD_CTL :: WDBI_ENABLE [14:14] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_STATIC_PAD_CTL_WDBI_ENABLE_MASK 0x00004000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_STATIC_PAD_CTL_WDBI_ENABLE_SHIFT 14
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_STATIC_PAD_CTL_WDBI_ENABLE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: STATIC_PAD_CTL :: RDBI_ENABLE [13:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_STATIC_PAD_CTL_RDBI_ENABLE_MASK 0x00002000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_STATIC_PAD_CTL_RDBI_ENABLE_SHIFT 13
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_STATIC_PAD_CTL_RDBI_ENABLE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: STATIC_PAD_CTL :: DM_MODE [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_STATIC_PAD_CTL_DM_MODE_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_STATIC_PAD_CTL_DM_MODE_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_STATIC_PAD_CTL_DM_MODE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: STATIC_PAD_CTL :: reserved3 [11:11] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_STATIC_PAD_CTL_reserved3_MASK 0x00000800
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_STATIC_PAD_CTL_reserved3_SHIFT 11
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: STATIC_PAD_CTL :: DQS_TX_PAUSE [10:10] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_STATIC_PAD_CTL_DQS_TX_PAUSE_MASK 0x00000400
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_STATIC_PAD_CTL_DQS_TX_PAUSE_SHIFT 10
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_STATIC_PAD_CTL_DQS_TX_PAUSE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: STATIC_PAD_CTL :: DQS_TX_DIS [09:09] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_STATIC_PAD_CTL_DQS_TX_DIS_MASK 0x00000200
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_STATIC_PAD_CTL_DQS_TX_DIS_SHIFT 9
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_STATIC_PAD_CTL_DQS_TX_DIS_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: STATIC_PAD_CTL :: reserved4 [08:08] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_STATIC_PAD_CTL_reserved4_MASK 0x00000100
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_STATIC_PAD_CTL_reserved4_SHIFT 8
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: STATIC_PAD_CTL :: TX_MODE [07:04] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_STATIC_PAD_CTL_TX_MODE_MASK 0x000000f0
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_STATIC_PAD_CTL_TX_MODE_SHIFT 4
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_STATIC_PAD_CTL_TX_MODE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: STATIC_PAD_CTL :: reserved5 [03:03] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_STATIC_PAD_CTL_reserved5_MASK 0x00000008
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_STATIC_PAD_CTL_reserved5_SHIFT 3
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: STATIC_PAD_CTL :: RX_MODE [02:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_STATIC_PAD_CTL_RX_MODE_MASK 0x00000007
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_STATIC_PAD_CTL_RX_MODE_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_STATIC_PAD_CTL_RX_MODE_DEFAULT 0x00000000
-
-/***************************************************************************
- *WR_PREAMBLE_MODE - Write cycle preamble control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_3_0 :: WR_PREAMBLE_MODE :: reserved0 [31:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_WR_PREAMBLE_MODE_reserved0_MASK 0xffff0000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_WR_PREAMBLE_MODE_reserved0_SHIFT 16
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: WR_PREAMBLE_MODE :: DQ_POSTAM_BITS [15:14] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_WR_PREAMBLE_MODE_DQ_POSTAM_BITS_MASK 0x0000c000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_WR_PREAMBLE_MODE_DQ_POSTAM_BITS_SHIFT 14
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_WR_PREAMBLE_MODE_DQ_POSTAM_BITS_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: WR_PREAMBLE_MODE :: DQ_PREAM_BITS [13:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_WR_PREAMBLE_MODE_DQ_PREAM_BITS_MASK 0x00003000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_WR_PREAMBLE_MODE_DQ_PREAM_BITS_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_WR_PREAMBLE_MODE_DQ_PREAM_BITS_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: WR_PREAMBLE_MODE :: DQS [11:08] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_WR_PREAMBLE_MODE_DQS_MASK 0x00000f00
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_WR_PREAMBLE_MODE_DQS_SHIFT 8
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_WR_PREAMBLE_MODE_DQS_DEFAULT 0x0000000e
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: WR_PREAMBLE_MODE :: reserved1 [07:05] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_WR_PREAMBLE_MODE_reserved1_MASK 0x000000e0
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_WR_PREAMBLE_MODE_reserved1_SHIFT 5
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: WR_PREAMBLE_MODE :: DQS_POSTAM_BITS [04:03] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_WR_PREAMBLE_MODE_DQS_POSTAM_BITS_MASK 0x00000018
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_WR_PREAMBLE_MODE_DQS_POSTAM_BITS_SHIFT 3
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_WR_PREAMBLE_MODE_DQS_POSTAM_BITS_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: WR_PREAMBLE_MODE :: DQS_PREAM_BITS [02:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_WR_PREAMBLE_MODE_DQS_PREAM_BITS_MASK 0x00000007
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_WR_PREAMBLE_MODE_DQS_PREAM_BITS_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_WR_PREAMBLE_MODE_DQS_PREAM_BITS_DEFAULT 0x00000002
-
-/***************************************************************************
- *ODT_CONTROL - Read channel ODT control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_3_0 :: ODT_CONTROL :: reserved_for_padding0 [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_ODT_CONTROL_reserved_for_padding0_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_ODT_CONTROL_reserved_for_padding0_SHIFT 31
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: ODT_CONTROL :: reserved1 [30:10] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_ODT_CONTROL_reserved1_MASK 0x7ffffc00
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_ODT_CONTROL_reserved1_SHIFT 10
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: ODT_CONTROL :: ODT_ENABLE [09:09] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_ODT_CONTROL_ODT_ENABLE_MASK 0x00000200
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_ODT_CONTROL_ODT_ENABLE_SHIFT 9
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_ODT_CONTROL_ODT_ENABLE_DEFAULT 0x00000001
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: ODT_CONTROL :: ODT_DELAY [08:06] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_ODT_CONTROL_ODT_DELAY_MASK 0x000001c0
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_ODT_CONTROL_ODT_DELAY_SHIFT 6
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_ODT_CONTROL_ODT_DELAY_DEFAULT 0x00000001
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: ODT_CONTROL :: ODT_POST_LENGTH [05:03] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_ODT_CONTROL_ODT_POST_LENGTH_MASK 0x00000038
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_ODT_CONTROL_ODT_POST_LENGTH_SHIFT 3
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_ODT_CONTROL_ODT_POST_LENGTH_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: ODT_CONTROL :: ODT_PRE_LENGTH [02:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_ODT_CONTROL_ODT_PRE_LENGTH_MASK 0x00000007
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_ODT_CONTROL_ODT_PRE_LENGTH_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_ODT_CONTROL_ODT_PRE_LENGTH_DEFAULT 0x00000003
-
-/***************************************************************************
- *EDC_DPD_CONTROL - GDDR5M EDC digital phase detector control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_3_0 :: EDC_DPD_CONTROL :: reserved0 [31:06] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_DPD_CONTROL_reserved0_MASK 0xffffffc0
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_DPD_CONTROL_reserved0_SHIFT 6
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: EDC_DPD_CONTROL :: DQS_PHASE_OVERRIDE_VALUE [05:05] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_DPD_CONTROL_DQS_PHASE_OVERRIDE_VALUE_MASK 0x00000020
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_DPD_CONTROL_DQS_PHASE_OVERRIDE_VALUE_SHIFT 5
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_DPD_CONTROL_DQS_PHASE_OVERRIDE_VALUE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: EDC_DPD_CONTROL :: DQS_PHASE_OVERRIDE_ENABLE [04:04] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_DPD_CONTROL_DQS_PHASE_OVERRIDE_ENABLE_MASK 0x00000010
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_DPD_CONTROL_DQS_PHASE_OVERRIDE_ENABLE_SHIFT 4
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_DPD_CONTROL_DQS_PHASE_OVERRIDE_ENABLE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: EDC_DPD_CONTROL :: SET_ADJ_EN [03:03] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_DPD_CONTROL_SET_ADJ_EN_MASK 0x00000008
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_DPD_CONTROL_SET_ADJ_EN_SHIFT 3
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_DPD_CONTROL_SET_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: EDC_DPD_CONTROL :: UPDATE [02:02] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_DPD_CONTROL_UPDATE_MASK 0x00000004
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_DPD_CONTROL_UPDATE_SHIFT 2
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_DPD_CONTROL_UPDATE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: EDC_DPD_CONTROL :: MONITOR [01:01] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_DPD_CONTROL_MONITOR_MASK 0x00000002
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_DPD_CONTROL_MONITOR_SHIFT 1
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_DPD_CONTROL_MONITOR_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: EDC_DPD_CONTROL :: INIT [00:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_DPD_CONTROL_INIT_MASK 0x00000001
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_DPD_CONTROL_INIT_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_DPD_CONTROL_INIT_DEFAULT 0x00000000
-
-/***************************************************************************
- *EDC_DPD_STATUS - GDDR5M EDC digital phase detector status register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_3_0 :: EDC_DPD_STATUS :: reserved0 [31:25] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_DPD_STATUS_reserved0_MASK 0xfe000000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_DPD_STATUS_reserved0_SHIFT 25
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: EDC_DPD_STATUS :: CURRENT_DQS_PHASE [24:24] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_DPD_STATUS_CURRENT_DQS_PHASE_MASK 0x01000000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_DPD_STATUS_CURRENT_DQS_PHASE_SHIFT 24
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_DPD_STATUS_CURRENT_DQS_PHASE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: EDC_DPD_STATUS :: CURRENT_VDL_SETTING [23:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_DPD_STATUS_CURRENT_VDL_SETTING_MASK 0x00ff0000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_DPD_STATUS_CURRENT_VDL_SETTING_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_DPD_STATUS_CURRENT_VDL_SETTING_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: EDC_DPD_STATUS :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_DPD_STATUS_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_DPD_STATUS_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: EDC_DPD_STATUS :: INIT_DQS_PHASE [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_DPD_STATUS_INIT_DQS_PHASE_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_DPD_STATUS_INIT_DQS_PHASE_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_DPD_STATUS_INIT_DQS_PHASE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: EDC_DPD_STATUS :: INIT_VDL_SETTING [11:04] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_DPD_STATUS_INIT_VDL_SETTING_MASK 0x00000ff0
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_DPD_STATUS_INIT_VDL_SETTING_SHIFT 4
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_DPD_STATUS_INIT_VDL_SETTING_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: EDC_DPD_STATUS :: EDGE_ERROR [03:03] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_DPD_STATUS_EDGE_ERROR_MASK 0x00000008
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_DPD_STATUS_EDGE_ERROR_SHIFT 3
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_DPD_STATUS_EDGE_ERROR_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: EDC_DPD_STATUS :: MONITOR_BUSY [02:02] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_DPD_STATUS_MONITOR_BUSY_MASK 0x00000004
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_DPD_STATUS_MONITOR_BUSY_SHIFT 2
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_DPD_STATUS_MONITOR_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: EDC_DPD_STATUS :: INIT_BUSY [01:01] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_DPD_STATUS_INIT_BUSY_MASK 0x00000002
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_DPD_STATUS_INIT_BUSY_SHIFT 1
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_DPD_STATUS_INIT_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: EDC_DPD_STATUS :: INIT_DONE [00:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_DPD_STATUS_INIT_DONE_MASK 0x00000001
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_DPD_STATUS_INIT_DONE_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_DPD_STATUS_INIT_DONE_DEFAULT 0x00000000
-
-/***************************************************************************
- *EDC_DPD_OUT_CONTROL - GDDR5M EDC digital phase detector output signal control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_3_0 :: EDC_DPD_OUT_CONTROL :: reserved0 [31:20] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_DPD_OUT_CONTROL_reserved0_MASK 0xfff00000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_DPD_OUT_CONTROL_reserved0_SHIFT 20
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: EDC_DPD_OUT_CONTROL :: LOWER_LIMIT [19:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_DPD_OUT_CONTROL_LOWER_LIMIT_MASK 0x000ff000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_DPD_OUT_CONTROL_LOWER_LIMIT_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_DPD_OUT_CONTROL_LOWER_LIMIT_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: EDC_DPD_OUT_CONTROL :: UPPER_LIMIT [11:04] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_DPD_OUT_CONTROL_UPPER_LIMIT_MASK 0x00000ff0
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_DPD_OUT_CONTROL_UPPER_LIMIT_SHIFT 4
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_DPD_OUT_CONTROL_UPPER_LIMIT_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: EDC_DPD_OUT_CONTROL :: reserved1 [03:01] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_DPD_OUT_CONTROL_reserved1_MASK 0x0000000e
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_DPD_OUT_CONTROL_reserved1_SHIFT 1
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: EDC_DPD_OUT_CONTROL :: ENABLE [00:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_DPD_OUT_CONTROL_ENABLE_MASK 0x00000001
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_DPD_OUT_CONTROL_ENABLE_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_DPD_OUT_CONTROL_ENABLE_DEFAULT 0x00000000
-
-/***************************************************************************
- *EDC_DPD_OUT_STATUS - GDDR5M EDC digital phase detector output signal status register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_3_0 :: EDC_DPD_OUT_STATUS :: reserved0 [31:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_DPD_OUT_STATUS_reserved0_MASK 0xfffff000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_DPD_OUT_STATUS_reserved0_SHIFT 12
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: EDC_DPD_OUT_STATUS :: VDL_SETTING [11:04] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_DPD_OUT_STATUS_VDL_SETTING_MASK 0x00000ff0
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_DPD_OUT_STATUS_VDL_SETTING_SHIFT 4
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_DPD_OUT_STATUS_VDL_SETTING_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: EDC_DPD_OUT_STATUS :: reserved1 [03:01] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_DPD_OUT_STATUS_reserved1_MASK 0x0000000e
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_DPD_OUT_STATUS_reserved1_SHIFT 1
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: EDC_DPD_OUT_STATUS :: VALID [00:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_DPD_OUT_STATUS_VALID_MASK 0x00000001
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_DPD_OUT_STATUS_VALID_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_DPD_OUT_STATUS_VALID_DEFAULT 0x00000000
-
-/***************************************************************************
- *EDC_DPD_OUT_STATUS_CLEAR - GDDR5M EDC digital phase detector output signal status clear register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_3_0 :: EDC_DPD_OUT_STATUS_CLEAR :: reserved0 [31:01] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_DPD_OUT_STATUS_CLEAR_reserved0_MASK 0xfffffffe
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_DPD_OUT_STATUS_CLEAR_reserved0_SHIFT 1
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: EDC_DPD_OUT_STATUS_CLEAR :: CLEAR [00:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_DPD_OUT_STATUS_CLEAR_CLEAR_MASK 0x00000001
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_DPD_OUT_STATUS_CLEAR_CLEAR_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_DPD_OUT_STATUS_CLEAR_CLEAR_DEFAULT 0x00000000
-
-/***************************************************************************
- *EDC_CRC_CONTROL - GDDR5M EDC signal path CRC control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_3_0 :: EDC_CRC_CONTROL :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_CRC_CONTROL_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_CRC_CONTROL_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_CRC_CONTROL_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: EDC_CRC_CONTROL :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_CRC_CONTROL_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_CRC_CONTROL_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: EDC_CRC_CONTROL :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_CRC_CONTROL_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_CRC_CONTROL_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_CRC_CONTROL_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: EDC_CRC_CONTROL :: reserved1 [15:11] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_CRC_CONTROL_reserved1_MASK 0x0000f800
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_CRC_CONTROL_reserved1_SHIFT 11
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: EDC_CRC_CONTROL :: CRCWL [10:08] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_CRC_CONTROL_CRCWL_MASK 0x00000700
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_CRC_CONTROL_CRCWL_SHIFT 8
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_CRC_CONTROL_CRCWL_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: EDC_CRC_CONTROL :: reserved2 [07:06] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_CRC_CONTROL_reserved2_MASK 0x000000c0
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_CRC_CONTROL_reserved2_SHIFT 6
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: EDC_CRC_CONTROL :: CRCRL [05:04] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_CRC_CONTROL_CRCRL_MASK 0x00000030
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_CRC_CONTROL_CRCRL_SHIFT 4
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_CRC_CONTROL_CRCRL_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: EDC_CRC_CONTROL :: reserved3 [03:03] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_CRC_CONTROL_reserved3_MASK 0x00000008
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_CRC_CONTROL_reserved3_SHIFT 3
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: EDC_CRC_CONTROL :: COUNT_MODE [02:02] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_CRC_CONTROL_COUNT_MODE_MASK 0x00000004
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_CRC_CONTROL_COUNT_MODE_SHIFT 2
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_CRC_CONTROL_COUNT_MODE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: EDC_CRC_CONTROL :: ENABLE_WR [01:01] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_CRC_CONTROL_ENABLE_WR_MASK 0x00000002
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_CRC_CONTROL_ENABLE_WR_SHIFT 1
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_CRC_CONTROL_ENABLE_WR_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: EDC_CRC_CONTROL :: ENABLE_RD [00:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_CRC_CONTROL_ENABLE_RD_MASK 0x00000001
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_CRC_CONTROL_ENABLE_RD_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_CRC_CONTROL_ENABLE_RD_DEFAULT 0x00000000
-
-/***************************************************************************
- *EDC_CRC_STATUS - GDDR5M EDC signal path CRC status register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_3_0 :: EDC_CRC_STATUS :: reserved0 [31:04] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_CRC_STATUS_reserved0_MASK 0xfffffff0
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_CRC_STATUS_reserved0_SHIFT 4
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: EDC_CRC_STATUS :: WR_FAIL [03:03] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_CRC_STATUS_WR_FAIL_MASK 0x00000008
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_CRC_STATUS_WR_FAIL_SHIFT 3
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_CRC_STATUS_WR_FAIL_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: EDC_CRC_STATUS :: WR_PASS [02:02] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_CRC_STATUS_WR_PASS_MASK 0x00000004
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_CRC_STATUS_WR_PASS_SHIFT 2
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_CRC_STATUS_WR_PASS_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: EDC_CRC_STATUS :: RD_FAIL [01:01] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_CRC_STATUS_RD_FAIL_MASK 0x00000002
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_CRC_STATUS_RD_FAIL_SHIFT 1
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_CRC_STATUS_RD_FAIL_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: EDC_CRC_STATUS :: RD_PASS [00:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_CRC_STATUS_RD_PASS_MASK 0x00000001
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_CRC_STATUS_RD_PASS_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_CRC_STATUS_RD_PASS_DEFAULT 0x00000000
-
-/***************************************************************************
- *EDC_CRC_COUNT - GDDR5M EDC signal path CRC counter register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_3_0 :: EDC_CRC_COUNT :: reserved0 [31:28] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_CRC_COUNT_reserved0_MASK 0xf0000000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_CRC_COUNT_reserved0_SHIFT 28
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: EDC_CRC_COUNT :: WR_COUNT [27:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_CRC_COUNT_WR_COUNT_MASK 0x0fff0000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_CRC_COUNT_WR_COUNT_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_CRC_COUNT_WR_COUNT_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: EDC_CRC_COUNT :: reserved1 [15:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_CRC_COUNT_reserved1_MASK 0x0000f000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_CRC_COUNT_reserved1_SHIFT 12
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: EDC_CRC_COUNT :: RD_COUNT [11:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_CRC_COUNT_RD_COUNT_MASK 0x00000fff
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_CRC_COUNT_RD_COUNT_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_CRC_COUNT_RD_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *EDC_CRC_STATUS_CLEAR - GDDR5M EDC signal path CRC counter register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_3_0 :: EDC_CRC_STATUS_CLEAR :: reserved0 [31:01] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_CRC_STATUS_CLEAR_reserved0_MASK 0xfffffffe
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_CRC_STATUS_CLEAR_reserved0_SHIFT 1
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: EDC_CRC_STATUS_CLEAR :: CLEAR [00:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_CRC_STATUS_CLEAR_CLEAR_MASK 0x00000001
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_CRC_STATUS_CLEAR_CLEAR_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_CRC_STATUS_CLEAR_CLEAR_DEFAULT 0x00000000
-
-/***************************************************************************
- *BL_SPARE_REG - Byte-Lane Spare register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_3_0 :: BL_SPARE_REG :: reserved_for_eco0 [31:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_BL_SPARE_REG_reserved_for_eco0_MASK 0xffffffff
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_BL_SPARE_REG_reserved_for_eco0_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_BL_SPARE_REG_reserved_for_eco0_DEFAULT 0x00000000
-
-#endif /* #ifndef BCHP_DDR34_PHY_BYTE_LANE_3_0_H__ */
-
-/* End of File */
diff --git a/include/linux/brcmstb/7145a0/bchp_ddr34_phy_byte_lane_3_1.h b/include/linux/brcmstb/7145a0/bchp_ddr34_phy_byte_lane_3_1.h
deleted file mode 100644
index 3d44956..0000000
--- a/include/linux/brcmstb/7145a0/bchp_ddr34_phy_byte_lane_3_1.h
+++ /dev/null
@@ -1,2101 +0,0 @@
-/***************************************************************************
- * Copyright (c) 1999-2014, Broadcom Corporation
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
- *
- * Module Description:
- * DO NOT EDIT THIS FILE DIRECTLY
- *
- * This module was generated magically with RDB from a source description
- * file. You must edit the source file for changes to be made to this file.
- *
- *
- * Date: Generated on Wed Sep 3 13:17:38 2014
- * Full Compile MD5 Checksum a8ee62ccf9dde43435c825f266da463d
- * (minus title and desc)
- * MD5 Checksum e373b364a1742e13a0f9eb15fd8aa94f
- *
- * Compiled with: RDB Utility combo_header.pl
- * RDB Parser 3.0
- * unknown unknown
- * Perl Interpreter 5.008005
- * Operating System linux
- *
- * Revision History:
- *
- * $brcm_Log: $
- *
- ***************************************************************************/
-
-#ifndef BCHP_DDR34_PHY_BYTE_LANE_3_1_H__
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_H__
-
-/***************************************************************************
- *DDR34_PHY_BYTE_LANE_3_1 - DDR34 Byte Lane #3 control registers
- ***************************************************************************/
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_WR_DQS_P 0x203c6a00 /* Write channel DQS-P VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_WR_DQS_N 0x203c6a04 /* Write channel DQS-N VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_WR_DQ0 0x203c6a08 /* Write channel DQ0 VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_WR_DQ1 0x203c6a0c /* Write channel DQ1 VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_WR_DQ2 0x203c6a10 /* Write channel DQ2 VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_WR_DQ3 0x203c6a14 /* Write channel DQ3 VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_WR_DQ4 0x203c6a18 /* Write channel DQ4 VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_WR_DQ5 0x203c6a1c /* Write channel DQ5 VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_WR_DQ6 0x203c6a20 /* Write channel DQ6 VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_WR_DQ7 0x203c6a24 /* Write channel DQ7 VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_WR_DM 0x203c6a28 /* Write channel DM VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_WR_EDC 0x203c6a2c /* Write channel EDC VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQSP 0x203c6a30 /* Read channel DQSP VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQSN 0x203c6a34 /* Read channel DQSP VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ0P 0x203c6a38 /* Read channel DQ0-P VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ0N 0x203c6a3c /* Read channel DQ0-N VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ1P 0x203c6a40 /* Read channel DQ1-P VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ1N 0x203c6a44 /* Read channel DQ1-N VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ2P 0x203c6a48 /* Read channel DQ2-P VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ2N 0x203c6a4c /* Read channel DQ2-N VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ3P 0x203c6a50 /* Read channel DQ3-P VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ3N 0x203c6a54 /* Read channel DQ3-N VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ4P 0x203c6a58 /* Read channel DQ4-P VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ4N 0x203c6a5c /* Read channel DQ4-N VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ5P 0x203c6a60 /* Read channel DQ5-P VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ5N 0x203c6a64 /* Read channel DQ5-N VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ6P 0x203c6a68 /* Read channel DQ6-P VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ6N 0x203c6a6c /* Read channel DQ6-N VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ7P 0x203c6a70 /* Read channel DQ7-P VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ7N 0x203c6a74 /* Read channel DQ7-N VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DMP 0x203c6a78 /* Read channel DM-P VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DMN 0x203c6a7c /* Read channel DM-N VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_EDCP 0x203c6a80 /* Read channel EDC-P VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_EDCN 0x203c6a84 /* Read channel EDC-N VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_EN_CS0 0x203c6a88 /* Read channel CS_N[0] read enable VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_EN_CS1 0x203c6a8c /* Read channel CS_N[1] read enable VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CLK_CONTROL 0x203c6a90 /* DDR interface signal Write Leveling CLK VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_LDE_CONTROL 0x203c6a94 /* DDR interface signal Write Leveling Capture Enable VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_RD_EN_DLY_CYC 0x203c6aa0 /* Read enable bit-clock cycle delay control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_WR_CHAN_DLY_CYC 0x203c6aa4 /* Write leveling bit-clock cycle delay control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_READ_CONTROL 0x203c6ab0 /* Read channel datapath control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_READ_FIFO_ADDR 0x203c6ab4 /* Read fifo addresss pointer register */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_READ_FIFO_DATA 0x203c6ab8 /* Read fifo data register */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_READ_FIFO_DM_DBI 0x203c6abc /* Read fifo dm/dbi register */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_READ_FIFO_STATUS 0x203c6ac0 /* Read fifo status register */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_READ_FIFO_CLEAR 0x203c6ac4 /* Read fifo status clear register */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_IDLE_PAD_CONTROL 0x203c6ac8 /* Idle mode SSTL pad control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_DRIVE_PAD_CTL 0x203c6acc /* SSTL pad drive characteristics control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_RD_EN_DRIVE_PAD_CTL 0x203c6ad0 /* SSTL read enable pad drive characteristics control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_STATIC_PAD_CTL 0x203c6ad4 /* pad rx and tx characteristics control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_WR_PREAMBLE_MODE 0x203c6ad8 /* Write cycle preamble control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_ODT_CONTROL 0x203c6ae0 /* Read channel ODT control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_EDC_DPD_CONTROL 0x203c6af0 /* GDDR5M EDC digital phase detector control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_EDC_DPD_STATUS 0x203c6af4 /* GDDR5M EDC digital phase detector status register */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_EDC_DPD_OUT_CONTROL 0x203c6af8 /* GDDR5M EDC digital phase detector output signal control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_EDC_DPD_OUT_STATUS 0x203c6afc /* GDDR5M EDC digital phase detector output signal status register */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_EDC_DPD_OUT_STATUS_CLEAR 0x203c6b00 /* GDDR5M EDC digital phase detector output signal status clear register */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_EDC_CRC_CONTROL 0x203c6b04 /* GDDR5M EDC signal path CRC control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_EDC_CRC_STATUS 0x203c6b08 /* GDDR5M EDC signal path CRC status register */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_EDC_CRC_COUNT 0x203c6b0c /* GDDR5M EDC signal path CRC counter register */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_EDC_CRC_STATUS_CLEAR 0x203c6b10 /* GDDR5M EDC signal path CRC counter register */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_BL_SPARE_REG 0x203c6b14 /* Byte-Lane Spare register */
-
-/***************************************************************************
- *VDL_CONTROL_WR_DQS_P - Write channel DQS-P VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_3_1 :: VDL_CONTROL_WR_DQS_P :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_WR_DQS_P_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_WR_DQS_P_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_WR_DQS_P_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_1 :: VDL_CONTROL_WR_DQS_P :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_WR_DQS_P_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_WR_DQS_P_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_3_1 :: VDL_CONTROL_WR_DQS_P :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_WR_DQS_P_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_WR_DQS_P_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_WR_DQS_P_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_1 :: VDL_CONTROL_WR_DQS_P :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_WR_DQS_P_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_WR_DQS_P_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_3_1 :: VDL_CONTROL_WR_DQS_P :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_WR_DQS_P_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_WR_DQS_P_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_WR_DQS_P_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_1 :: VDL_CONTROL_WR_DQS_P :: reserved2 [11:09] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_WR_DQS_P_reserved2_MASK 0x00000e00
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_WR_DQS_P_reserved2_SHIFT 9
-
-/* DDR34_PHY_BYTE_LANE_3_1 :: VDL_CONTROL_WR_DQS_P :: VDL_STEP [08:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_WR_DQS_P_VDL_STEP_MASK 0x000001ff
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_WR_DQS_P_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_WR_DQS_P_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_WR_DQS_N - Write channel DQS-N VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_3_1 :: VDL_CONTROL_WR_DQS_N :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_WR_DQS_N_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_WR_DQS_N_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_WR_DQS_N_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_1 :: VDL_CONTROL_WR_DQS_N :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_WR_DQS_N_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_WR_DQS_N_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_3_1 :: VDL_CONTROL_WR_DQS_N :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_WR_DQS_N_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_WR_DQS_N_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_WR_DQS_N_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_1 :: VDL_CONTROL_WR_DQS_N :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_WR_DQS_N_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_WR_DQS_N_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_3_1 :: VDL_CONTROL_WR_DQS_N :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_WR_DQS_N_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_WR_DQS_N_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_WR_DQS_N_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_1 :: VDL_CONTROL_WR_DQS_N :: reserved2 [11:09] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_WR_DQS_N_reserved2_MASK 0x00000e00
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_WR_DQS_N_reserved2_SHIFT 9
-
-/* DDR34_PHY_BYTE_LANE_3_1 :: VDL_CONTROL_WR_DQS_N :: VDL_STEP [08:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_WR_DQS_N_VDL_STEP_MASK 0x000001ff
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_WR_DQS_N_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_WR_DQS_N_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_WR_DQ0 - Write channel DQ0 VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_3_1 :: VDL_CONTROL_WR_DQ0 :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_WR_DQ0_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_WR_DQ0_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_WR_DQ0_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_1 :: VDL_CONTROL_WR_DQ0 :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_WR_DQ0_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_WR_DQ0_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_3_1 :: VDL_CONTROL_WR_DQ0 :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_WR_DQ0_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_WR_DQ0_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_WR_DQ0_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_1 :: VDL_CONTROL_WR_DQ0 :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_WR_DQ0_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_WR_DQ0_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_3_1 :: VDL_CONTROL_WR_DQ0 :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_WR_DQ0_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_WR_DQ0_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_WR_DQ0_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_1 :: VDL_CONTROL_WR_DQ0 :: reserved2 [11:09] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_WR_DQ0_reserved2_MASK 0x00000e00
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_WR_DQ0_reserved2_SHIFT 9
-
-/* DDR34_PHY_BYTE_LANE_3_1 :: VDL_CONTROL_WR_DQ0 :: VDL_STEP [08:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_WR_DQ0_VDL_STEP_MASK 0x000001ff
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_WR_DQ0_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_WR_DQ0_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_WR_DQ1 - Write channel DQ1 VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_3_1 :: VDL_CONTROL_WR_DQ1 :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_WR_DQ1_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_WR_DQ1_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_WR_DQ1_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_1 :: VDL_CONTROL_WR_DQ1 :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_WR_DQ1_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_WR_DQ1_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_3_1 :: VDL_CONTROL_WR_DQ1 :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_WR_DQ1_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_WR_DQ1_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_WR_DQ1_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_1 :: VDL_CONTROL_WR_DQ1 :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_WR_DQ1_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_WR_DQ1_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_3_1 :: VDL_CONTROL_WR_DQ1 :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_WR_DQ1_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_WR_DQ1_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_WR_DQ1_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_1 :: VDL_CONTROL_WR_DQ1 :: reserved2 [11:09] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_WR_DQ1_reserved2_MASK 0x00000e00
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_WR_DQ1_reserved2_SHIFT 9
-
-/* DDR34_PHY_BYTE_LANE_3_1 :: VDL_CONTROL_WR_DQ1 :: VDL_STEP [08:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_WR_DQ1_VDL_STEP_MASK 0x000001ff
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_WR_DQ1_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_WR_DQ1_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_WR_DQ2 - Write channel DQ2 VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_3_1 :: VDL_CONTROL_WR_DQ2 :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_WR_DQ2_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_WR_DQ2_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_WR_DQ2_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_1 :: VDL_CONTROL_WR_DQ2 :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_WR_DQ2_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_WR_DQ2_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_3_1 :: VDL_CONTROL_WR_DQ2 :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_WR_DQ2_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_WR_DQ2_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_WR_DQ2_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_1 :: VDL_CONTROL_WR_DQ2 :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_WR_DQ2_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_WR_DQ2_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_3_1 :: VDL_CONTROL_WR_DQ2 :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_WR_DQ2_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_WR_DQ2_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_WR_DQ2_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_1 :: VDL_CONTROL_WR_DQ2 :: reserved2 [11:09] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_WR_DQ2_reserved2_MASK 0x00000e00
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_WR_DQ2_reserved2_SHIFT 9
-
-/* DDR34_PHY_BYTE_LANE_3_1 :: VDL_CONTROL_WR_DQ2 :: VDL_STEP [08:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_WR_DQ2_VDL_STEP_MASK 0x000001ff
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_WR_DQ2_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_WR_DQ2_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_WR_DQ3 - Write channel DQ3 VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_3_1 :: VDL_CONTROL_WR_DQ3 :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_WR_DQ3_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_WR_DQ3_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_WR_DQ3_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_1 :: VDL_CONTROL_WR_DQ3 :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_WR_DQ3_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_WR_DQ3_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_3_1 :: VDL_CONTROL_WR_DQ3 :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_WR_DQ3_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_WR_DQ3_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_WR_DQ3_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_1 :: VDL_CONTROL_WR_DQ3 :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_WR_DQ3_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_WR_DQ3_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_3_1 :: VDL_CONTROL_WR_DQ3 :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_WR_DQ3_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_WR_DQ3_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_WR_DQ3_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_1 :: VDL_CONTROL_WR_DQ3 :: reserved2 [11:09] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_WR_DQ3_reserved2_MASK 0x00000e00
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_WR_DQ3_reserved2_SHIFT 9
-
-/* DDR34_PHY_BYTE_LANE_3_1 :: VDL_CONTROL_WR_DQ3 :: VDL_STEP [08:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_WR_DQ3_VDL_STEP_MASK 0x000001ff
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_WR_DQ3_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_WR_DQ3_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_WR_DQ4 - Write channel DQ4 VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_3_1 :: VDL_CONTROL_WR_DQ4 :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_WR_DQ4_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_WR_DQ4_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_WR_DQ4_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_1 :: VDL_CONTROL_WR_DQ4 :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_WR_DQ4_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_WR_DQ4_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_3_1 :: VDL_CONTROL_WR_DQ4 :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_WR_DQ4_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_WR_DQ4_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_WR_DQ4_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_1 :: VDL_CONTROL_WR_DQ4 :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_WR_DQ4_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_WR_DQ4_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_3_1 :: VDL_CONTROL_WR_DQ4 :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_WR_DQ4_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_WR_DQ4_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_WR_DQ4_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_1 :: VDL_CONTROL_WR_DQ4 :: reserved2 [11:09] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_WR_DQ4_reserved2_MASK 0x00000e00
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_WR_DQ4_reserved2_SHIFT 9
-
-/* DDR34_PHY_BYTE_LANE_3_1 :: VDL_CONTROL_WR_DQ4 :: VDL_STEP [08:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_WR_DQ4_VDL_STEP_MASK 0x000001ff
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_WR_DQ4_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_WR_DQ4_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_WR_DQ5 - Write channel DQ5 VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_3_1 :: VDL_CONTROL_WR_DQ5 :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_WR_DQ5_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_WR_DQ5_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_WR_DQ5_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_1 :: VDL_CONTROL_WR_DQ5 :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_WR_DQ5_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_WR_DQ5_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_3_1 :: VDL_CONTROL_WR_DQ5 :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_WR_DQ5_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_WR_DQ5_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_WR_DQ5_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_1 :: VDL_CONTROL_WR_DQ5 :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_WR_DQ5_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_WR_DQ5_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_3_1 :: VDL_CONTROL_WR_DQ5 :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_WR_DQ5_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_WR_DQ5_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_WR_DQ5_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_1 :: VDL_CONTROL_WR_DQ5 :: reserved2 [11:09] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_WR_DQ5_reserved2_MASK 0x00000e00
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_WR_DQ5_reserved2_SHIFT 9
-
-/* DDR34_PHY_BYTE_LANE_3_1 :: VDL_CONTROL_WR_DQ5 :: VDL_STEP [08:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_WR_DQ5_VDL_STEP_MASK 0x000001ff
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_WR_DQ5_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_WR_DQ5_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_WR_DQ6 - Write channel DQ6 VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_3_1 :: VDL_CONTROL_WR_DQ6 :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_WR_DQ6_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_WR_DQ6_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_WR_DQ6_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_1 :: VDL_CONTROL_WR_DQ6 :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_WR_DQ6_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_WR_DQ6_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_3_1 :: VDL_CONTROL_WR_DQ6 :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_WR_DQ6_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_WR_DQ6_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_WR_DQ6_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_1 :: VDL_CONTROL_WR_DQ6 :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_WR_DQ6_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_WR_DQ6_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_3_1 :: VDL_CONTROL_WR_DQ6 :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_WR_DQ6_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_WR_DQ6_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_WR_DQ6_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_1 :: VDL_CONTROL_WR_DQ6 :: reserved2 [11:09] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_WR_DQ6_reserved2_MASK 0x00000e00
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_WR_DQ6_reserved2_SHIFT 9
-
-/* DDR34_PHY_BYTE_LANE_3_1 :: VDL_CONTROL_WR_DQ6 :: VDL_STEP [08:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_WR_DQ6_VDL_STEP_MASK 0x000001ff
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_WR_DQ6_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_WR_DQ6_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_WR_DQ7 - Write channel DQ7 VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_3_1 :: VDL_CONTROL_WR_DQ7 :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_WR_DQ7_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_WR_DQ7_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_WR_DQ7_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_1 :: VDL_CONTROL_WR_DQ7 :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_WR_DQ7_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_WR_DQ7_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_3_1 :: VDL_CONTROL_WR_DQ7 :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_WR_DQ7_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_WR_DQ7_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_WR_DQ7_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_1 :: VDL_CONTROL_WR_DQ7 :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_WR_DQ7_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_WR_DQ7_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_3_1 :: VDL_CONTROL_WR_DQ7 :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_WR_DQ7_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_WR_DQ7_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_WR_DQ7_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_1 :: VDL_CONTROL_WR_DQ7 :: reserved2 [11:09] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_WR_DQ7_reserved2_MASK 0x00000e00
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_WR_DQ7_reserved2_SHIFT 9
-
-/* DDR34_PHY_BYTE_LANE_3_1 :: VDL_CONTROL_WR_DQ7 :: VDL_STEP [08:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_WR_DQ7_VDL_STEP_MASK 0x000001ff
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_WR_DQ7_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_WR_DQ7_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_WR_DM - Write channel DM VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_3_1 :: VDL_CONTROL_WR_DM :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_WR_DM_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_WR_DM_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_WR_DM_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_1 :: VDL_CONTROL_WR_DM :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_WR_DM_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_WR_DM_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_3_1 :: VDL_CONTROL_WR_DM :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_WR_DM_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_WR_DM_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_WR_DM_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_1 :: VDL_CONTROL_WR_DM :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_WR_DM_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_WR_DM_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_3_1 :: VDL_CONTROL_WR_DM :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_WR_DM_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_WR_DM_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_WR_DM_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_1 :: VDL_CONTROL_WR_DM :: reserved2 [11:09] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_WR_DM_reserved2_MASK 0x00000e00
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_WR_DM_reserved2_SHIFT 9
-
-/* DDR34_PHY_BYTE_LANE_3_1 :: VDL_CONTROL_WR_DM :: VDL_STEP [08:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_WR_DM_VDL_STEP_MASK 0x000001ff
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_WR_DM_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_WR_DM_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_WR_EDC - Write channel EDC VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_3_1 :: VDL_CONTROL_WR_EDC :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_WR_EDC_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_WR_EDC_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_WR_EDC_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_1 :: VDL_CONTROL_WR_EDC :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_WR_EDC_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_WR_EDC_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_3_1 :: VDL_CONTROL_WR_EDC :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_WR_EDC_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_WR_EDC_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_WR_EDC_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_1 :: VDL_CONTROL_WR_EDC :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_WR_EDC_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_WR_EDC_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_3_1 :: VDL_CONTROL_WR_EDC :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_WR_EDC_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_WR_EDC_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_WR_EDC_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_1 :: VDL_CONTROL_WR_EDC :: reserved2 [11:09] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_WR_EDC_reserved2_MASK 0x00000e00
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_WR_EDC_reserved2_SHIFT 9
-
-/* DDR34_PHY_BYTE_LANE_3_1 :: VDL_CONTROL_WR_EDC :: VDL_STEP [08:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_WR_EDC_VDL_STEP_MASK 0x000001ff
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_WR_EDC_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_WR_EDC_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_RD_DQSP - Read channel DQSP VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_3_1 :: VDL_CONTROL_RD_DQSP :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQSP_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQSP_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQSP_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_1 :: VDL_CONTROL_RD_DQSP :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQSP_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQSP_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_3_1 :: VDL_CONTROL_RD_DQSP :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQSP_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQSP_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQSP_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_1 :: VDL_CONTROL_RD_DQSP :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQSP_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQSP_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_3_1 :: VDL_CONTROL_RD_DQSP :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQSP_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQSP_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQSP_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_1 :: VDL_CONTROL_RD_DQSP :: reserved2 [11:08] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQSP_reserved2_MASK 0x00000f00
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQSP_reserved2_SHIFT 8
-
-/* DDR34_PHY_BYTE_LANE_3_1 :: VDL_CONTROL_RD_DQSP :: VDL_STEP [07:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQSP_VDL_STEP_MASK 0x000000ff
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQSP_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQSP_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_RD_DQSN - Read channel DQSP VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_3_1 :: VDL_CONTROL_RD_DQSN :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQSN_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQSN_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQSN_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_1 :: VDL_CONTROL_RD_DQSN :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQSN_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQSN_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_3_1 :: VDL_CONTROL_RD_DQSN :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQSN_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQSN_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQSN_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_1 :: VDL_CONTROL_RD_DQSN :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQSN_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQSN_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_3_1 :: VDL_CONTROL_RD_DQSN :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQSN_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQSN_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQSN_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_1 :: VDL_CONTROL_RD_DQSN :: reserved2 [11:08] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQSN_reserved2_MASK 0x00000f00
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQSN_reserved2_SHIFT 8
-
-/* DDR34_PHY_BYTE_LANE_3_1 :: VDL_CONTROL_RD_DQSN :: VDL_STEP [07:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQSN_VDL_STEP_MASK 0x000000ff
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQSN_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQSN_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_RD_DQ0P - Read channel DQ0-P VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_3_1 :: VDL_CONTROL_RD_DQ0P :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ0P_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ0P_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ0P_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_1 :: VDL_CONTROL_RD_DQ0P :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ0P_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ0P_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_3_1 :: VDL_CONTROL_RD_DQ0P :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ0P_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ0P_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ0P_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_1 :: VDL_CONTROL_RD_DQ0P :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ0P_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ0P_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_3_1 :: VDL_CONTROL_RD_DQ0P :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ0P_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ0P_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ0P_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_1 :: VDL_CONTROL_RD_DQ0P :: reserved2 [11:08] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ0P_reserved2_MASK 0x00000f00
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ0P_reserved2_SHIFT 8
-
-/* DDR34_PHY_BYTE_LANE_3_1 :: VDL_CONTROL_RD_DQ0P :: VDL_STEP [07:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ0P_VDL_STEP_MASK 0x000000ff
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ0P_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ0P_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_RD_DQ0N - Read channel DQ0-N VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_3_1 :: VDL_CONTROL_RD_DQ0N :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ0N_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ0N_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ0N_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_1 :: VDL_CONTROL_RD_DQ0N :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ0N_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ0N_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_3_1 :: VDL_CONTROL_RD_DQ0N :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ0N_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ0N_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ0N_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_1 :: VDL_CONTROL_RD_DQ0N :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ0N_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ0N_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_3_1 :: VDL_CONTROL_RD_DQ0N :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ0N_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ0N_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ0N_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_1 :: VDL_CONTROL_RD_DQ0N :: reserved2 [11:08] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ0N_reserved2_MASK 0x00000f00
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ0N_reserved2_SHIFT 8
-
-/* DDR34_PHY_BYTE_LANE_3_1 :: VDL_CONTROL_RD_DQ0N :: VDL_STEP [07:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ0N_VDL_STEP_MASK 0x000000ff
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ0N_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ0N_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_RD_DQ1P - Read channel DQ1-P VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_3_1 :: VDL_CONTROL_RD_DQ1P :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ1P_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ1P_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ1P_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_1 :: VDL_CONTROL_RD_DQ1P :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ1P_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ1P_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_3_1 :: VDL_CONTROL_RD_DQ1P :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ1P_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ1P_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ1P_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_1 :: VDL_CONTROL_RD_DQ1P :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ1P_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ1P_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_3_1 :: VDL_CONTROL_RD_DQ1P :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ1P_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ1P_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ1P_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_1 :: VDL_CONTROL_RD_DQ1P :: reserved2 [11:08] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ1P_reserved2_MASK 0x00000f00
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ1P_reserved2_SHIFT 8
-
-/* DDR34_PHY_BYTE_LANE_3_1 :: VDL_CONTROL_RD_DQ1P :: VDL_STEP [07:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ1P_VDL_STEP_MASK 0x000000ff
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ1P_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ1P_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_RD_DQ1N - Read channel DQ1-N VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_3_1 :: VDL_CONTROL_RD_DQ1N :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ1N_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ1N_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ1N_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_1 :: VDL_CONTROL_RD_DQ1N :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ1N_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ1N_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_3_1 :: VDL_CONTROL_RD_DQ1N :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ1N_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ1N_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ1N_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_1 :: VDL_CONTROL_RD_DQ1N :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ1N_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ1N_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_3_1 :: VDL_CONTROL_RD_DQ1N :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ1N_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ1N_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ1N_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_1 :: VDL_CONTROL_RD_DQ1N :: reserved2 [11:08] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ1N_reserved2_MASK 0x00000f00
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ1N_reserved2_SHIFT 8
-
-/* DDR34_PHY_BYTE_LANE_3_1 :: VDL_CONTROL_RD_DQ1N :: VDL_STEP [07:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ1N_VDL_STEP_MASK 0x000000ff
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ1N_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ1N_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_RD_DQ2P - Read channel DQ2-P VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_3_1 :: VDL_CONTROL_RD_DQ2P :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ2P_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ2P_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ2P_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_1 :: VDL_CONTROL_RD_DQ2P :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ2P_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ2P_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_3_1 :: VDL_CONTROL_RD_DQ2P :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ2P_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ2P_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ2P_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_1 :: VDL_CONTROL_RD_DQ2P :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ2P_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ2P_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_3_1 :: VDL_CONTROL_RD_DQ2P :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ2P_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ2P_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ2P_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_1 :: VDL_CONTROL_RD_DQ2P :: reserved2 [11:08] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ2P_reserved2_MASK 0x00000f00
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ2P_reserved2_SHIFT 8
-
-/* DDR34_PHY_BYTE_LANE_3_1 :: VDL_CONTROL_RD_DQ2P :: VDL_STEP [07:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ2P_VDL_STEP_MASK 0x000000ff
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ2P_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ2P_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_RD_DQ2N - Read channel DQ2-N VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_3_1 :: VDL_CONTROL_RD_DQ2N :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ2N_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ2N_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ2N_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_1 :: VDL_CONTROL_RD_DQ2N :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ2N_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ2N_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_3_1 :: VDL_CONTROL_RD_DQ2N :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ2N_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ2N_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ2N_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_1 :: VDL_CONTROL_RD_DQ2N :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ2N_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ2N_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_3_1 :: VDL_CONTROL_RD_DQ2N :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ2N_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ2N_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ2N_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_1 :: VDL_CONTROL_RD_DQ2N :: reserved2 [11:08] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ2N_reserved2_MASK 0x00000f00
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ2N_reserved2_SHIFT 8
-
-/* DDR34_PHY_BYTE_LANE_3_1 :: VDL_CONTROL_RD_DQ2N :: VDL_STEP [07:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ2N_VDL_STEP_MASK 0x000000ff
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ2N_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ2N_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_RD_DQ3P - Read channel DQ3-P VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_3_1 :: VDL_CONTROL_RD_DQ3P :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ3P_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ3P_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ3P_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_1 :: VDL_CONTROL_RD_DQ3P :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ3P_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ3P_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_3_1 :: VDL_CONTROL_RD_DQ3P :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ3P_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ3P_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ3P_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_1 :: VDL_CONTROL_RD_DQ3P :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ3P_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ3P_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_3_1 :: VDL_CONTROL_RD_DQ3P :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ3P_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ3P_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ3P_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_1 :: VDL_CONTROL_RD_DQ3P :: reserved2 [11:08] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ3P_reserved2_MASK 0x00000f00
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ3P_reserved2_SHIFT 8
-
-/* DDR34_PHY_BYTE_LANE_3_1 :: VDL_CONTROL_RD_DQ3P :: VDL_STEP [07:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ3P_VDL_STEP_MASK 0x000000ff
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ3P_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ3P_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_RD_DQ3N - Read channel DQ3-N VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_3_1 :: VDL_CONTROL_RD_DQ3N :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ3N_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ3N_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ3N_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_1 :: VDL_CONTROL_RD_DQ3N :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ3N_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ3N_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_3_1 :: VDL_CONTROL_RD_DQ3N :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ3N_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ3N_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ3N_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_1 :: VDL_CONTROL_RD_DQ3N :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ3N_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ3N_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_3_1 :: VDL_CONTROL_RD_DQ3N :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ3N_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ3N_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ3N_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_1 :: VDL_CONTROL_RD_DQ3N :: reserved2 [11:08] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ3N_reserved2_MASK 0x00000f00
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ3N_reserved2_SHIFT 8
-
-/* DDR34_PHY_BYTE_LANE_3_1 :: VDL_CONTROL_RD_DQ3N :: VDL_STEP [07:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ3N_VDL_STEP_MASK 0x000000ff
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ3N_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ3N_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_RD_DQ4P - Read channel DQ4-P VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_3_1 :: VDL_CONTROL_RD_DQ4P :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ4P_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ4P_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ4P_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_1 :: VDL_CONTROL_RD_DQ4P :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ4P_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ4P_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_3_1 :: VDL_CONTROL_RD_DQ4P :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ4P_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ4P_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ4P_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_1 :: VDL_CONTROL_RD_DQ4P :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ4P_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ4P_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_3_1 :: VDL_CONTROL_RD_DQ4P :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ4P_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ4P_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ4P_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_1 :: VDL_CONTROL_RD_DQ4P :: reserved2 [11:08] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ4P_reserved2_MASK 0x00000f00
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ4P_reserved2_SHIFT 8
-
-/* DDR34_PHY_BYTE_LANE_3_1 :: VDL_CONTROL_RD_DQ4P :: VDL_STEP [07:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ4P_VDL_STEP_MASK 0x000000ff
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ4P_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ4P_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_RD_DQ4N - Read channel DQ4-N VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_3_1 :: VDL_CONTROL_RD_DQ4N :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ4N_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ4N_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ4N_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_1 :: VDL_CONTROL_RD_DQ4N :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ4N_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ4N_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_3_1 :: VDL_CONTROL_RD_DQ4N :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ4N_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ4N_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ4N_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_1 :: VDL_CONTROL_RD_DQ4N :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ4N_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ4N_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_3_1 :: VDL_CONTROL_RD_DQ4N :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ4N_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ4N_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ4N_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_1 :: VDL_CONTROL_RD_DQ4N :: reserved2 [11:08] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ4N_reserved2_MASK 0x00000f00
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ4N_reserved2_SHIFT 8
-
-/* DDR34_PHY_BYTE_LANE_3_1 :: VDL_CONTROL_RD_DQ4N :: VDL_STEP [07:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ4N_VDL_STEP_MASK 0x000000ff
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ4N_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ4N_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_RD_DQ5P - Read channel DQ5-P VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_3_1 :: VDL_CONTROL_RD_DQ5P :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ5P_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ5P_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ5P_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_1 :: VDL_CONTROL_RD_DQ5P :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ5P_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ5P_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_3_1 :: VDL_CONTROL_RD_DQ5P :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ5P_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ5P_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ5P_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_1 :: VDL_CONTROL_RD_DQ5P :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ5P_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ5P_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_3_1 :: VDL_CONTROL_RD_DQ5P :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ5P_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ5P_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ5P_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_1 :: VDL_CONTROL_RD_DQ5P :: reserved2 [11:08] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ5P_reserved2_MASK 0x00000f00
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ5P_reserved2_SHIFT 8
-
-/* DDR34_PHY_BYTE_LANE_3_1 :: VDL_CONTROL_RD_DQ5P :: VDL_STEP [07:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ5P_VDL_STEP_MASK 0x000000ff
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ5P_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ5P_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_RD_DQ5N - Read channel DQ5-N VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_3_1 :: VDL_CONTROL_RD_DQ5N :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ5N_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ5N_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ5N_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_1 :: VDL_CONTROL_RD_DQ5N :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ5N_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ5N_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_3_1 :: VDL_CONTROL_RD_DQ5N :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ5N_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ5N_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ5N_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_1 :: VDL_CONTROL_RD_DQ5N :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ5N_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ5N_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_3_1 :: VDL_CONTROL_RD_DQ5N :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ5N_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ5N_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ5N_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_1 :: VDL_CONTROL_RD_DQ5N :: reserved2 [11:08] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ5N_reserved2_MASK 0x00000f00
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ5N_reserved2_SHIFT 8
-
-/* DDR34_PHY_BYTE_LANE_3_1 :: VDL_CONTROL_RD_DQ5N :: VDL_STEP [07:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ5N_VDL_STEP_MASK 0x000000ff
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ5N_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ5N_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_RD_DQ6P - Read channel DQ6-P VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_3_1 :: VDL_CONTROL_RD_DQ6P :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ6P_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ6P_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ6P_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_1 :: VDL_CONTROL_RD_DQ6P :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ6P_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ6P_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_3_1 :: VDL_CONTROL_RD_DQ6P :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ6P_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ6P_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ6P_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_1 :: VDL_CONTROL_RD_DQ6P :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ6P_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ6P_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_3_1 :: VDL_CONTROL_RD_DQ6P :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ6P_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ6P_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ6P_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_1 :: VDL_CONTROL_RD_DQ6P :: reserved2 [11:08] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ6P_reserved2_MASK 0x00000f00
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ6P_reserved2_SHIFT 8
-
-/* DDR34_PHY_BYTE_LANE_3_1 :: VDL_CONTROL_RD_DQ6P :: VDL_STEP [07:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ6P_VDL_STEP_MASK 0x000000ff
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ6P_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ6P_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_RD_DQ6N - Read channel DQ6-N VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_3_1 :: VDL_CONTROL_RD_DQ6N :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ6N_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ6N_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ6N_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_1 :: VDL_CONTROL_RD_DQ6N :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ6N_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ6N_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_3_1 :: VDL_CONTROL_RD_DQ6N :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ6N_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ6N_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ6N_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_1 :: VDL_CONTROL_RD_DQ6N :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ6N_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ6N_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_3_1 :: VDL_CONTROL_RD_DQ6N :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ6N_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ6N_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ6N_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_1 :: VDL_CONTROL_RD_DQ6N :: reserved2 [11:08] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ6N_reserved2_MASK 0x00000f00
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ6N_reserved2_SHIFT 8
-
-/* DDR34_PHY_BYTE_LANE_3_1 :: VDL_CONTROL_RD_DQ6N :: VDL_STEP [07:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ6N_VDL_STEP_MASK 0x000000ff
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ6N_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ6N_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_RD_DQ7P - Read channel DQ7-P VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_3_1 :: VDL_CONTROL_RD_DQ7P :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ7P_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ7P_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ7P_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_1 :: VDL_CONTROL_RD_DQ7P :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ7P_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ7P_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_3_1 :: VDL_CONTROL_RD_DQ7P :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ7P_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ7P_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ7P_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_1 :: VDL_CONTROL_RD_DQ7P :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ7P_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ7P_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_3_1 :: VDL_CONTROL_RD_DQ7P :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ7P_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ7P_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ7P_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_1 :: VDL_CONTROL_RD_DQ7P :: reserved2 [11:08] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ7P_reserved2_MASK 0x00000f00
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ7P_reserved2_SHIFT 8
-
-/* DDR34_PHY_BYTE_LANE_3_1 :: VDL_CONTROL_RD_DQ7P :: VDL_STEP [07:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ7P_VDL_STEP_MASK 0x000000ff
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ7P_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ7P_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_RD_DQ7N - Read channel DQ7-N VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_3_1 :: VDL_CONTROL_RD_DQ7N :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ7N_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ7N_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ7N_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_1 :: VDL_CONTROL_RD_DQ7N :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ7N_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ7N_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_3_1 :: VDL_CONTROL_RD_DQ7N :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ7N_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ7N_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ7N_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_1 :: VDL_CONTROL_RD_DQ7N :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ7N_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ7N_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_3_1 :: VDL_CONTROL_RD_DQ7N :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ7N_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ7N_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ7N_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_1 :: VDL_CONTROL_RD_DQ7N :: reserved2 [11:08] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ7N_reserved2_MASK 0x00000f00
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ7N_reserved2_SHIFT 8
-
-/* DDR34_PHY_BYTE_LANE_3_1 :: VDL_CONTROL_RD_DQ7N :: VDL_STEP [07:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ7N_VDL_STEP_MASK 0x000000ff
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ7N_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ7N_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_RD_DMP - Read channel DM-P VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_3_1 :: VDL_CONTROL_RD_DMP :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DMP_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DMP_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DMP_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_1 :: VDL_CONTROL_RD_DMP :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DMP_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DMP_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_3_1 :: VDL_CONTROL_RD_DMP :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DMP_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DMP_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DMP_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_1 :: VDL_CONTROL_RD_DMP :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DMP_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DMP_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_3_1 :: VDL_CONTROL_RD_DMP :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DMP_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DMP_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DMP_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_1 :: VDL_CONTROL_RD_DMP :: reserved2 [11:08] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DMP_reserved2_MASK 0x00000f00
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DMP_reserved2_SHIFT 8
-
-/* DDR34_PHY_BYTE_LANE_3_1 :: VDL_CONTROL_RD_DMP :: VDL_STEP [07:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DMP_VDL_STEP_MASK 0x000000ff
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DMP_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DMP_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_RD_DMN - Read channel DM-N VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_3_1 :: VDL_CONTROL_RD_DMN :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DMN_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DMN_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DMN_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_1 :: VDL_CONTROL_RD_DMN :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DMN_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DMN_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_3_1 :: VDL_CONTROL_RD_DMN :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DMN_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DMN_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DMN_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_1 :: VDL_CONTROL_RD_DMN :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DMN_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DMN_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_3_1 :: VDL_CONTROL_RD_DMN :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DMN_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DMN_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DMN_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_1 :: VDL_CONTROL_RD_DMN :: reserved2 [11:08] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DMN_reserved2_MASK 0x00000f00
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DMN_reserved2_SHIFT 8
-
-/* DDR34_PHY_BYTE_LANE_3_1 :: VDL_CONTROL_RD_DMN :: VDL_STEP [07:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DMN_VDL_STEP_MASK 0x000000ff
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DMN_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DMN_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_RD_EDCP - Read channel EDC-P VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_3_1 :: VDL_CONTROL_RD_EDCP :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_EDCP_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_EDCP_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_EDCP_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_1 :: VDL_CONTROL_RD_EDCP :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_EDCP_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_EDCP_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_3_1 :: VDL_CONTROL_RD_EDCP :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_EDCP_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_EDCP_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_EDCP_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_1 :: VDL_CONTROL_RD_EDCP :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_EDCP_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_EDCP_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_3_1 :: VDL_CONTROL_RD_EDCP :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_EDCP_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_EDCP_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_EDCP_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_1 :: VDL_CONTROL_RD_EDCP :: reserved2 [11:08] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_EDCP_reserved2_MASK 0x00000f00
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_EDCP_reserved2_SHIFT 8
-
-/* DDR34_PHY_BYTE_LANE_3_1 :: VDL_CONTROL_RD_EDCP :: VDL_STEP [07:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_EDCP_VDL_STEP_MASK 0x000000ff
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_EDCP_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_EDCP_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_RD_EDCN - Read channel EDC-N VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_3_1 :: VDL_CONTROL_RD_EDCN :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_EDCN_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_EDCN_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_EDCN_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_1 :: VDL_CONTROL_RD_EDCN :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_EDCN_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_EDCN_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_3_1 :: VDL_CONTROL_RD_EDCN :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_EDCN_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_EDCN_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_EDCN_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_1 :: VDL_CONTROL_RD_EDCN :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_EDCN_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_EDCN_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_3_1 :: VDL_CONTROL_RD_EDCN :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_EDCN_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_EDCN_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_EDCN_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_1 :: VDL_CONTROL_RD_EDCN :: reserved2 [11:08] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_EDCN_reserved2_MASK 0x00000f00
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_EDCN_reserved2_SHIFT 8
-
-/* DDR34_PHY_BYTE_LANE_3_1 :: VDL_CONTROL_RD_EDCN :: VDL_STEP [07:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_EDCN_VDL_STEP_MASK 0x000000ff
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_EDCN_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_EDCN_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_RD_EN_CS0 - Read channel CS_N[0] read enable VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_3_1 :: VDL_CONTROL_RD_EN_CS0 :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_EN_CS0_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_EN_CS0_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_EN_CS0_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_1 :: VDL_CONTROL_RD_EN_CS0 :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_EN_CS0_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_EN_CS0_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_3_1 :: VDL_CONTROL_RD_EN_CS0 :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_EN_CS0_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_EN_CS0_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_EN_CS0_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_1 :: VDL_CONTROL_RD_EN_CS0 :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_EN_CS0_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_EN_CS0_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_3_1 :: VDL_CONTROL_RD_EN_CS0 :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_EN_CS0_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_EN_CS0_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_EN_CS0_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_1 :: VDL_CONTROL_RD_EN_CS0 :: reserved2 [11:08] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_EN_CS0_reserved2_MASK 0x00000f00
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_EN_CS0_reserved2_SHIFT 8
-
-/* DDR34_PHY_BYTE_LANE_3_1 :: VDL_CONTROL_RD_EN_CS0 :: VDL_STEP [07:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_EN_CS0_VDL_STEP_MASK 0x000000ff
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_EN_CS0_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_EN_CS0_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_RD_EN_CS1 - Read channel CS_N[1] read enable VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_3_1 :: VDL_CONTROL_RD_EN_CS1 :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_EN_CS1_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_EN_CS1_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_EN_CS1_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_1 :: VDL_CONTROL_RD_EN_CS1 :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_EN_CS1_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_EN_CS1_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_3_1 :: VDL_CONTROL_RD_EN_CS1 :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_EN_CS1_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_EN_CS1_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_EN_CS1_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_1 :: VDL_CONTROL_RD_EN_CS1 :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_EN_CS1_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_EN_CS1_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_3_1 :: VDL_CONTROL_RD_EN_CS1 :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_EN_CS1_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_EN_CS1_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_EN_CS1_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_1 :: VDL_CONTROL_RD_EN_CS1 :: reserved2 [11:08] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_EN_CS1_reserved2_MASK 0x00000f00
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_EN_CS1_reserved2_SHIFT 8
-
-/* DDR34_PHY_BYTE_LANE_3_1 :: VDL_CONTROL_RD_EN_CS1 :: VDL_STEP [07:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_EN_CS1_VDL_STEP_MASK 0x000000ff
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_EN_CS1_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_EN_CS1_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CLK_CONTROL - DDR interface signal Write Leveling CLK VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_3_1 :: VDL_CLK_CONTROL :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CLK_CONTROL_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CLK_CONTROL_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CLK_CONTROL_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_1 :: VDL_CLK_CONTROL :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CLK_CONTROL_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CLK_CONTROL_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_3_1 :: VDL_CLK_CONTROL :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CLK_CONTROL_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CLK_CONTROL_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CLK_CONTROL_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_1 :: VDL_CLK_CONTROL :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CLK_CONTROL_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CLK_CONTROL_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_3_1 :: VDL_CLK_CONTROL :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CLK_CONTROL_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CLK_CONTROL_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CLK_CONTROL_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_1 :: VDL_CLK_CONTROL :: reserved2 [11:09] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CLK_CONTROL_reserved2_MASK 0x00000e00
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CLK_CONTROL_reserved2_SHIFT 9
-
-/* DDR34_PHY_BYTE_LANE_3_1 :: VDL_CLK_CONTROL :: VDL_STEP [08:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CLK_CONTROL_VDL_STEP_MASK 0x000001ff
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CLK_CONTROL_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CLK_CONTROL_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_LDE_CONTROL - DDR interface signal Write Leveling Capture Enable VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_3_1 :: VDL_LDE_CONTROL :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_LDE_CONTROL_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_LDE_CONTROL_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_LDE_CONTROL_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_1 :: VDL_LDE_CONTROL :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_LDE_CONTROL_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_LDE_CONTROL_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_3_1 :: VDL_LDE_CONTROL :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_LDE_CONTROL_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_LDE_CONTROL_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_LDE_CONTROL_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_1 :: VDL_LDE_CONTROL :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_LDE_CONTROL_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_LDE_CONTROL_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_3_1 :: VDL_LDE_CONTROL :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_LDE_CONTROL_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_LDE_CONTROL_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_LDE_CONTROL_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_1 :: VDL_LDE_CONTROL :: reserved2 [11:09] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_LDE_CONTROL_reserved2_MASK 0x00000e00
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_LDE_CONTROL_reserved2_SHIFT 9
-
-/* DDR34_PHY_BYTE_LANE_3_1 :: VDL_LDE_CONTROL :: VDL_STEP [08:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_LDE_CONTROL_VDL_STEP_MASK 0x000001ff
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_LDE_CONTROL_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_LDE_CONTROL_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *RD_EN_DLY_CYC - Read enable bit-clock cycle delay control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_3_1 :: RD_EN_DLY_CYC :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_RD_EN_DLY_CYC_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_RD_EN_DLY_CYC_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_RD_EN_DLY_CYC_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_1 :: RD_EN_DLY_CYC :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_RD_EN_DLY_CYC_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_RD_EN_DLY_CYC_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_3_1 :: RD_EN_DLY_CYC :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_RD_EN_DLY_CYC_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_RD_EN_DLY_CYC_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_RD_EN_DLY_CYC_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_1 :: RD_EN_DLY_CYC :: reserved1 [15:08] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_RD_EN_DLY_CYC_reserved1_MASK 0x0000ff00
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_RD_EN_DLY_CYC_reserved1_SHIFT 8
-
-/* DDR34_PHY_BYTE_LANE_3_1 :: RD_EN_DLY_CYC :: CS1_CYCLES [07:04] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_RD_EN_DLY_CYC_CS1_CYCLES_MASK 0x000000f0
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_RD_EN_DLY_CYC_CS1_CYCLES_SHIFT 4
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_RD_EN_DLY_CYC_CS1_CYCLES_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_1 :: RD_EN_DLY_CYC :: CS0_CYCLES [03:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_RD_EN_DLY_CYC_CS0_CYCLES_MASK 0x0000000f
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_RD_EN_DLY_CYC_CS0_CYCLES_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_RD_EN_DLY_CYC_CS0_CYCLES_DEFAULT 0x00000000
-
-/***************************************************************************
- *WR_CHAN_DLY_CYC - Write leveling bit-clock cycle delay control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_3_1 :: WR_CHAN_DLY_CYC :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_WR_CHAN_DLY_CYC_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_WR_CHAN_DLY_CYC_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_WR_CHAN_DLY_CYC_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_1 :: WR_CHAN_DLY_CYC :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_WR_CHAN_DLY_CYC_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_WR_CHAN_DLY_CYC_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_3_1 :: WR_CHAN_DLY_CYC :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_WR_CHAN_DLY_CYC_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_WR_CHAN_DLY_CYC_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_WR_CHAN_DLY_CYC_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_1 :: WR_CHAN_DLY_CYC :: reserved1 [15:03] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_WR_CHAN_DLY_CYC_reserved1_MASK 0x0000fff8
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_WR_CHAN_DLY_CYC_reserved1_SHIFT 3
-
-/* DDR34_PHY_BYTE_LANE_3_1 :: WR_CHAN_DLY_CYC :: CYCLES [02:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_WR_CHAN_DLY_CYC_CYCLES_MASK 0x00000007
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_WR_CHAN_DLY_CYC_CYCLES_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_WR_CHAN_DLY_CYC_CYCLES_DEFAULT 0x00000000
-
-/***************************************************************************
- *READ_CONTROL - Read channel datapath control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_3_1 :: READ_CONTROL :: reserved0 [31:05] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_READ_CONTROL_reserved0_MASK 0xffffffe0
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_READ_CONTROL_reserved0_SHIFT 5
-
-/* DDR34_PHY_BYTE_LANE_3_1 :: READ_CONTROL :: MODE [04:04] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_READ_CONTROL_MODE_MASK 0x00000010
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_READ_CONTROL_MODE_SHIFT 4
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_READ_CONTROL_MODE_DEFAULT 0x00000001
-
-/* DDR34_PHY_BYTE_LANE_3_1 :: READ_CONTROL :: reserved1 [03:03] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_READ_CONTROL_reserved1_MASK 0x00000008
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_READ_CONTROL_reserved1_SHIFT 3
-
-/* DDR34_PHY_BYTE_LANE_3_1 :: READ_CONTROL :: RD_DATA_DLY [02:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_READ_CONTROL_RD_DATA_DLY_MASK 0x00000007
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_READ_CONTROL_RD_DATA_DLY_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_READ_CONTROL_RD_DATA_DLY_DEFAULT 0x00000007
-
-/***************************************************************************
- *READ_FIFO_ADDR - Read fifo addresss pointer register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_3_1 :: READ_FIFO_ADDR :: reserved0 [31:03] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_READ_FIFO_ADDR_reserved0_MASK 0xfffffff8
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_READ_FIFO_ADDR_reserved0_SHIFT 3
-
-/* DDR34_PHY_BYTE_LANE_3_1 :: READ_FIFO_ADDR :: ADDR [02:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_READ_FIFO_ADDR_ADDR_MASK 0x00000007
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_READ_FIFO_ADDR_ADDR_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_READ_FIFO_ADDR_ADDR_DEFAULT 0x00000000
-
-/***************************************************************************
- *READ_FIFO_DATA - Read fifo data register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_3_1 :: READ_FIFO_DATA :: DATA [31:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_READ_FIFO_DATA_DATA_MASK 0xffffffff
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_READ_FIFO_DATA_DATA_SHIFT 0
-
-/***************************************************************************
- *READ_FIFO_DM_DBI - Read fifo dm/dbi register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_3_1 :: READ_FIFO_DM_DBI :: reserved0 [31:04] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_READ_FIFO_DM_DBI_reserved0_MASK 0xfffffff0
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_READ_FIFO_DM_DBI_reserved0_SHIFT 4
-
-/* DDR34_PHY_BYTE_LANE_3_1 :: READ_FIFO_DM_DBI :: DM_DBI [03:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_READ_FIFO_DM_DBI_DM_DBI_MASK 0x0000000f
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_READ_FIFO_DM_DBI_DM_DBI_SHIFT 0
-
-/***************************************************************************
- *READ_FIFO_STATUS - Read fifo status register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_3_1 :: READ_FIFO_STATUS :: reserved0 [31:02] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_READ_FIFO_STATUS_reserved0_MASK 0xfffffffc
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_READ_FIFO_STATUS_reserved0_SHIFT 2
-
-/* DDR34_PHY_BYTE_LANE_3_1 :: READ_FIFO_STATUS :: OVERFLOW [01:01] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_READ_FIFO_STATUS_OVERFLOW_MASK 0x00000002
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_READ_FIFO_STATUS_OVERFLOW_SHIFT 1
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_READ_FIFO_STATUS_OVERFLOW_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_1 :: READ_FIFO_STATUS :: UNDERFLOW [00:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_READ_FIFO_STATUS_UNDERFLOW_MASK 0x00000001
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_READ_FIFO_STATUS_UNDERFLOW_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_READ_FIFO_STATUS_UNDERFLOW_DEFAULT 0x00000000
-
-/***************************************************************************
- *READ_FIFO_CLEAR - Read fifo status clear register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_3_1 :: READ_FIFO_CLEAR :: reserved0 [31:01] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_READ_FIFO_CLEAR_reserved0_MASK 0xfffffffe
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_READ_FIFO_CLEAR_reserved0_SHIFT 1
-
-/* DDR34_PHY_BYTE_LANE_3_1 :: READ_FIFO_CLEAR :: CLEAR [00:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_READ_FIFO_CLEAR_CLEAR_MASK 0x00000001
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_READ_FIFO_CLEAR_CLEAR_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_READ_FIFO_CLEAR_CLEAR_DEFAULT 0x00000000
-
-/***************************************************************************
- *IDLE_PAD_CONTROL - Idle mode SSTL pad control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_3_1 :: IDLE_PAD_CONTROL :: IDLE [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_IDLE_PAD_CONTROL_IDLE_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_IDLE_PAD_CONTROL_IDLE_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_IDLE_PAD_CONTROL_IDLE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_1 :: IDLE_PAD_CONTROL :: reserved0 [30:20] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_IDLE_PAD_CONTROL_reserved0_MASK 0x7ff00000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_IDLE_PAD_CONTROL_reserved0_SHIFT 20
-
-/* DDR34_PHY_BYTE_LANE_3_1 :: IDLE_PAD_CONTROL :: AUTO_DQ_RXENB_MODE [19:18] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_IDLE_PAD_CONTROL_AUTO_DQ_RXENB_MODE_MASK 0x000c0000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_IDLE_PAD_CONTROL_AUTO_DQ_RXENB_MODE_SHIFT 18
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_IDLE_PAD_CONTROL_AUTO_DQ_RXENB_MODE_DEFAULT 0x00000001
-
-/* DDR34_PHY_BYTE_LANE_3_1 :: IDLE_PAD_CONTROL :: AUTO_DQ_IDDQ_MODE [17:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_IDLE_PAD_CONTROL_AUTO_DQ_IDDQ_MODE_MASK 0x00030000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_IDLE_PAD_CONTROL_AUTO_DQ_IDDQ_MODE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_IDLE_PAD_CONTROL_AUTO_DQ_IDDQ_MODE_DEFAULT 0x00000001
-
-/* DDR34_PHY_BYTE_LANE_3_1 :: IDLE_PAD_CONTROL :: reserved_for_padding1 [15:15] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_IDLE_PAD_CONTROL_reserved_for_padding1_MASK 0x00008000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_IDLE_PAD_CONTROL_reserved_for_padding1_SHIFT 15
-
-/* DDR34_PHY_BYTE_LANE_3_1 :: IDLE_PAD_CONTROL :: IO_IDLE_ENABLE [14:04] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_IDLE_PAD_CONTROL_IO_IDLE_ENABLE_MASK 0x00007ff0
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_IDLE_PAD_CONTROL_IO_IDLE_ENABLE_SHIFT 4
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_IDLE_PAD_CONTROL_IO_IDLE_ENABLE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_1 :: IDLE_PAD_CONTROL :: RXENB [03:03] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_IDLE_PAD_CONTROL_RXENB_MASK 0x00000008
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_IDLE_PAD_CONTROL_RXENB_SHIFT 3
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_IDLE_PAD_CONTROL_RXENB_DEFAULT 0x00000001
-
-/* DDR34_PHY_BYTE_LANE_3_1 :: IDLE_PAD_CONTROL :: IDDQ [02:02] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_IDLE_PAD_CONTROL_IDDQ_MASK 0x00000004
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_IDLE_PAD_CONTROL_IDDQ_SHIFT 2
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_IDLE_PAD_CONTROL_IDDQ_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_1 :: IDLE_PAD_CONTROL :: DOUT_N [01:01] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_IDLE_PAD_CONTROL_DOUT_N_MASK 0x00000002
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_IDLE_PAD_CONTROL_DOUT_N_SHIFT 1
-
-/* DDR34_PHY_BYTE_LANE_3_1 :: IDLE_PAD_CONTROL :: DOUT_P [00:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_IDLE_PAD_CONTROL_DOUT_P_MASK 0x00000001
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_IDLE_PAD_CONTROL_DOUT_P_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_IDLE_PAD_CONTROL_DOUT_P_DEFAULT 0x00000000
-
-/***************************************************************************
- *DRIVE_PAD_CTL - SSTL pad drive characteristics control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_3_1 :: DRIVE_PAD_CTL :: reserved0 [31:30] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_DRIVE_PAD_CTL_reserved0_MASK 0xc0000000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_DRIVE_PAD_CTL_reserved0_SHIFT 30
-
-/* DDR34_PHY_BYTE_LANE_3_1 :: DRIVE_PAD_CTL :: BL_PD_IDLE_STRENGTH [29:25] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_DRIVE_PAD_CTL_BL_PD_IDLE_STRENGTH_MASK 0x3e000000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_DRIVE_PAD_CTL_BL_PD_IDLE_STRENGTH_SHIFT 25
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_DRIVE_PAD_CTL_BL_PD_IDLE_STRENGTH_DEFAULT 0x0000001f
-
-/* DDR34_PHY_BYTE_LANE_3_1 :: DRIVE_PAD_CTL :: BL_ND_IDLE_STRENGTH [24:20] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_DRIVE_PAD_CTL_BL_ND_IDLE_STRENGTH_MASK 0x01f00000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_DRIVE_PAD_CTL_BL_ND_IDLE_STRENGTH_SHIFT 20
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_DRIVE_PAD_CTL_BL_ND_IDLE_STRENGTH_DEFAULT 0x0000001f
-
-/* DDR34_PHY_BYTE_LANE_3_1 :: DRIVE_PAD_CTL :: BL_PD_TERM_STRENGTH [19:15] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_DRIVE_PAD_CTL_BL_PD_TERM_STRENGTH_MASK 0x000f8000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_DRIVE_PAD_CTL_BL_PD_TERM_STRENGTH_SHIFT 15
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_DRIVE_PAD_CTL_BL_PD_TERM_STRENGTH_DEFAULT 0x00000008
-
-/* DDR34_PHY_BYTE_LANE_3_1 :: DRIVE_PAD_CTL :: BL_ND_TERM_STRENGTH [14:10] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_DRIVE_PAD_CTL_BL_ND_TERM_STRENGTH_MASK 0x00007c00
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_DRIVE_PAD_CTL_BL_ND_TERM_STRENGTH_SHIFT 10
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_DRIVE_PAD_CTL_BL_ND_TERM_STRENGTH_DEFAULT 0x00000008
-
-/* DDR34_PHY_BYTE_LANE_3_1 :: DRIVE_PAD_CTL :: BL_PD_STRENGTH [09:05] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_DRIVE_PAD_CTL_BL_PD_STRENGTH_MASK 0x000003e0
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_DRIVE_PAD_CTL_BL_PD_STRENGTH_SHIFT 5
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_DRIVE_PAD_CTL_BL_PD_STRENGTH_DEFAULT 0x0000001f
-
-/* DDR34_PHY_BYTE_LANE_3_1 :: DRIVE_PAD_CTL :: BL_ND_STRENGTH [04:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_DRIVE_PAD_CTL_BL_ND_STRENGTH_MASK 0x0000001f
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_DRIVE_PAD_CTL_BL_ND_STRENGTH_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_DRIVE_PAD_CTL_BL_ND_STRENGTH_DEFAULT 0x0000001f
-
-/***************************************************************************
- *RD_EN_DRIVE_PAD_CTL - SSTL read enable pad drive characteristics control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_3_1 :: RD_EN_DRIVE_PAD_CTL :: reserved0 [31:20] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_RD_EN_DRIVE_PAD_CTL_reserved0_MASK 0xfff00000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_RD_EN_DRIVE_PAD_CTL_reserved0_SHIFT 20
-
-/* DDR34_PHY_BYTE_LANE_3_1 :: RD_EN_DRIVE_PAD_CTL :: EDC_RD_EN_PD_STRENGTH [19:15] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_RD_EN_DRIVE_PAD_CTL_EDC_RD_EN_PD_STRENGTH_MASK 0x000f8000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_RD_EN_DRIVE_PAD_CTL_EDC_RD_EN_PD_STRENGTH_SHIFT 15
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_RD_EN_DRIVE_PAD_CTL_EDC_RD_EN_PD_STRENGTH_DEFAULT 0x0000001f
-
-/* DDR34_PHY_BYTE_LANE_3_1 :: RD_EN_DRIVE_PAD_CTL :: EDC_RD_EN_ND_STRENGTH [14:10] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_RD_EN_DRIVE_PAD_CTL_EDC_RD_EN_ND_STRENGTH_MASK 0x00007c00
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_RD_EN_DRIVE_PAD_CTL_EDC_RD_EN_ND_STRENGTH_SHIFT 10
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_RD_EN_DRIVE_PAD_CTL_EDC_RD_EN_ND_STRENGTH_DEFAULT 0x0000001f
-
-/* DDR34_PHY_BYTE_LANE_3_1 :: RD_EN_DRIVE_PAD_CTL :: BL_RD_EN_PD_STRENGTH [09:05] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_RD_EN_DRIVE_PAD_CTL_BL_RD_EN_PD_STRENGTH_MASK 0x000003e0
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_RD_EN_DRIVE_PAD_CTL_BL_RD_EN_PD_STRENGTH_SHIFT 5
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_RD_EN_DRIVE_PAD_CTL_BL_RD_EN_PD_STRENGTH_DEFAULT 0x0000001f
-
-/* DDR34_PHY_BYTE_LANE_3_1 :: RD_EN_DRIVE_PAD_CTL :: BL_RD_EN_ND_STRENGTH [04:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_RD_EN_DRIVE_PAD_CTL_BL_RD_EN_ND_STRENGTH_MASK 0x0000001f
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_RD_EN_DRIVE_PAD_CTL_BL_RD_EN_ND_STRENGTH_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_RD_EN_DRIVE_PAD_CTL_BL_RD_EN_ND_STRENGTH_DEFAULT 0x0000001f
-
-/***************************************************************************
- *STATIC_PAD_CTL - pad rx and tx characteristics control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_3_1 :: STATIC_PAD_CTL :: reserved0 [31:21] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_STATIC_PAD_CTL_reserved0_MASK 0xffe00000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_STATIC_PAD_CTL_reserved0_SHIFT 21
-
-/* DDR34_PHY_BYTE_LANE_3_1 :: STATIC_PAD_CTL :: DQS_MODE [20:20] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_STATIC_PAD_CTL_DQS_MODE_MASK 0x00100000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_STATIC_PAD_CTL_DQS_MODE_SHIFT 20
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_STATIC_PAD_CTL_DQS_MODE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_1 :: STATIC_PAD_CTL :: reserved1 [19:18] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_STATIC_PAD_CTL_reserved1_MASK 0x000c0000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_STATIC_PAD_CTL_reserved1_SHIFT 18
-
-/* DDR34_PHY_BYTE_LANE_3_1 :: STATIC_PAD_CTL :: EDC_MODE [17:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_STATIC_PAD_CTL_EDC_MODE_MASK 0x00030000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_STATIC_PAD_CTL_EDC_MODE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_STATIC_PAD_CTL_EDC_MODE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_1 :: STATIC_PAD_CTL :: reserved2 [15:15] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_STATIC_PAD_CTL_reserved2_MASK 0x00008000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_STATIC_PAD_CTL_reserved2_SHIFT 15
-
-/* DDR34_PHY_BYTE_LANE_3_1 :: STATIC_PAD_CTL :: WDBI_ENABLE [14:14] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_STATIC_PAD_CTL_WDBI_ENABLE_MASK 0x00004000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_STATIC_PAD_CTL_WDBI_ENABLE_SHIFT 14
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_STATIC_PAD_CTL_WDBI_ENABLE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_1 :: STATIC_PAD_CTL :: RDBI_ENABLE [13:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_STATIC_PAD_CTL_RDBI_ENABLE_MASK 0x00002000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_STATIC_PAD_CTL_RDBI_ENABLE_SHIFT 13
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_STATIC_PAD_CTL_RDBI_ENABLE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_1 :: STATIC_PAD_CTL :: DM_MODE [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_STATIC_PAD_CTL_DM_MODE_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_STATIC_PAD_CTL_DM_MODE_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_STATIC_PAD_CTL_DM_MODE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_1 :: STATIC_PAD_CTL :: reserved3 [11:11] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_STATIC_PAD_CTL_reserved3_MASK 0x00000800
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_STATIC_PAD_CTL_reserved3_SHIFT 11
-
-/* DDR34_PHY_BYTE_LANE_3_1 :: STATIC_PAD_CTL :: DQS_TX_PAUSE [10:10] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_STATIC_PAD_CTL_DQS_TX_PAUSE_MASK 0x00000400
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_STATIC_PAD_CTL_DQS_TX_PAUSE_SHIFT 10
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_STATIC_PAD_CTL_DQS_TX_PAUSE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_1 :: STATIC_PAD_CTL :: DQS_TX_DIS [09:09] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_STATIC_PAD_CTL_DQS_TX_DIS_MASK 0x00000200
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_STATIC_PAD_CTL_DQS_TX_DIS_SHIFT 9
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_STATIC_PAD_CTL_DQS_TX_DIS_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_1 :: STATIC_PAD_CTL :: reserved4 [08:08] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_STATIC_PAD_CTL_reserved4_MASK 0x00000100
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_STATIC_PAD_CTL_reserved4_SHIFT 8
-
-/* DDR34_PHY_BYTE_LANE_3_1 :: STATIC_PAD_CTL :: TX_MODE [07:04] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_STATIC_PAD_CTL_TX_MODE_MASK 0x000000f0
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_STATIC_PAD_CTL_TX_MODE_SHIFT 4
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_STATIC_PAD_CTL_TX_MODE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_1 :: STATIC_PAD_CTL :: reserved5 [03:03] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_STATIC_PAD_CTL_reserved5_MASK 0x00000008
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_STATIC_PAD_CTL_reserved5_SHIFT 3
-
-/* DDR34_PHY_BYTE_LANE_3_1 :: STATIC_PAD_CTL :: RX_MODE [02:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_STATIC_PAD_CTL_RX_MODE_MASK 0x00000007
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_STATIC_PAD_CTL_RX_MODE_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_STATIC_PAD_CTL_RX_MODE_DEFAULT 0x00000000
-
-/***************************************************************************
- *WR_PREAMBLE_MODE - Write cycle preamble control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_3_1 :: WR_PREAMBLE_MODE :: reserved0 [31:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_WR_PREAMBLE_MODE_reserved0_MASK 0xffff0000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_WR_PREAMBLE_MODE_reserved0_SHIFT 16
-
-/* DDR34_PHY_BYTE_LANE_3_1 :: WR_PREAMBLE_MODE :: DQ_POSTAM_BITS [15:14] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_WR_PREAMBLE_MODE_DQ_POSTAM_BITS_MASK 0x0000c000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_WR_PREAMBLE_MODE_DQ_POSTAM_BITS_SHIFT 14
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_WR_PREAMBLE_MODE_DQ_POSTAM_BITS_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_1 :: WR_PREAMBLE_MODE :: DQ_PREAM_BITS [13:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_WR_PREAMBLE_MODE_DQ_PREAM_BITS_MASK 0x00003000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_WR_PREAMBLE_MODE_DQ_PREAM_BITS_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_WR_PREAMBLE_MODE_DQ_PREAM_BITS_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_1 :: WR_PREAMBLE_MODE :: DQS [11:08] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_WR_PREAMBLE_MODE_DQS_MASK 0x00000f00
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_WR_PREAMBLE_MODE_DQS_SHIFT 8
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_WR_PREAMBLE_MODE_DQS_DEFAULT 0x0000000e
-
-/* DDR34_PHY_BYTE_LANE_3_1 :: WR_PREAMBLE_MODE :: reserved1 [07:05] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_WR_PREAMBLE_MODE_reserved1_MASK 0x000000e0
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_WR_PREAMBLE_MODE_reserved1_SHIFT 5
-
-/* DDR34_PHY_BYTE_LANE_3_1 :: WR_PREAMBLE_MODE :: DQS_POSTAM_BITS [04:03] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_WR_PREAMBLE_MODE_DQS_POSTAM_BITS_MASK 0x00000018
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_WR_PREAMBLE_MODE_DQS_POSTAM_BITS_SHIFT 3
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_WR_PREAMBLE_MODE_DQS_POSTAM_BITS_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_1 :: WR_PREAMBLE_MODE :: DQS_PREAM_BITS [02:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_WR_PREAMBLE_MODE_DQS_PREAM_BITS_MASK 0x00000007
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_WR_PREAMBLE_MODE_DQS_PREAM_BITS_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_WR_PREAMBLE_MODE_DQS_PREAM_BITS_DEFAULT 0x00000002
-
-/***************************************************************************
- *ODT_CONTROL - Read channel ODT control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_3_1 :: ODT_CONTROL :: reserved_for_padding0 [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_ODT_CONTROL_reserved_for_padding0_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_ODT_CONTROL_reserved_for_padding0_SHIFT 31
-
-/* DDR34_PHY_BYTE_LANE_3_1 :: ODT_CONTROL :: reserved1 [30:10] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_ODT_CONTROL_reserved1_MASK 0x7ffffc00
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_ODT_CONTROL_reserved1_SHIFT 10
-
-/* DDR34_PHY_BYTE_LANE_3_1 :: ODT_CONTROL :: ODT_ENABLE [09:09] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_ODT_CONTROL_ODT_ENABLE_MASK 0x00000200
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_ODT_CONTROL_ODT_ENABLE_SHIFT 9
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_ODT_CONTROL_ODT_ENABLE_DEFAULT 0x00000001
-
-/* DDR34_PHY_BYTE_LANE_3_1 :: ODT_CONTROL :: ODT_DELAY [08:06] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_ODT_CONTROL_ODT_DELAY_MASK 0x000001c0
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_ODT_CONTROL_ODT_DELAY_SHIFT 6
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_ODT_CONTROL_ODT_DELAY_DEFAULT 0x00000001
-
-/* DDR34_PHY_BYTE_LANE_3_1 :: ODT_CONTROL :: ODT_POST_LENGTH [05:03] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_ODT_CONTROL_ODT_POST_LENGTH_MASK 0x00000038
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_ODT_CONTROL_ODT_POST_LENGTH_SHIFT 3
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_ODT_CONTROL_ODT_POST_LENGTH_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_1 :: ODT_CONTROL :: ODT_PRE_LENGTH [02:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_ODT_CONTROL_ODT_PRE_LENGTH_MASK 0x00000007
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_ODT_CONTROL_ODT_PRE_LENGTH_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_ODT_CONTROL_ODT_PRE_LENGTH_DEFAULT 0x00000003
-
-/***************************************************************************
- *EDC_DPD_CONTROL - GDDR5M EDC digital phase detector control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_3_1 :: EDC_DPD_CONTROL :: reserved0 [31:06] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_EDC_DPD_CONTROL_reserved0_MASK 0xffffffc0
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_EDC_DPD_CONTROL_reserved0_SHIFT 6
-
-/* DDR34_PHY_BYTE_LANE_3_1 :: EDC_DPD_CONTROL :: DQS_PHASE_OVERRIDE_VALUE [05:05] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_EDC_DPD_CONTROL_DQS_PHASE_OVERRIDE_VALUE_MASK 0x00000020
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_EDC_DPD_CONTROL_DQS_PHASE_OVERRIDE_VALUE_SHIFT 5
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_EDC_DPD_CONTROL_DQS_PHASE_OVERRIDE_VALUE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_1 :: EDC_DPD_CONTROL :: DQS_PHASE_OVERRIDE_ENABLE [04:04] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_EDC_DPD_CONTROL_DQS_PHASE_OVERRIDE_ENABLE_MASK 0x00000010
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_EDC_DPD_CONTROL_DQS_PHASE_OVERRIDE_ENABLE_SHIFT 4
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_EDC_DPD_CONTROL_DQS_PHASE_OVERRIDE_ENABLE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_1 :: EDC_DPD_CONTROL :: SET_ADJ_EN [03:03] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_EDC_DPD_CONTROL_SET_ADJ_EN_MASK 0x00000008
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_EDC_DPD_CONTROL_SET_ADJ_EN_SHIFT 3
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_EDC_DPD_CONTROL_SET_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_1 :: EDC_DPD_CONTROL :: UPDATE [02:02] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_EDC_DPD_CONTROL_UPDATE_MASK 0x00000004
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_EDC_DPD_CONTROL_UPDATE_SHIFT 2
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_EDC_DPD_CONTROL_UPDATE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_1 :: EDC_DPD_CONTROL :: MONITOR [01:01] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_EDC_DPD_CONTROL_MONITOR_MASK 0x00000002
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_EDC_DPD_CONTROL_MONITOR_SHIFT 1
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_EDC_DPD_CONTROL_MONITOR_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_1 :: EDC_DPD_CONTROL :: INIT [00:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_EDC_DPD_CONTROL_INIT_MASK 0x00000001
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_EDC_DPD_CONTROL_INIT_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_EDC_DPD_CONTROL_INIT_DEFAULT 0x00000000
-
-/***************************************************************************
- *EDC_DPD_STATUS - GDDR5M EDC digital phase detector status register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_3_1 :: EDC_DPD_STATUS :: reserved0 [31:25] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_EDC_DPD_STATUS_reserved0_MASK 0xfe000000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_EDC_DPD_STATUS_reserved0_SHIFT 25
-
-/* DDR34_PHY_BYTE_LANE_3_1 :: EDC_DPD_STATUS :: CURRENT_DQS_PHASE [24:24] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_EDC_DPD_STATUS_CURRENT_DQS_PHASE_MASK 0x01000000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_EDC_DPD_STATUS_CURRENT_DQS_PHASE_SHIFT 24
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_EDC_DPD_STATUS_CURRENT_DQS_PHASE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_1 :: EDC_DPD_STATUS :: CURRENT_VDL_SETTING [23:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_EDC_DPD_STATUS_CURRENT_VDL_SETTING_MASK 0x00ff0000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_EDC_DPD_STATUS_CURRENT_VDL_SETTING_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_EDC_DPD_STATUS_CURRENT_VDL_SETTING_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_1 :: EDC_DPD_STATUS :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_EDC_DPD_STATUS_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_EDC_DPD_STATUS_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_3_1 :: EDC_DPD_STATUS :: INIT_DQS_PHASE [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_EDC_DPD_STATUS_INIT_DQS_PHASE_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_EDC_DPD_STATUS_INIT_DQS_PHASE_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_EDC_DPD_STATUS_INIT_DQS_PHASE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_1 :: EDC_DPD_STATUS :: INIT_VDL_SETTING [11:04] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_EDC_DPD_STATUS_INIT_VDL_SETTING_MASK 0x00000ff0
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_EDC_DPD_STATUS_INIT_VDL_SETTING_SHIFT 4
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_EDC_DPD_STATUS_INIT_VDL_SETTING_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_1 :: EDC_DPD_STATUS :: EDGE_ERROR [03:03] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_EDC_DPD_STATUS_EDGE_ERROR_MASK 0x00000008
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_EDC_DPD_STATUS_EDGE_ERROR_SHIFT 3
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_EDC_DPD_STATUS_EDGE_ERROR_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_1 :: EDC_DPD_STATUS :: MONITOR_BUSY [02:02] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_EDC_DPD_STATUS_MONITOR_BUSY_MASK 0x00000004
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_EDC_DPD_STATUS_MONITOR_BUSY_SHIFT 2
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_EDC_DPD_STATUS_MONITOR_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_1 :: EDC_DPD_STATUS :: INIT_BUSY [01:01] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_EDC_DPD_STATUS_INIT_BUSY_MASK 0x00000002
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_EDC_DPD_STATUS_INIT_BUSY_SHIFT 1
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_EDC_DPD_STATUS_INIT_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_1 :: EDC_DPD_STATUS :: INIT_DONE [00:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_EDC_DPD_STATUS_INIT_DONE_MASK 0x00000001
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_EDC_DPD_STATUS_INIT_DONE_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_EDC_DPD_STATUS_INIT_DONE_DEFAULT 0x00000000
-
-/***************************************************************************
- *EDC_DPD_OUT_CONTROL - GDDR5M EDC digital phase detector output signal control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_3_1 :: EDC_DPD_OUT_CONTROL :: reserved0 [31:20] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_EDC_DPD_OUT_CONTROL_reserved0_MASK 0xfff00000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_EDC_DPD_OUT_CONTROL_reserved0_SHIFT 20
-
-/* DDR34_PHY_BYTE_LANE_3_1 :: EDC_DPD_OUT_CONTROL :: LOWER_LIMIT [19:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_EDC_DPD_OUT_CONTROL_LOWER_LIMIT_MASK 0x000ff000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_EDC_DPD_OUT_CONTROL_LOWER_LIMIT_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_EDC_DPD_OUT_CONTROL_LOWER_LIMIT_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_1 :: EDC_DPD_OUT_CONTROL :: UPPER_LIMIT [11:04] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_EDC_DPD_OUT_CONTROL_UPPER_LIMIT_MASK 0x00000ff0
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_EDC_DPD_OUT_CONTROL_UPPER_LIMIT_SHIFT 4
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_EDC_DPD_OUT_CONTROL_UPPER_LIMIT_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_1 :: EDC_DPD_OUT_CONTROL :: reserved1 [03:01] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_EDC_DPD_OUT_CONTROL_reserved1_MASK 0x0000000e
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_EDC_DPD_OUT_CONTROL_reserved1_SHIFT 1
-
-/* DDR34_PHY_BYTE_LANE_3_1 :: EDC_DPD_OUT_CONTROL :: ENABLE [00:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_EDC_DPD_OUT_CONTROL_ENABLE_MASK 0x00000001
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_EDC_DPD_OUT_CONTROL_ENABLE_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_EDC_DPD_OUT_CONTROL_ENABLE_DEFAULT 0x00000000
-
-/***************************************************************************
- *EDC_DPD_OUT_STATUS - GDDR5M EDC digital phase detector output signal status register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_3_1 :: EDC_DPD_OUT_STATUS :: reserved0 [31:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_EDC_DPD_OUT_STATUS_reserved0_MASK 0xfffff000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_EDC_DPD_OUT_STATUS_reserved0_SHIFT 12
-
-/* DDR34_PHY_BYTE_LANE_3_1 :: EDC_DPD_OUT_STATUS :: VDL_SETTING [11:04] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_EDC_DPD_OUT_STATUS_VDL_SETTING_MASK 0x00000ff0
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_EDC_DPD_OUT_STATUS_VDL_SETTING_SHIFT 4
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_EDC_DPD_OUT_STATUS_VDL_SETTING_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_1 :: EDC_DPD_OUT_STATUS :: reserved1 [03:01] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_EDC_DPD_OUT_STATUS_reserved1_MASK 0x0000000e
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_EDC_DPD_OUT_STATUS_reserved1_SHIFT 1
-
-/* DDR34_PHY_BYTE_LANE_3_1 :: EDC_DPD_OUT_STATUS :: VALID [00:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_EDC_DPD_OUT_STATUS_VALID_MASK 0x00000001
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_EDC_DPD_OUT_STATUS_VALID_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_EDC_DPD_OUT_STATUS_VALID_DEFAULT 0x00000000
-
-/***************************************************************************
- *EDC_DPD_OUT_STATUS_CLEAR - GDDR5M EDC digital phase detector output signal status clear register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_3_1 :: EDC_DPD_OUT_STATUS_CLEAR :: reserved0 [31:01] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_EDC_DPD_OUT_STATUS_CLEAR_reserved0_MASK 0xfffffffe
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_EDC_DPD_OUT_STATUS_CLEAR_reserved0_SHIFT 1
-
-/* DDR34_PHY_BYTE_LANE_3_1 :: EDC_DPD_OUT_STATUS_CLEAR :: CLEAR [00:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_EDC_DPD_OUT_STATUS_CLEAR_CLEAR_MASK 0x00000001
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_EDC_DPD_OUT_STATUS_CLEAR_CLEAR_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_EDC_DPD_OUT_STATUS_CLEAR_CLEAR_DEFAULT 0x00000000
-
-/***************************************************************************
- *EDC_CRC_CONTROL - GDDR5M EDC signal path CRC control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_3_1 :: EDC_CRC_CONTROL :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_EDC_CRC_CONTROL_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_EDC_CRC_CONTROL_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_EDC_CRC_CONTROL_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_1 :: EDC_CRC_CONTROL :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_EDC_CRC_CONTROL_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_EDC_CRC_CONTROL_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_3_1 :: EDC_CRC_CONTROL :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_EDC_CRC_CONTROL_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_EDC_CRC_CONTROL_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_EDC_CRC_CONTROL_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_1 :: EDC_CRC_CONTROL :: reserved1 [15:11] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_EDC_CRC_CONTROL_reserved1_MASK 0x0000f800
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_EDC_CRC_CONTROL_reserved1_SHIFT 11
-
-/* DDR34_PHY_BYTE_LANE_3_1 :: EDC_CRC_CONTROL :: CRCWL [10:08] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_EDC_CRC_CONTROL_CRCWL_MASK 0x00000700
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_EDC_CRC_CONTROL_CRCWL_SHIFT 8
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_EDC_CRC_CONTROL_CRCWL_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_1 :: EDC_CRC_CONTROL :: reserved2 [07:06] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_EDC_CRC_CONTROL_reserved2_MASK 0x000000c0
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_EDC_CRC_CONTROL_reserved2_SHIFT 6
-
-/* DDR34_PHY_BYTE_LANE_3_1 :: EDC_CRC_CONTROL :: CRCRL [05:04] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_EDC_CRC_CONTROL_CRCRL_MASK 0x00000030
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_EDC_CRC_CONTROL_CRCRL_SHIFT 4
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_EDC_CRC_CONTROL_CRCRL_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_1 :: EDC_CRC_CONTROL :: reserved3 [03:03] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_EDC_CRC_CONTROL_reserved3_MASK 0x00000008
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_EDC_CRC_CONTROL_reserved3_SHIFT 3
-
-/* DDR34_PHY_BYTE_LANE_3_1 :: EDC_CRC_CONTROL :: COUNT_MODE [02:02] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_EDC_CRC_CONTROL_COUNT_MODE_MASK 0x00000004
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_EDC_CRC_CONTROL_COUNT_MODE_SHIFT 2
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_EDC_CRC_CONTROL_COUNT_MODE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_1 :: EDC_CRC_CONTROL :: ENABLE_WR [01:01] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_EDC_CRC_CONTROL_ENABLE_WR_MASK 0x00000002
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_EDC_CRC_CONTROL_ENABLE_WR_SHIFT 1
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_EDC_CRC_CONTROL_ENABLE_WR_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_1 :: EDC_CRC_CONTROL :: ENABLE_RD [00:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_EDC_CRC_CONTROL_ENABLE_RD_MASK 0x00000001
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_EDC_CRC_CONTROL_ENABLE_RD_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_EDC_CRC_CONTROL_ENABLE_RD_DEFAULT 0x00000000
-
-/***************************************************************************
- *EDC_CRC_STATUS - GDDR5M EDC signal path CRC status register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_3_1 :: EDC_CRC_STATUS :: reserved0 [31:04] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_EDC_CRC_STATUS_reserved0_MASK 0xfffffff0
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_EDC_CRC_STATUS_reserved0_SHIFT 4
-
-/* DDR34_PHY_BYTE_LANE_3_1 :: EDC_CRC_STATUS :: WR_FAIL [03:03] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_EDC_CRC_STATUS_WR_FAIL_MASK 0x00000008
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_EDC_CRC_STATUS_WR_FAIL_SHIFT 3
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_EDC_CRC_STATUS_WR_FAIL_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_1 :: EDC_CRC_STATUS :: WR_PASS [02:02] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_EDC_CRC_STATUS_WR_PASS_MASK 0x00000004
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_EDC_CRC_STATUS_WR_PASS_SHIFT 2
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_EDC_CRC_STATUS_WR_PASS_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_1 :: EDC_CRC_STATUS :: RD_FAIL [01:01] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_EDC_CRC_STATUS_RD_FAIL_MASK 0x00000002
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_EDC_CRC_STATUS_RD_FAIL_SHIFT 1
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_EDC_CRC_STATUS_RD_FAIL_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_1 :: EDC_CRC_STATUS :: RD_PASS [00:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_EDC_CRC_STATUS_RD_PASS_MASK 0x00000001
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_EDC_CRC_STATUS_RD_PASS_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_EDC_CRC_STATUS_RD_PASS_DEFAULT 0x00000000
-
-/***************************************************************************
- *EDC_CRC_COUNT - GDDR5M EDC signal path CRC counter register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_3_1 :: EDC_CRC_COUNT :: reserved0 [31:28] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_EDC_CRC_COUNT_reserved0_MASK 0xf0000000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_EDC_CRC_COUNT_reserved0_SHIFT 28
-
-/* DDR34_PHY_BYTE_LANE_3_1 :: EDC_CRC_COUNT :: WR_COUNT [27:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_EDC_CRC_COUNT_WR_COUNT_MASK 0x0fff0000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_EDC_CRC_COUNT_WR_COUNT_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_EDC_CRC_COUNT_WR_COUNT_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_1 :: EDC_CRC_COUNT :: reserved1 [15:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_EDC_CRC_COUNT_reserved1_MASK 0x0000f000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_EDC_CRC_COUNT_reserved1_SHIFT 12
-
-/* DDR34_PHY_BYTE_LANE_3_1 :: EDC_CRC_COUNT :: RD_COUNT [11:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_EDC_CRC_COUNT_RD_COUNT_MASK 0x00000fff
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_EDC_CRC_COUNT_RD_COUNT_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_EDC_CRC_COUNT_RD_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *EDC_CRC_STATUS_CLEAR - GDDR5M EDC signal path CRC counter register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_3_1 :: EDC_CRC_STATUS_CLEAR :: reserved0 [31:01] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_EDC_CRC_STATUS_CLEAR_reserved0_MASK 0xfffffffe
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_EDC_CRC_STATUS_CLEAR_reserved0_SHIFT 1
-
-/* DDR34_PHY_BYTE_LANE_3_1 :: EDC_CRC_STATUS_CLEAR :: CLEAR [00:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_EDC_CRC_STATUS_CLEAR_CLEAR_MASK 0x00000001
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_EDC_CRC_STATUS_CLEAR_CLEAR_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_EDC_CRC_STATUS_CLEAR_CLEAR_DEFAULT 0x00000000
-
-/***************************************************************************
- *BL_SPARE_REG - Byte-Lane Spare register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_3_1 :: BL_SPARE_REG :: reserved_for_eco0 [31:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_BL_SPARE_REG_reserved_for_eco0_MASK 0xffffffff
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_BL_SPARE_REG_reserved_for_eco0_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_BL_SPARE_REG_reserved_for_eco0_DEFAULT 0x00000000
-
-#endif /* #ifndef BCHP_DDR34_PHY_BYTE_LANE_3_1_H__ */
-
-/* End of File */
diff --git a/include/linux/brcmstb/7145a0/bchp_ddr34_phy_control_regs_0.h b/include/linux/brcmstb/7145a0/bchp_ddr34_phy_control_regs_0.h
deleted file mode 100644
index d78866f..0000000
--- a/include/linux/brcmstb/7145a0/bchp_ddr34_phy_control_regs_0.h
+++ /dev/null
@@ -1,4234 +0,0 @@
-/***************************************************************************
- * Copyright (c) 1999-2014, Broadcom Corporation
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
- *
- * Module Description:
- * DO NOT EDIT THIS FILE DIRECTLY
- *
- * This module was generated magically with RDB from a source description
- * file. You must edit the source file for changes to be made to this file.
- *
- *
- * Date: Generated on Wed Sep 3 13:17:41 2014
- * Full Compile MD5 Checksum a8ee62ccf9dde43435c825f266da463d
- * (minus title and desc)
- * MD5 Checksum e373b364a1742e13a0f9eb15fd8aa94f
- *
- * Compiled with: RDB Utility combo_header.pl
- * RDB Parser 3.0
- * unknown unknown
- * Perl Interpreter 5.008005
- * Operating System linux
- *
- * Revision History:
- *
- * $brcm_Log: $
- *
- ***************************************************************************/
-
-#ifndef BCHP_DDR34_PHY_CONTROL_REGS_0_H__
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_H__
-
-/***************************************************************************
- *DDR34_PHY_CONTROL_REGS_0 - DDR34 Address/Comand control registers
- ***************************************************************************/
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_REVISION 0x203b6000 /* Address & Control revision register */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_STATUS 0x203b6004 /* PHY PLL status register */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_CONFIG 0x203b6008 /* PHY PLL configuration register */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_CONTROL1 0x203b600c /* PHY PLL control register */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_CONTROL2 0x203b6010 /* PHY PLL control register */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_CONTROL3 0x203b6014 /* PHY PLL control register */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_DIVIDERS 0x203b6018 /* PHY PLL integer divider register */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_FRAC_DIVIDER 0x203b601c /* PHY PLL fractional divider register */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_SS_CONTROL 0x203b6020 /* PHY PLL spread spectrum control register */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_SS_LIMIT 0x203b6024 /* PHY PLL spread spectrum limit register */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_AUX_CONTROL 0x203b6028 /* Aux Control register */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL 0x203b602c /* Idle mode pad control register */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_IDLE_PAD_ENABLE0 0x203b6030 /* Idle mode pad enable register */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_IDLE_PAD_ENABLE1 0x203b6034 /* Idle mode pad enable register */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL 0x203b6038 /* PVT Compensation control register */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_STATIC_PAD_CTL 0x203b603c /* pad rx and tx characteristics control register */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_DRAM_CONFIG 0x203b6040 /* DRAM configuration register */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_DRAM_TIMING1 0x203b6044 /* DRAM timing register #1 */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_DRAM_TIMING2 0x203b6048 /* DRAM timing register #2 */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_DRAM_TIMING3 0x203b604c /* DRAM timing register #3 */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_DRAM_TIMING4 0x203b6050 /* DRAM timing register #4 */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CALIBRATE 0x203b6060 /* PHY VDL calibration control register */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS1 0x203b6064 /* PHY VDL calibration status register #1 */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS2 0x203b6068 /* PHY VDL calibration status register #2 */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_MONITOR_CONTROL 0x203b606c /* PHY VDL delay monitoring control register */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_MONITOR_REF 0x203b6070 /* PHY VDL delay monitoring reference register */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_MONITOR_STATUS 0x203b6074 /* PHY VDL delay monitoring status register */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_MONITOR_OVERRIDE 0x203b6078 /* PHY VDL delay monitoring override register */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_MONITOR_OUT_CONTROL 0x203b607c /* PHY VDL delay monitoring output control register */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_MONITOR_OUT_STATUS 0x203b6080 /* PHY VDL delay monitoring output status register */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_MONITOR_OUT_STATUS_CLEAR 0x203b6084 /* PHY VDL delay monitoring output status clear register */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD00 0x203b6090 /* DDR interface signal AD[00] VDL control register */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD01 0x203b6094 /* DDR interface signal AD[01] VDL control register */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD02 0x203b6098 /* DDR interface signal AD[02] VDL control register */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD03 0x203b609c /* DDR interface signal AD[03] VDL control register */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD04 0x203b60a0 /* DDR interface signal AD[04] VDL control register */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD05 0x203b60a4 /* DDR interface signal AD[05] VDL control register */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD06 0x203b60a8 /* DDR interface signal AD[06] VDL control register */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD07 0x203b60ac /* DDR interface signal AD[07] VDL control register */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD08 0x203b60b0 /* DDR interface signal AD[08] VDL control register */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD09 0x203b60b4 /* DDR interface signal AD[09] VDL control register */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD10 0x203b60b8 /* DDR interface signal AD[10] VDL control register */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD11 0x203b60bc /* DDR interface signal AD[11] VDL control register */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD12 0x203b60c0 /* DDR interface signal AD[12] VDL control register */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD13 0x203b60c4 /* DDR interface signal AD[13] VDL control register */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD14 0x203b60c8 /* DDR interface signal AD[14] VDL control register */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD15 0x203b60cc /* DDR interface signal AD[15] VDL control register */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_BA0 0x203b60d0 /* DDR interface signal BA[0] VDL control register */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_BA1 0x203b60d4 /* DDR interface signal BA[1] VDL control register */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_BA2 0x203b60d8 /* DDR interface signal BA[2] VDL control register */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AUX0 0x203b60dc /* DDR interface signal AUX[0] VDL control register */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AUX1 0x203b60e0 /* DDR interface signal AUX[1] VDL control register */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AUX2 0x203b60e4 /* DDR interface signal AUX[2] VDL control register */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_CS0 0x203b60e8 /* DDR interface signal CS0 VDL control register */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_CS1 0x203b60ec /* DDR interface signal CS1 VDL control register */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_PAR 0x203b60f0 /* DDR interface signal PAR VDL control register */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_RAS_N 0x203b60f4 /* DDR interface signal RAS_N VDL control register */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_CAS_N 0x203b60f8 /* DDR interface signal CAS_N VDL control register */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_CKE 0x203b60fc /* DDR interface signal CKE0 VDL control register */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_RST_N 0x203b6100 /* DDR interface signal RST_N VDL control register */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_ODT 0x203b6104 /* DDR interface signal ODT0 VDL control register */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_WE_N 0x203b6108 /* DDR interface signal WE_N VDL control register */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_DDR_CK_P 0x203b610c /* DDR interface signal DDR_CK-P VDL control register */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_DDR_CK_N 0x203b6110 /* DDR interface signal DDR_CK-N VDL control register */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CLK_CONTROL 0x203b6114 /* DDR interface signal Write Leveling CLK VDL control register */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_LDE_CONTROL 0x203b6118 /* DDR interface signal Write Leveling Capture Enable VDL control register */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_REFRESH 0x203b6130 /* Refresh engine controller */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_UPDATE_VDL 0x203b6134 /* Update VDL control register */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_UPDATE_VDL_SNOOP1 0x203b6138 /* Update VDL snoop control register #1 */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_UPDATE_VDL_SNOOP2 0x203b613c /* Update VDL snoop control register #2 */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_REG1 0x203b6140 /* DRAM Command Register #1 */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_AUX_REG1 0x203b6144 /* DRAM AUX_N Command Register #1 */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_REG2 0x203b6148 /* DRAM Command Register #2 */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_AUX_REG2 0x203b614c /* DRAM AUX_N Command Register #2 */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_REG3 0x203b6150 /* DRAM Command Register #3 */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_AUX_REG3 0x203b6154 /* DRAM AUX_N Command Register #3 */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_REG4 0x203b6158 /* DRAM Command Register #4 */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_AUX_REG4 0x203b615c /* DRAM AUX_N Command Register #4 */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_REG_TIMER 0x203b6160 /* DRAM Command Timer Register */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_MODE_REG0 0x203b6164 /* DDR3/DDR4/GDDR5 Mode Register 0 and LPDDR Mode Register 1 */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_MODE_REG1 0x203b6168 /* DDR3/DDR4/GDDR5 Mode Register 1 and LPDDR Mode Register 2 */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_MODE_REG2 0x203b616c /* DDR3/DDR4/GDDR5 Mode Register 2 and LPDDR Mode Register 3 */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_MODE_REG3 0x203b6170 /* DDR3/DDR4/GDDR5 Mode Register 3 and LPDDR Mode Register 9 */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_MODE_REG4 0x203b6174 /* DDR4/GDDR5 Mode Register 4 and LPDDR Mode Register 10 */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_MODE_REG5 0x203b6178 /* DDR4/GDDR5 Mode Register 5 and LPDDR Mode Register 16 */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_MODE_REG6 0x203b617c /* DDR4/GDDR5 Mode Register 6 and LPDDR Mode Register 17 */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_MODE_REG7 0x203b6180 /* DDR4/GDDR5 Mode Register 7 and LPDDR Mode Register 41 */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_MODE_REG8 0x203b6184 /* GDDR5 Mode Register 8 and LPDDR Mode Register 42 */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_MODE_REG15 0x203b6188 /* GDDR5 Mode Register 15 and LPDDR Mode Register 48 */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_MODE_REG63 0x203b618c /* LPDDR Mode Register 63 */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_ALERT_CLEAR 0x203b6190 /* DDR4 Alert status clear register */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_ALERT_STATUS 0x203b6194 /* DDR4 Alert status register */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_CA_PARITY 0x203b6198 /* DDR4 CA parity control register */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_CA_PLAYBACK_CONTROL 0x203b619c /* GDDR5 CA playback control register */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_CA_PLAYBACK_STATUS0 0x203b61a0 /* LPDDR3 and GDDR5 CA playback status register0 (for BL0 and BL1) */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_CA_PLAYBACK_STATUS1 0x203b61a4 /* LPDDR3 and GDDR5 CA playback status register1 (for BL2 and BL3) */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_WRITE_LEVELING_CONTROL 0x203b61ac /* Write leveling control register */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_WRITE_LEVELING_STATUS 0x203b61b0 /* Write leveling status register */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_READ_ENABLE_CONTROL 0x203b61b4 /* Read enable test cycle control register */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_READ_ENABLE_STATUS 0x203b61b8 /* Read enable test cycle status register */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_TRAFFIC_GEN_LFSR_SEED 0x203b61c0 /* Traffic generator seed register */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_TRAFFIC_GEN_ADDRESS1 0x203b61c4 /* Traffic generator address register #1 */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_TRAFFIC_GEN_ADDRESS2 0x203b61c8 /* Traffic generator address register #2 */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_TRAFFIC_GEN_CONTROL 0x203b61cc /* Traffic generator control register */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_TRAFFIC_GEN_DATA_CONTROL 0x203b61d0 /* Traffic generator data control register */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_TRAFFIC_GEN_DQ_MASK 0x203b61d4 /* Traffic generator DQ mask register */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_TRAFFIC_GEN_ECC_DQ_MASK 0x203b61d8 /* Traffic generator ECC DQ mask register */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_TRAFFIC_GEN_STATUS 0x203b61dc /* Traffic generator status register */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_TRAFFIC_GEN_DQ_STATUS 0x203b61e0 /* Traffic generator DQ status register */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_TRAFFIC_GEN_ECC_STATUS 0x203b61e4 /* Traffic generator ECC DQ status register */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_TRAFFIC_GEN_ERR_CNT_CONTROL 0x203b61e8 /* Traffic generator error count control register */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_TRAFFIC_GEN_ERR_CNT_STATUS 0x203b61ec /* Traffic generator error count status register */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONTROL 0x203b61f0 /* Virtual VTT Control and Status register */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VIRTUAL_VTT_STATUS 0x203b61f4 /* Virtual VTT Control and Status register */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONNECTIONS 0x203b61f8 /* Virtual VTT Connections register */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VIRTUAL_VTT_OVERRIDE 0x203b61fc /* Virtual VTT Override register */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL 0x203b6200 /* VREF DAC Control register */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PHYBIST_CNTRL 0x203b6204 /* PhyBist Control Register */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PHYBIST_SEED 0x203b6208 /* PhyBist Seed Register */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PHYBIST_STATUS 0x203b620c /* PhyBist General Status Register */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PHYBIST_CTL_STATUS 0x203b6210 /* PhyBist Per-Bit Control Pad Status Register */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PHYBIST_BL0_STATUS 0x203b6214 /* PhyBist Byte Lane #0 Status Register */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PHYBIST_BL1_STATUS 0x203b6218 /* PhyBist Byte Lane #1 Status Register */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PHYBIST_BL2_STATUS 0x203b621c /* PhyBist Byte Lane #2 Status Register */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PHYBIST_BL3_STATUS 0x203b6220 /* PhyBist Byte Lane #3 Status Register */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PHYBIST_BL4_STATUS 0x203b6224 /* PhyBist Byte Lane #4 (ECC) Status Register */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_STANDBY_CONTROL 0x203b6230 /* Standby Control register */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_DEBUG_FREEZE_ENABLE 0x203b6234 /* Freeze-on-error enable register */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_DEBUG_MUX_CONTROL 0x203b6238 /* Debug Mux Control register */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_DFI_CNTRL 0x203b623c /* DFI Interface Ownership Control register */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_WRITE_ODT_CNTRL 0x203b6240 /* Write ODT Control register */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_ABI_PAR_CNTRL 0x203b6244 /* ABI and PAR Control register */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_ZQ_CAL 0x203b6248 /* ZQ Calibration Control register */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_AC_SPARE_REG 0x203b611c /* Address and Control Spare register */
-
-/***************************************************************************
- *REVISION - Address & Control revision register
- ***************************************************************************/
-/* DDR34_PHY_CONTROL_REGS_0 :: REVISION :: reserved0 [31:25] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_REVISION_reserved0_MASK 0xfe000000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_REVISION_reserved0_SHIFT 25
-
-/* DDR34_PHY_CONTROL_REGS_0 :: REVISION :: PERFORMANCE [24:23] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_REVISION_PERFORMANCE_MASK 0x01800000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_REVISION_PERFORMANCE_SHIFT 23
-
-/* DDR34_PHY_CONTROL_REGS_0 :: REVISION :: TECHNOLOGY [22:20] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_REVISION_TECHNOLOGY_MASK 0x00700000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_REVISION_TECHNOLOGY_SHIFT 20
-
-/* DDR34_PHY_CONTROL_REGS_0 :: REVISION :: WB [19:19] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_REVISION_WB_MASK 0x00080000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_REVISION_WB_SHIFT 19
-
-/* DDR34_PHY_CONTROL_REGS_0 :: REVISION :: BITS [18:16] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_REVISION_BITS_MASK 0x00070000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_REVISION_BITS_SHIFT 16
-
-/* DDR34_PHY_CONTROL_REGS_0 :: REVISION :: MAJOR [15:08] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_REVISION_MAJOR_MASK 0x0000ff00
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_REVISION_MAJOR_SHIFT 8
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_REVISION_MAJOR_DEFAULT 0x000000e1
-
-/* DDR34_PHY_CONTROL_REGS_0 :: REVISION :: MINOR [07:00] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_REVISION_MINOR_MASK 0x000000ff
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_REVISION_MINOR_SHIFT 0
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_REVISION_MINOR_DEFAULT 0x00000001
-
-/***************************************************************************
- *PLL_STATUS - PHY PLL status register
- ***************************************************************************/
-/* DDR34_PHY_CONTROL_REGS_0 :: PLL_STATUS :: reserved0 [31:21] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_STATUS_reserved0_MASK 0xffe00000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_STATUS_reserved0_SHIFT 21
-
-/* DDR34_PHY_CONTROL_REGS_0 :: PLL_STATUS :: reserved_for_eco1 [20:17] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_STATUS_reserved_for_eco1_MASK 0x001e0000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_STATUS_reserved_for_eco1_SHIFT 17
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_STATUS_reserved_for_eco1_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: PLL_STATUS :: LOCK_LOST [16:16] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_STATUS_LOCK_LOST_MASK 0x00010000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_STATUS_LOCK_LOST_SHIFT 16
-
-/* DDR34_PHY_CONTROL_REGS_0 :: PLL_STATUS :: CLOCKING_8X [15:15] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_STATUS_CLOCKING_8X_MASK 0x00008000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_STATUS_CLOCKING_8X_SHIFT 15
-
-/* DDR34_PHY_CONTROL_REGS_0 :: PLL_STATUS :: CLOCKING_4X [14:14] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_STATUS_CLOCKING_4X_MASK 0x00004000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_STATUS_CLOCKING_4X_SHIFT 14
-
-/* DDR34_PHY_CONTROL_REGS_0 :: PLL_STATUS :: CLOCKING_2X [13:13] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_STATUS_CLOCKING_2X_MASK 0x00002000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_STATUS_CLOCKING_2X_SHIFT 13
-
-/* DDR34_PHY_CONTROL_REGS_0 :: PLL_STATUS :: STATUS [12:01] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_STATUS_STATUS_MASK 0x00001ffe
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_STATUS_STATUS_SHIFT 1
-
-/* DDR34_PHY_CONTROL_REGS_0 :: PLL_STATUS :: LOCK [00:00] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_STATUS_LOCK_MASK 0x00000001
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_STATUS_LOCK_SHIFT 0
-
-/***************************************************************************
- *PLL_CONFIG - PHY PLL configuration register
- ***************************************************************************/
-/* DDR34_PHY_CONTROL_REGS_0 :: PLL_CONFIG :: reserved0 [31:28] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_CONFIG_reserved0_MASK 0xf0000000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_CONFIG_reserved0_SHIFT 28
-
-/* DDR34_PHY_CONTROL_REGS_0 :: PLL_CONFIG :: reserved_for_eco1 [27:27] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_CONFIG_reserved_for_eco1_MASK 0x08000000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_CONFIG_reserved_for_eco1_SHIFT 27
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_CONFIG_reserved_for_eco1_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: PLL_CONFIG :: CK_LDO_REF_CTRL [26:25] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_CONFIG_CK_LDO_REF_CTRL_MASK 0x06000000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_CONFIG_CK_LDO_REF_CTRL_SHIFT 25
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_CONFIG_CK_LDO_REF_CTRL_DEFAULT 0x00000001
-
-/* DDR34_PHY_CONTROL_REGS_0 :: PLL_CONFIG :: CK_LDO_BIAS [24:23] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_CONFIG_CK_LDO_BIAS_MASK 0x01800000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_CONFIG_CK_LDO_BIAS_SHIFT 23
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_CONFIG_CK_LDO_BIAS_DEFAULT 0x00000003
-
-/* DDR34_PHY_CONTROL_REGS_0 :: PLL_CONFIG :: PLL_LDO_REF_SEL [22:22] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_CONFIG_PLL_LDO_REF_SEL_MASK 0x00400000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_CONFIG_PLL_LDO_REF_SEL_SHIFT 22
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_CONFIG_PLL_LDO_REF_SEL_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: PLL_CONFIG :: PLL_LDO_REF_CTRL [21:20] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_CONFIG_PLL_LDO_REF_CTRL_MASK 0x00300000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_CONFIG_PLL_LDO_REF_CTRL_SHIFT 20
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_CONFIG_PLL_LDO_REF_CTRL_DEFAULT 0x00000001
-
-/* DDR34_PHY_CONTROL_REGS_0 :: PLL_CONFIG :: PLL_LDO_BIAS [19:18] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_CONFIG_PLL_LDO_BIAS_MASK 0x000c0000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_CONFIG_PLL_LDO_BIAS_SHIFT 18
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_CONFIG_PLL_LDO_BIAS_DEFAULT 0x00000003
-
-/* DDR34_PHY_CONTROL_REGS_0 :: PLL_CONFIG :: HOLD [17:17] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_CONFIG_HOLD_MASK 0x00020000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_CONFIG_HOLD_SHIFT 17
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_CONFIG_HOLD_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: PLL_CONFIG :: ENABLE [16:16] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_CONFIG_ENABLE_MASK 0x00010000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_CONFIG_ENABLE_SHIFT 16
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_CONFIG_ENABLE_DEFAULT 0x00000001
-
-/* DDR34_PHY_CONTROL_REGS_0 :: PLL_CONFIG :: reserved2 [15:14] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_CONFIG_reserved2_MASK 0x0000c000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_CONFIG_reserved2_SHIFT 14
-
-/* DDR34_PHY_CONTROL_REGS_0 :: PLL_CONFIG :: FB_OFFSET [13:08] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_CONFIG_FB_OFFSET_MASK 0x00003f00
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_CONFIG_FB_OFFSET_SHIFT 8
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_CONFIG_FB_OFFSET_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: PLL_CONFIG :: reserved3 [07:05] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_CONFIG_reserved3_MASK 0x000000e0
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_CONFIG_reserved3_SHIFT 5
-
-/* DDR34_PHY_CONTROL_REGS_0 :: PLL_CONFIG :: RESET_POST_DIV [04:04] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_CONFIG_RESET_POST_DIV_MASK 0x00000010
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_CONFIG_RESET_POST_DIV_SHIFT 4
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_CONFIG_RESET_POST_DIV_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: PLL_CONFIG :: reserved4 [03:02] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_CONFIG_reserved4_MASK 0x0000000c
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_CONFIG_reserved4_SHIFT 2
-
-/* DDR34_PHY_CONTROL_REGS_0 :: PLL_CONFIG :: RESET [01:01] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_CONFIG_RESET_MASK 0x00000002
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_CONFIG_RESET_SHIFT 1
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_CONFIG_RESET_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: PLL_CONFIG :: PWRDN [00:00] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_CONFIG_PWRDN_MASK 0x00000001
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_CONFIG_PWRDN_SHIFT 0
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_CONFIG_PWRDN_DEFAULT 0x00000000
-
-/***************************************************************************
- *PLL_CONTROL1 - PHY PLL control register
- ***************************************************************************/
-/* DDR34_PHY_CONTROL_REGS_0 :: PLL_CONTROL1 :: reserved0 [31:10] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_CONTROL1_reserved0_MASK 0xfffffc00
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_CONTROL1_reserved0_SHIFT 10
-
-/* DDR34_PHY_CONTROL_REGS_0 :: PLL_CONTROL1 :: I_KP [09:06] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_CONTROL1_I_KP_MASK 0x000003c0
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_CONTROL1_I_KP_SHIFT 6
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_CONTROL1_I_KP_DEFAULT 0x00000005
-
-/* DDR34_PHY_CONTROL_REGS_0 :: PLL_CONTROL1 :: I_KI [05:03] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_CONTROL1_I_KI_MASK 0x00000038
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_CONTROL1_I_KI_SHIFT 3
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_CONTROL1_I_KI_DEFAULT 0x00000002
-
-/* DDR34_PHY_CONTROL_REGS_0 :: PLL_CONTROL1 :: I_KA [02:00] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_CONTROL1_I_KA_MASK 0x00000007
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_CONTROL1_I_KA_SHIFT 0
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_CONTROL1_I_KA_DEFAULT 0x00000000
-
-/***************************************************************************
- *PLL_CONTROL2 - PHY PLL control register
- ***************************************************************************/
-/* DDR34_PHY_CONTROL_REGS_0 :: PLL_CONTROL2 :: VCO_RANGE [31:30] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_CONTROL2_VCO_RANGE_MASK 0xc0000000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_CONTROL2_VCO_RANGE_SHIFT 30
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_CONTROL2_VCO_RANGE_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: PLL_CONTROL2 :: UNUSED2 [29:29] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_CONTROL2_UNUSED2_MASK 0x20000000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_CONTROL2_UNUSED2_SHIFT 29
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_CONTROL2_UNUSED2_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: PLL_CONTROL2 :: NDIV_RELOCK [28:28] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_CONTROL2_NDIV_RELOCK_MASK 0x10000000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_CONTROL2_NDIV_RELOCK_SHIFT 28
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_CONTROL2_NDIV_RELOCK_DEFAULT 0x00000001
-
-/* DDR34_PHY_CONTROL_REGS_0 :: PLL_CONTROL2 :: FAST_LOCK [27:27] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_CONTROL2_FAST_LOCK_MASK 0x08000000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_CONTROL2_FAST_LOCK_SHIFT 27
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_CONTROL2_FAST_LOCK_DEFAULT 0x00000001
-
-/* DDR34_PHY_CONTROL_REGS_0 :: PLL_CONTROL2 :: VCO_FB_DIV2 [26:26] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_CONTROL2_VCO_FB_DIV2_MASK 0x04000000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_CONTROL2_VCO_FB_DIV2_SHIFT 26
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_CONTROL2_VCO_FB_DIV2_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: PLL_CONTROL2 :: POST_CTRL_RESETB [25:24] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_CONTROL2_POST_CTRL_RESETB_MASK 0x03000000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_CONTROL2_POST_CTRL_RESETB_SHIFT 24
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_CONTROL2_POST_CTRL_RESETB_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: PLL_CONTROL2 :: PWM_RATE [23:22] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_CONTROL2_PWM_RATE_MASK 0x00c00000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_CONTROL2_PWM_RATE_SHIFT 22
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_CONTROL2_PWM_RATE_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: PLL_CONTROL2 :: STAT_MODE [21:20] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_CONTROL2_STAT_MODE_MASK 0x00300000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_CONTROL2_STAT_MODE_SHIFT 20
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_CONTROL2_STAT_MODE_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: PLL_CONTROL2 :: UNUSED1 [19:18] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_CONTROL2_UNUSED1_MASK 0x000c0000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_CONTROL2_UNUSED1_SHIFT 18
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_CONTROL2_UNUSED1_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: PLL_CONTROL2 :: STAT_UPDATE [17:17] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_CONTROL2_STAT_UPDATE_MASK 0x00020000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_CONTROL2_STAT_UPDATE_SHIFT 17
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_CONTROL2_STAT_UPDATE_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: PLL_CONTROL2 :: STAT_SELECT [16:14] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_CONTROL2_STAT_SELECT_MASK 0x0001c000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_CONTROL2_STAT_SELECT_SHIFT 14
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_CONTROL2_STAT_SELECT_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: PLL_CONTROL2 :: STAT_RESET [13:13] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_CONTROL2_STAT_RESET_MASK 0x00002000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_CONTROL2_STAT_RESET_SHIFT 13
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_CONTROL2_STAT_RESET_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: PLL_CONTROL2 :: DCO_CTRL_BYPASS_ENABLE [12:12] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_CONTROL2_DCO_CTRL_BYPASS_ENABLE_MASK 0x00001000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_CONTROL2_DCO_CTRL_BYPASS_ENABLE_SHIFT 12
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_CONTROL2_DCO_CTRL_BYPASS_ENABLE_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: PLL_CONTROL2 :: DCO_CTRL_BYPASS [11:00] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_CONTROL2_DCO_CTRL_BYPASS_MASK 0x00000fff
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_CONTROL2_DCO_CTRL_BYPASS_SHIFT 0
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_CONTROL2_DCO_CTRL_BYPASS_DEFAULT 0x00000000
-
-/***************************************************************************
- *PLL_CONTROL3 - PHY PLL control register
- ***************************************************************************/
-/* DDR34_PHY_CONTROL_REGS_0 :: PLL_CONTROL3 :: PLL_CONTROL [31:00] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_CONTROL3_PLL_CONTROL_MASK 0xffffffff
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_CONTROL3_PLL_CONTROL_SHIFT 0
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_CONTROL3_PLL_CONTROL_DEFAULT 0x00000000
-
-/***************************************************************************
- *PLL_DIVIDERS - PHY PLL integer divider register
- ***************************************************************************/
-/* DDR34_PHY_CONTROL_REGS_0 :: PLL_DIVIDERS :: reserved0 [31:28] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_DIVIDERS_reserved0_MASK 0xf0000000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_DIVIDERS_reserved0_SHIFT 28
-
-/* DDR34_PHY_CONTROL_REGS_0 :: PLL_DIVIDERS :: MDIV [27:20] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_DIVIDERS_MDIV_MASK 0x0ff00000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_DIVIDERS_MDIV_SHIFT 20
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_DIVIDERS_MDIV_DEFAULT 0x00000001
-
-/* DDR34_PHY_CONTROL_REGS_0 :: PLL_DIVIDERS :: reserved1 [19:16] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_DIVIDERS_reserved1_MASK 0x000f0000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_DIVIDERS_reserved1_SHIFT 16
-
-/* DDR34_PHY_CONTROL_REGS_0 :: PLL_DIVIDERS :: PDIV [15:12] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_DIVIDERS_PDIV_MASK 0x0000f000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_DIVIDERS_PDIV_SHIFT 12
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_DIVIDERS_PDIV_DEFAULT 0x00000001
-
-/* DDR34_PHY_CONTROL_REGS_0 :: PLL_DIVIDERS :: reserved2 [11:10] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_DIVIDERS_reserved2_MASK 0x00000c00
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_DIVIDERS_reserved2_SHIFT 10
-
-/* DDR34_PHY_CONTROL_REGS_0 :: PLL_DIVIDERS :: NDIV_INT [09:00] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_DIVIDERS_NDIV_INT_MASK 0x000003ff
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_DIVIDERS_NDIV_INT_SHIFT 0
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_DIVIDERS_NDIV_INT_DEFAULT 0x00000010
-
-/***************************************************************************
- *PLL_FRAC_DIVIDER - PHY PLL fractional divider register
- ***************************************************************************/
-/* DDR34_PHY_CONTROL_REGS_0 :: PLL_FRAC_DIVIDER :: reserved0 [31:20] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_FRAC_DIVIDER_reserved0_MASK 0xfff00000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_FRAC_DIVIDER_reserved0_SHIFT 20
-
-/* DDR34_PHY_CONTROL_REGS_0 :: PLL_FRAC_DIVIDER :: NDIV_FRAC [19:00] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_FRAC_DIVIDER_NDIV_FRAC_MASK 0x000fffff
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_FRAC_DIVIDER_NDIV_FRAC_SHIFT 0
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_FRAC_DIVIDER_NDIV_FRAC_DEFAULT 0x00000000
-
-/***************************************************************************
- *PLL_SS_CONTROL - PHY PLL spread spectrum control register
- ***************************************************************************/
-/* DDR34_PHY_CONTROL_REGS_0 :: PLL_SS_CONTROL :: reserved0 [31:20] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_SS_CONTROL_reserved0_MASK 0xfff00000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_SS_CONTROL_reserved0_SHIFT 20
-
-/* DDR34_PHY_CONTROL_REGS_0 :: PLL_SS_CONTROL :: SSC_STEP [19:04] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_SS_CONTROL_SSC_STEP_MASK 0x000ffff0
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_SS_CONTROL_SSC_STEP_SHIFT 4
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_SS_CONTROL_SSC_STEP_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: PLL_SS_CONTROL :: reserved1 [03:01] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_SS_CONTROL_reserved1_MASK 0x0000000e
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_SS_CONTROL_reserved1_SHIFT 1
-
-/* DDR34_PHY_CONTROL_REGS_0 :: PLL_SS_CONTROL :: SSC_MODE [00:00] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_SS_CONTROL_SSC_MODE_MASK 0x00000001
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_SS_CONTROL_SSC_MODE_SHIFT 0
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_SS_CONTROL_SSC_MODE_DEFAULT 0x00000000
-
-/***************************************************************************
- *PLL_SS_LIMIT - PHY PLL spread spectrum limit register
- ***************************************************************************/
-/* DDR34_PHY_CONTROL_REGS_0 :: PLL_SS_LIMIT :: reserved0 [31:26] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_SS_LIMIT_reserved0_MASK 0xfc000000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_SS_LIMIT_reserved0_SHIFT 26
-
-/* DDR34_PHY_CONTROL_REGS_0 :: PLL_SS_LIMIT :: SSC_LIMIT [25:04] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_SS_LIMIT_SSC_LIMIT_MASK 0x03fffff0
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_SS_LIMIT_SSC_LIMIT_SHIFT 4
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_SS_LIMIT_SSC_LIMIT_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: PLL_SS_LIMIT :: reserved1 [03:00] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_SS_LIMIT_reserved1_MASK 0x0000000f
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_SS_LIMIT_reserved1_SHIFT 0
-
-/***************************************************************************
- *AUX_CONTROL - Aux Control register
- ***************************************************************************/
-/* DDR34_PHY_CONTROL_REGS_0 :: AUX_CONTROL :: reserved0 [31:21] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_AUX_CONTROL_reserved0_MASK 0xffe00000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_AUX_CONTROL_reserved0_SHIFT 21
-
-/* DDR34_PHY_CONTROL_REGS_0 :: AUX_CONTROL :: IS_ODT [20:16] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_AUX_CONTROL_IS_ODT_MASK 0x001f0000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_AUX_CONTROL_IS_ODT_SHIFT 16
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_AUX_CONTROL_IS_ODT_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: AUX_CONTROL :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_AUX_CONTROL_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_AUX_CONTROL_reserved1_SHIFT 13
-
-/* DDR34_PHY_CONTROL_REGS_0 :: AUX_CONTROL :: IS_CS [12:08] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_AUX_CONTROL_IS_CS_MASK 0x00001f00
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_AUX_CONTROL_IS_CS_SHIFT 8
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_AUX_CONTROL_IS_CS_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: AUX_CONTROL :: reserved2 [07:05] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_AUX_CONTROL_reserved2_MASK 0x000000e0
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_AUX_CONTROL_reserved2_SHIFT 5
-
-/* DDR34_PHY_CONTROL_REGS_0 :: AUX_CONTROL :: IS_AD [04:00] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_AUX_CONTROL_IS_AD_MASK 0x0000001f
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_AUX_CONTROL_IS_AD_SHIFT 0
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_AUX_CONTROL_IS_AD_DEFAULT 0x00000000
-
-/***************************************************************************
- *IDLE_PAD_CONTROL - Idle mode pad control register
- ***************************************************************************/
-/* DDR34_PHY_CONTROL_REGS_0 :: IDLE_PAD_CONTROL :: IDLE [31:31] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_IDLE_MASK 0x80000000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_IDLE_SHIFT 31
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_IDLE_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: IDLE_PAD_CONTROL :: DIB_MODE [30:30] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_DIB_MODE_MASK 0x40000000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_DIB_MODE_SHIFT 30
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_DIB_MODE_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: IDLE_PAD_CONTROL :: reserved0 [29:08] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_reserved0_MASK 0x3fffff00
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_reserved0_SHIFT 8
-
-/* DDR34_PHY_CONTROL_REGS_0 :: IDLE_PAD_CONTROL :: reserved_for_eco1 [07:04] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_reserved_for_eco1_MASK 0x000000f0
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_reserved_for_eco1_SHIFT 4
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_reserved_for_eco1_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: IDLE_PAD_CONTROL :: RXENB [03:03] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_RXENB_MASK 0x00000008
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_RXENB_SHIFT 3
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_RXENB_DEFAULT 0x00000001
-
-/* DDR34_PHY_CONTROL_REGS_0 :: IDLE_PAD_CONTROL :: IDDQ [02:02] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_IDDQ_MASK 0x00000004
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_IDDQ_SHIFT 2
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_IDDQ_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: IDLE_PAD_CONTROL :: DOUT_N [01:01] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_DOUT_N_MASK 0x00000002
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_DOUT_N_SHIFT 1
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_DOUT_N_DEFAULT 0x00000001
-
-/* DDR34_PHY_CONTROL_REGS_0 :: IDLE_PAD_CONTROL :: DOUT_P [00:00] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_DOUT_P_MASK 0x00000001
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_DOUT_P_SHIFT 0
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_DOUT_P_DEFAULT 0x00000000
-
-/***************************************************************************
- *IDLE_PAD_ENABLE0 - Idle mode pad enable register
- ***************************************************************************/
-/* DDR34_PHY_CONTROL_REGS_0 :: IDLE_PAD_ENABLE0 :: reserved0 [31:15] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_IDLE_PAD_ENABLE0_reserved0_MASK 0xffff8000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_IDLE_PAD_ENABLE0_reserved0_SHIFT 15
-
-/* DDR34_PHY_CONTROL_REGS_0 :: IDLE_PAD_ENABLE0 :: reserved_for_eco1 [14:11] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_IDLE_PAD_ENABLE0_reserved_for_eco1_MASK 0x00007800
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_IDLE_PAD_ENABLE0_reserved_for_eco1_SHIFT 11
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_IDLE_PAD_ENABLE0_reserved_for_eco1_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: IDLE_PAD_ENABLE0 :: IO_IDLE_ENABLE [10:00] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_IDLE_PAD_ENABLE0_IO_IDLE_ENABLE_MASK 0x000007ff
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_IDLE_PAD_ENABLE0_IO_IDLE_ENABLE_SHIFT 0
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_IDLE_PAD_ENABLE0_IO_IDLE_ENABLE_DEFAULT 0x00000000
-
-/***************************************************************************
- *IDLE_PAD_ENABLE1 - Idle mode pad enable register
- ***************************************************************************/
-/* DDR34_PHY_CONTROL_REGS_0 :: IDLE_PAD_ENABLE1 :: reserved0 [31:22] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_IDLE_PAD_ENABLE1_reserved0_MASK 0xffc00000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_IDLE_PAD_ENABLE1_reserved0_SHIFT 22
-
-/* DDR34_PHY_CONTROL_REGS_0 :: IDLE_PAD_ENABLE1 :: IO_IDLE_ENABLE [21:00] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_IDLE_PAD_ENABLE1_IO_IDLE_ENABLE_MASK 0x003fffff
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_IDLE_PAD_ENABLE1_IO_IDLE_ENABLE_SHIFT 0
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_IDLE_PAD_ENABLE1_IO_IDLE_ENABLE_DEFAULT 0x00000000
-
-/***************************************************************************
- *DRIVE_PAD_CTL - PVT Compensation control register
- ***************************************************************************/
-/* DDR34_PHY_CONTROL_REGS_0 :: DRIVE_PAD_CTL :: reserved_for_padding0 [31:30] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_reserved_for_padding0_MASK 0xc0000000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_reserved_for_padding0_SHIFT 30
-
-/* DDR34_PHY_CONTROL_REGS_0 :: DRIVE_PAD_CTL :: ADDR_CTL_PD_IDLE_STRENGTH [29:25] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_ADDR_CTL_PD_IDLE_STRENGTH_MASK 0x3e000000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_ADDR_CTL_PD_IDLE_STRENGTH_SHIFT 25
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_ADDR_CTL_PD_IDLE_STRENGTH_DEFAULT 0x0000001f
-
-/* DDR34_PHY_CONTROL_REGS_0 :: DRIVE_PAD_CTL :: ADDR_CTL_ND_IDLE_STRENGTH [24:20] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_ADDR_CTL_ND_IDLE_STRENGTH_MASK 0x01f00000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_ADDR_CTL_ND_IDLE_STRENGTH_SHIFT 20
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_ADDR_CTL_ND_IDLE_STRENGTH_DEFAULT 0x0000001f
-
-/* DDR34_PHY_CONTROL_REGS_0 :: DRIVE_PAD_CTL :: ADDR_CTL_PD_TERM_STRENGTH [19:15] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_ADDR_CTL_PD_TERM_STRENGTH_MASK 0x000f8000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_ADDR_CTL_PD_TERM_STRENGTH_SHIFT 15
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_ADDR_CTL_PD_TERM_STRENGTH_DEFAULT 0x00000008
-
-/* DDR34_PHY_CONTROL_REGS_0 :: DRIVE_PAD_CTL :: ADDR_CTL_ND_TERM_STRENGTH [14:10] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_ADDR_CTL_ND_TERM_STRENGTH_MASK 0x00007c00
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_ADDR_CTL_ND_TERM_STRENGTH_SHIFT 10
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_ADDR_CTL_ND_TERM_STRENGTH_DEFAULT 0x00000008
-
-/* DDR34_PHY_CONTROL_REGS_0 :: DRIVE_PAD_CTL :: ADDR_CTL_PD_STRENGTH [09:05] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_ADDR_CTL_PD_STRENGTH_MASK 0x000003e0
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_ADDR_CTL_PD_STRENGTH_SHIFT 5
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_ADDR_CTL_PD_STRENGTH_DEFAULT 0x0000001f
-
-/* DDR34_PHY_CONTROL_REGS_0 :: DRIVE_PAD_CTL :: ADDR_CTL_ND_STRENGTH [04:00] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_ADDR_CTL_ND_STRENGTH_MASK 0x0000001f
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_ADDR_CTL_ND_STRENGTH_SHIFT 0
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_ADDR_CTL_ND_STRENGTH_DEFAULT 0x0000001f
-
-/***************************************************************************
- *STATIC_PAD_CTL - pad rx and tx characteristics control register
- ***************************************************************************/
-/* DDR34_PHY_CONTROL_REGS_0 :: STATIC_PAD_CTL :: reserved0 [31:28] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_STATIC_PAD_CTL_reserved0_MASK 0xf0000000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_STATIC_PAD_CTL_reserved0_SHIFT 28
-
-/* DDR34_PHY_CONTROL_REGS_0 :: STATIC_PAD_CTL :: AUTO_OEB [27:27] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_STATIC_PAD_CTL_AUTO_OEB_MASK 0x08000000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_STATIC_PAD_CTL_AUTO_OEB_SHIFT 27
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_STATIC_PAD_CTL_AUTO_OEB_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: STATIC_PAD_CTL :: IDDQ_GDDR5 [26:26] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_STATIC_PAD_CTL_IDDQ_GDDR5_MASK 0x04000000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_STATIC_PAD_CTL_IDDQ_GDDR5_SHIFT 26
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_STATIC_PAD_CTL_IDDQ_GDDR5_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: STATIC_PAD_CTL :: IDDQ_LPDDR [25:25] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_STATIC_PAD_CTL_IDDQ_LPDDR_MASK 0x02000000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_STATIC_PAD_CTL_IDDQ_LPDDR_SHIFT 25
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_STATIC_PAD_CTL_IDDQ_LPDDR_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: STATIC_PAD_CTL :: IDDQ_CLK1 [24:24] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_STATIC_PAD_CTL_IDDQ_CLK1_MASK 0x01000000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_STATIC_PAD_CTL_IDDQ_CLK1_SHIFT 24
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_STATIC_PAD_CTL_IDDQ_CLK1_DEFAULT 0x00000001
-
-/* DDR34_PHY_CONTROL_REGS_0 :: STATIC_PAD_CTL :: IDDQ_CLK0 [23:23] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_STATIC_PAD_CTL_IDDQ_CLK0_MASK 0x00800000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_STATIC_PAD_CTL_IDDQ_CLK0_SHIFT 23
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_STATIC_PAD_CTL_IDDQ_CLK0_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: STATIC_PAD_CTL :: IDDQ_ODT [22:22] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_STATIC_PAD_CTL_IDDQ_ODT_MASK 0x00400000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_STATIC_PAD_CTL_IDDQ_ODT_SHIFT 22
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_STATIC_PAD_CTL_IDDQ_ODT_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: STATIC_PAD_CTL :: IDDQ_PAR [21:21] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_STATIC_PAD_CTL_IDDQ_PAR_MASK 0x00200000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_STATIC_PAD_CTL_IDDQ_PAR_SHIFT 21
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_STATIC_PAD_CTL_IDDQ_PAR_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: STATIC_PAD_CTL :: IDDQ_BA [20:20] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_STATIC_PAD_CTL_IDDQ_BA_MASK 0x00100000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_STATIC_PAD_CTL_IDDQ_BA_SHIFT 20
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_STATIC_PAD_CTL_IDDQ_BA_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: STATIC_PAD_CTL :: IDDQ_AUX2 [19:19] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_STATIC_PAD_CTL_IDDQ_AUX2_MASK 0x00080000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_STATIC_PAD_CTL_IDDQ_AUX2_SHIFT 19
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_STATIC_PAD_CTL_IDDQ_AUX2_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: STATIC_PAD_CTL :: IDDQ_AUX1 [18:18] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_STATIC_PAD_CTL_IDDQ_AUX1_MASK 0x00040000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_STATIC_PAD_CTL_IDDQ_AUX1_SHIFT 18
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_STATIC_PAD_CTL_IDDQ_AUX1_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: STATIC_PAD_CTL :: IDDQ_AUX0 [17:17] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_STATIC_PAD_CTL_IDDQ_AUX0_MASK 0x00020000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_STATIC_PAD_CTL_IDDQ_AUX0_SHIFT 17
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_STATIC_PAD_CTL_IDDQ_AUX0_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: STATIC_PAD_CTL :: IDDQ_CS1 [16:16] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_STATIC_PAD_CTL_IDDQ_CS1_MASK 0x00010000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_STATIC_PAD_CTL_IDDQ_CS1_SHIFT 16
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_STATIC_PAD_CTL_IDDQ_CS1_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: STATIC_PAD_CTL :: IDDQ_A15 [15:15] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_STATIC_PAD_CTL_IDDQ_A15_MASK 0x00008000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_STATIC_PAD_CTL_IDDQ_A15_SHIFT 15
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_STATIC_PAD_CTL_IDDQ_A15_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: STATIC_PAD_CTL :: IDDQ_A14 [14:14] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_STATIC_PAD_CTL_IDDQ_A14_MASK 0x00004000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_STATIC_PAD_CTL_IDDQ_A14_SHIFT 14
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_STATIC_PAD_CTL_IDDQ_A14_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: STATIC_PAD_CTL :: IDDQ_A13 [13:13] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_STATIC_PAD_CTL_IDDQ_A13_MASK 0x00002000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_STATIC_PAD_CTL_IDDQ_A13_SHIFT 13
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_STATIC_PAD_CTL_IDDQ_A13_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: STATIC_PAD_CTL :: IDDQ_A12 [12:12] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_STATIC_PAD_CTL_IDDQ_A12_MASK 0x00001000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_STATIC_PAD_CTL_IDDQ_A12_SHIFT 12
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_STATIC_PAD_CTL_IDDQ_A12_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: STATIC_PAD_CTL :: IDDQ_A11 [11:11] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_STATIC_PAD_CTL_IDDQ_A11_MASK 0x00000800
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_STATIC_PAD_CTL_IDDQ_A11_SHIFT 11
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_STATIC_PAD_CTL_IDDQ_A11_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: STATIC_PAD_CTL :: IDDQ_A10 [10:10] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_STATIC_PAD_CTL_IDDQ_A10_MASK 0x00000400
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_STATIC_PAD_CTL_IDDQ_A10_SHIFT 10
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_STATIC_PAD_CTL_IDDQ_A10_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: STATIC_PAD_CTL :: IDDQ_A09 [09:09] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_STATIC_PAD_CTL_IDDQ_A09_MASK 0x00000200
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_STATIC_PAD_CTL_IDDQ_A09_SHIFT 9
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_STATIC_PAD_CTL_IDDQ_A09_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: STATIC_PAD_CTL :: reserved1 [08:08] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_STATIC_PAD_CTL_reserved1_MASK 0x00000100
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_STATIC_PAD_CTL_reserved1_SHIFT 8
-
-/* DDR34_PHY_CONTROL_REGS_0 :: STATIC_PAD_CTL :: TX_MODE [07:04] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_STATIC_PAD_CTL_TX_MODE_MASK 0x000000f0
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_STATIC_PAD_CTL_TX_MODE_SHIFT 4
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_STATIC_PAD_CTL_TX_MODE_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: STATIC_PAD_CTL :: reserved2 [03:03] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_STATIC_PAD_CTL_reserved2_MASK 0x00000008
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_STATIC_PAD_CTL_reserved2_SHIFT 3
-
-/* DDR34_PHY_CONTROL_REGS_0 :: STATIC_PAD_CTL :: RX_MODE [02:00] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_STATIC_PAD_CTL_RX_MODE_MASK 0x00000007
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_STATIC_PAD_CTL_RX_MODE_SHIFT 0
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_STATIC_PAD_CTL_RX_MODE_DEFAULT 0x00000000
-
-/***************************************************************************
- *DRAM_CONFIG - DRAM configuration register
- ***************************************************************************/
-/* DDR34_PHY_CONTROL_REGS_0 :: DRAM_CONFIG :: INIT_MODE [31:31] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_DRAM_CONFIG_INIT_MODE_MASK 0x80000000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_DRAM_CONFIG_INIT_MODE_SHIFT 31
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_DRAM_CONFIG_INIT_MODE_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: DRAM_CONFIG :: reserved0 [30:28] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_DRAM_CONFIG_reserved0_MASK 0x70000000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_DRAM_CONFIG_reserved0_SHIFT 28
-
-/* DDR34_PHY_CONTROL_REGS_0 :: DRAM_CONFIG :: ECC_ENABLED [27:27] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_DRAM_CONFIG_ECC_ENABLED_MASK 0x08000000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_DRAM_CONFIG_ECC_ENABLED_SHIFT 27
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_DRAM_CONFIG_ECC_ENABLED_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: DRAM_CONFIG :: SPLIT_DQ_BUS [26:26] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_DRAM_CONFIG_SPLIT_DQ_BUS_MASK 0x04000000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_DRAM_CONFIG_SPLIT_DQ_BUS_SHIFT 26
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_DRAM_CONFIG_SPLIT_DQ_BUS_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: DRAM_CONFIG :: BUS16 [25:25] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_DRAM_CONFIG_BUS16_MASK 0x02000000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_DRAM_CONFIG_BUS16_SHIFT 25
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_DRAM_CONFIG_BUS16_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: DRAM_CONFIG :: BUS8 [24:24] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_DRAM_CONFIG_BUS8_MASK 0x01000000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_DRAM_CONFIG_BUS8_SHIFT 24
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_DRAM_CONFIG_BUS8_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: DRAM_CONFIG :: reserved1 [23:16] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_DRAM_CONFIG_reserved1_MASK 0x00ff0000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_DRAM_CONFIG_reserved1_SHIFT 16
-
-/* DDR34_PHY_CONTROL_REGS_0 :: DRAM_CONFIG :: EDC_MODE [15:15] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_DRAM_CONFIG_EDC_MODE_MASK 0x00008000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_DRAM_CONFIG_EDC_MODE_SHIFT 15
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_DRAM_CONFIG_EDC_MODE_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: DRAM_CONFIG :: RDQS_MODE [14:14] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_DRAM_CONFIG_RDQS_MODE_MASK 0x00004000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_DRAM_CONFIG_RDQS_MODE_SHIFT 14
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_DRAM_CONFIG_RDQS_MODE_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: DRAM_CONFIG :: GROUP_BITS [13:12] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_DRAM_CONFIG_GROUP_BITS_MASK 0x00003000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_DRAM_CONFIG_GROUP_BITS_SHIFT 12
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_DRAM_CONFIG_GROUP_BITS_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: DRAM_CONFIG :: BANK_BITS [11:10] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_DRAM_CONFIG_BANK_BITS_MASK 0x00000c00
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_DRAM_CONFIG_BANK_BITS_SHIFT 10
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_DRAM_CONFIG_BANK_BITS_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: DRAM_CONFIG :: COL_BITS [09:08] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_DRAM_CONFIG_COL_BITS_MASK 0x00000300
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_DRAM_CONFIG_COL_BITS_SHIFT 8
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_DRAM_CONFIG_COL_BITS_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: DRAM_CONFIG :: ROW_BITS [07:04] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_DRAM_CONFIG_ROW_BITS_MASK 0x000000f0
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_DRAM_CONFIG_ROW_BITS_SHIFT 4
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_DRAM_CONFIG_ROW_BITS_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: DRAM_CONFIG :: DRAM_TYPE [03:00] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_DRAM_CONFIG_DRAM_TYPE_MASK 0x0000000f
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_DRAM_CONFIG_DRAM_TYPE_SHIFT 0
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_DRAM_CONFIG_DRAM_TYPE_DEFAULT 0x00000000
-
-/***************************************************************************
- *DRAM_TIMING1 - DRAM timing register #1
- ***************************************************************************/
-/* DDR34_PHY_CONTROL_REGS_0 :: DRAM_TIMING1 :: TRAS [31:24] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_DRAM_TIMING1_TRAS_MASK 0xff000000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_DRAM_TIMING1_TRAS_SHIFT 24
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_DRAM_TIMING1_TRAS_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: DRAM_TIMING1 :: TRRD [23:16] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_DRAM_TIMING1_TRRD_MASK 0x00ff0000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_DRAM_TIMING1_TRRD_SHIFT 16
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_DRAM_TIMING1_TRRD_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: DRAM_TIMING1 :: TRP [15:08] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_DRAM_TIMING1_TRP_MASK 0x0000ff00
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_DRAM_TIMING1_TRP_SHIFT 8
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_DRAM_TIMING1_TRP_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: DRAM_TIMING1 :: TRCD [07:00] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_DRAM_TIMING1_TRCD_MASK 0x000000ff
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_DRAM_TIMING1_TRCD_SHIFT 0
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_DRAM_TIMING1_TRCD_DEFAULT 0x00000000
-
-/***************************************************************************
- *DRAM_TIMING2 - DRAM timing register #2
- ***************************************************************************/
-/* DDR34_PHY_CONTROL_REGS_0 :: DRAM_TIMING2 :: TRTP [31:24] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_DRAM_TIMING2_TRTP_MASK 0xff000000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_DRAM_TIMING2_TRTP_SHIFT 24
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_DRAM_TIMING2_TRTP_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: DRAM_TIMING2 :: TWR [23:16] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_DRAM_TIMING2_TWR_MASK 0x00ff0000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_DRAM_TIMING2_TWR_SHIFT 16
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_DRAM_TIMING2_TWR_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: DRAM_TIMING2 :: TCWL [15:08] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_DRAM_TIMING2_TCWL_MASK 0x0000ff00
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_DRAM_TIMING2_TCWL_SHIFT 8
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_DRAM_TIMING2_TCWL_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: DRAM_TIMING2 :: TCAS [07:00] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_DRAM_TIMING2_TCAS_MASK 0x000000ff
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_DRAM_TIMING2_TCAS_SHIFT 0
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_DRAM_TIMING2_TCAS_DEFAULT 0x00000000
-
-/***************************************************************************
- *DRAM_TIMING3 - DRAM timing register #3
- ***************************************************************************/
-/* DDR34_PHY_CONTROL_REGS_0 :: DRAM_TIMING3 :: reserved0 [31:24] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_DRAM_TIMING3_reserved0_MASK 0xff000000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_DRAM_TIMING3_reserved0_SHIFT 24
-
-/* DDR34_PHY_CONTROL_REGS_0 :: DRAM_TIMING3 :: TCAL [23:20] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_DRAM_TIMING3_TCAL_MASK 0x00f00000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_DRAM_TIMING3_TCAL_SHIFT 20
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_DRAM_TIMING3_TCAL_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: DRAM_TIMING3 :: TRTW [19:16] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_DRAM_TIMING3_TRTW_MASK 0x000f0000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_DRAM_TIMING3_TRTW_SHIFT 16
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_DRAM_TIMING3_TRTW_DEFAULT 0x00000004
-
-/* DDR34_PHY_CONTROL_REGS_0 :: DRAM_TIMING3 :: TWTR [15:12] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_DRAM_TIMING3_TWTR_MASK 0x0000f000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_DRAM_TIMING3_TWTR_SHIFT 12
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_DRAM_TIMING3_TWTR_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: DRAM_TIMING3 :: TRFC [11:00] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_DRAM_TIMING3_TRFC_MASK 0x00000fff
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_DRAM_TIMING3_TRFC_SHIFT 0
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_DRAM_TIMING3_TRFC_DEFAULT 0x00000000
-
-/***************************************************************************
- *DRAM_TIMING4 - DRAM timing register #4
- ***************************************************************************/
-/* DDR34_PHY_CONTROL_REGS_0 :: DRAM_TIMING4 :: temp [31:00] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_DRAM_TIMING4_temp_MASK 0xffffffff
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_DRAM_TIMING4_temp_SHIFT 0
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_DRAM_TIMING4_temp_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CALIBRATE - PHY VDL calibration control register
- ***************************************************************************/
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CALIBRATE :: reserved0 [31:10] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CALIBRATE_reserved0_MASK 0xfffffc00
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CALIBRATE_reserved0_SHIFT 10
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CALIBRATE :: reserved_for_eco1 [09:06] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CALIBRATE_reserved_for_eco1_MASK 0x000003c0
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CALIBRATE_reserved_for_eco1_SHIFT 6
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CALIBRATE_reserved_for_eco1_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CALIBRATE :: HALF_STEPS [05:05] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CALIBRATE_HALF_STEPS_MASK 0x00000020
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CALIBRATE_HALF_STEPS_SHIFT 5
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CALIBRATE_HALF_STEPS_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CALIBRATE :: UPDATE_FAST [04:04] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CALIBRATE_UPDATE_FAST_MASK 0x00000010
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CALIBRATE_UPDATE_FAST_SHIFT 4
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CALIBRATE_UPDATE_FAST_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CALIBRATE :: UPDATE_REGS [03:03] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CALIBRATE_UPDATE_REGS_MASK 0x00000008
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CALIBRATE_UPDATE_REGS_SHIFT 3
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CALIBRATE_UPDATE_REGS_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CALIBRATE :: CALIB_FTM2 [02:02] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CALIBRATE_CALIB_FTM2_MASK 0x00000004
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CALIBRATE_CALIB_FTM2_SHIFT 2
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CALIBRATE_CALIB_FTM2_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CALIBRATE :: CALIB_PHYBIST [01:01] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CALIBRATE_CALIB_PHYBIST_MASK 0x00000002
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CALIBRATE_CALIB_PHYBIST_SHIFT 1
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CALIBRATE_CALIB_PHYBIST_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CALIBRATE :: CALIB_ONCE [00:00] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CALIBRATE_CALIB_ONCE_MASK 0x00000001
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CALIBRATE_CALIB_ONCE_SHIFT 0
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CALIBRATE_CALIB_ONCE_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CALIB_STATUS1 - PHY VDL calibration status register #1
- ***************************************************************************/
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CALIB_STATUS1 :: reserved0 [31:18] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS1_reserved0_MASK 0xfffc0000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS1_reserved0_SHIFT 18
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CALIB_STATUS1 :: CALIB_TOTAL_STEPS [17:08] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS1_CALIB_TOTAL_STEPS_MASK 0x0003ff00
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS1_CALIB_TOTAL_STEPS_SHIFT 8
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS1_CALIB_TOTAL_STEPS_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CALIB_STATUS1 :: reserved1 [07:06] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS1_reserved1_MASK 0x000000c0
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS1_reserved1_SHIFT 6
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CALIB_STATUS1 :: CALIB_BUS_ERROR [05:05] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS1_CALIB_BUS_ERROR_MASK 0x00000020
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS1_CALIB_BUS_ERROR_SHIFT 5
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS1_CALIB_BUS_ERROR_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CALIB_STATUS1 :: CALIB_REGS_DONE [04:04] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS1_CALIB_REGS_DONE_MASK 0x00000010
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS1_CALIB_REGS_DONE_SHIFT 4
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS1_CALIB_REGS_DONE_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CALIB_STATUS1 :: CALIB_LOCK_6B [03:03] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS1_CALIB_LOCK_6B_MASK 0x00000008
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS1_CALIB_LOCK_6B_SHIFT 3
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS1_CALIB_LOCK_6B_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CALIB_STATUS1 :: CALIB_LOCK_4B [02:02] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS1_CALIB_LOCK_4B_MASK 0x00000004
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS1_CALIB_LOCK_4B_SHIFT 2
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS1_CALIB_LOCK_4B_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CALIB_STATUS1 :: CALIB_LOCK_2B [01:01] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS1_CALIB_LOCK_2B_MASK 0x00000002
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS1_CALIB_LOCK_2B_SHIFT 1
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS1_CALIB_LOCK_2B_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CALIB_STATUS1 :: CALIB_IDLE [00:00] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS1_CALIB_IDLE_MASK 0x00000001
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS1_CALIB_IDLE_SHIFT 0
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS1_CALIB_IDLE_DEFAULT 0x00000001
-
-/***************************************************************************
- *VDL_CALIB_STATUS2 - PHY VDL calibration status register #2
- ***************************************************************************/
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CALIB_STATUS2 :: reserved0 [31:22] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS2_reserved0_MASK 0xffc00000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS2_reserved0_SHIFT 22
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CALIB_STATUS2 :: CALIB_4B_STEPS [21:12] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS2_CALIB_4B_STEPS_MASK 0x003ff000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS2_CALIB_4B_STEPS_SHIFT 12
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS2_CALIB_4B_STEPS_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CALIB_STATUS2 :: reserved1 [11:10] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS2_reserved1_MASK 0x00000c00
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS2_reserved1_SHIFT 10
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CALIB_STATUS2 :: CALIB_2B_STEPS [09:00] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS2_CALIB_2B_STEPS_MASK 0x000003ff
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS2_CALIB_2B_STEPS_SHIFT 0
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS2_CALIB_2B_STEPS_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_MONITOR_CONTROL - PHY VDL delay monitoring control register
- ***************************************************************************/
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_MONITOR_CONTROL :: reserved0 [31:22] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_MONITOR_CONTROL_reserved0_MASK 0xffc00000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_MONITOR_CONTROL_reserved0_SHIFT 22
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_MONITOR_CONTROL :: INTERVAL [21:08] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_MONITOR_CONTROL_INTERVAL_MASK 0x003fff00
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_MONITOR_CONTROL_INTERVAL_SHIFT 8
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_MONITOR_CONTROL_INTERVAL_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_MONITOR_CONTROL :: reserved1 [07:04] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_MONITOR_CONTROL_reserved1_MASK 0x000000f0
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_MONITOR_CONTROL_reserved1_SHIFT 4
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_MONITOR_CONTROL :: UPDATE [03:03] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_MONITOR_CONTROL_UPDATE_MASK 0x00000008
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_MONITOR_CONTROL_UPDATE_SHIFT 3
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_MONITOR_CONTROL_UPDATE_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_MONITOR_CONTROL :: FORCE [02:02] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_MONITOR_CONTROL_FORCE_MASK 0x00000004
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_MONITOR_CONTROL_FORCE_SHIFT 2
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_MONITOR_CONTROL_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_MONITOR_CONTROL :: DATA_RATE [01:01] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_MONITOR_CONTROL_DATA_RATE_MASK 0x00000002
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_MONITOR_CONTROL_DATA_RATE_SHIFT 1
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_MONITOR_CONTROL_DATA_RATE_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_MONITOR_CONTROL :: ENABLE [00:00] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_MONITOR_CONTROL_ENABLE_MASK 0x00000001
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_MONITOR_CONTROL_ENABLE_SHIFT 0
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_MONITOR_CONTROL_ENABLE_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_MONITOR_REF - PHY VDL delay monitoring reference register
- ***************************************************************************/
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_MONITOR_REF :: reserved0 [31:22] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_MONITOR_REF_reserved0_MASK 0xffc00000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_MONITOR_REF_reserved0_SHIFT 22
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_MONITOR_REF :: MONITOR_4B_STEPS [21:12] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_MONITOR_REF_MONITOR_4B_STEPS_MASK 0x003ff000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_MONITOR_REF_MONITOR_4B_STEPS_SHIFT 12
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_MONITOR_REF_MONITOR_4B_STEPS_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_MONITOR_REF :: reserved1 [11:10] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_MONITOR_REF_reserved1_MASK 0x00000c00
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_MONITOR_REF_reserved1_SHIFT 10
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_MONITOR_REF :: MONITOR_2B_STEPS [09:00] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_MONITOR_REF_MONITOR_2B_STEPS_MASK 0x000003ff
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_MONITOR_REF_MONITOR_2B_STEPS_SHIFT 0
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_MONITOR_REF_MONITOR_2B_STEPS_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_MONITOR_STATUS - PHY VDL delay monitoring status register
- ***************************************************************************/
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_MONITOR_STATUS :: reserved0 [31:29] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_MONITOR_STATUS_reserved0_MASK 0xe0000000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_MONITOR_STATUS_reserved0_SHIFT 29
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_MONITOR_STATUS :: MONITOR_BUS_ERROR [28:28] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_MONITOR_STATUS_MONITOR_BUS_ERROR_MASK 0x10000000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_MONITOR_STATUS_MONITOR_BUS_ERROR_SHIFT 28
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_MONITOR_STATUS_MONITOR_BUS_ERROR_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_MONITOR_STATUS :: reserved1 [27:25] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_MONITOR_STATUS_reserved1_MASK 0x0e000000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_MONITOR_STATUS_reserved1_SHIFT 25
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_MONITOR_STATUS :: MONITOR_ADJ [24:20] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_MONITOR_STATUS_MONITOR_ADJ_MASK 0x01f00000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_MONITOR_STATUS_MONITOR_ADJ_SHIFT 20
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_MONITOR_STATUS_MONITOR_ADJ_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_MONITOR_STATUS :: MONITOR_CHANGE [19:12] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_MONITOR_STATUS_MONITOR_CHANGE_MASK 0x000ff000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_MONITOR_STATUS_MONITOR_CHANGE_SHIFT 12
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_MONITOR_STATUS_MONITOR_CHANGE_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_MONITOR_STATUS :: reserved2 [11:10] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_MONITOR_STATUS_reserved2_MASK 0x00000c00
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_MONITOR_STATUS_reserved2_SHIFT 10
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_MONITOR_STATUS :: MONITOR_TOTAL [09:00] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_MONITOR_STATUS_MONITOR_TOTAL_MASK 0x000003ff
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_MONITOR_STATUS_MONITOR_TOTAL_SHIFT 0
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_MONITOR_STATUS_MONITOR_TOTAL_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_MONITOR_OVERRIDE - PHY VDL delay monitoring override register
- ***************************************************************************/
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_MONITOR_OVERRIDE :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_MONITOR_OVERRIDE_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_MONITOR_OVERRIDE_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_MONITOR_OVERRIDE_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_MONITOR_OVERRIDE :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_MONITOR_OVERRIDE_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_MONITOR_OVERRIDE_reserved0_SHIFT 17
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_MONITOR_OVERRIDE :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_MONITOR_OVERRIDE_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_MONITOR_OVERRIDE_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_MONITOR_OVERRIDE_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_MONITOR_OVERRIDE :: reserved1 [15:09] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_MONITOR_OVERRIDE_reserved1_MASK 0x0000fe00
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_MONITOR_OVERRIDE_reserved1_SHIFT 9
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_MONITOR_OVERRIDE :: ADJ [08:04] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_MONITOR_OVERRIDE_ADJ_MASK 0x000001f0
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_MONITOR_OVERRIDE_ADJ_SHIFT 4
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_MONITOR_OVERRIDE_ADJ_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_MONITOR_OVERRIDE :: reserved2 [03:01] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_MONITOR_OVERRIDE_reserved2_MASK 0x0000000e
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_MONITOR_OVERRIDE_reserved2_SHIFT 1
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_MONITOR_OVERRIDE :: ENABLE [00:00] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_MONITOR_OVERRIDE_ENABLE_MASK 0x00000001
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_MONITOR_OVERRIDE_ENABLE_SHIFT 0
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_MONITOR_OVERRIDE_ENABLE_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_MONITOR_OUT_CONTROL - PHY VDL delay monitoring output control register
- ***************************************************************************/
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_MONITOR_OUT_CONTROL :: reserved0 [31:20] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_MONITOR_OUT_CONTROL_reserved0_MASK 0xfff00000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_MONITOR_OUT_CONTROL_reserved0_SHIFT 20
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_MONITOR_OUT_CONTROL :: LOWER_LIMIT [19:12] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_MONITOR_OUT_CONTROL_LOWER_LIMIT_MASK 0x000ff000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_MONITOR_OUT_CONTROL_LOWER_LIMIT_SHIFT 12
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_MONITOR_OUT_CONTROL_LOWER_LIMIT_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_MONITOR_OUT_CONTROL :: UPPER_LIMIT [11:04] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_MONITOR_OUT_CONTROL_UPPER_LIMIT_MASK 0x00000ff0
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_MONITOR_OUT_CONTROL_UPPER_LIMIT_SHIFT 4
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_MONITOR_OUT_CONTROL_UPPER_LIMIT_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_MONITOR_OUT_CONTROL :: reserved1 [03:01] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_MONITOR_OUT_CONTROL_reserved1_MASK 0x0000000e
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_MONITOR_OUT_CONTROL_reserved1_SHIFT 1
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_MONITOR_OUT_CONTROL :: ENABLE [00:00] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_MONITOR_OUT_CONTROL_ENABLE_MASK 0x00000001
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_MONITOR_OUT_CONTROL_ENABLE_SHIFT 0
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_MONITOR_OUT_CONTROL_ENABLE_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_MONITOR_OUT_STATUS - PHY VDL delay monitoring output status register
- ***************************************************************************/
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_MONITOR_OUT_STATUS :: reserved0 [31:24] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_MONITOR_OUT_STATUS_reserved0_MASK 0xff000000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_MONITOR_OUT_STATUS_reserved0_SHIFT 24
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_MONITOR_OUT_STATUS :: MONITOR_CHANGE [23:16] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_MONITOR_OUT_STATUS_MONITOR_CHANGE_MASK 0x00ff0000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_MONITOR_OUT_STATUS_MONITOR_CHANGE_SHIFT 16
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_MONITOR_OUT_STATUS_MONITOR_CHANGE_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_MONITOR_OUT_STATUS :: reserved1 [15:14] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_MONITOR_OUT_STATUS_reserved1_MASK 0x0000c000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_MONITOR_OUT_STATUS_reserved1_SHIFT 14
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_MONITOR_OUT_STATUS :: MONITOR_TOTAL [13:04] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_MONITOR_OUT_STATUS_MONITOR_TOTAL_MASK 0x00003ff0
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_MONITOR_OUT_STATUS_MONITOR_TOTAL_SHIFT 4
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_MONITOR_OUT_STATUS_MONITOR_TOTAL_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_MONITOR_OUT_STATUS :: reserved2 [03:01] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_MONITOR_OUT_STATUS_reserved2_MASK 0x0000000e
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_MONITOR_OUT_STATUS_reserved2_SHIFT 1
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_MONITOR_OUT_STATUS :: VALID [00:00] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_MONITOR_OUT_STATUS_VALID_MASK 0x00000001
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_MONITOR_OUT_STATUS_VALID_SHIFT 0
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_MONITOR_OUT_STATUS_VALID_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_MONITOR_OUT_STATUS_CLEAR - PHY VDL delay monitoring output status clear register
- ***************************************************************************/
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_MONITOR_OUT_STATUS_CLEAR :: reserved0 [31:01] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_MONITOR_OUT_STATUS_CLEAR_reserved0_MASK 0xfffffffe
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_MONITOR_OUT_STATUS_CLEAR_reserved0_SHIFT 1
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_MONITOR_OUT_STATUS_CLEAR :: CLEAR [00:00] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_MONITOR_OUT_STATUS_CLEAR_CLEAR_MASK 0x00000001
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_MONITOR_OUT_STATUS_CLEAR_CLEAR_SHIFT 0
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_MONITOR_OUT_STATUS_CLEAR_CLEAR_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_AD00 - DDR interface signal AD[00] VDL control register
- ***************************************************************************/
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_AD00 :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD00_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD00_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD00_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_AD00 :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD00_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD00_reserved0_SHIFT 17
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_AD00 :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD00_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD00_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD00_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_AD00 :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD00_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD00_reserved1_SHIFT 13
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_AD00 :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD00_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD00_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD00_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_AD00 :: reserved2 [11:09] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD00_reserved2_MASK 0x00000e00
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD00_reserved2_SHIFT 9
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_AD00 :: VDL_STEP [08:00] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD00_VDL_STEP_MASK 0x000001ff
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD00_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD00_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_AD01 - DDR interface signal AD[01] VDL control register
- ***************************************************************************/
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_AD01 :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD01_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD01_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD01_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_AD01 :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD01_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD01_reserved0_SHIFT 17
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_AD01 :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD01_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD01_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD01_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_AD01 :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD01_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD01_reserved1_SHIFT 13
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_AD01 :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD01_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD01_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD01_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_AD01 :: reserved2 [11:09] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD01_reserved2_MASK 0x00000e00
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD01_reserved2_SHIFT 9
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_AD01 :: VDL_STEP [08:00] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD01_VDL_STEP_MASK 0x000001ff
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD01_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD01_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_AD02 - DDR interface signal AD[02] VDL control register
- ***************************************************************************/
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_AD02 :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD02_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD02_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD02_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_AD02 :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD02_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD02_reserved0_SHIFT 17
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_AD02 :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD02_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD02_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD02_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_AD02 :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD02_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD02_reserved1_SHIFT 13
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_AD02 :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD02_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD02_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD02_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_AD02 :: reserved2 [11:09] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD02_reserved2_MASK 0x00000e00
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD02_reserved2_SHIFT 9
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_AD02 :: VDL_STEP [08:00] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD02_VDL_STEP_MASK 0x000001ff
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD02_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD02_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_AD03 - DDR interface signal AD[03] VDL control register
- ***************************************************************************/
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_AD03 :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD03_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD03_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD03_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_AD03 :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD03_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD03_reserved0_SHIFT 17
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_AD03 :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD03_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD03_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD03_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_AD03 :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD03_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD03_reserved1_SHIFT 13
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_AD03 :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD03_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD03_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD03_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_AD03 :: reserved2 [11:09] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD03_reserved2_MASK 0x00000e00
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD03_reserved2_SHIFT 9
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_AD03 :: VDL_STEP [08:00] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD03_VDL_STEP_MASK 0x000001ff
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD03_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD03_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_AD04 - DDR interface signal AD[04] VDL control register
- ***************************************************************************/
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_AD04 :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD04_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD04_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD04_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_AD04 :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD04_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD04_reserved0_SHIFT 17
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_AD04 :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD04_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD04_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD04_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_AD04 :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD04_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD04_reserved1_SHIFT 13
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_AD04 :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD04_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD04_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD04_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_AD04 :: reserved2 [11:09] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD04_reserved2_MASK 0x00000e00
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD04_reserved2_SHIFT 9
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_AD04 :: VDL_STEP [08:00] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD04_VDL_STEP_MASK 0x000001ff
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD04_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD04_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_AD05 - DDR interface signal AD[05] VDL control register
- ***************************************************************************/
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_AD05 :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD05_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD05_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD05_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_AD05 :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD05_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD05_reserved0_SHIFT 17
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_AD05 :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD05_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD05_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD05_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_AD05 :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD05_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD05_reserved1_SHIFT 13
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_AD05 :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD05_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD05_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD05_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_AD05 :: reserved2 [11:09] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD05_reserved2_MASK 0x00000e00
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD05_reserved2_SHIFT 9
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_AD05 :: VDL_STEP [08:00] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD05_VDL_STEP_MASK 0x000001ff
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD05_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD05_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_AD06 - DDR interface signal AD[06] VDL control register
- ***************************************************************************/
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_AD06 :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD06_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD06_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD06_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_AD06 :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD06_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD06_reserved0_SHIFT 17
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_AD06 :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD06_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD06_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD06_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_AD06 :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD06_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD06_reserved1_SHIFT 13
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_AD06 :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD06_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD06_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD06_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_AD06 :: reserved2 [11:09] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD06_reserved2_MASK 0x00000e00
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD06_reserved2_SHIFT 9
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_AD06 :: VDL_STEP [08:00] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD06_VDL_STEP_MASK 0x000001ff
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD06_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD06_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_AD07 - DDR interface signal AD[07] VDL control register
- ***************************************************************************/
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_AD07 :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD07_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD07_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD07_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_AD07 :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD07_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD07_reserved0_SHIFT 17
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_AD07 :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD07_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD07_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD07_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_AD07 :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD07_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD07_reserved1_SHIFT 13
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_AD07 :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD07_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD07_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD07_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_AD07 :: reserved2 [11:09] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD07_reserved2_MASK 0x00000e00
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD07_reserved2_SHIFT 9
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_AD07 :: VDL_STEP [08:00] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD07_VDL_STEP_MASK 0x000001ff
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD07_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD07_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_AD08 - DDR interface signal AD[08] VDL control register
- ***************************************************************************/
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_AD08 :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD08_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD08_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD08_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_AD08 :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD08_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD08_reserved0_SHIFT 17
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_AD08 :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD08_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD08_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD08_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_AD08 :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD08_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD08_reserved1_SHIFT 13
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_AD08 :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD08_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD08_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD08_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_AD08 :: reserved2 [11:09] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD08_reserved2_MASK 0x00000e00
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD08_reserved2_SHIFT 9
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_AD08 :: VDL_STEP [08:00] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD08_VDL_STEP_MASK 0x000001ff
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD08_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD08_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_AD09 - DDR interface signal AD[09] VDL control register
- ***************************************************************************/
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_AD09 :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD09_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD09_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD09_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_AD09 :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD09_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD09_reserved0_SHIFT 17
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_AD09 :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD09_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD09_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD09_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_AD09 :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD09_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD09_reserved1_SHIFT 13
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_AD09 :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD09_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD09_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD09_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_AD09 :: reserved2 [11:09] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD09_reserved2_MASK 0x00000e00
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD09_reserved2_SHIFT 9
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_AD09 :: VDL_STEP [08:00] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD09_VDL_STEP_MASK 0x000001ff
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD09_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD09_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_AD10 - DDR interface signal AD[10] VDL control register
- ***************************************************************************/
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_AD10 :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD10_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD10_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD10_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_AD10 :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD10_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD10_reserved0_SHIFT 17
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_AD10 :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD10_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD10_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD10_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_AD10 :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD10_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD10_reserved1_SHIFT 13
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_AD10 :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD10_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD10_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD10_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_AD10 :: reserved2 [11:09] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD10_reserved2_MASK 0x00000e00
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD10_reserved2_SHIFT 9
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_AD10 :: VDL_STEP [08:00] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD10_VDL_STEP_MASK 0x000001ff
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD10_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD10_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_AD11 - DDR interface signal AD[11] VDL control register
- ***************************************************************************/
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_AD11 :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD11_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD11_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD11_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_AD11 :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD11_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD11_reserved0_SHIFT 17
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_AD11 :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD11_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD11_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD11_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_AD11 :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD11_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD11_reserved1_SHIFT 13
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_AD11 :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD11_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD11_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD11_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_AD11 :: reserved2 [11:09] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD11_reserved2_MASK 0x00000e00
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD11_reserved2_SHIFT 9
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_AD11 :: VDL_STEP [08:00] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD11_VDL_STEP_MASK 0x000001ff
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD11_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD11_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_AD12 - DDR interface signal AD[12] VDL control register
- ***************************************************************************/
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_AD12 :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD12_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD12_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD12_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_AD12 :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD12_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD12_reserved0_SHIFT 17
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_AD12 :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD12_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD12_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD12_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_AD12 :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD12_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD12_reserved1_SHIFT 13
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_AD12 :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD12_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD12_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD12_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_AD12 :: reserved2 [11:09] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD12_reserved2_MASK 0x00000e00
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD12_reserved2_SHIFT 9
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_AD12 :: VDL_STEP [08:00] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD12_VDL_STEP_MASK 0x000001ff
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD12_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD12_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_AD13 - DDR interface signal AD[13] VDL control register
- ***************************************************************************/
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_AD13 :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD13_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD13_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD13_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_AD13 :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD13_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD13_reserved0_SHIFT 17
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_AD13 :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD13_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD13_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD13_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_AD13 :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD13_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD13_reserved1_SHIFT 13
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_AD13 :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD13_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD13_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD13_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_AD13 :: reserved2 [11:09] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD13_reserved2_MASK 0x00000e00
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD13_reserved2_SHIFT 9
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_AD13 :: VDL_STEP [08:00] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD13_VDL_STEP_MASK 0x000001ff
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD13_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD13_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_AD14 - DDR interface signal AD[14] VDL control register
- ***************************************************************************/
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_AD14 :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD14_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD14_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD14_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_AD14 :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD14_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD14_reserved0_SHIFT 17
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_AD14 :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD14_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD14_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD14_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_AD14 :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD14_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD14_reserved1_SHIFT 13
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_AD14 :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD14_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD14_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD14_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_AD14 :: reserved2 [11:09] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD14_reserved2_MASK 0x00000e00
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD14_reserved2_SHIFT 9
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_AD14 :: VDL_STEP [08:00] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD14_VDL_STEP_MASK 0x000001ff
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD14_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD14_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_AD15 - DDR interface signal AD[15] VDL control register
- ***************************************************************************/
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_AD15 :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD15_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD15_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD15_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_AD15 :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD15_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD15_reserved0_SHIFT 17
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_AD15 :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD15_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD15_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD15_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_AD15 :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD15_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD15_reserved1_SHIFT 13
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_AD15 :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD15_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD15_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD15_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_AD15 :: reserved2 [11:09] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD15_reserved2_MASK 0x00000e00
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD15_reserved2_SHIFT 9
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_AD15 :: VDL_STEP [08:00] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD15_VDL_STEP_MASK 0x000001ff
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD15_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD15_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_BA0 - DDR interface signal BA[0] VDL control register
- ***************************************************************************/
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_BA0 :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_BA0_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_BA0_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_BA0_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_BA0 :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_BA0_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_BA0_reserved0_SHIFT 17
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_BA0 :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_BA0_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_BA0_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_BA0_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_BA0 :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_BA0_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_BA0_reserved1_SHIFT 13
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_BA0 :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_BA0_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_BA0_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_BA0_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_BA0 :: reserved2 [11:09] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_BA0_reserved2_MASK 0x00000e00
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_BA0_reserved2_SHIFT 9
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_BA0 :: VDL_STEP [08:00] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_BA0_VDL_STEP_MASK 0x000001ff
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_BA0_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_BA0_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_BA1 - DDR interface signal BA[1] VDL control register
- ***************************************************************************/
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_BA1 :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_BA1_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_BA1_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_BA1_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_BA1 :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_BA1_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_BA1_reserved0_SHIFT 17
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_BA1 :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_BA1_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_BA1_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_BA1_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_BA1 :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_BA1_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_BA1_reserved1_SHIFT 13
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_BA1 :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_BA1_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_BA1_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_BA1_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_BA1 :: reserved2 [11:09] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_BA1_reserved2_MASK 0x00000e00
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_BA1_reserved2_SHIFT 9
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_BA1 :: VDL_STEP [08:00] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_BA1_VDL_STEP_MASK 0x000001ff
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_BA1_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_BA1_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_BA2 - DDR interface signal BA[2] VDL control register
- ***************************************************************************/
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_BA2 :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_BA2_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_BA2_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_BA2_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_BA2 :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_BA2_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_BA2_reserved0_SHIFT 17
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_BA2 :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_BA2_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_BA2_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_BA2_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_BA2 :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_BA2_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_BA2_reserved1_SHIFT 13
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_BA2 :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_BA2_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_BA2_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_BA2_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_BA2 :: reserved2 [11:09] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_BA2_reserved2_MASK 0x00000e00
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_BA2_reserved2_SHIFT 9
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_BA2 :: VDL_STEP [08:00] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_BA2_VDL_STEP_MASK 0x000001ff
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_BA2_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_BA2_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_AUX0 - DDR interface signal AUX[0] VDL control register
- ***************************************************************************/
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_AUX0 :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AUX0_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AUX0_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AUX0_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_AUX0 :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AUX0_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AUX0_reserved0_SHIFT 17
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_AUX0 :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AUX0_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AUX0_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AUX0_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_AUX0 :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AUX0_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AUX0_reserved1_SHIFT 13
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_AUX0 :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AUX0_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AUX0_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AUX0_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_AUX0 :: reserved2 [11:09] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AUX0_reserved2_MASK 0x00000e00
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AUX0_reserved2_SHIFT 9
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_AUX0 :: VDL_STEP [08:00] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AUX0_VDL_STEP_MASK 0x000001ff
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AUX0_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AUX0_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_AUX1 - DDR interface signal AUX[1] VDL control register
- ***************************************************************************/
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_AUX1 :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AUX1_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AUX1_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AUX1_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_AUX1 :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AUX1_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AUX1_reserved0_SHIFT 17
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_AUX1 :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AUX1_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AUX1_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AUX1_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_AUX1 :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AUX1_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AUX1_reserved1_SHIFT 13
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_AUX1 :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AUX1_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AUX1_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AUX1_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_AUX1 :: reserved2 [11:09] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AUX1_reserved2_MASK 0x00000e00
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AUX1_reserved2_SHIFT 9
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_AUX1 :: VDL_STEP [08:00] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AUX1_VDL_STEP_MASK 0x000001ff
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AUX1_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AUX1_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_AUX2 - DDR interface signal AUX[2] VDL control register
- ***************************************************************************/
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_AUX2 :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AUX2_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AUX2_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AUX2_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_AUX2 :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AUX2_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AUX2_reserved0_SHIFT 17
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_AUX2 :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AUX2_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AUX2_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AUX2_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_AUX2 :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AUX2_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AUX2_reserved1_SHIFT 13
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_AUX2 :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AUX2_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AUX2_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AUX2_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_AUX2 :: reserved2 [11:09] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AUX2_reserved2_MASK 0x00000e00
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AUX2_reserved2_SHIFT 9
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_AUX2 :: VDL_STEP [08:00] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AUX2_VDL_STEP_MASK 0x000001ff
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AUX2_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AUX2_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_CS0 - DDR interface signal CS0 VDL control register
- ***************************************************************************/
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_CS0 :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_CS0_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_CS0_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_CS0_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_CS0 :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_CS0_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_CS0_reserved0_SHIFT 17
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_CS0 :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_CS0_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_CS0_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_CS0_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_CS0 :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_CS0_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_CS0_reserved1_SHIFT 13
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_CS0 :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_CS0_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_CS0_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_CS0_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_CS0 :: reserved2 [11:09] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_CS0_reserved2_MASK 0x00000e00
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_CS0_reserved2_SHIFT 9
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_CS0 :: VDL_STEP [08:00] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_CS0_VDL_STEP_MASK 0x000001ff
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_CS0_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_CS0_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_CS1 - DDR interface signal CS1 VDL control register
- ***************************************************************************/
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_CS1 :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_CS1_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_CS1_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_CS1_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_CS1 :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_CS1_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_CS1_reserved0_SHIFT 17
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_CS1 :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_CS1_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_CS1_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_CS1_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_CS1 :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_CS1_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_CS1_reserved1_SHIFT 13
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_CS1 :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_CS1_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_CS1_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_CS1_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_CS1 :: reserved2 [11:09] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_CS1_reserved2_MASK 0x00000e00
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_CS1_reserved2_SHIFT 9
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_CS1 :: VDL_STEP [08:00] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_CS1_VDL_STEP_MASK 0x000001ff
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_CS1_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_CS1_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_PAR - DDR interface signal PAR VDL control register
- ***************************************************************************/
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_PAR :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_PAR_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_PAR_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_PAR_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_PAR :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_PAR_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_PAR_reserved0_SHIFT 17
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_PAR :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_PAR_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_PAR_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_PAR_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_PAR :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_PAR_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_PAR_reserved1_SHIFT 13
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_PAR :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_PAR_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_PAR_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_PAR_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_PAR :: reserved2 [11:09] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_PAR_reserved2_MASK 0x00000e00
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_PAR_reserved2_SHIFT 9
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_PAR :: VDL_STEP [08:00] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_PAR_VDL_STEP_MASK 0x000001ff
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_PAR_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_PAR_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_RAS_N - DDR interface signal RAS_N VDL control register
- ***************************************************************************/
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_RAS_N :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_RAS_N_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_RAS_N_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_RAS_N_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_RAS_N :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_RAS_N_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_RAS_N_reserved0_SHIFT 17
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_RAS_N :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_RAS_N_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_RAS_N_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_RAS_N_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_RAS_N :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_RAS_N_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_RAS_N_reserved1_SHIFT 13
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_RAS_N :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_RAS_N_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_RAS_N_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_RAS_N_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_RAS_N :: reserved2 [11:09] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_RAS_N_reserved2_MASK 0x00000e00
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_RAS_N_reserved2_SHIFT 9
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_RAS_N :: VDL_STEP [08:00] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_RAS_N_VDL_STEP_MASK 0x000001ff
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_RAS_N_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_RAS_N_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_CAS_N - DDR interface signal CAS_N VDL control register
- ***************************************************************************/
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_CAS_N :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_CAS_N_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_CAS_N_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_CAS_N_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_CAS_N :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_CAS_N_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_CAS_N_reserved0_SHIFT 17
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_CAS_N :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_CAS_N_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_CAS_N_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_CAS_N_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_CAS_N :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_CAS_N_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_CAS_N_reserved1_SHIFT 13
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_CAS_N :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_CAS_N_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_CAS_N_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_CAS_N_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_CAS_N :: reserved2 [11:09] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_CAS_N_reserved2_MASK 0x00000e00
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_CAS_N_reserved2_SHIFT 9
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_CAS_N :: VDL_STEP [08:00] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_CAS_N_VDL_STEP_MASK 0x000001ff
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_CAS_N_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_CAS_N_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_CKE - DDR interface signal CKE0 VDL control register
- ***************************************************************************/
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_CKE :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_CKE_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_CKE_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_CKE_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_CKE :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_CKE_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_CKE_reserved0_SHIFT 17
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_CKE :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_CKE_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_CKE_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_CKE_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_CKE :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_CKE_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_CKE_reserved1_SHIFT 13
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_CKE :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_CKE_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_CKE_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_CKE_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_CKE :: reserved2 [11:09] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_CKE_reserved2_MASK 0x00000e00
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_CKE_reserved2_SHIFT 9
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_CKE :: VDL_STEP [08:00] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_CKE_VDL_STEP_MASK 0x000001ff
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_CKE_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_CKE_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_RST_N - DDR interface signal RST_N VDL control register
- ***************************************************************************/
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_RST_N :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_RST_N_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_RST_N_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_RST_N_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_RST_N :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_RST_N_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_RST_N_reserved0_SHIFT 17
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_RST_N :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_RST_N_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_RST_N_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_RST_N_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_RST_N :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_RST_N_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_RST_N_reserved1_SHIFT 13
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_RST_N :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_RST_N_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_RST_N_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_RST_N_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_RST_N :: reserved2 [11:09] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_RST_N_reserved2_MASK 0x00000e00
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_RST_N_reserved2_SHIFT 9
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_RST_N :: VDL_STEP [08:00] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_RST_N_VDL_STEP_MASK 0x000001ff
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_RST_N_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_RST_N_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_ODT - DDR interface signal ODT0 VDL control register
- ***************************************************************************/
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_ODT :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_ODT_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_ODT_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_ODT_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_ODT :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_ODT_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_ODT_reserved0_SHIFT 17
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_ODT :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_ODT_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_ODT_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_ODT_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_ODT :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_ODT_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_ODT_reserved1_SHIFT 13
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_ODT :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_ODT_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_ODT_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_ODT_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_ODT :: reserved2 [11:09] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_ODT_reserved2_MASK 0x00000e00
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_ODT_reserved2_SHIFT 9
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_ODT :: VDL_STEP [08:00] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_ODT_VDL_STEP_MASK 0x000001ff
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_ODT_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_ODT_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_WE_N - DDR interface signal WE_N VDL control register
- ***************************************************************************/
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_WE_N :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_WE_N_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_WE_N_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_WE_N_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_WE_N :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_WE_N_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_WE_N_reserved0_SHIFT 17
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_WE_N :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_WE_N_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_WE_N_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_WE_N_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_WE_N :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_WE_N_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_WE_N_reserved1_SHIFT 13
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_WE_N :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_WE_N_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_WE_N_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_WE_N_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_WE_N :: reserved2 [11:09] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_WE_N_reserved2_MASK 0x00000e00
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_WE_N_reserved2_SHIFT 9
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_WE_N :: VDL_STEP [08:00] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_WE_N_VDL_STEP_MASK 0x000001ff
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_WE_N_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_WE_N_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_DDR_CK_P - DDR interface signal DDR_CK-P VDL control register
- ***************************************************************************/
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_DDR_CK_P :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_DDR_CK_P_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_DDR_CK_P_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_DDR_CK_P_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_DDR_CK_P :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_DDR_CK_P_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_DDR_CK_P_reserved0_SHIFT 17
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_DDR_CK_P :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_DDR_CK_P_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_DDR_CK_P_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_DDR_CK_P_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_DDR_CK_P :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_DDR_CK_P_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_DDR_CK_P_reserved1_SHIFT 13
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_DDR_CK_P :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_DDR_CK_P_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_DDR_CK_P_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_DDR_CK_P_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_DDR_CK_P :: reserved2 [11:09] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_DDR_CK_P_reserved2_MASK 0x00000e00
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_DDR_CK_P_reserved2_SHIFT 9
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_DDR_CK_P :: VDL_STEP [08:00] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_DDR_CK_P_VDL_STEP_MASK 0x000001ff
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_DDR_CK_P_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_DDR_CK_P_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_DDR_CK_N - DDR interface signal DDR_CK-N VDL control register
- ***************************************************************************/
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_DDR_CK_N :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_DDR_CK_N_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_DDR_CK_N_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_DDR_CK_N_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_DDR_CK_N :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_DDR_CK_N_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_DDR_CK_N_reserved0_SHIFT 17
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_DDR_CK_N :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_DDR_CK_N_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_DDR_CK_N_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_DDR_CK_N_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_DDR_CK_N :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_DDR_CK_N_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_DDR_CK_N_reserved1_SHIFT 13
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_DDR_CK_N :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_DDR_CK_N_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_DDR_CK_N_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_DDR_CK_N_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_DDR_CK_N :: reserved2 [11:09] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_DDR_CK_N_reserved2_MASK 0x00000e00
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_DDR_CK_N_reserved2_SHIFT 9
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_DDR_CK_N :: VDL_STEP [08:00] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_DDR_CK_N_VDL_STEP_MASK 0x000001ff
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_DDR_CK_N_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_DDR_CK_N_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CLK_CONTROL - DDR interface signal Write Leveling CLK VDL control register
- ***************************************************************************/
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CLK_CONTROL :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CLK_CONTROL_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CLK_CONTROL_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CLK_CONTROL_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CLK_CONTROL :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CLK_CONTROL_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CLK_CONTROL_reserved0_SHIFT 17
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CLK_CONTROL :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CLK_CONTROL_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CLK_CONTROL_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CLK_CONTROL_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CLK_CONTROL :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CLK_CONTROL_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CLK_CONTROL_reserved1_SHIFT 13
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CLK_CONTROL :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CLK_CONTROL_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CLK_CONTROL_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CLK_CONTROL_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CLK_CONTROL :: reserved2 [11:09] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CLK_CONTROL_reserved2_MASK 0x00000e00
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CLK_CONTROL_reserved2_SHIFT 9
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CLK_CONTROL :: VDL_STEP [08:00] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CLK_CONTROL_VDL_STEP_MASK 0x000001ff
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CLK_CONTROL_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CLK_CONTROL_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_LDE_CONTROL - DDR interface signal Write Leveling Capture Enable VDL control register
- ***************************************************************************/
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_LDE_CONTROL :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_LDE_CONTROL_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_LDE_CONTROL_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_LDE_CONTROL_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_LDE_CONTROL :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_LDE_CONTROL_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_LDE_CONTROL_reserved0_SHIFT 17
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_LDE_CONTROL :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_LDE_CONTROL_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_LDE_CONTROL_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_LDE_CONTROL_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_LDE_CONTROL :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_LDE_CONTROL_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_LDE_CONTROL_reserved1_SHIFT 13
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_LDE_CONTROL :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_LDE_CONTROL_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_LDE_CONTROL_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_LDE_CONTROL_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_LDE_CONTROL :: reserved2 [11:09] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_LDE_CONTROL_reserved2_MASK 0x00000e00
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_LDE_CONTROL_reserved2_SHIFT 9
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_LDE_CONTROL :: VDL_STEP [08:00] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_LDE_CONTROL_VDL_STEP_MASK 0x000001ff
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_LDE_CONTROL_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_LDE_CONTROL_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *REFRESH - Refresh engine controller
- ***************************************************************************/
-/* DDR34_PHY_CONTROL_REGS_0 :: REFRESH :: reserved0 [31:17] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_REFRESH_reserved0_MASK 0xfffe0000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_REFRESH_reserved0_SHIFT 17
-
-/* DDR34_PHY_CONTROL_REGS_0 :: REFRESH :: ENABLE [16:16] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_REFRESH_ENABLE_MASK 0x00010000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_REFRESH_ENABLE_SHIFT 16
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_REFRESH_ENABLE_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: REFRESH :: PERIOD [15:00] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_REFRESH_PERIOD_MASK 0x0000ffff
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_REFRESH_PERIOD_SHIFT 0
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_REFRESH_PERIOD_DEFAULT 0x00000000
-
-/***************************************************************************
- *UPDATE_VDL - Update VDL control register
- ***************************************************************************/
-/* DDR34_PHY_CONTROL_REGS_0 :: UPDATE_VDL :: reserved0 [31:06] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_UPDATE_VDL_reserved0_MASK 0xffffffc0
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_UPDATE_VDL_reserved0_SHIFT 6
-
-/* DDR34_PHY_CONTROL_REGS_0 :: UPDATE_VDL :: MODE [05:04] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_UPDATE_VDL_MODE_MASK 0x00000030
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_UPDATE_VDL_MODE_SHIFT 4
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_UPDATE_VDL_MODE_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: UPDATE_VDL :: reserved1 [03:02] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_UPDATE_VDL_reserved1_MASK 0x0000000c
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_UPDATE_VDL_reserved1_SHIFT 2
-
-/* DDR34_PHY_CONTROL_REGS_0 :: UPDATE_VDL :: DISABLE_INPUT [01:01] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_UPDATE_VDL_DISABLE_INPUT_MASK 0x00000002
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_UPDATE_VDL_DISABLE_INPUT_SHIFT 1
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_UPDATE_VDL_DISABLE_INPUT_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: UPDATE_VDL :: ENABLE [00:00] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_UPDATE_VDL_ENABLE_MASK 0x00000001
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_UPDATE_VDL_ENABLE_SHIFT 0
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_UPDATE_VDL_ENABLE_DEFAULT 0x00000000
-
-/***************************************************************************
- *UPDATE_VDL_SNOOP1 - Update VDL snoop control register #1
- ***************************************************************************/
-/* DDR34_PHY_CONTROL_REGS_0 :: UPDATE_VDL_SNOOP1 :: reserved0 [31:30] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_UPDATE_VDL_SNOOP1_reserved0_MASK 0xc0000000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_UPDATE_VDL_SNOOP1_reserved0_SHIFT 30
-
-/* DDR34_PHY_CONTROL_REGS_0 :: UPDATE_VDL_SNOOP1 :: MODE [29:28] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_UPDATE_VDL_SNOOP1_MODE_MASK 0x30000000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_UPDATE_VDL_SNOOP1_MODE_SHIFT 28
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_UPDATE_VDL_SNOOP1_MODE_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: UPDATE_VDL_SNOOP1 :: reserved1 [27:27] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_UPDATE_VDL_SNOOP1_reserved1_MASK 0x08000000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_UPDATE_VDL_SNOOP1_reserved1_SHIFT 27
-
-/* DDR34_PHY_CONTROL_REGS_0 :: UPDATE_VDL_SNOOP1 :: MASK [26:16] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_UPDATE_VDL_SNOOP1_MASK_MASK 0x07ff0000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_UPDATE_VDL_SNOOP1_MASK_SHIFT 16
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_UPDATE_VDL_SNOOP1_MASK_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: UPDATE_VDL_SNOOP1 :: reserved2 [15:15] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_UPDATE_VDL_SNOOP1_reserved2_MASK 0x00008000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_UPDATE_VDL_SNOOP1_reserved2_SHIFT 15
-
-/* DDR34_PHY_CONTROL_REGS_0 :: UPDATE_VDL_SNOOP1 :: CMD [14:04] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_UPDATE_VDL_SNOOP1_CMD_MASK 0x00007ff0
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_UPDATE_VDL_SNOOP1_CMD_SHIFT 4
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_UPDATE_VDL_SNOOP1_CMD_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: UPDATE_VDL_SNOOP1 :: reserved3 [03:01] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_UPDATE_VDL_SNOOP1_reserved3_MASK 0x0000000e
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_UPDATE_VDL_SNOOP1_reserved3_SHIFT 1
-
-/* DDR34_PHY_CONTROL_REGS_0 :: UPDATE_VDL_SNOOP1 :: ENABLE [00:00] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_UPDATE_VDL_SNOOP1_ENABLE_MASK 0x00000001
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_UPDATE_VDL_SNOOP1_ENABLE_SHIFT 0
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_UPDATE_VDL_SNOOP1_ENABLE_DEFAULT 0x00000000
-
-/***************************************************************************
- *UPDATE_VDL_SNOOP2 - Update VDL snoop control register #2
- ***************************************************************************/
-/* DDR34_PHY_CONTROL_REGS_0 :: UPDATE_VDL_SNOOP2 :: reserved0 [31:30] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_UPDATE_VDL_SNOOP2_reserved0_MASK 0xc0000000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_UPDATE_VDL_SNOOP2_reserved0_SHIFT 30
-
-/* DDR34_PHY_CONTROL_REGS_0 :: UPDATE_VDL_SNOOP2 :: MODE [29:28] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_UPDATE_VDL_SNOOP2_MODE_MASK 0x30000000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_UPDATE_VDL_SNOOP2_MODE_SHIFT 28
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_UPDATE_VDL_SNOOP2_MODE_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: UPDATE_VDL_SNOOP2 :: reserved1 [27:27] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_UPDATE_VDL_SNOOP2_reserved1_MASK 0x08000000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_UPDATE_VDL_SNOOP2_reserved1_SHIFT 27
-
-/* DDR34_PHY_CONTROL_REGS_0 :: UPDATE_VDL_SNOOP2 :: MASK [26:16] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_UPDATE_VDL_SNOOP2_MASK_MASK 0x07ff0000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_UPDATE_VDL_SNOOP2_MASK_SHIFT 16
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_UPDATE_VDL_SNOOP2_MASK_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: UPDATE_VDL_SNOOP2 :: reserved2 [15:15] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_UPDATE_VDL_SNOOP2_reserved2_MASK 0x00008000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_UPDATE_VDL_SNOOP2_reserved2_SHIFT 15
-
-/* DDR34_PHY_CONTROL_REGS_0 :: UPDATE_VDL_SNOOP2 :: CMD [14:04] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_UPDATE_VDL_SNOOP2_CMD_MASK 0x00007ff0
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_UPDATE_VDL_SNOOP2_CMD_SHIFT 4
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_UPDATE_VDL_SNOOP2_CMD_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: UPDATE_VDL_SNOOP2 :: reserved3 [03:01] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_UPDATE_VDL_SNOOP2_reserved3_MASK 0x0000000e
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_UPDATE_VDL_SNOOP2_reserved3_SHIFT 1
-
-/* DDR34_PHY_CONTROL_REGS_0 :: UPDATE_VDL_SNOOP2 :: ENABLE [00:00] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_UPDATE_VDL_SNOOP2_ENABLE_MASK 0x00000001
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_UPDATE_VDL_SNOOP2_ENABLE_SHIFT 0
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_UPDATE_VDL_SNOOP2_ENABLE_DEFAULT 0x00000000
-
-/***************************************************************************
- *COMMAND_REG1 - DRAM Command Register #1
- ***************************************************************************/
-/* DDR34_PHY_CONTROL_REGS_0 :: COMMAND_REG1 :: MCP [31:31] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_REG1_MCP_MASK 0x80000000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_REG1_MCP_SHIFT 31
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_REG1_MCP_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: COMMAND_REG1 :: CS [30:29] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_REG1_CS_MASK 0x60000000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_REG1_CS_SHIFT 29
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_REG1_CS_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: COMMAND_REG1 :: AUX [28:24] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_REG1_AUX_MASK 0x1f000000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_REG1_AUX_SHIFT 24
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_REG1_AUX_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: COMMAND_REG1 :: ACT [23:23] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_REG1_ACT_MASK 0x00800000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_REG1_ACT_SHIFT 23
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_REG1_ACT_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: COMMAND_REG1 :: WE [22:22] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_REG1_WE_MASK 0x00400000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_REG1_WE_SHIFT 22
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_REG1_WE_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: COMMAND_REG1 :: CAS [21:21] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_REG1_CAS_MASK 0x00200000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_REG1_CAS_SHIFT 21
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_REG1_CAS_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: COMMAND_REG1 :: RAS [20:20] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_REG1_RAS_MASK 0x00100000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_REG1_RAS_SHIFT 20
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_REG1_RAS_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: COMMAND_REG1 :: BA [19:16] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_REG1_BA_MASK 0x000f0000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_REG1_BA_SHIFT 16
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_REG1_BA_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: COMMAND_REG1 :: AD [15:00] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_REG1_AD_MASK 0x0000ffff
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_REG1_AD_SHIFT 0
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_REG1_AD_DEFAULT 0x00000000
-
-/***************************************************************************
- *COMMAND_AUX_REG1 - DRAM AUX_N Command Register #1
- ***************************************************************************/
-/* DDR34_PHY_CONTROL_REGS_0 :: COMMAND_AUX_REG1 :: reserved0 [31:05] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_AUX_REG1_reserved0_MASK 0xffffffe0
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_AUX_REG1_reserved0_SHIFT 5
-
-/* DDR34_PHY_CONTROL_REGS_0 :: COMMAND_AUX_REG1 :: AUX [04:00] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_AUX_REG1_AUX_MASK 0x0000001f
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_AUX_REG1_AUX_SHIFT 0
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_AUX_REG1_AUX_DEFAULT 0x00000000
-
-/***************************************************************************
- *COMMAND_REG2 - DRAM Command Register #2
- ***************************************************************************/
-/* DDR34_PHY_CONTROL_REGS_0 :: COMMAND_REG2 :: MCP [31:31] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_REG2_MCP_MASK 0x80000000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_REG2_MCP_SHIFT 31
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_REG2_MCP_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: COMMAND_REG2 :: CS [30:29] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_REG2_CS_MASK 0x60000000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_REG2_CS_SHIFT 29
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_REG2_CS_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: COMMAND_REG2 :: AUX [28:24] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_REG2_AUX_MASK 0x1f000000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_REG2_AUX_SHIFT 24
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_REG2_AUX_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: COMMAND_REG2 :: ACT [23:23] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_REG2_ACT_MASK 0x00800000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_REG2_ACT_SHIFT 23
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_REG2_ACT_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: COMMAND_REG2 :: WE [22:22] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_REG2_WE_MASK 0x00400000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_REG2_WE_SHIFT 22
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_REG2_WE_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: COMMAND_REG2 :: CAS [21:21] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_REG2_CAS_MASK 0x00200000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_REG2_CAS_SHIFT 21
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_REG2_CAS_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: COMMAND_REG2 :: RAS [20:20] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_REG2_RAS_MASK 0x00100000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_REG2_RAS_SHIFT 20
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_REG2_RAS_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: COMMAND_REG2 :: BA [19:16] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_REG2_BA_MASK 0x000f0000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_REG2_BA_SHIFT 16
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_REG2_BA_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: COMMAND_REG2 :: AD [15:00] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_REG2_AD_MASK 0x0000ffff
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_REG2_AD_SHIFT 0
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_REG2_AD_DEFAULT 0x00000000
-
-/***************************************************************************
- *COMMAND_AUX_REG2 - DRAM AUX_N Command Register #2
- ***************************************************************************/
-/* DDR34_PHY_CONTROL_REGS_0 :: COMMAND_AUX_REG2 :: reserved0 [31:05] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_AUX_REG2_reserved0_MASK 0xffffffe0
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_AUX_REG2_reserved0_SHIFT 5
-
-/* DDR34_PHY_CONTROL_REGS_0 :: COMMAND_AUX_REG2 :: AUX [04:00] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_AUX_REG2_AUX_MASK 0x0000001f
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_AUX_REG2_AUX_SHIFT 0
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_AUX_REG2_AUX_DEFAULT 0x00000000
-
-/***************************************************************************
- *COMMAND_REG3 - DRAM Command Register #3
- ***************************************************************************/
-/* DDR34_PHY_CONTROL_REGS_0 :: COMMAND_REG3 :: MCP [31:31] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_REG3_MCP_MASK 0x80000000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_REG3_MCP_SHIFT 31
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_REG3_MCP_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: COMMAND_REG3 :: CS [30:29] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_REG3_CS_MASK 0x60000000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_REG3_CS_SHIFT 29
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_REG3_CS_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: COMMAND_REG3 :: AUX [28:24] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_REG3_AUX_MASK 0x1f000000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_REG3_AUX_SHIFT 24
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_REG3_AUX_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: COMMAND_REG3 :: ACT [23:23] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_REG3_ACT_MASK 0x00800000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_REG3_ACT_SHIFT 23
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_REG3_ACT_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: COMMAND_REG3 :: WE [22:22] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_REG3_WE_MASK 0x00400000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_REG3_WE_SHIFT 22
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_REG3_WE_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: COMMAND_REG3 :: CAS [21:21] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_REG3_CAS_MASK 0x00200000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_REG3_CAS_SHIFT 21
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_REG3_CAS_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: COMMAND_REG3 :: RAS [20:20] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_REG3_RAS_MASK 0x00100000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_REG3_RAS_SHIFT 20
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_REG3_RAS_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: COMMAND_REG3 :: BA [19:16] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_REG3_BA_MASK 0x000f0000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_REG3_BA_SHIFT 16
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_REG3_BA_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: COMMAND_REG3 :: AD [15:00] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_REG3_AD_MASK 0x0000ffff
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_REG3_AD_SHIFT 0
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_REG3_AD_DEFAULT 0x00000000
-
-/***************************************************************************
- *COMMAND_AUX_REG3 - DRAM AUX_N Command Register #3
- ***************************************************************************/
-/* DDR34_PHY_CONTROL_REGS_0 :: COMMAND_AUX_REG3 :: reserved0 [31:05] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_AUX_REG3_reserved0_MASK 0xffffffe0
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_AUX_REG3_reserved0_SHIFT 5
-
-/* DDR34_PHY_CONTROL_REGS_0 :: COMMAND_AUX_REG3 :: AUX [04:00] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_AUX_REG3_AUX_MASK 0x0000001f
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_AUX_REG3_AUX_SHIFT 0
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_AUX_REG3_AUX_DEFAULT 0x00000000
-
-/***************************************************************************
- *COMMAND_REG4 - DRAM Command Register #4
- ***************************************************************************/
-/* DDR34_PHY_CONTROL_REGS_0 :: COMMAND_REG4 :: MCP [31:31] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_REG4_MCP_MASK 0x80000000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_REG4_MCP_SHIFT 31
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_REG4_MCP_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: COMMAND_REG4 :: CS [30:29] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_REG4_CS_MASK 0x60000000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_REG4_CS_SHIFT 29
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_REG4_CS_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: COMMAND_REG4 :: AUX [28:24] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_REG4_AUX_MASK 0x1f000000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_REG4_AUX_SHIFT 24
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_REG4_AUX_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: COMMAND_REG4 :: ACT [23:23] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_REG4_ACT_MASK 0x00800000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_REG4_ACT_SHIFT 23
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_REG4_ACT_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: COMMAND_REG4 :: WE [22:22] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_REG4_WE_MASK 0x00400000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_REG4_WE_SHIFT 22
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_REG4_WE_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: COMMAND_REG4 :: CAS [21:21] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_REG4_CAS_MASK 0x00200000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_REG4_CAS_SHIFT 21
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_REG4_CAS_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: COMMAND_REG4 :: RAS [20:20] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_REG4_RAS_MASK 0x00100000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_REG4_RAS_SHIFT 20
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_REG4_RAS_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: COMMAND_REG4 :: BA [19:16] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_REG4_BA_MASK 0x000f0000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_REG4_BA_SHIFT 16
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_REG4_BA_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: COMMAND_REG4 :: AD [15:00] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_REG4_AD_MASK 0x0000ffff
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_REG4_AD_SHIFT 0
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_REG4_AD_DEFAULT 0x00000000
-
-/***************************************************************************
- *COMMAND_AUX_REG4 - DRAM AUX_N Command Register #4
- ***************************************************************************/
-/* DDR34_PHY_CONTROL_REGS_0 :: COMMAND_AUX_REG4 :: reserved0 [31:05] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_AUX_REG4_reserved0_MASK 0xffffffe0
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_AUX_REG4_reserved0_SHIFT 5
-
-/* DDR34_PHY_CONTROL_REGS_0 :: COMMAND_AUX_REG4 :: AUX [04:00] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_AUX_REG4_AUX_MASK 0x0000001f
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_AUX_REG4_AUX_SHIFT 0
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_AUX_REG4_AUX_DEFAULT 0x00000000
-
-/***************************************************************************
- *COMMAND_REG_TIMER - DRAM Command Timer Register
- ***************************************************************************/
-/* DDR34_PHY_CONTROL_REGS_0 :: COMMAND_REG_TIMER :: reserved0 [31:16] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_REG_TIMER_reserved0_MASK 0xffff0000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_REG_TIMER_reserved0_SHIFT 16
-
-/* DDR34_PHY_CONTROL_REGS_0 :: COMMAND_REG_TIMER :: INIT_VAL [15:08] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_REG_TIMER_INIT_VAL_MASK 0x0000ff00
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_REG_TIMER_INIT_VAL_SHIFT 8
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_REG_TIMER_INIT_VAL_DEFAULT 0x0000000f
-
-/* DDR34_PHY_CONTROL_REGS_0 :: COMMAND_REG_TIMER :: COUNT [07:00] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_REG_TIMER_COUNT_MASK 0x000000ff
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_REG_TIMER_COUNT_SHIFT 0
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_REG_TIMER_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *MODE_REG0 - DDR3/DDR4/GDDR5 Mode Register 0 and LPDDR Mode Register 1
- ***************************************************************************/
-/* DDR34_PHY_CONTROL_REGS_0 :: MODE_REG0 :: reserved0 [31:21] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_MODE_REG0_reserved0_MASK 0xffe00000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_MODE_REG0_reserved0_SHIFT 21
-
-/* DDR34_PHY_CONTROL_REGS_0 :: MODE_REG0 :: reserved_for_eco1 [20:17] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_MODE_REG0_reserved_for_eco1_MASK 0x001e0000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_MODE_REG0_reserved_for_eco1_SHIFT 17
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_MODE_REG0_reserved_for_eco1_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: MODE_REG0 :: VALID [16:16] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_MODE_REG0_VALID_MASK 0x00010000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_MODE_REG0_VALID_SHIFT 16
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_MODE_REG0_VALID_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: MODE_REG0 :: AD [15:00] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_MODE_REG0_AD_MASK 0x0000ffff
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_MODE_REG0_AD_SHIFT 0
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_MODE_REG0_AD_DEFAULT 0x00000000
-
-/***************************************************************************
- *MODE_REG1 - DDR3/DDR4/GDDR5 Mode Register 1 and LPDDR Mode Register 2
- ***************************************************************************/
-/* DDR34_PHY_CONTROL_REGS_0 :: MODE_REG1 :: reserved0 [31:21] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_MODE_REG1_reserved0_MASK 0xffe00000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_MODE_REG1_reserved0_SHIFT 21
-
-/* DDR34_PHY_CONTROL_REGS_0 :: MODE_REG1 :: reserved_for_eco1 [20:17] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_MODE_REG1_reserved_for_eco1_MASK 0x001e0000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_MODE_REG1_reserved_for_eco1_SHIFT 17
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_MODE_REG1_reserved_for_eco1_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: MODE_REG1 :: VALID [16:16] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_MODE_REG1_VALID_MASK 0x00010000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_MODE_REG1_VALID_SHIFT 16
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_MODE_REG1_VALID_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: MODE_REG1 :: AD [15:00] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_MODE_REG1_AD_MASK 0x0000ffff
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_MODE_REG1_AD_SHIFT 0
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_MODE_REG1_AD_DEFAULT 0x00000000
-
-/***************************************************************************
- *MODE_REG2 - DDR3/DDR4/GDDR5 Mode Register 2 and LPDDR Mode Register 3
- ***************************************************************************/
-/* DDR34_PHY_CONTROL_REGS_0 :: MODE_REG2 :: reserved0 [31:21] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_MODE_REG2_reserved0_MASK 0xffe00000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_MODE_REG2_reserved0_SHIFT 21
-
-/* DDR34_PHY_CONTROL_REGS_0 :: MODE_REG2 :: reserved_for_eco1 [20:17] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_MODE_REG2_reserved_for_eco1_MASK 0x001e0000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_MODE_REG2_reserved_for_eco1_SHIFT 17
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_MODE_REG2_reserved_for_eco1_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: MODE_REG2 :: VALID [16:16] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_MODE_REG2_VALID_MASK 0x00010000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_MODE_REG2_VALID_SHIFT 16
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_MODE_REG2_VALID_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: MODE_REG2 :: AD [15:00] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_MODE_REG2_AD_MASK 0x0000ffff
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_MODE_REG2_AD_SHIFT 0
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_MODE_REG2_AD_DEFAULT 0x00000000
-
-/***************************************************************************
- *MODE_REG3 - DDR3/DDR4/GDDR5 Mode Register 3 and LPDDR Mode Register 9
- ***************************************************************************/
-/* DDR34_PHY_CONTROL_REGS_0 :: MODE_REG3 :: reserved0 [31:21] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_MODE_REG3_reserved0_MASK 0xffe00000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_MODE_REG3_reserved0_SHIFT 21
-
-/* DDR34_PHY_CONTROL_REGS_0 :: MODE_REG3 :: reserved_for_eco1 [20:17] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_MODE_REG3_reserved_for_eco1_MASK 0x001e0000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_MODE_REG3_reserved_for_eco1_SHIFT 17
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_MODE_REG3_reserved_for_eco1_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: MODE_REG3 :: VALID [16:16] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_MODE_REG3_VALID_MASK 0x00010000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_MODE_REG3_VALID_SHIFT 16
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_MODE_REG3_VALID_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: MODE_REG3 :: AD [15:00] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_MODE_REG3_AD_MASK 0x0000ffff
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_MODE_REG3_AD_SHIFT 0
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_MODE_REG3_AD_DEFAULT 0x00000000
-
-/***************************************************************************
- *MODE_REG4 - DDR4/GDDR5 Mode Register 4 and LPDDR Mode Register 10
- ***************************************************************************/
-/* DDR34_PHY_CONTROL_REGS_0 :: MODE_REG4 :: reserved0 [31:21] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_MODE_REG4_reserved0_MASK 0xffe00000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_MODE_REG4_reserved0_SHIFT 21
-
-/* DDR34_PHY_CONTROL_REGS_0 :: MODE_REG4 :: reserved_for_eco1 [20:17] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_MODE_REG4_reserved_for_eco1_MASK 0x001e0000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_MODE_REG4_reserved_for_eco1_SHIFT 17
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_MODE_REG4_reserved_for_eco1_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: MODE_REG4 :: VALID [16:16] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_MODE_REG4_VALID_MASK 0x00010000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_MODE_REG4_VALID_SHIFT 16
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_MODE_REG4_VALID_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: MODE_REG4 :: AD [15:00] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_MODE_REG4_AD_MASK 0x0000ffff
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_MODE_REG4_AD_SHIFT 0
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_MODE_REG4_AD_DEFAULT 0x00000000
-
-/***************************************************************************
- *MODE_REG5 - DDR4/GDDR5 Mode Register 5 and LPDDR Mode Register 16
- ***************************************************************************/
-/* DDR34_PHY_CONTROL_REGS_0 :: MODE_REG5 :: reserved0 [31:21] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_MODE_REG5_reserved0_MASK 0xffe00000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_MODE_REG5_reserved0_SHIFT 21
-
-/* DDR34_PHY_CONTROL_REGS_0 :: MODE_REG5 :: reserved_for_eco1 [20:17] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_MODE_REG5_reserved_for_eco1_MASK 0x001e0000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_MODE_REG5_reserved_for_eco1_SHIFT 17
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_MODE_REG5_reserved_for_eco1_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: MODE_REG5 :: VALID [16:16] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_MODE_REG5_VALID_MASK 0x00010000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_MODE_REG5_VALID_SHIFT 16
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_MODE_REG5_VALID_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: MODE_REG5 :: AD [15:00] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_MODE_REG5_AD_MASK 0x0000ffff
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_MODE_REG5_AD_SHIFT 0
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_MODE_REG5_AD_DEFAULT 0x00000000
-
-/***************************************************************************
- *MODE_REG6 - DDR4/GDDR5 Mode Register 6 and LPDDR Mode Register 17
- ***************************************************************************/
-/* DDR34_PHY_CONTROL_REGS_0 :: MODE_REG6 :: reserved0 [31:21] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_MODE_REG6_reserved0_MASK 0xffe00000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_MODE_REG6_reserved0_SHIFT 21
-
-/* DDR34_PHY_CONTROL_REGS_0 :: MODE_REG6 :: reserved_for_eco1 [20:17] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_MODE_REG6_reserved_for_eco1_MASK 0x001e0000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_MODE_REG6_reserved_for_eco1_SHIFT 17
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_MODE_REG6_reserved_for_eco1_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: MODE_REG6 :: VALID [16:16] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_MODE_REG6_VALID_MASK 0x00010000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_MODE_REG6_VALID_SHIFT 16
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_MODE_REG6_VALID_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: MODE_REG6 :: AD [15:00] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_MODE_REG6_AD_MASK 0x0000ffff
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_MODE_REG6_AD_SHIFT 0
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_MODE_REG6_AD_DEFAULT 0x00000000
-
-/***************************************************************************
- *MODE_REG7 - DDR4/GDDR5 Mode Register 7 and LPDDR Mode Register 41
- ***************************************************************************/
-/* DDR34_PHY_CONTROL_REGS_0 :: MODE_REG7 :: reserved0 [31:21] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_MODE_REG7_reserved0_MASK 0xffe00000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_MODE_REG7_reserved0_SHIFT 21
-
-/* DDR34_PHY_CONTROL_REGS_0 :: MODE_REG7 :: reserved_for_eco1 [20:17] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_MODE_REG7_reserved_for_eco1_MASK 0x001e0000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_MODE_REG7_reserved_for_eco1_SHIFT 17
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_MODE_REG7_reserved_for_eco1_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: MODE_REG7 :: VALID [16:16] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_MODE_REG7_VALID_MASK 0x00010000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_MODE_REG7_VALID_SHIFT 16
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_MODE_REG7_VALID_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: MODE_REG7 :: AD [15:00] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_MODE_REG7_AD_MASK 0x0000ffff
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_MODE_REG7_AD_SHIFT 0
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_MODE_REG7_AD_DEFAULT 0x00000000
-
-/***************************************************************************
- *MODE_REG8 - GDDR5 Mode Register 8 and LPDDR Mode Register 42
- ***************************************************************************/
-/* DDR34_PHY_CONTROL_REGS_0 :: MODE_REG8 :: reserved0 [31:21] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_MODE_REG8_reserved0_MASK 0xffe00000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_MODE_REG8_reserved0_SHIFT 21
-
-/* DDR34_PHY_CONTROL_REGS_0 :: MODE_REG8 :: reserved_for_eco1 [20:17] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_MODE_REG8_reserved_for_eco1_MASK 0x001e0000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_MODE_REG8_reserved_for_eco1_SHIFT 17
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_MODE_REG8_reserved_for_eco1_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: MODE_REG8 :: VALID [16:16] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_MODE_REG8_VALID_MASK 0x00010000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_MODE_REG8_VALID_SHIFT 16
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_MODE_REG8_VALID_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: MODE_REG8 :: AD [15:00] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_MODE_REG8_AD_MASK 0x0000ffff
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_MODE_REG8_AD_SHIFT 0
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_MODE_REG8_AD_DEFAULT 0x00000000
-
-/***************************************************************************
- *MODE_REG15 - GDDR5 Mode Register 15 and LPDDR Mode Register 48
- ***************************************************************************/
-/* DDR34_PHY_CONTROL_REGS_0 :: MODE_REG15 :: reserved0 [31:21] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_MODE_REG15_reserved0_MASK 0xffe00000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_MODE_REG15_reserved0_SHIFT 21
-
-/* DDR34_PHY_CONTROL_REGS_0 :: MODE_REG15 :: reserved_for_eco1 [20:17] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_MODE_REG15_reserved_for_eco1_MASK 0x001e0000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_MODE_REG15_reserved_for_eco1_SHIFT 17
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_MODE_REG15_reserved_for_eco1_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: MODE_REG15 :: VALID [16:16] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_MODE_REG15_VALID_MASK 0x00010000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_MODE_REG15_VALID_SHIFT 16
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_MODE_REG15_VALID_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: MODE_REG15 :: AD [15:00] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_MODE_REG15_AD_MASK 0x0000ffff
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_MODE_REG15_AD_SHIFT 0
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_MODE_REG15_AD_DEFAULT 0x00000000
-
-/***************************************************************************
- *MODE_REG63 - LPDDR Mode Register 63
- ***************************************************************************/
-/* DDR34_PHY_CONTROL_REGS_0 :: MODE_REG63 :: reserved0 [31:21] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_MODE_REG63_reserved0_MASK 0xffe00000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_MODE_REG63_reserved0_SHIFT 21
-
-/* DDR34_PHY_CONTROL_REGS_0 :: MODE_REG63 :: reserved_for_eco1 [20:17] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_MODE_REG63_reserved_for_eco1_MASK 0x001e0000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_MODE_REG63_reserved_for_eco1_SHIFT 17
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_MODE_REG63_reserved_for_eco1_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: MODE_REG63 :: VALID [16:16] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_MODE_REG63_VALID_MASK 0x00010000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_MODE_REG63_VALID_SHIFT 16
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_MODE_REG63_VALID_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: MODE_REG63 :: AD [15:00] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_MODE_REG63_AD_MASK 0x0000ffff
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_MODE_REG63_AD_SHIFT 0
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_MODE_REG63_AD_DEFAULT 0x00000000
-
-/***************************************************************************
- *ALERT_CLEAR - DDR4 Alert status clear register
- ***************************************************************************/
-/* DDR34_PHY_CONTROL_REGS_0 :: ALERT_CLEAR :: reserved0 [31:01] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_ALERT_CLEAR_reserved0_MASK 0xfffffffe
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_ALERT_CLEAR_reserved0_SHIFT 1
-
-/* DDR34_PHY_CONTROL_REGS_0 :: ALERT_CLEAR :: CLEAR [00:00] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_ALERT_CLEAR_CLEAR_MASK 0x00000001
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_ALERT_CLEAR_CLEAR_SHIFT 0
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_ALERT_CLEAR_CLEAR_DEFAULT 0x00000000
-
-/***************************************************************************
- *ALERT_STATUS - DDR4 Alert status register
- ***************************************************************************/
-/* DDR34_PHY_CONTROL_REGS_0 :: ALERT_STATUS :: reserved0 [31:01] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_ALERT_STATUS_reserved0_MASK 0xfffffffe
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_ALERT_STATUS_reserved0_SHIFT 1
-
-/* DDR34_PHY_CONTROL_REGS_0 :: ALERT_STATUS :: STATUS [00:00] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_ALERT_STATUS_STATUS_MASK 0x00000001
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_ALERT_STATUS_STATUS_SHIFT 0
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_ALERT_STATUS_STATUS_DEFAULT 0x00000000
-
-/***************************************************************************
- *CA_PARITY - DDR4 CA parity control register
- ***************************************************************************/
-/* DDR34_PHY_CONTROL_REGS_0 :: CA_PARITY :: reserved0 [31:02] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_CA_PARITY_reserved0_MASK 0xfffffffc
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_CA_PARITY_reserved0_SHIFT 2
-
-/* DDR34_PHY_CONTROL_REGS_0 :: CA_PARITY :: ERROR [01:01] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_CA_PARITY_ERROR_MASK 0x00000002
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_CA_PARITY_ERROR_SHIFT 1
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_CA_PARITY_ERROR_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: CA_PARITY :: ENABLE [00:00] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_CA_PARITY_ENABLE_MASK 0x00000001
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_CA_PARITY_ENABLE_SHIFT 0
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_CA_PARITY_ENABLE_DEFAULT 0x00000000
-
-/***************************************************************************
- *CA_PLAYBACK_CONTROL - GDDR5 CA playback control register
- ***************************************************************************/
-/* DDR34_PHY_CONTROL_REGS_0 :: CA_PLAYBACK_CONTROL :: reserved0 [31:12] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_CA_PLAYBACK_CONTROL_reserved0_MASK 0xfffff000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_CA_PLAYBACK_CONTROL_reserved0_SHIFT 12
-
-/* DDR34_PHY_CONTROL_REGS_0 :: CA_PLAYBACK_CONTROL :: COUNT [11:04] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_CA_PLAYBACK_CONTROL_COUNT_MASK 0x00000ff0
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_CA_PLAYBACK_CONTROL_COUNT_SHIFT 4
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_CA_PLAYBACK_CONTROL_COUNT_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: CA_PLAYBACK_CONTROL :: reserved1 [03:01] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_CA_PLAYBACK_CONTROL_reserved1_MASK 0x0000000e
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_CA_PLAYBACK_CONTROL_reserved1_SHIFT 1
-
-/* DDR34_PHY_CONTROL_REGS_0 :: CA_PLAYBACK_CONTROL :: SAMPLE [00:00] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_CA_PLAYBACK_CONTROL_SAMPLE_MASK 0x00000001
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_CA_PLAYBACK_CONTROL_SAMPLE_SHIFT 0
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_CA_PLAYBACK_CONTROL_SAMPLE_DEFAULT 0x00000000
-
-/***************************************************************************
- *CA_PLAYBACK_STATUS0 - LPDDR3 and GDDR5 CA playback status register0 (for BL0 and BL1)
- ***************************************************************************/
-/* DDR34_PHY_CONTROL_REGS_0 :: CA_PLAYBACK_STATUS0 :: VALID [31:31] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_CA_PLAYBACK_STATUS0_VALID_MASK 0x80000000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_CA_PLAYBACK_STATUS0_VALID_SHIFT 31
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_CA_PLAYBACK_STATUS0_VALID_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: CA_PLAYBACK_STATUS0 :: reserved0 [30:26] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_CA_PLAYBACK_STATUS0_reserved0_MASK 0x7c000000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_CA_PLAYBACK_STATUS0_reserved0_SHIFT 26
-
-/* DDR34_PHY_CONTROL_REGS_0 :: CA_PLAYBACK_STATUS0 :: DATA1 [25:16] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_CA_PLAYBACK_STATUS0_DATA1_MASK 0x03ff0000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_CA_PLAYBACK_STATUS0_DATA1_SHIFT 16
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_CA_PLAYBACK_STATUS0_DATA1_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: CA_PLAYBACK_STATUS0 :: reserved1 [15:10] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_CA_PLAYBACK_STATUS0_reserved1_MASK 0x0000fc00
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_CA_PLAYBACK_STATUS0_reserved1_SHIFT 10
-
-/* DDR34_PHY_CONTROL_REGS_0 :: CA_PLAYBACK_STATUS0 :: DATA0 [09:00] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_CA_PLAYBACK_STATUS0_DATA0_MASK 0x000003ff
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_CA_PLAYBACK_STATUS0_DATA0_SHIFT 0
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_CA_PLAYBACK_STATUS0_DATA0_DEFAULT 0x00000000
-
-/***************************************************************************
- *CA_PLAYBACK_STATUS1 - LPDDR3 and GDDR5 CA playback status register1 (for BL2 and BL3)
- ***************************************************************************/
-/* DDR34_PHY_CONTROL_REGS_0 :: CA_PLAYBACK_STATUS1 :: VALID [31:31] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_CA_PLAYBACK_STATUS1_VALID_MASK 0x80000000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_CA_PLAYBACK_STATUS1_VALID_SHIFT 31
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_CA_PLAYBACK_STATUS1_VALID_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: CA_PLAYBACK_STATUS1 :: reserved0 [30:26] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_CA_PLAYBACK_STATUS1_reserved0_MASK 0x7c000000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_CA_PLAYBACK_STATUS1_reserved0_SHIFT 26
-
-/* DDR34_PHY_CONTROL_REGS_0 :: CA_PLAYBACK_STATUS1 :: DATA1 [25:16] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_CA_PLAYBACK_STATUS1_DATA1_MASK 0x03ff0000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_CA_PLAYBACK_STATUS1_DATA1_SHIFT 16
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_CA_PLAYBACK_STATUS1_DATA1_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: CA_PLAYBACK_STATUS1 :: reserved1 [15:10] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_CA_PLAYBACK_STATUS1_reserved1_MASK 0x0000fc00
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_CA_PLAYBACK_STATUS1_reserved1_SHIFT 10
-
-/* DDR34_PHY_CONTROL_REGS_0 :: CA_PLAYBACK_STATUS1 :: DATA0 [09:00] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_CA_PLAYBACK_STATUS1_DATA0_MASK 0x000003ff
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_CA_PLAYBACK_STATUS1_DATA0_SHIFT 0
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_CA_PLAYBACK_STATUS1_DATA0_DEFAULT 0x00000000
-
-/***************************************************************************
- *WRITE_LEVELING_CONTROL - Write leveling control register
- ***************************************************************************/
-/* DDR34_PHY_CONTROL_REGS_0 :: WRITE_LEVELING_CONTROL :: reserved0 [31:20] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_WRITE_LEVELING_CONTROL_reserved0_MASK 0xfff00000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_WRITE_LEVELING_CONTROL_reserved0_SHIFT 20
-
-/* DDR34_PHY_CONTROL_REGS_0 :: WRITE_LEVELING_CONTROL :: reserved_for_eco1 [19:16] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_WRITE_LEVELING_CONTROL_reserved_for_eco1_MASK 0x000f0000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_WRITE_LEVELING_CONTROL_reserved_for_eco1_SHIFT 16
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_WRITE_LEVELING_CONTROL_reserved_for_eco1_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: WRITE_LEVELING_CONTROL :: COUNT [15:08] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_WRITE_LEVELING_CONTROL_COUNT_MASK 0x0000ff00
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_WRITE_LEVELING_CONTROL_COUNT_SHIFT 8
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_WRITE_LEVELING_CONTROL_COUNT_DEFAULT 0x0000000f
-
-/* DDR34_PHY_CONTROL_REGS_0 :: WRITE_LEVELING_CONTROL :: reserved2 [07:03] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_WRITE_LEVELING_CONTROL_reserved2_MASK 0x000000f8
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_WRITE_LEVELING_CONTROL_reserved2_SHIFT 3
-
-/* DDR34_PHY_CONTROL_REGS_0 :: WRITE_LEVELING_CONTROL :: SAMPLE [02:02] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_WRITE_LEVELING_CONTROL_SAMPLE_MASK 0x00000004
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_WRITE_LEVELING_CONTROL_SAMPLE_SHIFT 2
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_WRITE_LEVELING_CONTROL_SAMPLE_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: WRITE_LEVELING_CONTROL :: CONTINUOUS [01:01] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_WRITE_LEVELING_CONTROL_CONTINUOUS_MASK 0x00000002
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_WRITE_LEVELING_CONTROL_CONTINUOUS_SHIFT 1
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_WRITE_LEVELING_CONTROL_CONTINUOUS_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: WRITE_LEVELING_CONTROL :: ENABLE [00:00] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_WRITE_LEVELING_CONTROL_ENABLE_MASK 0x00000001
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_WRITE_LEVELING_CONTROL_ENABLE_SHIFT 0
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_WRITE_LEVELING_CONTROL_ENABLE_DEFAULT 0x00000000
-
-/***************************************************************************
- *WRITE_LEVELING_STATUS - Write leveling status register
- ***************************************************************************/
-/* DDR34_PHY_CONTROL_REGS_0 :: WRITE_LEVELING_STATUS :: reserved0 [31:14] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_WRITE_LEVELING_STATUS_reserved0_MASK 0xffffc000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_WRITE_LEVELING_STATUS_reserved0_SHIFT 14
-
-/* DDR34_PHY_CONTROL_REGS_0 :: WRITE_LEVELING_STATUS :: EDC [13:09] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_WRITE_LEVELING_STATUS_EDC_MASK 0x00003e00
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_WRITE_LEVELING_STATUS_EDC_SHIFT 9
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_WRITE_LEVELING_STATUS_EDC_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: WRITE_LEVELING_STATUS :: STATUS [08:04] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_WRITE_LEVELING_STATUS_STATUS_MASK 0x000001f0
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_WRITE_LEVELING_STATUS_STATUS_SHIFT 4
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_WRITE_LEVELING_STATUS_STATUS_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: WRITE_LEVELING_STATUS :: reserved1 [03:01] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_WRITE_LEVELING_STATUS_reserved1_MASK 0x0000000e
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_WRITE_LEVELING_STATUS_reserved1_SHIFT 1
-
-/* DDR34_PHY_CONTROL_REGS_0 :: WRITE_LEVELING_STATUS :: VALID [00:00] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_WRITE_LEVELING_STATUS_VALID_MASK 0x00000001
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_WRITE_LEVELING_STATUS_VALID_SHIFT 0
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_WRITE_LEVELING_STATUS_VALID_DEFAULT 0x00000000
-
-/***************************************************************************
- *READ_ENABLE_CONTROL - Read enable test cycle control register
- ***************************************************************************/
-/* DDR34_PHY_CONTROL_REGS_0 :: READ_ENABLE_CONTROL :: reserved0 [31:13] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_READ_ENABLE_CONTROL_reserved0_MASK 0xffffe000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_READ_ENABLE_CONTROL_reserved0_SHIFT 13
-
-/* DDR34_PHY_CONTROL_REGS_0 :: READ_ENABLE_CONTROL :: TEST_CYCLE [12:12] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_READ_ENABLE_CONTROL_TEST_CYCLE_MASK 0x00001000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_READ_ENABLE_CONTROL_TEST_CYCLE_SHIFT 12
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_READ_ENABLE_CONTROL_TEST_CYCLE_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: READ_ENABLE_CONTROL :: SELECT [11:08] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_READ_ENABLE_CONTROL_SELECT_MASK 0x00000f00
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_READ_ENABLE_CONTROL_SELECT_SHIFT 8
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_READ_ENABLE_CONTROL_SELECT_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: READ_ENABLE_CONTROL :: reserved_for_eco1 [07:06] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_READ_ENABLE_CONTROL_reserved_for_eco1_MASK 0x000000c0
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_READ_ENABLE_CONTROL_reserved_for_eco1_SHIFT 6
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_READ_ENABLE_CONTROL_reserved_for_eco1_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: READ_ENABLE_CONTROL :: CS_N [05:04] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_READ_ENABLE_CONTROL_CS_N_MASK 0x00000030
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_READ_ENABLE_CONTROL_CS_N_SHIFT 4
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_READ_ENABLE_CONTROL_CS_N_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: READ_ENABLE_CONTROL :: EDC_DATA [03:03] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_READ_ENABLE_CONTROL_EDC_DATA_MASK 0x00000008
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_READ_ENABLE_CONTROL_EDC_DATA_SHIFT 3
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_READ_ENABLE_CONTROL_EDC_DATA_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: READ_ENABLE_CONTROL :: EDC_PHASE [02:02] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_READ_ENABLE_CONTROL_EDC_PHASE_MASK 0x00000004
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_READ_ENABLE_CONTROL_EDC_PHASE_SHIFT 2
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_READ_ENABLE_CONTROL_EDC_PHASE_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: READ_ENABLE_CONTROL :: DQS [01:01] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_READ_ENABLE_CONTROL_DQS_MASK 0x00000002
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_READ_ENABLE_CONTROL_DQS_SHIFT 1
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_READ_ENABLE_CONTROL_DQS_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: READ_ENABLE_CONTROL :: ENABLE [00:00] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_READ_ENABLE_CONTROL_ENABLE_MASK 0x00000001
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_READ_ENABLE_CONTROL_ENABLE_SHIFT 0
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_READ_ENABLE_CONTROL_ENABLE_DEFAULT 0x00000000
-
-/***************************************************************************
- *READ_ENABLE_STATUS - Read enable test cycle status register
- ***************************************************************************/
-/* DDR34_PHY_CONTROL_REGS_0 :: READ_ENABLE_STATUS :: reserved0 [31:20] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_READ_ENABLE_STATUS_reserved0_MASK 0xfff00000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_READ_ENABLE_STATUS_reserved0_SHIFT 20
-
-/* DDR34_PHY_CONTROL_REGS_0 :: READ_ENABLE_STATUS :: DATA [19:12] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_READ_ENABLE_STATUS_DATA_MASK 0x000ff000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_READ_ENABLE_STATUS_DATA_SHIFT 12
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_READ_ENABLE_STATUS_DATA_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: READ_ENABLE_STATUS :: reserved1 [11:09] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_READ_ENABLE_STATUS_reserved1_MASK 0x00000e00
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_READ_ENABLE_STATUS_reserved1_SHIFT 9
-
-/* DDR34_PHY_CONTROL_REGS_0 :: READ_ENABLE_STATUS :: BL4_STATUS [08:08] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_READ_ENABLE_STATUS_BL4_STATUS_MASK 0x00000100
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_READ_ENABLE_STATUS_BL4_STATUS_SHIFT 8
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_READ_ENABLE_STATUS_BL4_STATUS_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: READ_ENABLE_STATUS :: BL3_STATUS [07:07] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_READ_ENABLE_STATUS_BL3_STATUS_MASK 0x00000080
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_READ_ENABLE_STATUS_BL3_STATUS_SHIFT 7
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_READ_ENABLE_STATUS_BL3_STATUS_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: READ_ENABLE_STATUS :: BL2_STATUS [06:06] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_READ_ENABLE_STATUS_BL2_STATUS_MASK 0x00000040
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_READ_ENABLE_STATUS_BL2_STATUS_SHIFT 6
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_READ_ENABLE_STATUS_BL2_STATUS_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: READ_ENABLE_STATUS :: BL1_STATUS [05:05] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_READ_ENABLE_STATUS_BL1_STATUS_MASK 0x00000020
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_READ_ENABLE_STATUS_BL1_STATUS_SHIFT 5
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_READ_ENABLE_STATUS_BL1_STATUS_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: READ_ENABLE_STATUS :: BL0_STATUS [04:04] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_READ_ENABLE_STATUS_BL0_STATUS_MASK 0x00000010
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_READ_ENABLE_STATUS_BL0_STATUS_SHIFT 4
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_READ_ENABLE_STATUS_BL0_STATUS_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: READ_ENABLE_STATUS :: reserved2 [03:01] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_READ_ENABLE_STATUS_reserved2_MASK 0x0000000e
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_READ_ENABLE_STATUS_reserved2_SHIFT 1
-
-/* DDR34_PHY_CONTROL_REGS_0 :: READ_ENABLE_STATUS :: VALID [00:00] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_READ_ENABLE_STATUS_VALID_MASK 0x00000001
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_READ_ENABLE_STATUS_VALID_SHIFT 0
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_READ_ENABLE_STATUS_VALID_DEFAULT 0x00000000
-
-/***************************************************************************
- *TRAFFIC_GEN_LFSR_SEED - Traffic generator seed register
- ***************************************************************************/
-/* DDR34_PHY_CONTROL_REGS_0 :: TRAFFIC_GEN_LFSR_SEED :: SEED [31:00] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_TRAFFIC_GEN_LFSR_SEED_SEED_MASK 0xffffffff
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_TRAFFIC_GEN_LFSR_SEED_SEED_SHIFT 0
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_TRAFFIC_GEN_LFSR_SEED_SEED_DEFAULT 0xba5eba11
-
-/***************************************************************************
- *TRAFFIC_GEN_ADDRESS1 - Traffic generator address register #1
- ***************************************************************************/
-/* DDR34_PHY_CONTROL_REGS_0 :: TRAFFIC_GEN_ADDRESS1 :: reserved0 [31:20] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_TRAFFIC_GEN_ADDRESS1_reserved0_MASK 0xfff00000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_TRAFFIC_GEN_ADDRESS1_reserved0_SHIFT 20
-
-/* DDR34_PHY_CONTROL_REGS_0 :: TRAFFIC_GEN_ADDRESS1 :: BANK [19:16] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_TRAFFIC_GEN_ADDRESS1_BANK_MASK 0x000f0000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_TRAFFIC_GEN_ADDRESS1_BANK_SHIFT 16
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_TRAFFIC_GEN_ADDRESS1_BANK_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: TRAFFIC_GEN_ADDRESS1 :: ROW [15:00] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_TRAFFIC_GEN_ADDRESS1_ROW_MASK 0x0000ffff
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_TRAFFIC_GEN_ADDRESS1_ROW_SHIFT 0
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_TRAFFIC_GEN_ADDRESS1_ROW_DEFAULT 0x00000000
-
-/***************************************************************************
- *TRAFFIC_GEN_ADDRESS2 - Traffic generator address register #2
- ***************************************************************************/
-/* DDR34_PHY_CONTROL_REGS_0 :: TRAFFIC_GEN_ADDRESS2 :: reserved0 [31:20] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_TRAFFIC_GEN_ADDRESS2_reserved0_MASK 0xfff00000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_TRAFFIC_GEN_ADDRESS2_reserved0_SHIFT 20
-
-/* DDR34_PHY_CONTROL_REGS_0 :: TRAFFIC_GEN_ADDRESS2 :: BANK [19:16] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_TRAFFIC_GEN_ADDRESS2_BANK_MASK 0x000f0000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_TRAFFIC_GEN_ADDRESS2_BANK_SHIFT 16
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_TRAFFIC_GEN_ADDRESS2_BANK_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: TRAFFIC_GEN_ADDRESS2 :: ROW [15:00] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_TRAFFIC_GEN_ADDRESS2_ROW_MASK 0x0000ffff
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_TRAFFIC_GEN_ADDRESS2_ROW_SHIFT 0
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_TRAFFIC_GEN_ADDRESS2_ROW_DEFAULT 0x00000000
-
-/***************************************************************************
- *TRAFFIC_GEN_CONTROL - Traffic generator control register
- ***************************************************************************/
-/* DDR34_PHY_CONTROL_REGS_0 :: TRAFFIC_GEN_CONTROL :: reserved0 [31:17] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_TRAFFIC_GEN_CONTROL_reserved0_MASK 0xfffe0000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_TRAFFIC_GEN_CONTROL_reserved0_SHIFT 17
-
-/* DDR34_PHY_CONTROL_REGS_0 :: TRAFFIC_GEN_CONTROL :: reserved_for_eco1 [16:13] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_TRAFFIC_GEN_CONTROL_reserved_for_eco1_MASK 0x0001e000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_TRAFFIC_GEN_CONTROL_reserved_for_eco1_SHIFT 13
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_TRAFFIC_GEN_CONTROL_reserved_for_eco1_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: TRAFFIC_GEN_CONTROL :: DIAG_WRO [12:12] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_TRAFFIC_GEN_CONTROL_DIAG_WRO_MASK 0x00001000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_TRAFFIC_GEN_CONTROL_DIAG_WRO_SHIFT 12
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_TRAFFIC_GEN_CONTROL_DIAG_WRO_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: TRAFFIC_GEN_CONTROL :: DIAG_WRO_RD [11:11] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_TRAFFIC_GEN_CONTROL_DIAG_WRO_RD_MASK 0x00000800
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_TRAFFIC_GEN_CONTROL_DIAG_WRO_RD_SHIFT 11
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_TRAFFIC_GEN_CONTROL_DIAG_WRO_RD_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: TRAFFIC_GEN_CONTROL :: DIAG_WR_RD [10:10] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_TRAFFIC_GEN_CONTROL_DIAG_WR_RD_MASK 0x00000400
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_TRAFFIC_GEN_CONTROL_DIAG_WR_RD_SHIFT 10
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_TRAFFIC_GEN_CONTROL_DIAG_WR_RD_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: TRAFFIC_GEN_CONTROL :: WR_NOISE [09:09] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_TRAFFIC_GEN_CONTROL_WR_NOISE_MASK 0x00000200
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_TRAFFIC_GEN_CONTROL_WR_NOISE_SHIFT 9
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_TRAFFIC_GEN_CONTROL_WR_NOISE_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: TRAFFIC_GEN_CONTROL :: RD_NOISE [08:08] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_TRAFFIC_GEN_CONTROL_RD_NOISE_MASK 0x00000100
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_TRAFFIC_GEN_CONTROL_RD_NOISE_SHIFT 8
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_TRAFFIC_GEN_CONTROL_RD_NOISE_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: TRAFFIC_GEN_CONTROL :: CLEAR_DRAM [07:07] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_TRAFFIC_GEN_CONTROL_CLEAR_DRAM_MASK 0x00000080
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_TRAFFIC_GEN_CONTROL_CLEAR_DRAM_SHIFT 7
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_TRAFFIC_GEN_CONTROL_CLEAR_DRAM_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: TRAFFIC_GEN_CONTROL :: MASK_DM [06:06] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_TRAFFIC_GEN_CONTROL_MASK_DM_MASK 0x00000040
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_TRAFFIC_GEN_CONTROL_MASK_DM_SHIFT 6
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_TRAFFIC_GEN_CONTROL_MASK_DM_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: TRAFFIC_GEN_CONTROL :: INIT_LFSR [05:05] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_TRAFFIC_GEN_CONTROL_INIT_LFSR_MASK 0x00000020
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_TRAFFIC_GEN_CONTROL_INIT_LFSR_SHIFT 5
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_TRAFFIC_GEN_CONTROL_INIT_LFSR_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: TRAFFIC_GEN_CONTROL :: FIFO [04:04] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_TRAFFIC_GEN_CONTROL_FIFO_MASK 0x00000010
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_TRAFFIC_GEN_CONTROL_FIFO_SHIFT 4
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_TRAFFIC_GEN_CONTROL_FIFO_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: TRAFFIC_GEN_CONTROL :: MPR [03:03] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_TRAFFIC_GEN_CONTROL_MPR_MASK 0x00000008
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_TRAFFIC_GEN_CONTROL_MPR_SHIFT 3
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_TRAFFIC_GEN_CONTROL_MPR_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: TRAFFIC_GEN_CONTROL :: RD_WR [02:02] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_TRAFFIC_GEN_CONTROL_RD_WR_MASK 0x00000004
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_TRAFFIC_GEN_CONTROL_RD_WR_SHIFT 2
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_TRAFFIC_GEN_CONTROL_RD_WR_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: TRAFFIC_GEN_CONTROL :: RD_EN [01:01] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_TRAFFIC_GEN_CONTROL_RD_EN_MASK 0x00000002
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_TRAFFIC_GEN_CONTROL_RD_EN_SHIFT 1
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_TRAFFIC_GEN_CONTROL_RD_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: TRAFFIC_GEN_CONTROL :: ENABLE [00:00] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_TRAFFIC_GEN_CONTROL_ENABLE_MASK 0x00000001
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_TRAFFIC_GEN_CONTROL_ENABLE_SHIFT 0
-
-/***************************************************************************
- *TRAFFIC_GEN_DATA_CONTROL - Traffic generator data control register
- ***************************************************************************/
-/* DDR34_PHY_CONTROL_REGS_0 :: TRAFFIC_GEN_DATA_CONTROL :: reserved0 [31:22] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_TRAFFIC_GEN_DATA_CONTROL_reserved0_MASK 0xffc00000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_TRAFFIC_GEN_DATA_CONTROL_reserved0_SHIFT 22
-
-/* DDR34_PHY_CONTROL_REGS_0 :: TRAFFIC_GEN_DATA_CONTROL :: PATTERN [21:20] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_TRAFFIC_GEN_DATA_CONTROL_PATTERN_MASK 0x00300000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_TRAFFIC_GEN_DATA_CONTROL_PATTERN_SHIFT 20
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_TRAFFIC_GEN_DATA_CONTROL_PATTERN_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: TRAFFIC_GEN_DATA_CONTROL :: LENGTH [19:00] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_TRAFFIC_GEN_DATA_CONTROL_LENGTH_MASK 0x000fffff
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_TRAFFIC_GEN_DATA_CONTROL_LENGTH_SHIFT 0
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_TRAFFIC_GEN_DATA_CONTROL_LENGTH_DEFAULT 0x00000000
-
-/***************************************************************************
- *TRAFFIC_GEN_DQ_MASK - Traffic generator DQ mask register
- ***************************************************************************/
-/* DDR34_PHY_CONTROL_REGS_0 :: TRAFFIC_GEN_DQ_MASK :: MASK [31:00] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_TRAFFIC_GEN_DQ_MASK_MASK_MASK 0xffffffff
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_TRAFFIC_GEN_DQ_MASK_MASK_SHIFT 0
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_TRAFFIC_GEN_DQ_MASK_MASK_DEFAULT 0x00000000
-
-/***************************************************************************
- *TRAFFIC_GEN_ECC_DQ_MASK - Traffic generator ECC DQ mask register
- ***************************************************************************/
-/* DDR34_PHY_CONTROL_REGS_0 :: TRAFFIC_GEN_ECC_DQ_MASK :: reserved0 [31:04] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_TRAFFIC_GEN_ECC_DQ_MASK_reserved0_MASK 0xfffffff0
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_TRAFFIC_GEN_ECC_DQ_MASK_reserved0_SHIFT 4
-
-/* DDR34_PHY_CONTROL_REGS_0 :: TRAFFIC_GEN_ECC_DQ_MASK :: MASK [03:00] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_TRAFFIC_GEN_ECC_DQ_MASK_MASK_MASK 0x0000000f
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_TRAFFIC_GEN_ECC_DQ_MASK_MASK_SHIFT 0
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_TRAFFIC_GEN_ECC_DQ_MASK_MASK_DEFAULT 0x00000000
-
-/***************************************************************************
- *TRAFFIC_GEN_STATUS - Traffic generator status register
- ***************************************************************************/
-/* DDR34_PHY_CONTROL_REGS_0 :: TRAFFIC_GEN_STATUS :: reserved0 [31:01] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_TRAFFIC_GEN_STATUS_reserved0_MASK 0xfffffffe
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_TRAFFIC_GEN_STATUS_reserved0_SHIFT 1
-
-/* DDR34_PHY_CONTROL_REGS_0 :: TRAFFIC_GEN_STATUS :: BUSY [00:00] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_TRAFFIC_GEN_STATUS_BUSY_MASK 0x00000001
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_TRAFFIC_GEN_STATUS_BUSY_SHIFT 0
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_TRAFFIC_GEN_STATUS_BUSY_DEFAULT 0x00000000
-
-/***************************************************************************
- *TRAFFIC_GEN_DQ_STATUS - Traffic generator DQ status register
- ***************************************************************************/
-/* DDR34_PHY_CONTROL_REGS_0 :: TRAFFIC_GEN_DQ_STATUS :: STATUS [31:00] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_TRAFFIC_GEN_DQ_STATUS_STATUS_MASK 0xffffffff
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_TRAFFIC_GEN_DQ_STATUS_STATUS_SHIFT 0
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_TRAFFIC_GEN_DQ_STATUS_STATUS_DEFAULT 0x00000000
-
-/***************************************************************************
- *TRAFFIC_GEN_ECC_STATUS - Traffic generator ECC DQ status register
- ***************************************************************************/
-/* DDR34_PHY_CONTROL_REGS_0 :: TRAFFIC_GEN_ECC_STATUS :: reserved0 [31:04] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_TRAFFIC_GEN_ECC_STATUS_reserved0_MASK 0xfffffff0
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_TRAFFIC_GEN_ECC_STATUS_reserved0_SHIFT 4
-
-/* DDR34_PHY_CONTROL_REGS_0 :: TRAFFIC_GEN_ECC_STATUS :: STATUS [03:00] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_TRAFFIC_GEN_ECC_STATUS_STATUS_MASK 0x0000000f
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_TRAFFIC_GEN_ECC_STATUS_STATUS_SHIFT 0
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_TRAFFIC_GEN_ECC_STATUS_STATUS_DEFAULT 0x00000000
-
-/***************************************************************************
- *TRAFFIC_GEN_ERR_CNT_CONTROL - Traffic generator error count control register
- ***************************************************************************/
-/* DDR34_PHY_CONTROL_REGS_0 :: TRAFFIC_GEN_ERR_CNT_CONTROL :: reserved0 [31:09] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_TRAFFIC_GEN_ERR_CNT_CONTROL_reserved0_MASK 0xfffffe00
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_TRAFFIC_GEN_ERR_CNT_CONTROL_reserved0_SHIFT 9
-
-/* DDR34_PHY_CONTROL_REGS_0 :: TRAFFIC_GEN_ERR_CNT_CONTROL :: DQ_SEL [08:04] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_TRAFFIC_GEN_ERR_CNT_CONTROL_DQ_SEL_MASK 0x000001f0
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_TRAFFIC_GEN_ERR_CNT_CONTROL_DQ_SEL_SHIFT 4
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_TRAFFIC_GEN_ERR_CNT_CONTROL_DQ_SEL_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: TRAFFIC_GEN_ERR_CNT_CONTROL :: reserved1 [03:02] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_TRAFFIC_GEN_ERR_CNT_CONTROL_reserved1_MASK 0x0000000c
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_TRAFFIC_GEN_ERR_CNT_CONTROL_reserved1_SHIFT 2
-
-/* DDR34_PHY_CONTROL_REGS_0 :: TRAFFIC_GEN_ERR_CNT_CONTROL :: CLEAR [01:01] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_TRAFFIC_GEN_ERR_CNT_CONTROL_CLEAR_MASK 0x00000002
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_TRAFFIC_GEN_ERR_CNT_CONTROL_CLEAR_SHIFT 1
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_TRAFFIC_GEN_ERR_CNT_CONTROL_CLEAR_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: TRAFFIC_GEN_ERR_CNT_CONTROL :: ENABLE [00:00] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_TRAFFIC_GEN_ERR_CNT_CONTROL_ENABLE_MASK 0x00000001
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_TRAFFIC_GEN_ERR_CNT_CONTROL_ENABLE_SHIFT 0
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_TRAFFIC_GEN_ERR_CNT_CONTROL_ENABLE_DEFAULT 0x00000000
-
-/***************************************************************************
- *TRAFFIC_GEN_ERR_CNT_STATUS - Traffic generator error count status register
- ***************************************************************************/
-/* DDR34_PHY_CONTROL_REGS_0 :: TRAFFIC_GEN_ERR_CNT_STATUS :: reserved0 [31:16] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_TRAFFIC_GEN_ERR_CNT_STATUS_reserved0_MASK 0xffff0000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_TRAFFIC_GEN_ERR_CNT_STATUS_reserved0_SHIFT 16
-
-/* DDR34_PHY_CONTROL_REGS_0 :: TRAFFIC_GEN_ERR_CNT_STATUS :: COUNT [15:00] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_TRAFFIC_GEN_ERR_CNT_STATUS_COUNT_MASK 0x0000ffff
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_TRAFFIC_GEN_ERR_CNT_STATUS_COUNT_SHIFT 0
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_TRAFFIC_GEN_ERR_CNT_STATUS_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *VIRTUAL_VTT_CONTROL - Virtual VTT Control and Status register
- ***************************************************************************/
-/* DDR34_PHY_CONTROL_REGS_0 :: VIRTUAL_VTT_CONTROL :: reserved0 [31:12] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONTROL_reserved0_MASK 0xfffff000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONTROL_reserved0_SHIFT 12
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VIRTUAL_VTT_CONTROL :: reserved_for_eco1 [11:08] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONTROL_reserved_for_eco1_MASK 0x00000f00
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONTROL_reserved_for_eco1_SHIFT 8
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONTROL_reserved_for_eco1_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VIRTUAL_VTT_CONTROL :: MAX_NOISE [07:07] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONTROL_MAX_NOISE_MASK 0x00000080
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONTROL_MAX_NOISE_SHIFT 7
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONTROL_MAX_NOISE_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VIRTUAL_VTT_CONTROL :: LOW_NOISE [06:06] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONTROL_LOW_NOISE_MASK 0x00000040
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONTROL_LOW_NOISE_SHIFT 6
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONTROL_LOW_NOISE_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VIRTUAL_VTT_CONTROL :: LOW_VTT [05:05] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONTROL_LOW_VTT_MASK 0x00000020
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONTROL_LOW_VTT_SHIFT 5
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONTROL_LOW_VTT_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VIRTUAL_VTT_CONTROL :: HIGH_VTT [04:04] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONTROL_HIGH_VTT_MASK 0x00000010
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONTROL_HIGH_VTT_SHIFT 4
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONTROL_HIGH_VTT_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VIRTUAL_VTT_CONTROL :: ERROR_RESET [03:03] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONTROL_ERROR_RESET_MASK 0x00000008
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONTROL_ERROR_RESET_SHIFT 3
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONTROL_ERROR_RESET_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VIRTUAL_VTT_CONTROL :: ENABLE_CTL_IDLE [02:02] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONTROL_ENABLE_CTL_IDLE_MASK 0x00000004
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONTROL_ENABLE_CTL_IDLE_SHIFT 2
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONTROL_ENABLE_CTL_IDLE_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VIRTUAL_VTT_CONTROL :: ENABLE_CS_IDLE [01:01] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONTROL_ENABLE_CS_IDLE_MASK 0x00000002
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONTROL_ENABLE_CS_IDLE_SHIFT 1
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONTROL_ENABLE_CS_IDLE_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VIRTUAL_VTT_CONTROL :: ENABLE_CKE_IDLE [00:00] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONTROL_ENABLE_CKE_IDLE_MASK 0x00000001
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONTROL_ENABLE_CKE_IDLE_SHIFT 0
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONTROL_ENABLE_CKE_IDLE_DEFAULT 0x00000000
-
-/***************************************************************************
- *VIRTUAL_VTT_STATUS - Virtual VTT Control and Status register
- ***************************************************************************/
-/* DDR34_PHY_CONTROL_REGS_0 :: VIRTUAL_VTT_STATUS :: reserved0 [31:19] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VIRTUAL_VTT_STATUS_reserved0_MASK 0xfff80000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VIRTUAL_VTT_STATUS_reserved0_SHIFT 19
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VIRTUAL_VTT_STATUS :: ERROR [18:03] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VIRTUAL_VTT_STATUS_ERROR_MASK 0x0007fff8
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VIRTUAL_VTT_STATUS_ERROR_SHIFT 3
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VIRTUAL_VTT_STATUS_ERROR_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VIRTUAL_VTT_STATUS :: ERROR_LOW [02:02] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VIRTUAL_VTT_STATUS_ERROR_LOW_MASK 0x00000004
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VIRTUAL_VTT_STATUS_ERROR_LOW_SHIFT 2
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VIRTUAL_VTT_STATUS_ERROR_LOW_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VIRTUAL_VTT_STATUS :: ERROR_HIGH [01:01] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VIRTUAL_VTT_STATUS_ERROR_HIGH_MASK 0x00000002
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VIRTUAL_VTT_STATUS_ERROR_HIGH_SHIFT 1
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VIRTUAL_VTT_STATUS_ERROR_HIGH_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VIRTUAL_VTT_STATUS :: READY [00:00] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VIRTUAL_VTT_STATUS_READY_MASK 0x00000001
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VIRTUAL_VTT_STATUS_READY_SHIFT 0
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VIRTUAL_VTT_STATUS_READY_DEFAULT 0x00000000
-
-/***************************************************************************
- *VIRTUAL_VTT_CONNECTIONS - Virtual VTT Connections register
- ***************************************************************************/
-/* DDR34_PHY_CONTROL_REGS_0 :: VIRTUAL_VTT_CONNECTIONS :: reserved0 [31:31] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONNECTIONS_reserved0_MASK 0x80000000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONNECTIONS_reserved0_SHIFT 31
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VIRTUAL_VTT_CONNECTIONS :: MASK [30:00] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONNECTIONS_MASK_MASK 0x7fffffff
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONNECTIONS_MASK_SHIFT 0
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONNECTIONS_MASK_DEFAULT 0x1fffffff
-
-/***************************************************************************
- *VIRTUAL_VTT_OVERRIDE - Virtual VTT Override register
- ***************************************************************************/
-/* DDR34_PHY_CONTROL_REGS_0 :: VIRTUAL_VTT_OVERRIDE :: reserved0 [31:31] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VIRTUAL_VTT_OVERRIDE_reserved0_MASK 0x80000000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VIRTUAL_VTT_OVERRIDE_reserved0_SHIFT 31
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VIRTUAL_VTT_OVERRIDE :: MASK [30:00] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VIRTUAL_VTT_OVERRIDE_MASK_MASK 0x7fffffff
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VIRTUAL_VTT_OVERRIDE_MASK_SHIFT 0
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VIRTUAL_VTT_OVERRIDE_MASK_DEFAULT 0x0000ffff
-
-/***************************************************************************
- *VREF_DAC_CONTROL - VREF DAC Control register
- ***************************************************************************/
-/* DDR34_PHY_CONTROL_REGS_0 :: VREF_DAC_CONTROL :: reserved0 [31:20] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_reserved0_MASK 0xfff00000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_reserved0_SHIFT 20
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VREF_DAC_CONTROL :: AUX_GT_INT [19:19] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_AUX_GT_INT_MASK 0x00080000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_AUX_GT_INT_SHIFT 19
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_AUX_GT_INT_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VREF_DAC_CONTROL :: TESTOUT_MUX_CTL [18:17] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_TESTOUT_MUX_CTL_MASK 0x00060000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_TESTOUT_MUX_CTL_SHIFT 17
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_TESTOUT_MUX_CTL_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VREF_DAC_CONTROL :: TEST [16:16] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_TEST_MASK 0x00010000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_TEST_SHIFT 16
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_TEST_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VREF_DAC_CONTROL :: PDN3 [15:15] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_PDN3_MASK 0x00008000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_PDN3_SHIFT 15
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_PDN3_DEFAULT 0x00000001
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VREF_DAC_CONTROL :: PDN2 [14:14] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_PDN2_MASK 0x00004000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_PDN2_SHIFT 14
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_PDN2_DEFAULT 0x00000001
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VREF_DAC_CONTROL :: PDN1 [13:13] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_PDN1_MASK 0x00002000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_PDN1_SHIFT 13
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_PDN1_DEFAULT 0x00000001
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VREF_DAC_CONTROL :: PDN0 [12:12] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_PDN0_MASK 0x00001000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_PDN0_SHIFT 12
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_PDN0_DEFAULT 0x00000001
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VREF_DAC_CONTROL :: DAC1 [11:06] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_DAC1_MASK 0x00000fc0
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_DAC1_SHIFT 6
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_DAC1_DEFAULT 0x00000020
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VREF_DAC_CONTROL :: DAC0 [05:00] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_DAC0_MASK 0x0000003f
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_DAC0_SHIFT 0
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_DAC0_DEFAULT 0x00000020
-
-/***************************************************************************
- *PHYBIST_CNTRL - PhyBist Control Register
- ***************************************************************************/
-/* DDR34_PHY_CONTROL_REGS_0 :: PHYBIST_CNTRL :: reserved0 [31:30] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PHYBIST_CNTRL_reserved0_MASK 0xc0000000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PHYBIST_CNTRL_reserved0_SHIFT 30
-
-/* DDR34_PHY_CONTROL_REGS_0 :: PHYBIST_CNTRL :: CLK_PAD_ENB [29:28] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PHYBIST_CNTRL_CLK_PAD_ENB_MASK 0x30000000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PHYBIST_CNTRL_CLK_PAD_ENB_SHIFT 28
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PHYBIST_CNTRL_CLK_PAD_ENB_DEFAULT 0x00000002
-
-/* DDR34_PHY_CONTROL_REGS_0 :: PHYBIST_CNTRL :: reserved1 [27:27] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PHYBIST_CNTRL_reserved1_MASK 0x08000000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PHYBIST_CNTRL_reserved1_SHIFT 27
-
-/* DDR34_PHY_CONTROL_REGS_0 :: PHYBIST_CNTRL :: FORCE_DQ_ERROR_SEL [26:24] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PHYBIST_CNTRL_FORCE_DQ_ERROR_SEL_MASK 0x07000000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PHYBIST_CNTRL_FORCE_DQ_ERROR_SEL_SHIFT 24
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PHYBIST_CNTRL_FORCE_DQ_ERROR_SEL_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: PHYBIST_CNTRL :: reserved_for_eco2 [23:23] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PHYBIST_CNTRL_reserved_for_eco2_MASK 0x00800000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PHYBIST_CNTRL_reserved_for_eco2_SHIFT 23
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PHYBIST_CNTRL_reserved_for_eco2_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: PHYBIST_CNTRL :: FORCE_BL_ERROR_SEL [22:20] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PHYBIST_CNTRL_FORCE_BL_ERROR_SEL_MASK 0x00700000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PHYBIST_CNTRL_FORCE_BL_ERROR_SEL_SHIFT 20
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PHYBIST_CNTRL_FORCE_BL_ERROR_SEL_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: PHYBIST_CNTRL :: reserved_for_eco3 [19:17] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PHYBIST_CNTRL_reserved_for_eco3_MASK 0x000e0000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PHYBIST_CNTRL_reserved_for_eco3_SHIFT 17
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PHYBIST_CNTRL_reserved_for_eco3_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: PHYBIST_CNTRL :: FORCE_CTL_ERROR_SEL [16:12] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PHYBIST_CNTRL_FORCE_CTL_ERROR_SEL_MASK 0x0001f000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PHYBIST_CNTRL_FORCE_CTL_ERROR_SEL_SHIFT 12
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PHYBIST_CNTRL_FORCE_CTL_ERROR_SEL_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: PHYBIST_CNTRL :: reserved4 [11:10] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PHYBIST_CNTRL_reserved4_MASK 0x00000c00
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PHYBIST_CNTRL_reserved4_SHIFT 10
-
-/* DDR34_PHY_CONTROL_REGS_0 :: PHYBIST_CNTRL :: FORCE_DAT_ERROR [09:09] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PHYBIST_CNTRL_FORCE_DAT_ERROR_MASK 0x00000200
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PHYBIST_CNTRL_FORCE_DAT_ERROR_SHIFT 9
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PHYBIST_CNTRL_FORCE_DAT_ERROR_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: PHYBIST_CNTRL :: FORCE_CTL_ERROR [08:08] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PHYBIST_CNTRL_FORCE_CTL_ERROR_MASK 0x00000100
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PHYBIST_CNTRL_FORCE_CTL_ERROR_SHIFT 8
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PHYBIST_CNTRL_FORCE_CTL_ERROR_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: PHYBIST_CNTRL :: SSO [07:06] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PHYBIST_CNTRL_SSO_MASK 0x000000c0
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PHYBIST_CNTRL_SSO_SHIFT 6
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PHYBIST_CNTRL_SSO_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: PHYBIST_CNTRL :: LENGTH [05:04] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PHYBIST_CNTRL_LENGTH_MASK 0x00000030
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PHYBIST_CNTRL_LENGTH_SHIFT 4
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PHYBIST_CNTRL_LENGTH_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: PHYBIST_CNTRL :: MODE [03:01] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PHYBIST_CNTRL_MODE_MASK 0x0000000e
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PHYBIST_CNTRL_MODE_SHIFT 1
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PHYBIST_CNTRL_MODE_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: PHYBIST_CNTRL :: ENABLE [00:00] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PHYBIST_CNTRL_ENABLE_MASK 0x00000001
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PHYBIST_CNTRL_ENABLE_SHIFT 0
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PHYBIST_CNTRL_ENABLE_DEFAULT 0x00000000
-
-/***************************************************************************
- *PHYBIST_SEED - PhyBist Seed Register
- ***************************************************************************/
-/* DDR34_PHY_CONTROL_REGS_0 :: PHYBIST_SEED :: SEED [31:00] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PHYBIST_SEED_SEED_MASK 0xffffffff
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PHYBIST_SEED_SEED_SHIFT 0
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PHYBIST_SEED_SEED_DEFAULT 0xba5eba11
-
-/***************************************************************************
- *PHYBIST_STATUS - PhyBist General Status Register
- ***************************************************************************/
-/* DDR34_PHY_CONTROL_REGS_0 :: PHYBIST_STATUS :: reserved0 [31:04] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PHYBIST_STATUS_reserved0_MASK 0xfffffff0
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PHYBIST_STATUS_reserved0_SHIFT 4
-
-/* DDR34_PHY_CONTROL_REGS_0 :: PHYBIST_STATUS :: DAT_PASS [03:03] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PHYBIST_STATUS_DAT_PASS_MASK 0x00000008
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PHYBIST_STATUS_DAT_PASS_SHIFT 3
-
-/* DDR34_PHY_CONTROL_REGS_0 :: PHYBIST_STATUS :: CTL_PASS [02:02] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PHYBIST_STATUS_CTL_PASS_MASK 0x00000004
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PHYBIST_STATUS_CTL_PASS_SHIFT 2
-
-/* DDR34_PHY_CONTROL_REGS_0 :: PHYBIST_STATUS :: DAT_DONE [01:01] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PHYBIST_STATUS_DAT_DONE_MASK 0x00000002
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PHYBIST_STATUS_DAT_DONE_SHIFT 1
-
-/* DDR34_PHY_CONTROL_REGS_0 :: PHYBIST_STATUS :: CTL_DONE [00:00] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PHYBIST_STATUS_CTL_DONE_MASK 0x00000001
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PHYBIST_STATUS_CTL_DONE_SHIFT 0
-
-/***************************************************************************
- *PHYBIST_CTL_STATUS - PhyBist Per-Bit Control Pad Status Register
- ***************************************************************************/
-/* DDR34_PHY_CONTROL_REGS_0 :: PHYBIST_CTL_STATUS :: reserved0 [31:31] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PHYBIST_CTL_STATUS_reserved0_MASK 0x80000000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PHYBIST_CTL_STATUS_reserved0_SHIFT 31
-
-/* DDR34_PHY_CONTROL_REGS_0 :: PHYBIST_CTL_STATUS :: CTL_ERRORS [30:00] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PHYBIST_CTL_STATUS_CTL_ERRORS_MASK 0x7fffffff
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PHYBIST_CTL_STATUS_CTL_ERRORS_SHIFT 0
-
-/***************************************************************************
- *PHYBIST_BL0_STATUS - PhyBist Byte Lane #0 Status Register
- ***************************************************************************/
-/* DDR34_PHY_CONTROL_REGS_0 :: PHYBIST_BL0_STATUS :: reserved0 [31:10] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PHYBIST_BL0_STATUS_reserved0_MASK 0xfffffc00
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PHYBIST_BL0_STATUS_reserved0_SHIFT 10
-
-/* DDR34_PHY_CONTROL_REGS_0 :: PHYBIST_BL0_STATUS :: EDC [09:09] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PHYBIST_BL0_STATUS_EDC_MASK 0x00000200
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PHYBIST_BL0_STATUS_EDC_SHIFT 9
-
-/* DDR34_PHY_CONTROL_REGS_0 :: PHYBIST_BL0_STATUS :: DM [08:08] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PHYBIST_BL0_STATUS_DM_MASK 0x00000100
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PHYBIST_BL0_STATUS_DM_SHIFT 8
-
-/* DDR34_PHY_CONTROL_REGS_0 :: PHYBIST_BL0_STATUS :: DQ [07:00] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PHYBIST_BL0_STATUS_DQ_MASK 0x000000ff
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PHYBIST_BL0_STATUS_DQ_SHIFT 0
-
-/***************************************************************************
- *PHYBIST_BL1_STATUS - PhyBist Byte Lane #1 Status Register
- ***************************************************************************/
-/* DDR34_PHY_CONTROL_REGS_0 :: PHYBIST_BL1_STATUS :: reserved0 [31:10] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PHYBIST_BL1_STATUS_reserved0_MASK 0xfffffc00
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PHYBIST_BL1_STATUS_reserved0_SHIFT 10
-
-/* DDR34_PHY_CONTROL_REGS_0 :: PHYBIST_BL1_STATUS :: EDC [09:09] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PHYBIST_BL1_STATUS_EDC_MASK 0x00000200
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PHYBIST_BL1_STATUS_EDC_SHIFT 9
-
-/* DDR34_PHY_CONTROL_REGS_0 :: PHYBIST_BL1_STATUS :: DM [08:08] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PHYBIST_BL1_STATUS_DM_MASK 0x00000100
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PHYBIST_BL1_STATUS_DM_SHIFT 8
-
-/* DDR34_PHY_CONTROL_REGS_0 :: PHYBIST_BL1_STATUS :: DQ [07:00] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PHYBIST_BL1_STATUS_DQ_MASK 0x000000ff
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PHYBIST_BL1_STATUS_DQ_SHIFT 0
-
-/***************************************************************************
- *PHYBIST_BL2_STATUS - PhyBist Byte Lane #2 Status Register
- ***************************************************************************/
-/* DDR34_PHY_CONTROL_REGS_0 :: PHYBIST_BL2_STATUS :: reserved0 [31:10] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PHYBIST_BL2_STATUS_reserved0_MASK 0xfffffc00
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PHYBIST_BL2_STATUS_reserved0_SHIFT 10
-
-/* DDR34_PHY_CONTROL_REGS_0 :: PHYBIST_BL2_STATUS :: EDC [09:09] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PHYBIST_BL2_STATUS_EDC_MASK 0x00000200
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PHYBIST_BL2_STATUS_EDC_SHIFT 9
-
-/* DDR34_PHY_CONTROL_REGS_0 :: PHYBIST_BL2_STATUS :: DM [08:08] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PHYBIST_BL2_STATUS_DM_MASK 0x00000100
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PHYBIST_BL2_STATUS_DM_SHIFT 8
-
-/* DDR34_PHY_CONTROL_REGS_0 :: PHYBIST_BL2_STATUS :: DQ [07:00] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PHYBIST_BL2_STATUS_DQ_MASK 0x000000ff
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PHYBIST_BL2_STATUS_DQ_SHIFT 0
-
-/***************************************************************************
- *PHYBIST_BL3_STATUS - PhyBist Byte Lane #3 Status Register
- ***************************************************************************/
-/* DDR34_PHY_CONTROL_REGS_0 :: PHYBIST_BL3_STATUS :: reserved0 [31:10] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PHYBIST_BL3_STATUS_reserved0_MASK 0xfffffc00
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PHYBIST_BL3_STATUS_reserved0_SHIFT 10
-
-/* DDR34_PHY_CONTROL_REGS_0 :: PHYBIST_BL3_STATUS :: EDC [09:09] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PHYBIST_BL3_STATUS_EDC_MASK 0x00000200
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PHYBIST_BL3_STATUS_EDC_SHIFT 9
-
-/* DDR34_PHY_CONTROL_REGS_0 :: PHYBIST_BL3_STATUS :: DM [08:08] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PHYBIST_BL3_STATUS_DM_MASK 0x00000100
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PHYBIST_BL3_STATUS_DM_SHIFT 8
-
-/* DDR34_PHY_CONTROL_REGS_0 :: PHYBIST_BL3_STATUS :: DQ [07:00] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PHYBIST_BL3_STATUS_DQ_MASK 0x000000ff
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PHYBIST_BL3_STATUS_DQ_SHIFT 0
-
-/***************************************************************************
- *PHYBIST_BL4_STATUS - PhyBist Byte Lane #4 (ECC) Status Register
- ***************************************************************************/
-/* DDR34_PHY_CONTROL_REGS_0 :: PHYBIST_BL4_STATUS :: reserved0 [31:10] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PHYBIST_BL4_STATUS_reserved0_MASK 0xfffffc00
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PHYBIST_BL4_STATUS_reserved0_SHIFT 10
-
-/* DDR34_PHY_CONTROL_REGS_0 :: PHYBIST_BL4_STATUS :: EDC [09:09] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PHYBIST_BL4_STATUS_EDC_MASK 0x00000200
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PHYBIST_BL4_STATUS_EDC_SHIFT 9
-
-/* DDR34_PHY_CONTROL_REGS_0 :: PHYBIST_BL4_STATUS :: DM [08:08] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PHYBIST_BL4_STATUS_DM_MASK 0x00000100
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PHYBIST_BL4_STATUS_DM_SHIFT 8
-
-/* DDR34_PHY_CONTROL_REGS_0 :: PHYBIST_BL4_STATUS :: DQ [07:00] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PHYBIST_BL4_STATUS_DQ_MASK 0x000000ff
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PHYBIST_BL4_STATUS_DQ_SHIFT 0
-
-/***************************************************************************
- *STANDBY_CONTROL - Standby Control register
- ***************************************************************************/
-/* DDR34_PHY_CONTROL_REGS_0 :: STANDBY_CONTROL :: reserved0 [31:23] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_STANDBY_CONTROL_reserved0_MASK 0xff800000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_STANDBY_CONTROL_reserved0_SHIFT 23
-
-/* DDR34_PHY_CONTROL_REGS_0 :: STANDBY_CONTROL :: STANDBY_READY [22:22] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_STANDBY_CONTROL_STANDBY_READY_MASK 0x00400000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_STANDBY_CONTROL_STANDBY_READY_SHIFT 22
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_STANDBY_CONTROL_STANDBY_READY_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: STANDBY_CONTROL :: STANDBY_EXIT_PIN_EN [21:21] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_STANDBY_CONTROL_STANDBY_EXIT_PIN_EN_MASK 0x00200000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_STANDBY_CONTROL_STANDBY_EXIT_PIN_EN_SHIFT 21
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_STANDBY_CONTROL_STANDBY_EXIT_PIN_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: STANDBY_CONTROL :: STANDBY_ACTIVE [20:20] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_STANDBY_CONTROL_STANDBY_ACTIVE_MASK 0x00100000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_STANDBY_CONTROL_STANDBY_ACTIVE_SHIFT 20
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_STANDBY_CONTROL_STANDBY_ACTIVE_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: STANDBY_CONTROL :: ARMED [19:19] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_STANDBY_CONTROL_ARMED_MASK 0x00080000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_STANDBY_CONTROL_ARMED_SHIFT 19
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_STANDBY_CONTROL_ARMED_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: STANDBY_CONTROL :: WARMSTART [18:18] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_STANDBY_CONTROL_WARMSTART_MASK 0x00040000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_STANDBY_CONTROL_WARMSTART_SHIFT 18
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_STANDBY_CONTROL_WARMSTART_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: STANDBY_CONTROL :: PWRDOWN_LDO_BIAS [17:16] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_STANDBY_CONTROL_PWRDOWN_LDO_BIAS_MASK 0x00030000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_STANDBY_CONTROL_PWRDOWN_LDO_BIAS_SHIFT 16
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_STANDBY_CONTROL_PWRDOWN_LDO_BIAS_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: STANDBY_CONTROL :: PWRDOWN_LDO_VOLTS [15:14] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_STANDBY_CONTROL_PWRDOWN_LDO_VOLTS_MASK 0x0000c000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_STANDBY_CONTROL_PWRDOWN_LDO_VOLTS_SHIFT 14
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_STANDBY_CONTROL_PWRDOWN_LDO_VOLTS_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: STANDBY_CONTROL :: PWRDOWN_SKIP_MRS [13:13] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_STANDBY_CONTROL_PWRDOWN_SKIP_MRS_MASK 0x00002000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_STANDBY_CONTROL_PWRDOWN_SKIP_MRS_SHIFT 13
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_STANDBY_CONTROL_PWRDOWN_SKIP_MRS_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: STANDBY_CONTROL :: PWRDOWN_RST_N [12:12] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_STANDBY_CONTROL_PWRDOWN_RST_N_MASK 0x00001000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_STANDBY_CONTROL_PWRDOWN_RST_N_SHIFT 12
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_STANDBY_CONTROL_PWRDOWN_RST_N_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: STANDBY_CONTROL :: PWRDOWN_CKE [11:11] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_STANDBY_CONTROL_PWRDOWN_CKE_MASK 0x00000800
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_STANDBY_CONTROL_PWRDOWN_CKE_SHIFT 11
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_STANDBY_CONTROL_PWRDOWN_CKE_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: STANDBY_CONTROL :: LDO_BIAS [10:09] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_STANDBY_CONTROL_LDO_BIAS_MASK 0x00000600
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_STANDBY_CONTROL_LDO_BIAS_SHIFT 9
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_STANDBY_CONTROL_LDO_BIAS_DEFAULT 0x00000003
-
-/* DDR34_PHY_CONTROL_REGS_0 :: STANDBY_CONTROL :: LDO_VOLTS [08:07] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_STANDBY_CONTROL_LDO_VOLTS_MASK 0x00000180
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_STANDBY_CONTROL_LDO_VOLTS_SHIFT 7
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_STANDBY_CONTROL_LDO_VOLTS_DEFAULT 0x00000001
-
-/* DDR34_PHY_CONTROL_REGS_0 :: STANDBY_CONTROL :: SKIP_MRS [06:06] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_STANDBY_CONTROL_SKIP_MRS_MASK 0x00000040
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_STANDBY_CONTROL_SKIP_MRS_SHIFT 6
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_STANDBY_CONTROL_SKIP_MRS_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: STANDBY_CONTROL :: RST_N [05:05] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_STANDBY_CONTROL_RST_N_MASK 0x00000020
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_STANDBY_CONTROL_RST_N_SHIFT 5
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_STANDBY_CONTROL_RST_N_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: STANDBY_CONTROL :: CKE [04:04] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_STANDBY_CONTROL_CKE_MASK 0x00000010
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_STANDBY_CONTROL_CKE_SHIFT 4
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_STANDBY_CONTROL_CKE_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: STANDBY_CONTROL :: STANDBY [03:00] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_STANDBY_CONTROL_STANDBY_MASK 0x0000000f
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_STANDBY_CONTROL_STANDBY_SHIFT 0
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_STANDBY_CONTROL_STANDBY_DEFAULT 0x00000000
-
-/***************************************************************************
- *DEBUG_FREEZE_ENABLE - Freeze-on-error enable register
- ***************************************************************************/
-/* DDR34_PHY_CONTROL_REGS_0 :: DEBUG_FREEZE_ENABLE :: reserved0 [31:05] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_DEBUG_FREEZE_ENABLE_reserved0_MASK 0xffffffe0
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_DEBUG_FREEZE_ENABLE_reserved0_SHIFT 5
-
-/* DDR34_PHY_CONTROL_REGS_0 :: DEBUG_FREEZE_ENABLE :: WLECC [04:04] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_DEBUG_FREEZE_ENABLE_WLECC_MASK 0x00000010
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_DEBUG_FREEZE_ENABLE_WLECC_SHIFT 4
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_DEBUG_FREEZE_ENABLE_WLECC_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: DEBUG_FREEZE_ENABLE :: WL1_BL1 [03:03] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_DEBUG_FREEZE_ENABLE_WL1_BL1_MASK 0x00000008
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_DEBUG_FREEZE_ENABLE_WL1_BL1_SHIFT 3
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_DEBUG_FREEZE_ENABLE_WL1_BL1_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: DEBUG_FREEZE_ENABLE :: WL1_BL0 [02:02] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_DEBUG_FREEZE_ENABLE_WL1_BL0_MASK 0x00000004
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_DEBUG_FREEZE_ENABLE_WL1_BL0_SHIFT 2
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_DEBUG_FREEZE_ENABLE_WL1_BL0_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: DEBUG_FREEZE_ENABLE :: WL0_BL1 [01:01] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_DEBUG_FREEZE_ENABLE_WL0_BL1_MASK 0x00000002
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_DEBUG_FREEZE_ENABLE_WL0_BL1_SHIFT 1
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_DEBUG_FREEZE_ENABLE_WL0_BL1_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: DEBUG_FREEZE_ENABLE :: WL0_BL0 [00:00] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_DEBUG_FREEZE_ENABLE_WL0_BL0_MASK 0x00000001
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_DEBUG_FREEZE_ENABLE_WL0_BL0_SHIFT 0
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_DEBUG_FREEZE_ENABLE_WL0_BL0_DEFAULT 0x00000000
-
-/***************************************************************************
- *DEBUG_MUX_CONTROL - Debug Mux Control register
- ***************************************************************************/
-/* DDR34_PHY_CONTROL_REGS_0 :: DEBUG_MUX_CONTROL :: reserved0 [31:11] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_DEBUG_MUX_CONTROL_reserved0_MASK 0xfffff800
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_DEBUG_MUX_CONTROL_reserved0_SHIFT 11
-
-/* DDR34_PHY_CONTROL_REGS_0 :: DEBUG_MUX_CONTROL :: BYTE_SEL [10:08] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_DEBUG_MUX_CONTROL_BYTE_SEL_MASK 0x00000700
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_DEBUG_MUX_CONTROL_BYTE_SEL_SHIFT 8
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_DEBUG_MUX_CONTROL_BYTE_SEL_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: DEBUG_MUX_CONTROL :: reserved1 [07:06] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_DEBUG_MUX_CONTROL_reserved1_MASK 0x000000c0
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_DEBUG_MUX_CONTROL_reserved1_SHIFT 6
-
-/* DDR34_PHY_CONTROL_REGS_0 :: DEBUG_MUX_CONTROL :: PHASE_SEL [05:04] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_DEBUG_MUX_CONTROL_PHASE_SEL_MASK 0x00000030
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_DEBUG_MUX_CONTROL_PHASE_SEL_SHIFT 4
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_DEBUG_MUX_CONTROL_PHASE_SEL_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: DEBUG_MUX_CONTROL :: SOURCE_SEL [03:00] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_DEBUG_MUX_CONTROL_SOURCE_SEL_MASK 0x0000000f
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_DEBUG_MUX_CONTROL_SOURCE_SEL_SHIFT 0
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_DEBUG_MUX_CONTROL_SOURCE_SEL_DEFAULT 0x00000000
-
-/***************************************************************************
- *DFI_CNTRL - DFI Interface Ownership Control register
- ***************************************************************************/
-/* DDR34_PHY_CONTROL_REGS_0 :: DFI_CNTRL :: reserved0 [31:07] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_DFI_CNTRL_reserved0_MASK 0xffffff80
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_DFI_CNTRL_reserved0_SHIFT 7
-
-/* DDR34_PHY_CONTROL_REGS_0 :: DFI_CNTRL :: DFI_CS1 [06:06] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_DFI_CNTRL_DFI_CS1_MASK 0x00000040
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_DFI_CNTRL_DFI_CS1_SHIFT 6
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_DFI_CNTRL_DFI_CS1_DEFAULT 0x00000001
-
-/* DDR34_PHY_CONTROL_REGS_0 :: DFI_CNTRL :: DFI_CS0 [05:05] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_DFI_CNTRL_DFI_CS0_MASK 0x00000020
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_DFI_CNTRL_DFI_CS0_SHIFT 5
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_DFI_CNTRL_DFI_CS0_DEFAULT 0x00000001
-
-/* DDR34_PHY_CONTROL_REGS_0 :: DFI_CNTRL :: DFI_RST_N [04:04] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_DFI_CNTRL_DFI_RST_N_MASK 0x00000010
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_DFI_CNTRL_DFI_RST_N_SHIFT 4
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_DFI_CNTRL_DFI_RST_N_DEFAULT 0x00000001
-
-/* DDR34_PHY_CONTROL_REGS_0 :: DFI_CNTRL :: DFI_CKE [03:03] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_DFI_CNTRL_DFI_CKE_MASK 0x00000008
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_DFI_CNTRL_DFI_CKE_SHIFT 3
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_DFI_CNTRL_DFI_CKE_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: DFI_CNTRL :: ACK_ENABLE [02:02] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_DFI_CNTRL_ACK_ENABLE_MASK 0x00000004
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_DFI_CNTRL_ACK_ENABLE_SHIFT 2
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_DFI_CNTRL_ACK_ENABLE_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: DFI_CNTRL :: ACK_STATUS [01:01] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_DFI_CNTRL_ACK_STATUS_MASK 0x00000002
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_DFI_CNTRL_ACK_STATUS_SHIFT 1
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_DFI_CNTRL_ACK_STATUS_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: DFI_CNTRL :: ASSERT_REQ [00:00] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_DFI_CNTRL_ASSERT_REQ_MASK 0x00000001
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_DFI_CNTRL_ASSERT_REQ_SHIFT 0
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_DFI_CNTRL_ASSERT_REQ_DEFAULT 0x00000001
-
-/***************************************************************************
- *WRITE_ODT_CNTRL - Write ODT Control register
- ***************************************************************************/
-/* DDR34_PHY_CONTROL_REGS_0 :: WRITE_ODT_CNTRL :: reserved0 [31:13] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_WRITE_ODT_CNTRL_reserved0_MASK 0xffffe000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_WRITE_ODT_CNTRL_reserved0_SHIFT 13
-
-/* DDR34_PHY_CONTROL_REGS_0 :: WRITE_ODT_CNTRL :: ODT_FORCE_VALUE [12:12] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_WRITE_ODT_CNTRL_ODT_FORCE_VALUE_MASK 0x00001000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_WRITE_ODT_CNTRL_ODT_FORCE_VALUE_SHIFT 12
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_WRITE_ODT_CNTRL_ODT_FORCE_VALUE_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: WRITE_ODT_CNTRL :: ODT_FORCE [11:11] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_WRITE_ODT_CNTRL_ODT_FORCE_MASK 0x00000800
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_WRITE_ODT_CNTRL_ODT_FORCE_SHIFT 11
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_WRITE_ODT_CNTRL_ODT_FORCE_DEFAULT 0x00000001
-
-/* DDR34_PHY_CONTROL_REGS_0 :: WRITE_ODT_CNTRL :: ODT_ENABLE [10:10] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_WRITE_ODT_CNTRL_ODT_ENABLE_MASK 0x00000400
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_WRITE_ODT_CNTRL_ODT_ENABLE_SHIFT 10
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_WRITE_ODT_CNTRL_ODT_ENABLE_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: WRITE_ODT_CNTRL :: ODT_LENGTH [09:06] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_WRITE_ODT_CNTRL_ODT_LENGTH_MASK 0x000003c0
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_WRITE_ODT_CNTRL_ODT_LENGTH_SHIFT 6
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_WRITE_ODT_CNTRL_ODT_LENGTH_DEFAULT 0x00000004
-
-/* DDR34_PHY_CONTROL_REGS_0 :: WRITE_ODT_CNTRL :: ODT_DELAY [05:00] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_WRITE_ODT_CNTRL_ODT_DELAY_MASK 0x0000003f
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_WRITE_ODT_CNTRL_ODT_DELAY_SHIFT 0
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_WRITE_ODT_CNTRL_ODT_DELAY_DEFAULT 0x00000010
-
-/***************************************************************************
- *ABI_PAR_CNTRL - ABI and PAR Control register
- ***************************************************************************/
-/* DDR34_PHY_CONTROL_REGS_0 :: ABI_PAR_CNTRL :: reserved0 [31:04] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_ABI_PAR_CNTRL_reserved0_MASK 0xfffffff0
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_ABI_PAR_CNTRL_reserved0_SHIFT 4
-
-/* DDR34_PHY_CONTROL_REGS_0 :: ABI_PAR_CNTRL :: PAR_INCLUDE_AUX [03:03] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_ABI_PAR_CNTRL_PAR_INCLUDE_AUX_MASK 0x00000008
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_ABI_PAR_CNTRL_PAR_INCLUDE_AUX_SHIFT 3
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_ABI_PAR_CNTRL_PAR_INCLUDE_AUX_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: ABI_PAR_CNTRL :: PAR_ENABLE [02:02] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_ABI_PAR_CNTRL_PAR_ENABLE_MASK 0x00000004
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_ABI_PAR_CNTRL_PAR_ENABLE_SHIFT 2
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_ABI_PAR_CNTRL_PAR_ENABLE_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: ABI_PAR_CNTRL :: ABI_INCLUDE_AUX [01:01] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_ABI_PAR_CNTRL_ABI_INCLUDE_AUX_MASK 0x00000002
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_ABI_PAR_CNTRL_ABI_INCLUDE_AUX_SHIFT 1
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_ABI_PAR_CNTRL_ABI_INCLUDE_AUX_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: ABI_PAR_CNTRL :: ABI_ENABLE [00:00] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_ABI_PAR_CNTRL_ABI_ENABLE_MASK 0x00000001
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_ABI_PAR_CNTRL_ABI_ENABLE_SHIFT 0
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_ABI_PAR_CNTRL_ABI_ENABLE_DEFAULT 0x00000000
-
-/***************************************************************************
- *ZQ_CAL - ZQ Calibration Control register
- ***************************************************************************/
-/* DDR34_PHY_CONTROL_REGS_0 :: ZQ_CAL :: reserved0 [31:20] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_ZQ_CAL_reserved0_MASK 0xfff00000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_ZQ_CAL_reserved0_SHIFT 20
-
-/* DDR34_PHY_CONTROL_REGS_0 :: ZQ_CAL :: ZQ_STATUS [19:19] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_ZQ_CAL_ZQ_STATUS_MASK 0x00080000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_ZQ_CAL_ZQ_STATUS_SHIFT 19
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_ZQ_CAL_ZQ_STATUS_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: ZQ_CAL :: ZQ_RXENB [18:18] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_ZQ_CAL_ZQ_RXENB_MASK 0x00040000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_ZQ_CAL_ZQ_RXENB_SHIFT 18
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_ZQ_CAL_ZQ_RXENB_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: ZQ_CAL :: ZQ_IDDQ [17:17] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_ZQ_CAL_ZQ_IDDQ_MASK 0x00020000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_ZQ_CAL_ZQ_IDDQ_SHIFT 17
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_ZQ_CAL_ZQ_IDDQ_DEFAULT 0x00000001
-
-/* DDR34_PHY_CONTROL_REGS_0 :: ZQ_CAL :: ZQ_DRIVE_N [16:12] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_ZQ_CAL_ZQ_DRIVE_N_MASK 0x0001f000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_ZQ_CAL_ZQ_DRIVE_N_SHIFT 12
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_ZQ_CAL_ZQ_DRIVE_N_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: ZQ_CAL :: ZQ_DRIVE_P [11:07] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_ZQ_CAL_ZQ_DRIVE_P_MASK 0x00000f80
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_ZQ_CAL_ZQ_DRIVE_P_SHIFT 7
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_ZQ_CAL_ZQ_DRIVE_P_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: ZQ_CAL :: ZQ_TX_MODE [06:03] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_ZQ_CAL_ZQ_TX_MODE_MASK 0x00000078
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_ZQ_CAL_ZQ_TX_MODE_SHIFT 3
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_ZQ_CAL_ZQ_TX_MODE_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: ZQ_CAL :: ZQ_RX_MODE [02:00] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_ZQ_CAL_ZQ_RX_MODE_MASK 0x00000007
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_ZQ_CAL_ZQ_RX_MODE_SHIFT 0
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_ZQ_CAL_ZQ_RX_MODE_DEFAULT 0x00000000
-
-/***************************************************************************
- *AC_SPARE_REG - Address and Control Spare register
- ***************************************************************************/
-/* DDR34_PHY_CONTROL_REGS_0 :: AC_SPARE_REG :: reserved_for_eco0 [31:00] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_AC_SPARE_REG_reserved_for_eco0_MASK 0xffffffff
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_AC_SPARE_REG_reserved_for_eco0_SHIFT 0
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_AC_SPARE_REG_reserved_for_eco0_DEFAULT 0x00000000
-
-#endif /* #ifndef BCHP_DDR34_PHY_CONTROL_REGS_0_H__ */
-
-/* End of File */
diff --git a/include/linux/brcmstb/7145a0/bchp_ddr34_phy_control_regs_1.h b/include/linux/brcmstb/7145a0/bchp_ddr34_phy_control_regs_1.h
deleted file mode 100644
index a5e54e5..0000000
--- a/include/linux/brcmstb/7145a0/bchp_ddr34_phy_control_regs_1.h
+++ /dev/null
@@ -1,4234 +0,0 @@
-/***************************************************************************
- * Copyright (c) 1999-2014, Broadcom Corporation
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
- *
- * Module Description:
- * DO NOT EDIT THIS FILE DIRECTLY
- *
- * This module was generated magically with RDB from a source description
- * file. You must edit the source file for changes to be made to this file.
- *
- *
- * Date: Generated on Wed Sep 3 13:17:33 2014
- * Full Compile MD5 Checksum a8ee62ccf9dde43435c825f266da463d
- * (minus title and desc)
- * MD5 Checksum e373b364a1742e13a0f9eb15fd8aa94f
- *
- * Compiled with: RDB Utility combo_header.pl
- * RDB Parser 3.0
- * unknown unknown
- * Perl Interpreter 5.008005
- * Operating System linux
- *
- * Revision History:
- *
- * $brcm_Log: $
- *
- ***************************************************************************/
-
-#ifndef BCHP_DDR34_PHY_CONTROL_REGS_1_H__
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_H__
-
-/***************************************************************************
- *DDR34_PHY_CONTROL_REGS_1 - DDR34 Address/Comand control registers
- ***************************************************************************/
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_REVISION 0x203c6000 /* Address & Control revision register */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_PLL_STATUS 0x203c6004 /* PHY PLL status register */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_PLL_CONFIG 0x203c6008 /* PHY PLL configuration register */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_PLL_CONTROL1 0x203c600c /* PHY PLL control register */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_PLL_CONTROL2 0x203c6010 /* PHY PLL control register */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_PLL_CONTROL3 0x203c6014 /* PHY PLL control register */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_PLL_DIVIDERS 0x203c6018 /* PHY PLL integer divider register */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_PLL_FRAC_DIVIDER 0x203c601c /* PHY PLL fractional divider register */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_PLL_SS_CONTROL 0x203c6020 /* PHY PLL spread spectrum control register */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_PLL_SS_LIMIT 0x203c6024 /* PHY PLL spread spectrum limit register */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_AUX_CONTROL 0x203c6028 /* Aux Control register */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_IDLE_PAD_CONTROL 0x203c602c /* Idle mode pad control register */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_IDLE_PAD_ENABLE0 0x203c6030 /* Idle mode pad enable register */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_IDLE_PAD_ENABLE1 0x203c6034 /* Idle mode pad enable register */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_DRIVE_PAD_CTL 0x203c6038 /* PVT Compensation control register */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_STATIC_PAD_CTL 0x203c603c /* pad rx and tx characteristics control register */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_DRAM_CONFIG 0x203c6040 /* DRAM configuration register */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_DRAM_TIMING1 0x203c6044 /* DRAM timing register #1 */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_DRAM_TIMING2 0x203c6048 /* DRAM timing register #2 */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_DRAM_TIMING3 0x203c604c /* DRAM timing register #3 */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_DRAM_TIMING4 0x203c6050 /* DRAM timing register #4 */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CALIBRATE 0x203c6060 /* PHY VDL calibration control register */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CALIB_STATUS1 0x203c6064 /* PHY VDL calibration status register #1 */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CALIB_STATUS2 0x203c6068 /* PHY VDL calibration status register #2 */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_MONITOR_CONTROL 0x203c606c /* PHY VDL delay monitoring control register */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_MONITOR_REF 0x203c6070 /* PHY VDL delay monitoring reference register */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_MONITOR_STATUS 0x203c6074 /* PHY VDL delay monitoring status register */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_MONITOR_OVERRIDE 0x203c6078 /* PHY VDL delay monitoring override register */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_MONITOR_OUT_CONTROL 0x203c607c /* PHY VDL delay monitoring output control register */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_MONITOR_OUT_STATUS 0x203c6080 /* PHY VDL delay monitoring output status register */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_MONITOR_OUT_STATUS_CLEAR 0x203c6084 /* PHY VDL delay monitoring output status clear register */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_AD00 0x203c6090 /* DDR interface signal AD[00] VDL control register */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_AD01 0x203c6094 /* DDR interface signal AD[01] VDL control register */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_AD02 0x203c6098 /* DDR interface signal AD[02] VDL control register */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_AD03 0x203c609c /* DDR interface signal AD[03] VDL control register */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_AD04 0x203c60a0 /* DDR interface signal AD[04] VDL control register */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_AD05 0x203c60a4 /* DDR interface signal AD[05] VDL control register */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_AD06 0x203c60a8 /* DDR interface signal AD[06] VDL control register */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_AD07 0x203c60ac /* DDR interface signal AD[07] VDL control register */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_AD08 0x203c60b0 /* DDR interface signal AD[08] VDL control register */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_AD09 0x203c60b4 /* DDR interface signal AD[09] VDL control register */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_AD10 0x203c60b8 /* DDR interface signal AD[10] VDL control register */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_AD11 0x203c60bc /* DDR interface signal AD[11] VDL control register */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_AD12 0x203c60c0 /* DDR interface signal AD[12] VDL control register */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_AD13 0x203c60c4 /* DDR interface signal AD[13] VDL control register */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_AD14 0x203c60c8 /* DDR interface signal AD[14] VDL control register */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_AD15 0x203c60cc /* DDR interface signal AD[15] VDL control register */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_BA0 0x203c60d0 /* DDR interface signal BA[0] VDL control register */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_BA1 0x203c60d4 /* DDR interface signal BA[1] VDL control register */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_BA2 0x203c60d8 /* DDR interface signal BA[2] VDL control register */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_AUX0 0x203c60dc /* DDR interface signal AUX[0] VDL control register */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_AUX1 0x203c60e0 /* DDR interface signal AUX[1] VDL control register */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_AUX2 0x203c60e4 /* DDR interface signal AUX[2] VDL control register */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_CS0 0x203c60e8 /* DDR interface signal CS0 VDL control register */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_CS1 0x203c60ec /* DDR interface signal CS1 VDL control register */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_PAR 0x203c60f0 /* DDR interface signal PAR VDL control register */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_RAS_N 0x203c60f4 /* DDR interface signal RAS_N VDL control register */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_CAS_N 0x203c60f8 /* DDR interface signal CAS_N VDL control register */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_CKE 0x203c60fc /* DDR interface signal CKE0 VDL control register */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_RST_N 0x203c6100 /* DDR interface signal RST_N VDL control register */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_ODT 0x203c6104 /* DDR interface signal ODT0 VDL control register */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_WE_N 0x203c6108 /* DDR interface signal WE_N VDL control register */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_DDR_CK_P 0x203c610c /* DDR interface signal DDR_CK-P VDL control register */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_DDR_CK_N 0x203c6110 /* DDR interface signal DDR_CK-N VDL control register */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CLK_CONTROL 0x203c6114 /* DDR interface signal Write Leveling CLK VDL control register */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_LDE_CONTROL 0x203c6118 /* DDR interface signal Write Leveling Capture Enable VDL control register */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_REFRESH 0x203c6130 /* Refresh engine controller */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_UPDATE_VDL 0x203c6134 /* Update VDL control register */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_UPDATE_VDL_SNOOP1 0x203c6138 /* Update VDL snoop control register #1 */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_UPDATE_VDL_SNOOP2 0x203c613c /* Update VDL snoop control register #2 */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_COMMAND_REG1 0x203c6140 /* DRAM Command Register #1 */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_COMMAND_AUX_REG1 0x203c6144 /* DRAM AUX_N Command Register #1 */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_COMMAND_REG2 0x203c6148 /* DRAM Command Register #2 */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_COMMAND_AUX_REG2 0x203c614c /* DRAM AUX_N Command Register #2 */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_COMMAND_REG3 0x203c6150 /* DRAM Command Register #3 */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_COMMAND_AUX_REG3 0x203c6154 /* DRAM AUX_N Command Register #3 */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_COMMAND_REG4 0x203c6158 /* DRAM Command Register #4 */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_COMMAND_AUX_REG4 0x203c615c /* DRAM AUX_N Command Register #4 */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_COMMAND_REG_TIMER 0x203c6160 /* DRAM Command Timer Register */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_MODE_REG0 0x203c6164 /* DDR3/DDR4/GDDR5 Mode Register 0 and LPDDR Mode Register 1 */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_MODE_REG1 0x203c6168 /* DDR3/DDR4/GDDR5 Mode Register 1 and LPDDR Mode Register 2 */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_MODE_REG2 0x203c616c /* DDR3/DDR4/GDDR5 Mode Register 2 and LPDDR Mode Register 3 */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_MODE_REG3 0x203c6170 /* DDR3/DDR4/GDDR5 Mode Register 3 and LPDDR Mode Register 9 */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_MODE_REG4 0x203c6174 /* DDR4/GDDR5 Mode Register 4 and LPDDR Mode Register 10 */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_MODE_REG5 0x203c6178 /* DDR4/GDDR5 Mode Register 5 and LPDDR Mode Register 16 */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_MODE_REG6 0x203c617c /* DDR4/GDDR5 Mode Register 6 and LPDDR Mode Register 17 */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_MODE_REG7 0x203c6180 /* DDR4/GDDR5 Mode Register 7 and LPDDR Mode Register 41 */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_MODE_REG8 0x203c6184 /* GDDR5 Mode Register 8 and LPDDR Mode Register 42 */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_MODE_REG15 0x203c6188 /* GDDR5 Mode Register 15 and LPDDR Mode Register 48 */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_MODE_REG63 0x203c618c /* LPDDR Mode Register 63 */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_ALERT_CLEAR 0x203c6190 /* DDR4 Alert status clear register */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_ALERT_STATUS 0x203c6194 /* DDR4 Alert status register */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_CA_PARITY 0x203c6198 /* DDR4 CA parity control register */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_CA_PLAYBACK_CONTROL 0x203c619c /* GDDR5 CA playback control register */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_CA_PLAYBACK_STATUS0 0x203c61a0 /* LPDDR3 and GDDR5 CA playback status register0 (for BL0 and BL1) */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_CA_PLAYBACK_STATUS1 0x203c61a4 /* LPDDR3 and GDDR5 CA playback status register1 (for BL2 and BL3) */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_WRITE_LEVELING_CONTROL 0x203c61ac /* Write leveling control register */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_WRITE_LEVELING_STATUS 0x203c61b0 /* Write leveling status register */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_READ_ENABLE_CONTROL 0x203c61b4 /* Read enable test cycle control register */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_READ_ENABLE_STATUS 0x203c61b8 /* Read enable test cycle status register */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_TRAFFIC_GEN_LFSR_SEED 0x203c61c0 /* Traffic generator seed register */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_TRAFFIC_GEN_ADDRESS1 0x203c61c4 /* Traffic generator address register #1 */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_TRAFFIC_GEN_ADDRESS2 0x203c61c8 /* Traffic generator address register #2 */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_TRAFFIC_GEN_CONTROL 0x203c61cc /* Traffic generator control register */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_TRAFFIC_GEN_DATA_CONTROL 0x203c61d0 /* Traffic generator data control register */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_TRAFFIC_GEN_DQ_MASK 0x203c61d4 /* Traffic generator DQ mask register */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_TRAFFIC_GEN_ECC_DQ_MASK 0x203c61d8 /* Traffic generator ECC DQ mask register */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_TRAFFIC_GEN_STATUS 0x203c61dc /* Traffic generator status register */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_TRAFFIC_GEN_DQ_STATUS 0x203c61e0 /* Traffic generator DQ status register */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_TRAFFIC_GEN_ECC_STATUS 0x203c61e4 /* Traffic generator ECC DQ status register */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_TRAFFIC_GEN_ERR_CNT_CONTROL 0x203c61e8 /* Traffic generator error count control register */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_TRAFFIC_GEN_ERR_CNT_STATUS 0x203c61ec /* Traffic generator error count status register */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VIRTUAL_VTT_CONTROL 0x203c61f0 /* Virtual VTT Control and Status register */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VIRTUAL_VTT_STATUS 0x203c61f4 /* Virtual VTT Control and Status register */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VIRTUAL_VTT_CONNECTIONS 0x203c61f8 /* Virtual VTT Connections register */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VIRTUAL_VTT_OVERRIDE 0x203c61fc /* Virtual VTT Override register */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VREF_DAC_CONTROL 0x203c6200 /* VREF DAC Control register */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_PHYBIST_CNTRL 0x203c6204 /* PhyBist Control Register */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_PHYBIST_SEED 0x203c6208 /* PhyBist Seed Register */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_PHYBIST_STATUS 0x203c620c /* PhyBist General Status Register */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_PHYBIST_CTL_STATUS 0x203c6210 /* PhyBist Per-Bit Control Pad Status Register */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_PHYBIST_BL0_STATUS 0x203c6214 /* PhyBist Byte Lane #0 Status Register */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_PHYBIST_BL1_STATUS 0x203c6218 /* PhyBist Byte Lane #1 Status Register */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_PHYBIST_BL2_STATUS 0x203c621c /* PhyBist Byte Lane #2 Status Register */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_PHYBIST_BL3_STATUS 0x203c6220 /* PhyBist Byte Lane #3 Status Register */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_PHYBIST_BL4_STATUS 0x203c6224 /* PhyBist Byte Lane #4 (ECC) Status Register */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_STANDBY_CONTROL 0x203c6230 /* Standby Control register */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_DEBUG_FREEZE_ENABLE 0x203c6234 /* Freeze-on-error enable register */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_DEBUG_MUX_CONTROL 0x203c6238 /* Debug Mux Control register */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_DFI_CNTRL 0x203c623c /* DFI Interface Ownership Control register */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_WRITE_ODT_CNTRL 0x203c6240 /* Write ODT Control register */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_ABI_PAR_CNTRL 0x203c6244 /* ABI and PAR Control register */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_ZQ_CAL 0x203c6248 /* ZQ Calibration Control register */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_AC_SPARE_REG 0x203c611c /* Address and Control Spare register */
-
-/***************************************************************************
- *REVISION - Address & Control revision register
- ***************************************************************************/
-/* DDR34_PHY_CONTROL_REGS_1 :: REVISION :: reserved0 [31:25] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_REVISION_reserved0_MASK 0xfe000000
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_REVISION_reserved0_SHIFT 25
-
-/* DDR34_PHY_CONTROL_REGS_1 :: REVISION :: PERFORMANCE [24:23] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_REVISION_PERFORMANCE_MASK 0x01800000
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_REVISION_PERFORMANCE_SHIFT 23
-
-/* DDR34_PHY_CONTROL_REGS_1 :: REVISION :: TECHNOLOGY [22:20] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_REVISION_TECHNOLOGY_MASK 0x00700000
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_REVISION_TECHNOLOGY_SHIFT 20
-
-/* DDR34_PHY_CONTROL_REGS_1 :: REVISION :: WB [19:19] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_REVISION_WB_MASK 0x00080000
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_REVISION_WB_SHIFT 19
-
-/* DDR34_PHY_CONTROL_REGS_1 :: REVISION :: BITS [18:16] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_REVISION_BITS_MASK 0x00070000
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_REVISION_BITS_SHIFT 16
-
-/* DDR34_PHY_CONTROL_REGS_1 :: REVISION :: MAJOR [15:08] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_REVISION_MAJOR_MASK 0x0000ff00
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_REVISION_MAJOR_SHIFT 8
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_REVISION_MAJOR_DEFAULT 0x000000e1
-
-/* DDR34_PHY_CONTROL_REGS_1 :: REVISION :: MINOR [07:00] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_REVISION_MINOR_MASK 0x000000ff
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_REVISION_MINOR_SHIFT 0
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_REVISION_MINOR_DEFAULT 0x00000001
-
-/***************************************************************************
- *PLL_STATUS - PHY PLL status register
- ***************************************************************************/
-/* DDR34_PHY_CONTROL_REGS_1 :: PLL_STATUS :: reserved0 [31:21] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_PLL_STATUS_reserved0_MASK 0xffe00000
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_PLL_STATUS_reserved0_SHIFT 21
-
-/* DDR34_PHY_CONTROL_REGS_1 :: PLL_STATUS :: reserved_for_eco1 [20:17] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_PLL_STATUS_reserved_for_eco1_MASK 0x001e0000
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_PLL_STATUS_reserved_for_eco1_SHIFT 17
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_PLL_STATUS_reserved_for_eco1_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_1 :: PLL_STATUS :: LOCK_LOST [16:16] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_PLL_STATUS_LOCK_LOST_MASK 0x00010000
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_PLL_STATUS_LOCK_LOST_SHIFT 16
-
-/* DDR34_PHY_CONTROL_REGS_1 :: PLL_STATUS :: CLOCKING_8X [15:15] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_PLL_STATUS_CLOCKING_8X_MASK 0x00008000
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_PLL_STATUS_CLOCKING_8X_SHIFT 15
-
-/* DDR34_PHY_CONTROL_REGS_1 :: PLL_STATUS :: CLOCKING_4X [14:14] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_PLL_STATUS_CLOCKING_4X_MASK 0x00004000
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_PLL_STATUS_CLOCKING_4X_SHIFT 14
-
-/* DDR34_PHY_CONTROL_REGS_1 :: PLL_STATUS :: CLOCKING_2X [13:13] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_PLL_STATUS_CLOCKING_2X_MASK 0x00002000
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_PLL_STATUS_CLOCKING_2X_SHIFT 13
-
-/* DDR34_PHY_CONTROL_REGS_1 :: PLL_STATUS :: STATUS [12:01] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_PLL_STATUS_STATUS_MASK 0x00001ffe
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_PLL_STATUS_STATUS_SHIFT 1
-
-/* DDR34_PHY_CONTROL_REGS_1 :: PLL_STATUS :: LOCK [00:00] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_PLL_STATUS_LOCK_MASK 0x00000001
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_PLL_STATUS_LOCK_SHIFT 0
-
-/***************************************************************************
- *PLL_CONFIG - PHY PLL configuration register
- ***************************************************************************/
-/* DDR34_PHY_CONTROL_REGS_1 :: PLL_CONFIG :: reserved0 [31:28] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_PLL_CONFIG_reserved0_MASK 0xf0000000
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_PLL_CONFIG_reserved0_SHIFT 28
-
-/* DDR34_PHY_CONTROL_REGS_1 :: PLL_CONFIG :: reserved_for_eco1 [27:27] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_PLL_CONFIG_reserved_for_eco1_MASK 0x08000000
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_PLL_CONFIG_reserved_for_eco1_SHIFT 27
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_PLL_CONFIG_reserved_for_eco1_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_1 :: PLL_CONFIG :: CK_LDO_REF_CTRL [26:25] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_PLL_CONFIG_CK_LDO_REF_CTRL_MASK 0x06000000
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_PLL_CONFIG_CK_LDO_REF_CTRL_SHIFT 25
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_PLL_CONFIG_CK_LDO_REF_CTRL_DEFAULT 0x00000001
-
-/* DDR34_PHY_CONTROL_REGS_1 :: PLL_CONFIG :: CK_LDO_BIAS [24:23] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_PLL_CONFIG_CK_LDO_BIAS_MASK 0x01800000
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_PLL_CONFIG_CK_LDO_BIAS_SHIFT 23
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_PLL_CONFIG_CK_LDO_BIAS_DEFAULT 0x00000003
-
-/* DDR34_PHY_CONTROL_REGS_1 :: PLL_CONFIG :: PLL_LDO_REF_SEL [22:22] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_PLL_CONFIG_PLL_LDO_REF_SEL_MASK 0x00400000
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_PLL_CONFIG_PLL_LDO_REF_SEL_SHIFT 22
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_PLL_CONFIG_PLL_LDO_REF_SEL_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_1 :: PLL_CONFIG :: PLL_LDO_REF_CTRL [21:20] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_PLL_CONFIG_PLL_LDO_REF_CTRL_MASK 0x00300000
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_PLL_CONFIG_PLL_LDO_REF_CTRL_SHIFT 20
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_PLL_CONFIG_PLL_LDO_REF_CTRL_DEFAULT 0x00000001
-
-/* DDR34_PHY_CONTROL_REGS_1 :: PLL_CONFIG :: PLL_LDO_BIAS [19:18] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_PLL_CONFIG_PLL_LDO_BIAS_MASK 0x000c0000
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_PLL_CONFIG_PLL_LDO_BIAS_SHIFT 18
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_PLL_CONFIG_PLL_LDO_BIAS_DEFAULT 0x00000003
-
-/* DDR34_PHY_CONTROL_REGS_1 :: PLL_CONFIG :: HOLD [17:17] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_PLL_CONFIG_HOLD_MASK 0x00020000
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_PLL_CONFIG_HOLD_SHIFT 17
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_PLL_CONFIG_HOLD_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_1 :: PLL_CONFIG :: ENABLE [16:16] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_PLL_CONFIG_ENABLE_MASK 0x00010000
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_PLL_CONFIG_ENABLE_SHIFT 16
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_PLL_CONFIG_ENABLE_DEFAULT 0x00000001
-
-/* DDR34_PHY_CONTROL_REGS_1 :: PLL_CONFIG :: reserved2 [15:14] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_PLL_CONFIG_reserved2_MASK 0x0000c000
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_PLL_CONFIG_reserved2_SHIFT 14
-
-/* DDR34_PHY_CONTROL_REGS_1 :: PLL_CONFIG :: FB_OFFSET [13:08] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_PLL_CONFIG_FB_OFFSET_MASK 0x00003f00
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_PLL_CONFIG_FB_OFFSET_SHIFT 8
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_PLL_CONFIG_FB_OFFSET_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_1 :: PLL_CONFIG :: reserved3 [07:05] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_PLL_CONFIG_reserved3_MASK 0x000000e0
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_PLL_CONFIG_reserved3_SHIFT 5
-
-/* DDR34_PHY_CONTROL_REGS_1 :: PLL_CONFIG :: RESET_POST_DIV [04:04] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_PLL_CONFIG_RESET_POST_DIV_MASK 0x00000010
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_PLL_CONFIG_RESET_POST_DIV_SHIFT 4
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_PLL_CONFIG_RESET_POST_DIV_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_1 :: PLL_CONFIG :: reserved4 [03:02] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_PLL_CONFIG_reserved4_MASK 0x0000000c
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_PLL_CONFIG_reserved4_SHIFT 2
-
-/* DDR34_PHY_CONTROL_REGS_1 :: PLL_CONFIG :: RESET [01:01] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_PLL_CONFIG_RESET_MASK 0x00000002
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_PLL_CONFIG_RESET_SHIFT 1
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_PLL_CONFIG_RESET_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_1 :: PLL_CONFIG :: PWRDN [00:00] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_PLL_CONFIG_PWRDN_MASK 0x00000001
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_PLL_CONFIG_PWRDN_SHIFT 0
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_PLL_CONFIG_PWRDN_DEFAULT 0x00000000
-
-/***************************************************************************
- *PLL_CONTROL1 - PHY PLL control register
- ***************************************************************************/
-/* DDR34_PHY_CONTROL_REGS_1 :: PLL_CONTROL1 :: reserved0 [31:10] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_PLL_CONTROL1_reserved0_MASK 0xfffffc00
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_PLL_CONTROL1_reserved0_SHIFT 10
-
-/* DDR34_PHY_CONTROL_REGS_1 :: PLL_CONTROL1 :: I_KP [09:06] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_PLL_CONTROL1_I_KP_MASK 0x000003c0
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_PLL_CONTROL1_I_KP_SHIFT 6
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_PLL_CONTROL1_I_KP_DEFAULT 0x00000005
-
-/* DDR34_PHY_CONTROL_REGS_1 :: PLL_CONTROL1 :: I_KI [05:03] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_PLL_CONTROL1_I_KI_MASK 0x00000038
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_PLL_CONTROL1_I_KI_SHIFT 3
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_PLL_CONTROL1_I_KI_DEFAULT 0x00000002
-
-/* DDR34_PHY_CONTROL_REGS_1 :: PLL_CONTROL1 :: I_KA [02:00] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_PLL_CONTROL1_I_KA_MASK 0x00000007
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_PLL_CONTROL1_I_KA_SHIFT 0
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_PLL_CONTROL1_I_KA_DEFAULT 0x00000000
-
-/***************************************************************************
- *PLL_CONTROL2 - PHY PLL control register
- ***************************************************************************/
-/* DDR34_PHY_CONTROL_REGS_1 :: PLL_CONTROL2 :: VCO_RANGE [31:30] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_PLL_CONTROL2_VCO_RANGE_MASK 0xc0000000
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_PLL_CONTROL2_VCO_RANGE_SHIFT 30
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_PLL_CONTROL2_VCO_RANGE_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_1 :: PLL_CONTROL2 :: UNUSED2 [29:29] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_PLL_CONTROL2_UNUSED2_MASK 0x20000000
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_PLL_CONTROL2_UNUSED2_SHIFT 29
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_PLL_CONTROL2_UNUSED2_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_1 :: PLL_CONTROL2 :: NDIV_RELOCK [28:28] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_PLL_CONTROL2_NDIV_RELOCK_MASK 0x10000000
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_PLL_CONTROL2_NDIV_RELOCK_SHIFT 28
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_PLL_CONTROL2_NDIV_RELOCK_DEFAULT 0x00000001
-
-/* DDR34_PHY_CONTROL_REGS_1 :: PLL_CONTROL2 :: FAST_LOCK [27:27] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_PLL_CONTROL2_FAST_LOCK_MASK 0x08000000
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_PLL_CONTROL2_FAST_LOCK_SHIFT 27
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_PLL_CONTROL2_FAST_LOCK_DEFAULT 0x00000001
-
-/* DDR34_PHY_CONTROL_REGS_1 :: PLL_CONTROL2 :: VCO_FB_DIV2 [26:26] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_PLL_CONTROL2_VCO_FB_DIV2_MASK 0x04000000
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_PLL_CONTROL2_VCO_FB_DIV2_SHIFT 26
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_PLL_CONTROL2_VCO_FB_DIV2_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_1 :: PLL_CONTROL2 :: POST_CTRL_RESETB [25:24] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_PLL_CONTROL2_POST_CTRL_RESETB_MASK 0x03000000
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_PLL_CONTROL2_POST_CTRL_RESETB_SHIFT 24
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_PLL_CONTROL2_POST_CTRL_RESETB_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_1 :: PLL_CONTROL2 :: PWM_RATE [23:22] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_PLL_CONTROL2_PWM_RATE_MASK 0x00c00000
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_PLL_CONTROL2_PWM_RATE_SHIFT 22
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_PLL_CONTROL2_PWM_RATE_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_1 :: PLL_CONTROL2 :: STAT_MODE [21:20] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_PLL_CONTROL2_STAT_MODE_MASK 0x00300000
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_PLL_CONTROL2_STAT_MODE_SHIFT 20
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_PLL_CONTROL2_STAT_MODE_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_1 :: PLL_CONTROL2 :: UNUSED1 [19:18] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_PLL_CONTROL2_UNUSED1_MASK 0x000c0000
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_PLL_CONTROL2_UNUSED1_SHIFT 18
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_PLL_CONTROL2_UNUSED1_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_1 :: PLL_CONTROL2 :: STAT_UPDATE [17:17] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_PLL_CONTROL2_STAT_UPDATE_MASK 0x00020000
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_PLL_CONTROL2_STAT_UPDATE_SHIFT 17
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_PLL_CONTROL2_STAT_UPDATE_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_1 :: PLL_CONTROL2 :: STAT_SELECT [16:14] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_PLL_CONTROL2_STAT_SELECT_MASK 0x0001c000
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_PLL_CONTROL2_STAT_SELECT_SHIFT 14
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_PLL_CONTROL2_STAT_SELECT_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_1 :: PLL_CONTROL2 :: STAT_RESET [13:13] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_PLL_CONTROL2_STAT_RESET_MASK 0x00002000
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_PLL_CONTROL2_STAT_RESET_SHIFT 13
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_PLL_CONTROL2_STAT_RESET_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_1 :: PLL_CONTROL2 :: DCO_CTRL_BYPASS_ENABLE [12:12] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_PLL_CONTROL2_DCO_CTRL_BYPASS_ENABLE_MASK 0x00001000
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_PLL_CONTROL2_DCO_CTRL_BYPASS_ENABLE_SHIFT 12
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_PLL_CONTROL2_DCO_CTRL_BYPASS_ENABLE_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_1 :: PLL_CONTROL2 :: DCO_CTRL_BYPASS [11:00] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_PLL_CONTROL2_DCO_CTRL_BYPASS_MASK 0x00000fff
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_PLL_CONTROL2_DCO_CTRL_BYPASS_SHIFT 0
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_PLL_CONTROL2_DCO_CTRL_BYPASS_DEFAULT 0x00000000
-
-/***************************************************************************
- *PLL_CONTROL3 - PHY PLL control register
- ***************************************************************************/
-/* DDR34_PHY_CONTROL_REGS_1 :: PLL_CONTROL3 :: PLL_CONTROL [31:00] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_PLL_CONTROL3_PLL_CONTROL_MASK 0xffffffff
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_PLL_CONTROL3_PLL_CONTROL_SHIFT 0
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_PLL_CONTROL3_PLL_CONTROL_DEFAULT 0x00000000
-
-/***************************************************************************
- *PLL_DIVIDERS - PHY PLL integer divider register
- ***************************************************************************/
-/* DDR34_PHY_CONTROL_REGS_1 :: PLL_DIVIDERS :: reserved0 [31:28] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_PLL_DIVIDERS_reserved0_MASK 0xf0000000
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_PLL_DIVIDERS_reserved0_SHIFT 28
-
-/* DDR34_PHY_CONTROL_REGS_1 :: PLL_DIVIDERS :: MDIV [27:20] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_PLL_DIVIDERS_MDIV_MASK 0x0ff00000
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_PLL_DIVIDERS_MDIV_SHIFT 20
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_PLL_DIVIDERS_MDIV_DEFAULT 0x00000001
-
-/* DDR34_PHY_CONTROL_REGS_1 :: PLL_DIVIDERS :: reserved1 [19:16] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_PLL_DIVIDERS_reserved1_MASK 0x000f0000
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_PLL_DIVIDERS_reserved1_SHIFT 16
-
-/* DDR34_PHY_CONTROL_REGS_1 :: PLL_DIVIDERS :: PDIV [15:12] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_PLL_DIVIDERS_PDIV_MASK 0x0000f000
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_PLL_DIVIDERS_PDIV_SHIFT 12
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_PLL_DIVIDERS_PDIV_DEFAULT 0x00000001
-
-/* DDR34_PHY_CONTROL_REGS_1 :: PLL_DIVIDERS :: reserved2 [11:10] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_PLL_DIVIDERS_reserved2_MASK 0x00000c00
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_PLL_DIVIDERS_reserved2_SHIFT 10
-
-/* DDR34_PHY_CONTROL_REGS_1 :: PLL_DIVIDERS :: NDIV_INT [09:00] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_PLL_DIVIDERS_NDIV_INT_MASK 0x000003ff
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_PLL_DIVIDERS_NDIV_INT_SHIFT 0
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_PLL_DIVIDERS_NDIV_INT_DEFAULT 0x00000010
-
-/***************************************************************************
- *PLL_FRAC_DIVIDER - PHY PLL fractional divider register
- ***************************************************************************/
-/* DDR34_PHY_CONTROL_REGS_1 :: PLL_FRAC_DIVIDER :: reserved0 [31:20] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_PLL_FRAC_DIVIDER_reserved0_MASK 0xfff00000
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_PLL_FRAC_DIVIDER_reserved0_SHIFT 20
-
-/* DDR34_PHY_CONTROL_REGS_1 :: PLL_FRAC_DIVIDER :: NDIV_FRAC [19:00] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_PLL_FRAC_DIVIDER_NDIV_FRAC_MASK 0x000fffff
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_PLL_FRAC_DIVIDER_NDIV_FRAC_SHIFT 0
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_PLL_FRAC_DIVIDER_NDIV_FRAC_DEFAULT 0x00000000
-
-/***************************************************************************
- *PLL_SS_CONTROL - PHY PLL spread spectrum control register
- ***************************************************************************/
-/* DDR34_PHY_CONTROL_REGS_1 :: PLL_SS_CONTROL :: reserved0 [31:20] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_PLL_SS_CONTROL_reserved0_MASK 0xfff00000
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_PLL_SS_CONTROL_reserved0_SHIFT 20
-
-/* DDR34_PHY_CONTROL_REGS_1 :: PLL_SS_CONTROL :: SSC_STEP [19:04] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_PLL_SS_CONTROL_SSC_STEP_MASK 0x000ffff0
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_PLL_SS_CONTROL_SSC_STEP_SHIFT 4
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_PLL_SS_CONTROL_SSC_STEP_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_1 :: PLL_SS_CONTROL :: reserved1 [03:01] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_PLL_SS_CONTROL_reserved1_MASK 0x0000000e
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_PLL_SS_CONTROL_reserved1_SHIFT 1
-
-/* DDR34_PHY_CONTROL_REGS_1 :: PLL_SS_CONTROL :: SSC_MODE [00:00] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_PLL_SS_CONTROL_SSC_MODE_MASK 0x00000001
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_PLL_SS_CONTROL_SSC_MODE_SHIFT 0
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_PLL_SS_CONTROL_SSC_MODE_DEFAULT 0x00000000
-
-/***************************************************************************
- *PLL_SS_LIMIT - PHY PLL spread spectrum limit register
- ***************************************************************************/
-/* DDR34_PHY_CONTROL_REGS_1 :: PLL_SS_LIMIT :: reserved0 [31:26] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_PLL_SS_LIMIT_reserved0_MASK 0xfc000000
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_PLL_SS_LIMIT_reserved0_SHIFT 26
-
-/* DDR34_PHY_CONTROL_REGS_1 :: PLL_SS_LIMIT :: SSC_LIMIT [25:04] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_PLL_SS_LIMIT_SSC_LIMIT_MASK 0x03fffff0
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_PLL_SS_LIMIT_SSC_LIMIT_SHIFT 4
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_PLL_SS_LIMIT_SSC_LIMIT_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_1 :: PLL_SS_LIMIT :: reserved1 [03:00] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_PLL_SS_LIMIT_reserved1_MASK 0x0000000f
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_PLL_SS_LIMIT_reserved1_SHIFT 0
-
-/***************************************************************************
- *AUX_CONTROL - Aux Control register
- ***************************************************************************/
-/* DDR34_PHY_CONTROL_REGS_1 :: AUX_CONTROL :: reserved0 [31:21] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_AUX_CONTROL_reserved0_MASK 0xffe00000
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_AUX_CONTROL_reserved0_SHIFT 21
-
-/* DDR34_PHY_CONTROL_REGS_1 :: AUX_CONTROL :: IS_ODT [20:16] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_AUX_CONTROL_IS_ODT_MASK 0x001f0000
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_AUX_CONTROL_IS_ODT_SHIFT 16
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_AUX_CONTROL_IS_ODT_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_1 :: AUX_CONTROL :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_AUX_CONTROL_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_AUX_CONTROL_reserved1_SHIFT 13
-
-/* DDR34_PHY_CONTROL_REGS_1 :: AUX_CONTROL :: IS_CS [12:08] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_AUX_CONTROL_IS_CS_MASK 0x00001f00
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_AUX_CONTROL_IS_CS_SHIFT 8
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_AUX_CONTROL_IS_CS_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_1 :: AUX_CONTROL :: reserved2 [07:05] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_AUX_CONTROL_reserved2_MASK 0x000000e0
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_AUX_CONTROL_reserved2_SHIFT 5
-
-/* DDR34_PHY_CONTROL_REGS_1 :: AUX_CONTROL :: IS_AD [04:00] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_AUX_CONTROL_IS_AD_MASK 0x0000001f
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_AUX_CONTROL_IS_AD_SHIFT 0
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_AUX_CONTROL_IS_AD_DEFAULT 0x00000000
-
-/***************************************************************************
- *IDLE_PAD_CONTROL - Idle mode pad control register
- ***************************************************************************/
-/* DDR34_PHY_CONTROL_REGS_1 :: IDLE_PAD_CONTROL :: IDLE [31:31] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_IDLE_PAD_CONTROL_IDLE_MASK 0x80000000
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_IDLE_PAD_CONTROL_IDLE_SHIFT 31
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_IDLE_PAD_CONTROL_IDLE_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_1 :: IDLE_PAD_CONTROL :: DIB_MODE [30:30] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_IDLE_PAD_CONTROL_DIB_MODE_MASK 0x40000000
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_IDLE_PAD_CONTROL_DIB_MODE_SHIFT 30
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_IDLE_PAD_CONTROL_DIB_MODE_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_1 :: IDLE_PAD_CONTROL :: reserved0 [29:08] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_IDLE_PAD_CONTROL_reserved0_MASK 0x3fffff00
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_IDLE_PAD_CONTROL_reserved0_SHIFT 8
-
-/* DDR34_PHY_CONTROL_REGS_1 :: IDLE_PAD_CONTROL :: reserved_for_eco1 [07:04] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_IDLE_PAD_CONTROL_reserved_for_eco1_MASK 0x000000f0
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_IDLE_PAD_CONTROL_reserved_for_eco1_SHIFT 4
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_IDLE_PAD_CONTROL_reserved_for_eco1_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_1 :: IDLE_PAD_CONTROL :: RXENB [03:03] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_IDLE_PAD_CONTROL_RXENB_MASK 0x00000008
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_IDLE_PAD_CONTROL_RXENB_SHIFT 3
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_IDLE_PAD_CONTROL_RXENB_DEFAULT 0x00000001
-
-/* DDR34_PHY_CONTROL_REGS_1 :: IDLE_PAD_CONTROL :: IDDQ [02:02] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_IDLE_PAD_CONTROL_IDDQ_MASK 0x00000004
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_IDLE_PAD_CONTROL_IDDQ_SHIFT 2
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_IDLE_PAD_CONTROL_IDDQ_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_1 :: IDLE_PAD_CONTROL :: DOUT_N [01:01] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_IDLE_PAD_CONTROL_DOUT_N_MASK 0x00000002
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_IDLE_PAD_CONTROL_DOUT_N_SHIFT 1
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_IDLE_PAD_CONTROL_DOUT_N_DEFAULT 0x00000001
-
-/* DDR34_PHY_CONTROL_REGS_1 :: IDLE_PAD_CONTROL :: DOUT_P [00:00] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_IDLE_PAD_CONTROL_DOUT_P_MASK 0x00000001
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_IDLE_PAD_CONTROL_DOUT_P_SHIFT 0
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_IDLE_PAD_CONTROL_DOUT_P_DEFAULT 0x00000000
-
-/***************************************************************************
- *IDLE_PAD_ENABLE0 - Idle mode pad enable register
- ***************************************************************************/
-/* DDR34_PHY_CONTROL_REGS_1 :: IDLE_PAD_ENABLE0 :: reserved0 [31:15] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_IDLE_PAD_ENABLE0_reserved0_MASK 0xffff8000
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_IDLE_PAD_ENABLE0_reserved0_SHIFT 15
-
-/* DDR34_PHY_CONTROL_REGS_1 :: IDLE_PAD_ENABLE0 :: reserved_for_eco1 [14:11] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_IDLE_PAD_ENABLE0_reserved_for_eco1_MASK 0x00007800
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_IDLE_PAD_ENABLE0_reserved_for_eco1_SHIFT 11
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_IDLE_PAD_ENABLE0_reserved_for_eco1_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_1 :: IDLE_PAD_ENABLE0 :: IO_IDLE_ENABLE [10:00] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_IDLE_PAD_ENABLE0_IO_IDLE_ENABLE_MASK 0x000007ff
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_IDLE_PAD_ENABLE0_IO_IDLE_ENABLE_SHIFT 0
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_IDLE_PAD_ENABLE0_IO_IDLE_ENABLE_DEFAULT 0x00000000
-
-/***************************************************************************
- *IDLE_PAD_ENABLE1 - Idle mode pad enable register
- ***************************************************************************/
-/* DDR34_PHY_CONTROL_REGS_1 :: IDLE_PAD_ENABLE1 :: reserved0 [31:22] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_IDLE_PAD_ENABLE1_reserved0_MASK 0xffc00000
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_IDLE_PAD_ENABLE1_reserved0_SHIFT 22
-
-/* DDR34_PHY_CONTROL_REGS_1 :: IDLE_PAD_ENABLE1 :: IO_IDLE_ENABLE [21:00] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_IDLE_PAD_ENABLE1_IO_IDLE_ENABLE_MASK 0x003fffff
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_IDLE_PAD_ENABLE1_IO_IDLE_ENABLE_SHIFT 0
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_IDLE_PAD_ENABLE1_IO_IDLE_ENABLE_DEFAULT 0x00000000
-
-/***************************************************************************
- *DRIVE_PAD_CTL - PVT Compensation control register
- ***************************************************************************/
-/* DDR34_PHY_CONTROL_REGS_1 :: DRIVE_PAD_CTL :: reserved_for_padding0 [31:30] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_DRIVE_PAD_CTL_reserved_for_padding0_MASK 0xc0000000
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_DRIVE_PAD_CTL_reserved_for_padding0_SHIFT 30
-
-/* DDR34_PHY_CONTROL_REGS_1 :: DRIVE_PAD_CTL :: ADDR_CTL_PD_IDLE_STRENGTH [29:25] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_DRIVE_PAD_CTL_ADDR_CTL_PD_IDLE_STRENGTH_MASK 0x3e000000
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_DRIVE_PAD_CTL_ADDR_CTL_PD_IDLE_STRENGTH_SHIFT 25
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_DRIVE_PAD_CTL_ADDR_CTL_PD_IDLE_STRENGTH_DEFAULT 0x0000001f
-
-/* DDR34_PHY_CONTROL_REGS_1 :: DRIVE_PAD_CTL :: ADDR_CTL_ND_IDLE_STRENGTH [24:20] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_DRIVE_PAD_CTL_ADDR_CTL_ND_IDLE_STRENGTH_MASK 0x01f00000
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_DRIVE_PAD_CTL_ADDR_CTL_ND_IDLE_STRENGTH_SHIFT 20
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_DRIVE_PAD_CTL_ADDR_CTL_ND_IDLE_STRENGTH_DEFAULT 0x0000001f
-
-/* DDR34_PHY_CONTROL_REGS_1 :: DRIVE_PAD_CTL :: ADDR_CTL_PD_TERM_STRENGTH [19:15] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_DRIVE_PAD_CTL_ADDR_CTL_PD_TERM_STRENGTH_MASK 0x000f8000
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_DRIVE_PAD_CTL_ADDR_CTL_PD_TERM_STRENGTH_SHIFT 15
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_DRIVE_PAD_CTL_ADDR_CTL_PD_TERM_STRENGTH_DEFAULT 0x00000008
-
-/* DDR34_PHY_CONTROL_REGS_1 :: DRIVE_PAD_CTL :: ADDR_CTL_ND_TERM_STRENGTH [14:10] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_DRIVE_PAD_CTL_ADDR_CTL_ND_TERM_STRENGTH_MASK 0x00007c00
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_DRIVE_PAD_CTL_ADDR_CTL_ND_TERM_STRENGTH_SHIFT 10
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_DRIVE_PAD_CTL_ADDR_CTL_ND_TERM_STRENGTH_DEFAULT 0x00000008
-
-/* DDR34_PHY_CONTROL_REGS_1 :: DRIVE_PAD_CTL :: ADDR_CTL_PD_STRENGTH [09:05] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_DRIVE_PAD_CTL_ADDR_CTL_PD_STRENGTH_MASK 0x000003e0
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_DRIVE_PAD_CTL_ADDR_CTL_PD_STRENGTH_SHIFT 5
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_DRIVE_PAD_CTL_ADDR_CTL_PD_STRENGTH_DEFAULT 0x0000001f
-
-/* DDR34_PHY_CONTROL_REGS_1 :: DRIVE_PAD_CTL :: ADDR_CTL_ND_STRENGTH [04:00] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_DRIVE_PAD_CTL_ADDR_CTL_ND_STRENGTH_MASK 0x0000001f
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_DRIVE_PAD_CTL_ADDR_CTL_ND_STRENGTH_SHIFT 0
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_DRIVE_PAD_CTL_ADDR_CTL_ND_STRENGTH_DEFAULT 0x0000001f
-
-/***************************************************************************
- *STATIC_PAD_CTL - pad rx and tx characteristics control register
- ***************************************************************************/
-/* DDR34_PHY_CONTROL_REGS_1 :: STATIC_PAD_CTL :: reserved0 [31:28] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_STATIC_PAD_CTL_reserved0_MASK 0xf0000000
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_STATIC_PAD_CTL_reserved0_SHIFT 28
-
-/* DDR34_PHY_CONTROL_REGS_1 :: STATIC_PAD_CTL :: AUTO_OEB [27:27] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_STATIC_PAD_CTL_AUTO_OEB_MASK 0x08000000
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_STATIC_PAD_CTL_AUTO_OEB_SHIFT 27
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_STATIC_PAD_CTL_AUTO_OEB_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_1 :: STATIC_PAD_CTL :: IDDQ_GDDR5 [26:26] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_STATIC_PAD_CTL_IDDQ_GDDR5_MASK 0x04000000
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_STATIC_PAD_CTL_IDDQ_GDDR5_SHIFT 26
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_STATIC_PAD_CTL_IDDQ_GDDR5_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_1 :: STATIC_PAD_CTL :: IDDQ_LPDDR [25:25] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_STATIC_PAD_CTL_IDDQ_LPDDR_MASK 0x02000000
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_STATIC_PAD_CTL_IDDQ_LPDDR_SHIFT 25
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_STATIC_PAD_CTL_IDDQ_LPDDR_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_1 :: STATIC_PAD_CTL :: IDDQ_CLK1 [24:24] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_STATIC_PAD_CTL_IDDQ_CLK1_MASK 0x01000000
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_STATIC_PAD_CTL_IDDQ_CLK1_SHIFT 24
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_STATIC_PAD_CTL_IDDQ_CLK1_DEFAULT 0x00000001
-
-/* DDR34_PHY_CONTROL_REGS_1 :: STATIC_PAD_CTL :: IDDQ_CLK0 [23:23] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_STATIC_PAD_CTL_IDDQ_CLK0_MASK 0x00800000
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_STATIC_PAD_CTL_IDDQ_CLK0_SHIFT 23
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_STATIC_PAD_CTL_IDDQ_CLK0_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_1 :: STATIC_PAD_CTL :: IDDQ_ODT [22:22] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_STATIC_PAD_CTL_IDDQ_ODT_MASK 0x00400000
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_STATIC_PAD_CTL_IDDQ_ODT_SHIFT 22
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_STATIC_PAD_CTL_IDDQ_ODT_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_1 :: STATIC_PAD_CTL :: IDDQ_PAR [21:21] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_STATIC_PAD_CTL_IDDQ_PAR_MASK 0x00200000
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_STATIC_PAD_CTL_IDDQ_PAR_SHIFT 21
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_STATIC_PAD_CTL_IDDQ_PAR_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_1 :: STATIC_PAD_CTL :: IDDQ_BA [20:20] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_STATIC_PAD_CTL_IDDQ_BA_MASK 0x00100000
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_STATIC_PAD_CTL_IDDQ_BA_SHIFT 20
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_STATIC_PAD_CTL_IDDQ_BA_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_1 :: STATIC_PAD_CTL :: IDDQ_AUX2 [19:19] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_STATIC_PAD_CTL_IDDQ_AUX2_MASK 0x00080000
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_STATIC_PAD_CTL_IDDQ_AUX2_SHIFT 19
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_STATIC_PAD_CTL_IDDQ_AUX2_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_1 :: STATIC_PAD_CTL :: IDDQ_AUX1 [18:18] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_STATIC_PAD_CTL_IDDQ_AUX1_MASK 0x00040000
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_STATIC_PAD_CTL_IDDQ_AUX1_SHIFT 18
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_STATIC_PAD_CTL_IDDQ_AUX1_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_1 :: STATIC_PAD_CTL :: IDDQ_AUX0 [17:17] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_STATIC_PAD_CTL_IDDQ_AUX0_MASK 0x00020000
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_STATIC_PAD_CTL_IDDQ_AUX0_SHIFT 17
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_STATIC_PAD_CTL_IDDQ_AUX0_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_1 :: STATIC_PAD_CTL :: IDDQ_CS1 [16:16] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_STATIC_PAD_CTL_IDDQ_CS1_MASK 0x00010000
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_STATIC_PAD_CTL_IDDQ_CS1_SHIFT 16
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_STATIC_PAD_CTL_IDDQ_CS1_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_1 :: STATIC_PAD_CTL :: IDDQ_A15 [15:15] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_STATIC_PAD_CTL_IDDQ_A15_MASK 0x00008000
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_STATIC_PAD_CTL_IDDQ_A15_SHIFT 15
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_STATIC_PAD_CTL_IDDQ_A15_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_1 :: STATIC_PAD_CTL :: IDDQ_A14 [14:14] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_STATIC_PAD_CTL_IDDQ_A14_MASK 0x00004000
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_STATIC_PAD_CTL_IDDQ_A14_SHIFT 14
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_STATIC_PAD_CTL_IDDQ_A14_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_1 :: STATIC_PAD_CTL :: IDDQ_A13 [13:13] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_STATIC_PAD_CTL_IDDQ_A13_MASK 0x00002000
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_STATIC_PAD_CTL_IDDQ_A13_SHIFT 13
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_STATIC_PAD_CTL_IDDQ_A13_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_1 :: STATIC_PAD_CTL :: IDDQ_A12 [12:12] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_STATIC_PAD_CTL_IDDQ_A12_MASK 0x00001000
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_STATIC_PAD_CTL_IDDQ_A12_SHIFT 12
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_STATIC_PAD_CTL_IDDQ_A12_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_1 :: STATIC_PAD_CTL :: IDDQ_A11 [11:11] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_STATIC_PAD_CTL_IDDQ_A11_MASK 0x00000800
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_STATIC_PAD_CTL_IDDQ_A11_SHIFT 11
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_STATIC_PAD_CTL_IDDQ_A11_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_1 :: STATIC_PAD_CTL :: IDDQ_A10 [10:10] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_STATIC_PAD_CTL_IDDQ_A10_MASK 0x00000400
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_STATIC_PAD_CTL_IDDQ_A10_SHIFT 10
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_STATIC_PAD_CTL_IDDQ_A10_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_1 :: STATIC_PAD_CTL :: IDDQ_A09 [09:09] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_STATIC_PAD_CTL_IDDQ_A09_MASK 0x00000200
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_STATIC_PAD_CTL_IDDQ_A09_SHIFT 9
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_STATIC_PAD_CTL_IDDQ_A09_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_1 :: STATIC_PAD_CTL :: reserved1 [08:08] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_STATIC_PAD_CTL_reserved1_MASK 0x00000100
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_STATIC_PAD_CTL_reserved1_SHIFT 8
-
-/* DDR34_PHY_CONTROL_REGS_1 :: STATIC_PAD_CTL :: TX_MODE [07:04] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_STATIC_PAD_CTL_TX_MODE_MASK 0x000000f0
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_STATIC_PAD_CTL_TX_MODE_SHIFT 4
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_STATIC_PAD_CTL_TX_MODE_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_1 :: STATIC_PAD_CTL :: reserved2 [03:03] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_STATIC_PAD_CTL_reserved2_MASK 0x00000008
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_STATIC_PAD_CTL_reserved2_SHIFT 3
-
-/* DDR34_PHY_CONTROL_REGS_1 :: STATIC_PAD_CTL :: RX_MODE [02:00] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_STATIC_PAD_CTL_RX_MODE_MASK 0x00000007
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_STATIC_PAD_CTL_RX_MODE_SHIFT 0
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_STATIC_PAD_CTL_RX_MODE_DEFAULT 0x00000000
-
-/***************************************************************************
- *DRAM_CONFIG - DRAM configuration register
- ***************************************************************************/
-/* DDR34_PHY_CONTROL_REGS_1 :: DRAM_CONFIG :: INIT_MODE [31:31] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_DRAM_CONFIG_INIT_MODE_MASK 0x80000000
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_DRAM_CONFIG_INIT_MODE_SHIFT 31
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_DRAM_CONFIG_INIT_MODE_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_1 :: DRAM_CONFIG :: reserved0 [30:28] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_DRAM_CONFIG_reserved0_MASK 0x70000000
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_DRAM_CONFIG_reserved0_SHIFT 28
-
-/* DDR34_PHY_CONTROL_REGS_1 :: DRAM_CONFIG :: ECC_ENABLED [27:27] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_DRAM_CONFIG_ECC_ENABLED_MASK 0x08000000
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_DRAM_CONFIG_ECC_ENABLED_SHIFT 27
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_DRAM_CONFIG_ECC_ENABLED_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_1 :: DRAM_CONFIG :: SPLIT_DQ_BUS [26:26] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_DRAM_CONFIG_SPLIT_DQ_BUS_MASK 0x04000000
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_DRAM_CONFIG_SPLIT_DQ_BUS_SHIFT 26
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_DRAM_CONFIG_SPLIT_DQ_BUS_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_1 :: DRAM_CONFIG :: BUS16 [25:25] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_DRAM_CONFIG_BUS16_MASK 0x02000000
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_DRAM_CONFIG_BUS16_SHIFT 25
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_DRAM_CONFIG_BUS16_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_1 :: DRAM_CONFIG :: BUS8 [24:24] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_DRAM_CONFIG_BUS8_MASK 0x01000000
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_DRAM_CONFIG_BUS8_SHIFT 24
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_DRAM_CONFIG_BUS8_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_1 :: DRAM_CONFIG :: reserved1 [23:16] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_DRAM_CONFIG_reserved1_MASK 0x00ff0000
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_DRAM_CONFIG_reserved1_SHIFT 16
-
-/* DDR34_PHY_CONTROL_REGS_1 :: DRAM_CONFIG :: EDC_MODE [15:15] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_DRAM_CONFIG_EDC_MODE_MASK 0x00008000
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_DRAM_CONFIG_EDC_MODE_SHIFT 15
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_DRAM_CONFIG_EDC_MODE_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_1 :: DRAM_CONFIG :: RDQS_MODE [14:14] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_DRAM_CONFIG_RDQS_MODE_MASK 0x00004000
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_DRAM_CONFIG_RDQS_MODE_SHIFT 14
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_DRAM_CONFIG_RDQS_MODE_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_1 :: DRAM_CONFIG :: GROUP_BITS [13:12] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_DRAM_CONFIG_GROUP_BITS_MASK 0x00003000
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_DRAM_CONFIG_GROUP_BITS_SHIFT 12
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_DRAM_CONFIG_GROUP_BITS_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_1 :: DRAM_CONFIG :: BANK_BITS [11:10] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_DRAM_CONFIG_BANK_BITS_MASK 0x00000c00
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_DRAM_CONFIG_BANK_BITS_SHIFT 10
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_DRAM_CONFIG_BANK_BITS_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_1 :: DRAM_CONFIG :: COL_BITS [09:08] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_DRAM_CONFIG_COL_BITS_MASK 0x00000300
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_DRAM_CONFIG_COL_BITS_SHIFT 8
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_DRAM_CONFIG_COL_BITS_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_1 :: DRAM_CONFIG :: ROW_BITS [07:04] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_DRAM_CONFIG_ROW_BITS_MASK 0x000000f0
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_DRAM_CONFIG_ROW_BITS_SHIFT 4
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_DRAM_CONFIG_ROW_BITS_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_1 :: DRAM_CONFIG :: DRAM_TYPE [03:00] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_DRAM_CONFIG_DRAM_TYPE_MASK 0x0000000f
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_DRAM_CONFIG_DRAM_TYPE_SHIFT 0
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_DRAM_CONFIG_DRAM_TYPE_DEFAULT 0x00000000
-
-/***************************************************************************
- *DRAM_TIMING1 - DRAM timing register #1
- ***************************************************************************/
-/* DDR34_PHY_CONTROL_REGS_1 :: DRAM_TIMING1 :: TRAS [31:24] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_DRAM_TIMING1_TRAS_MASK 0xff000000
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_DRAM_TIMING1_TRAS_SHIFT 24
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_DRAM_TIMING1_TRAS_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_1 :: DRAM_TIMING1 :: TRRD [23:16] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_DRAM_TIMING1_TRRD_MASK 0x00ff0000
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_DRAM_TIMING1_TRRD_SHIFT 16
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_DRAM_TIMING1_TRRD_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_1 :: DRAM_TIMING1 :: TRP [15:08] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_DRAM_TIMING1_TRP_MASK 0x0000ff00
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_DRAM_TIMING1_TRP_SHIFT 8
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_DRAM_TIMING1_TRP_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_1 :: DRAM_TIMING1 :: TRCD [07:00] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_DRAM_TIMING1_TRCD_MASK 0x000000ff
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_DRAM_TIMING1_TRCD_SHIFT 0
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_DRAM_TIMING1_TRCD_DEFAULT 0x00000000
-
-/***************************************************************************
- *DRAM_TIMING2 - DRAM timing register #2
- ***************************************************************************/
-/* DDR34_PHY_CONTROL_REGS_1 :: DRAM_TIMING2 :: TRTP [31:24] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_DRAM_TIMING2_TRTP_MASK 0xff000000
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_DRAM_TIMING2_TRTP_SHIFT 24
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_DRAM_TIMING2_TRTP_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_1 :: DRAM_TIMING2 :: TWR [23:16] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_DRAM_TIMING2_TWR_MASK 0x00ff0000
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_DRAM_TIMING2_TWR_SHIFT 16
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_DRAM_TIMING2_TWR_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_1 :: DRAM_TIMING2 :: TCWL [15:08] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_DRAM_TIMING2_TCWL_MASK 0x0000ff00
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_DRAM_TIMING2_TCWL_SHIFT 8
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_DRAM_TIMING2_TCWL_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_1 :: DRAM_TIMING2 :: TCAS [07:00] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_DRAM_TIMING2_TCAS_MASK 0x000000ff
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_DRAM_TIMING2_TCAS_SHIFT 0
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_DRAM_TIMING2_TCAS_DEFAULT 0x00000000
-
-/***************************************************************************
- *DRAM_TIMING3 - DRAM timing register #3
- ***************************************************************************/
-/* DDR34_PHY_CONTROL_REGS_1 :: DRAM_TIMING3 :: reserved0 [31:24] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_DRAM_TIMING3_reserved0_MASK 0xff000000
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_DRAM_TIMING3_reserved0_SHIFT 24
-
-/* DDR34_PHY_CONTROL_REGS_1 :: DRAM_TIMING3 :: TCAL [23:20] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_DRAM_TIMING3_TCAL_MASK 0x00f00000
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_DRAM_TIMING3_TCAL_SHIFT 20
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_DRAM_TIMING3_TCAL_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_1 :: DRAM_TIMING3 :: TRTW [19:16] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_DRAM_TIMING3_TRTW_MASK 0x000f0000
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_DRAM_TIMING3_TRTW_SHIFT 16
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_DRAM_TIMING3_TRTW_DEFAULT 0x00000004
-
-/* DDR34_PHY_CONTROL_REGS_1 :: DRAM_TIMING3 :: TWTR [15:12] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_DRAM_TIMING3_TWTR_MASK 0x0000f000
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_DRAM_TIMING3_TWTR_SHIFT 12
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_DRAM_TIMING3_TWTR_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_1 :: DRAM_TIMING3 :: TRFC [11:00] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_DRAM_TIMING3_TRFC_MASK 0x00000fff
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_DRAM_TIMING3_TRFC_SHIFT 0
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_DRAM_TIMING3_TRFC_DEFAULT 0x00000000
-
-/***************************************************************************
- *DRAM_TIMING4 - DRAM timing register #4
- ***************************************************************************/
-/* DDR34_PHY_CONTROL_REGS_1 :: DRAM_TIMING4 :: temp [31:00] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_DRAM_TIMING4_temp_MASK 0xffffffff
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_DRAM_TIMING4_temp_SHIFT 0
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_DRAM_TIMING4_temp_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CALIBRATE - PHY VDL calibration control register
- ***************************************************************************/
-/* DDR34_PHY_CONTROL_REGS_1 :: VDL_CALIBRATE :: reserved0 [31:10] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CALIBRATE_reserved0_MASK 0xfffffc00
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CALIBRATE_reserved0_SHIFT 10
-
-/* DDR34_PHY_CONTROL_REGS_1 :: VDL_CALIBRATE :: reserved_for_eco1 [09:06] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CALIBRATE_reserved_for_eco1_MASK 0x000003c0
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CALIBRATE_reserved_for_eco1_SHIFT 6
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CALIBRATE_reserved_for_eco1_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_1 :: VDL_CALIBRATE :: HALF_STEPS [05:05] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CALIBRATE_HALF_STEPS_MASK 0x00000020
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CALIBRATE_HALF_STEPS_SHIFT 5
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CALIBRATE_HALF_STEPS_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_1 :: VDL_CALIBRATE :: UPDATE_FAST [04:04] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CALIBRATE_UPDATE_FAST_MASK 0x00000010
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CALIBRATE_UPDATE_FAST_SHIFT 4
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CALIBRATE_UPDATE_FAST_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_1 :: VDL_CALIBRATE :: UPDATE_REGS [03:03] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CALIBRATE_UPDATE_REGS_MASK 0x00000008
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CALIBRATE_UPDATE_REGS_SHIFT 3
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CALIBRATE_UPDATE_REGS_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_1 :: VDL_CALIBRATE :: CALIB_FTM2 [02:02] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CALIBRATE_CALIB_FTM2_MASK 0x00000004
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CALIBRATE_CALIB_FTM2_SHIFT 2
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CALIBRATE_CALIB_FTM2_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_1 :: VDL_CALIBRATE :: CALIB_PHYBIST [01:01] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CALIBRATE_CALIB_PHYBIST_MASK 0x00000002
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CALIBRATE_CALIB_PHYBIST_SHIFT 1
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CALIBRATE_CALIB_PHYBIST_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_1 :: VDL_CALIBRATE :: CALIB_ONCE [00:00] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CALIBRATE_CALIB_ONCE_MASK 0x00000001
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CALIBRATE_CALIB_ONCE_SHIFT 0
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CALIBRATE_CALIB_ONCE_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CALIB_STATUS1 - PHY VDL calibration status register #1
- ***************************************************************************/
-/* DDR34_PHY_CONTROL_REGS_1 :: VDL_CALIB_STATUS1 :: reserved0 [31:18] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CALIB_STATUS1_reserved0_MASK 0xfffc0000
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CALIB_STATUS1_reserved0_SHIFT 18
-
-/* DDR34_PHY_CONTROL_REGS_1 :: VDL_CALIB_STATUS1 :: CALIB_TOTAL_STEPS [17:08] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CALIB_STATUS1_CALIB_TOTAL_STEPS_MASK 0x0003ff00
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CALIB_STATUS1_CALIB_TOTAL_STEPS_SHIFT 8
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CALIB_STATUS1_CALIB_TOTAL_STEPS_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_1 :: VDL_CALIB_STATUS1 :: reserved1 [07:06] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CALIB_STATUS1_reserved1_MASK 0x000000c0
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CALIB_STATUS1_reserved1_SHIFT 6
-
-/* DDR34_PHY_CONTROL_REGS_1 :: VDL_CALIB_STATUS1 :: CALIB_BUS_ERROR [05:05] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CALIB_STATUS1_CALIB_BUS_ERROR_MASK 0x00000020
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CALIB_STATUS1_CALIB_BUS_ERROR_SHIFT 5
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CALIB_STATUS1_CALIB_BUS_ERROR_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_1 :: VDL_CALIB_STATUS1 :: CALIB_REGS_DONE [04:04] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CALIB_STATUS1_CALIB_REGS_DONE_MASK 0x00000010
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CALIB_STATUS1_CALIB_REGS_DONE_SHIFT 4
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CALIB_STATUS1_CALIB_REGS_DONE_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_1 :: VDL_CALIB_STATUS1 :: CALIB_LOCK_6B [03:03] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CALIB_STATUS1_CALIB_LOCK_6B_MASK 0x00000008
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CALIB_STATUS1_CALIB_LOCK_6B_SHIFT 3
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CALIB_STATUS1_CALIB_LOCK_6B_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_1 :: VDL_CALIB_STATUS1 :: CALIB_LOCK_4B [02:02] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CALIB_STATUS1_CALIB_LOCK_4B_MASK 0x00000004
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CALIB_STATUS1_CALIB_LOCK_4B_SHIFT 2
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CALIB_STATUS1_CALIB_LOCK_4B_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_1 :: VDL_CALIB_STATUS1 :: CALIB_LOCK_2B [01:01] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CALIB_STATUS1_CALIB_LOCK_2B_MASK 0x00000002
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CALIB_STATUS1_CALIB_LOCK_2B_SHIFT 1
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CALIB_STATUS1_CALIB_LOCK_2B_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_1 :: VDL_CALIB_STATUS1 :: CALIB_IDLE [00:00] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CALIB_STATUS1_CALIB_IDLE_MASK 0x00000001
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CALIB_STATUS1_CALIB_IDLE_SHIFT 0
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CALIB_STATUS1_CALIB_IDLE_DEFAULT 0x00000001
-
-/***************************************************************************
- *VDL_CALIB_STATUS2 - PHY VDL calibration status register #2
- ***************************************************************************/
-/* DDR34_PHY_CONTROL_REGS_1 :: VDL_CALIB_STATUS2 :: reserved0 [31:22] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CALIB_STATUS2_reserved0_MASK 0xffc00000
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CALIB_STATUS2_reserved0_SHIFT 22
-
-/* DDR34_PHY_CONTROL_REGS_1 :: VDL_CALIB_STATUS2 :: CALIB_4B_STEPS [21:12] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CALIB_STATUS2_CALIB_4B_STEPS_MASK 0x003ff000
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CALIB_STATUS2_CALIB_4B_STEPS_SHIFT 12
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CALIB_STATUS2_CALIB_4B_STEPS_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_1 :: VDL_CALIB_STATUS2 :: reserved1 [11:10] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CALIB_STATUS2_reserved1_MASK 0x00000c00
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CALIB_STATUS2_reserved1_SHIFT 10
-
-/* DDR34_PHY_CONTROL_REGS_1 :: VDL_CALIB_STATUS2 :: CALIB_2B_STEPS [09:00] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CALIB_STATUS2_CALIB_2B_STEPS_MASK 0x000003ff
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CALIB_STATUS2_CALIB_2B_STEPS_SHIFT 0
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CALIB_STATUS2_CALIB_2B_STEPS_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_MONITOR_CONTROL - PHY VDL delay monitoring control register
- ***************************************************************************/
-/* DDR34_PHY_CONTROL_REGS_1 :: VDL_MONITOR_CONTROL :: reserved0 [31:22] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_MONITOR_CONTROL_reserved0_MASK 0xffc00000
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_MONITOR_CONTROL_reserved0_SHIFT 22
-
-/* DDR34_PHY_CONTROL_REGS_1 :: VDL_MONITOR_CONTROL :: INTERVAL [21:08] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_MONITOR_CONTROL_INTERVAL_MASK 0x003fff00
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_MONITOR_CONTROL_INTERVAL_SHIFT 8
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_MONITOR_CONTROL_INTERVAL_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_1 :: VDL_MONITOR_CONTROL :: reserved1 [07:04] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_MONITOR_CONTROL_reserved1_MASK 0x000000f0
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_MONITOR_CONTROL_reserved1_SHIFT 4
-
-/* DDR34_PHY_CONTROL_REGS_1 :: VDL_MONITOR_CONTROL :: UPDATE [03:03] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_MONITOR_CONTROL_UPDATE_MASK 0x00000008
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_MONITOR_CONTROL_UPDATE_SHIFT 3
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_MONITOR_CONTROL_UPDATE_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_1 :: VDL_MONITOR_CONTROL :: FORCE [02:02] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_MONITOR_CONTROL_FORCE_MASK 0x00000004
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_MONITOR_CONTROL_FORCE_SHIFT 2
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_MONITOR_CONTROL_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_1 :: VDL_MONITOR_CONTROL :: DATA_RATE [01:01] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_MONITOR_CONTROL_DATA_RATE_MASK 0x00000002
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_MONITOR_CONTROL_DATA_RATE_SHIFT 1
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_MONITOR_CONTROL_DATA_RATE_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_1 :: VDL_MONITOR_CONTROL :: ENABLE [00:00] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_MONITOR_CONTROL_ENABLE_MASK 0x00000001
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_MONITOR_CONTROL_ENABLE_SHIFT 0
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_MONITOR_CONTROL_ENABLE_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_MONITOR_REF - PHY VDL delay monitoring reference register
- ***************************************************************************/
-/* DDR34_PHY_CONTROL_REGS_1 :: VDL_MONITOR_REF :: reserved0 [31:22] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_MONITOR_REF_reserved0_MASK 0xffc00000
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_MONITOR_REF_reserved0_SHIFT 22
-
-/* DDR34_PHY_CONTROL_REGS_1 :: VDL_MONITOR_REF :: MONITOR_4B_STEPS [21:12] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_MONITOR_REF_MONITOR_4B_STEPS_MASK 0x003ff000
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_MONITOR_REF_MONITOR_4B_STEPS_SHIFT 12
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_MONITOR_REF_MONITOR_4B_STEPS_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_1 :: VDL_MONITOR_REF :: reserved1 [11:10] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_MONITOR_REF_reserved1_MASK 0x00000c00
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_MONITOR_REF_reserved1_SHIFT 10
-
-/* DDR34_PHY_CONTROL_REGS_1 :: VDL_MONITOR_REF :: MONITOR_2B_STEPS [09:00] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_MONITOR_REF_MONITOR_2B_STEPS_MASK 0x000003ff
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_MONITOR_REF_MONITOR_2B_STEPS_SHIFT 0
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_MONITOR_REF_MONITOR_2B_STEPS_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_MONITOR_STATUS - PHY VDL delay monitoring status register
- ***************************************************************************/
-/* DDR34_PHY_CONTROL_REGS_1 :: VDL_MONITOR_STATUS :: reserved0 [31:29] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_MONITOR_STATUS_reserved0_MASK 0xe0000000
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_MONITOR_STATUS_reserved0_SHIFT 29
-
-/* DDR34_PHY_CONTROL_REGS_1 :: VDL_MONITOR_STATUS :: MONITOR_BUS_ERROR [28:28] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_MONITOR_STATUS_MONITOR_BUS_ERROR_MASK 0x10000000
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_MONITOR_STATUS_MONITOR_BUS_ERROR_SHIFT 28
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_MONITOR_STATUS_MONITOR_BUS_ERROR_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_1 :: VDL_MONITOR_STATUS :: reserved1 [27:25] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_MONITOR_STATUS_reserved1_MASK 0x0e000000
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_MONITOR_STATUS_reserved1_SHIFT 25
-
-/* DDR34_PHY_CONTROL_REGS_1 :: VDL_MONITOR_STATUS :: MONITOR_ADJ [24:20] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_MONITOR_STATUS_MONITOR_ADJ_MASK 0x01f00000
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_MONITOR_STATUS_MONITOR_ADJ_SHIFT 20
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_MONITOR_STATUS_MONITOR_ADJ_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_1 :: VDL_MONITOR_STATUS :: MONITOR_CHANGE [19:12] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_MONITOR_STATUS_MONITOR_CHANGE_MASK 0x000ff000
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_MONITOR_STATUS_MONITOR_CHANGE_SHIFT 12
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_MONITOR_STATUS_MONITOR_CHANGE_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_1 :: VDL_MONITOR_STATUS :: reserved2 [11:10] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_MONITOR_STATUS_reserved2_MASK 0x00000c00
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_MONITOR_STATUS_reserved2_SHIFT 10
-
-/* DDR34_PHY_CONTROL_REGS_1 :: VDL_MONITOR_STATUS :: MONITOR_TOTAL [09:00] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_MONITOR_STATUS_MONITOR_TOTAL_MASK 0x000003ff
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_MONITOR_STATUS_MONITOR_TOTAL_SHIFT 0
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_MONITOR_STATUS_MONITOR_TOTAL_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_MONITOR_OVERRIDE - PHY VDL delay monitoring override register
- ***************************************************************************/
-/* DDR34_PHY_CONTROL_REGS_1 :: VDL_MONITOR_OVERRIDE :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_MONITOR_OVERRIDE_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_MONITOR_OVERRIDE_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_MONITOR_OVERRIDE_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_1 :: VDL_MONITOR_OVERRIDE :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_MONITOR_OVERRIDE_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_MONITOR_OVERRIDE_reserved0_SHIFT 17
-
-/* DDR34_PHY_CONTROL_REGS_1 :: VDL_MONITOR_OVERRIDE :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_MONITOR_OVERRIDE_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_MONITOR_OVERRIDE_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_MONITOR_OVERRIDE_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_1 :: VDL_MONITOR_OVERRIDE :: reserved1 [15:09] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_MONITOR_OVERRIDE_reserved1_MASK 0x0000fe00
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_MONITOR_OVERRIDE_reserved1_SHIFT 9
-
-/* DDR34_PHY_CONTROL_REGS_1 :: VDL_MONITOR_OVERRIDE :: ADJ [08:04] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_MONITOR_OVERRIDE_ADJ_MASK 0x000001f0
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_MONITOR_OVERRIDE_ADJ_SHIFT 4
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_MONITOR_OVERRIDE_ADJ_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_1 :: VDL_MONITOR_OVERRIDE :: reserved2 [03:01] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_MONITOR_OVERRIDE_reserved2_MASK 0x0000000e
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_MONITOR_OVERRIDE_reserved2_SHIFT 1
-
-/* DDR34_PHY_CONTROL_REGS_1 :: VDL_MONITOR_OVERRIDE :: ENABLE [00:00] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_MONITOR_OVERRIDE_ENABLE_MASK 0x00000001
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_MONITOR_OVERRIDE_ENABLE_SHIFT 0
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_MONITOR_OVERRIDE_ENABLE_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_MONITOR_OUT_CONTROL - PHY VDL delay monitoring output control register
- ***************************************************************************/
-/* DDR34_PHY_CONTROL_REGS_1 :: VDL_MONITOR_OUT_CONTROL :: reserved0 [31:20] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_MONITOR_OUT_CONTROL_reserved0_MASK 0xfff00000
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_MONITOR_OUT_CONTROL_reserved0_SHIFT 20
-
-/* DDR34_PHY_CONTROL_REGS_1 :: VDL_MONITOR_OUT_CONTROL :: LOWER_LIMIT [19:12] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_MONITOR_OUT_CONTROL_LOWER_LIMIT_MASK 0x000ff000
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_MONITOR_OUT_CONTROL_LOWER_LIMIT_SHIFT 12
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_MONITOR_OUT_CONTROL_LOWER_LIMIT_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_1 :: VDL_MONITOR_OUT_CONTROL :: UPPER_LIMIT [11:04] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_MONITOR_OUT_CONTROL_UPPER_LIMIT_MASK 0x00000ff0
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_MONITOR_OUT_CONTROL_UPPER_LIMIT_SHIFT 4
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_MONITOR_OUT_CONTROL_UPPER_LIMIT_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_1 :: VDL_MONITOR_OUT_CONTROL :: reserved1 [03:01] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_MONITOR_OUT_CONTROL_reserved1_MASK 0x0000000e
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_MONITOR_OUT_CONTROL_reserved1_SHIFT 1
-
-/* DDR34_PHY_CONTROL_REGS_1 :: VDL_MONITOR_OUT_CONTROL :: ENABLE [00:00] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_MONITOR_OUT_CONTROL_ENABLE_MASK 0x00000001
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_MONITOR_OUT_CONTROL_ENABLE_SHIFT 0
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_MONITOR_OUT_CONTROL_ENABLE_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_MONITOR_OUT_STATUS - PHY VDL delay monitoring output status register
- ***************************************************************************/
-/* DDR34_PHY_CONTROL_REGS_1 :: VDL_MONITOR_OUT_STATUS :: reserved0 [31:24] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_MONITOR_OUT_STATUS_reserved0_MASK 0xff000000
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_MONITOR_OUT_STATUS_reserved0_SHIFT 24
-
-/* DDR34_PHY_CONTROL_REGS_1 :: VDL_MONITOR_OUT_STATUS :: MONITOR_CHANGE [23:16] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_MONITOR_OUT_STATUS_MONITOR_CHANGE_MASK 0x00ff0000
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_MONITOR_OUT_STATUS_MONITOR_CHANGE_SHIFT 16
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_MONITOR_OUT_STATUS_MONITOR_CHANGE_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_1 :: VDL_MONITOR_OUT_STATUS :: reserved1 [15:14] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_MONITOR_OUT_STATUS_reserved1_MASK 0x0000c000
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_MONITOR_OUT_STATUS_reserved1_SHIFT 14
-
-/* DDR34_PHY_CONTROL_REGS_1 :: VDL_MONITOR_OUT_STATUS :: MONITOR_TOTAL [13:04] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_MONITOR_OUT_STATUS_MONITOR_TOTAL_MASK 0x00003ff0
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_MONITOR_OUT_STATUS_MONITOR_TOTAL_SHIFT 4
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_MONITOR_OUT_STATUS_MONITOR_TOTAL_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_1 :: VDL_MONITOR_OUT_STATUS :: reserved2 [03:01] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_MONITOR_OUT_STATUS_reserved2_MASK 0x0000000e
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_MONITOR_OUT_STATUS_reserved2_SHIFT 1
-
-/* DDR34_PHY_CONTROL_REGS_1 :: VDL_MONITOR_OUT_STATUS :: VALID [00:00] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_MONITOR_OUT_STATUS_VALID_MASK 0x00000001
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_MONITOR_OUT_STATUS_VALID_SHIFT 0
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_MONITOR_OUT_STATUS_VALID_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_MONITOR_OUT_STATUS_CLEAR - PHY VDL delay monitoring output status clear register
- ***************************************************************************/
-/* DDR34_PHY_CONTROL_REGS_1 :: VDL_MONITOR_OUT_STATUS_CLEAR :: reserved0 [31:01] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_MONITOR_OUT_STATUS_CLEAR_reserved0_MASK 0xfffffffe
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_MONITOR_OUT_STATUS_CLEAR_reserved0_SHIFT 1
-
-/* DDR34_PHY_CONTROL_REGS_1 :: VDL_MONITOR_OUT_STATUS_CLEAR :: CLEAR [00:00] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_MONITOR_OUT_STATUS_CLEAR_CLEAR_MASK 0x00000001
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_MONITOR_OUT_STATUS_CLEAR_CLEAR_SHIFT 0
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_MONITOR_OUT_STATUS_CLEAR_CLEAR_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_AD00 - DDR interface signal AD[00] VDL control register
- ***************************************************************************/
-/* DDR34_PHY_CONTROL_REGS_1 :: VDL_CONTROL_AD00 :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_AD00_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_AD00_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_AD00_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_1 :: VDL_CONTROL_AD00 :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_AD00_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_AD00_reserved0_SHIFT 17
-
-/* DDR34_PHY_CONTROL_REGS_1 :: VDL_CONTROL_AD00 :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_AD00_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_AD00_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_AD00_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_1 :: VDL_CONTROL_AD00 :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_AD00_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_AD00_reserved1_SHIFT 13
-
-/* DDR34_PHY_CONTROL_REGS_1 :: VDL_CONTROL_AD00 :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_AD00_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_AD00_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_AD00_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_1 :: VDL_CONTROL_AD00 :: reserved2 [11:09] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_AD00_reserved2_MASK 0x00000e00
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_AD00_reserved2_SHIFT 9
-
-/* DDR34_PHY_CONTROL_REGS_1 :: VDL_CONTROL_AD00 :: VDL_STEP [08:00] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_AD00_VDL_STEP_MASK 0x000001ff
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_AD00_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_AD00_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_AD01 - DDR interface signal AD[01] VDL control register
- ***************************************************************************/
-/* DDR34_PHY_CONTROL_REGS_1 :: VDL_CONTROL_AD01 :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_AD01_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_AD01_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_AD01_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_1 :: VDL_CONTROL_AD01 :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_AD01_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_AD01_reserved0_SHIFT 17
-
-/* DDR34_PHY_CONTROL_REGS_1 :: VDL_CONTROL_AD01 :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_AD01_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_AD01_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_AD01_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_1 :: VDL_CONTROL_AD01 :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_AD01_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_AD01_reserved1_SHIFT 13
-
-/* DDR34_PHY_CONTROL_REGS_1 :: VDL_CONTROL_AD01 :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_AD01_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_AD01_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_AD01_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_1 :: VDL_CONTROL_AD01 :: reserved2 [11:09] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_AD01_reserved2_MASK 0x00000e00
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_AD01_reserved2_SHIFT 9
-
-/* DDR34_PHY_CONTROL_REGS_1 :: VDL_CONTROL_AD01 :: VDL_STEP [08:00] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_AD01_VDL_STEP_MASK 0x000001ff
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_AD01_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_AD01_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_AD02 - DDR interface signal AD[02] VDL control register
- ***************************************************************************/
-/* DDR34_PHY_CONTROL_REGS_1 :: VDL_CONTROL_AD02 :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_AD02_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_AD02_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_AD02_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_1 :: VDL_CONTROL_AD02 :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_AD02_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_AD02_reserved0_SHIFT 17
-
-/* DDR34_PHY_CONTROL_REGS_1 :: VDL_CONTROL_AD02 :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_AD02_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_AD02_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_AD02_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_1 :: VDL_CONTROL_AD02 :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_AD02_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_AD02_reserved1_SHIFT 13
-
-/* DDR34_PHY_CONTROL_REGS_1 :: VDL_CONTROL_AD02 :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_AD02_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_AD02_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_AD02_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_1 :: VDL_CONTROL_AD02 :: reserved2 [11:09] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_AD02_reserved2_MASK 0x00000e00
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_AD02_reserved2_SHIFT 9
-
-/* DDR34_PHY_CONTROL_REGS_1 :: VDL_CONTROL_AD02 :: VDL_STEP [08:00] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_AD02_VDL_STEP_MASK 0x000001ff
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_AD02_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_AD02_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_AD03 - DDR interface signal AD[03] VDL control register
- ***************************************************************************/
-/* DDR34_PHY_CONTROL_REGS_1 :: VDL_CONTROL_AD03 :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_AD03_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_AD03_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_AD03_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_1 :: VDL_CONTROL_AD03 :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_AD03_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_AD03_reserved0_SHIFT 17
-
-/* DDR34_PHY_CONTROL_REGS_1 :: VDL_CONTROL_AD03 :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_AD03_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_AD03_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_AD03_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_1 :: VDL_CONTROL_AD03 :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_AD03_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_AD03_reserved1_SHIFT 13
-
-/* DDR34_PHY_CONTROL_REGS_1 :: VDL_CONTROL_AD03 :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_AD03_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_AD03_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_AD03_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_1 :: VDL_CONTROL_AD03 :: reserved2 [11:09] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_AD03_reserved2_MASK 0x00000e00
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_AD03_reserved2_SHIFT 9
-
-/* DDR34_PHY_CONTROL_REGS_1 :: VDL_CONTROL_AD03 :: VDL_STEP [08:00] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_AD03_VDL_STEP_MASK 0x000001ff
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_AD03_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_AD03_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_AD04 - DDR interface signal AD[04] VDL control register
- ***************************************************************************/
-/* DDR34_PHY_CONTROL_REGS_1 :: VDL_CONTROL_AD04 :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_AD04_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_AD04_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_AD04_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_1 :: VDL_CONTROL_AD04 :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_AD04_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_AD04_reserved0_SHIFT 17
-
-/* DDR34_PHY_CONTROL_REGS_1 :: VDL_CONTROL_AD04 :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_AD04_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_AD04_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_AD04_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_1 :: VDL_CONTROL_AD04 :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_AD04_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_AD04_reserved1_SHIFT 13
-
-/* DDR34_PHY_CONTROL_REGS_1 :: VDL_CONTROL_AD04 :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_AD04_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_AD04_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_AD04_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_1 :: VDL_CONTROL_AD04 :: reserved2 [11:09] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_AD04_reserved2_MASK 0x00000e00
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_AD04_reserved2_SHIFT 9
-
-/* DDR34_PHY_CONTROL_REGS_1 :: VDL_CONTROL_AD04 :: VDL_STEP [08:00] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_AD04_VDL_STEP_MASK 0x000001ff
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_AD04_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_AD04_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_AD05 - DDR interface signal AD[05] VDL control register
- ***************************************************************************/
-/* DDR34_PHY_CONTROL_REGS_1 :: VDL_CONTROL_AD05 :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_AD05_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_AD05_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_AD05_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_1 :: VDL_CONTROL_AD05 :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_AD05_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_AD05_reserved0_SHIFT 17
-
-/* DDR34_PHY_CONTROL_REGS_1 :: VDL_CONTROL_AD05 :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_AD05_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_AD05_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_AD05_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_1 :: VDL_CONTROL_AD05 :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_AD05_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_AD05_reserved1_SHIFT 13
-
-/* DDR34_PHY_CONTROL_REGS_1 :: VDL_CONTROL_AD05 :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_AD05_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_AD05_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_AD05_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_1 :: VDL_CONTROL_AD05 :: reserved2 [11:09] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_AD05_reserved2_MASK 0x00000e00
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_AD05_reserved2_SHIFT 9
-
-/* DDR34_PHY_CONTROL_REGS_1 :: VDL_CONTROL_AD05 :: VDL_STEP [08:00] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_AD05_VDL_STEP_MASK 0x000001ff
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_AD05_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_AD05_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_AD06 - DDR interface signal AD[06] VDL control register
- ***************************************************************************/
-/* DDR34_PHY_CONTROL_REGS_1 :: VDL_CONTROL_AD06 :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_AD06_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_AD06_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_AD06_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_1 :: VDL_CONTROL_AD06 :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_AD06_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_AD06_reserved0_SHIFT 17
-
-/* DDR34_PHY_CONTROL_REGS_1 :: VDL_CONTROL_AD06 :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_AD06_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_AD06_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_AD06_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_1 :: VDL_CONTROL_AD06 :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_AD06_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_AD06_reserved1_SHIFT 13
-
-/* DDR34_PHY_CONTROL_REGS_1 :: VDL_CONTROL_AD06 :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_AD06_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_AD06_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_AD06_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_1 :: VDL_CONTROL_AD06 :: reserved2 [11:09] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_AD06_reserved2_MASK 0x00000e00
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_AD06_reserved2_SHIFT 9
-
-/* DDR34_PHY_CONTROL_REGS_1 :: VDL_CONTROL_AD06 :: VDL_STEP [08:00] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_AD06_VDL_STEP_MASK 0x000001ff
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_AD06_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_AD06_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_AD07 - DDR interface signal AD[07] VDL control register
- ***************************************************************************/
-/* DDR34_PHY_CONTROL_REGS_1 :: VDL_CONTROL_AD07 :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_AD07_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_AD07_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_AD07_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_1 :: VDL_CONTROL_AD07 :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_AD07_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_AD07_reserved0_SHIFT 17
-
-/* DDR34_PHY_CONTROL_REGS_1 :: VDL_CONTROL_AD07 :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_AD07_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_AD07_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_AD07_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_1 :: VDL_CONTROL_AD07 :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_AD07_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_AD07_reserved1_SHIFT 13
-
-/* DDR34_PHY_CONTROL_REGS_1 :: VDL_CONTROL_AD07 :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_AD07_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_AD07_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_AD07_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_1 :: VDL_CONTROL_AD07 :: reserved2 [11:09] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_AD07_reserved2_MASK 0x00000e00
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_AD07_reserved2_SHIFT 9
-
-/* DDR34_PHY_CONTROL_REGS_1 :: VDL_CONTROL_AD07 :: VDL_STEP [08:00] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_AD07_VDL_STEP_MASK 0x000001ff
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_AD07_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_AD07_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_AD08 - DDR interface signal AD[08] VDL control register
- ***************************************************************************/
-/* DDR34_PHY_CONTROL_REGS_1 :: VDL_CONTROL_AD08 :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_AD08_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_AD08_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_AD08_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_1 :: VDL_CONTROL_AD08 :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_AD08_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_AD08_reserved0_SHIFT 17
-
-/* DDR34_PHY_CONTROL_REGS_1 :: VDL_CONTROL_AD08 :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_AD08_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_AD08_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_AD08_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_1 :: VDL_CONTROL_AD08 :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_AD08_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_AD08_reserved1_SHIFT 13
-
-/* DDR34_PHY_CONTROL_REGS_1 :: VDL_CONTROL_AD08 :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_AD08_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_AD08_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_AD08_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_1 :: VDL_CONTROL_AD08 :: reserved2 [11:09] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_AD08_reserved2_MASK 0x00000e00
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_AD08_reserved2_SHIFT 9
-
-/* DDR34_PHY_CONTROL_REGS_1 :: VDL_CONTROL_AD08 :: VDL_STEP [08:00] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_AD08_VDL_STEP_MASK 0x000001ff
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_AD08_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_AD08_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_AD09 - DDR interface signal AD[09] VDL control register
- ***************************************************************************/
-/* DDR34_PHY_CONTROL_REGS_1 :: VDL_CONTROL_AD09 :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_AD09_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_AD09_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_AD09_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_1 :: VDL_CONTROL_AD09 :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_AD09_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_AD09_reserved0_SHIFT 17
-
-/* DDR34_PHY_CONTROL_REGS_1 :: VDL_CONTROL_AD09 :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_AD09_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_AD09_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_AD09_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_1 :: VDL_CONTROL_AD09 :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_AD09_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_AD09_reserved1_SHIFT 13
-
-/* DDR34_PHY_CONTROL_REGS_1 :: VDL_CONTROL_AD09 :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_AD09_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_AD09_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_AD09_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_1 :: VDL_CONTROL_AD09 :: reserved2 [11:09] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_AD09_reserved2_MASK 0x00000e00
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_AD09_reserved2_SHIFT 9
-
-/* DDR34_PHY_CONTROL_REGS_1 :: VDL_CONTROL_AD09 :: VDL_STEP [08:00] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_AD09_VDL_STEP_MASK 0x000001ff
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_AD09_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_AD09_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_AD10 - DDR interface signal AD[10] VDL control register
- ***************************************************************************/
-/* DDR34_PHY_CONTROL_REGS_1 :: VDL_CONTROL_AD10 :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_AD10_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_AD10_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_AD10_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_1 :: VDL_CONTROL_AD10 :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_AD10_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_AD10_reserved0_SHIFT 17
-
-/* DDR34_PHY_CONTROL_REGS_1 :: VDL_CONTROL_AD10 :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_AD10_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_AD10_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_AD10_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_1 :: VDL_CONTROL_AD10 :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_AD10_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_AD10_reserved1_SHIFT 13
-
-/* DDR34_PHY_CONTROL_REGS_1 :: VDL_CONTROL_AD10 :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_AD10_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_AD10_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_AD10_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_1 :: VDL_CONTROL_AD10 :: reserved2 [11:09] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_AD10_reserved2_MASK 0x00000e00
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_AD10_reserved2_SHIFT 9
-
-/* DDR34_PHY_CONTROL_REGS_1 :: VDL_CONTROL_AD10 :: VDL_STEP [08:00] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_AD10_VDL_STEP_MASK 0x000001ff
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_AD10_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_AD10_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_AD11 - DDR interface signal AD[11] VDL control register
- ***************************************************************************/
-/* DDR34_PHY_CONTROL_REGS_1 :: VDL_CONTROL_AD11 :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_AD11_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_AD11_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_AD11_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_1 :: VDL_CONTROL_AD11 :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_AD11_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_AD11_reserved0_SHIFT 17
-
-/* DDR34_PHY_CONTROL_REGS_1 :: VDL_CONTROL_AD11 :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_AD11_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_AD11_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_AD11_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_1 :: VDL_CONTROL_AD11 :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_AD11_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_AD11_reserved1_SHIFT 13
-
-/* DDR34_PHY_CONTROL_REGS_1 :: VDL_CONTROL_AD11 :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_AD11_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_AD11_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_AD11_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_1 :: VDL_CONTROL_AD11 :: reserved2 [11:09] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_AD11_reserved2_MASK 0x00000e00
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_AD11_reserved2_SHIFT 9
-
-/* DDR34_PHY_CONTROL_REGS_1 :: VDL_CONTROL_AD11 :: VDL_STEP [08:00] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_AD11_VDL_STEP_MASK 0x000001ff
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_AD11_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_AD11_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_AD12 - DDR interface signal AD[12] VDL control register
- ***************************************************************************/
-/* DDR34_PHY_CONTROL_REGS_1 :: VDL_CONTROL_AD12 :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_AD12_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_AD12_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_AD12_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_1 :: VDL_CONTROL_AD12 :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_AD12_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_AD12_reserved0_SHIFT 17
-
-/* DDR34_PHY_CONTROL_REGS_1 :: VDL_CONTROL_AD12 :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_AD12_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_AD12_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_AD12_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_1 :: VDL_CONTROL_AD12 :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_AD12_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_AD12_reserved1_SHIFT 13
-
-/* DDR34_PHY_CONTROL_REGS_1 :: VDL_CONTROL_AD12 :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_AD12_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_AD12_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_AD12_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_1 :: VDL_CONTROL_AD12 :: reserved2 [11:09] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_AD12_reserved2_MASK 0x00000e00
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_AD12_reserved2_SHIFT 9
-
-/* DDR34_PHY_CONTROL_REGS_1 :: VDL_CONTROL_AD12 :: VDL_STEP [08:00] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_AD12_VDL_STEP_MASK 0x000001ff
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_AD12_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_AD12_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_AD13 - DDR interface signal AD[13] VDL control register
- ***************************************************************************/
-/* DDR34_PHY_CONTROL_REGS_1 :: VDL_CONTROL_AD13 :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_AD13_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_AD13_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_AD13_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_1 :: VDL_CONTROL_AD13 :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_AD13_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_AD13_reserved0_SHIFT 17
-
-/* DDR34_PHY_CONTROL_REGS_1 :: VDL_CONTROL_AD13 :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_AD13_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_AD13_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_AD13_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_1 :: VDL_CONTROL_AD13 :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_AD13_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_AD13_reserved1_SHIFT 13
-
-/* DDR34_PHY_CONTROL_REGS_1 :: VDL_CONTROL_AD13 :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_AD13_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_AD13_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_AD13_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_1 :: VDL_CONTROL_AD13 :: reserved2 [11:09] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_AD13_reserved2_MASK 0x00000e00
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_AD13_reserved2_SHIFT 9
-
-/* DDR34_PHY_CONTROL_REGS_1 :: VDL_CONTROL_AD13 :: VDL_STEP [08:00] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_AD13_VDL_STEP_MASK 0x000001ff
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_AD13_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_AD13_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_AD14 - DDR interface signal AD[14] VDL control register
- ***************************************************************************/
-/* DDR34_PHY_CONTROL_REGS_1 :: VDL_CONTROL_AD14 :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_AD14_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_AD14_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_AD14_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_1 :: VDL_CONTROL_AD14 :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_AD14_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_AD14_reserved0_SHIFT 17
-
-/* DDR34_PHY_CONTROL_REGS_1 :: VDL_CONTROL_AD14 :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_AD14_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_AD14_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_AD14_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_1 :: VDL_CONTROL_AD14 :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_AD14_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_AD14_reserved1_SHIFT 13
-
-/* DDR34_PHY_CONTROL_REGS_1 :: VDL_CONTROL_AD14 :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_AD14_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_AD14_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_AD14_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_1 :: VDL_CONTROL_AD14 :: reserved2 [11:09] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_AD14_reserved2_MASK 0x00000e00
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_AD14_reserved2_SHIFT 9
-
-/* DDR34_PHY_CONTROL_REGS_1 :: VDL_CONTROL_AD14 :: VDL_STEP [08:00] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_AD14_VDL_STEP_MASK 0x000001ff
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_AD14_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_AD14_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_AD15 - DDR interface signal AD[15] VDL control register
- ***************************************************************************/
-/* DDR34_PHY_CONTROL_REGS_1 :: VDL_CONTROL_AD15 :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_AD15_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_AD15_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_AD15_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_1 :: VDL_CONTROL_AD15 :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_AD15_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_AD15_reserved0_SHIFT 17
-
-/* DDR34_PHY_CONTROL_REGS_1 :: VDL_CONTROL_AD15 :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_AD15_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_AD15_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_AD15_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_1 :: VDL_CONTROL_AD15 :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_AD15_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_AD15_reserved1_SHIFT 13
-
-/* DDR34_PHY_CONTROL_REGS_1 :: VDL_CONTROL_AD15 :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_AD15_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_AD15_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_AD15_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_1 :: VDL_CONTROL_AD15 :: reserved2 [11:09] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_AD15_reserved2_MASK 0x00000e00
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_AD15_reserved2_SHIFT 9
-
-/* DDR34_PHY_CONTROL_REGS_1 :: VDL_CONTROL_AD15 :: VDL_STEP [08:00] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_AD15_VDL_STEP_MASK 0x000001ff
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_AD15_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_AD15_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_BA0 - DDR interface signal BA[0] VDL control register
- ***************************************************************************/
-/* DDR34_PHY_CONTROL_REGS_1 :: VDL_CONTROL_BA0 :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_BA0_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_BA0_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_BA0_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_1 :: VDL_CONTROL_BA0 :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_BA0_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_BA0_reserved0_SHIFT 17
-
-/* DDR34_PHY_CONTROL_REGS_1 :: VDL_CONTROL_BA0 :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_BA0_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_BA0_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_BA0_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_1 :: VDL_CONTROL_BA0 :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_BA0_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_BA0_reserved1_SHIFT 13
-
-/* DDR34_PHY_CONTROL_REGS_1 :: VDL_CONTROL_BA0 :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_BA0_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_BA0_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_BA0_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_1 :: VDL_CONTROL_BA0 :: reserved2 [11:09] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_BA0_reserved2_MASK 0x00000e00
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_BA0_reserved2_SHIFT 9
-
-/* DDR34_PHY_CONTROL_REGS_1 :: VDL_CONTROL_BA0 :: VDL_STEP [08:00] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_BA0_VDL_STEP_MASK 0x000001ff
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_BA0_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_BA0_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_BA1 - DDR interface signal BA[1] VDL control register
- ***************************************************************************/
-/* DDR34_PHY_CONTROL_REGS_1 :: VDL_CONTROL_BA1 :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_BA1_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_BA1_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_BA1_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_1 :: VDL_CONTROL_BA1 :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_BA1_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_BA1_reserved0_SHIFT 17
-
-/* DDR34_PHY_CONTROL_REGS_1 :: VDL_CONTROL_BA1 :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_BA1_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_BA1_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_BA1_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_1 :: VDL_CONTROL_BA1 :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_BA1_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_BA1_reserved1_SHIFT 13
-
-/* DDR34_PHY_CONTROL_REGS_1 :: VDL_CONTROL_BA1 :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_BA1_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_BA1_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_BA1_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_1 :: VDL_CONTROL_BA1 :: reserved2 [11:09] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_BA1_reserved2_MASK 0x00000e00
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_BA1_reserved2_SHIFT 9
-
-/* DDR34_PHY_CONTROL_REGS_1 :: VDL_CONTROL_BA1 :: VDL_STEP [08:00] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_BA1_VDL_STEP_MASK 0x000001ff
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_BA1_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_BA1_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_BA2 - DDR interface signal BA[2] VDL control register
- ***************************************************************************/
-/* DDR34_PHY_CONTROL_REGS_1 :: VDL_CONTROL_BA2 :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_BA2_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_BA2_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_BA2_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_1 :: VDL_CONTROL_BA2 :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_BA2_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_BA2_reserved0_SHIFT 17
-
-/* DDR34_PHY_CONTROL_REGS_1 :: VDL_CONTROL_BA2 :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_BA2_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_BA2_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_BA2_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_1 :: VDL_CONTROL_BA2 :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_BA2_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_BA2_reserved1_SHIFT 13
-
-/* DDR34_PHY_CONTROL_REGS_1 :: VDL_CONTROL_BA2 :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_BA2_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_BA2_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_BA2_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_1 :: VDL_CONTROL_BA2 :: reserved2 [11:09] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_BA2_reserved2_MASK 0x00000e00
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_BA2_reserved2_SHIFT 9
-
-/* DDR34_PHY_CONTROL_REGS_1 :: VDL_CONTROL_BA2 :: VDL_STEP [08:00] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_BA2_VDL_STEP_MASK 0x000001ff
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_BA2_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_BA2_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_AUX0 - DDR interface signal AUX[0] VDL control register
- ***************************************************************************/
-/* DDR34_PHY_CONTROL_REGS_1 :: VDL_CONTROL_AUX0 :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_AUX0_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_AUX0_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_AUX0_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_1 :: VDL_CONTROL_AUX0 :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_AUX0_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_AUX0_reserved0_SHIFT 17
-
-/* DDR34_PHY_CONTROL_REGS_1 :: VDL_CONTROL_AUX0 :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_AUX0_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_AUX0_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_AUX0_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_1 :: VDL_CONTROL_AUX0 :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_AUX0_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_AUX0_reserved1_SHIFT 13
-
-/* DDR34_PHY_CONTROL_REGS_1 :: VDL_CONTROL_AUX0 :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_AUX0_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_AUX0_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_AUX0_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_1 :: VDL_CONTROL_AUX0 :: reserved2 [11:09] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_AUX0_reserved2_MASK 0x00000e00
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_AUX0_reserved2_SHIFT 9
-
-/* DDR34_PHY_CONTROL_REGS_1 :: VDL_CONTROL_AUX0 :: VDL_STEP [08:00] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_AUX0_VDL_STEP_MASK 0x000001ff
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_AUX0_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_AUX0_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_AUX1 - DDR interface signal AUX[1] VDL control register
- ***************************************************************************/
-/* DDR34_PHY_CONTROL_REGS_1 :: VDL_CONTROL_AUX1 :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_AUX1_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_AUX1_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_AUX1_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_1 :: VDL_CONTROL_AUX1 :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_AUX1_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_AUX1_reserved0_SHIFT 17
-
-/* DDR34_PHY_CONTROL_REGS_1 :: VDL_CONTROL_AUX1 :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_AUX1_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_AUX1_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_AUX1_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_1 :: VDL_CONTROL_AUX1 :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_AUX1_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_AUX1_reserved1_SHIFT 13
-
-/* DDR34_PHY_CONTROL_REGS_1 :: VDL_CONTROL_AUX1 :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_AUX1_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_AUX1_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_AUX1_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_1 :: VDL_CONTROL_AUX1 :: reserved2 [11:09] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_AUX1_reserved2_MASK 0x00000e00
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_AUX1_reserved2_SHIFT 9
-
-/* DDR34_PHY_CONTROL_REGS_1 :: VDL_CONTROL_AUX1 :: VDL_STEP [08:00] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_AUX1_VDL_STEP_MASK 0x000001ff
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_AUX1_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_AUX1_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_AUX2 - DDR interface signal AUX[2] VDL control register
- ***************************************************************************/
-/* DDR34_PHY_CONTROL_REGS_1 :: VDL_CONTROL_AUX2 :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_AUX2_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_AUX2_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_AUX2_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_1 :: VDL_CONTROL_AUX2 :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_AUX2_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_AUX2_reserved0_SHIFT 17
-
-/* DDR34_PHY_CONTROL_REGS_1 :: VDL_CONTROL_AUX2 :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_AUX2_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_AUX2_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_AUX2_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_1 :: VDL_CONTROL_AUX2 :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_AUX2_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_AUX2_reserved1_SHIFT 13
-
-/* DDR34_PHY_CONTROL_REGS_1 :: VDL_CONTROL_AUX2 :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_AUX2_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_AUX2_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_AUX2_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_1 :: VDL_CONTROL_AUX2 :: reserved2 [11:09] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_AUX2_reserved2_MASK 0x00000e00
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_AUX2_reserved2_SHIFT 9
-
-/* DDR34_PHY_CONTROL_REGS_1 :: VDL_CONTROL_AUX2 :: VDL_STEP [08:00] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_AUX2_VDL_STEP_MASK 0x000001ff
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_AUX2_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_AUX2_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_CS0 - DDR interface signal CS0 VDL control register
- ***************************************************************************/
-/* DDR34_PHY_CONTROL_REGS_1 :: VDL_CONTROL_CS0 :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_CS0_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_CS0_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_CS0_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_1 :: VDL_CONTROL_CS0 :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_CS0_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_CS0_reserved0_SHIFT 17
-
-/* DDR34_PHY_CONTROL_REGS_1 :: VDL_CONTROL_CS0 :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_CS0_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_CS0_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_CS0_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_1 :: VDL_CONTROL_CS0 :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_CS0_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_CS0_reserved1_SHIFT 13
-
-/* DDR34_PHY_CONTROL_REGS_1 :: VDL_CONTROL_CS0 :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_CS0_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_CS0_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_CS0_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_1 :: VDL_CONTROL_CS0 :: reserved2 [11:09] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_CS0_reserved2_MASK 0x00000e00
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_CS0_reserved2_SHIFT 9
-
-/* DDR34_PHY_CONTROL_REGS_1 :: VDL_CONTROL_CS0 :: VDL_STEP [08:00] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_CS0_VDL_STEP_MASK 0x000001ff
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_CS0_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_CS0_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_CS1 - DDR interface signal CS1 VDL control register
- ***************************************************************************/
-/* DDR34_PHY_CONTROL_REGS_1 :: VDL_CONTROL_CS1 :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_CS1_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_CS1_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_CS1_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_1 :: VDL_CONTROL_CS1 :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_CS1_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_CS1_reserved0_SHIFT 17
-
-/* DDR34_PHY_CONTROL_REGS_1 :: VDL_CONTROL_CS1 :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_CS1_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_CS1_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_CS1_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_1 :: VDL_CONTROL_CS1 :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_CS1_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_CS1_reserved1_SHIFT 13
-
-/* DDR34_PHY_CONTROL_REGS_1 :: VDL_CONTROL_CS1 :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_CS1_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_CS1_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_CS1_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_1 :: VDL_CONTROL_CS1 :: reserved2 [11:09] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_CS1_reserved2_MASK 0x00000e00
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_CS1_reserved2_SHIFT 9
-
-/* DDR34_PHY_CONTROL_REGS_1 :: VDL_CONTROL_CS1 :: VDL_STEP [08:00] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_CS1_VDL_STEP_MASK 0x000001ff
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_CS1_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_CS1_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_PAR - DDR interface signal PAR VDL control register
- ***************************************************************************/
-/* DDR34_PHY_CONTROL_REGS_1 :: VDL_CONTROL_PAR :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_PAR_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_PAR_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_PAR_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_1 :: VDL_CONTROL_PAR :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_PAR_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_PAR_reserved0_SHIFT 17
-
-/* DDR34_PHY_CONTROL_REGS_1 :: VDL_CONTROL_PAR :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_PAR_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_PAR_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_PAR_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_1 :: VDL_CONTROL_PAR :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_PAR_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_PAR_reserved1_SHIFT 13
-
-/* DDR34_PHY_CONTROL_REGS_1 :: VDL_CONTROL_PAR :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_PAR_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_PAR_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_PAR_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_1 :: VDL_CONTROL_PAR :: reserved2 [11:09] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_PAR_reserved2_MASK 0x00000e00
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_PAR_reserved2_SHIFT 9
-
-/* DDR34_PHY_CONTROL_REGS_1 :: VDL_CONTROL_PAR :: VDL_STEP [08:00] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_PAR_VDL_STEP_MASK 0x000001ff
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_PAR_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_PAR_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_RAS_N - DDR interface signal RAS_N VDL control register
- ***************************************************************************/
-/* DDR34_PHY_CONTROL_REGS_1 :: VDL_CONTROL_RAS_N :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_RAS_N_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_RAS_N_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_RAS_N_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_1 :: VDL_CONTROL_RAS_N :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_RAS_N_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_RAS_N_reserved0_SHIFT 17
-
-/* DDR34_PHY_CONTROL_REGS_1 :: VDL_CONTROL_RAS_N :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_RAS_N_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_RAS_N_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_RAS_N_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_1 :: VDL_CONTROL_RAS_N :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_RAS_N_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_RAS_N_reserved1_SHIFT 13
-
-/* DDR34_PHY_CONTROL_REGS_1 :: VDL_CONTROL_RAS_N :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_RAS_N_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_RAS_N_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_RAS_N_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_1 :: VDL_CONTROL_RAS_N :: reserved2 [11:09] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_RAS_N_reserved2_MASK 0x00000e00
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_RAS_N_reserved2_SHIFT 9
-
-/* DDR34_PHY_CONTROL_REGS_1 :: VDL_CONTROL_RAS_N :: VDL_STEP [08:00] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_RAS_N_VDL_STEP_MASK 0x000001ff
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_RAS_N_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_RAS_N_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_CAS_N - DDR interface signal CAS_N VDL control register
- ***************************************************************************/
-/* DDR34_PHY_CONTROL_REGS_1 :: VDL_CONTROL_CAS_N :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_CAS_N_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_CAS_N_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_CAS_N_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_1 :: VDL_CONTROL_CAS_N :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_CAS_N_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_CAS_N_reserved0_SHIFT 17
-
-/* DDR34_PHY_CONTROL_REGS_1 :: VDL_CONTROL_CAS_N :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_CAS_N_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_CAS_N_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_CAS_N_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_1 :: VDL_CONTROL_CAS_N :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_CAS_N_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_CAS_N_reserved1_SHIFT 13
-
-/* DDR34_PHY_CONTROL_REGS_1 :: VDL_CONTROL_CAS_N :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_CAS_N_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_CAS_N_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_CAS_N_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_1 :: VDL_CONTROL_CAS_N :: reserved2 [11:09] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_CAS_N_reserved2_MASK 0x00000e00
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_CAS_N_reserved2_SHIFT 9
-
-/* DDR34_PHY_CONTROL_REGS_1 :: VDL_CONTROL_CAS_N :: VDL_STEP [08:00] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_CAS_N_VDL_STEP_MASK 0x000001ff
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_CAS_N_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_CAS_N_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_CKE - DDR interface signal CKE0 VDL control register
- ***************************************************************************/
-/* DDR34_PHY_CONTROL_REGS_1 :: VDL_CONTROL_CKE :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_CKE_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_CKE_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_CKE_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_1 :: VDL_CONTROL_CKE :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_CKE_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_CKE_reserved0_SHIFT 17
-
-/* DDR34_PHY_CONTROL_REGS_1 :: VDL_CONTROL_CKE :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_CKE_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_CKE_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_CKE_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_1 :: VDL_CONTROL_CKE :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_CKE_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_CKE_reserved1_SHIFT 13
-
-/* DDR34_PHY_CONTROL_REGS_1 :: VDL_CONTROL_CKE :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_CKE_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_CKE_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_CKE_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_1 :: VDL_CONTROL_CKE :: reserved2 [11:09] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_CKE_reserved2_MASK 0x00000e00
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_CKE_reserved2_SHIFT 9
-
-/* DDR34_PHY_CONTROL_REGS_1 :: VDL_CONTROL_CKE :: VDL_STEP [08:00] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_CKE_VDL_STEP_MASK 0x000001ff
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_CKE_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_CKE_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_RST_N - DDR interface signal RST_N VDL control register
- ***************************************************************************/
-/* DDR34_PHY_CONTROL_REGS_1 :: VDL_CONTROL_RST_N :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_RST_N_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_RST_N_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_RST_N_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_1 :: VDL_CONTROL_RST_N :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_RST_N_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_RST_N_reserved0_SHIFT 17
-
-/* DDR34_PHY_CONTROL_REGS_1 :: VDL_CONTROL_RST_N :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_RST_N_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_RST_N_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_RST_N_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_1 :: VDL_CONTROL_RST_N :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_RST_N_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_RST_N_reserved1_SHIFT 13
-
-/* DDR34_PHY_CONTROL_REGS_1 :: VDL_CONTROL_RST_N :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_RST_N_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_RST_N_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_RST_N_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_1 :: VDL_CONTROL_RST_N :: reserved2 [11:09] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_RST_N_reserved2_MASK 0x00000e00
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_RST_N_reserved2_SHIFT 9
-
-/* DDR34_PHY_CONTROL_REGS_1 :: VDL_CONTROL_RST_N :: VDL_STEP [08:00] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_RST_N_VDL_STEP_MASK 0x000001ff
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_RST_N_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_RST_N_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_ODT - DDR interface signal ODT0 VDL control register
- ***************************************************************************/
-/* DDR34_PHY_CONTROL_REGS_1 :: VDL_CONTROL_ODT :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_ODT_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_ODT_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_ODT_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_1 :: VDL_CONTROL_ODT :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_ODT_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_ODT_reserved0_SHIFT 17
-
-/* DDR34_PHY_CONTROL_REGS_1 :: VDL_CONTROL_ODT :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_ODT_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_ODT_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_ODT_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_1 :: VDL_CONTROL_ODT :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_ODT_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_ODT_reserved1_SHIFT 13
-
-/* DDR34_PHY_CONTROL_REGS_1 :: VDL_CONTROL_ODT :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_ODT_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_ODT_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_ODT_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_1 :: VDL_CONTROL_ODT :: reserved2 [11:09] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_ODT_reserved2_MASK 0x00000e00
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_ODT_reserved2_SHIFT 9
-
-/* DDR34_PHY_CONTROL_REGS_1 :: VDL_CONTROL_ODT :: VDL_STEP [08:00] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_ODT_VDL_STEP_MASK 0x000001ff
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_ODT_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_ODT_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_WE_N - DDR interface signal WE_N VDL control register
- ***************************************************************************/
-/* DDR34_PHY_CONTROL_REGS_1 :: VDL_CONTROL_WE_N :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_WE_N_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_WE_N_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_WE_N_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_1 :: VDL_CONTROL_WE_N :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_WE_N_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_WE_N_reserved0_SHIFT 17
-
-/* DDR34_PHY_CONTROL_REGS_1 :: VDL_CONTROL_WE_N :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_WE_N_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_WE_N_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_WE_N_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_1 :: VDL_CONTROL_WE_N :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_WE_N_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_WE_N_reserved1_SHIFT 13
-
-/* DDR34_PHY_CONTROL_REGS_1 :: VDL_CONTROL_WE_N :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_WE_N_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_WE_N_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_WE_N_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_1 :: VDL_CONTROL_WE_N :: reserved2 [11:09] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_WE_N_reserved2_MASK 0x00000e00
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_WE_N_reserved2_SHIFT 9
-
-/* DDR34_PHY_CONTROL_REGS_1 :: VDL_CONTROL_WE_N :: VDL_STEP [08:00] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_WE_N_VDL_STEP_MASK 0x000001ff
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_WE_N_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_WE_N_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_DDR_CK_P - DDR interface signal DDR_CK-P VDL control register
- ***************************************************************************/
-/* DDR34_PHY_CONTROL_REGS_1 :: VDL_CONTROL_DDR_CK_P :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_DDR_CK_P_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_DDR_CK_P_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_DDR_CK_P_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_1 :: VDL_CONTROL_DDR_CK_P :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_DDR_CK_P_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_DDR_CK_P_reserved0_SHIFT 17
-
-/* DDR34_PHY_CONTROL_REGS_1 :: VDL_CONTROL_DDR_CK_P :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_DDR_CK_P_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_DDR_CK_P_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_DDR_CK_P_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_1 :: VDL_CONTROL_DDR_CK_P :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_DDR_CK_P_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_DDR_CK_P_reserved1_SHIFT 13
-
-/* DDR34_PHY_CONTROL_REGS_1 :: VDL_CONTROL_DDR_CK_P :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_DDR_CK_P_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_DDR_CK_P_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_DDR_CK_P_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_1 :: VDL_CONTROL_DDR_CK_P :: reserved2 [11:09] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_DDR_CK_P_reserved2_MASK 0x00000e00
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_DDR_CK_P_reserved2_SHIFT 9
-
-/* DDR34_PHY_CONTROL_REGS_1 :: VDL_CONTROL_DDR_CK_P :: VDL_STEP [08:00] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_DDR_CK_P_VDL_STEP_MASK 0x000001ff
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_DDR_CK_P_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_DDR_CK_P_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_DDR_CK_N - DDR interface signal DDR_CK-N VDL control register
- ***************************************************************************/
-/* DDR34_PHY_CONTROL_REGS_1 :: VDL_CONTROL_DDR_CK_N :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_DDR_CK_N_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_DDR_CK_N_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_DDR_CK_N_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_1 :: VDL_CONTROL_DDR_CK_N :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_DDR_CK_N_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_DDR_CK_N_reserved0_SHIFT 17
-
-/* DDR34_PHY_CONTROL_REGS_1 :: VDL_CONTROL_DDR_CK_N :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_DDR_CK_N_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_DDR_CK_N_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_DDR_CK_N_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_1 :: VDL_CONTROL_DDR_CK_N :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_DDR_CK_N_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_DDR_CK_N_reserved1_SHIFT 13
-
-/* DDR34_PHY_CONTROL_REGS_1 :: VDL_CONTROL_DDR_CK_N :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_DDR_CK_N_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_DDR_CK_N_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_DDR_CK_N_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_1 :: VDL_CONTROL_DDR_CK_N :: reserved2 [11:09] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_DDR_CK_N_reserved2_MASK 0x00000e00
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_DDR_CK_N_reserved2_SHIFT 9
-
-/* DDR34_PHY_CONTROL_REGS_1 :: VDL_CONTROL_DDR_CK_N :: VDL_STEP [08:00] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_DDR_CK_N_VDL_STEP_MASK 0x000001ff
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_DDR_CK_N_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CONTROL_DDR_CK_N_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CLK_CONTROL - DDR interface signal Write Leveling CLK VDL control register
- ***************************************************************************/
-/* DDR34_PHY_CONTROL_REGS_1 :: VDL_CLK_CONTROL :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CLK_CONTROL_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CLK_CONTROL_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CLK_CONTROL_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_1 :: VDL_CLK_CONTROL :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CLK_CONTROL_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CLK_CONTROL_reserved0_SHIFT 17
-
-/* DDR34_PHY_CONTROL_REGS_1 :: VDL_CLK_CONTROL :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CLK_CONTROL_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CLK_CONTROL_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CLK_CONTROL_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_1 :: VDL_CLK_CONTROL :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CLK_CONTROL_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CLK_CONTROL_reserved1_SHIFT 13
-
-/* DDR34_PHY_CONTROL_REGS_1 :: VDL_CLK_CONTROL :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CLK_CONTROL_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CLK_CONTROL_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CLK_CONTROL_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_1 :: VDL_CLK_CONTROL :: reserved2 [11:09] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CLK_CONTROL_reserved2_MASK 0x00000e00
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CLK_CONTROL_reserved2_SHIFT 9
-
-/* DDR34_PHY_CONTROL_REGS_1 :: VDL_CLK_CONTROL :: VDL_STEP [08:00] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CLK_CONTROL_VDL_STEP_MASK 0x000001ff
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CLK_CONTROL_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_CLK_CONTROL_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_LDE_CONTROL - DDR interface signal Write Leveling Capture Enable VDL control register
- ***************************************************************************/
-/* DDR34_PHY_CONTROL_REGS_1 :: VDL_LDE_CONTROL :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_LDE_CONTROL_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_LDE_CONTROL_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_LDE_CONTROL_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_1 :: VDL_LDE_CONTROL :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_LDE_CONTROL_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_LDE_CONTROL_reserved0_SHIFT 17
-
-/* DDR34_PHY_CONTROL_REGS_1 :: VDL_LDE_CONTROL :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_LDE_CONTROL_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_LDE_CONTROL_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_LDE_CONTROL_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_1 :: VDL_LDE_CONTROL :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_LDE_CONTROL_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_LDE_CONTROL_reserved1_SHIFT 13
-
-/* DDR34_PHY_CONTROL_REGS_1 :: VDL_LDE_CONTROL :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_LDE_CONTROL_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_LDE_CONTROL_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_LDE_CONTROL_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_1 :: VDL_LDE_CONTROL :: reserved2 [11:09] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_LDE_CONTROL_reserved2_MASK 0x00000e00
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_LDE_CONTROL_reserved2_SHIFT 9
-
-/* DDR34_PHY_CONTROL_REGS_1 :: VDL_LDE_CONTROL :: VDL_STEP [08:00] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_LDE_CONTROL_VDL_STEP_MASK 0x000001ff
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_LDE_CONTROL_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VDL_LDE_CONTROL_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *REFRESH - Refresh engine controller
- ***************************************************************************/
-/* DDR34_PHY_CONTROL_REGS_1 :: REFRESH :: reserved0 [31:17] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_REFRESH_reserved0_MASK 0xfffe0000
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_REFRESH_reserved0_SHIFT 17
-
-/* DDR34_PHY_CONTROL_REGS_1 :: REFRESH :: ENABLE [16:16] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_REFRESH_ENABLE_MASK 0x00010000
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_REFRESH_ENABLE_SHIFT 16
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_REFRESH_ENABLE_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_1 :: REFRESH :: PERIOD [15:00] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_REFRESH_PERIOD_MASK 0x0000ffff
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_REFRESH_PERIOD_SHIFT 0
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_REFRESH_PERIOD_DEFAULT 0x00000000
-
-/***************************************************************************
- *UPDATE_VDL - Update VDL control register
- ***************************************************************************/
-/* DDR34_PHY_CONTROL_REGS_1 :: UPDATE_VDL :: reserved0 [31:06] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_UPDATE_VDL_reserved0_MASK 0xffffffc0
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_UPDATE_VDL_reserved0_SHIFT 6
-
-/* DDR34_PHY_CONTROL_REGS_1 :: UPDATE_VDL :: MODE [05:04] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_UPDATE_VDL_MODE_MASK 0x00000030
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_UPDATE_VDL_MODE_SHIFT 4
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_UPDATE_VDL_MODE_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_1 :: UPDATE_VDL :: reserved1 [03:02] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_UPDATE_VDL_reserved1_MASK 0x0000000c
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_UPDATE_VDL_reserved1_SHIFT 2
-
-/* DDR34_PHY_CONTROL_REGS_1 :: UPDATE_VDL :: DISABLE_INPUT [01:01] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_UPDATE_VDL_DISABLE_INPUT_MASK 0x00000002
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_UPDATE_VDL_DISABLE_INPUT_SHIFT 1
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_UPDATE_VDL_DISABLE_INPUT_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_1 :: UPDATE_VDL :: ENABLE [00:00] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_UPDATE_VDL_ENABLE_MASK 0x00000001
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_UPDATE_VDL_ENABLE_SHIFT 0
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_UPDATE_VDL_ENABLE_DEFAULT 0x00000000
-
-/***************************************************************************
- *UPDATE_VDL_SNOOP1 - Update VDL snoop control register #1
- ***************************************************************************/
-/* DDR34_PHY_CONTROL_REGS_1 :: UPDATE_VDL_SNOOP1 :: reserved0 [31:30] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_UPDATE_VDL_SNOOP1_reserved0_MASK 0xc0000000
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_UPDATE_VDL_SNOOP1_reserved0_SHIFT 30
-
-/* DDR34_PHY_CONTROL_REGS_1 :: UPDATE_VDL_SNOOP1 :: MODE [29:28] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_UPDATE_VDL_SNOOP1_MODE_MASK 0x30000000
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_UPDATE_VDL_SNOOP1_MODE_SHIFT 28
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_UPDATE_VDL_SNOOP1_MODE_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_1 :: UPDATE_VDL_SNOOP1 :: reserved1 [27:27] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_UPDATE_VDL_SNOOP1_reserved1_MASK 0x08000000
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_UPDATE_VDL_SNOOP1_reserved1_SHIFT 27
-
-/* DDR34_PHY_CONTROL_REGS_1 :: UPDATE_VDL_SNOOP1 :: MASK [26:16] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_UPDATE_VDL_SNOOP1_MASK_MASK 0x07ff0000
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_UPDATE_VDL_SNOOP1_MASK_SHIFT 16
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_UPDATE_VDL_SNOOP1_MASK_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_1 :: UPDATE_VDL_SNOOP1 :: reserved2 [15:15] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_UPDATE_VDL_SNOOP1_reserved2_MASK 0x00008000
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_UPDATE_VDL_SNOOP1_reserved2_SHIFT 15
-
-/* DDR34_PHY_CONTROL_REGS_1 :: UPDATE_VDL_SNOOP1 :: CMD [14:04] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_UPDATE_VDL_SNOOP1_CMD_MASK 0x00007ff0
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_UPDATE_VDL_SNOOP1_CMD_SHIFT 4
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_UPDATE_VDL_SNOOP1_CMD_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_1 :: UPDATE_VDL_SNOOP1 :: reserved3 [03:01] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_UPDATE_VDL_SNOOP1_reserved3_MASK 0x0000000e
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_UPDATE_VDL_SNOOP1_reserved3_SHIFT 1
-
-/* DDR34_PHY_CONTROL_REGS_1 :: UPDATE_VDL_SNOOP1 :: ENABLE [00:00] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_UPDATE_VDL_SNOOP1_ENABLE_MASK 0x00000001
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_UPDATE_VDL_SNOOP1_ENABLE_SHIFT 0
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_UPDATE_VDL_SNOOP1_ENABLE_DEFAULT 0x00000000
-
-/***************************************************************************
- *UPDATE_VDL_SNOOP2 - Update VDL snoop control register #2
- ***************************************************************************/
-/* DDR34_PHY_CONTROL_REGS_1 :: UPDATE_VDL_SNOOP2 :: reserved0 [31:30] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_UPDATE_VDL_SNOOP2_reserved0_MASK 0xc0000000
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_UPDATE_VDL_SNOOP2_reserved0_SHIFT 30
-
-/* DDR34_PHY_CONTROL_REGS_1 :: UPDATE_VDL_SNOOP2 :: MODE [29:28] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_UPDATE_VDL_SNOOP2_MODE_MASK 0x30000000
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_UPDATE_VDL_SNOOP2_MODE_SHIFT 28
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_UPDATE_VDL_SNOOP2_MODE_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_1 :: UPDATE_VDL_SNOOP2 :: reserved1 [27:27] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_UPDATE_VDL_SNOOP2_reserved1_MASK 0x08000000
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_UPDATE_VDL_SNOOP2_reserved1_SHIFT 27
-
-/* DDR34_PHY_CONTROL_REGS_1 :: UPDATE_VDL_SNOOP2 :: MASK [26:16] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_UPDATE_VDL_SNOOP2_MASK_MASK 0x07ff0000
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_UPDATE_VDL_SNOOP2_MASK_SHIFT 16
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_UPDATE_VDL_SNOOP2_MASK_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_1 :: UPDATE_VDL_SNOOP2 :: reserved2 [15:15] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_UPDATE_VDL_SNOOP2_reserved2_MASK 0x00008000
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_UPDATE_VDL_SNOOP2_reserved2_SHIFT 15
-
-/* DDR34_PHY_CONTROL_REGS_1 :: UPDATE_VDL_SNOOP2 :: CMD [14:04] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_UPDATE_VDL_SNOOP2_CMD_MASK 0x00007ff0
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_UPDATE_VDL_SNOOP2_CMD_SHIFT 4
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_UPDATE_VDL_SNOOP2_CMD_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_1 :: UPDATE_VDL_SNOOP2 :: reserved3 [03:01] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_UPDATE_VDL_SNOOP2_reserved3_MASK 0x0000000e
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_UPDATE_VDL_SNOOP2_reserved3_SHIFT 1
-
-/* DDR34_PHY_CONTROL_REGS_1 :: UPDATE_VDL_SNOOP2 :: ENABLE [00:00] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_UPDATE_VDL_SNOOP2_ENABLE_MASK 0x00000001
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_UPDATE_VDL_SNOOP2_ENABLE_SHIFT 0
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_UPDATE_VDL_SNOOP2_ENABLE_DEFAULT 0x00000000
-
-/***************************************************************************
- *COMMAND_REG1 - DRAM Command Register #1
- ***************************************************************************/
-/* DDR34_PHY_CONTROL_REGS_1 :: COMMAND_REG1 :: MCP [31:31] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_COMMAND_REG1_MCP_MASK 0x80000000
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_COMMAND_REG1_MCP_SHIFT 31
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_COMMAND_REG1_MCP_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_1 :: COMMAND_REG1 :: CS [30:29] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_COMMAND_REG1_CS_MASK 0x60000000
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_COMMAND_REG1_CS_SHIFT 29
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_COMMAND_REG1_CS_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_1 :: COMMAND_REG1 :: AUX [28:24] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_COMMAND_REG1_AUX_MASK 0x1f000000
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_COMMAND_REG1_AUX_SHIFT 24
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_COMMAND_REG1_AUX_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_1 :: COMMAND_REG1 :: ACT [23:23] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_COMMAND_REG1_ACT_MASK 0x00800000
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_COMMAND_REG1_ACT_SHIFT 23
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_COMMAND_REG1_ACT_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_1 :: COMMAND_REG1 :: WE [22:22] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_COMMAND_REG1_WE_MASK 0x00400000
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_COMMAND_REG1_WE_SHIFT 22
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_COMMAND_REG1_WE_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_1 :: COMMAND_REG1 :: CAS [21:21] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_COMMAND_REG1_CAS_MASK 0x00200000
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_COMMAND_REG1_CAS_SHIFT 21
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_COMMAND_REG1_CAS_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_1 :: COMMAND_REG1 :: RAS [20:20] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_COMMAND_REG1_RAS_MASK 0x00100000
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_COMMAND_REG1_RAS_SHIFT 20
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_COMMAND_REG1_RAS_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_1 :: COMMAND_REG1 :: BA [19:16] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_COMMAND_REG1_BA_MASK 0x000f0000
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_COMMAND_REG1_BA_SHIFT 16
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_COMMAND_REG1_BA_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_1 :: COMMAND_REG1 :: AD [15:00] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_COMMAND_REG1_AD_MASK 0x0000ffff
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_COMMAND_REG1_AD_SHIFT 0
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_COMMAND_REG1_AD_DEFAULT 0x00000000
-
-/***************************************************************************
- *COMMAND_AUX_REG1 - DRAM AUX_N Command Register #1
- ***************************************************************************/
-/* DDR34_PHY_CONTROL_REGS_1 :: COMMAND_AUX_REG1 :: reserved0 [31:05] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_COMMAND_AUX_REG1_reserved0_MASK 0xffffffe0
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_COMMAND_AUX_REG1_reserved0_SHIFT 5
-
-/* DDR34_PHY_CONTROL_REGS_1 :: COMMAND_AUX_REG1 :: AUX [04:00] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_COMMAND_AUX_REG1_AUX_MASK 0x0000001f
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_COMMAND_AUX_REG1_AUX_SHIFT 0
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_COMMAND_AUX_REG1_AUX_DEFAULT 0x00000000
-
-/***************************************************************************
- *COMMAND_REG2 - DRAM Command Register #2
- ***************************************************************************/
-/* DDR34_PHY_CONTROL_REGS_1 :: COMMAND_REG2 :: MCP [31:31] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_COMMAND_REG2_MCP_MASK 0x80000000
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_COMMAND_REG2_MCP_SHIFT 31
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_COMMAND_REG2_MCP_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_1 :: COMMAND_REG2 :: CS [30:29] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_COMMAND_REG2_CS_MASK 0x60000000
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_COMMAND_REG2_CS_SHIFT 29
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_COMMAND_REG2_CS_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_1 :: COMMAND_REG2 :: AUX [28:24] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_COMMAND_REG2_AUX_MASK 0x1f000000
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_COMMAND_REG2_AUX_SHIFT 24
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_COMMAND_REG2_AUX_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_1 :: COMMAND_REG2 :: ACT [23:23] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_COMMAND_REG2_ACT_MASK 0x00800000
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_COMMAND_REG2_ACT_SHIFT 23
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_COMMAND_REG2_ACT_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_1 :: COMMAND_REG2 :: WE [22:22] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_COMMAND_REG2_WE_MASK 0x00400000
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_COMMAND_REG2_WE_SHIFT 22
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_COMMAND_REG2_WE_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_1 :: COMMAND_REG2 :: CAS [21:21] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_COMMAND_REG2_CAS_MASK 0x00200000
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_COMMAND_REG2_CAS_SHIFT 21
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_COMMAND_REG2_CAS_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_1 :: COMMAND_REG2 :: RAS [20:20] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_COMMAND_REG2_RAS_MASK 0x00100000
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_COMMAND_REG2_RAS_SHIFT 20
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_COMMAND_REG2_RAS_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_1 :: COMMAND_REG2 :: BA [19:16] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_COMMAND_REG2_BA_MASK 0x000f0000
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_COMMAND_REG2_BA_SHIFT 16
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_COMMAND_REG2_BA_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_1 :: COMMAND_REG2 :: AD [15:00] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_COMMAND_REG2_AD_MASK 0x0000ffff
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_COMMAND_REG2_AD_SHIFT 0
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_COMMAND_REG2_AD_DEFAULT 0x00000000
-
-/***************************************************************************
- *COMMAND_AUX_REG2 - DRAM AUX_N Command Register #2
- ***************************************************************************/
-/* DDR34_PHY_CONTROL_REGS_1 :: COMMAND_AUX_REG2 :: reserved0 [31:05] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_COMMAND_AUX_REG2_reserved0_MASK 0xffffffe0
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_COMMAND_AUX_REG2_reserved0_SHIFT 5
-
-/* DDR34_PHY_CONTROL_REGS_1 :: COMMAND_AUX_REG2 :: AUX [04:00] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_COMMAND_AUX_REG2_AUX_MASK 0x0000001f
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_COMMAND_AUX_REG2_AUX_SHIFT 0
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_COMMAND_AUX_REG2_AUX_DEFAULT 0x00000000
-
-/***************************************************************************
- *COMMAND_REG3 - DRAM Command Register #3
- ***************************************************************************/
-/* DDR34_PHY_CONTROL_REGS_1 :: COMMAND_REG3 :: MCP [31:31] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_COMMAND_REG3_MCP_MASK 0x80000000
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_COMMAND_REG3_MCP_SHIFT 31
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_COMMAND_REG3_MCP_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_1 :: COMMAND_REG3 :: CS [30:29] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_COMMAND_REG3_CS_MASK 0x60000000
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_COMMAND_REG3_CS_SHIFT 29
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_COMMAND_REG3_CS_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_1 :: COMMAND_REG3 :: AUX [28:24] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_COMMAND_REG3_AUX_MASK 0x1f000000
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_COMMAND_REG3_AUX_SHIFT 24
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_COMMAND_REG3_AUX_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_1 :: COMMAND_REG3 :: ACT [23:23] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_COMMAND_REG3_ACT_MASK 0x00800000
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_COMMAND_REG3_ACT_SHIFT 23
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_COMMAND_REG3_ACT_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_1 :: COMMAND_REG3 :: WE [22:22] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_COMMAND_REG3_WE_MASK 0x00400000
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_COMMAND_REG3_WE_SHIFT 22
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_COMMAND_REG3_WE_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_1 :: COMMAND_REG3 :: CAS [21:21] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_COMMAND_REG3_CAS_MASK 0x00200000
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_COMMAND_REG3_CAS_SHIFT 21
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_COMMAND_REG3_CAS_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_1 :: COMMAND_REG3 :: RAS [20:20] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_COMMAND_REG3_RAS_MASK 0x00100000
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_COMMAND_REG3_RAS_SHIFT 20
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_COMMAND_REG3_RAS_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_1 :: COMMAND_REG3 :: BA [19:16] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_COMMAND_REG3_BA_MASK 0x000f0000
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_COMMAND_REG3_BA_SHIFT 16
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_COMMAND_REG3_BA_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_1 :: COMMAND_REG3 :: AD [15:00] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_COMMAND_REG3_AD_MASK 0x0000ffff
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_COMMAND_REG3_AD_SHIFT 0
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_COMMAND_REG3_AD_DEFAULT 0x00000000
-
-/***************************************************************************
- *COMMAND_AUX_REG3 - DRAM AUX_N Command Register #3
- ***************************************************************************/
-/* DDR34_PHY_CONTROL_REGS_1 :: COMMAND_AUX_REG3 :: reserved0 [31:05] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_COMMAND_AUX_REG3_reserved0_MASK 0xffffffe0
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_COMMAND_AUX_REG3_reserved0_SHIFT 5
-
-/* DDR34_PHY_CONTROL_REGS_1 :: COMMAND_AUX_REG3 :: AUX [04:00] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_COMMAND_AUX_REG3_AUX_MASK 0x0000001f
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_COMMAND_AUX_REG3_AUX_SHIFT 0
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_COMMAND_AUX_REG3_AUX_DEFAULT 0x00000000
-
-/***************************************************************************
- *COMMAND_REG4 - DRAM Command Register #4
- ***************************************************************************/
-/* DDR34_PHY_CONTROL_REGS_1 :: COMMAND_REG4 :: MCP [31:31] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_COMMAND_REG4_MCP_MASK 0x80000000
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_COMMAND_REG4_MCP_SHIFT 31
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_COMMAND_REG4_MCP_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_1 :: COMMAND_REG4 :: CS [30:29] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_COMMAND_REG4_CS_MASK 0x60000000
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_COMMAND_REG4_CS_SHIFT 29
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_COMMAND_REG4_CS_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_1 :: COMMAND_REG4 :: AUX [28:24] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_COMMAND_REG4_AUX_MASK 0x1f000000
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_COMMAND_REG4_AUX_SHIFT 24
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_COMMAND_REG4_AUX_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_1 :: COMMAND_REG4 :: ACT [23:23] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_COMMAND_REG4_ACT_MASK 0x00800000
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_COMMAND_REG4_ACT_SHIFT 23
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_COMMAND_REG4_ACT_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_1 :: COMMAND_REG4 :: WE [22:22] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_COMMAND_REG4_WE_MASK 0x00400000
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_COMMAND_REG4_WE_SHIFT 22
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_COMMAND_REG4_WE_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_1 :: COMMAND_REG4 :: CAS [21:21] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_COMMAND_REG4_CAS_MASK 0x00200000
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_COMMAND_REG4_CAS_SHIFT 21
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_COMMAND_REG4_CAS_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_1 :: COMMAND_REG4 :: RAS [20:20] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_COMMAND_REG4_RAS_MASK 0x00100000
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_COMMAND_REG4_RAS_SHIFT 20
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_COMMAND_REG4_RAS_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_1 :: COMMAND_REG4 :: BA [19:16] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_COMMAND_REG4_BA_MASK 0x000f0000
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_COMMAND_REG4_BA_SHIFT 16
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_COMMAND_REG4_BA_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_1 :: COMMAND_REG4 :: AD [15:00] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_COMMAND_REG4_AD_MASK 0x0000ffff
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_COMMAND_REG4_AD_SHIFT 0
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_COMMAND_REG4_AD_DEFAULT 0x00000000
-
-/***************************************************************************
- *COMMAND_AUX_REG4 - DRAM AUX_N Command Register #4
- ***************************************************************************/
-/* DDR34_PHY_CONTROL_REGS_1 :: COMMAND_AUX_REG4 :: reserved0 [31:05] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_COMMAND_AUX_REG4_reserved0_MASK 0xffffffe0
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_COMMAND_AUX_REG4_reserved0_SHIFT 5
-
-/* DDR34_PHY_CONTROL_REGS_1 :: COMMAND_AUX_REG4 :: AUX [04:00] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_COMMAND_AUX_REG4_AUX_MASK 0x0000001f
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_COMMAND_AUX_REG4_AUX_SHIFT 0
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_COMMAND_AUX_REG4_AUX_DEFAULT 0x00000000
-
-/***************************************************************************
- *COMMAND_REG_TIMER - DRAM Command Timer Register
- ***************************************************************************/
-/* DDR34_PHY_CONTROL_REGS_1 :: COMMAND_REG_TIMER :: reserved0 [31:16] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_COMMAND_REG_TIMER_reserved0_MASK 0xffff0000
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_COMMAND_REG_TIMER_reserved0_SHIFT 16
-
-/* DDR34_PHY_CONTROL_REGS_1 :: COMMAND_REG_TIMER :: INIT_VAL [15:08] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_COMMAND_REG_TIMER_INIT_VAL_MASK 0x0000ff00
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_COMMAND_REG_TIMER_INIT_VAL_SHIFT 8
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_COMMAND_REG_TIMER_INIT_VAL_DEFAULT 0x0000000f
-
-/* DDR34_PHY_CONTROL_REGS_1 :: COMMAND_REG_TIMER :: COUNT [07:00] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_COMMAND_REG_TIMER_COUNT_MASK 0x000000ff
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_COMMAND_REG_TIMER_COUNT_SHIFT 0
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_COMMAND_REG_TIMER_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *MODE_REG0 - DDR3/DDR4/GDDR5 Mode Register 0 and LPDDR Mode Register 1
- ***************************************************************************/
-/* DDR34_PHY_CONTROL_REGS_1 :: MODE_REG0 :: reserved0 [31:21] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_MODE_REG0_reserved0_MASK 0xffe00000
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_MODE_REG0_reserved0_SHIFT 21
-
-/* DDR34_PHY_CONTROL_REGS_1 :: MODE_REG0 :: reserved_for_eco1 [20:17] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_MODE_REG0_reserved_for_eco1_MASK 0x001e0000
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_MODE_REG0_reserved_for_eco1_SHIFT 17
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_MODE_REG0_reserved_for_eco1_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_1 :: MODE_REG0 :: VALID [16:16] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_MODE_REG0_VALID_MASK 0x00010000
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_MODE_REG0_VALID_SHIFT 16
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_MODE_REG0_VALID_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_1 :: MODE_REG0 :: AD [15:00] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_MODE_REG0_AD_MASK 0x0000ffff
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_MODE_REG0_AD_SHIFT 0
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_MODE_REG0_AD_DEFAULT 0x00000000
-
-/***************************************************************************
- *MODE_REG1 - DDR3/DDR4/GDDR5 Mode Register 1 and LPDDR Mode Register 2
- ***************************************************************************/
-/* DDR34_PHY_CONTROL_REGS_1 :: MODE_REG1 :: reserved0 [31:21] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_MODE_REG1_reserved0_MASK 0xffe00000
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_MODE_REG1_reserved0_SHIFT 21
-
-/* DDR34_PHY_CONTROL_REGS_1 :: MODE_REG1 :: reserved_for_eco1 [20:17] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_MODE_REG1_reserved_for_eco1_MASK 0x001e0000
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_MODE_REG1_reserved_for_eco1_SHIFT 17
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_MODE_REG1_reserved_for_eco1_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_1 :: MODE_REG1 :: VALID [16:16] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_MODE_REG1_VALID_MASK 0x00010000
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_MODE_REG1_VALID_SHIFT 16
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_MODE_REG1_VALID_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_1 :: MODE_REG1 :: AD [15:00] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_MODE_REG1_AD_MASK 0x0000ffff
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_MODE_REG1_AD_SHIFT 0
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_MODE_REG1_AD_DEFAULT 0x00000000
-
-/***************************************************************************
- *MODE_REG2 - DDR3/DDR4/GDDR5 Mode Register 2 and LPDDR Mode Register 3
- ***************************************************************************/
-/* DDR34_PHY_CONTROL_REGS_1 :: MODE_REG2 :: reserved0 [31:21] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_MODE_REG2_reserved0_MASK 0xffe00000
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_MODE_REG2_reserved0_SHIFT 21
-
-/* DDR34_PHY_CONTROL_REGS_1 :: MODE_REG2 :: reserved_for_eco1 [20:17] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_MODE_REG2_reserved_for_eco1_MASK 0x001e0000
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_MODE_REG2_reserved_for_eco1_SHIFT 17
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_MODE_REG2_reserved_for_eco1_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_1 :: MODE_REG2 :: VALID [16:16] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_MODE_REG2_VALID_MASK 0x00010000
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_MODE_REG2_VALID_SHIFT 16
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_MODE_REG2_VALID_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_1 :: MODE_REG2 :: AD [15:00] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_MODE_REG2_AD_MASK 0x0000ffff
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_MODE_REG2_AD_SHIFT 0
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_MODE_REG2_AD_DEFAULT 0x00000000
-
-/***************************************************************************
- *MODE_REG3 - DDR3/DDR4/GDDR5 Mode Register 3 and LPDDR Mode Register 9
- ***************************************************************************/
-/* DDR34_PHY_CONTROL_REGS_1 :: MODE_REG3 :: reserved0 [31:21] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_MODE_REG3_reserved0_MASK 0xffe00000
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_MODE_REG3_reserved0_SHIFT 21
-
-/* DDR34_PHY_CONTROL_REGS_1 :: MODE_REG3 :: reserved_for_eco1 [20:17] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_MODE_REG3_reserved_for_eco1_MASK 0x001e0000
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_MODE_REG3_reserved_for_eco1_SHIFT 17
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_MODE_REG3_reserved_for_eco1_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_1 :: MODE_REG3 :: VALID [16:16] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_MODE_REG3_VALID_MASK 0x00010000
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_MODE_REG3_VALID_SHIFT 16
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_MODE_REG3_VALID_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_1 :: MODE_REG3 :: AD [15:00] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_MODE_REG3_AD_MASK 0x0000ffff
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_MODE_REG3_AD_SHIFT 0
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_MODE_REG3_AD_DEFAULT 0x00000000
-
-/***************************************************************************
- *MODE_REG4 - DDR4/GDDR5 Mode Register 4 and LPDDR Mode Register 10
- ***************************************************************************/
-/* DDR34_PHY_CONTROL_REGS_1 :: MODE_REG4 :: reserved0 [31:21] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_MODE_REG4_reserved0_MASK 0xffe00000
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_MODE_REG4_reserved0_SHIFT 21
-
-/* DDR34_PHY_CONTROL_REGS_1 :: MODE_REG4 :: reserved_for_eco1 [20:17] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_MODE_REG4_reserved_for_eco1_MASK 0x001e0000
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_MODE_REG4_reserved_for_eco1_SHIFT 17
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_MODE_REG4_reserved_for_eco1_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_1 :: MODE_REG4 :: VALID [16:16] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_MODE_REG4_VALID_MASK 0x00010000
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_MODE_REG4_VALID_SHIFT 16
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_MODE_REG4_VALID_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_1 :: MODE_REG4 :: AD [15:00] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_MODE_REG4_AD_MASK 0x0000ffff
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_MODE_REG4_AD_SHIFT 0
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_MODE_REG4_AD_DEFAULT 0x00000000
-
-/***************************************************************************
- *MODE_REG5 - DDR4/GDDR5 Mode Register 5 and LPDDR Mode Register 16
- ***************************************************************************/
-/* DDR34_PHY_CONTROL_REGS_1 :: MODE_REG5 :: reserved0 [31:21] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_MODE_REG5_reserved0_MASK 0xffe00000
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_MODE_REG5_reserved0_SHIFT 21
-
-/* DDR34_PHY_CONTROL_REGS_1 :: MODE_REG5 :: reserved_for_eco1 [20:17] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_MODE_REG5_reserved_for_eco1_MASK 0x001e0000
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_MODE_REG5_reserved_for_eco1_SHIFT 17
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_MODE_REG5_reserved_for_eco1_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_1 :: MODE_REG5 :: VALID [16:16] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_MODE_REG5_VALID_MASK 0x00010000
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_MODE_REG5_VALID_SHIFT 16
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_MODE_REG5_VALID_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_1 :: MODE_REG5 :: AD [15:00] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_MODE_REG5_AD_MASK 0x0000ffff
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_MODE_REG5_AD_SHIFT 0
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_MODE_REG5_AD_DEFAULT 0x00000000
-
-/***************************************************************************
- *MODE_REG6 - DDR4/GDDR5 Mode Register 6 and LPDDR Mode Register 17
- ***************************************************************************/
-/* DDR34_PHY_CONTROL_REGS_1 :: MODE_REG6 :: reserved0 [31:21] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_MODE_REG6_reserved0_MASK 0xffe00000
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_MODE_REG6_reserved0_SHIFT 21
-
-/* DDR34_PHY_CONTROL_REGS_1 :: MODE_REG6 :: reserved_for_eco1 [20:17] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_MODE_REG6_reserved_for_eco1_MASK 0x001e0000
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_MODE_REG6_reserved_for_eco1_SHIFT 17
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_MODE_REG6_reserved_for_eco1_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_1 :: MODE_REG6 :: VALID [16:16] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_MODE_REG6_VALID_MASK 0x00010000
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_MODE_REG6_VALID_SHIFT 16
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_MODE_REG6_VALID_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_1 :: MODE_REG6 :: AD [15:00] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_MODE_REG6_AD_MASK 0x0000ffff
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_MODE_REG6_AD_SHIFT 0
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_MODE_REG6_AD_DEFAULT 0x00000000
-
-/***************************************************************************
- *MODE_REG7 - DDR4/GDDR5 Mode Register 7 and LPDDR Mode Register 41
- ***************************************************************************/
-/* DDR34_PHY_CONTROL_REGS_1 :: MODE_REG7 :: reserved0 [31:21] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_MODE_REG7_reserved0_MASK 0xffe00000
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_MODE_REG7_reserved0_SHIFT 21
-
-/* DDR34_PHY_CONTROL_REGS_1 :: MODE_REG7 :: reserved_for_eco1 [20:17] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_MODE_REG7_reserved_for_eco1_MASK 0x001e0000
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_MODE_REG7_reserved_for_eco1_SHIFT 17
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_MODE_REG7_reserved_for_eco1_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_1 :: MODE_REG7 :: VALID [16:16] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_MODE_REG7_VALID_MASK 0x00010000
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_MODE_REG7_VALID_SHIFT 16
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_MODE_REG7_VALID_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_1 :: MODE_REG7 :: AD [15:00] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_MODE_REG7_AD_MASK 0x0000ffff
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_MODE_REG7_AD_SHIFT 0
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_MODE_REG7_AD_DEFAULT 0x00000000
-
-/***************************************************************************
- *MODE_REG8 - GDDR5 Mode Register 8 and LPDDR Mode Register 42
- ***************************************************************************/
-/* DDR34_PHY_CONTROL_REGS_1 :: MODE_REG8 :: reserved0 [31:21] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_MODE_REG8_reserved0_MASK 0xffe00000
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_MODE_REG8_reserved0_SHIFT 21
-
-/* DDR34_PHY_CONTROL_REGS_1 :: MODE_REG8 :: reserved_for_eco1 [20:17] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_MODE_REG8_reserved_for_eco1_MASK 0x001e0000
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_MODE_REG8_reserved_for_eco1_SHIFT 17
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_MODE_REG8_reserved_for_eco1_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_1 :: MODE_REG8 :: VALID [16:16] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_MODE_REG8_VALID_MASK 0x00010000
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_MODE_REG8_VALID_SHIFT 16
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_MODE_REG8_VALID_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_1 :: MODE_REG8 :: AD [15:00] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_MODE_REG8_AD_MASK 0x0000ffff
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_MODE_REG8_AD_SHIFT 0
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_MODE_REG8_AD_DEFAULT 0x00000000
-
-/***************************************************************************
- *MODE_REG15 - GDDR5 Mode Register 15 and LPDDR Mode Register 48
- ***************************************************************************/
-/* DDR34_PHY_CONTROL_REGS_1 :: MODE_REG15 :: reserved0 [31:21] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_MODE_REG15_reserved0_MASK 0xffe00000
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_MODE_REG15_reserved0_SHIFT 21
-
-/* DDR34_PHY_CONTROL_REGS_1 :: MODE_REG15 :: reserved_for_eco1 [20:17] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_MODE_REG15_reserved_for_eco1_MASK 0x001e0000
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_MODE_REG15_reserved_for_eco1_SHIFT 17
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_MODE_REG15_reserved_for_eco1_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_1 :: MODE_REG15 :: VALID [16:16] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_MODE_REG15_VALID_MASK 0x00010000
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_MODE_REG15_VALID_SHIFT 16
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_MODE_REG15_VALID_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_1 :: MODE_REG15 :: AD [15:00] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_MODE_REG15_AD_MASK 0x0000ffff
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_MODE_REG15_AD_SHIFT 0
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_MODE_REG15_AD_DEFAULT 0x00000000
-
-/***************************************************************************
- *MODE_REG63 - LPDDR Mode Register 63
- ***************************************************************************/
-/* DDR34_PHY_CONTROL_REGS_1 :: MODE_REG63 :: reserved0 [31:21] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_MODE_REG63_reserved0_MASK 0xffe00000
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_MODE_REG63_reserved0_SHIFT 21
-
-/* DDR34_PHY_CONTROL_REGS_1 :: MODE_REG63 :: reserved_for_eco1 [20:17] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_MODE_REG63_reserved_for_eco1_MASK 0x001e0000
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_MODE_REG63_reserved_for_eco1_SHIFT 17
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_MODE_REG63_reserved_for_eco1_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_1 :: MODE_REG63 :: VALID [16:16] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_MODE_REG63_VALID_MASK 0x00010000
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_MODE_REG63_VALID_SHIFT 16
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_MODE_REG63_VALID_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_1 :: MODE_REG63 :: AD [15:00] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_MODE_REG63_AD_MASK 0x0000ffff
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_MODE_REG63_AD_SHIFT 0
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_MODE_REG63_AD_DEFAULT 0x00000000
-
-/***************************************************************************
- *ALERT_CLEAR - DDR4 Alert status clear register
- ***************************************************************************/
-/* DDR34_PHY_CONTROL_REGS_1 :: ALERT_CLEAR :: reserved0 [31:01] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_ALERT_CLEAR_reserved0_MASK 0xfffffffe
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_ALERT_CLEAR_reserved0_SHIFT 1
-
-/* DDR34_PHY_CONTROL_REGS_1 :: ALERT_CLEAR :: CLEAR [00:00] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_ALERT_CLEAR_CLEAR_MASK 0x00000001
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_ALERT_CLEAR_CLEAR_SHIFT 0
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_ALERT_CLEAR_CLEAR_DEFAULT 0x00000000
-
-/***************************************************************************
- *ALERT_STATUS - DDR4 Alert status register
- ***************************************************************************/
-/* DDR34_PHY_CONTROL_REGS_1 :: ALERT_STATUS :: reserved0 [31:01] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_ALERT_STATUS_reserved0_MASK 0xfffffffe
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_ALERT_STATUS_reserved0_SHIFT 1
-
-/* DDR34_PHY_CONTROL_REGS_1 :: ALERT_STATUS :: STATUS [00:00] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_ALERT_STATUS_STATUS_MASK 0x00000001
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_ALERT_STATUS_STATUS_SHIFT 0
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_ALERT_STATUS_STATUS_DEFAULT 0x00000000
-
-/***************************************************************************
- *CA_PARITY - DDR4 CA parity control register
- ***************************************************************************/
-/* DDR34_PHY_CONTROL_REGS_1 :: CA_PARITY :: reserved0 [31:02] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_CA_PARITY_reserved0_MASK 0xfffffffc
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_CA_PARITY_reserved0_SHIFT 2
-
-/* DDR34_PHY_CONTROL_REGS_1 :: CA_PARITY :: ERROR [01:01] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_CA_PARITY_ERROR_MASK 0x00000002
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_CA_PARITY_ERROR_SHIFT 1
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_CA_PARITY_ERROR_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_1 :: CA_PARITY :: ENABLE [00:00] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_CA_PARITY_ENABLE_MASK 0x00000001
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_CA_PARITY_ENABLE_SHIFT 0
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_CA_PARITY_ENABLE_DEFAULT 0x00000000
-
-/***************************************************************************
- *CA_PLAYBACK_CONTROL - GDDR5 CA playback control register
- ***************************************************************************/
-/* DDR34_PHY_CONTROL_REGS_1 :: CA_PLAYBACK_CONTROL :: reserved0 [31:12] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_CA_PLAYBACK_CONTROL_reserved0_MASK 0xfffff000
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_CA_PLAYBACK_CONTROL_reserved0_SHIFT 12
-
-/* DDR34_PHY_CONTROL_REGS_1 :: CA_PLAYBACK_CONTROL :: COUNT [11:04] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_CA_PLAYBACK_CONTROL_COUNT_MASK 0x00000ff0
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_CA_PLAYBACK_CONTROL_COUNT_SHIFT 4
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_CA_PLAYBACK_CONTROL_COUNT_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_1 :: CA_PLAYBACK_CONTROL :: reserved1 [03:01] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_CA_PLAYBACK_CONTROL_reserved1_MASK 0x0000000e
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_CA_PLAYBACK_CONTROL_reserved1_SHIFT 1
-
-/* DDR34_PHY_CONTROL_REGS_1 :: CA_PLAYBACK_CONTROL :: SAMPLE [00:00] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_CA_PLAYBACK_CONTROL_SAMPLE_MASK 0x00000001
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_CA_PLAYBACK_CONTROL_SAMPLE_SHIFT 0
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_CA_PLAYBACK_CONTROL_SAMPLE_DEFAULT 0x00000000
-
-/***************************************************************************
- *CA_PLAYBACK_STATUS0 - LPDDR3 and GDDR5 CA playback status register0 (for BL0 and BL1)
- ***************************************************************************/
-/* DDR34_PHY_CONTROL_REGS_1 :: CA_PLAYBACK_STATUS0 :: VALID [31:31] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_CA_PLAYBACK_STATUS0_VALID_MASK 0x80000000
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_CA_PLAYBACK_STATUS0_VALID_SHIFT 31
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_CA_PLAYBACK_STATUS0_VALID_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_1 :: CA_PLAYBACK_STATUS0 :: reserved0 [30:26] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_CA_PLAYBACK_STATUS0_reserved0_MASK 0x7c000000
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_CA_PLAYBACK_STATUS0_reserved0_SHIFT 26
-
-/* DDR34_PHY_CONTROL_REGS_1 :: CA_PLAYBACK_STATUS0 :: DATA1 [25:16] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_CA_PLAYBACK_STATUS0_DATA1_MASK 0x03ff0000
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_CA_PLAYBACK_STATUS0_DATA1_SHIFT 16
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_CA_PLAYBACK_STATUS0_DATA1_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_1 :: CA_PLAYBACK_STATUS0 :: reserved1 [15:10] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_CA_PLAYBACK_STATUS0_reserved1_MASK 0x0000fc00
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_CA_PLAYBACK_STATUS0_reserved1_SHIFT 10
-
-/* DDR34_PHY_CONTROL_REGS_1 :: CA_PLAYBACK_STATUS0 :: DATA0 [09:00] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_CA_PLAYBACK_STATUS0_DATA0_MASK 0x000003ff
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_CA_PLAYBACK_STATUS0_DATA0_SHIFT 0
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_CA_PLAYBACK_STATUS0_DATA0_DEFAULT 0x00000000
-
-/***************************************************************************
- *CA_PLAYBACK_STATUS1 - LPDDR3 and GDDR5 CA playback status register1 (for BL2 and BL3)
- ***************************************************************************/
-/* DDR34_PHY_CONTROL_REGS_1 :: CA_PLAYBACK_STATUS1 :: VALID [31:31] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_CA_PLAYBACK_STATUS1_VALID_MASK 0x80000000
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_CA_PLAYBACK_STATUS1_VALID_SHIFT 31
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_CA_PLAYBACK_STATUS1_VALID_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_1 :: CA_PLAYBACK_STATUS1 :: reserved0 [30:26] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_CA_PLAYBACK_STATUS1_reserved0_MASK 0x7c000000
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_CA_PLAYBACK_STATUS1_reserved0_SHIFT 26
-
-/* DDR34_PHY_CONTROL_REGS_1 :: CA_PLAYBACK_STATUS1 :: DATA1 [25:16] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_CA_PLAYBACK_STATUS1_DATA1_MASK 0x03ff0000
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_CA_PLAYBACK_STATUS1_DATA1_SHIFT 16
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_CA_PLAYBACK_STATUS1_DATA1_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_1 :: CA_PLAYBACK_STATUS1 :: reserved1 [15:10] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_CA_PLAYBACK_STATUS1_reserved1_MASK 0x0000fc00
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_CA_PLAYBACK_STATUS1_reserved1_SHIFT 10
-
-/* DDR34_PHY_CONTROL_REGS_1 :: CA_PLAYBACK_STATUS1 :: DATA0 [09:00] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_CA_PLAYBACK_STATUS1_DATA0_MASK 0x000003ff
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_CA_PLAYBACK_STATUS1_DATA0_SHIFT 0
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_CA_PLAYBACK_STATUS1_DATA0_DEFAULT 0x00000000
-
-/***************************************************************************
- *WRITE_LEVELING_CONTROL - Write leveling control register
- ***************************************************************************/
-/* DDR34_PHY_CONTROL_REGS_1 :: WRITE_LEVELING_CONTROL :: reserved0 [31:20] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_WRITE_LEVELING_CONTROL_reserved0_MASK 0xfff00000
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_WRITE_LEVELING_CONTROL_reserved0_SHIFT 20
-
-/* DDR34_PHY_CONTROL_REGS_1 :: WRITE_LEVELING_CONTROL :: reserved_for_eco1 [19:16] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_WRITE_LEVELING_CONTROL_reserved_for_eco1_MASK 0x000f0000
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_WRITE_LEVELING_CONTROL_reserved_for_eco1_SHIFT 16
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_WRITE_LEVELING_CONTROL_reserved_for_eco1_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_1 :: WRITE_LEVELING_CONTROL :: COUNT [15:08] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_WRITE_LEVELING_CONTROL_COUNT_MASK 0x0000ff00
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_WRITE_LEVELING_CONTROL_COUNT_SHIFT 8
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_WRITE_LEVELING_CONTROL_COUNT_DEFAULT 0x0000000f
-
-/* DDR34_PHY_CONTROL_REGS_1 :: WRITE_LEVELING_CONTROL :: reserved2 [07:03] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_WRITE_LEVELING_CONTROL_reserved2_MASK 0x000000f8
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_WRITE_LEVELING_CONTROL_reserved2_SHIFT 3
-
-/* DDR34_PHY_CONTROL_REGS_1 :: WRITE_LEVELING_CONTROL :: SAMPLE [02:02] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_WRITE_LEVELING_CONTROL_SAMPLE_MASK 0x00000004
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_WRITE_LEVELING_CONTROL_SAMPLE_SHIFT 2
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_WRITE_LEVELING_CONTROL_SAMPLE_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_1 :: WRITE_LEVELING_CONTROL :: CONTINUOUS [01:01] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_WRITE_LEVELING_CONTROL_CONTINUOUS_MASK 0x00000002
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_WRITE_LEVELING_CONTROL_CONTINUOUS_SHIFT 1
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_WRITE_LEVELING_CONTROL_CONTINUOUS_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_1 :: WRITE_LEVELING_CONTROL :: ENABLE [00:00] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_WRITE_LEVELING_CONTROL_ENABLE_MASK 0x00000001
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_WRITE_LEVELING_CONTROL_ENABLE_SHIFT 0
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_WRITE_LEVELING_CONTROL_ENABLE_DEFAULT 0x00000000
-
-/***************************************************************************
- *WRITE_LEVELING_STATUS - Write leveling status register
- ***************************************************************************/
-/* DDR34_PHY_CONTROL_REGS_1 :: WRITE_LEVELING_STATUS :: reserved0 [31:14] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_WRITE_LEVELING_STATUS_reserved0_MASK 0xffffc000
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_WRITE_LEVELING_STATUS_reserved0_SHIFT 14
-
-/* DDR34_PHY_CONTROL_REGS_1 :: WRITE_LEVELING_STATUS :: EDC [13:09] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_WRITE_LEVELING_STATUS_EDC_MASK 0x00003e00
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_WRITE_LEVELING_STATUS_EDC_SHIFT 9
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_WRITE_LEVELING_STATUS_EDC_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_1 :: WRITE_LEVELING_STATUS :: STATUS [08:04] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_WRITE_LEVELING_STATUS_STATUS_MASK 0x000001f0
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_WRITE_LEVELING_STATUS_STATUS_SHIFT 4
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_WRITE_LEVELING_STATUS_STATUS_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_1 :: WRITE_LEVELING_STATUS :: reserved1 [03:01] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_WRITE_LEVELING_STATUS_reserved1_MASK 0x0000000e
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_WRITE_LEVELING_STATUS_reserved1_SHIFT 1
-
-/* DDR34_PHY_CONTROL_REGS_1 :: WRITE_LEVELING_STATUS :: VALID [00:00] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_WRITE_LEVELING_STATUS_VALID_MASK 0x00000001
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_WRITE_LEVELING_STATUS_VALID_SHIFT 0
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_WRITE_LEVELING_STATUS_VALID_DEFAULT 0x00000000
-
-/***************************************************************************
- *READ_ENABLE_CONTROL - Read enable test cycle control register
- ***************************************************************************/
-/* DDR34_PHY_CONTROL_REGS_1 :: READ_ENABLE_CONTROL :: reserved0 [31:13] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_READ_ENABLE_CONTROL_reserved0_MASK 0xffffe000
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_READ_ENABLE_CONTROL_reserved0_SHIFT 13
-
-/* DDR34_PHY_CONTROL_REGS_1 :: READ_ENABLE_CONTROL :: TEST_CYCLE [12:12] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_READ_ENABLE_CONTROL_TEST_CYCLE_MASK 0x00001000
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_READ_ENABLE_CONTROL_TEST_CYCLE_SHIFT 12
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_READ_ENABLE_CONTROL_TEST_CYCLE_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_1 :: READ_ENABLE_CONTROL :: SELECT [11:08] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_READ_ENABLE_CONTROL_SELECT_MASK 0x00000f00
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_READ_ENABLE_CONTROL_SELECT_SHIFT 8
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_READ_ENABLE_CONTROL_SELECT_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_1 :: READ_ENABLE_CONTROL :: reserved_for_eco1 [07:06] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_READ_ENABLE_CONTROL_reserved_for_eco1_MASK 0x000000c0
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_READ_ENABLE_CONTROL_reserved_for_eco1_SHIFT 6
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_READ_ENABLE_CONTROL_reserved_for_eco1_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_1 :: READ_ENABLE_CONTROL :: CS_N [05:04] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_READ_ENABLE_CONTROL_CS_N_MASK 0x00000030
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_READ_ENABLE_CONTROL_CS_N_SHIFT 4
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_READ_ENABLE_CONTROL_CS_N_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_1 :: READ_ENABLE_CONTROL :: EDC_DATA [03:03] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_READ_ENABLE_CONTROL_EDC_DATA_MASK 0x00000008
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_READ_ENABLE_CONTROL_EDC_DATA_SHIFT 3
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_READ_ENABLE_CONTROL_EDC_DATA_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_1 :: READ_ENABLE_CONTROL :: EDC_PHASE [02:02] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_READ_ENABLE_CONTROL_EDC_PHASE_MASK 0x00000004
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_READ_ENABLE_CONTROL_EDC_PHASE_SHIFT 2
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_READ_ENABLE_CONTROL_EDC_PHASE_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_1 :: READ_ENABLE_CONTROL :: DQS [01:01] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_READ_ENABLE_CONTROL_DQS_MASK 0x00000002
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_READ_ENABLE_CONTROL_DQS_SHIFT 1
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_READ_ENABLE_CONTROL_DQS_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_1 :: READ_ENABLE_CONTROL :: ENABLE [00:00] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_READ_ENABLE_CONTROL_ENABLE_MASK 0x00000001
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_READ_ENABLE_CONTROL_ENABLE_SHIFT 0
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_READ_ENABLE_CONTROL_ENABLE_DEFAULT 0x00000000
-
-/***************************************************************************
- *READ_ENABLE_STATUS - Read enable test cycle status register
- ***************************************************************************/
-/* DDR34_PHY_CONTROL_REGS_1 :: READ_ENABLE_STATUS :: reserved0 [31:20] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_READ_ENABLE_STATUS_reserved0_MASK 0xfff00000
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_READ_ENABLE_STATUS_reserved0_SHIFT 20
-
-/* DDR34_PHY_CONTROL_REGS_1 :: READ_ENABLE_STATUS :: DATA [19:12] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_READ_ENABLE_STATUS_DATA_MASK 0x000ff000
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_READ_ENABLE_STATUS_DATA_SHIFT 12
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_READ_ENABLE_STATUS_DATA_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_1 :: READ_ENABLE_STATUS :: reserved1 [11:09] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_READ_ENABLE_STATUS_reserved1_MASK 0x00000e00
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_READ_ENABLE_STATUS_reserved1_SHIFT 9
-
-/* DDR34_PHY_CONTROL_REGS_1 :: READ_ENABLE_STATUS :: BL4_STATUS [08:08] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_READ_ENABLE_STATUS_BL4_STATUS_MASK 0x00000100
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_READ_ENABLE_STATUS_BL4_STATUS_SHIFT 8
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_READ_ENABLE_STATUS_BL4_STATUS_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_1 :: READ_ENABLE_STATUS :: BL3_STATUS [07:07] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_READ_ENABLE_STATUS_BL3_STATUS_MASK 0x00000080
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_READ_ENABLE_STATUS_BL3_STATUS_SHIFT 7
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_READ_ENABLE_STATUS_BL3_STATUS_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_1 :: READ_ENABLE_STATUS :: BL2_STATUS [06:06] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_READ_ENABLE_STATUS_BL2_STATUS_MASK 0x00000040
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_READ_ENABLE_STATUS_BL2_STATUS_SHIFT 6
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_READ_ENABLE_STATUS_BL2_STATUS_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_1 :: READ_ENABLE_STATUS :: BL1_STATUS [05:05] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_READ_ENABLE_STATUS_BL1_STATUS_MASK 0x00000020
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_READ_ENABLE_STATUS_BL1_STATUS_SHIFT 5
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_READ_ENABLE_STATUS_BL1_STATUS_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_1 :: READ_ENABLE_STATUS :: BL0_STATUS [04:04] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_READ_ENABLE_STATUS_BL0_STATUS_MASK 0x00000010
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_READ_ENABLE_STATUS_BL0_STATUS_SHIFT 4
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_READ_ENABLE_STATUS_BL0_STATUS_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_1 :: READ_ENABLE_STATUS :: reserved2 [03:01] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_READ_ENABLE_STATUS_reserved2_MASK 0x0000000e
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_READ_ENABLE_STATUS_reserved2_SHIFT 1
-
-/* DDR34_PHY_CONTROL_REGS_1 :: READ_ENABLE_STATUS :: VALID [00:00] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_READ_ENABLE_STATUS_VALID_MASK 0x00000001
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_READ_ENABLE_STATUS_VALID_SHIFT 0
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_READ_ENABLE_STATUS_VALID_DEFAULT 0x00000000
-
-/***************************************************************************
- *TRAFFIC_GEN_LFSR_SEED - Traffic generator seed register
- ***************************************************************************/
-/* DDR34_PHY_CONTROL_REGS_1 :: TRAFFIC_GEN_LFSR_SEED :: SEED [31:00] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_TRAFFIC_GEN_LFSR_SEED_SEED_MASK 0xffffffff
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_TRAFFIC_GEN_LFSR_SEED_SEED_SHIFT 0
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_TRAFFIC_GEN_LFSR_SEED_SEED_DEFAULT 0xba5eba11
-
-/***************************************************************************
- *TRAFFIC_GEN_ADDRESS1 - Traffic generator address register #1
- ***************************************************************************/
-/* DDR34_PHY_CONTROL_REGS_1 :: TRAFFIC_GEN_ADDRESS1 :: reserved0 [31:20] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_TRAFFIC_GEN_ADDRESS1_reserved0_MASK 0xfff00000
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_TRAFFIC_GEN_ADDRESS1_reserved0_SHIFT 20
-
-/* DDR34_PHY_CONTROL_REGS_1 :: TRAFFIC_GEN_ADDRESS1 :: BANK [19:16] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_TRAFFIC_GEN_ADDRESS1_BANK_MASK 0x000f0000
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_TRAFFIC_GEN_ADDRESS1_BANK_SHIFT 16
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_TRAFFIC_GEN_ADDRESS1_BANK_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_1 :: TRAFFIC_GEN_ADDRESS1 :: ROW [15:00] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_TRAFFIC_GEN_ADDRESS1_ROW_MASK 0x0000ffff
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_TRAFFIC_GEN_ADDRESS1_ROW_SHIFT 0
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_TRAFFIC_GEN_ADDRESS1_ROW_DEFAULT 0x00000000
-
-/***************************************************************************
- *TRAFFIC_GEN_ADDRESS2 - Traffic generator address register #2
- ***************************************************************************/
-/* DDR34_PHY_CONTROL_REGS_1 :: TRAFFIC_GEN_ADDRESS2 :: reserved0 [31:20] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_TRAFFIC_GEN_ADDRESS2_reserved0_MASK 0xfff00000
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_TRAFFIC_GEN_ADDRESS2_reserved0_SHIFT 20
-
-/* DDR34_PHY_CONTROL_REGS_1 :: TRAFFIC_GEN_ADDRESS2 :: BANK [19:16] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_TRAFFIC_GEN_ADDRESS2_BANK_MASK 0x000f0000
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_TRAFFIC_GEN_ADDRESS2_BANK_SHIFT 16
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_TRAFFIC_GEN_ADDRESS2_BANK_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_1 :: TRAFFIC_GEN_ADDRESS2 :: ROW [15:00] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_TRAFFIC_GEN_ADDRESS2_ROW_MASK 0x0000ffff
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_TRAFFIC_GEN_ADDRESS2_ROW_SHIFT 0
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_TRAFFIC_GEN_ADDRESS2_ROW_DEFAULT 0x00000000
-
-/***************************************************************************
- *TRAFFIC_GEN_CONTROL - Traffic generator control register
- ***************************************************************************/
-/* DDR34_PHY_CONTROL_REGS_1 :: TRAFFIC_GEN_CONTROL :: reserved0 [31:17] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_TRAFFIC_GEN_CONTROL_reserved0_MASK 0xfffe0000
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_TRAFFIC_GEN_CONTROL_reserved0_SHIFT 17
-
-/* DDR34_PHY_CONTROL_REGS_1 :: TRAFFIC_GEN_CONTROL :: reserved_for_eco1 [16:13] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_TRAFFIC_GEN_CONTROL_reserved_for_eco1_MASK 0x0001e000
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_TRAFFIC_GEN_CONTROL_reserved_for_eco1_SHIFT 13
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_TRAFFIC_GEN_CONTROL_reserved_for_eco1_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_1 :: TRAFFIC_GEN_CONTROL :: DIAG_WRO [12:12] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_TRAFFIC_GEN_CONTROL_DIAG_WRO_MASK 0x00001000
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_TRAFFIC_GEN_CONTROL_DIAG_WRO_SHIFT 12
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_TRAFFIC_GEN_CONTROL_DIAG_WRO_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_1 :: TRAFFIC_GEN_CONTROL :: DIAG_WRO_RD [11:11] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_TRAFFIC_GEN_CONTROL_DIAG_WRO_RD_MASK 0x00000800
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_TRAFFIC_GEN_CONTROL_DIAG_WRO_RD_SHIFT 11
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_TRAFFIC_GEN_CONTROL_DIAG_WRO_RD_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_1 :: TRAFFIC_GEN_CONTROL :: DIAG_WR_RD [10:10] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_TRAFFIC_GEN_CONTROL_DIAG_WR_RD_MASK 0x00000400
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_TRAFFIC_GEN_CONTROL_DIAG_WR_RD_SHIFT 10
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_TRAFFIC_GEN_CONTROL_DIAG_WR_RD_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_1 :: TRAFFIC_GEN_CONTROL :: WR_NOISE [09:09] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_TRAFFIC_GEN_CONTROL_WR_NOISE_MASK 0x00000200
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_TRAFFIC_GEN_CONTROL_WR_NOISE_SHIFT 9
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_TRAFFIC_GEN_CONTROL_WR_NOISE_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_1 :: TRAFFIC_GEN_CONTROL :: RD_NOISE [08:08] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_TRAFFIC_GEN_CONTROL_RD_NOISE_MASK 0x00000100
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_TRAFFIC_GEN_CONTROL_RD_NOISE_SHIFT 8
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_TRAFFIC_GEN_CONTROL_RD_NOISE_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_1 :: TRAFFIC_GEN_CONTROL :: CLEAR_DRAM [07:07] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_TRAFFIC_GEN_CONTROL_CLEAR_DRAM_MASK 0x00000080
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_TRAFFIC_GEN_CONTROL_CLEAR_DRAM_SHIFT 7
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_TRAFFIC_GEN_CONTROL_CLEAR_DRAM_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_1 :: TRAFFIC_GEN_CONTROL :: MASK_DM [06:06] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_TRAFFIC_GEN_CONTROL_MASK_DM_MASK 0x00000040
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_TRAFFIC_GEN_CONTROL_MASK_DM_SHIFT 6
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_TRAFFIC_GEN_CONTROL_MASK_DM_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_1 :: TRAFFIC_GEN_CONTROL :: INIT_LFSR [05:05] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_TRAFFIC_GEN_CONTROL_INIT_LFSR_MASK 0x00000020
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_TRAFFIC_GEN_CONTROL_INIT_LFSR_SHIFT 5
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_TRAFFIC_GEN_CONTROL_INIT_LFSR_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_1 :: TRAFFIC_GEN_CONTROL :: FIFO [04:04] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_TRAFFIC_GEN_CONTROL_FIFO_MASK 0x00000010
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_TRAFFIC_GEN_CONTROL_FIFO_SHIFT 4
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_TRAFFIC_GEN_CONTROL_FIFO_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_1 :: TRAFFIC_GEN_CONTROL :: MPR [03:03] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_TRAFFIC_GEN_CONTROL_MPR_MASK 0x00000008
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_TRAFFIC_GEN_CONTROL_MPR_SHIFT 3
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_TRAFFIC_GEN_CONTROL_MPR_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_1 :: TRAFFIC_GEN_CONTROL :: RD_WR [02:02] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_TRAFFIC_GEN_CONTROL_RD_WR_MASK 0x00000004
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_TRAFFIC_GEN_CONTROL_RD_WR_SHIFT 2
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_TRAFFIC_GEN_CONTROL_RD_WR_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_1 :: TRAFFIC_GEN_CONTROL :: RD_EN [01:01] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_TRAFFIC_GEN_CONTROL_RD_EN_MASK 0x00000002
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_TRAFFIC_GEN_CONTROL_RD_EN_SHIFT 1
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_TRAFFIC_GEN_CONTROL_RD_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_1 :: TRAFFIC_GEN_CONTROL :: ENABLE [00:00] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_TRAFFIC_GEN_CONTROL_ENABLE_MASK 0x00000001
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_TRAFFIC_GEN_CONTROL_ENABLE_SHIFT 0
-
-/***************************************************************************
- *TRAFFIC_GEN_DATA_CONTROL - Traffic generator data control register
- ***************************************************************************/
-/* DDR34_PHY_CONTROL_REGS_1 :: TRAFFIC_GEN_DATA_CONTROL :: reserved0 [31:22] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_TRAFFIC_GEN_DATA_CONTROL_reserved0_MASK 0xffc00000
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_TRAFFIC_GEN_DATA_CONTROL_reserved0_SHIFT 22
-
-/* DDR34_PHY_CONTROL_REGS_1 :: TRAFFIC_GEN_DATA_CONTROL :: PATTERN [21:20] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_TRAFFIC_GEN_DATA_CONTROL_PATTERN_MASK 0x00300000
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_TRAFFIC_GEN_DATA_CONTROL_PATTERN_SHIFT 20
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_TRAFFIC_GEN_DATA_CONTROL_PATTERN_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_1 :: TRAFFIC_GEN_DATA_CONTROL :: LENGTH [19:00] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_TRAFFIC_GEN_DATA_CONTROL_LENGTH_MASK 0x000fffff
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_TRAFFIC_GEN_DATA_CONTROL_LENGTH_SHIFT 0
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_TRAFFIC_GEN_DATA_CONTROL_LENGTH_DEFAULT 0x00000000
-
-/***************************************************************************
- *TRAFFIC_GEN_DQ_MASK - Traffic generator DQ mask register
- ***************************************************************************/
-/* DDR34_PHY_CONTROL_REGS_1 :: TRAFFIC_GEN_DQ_MASK :: MASK [31:00] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_TRAFFIC_GEN_DQ_MASK_MASK_MASK 0xffffffff
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_TRAFFIC_GEN_DQ_MASK_MASK_SHIFT 0
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_TRAFFIC_GEN_DQ_MASK_MASK_DEFAULT 0x00000000
-
-/***************************************************************************
- *TRAFFIC_GEN_ECC_DQ_MASK - Traffic generator ECC DQ mask register
- ***************************************************************************/
-/* DDR34_PHY_CONTROL_REGS_1 :: TRAFFIC_GEN_ECC_DQ_MASK :: reserved0 [31:04] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_TRAFFIC_GEN_ECC_DQ_MASK_reserved0_MASK 0xfffffff0
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_TRAFFIC_GEN_ECC_DQ_MASK_reserved0_SHIFT 4
-
-/* DDR34_PHY_CONTROL_REGS_1 :: TRAFFIC_GEN_ECC_DQ_MASK :: MASK [03:00] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_TRAFFIC_GEN_ECC_DQ_MASK_MASK_MASK 0x0000000f
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_TRAFFIC_GEN_ECC_DQ_MASK_MASK_SHIFT 0
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_TRAFFIC_GEN_ECC_DQ_MASK_MASK_DEFAULT 0x00000000
-
-/***************************************************************************
- *TRAFFIC_GEN_STATUS - Traffic generator status register
- ***************************************************************************/
-/* DDR34_PHY_CONTROL_REGS_1 :: TRAFFIC_GEN_STATUS :: reserved0 [31:01] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_TRAFFIC_GEN_STATUS_reserved0_MASK 0xfffffffe
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_TRAFFIC_GEN_STATUS_reserved0_SHIFT 1
-
-/* DDR34_PHY_CONTROL_REGS_1 :: TRAFFIC_GEN_STATUS :: BUSY [00:00] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_TRAFFIC_GEN_STATUS_BUSY_MASK 0x00000001
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_TRAFFIC_GEN_STATUS_BUSY_SHIFT 0
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_TRAFFIC_GEN_STATUS_BUSY_DEFAULT 0x00000000
-
-/***************************************************************************
- *TRAFFIC_GEN_DQ_STATUS - Traffic generator DQ status register
- ***************************************************************************/
-/* DDR34_PHY_CONTROL_REGS_1 :: TRAFFIC_GEN_DQ_STATUS :: STATUS [31:00] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_TRAFFIC_GEN_DQ_STATUS_STATUS_MASK 0xffffffff
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_TRAFFIC_GEN_DQ_STATUS_STATUS_SHIFT 0
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_TRAFFIC_GEN_DQ_STATUS_STATUS_DEFAULT 0x00000000
-
-/***************************************************************************
- *TRAFFIC_GEN_ECC_STATUS - Traffic generator ECC DQ status register
- ***************************************************************************/
-/* DDR34_PHY_CONTROL_REGS_1 :: TRAFFIC_GEN_ECC_STATUS :: reserved0 [31:04] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_TRAFFIC_GEN_ECC_STATUS_reserved0_MASK 0xfffffff0
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_TRAFFIC_GEN_ECC_STATUS_reserved0_SHIFT 4
-
-/* DDR34_PHY_CONTROL_REGS_1 :: TRAFFIC_GEN_ECC_STATUS :: STATUS [03:00] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_TRAFFIC_GEN_ECC_STATUS_STATUS_MASK 0x0000000f
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_TRAFFIC_GEN_ECC_STATUS_STATUS_SHIFT 0
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_TRAFFIC_GEN_ECC_STATUS_STATUS_DEFAULT 0x00000000
-
-/***************************************************************************
- *TRAFFIC_GEN_ERR_CNT_CONTROL - Traffic generator error count control register
- ***************************************************************************/
-/* DDR34_PHY_CONTROL_REGS_1 :: TRAFFIC_GEN_ERR_CNT_CONTROL :: reserved0 [31:09] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_TRAFFIC_GEN_ERR_CNT_CONTROL_reserved0_MASK 0xfffffe00
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_TRAFFIC_GEN_ERR_CNT_CONTROL_reserved0_SHIFT 9
-
-/* DDR34_PHY_CONTROL_REGS_1 :: TRAFFIC_GEN_ERR_CNT_CONTROL :: DQ_SEL [08:04] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_TRAFFIC_GEN_ERR_CNT_CONTROL_DQ_SEL_MASK 0x000001f0
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_TRAFFIC_GEN_ERR_CNT_CONTROL_DQ_SEL_SHIFT 4
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_TRAFFIC_GEN_ERR_CNT_CONTROL_DQ_SEL_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_1 :: TRAFFIC_GEN_ERR_CNT_CONTROL :: reserved1 [03:02] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_TRAFFIC_GEN_ERR_CNT_CONTROL_reserved1_MASK 0x0000000c
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_TRAFFIC_GEN_ERR_CNT_CONTROL_reserved1_SHIFT 2
-
-/* DDR34_PHY_CONTROL_REGS_1 :: TRAFFIC_GEN_ERR_CNT_CONTROL :: CLEAR [01:01] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_TRAFFIC_GEN_ERR_CNT_CONTROL_CLEAR_MASK 0x00000002
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_TRAFFIC_GEN_ERR_CNT_CONTROL_CLEAR_SHIFT 1
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_TRAFFIC_GEN_ERR_CNT_CONTROL_CLEAR_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_1 :: TRAFFIC_GEN_ERR_CNT_CONTROL :: ENABLE [00:00] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_TRAFFIC_GEN_ERR_CNT_CONTROL_ENABLE_MASK 0x00000001
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_TRAFFIC_GEN_ERR_CNT_CONTROL_ENABLE_SHIFT 0
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_TRAFFIC_GEN_ERR_CNT_CONTROL_ENABLE_DEFAULT 0x00000000
-
-/***************************************************************************
- *TRAFFIC_GEN_ERR_CNT_STATUS - Traffic generator error count status register
- ***************************************************************************/
-/* DDR34_PHY_CONTROL_REGS_1 :: TRAFFIC_GEN_ERR_CNT_STATUS :: reserved0 [31:16] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_TRAFFIC_GEN_ERR_CNT_STATUS_reserved0_MASK 0xffff0000
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_TRAFFIC_GEN_ERR_CNT_STATUS_reserved0_SHIFT 16
-
-/* DDR34_PHY_CONTROL_REGS_1 :: TRAFFIC_GEN_ERR_CNT_STATUS :: COUNT [15:00] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_TRAFFIC_GEN_ERR_CNT_STATUS_COUNT_MASK 0x0000ffff
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_TRAFFIC_GEN_ERR_CNT_STATUS_COUNT_SHIFT 0
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_TRAFFIC_GEN_ERR_CNT_STATUS_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *VIRTUAL_VTT_CONTROL - Virtual VTT Control and Status register
- ***************************************************************************/
-/* DDR34_PHY_CONTROL_REGS_1 :: VIRTUAL_VTT_CONTROL :: reserved0 [31:12] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VIRTUAL_VTT_CONTROL_reserved0_MASK 0xfffff000
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VIRTUAL_VTT_CONTROL_reserved0_SHIFT 12
-
-/* DDR34_PHY_CONTROL_REGS_1 :: VIRTUAL_VTT_CONTROL :: reserved_for_eco1 [11:08] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VIRTUAL_VTT_CONTROL_reserved_for_eco1_MASK 0x00000f00
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VIRTUAL_VTT_CONTROL_reserved_for_eco1_SHIFT 8
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VIRTUAL_VTT_CONTROL_reserved_for_eco1_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_1 :: VIRTUAL_VTT_CONTROL :: MAX_NOISE [07:07] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VIRTUAL_VTT_CONTROL_MAX_NOISE_MASK 0x00000080
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VIRTUAL_VTT_CONTROL_MAX_NOISE_SHIFT 7
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VIRTUAL_VTT_CONTROL_MAX_NOISE_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_1 :: VIRTUAL_VTT_CONTROL :: LOW_NOISE [06:06] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VIRTUAL_VTT_CONTROL_LOW_NOISE_MASK 0x00000040
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VIRTUAL_VTT_CONTROL_LOW_NOISE_SHIFT 6
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VIRTUAL_VTT_CONTROL_LOW_NOISE_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_1 :: VIRTUAL_VTT_CONTROL :: LOW_VTT [05:05] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VIRTUAL_VTT_CONTROL_LOW_VTT_MASK 0x00000020
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VIRTUAL_VTT_CONTROL_LOW_VTT_SHIFT 5
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VIRTUAL_VTT_CONTROL_LOW_VTT_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_1 :: VIRTUAL_VTT_CONTROL :: HIGH_VTT [04:04] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VIRTUAL_VTT_CONTROL_HIGH_VTT_MASK 0x00000010
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VIRTUAL_VTT_CONTROL_HIGH_VTT_SHIFT 4
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VIRTUAL_VTT_CONTROL_HIGH_VTT_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_1 :: VIRTUAL_VTT_CONTROL :: ERROR_RESET [03:03] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VIRTUAL_VTT_CONTROL_ERROR_RESET_MASK 0x00000008
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VIRTUAL_VTT_CONTROL_ERROR_RESET_SHIFT 3
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VIRTUAL_VTT_CONTROL_ERROR_RESET_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_1 :: VIRTUAL_VTT_CONTROL :: ENABLE_CTL_IDLE [02:02] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VIRTUAL_VTT_CONTROL_ENABLE_CTL_IDLE_MASK 0x00000004
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VIRTUAL_VTT_CONTROL_ENABLE_CTL_IDLE_SHIFT 2
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VIRTUAL_VTT_CONTROL_ENABLE_CTL_IDLE_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_1 :: VIRTUAL_VTT_CONTROL :: ENABLE_CS_IDLE [01:01] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VIRTUAL_VTT_CONTROL_ENABLE_CS_IDLE_MASK 0x00000002
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VIRTUAL_VTT_CONTROL_ENABLE_CS_IDLE_SHIFT 1
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VIRTUAL_VTT_CONTROL_ENABLE_CS_IDLE_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_1 :: VIRTUAL_VTT_CONTROL :: ENABLE_CKE_IDLE [00:00] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VIRTUAL_VTT_CONTROL_ENABLE_CKE_IDLE_MASK 0x00000001
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VIRTUAL_VTT_CONTROL_ENABLE_CKE_IDLE_SHIFT 0
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VIRTUAL_VTT_CONTROL_ENABLE_CKE_IDLE_DEFAULT 0x00000000
-
-/***************************************************************************
- *VIRTUAL_VTT_STATUS - Virtual VTT Control and Status register
- ***************************************************************************/
-/* DDR34_PHY_CONTROL_REGS_1 :: VIRTUAL_VTT_STATUS :: reserved0 [31:19] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VIRTUAL_VTT_STATUS_reserved0_MASK 0xfff80000
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VIRTUAL_VTT_STATUS_reserved0_SHIFT 19
-
-/* DDR34_PHY_CONTROL_REGS_1 :: VIRTUAL_VTT_STATUS :: ERROR [18:03] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VIRTUAL_VTT_STATUS_ERROR_MASK 0x0007fff8
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VIRTUAL_VTT_STATUS_ERROR_SHIFT 3
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VIRTUAL_VTT_STATUS_ERROR_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_1 :: VIRTUAL_VTT_STATUS :: ERROR_LOW [02:02] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VIRTUAL_VTT_STATUS_ERROR_LOW_MASK 0x00000004
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VIRTUAL_VTT_STATUS_ERROR_LOW_SHIFT 2
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VIRTUAL_VTT_STATUS_ERROR_LOW_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_1 :: VIRTUAL_VTT_STATUS :: ERROR_HIGH [01:01] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VIRTUAL_VTT_STATUS_ERROR_HIGH_MASK 0x00000002
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VIRTUAL_VTT_STATUS_ERROR_HIGH_SHIFT 1
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VIRTUAL_VTT_STATUS_ERROR_HIGH_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_1 :: VIRTUAL_VTT_STATUS :: READY [00:00] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VIRTUAL_VTT_STATUS_READY_MASK 0x00000001
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VIRTUAL_VTT_STATUS_READY_SHIFT 0
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VIRTUAL_VTT_STATUS_READY_DEFAULT 0x00000000
-
-/***************************************************************************
- *VIRTUAL_VTT_CONNECTIONS - Virtual VTT Connections register
- ***************************************************************************/
-/* DDR34_PHY_CONTROL_REGS_1 :: VIRTUAL_VTT_CONNECTIONS :: reserved0 [31:31] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VIRTUAL_VTT_CONNECTIONS_reserved0_MASK 0x80000000
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VIRTUAL_VTT_CONNECTIONS_reserved0_SHIFT 31
-
-/* DDR34_PHY_CONTROL_REGS_1 :: VIRTUAL_VTT_CONNECTIONS :: MASK [30:00] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VIRTUAL_VTT_CONNECTIONS_MASK_MASK 0x7fffffff
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VIRTUAL_VTT_CONNECTIONS_MASK_SHIFT 0
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VIRTUAL_VTT_CONNECTIONS_MASK_DEFAULT 0x1fffffff
-
-/***************************************************************************
- *VIRTUAL_VTT_OVERRIDE - Virtual VTT Override register
- ***************************************************************************/
-/* DDR34_PHY_CONTROL_REGS_1 :: VIRTUAL_VTT_OVERRIDE :: reserved0 [31:31] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VIRTUAL_VTT_OVERRIDE_reserved0_MASK 0x80000000
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VIRTUAL_VTT_OVERRIDE_reserved0_SHIFT 31
-
-/* DDR34_PHY_CONTROL_REGS_1 :: VIRTUAL_VTT_OVERRIDE :: MASK [30:00] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VIRTUAL_VTT_OVERRIDE_MASK_MASK 0x7fffffff
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VIRTUAL_VTT_OVERRIDE_MASK_SHIFT 0
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VIRTUAL_VTT_OVERRIDE_MASK_DEFAULT 0x0000ffff
-
-/***************************************************************************
- *VREF_DAC_CONTROL - VREF DAC Control register
- ***************************************************************************/
-/* DDR34_PHY_CONTROL_REGS_1 :: VREF_DAC_CONTROL :: reserved0 [31:20] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VREF_DAC_CONTROL_reserved0_MASK 0xfff00000
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VREF_DAC_CONTROL_reserved0_SHIFT 20
-
-/* DDR34_PHY_CONTROL_REGS_1 :: VREF_DAC_CONTROL :: AUX_GT_INT [19:19] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VREF_DAC_CONTROL_AUX_GT_INT_MASK 0x00080000
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VREF_DAC_CONTROL_AUX_GT_INT_SHIFT 19
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VREF_DAC_CONTROL_AUX_GT_INT_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_1 :: VREF_DAC_CONTROL :: TESTOUT_MUX_CTL [18:17] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VREF_DAC_CONTROL_TESTOUT_MUX_CTL_MASK 0x00060000
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VREF_DAC_CONTROL_TESTOUT_MUX_CTL_SHIFT 17
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VREF_DAC_CONTROL_TESTOUT_MUX_CTL_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_1 :: VREF_DAC_CONTROL :: TEST [16:16] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VREF_DAC_CONTROL_TEST_MASK 0x00010000
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VREF_DAC_CONTROL_TEST_SHIFT 16
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VREF_DAC_CONTROL_TEST_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_1 :: VREF_DAC_CONTROL :: PDN3 [15:15] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VREF_DAC_CONTROL_PDN3_MASK 0x00008000
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VREF_DAC_CONTROL_PDN3_SHIFT 15
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VREF_DAC_CONTROL_PDN3_DEFAULT 0x00000001
-
-/* DDR34_PHY_CONTROL_REGS_1 :: VREF_DAC_CONTROL :: PDN2 [14:14] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VREF_DAC_CONTROL_PDN2_MASK 0x00004000
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VREF_DAC_CONTROL_PDN2_SHIFT 14
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VREF_DAC_CONTROL_PDN2_DEFAULT 0x00000001
-
-/* DDR34_PHY_CONTROL_REGS_1 :: VREF_DAC_CONTROL :: PDN1 [13:13] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VREF_DAC_CONTROL_PDN1_MASK 0x00002000
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VREF_DAC_CONTROL_PDN1_SHIFT 13
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VREF_DAC_CONTROL_PDN1_DEFAULT 0x00000001
-
-/* DDR34_PHY_CONTROL_REGS_1 :: VREF_DAC_CONTROL :: PDN0 [12:12] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VREF_DAC_CONTROL_PDN0_MASK 0x00001000
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VREF_DAC_CONTROL_PDN0_SHIFT 12
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VREF_DAC_CONTROL_PDN0_DEFAULT 0x00000001
-
-/* DDR34_PHY_CONTROL_REGS_1 :: VREF_DAC_CONTROL :: DAC1 [11:06] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VREF_DAC_CONTROL_DAC1_MASK 0x00000fc0
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VREF_DAC_CONTROL_DAC1_SHIFT 6
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VREF_DAC_CONTROL_DAC1_DEFAULT 0x00000020
-
-/* DDR34_PHY_CONTROL_REGS_1 :: VREF_DAC_CONTROL :: DAC0 [05:00] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VREF_DAC_CONTROL_DAC0_MASK 0x0000003f
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VREF_DAC_CONTROL_DAC0_SHIFT 0
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_VREF_DAC_CONTROL_DAC0_DEFAULT 0x00000020
-
-/***************************************************************************
- *PHYBIST_CNTRL - PhyBist Control Register
- ***************************************************************************/
-/* DDR34_PHY_CONTROL_REGS_1 :: PHYBIST_CNTRL :: reserved0 [31:30] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_PHYBIST_CNTRL_reserved0_MASK 0xc0000000
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_PHYBIST_CNTRL_reserved0_SHIFT 30
-
-/* DDR34_PHY_CONTROL_REGS_1 :: PHYBIST_CNTRL :: CLK_PAD_ENB [29:28] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_PHYBIST_CNTRL_CLK_PAD_ENB_MASK 0x30000000
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_PHYBIST_CNTRL_CLK_PAD_ENB_SHIFT 28
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_PHYBIST_CNTRL_CLK_PAD_ENB_DEFAULT 0x00000002
-
-/* DDR34_PHY_CONTROL_REGS_1 :: PHYBIST_CNTRL :: reserved1 [27:27] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_PHYBIST_CNTRL_reserved1_MASK 0x08000000
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_PHYBIST_CNTRL_reserved1_SHIFT 27
-
-/* DDR34_PHY_CONTROL_REGS_1 :: PHYBIST_CNTRL :: FORCE_DQ_ERROR_SEL [26:24] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_PHYBIST_CNTRL_FORCE_DQ_ERROR_SEL_MASK 0x07000000
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_PHYBIST_CNTRL_FORCE_DQ_ERROR_SEL_SHIFT 24
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_PHYBIST_CNTRL_FORCE_DQ_ERROR_SEL_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_1 :: PHYBIST_CNTRL :: reserved_for_eco2 [23:23] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_PHYBIST_CNTRL_reserved_for_eco2_MASK 0x00800000
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_PHYBIST_CNTRL_reserved_for_eco2_SHIFT 23
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_PHYBIST_CNTRL_reserved_for_eco2_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_1 :: PHYBIST_CNTRL :: FORCE_BL_ERROR_SEL [22:20] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_PHYBIST_CNTRL_FORCE_BL_ERROR_SEL_MASK 0x00700000
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_PHYBIST_CNTRL_FORCE_BL_ERROR_SEL_SHIFT 20
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_PHYBIST_CNTRL_FORCE_BL_ERROR_SEL_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_1 :: PHYBIST_CNTRL :: reserved_for_eco3 [19:17] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_PHYBIST_CNTRL_reserved_for_eco3_MASK 0x000e0000
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_PHYBIST_CNTRL_reserved_for_eco3_SHIFT 17
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_PHYBIST_CNTRL_reserved_for_eco3_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_1 :: PHYBIST_CNTRL :: FORCE_CTL_ERROR_SEL [16:12] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_PHYBIST_CNTRL_FORCE_CTL_ERROR_SEL_MASK 0x0001f000
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_PHYBIST_CNTRL_FORCE_CTL_ERROR_SEL_SHIFT 12
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_PHYBIST_CNTRL_FORCE_CTL_ERROR_SEL_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_1 :: PHYBIST_CNTRL :: reserved4 [11:10] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_PHYBIST_CNTRL_reserved4_MASK 0x00000c00
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_PHYBIST_CNTRL_reserved4_SHIFT 10
-
-/* DDR34_PHY_CONTROL_REGS_1 :: PHYBIST_CNTRL :: FORCE_DAT_ERROR [09:09] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_PHYBIST_CNTRL_FORCE_DAT_ERROR_MASK 0x00000200
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_PHYBIST_CNTRL_FORCE_DAT_ERROR_SHIFT 9
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_PHYBIST_CNTRL_FORCE_DAT_ERROR_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_1 :: PHYBIST_CNTRL :: FORCE_CTL_ERROR [08:08] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_PHYBIST_CNTRL_FORCE_CTL_ERROR_MASK 0x00000100
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_PHYBIST_CNTRL_FORCE_CTL_ERROR_SHIFT 8
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_PHYBIST_CNTRL_FORCE_CTL_ERROR_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_1 :: PHYBIST_CNTRL :: SSO [07:06] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_PHYBIST_CNTRL_SSO_MASK 0x000000c0
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_PHYBIST_CNTRL_SSO_SHIFT 6
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_PHYBIST_CNTRL_SSO_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_1 :: PHYBIST_CNTRL :: LENGTH [05:04] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_PHYBIST_CNTRL_LENGTH_MASK 0x00000030
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_PHYBIST_CNTRL_LENGTH_SHIFT 4
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_PHYBIST_CNTRL_LENGTH_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_1 :: PHYBIST_CNTRL :: MODE [03:01] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_PHYBIST_CNTRL_MODE_MASK 0x0000000e
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_PHYBIST_CNTRL_MODE_SHIFT 1
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_PHYBIST_CNTRL_MODE_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_1 :: PHYBIST_CNTRL :: ENABLE [00:00] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_PHYBIST_CNTRL_ENABLE_MASK 0x00000001
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_PHYBIST_CNTRL_ENABLE_SHIFT 0
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_PHYBIST_CNTRL_ENABLE_DEFAULT 0x00000000
-
-/***************************************************************************
- *PHYBIST_SEED - PhyBist Seed Register
- ***************************************************************************/
-/* DDR34_PHY_CONTROL_REGS_1 :: PHYBIST_SEED :: SEED [31:00] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_PHYBIST_SEED_SEED_MASK 0xffffffff
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_PHYBIST_SEED_SEED_SHIFT 0
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_PHYBIST_SEED_SEED_DEFAULT 0xba5eba11
-
-/***************************************************************************
- *PHYBIST_STATUS - PhyBist General Status Register
- ***************************************************************************/
-/* DDR34_PHY_CONTROL_REGS_1 :: PHYBIST_STATUS :: reserved0 [31:04] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_PHYBIST_STATUS_reserved0_MASK 0xfffffff0
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_PHYBIST_STATUS_reserved0_SHIFT 4
-
-/* DDR34_PHY_CONTROL_REGS_1 :: PHYBIST_STATUS :: DAT_PASS [03:03] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_PHYBIST_STATUS_DAT_PASS_MASK 0x00000008
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_PHYBIST_STATUS_DAT_PASS_SHIFT 3
-
-/* DDR34_PHY_CONTROL_REGS_1 :: PHYBIST_STATUS :: CTL_PASS [02:02] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_PHYBIST_STATUS_CTL_PASS_MASK 0x00000004
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_PHYBIST_STATUS_CTL_PASS_SHIFT 2
-
-/* DDR34_PHY_CONTROL_REGS_1 :: PHYBIST_STATUS :: DAT_DONE [01:01] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_PHYBIST_STATUS_DAT_DONE_MASK 0x00000002
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_PHYBIST_STATUS_DAT_DONE_SHIFT 1
-
-/* DDR34_PHY_CONTROL_REGS_1 :: PHYBIST_STATUS :: CTL_DONE [00:00] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_PHYBIST_STATUS_CTL_DONE_MASK 0x00000001
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_PHYBIST_STATUS_CTL_DONE_SHIFT 0
-
-/***************************************************************************
- *PHYBIST_CTL_STATUS - PhyBist Per-Bit Control Pad Status Register
- ***************************************************************************/
-/* DDR34_PHY_CONTROL_REGS_1 :: PHYBIST_CTL_STATUS :: reserved0 [31:31] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_PHYBIST_CTL_STATUS_reserved0_MASK 0x80000000
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_PHYBIST_CTL_STATUS_reserved0_SHIFT 31
-
-/* DDR34_PHY_CONTROL_REGS_1 :: PHYBIST_CTL_STATUS :: CTL_ERRORS [30:00] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_PHYBIST_CTL_STATUS_CTL_ERRORS_MASK 0x7fffffff
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_PHYBIST_CTL_STATUS_CTL_ERRORS_SHIFT 0
-
-/***************************************************************************
- *PHYBIST_BL0_STATUS - PhyBist Byte Lane #0 Status Register
- ***************************************************************************/
-/* DDR34_PHY_CONTROL_REGS_1 :: PHYBIST_BL0_STATUS :: reserved0 [31:10] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_PHYBIST_BL0_STATUS_reserved0_MASK 0xfffffc00
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_PHYBIST_BL0_STATUS_reserved0_SHIFT 10
-
-/* DDR34_PHY_CONTROL_REGS_1 :: PHYBIST_BL0_STATUS :: EDC [09:09] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_PHYBIST_BL0_STATUS_EDC_MASK 0x00000200
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_PHYBIST_BL0_STATUS_EDC_SHIFT 9
-
-/* DDR34_PHY_CONTROL_REGS_1 :: PHYBIST_BL0_STATUS :: DM [08:08] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_PHYBIST_BL0_STATUS_DM_MASK 0x00000100
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_PHYBIST_BL0_STATUS_DM_SHIFT 8
-
-/* DDR34_PHY_CONTROL_REGS_1 :: PHYBIST_BL0_STATUS :: DQ [07:00] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_PHYBIST_BL0_STATUS_DQ_MASK 0x000000ff
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_PHYBIST_BL0_STATUS_DQ_SHIFT 0
-
-/***************************************************************************
- *PHYBIST_BL1_STATUS - PhyBist Byte Lane #1 Status Register
- ***************************************************************************/
-/* DDR34_PHY_CONTROL_REGS_1 :: PHYBIST_BL1_STATUS :: reserved0 [31:10] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_PHYBIST_BL1_STATUS_reserved0_MASK 0xfffffc00
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_PHYBIST_BL1_STATUS_reserved0_SHIFT 10
-
-/* DDR34_PHY_CONTROL_REGS_1 :: PHYBIST_BL1_STATUS :: EDC [09:09] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_PHYBIST_BL1_STATUS_EDC_MASK 0x00000200
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_PHYBIST_BL1_STATUS_EDC_SHIFT 9
-
-/* DDR34_PHY_CONTROL_REGS_1 :: PHYBIST_BL1_STATUS :: DM [08:08] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_PHYBIST_BL1_STATUS_DM_MASK 0x00000100
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_PHYBIST_BL1_STATUS_DM_SHIFT 8
-
-/* DDR34_PHY_CONTROL_REGS_1 :: PHYBIST_BL1_STATUS :: DQ [07:00] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_PHYBIST_BL1_STATUS_DQ_MASK 0x000000ff
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_PHYBIST_BL1_STATUS_DQ_SHIFT 0
-
-/***************************************************************************
- *PHYBIST_BL2_STATUS - PhyBist Byte Lane #2 Status Register
- ***************************************************************************/
-/* DDR34_PHY_CONTROL_REGS_1 :: PHYBIST_BL2_STATUS :: reserved0 [31:10] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_PHYBIST_BL2_STATUS_reserved0_MASK 0xfffffc00
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_PHYBIST_BL2_STATUS_reserved0_SHIFT 10
-
-/* DDR34_PHY_CONTROL_REGS_1 :: PHYBIST_BL2_STATUS :: EDC [09:09] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_PHYBIST_BL2_STATUS_EDC_MASK 0x00000200
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_PHYBIST_BL2_STATUS_EDC_SHIFT 9
-
-/* DDR34_PHY_CONTROL_REGS_1 :: PHYBIST_BL2_STATUS :: DM [08:08] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_PHYBIST_BL2_STATUS_DM_MASK 0x00000100
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_PHYBIST_BL2_STATUS_DM_SHIFT 8
-
-/* DDR34_PHY_CONTROL_REGS_1 :: PHYBIST_BL2_STATUS :: DQ [07:00] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_PHYBIST_BL2_STATUS_DQ_MASK 0x000000ff
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_PHYBIST_BL2_STATUS_DQ_SHIFT 0
-
-/***************************************************************************
- *PHYBIST_BL3_STATUS - PhyBist Byte Lane #3 Status Register
- ***************************************************************************/
-/* DDR34_PHY_CONTROL_REGS_1 :: PHYBIST_BL3_STATUS :: reserved0 [31:10] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_PHYBIST_BL3_STATUS_reserved0_MASK 0xfffffc00
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_PHYBIST_BL3_STATUS_reserved0_SHIFT 10
-
-/* DDR34_PHY_CONTROL_REGS_1 :: PHYBIST_BL3_STATUS :: EDC [09:09] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_PHYBIST_BL3_STATUS_EDC_MASK 0x00000200
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_PHYBIST_BL3_STATUS_EDC_SHIFT 9
-
-/* DDR34_PHY_CONTROL_REGS_1 :: PHYBIST_BL3_STATUS :: DM [08:08] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_PHYBIST_BL3_STATUS_DM_MASK 0x00000100
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_PHYBIST_BL3_STATUS_DM_SHIFT 8
-
-/* DDR34_PHY_CONTROL_REGS_1 :: PHYBIST_BL3_STATUS :: DQ [07:00] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_PHYBIST_BL3_STATUS_DQ_MASK 0x000000ff
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_PHYBIST_BL3_STATUS_DQ_SHIFT 0
-
-/***************************************************************************
- *PHYBIST_BL4_STATUS - PhyBist Byte Lane #4 (ECC) Status Register
- ***************************************************************************/
-/* DDR34_PHY_CONTROL_REGS_1 :: PHYBIST_BL4_STATUS :: reserved0 [31:10] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_PHYBIST_BL4_STATUS_reserved0_MASK 0xfffffc00
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_PHYBIST_BL4_STATUS_reserved0_SHIFT 10
-
-/* DDR34_PHY_CONTROL_REGS_1 :: PHYBIST_BL4_STATUS :: EDC [09:09] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_PHYBIST_BL4_STATUS_EDC_MASK 0x00000200
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_PHYBIST_BL4_STATUS_EDC_SHIFT 9
-
-/* DDR34_PHY_CONTROL_REGS_1 :: PHYBIST_BL4_STATUS :: DM [08:08] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_PHYBIST_BL4_STATUS_DM_MASK 0x00000100
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_PHYBIST_BL4_STATUS_DM_SHIFT 8
-
-/* DDR34_PHY_CONTROL_REGS_1 :: PHYBIST_BL4_STATUS :: DQ [07:00] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_PHYBIST_BL4_STATUS_DQ_MASK 0x000000ff
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_PHYBIST_BL4_STATUS_DQ_SHIFT 0
-
-/***************************************************************************
- *STANDBY_CONTROL - Standby Control register
- ***************************************************************************/
-/* DDR34_PHY_CONTROL_REGS_1 :: STANDBY_CONTROL :: reserved0 [31:23] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_STANDBY_CONTROL_reserved0_MASK 0xff800000
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_STANDBY_CONTROL_reserved0_SHIFT 23
-
-/* DDR34_PHY_CONTROL_REGS_1 :: STANDBY_CONTROL :: STANDBY_READY [22:22] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_STANDBY_CONTROL_STANDBY_READY_MASK 0x00400000
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_STANDBY_CONTROL_STANDBY_READY_SHIFT 22
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_STANDBY_CONTROL_STANDBY_READY_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_1 :: STANDBY_CONTROL :: STANDBY_EXIT_PIN_EN [21:21] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_STANDBY_CONTROL_STANDBY_EXIT_PIN_EN_MASK 0x00200000
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_STANDBY_CONTROL_STANDBY_EXIT_PIN_EN_SHIFT 21
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_STANDBY_CONTROL_STANDBY_EXIT_PIN_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_1 :: STANDBY_CONTROL :: STANDBY_ACTIVE [20:20] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_STANDBY_CONTROL_STANDBY_ACTIVE_MASK 0x00100000
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_STANDBY_CONTROL_STANDBY_ACTIVE_SHIFT 20
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_STANDBY_CONTROL_STANDBY_ACTIVE_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_1 :: STANDBY_CONTROL :: ARMED [19:19] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_STANDBY_CONTROL_ARMED_MASK 0x00080000
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_STANDBY_CONTROL_ARMED_SHIFT 19
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_STANDBY_CONTROL_ARMED_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_1 :: STANDBY_CONTROL :: WARMSTART [18:18] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_STANDBY_CONTROL_WARMSTART_MASK 0x00040000
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_STANDBY_CONTROL_WARMSTART_SHIFT 18
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_STANDBY_CONTROL_WARMSTART_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_1 :: STANDBY_CONTROL :: PWRDOWN_LDO_BIAS [17:16] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_STANDBY_CONTROL_PWRDOWN_LDO_BIAS_MASK 0x00030000
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_STANDBY_CONTROL_PWRDOWN_LDO_BIAS_SHIFT 16
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_STANDBY_CONTROL_PWRDOWN_LDO_BIAS_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_1 :: STANDBY_CONTROL :: PWRDOWN_LDO_VOLTS [15:14] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_STANDBY_CONTROL_PWRDOWN_LDO_VOLTS_MASK 0x0000c000
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_STANDBY_CONTROL_PWRDOWN_LDO_VOLTS_SHIFT 14
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_STANDBY_CONTROL_PWRDOWN_LDO_VOLTS_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_1 :: STANDBY_CONTROL :: PWRDOWN_SKIP_MRS [13:13] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_STANDBY_CONTROL_PWRDOWN_SKIP_MRS_MASK 0x00002000
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_STANDBY_CONTROL_PWRDOWN_SKIP_MRS_SHIFT 13
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_STANDBY_CONTROL_PWRDOWN_SKIP_MRS_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_1 :: STANDBY_CONTROL :: PWRDOWN_RST_N [12:12] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_STANDBY_CONTROL_PWRDOWN_RST_N_MASK 0x00001000
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_STANDBY_CONTROL_PWRDOWN_RST_N_SHIFT 12
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_STANDBY_CONTROL_PWRDOWN_RST_N_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_1 :: STANDBY_CONTROL :: PWRDOWN_CKE [11:11] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_STANDBY_CONTROL_PWRDOWN_CKE_MASK 0x00000800
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_STANDBY_CONTROL_PWRDOWN_CKE_SHIFT 11
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_STANDBY_CONTROL_PWRDOWN_CKE_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_1 :: STANDBY_CONTROL :: LDO_BIAS [10:09] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_STANDBY_CONTROL_LDO_BIAS_MASK 0x00000600
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_STANDBY_CONTROL_LDO_BIAS_SHIFT 9
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_STANDBY_CONTROL_LDO_BIAS_DEFAULT 0x00000003
-
-/* DDR34_PHY_CONTROL_REGS_1 :: STANDBY_CONTROL :: LDO_VOLTS [08:07] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_STANDBY_CONTROL_LDO_VOLTS_MASK 0x00000180
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_STANDBY_CONTROL_LDO_VOLTS_SHIFT 7
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_STANDBY_CONTROL_LDO_VOLTS_DEFAULT 0x00000001
-
-/* DDR34_PHY_CONTROL_REGS_1 :: STANDBY_CONTROL :: SKIP_MRS [06:06] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_STANDBY_CONTROL_SKIP_MRS_MASK 0x00000040
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_STANDBY_CONTROL_SKIP_MRS_SHIFT 6
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_STANDBY_CONTROL_SKIP_MRS_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_1 :: STANDBY_CONTROL :: RST_N [05:05] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_STANDBY_CONTROL_RST_N_MASK 0x00000020
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_STANDBY_CONTROL_RST_N_SHIFT 5
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_STANDBY_CONTROL_RST_N_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_1 :: STANDBY_CONTROL :: CKE [04:04] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_STANDBY_CONTROL_CKE_MASK 0x00000010
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_STANDBY_CONTROL_CKE_SHIFT 4
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_STANDBY_CONTROL_CKE_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_1 :: STANDBY_CONTROL :: STANDBY [03:00] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_STANDBY_CONTROL_STANDBY_MASK 0x0000000f
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_STANDBY_CONTROL_STANDBY_SHIFT 0
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_STANDBY_CONTROL_STANDBY_DEFAULT 0x00000000
-
-/***************************************************************************
- *DEBUG_FREEZE_ENABLE - Freeze-on-error enable register
- ***************************************************************************/
-/* DDR34_PHY_CONTROL_REGS_1 :: DEBUG_FREEZE_ENABLE :: reserved0 [31:05] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_DEBUG_FREEZE_ENABLE_reserved0_MASK 0xffffffe0
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_DEBUG_FREEZE_ENABLE_reserved0_SHIFT 5
-
-/* DDR34_PHY_CONTROL_REGS_1 :: DEBUG_FREEZE_ENABLE :: WLECC [04:04] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_DEBUG_FREEZE_ENABLE_WLECC_MASK 0x00000010
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_DEBUG_FREEZE_ENABLE_WLECC_SHIFT 4
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_DEBUG_FREEZE_ENABLE_WLECC_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_1 :: DEBUG_FREEZE_ENABLE :: WL1_BL1 [03:03] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_DEBUG_FREEZE_ENABLE_WL1_BL1_MASK 0x00000008
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_DEBUG_FREEZE_ENABLE_WL1_BL1_SHIFT 3
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_DEBUG_FREEZE_ENABLE_WL1_BL1_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_1 :: DEBUG_FREEZE_ENABLE :: WL1_BL0 [02:02] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_DEBUG_FREEZE_ENABLE_WL1_BL0_MASK 0x00000004
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_DEBUG_FREEZE_ENABLE_WL1_BL0_SHIFT 2
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_DEBUG_FREEZE_ENABLE_WL1_BL0_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_1 :: DEBUG_FREEZE_ENABLE :: WL0_BL1 [01:01] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_DEBUG_FREEZE_ENABLE_WL0_BL1_MASK 0x00000002
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_DEBUG_FREEZE_ENABLE_WL0_BL1_SHIFT 1
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_DEBUG_FREEZE_ENABLE_WL0_BL1_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_1 :: DEBUG_FREEZE_ENABLE :: WL0_BL0 [00:00] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_DEBUG_FREEZE_ENABLE_WL0_BL0_MASK 0x00000001
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_DEBUG_FREEZE_ENABLE_WL0_BL0_SHIFT 0
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_DEBUG_FREEZE_ENABLE_WL0_BL0_DEFAULT 0x00000000
-
-/***************************************************************************
- *DEBUG_MUX_CONTROL - Debug Mux Control register
- ***************************************************************************/
-/* DDR34_PHY_CONTROL_REGS_1 :: DEBUG_MUX_CONTROL :: reserved0 [31:11] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_DEBUG_MUX_CONTROL_reserved0_MASK 0xfffff800
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_DEBUG_MUX_CONTROL_reserved0_SHIFT 11
-
-/* DDR34_PHY_CONTROL_REGS_1 :: DEBUG_MUX_CONTROL :: BYTE_SEL [10:08] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_DEBUG_MUX_CONTROL_BYTE_SEL_MASK 0x00000700
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_DEBUG_MUX_CONTROL_BYTE_SEL_SHIFT 8
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_DEBUG_MUX_CONTROL_BYTE_SEL_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_1 :: DEBUG_MUX_CONTROL :: reserved1 [07:06] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_DEBUG_MUX_CONTROL_reserved1_MASK 0x000000c0
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_DEBUG_MUX_CONTROL_reserved1_SHIFT 6
-
-/* DDR34_PHY_CONTROL_REGS_1 :: DEBUG_MUX_CONTROL :: PHASE_SEL [05:04] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_DEBUG_MUX_CONTROL_PHASE_SEL_MASK 0x00000030
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_DEBUG_MUX_CONTROL_PHASE_SEL_SHIFT 4
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_DEBUG_MUX_CONTROL_PHASE_SEL_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_1 :: DEBUG_MUX_CONTROL :: SOURCE_SEL [03:00] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_DEBUG_MUX_CONTROL_SOURCE_SEL_MASK 0x0000000f
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_DEBUG_MUX_CONTROL_SOURCE_SEL_SHIFT 0
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_DEBUG_MUX_CONTROL_SOURCE_SEL_DEFAULT 0x00000000
-
-/***************************************************************************
- *DFI_CNTRL - DFI Interface Ownership Control register
- ***************************************************************************/
-/* DDR34_PHY_CONTROL_REGS_1 :: DFI_CNTRL :: reserved0 [31:07] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_DFI_CNTRL_reserved0_MASK 0xffffff80
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_DFI_CNTRL_reserved0_SHIFT 7
-
-/* DDR34_PHY_CONTROL_REGS_1 :: DFI_CNTRL :: DFI_CS1 [06:06] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_DFI_CNTRL_DFI_CS1_MASK 0x00000040
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_DFI_CNTRL_DFI_CS1_SHIFT 6
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_DFI_CNTRL_DFI_CS1_DEFAULT 0x00000001
-
-/* DDR34_PHY_CONTROL_REGS_1 :: DFI_CNTRL :: DFI_CS0 [05:05] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_DFI_CNTRL_DFI_CS0_MASK 0x00000020
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_DFI_CNTRL_DFI_CS0_SHIFT 5
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_DFI_CNTRL_DFI_CS0_DEFAULT 0x00000001
-
-/* DDR34_PHY_CONTROL_REGS_1 :: DFI_CNTRL :: DFI_RST_N [04:04] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_DFI_CNTRL_DFI_RST_N_MASK 0x00000010
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_DFI_CNTRL_DFI_RST_N_SHIFT 4
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_DFI_CNTRL_DFI_RST_N_DEFAULT 0x00000001
-
-/* DDR34_PHY_CONTROL_REGS_1 :: DFI_CNTRL :: DFI_CKE [03:03] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_DFI_CNTRL_DFI_CKE_MASK 0x00000008
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_DFI_CNTRL_DFI_CKE_SHIFT 3
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_DFI_CNTRL_DFI_CKE_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_1 :: DFI_CNTRL :: ACK_ENABLE [02:02] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_DFI_CNTRL_ACK_ENABLE_MASK 0x00000004
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_DFI_CNTRL_ACK_ENABLE_SHIFT 2
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_DFI_CNTRL_ACK_ENABLE_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_1 :: DFI_CNTRL :: ACK_STATUS [01:01] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_DFI_CNTRL_ACK_STATUS_MASK 0x00000002
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_DFI_CNTRL_ACK_STATUS_SHIFT 1
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_DFI_CNTRL_ACK_STATUS_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_1 :: DFI_CNTRL :: ASSERT_REQ [00:00] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_DFI_CNTRL_ASSERT_REQ_MASK 0x00000001
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_DFI_CNTRL_ASSERT_REQ_SHIFT 0
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_DFI_CNTRL_ASSERT_REQ_DEFAULT 0x00000001
-
-/***************************************************************************
- *WRITE_ODT_CNTRL - Write ODT Control register
- ***************************************************************************/
-/* DDR34_PHY_CONTROL_REGS_1 :: WRITE_ODT_CNTRL :: reserved0 [31:13] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_WRITE_ODT_CNTRL_reserved0_MASK 0xffffe000
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_WRITE_ODT_CNTRL_reserved0_SHIFT 13
-
-/* DDR34_PHY_CONTROL_REGS_1 :: WRITE_ODT_CNTRL :: ODT_FORCE_VALUE [12:12] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_WRITE_ODT_CNTRL_ODT_FORCE_VALUE_MASK 0x00001000
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_WRITE_ODT_CNTRL_ODT_FORCE_VALUE_SHIFT 12
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_WRITE_ODT_CNTRL_ODT_FORCE_VALUE_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_1 :: WRITE_ODT_CNTRL :: ODT_FORCE [11:11] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_WRITE_ODT_CNTRL_ODT_FORCE_MASK 0x00000800
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_WRITE_ODT_CNTRL_ODT_FORCE_SHIFT 11
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_WRITE_ODT_CNTRL_ODT_FORCE_DEFAULT 0x00000001
-
-/* DDR34_PHY_CONTROL_REGS_1 :: WRITE_ODT_CNTRL :: ODT_ENABLE [10:10] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_WRITE_ODT_CNTRL_ODT_ENABLE_MASK 0x00000400
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_WRITE_ODT_CNTRL_ODT_ENABLE_SHIFT 10
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_WRITE_ODT_CNTRL_ODT_ENABLE_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_1 :: WRITE_ODT_CNTRL :: ODT_LENGTH [09:06] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_WRITE_ODT_CNTRL_ODT_LENGTH_MASK 0x000003c0
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_WRITE_ODT_CNTRL_ODT_LENGTH_SHIFT 6
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_WRITE_ODT_CNTRL_ODT_LENGTH_DEFAULT 0x00000004
-
-/* DDR34_PHY_CONTROL_REGS_1 :: WRITE_ODT_CNTRL :: ODT_DELAY [05:00] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_WRITE_ODT_CNTRL_ODT_DELAY_MASK 0x0000003f
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_WRITE_ODT_CNTRL_ODT_DELAY_SHIFT 0
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_WRITE_ODT_CNTRL_ODT_DELAY_DEFAULT 0x00000010
-
-/***************************************************************************
- *ABI_PAR_CNTRL - ABI and PAR Control register
- ***************************************************************************/
-/* DDR34_PHY_CONTROL_REGS_1 :: ABI_PAR_CNTRL :: reserved0 [31:04] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_ABI_PAR_CNTRL_reserved0_MASK 0xfffffff0
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_ABI_PAR_CNTRL_reserved0_SHIFT 4
-
-/* DDR34_PHY_CONTROL_REGS_1 :: ABI_PAR_CNTRL :: PAR_INCLUDE_AUX [03:03] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_ABI_PAR_CNTRL_PAR_INCLUDE_AUX_MASK 0x00000008
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_ABI_PAR_CNTRL_PAR_INCLUDE_AUX_SHIFT 3
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_ABI_PAR_CNTRL_PAR_INCLUDE_AUX_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_1 :: ABI_PAR_CNTRL :: PAR_ENABLE [02:02] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_ABI_PAR_CNTRL_PAR_ENABLE_MASK 0x00000004
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_ABI_PAR_CNTRL_PAR_ENABLE_SHIFT 2
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_ABI_PAR_CNTRL_PAR_ENABLE_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_1 :: ABI_PAR_CNTRL :: ABI_INCLUDE_AUX [01:01] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_ABI_PAR_CNTRL_ABI_INCLUDE_AUX_MASK 0x00000002
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_ABI_PAR_CNTRL_ABI_INCLUDE_AUX_SHIFT 1
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_ABI_PAR_CNTRL_ABI_INCLUDE_AUX_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_1 :: ABI_PAR_CNTRL :: ABI_ENABLE [00:00] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_ABI_PAR_CNTRL_ABI_ENABLE_MASK 0x00000001
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_ABI_PAR_CNTRL_ABI_ENABLE_SHIFT 0
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_ABI_PAR_CNTRL_ABI_ENABLE_DEFAULT 0x00000000
-
-/***************************************************************************
- *ZQ_CAL - ZQ Calibration Control register
- ***************************************************************************/
-/* DDR34_PHY_CONTROL_REGS_1 :: ZQ_CAL :: reserved0 [31:20] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_ZQ_CAL_reserved0_MASK 0xfff00000
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_ZQ_CAL_reserved0_SHIFT 20
-
-/* DDR34_PHY_CONTROL_REGS_1 :: ZQ_CAL :: ZQ_STATUS [19:19] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_ZQ_CAL_ZQ_STATUS_MASK 0x00080000
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_ZQ_CAL_ZQ_STATUS_SHIFT 19
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_ZQ_CAL_ZQ_STATUS_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_1 :: ZQ_CAL :: ZQ_RXENB [18:18] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_ZQ_CAL_ZQ_RXENB_MASK 0x00040000
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_ZQ_CAL_ZQ_RXENB_SHIFT 18
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_ZQ_CAL_ZQ_RXENB_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_1 :: ZQ_CAL :: ZQ_IDDQ [17:17] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_ZQ_CAL_ZQ_IDDQ_MASK 0x00020000
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_ZQ_CAL_ZQ_IDDQ_SHIFT 17
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_ZQ_CAL_ZQ_IDDQ_DEFAULT 0x00000001
-
-/* DDR34_PHY_CONTROL_REGS_1 :: ZQ_CAL :: ZQ_DRIVE_N [16:12] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_ZQ_CAL_ZQ_DRIVE_N_MASK 0x0001f000
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_ZQ_CAL_ZQ_DRIVE_N_SHIFT 12
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_ZQ_CAL_ZQ_DRIVE_N_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_1 :: ZQ_CAL :: ZQ_DRIVE_P [11:07] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_ZQ_CAL_ZQ_DRIVE_P_MASK 0x00000f80
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_ZQ_CAL_ZQ_DRIVE_P_SHIFT 7
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_ZQ_CAL_ZQ_DRIVE_P_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_1 :: ZQ_CAL :: ZQ_TX_MODE [06:03] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_ZQ_CAL_ZQ_TX_MODE_MASK 0x00000078
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_ZQ_CAL_ZQ_TX_MODE_SHIFT 3
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_ZQ_CAL_ZQ_TX_MODE_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_1 :: ZQ_CAL :: ZQ_RX_MODE [02:00] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_ZQ_CAL_ZQ_RX_MODE_MASK 0x00000007
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_ZQ_CAL_ZQ_RX_MODE_SHIFT 0
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_ZQ_CAL_ZQ_RX_MODE_DEFAULT 0x00000000
-
-/***************************************************************************
- *AC_SPARE_REG - Address and Control Spare register
- ***************************************************************************/
-/* DDR34_PHY_CONTROL_REGS_1 :: AC_SPARE_REG :: reserved_for_eco0 [31:00] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_AC_SPARE_REG_reserved_for_eco0_MASK 0xffffffff
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_AC_SPARE_REG_reserved_for_eco0_SHIFT 0
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_AC_SPARE_REG_reserved_for_eco0_DEFAULT 0x00000000
-
-#endif /* #ifndef BCHP_DDR34_PHY_CONTROL_REGS_1_H__ */
-
-/* End of File */
diff --git a/include/linux/brcmstb/7145a0/bchp_ebi.h b/include/linux/brcmstb/7145a0/bchp_ebi.h
deleted file mode 100644
index 73624d6..0000000
--- a/include/linux/brcmstb/7145a0/bchp_ebi.h
+++ /dev/null
@@ -1,2005 +0,0 @@
-/***************************************************************************
- * Copyright (c) 1999-2013, Broadcom Corporation
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
- *
- * Module Description:
- * DO NOT EDIT THIS FILE DIRECTLY
- *
- * This module was generated magically with RDB from a source description
- * file. You must edit the source file for changes to be made to this file.
- *
- *
- * Date: Generated on Sat Apr 6 03:07:48 2013
- * MD5 Checksum d41d8cd98f00b204e9800998ecf8427e
- *
- * Compiled with: RDB Utility combo_header.pl
- * RDB Parser 3.0
- * unknown unknown
- * Perl Interpreter 5.008008
- * Operating System linux
- *
- * Revision History:
- *
- * $brcm_Log: $
- *
- ***************************************************************************/
-
-#ifndef BCHP_EBI_H__
-#define BCHP_EBI_H__
-
-/***************************************************************************
- *EBI - EBI Registers
- ***************************************************************************/
-#define BCHP_EBI_CS_BASE_HI_0 0x203d0800 /* Upper 8-bit of EBI CS Base 0 Register */
-#define BCHP_EBI_CS_BASE_0 0x203d0804 /* Lower 32-bit of EBI CS Base 0 Register */
-#define BCHP_EBI_CS_CONFIG_0 0x203d0808 /* EBI CS Config 0 Register */
-#define BCHP_EBI_CS_BASE_HI_1 0x203d080c /* Upper 8-bit of EBI CS Base 1 Register */
-#define BCHP_EBI_CS_BASE_1 0x203d0810 /* Lower 32-bit of EBI CS Base 1 Register */
-#define BCHP_EBI_CS_CONFIG_1 0x203d0814 /* EBI CS Config 1 Register */
-#define BCHP_EBI_CS_BASE_HI_2 0x203d0818 /* Upper 8-bit of EBI CS Base 2 Register */
-#define BCHP_EBI_CS_BASE_2 0x203d081c /* Lower 32-bit of EBI CS Base 2 Register */
-#define BCHP_EBI_CS_CONFIG_2 0x203d0820 /* EBI CS Config 2 Register */
-#define BCHP_EBI_CS_BASE_HI_3 0x203d0824 /* Upper 8-bit of EBI CS Base 3 Register */
-#define BCHP_EBI_CS_BASE_3 0x203d0828 /* Lower 32-bit of EBI CS Base 3 Register */
-#define BCHP_EBI_CS_CONFIG_3 0x203d082c /* EBI CS Config 3 Register */
-#define BCHP_EBI_CS_BASE_HI_4 0x203d0830 /* Upper 8-bit of EBI CS Base 4 Register */
-#define BCHP_EBI_CS_BASE_4 0x203d0834 /* Lower 32-bit of EBI CS Base 4 Register */
-#define BCHP_EBI_CS_CONFIG_4 0x203d0838 /* EBI CS Config 4 Register */
-#define BCHP_EBI_CS_BASE_HI_5 0x203d083c /* Upper 8-bit of EBI CS Base 5 Register */
-#define BCHP_EBI_CS_BASE_5 0x203d0840 /* Lower 32-bit of EBI CS Base 5 Register */
-#define BCHP_EBI_CS_CONFIG_5 0x203d0844 /* EBI CS Config 5 Register */
-#define BCHP_EBI_CS_BASE_HI_6 0x203d0848 /* Upper 8-bit of EBI CS Base 6 Register */
-#define BCHP_EBI_CS_BASE_6 0x203d084c /* Lower 32-bit of EBI CS Base 6 Register */
-#define BCHP_EBI_CS_CONFIG_6 0x203d0850 /* EBI CS Config 6 Register */
-#define BCHP_EBI_BURST_CFG_0 0x203d0860 /* EBI Synchronous Intel StrataFlash Burst Configure Register */
-#define BCHP_EBI_BURST_CFG_1 0x203d0864 /* EBI Synchronous Intel StrataFlash Burst Configure Register */
-#define BCHP_EBI_BURST_CFG_2 0x203d0868 /* EBI Synchronous Intel StrataFlash Burst Configure Register */
-#define BCHP_EBI_BURST_CFG_3 0x203d086c /* EBI Synchronous Intel StrataFlash Burst Configure Register */
-#define BCHP_EBI_BURST_CFG_4 0x203d0870 /* EBI Synchronous Intel StrataFlash Burst Configure Register */
-#define BCHP_EBI_BURST_CFG_5 0x203d0874 /* EBI Synchronous Intel StrataFlash Burst Configure Register */
-#define BCHP_EBI_BURST_CFG_6 0x203d0878 /* EBI Synchronous Intel StrataFlash Burst Configure Register */
-#define BCHP_EBI_ECR 0x203d0900 /* EBI Configuration Register */
-#define BCHP_EBI_CS_TRISTATE_CFG 0x203d0918 /* EBI CS Tristate Configuration Register */
-#define BCHP_EBI_CS_SPI_SELECT 0x203d0920 /* SPI CS Select */
-#define BCHP_EBI_ARRAY_ADDRESS 0x203d09f0 /* EBI Data Array Address */
-
-/***************************************************************************
- *CS_BASE_HI_0 - Upper 8-bit of EBI CS Base 0 Register
- ***************************************************************************/
-/* EBI :: CS_BASE_HI_0 :: reserved0 [31:08] */
-#define BCHP_EBI_CS_BASE_HI_0_reserved0_MASK 0xffffff00
-#define BCHP_EBI_CS_BASE_HI_0_reserved0_SHIFT 8
-
-/* EBI :: CS_BASE_HI_0 :: base_addr_hi [07:00] */
-#define BCHP_EBI_CS_BASE_HI_0_base_addr_hi_MASK 0x000000ff
-#define BCHP_EBI_CS_BASE_HI_0_base_addr_hi_SHIFT 0
-#define BCHP_EBI_CS_BASE_HI_0_base_addr_hi_DEFAULT 0x00000000
-
-/***************************************************************************
- *CS_BASE_0 - Lower 32-bit of EBI CS Base 0 Register
- ***************************************************************************/
-/* EBI :: CS_BASE_0 :: base_addr [31:13] */
-#define BCHP_EBI_CS_BASE_0_base_addr_MASK 0xffffe000
-#define BCHP_EBI_CS_BASE_0_base_addr_SHIFT 13
-
-/* EBI :: CS_BASE_0 :: reserved0 [12:04] */
-#define BCHP_EBI_CS_BASE_0_reserved0_MASK 0x00001ff0
-#define BCHP_EBI_CS_BASE_0_reserved0_SHIFT 4
-
-/* EBI :: CS_BASE_0 :: size [03:00] */
-#define BCHP_EBI_CS_BASE_0_size_MASK 0x0000000f
-#define BCHP_EBI_CS_BASE_0_size_SHIFT 0
-#define BCHP_EBI_CS_BASE_0_size_SIZE_8KB 0
-#define BCHP_EBI_CS_BASE_0_size_SIZE_16KB 1
-#define BCHP_EBI_CS_BASE_0_size_SIZE_32KB 2
-#define BCHP_EBI_CS_BASE_0_size_SIZE_64KB 3
-#define BCHP_EBI_CS_BASE_0_size_SIZE_128KB 4
-#define BCHP_EBI_CS_BASE_0_size_SIZE_256KB 5
-#define BCHP_EBI_CS_BASE_0_size_SIZE_512KB 6
-#define BCHP_EBI_CS_BASE_0_size_SIZE_1MB 7
-#define BCHP_EBI_CS_BASE_0_size_SIZE_2MB 8
-#define BCHP_EBI_CS_BASE_0_size_SIZE_4MB 9
-#define BCHP_EBI_CS_BASE_0_size_SIZE_8MB 10
-#define BCHP_EBI_CS_BASE_0_size_SIZE_16MB 11
-#define BCHP_EBI_CS_BASE_0_size_SIZE_32MB 12
-#define BCHP_EBI_CS_BASE_0_size_SIZE_64MB 13
-#define BCHP_EBI_CS_BASE_0_size_SIZE_128MB 14
-#define BCHP_EBI_CS_BASE_0_size_SIZE_256MB 15
-
-/***************************************************************************
- *CS_CONFIG_0 - EBI CS Config 0 Register
- ***************************************************************************/
-/* EBI :: CS_CONFIG_0 :: mem_io [31:31] */
-#define BCHP_EBI_CS_CONFIG_0_mem_io_MASK 0x80000000
-#define BCHP_EBI_CS_CONFIG_0_mem_io_SHIFT 31
-#define BCHP_EBI_CS_CONFIG_0_mem_io_DEFAULT 0x00000000
-
-/* EBI :: CS_CONFIG_0 :: ta_wait [30:30] */
-#define BCHP_EBI_CS_CONFIG_0_ta_wait_MASK 0x40000000
-#define BCHP_EBI_CS_CONFIG_0_ta_wait_SHIFT 30
-#define BCHP_EBI_CS_CONFIG_0_ta_wait_DEFAULT 0x00000000
-
-/* EBI :: CS_CONFIG_0 :: wp [29:29] */
-#define BCHP_EBI_CS_CONFIG_0_wp_MASK 0x20000000
-#define BCHP_EBI_CS_CONFIG_0_wp_SHIFT 29
-#define BCHP_EBI_CS_CONFIG_0_wp_DEFAULT 0x00000000
-
-/* EBI :: CS_CONFIG_0 :: wait_count [28:24] */
-#define BCHP_EBI_CS_CONFIG_0_wait_count_MASK 0x1f000000
-#define BCHP_EBI_CS_CONFIG_0_wait_count_SHIFT 24
-#define BCHP_EBI_CS_CONFIG_0_wait_count_DEFAULT 0x00000007
-
-/* EBI :: CS_CONFIG_0 :: t_hold [23:20] */
-#define BCHP_EBI_CS_CONFIG_0_t_hold_MASK 0x00f00000
-#define BCHP_EBI_CS_CONFIG_0_t_hold_SHIFT 20
-#define BCHP_EBI_CS_CONFIG_0_t_hold_DEFAULT 0x00000000
-
-/* EBI :: CS_CONFIG_0 :: t_setup [19:16] */
-#define BCHP_EBI_CS_CONFIG_0_t_setup_MASK 0x000f0000
-#define BCHP_EBI_CS_CONFIG_0_t_setup_SHIFT 16
-#define BCHP_EBI_CS_CONFIG_0_t_setup_DEFAULT 0x00000000
-
-/* EBI :: CS_CONFIG_0 :: cs_hold [15:15] */
-#define BCHP_EBI_CS_CONFIG_0_cs_hold_MASK 0x00008000
-#define BCHP_EBI_CS_CONFIG_0_cs_hold_SHIFT 15
-#define BCHP_EBI_CS_CONFIG_0_cs_hold_DEFAULT 0x00000000
-
-/* EBI :: CS_CONFIG_0 :: split_cs [14:14] */
-#define BCHP_EBI_CS_CONFIG_0_split_cs_MASK 0x00004000
-#define BCHP_EBI_CS_CONFIG_0_split_cs_SHIFT 14
-#define BCHP_EBI_CS_CONFIG_0_split_cs_DEFAULT 0x00000000
-
-/* EBI :: CS_CONFIG_0 :: mask_en [13:13] */
-#define BCHP_EBI_CS_CONFIG_0_mask_en_MASK 0x00002000
-#define BCHP_EBI_CS_CONFIG_0_mask_en_SHIFT 13
-#define BCHP_EBI_CS_CONFIG_0_mask_en_DEFAULT 0x00000000
-
-/* EBI :: CS_CONFIG_0 :: ne_sample [12:12] */
-#define BCHP_EBI_CS_CONFIG_0_ne_sample_MASK 0x00001000
-#define BCHP_EBI_CS_CONFIG_0_ne_sample_SHIFT 12
-#define BCHP_EBI_CS_CONFIG_0_ne_sample_DEFAULT 0x00000000
-
-/* EBI :: CS_CONFIG_0 :: m68k [11:11] */
-#define BCHP_EBI_CS_CONFIG_0_m68k_MASK 0x00000800
-#define BCHP_EBI_CS_CONFIG_0_m68k_SHIFT 11
-#define BCHP_EBI_CS_CONFIG_0_m68k_DEFAULT 0x00000000
-
-/* EBI :: CS_CONFIG_0 :: le [10:10] */
-#define BCHP_EBI_CS_CONFIG_0_le_MASK 0x00000400
-#define BCHP_EBI_CS_CONFIG_0_le_SHIFT 10
-
-/* EBI :: CS_CONFIG_0 :: fast_read [09:09] */
-#define BCHP_EBI_CS_CONFIG_0_fast_read_MASK 0x00000200
-#define BCHP_EBI_CS_CONFIG_0_fast_read_SHIFT 9
-#define BCHP_EBI_CS_CONFIG_0_fast_read_DEFAULT 0x00000000
-#define BCHP_EBI_CS_CONFIG_0_fast_read_Normal 0
-#define BCHP_EBI_CS_CONFIG_0_fast_read_Fast_Read_Enable 1
-
-/* EBI :: CS_CONFIG_0 :: size_sel [08:08] */
-#define BCHP_EBI_CS_CONFIG_0_size_sel_MASK 0x00000100
-#define BCHP_EBI_CS_CONFIG_0_size_sel_SHIFT 8
-#define BCHP_EBI_CS_CONFIG_0_size_sel_DEFAULT 0x00000000
-
-/* EBI :: CS_CONFIG_0 :: sync [07:07] */
-#define BCHP_EBI_CS_CONFIG_0_sync_MASK 0x00000080
-#define BCHP_EBI_CS_CONFIG_0_sync_SHIFT 7
-#define BCHP_EBI_CS_CONFIG_0_sync_DEFAULT 0x00000000
-
-/* EBI :: CS_CONFIG_0 :: polarity [06:06] */
-#define BCHP_EBI_CS_CONFIG_0_polarity_MASK 0x00000040
-#define BCHP_EBI_CS_CONFIG_0_polarity_SHIFT 6
-#define BCHP_EBI_CS_CONFIG_0_polarity_DEFAULT 0x00000000
-
-/* EBI :: CS_CONFIG_0 :: we_ctl [05:05] */
-#define BCHP_EBI_CS_CONFIG_0_we_ctl_MASK 0x00000020
-#define BCHP_EBI_CS_CONFIG_0_we_ctl_SHIFT 5
-#define BCHP_EBI_CS_CONFIG_0_we_ctl_DEFAULT 0x00000000
-
-/* EBI :: CS_CONFIG_0 :: dest_size [04:04] */
-#define BCHP_EBI_CS_CONFIG_0_dest_size_MASK 0x00000010
-#define BCHP_EBI_CS_CONFIG_0_dest_size_SHIFT 4
-
-/* EBI :: CS_CONFIG_0 :: ms_inh [03:03] */
-#define BCHP_EBI_CS_CONFIG_0_ms_inh_MASK 0x00000008
-#define BCHP_EBI_CS_CONFIG_0_ms_inh_SHIFT 3
-#define BCHP_EBI_CS_CONFIG_0_ms_inh_DEFAULT 0x00000000
-
-/* EBI :: CS_CONFIG_0 :: ls_inh [02:02] */
-#define BCHP_EBI_CS_CONFIG_0_ls_inh_MASK 0x00000004
-#define BCHP_EBI_CS_CONFIG_0_ls_inh_SHIFT 2
-#define BCHP_EBI_CS_CONFIG_0_ls_inh_DEFAULT 0x00000000
-
-/* EBI :: CS_CONFIG_0 :: bcachen [01:01] */
-#define BCHP_EBI_CS_CONFIG_0_bcachen_MASK 0x00000002
-#define BCHP_EBI_CS_CONFIG_0_bcachen_SHIFT 1
-#define BCHP_EBI_CS_CONFIG_0_bcachen_DEFAULT 0x00000000
-
-/* EBI :: CS_CONFIG_0 :: enable [00:00] */
-#define BCHP_EBI_CS_CONFIG_0_enable_MASK 0x00000001
-#define BCHP_EBI_CS_CONFIG_0_enable_SHIFT 0
-#define BCHP_EBI_CS_CONFIG_0_enable_DEFAULT 0x00000001
-
-/***************************************************************************
- *CS_BASE_HI_1 - Upper 8-bit of EBI CS Base 1 Register
- ***************************************************************************/
-/* EBI :: CS_BASE_HI_1 :: reserved0 [31:08] */
-#define BCHP_EBI_CS_BASE_HI_1_reserved0_MASK 0xffffff00
-#define BCHP_EBI_CS_BASE_HI_1_reserved0_SHIFT 8
-
-/* EBI :: CS_BASE_HI_1 :: base_addr_hi [07:00] */
-#define BCHP_EBI_CS_BASE_HI_1_base_addr_hi_MASK 0x000000ff
-#define BCHP_EBI_CS_BASE_HI_1_base_addr_hi_SHIFT 0
-#define BCHP_EBI_CS_BASE_HI_1_base_addr_hi_DEFAULT 0x00000000
-
-/***************************************************************************
- *CS_BASE_1 - Lower 32-bit of EBI CS Base 1 Register
- ***************************************************************************/
-/* EBI :: CS_BASE_1 :: base_addr [31:13] */
-#define BCHP_EBI_CS_BASE_1_base_addr_MASK 0xffffe000
-#define BCHP_EBI_CS_BASE_1_base_addr_SHIFT 13
-#define BCHP_EBI_CS_BASE_1_base_addr_DEFAULT 0x00000000
-
-/* EBI :: CS_BASE_1 :: reserved0 [12:04] */
-#define BCHP_EBI_CS_BASE_1_reserved0_MASK 0x00001ff0
-#define BCHP_EBI_CS_BASE_1_reserved0_SHIFT 4
-
-/* EBI :: CS_BASE_1 :: size [03:00] */
-#define BCHP_EBI_CS_BASE_1_size_MASK 0x0000000f
-#define BCHP_EBI_CS_BASE_1_size_SHIFT 0
-#define BCHP_EBI_CS_BASE_1_size_DEFAULT 0x00000000
-#define BCHP_EBI_CS_BASE_1_size_SIZE_8KB 0
-#define BCHP_EBI_CS_BASE_1_size_SIZE_16KB 1
-#define BCHP_EBI_CS_BASE_1_size_SIZE_32KB 2
-#define BCHP_EBI_CS_BASE_1_size_SIZE_64KB 3
-#define BCHP_EBI_CS_BASE_1_size_SIZE_128KB 4
-#define BCHP_EBI_CS_BASE_1_size_SIZE_256KB 5
-#define BCHP_EBI_CS_BASE_1_size_SIZE_512KB 6
-#define BCHP_EBI_CS_BASE_1_size_SIZE_1MB 7
-#define BCHP_EBI_CS_BASE_1_size_SIZE_2MB 8
-#define BCHP_EBI_CS_BASE_1_size_SIZE_4MB 9
-#define BCHP_EBI_CS_BASE_1_size_SIZE_8MB 10
-#define BCHP_EBI_CS_BASE_1_size_SIZE_16MB 11
-#define BCHP_EBI_CS_BASE_1_size_SIZE_32MB 12
-#define BCHP_EBI_CS_BASE_1_size_SIZE_64MB 13
-#define BCHP_EBI_CS_BASE_1_size_SIZE_128MB 14
-#define BCHP_EBI_CS_BASE_1_size_SIZE_256MB 15
-
-/***************************************************************************
- *CS_CONFIG_1 - EBI CS Config 1 Register
- ***************************************************************************/
-/* EBI :: CS_CONFIG_1 :: mem_io [31:31] */
-#define BCHP_EBI_CS_CONFIG_1_mem_io_MASK 0x80000000
-#define BCHP_EBI_CS_CONFIG_1_mem_io_SHIFT 31
-#define BCHP_EBI_CS_CONFIG_1_mem_io_DEFAULT 0x00000000
-
-/* EBI :: CS_CONFIG_1 :: ta_wait [30:30] */
-#define BCHP_EBI_CS_CONFIG_1_ta_wait_MASK 0x40000000
-#define BCHP_EBI_CS_CONFIG_1_ta_wait_SHIFT 30
-#define BCHP_EBI_CS_CONFIG_1_ta_wait_DEFAULT 0x00000000
-
-/* EBI :: CS_CONFIG_1 :: wp [29:29] */
-#define BCHP_EBI_CS_CONFIG_1_wp_MASK 0x20000000
-#define BCHP_EBI_CS_CONFIG_1_wp_SHIFT 29
-#define BCHP_EBI_CS_CONFIG_1_wp_DEFAULT 0x00000000
-
-/* EBI :: CS_CONFIG_1 :: wait_count [28:24] */
-#define BCHP_EBI_CS_CONFIG_1_wait_count_MASK 0x1f000000
-#define BCHP_EBI_CS_CONFIG_1_wait_count_SHIFT 24
-#define BCHP_EBI_CS_CONFIG_1_wait_count_DEFAULT 0x00000007
-
-/* EBI :: CS_CONFIG_1 :: t_hold [23:20] */
-#define BCHP_EBI_CS_CONFIG_1_t_hold_MASK 0x00f00000
-#define BCHP_EBI_CS_CONFIG_1_t_hold_SHIFT 20
-#define BCHP_EBI_CS_CONFIG_1_t_hold_DEFAULT 0x00000000
-
-/* EBI :: CS_CONFIG_1 :: t_setup [19:16] */
-#define BCHP_EBI_CS_CONFIG_1_t_setup_MASK 0x000f0000
-#define BCHP_EBI_CS_CONFIG_1_t_setup_SHIFT 16
-#define BCHP_EBI_CS_CONFIG_1_t_setup_DEFAULT 0x00000000
-
-/* EBI :: CS_CONFIG_1 :: cs_hold [15:15] */
-#define BCHP_EBI_CS_CONFIG_1_cs_hold_MASK 0x00008000
-#define BCHP_EBI_CS_CONFIG_1_cs_hold_SHIFT 15
-#define BCHP_EBI_CS_CONFIG_1_cs_hold_DEFAULT 0x00000000
-
-/* EBI :: CS_CONFIG_1 :: split_cs [14:14] */
-#define BCHP_EBI_CS_CONFIG_1_split_cs_MASK 0x00004000
-#define BCHP_EBI_CS_CONFIG_1_split_cs_SHIFT 14
-#define BCHP_EBI_CS_CONFIG_1_split_cs_DEFAULT 0x00000000
-
-/* EBI :: CS_CONFIG_1 :: mask_en [13:13] */
-#define BCHP_EBI_CS_CONFIG_1_mask_en_MASK 0x00002000
-#define BCHP_EBI_CS_CONFIG_1_mask_en_SHIFT 13
-#define BCHP_EBI_CS_CONFIG_1_mask_en_DEFAULT 0x00000000
-
-/* EBI :: CS_CONFIG_1 :: ne_sample [12:12] */
-#define BCHP_EBI_CS_CONFIG_1_ne_sample_MASK 0x00001000
-#define BCHP_EBI_CS_CONFIG_1_ne_sample_SHIFT 12
-#define BCHP_EBI_CS_CONFIG_1_ne_sample_DEFAULT 0x00000000
-
-/* EBI :: CS_CONFIG_1 :: m68k [11:11] */
-#define BCHP_EBI_CS_CONFIG_1_m68k_MASK 0x00000800
-#define BCHP_EBI_CS_CONFIG_1_m68k_SHIFT 11
-#define BCHP_EBI_CS_CONFIG_1_m68k_DEFAULT 0x00000000
-
-/* EBI :: CS_CONFIG_1 :: le [10:10] */
-#define BCHP_EBI_CS_CONFIG_1_le_MASK 0x00000400
-#define BCHP_EBI_CS_CONFIG_1_le_SHIFT 10
-#define BCHP_EBI_CS_CONFIG_1_le_DEFAULT 0x00000000
-
-/* EBI :: CS_CONFIG_1 :: fast_read [09:09] */
-#define BCHP_EBI_CS_CONFIG_1_fast_read_MASK 0x00000200
-#define BCHP_EBI_CS_CONFIG_1_fast_read_SHIFT 9
-#define BCHP_EBI_CS_CONFIG_1_fast_read_DEFAULT 0x00000000
-#define BCHP_EBI_CS_CONFIG_1_fast_read_Normal 0
-#define BCHP_EBI_CS_CONFIG_1_fast_read_Fast_Read_Enable 1
-
-/* EBI :: CS_CONFIG_1 :: size_sel [08:08] */
-#define BCHP_EBI_CS_CONFIG_1_size_sel_MASK 0x00000100
-#define BCHP_EBI_CS_CONFIG_1_size_sel_SHIFT 8
-#define BCHP_EBI_CS_CONFIG_1_size_sel_DEFAULT 0x00000000
-
-/* EBI :: CS_CONFIG_1 :: sync [07:07] */
-#define BCHP_EBI_CS_CONFIG_1_sync_MASK 0x00000080
-#define BCHP_EBI_CS_CONFIG_1_sync_SHIFT 7
-#define BCHP_EBI_CS_CONFIG_1_sync_DEFAULT 0x00000000
-
-/* EBI :: CS_CONFIG_1 :: polarity [06:06] */
-#define BCHP_EBI_CS_CONFIG_1_polarity_MASK 0x00000040
-#define BCHP_EBI_CS_CONFIG_1_polarity_SHIFT 6
-#define BCHP_EBI_CS_CONFIG_1_polarity_DEFAULT 0x00000000
-
-/* EBI :: CS_CONFIG_1 :: we_ctl [05:05] */
-#define BCHP_EBI_CS_CONFIG_1_we_ctl_MASK 0x00000020
-#define BCHP_EBI_CS_CONFIG_1_we_ctl_SHIFT 5
-#define BCHP_EBI_CS_CONFIG_1_we_ctl_DEFAULT 0x00000000
-
-/* EBI :: CS_CONFIG_1 :: dest_size [04:04] */
-#define BCHP_EBI_CS_CONFIG_1_dest_size_MASK 0x00000010
-#define BCHP_EBI_CS_CONFIG_1_dest_size_SHIFT 4
-#define BCHP_EBI_CS_CONFIG_1_dest_size_DEFAULT 0x00000000
-
-/* EBI :: CS_CONFIG_1 :: ms_inh [03:03] */
-#define BCHP_EBI_CS_CONFIG_1_ms_inh_MASK 0x00000008
-#define BCHP_EBI_CS_CONFIG_1_ms_inh_SHIFT 3
-#define BCHP_EBI_CS_CONFIG_1_ms_inh_DEFAULT 0x00000000
-
-/* EBI :: CS_CONFIG_1 :: ls_inh [02:02] */
-#define BCHP_EBI_CS_CONFIG_1_ls_inh_MASK 0x00000004
-#define BCHP_EBI_CS_CONFIG_1_ls_inh_SHIFT 2
-#define BCHP_EBI_CS_CONFIG_1_ls_inh_DEFAULT 0x00000000
-
-/* EBI :: CS_CONFIG_1 :: bcachen [01:01] */
-#define BCHP_EBI_CS_CONFIG_1_bcachen_MASK 0x00000002
-#define BCHP_EBI_CS_CONFIG_1_bcachen_SHIFT 1
-#define BCHP_EBI_CS_CONFIG_1_bcachen_DEFAULT 0x00000000
-
-/* EBI :: CS_CONFIG_1 :: enable [00:00] */
-#define BCHP_EBI_CS_CONFIG_1_enable_MASK 0x00000001
-#define BCHP_EBI_CS_CONFIG_1_enable_SHIFT 0
-#define BCHP_EBI_CS_CONFIG_1_enable_DEFAULT 0x00000000
-
-/***************************************************************************
- *CS_BASE_HI_2 - Upper 8-bit of EBI CS Base 2 Register
- ***************************************************************************/
-/* EBI :: CS_BASE_HI_2 :: reserved0 [31:08] */
-#define BCHP_EBI_CS_BASE_HI_2_reserved0_MASK 0xffffff00
-#define BCHP_EBI_CS_BASE_HI_2_reserved0_SHIFT 8
-
-/* EBI :: CS_BASE_HI_2 :: base_addr_hi [07:00] */
-#define BCHP_EBI_CS_BASE_HI_2_base_addr_hi_MASK 0x000000ff
-#define BCHP_EBI_CS_BASE_HI_2_base_addr_hi_SHIFT 0
-#define BCHP_EBI_CS_BASE_HI_2_base_addr_hi_DEFAULT 0x00000000
-
-/***************************************************************************
- *CS_BASE_2 - Lower 32-bit of EBI CS Base 2 Register
- ***************************************************************************/
-/* EBI :: CS_BASE_2 :: base_addr [31:13] */
-#define BCHP_EBI_CS_BASE_2_base_addr_MASK 0xffffe000
-#define BCHP_EBI_CS_BASE_2_base_addr_SHIFT 13
-#define BCHP_EBI_CS_BASE_2_base_addr_DEFAULT 0x00000000
-
-/* EBI :: CS_BASE_2 :: reserved0 [12:04] */
-#define BCHP_EBI_CS_BASE_2_reserved0_MASK 0x00001ff0
-#define BCHP_EBI_CS_BASE_2_reserved0_SHIFT 4
-
-/* EBI :: CS_BASE_2 :: size [03:00] */
-#define BCHP_EBI_CS_BASE_2_size_MASK 0x0000000f
-#define BCHP_EBI_CS_BASE_2_size_SHIFT 0
-#define BCHP_EBI_CS_BASE_2_size_DEFAULT 0x00000000
-#define BCHP_EBI_CS_BASE_2_size_SIZE_8KB 0
-#define BCHP_EBI_CS_BASE_2_size_SIZE_16KB 1
-#define BCHP_EBI_CS_BASE_2_size_SIZE_32KB 2
-#define BCHP_EBI_CS_BASE_2_size_SIZE_64KB 3
-#define BCHP_EBI_CS_BASE_2_size_SIZE_128KB 4
-#define BCHP_EBI_CS_BASE_2_size_SIZE_256KB 5
-#define BCHP_EBI_CS_BASE_2_size_SIZE_512KB 6
-#define BCHP_EBI_CS_BASE_2_size_SIZE_1MB 7
-#define BCHP_EBI_CS_BASE_2_size_SIZE_2MB 8
-#define BCHP_EBI_CS_BASE_2_size_SIZE_4MB 9
-#define BCHP_EBI_CS_BASE_2_size_SIZE_8MB 10
-#define BCHP_EBI_CS_BASE_2_size_SIZE_16MB 11
-#define BCHP_EBI_CS_BASE_2_size_SIZE_32MB 12
-#define BCHP_EBI_CS_BASE_2_size_SIZE_64MB 13
-#define BCHP_EBI_CS_BASE_2_size_SIZE_128MB 14
-#define BCHP_EBI_CS_BASE_2_size_SIZE_256MB 15
-
-/***************************************************************************
- *CS_CONFIG_2 - EBI CS Config 2 Register
- ***************************************************************************/
-/* EBI :: CS_CONFIG_2 :: mem_io [31:31] */
-#define BCHP_EBI_CS_CONFIG_2_mem_io_MASK 0x80000000
-#define BCHP_EBI_CS_CONFIG_2_mem_io_SHIFT 31
-#define BCHP_EBI_CS_CONFIG_2_mem_io_DEFAULT 0x00000000
-
-/* EBI :: CS_CONFIG_2 :: ta_wait [30:30] */
-#define BCHP_EBI_CS_CONFIG_2_ta_wait_MASK 0x40000000
-#define BCHP_EBI_CS_CONFIG_2_ta_wait_SHIFT 30
-#define BCHP_EBI_CS_CONFIG_2_ta_wait_DEFAULT 0x00000000
-
-/* EBI :: CS_CONFIG_2 :: wp [29:29] */
-#define BCHP_EBI_CS_CONFIG_2_wp_MASK 0x20000000
-#define BCHP_EBI_CS_CONFIG_2_wp_SHIFT 29
-#define BCHP_EBI_CS_CONFIG_2_wp_DEFAULT 0x00000000
-
-/* EBI :: CS_CONFIG_2 :: wait_count [28:24] */
-#define BCHP_EBI_CS_CONFIG_2_wait_count_MASK 0x1f000000
-#define BCHP_EBI_CS_CONFIG_2_wait_count_SHIFT 24
-#define BCHP_EBI_CS_CONFIG_2_wait_count_DEFAULT 0x00000007
-
-/* EBI :: CS_CONFIG_2 :: t_hold [23:20] */
-#define BCHP_EBI_CS_CONFIG_2_t_hold_MASK 0x00f00000
-#define BCHP_EBI_CS_CONFIG_2_t_hold_SHIFT 20
-#define BCHP_EBI_CS_CONFIG_2_t_hold_DEFAULT 0x00000000
-
-/* EBI :: CS_CONFIG_2 :: t_setup [19:16] */
-#define BCHP_EBI_CS_CONFIG_2_t_setup_MASK 0x000f0000
-#define BCHP_EBI_CS_CONFIG_2_t_setup_SHIFT 16
-#define BCHP_EBI_CS_CONFIG_2_t_setup_DEFAULT 0x00000000
-
-/* EBI :: CS_CONFIG_2 :: cs_hold [15:15] */
-#define BCHP_EBI_CS_CONFIG_2_cs_hold_MASK 0x00008000
-#define BCHP_EBI_CS_CONFIG_2_cs_hold_SHIFT 15
-#define BCHP_EBI_CS_CONFIG_2_cs_hold_DEFAULT 0x00000000
-
-/* EBI :: CS_CONFIG_2 :: split_cs [14:14] */
-#define BCHP_EBI_CS_CONFIG_2_split_cs_MASK 0x00004000
-#define BCHP_EBI_CS_CONFIG_2_split_cs_SHIFT 14
-#define BCHP_EBI_CS_CONFIG_2_split_cs_DEFAULT 0x00000000
-
-/* EBI :: CS_CONFIG_2 :: mask_en [13:13] */
-#define BCHP_EBI_CS_CONFIG_2_mask_en_MASK 0x00002000
-#define BCHP_EBI_CS_CONFIG_2_mask_en_SHIFT 13
-#define BCHP_EBI_CS_CONFIG_2_mask_en_DEFAULT 0x00000000
-
-/* EBI :: CS_CONFIG_2 :: ne_sample [12:12] */
-#define BCHP_EBI_CS_CONFIG_2_ne_sample_MASK 0x00001000
-#define BCHP_EBI_CS_CONFIG_2_ne_sample_SHIFT 12
-#define BCHP_EBI_CS_CONFIG_2_ne_sample_DEFAULT 0x00000000
-
-/* EBI :: CS_CONFIG_2 :: m68k [11:11] */
-#define BCHP_EBI_CS_CONFIG_2_m68k_MASK 0x00000800
-#define BCHP_EBI_CS_CONFIG_2_m68k_SHIFT 11
-#define BCHP_EBI_CS_CONFIG_2_m68k_DEFAULT 0x00000000
-
-/* EBI :: CS_CONFIG_2 :: le [10:10] */
-#define BCHP_EBI_CS_CONFIG_2_le_MASK 0x00000400
-#define BCHP_EBI_CS_CONFIG_2_le_SHIFT 10
-#define BCHP_EBI_CS_CONFIG_2_le_DEFAULT 0x00000000
-
-/* EBI :: CS_CONFIG_2 :: fast_read [09:09] */
-#define BCHP_EBI_CS_CONFIG_2_fast_read_MASK 0x00000200
-#define BCHP_EBI_CS_CONFIG_2_fast_read_SHIFT 9
-#define BCHP_EBI_CS_CONFIG_2_fast_read_DEFAULT 0x00000000
-#define BCHP_EBI_CS_CONFIG_2_fast_read_Normal 0
-#define BCHP_EBI_CS_CONFIG_2_fast_read_Fast_Read_Enable 1
-
-/* EBI :: CS_CONFIG_2 :: size_sel [08:08] */
-#define BCHP_EBI_CS_CONFIG_2_size_sel_MASK 0x00000100
-#define BCHP_EBI_CS_CONFIG_2_size_sel_SHIFT 8
-#define BCHP_EBI_CS_CONFIG_2_size_sel_DEFAULT 0x00000000
-
-/* EBI :: CS_CONFIG_2 :: sync [07:07] */
-#define BCHP_EBI_CS_CONFIG_2_sync_MASK 0x00000080
-#define BCHP_EBI_CS_CONFIG_2_sync_SHIFT 7
-#define BCHP_EBI_CS_CONFIG_2_sync_DEFAULT 0x00000000
-
-/* EBI :: CS_CONFIG_2 :: polarity [06:06] */
-#define BCHP_EBI_CS_CONFIG_2_polarity_MASK 0x00000040
-#define BCHP_EBI_CS_CONFIG_2_polarity_SHIFT 6
-#define BCHP_EBI_CS_CONFIG_2_polarity_DEFAULT 0x00000000
-
-/* EBI :: CS_CONFIG_2 :: we_ctl [05:05] */
-#define BCHP_EBI_CS_CONFIG_2_we_ctl_MASK 0x00000020
-#define BCHP_EBI_CS_CONFIG_2_we_ctl_SHIFT 5
-#define BCHP_EBI_CS_CONFIG_2_we_ctl_DEFAULT 0x00000000
-
-/* EBI :: CS_CONFIG_2 :: dest_size [04:04] */
-#define BCHP_EBI_CS_CONFIG_2_dest_size_MASK 0x00000010
-#define BCHP_EBI_CS_CONFIG_2_dest_size_SHIFT 4
-#define BCHP_EBI_CS_CONFIG_2_dest_size_DEFAULT 0x00000000
-
-/* EBI :: CS_CONFIG_2 :: ms_inh [03:03] */
-#define BCHP_EBI_CS_CONFIG_2_ms_inh_MASK 0x00000008
-#define BCHP_EBI_CS_CONFIG_2_ms_inh_SHIFT 3
-#define BCHP_EBI_CS_CONFIG_2_ms_inh_DEFAULT 0x00000000
-
-/* EBI :: CS_CONFIG_2 :: ls_inh [02:02] */
-#define BCHP_EBI_CS_CONFIG_2_ls_inh_MASK 0x00000004
-#define BCHP_EBI_CS_CONFIG_2_ls_inh_SHIFT 2
-#define BCHP_EBI_CS_CONFIG_2_ls_inh_DEFAULT 0x00000000
-
-/* EBI :: CS_CONFIG_2 :: bcachen [01:01] */
-#define BCHP_EBI_CS_CONFIG_2_bcachen_MASK 0x00000002
-#define BCHP_EBI_CS_CONFIG_2_bcachen_SHIFT 1
-#define BCHP_EBI_CS_CONFIG_2_bcachen_DEFAULT 0x00000000
-
-/* EBI :: CS_CONFIG_2 :: enable [00:00] */
-#define BCHP_EBI_CS_CONFIG_2_enable_MASK 0x00000001
-#define BCHP_EBI_CS_CONFIG_2_enable_SHIFT 0
-#define BCHP_EBI_CS_CONFIG_2_enable_DEFAULT 0x00000000
-
-/***************************************************************************
- *CS_BASE_HI_3 - Upper 8-bit of EBI CS Base 3 Register
- ***************************************************************************/
-/* EBI :: CS_BASE_HI_3 :: reserved0 [31:08] */
-#define BCHP_EBI_CS_BASE_HI_3_reserved0_MASK 0xffffff00
-#define BCHP_EBI_CS_BASE_HI_3_reserved0_SHIFT 8
-
-/* EBI :: CS_BASE_HI_3 :: base_addr_hi [07:00] */
-#define BCHP_EBI_CS_BASE_HI_3_base_addr_hi_MASK 0x000000ff
-#define BCHP_EBI_CS_BASE_HI_3_base_addr_hi_SHIFT 0
-#define BCHP_EBI_CS_BASE_HI_3_base_addr_hi_DEFAULT 0x00000000
-
-/***************************************************************************
- *CS_BASE_3 - Lower 32-bit of EBI CS Base 3 Register
- ***************************************************************************/
-/* EBI :: CS_BASE_3 :: base_addr [31:13] */
-#define BCHP_EBI_CS_BASE_3_base_addr_MASK 0xffffe000
-#define BCHP_EBI_CS_BASE_3_base_addr_SHIFT 13
-#define BCHP_EBI_CS_BASE_3_base_addr_DEFAULT 0x00000000
-
-/* EBI :: CS_BASE_3 :: reserved0 [12:04] */
-#define BCHP_EBI_CS_BASE_3_reserved0_MASK 0x00001ff0
-#define BCHP_EBI_CS_BASE_3_reserved0_SHIFT 4
-
-/* EBI :: CS_BASE_3 :: size [03:00] */
-#define BCHP_EBI_CS_BASE_3_size_MASK 0x0000000f
-#define BCHP_EBI_CS_BASE_3_size_SHIFT 0
-#define BCHP_EBI_CS_BASE_3_size_DEFAULT 0x00000000
-#define BCHP_EBI_CS_BASE_3_size_SIZE_8KB 0
-#define BCHP_EBI_CS_BASE_3_size_SIZE_16KB 1
-#define BCHP_EBI_CS_BASE_3_size_SIZE_32KB 2
-#define BCHP_EBI_CS_BASE_3_size_SIZE_64KB 3
-#define BCHP_EBI_CS_BASE_3_size_SIZE_128KB 4
-#define BCHP_EBI_CS_BASE_3_size_SIZE_256KB 5
-#define BCHP_EBI_CS_BASE_3_size_SIZE_512KB 6
-#define BCHP_EBI_CS_BASE_3_size_SIZE_1MB 7
-#define BCHP_EBI_CS_BASE_3_size_SIZE_2MB 8
-#define BCHP_EBI_CS_BASE_3_size_SIZE_4MB 9
-#define BCHP_EBI_CS_BASE_3_size_SIZE_8MB 10
-#define BCHP_EBI_CS_BASE_3_size_SIZE_16MB 11
-#define BCHP_EBI_CS_BASE_3_size_SIZE_32MB 12
-#define BCHP_EBI_CS_BASE_3_size_SIZE_64MB 13
-#define BCHP_EBI_CS_BASE_3_size_SIZE_128MB 14
-#define BCHP_EBI_CS_BASE_3_size_SIZE_256MB 15
-
-/***************************************************************************
- *CS_CONFIG_3 - EBI CS Config 3 Register
- ***************************************************************************/
-/* EBI :: CS_CONFIG_3 :: mem_io [31:31] */
-#define BCHP_EBI_CS_CONFIG_3_mem_io_MASK 0x80000000
-#define BCHP_EBI_CS_CONFIG_3_mem_io_SHIFT 31
-#define BCHP_EBI_CS_CONFIG_3_mem_io_DEFAULT 0x00000000
-
-/* EBI :: CS_CONFIG_3 :: ta_wait [30:30] */
-#define BCHP_EBI_CS_CONFIG_3_ta_wait_MASK 0x40000000
-#define BCHP_EBI_CS_CONFIG_3_ta_wait_SHIFT 30
-#define BCHP_EBI_CS_CONFIG_3_ta_wait_DEFAULT 0x00000000
-
-/* EBI :: CS_CONFIG_3 :: wp [29:29] */
-#define BCHP_EBI_CS_CONFIG_3_wp_MASK 0x20000000
-#define BCHP_EBI_CS_CONFIG_3_wp_SHIFT 29
-#define BCHP_EBI_CS_CONFIG_3_wp_DEFAULT 0x00000000
-
-/* EBI :: CS_CONFIG_3 :: wait_count [28:24] */
-#define BCHP_EBI_CS_CONFIG_3_wait_count_MASK 0x1f000000
-#define BCHP_EBI_CS_CONFIG_3_wait_count_SHIFT 24
-#define BCHP_EBI_CS_CONFIG_3_wait_count_DEFAULT 0x00000007
-
-/* EBI :: CS_CONFIG_3 :: t_hold [23:20] */
-#define BCHP_EBI_CS_CONFIG_3_t_hold_MASK 0x00f00000
-#define BCHP_EBI_CS_CONFIG_3_t_hold_SHIFT 20
-#define BCHP_EBI_CS_CONFIG_3_t_hold_DEFAULT 0x00000000
-
-/* EBI :: CS_CONFIG_3 :: t_setup [19:16] */
-#define BCHP_EBI_CS_CONFIG_3_t_setup_MASK 0x000f0000
-#define BCHP_EBI_CS_CONFIG_3_t_setup_SHIFT 16
-#define BCHP_EBI_CS_CONFIG_3_t_setup_DEFAULT 0x00000000
-
-/* EBI :: CS_CONFIG_3 :: cs_hold [15:15] */
-#define BCHP_EBI_CS_CONFIG_3_cs_hold_MASK 0x00008000
-#define BCHP_EBI_CS_CONFIG_3_cs_hold_SHIFT 15
-#define BCHP_EBI_CS_CONFIG_3_cs_hold_DEFAULT 0x00000000
-
-/* EBI :: CS_CONFIG_3 :: split_cs [14:14] */
-#define BCHP_EBI_CS_CONFIG_3_split_cs_MASK 0x00004000
-#define BCHP_EBI_CS_CONFIG_3_split_cs_SHIFT 14
-#define BCHP_EBI_CS_CONFIG_3_split_cs_DEFAULT 0x00000000
-
-/* EBI :: CS_CONFIG_3 :: mask_en [13:13] */
-#define BCHP_EBI_CS_CONFIG_3_mask_en_MASK 0x00002000
-#define BCHP_EBI_CS_CONFIG_3_mask_en_SHIFT 13
-#define BCHP_EBI_CS_CONFIG_3_mask_en_DEFAULT 0x00000000
-
-/* EBI :: CS_CONFIG_3 :: ne_sample [12:12] */
-#define BCHP_EBI_CS_CONFIG_3_ne_sample_MASK 0x00001000
-#define BCHP_EBI_CS_CONFIG_3_ne_sample_SHIFT 12
-#define BCHP_EBI_CS_CONFIG_3_ne_sample_DEFAULT 0x00000000
-
-/* EBI :: CS_CONFIG_3 :: m68k [11:11] */
-#define BCHP_EBI_CS_CONFIG_3_m68k_MASK 0x00000800
-#define BCHP_EBI_CS_CONFIG_3_m68k_SHIFT 11
-#define BCHP_EBI_CS_CONFIG_3_m68k_DEFAULT 0x00000000
-
-/* EBI :: CS_CONFIG_3 :: le [10:10] */
-#define BCHP_EBI_CS_CONFIG_3_le_MASK 0x00000400
-#define BCHP_EBI_CS_CONFIG_3_le_SHIFT 10
-#define BCHP_EBI_CS_CONFIG_3_le_DEFAULT 0x00000000
-
-/* EBI :: CS_CONFIG_3 :: fast_read [09:09] */
-#define BCHP_EBI_CS_CONFIG_3_fast_read_MASK 0x00000200
-#define BCHP_EBI_CS_CONFIG_3_fast_read_SHIFT 9
-#define BCHP_EBI_CS_CONFIG_3_fast_read_DEFAULT 0x00000000
-#define BCHP_EBI_CS_CONFIG_3_fast_read_Normal 0
-#define BCHP_EBI_CS_CONFIG_3_fast_read_Fast_Read_Enable 1
-
-/* EBI :: CS_CONFIG_3 :: size_sel [08:08] */
-#define BCHP_EBI_CS_CONFIG_3_size_sel_MASK 0x00000100
-#define BCHP_EBI_CS_CONFIG_3_size_sel_SHIFT 8
-#define BCHP_EBI_CS_CONFIG_3_size_sel_DEFAULT 0x00000000
-
-/* EBI :: CS_CONFIG_3 :: sync [07:07] */
-#define BCHP_EBI_CS_CONFIG_3_sync_MASK 0x00000080
-#define BCHP_EBI_CS_CONFIG_3_sync_SHIFT 7
-#define BCHP_EBI_CS_CONFIG_3_sync_DEFAULT 0x00000000
-
-/* EBI :: CS_CONFIG_3 :: polarity [06:06] */
-#define BCHP_EBI_CS_CONFIG_3_polarity_MASK 0x00000040
-#define BCHP_EBI_CS_CONFIG_3_polarity_SHIFT 6
-#define BCHP_EBI_CS_CONFIG_3_polarity_DEFAULT 0x00000000
-
-/* EBI :: CS_CONFIG_3 :: we_ctl [05:05] */
-#define BCHP_EBI_CS_CONFIG_3_we_ctl_MASK 0x00000020
-#define BCHP_EBI_CS_CONFIG_3_we_ctl_SHIFT 5
-#define BCHP_EBI_CS_CONFIG_3_we_ctl_DEFAULT 0x00000000
-
-/* EBI :: CS_CONFIG_3 :: dest_size [04:04] */
-#define BCHP_EBI_CS_CONFIG_3_dest_size_MASK 0x00000010
-#define BCHP_EBI_CS_CONFIG_3_dest_size_SHIFT 4
-#define BCHP_EBI_CS_CONFIG_3_dest_size_DEFAULT 0x00000000
-
-/* EBI :: CS_CONFIG_3 :: ms_inh [03:03] */
-#define BCHP_EBI_CS_CONFIG_3_ms_inh_MASK 0x00000008
-#define BCHP_EBI_CS_CONFIG_3_ms_inh_SHIFT 3
-#define BCHP_EBI_CS_CONFIG_3_ms_inh_DEFAULT 0x00000000
-
-/* EBI :: CS_CONFIG_3 :: ls_inh [02:02] */
-#define BCHP_EBI_CS_CONFIG_3_ls_inh_MASK 0x00000004
-#define BCHP_EBI_CS_CONFIG_3_ls_inh_SHIFT 2
-#define BCHP_EBI_CS_CONFIG_3_ls_inh_DEFAULT 0x00000000
-
-/* EBI :: CS_CONFIG_3 :: bcachen [01:01] */
-#define BCHP_EBI_CS_CONFIG_3_bcachen_MASK 0x00000002
-#define BCHP_EBI_CS_CONFIG_3_bcachen_SHIFT 1
-#define BCHP_EBI_CS_CONFIG_3_bcachen_DEFAULT 0x00000000
-
-/* EBI :: CS_CONFIG_3 :: enable [00:00] */
-#define BCHP_EBI_CS_CONFIG_3_enable_MASK 0x00000001
-#define BCHP_EBI_CS_CONFIG_3_enable_SHIFT 0
-#define BCHP_EBI_CS_CONFIG_3_enable_DEFAULT 0x00000000
-
-/***************************************************************************
- *CS_BASE_HI_4 - Upper 8-bit of EBI CS Base 4 Register
- ***************************************************************************/
-/* EBI :: CS_BASE_HI_4 :: reserved0 [31:08] */
-#define BCHP_EBI_CS_BASE_HI_4_reserved0_MASK 0xffffff00
-#define BCHP_EBI_CS_BASE_HI_4_reserved0_SHIFT 8
-
-/* EBI :: CS_BASE_HI_4 :: base_addr_hi [07:00] */
-#define BCHP_EBI_CS_BASE_HI_4_base_addr_hi_MASK 0x000000ff
-#define BCHP_EBI_CS_BASE_HI_4_base_addr_hi_SHIFT 0
-#define BCHP_EBI_CS_BASE_HI_4_base_addr_hi_DEFAULT 0x00000000
-
-/***************************************************************************
- *CS_BASE_4 - Lower 32-bit of EBI CS Base 4 Register
- ***************************************************************************/
-/* EBI :: CS_BASE_4 :: base_addr [31:13] */
-#define BCHP_EBI_CS_BASE_4_base_addr_MASK 0xffffe000
-#define BCHP_EBI_CS_BASE_4_base_addr_SHIFT 13
-#define BCHP_EBI_CS_BASE_4_base_addr_DEFAULT 0x00000000
-
-/* EBI :: CS_BASE_4 :: reserved0 [12:04] */
-#define BCHP_EBI_CS_BASE_4_reserved0_MASK 0x00001ff0
-#define BCHP_EBI_CS_BASE_4_reserved0_SHIFT 4
-
-/* EBI :: CS_BASE_4 :: size [03:00] */
-#define BCHP_EBI_CS_BASE_4_size_MASK 0x0000000f
-#define BCHP_EBI_CS_BASE_4_size_SHIFT 0
-#define BCHP_EBI_CS_BASE_4_size_DEFAULT 0x00000000
-#define BCHP_EBI_CS_BASE_4_size_SIZE_8KB 0
-#define BCHP_EBI_CS_BASE_4_size_SIZE_16KB 1
-#define BCHP_EBI_CS_BASE_4_size_SIZE_32KB 2
-#define BCHP_EBI_CS_BASE_4_size_SIZE_64KB 3
-#define BCHP_EBI_CS_BASE_4_size_SIZE_128KB 4
-#define BCHP_EBI_CS_BASE_4_size_SIZE_256KB 5
-#define BCHP_EBI_CS_BASE_4_size_SIZE_512KB 6
-#define BCHP_EBI_CS_BASE_4_size_SIZE_1MB 7
-#define BCHP_EBI_CS_BASE_4_size_SIZE_2MB 8
-#define BCHP_EBI_CS_BASE_4_size_SIZE_4MB 9
-#define BCHP_EBI_CS_BASE_4_size_SIZE_8MB 10
-#define BCHP_EBI_CS_BASE_4_size_SIZE_16MB 11
-#define BCHP_EBI_CS_BASE_4_size_SIZE_32MB 12
-#define BCHP_EBI_CS_BASE_4_size_SIZE_64MB 13
-#define BCHP_EBI_CS_BASE_4_size_SIZE_128MB 14
-#define BCHP_EBI_CS_BASE_4_size_SIZE_256MB 15
-
-/***************************************************************************
- *CS_CONFIG_4 - EBI CS Config 4 Register
- ***************************************************************************/
-/* EBI :: CS_CONFIG_4 :: mem_io [31:31] */
-#define BCHP_EBI_CS_CONFIG_4_mem_io_MASK 0x80000000
-#define BCHP_EBI_CS_CONFIG_4_mem_io_SHIFT 31
-#define BCHP_EBI_CS_CONFIG_4_mem_io_DEFAULT 0x00000000
-
-/* EBI :: CS_CONFIG_4 :: ta_wait [30:30] */
-#define BCHP_EBI_CS_CONFIG_4_ta_wait_MASK 0x40000000
-#define BCHP_EBI_CS_CONFIG_4_ta_wait_SHIFT 30
-#define BCHP_EBI_CS_CONFIG_4_ta_wait_DEFAULT 0x00000000
-
-/* EBI :: CS_CONFIG_4 :: wp [29:29] */
-#define BCHP_EBI_CS_CONFIG_4_wp_MASK 0x20000000
-#define BCHP_EBI_CS_CONFIG_4_wp_SHIFT 29
-#define BCHP_EBI_CS_CONFIG_4_wp_DEFAULT 0x00000000
-
-/* EBI :: CS_CONFIG_4 :: wait_count [28:24] */
-#define BCHP_EBI_CS_CONFIG_4_wait_count_MASK 0x1f000000
-#define BCHP_EBI_CS_CONFIG_4_wait_count_SHIFT 24
-#define BCHP_EBI_CS_CONFIG_4_wait_count_DEFAULT 0x00000007
-
-/* EBI :: CS_CONFIG_4 :: t_hold [23:20] */
-#define BCHP_EBI_CS_CONFIG_4_t_hold_MASK 0x00f00000
-#define BCHP_EBI_CS_CONFIG_4_t_hold_SHIFT 20
-#define BCHP_EBI_CS_CONFIG_4_t_hold_DEFAULT 0x00000000
-
-/* EBI :: CS_CONFIG_4 :: t_setup [19:16] */
-#define BCHP_EBI_CS_CONFIG_4_t_setup_MASK 0x000f0000
-#define BCHP_EBI_CS_CONFIG_4_t_setup_SHIFT 16
-#define BCHP_EBI_CS_CONFIG_4_t_setup_DEFAULT 0x00000000
-
-/* EBI :: CS_CONFIG_4 :: cs_hold [15:15] */
-#define BCHP_EBI_CS_CONFIG_4_cs_hold_MASK 0x00008000
-#define BCHP_EBI_CS_CONFIG_4_cs_hold_SHIFT 15
-#define BCHP_EBI_CS_CONFIG_4_cs_hold_DEFAULT 0x00000000
-
-/* EBI :: CS_CONFIG_4 :: split_cs [14:14] */
-#define BCHP_EBI_CS_CONFIG_4_split_cs_MASK 0x00004000
-#define BCHP_EBI_CS_CONFIG_4_split_cs_SHIFT 14
-#define BCHP_EBI_CS_CONFIG_4_split_cs_DEFAULT 0x00000000
-
-/* EBI :: CS_CONFIG_4 :: mask_en [13:13] */
-#define BCHP_EBI_CS_CONFIG_4_mask_en_MASK 0x00002000
-#define BCHP_EBI_CS_CONFIG_4_mask_en_SHIFT 13
-#define BCHP_EBI_CS_CONFIG_4_mask_en_DEFAULT 0x00000000
-
-/* EBI :: CS_CONFIG_4 :: ne_sample [12:12] */
-#define BCHP_EBI_CS_CONFIG_4_ne_sample_MASK 0x00001000
-#define BCHP_EBI_CS_CONFIG_4_ne_sample_SHIFT 12
-#define BCHP_EBI_CS_CONFIG_4_ne_sample_DEFAULT 0x00000000
-
-/* EBI :: CS_CONFIG_4 :: m68k [11:11] */
-#define BCHP_EBI_CS_CONFIG_4_m68k_MASK 0x00000800
-#define BCHP_EBI_CS_CONFIG_4_m68k_SHIFT 11
-#define BCHP_EBI_CS_CONFIG_4_m68k_DEFAULT 0x00000000
-
-/* EBI :: CS_CONFIG_4 :: le [10:10] */
-#define BCHP_EBI_CS_CONFIG_4_le_MASK 0x00000400
-#define BCHP_EBI_CS_CONFIG_4_le_SHIFT 10
-#define BCHP_EBI_CS_CONFIG_4_le_DEFAULT 0x00000000
-
-/* EBI :: CS_CONFIG_4 :: fast_read [09:09] */
-#define BCHP_EBI_CS_CONFIG_4_fast_read_MASK 0x00000200
-#define BCHP_EBI_CS_CONFIG_4_fast_read_SHIFT 9
-#define BCHP_EBI_CS_CONFIG_4_fast_read_DEFAULT 0x00000000
-#define BCHP_EBI_CS_CONFIG_4_fast_read_Normal 0
-#define BCHP_EBI_CS_CONFIG_4_fast_read_Fast_Read_Enable 1
-
-/* EBI :: CS_CONFIG_4 :: size_sel [08:08] */
-#define BCHP_EBI_CS_CONFIG_4_size_sel_MASK 0x00000100
-#define BCHP_EBI_CS_CONFIG_4_size_sel_SHIFT 8
-#define BCHP_EBI_CS_CONFIG_4_size_sel_DEFAULT 0x00000000
-
-/* EBI :: CS_CONFIG_4 :: sync [07:07] */
-#define BCHP_EBI_CS_CONFIG_4_sync_MASK 0x00000080
-#define BCHP_EBI_CS_CONFIG_4_sync_SHIFT 7
-#define BCHP_EBI_CS_CONFIG_4_sync_DEFAULT 0x00000000
-
-/* EBI :: CS_CONFIG_4 :: polarity [06:06] */
-#define BCHP_EBI_CS_CONFIG_4_polarity_MASK 0x00000040
-#define BCHP_EBI_CS_CONFIG_4_polarity_SHIFT 6
-#define BCHP_EBI_CS_CONFIG_4_polarity_DEFAULT 0x00000000
-
-/* EBI :: CS_CONFIG_4 :: we_ctl [05:05] */
-#define BCHP_EBI_CS_CONFIG_4_we_ctl_MASK 0x00000020
-#define BCHP_EBI_CS_CONFIG_4_we_ctl_SHIFT 5
-#define BCHP_EBI_CS_CONFIG_4_we_ctl_DEFAULT 0x00000000
-
-/* EBI :: CS_CONFIG_4 :: dest_size [04:04] */
-#define BCHP_EBI_CS_CONFIG_4_dest_size_MASK 0x00000010
-#define BCHP_EBI_CS_CONFIG_4_dest_size_SHIFT 4
-#define BCHP_EBI_CS_CONFIG_4_dest_size_DEFAULT 0x00000000
-
-/* EBI :: CS_CONFIG_4 :: ms_inh [03:03] */
-#define BCHP_EBI_CS_CONFIG_4_ms_inh_MASK 0x00000008
-#define BCHP_EBI_CS_CONFIG_4_ms_inh_SHIFT 3
-#define BCHP_EBI_CS_CONFIG_4_ms_inh_DEFAULT 0x00000000
-
-/* EBI :: CS_CONFIG_4 :: ls_inh [02:02] */
-#define BCHP_EBI_CS_CONFIG_4_ls_inh_MASK 0x00000004
-#define BCHP_EBI_CS_CONFIG_4_ls_inh_SHIFT 2
-#define BCHP_EBI_CS_CONFIG_4_ls_inh_DEFAULT 0x00000000
-
-/* EBI :: CS_CONFIG_4 :: bcachen [01:01] */
-#define BCHP_EBI_CS_CONFIG_4_bcachen_MASK 0x00000002
-#define BCHP_EBI_CS_CONFIG_4_bcachen_SHIFT 1
-#define BCHP_EBI_CS_CONFIG_4_bcachen_DEFAULT 0x00000000
-
-/* EBI :: CS_CONFIG_4 :: enable [00:00] */
-#define BCHP_EBI_CS_CONFIG_4_enable_MASK 0x00000001
-#define BCHP_EBI_CS_CONFIG_4_enable_SHIFT 0
-#define BCHP_EBI_CS_CONFIG_4_enable_DEFAULT 0x00000000
-
-/***************************************************************************
- *CS_BASE_HI_5 - Upper 8-bit of EBI CS Base 5 Register
- ***************************************************************************/
-/* EBI :: CS_BASE_HI_5 :: reserved0 [31:08] */
-#define BCHP_EBI_CS_BASE_HI_5_reserved0_MASK 0xffffff00
-#define BCHP_EBI_CS_BASE_HI_5_reserved0_SHIFT 8
-
-/* EBI :: CS_BASE_HI_5 :: base_addr_hi [07:00] */
-#define BCHP_EBI_CS_BASE_HI_5_base_addr_hi_MASK 0x000000ff
-#define BCHP_EBI_CS_BASE_HI_5_base_addr_hi_SHIFT 0
-#define BCHP_EBI_CS_BASE_HI_5_base_addr_hi_DEFAULT 0x00000000
-
-/***************************************************************************
- *CS_BASE_5 - Lower 32-bit of EBI CS Base 5 Register
- ***************************************************************************/
-/* EBI :: CS_BASE_5 :: base_addr [31:13] */
-#define BCHP_EBI_CS_BASE_5_base_addr_MASK 0xffffe000
-#define BCHP_EBI_CS_BASE_5_base_addr_SHIFT 13
-#define BCHP_EBI_CS_BASE_5_base_addr_DEFAULT 0x00000000
-
-/* EBI :: CS_BASE_5 :: reserved0 [12:04] */
-#define BCHP_EBI_CS_BASE_5_reserved0_MASK 0x00001ff0
-#define BCHP_EBI_CS_BASE_5_reserved0_SHIFT 4
-
-/* EBI :: CS_BASE_5 :: size [03:00] */
-#define BCHP_EBI_CS_BASE_5_size_MASK 0x0000000f
-#define BCHP_EBI_CS_BASE_5_size_SHIFT 0
-#define BCHP_EBI_CS_BASE_5_size_DEFAULT 0x00000000
-#define BCHP_EBI_CS_BASE_5_size_SIZE_8KB 0
-#define BCHP_EBI_CS_BASE_5_size_SIZE_16KB 1
-#define BCHP_EBI_CS_BASE_5_size_SIZE_32KB 2
-#define BCHP_EBI_CS_BASE_5_size_SIZE_64KB 3
-#define BCHP_EBI_CS_BASE_5_size_SIZE_128KB 4
-#define BCHP_EBI_CS_BASE_5_size_SIZE_256KB 5
-#define BCHP_EBI_CS_BASE_5_size_SIZE_512KB 6
-#define BCHP_EBI_CS_BASE_5_size_SIZE_1MB 7
-#define BCHP_EBI_CS_BASE_5_size_SIZE_2MB 8
-#define BCHP_EBI_CS_BASE_5_size_SIZE_4MB 9
-#define BCHP_EBI_CS_BASE_5_size_SIZE_8MB 10
-#define BCHP_EBI_CS_BASE_5_size_SIZE_16MB 11
-#define BCHP_EBI_CS_BASE_5_size_SIZE_32MB 12
-#define BCHP_EBI_CS_BASE_5_size_SIZE_64MB 13
-#define BCHP_EBI_CS_BASE_5_size_SIZE_128MB 14
-#define BCHP_EBI_CS_BASE_5_size_SIZE_256MB 15
-
-/***************************************************************************
- *CS_CONFIG_5 - EBI CS Config 5 Register
- ***************************************************************************/
-/* EBI :: CS_CONFIG_5 :: mem_io [31:31] */
-#define BCHP_EBI_CS_CONFIG_5_mem_io_MASK 0x80000000
-#define BCHP_EBI_CS_CONFIG_5_mem_io_SHIFT 31
-#define BCHP_EBI_CS_CONFIG_5_mem_io_DEFAULT 0x00000000
-
-/* EBI :: CS_CONFIG_5 :: ta_wait [30:30] */
-#define BCHP_EBI_CS_CONFIG_5_ta_wait_MASK 0x40000000
-#define BCHP_EBI_CS_CONFIG_5_ta_wait_SHIFT 30
-#define BCHP_EBI_CS_CONFIG_5_ta_wait_DEFAULT 0x00000000
-
-/* EBI :: CS_CONFIG_5 :: wp [29:29] */
-#define BCHP_EBI_CS_CONFIG_5_wp_MASK 0x20000000
-#define BCHP_EBI_CS_CONFIG_5_wp_SHIFT 29
-#define BCHP_EBI_CS_CONFIG_5_wp_DEFAULT 0x00000000
-
-/* EBI :: CS_CONFIG_5 :: wait_count [28:24] */
-#define BCHP_EBI_CS_CONFIG_5_wait_count_MASK 0x1f000000
-#define BCHP_EBI_CS_CONFIG_5_wait_count_SHIFT 24
-#define BCHP_EBI_CS_CONFIG_5_wait_count_DEFAULT 0x00000007
-
-/* EBI :: CS_CONFIG_5 :: t_hold [23:20] */
-#define BCHP_EBI_CS_CONFIG_5_t_hold_MASK 0x00f00000
-#define BCHP_EBI_CS_CONFIG_5_t_hold_SHIFT 20
-#define BCHP_EBI_CS_CONFIG_5_t_hold_DEFAULT 0x00000000
-
-/* EBI :: CS_CONFIG_5 :: t_setup [19:16] */
-#define BCHP_EBI_CS_CONFIG_5_t_setup_MASK 0x000f0000
-#define BCHP_EBI_CS_CONFIG_5_t_setup_SHIFT 16
-#define BCHP_EBI_CS_CONFIG_5_t_setup_DEFAULT 0x00000000
-
-/* EBI :: CS_CONFIG_5 :: cs_hold [15:15] */
-#define BCHP_EBI_CS_CONFIG_5_cs_hold_MASK 0x00008000
-#define BCHP_EBI_CS_CONFIG_5_cs_hold_SHIFT 15
-#define BCHP_EBI_CS_CONFIG_5_cs_hold_DEFAULT 0x00000000
-
-/* EBI :: CS_CONFIG_5 :: split_cs [14:14] */
-#define BCHP_EBI_CS_CONFIG_5_split_cs_MASK 0x00004000
-#define BCHP_EBI_CS_CONFIG_5_split_cs_SHIFT 14
-#define BCHP_EBI_CS_CONFIG_5_split_cs_DEFAULT 0x00000000
-
-/* EBI :: CS_CONFIG_5 :: mask_en [13:13] */
-#define BCHP_EBI_CS_CONFIG_5_mask_en_MASK 0x00002000
-#define BCHP_EBI_CS_CONFIG_5_mask_en_SHIFT 13
-#define BCHP_EBI_CS_CONFIG_5_mask_en_DEFAULT 0x00000000
-
-/* EBI :: CS_CONFIG_5 :: ne_sample [12:12] */
-#define BCHP_EBI_CS_CONFIG_5_ne_sample_MASK 0x00001000
-#define BCHP_EBI_CS_CONFIG_5_ne_sample_SHIFT 12
-#define BCHP_EBI_CS_CONFIG_5_ne_sample_DEFAULT 0x00000000
-
-/* EBI :: CS_CONFIG_5 :: m68k [11:11] */
-#define BCHP_EBI_CS_CONFIG_5_m68k_MASK 0x00000800
-#define BCHP_EBI_CS_CONFIG_5_m68k_SHIFT 11
-#define BCHP_EBI_CS_CONFIG_5_m68k_DEFAULT 0x00000000
-
-/* EBI :: CS_CONFIG_5 :: le [10:10] */
-#define BCHP_EBI_CS_CONFIG_5_le_MASK 0x00000400
-#define BCHP_EBI_CS_CONFIG_5_le_SHIFT 10
-#define BCHP_EBI_CS_CONFIG_5_le_DEFAULT 0x00000000
-
-/* EBI :: CS_CONFIG_5 :: fast_read [09:09] */
-#define BCHP_EBI_CS_CONFIG_5_fast_read_MASK 0x00000200
-#define BCHP_EBI_CS_CONFIG_5_fast_read_SHIFT 9
-#define BCHP_EBI_CS_CONFIG_5_fast_read_DEFAULT 0x00000000
-#define BCHP_EBI_CS_CONFIG_5_fast_read_Normal 0
-#define BCHP_EBI_CS_CONFIG_5_fast_read_Fast_Read_Enable 1
-
-/* EBI :: CS_CONFIG_5 :: size_sel [08:08] */
-#define BCHP_EBI_CS_CONFIG_5_size_sel_MASK 0x00000100
-#define BCHP_EBI_CS_CONFIG_5_size_sel_SHIFT 8
-#define BCHP_EBI_CS_CONFIG_5_size_sel_DEFAULT 0x00000000
-
-/* EBI :: CS_CONFIG_5 :: sync [07:07] */
-#define BCHP_EBI_CS_CONFIG_5_sync_MASK 0x00000080
-#define BCHP_EBI_CS_CONFIG_5_sync_SHIFT 7
-#define BCHP_EBI_CS_CONFIG_5_sync_DEFAULT 0x00000000
-
-/* EBI :: CS_CONFIG_5 :: polarity [06:06] */
-#define BCHP_EBI_CS_CONFIG_5_polarity_MASK 0x00000040
-#define BCHP_EBI_CS_CONFIG_5_polarity_SHIFT 6
-#define BCHP_EBI_CS_CONFIG_5_polarity_DEFAULT 0x00000000
-
-/* EBI :: CS_CONFIG_5 :: we_ctl [05:05] */
-#define BCHP_EBI_CS_CONFIG_5_we_ctl_MASK 0x00000020
-#define BCHP_EBI_CS_CONFIG_5_we_ctl_SHIFT 5
-#define BCHP_EBI_CS_CONFIG_5_we_ctl_DEFAULT 0x00000000
-
-/* EBI :: CS_CONFIG_5 :: dest_size [04:04] */
-#define BCHP_EBI_CS_CONFIG_5_dest_size_MASK 0x00000010
-#define BCHP_EBI_CS_CONFIG_5_dest_size_SHIFT 4
-#define BCHP_EBI_CS_CONFIG_5_dest_size_DEFAULT 0x00000000
-
-/* EBI :: CS_CONFIG_5 :: ms_inh [03:03] */
-#define BCHP_EBI_CS_CONFIG_5_ms_inh_MASK 0x00000008
-#define BCHP_EBI_CS_CONFIG_5_ms_inh_SHIFT 3
-#define BCHP_EBI_CS_CONFIG_5_ms_inh_DEFAULT 0x00000000
-
-/* EBI :: CS_CONFIG_5 :: ls_inh [02:02] */
-#define BCHP_EBI_CS_CONFIG_5_ls_inh_MASK 0x00000004
-#define BCHP_EBI_CS_CONFIG_5_ls_inh_SHIFT 2
-#define BCHP_EBI_CS_CONFIG_5_ls_inh_DEFAULT 0x00000000
-
-/* EBI :: CS_CONFIG_5 :: bcachen [01:01] */
-#define BCHP_EBI_CS_CONFIG_5_bcachen_MASK 0x00000002
-#define BCHP_EBI_CS_CONFIG_5_bcachen_SHIFT 1
-#define BCHP_EBI_CS_CONFIG_5_bcachen_DEFAULT 0x00000000
-
-/* EBI :: CS_CONFIG_5 :: enable [00:00] */
-#define BCHP_EBI_CS_CONFIG_5_enable_MASK 0x00000001
-#define BCHP_EBI_CS_CONFIG_5_enable_SHIFT 0
-#define BCHP_EBI_CS_CONFIG_5_enable_DEFAULT 0x00000000
-
-/***************************************************************************
- *CS_BASE_HI_6 - Upper 8-bit of EBI CS Base 6 Register
- ***************************************************************************/
-/* EBI :: CS_BASE_HI_6 :: reserved0 [31:08] */
-#define BCHP_EBI_CS_BASE_HI_6_reserved0_MASK 0xffffff00
-#define BCHP_EBI_CS_BASE_HI_6_reserved0_SHIFT 8
-
-/* EBI :: CS_BASE_HI_6 :: base_addr_hi [07:00] */
-#define BCHP_EBI_CS_BASE_HI_6_base_addr_hi_MASK 0x000000ff
-#define BCHP_EBI_CS_BASE_HI_6_base_addr_hi_SHIFT 0
-#define BCHP_EBI_CS_BASE_HI_6_base_addr_hi_DEFAULT 0x00000000
-
-/***************************************************************************
- *CS_BASE_6 - Lower 32-bit of EBI CS Base 6 Register
- ***************************************************************************/
-/* EBI :: CS_BASE_6 :: base_addr [31:13] */
-#define BCHP_EBI_CS_BASE_6_base_addr_MASK 0xffffe000
-#define BCHP_EBI_CS_BASE_6_base_addr_SHIFT 13
-#define BCHP_EBI_CS_BASE_6_base_addr_DEFAULT 0x00000000
-
-/* EBI :: CS_BASE_6 :: reserved0 [12:04] */
-#define BCHP_EBI_CS_BASE_6_reserved0_MASK 0x00001ff0
-#define BCHP_EBI_CS_BASE_6_reserved0_SHIFT 4
-
-/* EBI :: CS_BASE_6 :: size [03:00] */
-#define BCHP_EBI_CS_BASE_6_size_MASK 0x0000000f
-#define BCHP_EBI_CS_BASE_6_size_SHIFT 0
-#define BCHP_EBI_CS_BASE_6_size_DEFAULT 0x00000000
-#define BCHP_EBI_CS_BASE_6_size_SIZE_8KB 0
-#define BCHP_EBI_CS_BASE_6_size_SIZE_16KB 1
-#define BCHP_EBI_CS_BASE_6_size_SIZE_32KB 2
-#define BCHP_EBI_CS_BASE_6_size_SIZE_64KB 3
-#define BCHP_EBI_CS_BASE_6_size_SIZE_128KB 4
-#define BCHP_EBI_CS_BASE_6_size_SIZE_256KB 5
-#define BCHP_EBI_CS_BASE_6_size_SIZE_512KB 6
-#define BCHP_EBI_CS_BASE_6_size_SIZE_1MB 7
-#define BCHP_EBI_CS_BASE_6_size_SIZE_2MB 8
-#define BCHP_EBI_CS_BASE_6_size_SIZE_4MB 9
-#define BCHP_EBI_CS_BASE_6_size_SIZE_8MB 10
-#define BCHP_EBI_CS_BASE_6_size_SIZE_16MB 11
-#define BCHP_EBI_CS_BASE_6_size_SIZE_32MB 12
-#define BCHP_EBI_CS_BASE_6_size_SIZE_64MB 13
-#define BCHP_EBI_CS_BASE_6_size_SIZE_128MB 14
-#define BCHP_EBI_CS_BASE_6_size_SIZE_256MB 15
-
-/***************************************************************************
- *CS_CONFIG_6 - EBI CS Config 6 Register
- ***************************************************************************/
-/* EBI :: CS_CONFIG_6 :: mem_io [31:31] */
-#define BCHP_EBI_CS_CONFIG_6_mem_io_MASK 0x80000000
-#define BCHP_EBI_CS_CONFIG_6_mem_io_SHIFT 31
-#define BCHP_EBI_CS_CONFIG_6_mem_io_DEFAULT 0x00000000
-
-/* EBI :: CS_CONFIG_6 :: ta_wait [30:30] */
-#define BCHP_EBI_CS_CONFIG_6_ta_wait_MASK 0x40000000
-#define BCHP_EBI_CS_CONFIG_6_ta_wait_SHIFT 30
-#define BCHP_EBI_CS_CONFIG_6_ta_wait_DEFAULT 0x00000000
-
-/* EBI :: CS_CONFIG_6 :: wp [29:29] */
-#define BCHP_EBI_CS_CONFIG_6_wp_MASK 0x20000000
-#define BCHP_EBI_CS_CONFIG_6_wp_SHIFT 29
-#define BCHP_EBI_CS_CONFIG_6_wp_DEFAULT 0x00000000
-
-/* EBI :: CS_CONFIG_6 :: wait_count [28:24] */
-#define BCHP_EBI_CS_CONFIG_6_wait_count_MASK 0x1f000000
-#define BCHP_EBI_CS_CONFIG_6_wait_count_SHIFT 24
-#define BCHP_EBI_CS_CONFIG_6_wait_count_DEFAULT 0x00000007
-
-/* EBI :: CS_CONFIG_6 :: t_hold [23:20] */
-#define BCHP_EBI_CS_CONFIG_6_t_hold_MASK 0x00f00000
-#define BCHP_EBI_CS_CONFIG_6_t_hold_SHIFT 20
-#define BCHP_EBI_CS_CONFIG_6_t_hold_DEFAULT 0x00000000
-
-/* EBI :: CS_CONFIG_6 :: t_setup [19:16] */
-#define BCHP_EBI_CS_CONFIG_6_t_setup_MASK 0x000f0000
-#define BCHP_EBI_CS_CONFIG_6_t_setup_SHIFT 16
-#define BCHP_EBI_CS_CONFIG_6_t_setup_DEFAULT 0x00000000
-
-/* EBI :: CS_CONFIG_6 :: cs_hold [15:15] */
-#define BCHP_EBI_CS_CONFIG_6_cs_hold_MASK 0x00008000
-#define BCHP_EBI_CS_CONFIG_6_cs_hold_SHIFT 15
-#define BCHP_EBI_CS_CONFIG_6_cs_hold_DEFAULT 0x00000000
-
-/* EBI :: CS_CONFIG_6 :: split_cs [14:14] */
-#define BCHP_EBI_CS_CONFIG_6_split_cs_MASK 0x00004000
-#define BCHP_EBI_CS_CONFIG_6_split_cs_SHIFT 14
-#define BCHP_EBI_CS_CONFIG_6_split_cs_DEFAULT 0x00000000
-
-/* EBI :: CS_CONFIG_6 :: mask_en [13:13] */
-#define BCHP_EBI_CS_CONFIG_6_mask_en_MASK 0x00002000
-#define BCHP_EBI_CS_CONFIG_6_mask_en_SHIFT 13
-#define BCHP_EBI_CS_CONFIG_6_mask_en_DEFAULT 0x00000000
-
-/* EBI :: CS_CONFIG_6 :: ne_sample [12:12] */
-#define BCHP_EBI_CS_CONFIG_6_ne_sample_MASK 0x00001000
-#define BCHP_EBI_CS_CONFIG_6_ne_sample_SHIFT 12
-#define BCHP_EBI_CS_CONFIG_6_ne_sample_DEFAULT 0x00000000
-
-/* EBI :: CS_CONFIG_6 :: m68k [11:11] */
-#define BCHP_EBI_CS_CONFIG_6_m68k_MASK 0x00000800
-#define BCHP_EBI_CS_CONFIG_6_m68k_SHIFT 11
-#define BCHP_EBI_CS_CONFIG_6_m68k_DEFAULT 0x00000000
-
-/* EBI :: CS_CONFIG_6 :: le [10:10] */
-#define BCHP_EBI_CS_CONFIG_6_le_MASK 0x00000400
-#define BCHP_EBI_CS_CONFIG_6_le_SHIFT 10
-#define BCHP_EBI_CS_CONFIG_6_le_DEFAULT 0x00000000
-
-/* EBI :: CS_CONFIG_6 :: fast_read [09:09] */
-#define BCHP_EBI_CS_CONFIG_6_fast_read_MASK 0x00000200
-#define BCHP_EBI_CS_CONFIG_6_fast_read_SHIFT 9
-#define BCHP_EBI_CS_CONFIG_6_fast_read_DEFAULT 0x00000000
-#define BCHP_EBI_CS_CONFIG_6_fast_read_Normal 0
-#define BCHP_EBI_CS_CONFIG_6_fast_read_Fast_Read_Enable 1
-
-/* EBI :: CS_CONFIG_6 :: size_sel [08:08] */
-#define BCHP_EBI_CS_CONFIG_6_size_sel_MASK 0x00000100
-#define BCHP_EBI_CS_CONFIG_6_size_sel_SHIFT 8
-#define BCHP_EBI_CS_CONFIG_6_size_sel_DEFAULT 0x00000000
-
-/* EBI :: CS_CONFIG_6 :: sync [07:07] */
-#define BCHP_EBI_CS_CONFIG_6_sync_MASK 0x00000080
-#define BCHP_EBI_CS_CONFIG_6_sync_SHIFT 7
-#define BCHP_EBI_CS_CONFIG_6_sync_DEFAULT 0x00000000
-
-/* EBI :: CS_CONFIG_6 :: polarity [06:06] */
-#define BCHP_EBI_CS_CONFIG_6_polarity_MASK 0x00000040
-#define BCHP_EBI_CS_CONFIG_6_polarity_SHIFT 6
-#define BCHP_EBI_CS_CONFIG_6_polarity_DEFAULT 0x00000000
-
-/* EBI :: CS_CONFIG_6 :: we_ctl [05:05] */
-#define BCHP_EBI_CS_CONFIG_6_we_ctl_MASK 0x00000020
-#define BCHP_EBI_CS_CONFIG_6_we_ctl_SHIFT 5
-#define BCHP_EBI_CS_CONFIG_6_we_ctl_DEFAULT 0x00000000
-
-/* EBI :: CS_CONFIG_6 :: dest_size [04:04] */
-#define BCHP_EBI_CS_CONFIG_6_dest_size_MASK 0x00000010
-#define BCHP_EBI_CS_CONFIG_6_dest_size_SHIFT 4
-#define BCHP_EBI_CS_CONFIG_6_dest_size_DEFAULT 0x00000000
-
-/* EBI :: CS_CONFIG_6 :: ms_inh [03:03] */
-#define BCHP_EBI_CS_CONFIG_6_ms_inh_MASK 0x00000008
-#define BCHP_EBI_CS_CONFIG_6_ms_inh_SHIFT 3
-#define BCHP_EBI_CS_CONFIG_6_ms_inh_DEFAULT 0x00000000
-
-/* EBI :: CS_CONFIG_6 :: ls_inh [02:02] */
-#define BCHP_EBI_CS_CONFIG_6_ls_inh_MASK 0x00000004
-#define BCHP_EBI_CS_CONFIG_6_ls_inh_SHIFT 2
-#define BCHP_EBI_CS_CONFIG_6_ls_inh_DEFAULT 0x00000000
-
-/* EBI :: CS_CONFIG_6 :: bcachen [01:01] */
-#define BCHP_EBI_CS_CONFIG_6_bcachen_MASK 0x00000002
-#define BCHP_EBI_CS_CONFIG_6_bcachen_SHIFT 1
-#define BCHP_EBI_CS_CONFIG_6_bcachen_DEFAULT 0x00000000
-
-/* EBI :: CS_CONFIG_6 :: enable [00:00] */
-#define BCHP_EBI_CS_CONFIG_6_enable_MASK 0x00000001
-#define BCHP_EBI_CS_CONFIG_6_enable_SHIFT 0
-#define BCHP_EBI_CS_CONFIG_6_enable_DEFAULT 0x00000000
-
-/***************************************************************************
- *BURST_CFG_0 - EBI Synchronous Intel StrataFlash Burst Configure Register
- ***************************************************************************/
-/* EBI :: BURST_CFG_0 :: prefetch_enable [31:31] */
-#define BCHP_EBI_BURST_CFG_0_prefetch_enable_MASK 0x80000000
-#define BCHP_EBI_BURST_CFG_0_prefetch_enable_SHIFT 31
-#define BCHP_EBI_BURST_CFG_0_prefetch_enable_DEFAULT 0x00000000
-
-/* EBI :: BURST_CFG_0 :: page_enable [30:30] */
-#define BCHP_EBI_BURST_CFG_0_page_enable_MASK 0x40000000
-#define BCHP_EBI_BURST_CFG_0_page_enable_SHIFT 30
-#define BCHP_EBI_BURST_CFG_0_page_enable_DEFAULT 0x00000000
-
-/* EBI :: BURST_CFG_0 :: pfetch_abort_enable [29:29] */
-#define BCHP_EBI_BURST_CFG_0_pfetch_abort_enable_MASK 0x20000000
-#define BCHP_EBI_BURST_CFG_0_pfetch_abort_enable_SHIFT 29
-#define BCHP_EBI_BURST_CFG_0_pfetch_abort_enable_DEFAULT 0x00000000
-
-/* EBI :: BURST_CFG_0 :: page_latch_enable [28:28] */
-#define BCHP_EBI_BURST_CFG_0_page_latch_enable_MASK 0x10000000
-#define BCHP_EBI_BURST_CFG_0_page_latch_enable_SHIFT 28
-#define BCHP_EBI_BURST_CFG_0_page_latch_enable_DEFAULT 0x00000000
-
-/* EBI :: BURST_CFG_0 :: pfetch_wrap_enable [27:27] */
-#define BCHP_EBI_BURST_CFG_0_pfetch_wrap_enable_MASK 0x08000000
-#define BCHP_EBI_BURST_CFG_0_pfetch_wrap_enable_SHIFT 27
-#define BCHP_EBI_BURST_CFG_0_pfetch_wrap_enable_DEFAULT 0x00000000
-
-/* EBI :: BURST_CFG_0 :: reserved0 [26:24] */
-#define BCHP_EBI_BURST_CFG_0_reserved0_MASK 0x07000000
-#define BCHP_EBI_BURST_CFG_0_reserved0_SHIFT 24
-
-/* EBI :: BURST_CFG_0 :: prefetch_size [23:22] */
-#define BCHP_EBI_BURST_CFG_0_prefetch_size_MASK 0x00c00000
-#define BCHP_EBI_BURST_CFG_0_prefetch_size_SHIFT 22
-#define BCHP_EBI_BURST_CFG_0_prefetch_size_DEFAULT 0x00000000
-#define BCHP_EBI_BURST_CFG_0_prefetch_size_SIZE_4_BYTES 0
-#define BCHP_EBI_BURST_CFG_0_prefetch_size_SIZE_8_BYTES 1
-#define BCHP_EBI_BURST_CFG_0_prefetch_size_SIZE_16_BYTES 2
-#define BCHP_EBI_BURST_CFG_0_prefetch_size_SIZE_32_BYTES 3
-
-/* EBI :: BURST_CFG_0 :: page_size [21:20] */
-#define BCHP_EBI_BURST_CFG_0_page_size_MASK 0x00300000
-#define BCHP_EBI_BURST_CFG_0_page_size_SHIFT 20
-#define BCHP_EBI_BURST_CFG_0_page_size_DEFAULT 0x00000000
-#define BCHP_EBI_BURST_CFG_0_page_size_SIZE_4_BYTES 0
-#define BCHP_EBI_BURST_CFG_0_page_size_SIZE_8_BYTES 1
-#define BCHP_EBI_BURST_CFG_0_page_size_SIZE_16_BYTES 2
-#define BCHP_EBI_BURST_CFG_0_page_size_SIZE_32_BYTES 3
-
-/* EBI :: BURST_CFG_0 :: page_wait_count [19:16] */
-#define BCHP_EBI_BURST_CFG_0_page_wait_count_MASK 0x000f0000
-#define BCHP_EBI_BURST_CFG_0_page_wait_count_SHIFT 16
-#define BCHP_EBI_BURST_CFG_0_page_wait_count_DEFAULT 0x00000001
-
-/* EBI :: BURST_CFG_0 :: burst_cyc_disable [15:15] */
-#define BCHP_EBI_BURST_CFG_0_burst_cyc_disable_MASK 0x00008000
-#define BCHP_EBI_BURST_CFG_0_burst_cyc_disable_SHIFT 15
-#define BCHP_EBI_BURST_CFG_0_burst_cyc_disable_DEFAULT 0x00000001
-
-/* EBI :: BURST_CFG_0 :: reserved1 [14:08] */
-#define BCHP_EBI_BURST_CFG_0_reserved1_MASK 0x00007f00
-#define BCHP_EBI_BURST_CFG_0_reserved1_SHIFT 8
-
-/* EBI :: BURST_CFG_0 :: burst_latency [07:04] */
-#define BCHP_EBI_BURST_CFG_0_burst_latency_MASK 0x000000f0
-#define BCHP_EBI_BURST_CFG_0_burst_latency_SHIFT 4
-#define BCHP_EBI_BURST_CFG_0_burst_latency_DEFAULT 0x00000000
-
-/* EBI :: BURST_CFG_0 :: reserved2 [03:02] */
-#define BCHP_EBI_BURST_CFG_0_reserved2_MASK 0x0000000c
-#define BCHP_EBI_BURST_CFG_0_reserved2_SHIFT 2
-
-/* EBI :: BURST_CFG_0 :: data_hold [01:01] */
-#define BCHP_EBI_BURST_CFG_0_data_hold_MASK 0x00000002
-#define BCHP_EBI_BURST_CFG_0_data_hold_SHIFT 1
-#define BCHP_EBI_BURST_CFG_0_data_hold_DEFAULT 0x00000000
-
-/* EBI :: BURST_CFG_0 :: burst_16 [00:00] */
-#define BCHP_EBI_BURST_CFG_0_burst_16_MASK 0x00000001
-#define BCHP_EBI_BURST_CFG_0_burst_16_SHIFT 0
-#define BCHP_EBI_BURST_CFG_0_burst_16_DEFAULT 0x00000000
-
-/***************************************************************************
- *BURST_CFG_1 - EBI Synchronous Intel StrataFlash Burst Configure Register
- ***************************************************************************/
-/* EBI :: BURST_CFG_1 :: prefetch_enable [31:31] */
-#define BCHP_EBI_BURST_CFG_1_prefetch_enable_MASK 0x80000000
-#define BCHP_EBI_BURST_CFG_1_prefetch_enable_SHIFT 31
-#define BCHP_EBI_BURST_CFG_1_prefetch_enable_DEFAULT 0x00000000
-
-/* EBI :: BURST_CFG_1 :: page_enable [30:30] */
-#define BCHP_EBI_BURST_CFG_1_page_enable_MASK 0x40000000
-#define BCHP_EBI_BURST_CFG_1_page_enable_SHIFT 30
-#define BCHP_EBI_BURST_CFG_1_page_enable_DEFAULT 0x00000000
-
-/* EBI :: BURST_CFG_1 :: pfetch_abort_enable [29:29] */
-#define BCHP_EBI_BURST_CFG_1_pfetch_abort_enable_MASK 0x20000000
-#define BCHP_EBI_BURST_CFG_1_pfetch_abort_enable_SHIFT 29
-#define BCHP_EBI_BURST_CFG_1_pfetch_abort_enable_DEFAULT 0x00000000
-
-/* EBI :: BURST_CFG_1 :: page_latch_enable [28:28] */
-#define BCHP_EBI_BURST_CFG_1_page_latch_enable_MASK 0x10000000
-#define BCHP_EBI_BURST_CFG_1_page_latch_enable_SHIFT 28
-#define BCHP_EBI_BURST_CFG_1_page_latch_enable_DEFAULT 0x00000000
-
-/* EBI :: BURST_CFG_1 :: pfetch_wrap_enable [27:27] */
-#define BCHP_EBI_BURST_CFG_1_pfetch_wrap_enable_MASK 0x08000000
-#define BCHP_EBI_BURST_CFG_1_pfetch_wrap_enable_SHIFT 27
-#define BCHP_EBI_BURST_CFG_1_pfetch_wrap_enable_DEFAULT 0x00000000
-
-/* EBI :: BURST_CFG_1 :: reserved0 [26:24] */
-#define BCHP_EBI_BURST_CFG_1_reserved0_MASK 0x07000000
-#define BCHP_EBI_BURST_CFG_1_reserved0_SHIFT 24
-
-/* EBI :: BURST_CFG_1 :: prefetch_size [23:22] */
-#define BCHP_EBI_BURST_CFG_1_prefetch_size_MASK 0x00c00000
-#define BCHP_EBI_BURST_CFG_1_prefetch_size_SHIFT 22
-#define BCHP_EBI_BURST_CFG_1_prefetch_size_DEFAULT 0x00000000
-#define BCHP_EBI_BURST_CFG_1_prefetch_size_SIZE_4_BYTES 0
-#define BCHP_EBI_BURST_CFG_1_prefetch_size_SIZE_8_BYTES 1
-#define BCHP_EBI_BURST_CFG_1_prefetch_size_SIZE_16_BYTES 2
-#define BCHP_EBI_BURST_CFG_1_prefetch_size_SIZE_32_BYTES 3
-
-/* EBI :: BURST_CFG_1 :: page_size [21:20] */
-#define BCHP_EBI_BURST_CFG_1_page_size_MASK 0x00300000
-#define BCHP_EBI_BURST_CFG_1_page_size_SHIFT 20
-#define BCHP_EBI_BURST_CFG_1_page_size_DEFAULT 0x00000000
-#define BCHP_EBI_BURST_CFG_1_page_size_SIZE_4_BYTES 0
-#define BCHP_EBI_BURST_CFG_1_page_size_SIZE_8_BYTES 1
-#define BCHP_EBI_BURST_CFG_1_page_size_SIZE_16_BYTES 2
-#define BCHP_EBI_BURST_CFG_1_page_size_SIZE_32_BYTES 3
-
-/* EBI :: BURST_CFG_1 :: page_wait_count [19:16] */
-#define BCHP_EBI_BURST_CFG_1_page_wait_count_MASK 0x000f0000
-#define BCHP_EBI_BURST_CFG_1_page_wait_count_SHIFT 16
-#define BCHP_EBI_BURST_CFG_1_page_wait_count_DEFAULT 0x00000001
-
-/* EBI :: BURST_CFG_1 :: burst_cyc_disable [15:15] */
-#define BCHP_EBI_BURST_CFG_1_burst_cyc_disable_MASK 0x00008000
-#define BCHP_EBI_BURST_CFG_1_burst_cyc_disable_SHIFT 15
-#define BCHP_EBI_BURST_CFG_1_burst_cyc_disable_DEFAULT 0x00000001
-
-/* EBI :: BURST_CFG_1 :: reserved1 [14:08] */
-#define BCHP_EBI_BURST_CFG_1_reserved1_MASK 0x00007f00
-#define BCHP_EBI_BURST_CFG_1_reserved1_SHIFT 8
-
-/* EBI :: BURST_CFG_1 :: burst_latency [07:04] */
-#define BCHP_EBI_BURST_CFG_1_burst_latency_MASK 0x000000f0
-#define BCHP_EBI_BURST_CFG_1_burst_latency_SHIFT 4
-#define BCHP_EBI_BURST_CFG_1_burst_latency_DEFAULT 0x00000000
-
-/* EBI :: BURST_CFG_1 :: reserved2 [03:02] */
-#define BCHP_EBI_BURST_CFG_1_reserved2_MASK 0x0000000c
-#define BCHP_EBI_BURST_CFG_1_reserved2_SHIFT 2
-
-/* EBI :: BURST_CFG_1 :: data_hold [01:01] */
-#define BCHP_EBI_BURST_CFG_1_data_hold_MASK 0x00000002
-#define BCHP_EBI_BURST_CFG_1_data_hold_SHIFT 1
-#define BCHP_EBI_BURST_CFG_1_data_hold_DEFAULT 0x00000000
-
-/* EBI :: BURST_CFG_1 :: burst_16 [00:00] */
-#define BCHP_EBI_BURST_CFG_1_burst_16_MASK 0x00000001
-#define BCHP_EBI_BURST_CFG_1_burst_16_SHIFT 0
-#define BCHP_EBI_BURST_CFG_1_burst_16_DEFAULT 0x00000000
-
-/***************************************************************************
- *BURST_CFG_2 - EBI Synchronous Intel StrataFlash Burst Configure Register
- ***************************************************************************/
-/* EBI :: BURST_CFG_2 :: prefetch_enable [31:31] */
-#define BCHP_EBI_BURST_CFG_2_prefetch_enable_MASK 0x80000000
-#define BCHP_EBI_BURST_CFG_2_prefetch_enable_SHIFT 31
-#define BCHP_EBI_BURST_CFG_2_prefetch_enable_DEFAULT 0x00000000
-
-/* EBI :: BURST_CFG_2 :: page_enable [30:30] */
-#define BCHP_EBI_BURST_CFG_2_page_enable_MASK 0x40000000
-#define BCHP_EBI_BURST_CFG_2_page_enable_SHIFT 30
-#define BCHP_EBI_BURST_CFG_2_page_enable_DEFAULT 0x00000000
-
-/* EBI :: BURST_CFG_2 :: pfetch_abort_enable [29:29] */
-#define BCHP_EBI_BURST_CFG_2_pfetch_abort_enable_MASK 0x20000000
-#define BCHP_EBI_BURST_CFG_2_pfetch_abort_enable_SHIFT 29
-#define BCHP_EBI_BURST_CFG_2_pfetch_abort_enable_DEFAULT 0x00000000
-
-/* EBI :: BURST_CFG_2 :: page_latch_enable [28:28] */
-#define BCHP_EBI_BURST_CFG_2_page_latch_enable_MASK 0x10000000
-#define BCHP_EBI_BURST_CFG_2_page_latch_enable_SHIFT 28
-#define BCHP_EBI_BURST_CFG_2_page_latch_enable_DEFAULT 0x00000000
-
-/* EBI :: BURST_CFG_2 :: pfetch_wrap_enable [27:27] */
-#define BCHP_EBI_BURST_CFG_2_pfetch_wrap_enable_MASK 0x08000000
-#define BCHP_EBI_BURST_CFG_2_pfetch_wrap_enable_SHIFT 27
-#define BCHP_EBI_BURST_CFG_2_pfetch_wrap_enable_DEFAULT 0x00000000
-
-/* EBI :: BURST_CFG_2 :: reserved0 [26:24] */
-#define BCHP_EBI_BURST_CFG_2_reserved0_MASK 0x07000000
-#define BCHP_EBI_BURST_CFG_2_reserved0_SHIFT 24
-
-/* EBI :: BURST_CFG_2 :: prefetch_size [23:22] */
-#define BCHP_EBI_BURST_CFG_2_prefetch_size_MASK 0x00c00000
-#define BCHP_EBI_BURST_CFG_2_prefetch_size_SHIFT 22
-#define BCHP_EBI_BURST_CFG_2_prefetch_size_DEFAULT 0x00000000
-#define BCHP_EBI_BURST_CFG_2_prefetch_size_SIZE_4_BYTES 0
-#define BCHP_EBI_BURST_CFG_2_prefetch_size_SIZE_8_BYTES 1
-#define BCHP_EBI_BURST_CFG_2_prefetch_size_SIZE_16_BYTES 2
-#define BCHP_EBI_BURST_CFG_2_prefetch_size_SIZE_32_BYTES 3
-
-/* EBI :: BURST_CFG_2 :: page_size [21:20] */
-#define BCHP_EBI_BURST_CFG_2_page_size_MASK 0x00300000
-#define BCHP_EBI_BURST_CFG_2_page_size_SHIFT 20
-#define BCHP_EBI_BURST_CFG_2_page_size_DEFAULT 0x00000000
-#define BCHP_EBI_BURST_CFG_2_page_size_SIZE_4_BYTES 0
-#define BCHP_EBI_BURST_CFG_2_page_size_SIZE_8_BYTES 1
-#define BCHP_EBI_BURST_CFG_2_page_size_SIZE_16_BYTES 2
-#define BCHP_EBI_BURST_CFG_2_page_size_SIZE_32_BYTES 3
-
-/* EBI :: BURST_CFG_2 :: page_wait_count [19:16] */
-#define BCHP_EBI_BURST_CFG_2_page_wait_count_MASK 0x000f0000
-#define BCHP_EBI_BURST_CFG_2_page_wait_count_SHIFT 16
-#define BCHP_EBI_BURST_CFG_2_page_wait_count_DEFAULT 0x00000001
-
-/* EBI :: BURST_CFG_2 :: burst_cyc_disable [15:15] */
-#define BCHP_EBI_BURST_CFG_2_burst_cyc_disable_MASK 0x00008000
-#define BCHP_EBI_BURST_CFG_2_burst_cyc_disable_SHIFT 15
-#define BCHP_EBI_BURST_CFG_2_burst_cyc_disable_DEFAULT 0x00000001
-
-/* EBI :: BURST_CFG_2 :: reserved1 [14:08] */
-#define BCHP_EBI_BURST_CFG_2_reserved1_MASK 0x00007f00
-#define BCHP_EBI_BURST_CFG_2_reserved1_SHIFT 8
-
-/* EBI :: BURST_CFG_2 :: burst_latency [07:04] */
-#define BCHP_EBI_BURST_CFG_2_burst_latency_MASK 0x000000f0
-#define BCHP_EBI_BURST_CFG_2_burst_latency_SHIFT 4
-#define BCHP_EBI_BURST_CFG_2_burst_latency_DEFAULT 0x00000000
-
-/* EBI :: BURST_CFG_2 :: reserved2 [03:02] */
-#define BCHP_EBI_BURST_CFG_2_reserved2_MASK 0x0000000c
-#define BCHP_EBI_BURST_CFG_2_reserved2_SHIFT 2
-
-/* EBI :: BURST_CFG_2 :: data_hold [01:01] */
-#define BCHP_EBI_BURST_CFG_2_data_hold_MASK 0x00000002
-#define BCHP_EBI_BURST_CFG_2_data_hold_SHIFT 1
-#define BCHP_EBI_BURST_CFG_2_data_hold_DEFAULT 0x00000000
-
-/* EBI :: BURST_CFG_2 :: burst_16 [00:00] */
-#define BCHP_EBI_BURST_CFG_2_burst_16_MASK 0x00000001
-#define BCHP_EBI_BURST_CFG_2_burst_16_SHIFT 0
-#define BCHP_EBI_BURST_CFG_2_burst_16_DEFAULT 0x00000000
-
-/***************************************************************************
- *BURST_CFG_3 - EBI Synchronous Intel StrataFlash Burst Configure Register
- ***************************************************************************/
-/* EBI :: BURST_CFG_3 :: prefetch_enable [31:31] */
-#define BCHP_EBI_BURST_CFG_3_prefetch_enable_MASK 0x80000000
-#define BCHP_EBI_BURST_CFG_3_prefetch_enable_SHIFT 31
-#define BCHP_EBI_BURST_CFG_3_prefetch_enable_DEFAULT 0x00000000
-
-/* EBI :: BURST_CFG_3 :: page_enable [30:30] */
-#define BCHP_EBI_BURST_CFG_3_page_enable_MASK 0x40000000
-#define BCHP_EBI_BURST_CFG_3_page_enable_SHIFT 30
-#define BCHP_EBI_BURST_CFG_3_page_enable_DEFAULT 0x00000000
-
-/* EBI :: BURST_CFG_3 :: pfetch_abort_enable [29:29] */
-#define BCHP_EBI_BURST_CFG_3_pfetch_abort_enable_MASK 0x20000000
-#define BCHP_EBI_BURST_CFG_3_pfetch_abort_enable_SHIFT 29
-#define BCHP_EBI_BURST_CFG_3_pfetch_abort_enable_DEFAULT 0x00000000
-
-/* EBI :: BURST_CFG_3 :: page_latch_enable [28:28] */
-#define BCHP_EBI_BURST_CFG_3_page_latch_enable_MASK 0x10000000
-#define BCHP_EBI_BURST_CFG_3_page_latch_enable_SHIFT 28
-#define BCHP_EBI_BURST_CFG_3_page_latch_enable_DEFAULT 0x00000000
-
-/* EBI :: BURST_CFG_3 :: pfetch_wrap_enable [27:27] */
-#define BCHP_EBI_BURST_CFG_3_pfetch_wrap_enable_MASK 0x08000000
-#define BCHP_EBI_BURST_CFG_3_pfetch_wrap_enable_SHIFT 27
-#define BCHP_EBI_BURST_CFG_3_pfetch_wrap_enable_DEFAULT 0x00000000
-
-/* EBI :: BURST_CFG_3 :: reserved0 [26:24] */
-#define BCHP_EBI_BURST_CFG_3_reserved0_MASK 0x07000000
-#define BCHP_EBI_BURST_CFG_3_reserved0_SHIFT 24
-
-/* EBI :: BURST_CFG_3 :: prefetch_size [23:22] */
-#define BCHP_EBI_BURST_CFG_3_prefetch_size_MASK 0x00c00000
-#define BCHP_EBI_BURST_CFG_3_prefetch_size_SHIFT 22
-#define BCHP_EBI_BURST_CFG_3_prefetch_size_DEFAULT 0x00000000
-#define BCHP_EBI_BURST_CFG_3_prefetch_size_SIZE_4_BYTES 0
-#define BCHP_EBI_BURST_CFG_3_prefetch_size_SIZE_8_BYTES 1
-#define BCHP_EBI_BURST_CFG_3_prefetch_size_SIZE_16_BYTES 2
-#define BCHP_EBI_BURST_CFG_3_prefetch_size_SIZE_32_BYTES 3
-
-/* EBI :: BURST_CFG_3 :: page_size [21:20] */
-#define BCHP_EBI_BURST_CFG_3_page_size_MASK 0x00300000
-#define BCHP_EBI_BURST_CFG_3_page_size_SHIFT 20
-#define BCHP_EBI_BURST_CFG_3_page_size_DEFAULT 0x00000000
-#define BCHP_EBI_BURST_CFG_3_page_size_SIZE_4_BYTES 0
-#define BCHP_EBI_BURST_CFG_3_page_size_SIZE_8_BYTES 1
-#define BCHP_EBI_BURST_CFG_3_page_size_SIZE_16_BYTES 2
-#define BCHP_EBI_BURST_CFG_3_page_size_SIZE_32_BYTES 3
-
-/* EBI :: BURST_CFG_3 :: page_wait_count [19:16] */
-#define BCHP_EBI_BURST_CFG_3_page_wait_count_MASK 0x000f0000
-#define BCHP_EBI_BURST_CFG_3_page_wait_count_SHIFT 16
-#define BCHP_EBI_BURST_CFG_3_page_wait_count_DEFAULT 0x00000001
-
-/* EBI :: BURST_CFG_3 :: burst_cyc_disable [15:15] */
-#define BCHP_EBI_BURST_CFG_3_burst_cyc_disable_MASK 0x00008000
-#define BCHP_EBI_BURST_CFG_3_burst_cyc_disable_SHIFT 15
-#define BCHP_EBI_BURST_CFG_3_burst_cyc_disable_DEFAULT 0x00000001
-
-/* EBI :: BURST_CFG_3 :: reserved1 [14:08] */
-#define BCHP_EBI_BURST_CFG_3_reserved1_MASK 0x00007f00
-#define BCHP_EBI_BURST_CFG_3_reserved1_SHIFT 8
-
-/* EBI :: BURST_CFG_3 :: burst_latency [07:04] */
-#define BCHP_EBI_BURST_CFG_3_burst_latency_MASK 0x000000f0
-#define BCHP_EBI_BURST_CFG_3_burst_latency_SHIFT 4
-#define BCHP_EBI_BURST_CFG_3_burst_latency_DEFAULT 0x00000000
-
-/* EBI :: BURST_CFG_3 :: reserved2 [03:02] */
-#define BCHP_EBI_BURST_CFG_3_reserved2_MASK 0x0000000c
-#define BCHP_EBI_BURST_CFG_3_reserved2_SHIFT 2
-
-/* EBI :: BURST_CFG_3 :: data_hold [01:01] */
-#define BCHP_EBI_BURST_CFG_3_data_hold_MASK 0x00000002
-#define BCHP_EBI_BURST_CFG_3_data_hold_SHIFT 1
-#define BCHP_EBI_BURST_CFG_3_data_hold_DEFAULT 0x00000000
-
-/* EBI :: BURST_CFG_3 :: burst_16 [00:00] */
-#define BCHP_EBI_BURST_CFG_3_burst_16_MASK 0x00000001
-#define BCHP_EBI_BURST_CFG_3_burst_16_SHIFT 0
-#define BCHP_EBI_BURST_CFG_3_burst_16_DEFAULT 0x00000000
-
-/***************************************************************************
- *BURST_CFG_4 - EBI Synchronous Intel StrataFlash Burst Configure Register
- ***************************************************************************/
-/* EBI :: BURST_CFG_4 :: prefetch_enable [31:31] */
-#define BCHP_EBI_BURST_CFG_4_prefetch_enable_MASK 0x80000000
-#define BCHP_EBI_BURST_CFG_4_prefetch_enable_SHIFT 31
-#define BCHP_EBI_BURST_CFG_4_prefetch_enable_DEFAULT 0x00000000
-
-/* EBI :: BURST_CFG_4 :: page_enable [30:30] */
-#define BCHP_EBI_BURST_CFG_4_page_enable_MASK 0x40000000
-#define BCHP_EBI_BURST_CFG_4_page_enable_SHIFT 30
-#define BCHP_EBI_BURST_CFG_4_page_enable_DEFAULT 0x00000000
-
-/* EBI :: BURST_CFG_4 :: pfetch_abort_enable [29:29] */
-#define BCHP_EBI_BURST_CFG_4_pfetch_abort_enable_MASK 0x20000000
-#define BCHP_EBI_BURST_CFG_4_pfetch_abort_enable_SHIFT 29
-#define BCHP_EBI_BURST_CFG_4_pfetch_abort_enable_DEFAULT 0x00000000
-
-/* EBI :: BURST_CFG_4 :: page_latch_enable [28:28] */
-#define BCHP_EBI_BURST_CFG_4_page_latch_enable_MASK 0x10000000
-#define BCHP_EBI_BURST_CFG_4_page_latch_enable_SHIFT 28
-#define BCHP_EBI_BURST_CFG_4_page_latch_enable_DEFAULT 0x00000000
-
-/* EBI :: BURST_CFG_4 :: pfetch_wrap_enable [27:27] */
-#define BCHP_EBI_BURST_CFG_4_pfetch_wrap_enable_MASK 0x08000000
-#define BCHP_EBI_BURST_CFG_4_pfetch_wrap_enable_SHIFT 27
-#define BCHP_EBI_BURST_CFG_4_pfetch_wrap_enable_DEFAULT 0x00000000
-
-/* EBI :: BURST_CFG_4 :: reserved0 [26:24] */
-#define BCHP_EBI_BURST_CFG_4_reserved0_MASK 0x07000000
-#define BCHP_EBI_BURST_CFG_4_reserved0_SHIFT 24
-
-/* EBI :: BURST_CFG_4 :: prefetch_size [23:22] */
-#define BCHP_EBI_BURST_CFG_4_prefetch_size_MASK 0x00c00000
-#define BCHP_EBI_BURST_CFG_4_prefetch_size_SHIFT 22
-#define BCHP_EBI_BURST_CFG_4_prefetch_size_DEFAULT 0x00000000
-#define BCHP_EBI_BURST_CFG_4_prefetch_size_SIZE_4_BYTES 0
-#define BCHP_EBI_BURST_CFG_4_prefetch_size_SIZE_8_BYTES 1
-#define BCHP_EBI_BURST_CFG_4_prefetch_size_SIZE_16_BYTES 2
-#define BCHP_EBI_BURST_CFG_4_prefetch_size_SIZE_32_BYTES 3
-
-/* EBI :: BURST_CFG_4 :: page_size [21:20] */
-#define BCHP_EBI_BURST_CFG_4_page_size_MASK 0x00300000
-#define BCHP_EBI_BURST_CFG_4_page_size_SHIFT 20
-#define BCHP_EBI_BURST_CFG_4_page_size_DEFAULT 0x00000000
-#define BCHP_EBI_BURST_CFG_4_page_size_SIZE_4_BYTES 0
-#define BCHP_EBI_BURST_CFG_4_page_size_SIZE_8_BYTES 1
-#define BCHP_EBI_BURST_CFG_4_page_size_SIZE_16_BYTES 2
-#define BCHP_EBI_BURST_CFG_4_page_size_SIZE_32_BYTES 3
-
-/* EBI :: BURST_CFG_4 :: page_wait_count [19:16] */
-#define BCHP_EBI_BURST_CFG_4_page_wait_count_MASK 0x000f0000
-#define BCHP_EBI_BURST_CFG_4_page_wait_count_SHIFT 16
-#define BCHP_EBI_BURST_CFG_4_page_wait_count_DEFAULT 0x00000001
-
-/* EBI :: BURST_CFG_4 :: burst_cyc_disable [15:15] */
-#define BCHP_EBI_BURST_CFG_4_burst_cyc_disable_MASK 0x00008000
-#define BCHP_EBI_BURST_CFG_4_burst_cyc_disable_SHIFT 15
-#define BCHP_EBI_BURST_CFG_4_burst_cyc_disable_DEFAULT 0x00000001
-
-/* EBI :: BURST_CFG_4 :: reserved1 [14:08] */
-#define BCHP_EBI_BURST_CFG_4_reserved1_MASK 0x00007f00
-#define BCHP_EBI_BURST_CFG_4_reserved1_SHIFT 8
-
-/* EBI :: BURST_CFG_4 :: burst_latency [07:04] */
-#define BCHP_EBI_BURST_CFG_4_burst_latency_MASK 0x000000f0
-#define BCHP_EBI_BURST_CFG_4_burst_latency_SHIFT 4
-#define BCHP_EBI_BURST_CFG_4_burst_latency_DEFAULT 0x00000000
-
-/* EBI :: BURST_CFG_4 :: reserved2 [03:02] */
-#define BCHP_EBI_BURST_CFG_4_reserved2_MASK 0x0000000c
-#define BCHP_EBI_BURST_CFG_4_reserved2_SHIFT 2
-
-/* EBI :: BURST_CFG_4 :: data_hold [01:01] */
-#define BCHP_EBI_BURST_CFG_4_data_hold_MASK 0x00000002
-#define BCHP_EBI_BURST_CFG_4_data_hold_SHIFT 1
-#define BCHP_EBI_BURST_CFG_4_data_hold_DEFAULT 0x00000000
-
-/* EBI :: BURST_CFG_4 :: burst_16 [00:00] */
-#define BCHP_EBI_BURST_CFG_4_burst_16_MASK 0x00000001
-#define BCHP_EBI_BURST_CFG_4_burst_16_SHIFT 0
-#define BCHP_EBI_BURST_CFG_4_burst_16_DEFAULT 0x00000000
-
-/***************************************************************************
- *BURST_CFG_5 - EBI Synchronous Intel StrataFlash Burst Configure Register
- ***************************************************************************/
-/* EBI :: BURST_CFG_5 :: prefetch_enable [31:31] */
-#define BCHP_EBI_BURST_CFG_5_prefetch_enable_MASK 0x80000000
-#define BCHP_EBI_BURST_CFG_5_prefetch_enable_SHIFT 31
-#define BCHP_EBI_BURST_CFG_5_prefetch_enable_DEFAULT 0x00000000
-
-/* EBI :: BURST_CFG_5 :: page_enable [30:30] */
-#define BCHP_EBI_BURST_CFG_5_page_enable_MASK 0x40000000
-#define BCHP_EBI_BURST_CFG_5_page_enable_SHIFT 30
-#define BCHP_EBI_BURST_CFG_5_page_enable_DEFAULT 0x00000000
-
-/* EBI :: BURST_CFG_5 :: pfetch_abort_enable [29:29] */
-#define BCHP_EBI_BURST_CFG_5_pfetch_abort_enable_MASK 0x20000000
-#define BCHP_EBI_BURST_CFG_5_pfetch_abort_enable_SHIFT 29
-#define BCHP_EBI_BURST_CFG_5_pfetch_abort_enable_DEFAULT 0x00000000
-
-/* EBI :: BURST_CFG_5 :: page_latch_enable [28:28] */
-#define BCHP_EBI_BURST_CFG_5_page_latch_enable_MASK 0x10000000
-#define BCHP_EBI_BURST_CFG_5_page_latch_enable_SHIFT 28
-#define BCHP_EBI_BURST_CFG_5_page_latch_enable_DEFAULT 0x00000000
-
-/* EBI :: BURST_CFG_5 :: pfetch_wrap_enable [27:27] */
-#define BCHP_EBI_BURST_CFG_5_pfetch_wrap_enable_MASK 0x08000000
-#define BCHP_EBI_BURST_CFG_5_pfetch_wrap_enable_SHIFT 27
-#define BCHP_EBI_BURST_CFG_5_pfetch_wrap_enable_DEFAULT 0x00000000
-
-/* EBI :: BURST_CFG_5 :: reserved0 [26:24] */
-#define BCHP_EBI_BURST_CFG_5_reserved0_MASK 0x07000000
-#define BCHP_EBI_BURST_CFG_5_reserved0_SHIFT 24
-
-/* EBI :: BURST_CFG_5 :: prefetch_size [23:22] */
-#define BCHP_EBI_BURST_CFG_5_prefetch_size_MASK 0x00c00000
-#define BCHP_EBI_BURST_CFG_5_prefetch_size_SHIFT 22
-#define BCHP_EBI_BURST_CFG_5_prefetch_size_DEFAULT 0x00000000
-#define BCHP_EBI_BURST_CFG_5_prefetch_size_SIZE_4_BYTES 0
-#define BCHP_EBI_BURST_CFG_5_prefetch_size_SIZE_8_BYTES 1
-#define BCHP_EBI_BURST_CFG_5_prefetch_size_SIZE_16_BYTES 2
-#define BCHP_EBI_BURST_CFG_5_prefetch_size_SIZE_32_BYTES 3
-
-/* EBI :: BURST_CFG_5 :: page_size [21:20] */
-#define BCHP_EBI_BURST_CFG_5_page_size_MASK 0x00300000
-#define BCHP_EBI_BURST_CFG_5_page_size_SHIFT 20
-#define BCHP_EBI_BURST_CFG_5_page_size_DEFAULT 0x00000000
-#define BCHP_EBI_BURST_CFG_5_page_size_SIZE_4_BYTES 0
-#define BCHP_EBI_BURST_CFG_5_page_size_SIZE_8_BYTES 1
-#define BCHP_EBI_BURST_CFG_5_page_size_SIZE_16_BYTES 2
-#define BCHP_EBI_BURST_CFG_5_page_size_SIZE_32_BYTES 3
-
-/* EBI :: BURST_CFG_5 :: page_wait_count [19:16] */
-#define BCHP_EBI_BURST_CFG_5_page_wait_count_MASK 0x000f0000
-#define BCHP_EBI_BURST_CFG_5_page_wait_count_SHIFT 16
-#define BCHP_EBI_BURST_CFG_5_page_wait_count_DEFAULT 0x00000001
-
-/* EBI :: BURST_CFG_5 :: burst_cyc_disable [15:15] */
-#define BCHP_EBI_BURST_CFG_5_burst_cyc_disable_MASK 0x00008000
-#define BCHP_EBI_BURST_CFG_5_burst_cyc_disable_SHIFT 15
-#define BCHP_EBI_BURST_CFG_5_burst_cyc_disable_DEFAULT 0x00000001
-
-/* EBI :: BURST_CFG_5 :: reserved1 [14:08] */
-#define BCHP_EBI_BURST_CFG_5_reserved1_MASK 0x00007f00
-#define BCHP_EBI_BURST_CFG_5_reserved1_SHIFT 8
-
-/* EBI :: BURST_CFG_5 :: burst_latency [07:04] */
-#define BCHP_EBI_BURST_CFG_5_burst_latency_MASK 0x000000f0
-#define BCHP_EBI_BURST_CFG_5_burst_latency_SHIFT 4
-#define BCHP_EBI_BURST_CFG_5_burst_latency_DEFAULT 0x00000000
-
-/* EBI :: BURST_CFG_5 :: reserved2 [03:02] */
-#define BCHP_EBI_BURST_CFG_5_reserved2_MASK 0x0000000c
-#define BCHP_EBI_BURST_CFG_5_reserved2_SHIFT 2
-
-/* EBI :: BURST_CFG_5 :: data_hold [01:01] */
-#define BCHP_EBI_BURST_CFG_5_data_hold_MASK 0x00000002
-#define BCHP_EBI_BURST_CFG_5_data_hold_SHIFT 1
-#define BCHP_EBI_BURST_CFG_5_data_hold_DEFAULT 0x00000000
-
-/* EBI :: BURST_CFG_5 :: burst_16 [00:00] */
-#define BCHP_EBI_BURST_CFG_5_burst_16_MASK 0x00000001
-#define BCHP_EBI_BURST_CFG_5_burst_16_SHIFT 0
-#define BCHP_EBI_BURST_CFG_5_burst_16_DEFAULT 0x00000000
-
-/***************************************************************************
- *BURST_CFG_6 - EBI Synchronous Intel StrataFlash Burst Configure Register
- ***************************************************************************/
-/* EBI :: BURST_CFG_6 :: prefetch_enable [31:31] */
-#define BCHP_EBI_BURST_CFG_6_prefetch_enable_MASK 0x80000000
-#define BCHP_EBI_BURST_CFG_6_prefetch_enable_SHIFT 31
-#define BCHP_EBI_BURST_CFG_6_prefetch_enable_DEFAULT 0x00000000
-
-/* EBI :: BURST_CFG_6 :: page_enable [30:30] */
-#define BCHP_EBI_BURST_CFG_6_page_enable_MASK 0x40000000
-#define BCHP_EBI_BURST_CFG_6_page_enable_SHIFT 30
-#define BCHP_EBI_BURST_CFG_6_page_enable_DEFAULT 0x00000000
-
-/* EBI :: BURST_CFG_6 :: pfetch_abort_enable [29:29] */
-#define BCHP_EBI_BURST_CFG_6_pfetch_abort_enable_MASK 0x20000000
-#define BCHP_EBI_BURST_CFG_6_pfetch_abort_enable_SHIFT 29
-#define BCHP_EBI_BURST_CFG_6_pfetch_abort_enable_DEFAULT 0x00000000
-
-/* EBI :: BURST_CFG_6 :: page_latch_enable [28:28] */
-#define BCHP_EBI_BURST_CFG_6_page_latch_enable_MASK 0x10000000
-#define BCHP_EBI_BURST_CFG_6_page_latch_enable_SHIFT 28
-#define BCHP_EBI_BURST_CFG_6_page_latch_enable_DEFAULT 0x00000000
-
-/* EBI :: BURST_CFG_6 :: pfetch_wrap_enable [27:27] */
-#define BCHP_EBI_BURST_CFG_6_pfetch_wrap_enable_MASK 0x08000000
-#define BCHP_EBI_BURST_CFG_6_pfetch_wrap_enable_SHIFT 27
-#define BCHP_EBI_BURST_CFG_6_pfetch_wrap_enable_DEFAULT 0x00000000
-
-/* EBI :: BURST_CFG_6 :: reserved0 [26:24] */
-#define BCHP_EBI_BURST_CFG_6_reserved0_MASK 0x07000000
-#define BCHP_EBI_BURST_CFG_6_reserved0_SHIFT 24
-
-/* EBI :: BURST_CFG_6 :: prefetch_size [23:22] */
-#define BCHP_EBI_BURST_CFG_6_prefetch_size_MASK 0x00c00000
-#define BCHP_EBI_BURST_CFG_6_prefetch_size_SHIFT 22
-#define BCHP_EBI_BURST_CFG_6_prefetch_size_DEFAULT 0x00000000
-#define BCHP_EBI_BURST_CFG_6_prefetch_size_SIZE_4_BYTES 0
-#define BCHP_EBI_BURST_CFG_6_prefetch_size_SIZE_8_BYTES 1
-#define BCHP_EBI_BURST_CFG_6_prefetch_size_SIZE_16_BYTES 2
-#define BCHP_EBI_BURST_CFG_6_prefetch_size_SIZE_32_BYTES 3
-
-/* EBI :: BURST_CFG_6 :: page_size [21:20] */
-#define BCHP_EBI_BURST_CFG_6_page_size_MASK 0x00300000
-#define BCHP_EBI_BURST_CFG_6_page_size_SHIFT 20
-#define BCHP_EBI_BURST_CFG_6_page_size_DEFAULT 0x00000000
-#define BCHP_EBI_BURST_CFG_6_page_size_SIZE_4_BYTES 0
-#define BCHP_EBI_BURST_CFG_6_page_size_SIZE_8_BYTES 1
-#define BCHP_EBI_BURST_CFG_6_page_size_SIZE_16_BYTES 2
-#define BCHP_EBI_BURST_CFG_6_page_size_SIZE_32_BYTES 3
-
-/* EBI :: BURST_CFG_6 :: page_wait_count [19:16] */
-#define BCHP_EBI_BURST_CFG_6_page_wait_count_MASK 0x000f0000
-#define BCHP_EBI_BURST_CFG_6_page_wait_count_SHIFT 16
-#define BCHP_EBI_BURST_CFG_6_page_wait_count_DEFAULT 0x00000001
-
-/* EBI :: BURST_CFG_6 :: burst_cyc_disable [15:15] */
-#define BCHP_EBI_BURST_CFG_6_burst_cyc_disable_MASK 0x00008000
-#define BCHP_EBI_BURST_CFG_6_burst_cyc_disable_SHIFT 15
-#define BCHP_EBI_BURST_CFG_6_burst_cyc_disable_DEFAULT 0x00000001
-
-/* EBI :: BURST_CFG_6 :: reserved1 [14:08] */
-#define BCHP_EBI_BURST_CFG_6_reserved1_MASK 0x00007f00
-#define BCHP_EBI_BURST_CFG_6_reserved1_SHIFT 8
-
-/* EBI :: BURST_CFG_6 :: burst_latency [07:04] */
-#define BCHP_EBI_BURST_CFG_6_burst_latency_MASK 0x000000f0
-#define BCHP_EBI_BURST_CFG_6_burst_latency_SHIFT 4
-#define BCHP_EBI_BURST_CFG_6_burst_latency_DEFAULT 0x00000000
-
-/* EBI :: BURST_CFG_6 :: reserved2 [03:02] */
-#define BCHP_EBI_BURST_CFG_6_reserved2_MASK 0x0000000c
-#define BCHP_EBI_BURST_CFG_6_reserved2_SHIFT 2
-
-/* EBI :: BURST_CFG_6 :: data_hold [01:01] */
-#define BCHP_EBI_BURST_CFG_6_data_hold_MASK 0x00000002
-#define BCHP_EBI_BURST_CFG_6_data_hold_SHIFT 1
-#define BCHP_EBI_BURST_CFG_6_data_hold_DEFAULT 0x00000000
-
-/* EBI :: BURST_CFG_6 :: burst_16 [00:00] */
-#define BCHP_EBI_BURST_CFG_6_burst_16_MASK 0x00000001
-#define BCHP_EBI_BURST_CFG_6_burst_16_SHIFT 0
-#define BCHP_EBI_BURST_CFG_6_burst_16_DEFAULT 0x00000000
-
-/***************************************************************************
- *ECR - EBI Configuration Register
- ***************************************************************************/
-/* EBI :: ECR :: reserved0 [31:28] */
-#define BCHP_EBI_ECR_reserved0_MASK 0xf0000000
-#define BCHP_EBI_ECR_reserved0_SHIFT 28
-
-/* EBI :: ECR :: Ebi_Byte_Swap [27:27] */
-#define BCHP_EBI_ECR_Ebi_Byte_Swap_MASK 0x08000000
-#define BCHP_EBI_ECR_Ebi_Byte_Swap_SHIFT 27
-#define BCHP_EBI_ECR_Ebi_Byte_Swap_DEFAULT 0x00000000
-#define BCHP_EBI_ECR_Ebi_Byte_Swap_Byte_Swap_For_32_16_and_8_bit_Xfers 0
-#define BCHP_EBI_ECR_Ebi_Byte_Swap_Byte_Swap_For_8_bit_Xfers_Only 1
-
-/* EBI :: ECR :: reserved1 [26:26] */
-#define BCHP_EBI_ECR_reserved1_MASK 0x04000000
-#define BCHP_EBI_ECR_reserved1_SHIFT 26
-
-/* EBI :: ECR :: Flag_32bit_Xfer [25:25] */
-#define BCHP_EBI_ECR_Flag_32bit_Xfer_MASK 0x02000000
-#define BCHP_EBI_ECR_Flag_32bit_Xfer_SHIFT 25
-#define BCHP_EBI_ECR_Flag_32bit_Xfer_DEFAULT 0x00000000
-#define BCHP_EBI_ECR_Flag_32bit_Xfer_Code_32bit_Xfer_as_10 0
-#define BCHP_EBI_ECR_Flag_32bit_Xfer_Code_32bit_Xfer_as_00 1
-
-/* EBI :: ECR :: reserved2 [24:11] */
-#define BCHP_EBI_ECR_reserved2_MASK 0x01fff800
-#define BCHP_EBI_ECR_reserved2_SHIFT 11
-
-/* EBI :: ECR :: timeout_count [10:00] */
-#define BCHP_EBI_ECR_timeout_count_MASK 0x000007ff
-#define BCHP_EBI_ECR_timeout_count_SHIFT 0
-#define BCHP_EBI_ECR_timeout_count_DEFAULT 0x00000400
-
-/***************************************************************************
- *CS_TRISTATE_CFG - EBI CS Tristate Configuration Register
- ***************************************************************************/
-/* EBI :: CS_TRISTATE_CFG :: tristate_ebi_rdb [31:31] */
-#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_rdb_MASK 0x80000000
-#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_rdb_SHIFT 31
-#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_rdb_DEFAULT 0x00000000
-
-/* EBI :: CS_TRISTATE_CFG :: tristate_ebi_dsb [30:30] */
-#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_dsb_MASK 0x40000000
-#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_dsb_SHIFT 30
-#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_dsb_DEFAULT 0x00000000
-
-/* EBI :: CS_TRISTATE_CFG :: tristate_ebi_tsb [29:29] */
-#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_tsb_MASK 0x20000000
-#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_tsb_SHIFT 29
-#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_tsb_DEFAULT 0x00000000
-
-/* EBI :: CS_TRISTATE_CFG :: tristate_ebi_rwb [28:28] */
-#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_rwb_MASK 0x10000000
-#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_rwb_SHIFT 28
-#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_rwb_DEFAULT 0x00000000
-
-/* EBI :: CS_TRISTATE_CFG :: tristate_ebi_we1b [27:27] */
-#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_we1b_MASK 0x08000000
-#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_we1b_SHIFT 27
-#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_we1b_DEFAULT 0x00000000
-
-/* EBI :: CS_TRISTATE_CFG :: tristate_ebi_we0b [26:26] */
-#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_we0b_MASK 0x04000000
-#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_we0b_SHIFT 26
-#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_we0b_DEFAULT 0x00000000
-
-/* EBI :: CS_TRISTATE_CFG :: tristate_ebi_tsize1b [25:25] */
-#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_tsize1b_MASK 0x02000000
-#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_tsize1b_SHIFT 25
-#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_tsize1b_DEFAULT 0x00000000
-
-/* EBI :: CS_TRISTATE_CFG :: tristate_ebi_tsize0b [24:24] */
-#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_tsize0b_MASK 0x01000000
-#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_tsize0b_SHIFT 24
-#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_tsize0b_DEFAULT 0x00000000
-
-/* EBI :: CS_TRISTATE_CFG :: reserved0 [23:07] */
-#define BCHP_EBI_CS_TRISTATE_CFG_reserved0_MASK 0x00ffff80
-#define BCHP_EBI_CS_TRISTATE_CFG_reserved0_SHIFT 7
-
-/* EBI :: CS_TRISTATE_CFG :: tristate_ebi_cs6 [06:06] */
-#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_cs6_MASK 0x00000040
-#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_cs6_SHIFT 6
-#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_cs6_DEFAULT 0x00000000
-
-/* EBI :: CS_TRISTATE_CFG :: tristate_ebi_cs5 [05:05] */
-#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_cs5_MASK 0x00000020
-#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_cs5_SHIFT 5
-#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_cs5_DEFAULT 0x00000000
-
-/* EBI :: CS_TRISTATE_CFG :: tristate_ebi_cs4 [04:04] */
-#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_cs4_MASK 0x00000010
-#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_cs4_SHIFT 4
-#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_cs4_DEFAULT 0x00000000
-
-/* EBI :: CS_TRISTATE_CFG :: tristate_ebi_cs3 [03:03] */
-#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_cs3_MASK 0x00000008
-#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_cs3_SHIFT 3
-#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_cs3_DEFAULT 0x00000000
-
-/* EBI :: CS_TRISTATE_CFG :: tristate_ebi_cs2 [02:02] */
-#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_cs2_MASK 0x00000004
-#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_cs2_SHIFT 2
-#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_cs2_DEFAULT 0x00000000
-
-/* EBI :: CS_TRISTATE_CFG :: tristate_ebi_cs1 [01:01] */
-#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_cs1_MASK 0x00000002
-#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_cs1_SHIFT 1
-#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_cs1_DEFAULT 0x00000000
-
-/* EBI :: CS_TRISTATE_CFG :: tristate_ebi_cs0 [00:00] */
-#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_cs0_MASK 0x00000001
-#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_cs0_SHIFT 0
-#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_cs0_DEFAULT 0x00000000
-
-/***************************************************************************
- *CS_SPI_SELECT - SPI CS Select
- ***************************************************************************/
-/* EBI :: CS_SPI_SELECT :: reserved0 [31:15] */
-#define BCHP_EBI_CS_SPI_SELECT_reserved0_MASK 0xffff8000
-#define BCHP_EBI_CS_SPI_SELECT_reserved0_SHIFT 15
-
-/* EBI :: CS_SPI_SELECT :: EBI_CS_6_USES_SPI [14:14] */
-#define BCHP_EBI_CS_SPI_SELECT_EBI_CS_6_USES_SPI_MASK 0x00004000
-#define BCHP_EBI_CS_SPI_SELECT_EBI_CS_6_USES_SPI_SHIFT 14
-#define BCHP_EBI_CS_SPI_SELECT_EBI_CS_6_USES_SPI_DEFAULT 0x00000000
-
-/* EBI :: CS_SPI_SELECT :: EBI_CS_5_USES_SPI [13:13] */
-#define BCHP_EBI_CS_SPI_SELECT_EBI_CS_5_USES_SPI_MASK 0x00002000
-#define BCHP_EBI_CS_SPI_SELECT_EBI_CS_5_USES_SPI_SHIFT 13
-#define BCHP_EBI_CS_SPI_SELECT_EBI_CS_5_USES_SPI_DEFAULT 0x00000000
-
-/* EBI :: CS_SPI_SELECT :: EBI_CS_4_USES_SPI [12:12] */
-#define BCHP_EBI_CS_SPI_SELECT_EBI_CS_4_USES_SPI_MASK 0x00001000
-#define BCHP_EBI_CS_SPI_SELECT_EBI_CS_4_USES_SPI_SHIFT 12
-#define BCHP_EBI_CS_SPI_SELECT_EBI_CS_4_USES_SPI_DEFAULT 0x00000000
-
-/* EBI :: CS_SPI_SELECT :: EBI_CS_3_USES_SPI [11:11] */
-#define BCHP_EBI_CS_SPI_SELECT_EBI_CS_3_USES_SPI_MASK 0x00000800
-#define BCHP_EBI_CS_SPI_SELECT_EBI_CS_3_USES_SPI_SHIFT 11
-#define BCHP_EBI_CS_SPI_SELECT_EBI_CS_3_USES_SPI_DEFAULT 0x00000000
-
-/* EBI :: CS_SPI_SELECT :: EBI_CS_2_USES_SPI [10:10] */
-#define BCHP_EBI_CS_SPI_SELECT_EBI_CS_2_USES_SPI_MASK 0x00000400
-#define BCHP_EBI_CS_SPI_SELECT_EBI_CS_2_USES_SPI_SHIFT 10
-#define BCHP_EBI_CS_SPI_SELECT_EBI_CS_2_USES_SPI_DEFAULT 0x00000000
-
-/* EBI :: CS_SPI_SELECT :: EBI_CS_1_USES_SPI [09:09] */
-#define BCHP_EBI_CS_SPI_SELECT_EBI_CS_1_USES_SPI_MASK 0x00000200
-#define BCHP_EBI_CS_SPI_SELECT_EBI_CS_1_USES_SPI_SHIFT 9
-#define BCHP_EBI_CS_SPI_SELECT_EBI_CS_1_USES_SPI_DEFAULT 0x00000000
-
-/* EBI :: CS_SPI_SELECT :: EBI_CS_0_USES_SPI [08:08] */
-#define BCHP_EBI_CS_SPI_SELECT_EBI_CS_0_USES_SPI_MASK 0x00000100
-#define BCHP_EBI_CS_SPI_SELECT_EBI_CS_0_USES_SPI_SHIFT 8
-
-/* EBI :: CS_SPI_SELECT :: reserved1 [07:07] */
-#define BCHP_EBI_CS_SPI_SELECT_reserved1_MASK 0x00000080
-#define BCHP_EBI_CS_SPI_SELECT_reserved1_SHIFT 7
-
-/* EBI :: CS_SPI_SELECT :: SPI_EBI_CS_6_SEL [06:06] */
-#define BCHP_EBI_CS_SPI_SELECT_SPI_EBI_CS_6_SEL_MASK 0x00000040
-#define BCHP_EBI_CS_SPI_SELECT_SPI_EBI_CS_6_SEL_SHIFT 6
-#define BCHP_EBI_CS_SPI_SELECT_SPI_EBI_CS_6_SEL_DEFAULT 0x00000000
-
-/* EBI :: CS_SPI_SELECT :: SPI_EBI_CS_5_SEL [05:05] */
-#define BCHP_EBI_CS_SPI_SELECT_SPI_EBI_CS_5_SEL_MASK 0x00000020
-#define BCHP_EBI_CS_SPI_SELECT_SPI_EBI_CS_5_SEL_SHIFT 5
-#define BCHP_EBI_CS_SPI_SELECT_SPI_EBI_CS_5_SEL_DEFAULT 0x00000000
-
-/* EBI :: CS_SPI_SELECT :: SPI_EBI_CS_4_SEL [04:04] */
-#define BCHP_EBI_CS_SPI_SELECT_SPI_EBI_CS_4_SEL_MASK 0x00000010
-#define BCHP_EBI_CS_SPI_SELECT_SPI_EBI_CS_4_SEL_SHIFT 4
-#define BCHP_EBI_CS_SPI_SELECT_SPI_EBI_CS_4_SEL_DEFAULT 0x00000000
-
-/* EBI :: CS_SPI_SELECT :: SPI_EBI_CS_3_SEL [03:03] */
-#define BCHP_EBI_CS_SPI_SELECT_SPI_EBI_CS_3_SEL_MASK 0x00000008
-#define BCHP_EBI_CS_SPI_SELECT_SPI_EBI_CS_3_SEL_SHIFT 3
-#define BCHP_EBI_CS_SPI_SELECT_SPI_EBI_CS_3_SEL_DEFAULT 0x00000000
-
-/* EBI :: CS_SPI_SELECT :: SPI_EBI_CS_2_SEL [02:02] */
-#define BCHP_EBI_CS_SPI_SELECT_SPI_EBI_CS_2_SEL_MASK 0x00000004
-#define BCHP_EBI_CS_SPI_SELECT_SPI_EBI_CS_2_SEL_SHIFT 2
-#define BCHP_EBI_CS_SPI_SELECT_SPI_EBI_CS_2_SEL_DEFAULT 0x00000000
-
-/* EBI :: CS_SPI_SELECT :: SPI_EBI_CS_1_SEL [01:01] */
-#define BCHP_EBI_CS_SPI_SELECT_SPI_EBI_CS_1_SEL_MASK 0x00000002
-#define BCHP_EBI_CS_SPI_SELECT_SPI_EBI_CS_1_SEL_SHIFT 1
-#define BCHP_EBI_CS_SPI_SELECT_SPI_EBI_CS_1_SEL_DEFAULT 0x00000000
-
-/* EBI :: CS_SPI_SELECT :: SPI_EBI_CS_0_SEL [00:00] */
-#define BCHP_EBI_CS_SPI_SELECT_SPI_EBI_CS_0_SEL_MASK 0x00000001
-#define BCHP_EBI_CS_SPI_SELECT_SPI_EBI_CS_0_SEL_SHIFT 0
-
-/***************************************************************************
- *ARRAY_ADDRESS - EBI Data Array Address
- ***************************************************************************/
-/* EBI :: ARRAY_ADDRESS :: ADDRESS [31:09] */
-#define BCHP_EBI_ARRAY_ADDRESS_ADDRESS_MASK 0xfffffe00
-#define BCHP_EBI_ARRAY_ADDRESS_ADDRESS_SHIFT 9
-#define BCHP_EBI_ARRAY_ADDRESS_ADDRESS_DEFAULT 0x00000000
-
-/* EBI :: ARRAY_ADDRESS :: reserved0 [08:03] */
-#define BCHP_EBI_ARRAY_ADDRESS_reserved0_MASK 0x000001f8
-#define BCHP_EBI_ARRAY_ADDRESS_reserved0_SHIFT 3
-
-/* EBI :: ARRAY_ADDRESS :: CS_SEL [02:00] */
-#define BCHP_EBI_ARRAY_ADDRESS_CS_SEL_MASK 0x00000007
-#define BCHP_EBI_ARRAY_ADDRESS_CS_SEL_SHIFT 0
-#define BCHP_EBI_ARRAY_ADDRESS_CS_SEL_DEFAULT 0x00000000
-
-/***************************************************************************
- *DATA_ARRAY%i - EBI Data Array Read/Write Access
- ***************************************************************************/
-#define BCHP_EBI_DATA_ARRAYi_ARRAY_BASE 0x203d0a00
-#define BCHP_EBI_DATA_ARRAYi_ARRAY_START 0
-#define BCHP_EBI_DATA_ARRAYi_ARRAY_END 127
-#define BCHP_EBI_DATA_ARRAYi_ARRAY_ELEMENT_SIZE 32
-
-/***************************************************************************
- *DATA_ARRAY%i - EBI Data Array Read/Write Access
- ***************************************************************************/
-/* EBI :: DATA_ARRAYi :: WORD [31:00] */
-#define BCHP_EBI_DATA_ARRAYi_WORD_MASK 0xffffffff
-#define BCHP_EBI_DATA_ARRAYi_WORD_SHIFT 0
-
-
-#endif /* #ifndef BCHP_EBI_H__ */
-
-/* End of File */
diff --git a/include/linux/brcmstb/7145a0/bchp_fpm_ctrl_fpm.h b/include/linux/brcmstb/7145a0/bchp_fpm_ctrl_fpm.h
deleted file mode 100644
index c09a702..0000000
--- a/include/linux/brcmstb/7145a0/bchp_fpm_ctrl_fpm.h
+++ /dev/null
@@ -1,592 +0,0 @@
-/***************************************************************************
- * Copyright (c) 1999-2013, Broadcom Corporation
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
- *
- * Module Description:
- * DO NOT EDIT THIS FILE DIRECTLY
- *
- * This module was generated magically with RDB from a source description
- * file. You must edit the source file for changes to be made to this file.
- *
- *
- * Date: Generated on Wed May 8 03:09:25 2013
- * MD5 Checksum d41d8cd98f00b204e9800998ecf8427e
- *
- * Compiled with: RDB Utility combo_header.pl
- * RDB Parser 3.0
- * unknown unknown
- * Perl Interpreter 5.008008
- * Operating System linux
- *
- * Revision History:
- *
- * $brcm_Log: $
- *
- ***************************************************************************/
-
-#ifndef BCHP_FPM_CTRL_FPM_H__
-#define BCHP_FPM_CTRL_FPM_H__
-
-/***************************************************************************
- *FPM_CTRL_FPM - FPM FPM Control Registers
- ***************************************************************************/
-#define BCHP_FPM_CTRL_FPM_FPM_CTL 0x03a00000 /* FPM Control Register */
-#define BCHP_FPM_CTRL_FPM_FPM_CFG1 0x03a00004 /* FPM Configuration Register */
-#define BCHP_FPM_CTRL_FPM_POOL1_INTR_MSK 0x03a00010 /* POOL1 Interrupt Mask Register */
-#define BCHP_FPM_CTRL_FPM_POOL1_INTR_STS 0x03a00014 /* POOL1 Interrupt Status Register */
-#define BCHP_FPM_CTRL_FPM_POOL1_STALL_MSK 0x03a00018 /* POOL1 Stall FPM mask */
-#define BCHP_FPM_CTRL_FPM_POOL1_CFG1 0x03a00040 /* POOL1 Configuration Register 1 */
-#define BCHP_FPM_CTRL_FPM_POOL1_CFG2 0x03a00044 /* POOL1 Configuration Register 2 */
-#define BCHP_FPM_CTRL_FPM_POOL1_CFG3 0x03a00048 /* POOL1 Configuration Register 3 */
-#define BCHP_FPM_CTRL_FPM_POOL1_STAT1 0x03a00050 /* POOL1 Status Register 1 */
-#define BCHP_FPM_CTRL_FPM_POOL1_STAT2 0x03a00054 /* POOL1 Status Register 2 */
-#define BCHP_FPM_CTRL_FPM_POOL1_STAT3 0x03a00058 /* POOL1 Status Register 3 */
-#define BCHP_FPM_CTRL_FPM_POOL1_STAT4 0x03a0005c /* POOL1 Status Register 4 */
-#define BCHP_FPM_CTRL_FPM_POOL1_STAT5 0x03a00060 /* POOL1 Status Register 5 */
-#define BCHP_FPM_CTRL_FPM_POOL1_STAT6 0x03a00064 /* POOL1 Status Register 6 */
-#define BCHP_FPM_CTRL_FPM_POOL1_STAT7 0x03a00068 /* POOL1 Status Register 7 */
-#define BCHP_FPM_CTRL_FPM_POOL1_XON_XOFF_CFG 0x03a000c0 /* POOL1 XON/XOFF Threshold Configuration Register */
-#define BCHP_FPM_CTRL_FPM_MEM_CTL 0x03a00100 /* Back door Memory Access Control Register */
-#define BCHP_FPM_CTRL_FPM_MEM_DATA1 0x03a00104 /* Back door Memory Data1 Register */
-#define BCHP_FPM_CTRL_FPM_MEM_DATA2 0x03a00108 /* Back door Memory Data2 Register */
-#define BCHP_FPM_CTRL_FPM_SPARE 0x03a00120 /* Spare Register for future use */
-
-/***************************************************************************
- *FPM_CTL - FPM Control Register
- ***************************************************************************/
-/* FPM_CTRL_FPM :: FPM_CTL :: TP_MUX_CNTRL [31:28] */
-#define BCHP_FPM_CTRL_FPM_FPM_CTL_TP_MUX_CNTRL_MASK 0xf0000000
-#define BCHP_FPM_CTRL_FPM_FPM_CTL_TP_MUX_CNTRL_SHIFT 28
-#define BCHP_FPM_CTRL_FPM_FPM_CTL_TP_MUX_CNTRL_DEFAULT 0x00000000
-
-/* FPM_CTRL_FPM :: FPM_CTL :: reserved0 [27:27] */
-#define BCHP_FPM_CTRL_FPM_FPM_CTL_reserved0_MASK 0x08000000
-#define BCHP_FPM_CTRL_FPM_FPM_CTL_reserved0_SHIFT 27
-
-/* FPM_CTRL_FPM :: FPM_CTL :: ENABLE_HIGH_TOK_ALWAYS [26:26] */
-#define BCHP_FPM_CTRL_FPM_FPM_CTL_ENABLE_HIGH_TOK_ALWAYS_MASK 0x04000000
-#define BCHP_FPM_CTRL_FPM_FPM_CTL_ENABLE_HIGH_TOK_ALWAYS_SHIFT 26
-#define BCHP_FPM_CTRL_FPM_FPM_CTL_ENABLE_HIGH_TOK_ALWAYS_DEFAULT 0x00000000
-
-/* FPM_CTRL_FPM :: FPM_CTL :: MEM_CORRUPT_CHECK_DISABLE [25:25] */
-#define BCHP_FPM_CTRL_FPM_FPM_CTL_MEM_CORRUPT_CHECK_DISABLE_MASK 0x02000000
-#define BCHP_FPM_CTRL_FPM_FPM_CTL_MEM_CORRUPT_CHECK_DISABLE_SHIFT 25
-#define BCHP_FPM_CTRL_FPM_FPM_CTL_MEM_CORRUPT_CHECK_DISABLE_DEFAULT 0x00000000
-
-/* FPM_CTRL_FPM :: FPM_CTL :: STOP_ALLOC_CACHE_LOAD [24:24] */
-#define BCHP_FPM_CTRL_FPM_FPM_CTL_STOP_ALLOC_CACHE_LOAD_MASK 0x01000000
-#define BCHP_FPM_CTRL_FPM_FPM_CTL_STOP_ALLOC_CACHE_LOAD_SHIFT 24
-#define BCHP_FPM_CTRL_FPM_FPM_CTL_STOP_ALLOC_CACHE_LOAD_DEFAULT 0x00000000
-
-/* FPM_CTRL_FPM :: FPM_CTL :: reserved1 [23:17] */
-#define BCHP_FPM_CTRL_FPM_FPM_CTL_reserved1_MASK 0x00fe0000
-#define BCHP_FPM_CTRL_FPM_FPM_CTL_reserved1_SHIFT 17
-
-/* FPM_CTRL_FPM :: FPM_CTL :: POOL1_ENABLE [16:16] */
-#define BCHP_FPM_CTRL_FPM_FPM_CTL_POOL1_ENABLE_MASK 0x00010000
-#define BCHP_FPM_CTRL_FPM_FPM_CTL_POOL1_ENABLE_SHIFT 16
-#define BCHP_FPM_CTRL_FPM_FPM_CTL_POOL1_ENABLE_DEFAULT 0x00000000
-
-/* FPM_CTRL_FPM :: FPM_CTL :: STRICT_PRIORITY_REQUEST_TYPE [15:15] */
-#define BCHP_FPM_CTRL_FPM_FPM_CTL_STRICT_PRIORITY_REQUEST_TYPE_MASK 0x00008000
-#define BCHP_FPM_CTRL_FPM_FPM_CTL_STRICT_PRIORITY_REQUEST_TYPE_SHIFT 15
-#define BCHP_FPM_CTRL_FPM_FPM_CTL_STRICT_PRIORITY_REQUEST_TYPE_DEFAULT 0x00000000
-
-/* FPM_CTRL_FPM :: FPM_CTL :: reserved2 [14:14] */
-#define BCHP_FPM_CTRL_FPM_FPM_CTL_reserved2_MASK 0x00004000
-#define BCHP_FPM_CTRL_FPM_FPM_CTL_reserved2_SHIFT 14
-
-/* FPM_CTRL_FPM :: FPM_CTL :: WEIGHT_FOR_ROUND_ROBIN_POLICY [13:08] */
-#define BCHP_FPM_CTRL_FPM_FPM_CTL_WEIGHT_FOR_ROUND_ROBIN_POLICY_MASK 0x00003f00
-#define BCHP_FPM_CTRL_FPM_FPM_CTL_WEIGHT_FOR_ROUND_ROBIN_POLICY_SHIFT 8
-#define BCHP_FPM_CTRL_FPM_FPM_CTL_WEIGHT_FOR_ROUND_ROBIN_POLICY_DEFAULT 0x00000000
-
-/* FPM_CTRL_FPM :: FPM_CTL :: ARBITRATION_POLICY [07:05] */
-#define BCHP_FPM_CTRL_FPM_FPM_CTL_ARBITRATION_POLICY_MASK 0x000000e0
-#define BCHP_FPM_CTRL_FPM_FPM_CTL_ARBITRATION_POLICY_SHIFT 5
-#define BCHP_FPM_CTRL_FPM_FPM_CTL_ARBITRATION_POLICY_DEFAULT 0x00000000
-
-/* FPM_CTRL_FPM :: FPM_CTL :: INIT_MEM [04:04] */
-#define BCHP_FPM_CTRL_FPM_FPM_CTL_INIT_MEM_MASK 0x00000010
-#define BCHP_FPM_CTRL_FPM_FPM_CTL_INIT_MEM_SHIFT 4
-#define BCHP_FPM_CTRL_FPM_FPM_CTL_INIT_MEM_DEFAULT 0x00000000
-
-/* FPM_CTRL_FPM :: FPM_CTL :: reserved3 [03:00] */
-#define BCHP_FPM_CTRL_FPM_FPM_CTL_reserved3_MASK 0x0000000f
-#define BCHP_FPM_CTRL_FPM_FPM_CTL_reserved3_SHIFT 0
-
-/***************************************************************************
- *FPM_CFG1 - FPM Configuration Register
- ***************************************************************************/
-/* FPM_CTRL_FPM :: FPM_CFG1 :: reserved0 [31:08] */
-#define BCHP_FPM_CTRL_FPM_FPM_CFG1_reserved0_MASK 0xffffff00
-#define BCHP_FPM_CTRL_FPM_FPM_CFG1_reserved0_SHIFT 8
-
-/* FPM_CTRL_FPM :: FPM_CFG1 :: POOL4_CACHE_BYPASS_EN [07:07] */
-#define BCHP_FPM_CTRL_FPM_FPM_CFG1_POOL4_CACHE_BYPASS_EN_MASK 0x00000080
-#define BCHP_FPM_CTRL_FPM_FPM_CFG1_POOL4_CACHE_BYPASS_EN_SHIFT 7
-#define BCHP_FPM_CTRL_FPM_FPM_CFG1_POOL4_CACHE_BYPASS_EN_DEFAULT 0x00000000
-
-/* FPM_CTRL_FPM :: FPM_CFG1 :: POOL3_CACHE_BYPASS_EN [06:06] */
-#define BCHP_FPM_CTRL_FPM_FPM_CFG1_POOL3_CACHE_BYPASS_EN_MASK 0x00000040
-#define BCHP_FPM_CTRL_FPM_FPM_CFG1_POOL3_CACHE_BYPASS_EN_SHIFT 6
-#define BCHP_FPM_CTRL_FPM_FPM_CFG1_POOL3_CACHE_BYPASS_EN_DEFAULT 0x00000000
-
-/* FPM_CTRL_FPM :: FPM_CFG1 :: POOL2_CACHE_BYPASS_EN [05:05] */
-#define BCHP_FPM_CTRL_FPM_FPM_CFG1_POOL2_CACHE_BYPASS_EN_MASK 0x00000020
-#define BCHP_FPM_CTRL_FPM_FPM_CFG1_POOL2_CACHE_BYPASS_EN_SHIFT 5
-#define BCHP_FPM_CTRL_FPM_FPM_CFG1_POOL2_CACHE_BYPASS_EN_DEFAULT 0x00000000
-
-/* FPM_CTRL_FPM :: FPM_CFG1 :: POOL1_CACHE_BYPASS_EN [04:04] */
-#define BCHP_FPM_CTRL_FPM_FPM_CFG1_POOL1_CACHE_BYPASS_EN_MASK 0x00000010
-#define BCHP_FPM_CTRL_FPM_FPM_CFG1_POOL1_CACHE_BYPASS_EN_SHIFT 4
-#define BCHP_FPM_CTRL_FPM_FPM_CFG1_POOL1_CACHE_BYPASS_EN_DEFAULT 0x00000000
-
-/* FPM_CTRL_FPM :: FPM_CFG1 :: POOL4_SEARCH_MODE [03:03] */
-#define BCHP_FPM_CTRL_FPM_FPM_CFG1_POOL4_SEARCH_MODE_MASK 0x00000008
-#define BCHP_FPM_CTRL_FPM_FPM_CFG1_POOL4_SEARCH_MODE_SHIFT 3
-#define BCHP_FPM_CTRL_FPM_FPM_CFG1_POOL4_SEARCH_MODE_DEFAULT 0x00000000
-
-/* FPM_CTRL_FPM :: FPM_CFG1 :: POOL3_SEARCH_MODE [02:02] */
-#define BCHP_FPM_CTRL_FPM_FPM_CFG1_POOL3_SEARCH_MODE_MASK 0x00000004
-#define BCHP_FPM_CTRL_FPM_FPM_CFG1_POOL3_SEARCH_MODE_SHIFT 2
-#define BCHP_FPM_CTRL_FPM_FPM_CFG1_POOL3_SEARCH_MODE_DEFAULT 0x00000000
-
-/* FPM_CTRL_FPM :: FPM_CFG1 :: POOL2_SEARCH_MODE [01:01] */
-#define BCHP_FPM_CTRL_FPM_FPM_CFG1_POOL2_SEARCH_MODE_MASK 0x00000002
-#define BCHP_FPM_CTRL_FPM_FPM_CFG1_POOL2_SEARCH_MODE_SHIFT 1
-#define BCHP_FPM_CTRL_FPM_FPM_CFG1_POOL2_SEARCH_MODE_DEFAULT 0x00000000
-
-/* FPM_CTRL_FPM :: FPM_CFG1 :: POOL1_SEARCH_MODE [00:00] */
-#define BCHP_FPM_CTRL_FPM_FPM_CFG1_POOL1_SEARCH_MODE_MASK 0x00000001
-#define BCHP_FPM_CTRL_FPM_FPM_CFG1_POOL1_SEARCH_MODE_SHIFT 0
-#define BCHP_FPM_CTRL_FPM_FPM_CFG1_POOL1_SEARCH_MODE_DEFAULT 0x00000000
-
-/***************************************************************************
- *POOL1_INTR_MSK - POOL1 Interrupt Mask Register
- ***************************************************************************/
-/* FPM_CTRL_FPM :: POOL1_INTR_MSK :: reserved0 [31:13] */
-#define BCHP_FPM_CTRL_FPM_POOL1_INTR_MSK_reserved0_MASK 0xffffe000
-#define BCHP_FPM_CTRL_FPM_POOL1_INTR_MSK_reserved0_SHIFT 13
-
-/* FPM_CTRL_FPM :: POOL1_INTR_MSK :: ILLEGAL_ALLOC_REQUEST_MSK [12:12] */
-#define BCHP_FPM_CTRL_FPM_POOL1_INTR_MSK_ILLEGAL_ALLOC_REQUEST_MSK_MASK 0x00001000
-#define BCHP_FPM_CTRL_FPM_POOL1_INTR_MSK_ILLEGAL_ALLOC_REQUEST_MSK_SHIFT 12
-#define BCHP_FPM_CTRL_FPM_POOL1_INTR_MSK_ILLEGAL_ALLOC_REQUEST_MSK_DEFAULT 0x00000000
-
-/* FPM_CTRL_FPM :: POOL1_INTR_MSK :: ILLEGAL_ADDRESS_ACCESS_MSK [11:11] */
-#define BCHP_FPM_CTRL_FPM_POOL1_INTR_MSK_ILLEGAL_ADDRESS_ACCESS_MSK_MASK 0x00000800
-#define BCHP_FPM_CTRL_FPM_POOL1_INTR_MSK_ILLEGAL_ADDRESS_ACCESS_MSK_SHIFT 11
-#define BCHP_FPM_CTRL_FPM_POOL1_INTR_MSK_ILLEGAL_ADDRESS_ACCESS_MSK_DEFAULT 0x00000000
-
-/* FPM_CTRL_FPM :: POOL1_INTR_MSK :: XON_MSK [10:10] */
-#define BCHP_FPM_CTRL_FPM_POOL1_INTR_MSK_XON_MSK_MASK 0x00000400
-#define BCHP_FPM_CTRL_FPM_POOL1_INTR_MSK_XON_MSK_SHIFT 10
-#define BCHP_FPM_CTRL_FPM_POOL1_INTR_MSK_XON_MSK_DEFAULT 0x00000000
-
-/* FPM_CTRL_FPM :: POOL1_INTR_MSK :: XOFF_MSK [09:09] */
-#define BCHP_FPM_CTRL_FPM_POOL1_INTR_MSK_XOFF_MSK_MASK 0x00000200
-#define BCHP_FPM_CTRL_FPM_POOL1_INTR_MSK_XOFF_MSK_SHIFT 9
-#define BCHP_FPM_CTRL_FPM_POOL1_INTR_MSK_XOFF_MSK_DEFAULT 0x00000000
-
-/* FPM_CTRL_FPM :: POOL1_INTR_MSK :: MEMORY_CORRUPT_MSK [08:08] */
-#define BCHP_FPM_CTRL_FPM_POOL1_INTR_MSK_MEMORY_CORRUPT_MSK_MASK 0x00000100
-#define BCHP_FPM_CTRL_FPM_POOL1_INTR_MSK_MEMORY_CORRUPT_MSK_SHIFT 8
-#define BCHP_FPM_CTRL_FPM_POOL1_INTR_MSK_MEMORY_CORRUPT_MSK_DEFAULT 0x00000000
-
-/* FPM_CTRL_FPM :: POOL1_INTR_MSK :: POOL_DIS_FREE_MULTI_MSK [07:07] */
-#define BCHP_FPM_CTRL_FPM_POOL1_INTR_MSK_POOL_DIS_FREE_MULTI_MSK_MASK 0x00000080
-#define BCHP_FPM_CTRL_FPM_POOL1_INTR_MSK_POOL_DIS_FREE_MULTI_MSK_SHIFT 7
-#define BCHP_FPM_CTRL_FPM_POOL1_INTR_MSK_POOL_DIS_FREE_MULTI_MSK_DEFAULT 0x00000000
-
-/* FPM_CTRL_FPM :: POOL1_INTR_MSK :: MULTI_TOKEN_INDEX_OUT_OF_RANGE_MSK [06:06] */
-#define BCHP_FPM_CTRL_FPM_POOL1_INTR_MSK_MULTI_TOKEN_INDEX_OUT_OF_RANGE_MSK_MASK 0x00000040
-#define BCHP_FPM_CTRL_FPM_POOL1_INTR_MSK_MULTI_TOKEN_INDEX_OUT_OF_RANGE_MSK_SHIFT 6
-#define BCHP_FPM_CTRL_FPM_POOL1_INTR_MSK_MULTI_TOKEN_INDEX_OUT_OF_RANGE_MSK_DEFAULT 0x00000000
-
-/* FPM_CTRL_FPM :: POOL1_INTR_MSK :: MULTI_TOKEN_NO_VALID_MSK [05:05] */
-#define BCHP_FPM_CTRL_FPM_POOL1_INTR_MSK_MULTI_TOKEN_NO_VALID_MSK_MASK 0x00000020
-#define BCHP_FPM_CTRL_FPM_POOL1_INTR_MSK_MULTI_TOKEN_NO_VALID_MSK_SHIFT 5
-#define BCHP_FPM_CTRL_FPM_POOL1_INTR_MSK_MULTI_TOKEN_NO_VALID_MSK_DEFAULT 0x00000000
-
-/* FPM_CTRL_FPM :: POOL1_INTR_MSK :: FREE_TOKEN_INDEX_OUT_OF_RANGE_MSK [04:04] */
-#define BCHP_FPM_CTRL_FPM_POOL1_INTR_MSK_FREE_TOKEN_INDEX_OUT_OF_RANGE_MSK_MASK 0x00000010
-#define BCHP_FPM_CTRL_FPM_POOL1_INTR_MSK_FREE_TOKEN_INDEX_OUT_OF_RANGE_MSK_SHIFT 4
-#define BCHP_FPM_CTRL_FPM_POOL1_INTR_MSK_FREE_TOKEN_INDEX_OUT_OF_RANGE_MSK_DEFAULT 0x00000000
-
-/* FPM_CTRL_FPM :: POOL1_INTR_MSK :: FREE_TOKEN_NO_VALID_MSK [03:03] */
-#define BCHP_FPM_CTRL_FPM_POOL1_INTR_MSK_FREE_TOKEN_NO_VALID_MSK_MASK 0x00000008
-#define BCHP_FPM_CTRL_FPM_POOL1_INTR_MSK_FREE_TOKEN_NO_VALID_MSK_SHIFT 3
-#define BCHP_FPM_CTRL_FPM_POOL1_INTR_MSK_FREE_TOKEN_NO_VALID_MSK_DEFAULT 0x00000000
-
-/* FPM_CTRL_FPM :: POOL1_INTR_MSK :: POOL_FULL_MSK [02:02] */
-#define BCHP_FPM_CTRL_FPM_POOL1_INTR_MSK_POOL_FULL_MSK_MASK 0x00000004
-#define BCHP_FPM_CTRL_FPM_POOL1_INTR_MSK_POOL_FULL_MSK_SHIFT 2
-#define BCHP_FPM_CTRL_FPM_POOL1_INTR_MSK_POOL_FULL_MSK_DEFAULT 0x00000000
-
-/* FPM_CTRL_FPM :: POOL1_INTR_MSK :: FREE_FIFO_FULL_MSK [01:01] */
-#define BCHP_FPM_CTRL_FPM_POOL1_INTR_MSK_FREE_FIFO_FULL_MSK_MASK 0x00000002
-#define BCHP_FPM_CTRL_FPM_POOL1_INTR_MSK_FREE_FIFO_FULL_MSK_SHIFT 1
-#define BCHP_FPM_CTRL_FPM_POOL1_INTR_MSK_FREE_FIFO_FULL_MSK_DEFAULT 0x00000000
-
-/* FPM_CTRL_FPM :: POOL1_INTR_MSK :: ALLOC_FIFO_FULL_MSK [00:00] */
-#define BCHP_FPM_CTRL_FPM_POOL1_INTR_MSK_ALLOC_FIFO_FULL_MSK_MASK 0x00000001
-#define BCHP_FPM_CTRL_FPM_POOL1_INTR_MSK_ALLOC_FIFO_FULL_MSK_SHIFT 0
-#define BCHP_FPM_CTRL_FPM_POOL1_INTR_MSK_ALLOC_FIFO_FULL_MSK_DEFAULT 0x00000000
-
-/***************************************************************************
- *POOL1_INTR_STS - POOL1 Interrupt Status Register
- ***************************************************************************/
-/* FPM_CTRL_FPM :: POOL1_INTR_STS :: reserved0 [31:13] */
-#define BCHP_FPM_CTRL_FPM_POOL1_INTR_STS_reserved0_MASK 0xffffe000
-#define BCHP_FPM_CTRL_FPM_POOL1_INTR_STS_reserved0_SHIFT 13
-
-/* FPM_CTRL_FPM :: POOL1_INTR_STS :: ILLEGAL_ALLOC_REQUEST_STS [12:12] */
-#define BCHP_FPM_CTRL_FPM_POOL1_INTR_STS_ILLEGAL_ALLOC_REQUEST_STS_MASK 0x00001000
-#define BCHP_FPM_CTRL_FPM_POOL1_INTR_STS_ILLEGAL_ALLOC_REQUEST_STS_SHIFT 12
-#define BCHP_FPM_CTRL_FPM_POOL1_INTR_STS_ILLEGAL_ALLOC_REQUEST_STS_DEFAULT 0x00000000
-
-/* FPM_CTRL_FPM :: POOL1_INTR_STS :: ILLEGAL_ADDRESS_ACCESS_STS [11:11] */
-#define BCHP_FPM_CTRL_FPM_POOL1_INTR_STS_ILLEGAL_ADDRESS_ACCESS_STS_MASK 0x00000800
-#define BCHP_FPM_CTRL_FPM_POOL1_INTR_STS_ILLEGAL_ADDRESS_ACCESS_STS_SHIFT 11
-#define BCHP_FPM_CTRL_FPM_POOL1_INTR_STS_ILLEGAL_ADDRESS_ACCESS_STS_DEFAULT 0x00000000
-
-/* FPM_CTRL_FPM :: POOL1_INTR_STS :: XON_STATE_STS [10:10] */
-#define BCHP_FPM_CTRL_FPM_POOL1_INTR_STS_XON_STATE_STS_MASK 0x00000400
-#define BCHP_FPM_CTRL_FPM_POOL1_INTR_STS_XON_STATE_STS_SHIFT 10
-#define BCHP_FPM_CTRL_FPM_POOL1_INTR_STS_XON_STATE_STS_DEFAULT 0x00000000
-
-/* FPM_CTRL_FPM :: POOL1_INTR_STS :: XOFF_STATE_STS [09:09] */
-#define BCHP_FPM_CTRL_FPM_POOL1_INTR_STS_XOFF_STATE_STS_MASK 0x00000200
-#define BCHP_FPM_CTRL_FPM_POOL1_INTR_STS_XOFF_STATE_STS_SHIFT 9
-#define BCHP_FPM_CTRL_FPM_POOL1_INTR_STS_XOFF_STATE_STS_DEFAULT 0x00000000
-
-/* FPM_CTRL_FPM :: POOL1_INTR_STS :: MEMORY_CORRUPT_STS [08:08] */
-#define BCHP_FPM_CTRL_FPM_POOL1_INTR_STS_MEMORY_CORRUPT_STS_MASK 0x00000100
-#define BCHP_FPM_CTRL_FPM_POOL1_INTR_STS_MEMORY_CORRUPT_STS_SHIFT 8
-#define BCHP_FPM_CTRL_FPM_POOL1_INTR_STS_MEMORY_CORRUPT_STS_DEFAULT 0x00000000
-
-/* FPM_CTRL_FPM :: POOL1_INTR_STS :: POOL_DIS_FREE_MULTI_STS [07:07] */
-#define BCHP_FPM_CTRL_FPM_POOL1_INTR_STS_POOL_DIS_FREE_MULTI_STS_MASK 0x00000080
-#define BCHP_FPM_CTRL_FPM_POOL1_INTR_STS_POOL_DIS_FREE_MULTI_STS_SHIFT 7
-#define BCHP_FPM_CTRL_FPM_POOL1_INTR_STS_POOL_DIS_FREE_MULTI_STS_DEFAULT 0x00000000
-
-/* FPM_CTRL_FPM :: POOL1_INTR_STS :: MULTI_TOKEN_INDEX_OUT_OF_RANGE_STS [06:06] */
-#define BCHP_FPM_CTRL_FPM_POOL1_INTR_STS_MULTI_TOKEN_INDEX_OUT_OF_RANGE_STS_MASK 0x00000040
-#define BCHP_FPM_CTRL_FPM_POOL1_INTR_STS_MULTI_TOKEN_INDEX_OUT_OF_RANGE_STS_SHIFT 6
-#define BCHP_FPM_CTRL_FPM_POOL1_INTR_STS_MULTI_TOKEN_INDEX_OUT_OF_RANGE_STS_DEFAULT 0x00000000
-
-/* FPM_CTRL_FPM :: POOL1_INTR_STS :: MULTI_TOKEN_NO_VALID_STS [05:05] */
-#define BCHP_FPM_CTRL_FPM_POOL1_INTR_STS_MULTI_TOKEN_NO_VALID_STS_MASK 0x00000020
-#define BCHP_FPM_CTRL_FPM_POOL1_INTR_STS_MULTI_TOKEN_NO_VALID_STS_SHIFT 5
-#define BCHP_FPM_CTRL_FPM_POOL1_INTR_STS_MULTI_TOKEN_NO_VALID_STS_DEFAULT 0x00000000
-
-/* FPM_CTRL_FPM :: POOL1_INTR_STS :: FREE_TOKEN_INDEX_OUT_OF_RANGE_STS [04:04] */
-#define BCHP_FPM_CTRL_FPM_POOL1_INTR_STS_FREE_TOKEN_INDEX_OUT_OF_RANGE_STS_MASK 0x00000010
-#define BCHP_FPM_CTRL_FPM_POOL1_INTR_STS_FREE_TOKEN_INDEX_OUT_OF_RANGE_STS_SHIFT 4
-#define BCHP_FPM_CTRL_FPM_POOL1_INTR_STS_FREE_TOKEN_INDEX_OUT_OF_RANGE_STS_DEFAULT 0x00000000
-
-/* FPM_CTRL_FPM :: POOL1_INTR_STS :: FREE_TOKEN_NO_VALID_STS [03:03] */
-#define BCHP_FPM_CTRL_FPM_POOL1_INTR_STS_FREE_TOKEN_NO_VALID_STS_MASK 0x00000008
-#define BCHP_FPM_CTRL_FPM_POOL1_INTR_STS_FREE_TOKEN_NO_VALID_STS_SHIFT 3
-#define BCHP_FPM_CTRL_FPM_POOL1_INTR_STS_FREE_TOKEN_NO_VALID_STS_DEFAULT 0x00000000
-
-/* FPM_CTRL_FPM :: POOL1_INTR_STS :: POOL_FULL_STS [02:02] */
-#define BCHP_FPM_CTRL_FPM_POOL1_INTR_STS_POOL_FULL_STS_MASK 0x00000004
-#define BCHP_FPM_CTRL_FPM_POOL1_INTR_STS_POOL_FULL_STS_SHIFT 2
-#define BCHP_FPM_CTRL_FPM_POOL1_INTR_STS_POOL_FULL_STS_DEFAULT 0x00000000
-
-/* FPM_CTRL_FPM :: POOL1_INTR_STS :: FREE_FIFO_FULL_STS [01:01] */
-#define BCHP_FPM_CTRL_FPM_POOL1_INTR_STS_FREE_FIFO_FULL_STS_MASK 0x00000002
-#define BCHP_FPM_CTRL_FPM_POOL1_INTR_STS_FREE_FIFO_FULL_STS_SHIFT 1
-#define BCHP_FPM_CTRL_FPM_POOL1_INTR_STS_FREE_FIFO_FULL_STS_DEFAULT 0x00000000
-
-/* FPM_CTRL_FPM :: POOL1_INTR_STS :: ALLOC_FIFO_FULL_STS [00:00] */
-#define BCHP_FPM_CTRL_FPM_POOL1_INTR_STS_ALLOC_FIFO_FULL_STS_MASK 0x00000001
-#define BCHP_FPM_CTRL_FPM_POOL1_INTR_STS_ALLOC_FIFO_FULL_STS_SHIFT 0
-#define BCHP_FPM_CTRL_FPM_POOL1_INTR_STS_ALLOC_FIFO_FULL_STS_DEFAULT 0x00000000
-
-/***************************************************************************
- *POOL1_STALL_MSK - POOL1 Stall FPM mask
- ***************************************************************************/
-/* FPM_CTRL_FPM :: POOL1_STALL_MSK :: reserved0 [31:09] */
-#define BCHP_FPM_CTRL_FPM_POOL1_STALL_MSK_reserved0_MASK 0xfffffe00
-#define BCHP_FPM_CTRL_FPM_POOL1_STALL_MSK_reserved0_SHIFT 9
-
-/* FPM_CTRL_FPM :: POOL1_STALL_MSK :: MEMORY_CORRUPT_STALL_MSK [08:08] */
-#define BCHP_FPM_CTRL_FPM_POOL1_STALL_MSK_MEMORY_CORRUPT_STALL_MSK_MASK 0x00000100
-#define BCHP_FPM_CTRL_FPM_POOL1_STALL_MSK_MEMORY_CORRUPT_STALL_MSK_SHIFT 8
-#define BCHP_FPM_CTRL_FPM_POOL1_STALL_MSK_MEMORY_CORRUPT_STALL_MSK_DEFAULT 0x00000000
-
-/* FPM_CTRL_FPM :: POOL1_STALL_MSK :: reserved1 [07:07] */
-#define BCHP_FPM_CTRL_FPM_POOL1_STALL_MSK_reserved1_MASK 0x00000080
-#define BCHP_FPM_CTRL_FPM_POOL1_STALL_MSK_reserved1_SHIFT 7
-
-/* FPM_CTRL_FPM :: POOL1_STALL_MSK :: MULTI_TOKEN_INDEX_OUT_OF_RANGE_STALL_MSK [06:06] */
-#define BCHP_FPM_CTRL_FPM_POOL1_STALL_MSK_MULTI_TOKEN_INDEX_OUT_OF_RANGE_STALL_MSK_MASK 0x00000040
-#define BCHP_FPM_CTRL_FPM_POOL1_STALL_MSK_MULTI_TOKEN_INDEX_OUT_OF_RANGE_STALL_MSK_SHIFT 6
-#define BCHP_FPM_CTRL_FPM_POOL1_STALL_MSK_MULTI_TOKEN_INDEX_OUT_OF_RANGE_STALL_MSK_DEFAULT 0x00000000
-
-/* FPM_CTRL_FPM :: POOL1_STALL_MSK :: MULTI_TOKEN_NO_VALID_STALL_MSK [05:05] */
-#define BCHP_FPM_CTRL_FPM_POOL1_STALL_MSK_MULTI_TOKEN_NO_VALID_STALL_MSK_MASK 0x00000020
-#define BCHP_FPM_CTRL_FPM_POOL1_STALL_MSK_MULTI_TOKEN_NO_VALID_STALL_MSK_SHIFT 5
-#define BCHP_FPM_CTRL_FPM_POOL1_STALL_MSK_MULTI_TOKEN_NO_VALID_STALL_MSK_DEFAULT 0x00000000
-
-/* FPM_CTRL_FPM :: POOL1_STALL_MSK :: FREE_TOKEN_INDEX_OUT_OF_RANGE_STALL_MSK [04:04] */
-#define BCHP_FPM_CTRL_FPM_POOL1_STALL_MSK_FREE_TOKEN_INDEX_OUT_OF_RANGE_STALL_MSK_MASK 0x00000010
-#define BCHP_FPM_CTRL_FPM_POOL1_STALL_MSK_FREE_TOKEN_INDEX_OUT_OF_RANGE_STALL_MSK_SHIFT 4
-#define BCHP_FPM_CTRL_FPM_POOL1_STALL_MSK_FREE_TOKEN_INDEX_OUT_OF_RANGE_STALL_MSK_DEFAULT 0x00000000
-
-/* FPM_CTRL_FPM :: POOL1_STALL_MSK :: FREE_TOKEN_NO_VALID_STALL_MSK [03:03] */
-#define BCHP_FPM_CTRL_FPM_POOL1_STALL_MSK_FREE_TOKEN_NO_VALID_STALL_MSK_MASK 0x00000008
-#define BCHP_FPM_CTRL_FPM_POOL1_STALL_MSK_FREE_TOKEN_NO_VALID_STALL_MSK_SHIFT 3
-#define BCHP_FPM_CTRL_FPM_POOL1_STALL_MSK_FREE_TOKEN_NO_VALID_STALL_MSK_DEFAULT 0x00000000
-
-/* FPM_CTRL_FPM :: POOL1_STALL_MSK :: reserved2 [02:00] */
-#define BCHP_FPM_CTRL_FPM_POOL1_STALL_MSK_reserved2_MASK 0x00000007
-#define BCHP_FPM_CTRL_FPM_POOL1_STALL_MSK_reserved2_SHIFT 0
-
-/***************************************************************************
- *POOL1_CFG1 - POOL1 Configuration Register 1
- ***************************************************************************/
-/* FPM_CTRL_FPM :: POOL1_CFG1 :: reserved0 [31:27] */
-#define BCHP_FPM_CTRL_FPM_POOL1_CFG1_reserved0_MASK 0xf8000000
-#define BCHP_FPM_CTRL_FPM_POOL1_CFG1_reserved0_SHIFT 27
-
-/* FPM_CTRL_FPM :: POOL1_CFG1 :: FP_BUF_SIZE [26:24] */
-#define BCHP_FPM_CTRL_FPM_POOL1_CFG1_FP_BUF_SIZE_MASK 0x07000000
-#define BCHP_FPM_CTRL_FPM_POOL1_CFG1_FP_BUF_SIZE_SHIFT 24
-#define BCHP_FPM_CTRL_FPM_POOL1_CFG1_FP_BUF_SIZE_DEFAULT 0x00000006
-#define BCHP_FPM_CTRL_FPM_POOL1_CFG1_FP_BUF_SIZE_BUF512 0
-#define BCHP_FPM_CTRL_FPM_POOL1_CFG1_FP_BUF_SIZE_BUF768 1
-#define BCHP_FPM_CTRL_FPM_POOL1_CFG1_FP_BUF_SIZE_BUF1024 2
-#define BCHP_FPM_CTRL_FPM_POOL1_CFG1_FP_BUF_SIZE_BUF1280 3
-#define BCHP_FPM_CTRL_FPM_POOL1_CFG1_FP_BUF_SIZE_BUF1536 4
-#define BCHP_FPM_CTRL_FPM_POOL1_CFG1_FP_BUF_SIZE_BUF1792 5
-#define BCHP_FPM_CTRL_FPM_POOL1_CFG1_FP_BUF_SIZE_BUF2048 6
-#define BCHP_FPM_CTRL_FPM_POOL1_CFG1_FP_BUF_SIZE_BUF2304 7
-
-/* FPM_CTRL_FPM :: POOL1_CFG1 :: reserved1 [23:00] */
-#define BCHP_FPM_CTRL_FPM_POOL1_CFG1_reserved1_MASK 0x00ffffff
-#define BCHP_FPM_CTRL_FPM_POOL1_CFG1_reserved1_SHIFT 0
-
-/***************************************************************************
- *POOL1_CFG2 - POOL1 Configuration Register 2
- ***************************************************************************/
-/* FPM_CTRL_FPM :: POOL1_CFG2 :: POOL_BASE_ADDRESS [31:02] */
-#define BCHP_FPM_CTRL_FPM_POOL1_CFG2_POOL_BASE_ADDRESS_MASK 0xfffffffc
-#define BCHP_FPM_CTRL_FPM_POOL1_CFG2_POOL_BASE_ADDRESS_SHIFT 2
-#define BCHP_FPM_CTRL_FPM_POOL1_CFG2_POOL_BASE_ADDRESS_DEFAULT 0x00000000
-
-/* FPM_CTRL_FPM :: POOL1_CFG2 :: reserved0 [01:00] */
-#define BCHP_FPM_CTRL_FPM_POOL1_CFG2_reserved0_MASK 0x00000003
-#define BCHP_FPM_CTRL_FPM_POOL1_CFG2_reserved0_SHIFT 0
-
-/***************************************************************************
- *POOL1_CFG3 - POOL1 Configuration Register 3
- ***************************************************************************/
-/* FPM_CTRL_FPM :: POOL1_CFG3 :: POOL_SEL [31:00] */
-#define BCHP_FPM_CTRL_FPM_POOL1_CFG3_POOL_SEL_MASK 0xffffffff
-#define BCHP_FPM_CTRL_FPM_POOL1_CFG3_POOL_SEL_SHIFT 0
-#define BCHP_FPM_CTRL_FPM_POOL1_CFG3_POOL_SEL_DEFAULT 0x00000001
-
-/***************************************************************************
- *POOL1_STAT1 - POOL1 Status Register 1
- ***************************************************************************/
-/* FPM_CTRL_FPM :: POOL1_STAT1 :: OVRFL [31:16] */
-#define BCHP_FPM_CTRL_FPM_POOL1_STAT1_OVRFL_MASK 0xffff0000
-#define BCHP_FPM_CTRL_FPM_POOL1_STAT1_OVRFL_SHIFT 16
-#define BCHP_FPM_CTRL_FPM_POOL1_STAT1_OVRFL_DEFAULT 0x00000000
-
-/* FPM_CTRL_FPM :: POOL1_STAT1 :: UNDRFL [15:00] */
-#define BCHP_FPM_CTRL_FPM_POOL1_STAT1_UNDRFL_MASK 0x0000ffff
-#define BCHP_FPM_CTRL_FPM_POOL1_STAT1_UNDRFL_SHIFT 0
-#define BCHP_FPM_CTRL_FPM_POOL1_STAT1_UNDRFL_DEFAULT 0x00000000
-
-/***************************************************************************
- *POOL1_STAT2 - POOL1 Status Register 2
- ***************************************************************************/
-/* FPM_CTRL_FPM :: POOL1_STAT2 :: POOL_FULL [31:31] */
-#define BCHP_FPM_CTRL_FPM_POOL1_STAT2_POOL_FULL_MASK 0x80000000
-#define BCHP_FPM_CTRL_FPM_POOL1_STAT2_POOL_FULL_SHIFT 31
-#define BCHP_FPM_CTRL_FPM_POOL1_STAT2_POOL_FULL_DEFAULT 0x00000000
-
-/* FPM_CTRL_FPM :: POOL1_STAT2 :: reserved0 [30:30] */
-#define BCHP_FPM_CTRL_FPM_POOL1_STAT2_reserved0_MASK 0x40000000
-#define BCHP_FPM_CTRL_FPM_POOL1_STAT2_reserved0_SHIFT 30
-
-/* FPM_CTRL_FPM :: POOL1_STAT2 :: FREE_FIFO_FULL [29:29] */
-#define BCHP_FPM_CTRL_FPM_POOL1_STAT2_FREE_FIFO_FULL_MASK 0x20000000
-#define BCHP_FPM_CTRL_FPM_POOL1_STAT2_FREE_FIFO_FULL_SHIFT 29
-#define BCHP_FPM_CTRL_FPM_POOL1_STAT2_FREE_FIFO_FULL_DEFAULT 0x00000000
-
-/* FPM_CTRL_FPM :: POOL1_STAT2 :: FREE_FIFO_EMPTY [28:28] */
-#define BCHP_FPM_CTRL_FPM_POOL1_STAT2_FREE_FIFO_EMPTY_MASK 0x10000000
-#define BCHP_FPM_CTRL_FPM_POOL1_STAT2_FREE_FIFO_EMPTY_SHIFT 28
-#define BCHP_FPM_CTRL_FPM_POOL1_STAT2_FREE_FIFO_EMPTY_DEFAULT 0x00000001
-
-/* FPM_CTRL_FPM :: POOL1_STAT2 :: ALLOC_FIFO_FULL [27:27] */
-#define BCHP_FPM_CTRL_FPM_POOL1_STAT2_ALLOC_FIFO_FULL_MASK 0x08000000
-#define BCHP_FPM_CTRL_FPM_POOL1_STAT2_ALLOC_FIFO_FULL_SHIFT 27
-#define BCHP_FPM_CTRL_FPM_POOL1_STAT2_ALLOC_FIFO_FULL_DEFAULT 0x00000000
-
-/* FPM_CTRL_FPM :: POOL1_STAT2 :: ALLOC_FIFO_EMPTY [26:26] */
-#define BCHP_FPM_CTRL_FPM_POOL1_STAT2_ALLOC_FIFO_EMPTY_MASK 0x04000000
-#define BCHP_FPM_CTRL_FPM_POOL1_STAT2_ALLOC_FIFO_EMPTY_SHIFT 26
-#define BCHP_FPM_CTRL_FPM_POOL1_STAT2_ALLOC_FIFO_EMPTY_DEFAULT 0x00000001
-
-/* FPM_CTRL_FPM :: POOL1_STAT2 :: reserved1 [25:18] */
-#define BCHP_FPM_CTRL_FPM_POOL1_STAT2_reserved1_MASK 0x03fc0000
-#define BCHP_FPM_CTRL_FPM_POOL1_STAT2_reserved1_SHIFT 18
-
-/* FPM_CTRL_FPM :: POOL1_STAT2 :: NUM_OF_TOKENS_AVAILABLE [17:00] */
-#define BCHP_FPM_CTRL_FPM_POOL1_STAT2_NUM_OF_TOKENS_AVAILABLE_MASK 0x0003ffff
-#define BCHP_FPM_CTRL_FPM_POOL1_STAT2_NUM_OF_TOKENS_AVAILABLE_SHIFT 0
-#define BCHP_FPM_CTRL_FPM_POOL1_STAT2_NUM_OF_TOKENS_AVAILABLE_DEFAULT 0x00010000
-
-/***************************************************************************
- *POOL1_STAT3 - POOL1 Status Register 3
- ***************************************************************************/
-/* FPM_CTRL_FPM :: POOL1_STAT3 :: reserved0 [31:18] */
-#define BCHP_FPM_CTRL_FPM_POOL1_STAT3_reserved0_MASK 0xfffc0000
-#define BCHP_FPM_CTRL_FPM_POOL1_STAT3_reserved0_SHIFT 18
-
-/* FPM_CTRL_FPM :: POOL1_STAT3 :: NUM_OF_NOT_VALID_TOKEN_FREES [17:00] */
-#define BCHP_FPM_CTRL_FPM_POOL1_STAT3_NUM_OF_NOT_VALID_TOKEN_FREES_MASK 0x0003ffff
-#define BCHP_FPM_CTRL_FPM_POOL1_STAT3_NUM_OF_NOT_VALID_TOKEN_FREES_SHIFT 0
-#define BCHP_FPM_CTRL_FPM_POOL1_STAT3_NUM_OF_NOT_VALID_TOKEN_FREES_DEFAULT 0x00000000
-
-/***************************************************************************
- *POOL1_STAT4 - POOL1 Status Register 4
- ***************************************************************************/
-/* FPM_CTRL_FPM :: POOL1_STAT4 :: reserved0 [31:18] */
-#define BCHP_FPM_CTRL_FPM_POOL1_STAT4_reserved0_MASK 0xfffc0000
-#define BCHP_FPM_CTRL_FPM_POOL1_STAT4_reserved0_SHIFT 18
-
-/* FPM_CTRL_FPM :: POOL1_STAT4 :: NUM_OF_NOT_VALID_TOKEN_MULTI [17:00] */
-#define BCHP_FPM_CTRL_FPM_POOL1_STAT4_NUM_OF_NOT_VALID_TOKEN_MULTI_MASK 0x0003ffff
-#define BCHP_FPM_CTRL_FPM_POOL1_STAT4_NUM_OF_NOT_VALID_TOKEN_MULTI_SHIFT 0
-#define BCHP_FPM_CTRL_FPM_POOL1_STAT4_NUM_OF_NOT_VALID_TOKEN_MULTI_DEFAULT 0x00000000
-
-/***************************************************************************
- *POOL1_STAT5 - POOL1 Status Register 5
- ***************************************************************************/
-/* FPM_CTRL_FPM :: POOL1_STAT5 :: MEM_CORRUPT_STS_RELATED_ALLOC_TOKEN_VALID [31:31] */
-#define BCHP_FPM_CTRL_FPM_POOL1_STAT5_MEM_CORRUPT_STS_RELATED_ALLOC_TOKEN_VALID_MASK 0x80000000
-#define BCHP_FPM_CTRL_FPM_POOL1_STAT5_MEM_CORRUPT_STS_RELATED_ALLOC_TOKEN_VALID_SHIFT 31
-#define BCHP_FPM_CTRL_FPM_POOL1_STAT5_MEM_CORRUPT_STS_RELATED_ALLOC_TOKEN_VALID_DEFAULT 0x00000000
-
-/* FPM_CTRL_FPM :: POOL1_STAT5 :: MEM_CORRUPT_STS_RELATED_ALLOC_TOKEN [30:00] */
-#define BCHP_FPM_CTRL_FPM_POOL1_STAT5_MEM_CORRUPT_STS_RELATED_ALLOC_TOKEN_MASK 0x7fffffff
-#define BCHP_FPM_CTRL_FPM_POOL1_STAT5_MEM_CORRUPT_STS_RELATED_ALLOC_TOKEN_SHIFT 0
-#define BCHP_FPM_CTRL_FPM_POOL1_STAT5_MEM_CORRUPT_STS_RELATED_ALLOC_TOKEN_DEFAULT 0x00000000
-
-/***************************************************************************
- *POOL1_STAT6 - POOL1 Status Register 6
- ***************************************************************************/
-/* FPM_CTRL_FPM :: POOL1_STAT6 :: INVALID_FREE_TOKEN_VALID [31:31] */
-#define BCHP_FPM_CTRL_FPM_POOL1_STAT6_INVALID_FREE_TOKEN_VALID_MASK 0x80000000
-#define BCHP_FPM_CTRL_FPM_POOL1_STAT6_INVALID_FREE_TOKEN_VALID_SHIFT 31
-#define BCHP_FPM_CTRL_FPM_POOL1_STAT6_INVALID_FREE_TOKEN_VALID_DEFAULT 0x00000000
-
-/* FPM_CTRL_FPM :: POOL1_STAT6 :: INVALID_FREE_TOKEN [30:00] */
-#define BCHP_FPM_CTRL_FPM_POOL1_STAT6_INVALID_FREE_TOKEN_MASK 0x7fffffff
-#define BCHP_FPM_CTRL_FPM_POOL1_STAT6_INVALID_FREE_TOKEN_SHIFT 0
-#define BCHP_FPM_CTRL_FPM_POOL1_STAT6_INVALID_FREE_TOKEN_DEFAULT 0x00000000
-
-/***************************************************************************
- *POOL1_STAT7 - POOL1 Status Register 7
- ***************************************************************************/
-/* FPM_CTRL_FPM :: POOL1_STAT7 :: INVALID_MCAST_TOKEN_VALID [31:31] */
-#define BCHP_FPM_CTRL_FPM_POOL1_STAT7_INVALID_MCAST_TOKEN_VALID_MASK 0x80000000
-#define BCHP_FPM_CTRL_FPM_POOL1_STAT7_INVALID_MCAST_TOKEN_VALID_SHIFT 31
-#define BCHP_FPM_CTRL_FPM_POOL1_STAT7_INVALID_MCAST_TOKEN_VALID_DEFAULT 0x00000000
-
-/* FPM_CTRL_FPM :: POOL1_STAT7 :: INVALID_MCAST_TOKEN [30:00] */
-#define BCHP_FPM_CTRL_FPM_POOL1_STAT7_INVALID_MCAST_TOKEN_MASK 0x7fffffff
-#define BCHP_FPM_CTRL_FPM_POOL1_STAT7_INVALID_MCAST_TOKEN_SHIFT 0
-#define BCHP_FPM_CTRL_FPM_POOL1_STAT7_INVALID_MCAST_TOKEN_DEFAULT 0x00000000
-
-/***************************************************************************
- *POOL1_XON_XOFF_CFG - POOL1 XON/XOFF Threshold Configuration Register
- ***************************************************************************/
-/* FPM_CTRL_FPM :: POOL1_XON_XOFF_CFG :: XON_THRESHOLD [31:16] */
-#define BCHP_FPM_CTRL_FPM_POOL1_XON_XOFF_CFG_XON_THRESHOLD_MASK 0xffff0000
-#define BCHP_FPM_CTRL_FPM_POOL1_XON_XOFF_CFG_XON_THRESHOLD_SHIFT 16
-#define BCHP_FPM_CTRL_FPM_POOL1_XON_XOFF_CFG_XON_THRESHOLD_DEFAULT 0x00000040
-
-/* FPM_CTRL_FPM :: POOL1_XON_XOFF_CFG :: XOFF_THRESHOLD [15:00] */
-#define BCHP_FPM_CTRL_FPM_POOL1_XON_XOFF_CFG_XOFF_THRESHOLD_MASK 0x0000ffff
-#define BCHP_FPM_CTRL_FPM_POOL1_XON_XOFF_CFG_XOFF_THRESHOLD_SHIFT 0
-#define BCHP_FPM_CTRL_FPM_POOL1_XON_XOFF_CFG_XOFF_THRESHOLD_DEFAULT 0x00000030
-
-/***************************************************************************
- *MEM_CTL - Back door Memory Access Control Register
- ***************************************************************************/
-/* FPM_CTRL_FPM :: MEM_CTL :: MEM_WR [31:31] */
-#define BCHP_FPM_CTRL_FPM_MEM_CTL_MEM_WR_MASK 0x80000000
-#define BCHP_FPM_CTRL_FPM_MEM_CTL_MEM_WR_SHIFT 31
-#define BCHP_FPM_CTRL_FPM_MEM_CTL_MEM_WR_DEFAULT 0x00000000
-
-/* FPM_CTRL_FPM :: MEM_CTL :: MEM_RD [30:30] */
-#define BCHP_FPM_CTRL_FPM_MEM_CTL_MEM_RD_MASK 0x40000000
-#define BCHP_FPM_CTRL_FPM_MEM_CTL_MEM_RD_SHIFT 30
-#define BCHP_FPM_CTRL_FPM_MEM_CTL_MEM_RD_DEFAULT 0x00000000
-
-/* FPM_CTRL_FPM :: MEM_CTL :: MEM_SEL [29:28] */
-#define BCHP_FPM_CTRL_FPM_MEM_CTL_MEM_SEL_MASK 0x30000000
-#define BCHP_FPM_CTRL_FPM_MEM_CTL_MEM_SEL_SHIFT 28
-#define BCHP_FPM_CTRL_FPM_MEM_CTL_MEM_SEL_DEFAULT 0x00000000
-
-/* FPM_CTRL_FPM :: MEM_CTL :: reserved0 [27:18] */
-#define BCHP_FPM_CTRL_FPM_MEM_CTL_reserved0_MASK 0x0ffc0000
-#define BCHP_FPM_CTRL_FPM_MEM_CTL_reserved0_SHIFT 18
-
-/* FPM_CTRL_FPM :: MEM_CTL :: MEM_ADDR [17:02] */
-#define BCHP_FPM_CTRL_FPM_MEM_CTL_MEM_ADDR_MASK 0x0003fffc
-#define BCHP_FPM_CTRL_FPM_MEM_CTL_MEM_ADDR_SHIFT 2
-#define BCHP_FPM_CTRL_FPM_MEM_CTL_MEM_ADDR_DEFAULT 0x00000000
-
-/* FPM_CTRL_FPM :: MEM_CTL :: reserved1 [01:00] */
-#define BCHP_FPM_CTRL_FPM_MEM_CTL_reserved1_MASK 0x00000003
-#define BCHP_FPM_CTRL_FPM_MEM_CTL_reserved1_SHIFT 0
-
-/***************************************************************************
- *MEM_DATA1 - Back door Memory Data1 Register
- ***************************************************************************/
-/* FPM_CTRL_FPM :: MEM_DATA1 :: MEM_DATA1 [31:00] */
-#define BCHP_FPM_CTRL_FPM_MEM_DATA1_MEM_DATA1_MASK 0xffffffff
-#define BCHP_FPM_CTRL_FPM_MEM_DATA1_MEM_DATA1_SHIFT 0
-#define BCHP_FPM_CTRL_FPM_MEM_DATA1_MEM_DATA1_DEFAULT 0x00000000
-
-/***************************************************************************
- *MEM_DATA2 - Back door Memory Data2 Register
- ***************************************************************************/
-/* FPM_CTRL_FPM :: MEM_DATA2 :: MEM_DATA2 [31:00] */
-#define BCHP_FPM_CTRL_FPM_MEM_DATA2_MEM_DATA2_MASK 0xffffffff
-#define BCHP_FPM_CTRL_FPM_MEM_DATA2_MEM_DATA2_SHIFT 0
-#define BCHP_FPM_CTRL_FPM_MEM_DATA2_MEM_DATA2_DEFAULT 0x00000000
-
-/***************************************************************************
- *SPARE - Spare Register for future use
- ***************************************************************************/
-/* FPM_CTRL_FPM :: SPARE :: SPARE_BITS [31:00] */
-#define BCHP_FPM_CTRL_FPM_SPARE_SPARE_BITS_MASK 0xffffffff
-#define BCHP_FPM_CTRL_FPM_SPARE_SPARE_BITS_SHIFT 0
-#define BCHP_FPM_CTRL_FPM_SPARE_SPARE_BITS_DEFAULT 0x00000000
-
-#endif /* #ifndef BCHP_FPM_CTRL_FPM_H__ */
-
-/* End of File */
diff --git a/include/linux/brcmstb/7145a0/bchp_fpm_pool_fpm.h b/include/linux/brcmstb/7145a0/bchp_fpm_pool_fpm.h
deleted file mode 100644
index efd4ddd..0000000
--- a/include/linux/brcmstb/7145a0/bchp_fpm_pool_fpm.h
+++ /dev/null
@@ -1,201 +0,0 @@
-/***************************************************************************
- * Copyright (c) 1999-2013, Broadcom Corporation
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
- *
- * Module Description:
- * DO NOT EDIT THIS FILE DIRECTLY
- *
- * This module was generated magically with RDB from a source description
- * file. You must edit the source file for changes to be made to this file.
- *
- *
- * Date: Generated on Wed May 8 03:09:20 2013
- * MD5 Checksum d41d8cd98f00b204e9800998ecf8427e
- *
- * Compiled with: RDB Utility combo_header.pl
- * RDB Parser 3.0
- * unknown unknown
- * Perl Interpreter 5.008008
- * Operating System linux
- *
- * Revision History:
- *
- * $brcm_Log: $
- *
- ***************************************************************************/
-
-#ifndef BCHP_FPM_POOL_FPM_H__
-#define BCHP_FPM_POOL_FPM_H__
-
-/***************************************************************************
- *FPM_POOL_FPM - FPM FPM Pool Management Registers
- ***************************************************************************/
-#define BCHP_FPM_POOL_FPM_POOL1_ALLOC_DEALLOC 0x03a00200 /* POOL1 Allocation & De-allocation/Free Management Register */
-#define BCHP_FPM_POOL_FPM_POOL2_ALLOC_DEALLOC 0x03a00208 /* POOL2 Allocation & De-allocation/Free Management Register */
-#define BCHP_FPM_POOL_FPM_POOL3_ALLOC_DEALLOC 0x03a00210 /* POOL3 Allocation & De-allocation/Free Management Register */
-#define BCHP_FPM_POOL_FPM_POOL4_ALLOC_DEALLOC 0x03a00218 /* POOL4 Allocation & De-allocation/Free Management Register */
-#define BCHP_FPM_POOL_FPM_SPARE 0x03a00220 /* Spare Register for future use */
-#define BCHP_FPM_POOL_FPM_POOL_MULTI 0x03a00224 /* Multi-cast Token Update Control Register */
-
-/***************************************************************************
- *POOL1_ALLOC_DEALLOC - POOL1 Allocation & De-allocation/Free Management Register
- ***************************************************************************/
-/* FPM_POOL_FPM :: POOL1_ALLOC_DEALLOC :: TOKEN_VALID [31:31] */
-#define BCHP_FPM_POOL_FPM_POOL1_ALLOC_DEALLOC_TOKEN_VALID_MASK 0x80000000
-#define BCHP_FPM_POOL_FPM_POOL1_ALLOC_DEALLOC_TOKEN_VALID_SHIFT 31
-#define BCHP_FPM_POOL_FPM_POOL1_ALLOC_DEALLOC_TOKEN_VALID_DEFAULT 0x00000000
-
-/* FPM_POOL_FPM :: POOL1_ALLOC_DEALLOC :: reserved0 [30:30] */
-#define BCHP_FPM_POOL_FPM_POOL1_ALLOC_DEALLOC_reserved0_MASK 0x40000000
-#define BCHP_FPM_POOL_FPM_POOL1_ALLOC_DEALLOC_reserved0_SHIFT 30
-
-/* FPM_POOL_FPM :: POOL1_ALLOC_DEALLOC :: POOL_ID [29:28] */
-#define BCHP_FPM_POOL_FPM_POOL1_ALLOC_DEALLOC_POOL_ID_MASK 0x30000000
-#define BCHP_FPM_POOL_FPM_POOL1_ALLOC_DEALLOC_POOL_ID_SHIFT 28
-#define BCHP_FPM_POOL_FPM_POOL1_ALLOC_DEALLOC_POOL_ID_DEFAULT 0x00000000
-
-/* FPM_POOL_FPM :: POOL1_ALLOC_DEALLOC :: TOKEN_INDEX [27:12] */
-#define BCHP_FPM_POOL_FPM_POOL1_ALLOC_DEALLOC_TOKEN_INDEX_MASK 0x0ffff000
-#define BCHP_FPM_POOL_FPM_POOL1_ALLOC_DEALLOC_TOKEN_INDEX_SHIFT 12
-#define BCHP_FPM_POOL_FPM_POOL1_ALLOC_DEALLOC_TOKEN_INDEX_DEFAULT 0x00000000
-
-/* FPM_POOL_FPM :: POOL1_ALLOC_DEALLOC :: TOKEN_SIZE [11:00] */
-#define BCHP_FPM_POOL_FPM_POOL1_ALLOC_DEALLOC_TOKEN_SIZE_MASK 0x00000fff
-#define BCHP_FPM_POOL_FPM_POOL1_ALLOC_DEALLOC_TOKEN_SIZE_SHIFT 0
-#define BCHP_FPM_POOL_FPM_POOL1_ALLOC_DEALLOC_TOKEN_SIZE_DEFAULT 0x00000000
-
-/***************************************************************************
- *POOL2_ALLOC_DEALLOC - POOL2 Allocation & De-allocation/Free Management Register
- ***************************************************************************/
-/* FPM_POOL_FPM :: POOL2_ALLOC_DEALLOC :: TOKEN_VALID [31:31] */
-#define BCHP_FPM_POOL_FPM_POOL2_ALLOC_DEALLOC_TOKEN_VALID_MASK 0x80000000
-#define BCHP_FPM_POOL_FPM_POOL2_ALLOC_DEALLOC_TOKEN_VALID_SHIFT 31
-#define BCHP_FPM_POOL_FPM_POOL2_ALLOC_DEALLOC_TOKEN_VALID_DEFAULT 0x00000000
-
-/* FPM_POOL_FPM :: POOL2_ALLOC_DEALLOC :: reserved0 [30:30] */
-#define BCHP_FPM_POOL_FPM_POOL2_ALLOC_DEALLOC_reserved0_MASK 0x40000000
-#define BCHP_FPM_POOL_FPM_POOL2_ALLOC_DEALLOC_reserved0_SHIFT 30
-
-/* FPM_POOL_FPM :: POOL2_ALLOC_DEALLOC :: POOL_ID [29:28] */
-#define BCHP_FPM_POOL_FPM_POOL2_ALLOC_DEALLOC_POOL_ID_MASK 0x30000000
-#define BCHP_FPM_POOL_FPM_POOL2_ALLOC_DEALLOC_POOL_ID_SHIFT 28
-#define BCHP_FPM_POOL_FPM_POOL2_ALLOC_DEALLOC_POOL_ID_DEFAULT 0x00000000
-
-/* FPM_POOL_FPM :: POOL2_ALLOC_DEALLOC :: TOKEN_INDEX [27:12] */
-#define BCHP_FPM_POOL_FPM_POOL2_ALLOC_DEALLOC_TOKEN_INDEX_MASK 0x0ffff000
-#define BCHP_FPM_POOL_FPM_POOL2_ALLOC_DEALLOC_TOKEN_INDEX_SHIFT 12
-#define BCHP_FPM_POOL_FPM_POOL2_ALLOC_DEALLOC_TOKEN_INDEX_DEFAULT 0x00000000
-
-/* FPM_POOL_FPM :: POOL2_ALLOC_DEALLOC :: TOKEN_SIZE [11:00] */
-#define BCHP_FPM_POOL_FPM_POOL2_ALLOC_DEALLOC_TOKEN_SIZE_MASK 0x00000fff
-#define BCHP_FPM_POOL_FPM_POOL2_ALLOC_DEALLOC_TOKEN_SIZE_SHIFT 0
-#define BCHP_FPM_POOL_FPM_POOL2_ALLOC_DEALLOC_TOKEN_SIZE_DEFAULT 0x00000000
-
-/***************************************************************************
- *POOL3_ALLOC_DEALLOC - POOL3 Allocation & De-allocation/Free Management Register
- ***************************************************************************/
-/* FPM_POOL_FPM :: POOL3_ALLOC_DEALLOC :: TOKEN_VALID [31:31] */
-#define BCHP_FPM_POOL_FPM_POOL3_ALLOC_DEALLOC_TOKEN_VALID_MASK 0x80000000
-#define BCHP_FPM_POOL_FPM_POOL3_ALLOC_DEALLOC_TOKEN_VALID_SHIFT 31
-#define BCHP_FPM_POOL_FPM_POOL3_ALLOC_DEALLOC_TOKEN_VALID_DEFAULT 0x00000000
-
-/* FPM_POOL_FPM :: POOL3_ALLOC_DEALLOC :: reserved0 [30:30] */
-#define BCHP_FPM_POOL_FPM_POOL3_ALLOC_DEALLOC_reserved0_MASK 0x40000000
-#define BCHP_FPM_POOL_FPM_POOL3_ALLOC_DEALLOC_reserved0_SHIFT 30
-
-/* FPM_POOL_FPM :: POOL3_ALLOC_DEALLOC :: POOL_ID [29:28] */
-#define BCHP_FPM_POOL_FPM_POOL3_ALLOC_DEALLOC_POOL_ID_MASK 0x30000000
-#define BCHP_FPM_POOL_FPM_POOL3_ALLOC_DEALLOC_POOL_ID_SHIFT 28
-#define BCHP_FPM_POOL_FPM_POOL3_ALLOC_DEALLOC_POOL_ID_DEFAULT 0x00000000
-
-/* FPM_POOL_FPM :: POOL3_ALLOC_DEALLOC :: TOKEN_INDEX [27:12] */
-#define BCHP_FPM_POOL_FPM_POOL3_ALLOC_DEALLOC_TOKEN_INDEX_MASK 0x0ffff000
-#define BCHP_FPM_POOL_FPM_POOL3_ALLOC_DEALLOC_TOKEN_INDEX_SHIFT 12
-#define BCHP_FPM_POOL_FPM_POOL3_ALLOC_DEALLOC_TOKEN_INDEX_DEFAULT 0x00000000
-
-/* FPM_POOL_FPM :: POOL3_ALLOC_DEALLOC :: TOKEN_SIZE [11:00] */
-#define BCHP_FPM_POOL_FPM_POOL3_ALLOC_DEALLOC_TOKEN_SIZE_MASK 0x00000fff
-#define BCHP_FPM_POOL_FPM_POOL3_ALLOC_DEALLOC_TOKEN_SIZE_SHIFT 0
-#define BCHP_FPM_POOL_FPM_POOL3_ALLOC_DEALLOC_TOKEN_SIZE_DEFAULT 0x00000000
-
-/***************************************************************************
- *POOL4_ALLOC_DEALLOC - POOL4 Allocation & De-allocation/Free Management Register
- ***************************************************************************/
-/* FPM_POOL_FPM :: POOL4_ALLOC_DEALLOC :: TOKEN_VALID [31:31] */
-#define BCHP_FPM_POOL_FPM_POOL4_ALLOC_DEALLOC_TOKEN_VALID_MASK 0x80000000
-#define BCHP_FPM_POOL_FPM_POOL4_ALLOC_DEALLOC_TOKEN_VALID_SHIFT 31
-#define BCHP_FPM_POOL_FPM_POOL4_ALLOC_DEALLOC_TOKEN_VALID_DEFAULT 0x00000000
-
-/* FPM_POOL_FPM :: POOL4_ALLOC_DEALLOC :: reserved0 [30:30] */
-#define BCHP_FPM_POOL_FPM_POOL4_ALLOC_DEALLOC_reserved0_MASK 0x40000000
-#define BCHP_FPM_POOL_FPM_POOL4_ALLOC_DEALLOC_reserved0_SHIFT 30
-
-/* FPM_POOL_FPM :: POOL4_ALLOC_DEALLOC :: POOL_ID [29:28] */
-#define BCHP_FPM_POOL_FPM_POOL4_ALLOC_DEALLOC_POOL_ID_MASK 0x30000000
-#define BCHP_FPM_POOL_FPM_POOL4_ALLOC_DEALLOC_POOL_ID_SHIFT 28
-#define BCHP_FPM_POOL_FPM_POOL4_ALLOC_DEALLOC_POOL_ID_DEFAULT 0x00000000
-
-/* FPM_POOL_FPM :: POOL4_ALLOC_DEALLOC :: TOKEN_INDEX [27:12] */
-#define BCHP_FPM_POOL_FPM_POOL4_ALLOC_DEALLOC_TOKEN_INDEX_MASK 0x0ffff000
-#define BCHP_FPM_POOL_FPM_POOL4_ALLOC_DEALLOC_TOKEN_INDEX_SHIFT 12
-#define BCHP_FPM_POOL_FPM_POOL4_ALLOC_DEALLOC_TOKEN_INDEX_DEFAULT 0x00000000
-
-/* FPM_POOL_FPM :: POOL4_ALLOC_DEALLOC :: TOKEN_SIZE [11:00] */
-#define BCHP_FPM_POOL_FPM_POOL4_ALLOC_DEALLOC_TOKEN_SIZE_MASK 0x00000fff
-#define BCHP_FPM_POOL_FPM_POOL4_ALLOC_DEALLOC_TOKEN_SIZE_SHIFT 0
-#define BCHP_FPM_POOL_FPM_POOL4_ALLOC_DEALLOC_TOKEN_SIZE_DEFAULT 0x00000000
-
-/***************************************************************************
- *SPARE - Spare Register for future use
- ***************************************************************************/
-/* FPM_POOL_FPM :: SPARE :: SPARE_BITS [31:00] */
-#define BCHP_FPM_POOL_FPM_SPARE_SPARE_BITS_MASK 0xffffffff
-#define BCHP_FPM_POOL_FPM_SPARE_SPARE_BITS_SHIFT 0
-#define BCHP_FPM_POOL_FPM_SPARE_SPARE_BITS_DEFAULT 0x00000000
-
-/***************************************************************************
- *POOL_MULTI - Multi-cast Token Update Control Register
- ***************************************************************************/
-/* FPM_POOL_FPM :: POOL_MULTI :: TOKEN_VALID [31:31] */
-#define BCHP_FPM_POOL_FPM_POOL_MULTI_TOKEN_VALID_MASK 0x80000000
-#define BCHP_FPM_POOL_FPM_POOL_MULTI_TOKEN_VALID_SHIFT 31
-#define BCHP_FPM_POOL_FPM_POOL_MULTI_TOKEN_VALID_DEFAULT 0x00000000
-
-/* FPM_POOL_FPM :: POOL_MULTI :: reserved0 [30:30] */
-#define BCHP_FPM_POOL_FPM_POOL_MULTI_reserved0_MASK 0x40000000
-#define BCHP_FPM_POOL_FPM_POOL_MULTI_reserved0_SHIFT 30
-
-/* FPM_POOL_FPM :: POOL_MULTI :: TOKEN_INDEX [29:12] */
-#define BCHP_FPM_POOL_FPM_POOL_MULTI_TOKEN_INDEX_MASK 0x3ffff000
-#define BCHP_FPM_POOL_FPM_POOL_MULTI_TOKEN_INDEX_SHIFT 12
-#define BCHP_FPM_POOL_FPM_POOL_MULTI_TOKEN_INDEX_DEFAULT 0x00000000
-
-/* FPM_POOL_FPM :: POOL_MULTI :: UPDATE_TYPE [11:11] */
-#define BCHP_FPM_POOL_FPM_POOL_MULTI_UPDATE_TYPE_MASK 0x00000800
-#define BCHP_FPM_POOL_FPM_POOL_MULTI_UPDATE_TYPE_SHIFT 11
-#define BCHP_FPM_POOL_FPM_POOL_MULTI_UPDATE_TYPE_DEFAULT 0x00000000
-
-/* FPM_POOL_FPM :: POOL_MULTI :: reserved1 [10:07] */
-#define BCHP_FPM_POOL_FPM_POOL_MULTI_reserved1_MASK 0x00000780
-#define BCHP_FPM_POOL_FPM_POOL_MULTI_reserved1_SHIFT 7
-
-/* FPM_POOL_FPM :: POOL_MULTI :: TOKEN_MULTI [06:00] */
-#define BCHP_FPM_POOL_FPM_POOL_MULTI_TOKEN_MULTI_MASK 0x0000007f
-#define BCHP_FPM_POOL_FPM_POOL_MULTI_TOKEN_MULTI_SHIFT 0
-#define BCHP_FPM_POOL_FPM_POOL_MULTI_TOKEN_MULTI_DEFAULT 0x00000000
-
-#endif /* #ifndef BCHP_FPM_POOL_FPM_H__ */
-
-/* End of File */
diff --git a/include/linux/brcmstb/7145a0/bchp_gio.h b/include/linux/brcmstb/7145a0/bchp_gio.h
deleted file mode 100644
index 7ae64cd..0000000
--- a/include/linux/brcmstb/7145a0/bchp_gio.h
+++ /dev/null
@@ -1,474 +0,0 @@
-/***************************************************************************
- * Copyright (c) 1999-2014, Broadcom Corporation
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
- *
- * Module Description:
- * DO NOT EDIT THIS FILE DIRECTLY
- *
- * This module was generated magically with RDB from a source description
- * file. You must edit the source file for changes to be made to this file.
- *
- *
- * Date: Generated on Wed Sep 3 13:17:33 2014
- * Full Compile MD5 Checksum a8ee62ccf9dde43435c825f266da463d
- * (minus title and desc)
- * MD5 Checksum e373b364a1742e13a0f9eb15fd8aa94f
- *
- * Compiled with: RDB Utility combo_header.pl
- * RDB Parser 3.0
- * unknown unknown
- * Perl Interpreter 5.008005
- * Operating System linux
- *
- * Revision History:
- *
- * $brcm_Log: $
- *
- ***************************************************************************/
-
-#ifndef BCHP_GIO_H__
-#define BCHP_GIO_H__
-
-/***************************************************************************
- *GIO - GPIO
- ***************************************************************************/
-#define BCHP_GIO_ODEN_LO 0x20406200 /* GENERAL PURPOSE I/O OPEN DRAIN ENABLE FOR GPIO[31:0] */
-#define BCHP_GIO_DATA_LO 0x20406204 /* GENERAL PURPOSE I/O DATA FOR GPIO[31:0] */
-#define BCHP_GIO_IODIR_LO 0x20406208 /* GENERAL PURPOSE I/O DIRECTION FOR GPIO[31:0] */
-#define BCHP_GIO_EC_LO 0x2040620c /* GENERAL PURPOSE I/O EDGE CONFIGURATION FOR GPIO[31:0] */
-#define BCHP_GIO_EI_LO 0x20406210 /* GENERAL PURPOSE I/O EDGE INSENSITIVE FOR GPIO[31:0] */
-#define BCHP_GIO_MASK_LO 0x20406214 /* GENERAL PURPOSE I/O INTERRUPT MASK FOR GPIO[31:0] */
-#define BCHP_GIO_LEVEL_LO 0x20406218 /* GENERAL PURPOSE I/O INTERRUPT TYPE FOR GPIO[31:0] */
-#define BCHP_GIO_STAT_LO 0x2040621c /* GENERAL PURPOSE I/O INTERRUPT STATUS FOR GPIO[31:0] */
-#define BCHP_GIO_ODEN_HI 0x20406220 /* GENERAL PURPOSE I/O OPEN DRAIN ENABLE FOR GPIO[63:32] */
-#define BCHP_GIO_DATA_HI 0x20406224 /* GENERAL PURPOSE I/O DATA FOR GPIO[63:32] */
-#define BCHP_GIO_IODIR_HI 0x20406228 /* GENERAL PURPOSE I/O DIRECTION FOR GPIO[63:32] */
-#define BCHP_GIO_EC_HI 0x2040622c /* GENERAL PURPOSE I/O EDGE CONFIGURATION FOR GPIO[63:32] */
-#define BCHP_GIO_EI_HI 0x20406230 /* GENERAL PURPOSE I/O EDGE INSENSITIVE FOR GPIO[63:32] */
-#define BCHP_GIO_MASK_HI 0x20406234 /* GENERAL PURPOSE I/O INTERRUPT MASK FOR GPIO[63:32] */
-#define BCHP_GIO_LEVEL_HI 0x20406238 /* GENERAL PURPOSE I/O INTERRUPT TYPE FOR GPIO[63:32] */
-#define BCHP_GIO_STAT_HI 0x2040623c /* GENERAL PURPOSE I/O INTERRUPT STATUS FOR GPIO[63:32] */
-#define BCHP_GIO_ODEN_EXT_HI 0x20406240 /* GENERAL PURPOSE I/O OPEN DRAIN ENABLE FOR GPIO[95:64] */
-#define BCHP_GIO_DATA_EXT_HI 0x20406244 /* GENERAL PURPOSE I/O DATA FOR GPIO[95:64] */
-#define BCHP_GIO_IODIR_EXT_HI 0x20406248 /* GENERAL PURPOSE I/O DIRECTION FOR GPIO[95:64] */
-#define BCHP_GIO_EC_EXT_HI 0x2040624c /* GENERAL PURPOSE I/O EDGE CONFIGURATION FOR GPIO[95:64] */
-#define BCHP_GIO_EI_EXT_HI 0x20406250 /* GENERAL PURPOSE I/O EDGE INSENSITIVE FOR GPIO[95:64] */
-#define BCHP_GIO_MASK_EXT_HI 0x20406254 /* GENERAL PURPOSE I/O INTERRUPT MASK FOR GPIO[95:64] */
-#define BCHP_GIO_LEVEL_EXT_HI 0x20406258 /* GENERAL PURPOSE I/O INTERRUPT TYPE FOR GPIO[95:64] */
-#define BCHP_GIO_STAT_EXT_HI 0x2040625c /* GENERAL PURPOSE I/O INTERRUPT STATUS FOR GPIO[95:64] */
-#define BCHP_GIO_ODEN_EXT2 0x20406260 /* GENERAL PURPOSE I/O OPEN DRAIN ENABLE FOR GPIO[110:96] */
-#define BCHP_GIO_DATA_EXT2 0x20406264 /* GENERAL PURPOSE I/O DATA FOR GPIO[110:96] */
-#define BCHP_GIO_IODIR_EXT2 0x20406268 /* GENERAL PURPOSE I/O DIRECTION FOR GPIO[110:96] */
-#define BCHP_GIO_EC_EXT2 0x2040626c /* GENERAL PURPOSE I/O EDGE CONFIGURATION FOR GPIO[110:96] */
-#define BCHP_GIO_EI_EXT2 0x20406270 /* GENERAL PURPOSE I/O EDGE INSENSITIVE FOR GPIO[110:96] */
-#define BCHP_GIO_MASK_EXT2 0x20406274 /* GENERAL PURPOSE I/O INTERRUPT MASK FOR GPIO[110:96] */
-#define BCHP_GIO_LEVEL_EXT2 0x20406278 /* GENERAL PURPOSE I/O INTERRUPT TYPE FOR GPIO[110:96] */
-#define BCHP_GIO_STAT_EXT2 0x2040627c /* GENERAL PURPOSE I/O INTERRUPT STATUS FOR GPIO[110:96] */
-#define BCHP_GIO_ODEN_EXT 0x20406280 /* GENERAL PURPOSE I/O OPEN DRAIN ENABLE FOR SGPIO[3:0] AND AON_SGPIO[1:0] */
-#define BCHP_GIO_DATA_EXT 0x20406284 /* GENERAL PURPOSE I/O DATA FOR SGPIO[3:0] AND AON_SGPIO[1:0] */
-#define BCHP_GIO_IODIR_EXT 0x20406288 /* GENERAL PURPOSE I/O DIRECTION FOR SGPIO[3:0] AND AON_SGPIO[1:0] */
-#define BCHP_GIO_EC_EXT 0x2040628c /* GENERAL PURPOSE I/O EDGE CONFIGURATION FOR SGPIO[3:0] AND AON_SGPIO[1:0] */
-#define BCHP_GIO_EI_EXT 0x20406290 /* GENERAL PURPOSE I/O EDGE INSENSITIVE FOR SGPIO[3:0] AND AON_SGPIO[1:0] */
-#define BCHP_GIO_MASK_EXT 0x20406294 /* GENERAL PURPOSE I/O INTERRUPT MASK FOR SGPIO[3:0] AND AON_SGPIO[1:0] */
-#define BCHP_GIO_LEVEL_EXT 0x20406298 /* GENERAL PURPOSE I/O INTERRUPT TYPE FOR SGPIO[3:0] AND AON_SGPIO[1:0] */
-#define BCHP_GIO_STAT_EXT 0x2040629c /* GENERAL PURPOSE I/O INTERRUPT STATUS FOR SGPIO[3:0] AND AON_SGPIO[1:0] */
-
-/***************************************************************************
- *ODEN_LO - GENERAL PURPOSE I/O OPEN DRAIN ENABLE FOR GPIO[31:0]
- ***************************************************************************/
-/* GIO :: ODEN_LO :: oden [31:00] */
-#define BCHP_GIO_ODEN_LO_oden_MASK 0xffffffff
-#define BCHP_GIO_ODEN_LO_oden_SHIFT 0
-#define BCHP_GIO_ODEN_LO_oden_DEFAULT 0x00000000
-
-/***************************************************************************
- *DATA_LO - GENERAL PURPOSE I/O DATA FOR GPIO[31:0]
- ***************************************************************************/
-/* GIO :: DATA_LO :: data [31:00] */
-#define BCHP_GIO_DATA_LO_data_MASK 0xffffffff
-#define BCHP_GIO_DATA_LO_data_SHIFT 0
-#define BCHP_GIO_DATA_LO_data_DEFAULT 0x00000000
-
-/***************************************************************************
- *IODIR_LO - GENERAL PURPOSE I/O DIRECTION FOR GPIO[31:0]
- ***************************************************************************/
-/* GIO :: IODIR_LO :: iodir [31:00] */
-#define BCHP_GIO_IODIR_LO_iodir_MASK 0xffffffff
-#define BCHP_GIO_IODIR_LO_iodir_SHIFT 0
-#define BCHP_GIO_IODIR_LO_iodir_DEFAULT 0x00ffffff
-
-/***************************************************************************
- *EC_LO - GENERAL PURPOSE I/O EDGE CONFIGURATION FOR GPIO[31:0]
- ***************************************************************************/
-/* GIO :: EC_LO :: edge_config [31:00] */
-#define BCHP_GIO_EC_LO_edge_config_MASK 0xffffffff
-#define BCHP_GIO_EC_LO_edge_config_SHIFT 0
-#define BCHP_GIO_EC_LO_edge_config_DEFAULT 0x00000000
-
-/***************************************************************************
- *EI_LO - GENERAL PURPOSE I/O EDGE INSENSITIVE FOR GPIO[31:0]
- ***************************************************************************/
-/* GIO :: EI_LO :: edge_insensitive [31:00] */
-#define BCHP_GIO_EI_LO_edge_insensitive_MASK 0xffffffff
-#define BCHP_GIO_EI_LO_edge_insensitive_SHIFT 0
-#define BCHP_GIO_EI_LO_edge_insensitive_DEFAULT 0x00000000
-
-/***************************************************************************
- *MASK_LO - GENERAL PURPOSE I/O INTERRUPT MASK FOR GPIO[31:0]
- ***************************************************************************/
-/* GIO :: MASK_LO :: irq_mask [31:00] */
-#define BCHP_GIO_MASK_LO_irq_mask_MASK 0xffffffff
-#define BCHP_GIO_MASK_LO_irq_mask_SHIFT 0
-#define BCHP_GIO_MASK_LO_irq_mask_DEFAULT 0x00000000
-
-/***************************************************************************
- *LEVEL_LO - GENERAL PURPOSE I/O INTERRUPT TYPE FOR GPIO[31:0]
- ***************************************************************************/
-/* GIO :: LEVEL_LO :: level [31:00] */
-#define BCHP_GIO_LEVEL_LO_level_MASK 0xffffffff
-#define BCHP_GIO_LEVEL_LO_level_SHIFT 0
-#define BCHP_GIO_LEVEL_LO_level_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_LO - GENERAL PURPOSE I/O INTERRUPT STATUS FOR GPIO[31:0]
- ***************************************************************************/
-/* GIO :: STAT_LO :: irq_status [31:00] */
-#define BCHP_GIO_STAT_LO_irq_status_MASK 0xffffffff
-#define BCHP_GIO_STAT_LO_irq_status_SHIFT 0
-#define BCHP_GIO_STAT_LO_irq_status_DEFAULT 0x00000000
-
-/***************************************************************************
- *ODEN_HI - GENERAL PURPOSE I/O OPEN DRAIN ENABLE FOR GPIO[63:32]
- ***************************************************************************/
-/* GIO :: ODEN_HI :: oden [31:00] */
-#define BCHP_GIO_ODEN_HI_oden_MASK 0xffffffff
-#define BCHP_GIO_ODEN_HI_oden_SHIFT 0
-#define BCHP_GIO_ODEN_HI_oden_DEFAULT 0x00000000
-
-/***************************************************************************
- *DATA_HI - GENERAL PURPOSE I/O DATA FOR GPIO[63:32]
- ***************************************************************************/
-/* GIO :: DATA_HI :: data [31:00] */
-#define BCHP_GIO_DATA_HI_data_MASK 0xffffffff
-#define BCHP_GIO_DATA_HI_data_SHIFT 0
-#define BCHP_GIO_DATA_HI_data_DEFAULT 0x00000000
-
-/***************************************************************************
- *IODIR_HI - GENERAL PURPOSE I/O DIRECTION FOR GPIO[63:32]
- ***************************************************************************/
-/* GIO :: IODIR_HI :: iodir [31:00] */
-#define BCHP_GIO_IODIR_HI_iodir_MASK 0xffffffff
-#define BCHP_GIO_IODIR_HI_iodir_SHIFT 0
-#define BCHP_GIO_IODIR_HI_iodir_DEFAULT 0x00ffffff
-
-/***************************************************************************
- *EC_HI - GENERAL PURPOSE I/O EDGE CONFIGURATION FOR GPIO[63:32]
- ***************************************************************************/
-/* GIO :: EC_HI :: edge_config [31:00] */
-#define BCHP_GIO_EC_HI_edge_config_MASK 0xffffffff
-#define BCHP_GIO_EC_HI_edge_config_SHIFT 0
-#define BCHP_GIO_EC_HI_edge_config_DEFAULT 0x00000000
-
-/***************************************************************************
- *EI_HI - GENERAL PURPOSE I/O EDGE INSENSITIVE FOR GPIO[63:32]
- ***************************************************************************/
-/* GIO :: EI_HI :: edge_insensitive [31:00] */
-#define BCHP_GIO_EI_HI_edge_insensitive_MASK 0xffffffff
-#define BCHP_GIO_EI_HI_edge_insensitive_SHIFT 0
-#define BCHP_GIO_EI_HI_edge_insensitive_DEFAULT 0x00000000
-
-/***************************************************************************
- *MASK_HI - GENERAL PURPOSE I/O INTERRUPT MASK FOR GPIO[63:32]
- ***************************************************************************/
-/* GIO :: MASK_HI :: irq_mask [31:00] */
-#define BCHP_GIO_MASK_HI_irq_mask_MASK 0xffffffff
-#define BCHP_GIO_MASK_HI_irq_mask_SHIFT 0
-#define BCHP_GIO_MASK_HI_irq_mask_DEFAULT 0x00000000
-
-/***************************************************************************
- *LEVEL_HI - GENERAL PURPOSE I/O INTERRUPT TYPE FOR GPIO[63:32]
- ***************************************************************************/
-/* GIO :: LEVEL_HI :: level [31:00] */
-#define BCHP_GIO_LEVEL_HI_level_MASK 0xffffffff
-#define BCHP_GIO_LEVEL_HI_level_SHIFT 0
-#define BCHP_GIO_LEVEL_HI_level_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_HI - GENERAL PURPOSE I/O INTERRUPT STATUS FOR GPIO[63:32]
- ***************************************************************************/
-/* GIO :: STAT_HI :: irq_status [31:00] */
-#define BCHP_GIO_STAT_HI_irq_status_MASK 0xffffffff
-#define BCHP_GIO_STAT_HI_irq_status_SHIFT 0
-#define BCHP_GIO_STAT_HI_irq_status_DEFAULT 0x00000000
-
-/***************************************************************************
- *ODEN_EXT_HI - GENERAL PURPOSE I/O OPEN DRAIN ENABLE FOR GPIO[95:64]
- ***************************************************************************/
-/* GIO :: ODEN_EXT_HI :: oden [31:00] */
-#define BCHP_GIO_ODEN_EXT_HI_oden_MASK 0xffffffff
-#define BCHP_GIO_ODEN_EXT_HI_oden_SHIFT 0
-#define BCHP_GIO_ODEN_EXT_HI_oden_DEFAULT 0x00000000
-
-/***************************************************************************
- *DATA_EXT_HI - GENERAL PURPOSE I/O DATA FOR GPIO[95:64]
- ***************************************************************************/
-/* GIO :: DATA_EXT_HI :: data [31:00] */
-#define BCHP_GIO_DATA_EXT_HI_data_MASK 0xffffffff
-#define BCHP_GIO_DATA_EXT_HI_data_SHIFT 0
-#define BCHP_GIO_DATA_EXT_HI_data_DEFAULT 0x00000000
-
-/***************************************************************************
- *IODIR_EXT_HI - GENERAL PURPOSE I/O DIRECTION FOR GPIO[95:64]
- ***************************************************************************/
-/* GIO :: IODIR_EXT_HI :: iodir [31:00] */
-#define BCHP_GIO_IODIR_EXT_HI_iodir_MASK 0xffffffff
-#define BCHP_GIO_IODIR_EXT_HI_iodir_SHIFT 0
-#define BCHP_GIO_IODIR_EXT_HI_iodir_DEFAULT 0x00ffffff
-
-/***************************************************************************
- *EC_EXT_HI - GENERAL PURPOSE I/O EDGE CONFIGURATION FOR GPIO[95:64]
- ***************************************************************************/
-/* GIO :: EC_EXT_HI :: edge_config [31:00] */
-#define BCHP_GIO_EC_EXT_HI_edge_config_MASK 0xffffffff
-#define BCHP_GIO_EC_EXT_HI_edge_config_SHIFT 0
-#define BCHP_GIO_EC_EXT_HI_edge_config_DEFAULT 0x00000000
-
-/***************************************************************************
- *EI_EXT_HI - GENERAL PURPOSE I/O EDGE INSENSITIVE FOR GPIO[95:64]
- ***************************************************************************/
-/* GIO :: EI_EXT_HI :: edge_insensitive [31:00] */
-#define BCHP_GIO_EI_EXT_HI_edge_insensitive_MASK 0xffffffff
-#define BCHP_GIO_EI_EXT_HI_edge_insensitive_SHIFT 0
-#define BCHP_GIO_EI_EXT_HI_edge_insensitive_DEFAULT 0x00000000
-
-/***************************************************************************
- *MASK_EXT_HI - GENERAL PURPOSE I/O INTERRUPT MASK FOR GPIO[95:64]
- ***************************************************************************/
-/* GIO :: MASK_EXT_HI :: irq_mask [31:00] */
-#define BCHP_GIO_MASK_EXT_HI_irq_mask_MASK 0xffffffff
-#define BCHP_GIO_MASK_EXT_HI_irq_mask_SHIFT 0
-#define BCHP_GIO_MASK_EXT_HI_irq_mask_DEFAULT 0x00000000
-
-/***************************************************************************
- *LEVEL_EXT_HI - GENERAL PURPOSE I/O INTERRUPT TYPE FOR GPIO[95:64]
- ***************************************************************************/
-/* GIO :: LEVEL_EXT_HI :: level [31:00] */
-#define BCHP_GIO_LEVEL_EXT_HI_level_MASK 0xffffffff
-#define BCHP_GIO_LEVEL_EXT_HI_level_SHIFT 0
-#define BCHP_GIO_LEVEL_EXT_HI_level_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_EXT_HI - GENERAL PURPOSE I/O INTERRUPT STATUS FOR GPIO[95:64]
- ***************************************************************************/
-/* GIO :: STAT_EXT_HI :: irq_status [31:00] */
-#define BCHP_GIO_STAT_EXT_HI_irq_status_MASK 0xffffffff
-#define BCHP_GIO_STAT_EXT_HI_irq_status_SHIFT 0
-#define BCHP_GIO_STAT_EXT_HI_irq_status_DEFAULT 0x00000000
-
-/***************************************************************************
- *ODEN_EXT2 - GENERAL PURPOSE I/O OPEN DRAIN ENABLE FOR GPIO[110:96]
- ***************************************************************************/
-/* GIO :: ODEN_EXT2 :: reserved0 [31:15] */
-#define BCHP_GIO_ODEN_EXT2_reserved0_MASK 0xffff8000
-#define BCHP_GIO_ODEN_EXT2_reserved0_SHIFT 15
-
-/* GIO :: ODEN_EXT2 :: oden [14:00] */
-#define BCHP_GIO_ODEN_EXT2_oden_MASK 0x00007fff
-#define BCHP_GIO_ODEN_EXT2_oden_SHIFT 0
-#define BCHP_GIO_ODEN_EXT2_oden_DEFAULT 0x00000000
-
-/***************************************************************************
- *DATA_EXT2 - GENERAL PURPOSE I/O DATA FOR GPIO[110:96]
- ***************************************************************************/
-/* GIO :: DATA_EXT2 :: reserved0 [31:15] */
-#define BCHP_GIO_DATA_EXT2_reserved0_MASK 0xffff8000
-#define BCHP_GIO_DATA_EXT2_reserved0_SHIFT 15
-
-/* GIO :: DATA_EXT2 :: data [14:00] */
-#define BCHP_GIO_DATA_EXT2_data_MASK 0x00007fff
-#define BCHP_GIO_DATA_EXT2_data_SHIFT 0
-#define BCHP_GIO_DATA_EXT2_data_DEFAULT 0x00000000
-
-/***************************************************************************
- *IODIR_EXT2 - GENERAL PURPOSE I/O DIRECTION FOR GPIO[110:96]
- ***************************************************************************/
-/* GIO :: IODIR_EXT2 :: reserved0 [31:15] */
-#define BCHP_GIO_IODIR_EXT2_reserved0_MASK 0xffff8000
-#define BCHP_GIO_IODIR_EXT2_reserved0_SHIFT 15
-
-/* GIO :: IODIR_EXT2 :: iodir [14:00] */
-#define BCHP_GIO_IODIR_EXT2_iodir_MASK 0x00007fff
-#define BCHP_GIO_IODIR_EXT2_iodir_SHIFT 0
-#define BCHP_GIO_IODIR_EXT2_iodir_DEFAULT 0x000007ff
-
-/***************************************************************************
- *EC_EXT2 - GENERAL PURPOSE I/O EDGE CONFIGURATION FOR GPIO[110:96]
- ***************************************************************************/
-/* GIO :: EC_EXT2 :: reserved0 [31:15] */
-#define BCHP_GIO_EC_EXT2_reserved0_MASK 0xffff8000
-#define BCHP_GIO_EC_EXT2_reserved0_SHIFT 15
-
-/* GIO :: EC_EXT2 :: edge_config [14:00] */
-#define BCHP_GIO_EC_EXT2_edge_config_MASK 0x00007fff
-#define BCHP_GIO_EC_EXT2_edge_config_SHIFT 0
-#define BCHP_GIO_EC_EXT2_edge_config_DEFAULT 0x00000000
-
-/***************************************************************************
- *EI_EXT2 - GENERAL PURPOSE I/O EDGE INSENSITIVE FOR GPIO[110:96]
- ***************************************************************************/
-/* GIO :: EI_EXT2 :: reserved0 [31:15] */
-#define BCHP_GIO_EI_EXT2_reserved0_MASK 0xffff8000
-#define BCHP_GIO_EI_EXT2_reserved0_SHIFT 15
-
-/* GIO :: EI_EXT2 :: edge_insensitive [14:00] */
-#define BCHP_GIO_EI_EXT2_edge_insensitive_MASK 0x00007fff
-#define BCHP_GIO_EI_EXT2_edge_insensitive_SHIFT 0
-#define BCHP_GIO_EI_EXT2_edge_insensitive_DEFAULT 0x00000000
-
-/***************************************************************************
- *MASK_EXT2 - GENERAL PURPOSE I/O INTERRUPT MASK FOR GPIO[110:96]
- ***************************************************************************/
-/* GIO :: MASK_EXT2 :: reserved0 [31:15] */
-#define BCHP_GIO_MASK_EXT2_reserved0_MASK 0xffff8000
-#define BCHP_GIO_MASK_EXT2_reserved0_SHIFT 15
-
-/* GIO :: MASK_EXT2 :: irq_mask [14:00] */
-#define BCHP_GIO_MASK_EXT2_irq_mask_MASK 0x00007fff
-#define BCHP_GIO_MASK_EXT2_irq_mask_SHIFT 0
-#define BCHP_GIO_MASK_EXT2_irq_mask_DEFAULT 0x00000000
-
-/***************************************************************************
- *LEVEL_EXT2 - GENERAL PURPOSE I/O INTERRUPT TYPE FOR GPIO[110:96]
- ***************************************************************************/
-/* GIO :: LEVEL_EXT2 :: reserved0 [31:15] */
-#define BCHP_GIO_LEVEL_EXT2_reserved0_MASK 0xffff8000
-#define BCHP_GIO_LEVEL_EXT2_reserved0_SHIFT 15
-
-/* GIO :: LEVEL_EXT2 :: level [14:00] */
-#define BCHP_GIO_LEVEL_EXT2_level_MASK 0x00007fff
-#define BCHP_GIO_LEVEL_EXT2_level_SHIFT 0
-#define BCHP_GIO_LEVEL_EXT2_level_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_EXT2 - GENERAL PURPOSE I/O INTERRUPT STATUS FOR GPIO[110:96]
- ***************************************************************************/
-/* GIO :: STAT_EXT2 :: reserved0 [31:15] */
-#define BCHP_GIO_STAT_EXT2_reserved0_MASK 0xffff8000
-#define BCHP_GIO_STAT_EXT2_reserved0_SHIFT 15
-
-/* GIO :: STAT_EXT2 :: irq_status [14:00] */
-#define BCHP_GIO_STAT_EXT2_irq_status_MASK 0x00007fff
-#define BCHP_GIO_STAT_EXT2_irq_status_SHIFT 0
-#define BCHP_GIO_STAT_EXT2_irq_status_DEFAULT 0x00000000
-
-/***************************************************************************
- *ODEN_EXT - GENERAL PURPOSE I/O OPEN DRAIN ENABLE FOR SGPIO[3:0] AND AON_SGPIO[1:0]
- ***************************************************************************/
-/* GIO :: ODEN_EXT :: reserved0 [31:06] */
-#define BCHP_GIO_ODEN_EXT_reserved0_MASK 0xffffffc0
-#define BCHP_GIO_ODEN_EXT_reserved0_SHIFT 6
-
-/* GIO :: ODEN_EXT :: oden [05:00] */
-#define BCHP_GIO_ODEN_EXT_oden_MASK 0x0000003f
-#define BCHP_GIO_ODEN_EXT_oden_SHIFT 0
-#define BCHP_GIO_ODEN_EXT_oden_DEFAULT 0x00000000
-
-/***************************************************************************
- *DATA_EXT - GENERAL PURPOSE I/O DATA FOR SGPIO[3:0] AND AON_SGPIO[1:0]
- ***************************************************************************/
-/* GIO :: DATA_EXT :: reserved0 [31:06] */
-#define BCHP_GIO_DATA_EXT_reserved0_MASK 0xffffffc0
-#define BCHP_GIO_DATA_EXT_reserved0_SHIFT 6
-
-/* GIO :: DATA_EXT :: data [05:00] */
-#define BCHP_GIO_DATA_EXT_data_MASK 0x0000003f
-#define BCHP_GIO_DATA_EXT_data_SHIFT 0
-#define BCHP_GIO_DATA_EXT_data_DEFAULT 0x00000000
-
-/***************************************************************************
- *IODIR_EXT - GENERAL PURPOSE I/O DIRECTION FOR SGPIO[3:0] AND AON_SGPIO[1:0]
- ***************************************************************************/
-/* GIO :: IODIR_EXT :: reserved0 [31:06] */
-#define BCHP_GIO_IODIR_EXT_reserved0_MASK 0xffffffc0
-#define BCHP_GIO_IODIR_EXT_reserved0_SHIFT 6
-
-/* GIO :: IODIR_EXT :: iodir [05:00] */
-#define BCHP_GIO_IODIR_EXT_iodir_MASK 0x0000003f
-#define BCHP_GIO_IODIR_EXT_iodir_SHIFT 0
-#define BCHP_GIO_IODIR_EXT_iodir_DEFAULT 0x0000003f
-
-/***************************************************************************
- *EC_EXT - GENERAL PURPOSE I/O EDGE CONFIGURATION FOR SGPIO[3:0] AND AON_SGPIO[1:0]
- ***************************************************************************/
-/* GIO :: EC_EXT :: reserved0 [31:06] */
-#define BCHP_GIO_EC_EXT_reserved0_MASK 0xffffffc0
-#define BCHP_GIO_EC_EXT_reserved0_SHIFT 6
-
-/* GIO :: EC_EXT :: edge_config [05:00] */
-#define BCHP_GIO_EC_EXT_edge_config_MASK 0x0000003f
-#define BCHP_GIO_EC_EXT_edge_config_SHIFT 0
-#define BCHP_GIO_EC_EXT_edge_config_DEFAULT 0x00000000
-
-/***************************************************************************
- *EI_EXT - GENERAL PURPOSE I/O EDGE INSENSITIVE FOR SGPIO[3:0] AND AON_SGPIO[1:0]
- ***************************************************************************/
-/* GIO :: EI_EXT :: reserved0 [31:06] */
-#define BCHP_GIO_EI_EXT_reserved0_MASK 0xffffffc0
-#define BCHP_GIO_EI_EXT_reserved0_SHIFT 6
-
-/* GIO :: EI_EXT :: edge_insensitive [05:00] */
-#define BCHP_GIO_EI_EXT_edge_insensitive_MASK 0x0000003f
-#define BCHP_GIO_EI_EXT_edge_insensitive_SHIFT 0
-#define BCHP_GIO_EI_EXT_edge_insensitive_DEFAULT 0x00000000
-
-/***************************************************************************
- *MASK_EXT - GENERAL PURPOSE I/O INTERRUPT MASK FOR SGPIO[3:0] AND AON_SGPIO[1:0]
- ***************************************************************************/
-/* GIO :: MASK_EXT :: reserved0 [31:06] */
-#define BCHP_GIO_MASK_EXT_reserved0_MASK 0xffffffc0
-#define BCHP_GIO_MASK_EXT_reserved0_SHIFT 6
-
-/* GIO :: MASK_EXT :: irq_mask [05:00] */
-#define BCHP_GIO_MASK_EXT_irq_mask_MASK 0x0000003f
-#define BCHP_GIO_MASK_EXT_irq_mask_SHIFT 0
-#define BCHP_GIO_MASK_EXT_irq_mask_DEFAULT 0x00000000
-
-/***************************************************************************
- *LEVEL_EXT - GENERAL PURPOSE I/O INTERRUPT TYPE FOR SGPIO[3:0] AND AON_SGPIO[1:0]
- ***************************************************************************/
-/* GIO :: LEVEL_EXT :: reserved0 [31:06] */
-#define BCHP_GIO_LEVEL_EXT_reserved0_MASK 0xffffffc0
-#define BCHP_GIO_LEVEL_EXT_reserved0_SHIFT 6
-
-/* GIO :: LEVEL_EXT :: level [05:00] */
-#define BCHP_GIO_LEVEL_EXT_level_MASK 0x0000003f
-#define BCHP_GIO_LEVEL_EXT_level_SHIFT 0
-#define BCHP_GIO_LEVEL_EXT_level_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_EXT - GENERAL PURPOSE I/O INTERRUPT STATUS FOR SGPIO[3:0] AND AON_SGPIO[1:0]
- ***************************************************************************/
-/* GIO :: STAT_EXT :: reserved0 [31:06] */
-#define BCHP_GIO_STAT_EXT_reserved0_MASK 0xffffffc0
-#define BCHP_GIO_STAT_EXT_reserved0_SHIFT 6
-
-/* GIO :: STAT_EXT :: irq_status [05:00] */
-#define BCHP_GIO_STAT_EXT_irq_status_MASK 0x0000003f
-#define BCHP_GIO_STAT_EXT_irq_status_SHIFT 0
-#define BCHP_GIO_STAT_EXT_irq_status_DEFAULT 0x00000000
-
-#endif /* #ifndef BCHP_GIO_H__ */
-
-/* End of File */
diff --git a/include/linux/brcmstb/7145a0/bchp_gio_aon.h b/include/linux/brcmstb/7145a0/bchp_gio_aon.h
deleted file mode 100644
index af55637..0000000
--- a/include/linux/brcmstb/7145a0/bchp_gio_aon.h
+++ /dev/null
@@ -1,258 +0,0 @@
-/***************************************************************************
- * Copyright (c) 1999-2014, Broadcom Corporation
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
- *
- * Module Description:
- * DO NOT EDIT THIS FILE DIRECTLY
- *
- * This module was generated magically with RDB from a source description
- * file. You must edit the source file for changes to be made to this file.
- *
- *
- * Date: Generated on Wed Sep 3 13:17:42 2014
- * Full Compile MD5 Checksum a8ee62ccf9dde43435c825f266da463d
- * (minus title and desc)
- * MD5 Checksum e373b364a1742e13a0f9eb15fd8aa94f
- *
- * Compiled with: RDB Utility combo_header.pl
- * RDB Parser 3.0
- * unknown unknown
- * Perl Interpreter 5.008005
- * Operating System linux
- *
- * Revision History:
- *
- * $brcm_Log: $
- *
- ***************************************************************************/
-
-#ifndef BCHP_GIO_AON_H__
-#define BCHP_GIO_AON_H__
-
-/***************************************************************************
- *GIO_AON - GPIO
- ***************************************************************************/
-#define BCHP_GIO_AON_ODEN_LO 0x20411200 /* GENERAL PURPOSE I/O OPEN DRAIN ENABLE FOR GPIO[17:0] */
-#define BCHP_GIO_AON_DATA_LO 0x20411204 /* GENERAL PURPOSE I/O DATA FOR GPIO[17:0] */
-#define BCHP_GIO_AON_IODIR_LO 0x20411208 /* GENERAL PURPOSE I/O DIRECTION FOR GPIO[17:0] */
-#define BCHP_GIO_AON_EC_LO 0x2041120c /* GENERAL PURPOSE I/O EDGE CONFIGURATION FOR GPIO[17:0] */
-#define BCHP_GIO_AON_EI_LO 0x20411210 /* GENERAL PURPOSE I/O EDGE INSENSITIVE FOR GPIO[17:0] */
-#define BCHP_GIO_AON_MASK_LO 0x20411214 /* GENERAL PURPOSE I/O INTERRUPT MASK FOR GPIO[17:0] */
-#define BCHP_GIO_AON_LEVEL_LO 0x20411218 /* GENERAL PURPOSE I/O INTERRUPT TYPE FOR GPIO[17:0] */
-#define BCHP_GIO_AON_STAT_LO 0x2041121c /* GENERAL PURPOSE I/O INTERRUPT STATUS FOR GPIO[17:0] */
-#define BCHP_GIO_AON_ODEN_EXT 0x20411220 /* GENERAL PURPOSE I/O OPEN DRAIN ENABLE FOR SGPIO[3:0] */
-#define BCHP_GIO_AON_DATA_EXT 0x20411224 /* GENERAL PURPOSE I/O DATA FOR SGPIO[3:0] */
-#define BCHP_GIO_AON_IODIR_EXT 0x20411228 /* GENERAL PURPOSE I/O DIRECTION FOR SGPIO[3:0] */
-#define BCHP_GIO_AON_EC_EXT 0x2041122c /* GENERAL PURPOSE I/O EDGE CONFIGURATION FOR SGPIO[3:0] */
-#define BCHP_GIO_AON_EI_EXT 0x20411230 /* GENERAL PURPOSE I/O EDGE INSENSITIVE FOR SGPIO[3:0] */
-#define BCHP_GIO_AON_MASK_EXT 0x20411234 /* GENERAL PURPOSE I/O INTERRUPT MASK FOR SGPIO[3:0] */
-#define BCHP_GIO_AON_LEVEL_EXT 0x20411238 /* GENERAL PURPOSE I/O INTERRUPT TYPE FOR SGPIO[3:0] */
-#define BCHP_GIO_AON_STAT_EXT 0x2041123c /* GENERAL PURPOSE I/O INTERRUPT STATUS FOR SGPIO[3:0] */
-
-/***************************************************************************
- *ODEN_LO - GENERAL PURPOSE I/O OPEN DRAIN ENABLE FOR GPIO[17:0]
- ***************************************************************************/
-/* GIO_AON :: ODEN_LO :: reserved0 [31:18] */
-#define BCHP_GIO_AON_ODEN_LO_reserved0_MASK 0xfffc0000
-#define BCHP_GIO_AON_ODEN_LO_reserved0_SHIFT 18
-
-/* GIO_AON :: ODEN_LO :: oden [17:00] */
-#define BCHP_GIO_AON_ODEN_LO_oden_MASK 0x0003ffff
-#define BCHP_GIO_AON_ODEN_LO_oden_SHIFT 0
-#define BCHP_GIO_AON_ODEN_LO_oden_DEFAULT 0x00000000
-
-/***************************************************************************
- *DATA_LO - GENERAL PURPOSE I/O DATA FOR GPIO[17:0]
- ***************************************************************************/
-/* GIO_AON :: DATA_LO :: reserved0 [31:18] */
-#define BCHP_GIO_AON_DATA_LO_reserved0_MASK 0xfffc0000
-#define BCHP_GIO_AON_DATA_LO_reserved0_SHIFT 18
-
-/* GIO_AON :: DATA_LO :: data [17:00] */
-#define BCHP_GIO_AON_DATA_LO_data_MASK 0x0003ffff
-#define BCHP_GIO_AON_DATA_LO_data_SHIFT 0
-#define BCHP_GIO_AON_DATA_LO_data_DEFAULT 0x00000000
-
-/***************************************************************************
- *IODIR_LO - GENERAL PURPOSE I/O DIRECTION FOR GPIO[17:0]
- ***************************************************************************/
-/* GIO_AON :: IODIR_LO :: reserved0 [31:18] */
-#define BCHP_GIO_AON_IODIR_LO_reserved0_MASK 0xfffc0000
-#define BCHP_GIO_AON_IODIR_LO_reserved0_SHIFT 18
-
-/* GIO_AON :: IODIR_LO :: iodir [17:00] */
-#define BCHP_GIO_AON_IODIR_LO_iodir_MASK 0x0003ffff
-#define BCHP_GIO_AON_IODIR_LO_iodir_SHIFT 0
-#define BCHP_GIO_AON_IODIR_LO_iodir_DEFAULT 0x0003ffff
-
-/***************************************************************************
- *EC_LO - GENERAL PURPOSE I/O EDGE CONFIGURATION FOR GPIO[17:0]
- ***************************************************************************/
-/* GIO_AON :: EC_LO :: reserved0 [31:18] */
-#define BCHP_GIO_AON_EC_LO_reserved0_MASK 0xfffc0000
-#define BCHP_GIO_AON_EC_LO_reserved0_SHIFT 18
-
-/* GIO_AON :: EC_LO :: edge_config [17:00] */
-#define BCHP_GIO_AON_EC_LO_edge_config_MASK 0x0003ffff
-#define BCHP_GIO_AON_EC_LO_edge_config_SHIFT 0
-#define BCHP_GIO_AON_EC_LO_edge_config_DEFAULT 0x00000000
-
-/***************************************************************************
- *EI_LO - GENERAL PURPOSE I/O EDGE INSENSITIVE FOR GPIO[17:0]
- ***************************************************************************/
-/* GIO_AON :: EI_LO :: reserved0 [31:18] */
-#define BCHP_GIO_AON_EI_LO_reserved0_MASK 0xfffc0000
-#define BCHP_GIO_AON_EI_LO_reserved0_SHIFT 18
-
-/* GIO_AON :: EI_LO :: edge_insensitive [17:00] */
-#define BCHP_GIO_AON_EI_LO_edge_insensitive_MASK 0x0003ffff
-#define BCHP_GIO_AON_EI_LO_edge_insensitive_SHIFT 0
-#define BCHP_GIO_AON_EI_LO_edge_insensitive_DEFAULT 0x00000000
-
-/***************************************************************************
- *MASK_LO - GENERAL PURPOSE I/O INTERRUPT MASK FOR GPIO[17:0]
- ***************************************************************************/
-/* GIO_AON :: MASK_LO :: reserved0 [31:18] */
-#define BCHP_GIO_AON_MASK_LO_reserved0_MASK 0xfffc0000
-#define BCHP_GIO_AON_MASK_LO_reserved0_SHIFT 18
-
-/* GIO_AON :: MASK_LO :: irq_mask [17:00] */
-#define BCHP_GIO_AON_MASK_LO_irq_mask_MASK 0x0003ffff
-#define BCHP_GIO_AON_MASK_LO_irq_mask_SHIFT 0
-#define BCHP_GIO_AON_MASK_LO_irq_mask_DEFAULT 0x00000000
-
-/***************************************************************************
- *LEVEL_LO - GENERAL PURPOSE I/O INTERRUPT TYPE FOR GPIO[17:0]
- ***************************************************************************/
-/* GIO_AON :: LEVEL_LO :: reserved0 [31:18] */
-#define BCHP_GIO_AON_LEVEL_LO_reserved0_MASK 0xfffc0000
-#define BCHP_GIO_AON_LEVEL_LO_reserved0_SHIFT 18
-
-/* GIO_AON :: LEVEL_LO :: level [17:00] */
-#define BCHP_GIO_AON_LEVEL_LO_level_MASK 0x0003ffff
-#define BCHP_GIO_AON_LEVEL_LO_level_SHIFT 0
-#define BCHP_GIO_AON_LEVEL_LO_level_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_LO - GENERAL PURPOSE I/O INTERRUPT STATUS FOR GPIO[17:0]
- ***************************************************************************/
-/* GIO_AON :: STAT_LO :: reserved0 [31:18] */
-#define BCHP_GIO_AON_STAT_LO_reserved0_MASK 0xfffc0000
-#define BCHP_GIO_AON_STAT_LO_reserved0_SHIFT 18
-
-/* GIO_AON :: STAT_LO :: irq_status [17:00] */
-#define BCHP_GIO_AON_STAT_LO_irq_status_MASK 0x0003ffff
-#define BCHP_GIO_AON_STAT_LO_irq_status_SHIFT 0
-#define BCHP_GIO_AON_STAT_LO_irq_status_DEFAULT 0x00000000
-
-/***************************************************************************
- *ODEN_EXT - GENERAL PURPOSE I/O OPEN DRAIN ENABLE FOR SGPIO[3:0]
- ***************************************************************************/
-/* GIO_AON :: ODEN_EXT :: reserved0 [31:04] */
-#define BCHP_GIO_AON_ODEN_EXT_reserved0_MASK 0xfffffff0
-#define BCHP_GIO_AON_ODEN_EXT_reserved0_SHIFT 4
-
-/* GIO_AON :: ODEN_EXT :: oden [03:00] */
-#define BCHP_GIO_AON_ODEN_EXT_oden_MASK 0x0000000f
-#define BCHP_GIO_AON_ODEN_EXT_oden_SHIFT 0
-#define BCHP_GIO_AON_ODEN_EXT_oden_DEFAULT 0x00000000
-
-/***************************************************************************
- *DATA_EXT - GENERAL PURPOSE I/O DATA FOR SGPIO[3:0]
- ***************************************************************************/
-/* GIO_AON :: DATA_EXT :: reserved0 [31:04] */
-#define BCHP_GIO_AON_DATA_EXT_reserved0_MASK 0xfffffff0
-#define BCHP_GIO_AON_DATA_EXT_reserved0_SHIFT 4
-
-/* GIO_AON :: DATA_EXT :: data [03:00] */
-#define BCHP_GIO_AON_DATA_EXT_data_MASK 0x0000000f
-#define BCHP_GIO_AON_DATA_EXT_data_SHIFT 0
-#define BCHP_GIO_AON_DATA_EXT_data_DEFAULT 0x00000000
-
-/***************************************************************************
- *IODIR_EXT - GENERAL PURPOSE I/O DIRECTION FOR SGPIO[3:0]
- ***************************************************************************/
-/* GIO_AON :: IODIR_EXT :: reserved0 [31:04] */
-#define BCHP_GIO_AON_IODIR_EXT_reserved0_MASK 0xfffffff0
-#define BCHP_GIO_AON_IODIR_EXT_reserved0_SHIFT 4
-
-/* GIO_AON :: IODIR_EXT :: iodir [03:00] */
-#define BCHP_GIO_AON_IODIR_EXT_iodir_MASK 0x0000000f
-#define BCHP_GIO_AON_IODIR_EXT_iodir_SHIFT 0
-#define BCHP_GIO_AON_IODIR_EXT_iodir_DEFAULT 0x0000000f
-
-/***************************************************************************
- *EC_EXT - GENERAL PURPOSE I/O EDGE CONFIGURATION FOR SGPIO[3:0]
- ***************************************************************************/
-/* GIO_AON :: EC_EXT :: reserved0 [31:04] */
-#define BCHP_GIO_AON_EC_EXT_reserved0_MASK 0xfffffff0
-#define BCHP_GIO_AON_EC_EXT_reserved0_SHIFT 4
-
-/* GIO_AON :: EC_EXT :: edge_config [03:00] */
-#define BCHP_GIO_AON_EC_EXT_edge_config_MASK 0x0000000f
-#define BCHP_GIO_AON_EC_EXT_edge_config_SHIFT 0
-#define BCHP_GIO_AON_EC_EXT_edge_config_DEFAULT 0x00000000
-
-/***************************************************************************
- *EI_EXT - GENERAL PURPOSE I/O EDGE INSENSITIVE FOR SGPIO[3:0]
- ***************************************************************************/
-/* GIO_AON :: EI_EXT :: reserved0 [31:04] */
-#define BCHP_GIO_AON_EI_EXT_reserved0_MASK 0xfffffff0
-#define BCHP_GIO_AON_EI_EXT_reserved0_SHIFT 4
-
-/* GIO_AON :: EI_EXT :: edge_insensitive [03:00] */
-#define BCHP_GIO_AON_EI_EXT_edge_insensitive_MASK 0x0000000f
-#define BCHP_GIO_AON_EI_EXT_edge_insensitive_SHIFT 0
-#define BCHP_GIO_AON_EI_EXT_edge_insensitive_DEFAULT 0x00000000
-
-/***************************************************************************
- *MASK_EXT - GENERAL PURPOSE I/O INTERRUPT MASK FOR SGPIO[3:0]
- ***************************************************************************/
-/* GIO_AON :: MASK_EXT :: reserved0 [31:04] */
-#define BCHP_GIO_AON_MASK_EXT_reserved0_MASK 0xfffffff0
-#define BCHP_GIO_AON_MASK_EXT_reserved0_SHIFT 4
-
-/* GIO_AON :: MASK_EXT :: irq_mask [03:00] */
-#define BCHP_GIO_AON_MASK_EXT_irq_mask_MASK 0x0000000f
-#define BCHP_GIO_AON_MASK_EXT_irq_mask_SHIFT 0
-#define BCHP_GIO_AON_MASK_EXT_irq_mask_DEFAULT 0x00000000
-
-/***************************************************************************
- *LEVEL_EXT - GENERAL PURPOSE I/O INTERRUPT TYPE FOR SGPIO[3:0]
- ***************************************************************************/
-/* GIO_AON :: LEVEL_EXT :: reserved0 [31:04] */
-#define BCHP_GIO_AON_LEVEL_EXT_reserved0_MASK 0xfffffff0
-#define BCHP_GIO_AON_LEVEL_EXT_reserved0_SHIFT 4
-
-/* GIO_AON :: LEVEL_EXT :: level [03:00] */
-#define BCHP_GIO_AON_LEVEL_EXT_level_MASK 0x0000000f
-#define BCHP_GIO_AON_LEVEL_EXT_level_SHIFT 0
-#define BCHP_GIO_AON_LEVEL_EXT_level_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_EXT - GENERAL PURPOSE I/O INTERRUPT STATUS FOR SGPIO[3:0]
- ***************************************************************************/
-/* GIO_AON :: STAT_EXT :: reserved0 [31:04] */
-#define BCHP_GIO_AON_STAT_EXT_reserved0_MASK 0xfffffff0
-#define BCHP_GIO_AON_STAT_EXT_reserved0_SHIFT 4
-
-/* GIO_AON :: STAT_EXT :: irq_status [03:00] */
-#define BCHP_GIO_AON_STAT_EXT_irq_status_MASK 0x0000000f
-#define BCHP_GIO_AON_STAT_EXT_irq_status_SHIFT 0
-#define BCHP_GIO_AON_STAT_EXT_irq_status_DEFAULT 0x00000000
-
-#endif /* #ifndef BCHP_GIO_AON_H__ */
-
-/* End of File */
diff --git a/include/linux/brcmstb/7145a0/bchp_hif_continuation.h b/include/linux/brcmstb/7145a0/bchp_hif_continuation.h
deleted file mode 100644
index 3ebcfa3..0000000
--- a/include/linux/brcmstb/7145a0/bchp_hif_continuation.h
+++ /dev/null
@@ -1,158 +0,0 @@
-/***************************************************************************
- * Copyright (c) 1999-2013, Broadcom Corporation
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
- *
- * Module Description:
- * DO NOT EDIT THIS FILE DIRECTLY
- *
- * This module was generated magically with RDB from a source description
- * file. You must edit the source file for changes to be made to this file.
- *
- *
- * Date: Generated on Sat Apr 6 03:07:50 2013
- * MD5 Checksum d41d8cd98f00b204e9800998ecf8427e
- *
- * Compiled with: RDB Utility combo_header.pl
- * RDB Parser 3.0
- * unknown unknown
- * Perl Interpreter 5.008008
- * Operating System linux
- *
- * Revision History:
- *
- * $brcm_Log: $
- *
- ***************************************************************************/
-
-#ifndef BCHP_HIF_CONTINUATION_H__
-#define BCHP_HIF_CONTINUATION_H__
-
-/***************************************************************************
- *HIF_CONTINUATION - HIF Boot Continuation Registers
- ***************************************************************************/
-#define BCHP_HIF_CONTINUATION_STB_BOOT_HI_ADDR0 0x20450000 /* Higher 8-bit of HIF's Read-only STB Boot Continuation Address 0 Register */
-#define BCHP_HIF_CONTINUATION_STB_BOOT_ADDR0 0x20450004 /* Lower 32-bit of HIF's Read-only STB Boot Continuation Address 0 Register */
-#define BCHP_HIF_CONTINUATION_STB_BOOT_HI_ADDR1 0x20450008 /* Higher 8-bit of HIF's STB Boot Continuation Address 1 Register */
-#define BCHP_HIF_CONTINUATION_STB_BOOT_ADDR1 0x2045000c /* Lower 32-bit of HIF's STB Boot Continuation Address 1 Register */
-#define BCHP_HIF_CONTINUATION_STB_BOOT_HI_ADDR2 0x20450010 /* Higher 8-bit of HIF's STB Boot Continuation Address 2 Register */
-#define BCHP_HIF_CONTINUATION_STB_BOOT_ADDR2 0x20450014 /* Lower 32-bit of HIF's STB Boot Continuation Address 2 Register */
-#define BCHP_HIF_CONTINUATION_STB_BOOT_HI_ADDR3 0x20450018 /* Higher 8-bit of HIF's STB Boot Continuation Address 3 Register */
-#define BCHP_HIF_CONTINUATION_STB_BOOT_ADDR3 0x2045001c /* Lower 32-bit of HIF's STB Boot Continuation Address 3 Register */
-#define BCHP_HIF_CONTINUATION_WEB_BOOT_HI_ADDR0 0x204500f8 /* Higher 8-bit of HIF's WEB Boot Continuation Address 0 Register */
-#define BCHP_HIF_CONTINUATION_WEB_BOOT_ADDR0 0x204500fc /* Lower 32-bit of HIF's WEB Boot Continuation Address 0 Register */
-
-/***************************************************************************
- *STB_BOOT_HI_ADDR0 - Higher 8-bit of HIF's Read-only STB Boot Continuation Address 0 Register
- ***************************************************************************/
-/* HIF_CONTINUATION :: STB_BOOT_HI_ADDR0 :: reserved0 [31:08] */
-#define BCHP_HIF_CONTINUATION_STB_BOOT_HI_ADDR0_reserved0_MASK 0xffffff00
-#define BCHP_HIF_CONTINUATION_STB_BOOT_HI_ADDR0_reserved0_SHIFT 8
-
-/* HIF_CONTINUATION :: STB_BOOT_HI_ADDR0 :: ADDRESS [07:00] */
-#define BCHP_HIF_CONTINUATION_STB_BOOT_HI_ADDR0_ADDRESS_MASK 0x000000ff
-#define BCHP_HIF_CONTINUATION_STB_BOOT_HI_ADDR0_ADDRESS_SHIFT 0
-#define BCHP_HIF_CONTINUATION_STB_BOOT_HI_ADDR0_ADDRESS_DEFAULT 0x00000000
-
-/***************************************************************************
- *STB_BOOT_ADDR0 - Lower 32-bit of HIF's Read-only STB Boot Continuation Address 0 Register
- ***************************************************************************/
-/* HIF_CONTINUATION :: STB_BOOT_ADDR0 :: ADDRESS [31:00] */
-#define BCHP_HIF_CONTINUATION_STB_BOOT_ADDR0_ADDRESS_MASK 0xffffffff
-#define BCHP_HIF_CONTINUATION_STB_BOOT_ADDR0_ADDRESS_SHIFT 0
-#define BCHP_HIF_CONTINUATION_STB_BOOT_ADDR0_ADDRESS_DEFAULT 0xe0000000
-
-/***************************************************************************
- *STB_BOOT_HI_ADDR1 - Higher 8-bit of HIF's STB Boot Continuation Address 1 Register
- ***************************************************************************/
-/* HIF_CONTINUATION :: STB_BOOT_HI_ADDR1 :: reserved0 [31:08] */
-#define BCHP_HIF_CONTINUATION_STB_BOOT_HI_ADDR1_reserved0_MASK 0xffffff00
-#define BCHP_HIF_CONTINUATION_STB_BOOT_HI_ADDR1_reserved0_SHIFT 8
-
-/* HIF_CONTINUATION :: STB_BOOT_HI_ADDR1 :: ADDRESS [07:00] */
-#define BCHP_HIF_CONTINUATION_STB_BOOT_HI_ADDR1_ADDRESS_MASK 0x000000ff
-#define BCHP_HIF_CONTINUATION_STB_BOOT_HI_ADDR1_ADDRESS_SHIFT 0
-#define BCHP_HIF_CONTINUATION_STB_BOOT_HI_ADDR1_ADDRESS_DEFAULT 0x00000000
-
-/***************************************************************************
- *STB_BOOT_ADDR1 - Lower 32-bit of HIF's STB Boot Continuation Address 1 Register
- ***************************************************************************/
-/* HIF_CONTINUATION :: STB_BOOT_ADDR1 :: ADDRESS [31:00] */
-#define BCHP_HIF_CONTINUATION_STB_BOOT_ADDR1_ADDRESS_MASK 0xffffffff
-#define BCHP_HIF_CONTINUATION_STB_BOOT_ADDR1_ADDRESS_SHIFT 0
-#define BCHP_HIF_CONTINUATION_STB_BOOT_ADDR1_ADDRESS_DEFAULT 0xffff0000
-
-/***************************************************************************
- *STB_BOOT_HI_ADDR2 - Higher 8-bit of HIF's STB Boot Continuation Address 2 Register
- ***************************************************************************/
-/* HIF_CONTINUATION :: STB_BOOT_HI_ADDR2 :: reserved0 [31:08] */
-#define BCHP_HIF_CONTINUATION_STB_BOOT_HI_ADDR2_reserved0_MASK 0xffffff00
-#define BCHP_HIF_CONTINUATION_STB_BOOT_HI_ADDR2_reserved0_SHIFT 8
-
-/* HIF_CONTINUATION :: STB_BOOT_HI_ADDR2 :: ADDRESS [07:00] */
-#define BCHP_HIF_CONTINUATION_STB_BOOT_HI_ADDR2_ADDRESS_MASK 0x000000ff
-#define BCHP_HIF_CONTINUATION_STB_BOOT_HI_ADDR2_ADDRESS_SHIFT 0
-#define BCHP_HIF_CONTINUATION_STB_BOOT_HI_ADDR2_ADDRESS_DEFAULT 0x00000000
-
-/***************************************************************************
- *STB_BOOT_ADDR2 - Lower 32-bit of HIF's STB Boot Continuation Address 2 Register
- ***************************************************************************/
-/* HIF_CONTINUATION :: STB_BOOT_ADDR2 :: ADDRESS [31:00] */
-#define BCHP_HIF_CONTINUATION_STB_BOOT_ADDR2_ADDRESS_MASK 0xffffffff
-#define BCHP_HIF_CONTINUATION_STB_BOOT_ADDR2_ADDRESS_SHIFT 0
-#define BCHP_HIF_CONTINUATION_STB_BOOT_ADDR2_ADDRESS_DEFAULT 0xffff0000
-
-/***************************************************************************
- *STB_BOOT_HI_ADDR3 - Higher 8-bit of HIF's STB Boot Continuation Address 3 Register
- ***************************************************************************/
-/* HIF_CONTINUATION :: STB_BOOT_HI_ADDR3 :: reserved0 [31:08] */
-#define BCHP_HIF_CONTINUATION_STB_BOOT_HI_ADDR3_reserved0_MASK 0xffffff00
-#define BCHP_HIF_CONTINUATION_STB_BOOT_HI_ADDR3_reserved0_SHIFT 8
-
-/* HIF_CONTINUATION :: STB_BOOT_HI_ADDR3 :: ADDRESS [07:00] */
-#define BCHP_HIF_CONTINUATION_STB_BOOT_HI_ADDR3_ADDRESS_MASK 0x000000ff
-#define BCHP_HIF_CONTINUATION_STB_BOOT_HI_ADDR3_ADDRESS_SHIFT 0
-#define BCHP_HIF_CONTINUATION_STB_BOOT_HI_ADDR3_ADDRESS_DEFAULT 0x00000000
-
-/***************************************************************************
- *STB_BOOT_ADDR3 - Lower 32-bit of HIF's STB Boot Continuation Address 3 Register
- ***************************************************************************/
-/* HIF_CONTINUATION :: STB_BOOT_ADDR3 :: ADDRESS [31:00] */
-#define BCHP_HIF_CONTINUATION_STB_BOOT_ADDR3_ADDRESS_MASK 0xffffffff
-#define BCHP_HIF_CONTINUATION_STB_BOOT_ADDR3_ADDRESS_SHIFT 0
-#define BCHP_HIF_CONTINUATION_STB_BOOT_ADDR3_ADDRESS_DEFAULT 0xffff0000
-
-/***************************************************************************
- *WEB_BOOT_HI_ADDR0 - Higher 8-bit of HIF's WEB Boot Continuation Address 0 Register
- ***************************************************************************/
-/* HIF_CONTINUATION :: WEB_BOOT_HI_ADDR0 :: reserved0 [31:08] */
-#define BCHP_HIF_CONTINUATION_WEB_BOOT_HI_ADDR0_reserved0_MASK 0xffffff00
-#define BCHP_HIF_CONTINUATION_WEB_BOOT_HI_ADDR0_reserved0_SHIFT 8
-
-/* HIF_CONTINUATION :: WEB_BOOT_HI_ADDR0 :: ADDRESS [07:00] */
-#define BCHP_HIF_CONTINUATION_WEB_BOOT_HI_ADDR0_ADDRESS_MASK 0x000000ff
-#define BCHP_HIF_CONTINUATION_WEB_BOOT_HI_ADDR0_ADDRESS_SHIFT 0
-#define BCHP_HIF_CONTINUATION_WEB_BOOT_HI_ADDR0_ADDRESS_DEFAULT 0x00000000
-
-/***************************************************************************
- *WEB_BOOT_ADDR0 - Lower 32-bit of HIF's WEB Boot Continuation Address 0 Register
- ***************************************************************************/
-/* HIF_CONTINUATION :: WEB_BOOT_ADDR0 :: ADDRESS [31:00] */
-#define BCHP_HIF_CONTINUATION_WEB_BOOT_ADDR0_ADDRESS_MASK 0xffffffff
-#define BCHP_HIF_CONTINUATION_WEB_BOOT_ADDR0_ADDRESS_SHIFT 0
-#define BCHP_HIF_CONTINUATION_WEB_BOOT_ADDR0_ADDRESS_DEFAULT 0xffff0000
-
-#endif /* #ifndef BCHP_HIF_CONTINUATION_H__ */
-
-/* End of File */
diff --git a/include/linux/brcmstb/7145a0/bchp_hif_cpubiuctrl.h b/include/linux/brcmstb/7145a0/bchp_hif_cpubiuctrl.h
deleted file mode 100644
index 485c445..0000000
--- a/include/linux/brcmstb/7145a0/bchp_hif_cpubiuctrl.h
+++ /dev/null
@@ -1,3222 +0,0 @@
-/***************************************************************************
- * Copyright (c) 1999-2013, Broadcom Corporation
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
- *
- * Module Description:
- * DO NOT EDIT THIS FILE DIRECTLY
- *
- * This module was generated magically with RDB from a source description
- * file. You must edit the source file for changes to be made to this file.
- *
- *
- * Date: Generated on Sat Apr 6 03:07:50 2013
- * MD5 Checksum d41d8cd98f00b204e9800998ecf8427e
- *
- * Compiled with: RDB Utility combo_header.pl
- * RDB Parser 3.0
- * unknown unknown
- * Perl Interpreter 5.008008
- * Operating System linux
- *
- * Revision History:
- *
- * $brcm_Log: $
- *
- ***************************************************************************/
-
-#ifndef BCHP_HIF_CPUBIUCTRL_H__
-#define BCHP_HIF_CPUBIUCTRL_H__
-
-/***************************************************************************
- *HIF_CPUBIUCTRL - CPU BIU Conrol registers
- ***************************************************************************/
-#define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_ULIMT0 0x203d2400 /* CPU Address Range0 Upper Limit Mapping Register */
-#define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_LLIMT0 0x203d2404 /* CPU Address Range0 Lower Limit Mapping Register */
-#define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_ULIMT1 0x203d2408 /* CPU Address Range1 Upper Limit Mapping Register */
-#define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_LLIMT1 0x203d240c /* CPU Address Range1 Lower Limit Mapping Register */
-#define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_ULIMT2 0x203d2410 /* CPU Address Range2 Upper Limit Mapping Register */
-#define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_LLIMT2 0x203d2414 /* CPU Address Range2 Lower Limit Mapping Register */
-#define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_ULIMT3 0x203d2418 /* CPU Address Range3 Upper Limit Mapping Register */
-#define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_LLIMT3 0x203d241c /* CPU Address Range3 Lower Limit Mapping Register */
-#define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_ULIMT4 0x203d2420 /* CPU Address Range4 Upper Limit Mapping Register */
-#define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_LLIMT4 0x203d2424 /* CPU Address Range4 Lower Limit Mapping Register */
-#define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_ULIMT5 0x203d2428 /* CPU Address Range5 Upper Limit Mapping Register */
-#define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_LLIMT5 0x203d242c /* CPU Address Range5 Lower Limit Mapping Register */
-#define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_ULIMT6 0x203d2430 /* CPU Address Range6 Upper Limit Mapping Register */
-#define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_LLIMT6 0x203d2434 /* CPU Address Range6 Lower Limit Mapping Register */
-#define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_ULIMT7 0x203d2438 /* CPU Address Range7 Upper Limit Mapping Register */
-#define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_LLIMT7 0x203d243c /* CPU Address Range7 Lower Limit Mapping Register */
-#define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_ULIMT8 0x203d2440 /* CPU Address Range8 Upper Limit Mapping Register */
-#define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_LLIMT8 0x203d2444 /* CPU Address Range8 Lower Limit Mapping Register */
-#define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_ULIMT9 0x203d2448 /* CPU Address Range9 Upper Limit Mapping Register */
-#define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_LLIMT9 0x203d244c /* CPU Address Range9 Lower Limit Mapping Register */
-#define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_ULIMT10 0x203d2450 /* CPU Address Range10 Upper Limit Mapping Register */
-#define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_LLIMT10 0x203d2454 /* CPU Address Range10 Lower Limit Mapping Register */
-#define BCHP_HIF_CPUBIUCTRL_SECURE_RESET_HNDSHAKE_REG 0x203d2458 /* CPU Secure Soft Reset Handshake Register */
-#define BCHP_HIF_CPUBIUCTRL_SECURE_SOFT_RESET_REG 0x203d245c /* CPU Secure Soft Reset Register */
-#define BCHP_HIF_CPUBIUCTRL_CPU_ACCESS_RIGHT_VIOL_ADDR0 0x203d2460 /* CPU Access Rights Violation Address0 Register */
-#define BCHP_HIF_CPUBIUCTRL_CPU_ACCESS_RIGHT_VIOL_UPPER_ADDR0 0x203d2464 /* CPU Access Rights Violation Upper Address0 Register */
-#define BCHP_HIF_CPUBIUCTRL_CPU_ACCESS_RIGHT_VIOL_DETAIL_ADDR0 0x203d2468 /* CPU Access Rights Violation Transaction Detail0 Register */
-#define BCHP_HIF_CPUBIUCTRL_CPU_ACCESS_RIGHT_VIOL_ADDR1 0x203d246c /* CPU Access Rights Violation Address1 Register */
-#define BCHP_HIF_CPUBIUCTRL_CPU_ACCESS_RIGHT_VIOL_UPPER_ADDR1 0x203d2470 /* CPU Access Rights Violation Upper Address1 Register */
-#define BCHP_HIF_CPUBIUCTRL_CPU_ACCESS_RIGHT_VIOL_DETAIL_ADDR1 0x203d2474 /* CPU Access Rights Violation Transaction Detail1 Register */
-#define BCHP_HIF_CPUBIUCTRL_RAC_CONFIG0_REG 0x203d2478 /* Read Ahead Cache Configuration0 Register */
-#define BCHP_HIF_CPUBIUCTRL_RAC_CONFIG1_REG 0x203d247c /* Read Ahead Cache Configuration1 Register */
-#define BCHP_HIF_CPUBIUCTRL_RAC_FLUSH_REG 0x203d2480 /* Read Ahead Cache Flush Register */
-#define BCHP_HIF_CPUBIUCTRL_CPU_POWER_CONFIG_REG 0x203d2484 /* CPU Power Configuration Register */
-#define BCHP_HIF_CPUBIUCTRL_CPU0_PWR_ZONE_CNTRL_REG 0x203d2488 /* CPU0 Power Zone Control Register */
-#define BCHP_HIF_CPUBIUCTRL_CPU1_PWR_ZONE_CNTRL_REG 0x203d248c /* CPU1 Power Zone Control Register */
-#define BCHP_HIF_CPUBIUCTRL_CPU2_PWR_ZONE_CNTRL_REG 0x203d2490 /* CPU2 Power Zone Control Register */
-#define BCHP_HIF_CPUBIUCTRL_CPU3_PWR_ZONE_CNTRL_REG 0x203d2494 /* CPU3 Power Zone Control Register */
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_PWR_ZONE_CNTRL_REG 0x203d2498 /* L2 and BIU Power Zone Control Register */
-#define BCHP_HIF_CPUBIUCTRL_CPU0_PWR_ZONE_CONFIG1_REG 0x203d249c /* CPU0 Power Zone Config1 Registers */
-#define BCHP_HIF_CPUBIUCTRL_CPU0_PWR_ZONE_CONFIG2_REG 0x203d24a0 /* CPU0 Power Zone Config2 Registers */
-#define BCHP_HIF_CPUBIUCTRL_CPU1_PWR_ZONE_CONFIG1_REG 0x203d24a4 /* CPU1 Power Zone Config1 Registers */
-#define BCHP_HIF_CPUBIUCTRL_CPU1_PWR_ZONE_CONFIG2_REG 0x203d24a8 /* CPU1 Power Zone Config2 Registers */
-#define BCHP_HIF_CPUBIUCTRL_CPU2_PWR_ZONE_CONFIG1_REG 0x203d24ac /* CPU2 Power Zone Config1 Registers */
-#define BCHP_HIF_CPUBIUCTRL_CPU2_PWR_ZONE_CONFIG2_REG 0x203d24b0 /* CPU2 Power Zone Config2 Registers */
-#define BCHP_HIF_CPUBIUCTRL_CPU3_PWR_ZONE_CONFIG1_REG 0x203d24b4 /* CPU3 Power Zone Config1 Registers */
-#define BCHP_HIF_CPUBIUCTRL_CPU3_PWR_ZONE_CONFIG2_REG 0x203d24b8 /* CPU3 Power Zone Config2 Registers */
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_PWR_ZONE_CONFIG1_REG 0x203d24bc /* L2/BIU Power Zone Config1 Registers */
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_PWR_ZONE_CONFIG2_REG 0x203d24c0 /* L2/BIU Power Zone Config2 Registers */
-#define BCHP_HIF_CPUBIUCTRL_CPU0_PWR_FREQ_SCALAR_CTRL_REG 0x203d24c4 /* CPU0 BPCM Frequency Scalar Control Register */
-#define BCHP_HIF_CPUBIUCTRL_CPU1_PWR_FREQ_SCALAR_CTRL_REG 0x203d24c8 /* CPU1 BPCM Frequency Scalar Control Register */
-#define BCHP_HIF_CPUBIUCTRL_CPU2_PWR_FREQ_SCALAR_CTRL_REG 0x203d24cc /* CPU2 BPCM Frequency Scalar Control Register */
-#define BCHP_HIF_CPUBIUCTRL_CPU3_PWR_FREQ_SCALAR_CTRL_REG 0x203d24d0 /* CPU3 BPCM Frequency Scalar Control Register */
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_PWR_FREQ_SCALAR_CTRL_REG 0x203d24d4 /* L2/BIU BPCM Frequency Scalar Control Register */
-#define BCHP_HIF_CPUBIUCTRL_CPU0_BPCM_ID 0x203d24d8 /* CPU0 BPCM ID Register */
-#define BCHP_HIF_CPUBIUCTRL_CPU0_BPCM_CAPABILITY 0x203d24dc /* CPU0 BPCM Capability Register */
-#define BCHP_HIF_CPUBIUCTRL_CPU0_BPCM_CONTROL 0x203d24e0 /* CPU0 BPCM Control Register */
-#define BCHP_HIF_CPUBIUCTRL_CPU0_BPCM_STATUS 0x203d24e4 /* CPU0 BPCM Status Register */
-#define BCHP_HIF_CPUBIUCTRL_CPU0_AVS_ROSC_CONTROL 0x203d24e8 /* CPU0 Ring Oscillator Control Register */
-#define BCHP_HIF_CPUBIUCTRL_CPU0_AVS_ROSC_THRESHOLD 0x203d24ec /* CPU0 Event Counter Threshold Register */
-#define BCHP_HIF_CPUBIUCTRL_CPU0_AVS_ROSC_COUNT 0x203d24f0 /* CPU0 Event Counter Count Register */
-#define BCHP_HIF_CPUBIUCTRL_CPU0_AVS_PWD_CONTROL 0x203d24f4 /* CPU0 PWD control Register */
-#define BCHP_HIF_CPUBIUCTRL_CPU1_BPCM_ID 0x203d24f8 /* CPU1 BPCM ID Register */
-#define BCHP_HIF_CPUBIUCTRL_CPU1_BPCM_CAPABILITY 0x203d24fc /* CPU1 BPCM Capability Register */
-#define BCHP_HIF_CPUBIUCTRL_CPU1_BPCM_CONTROL 0x203d2500 /* CPU1 BPCM Control Register */
-#define BCHP_HIF_CPUBIUCTRL_CPU1_BPCM_STATUS 0x203d2504 /* CPU1 BPCM Status Register */
-#define BCHP_HIF_CPUBIUCTRL_CPU1_AVS_ROSC_CONTROL 0x203d2508 /* CPU1 Ring Oscillator Control Register */
-#define BCHP_HIF_CPUBIUCTRL_CPU1_AVS_ROSC_THRESHOLD 0x203d250c /* CPU1 Event Counter Threshold Register */
-#define BCHP_HIF_CPUBIUCTRL_CPU1_AVS_ROSC_COUNT 0x203d2510 /* CPU1 Event Counter Count Register */
-#define BCHP_HIF_CPUBIUCTRL_CPU1_AVS_PWD_CONTROL 0x203d2514 /* CPU1 PWD control Register */
-#define BCHP_HIF_CPUBIUCTRL_CPU2_BPCM_ID 0x203d2518 /* CPU2 BPCM ID Register */
-#define BCHP_HIF_CPUBIUCTRL_CPU2_BPCM_CAPABILITY 0x203d251c /* CPU2 BPCM Capability Register */
-#define BCHP_HIF_CPUBIUCTRL_CPU2_BPCM_CONTROL 0x203d2520 /* CPU2 BPCM Control Register */
-#define BCHP_HIF_CPUBIUCTRL_CPU2_BPCM_STATUS 0x203d2524 /* CPU2 BPCM Status Register */
-#define BCHP_HIF_CPUBIUCTRL_CPU2_AVS_ROSC_CONTROL 0x203d2528 /* CPU2 Ring Oscillator Control Register */
-#define BCHP_HIF_CPUBIUCTRL_CPU2_AVS_ROSC_THRESHOLD 0x203d252c /* CPU2 Event Counter Threshold Register */
-#define BCHP_HIF_CPUBIUCTRL_CPU2_AVS_ROSC_COUNT 0x203d2530 /* CPU2 Event Counter Count Register */
-#define BCHP_HIF_CPUBIUCTRL_CPU2_AVS_PWD_CONTROL 0x203d2534 /* CPU2 PWD control Register */
-#define BCHP_HIF_CPUBIUCTRL_CPU3_BPCM_ID 0x203d2538 /* CPU3 BPCM ID Register */
-#define BCHP_HIF_CPUBIUCTRL_CPU3_BPCM_CAPABILITY 0x203d253c /* CPU3 BPCM Capability Register */
-#define BCHP_HIF_CPUBIUCTRL_CPU3_BPCM_CONTROL 0x203d2540 /* CPU3 BPCM Control Register */
-#define BCHP_HIF_CPUBIUCTRL_CPU3_BPCM_STATUS 0x203d2544 /* CPU3 BPCM Status Register */
-#define BCHP_HIF_CPUBIUCTRL_CPU3_AVS_ROSC_CONTROL 0x203d2548 /* CPU3 Ring Oscillator Control Register */
-#define BCHP_HIF_CPUBIUCTRL_CPU3_AVS_ROSC_THRESHOLD 0x203d254c /* CPU3 Event Counter Threshold Register */
-#define BCHP_HIF_CPUBIUCTRL_CPU3_AVS_ROSC_COUNT 0x203d2550 /* CPU3 Event Counter Count Register */
-#define BCHP_HIF_CPUBIUCTRL_CPU3_AVS_PWD_CONTROL 0x203d2554 /* CPU3 PWD control Register */
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_BPCM_ID 0x203d2558 /* L2BIU BPCM ID Register */
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_BPCM_CAPABILITY 0x203d255c /* L2BIU BPCM Capability Register */
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_BPCM_CONTROL 0x203d2560 /* L2BIU BPCM Control Register */
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_BPCM_STATUS 0x203d2564 /* L2BIU BPCM Status Register */
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_AVS_ROSC_CONTROL 0x203d2568 /* L2BIU Ring Oscillator Control Register */
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_AVS_ROSC_THRESHOLD 0x203d256c /* L2BIU Event Counter Threshold Register */
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_AVS_ROSC_COUNT 0x203d2570 /* L2BIU Event Counter Count Register */
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_AVS_PWD_CONTROL 0x203d2574 /* L2BIU PWD control Register */
-#define BCHP_HIF_CPUBIUCTRL_CPU_RESET_CONFIG_REG 0x203d2578 /* CPU Reset Configuration Register */
-#define BCHP_HIF_CPUBIUCTRL_CPU_CLOCK_CONFIG_REG 0x203d257c /* CPU Clock Configuration Register */
-#define BCHP_HIF_CPUBIUCTRL_CPU_MISC_CONFIG_REG 0x203d2580 /* CPU Miscellaneous Configuration Register */
-#define BCHP_HIF_CPUBIUCTRL_CPU_CREDIT_REG 0x203d2584 /* CPU Request Credit Register */
-#define BCHP_HIF_CPUBIUCTRL_CPU_THERM_THROTTLE_REG0 0x203d2588 /* CPU Thermal Throttling Register0 */
-#define BCHP_HIF_CPUBIUCTRL_CPU_THERM_THROTTLE_REG1 0x203d258c /* CPU Thermal Throttling Register1 */
-#define BCHP_HIF_CPUBIUCTRL_CPU_THERM_THROTTLE_REG2 0x203d2590 /* CPU Thermal Throttling Register2 */
-#define BCHP_HIF_CPUBIUCTRL_CPU_THERM_THROTTLE_REG3 0x203d2594 /* CPU Thermal Throttling Register3 */
-#define BCHP_HIF_CPUBIUCTRL_CPU_DEFEATURE_REG 0x203d2598 /* CPU Defeature Register */
-#define BCHP_HIF_CPUBIUCTRL_CPU_DEFEATURE_KEY_REG 0x203d259c /* CPU Defeature Key Register */
-#define BCHP_HIF_CPUBIUCTRL_CPU_DEBUGROMADDR_REG 0x203d25a0 /* CPU Debug ROM Address Register */
-#define BCHP_HIF_CPUBIUCTRL_CPU_DEBUGSELFADDR_REG 0x203d25a4 /* CPU Debug SELF Address Register */
-#define BCHP_HIF_CPUBIUCTRL_CPU_DEBUG_TRACECTRL_REG 0x203d25a8 /* CPU Debug Trace Control Registeer */
-#define BCHP_HIF_CPUBIUCTRL_CPU_AXICONFIG_REG 0x203d25ac /* CPU AXI Config Register */
-#define BCHP_HIF_CPUBIUCTRL_CPU_REVISION_REG 0x203d25b0 /* CPU Revision Register */
-#define BCHP_HIF_CPUBIUCTRL_CPU_SCRATCH_REG 0x203d27fc /* Scratch Register */
-
-/***************************************************************************
- *CPU_BUS_RANGE_ULIMT0 - CPU Address Range0 Upper Limit Mapping Register
- ***************************************************************************/
-/* HIF_CPUBIUCTRL :: CPU_BUS_RANGE_ULIMT0 :: ULIMIT [31:04] */
-#define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_ULIMT0_ULIMIT_MASK 0xfffffff0
-#define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_ULIMT0_ULIMIT_SHIFT 4
-#define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_ULIMT0_ULIMIT_DEFAULT 0x000fffff
-
-/* HIF_CPUBIUCTRL :: CPU_BUS_RANGE_ULIMT0 :: BUSNUM [03:00] */
-#define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_ULIMT0_BUSNUM_MASK 0x0000000f
-#define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_ULIMT0_BUSNUM_SHIFT 0
-#define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_ULIMT0_BUSNUM_DEFAULT 0x00000002
-
-/***************************************************************************
- *CPU_BUS_RANGE_LLIMT0 - CPU Address Range0 Lower Limit Mapping Register
- ***************************************************************************/
-/* HIF_CPUBIUCTRL :: CPU_BUS_RANGE_LLIMT0 :: LLIMIT [31:04] */
-#define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_LLIMT0_LLIMIT_MASK 0xfffffff0
-#define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_LLIMT0_LLIMIT_SHIFT 4
-#define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_LLIMT0_LLIMIT_DEFAULT 0x000ffe00
-
-/* HIF_CPUBIUCTRL :: CPU_BUS_RANGE_LLIMT0 :: reserved0 [03:01] */
-#define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_LLIMT0_reserved0_MASK 0x0000000e
-#define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_LLIMT0_reserved0_SHIFT 1
-
-/* HIF_CPUBIUCTRL :: CPU_BUS_RANGE_LLIMT0 :: UBUSCDBIT [00:00] */
-#define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_LLIMT0_UBUSCDBIT_MASK 0x00000001
-#define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_LLIMT0_UBUSCDBIT_SHIFT 0
-#define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_LLIMT0_UBUSCDBIT_DEFAULT 0x00000000
-
-/***************************************************************************
- *CPU_BUS_RANGE_ULIMT1 - CPU Address Range1 Upper Limit Mapping Register
- ***************************************************************************/
-/* HIF_CPUBIUCTRL :: CPU_BUS_RANGE_ULIMT1 :: ULIMIT [31:04] */
-#define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_ULIMT1_ULIMIT_MASK 0xfffffff0
-#define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_ULIMT1_ULIMIT_SHIFT 4
-#define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_ULIMT1_ULIMIT_DEFAULT 0x000f1fff
-
-/* HIF_CPUBIUCTRL :: CPU_BUS_RANGE_ULIMT1 :: BUSNUM [03:00] */
-#define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_ULIMT1_BUSNUM_MASK 0x0000000f
-#define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_ULIMT1_BUSNUM_SHIFT 0
-#define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_ULIMT1_BUSNUM_DEFAULT 0x00000002
-
-/***************************************************************************
- *CPU_BUS_RANGE_LLIMT1 - CPU Address Range1 Lower Limit Mapping Register
- ***************************************************************************/
-/* HIF_CPUBIUCTRL :: CPU_BUS_RANGE_LLIMT1 :: LLIMIT [31:04] */
-#define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_LLIMT1_LLIMIT_MASK 0xfffffff0
-#define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_LLIMT1_LLIMIT_SHIFT 4
-#define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_LLIMT1_LLIMIT_DEFAULT 0x000c0000
-
-/* HIF_CPUBIUCTRL :: CPU_BUS_RANGE_LLIMT1 :: reserved0 [03:01] */
-#define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_LLIMT1_reserved0_MASK 0x0000000e
-#define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_LLIMT1_reserved0_SHIFT 1
-
-/* HIF_CPUBIUCTRL :: CPU_BUS_RANGE_LLIMT1 :: UBUSCDBIT [00:00] */
-#define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_LLIMT1_UBUSCDBIT_MASK 0x00000001
-#define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_LLIMT1_UBUSCDBIT_SHIFT 0
-#define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_LLIMT1_UBUSCDBIT_DEFAULT 0x00000000
-
-/***************************************************************************
- *CPU_BUS_RANGE_ULIMT2 - CPU Address Range2 Upper Limit Mapping Register
- ***************************************************************************/
-/* HIF_CPUBIUCTRL :: CPU_BUS_RANGE_ULIMT2 :: ULIMIT [31:04] */
-#define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_ULIMT2_ULIMIT_MASK 0xfffffff0
-#define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_ULIMT2_ULIMIT_SHIFT 4
-#define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_ULIMT2_ULIMIT_DEFAULT 0x00bfffff
-
-/* HIF_CPUBIUCTRL :: CPU_BUS_RANGE_ULIMT2 :: BUSNUM [03:00] */
-#define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_ULIMT2_BUSNUM_MASK 0x0000000f
-#define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_ULIMT2_BUSNUM_SHIFT 0
-#define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_ULIMT2_BUSNUM_DEFAULT 0x00000002
-
-/***************************************************************************
- *CPU_BUS_RANGE_LLIMT2 - CPU Address Range2 Lower Limit Mapping Register
- ***************************************************************************/
-/* HIF_CPUBIUCTRL :: CPU_BUS_RANGE_LLIMT2 :: LLIMIT [31:04] */
-#define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_LLIMT2_LLIMIT_MASK 0xfffffff0
-#define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_LLIMT2_LLIMIT_SHIFT 4
-#define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_LLIMT2_LLIMIT_DEFAULT 0x00600000
-
-/* HIF_CPUBIUCTRL :: CPU_BUS_RANGE_LLIMT2 :: reserved0 [03:01] */
-#define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_LLIMT2_reserved0_MASK 0x0000000e
-#define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_LLIMT2_reserved0_SHIFT 1
-
-/* HIF_CPUBIUCTRL :: CPU_BUS_RANGE_LLIMT2 :: UBUSCDBIT [00:00] */
-#define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_LLIMT2_UBUSCDBIT_MASK 0x00000001
-#define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_LLIMT2_UBUSCDBIT_SHIFT 0
-#define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_LLIMT2_UBUSCDBIT_DEFAULT 0x00000000
-
-/***************************************************************************
- *CPU_BUS_RANGE_ULIMT3 - CPU Address Range3 Upper Limit Mapping Register
- ***************************************************************************/
-/* HIF_CPUBIUCTRL :: CPU_BUS_RANGE_ULIMT3 :: ULIMIT [31:04] */
-#define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_ULIMT3_ULIMIT_MASK 0xfffffff0
-#define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_ULIMT3_ULIMIT_SHIFT 4
-#define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_ULIMT3_ULIMIT_DEFAULT 0x0003ffff
-
-/* HIF_CPUBIUCTRL :: CPU_BUS_RANGE_ULIMT3 :: BUSNUM [03:00] */
-#define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_ULIMT3_BUSNUM_MASK 0x0000000f
-#define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_ULIMT3_BUSNUM_SHIFT 0
-#define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_ULIMT3_BUSNUM_DEFAULT 0x00000004
-
-/***************************************************************************
- *CPU_BUS_RANGE_LLIMT3 - CPU Address Range3 Lower Limit Mapping Register
- ***************************************************************************/
-/* HIF_CPUBIUCTRL :: CPU_BUS_RANGE_LLIMT3 :: LLIMIT [31:04] */
-#define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_LLIMT3_LLIMIT_MASK 0xfffffff0
-#define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_LLIMT3_LLIMIT_SHIFT 4
-#define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_LLIMT3_LLIMIT_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: CPU_BUS_RANGE_LLIMT3 :: reserved0 [03:01] */
-#define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_LLIMT3_reserved0_MASK 0x0000000e
-#define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_LLIMT3_reserved0_SHIFT 1
-
-/* HIF_CPUBIUCTRL :: CPU_BUS_RANGE_LLIMT3 :: UBUSCDBIT [00:00] */
-#define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_LLIMT3_UBUSCDBIT_MASK 0x00000001
-#define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_LLIMT3_UBUSCDBIT_SHIFT 0
-#define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_LLIMT3_UBUSCDBIT_DEFAULT 0x00000000
-
-/***************************************************************************
- *CPU_BUS_RANGE_ULIMT4 - CPU Address Range4 Upper Limit Mapping Register
- ***************************************************************************/
-/* HIF_CPUBIUCTRL :: CPU_BUS_RANGE_ULIMT4 :: ULIMIT [31:04] */
-#define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_ULIMT4_ULIMIT_MASK 0xfffffff0
-#define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_ULIMT4_ULIMIT_SHIFT 4
-#define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_ULIMT4_ULIMIT_DEFAULT 0x001bffff
-
-/* HIF_CPUBIUCTRL :: CPU_BUS_RANGE_ULIMT4 :: BUSNUM [03:00] */
-#define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_ULIMT4_BUSNUM_MASK 0x0000000f
-#define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_ULIMT4_BUSNUM_SHIFT 0
-#define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_ULIMT4_BUSNUM_DEFAULT 0x00000004
-
-/***************************************************************************
- *CPU_BUS_RANGE_LLIMT4 - CPU Address Range4 Lower Limit Mapping Register
- ***************************************************************************/
-/* HIF_CPUBIUCTRL :: CPU_BUS_RANGE_LLIMT4 :: LLIMIT [31:04] */
-#define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_LLIMT4_LLIMIT_MASK 0xfffffff0
-#define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_LLIMT4_LLIMIT_SHIFT 4
-#define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_LLIMT4_LLIMIT_DEFAULT 0x00100000
-
-/* HIF_CPUBIUCTRL :: CPU_BUS_RANGE_LLIMT4 :: reserved0 [03:01] */
-#define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_LLIMT4_reserved0_MASK 0x0000000e
-#define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_LLIMT4_reserved0_SHIFT 1
-
-/* HIF_CPUBIUCTRL :: CPU_BUS_RANGE_LLIMT4 :: UBUSCDBIT [00:00] */
-#define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_LLIMT4_UBUSCDBIT_MASK 0x00000001
-#define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_LLIMT4_UBUSCDBIT_SHIFT 0
-#define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_LLIMT4_UBUSCDBIT_DEFAULT 0x00000000
-
-/***************************************************************************
- *CPU_BUS_RANGE_ULIMT5 - CPU Address Range5 Upper Limit Mapping Register
- ***************************************************************************/
-/* HIF_CPUBIUCTRL :: CPU_BUS_RANGE_ULIMT5 :: ULIMIT [31:04] */
-#define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_ULIMT5_ULIMIT_MASK 0xfffffff0
-#define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_ULIMT5_ULIMIT_SHIFT 4
-#define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_ULIMT5_ULIMIT_DEFAULT 0x0007ffff
-
-/* HIF_CPUBIUCTRL :: CPU_BUS_RANGE_ULIMT5 :: BUSNUM [03:00] */
-#define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_ULIMT5_BUSNUM_MASK 0x0000000f
-#define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_ULIMT5_BUSNUM_SHIFT 0
-#define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_ULIMT5_BUSNUM_DEFAULT 0x00000005
-
-/***************************************************************************
- *CPU_BUS_RANGE_LLIMT5 - CPU Address Range5 Lower Limit Mapping Register
- ***************************************************************************/
-/* HIF_CPUBIUCTRL :: CPU_BUS_RANGE_LLIMT5 :: LLIMIT [31:04] */
-#define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_LLIMT5_LLIMIT_MASK 0xfffffff0
-#define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_LLIMT5_LLIMIT_SHIFT 4
-#define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_LLIMT5_LLIMIT_DEFAULT 0x00040000
-
-/* HIF_CPUBIUCTRL :: CPU_BUS_RANGE_LLIMT5 :: reserved0 [03:01] */
-#define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_LLIMT5_reserved0_MASK 0x0000000e
-#define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_LLIMT5_reserved0_SHIFT 1
-
-/* HIF_CPUBIUCTRL :: CPU_BUS_RANGE_LLIMT5 :: UBUSCDBIT [00:00] */
-#define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_LLIMT5_UBUSCDBIT_MASK 0x00000001
-#define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_LLIMT5_UBUSCDBIT_SHIFT 0
-#define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_LLIMT5_UBUSCDBIT_DEFAULT 0x00000000
-
-/***************************************************************************
- *CPU_BUS_RANGE_ULIMT6 - CPU Address Range6 Upper Limit Mapping Register
- ***************************************************************************/
-/* HIF_CPUBIUCTRL :: CPU_BUS_RANGE_ULIMT6 :: ULIMIT [31:04] */
-#define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_ULIMT6_ULIMIT_MASK 0xfffffff0
-#define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_ULIMT6_ULIMIT_SHIFT 4
-#define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_ULIMT6_ULIMIT_DEFAULT 0x003bffff
-
-/* HIF_CPUBIUCTRL :: CPU_BUS_RANGE_ULIMT6 :: BUSNUM [03:00] */
-#define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_ULIMT6_BUSNUM_MASK 0x0000000f
-#define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_ULIMT6_BUSNUM_SHIFT 0
-#define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_ULIMT6_BUSNUM_DEFAULT 0x00000005
-
-/***************************************************************************
- *CPU_BUS_RANGE_LLIMT6 - CPU Address Range6 Lower Limit Mapping Register
- ***************************************************************************/
-/* HIF_CPUBIUCTRL :: CPU_BUS_RANGE_LLIMT6 :: LLIMIT [31:04] */
-#define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_LLIMT6_LLIMIT_MASK 0xfffffff0
-#define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_LLIMT6_LLIMIT_SHIFT 4
-#define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_LLIMT6_LLIMIT_DEFAULT 0x00300000
-
-/* HIF_CPUBIUCTRL :: CPU_BUS_RANGE_LLIMT6 :: reserved0 [03:01] */
-#define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_LLIMT6_reserved0_MASK 0x0000000e
-#define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_LLIMT6_reserved0_SHIFT 1
-
-/* HIF_CPUBIUCTRL :: CPU_BUS_RANGE_LLIMT6 :: UBUSCDBIT [00:00] */
-#define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_LLIMT6_UBUSCDBIT_MASK 0x00000001
-#define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_LLIMT6_UBUSCDBIT_SHIFT 0
-#define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_LLIMT6_UBUSCDBIT_DEFAULT 0x00000000
-
-/***************************************************************************
- *CPU_BUS_RANGE_ULIMT7 - CPU Address Range7 Upper Limit Mapping Register
- ***************************************************************************/
-/* HIF_CPUBIUCTRL :: CPU_BUS_RANGE_ULIMT7 :: ULIMIT [31:04] */
-#define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_ULIMT7_ULIMIT_MASK 0xfffffff0
-#define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_ULIMT7_ULIMIT_SHIFT 4
-#define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_ULIMT7_ULIMIT_DEFAULT 0x000bffff
-
-/* HIF_CPUBIUCTRL :: CPU_BUS_RANGE_ULIMT7 :: BUSNUM [03:00] */
-#define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_ULIMT7_BUSNUM_MASK 0x0000000f
-#define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_ULIMT7_BUSNUM_SHIFT 0
-#define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_ULIMT7_BUSNUM_DEFAULT 0x00000006
-
-/***************************************************************************
- *CPU_BUS_RANGE_LLIMT7 - CPU Address Range7 Lower Limit Mapping Register
- ***************************************************************************/
-/* HIF_CPUBIUCTRL :: CPU_BUS_RANGE_LLIMT7 :: LLIMIT [31:04] */
-#define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_LLIMT7_LLIMIT_MASK 0xfffffff0
-#define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_LLIMT7_LLIMIT_SHIFT 4
-#define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_LLIMT7_LLIMIT_DEFAULT 0x00080000
-
-/* HIF_CPUBIUCTRL :: CPU_BUS_RANGE_LLIMT7 :: reserved0 [03:01] */
-#define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_LLIMT7_reserved0_MASK 0x0000000e
-#define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_LLIMT7_reserved0_SHIFT 1
-
-/* HIF_CPUBIUCTRL :: CPU_BUS_RANGE_LLIMT7 :: UBUSCDBIT [00:00] */
-#define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_LLIMT7_UBUSCDBIT_MASK 0x00000001
-#define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_LLIMT7_UBUSCDBIT_SHIFT 0
-#define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_LLIMT7_UBUSCDBIT_DEFAULT 0x00000000
-
-/***************************************************************************
- *CPU_BUS_RANGE_ULIMT8 - CPU Address Range8 Upper Limit Mapping Register
- ***************************************************************************/
-/* HIF_CPUBIUCTRL :: CPU_BUS_RANGE_ULIMT8 :: ULIMIT [31:04] */
-#define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_ULIMT8_ULIMIT_MASK 0xfffffff0
-#define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_ULIMT8_ULIMIT_SHIFT 4
-#define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_ULIMT8_ULIMIT_DEFAULT 0x00cbffff
-
-/* HIF_CPUBIUCTRL :: CPU_BUS_RANGE_ULIMT8 :: BUSNUM [03:00] */
-#define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_ULIMT8_BUSNUM_MASK 0x0000000f
-#define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_ULIMT8_BUSNUM_SHIFT 0
-#define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_ULIMT8_BUSNUM_DEFAULT 0x00000006
-
-/***************************************************************************
- *CPU_BUS_RANGE_LLIMT8 - CPU Address Range8 Lower Limit Mapping Register
- ***************************************************************************/
-/* HIF_CPUBIUCTRL :: CPU_BUS_RANGE_LLIMT8 :: LLIMIT [31:04] */
-#define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_LLIMT8_LLIMIT_MASK 0xfffffff0
-#define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_LLIMT8_LLIMIT_SHIFT 4
-#define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_LLIMT8_LLIMIT_DEFAULT 0x00c00000
-
-/* HIF_CPUBIUCTRL :: CPU_BUS_RANGE_LLIMT8 :: reserved0 [03:01] */
-#define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_LLIMT8_reserved0_MASK 0x0000000e
-#define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_LLIMT8_reserved0_SHIFT 1
-
-/* HIF_CPUBIUCTRL :: CPU_BUS_RANGE_LLIMT8 :: UBUSCDBIT [00:00] */
-#define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_LLIMT8_UBUSCDBIT_MASK 0x00000001
-#define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_LLIMT8_UBUSCDBIT_SHIFT 0
-#define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_LLIMT8_UBUSCDBIT_DEFAULT 0x00000000
-
-/***************************************************************************
- *CPU_BUS_RANGE_ULIMT9 - CPU Address Range9 Upper Limit Mapping Register
- ***************************************************************************/
-/* HIF_CPUBIUCTRL :: CPU_BUS_RANGE_ULIMT9 :: ULIMIT [31:04] */
-#define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_ULIMT9_ULIMIT_MASK 0xfffffff0
-#define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_ULIMT9_ULIMIT_SHIFT 4
-#define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_ULIMT9_ULIMIT_DEFAULT 0x00dfffff
-
-/* HIF_CPUBIUCTRL :: CPU_BUS_RANGE_ULIMT9 :: BUSNUM [03:00] */
-#define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_ULIMT9_BUSNUM_MASK 0x0000000f
-#define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_ULIMT9_BUSNUM_SHIFT 0
-#define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_ULIMT9_BUSNUM_DEFAULT 0x00000000
-
-/***************************************************************************
- *CPU_BUS_RANGE_LLIMT9 - CPU Address Range9 Lower Limit Mapping Register
- ***************************************************************************/
-/* HIF_CPUBIUCTRL :: CPU_BUS_RANGE_LLIMT9 :: LLIMIT [31:04] */
-#define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_LLIMT9_LLIMIT_MASK 0xfffffff0
-#define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_LLIMT9_LLIMIT_SHIFT 4
-#define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_LLIMT9_LLIMIT_DEFAULT 0x00d00000
-
-/* HIF_CPUBIUCTRL :: CPU_BUS_RANGE_LLIMT9 :: reserved0 [03:01] */
-#define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_LLIMT9_reserved0_MASK 0x0000000e
-#define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_LLIMT9_reserved0_SHIFT 1
-
-/* HIF_CPUBIUCTRL :: CPU_BUS_RANGE_LLIMT9 :: UBUSCDBIT [00:00] */
-#define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_LLIMT9_UBUSCDBIT_MASK 0x00000001
-#define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_LLIMT9_UBUSCDBIT_SHIFT 0
-#define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_LLIMT9_UBUSCDBIT_DEFAULT 0x00000000
-
-/***************************************************************************
- *CPU_BUS_RANGE_ULIMT10 - CPU Address Range10 Upper Limit Mapping Register
- ***************************************************************************/
-/* HIF_CPUBIUCTRL :: CPU_BUS_RANGE_ULIMT10 :: ULIMIT [31:04] */
-#define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_ULIMT10_ULIMIT_MASK 0xfffffff0
-#define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_ULIMT10_ULIMIT_SHIFT 4
-#define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_ULIMT10_ULIMIT_DEFAULT 0x00efffff
-
-/* HIF_CPUBIUCTRL :: CPU_BUS_RANGE_ULIMT10 :: BUSNUM [03:00] */
-#define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_ULIMT10_BUSNUM_MASK 0x0000000f
-#define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_ULIMT10_BUSNUM_SHIFT 0
-#define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_ULIMT10_BUSNUM_DEFAULT 0x00000000
-
-/***************************************************************************
- *CPU_BUS_RANGE_LLIMT10 - CPU Address Range10 Lower Limit Mapping Register
- ***************************************************************************/
-/* HIF_CPUBIUCTRL :: CPU_BUS_RANGE_LLIMT10 :: LLIMIT [31:04] */
-#define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_LLIMT10_LLIMIT_MASK 0xfffffff0
-#define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_LLIMT10_LLIMIT_SHIFT 4
-#define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_LLIMT10_LLIMIT_DEFAULT 0x00e00000
-
-/* HIF_CPUBIUCTRL :: CPU_BUS_RANGE_LLIMT10 :: reserved0 [03:01] */
-#define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_LLIMT10_reserved0_MASK 0x0000000e
-#define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_LLIMT10_reserved0_SHIFT 1
-
-/* HIF_CPUBIUCTRL :: CPU_BUS_RANGE_LLIMT10 :: UBUSCDBIT [00:00] */
-#define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_LLIMT10_UBUSCDBIT_MASK 0x00000001
-#define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_LLIMT10_UBUSCDBIT_SHIFT 0
-#define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_LLIMT10_UBUSCDBIT_DEFAULT 0x00000000
-
-/***************************************************************************
- *SECURE_RESET_HNDSHAKE_REG - CPU Secure Soft Reset Handshake Register
- ***************************************************************************/
-/* HIF_CPUBIUCTRL :: SECURE_RESET_HNDSHAKE_REG :: START [31:31] */
-#define BCHP_HIF_CPUBIUCTRL_SECURE_RESET_HNDSHAKE_REG_START_MASK 0x80000000
-#define BCHP_HIF_CPUBIUCTRL_SECURE_RESET_HNDSHAKE_REG_START_SHIFT 31
-#define BCHP_HIF_CPUBIUCTRL_SECURE_RESET_HNDSHAKE_REG_START_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: SECURE_RESET_HNDSHAKE_REG :: SW_DONE [30:30] */
-#define BCHP_HIF_CPUBIUCTRL_SECURE_RESET_HNDSHAKE_REG_SW_DONE_MASK 0x40000000
-#define BCHP_HIF_CPUBIUCTRL_SECURE_RESET_HNDSHAKE_REG_SW_DONE_SHIFT 30
-#define BCHP_HIF_CPUBIUCTRL_SECURE_RESET_HNDSHAKE_REG_SW_DONE_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: SECURE_RESET_HNDSHAKE_REG :: HW_DONE [29:29] */
-#define BCHP_HIF_CPUBIUCTRL_SECURE_RESET_HNDSHAKE_REG_HW_DONE_MASK 0x20000000
-#define BCHP_HIF_CPUBIUCTRL_SECURE_RESET_HNDSHAKE_REG_HW_DONE_SHIFT 29
-
-/* HIF_CPUBIUCTRL :: SECURE_RESET_HNDSHAKE_REG :: reserved0 [28:00] */
-#define BCHP_HIF_CPUBIUCTRL_SECURE_RESET_HNDSHAKE_REG_reserved0_MASK 0x1fffffff
-#define BCHP_HIF_CPUBIUCTRL_SECURE_RESET_HNDSHAKE_REG_reserved0_SHIFT 0
-
-/***************************************************************************
- *SECURE_SOFT_RESET_REG - CPU Secure Soft Reset Register
- ***************************************************************************/
-/* HIF_CPUBIUCTRL :: SECURE_SOFT_RESET_REG :: WEBCORES_SOFT_RESET [31:31] */
-#define BCHP_HIF_CPUBIUCTRL_SECURE_SOFT_RESET_REG_WEBCORES_SOFT_RESET_MASK 0x80000000
-#define BCHP_HIF_CPUBIUCTRL_SECURE_SOFT_RESET_REG_WEBCORES_SOFT_RESET_SHIFT 31
-#define BCHP_HIF_CPUBIUCTRL_SECURE_SOFT_RESET_REG_WEBCORES_SOFT_RESET_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: SECURE_SOFT_RESET_REG :: reserved0 [30:00] */
-#define BCHP_HIF_CPUBIUCTRL_SECURE_SOFT_RESET_REG_reserved0_MASK 0x7fffffff
-#define BCHP_HIF_CPUBIUCTRL_SECURE_SOFT_RESET_REG_reserved0_SHIFT 0
-
-/***************************************************************************
- *CPU_ACCESS_RIGHT_VIOL_ADDR0 - CPU Access Rights Violation Address0 Register
- ***************************************************************************/
-/* HIF_CPUBIUCTRL :: CPU_ACCESS_RIGHT_VIOL_ADDR0 :: VIOL_ADDR [31:00] */
-#define BCHP_HIF_CPUBIUCTRL_CPU_ACCESS_RIGHT_VIOL_ADDR0_VIOL_ADDR_MASK 0xffffffff
-#define BCHP_HIF_CPUBIUCTRL_CPU_ACCESS_RIGHT_VIOL_ADDR0_VIOL_ADDR_SHIFT 0
-#define BCHP_HIF_CPUBIUCTRL_CPU_ACCESS_RIGHT_VIOL_ADDR0_VIOL_ADDR_DEFAULT 0x00000000
-
-/***************************************************************************
- *CPU_ACCESS_RIGHT_VIOL_UPPER_ADDR0 - CPU Access Rights Violation Upper Address0 Register
- ***************************************************************************/
-/* HIF_CPUBIUCTRL :: CPU_ACCESS_RIGHT_VIOL_UPPER_ADDR0 :: reserved0 [31:08] */
-#define BCHP_HIF_CPUBIUCTRL_CPU_ACCESS_RIGHT_VIOL_UPPER_ADDR0_reserved0_MASK 0xffffff00
-#define BCHP_HIF_CPUBIUCTRL_CPU_ACCESS_RIGHT_VIOL_UPPER_ADDR0_reserved0_SHIFT 8
-
-/* HIF_CPUBIUCTRL :: CPU_ACCESS_RIGHT_VIOL_UPPER_ADDR0 :: VIOL_UPPER_ADDR [07:00] */
-#define BCHP_HIF_CPUBIUCTRL_CPU_ACCESS_RIGHT_VIOL_UPPER_ADDR0_VIOL_UPPER_ADDR_MASK 0x000000ff
-#define BCHP_HIF_CPUBIUCTRL_CPU_ACCESS_RIGHT_VIOL_UPPER_ADDR0_VIOL_UPPER_ADDR_SHIFT 0
-#define BCHP_HIF_CPUBIUCTRL_CPU_ACCESS_RIGHT_VIOL_UPPER_ADDR0_VIOL_UPPER_ADDR_DEFAULT 0x00000000
-
-/***************************************************************************
- *CPU_ACCESS_RIGHT_VIOL_DETAIL_ADDR0 - CPU Access Rights Violation Transaction Detail0 Register
- ***************************************************************************/
-/* HIF_CPUBIUCTRL :: CPU_ACCESS_RIGHT_VIOL_DETAIL_ADDR0 :: ERROR_VLD [31:31] */
-#define BCHP_HIF_CPUBIUCTRL_CPU_ACCESS_RIGHT_VIOL_DETAIL_ADDR0_ERROR_VLD_MASK 0x80000000
-#define BCHP_HIF_CPUBIUCTRL_CPU_ACCESS_RIGHT_VIOL_DETAIL_ADDR0_ERROR_VLD_SHIFT 31
-
-/* HIF_CPUBIUCTRL :: CPU_ACCESS_RIGHT_VIOL_DETAIL_ADDR0 :: reserved0 [30:30] */
-#define BCHP_HIF_CPUBIUCTRL_CPU_ACCESS_RIGHT_VIOL_DETAIL_ADDR0_reserved0_MASK 0x40000000
-#define BCHP_HIF_CPUBIUCTRL_CPU_ACCESS_RIGHT_VIOL_DETAIL_ADDR0_reserved0_SHIFT 30
-
-/* HIF_CPUBIUCTRL :: CPU_ACCESS_RIGHT_VIOL_DETAIL_ADDR0 :: CLUSTER_ID [29:26] */
-#define BCHP_HIF_CPUBIUCTRL_CPU_ACCESS_RIGHT_VIOL_DETAIL_ADDR0_CLUSTER_ID_MASK 0x3c000000
-#define BCHP_HIF_CPUBIUCTRL_CPU_ACCESS_RIGHT_VIOL_DETAIL_ADDR0_CLUSTER_ID_SHIFT 26
-
-/* HIF_CPUBIUCTRL :: CPU_ACCESS_RIGHT_VIOL_DETAIL_ADDR0 :: PROCESSOR_ID [25:24] */
-#define BCHP_HIF_CPUBIUCTRL_CPU_ACCESS_RIGHT_VIOL_DETAIL_ADDR0_PROCESSOR_ID_MASK 0x03000000
-#define BCHP_HIF_CPUBIUCTRL_CPU_ACCESS_RIGHT_VIOL_DETAIL_ADDR0_PROCESSOR_ID_SHIFT 24
-
-/* HIF_CPUBIUCTRL :: CPU_ACCESS_RIGHT_VIOL_DETAIL_ADDR0 :: reserved1 [23:23] */
-#define BCHP_HIF_CPUBIUCTRL_CPU_ACCESS_RIGHT_VIOL_DETAIL_ADDR0_reserved1_MASK 0x00800000
-#define BCHP_HIF_CPUBIUCTRL_CPU_ACCESS_RIGHT_VIOL_DETAIL_ADDR0_reserved1_SHIFT 23
-
-/* HIF_CPUBIUCTRL :: CPU_ACCESS_RIGHT_VIOL_DETAIL_ADDR0 :: INSTRUCTION_ACCESS [22:22] */
-#define BCHP_HIF_CPUBIUCTRL_CPU_ACCESS_RIGHT_VIOL_DETAIL_ADDR0_INSTRUCTION_ACCESS_MASK 0x00400000
-#define BCHP_HIF_CPUBIUCTRL_CPU_ACCESS_RIGHT_VIOL_DETAIL_ADDR0_INSTRUCTION_ACCESS_SHIFT 22
-
-/* HIF_CPUBIUCTRL :: CPU_ACCESS_RIGHT_VIOL_DETAIL_ADDR0 :: reserved2 [21:16] */
-#define BCHP_HIF_CPUBIUCTRL_CPU_ACCESS_RIGHT_VIOL_DETAIL_ADDR0_reserved2_MASK 0x003f0000
-#define BCHP_HIF_CPUBIUCTRL_CPU_ACCESS_RIGHT_VIOL_DETAIL_ADDR0_reserved2_SHIFT 16
-
-/* HIF_CPUBIUCTRL :: CPU_ACCESS_RIGHT_VIOL_DETAIL_ADDR0 :: REQUEST_SIZE [15:12] */
-#define BCHP_HIF_CPUBIUCTRL_CPU_ACCESS_RIGHT_VIOL_DETAIL_ADDR0_REQUEST_SIZE_MASK 0x0000f000
-#define BCHP_HIF_CPUBIUCTRL_CPU_ACCESS_RIGHT_VIOL_DETAIL_ADDR0_REQUEST_SIZE_SHIFT 12
-
-/* HIF_CPUBIUCTRL :: CPU_ACCESS_RIGHT_VIOL_DETAIL_ADDR0 :: UPPER_VIOL_ADDR [11:04] */
-#define BCHP_HIF_CPUBIUCTRL_CPU_ACCESS_RIGHT_VIOL_DETAIL_ADDR0_UPPER_VIOL_ADDR_MASK 0x00000ff0
-#define BCHP_HIF_CPUBIUCTRL_CPU_ACCESS_RIGHT_VIOL_DETAIL_ADDR0_UPPER_VIOL_ADDR_SHIFT 4
-#define BCHP_HIF_CPUBIUCTRL_CPU_ACCESS_RIGHT_VIOL_DETAIL_ADDR0_UPPER_VIOL_ADDR_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: CPU_ACCESS_RIGHT_VIOL_DETAIL_ADDR0 :: REQUEST_TYPE [03:00] */
-#define BCHP_HIF_CPUBIUCTRL_CPU_ACCESS_RIGHT_VIOL_DETAIL_ADDR0_REQUEST_TYPE_MASK 0x0000000f
-#define BCHP_HIF_CPUBIUCTRL_CPU_ACCESS_RIGHT_VIOL_DETAIL_ADDR0_REQUEST_TYPE_SHIFT 0
-
-/***************************************************************************
- *CPU_ACCESS_RIGHT_VIOL_ADDR1 - CPU Access Rights Violation Address1 Register
- ***************************************************************************/
-/* HIF_CPUBIUCTRL :: CPU_ACCESS_RIGHT_VIOL_ADDR1 :: VIOL_ADDR [31:00] */
-#define BCHP_HIF_CPUBIUCTRL_CPU_ACCESS_RIGHT_VIOL_ADDR1_VIOL_ADDR_MASK 0xffffffff
-#define BCHP_HIF_CPUBIUCTRL_CPU_ACCESS_RIGHT_VIOL_ADDR1_VIOL_ADDR_SHIFT 0
-#define BCHP_HIF_CPUBIUCTRL_CPU_ACCESS_RIGHT_VIOL_ADDR1_VIOL_ADDR_DEFAULT 0x00000000
-
-/***************************************************************************
- *CPU_ACCESS_RIGHT_VIOL_UPPER_ADDR1 - CPU Access Rights Violation Upper Address1 Register
- ***************************************************************************/
-/* HIF_CPUBIUCTRL :: CPU_ACCESS_RIGHT_VIOL_UPPER_ADDR1 :: reserved0 [31:08] */
-#define BCHP_HIF_CPUBIUCTRL_CPU_ACCESS_RIGHT_VIOL_UPPER_ADDR1_reserved0_MASK 0xffffff00
-#define BCHP_HIF_CPUBIUCTRL_CPU_ACCESS_RIGHT_VIOL_UPPER_ADDR1_reserved0_SHIFT 8
-
-/* HIF_CPUBIUCTRL :: CPU_ACCESS_RIGHT_VIOL_UPPER_ADDR1 :: VIOL_UPPER_ADDR [07:00] */
-#define BCHP_HIF_CPUBIUCTRL_CPU_ACCESS_RIGHT_VIOL_UPPER_ADDR1_VIOL_UPPER_ADDR_MASK 0x000000ff
-#define BCHP_HIF_CPUBIUCTRL_CPU_ACCESS_RIGHT_VIOL_UPPER_ADDR1_VIOL_UPPER_ADDR_SHIFT 0
-#define BCHP_HIF_CPUBIUCTRL_CPU_ACCESS_RIGHT_VIOL_UPPER_ADDR1_VIOL_UPPER_ADDR_DEFAULT 0x00000000
-
-/***************************************************************************
- *CPU_ACCESS_RIGHT_VIOL_DETAIL_ADDR1 - CPU Access Rights Violation Transaction Detail1 Register
- ***************************************************************************/
-/* HIF_CPUBIUCTRL :: CPU_ACCESS_RIGHT_VIOL_DETAIL_ADDR1 :: ERROR_VLD [31:31] */
-#define BCHP_HIF_CPUBIUCTRL_CPU_ACCESS_RIGHT_VIOL_DETAIL_ADDR1_ERROR_VLD_MASK 0x80000000
-#define BCHP_HIF_CPUBIUCTRL_CPU_ACCESS_RIGHT_VIOL_DETAIL_ADDR1_ERROR_VLD_SHIFT 31
-
-/* HIF_CPUBIUCTRL :: CPU_ACCESS_RIGHT_VIOL_DETAIL_ADDR1 :: reserved0 [30:30] */
-#define BCHP_HIF_CPUBIUCTRL_CPU_ACCESS_RIGHT_VIOL_DETAIL_ADDR1_reserved0_MASK 0x40000000
-#define BCHP_HIF_CPUBIUCTRL_CPU_ACCESS_RIGHT_VIOL_DETAIL_ADDR1_reserved0_SHIFT 30
-
-/* HIF_CPUBIUCTRL :: CPU_ACCESS_RIGHT_VIOL_DETAIL_ADDR1 :: CLUSTER_ID [29:26] */
-#define BCHP_HIF_CPUBIUCTRL_CPU_ACCESS_RIGHT_VIOL_DETAIL_ADDR1_CLUSTER_ID_MASK 0x3c000000
-#define BCHP_HIF_CPUBIUCTRL_CPU_ACCESS_RIGHT_VIOL_DETAIL_ADDR1_CLUSTER_ID_SHIFT 26
-
-/* HIF_CPUBIUCTRL :: CPU_ACCESS_RIGHT_VIOL_DETAIL_ADDR1 :: PROCESSOR_ID [25:24] */
-#define BCHP_HIF_CPUBIUCTRL_CPU_ACCESS_RIGHT_VIOL_DETAIL_ADDR1_PROCESSOR_ID_MASK 0x03000000
-#define BCHP_HIF_CPUBIUCTRL_CPU_ACCESS_RIGHT_VIOL_DETAIL_ADDR1_PROCESSOR_ID_SHIFT 24
-
-/* HIF_CPUBIUCTRL :: CPU_ACCESS_RIGHT_VIOL_DETAIL_ADDR1 :: reserved1 [23:23] */
-#define BCHP_HIF_CPUBIUCTRL_CPU_ACCESS_RIGHT_VIOL_DETAIL_ADDR1_reserved1_MASK 0x00800000
-#define BCHP_HIF_CPUBIUCTRL_CPU_ACCESS_RIGHT_VIOL_DETAIL_ADDR1_reserved1_SHIFT 23
-
-/* HIF_CPUBIUCTRL :: CPU_ACCESS_RIGHT_VIOL_DETAIL_ADDR1 :: INSTRUCTION_ACCESS [22:22] */
-#define BCHP_HIF_CPUBIUCTRL_CPU_ACCESS_RIGHT_VIOL_DETAIL_ADDR1_INSTRUCTION_ACCESS_MASK 0x00400000
-#define BCHP_HIF_CPUBIUCTRL_CPU_ACCESS_RIGHT_VIOL_DETAIL_ADDR1_INSTRUCTION_ACCESS_SHIFT 22
-
-/* HIF_CPUBIUCTRL :: CPU_ACCESS_RIGHT_VIOL_DETAIL_ADDR1 :: reserved2 [21:16] */
-#define BCHP_HIF_CPUBIUCTRL_CPU_ACCESS_RIGHT_VIOL_DETAIL_ADDR1_reserved2_MASK 0x003f0000
-#define BCHP_HIF_CPUBIUCTRL_CPU_ACCESS_RIGHT_VIOL_DETAIL_ADDR1_reserved2_SHIFT 16
-
-/* HIF_CPUBIUCTRL :: CPU_ACCESS_RIGHT_VIOL_DETAIL_ADDR1 :: REQUEST_SIZE [15:12] */
-#define BCHP_HIF_CPUBIUCTRL_CPU_ACCESS_RIGHT_VIOL_DETAIL_ADDR1_REQUEST_SIZE_MASK 0x0000f000
-#define BCHP_HIF_CPUBIUCTRL_CPU_ACCESS_RIGHT_VIOL_DETAIL_ADDR1_REQUEST_SIZE_SHIFT 12
-
-/* HIF_CPUBIUCTRL :: CPU_ACCESS_RIGHT_VIOL_DETAIL_ADDR1 :: UPPER_VIOL_ADDR [11:04] */
-#define BCHP_HIF_CPUBIUCTRL_CPU_ACCESS_RIGHT_VIOL_DETAIL_ADDR1_UPPER_VIOL_ADDR_MASK 0x00000ff0
-#define BCHP_HIF_CPUBIUCTRL_CPU_ACCESS_RIGHT_VIOL_DETAIL_ADDR1_UPPER_VIOL_ADDR_SHIFT 4
-#define BCHP_HIF_CPUBIUCTRL_CPU_ACCESS_RIGHT_VIOL_DETAIL_ADDR1_UPPER_VIOL_ADDR_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: CPU_ACCESS_RIGHT_VIOL_DETAIL_ADDR1 :: REQUEST_TYPE [03:00] */
-#define BCHP_HIF_CPUBIUCTRL_CPU_ACCESS_RIGHT_VIOL_DETAIL_ADDR1_REQUEST_TYPE_MASK 0x0000000f
-#define BCHP_HIF_CPUBIUCTRL_CPU_ACCESS_RIGHT_VIOL_DETAIL_ADDR1_REQUEST_TYPE_SHIFT 0
-
-/***************************************************************************
- *RAC_CONFIG0_REG - Read Ahead Cache Configuration0 Register
- ***************************************************************************/
-/* HIF_CPUBIUCTRL :: RAC_CONFIG0_REG :: RACENDATA3 [31:30] */
-#define BCHP_HIF_CPUBIUCTRL_RAC_CONFIG0_REG_RACENDATA3_MASK 0xc0000000
-#define BCHP_HIF_CPUBIUCTRL_RAC_CONFIG0_REG_RACENDATA3_SHIFT 30
-#define BCHP_HIF_CPUBIUCTRL_RAC_CONFIG0_REG_RACENDATA3_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: RAC_CONFIG0_REG :: RACPREFDATA3 [29:28] */
-#define BCHP_HIF_CPUBIUCTRL_RAC_CONFIG0_REG_RACPREFDATA3_MASK 0x30000000
-#define BCHP_HIF_CPUBIUCTRL_RAC_CONFIG0_REG_RACPREFDATA3_SHIFT 28
-#define BCHP_HIF_CPUBIUCTRL_RAC_CONFIG0_REG_RACPREFDATA3_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: RAC_CONFIG0_REG :: RACENINST3 [27:26] */
-#define BCHP_HIF_CPUBIUCTRL_RAC_CONFIG0_REG_RACENINST3_MASK 0x0c000000
-#define BCHP_HIF_CPUBIUCTRL_RAC_CONFIG0_REG_RACENINST3_SHIFT 26
-#define BCHP_HIF_CPUBIUCTRL_RAC_CONFIG0_REG_RACENINST3_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: RAC_CONFIG0_REG :: RACPREFINST3 [25:24] */
-#define BCHP_HIF_CPUBIUCTRL_RAC_CONFIG0_REG_RACPREFINST3_MASK 0x03000000
-#define BCHP_HIF_CPUBIUCTRL_RAC_CONFIG0_REG_RACPREFINST3_SHIFT 24
-#define BCHP_HIF_CPUBIUCTRL_RAC_CONFIG0_REG_RACPREFINST3_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: RAC_CONFIG0_REG :: RACENDATA2 [23:22] */
-#define BCHP_HIF_CPUBIUCTRL_RAC_CONFIG0_REG_RACENDATA2_MASK 0x00c00000
-#define BCHP_HIF_CPUBIUCTRL_RAC_CONFIG0_REG_RACENDATA2_SHIFT 22
-#define BCHP_HIF_CPUBIUCTRL_RAC_CONFIG0_REG_RACENDATA2_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: RAC_CONFIG0_REG :: RACPREFDATA2 [21:20] */
-#define BCHP_HIF_CPUBIUCTRL_RAC_CONFIG0_REG_RACPREFDATA2_MASK 0x00300000
-#define BCHP_HIF_CPUBIUCTRL_RAC_CONFIG0_REG_RACPREFDATA2_SHIFT 20
-#define BCHP_HIF_CPUBIUCTRL_RAC_CONFIG0_REG_RACPREFDATA2_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: RAC_CONFIG0_REG :: RACENINST2 [19:18] */
-#define BCHP_HIF_CPUBIUCTRL_RAC_CONFIG0_REG_RACENINST2_MASK 0x000c0000
-#define BCHP_HIF_CPUBIUCTRL_RAC_CONFIG0_REG_RACENINST2_SHIFT 18
-#define BCHP_HIF_CPUBIUCTRL_RAC_CONFIG0_REG_RACENINST2_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: RAC_CONFIG0_REG :: RACPREFINST2 [17:16] */
-#define BCHP_HIF_CPUBIUCTRL_RAC_CONFIG0_REG_RACPREFINST2_MASK 0x00030000
-#define BCHP_HIF_CPUBIUCTRL_RAC_CONFIG0_REG_RACPREFINST2_SHIFT 16
-#define BCHP_HIF_CPUBIUCTRL_RAC_CONFIG0_REG_RACPREFINST2_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: RAC_CONFIG0_REG :: RACENDATA1 [15:14] */
-#define BCHP_HIF_CPUBIUCTRL_RAC_CONFIG0_REG_RACENDATA1_MASK 0x0000c000
-#define BCHP_HIF_CPUBIUCTRL_RAC_CONFIG0_REG_RACENDATA1_SHIFT 14
-#define BCHP_HIF_CPUBIUCTRL_RAC_CONFIG0_REG_RACENDATA1_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: RAC_CONFIG0_REG :: RACPREFDATA1 [13:12] */
-#define BCHP_HIF_CPUBIUCTRL_RAC_CONFIG0_REG_RACPREFDATA1_MASK 0x00003000
-#define BCHP_HIF_CPUBIUCTRL_RAC_CONFIG0_REG_RACPREFDATA1_SHIFT 12
-#define BCHP_HIF_CPUBIUCTRL_RAC_CONFIG0_REG_RACPREFDATA1_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: RAC_CONFIG0_REG :: RACENINST1 [11:10] */
-#define BCHP_HIF_CPUBIUCTRL_RAC_CONFIG0_REG_RACENINST1_MASK 0x00000c00
-#define BCHP_HIF_CPUBIUCTRL_RAC_CONFIG0_REG_RACENINST1_SHIFT 10
-#define BCHP_HIF_CPUBIUCTRL_RAC_CONFIG0_REG_RACENINST1_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: RAC_CONFIG0_REG :: RACPREFINST1 [09:08] */
-#define BCHP_HIF_CPUBIUCTRL_RAC_CONFIG0_REG_RACPREFINST1_MASK 0x00000300
-#define BCHP_HIF_CPUBIUCTRL_RAC_CONFIG0_REG_RACPREFINST1_SHIFT 8
-#define BCHP_HIF_CPUBIUCTRL_RAC_CONFIG0_REG_RACPREFINST1_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: RAC_CONFIG0_REG :: RACENDATA0 [07:06] */
-#define BCHP_HIF_CPUBIUCTRL_RAC_CONFIG0_REG_RACENDATA0_MASK 0x000000c0
-#define BCHP_HIF_CPUBIUCTRL_RAC_CONFIG0_REG_RACENDATA0_SHIFT 6
-#define BCHP_HIF_CPUBIUCTRL_RAC_CONFIG0_REG_RACENDATA0_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: RAC_CONFIG0_REG :: RACPREFDATA0 [05:04] */
-#define BCHP_HIF_CPUBIUCTRL_RAC_CONFIG0_REG_RACPREFDATA0_MASK 0x00000030
-#define BCHP_HIF_CPUBIUCTRL_RAC_CONFIG0_REG_RACPREFDATA0_SHIFT 4
-#define BCHP_HIF_CPUBIUCTRL_RAC_CONFIG0_REG_RACPREFDATA0_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: RAC_CONFIG0_REG :: RACENINST0 [03:02] */
-#define BCHP_HIF_CPUBIUCTRL_RAC_CONFIG0_REG_RACENINST0_MASK 0x0000000c
-#define BCHP_HIF_CPUBIUCTRL_RAC_CONFIG0_REG_RACENINST0_SHIFT 2
-#define BCHP_HIF_CPUBIUCTRL_RAC_CONFIG0_REG_RACENINST0_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: RAC_CONFIG0_REG :: RACPREFINST0 [01:00] */
-#define BCHP_HIF_CPUBIUCTRL_RAC_CONFIG0_REG_RACPREFINST0_MASK 0x00000003
-#define BCHP_HIF_CPUBIUCTRL_RAC_CONFIG0_REG_RACPREFINST0_SHIFT 0
-#define BCHP_HIF_CPUBIUCTRL_RAC_CONFIG0_REG_RACPREFINST0_DEFAULT 0x00000000
-
-/***************************************************************************
- *RAC_CONFIG1_REG - Read Ahead Cache Configuration1 Register
- ***************************************************************************/
-/* HIF_CPUBIUCTRL :: RAC_CONFIG1_REG :: reserved0 [31:10] */
-#define BCHP_HIF_CPUBIUCTRL_RAC_CONFIG1_REG_reserved0_MASK 0xfffffc00
-#define BCHP_HIF_CPUBIUCTRL_RAC_CONFIG1_REG_reserved0_SHIFT 10
-
-/* HIF_CPUBIUCTRL :: RAC_CONFIG1_REG :: RAC_TAG_PARITY_EN [09:09] */
-#define BCHP_HIF_CPUBIUCTRL_RAC_CONFIG1_REG_RAC_TAG_PARITY_EN_MASK 0x00000200
-#define BCHP_HIF_CPUBIUCTRL_RAC_CONFIG1_REG_RAC_TAG_PARITY_EN_SHIFT 9
-#define BCHP_HIF_CPUBIUCTRL_RAC_CONFIG1_REG_RAC_TAG_PARITY_EN_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: RAC_CONFIG1_REG :: RAC_PARITY_EN [08:08] */
-#define BCHP_HIF_CPUBIUCTRL_RAC_CONFIG1_REG_RAC_PARITY_EN_MASK 0x00000100
-#define BCHP_HIF_CPUBIUCTRL_RAC_CONFIG1_REG_RAC_PARITY_EN_SHIFT 8
-#define BCHP_HIF_CPUBIUCTRL_RAC_CONFIG1_REG_RAC_PARITY_EN_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: RAC_CONFIG1_REG :: RAC_TBD_CTRL7to6 [07:06] */
-#define BCHP_HIF_CPUBIUCTRL_RAC_CONFIG1_REG_RAC_TBD_CTRL7to6_MASK 0x000000c0
-#define BCHP_HIF_CPUBIUCTRL_RAC_CONFIG1_REG_RAC_TBD_CTRL7to6_SHIFT 6
-#define BCHP_HIF_CPUBIUCTRL_RAC_CONFIG1_REG_RAC_TBD_CTRL7to6_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: RAC_CONFIG1_REG :: RAC_FIFO_CTRL [05:04] */
-#define BCHP_HIF_CPUBIUCTRL_RAC_CONFIG1_REG_RAC_FIFO_CTRL_MASK 0x00000030
-#define BCHP_HIF_CPUBIUCTRL_RAC_CONFIG1_REG_RAC_FIFO_CTRL_SHIFT 4
-#define BCHP_HIF_CPUBIUCTRL_RAC_CONFIG1_REG_RAC_FIFO_CTRL_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: RAC_CONFIG1_REG :: RAC_TBD_CTRL3to1 [03:01] */
-#define BCHP_HIF_CPUBIUCTRL_RAC_CONFIG1_REG_RAC_TBD_CTRL3to1_MASK 0x0000000e
-#define BCHP_HIF_CPUBIUCTRL_RAC_CONFIG1_REG_RAC_TBD_CTRL3to1_SHIFT 1
-#define BCHP_HIF_CPUBIUCTRL_RAC_CONFIG1_REG_RAC_TBD_CTRL3to1_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: RAC_CONFIG1_REG :: UBUS_RAC_EN [00:00] */
-#define BCHP_HIF_CPUBIUCTRL_RAC_CONFIG1_REG_UBUS_RAC_EN_MASK 0x00000001
-#define BCHP_HIF_CPUBIUCTRL_RAC_CONFIG1_REG_UBUS_RAC_EN_SHIFT 0
-#define BCHP_HIF_CPUBIUCTRL_RAC_CONFIG1_REG_UBUS_RAC_EN_DEFAULT 0x00000000
-
-/***************************************************************************
- *RAC_FLUSH_REG - Read Ahead Cache Flush Register
- ***************************************************************************/
-/* HIF_CPUBIUCTRL :: RAC_FLUSH_REG :: reserved0 [31:01] */
-#define BCHP_HIF_CPUBIUCTRL_RAC_FLUSH_REG_reserved0_MASK 0xfffffffe
-#define BCHP_HIF_CPUBIUCTRL_RAC_FLUSH_REG_reserved0_SHIFT 1
-
-/* HIF_CPUBIUCTRL :: RAC_FLUSH_REG :: FLUSH_RAC [00:00] */
-#define BCHP_HIF_CPUBIUCTRL_RAC_FLUSH_REG_FLUSH_RAC_MASK 0x00000001
-#define BCHP_HIF_CPUBIUCTRL_RAC_FLUSH_REG_FLUSH_RAC_SHIFT 0
-#define BCHP_HIF_CPUBIUCTRL_RAC_FLUSH_REG_FLUSH_RAC_DEFAULT 0x00000000
-
-/***************************************************************************
- *CPU_POWER_CONFIG_REG - CPU Power Configuration Register
- ***************************************************************************/
-/* HIF_CPUBIUCTRL :: CPU_POWER_CONFIG_REG :: reserved0 [31:08] */
-#define BCHP_HIF_CPUBIUCTRL_CPU_POWER_CONFIG_REG_reserved0_MASK 0xffffff00
-#define BCHP_HIF_CPUBIUCTRL_CPU_POWER_CONFIG_REG_reserved0_SHIFT 8
-
-/* HIF_CPUBIUCTRL :: CPU_POWER_CONFIG_REG :: CPU3_BPCM_INIT_ON [07:07] */
-#define BCHP_HIF_CPUBIUCTRL_CPU_POWER_CONFIG_REG_CPU3_BPCM_INIT_ON_MASK 0x00000080
-#define BCHP_HIF_CPUBIUCTRL_CPU_POWER_CONFIG_REG_CPU3_BPCM_INIT_ON_SHIFT 7
-#define BCHP_HIF_CPUBIUCTRL_CPU_POWER_CONFIG_REG_CPU3_BPCM_INIT_ON_DEFAULT 0x00000001
-
-/* HIF_CPUBIUCTRL :: CPU_POWER_CONFIG_REG :: CPU2_BPCM_INIT_ON [06:06] */
-#define BCHP_HIF_CPUBIUCTRL_CPU_POWER_CONFIG_REG_CPU2_BPCM_INIT_ON_MASK 0x00000040
-#define BCHP_HIF_CPUBIUCTRL_CPU_POWER_CONFIG_REG_CPU2_BPCM_INIT_ON_SHIFT 6
-#define BCHP_HIF_CPUBIUCTRL_CPU_POWER_CONFIG_REG_CPU2_BPCM_INIT_ON_DEFAULT 0x00000001
-
-/* HIF_CPUBIUCTRL :: CPU_POWER_CONFIG_REG :: CPU1_BPCM_INIT_ON [05:05] */
-#define BCHP_HIF_CPUBIUCTRL_CPU_POWER_CONFIG_REG_CPU1_BPCM_INIT_ON_MASK 0x00000020
-#define BCHP_HIF_CPUBIUCTRL_CPU_POWER_CONFIG_REG_CPU1_BPCM_INIT_ON_SHIFT 5
-#define BCHP_HIF_CPUBIUCTRL_CPU_POWER_CONFIG_REG_CPU1_BPCM_INIT_ON_DEFAULT 0x00000001
-
-/* HIF_CPUBIUCTRL :: CPU_POWER_CONFIG_REG :: CPU0_BPCM_INIT_ON [04:04] */
-#define BCHP_HIF_CPUBIUCTRL_CPU_POWER_CONFIG_REG_CPU0_BPCM_INIT_ON_MASK 0x00000010
-#define BCHP_HIF_CPUBIUCTRL_CPU_POWER_CONFIG_REG_CPU0_BPCM_INIT_ON_SHIFT 4
-#define BCHP_HIF_CPUBIUCTRL_CPU_POWER_CONFIG_REG_CPU0_BPCM_INIT_ON_DEFAULT 0x00000001
-
-/* HIF_CPUBIUCTRL :: CPU_POWER_CONFIG_REG :: CPU3_BPCM_DIS [03:03] */
-#define BCHP_HIF_CPUBIUCTRL_CPU_POWER_CONFIG_REG_CPU3_BPCM_DIS_MASK 0x00000008
-#define BCHP_HIF_CPUBIUCTRL_CPU_POWER_CONFIG_REG_CPU3_BPCM_DIS_SHIFT 3
-#define BCHP_HIF_CPUBIUCTRL_CPU_POWER_CONFIG_REG_CPU3_BPCM_DIS_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: CPU_POWER_CONFIG_REG :: CPU2_BPCM_DIS [02:02] */
-#define BCHP_HIF_CPUBIUCTRL_CPU_POWER_CONFIG_REG_CPU2_BPCM_DIS_MASK 0x00000004
-#define BCHP_HIF_CPUBIUCTRL_CPU_POWER_CONFIG_REG_CPU2_BPCM_DIS_SHIFT 2
-#define BCHP_HIF_CPUBIUCTRL_CPU_POWER_CONFIG_REG_CPU2_BPCM_DIS_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: CPU_POWER_CONFIG_REG :: CPU1_BPCM_DIS [01:01] */
-#define BCHP_HIF_CPUBIUCTRL_CPU_POWER_CONFIG_REG_CPU1_BPCM_DIS_MASK 0x00000002
-#define BCHP_HIF_CPUBIUCTRL_CPU_POWER_CONFIG_REG_CPU1_BPCM_DIS_SHIFT 1
-#define BCHP_HIF_CPUBIUCTRL_CPU_POWER_CONFIG_REG_CPU1_BPCM_DIS_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: CPU_POWER_CONFIG_REG :: CPU0_BPCM_DIS [00:00] */
-#define BCHP_HIF_CPUBIUCTRL_CPU_POWER_CONFIG_REG_CPU0_BPCM_DIS_MASK 0x00000001
-#define BCHP_HIF_CPUBIUCTRL_CPU_POWER_CONFIG_REG_CPU0_BPCM_DIS_SHIFT 0
-#define BCHP_HIF_CPUBIUCTRL_CPU_POWER_CONFIG_REG_CPU0_BPCM_DIS_DEFAULT 0x00000000
-
-/***************************************************************************
- *CPU0_PWR_ZONE_CNTRL_REG - CPU0 Power Zone Control Register
- ***************************************************************************/
-/* HIF_CPUBIUCTRL :: CPU0_PWR_ZONE_CNTRL_REG :: ZONE_RESET_STATE [31:31] */
-#define BCHP_HIF_CPUBIUCTRL_CPU0_PWR_ZONE_CNTRL_REG_ZONE_RESET_STATE_MASK 0x80000000
-#define BCHP_HIF_CPUBIUCTRL_CPU0_PWR_ZONE_CNTRL_REG_ZONE_RESET_STATE_SHIFT 31
-
-/* HIF_CPUBIUCTRL :: CPU0_PWR_ZONE_CNTRL_REG :: ZONE_ISO_STATE [30:30] */
-#define BCHP_HIF_CPUBIUCTRL_CPU0_PWR_ZONE_CNTRL_REG_ZONE_ISO_STATE_MASK 0x40000000
-#define BCHP_HIF_CPUBIUCTRL_CPU0_PWR_ZONE_CNTRL_REG_ZONE_ISO_STATE_SHIFT 30
-
-/* HIF_CPUBIUCTRL :: CPU0_PWR_ZONE_CNTRL_REG :: ZONE_MEM_PWR_STATE [29:29] */
-#define BCHP_HIF_CPUBIUCTRL_CPU0_PWR_ZONE_CNTRL_REG_ZONE_MEM_PWR_STATE_MASK 0x20000000
-#define BCHP_HIF_CPUBIUCTRL_CPU0_PWR_ZONE_CNTRL_REG_ZONE_MEM_PWR_STATE_SHIFT 29
-
-/* HIF_CPUBIUCTRL :: CPU0_PWR_ZONE_CNTRL_REG :: ZONE_DPG_PWR_STATE [28:28] */
-#define BCHP_HIF_CPUBIUCTRL_CPU0_PWR_ZONE_CNTRL_REG_ZONE_DPG_PWR_STATE_MASK 0x10000000
-#define BCHP_HIF_CPUBIUCTRL_CPU0_PWR_ZONE_CNTRL_REG_ZONE_DPG_PWR_STATE_SHIFT 28
-
-/* HIF_CPUBIUCTRL :: CPU0_PWR_ZONE_CNTRL_REG :: ZONE_POWER_GOOD [27:27] */
-#define BCHP_HIF_CPUBIUCTRL_CPU0_PWR_ZONE_CNTRL_REG_ZONE_POWER_GOOD_MASK 0x08000000
-#define BCHP_HIF_CPUBIUCTRL_CPU0_PWR_ZONE_CNTRL_REG_ZONE_POWER_GOOD_SHIFT 27
-
-/* HIF_CPUBIUCTRL :: CPU0_PWR_ZONE_CNTRL_REG :: ZONE_PWR_ON_STATE [26:26] */
-#define BCHP_HIF_CPUBIUCTRL_CPU0_PWR_ZONE_CNTRL_REG_ZONE_PWR_ON_STATE_MASK 0x04000000
-#define BCHP_HIF_CPUBIUCTRL_CPU0_PWR_ZONE_CNTRL_REG_ZONE_PWR_ON_STATE_SHIFT 26
-
-/* HIF_CPUBIUCTRL :: CPU0_PWR_ZONE_CNTRL_REG :: ZONE_PWR_OFF_STATE [25:25] */
-#define BCHP_HIF_CPUBIUCTRL_CPU0_PWR_ZONE_CNTRL_REG_ZONE_PWR_OFF_STATE_MASK 0x02000000
-#define BCHP_HIF_CPUBIUCTRL_CPU0_PWR_ZONE_CNTRL_REG_ZONE_PWR_OFF_STATE_SHIFT 25
-
-/* HIF_CPUBIUCTRL :: CPU0_PWR_ZONE_CNTRL_REG :: FREQ_SCALAR_DYNAMIC_SEL [24:24] */
-#define BCHP_HIF_CPUBIUCTRL_CPU0_PWR_ZONE_CNTRL_REG_FREQ_SCALAR_DYNAMIC_SEL_MASK 0x01000000
-#define BCHP_HIF_CPUBIUCTRL_CPU0_PWR_ZONE_CNTRL_REG_FREQ_SCALAR_DYNAMIC_SEL_SHIFT 24
-
-/* HIF_CPUBIUCTRL :: CPU0_PWR_ZONE_CNTRL_REG :: ZONE_PWR_CNTL_STATE [23:19] */
-#define BCHP_HIF_CPUBIUCTRL_CPU0_PWR_ZONE_CNTRL_REG_ZONE_PWR_CNTL_STATE_MASK 0x00f80000
-#define BCHP_HIF_CPUBIUCTRL_CPU0_PWR_ZONE_CNTRL_REG_ZONE_PWR_CNTL_STATE_SHIFT 19
-
-/* HIF_CPUBIUCTRL :: CPU0_PWR_ZONE_CNTRL_REG :: reserved0 [18:14] */
-#define BCHP_HIF_CPUBIUCTRL_CPU0_PWR_ZONE_CNTRL_REG_reserved0_MASK 0x0007c000
-#define BCHP_HIF_CPUBIUCTRL_CPU0_PWR_ZONE_CNTRL_REG_reserved0_SHIFT 14
-
-/* HIF_CPUBIUCTRL :: CPU0_PWR_ZONE_CNTRL_REG :: ZONE_MEM_STBY [13:13] */
-#define BCHP_HIF_CPUBIUCTRL_CPU0_PWR_ZONE_CNTRL_REG_ZONE_MEM_STBY_MASK 0x00002000
-#define BCHP_HIF_CPUBIUCTRL_CPU0_PWR_ZONE_CNTRL_REG_ZONE_MEM_STBY_SHIFT 13
-
-/* HIF_CPUBIUCTRL :: CPU0_PWR_ZONE_CNTRL_REG :: ZONE_BLK_RST_ASSERT [12:12] */
-#define BCHP_HIF_CPUBIUCTRL_CPU0_PWR_ZONE_CNTRL_REG_ZONE_BLK_RST_ASSERT_MASK 0x00001000
-#define BCHP_HIF_CPUBIUCTRL_CPU0_PWR_ZONE_CNTRL_REG_ZONE_BLK_RST_ASSERT_SHIFT 12
-#define BCHP_HIF_CPUBIUCTRL_CPU0_PWR_ZONE_CNTRL_REG_ZONE_BLK_RST_ASSERT_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: CPU0_PWR_ZONE_CNTRL_REG :: ZONE_MEM_PWR_CNTL_EN [11:11] */
-#define BCHP_HIF_CPUBIUCTRL_CPU0_PWR_ZONE_CNTRL_REG_ZONE_MEM_PWR_CNTL_EN_MASK 0x00000800
-#define BCHP_HIF_CPUBIUCTRL_CPU0_PWR_ZONE_CNTRL_REG_ZONE_MEM_PWR_CNTL_EN_SHIFT 11
-#define BCHP_HIF_CPUBIUCTRL_CPU0_PWR_ZONE_CNTRL_REG_ZONE_MEM_PWR_CNTL_EN_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: CPU0_PWR_ZONE_CNTRL_REG :: ZONE_PWR_UP_REQ [10:10] */
-#define BCHP_HIF_CPUBIUCTRL_CPU0_PWR_ZONE_CNTRL_REG_ZONE_PWR_UP_REQ_MASK 0x00000400
-#define BCHP_HIF_CPUBIUCTRL_CPU0_PWR_ZONE_CNTRL_REG_ZONE_PWR_UP_REQ_SHIFT 10
-#define BCHP_HIF_CPUBIUCTRL_CPU0_PWR_ZONE_CNTRL_REG_ZONE_PWR_UP_REQ_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: CPU0_PWR_ZONE_CNTRL_REG :: ZONE_PWR_DN_REQ [09:09] */
-#define BCHP_HIF_CPUBIUCTRL_CPU0_PWR_ZONE_CNTRL_REG_ZONE_PWR_DN_REQ_MASK 0x00000200
-#define BCHP_HIF_CPUBIUCTRL_CPU0_PWR_ZONE_CNTRL_REG_ZONE_PWR_DN_REQ_SHIFT 9
-#define BCHP_HIF_CPUBIUCTRL_CPU0_PWR_ZONE_CNTRL_REG_ZONE_PWR_DN_REQ_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: CPU0_PWR_ZONE_CNTRL_REG :: ZONE_DPG_CNTL_EN [08:08] */
-#define BCHP_HIF_CPUBIUCTRL_CPU0_PWR_ZONE_CNTRL_REG_ZONE_DPG_CNTL_EN_MASK 0x00000100
-#define BCHP_HIF_CPUBIUCTRL_CPU0_PWR_ZONE_CNTRL_REG_ZONE_DPG_CNTL_EN_SHIFT 8
-#define BCHP_HIF_CPUBIUCTRL_CPU0_PWR_ZONE_CNTRL_REG_ZONE_DPG_CNTL_EN_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: CPU0_PWR_ZONE_CNTRL_REG :: ZONE_MANUAL_CONTROL [07:07] */
-#define BCHP_HIF_CPUBIUCTRL_CPU0_PWR_ZONE_CNTRL_REG_ZONE_MANUAL_CONTROL_MASK 0x00000080
-#define BCHP_HIF_CPUBIUCTRL_CPU0_PWR_ZONE_CNTRL_REG_ZONE_MANUAL_CONTROL_SHIFT 7
-#define BCHP_HIF_CPUBIUCTRL_CPU0_PWR_ZONE_CNTRL_REG_ZONE_MANUAL_CONTROL_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: CPU0_PWR_ZONE_CNTRL_REG :: ZONE_MAN_ISO_CNTL [06:06] */
-#define BCHP_HIF_CPUBIUCTRL_CPU0_PWR_ZONE_CNTRL_REG_ZONE_MAN_ISO_CNTL_MASK 0x00000040
-#define BCHP_HIF_CPUBIUCTRL_CPU0_PWR_ZONE_CNTRL_REG_ZONE_MAN_ISO_CNTL_SHIFT 6
-#define BCHP_HIF_CPUBIUCTRL_CPU0_PWR_ZONE_CNTRL_REG_ZONE_MAN_ISO_CNTL_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: CPU0_PWR_ZONE_CNTRL_REG :: reserved1 [05:05] */
-#define BCHP_HIF_CPUBIUCTRL_CPU0_PWR_ZONE_CNTRL_REG_reserved1_MASK 0x00000020
-#define BCHP_HIF_CPUBIUCTRL_CPU0_PWR_ZONE_CNTRL_REG_reserved1_SHIFT 5
-
-/* HIF_CPUBIUCTRL :: CPU0_PWR_ZONE_CNTRL_REG :: ZONE_MAN_MEM_PWR [04:04] */
-#define BCHP_HIF_CPUBIUCTRL_CPU0_PWR_ZONE_CNTRL_REG_ZONE_MAN_MEM_PWR_MASK 0x00000010
-#define BCHP_HIF_CPUBIUCTRL_CPU0_PWR_ZONE_CNTRL_REG_ZONE_MAN_MEM_PWR_SHIFT 4
-#define BCHP_HIF_CPUBIUCTRL_CPU0_PWR_ZONE_CNTRL_REG_ZONE_MAN_MEM_PWR_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: CPU0_PWR_ZONE_CNTRL_REG :: ZONE_DPG_CAPABLE [03:03] */
-#define BCHP_HIF_CPUBIUCTRL_CPU0_PWR_ZONE_CNTRL_REG_ZONE_DPG_CAPABLE_MASK 0x00000008
-#define BCHP_HIF_CPUBIUCTRL_CPU0_PWR_ZONE_CNTRL_REG_ZONE_DPG_CAPABLE_SHIFT 3
-
-/* HIF_CPUBIUCTRL :: CPU0_PWR_ZONE_CNTRL_REG :: ZONE_FREQ_SCALE_USED [02:02] */
-#define BCHP_HIF_CPUBIUCTRL_CPU0_PWR_ZONE_CNTRL_REG_ZONE_FREQ_SCALE_USED_MASK 0x00000004
-#define BCHP_HIF_CPUBIUCTRL_CPU0_PWR_ZONE_CNTRL_REG_ZONE_FREQ_SCALE_USED_SHIFT 2
-
-/* HIF_CPUBIUCTRL :: CPU0_PWR_ZONE_CNTRL_REG :: ZONE_MAN_RESET_CNTL [01:01] */
-#define BCHP_HIF_CPUBIUCTRL_CPU0_PWR_ZONE_CNTRL_REG_ZONE_MAN_RESET_CNTL_MASK 0x00000002
-#define BCHP_HIF_CPUBIUCTRL_CPU0_PWR_ZONE_CNTRL_REG_ZONE_MAN_RESET_CNTL_SHIFT 1
-#define BCHP_HIF_CPUBIUCTRL_CPU0_PWR_ZONE_CNTRL_REG_ZONE_MAN_RESET_CNTL_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: CPU0_PWR_ZONE_CNTRL_REG :: ZONE_MAN_CLKEN [00:00] */
-#define BCHP_HIF_CPUBIUCTRL_CPU0_PWR_ZONE_CNTRL_REG_ZONE_MAN_CLKEN_MASK 0x00000001
-#define BCHP_HIF_CPUBIUCTRL_CPU0_PWR_ZONE_CNTRL_REG_ZONE_MAN_CLKEN_SHIFT 0
-#define BCHP_HIF_CPUBIUCTRL_CPU0_PWR_ZONE_CNTRL_REG_ZONE_MAN_CLKEN_DEFAULT 0x00000000
-
-/***************************************************************************
- *CPU1_PWR_ZONE_CNTRL_REG - CPU1 Power Zone Control Register
- ***************************************************************************/
-/* HIF_CPUBIUCTRL :: CPU1_PWR_ZONE_CNTRL_REG :: ZONE_RESET_STATE [31:31] */
-#define BCHP_HIF_CPUBIUCTRL_CPU1_PWR_ZONE_CNTRL_REG_ZONE_RESET_STATE_MASK 0x80000000
-#define BCHP_HIF_CPUBIUCTRL_CPU1_PWR_ZONE_CNTRL_REG_ZONE_RESET_STATE_SHIFT 31
-
-/* HIF_CPUBIUCTRL :: CPU1_PWR_ZONE_CNTRL_REG :: ZONE_ISO_STATE [30:30] */
-#define BCHP_HIF_CPUBIUCTRL_CPU1_PWR_ZONE_CNTRL_REG_ZONE_ISO_STATE_MASK 0x40000000
-#define BCHP_HIF_CPUBIUCTRL_CPU1_PWR_ZONE_CNTRL_REG_ZONE_ISO_STATE_SHIFT 30
-
-/* HIF_CPUBIUCTRL :: CPU1_PWR_ZONE_CNTRL_REG :: ZONE_MEM_PWR_STATE [29:29] */
-#define BCHP_HIF_CPUBIUCTRL_CPU1_PWR_ZONE_CNTRL_REG_ZONE_MEM_PWR_STATE_MASK 0x20000000
-#define BCHP_HIF_CPUBIUCTRL_CPU1_PWR_ZONE_CNTRL_REG_ZONE_MEM_PWR_STATE_SHIFT 29
-
-/* HIF_CPUBIUCTRL :: CPU1_PWR_ZONE_CNTRL_REG :: ZONE_DPG_PWR_STATE [28:28] */
-#define BCHP_HIF_CPUBIUCTRL_CPU1_PWR_ZONE_CNTRL_REG_ZONE_DPG_PWR_STATE_MASK 0x10000000
-#define BCHP_HIF_CPUBIUCTRL_CPU1_PWR_ZONE_CNTRL_REG_ZONE_DPG_PWR_STATE_SHIFT 28
-
-/* HIF_CPUBIUCTRL :: CPU1_PWR_ZONE_CNTRL_REG :: ZONE_POWER_GOOD [27:27] */
-#define BCHP_HIF_CPUBIUCTRL_CPU1_PWR_ZONE_CNTRL_REG_ZONE_POWER_GOOD_MASK 0x08000000
-#define BCHP_HIF_CPUBIUCTRL_CPU1_PWR_ZONE_CNTRL_REG_ZONE_POWER_GOOD_SHIFT 27
-
-/* HIF_CPUBIUCTRL :: CPU1_PWR_ZONE_CNTRL_REG :: ZONE_PWR_ON_STATE [26:26] */
-#define BCHP_HIF_CPUBIUCTRL_CPU1_PWR_ZONE_CNTRL_REG_ZONE_PWR_ON_STATE_MASK 0x04000000
-#define BCHP_HIF_CPUBIUCTRL_CPU1_PWR_ZONE_CNTRL_REG_ZONE_PWR_ON_STATE_SHIFT 26
-
-/* HIF_CPUBIUCTRL :: CPU1_PWR_ZONE_CNTRL_REG :: ZONE_PWR_OFF_STATE [25:25] */
-#define BCHP_HIF_CPUBIUCTRL_CPU1_PWR_ZONE_CNTRL_REG_ZONE_PWR_OFF_STATE_MASK 0x02000000
-#define BCHP_HIF_CPUBIUCTRL_CPU1_PWR_ZONE_CNTRL_REG_ZONE_PWR_OFF_STATE_SHIFT 25
-
-/* HIF_CPUBIUCTRL :: CPU1_PWR_ZONE_CNTRL_REG :: FREQ_SCALAR_DYNAMIC_SEL [24:24] */
-#define BCHP_HIF_CPUBIUCTRL_CPU1_PWR_ZONE_CNTRL_REG_FREQ_SCALAR_DYNAMIC_SEL_MASK 0x01000000
-#define BCHP_HIF_CPUBIUCTRL_CPU1_PWR_ZONE_CNTRL_REG_FREQ_SCALAR_DYNAMIC_SEL_SHIFT 24
-
-/* HIF_CPUBIUCTRL :: CPU1_PWR_ZONE_CNTRL_REG :: ZONE_PWR_CNTL_STATE [23:19] */
-#define BCHP_HIF_CPUBIUCTRL_CPU1_PWR_ZONE_CNTRL_REG_ZONE_PWR_CNTL_STATE_MASK 0x00f80000
-#define BCHP_HIF_CPUBIUCTRL_CPU1_PWR_ZONE_CNTRL_REG_ZONE_PWR_CNTL_STATE_SHIFT 19
-
-/* HIF_CPUBIUCTRL :: CPU1_PWR_ZONE_CNTRL_REG :: reserved0 [18:14] */
-#define BCHP_HIF_CPUBIUCTRL_CPU1_PWR_ZONE_CNTRL_REG_reserved0_MASK 0x0007c000
-#define BCHP_HIF_CPUBIUCTRL_CPU1_PWR_ZONE_CNTRL_REG_reserved0_SHIFT 14
-
-/* HIF_CPUBIUCTRL :: CPU1_PWR_ZONE_CNTRL_REG :: ZONE_MEM_STBY [13:13] */
-#define BCHP_HIF_CPUBIUCTRL_CPU1_PWR_ZONE_CNTRL_REG_ZONE_MEM_STBY_MASK 0x00002000
-#define BCHP_HIF_CPUBIUCTRL_CPU1_PWR_ZONE_CNTRL_REG_ZONE_MEM_STBY_SHIFT 13
-
-/* HIF_CPUBIUCTRL :: CPU1_PWR_ZONE_CNTRL_REG :: ZONE_BLK_RST_ASSERT [12:12] */
-#define BCHP_HIF_CPUBIUCTRL_CPU1_PWR_ZONE_CNTRL_REG_ZONE_BLK_RST_ASSERT_MASK 0x00001000
-#define BCHP_HIF_CPUBIUCTRL_CPU1_PWR_ZONE_CNTRL_REG_ZONE_BLK_RST_ASSERT_SHIFT 12
-#define BCHP_HIF_CPUBIUCTRL_CPU1_PWR_ZONE_CNTRL_REG_ZONE_BLK_RST_ASSERT_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: CPU1_PWR_ZONE_CNTRL_REG :: ZONE_MEM_PWR_CNTL_EN [11:11] */
-#define BCHP_HIF_CPUBIUCTRL_CPU1_PWR_ZONE_CNTRL_REG_ZONE_MEM_PWR_CNTL_EN_MASK 0x00000800
-#define BCHP_HIF_CPUBIUCTRL_CPU1_PWR_ZONE_CNTRL_REG_ZONE_MEM_PWR_CNTL_EN_SHIFT 11
-#define BCHP_HIF_CPUBIUCTRL_CPU1_PWR_ZONE_CNTRL_REG_ZONE_MEM_PWR_CNTL_EN_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: CPU1_PWR_ZONE_CNTRL_REG :: ZONE_PWR_UP_REQ [10:10] */
-#define BCHP_HIF_CPUBIUCTRL_CPU1_PWR_ZONE_CNTRL_REG_ZONE_PWR_UP_REQ_MASK 0x00000400
-#define BCHP_HIF_CPUBIUCTRL_CPU1_PWR_ZONE_CNTRL_REG_ZONE_PWR_UP_REQ_SHIFT 10
-#define BCHP_HIF_CPUBIUCTRL_CPU1_PWR_ZONE_CNTRL_REG_ZONE_PWR_UP_REQ_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: CPU1_PWR_ZONE_CNTRL_REG :: ZONE_PWR_DN_REQ [09:09] */
-#define BCHP_HIF_CPUBIUCTRL_CPU1_PWR_ZONE_CNTRL_REG_ZONE_PWR_DN_REQ_MASK 0x00000200
-#define BCHP_HIF_CPUBIUCTRL_CPU1_PWR_ZONE_CNTRL_REG_ZONE_PWR_DN_REQ_SHIFT 9
-#define BCHP_HIF_CPUBIUCTRL_CPU1_PWR_ZONE_CNTRL_REG_ZONE_PWR_DN_REQ_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: CPU1_PWR_ZONE_CNTRL_REG :: ZONE_DPG_CNTL_EN [08:08] */
-#define BCHP_HIF_CPUBIUCTRL_CPU1_PWR_ZONE_CNTRL_REG_ZONE_DPG_CNTL_EN_MASK 0x00000100
-#define BCHP_HIF_CPUBIUCTRL_CPU1_PWR_ZONE_CNTRL_REG_ZONE_DPG_CNTL_EN_SHIFT 8
-#define BCHP_HIF_CPUBIUCTRL_CPU1_PWR_ZONE_CNTRL_REG_ZONE_DPG_CNTL_EN_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: CPU1_PWR_ZONE_CNTRL_REG :: ZONE_MANUAL_CONTROL [07:07] */
-#define BCHP_HIF_CPUBIUCTRL_CPU1_PWR_ZONE_CNTRL_REG_ZONE_MANUAL_CONTROL_MASK 0x00000080
-#define BCHP_HIF_CPUBIUCTRL_CPU1_PWR_ZONE_CNTRL_REG_ZONE_MANUAL_CONTROL_SHIFT 7
-#define BCHP_HIF_CPUBIUCTRL_CPU1_PWR_ZONE_CNTRL_REG_ZONE_MANUAL_CONTROL_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: CPU1_PWR_ZONE_CNTRL_REG :: ZONE_MAN_ISO_CNTL [06:06] */
-#define BCHP_HIF_CPUBIUCTRL_CPU1_PWR_ZONE_CNTRL_REG_ZONE_MAN_ISO_CNTL_MASK 0x00000040
-#define BCHP_HIF_CPUBIUCTRL_CPU1_PWR_ZONE_CNTRL_REG_ZONE_MAN_ISO_CNTL_SHIFT 6
-#define BCHP_HIF_CPUBIUCTRL_CPU1_PWR_ZONE_CNTRL_REG_ZONE_MAN_ISO_CNTL_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: CPU1_PWR_ZONE_CNTRL_REG :: reserved1 [05:05] */
-#define BCHP_HIF_CPUBIUCTRL_CPU1_PWR_ZONE_CNTRL_REG_reserved1_MASK 0x00000020
-#define BCHP_HIF_CPUBIUCTRL_CPU1_PWR_ZONE_CNTRL_REG_reserved1_SHIFT 5
-
-/* HIF_CPUBIUCTRL :: CPU1_PWR_ZONE_CNTRL_REG :: ZONE_MAN_MEM_PWR [04:04] */
-#define BCHP_HIF_CPUBIUCTRL_CPU1_PWR_ZONE_CNTRL_REG_ZONE_MAN_MEM_PWR_MASK 0x00000010
-#define BCHP_HIF_CPUBIUCTRL_CPU1_PWR_ZONE_CNTRL_REG_ZONE_MAN_MEM_PWR_SHIFT 4
-#define BCHP_HIF_CPUBIUCTRL_CPU1_PWR_ZONE_CNTRL_REG_ZONE_MAN_MEM_PWR_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: CPU1_PWR_ZONE_CNTRL_REG :: ZONE_DPG_CAPABLE [03:03] */
-#define BCHP_HIF_CPUBIUCTRL_CPU1_PWR_ZONE_CNTRL_REG_ZONE_DPG_CAPABLE_MASK 0x00000008
-#define BCHP_HIF_CPUBIUCTRL_CPU1_PWR_ZONE_CNTRL_REG_ZONE_DPG_CAPABLE_SHIFT 3
-
-/* HIF_CPUBIUCTRL :: CPU1_PWR_ZONE_CNTRL_REG :: ZONE_FREQ_SCALE_USED [02:02] */
-#define BCHP_HIF_CPUBIUCTRL_CPU1_PWR_ZONE_CNTRL_REG_ZONE_FREQ_SCALE_USED_MASK 0x00000004
-#define BCHP_HIF_CPUBIUCTRL_CPU1_PWR_ZONE_CNTRL_REG_ZONE_FREQ_SCALE_USED_SHIFT 2
-
-/* HIF_CPUBIUCTRL :: CPU1_PWR_ZONE_CNTRL_REG :: ZONE_MAN_RESET_CNTL [01:01] */
-#define BCHP_HIF_CPUBIUCTRL_CPU1_PWR_ZONE_CNTRL_REG_ZONE_MAN_RESET_CNTL_MASK 0x00000002
-#define BCHP_HIF_CPUBIUCTRL_CPU1_PWR_ZONE_CNTRL_REG_ZONE_MAN_RESET_CNTL_SHIFT 1
-#define BCHP_HIF_CPUBIUCTRL_CPU1_PWR_ZONE_CNTRL_REG_ZONE_MAN_RESET_CNTL_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: CPU1_PWR_ZONE_CNTRL_REG :: ZONE_MAN_CLKEN [00:00] */
-#define BCHP_HIF_CPUBIUCTRL_CPU1_PWR_ZONE_CNTRL_REG_ZONE_MAN_CLKEN_MASK 0x00000001
-#define BCHP_HIF_CPUBIUCTRL_CPU1_PWR_ZONE_CNTRL_REG_ZONE_MAN_CLKEN_SHIFT 0
-#define BCHP_HIF_CPUBIUCTRL_CPU1_PWR_ZONE_CNTRL_REG_ZONE_MAN_CLKEN_DEFAULT 0x00000000
-
-/***************************************************************************
- *CPU2_PWR_ZONE_CNTRL_REG - CPU2 Power Zone Control Register
- ***************************************************************************/
-/* HIF_CPUBIUCTRL :: CPU2_PWR_ZONE_CNTRL_REG :: ZONE_RESET_STATE [31:31] */
-#define BCHP_HIF_CPUBIUCTRL_CPU2_PWR_ZONE_CNTRL_REG_ZONE_RESET_STATE_MASK 0x80000000
-#define BCHP_HIF_CPUBIUCTRL_CPU2_PWR_ZONE_CNTRL_REG_ZONE_RESET_STATE_SHIFT 31
-
-/* HIF_CPUBIUCTRL :: CPU2_PWR_ZONE_CNTRL_REG :: ZONE_ISO_STATE [30:30] */
-#define BCHP_HIF_CPUBIUCTRL_CPU2_PWR_ZONE_CNTRL_REG_ZONE_ISO_STATE_MASK 0x40000000
-#define BCHP_HIF_CPUBIUCTRL_CPU2_PWR_ZONE_CNTRL_REG_ZONE_ISO_STATE_SHIFT 30
-
-/* HIF_CPUBIUCTRL :: CPU2_PWR_ZONE_CNTRL_REG :: ZONE_MEM_PWR_STATE [29:29] */
-#define BCHP_HIF_CPUBIUCTRL_CPU2_PWR_ZONE_CNTRL_REG_ZONE_MEM_PWR_STATE_MASK 0x20000000
-#define BCHP_HIF_CPUBIUCTRL_CPU2_PWR_ZONE_CNTRL_REG_ZONE_MEM_PWR_STATE_SHIFT 29
-
-/* HIF_CPUBIUCTRL :: CPU2_PWR_ZONE_CNTRL_REG :: ZONE_DPG_PWR_STATE [28:28] */
-#define BCHP_HIF_CPUBIUCTRL_CPU2_PWR_ZONE_CNTRL_REG_ZONE_DPG_PWR_STATE_MASK 0x10000000
-#define BCHP_HIF_CPUBIUCTRL_CPU2_PWR_ZONE_CNTRL_REG_ZONE_DPG_PWR_STATE_SHIFT 28
-
-/* HIF_CPUBIUCTRL :: CPU2_PWR_ZONE_CNTRL_REG :: ZONE_POWER_GOOD [27:27] */
-#define BCHP_HIF_CPUBIUCTRL_CPU2_PWR_ZONE_CNTRL_REG_ZONE_POWER_GOOD_MASK 0x08000000
-#define BCHP_HIF_CPUBIUCTRL_CPU2_PWR_ZONE_CNTRL_REG_ZONE_POWER_GOOD_SHIFT 27
-
-/* HIF_CPUBIUCTRL :: CPU2_PWR_ZONE_CNTRL_REG :: ZONE_PWR_ON_STATE [26:26] */
-#define BCHP_HIF_CPUBIUCTRL_CPU2_PWR_ZONE_CNTRL_REG_ZONE_PWR_ON_STATE_MASK 0x04000000
-#define BCHP_HIF_CPUBIUCTRL_CPU2_PWR_ZONE_CNTRL_REG_ZONE_PWR_ON_STATE_SHIFT 26
-
-/* HIF_CPUBIUCTRL :: CPU2_PWR_ZONE_CNTRL_REG :: ZONE_PWR_OFF_STATE [25:25] */
-#define BCHP_HIF_CPUBIUCTRL_CPU2_PWR_ZONE_CNTRL_REG_ZONE_PWR_OFF_STATE_MASK 0x02000000
-#define BCHP_HIF_CPUBIUCTRL_CPU2_PWR_ZONE_CNTRL_REG_ZONE_PWR_OFF_STATE_SHIFT 25
-
-/* HIF_CPUBIUCTRL :: CPU2_PWR_ZONE_CNTRL_REG :: FREQ_SCALAR_DYNAMIC_SEL [24:24] */
-#define BCHP_HIF_CPUBIUCTRL_CPU2_PWR_ZONE_CNTRL_REG_FREQ_SCALAR_DYNAMIC_SEL_MASK 0x01000000
-#define BCHP_HIF_CPUBIUCTRL_CPU2_PWR_ZONE_CNTRL_REG_FREQ_SCALAR_DYNAMIC_SEL_SHIFT 24
-
-/* HIF_CPUBIUCTRL :: CPU2_PWR_ZONE_CNTRL_REG :: ZONE_PWR_CNTL_STATE [23:19] */
-#define BCHP_HIF_CPUBIUCTRL_CPU2_PWR_ZONE_CNTRL_REG_ZONE_PWR_CNTL_STATE_MASK 0x00f80000
-#define BCHP_HIF_CPUBIUCTRL_CPU2_PWR_ZONE_CNTRL_REG_ZONE_PWR_CNTL_STATE_SHIFT 19
-
-/* HIF_CPUBIUCTRL :: CPU2_PWR_ZONE_CNTRL_REG :: reserved0 [18:14] */
-#define BCHP_HIF_CPUBIUCTRL_CPU2_PWR_ZONE_CNTRL_REG_reserved0_MASK 0x0007c000
-#define BCHP_HIF_CPUBIUCTRL_CPU2_PWR_ZONE_CNTRL_REG_reserved0_SHIFT 14
-
-/* HIF_CPUBIUCTRL :: CPU2_PWR_ZONE_CNTRL_REG :: ZONE_MEM_STBY [13:13] */
-#define BCHP_HIF_CPUBIUCTRL_CPU2_PWR_ZONE_CNTRL_REG_ZONE_MEM_STBY_MASK 0x00002000
-#define BCHP_HIF_CPUBIUCTRL_CPU2_PWR_ZONE_CNTRL_REG_ZONE_MEM_STBY_SHIFT 13
-
-/* HIF_CPUBIUCTRL :: CPU2_PWR_ZONE_CNTRL_REG :: ZONE_BLK_RST_ASSERT [12:12] */
-#define BCHP_HIF_CPUBIUCTRL_CPU2_PWR_ZONE_CNTRL_REG_ZONE_BLK_RST_ASSERT_MASK 0x00001000
-#define BCHP_HIF_CPUBIUCTRL_CPU2_PWR_ZONE_CNTRL_REG_ZONE_BLK_RST_ASSERT_SHIFT 12
-#define BCHP_HIF_CPUBIUCTRL_CPU2_PWR_ZONE_CNTRL_REG_ZONE_BLK_RST_ASSERT_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: CPU2_PWR_ZONE_CNTRL_REG :: ZONE_MEM_PWR_CNTL_EN [11:11] */
-#define BCHP_HIF_CPUBIUCTRL_CPU2_PWR_ZONE_CNTRL_REG_ZONE_MEM_PWR_CNTL_EN_MASK 0x00000800
-#define BCHP_HIF_CPUBIUCTRL_CPU2_PWR_ZONE_CNTRL_REG_ZONE_MEM_PWR_CNTL_EN_SHIFT 11
-#define BCHP_HIF_CPUBIUCTRL_CPU2_PWR_ZONE_CNTRL_REG_ZONE_MEM_PWR_CNTL_EN_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: CPU2_PWR_ZONE_CNTRL_REG :: ZONE_PWR_UP_REQ [10:10] */
-#define BCHP_HIF_CPUBIUCTRL_CPU2_PWR_ZONE_CNTRL_REG_ZONE_PWR_UP_REQ_MASK 0x00000400
-#define BCHP_HIF_CPUBIUCTRL_CPU2_PWR_ZONE_CNTRL_REG_ZONE_PWR_UP_REQ_SHIFT 10
-#define BCHP_HIF_CPUBIUCTRL_CPU2_PWR_ZONE_CNTRL_REG_ZONE_PWR_UP_REQ_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: CPU2_PWR_ZONE_CNTRL_REG :: ZONE_PWR_DN_REQ [09:09] */
-#define BCHP_HIF_CPUBIUCTRL_CPU2_PWR_ZONE_CNTRL_REG_ZONE_PWR_DN_REQ_MASK 0x00000200
-#define BCHP_HIF_CPUBIUCTRL_CPU2_PWR_ZONE_CNTRL_REG_ZONE_PWR_DN_REQ_SHIFT 9
-#define BCHP_HIF_CPUBIUCTRL_CPU2_PWR_ZONE_CNTRL_REG_ZONE_PWR_DN_REQ_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: CPU2_PWR_ZONE_CNTRL_REG :: ZONE_DPG_CNTL_EN [08:08] */
-#define BCHP_HIF_CPUBIUCTRL_CPU2_PWR_ZONE_CNTRL_REG_ZONE_DPG_CNTL_EN_MASK 0x00000100
-#define BCHP_HIF_CPUBIUCTRL_CPU2_PWR_ZONE_CNTRL_REG_ZONE_DPG_CNTL_EN_SHIFT 8
-#define BCHP_HIF_CPUBIUCTRL_CPU2_PWR_ZONE_CNTRL_REG_ZONE_DPG_CNTL_EN_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: CPU2_PWR_ZONE_CNTRL_REG :: ZONE_MANUAL_CONTROL [07:07] */
-#define BCHP_HIF_CPUBIUCTRL_CPU2_PWR_ZONE_CNTRL_REG_ZONE_MANUAL_CONTROL_MASK 0x00000080
-#define BCHP_HIF_CPUBIUCTRL_CPU2_PWR_ZONE_CNTRL_REG_ZONE_MANUAL_CONTROL_SHIFT 7
-#define BCHP_HIF_CPUBIUCTRL_CPU2_PWR_ZONE_CNTRL_REG_ZONE_MANUAL_CONTROL_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: CPU2_PWR_ZONE_CNTRL_REG :: ZONE_MAN_ISO_CNTL [06:06] */
-#define BCHP_HIF_CPUBIUCTRL_CPU2_PWR_ZONE_CNTRL_REG_ZONE_MAN_ISO_CNTL_MASK 0x00000040
-#define BCHP_HIF_CPUBIUCTRL_CPU2_PWR_ZONE_CNTRL_REG_ZONE_MAN_ISO_CNTL_SHIFT 6
-#define BCHP_HIF_CPUBIUCTRL_CPU2_PWR_ZONE_CNTRL_REG_ZONE_MAN_ISO_CNTL_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: CPU2_PWR_ZONE_CNTRL_REG :: reserved1 [05:05] */
-#define BCHP_HIF_CPUBIUCTRL_CPU2_PWR_ZONE_CNTRL_REG_reserved1_MASK 0x00000020
-#define BCHP_HIF_CPUBIUCTRL_CPU2_PWR_ZONE_CNTRL_REG_reserved1_SHIFT 5
-
-/* HIF_CPUBIUCTRL :: CPU2_PWR_ZONE_CNTRL_REG :: ZONE_MAN_MEM_PWR [04:04] */
-#define BCHP_HIF_CPUBIUCTRL_CPU2_PWR_ZONE_CNTRL_REG_ZONE_MAN_MEM_PWR_MASK 0x00000010
-#define BCHP_HIF_CPUBIUCTRL_CPU2_PWR_ZONE_CNTRL_REG_ZONE_MAN_MEM_PWR_SHIFT 4
-#define BCHP_HIF_CPUBIUCTRL_CPU2_PWR_ZONE_CNTRL_REG_ZONE_MAN_MEM_PWR_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: CPU2_PWR_ZONE_CNTRL_REG :: ZONE_DPG_CAPABLE [03:03] */
-#define BCHP_HIF_CPUBIUCTRL_CPU2_PWR_ZONE_CNTRL_REG_ZONE_DPG_CAPABLE_MASK 0x00000008
-#define BCHP_HIF_CPUBIUCTRL_CPU2_PWR_ZONE_CNTRL_REG_ZONE_DPG_CAPABLE_SHIFT 3
-
-/* HIF_CPUBIUCTRL :: CPU2_PWR_ZONE_CNTRL_REG :: ZONE_FREQ_SCALE_USED [02:02] */
-#define BCHP_HIF_CPUBIUCTRL_CPU2_PWR_ZONE_CNTRL_REG_ZONE_FREQ_SCALE_USED_MASK 0x00000004
-#define BCHP_HIF_CPUBIUCTRL_CPU2_PWR_ZONE_CNTRL_REG_ZONE_FREQ_SCALE_USED_SHIFT 2
-
-/* HIF_CPUBIUCTRL :: CPU2_PWR_ZONE_CNTRL_REG :: ZONE_MAN_RESET_CNTL [01:01] */
-#define BCHP_HIF_CPUBIUCTRL_CPU2_PWR_ZONE_CNTRL_REG_ZONE_MAN_RESET_CNTL_MASK 0x00000002
-#define BCHP_HIF_CPUBIUCTRL_CPU2_PWR_ZONE_CNTRL_REG_ZONE_MAN_RESET_CNTL_SHIFT 1
-#define BCHP_HIF_CPUBIUCTRL_CPU2_PWR_ZONE_CNTRL_REG_ZONE_MAN_RESET_CNTL_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: CPU2_PWR_ZONE_CNTRL_REG :: ZONE_MAN_CLKEN [00:00] */
-#define BCHP_HIF_CPUBIUCTRL_CPU2_PWR_ZONE_CNTRL_REG_ZONE_MAN_CLKEN_MASK 0x00000001
-#define BCHP_HIF_CPUBIUCTRL_CPU2_PWR_ZONE_CNTRL_REG_ZONE_MAN_CLKEN_SHIFT 0
-#define BCHP_HIF_CPUBIUCTRL_CPU2_PWR_ZONE_CNTRL_REG_ZONE_MAN_CLKEN_DEFAULT 0x00000000
-
-/***************************************************************************
- *CPU3_PWR_ZONE_CNTRL_REG - CPU3 Power Zone Control Register
- ***************************************************************************/
-/* HIF_CPUBIUCTRL :: CPU3_PWR_ZONE_CNTRL_REG :: ZONE_RESET_STATE [31:31] */
-#define BCHP_HIF_CPUBIUCTRL_CPU3_PWR_ZONE_CNTRL_REG_ZONE_RESET_STATE_MASK 0x80000000
-#define BCHP_HIF_CPUBIUCTRL_CPU3_PWR_ZONE_CNTRL_REG_ZONE_RESET_STATE_SHIFT 31
-
-/* HIF_CPUBIUCTRL :: CPU3_PWR_ZONE_CNTRL_REG :: ZONE_ISO_STATE [30:30] */
-#define BCHP_HIF_CPUBIUCTRL_CPU3_PWR_ZONE_CNTRL_REG_ZONE_ISO_STATE_MASK 0x40000000
-#define BCHP_HIF_CPUBIUCTRL_CPU3_PWR_ZONE_CNTRL_REG_ZONE_ISO_STATE_SHIFT 30
-
-/* HIF_CPUBIUCTRL :: CPU3_PWR_ZONE_CNTRL_REG :: ZONE_MEM_PWR_STATE [29:29] */
-#define BCHP_HIF_CPUBIUCTRL_CPU3_PWR_ZONE_CNTRL_REG_ZONE_MEM_PWR_STATE_MASK 0x20000000
-#define BCHP_HIF_CPUBIUCTRL_CPU3_PWR_ZONE_CNTRL_REG_ZONE_MEM_PWR_STATE_SHIFT 29
-
-/* HIF_CPUBIUCTRL :: CPU3_PWR_ZONE_CNTRL_REG :: ZONE_DPG_PWR_STATE [28:28] */
-#define BCHP_HIF_CPUBIUCTRL_CPU3_PWR_ZONE_CNTRL_REG_ZONE_DPG_PWR_STATE_MASK 0x10000000
-#define BCHP_HIF_CPUBIUCTRL_CPU3_PWR_ZONE_CNTRL_REG_ZONE_DPG_PWR_STATE_SHIFT 28
-
-/* HIF_CPUBIUCTRL :: CPU3_PWR_ZONE_CNTRL_REG :: ZONE_POWER_GOOD [27:27] */
-#define BCHP_HIF_CPUBIUCTRL_CPU3_PWR_ZONE_CNTRL_REG_ZONE_POWER_GOOD_MASK 0x08000000
-#define BCHP_HIF_CPUBIUCTRL_CPU3_PWR_ZONE_CNTRL_REG_ZONE_POWER_GOOD_SHIFT 27
-
-/* HIF_CPUBIUCTRL :: CPU3_PWR_ZONE_CNTRL_REG :: ZONE_PWR_ON_STATE [26:26] */
-#define BCHP_HIF_CPUBIUCTRL_CPU3_PWR_ZONE_CNTRL_REG_ZONE_PWR_ON_STATE_MASK 0x04000000
-#define BCHP_HIF_CPUBIUCTRL_CPU3_PWR_ZONE_CNTRL_REG_ZONE_PWR_ON_STATE_SHIFT 26
-
-/* HIF_CPUBIUCTRL :: CPU3_PWR_ZONE_CNTRL_REG :: ZONE_PWR_OFF_STATE [25:25] */
-#define BCHP_HIF_CPUBIUCTRL_CPU3_PWR_ZONE_CNTRL_REG_ZONE_PWR_OFF_STATE_MASK 0x02000000
-#define BCHP_HIF_CPUBIUCTRL_CPU3_PWR_ZONE_CNTRL_REG_ZONE_PWR_OFF_STATE_SHIFT 25
-
-/* HIF_CPUBIUCTRL :: CPU3_PWR_ZONE_CNTRL_REG :: FREQ_SCALAR_DYNAMIC_SEL [24:24] */
-#define BCHP_HIF_CPUBIUCTRL_CPU3_PWR_ZONE_CNTRL_REG_FREQ_SCALAR_DYNAMIC_SEL_MASK 0x01000000
-#define BCHP_HIF_CPUBIUCTRL_CPU3_PWR_ZONE_CNTRL_REG_FREQ_SCALAR_DYNAMIC_SEL_SHIFT 24
-
-/* HIF_CPUBIUCTRL :: CPU3_PWR_ZONE_CNTRL_REG :: ZONE_PWR_CNTL_STATE [23:19] */
-#define BCHP_HIF_CPUBIUCTRL_CPU3_PWR_ZONE_CNTRL_REG_ZONE_PWR_CNTL_STATE_MASK 0x00f80000
-#define BCHP_HIF_CPUBIUCTRL_CPU3_PWR_ZONE_CNTRL_REG_ZONE_PWR_CNTL_STATE_SHIFT 19
-
-/* HIF_CPUBIUCTRL :: CPU3_PWR_ZONE_CNTRL_REG :: reserved0 [18:14] */
-#define BCHP_HIF_CPUBIUCTRL_CPU3_PWR_ZONE_CNTRL_REG_reserved0_MASK 0x0007c000
-#define BCHP_HIF_CPUBIUCTRL_CPU3_PWR_ZONE_CNTRL_REG_reserved0_SHIFT 14
-
-/* HIF_CPUBIUCTRL :: CPU3_PWR_ZONE_CNTRL_REG :: ZONE_MEM_STBY [13:13] */
-#define BCHP_HIF_CPUBIUCTRL_CPU3_PWR_ZONE_CNTRL_REG_ZONE_MEM_STBY_MASK 0x00002000
-#define BCHP_HIF_CPUBIUCTRL_CPU3_PWR_ZONE_CNTRL_REG_ZONE_MEM_STBY_SHIFT 13
-
-/* HIF_CPUBIUCTRL :: CPU3_PWR_ZONE_CNTRL_REG :: ZONE_BLK_RST_ASSERT [12:12] */
-#define BCHP_HIF_CPUBIUCTRL_CPU3_PWR_ZONE_CNTRL_REG_ZONE_BLK_RST_ASSERT_MASK 0x00001000
-#define BCHP_HIF_CPUBIUCTRL_CPU3_PWR_ZONE_CNTRL_REG_ZONE_BLK_RST_ASSERT_SHIFT 12
-#define BCHP_HIF_CPUBIUCTRL_CPU3_PWR_ZONE_CNTRL_REG_ZONE_BLK_RST_ASSERT_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: CPU3_PWR_ZONE_CNTRL_REG :: ZONE_MEM_PWR_CNTL_EN [11:11] */
-#define BCHP_HIF_CPUBIUCTRL_CPU3_PWR_ZONE_CNTRL_REG_ZONE_MEM_PWR_CNTL_EN_MASK 0x00000800
-#define BCHP_HIF_CPUBIUCTRL_CPU3_PWR_ZONE_CNTRL_REG_ZONE_MEM_PWR_CNTL_EN_SHIFT 11
-#define BCHP_HIF_CPUBIUCTRL_CPU3_PWR_ZONE_CNTRL_REG_ZONE_MEM_PWR_CNTL_EN_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: CPU3_PWR_ZONE_CNTRL_REG :: ZONE_PWR_UP_REQ [10:10] */
-#define BCHP_HIF_CPUBIUCTRL_CPU3_PWR_ZONE_CNTRL_REG_ZONE_PWR_UP_REQ_MASK 0x00000400
-#define BCHP_HIF_CPUBIUCTRL_CPU3_PWR_ZONE_CNTRL_REG_ZONE_PWR_UP_REQ_SHIFT 10
-#define BCHP_HIF_CPUBIUCTRL_CPU3_PWR_ZONE_CNTRL_REG_ZONE_PWR_UP_REQ_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: CPU3_PWR_ZONE_CNTRL_REG :: ZONE_PWR_DN_REQ [09:09] */
-#define BCHP_HIF_CPUBIUCTRL_CPU3_PWR_ZONE_CNTRL_REG_ZONE_PWR_DN_REQ_MASK 0x00000200
-#define BCHP_HIF_CPUBIUCTRL_CPU3_PWR_ZONE_CNTRL_REG_ZONE_PWR_DN_REQ_SHIFT 9
-#define BCHP_HIF_CPUBIUCTRL_CPU3_PWR_ZONE_CNTRL_REG_ZONE_PWR_DN_REQ_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: CPU3_PWR_ZONE_CNTRL_REG :: ZONE_DPG_CNTL_EN [08:08] */
-#define BCHP_HIF_CPUBIUCTRL_CPU3_PWR_ZONE_CNTRL_REG_ZONE_DPG_CNTL_EN_MASK 0x00000100
-#define BCHP_HIF_CPUBIUCTRL_CPU3_PWR_ZONE_CNTRL_REG_ZONE_DPG_CNTL_EN_SHIFT 8
-#define BCHP_HIF_CPUBIUCTRL_CPU3_PWR_ZONE_CNTRL_REG_ZONE_DPG_CNTL_EN_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: CPU3_PWR_ZONE_CNTRL_REG :: ZONE_MANUAL_CONTROL [07:07] */
-#define BCHP_HIF_CPUBIUCTRL_CPU3_PWR_ZONE_CNTRL_REG_ZONE_MANUAL_CONTROL_MASK 0x00000080
-#define BCHP_HIF_CPUBIUCTRL_CPU3_PWR_ZONE_CNTRL_REG_ZONE_MANUAL_CONTROL_SHIFT 7
-#define BCHP_HIF_CPUBIUCTRL_CPU3_PWR_ZONE_CNTRL_REG_ZONE_MANUAL_CONTROL_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: CPU3_PWR_ZONE_CNTRL_REG :: ZONE_MAN_ISO_CNTL [06:06] */
-#define BCHP_HIF_CPUBIUCTRL_CPU3_PWR_ZONE_CNTRL_REG_ZONE_MAN_ISO_CNTL_MASK 0x00000040
-#define BCHP_HIF_CPUBIUCTRL_CPU3_PWR_ZONE_CNTRL_REG_ZONE_MAN_ISO_CNTL_SHIFT 6
-#define BCHP_HIF_CPUBIUCTRL_CPU3_PWR_ZONE_CNTRL_REG_ZONE_MAN_ISO_CNTL_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: CPU3_PWR_ZONE_CNTRL_REG :: reserved1 [05:05] */
-#define BCHP_HIF_CPUBIUCTRL_CPU3_PWR_ZONE_CNTRL_REG_reserved1_MASK 0x00000020
-#define BCHP_HIF_CPUBIUCTRL_CPU3_PWR_ZONE_CNTRL_REG_reserved1_SHIFT 5
-
-/* HIF_CPUBIUCTRL :: CPU3_PWR_ZONE_CNTRL_REG :: ZONE_MAN_MEM_PWR [04:04] */
-#define BCHP_HIF_CPUBIUCTRL_CPU3_PWR_ZONE_CNTRL_REG_ZONE_MAN_MEM_PWR_MASK 0x00000010
-#define BCHP_HIF_CPUBIUCTRL_CPU3_PWR_ZONE_CNTRL_REG_ZONE_MAN_MEM_PWR_SHIFT 4
-#define BCHP_HIF_CPUBIUCTRL_CPU3_PWR_ZONE_CNTRL_REG_ZONE_MAN_MEM_PWR_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: CPU3_PWR_ZONE_CNTRL_REG :: ZONE_DPG_CAPABLE [03:03] */
-#define BCHP_HIF_CPUBIUCTRL_CPU3_PWR_ZONE_CNTRL_REG_ZONE_DPG_CAPABLE_MASK 0x00000008
-#define BCHP_HIF_CPUBIUCTRL_CPU3_PWR_ZONE_CNTRL_REG_ZONE_DPG_CAPABLE_SHIFT 3
-
-/* HIF_CPUBIUCTRL :: CPU3_PWR_ZONE_CNTRL_REG :: ZONE_FREQ_SCALE_USED [02:02] */
-#define BCHP_HIF_CPUBIUCTRL_CPU3_PWR_ZONE_CNTRL_REG_ZONE_FREQ_SCALE_USED_MASK 0x00000004
-#define BCHP_HIF_CPUBIUCTRL_CPU3_PWR_ZONE_CNTRL_REG_ZONE_FREQ_SCALE_USED_SHIFT 2
-
-/* HIF_CPUBIUCTRL :: CPU3_PWR_ZONE_CNTRL_REG :: ZONE_MAN_RESET_CNTL [01:01] */
-#define BCHP_HIF_CPUBIUCTRL_CPU3_PWR_ZONE_CNTRL_REG_ZONE_MAN_RESET_CNTL_MASK 0x00000002
-#define BCHP_HIF_CPUBIUCTRL_CPU3_PWR_ZONE_CNTRL_REG_ZONE_MAN_RESET_CNTL_SHIFT 1
-#define BCHP_HIF_CPUBIUCTRL_CPU3_PWR_ZONE_CNTRL_REG_ZONE_MAN_RESET_CNTL_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: CPU3_PWR_ZONE_CNTRL_REG :: ZONE_MAN_CLKEN [00:00] */
-#define BCHP_HIF_CPUBIUCTRL_CPU3_PWR_ZONE_CNTRL_REG_ZONE_MAN_CLKEN_MASK 0x00000001
-#define BCHP_HIF_CPUBIUCTRL_CPU3_PWR_ZONE_CNTRL_REG_ZONE_MAN_CLKEN_SHIFT 0
-#define BCHP_HIF_CPUBIUCTRL_CPU3_PWR_ZONE_CNTRL_REG_ZONE_MAN_CLKEN_DEFAULT 0x00000000
-
-/***************************************************************************
- *L2BIU_PWR_ZONE_CNTRL_REG - L2 and BIU Power Zone Control Register
- ***************************************************************************/
-/* HIF_CPUBIUCTRL :: L2BIU_PWR_ZONE_CNTRL_REG :: ZONE_RESET_STATE [31:31] */
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_PWR_ZONE_CNTRL_REG_ZONE_RESET_STATE_MASK 0x80000000
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_PWR_ZONE_CNTRL_REG_ZONE_RESET_STATE_SHIFT 31
-
-/* HIF_CPUBIUCTRL :: L2BIU_PWR_ZONE_CNTRL_REG :: ZONE_ISO_STATE [30:30] */
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_PWR_ZONE_CNTRL_REG_ZONE_ISO_STATE_MASK 0x40000000
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_PWR_ZONE_CNTRL_REG_ZONE_ISO_STATE_SHIFT 30
-
-/* HIF_CPUBIUCTRL :: L2BIU_PWR_ZONE_CNTRL_REG :: ZONE_MEM_PWR_STATE [29:29] */
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_PWR_ZONE_CNTRL_REG_ZONE_MEM_PWR_STATE_MASK 0x20000000
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_PWR_ZONE_CNTRL_REG_ZONE_MEM_PWR_STATE_SHIFT 29
-
-/* HIF_CPUBIUCTRL :: L2BIU_PWR_ZONE_CNTRL_REG :: ZONE_DPG_PWR_STATE [28:28] */
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_PWR_ZONE_CNTRL_REG_ZONE_DPG_PWR_STATE_MASK 0x10000000
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_PWR_ZONE_CNTRL_REG_ZONE_DPG_PWR_STATE_SHIFT 28
-
-/* HIF_CPUBIUCTRL :: L2BIU_PWR_ZONE_CNTRL_REG :: ZONE_POWER_GOOD [27:27] */
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_PWR_ZONE_CNTRL_REG_ZONE_POWER_GOOD_MASK 0x08000000
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_PWR_ZONE_CNTRL_REG_ZONE_POWER_GOOD_SHIFT 27
-
-/* HIF_CPUBIUCTRL :: L2BIU_PWR_ZONE_CNTRL_REG :: ZONE_PWR_ON_STATE [26:26] */
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_PWR_ZONE_CNTRL_REG_ZONE_PWR_ON_STATE_MASK 0x04000000
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_PWR_ZONE_CNTRL_REG_ZONE_PWR_ON_STATE_SHIFT 26
-
-/* HIF_CPUBIUCTRL :: L2BIU_PWR_ZONE_CNTRL_REG :: ZONE_PWR_OFF_STATE [25:25] */
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_PWR_ZONE_CNTRL_REG_ZONE_PWR_OFF_STATE_MASK 0x02000000
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_PWR_ZONE_CNTRL_REG_ZONE_PWR_OFF_STATE_SHIFT 25
-
-/* HIF_CPUBIUCTRL :: L2BIU_PWR_ZONE_CNTRL_REG :: FREQ_SCALAR_DYNAMIC_SEL [24:24] */
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_PWR_ZONE_CNTRL_REG_FREQ_SCALAR_DYNAMIC_SEL_MASK 0x01000000
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_PWR_ZONE_CNTRL_REG_FREQ_SCALAR_DYNAMIC_SEL_SHIFT 24
-
-/* HIF_CPUBIUCTRL :: L2BIU_PWR_ZONE_CNTRL_REG :: ZONE_PWR_CNTL_STATE [23:19] */
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_PWR_ZONE_CNTRL_REG_ZONE_PWR_CNTL_STATE_MASK 0x00f80000
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_PWR_ZONE_CNTRL_REG_ZONE_PWR_CNTL_STATE_SHIFT 19
-
-/* HIF_CPUBIUCTRL :: L2BIU_PWR_ZONE_CNTRL_REG :: reserved0 [18:14] */
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_PWR_ZONE_CNTRL_REG_reserved0_MASK 0x0007c000
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_PWR_ZONE_CNTRL_REG_reserved0_SHIFT 14
-
-/* HIF_CPUBIUCTRL :: L2BIU_PWR_ZONE_CNTRL_REG :: ZONE_MEM_STBY [13:13] */
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_PWR_ZONE_CNTRL_REG_ZONE_MEM_STBY_MASK 0x00002000
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_PWR_ZONE_CNTRL_REG_ZONE_MEM_STBY_SHIFT 13
-
-/* HIF_CPUBIUCTRL :: L2BIU_PWR_ZONE_CNTRL_REG :: ZONE_BLK_RST_ASSERT [12:12] */
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_PWR_ZONE_CNTRL_REG_ZONE_BLK_RST_ASSERT_MASK 0x00001000
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_PWR_ZONE_CNTRL_REG_ZONE_BLK_RST_ASSERT_SHIFT 12
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_PWR_ZONE_CNTRL_REG_ZONE_BLK_RST_ASSERT_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: L2BIU_PWR_ZONE_CNTRL_REG :: ZONE_MEM_PWR_CNTL_EN [11:11] */
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_PWR_ZONE_CNTRL_REG_ZONE_MEM_PWR_CNTL_EN_MASK 0x00000800
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_PWR_ZONE_CNTRL_REG_ZONE_MEM_PWR_CNTL_EN_SHIFT 11
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_PWR_ZONE_CNTRL_REG_ZONE_MEM_PWR_CNTL_EN_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: L2BIU_PWR_ZONE_CNTRL_REG :: ZONE_PWR_UP_REQ [10:10] */
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_PWR_ZONE_CNTRL_REG_ZONE_PWR_UP_REQ_MASK 0x00000400
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_PWR_ZONE_CNTRL_REG_ZONE_PWR_UP_REQ_SHIFT 10
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_PWR_ZONE_CNTRL_REG_ZONE_PWR_UP_REQ_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: L2BIU_PWR_ZONE_CNTRL_REG :: ZONE_PWR_DN_REQ [09:09] */
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_PWR_ZONE_CNTRL_REG_ZONE_PWR_DN_REQ_MASK 0x00000200
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_PWR_ZONE_CNTRL_REG_ZONE_PWR_DN_REQ_SHIFT 9
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_PWR_ZONE_CNTRL_REG_ZONE_PWR_DN_REQ_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: L2BIU_PWR_ZONE_CNTRL_REG :: ZONE_DPG_CNTL_EN [08:08] */
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_PWR_ZONE_CNTRL_REG_ZONE_DPG_CNTL_EN_MASK 0x00000100
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_PWR_ZONE_CNTRL_REG_ZONE_DPG_CNTL_EN_SHIFT 8
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_PWR_ZONE_CNTRL_REG_ZONE_DPG_CNTL_EN_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: L2BIU_PWR_ZONE_CNTRL_REG :: ZONE_MANUAL_CONTROL [07:07] */
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_PWR_ZONE_CNTRL_REG_ZONE_MANUAL_CONTROL_MASK 0x00000080
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_PWR_ZONE_CNTRL_REG_ZONE_MANUAL_CONTROL_SHIFT 7
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_PWR_ZONE_CNTRL_REG_ZONE_MANUAL_CONTROL_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: L2BIU_PWR_ZONE_CNTRL_REG :: ZONE_MAN_ISO_CNTL [06:06] */
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_PWR_ZONE_CNTRL_REG_ZONE_MAN_ISO_CNTL_MASK 0x00000040
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_PWR_ZONE_CNTRL_REG_ZONE_MAN_ISO_CNTL_SHIFT 6
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_PWR_ZONE_CNTRL_REG_ZONE_MAN_ISO_CNTL_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: L2BIU_PWR_ZONE_CNTRL_REG :: reserved1 [05:05] */
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_PWR_ZONE_CNTRL_REG_reserved1_MASK 0x00000020
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_PWR_ZONE_CNTRL_REG_reserved1_SHIFT 5
-
-/* HIF_CPUBIUCTRL :: L2BIU_PWR_ZONE_CNTRL_REG :: ZONE_MAN_MEM_PWR [04:04] */
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_PWR_ZONE_CNTRL_REG_ZONE_MAN_MEM_PWR_MASK 0x00000010
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_PWR_ZONE_CNTRL_REG_ZONE_MAN_MEM_PWR_SHIFT 4
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_PWR_ZONE_CNTRL_REG_ZONE_MAN_MEM_PWR_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: L2BIU_PWR_ZONE_CNTRL_REG :: ZONE_DPG_CAPABLE [03:03] */
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_PWR_ZONE_CNTRL_REG_ZONE_DPG_CAPABLE_MASK 0x00000008
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_PWR_ZONE_CNTRL_REG_ZONE_DPG_CAPABLE_SHIFT 3
-
-/* HIF_CPUBIUCTRL :: L2BIU_PWR_ZONE_CNTRL_REG :: ZONE_FREQ_SCALE_USED [02:02] */
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_PWR_ZONE_CNTRL_REG_ZONE_FREQ_SCALE_USED_MASK 0x00000004
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_PWR_ZONE_CNTRL_REG_ZONE_FREQ_SCALE_USED_SHIFT 2
-
-/* HIF_CPUBIUCTRL :: L2BIU_PWR_ZONE_CNTRL_REG :: ZONE_MAN_RESET_CNTL [01:01] */
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_PWR_ZONE_CNTRL_REG_ZONE_MAN_RESET_CNTL_MASK 0x00000002
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_PWR_ZONE_CNTRL_REG_ZONE_MAN_RESET_CNTL_SHIFT 1
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_PWR_ZONE_CNTRL_REG_ZONE_MAN_RESET_CNTL_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: L2BIU_PWR_ZONE_CNTRL_REG :: ZONE_MAN_CLKEN [00:00] */
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_PWR_ZONE_CNTRL_REG_ZONE_MAN_CLKEN_MASK 0x00000001
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_PWR_ZONE_CNTRL_REG_ZONE_MAN_CLKEN_SHIFT 0
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_PWR_ZONE_CNTRL_REG_ZONE_MAN_CLKEN_DEFAULT 0x00000000
-
-/***************************************************************************
- *CPU0_PWR_ZONE_CONFIG1_REG - CPU0 Power Zone Config1 Registers
- ***************************************************************************/
-/* HIF_CPUBIUCTRL :: CPU0_PWR_ZONE_CONFIG1_REG :: RST_OFF_DLY [31:28] */
-#define BCHP_HIF_CPUBIUCTRL_CPU0_PWR_ZONE_CONFIG1_REG_RST_OFF_DLY_MASK 0xf0000000
-#define BCHP_HIF_CPUBIUCTRL_CPU0_PWR_ZONE_CONFIG1_REG_RST_OFF_DLY_SHIFT 28
-#define BCHP_HIF_CPUBIUCTRL_CPU0_PWR_ZONE_CONFIG1_REG_RST_OFF_DLY_DEFAULT 0x00000004
-
-/* HIF_CPUBIUCTRL :: CPU0_PWR_ZONE_CONFIG1_REG :: RST_ON_DLY [27:24] */
-#define BCHP_HIF_CPUBIUCTRL_CPU0_PWR_ZONE_CONFIG1_REG_RST_ON_DLY_MASK 0x0f000000
-#define BCHP_HIF_CPUBIUCTRL_CPU0_PWR_ZONE_CONFIG1_REG_RST_ON_DLY_SHIFT 24
-#define BCHP_HIF_CPUBIUCTRL_CPU0_PWR_ZONE_CONFIG1_REG_RST_ON_DLY_DEFAULT 0x00000004
-
-/* HIF_CPUBIUCTRL :: CPU0_PWR_ZONE_CONFIG1_REG :: CLK_OFF_DLY [23:20] */
-#define BCHP_HIF_CPUBIUCTRL_CPU0_PWR_ZONE_CONFIG1_REG_CLK_OFF_DLY_MASK 0x00f00000
-#define BCHP_HIF_CPUBIUCTRL_CPU0_PWR_ZONE_CONFIG1_REG_CLK_OFF_DLY_SHIFT 20
-#define BCHP_HIF_CPUBIUCTRL_CPU0_PWR_ZONE_CONFIG1_REG_CLK_OFF_DLY_DEFAULT 0x00000004
-
-/* HIF_CPUBIUCTRL :: CPU0_PWR_ZONE_CONFIG1_REG :: CLK_ON_DLY [19:16] */
-#define BCHP_HIF_CPUBIUCTRL_CPU0_PWR_ZONE_CONFIG1_REG_CLK_ON_DLY_MASK 0x000f0000
-#define BCHP_HIF_CPUBIUCTRL_CPU0_PWR_ZONE_CONFIG1_REG_CLK_ON_DLY_SHIFT 16
-#define BCHP_HIF_CPUBIUCTRL_CPU0_PWR_ZONE_CONFIG1_REG_CLK_ON_DLY_DEFAULT 0x00000004
-
-/* HIF_CPUBIUCTRL :: CPU0_PWR_ZONE_CONFIG1_REG :: ISO_OFF_DLY [15:12] */
-#define BCHP_HIF_CPUBIUCTRL_CPU0_PWR_ZONE_CONFIG1_REG_ISO_OFF_DLY_MASK 0x0000f000
-#define BCHP_HIF_CPUBIUCTRL_CPU0_PWR_ZONE_CONFIG1_REG_ISO_OFF_DLY_SHIFT 12
-#define BCHP_HIF_CPUBIUCTRL_CPU0_PWR_ZONE_CONFIG1_REG_ISO_OFF_DLY_DEFAULT 0x00000004
-
-/* HIF_CPUBIUCTRL :: CPU0_PWR_ZONE_CONFIG1_REG :: ISO_ON_DLY [11:08] */
-#define BCHP_HIF_CPUBIUCTRL_CPU0_PWR_ZONE_CONFIG1_REG_ISO_ON_DLY_MASK 0x00000f00
-#define BCHP_HIF_CPUBIUCTRL_CPU0_PWR_ZONE_CONFIG1_REG_ISO_ON_DLY_SHIFT 8
-#define BCHP_HIF_CPUBIUCTRL_CPU0_PWR_ZONE_CONFIG1_REG_ISO_ON_DLY_DEFAULT 0x00000004
-
-/* HIF_CPUBIUCTRL :: CPU0_PWR_ZONE_CONFIG1_REG :: reserved0 [07:05] */
-#define BCHP_HIF_CPUBIUCTRL_CPU0_PWR_ZONE_CONFIG1_REG_reserved0_MASK 0x000000e0
-#define BCHP_HIF_CPUBIUCTRL_CPU0_PWR_ZONE_CONFIG1_REG_reserved0_SHIFT 5
-
-/* HIF_CPUBIUCTRL :: CPU0_PWR_ZONE_CONFIG1_REG :: PWROK_TRESH [04:03] */
-#define BCHP_HIF_CPUBIUCTRL_CPU0_PWR_ZONE_CONFIG1_REG_PWROK_TRESH_MASK 0x00000018
-#define BCHP_HIF_CPUBIUCTRL_CPU0_PWR_ZONE_CONFIG1_REG_PWROK_TRESH_SHIFT 3
-#define BCHP_HIF_CPUBIUCTRL_CPU0_PWR_ZONE_CONFIG1_REG_PWROK_TRESH_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: CPU0_PWR_ZONE_CONFIG1_REG :: PWROK_DELAY_SEL [02:00] */
-#define BCHP_HIF_CPUBIUCTRL_CPU0_PWR_ZONE_CONFIG1_REG_PWROK_DELAY_SEL_MASK 0x00000007
-#define BCHP_HIF_CPUBIUCTRL_CPU0_PWR_ZONE_CONFIG1_REG_PWROK_DELAY_SEL_SHIFT 0
-#define BCHP_HIF_CPUBIUCTRL_CPU0_PWR_ZONE_CONFIG1_REG_PWROK_DELAY_SEL_DEFAULT 0x00000000
-
-/***************************************************************************
- *CPU0_PWR_ZONE_CONFIG2_REG - CPU0 Power Zone Config2 Registers
- ***************************************************************************/
-/* HIF_CPUBIUCTRL :: CPU0_PWR_ZONE_CONFIG2_REG :: MEM_OFF_DLY [31:28] */
-#define BCHP_HIF_CPUBIUCTRL_CPU0_PWR_ZONE_CONFIG2_REG_MEM_OFF_DLY_MASK 0xf0000000
-#define BCHP_HIF_CPUBIUCTRL_CPU0_PWR_ZONE_CONFIG2_REG_MEM_OFF_DLY_SHIFT 28
-#define BCHP_HIF_CPUBIUCTRL_CPU0_PWR_ZONE_CONFIG2_REG_MEM_OFF_DLY_DEFAULT 0x00000004
-
-/* HIF_CPUBIUCTRL :: CPU0_PWR_ZONE_CONFIG2_REG :: MEM_ON_DLY [27:24] */
-#define BCHP_HIF_CPUBIUCTRL_CPU0_PWR_ZONE_CONFIG2_REG_MEM_ON_DLY_MASK 0x0f000000
-#define BCHP_HIF_CPUBIUCTRL_CPU0_PWR_ZONE_CONFIG2_REG_MEM_ON_DLY_SHIFT 24
-#define BCHP_HIF_CPUBIUCTRL_CPU0_PWR_ZONE_CONFIG2_REG_MEM_ON_DLY_DEFAULT 0x00000004
-
-/* HIF_CPUBIUCTRL :: CPU0_PWR_ZONE_CONFIG2_REG :: DPG_OFF_DLY [23:20] */
-#define BCHP_HIF_CPUBIUCTRL_CPU0_PWR_ZONE_CONFIG2_REG_DPG_OFF_DLY_MASK 0x00f00000
-#define BCHP_HIF_CPUBIUCTRL_CPU0_PWR_ZONE_CONFIG2_REG_DPG_OFF_DLY_SHIFT 20
-#define BCHP_HIF_CPUBIUCTRL_CPU0_PWR_ZONE_CONFIG2_REG_DPG_OFF_DLY_DEFAULT 0x00000004
-
-/* HIF_CPUBIUCTRL :: CPU0_PWR_ZONE_CONFIG2_REG :: DPG1_ON_DLY [19:16] */
-#define BCHP_HIF_CPUBIUCTRL_CPU0_PWR_ZONE_CONFIG2_REG_DPG1_ON_DLY_MASK 0x000f0000
-#define BCHP_HIF_CPUBIUCTRL_CPU0_PWR_ZONE_CONFIG2_REG_DPG1_ON_DLY_SHIFT 16
-#define BCHP_HIF_CPUBIUCTRL_CPU0_PWR_ZONE_CONFIG2_REG_DPG1_ON_DLY_DEFAULT 0x00000003
-
-/* HIF_CPUBIUCTRL :: CPU0_PWR_ZONE_CONFIG2_REG :: DPGN_ON_DLY [15:12] */
-#define BCHP_HIF_CPUBIUCTRL_CPU0_PWR_ZONE_CONFIG2_REG_DPGN_ON_DLY_MASK 0x0000f000
-#define BCHP_HIF_CPUBIUCTRL_CPU0_PWR_ZONE_CONFIG2_REG_DPGN_ON_DLY_SHIFT 12
-#define BCHP_HIF_CPUBIUCTRL_CPU0_PWR_ZONE_CONFIG2_REG_DPGN_ON_DLY_DEFAULT 0x00000001
-
-/* HIF_CPUBIUCTRL :: CPU0_PWR_ZONE_CONFIG2_REG :: reserved0 [11:06] */
-#define BCHP_HIF_CPUBIUCTRL_CPU0_PWR_ZONE_CONFIG2_REG_reserved0_MASK 0x00000fc0
-#define BCHP_HIF_CPUBIUCTRL_CPU0_PWR_ZONE_CONFIG2_REG_reserved0_SHIFT 6
-
-/* HIF_CPUBIUCTRL :: CPU0_PWR_ZONE_CONFIG2_REG :: SLEW_PRESCALE_SEL [05:03] */
-#define BCHP_HIF_CPUBIUCTRL_CPU0_PWR_ZONE_CONFIG2_REG_SLEW_PRESCALE_SEL_MASK 0x00000038
-#define BCHP_HIF_CPUBIUCTRL_CPU0_PWR_ZONE_CONFIG2_REG_SLEW_PRESCALE_SEL_SHIFT 3
-#define BCHP_HIF_CPUBIUCTRL_CPU0_PWR_ZONE_CONFIG2_REG_SLEW_PRESCALE_SEL_DEFAULT 0x00000002
-
-/* HIF_CPUBIUCTRL :: CPU0_PWR_ZONE_CONFIG2_REG :: DELAY_PRESCALE_SEL [02:00] */
-#define BCHP_HIF_CPUBIUCTRL_CPU0_PWR_ZONE_CONFIG2_REG_DELAY_PRESCALE_SEL_MASK 0x00000007
-#define BCHP_HIF_CPUBIUCTRL_CPU0_PWR_ZONE_CONFIG2_REG_DELAY_PRESCALE_SEL_SHIFT 0
-#define BCHP_HIF_CPUBIUCTRL_CPU0_PWR_ZONE_CONFIG2_REG_DELAY_PRESCALE_SEL_DEFAULT 0x00000002
-
-/***************************************************************************
- *CPU1_PWR_ZONE_CONFIG1_REG - CPU1 Power Zone Config1 Registers
- ***************************************************************************/
-/* HIF_CPUBIUCTRL :: CPU1_PWR_ZONE_CONFIG1_REG :: RST_OFF_DLY [31:28] */
-#define BCHP_HIF_CPUBIUCTRL_CPU1_PWR_ZONE_CONFIG1_REG_RST_OFF_DLY_MASK 0xf0000000
-#define BCHP_HIF_CPUBIUCTRL_CPU1_PWR_ZONE_CONFIG1_REG_RST_OFF_DLY_SHIFT 28
-#define BCHP_HIF_CPUBIUCTRL_CPU1_PWR_ZONE_CONFIG1_REG_RST_OFF_DLY_DEFAULT 0x00000004
-
-/* HIF_CPUBIUCTRL :: CPU1_PWR_ZONE_CONFIG1_REG :: RST_ON_DLY [27:24] */
-#define BCHP_HIF_CPUBIUCTRL_CPU1_PWR_ZONE_CONFIG1_REG_RST_ON_DLY_MASK 0x0f000000
-#define BCHP_HIF_CPUBIUCTRL_CPU1_PWR_ZONE_CONFIG1_REG_RST_ON_DLY_SHIFT 24
-#define BCHP_HIF_CPUBIUCTRL_CPU1_PWR_ZONE_CONFIG1_REG_RST_ON_DLY_DEFAULT 0x00000004
-
-/* HIF_CPUBIUCTRL :: CPU1_PWR_ZONE_CONFIG1_REG :: CLK_OFF_DLY [23:20] */
-#define BCHP_HIF_CPUBIUCTRL_CPU1_PWR_ZONE_CONFIG1_REG_CLK_OFF_DLY_MASK 0x00f00000
-#define BCHP_HIF_CPUBIUCTRL_CPU1_PWR_ZONE_CONFIG1_REG_CLK_OFF_DLY_SHIFT 20
-#define BCHP_HIF_CPUBIUCTRL_CPU1_PWR_ZONE_CONFIG1_REG_CLK_OFF_DLY_DEFAULT 0x00000004
-
-/* HIF_CPUBIUCTRL :: CPU1_PWR_ZONE_CONFIG1_REG :: CLK_ON_DLY [19:16] */
-#define BCHP_HIF_CPUBIUCTRL_CPU1_PWR_ZONE_CONFIG1_REG_CLK_ON_DLY_MASK 0x000f0000
-#define BCHP_HIF_CPUBIUCTRL_CPU1_PWR_ZONE_CONFIG1_REG_CLK_ON_DLY_SHIFT 16
-#define BCHP_HIF_CPUBIUCTRL_CPU1_PWR_ZONE_CONFIG1_REG_CLK_ON_DLY_DEFAULT 0x00000004
-
-/* HIF_CPUBIUCTRL :: CPU1_PWR_ZONE_CONFIG1_REG :: ISO_OFF_DLY [15:12] */
-#define BCHP_HIF_CPUBIUCTRL_CPU1_PWR_ZONE_CONFIG1_REG_ISO_OFF_DLY_MASK 0x0000f000
-#define BCHP_HIF_CPUBIUCTRL_CPU1_PWR_ZONE_CONFIG1_REG_ISO_OFF_DLY_SHIFT 12
-#define BCHP_HIF_CPUBIUCTRL_CPU1_PWR_ZONE_CONFIG1_REG_ISO_OFF_DLY_DEFAULT 0x00000004
-
-/* HIF_CPUBIUCTRL :: CPU1_PWR_ZONE_CONFIG1_REG :: ISO_ON_DLY [11:08] */
-#define BCHP_HIF_CPUBIUCTRL_CPU1_PWR_ZONE_CONFIG1_REG_ISO_ON_DLY_MASK 0x00000f00
-#define BCHP_HIF_CPUBIUCTRL_CPU1_PWR_ZONE_CONFIG1_REG_ISO_ON_DLY_SHIFT 8
-#define BCHP_HIF_CPUBIUCTRL_CPU1_PWR_ZONE_CONFIG1_REG_ISO_ON_DLY_DEFAULT 0x00000004
-
-/* HIF_CPUBIUCTRL :: CPU1_PWR_ZONE_CONFIG1_REG :: reserved0 [07:05] */
-#define BCHP_HIF_CPUBIUCTRL_CPU1_PWR_ZONE_CONFIG1_REG_reserved0_MASK 0x000000e0
-#define BCHP_HIF_CPUBIUCTRL_CPU1_PWR_ZONE_CONFIG1_REG_reserved0_SHIFT 5
-
-/* HIF_CPUBIUCTRL :: CPU1_PWR_ZONE_CONFIG1_REG :: PWROK_TRESH [04:03] */
-#define BCHP_HIF_CPUBIUCTRL_CPU1_PWR_ZONE_CONFIG1_REG_PWROK_TRESH_MASK 0x00000018
-#define BCHP_HIF_CPUBIUCTRL_CPU1_PWR_ZONE_CONFIG1_REG_PWROK_TRESH_SHIFT 3
-#define BCHP_HIF_CPUBIUCTRL_CPU1_PWR_ZONE_CONFIG1_REG_PWROK_TRESH_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: CPU1_PWR_ZONE_CONFIG1_REG :: PWROK_DELAY_SEL [02:00] */
-#define BCHP_HIF_CPUBIUCTRL_CPU1_PWR_ZONE_CONFIG1_REG_PWROK_DELAY_SEL_MASK 0x00000007
-#define BCHP_HIF_CPUBIUCTRL_CPU1_PWR_ZONE_CONFIG1_REG_PWROK_DELAY_SEL_SHIFT 0
-#define BCHP_HIF_CPUBIUCTRL_CPU1_PWR_ZONE_CONFIG1_REG_PWROK_DELAY_SEL_DEFAULT 0x00000000
-
-/***************************************************************************
- *CPU1_PWR_ZONE_CONFIG2_REG - CPU1 Power Zone Config2 Registers
- ***************************************************************************/
-/* HIF_CPUBIUCTRL :: CPU1_PWR_ZONE_CONFIG2_REG :: MEM_OFF_DLY [31:28] */
-#define BCHP_HIF_CPUBIUCTRL_CPU1_PWR_ZONE_CONFIG2_REG_MEM_OFF_DLY_MASK 0xf0000000
-#define BCHP_HIF_CPUBIUCTRL_CPU1_PWR_ZONE_CONFIG2_REG_MEM_OFF_DLY_SHIFT 28
-#define BCHP_HIF_CPUBIUCTRL_CPU1_PWR_ZONE_CONFIG2_REG_MEM_OFF_DLY_DEFAULT 0x00000004
-
-/* HIF_CPUBIUCTRL :: CPU1_PWR_ZONE_CONFIG2_REG :: MEM_ON_DLY [27:24] */
-#define BCHP_HIF_CPUBIUCTRL_CPU1_PWR_ZONE_CONFIG2_REG_MEM_ON_DLY_MASK 0x0f000000
-#define BCHP_HIF_CPUBIUCTRL_CPU1_PWR_ZONE_CONFIG2_REG_MEM_ON_DLY_SHIFT 24
-#define BCHP_HIF_CPUBIUCTRL_CPU1_PWR_ZONE_CONFIG2_REG_MEM_ON_DLY_DEFAULT 0x00000004
-
-/* HIF_CPUBIUCTRL :: CPU1_PWR_ZONE_CONFIG2_REG :: DPG_OFF_DLY [23:20] */
-#define BCHP_HIF_CPUBIUCTRL_CPU1_PWR_ZONE_CONFIG2_REG_DPG_OFF_DLY_MASK 0x00f00000
-#define BCHP_HIF_CPUBIUCTRL_CPU1_PWR_ZONE_CONFIG2_REG_DPG_OFF_DLY_SHIFT 20
-#define BCHP_HIF_CPUBIUCTRL_CPU1_PWR_ZONE_CONFIG2_REG_DPG_OFF_DLY_DEFAULT 0x00000004
-
-/* HIF_CPUBIUCTRL :: CPU1_PWR_ZONE_CONFIG2_REG :: DPG1_ON_DLY [19:16] */
-#define BCHP_HIF_CPUBIUCTRL_CPU1_PWR_ZONE_CONFIG2_REG_DPG1_ON_DLY_MASK 0x000f0000
-#define BCHP_HIF_CPUBIUCTRL_CPU1_PWR_ZONE_CONFIG2_REG_DPG1_ON_DLY_SHIFT 16
-#define BCHP_HIF_CPUBIUCTRL_CPU1_PWR_ZONE_CONFIG2_REG_DPG1_ON_DLY_DEFAULT 0x00000003
-
-/* HIF_CPUBIUCTRL :: CPU1_PWR_ZONE_CONFIG2_REG :: DPGN_ON_DLY [15:12] */
-#define BCHP_HIF_CPUBIUCTRL_CPU1_PWR_ZONE_CONFIG2_REG_DPGN_ON_DLY_MASK 0x0000f000
-#define BCHP_HIF_CPUBIUCTRL_CPU1_PWR_ZONE_CONFIG2_REG_DPGN_ON_DLY_SHIFT 12
-#define BCHP_HIF_CPUBIUCTRL_CPU1_PWR_ZONE_CONFIG2_REG_DPGN_ON_DLY_DEFAULT 0x00000001
-
-/* HIF_CPUBIUCTRL :: CPU1_PWR_ZONE_CONFIG2_REG :: reserved0 [11:06] */
-#define BCHP_HIF_CPUBIUCTRL_CPU1_PWR_ZONE_CONFIG2_REG_reserved0_MASK 0x00000fc0
-#define BCHP_HIF_CPUBIUCTRL_CPU1_PWR_ZONE_CONFIG2_REG_reserved0_SHIFT 6
-
-/* HIF_CPUBIUCTRL :: CPU1_PWR_ZONE_CONFIG2_REG :: SLEW_PRESCALE_SEL [05:03] */
-#define BCHP_HIF_CPUBIUCTRL_CPU1_PWR_ZONE_CONFIG2_REG_SLEW_PRESCALE_SEL_MASK 0x00000038
-#define BCHP_HIF_CPUBIUCTRL_CPU1_PWR_ZONE_CONFIG2_REG_SLEW_PRESCALE_SEL_SHIFT 3
-#define BCHP_HIF_CPUBIUCTRL_CPU1_PWR_ZONE_CONFIG2_REG_SLEW_PRESCALE_SEL_DEFAULT 0x00000002
-
-/* HIF_CPUBIUCTRL :: CPU1_PWR_ZONE_CONFIG2_REG :: DELAY_PRESCALE_SEL [02:00] */
-#define BCHP_HIF_CPUBIUCTRL_CPU1_PWR_ZONE_CONFIG2_REG_DELAY_PRESCALE_SEL_MASK 0x00000007
-#define BCHP_HIF_CPUBIUCTRL_CPU1_PWR_ZONE_CONFIG2_REG_DELAY_PRESCALE_SEL_SHIFT 0
-#define BCHP_HIF_CPUBIUCTRL_CPU1_PWR_ZONE_CONFIG2_REG_DELAY_PRESCALE_SEL_DEFAULT 0x00000002
-
-/***************************************************************************
- *CPU2_PWR_ZONE_CONFIG1_REG - CPU2 Power Zone Config1 Registers
- ***************************************************************************/
-/* HIF_CPUBIUCTRL :: CPU2_PWR_ZONE_CONFIG1_REG :: RST_OFF_DLY [31:28] */
-#define BCHP_HIF_CPUBIUCTRL_CPU2_PWR_ZONE_CONFIG1_REG_RST_OFF_DLY_MASK 0xf0000000
-#define BCHP_HIF_CPUBIUCTRL_CPU2_PWR_ZONE_CONFIG1_REG_RST_OFF_DLY_SHIFT 28
-#define BCHP_HIF_CPUBIUCTRL_CPU2_PWR_ZONE_CONFIG1_REG_RST_OFF_DLY_DEFAULT 0x00000004
-
-/* HIF_CPUBIUCTRL :: CPU2_PWR_ZONE_CONFIG1_REG :: RST_ON_DLY [27:24] */
-#define BCHP_HIF_CPUBIUCTRL_CPU2_PWR_ZONE_CONFIG1_REG_RST_ON_DLY_MASK 0x0f000000
-#define BCHP_HIF_CPUBIUCTRL_CPU2_PWR_ZONE_CONFIG1_REG_RST_ON_DLY_SHIFT 24
-#define BCHP_HIF_CPUBIUCTRL_CPU2_PWR_ZONE_CONFIG1_REG_RST_ON_DLY_DEFAULT 0x00000004
-
-/* HIF_CPUBIUCTRL :: CPU2_PWR_ZONE_CONFIG1_REG :: CLK_OFF_DLY [23:20] */
-#define BCHP_HIF_CPUBIUCTRL_CPU2_PWR_ZONE_CONFIG1_REG_CLK_OFF_DLY_MASK 0x00f00000
-#define BCHP_HIF_CPUBIUCTRL_CPU2_PWR_ZONE_CONFIG1_REG_CLK_OFF_DLY_SHIFT 20
-#define BCHP_HIF_CPUBIUCTRL_CPU2_PWR_ZONE_CONFIG1_REG_CLK_OFF_DLY_DEFAULT 0x00000004
-
-/* HIF_CPUBIUCTRL :: CPU2_PWR_ZONE_CONFIG1_REG :: CLK_ON_DLY [19:16] */
-#define BCHP_HIF_CPUBIUCTRL_CPU2_PWR_ZONE_CONFIG1_REG_CLK_ON_DLY_MASK 0x000f0000
-#define BCHP_HIF_CPUBIUCTRL_CPU2_PWR_ZONE_CONFIG1_REG_CLK_ON_DLY_SHIFT 16
-#define BCHP_HIF_CPUBIUCTRL_CPU2_PWR_ZONE_CONFIG1_REG_CLK_ON_DLY_DEFAULT 0x00000004
-
-/* HIF_CPUBIUCTRL :: CPU2_PWR_ZONE_CONFIG1_REG :: ISO_OFF_DLY [15:12] */
-#define BCHP_HIF_CPUBIUCTRL_CPU2_PWR_ZONE_CONFIG1_REG_ISO_OFF_DLY_MASK 0x0000f000
-#define BCHP_HIF_CPUBIUCTRL_CPU2_PWR_ZONE_CONFIG1_REG_ISO_OFF_DLY_SHIFT 12
-#define BCHP_HIF_CPUBIUCTRL_CPU2_PWR_ZONE_CONFIG1_REG_ISO_OFF_DLY_DEFAULT 0x00000004
-
-/* HIF_CPUBIUCTRL :: CPU2_PWR_ZONE_CONFIG1_REG :: ISO_ON_DLY [11:08] */
-#define BCHP_HIF_CPUBIUCTRL_CPU2_PWR_ZONE_CONFIG1_REG_ISO_ON_DLY_MASK 0x00000f00
-#define BCHP_HIF_CPUBIUCTRL_CPU2_PWR_ZONE_CONFIG1_REG_ISO_ON_DLY_SHIFT 8
-#define BCHP_HIF_CPUBIUCTRL_CPU2_PWR_ZONE_CONFIG1_REG_ISO_ON_DLY_DEFAULT 0x00000004
-
-/* HIF_CPUBIUCTRL :: CPU2_PWR_ZONE_CONFIG1_REG :: reserved0 [07:05] */
-#define BCHP_HIF_CPUBIUCTRL_CPU2_PWR_ZONE_CONFIG1_REG_reserved0_MASK 0x000000e0
-#define BCHP_HIF_CPUBIUCTRL_CPU2_PWR_ZONE_CONFIG1_REG_reserved0_SHIFT 5
-
-/* HIF_CPUBIUCTRL :: CPU2_PWR_ZONE_CONFIG1_REG :: PWROK_TRESH [04:03] */
-#define BCHP_HIF_CPUBIUCTRL_CPU2_PWR_ZONE_CONFIG1_REG_PWROK_TRESH_MASK 0x00000018
-#define BCHP_HIF_CPUBIUCTRL_CPU2_PWR_ZONE_CONFIG1_REG_PWROK_TRESH_SHIFT 3
-#define BCHP_HIF_CPUBIUCTRL_CPU2_PWR_ZONE_CONFIG1_REG_PWROK_TRESH_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: CPU2_PWR_ZONE_CONFIG1_REG :: PWROK_DELAY_SEL [02:00] */
-#define BCHP_HIF_CPUBIUCTRL_CPU2_PWR_ZONE_CONFIG1_REG_PWROK_DELAY_SEL_MASK 0x00000007
-#define BCHP_HIF_CPUBIUCTRL_CPU2_PWR_ZONE_CONFIG1_REG_PWROK_DELAY_SEL_SHIFT 0
-#define BCHP_HIF_CPUBIUCTRL_CPU2_PWR_ZONE_CONFIG1_REG_PWROK_DELAY_SEL_DEFAULT 0x00000000
-
-/***************************************************************************
- *CPU2_PWR_ZONE_CONFIG2_REG - CPU2 Power Zone Config2 Registers
- ***************************************************************************/
-/* HIF_CPUBIUCTRL :: CPU2_PWR_ZONE_CONFIG2_REG :: MEM_OFF_DLY [31:28] */
-#define BCHP_HIF_CPUBIUCTRL_CPU2_PWR_ZONE_CONFIG2_REG_MEM_OFF_DLY_MASK 0xf0000000
-#define BCHP_HIF_CPUBIUCTRL_CPU2_PWR_ZONE_CONFIG2_REG_MEM_OFF_DLY_SHIFT 28
-#define BCHP_HIF_CPUBIUCTRL_CPU2_PWR_ZONE_CONFIG2_REG_MEM_OFF_DLY_DEFAULT 0x00000004
-
-/* HIF_CPUBIUCTRL :: CPU2_PWR_ZONE_CONFIG2_REG :: MEM_ON_DLY [27:24] */
-#define BCHP_HIF_CPUBIUCTRL_CPU2_PWR_ZONE_CONFIG2_REG_MEM_ON_DLY_MASK 0x0f000000
-#define BCHP_HIF_CPUBIUCTRL_CPU2_PWR_ZONE_CONFIG2_REG_MEM_ON_DLY_SHIFT 24
-#define BCHP_HIF_CPUBIUCTRL_CPU2_PWR_ZONE_CONFIG2_REG_MEM_ON_DLY_DEFAULT 0x00000004
-
-/* HIF_CPUBIUCTRL :: CPU2_PWR_ZONE_CONFIG2_REG :: DPG_OFF_DLY [23:20] */
-#define BCHP_HIF_CPUBIUCTRL_CPU2_PWR_ZONE_CONFIG2_REG_DPG_OFF_DLY_MASK 0x00f00000
-#define BCHP_HIF_CPUBIUCTRL_CPU2_PWR_ZONE_CONFIG2_REG_DPG_OFF_DLY_SHIFT 20
-#define BCHP_HIF_CPUBIUCTRL_CPU2_PWR_ZONE_CONFIG2_REG_DPG_OFF_DLY_DEFAULT 0x00000004
-
-/* HIF_CPUBIUCTRL :: CPU2_PWR_ZONE_CONFIG2_REG :: DPG1_ON_DLY [19:16] */
-#define BCHP_HIF_CPUBIUCTRL_CPU2_PWR_ZONE_CONFIG2_REG_DPG1_ON_DLY_MASK 0x000f0000
-#define BCHP_HIF_CPUBIUCTRL_CPU2_PWR_ZONE_CONFIG2_REG_DPG1_ON_DLY_SHIFT 16
-#define BCHP_HIF_CPUBIUCTRL_CPU2_PWR_ZONE_CONFIG2_REG_DPG1_ON_DLY_DEFAULT 0x00000003
-
-/* HIF_CPUBIUCTRL :: CPU2_PWR_ZONE_CONFIG2_REG :: DPGN_ON_DLY [15:12] */
-#define BCHP_HIF_CPUBIUCTRL_CPU2_PWR_ZONE_CONFIG2_REG_DPGN_ON_DLY_MASK 0x0000f000
-#define BCHP_HIF_CPUBIUCTRL_CPU2_PWR_ZONE_CONFIG2_REG_DPGN_ON_DLY_SHIFT 12
-#define BCHP_HIF_CPUBIUCTRL_CPU2_PWR_ZONE_CONFIG2_REG_DPGN_ON_DLY_DEFAULT 0x00000001
-
-/* HIF_CPUBIUCTRL :: CPU2_PWR_ZONE_CONFIG2_REG :: reserved0 [11:06] */
-#define BCHP_HIF_CPUBIUCTRL_CPU2_PWR_ZONE_CONFIG2_REG_reserved0_MASK 0x00000fc0
-#define BCHP_HIF_CPUBIUCTRL_CPU2_PWR_ZONE_CONFIG2_REG_reserved0_SHIFT 6
-
-/* HIF_CPUBIUCTRL :: CPU2_PWR_ZONE_CONFIG2_REG :: SLEW_PRESCALE_SEL [05:03] */
-#define BCHP_HIF_CPUBIUCTRL_CPU2_PWR_ZONE_CONFIG2_REG_SLEW_PRESCALE_SEL_MASK 0x00000038
-#define BCHP_HIF_CPUBIUCTRL_CPU2_PWR_ZONE_CONFIG2_REG_SLEW_PRESCALE_SEL_SHIFT 3
-#define BCHP_HIF_CPUBIUCTRL_CPU2_PWR_ZONE_CONFIG2_REG_SLEW_PRESCALE_SEL_DEFAULT 0x00000002
-
-/* HIF_CPUBIUCTRL :: CPU2_PWR_ZONE_CONFIG2_REG :: DELAY_PRESCALE_SEL [02:00] */
-#define BCHP_HIF_CPUBIUCTRL_CPU2_PWR_ZONE_CONFIG2_REG_DELAY_PRESCALE_SEL_MASK 0x00000007
-#define BCHP_HIF_CPUBIUCTRL_CPU2_PWR_ZONE_CONFIG2_REG_DELAY_PRESCALE_SEL_SHIFT 0
-#define BCHP_HIF_CPUBIUCTRL_CPU2_PWR_ZONE_CONFIG2_REG_DELAY_PRESCALE_SEL_DEFAULT 0x00000002
-
-/***************************************************************************
- *CPU3_PWR_ZONE_CONFIG1_REG - CPU3 Power Zone Config1 Registers
- ***************************************************************************/
-/* HIF_CPUBIUCTRL :: CPU3_PWR_ZONE_CONFIG1_REG :: RST_OFF_DLY [31:28] */
-#define BCHP_HIF_CPUBIUCTRL_CPU3_PWR_ZONE_CONFIG1_REG_RST_OFF_DLY_MASK 0xf0000000
-#define BCHP_HIF_CPUBIUCTRL_CPU3_PWR_ZONE_CONFIG1_REG_RST_OFF_DLY_SHIFT 28
-#define BCHP_HIF_CPUBIUCTRL_CPU3_PWR_ZONE_CONFIG1_REG_RST_OFF_DLY_DEFAULT 0x00000004
-
-/* HIF_CPUBIUCTRL :: CPU3_PWR_ZONE_CONFIG1_REG :: RST_ON_DLY [27:24] */
-#define BCHP_HIF_CPUBIUCTRL_CPU3_PWR_ZONE_CONFIG1_REG_RST_ON_DLY_MASK 0x0f000000
-#define BCHP_HIF_CPUBIUCTRL_CPU3_PWR_ZONE_CONFIG1_REG_RST_ON_DLY_SHIFT 24
-#define BCHP_HIF_CPUBIUCTRL_CPU3_PWR_ZONE_CONFIG1_REG_RST_ON_DLY_DEFAULT 0x00000004
-
-/* HIF_CPUBIUCTRL :: CPU3_PWR_ZONE_CONFIG1_REG :: CLK_OFF_DLY [23:20] */
-#define BCHP_HIF_CPUBIUCTRL_CPU3_PWR_ZONE_CONFIG1_REG_CLK_OFF_DLY_MASK 0x00f00000
-#define BCHP_HIF_CPUBIUCTRL_CPU3_PWR_ZONE_CONFIG1_REG_CLK_OFF_DLY_SHIFT 20
-#define BCHP_HIF_CPUBIUCTRL_CPU3_PWR_ZONE_CONFIG1_REG_CLK_OFF_DLY_DEFAULT 0x00000004
-
-/* HIF_CPUBIUCTRL :: CPU3_PWR_ZONE_CONFIG1_REG :: CLK_ON_DLY [19:16] */
-#define BCHP_HIF_CPUBIUCTRL_CPU3_PWR_ZONE_CONFIG1_REG_CLK_ON_DLY_MASK 0x000f0000
-#define BCHP_HIF_CPUBIUCTRL_CPU3_PWR_ZONE_CONFIG1_REG_CLK_ON_DLY_SHIFT 16
-#define BCHP_HIF_CPUBIUCTRL_CPU3_PWR_ZONE_CONFIG1_REG_CLK_ON_DLY_DEFAULT 0x00000004
-
-/* HIF_CPUBIUCTRL :: CPU3_PWR_ZONE_CONFIG1_REG :: ISO_OFF_DLY [15:12] */
-#define BCHP_HIF_CPUBIUCTRL_CPU3_PWR_ZONE_CONFIG1_REG_ISO_OFF_DLY_MASK 0x0000f000
-#define BCHP_HIF_CPUBIUCTRL_CPU3_PWR_ZONE_CONFIG1_REG_ISO_OFF_DLY_SHIFT 12
-#define BCHP_HIF_CPUBIUCTRL_CPU3_PWR_ZONE_CONFIG1_REG_ISO_OFF_DLY_DEFAULT 0x00000004
-
-/* HIF_CPUBIUCTRL :: CPU3_PWR_ZONE_CONFIG1_REG :: ISO_ON_DLY [11:08] */
-#define BCHP_HIF_CPUBIUCTRL_CPU3_PWR_ZONE_CONFIG1_REG_ISO_ON_DLY_MASK 0x00000f00
-#define BCHP_HIF_CPUBIUCTRL_CPU3_PWR_ZONE_CONFIG1_REG_ISO_ON_DLY_SHIFT 8
-#define BCHP_HIF_CPUBIUCTRL_CPU3_PWR_ZONE_CONFIG1_REG_ISO_ON_DLY_DEFAULT 0x00000004
-
-/* HIF_CPUBIUCTRL :: CPU3_PWR_ZONE_CONFIG1_REG :: reserved0 [07:05] */
-#define BCHP_HIF_CPUBIUCTRL_CPU3_PWR_ZONE_CONFIG1_REG_reserved0_MASK 0x000000e0
-#define BCHP_HIF_CPUBIUCTRL_CPU3_PWR_ZONE_CONFIG1_REG_reserved0_SHIFT 5
-
-/* HIF_CPUBIUCTRL :: CPU3_PWR_ZONE_CONFIG1_REG :: PWROK_TRESH [04:03] */
-#define BCHP_HIF_CPUBIUCTRL_CPU3_PWR_ZONE_CONFIG1_REG_PWROK_TRESH_MASK 0x00000018
-#define BCHP_HIF_CPUBIUCTRL_CPU3_PWR_ZONE_CONFIG1_REG_PWROK_TRESH_SHIFT 3
-#define BCHP_HIF_CPUBIUCTRL_CPU3_PWR_ZONE_CONFIG1_REG_PWROK_TRESH_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: CPU3_PWR_ZONE_CONFIG1_REG :: PWROK_DELAY_SEL [02:00] */
-#define BCHP_HIF_CPUBIUCTRL_CPU3_PWR_ZONE_CONFIG1_REG_PWROK_DELAY_SEL_MASK 0x00000007
-#define BCHP_HIF_CPUBIUCTRL_CPU3_PWR_ZONE_CONFIG1_REG_PWROK_DELAY_SEL_SHIFT 0
-#define BCHP_HIF_CPUBIUCTRL_CPU3_PWR_ZONE_CONFIG1_REG_PWROK_DELAY_SEL_DEFAULT 0x00000000
-
-/***************************************************************************
- *CPU3_PWR_ZONE_CONFIG2_REG - CPU3 Power Zone Config2 Registers
- ***************************************************************************/
-/* HIF_CPUBIUCTRL :: CPU3_PWR_ZONE_CONFIG2_REG :: MEM_OFF_DLY [31:28] */
-#define BCHP_HIF_CPUBIUCTRL_CPU3_PWR_ZONE_CONFIG2_REG_MEM_OFF_DLY_MASK 0xf0000000
-#define BCHP_HIF_CPUBIUCTRL_CPU3_PWR_ZONE_CONFIG2_REG_MEM_OFF_DLY_SHIFT 28
-#define BCHP_HIF_CPUBIUCTRL_CPU3_PWR_ZONE_CONFIG2_REG_MEM_OFF_DLY_DEFAULT 0x00000004
-
-/* HIF_CPUBIUCTRL :: CPU3_PWR_ZONE_CONFIG2_REG :: MEM_ON_DLY [27:24] */
-#define BCHP_HIF_CPUBIUCTRL_CPU3_PWR_ZONE_CONFIG2_REG_MEM_ON_DLY_MASK 0x0f000000
-#define BCHP_HIF_CPUBIUCTRL_CPU3_PWR_ZONE_CONFIG2_REG_MEM_ON_DLY_SHIFT 24
-#define BCHP_HIF_CPUBIUCTRL_CPU3_PWR_ZONE_CONFIG2_REG_MEM_ON_DLY_DEFAULT 0x00000004
-
-/* HIF_CPUBIUCTRL :: CPU3_PWR_ZONE_CONFIG2_REG :: DPG_OFF_DLY [23:20] */
-#define BCHP_HIF_CPUBIUCTRL_CPU3_PWR_ZONE_CONFIG2_REG_DPG_OFF_DLY_MASK 0x00f00000
-#define BCHP_HIF_CPUBIUCTRL_CPU3_PWR_ZONE_CONFIG2_REG_DPG_OFF_DLY_SHIFT 20
-#define BCHP_HIF_CPUBIUCTRL_CPU3_PWR_ZONE_CONFIG2_REG_DPG_OFF_DLY_DEFAULT 0x00000004
-
-/* HIF_CPUBIUCTRL :: CPU3_PWR_ZONE_CONFIG2_REG :: DPG1_ON_DLY [19:16] */
-#define BCHP_HIF_CPUBIUCTRL_CPU3_PWR_ZONE_CONFIG2_REG_DPG1_ON_DLY_MASK 0x000f0000
-#define BCHP_HIF_CPUBIUCTRL_CPU3_PWR_ZONE_CONFIG2_REG_DPG1_ON_DLY_SHIFT 16
-#define BCHP_HIF_CPUBIUCTRL_CPU3_PWR_ZONE_CONFIG2_REG_DPG1_ON_DLY_DEFAULT 0x00000003
-
-/* HIF_CPUBIUCTRL :: CPU3_PWR_ZONE_CONFIG2_REG :: DPGN_ON_DLY [15:12] */
-#define BCHP_HIF_CPUBIUCTRL_CPU3_PWR_ZONE_CONFIG2_REG_DPGN_ON_DLY_MASK 0x0000f000
-#define BCHP_HIF_CPUBIUCTRL_CPU3_PWR_ZONE_CONFIG2_REG_DPGN_ON_DLY_SHIFT 12
-#define BCHP_HIF_CPUBIUCTRL_CPU3_PWR_ZONE_CONFIG2_REG_DPGN_ON_DLY_DEFAULT 0x00000001
-
-/* HIF_CPUBIUCTRL :: CPU3_PWR_ZONE_CONFIG2_REG :: reserved0 [11:06] */
-#define BCHP_HIF_CPUBIUCTRL_CPU3_PWR_ZONE_CONFIG2_REG_reserved0_MASK 0x00000fc0
-#define BCHP_HIF_CPUBIUCTRL_CPU3_PWR_ZONE_CONFIG2_REG_reserved0_SHIFT 6
-
-/* HIF_CPUBIUCTRL :: CPU3_PWR_ZONE_CONFIG2_REG :: SLEW_PRESCALE_SEL [05:03] */
-#define BCHP_HIF_CPUBIUCTRL_CPU3_PWR_ZONE_CONFIG2_REG_SLEW_PRESCALE_SEL_MASK 0x00000038
-#define BCHP_HIF_CPUBIUCTRL_CPU3_PWR_ZONE_CONFIG2_REG_SLEW_PRESCALE_SEL_SHIFT 3
-#define BCHP_HIF_CPUBIUCTRL_CPU3_PWR_ZONE_CONFIG2_REG_SLEW_PRESCALE_SEL_DEFAULT 0x00000002
-
-/* HIF_CPUBIUCTRL :: CPU3_PWR_ZONE_CONFIG2_REG :: DELAY_PRESCALE_SEL [02:00] */
-#define BCHP_HIF_CPUBIUCTRL_CPU3_PWR_ZONE_CONFIG2_REG_DELAY_PRESCALE_SEL_MASK 0x00000007
-#define BCHP_HIF_CPUBIUCTRL_CPU3_PWR_ZONE_CONFIG2_REG_DELAY_PRESCALE_SEL_SHIFT 0
-#define BCHP_HIF_CPUBIUCTRL_CPU3_PWR_ZONE_CONFIG2_REG_DELAY_PRESCALE_SEL_DEFAULT 0x00000002
-
-/***************************************************************************
- *L2BIU_PWR_ZONE_CONFIG1_REG - L2/BIU Power Zone Config1 Registers
- ***************************************************************************/
-/* HIF_CPUBIUCTRL :: L2BIU_PWR_ZONE_CONFIG1_REG :: RST_OFF_DLY [31:28] */
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_PWR_ZONE_CONFIG1_REG_RST_OFF_DLY_MASK 0xf0000000
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_PWR_ZONE_CONFIG1_REG_RST_OFF_DLY_SHIFT 28
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_PWR_ZONE_CONFIG1_REG_RST_OFF_DLY_DEFAULT 0x00000004
-
-/* HIF_CPUBIUCTRL :: L2BIU_PWR_ZONE_CONFIG1_REG :: RST_ON_DLY [27:24] */
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_PWR_ZONE_CONFIG1_REG_RST_ON_DLY_MASK 0x0f000000
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_PWR_ZONE_CONFIG1_REG_RST_ON_DLY_SHIFT 24
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_PWR_ZONE_CONFIG1_REG_RST_ON_DLY_DEFAULT 0x00000004
-
-/* HIF_CPUBIUCTRL :: L2BIU_PWR_ZONE_CONFIG1_REG :: CLK_OFF_DLY [23:20] */
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_PWR_ZONE_CONFIG1_REG_CLK_OFF_DLY_MASK 0x00f00000
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_PWR_ZONE_CONFIG1_REG_CLK_OFF_DLY_SHIFT 20
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_PWR_ZONE_CONFIG1_REG_CLK_OFF_DLY_DEFAULT 0x00000004
-
-/* HIF_CPUBIUCTRL :: L2BIU_PWR_ZONE_CONFIG1_REG :: CLK_ON_DLY [19:16] */
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_PWR_ZONE_CONFIG1_REG_CLK_ON_DLY_MASK 0x000f0000
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_PWR_ZONE_CONFIG1_REG_CLK_ON_DLY_SHIFT 16
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_PWR_ZONE_CONFIG1_REG_CLK_ON_DLY_DEFAULT 0x00000004
-
-/* HIF_CPUBIUCTRL :: L2BIU_PWR_ZONE_CONFIG1_REG :: ISO_OFF_DLY [15:12] */
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_PWR_ZONE_CONFIG1_REG_ISO_OFF_DLY_MASK 0x0000f000
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_PWR_ZONE_CONFIG1_REG_ISO_OFF_DLY_SHIFT 12
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_PWR_ZONE_CONFIG1_REG_ISO_OFF_DLY_DEFAULT 0x00000004
-
-/* HIF_CPUBIUCTRL :: L2BIU_PWR_ZONE_CONFIG1_REG :: ISO_ON_DLY [11:08] */
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_PWR_ZONE_CONFIG1_REG_ISO_ON_DLY_MASK 0x00000f00
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_PWR_ZONE_CONFIG1_REG_ISO_ON_DLY_SHIFT 8
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_PWR_ZONE_CONFIG1_REG_ISO_ON_DLY_DEFAULT 0x00000004
-
-/* HIF_CPUBIUCTRL :: L2BIU_PWR_ZONE_CONFIG1_REG :: reserved0 [07:05] */
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_PWR_ZONE_CONFIG1_REG_reserved0_MASK 0x000000e0
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_PWR_ZONE_CONFIG1_REG_reserved0_SHIFT 5
-
-/* HIF_CPUBIUCTRL :: L2BIU_PWR_ZONE_CONFIG1_REG :: PWROK_TRESH [04:03] */
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_PWR_ZONE_CONFIG1_REG_PWROK_TRESH_MASK 0x00000018
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_PWR_ZONE_CONFIG1_REG_PWROK_TRESH_SHIFT 3
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_PWR_ZONE_CONFIG1_REG_PWROK_TRESH_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: L2BIU_PWR_ZONE_CONFIG1_REG :: PWROK_DELAY_SEL [02:00] */
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_PWR_ZONE_CONFIG1_REG_PWROK_DELAY_SEL_MASK 0x00000007
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_PWR_ZONE_CONFIG1_REG_PWROK_DELAY_SEL_SHIFT 0
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_PWR_ZONE_CONFIG1_REG_PWROK_DELAY_SEL_DEFAULT 0x00000000
-
-/***************************************************************************
- *L2BIU_PWR_ZONE_CONFIG2_REG - L2/BIU Power Zone Config2 Registers
- ***************************************************************************/
-/* HIF_CPUBIUCTRL :: L2BIU_PWR_ZONE_CONFIG2_REG :: MEM_OFF_DLY [31:28] */
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_PWR_ZONE_CONFIG2_REG_MEM_OFF_DLY_MASK 0xf0000000
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_PWR_ZONE_CONFIG2_REG_MEM_OFF_DLY_SHIFT 28
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_PWR_ZONE_CONFIG2_REG_MEM_OFF_DLY_DEFAULT 0x00000004
-
-/* HIF_CPUBIUCTRL :: L2BIU_PWR_ZONE_CONFIG2_REG :: MEM_ON_DLY [27:24] */
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_PWR_ZONE_CONFIG2_REG_MEM_ON_DLY_MASK 0x0f000000
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_PWR_ZONE_CONFIG2_REG_MEM_ON_DLY_SHIFT 24
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_PWR_ZONE_CONFIG2_REG_MEM_ON_DLY_DEFAULT 0x00000004
-
-/* HIF_CPUBIUCTRL :: L2BIU_PWR_ZONE_CONFIG2_REG :: DPG_OFF_DLY [23:20] */
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_PWR_ZONE_CONFIG2_REG_DPG_OFF_DLY_MASK 0x00f00000
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_PWR_ZONE_CONFIG2_REG_DPG_OFF_DLY_SHIFT 20
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_PWR_ZONE_CONFIG2_REG_DPG_OFF_DLY_DEFAULT 0x00000004
-
-/* HIF_CPUBIUCTRL :: L2BIU_PWR_ZONE_CONFIG2_REG :: DPG1_ON_DLY [19:16] */
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_PWR_ZONE_CONFIG2_REG_DPG1_ON_DLY_MASK 0x000f0000
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_PWR_ZONE_CONFIG2_REG_DPG1_ON_DLY_SHIFT 16
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_PWR_ZONE_CONFIG2_REG_DPG1_ON_DLY_DEFAULT 0x00000003
-
-/* HIF_CPUBIUCTRL :: L2BIU_PWR_ZONE_CONFIG2_REG :: DPGN_ON_DLY [15:12] */
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_PWR_ZONE_CONFIG2_REG_DPGN_ON_DLY_MASK 0x0000f000
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_PWR_ZONE_CONFIG2_REG_DPGN_ON_DLY_SHIFT 12
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_PWR_ZONE_CONFIG2_REG_DPGN_ON_DLY_DEFAULT 0x00000001
-
-/* HIF_CPUBIUCTRL :: L2BIU_PWR_ZONE_CONFIG2_REG :: reserved0 [11:06] */
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_PWR_ZONE_CONFIG2_REG_reserved0_MASK 0x00000fc0
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_PWR_ZONE_CONFIG2_REG_reserved0_SHIFT 6
-
-/* HIF_CPUBIUCTRL :: L2BIU_PWR_ZONE_CONFIG2_REG :: SLEW_PRESCALE_SEL [05:03] */
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_PWR_ZONE_CONFIG2_REG_SLEW_PRESCALE_SEL_MASK 0x00000038
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_PWR_ZONE_CONFIG2_REG_SLEW_PRESCALE_SEL_SHIFT 3
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_PWR_ZONE_CONFIG2_REG_SLEW_PRESCALE_SEL_DEFAULT 0x00000002
-
-/* HIF_CPUBIUCTRL :: L2BIU_PWR_ZONE_CONFIG2_REG :: DELAY_PRESCALE_SEL [02:00] */
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_PWR_ZONE_CONFIG2_REG_DELAY_PRESCALE_SEL_MASK 0x00000007
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_PWR_ZONE_CONFIG2_REG_DELAY_PRESCALE_SEL_SHIFT 0
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_PWR_ZONE_CONFIG2_REG_DELAY_PRESCALE_SEL_DEFAULT 0x00000002
-
-/***************************************************************************
- *CPU0_PWR_FREQ_SCALAR_CTRL_REG - CPU0 BPCM Frequency Scalar Control Register
- ***************************************************************************/
-/* HIF_CPUBIUCTRL :: CPU0_PWR_FREQ_SCALAR_CTRL_REG :: reserved0 [31:10] */
-#define BCHP_HIF_CPUBIUCTRL_CPU0_PWR_FREQ_SCALAR_CTRL_REG_reserved0_MASK 0xfffffc00
-#define BCHP_HIF_CPUBIUCTRL_CPU0_PWR_FREQ_SCALAR_CTRL_REG_reserved0_SHIFT 10
-
-/* HIF_CPUBIUCTRL :: CPU0_PWR_FREQ_SCALAR_CTRL_REG :: HIGH_GEAR_DIV [09:07] */
-#define BCHP_HIF_CPUBIUCTRL_CPU0_PWR_FREQ_SCALAR_CTRL_REG_HIGH_GEAR_DIV_MASK 0x00000380
-#define BCHP_HIF_CPUBIUCTRL_CPU0_PWR_FREQ_SCALAR_CTRL_REG_HIGH_GEAR_DIV_SHIFT 7
-#define BCHP_HIF_CPUBIUCTRL_CPU0_PWR_FREQ_SCALAR_CTRL_REG_HIGH_GEAR_DIV_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: CPU0_PWR_FREQ_SCALAR_CTRL_REG :: LOW_GEAR_DIV [06:04] */
-#define BCHP_HIF_CPUBIUCTRL_CPU0_PWR_FREQ_SCALAR_CTRL_REG_LOW_GEAR_DIV_MASK 0x00000070
-#define BCHP_HIF_CPUBIUCTRL_CPU0_PWR_FREQ_SCALAR_CTRL_REG_LOW_GEAR_DIV_SHIFT 4
-#define BCHP_HIF_CPUBIUCTRL_CPU0_PWR_FREQ_SCALAR_CTRL_REG_LOW_GEAR_DIV_DEFAULT 0x00000001
-
-/* HIF_CPUBIUCTRL :: CPU0_PWR_FREQ_SCALAR_CTRL_REG :: reserved1 [03:03] */
-#define BCHP_HIF_CPUBIUCTRL_CPU0_PWR_FREQ_SCALAR_CTRL_REG_reserved1_MASK 0x00000008
-#define BCHP_HIF_CPUBIUCTRL_CPU0_PWR_FREQ_SCALAR_CTRL_REG_reserved1_SHIFT 3
-
-/* HIF_CPUBIUCTRL :: CPU0_PWR_FREQ_SCALAR_CTRL_REG :: USE_DYN_GEAR_SEL [02:02] */
-#define BCHP_HIF_CPUBIUCTRL_CPU0_PWR_FREQ_SCALAR_CTRL_REG_USE_DYN_GEAR_SEL_MASK 0x00000004
-#define BCHP_HIF_CPUBIUCTRL_CPU0_PWR_FREQ_SCALAR_CTRL_REG_USE_DYN_GEAR_SEL_SHIFT 2
-#define BCHP_HIF_CPUBIUCTRL_CPU0_PWR_FREQ_SCALAR_CTRL_REG_USE_DYN_GEAR_SEL_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: CPU0_PWR_FREQ_SCALAR_CTRL_REG :: GEAR_SELECT [01:01] */
-#define BCHP_HIF_CPUBIUCTRL_CPU0_PWR_FREQ_SCALAR_CTRL_REG_GEAR_SELECT_MASK 0x00000002
-#define BCHP_HIF_CPUBIUCTRL_CPU0_PWR_FREQ_SCALAR_CTRL_REG_GEAR_SELECT_SHIFT 1
-#define BCHP_HIF_CPUBIUCTRL_CPU0_PWR_FREQ_SCALAR_CTRL_REG_GEAR_SELECT_DEFAULT 0x00000001
-
-/* HIF_CPUBIUCTRL :: CPU0_PWR_FREQ_SCALAR_CTRL_REG :: FS_BYPASS_EN [00:00] */
-#define BCHP_HIF_CPUBIUCTRL_CPU0_PWR_FREQ_SCALAR_CTRL_REG_FS_BYPASS_EN_MASK 0x00000001
-#define BCHP_HIF_CPUBIUCTRL_CPU0_PWR_FREQ_SCALAR_CTRL_REG_FS_BYPASS_EN_SHIFT 0
-#define BCHP_HIF_CPUBIUCTRL_CPU0_PWR_FREQ_SCALAR_CTRL_REG_FS_BYPASS_EN_DEFAULT 0x00000000
-
-/***************************************************************************
- *CPU1_PWR_FREQ_SCALAR_CTRL_REG - CPU1 BPCM Frequency Scalar Control Register
- ***************************************************************************/
-/* HIF_CPUBIUCTRL :: CPU1_PWR_FREQ_SCALAR_CTRL_REG :: reserved0 [31:10] */
-#define BCHP_HIF_CPUBIUCTRL_CPU1_PWR_FREQ_SCALAR_CTRL_REG_reserved0_MASK 0xfffffc00
-#define BCHP_HIF_CPUBIUCTRL_CPU1_PWR_FREQ_SCALAR_CTRL_REG_reserved0_SHIFT 10
-
-/* HIF_CPUBIUCTRL :: CPU1_PWR_FREQ_SCALAR_CTRL_REG :: HIGH_GEAR_DIV [09:07] */
-#define BCHP_HIF_CPUBIUCTRL_CPU1_PWR_FREQ_SCALAR_CTRL_REG_HIGH_GEAR_DIV_MASK 0x00000380
-#define BCHP_HIF_CPUBIUCTRL_CPU1_PWR_FREQ_SCALAR_CTRL_REG_HIGH_GEAR_DIV_SHIFT 7
-#define BCHP_HIF_CPUBIUCTRL_CPU1_PWR_FREQ_SCALAR_CTRL_REG_HIGH_GEAR_DIV_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: CPU1_PWR_FREQ_SCALAR_CTRL_REG :: LOW_GEAR_DIV [06:04] */
-#define BCHP_HIF_CPUBIUCTRL_CPU1_PWR_FREQ_SCALAR_CTRL_REG_LOW_GEAR_DIV_MASK 0x00000070
-#define BCHP_HIF_CPUBIUCTRL_CPU1_PWR_FREQ_SCALAR_CTRL_REG_LOW_GEAR_DIV_SHIFT 4
-#define BCHP_HIF_CPUBIUCTRL_CPU1_PWR_FREQ_SCALAR_CTRL_REG_LOW_GEAR_DIV_DEFAULT 0x00000001
-
-/* HIF_CPUBIUCTRL :: CPU1_PWR_FREQ_SCALAR_CTRL_REG :: reserved1 [03:03] */
-#define BCHP_HIF_CPUBIUCTRL_CPU1_PWR_FREQ_SCALAR_CTRL_REG_reserved1_MASK 0x00000008
-#define BCHP_HIF_CPUBIUCTRL_CPU1_PWR_FREQ_SCALAR_CTRL_REG_reserved1_SHIFT 3
-
-/* HIF_CPUBIUCTRL :: CPU1_PWR_FREQ_SCALAR_CTRL_REG :: USE_DYN_GEAR_SEL [02:02] */
-#define BCHP_HIF_CPUBIUCTRL_CPU1_PWR_FREQ_SCALAR_CTRL_REG_USE_DYN_GEAR_SEL_MASK 0x00000004
-#define BCHP_HIF_CPUBIUCTRL_CPU1_PWR_FREQ_SCALAR_CTRL_REG_USE_DYN_GEAR_SEL_SHIFT 2
-#define BCHP_HIF_CPUBIUCTRL_CPU1_PWR_FREQ_SCALAR_CTRL_REG_USE_DYN_GEAR_SEL_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: CPU1_PWR_FREQ_SCALAR_CTRL_REG :: GEAR_SELECT [01:01] */
-#define BCHP_HIF_CPUBIUCTRL_CPU1_PWR_FREQ_SCALAR_CTRL_REG_GEAR_SELECT_MASK 0x00000002
-#define BCHP_HIF_CPUBIUCTRL_CPU1_PWR_FREQ_SCALAR_CTRL_REG_GEAR_SELECT_SHIFT 1
-#define BCHP_HIF_CPUBIUCTRL_CPU1_PWR_FREQ_SCALAR_CTRL_REG_GEAR_SELECT_DEFAULT 0x00000001
-
-/* HIF_CPUBIUCTRL :: CPU1_PWR_FREQ_SCALAR_CTRL_REG :: FS_BYPASS_EN [00:00] */
-#define BCHP_HIF_CPUBIUCTRL_CPU1_PWR_FREQ_SCALAR_CTRL_REG_FS_BYPASS_EN_MASK 0x00000001
-#define BCHP_HIF_CPUBIUCTRL_CPU1_PWR_FREQ_SCALAR_CTRL_REG_FS_BYPASS_EN_SHIFT 0
-#define BCHP_HIF_CPUBIUCTRL_CPU1_PWR_FREQ_SCALAR_CTRL_REG_FS_BYPASS_EN_DEFAULT 0x00000000
-
-/***************************************************************************
- *CPU2_PWR_FREQ_SCALAR_CTRL_REG - CPU2 BPCM Frequency Scalar Control Register
- ***************************************************************************/
-/* HIF_CPUBIUCTRL :: CPU2_PWR_FREQ_SCALAR_CTRL_REG :: reserved0 [31:10] */
-#define BCHP_HIF_CPUBIUCTRL_CPU2_PWR_FREQ_SCALAR_CTRL_REG_reserved0_MASK 0xfffffc00
-#define BCHP_HIF_CPUBIUCTRL_CPU2_PWR_FREQ_SCALAR_CTRL_REG_reserved0_SHIFT 10
-
-/* HIF_CPUBIUCTRL :: CPU2_PWR_FREQ_SCALAR_CTRL_REG :: HIGH_GEAR_DIV [09:07] */
-#define BCHP_HIF_CPUBIUCTRL_CPU2_PWR_FREQ_SCALAR_CTRL_REG_HIGH_GEAR_DIV_MASK 0x00000380
-#define BCHP_HIF_CPUBIUCTRL_CPU2_PWR_FREQ_SCALAR_CTRL_REG_HIGH_GEAR_DIV_SHIFT 7
-#define BCHP_HIF_CPUBIUCTRL_CPU2_PWR_FREQ_SCALAR_CTRL_REG_HIGH_GEAR_DIV_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: CPU2_PWR_FREQ_SCALAR_CTRL_REG :: LOW_GEAR_DIV [06:04] */
-#define BCHP_HIF_CPUBIUCTRL_CPU2_PWR_FREQ_SCALAR_CTRL_REG_LOW_GEAR_DIV_MASK 0x00000070
-#define BCHP_HIF_CPUBIUCTRL_CPU2_PWR_FREQ_SCALAR_CTRL_REG_LOW_GEAR_DIV_SHIFT 4
-#define BCHP_HIF_CPUBIUCTRL_CPU2_PWR_FREQ_SCALAR_CTRL_REG_LOW_GEAR_DIV_DEFAULT 0x00000001
-
-/* HIF_CPUBIUCTRL :: CPU2_PWR_FREQ_SCALAR_CTRL_REG :: reserved1 [03:03] */
-#define BCHP_HIF_CPUBIUCTRL_CPU2_PWR_FREQ_SCALAR_CTRL_REG_reserved1_MASK 0x00000008
-#define BCHP_HIF_CPUBIUCTRL_CPU2_PWR_FREQ_SCALAR_CTRL_REG_reserved1_SHIFT 3
-
-/* HIF_CPUBIUCTRL :: CPU2_PWR_FREQ_SCALAR_CTRL_REG :: USE_DYN_GEAR_SEL [02:02] */
-#define BCHP_HIF_CPUBIUCTRL_CPU2_PWR_FREQ_SCALAR_CTRL_REG_USE_DYN_GEAR_SEL_MASK 0x00000004
-#define BCHP_HIF_CPUBIUCTRL_CPU2_PWR_FREQ_SCALAR_CTRL_REG_USE_DYN_GEAR_SEL_SHIFT 2
-#define BCHP_HIF_CPUBIUCTRL_CPU2_PWR_FREQ_SCALAR_CTRL_REG_USE_DYN_GEAR_SEL_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: CPU2_PWR_FREQ_SCALAR_CTRL_REG :: GEAR_SELECT [01:01] */
-#define BCHP_HIF_CPUBIUCTRL_CPU2_PWR_FREQ_SCALAR_CTRL_REG_GEAR_SELECT_MASK 0x00000002
-#define BCHP_HIF_CPUBIUCTRL_CPU2_PWR_FREQ_SCALAR_CTRL_REG_GEAR_SELECT_SHIFT 1
-#define BCHP_HIF_CPUBIUCTRL_CPU2_PWR_FREQ_SCALAR_CTRL_REG_GEAR_SELECT_DEFAULT 0x00000001
-
-/* HIF_CPUBIUCTRL :: CPU2_PWR_FREQ_SCALAR_CTRL_REG :: FS_BYPASS_EN [00:00] */
-#define BCHP_HIF_CPUBIUCTRL_CPU2_PWR_FREQ_SCALAR_CTRL_REG_FS_BYPASS_EN_MASK 0x00000001
-#define BCHP_HIF_CPUBIUCTRL_CPU2_PWR_FREQ_SCALAR_CTRL_REG_FS_BYPASS_EN_SHIFT 0
-#define BCHP_HIF_CPUBIUCTRL_CPU2_PWR_FREQ_SCALAR_CTRL_REG_FS_BYPASS_EN_DEFAULT 0x00000000
-
-/***************************************************************************
- *CPU3_PWR_FREQ_SCALAR_CTRL_REG - CPU3 BPCM Frequency Scalar Control Register
- ***************************************************************************/
-/* HIF_CPUBIUCTRL :: CPU3_PWR_FREQ_SCALAR_CTRL_REG :: reserved0 [31:10] */
-#define BCHP_HIF_CPUBIUCTRL_CPU3_PWR_FREQ_SCALAR_CTRL_REG_reserved0_MASK 0xfffffc00
-#define BCHP_HIF_CPUBIUCTRL_CPU3_PWR_FREQ_SCALAR_CTRL_REG_reserved0_SHIFT 10
-
-/* HIF_CPUBIUCTRL :: CPU3_PWR_FREQ_SCALAR_CTRL_REG :: HIGH_GEAR_DIV [09:07] */
-#define BCHP_HIF_CPUBIUCTRL_CPU3_PWR_FREQ_SCALAR_CTRL_REG_HIGH_GEAR_DIV_MASK 0x00000380
-#define BCHP_HIF_CPUBIUCTRL_CPU3_PWR_FREQ_SCALAR_CTRL_REG_HIGH_GEAR_DIV_SHIFT 7
-#define BCHP_HIF_CPUBIUCTRL_CPU3_PWR_FREQ_SCALAR_CTRL_REG_HIGH_GEAR_DIV_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: CPU3_PWR_FREQ_SCALAR_CTRL_REG :: LOW_GEAR_DIV [06:04] */
-#define BCHP_HIF_CPUBIUCTRL_CPU3_PWR_FREQ_SCALAR_CTRL_REG_LOW_GEAR_DIV_MASK 0x00000070
-#define BCHP_HIF_CPUBIUCTRL_CPU3_PWR_FREQ_SCALAR_CTRL_REG_LOW_GEAR_DIV_SHIFT 4
-#define BCHP_HIF_CPUBIUCTRL_CPU3_PWR_FREQ_SCALAR_CTRL_REG_LOW_GEAR_DIV_DEFAULT 0x00000001
-
-/* HIF_CPUBIUCTRL :: CPU3_PWR_FREQ_SCALAR_CTRL_REG :: reserved1 [03:03] */
-#define BCHP_HIF_CPUBIUCTRL_CPU3_PWR_FREQ_SCALAR_CTRL_REG_reserved1_MASK 0x00000008
-#define BCHP_HIF_CPUBIUCTRL_CPU3_PWR_FREQ_SCALAR_CTRL_REG_reserved1_SHIFT 3
-
-/* HIF_CPUBIUCTRL :: CPU3_PWR_FREQ_SCALAR_CTRL_REG :: USE_DYN_GEAR_SEL [02:02] */
-#define BCHP_HIF_CPUBIUCTRL_CPU3_PWR_FREQ_SCALAR_CTRL_REG_USE_DYN_GEAR_SEL_MASK 0x00000004
-#define BCHP_HIF_CPUBIUCTRL_CPU3_PWR_FREQ_SCALAR_CTRL_REG_USE_DYN_GEAR_SEL_SHIFT 2
-#define BCHP_HIF_CPUBIUCTRL_CPU3_PWR_FREQ_SCALAR_CTRL_REG_USE_DYN_GEAR_SEL_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: CPU3_PWR_FREQ_SCALAR_CTRL_REG :: GEAR_SELECT [01:01] */
-#define BCHP_HIF_CPUBIUCTRL_CPU3_PWR_FREQ_SCALAR_CTRL_REG_GEAR_SELECT_MASK 0x00000002
-#define BCHP_HIF_CPUBIUCTRL_CPU3_PWR_FREQ_SCALAR_CTRL_REG_GEAR_SELECT_SHIFT 1
-#define BCHP_HIF_CPUBIUCTRL_CPU3_PWR_FREQ_SCALAR_CTRL_REG_GEAR_SELECT_DEFAULT 0x00000001
-
-/* HIF_CPUBIUCTRL :: CPU3_PWR_FREQ_SCALAR_CTRL_REG :: FS_BYPASS_EN [00:00] */
-#define BCHP_HIF_CPUBIUCTRL_CPU3_PWR_FREQ_SCALAR_CTRL_REG_FS_BYPASS_EN_MASK 0x00000001
-#define BCHP_HIF_CPUBIUCTRL_CPU3_PWR_FREQ_SCALAR_CTRL_REG_FS_BYPASS_EN_SHIFT 0
-#define BCHP_HIF_CPUBIUCTRL_CPU3_PWR_FREQ_SCALAR_CTRL_REG_FS_BYPASS_EN_DEFAULT 0x00000000
-
-/***************************************************************************
- *L2BIU_PWR_FREQ_SCALAR_CTRL_REG - L2/BIU BPCM Frequency Scalar Control Register
- ***************************************************************************/
-/* HIF_CPUBIUCTRL :: L2BIU_PWR_FREQ_SCALAR_CTRL_REG :: reserved0 [31:10] */
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_PWR_FREQ_SCALAR_CTRL_REG_reserved0_MASK 0xfffffc00
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_PWR_FREQ_SCALAR_CTRL_REG_reserved0_SHIFT 10
-
-/* HIF_CPUBIUCTRL :: L2BIU_PWR_FREQ_SCALAR_CTRL_REG :: HIGH_GEAR_DIV [09:07] */
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_PWR_FREQ_SCALAR_CTRL_REG_HIGH_GEAR_DIV_MASK 0x00000380
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_PWR_FREQ_SCALAR_CTRL_REG_HIGH_GEAR_DIV_SHIFT 7
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_PWR_FREQ_SCALAR_CTRL_REG_HIGH_GEAR_DIV_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: L2BIU_PWR_FREQ_SCALAR_CTRL_REG :: LOW_GEAR_DIV [06:04] */
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_PWR_FREQ_SCALAR_CTRL_REG_LOW_GEAR_DIV_MASK 0x00000070
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_PWR_FREQ_SCALAR_CTRL_REG_LOW_GEAR_DIV_SHIFT 4
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_PWR_FREQ_SCALAR_CTRL_REG_LOW_GEAR_DIV_DEFAULT 0x00000001
-
-/* HIF_CPUBIUCTRL :: L2BIU_PWR_FREQ_SCALAR_CTRL_REG :: reserved1 [03:03] */
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_PWR_FREQ_SCALAR_CTRL_REG_reserved1_MASK 0x00000008
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_PWR_FREQ_SCALAR_CTRL_REG_reserved1_SHIFT 3
-
-/* HIF_CPUBIUCTRL :: L2BIU_PWR_FREQ_SCALAR_CTRL_REG :: USE_DYN_GEAR_SEL [02:02] */
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_PWR_FREQ_SCALAR_CTRL_REG_USE_DYN_GEAR_SEL_MASK 0x00000004
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_PWR_FREQ_SCALAR_CTRL_REG_USE_DYN_GEAR_SEL_SHIFT 2
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_PWR_FREQ_SCALAR_CTRL_REG_USE_DYN_GEAR_SEL_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: L2BIU_PWR_FREQ_SCALAR_CTRL_REG :: GEAR_SELECT [01:01] */
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_PWR_FREQ_SCALAR_CTRL_REG_GEAR_SELECT_MASK 0x00000002
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_PWR_FREQ_SCALAR_CTRL_REG_GEAR_SELECT_SHIFT 1
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_PWR_FREQ_SCALAR_CTRL_REG_GEAR_SELECT_DEFAULT 0x00000001
-
-/* HIF_CPUBIUCTRL :: L2BIU_PWR_FREQ_SCALAR_CTRL_REG :: FS_BYPASS_EN [00:00] */
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_PWR_FREQ_SCALAR_CTRL_REG_FS_BYPASS_EN_MASK 0x00000001
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_PWR_FREQ_SCALAR_CTRL_REG_FS_BYPASS_EN_SHIFT 0
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_PWR_FREQ_SCALAR_CTRL_REG_FS_BYPASS_EN_DEFAULT 0x00000000
-
-/***************************************************************************
- *CPU0_BPCM_ID - CPU0 BPCM ID Register
- ***************************************************************************/
-/* HIF_CPUBIUCTRL :: CPU0_BPCM_ID :: SW_strap [31:16] */
-#define BCHP_HIF_CPUBIUCTRL_CPU0_BPCM_ID_SW_strap_MASK 0xffff0000
-#define BCHP_HIF_CPUBIUCTRL_CPU0_BPCM_ID_SW_strap_SHIFT 16
-
-/* HIF_CPUBIUCTRL :: CPU0_BPCM_ID :: HW_revision [15:08] */
-#define BCHP_HIF_CPUBIUCTRL_CPU0_BPCM_ID_HW_revision_MASK 0x0000ff00
-#define BCHP_HIF_CPUBIUCTRL_CPU0_BPCM_ID_HW_revision_SHIFT 8
-
-/* HIF_CPUBIUCTRL :: CPU0_BPCM_ID :: PMB_ADDR [07:00] */
-#define BCHP_HIF_CPUBIUCTRL_CPU0_BPCM_ID_PMB_ADDR_MASK 0x000000ff
-#define BCHP_HIF_CPUBIUCTRL_CPU0_BPCM_ID_PMB_ADDR_SHIFT 0
-
-/***************************************************************************
- *CPU0_BPCM_CAPABILITY - CPU0 BPCM Capability Register
- ***************************************************************************/
-/* HIF_CPUBIUCTRL :: CPU0_BPCM_CAPABILITY :: reserved0 [31:08] */
-#define BCHP_HIF_CPUBIUCTRL_CPU0_BPCM_CAPABILITY_reserved0_MASK 0xffffff00
-#define BCHP_HIF_CPUBIUCTRL_CPU0_BPCM_CAPABILITY_reserved0_SHIFT 8
-
-/* HIF_CPUBIUCTRL :: CPU0_BPCM_CAPABILITY :: Number_of_zones [07:00] */
-#define BCHP_HIF_CPUBIUCTRL_CPU0_BPCM_CAPABILITY_Number_of_zones_MASK 0x000000ff
-#define BCHP_HIF_CPUBIUCTRL_CPU0_BPCM_CAPABILITY_Number_of_zones_SHIFT 0
-
-/***************************************************************************
- *CPU0_BPCM_CONTROL - CPU0 BPCM Control Register
- ***************************************************************************/
-/* HIF_CPUBIUCTRL :: CPU0_BPCM_CONTROL :: TbdField [31:00] */
-#define BCHP_HIF_CPUBIUCTRL_CPU0_BPCM_CONTROL_TbdField_MASK 0xffffffff
-#define BCHP_HIF_CPUBIUCTRL_CPU0_BPCM_CONTROL_TbdField_SHIFT 0
-
-/***************************************************************************
- *CPU0_BPCM_STATUS - CPU0 BPCM Status Register
- ***************************************************************************/
-/* HIF_CPUBIUCTRL :: CPU0_BPCM_STATUS :: reserved0 [31:01] */
-#define BCHP_HIF_CPUBIUCTRL_CPU0_BPCM_STATUS_reserved0_MASK 0xfffffffe
-#define BCHP_HIF_CPUBIUCTRL_CPU0_BPCM_STATUS_reserved0_SHIFT 1
-
-/* HIF_CPUBIUCTRL :: CPU0_BPCM_STATUS :: PWD_Alert [00:00] */
-#define BCHP_HIF_CPUBIUCTRL_CPU0_BPCM_STATUS_PWD_Alert_MASK 0x00000001
-#define BCHP_HIF_CPUBIUCTRL_CPU0_BPCM_STATUS_PWD_Alert_SHIFT 0
-
-/***************************************************************************
- *CPU0_AVS_ROSC_CONTROL - CPU0 Ring Oscillator Control Register
- ***************************************************************************/
-/* HIF_CPUBIUCTRL :: CPU0_AVS_ROSC_CONTROL :: Test_interval [31:16] */
-#define BCHP_HIF_CPUBIUCTRL_CPU0_AVS_ROSC_CONTROL_Test_interval_MASK 0xffff0000
-#define BCHP_HIF_CPUBIUCTRL_CPU0_AVS_ROSC_CONTROL_Test_interval_SHIFT 16
-#define BCHP_HIF_CPUBIUCTRL_CPU0_AVS_ROSC_CONTROL_Test_interval_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: CPU0_AVS_ROSC_CONTROL :: ALERT_H [15:15] */
-#define BCHP_HIF_CPUBIUCTRL_CPU0_AVS_ROSC_CONTROL_ALERT_H_MASK 0x00008000
-#define BCHP_HIF_CPUBIUCTRL_CPU0_AVS_ROSC_CONTROL_ALERT_H_SHIFT 15
-#define BCHP_HIF_CPUBIUCTRL_CPU0_AVS_ROSC_CONTROL_ALERT_H_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: CPU0_AVS_ROSC_CONTROL :: VALID_H [14:14] */
-#define BCHP_HIF_CPUBIUCTRL_CPU0_AVS_ROSC_CONTROL_VALID_H_MASK 0x00004000
-#define BCHP_HIF_CPUBIUCTRL_CPU0_AVS_ROSC_CONTROL_VALID_H_SHIFT 14
-#define BCHP_HIF_CPUBIUCTRL_CPU0_AVS_ROSC_CONTROL_VALID_H_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: CPU0_AVS_ROSC_CONTROL :: ALERT_S [13:13] */
-#define BCHP_HIF_CPUBIUCTRL_CPU0_AVS_ROSC_CONTROL_ALERT_S_MASK 0x00002000
-#define BCHP_HIF_CPUBIUCTRL_CPU0_AVS_ROSC_CONTROL_ALERT_S_SHIFT 13
-#define BCHP_HIF_CPUBIUCTRL_CPU0_AVS_ROSC_CONTROL_ALERT_S_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: CPU0_AVS_ROSC_CONTROL :: VALID_S [12:12] */
-#define BCHP_HIF_CPUBIUCTRL_CPU0_AVS_ROSC_CONTROL_VALID_S_MASK 0x00001000
-#define BCHP_HIF_CPUBIUCTRL_CPU0_AVS_ROSC_CONTROL_VALID_S_SHIFT 12
-#define BCHP_HIF_CPUBIUCTRL_CPU0_AVS_ROSC_CONTROL_VALID_S_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: CPU0_AVS_ROSC_CONTROL :: reserved0 [11:08] */
-#define BCHP_HIF_CPUBIUCTRL_CPU0_AVS_ROSC_CONTROL_reserved0_MASK 0x00000f00
-#define BCHP_HIF_CPUBIUCTRL_CPU0_AVS_ROSC_CONTROL_reserved0_SHIFT 8
-
-/* HIF_CPUBIUCTRL :: CPU0_AVS_ROSC_CONTROL :: CONTINUOUS_H [07:07] */
-#define BCHP_HIF_CPUBIUCTRL_CPU0_AVS_ROSC_CONTROL_CONTINUOUS_H_MASK 0x00000080
-#define BCHP_HIF_CPUBIUCTRL_CPU0_AVS_ROSC_CONTROL_CONTINUOUS_H_SHIFT 7
-#define BCHP_HIF_CPUBIUCTRL_CPU0_AVS_ROSC_CONTROL_CONTINUOUS_H_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: CPU0_AVS_ROSC_CONTROL :: CONTINUOUS_S [06:06] */
-#define BCHP_HIF_CPUBIUCTRL_CPU0_AVS_ROSC_CONTROL_CONTINUOUS_S_MASK 0x00000040
-#define BCHP_HIF_CPUBIUCTRL_CPU0_AVS_ROSC_CONTROL_CONTINUOUS_S_SHIFT 6
-#define BCHP_HIF_CPUBIUCTRL_CPU0_AVS_ROSC_CONTROL_CONTINUOUS_S_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: CPU0_AVS_ROSC_CONTROL :: THRSH_EN_H [05:05] */
-#define BCHP_HIF_CPUBIUCTRL_CPU0_AVS_ROSC_CONTROL_THRSH_EN_H_MASK 0x00000020
-#define BCHP_HIF_CPUBIUCTRL_CPU0_AVS_ROSC_CONTROL_THRSH_EN_H_SHIFT 5
-#define BCHP_HIF_CPUBIUCTRL_CPU0_AVS_ROSC_CONTROL_THRSH_EN_H_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: CPU0_AVS_ROSC_CONTROL :: THRSH_EN_S [04:04] */
-#define BCHP_HIF_CPUBIUCTRL_CPU0_AVS_ROSC_CONTROL_THRSH_EN_S_MASK 0x00000010
-#define BCHP_HIF_CPUBIUCTRL_CPU0_AVS_ROSC_CONTROL_THRSH_EN_S_SHIFT 4
-#define BCHP_HIF_CPUBIUCTRL_CPU0_AVS_ROSC_CONTROL_THRSH_EN_S_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: CPU0_AVS_ROSC_CONTROL :: ECTR_EN_H [03:03] */
-#define BCHP_HIF_CPUBIUCTRL_CPU0_AVS_ROSC_CONTROL_ECTR_EN_H_MASK 0x00000008
-#define BCHP_HIF_CPUBIUCTRL_CPU0_AVS_ROSC_CONTROL_ECTR_EN_H_SHIFT 3
-#define BCHP_HIF_CPUBIUCTRL_CPU0_AVS_ROSC_CONTROL_ECTR_EN_H_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: CPU0_AVS_ROSC_CONTROL :: ECTR_EN_S [02:02] */
-#define BCHP_HIF_CPUBIUCTRL_CPU0_AVS_ROSC_CONTROL_ECTR_EN_S_MASK 0x00000004
-#define BCHP_HIF_CPUBIUCTRL_CPU0_AVS_ROSC_CONTROL_ECTR_EN_S_SHIFT 2
-#define BCHP_HIF_CPUBIUCTRL_CPU0_AVS_ROSC_CONTROL_ECTR_EN_S_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: CPU0_AVS_ROSC_CONTROL :: RO_EN_H [01:01] */
-#define BCHP_HIF_CPUBIUCTRL_CPU0_AVS_ROSC_CONTROL_RO_EN_H_MASK 0x00000002
-#define BCHP_HIF_CPUBIUCTRL_CPU0_AVS_ROSC_CONTROL_RO_EN_H_SHIFT 1
-#define BCHP_HIF_CPUBIUCTRL_CPU0_AVS_ROSC_CONTROL_RO_EN_H_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: CPU0_AVS_ROSC_CONTROL :: RO_EN_S [00:00] */
-#define BCHP_HIF_CPUBIUCTRL_CPU0_AVS_ROSC_CONTROL_RO_EN_S_MASK 0x00000001
-#define BCHP_HIF_CPUBIUCTRL_CPU0_AVS_ROSC_CONTROL_RO_EN_S_SHIFT 0
-#define BCHP_HIF_CPUBIUCTRL_CPU0_AVS_ROSC_CONTROL_RO_EN_S_DEFAULT 0x00000000
-
-/***************************************************************************
- *CPU0_AVS_ROSC_THRESHOLD - CPU0 Event Counter Threshold Register
- ***************************************************************************/
-/* HIF_CPUBIUCTRL :: CPU0_AVS_ROSC_THRESHOLD :: THRESH_HI [31:16] */
-#define BCHP_HIF_CPUBIUCTRL_CPU0_AVS_ROSC_THRESHOLD_THRESH_HI_MASK 0xffff0000
-#define BCHP_HIF_CPUBIUCTRL_CPU0_AVS_ROSC_THRESHOLD_THRESH_HI_SHIFT 16
-#define BCHP_HIF_CPUBIUCTRL_CPU0_AVS_ROSC_THRESHOLD_THRESH_HI_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: CPU0_AVS_ROSC_THRESHOLD :: THRESH_LO [15:00] */
-#define BCHP_HIF_CPUBIUCTRL_CPU0_AVS_ROSC_THRESHOLD_THRESH_LO_MASK 0x0000ffff
-#define BCHP_HIF_CPUBIUCTRL_CPU0_AVS_ROSC_THRESHOLD_THRESH_LO_SHIFT 0
-#define BCHP_HIF_CPUBIUCTRL_CPU0_AVS_ROSC_THRESHOLD_THRESH_LO_DEFAULT 0x00000000
-
-/***************************************************************************
- *CPU0_AVS_ROSC_COUNT - CPU0 Event Counter Count Register
- ***************************************************************************/
-/* HIF_CPUBIUCTRL :: CPU0_AVS_ROSC_COUNT :: COUNT_H [31:16] */
-#define BCHP_HIF_CPUBIUCTRL_CPU0_AVS_ROSC_COUNT_COUNT_H_MASK 0xffff0000
-#define BCHP_HIF_CPUBIUCTRL_CPU0_AVS_ROSC_COUNT_COUNT_H_SHIFT 16
-#define BCHP_HIF_CPUBIUCTRL_CPU0_AVS_ROSC_COUNT_COUNT_H_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: CPU0_AVS_ROSC_COUNT :: COUNT_S [15:00] */
-#define BCHP_HIF_CPUBIUCTRL_CPU0_AVS_ROSC_COUNT_COUNT_S_MASK 0x0000ffff
-#define BCHP_HIF_CPUBIUCTRL_CPU0_AVS_ROSC_COUNT_COUNT_S_SHIFT 0
-#define BCHP_HIF_CPUBIUCTRL_CPU0_AVS_ROSC_COUNT_COUNT_S_DEFAULT 0x00000000
-
-/***************************************************************************
- *CPU0_AVS_PWD_CONTROL - CPU0 PWD control Register
- ***************************************************************************/
-/* HIF_CPUBIUCTRL :: CPU0_AVS_PWD_CONTROL :: reserved0 [31:30] */
-#define BCHP_HIF_CPUBIUCTRL_CPU0_AVS_PWD_CONTROL_reserved0_MASK 0xc0000000
-#define BCHP_HIF_CPUBIUCTRL_CPU0_AVS_PWD_CONTROL_reserved0_SHIFT 30
-
-/* HIF_CPUBIUCTRL :: CPU0_AVS_PWD_CONTROL :: CLRCFG [29:27] */
-#define BCHP_HIF_CPUBIUCTRL_CPU0_AVS_PWD_CONTROL_CLRCFG_MASK 0x38000000
-#define BCHP_HIF_CPUBIUCTRL_CPU0_AVS_PWD_CONTROL_CLRCFG_SHIFT 27
-#define BCHP_HIF_CPUBIUCTRL_CPU0_AVS_PWD_CONTROL_CLRCFG_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: CPU0_AVS_PWD_CONTROL :: RSEL [26:24] */
-#define BCHP_HIF_CPUBIUCTRL_CPU0_AVS_PWD_CONTROL_RSEL_MASK 0x07000000
-#define BCHP_HIF_CPUBIUCTRL_CPU0_AVS_PWD_CONTROL_RSEL_SHIFT 24
-#define BCHP_HIF_CPUBIUCTRL_CPU0_AVS_PWD_CONTROL_RSEL_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: CPU0_AVS_PWD_CONTROL :: CGFG [23:16] */
-#define BCHP_HIF_CPUBIUCTRL_CPU0_AVS_PWD_CONTROL_CGFG_MASK 0x00ff0000
-#define BCHP_HIF_CPUBIUCTRL_CPU0_AVS_PWD_CONTROL_CGFG_SHIFT 16
-#define BCHP_HIF_CPUBIUCTRL_CPU0_AVS_PWD_CONTROL_CGFG_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: CPU0_AVS_PWD_CONTROL :: ALERT [15:15] */
-#define BCHP_HIF_CPUBIUCTRL_CPU0_AVS_PWD_CONTROL_ALERT_MASK 0x00008000
-#define BCHP_HIF_CPUBIUCTRL_CPU0_AVS_PWD_CONTROL_ALERT_SHIFT 15
-#define BCHP_HIF_CPUBIUCTRL_CPU0_AVS_PWD_CONTROL_ALERT_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: CPU0_AVS_PWD_CONTROL :: reserved1 [14:09] */
-#define BCHP_HIF_CPUBIUCTRL_CPU0_AVS_PWD_CONTROL_reserved1_MASK 0x00007e00
-#define BCHP_HIF_CPUBIUCTRL_CPU0_AVS_PWD_CONTROL_reserved1_SHIFT 9
-
-/* HIF_CPUBIUCTRL :: CPU0_AVS_PWD_CONTROL :: PWD_TM_EN [08:08] */
-#define BCHP_HIF_CPUBIUCTRL_CPU0_AVS_PWD_CONTROL_PWD_TM_EN_MASK 0x00000100
-#define BCHP_HIF_CPUBIUCTRL_CPU0_AVS_PWD_CONTROL_PWD_TM_EN_SHIFT 8
-#define BCHP_HIF_CPUBIUCTRL_CPU0_AVS_PWD_CONTROL_PWD_TM_EN_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: CPU0_AVS_PWD_CONTROL :: START [07:02] */
-#define BCHP_HIF_CPUBIUCTRL_CPU0_AVS_PWD_CONTROL_START_MASK 0x000000fc
-#define BCHP_HIF_CPUBIUCTRL_CPU0_AVS_PWD_CONTROL_START_SHIFT 2
-#define BCHP_HIF_CPUBIUCTRL_CPU0_AVS_PWD_CONTROL_START_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: CPU0_AVS_PWD_CONTROL :: PWD_ALERT_SEL [01:01] */
-#define BCHP_HIF_CPUBIUCTRL_CPU0_AVS_PWD_CONTROL_PWD_ALERT_SEL_MASK 0x00000002
-#define BCHP_HIF_CPUBIUCTRL_CPU0_AVS_PWD_CONTROL_PWD_ALERT_SEL_SHIFT 1
-#define BCHP_HIF_CPUBIUCTRL_CPU0_AVS_PWD_CONTROL_PWD_ALERT_SEL_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: CPU0_AVS_PWD_CONTROL :: PWD_EN [00:00] */
-#define BCHP_HIF_CPUBIUCTRL_CPU0_AVS_PWD_CONTROL_PWD_EN_MASK 0x00000001
-#define BCHP_HIF_CPUBIUCTRL_CPU0_AVS_PWD_CONTROL_PWD_EN_SHIFT 0
-#define BCHP_HIF_CPUBIUCTRL_CPU0_AVS_PWD_CONTROL_PWD_EN_DEFAULT 0x00000000
-
-/***************************************************************************
- *CPU1_BPCM_ID - CPU1 BPCM ID Register
- ***************************************************************************/
-/* HIF_CPUBIUCTRL :: CPU1_BPCM_ID :: SW_strap [31:16] */
-#define BCHP_HIF_CPUBIUCTRL_CPU1_BPCM_ID_SW_strap_MASK 0xffff0000
-#define BCHP_HIF_CPUBIUCTRL_CPU1_BPCM_ID_SW_strap_SHIFT 16
-
-/* HIF_CPUBIUCTRL :: CPU1_BPCM_ID :: HW_revision [15:08] */
-#define BCHP_HIF_CPUBIUCTRL_CPU1_BPCM_ID_HW_revision_MASK 0x0000ff00
-#define BCHP_HIF_CPUBIUCTRL_CPU1_BPCM_ID_HW_revision_SHIFT 8
-
-/* HIF_CPUBIUCTRL :: CPU1_BPCM_ID :: PMB_ADDR [07:00] */
-#define BCHP_HIF_CPUBIUCTRL_CPU1_BPCM_ID_PMB_ADDR_MASK 0x000000ff
-#define BCHP_HIF_CPUBIUCTRL_CPU1_BPCM_ID_PMB_ADDR_SHIFT 0
-
-/***************************************************************************
- *CPU1_BPCM_CAPABILITY - CPU1 BPCM Capability Register
- ***************************************************************************/
-/* HIF_CPUBIUCTRL :: CPU1_BPCM_CAPABILITY :: reserved0 [31:08] */
-#define BCHP_HIF_CPUBIUCTRL_CPU1_BPCM_CAPABILITY_reserved0_MASK 0xffffff00
-#define BCHP_HIF_CPUBIUCTRL_CPU1_BPCM_CAPABILITY_reserved0_SHIFT 8
-
-/* HIF_CPUBIUCTRL :: CPU1_BPCM_CAPABILITY :: Number_of_zones [07:00] */
-#define BCHP_HIF_CPUBIUCTRL_CPU1_BPCM_CAPABILITY_Number_of_zones_MASK 0x000000ff
-#define BCHP_HIF_CPUBIUCTRL_CPU1_BPCM_CAPABILITY_Number_of_zones_SHIFT 0
-
-/***************************************************************************
- *CPU1_BPCM_CONTROL - CPU1 BPCM Control Register
- ***************************************************************************/
-/* HIF_CPUBIUCTRL :: CPU1_BPCM_CONTROL :: TbdField [31:00] */
-#define BCHP_HIF_CPUBIUCTRL_CPU1_BPCM_CONTROL_TbdField_MASK 0xffffffff
-#define BCHP_HIF_CPUBIUCTRL_CPU1_BPCM_CONTROL_TbdField_SHIFT 0
-
-/***************************************************************************
- *CPU1_BPCM_STATUS - CPU1 BPCM Status Register
- ***************************************************************************/
-/* HIF_CPUBIUCTRL :: CPU1_BPCM_STATUS :: reserved0 [31:01] */
-#define BCHP_HIF_CPUBIUCTRL_CPU1_BPCM_STATUS_reserved0_MASK 0xfffffffe
-#define BCHP_HIF_CPUBIUCTRL_CPU1_BPCM_STATUS_reserved0_SHIFT 1
-
-/* HIF_CPUBIUCTRL :: CPU1_BPCM_STATUS :: PWD_Alert [00:00] */
-#define BCHP_HIF_CPUBIUCTRL_CPU1_BPCM_STATUS_PWD_Alert_MASK 0x00000001
-#define BCHP_HIF_CPUBIUCTRL_CPU1_BPCM_STATUS_PWD_Alert_SHIFT 0
-
-/***************************************************************************
- *CPU1_AVS_ROSC_CONTROL - CPU1 Ring Oscillator Control Register
- ***************************************************************************/
-/* HIF_CPUBIUCTRL :: CPU1_AVS_ROSC_CONTROL :: Test_interval [31:16] */
-#define BCHP_HIF_CPUBIUCTRL_CPU1_AVS_ROSC_CONTROL_Test_interval_MASK 0xffff0000
-#define BCHP_HIF_CPUBIUCTRL_CPU1_AVS_ROSC_CONTROL_Test_interval_SHIFT 16
-#define BCHP_HIF_CPUBIUCTRL_CPU1_AVS_ROSC_CONTROL_Test_interval_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: CPU1_AVS_ROSC_CONTROL :: ALERT_H [15:15] */
-#define BCHP_HIF_CPUBIUCTRL_CPU1_AVS_ROSC_CONTROL_ALERT_H_MASK 0x00008000
-#define BCHP_HIF_CPUBIUCTRL_CPU1_AVS_ROSC_CONTROL_ALERT_H_SHIFT 15
-#define BCHP_HIF_CPUBIUCTRL_CPU1_AVS_ROSC_CONTROL_ALERT_H_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: CPU1_AVS_ROSC_CONTROL :: VALID_H [14:14] */
-#define BCHP_HIF_CPUBIUCTRL_CPU1_AVS_ROSC_CONTROL_VALID_H_MASK 0x00004000
-#define BCHP_HIF_CPUBIUCTRL_CPU1_AVS_ROSC_CONTROL_VALID_H_SHIFT 14
-#define BCHP_HIF_CPUBIUCTRL_CPU1_AVS_ROSC_CONTROL_VALID_H_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: CPU1_AVS_ROSC_CONTROL :: ALERT_S [13:13] */
-#define BCHP_HIF_CPUBIUCTRL_CPU1_AVS_ROSC_CONTROL_ALERT_S_MASK 0x00002000
-#define BCHP_HIF_CPUBIUCTRL_CPU1_AVS_ROSC_CONTROL_ALERT_S_SHIFT 13
-#define BCHP_HIF_CPUBIUCTRL_CPU1_AVS_ROSC_CONTROL_ALERT_S_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: CPU1_AVS_ROSC_CONTROL :: VALID_S [12:12] */
-#define BCHP_HIF_CPUBIUCTRL_CPU1_AVS_ROSC_CONTROL_VALID_S_MASK 0x00001000
-#define BCHP_HIF_CPUBIUCTRL_CPU1_AVS_ROSC_CONTROL_VALID_S_SHIFT 12
-#define BCHP_HIF_CPUBIUCTRL_CPU1_AVS_ROSC_CONTROL_VALID_S_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: CPU1_AVS_ROSC_CONTROL :: reserved0 [11:08] */
-#define BCHP_HIF_CPUBIUCTRL_CPU1_AVS_ROSC_CONTROL_reserved0_MASK 0x00000f00
-#define BCHP_HIF_CPUBIUCTRL_CPU1_AVS_ROSC_CONTROL_reserved0_SHIFT 8
-
-/* HIF_CPUBIUCTRL :: CPU1_AVS_ROSC_CONTROL :: CONTINUOUS_H [07:07] */
-#define BCHP_HIF_CPUBIUCTRL_CPU1_AVS_ROSC_CONTROL_CONTINUOUS_H_MASK 0x00000080
-#define BCHP_HIF_CPUBIUCTRL_CPU1_AVS_ROSC_CONTROL_CONTINUOUS_H_SHIFT 7
-#define BCHP_HIF_CPUBIUCTRL_CPU1_AVS_ROSC_CONTROL_CONTINUOUS_H_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: CPU1_AVS_ROSC_CONTROL :: CONTINUOUS_S [06:06] */
-#define BCHP_HIF_CPUBIUCTRL_CPU1_AVS_ROSC_CONTROL_CONTINUOUS_S_MASK 0x00000040
-#define BCHP_HIF_CPUBIUCTRL_CPU1_AVS_ROSC_CONTROL_CONTINUOUS_S_SHIFT 6
-#define BCHP_HIF_CPUBIUCTRL_CPU1_AVS_ROSC_CONTROL_CONTINUOUS_S_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: CPU1_AVS_ROSC_CONTROL :: THRSH_EN_H [05:05] */
-#define BCHP_HIF_CPUBIUCTRL_CPU1_AVS_ROSC_CONTROL_THRSH_EN_H_MASK 0x00000020
-#define BCHP_HIF_CPUBIUCTRL_CPU1_AVS_ROSC_CONTROL_THRSH_EN_H_SHIFT 5
-#define BCHP_HIF_CPUBIUCTRL_CPU1_AVS_ROSC_CONTROL_THRSH_EN_H_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: CPU1_AVS_ROSC_CONTROL :: THRSH_EN_S [04:04] */
-#define BCHP_HIF_CPUBIUCTRL_CPU1_AVS_ROSC_CONTROL_THRSH_EN_S_MASK 0x00000010
-#define BCHP_HIF_CPUBIUCTRL_CPU1_AVS_ROSC_CONTROL_THRSH_EN_S_SHIFT 4
-#define BCHP_HIF_CPUBIUCTRL_CPU1_AVS_ROSC_CONTROL_THRSH_EN_S_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: CPU1_AVS_ROSC_CONTROL :: ECTR_EN_H [03:03] */
-#define BCHP_HIF_CPUBIUCTRL_CPU1_AVS_ROSC_CONTROL_ECTR_EN_H_MASK 0x00000008
-#define BCHP_HIF_CPUBIUCTRL_CPU1_AVS_ROSC_CONTROL_ECTR_EN_H_SHIFT 3
-#define BCHP_HIF_CPUBIUCTRL_CPU1_AVS_ROSC_CONTROL_ECTR_EN_H_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: CPU1_AVS_ROSC_CONTROL :: ECTR_EN_S [02:02] */
-#define BCHP_HIF_CPUBIUCTRL_CPU1_AVS_ROSC_CONTROL_ECTR_EN_S_MASK 0x00000004
-#define BCHP_HIF_CPUBIUCTRL_CPU1_AVS_ROSC_CONTROL_ECTR_EN_S_SHIFT 2
-#define BCHP_HIF_CPUBIUCTRL_CPU1_AVS_ROSC_CONTROL_ECTR_EN_S_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: CPU1_AVS_ROSC_CONTROL :: RO_EN_H [01:01] */
-#define BCHP_HIF_CPUBIUCTRL_CPU1_AVS_ROSC_CONTROL_RO_EN_H_MASK 0x00000002
-#define BCHP_HIF_CPUBIUCTRL_CPU1_AVS_ROSC_CONTROL_RO_EN_H_SHIFT 1
-#define BCHP_HIF_CPUBIUCTRL_CPU1_AVS_ROSC_CONTROL_RO_EN_H_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: CPU1_AVS_ROSC_CONTROL :: RO_EN_S [00:00] */
-#define BCHP_HIF_CPUBIUCTRL_CPU1_AVS_ROSC_CONTROL_RO_EN_S_MASK 0x00000001
-#define BCHP_HIF_CPUBIUCTRL_CPU1_AVS_ROSC_CONTROL_RO_EN_S_SHIFT 0
-#define BCHP_HIF_CPUBIUCTRL_CPU1_AVS_ROSC_CONTROL_RO_EN_S_DEFAULT 0x00000000
-
-/***************************************************************************
- *CPU1_AVS_ROSC_THRESHOLD - CPU1 Event Counter Threshold Register
- ***************************************************************************/
-/* HIF_CPUBIUCTRL :: CPU1_AVS_ROSC_THRESHOLD :: THRESH_HI [31:16] */
-#define BCHP_HIF_CPUBIUCTRL_CPU1_AVS_ROSC_THRESHOLD_THRESH_HI_MASK 0xffff0000
-#define BCHP_HIF_CPUBIUCTRL_CPU1_AVS_ROSC_THRESHOLD_THRESH_HI_SHIFT 16
-#define BCHP_HIF_CPUBIUCTRL_CPU1_AVS_ROSC_THRESHOLD_THRESH_HI_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: CPU1_AVS_ROSC_THRESHOLD :: THRESH_LO [15:00] */
-#define BCHP_HIF_CPUBIUCTRL_CPU1_AVS_ROSC_THRESHOLD_THRESH_LO_MASK 0x0000ffff
-#define BCHP_HIF_CPUBIUCTRL_CPU1_AVS_ROSC_THRESHOLD_THRESH_LO_SHIFT 0
-#define BCHP_HIF_CPUBIUCTRL_CPU1_AVS_ROSC_THRESHOLD_THRESH_LO_DEFAULT 0x00000000
-
-/***************************************************************************
- *CPU1_AVS_ROSC_COUNT - CPU1 Event Counter Count Register
- ***************************************************************************/
-/* HIF_CPUBIUCTRL :: CPU1_AVS_ROSC_COUNT :: COUNT_H [31:16] */
-#define BCHP_HIF_CPUBIUCTRL_CPU1_AVS_ROSC_COUNT_COUNT_H_MASK 0xffff0000
-#define BCHP_HIF_CPUBIUCTRL_CPU1_AVS_ROSC_COUNT_COUNT_H_SHIFT 16
-#define BCHP_HIF_CPUBIUCTRL_CPU1_AVS_ROSC_COUNT_COUNT_H_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: CPU1_AVS_ROSC_COUNT :: COUNT_S [15:00] */
-#define BCHP_HIF_CPUBIUCTRL_CPU1_AVS_ROSC_COUNT_COUNT_S_MASK 0x0000ffff
-#define BCHP_HIF_CPUBIUCTRL_CPU1_AVS_ROSC_COUNT_COUNT_S_SHIFT 0
-#define BCHP_HIF_CPUBIUCTRL_CPU1_AVS_ROSC_COUNT_COUNT_S_DEFAULT 0x00000000
-
-/***************************************************************************
- *CPU1_AVS_PWD_CONTROL - CPU1 PWD control Register
- ***************************************************************************/
-/* HIF_CPUBIUCTRL :: CPU1_AVS_PWD_CONTROL :: reserved0 [31:30] */
-#define BCHP_HIF_CPUBIUCTRL_CPU1_AVS_PWD_CONTROL_reserved0_MASK 0xc0000000
-#define BCHP_HIF_CPUBIUCTRL_CPU1_AVS_PWD_CONTROL_reserved0_SHIFT 30
-
-/* HIF_CPUBIUCTRL :: CPU1_AVS_PWD_CONTROL :: CLRCFG [29:27] */
-#define BCHP_HIF_CPUBIUCTRL_CPU1_AVS_PWD_CONTROL_CLRCFG_MASK 0x38000000
-#define BCHP_HIF_CPUBIUCTRL_CPU1_AVS_PWD_CONTROL_CLRCFG_SHIFT 27
-#define BCHP_HIF_CPUBIUCTRL_CPU1_AVS_PWD_CONTROL_CLRCFG_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: CPU1_AVS_PWD_CONTROL :: RSEL [26:24] */
-#define BCHP_HIF_CPUBIUCTRL_CPU1_AVS_PWD_CONTROL_RSEL_MASK 0x07000000
-#define BCHP_HIF_CPUBIUCTRL_CPU1_AVS_PWD_CONTROL_RSEL_SHIFT 24
-#define BCHP_HIF_CPUBIUCTRL_CPU1_AVS_PWD_CONTROL_RSEL_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: CPU1_AVS_PWD_CONTROL :: CGFG [23:16] */
-#define BCHP_HIF_CPUBIUCTRL_CPU1_AVS_PWD_CONTROL_CGFG_MASK 0x00ff0000
-#define BCHP_HIF_CPUBIUCTRL_CPU1_AVS_PWD_CONTROL_CGFG_SHIFT 16
-#define BCHP_HIF_CPUBIUCTRL_CPU1_AVS_PWD_CONTROL_CGFG_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: CPU1_AVS_PWD_CONTROL :: ALERT [15:15] */
-#define BCHP_HIF_CPUBIUCTRL_CPU1_AVS_PWD_CONTROL_ALERT_MASK 0x00008000
-#define BCHP_HIF_CPUBIUCTRL_CPU1_AVS_PWD_CONTROL_ALERT_SHIFT 15
-#define BCHP_HIF_CPUBIUCTRL_CPU1_AVS_PWD_CONTROL_ALERT_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: CPU1_AVS_PWD_CONTROL :: reserved1 [14:09] */
-#define BCHP_HIF_CPUBIUCTRL_CPU1_AVS_PWD_CONTROL_reserved1_MASK 0x00007e00
-#define BCHP_HIF_CPUBIUCTRL_CPU1_AVS_PWD_CONTROL_reserved1_SHIFT 9
-
-/* HIF_CPUBIUCTRL :: CPU1_AVS_PWD_CONTROL :: PWD_TM_EN [08:08] */
-#define BCHP_HIF_CPUBIUCTRL_CPU1_AVS_PWD_CONTROL_PWD_TM_EN_MASK 0x00000100
-#define BCHP_HIF_CPUBIUCTRL_CPU1_AVS_PWD_CONTROL_PWD_TM_EN_SHIFT 8
-#define BCHP_HIF_CPUBIUCTRL_CPU1_AVS_PWD_CONTROL_PWD_TM_EN_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: CPU1_AVS_PWD_CONTROL :: START [07:02] */
-#define BCHP_HIF_CPUBIUCTRL_CPU1_AVS_PWD_CONTROL_START_MASK 0x000000fc
-#define BCHP_HIF_CPUBIUCTRL_CPU1_AVS_PWD_CONTROL_START_SHIFT 2
-#define BCHP_HIF_CPUBIUCTRL_CPU1_AVS_PWD_CONTROL_START_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: CPU1_AVS_PWD_CONTROL :: PWD_ALERT_SEL [01:01] */
-#define BCHP_HIF_CPUBIUCTRL_CPU1_AVS_PWD_CONTROL_PWD_ALERT_SEL_MASK 0x00000002
-#define BCHP_HIF_CPUBIUCTRL_CPU1_AVS_PWD_CONTROL_PWD_ALERT_SEL_SHIFT 1
-#define BCHP_HIF_CPUBIUCTRL_CPU1_AVS_PWD_CONTROL_PWD_ALERT_SEL_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: CPU1_AVS_PWD_CONTROL :: PWD_EN [00:00] */
-#define BCHP_HIF_CPUBIUCTRL_CPU1_AVS_PWD_CONTROL_PWD_EN_MASK 0x00000001
-#define BCHP_HIF_CPUBIUCTRL_CPU1_AVS_PWD_CONTROL_PWD_EN_SHIFT 0
-#define BCHP_HIF_CPUBIUCTRL_CPU1_AVS_PWD_CONTROL_PWD_EN_DEFAULT 0x00000000
-
-/***************************************************************************
- *CPU2_BPCM_ID - CPU2 BPCM ID Register
- ***************************************************************************/
-/* HIF_CPUBIUCTRL :: CPU2_BPCM_ID :: SW_strap [31:16] */
-#define BCHP_HIF_CPUBIUCTRL_CPU2_BPCM_ID_SW_strap_MASK 0xffff0000
-#define BCHP_HIF_CPUBIUCTRL_CPU2_BPCM_ID_SW_strap_SHIFT 16
-
-/* HIF_CPUBIUCTRL :: CPU2_BPCM_ID :: HW_revision [15:08] */
-#define BCHP_HIF_CPUBIUCTRL_CPU2_BPCM_ID_HW_revision_MASK 0x0000ff00
-#define BCHP_HIF_CPUBIUCTRL_CPU2_BPCM_ID_HW_revision_SHIFT 8
-
-/* HIF_CPUBIUCTRL :: CPU2_BPCM_ID :: PMB_ADDR [07:00] */
-#define BCHP_HIF_CPUBIUCTRL_CPU2_BPCM_ID_PMB_ADDR_MASK 0x000000ff
-#define BCHP_HIF_CPUBIUCTRL_CPU2_BPCM_ID_PMB_ADDR_SHIFT 0
-
-/***************************************************************************
- *CPU2_BPCM_CAPABILITY - CPU2 BPCM Capability Register
- ***************************************************************************/
-/* HIF_CPUBIUCTRL :: CPU2_BPCM_CAPABILITY :: reserved0 [31:08] */
-#define BCHP_HIF_CPUBIUCTRL_CPU2_BPCM_CAPABILITY_reserved0_MASK 0xffffff00
-#define BCHP_HIF_CPUBIUCTRL_CPU2_BPCM_CAPABILITY_reserved0_SHIFT 8
-
-/* HIF_CPUBIUCTRL :: CPU2_BPCM_CAPABILITY :: Number_of_zones [07:00] */
-#define BCHP_HIF_CPUBIUCTRL_CPU2_BPCM_CAPABILITY_Number_of_zones_MASK 0x000000ff
-#define BCHP_HIF_CPUBIUCTRL_CPU2_BPCM_CAPABILITY_Number_of_zones_SHIFT 0
-
-/***************************************************************************
- *CPU2_BPCM_CONTROL - CPU2 BPCM Control Register
- ***************************************************************************/
-/* HIF_CPUBIUCTRL :: CPU2_BPCM_CONTROL :: TbdField [31:00] */
-#define BCHP_HIF_CPUBIUCTRL_CPU2_BPCM_CONTROL_TbdField_MASK 0xffffffff
-#define BCHP_HIF_CPUBIUCTRL_CPU2_BPCM_CONTROL_TbdField_SHIFT 0
-
-/***************************************************************************
- *CPU2_BPCM_STATUS - CPU2 BPCM Status Register
- ***************************************************************************/
-/* HIF_CPUBIUCTRL :: CPU2_BPCM_STATUS :: reserved0 [31:01] */
-#define BCHP_HIF_CPUBIUCTRL_CPU2_BPCM_STATUS_reserved0_MASK 0xfffffffe
-#define BCHP_HIF_CPUBIUCTRL_CPU2_BPCM_STATUS_reserved0_SHIFT 1
-
-/* HIF_CPUBIUCTRL :: CPU2_BPCM_STATUS :: PWD_Alert [00:00] */
-#define BCHP_HIF_CPUBIUCTRL_CPU2_BPCM_STATUS_PWD_Alert_MASK 0x00000001
-#define BCHP_HIF_CPUBIUCTRL_CPU2_BPCM_STATUS_PWD_Alert_SHIFT 0
-
-/***************************************************************************
- *CPU2_AVS_ROSC_CONTROL - CPU2 Ring Oscillator Control Register
- ***************************************************************************/
-/* HIF_CPUBIUCTRL :: CPU2_AVS_ROSC_CONTROL :: Test_interval [31:16] */
-#define BCHP_HIF_CPUBIUCTRL_CPU2_AVS_ROSC_CONTROL_Test_interval_MASK 0xffff0000
-#define BCHP_HIF_CPUBIUCTRL_CPU2_AVS_ROSC_CONTROL_Test_interval_SHIFT 16
-#define BCHP_HIF_CPUBIUCTRL_CPU2_AVS_ROSC_CONTROL_Test_interval_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: CPU2_AVS_ROSC_CONTROL :: ALERT_H [15:15] */
-#define BCHP_HIF_CPUBIUCTRL_CPU2_AVS_ROSC_CONTROL_ALERT_H_MASK 0x00008000
-#define BCHP_HIF_CPUBIUCTRL_CPU2_AVS_ROSC_CONTROL_ALERT_H_SHIFT 15
-#define BCHP_HIF_CPUBIUCTRL_CPU2_AVS_ROSC_CONTROL_ALERT_H_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: CPU2_AVS_ROSC_CONTROL :: VALID_H [14:14] */
-#define BCHP_HIF_CPUBIUCTRL_CPU2_AVS_ROSC_CONTROL_VALID_H_MASK 0x00004000
-#define BCHP_HIF_CPUBIUCTRL_CPU2_AVS_ROSC_CONTROL_VALID_H_SHIFT 14
-#define BCHP_HIF_CPUBIUCTRL_CPU2_AVS_ROSC_CONTROL_VALID_H_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: CPU2_AVS_ROSC_CONTROL :: ALERT_S [13:13] */
-#define BCHP_HIF_CPUBIUCTRL_CPU2_AVS_ROSC_CONTROL_ALERT_S_MASK 0x00002000
-#define BCHP_HIF_CPUBIUCTRL_CPU2_AVS_ROSC_CONTROL_ALERT_S_SHIFT 13
-#define BCHP_HIF_CPUBIUCTRL_CPU2_AVS_ROSC_CONTROL_ALERT_S_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: CPU2_AVS_ROSC_CONTROL :: VALID_S [12:12] */
-#define BCHP_HIF_CPUBIUCTRL_CPU2_AVS_ROSC_CONTROL_VALID_S_MASK 0x00001000
-#define BCHP_HIF_CPUBIUCTRL_CPU2_AVS_ROSC_CONTROL_VALID_S_SHIFT 12
-#define BCHP_HIF_CPUBIUCTRL_CPU2_AVS_ROSC_CONTROL_VALID_S_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: CPU2_AVS_ROSC_CONTROL :: reserved0 [11:08] */
-#define BCHP_HIF_CPUBIUCTRL_CPU2_AVS_ROSC_CONTROL_reserved0_MASK 0x00000f00
-#define BCHP_HIF_CPUBIUCTRL_CPU2_AVS_ROSC_CONTROL_reserved0_SHIFT 8
-
-/* HIF_CPUBIUCTRL :: CPU2_AVS_ROSC_CONTROL :: CONTINUOUS_H [07:07] */
-#define BCHP_HIF_CPUBIUCTRL_CPU2_AVS_ROSC_CONTROL_CONTINUOUS_H_MASK 0x00000080
-#define BCHP_HIF_CPUBIUCTRL_CPU2_AVS_ROSC_CONTROL_CONTINUOUS_H_SHIFT 7
-#define BCHP_HIF_CPUBIUCTRL_CPU2_AVS_ROSC_CONTROL_CONTINUOUS_H_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: CPU2_AVS_ROSC_CONTROL :: CONTINUOUS_S [06:06] */
-#define BCHP_HIF_CPUBIUCTRL_CPU2_AVS_ROSC_CONTROL_CONTINUOUS_S_MASK 0x00000040
-#define BCHP_HIF_CPUBIUCTRL_CPU2_AVS_ROSC_CONTROL_CONTINUOUS_S_SHIFT 6
-#define BCHP_HIF_CPUBIUCTRL_CPU2_AVS_ROSC_CONTROL_CONTINUOUS_S_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: CPU2_AVS_ROSC_CONTROL :: THRSH_EN_H [05:05] */
-#define BCHP_HIF_CPUBIUCTRL_CPU2_AVS_ROSC_CONTROL_THRSH_EN_H_MASK 0x00000020
-#define BCHP_HIF_CPUBIUCTRL_CPU2_AVS_ROSC_CONTROL_THRSH_EN_H_SHIFT 5
-#define BCHP_HIF_CPUBIUCTRL_CPU2_AVS_ROSC_CONTROL_THRSH_EN_H_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: CPU2_AVS_ROSC_CONTROL :: THRSH_EN_S [04:04] */
-#define BCHP_HIF_CPUBIUCTRL_CPU2_AVS_ROSC_CONTROL_THRSH_EN_S_MASK 0x00000010
-#define BCHP_HIF_CPUBIUCTRL_CPU2_AVS_ROSC_CONTROL_THRSH_EN_S_SHIFT 4
-#define BCHP_HIF_CPUBIUCTRL_CPU2_AVS_ROSC_CONTROL_THRSH_EN_S_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: CPU2_AVS_ROSC_CONTROL :: ECTR_EN_H [03:03] */
-#define BCHP_HIF_CPUBIUCTRL_CPU2_AVS_ROSC_CONTROL_ECTR_EN_H_MASK 0x00000008
-#define BCHP_HIF_CPUBIUCTRL_CPU2_AVS_ROSC_CONTROL_ECTR_EN_H_SHIFT 3
-#define BCHP_HIF_CPUBIUCTRL_CPU2_AVS_ROSC_CONTROL_ECTR_EN_H_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: CPU2_AVS_ROSC_CONTROL :: ECTR_EN_S [02:02] */
-#define BCHP_HIF_CPUBIUCTRL_CPU2_AVS_ROSC_CONTROL_ECTR_EN_S_MASK 0x00000004
-#define BCHP_HIF_CPUBIUCTRL_CPU2_AVS_ROSC_CONTROL_ECTR_EN_S_SHIFT 2
-#define BCHP_HIF_CPUBIUCTRL_CPU2_AVS_ROSC_CONTROL_ECTR_EN_S_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: CPU2_AVS_ROSC_CONTROL :: RO_EN_H [01:01] */
-#define BCHP_HIF_CPUBIUCTRL_CPU2_AVS_ROSC_CONTROL_RO_EN_H_MASK 0x00000002
-#define BCHP_HIF_CPUBIUCTRL_CPU2_AVS_ROSC_CONTROL_RO_EN_H_SHIFT 1
-#define BCHP_HIF_CPUBIUCTRL_CPU2_AVS_ROSC_CONTROL_RO_EN_H_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: CPU2_AVS_ROSC_CONTROL :: RO_EN_S [00:00] */
-#define BCHP_HIF_CPUBIUCTRL_CPU2_AVS_ROSC_CONTROL_RO_EN_S_MASK 0x00000001
-#define BCHP_HIF_CPUBIUCTRL_CPU2_AVS_ROSC_CONTROL_RO_EN_S_SHIFT 0
-#define BCHP_HIF_CPUBIUCTRL_CPU2_AVS_ROSC_CONTROL_RO_EN_S_DEFAULT 0x00000000
-
-/***************************************************************************
- *CPU2_AVS_ROSC_THRESHOLD - CPU2 Event Counter Threshold Register
- ***************************************************************************/
-/* HIF_CPUBIUCTRL :: CPU2_AVS_ROSC_THRESHOLD :: THRESH_HI [31:16] */
-#define BCHP_HIF_CPUBIUCTRL_CPU2_AVS_ROSC_THRESHOLD_THRESH_HI_MASK 0xffff0000
-#define BCHP_HIF_CPUBIUCTRL_CPU2_AVS_ROSC_THRESHOLD_THRESH_HI_SHIFT 16
-#define BCHP_HIF_CPUBIUCTRL_CPU2_AVS_ROSC_THRESHOLD_THRESH_HI_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: CPU2_AVS_ROSC_THRESHOLD :: THRESH_LO [15:00] */
-#define BCHP_HIF_CPUBIUCTRL_CPU2_AVS_ROSC_THRESHOLD_THRESH_LO_MASK 0x0000ffff
-#define BCHP_HIF_CPUBIUCTRL_CPU2_AVS_ROSC_THRESHOLD_THRESH_LO_SHIFT 0
-#define BCHP_HIF_CPUBIUCTRL_CPU2_AVS_ROSC_THRESHOLD_THRESH_LO_DEFAULT 0x00000000
-
-/***************************************************************************
- *CPU2_AVS_ROSC_COUNT - CPU2 Event Counter Count Register
- ***************************************************************************/
-/* HIF_CPUBIUCTRL :: CPU2_AVS_ROSC_COUNT :: COUNT_H [31:16] */
-#define BCHP_HIF_CPUBIUCTRL_CPU2_AVS_ROSC_COUNT_COUNT_H_MASK 0xffff0000
-#define BCHP_HIF_CPUBIUCTRL_CPU2_AVS_ROSC_COUNT_COUNT_H_SHIFT 16
-#define BCHP_HIF_CPUBIUCTRL_CPU2_AVS_ROSC_COUNT_COUNT_H_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: CPU2_AVS_ROSC_COUNT :: COUNT_S [15:00] */
-#define BCHP_HIF_CPUBIUCTRL_CPU2_AVS_ROSC_COUNT_COUNT_S_MASK 0x0000ffff
-#define BCHP_HIF_CPUBIUCTRL_CPU2_AVS_ROSC_COUNT_COUNT_S_SHIFT 0
-#define BCHP_HIF_CPUBIUCTRL_CPU2_AVS_ROSC_COUNT_COUNT_S_DEFAULT 0x00000000
-
-/***************************************************************************
- *CPU2_AVS_PWD_CONTROL - CPU2 PWD control Register
- ***************************************************************************/
-/* HIF_CPUBIUCTRL :: CPU2_AVS_PWD_CONTROL :: reserved0 [31:30] */
-#define BCHP_HIF_CPUBIUCTRL_CPU2_AVS_PWD_CONTROL_reserved0_MASK 0xc0000000
-#define BCHP_HIF_CPUBIUCTRL_CPU2_AVS_PWD_CONTROL_reserved0_SHIFT 30
-
-/* HIF_CPUBIUCTRL :: CPU2_AVS_PWD_CONTROL :: CLRCFG [29:27] */
-#define BCHP_HIF_CPUBIUCTRL_CPU2_AVS_PWD_CONTROL_CLRCFG_MASK 0x38000000
-#define BCHP_HIF_CPUBIUCTRL_CPU2_AVS_PWD_CONTROL_CLRCFG_SHIFT 27
-#define BCHP_HIF_CPUBIUCTRL_CPU2_AVS_PWD_CONTROL_CLRCFG_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: CPU2_AVS_PWD_CONTROL :: RSEL [26:24] */
-#define BCHP_HIF_CPUBIUCTRL_CPU2_AVS_PWD_CONTROL_RSEL_MASK 0x07000000
-#define BCHP_HIF_CPUBIUCTRL_CPU2_AVS_PWD_CONTROL_RSEL_SHIFT 24
-#define BCHP_HIF_CPUBIUCTRL_CPU2_AVS_PWD_CONTROL_RSEL_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: CPU2_AVS_PWD_CONTROL :: CGFG [23:16] */
-#define BCHP_HIF_CPUBIUCTRL_CPU2_AVS_PWD_CONTROL_CGFG_MASK 0x00ff0000
-#define BCHP_HIF_CPUBIUCTRL_CPU2_AVS_PWD_CONTROL_CGFG_SHIFT 16
-#define BCHP_HIF_CPUBIUCTRL_CPU2_AVS_PWD_CONTROL_CGFG_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: CPU2_AVS_PWD_CONTROL :: ALERT [15:15] */
-#define BCHP_HIF_CPUBIUCTRL_CPU2_AVS_PWD_CONTROL_ALERT_MASK 0x00008000
-#define BCHP_HIF_CPUBIUCTRL_CPU2_AVS_PWD_CONTROL_ALERT_SHIFT 15
-#define BCHP_HIF_CPUBIUCTRL_CPU2_AVS_PWD_CONTROL_ALERT_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: CPU2_AVS_PWD_CONTROL :: reserved1 [14:09] */
-#define BCHP_HIF_CPUBIUCTRL_CPU2_AVS_PWD_CONTROL_reserved1_MASK 0x00007e00
-#define BCHP_HIF_CPUBIUCTRL_CPU2_AVS_PWD_CONTROL_reserved1_SHIFT 9
-
-/* HIF_CPUBIUCTRL :: CPU2_AVS_PWD_CONTROL :: PWD_TM_EN [08:08] */
-#define BCHP_HIF_CPUBIUCTRL_CPU2_AVS_PWD_CONTROL_PWD_TM_EN_MASK 0x00000100
-#define BCHP_HIF_CPUBIUCTRL_CPU2_AVS_PWD_CONTROL_PWD_TM_EN_SHIFT 8
-#define BCHP_HIF_CPUBIUCTRL_CPU2_AVS_PWD_CONTROL_PWD_TM_EN_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: CPU2_AVS_PWD_CONTROL :: START [07:02] */
-#define BCHP_HIF_CPUBIUCTRL_CPU2_AVS_PWD_CONTROL_START_MASK 0x000000fc
-#define BCHP_HIF_CPUBIUCTRL_CPU2_AVS_PWD_CONTROL_START_SHIFT 2
-#define BCHP_HIF_CPUBIUCTRL_CPU2_AVS_PWD_CONTROL_START_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: CPU2_AVS_PWD_CONTROL :: PWD_ALERT_SEL [01:01] */
-#define BCHP_HIF_CPUBIUCTRL_CPU2_AVS_PWD_CONTROL_PWD_ALERT_SEL_MASK 0x00000002
-#define BCHP_HIF_CPUBIUCTRL_CPU2_AVS_PWD_CONTROL_PWD_ALERT_SEL_SHIFT 1
-#define BCHP_HIF_CPUBIUCTRL_CPU2_AVS_PWD_CONTROL_PWD_ALERT_SEL_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: CPU2_AVS_PWD_CONTROL :: PWD_EN [00:00] */
-#define BCHP_HIF_CPUBIUCTRL_CPU2_AVS_PWD_CONTROL_PWD_EN_MASK 0x00000001
-#define BCHP_HIF_CPUBIUCTRL_CPU2_AVS_PWD_CONTROL_PWD_EN_SHIFT 0
-#define BCHP_HIF_CPUBIUCTRL_CPU2_AVS_PWD_CONTROL_PWD_EN_DEFAULT 0x00000000
-
-/***************************************************************************
- *CPU3_BPCM_ID - CPU3 BPCM ID Register
- ***************************************************************************/
-/* HIF_CPUBIUCTRL :: CPU3_BPCM_ID :: SW_strap [31:16] */
-#define BCHP_HIF_CPUBIUCTRL_CPU3_BPCM_ID_SW_strap_MASK 0xffff0000
-#define BCHP_HIF_CPUBIUCTRL_CPU3_BPCM_ID_SW_strap_SHIFT 16
-
-/* HIF_CPUBIUCTRL :: CPU3_BPCM_ID :: HW_revision [15:08] */
-#define BCHP_HIF_CPUBIUCTRL_CPU3_BPCM_ID_HW_revision_MASK 0x0000ff00
-#define BCHP_HIF_CPUBIUCTRL_CPU3_BPCM_ID_HW_revision_SHIFT 8
-
-/* HIF_CPUBIUCTRL :: CPU3_BPCM_ID :: PMB_ADDR [07:00] */
-#define BCHP_HIF_CPUBIUCTRL_CPU3_BPCM_ID_PMB_ADDR_MASK 0x000000ff
-#define BCHP_HIF_CPUBIUCTRL_CPU3_BPCM_ID_PMB_ADDR_SHIFT 0
-
-/***************************************************************************
- *CPU3_BPCM_CAPABILITY - CPU3 BPCM Capability Register
- ***************************************************************************/
-/* HIF_CPUBIUCTRL :: CPU3_BPCM_CAPABILITY :: reserved0 [31:08] */
-#define BCHP_HIF_CPUBIUCTRL_CPU3_BPCM_CAPABILITY_reserved0_MASK 0xffffff00
-#define BCHP_HIF_CPUBIUCTRL_CPU3_BPCM_CAPABILITY_reserved0_SHIFT 8
-
-/* HIF_CPUBIUCTRL :: CPU3_BPCM_CAPABILITY :: Number_of_zones [07:00] */
-#define BCHP_HIF_CPUBIUCTRL_CPU3_BPCM_CAPABILITY_Number_of_zones_MASK 0x000000ff
-#define BCHP_HIF_CPUBIUCTRL_CPU3_BPCM_CAPABILITY_Number_of_zones_SHIFT 0
-
-/***************************************************************************
- *CPU3_BPCM_CONTROL - CPU3 BPCM Control Register
- ***************************************************************************/
-/* HIF_CPUBIUCTRL :: CPU3_BPCM_CONTROL :: TbdField [31:00] */
-#define BCHP_HIF_CPUBIUCTRL_CPU3_BPCM_CONTROL_TbdField_MASK 0xffffffff
-#define BCHP_HIF_CPUBIUCTRL_CPU3_BPCM_CONTROL_TbdField_SHIFT 0
-
-/***************************************************************************
- *CPU3_BPCM_STATUS - CPU3 BPCM Status Register
- ***************************************************************************/
-/* HIF_CPUBIUCTRL :: CPU3_BPCM_STATUS :: reserved0 [31:01] */
-#define BCHP_HIF_CPUBIUCTRL_CPU3_BPCM_STATUS_reserved0_MASK 0xfffffffe
-#define BCHP_HIF_CPUBIUCTRL_CPU3_BPCM_STATUS_reserved0_SHIFT 1
-
-/* HIF_CPUBIUCTRL :: CPU3_BPCM_STATUS :: PWD_Alert [00:00] */
-#define BCHP_HIF_CPUBIUCTRL_CPU3_BPCM_STATUS_PWD_Alert_MASK 0x00000001
-#define BCHP_HIF_CPUBIUCTRL_CPU3_BPCM_STATUS_PWD_Alert_SHIFT 0
-
-/***************************************************************************
- *CPU3_AVS_ROSC_CONTROL - CPU3 Ring Oscillator Control Register
- ***************************************************************************/
-/* HIF_CPUBIUCTRL :: CPU3_AVS_ROSC_CONTROL :: Test_interval [31:16] */
-#define BCHP_HIF_CPUBIUCTRL_CPU3_AVS_ROSC_CONTROL_Test_interval_MASK 0xffff0000
-#define BCHP_HIF_CPUBIUCTRL_CPU3_AVS_ROSC_CONTROL_Test_interval_SHIFT 16
-#define BCHP_HIF_CPUBIUCTRL_CPU3_AVS_ROSC_CONTROL_Test_interval_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: CPU3_AVS_ROSC_CONTROL :: ALERT_H [15:15] */
-#define BCHP_HIF_CPUBIUCTRL_CPU3_AVS_ROSC_CONTROL_ALERT_H_MASK 0x00008000
-#define BCHP_HIF_CPUBIUCTRL_CPU3_AVS_ROSC_CONTROL_ALERT_H_SHIFT 15
-#define BCHP_HIF_CPUBIUCTRL_CPU3_AVS_ROSC_CONTROL_ALERT_H_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: CPU3_AVS_ROSC_CONTROL :: VALID_H [14:14] */
-#define BCHP_HIF_CPUBIUCTRL_CPU3_AVS_ROSC_CONTROL_VALID_H_MASK 0x00004000
-#define BCHP_HIF_CPUBIUCTRL_CPU3_AVS_ROSC_CONTROL_VALID_H_SHIFT 14
-#define BCHP_HIF_CPUBIUCTRL_CPU3_AVS_ROSC_CONTROL_VALID_H_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: CPU3_AVS_ROSC_CONTROL :: ALERT_S [13:13] */
-#define BCHP_HIF_CPUBIUCTRL_CPU3_AVS_ROSC_CONTROL_ALERT_S_MASK 0x00002000
-#define BCHP_HIF_CPUBIUCTRL_CPU3_AVS_ROSC_CONTROL_ALERT_S_SHIFT 13
-#define BCHP_HIF_CPUBIUCTRL_CPU3_AVS_ROSC_CONTROL_ALERT_S_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: CPU3_AVS_ROSC_CONTROL :: VALID_S [12:12] */
-#define BCHP_HIF_CPUBIUCTRL_CPU3_AVS_ROSC_CONTROL_VALID_S_MASK 0x00001000
-#define BCHP_HIF_CPUBIUCTRL_CPU3_AVS_ROSC_CONTROL_VALID_S_SHIFT 12
-#define BCHP_HIF_CPUBIUCTRL_CPU3_AVS_ROSC_CONTROL_VALID_S_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: CPU3_AVS_ROSC_CONTROL :: reserved0 [11:08] */
-#define BCHP_HIF_CPUBIUCTRL_CPU3_AVS_ROSC_CONTROL_reserved0_MASK 0x00000f00
-#define BCHP_HIF_CPUBIUCTRL_CPU3_AVS_ROSC_CONTROL_reserved0_SHIFT 8
-
-/* HIF_CPUBIUCTRL :: CPU3_AVS_ROSC_CONTROL :: CONTINUOUS_H [07:07] */
-#define BCHP_HIF_CPUBIUCTRL_CPU3_AVS_ROSC_CONTROL_CONTINUOUS_H_MASK 0x00000080
-#define BCHP_HIF_CPUBIUCTRL_CPU3_AVS_ROSC_CONTROL_CONTINUOUS_H_SHIFT 7
-#define BCHP_HIF_CPUBIUCTRL_CPU3_AVS_ROSC_CONTROL_CONTINUOUS_H_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: CPU3_AVS_ROSC_CONTROL :: CONTINUOUS_S [06:06] */
-#define BCHP_HIF_CPUBIUCTRL_CPU3_AVS_ROSC_CONTROL_CONTINUOUS_S_MASK 0x00000040
-#define BCHP_HIF_CPUBIUCTRL_CPU3_AVS_ROSC_CONTROL_CONTINUOUS_S_SHIFT 6
-#define BCHP_HIF_CPUBIUCTRL_CPU3_AVS_ROSC_CONTROL_CONTINUOUS_S_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: CPU3_AVS_ROSC_CONTROL :: THRSH_EN_H [05:05] */
-#define BCHP_HIF_CPUBIUCTRL_CPU3_AVS_ROSC_CONTROL_THRSH_EN_H_MASK 0x00000020
-#define BCHP_HIF_CPUBIUCTRL_CPU3_AVS_ROSC_CONTROL_THRSH_EN_H_SHIFT 5
-#define BCHP_HIF_CPUBIUCTRL_CPU3_AVS_ROSC_CONTROL_THRSH_EN_H_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: CPU3_AVS_ROSC_CONTROL :: THRSH_EN_S [04:04] */
-#define BCHP_HIF_CPUBIUCTRL_CPU3_AVS_ROSC_CONTROL_THRSH_EN_S_MASK 0x00000010
-#define BCHP_HIF_CPUBIUCTRL_CPU3_AVS_ROSC_CONTROL_THRSH_EN_S_SHIFT 4
-#define BCHP_HIF_CPUBIUCTRL_CPU3_AVS_ROSC_CONTROL_THRSH_EN_S_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: CPU3_AVS_ROSC_CONTROL :: ECTR_EN_H [03:03] */
-#define BCHP_HIF_CPUBIUCTRL_CPU3_AVS_ROSC_CONTROL_ECTR_EN_H_MASK 0x00000008
-#define BCHP_HIF_CPUBIUCTRL_CPU3_AVS_ROSC_CONTROL_ECTR_EN_H_SHIFT 3
-#define BCHP_HIF_CPUBIUCTRL_CPU3_AVS_ROSC_CONTROL_ECTR_EN_H_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: CPU3_AVS_ROSC_CONTROL :: ECTR_EN_S [02:02] */
-#define BCHP_HIF_CPUBIUCTRL_CPU3_AVS_ROSC_CONTROL_ECTR_EN_S_MASK 0x00000004
-#define BCHP_HIF_CPUBIUCTRL_CPU3_AVS_ROSC_CONTROL_ECTR_EN_S_SHIFT 2
-#define BCHP_HIF_CPUBIUCTRL_CPU3_AVS_ROSC_CONTROL_ECTR_EN_S_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: CPU3_AVS_ROSC_CONTROL :: RO_EN_H [01:01] */
-#define BCHP_HIF_CPUBIUCTRL_CPU3_AVS_ROSC_CONTROL_RO_EN_H_MASK 0x00000002
-#define BCHP_HIF_CPUBIUCTRL_CPU3_AVS_ROSC_CONTROL_RO_EN_H_SHIFT 1
-#define BCHP_HIF_CPUBIUCTRL_CPU3_AVS_ROSC_CONTROL_RO_EN_H_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: CPU3_AVS_ROSC_CONTROL :: RO_EN_S [00:00] */
-#define BCHP_HIF_CPUBIUCTRL_CPU3_AVS_ROSC_CONTROL_RO_EN_S_MASK 0x00000001
-#define BCHP_HIF_CPUBIUCTRL_CPU3_AVS_ROSC_CONTROL_RO_EN_S_SHIFT 0
-#define BCHP_HIF_CPUBIUCTRL_CPU3_AVS_ROSC_CONTROL_RO_EN_S_DEFAULT 0x00000000
-
-/***************************************************************************
- *CPU3_AVS_ROSC_THRESHOLD - CPU3 Event Counter Threshold Register
- ***************************************************************************/
-/* HIF_CPUBIUCTRL :: CPU3_AVS_ROSC_THRESHOLD :: THRESH_HI [31:16] */
-#define BCHP_HIF_CPUBIUCTRL_CPU3_AVS_ROSC_THRESHOLD_THRESH_HI_MASK 0xffff0000
-#define BCHP_HIF_CPUBIUCTRL_CPU3_AVS_ROSC_THRESHOLD_THRESH_HI_SHIFT 16
-#define BCHP_HIF_CPUBIUCTRL_CPU3_AVS_ROSC_THRESHOLD_THRESH_HI_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: CPU3_AVS_ROSC_THRESHOLD :: THRESH_LO [15:00] */
-#define BCHP_HIF_CPUBIUCTRL_CPU3_AVS_ROSC_THRESHOLD_THRESH_LO_MASK 0x0000ffff
-#define BCHP_HIF_CPUBIUCTRL_CPU3_AVS_ROSC_THRESHOLD_THRESH_LO_SHIFT 0
-#define BCHP_HIF_CPUBIUCTRL_CPU3_AVS_ROSC_THRESHOLD_THRESH_LO_DEFAULT 0x00000000
-
-/***************************************************************************
- *CPU3_AVS_ROSC_COUNT - CPU3 Event Counter Count Register
- ***************************************************************************/
-/* HIF_CPUBIUCTRL :: CPU3_AVS_ROSC_COUNT :: COUNT_H [31:16] */
-#define BCHP_HIF_CPUBIUCTRL_CPU3_AVS_ROSC_COUNT_COUNT_H_MASK 0xffff0000
-#define BCHP_HIF_CPUBIUCTRL_CPU3_AVS_ROSC_COUNT_COUNT_H_SHIFT 16
-#define BCHP_HIF_CPUBIUCTRL_CPU3_AVS_ROSC_COUNT_COUNT_H_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: CPU3_AVS_ROSC_COUNT :: COUNT_S [15:00] */
-#define BCHP_HIF_CPUBIUCTRL_CPU3_AVS_ROSC_COUNT_COUNT_S_MASK 0x0000ffff
-#define BCHP_HIF_CPUBIUCTRL_CPU3_AVS_ROSC_COUNT_COUNT_S_SHIFT 0
-#define BCHP_HIF_CPUBIUCTRL_CPU3_AVS_ROSC_COUNT_COUNT_S_DEFAULT 0x00000000
-
-/***************************************************************************
- *CPU3_AVS_PWD_CONTROL - CPU3 PWD control Register
- ***************************************************************************/
-/* HIF_CPUBIUCTRL :: CPU3_AVS_PWD_CONTROL :: reserved0 [31:30] */
-#define BCHP_HIF_CPUBIUCTRL_CPU3_AVS_PWD_CONTROL_reserved0_MASK 0xc0000000
-#define BCHP_HIF_CPUBIUCTRL_CPU3_AVS_PWD_CONTROL_reserved0_SHIFT 30
-
-/* HIF_CPUBIUCTRL :: CPU3_AVS_PWD_CONTROL :: CLRCFG [29:27] */
-#define BCHP_HIF_CPUBIUCTRL_CPU3_AVS_PWD_CONTROL_CLRCFG_MASK 0x38000000
-#define BCHP_HIF_CPUBIUCTRL_CPU3_AVS_PWD_CONTROL_CLRCFG_SHIFT 27
-#define BCHP_HIF_CPUBIUCTRL_CPU3_AVS_PWD_CONTROL_CLRCFG_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: CPU3_AVS_PWD_CONTROL :: RSEL [26:24] */
-#define BCHP_HIF_CPUBIUCTRL_CPU3_AVS_PWD_CONTROL_RSEL_MASK 0x07000000
-#define BCHP_HIF_CPUBIUCTRL_CPU3_AVS_PWD_CONTROL_RSEL_SHIFT 24
-#define BCHP_HIF_CPUBIUCTRL_CPU3_AVS_PWD_CONTROL_RSEL_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: CPU3_AVS_PWD_CONTROL :: CGFG [23:16] */
-#define BCHP_HIF_CPUBIUCTRL_CPU3_AVS_PWD_CONTROL_CGFG_MASK 0x00ff0000
-#define BCHP_HIF_CPUBIUCTRL_CPU3_AVS_PWD_CONTROL_CGFG_SHIFT 16
-#define BCHP_HIF_CPUBIUCTRL_CPU3_AVS_PWD_CONTROL_CGFG_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: CPU3_AVS_PWD_CONTROL :: ALERT [15:15] */
-#define BCHP_HIF_CPUBIUCTRL_CPU3_AVS_PWD_CONTROL_ALERT_MASK 0x00008000
-#define BCHP_HIF_CPUBIUCTRL_CPU3_AVS_PWD_CONTROL_ALERT_SHIFT 15
-#define BCHP_HIF_CPUBIUCTRL_CPU3_AVS_PWD_CONTROL_ALERT_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: CPU3_AVS_PWD_CONTROL :: reserved1 [14:09] */
-#define BCHP_HIF_CPUBIUCTRL_CPU3_AVS_PWD_CONTROL_reserved1_MASK 0x00007e00
-#define BCHP_HIF_CPUBIUCTRL_CPU3_AVS_PWD_CONTROL_reserved1_SHIFT 9
-
-/* HIF_CPUBIUCTRL :: CPU3_AVS_PWD_CONTROL :: PWD_TM_EN [08:08] */
-#define BCHP_HIF_CPUBIUCTRL_CPU3_AVS_PWD_CONTROL_PWD_TM_EN_MASK 0x00000100
-#define BCHP_HIF_CPUBIUCTRL_CPU3_AVS_PWD_CONTROL_PWD_TM_EN_SHIFT 8
-#define BCHP_HIF_CPUBIUCTRL_CPU3_AVS_PWD_CONTROL_PWD_TM_EN_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: CPU3_AVS_PWD_CONTROL :: START [07:02] */
-#define BCHP_HIF_CPUBIUCTRL_CPU3_AVS_PWD_CONTROL_START_MASK 0x000000fc
-#define BCHP_HIF_CPUBIUCTRL_CPU3_AVS_PWD_CONTROL_START_SHIFT 2
-#define BCHP_HIF_CPUBIUCTRL_CPU3_AVS_PWD_CONTROL_START_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: CPU3_AVS_PWD_CONTROL :: PWD_ALERT_SEL [01:01] */
-#define BCHP_HIF_CPUBIUCTRL_CPU3_AVS_PWD_CONTROL_PWD_ALERT_SEL_MASK 0x00000002
-#define BCHP_HIF_CPUBIUCTRL_CPU3_AVS_PWD_CONTROL_PWD_ALERT_SEL_SHIFT 1
-#define BCHP_HIF_CPUBIUCTRL_CPU3_AVS_PWD_CONTROL_PWD_ALERT_SEL_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: CPU3_AVS_PWD_CONTROL :: PWD_EN [00:00] */
-#define BCHP_HIF_CPUBIUCTRL_CPU3_AVS_PWD_CONTROL_PWD_EN_MASK 0x00000001
-#define BCHP_HIF_CPUBIUCTRL_CPU3_AVS_PWD_CONTROL_PWD_EN_SHIFT 0
-#define BCHP_HIF_CPUBIUCTRL_CPU3_AVS_PWD_CONTROL_PWD_EN_DEFAULT 0x00000000
-
-/***************************************************************************
- *L2BIU_BPCM_ID - L2BIU BPCM ID Register
- ***************************************************************************/
-/* HIF_CPUBIUCTRL :: L2BIU_BPCM_ID :: SW_strap [31:16] */
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_BPCM_ID_SW_strap_MASK 0xffff0000
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_BPCM_ID_SW_strap_SHIFT 16
-
-/* HIF_CPUBIUCTRL :: L2BIU_BPCM_ID :: HW_revision [15:08] */
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_BPCM_ID_HW_revision_MASK 0x0000ff00
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_BPCM_ID_HW_revision_SHIFT 8
-
-/* HIF_CPUBIUCTRL :: L2BIU_BPCM_ID :: PMB_ADDR [07:00] */
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_BPCM_ID_PMB_ADDR_MASK 0x000000ff
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_BPCM_ID_PMB_ADDR_SHIFT 0
-
-/***************************************************************************
- *L2BIU_BPCM_CAPABILITY - L2BIU BPCM Capability Register
- ***************************************************************************/
-/* HIF_CPUBIUCTRL :: L2BIU_BPCM_CAPABILITY :: reserved0 [31:08] */
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_BPCM_CAPABILITY_reserved0_MASK 0xffffff00
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_BPCM_CAPABILITY_reserved0_SHIFT 8
-
-/* HIF_CPUBIUCTRL :: L2BIU_BPCM_CAPABILITY :: Number_of_zones [07:00] */
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_BPCM_CAPABILITY_Number_of_zones_MASK 0x000000ff
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_BPCM_CAPABILITY_Number_of_zones_SHIFT 0
-
-/***************************************************************************
- *L2BIU_BPCM_CONTROL - L2BIU BPCM Control Register
- ***************************************************************************/
-/* HIF_CPUBIUCTRL :: L2BIU_BPCM_CONTROL :: TbdField [31:00] */
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_BPCM_CONTROL_TbdField_MASK 0xffffffff
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_BPCM_CONTROL_TbdField_SHIFT 0
-
-/***************************************************************************
- *L2BIU_BPCM_STATUS - L2BIU BPCM Status Register
- ***************************************************************************/
-/* HIF_CPUBIUCTRL :: L2BIU_BPCM_STATUS :: reserved0 [31:01] */
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_BPCM_STATUS_reserved0_MASK 0xfffffffe
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_BPCM_STATUS_reserved0_SHIFT 1
-
-/* HIF_CPUBIUCTRL :: L2BIU_BPCM_STATUS :: PWD_Alert [00:00] */
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_BPCM_STATUS_PWD_Alert_MASK 0x00000001
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_BPCM_STATUS_PWD_Alert_SHIFT 0
-
-/***************************************************************************
- *L2BIU_AVS_ROSC_CONTROL - L2BIU Ring Oscillator Control Register
- ***************************************************************************/
-/* HIF_CPUBIUCTRL :: L2BIU_AVS_ROSC_CONTROL :: Test_interval [31:16] */
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_AVS_ROSC_CONTROL_Test_interval_MASK 0xffff0000
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_AVS_ROSC_CONTROL_Test_interval_SHIFT 16
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_AVS_ROSC_CONTROL_Test_interval_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: L2BIU_AVS_ROSC_CONTROL :: ALERT_H [15:15] */
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_AVS_ROSC_CONTROL_ALERT_H_MASK 0x00008000
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_AVS_ROSC_CONTROL_ALERT_H_SHIFT 15
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_AVS_ROSC_CONTROL_ALERT_H_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: L2BIU_AVS_ROSC_CONTROL :: VALID_H [14:14] */
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_AVS_ROSC_CONTROL_VALID_H_MASK 0x00004000
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_AVS_ROSC_CONTROL_VALID_H_SHIFT 14
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_AVS_ROSC_CONTROL_VALID_H_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: L2BIU_AVS_ROSC_CONTROL :: ALERT_S [13:13] */
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_AVS_ROSC_CONTROL_ALERT_S_MASK 0x00002000
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_AVS_ROSC_CONTROL_ALERT_S_SHIFT 13
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_AVS_ROSC_CONTROL_ALERT_S_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: L2BIU_AVS_ROSC_CONTROL :: VALID_S [12:12] */
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_AVS_ROSC_CONTROL_VALID_S_MASK 0x00001000
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_AVS_ROSC_CONTROL_VALID_S_SHIFT 12
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_AVS_ROSC_CONTROL_VALID_S_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: L2BIU_AVS_ROSC_CONTROL :: reserved0 [11:08] */
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_AVS_ROSC_CONTROL_reserved0_MASK 0x00000f00
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_AVS_ROSC_CONTROL_reserved0_SHIFT 8
-
-/* HIF_CPUBIUCTRL :: L2BIU_AVS_ROSC_CONTROL :: CONTINUOUS_H [07:07] */
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_AVS_ROSC_CONTROL_CONTINUOUS_H_MASK 0x00000080
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_AVS_ROSC_CONTROL_CONTINUOUS_H_SHIFT 7
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_AVS_ROSC_CONTROL_CONTINUOUS_H_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: L2BIU_AVS_ROSC_CONTROL :: CONTINUOUS_S [06:06] */
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_AVS_ROSC_CONTROL_CONTINUOUS_S_MASK 0x00000040
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_AVS_ROSC_CONTROL_CONTINUOUS_S_SHIFT 6
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_AVS_ROSC_CONTROL_CONTINUOUS_S_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: L2BIU_AVS_ROSC_CONTROL :: THRSH_EN_H [05:05] */
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_AVS_ROSC_CONTROL_THRSH_EN_H_MASK 0x00000020
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_AVS_ROSC_CONTROL_THRSH_EN_H_SHIFT 5
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_AVS_ROSC_CONTROL_THRSH_EN_H_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: L2BIU_AVS_ROSC_CONTROL :: THRSH_EN_S [04:04] */
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_AVS_ROSC_CONTROL_THRSH_EN_S_MASK 0x00000010
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_AVS_ROSC_CONTROL_THRSH_EN_S_SHIFT 4
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_AVS_ROSC_CONTROL_THRSH_EN_S_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: L2BIU_AVS_ROSC_CONTROL :: ECTR_EN_H [03:03] */
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_AVS_ROSC_CONTROL_ECTR_EN_H_MASK 0x00000008
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_AVS_ROSC_CONTROL_ECTR_EN_H_SHIFT 3
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_AVS_ROSC_CONTROL_ECTR_EN_H_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: L2BIU_AVS_ROSC_CONTROL :: ECTR_EN_S [02:02] */
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_AVS_ROSC_CONTROL_ECTR_EN_S_MASK 0x00000004
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_AVS_ROSC_CONTROL_ECTR_EN_S_SHIFT 2
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_AVS_ROSC_CONTROL_ECTR_EN_S_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: L2BIU_AVS_ROSC_CONTROL :: RO_EN_H [01:01] */
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_AVS_ROSC_CONTROL_RO_EN_H_MASK 0x00000002
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_AVS_ROSC_CONTROL_RO_EN_H_SHIFT 1
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_AVS_ROSC_CONTROL_RO_EN_H_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: L2BIU_AVS_ROSC_CONTROL :: RO_EN_S [00:00] */
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_AVS_ROSC_CONTROL_RO_EN_S_MASK 0x00000001
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_AVS_ROSC_CONTROL_RO_EN_S_SHIFT 0
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_AVS_ROSC_CONTROL_RO_EN_S_DEFAULT 0x00000000
-
-/***************************************************************************
- *L2BIU_AVS_ROSC_THRESHOLD - L2BIU Event Counter Threshold Register
- ***************************************************************************/
-/* HIF_CPUBIUCTRL :: L2BIU_AVS_ROSC_THRESHOLD :: THRESH_HI [31:16] */
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_AVS_ROSC_THRESHOLD_THRESH_HI_MASK 0xffff0000
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_AVS_ROSC_THRESHOLD_THRESH_HI_SHIFT 16
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_AVS_ROSC_THRESHOLD_THRESH_HI_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: L2BIU_AVS_ROSC_THRESHOLD :: THRESH_LO [15:00] */
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_AVS_ROSC_THRESHOLD_THRESH_LO_MASK 0x0000ffff
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_AVS_ROSC_THRESHOLD_THRESH_LO_SHIFT 0
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_AVS_ROSC_THRESHOLD_THRESH_LO_DEFAULT 0x00000000
-
-/***************************************************************************
- *L2BIU_AVS_ROSC_COUNT - L2BIU Event Counter Count Register
- ***************************************************************************/
-/* HIF_CPUBIUCTRL :: L2BIU_AVS_ROSC_COUNT :: COUNT_H [31:16] */
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_AVS_ROSC_COUNT_COUNT_H_MASK 0xffff0000
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_AVS_ROSC_COUNT_COUNT_H_SHIFT 16
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_AVS_ROSC_COUNT_COUNT_H_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: L2BIU_AVS_ROSC_COUNT :: COUNT_S [15:00] */
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_AVS_ROSC_COUNT_COUNT_S_MASK 0x0000ffff
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_AVS_ROSC_COUNT_COUNT_S_SHIFT 0
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_AVS_ROSC_COUNT_COUNT_S_DEFAULT 0x00000000
-
-/***************************************************************************
- *L2BIU_AVS_PWD_CONTROL - L2BIU PWD control Register
- ***************************************************************************/
-/* HIF_CPUBIUCTRL :: L2BIU_AVS_PWD_CONTROL :: reserved0 [31:30] */
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_AVS_PWD_CONTROL_reserved0_MASK 0xc0000000
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_AVS_PWD_CONTROL_reserved0_SHIFT 30
-
-/* HIF_CPUBIUCTRL :: L2BIU_AVS_PWD_CONTROL :: CLRCFG [29:27] */
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_AVS_PWD_CONTROL_CLRCFG_MASK 0x38000000
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_AVS_PWD_CONTROL_CLRCFG_SHIFT 27
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_AVS_PWD_CONTROL_CLRCFG_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: L2BIU_AVS_PWD_CONTROL :: RSEL [26:24] */
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_AVS_PWD_CONTROL_RSEL_MASK 0x07000000
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_AVS_PWD_CONTROL_RSEL_SHIFT 24
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_AVS_PWD_CONTROL_RSEL_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: L2BIU_AVS_PWD_CONTROL :: CGFG [23:16] */
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_AVS_PWD_CONTROL_CGFG_MASK 0x00ff0000
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_AVS_PWD_CONTROL_CGFG_SHIFT 16
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_AVS_PWD_CONTROL_CGFG_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: L2BIU_AVS_PWD_CONTROL :: ALERT [15:15] */
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_AVS_PWD_CONTROL_ALERT_MASK 0x00008000
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_AVS_PWD_CONTROL_ALERT_SHIFT 15
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_AVS_PWD_CONTROL_ALERT_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: L2BIU_AVS_PWD_CONTROL :: reserved1 [14:09] */
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_AVS_PWD_CONTROL_reserved1_MASK 0x00007e00
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_AVS_PWD_CONTROL_reserved1_SHIFT 9
-
-/* HIF_CPUBIUCTRL :: L2BIU_AVS_PWD_CONTROL :: PWD_TM_EN [08:08] */
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_AVS_PWD_CONTROL_PWD_TM_EN_MASK 0x00000100
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_AVS_PWD_CONTROL_PWD_TM_EN_SHIFT 8
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_AVS_PWD_CONTROL_PWD_TM_EN_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: L2BIU_AVS_PWD_CONTROL :: START [07:02] */
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_AVS_PWD_CONTROL_START_MASK 0x000000fc
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_AVS_PWD_CONTROL_START_SHIFT 2
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_AVS_PWD_CONTROL_START_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: L2BIU_AVS_PWD_CONTROL :: PWD_ALERT_SEL [01:01] */
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_AVS_PWD_CONTROL_PWD_ALERT_SEL_MASK 0x00000002
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_AVS_PWD_CONTROL_PWD_ALERT_SEL_SHIFT 1
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_AVS_PWD_CONTROL_PWD_ALERT_SEL_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: L2BIU_AVS_PWD_CONTROL :: PWD_EN [00:00] */
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_AVS_PWD_CONTROL_PWD_EN_MASK 0x00000001
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_AVS_PWD_CONTROL_PWD_EN_SHIFT 0
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_AVS_PWD_CONTROL_PWD_EN_DEFAULT 0x00000000
-
-/***************************************************************************
- *CPU_RESET_CONFIG_REG - CPU Reset Configuration Register
- ***************************************************************************/
-/* HIF_CPUBIUCTRL :: CPU_RESET_CONFIG_REG :: reserved0 [31:04] */
-#define BCHP_HIF_CPUBIUCTRL_CPU_RESET_CONFIG_REG_reserved0_MASK 0xfffffff0
-#define BCHP_HIF_CPUBIUCTRL_CPU_RESET_CONFIG_REG_reserved0_SHIFT 4
-
-/* HIF_CPUBIUCTRL :: CPU_RESET_CONFIG_REG :: CPU3_RESET [03:03] */
-#define BCHP_HIF_CPUBIUCTRL_CPU_RESET_CONFIG_REG_CPU3_RESET_MASK 0x00000008
-#define BCHP_HIF_CPUBIUCTRL_CPU_RESET_CONFIG_REG_CPU3_RESET_SHIFT 3
-#define BCHP_HIF_CPUBIUCTRL_CPU_RESET_CONFIG_REG_CPU3_RESET_DEFAULT 0x00000001
-
-/* HIF_CPUBIUCTRL :: CPU_RESET_CONFIG_REG :: CPU2_RESET [02:02] */
-#define BCHP_HIF_CPUBIUCTRL_CPU_RESET_CONFIG_REG_CPU2_RESET_MASK 0x00000004
-#define BCHP_HIF_CPUBIUCTRL_CPU_RESET_CONFIG_REG_CPU2_RESET_SHIFT 2
-#define BCHP_HIF_CPUBIUCTRL_CPU_RESET_CONFIG_REG_CPU2_RESET_DEFAULT 0x00000001
-
-/* HIF_CPUBIUCTRL :: CPU_RESET_CONFIG_REG :: CPU1_RESET [01:01] */
-#define BCHP_HIF_CPUBIUCTRL_CPU_RESET_CONFIG_REG_CPU1_RESET_MASK 0x00000002
-#define BCHP_HIF_CPUBIUCTRL_CPU_RESET_CONFIG_REG_CPU1_RESET_SHIFT 1
-#define BCHP_HIF_CPUBIUCTRL_CPU_RESET_CONFIG_REG_CPU1_RESET_DEFAULT 0x00000001
-
-/* HIF_CPUBIUCTRL :: CPU_RESET_CONFIG_REG :: CPU0_RESET [00:00] */
-#define BCHP_HIF_CPUBIUCTRL_CPU_RESET_CONFIG_REG_CPU0_RESET_MASK 0x00000001
-#define BCHP_HIF_CPUBIUCTRL_CPU_RESET_CONFIG_REG_CPU0_RESET_SHIFT 0
-#define BCHP_HIF_CPUBIUCTRL_CPU_RESET_CONFIG_REG_CPU0_RESET_DEFAULT 0x00000000
-
-/***************************************************************************
- *CPU_CLOCK_CONFIG_REG - CPU Clock Configuration Register
- ***************************************************************************/
-/* HIF_CPUBIUCTRL :: CPU_CLOCK_CONFIG_REG :: reserved0 [31:06] */
-#define BCHP_HIF_CPUBIUCTRL_CPU_CLOCK_CONFIG_REG_reserved0_MASK 0xffffffc0
-#define BCHP_HIF_CPUBIUCTRL_CPU_CLOCK_CONFIG_REG_reserved0_SHIFT 6
-
-/* HIF_CPUBIUCTRL :: CPU_CLOCK_CONFIG_REG :: UBUS_CLK_EN [05:05] */
-#define BCHP_HIF_CPUBIUCTRL_CPU_CLOCK_CONFIG_REG_UBUS_CLK_EN_MASK 0x00000020
-#define BCHP_HIF_CPUBIUCTRL_CPU_CLOCK_CONFIG_REG_UBUS_CLK_EN_SHIFT 5
-#define BCHP_HIF_CPUBIUCTRL_CPU_CLOCK_CONFIG_REG_UBUS_CLK_EN_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: CPU_CLOCK_CONFIG_REG :: SAFE_CLK_MODE [04:04] */
-#define BCHP_HIF_CPUBIUCTRL_CPU_CLOCK_CONFIG_REG_SAFE_CLK_MODE_MASK 0x00000010
-#define BCHP_HIF_CPUBIUCTRL_CPU_CLOCK_CONFIG_REG_SAFE_CLK_MODE_SHIFT 4
-#define BCHP_HIF_CPUBIUCTRL_CPU_CLOCK_CONFIG_REG_SAFE_CLK_MODE_DEFAULT 0x00000001
-
-/* HIF_CPUBIUCTRL :: CPU_CLOCK_CONFIG_REG :: CLK_RATIO [03:00] */
-#define BCHP_HIF_CPUBIUCTRL_CPU_CLOCK_CONFIG_REG_CLK_RATIO_MASK 0x0000000f
-#define BCHP_HIF_CPUBIUCTRL_CPU_CLOCK_CONFIG_REG_CLK_RATIO_SHIFT 0
-#define BCHP_HIF_CPUBIUCTRL_CPU_CLOCK_CONFIG_REG_CLK_RATIO_DEFAULT 0x00000001
-
-/***************************************************************************
- *CPU_MISC_CONFIG_REG - CPU Miscellaneous Configuration Register
- ***************************************************************************/
-/* HIF_CPUBIUCTRL :: CPU_MISC_CONFIG_REG :: MiscCommands [31:08] */
-#define BCHP_HIF_CPUBIUCTRL_CPU_MISC_CONFIG_REG_MiscCommands_MASK 0xffffff00
-#define BCHP_HIF_CPUBIUCTRL_CPU_MISC_CONFIG_REG_MiscCommands_SHIFT 8
-#define BCHP_HIF_CPUBIUCTRL_CPU_MISC_CONFIG_REG_MiscCommands_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: CPU_MISC_CONFIG_REG :: ENABLE_PMUIRQ [07:04] */
-#define BCHP_HIF_CPUBIUCTRL_CPU_MISC_CONFIG_REG_ENABLE_PMUIRQ_MASK 0x000000f0
-#define BCHP_HIF_CPUBIUCTRL_CPU_MISC_CONFIG_REG_ENABLE_PMUIRQ_SHIFT 4
-#define BCHP_HIF_CPUBIUCTRL_CPU_MISC_CONFIG_REG_ENABLE_PMUIRQ_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: CPU_MISC_CONFIG_REG :: VINITHI [03:00] */
-#define BCHP_HIF_CPUBIUCTRL_CPU_MISC_CONFIG_REG_VINITHI_MASK 0x0000000f
-#define BCHP_HIF_CPUBIUCTRL_CPU_MISC_CONFIG_REG_VINITHI_SHIFT 0
-#define BCHP_HIF_CPUBIUCTRL_CPU_MISC_CONFIG_REG_VINITHI_DEFAULT 0x0000000f
-
-/***************************************************************************
- *CPU_CREDIT_REG - CPU Request Credit Register
- ***************************************************************************/
-/* HIF_CPUBIUCTRL :: CPU_CREDIT_REG :: reserved0 [31:24] */
-#define BCHP_HIF_CPUBIUCTRL_CPU_CREDIT_REG_reserved0_MASK 0xff000000
-#define BCHP_HIF_CPUBIUCTRL_CPU_CREDIT_REG_reserved0_SHIFT 24
-
-/* HIF_CPUBIUCTRL :: CPU_CREDIT_REG :: MCP2_WRITE_CRED [23:20] */
-#define BCHP_HIF_CPUBIUCTRL_CPU_CREDIT_REG_MCP2_WRITE_CRED_MASK 0x00f00000
-#define BCHP_HIF_CPUBIUCTRL_CPU_CREDIT_REG_MCP2_WRITE_CRED_SHIFT 20
-#define BCHP_HIF_CPUBIUCTRL_CPU_CREDIT_REG_MCP2_WRITE_CRED_DEFAULT 0x00000004
-
-/* HIF_CPUBIUCTRL :: CPU_CREDIT_REG :: MCP2_READ_CRED [19:16] */
-#define BCHP_HIF_CPUBIUCTRL_CPU_CREDIT_REG_MCP2_READ_CRED_MASK 0x000f0000
-#define BCHP_HIF_CPUBIUCTRL_CPU_CREDIT_REG_MCP2_READ_CRED_SHIFT 16
-#define BCHP_HIF_CPUBIUCTRL_CPU_CREDIT_REG_MCP2_READ_CRED_DEFAULT 0x00000004
-
-/* HIF_CPUBIUCTRL :: CPU_CREDIT_REG :: MCP1_WRITE_CRED [15:12] */
-#define BCHP_HIF_CPUBIUCTRL_CPU_CREDIT_REG_MCP1_WRITE_CRED_MASK 0x0000f000
-#define BCHP_HIF_CPUBIUCTRL_CPU_CREDIT_REG_MCP1_WRITE_CRED_SHIFT 12
-#define BCHP_HIF_CPUBIUCTRL_CPU_CREDIT_REG_MCP1_WRITE_CRED_DEFAULT 0x00000004
-
-/* HIF_CPUBIUCTRL :: CPU_CREDIT_REG :: MCP1_READ_CRED [11:08] */
-#define BCHP_HIF_CPUBIUCTRL_CPU_CREDIT_REG_MCP1_READ_CRED_MASK 0x00000f00
-#define BCHP_HIF_CPUBIUCTRL_CPU_CREDIT_REG_MCP1_READ_CRED_SHIFT 8
-#define BCHP_HIF_CPUBIUCTRL_CPU_CREDIT_REG_MCP1_READ_CRED_DEFAULT 0x00000004
-
-/* HIF_CPUBIUCTRL :: CPU_CREDIT_REG :: MCP0_WRITE_CRED [07:04] */
-#define BCHP_HIF_CPUBIUCTRL_CPU_CREDIT_REG_MCP0_WRITE_CRED_MASK 0x000000f0
-#define BCHP_HIF_CPUBIUCTRL_CPU_CREDIT_REG_MCP0_WRITE_CRED_SHIFT 4
-#define BCHP_HIF_CPUBIUCTRL_CPU_CREDIT_REG_MCP0_WRITE_CRED_DEFAULT 0x00000004
-
-/* HIF_CPUBIUCTRL :: CPU_CREDIT_REG :: MCP0_READ_CRED [03:00] */
-#define BCHP_HIF_CPUBIUCTRL_CPU_CREDIT_REG_MCP0_READ_CRED_MASK 0x0000000f
-#define BCHP_HIF_CPUBIUCTRL_CPU_CREDIT_REG_MCP0_READ_CRED_SHIFT 0
-#define BCHP_HIF_CPUBIUCTRL_CPU_CREDIT_REG_MCP0_READ_CRED_DEFAULT 0x00000004
-
-/***************************************************************************
- *CPU_THERM_THROTTLE_REG0 - CPU Thermal Throttling Register0
- ***************************************************************************/
-/* HIF_CPUBIUCTRL :: CPU_THERM_THROTTLE_REG0 :: Misc [31:00] */
-#define BCHP_HIF_CPUBIUCTRL_CPU_THERM_THROTTLE_REG0_Misc_MASK 0xffffffff
-#define BCHP_HIF_CPUBIUCTRL_CPU_THERM_THROTTLE_REG0_Misc_SHIFT 0
-#define BCHP_HIF_CPUBIUCTRL_CPU_THERM_THROTTLE_REG0_Misc_DEFAULT 0x00000000
-
-/***************************************************************************
- *CPU_THERM_THROTTLE_REG1 - CPU Thermal Throttling Register1
- ***************************************************************************/
-/* HIF_CPUBIUCTRL :: CPU_THERM_THROTTLE_REG1 :: Misc [31:00] */
-#define BCHP_HIF_CPUBIUCTRL_CPU_THERM_THROTTLE_REG1_Misc_MASK 0xffffffff
-#define BCHP_HIF_CPUBIUCTRL_CPU_THERM_THROTTLE_REG1_Misc_SHIFT 0
-#define BCHP_HIF_CPUBIUCTRL_CPU_THERM_THROTTLE_REG1_Misc_DEFAULT 0x00000000
-
-/***************************************************************************
- *CPU_THERM_THROTTLE_REG2 - CPU Thermal Throttling Register2
- ***************************************************************************/
-/* HIF_CPUBIUCTRL :: CPU_THERM_THROTTLE_REG2 :: Misc [31:00] */
-#define BCHP_HIF_CPUBIUCTRL_CPU_THERM_THROTTLE_REG2_Misc_MASK 0xffffffff
-#define BCHP_HIF_CPUBIUCTRL_CPU_THERM_THROTTLE_REG2_Misc_SHIFT 0
-#define BCHP_HIF_CPUBIUCTRL_CPU_THERM_THROTTLE_REG2_Misc_DEFAULT 0x00000000
-
-/***************************************************************************
- *CPU_THERM_THROTTLE_REG3 - CPU Thermal Throttling Register3
- ***************************************************************************/
-/* HIF_CPUBIUCTRL :: CPU_THERM_THROTTLE_REG3 :: Misc [31:00] */
-#define BCHP_HIF_CPUBIUCTRL_CPU_THERM_THROTTLE_REG3_Misc_MASK 0xffffffff
-#define BCHP_HIF_CPUBIUCTRL_CPU_THERM_THROTTLE_REG3_Misc_SHIFT 0
-#define BCHP_HIF_CPUBIUCTRL_CPU_THERM_THROTTLE_REG3_Misc_DEFAULT 0x00000000
-
-/***************************************************************************
- *CPU_DEFEATURE_REG - CPU Defeature Register
- ***************************************************************************/
-/* HIF_CPUBIUCTRL :: CPU_DEFEATURE_REG :: reserved0 [31:08] */
-#define BCHP_HIF_CPUBIUCTRL_CPU_DEFEATURE_REG_reserved0_MASK 0xffffff00
-#define BCHP_HIF_CPUBIUCTRL_CPU_DEFEATURE_REG_reserved0_SHIFT 8
-
-/* HIF_CPUBIUCTRL :: CPU_DEFEATURE_REG :: RAC_DEBUG [07:04] */
-#define BCHP_HIF_CPUBIUCTRL_CPU_DEFEATURE_REG_RAC_DEBUG_MASK 0x000000f0
-#define BCHP_HIF_CPUBIUCTRL_CPU_DEFEATURE_REG_RAC_DEBUG_SHIFT 4
-#define BCHP_HIF_CPUBIUCTRL_CPU_DEFEATURE_REG_RAC_DEBUG_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: CPU_DEFEATURE_REG :: RAC_DEFEATURE [03:00] */
-#define BCHP_HIF_CPUBIUCTRL_CPU_DEFEATURE_REG_RAC_DEFEATURE_MASK 0x0000000f
-#define BCHP_HIF_CPUBIUCTRL_CPU_DEFEATURE_REG_RAC_DEFEATURE_SHIFT 0
-#define BCHP_HIF_CPUBIUCTRL_CPU_DEFEATURE_REG_RAC_DEFEATURE_DEFAULT 0x00000000
-
-/***************************************************************************
- *CPU_DEFEATURE_KEY_REG - CPU Defeature Key Register
- ***************************************************************************/
-/* HIF_CPUBIUCTRL :: CPU_DEFEATURE_KEY_REG :: KEY [31:00] */
-#define BCHP_HIF_CPUBIUCTRL_CPU_DEFEATURE_KEY_REG_KEY_MASK 0xffffffff
-#define BCHP_HIF_CPUBIUCTRL_CPU_DEFEATURE_KEY_REG_KEY_SHIFT 0
-#define BCHP_HIF_CPUBIUCTRL_CPU_DEFEATURE_KEY_REG_KEY_DEFAULT 0x00000000
-
-/***************************************************************************
- *CPU_DEBUGROMADDR_REG - CPU Debug ROM Address Register
- ***************************************************************************/
-/* HIF_CPUBIUCTRL :: CPU_DEBUGROMADDR_REG :: DBGROMADDR [31:04] */
-#define BCHP_HIF_CPUBIUCTRL_CPU_DEBUGROMADDR_REG_DBGROMADDR_MASK 0xfffffff0
-#define BCHP_HIF_CPUBIUCTRL_CPU_DEBUGROMADDR_REG_DBGROMADDR_SHIFT 4
-#define BCHP_HIF_CPUBIUCTRL_CPU_DEBUGROMADDR_REG_DBGROMADDR_DEFAULT 0x00012000
-
-/* HIF_CPUBIUCTRL :: CPU_DEBUGROMADDR_REG :: reserved0 [03:01] */
-#define BCHP_HIF_CPUBIUCTRL_CPU_DEBUGROMADDR_REG_reserved0_MASK 0x0000000e
-#define BCHP_HIF_CPUBIUCTRL_CPU_DEBUGROMADDR_REG_reserved0_SHIFT 1
-
-/* HIF_CPUBIUCTRL :: CPU_DEBUGROMADDR_REG :: DBGROMADDRV [00:00] */
-#define BCHP_HIF_CPUBIUCTRL_CPU_DEBUGROMADDR_REG_DBGROMADDRV_MASK 0x00000001
-#define BCHP_HIF_CPUBIUCTRL_CPU_DEBUGROMADDR_REG_DBGROMADDRV_SHIFT 0
-#define BCHP_HIF_CPUBIUCTRL_CPU_DEBUGROMADDR_REG_DBGROMADDRV_DEFAULT 0x00000000
-
-/***************************************************************************
- *CPU_DEBUGSELFADDR_REG - CPU Debug SELF Address Register
- ***************************************************************************/
-/* HIF_CPUBIUCTRL :: CPU_DEBUGSELFADDR_REG :: DBGSELFADDR [31:11] */
-#define BCHP_HIF_CPUBIUCTRL_CPU_DEBUGSELFADDR_REG_DBGSELFADDR_MASK 0xfffff800
-#define BCHP_HIF_CPUBIUCTRL_CPU_DEBUGSELFADDR_REG_DBGSELFADDR_SHIFT 11
-#define BCHP_HIF_CPUBIUCTRL_CPU_DEBUGSELFADDR_REG_DBGSELFADDR_DEFAULT 0x00000001
-
-/* HIF_CPUBIUCTRL :: CPU_DEBUGSELFADDR_REG :: reserved0 [10:01] */
-#define BCHP_HIF_CPUBIUCTRL_CPU_DEBUGSELFADDR_REG_reserved0_MASK 0x000007fe
-#define BCHP_HIF_CPUBIUCTRL_CPU_DEBUGSELFADDR_REG_reserved0_SHIFT 1
-
-/* HIF_CPUBIUCTRL :: CPU_DEBUGSELFADDR_REG :: DBGSELFADDRV [00:00] */
-#define BCHP_HIF_CPUBIUCTRL_CPU_DEBUGSELFADDR_REG_DBGSELFADDRV_MASK 0x00000001
-#define BCHP_HIF_CPUBIUCTRL_CPU_DEBUGSELFADDR_REG_DBGSELFADDRV_SHIFT 0
-#define BCHP_HIF_CPUBIUCTRL_CPU_DEBUGSELFADDR_REG_DBGSELFADDRV_DEFAULT 0x00000001
-
-/***************************************************************************
- *CPU_DEBUG_TRACECTRL_REG - CPU Debug Trace Control Registeer
- ***************************************************************************/
-/* HIF_CPUBIUCTRL :: CPU_DEBUG_TRACECTRL_REG :: reserved0 [31:05] */
-#define BCHP_HIF_CPUBIUCTRL_CPU_DEBUG_TRACECTRL_REG_reserved0_MASK 0xffffffe0
-#define BCHP_HIF_CPUBIUCTRL_CPU_DEBUG_TRACECTRL_REG_reserved0_SHIFT 5
-
-/* HIF_CPUBIUCTRL :: CPU_DEBUG_TRACECTRL_REG :: TPMAXDATASIZE [04:00] */
-#define BCHP_HIF_CPUBIUCTRL_CPU_DEBUG_TRACECTRL_REG_TPMAXDATASIZE_MASK 0x0000001f
-#define BCHP_HIF_CPUBIUCTRL_CPU_DEBUG_TRACECTRL_REG_TPMAXDATASIZE_SHIFT 0
-#define BCHP_HIF_CPUBIUCTRL_CPU_DEBUG_TRACECTRL_REG_TPMAXDATASIZE_DEFAULT 0x00000003
-
-/***************************************************************************
- *CPU_AXICONFIG_REG - CPU AXI Config Register
- ***************************************************************************/
-/* HIF_CPUBIUCTRL :: CPU_AXICONFIG_REG :: reserved0 [31:04] */
-#define BCHP_HIF_CPUBIUCTRL_CPU_AXICONFIG_REG_reserved0_MASK 0xfffffff0
-#define BCHP_HIF_CPUBIUCTRL_CPU_AXICONFIG_REG_reserved0_SHIFT 4
-
-/* HIF_CPUBIUCTRL :: CPU_AXICONFIG_REG :: BROADCASTINNER [03:03] */
-#define BCHP_HIF_CPUBIUCTRL_CPU_AXICONFIG_REG_BROADCASTINNER_MASK 0x00000008
-#define BCHP_HIF_CPUBIUCTRL_CPU_AXICONFIG_REG_BROADCASTINNER_SHIFT 3
-#define BCHP_HIF_CPUBIUCTRL_CPU_AXICONFIG_REG_BROADCASTINNER_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: CPU_AXICONFIG_REG :: BROADCASTOUTER [02:02] */
-#define BCHP_HIF_CPUBIUCTRL_CPU_AXICONFIG_REG_BROADCASTOUTER_MASK 0x00000004
-#define BCHP_HIF_CPUBIUCTRL_CPU_AXICONFIG_REG_BROADCASTOUTER_SHIFT 2
-#define BCHP_HIF_CPUBIUCTRL_CPU_AXICONFIG_REG_BROADCASTOUTER_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: CPU_AXICONFIG_REG :: BROADCASTCACHEMAINT [01:01] */
-#define BCHP_HIF_CPUBIUCTRL_CPU_AXICONFIG_REG_BROADCASTCACHEMAINT_MASK 0x00000002
-#define BCHP_HIF_CPUBIUCTRL_CPU_AXICONFIG_REG_BROADCASTCACHEMAINT_SHIFT 1
-#define BCHP_HIF_CPUBIUCTRL_CPU_AXICONFIG_REG_BROADCASTCACHEMAINT_DEFAULT 0x00000001
-
-/* HIF_CPUBIUCTRL :: CPU_AXICONFIG_REG :: SYSBARDISABLE [00:00] */
-#define BCHP_HIF_CPUBIUCTRL_CPU_AXICONFIG_REG_SYSBARDISABLE_MASK 0x00000001
-#define BCHP_HIF_CPUBIUCTRL_CPU_AXICONFIG_REG_SYSBARDISABLE_SHIFT 0
-#define BCHP_HIF_CPUBIUCTRL_CPU_AXICONFIG_REG_SYSBARDISABLE_DEFAULT 0x00000000
-
-/***************************************************************************
- *CPU_REVISION_REG - CPU Revision Register
- ***************************************************************************/
-/* HIF_CPUBIUCTRL :: CPU_REVISION_REG :: reserved0 [31:08] */
-#define BCHP_HIF_CPUBIUCTRL_CPU_REVISION_REG_reserved0_MASK 0xffffff00
-#define BCHP_HIF_CPUBIUCTRL_CPU_REVISION_REG_reserved0_SHIFT 8
-
-/* HIF_CPUBIUCTRL :: CPU_REVISION_REG :: MAJOR_REV [07:04] */
-#define BCHP_HIF_CPUBIUCTRL_CPU_REVISION_REG_MAJOR_REV_MASK 0x000000f0
-#define BCHP_HIF_CPUBIUCTRL_CPU_REVISION_REG_MAJOR_REV_SHIFT 4
-#define BCHP_HIF_CPUBIUCTRL_CPU_REVISION_REG_MAJOR_REV_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: CPU_REVISION_REG :: MINOR_REV [03:00] */
-#define BCHP_HIF_CPUBIUCTRL_CPU_REVISION_REG_MINOR_REV_MASK 0x0000000f
-#define BCHP_HIF_CPUBIUCTRL_CPU_REVISION_REG_MINOR_REV_SHIFT 0
-#define BCHP_HIF_CPUBIUCTRL_CPU_REVISION_REG_MINOR_REV_DEFAULT 0x00000001
-
-/***************************************************************************
- *CPU_SCRATCH_REG - Scratch Register
- ***************************************************************************/
-/* HIF_CPUBIUCTRL :: CPU_SCRATCH_REG :: scratch [31:00] */
-#define BCHP_HIF_CPUBIUCTRL_CPU_SCRATCH_REG_scratch_MASK 0xffffffff
-#define BCHP_HIF_CPUBIUCTRL_CPU_SCRATCH_REG_scratch_SHIFT 0
-#define BCHP_HIF_CPUBIUCTRL_CPU_SCRATCH_REG_scratch_DEFAULT 0x00000000
-
-#endif /* #ifndef BCHP_HIF_CPUBIUCTRL_H__ */
-
-/* End of File */
diff --git a/include/linux/brcmstb/7145a0/bchp_hif_intr2.h b/include/linux/brcmstb/7145a0/bchp_hif_intr2.h
deleted file mode 100644
index 48d42ae..0000000
--- a/include/linux/brcmstb/7145a0/bchp_hif_intr2.h
+++ /dev/null
@@ -1,1188 +0,0 @@
-/***************************************************************************
- * Copyright (c) 1999-2013, Broadcom Corporation
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
- *
- * Module Description:
- * DO NOT EDIT THIS FILE DIRECTLY
- *
- * This module was generated magically with RDB from a source description
- * file. You must edit the source file for changes to be made to this file.
- *
- *
- * Date: Generated on Sat Apr 6 03:07:50 2013
- * MD5 Checksum d41d8cd98f00b204e9800998ecf8427e
- *
- * Compiled with: RDB Utility combo_header.pl
- * RDB Parser 3.0
- * unknown unknown
- * Perl Interpreter 5.008008
- * Operating System linux
- *
- * Revision History:
- *
- * $brcm_Log: $
- *
- ***************************************************************************/
-
-#ifndef BCHP_HIF_INTR2_H__
-#define BCHP_HIF_INTR2_H__
-
-/***************************************************************************
- *HIF_INTR2 - HIF Level 2 Interrupt Controller Registers
- ***************************************************************************/
-#define BCHP_HIF_INTR2_CPU_STATUS 0x203d1000 /* CPU interrupt Status Register */
-#define BCHP_HIF_INTR2_CPU_SET 0x203d1004 /* CPU interrupt Set Register */
-#define BCHP_HIF_INTR2_CPU_CLEAR 0x203d1008 /* CPU interrupt Clear Register */
-#define BCHP_HIF_INTR2_CPU_MASK_STATUS 0x203d100c /* CPU interrupt Mask Status Register */
-#define BCHP_HIF_INTR2_CPU_MASK_SET 0x203d1010 /* CPU interrupt Mask Set Register */
-#define BCHP_HIF_INTR2_CPU_MASK_CLEAR 0x203d1014 /* CPU interrupt Mask Clear Register */
-#define BCHP_HIF_INTR2_PCI_STATUS 0x203d1018 /* PCI interrupt Status Register */
-#define BCHP_HIF_INTR2_PCI_SET 0x203d101c /* PCI interrupt Set Register */
-#define BCHP_HIF_INTR2_PCI_CLEAR 0x203d1020 /* PCI interrupt Clear Register */
-#define BCHP_HIF_INTR2_PCI_MASK_STATUS 0x203d1024 /* PCI interrupt Mask Status Register */
-#define BCHP_HIF_INTR2_PCI_MASK_SET 0x203d1028 /* PCI interrupt Mask Set Register */
-#define BCHP_HIF_INTR2_PCI_MASK_CLEAR 0x203d102c /* PCI interrupt Mask Clear Register */
-
-/***************************************************************************
- *CPU_STATUS - CPU interrupt Status Register
- ***************************************************************************/
-/* HIF_INTR2 :: CPU_STATUS :: reserved0 [31:28] */
-#define BCHP_HIF_INTR2_CPU_STATUS_reserved0_MASK 0xf0000000
-#define BCHP_HIF_INTR2_CPU_STATUS_reserved0_SHIFT 28
-
-/* HIF_INTR2 :: CPU_STATUS :: NAND_CORR_INTR [27:27] */
-#define BCHP_HIF_INTR2_CPU_STATUS_NAND_CORR_INTR_MASK 0x08000000
-#define BCHP_HIF_INTR2_CPU_STATUS_NAND_CORR_INTR_SHIFT 27
-#define BCHP_HIF_INTR2_CPU_STATUS_NAND_CORR_INTR_DEFAULT 0x00000000
-
-/* HIF_INTR2 :: CPU_STATUS :: NAND_UNC_INTR [26:26] */
-#define BCHP_HIF_INTR2_CPU_STATUS_NAND_UNC_INTR_MASK 0x04000000
-#define BCHP_HIF_INTR2_CPU_STATUS_NAND_UNC_INTR_SHIFT 26
-#define BCHP_HIF_INTR2_CPU_STATUS_NAND_UNC_INTR_DEFAULT 0x00000000
-
-/* HIF_INTR2 :: CPU_STATUS :: NAND_RBPIN_INTR [25:25] */
-#define BCHP_HIF_INTR2_CPU_STATUS_NAND_RBPIN_INTR_MASK 0x02000000
-#define BCHP_HIF_INTR2_CPU_STATUS_NAND_RBPIN_INTR_SHIFT 25
-#define BCHP_HIF_INTR2_CPU_STATUS_NAND_RBPIN_INTR_DEFAULT 0x00000000
-
-/* HIF_INTR2 :: CPU_STATUS :: NAND_CTLRDY_INTR [24:24] */
-#define BCHP_HIF_INTR2_CPU_STATUS_NAND_CTLRDY_INTR_MASK 0x01000000
-#define BCHP_HIF_INTR2_CPU_STATUS_NAND_CTLRDY_INTR_SHIFT 24
-#define BCHP_HIF_INTR2_CPU_STATUS_NAND_CTLRDY_INTR_DEFAULT 0x00000000
-
-/* HIF_INTR2 :: CPU_STATUS :: NAND_PGMPG_INTR [23:23] */
-#define BCHP_HIF_INTR2_CPU_STATUS_NAND_PGMPG_INTR_MASK 0x00800000
-#define BCHP_HIF_INTR2_CPU_STATUS_NAND_PGMPG_INTR_SHIFT 23
-#define BCHP_HIF_INTR2_CPU_STATUS_NAND_PGMPG_INTR_DEFAULT 0x00000000
-
-/* HIF_INTR2 :: CPU_STATUS :: NAND_CPYBK_INTR [22:22] */
-#define BCHP_HIF_INTR2_CPU_STATUS_NAND_CPYBK_INTR_MASK 0x00400000
-#define BCHP_HIF_INTR2_CPU_STATUS_NAND_CPYBK_INTR_SHIFT 22
-#define BCHP_HIF_INTR2_CPU_STATUS_NAND_CPYBK_INTR_DEFAULT 0x00000000
-
-/* HIF_INTR2 :: CPU_STATUS :: NAND_BLKERA_INTR [21:21] */
-#define BCHP_HIF_INTR2_CPU_STATUS_NAND_BLKERA_INTR_MASK 0x00200000
-#define BCHP_HIF_INTR2_CPU_STATUS_NAND_BLKERA_INTR_SHIFT 21
-#define BCHP_HIF_INTR2_CPU_STATUS_NAND_BLKERA_INTR_DEFAULT 0x00000000
-
-/* HIF_INTR2 :: CPU_STATUS :: NAND_NP_READ_INTR [20:20] */
-#define BCHP_HIF_INTR2_CPU_STATUS_NAND_NP_READ_INTR_MASK 0x00100000
-#define BCHP_HIF_INTR2_CPU_STATUS_NAND_NP_READ_INTR_SHIFT 20
-#define BCHP_HIF_INTR2_CPU_STATUS_NAND_NP_READ_INTR_DEFAULT 0x00000000
-
-/* HIF_INTR2 :: CPU_STATUS :: reserved1 [19:18] */
-#define BCHP_HIF_INTR2_CPU_STATUS_reserved1_MASK 0x000c0000
-#define BCHP_HIF_INTR2_CPU_STATUS_reserved1_SHIFT 18
-
-/* HIF_INTR2 :: CPU_STATUS :: EBI_TIMEOUT_INTR [17:17] */
-#define BCHP_HIF_INTR2_CPU_STATUS_EBI_TIMEOUT_INTR_MASK 0x00020000
-#define BCHP_HIF_INTR2_CPU_STATUS_EBI_TIMEOUT_INTR_SHIFT 17
-#define BCHP_HIF_INTR2_CPU_STATUS_EBI_TIMEOUT_INTR_DEFAULT 0x00000000
-
-/* HIF_INTR2 :: CPU_STATUS :: EBI_TEA_INTR [16:16] */
-#define BCHP_HIF_INTR2_CPU_STATUS_EBI_TEA_INTR_MASK 0x00010000
-#define BCHP_HIF_INTR2_CPU_STATUS_EBI_TEA_INTR_SHIFT 16
-#define BCHP_HIF_INTR2_CPU_STATUS_EBI_TEA_INTR_DEFAULT 0x00000000
-
-/* HIF_INTR2 :: CPU_STATUS :: ITCH0_RD_INTR [15:15] */
-#define BCHP_HIF_INTR2_CPU_STATUS_ITCH0_RD_INTR_MASK 0x00008000
-#define BCHP_HIF_INTR2_CPU_STATUS_ITCH0_RD_INTR_SHIFT 15
-#define BCHP_HIF_INTR2_CPU_STATUS_ITCH0_RD_INTR_DEFAULT 0x00000000
-
-/* HIF_INTR2 :: CPU_STATUS :: reserved2 [14:06] */
-#define BCHP_HIF_INTR2_CPU_STATUS_reserved2_MASK 0x00007fc0
-#define BCHP_HIF_INTR2_CPU_STATUS_reserved2_SHIFT 6
-
-/* HIF_INTR2 :: CPU_STATUS :: FLASH_DMA_ERR_INTR [05:05] */
-#define BCHP_HIF_INTR2_CPU_STATUS_FLASH_DMA_ERR_INTR_MASK 0x00000020
-#define BCHP_HIF_INTR2_CPU_STATUS_FLASH_DMA_ERR_INTR_SHIFT 5
-#define BCHP_HIF_INTR2_CPU_STATUS_FLASH_DMA_ERR_INTR_DEFAULT 0x00000000
-
-/* HIF_INTR2 :: CPU_STATUS :: FLASH_DMA_DONE_INTR [04:04] */
-#define BCHP_HIF_INTR2_CPU_STATUS_FLASH_DMA_DONE_INTR_MASK 0x00000010
-#define BCHP_HIF_INTR2_CPU_STATUS_FLASH_DMA_DONE_INTR_SHIFT 4
-#define BCHP_HIF_INTR2_CPU_STATUS_FLASH_DMA_DONE_INTR_DEFAULT 0x00000000
-
-/* HIF_INTR2 :: CPU_STATUS :: ROUTER_HIF_WD_TIMEOUT_INTR [03:03] */
-#define BCHP_HIF_INTR2_CPU_STATUS_ROUTER_HIF_WD_TIMEOUT_INTR_MASK 0x00000008
-#define BCHP_HIF_INTR2_CPU_STATUS_ROUTER_HIF_WD_TIMEOUT_INTR_SHIFT 3
-#define BCHP_HIF_INTR2_CPU_STATUS_ROUTER_HIF_WD_TIMEOUT_INTR_DEFAULT 0x00000000
-
-/* HIF_INTR2 :: CPU_STATUS :: reserved3 [02:01] */
-#define BCHP_HIF_INTR2_CPU_STATUS_reserved3_MASK 0x00000006
-#define BCHP_HIF_INTR2_CPU_STATUS_reserved3_SHIFT 1
-
-/* HIF_INTR2 :: CPU_STATUS :: HIF_RGR2_BRIDGE_INTR [00:00] */
-#define BCHP_HIF_INTR2_CPU_STATUS_HIF_RGR2_BRIDGE_INTR_MASK 0x00000001
-#define BCHP_HIF_INTR2_CPU_STATUS_HIF_RGR2_BRIDGE_INTR_SHIFT 0
-#define BCHP_HIF_INTR2_CPU_STATUS_HIF_RGR2_BRIDGE_INTR_DEFAULT 0x00000000
-
-/***************************************************************************
- *CPU_SET - CPU interrupt Set Register
- ***************************************************************************/
-/* HIF_INTR2 :: CPU_SET :: reserved0 [31:28] */
-#define BCHP_HIF_INTR2_CPU_SET_reserved0_MASK 0xf0000000
-#define BCHP_HIF_INTR2_CPU_SET_reserved0_SHIFT 28
-
-/* HIF_INTR2 :: CPU_SET :: NAND_CORR_INTR [27:27] */
-#define BCHP_HIF_INTR2_CPU_SET_NAND_CORR_INTR_MASK 0x08000000
-#define BCHP_HIF_INTR2_CPU_SET_NAND_CORR_INTR_SHIFT 27
-#define BCHP_HIF_INTR2_CPU_SET_NAND_CORR_INTR_DEFAULT 0x00000000
-
-/* HIF_INTR2 :: CPU_SET :: NAND_UNC_INTR [26:26] */
-#define BCHP_HIF_INTR2_CPU_SET_NAND_UNC_INTR_MASK 0x04000000
-#define BCHP_HIF_INTR2_CPU_SET_NAND_UNC_INTR_SHIFT 26
-#define BCHP_HIF_INTR2_CPU_SET_NAND_UNC_INTR_DEFAULT 0x00000000
-
-/* HIF_INTR2 :: CPU_SET :: NAND_RBPIN_INTR [25:25] */
-#define BCHP_HIF_INTR2_CPU_SET_NAND_RBPIN_INTR_MASK 0x02000000
-#define BCHP_HIF_INTR2_CPU_SET_NAND_RBPIN_INTR_SHIFT 25
-#define BCHP_HIF_INTR2_CPU_SET_NAND_RBPIN_INTR_DEFAULT 0x00000000
-
-/* HIF_INTR2 :: CPU_SET :: NAND_CTLRDY_INTR [24:24] */
-#define BCHP_HIF_INTR2_CPU_SET_NAND_CTLRDY_INTR_MASK 0x01000000
-#define BCHP_HIF_INTR2_CPU_SET_NAND_CTLRDY_INTR_SHIFT 24
-#define BCHP_HIF_INTR2_CPU_SET_NAND_CTLRDY_INTR_DEFAULT 0x00000000
-
-/* HIF_INTR2 :: CPU_SET :: NAND_PGMPG_INTR [23:23] */
-#define BCHP_HIF_INTR2_CPU_SET_NAND_PGMPG_INTR_MASK 0x00800000
-#define BCHP_HIF_INTR2_CPU_SET_NAND_PGMPG_INTR_SHIFT 23
-#define BCHP_HIF_INTR2_CPU_SET_NAND_PGMPG_INTR_DEFAULT 0x00000000
-
-/* HIF_INTR2 :: CPU_SET :: NAND_CPYBK_INTR [22:22] */
-#define BCHP_HIF_INTR2_CPU_SET_NAND_CPYBK_INTR_MASK 0x00400000
-#define BCHP_HIF_INTR2_CPU_SET_NAND_CPYBK_INTR_SHIFT 22
-#define BCHP_HIF_INTR2_CPU_SET_NAND_CPYBK_INTR_DEFAULT 0x00000000
-
-/* HIF_INTR2 :: CPU_SET :: NAND_BLKERA_INTR [21:21] */
-#define BCHP_HIF_INTR2_CPU_SET_NAND_BLKERA_INTR_MASK 0x00200000
-#define BCHP_HIF_INTR2_CPU_SET_NAND_BLKERA_INTR_SHIFT 21
-#define BCHP_HIF_INTR2_CPU_SET_NAND_BLKERA_INTR_DEFAULT 0x00000000
-
-/* HIF_INTR2 :: CPU_SET :: NAND_NP_READ_INTR [20:20] */
-#define BCHP_HIF_INTR2_CPU_SET_NAND_NP_READ_INTR_MASK 0x00100000
-#define BCHP_HIF_INTR2_CPU_SET_NAND_NP_READ_INTR_SHIFT 20
-#define BCHP_HIF_INTR2_CPU_SET_NAND_NP_READ_INTR_DEFAULT 0x00000000
-
-/* HIF_INTR2 :: CPU_SET :: reserved1 [19:18] */
-#define BCHP_HIF_INTR2_CPU_SET_reserved1_MASK 0x000c0000
-#define BCHP_HIF_INTR2_CPU_SET_reserved1_SHIFT 18
-
-/* HIF_INTR2 :: CPU_SET :: EBI_TIMEOUT_INTR [17:17] */
-#define BCHP_HIF_INTR2_CPU_SET_EBI_TIMEOUT_INTR_MASK 0x00020000
-#define BCHP_HIF_INTR2_CPU_SET_EBI_TIMEOUT_INTR_SHIFT 17
-#define BCHP_HIF_INTR2_CPU_SET_EBI_TIMEOUT_INTR_DEFAULT 0x00000000
-
-/* HIF_INTR2 :: CPU_SET :: EBI_TEA_INTR [16:16] */
-#define BCHP_HIF_INTR2_CPU_SET_EBI_TEA_INTR_MASK 0x00010000
-#define BCHP_HIF_INTR2_CPU_SET_EBI_TEA_INTR_SHIFT 16
-#define BCHP_HIF_INTR2_CPU_SET_EBI_TEA_INTR_DEFAULT 0x00000000
-
-/* HIF_INTR2 :: CPU_SET :: ITCH0_RD_INTR [15:15] */
-#define BCHP_HIF_INTR2_CPU_SET_ITCH0_RD_INTR_MASK 0x00008000
-#define BCHP_HIF_INTR2_CPU_SET_ITCH0_RD_INTR_SHIFT 15
-#define BCHP_HIF_INTR2_CPU_SET_ITCH0_RD_INTR_DEFAULT 0x00000000
-
-/* HIF_INTR2 :: CPU_SET :: reserved2 [14:06] */
-#define BCHP_HIF_INTR2_CPU_SET_reserved2_MASK 0x00007fc0
-#define BCHP_HIF_INTR2_CPU_SET_reserved2_SHIFT 6
-
-/* HIF_INTR2 :: CPU_SET :: FLASH_DMA_ERR_INTR [05:05] */
-#define BCHP_HIF_INTR2_CPU_SET_FLASH_DMA_ERR_INTR_MASK 0x00000020
-#define BCHP_HIF_INTR2_CPU_SET_FLASH_DMA_ERR_INTR_SHIFT 5
-#define BCHP_HIF_INTR2_CPU_SET_FLASH_DMA_ERR_INTR_DEFAULT 0x00000000
-
-/* HIF_INTR2 :: CPU_SET :: FLASH_DMA_DONE_INTR [04:04] */
-#define BCHP_HIF_INTR2_CPU_SET_FLASH_DMA_DONE_INTR_MASK 0x00000010
-#define BCHP_HIF_INTR2_CPU_SET_FLASH_DMA_DONE_INTR_SHIFT 4
-#define BCHP_HIF_INTR2_CPU_SET_FLASH_DMA_DONE_INTR_DEFAULT 0x00000000
-
-/* HIF_INTR2 :: CPU_SET :: ROUTER_HIF_WD_TIMEOUT_INTR [03:03] */
-#define BCHP_HIF_INTR2_CPU_SET_ROUTER_HIF_WD_TIMEOUT_INTR_MASK 0x00000008
-#define BCHP_HIF_INTR2_CPU_SET_ROUTER_HIF_WD_TIMEOUT_INTR_SHIFT 3
-#define BCHP_HIF_INTR2_CPU_SET_ROUTER_HIF_WD_TIMEOUT_INTR_DEFAULT 0x00000000
-
-/* HIF_INTR2 :: CPU_SET :: reserved3 [02:01] */
-#define BCHP_HIF_INTR2_CPU_SET_reserved3_MASK 0x00000006
-#define BCHP_HIF_INTR2_CPU_SET_reserved3_SHIFT 1
-
-/* HIF_INTR2 :: CPU_SET :: HIF_RGR2_BRIDGE_INTR [00:00] */
-#define BCHP_HIF_INTR2_CPU_SET_HIF_RGR2_BRIDGE_INTR_MASK 0x00000001
-#define BCHP_HIF_INTR2_CPU_SET_HIF_RGR2_BRIDGE_INTR_SHIFT 0
-#define BCHP_HIF_INTR2_CPU_SET_HIF_RGR2_BRIDGE_INTR_DEFAULT 0x00000000
-
-/***************************************************************************
- *CPU_CLEAR - CPU interrupt Clear Register
- ***************************************************************************/
-/* HIF_INTR2 :: CPU_CLEAR :: reserved0 [31:28] */
-#define BCHP_HIF_INTR2_CPU_CLEAR_reserved0_MASK 0xf0000000
-#define BCHP_HIF_INTR2_CPU_CLEAR_reserved0_SHIFT 28
-
-/* HIF_INTR2 :: CPU_CLEAR :: NAND_CORR_INTR [27:27] */
-#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_CORR_INTR_MASK 0x08000000
-#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_CORR_INTR_SHIFT 27
-#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_CORR_INTR_DEFAULT 0x00000000
-
-/* HIF_INTR2 :: CPU_CLEAR :: NAND_UNC_INTR [26:26] */
-#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_UNC_INTR_MASK 0x04000000
-#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_UNC_INTR_SHIFT 26
-#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_UNC_INTR_DEFAULT 0x00000000
-
-/* HIF_INTR2 :: CPU_CLEAR :: NAND_RBPIN_INTR [25:25] */
-#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_RBPIN_INTR_MASK 0x02000000
-#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_RBPIN_INTR_SHIFT 25
-#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_RBPIN_INTR_DEFAULT 0x00000000
-
-/* HIF_INTR2 :: CPU_CLEAR :: NAND_CTLRDY_INTR [24:24] */
-#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_CTLRDY_INTR_MASK 0x01000000
-#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_CTLRDY_INTR_SHIFT 24
-#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_CTLRDY_INTR_DEFAULT 0x00000000
-
-/* HIF_INTR2 :: CPU_CLEAR :: NAND_PGMPG_INTR [23:23] */
-#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_PGMPG_INTR_MASK 0x00800000
-#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_PGMPG_INTR_SHIFT 23
-#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_PGMPG_INTR_DEFAULT 0x00000000
-
-/* HIF_INTR2 :: CPU_CLEAR :: NAND_CPYBK_INTR [22:22] */
-#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_CPYBK_INTR_MASK 0x00400000
-#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_CPYBK_INTR_SHIFT 22
-#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_CPYBK_INTR_DEFAULT 0x00000000
-
-/* HIF_INTR2 :: CPU_CLEAR :: NAND_BLKERA_INTR [21:21] */
-#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_BLKERA_INTR_MASK 0x00200000
-#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_BLKERA_INTR_SHIFT 21
-#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_BLKERA_INTR_DEFAULT 0x00000000
-
-/* HIF_INTR2 :: CPU_CLEAR :: NAND_NP_READ_INTR [20:20] */
-#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_NP_READ_INTR_MASK 0x00100000
-#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_NP_READ_INTR_SHIFT 20
-#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_NP_READ_INTR_DEFAULT 0x00000000
-
-/* HIF_INTR2 :: CPU_CLEAR :: reserved1 [19:18] */
-#define BCHP_HIF_INTR2_CPU_CLEAR_reserved1_MASK 0x000c0000
-#define BCHP_HIF_INTR2_CPU_CLEAR_reserved1_SHIFT 18
-
-/* HIF_INTR2 :: CPU_CLEAR :: EBI_TIMEOUT_INTR [17:17] */
-#define BCHP_HIF_INTR2_CPU_CLEAR_EBI_TIMEOUT_INTR_MASK 0x00020000
-#define BCHP_HIF_INTR2_CPU_CLEAR_EBI_TIMEOUT_INTR_SHIFT 17
-#define BCHP_HIF_INTR2_CPU_CLEAR_EBI_TIMEOUT_INTR_DEFAULT 0x00000000
-
-/* HIF_INTR2 :: CPU_CLEAR :: EBI_TEA_INTR [16:16] */
-#define BCHP_HIF_INTR2_CPU_CLEAR_EBI_TEA_INTR_MASK 0x00010000
-#define BCHP_HIF_INTR2_CPU_CLEAR_EBI_TEA_INTR_SHIFT 16
-#define BCHP_HIF_INTR2_CPU_CLEAR_EBI_TEA_INTR_DEFAULT 0x00000000
-
-/* HIF_INTR2 :: CPU_CLEAR :: ITCH0_RD_INTR [15:15] */
-#define BCHP_HIF_INTR2_CPU_CLEAR_ITCH0_RD_INTR_MASK 0x00008000
-#define BCHP_HIF_INTR2_CPU_CLEAR_ITCH0_RD_INTR_SHIFT 15
-#define BCHP_HIF_INTR2_CPU_CLEAR_ITCH0_RD_INTR_DEFAULT 0x00000000
-
-/* HIF_INTR2 :: CPU_CLEAR :: reserved2 [14:06] */
-#define BCHP_HIF_INTR2_CPU_CLEAR_reserved2_MASK 0x00007fc0
-#define BCHP_HIF_INTR2_CPU_CLEAR_reserved2_SHIFT 6
-
-/* HIF_INTR2 :: CPU_CLEAR :: FLASH_DMA_ERR_INTR [05:05] */
-#define BCHP_HIF_INTR2_CPU_CLEAR_FLASH_DMA_ERR_INTR_MASK 0x00000020
-#define BCHP_HIF_INTR2_CPU_CLEAR_FLASH_DMA_ERR_INTR_SHIFT 5
-#define BCHP_HIF_INTR2_CPU_CLEAR_FLASH_DMA_ERR_INTR_DEFAULT 0x00000000
-
-/* HIF_INTR2 :: CPU_CLEAR :: FLASH_DMA_DONE_INTR [04:04] */
-#define BCHP_HIF_INTR2_CPU_CLEAR_FLASH_DMA_DONE_INTR_MASK 0x00000010
-#define BCHP_HIF_INTR2_CPU_CLEAR_FLASH_DMA_DONE_INTR_SHIFT 4
-#define BCHP_HIF_INTR2_CPU_CLEAR_FLASH_DMA_DONE_INTR_DEFAULT 0x00000000
-
-/* HIF_INTR2 :: CPU_CLEAR :: ROUTER_HIF_WD_TIMEOUT_INTR [03:03] */
-#define BCHP_HIF_INTR2_CPU_CLEAR_ROUTER_HIF_WD_TIMEOUT_INTR_MASK 0x00000008
-#define BCHP_HIF_INTR2_CPU_CLEAR_ROUTER_HIF_WD_TIMEOUT_INTR_SHIFT 3
-#define BCHP_HIF_INTR2_CPU_CLEAR_ROUTER_HIF_WD_TIMEOUT_INTR_DEFAULT 0x00000000
-
-/* HIF_INTR2 :: CPU_CLEAR :: reserved3 [02:01] */
-#define BCHP_HIF_INTR2_CPU_CLEAR_reserved3_MASK 0x00000006
-#define BCHP_HIF_INTR2_CPU_CLEAR_reserved3_SHIFT 1
-
-/* HIF_INTR2 :: CPU_CLEAR :: HIF_RGR2_BRIDGE_INTR [00:00] */
-#define BCHP_HIF_INTR2_CPU_CLEAR_HIF_RGR2_BRIDGE_INTR_MASK 0x00000001
-#define BCHP_HIF_INTR2_CPU_CLEAR_HIF_RGR2_BRIDGE_INTR_SHIFT 0
-#define BCHP_HIF_INTR2_CPU_CLEAR_HIF_RGR2_BRIDGE_INTR_DEFAULT 0x00000000
-
-/***************************************************************************
- *CPU_MASK_STATUS - CPU interrupt Mask Status Register
- ***************************************************************************/
-/* HIF_INTR2 :: CPU_MASK_STATUS :: reserved0 [31:28] */
-#define BCHP_HIF_INTR2_CPU_MASK_STATUS_reserved0_MASK 0xf0000000
-#define BCHP_HIF_INTR2_CPU_MASK_STATUS_reserved0_SHIFT 28
-
-/* HIF_INTR2 :: CPU_MASK_STATUS :: NAND_CORR_INTR [27:27] */
-#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_CORR_INTR_MASK 0x08000000
-#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_CORR_INTR_SHIFT 27
-#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_CORR_INTR_DEFAULT 0x00000001
-
-/* HIF_INTR2 :: CPU_MASK_STATUS :: NAND_UNC_INTR [26:26] */
-#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_UNC_INTR_MASK 0x04000000
-#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_UNC_INTR_SHIFT 26
-#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_UNC_INTR_DEFAULT 0x00000001
-
-/* HIF_INTR2 :: CPU_MASK_STATUS :: NAND_RBPIN_INTR [25:25] */
-#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_RBPIN_INTR_MASK 0x02000000
-#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_RBPIN_INTR_SHIFT 25
-#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_RBPIN_INTR_DEFAULT 0x00000001
-
-/* HIF_INTR2 :: CPU_MASK_STATUS :: NAND_CTLRDY_INTR [24:24] */
-#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_CTLRDY_INTR_MASK 0x01000000
-#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_CTLRDY_INTR_SHIFT 24
-#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_CTLRDY_INTR_DEFAULT 0x00000001
-
-/* HIF_INTR2 :: CPU_MASK_STATUS :: NAND_PGMPG_INTR [23:23] */
-#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_PGMPG_INTR_MASK 0x00800000
-#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_PGMPG_INTR_SHIFT 23
-#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_PGMPG_INTR_DEFAULT 0x00000001
-
-/* HIF_INTR2 :: CPU_MASK_STATUS :: NAND_CPYBK_INTR [22:22] */
-#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_CPYBK_INTR_MASK 0x00400000
-#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_CPYBK_INTR_SHIFT 22
-#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_CPYBK_INTR_DEFAULT 0x00000001
-
-/* HIF_INTR2 :: CPU_MASK_STATUS :: NAND_BLKERA_INTR [21:21] */
-#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_BLKERA_INTR_MASK 0x00200000
-#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_BLKERA_INTR_SHIFT 21
-#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_BLKERA_INTR_DEFAULT 0x00000001
-
-/* HIF_INTR2 :: CPU_MASK_STATUS :: NAND_NP_READ_INTR [20:20] */
-#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_NP_READ_INTR_MASK 0x00100000
-#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_NP_READ_INTR_SHIFT 20
-#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_NP_READ_INTR_DEFAULT 0x00000001
-
-/* HIF_INTR2 :: CPU_MASK_STATUS :: reserved1 [19:18] */
-#define BCHP_HIF_INTR2_CPU_MASK_STATUS_reserved1_MASK 0x000c0000
-#define BCHP_HIF_INTR2_CPU_MASK_STATUS_reserved1_SHIFT 18
-
-/* HIF_INTR2 :: CPU_MASK_STATUS :: EBI_TIMEOUT_INTR [17:17] */
-#define BCHP_HIF_INTR2_CPU_MASK_STATUS_EBI_TIMEOUT_INTR_MASK 0x00020000
-#define BCHP_HIF_INTR2_CPU_MASK_STATUS_EBI_TIMEOUT_INTR_SHIFT 17
-#define BCHP_HIF_INTR2_CPU_MASK_STATUS_EBI_TIMEOUT_INTR_DEFAULT 0x00000001
-
-/* HIF_INTR2 :: CPU_MASK_STATUS :: EBI_TEA_INTR [16:16] */
-#define BCHP_HIF_INTR2_CPU_MASK_STATUS_EBI_TEA_INTR_MASK 0x00010000
-#define BCHP_HIF_INTR2_CPU_MASK_STATUS_EBI_TEA_INTR_SHIFT 16
-#define BCHP_HIF_INTR2_CPU_MASK_STATUS_EBI_TEA_INTR_DEFAULT 0x00000001
-
-/* HIF_INTR2 :: CPU_MASK_STATUS :: ITCH0_RD_INTR [15:15] */
-#define BCHP_HIF_INTR2_CPU_MASK_STATUS_ITCH0_RD_INTR_MASK 0x00008000
-#define BCHP_HIF_INTR2_CPU_MASK_STATUS_ITCH0_RD_INTR_SHIFT 15
-#define BCHP_HIF_INTR2_CPU_MASK_STATUS_ITCH0_RD_INTR_DEFAULT 0x00000001
-
-/* HIF_INTR2 :: CPU_MASK_STATUS :: reserved2 [14:06] */
-#define BCHP_HIF_INTR2_CPU_MASK_STATUS_reserved2_MASK 0x00007fc0
-#define BCHP_HIF_INTR2_CPU_MASK_STATUS_reserved2_SHIFT 6
-
-/* HIF_INTR2 :: CPU_MASK_STATUS :: FLASH_DMA_ERR_INTR [05:05] */
-#define BCHP_HIF_INTR2_CPU_MASK_STATUS_FLASH_DMA_ERR_INTR_MASK 0x00000020
-#define BCHP_HIF_INTR2_CPU_MASK_STATUS_FLASH_DMA_ERR_INTR_SHIFT 5
-#define BCHP_HIF_INTR2_CPU_MASK_STATUS_FLASH_DMA_ERR_INTR_DEFAULT 0x00000000
-
-/* HIF_INTR2 :: CPU_MASK_STATUS :: FLASH_DMA_DONE_INTR [04:04] */
-#define BCHP_HIF_INTR2_CPU_MASK_STATUS_FLASH_DMA_DONE_INTR_MASK 0x00000010
-#define BCHP_HIF_INTR2_CPU_MASK_STATUS_FLASH_DMA_DONE_INTR_SHIFT 4
-#define BCHP_HIF_INTR2_CPU_MASK_STATUS_FLASH_DMA_DONE_INTR_DEFAULT 0x00000000
-
-/* HIF_INTR2 :: CPU_MASK_STATUS :: ROUTER_HIF_WD_TIMEOUT_INTR [03:03] */
-#define BCHP_HIF_INTR2_CPU_MASK_STATUS_ROUTER_HIF_WD_TIMEOUT_INTR_MASK 0x00000008
-#define BCHP_HIF_INTR2_CPU_MASK_STATUS_ROUTER_HIF_WD_TIMEOUT_INTR_SHIFT 3
-#define BCHP_HIF_INTR2_CPU_MASK_STATUS_ROUTER_HIF_WD_TIMEOUT_INTR_DEFAULT 0x00000000
-
-/* HIF_INTR2 :: CPU_MASK_STATUS :: reserved3 [02:01] */
-#define BCHP_HIF_INTR2_CPU_MASK_STATUS_reserved3_MASK 0x00000006
-#define BCHP_HIF_INTR2_CPU_MASK_STATUS_reserved3_SHIFT 1
-
-/* HIF_INTR2 :: CPU_MASK_STATUS :: HIF_RGR2_BRIDGE_INTR [00:00] */
-#define BCHP_HIF_INTR2_CPU_MASK_STATUS_HIF_RGR2_BRIDGE_INTR_MASK 0x00000001
-#define BCHP_HIF_INTR2_CPU_MASK_STATUS_HIF_RGR2_BRIDGE_INTR_SHIFT 0
-#define BCHP_HIF_INTR2_CPU_MASK_STATUS_HIF_RGR2_BRIDGE_INTR_DEFAULT 0x00000001
-
-/***************************************************************************
- *CPU_MASK_SET - CPU interrupt Mask Set Register
- ***************************************************************************/
-/* HIF_INTR2 :: CPU_MASK_SET :: reserved0 [31:28] */
-#define BCHP_HIF_INTR2_CPU_MASK_SET_reserved0_MASK 0xf0000000
-#define BCHP_HIF_INTR2_CPU_MASK_SET_reserved0_SHIFT 28
-
-/* HIF_INTR2 :: CPU_MASK_SET :: NAND_CORR_INTR [27:27] */
-#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_CORR_INTR_MASK 0x08000000
-#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_CORR_INTR_SHIFT 27
-#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_CORR_INTR_DEFAULT 0x00000001
-
-/* HIF_INTR2 :: CPU_MASK_SET :: NAND_UNC_INTR [26:26] */
-#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_UNC_INTR_MASK 0x04000000
-#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_UNC_INTR_SHIFT 26
-#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_UNC_INTR_DEFAULT 0x00000001
-
-/* HIF_INTR2 :: CPU_MASK_SET :: NAND_RBPIN_INTR [25:25] */
-#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_RBPIN_INTR_MASK 0x02000000
-#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_RBPIN_INTR_SHIFT 25
-#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_RBPIN_INTR_DEFAULT 0x00000001
-
-/* HIF_INTR2 :: CPU_MASK_SET :: NAND_CTLRDY_INTR [24:24] */
-#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_CTLRDY_INTR_MASK 0x01000000
-#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_CTLRDY_INTR_SHIFT 24
-#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_CTLRDY_INTR_DEFAULT 0x00000001
-
-/* HIF_INTR2 :: CPU_MASK_SET :: NAND_PGMPG_INTR [23:23] */
-#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_PGMPG_INTR_MASK 0x00800000
-#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_PGMPG_INTR_SHIFT 23
-#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_PGMPG_INTR_DEFAULT 0x00000001
-
-/* HIF_INTR2 :: CPU_MASK_SET :: NAND_CPYBK_INTR [22:22] */
-#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_CPYBK_INTR_MASK 0x00400000
-#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_CPYBK_INTR_SHIFT 22
-#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_CPYBK_INTR_DEFAULT 0x00000001
-
-/* HIF_INTR2 :: CPU_MASK_SET :: NAND_BLKERA_INTR [21:21] */
-#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_BLKERA_INTR_MASK 0x00200000
-#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_BLKERA_INTR_SHIFT 21
-#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_BLKERA_INTR_DEFAULT 0x00000001
-
-/* HIF_INTR2 :: CPU_MASK_SET :: NAND_NP_READ_INTR [20:20] */
-#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_NP_READ_INTR_MASK 0x00100000
-#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_NP_READ_INTR_SHIFT 20
-#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_NP_READ_INTR_DEFAULT 0x00000001
-
-/* HIF_INTR2 :: CPU_MASK_SET :: reserved1 [19:18] */
-#define BCHP_HIF_INTR2_CPU_MASK_SET_reserved1_MASK 0x000c0000
-#define BCHP_HIF_INTR2_CPU_MASK_SET_reserved1_SHIFT 18
-
-/* HIF_INTR2 :: CPU_MASK_SET :: EBI_TIMEOUT_INTR [17:17] */
-#define BCHP_HIF_INTR2_CPU_MASK_SET_EBI_TIMEOUT_INTR_MASK 0x00020000
-#define BCHP_HIF_INTR2_CPU_MASK_SET_EBI_TIMEOUT_INTR_SHIFT 17
-#define BCHP_HIF_INTR2_CPU_MASK_SET_EBI_TIMEOUT_INTR_DEFAULT 0x00000001
-
-/* HIF_INTR2 :: CPU_MASK_SET :: EBI_TEA_INTR [16:16] */
-#define BCHP_HIF_INTR2_CPU_MASK_SET_EBI_TEA_INTR_MASK 0x00010000
-#define BCHP_HIF_INTR2_CPU_MASK_SET_EBI_TEA_INTR_SHIFT 16
-#define BCHP_HIF_INTR2_CPU_MASK_SET_EBI_TEA_INTR_DEFAULT 0x00000001
-
-/* HIF_INTR2 :: CPU_MASK_SET :: ITCH0_RD_INTR [15:15] */
-#define BCHP_HIF_INTR2_CPU_MASK_SET_ITCH0_RD_INTR_MASK 0x00008000
-#define BCHP_HIF_INTR2_CPU_MASK_SET_ITCH0_RD_INTR_SHIFT 15
-#define BCHP_HIF_INTR2_CPU_MASK_SET_ITCH0_RD_INTR_DEFAULT 0x00000001
-
-/* HIF_INTR2 :: CPU_MASK_SET :: reserved2 [14:06] */
-#define BCHP_HIF_INTR2_CPU_MASK_SET_reserved2_MASK 0x00007fc0
-#define BCHP_HIF_INTR2_CPU_MASK_SET_reserved2_SHIFT 6
-
-/* HIF_INTR2 :: CPU_MASK_SET :: FLASH_DMA_ERR_INTR [05:05] */
-#define BCHP_HIF_INTR2_CPU_MASK_SET_FLASH_DMA_ERR_INTR_MASK 0x00000020
-#define BCHP_HIF_INTR2_CPU_MASK_SET_FLASH_DMA_ERR_INTR_SHIFT 5
-#define BCHP_HIF_INTR2_CPU_MASK_SET_FLASH_DMA_ERR_INTR_DEFAULT 0x00000000
-
-/* HIF_INTR2 :: CPU_MASK_SET :: FLASH_DMA_DONE_INTR [04:04] */
-#define BCHP_HIF_INTR2_CPU_MASK_SET_FLASH_DMA_DONE_INTR_MASK 0x00000010
-#define BCHP_HIF_INTR2_CPU_MASK_SET_FLASH_DMA_DONE_INTR_SHIFT 4
-#define BCHP_HIF_INTR2_CPU_MASK_SET_FLASH_DMA_DONE_INTR_DEFAULT 0x00000000
-
-/* HIF_INTR2 :: CPU_MASK_SET :: ROUTER_HIF_WD_TIMEOUT_INTR [03:03] */
-#define BCHP_HIF_INTR2_CPU_MASK_SET_ROUTER_HIF_WD_TIMEOUT_INTR_MASK 0x00000008
-#define BCHP_HIF_INTR2_CPU_MASK_SET_ROUTER_HIF_WD_TIMEOUT_INTR_SHIFT 3
-#define BCHP_HIF_INTR2_CPU_MASK_SET_ROUTER_HIF_WD_TIMEOUT_INTR_DEFAULT 0x00000000
-
-/* HIF_INTR2 :: CPU_MASK_SET :: reserved3 [02:01] */
-#define BCHP_HIF_INTR2_CPU_MASK_SET_reserved3_MASK 0x00000006
-#define BCHP_HIF_INTR2_CPU_MASK_SET_reserved3_SHIFT 1
-
-/* HIF_INTR2 :: CPU_MASK_SET :: HIF_RGR2_BRIDGE_INTR [00:00] */
-#define BCHP_HIF_INTR2_CPU_MASK_SET_HIF_RGR2_BRIDGE_INTR_MASK 0x00000001
-#define BCHP_HIF_INTR2_CPU_MASK_SET_HIF_RGR2_BRIDGE_INTR_SHIFT 0
-#define BCHP_HIF_INTR2_CPU_MASK_SET_HIF_RGR2_BRIDGE_INTR_DEFAULT 0x00000001
-
-/***************************************************************************
- *CPU_MASK_CLEAR - CPU interrupt Mask Clear Register
- ***************************************************************************/
-/* HIF_INTR2 :: CPU_MASK_CLEAR :: reserved0 [31:28] */
-#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_reserved0_MASK 0xf0000000
-#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_reserved0_SHIFT 28
-
-/* HIF_INTR2 :: CPU_MASK_CLEAR :: NAND_CORR_INTR [27:27] */
-#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_CORR_INTR_MASK 0x08000000
-#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_CORR_INTR_SHIFT 27
-#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_CORR_INTR_DEFAULT 0x00000001
-
-/* HIF_INTR2 :: CPU_MASK_CLEAR :: NAND_UNC_INTR [26:26] */
-#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_UNC_INTR_MASK 0x04000000
-#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_UNC_INTR_SHIFT 26
-#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_UNC_INTR_DEFAULT 0x00000001
-
-/* HIF_INTR2 :: CPU_MASK_CLEAR :: NAND_RBPIN_INTR [25:25] */
-#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_RBPIN_INTR_MASK 0x02000000
-#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_RBPIN_INTR_SHIFT 25
-#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_RBPIN_INTR_DEFAULT 0x00000001
-
-/* HIF_INTR2 :: CPU_MASK_CLEAR :: NAND_CTLRDY_INTR [24:24] */
-#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_CTLRDY_INTR_MASK 0x01000000
-#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_CTLRDY_INTR_SHIFT 24
-#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_CTLRDY_INTR_DEFAULT 0x00000001
-
-/* HIF_INTR2 :: CPU_MASK_CLEAR :: NAND_PGMPG_INTR [23:23] */
-#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_PGMPG_INTR_MASK 0x00800000
-#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_PGMPG_INTR_SHIFT 23
-#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_PGMPG_INTR_DEFAULT 0x00000001
-
-/* HIF_INTR2 :: CPU_MASK_CLEAR :: NAND_CPYBK_INTR [22:22] */
-#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_CPYBK_INTR_MASK 0x00400000
-#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_CPYBK_INTR_SHIFT 22
-#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_CPYBK_INTR_DEFAULT 0x00000001
-
-/* HIF_INTR2 :: CPU_MASK_CLEAR :: NAND_BLKERA_INTR [21:21] */
-#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_BLKERA_INTR_MASK 0x00200000
-#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_BLKERA_INTR_SHIFT 21
-#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_BLKERA_INTR_DEFAULT 0x00000001
-
-/* HIF_INTR2 :: CPU_MASK_CLEAR :: NAND_NP_READ_INTR [20:20] */
-#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_NP_READ_INTR_MASK 0x00100000
-#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_NP_READ_INTR_SHIFT 20
-#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_NP_READ_INTR_DEFAULT 0x00000001
-
-/* HIF_INTR2 :: CPU_MASK_CLEAR :: reserved1 [19:18] */
-#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_reserved1_MASK 0x000c0000
-#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_reserved1_SHIFT 18
-
-/* HIF_INTR2 :: CPU_MASK_CLEAR :: EBI_TIMEOUT_INTR [17:17] */
-#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_EBI_TIMEOUT_INTR_MASK 0x00020000
-#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_EBI_TIMEOUT_INTR_SHIFT 17
-#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_EBI_TIMEOUT_INTR_DEFAULT 0x00000001
-
-/* HIF_INTR2 :: CPU_MASK_CLEAR :: EBI_TEA_INTR [16:16] */
-#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_EBI_TEA_INTR_MASK 0x00010000
-#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_EBI_TEA_INTR_SHIFT 16
-#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_EBI_TEA_INTR_DEFAULT 0x00000001
-
-/* HIF_INTR2 :: CPU_MASK_CLEAR :: ITCH0_RD_INTR [15:15] */
-#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_ITCH0_RD_INTR_MASK 0x00008000
-#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_ITCH0_RD_INTR_SHIFT 15
-#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_ITCH0_RD_INTR_DEFAULT 0x00000001
-
-/* HIF_INTR2 :: CPU_MASK_CLEAR :: reserved2 [14:06] */
-#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_reserved2_MASK 0x00007fc0
-#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_reserved2_SHIFT 6
-
-/* HIF_INTR2 :: CPU_MASK_CLEAR :: FLASH_DMA_ERR_INTR [05:05] */
-#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_FLASH_DMA_ERR_INTR_MASK 0x00000020
-#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_FLASH_DMA_ERR_INTR_SHIFT 5
-#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_FLASH_DMA_ERR_INTR_DEFAULT 0x00000000
-
-/* HIF_INTR2 :: CPU_MASK_CLEAR :: FLASH_DMA_DONE_INTR [04:04] */
-#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_FLASH_DMA_DONE_INTR_MASK 0x00000010
-#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_FLASH_DMA_DONE_INTR_SHIFT 4
-#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_FLASH_DMA_DONE_INTR_DEFAULT 0x00000000
-
-/* HIF_INTR2 :: CPU_MASK_CLEAR :: ROUTER_HIF_WD_TIMEOUT_INTR [03:03] */
-#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_ROUTER_HIF_WD_TIMEOUT_INTR_MASK 0x00000008
-#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_ROUTER_HIF_WD_TIMEOUT_INTR_SHIFT 3
-#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_ROUTER_HIF_WD_TIMEOUT_INTR_DEFAULT 0x00000000
-
-/* HIF_INTR2 :: CPU_MASK_CLEAR :: reserved3 [02:01] */
-#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_reserved3_MASK 0x00000006
-#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_reserved3_SHIFT 1
-
-/* HIF_INTR2 :: CPU_MASK_CLEAR :: HIF_RGR2_BRIDGE_INTR [00:00] */
-#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_HIF_RGR2_BRIDGE_INTR_MASK 0x00000001
-#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_HIF_RGR2_BRIDGE_INTR_SHIFT 0
-#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_HIF_RGR2_BRIDGE_INTR_DEFAULT 0x00000001
-
-/***************************************************************************
- *PCI_STATUS - PCI interrupt Status Register
- ***************************************************************************/
-/* HIF_INTR2 :: PCI_STATUS :: reserved0 [31:28] */
-#define BCHP_HIF_INTR2_PCI_STATUS_reserved0_MASK 0xf0000000
-#define BCHP_HIF_INTR2_PCI_STATUS_reserved0_SHIFT 28
-
-/* HIF_INTR2 :: PCI_STATUS :: NAND_CORR_INTR [27:27] */
-#define BCHP_HIF_INTR2_PCI_STATUS_NAND_CORR_INTR_MASK 0x08000000
-#define BCHP_HIF_INTR2_PCI_STATUS_NAND_CORR_INTR_SHIFT 27
-#define BCHP_HIF_INTR2_PCI_STATUS_NAND_CORR_INTR_DEFAULT 0x00000000
-
-/* HIF_INTR2 :: PCI_STATUS :: NAND_UNC_INTR [26:26] */
-#define BCHP_HIF_INTR2_PCI_STATUS_NAND_UNC_INTR_MASK 0x04000000
-#define BCHP_HIF_INTR2_PCI_STATUS_NAND_UNC_INTR_SHIFT 26
-#define BCHP_HIF_INTR2_PCI_STATUS_NAND_UNC_INTR_DEFAULT 0x00000000
-
-/* HIF_INTR2 :: PCI_STATUS :: NAND_RBPIN_INTR [25:25] */
-#define BCHP_HIF_INTR2_PCI_STATUS_NAND_RBPIN_INTR_MASK 0x02000000
-#define BCHP_HIF_INTR2_PCI_STATUS_NAND_RBPIN_INTR_SHIFT 25
-#define BCHP_HIF_INTR2_PCI_STATUS_NAND_RBPIN_INTR_DEFAULT 0x00000000
-
-/* HIF_INTR2 :: PCI_STATUS :: NAND_CTLRDY_INTR [24:24] */
-#define BCHP_HIF_INTR2_PCI_STATUS_NAND_CTLRDY_INTR_MASK 0x01000000
-#define BCHP_HIF_INTR2_PCI_STATUS_NAND_CTLRDY_INTR_SHIFT 24
-#define BCHP_HIF_INTR2_PCI_STATUS_NAND_CTLRDY_INTR_DEFAULT 0x00000000
-
-/* HIF_INTR2 :: PCI_STATUS :: NAND_PGMPG_INTR [23:23] */
-#define BCHP_HIF_INTR2_PCI_STATUS_NAND_PGMPG_INTR_MASK 0x00800000
-#define BCHP_HIF_INTR2_PCI_STATUS_NAND_PGMPG_INTR_SHIFT 23
-#define BCHP_HIF_INTR2_PCI_STATUS_NAND_PGMPG_INTR_DEFAULT 0x00000000
-
-/* HIF_INTR2 :: PCI_STATUS :: NAND_CPYBK_INTR [22:22] */
-#define BCHP_HIF_INTR2_PCI_STATUS_NAND_CPYBK_INTR_MASK 0x00400000
-#define BCHP_HIF_INTR2_PCI_STATUS_NAND_CPYBK_INTR_SHIFT 22
-#define BCHP_HIF_INTR2_PCI_STATUS_NAND_CPYBK_INTR_DEFAULT 0x00000000
-
-/* HIF_INTR2 :: PCI_STATUS :: NAND_BLKERA_INTR [21:21] */
-#define BCHP_HIF_INTR2_PCI_STATUS_NAND_BLKERA_INTR_MASK 0x00200000
-#define BCHP_HIF_INTR2_PCI_STATUS_NAND_BLKERA_INTR_SHIFT 21
-#define BCHP_HIF_INTR2_PCI_STATUS_NAND_BLKERA_INTR_DEFAULT 0x00000000
-
-/* HIF_INTR2 :: PCI_STATUS :: NAND_NP_READ_INTR [20:20] */
-#define BCHP_HIF_INTR2_PCI_STATUS_NAND_NP_READ_INTR_MASK 0x00100000
-#define BCHP_HIF_INTR2_PCI_STATUS_NAND_NP_READ_INTR_SHIFT 20
-#define BCHP_HIF_INTR2_PCI_STATUS_NAND_NP_READ_INTR_DEFAULT 0x00000000
-
-/* HIF_INTR2 :: PCI_STATUS :: reserved1 [19:18] */
-#define BCHP_HIF_INTR2_PCI_STATUS_reserved1_MASK 0x000c0000
-#define BCHP_HIF_INTR2_PCI_STATUS_reserved1_SHIFT 18
-
-/* HIF_INTR2 :: PCI_STATUS :: EBI_TIMEOUT_INTR [17:17] */
-#define BCHP_HIF_INTR2_PCI_STATUS_EBI_TIMEOUT_INTR_MASK 0x00020000
-#define BCHP_HIF_INTR2_PCI_STATUS_EBI_TIMEOUT_INTR_SHIFT 17
-#define BCHP_HIF_INTR2_PCI_STATUS_EBI_TIMEOUT_INTR_DEFAULT 0x00000000
-
-/* HIF_INTR2 :: PCI_STATUS :: EBI_TEA_INTR [16:16] */
-#define BCHP_HIF_INTR2_PCI_STATUS_EBI_TEA_INTR_MASK 0x00010000
-#define BCHP_HIF_INTR2_PCI_STATUS_EBI_TEA_INTR_SHIFT 16
-#define BCHP_HIF_INTR2_PCI_STATUS_EBI_TEA_INTR_DEFAULT 0x00000000
-
-/* HIF_INTR2 :: PCI_STATUS :: ITCH0_RD_INTR [15:15] */
-#define BCHP_HIF_INTR2_PCI_STATUS_ITCH0_RD_INTR_MASK 0x00008000
-#define BCHP_HIF_INTR2_PCI_STATUS_ITCH0_RD_INTR_SHIFT 15
-#define BCHP_HIF_INTR2_PCI_STATUS_ITCH0_RD_INTR_DEFAULT 0x00000000
-
-/* HIF_INTR2 :: PCI_STATUS :: reserved2 [14:06] */
-#define BCHP_HIF_INTR2_PCI_STATUS_reserved2_MASK 0x00007fc0
-#define BCHP_HIF_INTR2_PCI_STATUS_reserved2_SHIFT 6
-
-/* HIF_INTR2 :: PCI_STATUS :: FLASH_DMA_ERR_INTR [05:05] */
-#define BCHP_HIF_INTR2_PCI_STATUS_FLASH_DMA_ERR_INTR_MASK 0x00000020
-#define BCHP_HIF_INTR2_PCI_STATUS_FLASH_DMA_ERR_INTR_SHIFT 5
-#define BCHP_HIF_INTR2_PCI_STATUS_FLASH_DMA_ERR_INTR_DEFAULT 0x00000000
-
-/* HIF_INTR2 :: PCI_STATUS :: FLASH_DMA_DONE_INTR [04:04] */
-#define BCHP_HIF_INTR2_PCI_STATUS_FLASH_DMA_DONE_INTR_MASK 0x00000010
-#define BCHP_HIF_INTR2_PCI_STATUS_FLASH_DMA_DONE_INTR_SHIFT 4
-#define BCHP_HIF_INTR2_PCI_STATUS_FLASH_DMA_DONE_INTR_DEFAULT 0x00000000
-
-/* HIF_INTR2 :: PCI_STATUS :: ROUTER_HIF_WD_TIMEOUT_INTR [03:03] */
-#define BCHP_HIF_INTR2_PCI_STATUS_ROUTER_HIF_WD_TIMEOUT_INTR_MASK 0x00000008
-#define BCHP_HIF_INTR2_PCI_STATUS_ROUTER_HIF_WD_TIMEOUT_INTR_SHIFT 3
-#define BCHP_HIF_INTR2_PCI_STATUS_ROUTER_HIF_WD_TIMEOUT_INTR_DEFAULT 0x00000000
-
-/* HIF_INTR2 :: PCI_STATUS :: reserved3 [02:01] */
-#define BCHP_HIF_INTR2_PCI_STATUS_reserved3_MASK 0x00000006
-#define BCHP_HIF_INTR2_PCI_STATUS_reserved3_SHIFT 1
-
-/* HIF_INTR2 :: PCI_STATUS :: HIF_RGR2_BRIDGE_INTR [00:00] */
-#define BCHP_HIF_INTR2_PCI_STATUS_HIF_RGR2_BRIDGE_INTR_MASK 0x00000001
-#define BCHP_HIF_INTR2_PCI_STATUS_HIF_RGR2_BRIDGE_INTR_SHIFT 0
-#define BCHP_HIF_INTR2_PCI_STATUS_HIF_RGR2_BRIDGE_INTR_DEFAULT 0x00000000
-
-/***************************************************************************
- *PCI_SET - PCI interrupt Set Register
- ***************************************************************************/
-/* HIF_INTR2 :: PCI_SET :: reserved0 [31:28] */
-#define BCHP_HIF_INTR2_PCI_SET_reserved0_MASK 0xf0000000
-#define BCHP_HIF_INTR2_PCI_SET_reserved0_SHIFT 28
-
-/* HIF_INTR2 :: PCI_SET :: NAND_CORR_INTR [27:27] */
-#define BCHP_HIF_INTR2_PCI_SET_NAND_CORR_INTR_MASK 0x08000000
-#define BCHP_HIF_INTR2_PCI_SET_NAND_CORR_INTR_SHIFT 27
-#define BCHP_HIF_INTR2_PCI_SET_NAND_CORR_INTR_DEFAULT 0x00000000
-
-/* HIF_INTR2 :: PCI_SET :: NAND_UNC_INTR [26:26] */
-#define BCHP_HIF_INTR2_PCI_SET_NAND_UNC_INTR_MASK 0x04000000
-#define BCHP_HIF_INTR2_PCI_SET_NAND_UNC_INTR_SHIFT 26
-#define BCHP_HIF_INTR2_PCI_SET_NAND_UNC_INTR_DEFAULT 0x00000000
-
-/* HIF_INTR2 :: PCI_SET :: NAND_RBPIN_INTR [25:25] */
-#define BCHP_HIF_INTR2_PCI_SET_NAND_RBPIN_INTR_MASK 0x02000000
-#define BCHP_HIF_INTR2_PCI_SET_NAND_RBPIN_INTR_SHIFT 25
-#define BCHP_HIF_INTR2_PCI_SET_NAND_RBPIN_INTR_DEFAULT 0x00000000
-
-/* HIF_INTR2 :: PCI_SET :: NAND_CTLRDY_INTR [24:24] */
-#define BCHP_HIF_INTR2_PCI_SET_NAND_CTLRDY_INTR_MASK 0x01000000
-#define BCHP_HIF_INTR2_PCI_SET_NAND_CTLRDY_INTR_SHIFT 24
-#define BCHP_HIF_INTR2_PCI_SET_NAND_CTLRDY_INTR_DEFAULT 0x00000000
-
-/* HIF_INTR2 :: PCI_SET :: NAND_PGMPG_INTR [23:23] */
-#define BCHP_HIF_INTR2_PCI_SET_NAND_PGMPG_INTR_MASK 0x00800000
-#define BCHP_HIF_INTR2_PCI_SET_NAND_PGMPG_INTR_SHIFT 23
-#define BCHP_HIF_INTR2_PCI_SET_NAND_PGMPG_INTR_DEFAULT 0x00000000
-
-/* HIF_INTR2 :: PCI_SET :: NAND_CPYBK_INTR [22:22] */
-#define BCHP_HIF_INTR2_PCI_SET_NAND_CPYBK_INTR_MASK 0x00400000
-#define BCHP_HIF_INTR2_PCI_SET_NAND_CPYBK_INTR_SHIFT 22
-#define BCHP_HIF_INTR2_PCI_SET_NAND_CPYBK_INTR_DEFAULT 0x00000000
-
-/* HIF_INTR2 :: PCI_SET :: NAND_BLKERA_INTR [21:21] */
-#define BCHP_HIF_INTR2_PCI_SET_NAND_BLKERA_INTR_MASK 0x00200000
-#define BCHP_HIF_INTR2_PCI_SET_NAND_BLKERA_INTR_SHIFT 21
-#define BCHP_HIF_INTR2_PCI_SET_NAND_BLKERA_INTR_DEFAULT 0x00000000
-
-/* HIF_INTR2 :: PCI_SET :: NAND_NP_READ_INTR [20:20] */
-#define BCHP_HIF_INTR2_PCI_SET_NAND_NP_READ_INTR_MASK 0x00100000
-#define BCHP_HIF_INTR2_PCI_SET_NAND_NP_READ_INTR_SHIFT 20
-#define BCHP_HIF_INTR2_PCI_SET_NAND_NP_READ_INTR_DEFAULT 0x00000000
-
-/* HIF_INTR2 :: PCI_SET :: reserved1 [19:18] */
-#define BCHP_HIF_INTR2_PCI_SET_reserved1_MASK 0x000c0000
-#define BCHP_HIF_INTR2_PCI_SET_reserved1_SHIFT 18
-
-/* HIF_INTR2 :: PCI_SET :: EBI_TIMEOUT_INTR [17:17] */
-#define BCHP_HIF_INTR2_PCI_SET_EBI_TIMEOUT_INTR_MASK 0x00020000
-#define BCHP_HIF_INTR2_PCI_SET_EBI_TIMEOUT_INTR_SHIFT 17
-#define BCHP_HIF_INTR2_PCI_SET_EBI_TIMEOUT_INTR_DEFAULT 0x00000000
-
-/* HIF_INTR2 :: PCI_SET :: EBI_TEA_INTR [16:16] */
-#define BCHP_HIF_INTR2_PCI_SET_EBI_TEA_INTR_MASK 0x00010000
-#define BCHP_HIF_INTR2_PCI_SET_EBI_TEA_INTR_SHIFT 16
-#define BCHP_HIF_INTR2_PCI_SET_EBI_TEA_INTR_DEFAULT 0x00000000
-
-/* HIF_INTR2 :: PCI_SET :: ITCH0_RD_INTR [15:15] */
-#define BCHP_HIF_INTR2_PCI_SET_ITCH0_RD_INTR_MASK 0x00008000
-#define BCHP_HIF_INTR2_PCI_SET_ITCH0_RD_INTR_SHIFT 15
-#define BCHP_HIF_INTR2_PCI_SET_ITCH0_RD_INTR_DEFAULT 0x00000000
-
-/* HIF_INTR2 :: PCI_SET :: reserved2 [14:06] */
-#define BCHP_HIF_INTR2_PCI_SET_reserved2_MASK 0x00007fc0
-#define BCHP_HIF_INTR2_PCI_SET_reserved2_SHIFT 6
-
-/* HIF_INTR2 :: PCI_SET :: FLASH_DMA_ERR_INTR [05:05] */
-#define BCHP_HIF_INTR2_PCI_SET_FLASH_DMA_ERR_INTR_MASK 0x00000020
-#define BCHP_HIF_INTR2_PCI_SET_FLASH_DMA_ERR_INTR_SHIFT 5
-#define BCHP_HIF_INTR2_PCI_SET_FLASH_DMA_ERR_INTR_DEFAULT 0x00000000
-
-/* HIF_INTR2 :: PCI_SET :: FLASH_DMA_DONE_INTR [04:04] */
-#define BCHP_HIF_INTR2_PCI_SET_FLASH_DMA_DONE_INTR_MASK 0x00000010
-#define BCHP_HIF_INTR2_PCI_SET_FLASH_DMA_DONE_INTR_SHIFT 4
-#define BCHP_HIF_INTR2_PCI_SET_FLASH_DMA_DONE_INTR_DEFAULT 0x00000000
-
-/* HIF_INTR2 :: PCI_SET :: ROUTER_HIF_WD_TIMEOUT_INTR [03:03] */
-#define BCHP_HIF_INTR2_PCI_SET_ROUTER_HIF_WD_TIMEOUT_INTR_MASK 0x00000008
-#define BCHP_HIF_INTR2_PCI_SET_ROUTER_HIF_WD_TIMEOUT_INTR_SHIFT 3
-#define BCHP_HIF_INTR2_PCI_SET_ROUTER_HIF_WD_TIMEOUT_INTR_DEFAULT 0x00000000
-
-/* HIF_INTR2 :: PCI_SET :: reserved3 [02:01] */
-#define BCHP_HIF_INTR2_PCI_SET_reserved3_MASK 0x00000006
-#define BCHP_HIF_INTR2_PCI_SET_reserved3_SHIFT 1
-
-/* HIF_INTR2 :: PCI_SET :: HIF_RGR2_BRIDGE_INTR [00:00] */
-#define BCHP_HIF_INTR2_PCI_SET_HIF_RGR2_BRIDGE_INTR_MASK 0x00000001
-#define BCHP_HIF_INTR2_PCI_SET_HIF_RGR2_BRIDGE_INTR_SHIFT 0
-#define BCHP_HIF_INTR2_PCI_SET_HIF_RGR2_BRIDGE_INTR_DEFAULT 0x00000000
-
-/***************************************************************************
- *PCI_CLEAR - PCI interrupt Clear Register
- ***************************************************************************/
-/* HIF_INTR2 :: PCI_CLEAR :: reserved0 [31:28] */
-#define BCHP_HIF_INTR2_PCI_CLEAR_reserved0_MASK 0xf0000000
-#define BCHP_HIF_INTR2_PCI_CLEAR_reserved0_SHIFT 28
-
-/* HIF_INTR2 :: PCI_CLEAR :: NAND_CORR_INTR [27:27] */
-#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_CORR_INTR_MASK 0x08000000
-#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_CORR_INTR_SHIFT 27
-#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_CORR_INTR_DEFAULT 0x00000000
-
-/* HIF_INTR2 :: PCI_CLEAR :: NAND_UNC_INTR [26:26] */
-#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_UNC_INTR_MASK 0x04000000
-#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_UNC_INTR_SHIFT 26
-#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_UNC_INTR_DEFAULT 0x00000000
-
-/* HIF_INTR2 :: PCI_CLEAR :: NAND_RBPIN_INTR [25:25] */
-#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_RBPIN_INTR_MASK 0x02000000
-#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_RBPIN_INTR_SHIFT 25
-#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_RBPIN_INTR_DEFAULT 0x00000000
-
-/* HIF_INTR2 :: PCI_CLEAR :: NAND_CTLRDY_INTR [24:24] */
-#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_CTLRDY_INTR_MASK 0x01000000
-#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_CTLRDY_INTR_SHIFT 24
-#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_CTLRDY_INTR_DEFAULT 0x00000000
-
-/* HIF_INTR2 :: PCI_CLEAR :: NAND_PGMPG_INTR [23:23] */
-#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_PGMPG_INTR_MASK 0x00800000
-#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_PGMPG_INTR_SHIFT 23
-#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_PGMPG_INTR_DEFAULT 0x00000000
-
-/* HIF_INTR2 :: PCI_CLEAR :: NAND_CPYBK_INTR [22:22] */
-#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_CPYBK_INTR_MASK 0x00400000
-#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_CPYBK_INTR_SHIFT 22
-#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_CPYBK_INTR_DEFAULT 0x00000000
-
-/* HIF_INTR2 :: PCI_CLEAR :: NAND_BLKERA_INTR [21:21] */
-#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_BLKERA_INTR_MASK 0x00200000
-#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_BLKERA_INTR_SHIFT 21
-#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_BLKERA_INTR_DEFAULT 0x00000000
-
-/* HIF_INTR2 :: PCI_CLEAR :: NAND_NP_READ_INTR [20:20] */
-#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_NP_READ_INTR_MASK 0x00100000
-#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_NP_READ_INTR_SHIFT 20
-#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_NP_READ_INTR_DEFAULT 0x00000000
-
-/* HIF_INTR2 :: PCI_CLEAR :: reserved1 [19:18] */
-#define BCHP_HIF_INTR2_PCI_CLEAR_reserved1_MASK 0x000c0000
-#define BCHP_HIF_INTR2_PCI_CLEAR_reserved1_SHIFT 18
-
-/* HIF_INTR2 :: PCI_CLEAR :: EBI_TIMEOUT_INTR [17:17] */
-#define BCHP_HIF_INTR2_PCI_CLEAR_EBI_TIMEOUT_INTR_MASK 0x00020000
-#define BCHP_HIF_INTR2_PCI_CLEAR_EBI_TIMEOUT_INTR_SHIFT 17
-#define BCHP_HIF_INTR2_PCI_CLEAR_EBI_TIMEOUT_INTR_DEFAULT 0x00000000
-
-/* HIF_INTR2 :: PCI_CLEAR :: EBI_TEA_INTR [16:16] */
-#define BCHP_HIF_INTR2_PCI_CLEAR_EBI_TEA_INTR_MASK 0x00010000
-#define BCHP_HIF_INTR2_PCI_CLEAR_EBI_TEA_INTR_SHIFT 16
-#define BCHP_HIF_INTR2_PCI_CLEAR_EBI_TEA_INTR_DEFAULT 0x00000000
-
-/* HIF_INTR2 :: PCI_CLEAR :: ITCH0_RD_INTR [15:15] */
-#define BCHP_HIF_INTR2_PCI_CLEAR_ITCH0_RD_INTR_MASK 0x00008000
-#define BCHP_HIF_INTR2_PCI_CLEAR_ITCH0_RD_INTR_SHIFT 15
-#define BCHP_HIF_INTR2_PCI_CLEAR_ITCH0_RD_INTR_DEFAULT 0x00000000
-
-/* HIF_INTR2 :: PCI_CLEAR :: reserved2 [14:06] */
-#define BCHP_HIF_INTR2_PCI_CLEAR_reserved2_MASK 0x00007fc0
-#define BCHP_HIF_INTR2_PCI_CLEAR_reserved2_SHIFT 6
-
-/* HIF_INTR2 :: PCI_CLEAR :: FLASH_DMA_ERR_INTR [05:05] */
-#define BCHP_HIF_INTR2_PCI_CLEAR_FLASH_DMA_ERR_INTR_MASK 0x00000020
-#define BCHP_HIF_INTR2_PCI_CLEAR_FLASH_DMA_ERR_INTR_SHIFT 5
-#define BCHP_HIF_INTR2_PCI_CLEAR_FLASH_DMA_ERR_INTR_DEFAULT 0x00000000
-
-/* HIF_INTR2 :: PCI_CLEAR :: FLASH_DMA_DONE_INTR [04:04] */
-#define BCHP_HIF_INTR2_PCI_CLEAR_FLASH_DMA_DONE_INTR_MASK 0x00000010
-#define BCHP_HIF_INTR2_PCI_CLEAR_FLASH_DMA_DONE_INTR_SHIFT 4
-#define BCHP_HIF_INTR2_PCI_CLEAR_FLASH_DMA_DONE_INTR_DEFAULT 0x00000000
-
-/* HIF_INTR2 :: PCI_CLEAR :: ROUTER_HIF_WD_TIMEOUT_INTR [03:03] */
-#define BCHP_HIF_INTR2_PCI_CLEAR_ROUTER_HIF_WD_TIMEOUT_INTR_MASK 0x00000008
-#define BCHP_HIF_INTR2_PCI_CLEAR_ROUTER_HIF_WD_TIMEOUT_INTR_SHIFT 3
-#define BCHP_HIF_INTR2_PCI_CLEAR_ROUTER_HIF_WD_TIMEOUT_INTR_DEFAULT 0x00000000
-
-/* HIF_INTR2 :: PCI_CLEAR :: reserved3 [02:01] */
-#define BCHP_HIF_INTR2_PCI_CLEAR_reserved3_MASK 0x00000006
-#define BCHP_HIF_INTR2_PCI_CLEAR_reserved3_SHIFT 1
-
-/* HIF_INTR2 :: PCI_CLEAR :: HIF_RGR2_BRIDGE_INTR [00:00] */
-#define BCHP_HIF_INTR2_PCI_CLEAR_HIF_RGR2_BRIDGE_INTR_MASK 0x00000001
-#define BCHP_HIF_INTR2_PCI_CLEAR_HIF_RGR2_BRIDGE_INTR_SHIFT 0
-#define BCHP_HIF_INTR2_PCI_CLEAR_HIF_RGR2_BRIDGE_INTR_DEFAULT 0x00000000
-
-/***************************************************************************
- *PCI_MASK_STATUS - PCI interrupt Mask Status Register
- ***************************************************************************/
-/* HIF_INTR2 :: PCI_MASK_STATUS :: reserved0 [31:28] */
-#define BCHP_HIF_INTR2_PCI_MASK_STATUS_reserved0_MASK 0xf0000000
-#define BCHP_HIF_INTR2_PCI_MASK_STATUS_reserved0_SHIFT 28
-
-/* HIF_INTR2 :: PCI_MASK_STATUS :: NAND_CORR_INTR [27:27] */
-#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_CORR_INTR_MASK 0x08000000
-#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_CORR_INTR_SHIFT 27
-#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_CORR_INTR_DEFAULT 0x00000001
-
-/* HIF_INTR2 :: PCI_MASK_STATUS :: NAND_UNC_INTR [26:26] */
-#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_UNC_INTR_MASK 0x04000000
-#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_UNC_INTR_SHIFT 26
-#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_UNC_INTR_DEFAULT 0x00000001
-
-/* HIF_INTR2 :: PCI_MASK_STATUS :: NAND_RBPIN_INTR [25:25] */
-#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_RBPIN_INTR_MASK 0x02000000
-#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_RBPIN_INTR_SHIFT 25
-#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_RBPIN_INTR_DEFAULT 0x00000001
-
-/* HIF_INTR2 :: PCI_MASK_STATUS :: NAND_CTLRDY_INTR [24:24] */
-#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_CTLRDY_INTR_MASK 0x01000000
-#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_CTLRDY_INTR_SHIFT 24
-#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_CTLRDY_INTR_DEFAULT 0x00000001
-
-/* HIF_INTR2 :: PCI_MASK_STATUS :: NAND_PGMPG_INTR [23:23] */
-#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_PGMPG_INTR_MASK 0x00800000
-#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_PGMPG_INTR_SHIFT 23
-#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_PGMPG_INTR_DEFAULT 0x00000001
-
-/* HIF_INTR2 :: PCI_MASK_STATUS :: NAND_CPYBK_INTR [22:22] */
-#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_CPYBK_INTR_MASK 0x00400000
-#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_CPYBK_INTR_SHIFT 22
-#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_CPYBK_INTR_DEFAULT 0x00000001
-
-/* HIF_INTR2 :: PCI_MASK_STATUS :: NAND_BLKERA_INTR [21:21] */
-#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_BLKERA_INTR_MASK 0x00200000
-#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_BLKERA_INTR_SHIFT 21
-#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_BLKERA_INTR_DEFAULT 0x00000001
-
-/* HIF_INTR2 :: PCI_MASK_STATUS :: NAND_NP_READ_INTR [20:20] */
-#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_NP_READ_INTR_MASK 0x00100000
-#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_NP_READ_INTR_SHIFT 20
-#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_NP_READ_INTR_DEFAULT 0x00000001
-
-/* HIF_INTR2 :: PCI_MASK_STATUS :: reserved1 [19:18] */
-#define BCHP_HIF_INTR2_PCI_MASK_STATUS_reserved1_MASK 0x000c0000
-#define BCHP_HIF_INTR2_PCI_MASK_STATUS_reserved1_SHIFT 18
-
-/* HIF_INTR2 :: PCI_MASK_STATUS :: EBI_TIMEOUT_INTR [17:17] */
-#define BCHP_HIF_INTR2_PCI_MASK_STATUS_EBI_TIMEOUT_INTR_MASK 0x00020000
-#define BCHP_HIF_INTR2_PCI_MASK_STATUS_EBI_TIMEOUT_INTR_SHIFT 17
-#define BCHP_HIF_INTR2_PCI_MASK_STATUS_EBI_TIMEOUT_INTR_DEFAULT 0x00000001
-
-/* HIF_INTR2 :: PCI_MASK_STATUS :: EBI_TEA_INTR [16:16] */
-#define BCHP_HIF_INTR2_PCI_MASK_STATUS_EBI_TEA_INTR_MASK 0x00010000
-#define BCHP_HIF_INTR2_PCI_MASK_STATUS_EBI_TEA_INTR_SHIFT 16
-#define BCHP_HIF_INTR2_PCI_MASK_STATUS_EBI_TEA_INTR_DEFAULT 0x00000001
-
-/* HIF_INTR2 :: PCI_MASK_STATUS :: ITCH0_RD_INTR [15:15] */
-#define BCHP_HIF_INTR2_PCI_MASK_STATUS_ITCH0_RD_INTR_MASK 0x00008000
-#define BCHP_HIF_INTR2_PCI_MASK_STATUS_ITCH0_RD_INTR_SHIFT 15
-#define BCHP_HIF_INTR2_PCI_MASK_STATUS_ITCH0_RD_INTR_DEFAULT 0x00000001
-
-/* HIF_INTR2 :: PCI_MASK_STATUS :: reserved2 [14:06] */
-#define BCHP_HIF_INTR2_PCI_MASK_STATUS_reserved2_MASK 0x00007fc0
-#define BCHP_HIF_INTR2_PCI_MASK_STATUS_reserved2_SHIFT 6
-
-/* HIF_INTR2 :: PCI_MASK_STATUS :: FLASH_DMA_ERR_INTR [05:05] */
-#define BCHP_HIF_INTR2_PCI_MASK_STATUS_FLASH_DMA_ERR_INTR_MASK 0x00000020
-#define BCHP_HIF_INTR2_PCI_MASK_STATUS_FLASH_DMA_ERR_INTR_SHIFT 5
-#define BCHP_HIF_INTR2_PCI_MASK_STATUS_FLASH_DMA_ERR_INTR_DEFAULT 0x00000000
-
-/* HIF_INTR2 :: PCI_MASK_STATUS :: FLASH_DMA_DONE_INTR [04:04] */
-#define BCHP_HIF_INTR2_PCI_MASK_STATUS_FLASH_DMA_DONE_INTR_MASK 0x00000010
-#define BCHP_HIF_INTR2_PCI_MASK_STATUS_FLASH_DMA_DONE_INTR_SHIFT 4
-#define BCHP_HIF_INTR2_PCI_MASK_STATUS_FLASH_DMA_DONE_INTR_DEFAULT 0x00000000
-
-/* HIF_INTR2 :: PCI_MASK_STATUS :: ROUTER_HIF_WD_TIMEOUT_INTR [03:03] */
-#define BCHP_HIF_INTR2_PCI_MASK_STATUS_ROUTER_HIF_WD_TIMEOUT_INTR_MASK 0x00000008
-#define BCHP_HIF_INTR2_PCI_MASK_STATUS_ROUTER_HIF_WD_TIMEOUT_INTR_SHIFT 3
-#define BCHP_HIF_INTR2_PCI_MASK_STATUS_ROUTER_HIF_WD_TIMEOUT_INTR_DEFAULT 0x00000000
-
-/* HIF_INTR2 :: PCI_MASK_STATUS :: reserved3 [02:01] */
-#define BCHP_HIF_INTR2_PCI_MASK_STATUS_reserved3_MASK 0x00000006
-#define BCHP_HIF_INTR2_PCI_MASK_STATUS_reserved3_SHIFT 1
-
-/* HIF_INTR2 :: PCI_MASK_STATUS :: HIF_RGR2_BRIDGE_INTR [00:00] */
-#define BCHP_HIF_INTR2_PCI_MASK_STATUS_HIF_RGR2_BRIDGE_INTR_MASK 0x00000001
-#define BCHP_HIF_INTR2_PCI_MASK_STATUS_HIF_RGR2_BRIDGE_INTR_SHIFT 0
-#define BCHP_HIF_INTR2_PCI_MASK_STATUS_HIF_RGR2_BRIDGE_INTR_DEFAULT 0x00000001
-
-/***************************************************************************
- *PCI_MASK_SET - PCI interrupt Mask Set Register
- ***************************************************************************/
-/* HIF_INTR2 :: PCI_MASK_SET :: reserved0 [31:28] */
-#define BCHP_HIF_INTR2_PCI_MASK_SET_reserved0_MASK 0xf0000000
-#define BCHP_HIF_INTR2_PCI_MASK_SET_reserved0_SHIFT 28
-
-/* HIF_INTR2 :: PCI_MASK_SET :: NAND_CORR_INTR [27:27] */
-#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_CORR_INTR_MASK 0x08000000
-#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_CORR_INTR_SHIFT 27
-#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_CORR_INTR_DEFAULT 0x00000001
-
-/* HIF_INTR2 :: PCI_MASK_SET :: NAND_UNC_INTR [26:26] */
-#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_UNC_INTR_MASK 0x04000000
-#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_UNC_INTR_SHIFT 26
-#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_UNC_INTR_DEFAULT 0x00000001
-
-/* HIF_INTR2 :: PCI_MASK_SET :: NAND_RBPIN_INTR [25:25] */
-#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_RBPIN_INTR_MASK 0x02000000
-#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_RBPIN_INTR_SHIFT 25
-#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_RBPIN_INTR_DEFAULT 0x00000001
-
-/* HIF_INTR2 :: PCI_MASK_SET :: NAND_CTLRDY_INTR [24:24] */
-#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_CTLRDY_INTR_MASK 0x01000000
-#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_CTLRDY_INTR_SHIFT 24
-#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_CTLRDY_INTR_DEFAULT 0x00000001
-
-/* HIF_INTR2 :: PCI_MASK_SET :: NAND_PGMPG_INTR [23:23] */
-#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_PGMPG_INTR_MASK 0x00800000
-#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_PGMPG_INTR_SHIFT 23
-#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_PGMPG_INTR_DEFAULT 0x00000001
-
-/* HIF_INTR2 :: PCI_MASK_SET :: NAND_CPYBK_INTR [22:22] */
-#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_CPYBK_INTR_MASK 0x00400000
-#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_CPYBK_INTR_SHIFT 22
-#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_CPYBK_INTR_DEFAULT 0x00000001
-
-/* HIF_INTR2 :: PCI_MASK_SET :: NAND_BLKERA_INTR [21:21] */
-#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_BLKERA_INTR_MASK 0x00200000
-#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_BLKERA_INTR_SHIFT 21
-#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_BLKERA_INTR_DEFAULT 0x00000001
-
-/* HIF_INTR2 :: PCI_MASK_SET :: NAND_NP_READ_INTR [20:20] */
-#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_NP_READ_INTR_MASK 0x00100000
-#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_NP_READ_INTR_SHIFT 20
-#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_NP_READ_INTR_DEFAULT 0x00000001
-
-/* HIF_INTR2 :: PCI_MASK_SET :: reserved1 [19:18] */
-#define BCHP_HIF_INTR2_PCI_MASK_SET_reserved1_MASK 0x000c0000
-#define BCHP_HIF_INTR2_PCI_MASK_SET_reserved1_SHIFT 18
-
-/* HIF_INTR2 :: PCI_MASK_SET :: EBI_TIMEOUT_INTR [17:17] */
-#define BCHP_HIF_INTR2_PCI_MASK_SET_EBI_TIMEOUT_INTR_MASK 0x00020000
-#define BCHP_HIF_INTR2_PCI_MASK_SET_EBI_TIMEOUT_INTR_SHIFT 17
-#define BCHP_HIF_INTR2_PCI_MASK_SET_EBI_TIMEOUT_INTR_DEFAULT 0x00000001
-
-/* HIF_INTR2 :: PCI_MASK_SET :: EBI_TEA_INTR [16:16] */
-#define BCHP_HIF_INTR2_PCI_MASK_SET_EBI_TEA_INTR_MASK 0x00010000
-#define BCHP_HIF_INTR2_PCI_MASK_SET_EBI_TEA_INTR_SHIFT 16
-#define BCHP_HIF_INTR2_PCI_MASK_SET_EBI_TEA_INTR_DEFAULT 0x00000001
-
-/* HIF_INTR2 :: PCI_MASK_SET :: ITCH0_RD_INTR [15:15] */
-#define BCHP_HIF_INTR2_PCI_MASK_SET_ITCH0_RD_INTR_MASK 0x00008000
-#define BCHP_HIF_INTR2_PCI_MASK_SET_ITCH0_RD_INTR_SHIFT 15
-#define BCHP_HIF_INTR2_PCI_MASK_SET_ITCH0_RD_INTR_DEFAULT 0x00000001
-
-/* HIF_INTR2 :: PCI_MASK_SET :: reserved2 [14:06] */
-#define BCHP_HIF_INTR2_PCI_MASK_SET_reserved2_MASK 0x00007fc0
-#define BCHP_HIF_INTR2_PCI_MASK_SET_reserved2_SHIFT 6
-
-/* HIF_INTR2 :: PCI_MASK_SET :: FLASH_DMA_ERR_INTR [05:05] */
-#define BCHP_HIF_INTR2_PCI_MASK_SET_FLASH_DMA_ERR_INTR_MASK 0x00000020
-#define BCHP_HIF_INTR2_PCI_MASK_SET_FLASH_DMA_ERR_INTR_SHIFT 5
-#define BCHP_HIF_INTR2_PCI_MASK_SET_FLASH_DMA_ERR_INTR_DEFAULT 0x00000000
-
-/* HIF_INTR2 :: PCI_MASK_SET :: FLASH_DMA_DONE_INTR [04:04] */
-#define BCHP_HIF_INTR2_PCI_MASK_SET_FLASH_DMA_DONE_INTR_MASK 0x00000010
-#define BCHP_HIF_INTR2_PCI_MASK_SET_FLASH_DMA_DONE_INTR_SHIFT 4
-#define BCHP_HIF_INTR2_PCI_MASK_SET_FLASH_DMA_DONE_INTR_DEFAULT 0x00000000
-
-/* HIF_INTR2 :: PCI_MASK_SET :: ROUTER_HIF_WD_TIMEOUT_INTR [03:03] */
-#define BCHP_HIF_INTR2_PCI_MASK_SET_ROUTER_HIF_WD_TIMEOUT_INTR_MASK 0x00000008
-#define BCHP_HIF_INTR2_PCI_MASK_SET_ROUTER_HIF_WD_TIMEOUT_INTR_SHIFT 3
-#define BCHP_HIF_INTR2_PCI_MASK_SET_ROUTER_HIF_WD_TIMEOUT_INTR_DEFAULT 0x00000000
-
-/* HIF_INTR2 :: PCI_MASK_SET :: reserved3 [02:01] */
-#define BCHP_HIF_INTR2_PCI_MASK_SET_reserved3_MASK 0x00000006
-#define BCHP_HIF_INTR2_PCI_MASK_SET_reserved3_SHIFT 1
-
-/* HIF_INTR2 :: PCI_MASK_SET :: HIF_RGR2_BRIDGE_INTR [00:00] */
-#define BCHP_HIF_INTR2_PCI_MASK_SET_HIF_RGR2_BRIDGE_INTR_MASK 0x00000001
-#define BCHP_HIF_INTR2_PCI_MASK_SET_HIF_RGR2_BRIDGE_INTR_SHIFT 0
-#define BCHP_HIF_INTR2_PCI_MASK_SET_HIF_RGR2_BRIDGE_INTR_DEFAULT 0x00000001
-
-/***************************************************************************
- *PCI_MASK_CLEAR - PCI interrupt Mask Clear Register
- ***************************************************************************/
-/* HIF_INTR2 :: PCI_MASK_CLEAR :: reserved0 [31:28] */
-#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_reserved0_MASK 0xf0000000
-#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_reserved0_SHIFT 28
-
-/* HIF_INTR2 :: PCI_MASK_CLEAR :: NAND_CORR_INTR [27:27] */
-#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_CORR_INTR_MASK 0x08000000
-#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_CORR_INTR_SHIFT 27
-#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_CORR_INTR_DEFAULT 0x00000001
-
-/* HIF_INTR2 :: PCI_MASK_CLEAR :: NAND_UNC_INTR [26:26] */
-#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_UNC_INTR_MASK 0x04000000
-#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_UNC_INTR_SHIFT 26
-#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_UNC_INTR_DEFAULT 0x00000001
-
-/* HIF_INTR2 :: PCI_MASK_CLEAR :: NAND_RBPIN_INTR [25:25] */
-#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_RBPIN_INTR_MASK 0x02000000
-#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_RBPIN_INTR_SHIFT 25
-#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_RBPIN_INTR_DEFAULT 0x00000001
-
-/* HIF_INTR2 :: PCI_MASK_CLEAR :: NAND_CTLRDY_INTR [24:24] */
-#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_CTLRDY_INTR_MASK 0x01000000
-#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_CTLRDY_INTR_SHIFT 24
-#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_CTLRDY_INTR_DEFAULT 0x00000001
-
-/* HIF_INTR2 :: PCI_MASK_CLEAR :: NAND_PGMPG_INTR [23:23] */
-#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_PGMPG_INTR_MASK 0x00800000
-#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_PGMPG_INTR_SHIFT 23
-#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_PGMPG_INTR_DEFAULT 0x00000001
-
-/* HIF_INTR2 :: PCI_MASK_CLEAR :: NAND_CPYBK_INTR [22:22] */
-#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_CPYBK_INTR_MASK 0x00400000
-#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_CPYBK_INTR_SHIFT 22
-#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_CPYBK_INTR_DEFAULT 0x00000001
-
-/* HIF_INTR2 :: PCI_MASK_CLEAR :: NAND_BLKERA_INTR [21:21] */
-#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_BLKERA_INTR_MASK 0x00200000
-#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_BLKERA_INTR_SHIFT 21
-#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_BLKERA_INTR_DEFAULT 0x00000001
-
-/* HIF_INTR2 :: PCI_MASK_CLEAR :: NAND_NP_READ_INTR [20:20] */
-#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_NP_READ_INTR_MASK 0x00100000
-#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_NP_READ_INTR_SHIFT 20
-#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_NP_READ_INTR_DEFAULT 0x00000001
-
-/* HIF_INTR2 :: PCI_MASK_CLEAR :: reserved1 [19:18] */
-#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_reserved1_MASK 0x000c0000
-#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_reserved1_SHIFT 18
-
-/* HIF_INTR2 :: PCI_MASK_CLEAR :: EBI_TIMEOUT_INTR [17:17] */
-#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_EBI_TIMEOUT_INTR_MASK 0x00020000
-#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_EBI_TIMEOUT_INTR_SHIFT 17
-#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_EBI_TIMEOUT_INTR_DEFAULT 0x00000001
-
-/* HIF_INTR2 :: PCI_MASK_CLEAR :: EBI_TEA_INTR [16:16] */
-#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_EBI_TEA_INTR_MASK 0x00010000
-#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_EBI_TEA_INTR_SHIFT 16
-#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_EBI_TEA_INTR_DEFAULT 0x00000001
-
-/* HIF_INTR2 :: PCI_MASK_CLEAR :: ITCH0_RD_INTR [15:15] */
-#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_ITCH0_RD_INTR_MASK 0x00008000
-#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_ITCH0_RD_INTR_SHIFT 15
-#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_ITCH0_RD_INTR_DEFAULT 0x00000001
-
-/* HIF_INTR2 :: PCI_MASK_CLEAR :: reserved2 [14:06] */
-#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_reserved2_MASK 0x00007fc0
-#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_reserved2_SHIFT 6
-
-/* HIF_INTR2 :: PCI_MASK_CLEAR :: FLASH_DMA_ERR_INTR [05:05] */
-#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_FLASH_DMA_ERR_INTR_MASK 0x00000020
-#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_FLASH_DMA_ERR_INTR_SHIFT 5
-#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_FLASH_DMA_ERR_INTR_DEFAULT 0x00000000
-
-/* HIF_INTR2 :: PCI_MASK_CLEAR :: FLASH_DMA_DONE_INTR [04:04] */
-#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_FLASH_DMA_DONE_INTR_MASK 0x00000010
-#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_FLASH_DMA_DONE_INTR_SHIFT 4
-#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_FLASH_DMA_DONE_INTR_DEFAULT 0x00000000
-
-/* HIF_INTR2 :: PCI_MASK_CLEAR :: ROUTER_HIF_WD_TIMEOUT_INTR [03:03] */
-#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_ROUTER_HIF_WD_TIMEOUT_INTR_MASK 0x00000008
-#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_ROUTER_HIF_WD_TIMEOUT_INTR_SHIFT 3
-#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_ROUTER_HIF_WD_TIMEOUT_INTR_DEFAULT 0x00000000
-
-/* HIF_INTR2 :: PCI_MASK_CLEAR :: reserved3 [02:01] */
-#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_reserved3_MASK 0x00000006
-#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_reserved3_SHIFT 1
-
-/* HIF_INTR2 :: PCI_MASK_CLEAR :: HIF_RGR2_BRIDGE_INTR [00:00] */
-#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_HIF_RGR2_BRIDGE_INTR_MASK 0x00000001
-#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_HIF_RGR2_BRIDGE_INTR_SHIFT 0
-#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_HIF_RGR2_BRIDGE_INTR_DEFAULT 0x00000001
-
-#endif /* #ifndef BCHP_HIF_INTR2_H__ */
-
-/* End of File */
diff --git a/include/linux/brcmstb/7145a0/bchp_hif_mspi.h b/include/linux/brcmstb/7145a0/bchp_hif_mspi.h
deleted file mode 100644
index bb07e19..0000000
--- a/include/linux/brcmstb/7145a0/bchp_hif_mspi.h
+++ /dev/null
@@ -1,1289 +0,0 @@
-/***************************************************************************
- * Copyright (c) 1999-2013, Broadcom Corporation
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
- *
- * Module Description:
- * DO NOT EDIT THIS FILE DIRECTLY
- *
- * This module was generated magically with RDB from a source description
- * file. You must edit the source file for changes to be made to this file.
- *
- *
- * Date: Generated on Sat Apr 6 03:07:48 2013
- * MD5 Checksum d41d8cd98f00b204e9800998ecf8427e
- *
- * Compiled with: RDB Utility combo_header.pl
- * RDB Parser 3.0
- * unknown unknown
- * Perl Interpreter 5.008008
- * Operating System linux
- *
- * Revision History:
- *
- * $brcm_Log: $
- *
- ***************************************************************************/
-
-#ifndef BCHP_HIF_MSPI_H__
-#define BCHP_HIF_MSPI_H__
-
-/***************************************************************************
- *HIF_MSPI - Public MSPI Registers
- ***************************************************************************/
-#define BCHP_HIF_MSPI_SPCR0_LSB 0x203d3400 /* SPCR0_LSB REGISTER */
-#define BCHP_HIF_MSPI_SPCR0_MSB 0x203d3404 /* SPCR0_MSB Register */
-#define BCHP_HIF_MSPI_SPCR1_LSB 0x203d3408 /* SPCR1_LSB REGISTER */
-#define BCHP_HIF_MSPI_SPCR1_MSB 0x203d340c /* SPCR1_MSB REGISTER */
-#define BCHP_HIF_MSPI_NEWQP 0x203d3410 /* NEWQP REGISTER */
-#define BCHP_HIF_MSPI_ENDQP 0x203d3414 /* ENDQP REGISTER */
-#define BCHP_HIF_MSPI_SPCR2 0x203d3418 /* SPCR2 REGISTER */
-#define BCHP_HIF_MSPI_MSPI_STATUS 0x203d3420 /* MSPI STATUS REGISTER */
-#define BCHP_HIF_MSPI_CPTQP 0x203d3424 /* CPTQP REGISTER */
-#define BCHP_HIF_MSPI_SPCR3 0x203d3428 /* SPCR3 REGISTER */
-#define BCHP_HIF_MSPI_REVISION 0x203d342c /* REVISION ID REGISTER */
-#define BCHP_HIF_MSPI_TXRAM00 0x203d3440 /* Most significant byte of TXRAM[0] (queue pointer = 0) */
-#define BCHP_HIF_MSPI_TXRAM01 0x203d3444 /* Least significant byte of TXRAM[0] (queue pointer = 0) */
-#define BCHP_HIF_MSPI_TXRAM02 0x203d3448 /* Most significant byte of TXRAM[1] (queue pointer = 1) */
-#define BCHP_HIF_MSPI_TXRAM03 0x203d344c /* Least significant byte of TXRAM[1] (queue pointer = 1) */
-#define BCHP_HIF_MSPI_TXRAM04 0x203d3450 /* Most significant byte of TXRAM[2] (queue pointer = 2) */
-#define BCHP_HIF_MSPI_TXRAM05 0x203d3454 /* Least significant byte of TXRAM[2] (queue pointer = 2) */
-#define BCHP_HIF_MSPI_TXRAM06 0x203d3458 /* Most significant byte of TXRAM[3] (queue pointer = 3) */
-#define BCHP_HIF_MSPI_TXRAM07 0x203d345c /* Least significant byte of TXRAM[3] (queue pointer = 3) */
-#define BCHP_HIF_MSPI_TXRAM08 0x203d3460 /* Most significant byte of TXRAM[4] (queue pointer = 4) */
-#define BCHP_HIF_MSPI_TXRAM09 0x203d3464 /* Least significant byte of TXRAM[4] (queue pointer = 4) */
-#define BCHP_HIF_MSPI_TXRAM10 0x203d3468 /* Most significant byte of TXRAM[5] (queue pointer = 5) */
-#define BCHP_HIF_MSPI_TXRAM11 0x203d346c /* Least significant byte of TXRAM[5] (queue pointer = 5) */
-#define BCHP_HIF_MSPI_TXRAM12 0x203d3470 /* Most significant byte of TXRAM[6] (queue pointer = 6) */
-#define BCHP_HIF_MSPI_TXRAM13 0x203d3474 /* Least significant byte of TXRAM[6] (queue pointer = 6) */
-#define BCHP_HIF_MSPI_TXRAM14 0x203d3478 /* Most significant byte of TXRAM[7] (queue pointer = 7) */
-#define BCHP_HIF_MSPI_TXRAM15 0x203d347c /* Least significant byte of TXRAM[7] (queue pointer = 7) */
-#define BCHP_HIF_MSPI_TXRAM16 0x203d3480 /* Most significant byte of TXRAM[8] (queue pointer = 8) */
-#define BCHP_HIF_MSPI_TXRAM17 0x203d3484 /* Least significant byte of TXRAM[8] (queue pointer = 8) */
-#define BCHP_HIF_MSPI_TXRAM18 0x203d3488 /* Most significant byte of TXRAM[9] (queue pointer = 9) */
-#define BCHP_HIF_MSPI_TXRAM19 0x203d348c /* Least significant byte of TXRAM[9] (queue pointer = 9) */
-#define BCHP_HIF_MSPI_TXRAM20 0x203d3490 /* Most significant byte of TXRAM[10] (queue pointer = 10) */
-#define BCHP_HIF_MSPI_TXRAM21 0x203d3494 /* Least significant byte of TXRAM[10] (queue pointer = 10) */
-#define BCHP_HIF_MSPI_TXRAM22 0x203d3498 /* Most significant byte of TXRAM[11] (queue pointer = 11) */
-#define BCHP_HIF_MSPI_TXRAM23 0x203d349c /* Least significant byte of TXRAM[11] (queue pointer = 11) */
-#define BCHP_HIF_MSPI_TXRAM24 0x203d34a0 /* Most significant byte of TXRAM[12] (queue pointer = 12) */
-#define BCHP_HIF_MSPI_TXRAM25 0x203d34a4 /* Least significant byte of TXRAM[12] (queue pointer = 12) */
-#define BCHP_HIF_MSPI_TXRAM26 0x203d34a8 /* Most significant byte of TXRAM[13] (queue pointer = 13) */
-#define BCHP_HIF_MSPI_TXRAM27 0x203d34ac /* Least significant byte of TXRAM[13] (queue pointer = 13) */
-#define BCHP_HIF_MSPI_TXRAM28 0x203d34b0 /* Most significant byte of TXRAM[14] (queue pointer = 14) */
-#define BCHP_HIF_MSPI_TXRAM29 0x203d34b4 /* Least significant byte of TXRAM[14] (queue pointer = 14) */
-#define BCHP_HIF_MSPI_TXRAM30 0x203d34b8 /* Most significant byte of TXRAM[15] (queue pointer = 15) */
-#define BCHP_HIF_MSPI_TXRAM31 0x203d34bc /* Least significant byte of TXRAM[15] (queue pointer = 15) */
-#define BCHP_HIF_MSPI_RXRAM00 0x203d34c0 /* Most significant byte of RXRAM[0] (queue pointer = 0) */
-#define BCHP_HIF_MSPI_RXRAM01 0x203d34c4 /* Least significant byte of RXRAM[0] (queue pointer = 0) */
-#define BCHP_HIF_MSPI_RXRAM02 0x203d34c8 /* Most significant byte of RXRAM[1] (queue pointer = 1) */
-#define BCHP_HIF_MSPI_RXRAM03 0x203d34cc /* Least significant byte of RXRAM[1] (queue pointer = 1) */
-#define BCHP_HIF_MSPI_RXRAM04 0x203d34d0 /* Most significant byte of RXRAM[2] (queue pointer = 2) */
-#define BCHP_HIF_MSPI_RXRAM05 0x203d34d4 /* Least significant byte of RXRAM[2] (queue pointer = 2) */
-#define BCHP_HIF_MSPI_RXRAM06 0x203d34d8 /* Most significant byte of RXRAM[3] (queue pointer = 3) */
-#define BCHP_HIF_MSPI_RXRAM07 0x203d34dc /* Least significant byte of RXRAM[3] (queue pointer = 3) */
-#define BCHP_HIF_MSPI_RXRAM08 0x203d34e0 /* Most significant byte of RXRAM[4] (queue pointer = 4) */
-#define BCHP_HIF_MSPI_RXRAM09 0x203d34e4 /* Least significant byte of RXRAM[4] (queue pointer = 4) */
-#define BCHP_HIF_MSPI_RXRAM10 0x203d34e8 /* Most significant byte of RXRAM[5] (queue pointer = 5) */
-#define BCHP_HIF_MSPI_RXRAM11 0x203d34ec /* Least significant byte of RXRAM[5] (queue pointer = 5) */
-#define BCHP_HIF_MSPI_RXRAM12 0x203d34f0 /* Most significant byte of RXRAM[6] (queue pointer = 6) */
-#define BCHP_HIF_MSPI_RXRAM13 0x203d34f4 /* Least significant byte of RXRAM[6] (queue pointer = 6) */
-#define BCHP_HIF_MSPI_RXRAM14 0x203d34f8 /* Most significant byte of RXRAM[7] (queue pointer = 7) */
-#define BCHP_HIF_MSPI_RXRAM15 0x203d34fc /* Least significant byte of RXRAM[7] (queue pointer = 7) */
-#define BCHP_HIF_MSPI_RXRAM16 0x203d3500 /* Most significant byte of RXRAM[8] (queue pointer = 8) */
-#define BCHP_HIF_MSPI_RXRAM17 0x203d3504 /* Least significant byte of RXRAM[8] (queue pointer = 8) */
-#define BCHP_HIF_MSPI_RXRAM18 0x203d3508 /* Most significant byte of RXRAM[9] (queue pointer = 9) */
-#define BCHP_HIF_MSPI_RXRAM19 0x203d350c /* Least significant byte of RXRAM[9] (queue pointer = 9) */
-#define BCHP_HIF_MSPI_RXRAM20 0x203d3510 /* Most significant byte of RXRAM[10] (queue pointer = 10) */
-#define BCHP_HIF_MSPI_RXRAM21 0x203d3514 /* Least significant byte of RXRAM[10] (queue pointer = 10) */
-#define BCHP_HIF_MSPI_RXRAM22 0x203d3518 /* Most significant byte of RXRAM[11] (queue pointer = 11) */
-#define BCHP_HIF_MSPI_RXRAM23 0x203d351c /* Least significant byte of RXRAM[11] (queue pointer = 11) */
-#define BCHP_HIF_MSPI_RXRAM24 0x203d3520 /* Most significant byte of RXRAM[12] (queue pointer = 12) */
-#define BCHP_HIF_MSPI_RXRAM25 0x203d3524 /* Least significant byte of RXRAM[12] (queue pointer = 12) */
-#define BCHP_HIF_MSPI_RXRAM26 0x203d3528 /* Most significant byte of RXRAM[13] (queue pointer = 13) */
-#define BCHP_HIF_MSPI_RXRAM27 0x203d352c /* Least significant byte of RXRAM[13] (queue pointer = 13) */
-#define BCHP_HIF_MSPI_RXRAM28 0x203d3530 /* Most significant byte of RXRAM[14] (queue pointer = 14) */
-#define BCHP_HIF_MSPI_RXRAM29 0x203d3534 /* Least significant byte of RXRAM[14] (queue pointer = 14) */
-#define BCHP_HIF_MSPI_RXRAM30 0x203d3538 /* Most significant byte of RXRAM[15] (queue pointer = 15) */
-#define BCHP_HIF_MSPI_RXRAM31 0x203d353c /* Least significant byte of RXRAM[15] (queue pointer = 15) */
-#define BCHP_HIF_MSPI_CDRAM00 0x203d3540 /* 8-bit command (queue pointer = 0) */
-#define BCHP_HIF_MSPI_CDRAM01 0x203d3544 /* 8-bit command (queue pointer = 1) */
-#define BCHP_HIF_MSPI_CDRAM02 0x203d3548 /* 8-bit command (queue pointer = 2) */
-#define BCHP_HIF_MSPI_CDRAM03 0x203d354c /* 8-bit command (queue pointer = 3) */
-#define BCHP_HIF_MSPI_CDRAM04 0x203d3550 /* 8-bit command (queue pointer = 4) */
-#define BCHP_HIF_MSPI_CDRAM05 0x203d3554 /* 8-bit command (queue pointer = 5) */
-#define BCHP_HIF_MSPI_CDRAM06 0x203d3558 /* 8-bit command (queue pointer = 6) */
-#define BCHP_HIF_MSPI_CDRAM07 0x203d355c /* 8-bit command (queue pointer = 7) */
-#define BCHP_HIF_MSPI_CDRAM08 0x203d3560 /* 8-bit command (queue pointer = 8) */
-#define BCHP_HIF_MSPI_CDRAM09 0x203d3564 /* 8-bit command (queue pointer = 9) */
-#define BCHP_HIF_MSPI_CDRAM10 0x203d3568 /* 8-bit command (queue pointer = a) */
-#define BCHP_HIF_MSPI_CDRAM11 0x203d356c /* 8-bit command (queue pointer = b) */
-#define BCHP_HIF_MSPI_CDRAM12 0x203d3570 /* 8-bit command (queue pointer = c) */
-#define BCHP_HIF_MSPI_CDRAM13 0x203d3574 /* 8-bit command (queue pointer = d) */
-#define BCHP_HIF_MSPI_CDRAM14 0x203d3578 /* 8-bit command (queue pointer = e) */
-#define BCHP_HIF_MSPI_CDRAM15 0x203d357c /* 8-bit command (queue pointer = f) */
-#define BCHP_HIF_MSPI_WRITE_LOCK 0x203d3580 /* Control bit to lock group of write commands */
-#define BCHP_HIF_MSPI_DISABLE_FLUSH_GEN 0x203d3584 /* Debug bit to mask the generation of flush signals from Mspi */
-
-/***************************************************************************
- *SPCR0_LSB - SPCR0_LSB REGISTER
- ***************************************************************************/
-/* HIF_MSPI :: SPCR0_LSB :: reserved0 [31:08] */
-#define BCHP_HIF_MSPI_SPCR0_LSB_reserved0_MASK 0xffffff00
-#define BCHP_HIF_MSPI_SPCR0_LSB_reserved0_SHIFT 8
-
-/* HIF_MSPI :: SPCR0_LSB :: SPBR [07:00] */
-#define BCHP_HIF_MSPI_SPCR0_LSB_SPBR_MASK 0x000000ff
-#define BCHP_HIF_MSPI_SPCR0_LSB_SPBR_SHIFT 0
-#define BCHP_HIF_MSPI_SPCR0_LSB_SPBR_DEFAULT 0x00000000
-
-/***************************************************************************
- *SPCR0_MSB - SPCR0_MSB Register
- ***************************************************************************/
-/* HIF_MSPI :: SPCR0_MSB :: reserved0 [31:09] */
-#define BCHP_HIF_MSPI_SPCR0_MSB_reserved0_MASK 0xfffffe00
-#define BCHP_HIF_MSPI_SPCR0_MSB_reserved0_SHIFT 9
-
-/* HIF_MSPI :: SPCR0_MSB :: StartTransDelay [08:08] */
-#define BCHP_HIF_MSPI_SPCR0_MSB_StartTransDelay_MASK 0x00000100
-#define BCHP_HIF_MSPI_SPCR0_MSB_StartTransDelay_SHIFT 8
-#define BCHP_HIF_MSPI_SPCR0_MSB_StartTransDelay_DEFAULT 0x00000000
-
-/* union - case data_reg_8 [07:02] */
-/* HIF_MSPI :: SPCR0_MSB :: data_reg_8 :: reserved0 [07:06] */
-#define BCHP_HIF_MSPI_SPCR0_MSB_data_reg_8_reserved0_MASK 0x000000c0
-#define BCHP_HIF_MSPI_SPCR0_MSB_data_reg_8_reserved0_SHIFT 6
-
-/* HIF_MSPI :: SPCR0_MSB :: data_reg_8 :: BITS [05:02] */
-#define BCHP_HIF_MSPI_SPCR0_MSB_data_reg_8_BITS_MASK 0x0000003c
-#define BCHP_HIF_MSPI_SPCR0_MSB_data_reg_8_BITS_SHIFT 2
-#define BCHP_HIF_MSPI_SPCR0_MSB_data_reg_8_BITS_DEFAULT 0x00000000
-
-/* union - case data_reg_32 [07:02] */
-/* HIF_MSPI :: SPCR0_MSB :: data_reg_32 :: BITS [07:02] */
-#define BCHP_HIF_MSPI_SPCR0_MSB_data_reg_32_BITS_MASK 0x000000fc
-#define BCHP_HIF_MSPI_SPCR0_MSB_data_reg_32_BITS_SHIFT 2
-#define BCHP_HIF_MSPI_SPCR0_MSB_data_reg_32_BITS_DEFAULT 0x00000000
-
-/* HIF_MSPI :: SPCR0_MSB :: CPOL [01:01] */
-#define BCHP_HIF_MSPI_SPCR0_MSB_CPOL_MASK 0x00000002
-#define BCHP_HIF_MSPI_SPCR0_MSB_CPOL_SHIFT 1
-#define BCHP_HIF_MSPI_SPCR0_MSB_CPOL_DEFAULT 0x00000000
-
-/* HIF_MSPI :: SPCR0_MSB :: CPHA [00:00] */
-#define BCHP_HIF_MSPI_SPCR0_MSB_CPHA_MASK 0x00000001
-#define BCHP_HIF_MSPI_SPCR0_MSB_CPHA_SHIFT 0
-#define BCHP_HIF_MSPI_SPCR0_MSB_CPHA_DEFAULT 0x00000000
-
-/***************************************************************************
- *SPCR1_LSB - SPCR1_LSB REGISTER
- ***************************************************************************/
-/* HIF_MSPI :: SPCR1_LSB :: reserved0 [31:08] */
-#define BCHP_HIF_MSPI_SPCR1_LSB_reserved0_MASK 0xffffff00
-#define BCHP_HIF_MSPI_SPCR1_LSB_reserved0_SHIFT 8
-
-/* HIF_MSPI :: SPCR1_LSB :: DTL [07:00] */
-#define BCHP_HIF_MSPI_SPCR1_LSB_DTL_MASK 0x000000ff
-#define BCHP_HIF_MSPI_SPCR1_LSB_DTL_SHIFT 0
-#define BCHP_HIF_MSPI_SPCR1_LSB_DTL_DEFAULT 0x00000000
-
-/***************************************************************************
- *SPCR1_MSB - SPCR1_MSB REGISTER
- ***************************************************************************/
-/* HIF_MSPI :: SPCR1_MSB :: reserved0 [31:08] */
-#define BCHP_HIF_MSPI_SPCR1_MSB_reserved0_MASK 0xffffff00
-#define BCHP_HIF_MSPI_SPCR1_MSB_reserved0_SHIFT 8
-
-/* HIF_MSPI :: SPCR1_MSB :: RDSCLK [07:00] */
-#define BCHP_HIF_MSPI_SPCR1_MSB_RDSCLK_MASK 0x000000ff
-#define BCHP_HIF_MSPI_SPCR1_MSB_RDSCLK_SHIFT 0
-#define BCHP_HIF_MSPI_SPCR1_MSB_RDSCLK_DEFAULT 0x00000000
-
-/***************************************************************************
- *NEWQP - NEWQP REGISTER
- ***************************************************************************/
-/* HIF_MSPI :: NEWQP :: reserved0 [31:04] */
-#define BCHP_HIF_MSPI_NEWQP_reserved0_MASK 0xfffffff0
-#define BCHP_HIF_MSPI_NEWQP_reserved0_SHIFT 4
-
-/* HIF_MSPI :: NEWQP :: newqp [03:00] */
-#define BCHP_HIF_MSPI_NEWQP_newqp_MASK 0x0000000f
-#define BCHP_HIF_MSPI_NEWQP_newqp_SHIFT 0
-#define BCHP_HIF_MSPI_NEWQP_newqp_DEFAULT 0x00000000
-
-/***************************************************************************
- *ENDQP - ENDQP REGISTER
- ***************************************************************************/
-/* HIF_MSPI :: ENDQP :: reserved0 [31:04] */
-#define BCHP_HIF_MSPI_ENDQP_reserved0_MASK 0xfffffff0
-#define BCHP_HIF_MSPI_ENDQP_reserved0_SHIFT 4
-
-/* HIF_MSPI :: ENDQP :: endqp [03:00] */
-#define BCHP_HIF_MSPI_ENDQP_endqp_MASK 0x0000000f
-#define BCHP_HIF_MSPI_ENDQP_endqp_SHIFT 0
-#define BCHP_HIF_MSPI_ENDQP_endqp_DEFAULT 0x00000000
-
-/***************************************************************************
- *SPCR2 - SPCR2 REGISTER
- ***************************************************************************/
-/* HIF_MSPI :: SPCR2 :: reserved0 [31:08] */
-#define BCHP_HIF_MSPI_SPCR2_reserved0_MASK 0xffffff00
-#define BCHP_HIF_MSPI_SPCR2_reserved0_SHIFT 8
-
-/* HIF_MSPI :: SPCR2 :: cont_after_cmd [07:07] */
-#define BCHP_HIF_MSPI_SPCR2_cont_after_cmd_MASK 0x00000080
-#define BCHP_HIF_MSPI_SPCR2_cont_after_cmd_SHIFT 7
-#define BCHP_HIF_MSPI_SPCR2_cont_after_cmd_DEFAULT 0x00000000
-
-/* HIF_MSPI :: SPCR2 :: spe [06:06] */
-#define BCHP_HIF_MSPI_SPCR2_spe_MASK 0x00000040
-#define BCHP_HIF_MSPI_SPCR2_spe_SHIFT 6
-#define BCHP_HIF_MSPI_SPCR2_spe_DEFAULT 0x00000000
-
-/* HIF_MSPI :: SPCR2 :: spifie [05:05] */
-#define BCHP_HIF_MSPI_SPCR2_spifie_MASK 0x00000020
-#define BCHP_HIF_MSPI_SPCR2_spifie_SHIFT 5
-#define BCHP_HIF_MSPI_SPCR2_spifie_DEFAULT 0x00000000
-
-/* HIF_MSPI :: SPCR2 :: wren [04:04] */
-#define BCHP_HIF_MSPI_SPCR2_wren_MASK 0x00000010
-#define BCHP_HIF_MSPI_SPCR2_wren_SHIFT 4
-#define BCHP_HIF_MSPI_SPCR2_wren_DEFAULT 0x00000000
-
-/* HIF_MSPI :: SPCR2 :: wrt0 [03:03] */
-#define BCHP_HIF_MSPI_SPCR2_wrt0_MASK 0x00000008
-#define BCHP_HIF_MSPI_SPCR2_wrt0_SHIFT 3
-#define BCHP_HIF_MSPI_SPCR2_wrt0_DEFAULT 0x00000000
-
-/* HIF_MSPI :: SPCR2 :: loopq [02:02] */
-#define BCHP_HIF_MSPI_SPCR2_loopq_MASK 0x00000004
-#define BCHP_HIF_MSPI_SPCR2_loopq_SHIFT 2
-#define BCHP_HIF_MSPI_SPCR2_loopq_DEFAULT 0x00000000
-
-/* HIF_MSPI :: SPCR2 :: hie [01:01] */
-#define BCHP_HIF_MSPI_SPCR2_hie_MASK 0x00000002
-#define BCHP_HIF_MSPI_SPCR2_hie_SHIFT 1
-#define BCHP_HIF_MSPI_SPCR2_hie_DEFAULT 0x00000000
-
-/* HIF_MSPI :: SPCR2 :: halt [00:00] */
-#define BCHP_HIF_MSPI_SPCR2_halt_MASK 0x00000001
-#define BCHP_HIF_MSPI_SPCR2_halt_SHIFT 0
-#define BCHP_HIF_MSPI_SPCR2_halt_DEFAULT 0x00000000
-
-/***************************************************************************
- *MSPI_STATUS - MSPI STATUS REGISTER
- ***************************************************************************/
-/* HIF_MSPI :: MSPI_STATUS :: reserved0 [31:02] */
-#define BCHP_HIF_MSPI_MSPI_STATUS_reserved0_MASK 0xfffffffc
-#define BCHP_HIF_MSPI_MSPI_STATUS_reserved0_SHIFT 2
-
-/* HIF_MSPI :: MSPI_STATUS :: HALTA [01:01] */
-#define BCHP_HIF_MSPI_MSPI_STATUS_HALTA_MASK 0x00000002
-#define BCHP_HIF_MSPI_MSPI_STATUS_HALTA_SHIFT 1
-#define BCHP_HIF_MSPI_MSPI_STATUS_HALTA_DEFAULT 0x00000000
-
-/* HIF_MSPI :: MSPI_STATUS :: SPIF [00:00] */
-#define BCHP_HIF_MSPI_MSPI_STATUS_SPIF_MASK 0x00000001
-#define BCHP_HIF_MSPI_MSPI_STATUS_SPIF_SHIFT 0
-#define BCHP_HIF_MSPI_MSPI_STATUS_SPIF_DEFAULT 0x00000000
-
-/***************************************************************************
- *CPTQP - CPTQP REGISTER
- ***************************************************************************/
-/* HIF_MSPI :: CPTQP :: reserved0 [31:04] */
-#define BCHP_HIF_MSPI_CPTQP_reserved0_MASK 0xfffffff0
-#define BCHP_HIF_MSPI_CPTQP_reserved0_SHIFT 4
-
-/* HIF_MSPI :: CPTQP :: cptqp [03:00] */
-#define BCHP_HIF_MSPI_CPTQP_cptqp_MASK 0x0000000f
-#define BCHP_HIF_MSPI_CPTQP_cptqp_SHIFT 0
-#define BCHP_HIF_MSPI_CPTQP_cptqp_DEFAULT 0x00000000
-
-/***************************************************************************
- *SPCR3 - SPCR3 REGISTER
- ***************************************************************************/
-/* HIF_MSPI :: SPCR3 :: reserved0 [31:10] */
-#define BCHP_HIF_MSPI_SPCR3_reserved0_MASK 0xfffffc00
-#define BCHP_HIF_MSPI_SPCR3_reserved0_SHIFT 10
-
-/* HIF_MSPI :: SPCR3 :: cpharx [09:09] */
-#define BCHP_HIF_MSPI_SPCR3_cpharx_MASK 0x00000200
-#define BCHP_HIF_MSPI_SPCR3_cpharx_SHIFT 9
-#define BCHP_HIF_MSPI_SPCR3_cpharx_DEFAULT 0x00000000
-
-/* HIF_MSPI :: SPCR3 :: data_reg_size [08:08] */
-#define BCHP_HIF_MSPI_SPCR3_data_reg_size_MASK 0x00000100
-#define BCHP_HIF_MSPI_SPCR3_data_reg_size_SHIFT 8
-#define BCHP_HIF_MSPI_SPCR3_data_reg_size_DEFAULT 0x00000000
-
-/* HIF_MSPI :: SPCR3 :: hdouttype [07:07] */
-#define BCHP_HIF_MSPI_SPCR3_hdouttype_MASK 0x00000080
-#define BCHP_HIF_MSPI_SPCR3_hdouttype_SHIFT 7
-#define BCHP_HIF_MSPI_SPCR3_hdouttype_DEFAULT 0x00000000
-
-/* HIF_MSPI :: SPCR3 :: halfduplex [06:06] */
-#define BCHP_HIF_MSPI_SPCR3_halfduplex_MASK 0x00000040
-#define BCHP_HIF_MSPI_SPCR3_halfduplex_SHIFT 6
-#define BCHP_HIF_MSPI_SPCR3_halfduplex_DEFAULT 0x00000000
-
-/* HIF_MSPI :: SPCR3 :: txramdam [05:04] */
-#define BCHP_HIF_MSPI_SPCR3_txramdam_MASK 0x00000030
-#define BCHP_HIF_MSPI_SPCR3_txramdam_SHIFT 4
-#define BCHP_HIF_MSPI_SPCR3_txramdam_DEFAULT 0x00000000
-#define BCHP_HIF_MSPI_SPCR3_txramdam_DAM_8B 0
-#define BCHP_HIF_MSPI_SPCR3_txramdam_DAM_16B 1
-#define BCHP_HIF_MSPI_SPCR3_txramdam_DAM_32B 2
-
-/* HIF_MSPI :: SPCR3 :: rxramdam [03:02] */
-#define BCHP_HIF_MSPI_SPCR3_rxramdam_MASK 0x0000000c
-#define BCHP_HIF_MSPI_SPCR3_rxramdam_SHIFT 2
-#define BCHP_HIF_MSPI_SPCR3_rxramdam_DEFAULT 0x00000000
-#define BCHP_HIF_MSPI_SPCR3_rxramdam_DAM_8B 0
-#define BCHP_HIF_MSPI_SPCR3_rxramdam_DAM_16B 1
-#define BCHP_HIF_MSPI_SPCR3_rxramdam_DAM_32B 2
-
-/* HIF_MSPI :: SPCR3 :: fastdt [01:01] */
-#define BCHP_HIF_MSPI_SPCR3_fastdt_MASK 0x00000002
-#define BCHP_HIF_MSPI_SPCR3_fastdt_SHIFT 1
-#define BCHP_HIF_MSPI_SPCR3_fastdt_DEFAULT 0x00000000
-
-/* HIF_MSPI :: SPCR3 :: fastbr [00:00] */
-#define BCHP_HIF_MSPI_SPCR3_fastbr_MASK 0x00000001
-#define BCHP_HIF_MSPI_SPCR3_fastbr_SHIFT 0
-#define BCHP_HIF_MSPI_SPCR3_fastbr_DEFAULT 0x00000000
-
-/***************************************************************************
- *REVISION - REVISION ID REGISTER
- ***************************************************************************/
-/* HIF_MSPI :: REVISION :: reserved0 [31:08] */
-#define BCHP_HIF_MSPI_REVISION_reserved0_MASK 0xffffff00
-#define BCHP_HIF_MSPI_REVISION_reserved0_SHIFT 8
-
-/* HIF_MSPI :: REVISION :: major [07:04] */
-#define BCHP_HIF_MSPI_REVISION_major_MASK 0x000000f0
-#define BCHP_HIF_MSPI_REVISION_major_SHIFT 4
-#define BCHP_HIF_MSPI_REVISION_major_DEFAULT 0x00000001
-
-/* HIF_MSPI :: REVISION :: minor [03:00] */
-#define BCHP_HIF_MSPI_REVISION_minor_MASK 0x0000000f
-#define BCHP_HIF_MSPI_REVISION_minor_SHIFT 0
-#define BCHP_HIF_MSPI_REVISION_minor_DEFAULT 0x00000005
-
-/***************************************************************************
- *TXRAM00 - Most significant byte of TXRAM[0] (queue pointer = 0)
- ***************************************************************************/
-/* HIF_MSPI :: TXRAM00 :: reserved0 [31:08] */
-#define BCHP_HIF_MSPI_TXRAM00_reserved0_MASK 0xffffff00
-#define BCHP_HIF_MSPI_TXRAM00_reserved0_SHIFT 8
-
-/* HIF_MSPI :: TXRAM00 :: txram [07:00] */
-#define BCHP_HIF_MSPI_TXRAM00_txram_MASK 0x000000ff
-#define BCHP_HIF_MSPI_TXRAM00_txram_SHIFT 0
-
-/***************************************************************************
- *TXRAM01 - Least significant byte of TXRAM[0] (queue pointer = 0)
- ***************************************************************************/
-/* HIF_MSPI :: TXRAM01 :: reserved0 [31:08] */
-#define BCHP_HIF_MSPI_TXRAM01_reserved0_MASK 0xffffff00
-#define BCHP_HIF_MSPI_TXRAM01_reserved0_SHIFT 8
-
-/* HIF_MSPI :: TXRAM01 :: txram [07:00] */
-#define BCHP_HIF_MSPI_TXRAM01_txram_MASK 0x000000ff
-#define BCHP_HIF_MSPI_TXRAM01_txram_SHIFT 0
-
-/***************************************************************************
- *TXRAM02 - Most significant byte of TXRAM[1] (queue pointer = 1)
- ***************************************************************************/
-/* HIF_MSPI :: TXRAM02 :: reserved0 [31:08] */
-#define BCHP_HIF_MSPI_TXRAM02_reserved0_MASK 0xffffff00
-#define BCHP_HIF_MSPI_TXRAM02_reserved0_SHIFT 8
-
-/* HIF_MSPI :: TXRAM02 :: txram [07:00] */
-#define BCHP_HIF_MSPI_TXRAM02_txram_MASK 0x000000ff
-#define BCHP_HIF_MSPI_TXRAM02_txram_SHIFT 0
-
-/***************************************************************************
- *TXRAM03 - Least significant byte of TXRAM[1] (queue pointer = 1)
- ***************************************************************************/
-/* HIF_MSPI :: TXRAM03 :: reserved0 [31:08] */
-#define BCHP_HIF_MSPI_TXRAM03_reserved0_MASK 0xffffff00
-#define BCHP_HIF_MSPI_TXRAM03_reserved0_SHIFT 8
-
-/* HIF_MSPI :: TXRAM03 :: txram [07:00] */
-#define BCHP_HIF_MSPI_TXRAM03_txram_MASK 0x000000ff
-#define BCHP_HIF_MSPI_TXRAM03_txram_SHIFT 0
-
-/***************************************************************************
- *TXRAM04 - Most significant byte of TXRAM[2] (queue pointer = 2)
- ***************************************************************************/
-/* HIF_MSPI :: TXRAM04 :: reserved0 [31:08] */
-#define BCHP_HIF_MSPI_TXRAM04_reserved0_MASK 0xffffff00
-#define BCHP_HIF_MSPI_TXRAM04_reserved0_SHIFT 8
-
-/* HIF_MSPI :: TXRAM04 :: txram [07:00] */
-#define BCHP_HIF_MSPI_TXRAM04_txram_MASK 0x000000ff
-#define BCHP_HIF_MSPI_TXRAM04_txram_SHIFT 0
-
-/***************************************************************************
- *TXRAM05 - Least significant byte of TXRAM[2] (queue pointer = 2)
- ***************************************************************************/
-/* HIF_MSPI :: TXRAM05 :: reserved0 [31:08] */
-#define BCHP_HIF_MSPI_TXRAM05_reserved0_MASK 0xffffff00
-#define BCHP_HIF_MSPI_TXRAM05_reserved0_SHIFT 8
-
-/* HIF_MSPI :: TXRAM05 :: txram [07:00] */
-#define BCHP_HIF_MSPI_TXRAM05_txram_MASK 0x000000ff
-#define BCHP_HIF_MSPI_TXRAM05_txram_SHIFT 0
-
-/***************************************************************************
- *TXRAM06 - Most significant byte of TXRAM[3] (queue pointer = 3)
- ***************************************************************************/
-/* HIF_MSPI :: TXRAM06 :: reserved0 [31:08] */
-#define BCHP_HIF_MSPI_TXRAM06_reserved0_MASK 0xffffff00
-#define BCHP_HIF_MSPI_TXRAM06_reserved0_SHIFT 8
-
-/* HIF_MSPI :: TXRAM06 :: txram [07:00] */
-#define BCHP_HIF_MSPI_TXRAM06_txram_MASK 0x000000ff
-#define BCHP_HIF_MSPI_TXRAM06_txram_SHIFT 0
-
-/***************************************************************************
- *TXRAM07 - Least significant byte of TXRAM[3] (queue pointer = 3)
- ***************************************************************************/
-/* HIF_MSPI :: TXRAM07 :: reserved0 [31:08] */
-#define BCHP_HIF_MSPI_TXRAM07_reserved0_MASK 0xffffff00
-#define BCHP_HIF_MSPI_TXRAM07_reserved0_SHIFT 8
-
-/* HIF_MSPI :: TXRAM07 :: txram [07:00] */
-#define BCHP_HIF_MSPI_TXRAM07_txram_MASK 0x000000ff
-#define BCHP_HIF_MSPI_TXRAM07_txram_SHIFT 0
-
-/***************************************************************************
- *TXRAM08 - Most significant byte of TXRAM[4] (queue pointer = 4)
- ***************************************************************************/
-/* HIF_MSPI :: TXRAM08 :: reserved0 [31:08] */
-#define BCHP_HIF_MSPI_TXRAM08_reserved0_MASK 0xffffff00
-#define BCHP_HIF_MSPI_TXRAM08_reserved0_SHIFT 8
-
-/* HIF_MSPI :: TXRAM08 :: txram [07:00] */
-#define BCHP_HIF_MSPI_TXRAM08_txram_MASK 0x000000ff
-#define BCHP_HIF_MSPI_TXRAM08_txram_SHIFT 0
-
-/***************************************************************************
- *TXRAM09 - Least significant byte of TXRAM[4] (queue pointer = 4)
- ***************************************************************************/
-/* HIF_MSPI :: TXRAM09 :: reserved0 [31:08] */
-#define BCHP_HIF_MSPI_TXRAM09_reserved0_MASK 0xffffff00
-#define BCHP_HIF_MSPI_TXRAM09_reserved0_SHIFT 8
-
-/* HIF_MSPI :: TXRAM09 :: txram [07:00] */
-#define BCHP_HIF_MSPI_TXRAM09_txram_MASK 0x000000ff
-#define BCHP_HIF_MSPI_TXRAM09_txram_SHIFT 0
-
-/***************************************************************************
- *TXRAM10 - Most significant byte of TXRAM[5] (queue pointer = 5)
- ***************************************************************************/
-/* HIF_MSPI :: TXRAM10 :: reserved0 [31:08] */
-#define BCHP_HIF_MSPI_TXRAM10_reserved0_MASK 0xffffff00
-#define BCHP_HIF_MSPI_TXRAM10_reserved0_SHIFT 8
-
-/* HIF_MSPI :: TXRAM10 :: txram [07:00] */
-#define BCHP_HIF_MSPI_TXRAM10_txram_MASK 0x000000ff
-#define BCHP_HIF_MSPI_TXRAM10_txram_SHIFT 0
-
-/***************************************************************************
- *TXRAM11 - Least significant byte of TXRAM[5] (queue pointer = 5)
- ***************************************************************************/
-/* HIF_MSPI :: TXRAM11 :: reserved0 [31:08] */
-#define BCHP_HIF_MSPI_TXRAM11_reserved0_MASK 0xffffff00
-#define BCHP_HIF_MSPI_TXRAM11_reserved0_SHIFT 8
-
-/* HIF_MSPI :: TXRAM11 :: txram [07:00] */
-#define BCHP_HIF_MSPI_TXRAM11_txram_MASK 0x000000ff
-#define BCHP_HIF_MSPI_TXRAM11_txram_SHIFT 0
-
-/***************************************************************************
- *TXRAM12 - Most significant byte of TXRAM[6] (queue pointer = 6)
- ***************************************************************************/
-/* HIF_MSPI :: TXRAM12 :: reserved0 [31:08] */
-#define BCHP_HIF_MSPI_TXRAM12_reserved0_MASK 0xffffff00
-#define BCHP_HIF_MSPI_TXRAM12_reserved0_SHIFT 8
-
-/* HIF_MSPI :: TXRAM12 :: txram [07:00] */
-#define BCHP_HIF_MSPI_TXRAM12_txram_MASK 0x000000ff
-#define BCHP_HIF_MSPI_TXRAM12_txram_SHIFT 0
-
-/***************************************************************************
- *TXRAM13 - Least significant byte of TXRAM[6] (queue pointer = 6)
- ***************************************************************************/
-/* HIF_MSPI :: TXRAM13 :: reserved0 [31:08] */
-#define BCHP_HIF_MSPI_TXRAM13_reserved0_MASK 0xffffff00
-#define BCHP_HIF_MSPI_TXRAM13_reserved0_SHIFT 8
-
-/* HIF_MSPI :: TXRAM13 :: txram [07:00] */
-#define BCHP_HIF_MSPI_TXRAM13_txram_MASK 0x000000ff
-#define BCHP_HIF_MSPI_TXRAM13_txram_SHIFT 0
-
-/***************************************************************************
- *TXRAM14 - Most significant byte of TXRAM[7] (queue pointer = 7)
- ***************************************************************************/
-/* HIF_MSPI :: TXRAM14 :: reserved0 [31:08] */
-#define BCHP_HIF_MSPI_TXRAM14_reserved0_MASK 0xffffff00
-#define BCHP_HIF_MSPI_TXRAM14_reserved0_SHIFT 8
-
-/* HIF_MSPI :: TXRAM14 :: txram [07:00] */
-#define BCHP_HIF_MSPI_TXRAM14_txram_MASK 0x000000ff
-#define BCHP_HIF_MSPI_TXRAM14_txram_SHIFT 0
-
-/***************************************************************************
- *TXRAM15 - Least significant byte of TXRAM[7] (queue pointer = 7)
- ***************************************************************************/
-/* HIF_MSPI :: TXRAM15 :: reserved0 [31:08] */
-#define BCHP_HIF_MSPI_TXRAM15_reserved0_MASK 0xffffff00
-#define BCHP_HIF_MSPI_TXRAM15_reserved0_SHIFT 8
-
-/* HIF_MSPI :: TXRAM15 :: txram [07:00] */
-#define BCHP_HIF_MSPI_TXRAM15_txram_MASK 0x000000ff
-#define BCHP_HIF_MSPI_TXRAM15_txram_SHIFT 0
-
-/***************************************************************************
- *TXRAM16 - Most significant byte of TXRAM[8] (queue pointer = 8)
- ***************************************************************************/
-/* HIF_MSPI :: TXRAM16 :: reserved0 [31:08] */
-#define BCHP_HIF_MSPI_TXRAM16_reserved0_MASK 0xffffff00
-#define BCHP_HIF_MSPI_TXRAM16_reserved0_SHIFT 8
-
-/* HIF_MSPI :: TXRAM16 :: txram [07:00] */
-#define BCHP_HIF_MSPI_TXRAM16_txram_MASK 0x000000ff
-#define BCHP_HIF_MSPI_TXRAM16_txram_SHIFT 0
-
-/***************************************************************************
- *TXRAM17 - Least significant byte of TXRAM[8] (queue pointer = 8)
- ***************************************************************************/
-/* HIF_MSPI :: TXRAM17 :: reserved0 [31:08] */
-#define BCHP_HIF_MSPI_TXRAM17_reserved0_MASK 0xffffff00
-#define BCHP_HIF_MSPI_TXRAM17_reserved0_SHIFT 8
-
-/* HIF_MSPI :: TXRAM17 :: txram [07:00] */
-#define BCHP_HIF_MSPI_TXRAM17_txram_MASK 0x000000ff
-#define BCHP_HIF_MSPI_TXRAM17_txram_SHIFT 0
-
-/***************************************************************************
- *TXRAM18 - Most significant byte of TXRAM[9] (queue pointer = 9)
- ***************************************************************************/
-/* HIF_MSPI :: TXRAM18 :: reserved0 [31:08] */
-#define BCHP_HIF_MSPI_TXRAM18_reserved0_MASK 0xffffff00
-#define BCHP_HIF_MSPI_TXRAM18_reserved0_SHIFT 8
-
-/* HIF_MSPI :: TXRAM18 :: txram [07:00] */
-#define BCHP_HIF_MSPI_TXRAM18_txram_MASK 0x000000ff
-#define BCHP_HIF_MSPI_TXRAM18_txram_SHIFT 0
-
-/***************************************************************************
- *TXRAM19 - Least significant byte of TXRAM[9] (queue pointer = 9)
- ***************************************************************************/
-/* HIF_MSPI :: TXRAM19 :: reserved0 [31:08] */
-#define BCHP_HIF_MSPI_TXRAM19_reserved0_MASK 0xffffff00
-#define BCHP_HIF_MSPI_TXRAM19_reserved0_SHIFT 8
-
-/* HIF_MSPI :: TXRAM19 :: txram [07:00] */
-#define BCHP_HIF_MSPI_TXRAM19_txram_MASK 0x000000ff
-#define BCHP_HIF_MSPI_TXRAM19_txram_SHIFT 0
-
-/***************************************************************************
- *TXRAM20 - Most significant byte of TXRAM[10] (queue pointer = 10)
- ***************************************************************************/
-/* HIF_MSPI :: TXRAM20 :: reserved0 [31:08] */
-#define BCHP_HIF_MSPI_TXRAM20_reserved0_MASK 0xffffff00
-#define BCHP_HIF_MSPI_TXRAM20_reserved0_SHIFT 8
-
-/* HIF_MSPI :: TXRAM20 :: txram [07:00] */
-#define BCHP_HIF_MSPI_TXRAM20_txram_MASK 0x000000ff
-#define BCHP_HIF_MSPI_TXRAM20_txram_SHIFT 0
-
-/***************************************************************************
- *TXRAM21 - Least significant byte of TXRAM[10] (queue pointer = 10)
- ***************************************************************************/
-/* HIF_MSPI :: TXRAM21 :: reserved0 [31:08] */
-#define BCHP_HIF_MSPI_TXRAM21_reserved0_MASK 0xffffff00
-#define BCHP_HIF_MSPI_TXRAM21_reserved0_SHIFT 8
-
-/* HIF_MSPI :: TXRAM21 :: txram [07:00] */
-#define BCHP_HIF_MSPI_TXRAM21_txram_MASK 0x000000ff
-#define BCHP_HIF_MSPI_TXRAM21_txram_SHIFT 0
-
-/***************************************************************************
- *TXRAM22 - Most significant byte of TXRAM[11] (queue pointer = 11)
- ***************************************************************************/
-/* HIF_MSPI :: TXRAM22 :: reserved0 [31:08] */
-#define BCHP_HIF_MSPI_TXRAM22_reserved0_MASK 0xffffff00
-#define BCHP_HIF_MSPI_TXRAM22_reserved0_SHIFT 8
-
-/* HIF_MSPI :: TXRAM22 :: txram [07:00] */
-#define BCHP_HIF_MSPI_TXRAM22_txram_MASK 0x000000ff
-#define BCHP_HIF_MSPI_TXRAM22_txram_SHIFT 0
-
-/***************************************************************************
- *TXRAM23 - Least significant byte of TXRAM[11] (queue pointer = 11)
- ***************************************************************************/
-/* HIF_MSPI :: TXRAM23 :: reserved0 [31:08] */
-#define BCHP_HIF_MSPI_TXRAM23_reserved0_MASK 0xffffff00
-#define BCHP_HIF_MSPI_TXRAM23_reserved0_SHIFT 8
-
-/* HIF_MSPI :: TXRAM23 :: txram [07:00] */
-#define BCHP_HIF_MSPI_TXRAM23_txram_MASK 0x000000ff
-#define BCHP_HIF_MSPI_TXRAM23_txram_SHIFT 0
-
-/***************************************************************************
- *TXRAM24 - Most significant byte of TXRAM[12] (queue pointer = 12)
- ***************************************************************************/
-/* HIF_MSPI :: TXRAM24 :: reserved0 [31:08] */
-#define BCHP_HIF_MSPI_TXRAM24_reserved0_MASK 0xffffff00
-#define BCHP_HIF_MSPI_TXRAM24_reserved0_SHIFT 8
-
-/* HIF_MSPI :: TXRAM24 :: txram [07:00] */
-#define BCHP_HIF_MSPI_TXRAM24_txram_MASK 0x000000ff
-#define BCHP_HIF_MSPI_TXRAM24_txram_SHIFT 0
-
-/***************************************************************************
- *TXRAM25 - Least significant byte of TXRAM[12] (queue pointer = 12)
- ***************************************************************************/
-/* HIF_MSPI :: TXRAM25 :: reserved0 [31:08] */
-#define BCHP_HIF_MSPI_TXRAM25_reserved0_MASK 0xffffff00
-#define BCHP_HIF_MSPI_TXRAM25_reserved0_SHIFT 8
-
-/* HIF_MSPI :: TXRAM25 :: txram [07:00] */
-#define BCHP_HIF_MSPI_TXRAM25_txram_MASK 0x000000ff
-#define BCHP_HIF_MSPI_TXRAM25_txram_SHIFT 0
-
-/***************************************************************************
- *TXRAM26 - Most significant byte of TXRAM[13] (queue pointer = 13)
- ***************************************************************************/
-/* HIF_MSPI :: TXRAM26 :: reserved0 [31:08] */
-#define BCHP_HIF_MSPI_TXRAM26_reserved0_MASK 0xffffff00
-#define BCHP_HIF_MSPI_TXRAM26_reserved0_SHIFT 8
-
-/* HIF_MSPI :: TXRAM26 :: txram [07:00] */
-#define BCHP_HIF_MSPI_TXRAM26_txram_MASK 0x000000ff
-#define BCHP_HIF_MSPI_TXRAM26_txram_SHIFT 0
-
-/***************************************************************************
- *TXRAM27 - Least significant byte of TXRAM[13] (queue pointer = 13)
- ***************************************************************************/
-/* HIF_MSPI :: TXRAM27 :: reserved0 [31:08] */
-#define BCHP_HIF_MSPI_TXRAM27_reserved0_MASK 0xffffff00
-#define BCHP_HIF_MSPI_TXRAM27_reserved0_SHIFT 8
-
-/* HIF_MSPI :: TXRAM27 :: txram [07:00] */
-#define BCHP_HIF_MSPI_TXRAM27_txram_MASK 0x000000ff
-#define BCHP_HIF_MSPI_TXRAM27_txram_SHIFT 0
-
-/***************************************************************************
- *TXRAM28 - Most significant byte of TXRAM[14] (queue pointer = 14)
- ***************************************************************************/
-/* HIF_MSPI :: TXRAM28 :: reserved0 [31:08] */
-#define BCHP_HIF_MSPI_TXRAM28_reserved0_MASK 0xffffff00
-#define BCHP_HIF_MSPI_TXRAM28_reserved0_SHIFT 8
-
-/* HIF_MSPI :: TXRAM28 :: txram [07:00] */
-#define BCHP_HIF_MSPI_TXRAM28_txram_MASK 0x000000ff
-#define BCHP_HIF_MSPI_TXRAM28_txram_SHIFT 0
-
-/***************************************************************************
- *TXRAM29 - Least significant byte of TXRAM[14] (queue pointer = 14)
- ***************************************************************************/
-/* HIF_MSPI :: TXRAM29 :: reserved0 [31:08] */
-#define BCHP_HIF_MSPI_TXRAM29_reserved0_MASK 0xffffff00
-#define BCHP_HIF_MSPI_TXRAM29_reserved0_SHIFT 8
-
-/* HIF_MSPI :: TXRAM29 :: txram [07:00] */
-#define BCHP_HIF_MSPI_TXRAM29_txram_MASK 0x000000ff
-#define BCHP_HIF_MSPI_TXRAM29_txram_SHIFT 0
-
-/***************************************************************************
- *TXRAM30 - Most significant byte of TXRAM[15] (queue pointer = 15)
- ***************************************************************************/
-/* HIF_MSPI :: TXRAM30 :: reserved0 [31:08] */
-#define BCHP_HIF_MSPI_TXRAM30_reserved0_MASK 0xffffff00
-#define BCHP_HIF_MSPI_TXRAM30_reserved0_SHIFT 8
-
-/* HIF_MSPI :: TXRAM30 :: txram [07:00] */
-#define BCHP_HIF_MSPI_TXRAM30_txram_MASK 0x000000ff
-#define BCHP_HIF_MSPI_TXRAM30_txram_SHIFT 0
-
-/***************************************************************************
- *TXRAM31 - Least significant byte of TXRAM[15] (queue pointer = 15)
- ***************************************************************************/
-/* HIF_MSPI :: TXRAM31 :: reserved0 [31:08] */
-#define BCHP_HIF_MSPI_TXRAM31_reserved0_MASK 0xffffff00
-#define BCHP_HIF_MSPI_TXRAM31_reserved0_SHIFT 8
-
-/* HIF_MSPI :: TXRAM31 :: txram [07:00] */
-#define BCHP_HIF_MSPI_TXRAM31_txram_MASK 0x000000ff
-#define BCHP_HIF_MSPI_TXRAM31_txram_SHIFT 0
-
-/***************************************************************************
- *RXRAM00 - Most significant byte of RXRAM[0] (queue pointer = 0)
- ***************************************************************************/
-/* HIF_MSPI :: RXRAM00 :: reserved0 [31:08] */
-#define BCHP_HIF_MSPI_RXRAM00_reserved0_MASK 0xffffff00
-#define BCHP_HIF_MSPI_RXRAM00_reserved0_SHIFT 8
-
-/* HIF_MSPI :: RXRAM00 :: rxram [07:00] */
-#define BCHP_HIF_MSPI_RXRAM00_rxram_MASK 0x000000ff
-#define BCHP_HIF_MSPI_RXRAM00_rxram_SHIFT 0
-
-/***************************************************************************
- *RXRAM01 - Least significant byte of RXRAM[0] (queue pointer = 0)
- ***************************************************************************/
-/* HIF_MSPI :: RXRAM01 :: reserved0 [31:08] */
-#define BCHP_HIF_MSPI_RXRAM01_reserved0_MASK 0xffffff00
-#define BCHP_HIF_MSPI_RXRAM01_reserved0_SHIFT 8
-
-/* HIF_MSPI :: RXRAM01 :: rxram [07:00] */
-#define BCHP_HIF_MSPI_RXRAM01_rxram_MASK 0x000000ff
-#define BCHP_HIF_MSPI_RXRAM01_rxram_SHIFT 0
-
-/***************************************************************************
- *RXRAM02 - Most significant byte of RXRAM[1] (queue pointer = 1)
- ***************************************************************************/
-/* HIF_MSPI :: RXRAM02 :: reserved0 [31:08] */
-#define BCHP_HIF_MSPI_RXRAM02_reserved0_MASK 0xffffff00
-#define BCHP_HIF_MSPI_RXRAM02_reserved0_SHIFT 8
-
-/* HIF_MSPI :: RXRAM02 :: rxram [07:00] */
-#define BCHP_HIF_MSPI_RXRAM02_rxram_MASK 0x000000ff
-#define BCHP_HIF_MSPI_RXRAM02_rxram_SHIFT 0
-
-/***************************************************************************
- *RXRAM03 - Least significant byte of RXRAM[1] (queue pointer = 1)
- ***************************************************************************/
-/* HIF_MSPI :: RXRAM03 :: reserved0 [31:08] */
-#define BCHP_HIF_MSPI_RXRAM03_reserved0_MASK 0xffffff00
-#define BCHP_HIF_MSPI_RXRAM03_reserved0_SHIFT 8
-
-/* HIF_MSPI :: RXRAM03 :: rxram [07:00] */
-#define BCHP_HIF_MSPI_RXRAM03_rxram_MASK 0x000000ff
-#define BCHP_HIF_MSPI_RXRAM03_rxram_SHIFT 0
-
-/***************************************************************************
- *RXRAM04 - Most significant byte of RXRAM[2] (queue pointer = 2)
- ***************************************************************************/
-/* HIF_MSPI :: RXRAM04 :: reserved0 [31:08] */
-#define BCHP_HIF_MSPI_RXRAM04_reserved0_MASK 0xffffff00
-#define BCHP_HIF_MSPI_RXRAM04_reserved0_SHIFT 8
-
-/* HIF_MSPI :: RXRAM04 :: rxram [07:00] */
-#define BCHP_HIF_MSPI_RXRAM04_rxram_MASK 0x000000ff
-#define BCHP_HIF_MSPI_RXRAM04_rxram_SHIFT 0
-
-/***************************************************************************
- *RXRAM05 - Least significant byte of RXRAM[2] (queue pointer = 2)
- ***************************************************************************/
-/* HIF_MSPI :: RXRAM05 :: reserved0 [31:08] */
-#define BCHP_HIF_MSPI_RXRAM05_reserved0_MASK 0xffffff00
-#define BCHP_HIF_MSPI_RXRAM05_reserved0_SHIFT 8
-
-/* HIF_MSPI :: RXRAM05 :: rxram [07:00] */
-#define BCHP_HIF_MSPI_RXRAM05_rxram_MASK 0x000000ff
-#define BCHP_HIF_MSPI_RXRAM05_rxram_SHIFT 0
-
-/***************************************************************************
- *RXRAM06 - Most significant byte of RXRAM[3] (queue pointer = 3)
- ***************************************************************************/
-/* HIF_MSPI :: RXRAM06 :: reserved0 [31:08] */
-#define BCHP_HIF_MSPI_RXRAM06_reserved0_MASK 0xffffff00
-#define BCHP_HIF_MSPI_RXRAM06_reserved0_SHIFT 8
-
-/* HIF_MSPI :: RXRAM06 :: rxram [07:00] */
-#define BCHP_HIF_MSPI_RXRAM06_rxram_MASK 0x000000ff
-#define BCHP_HIF_MSPI_RXRAM06_rxram_SHIFT 0
-
-/***************************************************************************
- *RXRAM07 - Least significant byte of RXRAM[3] (queue pointer = 3)
- ***************************************************************************/
-/* HIF_MSPI :: RXRAM07 :: reserved0 [31:08] */
-#define BCHP_HIF_MSPI_RXRAM07_reserved0_MASK 0xffffff00
-#define BCHP_HIF_MSPI_RXRAM07_reserved0_SHIFT 8
-
-/* HIF_MSPI :: RXRAM07 :: rxram [07:00] */
-#define BCHP_HIF_MSPI_RXRAM07_rxram_MASK 0x000000ff
-#define BCHP_HIF_MSPI_RXRAM07_rxram_SHIFT 0
-
-/***************************************************************************
- *RXRAM08 - Most significant byte of RXRAM[4] (queue pointer = 4)
- ***************************************************************************/
-/* HIF_MSPI :: RXRAM08 :: reserved0 [31:08] */
-#define BCHP_HIF_MSPI_RXRAM08_reserved0_MASK 0xffffff00
-#define BCHP_HIF_MSPI_RXRAM08_reserved0_SHIFT 8
-
-/* HIF_MSPI :: RXRAM08 :: rxram [07:00] */
-#define BCHP_HIF_MSPI_RXRAM08_rxram_MASK 0x000000ff
-#define BCHP_HIF_MSPI_RXRAM08_rxram_SHIFT 0
-
-/***************************************************************************
- *RXRAM09 - Least significant byte of RXRAM[4] (queue pointer = 4)
- ***************************************************************************/
-/* HIF_MSPI :: RXRAM09 :: reserved0 [31:08] */
-#define BCHP_HIF_MSPI_RXRAM09_reserved0_MASK 0xffffff00
-#define BCHP_HIF_MSPI_RXRAM09_reserved0_SHIFT 8
-
-/* HIF_MSPI :: RXRAM09 :: rxram [07:00] */
-#define BCHP_HIF_MSPI_RXRAM09_rxram_MASK 0x000000ff
-#define BCHP_HIF_MSPI_RXRAM09_rxram_SHIFT 0
-
-/***************************************************************************
- *RXRAM10 - Most significant byte of RXRAM[5] (queue pointer = 5)
- ***************************************************************************/
-/* HIF_MSPI :: RXRAM10 :: reserved0 [31:08] */
-#define BCHP_HIF_MSPI_RXRAM10_reserved0_MASK 0xffffff00
-#define BCHP_HIF_MSPI_RXRAM10_reserved0_SHIFT 8
-
-/* HIF_MSPI :: RXRAM10 :: rxram [07:00] */
-#define BCHP_HIF_MSPI_RXRAM10_rxram_MASK 0x000000ff
-#define BCHP_HIF_MSPI_RXRAM10_rxram_SHIFT 0
-
-/***************************************************************************
- *RXRAM11 - Least significant byte of RXRAM[5] (queue pointer = 5)
- ***************************************************************************/
-/* HIF_MSPI :: RXRAM11 :: reserved0 [31:08] */
-#define BCHP_HIF_MSPI_RXRAM11_reserved0_MASK 0xffffff00
-#define BCHP_HIF_MSPI_RXRAM11_reserved0_SHIFT 8
-
-/* HIF_MSPI :: RXRAM11 :: rxram [07:00] */
-#define BCHP_HIF_MSPI_RXRAM11_rxram_MASK 0x000000ff
-#define BCHP_HIF_MSPI_RXRAM11_rxram_SHIFT 0
-
-/***************************************************************************
- *RXRAM12 - Most significant byte of RXRAM[6] (queue pointer = 6)
- ***************************************************************************/
-/* HIF_MSPI :: RXRAM12 :: reserved0 [31:08] */
-#define BCHP_HIF_MSPI_RXRAM12_reserved0_MASK 0xffffff00
-#define BCHP_HIF_MSPI_RXRAM12_reserved0_SHIFT 8
-
-/* HIF_MSPI :: RXRAM12 :: rxram [07:00] */
-#define BCHP_HIF_MSPI_RXRAM12_rxram_MASK 0x000000ff
-#define BCHP_HIF_MSPI_RXRAM12_rxram_SHIFT 0
-
-/***************************************************************************
- *RXRAM13 - Least significant byte of RXRAM[6] (queue pointer = 6)
- ***************************************************************************/
-/* HIF_MSPI :: RXRAM13 :: reserved0 [31:08] */
-#define BCHP_HIF_MSPI_RXRAM13_reserved0_MASK 0xffffff00
-#define BCHP_HIF_MSPI_RXRAM13_reserved0_SHIFT 8
-
-/* HIF_MSPI :: RXRAM13 :: rxram [07:00] */
-#define BCHP_HIF_MSPI_RXRAM13_rxram_MASK 0x000000ff
-#define BCHP_HIF_MSPI_RXRAM13_rxram_SHIFT 0
-
-/***************************************************************************
- *RXRAM14 - Most significant byte of RXRAM[7] (queue pointer = 7)
- ***************************************************************************/
-/* HIF_MSPI :: RXRAM14 :: reserved0 [31:08] */
-#define BCHP_HIF_MSPI_RXRAM14_reserved0_MASK 0xffffff00
-#define BCHP_HIF_MSPI_RXRAM14_reserved0_SHIFT 8
-
-/* HIF_MSPI :: RXRAM14 :: rxram [07:00] */
-#define BCHP_HIF_MSPI_RXRAM14_rxram_MASK 0x000000ff
-#define BCHP_HIF_MSPI_RXRAM14_rxram_SHIFT 0
-
-/***************************************************************************
- *RXRAM15 - Least significant byte of RXRAM[7] (queue pointer = 7)
- ***************************************************************************/
-/* HIF_MSPI :: RXRAM15 :: reserved0 [31:08] */
-#define BCHP_HIF_MSPI_RXRAM15_reserved0_MASK 0xffffff00
-#define BCHP_HIF_MSPI_RXRAM15_reserved0_SHIFT 8
-
-/* HIF_MSPI :: RXRAM15 :: rxram [07:00] */
-#define BCHP_HIF_MSPI_RXRAM15_rxram_MASK 0x000000ff
-#define BCHP_HIF_MSPI_RXRAM15_rxram_SHIFT 0
-
-/***************************************************************************
- *RXRAM16 - Most significant byte of RXRAM[8] (queue pointer = 8)
- ***************************************************************************/
-/* HIF_MSPI :: RXRAM16 :: reserved0 [31:08] */
-#define BCHP_HIF_MSPI_RXRAM16_reserved0_MASK 0xffffff00
-#define BCHP_HIF_MSPI_RXRAM16_reserved0_SHIFT 8
-
-/* HIF_MSPI :: RXRAM16 :: rxram [07:00] */
-#define BCHP_HIF_MSPI_RXRAM16_rxram_MASK 0x000000ff
-#define BCHP_HIF_MSPI_RXRAM16_rxram_SHIFT 0
-
-/***************************************************************************
- *RXRAM17 - Least significant byte of RXRAM[8] (queue pointer = 8)
- ***************************************************************************/
-/* HIF_MSPI :: RXRAM17 :: reserved0 [31:08] */
-#define BCHP_HIF_MSPI_RXRAM17_reserved0_MASK 0xffffff00
-#define BCHP_HIF_MSPI_RXRAM17_reserved0_SHIFT 8
-
-/* HIF_MSPI :: RXRAM17 :: rxram [07:00] */
-#define BCHP_HIF_MSPI_RXRAM17_rxram_MASK 0x000000ff
-#define BCHP_HIF_MSPI_RXRAM17_rxram_SHIFT 0
-
-/***************************************************************************
- *RXRAM18 - Most significant byte of RXRAM[9] (queue pointer = 9)
- ***************************************************************************/
-/* HIF_MSPI :: RXRAM18 :: reserved0 [31:08] */
-#define BCHP_HIF_MSPI_RXRAM18_reserved0_MASK 0xffffff00
-#define BCHP_HIF_MSPI_RXRAM18_reserved0_SHIFT 8
-
-/* HIF_MSPI :: RXRAM18 :: rxram [07:00] */
-#define BCHP_HIF_MSPI_RXRAM18_rxram_MASK 0x000000ff
-#define BCHP_HIF_MSPI_RXRAM18_rxram_SHIFT 0
-
-/***************************************************************************
- *RXRAM19 - Least significant byte of RXRAM[9] (queue pointer = 9)
- ***************************************************************************/
-/* HIF_MSPI :: RXRAM19 :: reserved0 [31:08] */
-#define BCHP_HIF_MSPI_RXRAM19_reserved0_MASK 0xffffff00
-#define BCHP_HIF_MSPI_RXRAM19_reserved0_SHIFT 8
-
-/* HIF_MSPI :: RXRAM19 :: rxram [07:00] */
-#define BCHP_HIF_MSPI_RXRAM19_rxram_MASK 0x000000ff
-#define BCHP_HIF_MSPI_RXRAM19_rxram_SHIFT 0
-
-/***************************************************************************
- *RXRAM20 - Most significant byte of RXRAM[10] (queue pointer = 10)
- ***************************************************************************/
-/* HIF_MSPI :: RXRAM20 :: reserved0 [31:08] */
-#define BCHP_HIF_MSPI_RXRAM20_reserved0_MASK 0xffffff00
-#define BCHP_HIF_MSPI_RXRAM20_reserved0_SHIFT 8
-
-/* HIF_MSPI :: RXRAM20 :: rxram [07:00] */
-#define BCHP_HIF_MSPI_RXRAM20_rxram_MASK 0x000000ff
-#define BCHP_HIF_MSPI_RXRAM20_rxram_SHIFT 0
-
-/***************************************************************************
- *RXRAM21 - Least significant byte of RXRAM[10] (queue pointer = 10)
- ***************************************************************************/
-/* HIF_MSPI :: RXRAM21 :: reserved0 [31:08] */
-#define BCHP_HIF_MSPI_RXRAM21_reserved0_MASK 0xffffff00
-#define BCHP_HIF_MSPI_RXRAM21_reserved0_SHIFT 8
-
-/* HIF_MSPI :: RXRAM21 :: rxram [07:00] */
-#define BCHP_HIF_MSPI_RXRAM21_rxram_MASK 0x000000ff
-#define BCHP_HIF_MSPI_RXRAM21_rxram_SHIFT 0
-
-/***************************************************************************
- *RXRAM22 - Most significant byte of RXRAM[11] (queue pointer = 11)
- ***************************************************************************/
-/* HIF_MSPI :: RXRAM22 :: reserved0 [31:08] */
-#define BCHP_HIF_MSPI_RXRAM22_reserved0_MASK 0xffffff00
-#define BCHP_HIF_MSPI_RXRAM22_reserved0_SHIFT 8
-
-/* HIF_MSPI :: RXRAM22 :: rxram [07:00] */
-#define BCHP_HIF_MSPI_RXRAM22_rxram_MASK 0x000000ff
-#define BCHP_HIF_MSPI_RXRAM22_rxram_SHIFT 0
-
-/***************************************************************************
- *RXRAM23 - Least significant byte of RXRAM[11] (queue pointer = 11)
- ***************************************************************************/
-/* HIF_MSPI :: RXRAM23 :: reserved0 [31:08] */
-#define BCHP_HIF_MSPI_RXRAM23_reserved0_MASK 0xffffff00
-#define BCHP_HIF_MSPI_RXRAM23_reserved0_SHIFT 8
-
-/* HIF_MSPI :: RXRAM23 :: rxram [07:00] */
-#define BCHP_HIF_MSPI_RXRAM23_rxram_MASK 0x000000ff
-#define BCHP_HIF_MSPI_RXRAM23_rxram_SHIFT 0
-
-/***************************************************************************
- *RXRAM24 - Most significant byte of RXRAM[12] (queue pointer = 12)
- ***************************************************************************/
-/* HIF_MSPI :: RXRAM24 :: reserved0 [31:08] */
-#define BCHP_HIF_MSPI_RXRAM24_reserved0_MASK 0xffffff00
-#define BCHP_HIF_MSPI_RXRAM24_reserved0_SHIFT 8
-
-/* HIF_MSPI :: RXRAM24 :: rxram [07:00] */
-#define BCHP_HIF_MSPI_RXRAM24_rxram_MASK 0x000000ff
-#define BCHP_HIF_MSPI_RXRAM24_rxram_SHIFT 0
-
-/***************************************************************************
- *RXRAM25 - Least significant byte of RXRAM[12] (queue pointer = 12)
- ***************************************************************************/
-/* HIF_MSPI :: RXRAM25 :: reserved0 [31:08] */
-#define BCHP_HIF_MSPI_RXRAM25_reserved0_MASK 0xffffff00
-#define BCHP_HIF_MSPI_RXRAM25_reserved0_SHIFT 8
-
-/* HIF_MSPI :: RXRAM25 :: rxram [07:00] */
-#define BCHP_HIF_MSPI_RXRAM25_rxram_MASK 0x000000ff
-#define BCHP_HIF_MSPI_RXRAM25_rxram_SHIFT 0
-
-/***************************************************************************
- *RXRAM26 - Most significant byte of RXRAM[13] (queue pointer = 13)
- ***************************************************************************/
-/* HIF_MSPI :: RXRAM26 :: reserved0 [31:08] */
-#define BCHP_HIF_MSPI_RXRAM26_reserved0_MASK 0xffffff00
-#define BCHP_HIF_MSPI_RXRAM26_reserved0_SHIFT 8
-
-/* HIF_MSPI :: RXRAM26 :: rxram [07:00] */
-#define BCHP_HIF_MSPI_RXRAM26_rxram_MASK 0x000000ff
-#define BCHP_HIF_MSPI_RXRAM26_rxram_SHIFT 0
-
-/***************************************************************************
- *RXRAM27 - Least significant byte of RXRAM[13] (queue pointer = 13)
- ***************************************************************************/
-/* HIF_MSPI :: RXRAM27 :: reserved0 [31:08] */
-#define BCHP_HIF_MSPI_RXRAM27_reserved0_MASK 0xffffff00
-#define BCHP_HIF_MSPI_RXRAM27_reserved0_SHIFT 8
-
-/* HIF_MSPI :: RXRAM27 :: rxram [07:00] */
-#define BCHP_HIF_MSPI_RXRAM27_rxram_MASK 0x000000ff
-#define BCHP_HIF_MSPI_RXRAM27_rxram_SHIFT 0
-
-/***************************************************************************
- *RXRAM28 - Most significant byte of RXRAM[14] (queue pointer = 14)
- ***************************************************************************/
-/* HIF_MSPI :: RXRAM28 :: reserved0 [31:08] */
-#define BCHP_HIF_MSPI_RXRAM28_reserved0_MASK 0xffffff00
-#define BCHP_HIF_MSPI_RXRAM28_reserved0_SHIFT 8
-
-/* HIF_MSPI :: RXRAM28 :: rxram [07:00] */
-#define BCHP_HIF_MSPI_RXRAM28_rxram_MASK 0x000000ff
-#define BCHP_HIF_MSPI_RXRAM28_rxram_SHIFT 0
-
-/***************************************************************************
- *RXRAM29 - Least significant byte of RXRAM[14] (queue pointer = 14)
- ***************************************************************************/
-/* HIF_MSPI :: RXRAM29 :: reserved0 [31:08] */
-#define BCHP_HIF_MSPI_RXRAM29_reserved0_MASK 0xffffff00
-#define BCHP_HIF_MSPI_RXRAM29_reserved0_SHIFT 8
-
-/* HIF_MSPI :: RXRAM29 :: rxram [07:00] */
-#define BCHP_HIF_MSPI_RXRAM29_rxram_MASK 0x000000ff
-#define BCHP_HIF_MSPI_RXRAM29_rxram_SHIFT 0
-
-/***************************************************************************
- *RXRAM30 - Most significant byte of RXRAM[15] (queue pointer = 15)
- ***************************************************************************/
-/* HIF_MSPI :: RXRAM30 :: reserved0 [31:08] */
-#define BCHP_HIF_MSPI_RXRAM30_reserved0_MASK 0xffffff00
-#define BCHP_HIF_MSPI_RXRAM30_reserved0_SHIFT 8
-
-/* HIF_MSPI :: RXRAM30 :: rxram [07:00] */
-#define BCHP_HIF_MSPI_RXRAM30_rxram_MASK 0x000000ff
-#define BCHP_HIF_MSPI_RXRAM30_rxram_SHIFT 0
-
-/***************************************************************************
- *RXRAM31 - Least significant byte of RXRAM[15] (queue pointer = 15)
- ***************************************************************************/
-/* HIF_MSPI :: RXRAM31 :: reserved0 [31:08] */
-#define BCHP_HIF_MSPI_RXRAM31_reserved0_MASK 0xffffff00
-#define BCHP_HIF_MSPI_RXRAM31_reserved0_SHIFT 8
-
-/* HIF_MSPI :: RXRAM31 :: rxram [07:00] */
-#define BCHP_HIF_MSPI_RXRAM31_rxram_MASK 0x000000ff
-#define BCHP_HIF_MSPI_RXRAM31_rxram_SHIFT 0
-
-/***************************************************************************
- *CDRAM00 - 8-bit command (queue pointer = 0)
- ***************************************************************************/
-/* HIF_MSPI :: CDRAM00 :: reserved0 [31:09] */
-#define BCHP_HIF_MSPI_CDRAM00_reserved0_MASK 0xfffffe00
-#define BCHP_HIF_MSPI_CDRAM00_reserved0_SHIFT 9
-
-/* HIF_MSPI :: CDRAM00 :: cdram [08:00] */
-#define BCHP_HIF_MSPI_CDRAM00_cdram_MASK 0x000001ff
-#define BCHP_HIF_MSPI_CDRAM00_cdram_SHIFT 0
-
-/***************************************************************************
- *CDRAM01 - 8-bit command (queue pointer = 1)
- ***************************************************************************/
-/* HIF_MSPI :: CDRAM01 :: reserved0 [31:09] */
-#define BCHP_HIF_MSPI_CDRAM01_reserved0_MASK 0xfffffe00
-#define BCHP_HIF_MSPI_CDRAM01_reserved0_SHIFT 9
-
-/* HIF_MSPI :: CDRAM01 :: cdram [08:00] */
-#define BCHP_HIF_MSPI_CDRAM01_cdram_MASK 0x000001ff
-#define BCHP_HIF_MSPI_CDRAM01_cdram_SHIFT 0
-
-/***************************************************************************
- *CDRAM02 - 8-bit command (queue pointer = 2)
- ***************************************************************************/
-/* HIF_MSPI :: CDRAM02 :: reserved0 [31:09] */
-#define BCHP_HIF_MSPI_CDRAM02_reserved0_MASK 0xfffffe00
-#define BCHP_HIF_MSPI_CDRAM02_reserved0_SHIFT 9
-
-/* HIF_MSPI :: CDRAM02 :: cdram [08:00] */
-#define BCHP_HIF_MSPI_CDRAM02_cdram_MASK 0x000001ff
-#define BCHP_HIF_MSPI_CDRAM02_cdram_SHIFT 0
-
-/***************************************************************************
- *CDRAM03 - 8-bit command (queue pointer = 3)
- ***************************************************************************/
-/* HIF_MSPI :: CDRAM03 :: reserved0 [31:09] */
-#define BCHP_HIF_MSPI_CDRAM03_reserved0_MASK 0xfffffe00
-#define BCHP_HIF_MSPI_CDRAM03_reserved0_SHIFT 9
-
-/* HIF_MSPI :: CDRAM03 :: cdram [08:00] */
-#define BCHP_HIF_MSPI_CDRAM03_cdram_MASK 0x000001ff
-#define BCHP_HIF_MSPI_CDRAM03_cdram_SHIFT 0
-
-/***************************************************************************
- *CDRAM04 - 8-bit command (queue pointer = 4)
- ***************************************************************************/
-/* HIF_MSPI :: CDRAM04 :: reserved0 [31:09] */
-#define BCHP_HIF_MSPI_CDRAM04_reserved0_MASK 0xfffffe00
-#define BCHP_HIF_MSPI_CDRAM04_reserved0_SHIFT 9
-
-/* HIF_MSPI :: CDRAM04 :: cdram [08:00] */
-#define BCHP_HIF_MSPI_CDRAM04_cdram_MASK 0x000001ff
-#define BCHP_HIF_MSPI_CDRAM04_cdram_SHIFT 0
-
-/***************************************************************************
- *CDRAM05 - 8-bit command (queue pointer = 5)
- ***************************************************************************/
-/* HIF_MSPI :: CDRAM05 :: reserved0 [31:09] */
-#define BCHP_HIF_MSPI_CDRAM05_reserved0_MASK 0xfffffe00
-#define BCHP_HIF_MSPI_CDRAM05_reserved0_SHIFT 9
-
-/* HIF_MSPI :: CDRAM05 :: cdram [08:00] */
-#define BCHP_HIF_MSPI_CDRAM05_cdram_MASK 0x000001ff
-#define BCHP_HIF_MSPI_CDRAM05_cdram_SHIFT 0
-
-/***************************************************************************
- *CDRAM06 - 8-bit command (queue pointer = 6)
- ***************************************************************************/
-/* HIF_MSPI :: CDRAM06 :: reserved0 [31:09] */
-#define BCHP_HIF_MSPI_CDRAM06_reserved0_MASK 0xfffffe00
-#define BCHP_HIF_MSPI_CDRAM06_reserved0_SHIFT 9
-
-/* HIF_MSPI :: CDRAM06 :: cdram [08:00] */
-#define BCHP_HIF_MSPI_CDRAM06_cdram_MASK 0x000001ff
-#define BCHP_HIF_MSPI_CDRAM06_cdram_SHIFT 0
-
-/***************************************************************************
- *CDRAM07 - 8-bit command (queue pointer = 7)
- ***************************************************************************/
-/* HIF_MSPI :: CDRAM07 :: reserved0 [31:09] */
-#define BCHP_HIF_MSPI_CDRAM07_reserved0_MASK 0xfffffe00
-#define BCHP_HIF_MSPI_CDRAM07_reserved0_SHIFT 9
-
-/* HIF_MSPI :: CDRAM07 :: cdram [08:00] */
-#define BCHP_HIF_MSPI_CDRAM07_cdram_MASK 0x000001ff
-#define BCHP_HIF_MSPI_CDRAM07_cdram_SHIFT 0
-
-/***************************************************************************
- *CDRAM08 - 8-bit command (queue pointer = 8)
- ***************************************************************************/
-/* HIF_MSPI :: CDRAM08 :: reserved0 [31:09] */
-#define BCHP_HIF_MSPI_CDRAM08_reserved0_MASK 0xfffffe00
-#define BCHP_HIF_MSPI_CDRAM08_reserved0_SHIFT 9
-
-/* HIF_MSPI :: CDRAM08 :: cdram [08:00] */
-#define BCHP_HIF_MSPI_CDRAM08_cdram_MASK 0x000001ff
-#define BCHP_HIF_MSPI_CDRAM08_cdram_SHIFT 0
-
-/***************************************************************************
- *CDRAM09 - 8-bit command (queue pointer = 9)
- ***************************************************************************/
-/* HIF_MSPI :: CDRAM09 :: reserved0 [31:09] */
-#define BCHP_HIF_MSPI_CDRAM09_reserved0_MASK 0xfffffe00
-#define BCHP_HIF_MSPI_CDRAM09_reserved0_SHIFT 9
-
-/* HIF_MSPI :: CDRAM09 :: cdram [08:00] */
-#define BCHP_HIF_MSPI_CDRAM09_cdram_MASK 0x000001ff
-#define BCHP_HIF_MSPI_CDRAM09_cdram_SHIFT 0
-
-/***************************************************************************
- *CDRAM10 - 8-bit command (queue pointer = a)
- ***************************************************************************/
-/* HIF_MSPI :: CDRAM10 :: reserved0 [31:09] */
-#define BCHP_HIF_MSPI_CDRAM10_reserved0_MASK 0xfffffe00
-#define BCHP_HIF_MSPI_CDRAM10_reserved0_SHIFT 9
-
-/* HIF_MSPI :: CDRAM10 :: cdram [08:00] */
-#define BCHP_HIF_MSPI_CDRAM10_cdram_MASK 0x000001ff
-#define BCHP_HIF_MSPI_CDRAM10_cdram_SHIFT 0
-
-/***************************************************************************
- *CDRAM11 - 8-bit command (queue pointer = b)
- ***************************************************************************/
-/* HIF_MSPI :: CDRAM11 :: reserved0 [31:09] */
-#define BCHP_HIF_MSPI_CDRAM11_reserved0_MASK 0xfffffe00
-#define BCHP_HIF_MSPI_CDRAM11_reserved0_SHIFT 9
-
-/* HIF_MSPI :: CDRAM11 :: cdram [08:00] */
-#define BCHP_HIF_MSPI_CDRAM11_cdram_MASK 0x000001ff
-#define BCHP_HIF_MSPI_CDRAM11_cdram_SHIFT 0
-
-/***************************************************************************
- *CDRAM12 - 8-bit command (queue pointer = c)
- ***************************************************************************/
-/* HIF_MSPI :: CDRAM12 :: reserved0 [31:09] */
-#define BCHP_HIF_MSPI_CDRAM12_reserved0_MASK 0xfffffe00
-#define BCHP_HIF_MSPI_CDRAM12_reserved0_SHIFT 9
-
-/* HIF_MSPI :: CDRAM12 :: cdram [08:00] */
-#define BCHP_HIF_MSPI_CDRAM12_cdram_MASK 0x000001ff
-#define BCHP_HIF_MSPI_CDRAM12_cdram_SHIFT 0
-
-/***************************************************************************
- *CDRAM13 - 8-bit command (queue pointer = d)
- ***************************************************************************/
-/* HIF_MSPI :: CDRAM13 :: reserved0 [31:09] */
-#define BCHP_HIF_MSPI_CDRAM13_reserved0_MASK 0xfffffe00
-#define BCHP_HIF_MSPI_CDRAM13_reserved0_SHIFT 9
-
-/* HIF_MSPI :: CDRAM13 :: cdram [08:00] */
-#define BCHP_HIF_MSPI_CDRAM13_cdram_MASK 0x000001ff
-#define BCHP_HIF_MSPI_CDRAM13_cdram_SHIFT 0
-
-/***************************************************************************
- *CDRAM14 - 8-bit command (queue pointer = e)
- ***************************************************************************/
-/* HIF_MSPI :: CDRAM14 :: reserved0 [31:09] */
-#define BCHP_HIF_MSPI_CDRAM14_reserved0_MASK 0xfffffe00
-#define BCHP_HIF_MSPI_CDRAM14_reserved0_SHIFT 9
-
-/* HIF_MSPI :: CDRAM14 :: cdram [08:00] */
-#define BCHP_HIF_MSPI_CDRAM14_cdram_MASK 0x000001ff
-#define BCHP_HIF_MSPI_CDRAM14_cdram_SHIFT 0
-
-/***************************************************************************
- *CDRAM15 - 8-bit command (queue pointer = f)
- ***************************************************************************/
-/* HIF_MSPI :: CDRAM15 :: reserved0 [31:09] */
-#define BCHP_HIF_MSPI_CDRAM15_reserved0_MASK 0xfffffe00
-#define BCHP_HIF_MSPI_CDRAM15_reserved0_SHIFT 9
-
-/* HIF_MSPI :: CDRAM15 :: cdram [08:00] */
-#define BCHP_HIF_MSPI_CDRAM15_cdram_MASK 0x000001ff
-#define BCHP_HIF_MSPI_CDRAM15_cdram_SHIFT 0
-
-/***************************************************************************
- *WRITE_LOCK - Control bit to lock group of write commands
- ***************************************************************************/
-/* HIF_MSPI :: WRITE_LOCK :: reserved0 [31:01] */
-#define BCHP_HIF_MSPI_WRITE_LOCK_reserved0_MASK 0xfffffffe
-#define BCHP_HIF_MSPI_WRITE_LOCK_reserved0_SHIFT 1
-
-/* HIF_MSPI :: WRITE_LOCK :: WriteLock [00:00] */
-#define BCHP_HIF_MSPI_WRITE_LOCK_WriteLock_MASK 0x00000001
-#define BCHP_HIF_MSPI_WRITE_LOCK_WriteLock_SHIFT 0
-#define BCHP_HIF_MSPI_WRITE_LOCK_WriteLock_DEFAULT 0x00000000
-
-/***************************************************************************
- *DISABLE_FLUSH_GEN - Debug bit to mask the generation of flush signals from Mspi
- ***************************************************************************/
-/* HIF_MSPI :: DISABLE_FLUSH_GEN :: reserved0 [31:01] */
-#define BCHP_HIF_MSPI_DISABLE_FLUSH_GEN_reserved0_MASK 0xfffffffe
-#define BCHP_HIF_MSPI_DISABLE_FLUSH_GEN_reserved0_SHIFT 1
-
-/* HIF_MSPI :: DISABLE_FLUSH_GEN :: DisableFlushGen [00:00] */
-#define BCHP_HIF_MSPI_DISABLE_FLUSH_GEN_DisableFlushGen_MASK 0x00000001
-#define BCHP_HIF_MSPI_DISABLE_FLUSH_GEN_DisableFlushGen_SHIFT 0
-#define BCHP_HIF_MSPI_DISABLE_FLUSH_GEN_DisableFlushGen_DEFAULT 0x00000000
-
-#endif /* #ifndef BCHP_HIF_MSPI_H__ */
-
-/* End of File */
diff --git a/include/linux/brcmstb/7145a0/bchp_hif_spi_intr2.h b/include/linux/brcmstb/7145a0/bchp_hif_spi_intr2.h
deleted file mode 100644
index c9f929c..0000000
--- a/include/linux/brcmstb/7145a0/bchp_hif_spi_intr2.h
+++ /dev/null
@@ -1,564 +0,0 @@
-/***************************************************************************
- * Copyright (c) 1999-2013, Broadcom Corporation
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
- *
- * Module Description:
- * DO NOT EDIT THIS FILE DIRECTLY
- *
- * This module was generated magically with RDB from a source description
- * file. You must edit the source file for changes to be made to this file.
- *
- *
- * Date: Generated on Sat Apr 6 03:07:44 2013
- * MD5 Checksum d41d8cd98f00b204e9800998ecf8427e
- *
- * Compiled with: RDB Utility combo_header.pl
- * RDB Parser 3.0
- * unknown unknown
- * Perl Interpreter 5.008008
- * Operating System linux
- *
- * Revision History:
- *
- * $brcm_Log: $
- *
- ***************************************************************************/
-
-#ifndef BCHP_HIF_SPI_INTR2_H__
-#define BCHP_HIF_SPI_INTR2_H__
-
-/***************************************************************************
- *HIF_SPI_INTR2 - HIF Level 2 Interrupt Controller Registers for SPI
- ***************************************************************************/
-#define BCHP_HIF_SPI_INTR2_CPU_STATUS 0x203d1a00 /* CPU interrupt Status Register */
-#define BCHP_HIF_SPI_INTR2_CPU_SET 0x203d1a04 /* CPU interrupt Set Register */
-#define BCHP_HIF_SPI_INTR2_CPU_CLEAR 0x203d1a08 /* CPU interrupt Clear Register */
-#define BCHP_HIF_SPI_INTR2_CPU_MASK_STATUS 0x203d1a0c /* CPU interrupt Mask Status Register */
-#define BCHP_HIF_SPI_INTR2_CPU_MASK_SET 0x203d1a10 /* CPU interrupt Mask Set Register */
-#define BCHP_HIF_SPI_INTR2_CPU_MASK_CLEAR 0x203d1a14 /* CPU interrupt Mask Clear Register */
-#define BCHP_HIF_SPI_INTR2_PCI_STATUS 0x203d1a18 /* PCI interrupt Status Register */
-#define BCHP_HIF_SPI_INTR2_PCI_SET 0x203d1a1c /* PCI interrupt Set Register */
-#define BCHP_HIF_SPI_INTR2_PCI_CLEAR 0x203d1a20 /* PCI interrupt Clear Register */
-#define BCHP_HIF_SPI_INTR2_PCI_MASK_STATUS 0x203d1a24 /* PCI interrupt Mask Status Register */
-#define BCHP_HIF_SPI_INTR2_PCI_MASK_SET 0x203d1a28 /* PCI interrupt Mask Set Register */
-#define BCHP_HIF_SPI_INTR2_PCI_MASK_CLEAR 0x203d1a2c /* PCI interrupt Mask Clear Register */
-
-/***************************************************************************
- *CPU_STATUS - CPU interrupt Status Register
- ***************************************************************************/
-/* HIF_SPI_INTR2 :: CPU_STATUS :: reserved0 [31:07] */
-#define BCHP_HIF_SPI_INTR2_CPU_STATUS_reserved0_MASK 0xffffff80
-#define BCHP_HIF_SPI_INTR2_CPU_STATUS_reserved0_SHIFT 7
-
-/* HIF_SPI_INTR2 :: CPU_STATUS :: MSPI_HALTED [06:06] */
-#define BCHP_HIF_SPI_INTR2_CPU_STATUS_MSPI_HALTED_MASK 0x00000040
-#define BCHP_HIF_SPI_INTR2_CPU_STATUS_MSPI_HALTED_SHIFT 6
-#define BCHP_HIF_SPI_INTR2_CPU_STATUS_MSPI_HALTED_DEFAULT 0x00000000
-
-/* HIF_SPI_INTR2 :: CPU_STATUS :: MSPI_DONE [05:05] */
-#define BCHP_HIF_SPI_INTR2_CPU_STATUS_MSPI_DONE_MASK 0x00000020
-#define BCHP_HIF_SPI_INTR2_CPU_STATUS_MSPI_DONE_SHIFT 5
-#define BCHP_HIF_SPI_INTR2_CPU_STATUS_MSPI_DONE_DEFAULT 0x00000000
-
-/* HIF_SPI_INTR2 :: CPU_STATUS :: SPI_LR_OVERREAD [04:04] */
-#define BCHP_HIF_SPI_INTR2_CPU_STATUS_SPI_LR_OVERREAD_MASK 0x00000010
-#define BCHP_HIF_SPI_INTR2_CPU_STATUS_SPI_LR_OVERREAD_SHIFT 4
-#define BCHP_HIF_SPI_INTR2_CPU_STATUS_SPI_LR_OVERREAD_DEFAULT 0x00000000
-
-/* HIF_SPI_INTR2 :: CPU_STATUS :: SPI_LR_SESSION_DONE [03:03] */
-#define BCHP_HIF_SPI_INTR2_CPU_STATUS_SPI_LR_SESSION_DONE_MASK 0x00000008
-#define BCHP_HIF_SPI_INTR2_CPU_STATUS_SPI_LR_SESSION_DONE_SHIFT 3
-#define BCHP_HIF_SPI_INTR2_CPU_STATUS_SPI_LR_SESSION_DONE_DEFAULT 0x00000000
-
-/* HIF_SPI_INTR2 :: CPU_STATUS :: SPI_LR_IMPATIENT [02:02] */
-#define BCHP_HIF_SPI_INTR2_CPU_STATUS_SPI_LR_IMPATIENT_MASK 0x00000004
-#define BCHP_HIF_SPI_INTR2_CPU_STATUS_SPI_LR_IMPATIENT_SHIFT 2
-#define BCHP_HIF_SPI_INTR2_CPU_STATUS_SPI_LR_IMPATIENT_DEFAULT 0x00000000
-
-/* HIF_SPI_INTR2 :: CPU_STATUS :: SPI_LR_SESSION_ABORTED [01:01] */
-#define BCHP_HIF_SPI_INTR2_CPU_STATUS_SPI_LR_SESSION_ABORTED_MASK 0x00000002
-#define BCHP_HIF_SPI_INTR2_CPU_STATUS_SPI_LR_SESSION_ABORTED_SHIFT 1
-#define BCHP_HIF_SPI_INTR2_CPU_STATUS_SPI_LR_SESSION_ABORTED_DEFAULT 0x00000000
-
-/* HIF_SPI_INTR2 :: CPU_STATUS :: SPI_LR_FULLNESS_REACHED [00:00] */
-#define BCHP_HIF_SPI_INTR2_CPU_STATUS_SPI_LR_FULLNESS_REACHED_MASK 0x00000001
-#define BCHP_HIF_SPI_INTR2_CPU_STATUS_SPI_LR_FULLNESS_REACHED_SHIFT 0
-#define BCHP_HIF_SPI_INTR2_CPU_STATUS_SPI_LR_FULLNESS_REACHED_DEFAULT 0x00000000
-
-/***************************************************************************
- *CPU_SET - CPU interrupt Set Register
- ***************************************************************************/
-/* HIF_SPI_INTR2 :: CPU_SET :: reserved0 [31:07] */
-#define BCHP_HIF_SPI_INTR2_CPU_SET_reserved0_MASK 0xffffff80
-#define BCHP_HIF_SPI_INTR2_CPU_SET_reserved0_SHIFT 7
-
-/* HIF_SPI_INTR2 :: CPU_SET :: MSPI_HALTED [06:06] */
-#define BCHP_HIF_SPI_INTR2_CPU_SET_MSPI_HALTED_MASK 0x00000040
-#define BCHP_HIF_SPI_INTR2_CPU_SET_MSPI_HALTED_SHIFT 6
-#define BCHP_HIF_SPI_INTR2_CPU_SET_MSPI_HALTED_DEFAULT 0x00000000
-
-/* HIF_SPI_INTR2 :: CPU_SET :: MSPI_DONE [05:05] */
-#define BCHP_HIF_SPI_INTR2_CPU_SET_MSPI_DONE_MASK 0x00000020
-#define BCHP_HIF_SPI_INTR2_CPU_SET_MSPI_DONE_SHIFT 5
-#define BCHP_HIF_SPI_INTR2_CPU_SET_MSPI_DONE_DEFAULT 0x00000000
-
-/* HIF_SPI_INTR2 :: CPU_SET :: SPI_LR_OVERREAD [04:04] */
-#define BCHP_HIF_SPI_INTR2_CPU_SET_SPI_LR_OVERREAD_MASK 0x00000010
-#define BCHP_HIF_SPI_INTR2_CPU_SET_SPI_LR_OVERREAD_SHIFT 4
-#define BCHP_HIF_SPI_INTR2_CPU_SET_SPI_LR_OVERREAD_DEFAULT 0x00000000
-
-/* HIF_SPI_INTR2 :: CPU_SET :: SPI_LR_SESSION_DONE [03:03] */
-#define BCHP_HIF_SPI_INTR2_CPU_SET_SPI_LR_SESSION_DONE_MASK 0x00000008
-#define BCHP_HIF_SPI_INTR2_CPU_SET_SPI_LR_SESSION_DONE_SHIFT 3
-#define BCHP_HIF_SPI_INTR2_CPU_SET_SPI_LR_SESSION_DONE_DEFAULT 0x00000000
-
-/* HIF_SPI_INTR2 :: CPU_SET :: SPI_LR_IMPATIENT [02:02] */
-#define BCHP_HIF_SPI_INTR2_CPU_SET_SPI_LR_IMPATIENT_MASK 0x00000004
-#define BCHP_HIF_SPI_INTR2_CPU_SET_SPI_LR_IMPATIENT_SHIFT 2
-#define BCHP_HIF_SPI_INTR2_CPU_SET_SPI_LR_IMPATIENT_DEFAULT 0x00000000
-
-/* HIF_SPI_INTR2 :: CPU_SET :: SPI_LR_SESSION_ABORTED [01:01] */
-#define BCHP_HIF_SPI_INTR2_CPU_SET_SPI_LR_SESSION_ABORTED_MASK 0x00000002
-#define BCHP_HIF_SPI_INTR2_CPU_SET_SPI_LR_SESSION_ABORTED_SHIFT 1
-#define BCHP_HIF_SPI_INTR2_CPU_SET_SPI_LR_SESSION_ABORTED_DEFAULT 0x00000000
-
-/* HIF_SPI_INTR2 :: CPU_SET :: SPI_LR_FULLNESS_REACHED [00:00] */
-#define BCHP_HIF_SPI_INTR2_CPU_SET_SPI_LR_FULLNESS_REACHED_MASK 0x00000001
-#define BCHP_HIF_SPI_INTR2_CPU_SET_SPI_LR_FULLNESS_REACHED_SHIFT 0
-#define BCHP_HIF_SPI_INTR2_CPU_SET_SPI_LR_FULLNESS_REACHED_DEFAULT 0x00000000
-
-/***************************************************************************
- *CPU_CLEAR - CPU interrupt Clear Register
- ***************************************************************************/
-/* HIF_SPI_INTR2 :: CPU_CLEAR :: reserved0 [31:07] */
-#define BCHP_HIF_SPI_INTR2_CPU_CLEAR_reserved0_MASK 0xffffff80
-#define BCHP_HIF_SPI_INTR2_CPU_CLEAR_reserved0_SHIFT 7
-
-/* HIF_SPI_INTR2 :: CPU_CLEAR :: MSPI_HALTED [06:06] */
-#define BCHP_HIF_SPI_INTR2_CPU_CLEAR_MSPI_HALTED_MASK 0x00000040
-#define BCHP_HIF_SPI_INTR2_CPU_CLEAR_MSPI_HALTED_SHIFT 6
-#define BCHP_HIF_SPI_INTR2_CPU_CLEAR_MSPI_HALTED_DEFAULT 0x00000000
-
-/* HIF_SPI_INTR2 :: CPU_CLEAR :: MSPI_DONE [05:05] */
-#define BCHP_HIF_SPI_INTR2_CPU_CLEAR_MSPI_DONE_MASK 0x00000020
-#define BCHP_HIF_SPI_INTR2_CPU_CLEAR_MSPI_DONE_SHIFT 5
-#define BCHP_HIF_SPI_INTR2_CPU_CLEAR_MSPI_DONE_DEFAULT 0x00000000
-
-/* HIF_SPI_INTR2 :: CPU_CLEAR :: SPI_LR_OVERREAD [04:04] */
-#define BCHP_HIF_SPI_INTR2_CPU_CLEAR_SPI_LR_OVERREAD_MASK 0x00000010
-#define BCHP_HIF_SPI_INTR2_CPU_CLEAR_SPI_LR_OVERREAD_SHIFT 4
-#define BCHP_HIF_SPI_INTR2_CPU_CLEAR_SPI_LR_OVERREAD_DEFAULT 0x00000000
-
-/* HIF_SPI_INTR2 :: CPU_CLEAR :: SPI_LR_SESSION_DONE [03:03] */
-#define BCHP_HIF_SPI_INTR2_CPU_CLEAR_SPI_LR_SESSION_DONE_MASK 0x00000008
-#define BCHP_HIF_SPI_INTR2_CPU_CLEAR_SPI_LR_SESSION_DONE_SHIFT 3
-#define BCHP_HIF_SPI_INTR2_CPU_CLEAR_SPI_LR_SESSION_DONE_DEFAULT 0x00000000
-
-/* HIF_SPI_INTR2 :: CPU_CLEAR :: SPI_LR_IMPATIENT [02:02] */
-#define BCHP_HIF_SPI_INTR2_CPU_CLEAR_SPI_LR_IMPATIENT_MASK 0x00000004
-#define BCHP_HIF_SPI_INTR2_CPU_CLEAR_SPI_LR_IMPATIENT_SHIFT 2
-#define BCHP_HIF_SPI_INTR2_CPU_CLEAR_SPI_LR_IMPATIENT_DEFAULT 0x00000000
-
-/* HIF_SPI_INTR2 :: CPU_CLEAR :: SPI_LR_SESSION_ABORTED [01:01] */
-#define BCHP_HIF_SPI_INTR2_CPU_CLEAR_SPI_LR_SESSION_ABORTED_MASK 0x00000002
-#define BCHP_HIF_SPI_INTR2_CPU_CLEAR_SPI_LR_SESSION_ABORTED_SHIFT 1
-#define BCHP_HIF_SPI_INTR2_CPU_CLEAR_SPI_LR_SESSION_ABORTED_DEFAULT 0x00000000
-
-/* HIF_SPI_INTR2 :: CPU_CLEAR :: SPI_LR_FULLNESS_REACHED [00:00] */
-#define BCHP_HIF_SPI_INTR2_CPU_CLEAR_SPI_LR_FULLNESS_REACHED_MASK 0x00000001
-#define BCHP_HIF_SPI_INTR2_CPU_CLEAR_SPI_LR_FULLNESS_REACHED_SHIFT 0
-#define BCHP_HIF_SPI_INTR2_CPU_CLEAR_SPI_LR_FULLNESS_REACHED_DEFAULT 0x00000000
-
-/***************************************************************************
- *CPU_MASK_STATUS - CPU interrupt Mask Status Register
- ***************************************************************************/
-/* HIF_SPI_INTR2 :: CPU_MASK_STATUS :: reserved0 [31:07] */
-#define BCHP_HIF_SPI_INTR2_CPU_MASK_STATUS_reserved0_MASK 0xffffff80
-#define BCHP_HIF_SPI_INTR2_CPU_MASK_STATUS_reserved0_SHIFT 7
-
-/* HIF_SPI_INTR2 :: CPU_MASK_STATUS :: MSPI_HALTED [06:06] */
-#define BCHP_HIF_SPI_INTR2_CPU_MASK_STATUS_MSPI_HALTED_MASK 0x00000040
-#define BCHP_HIF_SPI_INTR2_CPU_MASK_STATUS_MSPI_HALTED_SHIFT 6
-#define BCHP_HIF_SPI_INTR2_CPU_MASK_STATUS_MSPI_HALTED_DEFAULT 0x00000000
-
-/* HIF_SPI_INTR2 :: CPU_MASK_STATUS :: MSPI_DONE [05:05] */
-#define BCHP_HIF_SPI_INTR2_CPU_MASK_STATUS_MSPI_DONE_MASK 0x00000020
-#define BCHP_HIF_SPI_INTR2_CPU_MASK_STATUS_MSPI_DONE_SHIFT 5
-#define BCHP_HIF_SPI_INTR2_CPU_MASK_STATUS_MSPI_DONE_DEFAULT 0x00000000
-
-/* HIF_SPI_INTR2 :: CPU_MASK_STATUS :: SPI_LR_OVERREAD [04:04] */
-#define BCHP_HIF_SPI_INTR2_CPU_MASK_STATUS_SPI_LR_OVERREAD_MASK 0x00000010
-#define BCHP_HIF_SPI_INTR2_CPU_MASK_STATUS_SPI_LR_OVERREAD_SHIFT 4
-#define BCHP_HIF_SPI_INTR2_CPU_MASK_STATUS_SPI_LR_OVERREAD_DEFAULT 0x00000000
-
-/* HIF_SPI_INTR2 :: CPU_MASK_STATUS :: SPI_LR_SESSION_DONE [03:03] */
-#define BCHP_HIF_SPI_INTR2_CPU_MASK_STATUS_SPI_LR_SESSION_DONE_MASK 0x00000008
-#define BCHP_HIF_SPI_INTR2_CPU_MASK_STATUS_SPI_LR_SESSION_DONE_SHIFT 3
-#define BCHP_HIF_SPI_INTR2_CPU_MASK_STATUS_SPI_LR_SESSION_DONE_DEFAULT 0x00000000
-
-/* HIF_SPI_INTR2 :: CPU_MASK_STATUS :: SPI_LR_IMPATIENT [02:02] */
-#define BCHP_HIF_SPI_INTR2_CPU_MASK_STATUS_SPI_LR_IMPATIENT_MASK 0x00000004
-#define BCHP_HIF_SPI_INTR2_CPU_MASK_STATUS_SPI_LR_IMPATIENT_SHIFT 2
-#define BCHP_HIF_SPI_INTR2_CPU_MASK_STATUS_SPI_LR_IMPATIENT_DEFAULT 0x00000000
-
-/* HIF_SPI_INTR2 :: CPU_MASK_STATUS :: SPI_LR_SESSION_ABORTED [01:01] */
-#define BCHP_HIF_SPI_INTR2_CPU_MASK_STATUS_SPI_LR_SESSION_ABORTED_MASK 0x00000002
-#define BCHP_HIF_SPI_INTR2_CPU_MASK_STATUS_SPI_LR_SESSION_ABORTED_SHIFT 1
-#define BCHP_HIF_SPI_INTR2_CPU_MASK_STATUS_SPI_LR_SESSION_ABORTED_DEFAULT 0x00000000
-
-/* HIF_SPI_INTR2 :: CPU_MASK_STATUS :: SPI_LR_FULLNESS_REACHED [00:00] */
-#define BCHP_HIF_SPI_INTR2_CPU_MASK_STATUS_SPI_LR_FULLNESS_REACHED_MASK 0x00000001
-#define BCHP_HIF_SPI_INTR2_CPU_MASK_STATUS_SPI_LR_FULLNESS_REACHED_SHIFT 0
-#define BCHP_HIF_SPI_INTR2_CPU_MASK_STATUS_SPI_LR_FULLNESS_REACHED_DEFAULT 0x00000000
-
-/***************************************************************************
- *CPU_MASK_SET - CPU interrupt Mask Set Register
- ***************************************************************************/
-/* HIF_SPI_INTR2 :: CPU_MASK_SET :: reserved0 [31:07] */
-#define BCHP_HIF_SPI_INTR2_CPU_MASK_SET_reserved0_MASK 0xffffff80
-#define BCHP_HIF_SPI_INTR2_CPU_MASK_SET_reserved0_SHIFT 7
-
-/* HIF_SPI_INTR2 :: CPU_MASK_SET :: MSPI_HALTED [06:06] */
-#define BCHP_HIF_SPI_INTR2_CPU_MASK_SET_MSPI_HALTED_MASK 0x00000040
-#define BCHP_HIF_SPI_INTR2_CPU_MASK_SET_MSPI_HALTED_SHIFT 6
-#define BCHP_HIF_SPI_INTR2_CPU_MASK_SET_MSPI_HALTED_DEFAULT 0x00000000
-
-/* HIF_SPI_INTR2 :: CPU_MASK_SET :: MSPI_DONE [05:05] */
-#define BCHP_HIF_SPI_INTR2_CPU_MASK_SET_MSPI_DONE_MASK 0x00000020
-#define BCHP_HIF_SPI_INTR2_CPU_MASK_SET_MSPI_DONE_SHIFT 5
-#define BCHP_HIF_SPI_INTR2_CPU_MASK_SET_MSPI_DONE_DEFAULT 0x00000000
-
-/* HIF_SPI_INTR2 :: CPU_MASK_SET :: SPI_LR_OVERREAD [04:04] */
-#define BCHP_HIF_SPI_INTR2_CPU_MASK_SET_SPI_LR_OVERREAD_MASK 0x00000010
-#define BCHP_HIF_SPI_INTR2_CPU_MASK_SET_SPI_LR_OVERREAD_SHIFT 4
-#define BCHP_HIF_SPI_INTR2_CPU_MASK_SET_SPI_LR_OVERREAD_DEFAULT 0x00000000
-
-/* HIF_SPI_INTR2 :: CPU_MASK_SET :: SPI_LR_SESSION_DONE [03:03] */
-#define BCHP_HIF_SPI_INTR2_CPU_MASK_SET_SPI_LR_SESSION_DONE_MASK 0x00000008
-#define BCHP_HIF_SPI_INTR2_CPU_MASK_SET_SPI_LR_SESSION_DONE_SHIFT 3
-#define BCHP_HIF_SPI_INTR2_CPU_MASK_SET_SPI_LR_SESSION_DONE_DEFAULT 0x00000000
-
-/* HIF_SPI_INTR2 :: CPU_MASK_SET :: SPI_LR_IMPATIENT [02:02] */
-#define BCHP_HIF_SPI_INTR2_CPU_MASK_SET_SPI_LR_IMPATIENT_MASK 0x00000004
-#define BCHP_HIF_SPI_INTR2_CPU_MASK_SET_SPI_LR_IMPATIENT_SHIFT 2
-#define BCHP_HIF_SPI_INTR2_CPU_MASK_SET_SPI_LR_IMPATIENT_DEFAULT 0x00000000
-
-/* HIF_SPI_INTR2 :: CPU_MASK_SET :: SPI_LR_SESSION_ABORTED [01:01] */
-#define BCHP_HIF_SPI_INTR2_CPU_MASK_SET_SPI_LR_SESSION_ABORTED_MASK 0x00000002
-#define BCHP_HIF_SPI_INTR2_CPU_MASK_SET_SPI_LR_SESSION_ABORTED_SHIFT 1
-#define BCHP_HIF_SPI_INTR2_CPU_MASK_SET_SPI_LR_SESSION_ABORTED_DEFAULT 0x00000000
-
-/* HIF_SPI_INTR2 :: CPU_MASK_SET :: SPI_LR_FULLNESS_REACHED [00:00] */
-#define BCHP_HIF_SPI_INTR2_CPU_MASK_SET_SPI_LR_FULLNESS_REACHED_MASK 0x00000001
-#define BCHP_HIF_SPI_INTR2_CPU_MASK_SET_SPI_LR_FULLNESS_REACHED_SHIFT 0
-#define BCHP_HIF_SPI_INTR2_CPU_MASK_SET_SPI_LR_FULLNESS_REACHED_DEFAULT 0x00000000
-
-/***************************************************************************
- *CPU_MASK_CLEAR - CPU interrupt Mask Clear Register
- ***************************************************************************/
-/* HIF_SPI_INTR2 :: CPU_MASK_CLEAR :: reserved0 [31:07] */
-#define BCHP_HIF_SPI_INTR2_CPU_MASK_CLEAR_reserved0_MASK 0xffffff80
-#define BCHP_HIF_SPI_INTR2_CPU_MASK_CLEAR_reserved0_SHIFT 7
-
-/* HIF_SPI_INTR2 :: CPU_MASK_CLEAR :: MSPI_HALTED [06:06] */
-#define BCHP_HIF_SPI_INTR2_CPU_MASK_CLEAR_MSPI_HALTED_MASK 0x00000040
-#define BCHP_HIF_SPI_INTR2_CPU_MASK_CLEAR_MSPI_HALTED_SHIFT 6
-#define BCHP_HIF_SPI_INTR2_CPU_MASK_CLEAR_MSPI_HALTED_DEFAULT 0x00000000
-
-/* HIF_SPI_INTR2 :: CPU_MASK_CLEAR :: MSPI_DONE [05:05] */
-#define BCHP_HIF_SPI_INTR2_CPU_MASK_CLEAR_MSPI_DONE_MASK 0x00000020
-#define BCHP_HIF_SPI_INTR2_CPU_MASK_CLEAR_MSPI_DONE_SHIFT 5
-#define BCHP_HIF_SPI_INTR2_CPU_MASK_CLEAR_MSPI_DONE_DEFAULT 0x00000000
-
-/* HIF_SPI_INTR2 :: CPU_MASK_CLEAR :: SPI_LR_OVERREAD [04:04] */
-#define BCHP_HIF_SPI_INTR2_CPU_MASK_CLEAR_SPI_LR_OVERREAD_MASK 0x00000010
-#define BCHP_HIF_SPI_INTR2_CPU_MASK_CLEAR_SPI_LR_OVERREAD_SHIFT 4
-#define BCHP_HIF_SPI_INTR2_CPU_MASK_CLEAR_SPI_LR_OVERREAD_DEFAULT 0x00000000
-
-/* HIF_SPI_INTR2 :: CPU_MASK_CLEAR :: SPI_LR_SESSION_DONE [03:03] */
-#define BCHP_HIF_SPI_INTR2_CPU_MASK_CLEAR_SPI_LR_SESSION_DONE_MASK 0x00000008
-#define BCHP_HIF_SPI_INTR2_CPU_MASK_CLEAR_SPI_LR_SESSION_DONE_SHIFT 3
-#define BCHP_HIF_SPI_INTR2_CPU_MASK_CLEAR_SPI_LR_SESSION_DONE_DEFAULT 0x00000000
-
-/* HIF_SPI_INTR2 :: CPU_MASK_CLEAR :: SPI_LR_IMPATIENT [02:02] */
-#define BCHP_HIF_SPI_INTR2_CPU_MASK_CLEAR_SPI_LR_IMPATIENT_MASK 0x00000004
-#define BCHP_HIF_SPI_INTR2_CPU_MASK_CLEAR_SPI_LR_IMPATIENT_SHIFT 2
-#define BCHP_HIF_SPI_INTR2_CPU_MASK_CLEAR_SPI_LR_IMPATIENT_DEFAULT 0x00000000
-
-/* HIF_SPI_INTR2 :: CPU_MASK_CLEAR :: SPI_LR_SESSION_ABORTED [01:01] */
-#define BCHP_HIF_SPI_INTR2_CPU_MASK_CLEAR_SPI_LR_SESSION_ABORTED_MASK 0x00000002
-#define BCHP_HIF_SPI_INTR2_CPU_MASK_CLEAR_SPI_LR_SESSION_ABORTED_SHIFT 1
-#define BCHP_HIF_SPI_INTR2_CPU_MASK_CLEAR_SPI_LR_SESSION_ABORTED_DEFAULT 0x00000000
-
-/* HIF_SPI_INTR2 :: CPU_MASK_CLEAR :: SPI_LR_FULLNESS_REACHED [00:00] */
-#define BCHP_HIF_SPI_INTR2_CPU_MASK_CLEAR_SPI_LR_FULLNESS_REACHED_MASK 0x00000001
-#define BCHP_HIF_SPI_INTR2_CPU_MASK_CLEAR_SPI_LR_FULLNESS_REACHED_SHIFT 0
-#define BCHP_HIF_SPI_INTR2_CPU_MASK_CLEAR_SPI_LR_FULLNESS_REACHED_DEFAULT 0x00000000
-
-/***************************************************************************
- *PCI_STATUS - PCI interrupt Status Register
- ***************************************************************************/
-/* HIF_SPI_INTR2 :: PCI_STATUS :: reserved0 [31:07] */
-#define BCHP_HIF_SPI_INTR2_PCI_STATUS_reserved0_MASK 0xffffff80
-#define BCHP_HIF_SPI_INTR2_PCI_STATUS_reserved0_SHIFT 7
-
-/* HIF_SPI_INTR2 :: PCI_STATUS :: MSPI_HALTED [06:06] */
-#define BCHP_HIF_SPI_INTR2_PCI_STATUS_MSPI_HALTED_MASK 0x00000040
-#define BCHP_HIF_SPI_INTR2_PCI_STATUS_MSPI_HALTED_SHIFT 6
-#define BCHP_HIF_SPI_INTR2_PCI_STATUS_MSPI_HALTED_DEFAULT 0x00000000
-
-/* HIF_SPI_INTR2 :: PCI_STATUS :: MSPI_DONE [05:05] */
-#define BCHP_HIF_SPI_INTR2_PCI_STATUS_MSPI_DONE_MASK 0x00000020
-#define BCHP_HIF_SPI_INTR2_PCI_STATUS_MSPI_DONE_SHIFT 5
-#define BCHP_HIF_SPI_INTR2_PCI_STATUS_MSPI_DONE_DEFAULT 0x00000000
-
-/* HIF_SPI_INTR2 :: PCI_STATUS :: SPI_LR_OVERREAD [04:04] */
-#define BCHP_HIF_SPI_INTR2_PCI_STATUS_SPI_LR_OVERREAD_MASK 0x00000010
-#define BCHP_HIF_SPI_INTR2_PCI_STATUS_SPI_LR_OVERREAD_SHIFT 4
-#define BCHP_HIF_SPI_INTR2_PCI_STATUS_SPI_LR_OVERREAD_DEFAULT 0x00000000
-
-/* HIF_SPI_INTR2 :: PCI_STATUS :: SPI_LR_SESSION_DONE [03:03] */
-#define BCHP_HIF_SPI_INTR2_PCI_STATUS_SPI_LR_SESSION_DONE_MASK 0x00000008
-#define BCHP_HIF_SPI_INTR2_PCI_STATUS_SPI_LR_SESSION_DONE_SHIFT 3
-#define BCHP_HIF_SPI_INTR2_PCI_STATUS_SPI_LR_SESSION_DONE_DEFAULT 0x00000000
-
-/* HIF_SPI_INTR2 :: PCI_STATUS :: SPI_LR_IMPATIENT [02:02] */
-#define BCHP_HIF_SPI_INTR2_PCI_STATUS_SPI_LR_IMPATIENT_MASK 0x00000004
-#define BCHP_HIF_SPI_INTR2_PCI_STATUS_SPI_LR_IMPATIENT_SHIFT 2
-#define BCHP_HIF_SPI_INTR2_PCI_STATUS_SPI_LR_IMPATIENT_DEFAULT 0x00000000
-
-/* HIF_SPI_INTR2 :: PCI_STATUS :: SPI_LR_SESSION_ABORTED [01:01] */
-#define BCHP_HIF_SPI_INTR2_PCI_STATUS_SPI_LR_SESSION_ABORTED_MASK 0x00000002
-#define BCHP_HIF_SPI_INTR2_PCI_STATUS_SPI_LR_SESSION_ABORTED_SHIFT 1
-#define BCHP_HIF_SPI_INTR2_PCI_STATUS_SPI_LR_SESSION_ABORTED_DEFAULT 0x00000000
-
-/* HIF_SPI_INTR2 :: PCI_STATUS :: SPI_LR_FULLNESS_REACHED [00:00] */
-#define BCHP_HIF_SPI_INTR2_PCI_STATUS_SPI_LR_FULLNESS_REACHED_MASK 0x00000001
-#define BCHP_HIF_SPI_INTR2_PCI_STATUS_SPI_LR_FULLNESS_REACHED_SHIFT 0
-#define BCHP_HIF_SPI_INTR2_PCI_STATUS_SPI_LR_FULLNESS_REACHED_DEFAULT 0x00000000
-
-/***************************************************************************
- *PCI_SET - PCI interrupt Set Register
- ***************************************************************************/
-/* HIF_SPI_INTR2 :: PCI_SET :: reserved0 [31:07] */
-#define BCHP_HIF_SPI_INTR2_PCI_SET_reserved0_MASK 0xffffff80
-#define BCHP_HIF_SPI_INTR2_PCI_SET_reserved0_SHIFT 7
-
-/* HIF_SPI_INTR2 :: PCI_SET :: MSPI_HALTED [06:06] */
-#define BCHP_HIF_SPI_INTR2_PCI_SET_MSPI_HALTED_MASK 0x00000040
-#define BCHP_HIF_SPI_INTR2_PCI_SET_MSPI_HALTED_SHIFT 6
-#define BCHP_HIF_SPI_INTR2_PCI_SET_MSPI_HALTED_DEFAULT 0x00000000
-
-/* HIF_SPI_INTR2 :: PCI_SET :: MSPI_DONE [05:05] */
-#define BCHP_HIF_SPI_INTR2_PCI_SET_MSPI_DONE_MASK 0x00000020
-#define BCHP_HIF_SPI_INTR2_PCI_SET_MSPI_DONE_SHIFT 5
-#define BCHP_HIF_SPI_INTR2_PCI_SET_MSPI_DONE_DEFAULT 0x00000000
-
-/* HIF_SPI_INTR2 :: PCI_SET :: SPI_LR_OVERREAD [04:04] */
-#define BCHP_HIF_SPI_INTR2_PCI_SET_SPI_LR_OVERREAD_MASK 0x00000010
-#define BCHP_HIF_SPI_INTR2_PCI_SET_SPI_LR_OVERREAD_SHIFT 4
-#define BCHP_HIF_SPI_INTR2_PCI_SET_SPI_LR_OVERREAD_DEFAULT 0x00000000
-
-/* HIF_SPI_INTR2 :: PCI_SET :: SPI_LR_SESSION_DONE [03:03] */
-#define BCHP_HIF_SPI_INTR2_PCI_SET_SPI_LR_SESSION_DONE_MASK 0x00000008
-#define BCHP_HIF_SPI_INTR2_PCI_SET_SPI_LR_SESSION_DONE_SHIFT 3
-#define BCHP_HIF_SPI_INTR2_PCI_SET_SPI_LR_SESSION_DONE_DEFAULT 0x00000000
-
-/* HIF_SPI_INTR2 :: PCI_SET :: SPI_LR_IMPATIENT [02:02] */
-#define BCHP_HIF_SPI_INTR2_PCI_SET_SPI_LR_IMPATIENT_MASK 0x00000004
-#define BCHP_HIF_SPI_INTR2_PCI_SET_SPI_LR_IMPATIENT_SHIFT 2
-#define BCHP_HIF_SPI_INTR2_PCI_SET_SPI_LR_IMPATIENT_DEFAULT 0x00000000
-
-/* HIF_SPI_INTR2 :: PCI_SET :: SPI_LR_SESSION_ABORTED [01:01] */
-#define BCHP_HIF_SPI_INTR2_PCI_SET_SPI_LR_SESSION_ABORTED_MASK 0x00000002
-#define BCHP_HIF_SPI_INTR2_PCI_SET_SPI_LR_SESSION_ABORTED_SHIFT 1
-#define BCHP_HIF_SPI_INTR2_PCI_SET_SPI_LR_SESSION_ABORTED_DEFAULT 0x00000000
-
-/* HIF_SPI_INTR2 :: PCI_SET :: SPI_LR_FULLNESS_REACHED [00:00] */
-#define BCHP_HIF_SPI_INTR2_PCI_SET_SPI_LR_FULLNESS_REACHED_MASK 0x00000001
-#define BCHP_HIF_SPI_INTR2_PCI_SET_SPI_LR_FULLNESS_REACHED_SHIFT 0
-#define BCHP_HIF_SPI_INTR2_PCI_SET_SPI_LR_FULLNESS_REACHED_DEFAULT 0x00000000
-
-/***************************************************************************
- *PCI_CLEAR - PCI interrupt Clear Register
- ***************************************************************************/
-/* HIF_SPI_INTR2 :: PCI_CLEAR :: reserved0 [31:07] */
-#define BCHP_HIF_SPI_INTR2_PCI_CLEAR_reserved0_MASK 0xffffff80
-#define BCHP_HIF_SPI_INTR2_PCI_CLEAR_reserved0_SHIFT 7
-
-/* HIF_SPI_INTR2 :: PCI_CLEAR :: MSPI_HALTED [06:06] */
-#define BCHP_HIF_SPI_INTR2_PCI_CLEAR_MSPI_HALTED_MASK 0x00000040
-#define BCHP_HIF_SPI_INTR2_PCI_CLEAR_MSPI_HALTED_SHIFT 6
-#define BCHP_HIF_SPI_INTR2_PCI_CLEAR_MSPI_HALTED_DEFAULT 0x00000000
-
-/* HIF_SPI_INTR2 :: PCI_CLEAR :: MSPI_DONE [05:05] */
-#define BCHP_HIF_SPI_INTR2_PCI_CLEAR_MSPI_DONE_MASK 0x00000020
-#define BCHP_HIF_SPI_INTR2_PCI_CLEAR_MSPI_DONE_SHIFT 5
-#define BCHP_HIF_SPI_INTR2_PCI_CLEAR_MSPI_DONE_DEFAULT 0x00000000
-
-/* HIF_SPI_INTR2 :: PCI_CLEAR :: SPI_LR_OVERREAD [04:04] */
-#define BCHP_HIF_SPI_INTR2_PCI_CLEAR_SPI_LR_OVERREAD_MASK 0x00000010
-#define BCHP_HIF_SPI_INTR2_PCI_CLEAR_SPI_LR_OVERREAD_SHIFT 4
-#define BCHP_HIF_SPI_INTR2_PCI_CLEAR_SPI_LR_OVERREAD_DEFAULT 0x00000000
-
-/* HIF_SPI_INTR2 :: PCI_CLEAR :: SPI_LR_SESSION_DONE [03:03] */
-#define BCHP_HIF_SPI_INTR2_PCI_CLEAR_SPI_LR_SESSION_DONE_MASK 0x00000008
-#define BCHP_HIF_SPI_INTR2_PCI_CLEAR_SPI_LR_SESSION_DONE_SHIFT 3
-#define BCHP_HIF_SPI_INTR2_PCI_CLEAR_SPI_LR_SESSION_DONE_DEFAULT 0x00000000
-
-/* HIF_SPI_INTR2 :: PCI_CLEAR :: SPI_LR_IMPATIENT [02:02] */
-#define BCHP_HIF_SPI_INTR2_PCI_CLEAR_SPI_LR_IMPATIENT_MASK 0x00000004
-#define BCHP_HIF_SPI_INTR2_PCI_CLEAR_SPI_LR_IMPATIENT_SHIFT 2
-#define BCHP_HIF_SPI_INTR2_PCI_CLEAR_SPI_LR_IMPATIENT_DEFAULT 0x00000000
-
-/* HIF_SPI_INTR2 :: PCI_CLEAR :: SPI_LR_SESSION_ABORTED [01:01] */
-#define BCHP_HIF_SPI_INTR2_PCI_CLEAR_SPI_LR_SESSION_ABORTED_MASK 0x00000002
-#define BCHP_HIF_SPI_INTR2_PCI_CLEAR_SPI_LR_SESSION_ABORTED_SHIFT 1
-#define BCHP_HIF_SPI_INTR2_PCI_CLEAR_SPI_LR_SESSION_ABORTED_DEFAULT 0x00000000
-
-/* HIF_SPI_INTR2 :: PCI_CLEAR :: SPI_LR_FULLNESS_REACHED [00:00] */
-#define BCHP_HIF_SPI_INTR2_PCI_CLEAR_SPI_LR_FULLNESS_REACHED_MASK 0x00000001
-#define BCHP_HIF_SPI_INTR2_PCI_CLEAR_SPI_LR_FULLNESS_REACHED_SHIFT 0
-#define BCHP_HIF_SPI_INTR2_PCI_CLEAR_SPI_LR_FULLNESS_REACHED_DEFAULT 0x00000000
-
-/***************************************************************************
- *PCI_MASK_STATUS - PCI interrupt Mask Status Register
- ***************************************************************************/
-/* HIF_SPI_INTR2 :: PCI_MASK_STATUS :: reserved0 [31:07] */
-#define BCHP_HIF_SPI_INTR2_PCI_MASK_STATUS_reserved0_MASK 0xffffff80
-#define BCHP_HIF_SPI_INTR2_PCI_MASK_STATUS_reserved0_SHIFT 7
-
-/* HIF_SPI_INTR2 :: PCI_MASK_STATUS :: MSPI_HALTED [06:06] */
-#define BCHP_HIF_SPI_INTR2_PCI_MASK_STATUS_MSPI_HALTED_MASK 0x00000040
-#define BCHP_HIF_SPI_INTR2_PCI_MASK_STATUS_MSPI_HALTED_SHIFT 6
-#define BCHP_HIF_SPI_INTR2_PCI_MASK_STATUS_MSPI_HALTED_DEFAULT 0x00000000
-
-/* HIF_SPI_INTR2 :: PCI_MASK_STATUS :: MSPI_DONE [05:05] */
-#define BCHP_HIF_SPI_INTR2_PCI_MASK_STATUS_MSPI_DONE_MASK 0x00000020
-#define BCHP_HIF_SPI_INTR2_PCI_MASK_STATUS_MSPI_DONE_SHIFT 5
-#define BCHP_HIF_SPI_INTR2_PCI_MASK_STATUS_MSPI_DONE_DEFAULT 0x00000000
-
-/* HIF_SPI_INTR2 :: PCI_MASK_STATUS :: SPI_LR_OVERREAD [04:04] */
-#define BCHP_HIF_SPI_INTR2_PCI_MASK_STATUS_SPI_LR_OVERREAD_MASK 0x00000010
-#define BCHP_HIF_SPI_INTR2_PCI_MASK_STATUS_SPI_LR_OVERREAD_SHIFT 4
-#define BCHP_HIF_SPI_INTR2_PCI_MASK_STATUS_SPI_LR_OVERREAD_DEFAULT 0x00000000
-
-/* HIF_SPI_INTR2 :: PCI_MASK_STATUS :: SPI_LR_SESSION_DONE [03:03] */
-#define BCHP_HIF_SPI_INTR2_PCI_MASK_STATUS_SPI_LR_SESSION_DONE_MASK 0x00000008
-#define BCHP_HIF_SPI_INTR2_PCI_MASK_STATUS_SPI_LR_SESSION_DONE_SHIFT 3
-#define BCHP_HIF_SPI_INTR2_PCI_MASK_STATUS_SPI_LR_SESSION_DONE_DEFAULT 0x00000000
-
-/* HIF_SPI_INTR2 :: PCI_MASK_STATUS :: SPI_LR_IMPATIENT [02:02] */
-#define BCHP_HIF_SPI_INTR2_PCI_MASK_STATUS_SPI_LR_IMPATIENT_MASK 0x00000004
-#define BCHP_HIF_SPI_INTR2_PCI_MASK_STATUS_SPI_LR_IMPATIENT_SHIFT 2
-#define BCHP_HIF_SPI_INTR2_PCI_MASK_STATUS_SPI_LR_IMPATIENT_DEFAULT 0x00000000
-
-/* HIF_SPI_INTR2 :: PCI_MASK_STATUS :: SPI_LR_SESSION_ABORTED [01:01] */
-#define BCHP_HIF_SPI_INTR2_PCI_MASK_STATUS_SPI_LR_SESSION_ABORTED_MASK 0x00000002
-#define BCHP_HIF_SPI_INTR2_PCI_MASK_STATUS_SPI_LR_SESSION_ABORTED_SHIFT 1
-#define BCHP_HIF_SPI_INTR2_PCI_MASK_STATUS_SPI_LR_SESSION_ABORTED_DEFAULT 0x00000000
-
-/* HIF_SPI_INTR2 :: PCI_MASK_STATUS :: SPI_LR_FULLNESS_REACHED [00:00] */
-#define BCHP_HIF_SPI_INTR2_PCI_MASK_STATUS_SPI_LR_FULLNESS_REACHED_MASK 0x00000001
-#define BCHP_HIF_SPI_INTR2_PCI_MASK_STATUS_SPI_LR_FULLNESS_REACHED_SHIFT 0
-#define BCHP_HIF_SPI_INTR2_PCI_MASK_STATUS_SPI_LR_FULLNESS_REACHED_DEFAULT 0x00000000
-
-/***************************************************************************
- *PCI_MASK_SET - PCI interrupt Mask Set Register
- ***************************************************************************/
-/* HIF_SPI_INTR2 :: PCI_MASK_SET :: reserved0 [31:07] */
-#define BCHP_HIF_SPI_INTR2_PCI_MASK_SET_reserved0_MASK 0xffffff80
-#define BCHP_HIF_SPI_INTR2_PCI_MASK_SET_reserved0_SHIFT 7
-
-/* HIF_SPI_INTR2 :: PCI_MASK_SET :: MSPI_HALTED [06:06] */
-#define BCHP_HIF_SPI_INTR2_PCI_MASK_SET_MSPI_HALTED_MASK 0x00000040
-#define BCHP_HIF_SPI_INTR2_PCI_MASK_SET_MSPI_HALTED_SHIFT 6
-#define BCHP_HIF_SPI_INTR2_PCI_MASK_SET_MSPI_HALTED_DEFAULT 0x00000000
-
-/* HIF_SPI_INTR2 :: PCI_MASK_SET :: MSPI_DONE [05:05] */
-#define BCHP_HIF_SPI_INTR2_PCI_MASK_SET_MSPI_DONE_MASK 0x00000020
-#define BCHP_HIF_SPI_INTR2_PCI_MASK_SET_MSPI_DONE_SHIFT 5
-#define BCHP_HIF_SPI_INTR2_PCI_MASK_SET_MSPI_DONE_DEFAULT 0x00000000
-
-/* HIF_SPI_INTR2 :: PCI_MASK_SET :: SPI_LR_OVERREAD [04:04] */
-#define BCHP_HIF_SPI_INTR2_PCI_MASK_SET_SPI_LR_OVERREAD_MASK 0x00000010
-#define BCHP_HIF_SPI_INTR2_PCI_MASK_SET_SPI_LR_OVERREAD_SHIFT 4
-#define BCHP_HIF_SPI_INTR2_PCI_MASK_SET_SPI_LR_OVERREAD_DEFAULT 0x00000000
-
-/* HIF_SPI_INTR2 :: PCI_MASK_SET :: SPI_LR_SESSION_DONE [03:03] */
-#define BCHP_HIF_SPI_INTR2_PCI_MASK_SET_SPI_LR_SESSION_DONE_MASK 0x00000008
-#define BCHP_HIF_SPI_INTR2_PCI_MASK_SET_SPI_LR_SESSION_DONE_SHIFT 3
-#define BCHP_HIF_SPI_INTR2_PCI_MASK_SET_SPI_LR_SESSION_DONE_DEFAULT 0x00000000
-
-/* HIF_SPI_INTR2 :: PCI_MASK_SET :: SPI_LR_IMPATIENT [02:02] */
-#define BCHP_HIF_SPI_INTR2_PCI_MASK_SET_SPI_LR_IMPATIENT_MASK 0x00000004
-#define BCHP_HIF_SPI_INTR2_PCI_MASK_SET_SPI_LR_IMPATIENT_SHIFT 2
-#define BCHP_HIF_SPI_INTR2_PCI_MASK_SET_SPI_LR_IMPATIENT_DEFAULT 0x00000000
-
-/* HIF_SPI_INTR2 :: PCI_MASK_SET :: SPI_LR_SESSION_ABORTED [01:01] */
-#define BCHP_HIF_SPI_INTR2_PCI_MASK_SET_SPI_LR_SESSION_ABORTED_MASK 0x00000002
-#define BCHP_HIF_SPI_INTR2_PCI_MASK_SET_SPI_LR_SESSION_ABORTED_SHIFT 1
-#define BCHP_HIF_SPI_INTR2_PCI_MASK_SET_SPI_LR_SESSION_ABORTED_DEFAULT 0x00000000
-
-/* HIF_SPI_INTR2 :: PCI_MASK_SET :: SPI_LR_FULLNESS_REACHED [00:00] */
-#define BCHP_HIF_SPI_INTR2_PCI_MASK_SET_SPI_LR_FULLNESS_REACHED_MASK 0x00000001
-#define BCHP_HIF_SPI_INTR2_PCI_MASK_SET_SPI_LR_FULLNESS_REACHED_SHIFT 0
-#define BCHP_HIF_SPI_INTR2_PCI_MASK_SET_SPI_LR_FULLNESS_REACHED_DEFAULT 0x00000000
-
-/***************************************************************************
- *PCI_MASK_CLEAR - PCI interrupt Mask Clear Register
- ***************************************************************************/
-/* HIF_SPI_INTR2 :: PCI_MASK_CLEAR :: reserved0 [31:07] */
-#define BCHP_HIF_SPI_INTR2_PCI_MASK_CLEAR_reserved0_MASK 0xffffff80
-#define BCHP_HIF_SPI_INTR2_PCI_MASK_CLEAR_reserved0_SHIFT 7
-
-/* HIF_SPI_INTR2 :: PCI_MASK_CLEAR :: MSPI_HALTED [06:06] */
-#define BCHP_HIF_SPI_INTR2_PCI_MASK_CLEAR_MSPI_HALTED_MASK 0x00000040
-#define BCHP_HIF_SPI_INTR2_PCI_MASK_CLEAR_MSPI_HALTED_SHIFT 6
-#define BCHP_HIF_SPI_INTR2_PCI_MASK_CLEAR_MSPI_HALTED_DEFAULT 0x00000000
-
-/* HIF_SPI_INTR2 :: PCI_MASK_CLEAR :: MSPI_DONE [05:05] */
-#define BCHP_HIF_SPI_INTR2_PCI_MASK_CLEAR_MSPI_DONE_MASK 0x00000020
-#define BCHP_HIF_SPI_INTR2_PCI_MASK_CLEAR_MSPI_DONE_SHIFT 5
-#define BCHP_HIF_SPI_INTR2_PCI_MASK_CLEAR_MSPI_DONE_DEFAULT 0x00000000
-
-/* HIF_SPI_INTR2 :: PCI_MASK_CLEAR :: SPI_LR_OVERREAD [04:04] */
-#define BCHP_HIF_SPI_INTR2_PCI_MASK_CLEAR_SPI_LR_OVERREAD_MASK 0x00000010
-#define BCHP_HIF_SPI_INTR2_PCI_MASK_CLEAR_SPI_LR_OVERREAD_SHIFT 4
-#define BCHP_HIF_SPI_INTR2_PCI_MASK_CLEAR_SPI_LR_OVERREAD_DEFAULT 0x00000000
-
-/* HIF_SPI_INTR2 :: PCI_MASK_CLEAR :: SPI_LR_SESSION_DONE [03:03] */
-#define BCHP_HIF_SPI_INTR2_PCI_MASK_CLEAR_SPI_LR_SESSION_DONE_MASK 0x00000008
-#define BCHP_HIF_SPI_INTR2_PCI_MASK_CLEAR_SPI_LR_SESSION_DONE_SHIFT 3
-#define BCHP_HIF_SPI_INTR2_PCI_MASK_CLEAR_SPI_LR_SESSION_DONE_DEFAULT 0x00000000
-
-/* HIF_SPI_INTR2 :: PCI_MASK_CLEAR :: SPI_LR_IMPATIENT [02:02] */
-#define BCHP_HIF_SPI_INTR2_PCI_MASK_CLEAR_SPI_LR_IMPATIENT_MASK 0x00000004
-#define BCHP_HIF_SPI_INTR2_PCI_MASK_CLEAR_SPI_LR_IMPATIENT_SHIFT 2
-#define BCHP_HIF_SPI_INTR2_PCI_MASK_CLEAR_SPI_LR_IMPATIENT_DEFAULT 0x00000000
-
-/* HIF_SPI_INTR2 :: PCI_MASK_CLEAR :: SPI_LR_SESSION_ABORTED [01:01] */
-#define BCHP_HIF_SPI_INTR2_PCI_MASK_CLEAR_SPI_LR_SESSION_ABORTED_MASK 0x00000002
-#define BCHP_HIF_SPI_INTR2_PCI_MASK_CLEAR_SPI_LR_SESSION_ABORTED_SHIFT 1
-#define BCHP_HIF_SPI_INTR2_PCI_MASK_CLEAR_SPI_LR_SESSION_ABORTED_DEFAULT 0x00000000
-
-/* HIF_SPI_INTR2 :: PCI_MASK_CLEAR :: SPI_LR_FULLNESS_REACHED [00:00] */
-#define BCHP_HIF_SPI_INTR2_PCI_MASK_CLEAR_SPI_LR_FULLNESS_REACHED_MASK 0x00000001
-#define BCHP_HIF_SPI_INTR2_PCI_MASK_CLEAR_SPI_LR_FULLNESS_REACHED_SHIFT 0
-#define BCHP_HIF_SPI_INTR2_PCI_MASK_CLEAR_SPI_LR_FULLNESS_REACHED_DEFAULT 0x00000000
-
-#endif /* #ifndef BCHP_HIF_SPI_INTR2_H__ */
-
-/* End of File */
diff --git a/include/linux/brcmstb/7145a0/bchp_hif_top_ctrl.h b/include/linux/brcmstb/7145a0/bchp_hif_top_ctrl.h
deleted file mode 100644
index 5a9cb0c..0000000
--- a/include/linux/brcmstb/7145a0/bchp_hif_top_ctrl.h
+++ /dev/null
@@ -1,579 +0,0 @@
-/***************************************************************************
- * Copyright (c) 1999-2013, Broadcom Corporation
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
- *
- * Module Description:
- * DO NOT EDIT THIS FILE DIRECTLY
- *
- * This module was generated magically with RDB from a source description
- * file. You must edit the source file for changes to be made to this file.
- *
- *
- * Date: Generated on Sat Apr 6 03:07:45 2013
- * MD5 Checksum d41d8cd98f00b204e9800998ecf8427e
- *
- * Compiled with: RDB Utility combo_header.pl
- * RDB Parser 3.0
- * unknown unknown
- * Perl Interpreter 5.008008
- * Operating System linux
- *
- * Revision History:
- *
- * $brcm_Log: $
- *
- ***************************************************************************/
-
-#ifndef BCHP_HIF_TOP_CTRL_H__
-#define BCHP_HIF_TOP_CTRL_H__
-
-/***************************************************************************
- *HIF_TOP_CTRL - HIF Top Control Registers
- ***************************************************************************/
-#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL 0x203d2000 /* External IRQ Active Level Control Register */
-#define BCHP_HIF_TOP_CTRL_SPI_DBG_SEL 0x203d2004 /* SPI test port select register */
-#define BCHP_HIF_TOP_CTRL_SCRATCH 0x203d2008 /* HIF Scratch Register */
-#define BCHP_HIF_TOP_CTRL_PM_CTRL0 0x203d200c /* HIF Power Management Control0 Register */
-#define BCHP_HIF_TOP_CTRL_PM_CTRL1 0x203d2010 /* HIF Power Management Control1 Register */
-#define BCHP_HIF_TOP_CTRL_PM_CTRL2 0x203d2014 /* HIF Power Management Control Register:used to control SDIO_0 (CARD) */
-#define BCHP_HIF_TOP_CTRL_PM_CTRL3 0x203d2018 /* HIF Power Management Control Register:used to control SDIO_1 (EMMC) */
-#define BCHP_HIF_TOP_CTRL_FLASH_TYPE 0x203d201c /* HIF Decoded Flash Type */
-#define BCHP_HIF_TOP_CTRL_EMMC_PIN_CTRL 0x203d2038 /* EMMC Pin Control register */
-
-/***************************************************************************
- *EXT_IRQ_LEVEL - External IRQ Active Level Control Register
- ***************************************************************************/
-/* HIF_TOP_CTRL :: EXT_IRQ_LEVEL :: reserved0 [31:08] */
-#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_reserved0_MASK 0xffffff00
-#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_reserved0_SHIFT 8
-
-/* HIF_TOP_CTRL :: EXT_IRQ_LEVEL :: ext_irq_7_level [07:07] */
-#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_7_level_MASK 0x00000080
-#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_7_level_SHIFT 7
-#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_7_level_DEFAULT 0x00000000
-#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_7_level_LOW 0
-#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_7_level_HIGH 1
-
-/* HIF_TOP_CTRL :: EXT_IRQ_LEVEL :: ext_irq_6_level [06:06] */
-#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_6_level_MASK 0x00000040
-#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_6_level_SHIFT 6
-#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_6_level_DEFAULT 0x00000000
-#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_6_level_LOW 0
-#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_6_level_HIGH 1
-
-/* HIF_TOP_CTRL :: EXT_IRQ_LEVEL :: ext_irq_5_level [05:05] */
-#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_5_level_MASK 0x00000020
-#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_5_level_SHIFT 5
-#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_5_level_DEFAULT 0x00000000
-#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_5_level_LOW 0
-#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_5_level_HIGH 1
-
-/* HIF_TOP_CTRL :: EXT_IRQ_LEVEL :: ext_irq_4_level [04:04] */
-#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_4_level_MASK 0x00000010
-#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_4_level_SHIFT 4
-#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_4_level_DEFAULT 0x00000000
-#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_4_level_LOW 0
-#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_4_level_HIGH 1
-
-/* HIF_TOP_CTRL :: EXT_IRQ_LEVEL :: ext_irq_3_level [03:03] */
-#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_3_level_MASK 0x00000008
-#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_3_level_SHIFT 3
-#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_3_level_DEFAULT 0x00000000
-#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_3_level_LOW 0
-#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_3_level_HIGH 1
-
-/* HIF_TOP_CTRL :: EXT_IRQ_LEVEL :: ext_irq_2_level [02:02] */
-#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_2_level_MASK 0x00000004
-#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_2_level_SHIFT 2
-#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_2_level_DEFAULT 0x00000000
-#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_2_level_LOW 0
-#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_2_level_HIGH 1
-
-/* HIF_TOP_CTRL :: EXT_IRQ_LEVEL :: ext_irq_1_level [01:01] */
-#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_1_level_MASK 0x00000002
-#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_1_level_SHIFT 1
-#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_1_level_DEFAULT 0x00000000
-#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_1_level_LOW 0
-#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_1_level_HIGH 1
-
-/* HIF_TOP_CTRL :: EXT_IRQ_LEVEL :: ext_irq_0_level [00:00] */
-#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_0_level_MASK 0x00000001
-#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_0_level_SHIFT 0
-#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_0_level_DEFAULT 0x00000000
-#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_0_level_LOW 0
-#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_0_level_HIGH 1
-
-/***************************************************************************
- *SPI_DBG_SEL - SPI test port select register
- ***************************************************************************/
-/* HIF_TOP_CTRL :: SPI_DBG_SEL :: reserved0 [31:03] */
-#define BCHP_HIF_TOP_CTRL_SPI_DBG_SEL_reserved0_MASK 0xfffffff8
-#define BCHP_HIF_TOP_CTRL_SPI_DBG_SEL_reserved0_SHIFT 3
-
-/* HIF_TOP_CTRL :: SPI_DBG_SEL :: DISABLE_MSPI_FLUSH [02:02] */
-#define BCHP_HIF_TOP_CTRL_SPI_DBG_SEL_DISABLE_MSPI_FLUSH_MASK 0x00000004
-#define BCHP_HIF_TOP_CTRL_SPI_DBG_SEL_DISABLE_MSPI_FLUSH_SHIFT 2
-#define BCHP_HIF_TOP_CTRL_SPI_DBG_SEL_DISABLE_MSPI_FLUSH_DEFAULT 0x00000000
-
-/* HIF_TOP_CTRL :: SPI_DBG_SEL :: SPI_RBUS_TIMER_EN [01:01] */
-#define BCHP_HIF_TOP_CTRL_SPI_DBG_SEL_SPI_RBUS_TIMER_EN_MASK 0x00000002
-#define BCHP_HIF_TOP_CTRL_SPI_DBG_SEL_SPI_RBUS_TIMER_EN_SHIFT 1
-#define BCHP_HIF_TOP_CTRL_SPI_DBG_SEL_SPI_RBUS_TIMER_EN_DEFAULT 0x00000000
-
-/* HIF_TOP_CTRL :: SPI_DBG_SEL :: reserved1 [00:00] */
-#define BCHP_HIF_TOP_CTRL_SPI_DBG_SEL_reserved1_MASK 0x00000001
-#define BCHP_HIF_TOP_CTRL_SPI_DBG_SEL_reserved1_SHIFT 0
-
-/***************************************************************************
- *SCRATCH - HIF Scratch Register
- ***************************************************************************/
-/* HIF_TOP_CTRL :: SCRATCH :: SCRATCH_BITS [31:00] */
-#define BCHP_HIF_TOP_CTRL_SCRATCH_SCRATCH_BITS_MASK 0xffffffff
-#define BCHP_HIF_TOP_CTRL_SCRATCH_SCRATCH_BITS_SHIFT 0
-#define BCHP_HIF_TOP_CTRL_SCRATCH_SCRATCH_BITS_DEFAULT 0x00000000
-
-/***************************************************************************
- *PM_CTRL0 - HIF Power Management Control0 Register
- ***************************************************************************/
-/* HIF_TOP_CTRL :: PM_CTRL0 :: EBI_PM_IN_DRIVE_INACTIVE [31:30] */
-#define BCHP_HIF_TOP_CTRL_PM_CTRL0_EBI_PM_IN_DRIVE_INACTIVE_MASK 0xc0000000
-#define BCHP_HIF_TOP_CTRL_PM_CTRL0_EBI_PM_IN_DRIVE_INACTIVE_SHIFT 30
-#define BCHP_HIF_TOP_CTRL_PM_CTRL0_EBI_PM_IN_DRIVE_INACTIVE_DEFAULT 0x00000000
-#define BCHP_HIF_TOP_CTRL_PM_CTRL0_EBI_PM_IN_DRIVE_INACTIVE_FUNCTIONAL 0
-#define BCHP_HIF_TOP_CTRL_PM_CTRL0_EBI_PM_IN_DRIVE_INACTIVE_Low 1
-#define BCHP_HIF_TOP_CTRL_PM_CTRL0_EBI_PM_IN_DRIVE_INACTIVE_HIGH 2
-
-/* HIF_TOP_CTRL :: PM_CTRL0 :: NAND_DATA_PM_IN_DRIVE_INACTIVE [29:28] */
-#define BCHP_HIF_TOP_CTRL_PM_CTRL0_NAND_DATA_PM_IN_DRIVE_INACTIVE_MASK 0x30000000
-#define BCHP_HIF_TOP_CTRL_PM_CTRL0_NAND_DATA_PM_IN_DRIVE_INACTIVE_SHIFT 28
-#define BCHP_HIF_TOP_CTRL_PM_CTRL0_NAND_DATA_PM_IN_DRIVE_INACTIVE_DEFAULT 0x00000000
-#define BCHP_HIF_TOP_CTRL_PM_CTRL0_NAND_DATA_PM_IN_DRIVE_INACTIVE_FUNCTIONAL 0
-#define BCHP_HIF_TOP_CTRL_PM_CTRL0_NAND_DATA_PM_IN_DRIVE_INACTIVE_Low 1
-#define BCHP_HIF_TOP_CTRL_PM_CTRL0_NAND_DATA_PM_IN_DRIVE_INACTIVE_HIGH 2
-
-/* HIF_TOP_CTRL :: PM_CTRL0 :: NAND_CTRL_PM_IN_DRIVE_INACTIVE [27:26] */
-#define BCHP_HIF_TOP_CTRL_PM_CTRL0_NAND_CTRL_PM_IN_DRIVE_INACTIVE_MASK 0x0c000000
-#define BCHP_HIF_TOP_CTRL_PM_CTRL0_NAND_CTRL_PM_IN_DRIVE_INACTIVE_SHIFT 26
-#define BCHP_HIF_TOP_CTRL_PM_CTRL0_NAND_CTRL_PM_IN_DRIVE_INACTIVE_DEFAULT 0x00000000
-#define BCHP_HIF_TOP_CTRL_PM_CTRL0_NAND_CTRL_PM_IN_DRIVE_INACTIVE_FUNCTIONAL 0
-#define BCHP_HIF_TOP_CTRL_PM_CTRL0_NAND_CTRL_PM_IN_DRIVE_INACTIVE_NOT_USED 1
-#define BCHP_HIF_TOP_CTRL_PM_CTRL0_NAND_CTRL_PM_IN_DRIVE_INACTIVE_HIGH 2
-
-/* HIF_TOP_CTRL :: PM_CTRL0 :: EBI_DATA_PM_OUT_CTRL [25:24] */
-#define BCHP_HIF_TOP_CTRL_PM_CTRL0_EBI_DATA_PM_OUT_CTRL_MASK 0x03000000
-#define BCHP_HIF_TOP_CTRL_PM_CTRL0_EBI_DATA_PM_OUT_CTRL_SHIFT 24
-#define BCHP_HIF_TOP_CTRL_PM_CTRL0_EBI_DATA_PM_OUT_CTRL_DEFAULT 0x00000000
-#define BCHP_HIF_TOP_CTRL_PM_CTRL0_EBI_DATA_PM_OUT_CTRL_FUNCTIONAL 0
-#define BCHP_HIF_TOP_CTRL_PM_CTRL0_EBI_DATA_PM_OUT_CTRL_LOW 1
-#define BCHP_HIF_TOP_CTRL_PM_CTRL0_EBI_DATA_PM_OUT_CTRL_HIGH 2
-#define BCHP_HIF_TOP_CTRL_PM_CTRL0_EBI_DATA_PM_OUT_CTRL_Tristate 3
-
-/* HIF_TOP_CTRL :: PM_CTRL0 :: EBI_ADDR_PM_OUT_CTRL [23:22] */
-#define BCHP_HIF_TOP_CTRL_PM_CTRL0_EBI_ADDR_PM_OUT_CTRL_MASK 0x00c00000
-#define BCHP_HIF_TOP_CTRL_PM_CTRL0_EBI_ADDR_PM_OUT_CTRL_SHIFT 22
-#define BCHP_HIF_TOP_CTRL_PM_CTRL0_EBI_ADDR_PM_OUT_CTRL_DEFAULT 0x00000000
-#define BCHP_HIF_TOP_CTRL_PM_CTRL0_EBI_ADDR_PM_OUT_CTRL_FUNCTIONAL 0
-#define BCHP_HIF_TOP_CTRL_PM_CTRL0_EBI_ADDR_PM_OUT_CTRL_LOW 1
-#define BCHP_HIF_TOP_CTRL_PM_CTRL0_EBI_ADDR_PM_OUT_CTRL_HIGH 2
-#define BCHP_HIF_TOP_CTRL_PM_CTRL0_EBI_ADDR_PM_OUT_CTRL_Tristate 3
-
-/* HIF_TOP_CTRL :: PM_CTRL0 :: EBI_CTRL_PM_OUT_CTRL [21:20] */
-#define BCHP_HIF_TOP_CTRL_PM_CTRL0_EBI_CTRL_PM_OUT_CTRL_MASK 0x00300000
-#define BCHP_HIF_TOP_CTRL_PM_CTRL0_EBI_CTRL_PM_OUT_CTRL_SHIFT 20
-#define BCHP_HIF_TOP_CTRL_PM_CTRL0_EBI_CTRL_PM_OUT_CTRL_DEFAULT 0x00000000
-#define BCHP_HIF_TOP_CTRL_PM_CTRL0_EBI_CTRL_PM_OUT_CTRL_FUNCTIONAL 0
-#define BCHP_HIF_TOP_CTRL_PM_CTRL0_EBI_CTRL_PM_OUT_CTRL_LOW 1
-#define BCHP_HIF_TOP_CTRL_PM_CTRL0_EBI_CTRL_PM_OUT_CTRL_HIGH 2
-#define BCHP_HIF_TOP_CTRL_PM_CTRL0_EBI_CTRL_PM_OUT_CTRL_Tristate 3
-
-/* HIF_TOP_CTRL :: PM_CTRL0 :: NAND_DATA_PM_OUT_CTRL [19:18] */
-#define BCHP_HIF_TOP_CTRL_PM_CTRL0_NAND_DATA_PM_OUT_CTRL_MASK 0x000c0000
-#define BCHP_HIF_TOP_CTRL_PM_CTRL0_NAND_DATA_PM_OUT_CTRL_SHIFT 18
-#define BCHP_HIF_TOP_CTRL_PM_CTRL0_NAND_DATA_PM_OUT_CTRL_DEFAULT 0x00000000
-#define BCHP_HIF_TOP_CTRL_PM_CTRL0_NAND_DATA_PM_OUT_CTRL_FUNCTIONAL 0
-#define BCHP_HIF_TOP_CTRL_PM_CTRL0_NAND_DATA_PM_OUT_CTRL_LOW 1
-#define BCHP_HIF_TOP_CTRL_PM_CTRL0_NAND_DATA_PM_OUT_CTRL_HIGH 2
-#define BCHP_HIF_TOP_CTRL_PM_CTRL0_NAND_DATA_PM_OUT_CTRL_Tristate 3
-
-/* HIF_TOP_CTRL :: PM_CTRL0 :: NAND_CTRL_PM_OUT_CTRL [17:16] */
-#define BCHP_HIF_TOP_CTRL_PM_CTRL0_NAND_CTRL_PM_OUT_CTRL_MASK 0x00030000
-#define BCHP_HIF_TOP_CTRL_PM_CTRL0_NAND_CTRL_PM_OUT_CTRL_SHIFT 16
-#define BCHP_HIF_TOP_CTRL_PM_CTRL0_NAND_CTRL_PM_OUT_CTRL_DEFAULT 0x00000000
-#define BCHP_HIF_TOP_CTRL_PM_CTRL0_NAND_CTRL_PM_OUT_CTRL_FUNCTIONAL 0
-#define BCHP_HIF_TOP_CTRL_PM_CTRL0_NAND_CTRL_PM_OUT_CTRL_LOW 1
-#define BCHP_HIF_TOP_CTRL_PM_CTRL0_NAND_CTRL_PM_OUT_CTRL_HIGH 2
-#define BCHP_HIF_TOP_CTRL_PM_CTRL0_NAND_CTRL_PM_OUT_CTRL_Tristate 3
-
-/* HIF_TOP_CTRL :: PM_CTRL0 :: PM_OUT_CTRL_CS7 [15:14] */
-#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS7_MASK 0x0000c000
-#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS7_SHIFT 14
-#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS7_DEFAULT 0x00000000
-#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS7_FUNCTIONAL 0
-#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS7_LOW 1
-#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS7_HIGH 2
-#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS7_Tristate 3
-
-/* HIF_TOP_CTRL :: PM_CTRL0 :: PM_OUT_CTRL_CS6 [13:12] */
-#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS6_MASK 0x00003000
-#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS6_SHIFT 12
-#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS6_DEFAULT 0x00000000
-#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS6_FUNCTIONAL 0
-#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS6_LOW 1
-#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS6_HIGH 2
-#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS6_Tristate 3
-
-/* HIF_TOP_CTRL :: PM_CTRL0 :: PM_OUT_CTRL_CS5 [11:10] */
-#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS5_MASK 0x00000c00
-#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS5_SHIFT 10
-#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS5_DEFAULT 0x00000000
-#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS5_FUNCTIONAL 0
-#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS5_LOW 1
-#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS5_HIGH 2
-#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS5_Tristate 3
-
-/* HIF_TOP_CTRL :: PM_CTRL0 :: PM_OUT_CTRL_CS4 [09:08] */
-#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS4_MASK 0x00000300
-#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS4_SHIFT 8
-#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS4_DEFAULT 0x00000000
-#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS4_FUNCTIONAL 0
-#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS4_LOW 1
-#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS4_HIGH 2
-#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS4_Tristate 3
-
-/* HIF_TOP_CTRL :: PM_CTRL0 :: PM_OUT_CTRL_CS3 [07:06] */
-#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS3_MASK 0x000000c0
-#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS3_SHIFT 6
-#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS3_DEFAULT 0x00000000
-#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS3_FUNCTIONAL 0
-#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS3_LOW 1
-#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS3_HIGH 2
-#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS3_Tristate 3
-
-/* HIF_TOP_CTRL :: PM_CTRL0 :: PM_OUT_CTRL_CS2 [05:04] */
-#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS2_MASK 0x00000030
-#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS2_SHIFT 4
-#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS2_DEFAULT 0x00000000
-#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS2_FUNCTIONAL 0
-#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS2_LOW 1
-#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS2_HIGH 2
-#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS2_Tristate 3
-
-/* HIF_TOP_CTRL :: PM_CTRL0 :: PM_OUT_CTRL_CS1 [03:02] */
-#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS1_MASK 0x0000000c
-#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS1_SHIFT 2
-#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS1_DEFAULT 0x00000000
-#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS1_FUNCTIONAL 0
-#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS1_LOW 1
-#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS1_HIGH 2
-#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS1_Tristate 3
-
-/* HIF_TOP_CTRL :: PM_CTRL0 :: PM_OUT_CTRL_CS0 [01:00] */
-#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS0_MASK 0x00000003
-#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS0_SHIFT 0
-#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS0_DEFAULT 0x00000000
-#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS0_FUNCTIONAL 0
-#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS0_LOW 1
-#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS0_HIGH 2
-#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS0_Tristate 3
-
-/***************************************************************************
- *PM_CTRL1 - HIF Power Management Control1 Register
- ***************************************************************************/
-/* HIF_TOP_CTRL :: PM_CTRL1 :: reserved0 [31:12] */
-#define BCHP_HIF_TOP_CTRL_PM_CTRL1_reserved0_MASK 0xfffff000
-#define BCHP_HIF_TOP_CTRL_PM_CTRL1_reserved0_SHIFT 12
-
-/* HIF_TOP_CTRL :: PM_CTRL1 :: SPI_PM_IN_DRIVE_INACTIVE [11:10] */
-#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_PM_IN_DRIVE_INACTIVE_MASK 0x00000c00
-#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_PM_IN_DRIVE_INACTIVE_SHIFT 10
-#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_PM_IN_DRIVE_INACTIVE_DEFAULT 0x00000000
-#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_PM_IN_DRIVE_INACTIVE_FUNCTIONAL 0
-#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_PM_IN_DRIVE_INACTIVE_Low 1
-#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_PM_IN_DRIVE_INACTIVE_HIGH 2
-
-/* HIF_TOP_CTRL :: PM_CTRL1 :: SPI_WPB_PM_OUT_CTRL [09:08] */
-#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_WPB_PM_OUT_CTRL_MASK 0x00000300
-#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_WPB_PM_OUT_CTRL_SHIFT 8
-#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_WPB_PM_OUT_CTRL_DEFAULT 0x00000000
-#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_WPB_PM_OUT_CTRL_FUNCTIONAL 0
-#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_WPB_PM_OUT_CTRL_LOW 1
-#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_WPB_PM_OUT_CTRL_HIGH 2
-#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_WPB_PM_OUT_CTRL_Tristate 3
-
-/* HIF_TOP_CTRL :: PM_CTRL1 :: SPI_HOLDB_PM_OUT_CTRL [07:06] */
-#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_HOLDB_PM_OUT_CTRL_MASK 0x000000c0
-#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_HOLDB_PM_OUT_CTRL_SHIFT 6
-#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_HOLDB_PM_OUT_CTRL_DEFAULT 0x00000000
-#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_HOLDB_PM_OUT_CTRL_FUNCTIONAL 0
-#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_HOLDB_PM_OUT_CTRL_LOW 1
-#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_HOLDB_PM_OUT_CTRL_HIGH 2
-#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_HOLDB_PM_OUT_CTRL_Tristate 3
-
-/* HIF_TOP_CTRL :: PM_CTRL1 :: SPI_MISO_PM_OUT_CTRL [05:04] */
-#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_MISO_PM_OUT_CTRL_MASK 0x00000030
-#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_MISO_PM_OUT_CTRL_SHIFT 4
-#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_MISO_PM_OUT_CTRL_DEFAULT 0x00000000
-#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_MISO_PM_OUT_CTRL_FUNCTIONAL 0
-#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_MISO_PM_OUT_CTRL_LOW 1
-#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_MISO_PM_OUT_CTRL_HIGH 2
-#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_MISO_PM_OUT_CTRL_Tristate 3
-
-/* HIF_TOP_CTRL :: PM_CTRL1 :: SPI_MOSI_PM_OUT_CTRL [03:02] */
-#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_MOSI_PM_OUT_CTRL_MASK 0x0000000c
-#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_MOSI_PM_OUT_CTRL_SHIFT 2
-#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_MOSI_PM_OUT_CTRL_DEFAULT 0x00000000
-#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_MOSI_PM_OUT_CTRL_FUNCTIONAL 0
-#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_MOSI_PM_OUT_CTRL_LOW 1
-#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_MOSI_PM_OUT_CTRL_HIGH 2
-#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_MOSI_PM_OUT_CTRL_Tristate 3
-
-/* HIF_TOP_CTRL :: PM_CTRL1 :: SPI_CLK_PM_OUT_CTRL [01:00] */
-#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_CLK_PM_OUT_CTRL_MASK 0x00000003
-#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_CLK_PM_OUT_CTRL_SHIFT 0
-#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_CLK_PM_OUT_CTRL_DEFAULT 0x00000000
-#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_CLK_PM_OUT_CTRL_FUNCTIONAL 0
-#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_CLK_PM_OUT_CTRL_LOW 1
-#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_CLK_PM_OUT_CTRL_HIGH 2
-#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_CLK_PM_OUT_CTRL_Tristate 3
-
-/***************************************************************************
- *PM_CTRL2 - HIF Power Management Control Register:used to control SDIO_0 (CARD)
- ***************************************************************************/
-/* HIF_TOP_CTRL :: PM_CTRL2 :: reserved0 [31:24] */
-#define BCHP_HIF_TOP_CTRL_PM_CTRL2_reserved0_MASK 0xff000000
-#define BCHP_HIF_TOP_CTRL_PM_CTRL2_reserved0_SHIFT 24
-
-/* HIF_TOP_CTRL :: PM_CTRL2 :: SDIO_CARD_DETECT_PM_IN_DRIVE_INACTIVE [23:22] */
-#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_CARD_DETECT_PM_IN_DRIVE_INACTIVE_MASK 0x00c00000
-#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_CARD_DETECT_PM_IN_DRIVE_INACTIVE_SHIFT 22
-#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_CARD_DETECT_PM_IN_DRIVE_INACTIVE_DEFAULT 0x00000000
-#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_CARD_DETECT_PM_IN_DRIVE_INACTIVE_FUNCTIONAL 0
-#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_CARD_DETECT_PM_IN_DRIVE_INACTIVE_Low 1
-#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_CARD_DETECT_PM_IN_DRIVE_INACTIVE_HIGH 2
-
-/* HIF_TOP_CTRL :: PM_CTRL2 :: SDIO_WRITE_PROTECT_PM_IN_DRIVE_INACTIVE [21:20] */
-#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_WRITE_PROTECT_PM_IN_DRIVE_INACTIVE_MASK 0x00300000
-#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_WRITE_PROTECT_PM_IN_DRIVE_INACTIVE_SHIFT 20
-#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_WRITE_PROTECT_PM_IN_DRIVE_INACTIVE_DEFAULT 0x00000000
-#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_WRITE_PROTECT_PM_IN_DRIVE_INACTIVE_FUNCTIONAL 0
-#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_WRITE_PROTECT_PM_IN_DRIVE_INACTIVE_Low 1
-#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_WRITE_PROTECT_PM_IN_DRIVE_INACTIVE_HIGH 2
-
-/* HIF_TOP_CTRL :: PM_CTRL2 :: SDIO_DATA_PM_IN_DRIVE_INACTIVE [19:18] */
-#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_DATA_PM_IN_DRIVE_INACTIVE_MASK 0x000c0000
-#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_DATA_PM_IN_DRIVE_INACTIVE_SHIFT 18
-#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_DATA_PM_IN_DRIVE_INACTIVE_DEFAULT 0x00000000
-#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_DATA_PM_IN_DRIVE_INACTIVE_FUNCTIONAL 0
-#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_DATA_PM_IN_DRIVE_INACTIVE_Low 1
-#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_DATA_PM_IN_DRIVE_INACTIVE_HIGH 2
-
-/* HIF_TOP_CTRL :: PM_CTRL2 :: SDIO_CMD_PM_IN_DRIVE_INACTIVE [17:16] */
-#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_CMD_PM_IN_DRIVE_INACTIVE_MASK 0x00030000
-#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_CMD_PM_IN_DRIVE_INACTIVE_SHIFT 16
-#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_CMD_PM_IN_DRIVE_INACTIVE_DEFAULT 0x00000000
-#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_CMD_PM_IN_DRIVE_INACTIVE_FUNCTIONAL 0
-#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_CMD_PM_IN_DRIVE_INACTIVE_Low 1
-#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_CMD_PM_IN_DRIVE_INACTIVE_HIGH 2
-
-/* HIF_TOP_CTRL :: PM_CTRL2 :: reserved1 [15:12] */
-#define BCHP_HIF_TOP_CTRL_PM_CTRL2_reserved1_MASK 0x0000f000
-#define BCHP_HIF_TOP_CTRL_PM_CTRL2_reserved1_SHIFT 12
-
-/* HIF_TOP_CTRL :: PM_CTRL2 :: SDIO_VOLTAGE_PM_OUT_CTRL [11:10] */
-#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_VOLTAGE_PM_OUT_CTRL_MASK 0x00000c00
-#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_VOLTAGE_PM_OUT_CTRL_SHIFT 10
-#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_VOLTAGE_PM_OUT_CTRL_DEFAULT 0x00000000
-#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_VOLTAGE_PM_OUT_CTRL_FUNCTIONAL 0
-#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_VOLTAGE_PM_OUT_CTRL_LOW 1
-#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_VOLTAGE_PM_OUT_CTRL_HIGH 2
-#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_VOLTAGE_PM_OUT_CTRL_Tristate 3
-
-/* HIF_TOP_CTRL :: PM_CTRL2 :: SDIO_POWER_PM_OUT_CTRL [09:08] */
-#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_POWER_PM_OUT_CTRL_MASK 0x00000300
-#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_POWER_PM_OUT_CTRL_SHIFT 8
-#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_POWER_PM_OUT_CTRL_DEFAULT 0x00000000
-#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_POWER_PM_OUT_CTRL_FUNCTIONAL 0
-#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_POWER_PM_OUT_CTRL_LOW 1
-#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_POWER_PM_OUT_CTRL_HIGH 2
-#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_POWER_PM_OUT_CTRL_Tristate 3
-
-/* HIF_TOP_CTRL :: PM_CTRL2 :: SDIO_LED_PM_OUT_CTRL [07:06] */
-#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_LED_PM_OUT_CTRL_MASK 0x000000c0
-#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_LED_PM_OUT_CTRL_SHIFT 6
-#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_LED_PM_OUT_CTRL_DEFAULT 0x00000000
-#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_LED_PM_OUT_CTRL_FUNCTIONAL 0
-#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_LED_PM_OUT_CTRL_LOW 1
-#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_LED_PM_OUT_CTRL_HIGH 2
-#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_LED_PM_OUT_CTRL_Tristate 3
-
-/* HIF_TOP_CTRL :: PM_CTRL2 :: SDIO_DATA_PM_OUT_CTRL [05:04] */
-#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_DATA_PM_OUT_CTRL_MASK 0x00000030
-#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_DATA_PM_OUT_CTRL_SHIFT 4
-#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_DATA_PM_OUT_CTRL_DEFAULT 0x00000000
-#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_DATA_PM_OUT_CTRL_FUNCTIONAL 0
-#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_DATA_PM_OUT_CTRL_LOW 1
-#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_DATA_PM_OUT_CTRL_HIGH 2
-#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_DATA_PM_OUT_CTRL_Tristate 3
-
-/* HIF_TOP_CTRL :: PM_CTRL2 :: SDIO_CMD_PM_OUT_CTRL [03:02] */
-#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_CMD_PM_OUT_CTRL_MASK 0x0000000c
-#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_CMD_PM_OUT_CTRL_SHIFT 2
-#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_CMD_PM_OUT_CTRL_DEFAULT 0x00000000
-#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_CMD_PM_OUT_CTRL_FUNCTIONAL 0
-#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_CMD_PM_OUT_CTRL_LOW 1
-#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_CMD_PM_OUT_CTRL_HIGH 2
-#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_CMD_PM_OUT_CTRL_Tristate 3
-
-/* HIF_TOP_CTRL :: PM_CTRL2 :: SDIO_CLK_PM_OUT_CTRL [01:00] */
-#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_CLK_PM_OUT_CTRL_MASK 0x00000003
-#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_CLK_PM_OUT_CTRL_SHIFT 0
-#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_CLK_PM_OUT_CTRL_DEFAULT 0x00000000
-#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_CLK_PM_OUT_CTRL_FUNCTIONAL 0
-#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_CLK_PM_OUT_CTRL_LOW 1
-#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_CLK_PM_OUT_CTRL_HIGH 2
-#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_CLK_PM_OUT_CTRL_Tristate 3
-
-/***************************************************************************
- *PM_CTRL3 - HIF Power Management Control Register:used to control SDIO_1 (EMMC)
- ***************************************************************************/
-/* HIF_TOP_CTRL :: PM_CTRL3 :: reserved0 [31:24] */
-#define BCHP_HIF_TOP_CTRL_PM_CTRL3_reserved0_MASK 0xff000000
-#define BCHP_HIF_TOP_CTRL_PM_CTRL3_reserved0_SHIFT 24
-
-/* HIF_TOP_CTRL :: PM_CTRL3 :: SDIO_CARD_DETECT_PM_IN_DRIVE_INACTIVE [23:22] */
-#define BCHP_HIF_TOP_CTRL_PM_CTRL3_SDIO_CARD_DETECT_PM_IN_DRIVE_INACTIVE_MASK 0x00c00000
-#define BCHP_HIF_TOP_CTRL_PM_CTRL3_SDIO_CARD_DETECT_PM_IN_DRIVE_INACTIVE_SHIFT 22
-#define BCHP_HIF_TOP_CTRL_PM_CTRL3_SDIO_CARD_DETECT_PM_IN_DRIVE_INACTIVE_DEFAULT 0x00000000
-#define BCHP_HIF_TOP_CTRL_PM_CTRL3_SDIO_CARD_DETECT_PM_IN_DRIVE_INACTIVE_FUNCTIONAL 0
-#define BCHP_HIF_TOP_CTRL_PM_CTRL3_SDIO_CARD_DETECT_PM_IN_DRIVE_INACTIVE_Low 1
-#define BCHP_HIF_TOP_CTRL_PM_CTRL3_SDIO_CARD_DETECT_PM_IN_DRIVE_INACTIVE_HIGH 2
-
-/* HIF_TOP_CTRL :: PM_CTRL3 :: SDIO_WRITE_PROTECT_PM_IN_DRIVE_INACTIVE [21:20] */
-#define BCHP_HIF_TOP_CTRL_PM_CTRL3_SDIO_WRITE_PROTECT_PM_IN_DRIVE_INACTIVE_MASK 0x00300000
-#define BCHP_HIF_TOP_CTRL_PM_CTRL3_SDIO_WRITE_PROTECT_PM_IN_DRIVE_INACTIVE_SHIFT 20
-#define BCHP_HIF_TOP_CTRL_PM_CTRL3_SDIO_WRITE_PROTECT_PM_IN_DRIVE_INACTIVE_DEFAULT 0x00000000
-#define BCHP_HIF_TOP_CTRL_PM_CTRL3_SDIO_WRITE_PROTECT_PM_IN_DRIVE_INACTIVE_FUNCTIONAL 0
-#define BCHP_HIF_TOP_CTRL_PM_CTRL3_SDIO_WRITE_PROTECT_PM_IN_DRIVE_INACTIVE_Low 1
-#define BCHP_HIF_TOP_CTRL_PM_CTRL3_SDIO_WRITE_PROTECT_PM_IN_DRIVE_INACTIVE_HIGH 2
-
-/* HIF_TOP_CTRL :: PM_CTRL3 :: SDIO_DATA_PM_IN_DRIVE_INACTIVE [19:18] */
-#define BCHP_HIF_TOP_CTRL_PM_CTRL3_SDIO_DATA_PM_IN_DRIVE_INACTIVE_MASK 0x000c0000
-#define BCHP_HIF_TOP_CTRL_PM_CTRL3_SDIO_DATA_PM_IN_DRIVE_INACTIVE_SHIFT 18
-#define BCHP_HIF_TOP_CTRL_PM_CTRL3_SDIO_DATA_PM_IN_DRIVE_INACTIVE_DEFAULT 0x00000000
-#define BCHP_HIF_TOP_CTRL_PM_CTRL3_SDIO_DATA_PM_IN_DRIVE_INACTIVE_FUNCTIONAL 0
-#define BCHP_HIF_TOP_CTRL_PM_CTRL3_SDIO_DATA_PM_IN_DRIVE_INACTIVE_Low 1
-#define BCHP_HIF_TOP_CTRL_PM_CTRL3_SDIO_DATA_PM_IN_DRIVE_INACTIVE_HIGH 2
-
-/* HIF_TOP_CTRL :: PM_CTRL3 :: SDIO_CMD_PM_IN_DRIVE_INACTIVE [17:16] */
-#define BCHP_HIF_TOP_CTRL_PM_CTRL3_SDIO_CMD_PM_IN_DRIVE_INACTIVE_MASK 0x00030000
-#define BCHP_HIF_TOP_CTRL_PM_CTRL3_SDIO_CMD_PM_IN_DRIVE_INACTIVE_SHIFT 16
-#define BCHP_HIF_TOP_CTRL_PM_CTRL3_SDIO_CMD_PM_IN_DRIVE_INACTIVE_DEFAULT 0x00000000
-#define BCHP_HIF_TOP_CTRL_PM_CTRL3_SDIO_CMD_PM_IN_DRIVE_INACTIVE_FUNCTIONAL 0
-#define BCHP_HIF_TOP_CTRL_PM_CTRL3_SDIO_CMD_PM_IN_DRIVE_INACTIVE_Low 1
-#define BCHP_HIF_TOP_CTRL_PM_CTRL3_SDIO_CMD_PM_IN_DRIVE_INACTIVE_HIGH 2
-
-/* HIF_TOP_CTRL :: PM_CTRL3 :: reserved1 [15:12] */
-#define BCHP_HIF_TOP_CTRL_PM_CTRL3_reserved1_MASK 0x0000f000
-#define BCHP_HIF_TOP_CTRL_PM_CTRL3_reserved1_SHIFT 12
-
-/* HIF_TOP_CTRL :: PM_CTRL3 :: SDIO_VOLTAGE_PM_OUT_CTRL [11:10] */
-#define BCHP_HIF_TOP_CTRL_PM_CTRL3_SDIO_VOLTAGE_PM_OUT_CTRL_MASK 0x00000c00
-#define BCHP_HIF_TOP_CTRL_PM_CTRL3_SDIO_VOLTAGE_PM_OUT_CTRL_SHIFT 10
-#define BCHP_HIF_TOP_CTRL_PM_CTRL3_SDIO_VOLTAGE_PM_OUT_CTRL_DEFAULT 0x00000000
-#define BCHP_HIF_TOP_CTRL_PM_CTRL3_SDIO_VOLTAGE_PM_OUT_CTRL_FUNCTIONAL 0
-#define BCHP_HIF_TOP_CTRL_PM_CTRL3_SDIO_VOLTAGE_PM_OUT_CTRL_LOW 1
-#define BCHP_HIF_TOP_CTRL_PM_CTRL3_SDIO_VOLTAGE_PM_OUT_CTRL_HIGH 2
-#define BCHP_HIF_TOP_CTRL_PM_CTRL3_SDIO_VOLTAGE_PM_OUT_CTRL_Tristate 3
-
-/* HIF_TOP_CTRL :: PM_CTRL3 :: SDIO_POWER_PM_OUT_CTRL [09:08] */
-#define BCHP_HIF_TOP_CTRL_PM_CTRL3_SDIO_POWER_PM_OUT_CTRL_MASK 0x00000300
-#define BCHP_HIF_TOP_CTRL_PM_CTRL3_SDIO_POWER_PM_OUT_CTRL_SHIFT 8
-#define BCHP_HIF_TOP_CTRL_PM_CTRL3_SDIO_POWER_PM_OUT_CTRL_DEFAULT 0x00000000
-#define BCHP_HIF_TOP_CTRL_PM_CTRL3_SDIO_POWER_PM_OUT_CTRL_FUNCTIONAL 0
-#define BCHP_HIF_TOP_CTRL_PM_CTRL3_SDIO_POWER_PM_OUT_CTRL_LOW 1
-#define BCHP_HIF_TOP_CTRL_PM_CTRL3_SDIO_POWER_PM_OUT_CTRL_HIGH 2
-#define BCHP_HIF_TOP_CTRL_PM_CTRL3_SDIO_POWER_PM_OUT_CTRL_Tristate 3
-
-/* HIF_TOP_CTRL :: PM_CTRL3 :: SDIO_LED_PM_OUT_CTRL [07:06] */
-#define BCHP_HIF_TOP_CTRL_PM_CTRL3_SDIO_LED_PM_OUT_CTRL_MASK 0x000000c0
-#define BCHP_HIF_TOP_CTRL_PM_CTRL3_SDIO_LED_PM_OUT_CTRL_SHIFT 6
-#define BCHP_HIF_TOP_CTRL_PM_CTRL3_SDIO_LED_PM_OUT_CTRL_DEFAULT 0x00000000
-#define BCHP_HIF_TOP_CTRL_PM_CTRL3_SDIO_LED_PM_OUT_CTRL_FUNCTIONAL 0
-#define BCHP_HIF_TOP_CTRL_PM_CTRL3_SDIO_LED_PM_OUT_CTRL_LOW 1
-#define BCHP_HIF_TOP_CTRL_PM_CTRL3_SDIO_LED_PM_OUT_CTRL_HIGH 2
-#define BCHP_HIF_TOP_CTRL_PM_CTRL3_SDIO_LED_PM_OUT_CTRL_Tristate 3
-
-/* HIF_TOP_CTRL :: PM_CTRL3 :: SDIO_DATA_PM_OUT_CTRL [05:04] */
-#define BCHP_HIF_TOP_CTRL_PM_CTRL3_SDIO_DATA_PM_OUT_CTRL_MASK 0x00000030
-#define BCHP_HIF_TOP_CTRL_PM_CTRL3_SDIO_DATA_PM_OUT_CTRL_SHIFT 4
-#define BCHP_HIF_TOP_CTRL_PM_CTRL3_SDIO_DATA_PM_OUT_CTRL_DEFAULT 0x00000000
-#define BCHP_HIF_TOP_CTRL_PM_CTRL3_SDIO_DATA_PM_OUT_CTRL_FUNCTIONAL 0
-#define BCHP_HIF_TOP_CTRL_PM_CTRL3_SDIO_DATA_PM_OUT_CTRL_LOW 1
-#define BCHP_HIF_TOP_CTRL_PM_CTRL3_SDIO_DATA_PM_OUT_CTRL_HIGH 2
-#define BCHP_HIF_TOP_CTRL_PM_CTRL3_SDIO_DATA_PM_OUT_CTRL_Tristate 3
-
-/* HIF_TOP_CTRL :: PM_CTRL3 :: SDIO_CMD_PM_OUT_CTRL [03:02] */
-#define BCHP_HIF_TOP_CTRL_PM_CTRL3_SDIO_CMD_PM_OUT_CTRL_MASK 0x0000000c
-#define BCHP_HIF_TOP_CTRL_PM_CTRL3_SDIO_CMD_PM_OUT_CTRL_SHIFT 2
-#define BCHP_HIF_TOP_CTRL_PM_CTRL3_SDIO_CMD_PM_OUT_CTRL_DEFAULT 0x00000000
-#define BCHP_HIF_TOP_CTRL_PM_CTRL3_SDIO_CMD_PM_OUT_CTRL_FUNCTIONAL 0
-#define BCHP_HIF_TOP_CTRL_PM_CTRL3_SDIO_CMD_PM_OUT_CTRL_LOW 1
-#define BCHP_HIF_TOP_CTRL_PM_CTRL3_SDIO_CMD_PM_OUT_CTRL_HIGH 2
-#define BCHP_HIF_TOP_CTRL_PM_CTRL3_SDIO_CMD_PM_OUT_CTRL_Tristate 3
-
-/* HIF_TOP_CTRL :: PM_CTRL3 :: SDIO_CLK_PM_OUT_CTRL [01:00] */
-#define BCHP_HIF_TOP_CTRL_PM_CTRL3_SDIO_CLK_PM_OUT_CTRL_MASK 0x00000003
-#define BCHP_HIF_TOP_CTRL_PM_CTRL3_SDIO_CLK_PM_OUT_CTRL_SHIFT 0
-#define BCHP_HIF_TOP_CTRL_PM_CTRL3_SDIO_CLK_PM_OUT_CTRL_DEFAULT 0x00000000
-#define BCHP_HIF_TOP_CTRL_PM_CTRL3_SDIO_CLK_PM_OUT_CTRL_FUNCTIONAL 0
-#define BCHP_HIF_TOP_CTRL_PM_CTRL3_SDIO_CLK_PM_OUT_CTRL_LOW 1
-#define BCHP_HIF_TOP_CTRL_PM_CTRL3_SDIO_CLK_PM_OUT_CTRL_HIGH 2
-#define BCHP_HIF_TOP_CTRL_PM_CTRL3_SDIO_CLK_PM_OUT_CTRL_Tristate 3
-
-/***************************************************************************
- *FLASH_TYPE - HIF Decoded Flash Type
- ***************************************************************************/
-/* HIF_TOP_CTRL :: FLASH_TYPE :: reserved0 [31:03] */
-#define BCHP_HIF_TOP_CTRL_FLASH_TYPE_reserved0_MASK 0xfffffff8
-#define BCHP_HIF_TOP_CTRL_FLASH_TYPE_reserved0_SHIFT 3
-
-/* HIF_TOP_CTRL :: FLASH_TYPE :: InvalidStrap [02:02] */
-#define BCHP_HIF_TOP_CTRL_FLASH_TYPE_InvalidStrap_MASK 0x00000004
-#define BCHP_HIF_TOP_CTRL_FLASH_TYPE_InvalidStrap_SHIFT 2
-#define BCHP_HIF_TOP_CTRL_FLASH_TYPE_InvalidStrap_DEFAULT 0x00000000
-
-/* HIF_TOP_CTRL :: FLASH_TYPE :: FLASH_TYPE [01:00] */
-#define BCHP_HIF_TOP_CTRL_FLASH_TYPE_FLASH_TYPE_MASK 0x00000003
-#define BCHP_HIF_TOP_CTRL_FLASH_TYPE_FLASH_TYPE_SHIFT 0
-#define BCHP_HIF_TOP_CTRL_FLASH_TYPE_FLASH_TYPE_ParallelNOR 0
-#define BCHP_HIF_TOP_CTRL_FLASH_TYPE_FLASH_TYPE_Nand 1
-#define BCHP_HIF_TOP_CTRL_FLASH_TYPE_FLASH_TYPE_SerialNOR 2
-#define BCHP_HIF_TOP_CTRL_FLASH_TYPE_FLASH_TYPE_eMMC 3
-
-/***************************************************************************
- *EMMC_PIN_CTRL - EMMC Pin Control register
- ***************************************************************************/
-/* HIF_TOP_CTRL :: EMMC_PIN_CTRL :: reserved0 [31:02] */
-#define BCHP_HIF_TOP_CTRL_EMMC_PIN_CTRL_reserved0_MASK 0xfffffffc
-#define BCHP_HIF_TOP_CTRL_EMMC_PIN_CTRL_reserved0_SHIFT 2
-
-/* HIF_TOP_CTRL :: EMMC_PIN_CTRL :: EMMC_PIN_SEL [01:00] */
-#define BCHP_HIF_TOP_CTRL_EMMC_PIN_CTRL_EMMC_PIN_SEL_MASK 0x00000003
-#define BCHP_HIF_TOP_CTRL_EMMC_PIN_CTRL_EMMC_PIN_SEL_SHIFT 0
-#define BCHP_HIF_TOP_CTRL_EMMC_PIN_CTRL_EMMC_PIN_SEL_DEFAULT 0x00000001
-
-#endif /* #ifndef BCHP_HIF_TOP_CTRL_H__ */
-
-/* End of File */
diff --git a/include/linux/brcmstb/7145a0/bchp_irq0.h b/include/linux/brcmstb/7145a0/bchp_irq0.h
deleted file mode 100644
index c08b318..0000000
--- a/include/linux/brcmstb/7145a0/bchp_irq0.h
+++ /dev/null
@@ -1,174 +0,0 @@
-/***************************************************************************
- * Copyright (c) 1999-2013, Broadcom Corporation
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
- *
- * Module Description:
- * DO NOT EDIT THIS FILE DIRECTLY
- *
- * This module was generated magically with RDB from a source description
- * file. You must edit the source file for changes to be made to this file.
- *
- *
- * Date: Generated on Sat Apr 6 03:07:51 2013
- * MD5 Checksum d41d8cd98f00b204e9800998ecf8427e
- *
- * Compiled with: RDB Utility combo_header.pl
- * RDB Parser 3.0
- * unknown unknown
- * Perl Interpreter 5.008008
- * Operating System linux
- *
- * Revision History:
- *
- * $brcm_Log: $
- *
- ***************************************************************************/
-
-#ifndef BCHP_IRQ0_H__
-#define BCHP_IRQ0_H__
-
-/***************************************************************************
- *IRQ0 - Level 2 CPU Interrupt Enable/Status
- ***************************************************************************/
-#define BCHP_IRQ0_IRQEN 0x20406840 /* Interrupt Enable */
-#define BCHP_IRQ0_IRQSTAT 0x20406844 /* Interrupt Status */
-
-/***************************************************************************
- *IRQEN - Interrupt Enable
- ***************************************************************************/
-/* IRQ0 :: IRQEN :: reserved0 [31:11] */
-#define BCHP_IRQ0_IRQEN_reserved0_MASK 0xfffff800
-#define BCHP_IRQ0_IRQEN_reserved0_SHIFT 11
-
-/* IRQ0 :: IRQEN :: irb_irqen [10:10] */
-#define BCHP_IRQ0_IRQEN_irb_irqen_MASK 0x00000400
-#define BCHP_IRQ0_IRQEN_irb_irqen_SHIFT 10
-#define BCHP_IRQ0_IRQEN_irb_irqen_DEFAULT 0x00000000
-
-/* IRQ0 :: IRQEN :: gio_irqen [09:09] */
-#define BCHP_IRQ0_IRQEN_gio_irqen_MASK 0x00000200
-#define BCHP_IRQ0_IRQEN_gio_irqen_SHIFT 9
-#define BCHP_IRQ0_IRQEN_gio_irqen_DEFAULT 0x00000000
-
-/* IRQ0 :: IRQEN :: iice_irqen [08:08] */
-#define BCHP_IRQ0_IRQEN_iice_irqen_MASK 0x00000100
-#define BCHP_IRQ0_IRQEN_iice_irqen_SHIFT 8
-#define BCHP_IRQ0_IRQEN_iice_irqen_DEFAULT 0x00000000
-
-/* IRQ0 :: IRQEN :: iicd_irqen [07:07] */
-#define BCHP_IRQ0_IRQEN_iicd_irqen_MASK 0x00000080
-#define BCHP_IRQ0_IRQEN_iicd_irqen_SHIFT 7
-#define BCHP_IRQ0_IRQEN_iicd_irqen_DEFAULT 0x00000000
-
-/* IRQ0 :: IRQEN :: iica_irqen [06:06] */
-#define BCHP_IRQ0_IRQEN_iica_irqen_MASK 0x00000040
-#define BCHP_IRQ0_IRQEN_iica_irqen_SHIFT 6
-#define BCHP_IRQ0_IRQEN_iica_irqen_DEFAULT 0x00000000
-
-/* IRQ0 :: IRQEN :: uc_irqen [05:05] */
-#define BCHP_IRQ0_IRQEN_uc_irqen_MASK 0x00000020
-#define BCHP_IRQ0_IRQEN_uc_irqen_SHIFT 5
-#define BCHP_IRQ0_IRQEN_uc_irqen_DEFAULT 0x00000000
-
-/* IRQ0 :: IRQEN :: ub_irqen [04:04] */
-#define BCHP_IRQ0_IRQEN_ub_irqen_MASK 0x00000010
-#define BCHP_IRQ0_IRQEN_ub_irqen_SHIFT 4
-#define BCHP_IRQ0_IRQEN_ub_irqen_DEFAULT 0x00000000
-
-/* IRQ0 :: IRQEN :: ua_irqen [03:03] */
-#define BCHP_IRQ0_IRQEN_ua_irqen_MASK 0x00000008
-#define BCHP_IRQ0_IRQEN_ua_irqen_SHIFT 3
-#define BCHP_IRQ0_IRQEN_ua_irqen_DEFAULT 0x00000000
-
-/* IRQ0 :: IRQEN :: uartc_irqen [02:02] */
-#define BCHP_IRQ0_IRQEN_uartc_irqen_MASK 0x00000004
-#define BCHP_IRQ0_IRQEN_uartc_irqen_SHIFT 2
-#define BCHP_IRQ0_IRQEN_uartc_irqen_DEFAULT 0x00000000
-
-/* IRQ0 :: IRQEN :: uartb_irqen [01:01] */
-#define BCHP_IRQ0_IRQEN_uartb_irqen_MASK 0x00000002
-#define BCHP_IRQ0_IRQEN_uartb_irqen_SHIFT 1
-#define BCHP_IRQ0_IRQEN_uartb_irqen_DEFAULT 0x00000000
-
-/* IRQ0 :: IRQEN :: uarta_irqen [00:00] */
-#define BCHP_IRQ0_IRQEN_uarta_irqen_MASK 0x00000001
-#define BCHP_IRQ0_IRQEN_uarta_irqen_SHIFT 0
-#define BCHP_IRQ0_IRQEN_uarta_irqen_DEFAULT 0x00000000
-
-/***************************************************************************
- *IRQSTAT - Interrupt Status
- ***************************************************************************/
-/* IRQ0 :: IRQSTAT :: reserved0 [31:11] */
-#define BCHP_IRQ0_IRQSTAT_reserved0_MASK 0xfffff800
-#define BCHP_IRQ0_IRQSTAT_reserved0_SHIFT 11
-
-/* IRQ0 :: IRQSTAT :: irbirq [10:10] */
-#define BCHP_IRQ0_IRQSTAT_irbirq_MASK 0x00000400
-#define BCHP_IRQ0_IRQSTAT_irbirq_SHIFT 10
-#define BCHP_IRQ0_IRQSTAT_irbirq_DEFAULT 0x00000000
-
-/* IRQ0 :: IRQSTAT :: gioirq [09:09] */
-#define BCHP_IRQ0_IRQSTAT_gioirq_MASK 0x00000200
-#define BCHP_IRQ0_IRQSTAT_gioirq_SHIFT 9
-#define BCHP_IRQ0_IRQSTAT_gioirq_DEFAULT 0x00000000
-
-/* IRQ0 :: IRQSTAT :: iiceirq [08:08] */
-#define BCHP_IRQ0_IRQSTAT_iiceirq_MASK 0x00000100
-#define BCHP_IRQ0_IRQSTAT_iiceirq_SHIFT 8
-#define BCHP_IRQ0_IRQSTAT_iiceirq_DEFAULT 0x00000000
-
-/* IRQ0 :: IRQSTAT :: iicdirq [07:07] */
-#define BCHP_IRQ0_IRQSTAT_iicdirq_MASK 0x00000080
-#define BCHP_IRQ0_IRQSTAT_iicdirq_SHIFT 7
-#define BCHP_IRQ0_IRQSTAT_iicdirq_DEFAULT 0x00000000
-
-/* IRQ0 :: IRQSTAT :: iicairq [06:06] */
-#define BCHP_IRQ0_IRQSTAT_iicairq_MASK 0x00000040
-#define BCHP_IRQ0_IRQSTAT_iicairq_SHIFT 6
-#define BCHP_IRQ0_IRQSTAT_iicairq_DEFAULT 0x00000000
-
-/* IRQ0 :: IRQSTAT :: ucirq [05:05] */
-#define BCHP_IRQ0_IRQSTAT_ucirq_MASK 0x00000020
-#define BCHP_IRQ0_IRQSTAT_ucirq_SHIFT 5
-#define BCHP_IRQ0_IRQSTAT_ucirq_DEFAULT 0x00000000
-
-/* IRQ0 :: IRQSTAT :: ubirq [04:04] */
-#define BCHP_IRQ0_IRQSTAT_ubirq_MASK 0x00000010
-#define BCHP_IRQ0_IRQSTAT_ubirq_SHIFT 4
-#define BCHP_IRQ0_IRQSTAT_ubirq_DEFAULT 0x00000000
-
-/* IRQ0 :: IRQSTAT :: uairq [03:03] */
-#define BCHP_IRQ0_IRQSTAT_uairq_MASK 0x00000008
-#define BCHP_IRQ0_IRQSTAT_uairq_SHIFT 3
-#define BCHP_IRQ0_IRQSTAT_uairq_DEFAULT 0x00000000
-
-/* IRQ0 :: IRQSTAT :: uartc_irq [02:02] */
-#define BCHP_IRQ0_IRQSTAT_uartc_irq_MASK 0x00000004
-#define BCHP_IRQ0_IRQSTAT_uartc_irq_SHIFT 2
-#define BCHP_IRQ0_IRQSTAT_uartc_irq_DEFAULT 0x00000000
-
-/* IRQ0 :: IRQSTAT :: uartb_irq [01:01] */
-#define BCHP_IRQ0_IRQSTAT_uartb_irq_MASK 0x00000002
-#define BCHP_IRQ0_IRQSTAT_uartb_irq_SHIFT 1
-#define BCHP_IRQ0_IRQSTAT_uartb_irq_DEFAULT 0x00000000
-
-/* IRQ0 :: IRQSTAT :: uarta_irq [00:00] */
-#define BCHP_IRQ0_IRQSTAT_uarta_irq_MASK 0x00000001
-#define BCHP_IRQ0_IRQSTAT_uarta_irq_SHIFT 0
-#define BCHP_IRQ0_IRQSTAT_uarta_irq_DEFAULT 0x00000000
-
-#endif /* #ifndef BCHP_IRQ0_H__ */
-
-/* End of File */
diff --git a/include/linux/brcmstb/7145a0/bchp_irq1.h b/include/linux/brcmstb/7145a0/bchp_irq1.h
deleted file mode 100644
index 05e5e4c..0000000
--- a/include/linux/brcmstb/7145a0/bchp_irq1.h
+++ /dev/null
@@ -1,174 +0,0 @@
-/***************************************************************************
- * Copyright (c) 1999-2013, Broadcom Corporation
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
- *
- * Module Description:
- * DO NOT EDIT THIS FILE DIRECTLY
- *
- * This module was generated magically with RDB from a source description
- * file. You must edit the source file for changes to be made to this file.
- *
- *
- * Date: Generated on Sat Apr 6 03:07:50 2013
- * MD5 Checksum d41d8cd98f00b204e9800998ecf8427e
- *
- * Compiled with: RDB Utility combo_header.pl
- * RDB Parser 3.0
- * unknown unknown
- * Perl Interpreter 5.008008
- * Operating System linux
- *
- * Revision History:
- *
- * $brcm_Log: $
- *
- ***************************************************************************/
-
-#ifndef BCHP_IRQ1_H__
-#define BCHP_IRQ1_H__
-
-/***************************************************************************
- *IRQ1 - Level 2 PCI Interrupt Enable/Status
- ***************************************************************************/
-#define BCHP_IRQ1_IRQEN 0x20406800 /* Interrupt Enable */
-#define BCHP_IRQ1_IRQSTAT 0x20406804 /* Interrupt Status */
-
-/***************************************************************************
- *IRQEN - Interrupt Enable
- ***************************************************************************/
-/* IRQ1 :: IRQEN :: reserved0 [31:11] */
-#define BCHP_IRQ1_IRQEN_reserved0_MASK 0xfffff800
-#define BCHP_IRQ1_IRQEN_reserved0_SHIFT 11
-
-/* IRQ1 :: IRQEN :: irb_irqen [10:10] */
-#define BCHP_IRQ1_IRQEN_irb_irqen_MASK 0x00000400
-#define BCHP_IRQ1_IRQEN_irb_irqen_SHIFT 10
-#define BCHP_IRQ1_IRQEN_irb_irqen_DEFAULT 0x00000000
-
-/* IRQ1 :: IRQEN :: gio_irqen [09:09] */
-#define BCHP_IRQ1_IRQEN_gio_irqen_MASK 0x00000200
-#define BCHP_IRQ1_IRQEN_gio_irqen_SHIFT 9
-#define BCHP_IRQ1_IRQEN_gio_irqen_DEFAULT 0x00000000
-
-/* IRQ1 :: IRQEN :: iice_irqen [08:08] */
-#define BCHP_IRQ1_IRQEN_iice_irqen_MASK 0x00000100
-#define BCHP_IRQ1_IRQEN_iice_irqen_SHIFT 8
-#define BCHP_IRQ1_IRQEN_iice_irqen_DEFAULT 0x00000000
-
-/* IRQ1 :: IRQEN :: iicd_irqen [07:07] */
-#define BCHP_IRQ1_IRQEN_iicd_irqen_MASK 0x00000080
-#define BCHP_IRQ1_IRQEN_iicd_irqen_SHIFT 7
-#define BCHP_IRQ1_IRQEN_iicd_irqen_DEFAULT 0x00000000
-
-/* IRQ1 :: IRQEN :: iica_irqen [06:06] */
-#define BCHP_IRQ1_IRQEN_iica_irqen_MASK 0x00000040
-#define BCHP_IRQ1_IRQEN_iica_irqen_SHIFT 6
-#define BCHP_IRQ1_IRQEN_iica_irqen_DEFAULT 0x00000000
-
-/* IRQ1 :: IRQEN :: uc_irqen [05:05] */
-#define BCHP_IRQ1_IRQEN_uc_irqen_MASK 0x00000020
-#define BCHP_IRQ1_IRQEN_uc_irqen_SHIFT 5
-#define BCHP_IRQ1_IRQEN_uc_irqen_DEFAULT 0x00000000
-
-/* IRQ1 :: IRQEN :: ub_irqen [04:04] */
-#define BCHP_IRQ1_IRQEN_ub_irqen_MASK 0x00000010
-#define BCHP_IRQ1_IRQEN_ub_irqen_SHIFT 4
-#define BCHP_IRQ1_IRQEN_ub_irqen_DEFAULT 0x00000000
-
-/* IRQ1 :: IRQEN :: ua_irqen [03:03] */
-#define BCHP_IRQ1_IRQEN_ua_irqen_MASK 0x00000008
-#define BCHP_IRQ1_IRQEN_ua_irqen_SHIFT 3
-#define BCHP_IRQ1_IRQEN_ua_irqen_DEFAULT 0x00000000
-
-/* IRQ1 :: IRQEN :: uartc_irqen [02:02] */
-#define BCHP_IRQ1_IRQEN_uartc_irqen_MASK 0x00000004
-#define BCHP_IRQ1_IRQEN_uartc_irqen_SHIFT 2
-#define BCHP_IRQ1_IRQEN_uartc_irqen_DEFAULT 0x00000000
-
-/* IRQ1 :: IRQEN :: uartb_irqen [01:01] */
-#define BCHP_IRQ1_IRQEN_uartb_irqen_MASK 0x00000002
-#define BCHP_IRQ1_IRQEN_uartb_irqen_SHIFT 1
-#define BCHP_IRQ1_IRQEN_uartb_irqen_DEFAULT 0x00000000
-
-/* IRQ1 :: IRQEN :: uarta_irqen [00:00] */
-#define BCHP_IRQ1_IRQEN_uarta_irqen_MASK 0x00000001
-#define BCHP_IRQ1_IRQEN_uarta_irqen_SHIFT 0
-#define BCHP_IRQ1_IRQEN_uarta_irqen_DEFAULT 0x00000000
-
-/***************************************************************************
- *IRQSTAT - Interrupt Status
- ***************************************************************************/
-/* IRQ1 :: IRQSTAT :: reserved0 [31:11] */
-#define BCHP_IRQ1_IRQSTAT_reserved0_MASK 0xfffff800
-#define BCHP_IRQ1_IRQSTAT_reserved0_SHIFT 11
-
-/* IRQ1 :: IRQSTAT :: irbirq [10:10] */
-#define BCHP_IRQ1_IRQSTAT_irbirq_MASK 0x00000400
-#define BCHP_IRQ1_IRQSTAT_irbirq_SHIFT 10
-#define BCHP_IRQ1_IRQSTAT_irbirq_DEFAULT 0x00000000
-
-/* IRQ1 :: IRQSTAT :: gioirq [09:09] */
-#define BCHP_IRQ1_IRQSTAT_gioirq_MASK 0x00000200
-#define BCHP_IRQ1_IRQSTAT_gioirq_SHIFT 9
-#define BCHP_IRQ1_IRQSTAT_gioirq_DEFAULT 0x00000000
-
-/* IRQ1 :: IRQSTAT :: iiceirq [08:08] */
-#define BCHP_IRQ1_IRQSTAT_iiceirq_MASK 0x00000100
-#define BCHP_IRQ1_IRQSTAT_iiceirq_SHIFT 8
-#define BCHP_IRQ1_IRQSTAT_iiceirq_DEFAULT 0x00000000
-
-/* IRQ1 :: IRQSTAT :: iicdirq [07:07] */
-#define BCHP_IRQ1_IRQSTAT_iicdirq_MASK 0x00000080
-#define BCHP_IRQ1_IRQSTAT_iicdirq_SHIFT 7
-#define BCHP_IRQ1_IRQSTAT_iicdirq_DEFAULT 0x00000000
-
-/* IRQ1 :: IRQSTAT :: iicairq [06:06] */
-#define BCHP_IRQ1_IRQSTAT_iicairq_MASK 0x00000040
-#define BCHP_IRQ1_IRQSTAT_iicairq_SHIFT 6
-#define BCHP_IRQ1_IRQSTAT_iicairq_DEFAULT 0x00000000
-
-/* IRQ1 :: IRQSTAT :: ucirq [05:05] */
-#define BCHP_IRQ1_IRQSTAT_ucirq_MASK 0x00000020
-#define BCHP_IRQ1_IRQSTAT_ucirq_SHIFT 5
-#define BCHP_IRQ1_IRQSTAT_ucirq_DEFAULT 0x00000000
-
-/* IRQ1 :: IRQSTAT :: ubirq [04:04] */
-#define BCHP_IRQ1_IRQSTAT_ubirq_MASK 0x00000010
-#define BCHP_IRQ1_IRQSTAT_ubirq_SHIFT 4
-#define BCHP_IRQ1_IRQSTAT_ubirq_DEFAULT 0x00000000
-
-/* IRQ1 :: IRQSTAT :: uairq [03:03] */
-#define BCHP_IRQ1_IRQSTAT_uairq_MASK 0x00000008
-#define BCHP_IRQ1_IRQSTAT_uairq_SHIFT 3
-#define BCHP_IRQ1_IRQSTAT_uairq_DEFAULT 0x00000000
-
-/* IRQ1 :: IRQSTAT :: uartc_irq [02:02] */
-#define BCHP_IRQ1_IRQSTAT_uartc_irq_MASK 0x00000004
-#define BCHP_IRQ1_IRQSTAT_uartc_irq_SHIFT 2
-#define BCHP_IRQ1_IRQSTAT_uartc_irq_DEFAULT 0x00000000
-
-/* IRQ1 :: IRQSTAT :: uartb_irq [01:01] */
-#define BCHP_IRQ1_IRQSTAT_uartb_irq_MASK 0x00000002
-#define BCHP_IRQ1_IRQSTAT_uartb_irq_SHIFT 1
-#define BCHP_IRQ1_IRQSTAT_uartb_irq_DEFAULT 0x00000000
-
-/* IRQ1 :: IRQSTAT :: uarta_irq [00:00] */
-#define BCHP_IRQ1_IRQSTAT_uarta_irq_MASK 0x00000001
-#define BCHP_IRQ1_IRQSTAT_uarta_irq_SHIFT 0
-#define BCHP_IRQ1_IRQSTAT_uarta_irq_DEFAULT 0x00000000
-
-#endif /* #ifndef BCHP_IRQ1_H__ */
-
-/* End of File */
diff --git a/include/linux/brcmstb/7145a0/bchp_memc_arb_1.h b/include/linux/brcmstb/7145a0/bchp_memc_arb_1.h
deleted file mode 100644
index 8ddb381..0000000
--- a/include/linux/brcmstb/7145a0/bchp_memc_arb_1.h
+++ /dev/null
@@ -1,8093 +0,0 @@
-/***************************************************************************
- * Copyright (c) 1999-2013, Broadcom Corporation
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
- *
- * Module Description:
- * DO NOT EDIT THIS FILE DIRECTLY
- *
- * This module was generated magically with RDB from a source description
- * file. You must edit the source file for changes to be made to this file.
- *
- *
- * Date: Generated on Sat Apr 6 03:07:45 2013
- * MD5 Checksum d41d8cd98f00b204e9800998ecf8427e
- *
- * Compiled with: RDB Utility combo_header.pl
- * RDB Parser 3.0
- * unknown unknown
- * Perl Interpreter 5.008008
- * Operating System linux
- *
- * Revision History:
- *
- * $brcm_Log: $
- *
- ***************************************************************************/
-
-#ifndef BCHP_MEMC_ARB_1_H__
-#define BCHP_MEMC_ARB_1_H__
-
-/***************************************************************************
- *MEMC_ARB_1 - 1 Arbitration & Client Info Registers
- ***************************************************************************/
-#define BCHP_MEMC_ARB_1_PHY_DEBUG_REGISTER 0x203c1000 /* MEMC CORE and IOBUF Interface Debug Register */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_0 0x203c1004 /* Client Programming register for client 0. */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_1 0x203c1008 /* Client Programming register for client 1. */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_2 0x203c100c /* Client Programming register for client 2. */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_3 0x203c1010 /* Client Programming register for client 3. */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_4 0x203c1014 /* Client Programming register for client 4. */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_5 0x203c1018 /* Client Programming register for client 5. */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_6 0x203c101c /* Client Programming register for client 6. */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_7 0x203c1020 /* Client Programming register for client 7. */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_8 0x203c1024 /* Client Programming register for client 8. */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_9 0x203c1028 /* Client Programming register for client 9. */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_10 0x203c102c /* Client Programming register for client 10. */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_11 0x203c1030 /* Client Programming register for client 11. */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_12 0x203c1034 /* Client Programming register for client 12. */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_13 0x203c1038 /* Client Programming register for client 13. */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_14 0x203c103c /* Client Programming register for client 14. */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_15 0x203c1040 /* Client Programming register for client 15. */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_16 0x203c1044 /* Client Programming register for client 16. */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_17 0x203c1048 /* Client Programming register for client 17. */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_18 0x203c104c /* Client Programming register for client 18. */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_19 0x203c1050 /* Client Programming register for client 19. */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_20 0x203c1054 /* Client Programming register for client 20. */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_21 0x203c1058 /* Client Programming register for client 21. */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_22 0x203c105c /* Client Programming register for client 22. */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_23 0x203c1060 /* Client Programming register for client 23. */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_24 0x203c1064 /* Client Programming register for client 24. */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_25 0x203c1068 /* Client Programming register for client 25. */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_26 0x203c106c /* Client Programming register for client 26. */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_27 0x203c1070 /* Client Programming register for client 27. */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_28 0x203c1074 /* Client Programming register for client 28. */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_29 0x203c1078 /* Client Programming register for client 29. */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_30 0x203c107c /* Client Programming register for client 30. */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_31 0x203c1080 /* Client Programming register for client 31. */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_32 0x203c1084 /* Client Programming register for client 32. */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_33 0x203c1088 /* Client Programming register for client 33. */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_34 0x203c108c /* Client Programming register for client 34. */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_35 0x203c1090 /* Client Programming register for client 35. */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_36 0x203c1094 /* Client Programming register for client 36. */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_37 0x203c1098 /* Client Programming register for client 37. */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_38 0x203c109c /* Client Programming register for client 38. */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_39 0x203c10a0 /* Client Programming register for client 39. */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_40 0x203c10a4 /* Client Programming register for client 40. */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_41 0x203c10a8 /* Client Programming register for client 41. */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_42 0x203c10ac /* Client Programming register for client 42. */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_43 0x203c10b0 /* Client Programming register for client 43. */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_44 0x203c10b4 /* Client Programming register for client 44. */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_45 0x203c10b8 /* Client Programming register for client 45. */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_46 0x203c10bc /* Client Programming register for client 46. */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_47 0x203c10c0 /* Client Programming register for client 47. */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_48 0x203c10c4 /* Client Programming register for client 48. */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_49 0x203c10c8 /* Client Programming register for client 49. */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_50 0x203c10cc /* Client Programming register for client 50. */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_51 0x203c10d0 /* Client Programming register for client 51. */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_52 0x203c10d4 /* Client Programming register for client 52. */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_53 0x203c10d8 /* Client Programming register for client 53. */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_54 0x203c10dc /* Client Programming register for client 54. */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_55 0x203c10e0 /* Client Programming register for client 55. */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_56 0x203c10e4 /* Client Programming register for client 56. */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_57 0x203c10e8 /* Client Programming register for client 57. */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_58 0x203c10ec /* Client Programming register for client 58. */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_59 0x203c10f0 /* Client Programming register for client 59. */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_60 0x203c10f4 /* Client Programming register for client 60. */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_61 0x203c10f8 /* Client Programming register for client 61. */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_62 0x203c10fc /* Client Programming register for client 62. */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_63 0x203c1100 /* Client Programming register for client 63. */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_64 0x203c1104 /* Client Programming register for client 64. */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_65 0x203c1108 /* Client Programming register for client 65. */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_66 0x203c110c /* Client Programming register for client 66. */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_67 0x203c1110 /* Client Programming register for client 67. */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_68 0x203c1114 /* Client Programming register for client 68. */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_69 0x203c1118 /* Client Programming register for client 69. */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_70 0x203c111c /* Client Programming register for client 70. */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_71 0x203c1120 /* Client Programming register for client 71. */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_72 0x203c1124 /* Client Programming register for client 72. */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_73 0x203c1128 /* Client Programming register for client 73. */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_74 0x203c112c /* Client Programming register for client 74. */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_75 0x203c1130 /* Client Programming register for client 75. */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_76 0x203c1134 /* Client Programming register for client 76. */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_77 0x203c1138 /* Client Programming register for client 77. */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_78 0x203c113c /* Client Programming register for client 78. */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_79 0x203c1140 /* Client Programming register for client 79. */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_80 0x203c1144 /* Client Programming register for client 80. */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_81 0x203c1148 /* Client Programming register for client 81. */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_82 0x203c114c /* Client Programming register for client 82. */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_83 0x203c1150 /* Client Programming register for client 83. */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_84 0x203c1154 /* Client Programming register for client 84. */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_85 0x203c1158 /* Client Programming register for client 85. */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_86 0x203c115c /* Client Programming register for client 86. */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_87 0x203c1160 /* Client Programming register for client 87. */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_88 0x203c1164 /* Client Programming register for client 88. */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_89 0x203c1168 /* Client Programming register for client 89. */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_90 0x203c116c /* Client Programming register for client 90. */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_91 0x203c1170 /* Client Programming register for client 91. */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_92 0x203c1174 /* Client Programming register for client 92. */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_93 0x203c1178 /* Client Programming register for client 93. */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_94 0x203c117c /* Client Programming register for client 94. */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_95 0x203c1180 /* Client Programming register for client 95. */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_96 0x203c1184 /* Client Programming register for client 96. */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_97 0x203c1188 /* Client Programming register for client 97. */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_98 0x203c118c /* Client Programming register for client 98. */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_99 0x203c1190 /* Client Programming register for client 99. */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_100 0x203c1194 /* Client Programming register for client 100. */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_101 0x203c1198 /* Client Programming register for client 101. */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_102 0x203c119c /* Client Programming register for client 102. */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_103 0x203c11a0 /* Client Programming register for client 103. */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_104 0x203c11a4 /* Client Programming register for client 104. */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_105 0x203c11a8 /* Client Programming register for client 105. */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_106 0x203c11ac /* Client Programming register for client 106. */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_107 0x203c11b0 /* Client Programming register for client 107. */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_108 0x203c11b4 /* Client Programming register for client 108. */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_109 0x203c11b8 /* Client Programming register for client 109. */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_110 0x203c11bc /* Client Programming register for client 110. */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_111 0x203c11c0 /* Client Programming register for client 111. */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_112 0x203c11c4 /* Client Programming register for client 112. */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_113 0x203c11c8 /* Client Programming register for client 113. */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_114 0x203c11cc /* Client Programming register for client 114. */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_115 0x203c11d0 /* Client Programming register for client 115. */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_116 0x203c11d4 /* Client Programming register for client 116. */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_117 0x203c11d8 /* Client Programming register for client 117. */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_118 0x203c11dc /* Client Programming register for client 118. */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_119 0x203c11e0 /* Client Programming register for client 119. */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_120 0x203c11e4 /* Client Programming register for client 120. */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_121 0x203c11e8 /* Client Programming register for client 121. */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_122 0x203c11ec /* Client Programming register for client 122. */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_123 0x203c11f0 /* Client Programming register for client 123. */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_124 0x203c11f4 /* Client Programming register for client 124. */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_125 0x203c11f8 /* Client Programming register for client 125. */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_126 0x203c11fc /* Client Programming register for client 126. */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_127 0x203c1200 /* Client Programming register for client 127 */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_128 0x203c1204 /* Client Programming register for client 128. */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_129 0x203c1208 /* Client Programming register for client 129. */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_130 0x203c120c /* Client Programming register for client 130. */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_131 0x203c1210 /* Client Programming register for client 131. */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_132 0x203c1214 /* Client Programming register for client 132. */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_133 0x203c1218 /* Client Programming register for client 133. */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_134 0x203c121c /* Client Programming register for client 134. */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_135 0x203c1220 /* Client Programming register for client 135. */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_136 0x203c1224 /* Client Programming register for client 136. */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_137 0x203c1228 /* Client Programming register for client 137. */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_138 0x203c122c /* Client Programming register for client 138. */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_139 0x203c1230 /* Client Programming register for client 139. */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_140 0x203c1234 /* Client Programming register for client 140. */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_141 0x203c1238 /* Client Programming register for client 141. */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_142 0x203c123c /* Client Programming register for client 142. */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_143 0x203c1240 /* Client Programming register for client 143. */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_144 0x203c1244 /* Client Programming register for client 144. */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_145 0x203c1248 /* Client Programming register for client 145. */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_146 0x203c124c /* Client Programming register for client 146. */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_147 0x203c1250 /* Client Programming register for client 147. */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_148 0x203c1254 /* Client Programming register for client 148. */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_149 0x203c1258 /* Client Programming register for client 149. */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_150 0x203c125c /* Client Programming register for client 150. */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_151 0x203c1260 /* Client Programming register for client 151. */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_152 0x203c1264 /* Client Programming register for client 152. */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_153 0x203c1268 /* Client Programming register for client 153. */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_154 0x203c126c /* Client Programming register for client 154. */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_155 0x203c1270 /* Client Programming register for client 155. */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_156 0x203c1274 /* Client Programming register for client 156. */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_157 0x203c1278 /* Client Programming register for client 157. */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_158 0x203c127c /* Client Programming register for client 158. */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_159 0x203c1280 /* Client Programming register for client 159. */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_160 0x203c1284 /* Client Programming register for client 160. */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_161 0x203c1288 /* Client Programming register for client 161. */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_162 0x203c128c /* Client Programming register for client 162. */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_163 0x203c1290 /* Client Programming register for client 163. */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_164 0x203c1294 /* Client Programming register for client 164. */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_165 0x203c1298 /* Client Programming register for client 165. */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_166 0x203c129c /* Client Programming register for client 166. */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_167 0x203c12a0 /* Client Programming register for client 167. */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_168 0x203c12a4 /* Client Programming register for client 168. */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_169 0x203c12a8 /* Client Programming register for client 169. */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_170 0x203c12ac /* Client Programming register for client 170. */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_171 0x203c12b0 /* Client Programming register for client 171. */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_172 0x203c12b4 /* Client Programming register for client 172. */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_173 0x203c12b8 /* Client Programming register for client 173. */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_174 0x203c12bc /* Client Programming register for client 174. */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_175 0x203c12c0 /* Client Programming register for client 175. */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_176 0x203c12c4 /* Client Programming register for client 176. */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_177 0x203c12c8 /* Client Programming register for client 177. */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_178 0x203c12cc /* Client Programming register for client 178. */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_179 0x203c12d0 /* Client Programming register for client 179. */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_180 0x203c12d4 /* Client Programming register for client 180. */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_181 0x203c12d8 /* Client Programming register for client 181. */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_182 0x203c12dc /* Client Programming register for client 182. */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_183 0x203c12e0 /* Client Programming register for client 183. */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_184 0x203c12e4 /* Client Programming register for client 184. */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_185 0x203c12e8 /* Client Programming register for client 185. */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_186 0x203c12ec /* Client Programming register for client 186. */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_187 0x203c12f0 /* Client Programming register for client 187. */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_188 0x203c12f4 /* Client Programming register for client 188. */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_189 0x203c12f8 /* Client Programming register for client 189. */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_190 0x203c12fc /* Client Programming register for client 190. */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_191 0x203c1300 /* Client Programming register for client 191. */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_192 0x203c1304 /* Client Programming register for client 192. */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_193 0x203c1308 /* Client Programming register for client 193. */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_194 0x203c130c /* Client Programming register for client 194. */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_195 0x203c1310 /* Client Programming register for client 195. */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_196 0x203c1314 /* Client Programming register for client 196. */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_197 0x203c1318 /* Client Programming register for client 197. */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_198 0x203c131c /* Client Programming register for client 198. */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_199 0x203c1320 /* Client Programming register for client 199. */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_200 0x203c1324 /* Client Programming register for client 200. */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_201 0x203c1328 /* Client Programming register for client 201. */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_202 0x203c132c /* Client Programming register for client 202. */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_203 0x203c1330 /* Client Programming register for client 203. */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_204 0x203c1334 /* Client Programming register for client 204. */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_205 0x203c1338 /* Client Programming register for client 205. */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_206 0x203c133c /* Client Programming register for client 206. */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_207 0x203c1340 /* Client Programming register for client 207. */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_208 0x203c1344 /* Client Programming register for client 208. */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_209 0x203c1348 /* Client Programming register for client 209. */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_210 0x203c134c /* Client Programming register for client 210. */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_211 0x203c1350 /* Client Programming register for client 211. */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_212 0x203c1354 /* Client Programming register for client 212. */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_213 0x203c1358 /* Client Programming register for client 213. */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_214 0x203c135c /* Client Programming register for client 214. */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_215 0x203c1360 /* Client Programming register for client 215. */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_216 0x203c1364 /* Client Programming register for client 216. */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_217 0x203c1368 /* Client Programming register for client 217. */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_218 0x203c136c /* Client Programming register for client 218. */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_219 0x203c1370 /* Client Programming register for client 219. */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_220 0x203c1374 /* Client Programming register for client 220. */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_221 0x203c1378 /* Client Programming register for client 221. */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_222 0x203c137c /* Client Programming register for client 222. */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_223 0x203c1380 /* Client Programming register for client 223. */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_224 0x203c1384 /* Client Programming register for client 224. */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_225 0x203c1388 /* Client Programming register for client 225. */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_226 0x203c138c /* Client Programming register for client 226. */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_227 0x203c1390 /* Client Programming register for client 227. */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_228 0x203c1394 /* Client Programming register for client 228. */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_229 0x203c1398 /* Client Programming register for client 229. */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_230 0x203c139c /* Client Programming register for client 230. */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_231 0x203c13a0 /* Client Programming register for client 231. */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_232 0x203c13a4 /* Client Programming register for client 232. */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_233 0x203c13a8 /* Client Programming register for client 233. */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_234 0x203c13ac /* Client Programming register for client 234. */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_235 0x203c13b0 /* Client Programming register for client 235. */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_236 0x203c13b4 /* Client Programming register for client 236. */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_237 0x203c13b8 /* Client Programming register for client 237. */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_238 0x203c13bc /* Client Programming register for client 238. */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_239 0x203c13c0 /* Client Programming register for client 239. */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_240 0x203c13c4 /* Client Programming register for client 240. */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_241 0x203c13c8 /* Client Programming register for client 241. */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_242 0x203c13cc /* Client Programming register for client 242. */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_243 0x203c13d0 /* Client Programming register for client 243. */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_244 0x203c13d4 /* Client Programming register for client 244. */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_245 0x203c13d8 /* Client Programming register for client 245. */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_246 0x203c13dc /* Client Programming register for client 246. */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_247 0x203c13e0 /* Client Programming register for client 247. */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_248 0x203c13e4 /* Client Programming register for client 248. */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_249 0x203c13e8 /* Client Programming register for client 249. */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_250 0x203c13ec /* Client Programming register for client 250. */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_251 0x203c13f0 /* Client Programming register for client 251. */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_252 0x203c13f4 /* Client Programming register for client 252. */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_253 0x203c13f8 /* Client Programming register for client 253. */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_254 0x203c13fc /* Client Programming register for client 254. */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_255 0x203c1400 /* Client Programming register for client 255 */
-#define BCHP_MEMC_ARB_1_REQ_MASK_0 0x203c1404 /* Request Mask register for Clients 0 to 31 */
-#define BCHP_MEMC_ARB_1_REQ_MASK_1 0x203c1408 /* Request Mask register for Clients 32 to 63 */
-#define BCHP_MEMC_ARB_1_REQ_MASK_2 0x203c140c /* Request Mask register for Clients 64 to 95 */
-#define BCHP_MEMC_ARB_1_REQ_MASK_3 0x203c1410 /* Request Mask register for Clients 96 to 127 */
-#define BCHP_MEMC_ARB_1_REQ_MASK_4 0x203c1414 /* Request Mask register for Clients 128 to 159 */
-#define BCHP_MEMC_ARB_1_REQ_MASK_5 0x203c1418 /* Request Mask register for Clients 160 to 191 */
-#define BCHP_MEMC_ARB_1_REQ_MASK_6 0x203c141c /* Request Mask register for Clients 192 to 223 */
-#define BCHP_MEMC_ARB_1_REQ_MASK_7 0x203c1420 /* Request Mask register for Clients 224 to 255 */
-#define BCHP_MEMC_ARB_1_ARB_WINNER 0x203c1424 /* SCB-Arbitration Winner. */
-#define BCHP_MEMC_ARB_1_RTS_ERR_0 0x203c1428 /* RTS Deadline miss register for Clients 0 to 31 */
-#define BCHP_MEMC_ARB_1_RTS_ERR_1 0x203c142c /* RTS Deadline miss register for Clients 32 to 63 */
-#define BCHP_MEMC_ARB_1_RTS_ERR_2 0x203c1430 /* RTS Deadline miss register for Clients 64 to 95 */
-#define BCHP_MEMC_ARB_1_RTS_ERR_3 0x203c1434 /* RTS Deadline miss register for Clients 96 to 127 */
-#define BCHP_MEMC_ARB_1_RTS_ERR_4 0x203c1438 /* RTS Deadline miss register for Clients 128 to 159 */
-#define BCHP_MEMC_ARB_1_RTS_ERR_5 0x203c143c /* RTS Deadline miss register for Clients 160 to 191 */
-#define BCHP_MEMC_ARB_1_RTS_ERR_6 0x203c1440 /* RTS Deadline miss register for Clients 192 to 223 */
-#define BCHP_MEMC_ARB_1_RTS_ERR_7 0x203c1444 /* RTS Deadline miss register for Clients 224 to 255 */
-#define BCHP_MEMC_ARB_1_FULLNESS_THRESHOLD 0x203c1448 /* Arbiter fullness threshold register */
-#define BCHP_MEMC_ARB_1_FULLNESS_UPDATE_HOLDOFF 0x203c144c /* SCB and MCP Write Fullness Update Holdoff register */
-#define BCHP_MEMC_ARB_1_MINIMUM_COMMAND_SIZE 0x203c1450 /* Minimum command size register */
-#define BCHP_MEMC_ARB_1_MINIMUM_COMMAND_SIZE2 0x203c1454 /* Minimum command size register for UBUS */
-#define BCHP_MEMC_ARB_1_RTS_ERR_INFO_WRITE_CLEAR 0x203c1458 /* MEMC RTS_ERR_INFO write clear register */
-#define BCHP_MEMC_ARB_1_SCB_ARBITER_DEBUG_REGISTER 0x203c145c /* MEMC SCB Interface and Arbiter State Machine and FIFO Debug Register */
-#define BCHP_MEMC_ARB_1_SPARE_1 0x203c1460 /* Spare Register 1 . */
-#define BCHP_MEMC_ARB_1_SPARE_2 0x203c1464 /* Spare Register 2 . */
-#define BCHP_MEMC_ARB_1_SPARE_RO_1 0x203c1468 /* Read only Spare Register 1 . */
-#define BCHP_MEMC_ARB_1_SPARE_RO_2 0x203c146c /* Read only Spare Register 2 . */
-#define BCHP_MEMC_ARB_1_CLIENT_INIT_ENABLE 0x203c1470 /* "Enable for client init block." */
-#define BCHP_MEMC_ARB_1_CLIENT_INIT_COUNTER_THRESH 0x203c1474 /* "Client init block counter threshold value" */
-#define BCHP_MEMC_ARB_1_CLIENT_INIT_ERROR_INTERRUPT 0x203c1478 /* "Client init error interrupt" */
-#define BCHP_MEMC_ARB_1_CLIENT_INIT_ERROR_WRITE_CLEAR 0x203c147c /* "Client init error write clear" */
-#define BCHP_MEMC_ARB_1_CLIENT_INIT_ERROR_INFO 0x203c1480 /* "Client init error violation info" */
-#define BCHP_MEMC_ARB_1_CLIENT_INIT_SW_INIT 0x203c1484 /* "Client init software init" */
-#define BCHP_MEMC_ARB_1_CLIENT_INIT_STATUS 0x203c1488 /* "Client init status and debug register" */
-#define BCHP_MEMC_ARB_1_LCA_VALID_REQ_0 0x203c148c /* LCA Valid Requests for Clients 0 to 31 */
-#define BCHP_MEMC_ARB_1_LCA_VALID_REQ_1 0x203c1490 /* LCA Valid Requests for Clients 32 to 63 */
-#define BCHP_MEMC_ARB_1_LCA_VALID_REQ_2 0x203c1494 /* LCA Valid Requests for Clients64 to 95 */
-#define BCHP_MEMC_ARB_1_LCA_VALID_REQ_3 0x203c1498 /* LCA Valid Requests for Clients 96 to 127 */
-#define BCHP_MEMC_ARB_1_LCA_VALID_REQ_4 0x203c149c /* LCA Valid Requests for Clients 128 to 159 */
-#define BCHP_MEMC_ARB_1_LCA_VALID_REQ_5 0x203c14a0 /* LCA Valid Requests for Clients 160 to 191 */
-#define BCHP_MEMC_ARB_1_LCA_VALID_REQ_6 0x203c14a4 /* LCA Valid Requests for Clients 192 to 223 */
-#define BCHP_MEMC_ARB_1_LCA_VALID_REQ_7 0x203c14a8 /* LCA Valid Requests for Clients 224 to 255 */
-
-/***************************************************************************
- *PHY_DEBUG_REGISTER - MEMC CORE and IOBUF Interface Debug Register
- ***************************************************************************/
-/* MEMC_ARB_1 :: PHY_DEBUG_REGISTER :: reserved0 [31:08] */
-#define BCHP_MEMC_ARB_1_PHY_DEBUG_REGISTER_reserved0_MASK 0xffffff00
-#define BCHP_MEMC_ARB_1_PHY_DEBUG_REGISTER_reserved0_SHIFT 8
-
-/* MEMC_ARB_1 :: PHY_DEBUG_REGISTER :: PMC2MEMC_BSP_RDY [07:07] */
-#define BCHP_MEMC_ARB_1_PHY_DEBUG_REGISTER_PMC2MEMC_BSP_RDY_MASK 0x00000080
-#define BCHP_MEMC_ARB_1_PHY_DEBUG_REGISTER_PMC2MEMC_BSP_RDY_SHIFT 7
-
-/* MEMC_ARB_1 :: PHY_DEBUG_REGISTER :: PHY2CORE_INIT_RDY [06:06] */
-#define BCHP_MEMC_ARB_1_PHY_DEBUG_REGISTER_PHY2CORE_INIT_RDY_MASK 0x00000040
-#define BCHP_MEMC_ARB_1_PHY_DEBUG_REGISTER_PHY2CORE_INIT_RDY_SHIFT 6
-
-/* MEMC_ARB_1 :: PHY_DEBUG_REGISTER :: PHY2CORE_POWERDOWN_RDY [05:05] */
-#define BCHP_MEMC_ARB_1_PHY_DEBUG_REGISTER_PHY2CORE_POWERDOWN_RDY_MASK 0x00000020
-#define BCHP_MEMC_ARB_1_PHY_DEBUG_REGISTER_PHY2CORE_POWERDOWN_RDY_SHIFT 5
-
-/* MEMC_ARB_1 :: PHY_DEBUG_REGISTER :: IO2C_CMD_DATA_FIFO_FULL [04:04] */
-#define BCHP_MEMC_ARB_1_PHY_DEBUG_REGISTER_IO2C_CMD_DATA_FIFO_FULL_MASK 0x00000010
-#define BCHP_MEMC_ARB_1_PHY_DEBUG_REGISTER_IO2C_CMD_DATA_FIFO_FULL_SHIFT 4
-
-/* MEMC_ARB_1 :: PHY_DEBUG_REGISTER :: IO2C_RD_DATA_FIFO_EMPTY [03:03] */
-#define BCHP_MEMC_ARB_1_PHY_DEBUG_REGISTER_IO2C_RD_DATA_FIFO_EMPTY_MASK 0x00000008
-#define BCHP_MEMC_ARB_1_PHY_DEBUG_REGISTER_IO2C_RD_DATA_FIFO_EMPTY_SHIFT 3
-
-/* MEMC_ARB_1 :: PHY_DEBUG_REGISTER :: C2IO_CMD_DATA_FIFO_PUSH [02:02] */
-#define BCHP_MEMC_ARB_1_PHY_DEBUG_REGISTER_C2IO_CMD_DATA_FIFO_PUSH_MASK 0x00000004
-#define BCHP_MEMC_ARB_1_PHY_DEBUG_REGISTER_C2IO_CMD_DATA_FIFO_PUSH_SHIFT 2
-
-/* MEMC_ARB_1 :: PHY_DEBUG_REGISTER :: DRAM_RD_DATA_FIFO_POP [01:01] */
-#define BCHP_MEMC_ARB_1_PHY_DEBUG_REGISTER_DRAM_RD_DATA_FIFO_POP_MASK 0x00000002
-#define BCHP_MEMC_ARB_1_PHY_DEBUG_REGISTER_DRAM_RD_DATA_FIFO_POP_SHIFT 1
-
-/* MEMC_ARB_1 :: PHY_DEBUG_REGISTER :: CORE2PHY_PLL_DLL_SHUTDOWN_REQ [00:00] */
-#define BCHP_MEMC_ARB_1_PHY_DEBUG_REGISTER_CORE2PHY_PLL_DLL_SHUTDOWN_REQ_MASK 0x00000001
-#define BCHP_MEMC_ARB_1_PHY_DEBUG_REGISTER_CORE2PHY_PLL_DLL_SHUTDOWN_REQ_SHIFT 0
-
-/***************************************************************************
- *CLIENT_INFO_0 - Client Programming register for client 0.
- ***************************************************************************/
-/* MEMC_ARB_1 :: CLIENT_INFO_0 :: RR_EN [31:31] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_0_RR_EN_MASK 0x80000000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_0_RR_EN_SHIFT 31
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_0_RR_EN_DEFAULT 0x00000001
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_0_RR_EN_DISABLED 0
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_0_RR_EN_ENABLED 1
-
-/* MEMC_ARB_1 :: CLIENT_INFO_0 :: reserved0 [30:30] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_0_reserved0_MASK 0x40000000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_0_reserved0_SHIFT 30
-
-/* MEMC_ARB_1 :: CLIENT_INFO_0 :: BO_VAL [29:12] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_0_BO_VAL_MASK 0x3ffff000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_0_BO_VAL_SHIFT 12
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_0_BO_VAL_DEFAULT 0x00000000
-
-/* MEMC_ARB_1 :: CLIENT_INFO_0 :: reserved1 [11:08] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_0_reserved1_MASK 0x00000f00
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_0_reserved1_SHIFT 8
-
-/* MEMC_ARB_1 :: CLIENT_INFO_0 :: PR_TAG [07:00] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_0_PR_TAG_MASK 0x000000ff
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_0_PR_TAG_SHIFT 0
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_0_PR_TAG_DEFAULT 0x00000000
-
-/***************************************************************************
- *CLIENT_INFO_1 - Client Programming register for client 1.
- ***************************************************************************/
-/* MEMC_ARB_1 :: CLIENT_INFO_1 :: RR_EN [31:31] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_1_RR_EN_MASK 0x80000000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_1_RR_EN_SHIFT 31
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_1_RR_EN_DEFAULT 0x00000001
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_1_RR_EN_DISABLED 0
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_1_RR_EN_ENABLED 1
-
-/* MEMC_ARB_1 :: CLIENT_INFO_1 :: reserved0 [30:30] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_1_reserved0_MASK 0x40000000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_1_reserved0_SHIFT 30
-
-/* MEMC_ARB_1 :: CLIENT_INFO_1 :: BO_VAL [29:12] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_1_BO_VAL_MASK 0x3ffff000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_1_BO_VAL_SHIFT 12
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_1_BO_VAL_DEFAULT 0x00000000
-
-/* MEMC_ARB_1 :: CLIENT_INFO_1 :: reserved1 [11:08] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_1_reserved1_MASK 0x00000f00
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_1_reserved1_SHIFT 8
-
-/* MEMC_ARB_1 :: CLIENT_INFO_1 :: PR_TAG [07:00] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_1_PR_TAG_MASK 0x000000ff
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_1_PR_TAG_SHIFT 0
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_1_PR_TAG_DEFAULT 0x00000000
-
-/***************************************************************************
- *CLIENT_INFO_2 - Client Programming register for client 2.
- ***************************************************************************/
-/* MEMC_ARB_1 :: CLIENT_INFO_2 :: RR_EN [31:31] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_2_RR_EN_MASK 0x80000000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_2_RR_EN_SHIFT 31
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_2_RR_EN_DEFAULT 0x00000001
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_2_RR_EN_DISABLED 0
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_2_RR_EN_ENABLED 1
-
-/* MEMC_ARB_1 :: CLIENT_INFO_2 :: reserved0 [30:30] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_2_reserved0_MASK 0x40000000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_2_reserved0_SHIFT 30
-
-/* MEMC_ARB_1 :: CLIENT_INFO_2 :: BO_VAL [29:12] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_2_BO_VAL_MASK 0x3ffff000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_2_BO_VAL_SHIFT 12
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_2_BO_VAL_DEFAULT 0x00000000
-
-/* MEMC_ARB_1 :: CLIENT_INFO_2 :: reserved1 [11:08] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_2_reserved1_MASK 0x00000f00
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_2_reserved1_SHIFT 8
-
-/* MEMC_ARB_1 :: CLIENT_INFO_2 :: PR_TAG [07:00] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_2_PR_TAG_MASK 0x000000ff
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_2_PR_TAG_SHIFT 0
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_2_PR_TAG_DEFAULT 0x00000000
-
-/***************************************************************************
- *CLIENT_INFO_3 - Client Programming register for client 3.
- ***************************************************************************/
-/* MEMC_ARB_1 :: CLIENT_INFO_3 :: RR_EN [31:31] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_3_RR_EN_MASK 0x80000000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_3_RR_EN_SHIFT 31
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_3_RR_EN_DEFAULT 0x00000001
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_3_RR_EN_DISABLED 0
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_3_RR_EN_ENABLED 1
-
-/* MEMC_ARB_1 :: CLIENT_INFO_3 :: reserved0 [30:30] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_3_reserved0_MASK 0x40000000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_3_reserved0_SHIFT 30
-
-/* MEMC_ARB_1 :: CLIENT_INFO_3 :: BO_VAL [29:12] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_3_BO_VAL_MASK 0x3ffff000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_3_BO_VAL_SHIFT 12
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_3_BO_VAL_DEFAULT 0x00000000
-
-/* MEMC_ARB_1 :: CLIENT_INFO_3 :: reserved1 [11:08] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_3_reserved1_MASK 0x00000f00
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_3_reserved1_SHIFT 8
-
-/* MEMC_ARB_1 :: CLIENT_INFO_3 :: PR_TAG [07:00] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_3_PR_TAG_MASK 0x000000ff
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_3_PR_TAG_SHIFT 0
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_3_PR_TAG_DEFAULT 0x00000000
-
-/***************************************************************************
- *CLIENT_INFO_4 - Client Programming register for client 4.
- ***************************************************************************/
-/* MEMC_ARB_1 :: CLIENT_INFO_4 :: RR_EN [31:31] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_4_RR_EN_MASK 0x80000000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_4_RR_EN_SHIFT 31
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_4_RR_EN_DEFAULT 0x00000001
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_4_RR_EN_DISABLED 0
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_4_RR_EN_ENABLED 1
-
-/* MEMC_ARB_1 :: CLIENT_INFO_4 :: reserved0 [30:30] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_4_reserved0_MASK 0x40000000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_4_reserved0_SHIFT 30
-
-/* MEMC_ARB_1 :: CLIENT_INFO_4 :: BO_VAL [29:12] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_4_BO_VAL_MASK 0x3ffff000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_4_BO_VAL_SHIFT 12
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_4_BO_VAL_DEFAULT 0x00000000
-
-/* MEMC_ARB_1 :: CLIENT_INFO_4 :: reserved1 [11:08] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_4_reserved1_MASK 0x00000f00
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_4_reserved1_SHIFT 8
-
-/* MEMC_ARB_1 :: CLIENT_INFO_4 :: PR_TAG [07:00] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_4_PR_TAG_MASK 0x000000ff
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_4_PR_TAG_SHIFT 0
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_4_PR_TAG_DEFAULT 0x00000000
-
-/***************************************************************************
- *CLIENT_INFO_5 - Client Programming register for client 5.
- ***************************************************************************/
-/* MEMC_ARB_1 :: CLIENT_INFO_5 :: RR_EN [31:31] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_5_RR_EN_MASK 0x80000000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_5_RR_EN_SHIFT 31
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_5_RR_EN_DEFAULT 0x00000001
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_5_RR_EN_DISABLED 0
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_5_RR_EN_ENABLED 1
-
-/* MEMC_ARB_1 :: CLIENT_INFO_5 :: reserved0 [30:30] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_5_reserved0_MASK 0x40000000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_5_reserved0_SHIFT 30
-
-/* MEMC_ARB_1 :: CLIENT_INFO_5 :: BO_VAL [29:12] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_5_BO_VAL_MASK 0x3ffff000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_5_BO_VAL_SHIFT 12
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_5_BO_VAL_DEFAULT 0x00000000
-
-/* MEMC_ARB_1 :: CLIENT_INFO_5 :: reserved1 [11:08] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_5_reserved1_MASK 0x00000f00
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_5_reserved1_SHIFT 8
-
-/* MEMC_ARB_1 :: CLIENT_INFO_5 :: PR_TAG [07:00] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_5_PR_TAG_MASK 0x000000ff
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_5_PR_TAG_SHIFT 0
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_5_PR_TAG_DEFAULT 0x00000000
-
-/***************************************************************************
- *CLIENT_INFO_6 - Client Programming register for client 6.
- ***************************************************************************/
-/* MEMC_ARB_1 :: CLIENT_INFO_6 :: RR_EN [31:31] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_6_RR_EN_MASK 0x80000000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_6_RR_EN_SHIFT 31
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_6_RR_EN_DEFAULT 0x00000001
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_6_RR_EN_DISABLED 0
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_6_RR_EN_ENABLED 1
-
-/* MEMC_ARB_1 :: CLIENT_INFO_6 :: reserved0 [30:30] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_6_reserved0_MASK 0x40000000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_6_reserved0_SHIFT 30
-
-/* MEMC_ARB_1 :: CLIENT_INFO_6 :: BO_VAL [29:12] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_6_BO_VAL_MASK 0x3ffff000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_6_BO_VAL_SHIFT 12
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_6_BO_VAL_DEFAULT 0x00000000
-
-/* MEMC_ARB_1 :: CLIENT_INFO_6 :: reserved1 [11:08] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_6_reserved1_MASK 0x00000f00
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_6_reserved1_SHIFT 8
-
-/* MEMC_ARB_1 :: CLIENT_INFO_6 :: PR_TAG [07:00] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_6_PR_TAG_MASK 0x000000ff
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_6_PR_TAG_SHIFT 0
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_6_PR_TAG_DEFAULT 0x00000000
-
-/***************************************************************************
- *CLIENT_INFO_7 - Client Programming register for client 7.
- ***************************************************************************/
-/* MEMC_ARB_1 :: CLIENT_INFO_7 :: RR_EN [31:31] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_7_RR_EN_MASK 0x80000000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_7_RR_EN_SHIFT 31
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_7_RR_EN_DEFAULT 0x00000001
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_7_RR_EN_DISABLED 0
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_7_RR_EN_ENABLED 1
-
-/* MEMC_ARB_1 :: CLIENT_INFO_7 :: reserved0 [30:30] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_7_reserved0_MASK 0x40000000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_7_reserved0_SHIFT 30
-
-/* MEMC_ARB_1 :: CLIENT_INFO_7 :: BO_VAL [29:12] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_7_BO_VAL_MASK 0x3ffff000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_7_BO_VAL_SHIFT 12
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_7_BO_VAL_DEFAULT 0x00000000
-
-/* MEMC_ARB_1 :: CLIENT_INFO_7 :: reserved1 [11:08] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_7_reserved1_MASK 0x00000f00
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_7_reserved1_SHIFT 8
-
-/* MEMC_ARB_1 :: CLIENT_INFO_7 :: PR_TAG [07:00] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_7_PR_TAG_MASK 0x000000ff
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_7_PR_TAG_SHIFT 0
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_7_PR_TAG_DEFAULT 0x00000000
-
-/***************************************************************************
- *CLIENT_INFO_8 - Client Programming register for client 8.
- ***************************************************************************/
-/* MEMC_ARB_1 :: CLIENT_INFO_8 :: RR_EN [31:31] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_8_RR_EN_MASK 0x80000000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_8_RR_EN_SHIFT 31
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_8_RR_EN_DEFAULT 0x00000001
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_8_RR_EN_DISABLED 0
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_8_RR_EN_ENABLED 1
-
-/* MEMC_ARB_1 :: CLIENT_INFO_8 :: reserved0 [30:30] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_8_reserved0_MASK 0x40000000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_8_reserved0_SHIFT 30
-
-/* MEMC_ARB_1 :: CLIENT_INFO_8 :: BO_VAL [29:12] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_8_BO_VAL_MASK 0x3ffff000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_8_BO_VAL_SHIFT 12
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_8_BO_VAL_DEFAULT 0x00000000
-
-/* MEMC_ARB_1 :: CLIENT_INFO_8 :: reserved1 [11:08] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_8_reserved1_MASK 0x00000f00
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_8_reserved1_SHIFT 8
-
-/* MEMC_ARB_1 :: CLIENT_INFO_8 :: PR_TAG [07:00] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_8_PR_TAG_MASK 0x000000ff
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_8_PR_TAG_SHIFT 0
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_8_PR_TAG_DEFAULT 0x00000000
-
-/***************************************************************************
- *CLIENT_INFO_9 - Client Programming register for client 9.
- ***************************************************************************/
-/* MEMC_ARB_1 :: CLIENT_INFO_9 :: RR_EN [31:31] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_9_RR_EN_MASK 0x80000000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_9_RR_EN_SHIFT 31
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_9_RR_EN_DEFAULT 0x00000001
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_9_RR_EN_DISABLED 0
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_9_RR_EN_ENABLED 1
-
-/* MEMC_ARB_1 :: CLIENT_INFO_9 :: reserved0 [30:30] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_9_reserved0_MASK 0x40000000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_9_reserved0_SHIFT 30
-
-/* MEMC_ARB_1 :: CLIENT_INFO_9 :: BO_VAL [29:12] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_9_BO_VAL_MASK 0x3ffff000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_9_BO_VAL_SHIFT 12
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_9_BO_VAL_DEFAULT 0x00000000
-
-/* MEMC_ARB_1 :: CLIENT_INFO_9 :: reserved1 [11:08] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_9_reserved1_MASK 0x00000f00
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_9_reserved1_SHIFT 8
-
-/* MEMC_ARB_1 :: CLIENT_INFO_9 :: PR_TAG [07:00] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_9_PR_TAG_MASK 0x000000ff
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_9_PR_TAG_SHIFT 0
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_9_PR_TAG_DEFAULT 0x00000000
-
-/***************************************************************************
- *CLIENT_INFO_10 - Client Programming register for client 10.
- ***************************************************************************/
-/* MEMC_ARB_1 :: CLIENT_INFO_10 :: RR_EN [31:31] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_10_RR_EN_MASK 0x80000000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_10_RR_EN_SHIFT 31
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_10_RR_EN_DEFAULT 0x00000001
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_10_RR_EN_DISABLED 0
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_10_RR_EN_ENABLED 1
-
-/* MEMC_ARB_1 :: CLIENT_INFO_10 :: reserved0 [30:30] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_10_reserved0_MASK 0x40000000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_10_reserved0_SHIFT 30
-
-/* MEMC_ARB_1 :: CLIENT_INFO_10 :: BO_VAL [29:12] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_10_BO_VAL_MASK 0x3ffff000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_10_BO_VAL_SHIFT 12
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_10_BO_VAL_DEFAULT 0x00000000
-
-/* MEMC_ARB_1 :: CLIENT_INFO_10 :: reserved1 [11:08] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_10_reserved1_MASK 0x00000f00
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_10_reserved1_SHIFT 8
-
-/* MEMC_ARB_1 :: CLIENT_INFO_10 :: PR_TAG [07:00] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_10_PR_TAG_MASK 0x000000ff
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_10_PR_TAG_SHIFT 0
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_10_PR_TAG_DEFAULT 0x00000000
-
-/***************************************************************************
- *CLIENT_INFO_11 - Client Programming register for client 11.
- ***************************************************************************/
-/* MEMC_ARB_1 :: CLIENT_INFO_11 :: RR_EN [31:31] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_11_RR_EN_MASK 0x80000000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_11_RR_EN_SHIFT 31
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_11_RR_EN_DEFAULT 0x00000001
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_11_RR_EN_DISABLED 0
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_11_RR_EN_ENABLED 1
-
-/* MEMC_ARB_1 :: CLIENT_INFO_11 :: reserved0 [30:30] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_11_reserved0_MASK 0x40000000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_11_reserved0_SHIFT 30
-
-/* MEMC_ARB_1 :: CLIENT_INFO_11 :: BO_VAL [29:12] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_11_BO_VAL_MASK 0x3ffff000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_11_BO_VAL_SHIFT 12
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_11_BO_VAL_DEFAULT 0x00000000
-
-/* MEMC_ARB_1 :: CLIENT_INFO_11 :: reserved1 [11:08] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_11_reserved1_MASK 0x00000f00
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_11_reserved1_SHIFT 8
-
-/* MEMC_ARB_1 :: CLIENT_INFO_11 :: PR_TAG [07:00] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_11_PR_TAG_MASK 0x000000ff
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_11_PR_TAG_SHIFT 0
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_11_PR_TAG_DEFAULT 0x00000000
-
-/***************************************************************************
- *CLIENT_INFO_12 - Client Programming register for client 12.
- ***************************************************************************/
-/* MEMC_ARB_1 :: CLIENT_INFO_12 :: RR_EN [31:31] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_12_RR_EN_MASK 0x80000000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_12_RR_EN_SHIFT 31
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_12_RR_EN_DEFAULT 0x00000001
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_12_RR_EN_DISABLED 0
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_12_RR_EN_ENABLED 1
-
-/* MEMC_ARB_1 :: CLIENT_INFO_12 :: reserved0 [30:30] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_12_reserved0_MASK 0x40000000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_12_reserved0_SHIFT 30
-
-/* MEMC_ARB_1 :: CLIENT_INFO_12 :: BO_VAL [29:12] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_12_BO_VAL_MASK 0x3ffff000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_12_BO_VAL_SHIFT 12
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_12_BO_VAL_DEFAULT 0x00000000
-
-/* MEMC_ARB_1 :: CLIENT_INFO_12 :: reserved1 [11:08] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_12_reserved1_MASK 0x00000f00
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_12_reserved1_SHIFT 8
-
-/* MEMC_ARB_1 :: CLIENT_INFO_12 :: PR_TAG [07:00] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_12_PR_TAG_MASK 0x000000ff
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_12_PR_TAG_SHIFT 0
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_12_PR_TAG_DEFAULT 0x00000000
-
-/***************************************************************************
- *CLIENT_INFO_13 - Client Programming register for client 13.
- ***************************************************************************/
-/* MEMC_ARB_1 :: CLIENT_INFO_13 :: RR_EN [31:31] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_13_RR_EN_MASK 0x80000000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_13_RR_EN_SHIFT 31
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_13_RR_EN_DEFAULT 0x00000001
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_13_RR_EN_DISABLED 0
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_13_RR_EN_ENABLED 1
-
-/* MEMC_ARB_1 :: CLIENT_INFO_13 :: reserved0 [30:30] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_13_reserved0_MASK 0x40000000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_13_reserved0_SHIFT 30
-
-/* MEMC_ARB_1 :: CLIENT_INFO_13 :: BO_VAL [29:12] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_13_BO_VAL_MASK 0x3ffff000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_13_BO_VAL_SHIFT 12
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_13_BO_VAL_DEFAULT 0x00000000
-
-/* MEMC_ARB_1 :: CLIENT_INFO_13 :: reserved1 [11:08] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_13_reserved1_MASK 0x00000f00
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_13_reserved1_SHIFT 8
-
-/* MEMC_ARB_1 :: CLIENT_INFO_13 :: PR_TAG [07:00] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_13_PR_TAG_MASK 0x000000ff
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_13_PR_TAG_SHIFT 0
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_13_PR_TAG_DEFAULT 0x00000000
-
-/***************************************************************************
- *CLIENT_INFO_14 - Client Programming register for client 14.
- ***************************************************************************/
-/* MEMC_ARB_1 :: CLIENT_INFO_14 :: RR_EN [31:31] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_14_RR_EN_MASK 0x80000000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_14_RR_EN_SHIFT 31
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_14_RR_EN_DEFAULT 0x00000001
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_14_RR_EN_DISABLED 0
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_14_RR_EN_ENABLED 1
-
-/* MEMC_ARB_1 :: CLIENT_INFO_14 :: reserved0 [30:30] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_14_reserved0_MASK 0x40000000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_14_reserved0_SHIFT 30
-
-/* MEMC_ARB_1 :: CLIENT_INFO_14 :: BO_VAL [29:12] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_14_BO_VAL_MASK 0x3ffff000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_14_BO_VAL_SHIFT 12
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_14_BO_VAL_DEFAULT 0x00000000
-
-/* MEMC_ARB_1 :: CLIENT_INFO_14 :: reserved1 [11:08] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_14_reserved1_MASK 0x00000f00
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_14_reserved1_SHIFT 8
-
-/* MEMC_ARB_1 :: CLIENT_INFO_14 :: PR_TAG [07:00] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_14_PR_TAG_MASK 0x000000ff
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_14_PR_TAG_SHIFT 0
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_14_PR_TAG_DEFAULT 0x00000000
-
-/***************************************************************************
- *CLIENT_INFO_15 - Client Programming register for client 15.
- ***************************************************************************/
-/* MEMC_ARB_1 :: CLIENT_INFO_15 :: RR_EN [31:31] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_15_RR_EN_MASK 0x80000000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_15_RR_EN_SHIFT 31
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_15_RR_EN_DEFAULT 0x00000001
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_15_RR_EN_DISABLED 0
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_15_RR_EN_ENABLED 1
-
-/* MEMC_ARB_1 :: CLIENT_INFO_15 :: reserved0 [30:30] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_15_reserved0_MASK 0x40000000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_15_reserved0_SHIFT 30
-
-/* MEMC_ARB_1 :: CLIENT_INFO_15 :: BO_VAL [29:12] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_15_BO_VAL_MASK 0x3ffff000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_15_BO_VAL_SHIFT 12
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_15_BO_VAL_DEFAULT 0x00000000
-
-/* MEMC_ARB_1 :: CLIENT_INFO_15 :: reserved1 [11:08] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_15_reserved1_MASK 0x00000f00
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_15_reserved1_SHIFT 8
-
-/* MEMC_ARB_1 :: CLIENT_INFO_15 :: PR_TAG [07:00] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_15_PR_TAG_MASK 0x000000ff
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_15_PR_TAG_SHIFT 0
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_15_PR_TAG_DEFAULT 0x00000000
-
-/***************************************************************************
- *CLIENT_INFO_16 - Client Programming register for client 16.
- ***************************************************************************/
-/* MEMC_ARB_1 :: CLIENT_INFO_16 :: RR_EN [31:31] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_16_RR_EN_MASK 0x80000000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_16_RR_EN_SHIFT 31
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_16_RR_EN_DEFAULT 0x00000001
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_16_RR_EN_DISABLED 0
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_16_RR_EN_ENABLED 1
-
-/* MEMC_ARB_1 :: CLIENT_INFO_16 :: reserved0 [30:30] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_16_reserved0_MASK 0x40000000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_16_reserved0_SHIFT 30
-
-/* MEMC_ARB_1 :: CLIENT_INFO_16 :: BO_VAL [29:12] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_16_BO_VAL_MASK 0x3ffff000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_16_BO_VAL_SHIFT 12
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_16_BO_VAL_DEFAULT 0x00000000
-
-/* MEMC_ARB_1 :: CLIENT_INFO_16 :: reserved1 [11:08] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_16_reserved1_MASK 0x00000f00
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_16_reserved1_SHIFT 8
-
-/* MEMC_ARB_1 :: CLIENT_INFO_16 :: PR_TAG [07:00] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_16_PR_TAG_MASK 0x000000ff
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_16_PR_TAG_SHIFT 0
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_16_PR_TAG_DEFAULT 0x00000000
-
-/***************************************************************************
- *CLIENT_INFO_17 - Client Programming register for client 17.
- ***************************************************************************/
-/* MEMC_ARB_1 :: CLIENT_INFO_17 :: RR_EN [31:31] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_17_RR_EN_MASK 0x80000000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_17_RR_EN_SHIFT 31
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_17_RR_EN_DEFAULT 0x00000001
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_17_RR_EN_DISABLED 0
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_17_RR_EN_ENABLED 1
-
-/* MEMC_ARB_1 :: CLIENT_INFO_17 :: reserved0 [30:30] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_17_reserved0_MASK 0x40000000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_17_reserved0_SHIFT 30
-
-/* MEMC_ARB_1 :: CLIENT_INFO_17 :: BO_VAL [29:12] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_17_BO_VAL_MASK 0x3ffff000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_17_BO_VAL_SHIFT 12
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_17_BO_VAL_DEFAULT 0x00000000
-
-/* MEMC_ARB_1 :: CLIENT_INFO_17 :: reserved1 [11:08] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_17_reserved1_MASK 0x00000f00
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_17_reserved1_SHIFT 8
-
-/* MEMC_ARB_1 :: CLIENT_INFO_17 :: PR_TAG [07:00] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_17_PR_TAG_MASK 0x000000ff
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_17_PR_TAG_SHIFT 0
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_17_PR_TAG_DEFAULT 0x00000000
-
-/***************************************************************************
- *CLIENT_INFO_18 - Client Programming register for client 18.
- ***************************************************************************/
-/* MEMC_ARB_1 :: CLIENT_INFO_18 :: RR_EN [31:31] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_18_RR_EN_MASK 0x80000000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_18_RR_EN_SHIFT 31
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_18_RR_EN_DEFAULT 0x00000001
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_18_RR_EN_DISABLED 0
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_18_RR_EN_ENABLED 1
-
-/* MEMC_ARB_1 :: CLIENT_INFO_18 :: reserved0 [30:30] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_18_reserved0_MASK 0x40000000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_18_reserved0_SHIFT 30
-
-/* MEMC_ARB_1 :: CLIENT_INFO_18 :: BO_VAL [29:12] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_18_BO_VAL_MASK 0x3ffff000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_18_BO_VAL_SHIFT 12
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_18_BO_VAL_DEFAULT 0x00000000
-
-/* MEMC_ARB_1 :: CLIENT_INFO_18 :: reserved1 [11:08] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_18_reserved1_MASK 0x00000f00
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_18_reserved1_SHIFT 8
-
-/* MEMC_ARB_1 :: CLIENT_INFO_18 :: PR_TAG [07:00] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_18_PR_TAG_MASK 0x000000ff
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_18_PR_TAG_SHIFT 0
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_18_PR_TAG_DEFAULT 0x00000000
-
-/***************************************************************************
- *CLIENT_INFO_19 - Client Programming register for client 19.
- ***************************************************************************/
-/* MEMC_ARB_1 :: CLIENT_INFO_19 :: RR_EN [31:31] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_19_RR_EN_MASK 0x80000000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_19_RR_EN_SHIFT 31
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_19_RR_EN_DEFAULT 0x00000001
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_19_RR_EN_DISABLED 0
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_19_RR_EN_ENABLED 1
-
-/* MEMC_ARB_1 :: CLIENT_INFO_19 :: reserved0 [30:30] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_19_reserved0_MASK 0x40000000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_19_reserved0_SHIFT 30
-
-/* MEMC_ARB_1 :: CLIENT_INFO_19 :: BO_VAL [29:12] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_19_BO_VAL_MASK 0x3ffff000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_19_BO_VAL_SHIFT 12
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_19_BO_VAL_DEFAULT 0x00000000
-
-/* MEMC_ARB_1 :: CLIENT_INFO_19 :: reserved1 [11:08] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_19_reserved1_MASK 0x00000f00
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_19_reserved1_SHIFT 8
-
-/* MEMC_ARB_1 :: CLIENT_INFO_19 :: PR_TAG [07:00] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_19_PR_TAG_MASK 0x000000ff
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_19_PR_TAG_SHIFT 0
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_19_PR_TAG_DEFAULT 0x00000000
-
-/***************************************************************************
- *CLIENT_INFO_20 - Client Programming register for client 20.
- ***************************************************************************/
-/* MEMC_ARB_1 :: CLIENT_INFO_20 :: RR_EN [31:31] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_20_RR_EN_MASK 0x80000000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_20_RR_EN_SHIFT 31
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_20_RR_EN_DEFAULT 0x00000001
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_20_RR_EN_DISABLED 0
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_20_RR_EN_ENABLED 1
-
-/* MEMC_ARB_1 :: CLIENT_INFO_20 :: reserved0 [30:30] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_20_reserved0_MASK 0x40000000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_20_reserved0_SHIFT 30
-
-/* MEMC_ARB_1 :: CLIENT_INFO_20 :: BO_VAL [29:12] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_20_BO_VAL_MASK 0x3ffff000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_20_BO_VAL_SHIFT 12
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_20_BO_VAL_DEFAULT 0x00000000
-
-/* MEMC_ARB_1 :: CLIENT_INFO_20 :: reserved1 [11:08] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_20_reserved1_MASK 0x00000f00
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_20_reserved1_SHIFT 8
-
-/* MEMC_ARB_1 :: CLIENT_INFO_20 :: PR_TAG [07:00] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_20_PR_TAG_MASK 0x000000ff
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_20_PR_TAG_SHIFT 0
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_20_PR_TAG_DEFAULT 0x00000000
-
-/***************************************************************************
- *CLIENT_INFO_21 - Client Programming register for client 21.
- ***************************************************************************/
-/* MEMC_ARB_1 :: CLIENT_INFO_21 :: RR_EN [31:31] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_21_RR_EN_MASK 0x80000000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_21_RR_EN_SHIFT 31
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_21_RR_EN_DEFAULT 0x00000001
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_21_RR_EN_DISABLED 0
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_21_RR_EN_ENABLED 1
-
-/* MEMC_ARB_1 :: CLIENT_INFO_21 :: reserved0 [30:30] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_21_reserved0_MASK 0x40000000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_21_reserved0_SHIFT 30
-
-/* MEMC_ARB_1 :: CLIENT_INFO_21 :: BO_VAL [29:12] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_21_BO_VAL_MASK 0x3ffff000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_21_BO_VAL_SHIFT 12
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_21_BO_VAL_DEFAULT 0x00000000
-
-/* MEMC_ARB_1 :: CLIENT_INFO_21 :: reserved1 [11:08] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_21_reserved1_MASK 0x00000f00
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_21_reserved1_SHIFT 8
-
-/* MEMC_ARB_1 :: CLIENT_INFO_21 :: PR_TAG [07:00] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_21_PR_TAG_MASK 0x000000ff
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_21_PR_TAG_SHIFT 0
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_21_PR_TAG_DEFAULT 0x00000000
-
-/***************************************************************************
- *CLIENT_INFO_22 - Client Programming register for client 22.
- ***************************************************************************/
-/* MEMC_ARB_1 :: CLIENT_INFO_22 :: RR_EN [31:31] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_22_RR_EN_MASK 0x80000000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_22_RR_EN_SHIFT 31
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_22_RR_EN_DEFAULT 0x00000001
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_22_RR_EN_DISABLED 0
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_22_RR_EN_ENABLED 1
-
-/* MEMC_ARB_1 :: CLIENT_INFO_22 :: reserved0 [30:30] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_22_reserved0_MASK 0x40000000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_22_reserved0_SHIFT 30
-
-/* MEMC_ARB_1 :: CLIENT_INFO_22 :: BO_VAL [29:12] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_22_BO_VAL_MASK 0x3ffff000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_22_BO_VAL_SHIFT 12
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_22_BO_VAL_DEFAULT 0x00000000
-
-/* MEMC_ARB_1 :: CLIENT_INFO_22 :: reserved1 [11:08] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_22_reserved1_MASK 0x00000f00
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_22_reserved1_SHIFT 8
-
-/* MEMC_ARB_1 :: CLIENT_INFO_22 :: PR_TAG [07:00] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_22_PR_TAG_MASK 0x000000ff
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_22_PR_TAG_SHIFT 0
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_22_PR_TAG_DEFAULT 0x00000000
-
-/***************************************************************************
- *CLIENT_INFO_23 - Client Programming register for client 23.
- ***************************************************************************/
-/* MEMC_ARB_1 :: CLIENT_INFO_23 :: RR_EN [31:31] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_23_RR_EN_MASK 0x80000000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_23_RR_EN_SHIFT 31
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_23_RR_EN_DEFAULT 0x00000001
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_23_RR_EN_DISABLED 0
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_23_RR_EN_ENABLED 1
-
-/* MEMC_ARB_1 :: CLIENT_INFO_23 :: reserved0 [30:30] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_23_reserved0_MASK 0x40000000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_23_reserved0_SHIFT 30
-
-/* MEMC_ARB_1 :: CLIENT_INFO_23 :: BO_VAL [29:12] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_23_BO_VAL_MASK 0x3ffff000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_23_BO_VAL_SHIFT 12
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_23_BO_VAL_DEFAULT 0x00000000
-
-/* MEMC_ARB_1 :: CLIENT_INFO_23 :: reserved1 [11:08] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_23_reserved1_MASK 0x00000f00
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_23_reserved1_SHIFT 8
-
-/* MEMC_ARB_1 :: CLIENT_INFO_23 :: PR_TAG [07:00] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_23_PR_TAG_MASK 0x000000ff
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_23_PR_TAG_SHIFT 0
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_23_PR_TAG_DEFAULT 0x00000000
-
-/***************************************************************************
- *CLIENT_INFO_24 - Client Programming register for client 24.
- ***************************************************************************/
-/* MEMC_ARB_1 :: CLIENT_INFO_24 :: RR_EN [31:31] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_24_RR_EN_MASK 0x80000000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_24_RR_EN_SHIFT 31
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_24_RR_EN_DEFAULT 0x00000001
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_24_RR_EN_DISABLED 0
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_24_RR_EN_ENABLED 1
-
-/* MEMC_ARB_1 :: CLIENT_INFO_24 :: reserved0 [30:30] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_24_reserved0_MASK 0x40000000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_24_reserved0_SHIFT 30
-
-/* MEMC_ARB_1 :: CLIENT_INFO_24 :: BO_VAL [29:12] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_24_BO_VAL_MASK 0x3ffff000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_24_BO_VAL_SHIFT 12
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_24_BO_VAL_DEFAULT 0x00000000
-
-/* MEMC_ARB_1 :: CLIENT_INFO_24 :: reserved1 [11:08] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_24_reserved1_MASK 0x00000f00
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_24_reserved1_SHIFT 8
-
-/* MEMC_ARB_1 :: CLIENT_INFO_24 :: PR_TAG [07:00] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_24_PR_TAG_MASK 0x000000ff
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_24_PR_TAG_SHIFT 0
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_24_PR_TAG_DEFAULT 0x00000000
-
-/***************************************************************************
- *CLIENT_INFO_25 - Client Programming register for client 25.
- ***************************************************************************/
-/* MEMC_ARB_1 :: CLIENT_INFO_25 :: RR_EN [31:31] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_25_RR_EN_MASK 0x80000000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_25_RR_EN_SHIFT 31
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_25_RR_EN_DEFAULT 0x00000001
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_25_RR_EN_DISABLED 0
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_25_RR_EN_ENABLED 1
-
-/* MEMC_ARB_1 :: CLIENT_INFO_25 :: reserved0 [30:30] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_25_reserved0_MASK 0x40000000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_25_reserved0_SHIFT 30
-
-/* MEMC_ARB_1 :: CLIENT_INFO_25 :: BO_VAL [29:12] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_25_BO_VAL_MASK 0x3ffff000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_25_BO_VAL_SHIFT 12
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_25_BO_VAL_DEFAULT 0x00000000
-
-/* MEMC_ARB_1 :: CLIENT_INFO_25 :: reserved1 [11:08] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_25_reserved1_MASK 0x00000f00
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_25_reserved1_SHIFT 8
-
-/* MEMC_ARB_1 :: CLIENT_INFO_25 :: PR_TAG [07:00] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_25_PR_TAG_MASK 0x000000ff
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_25_PR_TAG_SHIFT 0
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_25_PR_TAG_DEFAULT 0x00000000
-
-/***************************************************************************
- *CLIENT_INFO_26 - Client Programming register for client 26.
- ***************************************************************************/
-/* MEMC_ARB_1 :: CLIENT_INFO_26 :: RR_EN [31:31] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_26_RR_EN_MASK 0x80000000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_26_RR_EN_SHIFT 31
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_26_RR_EN_DEFAULT 0x00000001
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_26_RR_EN_DISABLED 0
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_26_RR_EN_ENABLED 1
-
-/* MEMC_ARB_1 :: CLIENT_INFO_26 :: reserved0 [30:30] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_26_reserved0_MASK 0x40000000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_26_reserved0_SHIFT 30
-
-/* MEMC_ARB_1 :: CLIENT_INFO_26 :: BO_VAL [29:12] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_26_BO_VAL_MASK 0x3ffff000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_26_BO_VAL_SHIFT 12
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_26_BO_VAL_DEFAULT 0x00000000
-
-/* MEMC_ARB_1 :: CLIENT_INFO_26 :: reserved1 [11:08] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_26_reserved1_MASK 0x00000f00
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_26_reserved1_SHIFT 8
-
-/* MEMC_ARB_1 :: CLIENT_INFO_26 :: PR_TAG [07:00] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_26_PR_TAG_MASK 0x000000ff
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_26_PR_TAG_SHIFT 0
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_26_PR_TAG_DEFAULT 0x00000000
-
-/***************************************************************************
- *CLIENT_INFO_27 - Client Programming register for client 27.
- ***************************************************************************/
-/* MEMC_ARB_1 :: CLIENT_INFO_27 :: RR_EN [31:31] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_27_RR_EN_MASK 0x80000000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_27_RR_EN_SHIFT 31
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_27_RR_EN_DEFAULT 0x00000001
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_27_RR_EN_DISABLED 0
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_27_RR_EN_ENABLED 1
-
-/* MEMC_ARB_1 :: CLIENT_INFO_27 :: reserved0 [30:30] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_27_reserved0_MASK 0x40000000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_27_reserved0_SHIFT 30
-
-/* MEMC_ARB_1 :: CLIENT_INFO_27 :: BO_VAL [29:12] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_27_BO_VAL_MASK 0x3ffff000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_27_BO_VAL_SHIFT 12
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_27_BO_VAL_DEFAULT 0x00000000
-
-/* MEMC_ARB_1 :: CLIENT_INFO_27 :: reserved1 [11:08] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_27_reserved1_MASK 0x00000f00
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_27_reserved1_SHIFT 8
-
-/* MEMC_ARB_1 :: CLIENT_INFO_27 :: PR_TAG [07:00] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_27_PR_TAG_MASK 0x000000ff
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_27_PR_TAG_SHIFT 0
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_27_PR_TAG_DEFAULT 0x00000000
-
-/***************************************************************************
- *CLIENT_INFO_28 - Client Programming register for client 28.
- ***************************************************************************/
-/* MEMC_ARB_1 :: CLIENT_INFO_28 :: RR_EN [31:31] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_28_RR_EN_MASK 0x80000000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_28_RR_EN_SHIFT 31
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_28_RR_EN_DEFAULT 0x00000001
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_28_RR_EN_DISABLED 0
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_28_RR_EN_ENABLED 1
-
-/* MEMC_ARB_1 :: CLIENT_INFO_28 :: reserved0 [30:30] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_28_reserved0_MASK 0x40000000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_28_reserved0_SHIFT 30
-
-/* MEMC_ARB_1 :: CLIENT_INFO_28 :: BO_VAL [29:12] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_28_BO_VAL_MASK 0x3ffff000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_28_BO_VAL_SHIFT 12
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_28_BO_VAL_DEFAULT 0x00000000
-
-/* MEMC_ARB_1 :: CLIENT_INFO_28 :: reserved1 [11:08] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_28_reserved1_MASK 0x00000f00
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_28_reserved1_SHIFT 8
-
-/* MEMC_ARB_1 :: CLIENT_INFO_28 :: PR_TAG [07:00] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_28_PR_TAG_MASK 0x000000ff
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_28_PR_TAG_SHIFT 0
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_28_PR_TAG_DEFAULT 0x00000000
-
-/***************************************************************************
- *CLIENT_INFO_29 - Client Programming register for client 29.
- ***************************************************************************/
-/* MEMC_ARB_1 :: CLIENT_INFO_29 :: RR_EN [31:31] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_29_RR_EN_MASK 0x80000000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_29_RR_EN_SHIFT 31
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_29_RR_EN_DEFAULT 0x00000001
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_29_RR_EN_DISABLED 0
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_29_RR_EN_ENABLED 1
-
-/* MEMC_ARB_1 :: CLIENT_INFO_29 :: reserved0 [30:30] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_29_reserved0_MASK 0x40000000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_29_reserved0_SHIFT 30
-
-/* MEMC_ARB_1 :: CLIENT_INFO_29 :: BO_VAL [29:12] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_29_BO_VAL_MASK 0x3ffff000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_29_BO_VAL_SHIFT 12
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_29_BO_VAL_DEFAULT 0x00000000
-
-/* MEMC_ARB_1 :: CLIENT_INFO_29 :: reserved1 [11:08] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_29_reserved1_MASK 0x00000f00
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_29_reserved1_SHIFT 8
-
-/* MEMC_ARB_1 :: CLIENT_INFO_29 :: PR_TAG [07:00] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_29_PR_TAG_MASK 0x000000ff
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_29_PR_TAG_SHIFT 0
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_29_PR_TAG_DEFAULT 0x00000000
-
-/***************************************************************************
- *CLIENT_INFO_30 - Client Programming register for client 30.
- ***************************************************************************/
-/* MEMC_ARB_1 :: CLIENT_INFO_30 :: RR_EN [31:31] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_30_RR_EN_MASK 0x80000000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_30_RR_EN_SHIFT 31
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_30_RR_EN_DEFAULT 0x00000001
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_30_RR_EN_DISABLED 0
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_30_RR_EN_ENABLED 1
-
-/* MEMC_ARB_1 :: CLIENT_INFO_30 :: reserved0 [30:30] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_30_reserved0_MASK 0x40000000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_30_reserved0_SHIFT 30
-
-/* MEMC_ARB_1 :: CLIENT_INFO_30 :: BO_VAL [29:12] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_30_BO_VAL_MASK 0x3ffff000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_30_BO_VAL_SHIFT 12
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_30_BO_VAL_DEFAULT 0x00000000
-
-/* MEMC_ARB_1 :: CLIENT_INFO_30 :: reserved1 [11:08] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_30_reserved1_MASK 0x00000f00
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_30_reserved1_SHIFT 8
-
-/* MEMC_ARB_1 :: CLIENT_INFO_30 :: PR_TAG [07:00] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_30_PR_TAG_MASK 0x000000ff
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_30_PR_TAG_SHIFT 0
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_30_PR_TAG_DEFAULT 0x00000000
-
-/***************************************************************************
- *CLIENT_INFO_31 - Client Programming register for client 31.
- ***************************************************************************/
-/* MEMC_ARB_1 :: CLIENT_INFO_31 :: RR_EN [31:31] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_31_RR_EN_MASK 0x80000000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_31_RR_EN_SHIFT 31
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_31_RR_EN_DEFAULT 0x00000001
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_31_RR_EN_DISABLED 0
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_31_RR_EN_ENABLED 1
-
-/* MEMC_ARB_1 :: CLIENT_INFO_31 :: reserved0 [30:30] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_31_reserved0_MASK 0x40000000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_31_reserved0_SHIFT 30
-
-/* MEMC_ARB_1 :: CLIENT_INFO_31 :: BO_VAL [29:12] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_31_BO_VAL_MASK 0x3ffff000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_31_BO_VAL_SHIFT 12
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_31_BO_VAL_DEFAULT 0x00000000
-
-/* MEMC_ARB_1 :: CLIENT_INFO_31 :: reserved1 [11:08] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_31_reserved1_MASK 0x00000f00
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_31_reserved1_SHIFT 8
-
-/* MEMC_ARB_1 :: CLIENT_INFO_31 :: PR_TAG [07:00] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_31_PR_TAG_MASK 0x000000ff
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_31_PR_TAG_SHIFT 0
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_31_PR_TAG_DEFAULT 0x00000000
-
-/***************************************************************************
- *CLIENT_INFO_32 - Client Programming register for client 32.
- ***************************************************************************/
-/* MEMC_ARB_1 :: CLIENT_INFO_32 :: RR_EN [31:31] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_32_RR_EN_MASK 0x80000000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_32_RR_EN_SHIFT 31
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_32_RR_EN_DEFAULT 0x00000001
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_32_RR_EN_DISABLED 0
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_32_RR_EN_ENABLED 1
-
-/* MEMC_ARB_1 :: CLIENT_INFO_32 :: reserved0 [30:30] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_32_reserved0_MASK 0x40000000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_32_reserved0_SHIFT 30
-
-/* MEMC_ARB_1 :: CLIENT_INFO_32 :: BO_VAL [29:12] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_32_BO_VAL_MASK 0x3ffff000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_32_BO_VAL_SHIFT 12
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_32_BO_VAL_DEFAULT 0x00000000
-
-/* MEMC_ARB_1 :: CLIENT_INFO_32 :: reserved1 [11:08] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_32_reserved1_MASK 0x00000f00
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_32_reserved1_SHIFT 8
-
-/* MEMC_ARB_1 :: CLIENT_INFO_32 :: PR_TAG [07:00] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_32_PR_TAG_MASK 0x000000ff
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_32_PR_TAG_SHIFT 0
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_32_PR_TAG_DEFAULT 0x00000000
-
-/***************************************************************************
- *CLIENT_INFO_33 - Client Programming register for client 33.
- ***************************************************************************/
-/* MEMC_ARB_1 :: CLIENT_INFO_33 :: RR_EN [31:31] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_33_RR_EN_MASK 0x80000000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_33_RR_EN_SHIFT 31
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_33_RR_EN_DEFAULT 0x00000001
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_33_RR_EN_DISABLED 0
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_33_RR_EN_ENABLED 1
-
-/* MEMC_ARB_1 :: CLIENT_INFO_33 :: reserved0 [30:30] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_33_reserved0_MASK 0x40000000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_33_reserved0_SHIFT 30
-
-/* MEMC_ARB_1 :: CLIENT_INFO_33 :: BO_VAL [29:12] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_33_BO_VAL_MASK 0x3ffff000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_33_BO_VAL_SHIFT 12
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_33_BO_VAL_DEFAULT 0x00000000
-
-/* MEMC_ARB_1 :: CLIENT_INFO_33 :: reserved1 [11:08] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_33_reserved1_MASK 0x00000f00
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_33_reserved1_SHIFT 8
-
-/* MEMC_ARB_1 :: CLIENT_INFO_33 :: PR_TAG [07:00] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_33_PR_TAG_MASK 0x000000ff
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_33_PR_TAG_SHIFT 0
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_33_PR_TAG_DEFAULT 0x00000000
-
-/***************************************************************************
- *CLIENT_INFO_34 - Client Programming register for client 34.
- ***************************************************************************/
-/* MEMC_ARB_1 :: CLIENT_INFO_34 :: RR_EN [31:31] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_34_RR_EN_MASK 0x80000000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_34_RR_EN_SHIFT 31
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_34_RR_EN_DEFAULT 0x00000001
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_34_RR_EN_DISABLED 0
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_34_RR_EN_ENABLED 1
-
-/* MEMC_ARB_1 :: CLIENT_INFO_34 :: reserved0 [30:30] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_34_reserved0_MASK 0x40000000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_34_reserved0_SHIFT 30
-
-/* MEMC_ARB_1 :: CLIENT_INFO_34 :: BO_VAL [29:12] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_34_BO_VAL_MASK 0x3ffff000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_34_BO_VAL_SHIFT 12
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_34_BO_VAL_DEFAULT 0x00000000
-
-/* MEMC_ARB_1 :: CLIENT_INFO_34 :: reserved1 [11:08] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_34_reserved1_MASK 0x00000f00
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_34_reserved1_SHIFT 8
-
-/* MEMC_ARB_1 :: CLIENT_INFO_34 :: PR_TAG [07:00] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_34_PR_TAG_MASK 0x000000ff
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_34_PR_TAG_SHIFT 0
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_34_PR_TAG_DEFAULT 0x00000000
-
-/***************************************************************************
- *CLIENT_INFO_35 - Client Programming register for client 35.
- ***************************************************************************/
-/* MEMC_ARB_1 :: CLIENT_INFO_35 :: RR_EN [31:31] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_35_RR_EN_MASK 0x80000000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_35_RR_EN_SHIFT 31
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_35_RR_EN_DEFAULT 0x00000001
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_35_RR_EN_DISABLED 0
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_35_RR_EN_ENABLED 1
-
-/* MEMC_ARB_1 :: CLIENT_INFO_35 :: reserved0 [30:30] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_35_reserved0_MASK 0x40000000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_35_reserved0_SHIFT 30
-
-/* MEMC_ARB_1 :: CLIENT_INFO_35 :: BO_VAL [29:12] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_35_BO_VAL_MASK 0x3ffff000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_35_BO_VAL_SHIFT 12
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_35_BO_VAL_DEFAULT 0x00000000
-
-/* MEMC_ARB_1 :: CLIENT_INFO_35 :: reserved1 [11:08] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_35_reserved1_MASK 0x00000f00
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_35_reserved1_SHIFT 8
-
-/* MEMC_ARB_1 :: CLIENT_INFO_35 :: PR_TAG [07:00] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_35_PR_TAG_MASK 0x000000ff
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_35_PR_TAG_SHIFT 0
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_35_PR_TAG_DEFAULT 0x00000000
-
-/***************************************************************************
- *CLIENT_INFO_36 - Client Programming register for client 36.
- ***************************************************************************/
-/* MEMC_ARB_1 :: CLIENT_INFO_36 :: RR_EN [31:31] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_36_RR_EN_MASK 0x80000000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_36_RR_EN_SHIFT 31
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_36_RR_EN_DEFAULT 0x00000001
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_36_RR_EN_DISABLED 0
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_36_RR_EN_ENABLED 1
-
-/* MEMC_ARB_1 :: CLIENT_INFO_36 :: reserved0 [30:30] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_36_reserved0_MASK 0x40000000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_36_reserved0_SHIFT 30
-
-/* MEMC_ARB_1 :: CLIENT_INFO_36 :: BO_VAL [29:12] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_36_BO_VAL_MASK 0x3ffff000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_36_BO_VAL_SHIFT 12
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_36_BO_VAL_DEFAULT 0x00000000
-
-/* MEMC_ARB_1 :: CLIENT_INFO_36 :: reserved1 [11:08] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_36_reserved1_MASK 0x00000f00
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_36_reserved1_SHIFT 8
-
-/* MEMC_ARB_1 :: CLIENT_INFO_36 :: PR_TAG [07:00] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_36_PR_TAG_MASK 0x000000ff
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_36_PR_TAG_SHIFT 0
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_36_PR_TAG_DEFAULT 0x00000000
-
-/***************************************************************************
- *CLIENT_INFO_37 - Client Programming register for client 37.
- ***************************************************************************/
-/* MEMC_ARB_1 :: CLIENT_INFO_37 :: RR_EN [31:31] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_37_RR_EN_MASK 0x80000000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_37_RR_EN_SHIFT 31
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_37_RR_EN_DEFAULT 0x00000001
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_37_RR_EN_DISABLED 0
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_37_RR_EN_ENABLED 1
-
-/* MEMC_ARB_1 :: CLIENT_INFO_37 :: reserved0 [30:30] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_37_reserved0_MASK 0x40000000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_37_reserved0_SHIFT 30
-
-/* MEMC_ARB_1 :: CLIENT_INFO_37 :: BO_VAL [29:12] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_37_BO_VAL_MASK 0x3ffff000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_37_BO_VAL_SHIFT 12
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_37_BO_VAL_DEFAULT 0x00000000
-
-/* MEMC_ARB_1 :: CLIENT_INFO_37 :: reserved1 [11:08] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_37_reserved1_MASK 0x00000f00
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_37_reserved1_SHIFT 8
-
-/* MEMC_ARB_1 :: CLIENT_INFO_37 :: PR_TAG [07:00] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_37_PR_TAG_MASK 0x000000ff
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_37_PR_TAG_SHIFT 0
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_37_PR_TAG_DEFAULT 0x00000000
-
-/***************************************************************************
- *CLIENT_INFO_38 - Client Programming register for client 38.
- ***************************************************************************/
-/* MEMC_ARB_1 :: CLIENT_INFO_38 :: RR_EN [31:31] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_38_RR_EN_MASK 0x80000000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_38_RR_EN_SHIFT 31
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_38_RR_EN_DEFAULT 0x00000001
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_38_RR_EN_DISABLED 0
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_38_RR_EN_ENABLED 1
-
-/* MEMC_ARB_1 :: CLIENT_INFO_38 :: reserved0 [30:30] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_38_reserved0_MASK 0x40000000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_38_reserved0_SHIFT 30
-
-/* MEMC_ARB_1 :: CLIENT_INFO_38 :: BO_VAL [29:12] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_38_BO_VAL_MASK 0x3ffff000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_38_BO_VAL_SHIFT 12
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_38_BO_VAL_DEFAULT 0x00000000
-
-/* MEMC_ARB_1 :: CLIENT_INFO_38 :: reserved1 [11:08] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_38_reserved1_MASK 0x00000f00
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_38_reserved1_SHIFT 8
-
-/* MEMC_ARB_1 :: CLIENT_INFO_38 :: PR_TAG [07:00] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_38_PR_TAG_MASK 0x000000ff
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_38_PR_TAG_SHIFT 0
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_38_PR_TAG_DEFAULT 0x00000000
-
-/***************************************************************************
- *CLIENT_INFO_39 - Client Programming register for client 39.
- ***************************************************************************/
-/* MEMC_ARB_1 :: CLIENT_INFO_39 :: RR_EN [31:31] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_39_RR_EN_MASK 0x80000000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_39_RR_EN_SHIFT 31
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_39_RR_EN_DEFAULT 0x00000001
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_39_RR_EN_DISABLED 0
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_39_RR_EN_ENABLED 1
-
-/* MEMC_ARB_1 :: CLIENT_INFO_39 :: reserved0 [30:30] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_39_reserved0_MASK 0x40000000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_39_reserved0_SHIFT 30
-
-/* MEMC_ARB_1 :: CLIENT_INFO_39 :: BO_VAL [29:12] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_39_BO_VAL_MASK 0x3ffff000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_39_BO_VAL_SHIFT 12
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_39_BO_VAL_DEFAULT 0x00000000
-
-/* MEMC_ARB_1 :: CLIENT_INFO_39 :: reserved1 [11:08] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_39_reserved1_MASK 0x00000f00
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_39_reserved1_SHIFT 8
-
-/* MEMC_ARB_1 :: CLIENT_INFO_39 :: PR_TAG [07:00] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_39_PR_TAG_MASK 0x000000ff
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_39_PR_TAG_SHIFT 0
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_39_PR_TAG_DEFAULT 0x00000000
-
-/***************************************************************************
- *CLIENT_INFO_40 - Client Programming register for client 40.
- ***************************************************************************/
-/* MEMC_ARB_1 :: CLIENT_INFO_40 :: RR_EN [31:31] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_40_RR_EN_MASK 0x80000000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_40_RR_EN_SHIFT 31
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_40_RR_EN_DEFAULT 0x00000001
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_40_RR_EN_DISABLED 0
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_40_RR_EN_ENABLED 1
-
-/* MEMC_ARB_1 :: CLIENT_INFO_40 :: reserved0 [30:30] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_40_reserved0_MASK 0x40000000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_40_reserved0_SHIFT 30
-
-/* MEMC_ARB_1 :: CLIENT_INFO_40 :: BO_VAL [29:12] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_40_BO_VAL_MASK 0x3ffff000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_40_BO_VAL_SHIFT 12
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_40_BO_VAL_DEFAULT 0x00000000
-
-/* MEMC_ARB_1 :: CLIENT_INFO_40 :: reserved1 [11:08] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_40_reserved1_MASK 0x00000f00
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_40_reserved1_SHIFT 8
-
-/* MEMC_ARB_1 :: CLIENT_INFO_40 :: PR_TAG [07:00] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_40_PR_TAG_MASK 0x000000ff
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_40_PR_TAG_SHIFT 0
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_40_PR_TAG_DEFAULT 0x00000000
-
-/***************************************************************************
- *CLIENT_INFO_41 - Client Programming register for client 41.
- ***************************************************************************/
-/* MEMC_ARB_1 :: CLIENT_INFO_41 :: RR_EN [31:31] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_41_RR_EN_MASK 0x80000000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_41_RR_EN_SHIFT 31
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_41_RR_EN_DEFAULT 0x00000001
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_41_RR_EN_DISABLED 0
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_41_RR_EN_ENABLED 1
-
-/* MEMC_ARB_1 :: CLIENT_INFO_41 :: reserved0 [30:30] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_41_reserved0_MASK 0x40000000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_41_reserved0_SHIFT 30
-
-/* MEMC_ARB_1 :: CLIENT_INFO_41 :: BO_VAL [29:12] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_41_BO_VAL_MASK 0x3ffff000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_41_BO_VAL_SHIFT 12
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_41_BO_VAL_DEFAULT 0x00000000
-
-/* MEMC_ARB_1 :: CLIENT_INFO_41 :: reserved1 [11:08] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_41_reserved1_MASK 0x00000f00
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_41_reserved1_SHIFT 8
-
-/* MEMC_ARB_1 :: CLIENT_INFO_41 :: PR_TAG [07:00] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_41_PR_TAG_MASK 0x000000ff
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_41_PR_TAG_SHIFT 0
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_41_PR_TAG_DEFAULT 0x00000000
-
-/***************************************************************************
- *CLIENT_INFO_42 - Client Programming register for client 42.
- ***************************************************************************/
-/* MEMC_ARB_1 :: CLIENT_INFO_42 :: RR_EN [31:31] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_42_RR_EN_MASK 0x80000000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_42_RR_EN_SHIFT 31
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_42_RR_EN_DEFAULT 0x00000001
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_42_RR_EN_DISABLED 0
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_42_RR_EN_ENABLED 1
-
-/* MEMC_ARB_1 :: CLIENT_INFO_42 :: reserved0 [30:30] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_42_reserved0_MASK 0x40000000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_42_reserved0_SHIFT 30
-
-/* MEMC_ARB_1 :: CLIENT_INFO_42 :: BO_VAL [29:12] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_42_BO_VAL_MASK 0x3ffff000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_42_BO_VAL_SHIFT 12
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_42_BO_VAL_DEFAULT 0x00000000
-
-/* MEMC_ARB_1 :: CLIENT_INFO_42 :: reserved1 [11:08] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_42_reserved1_MASK 0x00000f00
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_42_reserved1_SHIFT 8
-
-/* MEMC_ARB_1 :: CLIENT_INFO_42 :: PR_TAG [07:00] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_42_PR_TAG_MASK 0x000000ff
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_42_PR_TAG_SHIFT 0
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_42_PR_TAG_DEFAULT 0x00000000
-
-/***************************************************************************
- *CLIENT_INFO_43 - Client Programming register for client 43.
- ***************************************************************************/
-/* MEMC_ARB_1 :: CLIENT_INFO_43 :: RR_EN [31:31] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_43_RR_EN_MASK 0x80000000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_43_RR_EN_SHIFT 31
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_43_RR_EN_DEFAULT 0x00000001
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_43_RR_EN_DISABLED 0
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_43_RR_EN_ENABLED 1
-
-/* MEMC_ARB_1 :: CLIENT_INFO_43 :: reserved0 [30:30] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_43_reserved0_MASK 0x40000000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_43_reserved0_SHIFT 30
-
-/* MEMC_ARB_1 :: CLIENT_INFO_43 :: BO_VAL [29:12] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_43_BO_VAL_MASK 0x3ffff000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_43_BO_VAL_SHIFT 12
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_43_BO_VAL_DEFAULT 0x00000000
-
-/* MEMC_ARB_1 :: CLIENT_INFO_43 :: reserved1 [11:08] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_43_reserved1_MASK 0x00000f00
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_43_reserved1_SHIFT 8
-
-/* MEMC_ARB_1 :: CLIENT_INFO_43 :: PR_TAG [07:00] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_43_PR_TAG_MASK 0x000000ff
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_43_PR_TAG_SHIFT 0
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_43_PR_TAG_DEFAULT 0x00000000
-
-/***************************************************************************
- *CLIENT_INFO_44 - Client Programming register for client 44.
- ***************************************************************************/
-/* MEMC_ARB_1 :: CLIENT_INFO_44 :: RR_EN [31:31] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_44_RR_EN_MASK 0x80000000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_44_RR_EN_SHIFT 31
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_44_RR_EN_DEFAULT 0x00000001
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_44_RR_EN_DISABLED 0
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_44_RR_EN_ENABLED 1
-
-/* MEMC_ARB_1 :: CLIENT_INFO_44 :: reserved0 [30:30] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_44_reserved0_MASK 0x40000000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_44_reserved0_SHIFT 30
-
-/* MEMC_ARB_1 :: CLIENT_INFO_44 :: BO_VAL [29:12] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_44_BO_VAL_MASK 0x3ffff000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_44_BO_VAL_SHIFT 12
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_44_BO_VAL_DEFAULT 0x00000000
-
-/* MEMC_ARB_1 :: CLIENT_INFO_44 :: reserved1 [11:08] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_44_reserved1_MASK 0x00000f00
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_44_reserved1_SHIFT 8
-
-/* MEMC_ARB_1 :: CLIENT_INFO_44 :: PR_TAG [07:00] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_44_PR_TAG_MASK 0x000000ff
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_44_PR_TAG_SHIFT 0
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_44_PR_TAG_DEFAULT 0x00000000
-
-/***************************************************************************
- *CLIENT_INFO_45 - Client Programming register for client 45.
- ***************************************************************************/
-/* MEMC_ARB_1 :: CLIENT_INFO_45 :: RR_EN [31:31] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_45_RR_EN_MASK 0x80000000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_45_RR_EN_SHIFT 31
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_45_RR_EN_DEFAULT 0x00000001
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_45_RR_EN_DISABLED 0
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_45_RR_EN_ENABLED 1
-
-/* MEMC_ARB_1 :: CLIENT_INFO_45 :: reserved0 [30:30] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_45_reserved0_MASK 0x40000000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_45_reserved0_SHIFT 30
-
-/* MEMC_ARB_1 :: CLIENT_INFO_45 :: BO_VAL [29:12] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_45_BO_VAL_MASK 0x3ffff000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_45_BO_VAL_SHIFT 12
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_45_BO_VAL_DEFAULT 0x00000000
-
-/* MEMC_ARB_1 :: CLIENT_INFO_45 :: reserved1 [11:08] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_45_reserved1_MASK 0x00000f00
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_45_reserved1_SHIFT 8
-
-/* MEMC_ARB_1 :: CLIENT_INFO_45 :: PR_TAG [07:00] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_45_PR_TAG_MASK 0x000000ff
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_45_PR_TAG_SHIFT 0
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_45_PR_TAG_DEFAULT 0x00000000
-
-/***************************************************************************
- *CLIENT_INFO_46 - Client Programming register for client 46.
- ***************************************************************************/
-/* MEMC_ARB_1 :: CLIENT_INFO_46 :: RR_EN [31:31] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_46_RR_EN_MASK 0x80000000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_46_RR_EN_SHIFT 31
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_46_RR_EN_DEFAULT 0x00000001
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_46_RR_EN_DISABLED 0
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_46_RR_EN_ENABLED 1
-
-/* MEMC_ARB_1 :: CLIENT_INFO_46 :: reserved0 [30:30] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_46_reserved0_MASK 0x40000000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_46_reserved0_SHIFT 30
-
-/* MEMC_ARB_1 :: CLIENT_INFO_46 :: BO_VAL [29:12] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_46_BO_VAL_MASK 0x3ffff000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_46_BO_VAL_SHIFT 12
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_46_BO_VAL_DEFAULT 0x00000000
-
-/* MEMC_ARB_1 :: CLIENT_INFO_46 :: reserved1 [11:08] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_46_reserved1_MASK 0x00000f00
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_46_reserved1_SHIFT 8
-
-/* MEMC_ARB_1 :: CLIENT_INFO_46 :: PR_TAG [07:00] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_46_PR_TAG_MASK 0x000000ff
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_46_PR_TAG_SHIFT 0
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_46_PR_TAG_DEFAULT 0x00000000
-
-/***************************************************************************
- *CLIENT_INFO_47 - Client Programming register for client 47.
- ***************************************************************************/
-/* MEMC_ARB_1 :: CLIENT_INFO_47 :: RR_EN [31:31] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_47_RR_EN_MASK 0x80000000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_47_RR_EN_SHIFT 31
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_47_RR_EN_DEFAULT 0x00000001
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_47_RR_EN_DISABLED 0
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_47_RR_EN_ENABLED 1
-
-/* MEMC_ARB_1 :: CLIENT_INFO_47 :: reserved0 [30:30] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_47_reserved0_MASK 0x40000000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_47_reserved0_SHIFT 30
-
-/* MEMC_ARB_1 :: CLIENT_INFO_47 :: BO_VAL [29:12] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_47_BO_VAL_MASK 0x3ffff000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_47_BO_VAL_SHIFT 12
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_47_BO_VAL_DEFAULT 0x00000000
-
-/* MEMC_ARB_1 :: CLIENT_INFO_47 :: reserved1 [11:08] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_47_reserved1_MASK 0x00000f00
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_47_reserved1_SHIFT 8
-
-/* MEMC_ARB_1 :: CLIENT_INFO_47 :: PR_TAG [07:00] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_47_PR_TAG_MASK 0x000000ff
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_47_PR_TAG_SHIFT 0
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_47_PR_TAG_DEFAULT 0x00000000
-
-/***************************************************************************
- *CLIENT_INFO_48 - Client Programming register for client 48.
- ***************************************************************************/
-/* MEMC_ARB_1 :: CLIENT_INFO_48 :: RR_EN [31:31] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_48_RR_EN_MASK 0x80000000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_48_RR_EN_SHIFT 31
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_48_RR_EN_DEFAULT 0x00000001
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_48_RR_EN_DISABLED 0
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_48_RR_EN_ENABLED 1
-
-/* MEMC_ARB_1 :: CLIENT_INFO_48 :: reserved0 [30:30] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_48_reserved0_MASK 0x40000000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_48_reserved0_SHIFT 30
-
-/* MEMC_ARB_1 :: CLIENT_INFO_48 :: BO_VAL [29:12] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_48_BO_VAL_MASK 0x3ffff000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_48_BO_VAL_SHIFT 12
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_48_BO_VAL_DEFAULT 0x00000000
-
-/* MEMC_ARB_1 :: CLIENT_INFO_48 :: reserved1 [11:08] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_48_reserved1_MASK 0x00000f00
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_48_reserved1_SHIFT 8
-
-/* MEMC_ARB_1 :: CLIENT_INFO_48 :: PR_TAG [07:00] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_48_PR_TAG_MASK 0x000000ff
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_48_PR_TAG_SHIFT 0
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_48_PR_TAG_DEFAULT 0x00000000
-
-/***************************************************************************
- *CLIENT_INFO_49 - Client Programming register for client 49.
- ***************************************************************************/
-/* MEMC_ARB_1 :: CLIENT_INFO_49 :: RR_EN [31:31] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_49_RR_EN_MASK 0x80000000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_49_RR_EN_SHIFT 31
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_49_RR_EN_DEFAULT 0x00000001
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_49_RR_EN_DISABLED 0
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_49_RR_EN_ENABLED 1
-
-/* MEMC_ARB_1 :: CLIENT_INFO_49 :: reserved0 [30:30] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_49_reserved0_MASK 0x40000000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_49_reserved0_SHIFT 30
-
-/* MEMC_ARB_1 :: CLIENT_INFO_49 :: BO_VAL [29:12] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_49_BO_VAL_MASK 0x3ffff000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_49_BO_VAL_SHIFT 12
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_49_BO_VAL_DEFAULT 0x00000000
-
-/* MEMC_ARB_1 :: CLIENT_INFO_49 :: reserved1 [11:08] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_49_reserved1_MASK 0x00000f00
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_49_reserved1_SHIFT 8
-
-/* MEMC_ARB_1 :: CLIENT_INFO_49 :: PR_TAG [07:00] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_49_PR_TAG_MASK 0x000000ff
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_49_PR_TAG_SHIFT 0
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_49_PR_TAG_DEFAULT 0x00000000
-
-/***************************************************************************
- *CLIENT_INFO_50 - Client Programming register for client 50.
- ***************************************************************************/
-/* MEMC_ARB_1 :: CLIENT_INFO_50 :: RR_EN [31:31] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_50_RR_EN_MASK 0x80000000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_50_RR_EN_SHIFT 31
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_50_RR_EN_DEFAULT 0x00000001
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_50_RR_EN_DISABLED 0
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_50_RR_EN_ENABLED 1
-
-/* MEMC_ARB_1 :: CLIENT_INFO_50 :: reserved0 [30:30] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_50_reserved0_MASK 0x40000000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_50_reserved0_SHIFT 30
-
-/* MEMC_ARB_1 :: CLIENT_INFO_50 :: BO_VAL [29:12] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_50_BO_VAL_MASK 0x3ffff000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_50_BO_VAL_SHIFT 12
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_50_BO_VAL_DEFAULT 0x00000000
-
-/* MEMC_ARB_1 :: CLIENT_INFO_50 :: reserved1 [11:08] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_50_reserved1_MASK 0x00000f00
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_50_reserved1_SHIFT 8
-
-/* MEMC_ARB_1 :: CLIENT_INFO_50 :: PR_TAG [07:00] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_50_PR_TAG_MASK 0x000000ff
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_50_PR_TAG_SHIFT 0
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_50_PR_TAG_DEFAULT 0x00000000
-
-/***************************************************************************
- *CLIENT_INFO_51 - Client Programming register for client 51.
- ***************************************************************************/
-/* MEMC_ARB_1 :: CLIENT_INFO_51 :: RR_EN [31:31] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_51_RR_EN_MASK 0x80000000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_51_RR_EN_SHIFT 31
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_51_RR_EN_DEFAULT 0x00000001
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_51_RR_EN_DISABLED 0
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_51_RR_EN_ENABLED 1
-
-/* MEMC_ARB_1 :: CLIENT_INFO_51 :: reserved0 [30:30] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_51_reserved0_MASK 0x40000000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_51_reserved0_SHIFT 30
-
-/* MEMC_ARB_1 :: CLIENT_INFO_51 :: BO_VAL [29:12] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_51_BO_VAL_MASK 0x3ffff000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_51_BO_VAL_SHIFT 12
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_51_BO_VAL_DEFAULT 0x00000000
-
-/* MEMC_ARB_1 :: CLIENT_INFO_51 :: reserved1 [11:08] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_51_reserved1_MASK 0x00000f00
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_51_reserved1_SHIFT 8
-
-/* MEMC_ARB_1 :: CLIENT_INFO_51 :: PR_TAG [07:00] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_51_PR_TAG_MASK 0x000000ff
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_51_PR_TAG_SHIFT 0
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_51_PR_TAG_DEFAULT 0x00000000
-
-/***************************************************************************
- *CLIENT_INFO_52 - Client Programming register for client 52.
- ***************************************************************************/
-/* MEMC_ARB_1 :: CLIENT_INFO_52 :: RR_EN [31:31] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_52_RR_EN_MASK 0x80000000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_52_RR_EN_SHIFT 31
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_52_RR_EN_DEFAULT 0x00000001
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_52_RR_EN_DISABLED 0
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_52_RR_EN_ENABLED 1
-
-/* MEMC_ARB_1 :: CLIENT_INFO_52 :: reserved0 [30:30] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_52_reserved0_MASK 0x40000000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_52_reserved0_SHIFT 30
-
-/* MEMC_ARB_1 :: CLIENT_INFO_52 :: BO_VAL [29:12] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_52_BO_VAL_MASK 0x3ffff000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_52_BO_VAL_SHIFT 12
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_52_BO_VAL_DEFAULT 0x00000000
-
-/* MEMC_ARB_1 :: CLIENT_INFO_52 :: reserved1 [11:08] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_52_reserved1_MASK 0x00000f00
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_52_reserved1_SHIFT 8
-
-/* MEMC_ARB_1 :: CLIENT_INFO_52 :: PR_TAG [07:00] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_52_PR_TAG_MASK 0x000000ff
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_52_PR_TAG_SHIFT 0
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_52_PR_TAG_DEFAULT 0x00000000
-
-/***************************************************************************
- *CLIENT_INFO_53 - Client Programming register for client 53.
- ***************************************************************************/
-/* MEMC_ARB_1 :: CLIENT_INFO_53 :: RR_EN [31:31] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_53_RR_EN_MASK 0x80000000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_53_RR_EN_SHIFT 31
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_53_RR_EN_DEFAULT 0x00000001
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_53_RR_EN_DISABLED 0
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_53_RR_EN_ENABLED 1
-
-/* MEMC_ARB_1 :: CLIENT_INFO_53 :: reserved0 [30:30] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_53_reserved0_MASK 0x40000000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_53_reserved0_SHIFT 30
-
-/* MEMC_ARB_1 :: CLIENT_INFO_53 :: BO_VAL [29:12] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_53_BO_VAL_MASK 0x3ffff000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_53_BO_VAL_SHIFT 12
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_53_BO_VAL_DEFAULT 0x00000000
-
-/* MEMC_ARB_1 :: CLIENT_INFO_53 :: reserved1 [11:08] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_53_reserved1_MASK 0x00000f00
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_53_reserved1_SHIFT 8
-
-/* MEMC_ARB_1 :: CLIENT_INFO_53 :: PR_TAG [07:00] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_53_PR_TAG_MASK 0x000000ff
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_53_PR_TAG_SHIFT 0
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_53_PR_TAG_DEFAULT 0x00000000
-
-/***************************************************************************
- *CLIENT_INFO_54 - Client Programming register for client 54.
- ***************************************************************************/
-/* MEMC_ARB_1 :: CLIENT_INFO_54 :: RR_EN [31:31] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_54_RR_EN_MASK 0x80000000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_54_RR_EN_SHIFT 31
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_54_RR_EN_DEFAULT 0x00000001
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_54_RR_EN_DISABLED 0
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_54_RR_EN_ENABLED 1
-
-/* MEMC_ARB_1 :: CLIENT_INFO_54 :: reserved0 [30:30] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_54_reserved0_MASK 0x40000000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_54_reserved0_SHIFT 30
-
-/* MEMC_ARB_1 :: CLIENT_INFO_54 :: BO_VAL [29:12] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_54_BO_VAL_MASK 0x3ffff000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_54_BO_VAL_SHIFT 12
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_54_BO_VAL_DEFAULT 0x00000000
-
-/* MEMC_ARB_1 :: CLIENT_INFO_54 :: reserved1 [11:08] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_54_reserved1_MASK 0x00000f00
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_54_reserved1_SHIFT 8
-
-/* MEMC_ARB_1 :: CLIENT_INFO_54 :: PR_TAG [07:00] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_54_PR_TAG_MASK 0x000000ff
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_54_PR_TAG_SHIFT 0
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_54_PR_TAG_DEFAULT 0x00000000
-
-/***************************************************************************
- *CLIENT_INFO_55 - Client Programming register for client 55.
- ***************************************************************************/
-/* MEMC_ARB_1 :: CLIENT_INFO_55 :: RR_EN [31:31] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_55_RR_EN_MASK 0x80000000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_55_RR_EN_SHIFT 31
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_55_RR_EN_DEFAULT 0x00000001
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_55_RR_EN_DISABLED 0
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_55_RR_EN_ENABLED 1
-
-/* MEMC_ARB_1 :: CLIENT_INFO_55 :: reserved0 [30:30] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_55_reserved0_MASK 0x40000000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_55_reserved0_SHIFT 30
-
-/* MEMC_ARB_1 :: CLIENT_INFO_55 :: BO_VAL [29:12] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_55_BO_VAL_MASK 0x3ffff000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_55_BO_VAL_SHIFT 12
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_55_BO_VAL_DEFAULT 0x00000000
-
-/* MEMC_ARB_1 :: CLIENT_INFO_55 :: reserved1 [11:08] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_55_reserved1_MASK 0x00000f00
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_55_reserved1_SHIFT 8
-
-/* MEMC_ARB_1 :: CLIENT_INFO_55 :: PR_TAG [07:00] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_55_PR_TAG_MASK 0x000000ff
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_55_PR_TAG_SHIFT 0
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_55_PR_TAG_DEFAULT 0x00000000
-
-/***************************************************************************
- *CLIENT_INFO_56 - Client Programming register for client 56.
- ***************************************************************************/
-/* MEMC_ARB_1 :: CLIENT_INFO_56 :: RR_EN [31:31] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_56_RR_EN_MASK 0x80000000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_56_RR_EN_SHIFT 31
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_56_RR_EN_DEFAULT 0x00000001
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_56_RR_EN_DISABLED 0
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_56_RR_EN_ENABLED 1
-
-/* MEMC_ARB_1 :: CLIENT_INFO_56 :: reserved0 [30:30] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_56_reserved0_MASK 0x40000000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_56_reserved0_SHIFT 30
-
-/* MEMC_ARB_1 :: CLIENT_INFO_56 :: BO_VAL [29:12] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_56_BO_VAL_MASK 0x3ffff000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_56_BO_VAL_SHIFT 12
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_56_BO_VAL_DEFAULT 0x00000000
-
-/* MEMC_ARB_1 :: CLIENT_INFO_56 :: reserved1 [11:08] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_56_reserved1_MASK 0x00000f00
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_56_reserved1_SHIFT 8
-
-/* MEMC_ARB_1 :: CLIENT_INFO_56 :: PR_TAG [07:00] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_56_PR_TAG_MASK 0x000000ff
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_56_PR_TAG_SHIFT 0
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_56_PR_TAG_DEFAULT 0x00000000
-
-/***************************************************************************
- *CLIENT_INFO_57 - Client Programming register for client 57.
- ***************************************************************************/
-/* MEMC_ARB_1 :: CLIENT_INFO_57 :: RR_EN [31:31] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_57_RR_EN_MASK 0x80000000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_57_RR_EN_SHIFT 31
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_57_RR_EN_DEFAULT 0x00000001
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_57_RR_EN_DISABLED 0
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_57_RR_EN_ENABLED 1
-
-/* MEMC_ARB_1 :: CLIENT_INFO_57 :: reserved0 [30:30] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_57_reserved0_MASK 0x40000000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_57_reserved0_SHIFT 30
-
-/* MEMC_ARB_1 :: CLIENT_INFO_57 :: BO_VAL [29:12] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_57_BO_VAL_MASK 0x3ffff000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_57_BO_VAL_SHIFT 12
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_57_BO_VAL_DEFAULT 0x00000000
-
-/* MEMC_ARB_1 :: CLIENT_INFO_57 :: reserved1 [11:08] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_57_reserved1_MASK 0x00000f00
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_57_reserved1_SHIFT 8
-
-/* MEMC_ARB_1 :: CLIENT_INFO_57 :: PR_TAG [07:00] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_57_PR_TAG_MASK 0x000000ff
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_57_PR_TAG_SHIFT 0
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_57_PR_TAG_DEFAULT 0x00000000
-
-/***************************************************************************
- *CLIENT_INFO_58 - Client Programming register for client 58.
- ***************************************************************************/
-/* MEMC_ARB_1 :: CLIENT_INFO_58 :: RR_EN [31:31] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_58_RR_EN_MASK 0x80000000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_58_RR_EN_SHIFT 31
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_58_RR_EN_DEFAULT 0x00000001
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_58_RR_EN_DISABLED 0
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_58_RR_EN_ENABLED 1
-
-/* MEMC_ARB_1 :: CLIENT_INFO_58 :: reserved0 [30:30] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_58_reserved0_MASK 0x40000000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_58_reserved0_SHIFT 30
-
-/* MEMC_ARB_1 :: CLIENT_INFO_58 :: BO_VAL [29:12] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_58_BO_VAL_MASK 0x3ffff000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_58_BO_VAL_SHIFT 12
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_58_BO_VAL_DEFAULT 0x00000000
-
-/* MEMC_ARB_1 :: CLIENT_INFO_58 :: reserved1 [11:08] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_58_reserved1_MASK 0x00000f00
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_58_reserved1_SHIFT 8
-
-/* MEMC_ARB_1 :: CLIENT_INFO_58 :: PR_TAG [07:00] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_58_PR_TAG_MASK 0x000000ff
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_58_PR_TAG_SHIFT 0
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_58_PR_TAG_DEFAULT 0x00000000
-
-/***************************************************************************
- *CLIENT_INFO_59 - Client Programming register for client 59.
- ***************************************************************************/
-/* MEMC_ARB_1 :: CLIENT_INFO_59 :: RR_EN [31:31] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_59_RR_EN_MASK 0x80000000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_59_RR_EN_SHIFT 31
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_59_RR_EN_DEFAULT 0x00000001
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_59_RR_EN_DISABLED 0
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_59_RR_EN_ENABLED 1
-
-/* MEMC_ARB_1 :: CLIENT_INFO_59 :: reserved0 [30:30] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_59_reserved0_MASK 0x40000000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_59_reserved0_SHIFT 30
-
-/* MEMC_ARB_1 :: CLIENT_INFO_59 :: BO_VAL [29:12] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_59_BO_VAL_MASK 0x3ffff000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_59_BO_VAL_SHIFT 12
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_59_BO_VAL_DEFAULT 0x00000000
-
-/* MEMC_ARB_1 :: CLIENT_INFO_59 :: reserved1 [11:08] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_59_reserved1_MASK 0x00000f00
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_59_reserved1_SHIFT 8
-
-/* MEMC_ARB_1 :: CLIENT_INFO_59 :: PR_TAG [07:00] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_59_PR_TAG_MASK 0x000000ff
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_59_PR_TAG_SHIFT 0
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_59_PR_TAG_DEFAULT 0x00000000
-
-/***************************************************************************
- *CLIENT_INFO_60 - Client Programming register for client 60.
- ***************************************************************************/
-/* MEMC_ARB_1 :: CLIENT_INFO_60 :: RR_EN [31:31] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_60_RR_EN_MASK 0x80000000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_60_RR_EN_SHIFT 31
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_60_RR_EN_DEFAULT 0x00000001
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_60_RR_EN_DISABLED 0
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_60_RR_EN_ENABLED 1
-
-/* MEMC_ARB_1 :: CLIENT_INFO_60 :: reserved0 [30:30] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_60_reserved0_MASK 0x40000000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_60_reserved0_SHIFT 30
-
-/* MEMC_ARB_1 :: CLIENT_INFO_60 :: BO_VAL [29:12] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_60_BO_VAL_MASK 0x3ffff000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_60_BO_VAL_SHIFT 12
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_60_BO_VAL_DEFAULT 0x00000000
-
-/* MEMC_ARB_1 :: CLIENT_INFO_60 :: reserved1 [11:08] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_60_reserved1_MASK 0x00000f00
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_60_reserved1_SHIFT 8
-
-/* MEMC_ARB_1 :: CLIENT_INFO_60 :: PR_TAG [07:00] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_60_PR_TAG_MASK 0x000000ff
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_60_PR_TAG_SHIFT 0
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_60_PR_TAG_DEFAULT 0x00000000
-
-/***************************************************************************
- *CLIENT_INFO_61 - Client Programming register for client 61.
- ***************************************************************************/
-/* MEMC_ARB_1 :: CLIENT_INFO_61 :: RR_EN [31:31] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_61_RR_EN_MASK 0x80000000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_61_RR_EN_SHIFT 31
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_61_RR_EN_DEFAULT 0x00000001
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_61_RR_EN_DISABLED 0
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_61_RR_EN_ENABLED 1
-
-/* MEMC_ARB_1 :: CLIENT_INFO_61 :: reserved0 [30:30] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_61_reserved0_MASK 0x40000000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_61_reserved0_SHIFT 30
-
-/* MEMC_ARB_1 :: CLIENT_INFO_61 :: BO_VAL [29:12] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_61_BO_VAL_MASK 0x3ffff000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_61_BO_VAL_SHIFT 12
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_61_BO_VAL_DEFAULT 0x00000000
-
-/* MEMC_ARB_1 :: CLIENT_INFO_61 :: reserved1 [11:08] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_61_reserved1_MASK 0x00000f00
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_61_reserved1_SHIFT 8
-
-/* MEMC_ARB_1 :: CLIENT_INFO_61 :: PR_TAG [07:00] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_61_PR_TAG_MASK 0x000000ff
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_61_PR_TAG_SHIFT 0
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_61_PR_TAG_DEFAULT 0x00000000
-
-/***************************************************************************
- *CLIENT_INFO_62 - Client Programming register for client 62.
- ***************************************************************************/
-/* MEMC_ARB_1 :: CLIENT_INFO_62 :: RR_EN [31:31] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_62_RR_EN_MASK 0x80000000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_62_RR_EN_SHIFT 31
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_62_RR_EN_DEFAULT 0x00000001
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_62_RR_EN_DISABLED 0
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_62_RR_EN_ENABLED 1
-
-/* MEMC_ARB_1 :: CLIENT_INFO_62 :: reserved0 [30:30] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_62_reserved0_MASK 0x40000000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_62_reserved0_SHIFT 30
-
-/* MEMC_ARB_1 :: CLIENT_INFO_62 :: BO_VAL [29:12] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_62_BO_VAL_MASK 0x3ffff000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_62_BO_VAL_SHIFT 12
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_62_BO_VAL_DEFAULT 0x00000000
-
-/* MEMC_ARB_1 :: CLIENT_INFO_62 :: reserved1 [11:08] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_62_reserved1_MASK 0x00000f00
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_62_reserved1_SHIFT 8
-
-/* MEMC_ARB_1 :: CLIENT_INFO_62 :: PR_TAG [07:00] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_62_PR_TAG_MASK 0x000000ff
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_62_PR_TAG_SHIFT 0
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_62_PR_TAG_DEFAULT 0x00000000
-
-/***************************************************************************
- *CLIENT_INFO_63 - Client Programming register for client 63.
- ***************************************************************************/
-/* MEMC_ARB_1 :: CLIENT_INFO_63 :: RR_EN [31:31] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_63_RR_EN_MASK 0x80000000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_63_RR_EN_SHIFT 31
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_63_RR_EN_DEFAULT 0x00000001
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_63_RR_EN_DISABLED 0
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_63_RR_EN_ENABLED 1
-
-/* MEMC_ARB_1 :: CLIENT_INFO_63 :: reserved0 [30:30] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_63_reserved0_MASK 0x40000000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_63_reserved0_SHIFT 30
-
-/* MEMC_ARB_1 :: CLIENT_INFO_63 :: BO_VAL [29:12] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_63_BO_VAL_MASK 0x3ffff000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_63_BO_VAL_SHIFT 12
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_63_BO_VAL_DEFAULT 0x00000000
-
-/* MEMC_ARB_1 :: CLIENT_INFO_63 :: reserved1 [11:08] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_63_reserved1_MASK 0x00000f00
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_63_reserved1_SHIFT 8
-
-/* MEMC_ARB_1 :: CLIENT_INFO_63 :: PR_TAG [07:00] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_63_PR_TAG_MASK 0x000000ff
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_63_PR_TAG_SHIFT 0
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_63_PR_TAG_DEFAULT 0x00000000
-
-/***************************************************************************
- *CLIENT_INFO_64 - Client Programming register for client 64.
- ***************************************************************************/
-/* MEMC_ARB_1 :: CLIENT_INFO_64 :: RR_EN [31:31] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_64_RR_EN_MASK 0x80000000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_64_RR_EN_SHIFT 31
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_64_RR_EN_DEFAULT 0x00000001
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_64_RR_EN_DISABLED 0
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_64_RR_EN_ENABLED 1
-
-/* MEMC_ARB_1 :: CLIENT_INFO_64 :: reserved0 [30:30] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_64_reserved0_MASK 0x40000000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_64_reserved0_SHIFT 30
-
-/* MEMC_ARB_1 :: CLIENT_INFO_64 :: BO_VAL [29:12] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_64_BO_VAL_MASK 0x3ffff000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_64_BO_VAL_SHIFT 12
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_64_BO_VAL_DEFAULT 0x00000000
-
-/* MEMC_ARB_1 :: CLIENT_INFO_64 :: reserved1 [11:08] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_64_reserved1_MASK 0x00000f00
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_64_reserved1_SHIFT 8
-
-/* MEMC_ARB_1 :: CLIENT_INFO_64 :: PR_TAG [07:00] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_64_PR_TAG_MASK 0x000000ff
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_64_PR_TAG_SHIFT 0
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_64_PR_TAG_DEFAULT 0x00000000
-
-/***************************************************************************
- *CLIENT_INFO_65 - Client Programming register for client 65.
- ***************************************************************************/
-/* MEMC_ARB_1 :: CLIENT_INFO_65 :: RR_EN [31:31] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_65_RR_EN_MASK 0x80000000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_65_RR_EN_SHIFT 31
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_65_RR_EN_DEFAULT 0x00000001
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_65_RR_EN_DISABLED 0
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_65_RR_EN_ENABLED 1
-
-/* MEMC_ARB_1 :: CLIENT_INFO_65 :: reserved0 [30:30] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_65_reserved0_MASK 0x40000000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_65_reserved0_SHIFT 30
-
-/* MEMC_ARB_1 :: CLIENT_INFO_65 :: BO_VAL [29:12] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_65_BO_VAL_MASK 0x3ffff000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_65_BO_VAL_SHIFT 12
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_65_BO_VAL_DEFAULT 0x00000000
-
-/* MEMC_ARB_1 :: CLIENT_INFO_65 :: reserved1 [11:08] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_65_reserved1_MASK 0x00000f00
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_65_reserved1_SHIFT 8
-
-/* MEMC_ARB_1 :: CLIENT_INFO_65 :: PR_TAG [07:00] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_65_PR_TAG_MASK 0x000000ff
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_65_PR_TAG_SHIFT 0
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_65_PR_TAG_DEFAULT 0x00000000
-
-/***************************************************************************
- *CLIENT_INFO_66 - Client Programming register for client 66.
- ***************************************************************************/
-/* MEMC_ARB_1 :: CLIENT_INFO_66 :: RR_EN [31:31] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_66_RR_EN_MASK 0x80000000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_66_RR_EN_SHIFT 31
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_66_RR_EN_DEFAULT 0x00000001
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_66_RR_EN_DISABLED 0
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_66_RR_EN_ENABLED 1
-
-/* MEMC_ARB_1 :: CLIENT_INFO_66 :: reserved0 [30:30] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_66_reserved0_MASK 0x40000000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_66_reserved0_SHIFT 30
-
-/* MEMC_ARB_1 :: CLIENT_INFO_66 :: BO_VAL [29:12] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_66_BO_VAL_MASK 0x3ffff000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_66_BO_VAL_SHIFT 12
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_66_BO_VAL_DEFAULT 0x00000000
-
-/* MEMC_ARB_1 :: CLIENT_INFO_66 :: reserved1 [11:08] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_66_reserved1_MASK 0x00000f00
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_66_reserved1_SHIFT 8
-
-/* MEMC_ARB_1 :: CLIENT_INFO_66 :: PR_TAG [07:00] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_66_PR_TAG_MASK 0x000000ff
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_66_PR_TAG_SHIFT 0
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_66_PR_TAG_DEFAULT 0x00000000
-
-/***************************************************************************
- *CLIENT_INFO_67 - Client Programming register for client 67.
- ***************************************************************************/
-/* MEMC_ARB_1 :: CLIENT_INFO_67 :: RR_EN [31:31] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_67_RR_EN_MASK 0x80000000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_67_RR_EN_SHIFT 31
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_67_RR_EN_DEFAULT 0x00000001
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_67_RR_EN_DISABLED 0
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_67_RR_EN_ENABLED 1
-
-/* MEMC_ARB_1 :: CLIENT_INFO_67 :: reserved0 [30:30] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_67_reserved0_MASK 0x40000000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_67_reserved0_SHIFT 30
-
-/* MEMC_ARB_1 :: CLIENT_INFO_67 :: BO_VAL [29:12] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_67_BO_VAL_MASK 0x3ffff000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_67_BO_VAL_SHIFT 12
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_67_BO_VAL_DEFAULT 0x00000000
-
-/* MEMC_ARB_1 :: CLIENT_INFO_67 :: reserved1 [11:08] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_67_reserved1_MASK 0x00000f00
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_67_reserved1_SHIFT 8
-
-/* MEMC_ARB_1 :: CLIENT_INFO_67 :: PR_TAG [07:00] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_67_PR_TAG_MASK 0x000000ff
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_67_PR_TAG_SHIFT 0
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_67_PR_TAG_DEFAULT 0x00000000
-
-/***************************************************************************
- *CLIENT_INFO_68 - Client Programming register for client 68.
- ***************************************************************************/
-/* MEMC_ARB_1 :: CLIENT_INFO_68 :: RR_EN [31:31] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_68_RR_EN_MASK 0x80000000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_68_RR_EN_SHIFT 31
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_68_RR_EN_DEFAULT 0x00000001
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_68_RR_EN_DISABLED 0
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_68_RR_EN_ENABLED 1
-
-/* MEMC_ARB_1 :: CLIENT_INFO_68 :: reserved0 [30:30] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_68_reserved0_MASK 0x40000000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_68_reserved0_SHIFT 30
-
-/* MEMC_ARB_1 :: CLIENT_INFO_68 :: BO_VAL [29:12] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_68_BO_VAL_MASK 0x3ffff000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_68_BO_VAL_SHIFT 12
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_68_BO_VAL_DEFAULT 0x00000000
-
-/* MEMC_ARB_1 :: CLIENT_INFO_68 :: reserved1 [11:08] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_68_reserved1_MASK 0x00000f00
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_68_reserved1_SHIFT 8
-
-/* MEMC_ARB_1 :: CLIENT_INFO_68 :: PR_TAG [07:00] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_68_PR_TAG_MASK 0x000000ff
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_68_PR_TAG_SHIFT 0
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_68_PR_TAG_DEFAULT 0x00000000
-
-/***************************************************************************
- *CLIENT_INFO_69 - Client Programming register for client 69.
- ***************************************************************************/
-/* MEMC_ARB_1 :: CLIENT_INFO_69 :: RR_EN [31:31] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_69_RR_EN_MASK 0x80000000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_69_RR_EN_SHIFT 31
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_69_RR_EN_DEFAULT 0x00000001
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_69_RR_EN_DISABLED 0
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_69_RR_EN_ENABLED 1
-
-/* MEMC_ARB_1 :: CLIENT_INFO_69 :: reserved0 [30:30] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_69_reserved0_MASK 0x40000000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_69_reserved0_SHIFT 30
-
-/* MEMC_ARB_1 :: CLIENT_INFO_69 :: BO_VAL [29:12] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_69_BO_VAL_MASK 0x3ffff000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_69_BO_VAL_SHIFT 12
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_69_BO_VAL_DEFAULT 0x00000000
-
-/* MEMC_ARB_1 :: CLIENT_INFO_69 :: reserved1 [11:08] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_69_reserved1_MASK 0x00000f00
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_69_reserved1_SHIFT 8
-
-/* MEMC_ARB_1 :: CLIENT_INFO_69 :: PR_TAG [07:00] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_69_PR_TAG_MASK 0x000000ff
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_69_PR_TAG_SHIFT 0
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_69_PR_TAG_DEFAULT 0x00000000
-
-/***************************************************************************
- *CLIENT_INFO_70 - Client Programming register for client 70.
- ***************************************************************************/
-/* MEMC_ARB_1 :: CLIENT_INFO_70 :: RR_EN [31:31] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_70_RR_EN_MASK 0x80000000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_70_RR_EN_SHIFT 31
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_70_RR_EN_DEFAULT 0x00000001
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_70_RR_EN_DISABLED 0
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_70_RR_EN_ENABLED 1
-
-/* MEMC_ARB_1 :: CLIENT_INFO_70 :: reserved0 [30:30] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_70_reserved0_MASK 0x40000000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_70_reserved0_SHIFT 30
-
-/* MEMC_ARB_1 :: CLIENT_INFO_70 :: BO_VAL [29:12] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_70_BO_VAL_MASK 0x3ffff000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_70_BO_VAL_SHIFT 12
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_70_BO_VAL_DEFAULT 0x00000000
-
-/* MEMC_ARB_1 :: CLIENT_INFO_70 :: reserved1 [11:08] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_70_reserved1_MASK 0x00000f00
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_70_reserved1_SHIFT 8
-
-/* MEMC_ARB_1 :: CLIENT_INFO_70 :: PR_TAG [07:00] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_70_PR_TAG_MASK 0x000000ff
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_70_PR_TAG_SHIFT 0
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_70_PR_TAG_DEFAULT 0x00000000
-
-/***************************************************************************
- *CLIENT_INFO_71 - Client Programming register for client 71.
- ***************************************************************************/
-/* MEMC_ARB_1 :: CLIENT_INFO_71 :: RR_EN [31:31] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_71_RR_EN_MASK 0x80000000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_71_RR_EN_SHIFT 31
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_71_RR_EN_DEFAULT 0x00000001
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_71_RR_EN_DISABLED 0
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_71_RR_EN_ENABLED 1
-
-/* MEMC_ARB_1 :: CLIENT_INFO_71 :: reserved0 [30:30] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_71_reserved0_MASK 0x40000000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_71_reserved0_SHIFT 30
-
-/* MEMC_ARB_1 :: CLIENT_INFO_71 :: BO_VAL [29:12] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_71_BO_VAL_MASK 0x3ffff000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_71_BO_VAL_SHIFT 12
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_71_BO_VAL_DEFAULT 0x00000000
-
-/* MEMC_ARB_1 :: CLIENT_INFO_71 :: reserved1 [11:08] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_71_reserved1_MASK 0x00000f00
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_71_reserved1_SHIFT 8
-
-/* MEMC_ARB_1 :: CLIENT_INFO_71 :: PR_TAG [07:00] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_71_PR_TAG_MASK 0x000000ff
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_71_PR_TAG_SHIFT 0
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_71_PR_TAG_DEFAULT 0x00000000
-
-/***************************************************************************
- *CLIENT_INFO_72 - Client Programming register for client 72.
- ***************************************************************************/
-/* MEMC_ARB_1 :: CLIENT_INFO_72 :: RR_EN [31:31] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_72_RR_EN_MASK 0x80000000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_72_RR_EN_SHIFT 31
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_72_RR_EN_DEFAULT 0x00000001
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_72_RR_EN_DISABLED 0
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_72_RR_EN_ENABLED 1
-
-/* MEMC_ARB_1 :: CLIENT_INFO_72 :: reserved0 [30:30] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_72_reserved0_MASK 0x40000000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_72_reserved0_SHIFT 30
-
-/* MEMC_ARB_1 :: CLIENT_INFO_72 :: BO_VAL [29:12] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_72_BO_VAL_MASK 0x3ffff000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_72_BO_VAL_SHIFT 12
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_72_BO_VAL_DEFAULT 0x00000000
-
-/* MEMC_ARB_1 :: CLIENT_INFO_72 :: reserved1 [11:08] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_72_reserved1_MASK 0x00000f00
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_72_reserved1_SHIFT 8
-
-/* MEMC_ARB_1 :: CLIENT_INFO_72 :: PR_TAG [07:00] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_72_PR_TAG_MASK 0x000000ff
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_72_PR_TAG_SHIFT 0
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_72_PR_TAG_DEFAULT 0x00000000
-
-/***************************************************************************
- *CLIENT_INFO_73 - Client Programming register for client 73.
- ***************************************************************************/
-/* MEMC_ARB_1 :: CLIENT_INFO_73 :: RR_EN [31:31] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_73_RR_EN_MASK 0x80000000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_73_RR_EN_SHIFT 31
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_73_RR_EN_DEFAULT 0x00000001
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_73_RR_EN_DISABLED 0
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_73_RR_EN_ENABLED 1
-
-/* MEMC_ARB_1 :: CLIENT_INFO_73 :: reserved0 [30:30] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_73_reserved0_MASK 0x40000000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_73_reserved0_SHIFT 30
-
-/* MEMC_ARB_1 :: CLIENT_INFO_73 :: BO_VAL [29:12] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_73_BO_VAL_MASK 0x3ffff000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_73_BO_VAL_SHIFT 12
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_73_BO_VAL_DEFAULT 0x00000000
-
-/* MEMC_ARB_1 :: CLIENT_INFO_73 :: reserved1 [11:08] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_73_reserved1_MASK 0x00000f00
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_73_reserved1_SHIFT 8
-
-/* MEMC_ARB_1 :: CLIENT_INFO_73 :: PR_TAG [07:00] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_73_PR_TAG_MASK 0x000000ff
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_73_PR_TAG_SHIFT 0
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_73_PR_TAG_DEFAULT 0x00000000
-
-/***************************************************************************
- *CLIENT_INFO_74 - Client Programming register for client 74.
- ***************************************************************************/
-/* MEMC_ARB_1 :: CLIENT_INFO_74 :: RR_EN [31:31] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_74_RR_EN_MASK 0x80000000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_74_RR_EN_SHIFT 31
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_74_RR_EN_DEFAULT 0x00000001
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_74_RR_EN_DISABLED 0
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_74_RR_EN_ENABLED 1
-
-/* MEMC_ARB_1 :: CLIENT_INFO_74 :: reserved0 [30:30] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_74_reserved0_MASK 0x40000000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_74_reserved0_SHIFT 30
-
-/* MEMC_ARB_1 :: CLIENT_INFO_74 :: BO_VAL [29:12] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_74_BO_VAL_MASK 0x3ffff000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_74_BO_VAL_SHIFT 12
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_74_BO_VAL_DEFAULT 0x00000000
-
-/* MEMC_ARB_1 :: CLIENT_INFO_74 :: reserved1 [11:08] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_74_reserved1_MASK 0x00000f00
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_74_reserved1_SHIFT 8
-
-/* MEMC_ARB_1 :: CLIENT_INFO_74 :: PR_TAG [07:00] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_74_PR_TAG_MASK 0x000000ff
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_74_PR_TAG_SHIFT 0
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_74_PR_TAG_DEFAULT 0x00000000
-
-/***************************************************************************
- *CLIENT_INFO_75 - Client Programming register for client 75.
- ***************************************************************************/
-/* MEMC_ARB_1 :: CLIENT_INFO_75 :: RR_EN [31:31] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_75_RR_EN_MASK 0x80000000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_75_RR_EN_SHIFT 31
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_75_RR_EN_DEFAULT 0x00000001
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_75_RR_EN_DISABLED 0
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_75_RR_EN_ENABLED 1
-
-/* MEMC_ARB_1 :: CLIENT_INFO_75 :: reserved0 [30:30] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_75_reserved0_MASK 0x40000000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_75_reserved0_SHIFT 30
-
-/* MEMC_ARB_1 :: CLIENT_INFO_75 :: BO_VAL [29:12] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_75_BO_VAL_MASK 0x3ffff000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_75_BO_VAL_SHIFT 12
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_75_BO_VAL_DEFAULT 0x00000000
-
-/* MEMC_ARB_1 :: CLIENT_INFO_75 :: reserved1 [11:08] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_75_reserved1_MASK 0x00000f00
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_75_reserved1_SHIFT 8
-
-/* MEMC_ARB_1 :: CLIENT_INFO_75 :: PR_TAG [07:00] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_75_PR_TAG_MASK 0x000000ff
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_75_PR_TAG_SHIFT 0
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_75_PR_TAG_DEFAULT 0x00000000
-
-/***************************************************************************
- *CLIENT_INFO_76 - Client Programming register for client 76.
- ***************************************************************************/
-/* MEMC_ARB_1 :: CLIENT_INFO_76 :: RR_EN [31:31] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_76_RR_EN_MASK 0x80000000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_76_RR_EN_SHIFT 31
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_76_RR_EN_DEFAULT 0x00000001
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_76_RR_EN_DISABLED 0
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_76_RR_EN_ENABLED 1
-
-/* MEMC_ARB_1 :: CLIENT_INFO_76 :: reserved0 [30:30] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_76_reserved0_MASK 0x40000000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_76_reserved0_SHIFT 30
-
-/* MEMC_ARB_1 :: CLIENT_INFO_76 :: BO_VAL [29:12] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_76_BO_VAL_MASK 0x3ffff000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_76_BO_VAL_SHIFT 12
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_76_BO_VAL_DEFAULT 0x00000000
-
-/* MEMC_ARB_1 :: CLIENT_INFO_76 :: reserved1 [11:08] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_76_reserved1_MASK 0x00000f00
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_76_reserved1_SHIFT 8
-
-/* MEMC_ARB_1 :: CLIENT_INFO_76 :: PR_TAG [07:00] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_76_PR_TAG_MASK 0x000000ff
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_76_PR_TAG_SHIFT 0
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_76_PR_TAG_DEFAULT 0x00000000
-
-/***************************************************************************
- *CLIENT_INFO_77 - Client Programming register for client 77.
- ***************************************************************************/
-/* MEMC_ARB_1 :: CLIENT_INFO_77 :: RR_EN [31:31] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_77_RR_EN_MASK 0x80000000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_77_RR_EN_SHIFT 31
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_77_RR_EN_DEFAULT 0x00000001
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_77_RR_EN_DISABLED 0
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_77_RR_EN_ENABLED 1
-
-/* MEMC_ARB_1 :: CLIENT_INFO_77 :: reserved0 [30:30] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_77_reserved0_MASK 0x40000000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_77_reserved0_SHIFT 30
-
-/* MEMC_ARB_1 :: CLIENT_INFO_77 :: BO_VAL [29:12] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_77_BO_VAL_MASK 0x3ffff000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_77_BO_VAL_SHIFT 12
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_77_BO_VAL_DEFAULT 0x00000000
-
-/* MEMC_ARB_1 :: CLIENT_INFO_77 :: reserved1 [11:08] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_77_reserved1_MASK 0x00000f00
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_77_reserved1_SHIFT 8
-
-/* MEMC_ARB_1 :: CLIENT_INFO_77 :: PR_TAG [07:00] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_77_PR_TAG_MASK 0x000000ff
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_77_PR_TAG_SHIFT 0
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_77_PR_TAG_DEFAULT 0x00000000
-
-/***************************************************************************
- *CLIENT_INFO_78 - Client Programming register for client 78.
- ***************************************************************************/
-/* MEMC_ARB_1 :: CLIENT_INFO_78 :: RR_EN [31:31] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_78_RR_EN_MASK 0x80000000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_78_RR_EN_SHIFT 31
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_78_RR_EN_DEFAULT 0x00000001
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_78_RR_EN_DISABLED 0
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_78_RR_EN_ENABLED 1
-
-/* MEMC_ARB_1 :: CLIENT_INFO_78 :: reserved0 [30:30] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_78_reserved0_MASK 0x40000000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_78_reserved0_SHIFT 30
-
-/* MEMC_ARB_1 :: CLIENT_INFO_78 :: BO_VAL [29:12] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_78_BO_VAL_MASK 0x3ffff000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_78_BO_VAL_SHIFT 12
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_78_BO_VAL_DEFAULT 0x00000000
-
-/* MEMC_ARB_1 :: CLIENT_INFO_78 :: reserved1 [11:08] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_78_reserved1_MASK 0x00000f00
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_78_reserved1_SHIFT 8
-
-/* MEMC_ARB_1 :: CLIENT_INFO_78 :: PR_TAG [07:00] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_78_PR_TAG_MASK 0x000000ff
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_78_PR_TAG_SHIFT 0
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_78_PR_TAG_DEFAULT 0x00000000
-
-/***************************************************************************
- *CLIENT_INFO_79 - Client Programming register for client 79.
- ***************************************************************************/
-/* MEMC_ARB_1 :: CLIENT_INFO_79 :: RR_EN [31:31] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_79_RR_EN_MASK 0x80000000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_79_RR_EN_SHIFT 31
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_79_RR_EN_DEFAULT 0x00000001
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_79_RR_EN_DISABLED 0
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_79_RR_EN_ENABLED 1
-
-/* MEMC_ARB_1 :: CLIENT_INFO_79 :: reserved0 [30:30] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_79_reserved0_MASK 0x40000000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_79_reserved0_SHIFT 30
-
-/* MEMC_ARB_1 :: CLIENT_INFO_79 :: BO_VAL [29:12] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_79_BO_VAL_MASK 0x3ffff000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_79_BO_VAL_SHIFT 12
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_79_BO_VAL_DEFAULT 0x00000000
-
-/* MEMC_ARB_1 :: CLIENT_INFO_79 :: reserved1 [11:08] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_79_reserved1_MASK 0x00000f00
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_79_reserved1_SHIFT 8
-
-/* MEMC_ARB_1 :: CLIENT_INFO_79 :: PR_TAG [07:00] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_79_PR_TAG_MASK 0x000000ff
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_79_PR_TAG_SHIFT 0
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_79_PR_TAG_DEFAULT 0x00000000
-
-/***************************************************************************
- *CLIENT_INFO_80 - Client Programming register for client 80.
- ***************************************************************************/
-/* MEMC_ARB_1 :: CLIENT_INFO_80 :: RR_EN [31:31] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_80_RR_EN_MASK 0x80000000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_80_RR_EN_SHIFT 31
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_80_RR_EN_DEFAULT 0x00000001
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_80_RR_EN_DISABLED 0
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_80_RR_EN_ENABLED 1
-
-/* MEMC_ARB_1 :: CLIENT_INFO_80 :: reserved0 [30:30] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_80_reserved0_MASK 0x40000000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_80_reserved0_SHIFT 30
-
-/* MEMC_ARB_1 :: CLIENT_INFO_80 :: BO_VAL [29:12] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_80_BO_VAL_MASK 0x3ffff000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_80_BO_VAL_SHIFT 12
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_80_BO_VAL_DEFAULT 0x00000000
-
-/* MEMC_ARB_1 :: CLIENT_INFO_80 :: reserved1 [11:08] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_80_reserved1_MASK 0x00000f00
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_80_reserved1_SHIFT 8
-
-/* MEMC_ARB_1 :: CLIENT_INFO_80 :: PR_TAG [07:00] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_80_PR_TAG_MASK 0x000000ff
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_80_PR_TAG_SHIFT 0
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_80_PR_TAG_DEFAULT 0x00000000
-
-/***************************************************************************
- *CLIENT_INFO_81 - Client Programming register for client 81.
- ***************************************************************************/
-/* MEMC_ARB_1 :: CLIENT_INFO_81 :: RR_EN [31:31] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_81_RR_EN_MASK 0x80000000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_81_RR_EN_SHIFT 31
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_81_RR_EN_DEFAULT 0x00000001
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_81_RR_EN_DISABLED 0
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_81_RR_EN_ENABLED 1
-
-/* MEMC_ARB_1 :: CLIENT_INFO_81 :: reserved0 [30:30] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_81_reserved0_MASK 0x40000000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_81_reserved0_SHIFT 30
-
-/* MEMC_ARB_1 :: CLIENT_INFO_81 :: BO_VAL [29:12] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_81_BO_VAL_MASK 0x3ffff000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_81_BO_VAL_SHIFT 12
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_81_BO_VAL_DEFAULT 0x00000000
-
-/* MEMC_ARB_1 :: CLIENT_INFO_81 :: reserved1 [11:08] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_81_reserved1_MASK 0x00000f00
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_81_reserved1_SHIFT 8
-
-/* MEMC_ARB_1 :: CLIENT_INFO_81 :: PR_TAG [07:00] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_81_PR_TAG_MASK 0x000000ff
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_81_PR_TAG_SHIFT 0
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_81_PR_TAG_DEFAULT 0x00000000
-
-/***************************************************************************
- *CLIENT_INFO_82 - Client Programming register for client 82.
- ***************************************************************************/
-/* MEMC_ARB_1 :: CLIENT_INFO_82 :: RR_EN [31:31] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_82_RR_EN_MASK 0x80000000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_82_RR_EN_SHIFT 31
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_82_RR_EN_DEFAULT 0x00000001
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_82_RR_EN_DISABLED 0
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_82_RR_EN_ENABLED 1
-
-/* MEMC_ARB_1 :: CLIENT_INFO_82 :: reserved0 [30:30] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_82_reserved0_MASK 0x40000000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_82_reserved0_SHIFT 30
-
-/* MEMC_ARB_1 :: CLIENT_INFO_82 :: BO_VAL [29:12] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_82_BO_VAL_MASK 0x3ffff000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_82_BO_VAL_SHIFT 12
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_82_BO_VAL_DEFAULT 0x00000000
-
-/* MEMC_ARB_1 :: CLIENT_INFO_82 :: reserved1 [11:08] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_82_reserved1_MASK 0x00000f00
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_82_reserved1_SHIFT 8
-
-/* MEMC_ARB_1 :: CLIENT_INFO_82 :: PR_TAG [07:00] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_82_PR_TAG_MASK 0x000000ff
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_82_PR_TAG_SHIFT 0
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_82_PR_TAG_DEFAULT 0x00000000
-
-/***************************************************************************
- *CLIENT_INFO_83 - Client Programming register for client 83.
- ***************************************************************************/
-/* MEMC_ARB_1 :: CLIENT_INFO_83 :: RR_EN [31:31] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_83_RR_EN_MASK 0x80000000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_83_RR_EN_SHIFT 31
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_83_RR_EN_DEFAULT 0x00000001
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_83_RR_EN_DISABLED 0
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_83_RR_EN_ENABLED 1
-
-/* MEMC_ARB_1 :: CLIENT_INFO_83 :: reserved0 [30:30] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_83_reserved0_MASK 0x40000000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_83_reserved0_SHIFT 30
-
-/* MEMC_ARB_1 :: CLIENT_INFO_83 :: BO_VAL [29:12] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_83_BO_VAL_MASK 0x3ffff000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_83_BO_VAL_SHIFT 12
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_83_BO_VAL_DEFAULT 0x00000000
-
-/* MEMC_ARB_1 :: CLIENT_INFO_83 :: reserved1 [11:08] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_83_reserved1_MASK 0x00000f00
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_83_reserved1_SHIFT 8
-
-/* MEMC_ARB_1 :: CLIENT_INFO_83 :: PR_TAG [07:00] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_83_PR_TAG_MASK 0x000000ff
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_83_PR_TAG_SHIFT 0
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_83_PR_TAG_DEFAULT 0x00000000
-
-/***************************************************************************
- *CLIENT_INFO_84 - Client Programming register for client 84.
- ***************************************************************************/
-/* MEMC_ARB_1 :: CLIENT_INFO_84 :: RR_EN [31:31] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_84_RR_EN_MASK 0x80000000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_84_RR_EN_SHIFT 31
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_84_RR_EN_DEFAULT 0x00000001
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_84_RR_EN_DISABLED 0
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_84_RR_EN_ENABLED 1
-
-/* MEMC_ARB_1 :: CLIENT_INFO_84 :: reserved0 [30:30] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_84_reserved0_MASK 0x40000000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_84_reserved0_SHIFT 30
-
-/* MEMC_ARB_1 :: CLIENT_INFO_84 :: BO_VAL [29:12] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_84_BO_VAL_MASK 0x3ffff000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_84_BO_VAL_SHIFT 12
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_84_BO_VAL_DEFAULT 0x00000000
-
-/* MEMC_ARB_1 :: CLIENT_INFO_84 :: reserved1 [11:08] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_84_reserved1_MASK 0x00000f00
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_84_reserved1_SHIFT 8
-
-/* MEMC_ARB_1 :: CLIENT_INFO_84 :: PR_TAG [07:00] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_84_PR_TAG_MASK 0x000000ff
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_84_PR_TAG_SHIFT 0
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_84_PR_TAG_DEFAULT 0x00000000
-
-/***************************************************************************
- *CLIENT_INFO_85 - Client Programming register for client 85.
- ***************************************************************************/
-/* MEMC_ARB_1 :: CLIENT_INFO_85 :: RR_EN [31:31] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_85_RR_EN_MASK 0x80000000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_85_RR_EN_SHIFT 31
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_85_RR_EN_DEFAULT 0x00000001
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_85_RR_EN_DISABLED 0
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_85_RR_EN_ENABLED 1
-
-/* MEMC_ARB_1 :: CLIENT_INFO_85 :: reserved0 [30:30] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_85_reserved0_MASK 0x40000000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_85_reserved0_SHIFT 30
-
-/* MEMC_ARB_1 :: CLIENT_INFO_85 :: BO_VAL [29:12] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_85_BO_VAL_MASK 0x3ffff000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_85_BO_VAL_SHIFT 12
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_85_BO_VAL_DEFAULT 0x00000000
-
-/* MEMC_ARB_1 :: CLIENT_INFO_85 :: reserved1 [11:08] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_85_reserved1_MASK 0x00000f00
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_85_reserved1_SHIFT 8
-
-/* MEMC_ARB_1 :: CLIENT_INFO_85 :: PR_TAG [07:00] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_85_PR_TAG_MASK 0x000000ff
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_85_PR_TAG_SHIFT 0
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_85_PR_TAG_DEFAULT 0x00000000
-
-/***************************************************************************
- *CLIENT_INFO_86 - Client Programming register for client 86.
- ***************************************************************************/
-/* MEMC_ARB_1 :: CLIENT_INFO_86 :: RR_EN [31:31] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_86_RR_EN_MASK 0x80000000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_86_RR_EN_SHIFT 31
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_86_RR_EN_DEFAULT 0x00000001
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_86_RR_EN_DISABLED 0
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_86_RR_EN_ENABLED 1
-
-/* MEMC_ARB_1 :: CLIENT_INFO_86 :: reserved0 [30:30] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_86_reserved0_MASK 0x40000000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_86_reserved0_SHIFT 30
-
-/* MEMC_ARB_1 :: CLIENT_INFO_86 :: BO_VAL [29:12] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_86_BO_VAL_MASK 0x3ffff000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_86_BO_VAL_SHIFT 12
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_86_BO_VAL_DEFAULT 0x00000000
-
-/* MEMC_ARB_1 :: CLIENT_INFO_86 :: reserved1 [11:08] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_86_reserved1_MASK 0x00000f00
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_86_reserved1_SHIFT 8
-
-/* MEMC_ARB_1 :: CLIENT_INFO_86 :: PR_TAG [07:00] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_86_PR_TAG_MASK 0x000000ff
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_86_PR_TAG_SHIFT 0
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_86_PR_TAG_DEFAULT 0x00000000
-
-/***************************************************************************
- *CLIENT_INFO_87 - Client Programming register for client 87.
- ***************************************************************************/
-/* MEMC_ARB_1 :: CLIENT_INFO_87 :: RR_EN [31:31] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_87_RR_EN_MASK 0x80000000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_87_RR_EN_SHIFT 31
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_87_RR_EN_DEFAULT 0x00000001
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_87_RR_EN_DISABLED 0
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_87_RR_EN_ENABLED 1
-
-/* MEMC_ARB_1 :: CLIENT_INFO_87 :: reserved0 [30:30] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_87_reserved0_MASK 0x40000000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_87_reserved0_SHIFT 30
-
-/* MEMC_ARB_1 :: CLIENT_INFO_87 :: BO_VAL [29:12] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_87_BO_VAL_MASK 0x3ffff000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_87_BO_VAL_SHIFT 12
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_87_BO_VAL_DEFAULT 0x00000000
-
-/* MEMC_ARB_1 :: CLIENT_INFO_87 :: reserved1 [11:08] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_87_reserved1_MASK 0x00000f00
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_87_reserved1_SHIFT 8
-
-/* MEMC_ARB_1 :: CLIENT_INFO_87 :: PR_TAG [07:00] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_87_PR_TAG_MASK 0x000000ff
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_87_PR_TAG_SHIFT 0
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_87_PR_TAG_DEFAULT 0x00000000
-
-/***************************************************************************
- *CLIENT_INFO_88 - Client Programming register for client 88.
- ***************************************************************************/
-/* MEMC_ARB_1 :: CLIENT_INFO_88 :: RR_EN [31:31] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_88_RR_EN_MASK 0x80000000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_88_RR_EN_SHIFT 31
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_88_RR_EN_DEFAULT 0x00000001
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_88_RR_EN_DISABLED 0
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_88_RR_EN_ENABLED 1
-
-/* MEMC_ARB_1 :: CLIENT_INFO_88 :: reserved0 [30:30] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_88_reserved0_MASK 0x40000000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_88_reserved0_SHIFT 30
-
-/* MEMC_ARB_1 :: CLIENT_INFO_88 :: BO_VAL [29:12] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_88_BO_VAL_MASK 0x3ffff000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_88_BO_VAL_SHIFT 12
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_88_BO_VAL_DEFAULT 0x00000000
-
-/* MEMC_ARB_1 :: CLIENT_INFO_88 :: reserved1 [11:08] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_88_reserved1_MASK 0x00000f00
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_88_reserved1_SHIFT 8
-
-/* MEMC_ARB_1 :: CLIENT_INFO_88 :: PR_TAG [07:00] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_88_PR_TAG_MASK 0x000000ff
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_88_PR_TAG_SHIFT 0
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_88_PR_TAG_DEFAULT 0x00000000
-
-/***************************************************************************
- *CLIENT_INFO_89 - Client Programming register for client 89.
- ***************************************************************************/
-/* MEMC_ARB_1 :: CLIENT_INFO_89 :: RR_EN [31:31] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_89_RR_EN_MASK 0x80000000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_89_RR_EN_SHIFT 31
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_89_RR_EN_DEFAULT 0x00000001
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_89_RR_EN_DISABLED 0
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_89_RR_EN_ENABLED 1
-
-/* MEMC_ARB_1 :: CLIENT_INFO_89 :: reserved0 [30:30] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_89_reserved0_MASK 0x40000000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_89_reserved0_SHIFT 30
-
-/* MEMC_ARB_1 :: CLIENT_INFO_89 :: BO_VAL [29:12] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_89_BO_VAL_MASK 0x3ffff000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_89_BO_VAL_SHIFT 12
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_89_BO_VAL_DEFAULT 0x00000000
-
-/* MEMC_ARB_1 :: CLIENT_INFO_89 :: reserved1 [11:08] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_89_reserved1_MASK 0x00000f00
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_89_reserved1_SHIFT 8
-
-/* MEMC_ARB_1 :: CLIENT_INFO_89 :: PR_TAG [07:00] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_89_PR_TAG_MASK 0x000000ff
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_89_PR_TAG_SHIFT 0
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_89_PR_TAG_DEFAULT 0x00000000
-
-/***************************************************************************
- *CLIENT_INFO_90 - Client Programming register for client 90.
- ***************************************************************************/
-/* MEMC_ARB_1 :: CLIENT_INFO_90 :: RR_EN [31:31] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_90_RR_EN_MASK 0x80000000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_90_RR_EN_SHIFT 31
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_90_RR_EN_DEFAULT 0x00000001
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_90_RR_EN_DISABLED 0
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_90_RR_EN_ENABLED 1
-
-/* MEMC_ARB_1 :: CLIENT_INFO_90 :: reserved0 [30:30] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_90_reserved0_MASK 0x40000000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_90_reserved0_SHIFT 30
-
-/* MEMC_ARB_1 :: CLIENT_INFO_90 :: BO_VAL [29:12] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_90_BO_VAL_MASK 0x3ffff000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_90_BO_VAL_SHIFT 12
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_90_BO_VAL_DEFAULT 0x00000000
-
-/* MEMC_ARB_1 :: CLIENT_INFO_90 :: reserved1 [11:08] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_90_reserved1_MASK 0x00000f00
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_90_reserved1_SHIFT 8
-
-/* MEMC_ARB_1 :: CLIENT_INFO_90 :: PR_TAG [07:00] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_90_PR_TAG_MASK 0x000000ff
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_90_PR_TAG_SHIFT 0
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_90_PR_TAG_DEFAULT 0x00000000
-
-/***************************************************************************
- *CLIENT_INFO_91 - Client Programming register for client 91.
- ***************************************************************************/
-/* MEMC_ARB_1 :: CLIENT_INFO_91 :: RR_EN [31:31] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_91_RR_EN_MASK 0x80000000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_91_RR_EN_SHIFT 31
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_91_RR_EN_DEFAULT 0x00000001
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_91_RR_EN_DISABLED 0
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_91_RR_EN_ENABLED 1
-
-/* MEMC_ARB_1 :: CLIENT_INFO_91 :: reserved0 [30:30] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_91_reserved0_MASK 0x40000000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_91_reserved0_SHIFT 30
-
-/* MEMC_ARB_1 :: CLIENT_INFO_91 :: BO_VAL [29:12] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_91_BO_VAL_MASK 0x3ffff000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_91_BO_VAL_SHIFT 12
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_91_BO_VAL_DEFAULT 0x00000000
-
-/* MEMC_ARB_1 :: CLIENT_INFO_91 :: reserved1 [11:08] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_91_reserved1_MASK 0x00000f00
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_91_reserved1_SHIFT 8
-
-/* MEMC_ARB_1 :: CLIENT_INFO_91 :: PR_TAG [07:00] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_91_PR_TAG_MASK 0x000000ff
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_91_PR_TAG_SHIFT 0
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_91_PR_TAG_DEFAULT 0x00000000
-
-/***************************************************************************
- *CLIENT_INFO_92 - Client Programming register for client 92.
- ***************************************************************************/
-/* MEMC_ARB_1 :: CLIENT_INFO_92 :: RR_EN [31:31] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_92_RR_EN_MASK 0x80000000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_92_RR_EN_SHIFT 31
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_92_RR_EN_DEFAULT 0x00000001
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_92_RR_EN_DISABLED 0
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_92_RR_EN_ENABLED 1
-
-/* MEMC_ARB_1 :: CLIENT_INFO_92 :: reserved0 [30:30] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_92_reserved0_MASK 0x40000000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_92_reserved0_SHIFT 30
-
-/* MEMC_ARB_1 :: CLIENT_INFO_92 :: BO_VAL [29:12] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_92_BO_VAL_MASK 0x3ffff000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_92_BO_VAL_SHIFT 12
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_92_BO_VAL_DEFAULT 0x00000000
-
-/* MEMC_ARB_1 :: CLIENT_INFO_92 :: reserved1 [11:08] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_92_reserved1_MASK 0x00000f00
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_92_reserved1_SHIFT 8
-
-/* MEMC_ARB_1 :: CLIENT_INFO_92 :: PR_TAG [07:00] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_92_PR_TAG_MASK 0x000000ff
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_92_PR_TAG_SHIFT 0
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_92_PR_TAG_DEFAULT 0x00000000
-
-/***************************************************************************
- *CLIENT_INFO_93 - Client Programming register for client 93.
- ***************************************************************************/
-/* MEMC_ARB_1 :: CLIENT_INFO_93 :: RR_EN [31:31] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_93_RR_EN_MASK 0x80000000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_93_RR_EN_SHIFT 31
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_93_RR_EN_DEFAULT 0x00000001
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_93_RR_EN_DISABLED 0
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_93_RR_EN_ENABLED 1
-
-/* MEMC_ARB_1 :: CLIENT_INFO_93 :: reserved0 [30:30] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_93_reserved0_MASK 0x40000000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_93_reserved0_SHIFT 30
-
-/* MEMC_ARB_1 :: CLIENT_INFO_93 :: BO_VAL [29:12] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_93_BO_VAL_MASK 0x3ffff000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_93_BO_VAL_SHIFT 12
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_93_BO_VAL_DEFAULT 0x00000000
-
-/* MEMC_ARB_1 :: CLIENT_INFO_93 :: reserved1 [11:08] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_93_reserved1_MASK 0x00000f00
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_93_reserved1_SHIFT 8
-
-/* MEMC_ARB_1 :: CLIENT_INFO_93 :: PR_TAG [07:00] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_93_PR_TAG_MASK 0x000000ff
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_93_PR_TAG_SHIFT 0
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_93_PR_TAG_DEFAULT 0x00000000
-
-/***************************************************************************
- *CLIENT_INFO_94 - Client Programming register for client 94.
- ***************************************************************************/
-/* MEMC_ARB_1 :: CLIENT_INFO_94 :: RR_EN [31:31] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_94_RR_EN_MASK 0x80000000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_94_RR_EN_SHIFT 31
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_94_RR_EN_DEFAULT 0x00000001
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_94_RR_EN_DISABLED 0
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_94_RR_EN_ENABLED 1
-
-/* MEMC_ARB_1 :: CLIENT_INFO_94 :: reserved0 [30:30] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_94_reserved0_MASK 0x40000000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_94_reserved0_SHIFT 30
-
-/* MEMC_ARB_1 :: CLIENT_INFO_94 :: BO_VAL [29:12] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_94_BO_VAL_MASK 0x3ffff000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_94_BO_VAL_SHIFT 12
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_94_BO_VAL_DEFAULT 0x00000000
-
-/* MEMC_ARB_1 :: CLIENT_INFO_94 :: reserved1 [11:08] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_94_reserved1_MASK 0x00000f00
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_94_reserved1_SHIFT 8
-
-/* MEMC_ARB_1 :: CLIENT_INFO_94 :: PR_TAG [07:00] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_94_PR_TAG_MASK 0x000000ff
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_94_PR_TAG_SHIFT 0
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_94_PR_TAG_DEFAULT 0x00000000
-
-/***************************************************************************
- *CLIENT_INFO_95 - Client Programming register for client 95.
- ***************************************************************************/
-/* MEMC_ARB_1 :: CLIENT_INFO_95 :: RR_EN [31:31] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_95_RR_EN_MASK 0x80000000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_95_RR_EN_SHIFT 31
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_95_RR_EN_DEFAULT 0x00000001
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_95_RR_EN_DISABLED 0
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_95_RR_EN_ENABLED 1
-
-/* MEMC_ARB_1 :: CLIENT_INFO_95 :: reserved0 [30:30] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_95_reserved0_MASK 0x40000000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_95_reserved0_SHIFT 30
-
-/* MEMC_ARB_1 :: CLIENT_INFO_95 :: BO_VAL [29:12] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_95_BO_VAL_MASK 0x3ffff000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_95_BO_VAL_SHIFT 12
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_95_BO_VAL_DEFAULT 0x00000000
-
-/* MEMC_ARB_1 :: CLIENT_INFO_95 :: reserved1 [11:08] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_95_reserved1_MASK 0x00000f00
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_95_reserved1_SHIFT 8
-
-/* MEMC_ARB_1 :: CLIENT_INFO_95 :: PR_TAG [07:00] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_95_PR_TAG_MASK 0x000000ff
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_95_PR_TAG_SHIFT 0
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_95_PR_TAG_DEFAULT 0x00000000
-
-/***************************************************************************
- *CLIENT_INFO_96 - Client Programming register for client 96.
- ***************************************************************************/
-/* MEMC_ARB_1 :: CLIENT_INFO_96 :: RR_EN [31:31] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_96_RR_EN_MASK 0x80000000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_96_RR_EN_SHIFT 31
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_96_RR_EN_DEFAULT 0x00000001
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_96_RR_EN_DISABLED 0
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_96_RR_EN_ENABLED 1
-
-/* MEMC_ARB_1 :: CLIENT_INFO_96 :: reserved0 [30:30] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_96_reserved0_MASK 0x40000000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_96_reserved0_SHIFT 30
-
-/* MEMC_ARB_1 :: CLIENT_INFO_96 :: BO_VAL [29:12] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_96_BO_VAL_MASK 0x3ffff000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_96_BO_VAL_SHIFT 12
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_96_BO_VAL_DEFAULT 0x00000000
-
-/* MEMC_ARB_1 :: CLIENT_INFO_96 :: reserved1 [11:08] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_96_reserved1_MASK 0x00000f00
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_96_reserved1_SHIFT 8
-
-/* MEMC_ARB_1 :: CLIENT_INFO_96 :: PR_TAG [07:00] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_96_PR_TAG_MASK 0x000000ff
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_96_PR_TAG_SHIFT 0
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_96_PR_TAG_DEFAULT 0x00000000
-
-/***************************************************************************
- *CLIENT_INFO_97 - Client Programming register for client 97.
- ***************************************************************************/
-/* MEMC_ARB_1 :: CLIENT_INFO_97 :: RR_EN [31:31] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_97_RR_EN_MASK 0x80000000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_97_RR_EN_SHIFT 31
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_97_RR_EN_DEFAULT 0x00000001
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_97_RR_EN_DISABLED 0
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_97_RR_EN_ENABLED 1
-
-/* MEMC_ARB_1 :: CLIENT_INFO_97 :: reserved0 [30:30] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_97_reserved0_MASK 0x40000000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_97_reserved0_SHIFT 30
-
-/* MEMC_ARB_1 :: CLIENT_INFO_97 :: BO_VAL [29:12] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_97_BO_VAL_MASK 0x3ffff000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_97_BO_VAL_SHIFT 12
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_97_BO_VAL_DEFAULT 0x00000000
-
-/* MEMC_ARB_1 :: CLIENT_INFO_97 :: reserved1 [11:08] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_97_reserved1_MASK 0x00000f00
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_97_reserved1_SHIFT 8
-
-/* MEMC_ARB_1 :: CLIENT_INFO_97 :: PR_TAG [07:00] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_97_PR_TAG_MASK 0x000000ff
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_97_PR_TAG_SHIFT 0
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_97_PR_TAG_DEFAULT 0x00000000
-
-/***************************************************************************
- *CLIENT_INFO_98 - Client Programming register for client 98.
- ***************************************************************************/
-/* MEMC_ARB_1 :: CLIENT_INFO_98 :: RR_EN [31:31] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_98_RR_EN_MASK 0x80000000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_98_RR_EN_SHIFT 31
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_98_RR_EN_DEFAULT 0x00000001
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_98_RR_EN_DISABLED 0
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_98_RR_EN_ENABLED 1
-
-/* MEMC_ARB_1 :: CLIENT_INFO_98 :: reserved0 [30:30] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_98_reserved0_MASK 0x40000000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_98_reserved0_SHIFT 30
-
-/* MEMC_ARB_1 :: CLIENT_INFO_98 :: BO_VAL [29:12] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_98_BO_VAL_MASK 0x3ffff000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_98_BO_VAL_SHIFT 12
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_98_BO_VAL_DEFAULT 0x00000000
-
-/* MEMC_ARB_1 :: CLIENT_INFO_98 :: reserved1 [11:08] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_98_reserved1_MASK 0x00000f00
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_98_reserved1_SHIFT 8
-
-/* MEMC_ARB_1 :: CLIENT_INFO_98 :: PR_TAG [07:00] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_98_PR_TAG_MASK 0x000000ff
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_98_PR_TAG_SHIFT 0
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_98_PR_TAG_DEFAULT 0x00000000
-
-/***************************************************************************
- *CLIENT_INFO_99 - Client Programming register for client 99.
- ***************************************************************************/
-/* MEMC_ARB_1 :: CLIENT_INFO_99 :: RR_EN [31:31] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_99_RR_EN_MASK 0x80000000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_99_RR_EN_SHIFT 31
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_99_RR_EN_DEFAULT 0x00000001
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_99_RR_EN_DISABLED 0
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_99_RR_EN_ENABLED 1
-
-/* MEMC_ARB_1 :: CLIENT_INFO_99 :: reserved0 [30:30] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_99_reserved0_MASK 0x40000000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_99_reserved0_SHIFT 30
-
-/* MEMC_ARB_1 :: CLIENT_INFO_99 :: BO_VAL [29:12] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_99_BO_VAL_MASK 0x3ffff000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_99_BO_VAL_SHIFT 12
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_99_BO_VAL_DEFAULT 0x00000000
-
-/* MEMC_ARB_1 :: CLIENT_INFO_99 :: reserved1 [11:08] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_99_reserved1_MASK 0x00000f00
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_99_reserved1_SHIFT 8
-
-/* MEMC_ARB_1 :: CLIENT_INFO_99 :: PR_TAG [07:00] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_99_PR_TAG_MASK 0x000000ff
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_99_PR_TAG_SHIFT 0
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_99_PR_TAG_DEFAULT 0x00000000
-
-/***************************************************************************
- *CLIENT_INFO_100 - Client Programming register for client 100.
- ***************************************************************************/
-/* MEMC_ARB_1 :: CLIENT_INFO_100 :: RR_EN [31:31] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_100_RR_EN_MASK 0x80000000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_100_RR_EN_SHIFT 31
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_100_RR_EN_DEFAULT 0x00000001
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_100_RR_EN_DISABLED 0
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_100_RR_EN_ENABLED 1
-
-/* MEMC_ARB_1 :: CLIENT_INFO_100 :: reserved0 [30:30] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_100_reserved0_MASK 0x40000000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_100_reserved0_SHIFT 30
-
-/* MEMC_ARB_1 :: CLIENT_INFO_100 :: BO_VAL [29:12] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_100_BO_VAL_MASK 0x3ffff000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_100_BO_VAL_SHIFT 12
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_100_BO_VAL_DEFAULT 0x00000000
-
-/* MEMC_ARB_1 :: CLIENT_INFO_100 :: reserved1 [11:08] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_100_reserved1_MASK 0x00000f00
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_100_reserved1_SHIFT 8
-
-/* MEMC_ARB_1 :: CLIENT_INFO_100 :: PR_TAG [07:00] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_100_PR_TAG_MASK 0x000000ff
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_100_PR_TAG_SHIFT 0
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_100_PR_TAG_DEFAULT 0x00000000
-
-/***************************************************************************
- *CLIENT_INFO_101 - Client Programming register for client 101.
- ***************************************************************************/
-/* MEMC_ARB_1 :: CLIENT_INFO_101 :: RR_EN [31:31] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_101_RR_EN_MASK 0x80000000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_101_RR_EN_SHIFT 31
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_101_RR_EN_DEFAULT 0x00000001
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_101_RR_EN_DISABLED 0
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_101_RR_EN_ENABLED 1
-
-/* MEMC_ARB_1 :: CLIENT_INFO_101 :: reserved0 [30:30] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_101_reserved0_MASK 0x40000000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_101_reserved0_SHIFT 30
-
-/* MEMC_ARB_1 :: CLIENT_INFO_101 :: BO_VAL [29:12] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_101_BO_VAL_MASK 0x3ffff000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_101_BO_VAL_SHIFT 12
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_101_BO_VAL_DEFAULT 0x00000000
-
-/* MEMC_ARB_1 :: CLIENT_INFO_101 :: reserved1 [11:08] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_101_reserved1_MASK 0x00000f00
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_101_reserved1_SHIFT 8
-
-/* MEMC_ARB_1 :: CLIENT_INFO_101 :: PR_TAG [07:00] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_101_PR_TAG_MASK 0x000000ff
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_101_PR_TAG_SHIFT 0
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_101_PR_TAG_DEFAULT 0x00000000
-
-/***************************************************************************
- *CLIENT_INFO_102 - Client Programming register for client 102.
- ***************************************************************************/
-/* MEMC_ARB_1 :: CLIENT_INFO_102 :: RR_EN [31:31] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_102_RR_EN_MASK 0x80000000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_102_RR_EN_SHIFT 31
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_102_RR_EN_DEFAULT 0x00000001
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_102_RR_EN_DISABLED 0
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_102_RR_EN_ENABLED 1
-
-/* MEMC_ARB_1 :: CLIENT_INFO_102 :: reserved0 [30:30] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_102_reserved0_MASK 0x40000000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_102_reserved0_SHIFT 30
-
-/* MEMC_ARB_1 :: CLIENT_INFO_102 :: BO_VAL [29:12] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_102_BO_VAL_MASK 0x3ffff000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_102_BO_VAL_SHIFT 12
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_102_BO_VAL_DEFAULT 0x00000000
-
-/* MEMC_ARB_1 :: CLIENT_INFO_102 :: reserved1 [11:08] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_102_reserved1_MASK 0x00000f00
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_102_reserved1_SHIFT 8
-
-/* MEMC_ARB_1 :: CLIENT_INFO_102 :: PR_TAG [07:00] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_102_PR_TAG_MASK 0x000000ff
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_102_PR_TAG_SHIFT 0
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_102_PR_TAG_DEFAULT 0x00000000
-
-/***************************************************************************
- *CLIENT_INFO_103 - Client Programming register for client 103.
- ***************************************************************************/
-/* MEMC_ARB_1 :: CLIENT_INFO_103 :: RR_EN [31:31] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_103_RR_EN_MASK 0x80000000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_103_RR_EN_SHIFT 31
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_103_RR_EN_DEFAULT 0x00000001
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_103_RR_EN_DISABLED 0
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_103_RR_EN_ENABLED 1
-
-/* MEMC_ARB_1 :: CLIENT_INFO_103 :: reserved0 [30:30] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_103_reserved0_MASK 0x40000000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_103_reserved0_SHIFT 30
-
-/* MEMC_ARB_1 :: CLIENT_INFO_103 :: BO_VAL [29:12] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_103_BO_VAL_MASK 0x3ffff000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_103_BO_VAL_SHIFT 12
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_103_BO_VAL_DEFAULT 0x00000000
-
-/* MEMC_ARB_1 :: CLIENT_INFO_103 :: reserved1 [11:08] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_103_reserved1_MASK 0x00000f00
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_103_reserved1_SHIFT 8
-
-/* MEMC_ARB_1 :: CLIENT_INFO_103 :: PR_TAG [07:00] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_103_PR_TAG_MASK 0x000000ff
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_103_PR_TAG_SHIFT 0
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_103_PR_TAG_DEFAULT 0x00000000
-
-/***************************************************************************
- *CLIENT_INFO_104 - Client Programming register for client 104.
- ***************************************************************************/
-/* MEMC_ARB_1 :: CLIENT_INFO_104 :: RR_EN [31:31] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_104_RR_EN_MASK 0x80000000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_104_RR_EN_SHIFT 31
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_104_RR_EN_DEFAULT 0x00000001
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_104_RR_EN_DISABLED 0
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_104_RR_EN_ENABLED 1
-
-/* MEMC_ARB_1 :: CLIENT_INFO_104 :: reserved0 [30:30] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_104_reserved0_MASK 0x40000000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_104_reserved0_SHIFT 30
-
-/* MEMC_ARB_1 :: CLIENT_INFO_104 :: BO_VAL [29:12] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_104_BO_VAL_MASK 0x3ffff000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_104_BO_VAL_SHIFT 12
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_104_BO_VAL_DEFAULT 0x00000000
-
-/* MEMC_ARB_1 :: CLIENT_INFO_104 :: reserved1 [11:08] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_104_reserved1_MASK 0x00000f00
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_104_reserved1_SHIFT 8
-
-/* MEMC_ARB_1 :: CLIENT_INFO_104 :: PR_TAG [07:00] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_104_PR_TAG_MASK 0x000000ff
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_104_PR_TAG_SHIFT 0
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_104_PR_TAG_DEFAULT 0x00000000
-
-/***************************************************************************
- *CLIENT_INFO_105 - Client Programming register for client 105.
- ***************************************************************************/
-/* MEMC_ARB_1 :: CLIENT_INFO_105 :: RR_EN [31:31] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_105_RR_EN_MASK 0x80000000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_105_RR_EN_SHIFT 31
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_105_RR_EN_DEFAULT 0x00000001
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_105_RR_EN_DISABLED 0
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_105_RR_EN_ENABLED 1
-
-/* MEMC_ARB_1 :: CLIENT_INFO_105 :: reserved0 [30:30] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_105_reserved0_MASK 0x40000000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_105_reserved0_SHIFT 30
-
-/* MEMC_ARB_1 :: CLIENT_INFO_105 :: BO_VAL [29:12] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_105_BO_VAL_MASK 0x3ffff000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_105_BO_VAL_SHIFT 12
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_105_BO_VAL_DEFAULT 0x00000000
-
-/* MEMC_ARB_1 :: CLIENT_INFO_105 :: reserved1 [11:08] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_105_reserved1_MASK 0x00000f00
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_105_reserved1_SHIFT 8
-
-/* MEMC_ARB_1 :: CLIENT_INFO_105 :: PR_TAG [07:00] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_105_PR_TAG_MASK 0x000000ff
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_105_PR_TAG_SHIFT 0
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_105_PR_TAG_DEFAULT 0x00000000
-
-/***************************************************************************
- *CLIENT_INFO_106 - Client Programming register for client 106.
- ***************************************************************************/
-/* MEMC_ARB_1 :: CLIENT_INFO_106 :: RR_EN [31:31] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_106_RR_EN_MASK 0x80000000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_106_RR_EN_SHIFT 31
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_106_RR_EN_DEFAULT 0x00000001
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_106_RR_EN_DISABLED 0
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_106_RR_EN_ENABLED 1
-
-/* MEMC_ARB_1 :: CLIENT_INFO_106 :: reserved0 [30:30] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_106_reserved0_MASK 0x40000000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_106_reserved0_SHIFT 30
-
-/* MEMC_ARB_1 :: CLIENT_INFO_106 :: BO_VAL [29:12] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_106_BO_VAL_MASK 0x3ffff000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_106_BO_VAL_SHIFT 12
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_106_BO_VAL_DEFAULT 0x00000000
-
-/* MEMC_ARB_1 :: CLIENT_INFO_106 :: reserved1 [11:08] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_106_reserved1_MASK 0x00000f00
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_106_reserved1_SHIFT 8
-
-/* MEMC_ARB_1 :: CLIENT_INFO_106 :: PR_TAG [07:00] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_106_PR_TAG_MASK 0x000000ff
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_106_PR_TAG_SHIFT 0
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_106_PR_TAG_DEFAULT 0x00000000
-
-/***************************************************************************
- *CLIENT_INFO_107 - Client Programming register for client 107.
- ***************************************************************************/
-/* MEMC_ARB_1 :: CLIENT_INFO_107 :: RR_EN [31:31] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_107_RR_EN_MASK 0x80000000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_107_RR_EN_SHIFT 31
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_107_RR_EN_DEFAULT 0x00000001
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_107_RR_EN_DISABLED 0
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_107_RR_EN_ENABLED 1
-
-/* MEMC_ARB_1 :: CLIENT_INFO_107 :: reserved0 [30:30] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_107_reserved0_MASK 0x40000000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_107_reserved0_SHIFT 30
-
-/* MEMC_ARB_1 :: CLIENT_INFO_107 :: BO_VAL [29:12] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_107_BO_VAL_MASK 0x3ffff000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_107_BO_VAL_SHIFT 12
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_107_BO_VAL_DEFAULT 0x00000000
-
-/* MEMC_ARB_1 :: CLIENT_INFO_107 :: reserved1 [11:08] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_107_reserved1_MASK 0x00000f00
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_107_reserved1_SHIFT 8
-
-/* MEMC_ARB_1 :: CLIENT_INFO_107 :: PR_TAG [07:00] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_107_PR_TAG_MASK 0x000000ff
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_107_PR_TAG_SHIFT 0
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_107_PR_TAG_DEFAULT 0x00000000
-
-/***************************************************************************
- *CLIENT_INFO_108 - Client Programming register for client 108.
- ***************************************************************************/
-/* MEMC_ARB_1 :: CLIENT_INFO_108 :: RR_EN [31:31] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_108_RR_EN_MASK 0x80000000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_108_RR_EN_SHIFT 31
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_108_RR_EN_DEFAULT 0x00000001
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_108_RR_EN_DISABLED 0
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_108_RR_EN_ENABLED 1
-
-/* MEMC_ARB_1 :: CLIENT_INFO_108 :: reserved0 [30:30] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_108_reserved0_MASK 0x40000000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_108_reserved0_SHIFT 30
-
-/* MEMC_ARB_1 :: CLIENT_INFO_108 :: BO_VAL [29:12] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_108_BO_VAL_MASK 0x3ffff000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_108_BO_VAL_SHIFT 12
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_108_BO_VAL_DEFAULT 0x00000000
-
-/* MEMC_ARB_1 :: CLIENT_INFO_108 :: reserved1 [11:08] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_108_reserved1_MASK 0x00000f00
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_108_reserved1_SHIFT 8
-
-/* MEMC_ARB_1 :: CLIENT_INFO_108 :: PR_TAG [07:00] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_108_PR_TAG_MASK 0x000000ff
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_108_PR_TAG_SHIFT 0
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_108_PR_TAG_DEFAULT 0x00000000
-
-/***************************************************************************
- *CLIENT_INFO_109 - Client Programming register for client 109.
- ***************************************************************************/
-/* MEMC_ARB_1 :: CLIENT_INFO_109 :: RR_EN [31:31] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_109_RR_EN_MASK 0x80000000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_109_RR_EN_SHIFT 31
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_109_RR_EN_DEFAULT 0x00000001
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_109_RR_EN_DISABLED 0
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_109_RR_EN_ENABLED 1
-
-/* MEMC_ARB_1 :: CLIENT_INFO_109 :: reserved0 [30:30] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_109_reserved0_MASK 0x40000000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_109_reserved0_SHIFT 30
-
-/* MEMC_ARB_1 :: CLIENT_INFO_109 :: BO_VAL [29:12] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_109_BO_VAL_MASK 0x3ffff000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_109_BO_VAL_SHIFT 12
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_109_BO_VAL_DEFAULT 0x00000000
-
-/* MEMC_ARB_1 :: CLIENT_INFO_109 :: reserved1 [11:08] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_109_reserved1_MASK 0x00000f00
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_109_reserved1_SHIFT 8
-
-/* MEMC_ARB_1 :: CLIENT_INFO_109 :: PR_TAG [07:00] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_109_PR_TAG_MASK 0x000000ff
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_109_PR_TAG_SHIFT 0
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_109_PR_TAG_DEFAULT 0x00000000
-
-/***************************************************************************
- *CLIENT_INFO_110 - Client Programming register for client 110.
- ***************************************************************************/
-/* MEMC_ARB_1 :: CLIENT_INFO_110 :: RR_EN [31:31] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_110_RR_EN_MASK 0x80000000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_110_RR_EN_SHIFT 31
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_110_RR_EN_DEFAULT 0x00000001
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_110_RR_EN_DISABLED 0
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_110_RR_EN_ENABLED 1
-
-/* MEMC_ARB_1 :: CLIENT_INFO_110 :: reserved0 [30:30] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_110_reserved0_MASK 0x40000000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_110_reserved0_SHIFT 30
-
-/* MEMC_ARB_1 :: CLIENT_INFO_110 :: BO_VAL [29:12] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_110_BO_VAL_MASK 0x3ffff000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_110_BO_VAL_SHIFT 12
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_110_BO_VAL_DEFAULT 0x00000000
-
-/* MEMC_ARB_1 :: CLIENT_INFO_110 :: reserved1 [11:08] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_110_reserved1_MASK 0x00000f00
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_110_reserved1_SHIFT 8
-
-/* MEMC_ARB_1 :: CLIENT_INFO_110 :: PR_TAG [07:00] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_110_PR_TAG_MASK 0x000000ff
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_110_PR_TAG_SHIFT 0
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_110_PR_TAG_DEFAULT 0x00000000
-
-/***************************************************************************
- *CLIENT_INFO_111 - Client Programming register for client 111.
- ***************************************************************************/
-/* MEMC_ARB_1 :: CLIENT_INFO_111 :: RR_EN [31:31] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_111_RR_EN_MASK 0x80000000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_111_RR_EN_SHIFT 31
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_111_RR_EN_DEFAULT 0x00000001
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_111_RR_EN_DISABLED 0
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_111_RR_EN_ENABLED 1
-
-/* MEMC_ARB_1 :: CLIENT_INFO_111 :: reserved0 [30:30] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_111_reserved0_MASK 0x40000000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_111_reserved0_SHIFT 30
-
-/* MEMC_ARB_1 :: CLIENT_INFO_111 :: BO_VAL [29:12] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_111_BO_VAL_MASK 0x3ffff000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_111_BO_VAL_SHIFT 12
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_111_BO_VAL_DEFAULT 0x00000000
-
-/* MEMC_ARB_1 :: CLIENT_INFO_111 :: reserved1 [11:08] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_111_reserved1_MASK 0x00000f00
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_111_reserved1_SHIFT 8
-
-/* MEMC_ARB_1 :: CLIENT_INFO_111 :: PR_TAG [07:00] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_111_PR_TAG_MASK 0x000000ff
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_111_PR_TAG_SHIFT 0
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_111_PR_TAG_DEFAULT 0x00000000
-
-/***************************************************************************
- *CLIENT_INFO_112 - Client Programming register for client 112.
- ***************************************************************************/
-/* MEMC_ARB_1 :: CLIENT_INFO_112 :: RR_EN [31:31] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_112_RR_EN_MASK 0x80000000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_112_RR_EN_SHIFT 31
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_112_RR_EN_DEFAULT 0x00000001
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_112_RR_EN_DISABLED 0
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_112_RR_EN_ENABLED 1
-
-/* MEMC_ARB_1 :: CLIENT_INFO_112 :: reserved0 [30:30] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_112_reserved0_MASK 0x40000000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_112_reserved0_SHIFT 30
-
-/* MEMC_ARB_1 :: CLIENT_INFO_112 :: BO_VAL [29:12] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_112_BO_VAL_MASK 0x3ffff000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_112_BO_VAL_SHIFT 12
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_112_BO_VAL_DEFAULT 0x00000000
-
-/* MEMC_ARB_1 :: CLIENT_INFO_112 :: reserved1 [11:08] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_112_reserved1_MASK 0x00000f00
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_112_reserved1_SHIFT 8
-
-/* MEMC_ARB_1 :: CLIENT_INFO_112 :: PR_TAG [07:00] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_112_PR_TAG_MASK 0x000000ff
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_112_PR_TAG_SHIFT 0
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_112_PR_TAG_DEFAULT 0x00000000
-
-/***************************************************************************
- *CLIENT_INFO_113 - Client Programming register for client 113.
- ***************************************************************************/
-/* MEMC_ARB_1 :: CLIENT_INFO_113 :: RR_EN [31:31] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_113_RR_EN_MASK 0x80000000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_113_RR_EN_SHIFT 31
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_113_RR_EN_DEFAULT 0x00000001
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_113_RR_EN_DISABLED 0
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_113_RR_EN_ENABLED 1
-
-/* MEMC_ARB_1 :: CLIENT_INFO_113 :: reserved0 [30:30] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_113_reserved0_MASK 0x40000000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_113_reserved0_SHIFT 30
-
-/* MEMC_ARB_1 :: CLIENT_INFO_113 :: BO_VAL [29:12] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_113_BO_VAL_MASK 0x3ffff000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_113_BO_VAL_SHIFT 12
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_113_BO_VAL_DEFAULT 0x00000000
-
-/* MEMC_ARB_1 :: CLIENT_INFO_113 :: reserved1 [11:08] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_113_reserved1_MASK 0x00000f00
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_113_reserved1_SHIFT 8
-
-/* MEMC_ARB_1 :: CLIENT_INFO_113 :: PR_TAG [07:00] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_113_PR_TAG_MASK 0x000000ff
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_113_PR_TAG_SHIFT 0
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_113_PR_TAG_DEFAULT 0x00000000
-
-/***************************************************************************
- *CLIENT_INFO_114 - Client Programming register for client 114.
- ***************************************************************************/
-/* MEMC_ARB_1 :: CLIENT_INFO_114 :: RR_EN [31:31] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_114_RR_EN_MASK 0x80000000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_114_RR_EN_SHIFT 31
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_114_RR_EN_DEFAULT 0x00000001
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_114_RR_EN_DISABLED 0
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_114_RR_EN_ENABLED 1
-
-/* MEMC_ARB_1 :: CLIENT_INFO_114 :: reserved0 [30:30] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_114_reserved0_MASK 0x40000000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_114_reserved0_SHIFT 30
-
-/* MEMC_ARB_1 :: CLIENT_INFO_114 :: BO_VAL [29:12] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_114_BO_VAL_MASK 0x3ffff000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_114_BO_VAL_SHIFT 12
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_114_BO_VAL_DEFAULT 0x00000000
-
-/* MEMC_ARB_1 :: CLIENT_INFO_114 :: reserved1 [11:08] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_114_reserved1_MASK 0x00000f00
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_114_reserved1_SHIFT 8
-
-/* MEMC_ARB_1 :: CLIENT_INFO_114 :: PR_TAG [07:00] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_114_PR_TAG_MASK 0x000000ff
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_114_PR_TAG_SHIFT 0
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_114_PR_TAG_DEFAULT 0x00000000
-
-/***************************************************************************
- *CLIENT_INFO_115 - Client Programming register for client 115.
- ***************************************************************************/
-/* MEMC_ARB_1 :: CLIENT_INFO_115 :: RR_EN [31:31] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_115_RR_EN_MASK 0x80000000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_115_RR_EN_SHIFT 31
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_115_RR_EN_DEFAULT 0x00000001
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_115_RR_EN_DISABLED 0
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_115_RR_EN_ENABLED 1
-
-/* MEMC_ARB_1 :: CLIENT_INFO_115 :: reserved0 [30:30] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_115_reserved0_MASK 0x40000000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_115_reserved0_SHIFT 30
-
-/* MEMC_ARB_1 :: CLIENT_INFO_115 :: BO_VAL [29:12] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_115_BO_VAL_MASK 0x3ffff000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_115_BO_VAL_SHIFT 12
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_115_BO_VAL_DEFAULT 0x00000000
-
-/* MEMC_ARB_1 :: CLIENT_INFO_115 :: reserved1 [11:08] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_115_reserved1_MASK 0x00000f00
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_115_reserved1_SHIFT 8
-
-/* MEMC_ARB_1 :: CLIENT_INFO_115 :: PR_TAG [07:00] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_115_PR_TAG_MASK 0x000000ff
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_115_PR_TAG_SHIFT 0
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_115_PR_TAG_DEFAULT 0x00000000
-
-/***************************************************************************
- *CLIENT_INFO_116 - Client Programming register for client 116.
- ***************************************************************************/
-/* MEMC_ARB_1 :: CLIENT_INFO_116 :: RR_EN [31:31] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_116_RR_EN_MASK 0x80000000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_116_RR_EN_SHIFT 31
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_116_RR_EN_DEFAULT 0x00000001
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_116_RR_EN_DISABLED 0
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_116_RR_EN_ENABLED 1
-
-/* MEMC_ARB_1 :: CLIENT_INFO_116 :: reserved0 [30:30] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_116_reserved0_MASK 0x40000000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_116_reserved0_SHIFT 30
-
-/* MEMC_ARB_1 :: CLIENT_INFO_116 :: BO_VAL [29:12] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_116_BO_VAL_MASK 0x3ffff000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_116_BO_VAL_SHIFT 12
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_116_BO_VAL_DEFAULT 0x00000000
-
-/* MEMC_ARB_1 :: CLIENT_INFO_116 :: reserved1 [11:08] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_116_reserved1_MASK 0x00000f00
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_116_reserved1_SHIFT 8
-
-/* MEMC_ARB_1 :: CLIENT_INFO_116 :: PR_TAG [07:00] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_116_PR_TAG_MASK 0x000000ff
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_116_PR_TAG_SHIFT 0
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_116_PR_TAG_DEFAULT 0x00000000
-
-/***************************************************************************
- *CLIENT_INFO_117 - Client Programming register for client 117.
- ***************************************************************************/
-/* MEMC_ARB_1 :: CLIENT_INFO_117 :: RR_EN [31:31] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_117_RR_EN_MASK 0x80000000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_117_RR_EN_SHIFT 31
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_117_RR_EN_DEFAULT 0x00000001
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_117_RR_EN_DISABLED 0
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_117_RR_EN_ENABLED 1
-
-/* MEMC_ARB_1 :: CLIENT_INFO_117 :: reserved0 [30:30] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_117_reserved0_MASK 0x40000000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_117_reserved0_SHIFT 30
-
-/* MEMC_ARB_1 :: CLIENT_INFO_117 :: BO_VAL [29:12] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_117_BO_VAL_MASK 0x3ffff000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_117_BO_VAL_SHIFT 12
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_117_BO_VAL_DEFAULT 0x00000000
-
-/* MEMC_ARB_1 :: CLIENT_INFO_117 :: reserved1 [11:08] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_117_reserved1_MASK 0x00000f00
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_117_reserved1_SHIFT 8
-
-/* MEMC_ARB_1 :: CLIENT_INFO_117 :: PR_TAG [07:00] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_117_PR_TAG_MASK 0x000000ff
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_117_PR_TAG_SHIFT 0
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_117_PR_TAG_DEFAULT 0x00000000
-
-/***************************************************************************
- *CLIENT_INFO_118 - Client Programming register for client 118.
- ***************************************************************************/
-/* MEMC_ARB_1 :: CLIENT_INFO_118 :: RR_EN [31:31] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_118_RR_EN_MASK 0x80000000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_118_RR_EN_SHIFT 31
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_118_RR_EN_DEFAULT 0x00000001
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_118_RR_EN_DISABLED 0
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_118_RR_EN_ENABLED 1
-
-/* MEMC_ARB_1 :: CLIENT_INFO_118 :: reserved0 [30:30] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_118_reserved0_MASK 0x40000000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_118_reserved0_SHIFT 30
-
-/* MEMC_ARB_1 :: CLIENT_INFO_118 :: BO_VAL [29:12] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_118_BO_VAL_MASK 0x3ffff000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_118_BO_VAL_SHIFT 12
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_118_BO_VAL_DEFAULT 0x00000000
-
-/* MEMC_ARB_1 :: CLIENT_INFO_118 :: reserved1 [11:08] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_118_reserved1_MASK 0x00000f00
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_118_reserved1_SHIFT 8
-
-/* MEMC_ARB_1 :: CLIENT_INFO_118 :: PR_TAG [07:00] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_118_PR_TAG_MASK 0x000000ff
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_118_PR_TAG_SHIFT 0
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_118_PR_TAG_DEFAULT 0x00000000
-
-/***************************************************************************
- *CLIENT_INFO_119 - Client Programming register for client 119.
- ***************************************************************************/
-/* MEMC_ARB_1 :: CLIENT_INFO_119 :: RR_EN [31:31] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_119_RR_EN_MASK 0x80000000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_119_RR_EN_SHIFT 31
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_119_RR_EN_DEFAULT 0x00000001
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_119_RR_EN_DISABLED 0
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_119_RR_EN_ENABLED 1
-
-/* MEMC_ARB_1 :: CLIENT_INFO_119 :: reserved0 [30:30] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_119_reserved0_MASK 0x40000000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_119_reserved0_SHIFT 30
-
-/* MEMC_ARB_1 :: CLIENT_INFO_119 :: BO_VAL [29:12] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_119_BO_VAL_MASK 0x3ffff000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_119_BO_VAL_SHIFT 12
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_119_BO_VAL_DEFAULT 0x00000000
-
-/* MEMC_ARB_1 :: CLIENT_INFO_119 :: reserved1 [11:08] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_119_reserved1_MASK 0x00000f00
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_119_reserved1_SHIFT 8
-
-/* MEMC_ARB_1 :: CLIENT_INFO_119 :: PR_TAG [07:00] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_119_PR_TAG_MASK 0x000000ff
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_119_PR_TAG_SHIFT 0
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_119_PR_TAG_DEFAULT 0x00000000
-
-/***************************************************************************
- *CLIENT_INFO_120 - Client Programming register for client 120.
- ***************************************************************************/
-/* MEMC_ARB_1 :: CLIENT_INFO_120 :: RR_EN [31:31] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_120_RR_EN_MASK 0x80000000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_120_RR_EN_SHIFT 31
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_120_RR_EN_DEFAULT 0x00000001
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_120_RR_EN_DISABLED 0
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_120_RR_EN_ENABLED 1
-
-/* MEMC_ARB_1 :: CLIENT_INFO_120 :: reserved0 [30:30] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_120_reserved0_MASK 0x40000000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_120_reserved0_SHIFT 30
-
-/* MEMC_ARB_1 :: CLIENT_INFO_120 :: BO_VAL [29:12] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_120_BO_VAL_MASK 0x3ffff000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_120_BO_VAL_SHIFT 12
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_120_BO_VAL_DEFAULT 0x00000000
-
-/* MEMC_ARB_1 :: CLIENT_INFO_120 :: reserved1 [11:08] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_120_reserved1_MASK 0x00000f00
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_120_reserved1_SHIFT 8
-
-/* MEMC_ARB_1 :: CLIENT_INFO_120 :: PR_TAG [07:00] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_120_PR_TAG_MASK 0x000000ff
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_120_PR_TAG_SHIFT 0
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_120_PR_TAG_DEFAULT 0x00000000
-
-/***************************************************************************
- *CLIENT_INFO_121 - Client Programming register for client 121.
- ***************************************************************************/
-/* MEMC_ARB_1 :: CLIENT_INFO_121 :: RR_EN [31:31] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_121_RR_EN_MASK 0x80000000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_121_RR_EN_SHIFT 31
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_121_RR_EN_DEFAULT 0x00000001
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_121_RR_EN_DISABLED 0
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_121_RR_EN_ENABLED 1
-
-/* MEMC_ARB_1 :: CLIENT_INFO_121 :: reserved0 [30:30] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_121_reserved0_MASK 0x40000000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_121_reserved0_SHIFT 30
-
-/* MEMC_ARB_1 :: CLIENT_INFO_121 :: BO_VAL [29:12] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_121_BO_VAL_MASK 0x3ffff000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_121_BO_VAL_SHIFT 12
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_121_BO_VAL_DEFAULT 0x00000000
-
-/* MEMC_ARB_1 :: CLIENT_INFO_121 :: reserved1 [11:08] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_121_reserved1_MASK 0x00000f00
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_121_reserved1_SHIFT 8
-
-/* MEMC_ARB_1 :: CLIENT_INFO_121 :: PR_TAG [07:00] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_121_PR_TAG_MASK 0x000000ff
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_121_PR_TAG_SHIFT 0
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_121_PR_TAG_DEFAULT 0x00000000
-
-/***************************************************************************
- *CLIENT_INFO_122 - Client Programming register for client 122.
- ***************************************************************************/
-/* MEMC_ARB_1 :: CLIENT_INFO_122 :: RR_EN [31:31] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_122_RR_EN_MASK 0x80000000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_122_RR_EN_SHIFT 31
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_122_RR_EN_DEFAULT 0x00000001
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_122_RR_EN_DISABLED 0
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_122_RR_EN_ENABLED 1
-
-/* MEMC_ARB_1 :: CLIENT_INFO_122 :: reserved0 [30:30] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_122_reserved0_MASK 0x40000000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_122_reserved0_SHIFT 30
-
-/* MEMC_ARB_1 :: CLIENT_INFO_122 :: BO_VAL [29:12] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_122_BO_VAL_MASK 0x3ffff000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_122_BO_VAL_SHIFT 12
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_122_BO_VAL_DEFAULT 0x00000000
-
-/* MEMC_ARB_1 :: CLIENT_INFO_122 :: reserved1 [11:08] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_122_reserved1_MASK 0x00000f00
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_122_reserved1_SHIFT 8
-
-/* MEMC_ARB_1 :: CLIENT_INFO_122 :: PR_TAG [07:00] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_122_PR_TAG_MASK 0x000000ff
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_122_PR_TAG_SHIFT 0
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_122_PR_TAG_DEFAULT 0x00000000
-
-/***************************************************************************
- *CLIENT_INFO_123 - Client Programming register for client 123.
- ***************************************************************************/
-/* MEMC_ARB_1 :: CLIENT_INFO_123 :: RR_EN [31:31] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_123_RR_EN_MASK 0x80000000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_123_RR_EN_SHIFT 31
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_123_RR_EN_DEFAULT 0x00000001
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_123_RR_EN_DISABLED 0
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_123_RR_EN_ENABLED 1
-
-/* MEMC_ARB_1 :: CLIENT_INFO_123 :: reserved0 [30:30] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_123_reserved0_MASK 0x40000000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_123_reserved0_SHIFT 30
-
-/* MEMC_ARB_1 :: CLIENT_INFO_123 :: BO_VAL [29:12] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_123_BO_VAL_MASK 0x3ffff000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_123_BO_VAL_SHIFT 12
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_123_BO_VAL_DEFAULT 0x00000000
-
-/* MEMC_ARB_1 :: CLIENT_INFO_123 :: reserved1 [11:08] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_123_reserved1_MASK 0x00000f00
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_123_reserved1_SHIFT 8
-
-/* MEMC_ARB_1 :: CLIENT_INFO_123 :: PR_TAG [07:00] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_123_PR_TAG_MASK 0x000000ff
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_123_PR_TAG_SHIFT 0
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_123_PR_TAG_DEFAULT 0x00000000
-
-/***************************************************************************
- *CLIENT_INFO_124 - Client Programming register for client 124.
- ***************************************************************************/
-/* MEMC_ARB_1 :: CLIENT_INFO_124 :: RR_EN [31:31] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_124_RR_EN_MASK 0x80000000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_124_RR_EN_SHIFT 31
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_124_RR_EN_DEFAULT 0x00000001
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_124_RR_EN_DISABLED 0
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_124_RR_EN_ENABLED 1
-
-/* MEMC_ARB_1 :: CLIENT_INFO_124 :: reserved0 [30:30] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_124_reserved0_MASK 0x40000000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_124_reserved0_SHIFT 30
-
-/* MEMC_ARB_1 :: CLIENT_INFO_124 :: BO_VAL [29:12] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_124_BO_VAL_MASK 0x3ffff000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_124_BO_VAL_SHIFT 12
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_124_BO_VAL_DEFAULT 0x00000000
-
-/* MEMC_ARB_1 :: CLIENT_INFO_124 :: reserved1 [11:08] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_124_reserved1_MASK 0x00000f00
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_124_reserved1_SHIFT 8
-
-/* MEMC_ARB_1 :: CLIENT_INFO_124 :: PR_TAG [07:00] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_124_PR_TAG_MASK 0x000000ff
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_124_PR_TAG_SHIFT 0
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_124_PR_TAG_DEFAULT 0x00000000
-
-/***************************************************************************
- *CLIENT_INFO_125 - Client Programming register for client 125.
- ***************************************************************************/
-/* MEMC_ARB_1 :: CLIENT_INFO_125 :: RR_EN [31:31] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_125_RR_EN_MASK 0x80000000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_125_RR_EN_SHIFT 31
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_125_RR_EN_DEFAULT 0x00000001
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_125_RR_EN_DISABLED 0
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_125_RR_EN_ENABLED 1
-
-/* MEMC_ARB_1 :: CLIENT_INFO_125 :: reserved0 [30:30] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_125_reserved0_MASK 0x40000000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_125_reserved0_SHIFT 30
-
-/* MEMC_ARB_1 :: CLIENT_INFO_125 :: BO_VAL [29:12] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_125_BO_VAL_MASK 0x3ffff000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_125_BO_VAL_SHIFT 12
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_125_BO_VAL_DEFAULT 0x00000000
-
-/* MEMC_ARB_1 :: CLIENT_INFO_125 :: reserved1 [11:08] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_125_reserved1_MASK 0x00000f00
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_125_reserved1_SHIFT 8
-
-/* MEMC_ARB_1 :: CLIENT_INFO_125 :: PR_TAG [07:00] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_125_PR_TAG_MASK 0x000000ff
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_125_PR_TAG_SHIFT 0
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_125_PR_TAG_DEFAULT 0x00000000
-
-/***************************************************************************
- *CLIENT_INFO_126 - Client Programming register for client 126.
- ***************************************************************************/
-/* MEMC_ARB_1 :: CLIENT_INFO_126 :: RR_EN [31:31] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_126_RR_EN_MASK 0x80000000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_126_RR_EN_SHIFT 31
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_126_RR_EN_DEFAULT 0x00000001
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_126_RR_EN_DISABLED 0
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_126_RR_EN_ENABLED 1
-
-/* MEMC_ARB_1 :: CLIENT_INFO_126 :: reserved0 [30:30] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_126_reserved0_MASK 0x40000000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_126_reserved0_SHIFT 30
-
-/* MEMC_ARB_1 :: CLIENT_INFO_126 :: BO_VAL [29:12] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_126_BO_VAL_MASK 0x3ffff000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_126_BO_VAL_SHIFT 12
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_126_BO_VAL_DEFAULT 0x00000000
-
-/* MEMC_ARB_1 :: CLIENT_INFO_126 :: reserved1 [11:08] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_126_reserved1_MASK 0x00000f00
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_126_reserved1_SHIFT 8
-
-/* MEMC_ARB_1 :: CLIENT_INFO_126 :: PR_TAG [07:00] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_126_PR_TAG_MASK 0x000000ff
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_126_PR_TAG_SHIFT 0
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_126_PR_TAG_DEFAULT 0x00000000
-
-/***************************************************************************
- *CLIENT_INFO_127 - Client Programming register for client 127
- ***************************************************************************/
-/* MEMC_ARB_1 :: CLIENT_INFO_127 :: RR_EN [31:31] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_127_RR_EN_MASK 0x80000000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_127_RR_EN_SHIFT 31
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_127_RR_EN_DEFAULT 0x00000001
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_127_RR_EN_DISABLED 0
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_127_RR_EN_ENABLED 1
-
-/* MEMC_ARB_1 :: CLIENT_INFO_127 :: reserved0 [30:30] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_127_reserved0_MASK 0x40000000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_127_reserved0_SHIFT 30
-
-/* MEMC_ARB_1 :: CLIENT_INFO_127 :: BO_VAL [29:12] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_127_BO_VAL_MASK 0x3ffff000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_127_BO_VAL_SHIFT 12
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_127_BO_VAL_DEFAULT 0x00000000
-
-/* MEMC_ARB_1 :: CLIENT_INFO_127 :: reserved1 [11:08] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_127_reserved1_MASK 0x00000f00
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_127_reserved1_SHIFT 8
-
-/* MEMC_ARB_1 :: CLIENT_INFO_127 :: PR_TAG [07:00] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_127_PR_TAG_MASK 0x000000ff
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_127_PR_TAG_SHIFT 0
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_127_PR_TAG_DEFAULT 0x00000000
-
-/***************************************************************************
- *CLIENT_INFO_128 - Client Programming register for client 128.
- ***************************************************************************/
-/* MEMC_ARB_1 :: CLIENT_INFO_128 :: RR_EN [31:31] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_128_RR_EN_MASK 0x80000000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_128_RR_EN_SHIFT 31
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_128_RR_EN_DEFAULT 0x00000001
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_128_RR_EN_DISABLED 0
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_128_RR_EN_ENABLED 1
-
-/* MEMC_ARB_1 :: CLIENT_INFO_128 :: reserved0 [30:30] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_128_reserved0_MASK 0x40000000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_128_reserved0_SHIFT 30
-
-/* MEMC_ARB_1 :: CLIENT_INFO_128 :: BO_VAL [29:12] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_128_BO_VAL_MASK 0x3ffff000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_128_BO_VAL_SHIFT 12
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_128_BO_VAL_DEFAULT 0x00000000
-
-/* MEMC_ARB_1 :: CLIENT_INFO_128 :: reserved1 [11:08] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_128_reserved1_MASK 0x00000f00
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_128_reserved1_SHIFT 8
-
-/* MEMC_ARB_1 :: CLIENT_INFO_128 :: PR_TAG [07:00] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_128_PR_TAG_MASK 0x000000ff
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_128_PR_TAG_SHIFT 0
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_128_PR_TAG_DEFAULT 0x00000000
-
-/***************************************************************************
- *CLIENT_INFO_129 - Client Programming register for client 129.
- ***************************************************************************/
-/* MEMC_ARB_1 :: CLIENT_INFO_129 :: RR_EN [31:31] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_129_RR_EN_MASK 0x80000000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_129_RR_EN_SHIFT 31
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_129_RR_EN_DEFAULT 0x00000001
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_129_RR_EN_DISABLED 0
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_129_RR_EN_ENABLED 1
-
-/* MEMC_ARB_1 :: CLIENT_INFO_129 :: reserved0 [30:30] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_129_reserved0_MASK 0x40000000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_129_reserved0_SHIFT 30
-
-/* MEMC_ARB_1 :: CLIENT_INFO_129 :: BO_VAL [29:12] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_129_BO_VAL_MASK 0x3ffff000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_129_BO_VAL_SHIFT 12
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_129_BO_VAL_DEFAULT 0x00000000
-
-/* MEMC_ARB_1 :: CLIENT_INFO_129 :: reserved1 [11:08] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_129_reserved1_MASK 0x00000f00
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_129_reserved1_SHIFT 8
-
-/* MEMC_ARB_1 :: CLIENT_INFO_129 :: PR_TAG [07:00] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_129_PR_TAG_MASK 0x000000ff
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_129_PR_TAG_SHIFT 0
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_129_PR_TAG_DEFAULT 0x00000000
-
-/***************************************************************************
- *CLIENT_INFO_130 - Client Programming register for client 130.
- ***************************************************************************/
-/* MEMC_ARB_1 :: CLIENT_INFO_130 :: RR_EN [31:31] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_130_RR_EN_MASK 0x80000000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_130_RR_EN_SHIFT 31
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_130_RR_EN_DEFAULT 0x00000001
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_130_RR_EN_DISABLED 0
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_130_RR_EN_ENABLED 1
-
-/* MEMC_ARB_1 :: CLIENT_INFO_130 :: reserved0 [30:30] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_130_reserved0_MASK 0x40000000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_130_reserved0_SHIFT 30
-
-/* MEMC_ARB_1 :: CLIENT_INFO_130 :: BO_VAL [29:12] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_130_BO_VAL_MASK 0x3ffff000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_130_BO_VAL_SHIFT 12
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_130_BO_VAL_DEFAULT 0x00000000
-
-/* MEMC_ARB_1 :: CLIENT_INFO_130 :: reserved1 [11:08] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_130_reserved1_MASK 0x00000f00
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_130_reserved1_SHIFT 8
-
-/* MEMC_ARB_1 :: CLIENT_INFO_130 :: PR_TAG [07:00] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_130_PR_TAG_MASK 0x000000ff
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_130_PR_TAG_SHIFT 0
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_130_PR_TAG_DEFAULT 0x00000000
-
-/***************************************************************************
- *CLIENT_INFO_131 - Client Programming register for client 131.
- ***************************************************************************/
-/* MEMC_ARB_1 :: CLIENT_INFO_131 :: RR_EN [31:31] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_131_RR_EN_MASK 0x80000000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_131_RR_EN_SHIFT 31
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_131_RR_EN_DEFAULT 0x00000001
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_131_RR_EN_DISABLED 0
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_131_RR_EN_ENABLED 1
-
-/* MEMC_ARB_1 :: CLIENT_INFO_131 :: reserved0 [30:30] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_131_reserved0_MASK 0x40000000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_131_reserved0_SHIFT 30
-
-/* MEMC_ARB_1 :: CLIENT_INFO_131 :: BO_VAL [29:12] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_131_BO_VAL_MASK 0x3ffff000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_131_BO_VAL_SHIFT 12
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_131_BO_VAL_DEFAULT 0x00000000
-
-/* MEMC_ARB_1 :: CLIENT_INFO_131 :: reserved1 [11:08] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_131_reserved1_MASK 0x00000f00
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_131_reserved1_SHIFT 8
-
-/* MEMC_ARB_1 :: CLIENT_INFO_131 :: PR_TAG [07:00] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_131_PR_TAG_MASK 0x000000ff
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_131_PR_TAG_SHIFT 0
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_131_PR_TAG_DEFAULT 0x00000000
-
-/***************************************************************************
- *CLIENT_INFO_132 - Client Programming register for client 132.
- ***************************************************************************/
-/* MEMC_ARB_1 :: CLIENT_INFO_132 :: RR_EN [31:31] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_132_RR_EN_MASK 0x80000000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_132_RR_EN_SHIFT 31
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_132_RR_EN_DEFAULT 0x00000001
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_132_RR_EN_DISABLED 0
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_132_RR_EN_ENABLED 1
-
-/* MEMC_ARB_1 :: CLIENT_INFO_132 :: reserved0 [30:30] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_132_reserved0_MASK 0x40000000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_132_reserved0_SHIFT 30
-
-/* MEMC_ARB_1 :: CLIENT_INFO_132 :: BO_VAL [29:12] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_132_BO_VAL_MASK 0x3ffff000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_132_BO_VAL_SHIFT 12
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_132_BO_VAL_DEFAULT 0x00000000
-
-/* MEMC_ARB_1 :: CLIENT_INFO_132 :: reserved1 [11:08] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_132_reserved1_MASK 0x00000f00
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_132_reserved1_SHIFT 8
-
-/* MEMC_ARB_1 :: CLIENT_INFO_132 :: PR_TAG [07:00] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_132_PR_TAG_MASK 0x000000ff
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_132_PR_TAG_SHIFT 0
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_132_PR_TAG_DEFAULT 0x00000000
-
-/***************************************************************************
- *CLIENT_INFO_133 - Client Programming register for client 133.
- ***************************************************************************/
-/* MEMC_ARB_1 :: CLIENT_INFO_133 :: RR_EN [31:31] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_133_RR_EN_MASK 0x80000000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_133_RR_EN_SHIFT 31
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_133_RR_EN_DEFAULT 0x00000001
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_133_RR_EN_DISABLED 0
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_133_RR_EN_ENABLED 1
-
-/* MEMC_ARB_1 :: CLIENT_INFO_133 :: reserved0 [30:30] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_133_reserved0_MASK 0x40000000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_133_reserved0_SHIFT 30
-
-/* MEMC_ARB_1 :: CLIENT_INFO_133 :: BO_VAL [29:12] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_133_BO_VAL_MASK 0x3ffff000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_133_BO_VAL_SHIFT 12
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_133_BO_VAL_DEFAULT 0x00000000
-
-/* MEMC_ARB_1 :: CLIENT_INFO_133 :: reserved1 [11:08] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_133_reserved1_MASK 0x00000f00
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_133_reserved1_SHIFT 8
-
-/* MEMC_ARB_1 :: CLIENT_INFO_133 :: PR_TAG [07:00] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_133_PR_TAG_MASK 0x000000ff
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_133_PR_TAG_SHIFT 0
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_133_PR_TAG_DEFAULT 0x00000000
-
-/***************************************************************************
- *CLIENT_INFO_134 - Client Programming register for client 134.
- ***************************************************************************/
-/* MEMC_ARB_1 :: CLIENT_INFO_134 :: RR_EN [31:31] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_134_RR_EN_MASK 0x80000000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_134_RR_EN_SHIFT 31
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_134_RR_EN_DEFAULT 0x00000001
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_134_RR_EN_DISABLED 0
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_134_RR_EN_ENABLED 1
-
-/* MEMC_ARB_1 :: CLIENT_INFO_134 :: reserved0 [30:30] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_134_reserved0_MASK 0x40000000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_134_reserved0_SHIFT 30
-
-/* MEMC_ARB_1 :: CLIENT_INFO_134 :: BO_VAL [29:12] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_134_BO_VAL_MASK 0x3ffff000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_134_BO_VAL_SHIFT 12
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_134_BO_VAL_DEFAULT 0x00000000
-
-/* MEMC_ARB_1 :: CLIENT_INFO_134 :: reserved1 [11:08] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_134_reserved1_MASK 0x00000f00
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_134_reserved1_SHIFT 8
-
-/* MEMC_ARB_1 :: CLIENT_INFO_134 :: PR_TAG [07:00] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_134_PR_TAG_MASK 0x000000ff
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_134_PR_TAG_SHIFT 0
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_134_PR_TAG_DEFAULT 0x00000000
-
-/***************************************************************************
- *CLIENT_INFO_135 - Client Programming register for client 135.
- ***************************************************************************/
-/* MEMC_ARB_1 :: CLIENT_INFO_135 :: RR_EN [31:31] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_135_RR_EN_MASK 0x80000000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_135_RR_EN_SHIFT 31
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_135_RR_EN_DEFAULT 0x00000001
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_135_RR_EN_DISABLED 0
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_135_RR_EN_ENABLED 1
-
-/* MEMC_ARB_1 :: CLIENT_INFO_135 :: reserved0 [30:30] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_135_reserved0_MASK 0x40000000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_135_reserved0_SHIFT 30
-
-/* MEMC_ARB_1 :: CLIENT_INFO_135 :: BO_VAL [29:12] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_135_BO_VAL_MASK 0x3ffff000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_135_BO_VAL_SHIFT 12
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_135_BO_VAL_DEFAULT 0x00000000
-
-/* MEMC_ARB_1 :: CLIENT_INFO_135 :: reserved1 [11:08] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_135_reserved1_MASK 0x00000f00
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_135_reserved1_SHIFT 8
-
-/* MEMC_ARB_1 :: CLIENT_INFO_135 :: PR_TAG [07:00] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_135_PR_TAG_MASK 0x000000ff
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_135_PR_TAG_SHIFT 0
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_135_PR_TAG_DEFAULT 0x00000000
-
-/***************************************************************************
- *CLIENT_INFO_136 - Client Programming register for client 136.
- ***************************************************************************/
-/* MEMC_ARB_1 :: CLIENT_INFO_136 :: RR_EN [31:31] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_136_RR_EN_MASK 0x80000000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_136_RR_EN_SHIFT 31
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_136_RR_EN_DEFAULT 0x00000001
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_136_RR_EN_DISABLED 0
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_136_RR_EN_ENABLED 1
-
-/* MEMC_ARB_1 :: CLIENT_INFO_136 :: reserved0 [30:30] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_136_reserved0_MASK 0x40000000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_136_reserved0_SHIFT 30
-
-/* MEMC_ARB_1 :: CLIENT_INFO_136 :: BO_VAL [29:12] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_136_BO_VAL_MASK 0x3ffff000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_136_BO_VAL_SHIFT 12
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_136_BO_VAL_DEFAULT 0x00000000
-
-/* MEMC_ARB_1 :: CLIENT_INFO_136 :: reserved1 [11:08] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_136_reserved1_MASK 0x00000f00
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_136_reserved1_SHIFT 8
-
-/* MEMC_ARB_1 :: CLIENT_INFO_136 :: PR_TAG [07:00] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_136_PR_TAG_MASK 0x000000ff
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_136_PR_TAG_SHIFT 0
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_136_PR_TAG_DEFAULT 0x00000000
-
-/***************************************************************************
- *CLIENT_INFO_137 - Client Programming register for client 137.
- ***************************************************************************/
-/* MEMC_ARB_1 :: CLIENT_INFO_137 :: RR_EN [31:31] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_137_RR_EN_MASK 0x80000000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_137_RR_EN_SHIFT 31
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_137_RR_EN_DEFAULT 0x00000001
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_137_RR_EN_DISABLED 0
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_137_RR_EN_ENABLED 1
-
-/* MEMC_ARB_1 :: CLIENT_INFO_137 :: reserved0 [30:30] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_137_reserved0_MASK 0x40000000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_137_reserved0_SHIFT 30
-
-/* MEMC_ARB_1 :: CLIENT_INFO_137 :: BO_VAL [29:12] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_137_BO_VAL_MASK 0x3ffff000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_137_BO_VAL_SHIFT 12
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_137_BO_VAL_DEFAULT 0x00000000
-
-/* MEMC_ARB_1 :: CLIENT_INFO_137 :: reserved1 [11:08] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_137_reserved1_MASK 0x00000f00
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_137_reserved1_SHIFT 8
-
-/* MEMC_ARB_1 :: CLIENT_INFO_137 :: PR_TAG [07:00] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_137_PR_TAG_MASK 0x000000ff
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_137_PR_TAG_SHIFT 0
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_137_PR_TAG_DEFAULT 0x00000000
-
-/***************************************************************************
- *CLIENT_INFO_138 - Client Programming register for client 138.
- ***************************************************************************/
-/* MEMC_ARB_1 :: CLIENT_INFO_138 :: RR_EN [31:31] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_138_RR_EN_MASK 0x80000000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_138_RR_EN_SHIFT 31
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_138_RR_EN_DEFAULT 0x00000001
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_138_RR_EN_DISABLED 0
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_138_RR_EN_ENABLED 1
-
-/* MEMC_ARB_1 :: CLIENT_INFO_138 :: reserved0 [30:30] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_138_reserved0_MASK 0x40000000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_138_reserved0_SHIFT 30
-
-/* MEMC_ARB_1 :: CLIENT_INFO_138 :: BO_VAL [29:12] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_138_BO_VAL_MASK 0x3ffff000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_138_BO_VAL_SHIFT 12
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_138_BO_VAL_DEFAULT 0x00000000
-
-/* MEMC_ARB_1 :: CLIENT_INFO_138 :: reserved1 [11:08] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_138_reserved1_MASK 0x00000f00
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_138_reserved1_SHIFT 8
-
-/* MEMC_ARB_1 :: CLIENT_INFO_138 :: PR_TAG [07:00] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_138_PR_TAG_MASK 0x000000ff
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_138_PR_TAG_SHIFT 0
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_138_PR_TAG_DEFAULT 0x00000000
-
-/***************************************************************************
- *CLIENT_INFO_139 - Client Programming register for client 139.
- ***************************************************************************/
-/* MEMC_ARB_1 :: CLIENT_INFO_139 :: RR_EN [31:31] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_139_RR_EN_MASK 0x80000000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_139_RR_EN_SHIFT 31
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_139_RR_EN_DEFAULT 0x00000001
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_139_RR_EN_DISABLED 0
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_139_RR_EN_ENABLED 1
-
-/* MEMC_ARB_1 :: CLIENT_INFO_139 :: reserved0 [30:30] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_139_reserved0_MASK 0x40000000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_139_reserved0_SHIFT 30
-
-/* MEMC_ARB_1 :: CLIENT_INFO_139 :: BO_VAL [29:12] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_139_BO_VAL_MASK 0x3ffff000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_139_BO_VAL_SHIFT 12
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_139_BO_VAL_DEFAULT 0x00000000
-
-/* MEMC_ARB_1 :: CLIENT_INFO_139 :: reserved1 [11:08] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_139_reserved1_MASK 0x00000f00
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_139_reserved1_SHIFT 8
-
-/* MEMC_ARB_1 :: CLIENT_INFO_139 :: PR_TAG [07:00] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_139_PR_TAG_MASK 0x000000ff
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_139_PR_TAG_SHIFT 0
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_139_PR_TAG_DEFAULT 0x00000000
-
-/***************************************************************************
- *CLIENT_INFO_140 - Client Programming register for client 140.
- ***************************************************************************/
-/* MEMC_ARB_1 :: CLIENT_INFO_140 :: RR_EN [31:31] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_140_RR_EN_MASK 0x80000000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_140_RR_EN_SHIFT 31
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_140_RR_EN_DEFAULT 0x00000001
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_140_RR_EN_DISABLED 0
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_140_RR_EN_ENABLED 1
-
-/* MEMC_ARB_1 :: CLIENT_INFO_140 :: reserved0 [30:30] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_140_reserved0_MASK 0x40000000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_140_reserved0_SHIFT 30
-
-/* MEMC_ARB_1 :: CLIENT_INFO_140 :: BO_VAL [29:12] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_140_BO_VAL_MASK 0x3ffff000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_140_BO_VAL_SHIFT 12
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_140_BO_VAL_DEFAULT 0x00000000
-
-/* MEMC_ARB_1 :: CLIENT_INFO_140 :: reserved1 [11:08] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_140_reserved1_MASK 0x00000f00
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_140_reserved1_SHIFT 8
-
-/* MEMC_ARB_1 :: CLIENT_INFO_140 :: PR_TAG [07:00] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_140_PR_TAG_MASK 0x000000ff
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_140_PR_TAG_SHIFT 0
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_140_PR_TAG_DEFAULT 0x00000000
-
-/***************************************************************************
- *CLIENT_INFO_141 - Client Programming register for client 141.
- ***************************************************************************/
-/* MEMC_ARB_1 :: CLIENT_INFO_141 :: RR_EN [31:31] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_141_RR_EN_MASK 0x80000000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_141_RR_EN_SHIFT 31
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_141_RR_EN_DEFAULT 0x00000001
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_141_RR_EN_DISABLED 0
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_141_RR_EN_ENABLED 1
-
-/* MEMC_ARB_1 :: CLIENT_INFO_141 :: reserved0 [30:30] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_141_reserved0_MASK 0x40000000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_141_reserved0_SHIFT 30
-
-/* MEMC_ARB_1 :: CLIENT_INFO_141 :: BO_VAL [29:12] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_141_BO_VAL_MASK 0x3ffff000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_141_BO_VAL_SHIFT 12
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_141_BO_VAL_DEFAULT 0x00000000
-
-/* MEMC_ARB_1 :: CLIENT_INFO_141 :: reserved1 [11:08] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_141_reserved1_MASK 0x00000f00
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_141_reserved1_SHIFT 8
-
-/* MEMC_ARB_1 :: CLIENT_INFO_141 :: PR_TAG [07:00] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_141_PR_TAG_MASK 0x000000ff
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_141_PR_TAG_SHIFT 0
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_141_PR_TAG_DEFAULT 0x00000000
-
-/***************************************************************************
- *CLIENT_INFO_142 - Client Programming register for client 142.
- ***************************************************************************/
-/* MEMC_ARB_1 :: CLIENT_INFO_142 :: RR_EN [31:31] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_142_RR_EN_MASK 0x80000000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_142_RR_EN_SHIFT 31
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_142_RR_EN_DEFAULT 0x00000001
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_142_RR_EN_DISABLED 0
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_142_RR_EN_ENABLED 1
-
-/* MEMC_ARB_1 :: CLIENT_INFO_142 :: reserved0 [30:30] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_142_reserved0_MASK 0x40000000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_142_reserved0_SHIFT 30
-
-/* MEMC_ARB_1 :: CLIENT_INFO_142 :: BO_VAL [29:12] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_142_BO_VAL_MASK 0x3ffff000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_142_BO_VAL_SHIFT 12
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_142_BO_VAL_DEFAULT 0x00000000
-
-/* MEMC_ARB_1 :: CLIENT_INFO_142 :: reserved1 [11:08] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_142_reserved1_MASK 0x00000f00
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_142_reserved1_SHIFT 8
-
-/* MEMC_ARB_1 :: CLIENT_INFO_142 :: PR_TAG [07:00] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_142_PR_TAG_MASK 0x000000ff
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_142_PR_TAG_SHIFT 0
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_142_PR_TAG_DEFAULT 0x00000000
-
-/***************************************************************************
- *CLIENT_INFO_143 - Client Programming register for client 143.
- ***************************************************************************/
-/* MEMC_ARB_1 :: CLIENT_INFO_143 :: RR_EN [31:31] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_143_RR_EN_MASK 0x80000000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_143_RR_EN_SHIFT 31
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_143_RR_EN_DEFAULT 0x00000001
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_143_RR_EN_DISABLED 0
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_143_RR_EN_ENABLED 1
-
-/* MEMC_ARB_1 :: CLIENT_INFO_143 :: reserved0 [30:30] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_143_reserved0_MASK 0x40000000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_143_reserved0_SHIFT 30
-
-/* MEMC_ARB_1 :: CLIENT_INFO_143 :: BO_VAL [29:12] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_143_BO_VAL_MASK 0x3ffff000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_143_BO_VAL_SHIFT 12
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_143_BO_VAL_DEFAULT 0x00000000
-
-/* MEMC_ARB_1 :: CLIENT_INFO_143 :: reserved1 [11:08] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_143_reserved1_MASK 0x00000f00
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_143_reserved1_SHIFT 8
-
-/* MEMC_ARB_1 :: CLIENT_INFO_143 :: PR_TAG [07:00] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_143_PR_TAG_MASK 0x000000ff
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_143_PR_TAG_SHIFT 0
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_143_PR_TAG_DEFAULT 0x00000000
-
-/***************************************************************************
- *CLIENT_INFO_144 - Client Programming register for client 144.
- ***************************************************************************/
-/* MEMC_ARB_1 :: CLIENT_INFO_144 :: RR_EN [31:31] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_144_RR_EN_MASK 0x80000000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_144_RR_EN_SHIFT 31
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_144_RR_EN_DEFAULT 0x00000001
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_144_RR_EN_DISABLED 0
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_144_RR_EN_ENABLED 1
-
-/* MEMC_ARB_1 :: CLIENT_INFO_144 :: reserved0 [30:30] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_144_reserved0_MASK 0x40000000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_144_reserved0_SHIFT 30
-
-/* MEMC_ARB_1 :: CLIENT_INFO_144 :: BO_VAL [29:12] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_144_BO_VAL_MASK 0x3ffff000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_144_BO_VAL_SHIFT 12
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_144_BO_VAL_DEFAULT 0x00000000
-
-/* MEMC_ARB_1 :: CLIENT_INFO_144 :: reserved1 [11:08] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_144_reserved1_MASK 0x00000f00
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_144_reserved1_SHIFT 8
-
-/* MEMC_ARB_1 :: CLIENT_INFO_144 :: PR_TAG [07:00] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_144_PR_TAG_MASK 0x000000ff
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_144_PR_TAG_SHIFT 0
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_144_PR_TAG_DEFAULT 0x00000000
-
-/***************************************************************************
- *CLIENT_INFO_145 - Client Programming register for client 145.
- ***************************************************************************/
-/* MEMC_ARB_1 :: CLIENT_INFO_145 :: RR_EN [31:31] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_145_RR_EN_MASK 0x80000000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_145_RR_EN_SHIFT 31
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_145_RR_EN_DEFAULT 0x00000001
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_145_RR_EN_DISABLED 0
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_145_RR_EN_ENABLED 1
-
-/* MEMC_ARB_1 :: CLIENT_INFO_145 :: reserved0 [30:30] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_145_reserved0_MASK 0x40000000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_145_reserved0_SHIFT 30
-
-/* MEMC_ARB_1 :: CLIENT_INFO_145 :: BO_VAL [29:12] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_145_BO_VAL_MASK 0x3ffff000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_145_BO_VAL_SHIFT 12
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_145_BO_VAL_DEFAULT 0x00000000
-
-/* MEMC_ARB_1 :: CLIENT_INFO_145 :: reserved1 [11:08] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_145_reserved1_MASK 0x00000f00
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_145_reserved1_SHIFT 8
-
-/* MEMC_ARB_1 :: CLIENT_INFO_145 :: PR_TAG [07:00] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_145_PR_TAG_MASK 0x000000ff
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_145_PR_TAG_SHIFT 0
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_145_PR_TAG_DEFAULT 0x00000000
-
-/***************************************************************************
- *CLIENT_INFO_146 - Client Programming register for client 146.
- ***************************************************************************/
-/* MEMC_ARB_1 :: CLIENT_INFO_146 :: RR_EN [31:31] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_146_RR_EN_MASK 0x80000000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_146_RR_EN_SHIFT 31
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_146_RR_EN_DEFAULT 0x00000001
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_146_RR_EN_DISABLED 0
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_146_RR_EN_ENABLED 1
-
-/* MEMC_ARB_1 :: CLIENT_INFO_146 :: reserved0 [30:30] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_146_reserved0_MASK 0x40000000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_146_reserved0_SHIFT 30
-
-/* MEMC_ARB_1 :: CLIENT_INFO_146 :: BO_VAL [29:12] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_146_BO_VAL_MASK 0x3ffff000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_146_BO_VAL_SHIFT 12
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_146_BO_VAL_DEFAULT 0x00000000
-
-/* MEMC_ARB_1 :: CLIENT_INFO_146 :: reserved1 [11:08] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_146_reserved1_MASK 0x00000f00
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_146_reserved1_SHIFT 8
-
-/* MEMC_ARB_1 :: CLIENT_INFO_146 :: PR_TAG [07:00] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_146_PR_TAG_MASK 0x000000ff
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_146_PR_TAG_SHIFT 0
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_146_PR_TAG_DEFAULT 0x00000000
-
-/***************************************************************************
- *CLIENT_INFO_147 - Client Programming register for client 147.
- ***************************************************************************/
-/* MEMC_ARB_1 :: CLIENT_INFO_147 :: RR_EN [31:31] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_147_RR_EN_MASK 0x80000000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_147_RR_EN_SHIFT 31
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_147_RR_EN_DEFAULT 0x00000001
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_147_RR_EN_DISABLED 0
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_147_RR_EN_ENABLED 1
-
-/* MEMC_ARB_1 :: CLIENT_INFO_147 :: reserved0 [30:30] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_147_reserved0_MASK 0x40000000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_147_reserved0_SHIFT 30
-
-/* MEMC_ARB_1 :: CLIENT_INFO_147 :: BO_VAL [29:12] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_147_BO_VAL_MASK 0x3ffff000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_147_BO_VAL_SHIFT 12
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_147_BO_VAL_DEFAULT 0x00000000
-
-/* MEMC_ARB_1 :: CLIENT_INFO_147 :: reserved1 [11:08] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_147_reserved1_MASK 0x00000f00
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_147_reserved1_SHIFT 8
-
-/* MEMC_ARB_1 :: CLIENT_INFO_147 :: PR_TAG [07:00] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_147_PR_TAG_MASK 0x000000ff
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_147_PR_TAG_SHIFT 0
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_147_PR_TAG_DEFAULT 0x00000000
-
-/***************************************************************************
- *CLIENT_INFO_148 - Client Programming register for client 148.
- ***************************************************************************/
-/* MEMC_ARB_1 :: CLIENT_INFO_148 :: RR_EN [31:31] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_148_RR_EN_MASK 0x80000000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_148_RR_EN_SHIFT 31
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_148_RR_EN_DEFAULT 0x00000001
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_148_RR_EN_DISABLED 0
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_148_RR_EN_ENABLED 1
-
-/* MEMC_ARB_1 :: CLIENT_INFO_148 :: reserved0 [30:30] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_148_reserved0_MASK 0x40000000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_148_reserved0_SHIFT 30
-
-/* MEMC_ARB_1 :: CLIENT_INFO_148 :: BO_VAL [29:12] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_148_BO_VAL_MASK 0x3ffff000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_148_BO_VAL_SHIFT 12
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_148_BO_VAL_DEFAULT 0x00000000
-
-/* MEMC_ARB_1 :: CLIENT_INFO_148 :: reserved1 [11:08] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_148_reserved1_MASK 0x00000f00
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_148_reserved1_SHIFT 8
-
-/* MEMC_ARB_1 :: CLIENT_INFO_148 :: PR_TAG [07:00] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_148_PR_TAG_MASK 0x000000ff
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_148_PR_TAG_SHIFT 0
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_148_PR_TAG_DEFAULT 0x00000000
-
-/***************************************************************************
- *CLIENT_INFO_149 - Client Programming register for client 149.
- ***************************************************************************/
-/* MEMC_ARB_1 :: CLIENT_INFO_149 :: RR_EN [31:31] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_149_RR_EN_MASK 0x80000000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_149_RR_EN_SHIFT 31
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_149_RR_EN_DEFAULT 0x00000001
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_149_RR_EN_DISABLED 0
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_149_RR_EN_ENABLED 1
-
-/* MEMC_ARB_1 :: CLIENT_INFO_149 :: reserved0 [30:30] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_149_reserved0_MASK 0x40000000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_149_reserved0_SHIFT 30
-
-/* MEMC_ARB_1 :: CLIENT_INFO_149 :: BO_VAL [29:12] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_149_BO_VAL_MASK 0x3ffff000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_149_BO_VAL_SHIFT 12
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_149_BO_VAL_DEFAULT 0x00000000
-
-/* MEMC_ARB_1 :: CLIENT_INFO_149 :: reserved1 [11:08] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_149_reserved1_MASK 0x00000f00
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_149_reserved1_SHIFT 8
-
-/* MEMC_ARB_1 :: CLIENT_INFO_149 :: PR_TAG [07:00] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_149_PR_TAG_MASK 0x000000ff
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_149_PR_TAG_SHIFT 0
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_149_PR_TAG_DEFAULT 0x00000000
-
-/***************************************************************************
- *CLIENT_INFO_150 - Client Programming register for client 150.
- ***************************************************************************/
-/* MEMC_ARB_1 :: CLIENT_INFO_150 :: RR_EN [31:31] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_150_RR_EN_MASK 0x80000000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_150_RR_EN_SHIFT 31
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_150_RR_EN_DEFAULT 0x00000001
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_150_RR_EN_DISABLED 0
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_150_RR_EN_ENABLED 1
-
-/* MEMC_ARB_1 :: CLIENT_INFO_150 :: reserved0 [30:30] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_150_reserved0_MASK 0x40000000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_150_reserved0_SHIFT 30
-
-/* MEMC_ARB_1 :: CLIENT_INFO_150 :: BO_VAL [29:12] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_150_BO_VAL_MASK 0x3ffff000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_150_BO_VAL_SHIFT 12
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_150_BO_VAL_DEFAULT 0x00000000
-
-/* MEMC_ARB_1 :: CLIENT_INFO_150 :: reserved1 [11:08] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_150_reserved1_MASK 0x00000f00
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_150_reserved1_SHIFT 8
-
-/* MEMC_ARB_1 :: CLIENT_INFO_150 :: PR_TAG [07:00] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_150_PR_TAG_MASK 0x000000ff
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_150_PR_TAG_SHIFT 0
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_150_PR_TAG_DEFAULT 0x00000000
-
-/***************************************************************************
- *CLIENT_INFO_151 - Client Programming register for client 151.
- ***************************************************************************/
-/* MEMC_ARB_1 :: CLIENT_INFO_151 :: RR_EN [31:31] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_151_RR_EN_MASK 0x80000000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_151_RR_EN_SHIFT 31
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_151_RR_EN_DEFAULT 0x00000001
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_151_RR_EN_DISABLED 0
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_151_RR_EN_ENABLED 1
-
-/* MEMC_ARB_1 :: CLIENT_INFO_151 :: reserved0 [30:30] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_151_reserved0_MASK 0x40000000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_151_reserved0_SHIFT 30
-
-/* MEMC_ARB_1 :: CLIENT_INFO_151 :: BO_VAL [29:12] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_151_BO_VAL_MASK 0x3ffff000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_151_BO_VAL_SHIFT 12
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_151_BO_VAL_DEFAULT 0x00000000
-
-/* MEMC_ARB_1 :: CLIENT_INFO_151 :: reserved1 [11:08] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_151_reserved1_MASK 0x00000f00
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_151_reserved1_SHIFT 8
-
-/* MEMC_ARB_1 :: CLIENT_INFO_151 :: PR_TAG [07:00] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_151_PR_TAG_MASK 0x000000ff
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_151_PR_TAG_SHIFT 0
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_151_PR_TAG_DEFAULT 0x00000000
-
-/***************************************************************************
- *CLIENT_INFO_152 - Client Programming register for client 152.
- ***************************************************************************/
-/* MEMC_ARB_1 :: CLIENT_INFO_152 :: RR_EN [31:31] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_152_RR_EN_MASK 0x80000000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_152_RR_EN_SHIFT 31
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_152_RR_EN_DEFAULT 0x00000001
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_152_RR_EN_DISABLED 0
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_152_RR_EN_ENABLED 1
-
-/* MEMC_ARB_1 :: CLIENT_INFO_152 :: reserved0 [30:30] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_152_reserved0_MASK 0x40000000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_152_reserved0_SHIFT 30
-
-/* MEMC_ARB_1 :: CLIENT_INFO_152 :: BO_VAL [29:12] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_152_BO_VAL_MASK 0x3ffff000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_152_BO_VAL_SHIFT 12
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_152_BO_VAL_DEFAULT 0x00000000
-
-/* MEMC_ARB_1 :: CLIENT_INFO_152 :: reserved1 [11:08] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_152_reserved1_MASK 0x00000f00
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_152_reserved1_SHIFT 8
-
-/* MEMC_ARB_1 :: CLIENT_INFO_152 :: PR_TAG [07:00] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_152_PR_TAG_MASK 0x000000ff
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_152_PR_TAG_SHIFT 0
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_152_PR_TAG_DEFAULT 0x00000000
-
-/***************************************************************************
- *CLIENT_INFO_153 - Client Programming register for client 153.
- ***************************************************************************/
-/* MEMC_ARB_1 :: CLIENT_INFO_153 :: RR_EN [31:31] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_153_RR_EN_MASK 0x80000000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_153_RR_EN_SHIFT 31
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_153_RR_EN_DEFAULT 0x00000001
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_153_RR_EN_DISABLED 0
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_153_RR_EN_ENABLED 1
-
-/* MEMC_ARB_1 :: CLIENT_INFO_153 :: reserved0 [30:30] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_153_reserved0_MASK 0x40000000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_153_reserved0_SHIFT 30
-
-/* MEMC_ARB_1 :: CLIENT_INFO_153 :: BO_VAL [29:12] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_153_BO_VAL_MASK 0x3ffff000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_153_BO_VAL_SHIFT 12
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_153_BO_VAL_DEFAULT 0x00000000
-
-/* MEMC_ARB_1 :: CLIENT_INFO_153 :: reserved1 [11:08] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_153_reserved1_MASK 0x00000f00
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_153_reserved1_SHIFT 8
-
-/* MEMC_ARB_1 :: CLIENT_INFO_153 :: PR_TAG [07:00] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_153_PR_TAG_MASK 0x000000ff
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_153_PR_TAG_SHIFT 0
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_153_PR_TAG_DEFAULT 0x00000000
-
-/***************************************************************************
- *CLIENT_INFO_154 - Client Programming register for client 154.
- ***************************************************************************/
-/* MEMC_ARB_1 :: CLIENT_INFO_154 :: RR_EN [31:31] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_154_RR_EN_MASK 0x80000000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_154_RR_EN_SHIFT 31
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_154_RR_EN_DEFAULT 0x00000001
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_154_RR_EN_DISABLED 0
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_154_RR_EN_ENABLED 1
-
-/* MEMC_ARB_1 :: CLIENT_INFO_154 :: reserved0 [30:30] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_154_reserved0_MASK 0x40000000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_154_reserved0_SHIFT 30
-
-/* MEMC_ARB_1 :: CLIENT_INFO_154 :: BO_VAL [29:12] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_154_BO_VAL_MASK 0x3ffff000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_154_BO_VAL_SHIFT 12
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_154_BO_VAL_DEFAULT 0x00000000
-
-/* MEMC_ARB_1 :: CLIENT_INFO_154 :: reserved1 [11:08] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_154_reserved1_MASK 0x00000f00
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_154_reserved1_SHIFT 8
-
-/* MEMC_ARB_1 :: CLIENT_INFO_154 :: PR_TAG [07:00] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_154_PR_TAG_MASK 0x000000ff
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_154_PR_TAG_SHIFT 0
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_154_PR_TAG_DEFAULT 0x00000000
-
-/***************************************************************************
- *CLIENT_INFO_155 - Client Programming register for client 155.
- ***************************************************************************/
-/* MEMC_ARB_1 :: CLIENT_INFO_155 :: RR_EN [31:31] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_155_RR_EN_MASK 0x80000000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_155_RR_EN_SHIFT 31
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_155_RR_EN_DEFAULT 0x00000001
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_155_RR_EN_DISABLED 0
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_155_RR_EN_ENABLED 1
-
-/* MEMC_ARB_1 :: CLIENT_INFO_155 :: reserved0 [30:30] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_155_reserved0_MASK 0x40000000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_155_reserved0_SHIFT 30
-
-/* MEMC_ARB_1 :: CLIENT_INFO_155 :: BO_VAL [29:12] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_155_BO_VAL_MASK 0x3ffff000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_155_BO_VAL_SHIFT 12
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_155_BO_VAL_DEFAULT 0x00000000
-
-/* MEMC_ARB_1 :: CLIENT_INFO_155 :: reserved1 [11:08] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_155_reserved1_MASK 0x00000f00
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_155_reserved1_SHIFT 8
-
-/* MEMC_ARB_1 :: CLIENT_INFO_155 :: PR_TAG [07:00] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_155_PR_TAG_MASK 0x000000ff
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_155_PR_TAG_SHIFT 0
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_155_PR_TAG_DEFAULT 0x00000000
-
-/***************************************************************************
- *CLIENT_INFO_156 - Client Programming register for client 156.
- ***************************************************************************/
-/* MEMC_ARB_1 :: CLIENT_INFO_156 :: RR_EN [31:31] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_156_RR_EN_MASK 0x80000000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_156_RR_EN_SHIFT 31
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_156_RR_EN_DEFAULT 0x00000001
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_156_RR_EN_DISABLED 0
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_156_RR_EN_ENABLED 1
-
-/* MEMC_ARB_1 :: CLIENT_INFO_156 :: reserved0 [30:30] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_156_reserved0_MASK 0x40000000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_156_reserved0_SHIFT 30
-
-/* MEMC_ARB_1 :: CLIENT_INFO_156 :: BO_VAL [29:12] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_156_BO_VAL_MASK 0x3ffff000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_156_BO_VAL_SHIFT 12
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_156_BO_VAL_DEFAULT 0x00000000
-
-/* MEMC_ARB_1 :: CLIENT_INFO_156 :: reserved1 [11:08] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_156_reserved1_MASK 0x00000f00
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_156_reserved1_SHIFT 8
-
-/* MEMC_ARB_1 :: CLIENT_INFO_156 :: PR_TAG [07:00] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_156_PR_TAG_MASK 0x000000ff
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_156_PR_TAG_SHIFT 0
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_156_PR_TAG_DEFAULT 0x00000000
-
-/***************************************************************************
- *CLIENT_INFO_157 - Client Programming register for client 157.
- ***************************************************************************/
-/* MEMC_ARB_1 :: CLIENT_INFO_157 :: RR_EN [31:31] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_157_RR_EN_MASK 0x80000000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_157_RR_EN_SHIFT 31
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_157_RR_EN_DEFAULT 0x00000001
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_157_RR_EN_DISABLED 0
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_157_RR_EN_ENABLED 1
-
-/* MEMC_ARB_1 :: CLIENT_INFO_157 :: reserved0 [30:30] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_157_reserved0_MASK 0x40000000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_157_reserved0_SHIFT 30
-
-/* MEMC_ARB_1 :: CLIENT_INFO_157 :: BO_VAL [29:12] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_157_BO_VAL_MASK 0x3ffff000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_157_BO_VAL_SHIFT 12
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_157_BO_VAL_DEFAULT 0x00000000
-
-/* MEMC_ARB_1 :: CLIENT_INFO_157 :: reserved1 [11:08] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_157_reserved1_MASK 0x00000f00
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_157_reserved1_SHIFT 8
-
-/* MEMC_ARB_1 :: CLIENT_INFO_157 :: PR_TAG [07:00] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_157_PR_TAG_MASK 0x000000ff
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_157_PR_TAG_SHIFT 0
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_157_PR_TAG_DEFAULT 0x00000000
-
-/***************************************************************************
- *CLIENT_INFO_158 - Client Programming register for client 158.
- ***************************************************************************/
-/* MEMC_ARB_1 :: CLIENT_INFO_158 :: RR_EN [31:31] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_158_RR_EN_MASK 0x80000000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_158_RR_EN_SHIFT 31
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_158_RR_EN_DEFAULT 0x00000001
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_158_RR_EN_DISABLED 0
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_158_RR_EN_ENABLED 1
-
-/* MEMC_ARB_1 :: CLIENT_INFO_158 :: reserved0 [30:30] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_158_reserved0_MASK 0x40000000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_158_reserved0_SHIFT 30
-
-/* MEMC_ARB_1 :: CLIENT_INFO_158 :: BO_VAL [29:12] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_158_BO_VAL_MASK 0x3ffff000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_158_BO_VAL_SHIFT 12
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_158_BO_VAL_DEFAULT 0x00000000
-
-/* MEMC_ARB_1 :: CLIENT_INFO_158 :: reserved1 [11:08] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_158_reserved1_MASK 0x00000f00
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_158_reserved1_SHIFT 8
-
-/* MEMC_ARB_1 :: CLIENT_INFO_158 :: PR_TAG [07:00] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_158_PR_TAG_MASK 0x000000ff
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_158_PR_TAG_SHIFT 0
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_158_PR_TAG_DEFAULT 0x00000000
-
-/***************************************************************************
- *CLIENT_INFO_159 - Client Programming register for client 159.
- ***************************************************************************/
-/* MEMC_ARB_1 :: CLIENT_INFO_159 :: RR_EN [31:31] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_159_RR_EN_MASK 0x80000000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_159_RR_EN_SHIFT 31
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_159_RR_EN_DEFAULT 0x00000001
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_159_RR_EN_DISABLED 0
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_159_RR_EN_ENABLED 1
-
-/* MEMC_ARB_1 :: CLIENT_INFO_159 :: reserved0 [30:30] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_159_reserved0_MASK 0x40000000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_159_reserved0_SHIFT 30
-
-/* MEMC_ARB_1 :: CLIENT_INFO_159 :: BO_VAL [29:12] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_159_BO_VAL_MASK 0x3ffff000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_159_BO_VAL_SHIFT 12
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_159_BO_VAL_DEFAULT 0x00000000
-
-/* MEMC_ARB_1 :: CLIENT_INFO_159 :: reserved1 [11:08] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_159_reserved1_MASK 0x00000f00
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_159_reserved1_SHIFT 8
-
-/* MEMC_ARB_1 :: CLIENT_INFO_159 :: PR_TAG [07:00] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_159_PR_TAG_MASK 0x000000ff
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_159_PR_TAG_SHIFT 0
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_159_PR_TAG_DEFAULT 0x00000000
-
-/***************************************************************************
- *CLIENT_INFO_160 - Client Programming register for client 160.
- ***************************************************************************/
-/* MEMC_ARB_1 :: CLIENT_INFO_160 :: RR_EN [31:31] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_160_RR_EN_MASK 0x80000000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_160_RR_EN_SHIFT 31
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_160_RR_EN_DEFAULT 0x00000001
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_160_RR_EN_DISABLED 0
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_160_RR_EN_ENABLED 1
-
-/* MEMC_ARB_1 :: CLIENT_INFO_160 :: reserved0 [30:30] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_160_reserved0_MASK 0x40000000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_160_reserved0_SHIFT 30
-
-/* MEMC_ARB_1 :: CLIENT_INFO_160 :: BO_VAL [29:12] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_160_BO_VAL_MASK 0x3ffff000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_160_BO_VAL_SHIFT 12
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_160_BO_VAL_DEFAULT 0x00000000
-
-/* MEMC_ARB_1 :: CLIENT_INFO_160 :: reserved1 [11:08] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_160_reserved1_MASK 0x00000f00
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_160_reserved1_SHIFT 8
-
-/* MEMC_ARB_1 :: CLIENT_INFO_160 :: PR_TAG [07:00] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_160_PR_TAG_MASK 0x000000ff
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_160_PR_TAG_SHIFT 0
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_160_PR_TAG_DEFAULT 0x00000000
-
-/***************************************************************************
- *CLIENT_INFO_161 - Client Programming register for client 161.
- ***************************************************************************/
-/* MEMC_ARB_1 :: CLIENT_INFO_161 :: RR_EN [31:31] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_161_RR_EN_MASK 0x80000000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_161_RR_EN_SHIFT 31
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_161_RR_EN_DEFAULT 0x00000001
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_161_RR_EN_DISABLED 0
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_161_RR_EN_ENABLED 1
-
-/* MEMC_ARB_1 :: CLIENT_INFO_161 :: reserved0 [30:30] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_161_reserved0_MASK 0x40000000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_161_reserved0_SHIFT 30
-
-/* MEMC_ARB_1 :: CLIENT_INFO_161 :: BO_VAL [29:12] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_161_BO_VAL_MASK 0x3ffff000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_161_BO_VAL_SHIFT 12
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_161_BO_VAL_DEFAULT 0x00000000
-
-/* MEMC_ARB_1 :: CLIENT_INFO_161 :: reserved1 [11:08] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_161_reserved1_MASK 0x00000f00
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_161_reserved1_SHIFT 8
-
-/* MEMC_ARB_1 :: CLIENT_INFO_161 :: PR_TAG [07:00] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_161_PR_TAG_MASK 0x000000ff
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_161_PR_TAG_SHIFT 0
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_161_PR_TAG_DEFAULT 0x00000000
-
-/***************************************************************************
- *CLIENT_INFO_162 - Client Programming register for client 162.
- ***************************************************************************/
-/* MEMC_ARB_1 :: CLIENT_INFO_162 :: RR_EN [31:31] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_162_RR_EN_MASK 0x80000000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_162_RR_EN_SHIFT 31
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_162_RR_EN_DEFAULT 0x00000001
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_162_RR_EN_DISABLED 0
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_162_RR_EN_ENABLED 1
-
-/* MEMC_ARB_1 :: CLIENT_INFO_162 :: reserved0 [30:30] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_162_reserved0_MASK 0x40000000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_162_reserved0_SHIFT 30
-
-/* MEMC_ARB_1 :: CLIENT_INFO_162 :: BO_VAL [29:12] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_162_BO_VAL_MASK 0x3ffff000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_162_BO_VAL_SHIFT 12
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_162_BO_VAL_DEFAULT 0x00000000
-
-/* MEMC_ARB_1 :: CLIENT_INFO_162 :: reserved1 [11:08] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_162_reserved1_MASK 0x00000f00
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_162_reserved1_SHIFT 8
-
-/* MEMC_ARB_1 :: CLIENT_INFO_162 :: PR_TAG [07:00] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_162_PR_TAG_MASK 0x000000ff
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_162_PR_TAG_SHIFT 0
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_162_PR_TAG_DEFAULT 0x00000000
-
-/***************************************************************************
- *CLIENT_INFO_163 - Client Programming register for client 163.
- ***************************************************************************/
-/* MEMC_ARB_1 :: CLIENT_INFO_163 :: RR_EN [31:31] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_163_RR_EN_MASK 0x80000000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_163_RR_EN_SHIFT 31
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_163_RR_EN_DEFAULT 0x00000001
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_163_RR_EN_DISABLED 0
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_163_RR_EN_ENABLED 1
-
-/* MEMC_ARB_1 :: CLIENT_INFO_163 :: reserved0 [30:30] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_163_reserved0_MASK 0x40000000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_163_reserved0_SHIFT 30
-
-/* MEMC_ARB_1 :: CLIENT_INFO_163 :: BO_VAL [29:12] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_163_BO_VAL_MASK 0x3ffff000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_163_BO_VAL_SHIFT 12
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_163_BO_VAL_DEFAULT 0x00000000
-
-/* MEMC_ARB_1 :: CLIENT_INFO_163 :: reserved1 [11:08] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_163_reserved1_MASK 0x00000f00
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_163_reserved1_SHIFT 8
-
-/* MEMC_ARB_1 :: CLIENT_INFO_163 :: PR_TAG [07:00] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_163_PR_TAG_MASK 0x000000ff
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_163_PR_TAG_SHIFT 0
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_163_PR_TAG_DEFAULT 0x00000000
-
-/***************************************************************************
- *CLIENT_INFO_164 - Client Programming register for client 164.
- ***************************************************************************/
-/* MEMC_ARB_1 :: CLIENT_INFO_164 :: RR_EN [31:31] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_164_RR_EN_MASK 0x80000000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_164_RR_EN_SHIFT 31
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_164_RR_EN_DEFAULT 0x00000001
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_164_RR_EN_DISABLED 0
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_164_RR_EN_ENABLED 1
-
-/* MEMC_ARB_1 :: CLIENT_INFO_164 :: reserved0 [30:30] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_164_reserved0_MASK 0x40000000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_164_reserved0_SHIFT 30
-
-/* MEMC_ARB_1 :: CLIENT_INFO_164 :: BO_VAL [29:12] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_164_BO_VAL_MASK 0x3ffff000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_164_BO_VAL_SHIFT 12
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_164_BO_VAL_DEFAULT 0x00000000
-
-/* MEMC_ARB_1 :: CLIENT_INFO_164 :: reserved1 [11:08] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_164_reserved1_MASK 0x00000f00
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_164_reserved1_SHIFT 8
-
-/* MEMC_ARB_1 :: CLIENT_INFO_164 :: PR_TAG [07:00] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_164_PR_TAG_MASK 0x000000ff
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_164_PR_TAG_SHIFT 0
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_164_PR_TAG_DEFAULT 0x00000000
-
-/***************************************************************************
- *CLIENT_INFO_165 - Client Programming register for client 165.
- ***************************************************************************/
-/* MEMC_ARB_1 :: CLIENT_INFO_165 :: RR_EN [31:31] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_165_RR_EN_MASK 0x80000000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_165_RR_EN_SHIFT 31
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_165_RR_EN_DEFAULT 0x00000001
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_165_RR_EN_DISABLED 0
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_165_RR_EN_ENABLED 1
-
-/* MEMC_ARB_1 :: CLIENT_INFO_165 :: reserved0 [30:30] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_165_reserved0_MASK 0x40000000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_165_reserved0_SHIFT 30
-
-/* MEMC_ARB_1 :: CLIENT_INFO_165 :: BO_VAL [29:12] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_165_BO_VAL_MASK 0x3ffff000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_165_BO_VAL_SHIFT 12
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_165_BO_VAL_DEFAULT 0x00000000
-
-/* MEMC_ARB_1 :: CLIENT_INFO_165 :: reserved1 [11:08] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_165_reserved1_MASK 0x00000f00
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_165_reserved1_SHIFT 8
-
-/* MEMC_ARB_1 :: CLIENT_INFO_165 :: PR_TAG [07:00] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_165_PR_TAG_MASK 0x000000ff
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_165_PR_TAG_SHIFT 0
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_165_PR_TAG_DEFAULT 0x00000000
-
-/***************************************************************************
- *CLIENT_INFO_166 - Client Programming register for client 166.
- ***************************************************************************/
-/* MEMC_ARB_1 :: CLIENT_INFO_166 :: RR_EN [31:31] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_166_RR_EN_MASK 0x80000000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_166_RR_EN_SHIFT 31
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_166_RR_EN_DEFAULT 0x00000001
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_166_RR_EN_DISABLED 0
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_166_RR_EN_ENABLED 1
-
-/* MEMC_ARB_1 :: CLIENT_INFO_166 :: reserved0 [30:30] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_166_reserved0_MASK 0x40000000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_166_reserved0_SHIFT 30
-
-/* MEMC_ARB_1 :: CLIENT_INFO_166 :: BO_VAL [29:12] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_166_BO_VAL_MASK 0x3ffff000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_166_BO_VAL_SHIFT 12
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_166_BO_VAL_DEFAULT 0x00000000
-
-/* MEMC_ARB_1 :: CLIENT_INFO_166 :: reserved1 [11:08] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_166_reserved1_MASK 0x00000f00
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_166_reserved1_SHIFT 8
-
-/* MEMC_ARB_1 :: CLIENT_INFO_166 :: PR_TAG [07:00] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_166_PR_TAG_MASK 0x000000ff
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_166_PR_TAG_SHIFT 0
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_166_PR_TAG_DEFAULT 0x00000000
-
-/***************************************************************************
- *CLIENT_INFO_167 - Client Programming register for client 167.
- ***************************************************************************/
-/* MEMC_ARB_1 :: CLIENT_INFO_167 :: RR_EN [31:31] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_167_RR_EN_MASK 0x80000000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_167_RR_EN_SHIFT 31
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_167_RR_EN_DEFAULT 0x00000001
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_167_RR_EN_DISABLED 0
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_167_RR_EN_ENABLED 1
-
-/* MEMC_ARB_1 :: CLIENT_INFO_167 :: reserved0 [30:30] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_167_reserved0_MASK 0x40000000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_167_reserved0_SHIFT 30
-
-/* MEMC_ARB_1 :: CLIENT_INFO_167 :: BO_VAL [29:12] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_167_BO_VAL_MASK 0x3ffff000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_167_BO_VAL_SHIFT 12
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_167_BO_VAL_DEFAULT 0x00000000
-
-/* MEMC_ARB_1 :: CLIENT_INFO_167 :: reserved1 [11:08] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_167_reserved1_MASK 0x00000f00
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_167_reserved1_SHIFT 8
-
-/* MEMC_ARB_1 :: CLIENT_INFO_167 :: PR_TAG [07:00] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_167_PR_TAG_MASK 0x000000ff
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_167_PR_TAG_SHIFT 0
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_167_PR_TAG_DEFAULT 0x00000000
-
-/***************************************************************************
- *CLIENT_INFO_168 - Client Programming register for client 168.
- ***************************************************************************/
-/* MEMC_ARB_1 :: CLIENT_INFO_168 :: RR_EN [31:31] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_168_RR_EN_MASK 0x80000000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_168_RR_EN_SHIFT 31
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_168_RR_EN_DEFAULT 0x00000001
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_168_RR_EN_DISABLED 0
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_168_RR_EN_ENABLED 1
-
-/* MEMC_ARB_1 :: CLIENT_INFO_168 :: reserved0 [30:30] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_168_reserved0_MASK 0x40000000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_168_reserved0_SHIFT 30
-
-/* MEMC_ARB_1 :: CLIENT_INFO_168 :: BO_VAL [29:12] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_168_BO_VAL_MASK 0x3ffff000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_168_BO_VAL_SHIFT 12
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_168_BO_VAL_DEFAULT 0x00000000
-
-/* MEMC_ARB_1 :: CLIENT_INFO_168 :: reserved1 [11:08] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_168_reserved1_MASK 0x00000f00
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_168_reserved1_SHIFT 8
-
-/* MEMC_ARB_1 :: CLIENT_INFO_168 :: PR_TAG [07:00] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_168_PR_TAG_MASK 0x000000ff
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_168_PR_TAG_SHIFT 0
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_168_PR_TAG_DEFAULT 0x00000000
-
-/***************************************************************************
- *CLIENT_INFO_169 - Client Programming register for client 169.
- ***************************************************************************/
-/* MEMC_ARB_1 :: CLIENT_INFO_169 :: RR_EN [31:31] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_169_RR_EN_MASK 0x80000000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_169_RR_EN_SHIFT 31
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_169_RR_EN_DEFAULT 0x00000001
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_169_RR_EN_DISABLED 0
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_169_RR_EN_ENABLED 1
-
-/* MEMC_ARB_1 :: CLIENT_INFO_169 :: reserved0 [30:30] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_169_reserved0_MASK 0x40000000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_169_reserved0_SHIFT 30
-
-/* MEMC_ARB_1 :: CLIENT_INFO_169 :: BO_VAL [29:12] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_169_BO_VAL_MASK 0x3ffff000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_169_BO_VAL_SHIFT 12
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_169_BO_VAL_DEFAULT 0x00000000
-
-/* MEMC_ARB_1 :: CLIENT_INFO_169 :: reserved1 [11:08] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_169_reserved1_MASK 0x00000f00
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_169_reserved1_SHIFT 8
-
-/* MEMC_ARB_1 :: CLIENT_INFO_169 :: PR_TAG [07:00] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_169_PR_TAG_MASK 0x000000ff
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_169_PR_TAG_SHIFT 0
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_169_PR_TAG_DEFAULT 0x00000000
-
-/***************************************************************************
- *CLIENT_INFO_170 - Client Programming register for client 170.
- ***************************************************************************/
-/* MEMC_ARB_1 :: CLIENT_INFO_170 :: RR_EN [31:31] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_170_RR_EN_MASK 0x80000000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_170_RR_EN_SHIFT 31
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_170_RR_EN_DEFAULT 0x00000001
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_170_RR_EN_DISABLED 0
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_170_RR_EN_ENABLED 1
-
-/* MEMC_ARB_1 :: CLIENT_INFO_170 :: reserved0 [30:30] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_170_reserved0_MASK 0x40000000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_170_reserved0_SHIFT 30
-
-/* MEMC_ARB_1 :: CLIENT_INFO_170 :: BO_VAL [29:12] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_170_BO_VAL_MASK 0x3ffff000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_170_BO_VAL_SHIFT 12
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_170_BO_VAL_DEFAULT 0x00000000
-
-/* MEMC_ARB_1 :: CLIENT_INFO_170 :: reserved1 [11:08] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_170_reserved1_MASK 0x00000f00
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_170_reserved1_SHIFT 8
-
-/* MEMC_ARB_1 :: CLIENT_INFO_170 :: PR_TAG [07:00] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_170_PR_TAG_MASK 0x000000ff
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_170_PR_TAG_SHIFT 0
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_170_PR_TAG_DEFAULT 0x00000000
-
-/***************************************************************************
- *CLIENT_INFO_171 - Client Programming register for client 171.
- ***************************************************************************/
-/* MEMC_ARB_1 :: CLIENT_INFO_171 :: RR_EN [31:31] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_171_RR_EN_MASK 0x80000000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_171_RR_EN_SHIFT 31
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_171_RR_EN_DEFAULT 0x00000001
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_171_RR_EN_DISABLED 0
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_171_RR_EN_ENABLED 1
-
-/* MEMC_ARB_1 :: CLIENT_INFO_171 :: reserved0 [30:30] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_171_reserved0_MASK 0x40000000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_171_reserved0_SHIFT 30
-
-/* MEMC_ARB_1 :: CLIENT_INFO_171 :: BO_VAL [29:12] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_171_BO_VAL_MASK 0x3ffff000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_171_BO_VAL_SHIFT 12
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_171_BO_VAL_DEFAULT 0x00000000
-
-/* MEMC_ARB_1 :: CLIENT_INFO_171 :: reserved1 [11:08] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_171_reserved1_MASK 0x00000f00
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_171_reserved1_SHIFT 8
-
-/* MEMC_ARB_1 :: CLIENT_INFO_171 :: PR_TAG [07:00] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_171_PR_TAG_MASK 0x000000ff
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_171_PR_TAG_SHIFT 0
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_171_PR_TAG_DEFAULT 0x00000000
-
-/***************************************************************************
- *CLIENT_INFO_172 - Client Programming register for client 172.
- ***************************************************************************/
-/* MEMC_ARB_1 :: CLIENT_INFO_172 :: RR_EN [31:31] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_172_RR_EN_MASK 0x80000000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_172_RR_EN_SHIFT 31
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_172_RR_EN_DEFAULT 0x00000001
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_172_RR_EN_DISABLED 0
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_172_RR_EN_ENABLED 1
-
-/* MEMC_ARB_1 :: CLIENT_INFO_172 :: reserved0 [30:30] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_172_reserved0_MASK 0x40000000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_172_reserved0_SHIFT 30
-
-/* MEMC_ARB_1 :: CLIENT_INFO_172 :: BO_VAL [29:12] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_172_BO_VAL_MASK 0x3ffff000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_172_BO_VAL_SHIFT 12
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_172_BO_VAL_DEFAULT 0x00000000
-
-/* MEMC_ARB_1 :: CLIENT_INFO_172 :: reserved1 [11:08] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_172_reserved1_MASK 0x00000f00
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_172_reserved1_SHIFT 8
-
-/* MEMC_ARB_1 :: CLIENT_INFO_172 :: PR_TAG [07:00] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_172_PR_TAG_MASK 0x000000ff
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_172_PR_TAG_SHIFT 0
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_172_PR_TAG_DEFAULT 0x00000000
-
-/***************************************************************************
- *CLIENT_INFO_173 - Client Programming register for client 173.
- ***************************************************************************/
-/* MEMC_ARB_1 :: CLIENT_INFO_173 :: RR_EN [31:31] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_173_RR_EN_MASK 0x80000000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_173_RR_EN_SHIFT 31
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_173_RR_EN_DEFAULT 0x00000001
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_173_RR_EN_DISABLED 0
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_173_RR_EN_ENABLED 1
-
-/* MEMC_ARB_1 :: CLIENT_INFO_173 :: reserved0 [30:30] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_173_reserved0_MASK 0x40000000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_173_reserved0_SHIFT 30
-
-/* MEMC_ARB_1 :: CLIENT_INFO_173 :: BO_VAL [29:12] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_173_BO_VAL_MASK 0x3ffff000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_173_BO_VAL_SHIFT 12
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_173_BO_VAL_DEFAULT 0x00000000
-
-/* MEMC_ARB_1 :: CLIENT_INFO_173 :: reserved1 [11:08] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_173_reserved1_MASK 0x00000f00
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_173_reserved1_SHIFT 8
-
-/* MEMC_ARB_1 :: CLIENT_INFO_173 :: PR_TAG [07:00] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_173_PR_TAG_MASK 0x000000ff
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_173_PR_TAG_SHIFT 0
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_173_PR_TAG_DEFAULT 0x00000000
-
-/***************************************************************************
- *CLIENT_INFO_174 - Client Programming register for client 174.
- ***************************************************************************/
-/* MEMC_ARB_1 :: CLIENT_INFO_174 :: RR_EN [31:31] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_174_RR_EN_MASK 0x80000000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_174_RR_EN_SHIFT 31
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_174_RR_EN_DEFAULT 0x00000001
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_174_RR_EN_DISABLED 0
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_174_RR_EN_ENABLED 1
-
-/* MEMC_ARB_1 :: CLIENT_INFO_174 :: reserved0 [30:30] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_174_reserved0_MASK 0x40000000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_174_reserved0_SHIFT 30
-
-/* MEMC_ARB_1 :: CLIENT_INFO_174 :: BO_VAL [29:12] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_174_BO_VAL_MASK 0x3ffff000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_174_BO_VAL_SHIFT 12
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_174_BO_VAL_DEFAULT 0x00000000
-
-/* MEMC_ARB_1 :: CLIENT_INFO_174 :: reserved1 [11:08] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_174_reserved1_MASK 0x00000f00
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_174_reserved1_SHIFT 8
-
-/* MEMC_ARB_1 :: CLIENT_INFO_174 :: PR_TAG [07:00] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_174_PR_TAG_MASK 0x000000ff
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_174_PR_TAG_SHIFT 0
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_174_PR_TAG_DEFAULT 0x00000000
-
-/***************************************************************************
- *CLIENT_INFO_175 - Client Programming register for client 175.
- ***************************************************************************/
-/* MEMC_ARB_1 :: CLIENT_INFO_175 :: RR_EN [31:31] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_175_RR_EN_MASK 0x80000000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_175_RR_EN_SHIFT 31
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_175_RR_EN_DEFAULT 0x00000001
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_175_RR_EN_DISABLED 0
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_175_RR_EN_ENABLED 1
-
-/* MEMC_ARB_1 :: CLIENT_INFO_175 :: reserved0 [30:30] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_175_reserved0_MASK 0x40000000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_175_reserved0_SHIFT 30
-
-/* MEMC_ARB_1 :: CLIENT_INFO_175 :: BO_VAL [29:12] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_175_BO_VAL_MASK 0x3ffff000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_175_BO_VAL_SHIFT 12
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_175_BO_VAL_DEFAULT 0x00000000
-
-/* MEMC_ARB_1 :: CLIENT_INFO_175 :: reserved1 [11:08] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_175_reserved1_MASK 0x00000f00
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_175_reserved1_SHIFT 8
-
-/* MEMC_ARB_1 :: CLIENT_INFO_175 :: PR_TAG [07:00] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_175_PR_TAG_MASK 0x000000ff
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_175_PR_TAG_SHIFT 0
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_175_PR_TAG_DEFAULT 0x00000000
-
-/***************************************************************************
- *CLIENT_INFO_176 - Client Programming register for client 176.
- ***************************************************************************/
-/* MEMC_ARB_1 :: CLIENT_INFO_176 :: RR_EN [31:31] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_176_RR_EN_MASK 0x80000000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_176_RR_EN_SHIFT 31
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_176_RR_EN_DEFAULT 0x00000001
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_176_RR_EN_DISABLED 0
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_176_RR_EN_ENABLED 1
-
-/* MEMC_ARB_1 :: CLIENT_INFO_176 :: reserved0 [30:30] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_176_reserved0_MASK 0x40000000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_176_reserved0_SHIFT 30
-
-/* MEMC_ARB_1 :: CLIENT_INFO_176 :: BO_VAL [29:12] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_176_BO_VAL_MASK 0x3ffff000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_176_BO_VAL_SHIFT 12
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_176_BO_VAL_DEFAULT 0x00000000
-
-/* MEMC_ARB_1 :: CLIENT_INFO_176 :: reserved1 [11:08] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_176_reserved1_MASK 0x00000f00
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_176_reserved1_SHIFT 8
-
-/* MEMC_ARB_1 :: CLIENT_INFO_176 :: PR_TAG [07:00] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_176_PR_TAG_MASK 0x000000ff
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_176_PR_TAG_SHIFT 0
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_176_PR_TAG_DEFAULT 0x00000000
-
-/***************************************************************************
- *CLIENT_INFO_177 - Client Programming register for client 177.
- ***************************************************************************/
-/* MEMC_ARB_1 :: CLIENT_INFO_177 :: RR_EN [31:31] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_177_RR_EN_MASK 0x80000000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_177_RR_EN_SHIFT 31
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_177_RR_EN_DEFAULT 0x00000001
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_177_RR_EN_DISABLED 0
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_177_RR_EN_ENABLED 1
-
-/* MEMC_ARB_1 :: CLIENT_INFO_177 :: reserved0 [30:30] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_177_reserved0_MASK 0x40000000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_177_reserved0_SHIFT 30
-
-/* MEMC_ARB_1 :: CLIENT_INFO_177 :: BO_VAL [29:12] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_177_BO_VAL_MASK 0x3ffff000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_177_BO_VAL_SHIFT 12
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_177_BO_VAL_DEFAULT 0x00000000
-
-/* MEMC_ARB_1 :: CLIENT_INFO_177 :: reserved1 [11:08] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_177_reserved1_MASK 0x00000f00
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_177_reserved1_SHIFT 8
-
-/* MEMC_ARB_1 :: CLIENT_INFO_177 :: PR_TAG [07:00] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_177_PR_TAG_MASK 0x000000ff
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_177_PR_TAG_SHIFT 0
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_177_PR_TAG_DEFAULT 0x00000000
-
-/***************************************************************************
- *CLIENT_INFO_178 - Client Programming register for client 178.
- ***************************************************************************/
-/* MEMC_ARB_1 :: CLIENT_INFO_178 :: RR_EN [31:31] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_178_RR_EN_MASK 0x80000000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_178_RR_EN_SHIFT 31
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_178_RR_EN_DEFAULT 0x00000001
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_178_RR_EN_DISABLED 0
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_178_RR_EN_ENABLED 1
-
-/* MEMC_ARB_1 :: CLIENT_INFO_178 :: reserved0 [30:30] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_178_reserved0_MASK 0x40000000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_178_reserved0_SHIFT 30
-
-/* MEMC_ARB_1 :: CLIENT_INFO_178 :: BO_VAL [29:12] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_178_BO_VAL_MASK 0x3ffff000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_178_BO_VAL_SHIFT 12
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_178_BO_VAL_DEFAULT 0x00000000
-
-/* MEMC_ARB_1 :: CLIENT_INFO_178 :: reserved1 [11:08] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_178_reserved1_MASK 0x00000f00
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_178_reserved1_SHIFT 8
-
-/* MEMC_ARB_1 :: CLIENT_INFO_178 :: PR_TAG [07:00] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_178_PR_TAG_MASK 0x000000ff
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_178_PR_TAG_SHIFT 0
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_178_PR_TAG_DEFAULT 0x00000000
-
-/***************************************************************************
- *CLIENT_INFO_179 - Client Programming register for client 179.
- ***************************************************************************/
-/* MEMC_ARB_1 :: CLIENT_INFO_179 :: RR_EN [31:31] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_179_RR_EN_MASK 0x80000000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_179_RR_EN_SHIFT 31
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_179_RR_EN_DEFAULT 0x00000001
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_179_RR_EN_DISABLED 0
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_179_RR_EN_ENABLED 1
-
-/* MEMC_ARB_1 :: CLIENT_INFO_179 :: reserved0 [30:30] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_179_reserved0_MASK 0x40000000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_179_reserved0_SHIFT 30
-
-/* MEMC_ARB_1 :: CLIENT_INFO_179 :: BO_VAL [29:12] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_179_BO_VAL_MASK 0x3ffff000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_179_BO_VAL_SHIFT 12
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_179_BO_VAL_DEFAULT 0x00000000
-
-/* MEMC_ARB_1 :: CLIENT_INFO_179 :: reserved1 [11:08] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_179_reserved1_MASK 0x00000f00
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_179_reserved1_SHIFT 8
-
-/* MEMC_ARB_1 :: CLIENT_INFO_179 :: PR_TAG [07:00] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_179_PR_TAG_MASK 0x000000ff
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_179_PR_TAG_SHIFT 0
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_179_PR_TAG_DEFAULT 0x00000000
-
-/***************************************************************************
- *CLIENT_INFO_180 - Client Programming register for client 180.
- ***************************************************************************/
-/* MEMC_ARB_1 :: CLIENT_INFO_180 :: RR_EN [31:31] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_180_RR_EN_MASK 0x80000000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_180_RR_EN_SHIFT 31
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_180_RR_EN_DEFAULT 0x00000001
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_180_RR_EN_DISABLED 0
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_180_RR_EN_ENABLED 1
-
-/* MEMC_ARB_1 :: CLIENT_INFO_180 :: reserved0 [30:30] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_180_reserved0_MASK 0x40000000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_180_reserved0_SHIFT 30
-
-/* MEMC_ARB_1 :: CLIENT_INFO_180 :: BO_VAL [29:12] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_180_BO_VAL_MASK 0x3ffff000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_180_BO_VAL_SHIFT 12
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_180_BO_VAL_DEFAULT 0x00000000
-
-/* MEMC_ARB_1 :: CLIENT_INFO_180 :: reserved1 [11:08] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_180_reserved1_MASK 0x00000f00
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_180_reserved1_SHIFT 8
-
-/* MEMC_ARB_1 :: CLIENT_INFO_180 :: PR_TAG [07:00] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_180_PR_TAG_MASK 0x000000ff
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_180_PR_TAG_SHIFT 0
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_180_PR_TAG_DEFAULT 0x00000000
-
-/***************************************************************************
- *CLIENT_INFO_181 - Client Programming register for client 181.
- ***************************************************************************/
-/* MEMC_ARB_1 :: CLIENT_INFO_181 :: RR_EN [31:31] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_181_RR_EN_MASK 0x80000000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_181_RR_EN_SHIFT 31
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_181_RR_EN_DEFAULT 0x00000001
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_181_RR_EN_DISABLED 0
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_181_RR_EN_ENABLED 1
-
-/* MEMC_ARB_1 :: CLIENT_INFO_181 :: reserved0 [30:30] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_181_reserved0_MASK 0x40000000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_181_reserved0_SHIFT 30
-
-/* MEMC_ARB_1 :: CLIENT_INFO_181 :: BO_VAL [29:12] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_181_BO_VAL_MASK 0x3ffff000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_181_BO_VAL_SHIFT 12
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_181_BO_VAL_DEFAULT 0x00000000
-
-/* MEMC_ARB_1 :: CLIENT_INFO_181 :: reserved1 [11:08] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_181_reserved1_MASK 0x00000f00
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_181_reserved1_SHIFT 8
-
-/* MEMC_ARB_1 :: CLIENT_INFO_181 :: PR_TAG [07:00] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_181_PR_TAG_MASK 0x000000ff
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_181_PR_TAG_SHIFT 0
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_181_PR_TAG_DEFAULT 0x00000000
-
-/***************************************************************************
- *CLIENT_INFO_182 - Client Programming register for client 182.
- ***************************************************************************/
-/* MEMC_ARB_1 :: CLIENT_INFO_182 :: RR_EN [31:31] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_182_RR_EN_MASK 0x80000000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_182_RR_EN_SHIFT 31
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_182_RR_EN_DEFAULT 0x00000001
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_182_RR_EN_DISABLED 0
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_182_RR_EN_ENABLED 1
-
-/* MEMC_ARB_1 :: CLIENT_INFO_182 :: reserved0 [30:30] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_182_reserved0_MASK 0x40000000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_182_reserved0_SHIFT 30
-
-/* MEMC_ARB_1 :: CLIENT_INFO_182 :: BO_VAL [29:12] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_182_BO_VAL_MASK 0x3ffff000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_182_BO_VAL_SHIFT 12
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_182_BO_VAL_DEFAULT 0x00000000
-
-/* MEMC_ARB_1 :: CLIENT_INFO_182 :: reserved1 [11:08] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_182_reserved1_MASK 0x00000f00
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_182_reserved1_SHIFT 8
-
-/* MEMC_ARB_1 :: CLIENT_INFO_182 :: PR_TAG [07:00] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_182_PR_TAG_MASK 0x000000ff
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_182_PR_TAG_SHIFT 0
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_182_PR_TAG_DEFAULT 0x00000000
-
-/***************************************************************************
- *CLIENT_INFO_183 - Client Programming register for client 183.
- ***************************************************************************/
-/* MEMC_ARB_1 :: CLIENT_INFO_183 :: RR_EN [31:31] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_183_RR_EN_MASK 0x80000000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_183_RR_EN_SHIFT 31
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_183_RR_EN_DEFAULT 0x00000001
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_183_RR_EN_DISABLED 0
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_183_RR_EN_ENABLED 1
-
-/* MEMC_ARB_1 :: CLIENT_INFO_183 :: reserved0 [30:30] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_183_reserved0_MASK 0x40000000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_183_reserved0_SHIFT 30
-
-/* MEMC_ARB_1 :: CLIENT_INFO_183 :: BO_VAL [29:12] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_183_BO_VAL_MASK 0x3ffff000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_183_BO_VAL_SHIFT 12
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_183_BO_VAL_DEFAULT 0x00000000
-
-/* MEMC_ARB_1 :: CLIENT_INFO_183 :: reserved1 [11:08] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_183_reserved1_MASK 0x00000f00
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_183_reserved1_SHIFT 8
-
-/* MEMC_ARB_1 :: CLIENT_INFO_183 :: PR_TAG [07:00] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_183_PR_TAG_MASK 0x000000ff
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_183_PR_TAG_SHIFT 0
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_183_PR_TAG_DEFAULT 0x00000000
-
-/***************************************************************************
- *CLIENT_INFO_184 - Client Programming register for client 184.
- ***************************************************************************/
-/* MEMC_ARB_1 :: CLIENT_INFO_184 :: RR_EN [31:31] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_184_RR_EN_MASK 0x80000000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_184_RR_EN_SHIFT 31
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_184_RR_EN_DEFAULT 0x00000001
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_184_RR_EN_DISABLED 0
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_184_RR_EN_ENABLED 1
-
-/* MEMC_ARB_1 :: CLIENT_INFO_184 :: reserved0 [30:30] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_184_reserved0_MASK 0x40000000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_184_reserved0_SHIFT 30
-
-/* MEMC_ARB_1 :: CLIENT_INFO_184 :: BO_VAL [29:12] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_184_BO_VAL_MASK 0x3ffff000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_184_BO_VAL_SHIFT 12
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_184_BO_VAL_DEFAULT 0x00000000
-
-/* MEMC_ARB_1 :: CLIENT_INFO_184 :: reserved1 [11:08] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_184_reserved1_MASK 0x00000f00
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_184_reserved1_SHIFT 8
-
-/* MEMC_ARB_1 :: CLIENT_INFO_184 :: PR_TAG [07:00] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_184_PR_TAG_MASK 0x000000ff
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_184_PR_TAG_SHIFT 0
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_184_PR_TAG_DEFAULT 0x00000000
-
-/***************************************************************************
- *CLIENT_INFO_185 - Client Programming register for client 185.
- ***************************************************************************/
-/* MEMC_ARB_1 :: CLIENT_INFO_185 :: RR_EN [31:31] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_185_RR_EN_MASK 0x80000000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_185_RR_EN_SHIFT 31
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_185_RR_EN_DEFAULT 0x00000001
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_185_RR_EN_DISABLED 0
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_185_RR_EN_ENABLED 1
-
-/* MEMC_ARB_1 :: CLIENT_INFO_185 :: reserved0 [30:30] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_185_reserved0_MASK 0x40000000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_185_reserved0_SHIFT 30
-
-/* MEMC_ARB_1 :: CLIENT_INFO_185 :: BO_VAL [29:12] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_185_BO_VAL_MASK 0x3ffff000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_185_BO_VAL_SHIFT 12
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_185_BO_VAL_DEFAULT 0x00000000
-
-/* MEMC_ARB_1 :: CLIENT_INFO_185 :: reserved1 [11:08] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_185_reserved1_MASK 0x00000f00
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_185_reserved1_SHIFT 8
-
-/* MEMC_ARB_1 :: CLIENT_INFO_185 :: PR_TAG [07:00] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_185_PR_TAG_MASK 0x000000ff
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_185_PR_TAG_SHIFT 0
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_185_PR_TAG_DEFAULT 0x00000000
-
-/***************************************************************************
- *CLIENT_INFO_186 - Client Programming register for client 186.
- ***************************************************************************/
-/* MEMC_ARB_1 :: CLIENT_INFO_186 :: RR_EN [31:31] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_186_RR_EN_MASK 0x80000000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_186_RR_EN_SHIFT 31
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_186_RR_EN_DEFAULT 0x00000001
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_186_RR_EN_DISABLED 0
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_186_RR_EN_ENABLED 1
-
-/* MEMC_ARB_1 :: CLIENT_INFO_186 :: reserved0 [30:30] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_186_reserved0_MASK 0x40000000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_186_reserved0_SHIFT 30
-
-/* MEMC_ARB_1 :: CLIENT_INFO_186 :: BO_VAL [29:12] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_186_BO_VAL_MASK 0x3ffff000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_186_BO_VAL_SHIFT 12
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_186_BO_VAL_DEFAULT 0x00000000
-
-/* MEMC_ARB_1 :: CLIENT_INFO_186 :: reserved1 [11:08] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_186_reserved1_MASK 0x00000f00
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_186_reserved1_SHIFT 8
-
-/* MEMC_ARB_1 :: CLIENT_INFO_186 :: PR_TAG [07:00] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_186_PR_TAG_MASK 0x000000ff
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_186_PR_TAG_SHIFT 0
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_186_PR_TAG_DEFAULT 0x00000000
-
-/***************************************************************************
- *CLIENT_INFO_187 - Client Programming register for client 187.
- ***************************************************************************/
-/* MEMC_ARB_1 :: CLIENT_INFO_187 :: RR_EN [31:31] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_187_RR_EN_MASK 0x80000000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_187_RR_EN_SHIFT 31
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_187_RR_EN_DEFAULT 0x00000001
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_187_RR_EN_DISABLED 0
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_187_RR_EN_ENABLED 1
-
-/* MEMC_ARB_1 :: CLIENT_INFO_187 :: reserved0 [30:30] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_187_reserved0_MASK 0x40000000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_187_reserved0_SHIFT 30
-
-/* MEMC_ARB_1 :: CLIENT_INFO_187 :: BO_VAL [29:12] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_187_BO_VAL_MASK 0x3ffff000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_187_BO_VAL_SHIFT 12
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_187_BO_VAL_DEFAULT 0x00000000
-
-/* MEMC_ARB_1 :: CLIENT_INFO_187 :: reserved1 [11:08] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_187_reserved1_MASK 0x00000f00
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_187_reserved1_SHIFT 8
-
-/* MEMC_ARB_1 :: CLIENT_INFO_187 :: PR_TAG [07:00] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_187_PR_TAG_MASK 0x000000ff
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_187_PR_TAG_SHIFT 0
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_187_PR_TAG_DEFAULT 0x00000000
-
-/***************************************************************************
- *CLIENT_INFO_188 - Client Programming register for client 188.
- ***************************************************************************/
-/* MEMC_ARB_1 :: CLIENT_INFO_188 :: RR_EN [31:31] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_188_RR_EN_MASK 0x80000000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_188_RR_EN_SHIFT 31
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_188_RR_EN_DEFAULT 0x00000001
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_188_RR_EN_DISABLED 0
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_188_RR_EN_ENABLED 1
-
-/* MEMC_ARB_1 :: CLIENT_INFO_188 :: reserved0 [30:30] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_188_reserved0_MASK 0x40000000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_188_reserved0_SHIFT 30
-
-/* MEMC_ARB_1 :: CLIENT_INFO_188 :: BO_VAL [29:12] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_188_BO_VAL_MASK 0x3ffff000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_188_BO_VAL_SHIFT 12
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_188_BO_VAL_DEFAULT 0x00000000
-
-/* MEMC_ARB_1 :: CLIENT_INFO_188 :: reserved1 [11:08] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_188_reserved1_MASK 0x00000f00
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_188_reserved1_SHIFT 8
-
-/* MEMC_ARB_1 :: CLIENT_INFO_188 :: PR_TAG [07:00] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_188_PR_TAG_MASK 0x000000ff
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_188_PR_TAG_SHIFT 0
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_188_PR_TAG_DEFAULT 0x00000000
-
-/***************************************************************************
- *CLIENT_INFO_189 - Client Programming register for client 189.
- ***************************************************************************/
-/* MEMC_ARB_1 :: CLIENT_INFO_189 :: RR_EN [31:31] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_189_RR_EN_MASK 0x80000000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_189_RR_EN_SHIFT 31
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_189_RR_EN_DEFAULT 0x00000001
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_189_RR_EN_DISABLED 0
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_189_RR_EN_ENABLED 1
-
-/* MEMC_ARB_1 :: CLIENT_INFO_189 :: reserved0 [30:30] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_189_reserved0_MASK 0x40000000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_189_reserved0_SHIFT 30
-
-/* MEMC_ARB_1 :: CLIENT_INFO_189 :: BO_VAL [29:12] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_189_BO_VAL_MASK 0x3ffff000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_189_BO_VAL_SHIFT 12
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_189_BO_VAL_DEFAULT 0x00000000
-
-/* MEMC_ARB_1 :: CLIENT_INFO_189 :: reserved1 [11:08] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_189_reserved1_MASK 0x00000f00
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_189_reserved1_SHIFT 8
-
-/* MEMC_ARB_1 :: CLIENT_INFO_189 :: PR_TAG [07:00] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_189_PR_TAG_MASK 0x000000ff
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_189_PR_TAG_SHIFT 0
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_189_PR_TAG_DEFAULT 0x00000000
-
-/***************************************************************************
- *CLIENT_INFO_190 - Client Programming register for client 190.
- ***************************************************************************/
-/* MEMC_ARB_1 :: CLIENT_INFO_190 :: RR_EN [31:31] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_190_RR_EN_MASK 0x80000000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_190_RR_EN_SHIFT 31
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_190_RR_EN_DEFAULT 0x00000001
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_190_RR_EN_DISABLED 0
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_190_RR_EN_ENABLED 1
-
-/* MEMC_ARB_1 :: CLIENT_INFO_190 :: reserved0 [30:30] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_190_reserved0_MASK 0x40000000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_190_reserved0_SHIFT 30
-
-/* MEMC_ARB_1 :: CLIENT_INFO_190 :: BO_VAL [29:12] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_190_BO_VAL_MASK 0x3ffff000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_190_BO_VAL_SHIFT 12
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_190_BO_VAL_DEFAULT 0x00000000
-
-/* MEMC_ARB_1 :: CLIENT_INFO_190 :: reserved1 [11:08] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_190_reserved1_MASK 0x00000f00
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_190_reserved1_SHIFT 8
-
-/* MEMC_ARB_1 :: CLIENT_INFO_190 :: PR_TAG [07:00] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_190_PR_TAG_MASK 0x000000ff
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_190_PR_TAG_SHIFT 0
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_190_PR_TAG_DEFAULT 0x00000000
-
-/***************************************************************************
- *CLIENT_INFO_191 - Client Programming register for client 191.
- ***************************************************************************/
-/* MEMC_ARB_1 :: CLIENT_INFO_191 :: RR_EN [31:31] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_191_RR_EN_MASK 0x80000000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_191_RR_EN_SHIFT 31
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_191_RR_EN_DEFAULT 0x00000001
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_191_RR_EN_DISABLED 0
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_191_RR_EN_ENABLED 1
-
-/* MEMC_ARB_1 :: CLIENT_INFO_191 :: reserved0 [30:30] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_191_reserved0_MASK 0x40000000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_191_reserved0_SHIFT 30
-
-/* MEMC_ARB_1 :: CLIENT_INFO_191 :: BO_VAL [29:12] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_191_BO_VAL_MASK 0x3ffff000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_191_BO_VAL_SHIFT 12
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_191_BO_VAL_DEFAULT 0x00000000
-
-/* MEMC_ARB_1 :: CLIENT_INFO_191 :: reserved1 [11:08] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_191_reserved1_MASK 0x00000f00
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_191_reserved1_SHIFT 8
-
-/* MEMC_ARB_1 :: CLIENT_INFO_191 :: PR_TAG [07:00] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_191_PR_TAG_MASK 0x000000ff
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_191_PR_TAG_SHIFT 0
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_191_PR_TAG_DEFAULT 0x00000000
-
-/***************************************************************************
- *CLIENT_INFO_192 - Client Programming register for client 192.
- ***************************************************************************/
-/* MEMC_ARB_1 :: CLIENT_INFO_192 :: RR_EN [31:31] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_192_RR_EN_MASK 0x80000000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_192_RR_EN_SHIFT 31
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_192_RR_EN_DEFAULT 0x00000001
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_192_RR_EN_DISABLED 0
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_192_RR_EN_ENABLED 1
-
-/* MEMC_ARB_1 :: CLIENT_INFO_192 :: reserved0 [30:30] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_192_reserved0_MASK 0x40000000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_192_reserved0_SHIFT 30
-
-/* MEMC_ARB_1 :: CLIENT_INFO_192 :: BO_VAL [29:12] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_192_BO_VAL_MASK 0x3ffff000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_192_BO_VAL_SHIFT 12
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_192_BO_VAL_DEFAULT 0x00000000
-
-/* MEMC_ARB_1 :: CLIENT_INFO_192 :: reserved1 [11:08] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_192_reserved1_MASK 0x00000f00
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_192_reserved1_SHIFT 8
-
-/* MEMC_ARB_1 :: CLIENT_INFO_192 :: PR_TAG [07:00] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_192_PR_TAG_MASK 0x000000ff
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_192_PR_TAG_SHIFT 0
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_192_PR_TAG_DEFAULT 0x00000000
-
-/***************************************************************************
- *CLIENT_INFO_193 - Client Programming register for client 193.
- ***************************************************************************/
-/* MEMC_ARB_1 :: CLIENT_INFO_193 :: RR_EN [31:31] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_193_RR_EN_MASK 0x80000000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_193_RR_EN_SHIFT 31
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_193_RR_EN_DEFAULT 0x00000001
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_193_RR_EN_DISABLED 0
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_193_RR_EN_ENABLED 1
-
-/* MEMC_ARB_1 :: CLIENT_INFO_193 :: reserved0 [30:30] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_193_reserved0_MASK 0x40000000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_193_reserved0_SHIFT 30
-
-/* MEMC_ARB_1 :: CLIENT_INFO_193 :: BO_VAL [29:12] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_193_BO_VAL_MASK 0x3ffff000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_193_BO_VAL_SHIFT 12
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_193_BO_VAL_DEFAULT 0x00000000
-
-/* MEMC_ARB_1 :: CLIENT_INFO_193 :: reserved1 [11:08] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_193_reserved1_MASK 0x00000f00
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_193_reserved1_SHIFT 8
-
-/* MEMC_ARB_1 :: CLIENT_INFO_193 :: PR_TAG [07:00] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_193_PR_TAG_MASK 0x000000ff
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_193_PR_TAG_SHIFT 0
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_193_PR_TAG_DEFAULT 0x00000000
-
-/***************************************************************************
- *CLIENT_INFO_194 - Client Programming register for client 194.
- ***************************************************************************/
-/* MEMC_ARB_1 :: CLIENT_INFO_194 :: RR_EN [31:31] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_194_RR_EN_MASK 0x80000000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_194_RR_EN_SHIFT 31
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_194_RR_EN_DEFAULT 0x00000001
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_194_RR_EN_DISABLED 0
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_194_RR_EN_ENABLED 1
-
-/* MEMC_ARB_1 :: CLIENT_INFO_194 :: reserved0 [30:30] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_194_reserved0_MASK 0x40000000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_194_reserved0_SHIFT 30
-
-/* MEMC_ARB_1 :: CLIENT_INFO_194 :: BO_VAL [29:12] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_194_BO_VAL_MASK 0x3ffff000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_194_BO_VAL_SHIFT 12
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_194_BO_VAL_DEFAULT 0x00000000
-
-/* MEMC_ARB_1 :: CLIENT_INFO_194 :: reserved1 [11:08] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_194_reserved1_MASK 0x00000f00
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_194_reserved1_SHIFT 8
-
-/* MEMC_ARB_1 :: CLIENT_INFO_194 :: PR_TAG [07:00] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_194_PR_TAG_MASK 0x000000ff
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_194_PR_TAG_SHIFT 0
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_194_PR_TAG_DEFAULT 0x00000000
-
-/***************************************************************************
- *CLIENT_INFO_195 - Client Programming register for client 195.
- ***************************************************************************/
-/* MEMC_ARB_1 :: CLIENT_INFO_195 :: RR_EN [31:31] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_195_RR_EN_MASK 0x80000000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_195_RR_EN_SHIFT 31
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_195_RR_EN_DEFAULT 0x00000001
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_195_RR_EN_DISABLED 0
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_195_RR_EN_ENABLED 1
-
-/* MEMC_ARB_1 :: CLIENT_INFO_195 :: reserved0 [30:30] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_195_reserved0_MASK 0x40000000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_195_reserved0_SHIFT 30
-
-/* MEMC_ARB_1 :: CLIENT_INFO_195 :: BO_VAL [29:12] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_195_BO_VAL_MASK 0x3ffff000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_195_BO_VAL_SHIFT 12
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_195_BO_VAL_DEFAULT 0x00000000
-
-/* MEMC_ARB_1 :: CLIENT_INFO_195 :: reserved1 [11:08] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_195_reserved1_MASK 0x00000f00
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_195_reserved1_SHIFT 8
-
-/* MEMC_ARB_1 :: CLIENT_INFO_195 :: PR_TAG [07:00] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_195_PR_TAG_MASK 0x000000ff
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_195_PR_TAG_SHIFT 0
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_195_PR_TAG_DEFAULT 0x00000000
-
-/***************************************************************************
- *CLIENT_INFO_196 - Client Programming register for client 196.
- ***************************************************************************/
-/* MEMC_ARB_1 :: CLIENT_INFO_196 :: RR_EN [31:31] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_196_RR_EN_MASK 0x80000000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_196_RR_EN_SHIFT 31
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_196_RR_EN_DEFAULT 0x00000001
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_196_RR_EN_DISABLED 0
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_196_RR_EN_ENABLED 1
-
-/* MEMC_ARB_1 :: CLIENT_INFO_196 :: reserved0 [30:30] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_196_reserved0_MASK 0x40000000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_196_reserved0_SHIFT 30
-
-/* MEMC_ARB_1 :: CLIENT_INFO_196 :: BO_VAL [29:12] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_196_BO_VAL_MASK 0x3ffff000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_196_BO_VAL_SHIFT 12
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_196_BO_VAL_DEFAULT 0x00000000
-
-/* MEMC_ARB_1 :: CLIENT_INFO_196 :: reserved1 [11:08] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_196_reserved1_MASK 0x00000f00
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_196_reserved1_SHIFT 8
-
-/* MEMC_ARB_1 :: CLIENT_INFO_196 :: PR_TAG [07:00] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_196_PR_TAG_MASK 0x000000ff
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_196_PR_TAG_SHIFT 0
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_196_PR_TAG_DEFAULT 0x00000000
-
-/***************************************************************************
- *CLIENT_INFO_197 - Client Programming register for client 197.
- ***************************************************************************/
-/* MEMC_ARB_1 :: CLIENT_INFO_197 :: RR_EN [31:31] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_197_RR_EN_MASK 0x80000000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_197_RR_EN_SHIFT 31
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_197_RR_EN_DEFAULT 0x00000001
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_197_RR_EN_DISABLED 0
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_197_RR_EN_ENABLED 1
-
-/* MEMC_ARB_1 :: CLIENT_INFO_197 :: reserved0 [30:30] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_197_reserved0_MASK 0x40000000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_197_reserved0_SHIFT 30
-
-/* MEMC_ARB_1 :: CLIENT_INFO_197 :: BO_VAL [29:12] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_197_BO_VAL_MASK 0x3ffff000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_197_BO_VAL_SHIFT 12
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_197_BO_VAL_DEFAULT 0x00000000
-
-/* MEMC_ARB_1 :: CLIENT_INFO_197 :: reserved1 [11:08] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_197_reserved1_MASK 0x00000f00
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_197_reserved1_SHIFT 8
-
-/* MEMC_ARB_1 :: CLIENT_INFO_197 :: PR_TAG [07:00] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_197_PR_TAG_MASK 0x000000ff
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_197_PR_TAG_SHIFT 0
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_197_PR_TAG_DEFAULT 0x00000000
-
-/***************************************************************************
- *CLIENT_INFO_198 - Client Programming register for client 198.
- ***************************************************************************/
-/* MEMC_ARB_1 :: CLIENT_INFO_198 :: RR_EN [31:31] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_198_RR_EN_MASK 0x80000000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_198_RR_EN_SHIFT 31
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_198_RR_EN_DEFAULT 0x00000001
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_198_RR_EN_DISABLED 0
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_198_RR_EN_ENABLED 1
-
-/* MEMC_ARB_1 :: CLIENT_INFO_198 :: reserved0 [30:30] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_198_reserved0_MASK 0x40000000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_198_reserved0_SHIFT 30
-
-/* MEMC_ARB_1 :: CLIENT_INFO_198 :: BO_VAL [29:12] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_198_BO_VAL_MASK 0x3ffff000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_198_BO_VAL_SHIFT 12
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_198_BO_VAL_DEFAULT 0x00000000
-
-/* MEMC_ARB_1 :: CLIENT_INFO_198 :: reserved1 [11:08] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_198_reserved1_MASK 0x00000f00
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_198_reserved1_SHIFT 8
-
-/* MEMC_ARB_1 :: CLIENT_INFO_198 :: PR_TAG [07:00] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_198_PR_TAG_MASK 0x000000ff
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_198_PR_TAG_SHIFT 0
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_198_PR_TAG_DEFAULT 0x00000000
-
-/***************************************************************************
- *CLIENT_INFO_199 - Client Programming register for client 199.
- ***************************************************************************/
-/* MEMC_ARB_1 :: CLIENT_INFO_199 :: RR_EN [31:31] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_199_RR_EN_MASK 0x80000000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_199_RR_EN_SHIFT 31
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_199_RR_EN_DEFAULT 0x00000001
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_199_RR_EN_DISABLED 0
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_199_RR_EN_ENABLED 1
-
-/* MEMC_ARB_1 :: CLIENT_INFO_199 :: reserved0 [30:30] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_199_reserved0_MASK 0x40000000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_199_reserved0_SHIFT 30
-
-/* MEMC_ARB_1 :: CLIENT_INFO_199 :: BO_VAL [29:12] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_199_BO_VAL_MASK 0x3ffff000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_199_BO_VAL_SHIFT 12
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_199_BO_VAL_DEFAULT 0x00000000
-
-/* MEMC_ARB_1 :: CLIENT_INFO_199 :: reserved1 [11:08] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_199_reserved1_MASK 0x00000f00
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_199_reserved1_SHIFT 8
-
-/* MEMC_ARB_1 :: CLIENT_INFO_199 :: PR_TAG [07:00] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_199_PR_TAG_MASK 0x000000ff
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_199_PR_TAG_SHIFT 0
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_199_PR_TAG_DEFAULT 0x00000000
-
-/***************************************************************************
- *CLIENT_INFO_200 - Client Programming register for client 200.
- ***************************************************************************/
-/* MEMC_ARB_1 :: CLIENT_INFO_200 :: RR_EN [31:31] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_200_RR_EN_MASK 0x80000000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_200_RR_EN_SHIFT 31
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_200_RR_EN_DEFAULT 0x00000001
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_200_RR_EN_DISABLED 0
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_200_RR_EN_ENABLED 1
-
-/* MEMC_ARB_1 :: CLIENT_INFO_200 :: reserved0 [30:30] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_200_reserved0_MASK 0x40000000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_200_reserved0_SHIFT 30
-
-/* MEMC_ARB_1 :: CLIENT_INFO_200 :: BO_VAL [29:12] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_200_BO_VAL_MASK 0x3ffff000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_200_BO_VAL_SHIFT 12
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_200_BO_VAL_DEFAULT 0x00000000
-
-/* MEMC_ARB_1 :: CLIENT_INFO_200 :: reserved1 [11:08] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_200_reserved1_MASK 0x00000f00
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_200_reserved1_SHIFT 8
-
-/* MEMC_ARB_1 :: CLIENT_INFO_200 :: PR_TAG [07:00] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_200_PR_TAG_MASK 0x000000ff
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_200_PR_TAG_SHIFT 0
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_200_PR_TAG_DEFAULT 0x00000000
-
-/***************************************************************************
- *CLIENT_INFO_201 - Client Programming register for client 201.
- ***************************************************************************/
-/* MEMC_ARB_1 :: CLIENT_INFO_201 :: RR_EN [31:31] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_201_RR_EN_MASK 0x80000000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_201_RR_EN_SHIFT 31
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_201_RR_EN_DEFAULT 0x00000001
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_201_RR_EN_DISABLED 0
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_201_RR_EN_ENABLED 1
-
-/* MEMC_ARB_1 :: CLIENT_INFO_201 :: reserved0 [30:30] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_201_reserved0_MASK 0x40000000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_201_reserved0_SHIFT 30
-
-/* MEMC_ARB_1 :: CLIENT_INFO_201 :: BO_VAL [29:12] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_201_BO_VAL_MASK 0x3ffff000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_201_BO_VAL_SHIFT 12
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_201_BO_VAL_DEFAULT 0x00000000
-
-/* MEMC_ARB_1 :: CLIENT_INFO_201 :: reserved1 [11:08] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_201_reserved1_MASK 0x00000f00
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_201_reserved1_SHIFT 8
-
-/* MEMC_ARB_1 :: CLIENT_INFO_201 :: PR_TAG [07:00] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_201_PR_TAG_MASK 0x000000ff
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_201_PR_TAG_SHIFT 0
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_201_PR_TAG_DEFAULT 0x00000000
-
-/***************************************************************************
- *CLIENT_INFO_202 - Client Programming register for client 202.
- ***************************************************************************/
-/* MEMC_ARB_1 :: CLIENT_INFO_202 :: RR_EN [31:31] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_202_RR_EN_MASK 0x80000000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_202_RR_EN_SHIFT 31
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_202_RR_EN_DEFAULT 0x00000001
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_202_RR_EN_DISABLED 0
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_202_RR_EN_ENABLED 1
-
-/* MEMC_ARB_1 :: CLIENT_INFO_202 :: reserved0 [30:30] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_202_reserved0_MASK 0x40000000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_202_reserved0_SHIFT 30
-
-/* MEMC_ARB_1 :: CLIENT_INFO_202 :: BO_VAL [29:12] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_202_BO_VAL_MASK 0x3ffff000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_202_BO_VAL_SHIFT 12
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_202_BO_VAL_DEFAULT 0x00000000
-
-/* MEMC_ARB_1 :: CLIENT_INFO_202 :: reserved1 [11:08] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_202_reserved1_MASK 0x00000f00
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_202_reserved1_SHIFT 8
-
-/* MEMC_ARB_1 :: CLIENT_INFO_202 :: PR_TAG [07:00] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_202_PR_TAG_MASK 0x000000ff
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_202_PR_TAG_SHIFT 0
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_202_PR_TAG_DEFAULT 0x00000000
-
-/***************************************************************************
- *CLIENT_INFO_203 - Client Programming register for client 203.
- ***************************************************************************/
-/* MEMC_ARB_1 :: CLIENT_INFO_203 :: RR_EN [31:31] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_203_RR_EN_MASK 0x80000000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_203_RR_EN_SHIFT 31
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_203_RR_EN_DEFAULT 0x00000001
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_203_RR_EN_DISABLED 0
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_203_RR_EN_ENABLED 1
-
-/* MEMC_ARB_1 :: CLIENT_INFO_203 :: reserved0 [30:30] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_203_reserved0_MASK 0x40000000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_203_reserved0_SHIFT 30
-
-/* MEMC_ARB_1 :: CLIENT_INFO_203 :: BO_VAL [29:12] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_203_BO_VAL_MASK 0x3ffff000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_203_BO_VAL_SHIFT 12
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_203_BO_VAL_DEFAULT 0x00000000
-
-/* MEMC_ARB_1 :: CLIENT_INFO_203 :: reserved1 [11:08] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_203_reserved1_MASK 0x00000f00
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_203_reserved1_SHIFT 8
-
-/* MEMC_ARB_1 :: CLIENT_INFO_203 :: PR_TAG [07:00] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_203_PR_TAG_MASK 0x000000ff
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_203_PR_TAG_SHIFT 0
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_203_PR_TAG_DEFAULT 0x00000000
-
-/***************************************************************************
- *CLIENT_INFO_204 - Client Programming register for client 204.
- ***************************************************************************/
-/* MEMC_ARB_1 :: CLIENT_INFO_204 :: RR_EN [31:31] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_204_RR_EN_MASK 0x80000000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_204_RR_EN_SHIFT 31
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_204_RR_EN_DEFAULT 0x00000001
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_204_RR_EN_DISABLED 0
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_204_RR_EN_ENABLED 1
-
-/* MEMC_ARB_1 :: CLIENT_INFO_204 :: reserved0 [30:30] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_204_reserved0_MASK 0x40000000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_204_reserved0_SHIFT 30
-
-/* MEMC_ARB_1 :: CLIENT_INFO_204 :: BO_VAL [29:12] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_204_BO_VAL_MASK 0x3ffff000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_204_BO_VAL_SHIFT 12
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_204_BO_VAL_DEFAULT 0x00000000
-
-/* MEMC_ARB_1 :: CLIENT_INFO_204 :: reserved1 [11:08] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_204_reserved1_MASK 0x00000f00
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_204_reserved1_SHIFT 8
-
-/* MEMC_ARB_1 :: CLIENT_INFO_204 :: PR_TAG [07:00] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_204_PR_TAG_MASK 0x000000ff
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_204_PR_TAG_SHIFT 0
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_204_PR_TAG_DEFAULT 0x00000000
-
-/***************************************************************************
- *CLIENT_INFO_205 - Client Programming register for client 205.
- ***************************************************************************/
-/* MEMC_ARB_1 :: CLIENT_INFO_205 :: RR_EN [31:31] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_205_RR_EN_MASK 0x80000000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_205_RR_EN_SHIFT 31
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_205_RR_EN_DEFAULT 0x00000001
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_205_RR_EN_DISABLED 0
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_205_RR_EN_ENABLED 1
-
-/* MEMC_ARB_1 :: CLIENT_INFO_205 :: reserved0 [30:30] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_205_reserved0_MASK 0x40000000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_205_reserved0_SHIFT 30
-
-/* MEMC_ARB_1 :: CLIENT_INFO_205 :: BO_VAL [29:12] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_205_BO_VAL_MASK 0x3ffff000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_205_BO_VAL_SHIFT 12
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_205_BO_VAL_DEFAULT 0x00000000
-
-/* MEMC_ARB_1 :: CLIENT_INFO_205 :: reserved1 [11:08] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_205_reserved1_MASK 0x00000f00
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_205_reserved1_SHIFT 8
-
-/* MEMC_ARB_1 :: CLIENT_INFO_205 :: PR_TAG [07:00] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_205_PR_TAG_MASK 0x000000ff
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_205_PR_TAG_SHIFT 0
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_205_PR_TAG_DEFAULT 0x00000000
-
-/***************************************************************************
- *CLIENT_INFO_206 - Client Programming register for client 206.
- ***************************************************************************/
-/* MEMC_ARB_1 :: CLIENT_INFO_206 :: RR_EN [31:31] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_206_RR_EN_MASK 0x80000000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_206_RR_EN_SHIFT 31
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_206_RR_EN_DEFAULT 0x00000001
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_206_RR_EN_DISABLED 0
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_206_RR_EN_ENABLED 1
-
-/* MEMC_ARB_1 :: CLIENT_INFO_206 :: reserved0 [30:30] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_206_reserved0_MASK 0x40000000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_206_reserved0_SHIFT 30
-
-/* MEMC_ARB_1 :: CLIENT_INFO_206 :: BO_VAL [29:12] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_206_BO_VAL_MASK 0x3ffff000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_206_BO_VAL_SHIFT 12
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_206_BO_VAL_DEFAULT 0x00000000
-
-/* MEMC_ARB_1 :: CLIENT_INFO_206 :: reserved1 [11:08] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_206_reserved1_MASK 0x00000f00
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_206_reserved1_SHIFT 8
-
-/* MEMC_ARB_1 :: CLIENT_INFO_206 :: PR_TAG [07:00] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_206_PR_TAG_MASK 0x000000ff
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_206_PR_TAG_SHIFT 0
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_206_PR_TAG_DEFAULT 0x00000000
-
-/***************************************************************************
- *CLIENT_INFO_207 - Client Programming register for client 207.
- ***************************************************************************/
-/* MEMC_ARB_1 :: CLIENT_INFO_207 :: RR_EN [31:31] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_207_RR_EN_MASK 0x80000000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_207_RR_EN_SHIFT 31
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_207_RR_EN_DEFAULT 0x00000001
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_207_RR_EN_DISABLED 0
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_207_RR_EN_ENABLED 1
-
-/* MEMC_ARB_1 :: CLIENT_INFO_207 :: reserved0 [30:30] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_207_reserved0_MASK 0x40000000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_207_reserved0_SHIFT 30
-
-/* MEMC_ARB_1 :: CLIENT_INFO_207 :: BO_VAL [29:12] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_207_BO_VAL_MASK 0x3ffff000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_207_BO_VAL_SHIFT 12
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_207_BO_VAL_DEFAULT 0x00000000
-
-/* MEMC_ARB_1 :: CLIENT_INFO_207 :: reserved1 [11:08] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_207_reserved1_MASK 0x00000f00
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_207_reserved1_SHIFT 8
-
-/* MEMC_ARB_1 :: CLIENT_INFO_207 :: PR_TAG [07:00] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_207_PR_TAG_MASK 0x000000ff
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_207_PR_TAG_SHIFT 0
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_207_PR_TAG_DEFAULT 0x00000000
-
-/***************************************************************************
- *CLIENT_INFO_208 - Client Programming register for client 208.
- ***************************************************************************/
-/* MEMC_ARB_1 :: CLIENT_INFO_208 :: RR_EN [31:31] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_208_RR_EN_MASK 0x80000000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_208_RR_EN_SHIFT 31
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_208_RR_EN_DEFAULT 0x00000001
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_208_RR_EN_DISABLED 0
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_208_RR_EN_ENABLED 1
-
-/* MEMC_ARB_1 :: CLIENT_INFO_208 :: reserved0 [30:30] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_208_reserved0_MASK 0x40000000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_208_reserved0_SHIFT 30
-
-/* MEMC_ARB_1 :: CLIENT_INFO_208 :: BO_VAL [29:12] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_208_BO_VAL_MASK 0x3ffff000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_208_BO_VAL_SHIFT 12
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_208_BO_VAL_DEFAULT 0x00000000
-
-/* MEMC_ARB_1 :: CLIENT_INFO_208 :: reserved1 [11:08] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_208_reserved1_MASK 0x00000f00
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_208_reserved1_SHIFT 8
-
-/* MEMC_ARB_1 :: CLIENT_INFO_208 :: PR_TAG [07:00] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_208_PR_TAG_MASK 0x000000ff
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_208_PR_TAG_SHIFT 0
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_208_PR_TAG_DEFAULT 0x00000000
-
-/***************************************************************************
- *CLIENT_INFO_209 - Client Programming register for client 209.
- ***************************************************************************/
-/* MEMC_ARB_1 :: CLIENT_INFO_209 :: RR_EN [31:31] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_209_RR_EN_MASK 0x80000000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_209_RR_EN_SHIFT 31
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_209_RR_EN_DEFAULT 0x00000001
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_209_RR_EN_DISABLED 0
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_209_RR_EN_ENABLED 1
-
-/* MEMC_ARB_1 :: CLIENT_INFO_209 :: reserved0 [30:30] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_209_reserved0_MASK 0x40000000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_209_reserved0_SHIFT 30
-
-/* MEMC_ARB_1 :: CLIENT_INFO_209 :: BO_VAL [29:12] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_209_BO_VAL_MASK 0x3ffff000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_209_BO_VAL_SHIFT 12
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_209_BO_VAL_DEFAULT 0x00000000
-
-/* MEMC_ARB_1 :: CLIENT_INFO_209 :: reserved1 [11:08] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_209_reserved1_MASK 0x00000f00
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_209_reserved1_SHIFT 8
-
-/* MEMC_ARB_1 :: CLIENT_INFO_209 :: PR_TAG [07:00] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_209_PR_TAG_MASK 0x000000ff
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_209_PR_TAG_SHIFT 0
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_209_PR_TAG_DEFAULT 0x00000000
-
-/***************************************************************************
- *CLIENT_INFO_210 - Client Programming register for client 210.
- ***************************************************************************/
-/* MEMC_ARB_1 :: CLIENT_INFO_210 :: RR_EN [31:31] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_210_RR_EN_MASK 0x80000000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_210_RR_EN_SHIFT 31
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_210_RR_EN_DEFAULT 0x00000001
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_210_RR_EN_DISABLED 0
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_210_RR_EN_ENABLED 1
-
-/* MEMC_ARB_1 :: CLIENT_INFO_210 :: reserved0 [30:30] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_210_reserved0_MASK 0x40000000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_210_reserved0_SHIFT 30
-
-/* MEMC_ARB_1 :: CLIENT_INFO_210 :: BO_VAL [29:12] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_210_BO_VAL_MASK 0x3ffff000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_210_BO_VAL_SHIFT 12
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_210_BO_VAL_DEFAULT 0x00000000
-
-/* MEMC_ARB_1 :: CLIENT_INFO_210 :: reserved1 [11:08] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_210_reserved1_MASK 0x00000f00
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_210_reserved1_SHIFT 8
-
-/* MEMC_ARB_1 :: CLIENT_INFO_210 :: PR_TAG [07:00] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_210_PR_TAG_MASK 0x000000ff
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_210_PR_TAG_SHIFT 0
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_210_PR_TAG_DEFAULT 0x00000000
-
-/***************************************************************************
- *CLIENT_INFO_211 - Client Programming register for client 211.
- ***************************************************************************/
-/* MEMC_ARB_1 :: CLIENT_INFO_211 :: RR_EN [31:31] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_211_RR_EN_MASK 0x80000000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_211_RR_EN_SHIFT 31
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_211_RR_EN_DEFAULT 0x00000001
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_211_RR_EN_DISABLED 0
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_211_RR_EN_ENABLED 1
-
-/* MEMC_ARB_1 :: CLIENT_INFO_211 :: reserved0 [30:30] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_211_reserved0_MASK 0x40000000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_211_reserved0_SHIFT 30
-
-/* MEMC_ARB_1 :: CLIENT_INFO_211 :: BO_VAL [29:12] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_211_BO_VAL_MASK 0x3ffff000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_211_BO_VAL_SHIFT 12
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_211_BO_VAL_DEFAULT 0x00000000
-
-/* MEMC_ARB_1 :: CLIENT_INFO_211 :: reserved1 [11:08] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_211_reserved1_MASK 0x00000f00
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_211_reserved1_SHIFT 8
-
-/* MEMC_ARB_1 :: CLIENT_INFO_211 :: PR_TAG [07:00] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_211_PR_TAG_MASK 0x000000ff
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_211_PR_TAG_SHIFT 0
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_211_PR_TAG_DEFAULT 0x00000000
-
-/***************************************************************************
- *CLIENT_INFO_212 - Client Programming register for client 212.
- ***************************************************************************/
-/* MEMC_ARB_1 :: CLIENT_INFO_212 :: RR_EN [31:31] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_212_RR_EN_MASK 0x80000000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_212_RR_EN_SHIFT 31
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_212_RR_EN_DEFAULT 0x00000001
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_212_RR_EN_DISABLED 0
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_212_RR_EN_ENABLED 1
-
-/* MEMC_ARB_1 :: CLIENT_INFO_212 :: reserved0 [30:30] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_212_reserved0_MASK 0x40000000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_212_reserved0_SHIFT 30
-
-/* MEMC_ARB_1 :: CLIENT_INFO_212 :: BO_VAL [29:12] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_212_BO_VAL_MASK 0x3ffff000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_212_BO_VAL_SHIFT 12
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_212_BO_VAL_DEFAULT 0x00000000
-
-/* MEMC_ARB_1 :: CLIENT_INFO_212 :: reserved1 [11:08] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_212_reserved1_MASK 0x00000f00
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_212_reserved1_SHIFT 8
-
-/* MEMC_ARB_1 :: CLIENT_INFO_212 :: PR_TAG [07:00] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_212_PR_TAG_MASK 0x000000ff
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_212_PR_TAG_SHIFT 0
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_212_PR_TAG_DEFAULT 0x00000000
-
-/***************************************************************************
- *CLIENT_INFO_213 - Client Programming register for client 213.
- ***************************************************************************/
-/* MEMC_ARB_1 :: CLIENT_INFO_213 :: RR_EN [31:31] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_213_RR_EN_MASK 0x80000000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_213_RR_EN_SHIFT 31
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_213_RR_EN_DEFAULT 0x00000001
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_213_RR_EN_DISABLED 0
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_213_RR_EN_ENABLED 1
-
-/* MEMC_ARB_1 :: CLIENT_INFO_213 :: reserved0 [30:30] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_213_reserved0_MASK 0x40000000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_213_reserved0_SHIFT 30
-
-/* MEMC_ARB_1 :: CLIENT_INFO_213 :: BO_VAL [29:12] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_213_BO_VAL_MASK 0x3ffff000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_213_BO_VAL_SHIFT 12
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_213_BO_VAL_DEFAULT 0x00000000
-
-/* MEMC_ARB_1 :: CLIENT_INFO_213 :: reserved1 [11:08] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_213_reserved1_MASK 0x00000f00
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_213_reserved1_SHIFT 8
-
-/* MEMC_ARB_1 :: CLIENT_INFO_213 :: PR_TAG [07:00] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_213_PR_TAG_MASK 0x000000ff
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_213_PR_TAG_SHIFT 0
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_213_PR_TAG_DEFAULT 0x00000000
-
-/***************************************************************************
- *CLIENT_INFO_214 - Client Programming register for client 214.
- ***************************************************************************/
-/* MEMC_ARB_1 :: CLIENT_INFO_214 :: RR_EN [31:31] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_214_RR_EN_MASK 0x80000000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_214_RR_EN_SHIFT 31
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_214_RR_EN_DEFAULT 0x00000001
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_214_RR_EN_DISABLED 0
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_214_RR_EN_ENABLED 1
-
-/* MEMC_ARB_1 :: CLIENT_INFO_214 :: reserved0 [30:30] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_214_reserved0_MASK 0x40000000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_214_reserved0_SHIFT 30
-
-/* MEMC_ARB_1 :: CLIENT_INFO_214 :: BO_VAL [29:12] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_214_BO_VAL_MASK 0x3ffff000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_214_BO_VAL_SHIFT 12
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_214_BO_VAL_DEFAULT 0x00000000
-
-/* MEMC_ARB_1 :: CLIENT_INFO_214 :: reserved1 [11:08] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_214_reserved1_MASK 0x00000f00
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_214_reserved1_SHIFT 8
-
-/* MEMC_ARB_1 :: CLIENT_INFO_214 :: PR_TAG [07:00] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_214_PR_TAG_MASK 0x000000ff
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_214_PR_TAG_SHIFT 0
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_214_PR_TAG_DEFAULT 0x00000000
-
-/***************************************************************************
- *CLIENT_INFO_215 - Client Programming register for client 215.
- ***************************************************************************/
-/* MEMC_ARB_1 :: CLIENT_INFO_215 :: RR_EN [31:31] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_215_RR_EN_MASK 0x80000000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_215_RR_EN_SHIFT 31
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_215_RR_EN_DEFAULT 0x00000001
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_215_RR_EN_DISABLED 0
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_215_RR_EN_ENABLED 1
-
-/* MEMC_ARB_1 :: CLIENT_INFO_215 :: reserved0 [30:30] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_215_reserved0_MASK 0x40000000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_215_reserved0_SHIFT 30
-
-/* MEMC_ARB_1 :: CLIENT_INFO_215 :: BO_VAL [29:12] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_215_BO_VAL_MASK 0x3ffff000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_215_BO_VAL_SHIFT 12
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_215_BO_VAL_DEFAULT 0x00000000
-
-/* MEMC_ARB_1 :: CLIENT_INFO_215 :: reserved1 [11:08] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_215_reserved1_MASK 0x00000f00
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_215_reserved1_SHIFT 8
-
-/* MEMC_ARB_1 :: CLIENT_INFO_215 :: PR_TAG [07:00] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_215_PR_TAG_MASK 0x000000ff
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_215_PR_TAG_SHIFT 0
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_215_PR_TAG_DEFAULT 0x00000000
-
-/***************************************************************************
- *CLIENT_INFO_216 - Client Programming register for client 216.
- ***************************************************************************/
-/* MEMC_ARB_1 :: CLIENT_INFO_216 :: RR_EN [31:31] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_216_RR_EN_MASK 0x80000000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_216_RR_EN_SHIFT 31
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_216_RR_EN_DEFAULT 0x00000001
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_216_RR_EN_DISABLED 0
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_216_RR_EN_ENABLED 1
-
-/* MEMC_ARB_1 :: CLIENT_INFO_216 :: reserved0 [30:30] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_216_reserved0_MASK 0x40000000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_216_reserved0_SHIFT 30
-
-/* MEMC_ARB_1 :: CLIENT_INFO_216 :: BO_VAL [29:12] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_216_BO_VAL_MASK 0x3ffff000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_216_BO_VAL_SHIFT 12
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_216_BO_VAL_DEFAULT 0x00000000
-
-/* MEMC_ARB_1 :: CLIENT_INFO_216 :: reserved1 [11:08] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_216_reserved1_MASK 0x00000f00
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_216_reserved1_SHIFT 8
-
-/* MEMC_ARB_1 :: CLIENT_INFO_216 :: PR_TAG [07:00] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_216_PR_TAG_MASK 0x000000ff
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_216_PR_TAG_SHIFT 0
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_216_PR_TAG_DEFAULT 0x00000000
-
-/***************************************************************************
- *CLIENT_INFO_217 - Client Programming register for client 217.
- ***************************************************************************/
-/* MEMC_ARB_1 :: CLIENT_INFO_217 :: RR_EN [31:31] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_217_RR_EN_MASK 0x80000000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_217_RR_EN_SHIFT 31
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_217_RR_EN_DEFAULT 0x00000001
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_217_RR_EN_DISABLED 0
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_217_RR_EN_ENABLED 1
-
-/* MEMC_ARB_1 :: CLIENT_INFO_217 :: reserved0 [30:30] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_217_reserved0_MASK 0x40000000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_217_reserved0_SHIFT 30
-
-/* MEMC_ARB_1 :: CLIENT_INFO_217 :: BO_VAL [29:12] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_217_BO_VAL_MASK 0x3ffff000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_217_BO_VAL_SHIFT 12
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_217_BO_VAL_DEFAULT 0x00000000
-
-/* MEMC_ARB_1 :: CLIENT_INFO_217 :: reserved1 [11:08] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_217_reserved1_MASK 0x00000f00
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_217_reserved1_SHIFT 8
-
-/* MEMC_ARB_1 :: CLIENT_INFO_217 :: PR_TAG [07:00] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_217_PR_TAG_MASK 0x000000ff
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_217_PR_TAG_SHIFT 0
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_217_PR_TAG_DEFAULT 0x00000000
-
-/***************************************************************************
- *CLIENT_INFO_218 - Client Programming register for client 218.
- ***************************************************************************/
-/* MEMC_ARB_1 :: CLIENT_INFO_218 :: RR_EN [31:31] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_218_RR_EN_MASK 0x80000000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_218_RR_EN_SHIFT 31
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_218_RR_EN_DEFAULT 0x00000001
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_218_RR_EN_DISABLED 0
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_218_RR_EN_ENABLED 1
-
-/* MEMC_ARB_1 :: CLIENT_INFO_218 :: reserved0 [30:30] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_218_reserved0_MASK 0x40000000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_218_reserved0_SHIFT 30
-
-/* MEMC_ARB_1 :: CLIENT_INFO_218 :: BO_VAL [29:12] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_218_BO_VAL_MASK 0x3ffff000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_218_BO_VAL_SHIFT 12
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_218_BO_VAL_DEFAULT 0x00000000
-
-/* MEMC_ARB_1 :: CLIENT_INFO_218 :: reserved1 [11:08] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_218_reserved1_MASK 0x00000f00
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_218_reserved1_SHIFT 8
-
-/* MEMC_ARB_1 :: CLIENT_INFO_218 :: PR_TAG [07:00] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_218_PR_TAG_MASK 0x000000ff
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_218_PR_TAG_SHIFT 0
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_218_PR_TAG_DEFAULT 0x00000000
-
-/***************************************************************************
- *CLIENT_INFO_219 - Client Programming register for client 219.
- ***************************************************************************/
-/* MEMC_ARB_1 :: CLIENT_INFO_219 :: RR_EN [31:31] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_219_RR_EN_MASK 0x80000000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_219_RR_EN_SHIFT 31
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_219_RR_EN_DEFAULT 0x00000001
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_219_RR_EN_DISABLED 0
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_219_RR_EN_ENABLED 1
-
-/* MEMC_ARB_1 :: CLIENT_INFO_219 :: reserved0 [30:30] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_219_reserved0_MASK 0x40000000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_219_reserved0_SHIFT 30
-
-/* MEMC_ARB_1 :: CLIENT_INFO_219 :: BO_VAL [29:12] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_219_BO_VAL_MASK 0x3ffff000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_219_BO_VAL_SHIFT 12
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_219_BO_VAL_DEFAULT 0x00000000
-
-/* MEMC_ARB_1 :: CLIENT_INFO_219 :: reserved1 [11:08] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_219_reserved1_MASK 0x00000f00
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_219_reserved1_SHIFT 8
-
-/* MEMC_ARB_1 :: CLIENT_INFO_219 :: PR_TAG [07:00] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_219_PR_TAG_MASK 0x000000ff
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_219_PR_TAG_SHIFT 0
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_219_PR_TAG_DEFAULT 0x00000000
-
-/***************************************************************************
- *CLIENT_INFO_220 - Client Programming register for client 220.
- ***************************************************************************/
-/* MEMC_ARB_1 :: CLIENT_INFO_220 :: RR_EN [31:31] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_220_RR_EN_MASK 0x80000000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_220_RR_EN_SHIFT 31
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_220_RR_EN_DEFAULT 0x00000001
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_220_RR_EN_DISABLED 0
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_220_RR_EN_ENABLED 1
-
-/* MEMC_ARB_1 :: CLIENT_INFO_220 :: reserved0 [30:30] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_220_reserved0_MASK 0x40000000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_220_reserved0_SHIFT 30
-
-/* MEMC_ARB_1 :: CLIENT_INFO_220 :: BO_VAL [29:12] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_220_BO_VAL_MASK 0x3ffff000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_220_BO_VAL_SHIFT 12
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_220_BO_VAL_DEFAULT 0x00000000
-
-/* MEMC_ARB_1 :: CLIENT_INFO_220 :: reserved1 [11:08] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_220_reserved1_MASK 0x00000f00
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_220_reserved1_SHIFT 8
-
-/* MEMC_ARB_1 :: CLIENT_INFO_220 :: PR_TAG [07:00] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_220_PR_TAG_MASK 0x000000ff
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_220_PR_TAG_SHIFT 0
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_220_PR_TAG_DEFAULT 0x00000000
-
-/***************************************************************************
- *CLIENT_INFO_221 - Client Programming register for client 221.
- ***************************************************************************/
-/* MEMC_ARB_1 :: CLIENT_INFO_221 :: RR_EN [31:31] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_221_RR_EN_MASK 0x80000000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_221_RR_EN_SHIFT 31
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_221_RR_EN_DEFAULT 0x00000001
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_221_RR_EN_DISABLED 0
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_221_RR_EN_ENABLED 1
-
-/* MEMC_ARB_1 :: CLIENT_INFO_221 :: reserved0 [30:30] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_221_reserved0_MASK 0x40000000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_221_reserved0_SHIFT 30
-
-/* MEMC_ARB_1 :: CLIENT_INFO_221 :: BO_VAL [29:12] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_221_BO_VAL_MASK 0x3ffff000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_221_BO_VAL_SHIFT 12
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_221_BO_VAL_DEFAULT 0x00000000
-
-/* MEMC_ARB_1 :: CLIENT_INFO_221 :: reserved1 [11:08] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_221_reserved1_MASK 0x00000f00
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_221_reserved1_SHIFT 8
-
-/* MEMC_ARB_1 :: CLIENT_INFO_221 :: PR_TAG [07:00] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_221_PR_TAG_MASK 0x000000ff
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_221_PR_TAG_SHIFT 0
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_221_PR_TAG_DEFAULT 0x00000000
-
-/***************************************************************************
- *CLIENT_INFO_222 - Client Programming register for client 222.
- ***************************************************************************/
-/* MEMC_ARB_1 :: CLIENT_INFO_222 :: RR_EN [31:31] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_222_RR_EN_MASK 0x80000000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_222_RR_EN_SHIFT 31
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_222_RR_EN_DEFAULT 0x00000001
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_222_RR_EN_DISABLED 0
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_222_RR_EN_ENABLED 1
-
-/* MEMC_ARB_1 :: CLIENT_INFO_222 :: reserved0 [30:30] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_222_reserved0_MASK 0x40000000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_222_reserved0_SHIFT 30
-
-/* MEMC_ARB_1 :: CLIENT_INFO_222 :: BO_VAL [29:12] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_222_BO_VAL_MASK 0x3ffff000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_222_BO_VAL_SHIFT 12
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_222_BO_VAL_DEFAULT 0x00000000
-
-/* MEMC_ARB_1 :: CLIENT_INFO_222 :: reserved1 [11:08] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_222_reserved1_MASK 0x00000f00
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_222_reserved1_SHIFT 8
-
-/* MEMC_ARB_1 :: CLIENT_INFO_222 :: PR_TAG [07:00] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_222_PR_TAG_MASK 0x000000ff
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_222_PR_TAG_SHIFT 0
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_222_PR_TAG_DEFAULT 0x00000000
-
-/***************************************************************************
- *CLIENT_INFO_223 - Client Programming register for client 223.
- ***************************************************************************/
-/* MEMC_ARB_1 :: CLIENT_INFO_223 :: RR_EN [31:31] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_223_RR_EN_MASK 0x80000000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_223_RR_EN_SHIFT 31
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_223_RR_EN_DEFAULT 0x00000001
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_223_RR_EN_DISABLED 0
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_223_RR_EN_ENABLED 1
-
-/* MEMC_ARB_1 :: CLIENT_INFO_223 :: reserved0 [30:30] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_223_reserved0_MASK 0x40000000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_223_reserved0_SHIFT 30
-
-/* MEMC_ARB_1 :: CLIENT_INFO_223 :: BO_VAL [29:12] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_223_BO_VAL_MASK 0x3ffff000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_223_BO_VAL_SHIFT 12
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_223_BO_VAL_DEFAULT 0x00000000
-
-/* MEMC_ARB_1 :: CLIENT_INFO_223 :: reserved1 [11:08] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_223_reserved1_MASK 0x00000f00
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_223_reserved1_SHIFT 8
-
-/* MEMC_ARB_1 :: CLIENT_INFO_223 :: PR_TAG [07:00] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_223_PR_TAG_MASK 0x000000ff
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_223_PR_TAG_SHIFT 0
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_223_PR_TAG_DEFAULT 0x00000000
-
-/***************************************************************************
- *CLIENT_INFO_224 - Client Programming register for client 224.
- ***************************************************************************/
-/* MEMC_ARB_1 :: CLIENT_INFO_224 :: RR_EN [31:31] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_224_RR_EN_MASK 0x80000000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_224_RR_EN_SHIFT 31
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_224_RR_EN_DEFAULT 0x00000001
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_224_RR_EN_DISABLED 0
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_224_RR_EN_ENABLED 1
-
-/* MEMC_ARB_1 :: CLIENT_INFO_224 :: reserved0 [30:30] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_224_reserved0_MASK 0x40000000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_224_reserved0_SHIFT 30
-
-/* MEMC_ARB_1 :: CLIENT_INFO_224 :: BO_VAL [29:12] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_224_BO_VAL_MASK 0x3ffff000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_224_BO_VAL_SHIFT 12
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_224_BO_VAL_DEFAULT 0x00000000
-
-/* MEMC_ARB_1 :: CLIENT_INFO_224 :: reserved1 [11:08] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_224_reserved1_MASK 0x00000f00
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_224_reserved1_SHIFT 8
-
-/* MEMC_ARB_1 :: CLIENT_INFO_224 :: PR_TAG [07:00] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_224_PR_TAG_MASK 0x000000ff
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_224_PR_TAG_SHIFT 0
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_224_PR_TAG_DEFAULT 0x00000000
-
-/***************************************************************************
- *CLIENT_INFO_225 - Client Programming register for client 225.
- ***************************************************************************/
-/* MEMC_ARB_1 :: CLIENT_INFO_225 :: RR_EN [31:31] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_225_RR_EN_MASK 0x80000000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_225_RR_EN_SHIFT 31
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_225_RR_EN_DEFAULT 0x00000001
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_225_RR_EN_DISABLED 0
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_225_RR_EN_ENABLED 1
-
-/* MEMC_ARB_1 :: CLIENT_INFO_225 :: reserved0 [30:30] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_225_reserved0_MASK 0x40000000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_225_reserved0_SHIFT 30
-
-/* MEMC_ARB_1 :: CLIENT_INFO_225 :: BO_VAL [29:12] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_225_BO_VAL_MASK 0x3ffff000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_225_BO_VAL_SHIFT 12
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_225_BO_VAL_DEFAULT 0x00000000
-
-/* MEMC_ARB_1 :: CLIENT_INFO_225 :: reserved1 [11:08] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_225_reserved1_MASK 0x00000f00
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_225_reserved1_SHIFT 8
-
-/* MEMC_ARB_1 :: CLIENT_INFO_225 :: PR_TAG [07:00] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_225_PR_TAG_MASK 0x000000ff
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_225_PR_TAG_SHIFT 0
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_225_PR_TAG_DEFAULT 0x00000000
-
-/***************************************************************************
- *CLIENT_INFO_226 - Client Programming register for client 226.
- ***************************************************************************/
-/* MEMC_ARB_1 :: CLIENT_INFO_226 :: RR_EN [31:31] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_226_RR_EN_MASK 0x80000000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_226_RR_EN_SHIFT 31
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_226_RR_EN_DEFAULT 0x00000001
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_226_RR_EN_DISABLED 0
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_226_RR_EN_ENABLED 1
-
-/* MEMC_ARB_1 :: CLIENT_INFO_226 :: reserved0 [30:30] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_226_reserved0_MASK 0x40000000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_226_reserved0_SHIFT 30
-
-/* MEMC_ARB_1 :: CLIENT_INFO_226 :: BO_VAL [29:12] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_226_BO_VAL_MASK 0x3ffff000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_226_BO_VAL_SHIFT 12
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_226_BO_VAL_DEFAULT 0x00000000
-
-/* MEMC_ARB_1 :: CLIENT_INFO_226 :: reserved1 [11:08] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_226_reserved1_MASK 0x00000f00
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_226_reserved1_SHIFT 8
-
-/* MEMC_ARB_1 :: CLIENT_INFO_226 :: PR_TAG [07:00] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_226_PR_TAG_MASK 0x000000ff
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_226_PR_TAG_SHIFT 0
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_226_PR_TAG_DEFAULT 0x00000000
-
-/***************************************************************************
- *CLIENT_INFO_227 - Client Programming register for client 227.
- ***************************************************************************/
-/* MEMC_ARB_1 :: CLIENT_INFO_227 :: RR_EN [31:31] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_227_RR_EN_MASK 0x80000000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_227_RR_EN_SHIFT 31
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_227_RR_EN_DEFAULT 0x00000001
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_227_RR_EN_DISABLED 0
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_227_RR_EN_ENABLED 1
-
-/* MEMC_ARB_1 :: CLIENT_INFO_227 :: reserved0 [30:30] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_227_reserved0_MASK 0x40000000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_227_reserved0_SHIFT 30
-
-/* MEMC_ARB_1 :: CLIENT_INFO_227 :: BO_VAL [29:12] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_227_BO_VAL_MASK 0x3ffff000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_227_BO_VAL_SHIFT 12
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_227_BO_VAL_DEFAULT 0x00000000
-
-/* MEMC_ARB_1 :: CLIENT_INFO_227 :: reserved1 [11:08] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_227_reserved1_MASK 0x00000f00
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_227_reserved1_SHIFT 8
-
-/* MEMC_ARB_1 :: CLIENT_INFO_227 :: PR_TAG [07:00] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_227_PR_TAG_MASK 0x000000ff
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_227_PR_TAG_SHIFT 0
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_227_PR_TAG_DEFAULT 0x00000000
-
-/***************************************************************************
- *CLIENT_INFO_228 - Client Programming register for client 228.
- ***************************************************************************/
-/* MEMC_ARB_1 :: CLIENT_INFO_228 :: RR_EN [31:31] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_228_RR_EN_MASK 0x80000000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_228_RR_EN_SHIFT 31
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_228_RR_EN_DEFAULT 0x00000001
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_228_RR_EN_DISABLED 0
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_228_RR_EN_ENABLED 1
-
-/* MEMC_ARB_1 :: CLIENT_INFO_228 :: reserved0 [30:30] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_228_reserved0_MASK 0x40000000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_228_reserved0_SHIFT 30
-
-/* MEMC_ARB_1 :: CLIENT_INFO_228 :: BO_VAL [29:12] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_228_BO_VAL_MASK 0x3ffff000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_228_BO_VAL_SHIFT 12
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_228_BO_VAL_DEFAULT 0x00000000
-
-/* MEMC_ARB_1 :: CLIENT_INFO_228 :: reserved1 [11:08] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_228_reserved1_MASK 0x00000f00
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_228_reserved1_SHIFT 8
-
-/* MEMC_ARB_1 :: CLIENT_INFO_228 :: PR_TAG [07:00] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_228_PR_TAG_MASK 0x000000ff
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_228_PR_TAG_SHIFT 0
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_228_PR_TAG_DEFAULT 0x00000000
-
-/***************************************************************************
- *CLIENT_INFO_229 - Client Programming register for client 229.
- ***************************************************************************/
-/* MEMC_ARB_1 :: CLIENT_INFO_229 :: RR_EN [31:31] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_229_RR_EN_MASK 0x80000000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_229_RR_EN_SHIFT 31
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_229_RR_EN_DEFAULT 0x00000001
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_229_RR_EN_DISABLED 0
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_229_RR_EN_ENABLED 1
-
-/* MEMC_ARB_1 :: CLIENT_INFO_229 :: reserved0 [30:30] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_229_reserved0_MASK 0x40000000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_229_reserved0_SHIFT 30
-
-/* MEMC_ARB_1 :: CLIENT_INFO_229 :: BO_VAL [29:12] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_229_BO_VAL_MASK 0x3ffff000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_229_BO_VAL_SHIFT 12
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_229_BO_VAL_DEFAULT 0x00000000
-
-/* MEMC_ARB_1 :: CLIENT_INFO_229 :: reserved1 [11:08] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_229_reserved1_MASK 0x00000f00
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_229_reserved1_SHIFT 8
-
-/* MEMC_ARB_1 :: CLIENT_INFO_229 :: PR_TAG [07:00] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_229_PR_TAG_MASK 0x000000ff
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_229_PR_TAG_SHIFT 0
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_229_PR_TAG_DEFAULT 0x00000000
-
-/***************************************************************************
- *CLIENT_INFO_230 - Client Programming register for client 230.
- ***************************************************************************/
-/* MEMC_ARB_1 :: CLIENT_INFO_230 :: RR_EN [31:31] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_230_RR_EN_MASK 0x80000000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_230_RR_EN_SHIFT 31
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_230_RR_EN_DEFAULT 0x00000001
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_230_RR_EN_DISABLED 0
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_230_RR_EN_ENABLED 1
-
-/* MEMC_ARB_1 :: CLIENT_INFO_230 :: reserved0 [30:30] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_230_reserved0_MASK 0x40000000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_230_reserved0_SHIFT 30
-
-/* MEMC_ARB_1 :: CLIENT_INFO_230 :: BO_VAL [29:12] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_230_BO_VAL_MASK 0x3ffff000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_230_BO_VAL_SHIFT 12
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_230_BO_VAL_DEFAULT 0x00000000
-
-/* MEMC_ARB_1 :: CLIENT_INFO_230 :: reserved1 [11:08] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_230_reserved1_MASK 0x00000f00
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_230_reserved1_SHIFT 8
-
-/* MEMC_ARB_1 :: CLIENT_INFO_230 :: PR_TAG [07:00] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_230_PR_TAG_MASK 0x000000ff
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_230_PR_TAG_SHIFT 0
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_230_PR_TAG_DEFAULT 0x00000000
-
-/***************************************************************************
- *CLIENT_INFO_231 - Client Programming register for client 231.
- ***************************************************************************/
-/* MEMC_ARB_1 :: CLIENT_INFO_231 :: RR_EN [31:31] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_231_RR_EN_MASK 0x80000000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_231_RR_EN_SHIFT 31
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_231_RR_EN_DEFAULT 0x00000001
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_231_RR_EN_DISABLED 0
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_231_RR_EN_ENABLED 1
-
-/* MEMC_ARB_1 :: CLIENT_INFO_231 :: reserved0 [30:30] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_231_reserved0_MASK 0x40000000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_231_reserved0_SHIFT 30
-
-/* MEMC_ARB_1 :: CLIENT_INFO_231 :: BO_VAL [29:12] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_231_BO_VAL_MASK 0x3ffff000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_231_BO_VAL_SHIFT 12
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_231_BO_VAL_DEFAULT 0x00000000
-
-/* MEMC_ARB_1 :: CLIENT_INFO_231 :: reserved1 [11:08] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_231_reserved1_MASK 0x00000f00
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_231_reserved1_SHIFT 8
-
-/* MEMC_ARB_1 :: CLIENT_INFO_231 :: PR_TAG [07:00] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_231_PR_TAG_MASK 0x000000ff
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_231_PR_TAG_SHIFT 0
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_231_PR_TAG_DEFAULT 0x00000000
-
-/***************************************************************************
- *CLIENT_INFO_232 - Client Programming register for client 232.
- ***************************************************************************/
-/* MEMC_ARB_1 :: CLIENT_INFO_232 :: RR_EN [31:31] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_232_RR_EN_MASK 0x80000000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_232_RR_EN_SHIFT 31
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_232_RR_EN_DEFAULT 0x00000001
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_232_RR_EN_DISABLED 0
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_232_RR_EN_ENABLED 1
-
-/* MEMC_ARB_1 :: CLIENT_INFO_232 :: reserved0 [30:30] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_232_reserved0_MASK 0x40000000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_232_reserved0_SHIFT 30
-
-/* MEMC_ARB_1 :: CLIENT_INFO_232 :: BO_VAL [29:12] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_232_BO_VAL_MASK 0x3ffff000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_232_BO_VAL_SHIFT 12
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_232_BO_VAL_DEFAULT 0x00000000
-
-/* MEMC_ARB_1 :: CLIENT_INFO_232 :: reserved1 [11:08] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_232_reserved1_MASK 0x00000f00
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_232_reserved1_SHIFT 8
-
-/* MEMC_ARB_1 :: CLIENT_INFO_232 :: PR_TAG [07:00] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_232_PR_TAG_MASK 0x000000ff
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_232_PR_TAG_SHIFT 0
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_232_PR_TAG_DEFAULT 0x00000000
-
-/***************************************************************************
- *CLIENT_INFO_233 - Client Programming register for client 233.
- ***************************************************************************/
-/* MEMC_ARB_1 :: CLIENT_INFO_233 :: RR_EN [31:31] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_233_RR_EN_MASK 0x80000000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_233_RR_EN_SHIFT 31
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_233_RR_EN_DEFAULT 0x00000001
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_233_RR_EN_DISABLED 0
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_233_RR_EN_ENABLED 1
-
-/* MEMC_ARB_1 :: CLIENT_INFO_233 :: reserved0 [30:30] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_233_reserved0_MASK 0x40000000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_233_reserved0_SHIFT 30
-
-/* MEMC_ARB_1 :: CLIENT_INFO_233 :: BO_VAL [29:12] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_233_BO_VAL_MASK 0x3ffff000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_233_BO_VAL_SHIFT 12
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_233_BO_VAL_DEFAULT 0x00000000
-
-/* MEMC_ARB_1 :: CLIENT_INFO_233 :: reserved1 [11:08] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_233_reserved1_MASK 0x00000f00
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_233_reserved1_SHIFT 8
-
-/* MEMC_ARB_1 :: CLIENT_INFO_233 :: PR_TAG [07:00] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_233_PR_TAG_MASK 0x000000ff
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_233_PR_TAG_SHIFT 0
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_233_PR_TAG_DEFAULT 0x00000000
-
-/***************************************************************************
- *CLIENT_INFO_234 - Client Programming register for client 234.
- ***************************************************************************/
-/* MEMC_ARB_1 :: CLIENT_INFO_234 :: RR_EN [31:31] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_234_RR_EN_MASK 0x80000000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_234_RR_EN_SHIFT 31
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_234_RR_EN_DEFAULT 0x00000001
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_234_RR_EN_DISABLED 0
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_234_RR_EN_ENABLED 1
-
-/* MEMC_ARB_1 :: CLIENT_INFO_234 :: reserved0 [30:30] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_234_reserved0_MASK 0x40000000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_234_reserved0_SHIFT 30
-
-/* MEMC_ARB_1 :: CLIENT_INFO_234 :: BO_VAL [29:12] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_234_BO_VAL_MASK 0x3ffff000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_234_BO_VAL_SHIFT 12
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_234_BO_VAL_DEFAULT 0x00000000
-
-/* MEMC_ARB_1 :: CLIENT_INFO_234 :: reserved1 [11:08] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_234_reserved1_MASK 0x00000f00
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_234_reserved1_SHIFT 8
-
-/* MEMC_ARB_1 :: CLIENT_INFO_234 :: PR_TAG [07:00] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_234_PR_TAG_MASK 0x000000ff
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_234_PR_TAG_SHIFT 0
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_234_PR_TAG_DEFAULT 0x00000000
-
-/***************************************************************************
- *CLIENT_INFO_235 - Client Programming register for client 235.
- ***************************************************************************/
-/* MEMC_ARB_1 :: CLIENT_INFO_235 :: RR_EN [31:31] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_235_RR_EN_MASK 0x80000000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_235_RR_EN_SHIFT 31
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_235_RR_EN_DEFAULT 0x00000001
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_235_RR_EN_DISABLED 0
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_235_RR_EN_ENABLED 1
-
-/* MEMC_ARB_1 :: CLIENT_INFO_235 :: reserved0 [30:30] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_235_reserved0_MASK 0x40000000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_235_reserved0_SHIFT 30
-
-/* MEMC_ARB_1 :: CLIENT_INFO_235 :: BO_VAL [29:12] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_235_BO_VAL_MASK 0x3ffff000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_235_BO_VAL_SHIFT 12
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_235_BO_VAL_DEFAULT 0x00000000
-
-/* MEMC_ARB_1 :: CLIENT_INFO_235 :: reserved1 [11:08] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_235_reserved1_MASK 0x00000f00
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_235_reserved1_SHIFT 8
-
-/* MEMC_ARB_1 :: CLIENT_INFO_235 :: PR_TAG [07:00] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_235_PR_TAG_MASK 0x000000ff
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_235_PR_TAG_SHIFT 0
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_235_PR_TAG_DEFAULT 0x00000000
-
-/***************************************************************************
- *CLIENT_INFO_236 - Client Programming register for client 236.
- ***************************************************************************/
-/* MEMC_ARB_1 :: CLIENT_INFO_236 :: RR_EN [31:31] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_236_RR_EN_MASK 0x80000000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_236_RR_EN_SHIFT 31
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_236_RR_EN_DEFAULT 0x00000001
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_236_RR_EN_DISABLED 0
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_236_RR_EN_ENABLED 1
-
-/* MEMC_ARB_1 :: CLIENT_INFO_236 :: reserved0 [30:30] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_236_reserved0_MASK 0x40000000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_236_reserved0_SHIFT 30
-
-/* MEMC_ARB_1 :: CLIENT_INFO_236 :: BO_VAL [29:12] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_236_BO_VAL_MASK 0x3ffff000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_236_BO_VAL_SHIFT 12
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_236_BO_VAL_DEFAULT 0x00000000
-
-/* MEMC_ARB_1 :: CLIENT_INFO_236 :: reserved1 [11:08] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_236_reserved1_MASK 0x00000f00
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_236_reserved1_SHIFT 8
-
-/* MEMC_ARB_1 :: CLIENT_INFO_236 :: PR_TAG [07:00] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_236_PR_TAG_MASK 0x000000ff
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_236_PR_TAG_SHIFT 0
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_236_PR_TAG_DEFAULT 0x00000000
-
-/***************************************************************************
- *CLIENT_INFO_237 - Client Programming register for client 237.
- ***************************************************************************/
-/* MEMC_ARB_1 :: CLIENT_INFO_237 :: RR_EN [31:31] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_237_RR_EN_MASK 0x80000000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_237_RR_EN_SHIFT 31
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_237_RR_EN_DEFAULT 0x00000001
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_237_RR_EN_DISABLED 0
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_237_RR_EN_ENABLED 1
-
-/* MEMC_ARB_1 :: CLIENT_INFO_237 :: reserved0 [30:30] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_237_reserved0_MASK 0x40000000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_237_reserved0_SHIFT 30
-
-/* MEMC_ARB_1 :: CLIENT_INFO_237 :: BO_VAL [29:12] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_237_BO_VAL_MASK 0x3ffff000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_237_BO_VAL_SHIFT 12
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_237_BO_VAL_DEFAULT 0x00000000
-
-/* MEMC_ARB_1 :: CLIENT_INFO_237 :: reserved1 [11:08] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_237_reserved1_MASK 0x00000f00
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_237_reserved1_SHIFT 8
-
-/* MEMC_ARB_1 :: CLIENT_INFO_237 :: PR_TAG [07:00] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_237_PR_TAG_MASK 0x000000ff
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_237_PR_TAG_SHIFT 0
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_237_PR_TAG_DEFAULT 0x00000000
-
-/***************************************************************************
- *CLIENT_INFO_238 - Client Programming register for client 238.
- ***************************************************************************/
-/* MEMC_ARB_1 :: CLIENT_INFO_238 :: RR_EN [31:31] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_238_RR_EN_MASK 0x80000000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_238_RR_EN_SHIFT 31
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_238_RR_EN_DEFAULT 0x00000001
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_238_RR_EN_DISABLED 0
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_238_RR_EN_ENABLED 1
-
-/* MEMC_ARB_1 :: CLIENT_INFO_238 :: reserved0 [30:30] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_238_reserved0_MASK 0x40000000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_238_reserved0_SHIFT 30
-
-/* MEMC_ARB_1 :: CLIENT_INFO_238 :: BO_VAL [29:12] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_238_BO_VAL_MASK 0x3ffff000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_238_BO_VAL_SHIFT 12
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_238_BO_VAL_DEFAULT 0x00000000
-
-/* MEMC_ARB_1 :: CLIENT_INFO_238 :: reserved1 [11:08] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_238_reserved1_MASK 0x00000f00
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_238_reserved1_SHIFT 8
-
-/* MEMC_ARB_1 :: CLIENT_INFO_238 :: PR_TAG [07:00] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_238_PR_TAG_MASK 0x000000ff
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_238_PR_TAG_SHIFT 0
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_238_PR_TAG_DEFAULT 0x00000000
-
-/***************************************************************************
- *CLIENT_INFO_239 - Client Programming register for client 239.
- ***************************************************************************/
-/* MEMC_ARB_1 :: CLIENT_INFO_239 :: RR_EN [31:31] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_239_RR_EN_MASK 0x80000000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_239_RR_EN_SHIFT 31
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_239_RR_EN_DEFAULT 0x00000001
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_239_RR_EN_DISABLED 0
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_239_RR_EN_ENABLED 1
-
-/* MEMC_ARB_1 :: CLIENT_INFO_239 :: reserved0 [30:30] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_239_reserved0_MASK 0x40000000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_239_reserved0_SHIFT 30
-
-/* MEMC_ARB_1 :: CLIENT_INFO_239 :: BO_VAL [29:12] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_239_BO_VAL_MASK 0x3ffff000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_239_BO_VAL_SHIFT 12
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_239_BO_VAL_DEFAULT 0x00000000
-
-/* MEMC_ARB_1 :: CLIENT_INFO_239 :: reserved1 [11:08] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_239_reserved1_MASK 0x00000f00
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_239_reserved1_SHIFT 8
-
-/* MEMC_ARB_1 :: CLIENT_INFO_239 :: PR_TAG [07:00] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_239_PR_TAG_MASK 0x000000ff
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_239_PR_TAG_SHIFT 0
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_239_PR_TAG_DEFAULT 0x00000000
-
-/***************************************************************************
- *CLIENT_INFO_240 - Client Programming register for client 240.
- ***************************************************************************/
-/* MEMC_ARB_1 :: CLIENT_INFO_240 :: RR_EN [31:31] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_240_RR_EN_MASK 0x80000000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_240_RR_EN_SHIFT 31
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_240_RR_EN_DEFAULT 0x00000001
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_240_RR_EN_DISABLED 0
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_240_RR_EN_ENABLED 1
-
-/* MEMC_ARB_1 :: CLIENT_INFO_240 :: reserved0 [30:30] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_240_reserved0_MASK 0x40000000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_240_reserved0_SHIFT 30
-
-/* MEMC_ARB_1 :: CLIENT_INFO_240 :: BO_VAL [29:12] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_240_BO_VAL_MASK 0x3ffff000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_240_BO_VAL_SHIFT 12
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_240_BO_VAL_DEFAULT 0x00000000
-
-/* MEMC_ARB_1 :: CLIENT_INFO_240 :: reserved1 [11:08] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_240_reserved1_MASK 0x00000f00
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_240_reserved1_SHIFT 8
-
-/* MEMC_ARB_1 :: CLIENT_INFO_240 :: PR_TAG [07:00] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_240_PR_TAG_MASK 0x000000ff
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_240_PR_TAG_SHIFT 0
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_240_PR_TAG_DEFAULT 0x00000000
-
-/***************************************************************************
- *CLIENT_INFO_241 - Client Programming register for client 241.
- ***************************************************************************/
-/* MEMC_ARB_1 :: CLIENT_INFO_241 :: RR_EN [31:31] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_241_RR_EN_MASK 0x80000000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_241_RR_EN_SHIFT 31
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_241_RR_EN_DEFAULT 0x00000001
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_241_RR_EN_DISABLED 0
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_241_RR_EN_ENABLED 1
-
-/* MEMC_ARB_1 :: CLIENT_INFO_241 :: reserved0 [30:30] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_241_reserved0_MASK 0x40000000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_241_reserved0_SHIFT 30
-
-/* MEMC_ARB_1 :: CLIENT_INFO_241 :: BO_VAL [29:12] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_241_BO_VAL_MASK 0x3ffff000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_241_BO_VAL_SHIFT 12
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_241_BO_VAL_DEFAULT 0x00000000
-
-/* MEMC_ARB_1 :: CLIENT_INFO_241 :: reserved1 [11:08] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_241_reserved1_MASK 0x00000f00
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_241_reserved1_SHIFT 8
-
-/* MEMC_ARB_1 :: CLIENT_INFO_241 :: PR_TAG [07:00] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_241_PR_TAG_MASK 0x000000ff
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_241_PR_TAG_SHIFT 0
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_241_PR_TAG_DEFAULT 0x00000000
-
-/***************************************************************************
- *CLIENT_INFO_242 - Client Programming register for client 242.
- ***************************************************************************/
-/* MEMC_ARB_1 :: CLIENT_INFO_242 :: RR_EN [31:31] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_242_RR_EN_MASK 0x80000000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_242_RR_EN_SHIFT 31
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_242_RR_EN_DEFAULT 0x00000001
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_242_RR_EN_DISABLED 0
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_242_RR_EN_ENABLED 1
-
-/* MEMC_ARB_1 :: CLIENT_INFO_242 :: reserved0 [30:30] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_242_reserved0_MASK 0x40000000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_242_reserved0_SHIFT 30
-
-/* MEMC_ARB_1 :: CLIENT_INFO_242 :: BO_VAL [29:12] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_242_BO_VAL_MASK 0x3ffff000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_242_BO_VAL_SHIFT 12
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_242_BO_VAL_DEFAULT 0x00000000
-
-/* MEMC_ARB_1 :: CLIENT_INFO_242 :: reserved1 [11:08] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_242_reserved1_MASK 0x00000f00
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_242_reserved1_SHIFT 8
-
-/* MEMC_ARB_1 :: CLIENT_INFO_242 :: PR_TAG [07:00] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_242_PR_TAG_MASK 0x000000ff
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_242_PR_TAG_SHIFT 0
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_242_PR_TAG_DEFAULT 0x00000000
-
-/***************************************************************************
- *CLIENT_INFO_243 - Client Programming register for client 243.
- ***************************************************************************/
-/* MEMC_ARB_1 :: CLIENT_INFO_243 :: RR_EN [31:31] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_243_RR_EN_MASK 0x80000000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_243_RR_EN_SHIFT 31
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_243_RR_EN_DEFAULT 0x00000001
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_243_RR_EN_DISABLED 0
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_243_RR_EN_ENABLED 1
-
-/* MEMC_ARB_1 :: CLIENT_INFO_243 :: reserved0 [30:30] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_243_reserved0_MASK 0x40000000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_243_reserved0_SHIFT 30
-
-/* MEMC_ARB_1 :: CLIENT_INFO_243 :: BO_VAL [29:12] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_243_BO_VAL_MASK 0x3ffff000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_243_BO_VAL_SHIFT 12
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_243_BO_VAL_DEFAULT 0x00000000
-
-/* MEMC_ARB_1 :: CLIENT_INFO_243 :: reserved1 [11:08] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_243_reserved1_MASK 0x00000f00
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_243_reserved1_SHIFT 8
-
-/* MEMC_ARB_1 :: CLIENT_INFO_243 :: PR_TAG [07:00] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_243_PR_TAG_MASK 0x000000ff
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_243_PR_TAG_SHIFT 0
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_243_PR_TAG_DEFAULT 0x00000000
-
-/***************************************************************************
- *CLIENT_INFO_244 - Client Programming register for client 244.
- ***************************************************************************/
-/* MEMC_ARB_1 :: CLIENT_INFO_244 :: RR_EN [31:31] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_244_RR_EN_MASK 0x80000000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_244_RR_EN_SHIFT 31
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_244_RR_EN_DEFAULT 0x00000001
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_244_RR_EN_DISABLED 0
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_244_RR_EN_ENABLED 1
-
-/* MEMC_ARB_1 :: CLIENT_INFO_244 :: reserved0 [30:30] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_244_reserved0_MASK 0x40000000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_244_reserved0_SHIFT 30
-
-/* MEMC_ARB_1 :: CLIENT_INFO_244 :: BO_VAL [29:12] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_244_BO_VAL_MASK 0x3ffff000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_244_BO_VAL_SHIFT 12
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_244_BO_VAL_DEFAULT 0x00000000
-
-/* MEMC_ARB_1 :: CLIENT_INFO_244 :: reserved1 [11:08] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_244_reserved1_MASK 0x00000f00
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_244_reserved1_SHIFT 8
-
-/* MEMC_ARB_1 :: CLIENT_INFO_244 :: PR_TAG [07:00] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_244_PR_TAG_MASK 0x000000ff
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_244_PR_TAG_SHIFT 0
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_244_PR_TAG_DEFAULT 0x00000000
-
-/***************************************************************************
- *CLIENT_INFO_245 - Client Programming register for client 245.
- ***************************************************************************/
-/* MEMC_ARB_1 :: CLIENT_INFO_245 :: RR_EN [31:31] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_245_RR_EN_MASK 0x80000000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_245_RR_EN_SHIFT 31
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_245_RR_EN_DEFAULT 0x00000001
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_245_RR_EN_DISABLED 0
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_245_RR_EN_ENABLED 1
-
-/* MEMC_ARB_1 :: CLIENT_INFO_245 :: reserved0 [30:30] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_245_reserved0_MASK 0x40000000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_245_reserved0_SHIFT 30
-
-/* MEMC_ARB_1 :: CLIENT_INFO_245 :: BO_VAL [29:12] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_245_BO_VAL_MASK 0x3ffff000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_245_BO_VAL_SHIFT 12
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_245_BO_VAL_DEFAULT 0x00000000
-
-/* MEMC_ARB_1 :: CLIENT_INFO_245 :: reserved1 [11:08] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_245_reserved1_MASK 0x00000f00
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_245_reserved1_SHIFT 8
-
-/* MEMC_ARB_1 :: CLIENT_INFO_245 :: PR_TAG [07:00] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_245_PR_TAG_MASK 0x000000ff
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_245_PR_TAG_SHIFT 0
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_245_PR_TAG_DEFAULT 0x00000000
-
-/***************************************************************************
- *CLIENT_INFO_246 - Client Programming register for client 246.
- ***************************************************************************/
-/* MEMC_ARB_1 :: CLIENT_INFO_246 :: RR_EN [31:31] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_246_RR_EN_MASK 0x80000000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_246_RR_EN_SHIFT 31
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_246_RR_EN_DEFAULT 0x00000001
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_246_RR_EN_DISABLED 0
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_246_RR_EN_ENABLED 1
-
-/* MEMC_ARB_1 :: CLIENT_INFO_246 :: reserved0 [30:30] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_246_reserved0_MASK 0x40000000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_246_reserved0_SHIFT 30
-
-/* MEMC_ARB_1 :: CLIENT_INFO_246 :: BO_VAL [29:12] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_246_BO_VAL_MASK 0x3ffff000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_246_BO_VAL_SHIFT 12
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_246_BO_VAL_DEFAULT 0x00000000
-
-/* MEMC_ARB_1 :: CLIENT_INFO_246 :: reserved1 [11:08] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_246_reserved1_MASK 0x00000f00
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_246_reserved1_SHIFT 8
-
-/* MEMC_ARB_1 :: CLIENT_INFO_246 :: PR_TAG [07:00] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_246_PR_TAG_MASK 0x000000ff
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_246_PR_TAG_SHIFT 0
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_246_PR_TAG_DEFAULT 0x00000000
-
-/***************************************************************************
- *CLIENT_INFO_247 - Client Programming register for client 247.
- ***************************************************************************/
-/* MEMC_ARB_1 :: CLIENT_INFO_247 :: RR_EN [31:31] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_247_RR_EN_MASK 0x80000000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_247_RR_EN_SHIFT 31
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_247_RR_EN_DEFAULT 0x00000001
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_247_RR_EN_DISABLED 0
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_247_RR_EN_ENABLED 1
-
-/* MEMC_ARB_1 :: CLIENT_INFO_247 :: reserved0 [30:30] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_247_reserved0_MASK 0x40000000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_247_reserved0_SHIFT 30
-
-/* MEMC_ARB_1 :: CLIENT_INFO_247 :: BO_VAL [29:12] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_247_BO_VAL_MASK 0x3ffff000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_247_BO_VAL_SHIFT 12
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_247_BO_VAL_DEFAULT 0x00000000
-
-/* MEMC_ARB_1 :: CLIENT_INFO_247 :: reserved1 [11:08] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_247_reserved1_MASK 0x00000f00
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_247_reserved1_SHIFT 8
-
-/* MEMC_ARB_1 :: CLIENT_INFO_247 :: PR_TAG [07:00] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_247_PR_TAG_MASK 0x000000ff
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_247_PR_TAG_SHIFT 0
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_247_PR_TAG_DEFAULT 0x00000000
-
-/***************************************************************************
- *CLIENT_INFO_248 - Client Programming register for client 248.
- ***************************************************************************/
-/* MEMC_ARB_1 :: CLIENT_INFO_248 :: RR_EN [31:31] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_248_RR_EN_MASK 0x80000000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_248_RR_EN_SHIFT 31
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_248_RR_EN_DEFAULT 0x00000001
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_248_RR_EN_DISABLED 0
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_248_RR_EN_ENABLED 1
-
-/* MEMC_ARB_1 :: CLIENT_INFO_248 :: reserved0 [30:30] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_248_reserved0_MASK 0x40000000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_248_reserved0_SHIFT 30
-
-/* MEMC_ARB_1 :: CLIENT_INFO_248 :: BO_VAL [29:12] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_248_BO_VAL_MASK 0x3ffff000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_248_BO_VAL_SHIFT 12
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_248_BO_VAL_DEFAULT 0x00000000
-
-/* MEMC_ARB_1 :: CLIENT_INFO_248 :: reserved1 [11:08] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_248_reserved1_MASK 0x00000f00
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_248_reserved1_SHIFT 8
-
-/* MEMC_ARB_1 :: CLIENT_INFO_248 :: PR_TAG [07:00] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_248_PR_TAG_MASK 0x000000ff
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_248_PR_TAG_SHIFT 0
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_248_PR_TAG_DEFAULT 0x00000000
-
-/***************************************************************************
- *CLIENT_INFO_249 - Client Programming register for client 249.
- ***************************************************************************/
-/* MEMC_ARB_1 :: CLIENT_INFO_249 :: RR_EN [31:31] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_249_RR_EN_MASK 0x80000000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_249_RR_EN_SHIFT 31
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_249_RR_EN_DEFAULT 0x00000001
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_249_RR_EN_DISABLED 0
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_249_RR_EN_ENABLED 1
-
-/* MEMC_ARB_1 :: CLIENT_INFO_249 :: reserved0 [30:30] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_249_reserved0_MASK 0x40000000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_249_reserved0_SHIFT 30
-
-/* MEMC_ARB_1 :: CLIENT_INFO_249 :: BO_VAL [29:12] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_249_BO_VAL_MASK 0x3ffff000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_249_BO_VAL_SHIFT 12
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_249_BO_VAL_DEFAULT 0x00000000
-
-/* MEMC_ARB_1 :: CLIENT_INFO_249 :: reserved1 [11:08] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_249_reserved1_MASK 0x00000f00
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_249_reserved1_SHIFT 8
-
-/* MEMC_ARB_1 :: CLIENT_INFO_249 :: PR_TAG [07:00] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_249_PR_TAG_MASK 0x000000ff
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_249_PR_TAG_SHIFT 0
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_249_PR_TAG_DEFAULT 0x00000000
-
-/***************************************************************************
- *CLIENT_INFO_250 - Client Programming register for client 250.
- ***************************************************************************/
-/* MEMC_ARB_1 :: CLIENT_INFO_250 :: RR_EN [31:31] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_250_RR_EN_MASK 0x80000000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_250_RR_EN_SHIFT 31
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_250_RR_EN_DEFAULT 0x00000001
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_250_RR_EN_DISABLED 0
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_250_RR_EN_ENABLED 1
-
-/* MEMC_ARB_1 :: CLIENT_INFO_250 :: reserved0 [30:30] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_250_reserved0_MASK 0x40000000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_250_reserved0_SHIFT 30
-
-/* MEMC_ARB_1 :: CLIENT_INFO_250 :: BO_VAL [29:12] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_250_BO_VAL_MASK 0x3ffff000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_250_BO_VAL_SHIFT 12
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_250_BO_VAL_DEFAULT 0x00000000
-
-/* MEMC_ARB_1 :: CLIENT_INFO_250 :: reserved1 [11:08] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_250_reserved1_MASK 0x00000f00
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_250_reserved1_SHIFT 8
-
-/* MEMC_ARB_1 :: CLIENT_INFO_250 :: PR_TAG [07:00] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_250_PR_TAG_MASK 0x000000ff
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_250_PR_TAG_SHIFT 0
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_250_PR_TAG_DEFAULT 0x00000000
-
-/***************************************************************************
- *CLIENT_INFO_251 - Client Programming register for client 251.
- ***************************************************************************/
-/* MEMC_ARB_1 :: CLIENT_INFO_251 :: RR_EN [31:31] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_251_RR_EN_MASK 0x80000000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_251_RR_EN_SHIFT 31
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_251_RR_EN_DEFAULT 0x00000001
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_251_RR_EN_DISABLED 0
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_251_RR_EN_ENABLED 1
-
-/* MEMC_ARB_1 :: CLIENT_INFO_251 :: reserved0 [30:30] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_251_reserved0_MASK 0x40000000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_251_reserved0_SHIFT 30
-
-/* MEMC_ARB_1 :: CLIENT_INFO_251 :: BO_VAL [29:12] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_251_BO_VAL_MASK 0x3ffff000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_251_BO_VAL_SHIFT 12
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_251_BO_VAL_DEFAULT 0x00000000
-
-/* MEMC_ARB_1 :: CLIENT_INFO_251 :: reserved1 [11:08] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_251_reserved1_MASK 0x00000f00
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_251_reserved1_SHIFT 8
-
-/* MEMC_ARB_1 :: CLIENT_INFO_251 :: PR_TAG [07:00] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_251_PR_TAG_MASK 0x000000ff
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_251_PR_TAG_SHIFT 0
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_251_PR_TAG_DEFAULT 0x00000000
-
-/***************************************************************************
- *CLIENT_INFO_252 - Client Programming register for client 252.
- ***************************************************************************/
-/* MEMC_ARB_1 :: CLIENT_INFO_252 :: RR_EN [31:31] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_252_RR_EN_MASK 0x80000000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_252_RR_EN_SHIFT 31
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_252_RR_EN_DEFAULT 0x00000001
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_252_RR_EN_DISABLED 0
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_252_RR_EN_ENABLED 1
-
-/* MEMC_ARB_1 :: CLIENT_INFO_252 :: reserved0 [30:30] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_252_reserved0_MASK 0x40000000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_252_reserved0_SHIFT 30
-
-/* MEMC_ARB_1 :: CLIENT_INFO_252 :: BO_VAL [29:12] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_252_BO_VAL_MASK 0x3ffff000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_252_BO_VAL_SHIFT 12
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_252_BO_VAL_DEFAULT 0x00000000
-
-/* MEMC_ARB_1 :: CLIENT_INFO_252 :: reserved1 [11:08] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_252_reserved1_MASK 0x00000f00
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_252_reserved1_SHIFT 8
-
-/* MEMC_ARB_1 :: CLIENT_INFO_252 :: PR_TAG [07:00] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_252_PR_TAG_MASK 0x000000ff
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_252_PR_TAG_SHIFT 0
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_252_PR_TAG_DEFAULT 0x00000000
-
-/***************************************************************************
- *CLIENT_INFO_253 - Client Programming register for client 253.
- ***************************************************************************/
-/* MEMC_ARB_1 :: CLIENT_INFO_253 :: RR_EN [31:31] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_253_RR_EN_MASK 0x80000000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_253_RR_EN_SHIFT 31
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_253_RR_EN_DEFAULT 0x00000001
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_253_RR_EN_DISABLED 0
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_253_RR_EN_ENABLED 1
-
-/* MEMC_ARB_1 :: CLIENT_INFO_253 :: reserved0 [30:30] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_253_reserved0_MASK 0x40000000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_253_reserved0_SHIFT 30
-
-/* MEMC_ARB_1 :: CLIENT_INFO_253 :: BO_VAL [29:12] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_253_BO_VAL_MASK 0x3ffff000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_253_BO_VAL_SHIFT 12
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_253_BO_VAL_DEFAULT 0x00000000
-
-/* MEMC_ARB_1 :: CLIENT_INFO_253 :: reserved1 [11:08] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_253_reserved1_MASK 0x00000f00
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_253_reserved1_SHIFT 8
-
-/* MEMC_ARB_1 :: CLIENT_INFO_253 :: PR_TAG [07:00] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_253_PR_TAG_MASK 0x000000ff
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_253_PR_TAG_SHIFT 0
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_253_PR_TAG_DEFAULT 0x00000000
-
-/***************************************************************************
- *CLIENT_INFO_254 - Client Programming register for client 254.
- ***************************************************************************/
-/* MEMC_ARB_1 :: CLIENT_INFO_254 :: RR_EN [31:31] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_254_RR_EN_MASK 0x80000000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_254_RR_EN_SHIFT 31
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_254_RR_EN_DEFAULT 0x00000001
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_254_RR_EN_DISABLED 0
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_254_RR_EN_ENABLED 1
-
-/* MEMC_ARB_1 :: CLIENT_INFO_254 :: reserved0 [30:30] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_254_reserved0_MASK 0x40000000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_254_reserved0_SHIFT 30
-
-/* MEMC_ARB_1 :: CLIENT_INFO_254 :: BO_VAL [29:12] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_254_BO_VAL_MASK 0x3ffff000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_254_BO_VAL_SHIFT 12
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_254_BO_VAL_DEFAULT 0x00000000
-
-/* MEMC_ARB_1 :: CLIENT_INFO_254 :: reserved1 [11:08] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_254_reserved1_MASK 0x00000f00
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_254_reserved1_SHIFT 8
-
-/* MEMC_ARB_1 :: CLIENT_INFO_254 :: PR_TAG [07:00] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_254_PR_TAG_MASK 0x000000ff
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_254_PR_TAG_SHIFT 0
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_254_PR_TAG_DEFAULT 0x00000000
-
-/***************************************************************************
- *CLIENT_INFO_255 - Client Programming register for client 255
- ***************************************************************************/
-/* MEMC_ARB_1 :: CLIENT_INFO_255 :: RR_EN [31:31] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_255_RR_EN_MASK 0x80000000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_255_RR_EN_SHIFT 31
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_255_RR_EN_DEFAULT 0x00000000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_255_RR_EN_DISABLED 0
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_255_RR_EN_ENABLED 1
-
-/* MEMC_ARB_1 :: CLIENT_INFO_255 :: REF_PRD [30:12] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_255_REF_PRD_MASK 0x7ffff000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_255_REF_PRD_SHIFT 12
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_255_REF_PRD_DEFAULT 0x00000818
-
-/* MEMC_ARB_1 :: CLIENT_INFO_255 :: reserved0 [11:10] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_255_reserved0_MASK 0x00000c00
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_255_reserved0_SHIFT 10
-
-/* MEMC_ARB_1 :: CLIENT_INFO_255 :: REF_CLUST [09:08] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_255_REF_CLUST_MASK 0x00000300
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_255_REF_CLUST_SHIFT 8
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_255_REF_CLUST_DEFAULT 0x00000000
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_255_REF_CLUST_NO_CLUSTER 0
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_255_REF_CLUST_CLUSTER_TWO 1
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_255_REF_CLUST_CLUSTER_FOUR 2
-
-/* MEMC_ARB_1 :: CLIENT_INFO_255 :: PR_TAG [07:00] */
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_255_PR_TAG_MASK 0x000000ff
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_255_PR_TAG_SHIFT 0
-#define BCHP_MEMC_ARB_1_CLIENT_INFO_255_PR_TAG_DEFAULT 0x00000000
-
-/***************************************************************************
- *REQ_MASK_0 - Request Mask register for Clients 0 to 31
- ***************************************************************************/
-/* MEMC_ARB_1 :: REQ_MASK_0 :: MASK [31:00] */
-#define BCHP_MEMC_ARB_1_REQ_MASK_0_MASK_MASK 0xffffffff
-#define BCHP_MEMC_ARB_1_REQ_MASK_0_MASK_SHIFT 0
-#define BCHP_MEMC_ARB_1_REQ_MASK_0_MASK_DEFAULT 0x00000000
-#define BCHP_MEMC_ARB_1_REQ_MASK_0_MASK_UNMASK 0
-
-/***************************************************************************
- *REQ_MASK_1 - Request Mask register for Clients 32 to 63
- ***************************************************************************/
-/* MEMC_ARB_1 :: REQ_MASK_1 :: MASK [31:00] */
-#define BCHP_MEMC_ARB_1_REQ_MASK_1_MASK_MASK 0xffffffff
-#define BCHP_MEMC_ARB_1_REQ_MASK_1_MASK_SHIFT 0
-#define BCHP_MEMC_ARB_1_REQ_MASK_1_MASK_DEFAULT 0x00000000
-#define BCHP_MEMC_ARB_1_REQ_MASK_1_MASK_UNMASK 0
-
-/***************************************************************************
- *REQ_MASK_2 - Request Mask register for Clients 64 to 95
- ***************************************************************************/
-/* MEMC_ARB_1 :: REQ_MASK_2 :: MASK [31:00] */
-#define BCHP_MEMC_ARB_1_REQ_MASK_2_MASK_MASK 0xffffffff
-#define BCHP_MEMC_ARB_1_REQ_MASK_2_MASK_SHIFT 0
-#define BCHP_MEMC_ARB_1_REQ_MASK_2_MASK_DEFAULT 0x00000000
-#define BCHP_MEMC_ARB_1_REQ_MASK_2_MASK_UNMASK 0
-
-/***************************************************************************
- *REQ_MASK_3 - Request Mask register for Clients 96 to 127
- ***************************************************************************/
-/* MEMC_ARB_1 :: REQ_MASK_3 :: MASK [31:00] */
-#define BCHP_MEMC_ARB_1_REQ_MASK_3_MASK_MASK 0xffffffff
-#define BCHP_MEMC_ARB_1_REQ_MASK_3_MASK_SHIFT 0
-#define BCHP_MEMC_ARB_1_REQ_MASK_3_MASK_DEFAULT 0x00000000
-#define BCHP_MEMC_ARB_1_REQ_MASK_3_MASK_UNMASK 0
-
-/***************************************************************************
- *REQ_MASK_4 - Request Mask register for Clients 128 to 159
- ***************************************************************************/
-/* MEMC_ARB_1 :: REQ_MASK_4 :: MASK [31:00] */
-#define BCHP_MEMC_ARB_1_REQ_MASK_4_MASK_MASK 0xffffffff
-#define BCHP_MEMC_ARB_1_REQ_MASK_4_MASK_SHIFT 0
-#define BCHP_MEMC_ARB_1_REQ_MASK_4_MASK_DEFAULT 0x00000000
-#define BCHP_MEMC_ARB_1_REQ_MASK_4_MASK_UNMASK 0
-
-/***************************************************************************
- *REQ_MASK_5 - Request Mask register for Clients 160 to 191
- ***************************************************************************/
-/* MEMC_ARB_1 :: REQ_MASK_5 :: MASK [31:00] */
-#define BCHP_MEMC_ARB_1_REQ_MASK_5_MASK_MASK 0xffffffff
-#define BCHP_MEMC_ARB_1_REQ_MASK_5_MASK_SHIFT 0
-#define BCHP_MEMC_ARB_1_REQ_MASK_5_MASK_DEFAULT 0x00000000
-#define BCHP_MEMC_ARB_1_REQ_MASK_5_MASK_UNMASK 0
-
-/***************************************************************************
- *REQ_MASK_6 - Request Mask register for Clients 192 to 223
- ***************************************************************************/
-/* MEMC_ARB_1 :: REQ_MASK_6 :: MASK [31:00] */
-#define BCHP_MEMC_ARB_1_REQ_MASK_6_MASK_MASK 0xffffffff
-#define BCHP_MEMC_ARB_1_REQ_MASK_6_MASK_SHIFT 0
-#define BCHP_MEMC_ARB_1_REQ_MASK_6_MASK_DEFAULT 0x00000000
-#define BCHP_MEMC_ARB_1_REQ_MASK_6_MASK_UNMASK 0
-
-/***************************************************************************
- *REQ_MASK_7 - Request Mask register for Clients 224 to 255
- ***************************************************************************/
-/* MEMC_ARB_1 :: REQ_MASK_7 :: MASK [31:00] */
-#define BCHP_MEMC_ARB_1_REQ_MASK_7_MASK_MASK 0xffffffff
-#define BCHP_MEMC_ARB_1_REQ_MASK_7_MASK_SHIFT 0
-#define BCHP_MEMC_ARB_1_REQ_MASK_7_MASK_DEFAULT 0x00000000
-#define BCHP_MEMC_ARB_1_REQ_MASK_7_MASK_UNMASK 0
-
-/***************************************************************************
- *ARB_WINNER - SCB-Arbitration Winner.
- ***************************************************************************/
-/* MEMC_ARB_1 :: ARB_WINNER :: reserved0 [31:08] */
-#define BCHP_MEMC_ARB_1_ARB_WINNER_reserved0_MASK 0xffffff00
-#define BCHP_MEMC_ARB_1_ARB_WINNER_reserved0_SHIFT 8
-
-/* MEMC_ARB_1 :: ARB_WINNER :: CLIENT_ID [07:00] */
-#define BCHP_MEMC_ARB_1_ARB_WINNER_CLIENT_ID_MASK 0x000000ff
-#define BCHP_MEMC_ARB_1_ARB_WINNER_CLIENT_ID_SHIFT 0
-#define BCHP_MEMC_ARB_1_ARB_WINNER_CLIENT_ID_DEFAULT 0x00000000
-
-/***************************************************************************
- *RTS_ERR_0 - RTS Deadline miss register for Clients 0 to 31
- ***************************************************************************/
-/* MEMC_ARB_1 :: RTS_ERR_0 :: CLIENT [31:00] */
-#define BCHP_MEMC_ARB_1_RTS_ERR_0_CLIENT_MASK 0xffffffff
-#define BCHP_MEMC_ARB_1_RTS_ERR_0_CLIENT_SHIFT 0
-#define BCHP_MEMC_ARB_1_RTS_ERR_0_CLIENT_DEFAULT 0x00000000
-#define BCHP_MEMC_ARB_1_RTS_ERR_0_CLIENT_ERROR 1
-#define BCHP_MEMC_ARB_1_RTS_ERR_0_CLIENT_NOERROR 0
-
-/***************************************************************************
- *RTS_ERR_1 - RTS Deadline miss register for Clients 32 to 63
- ***************************************************************************/
-/* MEMC_ARB_1 :: RTS_ERR_1 :: CLIENT [31:00] */
-#define BCHP_MEMC_ARB_1_RTS_ERR_1_CLIENT_MASK 0xffffffff
-#define BCHP_MEMC_ARB_1_RTS_ERR_1_CLIENT_SHIFT 0
-#define BCHP_MEMC_ARB_1_RTS_ERR_1_CLIENT_DEFAULT 0x00000000
-#define BCHP_MEMC_ARB_1_RTS_ERR_1_CLIENT_ERROR 1
-#define BCHP_MEMC_ARB_1_RTS_ERR_1_CLIENT_NOERROR 0
-
-/***************************************************************************
- *RTS_ERR_2 - RTS Deadline miss register for Clients 64 to 95
- ***************************************************************************/
-/* MEMC_ARB_1 :: RTS_ERR_2 :: CLIENT [31:00] */
-#define BCHP_MEMC_ARB_1_RTS_ERR_2_CLIENT_MASK 0xffffffff
-#define BCHP_MEMC_ARB_1_RTS_ERR_2_CLIENT_SHIFT 0
-#define BCHP_MEMC_ARB_1_RTS_ERR_2_CLIENT_DEFAULT 0x00000000
-#define BCHP_MEMC_ARB_1_RTS_ERR_2_CLIENT_ERROR 1
-#define BCHP_MEMC_ARB_1_RTS_ERR_2_CLIENT_NOERROR 0
-
-/***************************************************************************
- *RTS_ERR_3 - RTS Deadline miss register for Clients 96 to 127
- ***************************************************************************/
-/* MEMC_ARB_1 :: RTS_ERR_3 :: CLIENT [31:00] */
-#define BCHP_MEMC_ARB_1_RTS_ERR_3_CLIENT_MASK 0xffffffff
-#define BCHP_MEMC_ARB_1_RTS_ERR_3_CLIENT_SHIFT 0
-#define BCHP_MEMC_ARB_1_RTS_ERR_3_CLIENT_DEFAULT 0x00000000
-#define BCHP_MEMC_ARB_1_RTS_ERR_3_CLIENT_ERROR 1
-#define BCHP_MEMC_ARB_1_RTS_ERR_3_CLIENT_NOERROR 0
-
-/***************************************************************************
- *RTS_ERR_4 - RTS Deadline miss register for Clients 128 to 159
- ***************************************************************************/
-/* MEMC_ARB_1 :: RTS_ERR_4 :: CLIENT [31:00] */
-#define BCHP_MEMC_ARB_1_RTS_ERR_4_CLIENT_MASK 0xffffffff
-#define BCHP_MEMC_ARB_1_RTS_ERR_4_CLIENT_SHIFT 0
-#define BCHP_MEMC_ARB_1_RTS_ERR_4_CLIENT_DEFAULT 0x00000000
-#define BCHP_MEMC_ARB_1_RTS_ERR_4_CLIENT_ERROR 1
-#define BCHP_MEMC_ARB_1_RTS_ERR_4_CLIENT_NOERROR 0
-
-/***************************************************************************
- *RTS_ERR_5 - RTS Deadline miss register for Clients 160 to 191
- ***************************************************************************/
-/* MEMC_ARB_1 :: RTS_ERR_5 :: CLIENT [31:00] */
-#define BCHP_MEMC_ARB_1_RTS_ERR_5_CLIENT_MASK 0xffffffff
-#define BCHP_MEMC_ARB_1_RTS_ERR_5_CLIENT_SHIFT 0
-#define BCHP_MEMC_ARB_1_RTS_ERR_5_CLIENT_DEFAULT 0x00000000
-#define BCHP_MEMC_ARB_1_RTS_ERR_5_CLIENT_ERROR 1
-#define BCHP_MEMC_ARB_1_RTS_ERR_5_CLIENT_NOERROR 0
-
-/***************************************************************************
- *RTS_ERR_6 - RTS Deadline miss register for Clients 192 to 223
- ***************************************************************************/
-/* MEMC_ARB_1 :: RTS_ERR_6 :: CLIENT [31:00] */
-#define BCHP_MEMC_ARB_1_RTS_ERR_6_CLIENT_MASK 0xffffffff
-#define BCHP_MEMC_ARB_1_RTS_ERR_6_CLIENT_SHIFT 0
-#define BCHP_MEMC_ARB_1_RTS_ERR_6_CLIENT_DEFAULT 0x00000000
-#define BCHP_MEMC_ARB_1_RTS_ERR_6_CLIENT_ERROR 1
-#define BCHP_MEMC_ARB_1_RTS_ERR_6_CLIENT_NOERROR 0
-
-/***************************************************************************
- *RTS_ERR_7 - RTS Deadline miss register for Clients 224 to 255
- ***************************************************************************/
-/* MEMC_ARB_1 :: RTS_ERR_7 :: CLIENT [31:00] */
-#define BCHP_MEMC_ARB_1_RTS_ERR_7_CLIENT_MASK 0xffffffff
-#define BCHP_MEMC_ARB_1_RTS_ERR_7_CLIENT_SHIFT 0
-#define BCHP_MEMC_ARB_1_RTS_ERR_7_CLIENT_DEFAULT 0x00000000
-#define BCHP_MEMC_ARB_1_RTS_ERR_7_CLIENT_ERROR 1
-#define BCHP_MEMC_ARB_1_RTS_ERR_7_CLIENT_NOERROR 0
-
-/***************************************************************************
- *FULLNESS_THRESHOLD - Arbiter fullness threshold register
- ***************************************************************************/
-/* MEMC_ARB_1 :: FULLNESS_THRESHOLD :: reserved0 [31:06] */
-#define BCHP_MEMC_ARB_1_FULLNESS_THRESHOLD_reserved0_MASK 0xffffffc0
-#define BCHP_MEMC_ARB_1_FULLNESS_THRESHOLD_reserved0_SHIFT 6
-
-/* MEMC_ARB_1 :: FULLNESS_THRESHOLD :: FULLNESS_THRESHOLD_VALUE [05:00] */
-#define BCHP_MEMC_ARB_1_FULLNESS_THRESHOLD_FULLNESS_THRESHOLD_VALUE_MASK 0x0000003f
-#define BCHP_MEMC_ARB_1_FULLNESS_THRESHOLD_FULLNESS_THRESHOLD_VALUE_SHIFT 0
-#define BCHP_MEMC_ARB_1_FULLNESS_THRESHOLD_FULLNESS_THRESHOLD_VALUE_DEFAULT 0x00000005
-
-/***************************************************************************
- *FULLNESS_UPDATE_HOLDOFF - SCB and MCP Write Fullness Update Holdoff register
- ***************************************************************************/
-/* MEMC_ARB_1 :: FULLNESS_UPDATE_HOLDOFF :: reserved0 [31:06] */
-#define BCHP_MEMC_ARB_1_FULLNESS_UPDATE_HOLDOFF_reserved0_MASK 0xffffffc0
-#define BCHP_MEMC_ARB_1_FULLNESS_UPDATE_HOLDOFF_reserved0_SHIFT 6
-
-/* MEMC_ARB_1 :: FULLNESS_UPDATE_HOLDOFF :: SCB_MCP_WRITE_DATA_FULLNESS_UPDATE_HOLDOFF [05:00] */
-#define BCHP_MEMC_ARB_1_FULLNESS_UPDATE_HOLDOFF_SCB_MCP_WRITE_DATA_FULLNESS_UPDATE_HOLDOFF_MASK 0x0000003f
-#define BCHP_MEMC_ARB_1_FULLNESS_UPDATE_HOLDOFF_SCB_MCP_WRITE_DATA_FULLNESS_UPDATE_HOLDOFF_SHIFT 0
-#define BCHP_MEMC_ARB_1_FULLNESS_UPDATE_HOLDOFF_SCB_MCP_WRITE_DATA_FULLNESS_UPDATE_HOLDOFF_DEFAULT 0x00000002
-
-/***************************************************************************
- *MINIMUM_COMMAND_SIZE - Minimum command size register
- ***************************************************************************/
-/* MEMC_ARB_1 :: MINIMUM_COMMAND_SIZE :: reserved0 [31:30] */
-#define BCHP_MEMC_ARB_1_MINIMUM_COMMAND_SIZE_reserved0_MASK 0xc0000000
-#define BCHP_MEMC_ARB_1_MINIMUM_COMMAND_SIZE_reserved0_SHIFT 30
-
-/* MEMC_ARB_1 :: MINIMUM_COMMAND_SIZE :: MINIMUM_MCP_COMMAND_SIZE [29:24] */
-#define BCHP_MEMC_ARB_1_MINIMUM_COMMAND_SIZE_MINIMUM_MCP_COMMAND_SIZE_MASK 0x3f000000
-#define BCHP_MEMC_ARB_1_MINIMUM_COMMAND_SIZE_MINIMUM_MCP_COMMAND_SIZE_SHIFT 24
-#define BCHP_MEMC_ARB_1_MINIMUM_COMMAND_SIZE_MINIMUM_MCP_COMMAND_SIZE_DEFAULT 0x00000003
-
-/* MEMC_ARB_1 :: MINIMUM_COMMAND_SIZE :: reserved1 [23:22] */
-#define BCHP_MEMC_ARB_1_MINIMUM_COMMAND_SIZE_reserved1_MASK 0x00c00000
-#define BCHP_MEMC_ARB_1_MINIMUM_COMMAND_SIZE_reserved1_SHIFT 22
-
-/* MEMC_ARB_1 :: MINIMUM_COMMAND_SIZE :: MINIMUM_LMB_COMMAND_SIZE [21:16] */
-#define BCHP_MEMC_ARB_1_MINIMUM_COMMAND_SIZE_MINIMUM_LMB_COMMAND_SIZE_MASK 0x003f0000
-#define BCHP_MEMC_ARB_1_MINIMUM_COMMAND_SIZE_MINIMUM_LMB_COMMAND_SIZE_SHIFT 16
-#define BCHP_MEMC_ARB_1_MINIMUM_COMMAND_SIZE_MINIMUM_LMB_COMMAND_SIZE_DEFAULT 0x00000003
-
-/* MEMC_ARB_1 :: MINIMUM_COMMAND_SIZE :: reserved2 [15:14] */
-#define BCHP_MEMC_ARB_1_MINIMUM_COMMAND_SIZE_reserved2_MASK 0x0000c000
-#define BCHP_MEMC_ARB_1_MINIMUM_COMMAND_SIZE_reserved2_SHIFT 14
-
-/* MEMC_ARB_1 :: MINIMUM_COMMAND_SIZE :: MINIMUM_PFRI_COMMAND_SIZE [13:08] */
-#define BCHP_MEMC_ARB_1_MINIMUM_COMMAND_SIZE_MINIMUM_PFRI_COMMAND_SIZE_MASK 0x00003f00
-#define BCHP_MEMC_ARB_1_MINIMUM_COMMAND_SIZE_MINIMUM_PFRI_COMMAND_SIZE_SHIFT 8
-#define BCHP_MEMC_ARB_1_MINIMUM_COMMAND_SIZE_MINIMUM_PFRI_COMMAND_SIZE_DEFAULT 0x00000003
-
-/* MEMC_ARB_1 :: MINIMUM_COMMAND_SIZE :: reserved3 [07:06] */
-#define BCHP_MEMC_ARB_1_MINIMUM_COMMAND_SIZE_reserved3_MASK 0x000000c0
-#define BCHP_MEMC_ARB_1_MINIMUM_COMMAND_SIZE_reserved3_SHIFT 6
-
-/* MEMC_ARB_1 :: MINIMUM_COMMAND_SIZE :: MINIMUM_SCB_COMMAND_SIZE [05:00] */
-#define BCHP_MEMC_ARB_1_MINIMUM_COMMAND_SIZE_MINIMUM_SCB_COMMAND_SIZE_MASK 0x0000003f
-#define BCHP_MEMC_ARB_1_MINIMUM_COMMAND_SIZE_MINIMUM_SCB_COMMAND_SIZE_SHIFT 0
-#define BCHP_MEMC_ARB_1_MINIMUM_COMMAND_SIZE_MINIMUM_SCB_COMMAND_SIZE_DEFAULT 0x00000003
-
-/***************************************************************************
- *MINIMUM_COMMAND_SIZE2 - Minimum command size register for UBUS
- ***************************************************************************/
-/* MEMC_ARB_1 :: MINIMUM_COMMAND_SIZE2 :: reserved0 [31:06] */
-#define BCHP_MEMC_ARB_1_MINIMUM_COMMAND_SIZE2_reserved0_MASK 0xffffffc0
-#define BCHP_MEMC_ARB_1_MINIMUM_COMMAND_SIZE2_reserved0_SHIFT 6
-
-/* MEMC_ARB_1 :: MINIMUM_COMMAND_SIZE2 :: MINIMUM_UBUS_COMMAND_SIZE [05:00] */
-#define BCHP_MEMC_ARB_1_MINIMUM_COMMAND_SIZE2_MINIMUM_UBUS_COMMAND_SIZE_MASK 0x0000003f
-#define BCHP_MEMC_ARB_1_MINIMUM_COMMAND_SIZE2_MINIMUM_UBUS_COMMAND_SIZE_SHIFT 0
-#define BCHP_MEMC_ARB_1_MINIMUM_COMMAND_SIZE2_MINIMUM_UBUS_COMMAND_SIZE_DEFAULT 0x00000003
-
-/***************************************************************************
- *RTS_ERR_INFO_WRITE_CLEAR - MEMC RTS_ERR_INFO write clear register
- ***************************************************************************/
-/* MEMC_ARB_1 :: RTS_ERR_INFO_WRITE_CLEAR :: reserved0 [31:01] */
-#define BCHP_MEMC_ARB_1_RTS_ERR_INFO_WRITE_CLEAR_reserved0_MASK 0xfffffffe
-#define BCHP_MEMC_ARB_1_RTS_ERR_INFO_WRITE_CLEAR_reserved0_SHIFT 1
-
-/* MEMC_ARB_1 :: RTS_ERR_INFO_WRITE_CLEAR :: WRITE_CLEAR [00:00] */
-#define BCHP_MEMC_ARB_1_RTS_ERR_INFO_WRITE_CLEAR_WRITE_CLEAR_MASK 0x00000001
-#define BCHP_MEMC_ARB_1_RTS_ERR_INFO_WRITE_CLEAR_WRITE_CLEAR_SHIFT 0
-#define BCHP_MEMC_ARB_1_RTS_ERR_INFO_WRITE_CLEAR_WRITE_CLEAR_DEFAULT 0x00000000
-
-/***************************************************************************
- *SCB_ARBITER_DEBUG_REGISTER - MEMC SCB Interface and Arbiter State Machine and FIFO Debug Register
- ***************************************************************************/
-/* MEMC_ARB_1 :: SCB_ARBITER_DEBUG_REGISTER :: reserved0 [31:30] */
-#define BCHP_MEMC_ARB_1_SCB_ARBITER_DEBUG_REGISTER_reserved0_MASK 0xc0000000
-#define BCHP_MEMC_ARB_1_SCB_ARBITER_DEBUG_REGISTER_reserved0_SHIFT 30
-
-/* MEMC_ARB_1 :: SCB_ARBITER_DEBUG_REGISTER :: SCB_RD_STATE [29:28] */
-#define BCHP_MEMC_ARB_1_SCB_ARBITER_DEBUG_REGISTER_SCB_RD_STATE_MASK 0x30000000
-#define BCHP_MEMC_ARB_1_SCB_ARBITER_DEBUG_REGISTER_SCB_RD_STATE_SHIFT 28
-
-/* MEMC_ARB_1 :: SCB_ARBITER_DEBUG_REGISTER :: reserved1 [27:26] */
-#define BCHP_MEMC_ARB_1_SCB_ARBITER_DEBUG_REGISTER_reserved1_MASK 0x0c000000
-#define BCHP_MEMC_ARB_1_SCB_ARBITER_DEBUG_REGISTER_reserved1_SHIFT 26
-
-/* MEMC_ARB_1 :: SCB_ARBITER_DEBUG_REGISTER :: SS_WR_STRB_STATE [25:24] */
-#define BCHP_MEMC_ARB_1_SCB_ARBITER_DEBUG_REGISTER_SS_WR_STRB_STATE_MASK 0x03000000
-#define BCHP_MEMC_ARB_1_SCB_ARBITER_DEBUG_REGISTER_SS_WR_STRB_STATE_SHIFT 24
-
-/* MEMC_ARB_1 :: SCB_ARBITER_DEBUG_REGISTER :: reserved2 [23:21] */
-#define BCHP_MEMC_ARB_1_SCB_ARBITER_DEBUG_REGISTER_reserved2_MASK 0x00e00000
-#define BCHP_MEMC_ARB_1_SCB_ARBITER_DEBUG_REGISTER_reserved2_SHIFT 21
-
-/* MEMC_ARB_1 :: SCB_ARBITER_DEBUG_REGISTER :: SCB_LAST_WRITE_STATE [20:20] */
-#define BCHP_MEMC_ARB_1_SCB_ARBITER_DEBUG_REGISTER_SCB_LAST_WRITE_STATE_MASK 0x00100000
-#define BCHP_MEMC_ARB_1_SCB_ARBITER_DEBUG_REGISTER_SCB_LAST_WRITE_STATE_SHIFT 20
-
-/* MEMC_ARB_1 :: SCB_ARBITER_DEBUG_REGISTER :: reserved3 [19:17] */
-#define BCHP_MEMC_ARB_1_SCB_ARBITER_DEBUG_REGISTER_reserved3_MASK 0x000e0000
-#define BCHP_MEMC_ARB_1_SCB_ARBITER_DEBUG_REGISTER_reserved3_SHIFT 17
-
-/* MEMC_ARB_1 :: SCB_ARBITER_DEBUG_REGISTER :: SCB_WR_NATIVE_WORD_STATE [16:16] */
-#define BCHP_MEMC_ARB_1_SCB_ARBITER_DEBUG_REGISTER_SCB_WR_NATIVE_WORD_STATE_MASK 0x00010000
-#define BCHP_MEMC_ARB_1_SCB_ARBITER_DEBUG_REGISTER_SCB_WR_NATIVE_WORD_STATE_SHIFT 16
-
-/* MEMC_ARB_1 :: SCB_ARBITER_DEBUG_REGISTER :: reserved4 [15:14] */
-#define BCHP_MEMC_ARB_1_SCB_ARBITER_DEBUG_REGISTER_reserved4_MASK 0x0000c000
-#define BCHP_MEMC_ARB_1_SCB_ARBITER_DEBUG_REGISTER_reserved4_SHIFT 14
-
-/* MEMC_ARB_1 :: SCB_ARBITER_DEBUG_REGISTER :: SCB_WR_DATA_FIFO_FULL [13:13] */
-#define BCHP_MEMC_ARB_1_SCB_ARBITER_DEBUG_REGISTER_SCB_WR_DATA_FIFO_FULL_MASK 0x00002000
-#define BCHP_MEMC_ARB_1_SCB_ARBITER_DEBUG_REGISTER_SCB_WR_DATA_FIFO_FULL_SHIFT 13
-
-/* MEMC_ARB_1 :: SCB_ARBITER_DEBUG_REGISTER :: SCB_WR_DATA_FIFO_EMPTY [12:12] */
-#define BCHP_MEMC_ARB_1_SCB_ARBITER_DEBUG_REGISTER_SCB_WR_DATA_FIFO_EMPTY_MASK 0x00001000
-#define BCHP_MEMC_ARB_1_SCB_ARBITER_DEBUG_REGISTER_SCB_WR_DATA_FIFO_EMPTY_SHIFT 12
-
-/* MEMC_ARB_1 :: SCB_ARBITER_DEBUG_REGISTER :: SCB_WR_MASK_FIFO_FULL [11:11] */
-#define BCHP_MEMC_ARB_1_SCB_ARBITER_DEBUG_REGISTER_SCB_WR_MASK_FIFO_FULL_MASK 0x00000800
-#define BCHP_MEMC_ARB_1_SCB_ARBITER_DEBUG_REGISTER_SCB_WR_MASK_FIFO_FULL_SHIFT 11
-
-/* MEMC_ARB_1 :: SCB_ARBITER_DEBUG_REGISTER :: SCB_WR_MASK_FIFO_EMPTY [10:10] */
-#define BCHP_MEMC_ARB_1_SCB_ARBITER_DEBUG_REGISTER_SCB_WR_MASK_FIFO_EMPTY_MASK 0x00000400
-#define BCHP_MEMC_ARB_1_SCB_ARBITER_DEBUG_REGISTER_SCB_WR_MASK_FIFO_EMPTY_SHIFT 10
-
-/* MEMC_ARB_1 :: SCB_ARBITER_DEBUG_REGISTER :: SCB_CMD_FIFO_FULL [09:09] */
-#define BCHP_MEMC_ARB_1_SCB_ARBITER_DEBUG_REGISTER_SCB_CMD_FIFO_FULL_MASK 0x00000200
-#define BCHP_MEMC_ARB_1_SCB_ARBITER_DEBUG_REGISTER_SCB_CMD_FIFO_FULL_SHIFT 9
-
-/* MEMC_ARB_1 :: SCB_ARBITER_DEBUG_REGISTER :: SCB_CMD_FIFO_EMPTY [08:08] */
-#define BCHP_MEMC_ARB_1_SCB_ARBITER_DEBUG_REGISTER_SCB_CMD_FIFO_EMPTY_MASK 0x00000100
-#define BCHP_MEMC_ARB_1_SCB_ARBITER_DEBUG_REGISTER_SCB_CMD_FIFO_EMPTY_SHIFT 8
-
-/* MEMC_ARB_1 :: SCB_ARBITER_DEBUG_REGISTER :: reserved5 [07:06] */
-#define BCHP_MEMC_ARB_1_SCB_ARBITER_DEBUG_REGISTER_reserved5_MASK 0x000000c0
-#define BCHP_MEMC_ARB_1_SCB_ARBITER_DEBUG_REGISTER_reserved5_SHIFT 6
-
-/* MEMC_ARB_1 :: SCB_ARBITER_DEBUG_REGISTER :: LCA_ARB_STATE [05:03] */
-#define BCHP_MEMC_ARB_1_SCB_ARBITER_DEBUG_REGISTER_LCA_ARB_STATE_MASK 0x00000038
-#define BCHP_MEMC_ARB_1_SCB_ARBITER_DEBUG_REGISTER_LCA_ARB_STATE_SHIFT 3
-
-/* MEMC_ARB_1 :: SCB_ARBITER_DEBUG_REGISTER :: RCA_ARB_STATE [02:00] */
-#define BCHP_MEMC_ARB_1_SCB_ARBITER_DEBUG_REGISTER_RCA_ARB_STATE_MASK 0x00000007
-#define BCHP_MEMC_ARB_1_SCB_ARBITER_DEBUG_REGISTER_RCA_ARB_STATE_SHIFT 0
-
-/***************************************************************************
- *SPARE_1 - Spare Register 1 .
- ***************************************************************************/
-/* MEMC_ARB_1 :: SPARE_1 :: SPARE [31:00] */
-#define BCHP_MEMC_ARB_1_SPARE_1_SPARE_MASK 0xffffffff
-#define BCHP_MEMC_ARB_1_SPARE_1_SPARE_SHIFT 0
-#define BCHP_MEMC_ARB_1_SPARE_1_SPARE_DEFAULT 0x00000000
-
-/***************************************************************************
- *SPARE_2 - Spare Register 2 .
- ***************************************************************************/
-/* MEMC_ARB_1 :: SPARE_2 :: SPARE [31:00] */
-#define BCHP_MEMC_ARB_1_SPARE_2_SPARE_MASK 0xffffffff
-#define BCHP_MEMC_ARB_1_SPARE_2_SPARE_SHIFT 0
-#define BCHP_MEMC_ARB_1_SPARE_2_SPARE_DEFAULT 0x00000000
-
-/***************************************************************************
- *SPARE_RO_1 - Read only Spare Register 1 .
- ***************************************************************************/
-/* MEMC_ARB_1 :: SPARE_RO_1 :: SPARE_RO [31:00] */
-#define BCHP_MEMC_ARB_1_SPARE_RO_1_SPARE_RO_MASK 0xffffffff
-#define BCHP_MEMC_ARB_1_SPARE_RO_1_SPARE_RO_SHIFT 0
-#define BCHP_MEMC_ARB_1_SPARE_RO_1_SPARE_RO_DEFAULT 0x00000000
-
-/***************************************************************************
- *SPARE_RO_2 - Read only Spare Register 2 .
- ***************************************************************************/
-/* MEMC_ARB_1 :: SPARE_RO_2 :: SPARE_RO [31:00] */
-#define BCHP_MEMC_ARB_1_SPARE_RO_2_SPARE_RO_MASK 0xffffffff
-#define BCHP_MEMC_ARB_1_SPARE_RO_2_SPARE_RO_SHIFT 0
-#define BCHP_MEMC_ARB_1_SPARE_RO_2_SPARE_RO_DEFAULT 0x00000000
-
-/***************************************************************************
- *CLIENT_INIT_ENABLE - "Enable for client init block."
- ***************************************************************************/
-/* MEMC_ARB_1 :: CLIENT_INIT_ENABLE :: reserved0 [31:01] */
-#define BCHP_MEMC_ARB_1_CLIENT_INIT_ENABLE_reserved0_MASK 0xfffffffe
-#define BCHP_MEMC_ARB_1_CLIENT_INIT_ENABLE_reserved0_SHIFT 1
-
-/* MEMC_ARB_1 :: CLIENT_INIT_ENABLE :: ENABLE [00:00] */
-#define BCHP_MEMC_ARB_1_CLIENT_INIT_ENABLE_ENABLE_MASK 0x00000001
-#define BCHP_MEMC_ARB_1_CLIENT_INIT_ENABLE_ENABLE_SHIFT 0
-#define BCHP_MEMC_ARB_1_CLIENT_INIT_ENABLE_ENABLE_DEFAULT 0x00000001
-
-/***************************************************************************
- *CLIENT_INIT_COUNTER_THRESH - "Client init block counter threshold value"
- ***************************************************************************/
-/* MEMC_ARB_1 :: CLIENT_INIT_COUNTER_THRESH :: reserved0 [31:12] */
-#define BCHP_MEMC_ARB_1_CLIENT_INIT_COUNTER_THRESH_reserved0_MASK 0xfffff000
-#define BCHP_MEMC_ARB_1_CLIENT_INIT_COUNTER_THRESH_reserved0_SHIFT 12
-
-/* MEMC_ARB_1 :: CLIENT_INIT_COUNTER_THRESH :: THRESHOLD [11:00] */
-#define BCHP_MEMC_ARB_1_CLIENT_INIT_COUNTER_THRESH_THRESHOLD_MASK 0x00000fff
-#define BCHP_MEMC_ARB_1_CLIENT_INIT_COUNTER_THRESH_THRESHOLD_SHIFT 0
-#define BCHP_MEMC_ARB_1_CLIENT_INIT_COUNTER_THRESH_THRESHOLD_DEFAULT 0x00000100
-
-/***************************************************************************
- *CLIENT_INIT_ERROR_INTERRUPT - "Client init error interrupt"
- ***************************************************************************/
-/* MEMC_ARB_1 :: CLIENT_INIT_ERROR_INTERRUPT :: reserved0 [31:01] */
-#define BCHP_MEMC_ARB_1_CLIENT_INIT_ERROR_INTERRUPT_reserved0_MASK 0xfffffffe
-#define BCHP_MEMC_ARB_1_CLIENT_INIT_ERROR_INTERRUPT_reserved0_SHIFT 1
-
-/* MEMC_ARB_1 :: CLIENT_INIT_ERROR_INTERRUPT :: INIT_REQ_ERROR [00:00] */
-#define BCHP_MEMC_ARB_1_CLIENT_INIT_ERROR_INTERRUPT_INIT_REQ_ERROR_MASK 0x00000001
-#define BCHP_MEMC_ARB_1_CLIENT_INIT_ERROR_INTERRUPT_INIT_REQ_ERROR_SHIFT 0
-#define BCHP_MEMC_ARB_1_CLIENT_INIT_ERROR_INTERRUPT_INIT_REQ_ERROR_DEFAULT 0x00000000
-
-/***************************************************************************
- *CLIENT_INIT_ERROR_WRITE_CLEAR - "Client init error write clear"
- ***************************************************************************/
-/* MEMC_ARB_1 :: CLIENT_INIT_ERROR_WRITE_CLEAR :: reserved0 [31:01] */
-#define BCHP_MEMC_ARB_1_CLIENT_INIT_ERROR_WRITE_CLEAR_reserved0_MASK 0xfffffffe
-#define BCHP_MEMC_ARB_1_CLIENT_INIT_ERROR_WRITE_CLEAR_reserved0_SHIFT 1
-
-/* MEMC_ARB_1 :: CLIENT_INIT_ERROR_WRITE_CLEAR :: WRITE_CLEAR [00:00] */
-#define BCHP_MEMC_ARB_1_CLIENT_INIT_ERROR_WRITE_CLEAR_WRITE_CLEAR_MASK 0x00000001
-#define BCHP_MEMC_ARB_1_CLIENT_INIT_ERROR_WRITE_CLEAR_WRITE_CLEAR_SHIFT 0
-#define BCHP_MEMC_ARB_1_CLIENT_INIT_ERROR_WRITE_CLEAR_WRITE_CLEAR_DEFAULT 0x00000000
-
-/***************************************************************************
- *CLIENT_INIT_ERROR_INFO - "Client init error violation info"
- ***************************************************************************/
-/* MEMC_ARB_1 :: CLIENT_INIT_ERROR_INFO :: reserved0 [31:24] */
-#define BCHP_MEMC_ARB_1_CLIENT_INIT_ERROR_INFO_reserved0_MASK 0xff000000
-#define BCHP_MEMC_ARB_1_CLIENT_INIT_ERROR_INFO_reserved0_SHIFT 24
-
-/* MEMC_ARB_1 :: CLIENT_INIT_ERROR_INFO :: reserved_for_padding1 [23:08] */
-#define BCHP_MEMC_ARB_1_CLIENT_INIT_ERROR_INFO_reserved_for_padding1_MASK 0x00ffff00
-#define BCHP_MEMC_ARB_1_CLIENT_INIT_ERROR_INFO_reserved_for_padding1_SHIFT 8
-
-/* MEMC_ARB_1 :: CLIENT_INIT_ERROR_INFO :: CLIENT_ID [07:00] */
-#define BCHP_MEMC_ARB_1_CLIENT_INIT_ERROR_INFO_CLIENT_ID_MASK 0x000000ff
-#define BCHP_MEMC_ARB_1_CLIENT_INIT_ERROR_INFO_CLIENT_ID_SHIFT 0
-#define BCHP_MEMC_ARB_1_CLIENT_INIT_ERROR_INFO_CLIENT_ID_DEFAULT 0x00000000
-
-/***************************************************************************
- *CLIENT_INIT_SW_INIT - "Client init software init"
- ***************************************************************************/
-/* MEMC_ARB_1 :: CLIENT_INIT_SW_INIT :: reserved0 [31:09] */
-#define BCHP_MEMC_ARB_1_CLIENT_INIT_SW_INIT_reserved0_MASK 0xfffffe00
-#define BCHP_MEMC_ARB_1_CLIENT_INIT_SW_INIT_reserved0_SHIFT 9
-
-/* MEMC_ARB_1 :: CLIENT_INIT_SW_INIT :: CLIENT_INIT_REQ [08:08] */
-#define BCHP_MEMC_ARB_1_CLIENT_INIT_SW_INIT_CLIENT_INIT_REQ_MASK 0x00000100
-#define BCHP_MEMC_ARB_1_CLIENT_INIT_SW_INIT_CLIENT_INIT_REQ_SHIFT 8
-#define BCHP_MEMC_ARB_1_CLIENT_INIT_SW_INIT_CLIENT_INIT_REQ_DEFAULT 0x00000000
-
-/* MEMC_ARB_1 :: CLIENT_INIT_SW_INIT :: CLIENT_INIT_ID [07:00] */
-#define BCHP_MEMC_ARB_1_CLIENT_INIT_SW_INIT_CLIENT_INIT_ID_MASK 0x000000ff
-#define BCHP_MEMC_ARB_1_CLIENT_INIT_SW_INIT_CLIENT_INIT_ID_SHIFT 0
-#define BCHP_MEMC_ARB_1_CLIENT_INIT_SW_INIT_CLIENT_INIT_ID_DEFAULT 0x00000000
-
-/***************************************************************************
- *CLIENT_INIT_STATUS - "Client init status and debug register"
- ***************************************************************************/
-/* MEMC_ARB_1 :: CLIENT_INIT_STATUS :: CLIENT_ISOLATION [31:31] */
-#define BCHP_MEMC_ARB_1_CLIENT_INIT_STATUS_CLIENT_ISOLATION_MASK 0x80000000
-#define BCHP_MEMC_ARB_1_CLIENT_INIT_STATUS_CLIENT_ISOLATION_SHIFT 31
-
-/* MEMC_ARB_1 :: CLIENT_INIT_STATUS :: reserved0 [30:20] */
-#define BCHP_MEMC_ARB_1_CLIENT_INIT_STATUS_reserved0_MASK 0x7ff00000
-#define BCHP_MEMC_ARB_1_CLIENT_INIT_STATUS_reserved0_SHIFT 20
-
-/* MEMC_ARB_1 :: CLIENT_INIT_STATUS :: COUNTER_VALUE [19:08] */
-#define BCHP_MEMC_ARB_1_CLIENT_INIT_STATUS_COUNTER_VALUE_MASK 0x000fff00
-#define BCHP_MEMC_ARB_1_CLIENT_INIT_STATUS_COUNTER_VALUE_SHIFT 8
-
-/* MEMC_ARB_1 :: CLIENT_INIT_STATUS :: reserved1 [07:06] */
-#define BCHP_MEMC_ARB_1_CLIENT_INIT_STATUS_reserved1_MASK 0x000000c0
-#define BCHP_MEMC_ARB_1_CLIENT_INIT_STATUS_reserved1_SHIFT 6
-
-/* MEMC_ARB_1 :: CLIENT_INIT_STATUS :: CLIENT_INIT_STATE [05:04] */
-#define BCHP_MEMC_ARB_1_CLIENT_INIT_STATUS_CLIENT_INIT_STATE_MASK 0x00000030
-#define BCHP_MEMC_ARB_1_CLIENT_INIT_STATUS_CLIENT_INIT_STATE_SHIFT 4
-
-/* MEMC_ARB_1 :: CLIENT_INIT_STATUS :: reserved2 [03:01] */
-#define BCHP_MEMC_ARB_1_CLIENT_INIT_STATUS_reserved2_MASK 0x0000000e
-#define BCHP_MEMC_ARB_1_CLIENT_INIT_STATUS_reserved2_SHIFT 1
-
-/* MEMC_ARB_1 :: CLIENT_INIT_STATUS :: CLIENT_INIT_ACK [00:00] */
-#define BCHP_MEMC_ARB_1_CLIENT_INIT_STATUS_CLIENT_INIT_ACK_MASK 0x00000001
-#define BCHP_MEMC_ARB_1_CLIENT_INIT_STATUS_CLIENT_INIT_ACK_SHIFT 0
-#define BCHP_MEMC_ARB_1_CLIENT_INIT_STATUS_CLIENT_INIT_ACK_DEFAULT 0x00000000
-
-/***************************************************************************
- *LCA_VALID_REQ_0 - LCA Valid Requests for Clients 0 to 31
- ***************************************************************************/
-/* MEMC_ARB_1 :: LCA_VALID_REQ_0 :: LCA_VALID_REQS [31:00] */
-#define BCHP_MEMC_ARB_1_LCA_VALID_REQ_0_LCA_VALID_REQS_MASK 0xffffffff
-#define BCHP_MEMC_ARB_1_LCA_VALID_REQ_0_LCA_VALID_REQS_SHIFT 0
-#define BCHP_MEMC_ARB_1_LCA_VALID_REQ_0_LCA_VALID_REQS_DEFAULT 0x00000000
-
-/***************************************************************************
- *LCA_VALID_REQ_1 - LCA Valid Requests for Clients 32 to 63
- ***************************************************************************/
-/* MEMC_ARB_1 :: LCA_VALID_REQ_1 :: LCA_VALID_REQS [31:00] */
-#define BCHP_MEMC_ARB_1_LCA_VALID_REQ_1_LCA_VALID_REQS_MASK 0xffffffff
-#define BCHP_MEMC_ARB_1_LCA_VALID_REQ_1_LCA_VALID_REQS_SHIFT 0
-#define BCHP_MEMC_ARB_1_LCA_VALID_REQ_1_LCA_VALID_REQS_DEFAULT 0x00000000
-
-/***************************************************************************
- *LCA_VALID_REQ_2 - LCA Valid Requests for Clients64 to 95
- ***************************************************************************/
-/* MEMC_ARB_1 :: LCA_VALID_REQ_2 :: LCA_VALID_REQS [31:00] */
-#define BCHP_MEMC_ARB_1_LCA_VALID_REQ_2_LCA_VALID_REQS_MASK 0xffffffff
-#define BCHP_MEMC_ARB_1_LCA_VALID_REQ_2_LCA_VALID_REQS_SHIFT 0
-#define BCHP_MEMC_ARB_1_LCA_VALID_REQ_2_LCA_VALID_REQS_DEFAULT 0x00000000
-
-/***************************************************************************
- *LCA_VALID_REQ_3 - LCA Valid Requests for Clients 96 to 127
- ***************************************************************************/
-/* MEMC_ARB_1 :: LCA_VALID_REQ_3 :: LCA_VALID_REQS [31:00] */
-#define BCHP_MEMC_ARB_1_LCA_VALID_REQ_3_LCA_VALID_REQS_MASK 0xffffffff
-#define BCHP_MEMC_ARB_1_LCA_VALID_REQ_3_LCA_VALID_REQS_SHIFT 0
-#define BCHP_MEMC_ARB_1_LCA_VALID_REQ_3_LCA_VALID_REQS_DEFAULT 0x00000000
-
-/***************************************************************************
- *LCA_VALID_REQ_4 - LCA Valid Requests for Clients 128 to 159
- ***************************************************************************/
-/* MEMC_ARB_1 :: LCA_VALID_REQ_4 :: LCA_VALID_REQS [31:00] */
-#define BCHP_MEMC_ARB_1_LCA_VALID_REQ_4_LCA_VALID_REQS_MASK 0xffffffff
-#define BCHP_MEMC_ARB_1_LCA_VALID_REQ_4_LCA_VALID_REQS_SHIFT 0
-#define BCHP_MEMC_ARB_1_LCA_VALID_REQ_4_LCA_VALID_REQS_DEFAULT 0x00000000
-
-/***************************************************************************
- *LCA_VALID_REQ_5 - LCA Valid Requests for Clients 160 to 191
- ***************************************************************************/
-/* MEMC_ARB_1 :: LCA_VALID_REQ_5 :: LCA_VALID_REQS [31:00] */
-#define BCHP_MEMC_ARB_1_LCA_VALID_REQ_5_LCA_VALID_REQS_MASK 0xffffffff
-#define BCHP_MEMC_ARB_1_LCA_VALID_REQ_5_LCA_VALID_REQS_SHIFT 0
-#define BCHP_MEMC_ARB_1_LCA_VALID_REQ_5_LCA_VALID_REQS_DEFAULT 0x00000000
-
-/***************************************************************************
- *LCA_VALID_REQ_6 - LCA Valid Requests for Clients 192 to 223
- ***************************************************************************/
-/* MEMC_ARB_1 :: LCA_VALID_REQ_6 :: LCA_VALID_REQS [31:00] */
-#define BCHP_MEMC_ARB_1_LCA_VALID_REQ_6_LCA_VALID_REQS_MASK 0xffffffff
-#define BCHP_MEMC_ARB_1_LCA_VALID_REQ_6_LCA_VALID_REQS_SHIFT 0
-#define BCHP_MEMC_ARB_1_LCA_VALID_REQ_6_LCA_VALID_REQS_DEFAULT 0x00000000
-
-/***************************************************************************
- *LCA_VALID_REQ_7 - LCA Valid Requests for Clients 224 to 255
- ***************************************************************************/
-/* MEMC_ARB_1 :: LCA_VALID_REQ_7 :: LCA_VALID_REQS [31:00] */
-#define BCHP_MEMC_ARB_1_LCA_VALID_REQ_7_LCA_VALID_REQS_MASK 0xffffffff
-#define BCHP_MEMC_ARB_1_LCA_VALID_REQ_7_LCA_VALID_REQS_SHIFT 0
-#define BCHP_MEMC_ARB_1_LCA_VALID_REQ_7_LCA_VALID_REQS_DEFAULT 0x00000000
-
-#endif /* #ifndef BCHP_MEMC_ARB_1_H__ */
-
-/* End of File */
diff --git a/include/linux/brcmstb/7145a0/bchp_memc_ddr_0.h b/include/linux/brcmstb/7145a0/bchp_memc_ddr_0.h
deleted file mode 100644
index 95bc4cb..0000000
--- a/include/linux/brcmstb/7145a0/bchp_memc_ddr_0.h
+++ /dev/null
@@ -1,4679 +0,0 @@
-/***************************************************************************
- * Copyright (c) 1999-2013, Broadcom Corporation
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
- *
- * Module Description:
- * DO NOT EDIT THIS FILE DIRECTLY
- *
- * This module was generated magically with RDB from a source description
- * file. You must edit the source file for changes to be made to this file.
- *
- *
- * Date: Generated on Sat Apr 6 03:07:45 2013
- * MD5 Checksum d41d8cd98f00b204e9800998ecf8427e
- *
- * Compiled with: RDB Utility combo_header.pl
- * RDB Parser 3.0
- * unknown unknown
- * Perl Interpreter 5.008008
- * Operating System linux
- *
- * Revision History:
- *
- * $brcm_Log: $
- *
- ***************************************************************************/
-
-#ifndef BCHP_MEMC_DDR_0_H__
-#define BCHP_MEMC_DDR_0_H__
-
-/***************************************************************************
- *MEMC_DDR_0 - 0 Sequencer DRAM Param and Control Registers
- ***************************************************************************/
-#define BCHP_MEMC_DDR_0_CNTRLR_CONFIG 0x203b2000 /* Memory Controller Configuration Register */
-#define BCHP_MEMC_DDR_0_DRAM_INIT_CNTRL 0x203b2004 /* Dram initialization control */
-#define BCHP_MEMC_DDR_0_DRAM_INIT_STATUS 0x203b2008 /* Dram initialization status */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_0 0x203b200c /* Dram Mode Register 0 */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_1 0x203b2010 /* Dram Mode Register 1 */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_2 0x203b2014 /* Dram Mode Register 2 */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_3 0x203b2018 /* Dram Mode Register 3 */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_4 0x203b201c /* Dram Mode Register 4 */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_5 0x203b2020 /* Dram Mode Register 5 */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_6 0x203b2024 /* Dram Mode Register 6 */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_7 0x203b2028 /* Dram Mode Register 7 */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_8 0x203b202c /* Dram Mode Register 8 */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_15 0x203b2030 /* Dram Mode Register 15 */
-#define BCHP_MEMC_DDR_0_PPD_CONFIG 0x203b2034 /* Precharge power down mode configuration register */
-#define BCHP_MEMC_DDR_0_SRPD_CONFIG 0x203b2038 /* Self-refresh power down mode configuration register */
-#define BCHP_MEMC_DDR_0_SSPD_CMD 0x203b203c /* Software standby power down mode */
-#define BCHP_MEMC_DDR_0_POWER_DOWN_STATUS 0x203b2040 /* Power down status */
-#define BCHP_MEMC_DDR_0_WARM_BOOT 0x203b2044 /* Warm boot control registers */
-#define BCHP_MEMC_DDR_0_DRAM_TIMING_0 0x203b2048 /* DDR-SDRAM Timing Register 0 */
-#define BCHP_MEMC_DDR_0_DRAM_TIMING_1 0x203b204c /* DDR-SDRAM Timing Register 1 */
-#define BCHP_MEMC_DDR_0_DRAM_TIMING_2 0x203b2050 /* Read to Write & write to read timing register */
-#define BCHP_MEMC_DDR_0_DRAM_TIMING_3 0x203b2054 /* DDR-SDRAM Timing Register 3 */
-#define BCHP_MEMC_DDR_0_DRAM_TIMING_4 0x203b2058 /* DDR-SDRAM Timing Register 4 */
-#define BCHP_MEMC_DDR_0_DRAM_TIMING_5 0x203b205c /* DDR-SDRAM Timing Register 5 */
-#define BCHP_MEMC_DDR_0_MIN_DQ_IDLE_CONTROL 0x203b2060 /* Minimum DQ Idle Time Control */
-#define BCHP_MEMC_DDR_0_PHY_OP_ACCESS_PENALTY 0x203b2064 /* PHY Operational Access Penalty Count. */
-#define BCHP_MEMC_DDR_0_CNTRLR_SM_TIMEOUT 0x203b2068 /* Memory Controller , state machine timeout register. */
-#define BCHP_MEMC_DDR_0_BANK_STATUS 0x203b206c /* Memory Controller, Bank Status Register */
-#define BCHP_MEMC_DDR_0_TESTER_LATENCY 0x203b2070 /* Memory Controller, Tester Latency Register. */
-#define BCHP_MEMC_DDR_0_SEQ_RING_BUF_DEPTH 0x203b2074 /* Sequencer Ring Buffer programmable depth. */
-#define BCHP_MEMC_DDR_0_SEQ_WRDATA_ERR_INFO 0x203b2078 /* Sequencer write data error info */
-#define BCHP_MEMC_DDR_0_SEQ_WRDATA_TRANSID_MISMATCH_INFO 0x203b207c /* Sequencer transaction ID mismatch error info */
-#define BCHP_MEMC_DDR_0_SEQ_CLEAR_VIOLATIONS 0x203b2080 /* Sequencer Violation Info register clear. */
-#define BCHP_MEMC_DDR_0_STAT_CONTROL 0x203b2084 /* Statistics Control register */
-#define BCHP_MEMC_DDR_0_STAT_TIMER 0x203b2088 /* Statistics Timer */
-#define BCHP_MEMC_DDR_0_STAT_IDLE_NOP 0x203b208c /* DRAM Idle_NOP Cycle Count Register. */
-#define BCHP_MEMC_DDR_0_STAT_MAX_IDLE_NOP 0x203b2090 /* Maximum DRAM idle_NOP cycle count register. */
-#define BCHP_MEMC_DDR_0_STAT_MIN_IDLE_NOP 0x203b2094 /* Minimum DRAM idle_NOP cycle count register. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_ALL 0x203b2098 /* CAS Count Register. */
-#define BCHP_MEMC_DDR_0_STAT_MAX_CAS_ALL 0x203b209c /* Maximum DRAM CAS cycle count register. */
-#define BCHP_MEMC_DDR_0_STAT_MIN_CAS_ALL 0x203b20a0 /* Minimum DRAM CAS cycle count register. */
-#define BCHP_MEMC_DDR_0_STAT_PENALTY_ALL 0x203b20a4 /* DRAM Penalty Cycle Count register. */
-#define BCHP_MEMC_DDR_0_STAT_PENALTY_GDDRWM 0x203b20a8 /* GDDR Write Mask Penalty Cycle Count register. */
-#define BCHP_MEMC_DDR_0_STAT_MAX_TRANS_CYCLES_ALL 0x203b20ac /* Maximum number of transactions cycles (CAS+Penalty_ALL). */
-#define BCHP_MEMC_DDR_0_STAT_MIN_TRANS_CYCLES_ALL 0x203b20b0 /* Minimum number of transactions cycles (CAS+Penalty_ALL). */
-#define BCHP_MEMC_DDR_0_STAT_TRANS_READ_ALL 0x203b20b4 /* Number of overall system memory read transactions. */
-#define BCHP_MEMC_DDR_0_STAT_TRANS_WRITE_ALL 0x203b20b8 /* Number of overall system memory write transactions. */
-#define BCHP_MEMC_DDR_0_STAT_MAX_TRANS_ALL 0x203b20bc /* Maximum Number of Overall System memory transactions. */
-#define BCHP_MEMC_DDR_0_STAT_MIN_TRANS_ALL 0x203b20c0 /* Minimum Number of Overall System memory transactions. */
-#define BCHP_MEMC_DDR_0_STAT_CLIENT_SERVICE_CAS 0x203b20c4 /* Service CAS Cycle Count register. */
-#define BCHP_MEMC_DDR_0_STAT_MAX_CLIENT_SERVICE_CAS 0x203b20c8 /* Maximum service CAS cycle count register. */
-#define BCHP_MEMC_DDR_0_STAT_MIN_CLIENT_SERVICE_CAS 0x203b20cc /* Minimum service CAS cycle count register. */
-#define BCHP_MEMC_DDR_0_STAT_CLIENT_SERVICE_INTR_PENALTY 0x203b20d0 /* Service Intra DRAM Penalty Cycle Count register. */
-#define BCHP_MEMC_DDR_0_STAT_CLIENT_SERVICE_POST_PENALTY 0x203b20d4 /* Service Post DRAM Penalty Cycle Count register. */
-#define BCHP_MEMC_DDR_0_STAT_CLIENT_SERVICE_GDDRWM_PENALTY 0x203b20d8 /* Service GDDR Write Mask Penalty Cycle Count register. */
-#define BCHP_MEMC_DDR_0_STAT_MAX_CLIENT_SERVICE_CYCLES 0x203b20dc /* Maximum service cycle count register. */
-#define BCHP_MEMC_DDR_0_STAT_MIN_CLIENT_SERVICE_CYCLES 0x203b20e0 /* Minimum service cycle count register. */
-#define BCHP_MEMC_DDR_0_STAT_CLIENT_SERVICE_TRANS_READ 0x203b20e4 /* Service Read Transaction Count register. */
-#define BCHP_MEMC_DDR_0_STAT_CLIENT_SERVICE_TRANS_WRITE 0x203b20e8 /* Service Write Transaction Count register. */
-#define BCHP_MEMC_DDR_0_STAT_MAX_CLIENT_SERVICE_TRANS 0x203b20ec /* Maximum service Transaction count register. */
-#define BCHP_MEMC_DDR_0_STAT_MIN_CLIENT_SERVICE_TRANS 0x203b20f0 /* Minimum service cycle Transaction register. */
-#define BCHP_MEMC_DDR_0_STAT_CLIENT_SERVICE_LATENCY 0x203b20f4 /* Service Latency Count register. */
-#define BCHP_MEMC_DDR_0_STAT_MAX_CLIENT_SERVICE_LATENCY 0x203b20f8 /* Maximum Service Latency count register. */
-#define BCHP_MEMC_DDR_0_STAT_MIN_CLIENT_SERVICE_LATENCY 0x203b20fc /* Minimum Service Latency count register. */
-#define BCHP_MEMC_DDR_0_STAT_CLIENT_ABS_MAX_SERVICE_LATENCY 0x203b2100 /* Absolute Minimum Service Latency count register. */
-#define BCHP_MEMC_DDR_0_STAT_CLIENT_ABS_MIN_SERVICE_LATENCY 0x203b2104 /* Absolute Maximum Service Latency count register. */
-#define BCHP_MEMC_DDR_0_STAT_REFRESH 0x203b2108 /* Total number of refreshes issued. */
-#define BCHP_MEMC_DDR_0_STAT_MIN_DQ_IDLE_WRITE 0x203b210c /* Min DQ Idle Write event counter */
-#define BCHP_MEMC_DDR_0_STAT_MIN_DQ_IDLE_READ 0x203b2110 /* Min DQ Idle Read event counter */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_0 0x203b2400 /* CAS or consumption cycle count register for client 0. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_1 0x203b2404 /* CAS or consumption cycle count register for client 1. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_2 0x203b2408 /* CAS or consumption cycle count register for client 2. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_3 0x203b240c /* CAS or consumption cycle count register for client 3. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_4 0x203b2410 /* CAS or consumption cycle count register for client 4. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_5 0x203b2414 /* CAS or consumption cycle count register for client 5. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_6 0x203b2418 /* CAS or consumption cycle count register for client 6. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_7 0x203b241c /* CAS or consumption cycle count register for client 7. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_8 0x203b2420 /* CAS or consumption cycle count register for client 8. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_9 0x203b2424 /* CAS or consumption cycle count register for client 9. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_10 0x203b2428 /* CAS or consumption cycle count register for client 10. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_11 0x203b242c /* CAS or consumption cycle count register for client 11. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_12 0x203b2430 /* CAS or consumption cycle count register for client 12. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_13 0x203b2434 /* CAS or consumption cycle count register for client 13. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_14 0x203b2438 /* CAS or consumption cycle count register for client 14. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_15 0x203b243c /* CAS or consumption cycle count register for client 15. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_16 0x203b2440 /* CAS or consumption cycle count register for client 16. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_17 0x203b2444 /* CAS or consumption cycle count register for client 17. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_18 0x203b2448 /* CAS or consumption cycle count register for client 18. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_19 0x203b244c /* CAS or consumption cycle count register for client 19. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_20 0x203b2450 /* CAS or consumption cycle count register for client 20. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_21 0x203b2454 /* CAS or consumption cycle count register for client 21. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_22 0x203b2458 /* CAS or consumption cycle count register for client 22. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_23 0x203b245c /* CAS or consumption cycle count register for client 23. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_24 0x203b2460 /* CAS or consumption cycle count register for client 24. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_25 0x203b2464 /* CAS or consumption cycle count register for client 25. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_26 0x203b2468 /* CAS or consumption cycle count register for client 26. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_27 0x203b246c /* CAS or consumption cycle count register for client 27. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_28 0x203b2470 /* CAS or consumption cycle count register for client 28. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_29 0x203b2474 /* CAS or consumption cycle count register for client 29. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_30 0x203b2478 /* CAS or consumption cycle count register for client 30. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_31 0x203b247c /* CAS or consumption cycle count register for client 31. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_32 0x203b2480 /* CAS or consumption cycle count register for client 32. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_33 0x203b2484 /* CAS or consumption cycle count register for client 33. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_34 0x203b2488 /* CAS or consumption cycle count register for client 34. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_35 0x203b248c /* CAS or consumption cycle count register for client 35. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_36 0x203b2490 /* CAS or consumption cycle count register for client 36. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_37 0x203b2494 /* CAS or consumption cycle count register for client 37. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_38 0x203b2498 /* CAS or consumption cycle count register for client 38. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_39 0x203b249c /* CAS or consumption cycle count register for client 39. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_40 0x203b24a0 /* CAS or consumption cycle count register for client 40. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_41 0x203b24a4 /* CAS or consumption cycle count register for client 41. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_42 0x203b24a8 /* CAS or consumption cycle count register for client 42. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_43 0x203b24ac /* CAS or consumption cycle count register for client 43. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_44 0x203b24b0 /* CAS or consumption cycle count register for client 44. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_45 0x203b24b4 /* CAS or consumption cycle count register for client 45. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_46 0x203b24b8 /* CAS or consumption cycle count register for client 46. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_47 0x203b24bc /* CAS or consumption cycle count register for client 47. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_48 0x203b24c0 /* CAS or consumption cycle count register for client 48. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_49 0x203b24c4 /* CAS or consumption cycle count register for client 49. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_50 0x203b24c8 /* CAS or consumption cycle count register for client 50. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_51 0x203b24cc /* CAS or consumption cycle count register for client 51. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_52 0x203b24d0 /* CAS or consumption cycle count register for client 52. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_53 0x203b24d4 /* CAS or consumption cycle count register for client 53. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_54 0x203b24d8 /* CAS or consumption cycle count register for client 54. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_55 0x203b24dc /* CAS or consumption cycle count register for client 55. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_56 0x203b24e0 /* CAS or consumption cycle count register for client 56. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_57 0x203b24e4 /* CAS or consumption cycle count register for client 57. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_58 0x203b24e8 /* CAS or consumption cycle count register for client 58. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_59 0x203b24ec /* CAS or consumption cycle count register for client 59. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_60 0x203b24f0 /* CAS or consumption cycle count register for client 60. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_61 0x203b24f4 /* CAS or consumption cycle count register for client 61. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_62 0x203b24f8 /* CAS or consumption cycle count register for client 62. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_63 0x203b24fc /* CAS or consumption cycle count register for client 63. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_64 0x203b2500 /* CAS or consumption cycle count register for client 64. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_65 0x203b2504 /* CAS or consumption cycle count register for client 65. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_66 0x203b2508 /* CAS or consumption cycle count register for client 66. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_67 0x203b250c /* CAS or consumption cycle count register for client 67. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_68 0x203b2510 /* CAS or consumption cycle count register for client 68. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_69 0x203b2514 /* CAS or consumption cycle count register for client 69. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_70 0x203b2518 /* CAS or consumption cycle count register for client 70. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_71 0x203b251c /* CAS or consumption cycle count register for client 71. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_72 0x203b2520 /* CAS or consumption cycle count register for client 72. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_73 0x203b2524 /* CAS or consumption cycle count register for client 73. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_74 0x203b2528 /* CAS or consumption cycle count register for client 74. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_75 0x203b252c /* CAS or consumption cycle count register for client 75. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_76 0x203b2530 /* CAS or consumption cycle count register for client 76. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_77 0x203b2534 /* CAS or consumption cycle count register for client 77. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_78 0x203b2538 /* CAS or consumption cycle count register for client 78. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_79 0x203b253c /* CAS or consumption cycle count register for client 79. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_80 0x203b2540 /* CAS or consumption cycle count register for client 80. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_81 0x203b2544 /* CAS or consumption cycle count register for client 81. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_82 0x203b2548 /* CAS or consumption cycle count register for client 82. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_83 0x203b254c /* CAS or consumption cycle count register for client 83. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_84 0x203b2550 /* CAS or consumption cycle count register for client 84. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_85 0x203b2554 /* CAS or consumption cycle count register for client 85. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_86 0x203b2558 /* CAS or consumption cycle count register for client 86. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_87 0x203b255c /* CAS or consumption cycle count register for client 87. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_88 0x203b2560 /* CAS or consumption cycle count register for client 88. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_89 0x203b2564 /* CAS or consumption cycle count register for client 89. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_90 0x203b2568 /* CAS or consumption cycle count register for client 90. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_91 0x203b256c /* CAS or consumption cycle count register for client 91. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_92 0x203b2570 /* CAS or consumption cycle count register for client 92. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_93 0x203b2574 /* CAS or consumption cycle count register for client 93. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_94 0x203b2578 /* CAS or consumption cycle count register for client 94. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_95 0x203b257c /* CAS or consumption cycle count register for client 95. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_96 0x203b2580 /* CAS or consumption cycle count register for client 96. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_97 0x203b2584 /* CAS or consumption cycle count register for client 97. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_98 0x203b2588 /* CAS or consumption cycle count register for client 98. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_99 0x203b258c /* CAS or consumption cycle count register for client 99. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_100 0x203b2590 /* CAS or consumption cycle count register for client 100. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_101 0x203b2594 /* CAS or consumption cycle count register for client 101. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_102 0x203b2598 /* CAS or consumption cycle count register for client 102. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_103 0x203b259c /* CAS or consumption cycle count register for client 103. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_104 0x203b25a0 /* CAS or consumption cycle count register for client 104. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_105 0x203b25a4 /* CAS or consumption cycle count register for client 105. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_106 0x203b25a8 /* CAS or consumption cycle count register for client 106. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_107 0x203b25ac /* CAS or consumption cycle count register for client 107. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_108 0x203b25b0 /* CAS or consumption cycle count register for client 108. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_109 0x203b25b4 /* CAS or consumption cycle count register for client 109. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_110 0x203b25b8 /* CAS or consumption cycle count register for client 110. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_111 0x203b25bc /* CAS or consumption cycle count register for client 111. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_112 0x203b25c0 /* CAS or consumption cycle count register for client 112. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_113 0x203b25c4 /* CAS or consumption cycle count register for client 113. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_114 0x203b25c8 /* CAS or consumption cycle count register for client 114. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_115 0x203b25cc /* CAS or consumption cycle count register for client 115. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_116 0x203b25d0 /* CAS or consumption cycle count register for client 116. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_117 0x203b25d4 /* CAS or consumption cycle count register for client 117. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_118 0x203b25d8 /* CAS or consumption cycle count register for client 118. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_119 0x203b25dc /* CAS or consumption cycle count register for client 119. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_120 0x203b25e0 /* CAS or consumption cycle count register for client 120. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_121 0x203b25e4 /* CAS or consumption cycle count register for client 121. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_122 0x203b25e8 /* CAS or consumption cycle count register for client 122. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_123 0x203b25ec /* CAS or consumption cycle count register for client 123. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_124 0x203b25f0 /* CAS or consumption cycle count register for client 124. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_125 0x203b25f4 /* CAS or consumption cycle count register for client 125. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_126 0x203b25f8 /* CAS or consumption cycle count register for client 126. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_127 0x203b25fc /* CAS or consumption cycle count register for client 127. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_128 0x203b2600 /* CAS or consumption cycle count register for client 128. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_129 0x203b2604 /* CAS or consumption cycle count register for client 129. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_130 0x203b2608 /* CAS or consumption cycle count register for client 130. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_131 0x203b260c /* CAS or consumption cycle count register for client 131. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_132 0x203b2610 /* CAS or consumption cycle count register for client 132. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_133 0x203b2614 /* CAS or consumption cycle count register for client 133. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_134 0x203b2618 /* CAS or consumption cycle count register for client 134. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_135 0x203b261c /* CAS or consumption cycle count register for client 135. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_136 0x203b2620 /* CAS or consumption cycle count register for client 136. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_137 0x203b2624 /* CAS or consumption cycle count register for client 137. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_138 0x203b2628 /* CAS or consumption cycle count register for client 138. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_139 0x203b262c /* CAS or consumption cycle count register for client 139. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_140 0x203b2630 /* CAS or consumption cycle count register for client 140. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_141 0x203b2634 /* CAS or consumption cycle count register for client 141. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_142 0x203b2638 /* CAS or consumption cycle count register for client 142. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_143 0x203b263c /* CAS or consumption cycle count register for client 143. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_144 0x203b2640 /* CAS or consumption cycle count register for client 144. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_145 0x203b2644 /* CAS or consumption cycle count register for client 145. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_146 0x203b2648 /* CAS or consumption cycle count register for client 146. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_147 0x203b264c /* CAS or consumption cycle count register for client 147. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_148 0x203b2650 /* CAS or consumption cycle count register for client 148. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_149 0x203b2654 /* CAS or consumption cycle count register for client 149. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_150 0x203b2658 /* CAS or consumption cycle count register for client 150. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_151 0x203b265c /* CAS or consumption cycle count register for client 151. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_152 0x203b2660 /* CAS or consumption cycle count register for client 152. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_153 0x203b2664 /* CAS or consumption cycle count register for client 153. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_154 0x203b2668 /* CAS or consumption cycle count register for client 154. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_155 0x203b266c /* CAS or consumption cycle count register for client 155. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_156 0x203b2670 /* CAS or consumption cycle count register for client 156. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_157 0x203b2674 /* CAS or consumption cycle count register for client 157. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_158 0x203b2678 /* CAS or consumption cycle count register for client 158. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_159 0x203b267c /* CAS or consumption cycle count register for client 159. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_160 0x203b2680 /* CAS or consumption cycle count register for client 160. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_161 0x203b2684 /* CAS or consumption cycle count register for client 161. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_162 0x203b2688 /* CAS or consumption cycle count register for client 162. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_163 0x203b268c /* CAS or consumption cycle count register for client 163. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_164 0x203b2690 /* CAS or consumption cycle count register for client 164. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_165 0x203b2694 /* CAS or consumption cycle count register for client 165. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_166 0x203b2698 /* CAS or consumption cycle count register for client 166. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_167 0x203b269c /* CAS or consumption cycle count register for client 167. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_168 0x203b26a0 /* CAS or consumption cycle count register for client 168. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_169 0x203b26a4 /* CAS or consumption cycle count register for client 169. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_170 0x203b26a8 /* CAS or consumption cycle count register for client 170. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_171 0x203b26ac /* CAS or consumption cycle count register for client 171. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_172 0x203b26b0 /* CAS or consumption cycle count register for client 172. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_173 0x203b26b4 /* CAS or consumption cycle count register for client 173. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_174 0x203b26b8 /* CAS or consumption cycle count register for client 174. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_175 0x203b26bc /* CAS or consumption cycle count register for client 175. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_176 0x203b26c0 /* CAS or consumption cycle count register for client 176. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_177 0x203b26c4 /* CAS or consumption cycle count register for client 177. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_178 0x203b26c8 /* CAS or consumption cycle count register for client 178. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_179 0x203b26cc /* CAS or consumption cycle count register for client 179. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_180 0x203b26d0 /* CAS or consumption cycle count register for client 180. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_181 0x203b26d4 /* CAS or consumption cycle count register for client 181. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_182 0x203b26d8 /* CAS or consumption cycle count register for client 182. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_183 0x203b26dc /* CAS or consumption cycle count register for client 183. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_184 0x203b26e0 /* CAS or consumption cycle count register for client 184. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_185 0x203b26e4 /* CAS or consumption cycle count register for client 185. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_186 0x203b26e8 /* CAS or consumption cycle count register for client 186. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_187 0x203b26ec /* CAS or consumption cycle count register for client 187. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_188 0x203b26f0 /* CAS or consumption cycle count register for client 188. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_189 0x203b26f4 /* CAS or consumption cycle count register for client 189. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_190 0x203b26f8 /* CAS or consumption cycle count register for client 190. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_191 0x203b26fc /* CAS or consumption cycle count register for client 191. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_192 0x203b2700 /* CAS or consumption cycle count register for client 192. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_193 0x203b2704 /* CAS or consumption cycle count register for client 193. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_194 0x203b2708 /* CAS or consumption cycle count register for client 194. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_195 0x203b270c /* CAS or consumption cycle count register for client 195. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_196 0x203b2710 /* CAS or consumption cycle count register for client 196. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_197 0x203b2714 /* CAS or consumption cycle count register for client 197. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_198 0x203b2718 /* CAS or consumption cycle count register for client 198. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_199 0x203b271c /* CAS or consumption cycle count register for client 199. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_200 0x203b2720 /* CAS or consumption cycle count register for client 200. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_201 0x203b2724 /* CAS or consumption cycle count register for client 201. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_202 0x203b2728 /* CAS or consumption cycle count register for client 202. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_203 0x203b272c /* CAS or consumption cycle count register for client 203. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_204 0x203b2730 /* CAS or consumption cycle count register for client 204. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_205 0x203b2734 /* CAS or consumption cycle count register for client 205. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_206 0x203b2738 /* CAS or consumption cycle count register for client 206. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_207 0x203b273c /* CAS or consumption cycle count register for client 207. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_208 0x203b2740 /* CAS or consumption cycle count register for client 208. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_209 0x203b2744 /* CAS or consumption cycle count register for client 209. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_210 0x203b2748 /* CAS or consumption cycle count register for client 210. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_211 0x203b274c /* CAS or consumption cycle count register for client 211. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_212 0x203b2750 /* CAS or consumption cycle count register for client 212. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_213 0x203b2754 /* CAS or consumption cycle count register for client 213. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_214 0x203b2758 /* CAS or consumption cycle count register for client 214. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_215 0x203b275c /* CAS or consumption cycle count register for client 215. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_216 0x203b2760 /* CAS or consumption cycle count register for client 216. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_217 0x203b2764 /* CAS or consumption cycle count register for client 217. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_218 0x203b2768 /* CAS or consumption cycle count register for client 218. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_219 0x203b276c /* CAS or consumption cycle count register for client 219. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_220 0x203b2770 /* CAS or consumption cycle count register for client 220. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_221 0x203b2774 /* CAS or consumption cycle count register for client 221. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_222 0x203b2778 /* CAS or consumption cycle count register for client 222. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_223 0x203b277c /* CAS or consumption cycle count register for client 223. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_224 0x203b2780 /* CAS or consumption cycle count register for client 224. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_225 0x203b2784 /* CAS or consumption cycle count register for client 225. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_226 0x203b2788 /* CAS or consumption cycle count register for client 226. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_227 0x203b278c /* CAS or consumption cycle count register for client 227. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_228 0x203b2790 /* CAS or consumption cycle count register for client 228. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_229 0x203b2794 /* CAS or consumption cycle count register for client 229. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_230 0x203b2798 /* CAS or consumption cycle count register for client 230. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_231 0x203b279c /* CAS or consumption cycle count register for client 231. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_232 0x203b27a0 /* CAS or consumption cycle count register for client 232. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_233 0x203b27a4 /* CAS or consumption cycle count register for client 233. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_234 0x203b27a8 /* CAS or consumption cycle count register for client 234. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_235 0x203b27ac /* CAS or consumption cycle count register for client 235. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_236 0x203b27b0 /* CAS or consumption cycle count register for client 236. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_237 0x203b27b4 /* CAS or consumption cycle count register for client 237. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_238 0x203b27b8 /* CAS or consumption cycle count register for client 238. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_239 0x203b27bc /* CAS or consumption cycle count register for client 239. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_240 0x203b27c0 /* CAS or consumption cycle count register for client 240. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_241 0x203b27c4 /* CAS or consumption cycle count register for client 241. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_242 0x203b27c8 /* CAS or consumption cycle count register for client 242. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_243 0x203b27cc /* CAS or consumption cycle count register for client 243. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_244 0x203b27d0 /* CAS or consumption cycle count register for client 244. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_245 0x203b27d4 /* CAS or consumption cycle count register for client 245. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_246 0x203b27d8 /* CAS or consumption cycle count register for client 246. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_247 0x203b27dc /* CAS or consumption cycle count register for client 247. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_248 0x203b27e0 /* CAS or consumption cycle count register for client 248. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_249 0x203b27e4 /* CAS or consumption cycle count register for client 249. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_250 0x203b27e8 /* CAS or consumption cycle count register for client 250. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_251 0x203b27ec /* CAS or consumption cycle count register for client 251. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_252 0x203b27f0 /* CAS or consumption cycle count register for client 252. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_253 0x203b27f4 /* CAS or consumption cycle count register for client 253. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_254 0x203b27f8 /* CAS or consumption cycle count register for client 254. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_255 0x203b27fc /* CAS or consumption cycle count register for client 255. */
-
-/***************************************************************************
- *CNTRLR_CONFIG - Memory Controller Configuration Register
- ***************************************************************************/
-/* MEMC_DDR_0 :: CNTRLR_CONFIG :: reserved0 [31:15] */
-#define BCHP_MEMC_DDR_0_CNTRLR_CONFIG_reserved0_MASK 0xffff8000
-#define BCHP_MEMC_DDR_0_CNTRLR_CONFIG_reserved0_SHIFT 15
-
-/* MEMC_DDR_0 :: CNTRLR_CONFIG :: GROUPAGE_ENABLE [14:14] */
-#define BCHP_MEMC_DDR_0_CNTRLR_CONFIG_GROUPAGE_ENABLE_MASK 0x00004000
-#define BCHP_MEMC_DDR_0_CNTRLR_CONFIG_GROUPAGE_ENABLE_SHIFT 14
-#define BCHP_MEMC_DDR_0_CNTRLR_CONFIG_GROUPAGE_ENABLE_DEFAULT 0x00000000
-
-/* MEMC_DDR_0 :: CNTRLR_CONFIG :: MODIFY_RASTER_ADDR [13:13] */
-#define BCHP_MEMC_DDR_0_CNTRLR_CONFIG_MODIFY_RASTER_ADDR_MASK 0x00002000
-#define BCHP_MEMC_DDR_0_CNTRLR_CONFIG_MODIFY_RASTER_ADDR_SHIFT 13
-#define BCHP_MEMC_DDR_0_CNTRLR_CONFIG_MODIFY_RASTER_ADDR_DEFAULT 0x00000001
-
-/* MEMC_DDR_0 :: CNTRLR_CONFIG :: DRAM_COMMANDS_2T [12:12] */
-#define BCHP_MEMC_DDR_0_CNTRLR_CONFIG_DRAM_COMMANDS_2T_MASK 0x00001000
-#define BCHP_MEMC_DDR_0_CNTRLR_CONFIG_DRAM_COMMANDS_2T_SHIFT 12
-#define BCHP_MEMC_DDR_0_CNTRLR_CONFIG_DRAM_COMMANDS_2T_DEFAULT 0x00000000
-
-/* MEMC_DDR_0 :: CNTRLR_CONFIG :: DRAM_TOTAL_WIDTH [11:10] */
-#define BCHP_MEMC_DDR_0_CNTRLR_CONFIG_DRAM_TOTAL_WIDTH_MASK 0x00000c00
-#define BCHP_MEMC_DDR_0_CNTRLR_CONFIG_DRAM_TOTAL_WIDTH_SHIFT 10
-#define BCHP_MEMC_DDR_0_CNTRLR_CONFIG_DRAM_TOTAL_WIDTH_DEFAULT 0x00000002
-#define BCHP_MEMC_DDR_0_CNTRLR_CONFIG_DRAM_TOTAL_WIDTH_reserved_x8 0
-#define BCHP_MEMC_DDR_0_CNTRLR_CONFIG_DRAM_TOTAL_WIDTH_x16 1
-#define BCHP_MEMC_DDR_0_CNTRLR_CONFIG_DRAM_TOTAL_WIDTH_x32 2
-#define BCHP_MEMC_DDR_0_CNTRLR_CONFIG_DRAM_TOTAL_WIDTH_reserved_x64 3
-
-/* MEMC_DDR_0 :: CNTRLR_CONFIG :: DRAM_DEVICE_WIDTH [09:08] */
-#define BCHP_MEMC_DDR_0_CNTRLR_CONFIG_DRAM_DEVICE_WIDTH_MASK 0x00000300
-#define BCHP_MEMC_DDR_0_CNTRLR_CONFIG_DRAM_DEVICE_WIDTH_SHIFT 8
-#define BCHP_MEMC_DDR_0_CNTRLR_CONFIG_DRAM_DEVICE_WIDTH_DEFAULT 0x00000001
-#define BCHP_MEMC_DDR_0_CNTRLR_CONFIG_DRAM_DEVICE_WIDTH_x8 0
-#define BCHP_MEMC_DDR_0_CNTRLR_CONFIG_DRAM_DEVICE_WIDTH_x16 1
-#define BCHP_MEMC_DDR_0_CNTRLR_CONFIG_DRAM_DEVICE_WIDTH_reserved_2 2
-#define BCHP_MEMC_DDR_0_CNTRLR_CONFIG_DRAM_DEVICE_WIDTH_reserved_3 3
-
-/* MEMC_DDR_0 :: CNTRLR_CONFIG :: DRAM_DEVICE_SIZE [07:04] */
-#define BCHP_MEMC_DDR_0_CNTRLR_CONFIG_DRAM_DEVICE_SIZE_MASK 0x000000f0
-#define BCHP_MEMC_DDR_0_CNTRLR_CONFIG_DRAM_DEVICE_SIZE_SHIFT 4
-#define BCHP_MEMC_DDR_0_CNTRLR_CONFIG_DRAM_DEVICE_SIZE_DEFAULT 0x00000003
-#define BCHP_MEMC_DDR_0_CNTRLR_CONFIG_DRAM_DEVICE_SIZE_reserved_256_Mb 0
-#define BCHP_MEMC_DDR_0_CNTRLR_CONFIG_DRAM_DEVICE_SIZE_512_Mb 1
-#define BCHP_MEMC_DDR_0_CNTRLR_CONFIG_DRAM_DEVICE_SIZE_1_Gb 2
-#define BCHP_MEMC_DDR_0_CNTRLR_CONFIG_DRAM_DEVICE_SIZE_2_Gb 3
-#define BCHP_MEMC_DDR_0_CNTRLR_CONFIG_DRAM_DEVICE_SIZE_4_Gb 4
-#define BCHP_MEMC_DDR_0_CNTRLR_CONFIG_DRAM_DEVICE_SIZE_8_Gb 5
-#define BCHP_MEMC_DDR_0_CNTRLR_CONFIG_DRAM_DEVICE_SIZE_16_Gb 6
-#define BCHP_MEMC_DDR_0_CNTRLR_CONFIG_DRAM_DEVICE_SIZE_reserved_7 7
-#define BCHP_MEMC_DDR_0_CNTRLR_CONFIG_DRAM_DEVICE_SIZE_reserved_8 8
-#define BCHP_MEMC_DDR_0_CNTRLR_CONFIG_DRAM_DEVICE_SIZE_reserved_9 9
-#define BCHP_MEMC_DDR_0_CNTRLR_CONFIG_DRAM_DEVICE_SIZE_reserved_10 10
-#define BCHP_MEMC_DDR_0_CNTRLR_CONFIG_DRAM_DEVICE_SIZE_reserved_11 11
-#define BCHP_MEMC_DDR_0_CNTRLR_CONFIG_DRAM_DEVICE_SIZE_reserved_12 12
-#define BCHP_MEMC_DDR_0_CNTRLR_CONFIG_DRAM_DEVICE_SIZE_reserved_13 13
-#define BCHP_MEMC_DDR_0_CNTRLR_CONFIG_DRAM_DEVICE_SIZE_reserved_14 14
-#define BCHP_MEMC_DDR_0_CNTRLR_CONFIG_DRAM_DEVICE_SIZE_reserved_15 15
-
-/* MEMC_DDR_0 :: CNTRLR_CONFIG :: DRAM_DEVICE_TYPE [03:00] */
-#define BCHP_MEMC_DDR_0_CNTRLR_CONFIG_DRAM_DEVICE_TYPE_MASK 0x0000000f
-#define BCHP_MEMC_DDR_0_CNTRLR_CONFIG_DRAM_DEVICE_TYPE_SHIFT 0
-#define BCHP_MEMC_DDR_0_CNTRLR_CONFIG_DRAM_DEVICE_TYPE_DEFAULT 0x00000001
-#define BCHP_MEMC_DDR_0_CNTRLR_CONFIG_DRAM_DEVICE_TYPE_reserved_DDR2 0
-#define BCHP_MEMC_DDR_0_CNTRLR_CONFIG_DRAM_DEVICE_TYPE_DDR3 1
-#define BCHP_MEMC_DDR_0_CNTRLR_CONFIG_DRAM_DEVICE_TYPE_DDR4 2
-#define BCHP_MEMC_DDR_0_CNTRLR_CONFIG_DRAM_DEVICE_TYPE_GDDR5M 3
-#define BCHP_MEMC_DDR_0_CNTRLR_CONFIG_DRAM_DEVICE_TYPE_GDDR5 4
-#define BCHP_MEMC_DDR_0_CNTRLR_CONFIG_DRAM_DEVICE_TYPE_reserved_5 5
-#define BCHP_MEMC_DDR_0_CNTRLR_CONFIG_DRAM_DEVICE_TYPE_reserved_6 6
-#define BCHP_MEMC_DDR_0_CNTRLR_CONFIG_DRAM_DEVICE_TYPE_reserved_7 7
-#define BCHP_MEMC_DDR_0_CNTRLR_CONFIG_DRAM_DEVICE_TYPE_reserved_8 8
-#define BCHP_MEMC_DDR_0_CNTRLR_CONFIG_DRAM_DEVICE_TYPE_reserved_9 9
-#define BCHP_MEMC_DDR_0_CNTRLR_CONFIG_DRAM_DEVICE_TYPE_reserved_10 10
-#define BCHP_MEMC_DDR_0_CNTRLR_CONFIG_DRAM_DEVICE_TYPE_reserved_11 11
-#define BCHP_MEMC_DDR_0_CNTRLR_CONFIG_DRAM_DEVICE_TYPE_reserved_12 12
-#define BCHP_MEMC_DDR_0_CNTRLR_CONFIG_DRAM_DEVICE_TYPE_reserved_13 13
-#define BCHP_MEMC_DDR_0_CNTRLR_CONFIG_DRAM_DEVICE_TYPE_reserved_14 14
-#define BCHP_MEMC_DDR_0_CNTRLR_CONFIG_DRAM_DEVICE_TYPE_reserved_15 15
-
-/***************************************************************************
- *DRAM_INIT_CNTRL - Dram initialization control
- ***************************************************************************/
-/* MEMC_DDR_0 :: DRAM_INIT_CNTRL :: reserved0 [31:06] */
-#define BCHP_MEMC_DDR_0_DRAM_INIT_CNTRL_reserved0_MASK 0xffffffc0
-#define BCHP_MEMC_DDR_0_DRAM_INIT_CNTRL_reserved0_SHIFT 6
-
-/* MEMC_DDR_0 :: DRAM_INIT_CNTRL :: IGNORE_PHY_REQUEST_AT_RESET [05:05] */
-#define BCHP_MEMC_DDR_0_DRAM_INIT_CNTRL_IGNORE_PHY_REQUEST_AT_RESET_MASK 0x00000020
-#define BCHP_MEMC_DDR_0_DRAM_INIT_CNTRL_IGNORE_PHY_REQUEST_AT_RESET_SHIFT 5
-#define BCHP_MEMC_DDR_0_DRAM_INIT_CNTRL_IGNORE_PHY_REQUEST_AT_RESET_DEFAULT 0x00000000
-
-/* MEMC_DDR_0 :: DRAM_INIT_CNTRL :: ENTER_PHY_OP_STATE [04:04] */
-#define BCHP_MEMC_DDR_0_DRAM_INIT_CNTRL_ENTER_PHY_OP_STATE_MASK 0x00000010
-#define BCHP_MEMC_DDR_0_DRAM_INIT_CNTRL_ENTER_PHY_OP_STATE_SHIFT 4
-#define BCHP_MEMC_DDR_0_DRAM_INIT_CNTRL_ENTER_PHY_OP_STATE_DEFAULT 0x00000000
-
-/* MEMC_DDR_0 :: DRAM_INIT_CNTRL :: ENABLE_AUTO_PHY_OP_ACCESS [03:03] */
-#define BCHP_MEMC_DDR_0_DRAM_INIT_CNTRL_ENABLE_AUTO_PHY_OP_ACCESS_MASK 0x00000008
-#define BCHP_MEMC_DDR_0_DRAM_INIT_CNTRL_ENABLE_AUTO_PHY_OP_ACCESS_SHIFT 3
-#define BCHP_MEMC_DDR_0_DRAM_INIT_CNTRL_ENABLE_AUTO_PHY_OP_ACCESS_DEFAULT 0x00000000
-
-/* MEMC_DDR_0 :: DRAM_INIT_CNTRL :: OVERRIDE_PHY_INIT_COMPLETE [02:02] */
-#define BCHP_MEMC_DDR_0_DRAM_INIT_CNTRL_OVERRIDE_PHY_INIT_COMPLETE_MASK 0x00000004
-#define BCHP_MEMC_DDR_0_DRAM_INIT_CNTRL_OVERRIDE_PHY_INIT_COMPLETE_SHIFT 2
-#define BCHP_MEMC_DDR_0_DRAM_INIT_CNTRL_OVERRIDE_PHY_INIT_COMPLETE_DEFAULT 0x00000000
-
-/* MEMC_DDR_0 :: DRAM_INIT_CNTRL :: OVERRIDE_PHY_DFI_GRANT [01:01] */
-#define BCHP_MEMC_DDR_0_DRAM_INIT_CNTRL_OVERRIDE_PHY_DFI_GRANT_MASK 0x00000002
-#define BCHP_MEMC_DDR_0_DRAM_INIT_CNTRL_OVERRIDE_PHY_DFI_GRANT_SHIFT 1
-#define BCHP_MEMC_DDR_0_DRAM_INIT_CNTRL_OVERRIDE_PHY_DFI_GRANT_DEFAULT 0x00000000
-
-/* MEMC_DDR_0 :: DRAM_INIT_CNTRL :: PHY_DFI_GRANT_VALUE [00:00] */
-#define BCHP_MEMC_DDR_0_DRAM_INIT_CNTRL_PHY_DFI_GRANT_VALUE_MASK 0x00000001
-#define BCHP_MEMC_DDR_0_DRAM_INIT_CNTRL_PHY_DFI_GRANT_VALUE_SHIFT 0
-#define BCHP_MEMC_DDR_0_DRAM_INIT_CNTRL_PHY_DFI_GRANT_VALUE_DEFAULT 0x00000000
-
-/***************************************************************************
- *DRAM_INIT_STATUS - Dram initialization status
- ***************************************************************************/
-/* MEMC_DDR_0 :: DRAM_INIT_STATUS :: reserved0 [31:02] */
-#define BCHP_MEMC_DDR_0_DRAM_INIT_STATUS_reserved0_MASK 0xfffffffc
-#define BCHP_MEMC_DDR_0_DRAM_INIT_STATUS_reserved0_SHIFT 2
-
-/* MEMC_DDR_0 :: DRAM_INIT_STATUS :: PHY_DFI_REQUEST_VALUE [01:01] */
-#define BCHP_MEMC_DDR_0_DRAM_INIT_STATUS_PHY_DFI_REQUEST_VALUE_MASK 0x00000002
-#define BCHP_MEMC_DDR_0_DRAM_INIT_STATUS_PHY_DFI_REQUEST_VALUE_SHIFT 1
-#define BCHP_MEMC_DDR_0_DRAM_INIT_STATUS_PHY_DFI_REQUEST_VALUE_DEFAULT 0x00000000
-
-/* MEMC_DDR_0 :: DRAM_INIT_STATUS :: INIT_DONE [00:00] */
-#define BCHP_MEMC_DDR_0_DRAM_INIT_STATUS_INIT_DONE_MASK 0x00000001
-#define BCHP_MEMC_DDR_0_DRAM_INIT_STATUS_INIT_DONE_SHIFT 0
-#define BCHP_MEMC_DDR_0_DRAM_INIT_STATUS_INIT_DONE_DEFAULT 0x00000000
-
-/***************************************************************************
- *DRAM_MODE_0 - Dram Mode Register 0
- ***************************************************************************/
-/* MEMC_DDR_0 :: DRAM_MODE_0 :: reserved0 [31:16] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_0_reserved0_MASK 0xffff0000
-#define BCHP_MEMC_DDR_0_DRAM_MODE_0_reserved0_SHIFT 16
-
-/* MEMC_DDR_0 :: DRAM_MODE_0 :: unused_0 [15:13] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_0_unused_0_MASK 0x0000e000
-#define BCHP_MEMC_DDR_0_DRAM_MODE_0_unused_0_SHIFT 13
-#define BCHP_MEMC_DDR_0_DRAM_MODE_0_unused_0_DEFAULT 0x00000000
-
-/* union - case DDR3 [12:00] */
-/* MEMC_DDR_0 :: DRAM_MODE_0 :: DDR3 :: DLL_CNTRL_PPD [12:12] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR3_DLL_CNTRL_PPD_MASK 0x00001000
-#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR3_DLL_CNTRL_PPD_SHIFT 12
-#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR3_DLL_CNTRL_PPD_DEFAULT 0x00000000
-
-/* MEMC_DDR_0 :: DRAM_MODE_0 :: DDR3 :: WR [11:09] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR3_WR_MASK 0x00000e00
-#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR3_WR_SHIFT 9
-#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR3_WR_DEFAULT 0x00000004
-
-/* MEMC_DDR_0 :: DRAM_MODE_0 :: DDR3 :: DLL_RST [08:08] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR3_DLL_RST_MASK 0x00000100
-#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR3_DLL_RST_SHIFT 8
-#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR3_DLL_RST_DEFAULT 0x00000000
-
-/* MEMC_DDR_0 :: DRAM_MODE_0 :: DDR3 :: TEST_MODE [07:07] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR3_TEST_MODE_MASK 0x00000080
-#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR3_TEST_MODE_SHIFT 7
-#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR3_TEST_MODE_DEFAULT 0x00000000
-
-/* MEMC_DDR_0 :: DRAM_MODE_0 :: DDR3 :: CL_3_1 [06:04] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR3_CL_3_1_MASK 0x00000070
-#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR3_CL_3_1_SHIFT 4
-#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR3_CL_3_1_DEFAULT 0x00000004
-
-/* MEMC_DDR_0 :: DRAM_MODE_0 :: DDR3 :: RBT [03:03] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR3_RBT_MASK 0x00000008
-#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR3_RBT_SHIFT 3
-#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR3_RBT_DEFAULT 0x00000000
-
-/* MEMC_DDR_0 :: DRAM_MODE_0 :: DDR3 :: CL_0 [02:02] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR3_CL_0_MASK 0x00000004
-#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR3_CL_0_SHIFT 2
-#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR3_CL_0_DEFAULT 0x00000000
-
-/* MEMC_DDR_0 :: DRAM_MODE_0 :: DDR3 :: BL [01:00] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR3_BL_MASK 0x00000003
-#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR3_BL_SHIFT 0
-#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR3_BL_DEFAULT 0x00000000
-
-/* union - case DDR4 [12:00] */
-/* MEMC_DDR_0 :: DRAM_MODE_0 :: DDR4 :: unused_1 [12:12] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR4_unused_1_MASK 0x00001000
-#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR4_unused_1_SHIFT 12
-#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR4_unused_1_DEFAULT 0x00000000
-
-/* MEMC_DDR_0 :: DRAM_MODE_0 :: DDR4 :: WR [11:09] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR4_WR_MASK 0x00000e00
-#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR4_WR_SHIFT 9
-#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR4_WR_DEFAULT 0x00000004
-
-/* MEMC_DDR_0 :: DRAM_MODE_0 :: DDR4 :: DLL_RST [08:08] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR4_DLL_RST_MASK 0x00000100
-#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR4_DLL_RST_SHIFT 8
-#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR4_DLL_RST_DEFAULT 0x00000000
-
-/* MEMC_DDR_0 :: DRAM_MODE_0 :: DDR4 :: TEST_MODE [07:07] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR4_TEST_MODE_MASK 0x00000080
-#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR4_TEST_MODE_SHIFT 7
-#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR4_TEST_MODE_DEFAULT 0x00000000
-
-/* MEMC_DDR_0 :: DRAM_MODE_0 :: DDR4 :: CL_3_1 [06:04] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR4_CL_3_1_MASK 0x00000070
-#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR4_CL_3_1_SHIFT 4
-#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR4_CL_3_1_DEFAULT 0x00000004
-
-/* MEMC_DDR_0 :: DRAM_MODE_0 :: DDR4 :: BT [03:03] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR4_BT_MASK 0x00000008
-#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR4_BT_SHIFT 3
-#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR4_BT_DEFAULT 0x00000000
-
-/* MEMC_DDR_0 :: DRAM_MODE_0 :: DDR4 :: CL_0 [02:02] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR4_CL_0_MASK 0x00000004
-#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR4_CL_0_SHIFT 2
-#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR4_CL_0_DEFAULT 0x00000000
-
-/* MEMC_DDR_0 :: DRAM_MODE_0 :: DDR4 :: BL [01:00] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR4_BL_MASK 0x00000003
-#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR4_BL_SHIFT 0
-#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR4_BL_DEFAULT 0x00000000
-
-/* union - case GDDR5M [12:00] */
-/* MEMC_DDR_0 :: DRAM_MODE_0 :: GDDR5M :: unused_1 [12:12] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_0_GDDR5M_unused_1_MASK 0x00001000
-#define BCHP_MEMC_DDR_0_DRAM_MODE_0_GDDR5M_unused_1_SHIFT 12
-#define BCHP_MEMC_DDR_0_DRAM_MODE_0_GDDR5M_unused_1_DEFAULT 0x00000000
-
-/* MEMC_DDR_0 :: DRAM_MODE_0 :: GDDR5M :: WR [11:08] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_0_GDDR5M_WR_MASK 0x00000f00
-#define BCHP_MEMC_DDR_0_DRAM_MODE_0_GDDR5M_WR_SHIFT 8
-#define BCHP_MEMC_DDR_0_DRAM_MODE_0_GDDR5M_WR_DEFAULT 0x00000008
-
-/* MEMC_DDR_0 :: DRAM_MODE_0 :: GDDR5M :: TEST_MODE [07:07] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_0_GDDR5M_TEST_MODE_MASK 0x00000080
-#define BCHP_MEMC_DDR_0_DRAM_MODE_0_GDDR5M_TEST_MODE_SHIFT 7
-#define BCHP_MEMC_DDR_0_DRAM_MODE_0_GDDR5M_TEST_MODE_DEFAULT 0x00000000
-
-/* MEMC_DDR_0 :: DRAM_MODE_0 :: GDDR5M :: CL [06:03] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_0_GDDR5M_CL_MASK 0x00000078
-#define BCHP_MEMC_DDR_0_DRAM_MODE_0_GDDR5M_CL_SHIFT 3
-#define BCHP_MEMC_DDR_0_DRAM_MODE_0_GDDR5M_CL_DEFAULT 0x00000009
-
-/* MEMC_DDR_0 :: DRAM_MODE_0 :: GDDR5M :: WL [02:00] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_0_GDDR5M_WL_MASK 0x00000007
-#define BCHP_MEMC_DDR_0_DRAM_MODE_0_GDDR5M_WL_SHIFT 0
-#define BCHP_MEMC_DDR_0_DRAM_MODE_0_GDDR5M_WL_DEFAULT 0x00000004
-
-/* union - case GDDR5 [12:00] */
-/* MEMC_DDR_0 :: DRAM_MODE_0 :: GDDR5 :: unused_1 [12:12] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_0_GDDR5_unused_1_MASK 0x00001000
-#define BCHP_MEMC_DDR_0_DRAM_MODE_0_GDDR5_unused_1_SHIFT 12
-#define BCHP_MEMC_DDR_0_DRAM_MODE_0_GDDR5_unused_1_DEFAULT 0x00000000
-
-/* MEMC_DDR_0 :: DRAM_MODE_0 :: GDDR5 :: WR [11:08] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_0_GDDR5_WR_MASK 0x00000f00
-#define BCHP_MEMC_DDR_0_DRAM_MODE_0_GDDR5_WR_SHIFT 8
-#define BCHP_MEMC_DDR_0_DRAM_MODE_0_GDDR5_WR_DEFAULT 0x00000008
-
-/* MEMC_DDR_0 :: DRAM_MODE_0 :: GDDR5 :: TEST_MODE [07:07] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_0_GDDR5_TEST_MODE_MASK 0x00000080
-#define BCHP_MEMC_DDR_0_DRAM_MODE_0_GDDR5_TEST_MODE_SHIFT 7
-#define BCHP_MEMC_DDR_0_DRAM_MODE_0_GDDR5_TEST_MODE_DEFAULT 0x00000000
-
-/* MEMC_DDR_0 :: DRAM_MODE_0 :: GDDR5 :: CL [06:03] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_0_GDDR5_CL_MASK 0x00000078
-#define BCHP_MEMC_DDR_0_DRAM_MODE_0_GDDR5_CL_SHIFT 3
-#define BCHP_MEMC_DDR_0_DRAM_MODE_0_GDDR5_CL_DEFAULT 0x00000009
-
-/* MEMC_DDR_0 :: DRAM_MODE_0 :: GDDR5 :: WL [02:00] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_0_GDDR5_WL_MASK 0x00000007
-#define BCHP_MEMC_DDR_0_DRAM_MODE_0_GDDR5_WL_SHIFT 0
-#define BCHP_MEMC_DDR_0_DRAM_MODE_0_GDDR5_WL_DEFAULT 0x00000004
-
-/***************************************************************************
- *DRAM_MODE_1 - Dram Mode Register 1
- ***************************************************************************/
-/* MEMC_DDR_0 :: DRAM_MODE_1 :: reserved0 [31:16] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_1_reserved0_MASK 0xffff0000
-#define BCHP_MEMC_DDR_0_DRAM_MODE_1_reserved0_SHIFT 16
-
-/* MEMC_DDR_0 :: DRAM_MODE_1 :: unused_0 [15:13] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_1_unused_0_MASK 0x0000e000
-#define BCHP_MEMC_DDR_0_DRAM_MODE_1_unused_0_SHIFT 13
-#define BCHP_MEMC_DDR_0_DRAM_MODE_1_unused_0_DEFAULT 0x00000000
-
-/* union - case DDR3 [12:00] */
-/* MEMC_DDR_0 :: DRAM_MODE_1 :: DDR3 :: Q_OFF [12:12] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_Q_OFF_MASK 0x00001000
-#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_Q_OFF_SHIFT 12
-#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_Q_OFF_DEFAULT 0x00000000
-#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_Q_OFF_ENABLE 0
-#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_Q_OFF_DISABLE 1
-
-/* MEMC_DDR_0 :: DRAM_MODE_1 :: DDR3 :: TDQS [11:11] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_TDQS_MASK 0x00000800
-#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_TDQS_SHIFT 11
-#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_TDQS_DEFAULT 0x00000000
-#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_TDQS_ENABLE 1
-#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_TDQS_DISABLE 0
-
-/* MEMC_DDR_0 :: DRAM_MODE_1 :: DDR3 :: unused_1 [10:10] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_unused_1_MASK 0x00000400
-#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_unused_1_SHIFT 10
-#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_unused_1_DEFAULT 0x00000000
-
-/* MEMC_DDR_0 :: DRAM_MODE_1 :: DDR3 :: ODT_CNTRL_2 [09:09] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_ODT_CNTRL_2_MASK 0x00000200
-#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_ODT_CNTRL_2_SHIFT 9
-#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_ODT_CNTRL_2_DEFAULT 0x00000000
-
-/* MEMC_DDR_0 :: DRAM_MODE_1 :: DDR3 :: unused_2 [08:08] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_unused_2_MASK 0x00000100
-#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_unused_2_SHIFT 8
-#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_unused_2_DEFAULT 0x00000000
-
-/* MEMC_DDR_0 :: DRAM_MODE_1 :: DDR3 :: WR_LEVEL [07:07] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_WR_LEVEL_MASK 0x00000080
-#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_WR_LEVEL_SHIFT 7
-#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_WR_LEVEL_DEFAULT 0x00000000
-#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_WR_LEVEL_ENABLE 1
-#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_WR_LEVEL_DISABLE 0
-
-/* MEMC_DDR_0 :: DRAM_MODE_1 :: DDR3 :: ODT_CNTRL_1 [06:06] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_ODT_CNTRL_1_MASK 0x00000040
-#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_ODT_CNTRL_1_SHIFT 6
-#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_ODT_CNTRL_1_DEFAULT 0x00000000
-
-/* MEMC_DDR_0 :: DRAM_MODE_1 :: DDR3 :: DRIVER_IMP_CNTRL_1 [05:05] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_DRIVER_IMP_CNTRL_1_MASK 0x00000020
-#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_DRIVER_IMP_CNTRL_1_SHIFT 5
-#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_DRIVER_IMP_CNTRL_1_DEFAULT 0x00000000
-
-/* MEMC_DDR_0 :: DRAM_MODE_1 :: DDR3 :: AL [04:03] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_AL_MASK 0x00000018
-#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_AL_SHIFT 3
-#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_AL_DEFAULT 0x00000001
-
-/* MEMC_DDR_0 :: DRAM_MODE_1 :: DDR3 :: ODT_CNTRL_0 [02:02] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_ODT_CNTRL_0_MASK 0x00000004
-#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_ODT_CNTRL_0_SHIFT 2
-#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_ODT_CNTRL_0_DEFAULT 0x00000001
-
-/* MEMC_DDR_0 :: DRAM_MODE_1 :: DDR3 :: DRIVER_IMP_CNTRL_0 [01:01] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_DRIVER_IMP_CNTRL_0_MASK 0x00000002
-#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_DRIVER_IMP_CNTRL_0_SHIFT 1
-#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_DRIVER_IMP_CNTRL_0_DEFAULT 0x00000000
-
-/* MEMC_DDR_0 :: DRAM_MODE_1 :: DDR3 :: DLL_EN [00:00] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_DLL_EN_MASK 0x00000001
-#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_DLL_EN_SHIFT 0
-#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_DLL_EN_DEFAULT 0x00000000
-#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_DLL_EN_ENABLE 0
-#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_DLL_EN_DISABLE 1
-
-/* union - case DDR4 [12:00] */
-/* MEMC_DDR_0 :: DRAM_MODE_1 :: DDR4 :: Q_OFF [12:12] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR4_Q_OFF_MASK 0x00001000
-#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR4_Q_OFF_SHIFT 12
-#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR4_Q_OFF_DEFAULT 0x00000000
-#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR4_Q_OFF_ENABLE 0
-#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR4_Q_OFF_DISABLE 1
-
-/* MEMC_DDR_0 :: DRAM_MODE_1 :: DDR4 :: TDQS [11:11] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR4_TDQS_MASK 0x00000800
-#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR4_TDQS_SHIFT 11
-#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR4_TDQS_DEFAULT 0x00000000
-#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR4_TDQS_ENABLE 1
-#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR4_TDQS_DISABLE 0
-
-/* MEMC_DDR_0 :: DRAM_MODE_1 :: DDR4 :: unused_1 [10:10] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR4_unused_1_MASK 0x00000400
-#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR4_unused_1_SHIFT 10
-#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR4_unused_1_DEFAULT 0x00000000
-
-/* MEMC_DDR_0 :: DRAM_MODE_1 :: DDR4 :: ODT_CNTRL_2 [09:09] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR4_ODT_CNTRL_2_MASK 0x00000200
-#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR4_ODT_CNTRL_2_SHIFT 9
-#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR4_ODT_CNTRL_2_DEFAULT 0x00000000
-
-/* MEMC_DDR_0 :: DRAM_MODE_1 :: DDR4 :: unused_2 [08:08] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR4_unused_2_MASK 0x00000100
-#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR4_unused_2_SHIFT 8
-#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR4_unused_2_DEFAULT 0x00000000
-
-/* MEMC_DDR_0 :: DRAM_MODE_1 :: DDR4 :: WR_LEVEL [07:07] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR4_WR_LEVEL_MASK 0x00000080
-#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR4_WR_LEVEL_SHIFT 7
-#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR4_WR_LEVEL_DEFAULT 0x00000000
-#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR4_WR_LEVEL_ENABLE 1
-#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR4_WR_LEVEL_DISABLE 0
-
-/* MEMC_DDR_0 :: DRAM_MODE_1 :: DDR4 :: ODT_CNTRL_1 [06:06] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR4_ODT_CNTRL_1_MASK 0x00000040
-#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR4_ODT_CNTRL_1_SHIFT 6
-#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR4_ODT_CNTRL_1_DEFAULT 0x00000000
-
-/* MEMC_DDR_0 :: DRAM_MODE_1 :: DDR4 :: DRIVER_IMP_CNTRL_1 [05:05] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR4_DRIVER_IMP_CNTRL_1_MASK 0x00000020
-#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR4_DRIVER_IMP_CNTRL_1_SHIFT 5
-#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR4_DRIVER_IMP_CNTRL_1_DEFAULT 0x00000000
-
-/* MEMC_DDR_0 :: DRAM_MODE_1 :: DDR4 :: AL [04:03] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR4_AL_MASK 0x00000018
-#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR4_AL_SHIFT 3
-#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR4_AL_DEFAULT 0x00000001
-
-/* MEMC_DDR_0 :: DRAM_MODE_1 :: DDR4 :: ODT_CNTRL_0 [02:02] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR4_ODT_CNTRL_0_MASK 0x00000004
-#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR4_ODT_CNTRL_0_SHIFT 2
-#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR4_ODT_CNTRL_0_DEFAULT 0x00000001
-
-/* MEMC_DDR_0 :: DRAM_MODE_1 :: DDR4 :: DRIVER_IMP_CNTRL_0 [01:01] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR4_DRIVER_IMP_CNTRL_0_MASK 0x00000002
-#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR4_DRIVER_IMP_CNTRL_0_SHIFT 1
-#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR4_DRIVER_IMP_CNTRL_0_DEFAULT 0x00000000
-
-/* MEMC_DDR_0 :: DRAM_MODE_1 :: DDR4 :: DLL_EN [00:00] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR4_DLL_EN_MASK 0x00000001
-#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR4_DLL_EN_SHIFT 0
-#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR4_DLL_EN_DEFAULT 0x00000000
-#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR4_DLL_EN_ENABLE 0
-#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR4_DLL_EN_DISABLE 1
-
-/* union - case GDDR5M [12:00] */
-/* MEMC_DDR_0 :: DRAM_MODE_1 :: GDDR5M :: unused_1 [12:11] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_1_GDDR5M_unused_1_MASK 0x00001800
-#define BCHP_MEMC_DDR_0_DRAM_MODE_1_GDDR5M_unused_1_SHIFT 11
-#define BCHP_MEMC_DDR_0_DRAM_MODE_1_GDDR5M_unused_1_DEFAULT 0x00000000
-
-/* MEMC_DDR_0 :: DRAM_MODE_1 :: GDDR5M :: ABI [10:10] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_1_GDDR5M_ABI_MASK 0x00000400
-#define BCHP_MEMC_DDR_0_DRAM_MODE_1_GDDR5M_ABI_SHIFT 10
-#define BCHP_MEMC_DDR_0_DRAM_MODE_1_GDDR5M_ABI_DEFAULT 0x00000000
-#define BCHP_MEMC_DDR_0_DRAM_MODE_1_GDDR5M_ABI_ENABLE 0
-#define BCHP_MEMC_DDR_0_DRAM_MODE_1_GDDR5M_ABI_DISABLE 1
-
-/* MEMC_DDR_0 :: DRAM_MODE_1 :: GDDR5M :: WDBI [09:09] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_1_GDDR5M_WDBI_MASK 0x00000200
-#define BCHP_MEMC_DDR_0_DRAM_MODE_1_GDDR5M_WDBI_SHIFT 9
-#define BCHP_MEMC_DDR_0_DRAM_MODE_1_GDDR5M_WDBI_DEFAULT 0x00000000
-#define BCHP_MEMC_DDR_0_DRAM_MODE_1_GDDR5M_WDBI_ENABLE 0
-#define BCHP_MEMC_DDR_0_DRAM_MODE_1_GDDR5M_WDBI_DISABLE 1
-
-/* MEMC_DDR_0 :: DRAM_MODE_1 :: GDDR5M :: RDBI [08:08] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_1_GDDR5M_RDBI_MASK 0x00000100
-#define BCHP_MEMC_DDR_0_DRAM_MODE_1_GDDR5M_RDBI_SHIFT 8
-#define BCHP_MEMC_DDR_0_DRAM_MODE_1_GDDR5M_RDBI_DEFAULT 0x00000000
-#define BCHP_MEMC_DDR_0_DRAM_MODE_1_GDDR5M_RDBI_ENABLE 0
-#define BCHP_MEMC_DDR_0_DRAM_MODE_1_GDDR5M_RDBI_DISABLE 1
-
-/* MEMC_DDR_0 :: DRAM_MODE_1 :: GDDR5M :: unused_2 [07:07] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_1_GDDR5M_unused_2_MASK 0x00000080
-#define BCHP_MEMC_DDR_0_DRAM_MODE_1_GDDR5M_unused_2_SHIFT 7
-#define BCHP_MEMC_DDR_0_DRAM_MODE_1_GDDR5M_unused_2_DEFAULT 0x00000000
-
-/* MEMC_DDR_0 :: DRAM_MODE_1 :: GDDR5M :: CAL_UPD [06:06] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_1_GDDR5M_CAL_UPD_MASK 0x00000040
-#define BCHP_MEMC_DDR_0_DRAM_MODE_1_GDDR5M_CAL_UPD_SHIFT 6
-#define BCHP_MEMC_DDR_0_DRAM_MODE_1_GDDR5M_CAL_UPD_DEFAULT 0x00000000
-#define BCHP_MEMC_DDR_0_DRAM_MODE_1_GDDR5M_CAL_UPD_ENABLE 0
-#define BCHP_MEMC_DDR_0_DRAM_MODE_1_GDDR5M_CAL_UPD_DISABLE 1
-
-/* MEMC_DDR_0 :: DRAM_MODE_1 :: GDDR5M :: ADDR_CMD_TERM [05:04] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_1_GDDR5M_ADDR_CMD_TERM_MASK 0x00000030
-#define BCHP_MEMC_DDR_0_DRAM_MODE_1_GDDR5M_ADDR_CMD_TERM_SHIFT 4
-#define BCHP_MEMC_DDR_0_DRAM_MODE_1_GDDR5M_ADDR_CMD_TERM_DEFAULT 0x00000000
-
-/* MEMC_DDR_0 :: DRAM_MODE_1 :: GDDR5M :: DATA_TERM [03:02] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_1_GDDR5M_DATA_TERM_MASK 0x0000000c
-#define BCHP_MEMC_DDR_0_DRAM_MODE_1_GDDR5M_DATA_TERM_SHIFT 2
-#define BCHP_MEMC_DDR_0_DRAM_MODE_1_GDDR5M_DATA_TERM_DEFAULT 0x00000000
-
-/* MEMC_DDR_0 :: DRAM_MODE_1 :: GDDR5M :: DRIVER_STRENGTH [01:00] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_1_GDDR5M_DRIVER_STRENGTH_MASK 0x00000003
-#define BCHP_MEMC_DDR_0_DRAM_MODE_1_GDDR5M_DRIVER_STRENGTH_SHIFT 0
-#define BCHP_MEMC_DDR_0_DRAM_MODE_1_GDDR5M_DRIVER_STRENGTH_DEFAULT 0x00000000
-
-/* union - case GDDR5 [12:00] */
-/* MEMC_DDR_0 :: DRAM_MODE_1 :: GDDR5 :: unused_1 [12:12] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_1_GDDR5_unused_1_MASK 0x00001000
-#define BCHP_MEMC_DDR_0_DRAM_MODE_1_GDDR5_unused_1_SHIFT 12
-#define BCHP_MEMC_DDR_0_DRAM_MODE_1_GDDR5_unused_1_DEFAULT 0x00000000
-
-/* MEMC_DDR_0 :: DRAM_MODE_1 :: GDDR5 :: PLL_DLL_RST [11:11] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_1_GDDR5_PLL_DLL_RST_MASK 0x00000800
-#define BCHP_MEMC_DDR_0_DRAM_MODE_1_GDDR5_PLL_DLL_RST_SHIFT 11
-#define BCHP_MEMC_DDR_0_DRAM_MODE_1_GDDR5_PLL_DLL_RST_DEFAULT 0x00000000
-
-/* MEMC_DDR_0 :: DRAM_MODE_1 :: GDDR5 :: ABI [10:10] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_1_GDDR5_ABI_MASK 0x00000400
-#define BCHP_MEMC_DDR_0_DRAM_MODE_1_GDDR5_ABI_SHIFT 10
-#define BCHP_MEMC_DDR_0_DRAM_MODE_1_GDDR5_ABI_DEFAULT 0x00000000
-#define BCHP_MEMC_DDR_0_DRAM_MODE_1_GDDR5_ABI_ENABLE 0
-#define BCHP_MEMC_DDR_0_DRAM_MODE_1_GDDR5_ABI_DISABLE 1
-
-/* MEMC_DDR_0 :: DRAM_MODE_1 :: GDDR5 :: WDBI [09:09] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_1_GDDR5_WDBI_MASK 0x00000200
-#define BCHP_MEMC_DDR_0_DRAM_MODE_1_GDDR5_WDBI_SHIFT 9
-#define BCHP_MEMC_DDR_0_DRAM_MODE_1_GDDR5_WDBI_DEFAULT 0x00000000
-#define BCHP_MEMC_DDR_0_DRAM_MODE_1_GDDR5_WDBI_ENABLE 0
-#define BCHP_MEMC_DDR_0_DRAM_MODE_1_GDDR5_WDBI_DISABLE 1
-
-/* MEMC_DDR_0 :: DRAM_MODE_1 :: GDDR5 :: RDBI [08:08] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_1_GDDR5_RDBI_MASK 0x00000100
-#define BCHP_MEMC_DDR_0_DRAM_MODE_1_GDDR5_RDBI_SHIFT 8
-#define BCHP_MEMC_DDR_0_DRAM_MODE_1_GDDR5_RDBI_DEFAULT 0x00000000
-#define BCHP_MEMC_DDR_0_DRAM_MODE_1_GDDR5_RDBI_ENABLE 0
-#define BCHP_MEMC_DDR_0_DRAM_MODE_1_GDDR5_RDBI_DISABLE 1
-
-/* MEMC_DDR_0 :: DRAM_MODE_1 :: GDDR5 :: PLL_DLL [07:07] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_1_GDDR5_PLL_DLL_MASK 0x00000080
-#define BCHP_MEMC_DDR_0_DRAM_MODE_1_GDDR5_PLL_DLL_SHIFT 7
-#define BCHP_MEMC_DDR_0_DRAM_MODE_1_GDDR5_PLL_DLL_DEFAULT 0x00000000
-
-/* MEMC_DDR_0 :: DRAM_MODE_1 :: GDDR5 :: CAL_UPD [06:06] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_1_GDDR5_CAL_UPD_MASK 0x00000040
-#define BCHP_MEMC_DDR_0_DRAM_MODE_1_GDDR5_CAL_UPD_SHIFT 6
-#define BCHP_MEMC_DDR_0_DRAM_MODE_1_GDDR5_CAL_UPD_DEFAULT 0x00000000
-#define BCHP_MEMC_DDR_0_DRAM_MODE_1_GDDR5_CAL_UPD_ENABLE 0
-#define BCHP_MEMC_DDR_0_DRAM_MODE_1_GDDR5_CAL_UPD_DISABLE 1
-
-/* MEMC_DDR_0 :: DRAM_MODE_1 :: GDDR5 :: ADDR_CMD_TERM [05:04] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_1_GDDR5_ADDR_CMD_TERM_MASK 0x00000030
-#define BCHP_MEMC_DDR_0_DRAM_MODE_1_GDDR5_ADDR_CMD_TERM_SHIFT 4
-#define BCHP_MEMC_DDR_0_DRAM_MODE_1_GDDR5_ADDR_CMD_TERM_DEFAULT 0x00000000
-
-/* MEMC_DDR_0 :: DRAM_MODE_1 :: GDDR5 :: DATA_TERM [03:02] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_1_GDDR5_DATA_TERM_MASK 0x0000000c
-#define BCHP_MEMC_DDR_0_DRAM_MODE_1_GDDR5_DATA_TERM_SHIFT 2
-#define BCHP_MEMC_DDR_0_DRAM_MODE_1_GDDR5_DATA_TERM_DEFAULT 0x00000000
-
-/* MEMC_DDR_0 :: DRAM_MODE_1 :: GDDR5 :: DRIVER_STRENGTH [01:00] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_1_GDDR5_DRIVER_STRENGTH_MASK 0x00000003
-#define BCHP_MEMC_DDR_0_DRAM_MODE_1_GDDR5_DRIVER_STRENGTH_SHIFT 0
-#define BCHP_MEMC_DDR_0_DRAM_MODE_1_GDDR5_DRIVER_STRENGTH_DEFAULT 0x00000000
-
-/***************************************************************************
- *DRAM_MODE_2 - Dram Mode Register 2
- ***************************************************************************/
-/* MEMC_DDR_0 :: DRAM_MODE_2 :: reserved0 [31:16] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_2_reserved0_MASK 0xffff0000
-#define BCHP_MEMC_DDR_0_DRAM_MODE_2_reserved0_SHIFT 16
-
-/* MEMC_DDR_0 :: DRAM_MODE_2 :: unused_0 [15:13] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_2_unused_0_MASK 0x0000e000
-#define BCHP_MEMC_DDR_0_DRAM_MODE_2_unused_0_SHIFT 13
-#define BCHP_MEMC_DDR_0_DRAM_MODE_2_unused_0_DEFAULT 0x00000000
-
-/* union - case DDR3 [12:00] */
-/* MEMC_DDR_0 :: DRAM_MODE_2 :: DDR3 :: unused_1 [12:11] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR3_unused_1_MASK 0x00001800
-#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR3_unused_1_SHIFT 11
-#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR3_unused_1_DEFAULT 0x00000000
-
-/* MEMC_DDR_0 :: DRAM_MODE_2 :: DDR3 :: WR_ODT [10:09] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR3_WR_ODT_MASK 0x00000600
-#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR3_WR_ODT_SHIFT 9
-#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR3_WR_ODT_DEFAULT 0x00000001
-
-/* MEMC_DDR_0 :: DRAM_MODE_2 :: DDR3 :: unused_2 [08:08] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR3_unused_2_MASK 0x00000100
-#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR3_unused_2_SHIFT 8
-#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR3_unused_2_DEFAULT 0x00000000
-
-/* MEMC_DDR_0 :: DRAM_MODE_2 :: DDR3 :: SRF_TR [07:07] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR3_SRF_TR_MASK 0x00000080
-#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR3_SRF_TR_SHIFT 7
-#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR3_SRF_TR_DEFAULT 0x00000000
-
-/* MEMC_DDR_0 :: DRAM_MODE_2 :: DDR3 :: AUTO_SR [06:06] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR3_AUTO_SR_MASK 0x00000040
-#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR3_AUTO_SR_SHIFT 6
-#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR3_AUTO_SR_DEFAULT 0x00000001
-
-/* MEMC_DDR_0 :: DRAM_MODE_2 :: DDR3 :: WCL [05:03] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR3_WCL_MASK 0x00000038
-#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR3_WCL_SHIFT 3
-#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR3_WCL_DEFAULT 0x00000001
-
-/* MEMC_DDR_0 :: DRAM_MODE_2 :: DDR3 :: PASR [02:00] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR3_PASR_MASK 0x00000007
-#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR3_PASR_SHIFT 0
-#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR3_PASR_DEFAULT 0x00000000
-
-/* union - case DDR4 [12:00] */
-/* MEMC_DDR_0 :: DRAM_MODE_2 :: DDR4 :: WR_DATA_CRC [12:12] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR4_WR_DATA_CRC_MASK 0x00001000
-#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR4_WR_DATA_CRC_SHIFT 12
-#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR4_WR_DATA_CRC_DEFAULT 0x00000000
-#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR4_WR_DATA_CRC_ENABLE 1
-#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR4_WR_DATA_CRC_DISABLE 0
-
-/* MEMC_DDR_0 :: DRAM_MODE_2 :: DDR4 :: RD_DATA_CRC [11:11] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR4_RD_DATA_CRC_MASK 0x00000800
-#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR4_RD_DATA_CRC_SHIFT 11
-#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR4_RD_DATA_CRC_DEFAULT 0x00000000
-#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR4_RD_DATA_CRC_ENABLE 1
-#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR4_RD_DATA_CRC_DISABLE 0
-
-/* MEMC_DDR_0 :: DRAM_MODE_2 :: DDR4 :: RTT_WR [10:09] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR4_RTT_WR_MASK 0x00000600
-#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR4_RTT_WR_SHIFT 9
-#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR4_RTT_WR_DEFAULT 0x00000001
-
-/* MEMC_DDR_0 :: DRAM_MODE_2 :: DDR4 :: unused_1 [08:08] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR4_unused_1_MASK 0x00000100
-#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR4_unused_1_SHIFT 8
-#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR4_unused_1_DEFAULT 0x00000000
-
-/* MEMC_DDR_0 :: DRAM_MODE_2 :: DDR4 :: LPASR [07:06] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR4_LPASR_MASK 0x000000c0
-#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR4_LPASR_SHIFT 6
-#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR4_LPASR_DEFAULT 0x00000000
-
-/* MEMC_DDR_0 :: DRAM_MODE_2 :: DDR4 :: CWL [05:03] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR4_CWL_MASK 0x00000038
-#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR4_CWL_SHIFT 3
-#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR4_CWL_DEFAULT 0x00000001
-
-/* MEMC_DDR_0 :: DRAM_MODE_2 :: DDR4 :: PASR [02:00] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR4_PASR_MASK 0x00000007
-#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR4_PASR_SHIFT 0
-#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR4_PASR_DEFAULT 0x00000000
-
-/* union - case GDDR5M [12:00] */
-/* MEMC_DDR_0 :: DRAM_MODE_2 :: GDDR5M :: unused_1 [12:12] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_2_GDDR5M_unused_1_MASK 0x00001000
-#define BCHP_MEMC_DDR_0_DRAM_MODE_2_GDDR5M_unused_1_SHIFT 12
-#define BCHP_MEMC_DDR_0_DRAM_MODE_2_GDDR5M_unused_1_DEFAULT 0x00000000
-
-/* MEMC_DDR_0 :: DRAM_MODE_2 :: GDDR5M :: ADDR_CMD_TERM_OFFSET [11:09] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_2_GDDR5M_ADDR_CMD_TERM_OFFSET_MASK 0x00000e00
-#define BCHP_MEMC_DDR_0_DRAM_MODE_2_GDDR5M_ADDR_CMD_TERM_OFFSET_SHIFT 9
-#define BCHP_MEMC_DDR_0_DRAM_MODE_2_GDDR5M_ADDR_CMD_TERM_OFFSET_DEFAULT 0x00000000
-
-/* MEMC_DDR_0 :: DRAM_MODE_2 :: GDDR5M :: DATA_WCK_TERM_OFFSET [08:06] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_2_GDDR5M_DATA_WCK_TERM_OFFSET_MASK 0x000001c0
-#define BCHP_MEMC_DDR_0_DRAM_MODE_2_GDDR5M_DATA_WCK_TERM_OFFSET_SHIFT 6
-#define BCHP_MEMC_DDR_0_DRAM_MODE_2_GDDR5M_DATA_WCK_TERM_OFFSET_DEFAULT 0x00000000
-
-/* MEMC_DDR_0 :: DRAM_MODE_2 :: GDDR5M :: OCD_PUP_DRIVER_OFFSET [05:03] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_2_GDDR5M_OCD_PUP_DRIVER_OFFSET_MASK 0x00000038
-#define BCHP_MEMC_DDR_0_DRAM_MODE_2_GDDR5M_OCD_PUP_DRIVER_OFFSET_SHIFT 3
-#define BCHP_MEMC_DDR_0_DRAM_MODE_2_GDDR5M_OCD_PUP_DRIVER_OFFSET_DEFAULT 0x00000000
-
-/* MEMC_DDR_0 :: DRAM_MODE_2 :: GDDR5M :: OCD_PDN_DRIVER_OFFSET [02:00] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_2_GDDR5M_OCD_PDN_DRIVER_OFFSET_MASK 0x00000007
-#define BCHP_MEMC_DDR_0_DRAM_MODE_2_GDDR5M_OCD_PDN_DRIVER_OFFSET_SHIFT 0
-#define BCHP_MEMC_DDR_0_DRAM_MODE_2_GDDR5M_OCD_PDN_DRIVER_OFFSET_DEFAULT 0x00000000
-
-/* union - case GDDR5 [12:00] */
-/* MEMC_DDR_0 :: DRAM_MODE_2 :: GDDR5 :: unused_1 [12:12] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_2_GDDR5_unused_1_MASK 0x00001000
-#define BCHP_MEMC_DDR_0_DRAM_MODE_2_GDDR5_unused_1_SHIFT 12
-#define BCHP_MEMC_DDR_0_DRAM_MODE_2_GDDR5_unused_1_DEFAULT 0x00000000
-
-/* MEMC_DDR_0 :: DRAM_MODE_2 :: GDDR5 :: ADDR_CMD_TERM_OFFSET [11:09] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_2_GDDR5_ADDR_CMD_TERM_OFFSET_MASK 0x00000e00
-#define BCHP_MEMC_DDR_0_DRAM_MODE_2_GDDR5_ADDR_CMD_TERM_OFFSET_SHIFT 9
-#define BCHP_MEMC_DDR_0_DRAM_MODE_2_GDDR5_ADDR_CMD_TERM_OFFSET_DEFAULT 0x00000000
-
-/* MEMC_DDR_0 :: DRAM_MODE_2 :: GDDR5 :: DATA_WCK_TERM_OFFSET [08:06] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_2_GDDR5_DATA_WCK_TERM_OFFSET_MASK 0x000001c0
-#define BCHP_MEMC_DDR_0_DRAM_MODE_2_GDDR5_DATA_WCK_TERM_OFFSET_SHIFT 6
-#define BCHP_MEMC_DDR_0_DRAM_MODE_2_GDDR5_DATA_WCK_TERM_OFFSET_DEFAULT 0x00000000
-
-/* MEMC_DDR_0 :: DRAM_MODE_2 :: GDDR5 :: OCD_PUP_DRIVER_OFFSET [05:03] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_2_GDDR5_OCD_PUP_DRIVER_OFFSET_MASK 0x00000038
-#define BCHP_MEMC_DDR_0_DRAM_MODE_2_GDDR5_OCD_PUP_DRIVER_OFFSET_SHIFT 3
-#define BCHP_MEMC_DDR_0_DRAM_MODE_2_GDDR5_OCD_PUP_DRIVER_OFFSET_DEFAULT 0x00000000
-
-/* MEMC_DDR_0 :: DRAM_MODE_2 :: GDDR5 :: OCD_PDN_DRIVER_OFFSET [02:00] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_2_GDDR5_OCD_PDN_DRIVER_OFFSET_MASK 0x00000007
-#define BCHP_MEMC_DDR_0_DRAM_MODE_2_GDDR5_OCD_PDN_DRIVER_OFFSET_SHIFT 0
-#define BCHP_MEMC_DDR_0_DRAM_MODE_2_GDDR5_OCD_PDN_DRIVER_OFFSET_DEFAULT 0x00000000
-
-/***************************************************************************
- *DRAM_MODE_3 - Dram Mode Register 3
- ***************************************************************************/
-/* MEMC_DDR_0 :: DRAM_MODE_3 :: reserved0 [31:16] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_3_reserved0_MASK 0xffff0000
-#define BCHP_MEMC_DDR_0_DRAM_MODE_3_reserved0_SHIFT 16
-
-/* MEMC_DDR_0 :: DRAM_MODE_3 :: unused_0 [15:13] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_3_unused_0_MASK 0x0000e000
-#define BCHP_MEMC_DDR_0_DRAM_MODE_3_unused_0_SHIFT 13
-#define BCHP_MEMC_DDR_0_DRAM_MODE_3_unused_0_DEFAULT 0x00000000
-
-/* union - case DDR3 [12:00] */
-/* MEMC_DDR_0 :: DRAM_MODE_3 :: DDR3 :: unused_1 [12:03] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_3_DDR3_unused_1_MASK 0x00001ff8
-#define BCHP_MEMC_DDR_0_DRAM_MODE_3_DDR3_unused_1_SHIFT 3
-#define BCHP_MEMC_DDR_0_DRAM_MODE_3_DDR3_unused_1_DEFAULT 0x00000000
-
-/* MEMC_DDR_0 :: DRAM_MODE_3 :: DDR3 :: MPR [02:02] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_3_DDR3_MPR_MASK 0x00000004
-#define BCHP_MEMC_DDR_0_DRAM_MODE_3_DDR3_MPR_SHIFT 2
-#define BCHP_MEMC_DDR_0_DRAM_MODE_3_DDR3_MPR_DEFAULT 0x00000000
-
-/* MEMC_DDR_0 :: DRAM_MODE_3 :: DDR3 :: MPR_LOC [01:00] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_3_DDR3_MPR_LOC_MASK 0x00000003
-#define BCHP_MEMC_DDR_0_DRAM_MODE_3_DDR3_MPR_LOC_SHIFT 0
-#define BCHP_MEMC_DDR_0_DRAM_MODE_3_DDR3_MPR_LOC_DEFAULT 0x00000000
-
-/* union - case DDR4 [12:00] */
-/* MEMC_DDR_0 :: DRAM_MODE_3 :: DDR4 :: MPR_READ_FORMAT [12:11] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_3_DDR4_MPR_READ_FORMAT_MASK 0x00001800
-#define BCHP_MEMC_DDR_0_DRAM_MODE_3_DDR4_MPR_READ_FORMAT_SHIFT 11
-#define BCHP_MEMC_DDR_0_DRAM_MODE_3_DDR4_MPR_READ_FORMAT_DEFAULT 0x00000000
-
-/* MEMC_DDR_0 :: DRAM_MODE_3 :: DDR4 :: unused_1 [10:09] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_3_DDR4_unused_1_MASK 0x00000600
-#define BCHP_MEMC_DDR_0_DRAM_MODE_3_DDR4_unused_1_SHIFT 9
-#define BCHP_MEMC_DDR_0_DRAM_MODE_3_DDR4_unused_1_DEFAULT 0x00000000
-
-/* MEMC_DDR_0 :: DRAM_MODE_3 :: DDR4 :: FGR [08:06] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_3_DDR4_FGR_MASK 0x000001c0
-#define BCHP_MEMC_DDR_0_DRAM_MODE_3_DDR4_FGR_SHIFT 6
-#define BCHP_MEMC_DDR_0_DRAM_MODE_3_DDR4_FGR_DEFAULT 0x00000000
-
-/* MEMC_DDR_0 :: DRAM_MODE_3 :: DDR4 :: MRS_READOUT [05:05] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_3_DDR4_MRS_READOUT_MASK 0x00000020
-#define BCHP_MEMC_DDR_0_DRAM_MODE_3_DDR4_MRS_READOUT_SHIFT 5
-#define BCHP_MEMC_DDR_0_DRAM_MODE_3_DDR4_MRS_READOUT_DEFAULT 0x00000000
-#define BCHP_MEMC_DDR_0_DRAM_MODE_3_DDR4_MRS_READOUT_ENABLE 1
-#define BCHP_MEMC_DDR_0_DRAM_MODE_3_DDR4_MRS_READOUT_DISABLE 0
-
-/* MEMC_DDR_0 :: DRAM_MODE_3 :: DDR4 :: PER_DRAM_ADDR [04:04] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_3_DDR4_PER_DRAM_ADDR_MASK 0x00000010
-#define BCHP_MEMC_DDR_0_DRAM_MODE_3_DDR4_PER_DRAM_ADDR_SHIFT 4
-#define BCHP_MEMC_DDR_0_DRAM_MODE_3_DDR4_PER_DRAM_ADDR_DEFAULT 0x00000000
-#define BCHP_MEMC_DDR_0_DRAM_MODE_3_DDR4_PER_DRAM_ADDR_ENABLE 1
-#define BCHP_MEMC_DDR_0_DRAM_MODE_3_DDR4_PER_DRAM_ADDR_DISABLE 0
-
-/* MEMC_DDR_0 :: DRAM_MODE_3 :: DDR4 :: GEARDOWN [03:03] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_3_DDR4_GEARDOWN_MASK 0x00000008
-#define BCHP_MEMC_DDR_0_DRAM_MODE_3_DDR4_GEARDOWN_SHIFT 3
-#define BCHP_MEMC_DDR_0_DRAM_MODE_3_DDR4_GEARDOWN_DEFAULT 0x00000000
-
-/* MEMC_DDR_0 :: DRAM_MODE_3 :: DDR4 :: MPR [02:02] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_3_DDR4_MPR_MASK 0x00000004
-#define BCHP_MEMC_DDR_0_DRAM_MODE_3_DDR4_MPR_SHIFT 2
-#define BCHP_MEMC_DDR_0_DRAM_MODE_3_DDR4_MPR_DEFAULT 0x00000000
-
-/* MEMC_DDR_0 :: DRAM_MODE_3 :: DDR4 :: MPR_PAGE [01:00] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_3_DDR4_MPR_PAGE_MASK 0x00000003
-#define BCHP_MEMC_DDR_0_DRAM_MODE_3_DDR4_MPR_PAGE_SHIFT 0
-#define BCHP_MEMC_DDR_0_DRAM_MODE_3_DDR4_MPR_PAGE_DEFAULT 0x00000000
-
-/* union - case GDDR5M [12:00] */
-/* MEMC_DDR_0 :: DRAM_MODE_3 :: GDDR5M :: unused_1 [12:12] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_3_GDDR5M_unused_1_MASK 0x00001000
-#define BCHP_MEMC_DDR_0_DRAM_MODE_3_GDDR5M_unused_1_SHIFT 12
-#define BCHP_MEMC_DDR_0_DRAM_MODE_3_GDDR5M_unused_1_DEFAULT 0x00000000
-
-/* MEMC_DDR_0 :: DRAM_MODE_3 :: GDDR5M :: BANK_GROUPS [11:10] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_3_GDDR5M_BANK_GROUPS_MASK 0x00000c00
-#define BCHP_MEMC_DDR_0_DRAM_MODE_3_GDDR5M_BANK_GROUPS_SHIFT 10
-#define BCHP_MEMC_DDR_0_DRAM_MODE_3_GDDR5M_BANK_GROUPS_DEFAULT 0x00000000
-
-/* MEMC_DDR_0 :: DRAM_MODE_3 :: GDDR5M :: WCK_TERM [09:08] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_3_GDDR5M_WCK_TERM_MASK 0x00000300
-#define BCHP_MEMC_DDR_0_DRAM_MODE_3_GDDR5M_WCK_TERM_SHIFT 8
-#define BCHP_MEMC_DDR_0_DRAM_MODE_3_GDDR5M_WCK_TERM_DEFAULT 0x00000000
-
-/* MEMC_DDR_0 :: DRAM_MODE_3 :: GDDR5M :: DRAM_INFO [07:06] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_3_GDDR5M_DRAM_INFO_MASK 0x000000c0
-#define BCHP_MEMC_DDR_0_DRAM_MODE_3_GDDR5M_DRAM_INFO_SHIFT 6
-#define BCHP_MEMC_DDR_0_DRAM_MODE_3_GDDR5M_DRAM_INFO_DEFAULT 0x00000000
-
-/* MEMC_DDR_0 :: DRAM_MODE_3 :: GDDR5M :: RDQS_MODE [05:05] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_3_GDDR5M_RDQS_MODE_MASK 0x00000020
-#define BCHP_MEMC_DDR_0_DRAM_MODE_3_GDDR5M_RDQS_MODE_SHIFT 5
-#define BCHP_MEMC_DDR_0_DRAM_MODE_3_GDDR5M_RDQS_MODE_DEFAULT 0x00000000
-#define BCHP_MEMC_DDR_0_DRAM_MODE_3_GDDR5M_RDQS_MODE_ENABLE 1
-#define BCHP_MEMC_DDR_0_DRAM_MODE_3_GDDR5M_RDQS_MODE_DISABLE 0
-
-/* MEMC_DDR_0 :: DRAM_MODE_3 :: GDDR5M :: WCK2CK_TRAIN [04:04] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_3_GDDR5M_WCK2CK_TRAIN_MASK 0x00000010
-#define BCHP_MEMC_DDR_0_DRAM_MODE_3_GDDR5M_WCK2CK_TRAIN_SHIFT 4
-#define BCHP_MEMC_DDR_0_DRAM_MODE_3_GDDR5M_WCK2CK_TRAIN_DEFAULT 0x00000000
-#define BCHP_MEMC_DDR_0_DRAM_MODE_3_GDDR5M_WCK2CK_TRAIN_ENABLE 1
-#define BCHP_MEMC_DDR_0_DRAM_MODE_3_GDDR5M_WCK2CK_TRAIN_DISABLE 0
-
-/* MEMC_DDR_0 :: DRAM_MODE_3 :: GDDR5M :: WCK23_INVERT [03:03] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_3_GDDR5M_WCK23_INVERT_MASK 0x00000008
-#define BCHP_MEMC_DDR_0_DRAM_MODE_3_GDDR5M_WCK23_INVERT_SHIFT 3
-#define BCHP_MEMC_DDR_0_DRAM_MODE_3_GDDR5M_WCK23_INVERT_DEFAULT 0x00000000
-#define BCHP_MEMC_DDR_0_DRAM_MODE_3_GDDR5M_WCK23_INVERT_ENABLE 1
-#define BCHP_MEMC_DDR_0_DRAM_MODE_3_GDDR5M_WCK23_INVERT_DISABLE 0
-
-/* MEMC_DDR_0 :: DRAM_MODE_3 :: GDDR5M :: WCK01_INVERT [02:02] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_3_GDDR5M_WCK01_INVERT_MASK 0x00000004
-#define BCHP_MEMC_DDR_0_DRAM_MODE_3_GDDR5M_WCK01_INVERT_SHIFT 2
-#define BCHP_MEMC_DDR_0_DRAM_MODE_3_GDDR5M_WCK01_INVERT_DEFAULT 0x00000000
-#define BCHP_MEMC_DDR_0_DRAM_MODE_3_GDDR5M_WCK01_INVERT_ENABLE 1
-#define BCHP_MEMC_DDR_0_DRAM_MODE_3_GDDR5M_WCK01_INVERT_DISABLE 0
-
-/* MEMC_DDR_0 :: DRAM_MODE_3 :: GDDR5M :: SELF_REFRESH [01:00] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_3_GDDR5M_SELF_REFRESH_MASK 0x00000003
-#define BCHP_MEMC_DDR_0_DRAM_MODE_3_GDDR5M_SELF_REFRESH_SHIFT 0
-#define BCHP_MEMC_DDR_0_DRAM_MODE_3_GDDR5M_SELF_REFRESH_DEFAULT 0x00000000
-
-/* union - case GDDR5 [12:00] */
-/* MEMC_DDR_0 :: DRAM_MODE_3 :: GDDR5 :: unused_1 [12:12] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_3_GDDR5_unused_1_MASK 0x00001000
-#define BCHP_MEMC_DDR_0_DRAM_MODE_3_GDDR5_unused_1_SHIFT 12
-#define BCHP_MEMC_DDR_0_DRAM_MODE_3_GDDR5_unused_1_DEFAULT 0x00000000
-
-/* MEMC_DDR_0 :: DRAM_MODE_3 :: GDDR5 :: BANK_GROUPS [11:10] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_3_GDDR5_BANK_GROUPS_MASK 0x00000c00
-#define BCHP_MEMC_DDR_0_DRAM_MODE_3_GDDR5_BANK_GROUPS_SHIFT 10
-#define BCHP_MEMC_DDR_0_DRAM_MODE_3_GDDR5_BANK_GROUPS_DEFAULT 0x00000000
-
-/* MEMC_DDR_0 :: DRAM_MODE_3 :: GDDR5 :: WCK_TERM [09:08] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_3_GDDR5_WCK_TERM_MASK 0x00000300
-#define BCHP_MEMC_DDR_0_DRAM_MODE_3_GDDR5_WCK_TERM_SHIFT 8
-#define BCHP_MEMC_DDR_0_DRAM_MODE_3_GDDR5_WCK_TERM_DEFAULT 0x00000000
-
-/* MEMC_DDR_0 :: DRAM_MODE_3 :: GDDR5 :: DRAM_INFO [07:06] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_3_GDDR5_DRAM_INFO_MASK 0x000000c0
-#define BCHP_MEMC_DDR_0_DRAM_MODE_3_GDDR5_DRAM_INFO_SHIFT 6
-#define BCHP_MEMC_DDR_0_DRAM_MODE_3_GDDR5_DRAM_INFO_DEFAULT 0x00000000
-
-/* MEMC_DDR_0 :: DRAM_MODE_3 :: GDDR5 :: RDQS_MODE [05:05] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_3_GDDR5_RDQS_MODE_MASK 0x00000020
-#define BCHP_MEMC_DDR_0_DRAM_MODE_3_GDDR5_RDQS_MODE_SHIFT 5
-#define BCHP_MEMC_DDR_0_DRAM_MODE_3_GDDR5_RDQS_MODE_DEFAULT 0x00000000
-#define BCHP_MEMC_DDR_0_DRAM_MODE_3_GDDR5_RDQS_MODE_ENABLE 1
-#define BCHP_MEMC_DDR_0_DRAM_MODE_3_GDDR5_RDQS_MODE_DISABLE 0
-
-/* MEMC_DDR_0 :: DRAM_MODE_3 :: GDDR5 :: WCK2CK_TRAIN [04:04] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_3_GDDR5_WCK2CK_TRAIN_MASK 0x00000010
-#define BCHP_MEMC_DDR_0_DRAM_MODE_3_GDDR5_WCK2CK_TRAIN_SHIFT 4
-#define BCHP_MEMC_DDR_0_DRAM_MODE_3_GDDR5_WCK2CK_TRAIN_DEFAULT 0x00000000
-#define BCHP_MEMC_DDR_0_DRAM_MODE_3_GDDR5_WCK2CK_TRAIN_ENABLE 1
-#define BCHP_MEMC_DDR_0_DRAM_MODE_3_GDDR5_WCK2CK_TRAIN_DISABLE 0
-
-/* MEMC_DDR_0 :: DRAM_MODE_3 :: GDDR5 :: WCK23_INVERT [03:03] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_3_GDDR5_WCK23_INVERT_MASK 0x00000008
-#define BCHP_MEMC_DDR_0_DRAM_MODE_3_GDDR5_WCK23_INVERT_SHIFT 3
-#define BCHP_MEMC_DDR_0_DRAM_MODE_3_GDDR5_WCK23_INVERT_DEFAULT 0x00000000
-#define BCHP_MEMC_DDR_0_DRAM_MODE_3_GDDR5_WCK23_INVERT_ENABLE 1
-#define BCHP_MEMC_DDR_0_DRAM_MODE_3_GDDR5_WCK23_INVERT_DISABLE 0
-
-/* MEMC_DDR_0 :: DRAM_MODE_3 :: GDDR5 :: WCK01_INVERT [02:02] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_3_GDDR5_WCK01_INVERT_MASK 0x00000004
-#define BCHP_MEMC_DDR_0_DRAM_MODE_3_GDDR5_WCK01_INVERT_SHIFT 2
-#define BCHP_MEMC_DDR_0_DRAM_MODE_3_GDDR5_WCK01_INVERT_DEFAULT 0x00000000
-#define BCHP_MEMC_DDR_0_DRAM_MODE_3_GDDR5_WCK01_INVERT_ENABLE 1
-#define BCHP_MEMC_DDR_0_DRAM_MODE_3_GDDR5_WCK01_INVERT_DISABLE 0
-
-/* MEMC_DDR_0 :: DRAM_MODE_3 :: GDDR5 :: SELF_REFRESH [01:00] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_3_GDDR5_SELF_REFRESH_MASK 0x00000003
-#define BCHP_MEMC_DDR_0_DRAM_MODE_3_GDDR5_SELF_REFRESH_SHIFT 0
-#define BCHP_MEMC_DDR_0_DRAM_MODE_3_GDDR5_SELF_REFRESH_DEFAULT 0x00000000
-
-/* union - case Others [12:00] */
-/* MEMC_DDR_0 :: DRAM_MODE_3 :: Others :: unused_1 [12:00] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_3_Others_unused_1_MASK 0x00001fff
-#define BCHP_MEMC_DDR_0_DRAM_MODE_3_Others_unused_1_SHIFT 0
-#define BCHP_MEMC_DDR_0_DRAM_MODE_3_Others_unused_1_DEFAULT 0x00000000
-
-/***************************************************************************
- *DRAM_MODE_4 - Dram Mode Register 4
- ***************************************************************************/
-/* MEMC_DDR_0 :: DRAM_MODE_4 :: reserved0 [31:16] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_4_reserved0_MASK 0xffff0000
-#define BCHP_MEMC_DDR_0_DRAM_MODE_4_reserved0_SHIFT 16
-
-/* MEMC_DDR_0 :: DRAM_MODE_4 :: unused_0 [15:13] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_4_unused_0_MASK 0x0000e000
-#define BCHP_MEMC_DDR_0_DRAM_MODE_4_unused_0_SHIFT 13
-#define BCHP_MEMC_DDR_0_DRAM_MODE_4_unused_0_DEFAULT 0x00000000
-
-/* union - case DDR4 [12:00] */
-/* MEMC_DDR_0 :: DRAM_MODE_4 :: DDR4 :: WR_PREAMBLE [12:12] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_4_DDR4_WR_PREAMBLE_MASK 0x00001000
-#define BCHP_MEMC_DDR_0_DRAM_MODE_4_DDR4_WR_PREAMBLE_SHIFT 12
-#define BCHP_MEMC_DDR_0_DRAM_MODE_4_DDR4_WR_PREAMBLE_DEFAULT 0x00000000
-
-/* MEMC_DDR_0 :: DRAM_MODE_4 :: DDR4 :: RD_PREAMBLE [11:11] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_4_DDR4_RD_PREAMBLE_MASK 0x00000800
-#define BCHP_MEMC_DDR_0_DRAM_MODE_4_DDR4_RD_PREAMBLE_SHIFT 11
-#define BCHP_MEMC_DDR_0_DRAM_MODE_4_DDR4_RD_PREAMBLE_DEFAULT 0x00000000
-
-/* MEMC_DDR_0 :: DRAM_MODE_4 :: DDR4 :: RD_PREAMBLE_TRAINING [10:10] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_4_DDR4_RD_PREAMBLE_TRAINING_MASK 0x00000400
-#define BCHP_MEMC_DDR_0_DRAM_MODE_4_DDR4_RD_PREAMBLE_TRAINING_SHIFT 10
-#define BCHP_MEMC_DDR_0_DRAM_MODE_4_DDR4_RD_PREAMBLE_TRAINING_DEFAULT 0x00000000
-#define BCHP_MEMC_DDR_0_DRAM_MODE_4_DDR4_RD_PREAMBLE_TRAINING_ENABLE 1
-#define BCHP_MEMC_DDR_0_DRAM_MODE_4_DDR4_RD_PREAMBLE_TRAINING_DISABLE 0
-
-/* MEMC_DDR_0 :: DRAM_MODE_4 :: DDR4 :: SELF_REFRESH_ABORT [09:09] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_4_DDR4_SELF_REFRESH_ABORT_MASK 0x00000200
-#define BCHP_MEMC_DDR_0_DRAM_MODE_4_DDR4_SELF_REFRESH_ABORT_SHIFT 9
-#define BCHP_MEMC_DDR_0_DRAM_MODE_4_DDR4_SELF_REFRESH_ABORT_DEFAULT 0x00000000
-#define BCHP_MEMC_DDR_0_DRAM_MODE_4_DDR4_SELF_REFRESH_ABORT_ENABLE 1
-#define BCHP_MEMC_DDR_0_DRAM_MODE_4_DDR4_SELF_REFRESH_ABORT_DISABLE 0
-
-/* MEMC_DDR_0 :: DRAM_MODE_4 :: DDR4 :: CMD_ADDR_LATENCY [08:06] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_4_DDR4_CMD_ADDR_LATENCY_MASK 0x000001c0
-#define BCHP_MEMC_DDR_0_DRAM_MODE_4_DDR4_CMD_ADDR_LATENCY_SHIFT 6
-#define BCHP_MEMC_DDR_0_DRAM_MODE_4_DDR4_CMD_ADDR_LATENCY_DEFAULT 0x00000000
-
-/* MEMC_DDR_0 :: DRAM_MODE_4 :: DDR4 :: CMD_ADDR_PARITY [05:05] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_4_DDR4_CMD_ADDR_PARITY_MASK 0x00000020
-#define BCHP_MEMC_DDR_0_DRAM_MODE_4_DDR4_CMD_ADDR_PARITY_SHIFT 5
-#define BCHP_MEMC_DDR_0_DRAM_MODE_4_DDR4_CMD_ADDR_PARITY_DEFAULT 0x00000000
-#define BCHP_MEMC_DDR_0_DRAM_MODE_4_DDR4_CMD_ADDR_PARITY_ENABLE 1
-#define BCHP_MEMC_DDR_0_DRAM_MODE_4_DDR4_CMD_ADDR_PARITY_DISABLE 0
-
-/* MEMC_DDR_0 :: DRAM_MODE_4 :: DDR4 :: VREF_MONITOR [04:04] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_4_DDR4_VREF_MONITOR_MASK 0x00000010
-#define BCHP_MEMC_DDR_0_DRAM_MODE_4_DDR4_VREF_MONITOR_SHIFT 4
-#define BCHP_MEMC_DDR_0_DRAM_MODE_4_DDR4_VREF_MONITOR_DEFAULT 0x00000000
-#define BCHP_MEMC_DDR_0_DRAM_MODE_4_DDR4_VREF_MONITOR_ENABLE 1
-#define BCHP_MEMC_DDR_0_DRAM_MODE_4_DDR4_VREF_MONITOR_DISABLE 0
-
-/* MEMC_DDR_0 :: DRAM_MODE_4 :: DDR4 :: TEMP_CONTROLLED_REFRESH [03:03] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_4_DDR4_TEMP_CONTROLLED_REFRESH_MASK 0x00000008
-#define BCHP_MEMC_DDR_0_DRAM_MODE_4_DDR4_TEMP_CONTROLLED_REFRESH_SHIFT 3
-#define BCHP_MEMC_DDR_0_DRAM_MODE_4_DDR4_TEMP_CONTROLLED_REFRESH_DEFAULT 0x00000000
-#define BCHP_MEMC_DDR_0_DRAM_MODE_4_DDR4_TEMP_CONTROLLED_REFRESH_ENABLE 1
-#define BCHP_MEMC_DDR_0_DRAM_MODE_4_DDR4_TEMP_CONTROLLED_REFRESH_DISABLE 0
-
-/* MEMC_DDR_0 :: DRAM_MODE_4 :: DDR4 :: TEMP_CONTROLLED_REFRESH_RANGE [02:02] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_4_DDR4_TEMP_CONTROLLED_REFRESH_RANGE_MASK 0x00000004
-#define BCHP_MEMC_DDR_0_DRAM_MODE_4_DDR4_TEMP_CONTROLLED_REFRESH_RANGE_SHIFT 2
-#define BCHP_MEMC_DDR_0_DRAM_MODE_4_DDR4_TEMP_CONTROLLED_REFRESH_RANGE_DEFAULT 0x00000000
-
-/* MEMC_DDR_0 :: DRAM_MODE_4 :: DDR4 :: MAXIMUM_POWER_SAVINGS [01:01] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_4_DDR4_MAXIMUM_POWER_SAVINGS_MASK 0x00000002
-#define BCHP_MEMC_DDR_0_DRAM_MODE_4_DDR4_MAXIMUM_POWER_SAVINGS_SHIFT 1
-#define BCHP_MEMC_DDR_0_DRAM_MODE_4_DDR4_MAXIMUM_POWER_SAVINGS_DEFAULT 0x00000000
-#define BCHP_MEMC_DDR_0_DRAM_MODE_4_DDR4_MAXIMUM_POWER_SAVINGS_ENABLE 1
-#define BCHP_MEMC_DDR_0_DRAM_MODE_4_DDR4_MAXIMUM_POWER_SAVINGS_DISABLE 0
-
-/* MEMC_DDR_0 :: DRAM_MODE_4 :: DDR4 :: unused_1 [00:00] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_4_DDR4_unused_1_MASK 0x00000001
-#define BCHP_MEMC_DDR_0_DRAM_MODE_4_DDR4_unused_1_SHIFT 0
-#define BCHP_MEMC_DDR_0_DRAM_MODE_4_DDR4_unused_1_DEFAULT 0x00000000
-
-/* union - case GDDR5M [12:00] */
-/* MEMC_DDR_0 :: DRAM_MODE_4 :: GDDR5M :: unused_1 [12:12] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_4_GDDR5M_unused_1_MASK 0x00001000
-#define BCHP_MEMC_DDR_0_DRAM_MODE_4_GDDR5M_unused_1_SHIFT 12
-#define BCHP_MEMC_DDR_0_DRAM_MODE_4_GDDR5M_unused_1_DEFAULT 0x00000000
-
-/* MEMC_DDR_0 :: DRAM_MODE_4 :: GDDR5M :: EDC_HOLD_INVERT [11:11] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_4_GDDR5M_EDC_HOLD_INVERT_MASK 0x00000800
-#define BCHP_MEMC_DDR_0_DRAM_MODE_4_GDDR5M_EDC_HOLD_INVERT_SHIFT 11
-#define BCHP_MEMC_DDR_0_DRAM_MODE_4_GDDR5M_EDC_HOLD_INVERT_DEFAULT 0x00000000
-
-/* MEMC_DDR_0 :: DRAM_MODE_4 :: GDDR5M :: WR_CRC [10:10] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_4_GDDR5M_WR_CRC_MASK 0x00000400
-#define BCHP_MEMC_DDR_0_DRAM_MODE_4_GDDR5M_WR_CRC_SHIFT 10
-#define BCHP_MEMC_DDR_0_DRAM_MODE_4_GDDR5M_WR_CRC_DEFAULT 0x00000001
-#define BCHP_MEMC_DDR_0_DRAM_MODE_4_GDDR5M_WR_CRC_ENABLE 0
-#define BCHP_MEMC_DDR_0_DRAM_MODE_4_GDDR5M_WR_CRC_DISABLE 1
-
-/* MEMC_DDR_0 :: DRAM_MODE_4 :: GDDR5M :: RD_CRC [09:09] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_4_GDDR5M_RD_CRC_MASK 0x00000200
-#define BCHP_MEMC_DDR_0_DRAM_MODE_4_GDDR5M_RD_CRC_SHIFT 9
-#define BCHP_MEMC_DDR_0_DRAM_MODE_4_GDDR5M_RD_CRC_DEFAULT 0x00000001
-#define BCHP_MEMC_DDR_0_DRAM_MODE_4_GDDR5M_RD_CRC_ENABLE 0
-#define BCHP_MEMC_DDR_0_DRAM_MODE_4_GDDR5M_RD_CRC_DISABLE 1
-
-/* MEMC_DDR_0 :: DRAM_MODE_4 :: GDDR5M :: CRC_RD_LATENCY [08:07] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_4_GDDR5M_CRC_RD_LATENCY_MASK 0x00000180
-#define BCHP_MEMC_DDR_0_DRAM_MODE_4_GDDR5M_CRC_RD_LATENCY_SHIFT 7
-#define BCHP_MEMC_DDR_0_DRAM_MODE_4_GDDR5M_CRC_RD_LATENCY_DEFAULT 0x00000000
-
-/* MEMC_DDR_0 :: DRAM_MODE_4 :: GDDR5M :: CRC_WR_LATENCY [06:04] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_4_GDDR5M_CRC_WR_LATENCY_MASK 0x00000070
-#define BCHP_MEMC_DDR_0_DRAM_MODE_4_GDDR5M_CRC_WR_LATENCY_SHIFT 4
-#define BCHP_MEMC_DDR_0_DRAM_MODE_4_GDDR5M_CRC_WR_LATENCY_DEFAULT 0x00000000
-
-/* MEMC_DDR_0 :: DRAM_MODE_4 :: GDDR5M :: EDC_HOLD_PATTERN [03:00] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_4_GDDR5M_EDC_HOLD_PATTERN_MASK 0x0000000f
-#define BCHP_MEMC_DDR_0_DRAM_MODE_4_GDDR5M_EDC_HOLD_PATTERN_SHIFT 0
-#define BCHP_MEMC_DDR_0_DRAM_MODE_4_GDDR5M_EDC_HOLD_PATTERN_DEFAULT 0x00000000
-
-/* union - case GDDR5 [12:00] */
-/* MEMC_DDR_0 :: DRAM_MODE_4 :: GDDR5 :: unused_1 [12:12] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_4_GDDR5_unused_1_MASK 0x00001000
-#define BCHP_MEMC_DDR_0_DRAM_MODE_4_GDDR5_unused_1_SHIFT 12
-#define BCHP_MEMC_DDR_0_DRAM_MODE_4_GDDR5_unused_1_DEFAULT 0x00000000
-
-/* MEMC_DDR_0 :: DRAM_MODE_4 :: GDDR5 :: EDC_HOLD_INVERT [11:11] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_4_GDDR5_EDC_HOLD_INVERT_MASK 0x00000800
-#define BCHP_MEMC_DDR_0_DRAM_MODE_4_GDDR5_EDC_HOLD_INVERT_SHIFT 11
-#define BCHP_MEMC_DDR_0_DRAM_MODE_4_GDDR5_EDC_HOLD_INVERT_DEFAULT 0x00000000
-
-/* MEMC_DDR_0 :: DRAM_MODE_4 :: GDDR5 :: WR_CRC [10:10] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_4_GDDR5_WR_CRC_MASK 0x00000400
-#define BCHP_MEMC_DDR_0_DRAM_MODE_4_GDDR5_WR_CRC_SHIFT 10
-#define BCHP_MEMC_DDR_0_DRAM_MODE_4_GDDR5_WR_CRC_DEFAULT 0x00000001
-#define BCHP_MEMC_DDR_0_DRAM_MODE_4_GDDR5_WR_CRC_ENABLE 0
-#define BCHP_MEMC_DDR_0_DRAM_MODE_4_GDDR5_WR_CRC_DISABLE 1
-
-/* MEMC_DDR_0 :: DRAM_MODE_4 :: GDDR5 :: RD_CRC [09:09] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_4_GDDR5_RD_CRC_MASK 0x00000200
-#define BCHP_MEMC_DDR_0_DRAM_MODE_4_GDDR5_RD_CRC_SHIFT 9
-#define BCHP_MEMC_DDR_0_DRAM_MODE_4_GDDR5_RD_CRC_DEFAULT 0x00000001
-#define BCHP_MEMC_DDR_0_DRAM_MODE_4_GDDR5_RD_CRC_ENABLE 0
-#define BCHP_MEMC_DDR_0_DRAM_MODE_4_GDDR5_RD_CRC_DISABLE 1
-
-/* MEMC_DDR_0 :: DRAM_MODE_4 :: GDDR5 :: CRC_RD_LATENCY [08:07] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_4_GDDR5_CRC_RD_LATENCY_MASK 0x00000180
-#define BCHP_MEMC_DDR_0_DRAM_MODE_4_GDDR5_CRC_RD_LATENCY_SHIFT 7
-#define BCHP_MEMC_DDR_0_DRAM_MODE_4_GDDR5_CRC_RD_LATENCY_DEFAULT 0x00000000
-
-/* MEMC_DDR_0 :: DRAM_MODE_4 :: GDDR5 :: CRC_WR_LATENCY [06:04] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_4_GDDR5_CRC_WR_LATENCY_MASK 0x00000070
-#define BCHP_MEMC_DDR_0_DRAM_MODE_4_GDDR5_CRC_WR_LATENCY_SHIFT 4
-#define BCHP_MEMC_DDR_0_DRAM_MODE_4_GDDR5_CRC_WR_LATENCY_DEFAULT 0x00000000
-
-/* MEMC_DDR_0 :: DRAM_MODE_4 :: GDDR5 :: EDC_HOLD_PATTERN [03:00] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_4_GDDR5_EDC_HOLD_PATTERN_MASK 0x0000000f
-#define BCHP_MEMC_DDR_0_DRAM_MODE_4_GDDR5_EDC_HOLD_PATTERN_SHIFT 0
-#define BCHP_MEMC_DDR_0_DRAM_MODE_4_GDDR5_EDC_HOLD_PATTERN_DEFAULT 0x00000000
-
-/* union - case Others [12:00] */
-/* MEMC_DDR_0 :: DRAM_MODE_4 :: Others :: unused_1 [12:00] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_4_Others_unused_1_MASK 0x00001fff
-#define BCHP_MEMC_DDR_0_DRAM_MODE_4_Others_unused_1_SHIFT 0
-#define BCHP_MEMC_DDR_0_DRAM_MODE_4_Others_unused_1_DEFAULT 0x00000000
-
-/***************************************************************************
- *DRAM_MODE_5 - Dram Mode Register 5
- ***************************************************************************/
-/* MEMC_DDR_0 :: DRAM_MODE_5 :: reserved0 [31:16] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_5_reserved0_MASK 0xffff0000
-#define BCHP_MEMC_DDR_0_DRAM_MODE_5_reserved0_SHIFT 16
-
-/* MEMC_DDR_0 :: DRAM_MODE_5 :: unused_0 [15:13] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_5_unused_0_MASK 0x0000e000
-#define BCHP_MEMC_DDR_0_DRAM_MODE_5_unused_0_SHIFT 13
-#define BCHP_MEMC_DDR_0_DRAM_MODE_5_unused_0_DEFAULT 0x00000000
-
-/* union - case DDR4 [12:00] */
-/* MEMC_DDR_0 :: DRAM_MODE_5 :: DDR4 :: RD_DBI [12:12] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_5_DDR4_RD_DBI_MASK 0x00001000
-#define BCHP_MEMC_DDR_0_DRAM_MODE_5_DDR4_RD_DBI_SHIFT 12
-#define BCHP_MEMC_DDR_0_DRAM_MODE_5_DDR4_RD_DBI_DEFAULT 0x00000000
-#define BCHP_MEMC_DDR_0_DRAM_MODE_5_DDR4_RD_DBI_ENABLE 1
-#define BCHP_MEMC_DDR_0_DRAM_MODE_5_DDR4_RD_DBI_DISABLE 0
-
-/* MEMC_DDR_0 :: DRAM_MODE_5 :: DDR4 :: WR_DBI [11:11] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_5_DDR4_WR_DBI_MASK 0x00000800
-#define BCHP_MEMC_DDR_0_DRAM_MODE_5_DDR4_WR_DBI_SHIFT 11
-#define BCHP_MEMC_DDR_0_DRAM_MODE_5_DDR4_WR_DBI_DEFAULT 0x00000000
-#define BCHP_MEMC_DDR_0_DRAM_MODE_5_DDR4_WR_DBI_ENABLE 1
-#define BCHP_MEMC_DDR_0_DRAM_MODE_5_DDR4_WR_DBI_DISABLE 0
-
-/* MEMC_DDR_0 :: DRAM_MODE_5 :: DDR4 :: DM [10:10] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_5_DDR4_DM_MASK 0x00000400
-#define BCHP_MEMC_DDR_0_DRAM_MODE_5_DDR4_DM_SHIFT 10
-#define BCHP_MEMC_DDR_0_DRAM_MODE_5_DDR4_DM_DEFAULT 0x00000000
-#define BCHP_MEMC_DDR_0_DRAM_MODE_5_DDR4_DM_ENABLE 1
-#define BCHP_MEMC_DDR_0_DRAM_MODE_5_DDR4_DM_DISABLE 0
-
-/* MEMC_DDR_0 :: DRAM_MODE_5 :: DDR4 :: unused_1 [09:09] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_5_DDR4_unused_1_MASK 0x00000200
-#define BCHP_MEMC_DDR_0_DRAM_MODE_5_DDR4_unused_1_SHIFT 9
-#define BCHP_MEMC_DDR_0_DRAM_MODE_5_DDR4_unused_1_DEFAULT 0x00000000
-
-/* MEMC_DDR_0 :: DRAM_MODE_5 :: DDR4 :: RTT_PARK [08:06] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_5_DDR4_RTT_PARK_MASK 0x000001c0
-#define BCHP_MEMC_DDR_0_DRAM_MODE_5_DDR4_RTT_PARK_SHIFT 6
-#define BCHP_MEMC_DDR_0_DRAM_MODE_5_DDR4_RTT_PARK_DEFAULT 0x00000000
-
-/* MEMC_DDR_0 :: DRAM_MODE_5 :: DDR4 :: unused_2 [05:05] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_5_DDR4_unused_2_MASK 0x00000020
-#define BCHP_MEMC_DDR_0_DRAM_MODE_5_DDR4_unused_2_SHIFT 5
-#define BCHP_MEMC_DDR_0_DRAM_MODE_5_DDR4_unused_2_DEFAULT 0x00000000
-
-/* MEMC_DDR_0 :: DRAM_MODE_5 :: DDR4 :: CMD_ADDR_PARITY_ERROR [04:04] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_5_DDR4_CMD_ADDR_PARITY_ERROR_MASK 0x00000010
-#define BCHP_MEMC_DDR_0_DRAM_MODE_5_DDR4_CMD_ADDR_PARITY_ERROR_SHIFT 4
-#define BCHP_MEMC_DDR_0_DRAM_MODE_5_DDR4_CMD_ADDR_PARITY_ERROR_DEFAULT 0x00000000
-
-/* MEMC_DDR_0 :: DRAM_MODE_5 :: DDR4 :: CRC_ERROR [03:03] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_5_DDR4_CRC_ERROR_MASK 0x00000008
-#define BCHP_MEMC_DDR_0_DRAM_MODE_5_DDR4_CRC_ERROR_SHIFT 3
-#define BCHP_MEMC_DDR_0_DRAM_MODE_5_DDR4_CRC_ERROR_DEFAULT 0x00000000
-
-/* MEMC_DDR_0 :: DRAM_MODE_5 :: DDR4 :: CMD_ADDR_PARITY_LATENCY [02:00] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_5_DDR4_CMD_ADDR_PARITY_LATENCY_MASK 0x00000007
-#define BCHP_MEMC_DDR_0_DRAM_MODE_5_DDR4_CMD_ADDR_PARITY_LATENCY_SHIFT 0
-#define BCHP_MEMC_DDR_0_DRAM_MODE_5_DDR4_CMD_ADDR_PARITY_LATENCY_DEFAULT 0x00000000
-
-/* union - case GDDR5M [12:00] */
-/* MEMC_DDR_0 :: DRAM_MODE_5 :: GDDR5M :: unused_1 [12:12] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_5_GDDR5M_unused_1_MASK 0x00001000
-#define BCHP_MEMC_DDR_0_DRAM_MODE_5_GDDR5M_unused_1_SHIFT 12
-#define BCHP_MEMC_DDR_0_DRAM_MODE_5_GDDR5M_unused_1_DEFAULT 0x00000000
-
-/* MEMC_DDR_0 :: DRAM_MODE_5 :: GDDR5M :: RAS [11:06] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_5_GDDR5M_RAS_MASK 0x00000fc0
-#define BCHP_MEMC_DDR_0_DRAM_MODE_5_GDDR5M_RAS_SHIFT 6
-#define BCHP_MEMC_DDR_0_DRAM_MODE_5_GDDR5M_RAS_DEFAULT 0x00000000
-
-/* MEMC_DDR_0 :: DRAM_MODE_5 :: GDDR5M :: unused_2 [05:03] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_5_GDDR5M_unused_2_MASK 0x00000038
-#define BCHP_MEMC_DDR_0_DRAM_MODE_5_GDDR5M_unused_2_SHIFT 3
-#define BCHP_MEMC_DDR_0_DRAM_MODE_5_GDDR5M_unused_2_DEFAULT 0x00000000
-
-/* MEMC_DDR_0 :: DRAM_MODE_5 :: GDDR5M :: LP3 [02:02] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_5_GDDR5M_LP3_MASK 0x00000004
-#define BCHP_MEMC_DDR_0_DRAM_MODE_5_GDDR5M_LP3_SHIFT 2
-#define BCHP_MEMC_DDR_0_DRAM_MODE_5_GDDR5M_LP3_DEFAULT 0x00000000
-#define BCHP_MEMC_DDR_0_DRAM_MODE_5_GDDR5M_LP3_ENABLE 1
-#define BCHP_MEMC_DDR_0_DRAM_MODE_5_GDDR5M_LP3_DISABLE 0
-
-/* MEMC_DDR_0 :: DRAM_MODE_5 :: GDDR5M :: LP2 [01:01] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_5_GDDR5M_LP2_MASK 0x00000002
-#define BCHP_MEMC_DDR_0_DRAM_MODE_5_GDDR5M_LP2_SHIFT 1
-#define BCHP_MEMC_DDR_0_DRAM_MODE_5_GDDR5M_LP2_DEFAULT 0x00000000
-#define BCHP_MEMC_DDR_0_DRAM_MODE_5_GDDR5M_LP2_ENABLE 1
-#define BCHP_MEMC_DDR_0_DRAM_MODE_5_GDDR5M_LP2_DISABLE 0
-
-/* MEMC_DDR_0 :: DRAM_MODE_5 :: GDDR5M :: LP1 [00:00] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_5_GDDR5M_LP1_MASK 0x00000001
-#define BCHP_MEMC_DDR_0_DRAM_MODE_5_GDDR5M_LP1_SHIFT 0
-#define BCHP_MEMC_DDR_0_DRAM_MODE_5_GDDR5M_LP1_DEFAULT 0x00000000
-#define BCHP_MEMC_DDR_0_DRAM_MODE_5_GDDR5M_LP1_ENABLE 1
-#define BCHP_MEMC_DDR_0_DRAM_MODE_5_GDDR5M_LP1_DISABLE 0
-
-/* union - case GDDR5 [12:00] */
-/* MEMC_DDR_0 :: DRAM_MODE_5 :: GDDR5 :: unused_1 [12:12] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_5_GDDR5_unused_1_MASK 0x00001000
-#define BCHP_MEMC_DDR_0_DRAM_MODE_5_GDDR5_unused_1_SHIFT 12
-#define BCHP_MEMC_DDR_0_DRAM_MODE_5_GDDR5_unused_1_DEFAULT 0x00000000
-
-/* MEMC_DDR_0 :: DRAM_MODE_5 :: GDDR5 :: RAS [11:06] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_5_GDDR5_RAS_MASK 0x00000fc0
-#define BCHP_MEMC_DDR_0_DRAM_MODE_5_GDDR5_RAS_SHIFT 6
-#define BCHP_MEMC_DDR_0_DRAM_MODE_5_GDDR5_RAS_DEFAULT 0x00000000
-
-/* MEMC_DDR_0 :: DRAM_MODE_5 :: GDDR5 :: PLL_DLL_BANDWIDTH [05:03] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_5_GDDR5_PLL_DLL_BANDWIDTH_MASK 0x00000038
-#define BCHP_MEMC_DDR_0_DRAM_MODE_5_GDDR5_PLL_DLL_BANDWIDTH_SHIFT 3
-#define BCHP_MEMC_DDR_0_DRAM_MODE_5_GDDR5_PLL_DLL_BANDWIDTH_DEFAULT 0x00000000
-
-/* MEMC_DDR_0 :: DRAM_MODE_5 :: GDDR5 :: LP3 [02:02] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_5_GDDR5_LP3_MASK 0x00000004
-#define BCHP_MEMC_DDR_0_DRAM_MODE_5_GDDR5_LP3_SHIFT 2
-#define BCHP_MEMC_DDR_0_DRAM_MODE_5_GDDR5_LP3_DEFAULT 0x00000000
-#define BCHP_MEMC_DDR_0_DRAM_MODE_5_GDDR5_LP3_ENABLE 1
-#define BCHP_MEMC_DDR_0_DRAM_MODE_5_GDDR5_LP3_DISABLE 0
-
-/* MEMC_DDR_0 :: DRAM_MODE_5 :: GDDR5 :: LP2 [01:01] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_5_GDDR5_LP2_MASK 0x00000002
-#define BCHP_MEMC_DDR_0_DRAM_MODE_5_GDDR5_LP2_SHIFT 1
-#define BCHP_MEMC_DDR_0_DRAM_MODE_5_GDDR5_LP2_DEFAULT 0x00000000
-#define BCHP_MEMC_DDR_0_DRAM_MODE_5_GDDR5_LP2_ENABLE 1
-#define BCHP_MEMC_DDR_0_DRAM_MODE_5_GDDR5_LP2_DISABLE 0
-
-/* MEMC_DDR_0 :: DRAM_MODE_5 :: GDDR5 :: LP1 [00:00] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_5_GDDR5_LP1_MASK 0x00000001
-#define BCHP_MEMC_DDR_0_DRAM_MODE_5_GDDR5_LP1_SHIFT 0
-#define BCHP_MEMC_DDR_0_DRAM_MODE_5_GDDR5_LP1_DEFAULT 0x00000000
-#define BCHP_MEMC_DDR_0_DRAM_MODE_5_GDDR5_LP1_ENABLE 1
-#define BCHP_MEMC_DDR_0_DRAM_MODE_5_GDDR5_LP1_DISABLE 0
-
-/* union - case Others [12:00] */
-/* MEMC_DDR_0 :: DRAM_MODE_5 :: Others :: unused_1 [12:00] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_5_Others_unused_1_MASK 0x00001fff
-#define BCHP_MEMC_DDR_0_DRAM_MODE_5_Others_unused_1_SHIFT 0
-#define BCHP_MEMC_DDR_0_DRAM_MODE_5_Others_unused_1_DEFAULT 0x00000000
-
-/***************************************************************************
- *DRAM_MODE_6 - Dram Mode Register 6
- ***************************************************************************/
-/* MEMC_DDR_0 :: DRAM_MODE_6 :: reserved0 [31:16] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_6_reserved0_MASK 0xffff0000
-#define BCHP_MEMC_DDR_0_DRAM_MODE_6_reserved0_SHIFT 16
-
-/* MEMC_DDR_0 :: DRAM_MODE_6 :: unused_0 [15:13] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_6_unused_0_MASK 0x0000e000
-#define BCHP_MEMC_DDR_0_DRAM_MODE_6_unused_0_SHIFT 13
-#define BCHP_MEMC_DDR_0_DRAM_MODE_6_unused_0_DEFAULT 0x00000000
-
-/* union - case DDR4 [12:00] */
-/* MEMC_DDR_0 :: DRAM_MODE_6 :: DDR4 :: unused_1 [12:07] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_6_DDR4_unused_1_MASK 0x00001f80
-#define BCHP_MEMC_DDR_0_DRAM_MODE_6_DDR4_unused_1_SHIFT 7
-#define BCHP_MEMC_DDR_0_DRAM_MODE_6_DDR4_unused_1_DEFAULT 0x00000000
-
-/* MEMC_DDR_0 :: DRAM_MODE_6 :: DDR4 :: VREF_TRAINING_RANGE [06:06] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_6_DDR4_VREF_TRAINING_RANGE_MASK 0x00000040
-#define BCHP_MEMC_DDR_0_DRAM_MODE_6_DDR4_VREF_TRAINING_RANGE_SHIFT 6
-#define BCHP_MEMC_DDR_0_DRAM_MODE_6_DDR4_VREF_TRAINING_RANGE_DEFAULT 0x00000000
-
-/* MEMC_DDR_0 :: DRAM_MODE_6 :: DDR4 :: VREF_TRAINING [05:00] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_6_DDR4_VREF_TRAINING_MASK 0x0000003f
-#define BCHP_MEMC_DDR_0_DRAM_MODE_6_DDR4_VREF_TRAINING_SHIFT 0
-#define BCHP_MEMC_DDR_0_DRAM_MODE_6_DDR4_VREF_TRAINING_DEFAULT 0x00000000
-
-/* union - case GDDR5M [12:00] */
-/* MEMC_DDR_0 :: DRAM_MODE_6 :: GDDR5M :: unused_1 [12:12] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_6_GDDR5M_unused_1_MASK 0x00001000
-#define BCHP_MEMC_DDR_0_DRAM_MODE_6_GDDR5M_unused_1_SHIFT 12
-#define BCHP_MEMC_DDR_0_DRAM_MODE_6_GDDR5M_unused_1_DEFAULT 0x00000000
-
-/* MEMC_DDR_0 :: DRAM_MODE_6 :: GDDR5M :: VREFD_OFFSET_01 [11:08] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_6_GDDR5M_VREFD_OFFSET_01_MASK 0x00000f00
-#define BCHP_MEMC_DDR_0_DRAM_MODE_6_GDDR5M_VREFD_OFFSET_01_SHIFT 8
-#define BCHP_MEMC_DDR_0_DRAM_MODE_6_GDDR5M_VREFD_OFFSET_01_DEFAULT 0x00000000
-
-/* MEMC_DDR_0 :: DRAM_MODE_6 :: GDDR5M :: VREFD_OFFSET_23 [07:04] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_6_GDDR5M_VREFD_OFFSET_23_MASK 0x000000f0
-#define BCHP_MEMC_DDR_0_DRAM_MODE_6_GDDR5M_VREFD_OFFSET_23_SHIFT 4
-#define BCHP_MEMC_DDR_0_DRAM_MODE_6_GDDR5M_VREFD_OFFSET_23_DEFAULT 0x00000000
-
-/* MEMC_DDR_0 :: DRAM_MODE_6 :: GDDR5M :: unused_2 [03:01] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_6_GDDR5M_unused_2_MASK 0x0000000e
-#define BCHP_MEMC_DDR_0_DRAM_MODE_6_GDDR5M_unused_2_SHIFT 1
-#define BCHP_MEMC_DDR_0_DRAM_MODE_6_GDDR5M_unused_2_DEFAULT 0x00000000
-
-/* MEMC_DDR_0 :: DRAM_MODE_6 :: GDDR5M :: WCK2CK_ALIGN [00:00] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_6_GDDR5M_WCK2CK_ALIGN_MASK 0x00000001
-#define BCHP_MEMC_DDR_0_DRAM_MODE_6_GDDR5M_WCK2CK_ALIGN_SHIFT 0
-#define BCHP_MEMC_DDR_0_DRAM_MODE_6_GDDR5M_WCK2CK_ALIGN_DEFAULT 0x00000000
-
-/* union - case GDDR5 [12:00] */
-/* MEMC_DDR_0 :: DRAM_MODE_6 :: GDDR5 :: unused_1 [12:12] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_6_GDDR5_unused_1_MASK 0x00001000
-#define BCHP_MEMC_DDR_0_DRAM_MODE_6_GDDR5_unused_1_SHIFT 12
-#define BCHP_MEMC_DDR_0_DRAM_MODE_6_GDDR5_unused_1_DEFAULT 0x00000000
-
-/* MEMC_DDR_0 :: DRAM_MODE_6 :: GDDR5 :: VREFD_OFFSET_01 [11:08] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_6_GDDR5_VREFD_OFFSET_01_MASK 0x00000f00
-#define BCHP_MEMC_DDR_0_DRAM_MODE_6_GDDR5_VREFD_OFFSET_01_SHIFT 8
-#define BCHP_MEMC_DDR_0_DRAM_MODE_6_GDDR5_VREFD_OFFSET_01_DEFAULT 0x00000000
-
-/* MEMC_DDR_0 :: DRAM_MODE_6 :: GDDR5 :: VREFD_OFFSET_23 [07:04] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_6_GDDR5_VREFD_OFFSET_23_MASK 0x000000f0
-#define BCHP_MEMC_DDR_0_DRAM_MODE_6_GDDR5_VREFD_OFFSET_23_SHIFT 4
-#define BCHP_MEMC_DDR_0_DRAM_MODE_6_GDDR5_VREFD_OFFSET_23_DEFAULT 0x00000000
-
-/* MEMC_DDR_0 :: DRAM_MODE_6 :: GDDR5 :: VREFD [03:03] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_6_GDDR5_VREFD_MASK 0x00000008
-#define BCHP_MEMC_DDR_0_DRAM_MODE_6_GDDR5_VREFD_SHIFT 3
-#define BCHP_MEMC_DDR_0_DRAM_MODE_6_GDDR5_VREFD_DEFAULT 0x00000000
-
-/* MEMC_DDR_0 :: DRAM_MODE_6 :: GDDR5 :: AUTO_VREFD [02:02] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_6_GDDR5_AUTO_VREFD_MASK 0x00000004
-#define BCHP_MEMC_DDR_0_DRAM_MODE_6_GDDR5_AUTO_VREFD_SHIFT 2
-#define BCHP_MEMC_DDR_0_DRAM_MODE_6_GDDR5_AUTO_VREFD_DEFAULT 0x00000000
-
-/* MEMC_DDR_0 :: DRAM_MODE_6 :: GDDR5 :: VREFD_MERGE [01:01] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_6_GDDR5_VREFD_MERGE_MASK 0x00000002
-#define BCHP_MEMC_DDR_0_DRAM_MODE_6_GDDR5_VREFD_MERGE_SHIFT 1
-#define BCHP_MEMC_DDR_0_DRAM_MODE_6_GDDR5_VREFD_MERGE_DEFAULT 0x00000000
-
-/* MEMC_DDR_0 :: DRAM_MODE_6 :: GDDR5 :: WCK2CK_ALIGN [00:00] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_6_GDDR5_WCK2CK_ALIGN_MASK 0x00000001
-#define BCHP_MEMC_DDR_0_DRAM_MODE_6_GDDR5_WCK2CK_ALIGN_SHIFT 0
-#define BCHP_MEMC_DDR_0_DRAM_MODE_6_GDDR5_WCK2CK_ALIGN_DEFAULT 0x00000000
-
-/* union - case Others [12:00] */
-/* MEMC_DDR_0 :: DRAM_MODE_6 :: Others :: unused_1 [12:00] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_6_Others_unused_1_MASK 0x00001fff
-#define BCHP_MEMC_DDR_0_DRAM_MODE_6_Others_unused_1_SHIFT 0
-#define BCHP_MEMC_DDR_0_DRAM_MODE_6_Others_unused_1_DEFAULT 0x00000000
-
-/***************************************************************************
- *DRAM_MODE_7 - Dram Mode Register 7
- ***************************************************************************/
-/* MEMC_DDR_0 :: DRAM_MODE_7 :: reserved0 [31:16] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_7_reserved0_MASK 0xffff0000
-#define BCHP_MEMC_DDR_0_DRAM_MODE_7_reserved0_SHIFT 16
-
-/* MEMC_DDR_0 :: DRAM_MODE_7 :: unused_0 [15:13] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_7_unused_0_MASK 0x0000e000
-#define BCHP_MEMC_DDR_0_DRAM_MODE_7_unused_0_SHIFT 13
-#define BCHP_MEMC_DDR_0_DRAM_MODE_7_unused_0_DEFAULT 0x00000000
-
-/* union - case GDDR5M [12:00] */
-/* MEMC_DDR_0 :: DRAM_MODE_7 :: GDDR5M :: unused_1 [12:12] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_7_GDDR5M_unused_1_MASK 0x00001000
-#define BCHP_MEMC_DDR_0_DRAM_MODE_7_GDDR5M_unused_1_SHIFT 12
-#define BCHP_MEMC_DDR_0_DRAM_MODE_7_GDDR5M_unused_1_DEFAULT 0x00000000
-
-/* MEMC_DDR_0 :: DRAM_MODE_7 :: GDDR5M :: DDC [11:10] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_7_GDDR5M_DDC_MASK 0x00000c00
-#define BCHP_MEMC_DDR_0_DRAM_MODE_7_GDDR5M_DDC_SHIFT 10
-#define BCHP_MEMC_DDR_0_DRAM_MODE_7_GDDR5M_DDC_DEFAULT 0x00000000
-
-/* MEMC_DDR_0 :: DRAM_MODE_7 :: GDDR5M :: VDD_RANGE [09:08] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_7_GDDR5M_VDD_RANGE_MASK 0x00000300
-#define BCHP_MEMC_DDR_0_DRAM_MODE_7_GDDR5M_VDD_RANGE_SHIFT 8
-#define BCHP_MEMC_DDR_0_DRAM_MODE_7_GDDR5M_VDD_RANGE_DEFAULT 0x00000000
-
-/* MEMC_DDR_0 :: DRAM_MODE_7 :: GDDR5M :: HALF_VREFD [07:07] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_7_GDDR5M_HALF_VREFD_MASK 0x00000080
-#define BCHP_MEMC_DDR_0_DRAM_MODE_7_GDDR5M_HALF_VREFD_SHIFT 7
-#define BCHP_MEMC_DDR_0_DRAM_MODE_7_GDDR5M_HALF_VREFD_DEFAULT 0x00000000
-
-/* MEMC_DDR_0 :: DRAM_MODE_7 :: GDDR5M :: TEMP_SENSE [06:06] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_7_GDDR5M_TEMP_SENSE_MASK 0x00000040
-#define BCHP_MEMC_DDR_0_DRAM_MODE_7_GDDR5M_TEMP_SENSE_SHIFT 6
-#define BCHP_MEMC_DDR_0_DRAM_MODE_7_GDDR5M_TEMP_SENSE_DEFAULT 0x00000000
-#define BCHP_MEMC_DDR_0_DRAM_MODE_7_GDDR5M_TEMP_SENSE_ENABLE 1
-#define BCHP_MEMC_DDR_0_DRAM_MODE_7_GDDR5M_TEMP_SENSE_DISABLE 0
-
-/* MEMC_DDR_0 :: DRAM_MODE_7 :: GDDR5M :: DQ_PREAMBLE [05:05] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_7_GDDR5M_DQ_PREAMBLE_MASK 0x00000020
-#define BCHP_MEMC_DDR_0_DRAM_MODE_7_GDDR5M_DQ_PREAMBLE_SHIFT 5
-#define BCHP_MEMC_DDR_0_DRAM_MODE_7_GDDR5M_DQ_PREAMBLE_DEFAULT 0x00000000
-#define BCHP_MEMC_DDR_0_DRAM_MODE_7_GDDR5M_DQ_PREAMBLE_ENABLE 1
-#define BCHP_MEMC_DDR_0_DRAM_MODE_7_GDDR5M_DQ_PREAMBLE_DISABLE 0
-
-/* MEMC_DDR_0 :: DRAM_MODE_7 :: GDDR5M :: WCK2CK_AUTO_SYNC [04:04] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_7_GDDR5M_WCK2CK_AUTO_SYNC_MASK 0x00000010
-#define BCHP_MEMC_DDR_0_DRAM_MODE_7_GDDR5M_WCK2CK_AUTO_SYNC_SHIFT 4
-#define BCHP_MEMC_DDR_0_DRAM_MODE_7_GDDR5M_WCK2CK_AUTO_SYNC_DEFAULT 0x00000000
-#define BCHP_MEMC_DDR_0_DRAM_MODE_7_GDDR5M_WCK2CK_AUTO_SYNC_ENABLE 1
-#define BCHP_MEMC_DDR_0_DRAM_MODE_7_GDDR5M_WCK2CK_AUTO_SYNC_DISABLE 0
-
-/* MEMC_DDR_0 :: DRAM_MODE_7 :: GDDR5M :: LOW_FREQ [03:03] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_7_GDDR5M_LOW_FREQ_MASK 0x00000008
-#define BCHP_MEMC_DDR_0_DRAM_MODE_7_GDDR5M_LOW_FREQ_SHIFT 3
-#define BCHP_MEMC_DDR_0_DRAM_MODE_7_GDDR5M_LOW_FREQ_DEFAULT 0x00000000
-#define BCHP_MEMC_DDR_0_DRAM_MODE_7_GDDR5M_LOW_FREQ_ENABLE 1
-#define BCHP_MEMC_DDR_0_DRAM_MODE_7_GDDR5M_LOW_FREQ_DISABLE 0
-
-/* MEMC_DDR_0 :: DRAM_MODE_7 :: GDDR5M :: unused_2 [02:00] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_7_GDDR5M_unused_2_MASK 0x00000007
-#define BCHP_MEMC_DDR_0_DRAM_MODE_7_GDDR5M_unused_2_SHIFT 0
-#define BCHP_MEMC_DDR_0_DRAM_MODE_7_GDDR5M_unused_2_DEFAULT 0x00000000
-
-/* union - case GDDR5 [12:00] */
-/* MEMC_DDR_0 :: DRAM_MODE_7 :: GDDR5 :: unused_1 [12:12] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_7_GDDR5_unused_1_MASK 0x00001000
-#define BCHP_MEMC_DDR_0_DRAM_MODE_7_GDDR5_unused_1_SHIFT 12
-#define BCHP_MEMC_DDR_0_DRAM_MODE_7_GDDR5_unused_1_DEFAULT 0x00000000
-
-/* MEMC_DDR_0 :: DRAM_MODE_7 :: GDDR5 :: DDC [11:10] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_7_GDDR5_DDC_MASK 0x00000c00
-#define BCHP_MEMC_DDR_0_DRAM_MODE_7_GDDR5_DDC_SHIFT 10
-#define BCHP_MEMC_DDR_0_DRAM_MODE_7_GDDR5_DDC_DEFAULT 0x00000000
-
-/* MEMC_DDR_0 :: DRAM_MODE_7 :: GDDR5 :: VDD_RANGE [09:08] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_7_GDDR5_VDD_RANGE_MASK 0x00000300
-#define BCHP_MEMC_DDR_0_DRAM_MODE_7_GDDR5_VDD_RANGE_SHIFT 8
-#define BCHP_MEMC_DDR_0_DRAM_MODE_7_GDDR5_VDD_RANGE_DEFAULT 0x00000000
-
-/* MEMC_DDR_0 :: DRAM_MODE_7 :: GDDR5 :: HALF_VREFD [07:07] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_7_GDDR5_HALF_VREFD_MASK 0x00000080
-#define BCHP_MEMC_DDR_0_DRAM_MODE_7_GDDR5_HALF_VREFD_SHIFT 7
-#define BCHP_MEMC_DDR_0_DRAM_MODE_7_GDDR5_HALF_VREFD_DEFAULT 0x00000000
-
-/* MEMC_DDR_0 :: DRAM_MODE_7 :: GDDR5 :: TEMP_SENSE [06:06] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_7_GDDR5_TEMP_SENSE_MASK 0x00000040
-#define BCHP_MEMC_DDR_0_DRAM_MODE_7_GDDR5_TEMP_SENSE_SHIFT 6
-#define BCHP_MEMC_DDR_0_DRAM_MODE_7_GDDR5_TEMP_SENSE_DEFAULT 0x00000000
-#define BCHP_MEMC_DDR_0_DRAM_MODE_7_GDDR5_TEMP_SENSE_ENABLE 1
-#define BCHP_MEMC_DDR_0_DRAM_MODE_7_GDDR5_TEMP_SENSE_DISABLE 0
-
-/* MEMC_DDR_0 :: DRAM_MODE_7 :: GDDR5 :: DQ_PREAMBLE [05:05] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_7_GDDR5_DQ_PREAMBLE_MASK 0x00000020
-#define BCHP_MEMC_DDR_0_DRAM_MODE_7_GDDR5_DQ_PREAMBLE_SHIFT 5
-#define BCHP_MEMC_DDR_0_DRAM_MODE_7_GDDR5_DQ_PREAMBLE_DEFAULT 0x00000000
-#define BCHP_MEMC_DDR_0_DRAM_MODE_7_GDDR5_DQ_PREAMBLE_ENABLE 1
-#define BCHP_MEMC_DDR_0_DRAM_MODE_7_GDDR5_DQ_PREAMBLE_DISABLE 0
-
-/* MEMC_DDR_0 :: DRAM_MODE_7 :: GDDR5 :: WCK2CK_AUTO_SYNC [04:04] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_7_GDDR5_WCK2CK_AUTO_SYNC_MASK 0x00000010
-#define BCHP_MEMC_DDR_0_DRAM_MODE_7_GDDR5_WCK2CK_AUTO_SYNC_SHIFT 4
-#define BCHP_MEMC_DDR_0_DRAM_MODE_7_GDDR5_WCK2CK_AUTO_SYNC_DEFAULT 0x00000000
-#define BCHP_MEMC_DDR_0_DRAM_MODE_7_GDDR5_WCK2CK_AUTO_SYNC_ENABLE 1
-#define BCHP_MEMC_DDR_0_DRAM_MODE_7_GDDR5_WCK2CK_AUTO_SYNC_DISABLE 0
-
-/* MEMC_DDR_0 :: DRAM_MODE_7 :: GDDR5 :: LOW_FREQ [03:03] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_7_GDDR5_LOW_FREQ_MASK 0x00000008
-#define BCHP_MEMC_DDR_0_DRAM_MODE_7_GDDR5_LOW_FREQ_SHIFT 3
-#define BCHP_MEMC_DDR_0_DRAM_MODE_7_GDDR5_LOW_FREQ_DEFAULT 0x00000000
-#define BCHP_MEMC_DDR_0_DRAM_MODE_7_GDDR5_LOW_FREQ_ENABLE 1
-#define BCHP_MEMC_DDR_0_DRAM_MODE_7_GDDR5_LOW_FREQ_DISABLE 0
-
-/* MEMC_DDR_0 :: DRAM_MODE_7 :: GDDR5 :: PLL_DELAY_COMP [02:02] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_7_GDDR5_PLL_DELAY_COMP_MASK 0x00000004
-#define BCHP_MEMC_DDR_0_DRAM_MODE_7_GDDR5_PLL_DELAY_COMP_SHIFT 2
-#define BCHP_MEMC_DDR_0_DRAM_MODE_7_GDDR5_PLL_DELAY_COMP_DEFAULT 0x00000000
-#define BCHP_MEMC_DDR_0_DRAM_MODE_7_GDDR5_PLL_DELAY_COMP_ENABLE 1
-#define BCHP_MEMC_DDR_0_DRAM_MODE_7_GDDR5_PLL_DELAY_COMP_DISABLE 0
-
-/* MEMC_DDR_0 :: DRAM_MODE_7 :: GDDR5 :: PLL_FAST_LOCK [01:01] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_7_GDDR5_PLL_FAST_LOCK_MASK 0x00000002
-#define BCHP_MEMC_DDR_0_DRAM_MODE_7_GDDR5_PLL_FAST_LOCK_SHIFT 1
-#define BCHP_MEMC_DDR_0_DRAM_MODE_7_GDDR5_PLL_FAST_LOCK_DEFAULT 0x00000000
-#define BCHP_MEMC_DDR_0_DRAM_MODE_7_GDDR5_PLL_FAST_LOCK_ENABLE 1
-#define BCHP_MEMC_DDR_0_DRAM_MODE_7_GDDR5_PLL_FAST_LOCK_DISABLE 0
-
-/* MEMC_DDR_0 :: DRAM_MODE_7 :: GDDR5 :: PLL_STANDBY [00:00] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_7_GDDR5_PLL_STANDBY_MASK 0x00000001
-#define BCHP_MEMC_DDR_0_DRAM_MODE_7_GDDR5_PLL_STANDBY_SHIFT 0
-#define BCHP_MEMC_DDR_0_DRAM_MODE_7_GDDR5_PLL_STANDBY_DEFAULT 0x00000000
-#define BCHP_MEMC_DDR_0_DRAM_MODE_7_GDDR5_PLL_STANDBY_ENABLE 1
-#define BCHP_MEMC_DDR_0_DRAM_MODE_7_GDDR5_PLL_STANDBY_DISABLE 0
-
-/* union - case Others [12:00] */
-/* MEMC_DDR_0 :: DRAM_MODE_7 :: Others :: unused_1 [12:00] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_7_Others_unused_1_MASK 0x00001fff
-#define BCHP_MEMC_DDR_0_DRAM_MODE_7_Others_unused_1_SHIFT 0
-#define BCHP_MEMC_DDR_0_DRAM_MODE_7_Others_unused_1_DEFAULT 0x00000000
-
-/***************************************************************************
- *DRAM_MODE_8 - Dram Mode Register 8
- ***************************************************************************/
-/* MEMC_DDR_0 :: DRAM_MODE_8 :: reserved0 [31:16] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_8_reserved0_MASK 0xffff0000
-#define BCHP_MEMC_DDR_0_DRAM_MODE_8_reserved0_SHIFT 16
-
-/* MEMC_DDR_0 :: DRAM_MODE_8 :: unused_0 [15:13] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_8_unused_0_MASK 0x0000e000
-#define BCHP_MEMC_DDR_0_DRAM_MODE_8_unused_0_SHIFT 13
-#define BCHP_MEMC_DDR_0_DRAM_MODE_8_unused_0_DEFAULT 0x00000000
-
-/* union - case GDDR5 [12:00] */
-/* MEMC_DDR_0 :: DRAM_MODE_8 :: GDDR5 :: unused_1 [12:02] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_8_GDDR5_unused_1_MASK 0x00001ffc
-#define BCHP_MEMC_DDR_0_DRAM_MODE_8_GDDR5_unused_1_SHIFT 2
-#define BCHP_MEMC_DDR_0_DRAM_MODE_8_GDDR5_unused_1_DEFAULT 0x00000000
-
-/* MEMC_DDR_0 :: DRAM_MODE_8 :: GDDR5 :: WR_EHF [01:01] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_8_GDDR5_WR_EHF_MASK 0x00000002
-#define BCHP_MEMC_DDR_0_DRAM_MODE_8_GDDR5_WR_EHF_SHIFT 1
-#define BCHP_MEMC_DDR_0_DRAM_MODE_8_GDDR5_WR_EHF_DEFAULT 0x00000000
-
-/* MEMC_DDR_0 :: DRAM_MODE_8 :: GDDR5 :: CL_EHF [00:00] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_8_GDDR5_CL_EHF_MASK 0x00000001
-#define BCHP_MEMC_DDR_0_DRAM_MODE_8_GDDR5_CL_EHF_SHIFT 0
-#define BCHP_MEMC_DDR_0_DRAM_MODE_8_GDDR5_CL_EHF_DEFAULT 0x00000000
-
-/* union - case Others [12:00] */
-/* MEMC_DDR_0 :: DRAM_MODE_8 :: Others :: unused_1 [12:00] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_8_Others_unused_1_MASK 0x00001fff
-#define BCHP_MEMC_DDR_0_DRAM_MODE_8_Others_unused_1_SHIFT 0
-#define BCHP_MEMC_DDR_0_DRAM_MODE_8_Others_unused_1_DEFAULT 0x00000000
-
-/***************************************************************************
- *DRAM_MODE_15 - Dram Mode Register 15
- ***************************************************************************/
-/* MEMC_DDR_0 :: DRAM_MODE_15 :: reserved0 [31:16] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_15_reserved0_MASK 0xffff0000
-#define BCHP_MEMC_DDR_0_DRAM_MODE_15_reserved0_SHIFT 16
-
-/* MEMC_DDR_0 :: DRAM_MODE_15 :: unused_0 [15:13] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_15_unused_0_MASK 0x0000e000
-#define BCHP_MEMC_DDR_0_DRAM_MODE_15_unused_0_SHIFT 13
-#define BCHP_MEMC_DDR_0_DRAM_MODE_15_unused_0_DEFAULT 0x00000000
-
-/* union - case GDDR5M [12:00] */
-/* MEMC_DDR_0 :: DRAM_MODE_15 :: GDDR5M :: unused_1 [12:12] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_15_GDDR5M_unused_1_MASK 0x00001000
-#define BCHP_MEMC_DDR_0_DRAM_MODE_15_GDDR5M_unused_1_SHIFT 12
-#define BCHP_MEMC_DDR_0_DRAM_MODE_15_GDDR5M_unused_1_DEFAULT 0x00000000
-
-/* MEMC_DDR_0 :: DRAM_MODE_15 :: GDDR5M :: ADDR_TRAINING [11:10] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_15_GDDR5M_ADDR_TRAINING_MASK 0x00000c00
-#define BCHP_MEMC_DDR_0_DRAM_MODE_15_GDDR5M_ADDR_TRAINING_SHIFT 10
-#define BCHP_MEMC_DDR_0_DRAM_MODE_15_GDDR5M_ADDR_TRAINING_DEFAULT 0x00000000
-
-/* MEMC_DDR_0 :: DRAM_MODE_15 :: GDDR5M :: MRE_MF1 [09:09] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_15_GDDR5M_MRE_MF1_MASK 0x00000200
-#define BCHP_MEMC_DDR_0_DRAM_MODE_15_GDDR5M_MRE_MF1_SHIFT 9
-#define BCHP_MEMC_DDR_0_DRAM_MODE_15_GDDR5M_MRE_MF1_DEFAULT 0x00000000
-#define BCHP_MEMC_DDR_0_DRAM_MODE_15_GDDR5M_MRE_MF1_ENABLE 0
-#define BCHP_MEMC_DDR_0_DRAM_MODE_15_GDDR5M_MRE_MF1_DISABLE 1
-
-/* MEMC_DDR_0 :: DRAM_MODE_15 :: GDDR5M :: MRE_MF2 [08:08] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_15_GDDR5M_MRE_MF2_MASK 0x00000100
-#define BCHP_MEMC_DDR_0_DRAM_MODE_15_GDDR5M_MRE_MF2_SHIFT 8
-#define BCHP_MEMC_DDR_0_DRAM_MODE_15_GDDR5M_MRE_MF2_DEFAULT 0x00000000
-#define BCHP_MEMC_DDR_0_DRAM_MODE_15_GDDR5M_MRE_MF2_ENABLE 0
-#define BCHP_MEMC_DDR_0_DRAM_MODE_15_GDDR5M_MRE_MF2_DISABLE 1
-
-/* MEMC_DDR_0 :: DRAM_MODE_15 :: GDDR5M :: unused_2 [07:00] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_15_GDDR5M_unused_2_MASK 0x000000ff
-#define BCHP_MEMC_DDR_0_DRAM_MODE_15_GDDR5M_unused_2_SHIFT 0
-#define BCHP_MEMC_DDR_0_DRAM_MODE_15_GDDR5M_unused_2_DEFAULT 0x00000000
-
-/* union - case GDDR5 [12:00] */
-/* MEMC_DDR_0 :: DRAM_MODE_15 :: GDDR5 :: unused_1 [12:11] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_15_GDDR5_unused_1_MASK 0x00001800
-#define BCHP_MEMC_DDR_0_DRAM_MODE_15_GDDR5_unused_1_SHIFT 11
-#define BCHP_MEMC_DDR_0_DRAM_MODE_15_GDDR5_unused_1_DEFAULT 0x00000000
-
-/* MEMC_DDR_0 :: DRAM_MODE_15 :: GDDR5 :: ADDR_TRAINING [10:10] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_15_GDDR5_ADDR_TRAINING_MASK 0x00000400
-#define BCHP_MEMC_DDR_0_DRAM_MODE_15_GDDR5_ADDR_TRAINING_SHIFT 10
-#define BCHP_MEMC_DDR_0_DRAM_MODE_15_GDDR5_ADDR_TRAINING_DEFAULT 0x00000000
-#define BCHP_MEMC_DDR_0_DRAM_MODE_15_GDDR5_ADDR_TRAINING_ENABLE 1
-#define BCHP_MEMC_DDR_0_DRAM_MODE_15_GDDR5_ADDR_TRAINING_DISABLE 0
-
-/* MEMC_DDR_0 :: DRAM_MODE_15 :: GDDR5 :: MRE_MF1 [09:09] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_15_GDDR5_MRE_MF1_MASK 0x00000200
-#define BCHP_MEMC_DDR_0_DRAM_MODE_15_GDDR5_MRE_MF1_SHIFT 9
-#define BCHP_MEMC_DDR_0_DRAM_MODE_15_GDDR5_MRE_MF1_DEFAULT 0x00000000
-#define BCHP_MEMC_DDR_0_DRAM_MODE_15_GDDR5_MRE_MF1_ENABLE 0
-#define BCHP_MEMC_DDR_0_DRAM_MODE_15_GDDR5_MRE_MF1_DISABLE 1
-
-/* MEMC_DDR_0 :: DRAM_MODE_15 :: GDDR5 :: MRE_MF2 [08:08] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_15_GDDR5_MRE_MF2_MASK 0x00000100
-#define BCHP_MEMC_DDR_0_DRAM_MODE_15_GDDR5_MRE_MF2_SHIFT 8
-#define BCHP_MEMC_DDR_0_DRAM_MODE_15_GDDR5_MRE_MF2_DEFAULT 0x00000000
-#define BCHP_MEMC_DDR_0_DRAM_MODE_15_GDDR5_MRE_MF2_ENABLE 0
-#define BCHP_MEMC_DDR_0_DRAM_MODE_15_GDDR5_MRE_MF2_DISABLE 1
-
-/* MEMC_DDR_0 :: DRAM_MODE_15 :: GDDR5 :: unused_2 [07:00] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_15_GDDR5_unused_2_MASK 0x000000ff
-#define BCHP_MEMC_DDR_0_DRAM_MODE_15_GDDR5_unused_2_SHIFT 0
-#define BCHP_MEMC_DDR_0_DRAM_MODE_15_GDDR5_unused_2_DEFAULT 0x00000000
-
-/* union - case Others [12:00] */
-/* MEMC_DDR_0 :: DRAM_MODE_15 :: Others :: unused_1 [12:00] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_15_Others_unused_1_MASK 0x00001fff
-#define BCHP_MEMC_DDR_0_DRAM_MODE_15_Others_unused_1_SHIFT 0
-#define BCHP_MEMC_DDR_0_DRAM_MODE_15_Others_unused_1_DEFAULT 0x00000000
-
-/***************************************************************************
- *PPD_CONFIG - Precharge power down mode configuration register
- ***************************************************************************/
-/* MEMC_DDR_0 :: PPD_CONFIG :: reserved0 [31:15] */
-#define BCHP_MEMC_DDR_0_PPD_CONFIG_reserved0_MASK 0xffff8000
-#define BCHP_MEMC_DDR_0_PPD_CONFIG_reserved0_SHIFT 15
-
-/* MEMC_DDR_0 :: PPD_CONFIG :: FORCE_PPD_EXIT [14:14] */
-#define BCHP_MEMC_DDR_0_PPD_CONFIG_FORCE_PPD_EXIT_MASK 0x00004000
-#define BCHP_MEMC_DDR_0_PPD_CONFIG_FORCE_PPD_EXIT_SHIFT 14
-#define BCHP_MEMC_DDR_0_PPD_CONFIG_FORCE_PPD_EXIT_DEFAULT 0x00000000
-
-/* MEMC_DDR_0 :: PPD_CONFIG :: PPD_FORCE [13:13] */
-#define BCHP_MEMC_DDR_0_PPD_CONFIG_PPD_FORCE_MASK 0x00002000
-#define BCHP_MEMC_DDR_0_PPD_CONFIG_PPD_FORCE_SHIFT 13
-#define BCHP_MEMC_DDR_0_PPD_CONFIG_PPD_FORCE_DEFAULT 0x00000000
-
-/* MEMC_DDR_0 :: PPD_CONFIG :: PPD_EN [12:12] */
-#define BCHP_MEMC_DDR_0_PPD_CONFIG_PPD_EN_MASK 0x00001000
-#define BCHP_MEMC_DDR_0_PPD_CONFIG_PPD_EN_SHIFT 12
-#define BCHP_MEMC_DDR_0_PPD_CONFIG_PPD_EN_DEFAULT 0x00000000
-
-/* MEMC_DDR_0 :: PPD_CONFIG :: INACT_COUNT [11:00] */
-#define BCHP_MEMC_DDR_0_PPD_CONFIG_INACT_COUNT_MASK 0x00000fff
-#define BCHP_MEMC_DDR_0_PPD_CONFIG_INACT_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_PPD_CONFIG_INACT_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *SRPD_CONFIG - Self-refresh power down mode configuration register
- ***************************************************************************/
-/* MEMC_DDR_0 :: SRPD_CONFIG :: reserved0 [31:18] */
-#define BCHP_MEMC_DDR_0_SRPD_CONFIG_reserved0_MASK 0xfffc0000
-#define BCHP_MEMC_DDR_0_SRPD_CONFIG_reserved0_SHIFT 18
-
-/* MEMC_DDR_0 :: SRPD_CONFIG :: FORCE_SRPD_EXIT [17:17] */
-#define BCHP_MEMC_DDR_0_SRPD_CONFIG_FORCE_SRPD_EXIT_MASK 0x00020000
-#define BCHP_MEMC_DDR_0_SRPD_CONFIG_FORCE_SRPD_EXIT_SHIFT 17
-#define BCHP_MEMC_DDR_0_SRPD_CONFIG_FORCE_SRPD_EXIT_DEFAULT 0x00000000
-
-/* MEMC_DDR_0 :: SRPD_CONFIG :: SRPD_EN [16:16] */
-#define BCHP_MEMC_DDR_0_SRPD_CONFIG_SRPD_EN_MASK 0x00010000
-#define BCHP_MEMC_DDR_0_SRPD_CONFIG_SRPD_EN_SHIFT 16
-#define BCHP_MEMC_DDR_0_SRPD_CONFIG_SRPD_EN_DEFAULT 0x00000000
-
-/* MEMC_DDR_0 :: SRPD_CONFIG :: INACT_COUNT [15:00] */
-#define BCHP_MEMC_DDR_0_SRPD_CONFIG_INACT_COUNT_MASK 0x0000ffff
-#define BCHP_MEMC_DDR_0_SRPD_CONFIG_INACT_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_SRPD_CONFIG_INACT_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *SSPD_CMD - Software standby power down mode
- ***************************************************************************/
-/* MEMC_DDR_0 :: SSPD_CMD :: reserved0 [31:01] */
-#define BCHP_MEMC_DDR_0_SSPD_CMD_reserved0_MASK 0xfffffffe
-#define BCHP_MEMC_DDR_0_SSPD_CMD_reserved0_SHIFT 1
-
-/* MEMC_DDR_0 :: SSPD_CMD :: SSPD [00:00] */
-#define BCHP_MEMC_DDR_0_SSPD_CMD_SSPD_MASK 0x00000001
-#define BCHP_MEMC_DDR_0_SSPD_CMD_SSPD_SHIFT 0
-#define BCHP_MEMC_DDR_0_SSPD_CMD_SSPD_DEFAULT 0x00000000
-
-/***************************************************************************
- *POWER_DOWN_STATUS - Power down status
- ***************************************************************************/
-/* MEMC_DDR_0 :: POWER_DOWN_STATUS :: reserved0 [31:03] */
-#define BCHP_MEMC_DDR_0_POWER_DOWN_STATUS_reserved0_MASK 0xfffffff8
-#define BCHP_MEMC_DDR_0_POWER_DOWN_STATUS_reserved0_SHIFT 3
-
-/* MEMC_DDR_0 :: POWER_DOWN_STATUS :: SSPD [02:02] */
-#define BCHP_MEMC_DDR_0_POWER_DOWN_STATUS_SSPD_MASK 0x00000004
-#define BCHP_MEMC_DDR_0_POWER_DOWN_STATUS_SSPD_SHIFT 2
-#define BCHP_MEMC_DDR_0_POWER_DOWN_STATUS_SSPD_DEFAULT 0x00000000
-
-/* MEMC_DDR_0 :: POWER_DOWN_STATUS :: SRPD [01:01] */
-#define BCHP_MEMC_DDR_0_POWER_DOWN_STATUS_SRPD_MASK 0x00000002
-#define BCHP_MEMC_DDR_0_POWER_DOWN_STATUS_SRPD_SHIFT 1
-#define BCHP_MEMC_DDR_0_POWER_DOWN_STATUS_SRPD_DEFAULT 0x00000000
-
-/* MEMC_DDR_0 :: POWER_DOWN_STATUS :: PPD [00:00] */
-#define BCHP_MEMC_DDR_0_POWER_DOWN_STATUS_PPD_MASK 0x00000001
-#define BCHP_MEMC_DDR_0_POWER_DOWN_STATUS_PPD_SHIFT 0
-#define BCHP_MEMC_DDR_0_POWER_DOWN_STATUS_PPD_DEFAULT 0x00000000
-
-/***************************************************************************
- *WARM_BOOT - Warm boot control registers
- ***************************************************************************/
-/* MEMC_DDR_0 :: WARM_BOOT :: reserved0 [31:01] */
-#define BCHP_MEMC_DDR_0_WARM_BOOT_reserved0_MASK 0xfffffffe
-#define BCHP_MEMC_DDR_0_WARM_BOOT_reserved0_SHIFT 1
-
-/* MEMC_DDR_0 :: WARM_BOOT :: WARM_BOOT [00:00] */
-#define BCHP_MEMC_DDR_0_WARM_BOOT_WARM_BOOT_MASK 0x00000001
-#define BCHP_MEMC_DDR_0_WARM_BOOT_WARM_BOOT_SHIFT 0
-#define BCHP_MEMC_DDR_0_WARM_BOOT_WARM_BOOT_DEFAULT 0x00000000
-
-/***************************************************************************
- *DRAM_TIMING_0 - DDR-SDRAM Timing Register 0
- ***************************************************************************/
-/* MEMC_DDR_0 :: DRAM_TIMING_0 :: TRRD_NOP [31:24] */
-#define BCHP_MEMC_DDR_0_DRAM_TIMING_0_TRRD_NOP_MASK 0xff000000
-#define BCHP_MEMC_DDR_0_DRAM_TIMING_0_TRRD_NOP_SHIFT 24
-#define BCHP_MEMC_DDR_0_DRAM_TIMING_0_TRRD_NOP_DEFAULT 0x00000006
-
-/* MEMC_DDR_0 :: DRAM_TIMING_0 :: TRCD_NOP [23:16] */
-#define BCHP_MEMC_DDR_0_DRAM_TIMING_0_TRCD_NOP_MASK 0x00ff0000
-#define BCHP_MEMC_DDR_0_DRAM_TIMING_0_TRCD_NOP_SHIFT 16
-#define BCHP_MEMC_DDR_0_DRAM_TIMING_0_TRCD_NOP_DEFAULT 0x00000008
-
-/* MEMC_DDR_0 :: DRAM_TIMING_0 :: TRP_NOP [15:08] */
-#define BCHP_MEMC_DDR_0_DRAM_TIMING_0_TRP_NOP_MASK 0x0000ff00
-#define BCHP_MEMC_DDR_0_DRAM_TIMING_0_TRP_NOP_SHIFT 8
-#define BCHP_MEMC_DDR_0_DRAM_TIMING_0_TRP_NOP_DEFAULT 0x00000008
-
-/* MEMC_DDR_0 :: DRAM_TIMING_0 :: TRAS_NOP [07:00] */
-#define BCHP_MEMC_DDR_0_DRAM_TIMING_0_TRAS_NOP_MASK 0x000000ff
-#define BCHP_MEMC_DDR_0_DRAM_TIMING_0_TRAS_NOP_SHIFT 0
-#define BCHP_MEMC_DDR_0_DRAM_TIMING_0_TRAS_NOP_DEFAULT 0x00000014
-
-/***************************************************************************
- *DRAM_TIMING_1 - DDR-SDRAM Timing Register 1
- ***************************************************************************/
-/* MEMC_DDR_0 :: DRAM_TIMING_1 :: reserved0 [31:28] */
-#define BCHP_MEMC_DDR_0_DRAM_TIMING_1_reserved0_MASK 0xf0000000
-#define BCHP_MEMC_DDR_0_DRAM_TIMING_1_reserved0_SHIFT 28
-
-/* MEMC_DDR_0 :: DRAM_TIMING_1 :: T32AW_NOP [27:16] */
-#define BCHP_MEMC_DDR_0_DRAM_TIMING_1_T32AW_NOP_MASK 0x0fff0000
-#define BCHP_MEMC_DDR_0_DRAM_TIMING_1_T32AW_NOP_SHIFT 16
-#define BCHP_MEMC_DDR_0_DRAM_TIMING_1_T32AW_NOP_DEFAULT 0x00000020
-
-/* MEMC_DDR_0 :: DRAM_TIMING_1 :: TFAW_NOP [15:08] */
-#define BCHP_MEMC_DDR_0_DRAM_TIMING_1_TFAW_NOP_MASK 0x0000ff00
-#define BCHP_MEMC_DDR_0_DRAM_TIMING_1_TFAW_NOP_SHIFT 8
-#define BCHP_MEMC_DDR_0_DRAM_TIMING_1_TFAW_NOP_DEFAULT 0x0000001b
-
-/* MEMC_DDR_0 :: DRAM_TIMING_1 :: TRTP_NOP [07:00] */
-#define BCHP_MEMC_DDR_0_DRAM_TIMING_1_TRTP_NOP_MASK 0x000000ff
-#define BCHP_MEMC_DDR_0_DRAM_TIMING_1_TRTP_NOP_SHIFT 0
-#define BCHP_MEMC_DDR_0_DRAM_TIMING_1_TRTP_NOP_DEFAULT 0x00000004
-
-/***************************************************************************
- *DRAM_TIMING_2 - Read to Write & write to read timing register
- ***************************************************************************/
-/* MEMC_DDR_0 :: DRAM_TIMING_2 :: TRRDL_NOP [31:24] */
-#define BCHP_MEMC_DDR_0_DRAM_TIMING_2_TRRDL_NOP_MASK 0xff000000
-#define BCHP_MEMC_DDR_0_DRAM_TIMING_2_TRRDL_NOP_SHIFT 24
-#define BCHP_MEMC_DDR_0_DRAM_TIMING_2_TRRDL_NOP_DEFAULT 0x00000006
-
-/* MEMC_DDR_0 :: DRAM_TIMING_2 :: WR2RDL_NOP [23:16] */
-#define BCHP_MEMC_DDR_0_DRAM_TIMING_2_WR2RDL_NOP_MASK 0x00ff0000
-#define BCHP_MEMC_DDR_0_DRAM_TIMING_2_WR2RDL_NOP_SHIFT 16
-#define BCHP_MEMC_DDR_0_DRAM_TIMING_2_WR2RDL_NOP_DEFAULT 0x0000000e
-
-/* MEMC_DDR_0 :: DRAM_TIMING_2 :: WR2RD_NOP [15:08] */
-#define BCHP_MEMC_DDR_0_DRAM_TIMING_2_WR2RD_NOP_MASK 0x0000ff00
-#define BCHP_MEMC_DDR_0_DRAM_TIMING_2_WR2RD_NOP_SHIFT 8
-#define BCHP_MEMC_DDR_0_DRAM_TIMING_2_WR2RD_NOP_DEFAULT 0x0000000e
-
-/* MEMC_DDR_0 :: DRAM_TIMING_2 :: RD2WR_NOP [07:00] */
-#define BCHP_MEMC_DDR_0_DRAM_TIMING_2_RD2WR_NOP_MASK 0x000000ff
-#define BCHP_MEMC_DDR_0_DRAM_TIMING_2_RD2WR_NOP_SHIFT 0
-#define BCHP_MEMC_DDR_0_DRAM_TIMING_2_RD2WR_NOP_DEFAULT 0x00000009
-
-/***************************************************************************
- *DRAM_TIMING_3 - DDR-SDRAM Timing Register 3
- ***************************************************************************/
-/* MEMC_DDR_0 :: DRAM_TIMING_3 :: reserved0 [31:24] */
-#define BCHP_MEMC_DDR_0_DRAM_TIMING_3_reserved0_MASK 0xff000000
-#define BCHP_MEMC_DDR_0_DRAM_TIMING_3_reserved0_SHIFT 24
-
-/* MEMC_DDR_0 :: DRAM_TIMING_3 :: CKENB_CKE_DELAY [23:19] */
-#define BCHP_MEMC_DDR_0_DRAM_TIMING_3_CKENB_CKE_DELAY_MASK 0x00f80000
-#define BCHP_MEMC_DDR_0_DRAM_TIMING_3_CKENB_CKE_DELAY_SHIFT 19
-#define BCHP_MEMC_DDR_0_DRAM_TIMING_3_CKENB_CKE_DELAY_DEFAULT 0x0000000c
-
-/* MEMC_DDR_0 :: DRAM_TIMING_3 :: POWERUP_CKE_DELAY [18:10] */
-#define BCHP_MEMC_DDR_0_DRAM_TIMING_3_POWERUP_CKE_DELAY_MASK 0x0007fc00
-#define BCHP_MEMC_DDR_0_DRAM_TIMING_3_POWERUP_CKE_DELAY_SHIFT 10
-#define BCHP_MEMC_DDR_0_DRAM_TIMING_3_POWERUP_CKE_DELAY_DEFAULT 0x0000005e
-
-/* MEMC_DDR_0 :: DRAM_TIMING_3 :: DLL_LOCK_DELAY [09:00] */
-#define BCHP_MEMC_DDR_0_DRAM_TIMING_3_DLL_LOCK_DELAY_MASK 0x000003ff
-#define BCHP_MEMC_DDR_0_DRAM_TIMING_3_DLL_LOCK_DELAY_SHIFT 0
-#define BCHP_MEMC_DDR_0_DRAM_TIMING_3_DLL_LOCK_DELAY_DEFAULT 0x00000200
-
-/***************************************************************************
- *DRAM_TIMING_4 - DDR-SDRAM Timing Register 4
- ***************************************************************************/
-/* MEMC_DDR_0 :: DRAM_TIMING_4 :: reserved0 [31:29] */
-#define BCHP_MEMC_DDR_0_DRAM_TIMING_4_reserved0_MASK 0xe0000000
-#define BCHP_MEMC_DDR_0_DRAM_TIMING_4_reserved0_SHIFT 29
-
-/* MEMC_DDR_0 :: DRAM_TIMING_4 :: PRECHARGE_ALL_DELAY [28:24] */
-#define BCHP_MEMC_DDR_0_DRAM_TIMING_4_PRECHARGE_ALL_DELAY_MASK 0x1f000000
-#define BCHP_MEMC_DDR_0_DRAM_TIMING_4_PRECHARGE_ALL_DELAY_SHIFT 24
-#define BCHP_MEMC_DDR_0_DRAM_TIMING_4_PRECHARGE_ALL_DELAY_DEFAULT 0x00000008
-
-/* MEMC_DDR_0 :: DRAM_TIMING_4 :: LOAD_MODE_DELAY [23:19] */
-#define BCHP_MEMC_DDR_0_DRAM_TIMING_4_LOAD_MODE_DELAY_MASK 0x00f80000
-#define BCHP_MEMC_DDR_0_DRAM_TIMING_4_LOAD_MODE_DELAY_SHIFT 19
-#define BCHP_MEMC_DDR_0_DRAM_TIMING_4_LOAD_MODE_DELAY_DEFAULT 0x0000000c
-
-/* MEMC_DDR_0 :: DRAM_TIMING_4 :: REFRESH_DELAY [18:10] */
-#define BCHP_MEMC_DDR_0_DRAM_TIMING_4_REFRESH_DELAY_MASK 0x0007fc00
-#define BCHP_MEMC_DDR_0_DRAM_TIMING_4_REFRESH_DELAY_SHIFT 10
-#define BCHP_MEMC_DDR_0_DRAM_TIMING_4_REFRESH_DELAY_DEFAULT 0x00000058
-
-/* MEMC_DDR_0 :: DRAM_TIMING_4 :: ZQCALIB_DELAY [09:00] */
-#define BCHP_MEMC_DDR_0_DRAM_TIMING_4_ZQCALIB_DELAY_MASK 0x000003ff
-#define BCHP_MEMC_DDR_0_DRAM_TIMING_4_ZQCALIB_DELAY_SHIFT 0
-#define BCHP_MEMC_DDR_0_DRAM_TIMING_4_ZQCALIB_DELAY_DEFAULT 0x00000200
-
-/***************************************************************************
- *DRAM_TIMING_5 - DDR-SDRAM Timing Register 5
- ***************************************************************************/
-/* MEMC_DDR_0 :: DRAM_TIMING_5 :: reserved0 [31:29] */
-#define BCHP_MEMC_DDR_0_DRAM_TIMING_5_reserved0_MASK 0xe0000000
-#define BCHP_MEMC_DDR_0_DRAM_TIMING_5_reserved0_SHIFT 29
-
-/* MEMC_DDR_0 :: DRAM_TIMING_5 :: CKE_ASSETION_DELAY [28:19] */
-#define BCHP_MEMC_DDR_0_DRAM_TIMING_5_CKE_ASSETION_DELAY_MASK 0x1ff80000
-#define BCHP_MEMC_DDR_0_DRAM_TIMING_5_CKE_ASSETION_DELAY_SHIFT 19
-#define BCHP_MEMC_DDR_0_DRAM_TIMING_5_CKE_ASSETION_DELAY_DEFAULT 0x00000105
-
-/* MEMC_DDR_0 :: DRAM_TIMING_5 :: CKE_MIN_WIDTH [18:15] */
-#define BCHP_MEMC_DDR_0_DRAM_TIMING_5_CKE_MIN_WIDTH_MASK 0x00078000
-#define BCHP_MEMC_DDR_0_DRAM_TIMING_5_CKE_MIN_WIDTH_SHIFT 15
-#define BCHP_MEMC_DDR_0_DRAM_TIMING_5_CKE_MIN_WIDTH_DEFAULT 0x00000003
-
-/* MEMC_DDR_0 :: DRAM_TIMING_5 :: PWDN_EXIT_DELAY [14:10] */
-#define BCHP_MEMC_DDR_0_DRAM_TIMING_5_PWDN_EXIT_DELAY_MASK 0x00007c00
-#define BCHP_MEMC_DDR_0_DRAM_TIMING_5_PWDN_EXIT_DELAY_SHIFT 10
-#define BCHP_MEMC_DDR_0_DRAM_TIMING_5_PWDN_EXIT_DELAY_DEFAULT 0x0000000d
-
-/* MEMC_DDR_0 :: DRAM_TIMING_5 :: SELFREF_EXIT_DELAY [09:00] */
-#define BCHP_MEMC_DDR_0_DRAM_TIMING_5_SELFREF_EXIT_DELAY_MASK 0x000003ff
-#define BCHP_MEMC_DDR_0_DRAM_TIMING_5_SELFREF_EXIT_DELAY_SHIFT 0
-#define BCHP_MEMC_DDR_0_DRAM_TIMING_5_SELFREF_EXIT_DELAY_DEFAULT 0x00000200
-
-/***************************************************************************
- *MIN_DQ_IDLE_CONTROL - Minimum DQ Idle Time Control
- ***************************************************************************/
-/* MEMC_DDR_0 :: MIN_DQ_IDLE_CONTROL :: reserved0 [31:23] */
-#define BCHP_MEMC_DDR_0_MIN_DQ_IDLE_CONTROL_reserved0_MASK 0xff800000
-#define BCHP_MEMC_DDR_0_MIN_DQ_IDLE_CONTROL_reserved0_SHIFT 23
-
-/* MEMC_DDR_0 :: MIN_DQ_IDLE_CONTROL :: WriteDelay [22:20] */
-#define BCHP_MEMC_DDR_0_MIN_DQ_IDLE_CONTROL_WriteDelay_MASK 0x00700000
-#define BCHP_MEMC_DDR_0_MIN_DQ_IDLE_CONTROL_WriteDelay_SHIFT 20
-#define BCHP_MEMC_DDR_0_MIN_DQ_IDLE_CONTROL_WriteDelay_DEFAULT 0x00000000
-
-/* MEMC_DDR_0 :: MIN_DQ_IDLE_CONTROL :: reserved1 [19:18] */
-#define BCHP_MEMC_DDR_0_MIN_DQ_IDLE_CONTROL_reserved1_MASK 0x000c0000
-#define BCHP_MEMC_DDR_0_MIN_DQ_IDLE_CONTROL_reserved1_SHIFT 18
-
-/* MEMC_DDR_0 :: MIN_DQ_IDLE_CONTROL :: WriteForceIdle [17:17] */
-#define BCHP_MEMC_DDR_0_MIN_DQ_IDLE_CONTROL_WriteForceIdle_MASK 0x00020000
-#define BCHP_MEMC_DDR_0_MIN_DQ_IDLE_CONTROL_WriteForceIdle_SHIFT 17
-#define BCHP_MEMC_DDR_0_MIN_DQ_IDLE_CONTROL_WriteForceIdle_DEFAULT 0x00000000
-
-/* MEMC_DDR_0 :: MIN_DQ_IDLE_CONTROL :: WriteEnable [16:16] */
-#define BCHP_MEMC_DDR_0_MIN_DQ_IDLE_CONTROL_WriteEnable_MASK 0x00010000
-#define BCHP_MEMC_DDR_0_MIN_DQ_IDLE_CONTROL_WriteEnable_SHIFT 16
-#define BCHP_MEMC_DDR_0_MIN_DQ_IDLE_CONTROL_WriteEnable_DEFAULT 0x00000000
-
-/* MEMC_DDR_0 :: MIN_DQ_IDLE_CONTROL :: reserved2 [15:07] */
-#define BCHP_MEMC_DDR_0_MIN_DQ_IDLE_CONTROL_reserved2_MASK 0x0000ff80
-#define BCHP_MEMC_DDR_0_MIN_DQ_IDLE_CONTROL_reserved2_SHIFT 7
-
-/* MEMC_DDR_0 :: MIN_DQ_IDLE_CONTROL :: ReadDelay [06:04] */
-#define BCHP_MEMC_DDR_0_MIN_DQ_IDLE_CONTROL_ReadDelay_MASK 0x00000070
-#define BCHP_MEMC_DDR_0_MIN_DQ_IDLE_CONTROL_ReadDelay_SHIFT 4
-#define BCHP_MEMC_DDR_0_MIN_DQ_IDLE_CONTROL_ReadDelay_DEFAULT 0x00000000
-
-/* MEMC_DDR_0 :: MIN_DQ_IDLE_CONTROL :: reserved3 [03:02] */
-#define BCHP_MEMC_DDR_0_MIN_DQ_IDLE_CONTROL_reserved3_MASK 0x0000000c
-#define BCHP_MEMC_DDR_0_MIN_DQ_IDLE_CONTROL_reserved3_SHIFT 2
-
-/* MEMC_DDR_0 :: MIN_DQ_IDLE_CONTROL :: ReadForceIdle [01:01] */
-#define BCHP_MEMC_DDR_0_MIN_DQ_IDLE_CONTROL_ReadForceIdle_MASK 0x00000002
-#define BCHP_MEMC_DDR_0_MIN_DQ_IDLE_CONTROL_ReadForceIdle_SHIFT 1
-#define BCHP_MEMC_DDR_0_MIN_DQ_IDLE_CONTROL_ReadForceIdle_DEFAULT 0x00000000
-
-/* MEMC_DDR_0 :: MIN_DQ_IDLE_CONTROL :: ReadEnable [00:00] */
-#define BCHP_MEMC_DDR_0_MIN_DQ_IDLE_CONTROL_ReadEnable_MASK 0x00000001
-#define BCHP_MEMC_DDR_0_MIN_DQ_IDLE_CONTROL_ReadEnable_SHIFT 0
-#define BCHP_MEMC_DDR_0_MIN_DQ_IDLE_CONTROL_ReadEnable_DEFAULT 0x00000000
-
-/***************************************************************************
- *PHY_OP_ACCESS_PENALTY - PHY Operational Access Penalty Count.
- ***************************************************************************/
-/* MEMC_DDR_0 :: PHY_OP_ACCESS_PENALTY :: PHY_OP_ACCESS_WAIT_PENALTY [31:00] */
-#define BCHP_MEMC_DDR_0_PHY_OP_ACCESS_PENALTY_PHY_OP_ACCESS_WAIT_PENALTY_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_PHY_OP_ACCESS_PENALTY_PHY_OP_ACCESS_WAIT_PENALTY_SHIFT 0
-#define BCHP_MEMC_DDR_0_PHY_OP_ACCESS_PENALTY_PHY_OP_ACCESS_WAIT_PENALTY_DEFAULT 0x00000000
-
-/***************************************************************************
- *CNTRLR_SM_TIMEOUT - Memory Controller , state machine timeout register.
- ***************************************************************************/
-/* MEMC_DDR_0 :: CNTRLR_SM_TIMEOUT :: reserved0 [31:17] */
-#define BCHP_MEMC_DDR_0_CNTRLR_SM_TIMEOUT_reserved0_MASK 0xfffe0000
-#define BCHP_MEMC_DDR_0_CNTRLR_SM_TIMEOUT_reserved0_SHIFT 17
-
-/* MEMC_DDR_0 :: CNTRLR_SM_TIMEOUT :: ENABLE [16:16] */
-#define BCHP_MEMC_DDR_0_CNTRLR_SM_TIMEOUT_ENABLE_MASK 0x00010000
-#define BCHP_MEMC_DDR_0_CNTRLR_SM_TIMEOUT_ENABLE_SHIFT 16
-#define BCHP_MEMC_DDR_0_CNTRLR_SM_TIMEOUT_ENABLE_DEFAULT 0x00000000
-
-/* MEMC_DDR_0 :: CNTRLR_SM_TIMEOUT :: COUNT [15:00] */
-#define BCHP_MEMC_DDR_0_CNTRLR_SM_TIMEOUT_COUNT_MASK 0x0000ffff
-#define BCHP_MEMC_DDR_0_CNTRLR_SM_TIMEOUT_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_CNTRLR_SM_TIMEOUT_COUNT_DEFAULT 0x0000ffff
-
-/***************************************************************************
- *BANK_STATUS - Memory Controller, Bank Status Register
- ***************************************************************************/
-/* MEMC_DDR_0 :: BANK_STATUS :: reserved0 [31:16] */
-#define BCHP_MEMC_DDR_0_BANK_STATUS_reserved0_MASK 0xffff0000
-#define BCHP_MEMC_DDR_0_BANK_STATUS_reserved0_SHIFT 16
-
-/* MEMC_DDR_0 :: BANK_STATUS :: BANK_STATUS [15:00] */
-#define BCHP_MEMC_DDR_0_BANK_STATUS_BANK_STATUS_MASK 0x0000ffff
-#define BCHP_MEMC_DDR_0_BANK_STATUS_BANK_STATUS_SHIFT 0
-#define BCHP_MEMC_DDR_0_BANK_STATUS_BANK_STATUS_DEFAULT 0x0000ffff
-
-/***************************************************************************
- *TESTER_LATENCY - Memory Controller, Tester Latency Register.
- ***************************************************************************/
-/* MEMC_DDR_0 :: TESTER_LATENCY :: reserved0 [31:08] */
-#define BCHP_MEMC_DDR_0_TESTER_LATENCY_reserved0_MASK 0xffffff00
-#define BCHP_MEMC_DDR_0_TESTER_LATENCY_reserved0_SHIFT 8
-
-/* MEMC_DDR_0 :: TESTER_LATENCY :: TLATENCY_SEL [07:00] */
-#define BCHP_MEMC_DDR_0_TESTER_LATENCY_TLATENCY_SEL_MASK 0x000000ff
-#define BCHP_MEMC_DDR_0_TESTER_LATENCY_TLATENCY_SEL_SHIFT 0
-#define BCHP_MEMC_DDR_0_TESTER_LATENCY_TLATENCY_SEL_DEFAULT 0x00000000
-
-/***************************************************************************
- *SEQ_RING_BUF_DEPTH - Sequencer Ring Buffer programmable depth.
- ***************************************************************************/
-/* MEMC_DDR_0 :: SEQ_RING_BUF_DEPTH :: reserved0 [31:05] */
-#define BCHP_MEMC_DDR_0_SEQ_RING_BUF_DEPTH_reserved0_MASK 0xffffffe0
-#define BCHP_MEMC_DDR_0_SEQ_RING_BUF_DEPTH_reserved0_SHIFT 5
-
-/* MEMC_DDR_0 :: SEQ_RING_BUF_DEPTH :: RING_BUF_DEPTH [04:00] */
-#define BCHP_MEMC_DDR_0_SEQ_RING_BUF_DEPTH_RING_BUF_DEPTH_MASK 0x0000001f
-#define BCHP_MEMC_DDR_0_SEQ_RING_BUF_DEPTH_RING_BUF_DEPTH_SHIFT 0
-#define BCHP_MEMC_DDR_0_SEQ_RING_BUF_DEPTH_RING_BUF_DEPTH_DEFAULT 0x0000000f
-
-/***************************************************************************
- *SEQ_WRDATA_ERR_INFO - Sequencer write data error info
- ***************************************************************************/
-/* MEMC_DDR_0 :: SEQ_WRDATA_ERR_INFO :: reserved0 [31:21] */
-#define BCHP_MEMC_DDR_0_SEQ_WRDATA_ERR_INFO_reserved0_MASK 0xffe00000
-#define BCHP_MEMC_DDR_0_SEQ_WRDATA_ERR_INFO_reserved0_SHIFT 21
-
-/* MEMC_DDR_0 :: SEQ_WRDATA_ERR_INFO :: INTF_ID [20:16] */
-#define BCHP_MEMC_DDR_0_SEQ_WRDATA_ERR_INFO_INTF_ID_MASK 0x001f0000
-#define BCHP_MEMC_DDR_0_SEQ_WRDATA_ERR_INFO_INTF_ID_SHIFT 16
-#define BCHP_MEMC_DDR_0_SEQ_WRDATA_ERR_INFO_INTF_ID_DEFAULT 0x00000000
-
-/* MEMC_DDR_0 :: SEQ_WRDATA_ERR_INFO :: reserved1 [15:08] */
-#define BCHP_MEMC_DDR_0_SEQ_WRDATA_ERR_INFO_reserved1_MASK 0x0000ff00
-#define BCHP_MEMC_DDR_0_SEQ_WRDATA_ERR_INFO_reserved1_SHIFT 8
-
-/* MEMC_DDR_0 :: SEQ_WRDATA_ERR_INFO :: INTF_TRANSACTION_ID [07:00] */
-#define BCHP_MEMC_DDR_0_SEQ_WRDATA_ERR_INFO_INTF_TRANSACTION_ID_MASK 0x000000ff
-#define BCHP_MEMC_DDR_0_SEQ_WRDATA_ERR_INFO_INTF_TRANSACTION_ID_SHIFT 0
-#define BCHP_MEMC_DDR_0_SEQ_WRDATA_ERR_INFO_INTF_TRANSACTION_ID_DEFAULT 0x00000000
-
-/***************************************************************************
- *SEQ_WRDATA_TRANSID_MISMATCH_INFO - Sequencer transaction ID mismatch error info
- ***************************************************************************/
-/* MEMC_DDR_0 :: SEQ_WRDATA_TRANSID_MISMATCH_INFO :: reserved0 [31:28] */
-#define BCHP_MEMC_DDR_0_SEQ_WRDATA_TRANSID_MISMATCH_INFO_reserved0_MASK 0xf0000000
-#define BCHP_MEMC_DDR_0_SEQ_WRDATA_TRANSID_MISMATCH_INFO_reserved0_SHIFT 28
-
-/* MEMC_DDR_0 :: SEQ_WRDATA_TRANSID_MISMATCH_INFO :: INTF_TYPE [27:24] */
-#define BCHP_MEMC_DDR_0_SEQ_WRDATA_TRANSID_MISMATCH_INFO_INTF_TYPE_MASK 0x0f000000
-#define BCHP_MEMC_DDR_0_SEQ_WRDATA_TRANSID_MISMATCH_INFO_INTF_TYPE_SHIFT 24
-#define BCHP_MEMC_DDR_0_SEQ_WRDATA_TRANSID_MISMATCH_INFO_INTF_TYPE_DEFAULT 0x00000000
-
-/* MEMC_DDR_0 :: SEQ_WRDATA_TRANSID_MISMATCH_INFO :: reserved1 [23:21] */
-#define BCHP_MEMC_DDR_0_SEQ_WRDATA_TRANSID_MISMATCH_INFO_reserved1_MASK 0x00e00000
-#define BCHP_MEMC_DDR_0_SEQ_WRDATA_TRANSID_MISMATCH_INFO_reserved1_SHIFT 21
-
-/* MEMC_DDR_0 :: SEQ_WRDATA_TRANSID_MISMATCH_INFO :: INTF_ID [20:16] */
-#define BCHP_MEMC_DDR_0_SEQ_WRDATA_TRANSID_MISMATCH_INFO_INTF_ID_MASK 0x001f0000
-#define BCHP_MEMC_DDR_0_SEQ_WRDATA_TRANSID_MISMATCH_INFO_INTF_ID_SHIFT 16
-#define BCHP_MEMC_DDR_0_SEQ_WRDATA_TRANSID_MISMATCH_INFO_INTF_ID_DEFAULT 0x00000000
-
-/* MEMC_DDR_0 :: SEQ_WRDATA_TRANSID_MISMATCH_INFO :: CMD_TRANS_ID [15:08] */
-#define BCHP_MEMC_DDR_0_SEQ_WRDATA_TRANSID_MISMATCH_INFO_CMD_TRANS_ID_MASK 0x0000ff00
-#define BCHP_MEMC_DDR_0_SEQ_WRDATA_TRANSID_MISMATCH_INFO_CMD_TRANS_ID_SHIFT 8
-#define BCHP_MEMC_DDR_0_SEQ_WRDATA_TRANSID_MISMATCH_INFO_CMD_TRANS_ID_DEFAULT 0x00000000
-
-/* MEMC_DDR_0 :: SEQ_WRDATA_TRANSID_MISMATCH_INFO :: WRDATA_TRANS_ID [07:00] */
-#define BCHP_MEMC_DDR_0_SEQ_WRDATA_TRANSID_MISMATCH_INFO_WRDATA_TRANS_ID_MASK 0x000000ff
-#define BCHP_MEMC_DDR_0_SEQ_WRDATA_TRANSID_MISMATCH_INFO_WRDATA_TRANS_ID_SHIFT 0
-#define BCHP_MEMC_DDR_0_SEQ_WRDATA_TRANSID_MISMATCH_INFO_WRDATA_TRANS_ID_DEFAULT 0x00000000
-
-/***************************************************************************
- *SEQ_CLEAR_VIOLATIONS - Sequencer Violation Info register clear.
- ***************************************************************************/
-/* MEMC_DDR_0 :: SEQ_CLEAR_VIOLATIONS :: reserved0 [31:01] */
-#define BCHP_MEMC_DDR_0_SEQ_CLEAR_VIOLATIONS_reserved0_MASK 0xfffffffe
-#define BCHP_MEMC_DDR_0_SEQ_CLEAR_VIOLATIONS_reserved0_SHIFT 1
-
-/* MEMC_DDR_0 :: SEQ_CLEAR_VIOLATIONS :: SEQ_CLEAR_VIOL [00:00] */
-#define BCHP_MEMC_DDR_0_SEQ_CLEAR_VIOLATIONS_SEQ_CLEAR_VIOL_MASK 0x00000001
-#define BCHP_MEMC_DDR_0_SEQ_CLEAR_VIOLATIONS_SEQ_CLEAR_VIOL_SHIFT 0
-#define BCHP_MEMC_DDR_0_SEQ_CLEAR_VIOLATIONS_SEQ_CLEAR_VIOL_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CONTROL - Statistics Control register
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CONTROL :: reserved0 [31:11] */
-#define BCHP_MEMC_DDR_0_STAT_CONTROL_reserved0_MASK 0xfffff800
-#define BCHP_MEMC_DDR_0_STAT_CONTROL_reserved0_SHIFT 11
-
-/* MEMC_DDR_0 :: STAT_CONTROL :: PER_CLIENT_MODE [10:10] */
-#define BCHP_MEMC_DDR_0_STAT_CONTROL_PER_CLIENT_MODE_MASK 0x00000400
-#define BCHP_MEMC_DDR_0_STAT_CONTROL_PER_CLIENT_MODE_SHIFT 10
-#define BCHP_MEMC_DDR_0_STAT_CONTROL_PER_CLIENT_MODE_DEFAULT 0x00000000
-
-/* MEMC_DDR_0 :: STAT_CONTROL :: COUNTER_MODE [09:09] */
-#define BCHP_MEMC_DDR_0_STAT_CONTROL_COUNTER_MODE_MASK 0x00000200
-#define BCHP_MEMC_DDR_0_STAT_CONTROL_COUNTER_MODE_SHIFT 9
-#define BCHP_MEMC_DDR_0_STAT_CONTROL_COUNTER_MODE_DEFAULT 0x00000000
-#define BCHP_MEMC_DDR_0_STAT_CONTROL_COUNTER_MODE_MAX_MIN_FUNCT 1
-#define BCHP_MEMC_DDR_0_STAT_CONTROL_COUNTER_MODE_NORMAL 0
-
-/* MEMC_DDR_0 :: STAT_CONTROL :: STAT_ENABLE [08:08] */
-#define BCHP_MEMC_DDR_0_STAT_CONTROL_STAT_ENABLE_MASK 0x00000100
-#define BCHP_MEMC_DDR_0_STAT_CONTROL_STAT_ENABLE_SHIFT 8
-#define BCHP_MEMC_DDR_0_STAT_CONTROL_STAT_ENABLE_DEFAULT 0x00000000
-#define BCHP_MEMC_DDR_0_STAT_CONTROL_STAT_ENABLE_ENABLE 1
-#define BCHP_MEMC_DDR_0_STAT_CONTROL_STAT_ENABLE_DISABLE 0
-
-/* MEMC_DDR_0 :: STAT_CONTROL :: CLIENT_ID [07:00] */
-#define BCHP_MEMC_DDR_0_STAT_CONTROL_CLIENT_ID_MASK 0x000000ff
-#define BCHP_MEMC_DDR_0_STAT_CONTROL_CLIENT_ID_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CONTROL_CLIENT_ID_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_TIMER - Statistics Timer
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_TIMER :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_TIMER_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_TIMER_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_TIMER_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_IDLE_NOP - DRAM Idle_NOP Cycle Count Register.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_IDLE_NOP :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_IDLE_NOP_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_IDLE_NOP_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_IDLE_NOP_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_MAX_IDLE_NOP - Maximum DRAM idle_NOP cycle count register.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_MAX_IDLE_NOP :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_MAX_IDLE_NOP_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_MAX_IDLE_NOP_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_MAX_IDLE_NOP_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_MIN_IDLE_NOP - Minimum DRAM idle_NOP cycle count register.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_MIN_IDLE_NOP :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_MIN_IDLE_NOP_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_MIN_IDLE_NOP_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_MIN_IDLE_NOP_COUNT_DEFAULT 0xffffffff
-
-/***************************************************************************
- *STAT_CAS_ALL - CAS Count Register.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_ALL :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_ALL_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_ALL_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_ALL_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_MAX_CAS_ALL - Maximum DRAM CAS cycle count register.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_MAX_CAS_ALL :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_MAX_CAS_ALL_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_MAX_CAS_ALL_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_MAX_CAS_ALL_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_MIN_CAS_ALL - Minimum DRAM CAS cycle count register.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_MIN_CAS_ALL :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_MIN_CAS_ALL_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_MIN_CAS_ALL_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_MIN_CAS_ALL_COUNT_DEFAULT 0xffffffff
-
-/***************************************************************************
- *STAT_PENALTY_ALL - DRAM Penalty Cycle Count register.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_PENALTY_ALL :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_PENALTY_ALL_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_PENALTY_ALL_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_PENALTY_ALL_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_PENALTY_GDDRWM - GDDR Write Mask Penalty Cycle Count register.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_PENALTY_GDDRWM :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_PENALTY_GDDRWM_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_PENALTY_GDDRWM_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_PENALTY_GDDRWM_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_MAX_TRANS_CYCLES_ALL - Maximum number of transactions cycles (CAS+Penalty_ALL).
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_MAX_TRANS_CYCLES_ALL :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_MAX_TRANS_CYCLES_ALL_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_MAX_TRANS_CYCLES_ALL_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_MAX_TRANS_CYCLES_ALL_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_MIN_TRANS_CYCLES_ALL - Minimum number of transactions cycles (CAS+Penalty_ALL).
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_MIN_TRANS_CYCLES_ALL :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_MIN_TRANS_CYCLES_ALL_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_MIN_TRANS_CYCLES_ALL_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_MIN_TRANS_CYCLES_ALL_COUNT_DEFAULT 0xffffffff
-
-/***************************************************************************
- *STAT_TRANS_READ_ALL - Number of overall system memory read transactions.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_TRANS_READ_ALL :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_TRANS_READ_ALL_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_TRANS_READ_ALL_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_TRANS_READ_ALL_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_TRANS_WRITE_ALL - Number of overall system memory write transactions.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_TRANS_WRITE_ALL :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_TRANS_WRITE_ALL_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_TRANS_WRITE_ALL_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_TRANS_WRITE_ALL_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_MAX_TRANS_ALL - Maximum Number of Overall System memory transactions.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_MAX_TRANS_ALL :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_MAX_TRANS_ALL_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_MAX_TRANS_ALL_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_MAX_TRANS_ALL_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_MIN_TRANS_ALL - Minimum Number of Overall System memory transactions.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_MIN_TRANS_ALL :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_MIN_TRANS_ALL_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_MIN_TRANS_ALL_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_MIN_TRANS_ALL_COUNT_DEFAULT 0xffffffff
-
-/***************************************************************************
- *STAT_CLIENT_SERVICE_CAS - Service CAS Cycle Count register.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CLIENT_SERVICE_CAS :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CLIENT_SERVICE_CAS_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CLIENT_SERVICE_CAS_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CLIENT_SERVICE_CAS_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_MAX_CLIENT_SERVICE_CAS - Maximum service CAS cycle count register.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_MAX_CLIENT_SERVICE_CAS :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_MAX_CLIENT_SERVICE_CAS_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_MAX_CLIENT_SERVICE_CAS_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_MAX_CLIENT_SERVICE_CAS_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_MIN_CLIENT_SERVICE_CAS - Minimum service CAS cycle count register.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_MIN_CLIENT_SERVICE_CAS :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_MIN_CLIENT_SERVICE_CAS_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_MIN_CLIENT_SERVICE_CAS_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_MIN_CLIENT_SERVICE_CAS_COUNT_DEFAULT 0xffffffff
-
-/***************************************************************************
- *STAT_CLIENT_SERVICE_INTR_PENALTY - Service Intra DRAM Penalty Cycle Count register.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CLIENT_SERVICE_INTR_PENALTY :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CLIENT_SERVICE_INTR_PENALTY_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CLIENT_SERVICE_INTR_PENALTY_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CLIENT_SERVICE_INTR_PENALTY_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CLIENT_SERVICE_POST_PENALTY - Service Post DRAM Penalty Cycle Count register.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CLIENT_SERVICE_POST_PENALTY :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CLIENT_SERVICE_POST_PENALTY_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CLIENT_SERVICE_POST_PENALTY_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CLIENT_SERVICE_POST_PENALTY_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CLIENT_SERVICE_GDDRWM_PENALTY - Service GDDR Write Mask Penalty Cycle Count register.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CLIENT_SERVICE_GDDRWM_PENALTY :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CLIENT_SERVICE_GDDRWM_PENALTY_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CLIENT_SERVICE_GDDRWM_PENALTY_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CLIENT_SERVICE_GDDRWM_PENALTY_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_MAX_CLIENT_SERVICE_CYCLES - Maximum service cycle count register.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_MAX_CLIENT_SERVICE_CYCLES :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_MAX_CLIENT_SERVICE_CYCLES_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_MAX_CLIENT_SERVICE_CYCLES_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_MAX_CLIENT_SERVICE_CYCLES_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_MIN_CLIENT_SERVICE_CYCLES - Minimum service cycle count register.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_MIN_CLIENT_SERVICE_CYCLES :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_MIN_CLIENT_SERVICE_CYCLES_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_MIN_CLIENT_SERVICE_CYCLES_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_MIN_CLIENT_SERVICE_CYCLES_COUNT_DEFAULT 0xffffffff
-
-/***************************************************************************
- *STAT_CLIENT_SERVICE_TRANS_READ - Service Read Transaction Count register.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CLIENT_SERVICE_TRANS_READ :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CLIENT_SERVICE_TRANS_READ_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CLIENT_SERVICE_TRANS_READ_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CLIENT_SERVICE_TRANS_READ_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CLIENT_SERVICE_TRANS_WRITE - Service Write Transaction Count register.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CLIENT_SERVICE_TRANS_WRITE :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CLIENT_SERVICE_TRANS_WRITE_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CLIENT_SERVICE_TRANS_WRITE_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CLIENT_SERVICE_TRANS_WRITE_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_MAX_CLIENT_SERVICE_TRANS - Maximum service Transaction count register.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_MAX_CLIENT_SERVICE_TRANS :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_MAX_CLIENT_SERVICE_TRANS_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_MAX_CLIENT_SERVICE_TRANS_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_MAX_CLIENT_SERVICE_TRANS_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_MIN_CLIENT_SERVICE_TRANS - Minimum service cycle Transaction register.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_MIN_CLIENT_SERVICE_TRANS :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_MIN_CLIENT_SERVICE_TRANS_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_MIN_CLIENT_SERVICE_TRANS_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_MIN_CLIENT_SERVICE_TRANS_COUNT_DEFAULT 0xffffffff
-
-/***************************************************************************
- *STAT_CLIENT_SERVICE_LATENCY - Service Latency Count register.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CLIENT_SERVICE_LATENCY :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CLIENT_SERVICE_LATENCY_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CLIENT_SERVICE_LATENCY_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CLIENT_SERVICE_LATENCY_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_MAX_CLIENT_SERVICE_LATENCY - Maximum Service Latency count register.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_MAX_CLIENT_SERVICE_LATENCY :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_MAX_CLIENT_SERVICE_LATENCY_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_MAX_CLIENT_SERVICE_LATENCY_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_MAX_CLIENT_SERVICE_LATENCY_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_MIN_CLIENT_SERVICE_LATENCY - Minimum Service Latency count register.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_MIN_CLIENT_SERVICE_LATENCY :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_MIN_CLIENT_SERVICE_LATENCY_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_MIN_CLIENT_SERVICE_LATENCY_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_MIN_CLIENT_SERVICE_LATENCY_COUNT_DEFAULT 0xffffffff
-
-/***************************************************************************
- *STAT_CLIENT_ABS_MAX_SERVICE_LATENCY - Absolute Minimum Service Latency count register.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CLIENT_ABS_MAX_SERVICE_LATENCY :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CLIENT_ABS_MAX_SERVICE_LATENCY_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CLIENT_ABS_MAX_SERVICE_LATENCY_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CLIENT_ABS_MAX_SERVICE_LATENCY_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CLIENT_ABS_MIN_SERVICE_LATENCY - Absolute Maximum Service Latency count register.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CLIENT_ABS_MIN_SERVICE_LATENCY :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CLIENT_ABS_MIN_SERVICE_LATENCY_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CLIENT_ABS_MIN_SERVICE_LATENCY_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CLIENT_ABS_MIN_SERVICE_LATENCY_COUNT_DEFAULT 0xffffffff
-
-/***************************************************************************
- *STAT_REFRESH - Total number of refreshes issued.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_REFRESH :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_REFRESH_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_REFRESH_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_REFRESH_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_MIN_DQ_IDLE_WRITE - Min DQ Idle Write event counter
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_MIN_DQ_IDLE_WRITE :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_MIN_DQ_IDLE_WRITE_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_MIN_DQ_IDLE_WRITE_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_MIN_DQ_IDLE_WRITE_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_MIN_DQ_IDLE_READ - Min DQ Idle Read event counter
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_MIN_DQ_IDLE_READ :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_MIN_DQ_IDLE_READ_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_MIN_DQ_IDLE_READ_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_MIN_DQ_IDLE_READ_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_0 - CAS or consumption cycle count register for client 0.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_0 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_0_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_0_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_0_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_1 - CAS or consumption cycle count register for client 1.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_1 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_1_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_1_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_1_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_2 - CAS or consumption cycle count register for client 2.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_2 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_2_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_2_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_2_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_3 - CAS or consumption cycle count register for client 3.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_3 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_3_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_3_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_3_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_4 - CAS or consumption cycle count register for client 4.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_4 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_4_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_4_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_4_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_5 - CAS or consumption cycle count register for client 5.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_5 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_5_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_5_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_5_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_6 - CAS or consumption cycle count register for client 6.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_6 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_6_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_6_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_6_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_7 - CAS or consumption cycle count register for client 7.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_7 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_7_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_7_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_7_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_8 - CAS or consumption cycle count register for client 8.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_8 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_8_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_8_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_8_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_9 - CAS or consumption cycle count register for client 9.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_9 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_9_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_9_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_9_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_10 - CAS or consumption cycle count register for client 10.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_10 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_10_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_10_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_10_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_11 - CAS or consumption cycle count register for client 11.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_11 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_11_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_11_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_11_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_12 - CAS or consumption cycle count register for client 12.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_12 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_12_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_12_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_12_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_13 - CAS or consumption cycle count register for client 13.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_13 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_13_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_13_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_13_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_14 - CAS or consumption cycle count register for client 14.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_14 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_14_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_14_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_14_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_15 - CAS or consumption cycle count register for client 15.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_15 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_15_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_15_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_15_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_16 - CAS or consumption cycle count register for client 16.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_16 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_16_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_16_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_16_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_17 - CAS or consumption cycle count register for client 17.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_17 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_17_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_17_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_17_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_18 - CAS or consumption cycle count register for client 18.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_18 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_18_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_18_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_18_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_19 - CAS or consumption cycle count register for client 19.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_19 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_19_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_19_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_19_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_20 - CAS or consumption cycle count register for client 20.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_20 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_20_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_20_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_20_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_21 - CAS or consumption cycle count register for client 21.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_21 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_21_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_21_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_21_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_22 - CAS or consumption cycle count register for client 22.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_22 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_22_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_22_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_22_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_23 - CAS or consumption cycle count register for client 23.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_23 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_23_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_23_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_23_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_24 - CAS or consumption cycle count register for client 24.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_24 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_24_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_24_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_24_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_25 - CAS or consumption cycle count register for client 25.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_25 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_25_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_25_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_25_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_26 - CAS or consumption cycle count register for client 26.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_26 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_26_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_26_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_26_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_27 - CAS or consumption cycle count register for client 27.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_27 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_27_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_27_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_27_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_28 - CAS or consumption cycle count register for client 28.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_28 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_28_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_28_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_28_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_29 - CAS or consumption cycle count register for client 29.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_29 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_29_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_29_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_29_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_30 - CAS or consumption cycle count register for client 30.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_30 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_30_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_30_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_30_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_31 - CAS or consumption cycle count register for client 31.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_31 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_31_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_31_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_31_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_32 - CAS or consumption cycle count register for client 32.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_32 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_32_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_32_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_32_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_33 - CAS or consumption cycle count register for client 33.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_33 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_33_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_33_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_33_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_34 - CAS or consumption cycle count register for client 34.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_34 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_34_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_34_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_34_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_35 - CAS or consumption cycle count register for client 35.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_35 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_35_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_35_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_35_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_36 - CAS or consumption cycle count register for client 36.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_36 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_36_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_36_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_36_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_37 - CAS or consumption cycle count register for client 37.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_37 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_37_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_37_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_37_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_38 - CAS or consumption cycle count register for client 38.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_38 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_38_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_38_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_38_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_39 - CAS or consumption cycle count register for client 39.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_39 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_39_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_39_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_39_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_40 - CAS or consumption cycle count register for client 40.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_40 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_40_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_40_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_40_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_41 - CAS or consumption cycle count register for client 41.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_41 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_41_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_41_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_41_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_42 - CAS or consumption cycle count register for client 42.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_42 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_42_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_42_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_42_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_43 - CAS or consumption cycle count register for client 43.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_43 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_43_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_43_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_43_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_44 - CAS or consumption cycle count register for client 44.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_44 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_44_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_44_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_44_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_45 - CAS or consumption cycle count register for client 45.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_45 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_45_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_45_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_45_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_46 - CAS or consumption cycle count register for client 46.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_46 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_46_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_46_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_46_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_47 - CAS or consumption cycle count register for client 47.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_47 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_47_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_47_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_47_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_48 - CAS or consumption cycle count register for client 48.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_48 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_48_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_48_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_48_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_49 - CAS or consumption cycle count register for client 49.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_49 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_49_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_49_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_49_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_50 - CAS or consumption cycle count register for client 50.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_50 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_50_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_50_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_50_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_51 - CAS or consumption cycle count register for client 51.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_51 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_51_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_51_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_51_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_52 - CAS or consumption cycle count register for client 52.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_52 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_52_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_52_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_52_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_53 - CAS or consumption cycle count register for client 53.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_53 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_53_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_53_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_53_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_54 - CAS or consumption cycle count register for client 54.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_54 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_54_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_54_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_54_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_55 - CAS or consumption cycle count register for client 55.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_55 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_55_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_55_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_55_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_56 - CAS or consumption cycle count register for client 56.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_56 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_56_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_56_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_56_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_57 - CAS or consumption cycle count register for client 57.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_57 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_57_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_57_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_57_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_58 - CAS or consumption cycle count register for client 58.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_58 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_58_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_58_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_58_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_59 - CAS or consumption cycle count register for client 59.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_59 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_59_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_59_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_59_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_60 - CAS or consumption cycle count register for client 60.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_60 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_60_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_60_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_60_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_61 - CAS or consumption cycle count register for client 61.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_61 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_61_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_61_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_61_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_62 - CAS or consumption cycle count register for client 62.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_62 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_62_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_62_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_62_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_63 - CAS or consumption cycle count register for client 63.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_63 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_63_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_63_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_63_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_64 - CAS or consumption cycle count register for client 64.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_64 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_64_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_64_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_64_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_65 - CAS or consumption cycle count register for client 65.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_65 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_65_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_65_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_65_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_66 - CAS or consumption cycle count register for client 66.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_66 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_66_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_66_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_66_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_67 - CAS or consumption cycle count register for client 67.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_67 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_67_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_67_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_67_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_68 - CAS or consumption cycle count register for client 68.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_68 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_68_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_68_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_68_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_69 - CAS or consumption cycle count register for client 69.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_69 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_69_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_69_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_69_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_70 - CAS or consumption cycle count register for client 70.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_70 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_70_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_70_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_70_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_71 - CAS or consumption cycle count register for client 71.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_71 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_71_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_71_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_71_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_72 - CAS or consumption cycle count register for client 72.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_72 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_72_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_72_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_72_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_73 - CAS or consumption cycle count register for client 73.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_73 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_73_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_73_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_73_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_74 - CAS or consumption cycle count register for client 74.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_74 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_74_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_74_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_74_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_75 - CAS or consumption cycle count register for client 75.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_75 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_75_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_75_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_75_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_76 - CAS or consumption cycle count register for client 76.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_76 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_76_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_76_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_76_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_77 - CAS or consumption cycle count register for client 77.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_77 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_77_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_77_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_77_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_78 - CAS or consumption cycle count register for client 78.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_78 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_78_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_78_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_78_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_79 - CAS or consumption cycle count register for client 79.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_79 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_79_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_79_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_79_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_80 - CAS or consumption cycle count register for client 80.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_80 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_80_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_80_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_80_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_81 - CAS or consumption cycle count register for client 81.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_81 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_81_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_81_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_81_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_82 - CAS or consumption cycle count register for client 82.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_82 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_82_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_82_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_82_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_83 - CAS or consumption cycle count register for client 83.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_83 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_83_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_83_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_83_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_84 - CAS or consumption cycle count register for client 84.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_84 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_84_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_84_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_84_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_85 - CAS or consumption cycle count register for client 85.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_85 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_85_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_85_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_85_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_86 - CAS or consumption cycle count register for client 86.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_86 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_86_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_86_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_86_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_87 - CAS or consumption cycle count register for client 87.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_87 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_87_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_87_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_87_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_88 - CAS or consumption cycle count register for client 88.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_88 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_88_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_88_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_88_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_89 - CAS or consumption cycle count register for client 89.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_89 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_89_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_89_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_89_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_90 - CAS or consumption cycle count register for client 90.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_90 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_90_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_90_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_90_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_91 - CAS or consumption cycle count register for client 91.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_91 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_91_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_91_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_91_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_92 - CAS or consumption cycle count register for client 92.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_92 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_92_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_92_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_92_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_93 - CAS or consumption cycle count register for client 93.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_93 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_93_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_93_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_93_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_94 - CAS or consumption cycle count register for client 94.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_94 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_94_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_94_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_94_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_95 - CAS or consumption cycle count register for client 95.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_95 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_95_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_95_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_95_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_96 - CAS or consumption cycle count register for client 96.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_96 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_96_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_96_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_96_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_97 - CAS or consumption cycle count register for client 97.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_97 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_97_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_97_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_97_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_98 - CAS or consumption cycle count register for client 98.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_98 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_98_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_98_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_98_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_99 - CAS or consumption cycle count register for client 99.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_99 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_99_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_99_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_99_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_100 - CAS or consumption cycle count register for client 100.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_100 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_100_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_100_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_100_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_101 - CAS or consumption cycle count register for client 101.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_101 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_101_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_101_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_101_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_102 - CAS or consumption cycle count register for client 102.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_102 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_102_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_102_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_102_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_103 - CAS or consumption cycle count register for client 103.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_103 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_103_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_103_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_103_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_104 - CAS or consumption cycle count register for client 104.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_104 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_104_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_104_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_104_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_105 - CAS or consumption cycle count register for client 105.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_105 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_105_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_105_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_105_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_106 - CAS or consumption cycle count register for client 106.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_106 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_106_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_106_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_106_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_107 - CAS or consumption cycle count register for client 107.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_107 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_107_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_107_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_107_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_108 - CAS or consumption cycle count register for client 108.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_108 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_108_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_108_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_108_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_109 - CAS or consumption cycle count register for client 109.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_109 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_109_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_109_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_109_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_110 - CAS or consumption cycle count register for client 110.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_110 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_110_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_110_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_110_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_111 - CAS or consumption cycle count register for client 111.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_111 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_111_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_111_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_111_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_112 - CAS or consumption cycle count register for client 112.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_112 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_112_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_112_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_112_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_113 - CAS or consumption cycle count register for client 113.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_113 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_113_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_113_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_113_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_114 - CAS or consumption cycle count register for client 114.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_114 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_114_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_114_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_114_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_115 - CAS or consumption cycle count register for client 115.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_115 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_115_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_115_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_115_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_116 - CAS or consumption cycle count register for client 116.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_116 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_116_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_116_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_116_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_117 - CAS or consumption cycle count register for client 117.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_117 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_117_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_117_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_117_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_118 - CAS or consumption cycle count register for client 118.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_118 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_118_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_118_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_118_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_119 - CAS or consumption cycle count register for client 119.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_119 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_119_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_119_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_119_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_120 - CAS or consumption cycle count register for client 120.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_120 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_120_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_120_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_120_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_121 - CAS or consumption cycle count register for client 121.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_121 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_121_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_121_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_121_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_122 - CAS or consumption cycle count register for client 122.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_122 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_122_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_122_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_122_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_123 - CAS or consumption cycle count register for client 123.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_123 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_123_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_123_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_123_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_124 - CAS or consumption cycle count register for client 124.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_124 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_124_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_124_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_124_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_125 - CAS or consumption cycle count register for client 125.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_125 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_125_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_125_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_125_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_126 - CAS or consumption cycle count register for client 126.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_126 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_126_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_126_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_126_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_127 - CAS or consumption cycle count register for client 127.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_127 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_127_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_127_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_127_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_128 - CAS or consumption cycle count register for client 128.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_128 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_128_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_128_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_128_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_129 - CAS or consumption cycle count register for client 129.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_129 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_129_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_129_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_129_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_130 - CAS or consumption cycle count register for client 130.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_130 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_130_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_130_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_130_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_131 - CAS or consumption cycle count register for client 131.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_131 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_131_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_131_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_131_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_132 - CAS or consumption cycle count register for client 132.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_132 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_132_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_132_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_132_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_133 - CAS or consumption cycle count register for client 133.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_133 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_133_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_133_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_133_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_134 - CAS or consumption cycle count register for client 134.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_134 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_134_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_134_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_134_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_135 - CAS or consumption cycle count register for client 135.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_135 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_135_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_135_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_135_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_136 - CAS or consumption cycle count register for client 136.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_136 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_136_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_136_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_136_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_137 - CAS or consumption cycle count register for client 137.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_137 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_137_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_137_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_137_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_138 - CAS or consumption cycle count register for client 138.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_138 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_138_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_138_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_138_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_139 - CAS or consumption cycle count register for client 139.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_139 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_139_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_139_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_139_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_140 - CAS or consumption cycle count register for client 140.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_140 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_140_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_140_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_140_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_141 - CAS or consumption cycle count register for client 141.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_141 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_141_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_141_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_141_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_142 - CAS or consumption cycle count register for client 142.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_142 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_142_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_142_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_142_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_143 - CAS or consumption cycle count register for client 143.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_143 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_143_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_143_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_143_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_144 - CAS or consumption cycle count register for client 144.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_144 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_144_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_144_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_144_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_145 - CAS or consumption cycle count register for client 145.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_145 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_145_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_145_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_145_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_146 - CAS or consumption cycle count register for client 146.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_146 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_146_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_146_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_146_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_147 - CAS or consumption cycle count register for client 147.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_147 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_147_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_147_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_147_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_148 - CAS or consumption cycle count register for client 148.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_148 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_148_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_148_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_148_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_149 - CAS or consumption cycle count register for client 149.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_149 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_149_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_149_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_149_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_150 - CAS or consumption cycle count register for client 150.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_150 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_150_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_150_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_150_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_151 - CAS or consumption cycle count register for client 151.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_151 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_151_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_151_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_151_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_152 - CAS or consumption cycle count register for client 152.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_152 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_152_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_152_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_152_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_153 - CAS or consumption cycle count register for client 153.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_153 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_153_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_153_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_153_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_154 - CAS or consumption cycle count register for client 154.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_154 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_154_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_154_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_154_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_155 - CAS or consumption cycle count register for client 155.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_155 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_155_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_155_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_155_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_156 - CAS or consumption cycle count register for client 156.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_156 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_156_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_156_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_156_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_157 - CAS or consumption cycle count register for client 157.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_157 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_157_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_157_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_157_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_158 - CAS or consumption cycle count register for client 158.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_158 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_158_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_158_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_158_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_159 - CAS or consumption cycle count register for client 159.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_159 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_159_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_159_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_159_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_160 - CAS or consumption cycle count register for client 160.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_160 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_160_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_160_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_160_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_161 - CAS or consumption cycle count register for client 161.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_161 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_161_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_161_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_161_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_162 - CAS or consumption cycle count register for client 162.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_162 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_162_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_162_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_162_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_163 - CAS or consumption cycle count register for client 163.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_163 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_163_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_163_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_163_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_164 - CAS or consumption cycle count register for client 164.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_164 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_164_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_164_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_164_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_165 - CAS or consumption cycle count register for client 165.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_165 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_165_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_165_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_165_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_166 - CAS or consumption cycle count register for client 166.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_166 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_166_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_166_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_166_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_167 - CAS or consumption cycle count register for client 167.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_167 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_167_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_167_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_167_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_168 - CAS or consumption cycle count register for client 168.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_168 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_168_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_168_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_168_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_169 - CAS or consumption cycle count register for client 169.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_169 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_169_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_169_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_169_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_170 - CAS or consumption cycle count register for client 170.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_170 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_170_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_170_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_170_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_171 - CAS or consumption cycle count register for client 171.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_171 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_171_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_171_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_171_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_172 - CAS or consumption cycle count register for client 172.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_172 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_172_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_172_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_172_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_173 - CAS or consumption cycle count register for client 173.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_173 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_173_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_173_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_173_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_174 - CAS or consumption cycle count register for client 174.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_174 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_174_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_174_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_174_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_175 - CAS or consumption cycle count register for client 175.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_175 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_175_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_175_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_175_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_176 - CAS or consumption cycle count register for client 176.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_176 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_176_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_176_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_176_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_177 - CAS or consumption cycle count register for client 177.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_177 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_177_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_177_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_177_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_178 - CAS or consumption cycle count register for client 178.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_178 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_178_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_178_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_178_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_179 - CAS or consumption cycle count register for client 179.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_179 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_179_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_179_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_179_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_180 - CAS or consumption cycle count register for client 180.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_180 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_180_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_180_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_180_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_181 - CAS or consumption cycle count register for client 181.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_181 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_181_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_181_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_181_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_182 - CAS or consumption cycle count register for client 182.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_182 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_182_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_182_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_182_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_183 - CAS or consumption cycle count register for client 183.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_183 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_183_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_183_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_183_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_184 - CAS or consumption cycle count register for client 184.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_184 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_184_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_184_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_184_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_185 - CAS or consumption cycle count register for client 185.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_185 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_185_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_185_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_185_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_186 - CAS or consumption cycle count register for client 186.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_186 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_186_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_186_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_186_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_187 - CAS or consumption cycle count register for client 187.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_187 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_187_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_187_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_187_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_188 - CAS or consumption cycle count register for client 188.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_188 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_188_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_188_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_188_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_189 - CAS or consumption cycle count register for client 189.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_189 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_189_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_189_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_189_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_190 - CAS or consumption cycle count register for client 190.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_190 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_190_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_190_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_190_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_191 - CAS or consumption cycle count register for client 191.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_191 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_191_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_191_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_191_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_192 - CAS or consumption cycle count register for client 192.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_192 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_192_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_192_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_192_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_193 - CAS or consumption cycle count register for client 193.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_193 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_193_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_193_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_193_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_194 - CAS or consumption cycle count register for client 194.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_194 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_194_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_194_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_194_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_195 - CAS or consumption cycle count register for client 195.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_195 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_195_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_195_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_195_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_196 - CAS or consumption cycle count register for client 196.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_196 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_196_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_196_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_196_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_197 - CAS or consumption cycle count register for client 197.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_197 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_197_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_197_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_197_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_198 - CAS or consumption cycle count register for client 198.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_198 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_198_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_198_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_198_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_199 - CAS or consumption cycle count register for client 199.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_199 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_199_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_199_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_199_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_200 - CAS or consumption cycle count register for client 200.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_200 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_200_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_200_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_200_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_201 - CAS or consumption cycle count register for client 201.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_201 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_201_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_201_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_201_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_202 - CAS or consumption cycle count register for client 202.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_202 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_202_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_202_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_202_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_203 - CAS or consumption cycle count register for client 203.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_203 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_203_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_203_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_203_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_204 - CAS or consumption cycle count register for client 204.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_204 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_204_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_204_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_204_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_205 - CAS or consumption cycle count register for client 205.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_205 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_205_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_205_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_205_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_206 - CAS or consumption cycle count register for client 206.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_206 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_206_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_206_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_206_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_207 - CAS or consumption cycle count register for client 207.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_207 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_207_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_207_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_207_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_208 - CAS or consumption cycle count register for client 208.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_208 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_208_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_208_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_208_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_209 - CAS or consumption cycle count register for client 209.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_209 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_209_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_209_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_209_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_210 - CAS or consumption cycle count register for client 210.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_210 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_210_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_210_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_210_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_211 - CAS or consumption cycle count register for client 211.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_211 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_211_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_211_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_211_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_212 - CAS or consumption cycle count register for client 212.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_212 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_212_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_212_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_212_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_213 - CAS or consumption cycle count register for client 213.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_213 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_213_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_213_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_213_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_214 - CAS or consumption cycle count register for client 214.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_214 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_214_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_214_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_214_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_215 - CAS or consumption cycle count register for client 215.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_215 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_215_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_215_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_215_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_216 - CAS or consumption cycle count register for client 216.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_216 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_216_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_216_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_216_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_217 - CAS or consumption cycle count register for client 217.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_217 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_217_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_217_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_217_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_218 - CAS or consumption cycle count register for client 218.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_218 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_218_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_218_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_218_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_219 - CAS or consumption cycle count register for client 219.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_219 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_219_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_219_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_219_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_220 - CAS or consumption cycle count register for client 220.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_220 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_220_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_220_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_220_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_221 - CAS or consumption cycle count register for client 221.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_221 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_221_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_221_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_221_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_222 - CAS or consumption cycle count register for client 222.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_222 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_222_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_222_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_222_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_223 - CAS or consumption cycle count register for client 223.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_223 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_223_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_223_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_223_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_224 - CAS or consumption cycle count register for client 224.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_224 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_224_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_224_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_224_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_225 - CAS or consumption cycle count register for client 225.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_225 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_225_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_225_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_225_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_226 - CAS or consumption cycle count register for client 226.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_226 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_226_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_226_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_226_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_227 - CAS or consumption cycle count register for client 227.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_227 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_227_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_227_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_227_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_228 - CAS or consumption cycle count register for client 228.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_228 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_228_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_228_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_228_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_229 - CAS or consumption cycle count register for client 229.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_229 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_229_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_229_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_229_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_230 - CAS or consumption cycle count register for client 230.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_230 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_230_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_230_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_230_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_231 - CAS or consumption cycle count register for client 231.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_231 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_231_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_231_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_231_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_232 - CAS or consumption cycle count register for client 232.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_232 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_232_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_232_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_232_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_233 - CAS or consumption cycle count register for client 233.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_233 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_233_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_233_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_233_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_234 - CAS or consumption cycle count register for client 234.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_234 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_234_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_234_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_234_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_235 - CAS or consumption cycle count register for client 235.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_235 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_235_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_235_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_235_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_236 - CAS or consumption cycle count register for client 236.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_236 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_236_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_236_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_236_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_237 - CAS or consumption cycle count register for client 237.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_237 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_237_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_237_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_237_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_238 - CAS or consumption cycle count register for client 238.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_238 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_238_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_238_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_238_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_239 - CAS or consumption cycle count register for client 239.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_239 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_239_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_239_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_239_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_240 - CAS or consumption cycle count register for client 240.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_240 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_240_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_240_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_240_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_241 - CAS or consumption cycle count register for client 241.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_241 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_241_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_241_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_241_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_242 - CAS or consumption cycle count register for client 242.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_242 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_242_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_242_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_242_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_243 - CAS or consumption cycle count register for client 243.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_243 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_243_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_243_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_243_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_244 - CAS or consumption cycle count register for client 244.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_244 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_244_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_244_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_244_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_245 - CAS or consumption cycle count register for client 245.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_245 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_245_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_245_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_245_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_246 - CAS or consumption cycle count register for client 246.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_246 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_246_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_246_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_246_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_247 - CAS or consumption cycle count register for client 247.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_247 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_247_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_247_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_247_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_248 - CAS or consumption cycle count register for client 248.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_248 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_248_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_248_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_248_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_249 - CAS or consumption cycle count register for client 249.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_249 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_249_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_249_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_249_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_250 - CAS or consumption cycle count register for client 250.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_250 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_250_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_250_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_250_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_251 - CAS or consumption cycle count register for client 251.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_251 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_251_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_251_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_251_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_252 - CAS or consumption cycle count register for client 252.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_252 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_252_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_252_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_252_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_253 - CAS or consumption cycle count register for client 253.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_253 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_253_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_253_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_253_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_254 - CAS or consumption cycle count register for client 254.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_254 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_254_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_254_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_254_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_255 - CAS or consumption cycle count register for client 255.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_255 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_255_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_255_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_255_COUNT_DEFAULT 0x00000000
-
-#endif /* #ifndef BCHP_MEMC_DDR_0_H__ */
-
-/* End of File */
diff --git a/include/linux/brcmstb/7145a0/bchp_memc_ddr_1.h b/include/linux/brcmstb/7145a0/bchp_memc_ddr_1.h
deleted file mode 100644
index bda50c6..0000000
--- a/include/linux/brcmstb/7145a0/bchp_memc_ddr_1.h
+++ /dev/null
@@ -1,4679 +0,0 @@
-/***************************************************************************
- * Copyright (c) 1999-2013, Broadcom Corporation
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
- *
- * Module Description:
- * DO NOT EDIT THIS FILE DIRECTLY
- *
- * This module was generated magically with RDB from a source description
- * file. You must edit the source file for changes to be made to this file.
- *
- *
- * Date: Generated on Sat Apr 6 03:07:49 2013
- * MD5 Checksum d41d8cd98f00b204e9800998ecf8427e
- *
- * Compiled with: RDB Utility combo_header.pl
- * RDB Parser 3.0
- * unknown unknown
- * Perl Interpreter 5.008008
- * Operating System linux
- *
- * Revision History:
- *
- * $brcm_Log: $
- *
- ***************************************************************************/
-
-#ifndef BCHP_MEMC_DDR_1_H__
-#define BCHP_MEMC_DDR_1_H__
-
-/***************************************************************************
- *MEMC_DDR_1 - 1 Sequencer DRAM Param and Control Registers
- ***************************************************************************/
-#define BCHP_MEMC_DDR_1_CNTRLR_CONFIG 0x203c2000 /* Memory Controller Configuration Register */
-#define BCHP_MEMC_DDR_1_DRAM_INIT_CNTRL 0x203c2004 /* Dram initialization control */
-#define BCHP_MEMC_DDR_1_DRAM_INIT_STATUS 0x203c2008 /* Dram initialization status */
-#define BCHP_MEMC_DDR_1_DRAM_MODE_0 0x203c200c /* Dram Mode Register 0 */
-#define BCHP_MEMC_DDR_1_DRAM_MODE_1 0x203c2010 /* Dram Mode Register 1 */
-#define BCHP_MEMC_DDR_1_DRAM_MODE_2 0x203c2014 /* Dram Mode Register 2 */
-#define BCHP_MEMC_DDR_1_DRAM_MODE_3 0x203c2018 /* Dram Mode Register 3 */
-#define BCHP_MEMC_DDR_1_DRAM_MODE_4 0x203c201c /* Dram Mode Register 4 */
-#define BCHP_MEMC_DDR_1_DRAM_MODE_5 0x203c2020 /* Dram Mode Register 5 */
-#define BCHP_MEMC_DDR_1_DRAM_MODE_6 0x203c2024 /* Dram Mode Register 6 */
-#define BCHP_MEMC_DDR_1_DRAM_MODE_7 0x203c2028 /* Dram Mode Register 7 */
-#define BCHP_MEMC_DDR_1_DRAM_MODE_8 0x203c202c /* Dram Mode Register 8 */
-#define BCHP_MEMC_DDR_1_DRAM_MODE_15 0x203c2030 /* Dram Mode Register 15 */
-#define BCHP_MEMC_DDR_1_PPD_CONFIG 0x203c2034 /* Precharge power down mode configuration register */
-#define BCHP_MEMC_DDR_1_SRPD_CONFIG 0x203c2038 /* Self-refresh power down mode configuration register */
-#define BCHP_MEMC_DDR_1_SSPD_CMD 0x203c203c /* Software standby power down mode */
-#define BCHP_MEMC_DDR_1_POWER_DOWN_STATUS 0x203c2040 /* Power down status */
-#define BCHP_MEMC_DDR_1_WARM_BOOT 0x203c2044 /* Warm boot control registers */
-#define BCHP_MEMC_DDR_1_DRAM_TIMING_0 0x203c2048 /* DDR-SDRAM Timing Register 0 */
-#define BCHP_MEMC_DDR_1_DRAM_TIMING_1 0x203c204c /* DDR-SDRAM Timing Register 1 */
-#define BCHP_MEMC_DDR_1_DRAM_TIMING_2 0x203c2050 /* Read to Write & write to read timing register */
-#define BCHP_MEMC_DDR_1_DRAM_TIMING_3 0x203c2054 /* DDR-SDRAM Timing Register 3 */
-#define BCHP_MEMC_DDR_1_DRAM_TIMING_4 0x203c2058 /* DDR-SDRAM Timing Register 4 */
-#define BCHP_MEMC_DDR_1_DRAM_TIMING_5 0x203c205c /* DDR-SDRAM Timing Register 5 */
-#define BCHP_MEMC_DDR_1_MIN_DQ_IDLE_CONTROL 0x203c2060 /* Minimum DQ Idle Time Control */
-#define BCHP_MEMC_DDR_1_PHY_OP_ACCESS_PENALTY 0x203c2064 /* PHY Operational Access Penalty Count. */
-#define BCHP_MEMC_DDR_1_CNTRLR_SM_TIMEOUT 0x203c2068 /* Memory Controller , state machine timeout register. */
-#define BCHP_MEMC_DDR_1_BANK_STATUS 0x203c206c /* Memory Controller, Bank Status Register */
-#define BCHP_MEMC_DDR_1_TESTER_LATENCY 0x203c2070 /* Memory Controller, Tester Latency Register. */
-#define BCHP_MEMC_DDR_1_SEQ_RING_BUF_DEPTH 0x203c2074 /* Sequencer Ring Buffer programmable depth. */
-#define BCHP_MEMC_DDR_1_SEQ_WRDATA_ERR_INFO 0x203c2078 /* Sequencer write data error info */
-#define BCHP_MEMC_DDR_1_SEQ_WRDATA_TRANSID_MISMATCH_INFO 0x203c207c /* Sequencer transaction ID mismatch error info */
-#define BCHP_MEMC_DDR_1_SEQ_CLEAR_VIOLATIONS 0x203c2080 /* Sequencer Violation Info register clear. */
-#define BCHP_MEMC_DDR_1_STAT_CONTROL 0x203c2084 /* Statistics Control register */
-#define BCHP_MEMC_DDR_1_STAT_TIMER 0x203c2088 /* Statistics Timer */
-#define BCHP_MEMC_DDR_1_STAT_IDLE_NOP 0x203c208c /* DRAM Idle_NOP Cycle Count Register. */
-#define BCHP_MEMC_DDR_1_STAT_MAX_IDLE_NOP 0x203c2090 /* Maximum DRAM idle_NOP cycle count register. */
-#define BCHP_MEMC_DDR_1_STAT_MIN_IDLE_NOP 0x203c2094 /* Minimum DRAM idle_NOP cycle count register. */
-#define BCHP_MEMC_DDR_1_STAT_CAS_ALL 0x203c2098 /* CAS Count Register. */
-#define BCHP_MEMC_DDR_1_STAT_MAX_CAS_ALL 0x203c209c /* Maximum DRAM CAS cycle count register. */
-#define BCHP_MEMC_DDR_1_STAT_MIN_CAS_ALL 0x203c20a0 /* Minimum DRAM CAS cycle count register. */
-#define BCHP_MEMC_DDR_1_STAT_PENALTY_ALL 0x203c20a4 /* DRAM Penalty Cycle Count register. */
-#define BCHP_MEMC_DDR_1_STAT_PENALTY_GDDRWM 0x203c20a8 /* GDDR Write Mask Penalty Cycle Count register. */
-#define BCHP_MEMC_DDR_1_STAT_MAX_TRANS_CYCLES_ALL 0x203c20ac /* Maximum number of transactions cycles (CAS+Penalty_ALL). */
-#define BCHP_MEMC_DDR_1_STAT_MIN_TRANS_CYCLES_ALL 0x203c20b0 /* Minimum number of transactions cycles (CAS+Penalty_ALL). */
-#define BCHP_MEMC_DDR_1_STAT_TRANS_READ_ALL 0x203c20b4 /* Number of overall system memory read transactions. */
-#define BCHP_MEMC_DDR_1_STAT_TRANS_WRITE_ALL 0x203c20b8 /* Number of overall system memory write transactions. */
-#define BCHP_MEMC_DDR_1_STAT_MAX_TRANS_ALL 0x203c20bc /* Maximum Number of Overall System memory transactions. */
-#define BCHP_MEMC_DDR_1_STAT_MIN_TRANS_ALL 0x203c20c0 /* Minimum Number of Overall System memory transactions. */
-#define BCHP_MEMC_DDR_1_STAT_CLIENT_SERVICE_CAS 0x203c20c4 /* Service CAS Cycle Count register. */
-#define BCHP_MEMC_DDR_1_STAT_MAX_CLIENT_SERVICE_CAS 0x203c20c8 /* Maximum service CAS cycle count register. */
-#define BCHP_MEMC_DDR_1_STAT_MIN_CLIENT_SERVICE_CAS 0x203c20cc /* Minimum service CAS cycle count register. */
-#define BCHP_MEMC_DDR_1_STAT_CLIENT_SERVICE_INTR_PENALTY 0x203c20d0 /* Service Intra DRAM Penalty Cycle Count register. */
-#define BCHP_MEMC_DDR_1_STAT_CLIENT_SERVICE_POST_PENALTY 0x203c20d4 /* Service Post DRAM Penalty Cycle Count register. */
-#define BCHP_MEMC_DDR_1_STAT_CLIENT_SERVICE_GDDRWM_PENALTY 0x203c20d8 /* Service GDDR Write Mask Penalty Cycle Count register. */
-#define BCHP_MEMC_DDR_1_STAT_MAX_CLIENT_SERVICE_CYCLES 0x203c20dc /* Maximum service cycle count register. */
-#define BCHP_MEMC_DDR_1_STAT_MIN_CLIENT_SERVICE_CYCLES 0x203c20e0 /* Minimum service cycle count register. */
-#define BCHP_MEMC_DDR_1_STAT_CLIENT_SERVICE_TRANS_READ 0x203c20e4 /* Service Read Transaction Count register. */
-#define BCHP_MEMC_DDR_1_STAT_CLIENT_SERVICE_TRANS_WRITE 0x203c20e8 /* Service Write Transaction Count register. */
-#define BCHP_MEMC_DDR_1_STAT_MAX_CLIENT_SERVICE_TRANS 0x203c20ec /* Maximum service Transaction count register. */
-#define BCHP_MEMC_DDR_1_STAT_MIN_CLIENT_SERVICE_TRANS 0x203c20f0 /* Minimum service cycle Transaction register. */
-#define BCHP_MEMC_DDR_1_STAT_CLIENT_SERVICE_LATENCY 0x203c20f4 /* Service Latency Count register. */
-#define BCHP_MEMC_DDR_1_STAT_MAX_CLIENT_SERVICE_LATENCY 0x203c20f8 /* Maximum Service Latency count register. */
-#define BCHP_MEMC_DDR_1_STAT_MIN_CLIENT_SERVICE_LATENCY 0x203c20fc /* Minimum Service Latency count register. */
-#define BCHP_MEMC_DDR_1_STAT_CLIENT_ABS_MAX_SERVICE_LATENCY 0x203c2100 /* Absolute Minimum Service Latency count register. */
-#define BCHP_MEMC_DDR_1_STAT_CLIENT_ABS_MIN_SERVICE_LATENCY 0x203c2104 /* Absolute Maximum Service Latency count register. */
-#define BCHP_MEMC_DDR_1_STAT_REFRESH 0x203c2108 /* Total number of refreshes issued. */
-#define BCHP_MEMC_DDR_1_STAT_MIN_DQ_IDLE_WRITE 0x203c210c /* Min DQ Idle Write event counter */
-#define BCHP_MEMC_DDR_1_STAT_MIN_DQ_IDLE_READ 0x203c2110 /* Min DQ Idle Read event counter */
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_0 0x203c2400 /* CAS or consumption cycle count register for client 0. */
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_1 0x203c2404 /* CAS or consumption cycle count register for client 1. */
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_2 0x203c2408 /* CAS or consumption cycle count register for client 2. */
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_3 0x203c240c /* CAS or consumption cycle count register for client 3. */
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_4 0x203c2410 /* CAS or consumption cycle count register for client 4. */
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_5 0x203c2414 /* CAS or consumption cycle count register for client 5. */
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_6 0x203c2418 /* CAS or consumption cycle count register for client 6. */
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_7 0x203c241c /* CAS or consumption cycle count register for client 7. */
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_8 0x203c2420 /* CAS or consumption cycle count register for client 8. */
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_9 0x203c2424 /* CAS or consumption cycle count register for client 9. */
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_10 0x203c2428 /* CAS or consumption cycle count register for client 10. */
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_11 0x203c242c /* CAS or consumption cycle count register for client 11. */
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_12 0x203c2430 /* CAS or consumption cycle count register for client 12. */
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_13 0x203c2434 /* CAS or consumption cycle count register for client 13. */
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_14 0x203c2438 /* CAS or consumption cycle count register for client 14. */
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_15 0x203c243c /* CAS or consumption cycle count register for client 15. */
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_16 0x203c2440 /* CAS or consumption cycle count register for client 16. */
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_17 0x203c2444 /* CAS or consumption cycle count register for client 17. */
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_18 0x203c2448 /* CAS or consumption cycle count register for client 18. */
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_19 0x203c244c /* CAS or consumption cycle count register for client 19. */
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_20 0x203c2450 /* CAS or consumption cycle count register for client 20. */
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_21 0x203c2454 /* CAS or consumption cycle count register for client 21. */
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_22 0x203c2458 /* CAS or consumption cycle count register for client 22. */
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_23 0x203c245c /* CAS or consumption cycle count register for client 23. */
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_24 0x203c2460 /* CAS or consumption cycle count register for client 24. */
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_25 0x203c2464 /* CAS or consumption cycle count register for client 25. */
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_26 0x203c2468 /* CAS or consumption cycle count register for client 26. */
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_27 0x203c246c /* CAS or consumption cycle count register for client 27. */
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_28 0x203c2470 /* CAS or consumption cycle count register for client 28. */
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_29 0x203c2474 /* CAS or consumption cycle count register for client 29. */
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_30 0x203c2478 /* CAS or consumption cycle count register for client 30. */
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_31 0x203c247c /* CAS or consumption cycle count register for client 31. */
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_32 0x203c2480 /* CAS or consumption cycle count register for client 32. */
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_33 0x203c2484 /* CAS or consumption cycle count register for client 33. */
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_34 0x203c2488 /* CAS or consumption cycle count register for client 34. */
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_35 0x203c248c /* CAS or consumption cycle count register for client 35. */
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_36 0x203c2490 /* CAS or consumption cycle count register for client 36. */
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_37 0x203c2494 /* CAS or consumption cycle count register for client 37. */
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_38 0x203c2498 /* CAS or consumption cycle count register for client 38. */
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_39 0x203c249c /* CAS or consumption cycle count register for client 39. */
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_40 0x203c24a0 /* CAS or consumption cycle count register for client 40. */
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_41 0x203c24a4 /* CAS or consumption cycle count register for client 41. */
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_42 0x203c24a8 /* CAS or consumption cycle count register for client 42. */
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_43 0x203c24ac /* CAS or consumption cycle count register for client 43. */
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_44 0x203c24b0 /* CAS or consumption cycle count register for client 44. */
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_45 0x203c24b4 /* CAS or consumption cycle count register for client 45. */
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_46 0x203c24b8 /* CAS or consumption cycle count register for client 46. */
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_47 0x203c24bc /* CAS or consumption cycle count register for client 47. */
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_48 0x203c24c0 /* CAS or consumption cycle count register for client 48. */
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_49 0x203c24c4 /* CAS or consumption cycle count register for client 49. */
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_50 0x203c24c8 /* CAS or consumption cycle count register for client 50. */
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_51 0x203c24cc /* CAS or consumption cycle count register for client 51. */
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_52 0x203c24d0 /* CAS or consumption cycle count register for client 52. */
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_53 0x203c24d4 /* CAS or consumption cycle count register for client 53. */
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_54 0x203c24d8 /* CAS or consumption cycle count register for client 54. */
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_55 0x203c24dc /* CAS or consumption cycle count register for client 55. */
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_56 0x203c24e0 /* CAS or consumption cycle count register for client 56. */
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_57 0x203c24e4 /* CAS or consumption cycle count register for client 57. */
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_58 0x203c24e8 /* CAS or consumption cycle count register for client 58. */
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_59 0x203c24ec /* CAS or consumption cycle count register for client 59. */
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_60 0x203c24f0 /* CAS or consumption cycle count register for client 60. */
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_61 0x203c24f4 /* CAS or consumption cycle count register for client 61. */
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_62 0x203c24f8 /* CAS or consumption cycle count register for client 62. */
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_63 0x203c24fc /* CAS or consumption cycle count register for client 63. */
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_64 0x203c2500 /* CAS or consumption cycle count register for client 64. */
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_65 0x203c2504 /* CAS or consumption cycle count register for client 65. */
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_66 0x203c2508 /* CAS or consumption cycle count register for client 66. */
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_67 0x203c250c /* CAS or consumption cycle count register for client 67. */
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_68 0x203c2510 /* CAS or consumption cycle count register for client 68. */
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_69 0x203c2514 /* CAS or consumption cycle count register for client 69. */
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_70 0x203c2518 /* CAS or consumption cycle count register for client 70. */
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_71 0x203c251c /* CAS or consumption cycle count register for client 71. */
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_72 0x203c2520 /* CAS or consumption cycle count register for client 72. */
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_73 0x203c2524 /* CAS or consumption cycle count register for client 73. */
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_74 0x203c2528 /* CAS or consumption cycle count register for client 74. */
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_75 0x203c252c /* CAS or consumption cycle count register for client 75. */
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_76 0x203c2530 /* CAS or consumption cycle count register for client 76. */
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_77 0x203c2534 /* CAS or consumption cycle count register for client 77. */
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_78 0x203c2538 /* CAS or consumption cycle count register for client 78. */
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_79 0x203c253c /* CAS or consumption cycle count register for client 79. */
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_80 0x203c2540 /* CAS or consumption cycle count register for client 80. */
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_81 0x203c2544 /* CAS or consumption cycle count register for client 81. */
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_82 0x203c2548 /* CAS or consumption cycle count register for client 82. */
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_83 0x203c254c /* CAS or consumption cycle count register for client 83. */
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_84 0x203c2550 /* CAS or consumption cycle count register for client 84. */
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_85 0x203c2554 /* CAS or consumption cycle count register for client 85. */
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_86 0x203c2558 /* CAS or consumption cycle count register for client 86. */
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_87 0x203c255c /* CAS or consumption cycle count register for client 87. */
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_88 0x203c2560 /* CAS or consumption cycle count register for client 88. */
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_89 0x203c2564 /* CAS or consumption cycle count register for client 89. */
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_90 0x203c2568 /* CAS or consumption cycle count register for client 90. */
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_91 0x203c256c /* CAS or consumption cycle count register for client 91. */
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_92 0x203c2570 /* CAS or consumption cycle count register for client 92. */
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_93 0x203c2574 /* CAS or consumption cycle count register for client 93. */
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_94 0x203c2578 /* CAS or consumption cycle count register for client 94. */
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_95 0x203c257c /* CAS or consumption cycle count register for client 95. */
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_96 0x203c2580 /* CAS or consumption cycle count register for client 96. */
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_97 0x203c2584 /* CAS or consumption cycle count register for client 97. */
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_98 0x203c2588 /* CAS or consumption cycle count register for client 98. */
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_99 0x203c258c /* CAS or consumption cycle count register for client 99. */
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_100 0x203c2590 /* CAS or consumption cycle count register for client 100. */
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_101 0x203c2594 /* CAS or consumption cycle count register for client 101. */
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_102 0x203c2598 /* CAS or consumption cycle count register for client 102. */
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_103 0x203c259c /* CAS or consumption cycle count register for client 103. */
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_104 0x203c25a0 /* CAS or consumption cycle count register for client 104. */
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_105 0x203c25a4 /* CAS or consumption cycle count register for client 105. */
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_106 0x203c25a8 /* CAS or consumption cycle count register for client 106. */
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_107 0x203c25ac /* CAS or consumption cycle count register for client 107. */
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_108 0x203c25b0 /* CAS or consumption cycle count register for client 108. */
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_109 0x203c25b4 /* CAS or consumption cycle count register for client 109. */
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_110 0x203c25b8 /* CAS or consumption cycle count register for client 110. */
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_111 0x203c25bc /* CAS or consumption cycle count register for client 111. */
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_112 0x203c25c0 /* CAS or consumption cycle count register for client 112. */
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_113 0x203c25c4 /* CAS or consumption cycle count register for client 113. */
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_114 0x203c25c8 /* CAS or consumption cycle count register for client 114. */
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_115 0x203c25cc /* CAS or consumption cycle count register for client 115. */
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_116 0x203c25d0 /* CAS or consumption cycle count register for client 116. */
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_117 0x203c25d4 /* CAS or consumption cycle count register for client 117. */
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_118 0x203c25d8 /* CAS or consumption cycle count register for client 118. */
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_119 0x203c25dc /* CAS or consumption cycle count register for client 119. */
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_120 0x203c25e0 /* CAS or consumption cycle count register for client 120. */
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_121 0x203c25e4 /* CAS or consumption cycle count register for client 121. */
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_122 0x203c25e8 /* CAS or consumption cycle count register for client 122. */
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_123 0x203c25ec /* CAS or consumption cycle count register for client 123. */
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_124 0x203c25f0 /* CAS or consumption cycle count register for client 124. */
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_125 0x203c25f4 /* CAS or consumption cycle count register for client 125. */
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_126 0x203c25f8 /* CAS or consumption cycle count register for client 126. */
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_127 0x203c25fc /* CAS or consumption cycle count register for client 127. */
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_128 0x203c2600 /* CAS or consumption cycle count register for client 128. */
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_129 0x203c2604 /* CAS or consumption cycle count register for client 129. */
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_130 0x203c2608 /* CAS or consumption cycle count register for client 130. */
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_131 0x203c260c /* CAS or consumption cycle count register for client 131. */
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_132 0x203c2610 /* CAS or consumption cycle count register for client 132. */
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_133 0x203c2614 /* CAS or consumption cycle count register for client 133. */
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_134 0x203c2618 /* CAS or consumption cycle count register for client 134. */
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_135 0x203c261c /* CAS or consumption cycle count register for client 135. */
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_136 0x203c2620 /* CAS or consumption cycle count register for client 136. */
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_137 0x203c2624 /* CAS or consumption cycle count register for client 137. */
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_138 0x203c2628 /* CAS or consumption cycle count register for client 138. */
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_139 0x203c262c /* CAS or consumption cycle count register for client 139. */
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_140 0x203c2630 /* CAS or consumption cycle count register for client 140. */
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_141 0x203c2634 /* CAS or consumption cycle count register for client 141. */
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_142 0x203c2638 /* CAS or consumption cycle count register for client 142. */
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_143 0x203c263c /* CAS or consumption cycle count register for client 143. */
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_144 0x203c2640 /* CAS or consumption cycle count register for client 144. */
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_145 0x203c2644 /* CAS or consumption cycle count register for client 145. */
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_146 0x203c2648 /* CAS or consumption cycle count register for client 146. */
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_147 0x203c264c /* CAS or consumption cycle count register for client 147. */
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_148 0x203c2650 /* CAS or consumption cycle count register for client 148. */
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_149 0x203c2654 /* CAS or consumption cycle count register for client 149. */
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_150 0x203c2658 /* CAS or consumption cycle count register for client 150. */
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_151 0x203c265c /* CAS or consumption cycle count register for client 151. */
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_152 0x203c2660 /* CAS or consumption cycle count register for client 152. */
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_153 0x203c2664 /* CAS or consumption cycle count register for client 153. */
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_154 0x203c2668 /* CAS or consumption cycle count register for client 154. */
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_155 0x203c266c /* CAS or consumption cycle count register for client 155. */
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_156 0x203c2670 /* CAS or consumption cycle count register for client 156. */
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_157 0x203c2674 /* CAS or consumption cycle count register for client 157. */
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_158 0x203c2678 /* CAS or consumption cycle count register for client 158. */
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_159 0x203c267c /* CAS or consumption cycle count register for client 159. */
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_160 0x203c2680 /* CAS or consumption cycle count register for client 160. */
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_161 0x203c2684 /* CAS or consumption cycle count register for client 161. */
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_162 0x203c2688 /* CAS or consumption cycle count register for client 162. */
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_163 0x203c268c /* CAS or consumption cycle count register for client 163. */
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_164 0x203c2690 /* CAS or consumption cycle count register for client 164. */
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_165 0x203c2694 /* CAS or consumption cycle count register for client 165. */
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_166 0x203c2698 /* CAS or consumption cycle count register for client 166. */
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_167 0x203c269c /* CAS or consumption cycle count register for client 167. */
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_168 0x203c26a0 /* CAS or consumption cycle count register for client 168. */
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_169 0x203c26a4 /* CAS or consumption cycle count register for client 169. */
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_170 0x203c26a8 /* CAS or consumption cycle count register for client 170. */
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_171 0x203c26ac /* CAS or consumption cycle count register for client 171. */
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_172 0x203c26b0 /* CAS or consumption cycle count register for client 172. */
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_173 0x203c26b4 /* CAS or consumption cycle count register for client 173. */
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_174 0x203c26b8 /* CAS or consumption cycle count register for client 174. */
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_175 0x203c26bc /* CAS or consumption cycle count register for client 175. */
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_176 0x203c26c0 /* CAS or consumption cycle count register for client 176. */
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_177 0x203c26c4 /* CAS or consumption cycle count register for client 177. */
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_178 0x203c26c8 /* CAS or consumption cycle count register for client 178. */
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_179 0x203c26cc /* CAS or consumption cycle count register for client 179. */
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_180 0x203c26d0 /* CAS or consumption cycle count register for client 180. */
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_181 0x203c26d4 /* CAS or consumption cycle count register for client 181. */
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_182 0x203c26d8 /* CAS or consumption cycle count register for client 182. */
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_183 0x203c26dc /* CAS or consumption cycle count register for client 183. */
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_184 0x203c26e0 /* CAS or consumption cycle count register for client 184. */
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_185 0x203c26e4 /* CAS or consumption cycle count register for client 185. */
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_186 0x203c26e8 /* CAS or consumption cycle count register for client 186. */
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_187 0x203c26ec /* CAS or consumption cycle count register for client 187. */
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_188 0x203c26f0 /* CAS or consumption cycle count register for client 188. */
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_189 0x203c26f4 /* CAS or consumption cycle count register for client 189. */
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_190 0x203c26f8 /* CAS or consumption cycle count register for client 190. */
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_191 0x203c26fc /* CAS or consumption cycle count register for client 191. */
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_192 0x203c2700 /* CAS or consumption cycle count register for client 192. */
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_193 0x203c2704 /* CAS or consumption cycle count register for client 193. */
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_194 0x203c2708 /* CAS or consumption cycle count register for client 194. */
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_195 0x203c270c /* CAS or consumption cycle count register for client 195. */
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_196 0x203c2710 /* CAS or consumption cycle count register for client 196. */
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_197 0x203c2714 /* CAS or consumption cycle count register for client 197. */
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_198 0x203c2718 /* CAS or consumption cycle count register for client 198. */
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_199 0x203c271c /* CAS or consumption cycle count register for client 199. */
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_200 0x203c2720 /* CAS or consumption cycle count register for client 200. */
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_201 0x203c2724 /* CAS or consumption cycle count register for client 201. */
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_202 0x203c2728 /* CAS or consumption cycle count register for client 202. */
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_203 0x203c272c /* CAS or consumption cycle count register for client 203. */
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_204 0x203c2730 /* CAS or consumption cycle count register for client 204. */
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_205 0x203c2734 /* CAS or consumption cycle count register for client 205. */
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_206 0x203c2738 /* CAS or consumption cycle count register for client 206. */
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_207 0x203c273c /* CAS or consumption cycle count register for client 207. */
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_208 0x203c2740 /* CAS or consumption cycle count register for client 208. */
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_209 0x203c2744 /* CAS or consumption cycle count register for client 209. */
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_210 0x203c2748 /* CAS or consumption cycle count register for client 210. */
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_211 0x203c274c /* CAS or consumption cycle count register for client 211. */
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_212 0x203c2750 /* CAS or consumption cycle count register for client 212. */
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_213 0x203c2754 /* CAS or consumption cycle count register for client 213. */
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_214 0x203c2758 /* CAS or consumption cycle count register for client 214. */
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_215 0x203c275c /* CAS or consumption cycle count register for client 215. */
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_216 0x203c2760 /* CAS or consumption cycle count register for client 216. */
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_217 0x203c2764 /* CAS or consumption cycle count register for client 217. */
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_218 0x203c2768 /* CAS or consumption cycle count register for client 218. */
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_219 0x203c276c /* CAS or consumption cycle count register for client 219. */
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_220 0x203c2770 /* CAS or consumption cycle count register for client 220. */
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_221 0x203c2774 /* CAS or consumption cycle count register for client 221. */
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_222 0x203c2778 /* CAS or consumption cycle count register for client 222. */
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_223 0x203c277c /* CAS or consumption cycle count register for client 223. */
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_224 0x203c2780 /* CAS or consumption cycle count register for client 224. */
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_225 0x203c2784 /* CAS or consumption cycle count register for client 225. */
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_226 0x203c2788 /* CAS or consumption cycle count register for client 226. */
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_227 0x203c278c /* CAS or consumption cycle count register for client 227. */
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_228 0x203c2790 /* CAS or consumption cycle count register for client 228. */
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_229 0x203c2794 /* CAS or consumption cycle count register for client 229. */
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_230 0x203c2798 /* CAS or consumption cycle count register for client 230. */
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_231 0x203c279c /* CAS or consumption cycle count register for client 231. */
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_232 0x203c27a0 /* CAS or consumption cycle count register for client 232. */
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_233 0x203c27a4 /* CAS or consumption cycle count register for client 233. */
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_234 0x203c27a8 /* CAS or consumption cycle count register for client 234. */
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_235 0x203c27ac /* CAS or consumption cycle count register for client 235. */
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_236 0x203c27b0 /* CAS or consumption cycle count register for client 236. */
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_237 0x203c27b4 /* CAS or consumption cycle count register for client 237. */
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_238 0x203c27b8 /* CAS or consumption cycle count register for client 238. */
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_239 0x203c27bc /* CAS or consumption cycle count register for client 239. */
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_240 0x203c27c0 /* CAS or consumption cycle count register for client 240. */
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_241 0x203c27c4 /* CAS or consumption cycle count register for client 241. */
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_242 0x203c27c8 /* CAS or consumption cycle count register for client 242. */
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_243 0x203c27cc /* CAS or consumption cycle count register for client 243. */
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_244 0x203c27d0 /* CAS or consumption cycle count register for client 244. */
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_245 0x203c27d4 /* CAS or consumption cycle count register for client 245. */
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_246 0x203c27d8 /* CAS or consumption cycle count register for client 246. */
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_247 0x203c27dc /* CAS or consumption cycle count register for client 247. */
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_248 0x203c27e0 /* CAS or consumption cycle count register for client 248. */
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_249 0x203c27e4 /* CAS or consumption cycle count register for client 249. */
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_250 0x203c27e8 /* CAS or consumption cycle count register for client 250. */
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_251 0x203c27ec /* CAS or consumption cycle count register for client 251. */
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_252 0x203c27f0 /* CAS or consumption cycle count register for client 252. */
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_253 0x203c27f4 /* CAS or consumption cycle count register for client 253. */
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_254 0x203c27f8 /* CAS or consumption cycle count register for client 254. */
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_255 0x203c27fc /* CAS or consumption cycle count register for client 255. */
-
-/***************************************************************************
- *CNTRLR_CONFIG - Memory Controller Configuration Register
- ***************************************************************************/
-/* MEMC_DDR_1 :: CNTRLR_CONFIG :: reserved0 [31:15] */
-#define BCHP_MEMC_DDR_1_CNTRLR_CONFIG_reserved0_MASK 0xffff8000
-#define BCHP_MEMC_DDR_1_CNTRLR_CONFIG_reserved0_SHIFT 15
-
-/* MEMC_DDR_1 :: CNTRLR_CONFIG :: GROUPAGE_ENABLE [14:14] */
-#define BCHP_MEMC_DDR_1_CNTRLR_CONFIG_GROUPAGE_ENABLE_MASK 0x00004000
-#define BCHP_MEMC_DDR_1_CNTRLR_CONFIG_GROUPAGE_ENABLE_SHIFT 14
-#define BCHP_MEMC_DDR_1_CNTRLR_CONFIG_GROUPAGE_ENABLE_DEFAULT 0x00000000
-
-/* MEMC_DDR_1 :: CNTRLR_CONFIG :: MODIFY_RASTER_ADDR [13:13] */
-#define BCHP_MEMC_DDR_1_CNTRLR_CONFIG_MODIFY_RASTER_ADDR_MASK 0x00002000
-#define BCHP_MEMC_DDR_1_CNTRLR_CONFIG_MODIFY_RASTER_ADDR_SHIFT 13
-#define BCHP_MEMC_DDR_1_CNTRLR_CONFIG_MODIFY_RASTER_ADDR_DEFAULT 0x00000001
-
-/* MEMC_DDR_1 :: CNTRLR_CONFIG :: DRAM_COMMANDS_2T [12:12] */
-#define BCHP_MEMC_DDR_1_CNTRLR_CONFIG_DRAM_COMMANDS_2T_MASK 0x00001000
-#define BCHP_MEMC_DDR_1_CNTRLR_CONFIG_DRAM_COMMANDS_2T_SHIFT 12
-#define BCHP_MEMC_DDR_1_CNTRLR_CONFIG_DRAM_COMMANDS_2T_DEFAULT 0x00000000
-
-/* MEMC_DDR_1 :: CNTRLR_CONFIG :: DRAM_TOTAL_WIDTH [11:10] */
-#define BCHP_MEMC_DDR_1_CNTRLR_CONFIG_DRAM_TOTAL_WIDTH_MASK 0x00000c00
-#define BCHP_MEMC_DDR_1_CNTRLR_CONFIG_DRAM_TOTAL_WIDTH_SHIFT 10
-#define BCHP_MEMC_DDR_1_CNTRLR_CONFIG_DRAM_TOTAL_WIDTH_DEFAULT 0x00000002
-#define BCHP_MEMC_DDR_1_CNTRLR_CONFIG_DRAM_TOTAL_WIDTH_reserved_x8 0
-#define BCHP_MEMC_DDR_1_CNTRLR_CONFIG_DRAM_TOTAL_WIDTH_x16 1
-#define BCHP_MEMC_DDR_1_CNTRLR_CONFIG_DRAM_TOTAL_WIDTH_x32 2
-#define BCHP_MEMC_DDR_1_CNTRLR_CONFIG_DRAM_TOTAL_WIDTH_reserved_x64 3
-
-/* MEMC_DDR_1 :: CNTRLR_CONFIG :: DRAM_DEVICE_WIDTH [09:08] */
-#define BCHP_MEMC_DDR_1_CNTRLR_CONFIG_DRAM_DEVICE_WIDTH_MASK 0x00000300
-#define BCHP_MEMC_DDR_1_CNTRLR_CONFIG_DRAM_DEVICE_WIDTH_SHIFT 8
-#define BCHP_MEMC_DDR_1_CNTRLR_CONFIG_DRAM_DEVICE_WIDTH_DEFAULT 0x00000001
-#define BCHP_MEMC_DDR_1_CNTRLR_CONFIG_DRAM_DEVICE_WIDTH_x8 0
-#define BCHP_MEMC_DDR_1_CNTRLR_CONFIG_DRAM_DEVICE_WIDTH_x16 1
-#define BCHP_MEMC_DDR_1_CNTRLR_CONFIG_DRAM_DEVICE_WIDTH_reserved_2 2
-#define BCHP_MEMC_DDR_1_CNTRLR_CONFIG_DRAM_DEVICE_WIDTH_reserved_3 3
-
-/* MEMC_DDR_1 :: CNTRLR_CONFIG :: DRAM_DEVICE_SIZE [07:04] */
-#define BCHP_MEMC_DDR_1_CNTRLR_CONFIG_DRAM_DEVICE_SIZE_MASK 0x000000f0
-#define BCHP_MEMC_DDR_1_CNTRLR_CONFIG_DRAM_DEVICE_SIZE_SHIFT 4
-#define BCHP_MEMC_DDR_1_CNTRLR_CONFIG_DRAM_DEVICE_SIZE_DEFAULT 0x00000003
-#define BCHP_MEMC_DDR_1_CNTRLR_CONFIG_DRAM_DEVICE_SIZE_reserved_256_Mb 0
-#define BCHP_MEMC_DDR_1_CNTRLR_CONFIG_DRAM_DEVICE_SIZE_512_Mb 1
-#define BCHP_MEMC_DDR_1_CNTRLR_CONFIG_DRAM_DEVICE_SIZE_1_Gb 2
-#define BCHP_MEMC_DDR_1_CNTRLR_CONFIG_DRAM_DEVICE_SIZE_2_Gb 3
-#define BCHP_MEMC_DDR_1_CNTRLR_CONFIG_DRAM_DEVICE_SIZE_4_Gb 4
-#define BCHP_MEMC_DDR_1_CNTRLR_CONFIG_DRAM_DEVICE_SIZE_8_Gb 5
-#define BCHP_MEMC_DDR_1_CNTRLR_CONFIG_DRAM_DEVICE_SIZE_16_Gb 6
-#define BCHP_MEMC_DDR_1_CNTRLR_CONFIG_DRAM_DEVICE_SIZE_reserved_7 7
-#define BCHP_MEMC_DDR_1_CNTRLR_CONFIG_DRAM_DEVICE_SIZE_reserved_8 8
-#define BCHP_MEMC_DDR_1_CNTRLR_CONFIG_DRAM_DEVICE_SIZE_reserved_9 9
-#define BCHP_MEMC_DDR_1_CNTRLR_CONFIG_DRAM_DEVICE_SIZE_reserved_10 10
-#define BCHP_MEMC_DDR_1_CNTRLR_CONFIG_DRAM_DEVICE_SIZE_reserved_11 11
-#define BCHP_MEMC_DDR_1_CNTRLR_CONFIG_DRAM_DEVICE_SIZE_reserved_12 12
-#define BCHP_MEMC_DDR_1_CNTRLR_CONFIG_DRAM_DEVICE_SIZE_reserved_13 13
-#define BCHP_MEMC_DDR_1_CNTRLR_CONFIG_DRAM_DEVICE_SIZE_reserved_14 14
-#define BCHP_MEMC_DDR_1_CNTRLR_CONFIG_DRAM_DEVICE_SIZE_reserved_15 15
-
-/* MEMC_DDR_1 :: CNTRLR_CONFIG :: DRAM_DEVICE_TYPE [03:00] */
-#define BCHP_MEMC_DDR_1_CNTRLR_CONFIG_DRAM_DEVICE_TYPE_MASK 0x0000000f
-#define BCHP_MEMC_DDR_1_CNTRLR_CONFIG_DRAM_DEVICE_TYPE_SHIFT 0
-#define BCHP_MEMC_DDR_1_CNTRLR_CONFIG_DRAM_DEVICE_TYPE_DEFAULT 0x00000001
-#define BCHP_MEMC_DDR_1_CNTRLR_CONFIG_DRAM_DEVICE_TYPE_reserved_DDR2 0
-#define BCHP_MEMC_DDR_1_CNTRLR_CONFIG_DRAM_DEVICE_TYPE_DDR3 1
-#define BCHP_MEMC_DDR_1_CNTRLR_CONFIG_DRAM_DEVICE_TYPE_DDR4 2
-#define BCHP_MEMC_DDR_1_CNTRLR_CONFIG_DRAM_DEVICE_TYPE_GDDR5M 3
-#define BCHP_MEMC_DDR_1_CNTRLR_CONFIG_DRAM_DEVICE_TYPE_GDDR5 4
-#define BCHP_MEMC_DDR_1_CNTRLR_CONFIG_DRAM_DEVICE_TYPE_reserved_5 5
-#define BCHP_MEMC_DDR_1_CNTRLR_CONFIG_DRAM_DEVICE_TYPE_reserved_6 6
-#define BCHP_MEMC_DDR_1_CNTRLR_CONFIG_DRAM_DEVICE_TYPE_reserved_7 7
-#define BCHP_MEMC_DDR_1_CNTRLR_CONFIG_DRAM_DEVICE_TYPE_reserved_8 8
-#define BCHP_MEMC_DDR_1_CNTRLR_CONFIG_DRAM_DEVICE_TYPE_reserved_9 9
-#define BCHP_MEMC_DDR_1_CNTRLR_CONFIG_DRAM_DEVICE_TYPE_reserved_10 10
-#define BCHP_MEMC_DDR_1_CNTRLR_CONFIG_DRAM_DEVICE_TYPE_reserved_11 11
-#define BCHP_MEMC_DDR_1_CNTRLR_CONFIG_DRAM_DEVICE_TYPE_reserved_12 12
-#define BCHP_MEMC_DDR_1_CNTRLR_CONFIG_DRAM_DEVICE_TYPE_reserved_13 13
-#define BCHP_MEMC_DDR_1_CNTRLR_CONFIG_DRAM_DEVICE_TYPE_reserved_14 14
-#define BCHP_MEMC_DDR_1_CNTRLR_CONFIG_DRAM_DEVICE_TYPE_reserved_15 15
-
-/***************************************************************************
- *DRAM_INIT_CNTRL - Dram initialization control
- ***************************************************************************/
-/* MEMC_DDR_1 :: DRAM_INIT_CNTRL :: reserved0 [31:06] */
-#define BCHP_MEMC_DDR_1_DRAM_INIT_CNTRL_reserved0_MASK 0xffffffc0
-#define BCHP_MEMC_DDR_1_DRAM_INIT_CNTRL_reserved0_SHIFT 6
-
-/* MEMC_DDR_1 :: DRAM_INIT_CNTRL :: IGNORE_PHY_REQUEST_AT_RESET [05:05] */
-#define BCHP_MEMC_DDR_1_DRAM_INIT_CNTRL_IGNORE_PHY_REQUEST_AT_RESET_MASK 0x00000020
-#define BCHP_MEMC_DDR_1_DRAM_INIT_CNTRL_IGNORE_PHY_REQUEST_AT_RESET_SHIFT 5
-#define BCHP_MEMC_DDR_1_DRAM_INIT_CNTRL_IGNORE_PHY_REQUEST_AT_RESET_DEFAULT 0x00000000
-
-/* MEMC_DDR_1 :: DRAM_INIT_CNTRL :: ENTER_PHY_OP_STATE [04:04] */
-#define BCHP_MEMC_DDR_1_DRAM_INIT_CNTRL_ENTER_PHY_OP_STATE_MASK 0x00000010
-#define BCHP_MEMC_DDR_1_DRAM_INIT_CNTRL_ENTER_PHY_OP_STATE_SHIFT 4
-#define BCHP_MEMC_DDR_1_DRAM_INIT_CNTRL_ENTER_PHY_OP_STATE_DEFAULT 0x00000000
-
-/* MEMC_DDR_1 :: DRAM_INIT_CNTRL :: ENABLE_AUTO_PHY_OP_ACCESS [03:03] */
-#define BCHP_MEMC_DDR_1_DRAM_INIT_CNTRL_ENABLE_AUTO_PHY_OP_ACCESS_MASK 0x00000008
-#define BCHP_MEMC_DDR_1_DRAM_INIT_CNTRL_ENABLE_AUTO_PHY_OP_ACCESS_SHIFT 3
-#define BCHP_MEMC_DDR_1_DRAM_INIT_CNTRL_ENABLE_AUTO_PHY_OP_ACCESS_DEFAULT 0x00000000
-
-/* MEMC_DDR_1 :: DRAM_INIT_CNTRL :: OVERRIDE_PHY_INIT_COMPLETE [02:02] */
-#define BCHP_MEMC_DDR_1_DRAM_INIT_CNTRL_OVERRIDE_PHY_INIT_COMPLETE_MASK 0x00000004
-#define BCHP_MEMC_DDR_1_DRAM_INIT_CNTRL_OVERRIDE_PHY_INIT_COMPLETE_SHIFT 2
-#define BCHP_MEMC_DDR_1_DRAM_INIT_CNTRL_OVERRIDE_PHY_INIT_COMPLETE_DEFAULT 0x00000000
-
-/* MEMC_DDR_1 :: DRAM_INIT_CNTRL :: OVERRIDE_PHY_DFI_GRANT [01:01] */
-#define BCHP_MEMC_DDR_1_DRAM_INIT_CNTRL_OVERRIDE_PHY_DFI_GRANT_MASK 0x00000002
-#define BCHP_MEMC_DDR_1_DRAM_INIT_CNTRL_OVERRIDE_PHY_DFI_GRANT_SHIFT 1
-#define BCHP_MEMC_DDR_1_DRAM_INIT_CNTRL_OVERRIDE_PHY_DFI_GRANT_DEFAULT 0x00000000
-
-/* MEMC_DDR_1 :: DRAM_INIT_CNTRL :: PHY_DFI_GRANT_VALUE [00:00] */
-#define BCHP_MEMC_DDR_1_DRAM_INIT_CNTRL_PHY_DFI_GRANT_VALUE_MASK 0x00000001
-#define BCHP_MEMC_DDR_1_DRAM_INIT_CNTRL_PHY_DFI_GRANT_VALUE_SHIFT 0
-#define BCHP_MEMC_DDR_1_DRAM_INIT_CNTRL_PHY_DFI_GRANT_VALUE_DEFAULT 0x00000000
-
-/***************************************************************************
- *DRAM_INIT_STATUS - Dram initialization status
- ***************************************************************************/
-/* MEMC_DDR_1 :: DRAM_INIT_STATUS :: reserved0 [31:02] */
-#define BCHP_MEMC_DDR_1_DRAM_INIT_STATUS_reserved0_MASK 0xfffffffc
-#define BCHP_MEMC_DDR_1_DRAM_INIT_STATUS_reserved0_SHIFT 2
-
-/* MEMC_DDR_1 :: DRAM_INIT_STATUS :: PHY_DFI_REQUEST_VALUE [01:01] */
-#define BCHP_MEMC_DDR_1_DRAM_INIT_STATUS_PHY_DFI_REQUEST_VALUE_MASK 0x00000002
-#define BCHP_MEMC_DDR_1_DRAM_INIT_STATUS_PHY_DFI_REQUEST_VALUE_SHIFT 1
-#define BCHP_MEMC_DDR_1_DRAM_INIT_STATUS_PHY_DFI_REQUEST_VALUE_DEFAULT 0x00000000
-
-/* MEMC_DDR_1 :: DRAM_INIT_STATUS :: INIT_DONE [00:00] */
-#define BCHP_MEMC_DDR_1_DRAM_INIT_STATUS_INIT_DONE_MASK 0x00000001
-#define BCHP_MEMC_DDR_1_DRAM_INIT_STATUS_INIT_DONE_SHIFT 0
-#define BCHP_MEMC_DDR_1_DRAM_INIT_STATUS_INIT_DONE_DEFAULT 0x00000000
-
-/***************************************************************************
- *DRAM_MODE_0 - Dram Mode Register 0
- ***************************************************************************/
-/* MEMC_DDR_1 :: DRAM_MODE_0 :: reserved0 [31:16] */
-#define BCHP_MEMC_DDR_1_DRAM_MODE_0_reserved0_MASK 0xffff0000
-#define BCHP_MEMC_DDR_1_DRAM_MODE_0_reserved0_SHIFT 16
-
-/* MEMC_DDR_1 :: DRAM_MODE_0 :: unused_0 [15:13] */
-#define BCHP_MEMC_DDR_1_DRAM_MODE_0_unused_0_MASK 0x0000e000
-#define BCHP_MEMC_DDR_1_DRAM_MODE_0_unused_0_SHIFT 13
-#define BCHP_MEMC_DDR_1_DRAM_MODE_0_unused_0_DEFAULT 0x00000000
-
-/* union - case DDR3 [12:00] */
-/* MEMC_DDR_1 :: DRAM_MODE_0 :: DDR3 :: DLL_CNTRL_PPD [12:12] */
-#define BCHP_MEMC_DDR_1_DRAM_MODE_0_DDR3_DLL_CNTRL_PPD_MASK 0x00001000
-#define BCHP_MEMC_DDR_1_DRAM_MODE_0_DDR3_DLL_CNTRL_PPD_SHIFT 12
-#define BCHP_MEMC_DDR_1_DRAM_MODE_0_DDR3_DLL_CNTRL_PPD_DEFAULT 0x00000000
-
-/* MEMC_DDR_1 :: DRAM_MODE_0 :: DDR3 :: WR [11:09] */
-#define BCHP_MEMC_DDR_1_DRAM_MODE_0_DDR3_WR_MASK 0x00000e00
-#define BCHP_MEMC_DDR_1_DRAM_MODE_0_DDR3_WR_SHIFT 9
-#define BCHP_MEMC_DDR_1_DRAM_MODE_0_DDR3_WR_DEFAULT 0x00000004
-
-/* MEMC_DDR_1 :: DRAM_MODE_0 :: DDR3 :: DLL_RST [08:08] */
-#define BCHP_MEMC_DDR_1_DRAM_MODE_0_DDR3_DLL_RST_MASK 0x00000100
-#define BCHP_MEMC_DDR_1_DRAM_MODE_0_DDR3_DLL_RST_SHIFT 8
-#define BCHP_MEMC_DDR_1_DRAM_MODE_0_DDR3_DLL_RST_DEFAULT 0x00000000
-
-/* MEMC_DDR_1 :: DRAM_MODE_0 :: DDR3 :: TEST_MODE [07:07] */
-#define BCHP_MEMC_DDR_1_DRAM_MODE_0_DDR3_TEST_MODE_MASK 0x00000080
-#define BCHP_MEMC_DDR_1_DRAM_MODE_0_DDR3_TEST_MODE_SHIFT 7
-#define BCHP_MEMC_DDR_1_DRAM_MODE_0_DDR3_TEST_MODE_DEFAULT 0x00000000
-
-/* MEMC_DDR_1 :: DRAM_MODE_0 :: DDR3 :: CL_3_1 [06:04] */
-#define BCHP_MEMC_DDR_1_DRAM_MODE_0_DDR3_CL_3_1_MASK 0x00000070
-#define BCHP_MEMC_DDR_1_DRAM_MODE_0_DDR3_CL_3_1_SHIFT 4
-#define BCHP_MEMC_DDR_1_DRAM_MODE_0_DDR3_CL_3_1_DEFAULT 0x00000004
-
-/* MEMC_DDR_1 :: DRAM_MODE_0 :: DDR3 :: RBT [03:03] */
-#define BCHP_MEMC_DDR_1_DRAM_MODE_0_DDR3_RBT_MASK 0x00000008
-#define BCHP_MEMC_DDR_1_DRAM_MODE_0_DDR3_RBT_SHIFT 3
-#define BCHP_MEMC_DDR_1_DRAM_MODE_0_DDR3_RBT_DEFAULT 0x00000000
-
-/* MEMC_DDR_1 :: DRAM_MODE_0 :: DDR3 :: CL_0 [02:02] */
-#define BCHP_MEMC_DDR_1_DRAM_MODE_0_DDR3_CL_0_MASK 0x00000004
-#define BCHP_MEMC_DDR_1_DRAM_MODE_0_DDR3_CL_0_SHIFT 2
-#define BCHP_MEMC_DDR_1_DRAM_MODE_0_DDR3_CL_0_DEFAULT 0x00000000
-
-/* MEMC_DDR_1 :: DRAM_MODE_0 :: DDR3 :: BL [01:00] */
-#define BCHP_MEMC_DDR_1_DRAM_MODE_0_DDR3_BL_MASK 0x00000003
-#define BCHP_MEMC_DDR_1_DRAM_MODE_0_DDR3_BL_SHIFT 0
-#define BCHP_MEMC_DDR_1_DRAM_MODE_0_DDR3_BL_DEFAULT 0x00000000
-
-/* union - case DDR4 [12:00] */
-/* MEMC_DDR_1 :: DRAM_MODE_0 :: DDR4 :: unused_1 [12:12] */
-#define BCHP_MEMC_DDR_1_DRAM_MODE_0_DDR4_unused_1_MASK 0x00001000
-#define BCHP_MEMC_DDR_1_DRAM_MODE_0_DDR4_unused_1_SHIFT 12
-#define BCHP_MEMC_DDR_1_DRAM_MODE_0_DDR4_unused_1_DEFAULT 0x00000000
-
-/* MEMC_DDR_1 :: DRAM_MODE_0 :: DDR4 :: WR [11:09] */
-#define BCHP_MEMC_DDR_1_DRAM_MODE_0_DDR4_WR_MASK 0x00000e00
-#define BCHP_MEMC_DDR_1_DRAM_MODE_0_DDR4_WR_SHIFT 9
-#define BCHP_MEMC_DDR_1_DRAM_MODE_0_DDR4_WR_DEFAULT 0x00000004
-
-/* MEMC_DDR_1 :: DRAM_MODE_0 :: DDR4 :: DLL_RST [08:08] */
-#define BCHP_MEMC_DDR_1_DRAM_MODE_0_DDR4_DLL_RST_MASK 0x00000100
-#define BCHP_MEMC_DDR_1_DRAM_MODE_0_DDR4_DLL_RST_SHIFT 8
-#define BCHP_MEMC_DDR_1_DRAM_MODE_0_DDR4_DLL_RST_DEFAULT 0x00000000
-
-/* MEMC_DDR_1 :: DRAM_MODE_0 :: DDR4 :: TEST_MODE [07:07] */
-#define BCHP_MEMC_DDR_1_DRAM_MODE_0_DDR4_TEST_MODE_MASK 0x00000080
-#define BCHP_MEMC_DDR_1_DRAM_MODE_0_DDR4_TEST_MODE_SHIFT 7
-#define BCHP_MEMC_DDR_1_DRAM_MODE_0_DDR4_TEST_MODE_DEFAULT 0x00000000
-
-/* MEMC_DDR_1 :: DRAM_MODE_0 :: DDR4 :: CL_3_1 [06:04] */
-#define BCHP_MEMC_DDR_1_DRAM_MODE_0_DDR4_CL_3_1_MASK 0x00000070
-#define BCHP_MEMC_DDR_1_DRAM_MODE_0_DDR4_CL_3_1_SHIFT 4
-#define BCHP_MEMC_DDR_1_DRAM_MODE_0_DDR4_CL_3_1_DEFAULT 0x00000004
-
-/* MEMC_DDR_1 :: DRAM_MODE_0 :: DDR4 :: BT [03:03] */
-#define BCHP_MEMC_DDR_1_DRAM_MODE_0_DDR4_BT_MASK 0x00000008
-#define BCHP_MEMC_DDR_1_DRAM_MODE_0_DDR4_BT_SHIFT 3
-#define BCHP_MEMC_DDR_1_DRAM_MODE_0_DDR4_BT_DEFAULT 0x00000000
-
-/* MEMC_DDR_1 :: DRAM_MODE_0 :: DDR4 :: CL_0 [02:02] */
-#define BCHP_MEMC_DDR_1_DRAM_MODE_0_DDR4_CL_0_MASK 0x00000004
-#define BCHP_MEMC_DDR_1_DRAM_MODE_0_DDR4_CL_0_SHIFT 2
-#define BCHP_MEMC_DDR_1_DRAM_MODE_0_DDR4_CL_0_DEFAULT 0x00000000
-
-/* MEMC_DDR_1 :: DRAM_MODE_0 :: DDR4 :: BL [01:00] */
-#define BCHP_MEMC_DDR_1_DRAM_MODE_0_DDR4_BL_MASK 0x00000003
-#define BCHP_MEMC_DDR_1_DRAM_MODE_0_DDR4_BL_SHIFT 0
-#define BCHP_MEMC_DDR_1_DRAM_MODE_0_DDR4_BL_DEFAULT 0x00000000
-
-/* union - case GDDR5M [12:00] */
-/* MEMC_DDR_1 :: DRAM_MODE_0 :: GDDR5M :: unused_1 [12:12] */
-#define BCHP_MEMC_DDR_1_DRAM_MODE_0_GDDR5M_unused_1_MASK 0x00001000
-#define BCHP_MEMC_DDR_1_DRAM_MODE_0_GDDR5M_unused_1_SHIFT 12
-#define BCHP_MEMC_DDR_1_DRAM_MODE_0_GDDR5M_unused_1_DEFAULT 0x00000000
-
-/* MEMC_DDR_1 :: DRAM_MODE_0 :: GDDR5M :: WR [11:08] */
-#define BCHP_MEMC_DDR_1_DRAM_MODE_0_GDDR5M_WR_MASK 0x00000f00
-#define BCHP_MEMC_DDR_1_DRAM_MODE_0_GDDR5M_WR_SHIFT 8
-#define BCHP_MEMC_DDR_1_DRAM_MODE_0_GDDR5M_WR_DEFAULT 0x00000008
-
-/* MEMC_DDR_1 :: DRAM_MODE_0 :: GDDR5M :: TEST_MODE [07:07] */
-#define BCHP_MEMC_DDR_1_DRAM_MODE_0_GDDR5M_TEST_MODE_MASK 0x00000080
-#define BCHP_MEMC_DDR_1_DRAM_MODE_0_GDDR5M_TEST_MODE_SHIFT 7
-#define BCHP_MEMC_DDR_1_DRAM_MODE_0_GDDR5M_TEST_MODE_DEFAULT 0x00000000
-
-/* MEMC_DDR_1 :: DRAM_MODE_0 :: GDDR5M :: CL [06:03] */
-#define BCHP_MEMC_DDR_1_DRAM_MODE_0_GDDR5M_CL_MASK 0x00000078
-#define BCHP_MEMC_DDR_1_DRAM_MODE_0_GDDR5M_CL_SHIFT 3
-#define BCHP_MEMC_DDR_1_DRAM_MODE_0_GDDR5M_CL_DEFAULT 0x00000009
-
-/* MEMC_DDR_1 :: DRAM_MODE_0 :: GDDR5M :: WL [02:00] */
-#define BCHP_MEMC_DDR_1_DRAM_MODE_0_GDDR5M_WL_MASK 0x00000007
-#define BCHP_MEMC_DDR_1_DRAM_MODE_0_GDDR5M_WL_SHIFT 0
-#define BCHP_MEMC_DDR_1_DRAM_MODE_0_GDDR5M_WL_DEFAULT 0x00000004
-
-/* union - case GDDR5 [12:00] */
-/* MEMC_DDR_1 :: DRAM_MODE_0 :: GDDR5 :: unused_1 [12:12] */
-#define BCHP_MEMC_DDR_1_DRAM_MODE_0_GDDR5_unused_1_MASK 0x00001000
-#define BCHP_MEMC_DDR_1_DRAM_MODE_0_GDDR5_unused_1_SHIFT 12
-#define BCHP_MEMC_DDR_1_DRAM_MODE_0_GDDR5_unused_1_DEFAULT 0x00000000
-
-/* MEMC_DDR_1 :: DRAM_MODE_0 :: GDDR5 :: WR [11:08] */
-#define BCHP_MEMC_DDR_1_DRAM_MODE_0_GDDR5_WR_MASK 0x00000f00
-#define BCHP_MEMC_DDR_1_DRAM_MODE_0_GDDR5_WR_SHIFT 8
-#define BCHP_MEMC_DDR_1_DRAM_MODE_0_GDDR5_WR_DEFAULT 0x00000008
-
-/* MEMC_DDR_1 :: DRAM_MODE_0 :: GDDR5 :: TEST_MODE [07:07] */
-#define BCHP_MEMC_DDR_1_DRAM_MODE_0_GDDR5_TEST_MODE_MASK 0x00000080
-#define BCHP_MEMC_DDR_1_DRAM_MODE_0_GDDR5_TEST_MODE_SHIFT 7
-#define BCHP_MEMC_DDR_1_DRAM_MODE_0_GDDR5_TEST_MODE_DEFAULT 0x00000000
-
-/* MEMC_DDR_1 :: DRAM_MODE_0 :: GDDR5 :: CL [06:03] */
-#define BCHP_MEMC_DDR_1_DRAM_MODE_0_GDDR5_CL_MASK 0x00000078
-#define BCHP_MEMC_DDR_1_DRAM_MODE_0_GDDR5_CL_SHIFT 3
-#define BCHP_MEMC_DDR_1_DRAM_MODE_0_GDDR5_CL_DEFAULT 0x00000009
-
-/* MEMC_DDR_1 :: DRAM_MODE_0 :: GDDR5 :: WL [02:00] */
-#define BCHP_MEMC_DDR_1_DRAM_MODE_0_GDDR5_WL_MASK 0x00000007
-#define BCHP_MEMC_DDR_1_DRAM_MODE_0_GDDR5_WL_SHIFT 0
-#define BCHP_MEMC_DDR_1_DRAM_MODE_0_GDDR5_WL_DEFAULT 0x00000004
-
-/***************************************************************************
- *DRAM_MODE_1 - Dram Mode Register 1
- ***************************************************************************/
-/* MEMC_DDR_1 :: DRAM_MODE_1 :: reserved0 [31:16] */
-#define BCHP_MEMC_DDR_1_DRAM_MODE_1_reserved0_MASK 0xffff0000
-#define BCHP_MEMC_DDR_1_DRAM_MODE_1_reserved0_SHIFT 16
-
-/* MEMC_DDR_1 :: DRAM_MODE_1 :: unused_0 [15:13] */
-#define BCHP_MEMC_DDR_1_DRAM_MODE_1_unused_0_MASK 0x0000e000
-#define BCHP_MEMC_DDR_1_DRAM_MODE_1_unused_0_SHIFT 13
-#define BCHP_MEMC_DDR_1_DRAM_MODE_1_unused_0_DEFAULT 0x00000000
-
-/* union - case DDR3 [12:00] */
-/* MEMC_DDR_1 :: DRAM_MODE_1 :: DDR3 :: Q_OFF [12:12] */
-#define BCHP_MEMC_DDR_1_DRAM_MODE_1_DDR3_Q_OFF_MASK 0x00001000
-#define BCHP_MEMC_DDR_1_DRAM_MODE_1_DDR3_Q_OFF_SHIFT 12
-#define BCHP_MEMC_DDR_1_DRAM_MODE_1_DDR3_Q_OFF_DEFAULT 0x00000000
-#define BCHP_MEMC_DDR_1_DRAM_MODE_1_DDR3_Q_OFF_ENABLE 0
-#define BCHP_MEMC_DDR_1_DRAM_MODE_1_DDR3_Q_OFF_DISABLE 1
-
-/* MEMC_DDR_1 :: DRAM_MODE_1 :: DDR3 :: TDQS [11:11] */
-#define BCHP_MEMC_DDR_1_DRAM_MODE_1_DDR3_TDQS_MASK 0x00000800
-#define BCHP_MEMC_DDR_1_DRAM_MODE_1_DDR3_TDQS_SHIFT 11
-#define BCHP_MEMC_DDR_1_DRAM_MODE_1_DDR3_TDQS_DEFAULT 0x00000000
-#define BCHP_MEMC_DDR_1_DRAM_MODE_1_DDR3_TDQS_ENABLE 1
-#define BCHP_MEMC_DDR_1_DRAM_MODE_1_DDR3_TDQS_DISABLE 0
-
-/* MEMC_DDR_1 :: DRAM_MODE_1 :: DDR3 :: unused_1 [10:10] */
-#define BCHP_MEMC_DDR_1_DRAM_MODE_1_DDR3_unused_1_MASK 0x00000400
-#define BCHP_MEMC_DDR_1_DRAM_MODE_1_DDR3_unused_1_SHIFT 10
-#define BCHP_MEMC_DDR_1_DRAM_MODE_1_DDR3_unused_1_DEFAULT 0x00000000
-
-/* MEMC_DDR_1 :: DRAM_MODE_1 :: DDR3 :: ODT_CNTRL_2 [09:09] */
-#define BCHP_MEMC_DDR_1_DRAM_MODE_1_DDR3_ODT_CNTRL_2_MASK 0x00000200
-#define BCHP_MEMC_DDR_1_DRAM_MODE_1_DDR3_ODT_CNTRL_2_SHIFT 9
-#define BCHP_MEMC_DDR_1_DRAM_MODE_1_DDR3_ODT_CNTRL_2_DEFAULT 0x00000000
-
-/* MEMC_DDR_1 :: DRAM_MODE_1 :: DDR3 :: unused_2 [08:08] */
-#define BCHP_MEMC_DDR_1_DRAM_MODE_1_DDR3_unused_2_MASK 0x00000100
-#define BCHP_MEMC_DDR_1_DRAM_MODE_1_DDR3_unused_2_SHIFT 8
-#define BCHP_MEMC_DDR_1_DRAM_MODE_1_DDR3_unused_2_DEFAULT 0x00000000
-
-/* MEMC_DDR_1 :: DRAM_MODE_1 :: DDR3 :: WR_LEVEL [07:07] */
-#define BCHP_MEMC_DDR_1_DRAM_MODE_1_DDR3_WR_LEVEL_MASK 0x00000080
-#define BCHP_MEMC_DDR_1_DRAM_MODE_1_DDR3_WR_LEVEL_SHIFT 7
-#define BCHP_MEMC_DDR_1_DRAM_MODE_1_DDR3_WR_LEVEL_DEFAULT 0x00000000
-#define BCHP_MEMC_DDR_1_DRAM_MODE_1_DDR3_WR_LEVEL_ENABLE 1
-#define BCHP_MEMC_DDR_1_DRAM_MODE_1_DDR3_WR_LEVEL_DISABLE 0
-
-/* MEMC_DDR_1 :: DRAM_MODE_1 :: DDR3 :: ODT_CNTRL_1 [06:06] */
-#define BCHP_MEMC_DDR_1_DRAM_MODE_1_DDR3_ODT_CNTRL_1_MASK 0x00000040
-#define BCHP_MEMC_DDR_1_DRAM_MODE_1_DDR3_ODT_CNTRL_1_SHIFT 6
-#define BCHP_MEMC_DDR_1_DRAM_MODE_1_DDR3_ODT_CNTRL_1_DEFAULT 0x00000000
-
-/* MEMC_DDR_1 :: DRAM_MODE_1 :: DDR3 :: DRIVER_IMP_CNTRL_1 [05:05] */
-#define BCHP_MEMC_DDR_1_DRAM_MODE_1_DDR3_DRIVER_IMP_CNTRL_1_MASK 0x00000020
-#define BCHP_MEMC_DDR_1_DRAM_MODE_1_DDR3_DRIVER_IMP_CNTRL_1_SHIFT 5
-#define BCHP_MEMC_DDR_1_DRAM_MODE_1_DDR3_DRIVER_IMP_CNTRL_1_DEFAULT 0x00000000
-
-/* MEMC_DDR_1 :: DRAM_MODE_1 :: DDR3 :: AL [04:03] */
-#define BCHP_MEMC_DDR_1_DRAM_MODE_1_DDR3_AL_MASK 0x00000018
-#define BCHP_MEMC_DDR_1_DRAM_MODE_1_DDR3_AL_SHIFT 3
-#define BCHP_MEMC_DDR_1_DRAM_MODE_1_DDR3_AL_DEFAULT 0x00000001
-
-/* MEMC_DDR_1 :: DRAM_MODE_1 :: DDR3 :: ODT_CNTRL_0 [02:02] */
-#define BCHP_MEMC_DDR_1_DRAM_MODE_1_DDR3_ODT_CNTRL_0_MASK 0x00000004
-#define BCHP_MEMC_DDR_1_DRAM_MODE_1_DDR3_ODT_CNTRL_0_SHIFT 2
-#define BCHP_MEMC_DDR_1_DRAM_MODE_1_DDR3_ODT_CNTRL_0_DEFAULT 0x00000001
-
-/* MEMC_DDR_1 :: DRAM_MODE_1 :: DDR3 :: DRIVER_IMP_CNTRL_0 [01:01] */
-#define BCHP_MEMC_DDR_1_DRAM_MODE_1_DDR3_DRIVER_IMP_CNTRL_0_MASK 0x00000002
-#define BCHP_MEMC_DDR_1_DRAM_MODE_1_DDR3_DRIVER_IMP_CNTRL_0_SHIFT 1
-#define BCHP_MEMC_DDR_1_DRAM_MODE_1_DDR3_DRIVER_IMP_CNTRL_0_DEFAULT 0x00000000
-
-/* MEMC_DDR_1 :: DRAM_MODE_1 :: DDR3 :: DLL_EN [00:00] */
-#define BCHP_MEMC_DDR_1_DRAM_MODE_1_DDR3_DLL_EN_MASK 0x00000001
-#define BCHP_MEMC_DDR_1_DRAM_MODE_1_DDR3_DLL_EN_SHIFT 0
-#define BCHP_MEMC_DDR_1_DRAM_MODE_1_DDR3_DLL_EN_DEFAULT 0x00000000
-#define BCHP_MEMC_DDR_1_DRAM_MODE_1_DDR3_DLL_EN_ENABLE 0
-#define BCHP_MEMC_DDR_1_DRAM_MODE_1_DDR3_DLL_EN_DISABLE 1
-
-/* union - case DDR4 [12:00] */
-/* MEMC_DDR_1 :: DRAM_MODE_1 :: DDR4 :: Q_OFF [12:12] */
-#define BCHP_MEMC_DDR_1_DRAM_MODE_1_DDR4_Q_OFF_MASK 0x00001000
-#define BCHP_MEMC_DDR_1_DRAM_MODE_1_DDR4_Q_OFF_SHIFT 12
-#define BCHP_MEMC_DDR_1_DRAM_MODE_1_DDR4_Q_OFF_DEFAULT 0x00000000
-#define BCHP_MEMC_DDR_1_DRAM_MODE_1_DDR4_Q_OFF_ENABLE 0
-#define BCHP_MEMC_DDR_1_DRAM_MODE_1_DDR4_Q_OFF_DISABLE 1
-
-/* MEMC_DDR_1 :: DRAM_MODE_1 :: DDR4 :: TDQS [11:11] */
-#define BCHP_MEMC_DDR_1_DRAM_MODE_1_DDR4_TDQS_MASK 0x00000800
-#define BCHP_MEMC_DDR_1_DRAM_MODE_1_DDR4_TDQS_SHIFT 11
-#define BCHP_MEMC_DDR_1_DRAM_MODE_1_DDR4_TDQS_DEFAULT 0x00000000
-#define BCHP_MEMC_DDR_1_DRAM_MODE_1_DDR4_TDQS_ENABLE 1
-#define BCHP_MEMC_DDR_1_DRAM_MODE_1_DDR4_TDQS_DISABLE 0
-
-/* MEMC_DDR_1 :: DRAM_MODE_1 :: DDR4 :: unused_1 [10:10] */
-#define BCHP_MEMC_DDR_1_DRAM_MODE_1_DDR4_unused_1_MASK 0x00000400
-#define BCHP_MEMC_DDR_1_DRAM_MODE_1_DDR4_unused_1_SHIFT 10
-#define BCHP_MEMC_DDR_1_DRAM_MODE_1_DDR4_unused_1_DEFAULT 0x00000000
-
-/* MEMC_DDR_1 :: DRAM_MODE_1 :: DDR4 :: ODT_CNTRL_2 [09:09] */
-#define BCHP_MEMC_DDR_1_DRAM_MODE_1_DDR4_ODT_CNTRL_2_MASK 0x00000200
-#define BCHP_MEMC_DDR_1_DRAM_MODE_1_DDR4_ODT_CNTRL_2_SHIFT 9
-#define BCHP_MEMC_DDR_1_DRAM_MODE_1_DDR4_ODT_CNTRL_2_DEFAULT 0x00000000
-
-/* MEMC_DDR_1 :: DRAM_MODE_1 :: DDR4 :: unused_2 [08:08] */
-#define BCHP_MEMC_DDR_1_DRAM_MODE_1_DDR4_unused_2_MASK 0x00000100
-#define BCHP_MEMC_DDR_1_DRAM_MODE_1_DDR4_unused_2_SHIFT 8
-#define BCHP_MEMC_DDR_1_DRAM_MODE_1_DDR4_unused_2_DEFAULT 0x00000000
-
-/* MEMC_DDR_1 :: DRAM_MODE_1 :: DDR4 :: WR_LEVEL [07:07] */
-#define BCHP_MEMC_DDR_1_DRAM_MODE_1_DDR4_WR_LEVEL_MASK 0x00000080
-#define BCHP_MEMC_DDR_1_DRAM_MODE_1_DDR4_WR_LEVEL_SHIFT 7
-#define BCHP_MEMC_DDR_1_DRAM_MODE_1_DDR4_WR_LEVEL_DEFAULT 0x00000000
-#define BCHP_MEMC_DDR_1_DRAM_MODE_1_DDR4_WR_LEVEL_ENABLE 1
-#define BCHP_MEMC_DDR_1_DRAM_MODE_1_DDR4_WR_LEVEL_DISABLE 0
-
-/* MEMC_DDR_1 :: DRAM_MODE_1 :: DDR4 :: ODT_CNTRL_1 [06:06] */
-#define BCHP_MEMC_DDR_1_DRAM_MODE_1_DDR4_ODT_CNTRL_1_MASK 0x00000040
-#define BCHP_MEMC_DDR_1_DRAM_MODE_1_DDR4_ODT_CNTRL_1_SHIFT 6
-#define BCHP_MEMC_DDR_1_DRAM_MODE_1_DDR4_ODT_CNTRL_1_DEFAULT 0x00000000
-
-/* MEMC_DDR_1 :: DRAM_MODE_1 :: DDR4 :: DRIVER_IMP_CNTRL_1 [05:05] */
-#define BCHP_MEMC_DDR_1_DRAM_MODE_1_DDR4_DRIVER_IMP_CNTRL_1_MASK 0x00000020
-#define BCHP_MEMC_DDR_1_DRAM_MODE_1_DDR4_DRIVER_IMP_CNTRL_1_SHIFT 5
-#define BCHP_MEMC_DDR_1_DRAM_MODE_1_DDR4_DRIVER_IMP_CNTRL_1_DEFAULT 0x00000000
-
-/* MEMC_DDR_1 :: DRAM_MODE_1 :: DDR4 :: AL [04:03] */
-#define BCHP_MEMC_DDR_1_DRAM_MODE_1_DDR4_AL_MASK 0x00000018
-#define BCHP_MEMC_DDR_1_DRAM_MODE_1_DDR4_AL_SHIFT 3
-#define BCHP_MEMC_DDR_1_DRAM_MODE_1_DDR4_AL_DEFAULT 0x00000001
-
-/* MEMC_DDR_1 :: DRAM_MODE_1 :: DDR4 :: ODT_CNTRL_0 [02:02] */
-#define BCHP_MEMC_DDR_1_DRAM_MODE_1_DDR4_ODT_CNTRL_0_MASK 0x00000004
-#define BCHP_MEMC_DDR_1_DRAM_MODE_1_DDR4_ODT_CNTRL_0_SHIFT 2
-#define BCHP_MEMC_DDR_1_DRAM_MODE_1_DDR4_ODT_CNTRL_0_DEFAULT 0x00000001
-
-/* MEMC_DDR_1 :: DRAM_MODE_1 :: DDR4 :: DRIVER_IMP_CNTRL_0 [01:01] */
-#define BCHP_MEMC_DDR_1_DRAM_MODE_1_DDR4_DRIVER_IMP_CNTRL_0_MASK 0x00000002
-#define BCHP_MEMC_DDR_1_DRAM_MODE_1_DDR4_DRIVER_IMP_CNTRL_0_SHIFT 1
-#define BCHP_MEMC_DDR_1_DRAM_MODE_1_DDR4_DRIVER_IMP_CNTRL_0_DEFAULT 0x00000000
-
-/* MEMC_DDR_1 :: DRAM_MODE_1 :: DDR4 :: DLL_EN [00:00] */
-#define BCHP_MEMC_DDR_1_DRAM_MODE_1_DDR4_DLL_EN_MASK 0x00000001
-#define BCHP_MEMC_DDR_1_DRAM_MODE_1_DDR4_DLL_EN_SHIFT 0
-#define BCHP_MEMC_DDR_1_DRAM_MODE_1_DDR4_DLL_EN_DEFAULT 0x00000000
-#define BCHP_MEMC_DDR_1_DRAM_MODE_1_DDR4_DLL_EN_ENABLE 0
-#define BCHP_MEMC_DDR_1_DRAM_MODE_1_DDR4_DLL_EN_DISABLE 1
-
-/* union - case GDDR5M [12:00] */
-/* MEMC_DDR_1 :: DRAM_MODE_1 :: GDDR5M :: unused_1 [12:11] */
-#define BCHP_MEMC_DDR_1_DRAM_MODE_1_GDDR5M_unused_1_MASK 0x00001800
-#define BCHP_MEMC_DDR_1_DRAM_MODE_1_GDDR5M_unused_1_SHIFT 11
-#define BCHP_MEMC_DDR_1_DRAM_MODE_1_GDDR5M_unused_1_DEFAULT 0x00000000
-
-/* MEMC_DDR_1 :: DRAM_MODE_1 :: GDDR5M :: ABI [10:10] */
-#define BCHP_MEMC_DDR_1_DRAM_MODE_1_GDDR5M_ABI_MASK 0x00000400
-#define BCHP_MEMC_DDR_1_DRAM_MODE_1_GDDR5M_ABI_SHIFT 10
-#define BCHP_MEMC_DDR_1_DRAM_MODE_1_GDDR5M_ABI_DEFAULT 0x00000000
-#define BCHP_MEMC_DDR_1_DRAM_MODE_1_GDDR5M_ABI_ENABLE 0
-#define BCHP_MEMC_DDR_1_DRAM_MODE_1_GDDR5M_ABI_DISABLE 1
-
-/* MEMC_DDR_1 :: DRAM_MODE_1 :: GDDR5M :: WDBI [09:09] */
-#define BCHP_MEMC_DDR_1_DRAM_MODE_1_GDDR5M_WDBI_MASK 0x00000200
-#define BCHP_MEMC_DDR_1_DRAM_MODE_1_GDDR5M_WDBI_SHIFT 9
-#define BCHP_MEMC_DDR_1_DRAM_MODE_1_GDDR5M_WDBI_DEFAULT 0x00000000
-#define BCHP_MEMC_DDR_1_DRAM_MODE_1_GDDR5M_WDBI_ENABLE 0
-#define BCHP_MEMC_DDR_1_DRAM_MODE_1_GDDR5M_WDBI_DISABLE 1
-
-/* MEMC_DDR_1 :: DRAM_MODE_1 :: GDDR5M :: RDBI [08:08] */
-#define BCHP_MEMC_DDR_1_DRAM_MODE_1_GDDR5M_RDBI_MASK 0x00000100
-#define BCHP_MEMC_DDR_1_DRAM_MODE_1_GDDR5M_RDBI_SHIFT 8
-#define BCHP_MEMC_DDR_1_DRAM_MODE_1_GDDR5M_RDBI_DEFAULT 0x00000000
-#define BCHP_MEMC_DDR_1_DRAM_MODE_1_GDDR5M_RDBI_ENABLE 0
-#define BCHP_MEMC_DDR_1_DRAM_MODE_1_GDDR5M_RDBI_DISABLE 1
-
-/* MEMC_DDR_1 :: DRAM_MODE_1 :: GDDR5M :: unused_2 [07:07] */
-#define BCHP_MEMC_DDR_1_DRAM_MODE_1_GDDR5M_unused_2_MASK 0x00000080
-#define BCHP_MEMC_DDR_1_DRAM_MODE_1_GDDR5M_unused_2_SHIFT 7
-#define BCHP_MEMC_DDR_1_DRAM_MODE_1_GDDR5M_unused_2_DEFAULT 0x00000000
-
-/* MEMC_DDR_1 :: DRAM_MODE_1 :: GDDR5M :: CAL_UPD [06:06] */
-#define BCHP_MEMC_DDR_1_DRAM_MODE_1_GDDR5M_CAL_UPD_MASK 0x00000040
-#define BCHP_MEMC_DDR_1_DRAM_MODE_1_GDDR5M_CAL_UPD_SHIFT 6
-#define BCHP_MEMC_DDR_1_DRAM_MODE_1_GDDR5M_CAL_UPD_DEFAULT 0x00000000
-#define BCHP_MEMC_DDR_1_DRAM_MODE_1_GDDR5M_CAL_UPD_ENABLE 0
-#define BCHP_MEMC_DDR_1_DRAM_MODE_1_GDDR5M_CAL_UPD_DISABLE 1
-
-/* MEMC_DDR_1 :: DRAM_MODE_1 :: GDDR5M :: ADDR_CMD_TERM [05:04] */
-#define BCHP_MEMC_DDR_1_DRAM_MODE_1_GDDR5M_ADDR_CMD_TERM_MASK 0x00000030
-#define BCHP_MEMC_DDR_1_DRAM_MODE_1_GDDR5M_ADDR_CMD_TERM_SHIFT 4
-#define BCHP_MEMC_DDR_1_DRAM_MODE_1_GDDR5M_ADDR_CMD_TERM_DEFAULT 0x00000000
-
-/* MEMC_DDR_1 :: DRAM_MODE_1 :: GDDR5M :: DATA_TERM [03:02] */
-#define BCHP_MEMC_DDR_1_DRAM_MODE_1_GDDR5M_DATA_TERM_MASK 0x0000000c
-#define BCHP_MEMC_DDR_1_DRAM_MODE_1_GDDR5M_DATA_TERM_SHIFT 2
-#define BCHP_MEMC_DDR_1_DRAM_MODE_1_GDDR5M_DATA_TERM_DEFAULT 0x00000000
-
-/* MEMC_DDR_1 :: DRAM_MODE_1 :: GDDR5M :: DRIVER_STRENGTH [01:00] */
-#define BCHP_MEMC_DDR_1_DRAM_MODE_1_GDDR5M_DRIVER_STRENGTH_MASK 0x00000003
-#define BCHP_MEMC_DDR_1_DRAM_MODE_1_GDDR5M_DRIVER_STRENGTH_SHIFT 0
-#define BCHP_MEMC_DDR_1_DRAM_MODE_1_GDDR5M_DRIVER_STRENGTH_DEFAULT 0x00000000
-
-/* union - case GDDR5 [12:00] */
-/* MEMC_DDR_1 :: DRAM_MODE_1 :: GDDR5 :: unused_1 [12:12] */
-#define BCHP_MEMC_DDR_1_DRAM_MODE_1_GDDR5_unused_1_MASK 0x00001000
-#define BCHP_MEMC_DDR_1_DRAM_MODE_1_GDDR5_unused_1_SHIFT 12
-#define BCHP_MEMC_DDR_1_DRAM_MODE_1_GDDR5_unused_1_DEFAULT 0x00000000
-
-/* MEMC_DDR_1 :: DRAM_MODE_1 :: GDDR5 :: PLL_DLL_RST [11:11] */
-#define BCHP_MEMC_DDR_1_DRAM_MODE_1_GDDR5_PLL_DLL_RST_MASK 0x00000800
-#define BCHP_MEMC_DDR_1_DRAM_MODE_1_GDDR5_PLL_DLL_RST_SHIFT 11
-#define BCHP_MEMC_DDR_1_DRAM_MODE_1_GDDR5_PLL_DLL_RST_DEFAULT 0x00000000
-
-/* MEMC_DDR_1 :: DRAM_MODE_1 :: GDDR5 :: ABI [10:10] */
-#define BCHP_MEMC_DDR_1_DRAM_MODE_1_GDDR5_ABI_MASK 0x00000400
-#define BCHP_MEMC_DDR_1_DRAM_MODE_1_GDDR5_ABI_SHIFT 10
-#define BCHP_MEMC_DDR_1_DRAM_MODE_1_GDDR5_ABI_DEFAULT 0x00000000
-#define BCHP_MEMC_DDR_1_DRAM_MODE_1_GDDR5_ABI_ENABLE 0
-#define BCHP_MEMC_DDR_1_DRAM_MODE_1_GDDR5_ABI_DISABLE 1
-
-/* MEMC_DDR_1 :: DRAM_MODE_1 :: GDDR5 :: WDBI [09:09] */
-#define BCHP_MEMC_DDR_1_DRAM_MODE_1_GDDR5_WDBI_MASK 0x00000200
-#define BCHP_MEMC_DDR_1_DRAM_MODE_1_GDDR5_WDBI_SHIFT 9
-#define BCHP_MEMC_DDR_1_DRAM_MODE_1_GDDR5_WDBI_DEFAULT 0x00000000
-#define BCHP_MEMC_DDR_1_DRAM_MODE_1_GDDR5_WDBI_ENABLE 0
-#define BCHP_MEMC_DDR_1_DRAM_MODE_1_GDDR5_WDBI_DISABLE 1
-
-/* MEMC_DDR_1 :: DRAM_MODE_1 :: GDDR5 :: RDBI [08:08] */
-#define BCHP_MEMC_DDR_1_DRAM_MODE_1_GDDR5_RDBI_MASK 0x00000100
-#define BCHP_MEMC_DDR_1_DRAM_MODE_1_GDDR5_RDBI_SHIFT 8
-#define BCHP_MEMC_DDR_1_DRAM_MODE_1_GDDR5_RDBI_DEFAULT 0x00000000
-#define BCHP_MEMC_DDR_1_DRAM_MODE_1_GDDR5_RDBI_ENABLE 0
-#define BCHP_MEMC_DDR_1_DRAM_MODE_1_GDDR5_RDBI_DISABLE 1
-
-/* MEMC_DDR_1 :: DRAM_MODE_1 :: GDDR5 :: PLL_DLL [07:07] */
-#define BCHP_MEMC_DDR_1_DRAM_MODE_1_GDDR5_PLL_DLL_MASK 0x00000080
-#define BCHP_MEMC_DDR_1_DRAM_MODE_1_GDDR5_PLL_DLL_SHIFT 7
-#define BCHP_MEMC_DDR_1_DRAM_MODE_1_GDDR5_PLL_DLL_DEFAULT 0x00000000
-
-/* MEMC_DDR_1 :: DRAM_MODE_1 :: GDDR5 :: CAL_UPD [06:06] */
-#define BCHP_MEMC_DDR_1_DRAM_MODE_1_GDDR5_CAL_UPD_MASK 0x00000040
-#define BCHP_MEMC_DDR_1_DRAM_MODE_1_GDDR5_CAL_UPD_SHIFT 6
-#define BCHP_MEMC_DDR_1_DRAM_MODE_1_GDDR5_CAL_UPD_DEFAULT 0x00000000
-#define BCHP_MEMC_DDR_1_DRAM_MODE_1_GDDR5_CAL_UPD_ENABLE 0
-#define BCHP_MEMC_DDR_1_DRAM_MODE_1_GDDR5_CAL_UPD_DISABLE 1
-
-/* MEMC_DDR_1 :: DRAM_MODE_1 :: GDDR5 :: ADDR_CMD_TERM [05:04] */
-#define BCHP_MEMC_DDR_1_DRAM_MODE_1_GDDR5_ADDR_CMD_TERM_MASK 0x00000030
-#define BCHP_MEMC_DDR_1_DRAM_MODE_1_GDDR5_ADDR_CMD_TERM_SHIFT 4
-#define BCHP_MEMC_DDR_1_DRAM_MODE_1_GDDR5_ADDR_CMD_TERM_DEFAULT 0x00000000
-
-/* MEMC_DDR_1 :: DRAM_MODE_1 :: GDDR5 :: DATA_TERM [03:02] */
-#define BCHP_MEMC_DDR_1_DRAM_MODE_1_GDDR5_DATA_TERM_MASK 0x0000000c
-#define BCHP_MEMC_DDR_1_DRAM_MODE_1_GDDR5_DATA_TERM_SHIFT 2
-#define BCHP_MEMC_DDR_1_DRAM_MODE_1_GDDR5_DATA_TERM_DEFAULT 0x00000000
-
-/* MEMC_DDR_1 :: DRAM_MODE_1 :: GDDR5 :: DRIVER_STRENGTH [01:00] */
-#define BCHP_MEMC_DDR_1_DRAM_MODE_1_GDDR5_DRIVER_STRENGTH_MASK 0x00000003
-#define BCHP_MEMC_DDR_1_DRAM_MODE_1_GDDR5_DRIVER_STRENGTH_SHIFT 0
-#define BCHP_MEMC_DDR_1_DRAM_MODE_1_GDDR5_DRIVER_STRENGTH_DEFAULT 0x00000000
-
-/***************************************************************************
- *DRAM_MODE_2 - Dram Mode Register 2
- ***************************************************************************/
-/* MEMC_DDR_1 :: DRAM_MODE_2 :: reserved0 [31:16] */
-#define BCHP_MEMC_DDR_1_DRAM_MODE_2_reserved0_MASK 0xffff0000
-#define BCHP_MEMC_DDR_1_DRAM_MODE_2_reserved0_SHIFT 16
-
-/* MEMC_DDR_1 :: DRAM_MODE_2 :: unused_0 [15:13] */
-#define BCHP_MEMC_DDR_1_DRAM_MODE_2_unused_0_MASK 0x0000e000
-#define BCHP_MEMC_DDR_1_DRAM_MODE_2_unused_0_SHIFT 13
-#define BCHP_MEMC_DDR_1_DRAM_MODE_2_unused_0_DEFAULT 0x00000000
-
-/* union - case DDR3 [12:00] */
-/* MEMC_DDR_1 :: DRAM_MODE_2 :: DDR3 :: unused_1 [12:11] */
-#define BCHP_MEMC_DDR_1_DRAM_MODE_2_DDR3_unused_1_MASK 0x00001800
-#define BCHP_MEMC_DDR_1_DRAM_MODE_2_DDR3_unused_1_SHIFT 11
-#define BCHP_MEMC_DDR_1_DRAM_MODE_2_DDR3_unused_1_DEFAULT 0x00000000
-
-/* MEMC_DDR_1 :: DRAM_MODE_2 :: DDR3 :: WR_ODT [10:09] */
-#define BCHP_MEMC_DDR_1_DRAM_MODE_2_DDR3_WR_ODT_MASK 0x00000600
-#define BCHP_MEMC_DDR_1_DRAM_MODE_2_DDR3_WR_ODT_SHIFT 9
-#define BCHP_MEMC_DDR_1_DRAM_MODE_2_DDR3_WR_ODT_DEFAULT 0x00000001
-
-/* MEMC_DDR_1 :: DRAM_MODE_2 :: DDR3 :: unused_2 [08:08] */
-#define BCHP_MEMC_DDR_1_DRAM_MODE_2_DDR3_unused_2_MASK 0x00000100
-#define BCHP_MEMC_DDR_1_DRAM_MODE_2_DDR3_unused_2_SHIFT 8
-#define BCHP_MEMC_DDR_1_DRAM_MODE_2_DDR3_unused_2_DEFAULT 0x00000000
-
-/* MEMC_DDR_1 :: DRAM_MODE_2 :: DDR3 :: SRF_TR [07:07] */
-#define BCHP_MEMC_DDR_1_DRAM_MODE_2_DDR3_SRF_TR_MASK 0x00000080
-#define BCHP_MEMC_DDR_1_DRAM_MODE_2_DDR3_SRF_TR_SHIFT 7
-#define BCHP_MEMC_DDR_1_DRAM_MODE_2_DDR3_SRF_TR_DEFAULT 0x00000000
-
-/* MEMC_DDR_1 :: DRAM_MODE_2 :: DDR3 :: AUTO_SR [06:06] */
-#define BCHP_MEMC_DDR_1_DRAM_MODE_2_DDR3_AUTO_SR_MASK 0x00000040
-#define BCHP_MEMC_DDR_1_DRAM_MODE_2_DDR3_AUTO_SR_SHIFT 6
-#define BCHP_MEMC_DDR_1_DRAM_MODE_2_DDR3_AUTO_SR_DEFAULT 0x00000001
-
-/* MEMC_DDR_1 :: DRAM_MODE_2 :: DDR3 :: WCL [05:03] */
-#define BCHP_MEMC_DDR_1_DRAM_MODE_2_DDR3_WCL_MASK 0x00000038
-#define BCHP_MEMC_DDR_1_DRAM_MODE_2_DDR3_WCL_SHIFT 3
-#define BCHP_MEMC_DDR_1_DRAM_MODE_2_DDR3_WCL_DEFAULT 0x00000001
-
-/* MEMC_DDR_1 :: DRAM_MODE_2 :: DDR3 :: PASR [02:00] */
-#define BCHP_MEMC_DDR_1_DRAM_MODE_2_DDR3_PASR_MASK 0x00000007
-#define BCHP_MEMC_DDR_1_DRAM_MODE_2_DDR3_PASR_SHIFT 0
-#define BCHP_MEMC_DDR_1_DRAM_MODE_2_DDR3_PASR_DEFAULT 0x00000000
-
-/* union - case DDR4 [12:00] */
-/* MEMC_DDR_1 :: DRAM_MODE_2 :: DDR4 :: WR_DATA_CRC [12:12] */
-#define BCHP_MEMC_DDR_1_DRAM_MODE_2_DDR4_WR_DATA_CRC_MASK 0x00001000
-#define BCHP_MEMC_DDR_1_DRAM_MODE_2_DDR4_WR_DATA_CRC_SHIFT 12
-#define BCHP_MEMC_DDR_1_DRAM_MODE_2_DDR4_WR_DATA_CRC_DEFAULT 0x00000000
-#define BCHP_MEMC_DDR_1_DRAM_MODE_2_DDR4_WR_DATA_CRC_ENABLE 1
-#define BCHP_MEMC_DDR_1_DRAM_MODE_2_DDR4_WR_DATA_CRC_DISABLE 0
-
-/* MEMC_DDR_1 :: DRAM_MODE_2 :: DDR4 :: RD_DATA_CRC [11:11] */
-#define BCHP_MEMC_DDR_1_DRAM_MODE_2_DDR4_RD_DATA_CRC_MASK 0x00000800
-#define BCHP_MEMC_DDR_1_DRAM_MODE_2_DDR4_RD_DATA_CRC_SHIFT 11
-#define BCHP_MEMC_DDR_1_DRAM_MODE_2_DDR4_RD_DATA_CRC_DEFAULT 0x00000000
-#define BCHP_MEMC_DDR_1_DRAM_MODE_2_DDR4_RD_DATA_CRC_ENABLE 1
-#define BCHP_MEMC_DDR_1_DRAM_MODE_2_DDR4_RD_DATA_CRC_DISABLE 0
-
-/* MEMC_DDR_1 :: DRAM_MODE_2 :: DDR4 :: RTT_WR [10:09] */
-#define BCHP_MEMC_DDR_1_DRAM_MODE_2_DDR4_RTT_WR_MASK 0x00000600
-#define BCHP_MEMC_DDR_1_DRAM_MODE_2_DDR4_RTT_WR_SHIFT 9
-#define BCHP_MEMC_DDR_1_DRAM_MODE_2_DDR4_RTT_WR_DEFAULT 0x00000001
-
-/* MEMC_DDR_1 :: DRAM_MODE_2 :: DDR4 :: unused_1 [08:08] */
-#define BCHP_MEMC_DDR_1_DRAM_MODE_2_DDR4_unused_1_MASK 0x00000100
-#define BCHP_MEMC_DDR_1_DRAM_MODE_2_DDR4_unused_1_SHIFT 8
-#define BCHP_MEMC_DDR_1_DRAM_MODE_2_DDR4_unused_1_DEFAULT 0x00000000
-
-/* MEMC_DDR_1 :: DRAM_MODE_2 :: DDR4 :: LPASR [07:06] */
-#define BCHP_MEMC_DDR_1_DRAM_MODE_2_DDR4_LPASR_MASK 0x000000c0
-#define BCHP_MEMC_DDR_1_DRAM_MODE_2_DDR4_LPASR_SHIFT 6
-#define BCHP_MEMC_DDR_1_DRAM_MODE_2_DDR4_LPASR_DEFAULT 0x00000000
-
-/* MEMC_DDR_1 :: DRAM_MODE_2 :: DDR4 :: CWL [05:03] */
-#define BCHP_MEMC_DDR_1_DRAM_MODE_2_DDR4_CWL_MASK 0x00000038
-#define BCHP_MEMC_DDR_1_DRAM_MODE_2_DDR4_CWL_SHIFT 3
-#define BCHP_MEMC_DDR_1_DRAM_MODE_2_DDR4_CWL_DEFAULT 0x00000001
-
-/* MEMC_DDR_1 :: DRAM_MODE_2 :: DDR4 :: PASR [02:00] */
-#define BCHP_MEMC_DDR_1_DRAM_MODE_2_DDR4_PASR_MASK 0x00000007
-#define BCHP_MEMC_DDR_1_DRAM_MODE_2_DDR4_PASR_SHIFT 0
-#define BCHP_MEMC_DDR_1_DRAM_MODE_2_DDR4_PASR_DEFAULT 0x00000000
-
-/* union - case GDDR5M [12:00] */
-/* MEMC_DDR_1 :: DRAM_MODE_2 :: GDDR5M :: unused_1 [12:12] */
-#define BCHP_MEMC_DDR_1_DRAM_MODE_2_GDDR5M_unused_1_MASK 0x00001000
-#define BCHP_MEMC_DDR_1_DRAM_MODE_2_GDDR5M_unused_1_SHIFT 12
-#define BCHP_MEMC_DDR_1_DRAM_MODE_2_GDDR5M_unused_1_DEFAULT 0x00000000
-
-/* MEMC_DDR_1 :: DRAM_MODE_2 :: GDDR5M :: ADDR_CMD_TERM_OFFSET [11:09] */
-#define BCHP_MEMC_DDR_1_DRAM_MODE_2_GDDR5M_ADDR_CMD_TERM_OFFSET_MASK 0x00000e00
-#define BCHP_MEMC_DDR_1_DRAM_MODE_2_GDDR5M_ADDR_CMD_TERM_OFFSET_SHIFT 9
-#define BCHP_MEMC_DDR_1_DRAM_MODE_2_GDDR5M_ADDR_CMD_TERM_OFFSET_DEFAULT 0x00000000
-
-/* MEMC_DDR_1 :: DRAM_MODE_2 :: GDDR5M :: DATA_WCK_TERM_OFFSET [08:06] */
-#define BCHP_MEMC_DDR_1_DRAM_MODE_2_GDDR5M_DATA_WCK_TERM_OFFSET_MASK 0x000001c0
-#define BCHP_MEMC_DDR_1_DRAM_MODE_2_GDDR5M_DATA_WCK_TERM_OFFSET_SHIFT 6
-#define BCHP_MEMC_DDR_1_DRAM_MODE_2_GDDR5M_DATA_WCK_TERM_OFFSET_DEFAULT 0x00000000
-
-/* MEMC_DDR_1 :: DRAM_MODE_2 :: GDDR5M :: OCD_PUP_DRIVER_OFFSET [05:03] */
-#define BCHP_MEMC_DDR_1_DRAM_MODE_2_GDDR5M_OCD_PUP_DRIVER_OFFSET_MASK 0x00000038
-#define BCHP_MEMC_DDR_1_DRAM_MODE_2_GDDR5M_OCD_PUP_DRIVER_OFFSET_SHIFT 3
-#define BCHP_MEMC_DDR_1_DRAM_MODE_2_GDDR5M_OCD_PUP_DRIVER_OFFSET_DEFAULT 0x00000000
-
-/* MEMC_DDR_1 :: DRAM_MODE_2 :: GDDR5M :: OCD_PDN_DRIVER_OFFSET [02:00] */
-#define BCHP_MEMC_DDR_1_DRAM_MODE_2_GDDR5M_OCD_PDN_DRIVER_OFFSET_MASK 0x00000007
-#define BCHP_MEMC_DDR_1_DRAM_MODE_2_GDDR5M_OCD_PDN_DRIVER_OFFSET_SHIFT 0
-#define BCHP_MEMC_DDR_1_DRAM_MODE_2_GDDR5M_OCD_PDN_DRIVER_OFFSET_DEFAULT 0x00000000
-
-/* union - case GDDR5 [12:00] */
-/* MEMC_DDR_1 :: DRAM_MODE_2 :: GDDR5 :: unused_1 [12:12] */
-#define BCHP_MEMC_DDR_1_DRAM_MODE_2_GDDR5_unused_1_MASK 0x00001000
-#define BCHP_MEMC_DDR_1_DRAM_MODE_2_GDDR5_unused_1_SHIFT 12
-#define BCHP_MEMC_DDR_1_DRAM_MODE_2_GDDR5_unused_1_DEFAULT 0x00000000
-
-/* MEMC_DDR_1 :: DRAM_MODE_2 :: GDDR5 :: ADDR_CMD_TERM_OFFSET [11:09] */
-#define BCHP_MEMC_DDR_1_DRAM_MODE_2_GDDR5_ADDR_CMD_TERM_OFFSET_MASK 0x00000e00
-#define BCHP_MEMC_DDR_1_DRAM_MODE_2_GDDR5_ADDR_CMD_TERM_OFFSET_SHIFT 9
-#define BCHP_MEMC_DDR_1_DRAM_MODE_2_GDDR5_ADDR_CMD_TERM_OFFSET_DEFAULT 0x00000000
-
-/* MEMC_DDR_1 :: DRAM_MODE_2 :: GDDR5 :: DATA_WCK_TERM_OFFSET [08:06] */
-#define BCHP_MEMC_DDR_1_DRAM_MODE_2_GDDR5_DATA_WCK_TERM_OFFSET_MASK 0x000001c0
-#define BCHP_MEMC_DDR_1_DRAM_MODE_2_GDDR5_DATA_WCK_TERM_OFFSET_SHIFT 6
-#define BCHP_MEMC_DDR_1_DRAM_MODE_2_GDDR5_DATA_WCK_TERM_OFFSET_DEFAULT 0x00000000
-
-/* MEMC_DDR_1 :: DRAM_MODE_2 :: GDDR5 :: OCD_PUP_DRIVER_OFFSET [05:03] */
-#define BCHP_MEMC_DDR_1_DRAM_MODE_2_GDDR5_OCD_PUP_DRIVER_OFFSET_MASK 0x00000038
-#define BCHP_MEMC_DDR_1_DRAM_MODE_2_GDDR5_OCD_PUP_DRIVER_OFFSET_SHIFT 3
-#define BCHP_MEMC_DDR_1_DRAM_MODE_2_GDDR5_OCD_PUP_DRIVER_OFFSET_DEFAULT 0x00000000
-
-/* MEMC_DDR_1 :: DRAM_MODE_2 :: GDDR5 :: OCD_PDN_DRIVER_OFFSET [02:00] */
-#define BCHP_MEMC_DDR_1_DRAM_MODE_2_GDDR5_OCD_PDN_DRIVER_OFFSET_MASK 0x00000007
-#define BCHP_MEMC_DDR_1_DRAM_MODE_2_GDDR5_OCD_PDN_DRIVER_OFFSET_SHIFT 0
-#define BCHP_MEMC_DDR_1_DRAM_MODE_2_GDDR5_OCD_PDN_DRIVER_OFFSET_DEFAULT 0x00000000
-
-/***************************************************************************
- *DRAM_MODE_3 - Dram Mode Register 3
- ***************************************************************************/
-/* MEMC_DDR_1 :: DRAM_MODE_3 :: reserved0 [31:16] */
-#define BCHP_MEMC_DDR_1_DRAM_MODE_3_reserved0_MASK 0xffff0000
-#define BCHP_MEMC_DDR_1_DRAM_MODE_3_reserved0_SHIFT 16
-
-/* MEMC_DDR_1 :: DRAM_MODE_3 :: unused_0 [15:13] */
-#define BCHP_MEMC_DDR_1_DRAM_MODE_3_unused_0_MASK 0x0000e000
-#define BCHP_MEMC_DDR_1_DRAM_MODE_3_unused_0_SHIFT 13
-#define BCHP_MEMC_DDR_1_DRAM_MODE_3_unused_0_DEFAULT 0x00000000
-
-/* union - case DDR3 [12:00] */
-/* MEMC_DDR_1 :: DRAM_MODE_3 :: DDR3 :: unused_1 [12:03] */
-#define BCHP_MEMC_DDR_1_DRAM_MODE_3_DDR3_unused_1_MASK 0x00001ff8
-#define BCHP_MEMC_DDR_1_DRAM_MODE_3_DDR3_unused_1_SHIFT 3
-#define BCHP_MEMC_DDR_1_DRAM_MODE_3_DDR3_unused_1_DEFAULT 0x00000000
-
-/* MEMC_DDR_1 :: DRAM_MODE_3 :: DDR3 :: MPR [02:02] */
-#define BCHP_MEMC_DDR_1_DRAM_MODE_3_DDR3_MPR_MASK 0x00000004
-#define BCHP_MEMC_DDR_1_DRAM_MODE_3_DDR3_MPR_SHIFT 2
-#define BCHP_MEMC_DDR_1_DRAM_MODE_3_DDR3_MPR_DEFAULT 0x00000000
-
-/* MEMC_DDR_1 :: DRAM_MODE_3 :: DDR3 :: MPR_LOC [01:00] */
-#define BCHP_MEMC_DDR_1_DRAM_MODE_3_DDR3_MPR_LOC_MASK 0x00000003
-#define BCHP_MEMC_DDR_1_DRAM_MODE_3_DDR3_MPR_LOC_SHIFT 0
-#define BCHP_MEMC_DDR_1_DRAM_MODE_3_DDR3_MPR_LOC_DEFAULT 0x00000000
-
-/* union - case DDR4 [12:00] */
-/* MEMC_DDR_1 :: DRAM_MODE_3 :: DDR4 :: MPR_READ_FORMAT [12:11] */
-#define BCHP_MEMC_DDR_1_DRAM_MODE_3_DDR4_MPR_READ_FORMAT_MASK 0x00001800
-#define BCHP_MEMC_DDR_1_DRAM_MODE_3_DDR4_MPR_READ_FORMAT_SHIFT 11
-#define BCHP_MEMC_DDR_1_DRAM_MODE_3_DDR4_MPR_READ_FORMAT_DEFAULT 0x00000000
-
-/* MEMC_DDR_1 :: DRAM_MODE_3 :: DDR4 :: unused_1 [10:09] */
-#define BCHP_MEMC_DDR_1_DRAM_MODE_3_DDR4_unused_1_MASK 0x00000600
-#define BCHP_MEMC_DDR_1_DRAM_MODE_3_DDR4_unused_1_SHIFT 9
-#define BCHP_MEMC_DDR_1_DRAM_MODE_3_DDR4_unused_1_DEFAULT 0x00000000
-
-/* MEMC_DDR_1 :: DRAM_MODE_3 :: DDR4 :: FGR [08:06] */
-#define BCHP_MEMC_DDR_1_DRAM_MODE_3_DDR4_FGR_MASK 0x000001c0
-#define BCHP_MEMC_DDR_1_DRAM_MODE_3_DDR4_FGR_SHIFT 6
-#define BCHP_MEMC_DDR_1_DRAM_MODE_3_DDR4_FGR_DEFAULT 0x00000000
-
-/* MEMC_DDR_1 :: DRAM_MODE_3 :: DDR4 :: MRS_READOUT [05:05] */
-#define BCHP_MEMC_DDR_1_DRAM_MODE_3_DDR4_MRS_READOUT_MASK 0x00000020
-#define BCHP_MEMC_DDR_1_DRAM_MODE_3_DDR4_MRS_READOUT_SHIFT 5
-#define BCHP_MEMC_DDR_1_DRAM_MODE_3_DDR4_MRS_READOUT_DEFAULT 0x00000000
-#define BCHP_MEMC_DDR_1_DRAM_MODE_3_DDR4_MRS_READOUT_ENABLE 1
-#define BCHP_MEMC_DDR_1_DRAM_MODE_3_DDR4_MRS_READOUT_DISABLE 0
-
-/* MEMC_DDR_1 :: DRAM_MODE_3 :: DDR4 :: PER_DRAM_ADDR [04:04] */
-#define BCHP_MEMC_DDR_1_DRAM_MODE_3_DDR4_PER_DRAM_ADDR_MASK 0x00000010
-#define BCHP_MEMC_DDR_1_DRAM_MODE_3_DDR4_PER_DRAM_ADDR_SHIFT 4
-#define BCHP_MEMC_DDR_1_DRAM_MODE_3_DDR4_PER_DRAM_ADDR_DEFAULT 0x00000000
-#define BCHP_MEMC_DDR_1_DRAM_MODE_3_DDR4_PER_DRAM_ADDR_ENABLE 1
-#define BCHP_MEMC_DDR_1_DRAM_MODE_3_DDR4_PER_DRAM_ADDR_DISABLE 0
-
-/* MEMC_DDR_1 :: DRAM_MODE_3 :: DDR4 :: GEARDOWN [03:03] */
-#define BCHP_MEMC_DDR_1_DRAM_MODE_3_DDR4_GEARDOWN_MASK 0x00000008
-#define BCHP_MEMC_DDR_1_DRAM_MODE_3_DDR4_GEARDOWN_SHIFT 3
-#define BCHP_MEMC_DDR_1_DRAM_MODE_3_DDR4_GEARDOWN_DEFAULT 0x00000000
-
-/* MEMC_DDR_1 :: DRAM_MODE_3 :: DDR4 :: MPR [02:02] */
-#define BCHP_MEMC_DDR_1_DRAM_MODE_3_DDR4_MPR_MASK 0x00000004
-#define BCHP_MEMC_DDR_1_DRAM_MODE_3_DDR4_MPR_SHIFT 2
-#define BCHP_MEMC_DDR_1_DRAM_MODE_3_DDR4_MPR_DEFAULT 0x00000000
-
-/* MEMC_DDR_1 :: DRAM_MODE_3 :: DDR4 :: MPR_PAGE [01:00] */
-#define BCHP_MEMC_DDR_1_DRAM_MODE_3_DDR4_MPR_PAGE_MASK 0x00000003
-#define BCHP_MEMC_DDR_1_DRAM_MODE_3_DDR4_MPR_PAGE_SHIFT 0
-#define BCHP_MEMC_DDR_1_DRAM_MODE_3_DDR4_MPR_PAGE_DEFAULT 0x00000000
-
-/* union - case GDDR5M [12:00] */
-/* MEMC_DDR_1 :: DRAM_MODE_3 :: GDDR5M :: unused_1 [12:12] */
-#define BCHP_MEMC_DDR_1_DRAM_MODE_3_GDDR5M_unused_1_MASK 0x00001000
-#define BCHP_MEMC_DDR_1_DRAM_MODE_3_GDDR5M_unused_1_SHIFT 12
-#define BCHP_MEMC_DDR_1_DRAM_MODE_3_GDDR5M_unused_1_DEFAULT 0x00000000
-
-/* MEMC_DDR_1 :: DRAM_MODE_3 :: GDDR5M :: BANK_GROUPS [11:10] */
-#define BCHP_MEMC_DDR_1_DRAM_MODE_3_GDDR5M_BANK_GROUPS_MASK 0x00000c00
-#define BCHP_MEMC_DDR_1_DRAM_MODE_3_GDDR5M_BANK_GROUPS_SHIFT 10
-#define BCHP_MEMC_DDR_1_DRAM_MODE_3_GDDR5M_BANK_GROUPS_DEFAULT 0x00000000
-
-/* MEMC_DDR_1 :: DRAM_MODE_3 :: GDDR5M :: WCK_TERM [09:08] */
-#define BCHP_MEMC_DDR_1_DRAM_MODE_3_GDDR5M_WCK_TERM_MASK 0x00000300
-#define BCHP_MEMC_DDR_1_DRAM_MODE_3_GDDR5M_WCK_TERM_SHIFT 8
-#define BCHP_MEMC_DDR_1_DRAM_MODE_3_GDDR5M_WCK_TERM_DEFAULT 0x00000000
-
-/* MEMC_DDR_1 :: DRAM_MODE_3 :: GDDR5M :: DRAM_INFO [07:06] */
-#define BCHP_MEMC_DDR_1_DRAM_MODE_3_GDDR5M_DRAM_INFO_MASK 0x000000c0
-#define BCHP_MEMC_DDR_1_DRAM_MODE_3_GDDR5M_DRAM_INFO_SHIFT 6
-#define BCHP_MEMC_DDR_1_DRAM_MODE_3_GDDR5M_DRAM_INFO_DEFAULT 0x00000000
-
-/* MEMC_DDR_1 :: DRAM_MODE_3 :: GDDR5M :: RDQS_MODE [05:05] */
-#define BCHP_MEMC_DDR_1_DRAM_MODE_3_GDDR5M_RDQS_MODE_MASK 0x00000020
-#define BCHP_MEMC_DDR_1_DRAM_MODE_3_GDDR5M_RDQS_MODE_SHIFT 5
-#define BCHP_MEMC_DDR_1_DRAM_MODE_3_GDDR5M_RDQS_MODE_DEFAULT 0x00000000
-#define BCHP_MEMC_DDR_1_DRAM_MODE_3_GDDR5M_RDQS_MODE_ENABLE 1
-#define BCHP_MEMC_DDR_1_DRAM_MODE_3_GDDR5M_RDQS_MODE_DISABLE 0
-
-/* MEMC_DDR_1 :: DRAM_MODE_3 :: GDDR5M :: WCK2CK_TRAIN [04:04] */
-#define BCHP_MEMC_DDR_1_DRAM_MODE_3_GDDR5M_WCK2CK_TRAIN_MASK 0x00000010
-#define BCHP_MEMC_DDR_1_DRAM_MODE_3_GDDR5M_WCK2CK_TRAIN_SHIFT 4
-#define BCHP_MEMC_DDR_1_DRAM_MODE_3_GDDR5M_WCK2CK_TRAIN_DEFAULT 0x00000000
-#define BCHP_MEMC_DDR_1_DRAM_MODE_3_GDDR5M_WCK2CK_TRAIN_ENABLE 1
-#define BCHP_MEMC_DDR_1_DRAM_MODE_3_GDDR5M_WCK2CK_TRAIN_DISABLE 0
-
-/* MEMC_DDR_1 :: DRAM_MODE_3 :: GDDR5M :: WCK23_INVERT [03:03] */
-#define BCHP_MEMC_DDR_1_DRAM_MODE_3_GDDR5M_WCK23_INVERT_MASK 0x00000008
-#define BCHP_MEMC_DDR_1_DRAM_MODE_3_GDDR5M_WCK23_INVERT_SHIFT 3
-#define BCHP_MEMC_DDR_1_DRAM_MODE_3_GDDR5M_WCK23_INVERT_DEFAULT 0x00000000
-#define BCHP_MEMC_DDR_1_DRAM_MODE_3_GDDR5M_WCK23_INVERT_ENABLE 1
-#define BCHP_MEMC_DDR_1_DRAM_MODE_3_GDDR5M_WCK23_INVERT_DISABLE 0
-
-/* MEMC_DDR_1 :: DRAM_MODE_3 :: GDDR5M :: WCK01_INVERT [02:02] */
-#define BCHP_MEMC_DDR_1_DRAM_MODE_3_GDDR5M_WCK01_INVERT_MASK 0x00000004
-#define BCHP_MEMC_DDR_1_DRAM_MODE_3_GDDR5M_WCK01_INVERT_SHIFT 2
-#define BCHP_MEMC_DDR_1_DRAM_MODE_3_GDDR5M_WCK01_INVERT_DEFAULT 0x00000000
-#define BCHP_MEMC_DDR_1_DRAM_MODE_3_GDDR5M_WCK01_INVERT_ENABLE 1
-#define BCHP_MEMC_DDR_1_DRAM_MODE_3_GDDR5M_WCK01_INVERT_DISABLE 0
-
-/* MEMC_DDR_1 :: DRAM_MODE_3 :: GDDR5M :: SELF_REFRESH [01:00] */
-#define BCHP_MEMC_DDR_1_DRAM_MODE_3_GDDR5M_SELF_REFRESH_MASK 0x00000003
-#define BCHP_MEMC_DDR_1_DRAM_MODE_3_GDDR5M_SELF_REFRESH_SHIFT 0
-#define BCHP_MEMC_DDR_1_DRAM_MODE_3_GDDR5M_SELF_REFRESH_DEFAULT 0x00000000
-
-/* union - case GDDR5 [12:00] */
-/* MEMC_DDR_1 :: DRAM_MODE_3 :: GDDR5 :: unused_1 [12:12] */
-#define BCHP_MEMC_DDR_1_DRAM_MODE_3_GDDR5_unused_1_MASK 0x00001000
-#define BCHP_MEMC_DDR_1_DRAM_MODE_3_GDDR5_unused_1_SHIFT 12
-#define BCHP_MEMC_DDR_1_DRAM_MODE_3_GDDR5_unused_1_DEFAULT 0x00000000
-
-/* MEMC_DDR_1 :: DRAM_MODE_3 :: GDDR5 :: BANK_GROUPS [11:10] */
-#define BCHP_MEMC_DDR_1_DRAM_MODE_3_GDDR5_BANK_GROUPS_MASK 0x00000c00
-#define BCHP_MEMC_DDR_1_DRAM_MODE_3_GDDR5_BANK_GROUPS_SHIFT 10
-#define BCHP_MEMC_DDR_1_DRAM_MODE_3_GDDR5_BANK_GROUPS_DEFAULT 0x00000000
-
-/* MEMC_DDR_1 :: DRAM_MODE_3 :: GDDR5 :: WCK_TERM [09:08] */
-#define BCHP_MEMC_DDR_1_DRAM_MODE_3_GDDR5_WCK_TERM_MASK 0x00000300
-#define BCHP_MEMC_DDR_1_DRAM_MODE_3_GDDR5_WCK_TERM_SHIFT 8
-#define BCHP_MEMC_DDR_1_DRAM_MODE_3_GDDR5_WCK_TERM_DEFAULT 0x00000000
-
-/* MEMC_DDR_1 :: DRAM_MODE_3 :: GDDR5 :: DRAM_INFO [07:06] */
-#define BCHP_MEMC_DDR_1_DRAM_MODE_3_GDDR5_DRAM_INFO_MASK 0x000000c0
-#define BCHP_MEMC_DDR_1_DRAM_MODE_3_GDDR5_DRAM_INFO_SHIFT 6
-#define BCHP_MEMC_DDR_1_DRAM_MODE_3_GDDR5_DRAM_INFO_DEFAULT 0x00000000
-
-/* MEMC_DDR_1 :: DRAM_MODE_3 :: GDDR5 :: RDQS_MODE [05:05] */
-#define BCHP_MEMC_DDR_1_DRAM_MODE_3_GDDR5_RDQS_MODE_MASK 0x00000020
-#define BCHP_MEMC_DDR_1_DRAM_MODE_3_GDDR5_RDQS_MODE_SHIFT 5
-#define BCHP_MEMC_DDR_1_DRAM_MODE_3_GDDR5_RDQS_MODE_DEFAULT 0x00000000
-#define BCHP_MEMC_DDR_1_DRAM_MODE_3_GDDR5_RDQS_MODE_ENABLE 1
-#define BCHP_MEMC_DDR_1_DRAM_MODE_3_GDDR5_RDQS_MODE_DISABLE 0
-
-/* MEMC_DDR_1 :: DRAM_MODE_3 :: GDDR5 :: WCK2CK_TRAIN [04:04] */
-#define BCHP_MEMC_DDR_1_DRAM_MODE_3_GDDR5_WCK2CK_TRAIN_MASK 0x00000010
-#define BCHP_MEMC_DDR_1_DRAM_MODE_3_GDDR5_WCK2CK_TRAIN_SHIFT 4
-#define BCHP_MEMC_DDR_1_DRAM_MODE_3_GDDR5_WCK2CK_TRAIN_DEFAULT 0x00000000
-#define BCHP_MEMC_DDR_1_DRAM_MODE_3_GDDR5_WCK2CK_TRAIN_ENABLE 1
-#define BCHP_MEMC_DDR_1_DRAM_MODE_3_GDDR5_WCK2CK_TRAIN_DISABLE 0
-
-/* MEMC_DDR_1 :: DRAM_MODE_3 :: GDDR5 :: WCK23_INVERT [03:03] */
-#define BCHP_MEMC_DDR_1_DRAM_MODE_3_GDDR5_WCK23_INVERT_MASK 0x00000008
-#define BCHP_MEMC_DDR_1_DRAM_MODE_3_GDDR5_WCK23_INVERT_SHIFT 3
-#define BCHP_MEMC_DDR_1_DRAM_MODE_3_GDDR5_WCK23_INVERT_DEFAULT 0x00000000
-#define BCHP_MEMC_DDR_1_DRAM_MODE_3_GDDR5_WCK23_INVERT_ENABLE 1
-#define BCHP_MEMC_DDR_1_DRAM_MODE_3_GDDR5_WCK23_INVERT_DISABLE 0
-
-/* MEMC_DDR_1 :: DRAM_MODE_3 :: GDDR5 :: WCK01_INVERT [02:02] */
-#define BCHP_MEMC_DDR_1_DRAM_MODE_3_GDDR5_WCK01_INVERT_MASK 0x00000004
-#define BCHP_MEMC_DDR_1_DRAM_MODE_3_GDDR5_WCK01_INVERT_SHIFT 2
-#define BCHP_MEMC_DDR_1_DRAM_MODE_3_GDDR5_WCK01_INVERT_DEFAULT 0x00000000
-#define BCHP_MEMC_DDR_1_DRAM_MODE_3_GDDR5_WCK01_INVERT_ENABLE 1
-#define BCHP_MEMC_DDR_1_DRAM_MODE_3_GDDR5_WCK01_INVERT_DISABLE 0
-
-/* MEMC_DDR_1 :: DRAM_MODE_3 :: GDDR5 :: SELF_REFRESH [01:00] */
-#define BCHP_MEMC_DDR_1_DRAM_MODE_3_GDDR5_SELF_REFRESH_MASK 0x00000003
-#define BCHP_MEMC_DDR_1_DRAM_MODE_3_GDDR5_SELF_REFRESH_SHIFT 0
-#define BCHP_MEMC_DDR_1_DRAM_MODE_3_GDDR5_SELF_REFRESH_DEFAULT 0x00000000
-
-/* union - case Others [12:00] */
-/* MEMC_DDR_1 :: DRAM_MODE_3 :: Others :: unused_1 [12:00] */
-#define BCHP_MEMC_DDR_1_DRAM_MODE_3_Others_unused_1_MASK 0x00001fff
-#define BCHP_MEMC_DDR_1_DRAM_MODE_3_Others_unused_1_SHIFT 0
-#define BCHP_MEMC_DDR_1_DRAM_MODE_3_Others_unused_1_DEFAULT 0x00000000
-
-/***************************************************************************
- *DRAM_MODE_4 - Dram Mode Register 4
- ***************************************************************************/
-/* MEMC_DDR_1 :: DRAM_MODE_4 :: reserved0 [31:16] */
-#define BCHP_MEMC_DDR_1_DRAM_MODE_4_reserved0_MASK 0xffff0000
-#define BCHP_MEMC_DDR_1_DRAM_MODE_4_reserved0_SHIFT 16
-
-/* MEMC_DDR_1 :: DRAM_MODE_4 :: unused_0 [15:13] */
-#define BCHP_MEMC_DDR_1_DRAM_MODE_4_unused_0_MASK 0x0000e000
-#define BCHP_MEMC_DDR_1_DRAM_MODE_4_unused_0_SHIFT 13
-#define BCHP_MEMC_DDR_1_DRAM_MODE_4_unused_0_DEFAULT 0x00000000
-
-/* union - case DDR4 [12:00] */
-/* MEMC_DDR_1 :: DRAM_MODE_4 :: DDR4 :: WR_PREAMBLE [12:12] */
-#define BCHP_MEMC_DDR_1_DRAM_MODE_4_DDR4_WR_PREAMBLE_MASK 0x00001000
-#define BCHP_MEMC_DDR_1_DRAM_MODE_4_DDR4_WR_PREAMBLE_SHIFT 12
-#define BCHP_MEMC_DDR_1_DRAM_MODE_4_DDR4_WR_PREAMBLE_DEFAULT 0x00000000
-
-/* MEMC_DDR_1 :: DRAM_MODE_4 :: DDR4 :: RD_PREAMBLE [11:11] */
-#define BCHP_MEMC_DDR_1_DRAM_MODE_4_DDR4_RD_PREAMBLE_MASK 0x00000800
-#define BCHP_MEMC_DDR_1_DRAM_MODE_4_DDR4_RD_PREAMBLE_SHIFT 11
-#define BCHP_MEMC_DDR_1_DRAM_MODE_4_DDR4_RD_PREAMBLE_DEFAULT 0x00000000
-
-/* MEMC_DDR_1 :: DRAM_MODE_4 :: DDR4 :: RD_PREAMBLE_TRAINING [10:10] */
-#define BCHP_MEMC_DDR_1_DRAM_MODE_4_DDR4_RD_PREAMBLE_TRAINING_MASK 0x00000400
-#define BCHP_MEMC_DDR_1_DRAM_MODE_4_DDR4_RD_PREAMBLE_TRAINING_SHIFT 10
-#define BCHP_MEMC_DDR_1_DRAM_MODE_4_DDR4_RD_PREAMBLE_TRAINING_DEFAULT 0x00000000
-#define BCHP_MEMC_DDR_1_DRAM_MODE_4_DDR4_RD_PREAMBLE_TRAINING_ENABLE 1
-#define BCHP_MEMC_DDR_1_DRAM_MODE_4_DDR4_RD_PREAMBLE_TRAINING_DISABLE 0
-
-/* MEMC_DDR_1 :: DRAM_MODE_4 :: DDR4 :: SELF_REFRESH_ABORT [09:09] */
-#define BCHP_MEMC_DDR_1_DRAM_MODE_4_DDR4_SELF_REFRESH_ABORT_MASK 0x00000200
-#define BCHP_MEMC_DDR_1_DRAM_MODE_4_DDR4_SELF_REFRESH_ABORT_SHIFT 9
-#define BCHP_MEMC_DDR_1_DRAM_MODE_4_DDR4_SELF_REFRESH_ABORT_DEFAULT 0x00000000
-#define BCHP_MEMC_DDR_1_DRAM_MODE_4_DDR4_SELF_REFRESH_ABORT_ENABLE 1
-#define BCHP_MEMC_DDR_1_DRAM_MODE_4_DDR4_SELF_REFRESH_ABORT_DISABLE 0
-
-/* MEMC_DDR_1 :: DRAM_MODE_4 :: DDR4 :: CMD_ADDR_LATENCY [08:06] */
-#define BCHP_MEMC_DDR_1_DRAM_MODE_4_DDR4_CMD_ADDR_LATENCY_MASK 0x000001c0
-#define BCHP_MEMC_DDR_1_DRAM_MODE_4_DDR4_CMD_ADDR_LATENCY_SHIFT 6
-#define BCHP_MEMC_DDR_1_DRAM_MODE_4_DDR4_CMD_ADDR_LATENCY_DEFAULT 0x00000000
-
-/* MEMC_DDR_1 :: DRAM_MODE_4 :: DDR4 :: CMD_ADDR_PARITY [05:05] */
-#define BCHP_MEMC_DDR_1_DRAM_MODE_4_DDR4_CMD_ADDR_PARITY_MASK 0x00000020
-#define BCHP_MEMC_DDR_1_DRAM_MODE_4_DDR4_CMD_ADDR_PARITY_SHIFT 5
-#define BCHP_MEMC_DDR_1_DRAM_MODE_4_DDR4_CMD_ADDR_PARITY_DEFAULT 0x00000000
-#define BCHP_MEMC_DDR_1_DRAM_MODE_4_DDR4_CMD_ADDR_PARITY_ENABLE 1
-#define BCHP_MEMC_DDR_1_DRAM_MODE_4_DDR4_CMD_ADDR_PARITY_DISABLE 0
-
-/* MEMC_DDR_1 :: DRAM_MODE_4 :: DDR4 :: VREF_MONITOR [04:04] */
-#define BCHP_MEMC_DDR_1_DRAM_MODE_4_DDR4_VREF_MONITOR_MASK 0x00000010
-#define BCHP_MEMC_DDR_1_DRAM_MODE_4_DDR4_VREF_MONITOR_SHIFT 4
-#define BCHP_MEMC_DDR_1_DRAM_MODE_4_DDR4_VREF_MONITOR_DEFAULT 0x00000000
-#define BCHP_MEMC_DDR_1_DRAM_MODE_4_DDR4_VREF_MONITOR_ENABLE 1
-#define BCHP_MEMC_DDR_1_DRAM_MODE_4_DDR4_VREF_MONITOR_DISABLE 0
-
-/* MEMC_DDR_1 :: DRAM_MODE_4 :: DDR4 :: TEMP_CONTROLLED_REFRESH [03:03] */
-#define BCHP_MEMC_DDR_1_DRAM_MODE_4_DDR4_TEMP_CONTROLLED_REFRESH_MASK 0x00000008
-#define BCHP_MEMC_DDR_1_DRAM_MODE_4_DDR4_TEMP_CONTROLLED_REFRESH_SHIFT 3
-#define BCHP_MEMC_DDR_1_DRAM_MODE_4_DDR4_TEMP_CONTROLLED_REFRESH_DEFAULT 0x00000000
-#define BCHP_MEMC_DDR_1_DRAM_MODE_4_DDR4_TEMP_CONTROLLED_REFRESH_ENABLE 1
-#define BCHP_MEMC_DDR_1_DRAM_MODE_4_DDR4_TEMP_CONTROLLED_REFRESH_DISABLE 0
-
-/* MEMC_DDR_1 :: DRAM_MODE_4 :: DDR4 :: TEMP_CONTROLLED_REFRESH_RANGE [02:02] */
-#define BCHP_MEMC_DDR_1_DRAM_MODE_4_DDR4_TEMP_CONTROLLED_REFRESH_RANGE_MASK 0x00000004
-#define BCHP_MEMC_DDR_1_DRAM_MODE_4_DDR4_TEMP_CONTROLLED_REFRESH_RANGE_SHIFT 2
-#define BCHP_MEMC_DDR_1_DRAM_MODE_4_DDR4_TEMP_CONTROLLED_REFRESH_RANGE_DEFAULT 0x00000000
-
-/* MEMC_DDR_1 :: DRAM_MODE_4 :: DDR4 :: MAXIMUM_POWER_SAVINGS [01:01] */
-#define BCHP_MEMC_DDR_1_DRAM_MODE_4_DDR4_MAXIMUM_POWER_SAVINGS_MASK 0x00000002
-#define BCHP_MEMC_DDR_1_DRAM_MODE_4_DDR4_MAXIMUM_POWER_SAVINGS_SHIFT 1
-#define BCHP_MEMC_DDR_1_DRAM_MODE_4_DDR4_MAXIMUM_POWER_SAVINGS_DEFAULT 0x00000000
-#define BCHP_MEMC_DDR_1_DRAM_MODE_4_DDR4_MAXIMUM_POWER_SAVINGS_ENABLE 1
-#define BCHP_MEMC_DDR_1_DRAM_MODE_4_DDR4_MAXIMUM_POWER_SAVINGS_DISABLE 0
-
-/* MEMC_DDR_1 :: DRAM_MODE_4 :: DDR4 :: unused_1 [00:00] */
-#define BCHP_MEMC_DDR_1_DRAM_MODE_4_DDR4_unused_1_MASK 0x00000001
-#define BCHP_MEMC_DDR_1_DRAM_MODE_4_DDR4_unused_1_SHIFT 0
-#define BCHP_MEMC_DDR_1_DRAM_MODE_4_DDR4_unused_1_DEFAULT 0x00000000
-
-/* union - case GDDR5M [12:00] */
-/* MEMC_DDR_1 :: DRAM_MODE_4 :: GDDR5M :: unused_1 [12:12] */
-#define BCHP_MEMC_DDR_1_DRAM_MODE_4_GDDR5M_unused_1_MASK 0x00001000
-#define BCHP_MEMC_DDR_1_DRAM_MODE_4_GDDR5M_unused_1_SHIFT 12
-#define BCHP_MEMC_DDR_1_DRAM_MODE_4_GDDR5M_unused_1_DEFAULT 0x00000000
-
-/* MEMC_DDR_1 :: DRAM_MODE_4 :: GDDR5M :: EDC_HOLD_INVERT [11:11] */
-#define BCHP_MEMC_DDR_1_DRAM_MODE_4_GDDR5M_EDC_HOLD_INVERT_MASK 0x00000800
-#define BCHP_MEMC_DDR_1_DRAM_MODE_4_GDDR5M_EDC_HOLD_INVERT_SHIFT 11
-#define BCHP_MEMC_DDR_1_DRAM_MODE_4_GDDR5M_EDC_HOLD_INVERT_DEFAULT 0x00000000
-
-/* MEMC_DDR_1 :: DRAM_MODE_4 :: GDDR5M :: WR_CRC [10:10] */
-#define BCHP_MEMC_DDR_1_DRAM_MODE_4_GDDR5M_WR_CRC_MASK 0x00000400
-#define BCHP_MEMC_DDR_1_DRAM_MODE_4_GDDR5M_WR_CRC_SHIFT 10
-#define BCHP_MEMC_DDR_1_DRAM_MODE_4_GDDR5M_WR_CRC_DEFAULT 0x00000001
-#define BCHP_MEMC_DDR_1_DRAM_MODE_4_GDDR5M_WR_CRC_ENABLE 0
-#define BCHP_MEMC_DDR_1_DRAM_MODE_4_GDDR5M_WR_CRC_DISABLE 1
-
-/* MEMC_DDR_1 :: DRAM_MODE_4 :: GDDR5M :: RD_CRC [09:09] */
-#define BCHP_MEMC_DDR_1_DRAM_MODE_4_GDDR5M_RD_CRC_MASK 0x00000200
-#define BCHP_MEMC_DDR_1_DRAM_MODE_4_GDDR5M_RD_CRC_SHIFT 9
-#define BCHP_MEMC_DDR_1_DRAM_MODE_4_GDDR5M_RD_CRC_DEFAULT 0x00000001
-#define BCHP_MEMC_DDR_1_DRAM_MODE_4_GDDR5M_RD_CRC_ENABLE 0
-#define BCHP_MEMC_DDR_1_DRAM_MODE_4_GDDR5M_RD_CRC_DISABLE 1
-
-/* MEMC_DDR_1 :: DRAM_MODE_4 :: GDDR5M :: CRC_RD_LATENCY [08:07] */
-#define BCHP_MEMC_DDR_1_DRAM_MODE_4_GDDR5M_CRC_RD_LATENCY_MASK 0x00000180
-#define BCHP_MEMC_DDR_1_DRAM_MODE_4_GDDR5M_CRC_RD_LATENCY_SHIFT 7
-#define BCHP_MEMC_DDR_1_DRAM_MODE_4_GDDR5M_CRC_RD_LATENCY_DEFAULT 0x00000000
-
-/* MEMC_DDR_1 :: DRAM_MODE_4 :: GDDR5M :: CRC_WR_LATENCY [06:04] */
-#define BCHP_MEMC_DDR_1_DRAM_MODE_4_GDDR5M_CRC_WR_LATENCY_MASK 0x00000070
-#define BCHP_MEMC_DDR_1_DRAM_MODE_4_GDDR5M_CRC_WR_LATENCY_SHIFT 4
-#define BCHP_MEMC_DDR_1_DRAM_MODE_4_GDDR5M_CRC_WR_LATENCY_DEFAULT 0x00000000
-
-/* MEMC_DDR_1 :: DRAM_MODE_4 :: GDDR5M :: EDC_HOLD_PATTERN [03:00] */
-#define BCHP_MEMC_DDR_1_DRAM_MODE_4_GDDR5M_EDC_HOLD_PATTERN_MASK 0x0000000f
-#define BCHP_MEMC_DDR_1_DRAM_MODE_4_GDDR5M_EDC_HOLD_PATTERN_SHIFT 0
-#define BCHP_MEMC_DDR_1_DRAM_MODE_4_GDDR5M_EDC_HOLD_PATTERN_DEFAULT 0x00000000
-
-/* union - case GDDR5 [12:00] */
-/* MEMC_DDR_1 :: DRAM_MODE_4 :: GDDR5 :: unused_1 [12:12] */
-#define BCHP_MEMC_DDR_1_DRAM_MODE_4_GDDR5_unused_1_MASK 0x00001000
-#define BCHP_MEMC_DDR_1_DRAM_MODE_4_GDDR5_unused_1_SHIFT 12
-#define BCHP_MEMC_DDR_1_DRAM_MODE_4_GDDR5_unused_1_DEFAULT 0x00000000
-
-/* MEMC_DDR_1 :: DRAM_MODE_4 :: GDDR5 :: EDC_HOLD_INVERT [11:11] */
-#define BCHP_MEMC_DDR_1_DRAM_MODE_4_GDDR5_EDC_HOLD_INVERT_MASK 0x00000800
-#define BCHP_MEMC_DDR_1_DRAM_MODE_4_GDDR5_EDC_HOLD_INVERT_SHIFT 11
-#define BCHP_MEMC_DDR_1_DRAM_MODE_4_GDDR5_EDC_HOLD_INVERT_DEFAULT 0x00000000
-
-/* MEMC_DDR_1 :: DRAM_MODE_4 :: GDDR5 :: WR_CRC [10:10] */
-#define BCHP_MEMC_DDR_1_DRAM_MODE_4_GDDR5_WR_CRC_MASK 0x00000400
-#define BCHP_MEMC_DDR_1_DRAM_MODE_4_GDDR5_WR_CRC_SHIFT 10
-#define BCHP_MEMC_DDR_1_DRAM_MODE_4_GDDR5_WR_CRC_DEFAULT 0x00000001
-#define BCHP_MEMC_DDR_1_DRAM_MODE_4_GDDR5_WR_CRC_ENABLE 0
-#define BCHP_MEMC_DDR_1_DRAM_MODE_4_GDDR5_WR_CRC_DISABLE 1
-
-/* MEMC_DDR_1 :: DRAM_MODE_4 :: GDDR5 :: RD_CRC [09:09] */
-#define BCHP_MEMC_DDR_1_DRAM_MODE_4_GDDR5_RD_CRC_MASK 0x00000200
-#define BCHP_MEMC_DDR_1_DRAM_MODE_4_GDDR5_RD_CRC_SHIFT 9
-#define BCHP_MEMC_DDR_1_DRAM_MODE_4_GDDR5_RD_CRC_DEFAULT 0x00000001
-#define BCHP_MEMC_DDR_1_DRAM_MODE_4_GDDR5_RD_CRC_ENABLE 0
-#define BCHP_MEMC_DDR_1_DRAM_MODE_4_GDDR5_RD_CRC_DISABLE 1
-
-/* MEMC_DDR_1 :: DRAM_MODE_4 :: GDDR5 :: CRC_RD_LATENCY [08:07] */
-#define BCHP_MEMC_DDR_1_DRAM_MODE_4_GDDR5_CRC_RD_LATENCY_MASK 0x00000180
-#define BCHP_MEMC_DDR_1_DRAM_MODE_4_GDDR5_CRC_RD_LATENCY_SHIFT 7
-#define BCHP_MEMC_DDR_1_DRAM_MODE_4_GDDR5_CRC_RD_LATENCY_DEFAULT 0x00000000
-
-/* MEMC_DDR_1 :: DRAM_MODE_4 :: GDDR5 :: CRC_WR_LATENCY [06:04] */
-#define BCHP_MEMC_DDR_1_DRAM_MODE_4_GDDR5_CRC_WR_LATENCY_MASK 0x00000070
-#define BCHP_MEMC_DDR_1_DRAM_MODE_4_GDDR5_CRC_WR_LATENCY_SHIFT 4
-#define BCHP_MEMC_DDR_1_DRAM_MODE_4_GDDR5_CRC_WR_LATENCY_DEFAULT 0x00000000
-
-/* MEMC_DDR_1 :: DRAM_MODE_4 :: GDDR5 :: EDC_HOLD_PATTERN [03:00] */
-#define BCHP_MEMC_DDR_1_DRAM_MODE_4_GDDR5_EDC_HOLD_PATTERN_MASK 0x0000000f
-#define BCHP_MEMC_DDR_1_DRAM_MODE_4_GDDR5_EDC_HOLD_PATTERN_SHIFT 0
-#define BCHP_MEMC_DDR_1_DRAM_MODE_4_GDDR5_EDC_HOLD_PATTERN_DEFAULT 0x00000000
-
-/* union - case Others [12:00] */
-/* MEMC_DDR_1 :: DRAM_MODE_4 :: Others :: unused_1 [12:00] */
-#define BCHP_MEMC_DDR_1_DRAM_MODE_4_Others_unused_1_MASK 0x00001fff
-#define BCHP_MEMC_DDR_1_DRAM_MODE_4_Others_unused_1_SHIFT 0
-#define BCHP_MEMC_DDR_1_DRAM_MODE_4_Others_unused_1_DEFAULT 0x00000000
-
-/***************************************************************************
- *DRAM_MODE_5 - Dram Mode Register 5
- ***************************************************************************/
-/* MEMC_DDR_1 :: DRAM_MODE_5 :: reserved0 [31:16] */
-#define BCHP_MEMC_DDR_1_DRAM_MODE_5_reserved0_MASK 0xffff0000
-#define BCHP_MEMC_DDR_1_DRAM_MODE_5_reserved0_SHIFT 16
-
-/* MEMC_DDR_1 :: DRAM_MODE_5 :: unused_0 [15:13] */
-#define BCHP_MEMC_DDR_1_DRAM_MODE_5_unused_0_MASK 0x0000e000
-#define BCHP_MEMC_DDR_1_DRAM_MODE_5_unused_0_SHIFT 13
-#define BCHP_MEMC_DDR_1_DRAM_MODE_5_unused_0_DEFAULT 0x00000000
-
-/* union - case DDR4 [12:00] */
-/* MEMC_DDR_1 :: DRAM_MODE_5 :: DDR4 :: RD_DBI [12:12] */
-#define BCHP_MEMC_DDR_1_DRAM_MODE_5_DDR4_RD_DBI_MASK 0x00001000
-#define BCHP_MEMC_DDR_1_DRAM_MODE_5_DDR4_RD_DBI_SHIFT 12
-#define BCHP_MEMC_DDR_1_DRAM_MODE_5_DDR4_RD_DBI_DEFAULT 0x00000000
-#define BCHP_MEMC_DDR_1_DRAM_MODE_5_DDR4_RD_DBI_ENABLE 1
-#define BCHP_MEMC_DDR_1_DRAM_MODE_5_DDR4_RD_DBI_DISABLE 0
-
-/* MEMC_DDR_1 :: DRAM_MODE_5 :: DDR4 :: WR_DBI [11:11] */
-#define BCHP_MEMC_DDR_1_DRAM_MODE_5_DDR4_WR_DBI_MASK 0x00000800
-#define BCHP_MEMC_DDR_1_DRAM_MODE_5_DDR4_WR_DBI_SHIFT 11
-#define BCHP_MEMC_DDR_1_DRAM_MODE_5_DDR4_WR_DBI_DEFAULT 0x00000000
-#define BCHP_MEMC_DDR_1_DRAM_MODE_5_DDR4_WR_DBI_ENABLE 1
-#define BCHP_MEMC_DDR_1_DRAM_MODE_5_DDR4_WR_DBI_DISABLE 0
-
-/* MEMC_DDR_1 :: DRAM_MODE_5 :: DDR4 :: DM [10:10] */
-#define BCHP_MEMC_DDR_1_DRAM_MODE_5_DDR4_DM_MASK 0x00000400
-#define BCHP_MEMC_DDR_1_DRAM_MODE_5_DDR4_DM_SHIFT 10
-#define BCHP_MEMC_DDR_1_DRAM_MODE_5_DDR4_DM_DEFAULT 0x00000000
-#define BCHP_MEMC_DDR_1_DRAM_MODE_5_DDR4_DM_ENABLE 1
-#define BCHP_MEMC_DDR_1_DRAM_MODE_5_DDR4_DM_DISABLE 0
-
-/* MEMC_DDR_1 :: DRAM_MODE_5 :: DDR4 :: unused_1 [09:09] */
-#define BCHP_MEMC_DDR_1_DRAM_MODE_5_DDR4_unused_1_MASK 0x00000200
-#define BCHP_MEMC_DDR_1_DRAM_MODE_5_DDR4_unused_1_SHIFT 9
-#define BCHP_MEMC_DDR_1_DRAM_MODE_5_DDR4_unused_1_DEFAULT 0x00000000
-
-/* MEMC_DDR_1 :: DRAM_MODE_5 :: DDR4 :: RTT_PARK [08:06] */
-#define BCHP_MEMC_DDR_1_DRAM_MODE_5_DDR4_RTT_PARK_MASK 0x000001c0
-#define BCHP_MEMC_DDR_1_DRAM_MODE_5_DDR4_RTT_PARK_SHIFT 6
-#define BCHP_MEMC_DDR_1_DRAM_MODE_5_DDR4_RTT_PARK_DEFAULT 0x00000000
-
-/* MEMC_DDR_1 :: DRAM_MODE_5 :: DDR4 :: unused_2 [05:05] */
-#define BCHP_MEMC_DDR_1_DRAM_MODE_5_DDR4_unused_2_MASK 0x00000020
-#define BCHP_MEMC_DDR_1_DRAM_MODE_5_DDR4_unused_2_SHIFT 5
-#define BCHP_MEMC_DDR_1_DRAM_MODE_5_DDR4_unused_2_DEFAULT 0x00000000
-
-/* MEMC_DDR_1 :: DRAM_MODE_5 :: DDR4 :: CMD_ADDR_PARITY_ERROR [04:04] */
-#define BCHP_MEMC_DDR_1_DRAM_MODE_5_DDR4_CMD_ADDR_PARITY_ERROR_MASK 0x00000010
-#define BCHP_MEMC_DDR_1_DRAM_MODE_5_DDR4_CMD_ADDR_PARITY_ERROR_SHIFT 4
-#define BCHP_MEMC_DDR_1_DRAM_MODE_5_DDR4_CMD_ADDR_PARITY_ERROR_DEFAULT 0x00000000
-
-/* MEMC_DDR_1 :: DRAM_MODE_5 :: DDR4 :: CRC_ERROR [03:03] */
-#define BCHP_MEMC_DDR_1_DRAM_MODE_5_DDR4_CRC_ERROR_MASK 0x00000008
-#define BCHP_MEMC_DDR_1_DRAM_MODE_5_DDR4_CRC_ERROR_SHIFT 3
-#define BCHP_MEMC_DDR_1_DRAM_MODE_5_DDR4_CRC_ERROR_DEFAULT 0x00000000
-
-/* MEMC_DDR_1 :: DRAM_MODE_5 :: DDR4 :: CMD_ADDR_PARITY_LATENCY [02:00] */
-#define BCHP_MEMC_DDR_1_DRAM_MODE_5_DDR4_CMD_ADDR_PARITY_LATENCY_MASK 0x00000007
-#define BCHP_MEMC_DDR_1_DRAM_MODE_5_DDR4_CMD_ADDR_PARITY_LATENCY_SHIFT 0
-#define BCHP_MEMC_DDR_1_DRAM_MODE_5_DDR4_CMD_ADDR_PARITY_LATENCY_DEFAULT 0x00000000
-
-/* union - case GDDR5M [12:00] */
-/* MEMC_DDR_1 :: DRAM_MODE_5 :: GDDR5M :: unused_1 [12:12] */
-#define BCHP_MEMC_DDR_1_DRAM_MODE_5_GDDR5M_unused_1_MASK 0x00001000
-#define BCHP_MEMC_DDR_1_DRAM_MODE_5_GDDR5M_unused_1_SHIFT 12
-#define BCHP_MEMC_DDR_1_DRAM_MODE_5_GDDR5M_unused_1_DEFAULT 0x00000000
-
-/* MEMC_DDR_1 :: DRAM_MODE_5 :: GDDR5M :: RAS [11:06] */
-#define BCHP_MEMC_DDR_1_DRAM_MODE_5_GDDR5M_RAS_MASK 0x00000fc0
-#define BCHP_MEMC_DDR_1_DRAM_MODE_5_GDDR5M_RAS_SHIFT 6
-#define BCHP_MEMC_DDR_1_DRAM_MODE_5_GDDR5M_RAS_DEFAULT 0x00000000
-
-/* MEMC_DDR_1 :: DRAM_MODE_5 :: GDDR5M :: unused_2 [05:03] */
-#define BCHP_MEMC_DDR_1_DRAM_MODE_5_GDDR5M_unused_2_MASK 0x00000038
-#define BCHP_MEMC_DDR_1_DRAM_MODE_5_GDDR5M_unused_2_SHIFT 3
-#define BCHP_MEMC_DDR_1_DRAM_MODE_5_GDDR5M_unused_2_DEFAULT 0x00000000
-
-/* MEMC_DDR_1 :: DRAM_MODE_5 :: GDDR5M :: LP3 [02:02] */
-#define BCHP_MEMC_DDR_1_DRAM_MODE_5_GDDR5M_LP3_MASK 0x00000004
-#define BCHP_MEMC_DDR_1_DRAM_MODE_5_GDDR5M_LP3_SHIFT 2
-#define BCHP_MEMC_DDR_1_DRAM_MODE_5_GDDR5M_LP3_DEFAULT 0x00000000
-#define BCHP_MEMC_DDR_1_DRAM_MODE_5_GDDR5M_LP3_ENABLE 1
-#define BCHP_MEMC_DDR_1_DRAM_MODE_5_GDDR5M_LP3_DISABLE 0
-
-/* MEMC_DDR_1 :: DRAM_MODE_5 :: GDDR5M :: LP2 [01:01] */
-#define BCHP_MEMC_DDR_1_DRAM_MODE_5_GDDR5M_LP2_MASK 0x00000002
-#define BCHP_MEMC_DDR_1_DRAM_MODE_5_GDDR5M_LP2_SHIFT 1
-#define BCHP_MEMC_DDR_1_DRAM_MODE_5_GDDR5M_LP2_DEFAULT 0x00000000
-#define BCHP_MEMC_DDR_1_DRAM_MODE_5_GDDR5M_LP2_ENABLE 1
-#define BCHP_MEMC_DDR_1_DRAM_MODE_5_GDDR5M_LP2_DISABLE 0
-
-/* MEMC_DDR_1 :: DRAM_MODE_5 :: GDDR5M :: LP1 [00:00] */
-#define BCHP_MEMC_DDR_1_DRAM_MODE_5_GDDR5M_LP1_MASK 0x00000001
-#define BCHP_MEMC_DDR_1_DRAM_MODE_5_GDDR5M_LP1_SHIFT 0
-#define BCHP_MEMC_DDR_1_DRAM_MODE_5_GDDR5M_LP1_DEFAULT 0x00000000
-#define BCHP_MEMC_DDR_1_DRAM_MODE_5_GDDR5M_LP1_ENABLE 1
-#define BCHP_MEMC_DDR_1_DRAM_MODE_5_GDDR5M_LP1_DISABLE 0
-
-/* union - case GDDR5 [12:00] */
-/* MEMC_DDR_1 :: DRAM_MODE_5 :: GDDR5 :: unused_1 [12:12] */
-#define BCHP_MEMC_DDR_1_DRAM_MODE_5_GDDR5_unused_1_MASK 0x00001000
-#define BCHP_MEMC_DDR_1_DRAM_MODE_5_GDDR5_unused_1_SHIFT 12
-#define BCHP_MEMC_DDR_1_DRAM_MODE_5_GDDR5_unused_1_DEFAULT 0x00000000
-
-/* MEMC_DDR_1 :: DRAM_MODE_5 :: GDDR5 :: RAS [11:06] */
-#define BCHP_MEMC_DDR_1_DRAM_MODE_5_GDDR5_RAS_MASK 0x00000fc0
-#define BCHP_MEMC_DDR_1_DRAM_MODE_5_GDDR5_RAS_SHIFT 6
-#define BCHP_MEMC_DDR_1_DRAM_MODE_5_GDDR5_RAS_DEFAULT 0x00000000
-
-/* MEMC_DDR_1 :: DRAM_MODE_5 :: GDDR5 :: PLL_DLL_BANDWIDTH [05:03] */
-#define BCHP_MEMC_DDR_1_DRAM_MODE_5_GDDR5_PLL_DLL_BANDWIDTH_MASK 0x00000038
-#define BCHP_MEMC_DDR_1_DRAM_MODE_5_GDDR5_PLL_DLL_BANDWIDTH_SHIFT 3
-#define BCHP_MEMC_DDR_1_DRAM_MODE_5_GDDR5_PLL_DLL_BANDWIDTH_DEFAULT 0x00000000
-
-/* MEMC_DDR_1 :: DRAM_MODE_5 :: GDDR5 :: LP3 [02:02] */
-#define BCHP_MEMC_DDR_1_DRAM_MODE_5_GDDR5_LP3_MASK 0x00000004
-#define BCHP_MEMC_DDR_1_DRAM_MODE_5_GDDR5_LP3_SHIFT 2
-#define BCHP_MEMC_DDR_1_DRAM_MODE_5_GDDR5_LP3_DEFAULT 0x00000000
-#define BCHP_MEMC_DDR_1_DRAM_MODE_5_GDDR5_LP3_ENABLE 1
-#define BCHP_MEMC_DDR_1_DRAM_MODE_5_GDDR5_LP3_DISABLE 0
-
-/* MEMC_DDR_1 :: DRAM_MODE_5 :: GDDR5 :: LP2 [01:01] */
-#define BCHP_MEMC_DDR_1_DRAM_MODE_5_GDDR5_LP2_MASK 0x00000002
-#define BCHP_MEMC_DDR_1_DRAM_MODE_5_GDDR5_LP2_SHIFT 1
-#define BCHP_MEMC_DDR_1_DRAM_MODE_5_GDDR5_LP2_DEFAULT 0x00000000
-#define BCHP_MEMC_DDR_1_DRAM_MODE_5_GDDR5_LP2_ENABLE 1
-#define BCHP_MEMC_DDR_1_DRAM_MODE_5_GDDR5_LP2_DISABLE 0
-
-/* MEMC_DDR_1 :: DRAM_MODE_5 :: GDDR5 :: LP1 [00:00] */
-#define BCHP_MEMC_DDR_1_DRAM_MODE_5_GDDR5_LP1_MASK 0x00000001
-#define BCHP_MEMC_DDR_1_DRAM_MODE_5_GDDR5_LP1_SHIFT 0
-#define BCHP_MEMC_DDR_1_DRAM_MODE_5_GDDR5_LP1_DEFAULT 0x00000000
-#define BCHP_MEMC_DDR_1_DRAM_MODE_5_GDDR5_LP1_ENABLE 1
-#define BCHP_MEMC_DDR_1_DRAM_MODE_5_GDDR5_LP1_DISABLE 0
-
-/* union - case Others [12:00] */
-/* MEMC_DDR_1 :: DRAM_MODE_5 :: Others :: unused_1 [12:00] */
-#define BCHP_MEMC_DDR_1_DRAM_MODE_5_Others_unused_1_MASK 0x00001fff
-#define BCHP_MEMC_DDR_1_DRAM_MODE_5_Others_unused_1_SHIFT 0
-#define BCHP_MEMC_DDR_1_DRAM_MODE_5_Others_unused_1_DEFAULT 0x00000000
-
-/***************************************************************************
- *DRAM_MODE_6 - Dram Mode Register 6
- ***************************************************************************/
-/* MEMC_DDR_1 :: DRAM_MODE_6 :: reserved0 [31:16] */
-#define BCHP_MEMC_DDR_1_DRAM_MODE_6_reserved0_MASK 0xffff0000
-#define BCHP_MEMC_DDR_1_DRAM_MODE_6_reserved0_SHIFT 16
-
-/* MEMC_DDR_1 :: DRAM_MODE_6 :: unused_0 [15:13] */
-#define BCHP_MEMC_DDR_1_DRAM_MODE_6_unused_0_MASK 0x0000e000
-#define BCHP_MEMC_DDR_1_DRAM_MODE_6_unused_0_SHIFT 13
-#define BCHP_MEMC_DDR_1_DRAM_MODE_6_unused_0_DEFAULT 0x00000000
-
-/* union - case DDR4 [12:00] */
-/* MEMC_DDR_1 :: DRAM_MODE_6 :: DDR4 :: unused_1 [12:07] */
-#define BCHP_MEMC_DDR_1_DRAM_MODE_6_DDR4_unused_1_MASK 0x00001f80
-#define BCHP_MEMC_DDR_1_DRAM_MODE_6_DDR4_unused_1_SHIFT 7
-#define BCHP_MEMC_DDR_1_DRAM_MODE_6_DDR4_unused_1_DEFAULT 0x00000000
-
-/* MEMC_DDR_1 :: DRAM_MODE_6 :: DDR4 :: VREF_TRAINING_RANGE [06:06] */
-#define BCHP_MEMC_DDR_1_DRAM_MODE_6_DDR4_VREF_TRAINING_RANGE_MASK 0x00000040
-#define BCHP_MEMC_DDR_1_DRAM_MODE_6_DDR4_VREF_TRAINING_RANGE_SHIFT 6
-#define BCHP_MEMC_DDR_1_DRAM_MODE_6_DDR4_VREF_TRAINING_RANGE_DEFAULT 0x00000000
-
-/* MEMC_DDR_1 :: DRAM_MODE_6 :: DDR4 :: VREF_TRAINING [05:00] */
-#define BCHP_MEMC_DDR_1_DRAM_MODE_6_DDR4_VREF_TRAINING_MASK 0x0000003f
-#define BCHP_MEMC_DDR_1_DRAM_MODE_6_DDR4_VREF_TRAINING_SHIFT 0
-#define BCHP_MEMC_DDR_1_DRAM_MODE_6_DDR4_VREF_TRAINING_DEFAULT 0x00000000
-
-/* union - case GDDR5M [12:00] */
-/* MEMC_DDR_1 :: DRAM_MODE_6 :: GDDR5M :: unused_1 [12:12] */
-#define BCHP_MEMC_DDR_1_DRAM_MODE_6_GDDR5M_unused_1_MASK 0x00001000
-#define BCHP_MEMC_DDR_1_DRAM_MODE_6_GDDR5M_unused_1_SHIFT 12
-#define BCHP_MEMC_DDR_1_DRAM_MODE_6_GDDR5M_unused_1_DEFAULT 0x00000000
-
-/* MEMC_DDR_1 :: DRAM_MODE_6 :: GDDR5M :: VREFD_OFFSET_01 [11:08] */
-#define BCHP_MEMC_DDR_1_DRAM_MODE_6_GDDR5M_VREFD_OFFSET_01_MASK 0x00000f00
-#define BCHP_MEMC_DDR_1_DRAM_MODE_6_GDDR5M_VREFD_OFFSET_01_SHIFT 8
-#define BCHP_MEMC_DDR_1_DRAM_MODE_6_GDDR5M_VREFD_OFFSET_01_DEFAULT 0x00000000
-
-/* MEMC_DDR_1 :: DRAM_MODE_6 :: GDDR5M :: VREFD_OFFSET_23 [07:04] */
-#define BCHP_MEMC_DDR_1_DRAM_MODE_6_GDDR5M_VREFD_OFFSET_23_MASK 0x000000f0
-#define BCHP_MEMC_DDR_1_DRAM_MODE_6_GDDR5M_VREFD_OFFSET_23_SHIFT 4
-#define BCHP_MEMC_DDR_1_DRAM_MODE_6_GDDR5M_VREFD_OFFSET_23_DEFAULT 0x00000000
-
-/* MEMC_DDR_1 :: DRAM_MODE_6 :: GDDR5M :: unused_2 [03:01] */
-#define BCHP_MEMC_DDR_1_DRAM_MODE_6_GDDR5M_unused_2_MASK 0x0000000e
-#define BCHP_MEMC_DDR_1_DRAM_MODE_6_GDDR5M_unused_2_SHIFT 1
-#define BCHP_MEMC_DDR_1_DRAM_MODE_6_GDDR5M_unused_2_DEFAULT 0x00000000
-
-/* MEMC_DDR_1 :: DRAM_MODE_6 :: GDDR5M :: WCK2CK_ALIGN [00:00] */
-#define BCHP_MEMC_DDR_1_DRAM_MODE_6_GDDR5M_WCK2CK_ALIGN_MASK 0x00000001
-#define BCHP_MEMC_DDR_1_DRAM_MODE_6_GDDR5M_WCK2CK_ALIGN_SHIFT 0
-#define BCHP_MEMC_DDR_1_DRAM_MODE_6_GDDR5M_WCK2CK_ALIGN_DEFAULT 0x00000000
-
-/* union - case GDDR5 [12:00] */
-/* MEMC_DDR_1 :: DRAM_MODE_6 :: GDDR5 :: unused_1 [12:12] */
-#define BCHP_MEMC_DDR_1_DRAM_MODE_6_GDDR5_unused_1_MASK 0x00001000
-#define BCHP_MEMC_DDR_1_DRAM_MODE_6_GDDR5_unused_1_SHIFT 12
-#define BCHP_MEMC_DDR_1_DRAM_MODE_6_GDDR5_unused_1_DEFAULT 0x00000000
-
-/* MEMC_DDR_1 :: DRAM_MODE_6 :: GDDR5 :: VREFD_OFFSET_01 [11:08] */
-#define BCHP_MEMC_DDR_1_DRAM_MODE_6_GDDR5_VREFD_OFFSET_01_MASK 0x00000f00
-#define BCHP_MEMC_DDR_1_DRAM_MODE_6_GDDR5_VREFD_OFFSET_01_SHIFT 8
-#define BCHP_MEMC_DDR_1_DRAM_MODE_6_GDDR5_VREFD_OFFSET_01_DEFAULT 0x00000000
-
-/* MEMC_DDR_1 :: DRAM_MODE_6 :: GDDR5 :: VREFD_OFFSET_23 [07:04] */
-#define BCHP_MEMC_DDR_1_DRAM_MODE_6_GDDR5_VREFD_OFFSET_23_MASK 0x000000f0
-#define BCHP_MEMC_DDR_1_DRAM_MODE_6_GDDR5_VREFD_OFFSET_23_SHIFT 4
-#define BCHP_MEMC_DDR_1_DRAM_MODE_6_GDDR5_VREFD_OFFSET_23_DEFAULT 0x00000000
-
-/* MEMC_DDR_1 :: DRAM_MODE_6 :: GDDR5 :: VREFD [03:03] */
-#define BCHP_MEMC_DDR_1_DRAM_MODE_6_GDDR5_VREFD_MASK 0x00000008
-#define BCHP_MEMC_DDR_1_DRAM_MODE_6_GDDR5_VREFD_SHIFT 3
-#define BCHP_MEMC_DDR_1_DRAM_MODE_6_GDDR5_VREFD_DEFAULT 0x00000000
-
-/* MEMC_DDR_1 :: DRAM_MODE_6 :: GDDR5 :: AUTO_VREFD [02:02] */
-#define BCHP_MEMC_DDR_1_DRAM_MODE_6_GDDR5_AUTO_VREFD_MASK 0x00000004
-#define BCHP_MEMC_DDR_1_DRAM_MODE_6_GDDR5_AUTO_VREFD_SHIFT 2
-#define BCHP_MEMC_DDR_1_DRAM_MODE_6_GDDR5_AUTO_VREFD_DEFAULT 0x00000000
-
-/* MEMC_DDR_1 :: DRAM_MODE_6 :: GDDR5 :: VREFD_MERGE [01:01] */
-#define BCHP_MEMC_DDR_1_DRAM_MODE_6_GDDR5_VREFD_MERGE_MASK 0x00000002
-#define BCHP_MEMC_DDR_1_DRAM_MODE_6_GDDR5_VREFD_MERGE_SHIFT 1
-#define BCHP_MEMC_DDR_1_DRAM_MODE_6_GDDR5_VREFD_MERGE_DEFAULT 0x00000000
-
-/* MEMC_DDR_1 :: DRAM_MODE_6 :: GDDR5 :: WCK2CK_ALIGN [00:00] */
-#define BCHP_MEMC_DDR_1_DRAM_MODE_6_GDDR5_WCK2CK_ALIGN_MASK 0x00000001
-#define BCHP_MEMC_DDR_1_DRAM_MODE_6_GDDR5_WCK2CK_ALIGN_SHIFT 0
-#define BCHP_MEMC_DDR_1_DRAM_MODE_6_GDDR5_WCK2CK_ALIGN_DEFAULT 0x00000000
-
-/* union - case Others [12:00] */
-/* MEMC_DDR_1 :: DRAM_MODE_6 :: Others :: unused_1 [12:00] */
-#define BCHP_MEMC_DDR_1_DRAM_MODE_6_Others_unused_1_MASK 0x00001fff
-#define BCHP_MEMC_DDR_1_DRAM_MODE_6_Others_unused_1_SHIFT 0
-#define BCHP_MEMC_DDR_1_DRAM_MODE_6_Others_unused_1_DEFAULT 0x00000000
-
-/***************************************************************************
- *DRAM_MODE_7 - Dram Mode Register 7
- ***************************************************************************/
-/* MEMC_DDR_1 :: DRAM_MODE_7 :: reserved0 [31:16] */
-#define BCHP_MEMC_DDR_1_DRAM_MODE_7_reserved0_MASK 0xffff0000
-#define BCHP_MEMC_DDR_1_DRAM_MODE_7_reserved0_SHIFT 16
-
-/* MEMC_DDR_1 :: DRAM_MODE_7 :: unused_0 [15:13] */
-#define BCHP_MEMC_DDR_1_DRAM_MODE_7_unused_0_MASK 0x0000e000
-#define BCHP_MEMC_DDR_1_DRAM_MODE_7_unused_0_SHIFT 13
-#define BCHP_MEMC_DDR_1_DRAM_MODE_7_unused_0_DEFAULT 0x00000000
-
-/* union - case GDDR5M [12:00] */
-/* MEMC_DDR_1 :: DRAM_MODE_7 :: GDDR5M :: unused_1 [12:12] */
-#define BCHP_MEMC_DDR_1_DRAM_MODE_7_GDDR5M_unused_1_MASK 0x00001000
-#define BCHP_MEMC_DDR_1_DRAM_MODE_7_GDDR5M_unused_1_SHIFT 12
-#define BCHP_MEMC_DDR_1_DRAM_MODE_7_GDDR5M_unused_1_DEFAULT 0x00000000
-
-/* MEMC_DDR_1 :: DRAM_MODE_7 :: GDDR5M :: DDC [11:10] */
-#define BCHP_MEMC_DDR_1_DRAM_MODE_7_GDDR5M_DDC_MASK 0x00000c00
-#define BCHP_MEMC_DDR_1_DRAM_MODE_7_GDDR5M_DDC_SHIFT 10
-#define BCHP_MEMC_DDR_1_DRAM_MODE_7_GDDR5M_DDC_DEFAULT 0x00000000
-
-/* MEMC_DDR_1 :: DRAM_MODE_7 :: GDDR5M :: VDD_RANGE [09:08] */
-#define BCHP_MEMC_DDR_1_DRAM_MODE_7_GDDR5M_VDD_RANGE_MASK 0x00000300
-#define BCHP_MEMC_DDR_1_DRAM_MODE_7_GDDR5M_VDD_RANGE_SHIFT 8
-#define BCHP_MEMC_DDR_1_DRAM_MODE_7_GDDR5M_VDD_RANGE_DEFAULT 0x00000000
-
-/* MEMC_DDR_1 :: DRAM_MODE_7 :: GDDR5M :: HALF_VREFD [07:07] */
-#define BCHP_MEMC_DDR_1_DRAM_MODE_7_GDDR5M_HALF_VREFD_MASK 0x00000080
-#define BCHP_MEMC_DDR_1_DRAM_MODE_7_GDDR5M_HALF_VREFD_SHIFT 7
-#define BCHP_MEMC_DDR_1_DRAM_MODE_7_GDDR5M_HALF_VREFD_DEFAULT 0x00000000
-
-/* MEMC_DDR_1 :: DRAM_MODE_7 :: GDDR5M :: TEMP_SENSE [06:06] */
-#define BCHP_MEMC_DDR_1_DRAM_MODE_7_GDDR5M_TEMP_SENSE_MASK 0x00000040
-#define BCHP_MEMC_DDR_1_DRAM_MODE_7_GDDR5M_TEMP_SENSE_SHIFT 6
-#define BCHP_MEMC_DDR_1_DRAM_MODE_7_GDDR5M_TEMP_SENSE_DEFAULT 0x00000000
-#define BCHP_MEMC_DDR_1_DRAM_MODE_7_GDDR5M_TEMP_SENSE_ENABLE 1
-#define BCHP_MEMC_DDR_1_DRAM_MODE_7_GDDR5M_TEMP_SENSE_DISABLE 0
-
-/* MEMC_DDR_1 :: DRAM_MODE_7 :: GDDR5M :: DQ_PREAMBLE [05:05] */
-#define BCHP_MEMC_DDR_1_DRAM_MODE_7_GDDR5M_DQ_PREAMBLE_MASK 0x00000020
-#define BCHP_MEMC_DDR_1_DRAM_MODE_7_GDDR5M_DQ_PREAMBLE_SHIFT 5
-#define BCHP_MEMC_DDR_1_DRAM_MODE_7_GDDR5M_DQ_PREAMBLE_DEFAULT 0x00000000
-#define BCHP_MEMC_DDR_1_DRAM_MODE_7_GDDR5M_DQ_PREAMBLE_ENABLE 1
-#define BCHP_MEMC_DDR_1_DRAM_MODE_7_GDDR5M_DQ_PREAMBLE_DISABLE 0
-
-/* MEMC_DDR_1 :: DRAM_MODE_7 :: GDDR5M :: WCK2CK_AUTO_SYNC [04:04] */
-#define BCHP_MEMC_DDR_1_DRAM_MODE_7_GDDR5M_WCK2CK_AUTO_SYNC_MASK 0x00000010
-#define BCHP_MEMC_DDR_1_DRAM_MODE_7_GDDR5M_WCK2CK_AUTO_SYNC_SHIFT 4
-#define BCHP_MEMC_DDR_1_DRAM_MODE_7_GDDR5M_WCK2CK_AUTO_SYNC_DEFAULT 0x00000000
-#define BCHP_MEMC_DDR_1_DRAM_MODE_7_GDDR5M_WCK2CK_AUTO_SYNC_ENABLE 1
-#define BCHP_MEMC_DDR_1_DRAM_MODE_7_GDDR5M_WCK2CK_AUTO_SYNC_DISABLE 0
-
-/* MEMC_DDR_1 :: DRAM_MODE_7 :: GDDR5M :: LOW_FREQ [03:03] */
-#define BCHP_MEMC_DDR_1_DRAM_MODE_7_GDDR5M_LOW_FREQ_MASK 0x00000008
-#define BCHP_MEMC_DDR_1_DRAM_MODE_7_GDDR5M_LOW_FREQ_SHIFT 3
-#define BCHP_MEMC_DDR_1_DRAM_MODE_7_GDDR5M_LOW_FREQ_DEFAULT 0x00000000
-#define BCHP_MEMC_DDR_1_DRAM_MODE_7_GDDR5M_LOW_FREQ_ENABLE 1
-#define BCHP_MEMC_DDR_1_DRAM_MODE_7_GDDR5M_LOW_FREQ_DISABLE 0
-
-/* MEMC_DDR_1 :: DRAM_MODE_7 :: GDDR5M :: unused_2 [02:00] */
-#define BCHP_MEMC_DDR_1_DRAM_MODE_7_GDDR5M_unused_2_MASK 0x00000007
-#define BCHP_MEMC_DDR_1_DRAM_MODE_7_GDDR5M_unused_2_SHIFT 0
-#define BCHP_MEMC_DDR_1_DRAM_MODE_7_GDDR5M_unused_2_DEFAULT 0x00000000
-
-/* union - case GDDR5 [12:00] */
-/* MEMC_DDR_1 :: DRAM_MODE_7 :: GDDR5 :: unused_1 [12:12] */
-#define BCHP_MEMC_DDR_1_DRAM_MODE_7_GDDR5_unused_1_MASK 0x00001000
-#define BCHP_MEMC_DDR_1_DRAM_MODE_7_GDDR5_unused_1_SHIFT 12
-#define BCHP_MEMC_DDR_1_DRAM_MODE_7_GDDR5_unused_1_DEFAULT 0x00000000
-
-/* MEMC_DDR_1 :: DRAM_MODE_7 :: GDDR5 :: DDC [11:10] */
-#define BCHP_MEMC_DDR_1_DRAM_MODE_7_GDDR5_DDC_MASK 0x00000c00
-#define BCHP_MEMC_DDR_1_DRAM_MODE_7_GDDR5_DDC_SHIFT 10
-#define BCHP_MEMC_DDR_1_DRAM_MODE_7_GDDR5_DDC_DEFAULT 0x00000000
-
-/* MEMC_DDR_1 :: DRAM_MODE_7 :: GDDR5 :: VDD_RANGE [09:08] */
-#define BCHP_MEMC_DDR_1_DRAM_MODE_7_GDDR5_VDD_RANGE_MASK 0x00000300
-#define BCHP_MEMC_DDR_1_DRAM_MODE_7_GDDR5_VDD_RANGE_SHIFT 8
-#define BCHP_MEMC_DDR_1_DRAM_MODE_7_GDDR5_VDD_RANGE_DEFAULT 0x00000000
-
-/* MEMC_DDR_1 :: DRAM_MODE_7 :: GDDR5 :: HALF_VREFD [07:07] */
-#define BCHP_MEMC_DDR_1_DRAM_MODE_7_GDDR5_HALF_VREFD_MASK 0x00000080
-#define BCHP_MEMC_DDR_1_DRAM_MODE_7_GDDR5_HALF_VREFD_SHIFT 7
-#define BCHP_MEMC_DDR_1_DRAM_MODE_7_GDDR5_HALF_VREFD_DEFAULT 0x00000000
-
-/* MEMC_DDR_1 :: DRAM_MODE_7 :: GDDR5 :: TEMP_SENSE [06:06] */
-#define BCHP_MEMC_DDR_1_DRAM_MODE_7_GDDR5_TEMP_SENSE_MASK 0x00000040
-#define BCHP_MEMC_DDR_1_DRAM_MODE_7_GDDR5_TEMP_SENSE_SHIFT 6
-#define BCHP_MEMC_DDR_1_DRAM_MODE_7_GDDR5_TEMP_SENSE_DEFAULT 0x00000000
-#define BCHP_MEMC_DDR_1_DRAM_MODE_7_GDDR5_TEMP_SENSE_ENABLE 1
-#define BCHP_MEMC_DDR_1_DRAM_MODE_7_GDDR5_TEMP_SENSE_DISABLE 0
-
-/* MEMC_DDR_1 :: DRAM_MODE_7 :: GDDR5 :: DQ_PREAMBLE [05:05] */
-#define BCHP_MEMC_DDR_1_DRAM_MODE_7_GDDR5_DQ_PREAMBLE_MASK 0x00000020
-#define BCHP_MEMC_DDR_1_DRAM_MODE_7_GDDR5_DQ_PREAMBLE_SHIFT 5
-#define BCHP_MEMC_DDR_1_DRAM_MODE_7_GDDR5_DQ_PREAMBLE_DEFAULT 0x00000000
-#define BCHP_MEMC_DDR_1_DRAM_MODE_7_GDDR5_DQ_PREAMBLE_ENABLE 1
-#define BCHP_MEMC_DDR_1_DRAM_MODE_7_GDDR5_DQ_PREAMBLE_DISABLE 0
-
-/* MEMC_DDR_1 :: DRAM_MODE_7 :: GDDR5 :: WCK2CK_AUTO_SYNC [04:04] */
-#define BCHP_MEMC_DDR_1_DRAM_MODE_7_GDDR5_WCK2CK_AUTO_SYNC_MASK 0x00000010
-#define BCHP_MEMC_DDR_1_DRAM_MODE_7_GDDR5_WCK2CK_AUTO_SYNC_SHIFT 4
-#define BCHP_MEMC_DDR_1_DRAM_MODE_7_GDDR5_WCK2CK_AUTO_SYNC_DEFAULT 0x00000000
-#define BCHP_MEMC_DDR_1_DRAM_MODE_7_GDDR5_WCK2CK_AUTO_SYNC_ENABLE 1
-#define BCHP_MEMC_DDR_1_DRAM_MODE_7_GDDR5_WCK2CK_AUTO_SYNC_DISABLE 0
-
-/* MEMC_DDR_1 :: DRAM_MODE_7 :: GDDR5 :: LOW_FREQ [03:03] */
-#define BCHP_MEMC_DDR_1_DRAM_MODE_7_GDDR5_LOW_FREQ_MASK 0x00000008
-#define BCHP_MEMC_DDR_1_DRAM_MODE_7_GDDR5_LOW_FREQ_SHIFT 3
-#define BCHP_MEMC_DDR_1_DRAM_MODE_7_GDDR5_LOW_FREQ_DEFAULT 0x00000000
-#define BCHP_MEMC_DDR_1_DRAM_MODE_7_GDDR5_LOW_FREQ_ENABLE 1
-#define BCHP_MEMC_DDR_1_DRAM_MODE_7_GDDR5_LOW_FREQ_DISABLE 0
-
-/* MEMC_DDR_1 :: DRAM_MODE_7 :: GDDR5 :: PLL_DELAY_COMP [02:02] */
-#define BCHP_MEMC_DDR_1_DRAM_MODE_7_GDDR5_PLL_DELAY_COMP_MASK 0x00000004
-#define BCHP_MEMC_DDR_1_DRAM_MODE_7_GDDR5_PLL_DELAY_COMP_SHIFT 2
-#define BCHP_MEMC_DDR_1_DRAM_MODE_7_GDDR5_PLL_DELAY_COMP_DEFAULT 0x00000000
-#define BCHP_MEMC_DDR_1_DRAM_MODE_7_GDDR5_PLL_DELAY_COMP_ENABLE 1
-#define BCHP_MEMC_DDR_1_DRAM_MODE_7_GDDR5_PLL_DELAY_COMP_DISABLE 0
-
-/* MEMC_DDR_1 :: DRAM_MODE_7 :: GDDR5 :: PLL_FAST_LOCK [01:01] */
-#define BCHP_MEMC_DDR_1_DRAM_MODE_7_GDDR5_PLL_FAST_LOCK_MASK 0x00000002
-#define BCHP_MEMC_DDR_1_DRAM_MODE_7_GDDR5_PLL_FAST_LOCK_SHIFT 1
-#define BCHP_MEMC_DDR_1_DRAM_MODE_7_GDDR5_PLL_FAST_LOCK_DEFAULT 0x00000000
-#define BCHP_MEMC_DDR_1_DRAM_MODE_7_GDDR5_PLL_FAST_LOCK_ENABLE 1
-#define BCHP_MEMC_DDR_1_DRAM_MODE_7_GDDR5_PLL_FAST_LOCK_DISABLE 0
-
-/* MEMC_DDR_1 :: DRAM_MODE_7 :: GDDR5 :: PLL_STANDBY [00:00] */
-#define BCHP_MEMC_DDR_1_DRAM_MODE_7_GDDR5_PLL_STANDBY_MASK 0x00000001
-#define BCHP_MEMC_DDR_1_DRAM_MODE_7_GDDR5_PLL_STANDBY_SHIFT 0
-#define BCHP_MEMC_DDR_1_DRAM_MODE_7_GDDR5_PLL_STANDBY_DEFAULT 0x00000000
-#define BCHP_MEMC_DDR_1_DRAM_MODE_7_GDDR5_PLL_STANDBY_ENABLE 1
-#define BCHP_MEMC_DDR_1_DRAM_MODE_7_GDDR5_PLL_STANDBY_DISABLE 0
-
-/* union - case Others [12:00] */
-/* MEMC_DDR_1 :: DRAM_MODE_7 :: Others :: unused_1 [12:00] */
-#define BCHP_MEMC_DDR_1_DRAM_MODE_7_Others_unused_1_MASK 0x00001fff
-#define BCHP_MEMC_DDR_1_DRAM_MODE_7_Others_unused_1_SHIFT 0
-#define BCHP_MEMC_DDR_1_DRAM_MODE_7_Others_unused_1_DEFAULT 0x00000000
-
-/***************************************************************************
- *DRAM_MODE_8 - Dram Mode Register 8
- ***************************************************************************/
-/* MEMC_DDR_1 :: DRAM_MODE_8 :: reserved0 [31:16] */
-#define BCHP_MEMC_DDR_1_DRAM_MODE_8_reserved0_MASK 0xffff0000
-#define BCHP_MEMC_DDR_1_DRAM_MODE_8_reserved0_SHIFT 16
-
-/* MEMC_DDR_1 :: DRAM_MODE_8 :: unused_0 [15:13] */
-#define BCHP_MEMC_DDR_1_DRAM_MODE_8_unused_0_MASK 0x0000e000
-#define BCHP_MEMC_DDR_1_DRAM_MODE_8_unused_0_SHIFT 13
-#define BCHP_MEMC_DDR_1_DRAM_MODE_8_unused_0_DEFAULT 0x00000000
-
-/* union - case GDDR5 [12:00] */
-/* MEMC_DDR_1 :: DRAM_MODE_8 :: GDDR5 :: unused_1 [12:02] */
-#define BCHP_MEMC_DDR_1_DRAM_MODE_8_GDDR5_unused_1_MASK 0x00001ffc
-#define BCHP_MEMC_DDR_1_DRAM_MODE_8_GDDR5_unused_1_SHIFT 2
-#define BCHP_MEMC_DDR_1_DRAM_MODE_8_GDDR5_unused_1_DEFAULT 0x00000000
-
-/* MEMC_DDR_1 :: DRAM_MODE_8 :: GDDR5 :: WR_EHF [01:01] */
-#define BCHP_MEMC_DDR_1_DRAM_MODE_8_GDDR5_WR_EHF_MASK 0x00000002
-#define BCHP_MEMC_DDR_1_DRAM_MODE_8_GDDR5_WR_EHF_SHIFT 1
-#define BCHP_MEMC_DDR_1_DRAM_MODE_8_GDDR5_WR_EHF_DEFAULT 0x00000000
-
-/* MEMC_DDR_1 :: DRAM_MODE_8 :: GDDR5 :: CL_EHF [00:00] */
-#define BCHP_MEMC_DDR_1_DRAM_MODE_8_GDDR5_CL_EHF_MASK 0x00000001
-#define BCHP_MEMC_DDR_1_DRAM_MODE_8_GDDR5_CL_EHF_SHIFT 0
-#define BCHP_MEMC_DDR_1_DRAM_MODE_8_GDDR5_CL_EHF_DEFAULT 0x00000000
-
-/* union - case Others [12:00] */
-/* MEMC_DDR_1 :: DRAM_MODE_8 :: Others :: unused_1 [12:00] */
-#define BCHP_MEMC_DDR_1_DRAM_MODE_8_Others_unused_1_MASK 0x00001fff
-#define BCHP_MEMC_DDR_1_DRAM_MODE_8_Others_unused_1_SHIFT 0
-#define BCHP_MEMC_DDR_1_DRAM_MODE_8_Others_unused_1_DEFAULT 0x00000000
-
-/***************************************************************************
- *DRAM_MODE_15 - Dram Mode Register 15
- ***************************************************************************/
-/* MEMC_DDR_1 :: DRAM_MODE_15 :: reserved0 [31:16] */
-#define BCHP_MEMC_DDR_1_DRAM_MODE_15_reserved0_MASK 0xffff0000
-#define BCHP_MEMC_DDR_1_DRAM_MODE_15_reserved0_SHIFT 16
-
-/* MEMC_DDR_1 :: DRAM_MODE_15 :: unused_0 [15:13] */
-#define BCHP_MEMC_DDR_1_DRAM_MODE_15_unused_0_MASK 0x0000e000
-#define BCHP_MEMC_DDR_1_DRAM_MODE_15_unused_0_SHIFT 13
-#define BCHP_MEMC_DDR_1_DRAM_MODE_15_unused_0_DEFAULT 0x00000000
-
-/* union - case GDDR5M [12:00] */
-/* MEMC_DDR_1 :: DRAM_MODE_15 :: GDDR5M :: unused_1 [12:12] */
-#define BCHP_MEMC_DDR_1_DRAM_MODE_15_GDDR5M_unused_1_MASK 0x00001000
-#define BCHP_MEMC_DDR_1_DRAM_MODE_15_GDDR5M_unused_1_SHIFT 12
-#define BCHP_MEMC_DDR_1_DRAM_MODE_15_GDDR5M_unused_1_DEFAULT 0x00000000
-
-/* MEMC_DDR_1 :: DRAM_MODE_15 :: GDDR5M :: ADDR_TRAINING [11:10] */
-#define BCHP_MEMC_DDR_1_DRAM_MODE_15_GDDR5M_ADDR_TRAINING_MASK 0x00000c00
-#define BCHP_MEMC_DDR_1_DRAM_MODE_15_GDDR5M_ADDR_TRAINING_SHIFT 10
-#define BCHP_MEMC_DDR_1_DRAM_MODE_15_GDDR5M_ADDR_TRAINING_DEFAULT 0x00000000
-
-/* MEMC_DDR_1 :: DRAM_MODE_15 :: GDDR5M :: MRE_MF1 [09:09] */
-#define BCHP_MEMC_DDR_1_DRAM_MODE_15_GDDR5M_MRE_MF1_MASK 0x00000200
-#define BCHP_MEMC_DDR_1_DRAM_MODE_15_GDDR5M_MRE_MF1_SHIFT 9
-#define BCHP_MEMC_DDR_1_DRAM_MODE_15_GDDR5M_MRE_MF1_DEFAULT 0x00000000
-#define BCHP_MEMC_DDR_1_DRAM_MODE_15_GDDR5M_MRE_MF1_ENABLE 0
-#define BCHP_MEMC_DDR_1_DRAM_MODE_15_GDDR5M_MRE_MF1_DISABLE 1
-
-/* MEMC_DDR_1 :: DRAM_MODE_15 :: GDDR5M :: MRE_MF2 [08:08] */
-#define BCHP_MEMC_DDR_1_DRAM_MODE_15_GDDR5M_MRE_MF2_MASK 0x00000100
-#define BCHP_MEMC_DDR_1_DRAM_MODE_15_GDDR5M_MRE_MF2_SHIFT 8
-#define BCHP_MEMC_DDR_1_DRAM_MODE_15_GDDR5M_MRE_MF2_DEFAULT 0x00000000
-#define BCHP_MEMC_DDR_1_DRAM_MODE_15_GDDR5M_MRE_MF2_ENABLE 0
-#define BCHP_MEMC_DDR_1_DRAM_MODE_15_GDDR5M_MRE_MF2_DISABLE 1
-
-/* MEMC_DDR_1 :: DRAM_MODE_15 :: GDDR5M :: unused_2 [07:00] */
-#define BCHP_MEMC_DDR_1_DRAM_MODE_15_GDDR5M_unused_2_MASK 0x000000ff
-#define BCHP_MEMC_DDR_1_DRAM_MODE_15_GDDR5M_unused_2_SHIFT 0
-#define BCHP_MEMC_DDR_1_DRAM_MODE_15_GDDR5M_unused_2_DEFAULT 0x00000000
-
-/* union - case GDDR5 [12:00] */
-/* MEMC_DDR_1 :: DRAM_MODE_15 :: GDDR5 :: unused_1 [12:11] */
-#define BCHP_MEMC_DDR_1_DRAM_MODE_15_GDDR5_unused_1_MASK 0x00001800
-#define BCHP_MEMC_DDR_1_DRAM_MODE_15_GDDR5_unused_1_SHIFT 11
-#define BCHP_MEMC_DDR_1_DRAM_MODE_15_GDDR5_unused_1_DEFAULT 0x00000000
-
-/* MEMC_DDR_1 :: DRAM_MODE_15 :: GDDR5 :: ADDR_TRAINING [10:10] */
-#define BCHP_MEMC_DDR_1_DRAM_MODE_15_GDDR5_ADDR_TRAINING_MASK 0x00000400
-#define BCHP_MEMC_DDR_1_DRAM_MODE_15_GDDR5_ADDR_TRAINING_SHIFT 10
-#define BCHP_MEMC_DDR_1_DRAM_MODE_15_GDDR5_ADDR_TRAINING_DEFAULT 0x00000000
-#define BCHP_MEMC_DDR_1_DRAM_MODE_15_GDDR5_ADDR_TRAINING_ENABLE 1
-#define BCHP_MEMC_DDR_1_DRAM_MODE_15_GDDR5_ADDR_TRAINING_DISABLE 0
-
-/* MEMC_DDR_1 :: DRAM_MODE_15 :: GDDR5 :: MRE_MF1 [09:09] */
-#define BCHP_MEMC_DDR_1_DRAM_MODE_15_GDDR5_MRE_MF1_MASK 0x00000200
-#define BCHP_MEMC_DDR_1_DRAM_MODE_15_GDDR5_MRE_MF1_SHIFT 9
-#define BCHP_MEMC_DDR_1_DRAM_MODE_15_GDDR5_MRE_MF1_DEFAULT 0x00000000
-#define BCHP_MEMC_DDR_1_DRAM_MODE_15_GDDR5_MRE_MF1_ENABLE 0
-#define BCHP_MEMC_DDR_1_DRAM_MODE_15_GDDR5_MRE_MF1_DISABLE 1
-
-/* MEMC_DDR_1 :: DRAM_MODE_15 :: GDDR5 :: MRE_MF2 [08:08] */
-#define BCHP_MEMC_DDR_1_DRAM_MODE_15_GDDR5_MRE_MF2_MASK 0x00000100
-#define BCHP_MEMC_DDR_1_DRAM_MODE_15_GDDR5_MRE_MF2_SHIFT 8
-#define BCHP_MEMC_DDR_1_DRAM_MODE_15_GDDR5_MRE_MF2_DEFAULT 0x00000000
-#define BCHP_MEMC_DDR_1_DRAM_MODE_15_GDDR5_MRE_MF2_ENABLE 0
-#define BCHP_MEMC_DDR_1_DRAM_MODE_15_GDDR5_MRE_MF2_DISABLE 1
-
-/* MEMC_DDR_1 :: DRAM_MODE_15 :: GDDR5 :: unused_2 [07:00] */
-#define BCHP_MEMC_DDR_1_DRAM_MODE_15_GDDR5_unused_2_MASK 0x000000ff
-#define BCHP_MEMC_DDR_1_DRAM_MODE_15_GDDR5_unused_2_SHIFT 0
-#define BCHP_MEMC_DDR_1_DRAM_MODE_15_GDDR5_unused_2_DEFAULT 0x00000000
-
-/* union - case Others [12:00] */
-/* MEMC_DDR_1 :: DRAM_MODE_15 :: Others :: unused_1 [12:00] */
-#define BCHP_MEMC_DDR_1_DRAM_MODE_15_Others_unused_1_MASK 0x00001fff
-#define BCHP_MEMC_DDR_1_DRAM_MODE_15_Others_unused_1_SHIFT 0
-#define BCHP_MEMC_DDR_1_DRAM_MODE_15_Others_unused_1_DEFAULT 0x00000000
-
-/***************************************************************************
- *PPD_CONFIG - Precharge power down mode configuration register
- ***************************************************************************/
-/* MEMC_DDR_1 :: PPD_CONFIG :: reserved0 [31:15] */
-#define BCHP_MEMC_DDR_1_PPD_CONFIG_reserved0_MASK 0xffff8000
-#define BCHP_MEMC_DDR_1_PPD_CONFIG_reserved0_SHIFT 15
-
-/* MEMC_DDR_1 :: PPD_CONFIG :: FORCE_PPD_EXIT [14:14] */
-#define BCHP_MEMC_DDR_1_PPD_CONFIG_FORCE_PPD_EXIT_MASK 0x00004000
-#define BCHP_MEMC_DDR_1_PPD_CONFIG_FORCE_PPD_EXIT_SHIFT 14
-#define BCHP_MEMC_DDR_1_PPD_CONFIG_FORCE_PPD_EXIT_DEFAULT 0x00000000
-
-/* MEMC_DDR_1 :: PPD_CONFIG :: PPD_FORCE [13:13] */
-#define BCHP_MEMC_DDR_1_PPD_CONFIG_PPD_FORCE_MASK 0x00002000
-#define BCHP_MEMC_DDR_1_PPD_CONFIG_PPD_FORCE_SHIFT 13
-#define BCHP_MEMC_DDR_1_PPD_CONFIG_PPD_FORCE_DEFAULT 0x00000000
-
-/* MEMC_DDR_1 :: PPD_CONFIG :: PPD_EN [12:12] */
-#define BCHP_MEMC_DDR_1_PPD_CONFIG_PPD_EN_MASK 0x00001000
-#define BCHP_MEMC_DDR_1_PPD_CONFIG_PPD_EN_SHIFT 12
-#define BCHP_MEMC_DDR_1_PPD_CONFIG_PPD_EN_DEFAULT 0x00000000
-
-/* MEMC_DDR_1 :: PPD_CONFIG :: INACT_COUNT [11:00] */
-#define BCHP_MEMC_DDR_1_PPD_CONFIG_INACT_COUNT_MASK 0x00000fff
-#define BCHP_MEMC_DDR_1_PPD_CONFIG_INACT_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_1_PPD_CONFIG_INACT_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *SRPD_CONFIG - Self-refresh power down mode configuration register
- ***************************************************************************/
-/* MEMC_DDR_1 :: SRPD_CONFIG :: reserved0 [31:18] */
-#define BCHP_MEMC_DDR_1_SRPD_CONFIG_reserved0_MASK 0xfffc0000
-#define BCHP_MEMC_DDR_1_SRPD_CONFIG_reserved0_SHIFT 18
-
-/* MEMC_DDR_1 :: SRPD_CONFIG :: FORCE_SRPD_EXIT [17:17] */
-#define BCHP_MEMC_DDR_1_SRPD_CONFIG_FORCE_SRPD_EXIT_MASK 0x00020000
-#define BCHP_MEMC_DDR_1_SRPD_CONFIG_FORCE_SRPD_EXIT_SHIFT 17
-#define BCHP_MEMC_DDR_1_SRPD_CONFIG_FORCE_SRPD_EXIT_DEFAULT 0x00000000
-
-/* MEMC_DDR_1 :: SRPD_CONFIG :: SRPD_EN [16:16] */
-#define BCHP_MEMC_DDR_1_SRPD_CONFIG_SRPD_EN_MASK 0x00010000
-#define BCHP_MEMC_DDR_1_SRPD_CONFIG_SRPD_EN_SHIFT 16
-#define BCHP_MEMC_DDR_1_SRPD_CONFIG_SRPD_EN_DEFAULT 0x00000000
-
-/* MEMC_DDR_1 :: SRPD_CONFIG :: INACT_COUNT [15:00] */
-#define BCHP_MEMC_DDR_1_SRPD_CONFIG_INACT_COUNT_MASK 0x0000ffff
-#define BCHP_MEMC_DDR_1_SRPD_CONFIG_INACT_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_1_SRPD_CONFIG_INACT_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *SSPD_CMD - Software standby power down mode
- ***************************************************************************/
-/* MEMC_DDR_1 :: SSPD_CMD :: reserved0 [31:01] */
-#define BCHP_MEMC_DDR_1_SSPD_CMD_reserved0_MASK 0xfffffffe
-#define BCHP_MEMC_DDR_1_SSPD_CMD_reserved0_SHIFT 1
-
-/* MEMC_DDR_1 :: SSPD_CMD :: SSPD [00:00] */
-#define BCHP_MEMC_DDR_1_SSPD_CMD_SSPD_MASK 0x00000001
-#define BCHP_MEMC_DDR_1_SSPD_CMD_SSPD_SHIFT 0
-#define BCHP_MEMC_DDR_1_SSPD_CMD_SSPD_DEFAULT 0x00000000
-
-/***************************************************************************
- *POWER_DOWN_STATUS - Power down status
- ***************************************************************************/
-/* MEMC_DDR_1 :: POWER_DOWN_STATUS :: reserved0 [31:03] */
-#define BCHP_MEMC_DDR_1_POWER_DOWN_STATUS_reserved0_MASK 0xfffffff8
-#define BCHP_MEMC_DDR_1_POWER_DOWN_STATUS_reserved0_SHIFT 3
-
-/* MEMC_DDR_1 :: POWER_DOWN_STATUS :: SSPD [02:02] */
-#define BCHP_MEMC_DDR_1_POWER_DOWN_STATUS_SSPD_MASK 0x00000004
-#define BCHP_MEMC_DDR_1_POWER_DOWN_STATUS_SSPD_SHIFT 2
-#define BCHP_MEMC_DDR_1_POWER_DOWN_STATUS_SSPD_DEFAULT 0x00000000
-
-/* MEMC_DDR_1 :: POWER_DOWN_STATUS :: SRPD [01:01] */
-#define BCHP_MEMC_DDR_1_POWER_DOWN_STATUS_SRPD_MASK 0x00000002
-#define BCHP_MEMC_DDR_1_POWER_DOWN_STATUS_SRPD_SHIFT 1
-#define BCHP_MEMC_DDR_1_POWER_DOWN_STATUS_SRPD_DEFAULT 0x00000000
-
-/* MEMC_DDR_1 :: POWER_DOWN_STATUS :: PPD [00:00] */
-#define BCHP_MEMC_DDR_1_POWER_DOWN_STATUS_PPD_MASK 0x00000001
-#define BCHP_MEMC_DDR_1_POWER_DOWN_STATUS_PPD_SHIFT 0
-#define BCHP_MEMC_DDR_1_POWER_DOWN_STATUS_PPD_DEFAULT 0x00000000
-
-/***************************************************************************
- *WARM_BOOT - Warm boot control registers
- ***************************************************************************/
-/* MEMC_DDR_1 :: WARM_BOOT :: reserved0 [31:01] */
-#define BCHP_MEMC_DDR_1_WARM_BOOT_reserved0_MASK 0xfffffffe
-#define BCHP_MEMC_DDR_1_WARM_BOOT_reserved0_SHIFT 1
-
-/* MEMC_DDR_1 :: WARM_BOOT :: WARM_BOOT [00:00] */
-#define BCHP_MEMC_DDR_1_WARM_BOOT_WARM_BOOT_MASK 0x00000001
-#define BCHP_MEMC_DDR_1_WARM_BOOT_WARM_BOOT_SHIFT 0
-#define BCHP_MEMC_DDR_1_WARM_BOOT_WARM_BOOT_DEFAULT 0x00000000
-
-/***************************************************************************
- *DRAM_TIMING_0 - DDR-SDRAM Timing Register 0
- ***************************************************************************/
-/* MEMC_DDR_1 :: DRAM_TIMING_0 :: TRRD_NOP [31:24] */
-#define BCHP_MEMC_DDR_1_DRAM_TIMING_0_TRRD_NOP_MASK 0xff000000
-#define BCHP_MEMC_DDR_1_DRAM_TIMING_0_TRRD_NOP_SHIFT 24
-#define BCHP_MEMC_DDR_1_DRAM_TIMING_0_TRRD_NOP_DEFAULT 0x00000006
-
-/* MEMC_DDR_1 :: DRAM_TIMING_0 :: TRCD_NOP [23:16] */
-#define BCHP_MEMC_DDR_1_DRAM_TIMING_0_TRCD_NOP_MASK 0x00ff0000
-#define BCHP_MEMC_DDR_1_DRAM_TIMING_0_TRCD_NOP_SHIFT 16
-#define BCHP_MEMC_DDR_1_DRAM_TIMING_0_TRCD_NOP_DEFAULT 0x00000008
-
-/* MEMC_DDR_1 :: DRAM_TIMING_0 :: TRP_NOP [15:08] */
-#define BCHP_MEMC_DDR_1_DRAM_TIMING_0_TRP_NOP_MASK 0x0000ff00
-#define BCHP_MEMC_DDR_1_DRAM_TIMING_0_TRP_NOP_SHIFT 8
-#define BCHP_MEMC_DDR_1_DRAM_TIMING_0_TRP_NOP_DEFAULT 0x00000008
-
-/* MEMC_DDR_1 :: DRAM_TIMING_0 :: TRAS_NOP [07:00] */
-#define BCHP_MEMC_DDR_1_DRAM_TIMING_0_TRAS_NOP_MASK 0x000000ff
-#define BCHP_MEMC_DDR_1_DRAM_TIMING_0_TRAS_NOP_SHIFT 0
-#define BCHP_MEMC_DDR_1_DRAM_TIMING_0_TRAS_NOP_DEFAULT 0x00000014
-
-/***************************************************************************
- *DRAM_TIMING_1 - DDR-SDRAM Timing Register 1
- ***************************************************************************/
-/* MEMC_DDR_1 :: DRAM_TIMING_1 :: reserved0 [31:28] */
-#define BCHP_MEMC_DDR_1_DRAM_TIMING_1_reserved0_MASK 0xf0000000
-#define BCHP_MEMC_DDR_1_DRAM_TIMING_1_reserved0_SHIFT 28
-
-/* MEMC_DDR_1 :: DRAM_TIMING_1 :: T32AW_NOP [27:16] */
-#define BCHP_MEMC_DDR_1_DRAM_TIMING_1_T32AW_NOP_MASK 0x0fff0000
-#define BCHP_MEMC_DDR_1_DRAM_TIMING_1_T32AW_NOP_SHIFT 16
-#define BCHP_MEMC_DDR_1_DRAM_TIMING_1_T32AW_NOP_DEFAULT 0x00000020
-
-/* MEMC_DDR_1 :: DRAM_TIMING_1 :: TFAW_NOP [15:08] */
-#define BCHP_MEMC_DDR_1_DRAM_TIMING_1_TFAW_NOP_MASK 0x0000ff00
-#define BCHP_MEMC_DDR_1_DRAM_TIMING_1_TFAW_NOP_SHIFT 8
-#define BCHP_MEMC_DDR_1_DRAM_TIMING_1_TFAW_NOP_DEFAULT 0x0000001b
-
-/* MEMC_DDR_1 :: DRAM_TIMING_1 :: TRTP_NOP [07:00] */
-#define BCHP_MEMC_DDR_1_DRAM_TIMING_1_TRTP_NOP_MASK 0x000000ff
-#define BCHP_MEMC_DDR_1_DRAM_TIMING_1_TRTP_NOP_SHIFT 0
-#define BCHP_MEMC_DDR_1_DRAM_TIMING_1_TRTP_NOP_DEFAULT 0x00000004
-
-/***************************************************************************
- *DRAM_TIMING_2 - Read to Write & write to read timing register
- ***************************************************************************/
-/* MEMC_DDR_1 :: DRAM_TIMING_2 :: TRRDL_NOP [31:24] */
-#define BCHP_MEMC_DDR_1_DRAM_TIMING_2_TRRDL_NOP_MASK 0xff000000
-#define BCHP_MEMC_DDR_1_DRAM_TIMING_2_TRRDL_NOP_SHIFT 24
-#define BCHP_MEMC_DDR_1_DRAM_TIMING_2_TRRDL_NOP_DEFAULT 0x00000006
-
-/* MEMC_DDR_1 :: DRAM_TIMING_2 :: WR2RDL_NOP [23:16] */
-#define BCHP_MEMC_DDR_1_DRAM_TIMING_2_WR2RDL_NOP_MASK 0x00ff0000
-#define BCHP_MEMC_DDR_1_DRAM_TIMING_2_WR2RDL_NOP_SHIFT 16
-#define BCHP_MEMC_DDR_1_DRAM_TIMING_2_WR2RDL_NOP_DEFAULT 0x0000000e
-
-/* MEMC_DDR_1 :: DRAM_TIMING_2 :: WR2RD_NOP [15:08] */
-#define BCHP_MEMC_DDR_1_DRAM_TIMING_2_WR2RD_NOP_MASK 0x0000ff00
-#define BCHP_MEMC_DDR_1_DRAM_TIMING_2_WR2RD_NOP_SHIFT 8
-#define BCHP_MEMC_DDR_1_DRAM_TIMING_2_WR2RD_NOP_DEFAULT 0x0000000e
-
-/* MEMC_DDR_1 :: DRAM_TIMING_2 :: RD2WR_NOP [07:00] */
-#define BCHP_MEMC_DDR_1_DRAM_TIMING_2_RD2WR_NOP_MASK 0x000000ff
-#define BCHP_MEMC_DDR_1_DRAM_TIMING_2_RD2WR_NOP_SHIFT 0
-#define BCHP_MEMC_DDR_1_DRAM_TIMING_2_RD2WR_NOP_DEFAULT 0x00000009
-
-/***************************************************************************
- *DRAM_TIMING_3 - DDR-SDRAM Timing Register 3
- ***************************************************************************/
-/* MEMC_DDR_1 :: DRAM_TIMING_3 :: reserved0 [31:24] */
-#define BCHP_MEMC_DDR_1_DRAM_TIMING_3_reserved0_MASK 0xff000000
-#define BCHP_MEMC_DDR_1_DRAM_TIMING_3_reserved0_SHIFT 24
-
-/* MEMC_DDR_1 :: DRAM_TIMING_3 :: CKENB_CKE_DELAY [23:19] */
-#define BCHP_MEMC_DDR_1_DRAM_TIMING_3_CKENB_CKE_DELAY_MASK 0x00f80000
-#define BCHP_MEMC_DDR_1_DRAM_TIMING_3_CKENB_CKE_DELAY_SHIFT 19
-#define BCHP_MEMC_DDR_1_DRAM_TIMING_3_CKENB_CKE_DELAY_DEFAULT 0x0000000c
-
-/* MEMC_DDR_1 :: DRAM_TIMING_3 :: POWERUP_CKE_DELAY [18:10] */
-#define BCHP_MEMC_DDR_1_DRAM_TIMING_3_POWERUP_CKE_DELAY_MASK 0x0007fc00
-#define BCHP_MEMC_DDR_1_DRAM_TIMING_3_POWERUP_CKE_DELAY_SHIFT 10
-#define BCHP_MEMC_DDR_1_DRAM_TIMING_3_POWERUP_CKE_DELAY_DEFAULT 0x0000005e
-
-/* MEMC_DDR_1 :: DRAM_TIMING_3 :: DLL_LOCK_DELAY [09:00] */
-#define BCHP_MEMC_DDR_1_DRAM_TIMING_3_DLL_LOCK_DELAY_MASK 0x000003ff
-#define BCHP_MEMC_DDR_1_DRAM_TIMING_3_DLL_LOCK_DELAY_SHIFT 0
-#define BCHP_MEMC_DDR_1_DRAM_TIMING_3_DLL_LOCK_DELAY_DEFAULT 0x00000200
-
-/***************************************************************************
- *DRAM_TIMING_4 - DDR-SDRAM Timing Register 4
- ***************************************************************************/
-/* MEMC_DDR_1 :: DRAM_TIMING_4 :: reserved0 [31:29] */
-#define BCHP_MEMC_DDR_1_DRAM_TIMING_4_reserved0_MASK 0xe0000000
-#define BCHP_MEMC_DDR_1_DRAM_TIMING_4_reserved0_SHIFT 29
-
-/* MEMC_DDR_1 :: DRAM_TIMING_4 :: PRECHARGE_ALL_DELAY [28:24] */
-#define BCHP_MEMC_DDR_1_DRAM_TIMING_4_PRECHARGE_ALL_DELAY_MASK 0x1f000000
-#define BCHP_MEMC_DDR_1_DRAM_TIMING_4_PRECHARGE_ALL_DELAY_SHIFT 24
-#define BCHP_MEMC_DDR_1_DRAM_TIMING_4_PRECHARGE_ALL_DELAY_DEFAULT 0x00000008
-
-/* MEMC_DDR_1 :: DRAM_TIMING_4 :: LOAD_MODE_DELAY [23:19] */
-#define BCHP_MEMC_DDR_1_DRAM_TIMING_4_LOAD_MODE_DELAY_MASK 0x00f80000
-#define BCHP_MEMC_DDR_1_DRAM_TIMING_4_LOAD_MODE_DELAY_SHIFT 19
-#define BCHP_MEMC_DDR_1_DRAM_TIMING_4_LOAD_MODE_DELAY_DEFAULT 0x0000000c
-
-/* MEMC_DDR_1 :: DRAM_TIMING_4 :: REFRESH_DELAY [18:10] */
-#define BCHP_MEMC_DDR_1_DRAM_TIMING_4_REFRESH_DELAY_MASK 0x0007fc00
-#define BCHP_MEMC_DDR_1_DRAM_TIMING_4_REFRESH_DELAY_SHIFT 10
-#define BCHP_MEMC_DDR_1_DRAM_TIMING_4_REFRESH_DELAY_DEFAULT 0x00000058
-
-/* MEMC_DDR_1 :: DRAM_TIMING_4 :: ZQCALIB_DELAY [09:00] */
-#define BCHP_MEMC_DDR_1_DRAM_TIMING_4_ZQCALIB_DELAY_MASK 0x000003ff
-#define BCHP_MEMC_DDR_1_DRAM_TIMING_4_ZQCALIB_DELAY_SHIFT 0
-#define BCHP_MEMC_DDR_1_DRAM_TIMING_4_ZQCALIB_DELAY_DEFAULT 0x00000200
-
-/***************************************************************************
- *DRAM_TIMING_5 - DDR-SDRAM Timing Register 5
- ***************************************************************************/
-/* MEMC_DDR_1 :: DRAM_TIMING_5 :: reserved0 [31:29] */
-#define BCHP_MEMC_DDR_1_DRAM_TIMING_5_reserved0_MASK 0xe0000000
-#define BCHP_MEMC_DDR_1_DRAM_TIMING_5_reserved0_SHIFT 29
-
-/* MEMC_DDR_1 :: DRAM_TIMING_5 :: CKE_ASSETION_DELAY [28:19] */
-#define BCHP_MEMC_DDR_1_DRAM_TIMING_5_CKE_ASSETION_DELAY_MASK 0x1ff80000
-#define BCHP_MEMC_DDR_1_DRAM_TIMING_5_CKE_ASSETION_DELAY_SHIFT 19
-#define BCHP_MEMC_DDR_1_DRAM_TIMING_5_CKE_ASSETION_DELAY_DEFAULT 0x00000105
-
-/* MEMC_DDR_1 :: DRAM_TIMING_5 :: CKE_MIN_WIDTH [18:15] */
-#define BCHP_MEMC_DDR_1_DRAM_TIMING_5_CKE_MIN_WIDTH_MASK 0x00078000
-#define BCHP_MEMC_DDR_1_DRAM_TIMING_5_CKE_MIN_WIDTH_SHIFT 15
-#define BCHP_MEMC_DDR_1_DRAM_TIMING_5_CKE_MIN_WIDTH_DEFAULT 0x00000003
-
-/* MEMC_DDR_1 :: DRAM_TIMING_5 :: PWDN_EXIT_DELAY [14:10] */
-#define BCHP_MEMC_DDR_1_DRAM_TIMING_5_PWDN_EXIT_DELAY_MASK 0x00007c00
-#define BCHP_MEMC_DDR_1_DRAM_TIMING_5_PWDN_EXIT_DELAY_SHIFT 10
-#define BCHP_MEMC_DDR_1_DRAM_TIMING_5_PWDN_EXIT_DELAY_DEFAULT 0x0000000d
-
-/* MEMC_DDR_1 :: DRAM_TIMING_5 :: SELFREF_EXIT_DELAY [09:00] */
-#define BCHP_MEMC_DDR_1_DRAM_TIMING_5_SELFREF_EXIT_DELAY_MASK 0x000003ff
-#define BCHP_MEMC_DDR_1_DRAM_TIMING_5_SELFREF_EXIT_DELAY_SHIFT 0
-#define BCHP_MEMC_DDR_1_DRAM_TIMING_5_SELFREF_EXIT_DELAY_DEFAULT 0x00000200
-
-/***************************************************************************
- *MIN_DQ_IDLE_CONTROL - Minimum DQ Idle Time Control
- ***************************************************************************/
-/* MEMC_DDR_1 :: MIN_DQ_IDLE_CONTROL :: reserved0 [31:23] */
-#define BCHP_MEMC_DDR_1_MIN_DQ_IDLE_CONTROL_reserved0_MASK 0xff800000
-#define BCHP_MEMC_DDR_1_MIN_DQ_IDLE_CONTROL_reserved0_SHIFT 23
-
-/* MEMC_DDR_1 :: MIN_DQ_IDLE_CONTROL :: WriteDelay [22:20] */
-#define BCHP_MEMC_DDR_1_MIN_DQ_IDLE_CONTROL_WriteDelay_MASK 0x00700000
-#define BCHP_MEMC_DDR_1_MIN_DQ_IDLE_CONTROL_WriteDelay_SHIFT 20
-#define BCHP_MEMC_DDR_1_MIN_DQ_IDLE_CONTROL_WriteDelay_DEFAULT 0x00000000
-
-/* MEMC_DDR_1 :: MIN_DQ_IDLE_CONTROL :: reserved1 [19:18] */
-#define BCHP_MEMC_DDR_1_MIN_DQ_IDLE_CONTROL_reserved1_MASK 0x000c0000
-#define BCHP_MEMC_DDR_1_MIN_DQ_IDLE_CONTROL_reserved1_SHIFT 18
-
-/* MEMC_DDR_1 :: MIN_DQ_IDLE_CONTROL :: WriteForceIdle [17:17] */
-#define BCHP_MEMC_DDR_1_MIN_DQ_IDLE_CONTROL_WriteForceIdle_MASK 0x00020000
-#define BCHP_MEMC_DDR_1_MIN_DQ_IDLE_CONTROL_WriteForceIdle_SHIFT 17
-#define BCHP_MEMC_DDR_1_MIN_DQ_IDLE_CONTROL_WriteForceIdle_DEFAULT 0x00000000
-
-/* MEMC_DDR_1 :: MIN_DQ_IDLE_CONTROL :: WriteEnable [16:16] */
-#define BCHP_MEMC_DDR_1_MIN_DQ_IDLE_CONTROL_WriteEnable_MASK 0x00010000
-#define BCHP_MEMC_DDR_1_MIN_DQ_IDLE_CONTROL_WriteEnable_SHIFT 16
-#define BCHP_MEMC_DDR_1_MIN_DQ_IDLE_CONTROL_WriteEnable_DEFAULT 0x00000000
-
-/* MEMC_DDR_1 :: MIN_DQ_IDLE_CONTROL :: reserved2 [15:07] */
-#define BCHP_MEMC_DDR_1_MIN_DQ_IDLE_CONTROL_reserved2_MASK 0x0000ff80
-#define BCHP_MEMC_DDR_1_MIN_DQ_IDLE_CONTROL_reserved2_SHIFT 7
-
-/* MEMC_DDR_1 :: MIN_DQ_IDLE_CONTROL :: ReadDelay [06:04] */
-#define BCHP_MEMC_DDR_1_MIN_DQ_IDLE_CONTROL_ReadDelay_MASK 0x00000070
-#define BCHP_MEMC_DDR_1_MIN_DQ_IDLE_CONTROL_ReadDelay_SHIFT 4
-#define BCHP_MEMC_DDR_1_MIN_DQ_IDLE_CONTROL_ReadDelay_DEFAULT 0x00000000
-
-/* MEMC_DDR_1 :: MIN_DQ_IDLE_CONTROL :: reserved3 [03:02] */
-#define BCHP_MEMC_DDR_1_MIN_DQ_IDLE_CONTROL_reserved3_MASK 0x0000000c
-#define BCHP_MEMC_DDR_1_MIN_DQ_IDLE_CONTROL_reserved3_SHIFT 2
-
-/* MEMC_DDR_1 :: MIN_DQ_IDLE_CONTROL :: ReadForceIdle [01:01] */
-#define BCHP_MEMC_DDR_1_MIN_DQ_IDLE_CONTROL_ReadForceIdle_MASK 0x00000002
-#define BCHP_MEMC_DDR_1_MIN_DQ_IDLE_CONTROL_ReadForceIdle_SHIFT 1
-#define BCHP_MEMC_DDR_1_MIN_DQ_IDLE_CONTROL_ReadForceIdle_DEFAULT 0x00000000
-
-/* MEMC_DDR_1 :: MIN_DQ_IDLE_CONTROL :: ReadEnable [00:00] */
-#define BCHP_MEMC_DDR_1_MIN_DQ_IDLE_CONTROL_ReadEnable_MASK 0x00000001
-#define BCHP_MEMC_DDR_1_MIN_DQ_IDLE_CONTROL_ReadEnable_SHIFT 0
-#define BCHP_MEMC_DDR_1_MIN_DQ_IDLE_CONTROL_ReadEnable_DEFAULT 0x00000000
-
-/***************************************************************************
- *PHY_OP_ACCESS_PENALTY - PHY Operational Access Penalty Count.
- ***************************************************************************/
-/* MEMC_DDR_1 :: PHY_OP_ACCESS_PENALTY :: PHY_OP_ACCESS_WAIT_PENALTY [31:00] */
-#define BCHP_MEMC_DDR_1_PHY_OP_ACCESS_PENALTY_PHY_OP_ACCESS_WAIT_PENALTY_MASK 0xffffffff
-#define BCHP_MEMC_DDR_1_PHY_OP_ACCESS_PENALTY_PHY_OP_ACCESS_WAIT_PENALTY_SHIFT 0
-#define BCHP_MEMC_DDR_1_PHY_OP_ACCESS_PENALTY_PHY_OP_ACCESS_WAIT_PENALTY_DEFAULT 0x00000000
-
-/***************************************************************************
- *CNTRLR_SM_TIMEOUT - Memory Controller , state machine timeout register.
- ***************************************************************************/
-/* MEMC_DDR_1 :: CNTRLR_SM_TIMEOUT :: reserved0 [31:17] */
-#define BCHP_MEMC_DDR_1_CNTRLR_SM_TIMEOUT_reserved0_MASK 0xfffe0000
-#define BCHP_MEMC_DDR_1_CNTRLR_SM_TIMEOUT_reserved0_SHIFT 17
-
-/* MEMC_DDR_1 :: CNTRLR_SM_TIMEOUT :: ENABLE [16:16] */
-#define BCHP_MEMC_DDR_1_CNTRLR_SM_TIMEOUT_ENABLE_MASK 0x00010000
-#define BCHP_MEMC_DDR_1_CNTRLR_SM_TIMEOUT_ENABLE_SHIFT 16
-#define BCHP_MEMC_DDR_1_CNTRLR_SM_TIMEOUT_ENABLE_DEFAULT 0x00000000
-
-/* MEMC_DDR_1 :: CNTRLR_SM_TIMEOUT :: COUNT [15:00] */
-#define BCHP_MEMC_DDR_1_CNTRLR_SM_TIMEOUT_COUNT_MASK 0x0000ffff
-#define BCHP_MEMC_DDR_1_CNTRLR_SM_TIMEOUT_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_1_CNTRLR_SM_TIMEOUT_COUNT_DEFAULT 0x0000ffff
-
-/***************************************************************************
- *BANK_STATUS - Memory Controller, Bank Status Register
- ***************************************************************************/
-/* MEMC_DDR_1 :: BANK_STATUS :: reserved0 [31:16] */
-#define BCHP_MEMC_DDR_1_BANK_STATUS_reserved0_MASK 0xffff0000
-#define BCHP_MEMC_DDR_1_BANK_STATUS_reserved0_SHIFT 16
-
-/* MEMC_DDR_1 :: BANK_STATUS :: BANK_STATUS [15:00] */
-#define BCHP_MEMC_DDR_1_BANK_STATUS_BANK_STATUS_MASK 0x0000ffff
-#define BCHP_MEMC_DDR_1_BANK_STATUS_BANK_STATUS_SHIFT 0
-#define BCHP_MEMC_DDR_1_BANK_STATUS_BANK_STATUS_DEFAULT 0x0000ffff
-
-/***************************************************************************
- *TESTER_LATENCY - Memory Controller, Tester Latency Register.
- ***************************************************************************/
-/* MEMC_DDR_1 :: TESTER_LATENCY :: reserved0 [31:08] */
-#define BCHP_MEMC_DDR_1_TESTER_LATENCY_reserved0_MASK 0xffffff00
-#define BCHP_MEMC_DDR_1_TESTER_LATENCY_reserved0_SHIFT 8
-
-/* MEMC_DDR_1 :: TESTER_LATENCY :: TLATENCY_SEL [07:00] */
-#define BCHP_MEMC_DDR_1_TESTER_LATENCY_TLATENCY_SEL_MASK 0x000000ff
-#define BCHP_MEMC_DDR_1_TESTER_LATENCY_TLATENCY_SEL_SHIFT 0
-#define BCHP_MEMC_DDR_1_TESTER_LATENCY_TLATENCY_SEL_DEFAULT 0x00000000
-
-/***************************************************************************
- *SEQ_RING_BUF_DEPTH - Sequencer Ring Buffer programmable depth.
- ***************************************************************************/
-/* MEMC_DDR_1 :: SEQ_RING_BUF_DEPTH :: reserved0 [31:05] */
-#define BCHP_MEMC_DDR_1_SEQ_RING_BUF_DEPTH_reserved0_MASK 0xffffffe0
-#define BCHP_MEMC_DDR_1_SEQ_RING_BUF_DEPTH_reserved0_SHIFT 5
-
-/* MEMC_DDR_1 :: SEQ_RING_BUF_DEPTH :: RING_BUF_DEPTH [04:00] */
-#define BCHP_MEMC_DDR_1_SEQ_RING_BUF_DEPTH_RING_BUF_DEPTH_MASK 0x0000001f
-#define BCHP_MEMC_DDR_1_SEQ_RING_BUF_DEPTH_RING_BUF_DEPTH_SHIFT 0
-#define BCHP_MEMC_DDR_1_SEQ_RING_BUF_DEPTH_RING_BUF_DEPTH_DEFAULT 0x0000000f
-
-/***************************************************************************
- *SEQ_WRDATA_ERR_INFO - Sequencer write data error info
- ***************************************************************************/
-/* MEMC_DDR_1 :: SEQ_WRDATA_ERR_INFO :: reserved0 [31:21] */
-#define BCHP_MEMC_DDR_1_SEQ_WRDATA_ERR_INFO_reserved0_MASK 0xffe00000
-#define BCHP_MEMC_DDR_1_SEQ_WRDATA_ERR_INFO_reserved0_SHIFT 21
-
-/* MEMC_DDR_1 :: SEQ_WRDATA_ERR_INFO :: INTF_ID [20:16] */
-#define BCHP_MEMC_DDR_1_SEQ_WRDATA_ERR_INFO_INTF_ID_MASK 0x001f0000
-#define BCHP_MEMC_DDR_1_SEQ_WRDATA_ERR_INFO_INTF_ID_SHIFT 16
-#define BCHP_MEMC_DDR_1_SEQ_WRDATA_ERR_INFO_INTF_ID_DEFAULT 0x00000000
-
-/* MEMC_DDR_1 :: SEQ_WRDATA_ERR_INFO :: reserved1 [15:08] */
-#define BCHP_MEMC_DDR_1_SEQ_WRDATA_ERR_INFO_reserved1_MASK 0x0000ff00
-#define BCHP_MEMC_DDR_1_SEQ_WRDATA_ERR_INFO_reserved1_SHIFT 8
-
-/* MEMC_DDR_1 :: SEQ_WRDATA_ERR_INFO :: INTF_TRANSACTION_ID [07:00] */
-#define BCHP_MEMC_DDR_1_SEQ_WRDATA_ERR_INFO_INTF_TRANSACTION_ID_MASK 0x000000ff
-#define BCHP_MEMC_DDR_1_SEQ_WRDATA_ERR_INFO_INTF_TRANSACTION_ID_SHIFT 0
-#define BCHP_MEMC_DDR_1_SEQ_WRDATA_ERR_INFO_INTF_TRANSACTION_ID_DEFAULT 0x00000000
-
-/***************************************************************************
- *SEQ_WRDATA_TRANSID_MISMATCH_INFO - Sequencer transaction ID mismatch error info
- ***************************************************************************/
-/* MEMC_DDR_1 :: SEQ_WRDATA_TRANSID_MISMATCH_INFO :: reserved0 [31:28] */
-#define BCHP_MEMC_DDR_1_SEQ_WRDATA_TRANSID_MISMATCH_INFO_reserved0_MASK 0xf0000000
-#define BCHP_MEMC_DDR_1_SEQ_WRDATA_TRANSID_MISMATCH_INFO_reserved0_SHIFT 28
-
-/* MEMC_DDR_1 :: SEQ_WRDATA_TRANSID_MISMATCH_INFO :: INTF_TYPE [27:24] */
-#define BCHP_MEMC_DDR_1_SEQ_WRDATA_TRANSID_MISMATCH_INFO_INTF_TYPE_MASK 0x0f000000
-#define BCHP_MEMC_DDR_1_SEQ_WRDATA_TRANSID_MISMATCH_INFO_INTF_TYPE_SHIFT 24
-#define BCHP_MEMC_DDR_1_SEQ_WRDATA_TRANSID_MISMATCH_INFO_INTF_TYPE_DEFAULT 0x00000000
-
-/* MEMC_DDR_1 :: SEQ_WRDATA_TRANSID_MISMATCH_INFO :: reserved1 [23:21] */
-#define BCHP_MEMC_DDR_1_SEQ_WRDATA_TRANSID_MISMATCH_INFO_reserved1_MASK 0x00e00000
-#define BCHP_MEMC_DDR_1_SEQ_WRDATA_TRANSID_MISMATCH_INFO_reserved1_SHIFT 21
-
-/* MEMC_DDR_1 :: SEQ_WRDATA_TRANSID_MISMATCH_INFO :: INTF_ID [20:16] */
-#define BCHP_MEMC_DDR_1_SEQ_WRDATA_TRANSID_MISMATCH_INFO_INTF_ID_MASK 0x001f0000
-#define BCHP_MEMC_DDR_1_SEQ_WRDATA_TRANSID_MISMATCH_INFO_INTF_ID_SHIFT 16
-#define BCHP_MEMC_DDR_1_SEQ_WRDATA_TRANSID_MISMATCH_INFO_INTF_ID_DEFAULT 0x00000000
-
-/* MEMC_DDR_1 :: SEQ_WRDATA_TRANSID_MISMATCH_INFO :: CMD_TRANS_ID [15:08] */
-#define BCHP_MEMC_DDR_1_SEQ_WRDATA_TRANSID_MISMATCH_INFO_CMD_TRANS_ID_MASK 0x0000ff00
-#define BCHP_MEMC_DDR_1_SEQ_WRDATA_TRANSID_MISMATCH_INFO_CMD_TRANS_ID_SHIFT 8
-#define BCHP_MEMC_DDR_1_SEQ_WRDATA_TRANSID_MISMATCH_INFO_CMD_TRANS_ID_DEFAULT 0x00000000
-
-/* MEMC_DDR_1 :: SEQ_WRDATA_TRANSID_MISMATCH_INFO :: WRDATA_TRANS_ID [07:00] */
-#define BCHP_MEMC_DDR_1_SEQ_WRDATA_TRANSID_MISMATCH_INFO_WRDATA_TRANS_ID_MASK 0x000000ff
-#define BCHP_MEMC_DDR_1_SEQ_WRDATA_TRANSID_MISMATCH_INFO_WRDATA_TRANS_ID_SHIFT 0
-#define BCHP_MEMC_DDR_1_SEQ_WRDATA_TRANSID_MISMATCH_INFO_WRDATA_TRANS_ID_DEFAULT 0x00000000
-
-/***************************************************************************
- *SEQ_CLEAR_VIOLATIONS - Sequencer Violation Info register clear.
- ***************************************************************************/
-/* MEMC_DDR_1 :: SEQ_CLEAR_VIOLATIONS :: reserved0 [31:01] */
-#define BCHP_MEMC_DDR_1_SEQ_CLEAR_VIOLATIONS_reserved0_MASK 0xfffffffe
-#define BCHP_MEMC_DDR_1_SEQ_CLEAR_VIOLATIONS_reserved0_SHIFT 1
-
-/* MEMC_DDR_1 :: SEQ_CLEAR_VIOLATIONS :: SEQ_CLEAR_VIOL [00:00] */
-#define BCHP_MEMC_DDR_1_SEQ_CLEAR_VIOLATIONS_SEQ_CLEAR_VIOL_MASK 0x00000001
-#define BCHP_MEMC_DDR_1_SEQ_CLEAR_VIOLATIONS_SEQ_CLEAR_VIOL_SHIFT 0
-#define BCHP_MEMC_DDR_1_SEQ_CLEAR_VIOLATIONS_SEQ_CLEAR_VIOL_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CONTROL - Statistics Control register
- ***************************************************************************/
-/* MEMC_DDR_1 :: STAT_CONTROL :: reserved0 [31:11] */
-#define BCHP_MEMC_DDR_1_STAT_CONTROL_reserved0_MASK 0xfffff800
-#define BCHP_MEMC_DDR_1_STAT_CONTROL_reserved0_SHIFT 11
-
-/* MEMC_DDR_1 :: STAT_CONTROL :: PER_CLIENT_MODE [10:10] */
-#define BCHP_MEMC_DDR_1_STAT_CONTROL_PER_CLIENT_MODE_MASK 0x00000400
-#define BCHP_MEMC_DDR_1_STAT_CONTROL_PER_CLIENT_MODE_SHIFT 10
-#define BCHP_MEMC_DDR_1_STAT_CONTROL_PER_CLIENT_MODE_DEFAULT 0x00000000
-
-/* MEMC_DDR_1 :: STAT_CONTROL :: COUNTER_MODE [09:09] */
-#define BCHP_MEMC_DDR_1_STAT_CONTROL_COUNTER_MODE_MASK 0x00000200
-#define BCHP_MEMC_DDR_1_STAT_CONTROL_COUNTER_MODE_SHIFT 9
-#define BCHP_MEMC_DDR_1_STAT_CONTROL_COUNTER_MODE_DEFAULT 0x00000000
-#define BCHP_MEMC_DDR_1_STAT_CONTROL_COUNTER_MODE_MAX_MIN_FUNCT 1
-#define BCHP_MEMC_DDR_1_STAT_CONTROL_COUNTER_MODE_NORMAL 0
-
-/* MEMC_DDR_1 :: STAT_CONTROL :: STAT_ENABLE [08:08] */
-#define BCHP_MEMC_DDR_1_STAT_CONTROL_STAT_ENABLE_MASK 0x00000100
-#define BCHP_MEMC_DDR_1_STAT_CONTROL_STAT_ENABLE_SHIFT 8
-#define BCHP_MEMC_DDR_1_STAT_CONTROL_STAT_ENABLE_DEFAULT 0x00000000
-#define BCHP_MEMC_DDR_1_STAT_CONTROL_STAT_ENABLE_ENABLE 1
-#define BCHP_MEMC_DDR_1_STAT_CONTROL_STAT_ENABLE_DISABLE 0
-
-/* MEMC_DDR_1 :: STAT_CONTROL :: CLIENT_ID [07:00] */
-#define BCHP_MEMC_DDR_1_STAT_CONTROL_CLIENT_ID_MASK 0x000000ff
-#define BCHP_MEMC_DDR_1_STAT_CONTROL_CLIENT_ID_SHIFT 0
-#define BCHP_MEMC_DDR_1_STAT_CONTROL_CLIENT_ID_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_TIMER - Statistics Timer
- ***************************************************************************/
-/* MEMC_DDR_1 :: STAT_TIMER :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_1_STAT_TIMER_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_1_STAT_TIMER_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_1_STAT_TIMER_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_IDLE_NOP - DRAM Idle_NOP Cycle Count Register.
- ***************************************************************************/
-/* MEMC_DDR_1 :: STAT_IDLE_NOP :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_1_STAT_IDLE_NOP_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_1_STAT_IDLE_NOP_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_1_STAT_IDLE_NOP_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_MAX_IDLE_NOP - Maximum DRAM idle_NOP cycle count register.
- ***************************************************************************/
-/* MEMC_DDR_1 :: STAT_MAX_IDLE_NOP :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_1_STAT_MAX_IDLE_NOP_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_1_STAT_MAX_IDLE_NOP_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_1_STAT_MAX_IDLE_NOP_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_MIN_IDLE_NOP - Minimum DRAM idle_NOP cycle count register.
- ***************************************************************************/
-/* MEMC_DDR_1 :: STAT_MIN_IDLE_NOP :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_1_STAT_MIN_IDLE_NOP_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_1_STAT_MIN_IDLE_NOP_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_1_STAT_MIN_IDLE_NOP_COUNT_DEFAULT 0xffffffff
-
-/***************************************************************************
- *STAT_CAS_ALL - CAS Count Register.
- ***************************************************************************/
-/* MEMC_DDR_1 :: STAT_CAS_ALL :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_1_STAT_CAS_ALL_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_1_STAT_CAS_ALL_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_1_STAT_CAS_ALL_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_MAX_CAS_ALL - Maximum DRAM CAS cycle count register.
- ***************************************************************************/
-/* MEMC_DDR_1 :: STAT_MAX_CAS_ALL :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_1_STAT_MAX_CAS_ALL_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_1_STAT_MAX_CAS_ALL_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_1_STAT_MAX_CAS_ALL_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_MIN_CAS_ALL - Minimum DRAM CAS cycle count register.
- ***************************************************************************/
-/* MEMC_DDR_1 :: STAT_MIN_CAS_ALL :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_1_STAT_MIN_CAS_ALL_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_1_STAT_MIN_CAS_ALL_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_1_STAT_MIN_CAS_ALL_COUNT_DEFAULT 0xffffffff
-
-/***************************************************************************
- *STAT_PENALTY_ALL - DRAM Penalty Cycle Count register.
- ***************************************************************************/
-/* MEMC_DDR_1 :: STAT_PENALTY_ALL :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_1_STAT_PENALTY_ALL_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_1_STAT_PENALTY_ALL_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_1_STAT_PENALTY_ALL_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_PENALTY_GDDRWM - GDDR Write Mask Penalty Cycle Count register.
- ***************************************************************************/
-/* MEMC_DDR_1 :: STAT_PENALTY_GDDRWM :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_1_STAT_PENALTY_GDDRWM_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_1_STAT_PENALTY_GDDRWM_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_1_STAT_PENALTY_GDDRWM_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_MAX_TRANS_CYCLES_ALL - Maximum number of transactions cycles (CAS+Penalty_ALL).
- ***************************************************************************/
-/* MEMC_DDR_1 :: STAT_MAX_TRANS_CYCLES_ALL :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_1_STAT_MAX_TRANS_CYCLES_ALL_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_1_STAT_MAX_TRANS_CYCLES_ALL_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_1_STAT_MAX_TRANS_CYCLES_ALL_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_MIN_TRANS_CYCLES_ALL - Minimum number of transactions cycles (CAS+Penalty_ALL).
- ***************************************************************************/
-/* MEMC_DDR_1 :: STAT_MIN_TRANS_CYCLES_ALL :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_1_STAT_MIN_TRANS_CYCLES_ALL_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_1_STAT_MIN_TRANS_CYCLES_ALL_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_1_STAT_MIN_TRANS_CYCLES_ALL_COUNT_DEFAULT 0xffffffff
-
-/***************************************************************************
- *STAT_TRANS_READ_ALL - Number of overall system memory read transactions.
- ***************************************************************************/
-/* MEMC_DDR_1 :: STAT_TRANS_READ_ALL :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_1_STAT_TRANS_READ_ALL_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_1_STAT_TRANS_READ_ALL_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_1_STAT_TRANS_READ_ALL_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_TRANS_WRITE_ALL - Number of overall system memory write transactions.
- ***************************************************************************/
-/* MEMC_DDR_1 :: STAT_TRANS_WRITE_ALL :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_1_STAT_TRANS_WRITE_ALL_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_1_STAT_TRANS_WRITE_ALL_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_1_STAT_TRANS_WRITE_ALL_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_MAX_TRANS_ALL - Maximum Number of Overall System memory transactions.
- ***************************************************************************/
-/* MEMC_DDR_1 :: STAT_MAX_TRANS_ALL :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_1_STAT_MAX_TRANS_ALL_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_1_STAT_MAX_TRANS_ALL_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_1_STAT_MAX_TRANS_ALL_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_MIN_TRANS_ALL - Minimum Number of Overall System memory transactions.
- ***************************************************************************/
-/* MEMC_DDR_1 :: STAT_MIN_TRANS_ALL :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_1_STAT_MIN_TRANS_ALL_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_1_STAT_MIN_TRANS_ALL_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_1_STAT_MIN_TRANS_ALL_COUNT_DEFAULT 0xffffffff
-
-/***************************************************************************
- *STAT_CLIENT_SERVICE_CAS - Service CAS Cycle Count register.
- ***************************************************************************/
-/* MEMC_DDR_1 :: STAT_CLIENT_SERVICE_CAS :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_1_STAT_CLIENT_SERVICE_CAS_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_1_STAT_CLIENT_SERVICE_CAS_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_1_STAT_CLIENT_SERVICE_CAS_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_MAX_CLIENT_SERVICE_CAS - Maximum service CAS cycle count register.
- ***************************************************************************/
-/* MEMC_DDR_1 :: STAT_MAX_CLIENT_SERVICE_CAS :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_1_STAT_MAX_CLIENT_SERVICE_CAS_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_1_STAT_MAX_CLIENT_SERVICE_CAS_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_1_STAT_MAX_CLIENT_SERVICE_CAS_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_MIN_CLIENT_SERVICE_CAS - Minimum service CAS cycle count register.
- ***************************************************************************/
-/* MEMC_DDR_1 :: STAT_MIN_CLIENT_SERVICE_CAS :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_1_STAT_MIN_CLIENT_SERVICE_CAS_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_1_STAT_MIN_CLIENT_SERVICE_CAS_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_1_STAT_MIN_CLIENT_SERVICE_CAS_COUNT_DEFAULT 0xffffffff
-
-/***************************************************************************
- *STAT_CLIENT_SERVICE_INTR_PENALTY - Service Intra DRAM Penalty Cycle Count register.
- ***************************************************************************/
-/* MEMC_DDR_1 :: STAT_CLIENT_SERVICE_INTR_PENALTY :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_1_STAT_CLIENT_SERVICE_INTR_PENALTY_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_1_STAT_CLIENT_SERVICE_INTR_PENALTY_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_1_STAT_CLIENT_SERVICE_INTR_PENALTY_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CLIENT_SERVICE_POST_PENALTY - Service Post DRAM Penalty Cycle Count register.
- ***************************************************************************/
-/* MEMC_DDR_1 :: STAT_CLIENT_SERVICE_POST_PENALTY :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_1_STAT_CLIENT_SERVICE_POST_PENALTY_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_1_STAT_CLIENT_SERVICE_POST_PENALTY_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_1_STAT_CLIENT_SERVICE_POST_PENALTY_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CLIENT_SERVICE_GDDRWM_PENALTY - Service GDDR Write Mask Penalty Cycle Count register.
- ***************************************************************************/
-/* MEMC_DDR_1 :: STAT_CLIENT_SERVICE_GDDRWM_PENALTY :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_1_STAT_CLIENT_SERVICE_GDDRWM_PENALTY_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_1_STAT_CLIENT_SERVICE_GDDRWM_PENALTY_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_1_STAT_CLIENT_SERVICE_GDDRWM_PENALTY_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_MAX_CLIENT_SERVICE_CYCLES - Maximum service cycle count register.
- ***************************************************************************/
-/* MEMC_DDR_1 :: STAT_MAX_CLIENT_SERVICE_CYCLES :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_1_STAT_MAX_CLIENT_SERVICE_CYCLES_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_1_STAT_MAX_CLIENT_SERVICE_CYCLES_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_1_STAT_MAX_CLIENT_SERVICE_CYCLES_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_MIN_CLIENT_SERVICE_CYCLES - Minimum service cycle count register.
- ***************************************************************************/
-/* MEMC_DDR_1 :: STAT_MIN_CLIENT_SERVICE_CYCLES :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_1_STAT_MIN_CLIENT_SERVICE_CYCLES_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_1_STAT_MIN_CLIENT_SERVICE_CYCLES_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_1_STAT_MIN_CLIENT_SERVICE_CYCLES_COUNT_DEFAULT 0xffffffff
-
-/***************************************************************************
- *STAT_CLIENT_SERVICE_TRANS_READ - Service Read Transaction Count register.
- ***************************************************************************/
-/* MEMC_DDR_1 :: STAT_CLIENT_SERVICE_TRANS_READ :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_1_STAT_CLIENT_SERVICE_TRANS_READ_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_1_STAT_CLIENT_SERVICE_TRANS_READ_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_1_STAT_CLIENT_SERVICE_TRANS_READ_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CLIENT_SERVICE_TRANS_WRITE - Service Write Transaction Count register.
- ***************************************************************************/
-/* MEMC_DDR_1 :: STAT_CLIENT_SERVICE_TRANS_WRITE :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_1_STAT_CLIENT_SERVICE_TRANS_WRITE_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_1_STAT_CLIENT_SERVICE_TRANS_WRITE_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_1_STAT_CLIENT_SERVICE_TRANS_WRITE_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_MAX_CLIENT_SERVICE_TRANS - Maximum service Transaction count register.
- ***************************************************************************/
-/* MEMC_DDR_1 :: STAT_MAX_CLIENT_SERVICE_TRANS :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_1_STAT_MAX_CLIENT_SERVICE_TRANS_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_1_STAT_MAX_CLIENT_SERVICE_TRANS_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_1_STAT_MAX_CLIENT_SERVICE_TRANS_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_MIN_CLIENT_SERVICE_TRANS - Minimum service cycle Transaction register.
- ***************************************************************************/
-/* MEMC_DDR_1 :: STAT_MIN_CLIENT_SERVICE_TRANS :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_1_STAT_MIN_CLIENT_SERVICE_TRANS_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_1_STAT_MIN_CLIENT_SERVICE_TRANS_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_1_STAT_MIN_CLIENT_SERVICE_TRANS_COUNT_DEFAULT 0xffffffff
-
-/***************************************************************************
- *STAT_CLIENT_SERVICE_LATENCY - Service Latency Count register.
- ***************************************************************************/
-/* MEMC_DDR_1 :: STAT_CLIENT_SERVICE_LATENCY :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_1_STAT_CLIENT_SERVICE_LATENCY_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_1_STAT_CLIENT_SERVICE_LATENCY_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_1_STAT_CLIENT_SERVICE_LATENCY_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_MAX_CLIENT_SERVICE_LATENCY - Maximum Service Latency count register.
- ***************************************************************************/
-/* MEMC_DDR_1 :: STAT_MAX_CLIENT_SERVICE_LATENCY :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_1_STAT_MAX_CLIENT_SERVICE_LATENCY_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_1_STAT_MAX_CLIENT_SERVICE_LATENCY_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_1_STAT_MAX_CLIENT_SERVICE_LATENCY_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_MIN_CLIENT_SERVICE_LATENCY - Minimum Service Latency count register.
- ***************************************************************************/
-/* MEMC_DDR_1 :: STAT_MIN_CLIENT_SERVICE_LATENCY :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_1_STAT_MIN_CLIENT_SERVICE_LATENCY_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_1_STAT_MIN_CLIENT_SERVICE_LATENCY_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_1_STAT_MIN_CLIENT_SERVICE_LATENCY_COUNT_DEFAULT 0xffffffff
-
-/***************************************************************************
- *STAT_CLIENT_ABS_MAX_SERVICE_LATENCY - Absolute Minimum Service Latency count register.
- ***************************************************************************/
-/* MEMC_DDR_1 :: STAT_CLIENT_ABS_MAX_SERVICE_LATENCY :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_1_STAT_CLIENT_ABS_MAX_SERVICE_LATENCY_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_1_STAT_CLIENT_ABS_MAX_SERVICE_LATENCY_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_1_STAT_CLIENT_ABS_MAX_SERVICE_LATENCY_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CLIENT_ABS_MIN_SERVICE_LATENCY - Absolute Maximum Service Latency count register.
- ***************************************************************************/
-/* MEMC_DDR_1 :: STAT_CLIENT_ABS_MIN_SERVICE_LATENCY :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_1_STAT_CLIENT_ABS_MIN_SERVICE_LATENCY_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_1_STAT_CLIENT_ABS_MIN_SERVICE_LATENCY_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_1_STAT_CLIENT_ABS_MIN_SERVICE_LATENCY_COUNT_DEFAULT 0xffffffff
-
-/***************************************************************************
- *STAT_REFRESH - Total number of refreshes issued.
- ***************************************************************************/
-/* MEMC_DDR_1 :: STAT_REFRESH :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_1_STAT_REFRESH_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_1_STAT_REFRESH_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_1_STAT_REFRESH_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_MIN_DQ_IDLE_WRITE - Min DQ Idle Write event counter
- ***************************************************************************/
-/* MEMC_DDR_1 :: STAT_MIN_DQ_IDLE_WRITE :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_1_STAT_MIN_DQ_IDLE_WRITE_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_1_STAT_MIN_DQ_IDLE_WRITE_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_1_STAT_MIN_DQ_IDLE_WRITE_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_MIN_DQ_IDLE_READ - Min DQ Idle Read event counter
- ***************************************************************************/
-/* MEMC_DDR_1 :: STAT_MIN_DQ_IDLE_READ :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_1_STAT_MIN_DQ_IDLE_READ_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_1_STAT_MIN_DQ_IDLE_READ_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_1_STAT_MIN_DQ_IDLE_READ_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_0 - CAS or consumption cycle count register for client 0.
- ***************************************************************************/
-/* MEMC_DDR_1 :: STAT_CAS_CLIENT_0 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_0_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_0_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_0_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_1 - CAS or consumption cycle count register for client 1.
- ***************************************************************************/
-/* MEMC_DDR_1 :: STAT_CAS_CLIENT_1 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_1_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_1_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_1_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_2 - CAS or consumption cycle count register for client 2.
- ***************************************************************************/
-/* MEMC_DDR_1 :: STAT_CAS_CLIENT_2 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_2_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_2_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_2_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_3 - CAS or consumption cycle count register for client 3.
- ***************************************************************************/
-/* MEMC_DDR_1 :: STAT_CAS_CLIENT_3 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_3_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_3_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_3_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_4 - CAS or consumption cycle count register for client 4.
- ***************************************************************************/
-/* MEMC_DDR_1 :: STAT_CAS_CLIENT_4 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_4_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_4_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_4_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_5 - CAS or consumption cycle count register for client 5.
- ***************************************************************************/
-/* MEMC_DDR_1 :: STAT_CAS_CLIENT_5 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_5_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_5_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_5_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_6 - CAS or consumption cycle count register for client 6.
- ***************************************************************************/
-/* MEMC_DDR_1 :: STAT_CAS_CLIENT_6 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_6_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_6_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_6_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_7 - CAS or consumption cycle count register for client 7.
- ***************************************************************************/
-/* MEMC_DDR_1 :: STAT_CAS_CLIENT_7 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_7_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_7_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_7_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_8 - CAS or consumption cycle count register for client 8.
- ***************************************************************************/
-/* MEMC_DDR_1 :: STAT_CAS_CLIENT_8 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_8_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_8_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_8_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_9 - CAS or consumption cycle count register for client 9.
- ***************************************************************************/
-/* MEMC_DDR_1 :: STAT_CAS_CLIENT_9 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_9_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_9_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_9_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_10 - CAS or consumption cycle count register for client 10.
- ***************************************************************************/
-/* MEMC_DDR_1 :: STAT_CAS_CLIENT_10 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_10_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_10_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_10_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_11 - CAS or consumption cycle count register for client 11.
- ***************************************************************************/
-/* MEMC_DDR_1 :: STAT_CAS_CLIENT_11 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_11_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_11_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_11_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_12 - CAS or consumption cycle count register for client 12.
- ***************************************************************************/
-/* MEMC_DDR_1 :: STAT_CAS_CLIENT_12 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_12_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_12_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_12_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_13 - CAS or consumption cycle count register for client 13.
- ***************************************************************************/
-/* MEMC_DDR_1 :: STAT_CAS_CLIENT_13 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_13_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_13_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_13_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_14 - CAS or consumption cycle count register for client 14.
- ***************************************************************************/
-/* MEMC_DDR_1 :: STAT_CAS_CLIENT_14 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_14_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_14_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_14_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_15 - CAS or consumption cycle count register for client 15.
- ***************************************************************************/
-/* MEMC_DDR_1 :: STAT_CAS_CLIENT_15 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_15_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_15_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_15_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_16 - CAS or consumption cycle count register for client 16.
- ***************************************************************************/
-/* MEMC_DDR_1 :: STAT_CAS_CLIENT_16 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_16_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_16_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_16_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_17 - CAS or consumption cycle count register for client 17.
- ***************************************************************************/
-/* MEMC_DDR_1 :: STAT_CAS_CLIENT_17 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_17_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_17_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_17_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_18 - CAS or consumption cycle count register for client 18.
- ***************************************************************************/
-/* MEMC_DDR_1 :: STAT_CAS_CLIENT_18 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_18_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_18_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_18_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_19 - CAS or consumption cycle count register for client 19.
- ***************************************************************************/
-/* MEMC_DDR_1 :: STAT_CAS_CLIENT_19 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_19_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_19_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_19_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_20 - CAS or consumption cycle count register for client 20.
- ***************************************************************************/
-/* MEMC_DDR_1 :: STAT_CAS_CLIENT_20 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_20_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_20_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_20_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_21 - CAS or consumption cycle count register for client 21.
- ***************************************************************************/
-/* MEMC_DDR_1 :: STAT_CAS_CLIENT_21 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_21_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_21_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_21_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_22 - CAS or consumption cycle count register for client 22.
- ***************************************************************************/
-/* MEMC_DDR_1 :: STAT_CAS_CLIENT_22 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_22_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_22_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_22_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_23 - CAS or consumption cycle count register for client 23.
- ***************************************************************************/
-/* MEMC_DDR_1 :: STAT_CAS_CLIENT_23 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_23_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_23_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_23_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_24 - CAS or consumption cycle count register for client 24.
- ***************************************************************************/
-/* MEMC_DDR_1 :: STAT_CAS_CLIENT_24 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_24_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_24_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_24_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_25 - CAS or consumption cycle count register for client 25.
- ***************************************************************************/
-/* MEMC_DDR_1 :: STAT_CAS_CLIENT_25 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_25_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_25_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_25_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_26 - CAS or consumption cycle count register for client 26.
- ***************************************************************************/
-/* MEMC_DDR_1 :: STAT_CAS_CLIENT_26 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_26_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_26_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_26_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_27 - CAS or consumption cycle count register for client 27.
- ***************************************************************************/
-/* MEMC_DDR_1 :: STAT_CAS_CLIENT_27 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_27_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_27_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_27_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_28 - CAS or consumption cycle count register for client 28.
- ***************************************************************************/
-/* MEMC_DDR_1 :: STAT_CAS_CLIENT_28 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_28_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_28_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_28_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_29 - CAS or consumption cycle count register for client 29.
- ***************************************************************************/
-/* MEMC_DDR_1 :: STAT_CAS_CLIENT_29 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_29_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_29_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_29_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_30 - CAS or consumption cycle count register for client 30.
- ***************************************************************************/
-/* MEMC_DDR_1 :: STAT_CAS_CLIENT_30 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_30_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_30_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_30_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_31 - CAS or consumption cycle count register for client 31.
- ***************************************************************************/
-/* MEMC_DDR_1 :: STAT_CAS_CLIENT_31 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_31_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_31_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_31_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_32 - CAS or consumption cycle count register for client 32.
- ***************************************************************************/
-/* MEMC_DDR_1 :: STAT_CAS_CLIENT_32 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_32_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_32_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_32_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_33 - CAS or consumption cycle count register for client 33.
- ***************************************************************************/
-/* MEMC_DDR_1 :: STAT_CAS_CLIENT_33 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_33_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_33_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_33_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_34 - CAS or consumption cycle count register for client 34.
- ***************************************************************************/
-/* MEMC_DDR_1 :: STAT_CAS_CLIENT_34 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_34_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_34_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_34_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_35 - CAS or consumption cycle count register for client 35.
- ***************************************************************************/
-/* MEMC_DDR_1 :: STAT_CAS_CLIENT_35 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_35_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_35_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_35_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_36 - CAS or consumption cycle count register for client 36.
- ***************************************************************************/
-/* MEMC_DDR_1 :: STAT_CAS_CLIENT_36 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_36_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_36_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_36_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_37 - CAS or consumption cycle count register for client 37.
- ***************************************************************************/
-/* MEMC_DDR_1 :: STAT_CAS_CLIENT_37 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_37_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_37_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_37_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_38 - CAS or consumption cycle count register for client 38.
- ***************************************************************************/
-/* MEMC_DDR_1 :: STAT_CAS_CLIENT_38 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_38_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_38_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_38_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_39 - CAS or consumption cycle count register for client 39.
- ***************************************************************************/
-/* MEMC_DDR_1 :: STAT_CAS_CLIENT_39 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_39_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_39_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_39_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_40 - CAS or consumption cycle count register for client 40.
- ***************************************************************************/
-/* MEMC_DDR_1 :: STAT_CAS_CLIENT_40 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_40_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_40_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_40_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_41 - CAS or consumption cycle count register for client 41.
- ***************************************************************************/
-/* MEMC_DDR_1 :: STAT_CAS_CLIENT_41 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_41_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_41_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_41_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_42 - CAS or consumption cycle count register for client 42.
- ***************************************************************************/
-/* MEMC_DDR_1 :: STAT_CAS_CLIENT_42 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_42_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_42_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_42_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_43 - CAS or consumption cycle count register for client 43.
- ***************************************************************************/
-/* MEMC_DDR_1 :: STAT_CAS_CLIENT_43 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_43_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_43_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_43_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_44 - CAS or consumption cycle count register for client 44.
- ***************************************************************************/
-/* MEMC_DDR_1 :: STAT_CAS_CLIENT_44 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_44_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_44_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_44_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_45 - CAS or consumption cycle count register for client 45.
- ***************************************************************************/
-/* MEMC_DDR_1 :: STAT_CAS_CLIENT_45 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_45_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_45_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_45_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_46 - CAS or consumption cycle count register for client 46.
- ***************************************************************************/
-/* MEMC_DDR_1 :: STAT_CAS_CLIENT_46 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_46_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_46_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_46_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_47 - CAS or consumption cycle count register for client 47.
- ***************************************************************************/
-/* MEMC_DDR_1 :: STAT_CAS_CLIENT_47 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_47_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_47_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_47_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_48 - CAS or consumption cycle count register for client 48.
- ***************************************************************************/
-/* MEMC_DDR_1 :: STAT_CAS_CLIENT_48 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_48_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_48_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_48_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_49 - CAS or consumption cycle count register for client 49.
- ***************************************************************************/
-/* MEMC_DDR_1 :: STAT_CAS_CLIENT_49 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_49_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_49_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_49_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_50 - CAS or consumption cycle count register for client 50.
- ***************************************************************************/
-/* MEMC_DDR_1 :: STAT_CAS_CLIENT_50 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_50_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_50_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_50_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_51 - CAS or consumption cycle count register for client 51.
- ***************************************************************************/
-/* MEMC_DDR_1 :: STAT_CAS_CLIENT_51 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_51_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_51_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_51_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_52 - CAS or consumption cycle count register for client 52.
- ***************************************************************************/
-/* MEMC_DDR_1 :: STAT_CAS_CLIENT_52 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_52_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_52_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_52_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_53 - CAS or consumption cycle count register for client 53.
- ***************************************************************************/
-/* MEMC_DDR_1 :: STAT_CAS_CLIENT_53 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_53_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_53_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_53_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_54 - CAS or consumption cycle count register for client 54.
- ***************************************************************************/
-/* MEMC_DDR_1 :: STAT_CAS_CLIENT_54 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_54_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_54_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_54_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_55 - CAS or consumption cycle count register for client 55.
- ***************************************************************************/
-/* MEMC_DDR_1 :: STAT_CAS_CLIENT_55 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_55_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_55_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_55_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_56 - CAS or consumption cycle count register for client 56.
- ***************************************************************************/
-/* MEMC_DDR_1 :: STAT_CAS_CLIENT_56 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_56_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_56_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_56_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_57 - CAS or consumption cycle count register for client 57.
- ***************************************************************************/
-/* MEMC_DDR_1 :: STAT_CAS_CLIENT_57 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_57_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_57_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_57_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_58 - CAS or consumption cycle count register for client 58.
- ***************************************************************************/
-/* MEMC_DDR_1 :: STAT_CAS_CLIENT_58 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_58_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_58_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_58_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_59 - CAS or consumption cycle count register for client 59.
- ***************************************************************************/
-/* MEMC_DDR_1 :: STAT_CAS_CLIENT_59 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_59_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_59_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_59_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_60 - CAS or consumption cycle count register for client 60.
- ***************************************************************************/
-/* MEMC_DDR_1 :: STAT_CAS_CLIENT_60 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_60_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_60_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_60_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_61 - CAS or consumption cycle count register for client 61.
- ***************************************************************************/
-/* MEMC_DDR_1 :: STAT_CAS_CLIENT_61 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_61_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_61_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_61_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_62 - CAS or consumption cycle count register for client 62.
- ***************************************************************************/
-/* MEMC_DDR_1 :: STAT_CAS_CLIENT_62 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_62_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_62_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_62_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_63 - CAS or consumption cycle count register for client 63.
- ***************************************************************************/
-/* MEMC_DDR_1 :: STAT_CAS_CLIENT_63 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_63_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_63_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_63_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_64 - CAS or consumption cycle count register for client 64.
- ***************************************************************************/
-/* MEMC_DDR_1 :: STAT_CAS_CLIENT_64 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_64_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_64_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_64_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_65 - CAS or consumption cycle count register for client 65.
- ***************************************************************************/
-/* MEMC_DDR_1 :: STAT_CAS_CLIENT_65 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_65_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_65_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_65_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_66 - CAS or consumption cycle count register for client 66.
- ***************************************************************************/
-/* MEMC_DDR_1 :: STAT_CAS_CLIENT_66 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_66_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_66_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_66_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_67 - CAS or consumption cycle count register for client 67.
- ***************************************************************************/
-/* MEMC_DDR_1 :: STAT_CAS_CLIENT_67 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_67_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_67_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_67_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_68 - CAS or consumption cycle count register for client 68.
- ***************************************************************************/
-/* MEMC_DDR_1 :: STAT_CAS_CLIENT_68 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_68_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_68_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_68_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_69 - CAS or consumption cycle count register for client 69.
- ***************************************************************************/
-/* MEMC_DDR_1 :: STAT_CAS_CLIENT_69 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_69_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_69_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_69_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_70 - CAS or consumption cycle count register for client 70.
- ***************************************************************************/
-/* MEMC_DDR_1 :: STAT_CAS_CLIENT_70 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_70_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_70_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_70_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_71 - CAS or consumption cycle count register for client 71.
- ***************************************************************************/
-/* MEMC_DDR_1 :: STAT_CAS_CLIENT_71 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_71_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_71_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_71_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_72 - CAS or consumption cycle count register for client 72.
- ***************************************************************************/
-/* MEMC_DDR_1 :: STAT_CAS_CLIENT_72 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_72_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_72_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_72_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_73 - CAS or consumption cycle count register for client 73.
- ***************************************************************************/
-/* MEMC_DDR_1 :: STAT_CAS_CLIENT_73 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_73_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_73_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_73_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_74 - CAS or consumption cycle count register for client 74.
- ***************************************************************************/
-/* MEMC_DDR_1 :: STAT_CAS_CLIENT_74 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_74_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_74_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_74_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_75 - CAS or consumption cycle count register for client 75.
- ***************************************************************************/
-/* MEMC_DDR_1 :: STAT_CAS_CLIENT_75 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_75_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_75_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_75_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_76 - CAS or consumption cycle count register for client 76.
- ***************************************************************************/
-/* MEMC_DDR_1 :: STAT_CAS_CLIENT_76 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_76_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_76_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_76_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_77 - CAS or consumption cycle count register for client 77.
- ***************************************************************************/
-/* MEMC_DDR_1 :: STAT_CAS_CLIENT_77 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_77_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_77_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_77_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_78 - CAS or consumption cycle count register for client 78.
- ***************************************************************************/
-/* MEMC_DDR_1 :: STAT_CAS_CLIENT_78 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_78_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_78_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_78_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_79 - CAS or consumption cycle count register for client 79.
- ***************************************************************************/
-/* MEMC_DDR_1 :: STAT_CAS_CLIENT_79 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_79_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_79_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_79_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_80 - CAS or consumption cycle count register for client 80.
- ***************************************************************************/
-/* MEMC_DDR_1 :: STAT_CAS_CLIENT_80 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_80_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_80_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_80_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_81 - CAS or consumption cycle count register for client 81.
- ***************************************************************************/
-/* MEMC_DDR_1 :: STAT_CAS_CLIENT_81 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_81_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_81_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_81_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_82 - CAS or consumption cycle count register for client 82.
- ***************************************************************************/
-/* MEMC_DDR_1 :: STAT_CAS_CLIENT_82 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_82_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_82_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_82_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_83 - CAS or consumption cycle count register for client 83.
- ***************************************************************************/
-/* MEMC_DDR_1 :: STAT_CAS_CLIENT_83 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_83_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_83_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_83_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_84 - CAS or consumption cycle count register for client 84.
- ***************************************************************************/
-/* MEMC_DDR_1 :: STAT_CAS_CLIENT_84 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_84_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_84_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_84_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_85 - CAS or consumption cycle count register for client 85.
- ***************************************************************************/
-/* MEMC_DDR_1 :: STAT_CAS_CLIENT_85 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_85_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_85_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_85_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_86 - CAS or consumption cycle count register for client 86.
- ***************************************************************************/
-/* MEMC_DDR_1 :: STAT_CAS_CLIENT_86 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_86_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_86_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_86_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_87 - CAS or consumption cycle count register for client 87.
- ***************************************************************************/
-/* MEMC_DDR_1 :: STAT_CAS_CLIENT_87 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_87_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_87_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_87_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_88 - CAS or consumption cycle count register for client 88.
- ***************************************************************************/
-/* MEMC_DDR_1 :: STAT_CAS_CLIENT_88 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_88_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_88_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_88_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_89 - CAS or consumption cycle count register for client 89.
- ***************************************************************************/
-/* MEMC_DDR_1 :: STAT_CAS_CLIENT_89 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_89_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_89_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_89_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_90 - CAS or consumption cycle count register for client 90.
- ***************************************************************************/
-/* MEMC_DDR_1 :: STAT_CAS_CLIENT_90 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_90_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_90_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_90_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_91 - CAS or consumption cycle count register for client 91.
- ***************************************************************************/
-/* MEMC_DDR_1 :: STAT_CAS_CLIENT_91 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_91_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_91_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_91_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_92 - CAS or consumption cycle count register for client 92.
- ***************************************************************************/
-/* MEMC_DDR_1 :: STAT_CAS_CLIENT_92 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_92_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_92_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_92_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_93 - CAS or consumption cycle count register for client 93.
- ***************************************************************************/
-/* MEMC_DDR_1 :: STAT_CAS_CLIENT_93 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_93_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_93_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_93_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_94 - CAS or consumption cycle count register for client 94.
- ***************************************************************************/
-/* MEMC_DDR_1 :: STAT_CAS_CLIENT_94 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_94_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_94_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_94_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_95 - CAS or consumption cycle count register for client 95.
- ***************************************************************************/
-/* MEMC_DDR_1 :: STAT_CAS_CLIENT_95 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_95_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_95_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_95_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_96 - CAS or consumption cycle count register for client 96.
- ***************************************************************************/
-/* MEMC_DDR_1 :: STAT_CAS_CLIENT_96 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_96_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_96_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_96_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_97 - CAS or consumption cycle count register for client 97.
- ***************************************************************************/
-/* MEMC_DDR_1 :: STAT_CAS_CLIENT_97 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_97_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_97_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_97_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_98 - CAS or consumption cycle count register for client 98.
- ***************************************************************************/
-/* MEMC_DDR_1 :: STAT_CAS_CLIENT_98 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_98_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_98_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_98_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_99 - CAS or consumption cycle count register for client 99.
- ***************************************************************************/
-/* MEMC_DDR_1 :: STAT_CAS_CLIENT_99 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_99_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_99_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_99_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_100 - CAS or consumption cycle count register for client 100.
- ***************************************************************************/
-/* MEMC_DDR_1 :: STAT_CAS_CLIENT_100 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_100_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_100_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_100_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_101 - CAS or consumption cycle count register for client 101.
- ***************************************************************************/
-/* MEMC_DDR_1 :: STAT_CAS_CLIENT_101 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_101_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_101_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_101_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_102 - CAS or consumption cycle count register for client 102.
- ***************************************************************************/
-/* MEMC_DDR_1 :: STAT_CAS_CLIENT_102 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_102_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_102_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_102_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_103 - CAS or consumption cycle count register for client 103.
- ***************************************************************************/
-/* MEMC_DDR_1 :: STAT_CAS_CLIENT_103 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_103_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_103_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_103_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_104 - CAS or consumption cycle count register for client 104.
- ***************************************************************************/
-/* MEMC_DDR_1 :: STAT_CAS_CLIENT_104 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_104_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_104_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_104_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_105 - CAS or consumption cycle count register for client 105.
- ***************************************************************************/
-/* MEMC_DDR_1 :: STAT_CAS_CLIENT_105 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_105_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_105_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_105_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_106 - CAS or consumption cycle count register for client 106.
- ***************************************************************************/
-/* MEMC_DDR_1 :: STAT_CAS_CLIENT_106 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_106_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_106_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_106_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_107 - CAS or consumption cycle count register for client 107.
- ***************************************************************************/
-/* MEMC_DDR_1 :: STAT_CAS_CLIENT_107 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_107_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_107_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_107_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_108 - CAS or consumption cycle count register for client 108.
- ***************************************************************************/
-/* MEMC_DDR_1 :: STAT_CAS_CLIENT_108 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_108_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_108_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_108_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_109 - CAS or consumption cycle count register for client 109.
- ***************************************************************************/
-/* MEMC_DDR_1 :: STAT_CAS_CLIENT_109 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_109_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_109_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_109_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_110 - CAS or consumption cycle count register for client 110.
- ***************************************************************************/
-/* MEMC_DDR_1 :: STAT_CAS_CLIENT_110 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_110_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_110_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_110_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_111 - CAS or consumption cycle count register for client 111.
- ***************************************************************************/
-/* MEMC_DDR_1 :: STAT_CAS_CLIENT_111 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_111_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_111_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_111_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_112 - CAS or consumption cycle count register for client 112.
- ***************************************************************************/
-/* MEMC_DDR_1 :: STAT_CAS_CLIENT_112 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_112_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_112_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_112_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_113 - CAS or consumption cycle count register for client 113.
- ***************************************************************************/
-/* MEMC_DDR_1 :: STAT_CAS_CLIENT_113 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_113_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_113_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_113_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_114 - CAS or consumption cycle count register for client 114.
- ***************************************************************************/
-/* MEMC_DDR_1 :: STAT_CAS_CLIENT_114 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_114_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_114_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_114_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_115 - CAS or consumption cycle count register for client 115.
- ***************************************************************************/
-/* MEMC_DDR_1 :: STAT_CAS_CLIENT_115 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_115_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_115_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_115_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_116 - CAS or consumption cycle count register for client 116.
- ***************************************************************************/
-/* MEMC_DDR_1 :: STAT_CAS_CLIENT_116 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_116_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_116_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_116_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_117 - CAS or consumption cycle count register for client 117.
- ***************************************************************************/
-/* MEMC_DDR_1 :: STAT_CAS_CLIENT_117 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_117_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_117_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_117_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_118 - CAS or consumption cycle count register for client 118.
- ***************************************************************************/
-/* MEMC_DDR_1 :: STAT_CAS_CLIENT_118 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_118_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_118_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_118_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_119 - CAS or consumption cycle count register for client 119.
- ***************************************************************************/
-/* MEMC_DDR_1 :: STAT_CAS_CLIENT_119 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_119_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_119_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_119_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_120 - CAS or consumption cycle count register for client 120.
- ***************************************************************************/
-/* MEMC_DDR_1 :: STAT_CAS_CLIENT_120 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_120_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_120_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_120_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_121 - CAS or consumption cycle count register for client 121.
- ***************************************************************************/
-/* MEMC_DDR_1 :: STAT_CAS_CLIENT_121 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_121_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_121_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_121_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_122 - CAS or consumption cycle count register for client 122.
- ***************************************************************************/
-/* MEMC_DDR_1 :: STAT_CAS_CLIENT_122 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_122_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_122_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_122_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_123 - CAS or consumption cycle count register for client 123.
- ***************************************************************************/
-/* MEMC_DDR_1 :: STAT_CAS_CLIENT_123 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_123_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_123_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_123_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_124 - CAS or consumption cycle count register for client 124.
- ***************************************************************************/
-/* MEMC_DDR_1 :: STAT_CAS_CLIENT_124 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_124_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_124_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_124_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_125 - CAS or consumption cycle count register for client 125.
- ***************************************************************************/
-/* MEMC_DDR_1 :: STAT_CAS_CLIENT_125 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_125_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_125_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_125_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_126 - CAS or consumption cycle count register for client 126.
- ***************************************************************************/
-/* MEMC_DDR_1 :: STAT_CAS_CLIENT_126 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_126_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_126_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_126_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_127 - CAS or consumption cycle count register for client 127.
- ***************************************************************************/
-/* MEMC_DDR_1 :: STAT_CAS_CLIENT_127 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_127_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_127_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_127_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_128 - CAS or consumption cycle count register for client 128.
- ***************************************************************************/
-/* MEMC_DDR_1 :: STAT_CAS_CLIENT_128 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_128_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_128_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_128_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_129 - CAS or consumption cycle count register for client 129.
- ***************************************************************************/
-/* MEMC_DDR_1 :: STAT_CAS_CLIENT_129 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_129_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_129_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_129_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_130 - CAS or consumption cycle count register for client 130.
- ***************************************************************************/
-/* MEMC_DDR_1 :: STAT_CAS_CLIENT_130 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_130_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_130_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_130_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_131 - CAS or consumption cycle count register for client 131.
- ***************************************************************************/
-/* MEMC_DDR_1 :: STAT_CAS_CLIENT_131 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_131_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_131_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_131_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_132 - CAS or consumption cycle count register for client 132.
- ***************************************************************************/
-/* MEMC_DDR_1 :: STAT_CAS_CLIENT_132 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_132_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_132_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_132_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_133 - CAS or consumption cycle count register for client 133.
- ***************************************************************************/
-/* MEMC_DDR_1 :: STAT_CAS_CLIENT_133 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_133_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_133_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_133_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_134 - CAS or consumption cycle count register for client 134.
- ***************************************************************************/
-/* MEMC_DDR_1 :: STAT_CAS_CLIENT_134 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_134_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_134_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_134_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_135 - CAS or consumption cycle count register for client 135.
- ***************************************************************************/
-/* MEMC_DDR_1 :: STAT_CAS_CLIENT_135 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_135_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_135_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_135_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_136 - CAS or consumption cycle count register for client 136.
- ***************************************************************************/
-/* MEMC_DDR_1 :: STAT_CAS_CLIENT_136 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_136_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_136_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_136_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_137 - CAS or consumption cycle count register for client 137.
- ***************************************************************************/
-/* MEMC_DDR_1 :: STAT_CAS_CLIENT_137 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_137_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_137_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_137_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_138 - CAS or consumption cycle count register for client 138.
- ***************************************************************************/
-/* MEMC_DDR_1 :: STAT_CAS_CLIENT_138 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_138_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_138_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_138_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_139 - CAS or consumption cycle count register for client 139.
- ***************************************************************************/
-/* MEMC_DDR_1 :: STAT_CAS_CLIENT_139 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_139_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_139_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_139_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_140 - CAS or consumption cycle count register for client 140.
- ***************************************************************************/
-/* MEMC_DDR_1 :: STAT_CAS_CLIENT_140 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_140_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_140_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_140_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_141 - CAS or consumption cycle count register for client 141.
- ***************************************************************************/
-/* MEMC_DDR_1 :: STAT_CAS_CLIENT_141 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_141_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_141_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_141_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_142 - CAS or consumption cycle count register for client 142.
- ***************************************************************************/
-/* MEMC_DDR_1 :: STAT_CAS_CLIENT_142 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_142_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_142_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_142_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_143 - CAS or consumption cycle count register for client 143.
- ***************************************************************************/
-/* MEMC_DDR_1 :: STAT_CAS_CLIENT_143 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_143_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_143_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_143_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_144 - CAS or consumption cycle count register for client 144.
- ***************************************************************************/
-/* MEMC_DDR_1 :: STAT_CAS_CLIENT_144 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_144_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_144_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_144_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_145 - CAS or consumption cycle count register for client 145.
- ***************************************************************************/
-/* MEMC_DDR_1 :: STAT_CAS_CLIENT_145 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_145_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_145_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_145_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_146 - CAS or consumption cycle count register for client 146.
- ***************************************************************************/
-/* MEMC_DDR_1 :: STAT_CAS_CLIENT_146 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_146_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_146_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_146_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_147 - CAS or consumption cycle count register for client 147.
- ***************************************************************************/
-/* MEMC_DDR_1 :: STAT_CAS_CLIENT_147 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_147_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_147_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_147_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_148 - CAS or consumption cycle count register for client 148.
- ***************************************************************************/
-/* MEMC_DDR_1 :: STAT_CAS_CLIENT_148 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_148_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_148_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_148_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_149 - CAS or consumption cycle count register for client 149.
- ***************************************************************************/
-/* MEMC_DDR_1 :: STAT_CAS_CLIENT_149 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_149_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_149_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_149_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_150 - CAS or consumption cycle count register for client 150.
- ***************************************************************************/
-/* MEMC_DDR_1 :: STAT_CAS_CLIENT_150 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_150_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_150_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_150_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_151 - CAS or consumption cycle count register for client 151.
- ***************************************************************************/
-/* MEMC_DDR_1 :: STAT_CAS_CLIENT_151 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_151_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_151_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_151_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_152 - CAS or consumption cycle count register for client 152.
- ***************************************************************************/
-/* MEMC_DDR_1 :: STAT_CAS_CLIENT_152 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_152_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_152_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_152_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_153 - CAS or consumption cycle count register for client 153.
- ***************************************************************************/
-/* MEMC_DDR_1 :: STAT_CAS_CLIENT_153 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_153_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_153_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_153_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_154 - CAS or consumption cycle count register for client 154.
- ***************************************************************************/
-/* MEMC_DDR_1 :: STAT_CAS_CLIENT_154 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_154_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_154_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_154_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_155 - CAS or consumption cycle count register for client 155.
- ***************************************************************************/
-/* MEMC_DDR_1 :: STAT_CAS_CLIENT_155 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_155_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_155_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_155_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_156 - CAS or consumption cycle count register for client 156.
- ***************************************************************************/
-/* MEMC_DDR_1 :: STAT_CAS_CLIENT_156 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_156_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_156_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_156_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_157 - CAS or consumption cycle count register for client 157.
- ***************************************************************************/
-/* MEMC_DDR_1 :: STAT_CAS_CLIENT_157 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_157_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_157_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_157_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_158 - CAS or consumption cycle count register for client 158.
- ***************************************************************************/
-/* MEMC_DDR_1 :: STAT_CAS_CLIENT_158 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_158_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_158_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_158_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_159 - CAS or consumption cycle count register for client 159.
- ***************************************************************************/
-/* MEMC_DDR_1 :: STAT_CAS_CLIENT_159 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_159_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_159_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_159_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_160 - CAS or consumption cycle count register for client 160.
- ***************************************************************************/
-/* MEMC_DDR_1 :: STAT_CAS_CLIENT_160 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_160_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_160_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_160_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_161 - CAS or consumption cycle count register for client 161.
- ***************************************************************************/
-/* MEMC_DDR_1 :: STAT_CAS_CLIENT_161 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_161_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_161_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_161_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_162 - CAS or consumption cycle count register for client 162.
- ***************************************************************************/
-/* MEMC_DDR_1 :: STAT_CAS_CLIENT_162 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_162_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_162_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_162_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_163 - CAS or consumption cycle count register for client 163.
- ***************************************************************************/
-/* MEMC_DDR_1 :: STAT_CAS_CLIENT_163 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_163_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_163_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_163_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_164 - CAS or consumption cycle count register for client 164.
- ***************************************************************************/
-/* MEMC_DDR_1 :: STAT_CAS_CLIENT_164 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_164_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_164_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_164_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_165 - CAS or consumption cycle count register for client 165.
- ***************************************************************************/
-/* MEMC_DDR_1 :: STAT_CAS_CLIENT_165 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_165_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_165_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_165_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_166 - CAS or consumption cycle count register for client 166.
- ***************************************************************************/
-/* MEMC_DDR_1 :: STAT_CAS_CLIENT_166 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_166_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_166_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_166_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_167 - CAS or consumption cycle count register for client 167.
- ***************************************************************************/
-/* MEMC_DDR_1 :: STAT_CAS_CLIENT_167 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_167_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_167_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_167_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_168 - CAS or consumption cycle count register for client 168.
- ***************************************************************************/
-/* MEMC_DDR_1 :: STAT_CAS_CLIENT_168 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_168_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_168_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_168_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_169 - CAS or consumption cycle count register for client 169.
- ***************************************************************************/
-/* MEMC_DDR_1 :: STAT_CAS_CLIENT_169 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_169_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_169_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_169_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_170 - CAS or consumption cycle count register for client 170.
- ***************************************************************************/
-/* MEMC_DDR_1 :: STAT_CAS_CLIENT_170 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_170_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_170_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_170_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_171 - CAS or consumption cycle count register for client 171.
- ***************************************************************************/
-/* MEMC_DDR_1 :: STAT_CAS_CLIENT_171 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_171_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_171_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_171_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_172 - CAS or consumption cycle count register for client 172.
- ***************************************************************************/
-/* MEMC_DDR_1 :: STAT_CAS_CLIENT_172 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_172_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_172_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_172_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_173 - CAS or consumption cycle count register for client 173.
- ***************************************************************************/
-/* MEMC_DDR_1 :: STAT_CAS_CLIENT_173 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_173_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_173_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_173_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_174 - CAS or consumption cycle count register for client 174.
- ***************************************************************************/
-/* MEMC_DDR_1 :: STAT_CAS_CLIENT_174 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_174_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_174_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_174_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_175 - CAS or consumption cycle count register for client 175.
- ***************************************************************************/
-/* MEMC_DDR_1 :: STAT_CAS_CLIENT_175 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_175_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_175_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_175_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_176 - CAS or consumption cycle count register for client 176.
- ***************************************************************************/
-/* MEMC_DDR_1 :: STAT_CAS_CLIENT_176 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_176_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_176_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_176_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_177 - CAS or consumption cycle count register for client 177.
- ***************************************************************************/
-/* MEMC_DDR_1 :: STAT_CAS_CLIENT_177 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_177_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_177_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_177_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_178 - CAS or consumption cycle count register for client 178.
- ***************************************************************************/
-/* MEMC_DDR_1 :: STAT_CAS_CLIENT_178 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_178_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_178_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_178_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_179 - CAS or consumption cycle count register for client 179.
- ***************************************************************************/
-/* MEMC_DDR_1 :: STAT_CAS_CLIENT_179 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_179_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_179_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_179_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_180 - CAS or consumption cycle count register for client 180.
- ***************************************************************************/
-/* MEMC_DDR_1 :: STAT_CAS_CLIENT_180 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_180_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_180_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_180_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_181 - CAS or consumption cycle count register for client 181.
- ***************************************************************************/
-/* MEMC_DDR_1 :: STAT_CAS_CLIENT_181 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_181_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_181_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_181_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_182 - CAS or consumption cycle count register for client 182.
- ***************************************************************************/
-/* MEMC_DDR_1 :: STAT_CAS_CLIENT_182 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_182_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_182_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_182_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_183 - CAS or consumption cycle count register for client 183.
- ***************************************************************************/
-/* MEMC_DDR_1 :: STAT_CAS_CLIENT_183 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_183_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_183_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_183_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_184 - CAS or consumption cycle count register for client 184.
- ***************************************************************************/
-/* MEMC_DDR_1 :: STAT_CAS_CLIENT_184 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_184_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_184_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_184_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_185 - CAS or consumption cycle count register for client 185.
- ***************************************************************************/
-/* MEMC_DDR_1 :: STAT_CAS_CLIENT_185 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_185_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_185_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_185_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_186 - CAS or consumption cycle count register for client 186.
- ***************************************************************************/
-/* MEMC_DDR_1 :: STAT_CAS_CLIENT_186 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_186_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_186_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_186_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_187 - CAS or consumption cycle count register for client 187.
- ***************************************************************************/
-/* MEMC_DDR_1 :: STAT_CAS_CLIENT_187 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_187_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_187_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_187_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_188 - CAS or consumption cycle count register for client 188.
- ***************************************************************************/
-/* MEMC_DDR_1 :: STAT_CAS_CLIENT_188 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_188_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_188_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_188_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_189 - CAS or consumption cycle count register for client 189.
- ***************************************************************************/
-/* MEMC_DDR_1 :: STAT_CAS_CLIENT_189 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_189_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_189_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_189_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_190 - CAS or consumption cycle count register for client 190.
- ***************************************************************************/
-/* MEMC_DDR_1 :: STAT_CAS_CLIENT_190 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_190_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_190_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_190_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_191 - CAS or consumption cycle count register for client 191.
- ***************************************************************************/
-/* MEMC_DDR_1 :: STAT_CAS_CLIENT_191 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_191_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_191_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_191_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_192 - CAS or consumption cycle count register for client 192.
- ***************************************************************************/
-/* MEMC_DDR_1 :: STAT_CAS_CLIENT_192 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_192_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_192_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_192_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_193 - CAS or consumption cycle count register for client 193.
- ***************************************************************************/
-/* MEMC_DDR_1 :: STAT_CAS_CLIENT_193 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_193_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_193_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_193_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_194 - CAS or consumption cycle count register for client 194.
- ***************************************************************************/
-/* MEMC_DDR_1 :: STAT_CAS_CLIENT_194 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_194_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_194_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_194_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_195 - CAS or consumption cycle count register for client 195.
- ***************************************************************************/
-/* MEMC_DDR_1 :: STAT_CAS_CLIENT_195 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_195_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_195_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_195_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_196 - CAS or consumption cycle count register for client 196.
- ***************************************************************************/
-/* MEMC_DDR_1 :: STAT_CAS_CLIENT_196 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_196_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_196_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_196_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_197 - CAS or consumption cycle count register for client 197.
- ***************************************************************************/
-/* MEMC_DDR_1 :: STAT_CAS_CLIENT_197 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_197_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_197_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_197_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_198 - CAS or consumption cycle count register for client 198.
- ***************************************************************************/
-/* MEMC_DDR_1 :: STAT_CAS_CLIENT_198 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_198_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_198_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_198_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_199 - CAS or consumption cycle count register for client 199.
- ***************************************************************************/
-/* MEMC_DDR_1 :: STAT_CAS_CLIENT_199 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_199_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_199_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_199_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_200 - CAS or consumption cycle count register for client 200.
- ***************************************************************************/
-/* MEMC_DDR_1 :: STAT_CAS_CLIENT_200 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_200_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_200_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_200_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_201 - CAS or consumption cycle count register for client 201.
- ***************************************************************************/
-/* MEMC_DDR_1 :: STAT_CAS_CLIENT_201 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_201_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_201_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_201_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_202 - CAS or consumption cycle count register for client 202.
- ***************************************************************************/
-/* MEMC_DDR_1 :: STAT_CAS_CLIENT_202 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_202_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_202_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_202_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_203 - CAS or consumption cycle count register for client 203.
- ***************************************************************************/
-/* MEMC_DDR_1 :: STAT_CAS_CLIENT_203 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_203_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_203_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_203_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_204 - CAS or consumption cycle count register for client 204.
- ***************************************************************************/
-/* MEMC_DDR_1 :: STAT_CAS_CLIENT_204 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_204_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_204_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_204_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_205 - CAS or consumption cycle count register for client 205.
- ***************************************************************************/
-/* MEMC_DDR_1 :: STAT_CAS_CLIENT_205 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_205_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_205_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_205_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_206 - CAS or consumption cycle count register for client 206.
- ***************************************************************************/
-/* MEMC_DDR_1 :: STAT_CAS_CLIENT_206 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_206_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_206_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_206_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_207 - CAS or consumption cycle count register for client 207.
- ***************************************************************************/
-/* MEMC_DDR_1 :: STAT_CAS_CLIENT_207 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_207_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_207_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_207_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_208 - CAS or consumption cycle count register for client 208.
- ***************************************************************************/
-/* MEMC_DDR_1 :: STAT_CAS_CLIENT_208 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_208_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_208_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_208_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_209 - CAS or consumption cycle count register for client 209.
- ***************************************************************************/
-/* MEMC_DDR_1 :: STAT_CAS_CLIENT_209 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_209_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_209_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_209_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_210 - CAS or consumption cycle count register for client 210.
- ***************************************************************************/
-/* MEMC_DDR_1 :: STAT_CAS_CLIENT_210 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_210_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_210_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_210_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_211 - CAS or consumption cycle count register for client 211.
- ***************************************************************************/
-/* MEMC_DDR_1 :: STAT_CAS_CLIENT_211 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_211_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_211_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_211_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_212 - CAS or consumption cycle count register for client 212.
- ***************************************************************************/
-/* MEMC_DDR_1 :: STAT_CAS_CLIENT_212 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_212_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_212_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_212_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_213 - CAS or consumption cycle count register for client 213.
- ***************************************************************************/
-/* MEMC_DDR_1 :: STAT_CAS_CLIENT_213 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_213_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_213_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_213_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_214 - CAS or consumption cycle count register for client 214.
- ***************************************************************************/
-/* MEMC_DDR_1 :: STAT_CAS_CLIENT_214 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_214_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_214_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_214_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_215 - CAS or consumption cycle count register for client 215.
- ***************************************************************************/
-/* MEMC_DDR_1 :: STAT_CAS_CLIENT_215 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_215_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_215_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_215_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_216 - CAS or consumption cycle count register for client 216.
- ***************************************************************************/
-/* MEMC_DDR_1 :: STAT_CAS_CLIENT_216 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_216_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_216_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_216_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_217 - CAS or consumption cycle count register for client 217.
- ***************************************************************************/
-/* MEMC_DDR_1 :: STAT_CAS_CLIENT_217 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_217_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_217_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_217_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_218 - CAS or consumption cycle count register for client 218.
- ***************************************************************************/
-/* MEMC_DDR_1 :: STAT_CAS_CLIENT_218 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_218_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_218_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_218_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_219 - CAS or consumption cycle count register for client 219.
- ***************************************************************************/
-/* MEMC_DDR_1 :: STAT_CAS_CLIENT_219 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_219_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_219_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_219_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_220 - CAS or consumption cycle count register for client 220.
- ***************************************************************************/
-/* MEMC_DDR_1 :: STAT_CAS_CLIENT_220 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_220_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_220_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_220_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_221 - CAS or consumption cycle count register for client 221.
- ***************************************************************************/
-/* MEMC_DDR_1 :: STAT_CAS_CLIENT_221 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_221_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_221_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_221_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_222 - CAS or consumption cycle count register for client 222.
- ***************************************************************************/
-/* MEMC_DDR_1 :: STAT_CAS_CLIENT_222 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_222_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_222_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_222_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_223 - CAS or consumption cycle count register for client 223.
- ***************************************************************************/
-/* MEMC_DDR_1 :: STAT_CAS_CLIENT_223 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_223_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_223_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_223_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_224 - CAS or consumption cycle count register for client 224.
- ***************************************************************************/
-/* MEMC_DDR_1 :: STAT_CAS_CLIENT_224 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_224_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_224_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_224_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_225 - CAS or consumption cycle count register for client 225.
- ***************************************************************************/
-/* MEMC_DDR_1 :: STAT_CAS_CLIENT_225 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_225_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_225_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_225_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_226 - CAS or consumption cycle count register for client 226.
- ***************************************************************************/
-/* MEMC_DDR_1 :: STAT_CAS_CLIENT_226 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_226_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_226_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_226_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_227 - CAS or consumption cycle count register for client 227.
- ***************************************************************************/
-/* MEMC_DDR_1 :: STAT_CAS_CLIENT_227 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_227_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_227_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_227_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_228 - CAS or consumption cycle count register for client 228.
- ***************************************************************************/
-/* MEMC_DDR_1 :: STAT_CAS_CLIENT_228 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_228_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_228_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_228_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_229 - CAS or consumption cycle count register for client 229.
- ***************************************************************************/
-/* MEMC_DDR_1 :: STAT_CAS_CLIENT_229 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_229_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_229_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_229_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_230 - CAS or consumption cycle count register for client 230.
- ***************************************************************************/
-/* MEMC_DDR_1 :: STAT_CAS_CLIENT_230 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_230_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_230_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_230_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_231 - CAS or consumption cycle count register for client 231.
- ***************************************************************************/
-/* MEMC_DDR_1 :: STAT_CAS_CLIENT_231 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_231_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_231_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_231_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_232 - CAS or consumption cycle count register for client 232.
- ***************************************************************************/
-/* MEMC_DDR_1 :: STAT_CAS_CLIENT_232 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_232_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_232_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_232_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_233 - CAS or consumption cycle count register for client 233.
- ***************************************************************************/
-/* MEMC_DDR_1 :: STAT_CAS_CLIENT_233 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_233_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_233_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_233_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_234 - CAS or consumption cycle count register for client 234.
- ***************************************************************************/
-/* MEMC_DDR_1 :: STAT_CAS_CLIENT_234 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_234_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_234_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_234_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_235 - CAS or consumption cycle count register for client 235.
- ***************************************************************************/
-/* MEMC_DDR_1 :: STAT_CAS_CLIENT_235 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_235_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_235_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_235_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_236 - CAS or consumption cycle count register for client 236.
- ***************************************************************************/
-/* MEMC_DDR_1 :: STAT_CAS_CLIENT_236 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_236_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_236_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_236_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_237 - CAS or consumption cycle count register for client 237.
- ***************************************************************************/
-/* MEMC_DDR_1 :: STAT_CAS_CLIENT_237 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_237_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_237_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_237_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_238 - CAS or consumption cycle count register for client 238.
- ***************************************************************************/
-/* MEMC_DDR_1 :: STAT_CAS_CLIENT_238 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_238_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_238_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_238_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_239 - CAS or consumption cycle count register for client 239.
- ***************************************************************************/
-/* MEMC_DDR_1 :: STAT_CAS_CLIENT_239 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_239_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_239_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_239_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_240 - CAS or consumption cycle count register for client 240.
- ***************************************************************************/
-/* MEMC_DDR_1 :: STAT_CAS_CLIENT_240 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_240_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_240_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_240_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_241 - CAS or consumption cycle count register for client 241.
- ***************************************************************************/
-/* MEMC_DDR_1 :: STAT_CAS_CLIENT_241 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_241_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_241_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_241_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_242 - CAS or consumption cycle count register for client 242.
- ***************************************************************************/
-/* MEMC_DDR_1 :: STAT_CAS_CLIENT_242 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_242_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_242_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_242_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_243 - CAS or consumption cycle count register for client 243.
- ***************************************************************************/
-/* MEMC_DDR_1 :: STAT_CAS_CLIENT_243 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_243_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_243_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_243_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_244 - CAS or consumption cycle count register for client 244.
- ***************************************************************************/
-/* MEMC_DDR_1 :: STAT_CAS_CLIENT_244 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_244_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_244_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_244_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_245 - CAS or consumption cycle count register for client 245.
- ***************************************************************************/
-/* MEMC_DDR_1 :: STAT_CAS_CLIENT_245 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_245_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_245_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_245_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_246 - CAS or consumption cycle count register for client 246.
- ***************************************************************************/
-/* MEMC_DDR_1 :: STAT_CAS_CLIENT_246 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_246_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_246_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_246_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_247 - CAS or consumption cycle count register for client 247.
- ***************************************************************************/
-/* MEMC_DDR_1 :: STAT_CAS_CLIENT_247 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_247_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_247_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_247_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_248 - CAS or consumption cycle count register for client 248.
- ***************************************************************************/
-/* MEMC_DDR_1 :: STAT_CAS_CLIENT_248 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_248_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_248_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_248_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_249 - CAS or consumption cycle count register for client 249.
- ***************************************************************************/
-/* MEMC_DDR_1 :: STAT_CAS_CLIENT_249 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_249_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_249_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_249_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_250 - CAS or consumption cycle count register for client 250.
- ***************************************************************************/
-/* MEMC_DDR_1 :: STAT_CAS_CLIENT_250 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_250_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_250_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_250_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_251 - CAS or consumption cycle count register for client 251.
- ***************************************************************************/
-/* MEMC_DDR_1 :: STAT_CAS_CLIENT_251 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_251_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_251_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_251_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_252 - CAS or consumption cycle count register for client 252.
- ***************************************************************************/
-/* MEMC_DDR_1 :: STAT_CAS_CLIENT_252 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_252_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_252_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_252_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_253 - CAS or consumption cycle count register for client 253.
- ***************************************************************************/
-/* MEMC_DDR_1 :: STAT_CAS_CLIENT_253 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_253_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_253_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_253_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_254 - CAS or consumption cycle count register for client 254.
- ***************************************************************************/
-/* MEMC_DDR_1 :: STAT_CAS_CLIENT_254 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_254_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_254_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_254_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_255 - CAS or consumption cycle count register for client 255.
- ***************************************************************************/
-/* MEMC_DDR_1 :: STAT_CAS_CLIENT_255 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_255_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_255_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_255_COUNT_DEFAULT 0x00000000
-
-#endif /* #ifndef BCHP_MEMC_DDR_1_H__ */
-
-/* End of File */
diff --git a/include/linux/brcmstb/7145a0/bchp_memc_misc_1.h b/include/linux/brcmstb/7145a0/bchp_memc_misc_1.h
deleted file mode 100644
index 375c7b2..0000000
--- a/include/linux/brcmstb/7145a0/bchp_memc_misc_1.h
+++ /dev/null
@@ -1,131 +0,0 @@
-/***************************************************************************
- * Copyright (c) 1999-2013, Broadcom Corporation
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
- *
- * Module Description:
- * DO NOT EDIT THIS FILE DIRECTLY
- *
- * This module was generated magically with RDB from a source description
- * file. You must edit the source file for changes to be made to this file.
- *
- *
- * Date: Generated on Sat Apr 6 03:07:49 2013
- * MD5 Checksum d41d8cd98f00b204e9800998ecf8427e
- *
- * Compiled with: RDB Utility combo_header.pl
- * RDB Parser 3.0
- * unknown unknown
- * Perl Interpreter 5.008008
- * Operating System linux
- *
- * Revision History:
- *
- * $brcm_Log: $
- *
- ***************************************************************************/
-
-#ifndef BCHP_MEMC_MISC_1_H__
-#define BCHP_MEMC_MISC_1_H__
-
-/***************************************************************************
- *MEMC_MISC_1 - 1 MEMSYS Misc (Soft-Resets/Configuration) Registers
- ***************************************************************************/
-#define BCHP_MEMC_MISC_1_SOFT_RESET 0x203c5000 /* MEMC_TOP layout block Soft Reset */
-#define BCHP_MEMC_MISC_1_MEMC_STRAP_DDR_CONFIG 0x203c5004 /* MEMC_STRAP_DDR_CONFIG Control Register */
-#define BCHP_MEMC_MISC_1_MEMC_TOP_TM_CNTRL 0x203c5008 /* MEMC MBIST TM Control Register */
-#define BCHP_MEMC_MISC_1_FSBL_STATE 0x203c500c /* Firmware State Scratchpad */
-#define BCHP_MEMC_MISC_1_SCRATCH_0 0x203c5010 /* Scratch Register */
-
-/***************************************************************************
- *SOFT_RESET - MEMC_TOP layout block Soft Reset
- ***************************************************************************/
-/* MEMC_MISC_1 :: SOFT_RESET :: reserved0 [31:05] */
-#define BCHP_MEMC_MISC_1_SOFT_RESET_reserved0_MASK 0xffffffe0
-#define BCHP_MEMC_MISC_1_SOFT_RESET_reserved0_SHIFT 5
-
-/* MEMC_MISC_1 :: SOFT_RESET :: MEMC_IOBUF_RBUS [04:04] */
-#define BCHP_MEMC_MISC_1_SOFT_RESET_MEMC_IOBUF_RBUS_MASK 0x00000010
-#define BCHP_MEMC_MISC_1_SOFT_RESET_MEMC_IOBUF_RBUS_SHIFT 4
-#define BCHP_MEMC_MISC_1_SOFT_RESET_MEMC_IOBUF_RBUS_DEFAULT 0x00000000
-
-/* MEMC_MISC_1 :: SOFT_RESET :: MEMC_IOBUF [03:03] */
-#define BCHP_MEMC_MISC_1_SOFT_RESET_MEMC_IOBUF_MASK 0x00000008
-#define BCHP_MEMC_MISC_1_SOFT_RESET_MEMC_IOBUF_SHIFT 3
-#define BCHP_MEMC_MISC_1_SOFT_RESET_MEMC_IOBUF_DEFAULT 0x00000000
-
-/* MEMC_MISC_1 :: SOFT_RESET :: MEMC_DRAM_INIT [02:02] */
-#define BCHP_MEMC_MISC_1_SOFT_RESET_MEMC_DRAM_INIT_MASK 0x00000004
-#define BCHP_MEMC_MISC_1_SOFT_RESET_MEMC_DRAM_INIT_SHIFT 2
-#define BCHP_MEMC_MISC_1_SOFT_RESET_MEMC_DRAM_INIT_DEFAULT 0x00000000
-
-/* MEMC_MISC_1 :: SOFT_RESET :: MEMC_RBUS [01:01] */
-#define BCHP_MEMC_MISC_1_SOFT_RESET_MEMC_RBUS_MASK 0x00000002
-#define BCHP_MEMC_MISC_1_SOFT_RESET_MEMC_RBUS_SHIFT 1
-#define BCHP_MEMC_MISC_1_SOFT_RESET_MEMC_RBUS_DEFAULT 0x00000000
-
-/* MEMC_MISC_1 :: SOFT_RESET :: MEMC_CORE [00:00] */
-#define BCHP_MEMC_MISC_1_SOFT_RESET_MEMC_CORE_MASK 0x00000001
-#define BCHP_MEMC_MISC_1_SOFT_RESET_MEMC_CORE_SHIFT 0
-#define BCHP_MEMC_MISC_1_SOFT_RESET_MEMC_CORE_DEFAULT 0x00000000
-
-/***************************************************************************
- *MEMC_STRAP_DDR_CONFIG - MEMC_STRAP_DDR_CONFIG Control Register
- ***************************************************************************/
-/* MEMC_MISC_1 :: MEMC_STRAP_DDR_CONFIG :: reserved_for_eco0 [31:00] */
-#define BCHP_MEMC_MISC_1_MEMC_STRAP_DDR_CONFIG_reserved_for_eco0_MASK 0xffffffff
-#define BCHP_MEMC_MISC_1_MEMC_STRAP_DDR_CONFIG_reserved_for_eco0_SHIFT 0
-#define BCHP_MEMC_MISC_1_MEMC_STRAP_DDR_CONFIG_reserved_for_eco0_DEFAULT 0x00000000
-
-/***************************************************************************
- *MEMC_TOP_TM_CNTRL - MEMC MBIST TM Control Register
- ***************************************************************************/
-/* MEMC_MISC_1 :: MEMC_TOP_TM_CNTRL :: reserved0 [31:06] */
-#define BCHP_MEMC_MISC_1_MEMC_TOP_TM_CNTRL_reserved0_MASK 0xffffffc0
-#define BCHP_MEMC_MISC_1_MEMC_TOP_TM_CNTRL_reserved0_SHIFT 6
-
-/* MEMC_MISC_1 :: MEMC_TOP_TM_CNTRL :: MEMC_PFRI_FIFO_2 [05:04] */
-#define BCHP_MEMC_MISC_1_MEMC_TOP_TM_CNTRL_MEMC_PFRI_FIFO_2_MASK 0x00000030
-#define BCHP_MEMC_MISC_1_MEMC_TOP_TM_CNTRL_MEMC_PFRI_FIFO_2_SHIFT 4
-#define BCHP_MEMC_MISC_1_MEMC_TOP_TM_CNTRL_MEMC_PFRI_FIFO_2_DEFAULT 0x00000000
-
-/* MEMC_MISC_1 :: MEMC_TOP_TM_CNTRL :: MEMC_PFRI_FIFO_1 [03:02] */
-#define BCHP_MEMC_MISC_1_MEMC_TOP_TM_CNTRL_MEMC_PFRI_FIFO_1_MASK 0x0000000c
-#define BCHP_MEMC_MISC_1_MEMC_TOP_TM_CNTRL_MEMC_PFRI_FIFO_1_SHIFT 2
-#define BCHP_MEMC_MISC_1_MEMC_TOP_TM_CNTRL_MEMC_PFRI_FIFO_1_DEFAULT 0x00000000
-
-/* MEMC_MISC_1 :: MEMC_TOP_TM_CNTRL :: MEMC_PFRI_FIFO_0 [01:00] */
-#define BCHP_MEMC_MISC_1_MEMC_TOP_TM_CNTRL_MEMC_PFRI_FIFO_0_MASK 0x00000003
-#define BCHP_MEMC_MISC_1_MEMC_TOP_TM_CNTRL_MEMC_PFRI_FIFO_0_SHIFT 0
-#define BCHP_MEMC_MISC_1_MEMC_TOP_TM_CNTRL_MEMC_PFRI_FIFO_0_DEFAULT 0x00000000
-
-/***************************************************************************
- *FSBL_STATE - Firmware State Scratchpad
- ***************************************************************************/
-/* MEMC_MISC_1 :: FSBL_STATE :: STATE [31:00] */
-#define BCHP_MEMC_MISC_1_FSBL_STATE_STATE_MASK 0xffffffff
-#define BCHP_MEMC_MISC_1_FSBL_STATE_STATE_SHIFT 0
-#define BCHP_MEMC_MISC_1_FSBL_STATE_STATE_DEFAULT 0x00000000
-
-/***************************************************************************
- *SCRATCH_0 - Scratch Register
- ***************************************************************************/
-/* MEMC_MISC_1 :: SCRATCH_0 :: VALUE [31:00] */
-#define BCHP_MEMC_MISC_1_SCRATCH_0_VALUE_MASK 0xffffffff
-#define BCHP_MEMC_MISC_1_SCRATCH_0_VALUE_SHIFT 0
-#define BCHP_MEMC_MISC_1_SCRATCH_0_VALUE_DEFAULT 0x00000000
-
-#endif /* #ifndef BCHP_MEMC_MISC_1_H__ */
-
-/* End of File */
diff --git a/include/linux/brcmstb/7145a0/bchp_moca_hostmisc.h b/include/linux/brcmstb/7145a0/bchp_moca_hostmisc.h
deleted file mode 100644
index 3ff66e4..0000000
--- a/include/linux/brcmstb/7145a0/bchp_moca_hostmisc.h
+++ /dev/null
@@ -1,511 +0,0 @@
-/***************************************************************************
- * Copyright (c) 1999-2013, Broadcom Corporation
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
- *
- * Module Description:
- * DO NOT EDIT THIS FILE DIRECTLY
- *
- * This module was generated magically with RDB from a source description
- * file. You must edit the source file for changes to be made to this file.
- *
- *
- * Date: Generated on Sat Apr 6 03:07:50 2013
- * MD5 Checksum d41d8cd98f00b204e9800998ecf8427e
- *
- * Compiled with: RDB Utility combo_header.pl
- * RDB Parser 3.0
- * unknown unknown
- * Perl Interpreter 5.008008
- * Operating System linux
- *
- * Revision History:
- *
- * $brcm_Log: $
- *
- ***************************************************************************/
-
-#ifndef BCHP_MOCA_HOSTMISC_H__
-#define BCHP_MOCA_HOSTMISC_H__
-
-/***************************************************************************
- *MOCA_HOSTMISC - MOCA_HOSTMISC registers
- ***************************************************************************/
-#define BCHP_MOCA_HOSTMISC_MISC_CTRL 0x07dffd00 /* Moca Software Reset */
-#define BCHP_MOCA_HOSTMISC_SCRATCH 0x07dffd04 /* Moca Scratch Register */
-#define BCHP_MOCA_HOSTMISC_VERSION 0x07dffd08 /* MoCA version register */
-#define BCHP_MOCA_HOSTMISC_H2M_INT_TRIG 0x07dffd0c /* Host-to-MoCA Interrupt Trigger */
-#define BCHP_MOCA_HOSTMISC_WAKEUP 0x07dffd10 /* Host-to-MoCA Wakeup Interrupt */
-#define BCHP_MOCA_HOSTMISC_SUBSYS_CFG 0x07dffd14 /* Moca Subsystem configuration */
-#define BCHP_MOCA_HOSTMISC_H2M_MMP_OUTBOX_0 0x07dffd18 /* Host to MoCA MMP outbox registes , register set index 0. */
-#define BCHP_MOCA_HOSTMISC_H2M_MMP_OUTBOX_1 0x07dffd1c /* Host to MoCA MMP outbox registes , register set index 1. */
-#define BCHP_MOCA_HOSTMISC_H2M_MMP_OUTBOX_2 0x07dffd20 /* Host to MoCA MMP outbox registes , register set index 2. */
-#define BCHP_MOCA_HOSTMISC_H2M_MMP_OUTBOX_3 0x07dffd24 /* Host to MoCA MMP outbox registes , register set index 3. */
-#define BCHP_MOCA_HOSTMISC_H2M_MMP_OUTBOX_4 0x07dffd28 /* Host to MoCA MMP outbox registes , register set index 4. */
-#define BCHP_MOCA_HOSTMISC_H2M_MMP_OUTBOX_5 0x07dffd2c /* Host to MoCA MMP outbox registes , register set index 5. */
-#define BCHP_MOCA_HOSTMISC_H2M_MMP_OUTBOX_6 0x07dffd30 /* Host to MoCA MMP outbox registes , register set index 6. */
-#define BCHP_MOCA_HOSTMISC_H2M_MMP_OUTBOX_7 0x07dffd34 /* Host to MoCA MMP outbox registes , register set index 7. */
-#define BCHP_MOCA_HOSTMISC_H2M_MMP_OUTBOX_8 0x07dffd38 /* Host to MoCA MMP outbox registes , register set index 8. */
-#define BCHP_MOCA_HOSTMISC_H2M_MMP_OUTBOX_9 0x07dffd3c /* Host to MoCA MMP outbox registes , register set index 9. */
-#define BCHP_MOCA_HOSTMISC_H2M_MMP_OUTBOX_10 0x07dffd40 /* Host to MoCA MMP outbox registes , register set index 10. */
-#define BCHP_MOCA_HOSTMISC_H2M_MMP_OUTBOX_11 0x07dffd44 /* Host to MoCA MMP outbox registes , register set index 11. */
-#define BCHP_MOCA_HOSTMISC_H2M_MMP_OUTBOX_12 0x07dffd48 /* Host to MoCA MMP outbox registes , register set index 12. */
-#define BCHP_MOCA_HOSTMISC_H2M_MMP_OUTBOX_13 0x07dffd4c /* Host to MoCA MMP outbox registes , register set index 13. */
-#define BCHP_MOCA_HOSTMISC_H2M_MMP_OUTBOX_14 0x07dffd50 /* Host to MoCA MMP outbox registes , register set index 14. */
-#define BCHP_MOCA_HOSTMISC_H2M_MMP_OUTBOX_15 0x07dffd54 /* Host to MoCA MMP outbox registes , register set index 15. */
-#define BCHP_MOCA_HOSTMISC_M2H_MMP_INBOX_0 0x07dffd58 /* MoCA to Host MMP inbox registers , register set index 0. */
-#define BCHP_MOCA_HOSTMISC_M2H_MMP_INBOX_1 0x07dffd5c /* MoCA to Host MMP inbox registers , register set index 1. */
-#define BCHP_MOCA_HOSTMISC_M2H_MMP_INBOX_2 0x07dffd60 /* MoCA to Host MMP inbox registers , register set index 2. */
-#define BCHP_MOCA_HOSTMISC_M2H_MMP_INBOX_3 0x07dffd64 /* MoCA to Host MMP inbox registers , register set index 3. */
-#define BCHP_MOCA_HOSTMISC_M2H_MMP_INBOX_4 0x07dffd68 /* MoCA to Host MMP inbox registers , register set index 4. */
-#define BCHP_MOCA_HOSTMISC_M2H_MMP_INBOX_5 0x07dffd6c /* MoCA to Host MMP inbox registers , register set index 5. */
-#define BCHP_MOCA_HOSTMISC_M2H_MMP_INBOX_6 0x07dffd70 /* MoCA to Host MMP inbox registers , register set index 6. */
-#define BCHP_MOCA_HOSTMISC_M2H_MMP_INBOX_7 0x07dffd74 /* MoCA to Host MMP inbox registers , register set index 7. */
-#define BCHP_MOCA_HOSTMISC_M2H_MMP_INBOX_8 0x07dffd78 /* MoCA to Host MMP inbox registers , register set index 8. */
-#define BCHP_MOCA_HOSTMISC_M2H_MMP_INBOX_9 0x07dffd7c /* MoCA to Host MMP inbox registers , register set index 9. */
-#define BCHP_MOCA_HOSTMISC_M2H_MMP_INBOX_10 0x07dffd80 /* MoCA to Host MMP inbox registers , register set index 10. */
-#define BCHP_MOCA_HOSTMISC_M2H_MMP_INBOX_11 0x07dffd84 /* MoCA to Host MMP inbox registers , register set index 11. */
-#define BCHP_MOCA_HOSTMISC_M2H_MMP_INBOX_12 0x07dffd88 /* MoCA to Host MMP inbox registers , register set index 12. */
-#define BCHP_MOCA_HOSTMISC_M2H_MMP_INBOX_13 0x07dffd8c /* MoCA to Host MMP inbox registers , register set index 13. */
-#define BCHP_MOCA_HOSTMISC_M2H_MMP_INBOX_14 0x07dffd90 /* MoCA to Host MMP inbox registers , register set index 14. */
-#define BCHP_MOCA_HOSTMISC_M2H_MMP_INBOX_15 0x07dffd94 /* MoCA to Host MMP inbox registers , register set index 15. */
-#define BCHP_MOCA_HOSTMISC_DMPG_CHAINS_STATUS 0x07dffd98 /* "MoCA dynamic memory power gating chain power up (bit per chain),Active when moca_dmpg_gisb_en is high,0: Chain is on,1: Chain is off" */
-#define BCHP_MOCA_HOSTMISC_DMPG_CHAINS_PWR_UP 0x07dffd9c /* "MoCA dynamic memory power gating chain status (bit per chain),0: Power down chain,1: Power up chain" */
-
-/***************************************************************************
- *MISC_CTRL - Moca Software Reset
- ***************************************************************************/
-/* MOCA_HOSTMISC :: MISC_CTRL :: spare_ctrl [31:17] */
-#define BCHP_MOCA_HOSTMISC_MISC_CTRL_spare_ctrl_MASK 0xfffe0000
-#define BCHP_MOCA_HOSTMISC_MISC_CTRL_spare_ctrl_SHIFT 17
-#define BCHP_MOCA_HOSTMISC_MISC_CTRL_spare_ctrl_DEFAULT 0x00007fff
-
-/* MOCA_HOSTMISC :: MISC_CTRL :: moca_dmpg_sel [16:16] */
-#define BCHP_MOCA_HOSTMISC_MISC_CTRL_moca_dmpg_sel_MASK 0x00010000
-#define BCHP_MOCA_HOSTMISC_MISC_CTRL_moca_dmpg_sel_SHIFT 16
-#define BCHP_MOCA_HOSTMISC_MISC_CTRL_moca_dmpg_sel_DEFAULT 0x00000000
-
-/* MOCA_HOSTMISC :: MISC_CTRL :: moca_dmpg_en [15:15] */
-#define BCHP_MOCA_HOSTMISC_MISC_CTRL_moca_dmpg_en_MASK 0x00008000
-#define BCHP_MOCA_HOSTMISC_MISC_CTRL_moca_dmpg_en_SHIFT 15
-#define BCHP_MOCA_HOSTMISC_MISC_CTRL_moca_dmpg_en_DEFAULT 0x00000001
-
-/* MOCA_HOSTMISC :: MISC_CTRL :: spare_status [14:10] */
-#define BCHP_MOCA_HOSTMISC_MISC_CTRL_spare_status_MASK 0x00007c00
-#define BCHP_MOCA_HOSTMISC_MISC_CTRL_spare_status_SHIFT 10
-#define BCHP_MOCA_HOSTMISC_MISC_CTRL_spare_status_DEFAULT 0x0000001f
-
-/* MOCA_HOSTMISC :: MISC_CTRL :: moca_phy1_disable_clk [09:09] */
-#define BCHP_MOCA_HOSTMISC_MISC_CTRL_moca_phy1_disable_clk_MASK 0x00000200
-#define BCHP_MOCA_HOSTMISC_MISC_CTRL_moca_phy1_disable_clk_SHIFT 9
-#define BCHP_MOCA_HOSTMISC_MISC_CTRL_moca_phy1_disable_clk_DEFAULT 0x00000000
-
-/* MOCA_HOSTMISC :: MISC_CTRL :: moca_phy0_disable_clk [08:08] */
-#define BCHP_MOCA_HOSTMISC_MISC_CTRL_moca_phy0_disable_clk_MASK 0x00000100
-#define BCHP_MOCA_HOSTMISC_MISC_CTRL_moca_phy0_disable_clk_SHIFT 8
-#define BCHP_MOCA_HOSTMISC_MISC_CTRL_moca_phy0_disable_clk_DEFAULT 0x00000000
-
-/* MOCA_HOSTMISC :: MISC_CTRL :: moca_disable_clocks [07:07] */
-#define BCHP_MOCA_HOSTMISC_MISC_CTRL_moca_disable_clocks_MASK 0x00000080
-#define BCHP_MOCA_HOSTMISC_MISC_CTRL_moca_disable_clocks_SHIFT 7
-#define BCHP_MOCA_HOSTMISC_MISC_CTRL_moca_disable_clocks_DEFAULT 0x00000000
-
-/* MOCA_HOSTMISC :: MISC_CTRL :: spare_reset [06:06] */
-#define BCHP_MOCA_HOSTMISC_MISC_CTRL_spare_reset_MASK 0x00000040
-#define BCHP_MOCA_HOSTMISC_MISC_CTRL_spare_reset_SHIFT 6
-#define BCHP_MOCA_HOSTMISC_MISC_CTRL_spare_reset_DEFAULT 0x00000001
-
-/* MOCA_HOSTMISC :: MISC_CTRL :: moca_phy1_reset [05:05] */
-#define BCHP_MOCA_HOSTMISC_MISC_CTRL_moca_phy1_reset_MASK 0x00000020
-#define BCHP_MOCA_HOSTMISC_MISC_CTRL_moca_phy1_reset_SHIFT 5
-#define BCHP_MOCA_HOSTMISC_MISC_CTRL_moca_phy1_reset_DEFAULT 0x00000000
-
-/* MOCA_HOSTMISC :: MISC_CTRL :: moca_phy0_reset [04:04] */
-#define BCHP_MOCA_HOSTMISC_MISC_CTRL_moca_phy0_reset_MASK 0x00000010
-#define BCHP_MOCA_HOSTMISC_MISC_CTRL_moca_phy0_reset_SHIFT 4
-#define BCHP_MOCA_HOSTMISC_MISC_CTRL_moca_phy0_reset_DEFAULT 0x00000000
-
-/* MOCA_HOSTMISC :: MISC_CTRL :: moca_gmii_sw_init [03:03] */
-#define BCHP_MOCA_HOSTMISC_MISC_CTRL_moca_gmii_sw_init_MASK 0x00000008
-#define BCHP_MOCA_HOSTMISC_MISC_CTRL_moca_gmii_sw_init_SHIFT 3
-#define BCHP_MOCA_HOSTMISC_MISC_CTRL_moca_gmii_sw_init_DEFAULT 0x00000000
-
-/* MOCA_HOSTMISC :: MISC_CTRL :: moca_cpu_l_reset [02:02] */
-#define BCHP_MOCA_HOSTMISC_MISC_CTRL_moca_cpu_l_reset_MASK 0x00000004
-#define BCHP_MOCA_HOSTMISC_MISC_CTRL_moca_cpu_l_reset_SHIFT 2
-#define BCHP_MOCA_HOSTMISC_MISC_CTRL_moca_cpu_l_reset_DEFAULT 0x00000001
-
-/* MOCA_HOSTMISC :: MISC_CTRL :: moca_sys_reset [01:01] */
-#define BCHP_MOCA_HOSTMISC_MISC_CTRL_moca_sys_reset_MASK 0x00000002
-#define BCHP_MOCA_HOSTMISC_MISC_CTRL_moca_sys_reset_SHIFT 1
-#define BCHP_MOCA_HOSTMISC_MISC_CTRL_moca_sys_reset_DEFAULT 0x00000001
-
-/* MOCA_HOSTMISC :: MISC_CTRL :: moca_cpu_h_reset [00:00] */
-#define BCHP_MOCA_HOSTMISC_MISC_CTRL_moca_cpu_h_reset_MASK 0x00000001
-#define BCHP_MOCA_HOSTMISC_MISC_CTRL_moca_cpu_h_reset_SHIFT 0
-#define BCHP_MOCA_HOSTMISC_MISC_CTRL_moca_cpu_h_reset_DEFAULT 0x00000001
-
-/***************************************************************************
- *SCRATCH - Moca Scratch Register
- ***************************************************************************/
-/* MOCA_HOSTMISC :: SCRATCH :: value [31:00] */
-#define BCHP_MOCA_HOSTMISC_SCRATCH_value_MASK 0xffffffff
-#define BCHP_MOCA_HOSTMISC_SCRATCH_value_SHIFT 0
-#define BCHP_MOCA_HOSTMISC_SCRATCH_value_DEFAULT 0x00000000
-
-/***************************************************************************
- *VERSION - MoCA version register
- ***************************************************************************/
-/* MOCA_HOSTMISC :: VERSION :: moca_id [31:16] */
-#define BCHP_MOCA_HOSTMISC_VERSION_moca_id_MASK 0xffff0000
-#define BCHP_MOCA_HOSTMISC_VERSION_moca_id_SHIFT 16
-#define BCHP_MOCA_HOSTMISC_VERSION_moca_id_DEFAULT 0x00006622
-
-/* MOCA_HOSTMISC :: VERSION :: moca_spec_ver [15:12] */
-#define BCHP_MOCA_HOSTMISC_VERSION_moca_spec_ver_MASK 0x0000f000
-#define BCHP_MOCA_HOSTMISC_VERSION_moca_spec_ver_SHIFT 12
-#define BCHP_MOCA_HOSTMISC_VERSION_moca_spec_ver_DEFAULT 0x00000003
-
-/* MOCA_HOSTMISC :: VERSION :: core_version [11:08] */
-#define BCHP_MOCA_HOSTMISC_VERSION_core_version_MASK 0x00000f00
-#define BCHP_MOCA_HOSTMISC_VERSION_core_version_SHIFT 8
-#define BCHP_MOCA_HOSTMISC_VERSION_core_version_DEFAULT 0x00000000
-
-/* MOCA_HOSTMISC :: VERSION :: core_revision [07:04] */
-#define BCHP_MOCA_HOSTMISC_VERSION_core_revision_MASK 0x000000f0
-#define BCHP_MOCA_HOSTMISC_VERSION_core_revision_SHIFT 4
-#define BCHP_MOCA_HOSTMISC_VERSION_core_revision_DEFAULT 0x00000000
-
-/* MOCA_HOSTMISC :: VERSION :: core_mask [03:00] */
-#define BCHP_MOCA_HOSTMISC_VERSION_core_mask_MASK 0x0000000f
-#define BCHP_MOCA_HOSTMISC_VERSION_core_mask_SHIFT 0
-#define BCHP_MOCA_HOSTMISC_VERSION_core_mask_DEFAULT 0x00000000
-
-/***************************************************************************
- *H2M_INT_TRIG - Host-to-MoCA Interrupt Trigger
- ***************************************************************************/
-/* MOCA_HOSTMISC :: H2M_INT_TRIG :: reserved0 [31:08] */
-#define BCHP_MOCA_HOSTMISC_H2M_INT_TRIG_reserved0_MASK 0xffffff00
-#define BCHP_MOCA_HOSTMISC_H2M_INT_TRIG_reserved0_SHIFT 8
-
-/* MOCA_HOSTMISC :: H2M_INT_TRIG :: INT_TRIG [07:00] */
-#define BCHP_MOCA_HOSTMISC_H2M_INT_TRIG_INT_TRIG_MASK 0x000000ff
-#define BCHP_MOCA_HOSTMISC_H2M_INT_TRIG_INT_TRIG_SHIFT 0
-#define BCHP_MOCA_HOSTMISC_H2M_INT_TRIG_INT_TRIG_DEFAULT 0x00000000
-
-/***************************************************************************
- *WAKEUP - Host-to-MoCA Wakeup Interrupt
- ***************************************************************************/
-/* MOCA_HOSTMISC :: WAKEUP :: reserved0 [31:02] */
-#define BCHP_MOCA_HOSTMISC_WAKEUP_reserved0_MASK 0xfffffffc
-#define BCHP_MOCA_HOSTMISC_WAKEUP_reserved0_SHIFT 2
-
-/* MOCA_HOSTMISC :: WAKEUP :: cpu_l_wakeup_int [01:01] */
-#define BCHP_MOCA_HOSTMISC_WAKEUP_cpu_l_wakeup_int_MASK 0x00000002
-#define BCHP_MOCA_HOSTMISC_WAKEUP_cpu_l_wakeup_int_SHIFT 1
-#define BCHP_MOCA_HOSTMISC_WAKEUP_cpu_l_wakeup_int_DEFAULT 0x00000000
-
-/* MOCA_HOSTMISC :: WAKEUP :: cpu_h_wakeup_int [00:00] */
-#define BCHP_MOCA_HOSTMISC_WAKEUP_cpu_h_wakeup_int_MASK 0x00000001
-#define BCHP_MOCA_HOSTMISC_WAKEUP_cpu_h_wakeup_int_SHIFT 0
-#define BCHP_MOCA_HOSTMISC_WAKEUP_cpu_h_wakeup_int_DEFAULT 0x00000000
-
-/***************************************************************************
- *SUBSYS_CFG - Moca Subsystem configuration
- ***************************************************************************/
-/* MOCA_HOSTMISC :: SUBSYS_CFG :: spare_cfg [31:01] */
-#define BCHP_MOCA_HOSTMISC_SUBSYS_CFG_spare_cfg_MASK 0xfffffffe
-#define BCHP_MOCA_HOSTMISC_SUBSYS_CFG_spare_cfg_SHIFT 1
-#define BCHP_MOCA_HOSTMISC_SUBSYS_CFG_spare_cfg_DEFAULT 0x00000000
-
-/* MOCA_HOSTMISC :: SUBSYS_CFG :: moca_arb_rr_sel [00:00] */
-#define BCHP_MOCA_HOSTMISC_SUBSYS_CFG_moca_arb_rr_sel_MASK 0x00000001
-#define BCHP_MOCA_HOSTMISC_SUBSYS_CFG_moca_arb_rr_sel_SHIFT 0
-#define BCHP_MOCA_HOSTMISC_SUBSYS_CFG_moca_arb_rr_sel_DEFAULT 0x00000001
-
-/***************************************************************************
- *H2M_MMP_OUTBOX_0 - Host to MoCA MMP outbox registes , register set index 0.
- ***************************************************************************/
-/* MOCA_HOSTMISC :: H2M_MMP_OUTBOX_0 :: m2h_mmp_outbox [31:00] */
-#define BCHP_MOCA_HOSTMISC_H2M_MMP_OUTBOX_0_m2h_mmp_outbox_MASK 0xffffffff
-#define BCHP_MOCA_HOSTMISC_H2M_MMP_OUTBOX_0_m2h_mmp_outbox_SHIFT 0
-#define BCHP_MOCA_HOSTMISC_H2M_MMP_OUTBOX_0_m2h_mmp_outbox_DEFAULT 0x00000000
-
-/***************************************************************************
- *H2M_MMP_OUTBOX_1 - Host to MoCA MMP outbox registes , register set index 1.
- ***************************************************************************/
-/* MOCA_HOSTMISC :: H2M_MMP_OUTBOX_1 :: m2h_mmp_outbox [31:00] */
-#define BCHP_MOCA_HOSTMISC_H2M_MMP_OUTBOX_1_m2h_mmp_outbox_MASK 0xffffffff
-#define BCHP_MOCA_HOSTMISC_H2M_MMP_OUTBOX_1_m2h_mmp_outbox_SHIFT 0
-#define BCHP_MOCA_HOSTMISC_H2M_MMP_OUTBOX_1_m2h_mmp_outbox_DEFAULT 0x00000000
-
-/***************************************************************************
- *H2M_MMP_OUTBOX_2 - Host to MoCA MMP outbox registes , register set index 2.
- ***************************************************************************/
-/* MOCA_HOSTMISC :: H2M_MMP_OUTBOX_2 :: m2h_mmp_outbox [31:00] */
-#define BCHP_MOCA_HOSTMISC_H2M_MMP_OUTBOX_2_m2h_mmp_outbox_MASK 0xffffffff
-#define BCHP_MOCA_HOSTMISC_H2M_MMP_OUTBOX_2_m2h_mmp_outbox_SHIFT 0
-#define BCHP_MOCA_HOSTMISC_H2M_MMP_OUTBOX_2_m2h_mmp_outbox_DEFAULT 0x00000000
-
-/***************************************************************************
- *H2M_MMP_OUTBOX_3 - Host to MoCA MMP outbox registes , register set index 3.
- ***************************************************************************/
-/* MOCA_HOSTMISC :: H2M_MMP_OUTBOX_3 :: m2h_mmp_outbox [31:00] */
-#define BCHP_MOCA_HOSTMISC_H2M_MMP_OUTBOX_3_m2h_mmp_outbox_MASK 0xffffffff
-#define BCHP_MOCA_HOSTMISC_H2M_MMP_OUTBOX_3_m2h_mmp_outbox_SHIFT 0
-#define BCHP_MOCA_HOSTMISC_H2M_MMP_OUTBOX_3_m2h_mmp_outbox_DEFAULT 0x00000000
-
-/***************************************************************************
- *H2M_MMP_OUTBOX_4 - Host to MoCA MMP outbox registes , register set index 4.
- ***************************************************************************/
-/* MOCA_HOSTMISC :: H2M_MMP_OUTBOX_4 :: m2h_mmp_outbox [31:00] */
-#define BCHP_MOCA_HOSTMISC_H2M_MMP_OUTBOX_4_m2h_mmp_outbox_MASK 0xffffffff
-#define BCHP_MOCA_HOSTMISC_H2M_MMP_OUTBOX_4_m2h_mmp_outbox_SHIFT 0
-#define BCHP_MOCA_HOSTMISC_H2M_MMP_OUTBOX_4_m2h_mmp_outbox_DEFAULT 0x00000000
-
-/***************************************************************************
- *H2M_MMP_OUTBOX_5 - Host to MoCA MMP outbox registes , register set index 5.
- ***************************************************************************/
-/* MOCA_HOSTMISC :: H2M_MMP_OUTBOX_5 :: m2h_mmp_outbox [31:00] */
-#define BCHP_MOCA_HOSTMISC_H2M_MMP_OUTBOX_5_m2h_mmp_outbox_MASK 0xffffffff
-#define BCHP_MOCA_HOSTMISC_H2M_MMP_OUTBOX_5_m2h_mmp_outbox_SHIFT 0
-#define BCHP_MOCA_HOSTMISC_H2M_MMP_OUTBOX_5_m2h_mmp_outbox_DEFAULT 0x00000000
-
-/***************************************************************************
- *H2M_MMP_OUTBOX_6 - Host to MoCA MMP outbox registes , register set index 6.
- ***************************************************************************/
-/* MOCA_HOSTMISC :: H2M_MMP_OUTBOX_6 :: m2h_mmp_outbox [31:00] */
-#define BCHP_MOCA_HOSTMISC_H2M_MMP_OUTBOX_6_m2h_mmp_outbox_MASK 0xffffffff
-#define BCHP_MOCA_HOSTMISC_H2M_MMP_OUTBOX_6_m2h_mmp_outbox_SHIFT 0
-#define BCHP_MOCA_HOSTMISC_H2M_MMP_OUTBOX_6_m2h_mmp_outbox_DEFAULT 0x00000000
-
-/***************************************************************************
- *H2M_MMP_OUTBOX_7 - Host to MoCA MMP outbox registes , register set index 7.
- ***************************************************************************/
-/* MOCA_HOSTMISC :: H2M_MMP_OUTBOX_7 :: m2h_mmp_outbox [31:00] */
-#define BCHP_MOCA_HOSTMISC_H2M_MMP_OUTBOX_7_m2h_mmp_outbox_MASK 0xffffffff
-#define BCHP_MOCA_HOSTMISC_H2M_MMP_OUTBOX_7_m2h_mmp_outbox_SHIFT 0
-#define BCHP_MOCA_HOSTMISC_H2M_MMP_OUTBOX_7_m2h_mmp_outbox_DEFAULT 0x00000000
-
-/***************************************************************************
- *H2M_MMP_OUTBOX_8 - Host to MoCA MMP outbox registes , register set index 8.
- ***************************************************************************/
-/* MOCA_HOSTMISC :: H2M_MMP_OUTBOX_8 :: m2h_mmp_outbox [31:00] */
-#define BCHP_MOCA_HOSTMISC_H2M_MMP_OUTBOX_8_m2h_mmp_outbox_MASK 0xffffffff
-#define BCHP_MOCA_HOSTMISC_H2M_MMP_OUTBOX_8_m2h_mmp_outbox_SHIFT 0
-#define BCHP_MOCA_HOSTMISC_H2M_MMP_OUTBOX_8_m2h_mmp_outbox_DEFAULT 0x00000000
-
-/***************************************************************************
- *H2M_MMP_OUTBOX_9 - Host to MoCA MMP outbox registes , register set index 9.
- ***************************************************************************/
-/* MOCA_HOSTMISC :: H2M_MMP_OUTBOX_9 :: m2h_mmp_outbox [31:00] */
-#define BCHP_MOCA_HOSTMISC_H2M_MMP_OUTBOX_9_m2h_mmp_outbox_MASK 0xffffffff
-#define BCHP_MOCA_HOSTMISC_H2M_MMP_OUTBOX_9_m2h_mmp_outbox_SHIFT 0
-#define BCHP_MOCA_HOSTMISC_H2M_MMP_OUTBOX_9_m2h_mmp_outbox_DEFAULT 0x00000000
-
-/***************************************************************************
- *H2M_MMP_OUTBOX_10 - Host to MoCA MMP outbox registes , register set index 10.
- ***************************************************************************/
-/* MOCA_HOSTMISC :: H2M_MMP_OUTBOX_10 :: m2h_mmp_outbox [31:00] */
-#define BCHP_MOCA_HOSTMISC_H2M_MMP_OUTBOX_10_m2h_mmp_outbox_MASK 0xffffffff
-#define BCHP_MOCA_HOSTMISC_H2M_MMP_OUTBOX_10_m2h_mmp_outbox_SHIFT 0
-#define BCHP_MOCA_HOSTMISC_H2M_MMP_OUTBOX_10_m2h_mmp_outbox_DEFAULT 0x00000000
-
-/***************************************************************************
- *H2M_MMP_OUTBOX_11 - Host to MoCA MMP outbox registes , register set index 11.
- ***************************************************************************/
-/* MOCA_HOSTMISC :: H2M_MMP_OUTBOX_11 :: m2h_mmp_outbox [31:00] */
-#define BCHP_MOCA_HOSTMISC_H2M_MMP_OUTBOX_11_m2h_mmp_outbox_MASK 0xffffffff
-#define BCHP_MOCA_HOSTMISC_H2M_MMP_OUTBOX_11_m2h_mmp_outbox_SHIFT 0
-#define BCHP_MOCA_HOSTMISC_H2M_MMP_OUTBOX_11_m2h_mmp_outbox_DEFAULT 0x00000000
-
-/***************************************************************************
- *H2M_MMP_OUTBOX_12 - Host to MoCA MMP outbox registes , register set index 12.
- ***************************************************************************/
-/* MOCA_HOSTMISC :: H2M_MMP_OUTBOX_12 :: m2h_mmp_outbox [31:00] */
-#define BCHP_MOCA_HOSTMISC_H2M_MMP_OUTBOX_12_m2h_mmp_outbox_MASK 0xffffffff
-#define BCHP_MOCA_HOSTMISC_H2M_MMP_OUTBOX_12_m2h_mmp_outbox_SHIFT 0
-#define BCHP_MOCA_HOSTMISC_H2M_MMP_OUTBOX_12_m2h_mmp_outbox_DEFAULT 0x00000000
-
-/***************************************************************************
- *H2M_MMP_OUTBOX_13 - Host to MoCA MMP outbox registes , register set index 13.
- ***************************************************************************/
-/* MOCA_HOSTMISC :: H2M_MMP_OUTBOX_13 :: m2h_mmp_outbox [31:00] */
-#define BCHP_MOCA_HOSTMISC_H2M_MMP_OUTBOX_13_m2h_mmp_outbox_MASK 0xffffffff
-#define BCHP_MOCA_HOSTMISC_H2M_MMP_OUTBOX_13_m2h_mmp_outbox_SHIFT 0
-#define BCHP_MOCA_HOSTMISC_H2M_MMP_OUTBOX_13_m2h_mmp_outbox_DEFAULT 0x00000000
-
-/***************************************************************************
- *H2M_MMP_OUTBOX_14 - Host to MoCA MMP outbox registes , register set index 14.
- ***************************************************************************/
-/* MOCA_HOSTMISC :: H2M_MMP_OUTBOX_14 :: m2h_mmp_outbox [31:00] */
-#define BCHP_MOCA_HOSTMISC_H2M_MMP_OUTBOX_14_m2h_mmp_outbox_MASK 0xffffffff
-#define BCHP_MOCA_HOSTMISC_H2M_MMP_OUTBOX_14_m2h_mmp_outbox_SHIFT 0
-#define BCHP_MOCA_HOSTMISC_H2M_MMP_OUTBOX_14_m2h_mmp_outbox_DEFAULT 0x00000000
-
-/***************************************************************************
- *H2M_MMP_OUTBOX_15 - Host to MoCA MMP outbox registes , register set index 15.
- ***************************************************************************/
-/* MOCA_HOSTMISC :: H2M_MMP_OUTBOX_15 :: m2h_mmp_outbox [31:00] */
-#define BCHP_MOCA_HOSTMISC_H2M_MMP_OUTBOX_15_m2h_mmp_outbox_MASK 0xffffffff
-#define BCHP_MOCA_HOSTMISC_H2M_MMP_OUTBOX_15_m2h_mmp_outbox_SHIFT 0
-#define BCHP_MOCA_HOSTMISC_H2M_MMP_OUTBOX_15_m2h_mmp_outbox_DEFAULT 0x00000000
-
-/***************************************************************************
- *M2H_MMP_INBOX_0 - MoCA to Host MMP inbox registers , register set index 0.
- ***************************************************************************/
-/* MOCA_HOSTMISC :: M2H_MMP_INBOX_0 :: h2m_mmp_inbox [31:00] */
-#define BCHP_MOCA_HOSTMISC_M2H_MMP_INBOX_0_h2m_mmp_inbox_MASK 0xffffffff
-#define BCHP_MOCA_HOSTMISC_M2H_MMP_INBOX_0_h2m_mmp_inbox_SHIFT 0
-#define BCHP_MOCA_HOSTMISC_M2H_MMP_INBOX_0_h2m_mmp_inbox_DEFAULT 0x00000000
-
-/***************************************************************************
- *M2H_MMP_INBOX_1 - MoCA to Host MMP inbox registers , register set index 1.
- ***************************************************************************/
-/* MOCA_HOSTMISC :: M2H_MMP_INBOX_1 :: h2m_mmp_inbox [31:00] */
-#define BCHP_MOCA_HOSTMISC_M2H_MMP_INBOX_1_h2m_mmp_inbox_MASK 0xffffffff
-#define BCHP_MOCA_HOSTMISC_M2H_MMP_INBOX_1_h2m_mmp_inbox_SHIFT 0
-#define BCHP_MOCA_HOSTMISC_M2H_MMP_INBOX_1_h2m_mmp_inbox_DEFAULT 0x00000000
-
-/***************************************************************************
- *M2H_MMP_INBOX_2 - MoCA to Host MMP inbox registers , register set index 2.
- ***************************************************************************/
-/* MOCA_HOSTMISC :: M2H_MMP_INBOX_2 :: h2m_mmp_inbox [31:00] */
-#define BCHP_MOCA_HOSTMISC_M2H_MMP_INBOX_2_h2m_mmp_inbox_MASK 0xffffffff
-#define BCHP_MOCA_HOSTMISC_M2H_MMP_INBOX_2_h2m_mmp_inbox_SHIFT 0
-#define BCHP_MOCA_HOSTMISC_M2H_MMP_INBOX_2_h2m_mmp_inbox_DEFAULT 0x00000000
-
-/***************************************************************************
- *M2H_MMP_INBOX_3 - MoCA to Host MMP inbox registers , register set index 3.
- ***************************************************************************/
-/* MOCA_HOSTMISC :: M2H_MMP_INBOX_3 :: h2m_mmp_inbox [31:00] */
-#define BCHP_MOCA_HOSTMISC_M2H_MMP_INBOX_3_h2m_mmp_inbox_MASK 0xffffffff
-#define BCHP_MOCA_HOSTMISC_M2H_MMP_INBOX_3_h2m_mmp_inbox_SHIFT 0
-#define BCHP_MOCA_HOSTMISC_M2H_MMP_INBOX_3_h2m_mmp_inbox_DEFAULT 0x00000000
-
-/***************************************************************************
- *M2H_MMP_INBOX_4 - MoCA to Host MMP inbox registers , register set index 4.
- ***************************************************************************/
-/* MOCA_HOSTMISC :: M2H_MMP_INBOX_4 :: h2m_mmp_inbox [31:00] */
-#define BCHP_MOCA_HOSTMISC_M2H_MMP_INBOX_4_h2m_mmp_inbox_MASK 0xffffffff
-#define BCHP_MOCA_HOSTMISC_M2H_MMP_INBOX_4_h2m_mmp_inbox_SHIFT 0
-#define BCHP_MOCA_HOSTMISC_M2H_MMP_INBOX_4_h2m_mmp_inbox_DEFAULT 0x00000000
-
-/***************************************************************************
- *M2H_MMP_INBOX_5 - MoCA to Host MMP inbox registers , register set index 5.
- ***************************************************************************/
-/* MOCA_HOSTMISC :: M2H_MMP_INBOX_5 :: h2m_mmp_inbox [31:00] */
-#define BCHP_MOCA_HOSTMISC_M2H_MMP_INBOX_5_h2m_mmp_inbox_MASK 0xffffffff
-#define BCHP_MOCA_HOSTMISC_M2H_MMP_INBOX_5_h2m_mmp_inbox_SHIFT 0
-#define BCHP_MOCA_HOSTMISC_M2H_MMP_INBOX_5_h2m_mmp_inbox_DEFAULT 0x00000000
-
-/***************************************************************************
- *M2H_MMP_INBOX_6 - MoCA to Host MMP inbox registers , register set index 6.
- ***************************************************************************/
-/* MOCA_HOSTMISC :: M2H_MMP_INBOX_6 :: h2m_mmp_inbox [31:00] */
-#define BCHP_MOCA_HOSTMISC_M2H_MMP_INBOX_6_h2m_mmp_inbox_MASK 0xffffffff
-#define BCHP_MOCA_HOSTMISC_M2H_MMP_INBOX_6_h2m_mmp_inbox_SHIFT 0
-#define BCHP_MOCA_HOSTMISC_M2H_MMP_INBOX_6_h2m_mmp_inbox_DEFAULT 0x00000000
-
-/***************************************************************************
- *M2H_MMP_INBOX_7 - MoCA to Host MMP inbox registers , register set index 7.
- ***************************************************************************/
-/* MOCA_HOSTMISC :: M2H_MMP_INBOX_7 :: h2m_mmp_inbox [31:00] */
-#define BCHP_MOCA_HOSTMISC_M2H_MMP_INBOX_7_h2m_mmp_inbox_MASK 0xffffffff
-#define BCHP_MOCA_HOSTMISC_M2H_MMP_INBOX_7_h2m_mmp_inbox_SHIFT 0
-#define BCHP_MOCA_HOSTMISC_M2H_MMP_INBOX_7_h2m_mmp_inbox_DEFAULT 0x00000000
-
-/***************************************************************************
- *M2H_MMP_INBOX_8 - MoCA to Host MMP inbox registers , register set index 8.
- ***************************************************************************/
-/* MOCA_HOSTMISC :: M2H_MMP_INBOX_8 :: h2m_mmp_inbox [31:00] */
-#define BCHP_MOCA_HOSTMISC_M2H_MMP_INBOX_8_h2m_mmp_inbox_MASK 0xffffffff
-#define BCHP_MOCA_HOSTMISC_M2H_MMP_INBOX_8_h2m_mmp_inbox_SHIFT 0
-#define BCHP_MOCA_HOSTMISC_M2H_MMP_INBOX_8_h2m_mmp_inbox_DEFAULT 0x00000000
-
-/***************************************************************************
- *M2H_MMP_INBOX_9 - MoCA to Host MMP inbox registers , register set index 9.
- ***************************************************************************/
-/* MOCA_HOSTMISC :: M2H_MMP_INBOX_9 :: h2m_mmp_inbox [31:00] */
-#define BCHP_MOCA_HOSTMISC_M2H_MMP_INBOX_9_h2m_mmp_inbox_MASK 0xffffffff
-#define BCHP_MOCA_HOSTMISC_M2H_MMP_INBOX_9_h2m_mmp_inbox_SHIFT 0
-#define BCHP_MOCA_HOSTMISC_M2H_MMP_INBOX_9_h2m_mmp_inbox_DEFAULT 0x00000000
-
-/***************************************************************************
- *M2H_MMP_INBOX_10 - MoCA to Host MMP inbox registers , register set index 10.
- ***************************************************************************/
-/* MOCA_HOSTMISC :: M2H_MMP_INBOX_10 :: h2m_mmp_inbox [31:00] */
-#define BCHP_MOCA_HOSTMISC_M2H_MMP_INBOX_10_h2m_mmp_inbox_MASK 0xffffffff
-#define BCHP_MOCA_HOSTMISC_M2H_MMP_INBOX_10_h2m_mmp_inbox_SHIFT 0
-#define BCHP_MOCA_HOSTMISC_M2H_MMP_INBOX_10_h2m_mmp_inbox_DEFAULT 0x00000000
-
-/***************************************************************************
- *M2H_MMP_INBOX_11 - MoCA to Host MMP inbox registers , register set index 11.
- ***************************************************************************/
-/* MOCA_HOSTMISC :: M2H_MMP_INBOX_11 :: h2m_mmp_inbox [31:00] */
-#define BCHP_MOCA_HOSTMISC_M2H_MMP_INBOX_11_h2m_mmp_inbox_MASK 0xffffffff
-#define BCHP_MOCA_HOSTMISC_M2H_MMP_INBOX_11_h2m_mmp_inbox_SHIFT 0
-#define BCHP_MOCA_HOSTMISC_M2H_MMP_INBOX_11_h2m_mmp_inbox_DEFAULT 0x00000000
-
-/***************************************************************************
- *M2H_MMP_INBOX_12 - MoCA to Host MMP inbox registers , register set index 12.
- ***************************************************************************/
-/* MOCA_HOSTMISC :: M2H_MMP_INBOX_12 :: h2m_mmp_inbox [31:00] */
-#define BCHP_MOCA_HOSTMISC_M2H_MMP_INBOX_12_h2m_mmp_inbox_MASK 0xffffffff
-#define BCHP_MOCA_HOSTMISC_M2H_MMP_INBOX_12_h2m_mmp_inbox_SHIFT 0
-#define BCHP_MOCA_HOSTMISC_M2H_MMP_INBOX_12_h2m_mmp_inbox_DEFAULT 0x00000000
-
-/***************************************************************************
- *M2H_MMP_INBOX_13 - MoCA to Host MMP inbox registers , register set index 13.
- ***************************************************************************/
-/* MOCA_HOSTMISC :: M2H_MMP_INBOX_13 :: h2m_mmp_inbox [31:00] */
-#define BCHP_MOCA_HOSTMISC_M2H_MMP_INBOX_13_h2m_mmp_inbox_MASK 0xffffffff
-#define BCHP_MOCA_HOSTMISC_M2H_MMP_INBOX_13_h2m_mmp_inbox_SHIFT 0
-#define BCHP_MOCA_HOSTMISC_M2H_MMP_INBOX_13_h2m_mmp_inbox_DEFAULT 0x00000000
-
-/***************************************************************************
- *M2H_MMP_INBOX_14 - MoCA to Host MMP inbox registers , register set index 14.
- ***************************************************************************/
-/* MOCA_HOSTMISC :: M2H_MMP_INBOX_14 :: h2m_mmp_inbox [31:00] */
-#define BCHP_MOCA_HOSTMISC_M2H_MMP_INBOX_14_h2m_mmp_inbox_MASK 0xffffffff
-#define BCHP_MOCA_HOSTMISC_M2H_MMP_INBOX_14_h2m_mmp_inbox_SHIFT 0
-#define BCHP_MOCA_HOSTMISC_M2H_MMP_INBOX_14_h2m_mmp_inbox_DEFAULT 0x00000000
-
-/***************************************************************************
- *M2H_MMP_INBOX_15 - MoCA to Host MMP inbox registers , register set index 15.
- ***************************************************************************/
-/* MOCA_HOSTMISC :: M2H_MMP_INBOX_15 :: h2m_mmp_inbox [31:00] */
-#define BCHP_MOCA_HOSTMISC_M2H_MMP_INBOX_15_h2m_mmp_inbox_MASK 0xffffffff
-#define BCHP_MOCA_HOSTMISC_M2H_MMP_INBOX_15_h2m_mmp_inbox_SHIFT 0
-#define BCHP_MOCA_HOSTMISC_M2H_MMP_INBOX_15_h2m_mmp_inbox_DEFAULT 0x00000000
-
-/***************************************************************************
- *DMPG_CHAINS_STATUS - "MoCA dynamic memory power gating chain power up (bit per chain),Active when moca_dmpg_gisb_en is high,0: Chain is on,1: Chain is off"
- ***************************************************************************/
-/* MOCA_HOSTMISC :: DMPG_CHAINS_STATUS :: dmpg_pda_out_status [31:00] */
-#define BCHP_MOCA_HOSTMISC_DMPG_CHAINS_STATUS_dmpg_pda_out_status_MASK 0xffffffff
-#define BCHP_MOCA_HOSTMISC_DMPG_CHAINS_STATUS_dmpg_pda_out_status_SHIFT 0
-#define BCHP_MOCA_HOSTMISC_DMPG_CHAINS_STATUS_dmpg_pda_out_status_DEFAULT 0x00000000
-
-/***************************************************************************
- *DMPG_CHAINS_PWR_UP - "MoCA dynamic memory power gating chain status (bit per chain),0: Power down chain,1: Power up chain"
- ***************************************************************************/
-/* MOCA_HOSTMISC :: DMPG_CHAINS_PWR_UP :: dmpg_pwr_up [31:00] */
-#define BCHP_MOCA_HOSTMISC_DMPG_CHAINS_PWR_UP_dmpg_pwr_up_MASK 0xffffffff
-#define BCHP_MOCA_HOSTMISC_DMPG_CHAINS_PWR_UP_dmpg_pwr_up_SHIFT 0
-#define BCHP_MOCA_HOSTMISC_DMPG_CHAINS_PWR_UP_dmpg_pwr_up_DEFAULT 0xffffffff
-
-#endif /* #ifndef BCHP_MOCA_HOSTMISC_H__ */
-
-/* End of File */
diff --git a/include/linux/brcmstb/7145a0/bchp_nand.h b/include/linux/brcmstb/7145a0/bchp_nand.h
deleted file mode 100644
index 65f3bc9..0000000
--- a/include/linux/brcmstb/7145a0/bchp_nand.h
+++ /dev/null
@@ -1,3594 +0,0 @@
-/***************************************************************************
- * Copyright (c) 1999-2013, Broadcom Corporation
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
- *
- * Module Description:
- * DO NOT EDIT THIS FILE DIRECTLY
- *
- * This module was generated magically with RDB from a source description
- * file. You must edit the source file for changes to be made to this file.
- *
- *
- * Date: Generated on Sat Apr 6 03:07:49 2013
- * MD5 Checksum d41d8cd98f00b204e9800998ecf8427e
- *
- * Compiled with: RDB Utility combo_header.pl
- * RDB Parser 3.0
- * unknown unknown
- * Perl Interpreter 5.008008
- * Operating System linux
- *
- * Revision History:
- *
- * $brcm_Log: $
- *
- ***************************************************************************/
-
-#ifndef BCHP_NAND_H__
-#define BCHP_NAND_H__
-
-/***************************************************************************
- *NAND - Nand Flash Control Registers
- ***************************************************************************/
-#define BCHP_NAND_REVISION 0x203d2800 /* NAND Revision */
-#define BCHP_NAND_CMD_START 0x203d2804 /* Nand Flash Command Start */
-#define BCHP_NAND_CMD_EXT_ADDRESS 0x203d2808 /* Nand Flash Command Extended Address */
-#define BCHP_NAND_CMD_ADDRESS 0x203d280c /* Nand Flash Command Address */
-#define BCHP_NAND_CMD_END_ADDRESS 0x203d2810 /* Nand Flash Command End Address */
-#define BCHP_NAND_INTFC_STATUS 0x203d2814 /* Nand Flash Interface Status */
-#define BCHP_NAND_CS_NAND_SELECT 0x203d2818 /* Nand Flash EBI CS Select */
-#define BCHP_NAND_CS_NAND_XOR 0x203d281c /* Nand Flash EBI CS XOR masking on CPU address Control */
-#define BCHP_NAND_LL_OP 0x203d2820 /* Nand Flash Low Level Operation */
-#define BCHP_NAND_MPLANE_BASE_EXT_ADDRESS 0x203d2824 /* Nand Flash Multiplane base address */
-#define BCHP_NAND_MPLANE_BASE_ADDRESS 0x203d2828 /* Nand Flash Multiplane base address */
-#define BCHP_NAND_ACC_CONTROL_CS0 0x203d2850 /* Nand Flash Access Control */
-#define BCHP_NAND_CONFIG_CS0 0x203d2854 /* Nand Flash Config */
-#define BCHP_NAND_TIMING_1_CS0 0x203d2858 /* Nand Flash Timing Parameters 1 */
-#define BCHP_NAND_TIMING_2_CS0 0x203d285c /* Nand Flash Timing Parameters 2 */
-#define BCHP_NAND_ACC_CONTROL_CS1 0x203d2860 /* Nand Flash Access Control */
-#define BCHP_NAND_CONFIG_CS1 0x203d2864 /* Nand Flash Config */
-#define BCHP_NAND_TIMING_1_CS1 0x203d2868 /* Nand Flash Timing Parameters 1 */
-#define BCHP_NAND_TIMING_2_CS1 0x203d286c /* Nand Flash Timing Parameters 2 */
-#define BCHP_NAND_ACC_CONTROL_CS2 0x203d2870 /* Nand Flash Access Control */
-#define BCHP_NAND_CONFIG_CS2 0x203d2874 /* Nand Flash Config */
-#define BCHP_NAND_TIMING_1_CS2 0x203d2878 /* Nand Flash Timing Parameters 1 */
-#define BCHP_NAND_TIMING_2_CS2 0x203d287c /* Nand Flash Timing Parameters 2 */
-#define BCHP_NAND_ACC_CONTROL_CS3 0x203d2880 /* Nand Flash Access Control */
-#define BCHP_NAND_CONFIG_CS3 0x203d2884 /* Nand Flash Config */
-#define BCHP_NAND_TIMING_1_CS3 0x203d2888 /* Nand Flash Timing Parameters 1 */
-#define BCHP_NAND_TIMING_2_CS3 0x203d288c /* Nand Flash Timing Parameters 2 */
-#define BCHP_NAND_ACC_CONTROL_CS4 0x203d2890 /* Nand Flash Access Control */
-#define BCHP_NAND_CONFIG_CS4 0x203d2894 /* Nand Flash Config */
-#define BCHP_NAND_TIMING_1_CS4 0x203d2898 /* Nand Flash Timing Parameters 1 */
-#define BCHP_NAND_TIMING_2_CS4 0x203d289c /* Nand Flash Timing Parameters 2 */
-#define BCHP_NAND_ACC_CONTROL_CS5 0x203d28a0 /* Nand Flash Access Control */
-#define BCHP_NAND_CONFIG_CS5 0x203d28a4 /* Nand Flash Config */
-#define BCHP_NAND_TIMING_1_CS5 0x203d28a8 /* Nand Flash Timing Parameters 1 */
-#define BCHP_NAND_TIMING_2_CS5 0x203d28ac /* Nand Flash Timing Parameters 2 */
-#define BCHP_NAND_ACC_CONTROL_CS6 0x203d28b0 /* Nand Flash Access Control */
-#define BCHP_NAND_CONFIG_CS6 0x203d28b4 /* Nand Flash Config */
-#define BCHP_NAND_TIMING_1_CS6 0x203d28b8 /* Nand Flash Timing Parameters 1 */
-#define BCHP_NAND_TIMING_2_CS6 0x203d28bc /* Nand Flash Timing Parameters 2 */
-#define BCHP_NAND_CORR_STAT_THRESHOLD 0x203d28c0 /* Correctable Error Reporting Threshold */
-#define BCHP_NAND_CORR_STAT_THRESHOLD_EXT 0x203d28c4 /* Correctable Error Reporting Threshold */
-#define BCHP_NAND_BLK_WR_PROTECT 0x203d28c8 /* Block Write Protect Enable and Size for EBI_CS0b */
-#define BCHP_NAND_MULTIPLANE_OPCODES_1 0x203d28cc /* Nand Flash Multiplane Customerized Opcodes */
-#define BCHP_NAND_MULTIPLANE_OPCODES_2 0x203d28d0 /* Nand Flash Multiplane Customerized Opcodes */
-#define BCHP_NAND_MULTIPLANE_CTRL 0x203d28d4 /* Nand Flash Multiplane Control */
-#define BCHP_NAND_UNCORR_ERROR_COUNT 0x203d28fc /* Read Uncorrectable Event Count */
-#define BCHP_NAND_CORR_ERROR_COUNT 0x203d2900 /* Read Error Count */
-#define BCHP_NAND_READ_ERROR_COUNT 0x203d2904 /* Read Error Count */
-#define BCHP_NAND_BLOCK_LOCK_STATUS 0x203d2908 /* Nand Flash Block Lock Status */
-#define BCHP_NAND_ECC_CORR_EXT_ADDR 0x203d290c /* ECC Correctable Error Extended Address */
-#define BCHP_NAND_ECC_CORR_ADDR 0x203d2910 /* ECC Correctable Error Address */
-#define BCHP_NAND_ECC_UNC_EXT_ADDR 0x203d2914 /* ECC Uncorrectable Error Extended Address */
-#define BCHP_NAND_ECC_UNC_ADDR 0x203d2918 /* ECC Uncorrectable Error Address */
-#define BCHP_NAND_FLASH_READ_EXT_ADDR 0x203d291c /* Flash Read Data Extended Address */
-#define BCHP_NAND_FLASH_READ_ADDR 0x203d2920 /* Flash Read Data Address */
-#define BCHP_NAND_PROGRAM_PAGE_EXT_ADDR 0x203d2924 /* Page Program Extended Address */
-#define BCHP_NAND_PROGRAM_PAGE_ADDR 0x203d2928 /* Page Program Address */
-#define BCHP_NAND_COPY_BACK_EXT_ADDR 0x203d292c /* Copy Back Extended Address */
-#define BCHP_NAND_COPY_BACK_ADDR 0x203d2930 /* Copy Back Address */
-#define BCHP_NAND_BLOCK_ERASE_EXT_ADDR 0x203d2934 /* Block Erase Extended Address */
-#define BCHP_NAND_BLOCK_ERASE_ADDR 0x203d2938 /* Block Erase Address */
-#define BCHP_NAND_INV_READ_EXT_ADDR 0x203d293c /* Flash Invalid Data Extended Address */
-#define BCHP_NAND_INV_READ_ADDR 0x203d2940 /* Flash Invalid Data Address */
-#define BCHP_NAND_INIT_STATUS 0x203d2944 /* Initialization status */
-#define BCHP_NAND_ONFI_STATUS 0x203d2948 /* ONFI Status */
-#define BCHP_NAND_ONFI_DEBUG_DATA 0x203d294c /* ONFI Debug Data */
-#define BCHP_NAND_SEMAPHORE 0x203d2950 /* Semaphore */
-#define BCHP_NAND_FLASH_DEVICE_ID 0x203d2994 /* Nand Flash Device ID */
-#define BCHP_NAND_FLASH_DEVICE_ID_EXT 0x203d2998 /* Nand Flash Extended Device ID */
-#define BCHP_NAND_LL_RDDATA 0x203d299c /* Nand Flash Low Level Read Data */
-#define BCHP_NAND_SPARE_AREA_READ_OFS_0 0x203d2a00 /* Nand Flash Spare Area Read Bytes 0-3 */
-#define BCHP_NAND_SPARE_AREA_READ_OFS_4 0x203d2a04 /* Nand Flash Spare Area Read Bytes 4-7 */
-#define BCHP_NAND_SPARE_AREA_READ_OFS_8 0x203d2a08 /* Nand Flash Spare Area Read Bytes 8-11 */
-#define BCHP_NAND_SPARE_AREA_READ_OFS_C 0x203d2a0c /* Nand Flash Spare Area Read Bytes 12-15 */
-#define BCHP_NAND_SPARE_AREA_READ_OFS_10 0x203d2a10 /* Nand Flash Spare Area Read Bytes 16-19 */
-#define BCHP_NAND_SPARE_AREA_READ_OFS_14 0x203d2a14 /* Nand Flash Spare Area Read Bytes 20-23 */
-#define BCHP_NAND_SPARE_AREA_READ_OFS_18 0x203d2a18 /* Nand Flash Spare Area Read Bytes 24-27 */
-#define BCHP_NAND_SPARE_AREA_READ_OFS_1C 0x203d2a1c /* Nand Flash Spare Area Read Bytes 28-31 */
-#define BCHP_NAND_SPARE_AREA_READ_OFS_20 0x203d2a20 /* Nand Flash Spare Area Read Bytes 32-35 */
-#define BCHP_NAND_SPARE_AREA_READ_OFS_24 0x203d2a24 /* Nand Flash Spare Area Read Bytes 36-39 */
-#define BCHP_NAND_SPARE_AREA_READ_OFS_28 0x203d2a28 /* Nand Flash Spare Area Read Bytes 40-43 */
-#define BCHP_NAND_SPARE_AREA_READ_OFS_2C 0x203d2a2c /* Nand Flash Spare Area Read Bytes 44-47 */
-#define BCHP_NAND_SPARE_AREA_READ_OFS_30 0x203d2a30 /* Nand Flash Spare Area Read Bytes 48-51 */
-#define BCHP_NAND_SPARE_AREA_READ_OFS_34 0x203d2a34 /* Nand Flash Spare Area Read Bytes 52-55 */
-#define BCHP_NAND_SPARE_AREA_READ_OFS_38 0x203d2a38 /* Nand Flash Spare Area Read Bytes 56-59 */
-#define BCHP_NAND_SPARE_AREA_READ_OFS_3C 0x203d2a3c /* Nand Flash Spare Area Read Bytes 60-63 */
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_0 0x203d2a80 /* Nand Flash Spare Area Write Bytes 0-3 */
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_4 0x203d2a84 /* Nand Flash Spare Area Write Bytes 4-7 */
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_8 0x203d2a88 /* Nand Flash Spare Area Write Bytes 8-11 */
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_C 0x203d2a8c /* Nand Flash Spare Area Write Bytes 12-15 */
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_10 0x203d2a90 /* Nand Flash Spare Area Write Bytes 16-19 */
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_14 0x203d2a94 /* Nand Flash Spare Area Write Bytes 20-23 */
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_18 0x203d2a98 /* Nand Flash Spare Area Write Bytes 24-27 */
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_1C 0x203d2a9c /* Nand Flash Spare Area Write Bytes 28-31 */
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_20 0x203d2aa0 /* Nand Flash Spare Area Write Bytes 32-35 */
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_24 0x203d2aa4 /* Nand Flash Spare Area Write Bytes 36-39 */
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_28 0x203d2aa8 /* Nand Flash Spare Area Write Bytes 40-43 */
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_2C 0x203d2aac /* Nand Flash Spare Area Write Bytes 44-47 */
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_30 0x203d2ab0 /* Nand Flash Spare Area Write Bytes 48-51 */
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_34 0x203d2ab4 /* Nand Flash Spare Area Write Bytes 52-55 */
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_38 0x203d2ab8 /* Nand Flash Spare Area Write Bytes 56-59 */
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_3C 0x203d2abc /* Nand Flash Spare Area Write Bytes 60-63 */
-#define BCHP_NAND_DDR_TIMING 0x203d2ac0 /* Nand Flash DDR TIMING */
-#define BCHP_NAND_DDR_NCDL_CALIB_CTL 0x203d2ac4 /* Nand Flash Calibration Control for Master DLL */
-#define BCHP_NAND_DDR_NCDL_CALIB_PERIOD 0x203d2ac8 /* Nand Flash Calibration Period */
-#define BCHP_NAND_DDR_NCDL_CALIB_STAT 0x203d2acc /* Nand Flash Calibration Status for Master DLL */
-#define BCHP_NAND_DDR_NCDL_MODE 0x203d2ad0 /* Nand Flash NCDL mode for Slave DLLs */
-#define BCHP_NAND_DDR_NCDL_OFFSET 0x203d2ad4 /* Nand Flash NCDL offset for Slave DLLs */
-#define BCHP_NAND_DDR_PHY_CTL 0x203d2ad8 /* Nand Flash DDR PHY CONTROL */
-#define BCHP_NAND_DDR_PHY_BIST_CTL 0x203d2adc /* Nand Flash DDR PHY BIST CONTROL */
-#define BCHP_NAND_DDR_PHY_BIST_STAT 0x203d2ae0 /* Nand Flash DDR PHY BIST STATUS */
-#define BCHP_NAND_DDR_DIAG_STAT0 0x203d2ae4 /* Nand Flash DDR DIAG STATUS0 */
-#define BCHP_NAND_DDR_DIAG_STAT1 0x203d2ae8 /* Nand Flash DDR DIAG STATUS1 */
-
-/***************************************************************************
- *REVISION - NAND Revision
- ***************************************************************************/
-/* NAND :: REVISION :: 8KB_PAGE_SUPPORT [31:31] */
-#define BCHP_NAND_REVISION_8KB_PAGE_SUPPORT_MASK 0x80000000
-#define BCHP_NAND_REVISION_8KB_PAGE_SUPPORT_SHIFT 31
-#define BCHP_NAND_REVISION_8KB_PAGE_SUPPORT_DEFAULT 0x00000001
-
-/* NAND :: REVISION :: reserved0 [30:16] */
-#define BCHP_NAND_REVISION_reserved0_MASK 0x7fff0000
-#define BCHP_NAND_REVISION_reserved0_SHIFT 16
-
-/* NAND :: REVISION :: MAJOR [15:08] */
-#define BCHP_NAND_REVISION_MAJOR_MASK 0x0000ff00
-#define BCHP_NAND_REVISION_MAJOR_SHIFT 8
-#define BCHP_NAND_REVISION_MAJOR_DEFAULT 0x00000007
-
-/* NAND :: REVISION :: MINOR [07:00] */
-#define BCHP_NAND_REVISION_MINOR_MASK 0x000000ff
-#define BCHP_NAND_REVISION_MINOR_SHIFT 0
-#define BCHP_NAND_REVISION_MINOR_DEFAULT 0x00000000
-
-/***************************************************************************
- *CMD_START - Nand Flash Command Start
- ***************************************************************************/
-/* NAND :: CMD_START :: reserved0 [31:05] */
-#define BCHP_NAND_CMD_START_reserved0_MASK 0xffffffe0
-#define BCHP_NAND_CMD_START_reserved0_SHIFT 5
-
-/* NAND :: CMD_START :: OPCODE [04:00] */
-#define BCHP_NAND_CMD_START_OPCODE_MASK 0x0000001f
-#define BCHP_NAND_CMD_START_OPCODE_SHIFT 0
-#define BCHP_NAND_CMD_START_OPCODE_DEFAULT 0x00000000
-#define BCHP_NAND_CMD_START_OPCODE_NULL 0
-#define BCHP_NAND_CMD_START_OPCODE_PAGE_READ 1
-#define BCHP_NAND_CMD_START_OPCODE_SPARE_AREA_READ 2
-#define BCHP_NAND_CMD_START_OPCODE_STATUS_READ 3
-#define BCHP_NAND_CMD_START_OPCODE_PROGRAM_PAGE 4
-#define BCHP_NAND_CMD_START_OPCODE_PROGRAM_SPARE_AREA 5
-#define BCHP_NAND_CMD_START_OPCODE_COPY_BACK 6
-#define BCHP_NAND_CMD_START_OPCODE_DEVICE_ID_READ 7
-#define BCHP_NAND_CMD_START_OPCODE_BLOCK_ERASE 8
-#define BCHP_NAND_CMD_START_OPCODE_FLASH_RESET 9
-#define BCHP_NAND_CMD_START_OPCODE_BLOCKS_LOCK 10
-#define BCHP_NAND_CMD_START_OPCODE_BLOCKS_LOCK_DOWN 11
-#define BCHP_NAND_CMD_START_OPCODE_BLOCKS_UNLOCK 12
-#define BCHP_NAND_CMD_START_OPCODE_READ_BLOCKS_LOCK_STATUS 13
-#define BCHP_NAND_CMD_START_OPCODE_PARAMETER_READ 14
-#define BCHP_NAND_CMD_START_OPCODE_PARAMETER_CHANGE_COL 15
-#define BCHP_NAND_CMD_START_OPCODE_LOW_LEVEL_OP 16
-#define BCHP_NAND_CMD_START_OPCODE_PAGE_READ_MULTI 17
-#define BCHP_NAND_CMD_START_OPCODE_STATUS_READ_MULTI 18
-#define BCHP_NAND_CMD_START_OPCODE_PROGRAM_PAGE_MULTI 19
-#define BCHP_NAND_CMD_START_OPCODE_BLOCK_ERASE_MULTI 21
-
-/***************************************************************************
- *CMD_EXT_ADDRESS - Nand Flash Command Extended Address
- ***************************************************************************/
-/* NAND :: CMD_EXT_ADDRESS :: reserved0 [31:19] */
-#define BCHP_NAND_CMD_EXT_ADDRESS_reserved0_MASK 0xfff80000
-#define BCHP_NAND_CMD_EXT_ADDRESS_reserved0_SHIFT 19
-
-/* NAND :: CMD_EXT_ADDRESS :: CS_SEL [18:16] */
-#define BCHP_NAND_CMD_EXT_ADDRESS_CS_SEL_MASK 0x00070000
-#define BCHP_NAND_CMD_EXT_ADDRESS_CS_SEL_SHIFT 16
-#define BCHP_NAND_CMD_EXT_ADDRESS_CS_SEL_DEFAULT 0x00000000
-
-/* NAND :: CMD_EXT_ADDRESS :: EXT_ADDRESS [15:00] */
-#define BCHP_NAND_CMD_EXT_ADDRESS_EXT_ADDRESS_MASK 0x0000ffff
-#define BCHP_NAND_CMD_EXT_ADDRESS_EXT_ADDRESS_SHIFT 0
-#define BCHP_NAND_CMD_EXT_ADDRESS_EXT_ADDRESS_DEFAULT 0x00000000
-
-/***************************************************************************
- *CMD_ADDRESS - Nand Flash Command Address
- ***************************************************************************/
-/* NAND :: CMD_ADDRESS :: ADDRESS [31:00] */
-#define BCHP_NAND_CMD_ADDRESS_ADDRESS_MASK 0xffffffff
-#define BCHP_NAND_CMD_ADDRESS_ADDRESS_SHIFT 0
-#define BCHP_NAND_CMD_ADDRESS_ADDRESS_DEFAULT 0x00000000
-
-/***************************************************************************
- *CMD_END_ADDRESS - Nand Flash Command End Address
- ***************************************************************************/
-/* NAND :: CMD_END_ADDRESS :: ADDRESS [31:00] */
-#define BCHP_NAND_CMD_END_ADDRESS_ADDRESS_MASK 0xffffffff
-#define BCHP_NAND_CMD_END_ADDRESS_ADDRESS_SHIFT 0
-#define BCHP_NAND_CMD_END_ADDRESS_ADDRESS_DEFAULT 0x00000000
-
-/***************************************************************************
- *INTFC_STATUS - Nand Flash Interface Status
- ***************************************************************************/
-/* NAND :: INTFC_STATUS :: CTLR_READY [31:31] */
-#define BCHP_NAND_INTFC_STATUS_CTLR_READY_MASK 0x80000000
-#define BCHP_NAND_INTFC_STATUS_CTLR_READY_SHIFT 31
-
-/* NAND :: INTFC_STATUS :: FLASH_READY [30:30] */
-#define BCHP_NAND_INTFC_STATUS_FLASH_READY_MASK 0x40000000
-#define BCHP_NAND_INTFC_STATUS_FLASH_READY_SHIFT 30
-
-/* NAND :: INTFC_STATUS :: CACHE_VALID [29:29] */
-#define BCHP_NAND_INTFC_STATUS_CACHE_VALID_MASK 0x20000000
-#define BCHP_NAND_INTFC_STATUS_CACHE_VALID_SHIFT 29
-
-/* NAND :: INTFC_STATUS :: SPARE_AREA_VALID [28:28] */
-#define BCHP_NAND_INTFC_STATUS_SPARE_AREA_VALID_MASK 0x10000000
-#define BCHP_NAND_INTFC_STATUS_SPARE_AREA_VALID_SHIFT 28
-
-/* NAND :: INTFC_STATUS :: ERASED [27:27] */
-#define BCHP_NAND_INTFC_STATUS_ERASED_MASK 0x08000000
-#define BCHP_NAND_INTFC_STATUS_ERASED_SHIFT 27
-
-/* NAND :: INTFC_STATUS :: PLANE_READY [26:26] */
-#define BCHP_NAND_INTFC_STATUS_PLANE_READY_MASK 0x04000000
-#define BCHP_NAND_INTFC_STATUS_PLANE_READY_SHIFT 26
-
-/* NAND :: INTFC_STATUS :: reserved0 [25:08] */
-#define BCHP_NAND_INTFC_STATUS_reserved0_MASK 0x03ffff00
-#define BCHP_NAND_INTFC_STATUS_reserved0_SHIFT 8
-
-/* NAND :: INTFC_STATUS :: FLASH_STATUS [07:00] */
-#define BCHP_NAND_INTFC_STATUS_FLASH_STATUS_MASK 0x000000ff
-#define BCHP_NAND_INTFC_STATUS_FLASH_STATUS_SHIFT 0
-#define BCHP_NAND_INTFC_STATUS_FLASH_STATUS_DEFAULT 0x00000000
-
-/***************************************************************************
- *CS_NAND_SELECT - Nand Flash EBI CS Select
- ***************************************************************************/
-/* NAND :: CS_NAND_SELECT :: CS_LOCK [31:31] */
-#define BCHP_NAND_CS_NAND_SELECT_CS_LOCK_MASK 0x80000000
-#define BCHP_NAND_CS_NAND_SELECT_CS_LOCK_SHIFT 31
-#define BCHP_NAND_CS_NAND_SELECT_CS_LOCK_DEFAULT 0x00000000
-
-/* NAND :: CS_NAND_SELECT :: AUTO_DEVICE_ID_CONFIG [30:30] */
-#define BCHP_NAND_CS_NAND_SELECT_AUTO_DEVICE_ID_CONFIG_MASK 0x40000000
-#define BCHP_NAND_CS_NAND_SELECT_AUTO_DEVICE_ID_CONFIG_SHIFT 30
-
-/* NAND :: CS_NAND_SELECT :: NAND_WP [29:29] */
-#define BCHP_NAND_CS_NAND_SELECT_NAND_WP_MASK 0x20000000
-#define BCHP_NAND_CS_NAND_SELECT_NAND_WP_SHIFT 29
-#define BCHP_NAND_CS_NAND_SELECT_NAND_WP_DEFAULT 0x00000001
-
-/* NAND :: CS_NAND_SELECT :: WR_PROTECT_BLK0 [28:28] */
-#define BCHP_NAND_CS_NAND_SELECT_WR_PROTECT_BLK0_MASK 0x10000000
-#define BCHP_NAND_CS_NAND_SELECT_WR_PROTECT_BLK0_SHIFT 28
-#define BCHP_NAND_CS_NAND_SELECT_WR_PROTECT_BLK0_DEFAULT 0x00000000
-
-/* NAND :: CS_NAND_SELECT :: reserved0 [27:16] */
-#define BCHP_NAND_CS_NAND_SELECT_reserved0_MASK 0x0fff0000
-#define BCHP_NAND_CS_NAND_SELECT_reserved0_SHIFT 16
-
-/* NAND :: CS_NAND_SELECT :: EBI_CS_7_USES_NAND [15:15] */
-#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_7_USES_NAND_MASK 0x00008000
-#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_7_USES_NAND_SHIFT 15
-#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_7_USES_NAND_DEFAULT 0x00000000
-
-/* NAND :: CS_NAND_SELECT :: EBI_CS_6_USES_NAND [14:14] */
-#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_6_USES_NAND_MASK 0x00004000
-#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_6_USES_NAND_SHIFT 14
-#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_6_USES_NAND_DEFAULT 0x00000000
-
-/* NAND :: CS_NAND_SELECT :: EBI_CS_5_USES_NAND [13:13] */
-#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_5_USES_NAND_MASK 0x00002000
-#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_5_USES_NAND_SHIFT 13
-#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_5_USES_NAND_DEFAULT 0x00000000
-
-/* NAND :: CS_NAND_SELECT :: EBI_CS_4_USES_NAND [12:12] */
-#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_4_USES_NAND_MASK 0x00001000
-#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_4_USES_NAND_SHIFT 12
-#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_4_USES_NAND_DEFAULT 0x00000000
-
-/* NAND :: CS_NAND_SELECT :: EBI_CS_3_USES_NAND [11:11] */
-#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_3_USES_NAND_MASK 0x00000800
-#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_3_USES_NAND_SHIFT 11
-#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_3_USES_NAND_DEFAULT 0x00000000
-
-/* NAND :: CS_NAND_SELECT :: EBI_CS_2_USES_NAND [10:10] */
-#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_2_USES_NAND_MASK 0x00000400
-#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_2_USES_NAND_SHIFT 10
-#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_2_USES_NAND_DEFAULT 0x00000000
-
-/* NAND :: CS_NAND_SELECT :: EBI_CS_1_USES_NAND [09:09] */
-#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_1_USES_NAND_MASK 0x00000200
-#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_1_USES_NAND_SHIFT 9
-#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_1_USES_NAND_DEFAULT 0x00000000
-
-/* NAND :: CS_NAND_SELECT :: EBI_CS_0_USES_NAND [08:08] */
-#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_0_USES_NAND_MASK 0x00000100
-#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_0_USES_NAND_SHIFT 8
-
-/* NAND :: CS_NAND_SELECT :: EBI_CS_7_SEL [07:07] */
-#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_7_SEL_MASK 0x00000080
-#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_7_SEL_SHIFT 7
-#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_7_SEL_DEFAULT 0x00000000
-
-/* NAND :: CS_NAND_SELECT :: EBI_CS_6_SEL [06:06] */
-#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_6_SEL_MASK 0x00000040
-#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_6_SEL_SHIFT 6
-#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_6_SEL_DEFAULT 0x00000000
-
-/* NAND :: CS_NAND_SELECT :: EBI_CS_5_SEL [05:05] */
-#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_5_SEL_MASK 0x00000020
-#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_5_SEL_SHIFT 5
-#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_5_SEL_DEFAULT 0x00000000
-
-/* NAND :: CS_NAND_SELECT :: EBI_CS_4_SEL [04:04] */
-#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_4_SEL_MASK 0x00000010
-#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_4_SEL_SHIFT 4
-#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_4_SEL_DEFAULT 0x00000000
-
-/* NAND :: CS_NAND_SELECT :: EBI_CS_3_SEL [03:03] */
-#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_3_SEL_MASK 0x00000008
-#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_3_SEL_SHIFT 3
-#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_3_SEL_DEFAULT 0x00000000
-
-/* NAND :: CS_NAND_SELECT :: EBI_CS_2_SEL [02:02] */
-#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_2_SEL_MASK 0x00000004
-#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_2_SEL_SHIFT 2
-#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_2_SEL_DEFAULT 0x00000000
-
-/* NAND :: CS_NAND_SELECT :: EBI_CS_1_SEL [01:01] */
-#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_1_SEL_MASK 0x00000002
-#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_1_SEL_SHIFT 1
-#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_1_SEL_DEFAULT 0x00000000
-
-/* NAND :: CS_NAND_SELECT :: EBI_CS_0_SEL [00:00] */
-#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_0_SEL_MASK 0x00000001
-#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_0_SEL_SHIFT 0
-
-/***************************************************************************
- *CS_NAND_XOR - Nand Flash EBI CS XOR masking on CPU address Control
- ***************************************************************************/
-/* NAND :: CS_NAND_XOR :: ONLY_BLOCK_0_XOR [31:31] */
-#define BCHP_NAND_CS_NAND_XOR_ONLY_BLOCK_0_XOR_MASK 0x80000000
-#define BCHP_NAND_CS_NAND_XOR_ONLY_BLOCK_0_XOR_SHIFT 31
-#define BCHP_NAND_CS_NAND_XOR_ONLY_BLOCK_0_XOR_DEFAULT 0x00000000
-
-/* NAND :: CS_NAND_XOR :: reserved0 [30:08] */
-#define BCHP_NAND_CS_NAND_XOR_reserved0_MASK 0x7fffff00
-#define BCHP_NAND_CS_NAND_XOR_reserved0_SHIFT 8
-
-/* NAND :: CS_NAND_XOR :: EBI_CS_7_ADDR_XOR [07:07] */
-#define BCHP_NAND_CS_NAND_XOR_EBI_CS_7_ADDR_XOR_MASK 0x00000080
-#define BCHP_NAND_CS_NAND_XOR_EBI_CS_7_ADDR_XOR_SHIFT 7
-#define BCHP_NAND_CS_NAND_XOR_EBI_CS_7_ADDR_XOR_DEFAULT 0x00000000
-
-/* NAND :: CS_NAND_XOR :: EBI_CS_6_ADDR_XOR [06:06] */
-#define BCHP_NAND_CS_NAND_XOR_EBI_CS_6_ADDR_XOR_MASK 0x00000040
-#define BCHP_NAND_CS_NAND_XOR_EBI_CS_6_ADDR_XOR_SHIFT 6
-#define BCHP_NAND_CS_NAND_XOR_EBI_CS_6_ADDR_XOR_DEFAULT 0x00000000
-
-/* NAND :: CS_NAND_XOR :: EBI_CS_5_ADDR_XOR [05:05] */
-#define BCHP_NAND_CS_NAND_XOR_EBI_CS_5_ADDR_XOR_MASK 0x00000020
-#define BCHP_NAND_CS_NAND_XOR_EBI_CS_5_ADDR_XOR_SHIFT 5
-#define BCHP_NAND_CS_NAND_XOR_EBI_CS_5_ADDR_XOR_DEFAULT 0x00000000
-
-/* NAND :: CS_NAND_XOR :: EBI_CS_4_ADDR_XOR [04:04] */
-#define BCHP_NAND_CS_NAND_XOR_EBI_CS_4_ADDR_XOR_MASK 0x00000010
-#define BCHP_NAND_CS_NAND_XOR_EBI_CS_4_ADDR_XOR_SHIFT 4
-#define BCHP_NAND_CS_NAND_XOR_EBI_CS_4_ADDR_XOR_DEFAULT 0x00000000
-
-/* NAND :: CS_NAND_XOR :: EBI_CS_3_ADDR_XOR [03:03] */
-#define BCHP_NAND_CS_NAND_XOR_EBI_CS_3_ADDR_XOR_MASK 0x00000008
-#define BCHP_NAND_CS_NAND_XOR_EBI_CS_3_ADDR_XOR_SHIFT 3
-#define BCHP_NAND_CS_NAND_XOR_EBI_CS_3_ADDR_XOR_DEFAULT 0x00000000
-
-/* NAND :: CS_NAND_XOR :: EBI_CS_2_ADDR_XOR [02:02] */
-#define BCHP_NAND_CS_NAND_XOR_EBI_CS_2_ADDR_XOR_MASK 0x00000004
-#define BCHP_NAND_CS_NAND_XOR_EBI_CS_2_ADDR_XOR_SHIFT 2
-#define BCHP_NAND_CS_NAND_XOR_EBI_CS_2_ADDR_XOR_DEFAULT 0x00000000
-
-/* NAND :: CS_NAND_XOR :: EBI_CS_1_ADDR_XOR [01:01] */
-#define BCHP_NAND_CS_NAND_XOR_EBI_CS_1_ADDR_XOR_MASK 0x00000002
-#define BCHP_NAND_CS_NAND_XOR_EBI_CS_1_ADDR_XOR_SHIFT 1
-#define BCHP_NAND_CS_NAND_XOR_EBI_CS_1_ADDR_XOR_DEFAULT 0x00000000
-
-/* NAND :: CS_NAND_XOR :: EBI_CS_0_ADDR_XOR [00:00] */
-#define BCHP_NAND_CS_NAND_XOR_EBI_CS_0_ADDR_XOR_MASK 0x00000001
-#define BCHP_NAND_CS_NAND_XOR_EBI_CS_0_ADDR_XOR_SHIFT 0
-
-/***************************************************************************
- *LL_OP - Nand Flash Low Level Operation
- ***************************************************************************/
-/* NAND :: LL_OP :: RETURN_IDLE [31:31] */
-#define BCHP_NAND_LL_OP_RETURN_IDLE_MASK 0x80000000
-#define BCHP_NAND_LL_OP_RETURN_IDLE_SHIFT 31
-#define BCHP_NAND_LL_OP_RETURN_IDLE_DEFAULT 0x00000000
-
-/* NAND :: LL_OP :: reserved0 [30:20] */
-#define BCHP_NAND_LL_OP_reserved0_MASK 0x7ff00000
-#define BCHP_NAND_LL_OP_reserved0_SHIFT 20
-
-/* NAND :: LL_OP :: CLE [19:19] */
-#define BCHP_NAND_LL_OP_CLE_MASK 0x00080000
-#define BCHP_NAND_LL_OP_CLE_SHIFT 19
-#define BCHP_NAND_LL_OP_CLE_DEFAULT 0x00000000
-
-/* NAND :: LL_OP :: ALE [18:18] */
-#define BCHP_NAND_LL_OP_ALE_MASK 0x00040000
-#define BCHP_NAND_LL_OP_ALE_SHIFT 18
-#define BCHP_NAND_LL_OP_ALE_DEFAULT 0x00000000
-
-/* NAND :: LL_OP :: WE [17:17] */
-#define BCHP_NAND_LL_OP_WE_MASK 0x00020000
-#define BCHP_NAND_LL_OP_WE_SHIFT 17
-#define BCHP_NAND_LL_OP_WE_DEFAULT 0x00000000
-
-/* NAND :: LL_OP :: RE [16:16] */
-#define BCHP_NAND_LL_OP_RE_MASK 0x00010000
-#define BCHP_NAND_LL_OP_RE_SHIFT 16
-#define BCHP_NAND_LL_OP_RE_DEFAULT 0x00000000
-
-/* NAND :: LL_OP :: DATA [15:00] */
-#define BCHP_NAND_LL_OP_DATA_MASK 0x0000ffff
-#define BCHP_NAND_LL_OP_DATA_SHIFT 0
-#define BCHP_NAND_LL_OP_DATA_DEFAULT 0x00000000
-
-/***************************************************************************
- *MPLANE_BASE_EXT_ADDRESS - Nand Flash Multiplane base address
- ***************************************************************************/
-/* NAND :: MPLANE_BASE_EXT_ADDRESS :: reserved0 [31:16] */
-#define BCHP_NAND_MPLANE_BASE_EXT_ADDRESS_reserved0_MASK 0xffff0000
-#define BCHP_NAND_MPLANE_BASE_EXT_ADDRESS_reserved0_SHIFT 16
-
-/* NAND :: MPLANE_BASE_EXT_ADDRESS :: EXT_ADDRESS [15:00] */
-#define BCHP_NAND_MPLANE_BASE_EXT_ADDRESS_EXT_ADDRESS_MASK 0x0000ffff
-#define BCHP_NAND_MPLANE_BASE_EXT_ADDRESS_EXT_ADDRESS_SHIFT 0
-#define BCHP_NAND_MPLANE_BASE_EXT_ADDRESS_EXT_ADDRESS_DEFAULT 0x00000000
-
-/***************************************************************************
- *MPLANE_BASE_ADDRESS - Nand Flash Multiplane base address
- ***************************************************************************/
-/* NAND :: MPLANE_BASE_ADDRESS :: ADDRESS [31:00] */
-#define BCHP_NAND_MPLANE_BASE_ADDRESS_ADDRESS_MASK 0xffffffff
-#define BCHP_NAND_MPLANE_BASE_ADDRESS_ADDRESS_SHIFT 0
-#define BCHP_NAND_MPLANE_BASE_ADDRESS_ADDRESS_DEFAULT 0x00000000
-
-/***************************************************************************
- *ACC_CONTROL_CS0 - Nand Flash Access Control
- ***************************************************************************/
-/* NAND :: ACC_CONTROL_CS0 :: RD_ECC_EN [31:31] */
-#define BCHP_NAND_ACC_CONTROL_CS0_RD_ECC_EN_MASK 0x80000000
-#define BCHP_NAND_ACC_CONTROL_CS0_RD_ECC_EN_SHIFT 31
-#define BCHP_NAND_ACC_CONTROL_CS0_RD_ECC_EN_DEFAULT 0x00000001
-
-/* NAND :: ACC_CONTROL_CS0 :: WR_ECC_EN [30:30] */
-#define BCHP_NAND_ACC_CONTROL_CS0_WR_ECC_EN_MASK 0x40000000
-#define BCHP_NAND_ACC_CONTROL_CS0_WR_ECC_EN_SHIFT 30
-#define BCHP_NAND_ACC_CONTROL_CS0_WR_ECC_EN_DEFAULT 0x00000001
-
-/* NAND :: ACC_CONTROL_CS0 :: CE_CARE [29:29] */
-#define BCHP_NAND_ACC_CONTROL_CS0_CE_CARE_MASK 0x20000000
-#define BCHP_NAND_ACC_CONTROL_CS0_CE_CARE_SHIFT 29
-#define BCHP_NAND_ACC_CONTROL_CS0_CE_CARE_DEFAULT 0x00000000
-
-/* NAND :: ACC_CONTROL_CS0 :: reserved0 [28:28] */
-#define BCHP_NAND_ACC_CONTROL_CS0_reserved0_MASK 0x10000000
-#define BCHP_NAND_ACC_CONTROL_CS0_reserved0_SHIFT 28
-
-/* NAND :: ACC_CONTROL_CS0 :: RD_ERASED_ECC_EN [27:27] */
-#define BCHP_NAND_ACC_CONTROL_CS0_RD_ERASED_ECC_EN_MASK 0x08000000
-#define BCHP_NAND_ACC_CONTROL_CS0_RD_ERASED_ECC_EN_SHIFT 27
-#define BCHP_NAND_ACC_CONTROL_CS0_RD_ERASED_ECC_EN_DEFAULT 0x00000000
-
-/* NAND :: ACC_CONTROL_CS0 :: PARTIAL_PAGE_EN [26:26] */
-#define BCHP_NAND_ACC_CONTROL_CS0_PARTIAL_PAGE_EN_MASK 0x04000000
-#define BCHP_NAND_ACC_CONTROL_CS0_PARTIAL_PAGE_EN_SHIFT 26
-#define BCHP_NAND_ACC_CONTROL_CS0_PARTIAL_PAGE_EN_DEFAULT 0x00000000
-
-/* NAND :: ACC_CONTROL_CS0 :: WR_PREEMPT_EN [25:25] */
-#define BCHP_NAND_ACC_CONTROL_CS0_WR_PREEMPT_EN_MASK 0x02000000
-#define BCHP_NAND_ACC_CONTROL_CS0_WR_PREEMPT_EN_SHIFT 25
-#define BCHP_NAND_ACC_CONTROL_CS0_WR_PREEMPT_EN_DEFAULT 0x00000001
-
-/* NAND :: ACC_CONTROL_CS0 :: PAGE_HIT_EN [24:24] */
-#define BCHP_NAND_ACC_CONTROL_CS0_PAGE_HIT_EN_MASK 0x01000000
-#define BCHP_NAND_ACC_CONTROL_CS0_PAGE_HIT_EN_SHIFT 24
-#define BCHP_NAND_ACC_CONTROL_CS0_PAGE_HIT_EN_DEFAULT 0x00000001
-
-/* NAND :: ACC_CONTROL_CS0 :: PREFETCH_EN [23:23] */
-#define BCHP_NAND_ACC_CONTROL_CS0_PREFETCH_EN_MASK 0x00800000
-#define BCHP_NAND_ACC_CONTROL_CS0_PREFETCH_EN_SHIFT 23
-#define BCHP_NAND_ACC_CONTROL_CS0_PREFETCH_EN_DEFAULT 0x00000000
-
-/* NAND :: ACC_CONTROL_CS0 :: CACHE_MODE_EN [22:22] */
-#define BCHP_NAND_ACC_CONTROL_CS0_CACHE_MODE_EN_MASK 0x00400000
-#define BCHP_NAND_ACC_CONTROL_CS0_CACHE_MODE_EN_SHIFT 22
-#define BCHP_NAND_ACC_CONTROL_CS0_CACHE_MODE_EN_DEFAULT 0x00000000
-
-/* NAND :: ACC_CONTROL_CS0 :: reserved1 [21:21] */
-#define BCHP_NAND_ACC_CONTROL_CS0_reserved1_MASK 0x00200000
-#define BCHP_NAND_ACC_CONTROL_CS0_reserved1_SHIFT 21
-
-/* NAND :: ACC_CONTROL_CS0 :: ECC_LEVEL [20:16] */
-#define BCHP_NAND_ACC_CONTROL_CS0_ECC_LEVEL_MASK 0x001f0000
-#define BCHP_NAND_ACC_CONTROL_CS0_ECC_LEVEL_SHIFT 16
-#define BCHP_NAND_ACC_CONTROL_CS0_ECC_LEVEL_DEFAULT 0x0000000f
-
-/* NAND :: ACC_CONTROL_CS0 :: reserved2 [15:08] */
-#define BCHP_NAND_ACC_CONTROL_CS0_reserved2_MASK 0x0000ff00
-#define BCHP_NAND_ACC_CONTROL_CS0_reserved2_SHIFT 8
-
-/* NAND :: ACC_CONTROL_CS0 :: SECTOR_SIZE_1K [07:07] */
-#define BCHP_NAND_ACC_CONTROL_CS0_SECTOR_SIZE_1K_MASK 0x00000080
-#define BCHP_NAND_ACC_CONTROL_CS0_SECTOR_SIZE_1K_SHIFT 7
-#define BCHP_NAND_ACC_CONTROL_CS0_SECTOR_SIZE_1K_DEFAULT 0x00000000
-
-/* NAND :: ACC_CONTROL_CS0 :: SPARE_AREA_SIZE [06:00] */
-#define BCHP_NAND_ACC_CONTROL_CS0_SPARE_AREA_SIZE_MASK 0x0000007f
-#define BCHP_NAND_ACC_CONTROL_CS0_SPARE_AREA_SIZE_SHIFT 0
-#define BCHP_NAND_ACC_CONTROL_CS0_SPARE_AREA_SIZE_DEFAULT 0x00000010
-
-/***************************************************************************
- *CONFIG_CS0 - Nand Flash Config
- ***************************************************************************/
-/* NAND :: CONFIG_CS0 :: CONFIG_LOCK [31:31] */
-#define BCHP_NAND_CONFIG_CS0_CONFIG_LOCK_MASK 0x80000000
-#define BCHP_NAND_CONFIG_CS0_CONFIG_LOCK_SHIFT 31
-#define BCHP_NAND_CONFIG_CS0_CONFIG_LOCK_DEFAULT 0x00000000
-
-/* NAND :: CONFIG_CS0 :: BLOCK_SIZE [30:28] */
-#define BCHP_NAND_CONFIG_CS0_BLOCK_SIZE_MASK 0x70000000
-#define BCHP_NAND_CONFIG_CS0_BLOCK_SIZE_SHIFT 28
-#define BCHP_NAND_CONFIG_CS0_BLOCK_SIZE_BK_SIZE_2048KB 6
-#define BCHP_NAND_CONFIG_CS0_BLOCK_SIZE_BK_SIZE_1024KB 5
-#define BCHP_NAND_CONFIG_CS0_BLOCK_SIZE_BK_SIZE_512KB 4
-#define BCHP_NAND_CONFIG_CS0_BLOCK_SIZE_BK_SIZE_256KB 3
-#define BCHP_NAND_CONFIG_CS0_BLOCK_SIZE_BK_SIZE_128KB 2
-#define BCHP_NAND_CONFIG_CS0_BLOCK_SIZE_BK_SIZE_16KB 1
-#define BCHP_NAND_CONFIG_CS0_BLOCK_SIZE_BK_SIZE_8KB 0
-
-/* NAND :: CONFIG_CS0 :: DEVICE_SIZE [27:24] */
-#define BCHP_NAND_CONFIG_CS0_DEVICE_SIZE_MASK 0x0f000000
-#define BCHP_NAND_CONFIG_CS0_DEVICE_SIZE_SHIFT 24
-#define BCHP_NAND_CONFIG_CS0_DEVICE_SIZE_DVC_SIZE_4MB 0
-#define BCHP_NAND_CONFIG_CS0_DEVICE_SIZE_DVC_SIZE_8MB 1
-#define BCHP_NAND_CONFIG_CS0_DEVICE_SIZE_DVC_SIZE_16MB 2
-#define BCHP_NAND_CONFIG_CS0_DEVICE_SIZE_DVC_SIZE_32MB 3
-#define BCHP_NAND_CONFIG_CS0_DEVICE_SIZE_DVC_SIZE_64MB 4
-#define BCHP_NAND_CONFIG_CS0_DEVICE_SIZE_DVC_SIZE_128MB 5
-#define BCHP_NAND_CONFIG_CS0_DEVICE_SIZE_DVC_SIZE_256MB 6
-#define BCHP_NAND_CONFIG_CS0_DEVICE_SIZE_DVC_SIZE_512MB 7
-#define BCHP_NAND_CONFIG_CS0_DEVICE_SIZE_DVC_SIZE_1GB 8
-#define BCHP_NAND_CONFIG_CS0_DEVICE_SIZE_DVC_SIZE_2GB 9
-#define BCHP_NAND_CONFIG_CS0_DEVICE_SIZE_DVC_SIZE_4GB 10
-#define BCHP_NAND_CONFIG_CS0_DEVICE_SIZE_DVC_SIZE_8GB 11
-#define BCHP_NAND_CONFIG_CS0_DEVICE_SIZE_DVC_SIZE_16GB 12
-#define BCHP_NAND_CONFIG_CS0_DEVICE_SIZE_DVC_SIZE_32GB 13
-#define BCHP_NAND_CONFIG_CS0_DEVICE_SIZE_DVC_SIZE_64GB 14
-#define BCHP_NAND_CONFIG_CS0_DEVICE_SIZE_DVC_SIZE_128GB 15
-
-/* NAND :: CONFIG_CS0 :: DEVICE_WIDTH [23:23] */
-#define BCHP_NAND_CONFIG_CS0_DEVICE_WIDTH_MASK 0x00800000
-#define BCHP_NAND_CONFIG_CS0_DEVICE_WIDTH_SHIFT 23
-#define BCHP_NAND_CONFIG_CS0_DEVICE_WIDTH_DVC_WIDTH_8 0
-#define BCHP_NAND_CONFIG_CS0_DEVICE_WIDTH_DVC_WIDTH_16 1
-
-/* NAND :: CONFIG_CS0 :: reserved0 [22:22] */
-#define BCHP_NAND_CONFIG_CS0_reserved0_MASK 0x00400000
-#define BCHP_NAND_CONFIG_CS0_reserved0_SHIFT 22
-
-/* NAND :: CONFIG_CS0 :: PAGE_SIZE [21:20] */
-#define BCHP_NAND_CONFIG_CS0_PAGE_SIZE_MASK 0x00300000
-#define BCHP_NAND_CONFIG_CS0_PAGE_SIZE_SHIFT 20
-#define BCHP_NAND_CONFIG_CS0_PAGE_SIZE_PG_SIZE_512 0
-#define BCHP_NAND_CONFIG_CS0_PAGE_SIZE_PG_SIZE_2KB 1
-#define BCHP_NAND_CONFIG_CS0_PAGE_SIZE_PG_SIZE_4KB 2
-#define BCHP_NAND_CONFIG_CS0_PAGE_SIZE_PG_SIZE_8KB 3
-
-/* NAND :: CONFIG_CS0 :: reserved1 [19:19] */
-#define BCHP_NAND_CONFIG_CS0_reserved1_MASK 0x00080000
-#define BCHP_NAND_CONFIG_CS0_reserved1_SHIFT 19
-
-/* NAND :: CONFIG_CS0 :: FUL_ADR_BYTES [18:16] */
-#define BCHP_NAND_CONFIG_CS0_FUL_ADR_BYTES_MASK 0x00070000
-#define BCHP_NAND_CONFIG_CS0_FUL_ADR_BYTES_SHIFT 16
-
-/* NAND :: CONFIG_CS0 :: reserved2 [15:15] */
-#define BCHP_NAND_CONFIG_CS0_reserved2_MASK 0x00008000
-#define BCHP_NAND_CONFIG_CS0_reserved2_SHIFT 15
-
-/* NAND :: CONFIG_CS0 :: COL_ADR_BYTES [14:12] */
-#define BCHP_NAND_CONFIG_CS0_COL_ADR_BYTES_MASK 0x00007000
-#define BCHP_NAND_CONFIG_CS0_COL_ADR_BYTES_SHIFT 12
-
-/* NAND :: CONFIG_CS0 :: reserved3 [11:11] */
-#define BCHP_NAND_CONFIG_CS0_reserved3_MASK 0x00000800
-#define BCHP_NAND_CONFIG_CS0_reserved3_SHIFT 11
-
-/* NAND :: CONFIG_CS0 :: BLK_ADR_BYTES [10:08] */
-#define BCHP_NAND_CONFIG_CS0_BLK_ADR_BYTES_MASK 0x00000700
-#define BCHP_NAND_CONFIG_CS0_BLK_ADR_BYTES_SHIFT 8
-
-/* NAND :: CONFIG_CS0 :: reserved4 [07:00] */
-#define BCHP_NAND_CONFIG_CS0_reserved4_MASK 0x000000ff
-#define BCHP_NAND_CONFIG_CS0_reserved4_SHIFT 0
-
-/***************************************************************************
- *TIMING_1_CS0 - Nand Flash Timing Parameters 1
- ***************************************************************************/
-/* NAND :: TIMING_1_CS0 :: tWP [31:28] */
-#define BCHP_NAND_TIMING_1_CS0_tWP_MASK 0xf0000000
-#define BCHP_NAND_TIMING_1_CS0_tWP_SHIFT 28
-#define BCHP_NAND_TIMING_1_CS0_tWP_DEFAULT 0x00000006
-
-/* NAND :: TIMING_1_CS0 :: tWH [27:24] */
-#define BCHP_NAND_TIMING_1_CS0_tWH_MASK 0x0f000000
-#define BCHP_NAND_TIMING_1_CS0_tWH_SHIFT 24
-#define BCHP_NAND_TIMING_1_CS0_tWH_DEFAULT 0x00000005
-
-/* NAND :: TIMING_1_CS0 :: tRP [23:20] */
-#define BCHP_NAND_TIMING_1_CS0_tRP_MASK 0x00f00000
-#define BCHP_NAND_TIMING_1_CS0_tRP_SHIFT 20
-#define BCHP_NAND_TIMING_1_CS0_tRP_DEFAULT 0x00000007
-
-/* NAND :: TIMING_1_CS0 :: tREH [19:16] */
-#define BCHP_NAND_TIMING_1_CS0_tREH_MASK 0x000f0000
-#define BCHP_NAND_TIMING_1_CS0_tREH_SHIFT 16
-#define BCHP_NAND_TIMING_1_CS0_tREH_DEFAULT 0x00000004
-
-/* NAND :: TIMING_1_CS0 :: tCS [15:12] */
-#define BCHP_NAND_TIMING_1_CS0_tCS_MASK 0x0000f000
-#define BCHP_NAND_TIMING_1_CS0_tCS_SHIFT 12
-#define BCHP_NAND_TIMING_1_CS0_tCS_DEFAULT 0x00000008
-
-/* NAND :: TIMING_1_CS0 :: tCLH [11:08] */
-#define BCHP_NAND_TIMING_1_CS0_tCLH_MASK 0x00000f00
-#define BCHP_NAND_TIMING_1_CS0_tCLH_SHIFT 8
-#define BCHP_NAND_TIMING_1_CS0_tCLH_DEFAULT 0x00000004
-
-/* NAND :: TIMING_1_CS0 :: tALH [07:04] */
-#define BCHP_NAND_TIMING_1_CS0_tALH_MASK 0x000000f0
-#define BCHP_NAND_TIMING_1_CS0_tALH_SHIFT 4
-#define BCHP_NAND_TIMING_1_CS0_tALH_DEFAULT 0x00000005
-
-/* NAND :: TIMING_1_CS0 :: tADL [03:00] */
-#define BCHP_NAND_TIMING_1_CS0_tADL_MASK 0x0000000f
-#define BCHP_NAND_TIMING_1_CS0_tADL_SHIFT 0
-#define BCHP_NAND_TIMING_1_CS0_tADL_DEFAULT 0x0000000b
-
-/***************************************************************************
- *TIMING_2_CS0 - Nand Flash Timing Parameters 2
- ***************************************************************************/
-/* NAND :: TIMING_2_CS0 :: CLK_SELECT [31:31] */
-#define BCHP_NAND_TIMING_2_CS0_CLK_SELECT_MASK 0x80000000
-#define BCHP_NAND_TIMING_2_CS0_CLK_SELECT_SHIFT 31
-#define BCHP_NAND_TIMING_2_CS0_CLK_SELECT_DEFAULT 0x00000000
-#define BCHP_NAND_TIMING_2_CS0_CLK_SELECT_CLK_108 0
-#define BCHP_NAND_TIMING_2_CS0_CLK_SELECT_CLK_216 1
-
-/* NAND :: TIMING_2_CS0 :: reserved0 [30:13] */
-#define BCHP_NAND_TIMING_2_CS0_reserved0_MASK 0x7fffe000
-#define BCHP_NAND_TIMING_2_CS0_reserved0_SHIFT 13
-
-/* NAND :: TIMING_2_CS0 :: tWB [12:09] */
-#define BCHP_NAND_TIMING_2_CS0_tWB_MASK 0x00001e00
-#define BCHP_NAND_TIMING_2_CS0_tWB_SHIFT 9
-#define BCHP_NAND_TIMING_2_CS0_tWB_DEFAULT 0x0000000f
-
-/* NAND :: TIMING_2_CS0 :: tWHR [08:04] */
-#define BCHP_NAND_TIMING_2_CS0_tWHR_MASK 0x000001f0
-#define BCHP_NAND_TIMING_2_CS0_tWHR_SHIFT 4
-#define BCHP_NAND_TIMING_2_CS0_tWHR_DEFAULT 0x00000009
-
-/* NAND :: TIMING_2_CS0 :: tREAD [03:00] */
-#define BCHP_NAND_TIMING_2_CS0_tREAD_MASK 0x0000000f
-#define BCHP_NAND_TIMING_2_CS0_tREAD_SHIFT 0
-#define BCHP_NAND_TIMING_2_CS0_tREAD_DEFAULT 0x00000006
-
-/***************************************************************************
- *ACC_CONTROL_CS1 - Nand Flash Access Control
- ***************************************************************************/
-/* NAND :: ACC_CONTROL_CS1 :: RD_ECC_EN [31:31] */
-#define BCHP_NAND_ACC_CONTROL_CS1_RD_ECC_EN_MASK 0x80000000
-#define BCHP_NAND_ACC_CONTROL_CS1_RD_ECC_EN_SHIFT 31
-#define BCHP_NAND_ACC_CONTROL_CS1_RD_ECC_EN_DEFAULT 0x00000001
-
-/* NAND :: ACC_CONTROL_CS1 :: WR_ECC_EN [30:30] */
-#define BCHP_NAND_ACC_CONTROL_CS1_WR_ECC_EN_MASK 0x40000000
-#define BCHP_NAND_ACC_CONTROL_CS1_WR_ECC_EN_SHIFT 30
-#define BCHP_NAND_ACC_CONTROL_CS1_WR_ECC_EN_DEFAULT 0x00000001
-
-/* NAND :: ACC_CONTROL_CS1 :: CE_CARE [29:29] */
-#define BCHP_NAND_ACC_CONTROL_CS1_CE_CARE_MASK 0x20000000
-#define BCHP_NAND_ACC_CONTROL_CS1_CE_CARE_SHIFT 29
-#define BCHP_NAND_ACC_CONTROL_CS1_CE_CARE_DEFAULT 0x00000000
-
-/* NAND :: ACC_CONTROL_CS1 :: reserved0 [28:28] */
-#define BCHP_NAND_ACC_CONTROL_CS1_reserved0_MASK 0x10000000
-#define BCHP_NAND_ACC_CONTROL_CS1_reserved0_SHIFT 28
-
-/* NAND :: ACC_CONTROL_CS1 :: RD_ERASED_ECC_EN [27:27] */
-#define BCHP_NAND_ACC_CONTROL_CS1_RD_ERASED_ECC_EN_MASK 0x08000000
-#define BCHP_NAND_ACC_CONTROL_CS1_RD_ERASED_ECC_EN_SHIFT 27
-#define BCHP_NAND_ACC_CONTROL_CS1_RD_ERASED_ECC_EN_DEFAULT 0x00000000
-
-/* NAND :: ACC_CONTROL_CS1 :: PARTIAL_PAGE_EN [26:26] */
-#define BCHP_NAND_ACC_CONTROL_CS1_PARTIAL_PAGE_EN_MASK 0x04000000
-#define BCHP_NAND_ACC_CONTROL_CS1_PARTIAL_PAGE_EN_SHIFT 26
-#define BCHP_NAND_ACC_CONTROL_CS1_PARTIAL_PAGE_EN_DEFAULT 0x00000000
-
-/* NAND :: ACC_CONTROL_CS1 :: WR_PREEMPT_EN [25:25] */
-#define BCHP_NAND_ACC_CONTROL_CS1_WR_PREEMPT_EN_MASK 0x02000000
-#define BCHP_NAND_ACC_CONTROL_CS1_WR_PREEMPT_EN_SHIFT 25
-#define BCHP_NAND_ACC_CONTROL_CS1_WR_PREEMPT_EN_DEFAULT 0x00000001
-
-/* NAND :: ACC_CONTROL_CS1 :: PAGE_HIT_EN [24:24] */
-#define BCHP_NAND_ACC_CONTROL_CS1_PAGE_HIT_EN_MASK 0x01000000
-#define BCHP_NAND_ACC_CONTROL_CS1_PAGE_HIT_EN_SHIFT 24
-#define BCHP_NAND_ACC_CONTROL_CS1_PAGE_HIT_EN_DEFAULT 0x00000001
-
-/* NAND :: ACC_CONTROL_CS1 :: PREFETCH_EN [23:23] */
-#define BCHP_NAND_ACC_CONTROL_CS1_PREFETCH_EN_MASK 0x00800000
-#define BCHP_NAND_ACC_CONTROL_CS1_PREFETCH_EN_SHIFT 23
-#define BCHP_NAND_ACC_CONTROL_CS1_PREFETCH_EN_DEFAULT 0x00000000
-
-/* NAND :: ACC_CONTROL_CS1 :: CACHE_MODE_EN [22:22] */
-#define BCHP_NAND_ACC_CONTROL_CS1_CACHE_MODE_EN_MASK 0x00400000
-#define BCHP_NAND_ACC_CONTROL_CS1_CACHE_MODE_EN_SHIFT 22
-#define BCHP_NAND_ACC_CONTROL_CS1_CACHE_MODE_EN_DEFAULT 0x00000000
-
-/* NAND :: ACC_CONTROL_CS1 :: reserved1 [21:21] */
-#define BCHP_NAND_ACC_CONTROL_CS1_reserved1_MASK 0x00200000
-#define BCHP_NAND_ACC_CONTROL_CS1_reserved1_SHIFT 21
-
-/* NAND :: ACC_CONTROL_CS1 :: ECC_LEVEL [20:16] */
-#define BCHP_NAND_ACC_CONTROL_CS1_ECC_LEVEL_MASK 0x001f0000
-#define BCHP_NAND_ACC_CONTROL_CS1_ECC_LEVEL_SHIFT 16
-#define BCHP_NAND_ACC_CONTROL_CS1_ECC_LEVEL_DEFAULT 0x0000000f
-
-/* NAND :: ACC_CONTROL_CS1 :: reserved2 [15:08] */
-#define BCHP_NAND_ACC_CONTROL_CS1_reserved2_MASK 0x0000ff00
-#define BCHP_NAND_ACC_CONTROL_CS1_reserved2_SHIFT 8
-
-/* NAND :: ACC_CONTROL_CS1 :: SECTOR_SIZE_1K [07:07] */
-#define BCHP_NAND_ACC_CONTROL_CS1_SECTOR_SIZE_1K_MASK 0x00000080
-#define BCHP_NAND_ACC_CONTROL_CS1_SECTOR_SIZE_1K_SHIFT 7
-#define BCHP_NAND_ACC_CONTROL_CS1_SECTOR_SIZE_1K_DEFAULT 0x00000000
-
-/* NAND :: ACC_CONTROL_CS1 :: SPARE_AREA_SIZE [06:00] */
-#define BCHP_NAND_ACC_CONTROL_CS1_SPARE_AREA_SIZE_MASK 0x0000007f
-#define BCHP_NAND_ACC_CONTROL_CS1_SPARE_AREA_SIZE_SHIFT 0
-#define BCHP_NAND_ACC_CONTROL_CS1_SPARE_AREA_SIZE_DEFAULT 0x00000010
-
-/***************************************************************************
- *CONFIG_CS1 - Nand Flash Config
- ***************************************************************************/
-/* NAND :: CONFIG_CS1 :: CONFIG_LOCK [31:31] */
-#define BCHP_NAND_CONFIG_CS1_CONFIG_LOCK_MASK 0x80000000
-#define BCHP_NAND_CONFIG_CS1_CONFIG_LOCK_SHIFT 31
-#define BCHP_NAND_CONFIG_CS1_CONFIG_LOCK_DEFAULT 0x00000000
-
-/* NAND :: CONFIG_CS1 :: BLOCK_SIZE [30:28] */
-#define BCHP_NAND_CONFIG_CS1_BLOCK_SIZE_MASK 0x70000000
-#define BCHP_NAND_CONFIG_CS1_BLOCK_SIZE_SHIFT 28
-#define BCHP_NAND_CONFIG_CS1_BLOCK_SIZE_BK_SIZE_2048KB 6
-#define BCHP_NAND_CONFIG_CS1_BLOCK_SIZE_BK_SIZE_1024KB 5
-#define BCHP_NAND_CONFIG_CS1_BLOCK_SIZE_BK_SIZE_512KB 4
-#define BCHP_NAND_CONFIG_CS1_BLOCK_SIZE_BK_SIZE_256KB 3
-#define BCHP_NAND_CONFIG_CS1_BLOCK_SIZE_BK_SIZE_128KB 2
-#define BCHP_NAND_CONFIG_CS1_BLOCK_SIZE_BK_SIZE_16KB 1
-#define BCHP_NAND_CONFIG_CS1_BLOCK_SIZE_BK_SIZE_8KB 0
-
-/* NAND :: CONFIG_CS1 :: DEVICE_SIZE [27:24] */
-#define BCHP_NAND_CONFIG_CS1_DEVICE_SIZE_MASK 0x0f000000
-#define BCHP_NAND_CONFIG_CS1_DEVICE_SIZE_SHIFT 24
-#define BCHP_NAND_CONFIG_CS1_DEVICE_SIZE_DVC_SIZE_4MB 0
-#define BCHP_NAND_CONFIG_CS1_DEVICE_SIZE_DVC_SIZE_8MB 1
-#define BCHP_NAND_CONFIG_CS1_DEVICE_SIZE_DVC_SIZE_16MB 2
-#define BCHP_NAND_CONFIG_CS1_DEVICE_SIZE_DVC_SIZE_32MB 3
-#define BCHP_NAND_CONFIG_CS1_DEVICE_SIZE_DVC_SIZE_64MB 4
-#define BCHP_NAND_CONFIG_CS1_DEVICE_SIZE_DVC_SIZE_128MB 5
-#define BCHP_NAND_CONFIG_CS1_DEVICE_SIZE_DVC_SIZE_256MB 6
-#define BCHP_NAND_CONFIG_CS1_DEVICE_SIZE_DVC_SIZE_512MB 7
-#define BCHP_NAND_CONFIG_CS1_DEVICE_SIZE_DVC_SIZE_1GB 8
-#define BCHP_NAND_CONFIG_CS1_DEVICE_SIZE_DVC_SIZE_2GB 9
-#define BCHP_NAND_CONFIG_CS1_DEVICE_SIZE_DVC_SIZE_4GB 10
-#define BCHP_NAND_CONFIG_CS1_DEVICE_SIZE_DVC_SIZE_8GB 11
-#define BCHP_NAND_CONFIG_CS1_DEVICE_SIZE_DVC_SIZE_16GB 12
-#define BCHP_NAND_CONFIG_CS1_DEVICE_SIZE_DVC_SIZE_32GB 13
-#define BCHP_NAND_CONFIG_CS1_DEVICE_SIZE_DVC_SIZE_64GB 14
-#define BCHP_NAND_CONFIG_CS1_DEVICE_SIZE_DVC_SIZE_128GB 15
-
-/* NAND :: CONFIG_CS1 :: DEVICE_WIDTH [23:23] */
-#define BCHP_NAND_CONFIG_CS1_DEVICE_WIDTH_MASK 0x00800000
-#define BCHP_NAND_CONFIG_CS1_DEVICE_WIDTH_SHIFT 23
-#define BCHP_NAND_CONFIG_CS1_DEVICE_WIDTH_DVC_WIDTH_8 0
-#define BCHP_NAND_CONFIG_CS1_DEVICE_WIDTH_DVC_WIDTH_16 1
-
-/* NAND :: CONFIG_CS1 :: reserved0 [22:22] */
-#define BCHP_NAND_CONFIG_CS1_reserved0_MASK 0x00400000
-#define BCHP_NAND_CONFIG_CS1_reserved0_SHIFT 22
-
-/* NAND :: CONFIG_CS1 :: PAGE_SIZE [21:20] */
-#define BCHP_NAND_CONFIG_CS1_PAGE_SIZE_MASK 0x00300000
-#define BCHP_NAND_CONFIG_CS1_PAGE_SIZE_SHIFT 20
-#define BCHP_NAND_CONFIG_CS1_PAGE_SIZE_PG_SIZE_512 0
-#define BCHP_NAND_CONFIG_CS1_PAGE_SIZE_PG_SIZE_2KB 1
-#define BCHP_NAND_CONFIG_CS1_PAGE_SIZE_PG_SIZE_4KB 2
-#define BCHP_NAND_CONFIG_CS1_PAGE_SIZE_PG_SIZE_8KB 3
-
-/* NAND :: CONFIG_CS1 :: reserved1 [19:19] */
-#define BCHP_NAND_CONFIG_CS1_reserved1_MASK 0x00080000
-#define BCHP_NAND_CONFIG_CS1_reserved1_SHIFT 19
-
-/* NAND :: CONFIG_CS1 :: FUL_ADR_BYTES [18:16] */
-#define BCHP_NAND_CONFIG_CS1_FUL_ADR_BYTES_MASK 0x00070000
-#define BCHP_NAND_CONFIG_CS1_FUL_ADR_BYTES_SHIFT 16
-
-/* NAND :: CONFIG_CS1 :: reserved2 [15:15] */
-#define BCHP_NAND_CONFIG_CS1_reserved2_MASK 0x00008000
-#define BCHP_NAND_CONFIG_CS1_reserved2_SHIFT 15
-
-/* NAND :: CONFIG_CS1 :: COL_ADR_BYTES [14:12] */
-#define BCHP_NAND_CONFIG_CS1_COL_ADR_BYTES_MASK 0x00007000
-#define BCHP_NAND_CONFIG_CS1_COL_ADR_BYTES_SHIFT 12
-
-/* NAND :: CONFIG_CS1 :: reserved3 [11:11] */
-#define BCHP_NAND_CONFIG_CS1_reserved3_MASK 0x00000800
-#define BCHP_NAND_CONFIG_CS1_reserved3_SHIFT 11
-
-/* NAND :: CONFIG_CS1 :: BLK_ADR_BYTES [10:08] */
-#define BCHP_NAND_CONFIG_CS1_BLK_ADR_BYTES_MASK 0x00000700
-#define BCHP_NAND_CONFIG_CS1_BLK_ADR_BYTES_SHIFT 8
-
-/* NAND :: CONFIG_CS1 :: reserved4 [07:00] */
-#define BCHP_NAND_CONFIG_CS1_reserved4_MASK 0x000000ff
-#define BCHP_NAND_CONFIG_CS1_reserved4_SHIFT 0
-
-/***************************************************************************
- *TIMING_1_CS1 - Nand Flash Timing Parameters 1
- ***************************************************************************/
-/* NAND :: TIMING_1_CS1 :: tWP [31:28] */
-#define BCHP_NAND_TIMING_1_CS1_tWP_MASK 0xf0000000
-#define BCHP_NAND_TIMING_1_CS1_tWP_SHIFT 28
-#define BCHP_NAND_TIMING_1_CS1_tWP_DEFAULT 0x00000006
-
-/* NAND :: TIMING_1_CS1 :: tWH [27:24] */
-#define BCHP_NAND_TIMING_1_CS1_tWH_MASK 0x0f000000
-#define BCHP_NAND_TIMING_1_CS1_tWH_SHIFT 24
-#define BCHP_NAND_TIMING_1_CS1_tWH_DEFAULT 0x00000005
-
-/* NAND :: TIMING_1_CS1 :: tRP [23:20] */
-#define BCHP_NAND_TIMING_1_CS1_tRP_MASK 0x00f00000
-#define BCHP_NAND_TIMING_1_CS1_tRP_SHIFT 20
-#define BCHP_NAND_TIMING_1_CS1_tRP_DEFAULT 0x00000007
-
-/* NAND :: TIMING_1_CS1 :: tREH [19:16] */
-#define BCHP_NAND_TIMING_1_CS1_tREH_MASK 0x000f0000
-#define BCHP_NAND_TIMING_1_CS1_tREH_SHIFT 16
-#define BCHP_NAND_TIMING_1_CS1_tREH_DEFAULT 0x00000004
-
-/* NAND :: TIMING_1_CS1 :: tCS [15:12] */
-#define BCHP_NAND_TIMING_1_CS1_tCS_MASK 0x0000f000
-#define BCHP_NAND_TIMING_1_CS1_tCS_SHIFT 12
-#define BCHP_NAND_TIMING_1_CS1_tCS_DEFAULT 0x00000008
-
-/* NAND :: TIMING_1_CS1 :: tCLH [11:08] */
-#define BCHP_NAND_TIMING_1_CS1_tCLH_MASK 0x00000f00
-#define BCHP_NAND_TIMING_1_CS1_tCLH_SHIFT 8
-#define BCHP_NAND_TIMING_1_CS1_tCLH_DEFAULT 0x00000004
-
-/* NAND :: TIMING_1_CS1 :: tALH [07:04] */
-#define BCHP_NAND_TIMING_1_CS1_tALH_MASK 0x000000f0
-#define BCHP_NAND_TIMING_1_CS1_tALH_SHIFT 4
-#define BCHP_NAND_TIMING_1_CS1_tALH_DEFAULT 0x00000005
-
-/* NAND :: TIMING_1_CS1 :: tADL [03:00] */
-#define BCHP_NAND_TIMING_1_CS1_tADL_MASK 0x0000000f
-#define BCHP_NAND_TIMING_1_CS1_tADL_SHIFT 0
-#define BCHP_NAND_TIMING_1_CS1_tADL_DEFAULT 0x0000000b
-
-/***************************************************************************
- *TIMING_2_CS1 - Nand Flash Timing Parameters 2
- ***************************************************************************/
-/* NAND :: TIMING_2_CS1 :: CLK_SELECT [31:31] */
-#define BCHP_NAND_TIMING_2_CS1_CLK_SELECT_MASK 0x80000000
-#define BCHP_NAND_TIMING_2_CS1_CLK_SELECT_SHIFT 31
-#define BCHP_NAND_TIMING_2_CS1_CLK_SELECT_DEFAULT 0x00000000
-#define BCHP_NAND_TIMING_2_CS1_CLK_SELECT_CLK_108 0
-#define BCHP_NAND_TIMING_2_CS1_CLK_SELECT_CLK_216 1
-
-/* NAND :: TIMING_2_CS1 :: reserved0 [30:13] */
-#define BCHP_NAND_TIMING_2_CS1_reserved0_MASK 0x7fffe000
-#define BCHP_NAND_TIMING_2_CS1_reserved0_SHIFT 13
-
-/* NAND :: TIMING_2_CS1 :: tWB [12:09] */
-#define BCHP_NAND_TIMING_2_CS1_tWB_MASK 0x00001e00
-#define BCHP_NAND_TIMING_2_CS1_tWB_SHIFT 9
-#define BCHP_NAND_TIMING_2_CS1_tWB_DEFAULT 0x0000000f
-
-/* NAND :: TIMING_2_CS1 :: tWHR [08:04] */
-#define BCHP_NAND_TIMING_2_CS1_tWHR_MASK 0x000001f0
-#define BCHP_NAND_TIMING_2_CS1_tWHR_SHIFT 4
-#define BCHP_NAND_TIMING_2_CS1_tWHR_DEFAULT 0x00000009
-
-/* NAND :: TIMING_2_CS1 :: tREAD [03:00] */
-#define BCHP_NAND_TIMING_2_CS1_tREAD_MASK 0x0000000f
-#define BCHP_NAND_TIMING_2_CS1_tREAD_SHIFT 0
-#define BCHP_NAND_TIMING_2_CS1_tREAD_DEFAULT 0x00000006
-
-/***************************************************************************
- *ACC_CONTROL_CS2 - Nand Flash Access Control
- ***************************************************************************/
-/* NAND :: ACC_CONTROL_CS2 :: RD_ECC_EN [31:31] */
-#define BCHP_NAND_ACC_CONTROL_CS2_RD_ECC_EN_MASK 0x80000000
-#define BCHP_NAND_ACC_CONTROL_CS2_RD_ECC_EN_SHIFT 31
-#define BCHP_NAND_ACC_CONTROL_CS2_RD_ECC_EN_DEFAULT 0x00000001
-
-/* NAND :: ACC_CONTROL_CS2 :: WR_ECC_EN [30:30] */
-#define BCHP_NAND_ACC_CONTROL_CS2_WR_ECC_EN_MASK 0x40000000
-#define BCHP_NAND_ACC_CONTROL_CS2_WR_ECC_EN_SHIFT 30
-#define BCHP_NAND_ACC_CONTROL_CS2_WR_ECC_EN_DEFAULT 0x00000001
-
-/* NAND :: ACC_CONTROL_CS2 :: CE_CARE [29:29] */
-#define BCHP_NAND_ACC_CONTROL_CS2_CE_CARE_MASK 0x20000000
-#define BCHP_NAND_ACC_CONTROL_CS2_CE_CARE_SHIFT 29
-#define BCHP_NAND_ACC_CONTROL_CS2_CE_CARE_DEFAULT 0x00000000
-
-/* NAND :: ACC_CONTROL_CS2 :: reserved0 [28:28] */
-#define BCHP_NAND_ACC_CONTROL_CS2_reserved0_MASK 0x10000000
-#define BCHP_NAND_ACC_CONTROL_CS2_reserved0_SHIFT 28
-
-/* NAND :: ACC_CONTROL_CS2 :: RD_ERASED_ECC_EN [27:27] */
-#define BCHP_NAND_ACC_CONTROL_CS2_RD_ERASED_ECC_EN_MASK 0x08000000
-#define BCHP_NAND_ACC_CONTROL_CS2_RD_ERASED_ECC_EN_SHIFT 27
-#define BCHP_NAND_ACC_CONTROL_CS2_RD_ERASED_ECC_EN_DEFAULT 0x00000000
-
-/* NAND :: ACC_CONTROL_CS2 :: PARTIAL_PAGE_EN [26:26] */
-#define BCHP_NAND_ACC_CONTROL_CS2_PARTIAL_PAGE_EN_MASK 0x04000000
-#define BCHP_NAND_ACC_CONTROL_CS2_PARTIAL_PAGE_EN_SHIFT 26
-#define BCHP_NAND_ACC_CONTROL_CS2_PARTIAL_PAGE_EN_DEFAULT 0x00000000
-
-/* NAND :: ACC_CONTROL_CS2 :: WR_PREEMPT_EN [25:25] */
-#define BCHP_NAND_ACC_CONTROL_CS2_WR_PREEMPT_EN_MASK 0x02000000
-#define BCHP_NAND_ACC_CONTROL_CS2_WR_PREEMPT_EN_SHIFT 25
-#define BCHP_NAND_ACC_CONTROL_CS2_WR_PREEMPT_EN_DEFAULT 0x00000001
-
-/* NAND :: ACC_CONTROL_CS2 :: PAGE_HIT_EN [24:24] */
-#define BCHP_NAND_ACC_CONTROL_CS2_PAGE_HIT_EN_MASK 0x01000000
-#define BCHP_NAND_ACC_CONTROL_CS2_PAGE_HIT_EN_SHIFT 24
-#define BCHP_NAND_ACC_CONTROL_CS2_PAGE_HIT_EN_DEFAULT 0x00000001
-
-/* NAND :: ACC_CONTROL_CS2 :: PREFETCH_EN [23:23] */
-#define BCHP_NAND_ACC_CONTROL_CS2_PREFETCH_EN_MASK 0x00800000
-#define BCHP_NAND_ACC_CONTROL_CS2_PREFETCH_EN_SHIFT 23
-#define BCHP_NAND_ACC_CONTROL_CS2_PREFETCH_EN_DEFAULT 0x00000000
-
-/* NAND :: ACC_CONTROL_CS2 :: CACHE_MODE_EN [22:22] */
-#define BCHP_NAND_ACC_CONTROL_CS2_CACHE_MODE_EN_MASK 0x00400000
-#define BCHP_NAND_ACC_CONTROL_CS2_CACHE_MODE_EN_SHIFT 22
-#define BCHP_NAND_ACC_CONTROL_CS2_CACHE_MODE_EN_DEFAULT 0x00000000
-
-/* NAND :: ACC_CONTROL_CS2 :: reserved1 [21:21] */
-#define BCHP_NAND_ACC_CONTROL_CS2_reserved1_MASK 0x00200000
-#define BCHP_NAND_ACC_CONTROL_CS2_reserved1_SHIFT 21
-
-/* NAND :: ACC_CONTROL_CS2 :: ECC_LEVEL [20:16] */
-#define BCHP_NAND_ACC_CONTROL_CS2_ECC_LEVEL_MASK 0x001f0000
-#define BCHP_NAND_ACC_CONTROL_CS2_ECC_LEVEL_SHIFT 16
-#define BCHP_NAND_ACC_CONTROL_CS2_ECC_LEVEL_DEFAULT 0x0000000f
-
-/* NAND :: ACC_CONTROL_CS2 :: reserved2 [15:08] */
-#define BCHP_NAND_ACC_CONTROL_CS2_reserved2_MASK 0x0000ff00
-#define BCHP_NAND_ACC_CONTROL_CS2_reserved2_SHIFT 8
-
-/* NAND :: ACC_CONTROL_CS2 :: SECTOR_SIZE_1K [07:07] */
-#define BCHP_NAND_ACC_CONTROL_CS2_SECTOR_SIZE_1K_MASK 0x00000080
-#define BCHP_NAND_ACC_CONTROL_CS2_SECTOR_SIZE_1K_SHIFT 7
-#define BCHP_NAND_ACC_CONTROL_CS2_SECTOR_SIZE_1K_DEFAULT 0x00000000
-
-/* NAND :: ACC_CONTROL_CS2 :: SPARE_AREA_SIZE [06:00] */
-#define BCHP_NAND_ACC_CONTROL_CS2_SPARE_AREA_SIZE_MASK 0x0000007f
-#define BCHP_NAND_ACC_CONTROL_CS2_SPARE_AREA_SIZE_SHIFT 0
-#define BCHP_NAND_ACC_CONTROL_CS2_SPARE_AREA_SIZE_DEFAULT 0x00000010
-
-/***************************************************************************
- *CONFIG_CS2 - Nand Flash Config
- ***************************************************************************/
-/* NAND :: CONFIG_CS2 :: CONFIG_LOCK [31:31] */
-#define BCHP_NAND_CONFIG_CS2_CONFIG_LOCK_MASK 0x80000000
-#define BCHP_NAND_CONFIG_CS2_CONFIG_LOCK_SHIFT 31
-#define BCHP_NAND_CONFIG_CS2_CONFIG_LOCK_DEFAULT 0x00000000
-
-/* NAND :: CONFIG_CS2 :: BLOCK_SIZE [30:28] */
-#define BCHP_NAND_CONFIG_CS2_BLOCK_SIZE_MASK 0x70000000
-#define BCHP_NAND_CONFIG_CS2_BLOCK_SIZE_SHIFT 28
-#define BCHP_NAND_CONFIG_CS2_BLOCK_SIZE_BK_SIZE_2048KB 6
-#define BCHP_NAND_CONFIG_CS2_BLOCK_SIZE_BK_SIZE_1024KB 5
-#define BCHP_NAND_CONFIG_CS2_BLOCK_SIZE_BK_SIZE_512KB 4
-#define BCHP_NAND_CONFIG_CS2_BLOCK_SIZE_BK_SIZE_256KB 3
-#define BCHP_NAND_CONFIG_CS2_BLOCK_SIZE_BK_SIZE_128KB 2
-#define BCHP_NAND_CONFIG_CS2_BLOCK_SIZE_BK_SIZE_16KB 1
-#define BCHP_NAND_CONFIG_CS2_BLOCK_SIZE_BK_SIZE_8KB 0
-
-/* NAND :: CONFIG_CS2 :: DEVICE_SIZE [27:24] */
-#define BCHP_NAND_CONFIG_CS2_DEVICE_SIZE_MASK 0x0f000000
-#define BCHP_NAND_CONFIG_CS2_DEVICE_SIZE_SHIFT 24
-#define BCHP_NAND_CONFIG_CS2_DEVICE_SIZE_DVC_SIZE_4MB 0
-#define BCHP_NAND_CONFIG_CS2_DEVICE_SIZE_DVC_SIZE_8MB 1
-#define BCHP_NAND_CONFIG_CS2_DEVICE_SIZE_DVC_SIZE_16MB 2
-#define BCHP_NAND_CONFIG_CS2_DEVICE_SIZE_DVC_SIZE_32MB 3
-#define BCHP_NAND_CONFIG_CS2_DEVICE_SIZE_DVC_SIZE_64MB 4
-#define BCHP_NAND_CONFIG_CS2_DEVICE_SIZE_DVC_SIZE_128MB 5
-#define BCHP_NAND_CONFIG_CS2_DEVICE_SIZE_DVC_SIZE_256MB 6
-#define BCHP_NAND_CONFIG_CS2_DEVICE_SIZE_DVC_SIZE_512MB 7
-#define BCHP_NAND_CONFIG_CS2_DEVICE_SIZE_DVC_SIZE_1GB 8
-#define BCHP_NAND_CONFIG_CS2_DEVICE_SIZE_DVC_SIZE_2GB 9
-#define BCHP_NAND_CONFIG_CS2_DEVICE_SIZE_DVC_SIZE_4GB 10
-#define BCHP_NAND_CONFIG_CS2_DEVICE_SIZE_DVC_SIZE_8GB 11
-#define BCHP_NAND_CONFIG_CS2_DEVICE_SIZE_DVC_SIZE_16GB 12
-#define BCHP_NAND_CONFIG_CS2_DEVICE_SIZE_DVC_SIZE_32GB 13
-#define BCHP_NAND_CONFIG_CS2_DEVICE_SIZE_DVC_SIZE_64GB 14
-#define BCHP_NAND_CONFIG_CS2_DEVICE_SIZE_DVC_SIZE_128GB 15
-
-/* NAND :: CONFIG_CS2 :: DEVICE_WIDTH [23:23] */
-#define BCHP_NAND_CONFIG_CS2_DEVICE_WIDTH_MASK 0x00800000
-#define BCHP_NAND_CONFIG_CS2_DEVICE_WIDTH_SHIFT 23
-#define BCHP_NAND_CONFIG_CS2_DEVICE_WIDTH_DVC_WIDTH_8 0
-#define BCHP_NAND_CONFIG_CS2_DEVICE_WIDTH_DVC_WIDTH_16 1
-
-/* NAND :: CONFIG_CS2 :: reserved0 [22:22] */
-#define BCHP_NAND_CONFIG_CS2_reserved0_MASK 0x00400000
-#define BCHP_NAND_CONFIG_CS2_reserved0_SHIFT 22
-
-/* NAND :: CONFIG_CS2 :: PAGE_SIZE [21:20] */
-#define BCHP_NAND_CONFIG_CS2_PAGE_SIZE_MASK 0x00300000
-#define BCHP_NAND_CONFIG_CS2_PAGE_SIZE_SHIFT 20
-#define BCHP_NAND_CONFIG_CS2_PAGE_SIZE_PG_SIZE_512 0
-#define BCHP_NAND_CONFIG_CS2_PAGE_SIZE_PG_SIZE_2KB 1
-#define BCHP_NAND_CONFIG_CS2_PAGE_SIZE_PG_SIZE_4KB 2
-#define BCHP_NAND_CONFIG_CS2_PAGE_SIZE_PG_SIZE_8KB 3
-
-/* NAND :: CONFIG_CS2 :: reserved1 [19:19] */
-#define BCHP_NAND_CONFIG_CS2_reserved1_MASK 0x00080000
-#define BCHP_NAND_CONFIG_CS2_reserved1_SHIFT 19
-
-/* NAND :: CONFIG_CS2 :: FUL_ADR_BYTES [18:16] */
-#define BCHP_NAND_CONFIG_CS2_FUL_ADR_BYTES_MASK 0x00070000
-#define BCHP_NAND_CONFIG_CS2_FUL_ADR_BYTES_SHIFT 16
-
-/* NAND :: CONFIG_CS2 :: reserved2 [15:15] */
-#define BCHP_NAND_CONFIG_CS2_reserved2_MASK 0x00008000
-#define BCHP_NAND_CONFIG_CS2_reserved2_SHIFT 15
-
-/* NAND :: CONFIG_CS2 :: COL_ADR_BYTES [14:12] */
-#define BCHP_NAND_CONFIG_CS2_COL_ADR_BYTES_MASK 0x00007000
-#define BCHP_NAND_CONFIG_CS2_COL_ADR_BYTES_SHIFT 12
-
-/* NAND :: CONFIG_CS2 :: reserved3 [11:11] */
-#define BCHP_NAND_CONFIG_CS2_reserved3_MASK 0x00000800
-#define BCHP_NAND_CONFIG_CS2_reserved3_SHIFT 11
-
-/* NAND :: CONFIG_CS2 :: BLK_ADR_BYTES [10:08] */
-#define BCHP_NAND_CONFIG_CS2_BLK_ADR_BYTES_MASK 0x00000700
-#define BCHP_NAND_CONFIG_CS2_BLK_ADR_BYTES_SHIFT 8
-
-/* NAND :: CONFIG_CS2 :: reserved4 [07:00] */
-#define BCHP_NAND_CONFIG_CS2_reserved4_MASK 0x000000ff
-#define BCHP_NAND_CONFIG_CS2_reserved4_SHIFT 0
-
-/***************************************************************************
- *TIMING_1_CS2 - Nand Flash Timing Parameters 1
- ***************************************************************************/
-/* NAND :: TIMING_1_CS2 :: tWP [31:28] */
-#define BCHP_NAND_TIMING_1_CS2_tWP_MASK 0xf0000000
-#define BCHP_NAND_TIMING_1_CS2_tWP_SHIFT 28
-#define BCHP_NAND_TIMING_1_CS2_tWP_DEFAULT 0x00000006
-
-/* NAND :: TIMING_1_CS2 :: tWH [27:24] */
-#define BCHP_NAND_TIMING_1_CS2_tWH_MASK 0x0f000000
-#define BCHP_NAND_TIMING_1_CS2_tWH_SHIFT 24
-#define BCHP_NAND_TIMING_1_CS2_tWH_DEFAULT 0x00000005
-
-/* NAND :: TIMING_1_CS2 :: tRP [23:20] */
-#define BCHP_NAND_TIMING_1_CS2_tRP_MASK 0x00f00000
-#define BCHP_NAND_TIMING_1_CS2_tRP_SHIFT 20
-#define BCHP_NAND_TIMING_1_CS2_tRP_DEFAULT 0x00000007
-
-/* NAND :: TIMING_1_CS2 :: tREH [19:16] */
-#define BCHP_NAND_TIMING_1_CS2_tREH_MASK 0x000f0000
-#define BCHP_NAND_TIMING_1_CS2_tREH_SHIFT 16
-#define BCHP_NAND_TIMING_1_CS2_tREH_DEFAULT 0x00000004
-
-/* NAND :: TIMING_1_CS2 :: tCS [15:12] */
-#define BCHP_NAND_TIMING_1_CS2_tCS_MASK 0x0000f000
-#define BCHP_NAND_TIMING_1_CS2_tCS_SHIFT 12
-#define BCHP_NAND_TIMING_1_CS2_tCS_DEFAULT 0x00000008
-
-/* NAND :: TIMING_1_CS2 :: tCLH [11:08] */
-#define BCHP_NAND_TIMING_1_CS2_tCLH_MASK 0x00000f00
-#define BCHP_NAND_TIMING_1_CS2_tCLH_SHIFT 8
-#define BCHP_NAND_TIMING_1_CS2_tCLH_DEFAULT 0x00000004
-
-/* NAND :: TIMING_1_CS2 :: tALH [07:04] */
-#define BCHP_NAND_TIMING_1_CS2_tALH_MASK 0x000000f0
-#define BCHP_NAND_TIMING_1_CS2_tALH_SHIFT 4
-#define BCHP_NAND_TIMING_1_CS2_tALH_DEFAULT 0x00000005
-
-/* NAND :: TIMING_1_CS2 :: tADL [03:00] */
-#define BCHP_NAND_TIMING_1_CS2_tADL_MASK 0x0000000f
-#define BCHP_NAND_TIMING_1_CS2_tADL_SHIFT 0
-#define BCHP_NAND_TIMING_1_CS2_tADL_DEFAULT 0x0000000b
-
-/***************************************************************************
- *TIMING_2_CS2 - Nand Flash Timing Parameters 2
- ***************************************************************************/
-/* NAND :: TIMING_2_CS2 :: CLK_SELECT [31:31] */
-#define BCHP_NAND_TIMING_2_CS2_CLK_SELECT_MASK 0x80000000
-#define BCHP_NAND_TIMING_2_CS2_CLK_SELECT_SHIFT 31
-#define BCHP_NAND_TIMING_2_CS2_CLK_SELECT_DEFAULT 0x00000000
-#define BCHP_NAND_TIMING_2_CS2_CLK_SELECT_CLK_108 0
-#define BCHP_NAND_TIMING_2_CS2_CLK_SELECT_CLK_216 1
-
-/* NAND :: TIMING_2_CS2 :: reserved0 [30:13] */
-#define BCHP_NAND_TIMING_2_CS2_reserved0_MASK 0x7fffe000
-#define BCHP_NAND_TIMING_2_CS2_reserved0_SHIFT 13
-
-/* NAND :: TIMING_2_CS2 :: tWB [12:09] */
-#define BCHP_NAND_TIMING_2_CS2_tWB_MASK 0x00001e00
-#define BCHP_NAND_TIMING_2_CS2_tWB_SHIFT 9
-#define BCHP_NAND_TIMING_2_CS2_tWB_DEFAULT 0x0000000f
-
-/* NAND :: TIMING_2_CS2 :: tWHR [08:04] */
-#define BCHP_NAND_TIMING_2_CS2_tWHR_MASK 0x000001f0
-#define BCHP_NAND_TIMING_2_CS2_tWHR_SHIFT 4
-#define BCHP_NAND_TIMING_2_CS2_tWHR_DEFAULT 0x00000009
-
-/* NAND :: TIMING_2_CS2 :: tREAD [03:00] */
-#define BCHP_NAND_TIMING_2_CS2_tREAD_MASK 0x0000000f
-#define BCHP_NAND_TIMING_2_CS2_tREAD_SHIFT 0
-#define BCHP_NAND_TIMING_2_CS2_tREAD_DEFAULT 0x00000006
-
-/***************************************************************************
- *ACC_CONTROL_CS3 - Nand Flash Access Control
- ***************************************************************************/
-/* NAND :: ACC_CONTROL_CS3 :: RD_ECC_EN [31:31] */
-#define BCHP_NAND_ACC_CONTROL_CS3_RD_ECC_EN_MASK 0x80000000
-#define BCHP_NAND_ACC_CONTROL_CS3_RD_ECC_EN_SHIFT 31
-#define BCHP_NAND_ACC_CONTROL_CS3_RD_ECC_EN_DEFAULT 0x00000001
-
-/* NAND :: ACC_CONTROL_CS3 :: WR_ECC_EN [30:30] */
-#define BCHP_NAND_ACC_CONTROL_CS3_WR_ECC_EN_MASK 0x40000000
-#define BCHP_NAND_ACC_CONTROL_CS3_WR_ECC_EN_SHIFT 30
-#define BCHP_NAND_ACC_CONTROL_CS3_WR_ECC_EN_DEFAULT 0x00000001
-
-/* NAND :: ACC_CONTROL_CS3 :: CE_CARE [29:29] */
-#define BCHP_NAND_ACC_CONTROL_CS3_CE_CARE_MASK 0x20000000
-#define BCHP_NAND_ACC_CONTROL_CS3_CE_CARE_SHIFT 29
-#define BCHP_NAND_ACC_CONTROL_CS3_CE_CARE_DEFAULT 0x00000000
-
-/* NAND :: ACC_CONTROL_CS3 :: reserved0 [28:28] */
-#define BCHP_NAND_ACC_CONTROL_CS3_reserved0_MASK 0x10000000
-#define BCHP_NAND_ACC_CONTROL_CS3_reserved0_SHIFT 28
-
-/* NAND :: ACC_CONTROL_CS3 :: RD_ERASED_ECC_EN [27:27] */
-#define BCHP_NAND_ACC_CONTROL_CS3_RD_ERASED_ECC_EN_MASK 0x08000000
-#define BCHP_NAND_ACC_CONTROL_CS3_RD_ERASED_ECC_EN_SHIFT 27
-#define BCHP_NAND_ACC_CONTROL_CS3_RD_ERASED_ECC_EN_DEFAULT 0x00000000
-
-/* NAND :: ACC_CONTROL_CS3 :: PARTIAL_PAGE_EN [26:26] */
-#define BCHP_NAND_ACC_CONTROL_CS3_PARTIAL_PAGE_EN_MASK 0x04000000
-#define BCHP_NAND_ACC_CONTROL_CS3_PARTIAL_PAGE_EN_SHIFT 26
-#define BCHP_NAND_ACC_CONTROL_CS3_PARTIAL_PAGE_EN_DEFAULT 0x00000000
-
-/* NAND :: ACC_CONTROL_CS3 :: WR_PREEMPT_EN [25:25] */
-#define BCHP_NAND_ACC_CONTROL_CS3_WR_PREEMPT_EN_MASK 0x02000000
-#define BCHP_NAND_ACC_CONTROL_CS3_WR_PREEMPT_EN_SHIFT 25
-#define BCHP_NAND_ACC_CONTROL_CS3_WR_PREEMPT_EN_DEFAULT 0x00000001
-
-/* NAND :: ACC_CONTROL_CS3 :: PAGE_HIT_EN [24:24] */
-#define BCHP_NAND_ACC_CONTROL_CS3_PAGE_HIT_EN_MASK 0x01000000
-#define BCHP_NAND_ACC_CONTROL_CS3_PAGE_HIT_EN_SHIFT 24
-#define BCHP_NAND_ACC_CONTROL_CS3_PAGE_HIT_EN_DEFAULT 0x00000001
-
-/* NAND :: ACC_CONTROL_CS3 :: PREFETCH_EN [23:23] */
-#define BCHP_NAND_ACC_CONTROL_CS3_PREFETCH_EN_MASK 0x00800000
-#define BCHP_NAND_ACC_CONTROL_CS3_PREFETCH_EN_SHIFT 23
-#define BCHP_NAND_ACC_CONTROL_CS3_PREFETCH_EN_DEFAULT 0x00000000
-
-/* NAND :: ACC_CONTROL_CS3 :: CACHE_MODE_EN [22:22] */
-#define BCHP_NAND_ACC_CONTROL_CS3_CACHE_MODE_EN_MASK 0x00400000
-#define BCHP_NAND_ACC_CONTROL_CS3_CACHE_MODE_EN_SHIFT 22
-#define BCHP_NAND_ACC_CONTROL_CS3_CACHE_MODE_EN_DEFAULT 0x00000000
-
-/* NAND :: ACC_CONTROL_CS3 :: reserved1 [21:21] */
-#define BCHP_NAND_ACC_CONTROL_CS3_reserved1_MASK 0x00200000
-#define BCHP_NAND_ACC_CONTROL_CS3_reserved1_SHIFT 21
-
-/* NAND :: ACC_CONTROL_CS3 :: ECC_LEVEL [20:16] */
-#define BCHP_NAND_ACC_CONTROL_CS3_ECC_LEVEL_MASK 0x001f0000
-#define BCHP_NAND_ACC_CONTROL_CS3_ECC_LEVEL_SHIFT 16
-#define BCHP_NAND_ACC_CONTROL_CS3_ECC_LEVEL_DEFAULT 0x0000000f
-
-/* NAND :: ACC_CONTROL_CS3 :: reserved2 [15:08] */
-#define BCHP_NAND_ACC_CONTROL_CS3_reserved2_MASK 0x0000ff00
-#define BCHP_NAND_ACC_CONTROL_CS3_reserved2_SHIFT 8
-
-/* NAND :: ACC_CONTROL_CS3 :: SECTOR_SIZE_1K [07:07] */
-#define BCHP_NAND_ACC_CONTROL_CS3_SECTOR_SIZE_1K_MASK 0x00000080
-#define BCHP_NAND_ACC_CONTROL_CS3_SECTOR_SIZE_1K_SHIFT 7
-#define BCHP_NAND_ACC_CONTROL_CS3_SECTOR_SIZE_1K_DEFAULT 0x00000000
-
-/* NAND :: ACC_CONTROL_CS3 :: SPARE_AREA_SIZE [06:00] */
-#define BCHP_NAND_ACC_CONTROL_CS3_SPARE_AREA_SIZE_MASK 0x0000007f
-#define BCHP_NAND_ACC_CONTROL_CS3_SPARE_AREA_SIZE_SHIFT 0
-#define BCHP_NAND_ACC_CONTROL_CS3_SPARE_AREA_SIZE_DEFAULT 0x00000010
-
-/***************************************************************************
- *CONFIG_CS3 - Nand Flash Config
- ***************************************************************************/
-/* NAND :: CONFIG_CS3 :: CONFIG_LOCK [31:31] */
-#define BCHP_NAND_CONFIG_CS3_CONFIG_LOCK_MASK 0x80000000
-#define BCHP_NAND_CONFIG_CS3_CONFIG_LOCK_SHIFT 31
-#define BCHP_NAND_CONFIG_CS3_CONFIG_LOCK_DEFAULT 0x00000000
-
-/* NAND :: CONFIG_CS3 :: BLOCK_SIZE [30:28] */
-#define BCHP_NAND_CONFIG_CS3_BLOCK_SIZE_MASK 0x70000000
-#define BCHP_NAND_CONFIG_CS3_BLOCK_SIZE_SHIFT 28
-#define BCHP_NAND_CONFIG_CS3_BLOCK_SIZE_BK_SIZE_2048KB 6
-#define BCHP_NAND_CONFIG_CS3_BLOCK_SIZE_BK_SIZE_1024KB 5
-#define BCHP_NAND_CONFIG_CS3_BLOCK_SIZE_BK_SIZE_512KB 4
-#define BCHP_NAND_CONFIG_CS3_BLOCK_SIZE_BK_SIZE_256KB 3
-#define BCHP_NAND_CONFIG_CS3_BLOCK_SIZE_BK_SIZE_128KB 2
-#define BCHP_NAND_CONFIG_CS3_BLOCK_SIZE_BK_SIZE_16KB 1
-#define BCHP_NAND_CONFIG_CS3_BLOCK_SIZE_BK_SIZE_8KB 0
-
-/* NAND :: CONFIG_CS3 :: DEVICE_SIZE [27:24] */
-#define BCHP_NAND_CONFIG_CS3_DEVICE_SIZE_MASK 0x0f000000
-#define BCHP_NAND_CONFIG_CS3_DEVICE_SIZE_SHIFT 24
-#define BCHP_NAND_CONFIG_CS3_DEVICE_SIZE_DVC_SIZE_4MB 0
-#define BCHP_NAND_CONFIG_CS3_DEVICE_SIZE_DVC_SIZE_8MB 1
-#define BCHP_NAND_CONFIG_CS3_DEVICE_SIZE_DVC_SIZE_16MB 2
-#define BCHP_NAND_CONFIG_CS3_DEVICE_SIZE_DVC_SIZE_32MB 3
-#define BCHP_NAND_CONFIG_CS3_DEVICE_SIZE_DVC_SIZE_64MB 4
-#define BCHP_NAND_CONFIG_CS3_DEVICE_SIZE_DVC_SIZE_128MB 5
-#define BCHP_NAND_CONFIG_CS3_DEVICE_SIZE_DVC_SIZE_256MB 6
-#define BCHP_NAND_CONFIG_CS3_DEVICE_SIZE_DVC_SIZE_512MB 7
-#define BCHP_NAND_CONFIG_CS3_DEVICE_SIZE_DVC_SIZE_1GB 8
-#define BCHP_NAND_CONFIG_CS3_DEVICE_SIZE_DVC_SIZE_2GB 9
-#define BCHP_NAND_CONFIG_CS3_DEVICE_SIZE_DVC_SIZE_4GB 10
-#define BCHP_NAND_CONFIG_CS3_DEVICE_SIZE_DVC_SIZE_8GB 11
-#define BCHP_NAND_CONFIG_CS3_DEVICE_SIZE_DVC_SIZE_16GB 12
-#define BCHP_NAND_CONFIG_CS3_DEVICE_SIZE_DVC_SIZE_32GB 13
-#define BCHP_NAND_CONFIG_CS3_DEVICE_SIZE_DVC_SIZE_64GB 14
-#define BCHP_NAND_CONFIG_CS3_DEVICE_SIZE_DVC_SIZE_128GB 15
-
-/* NAND :: CONFIG_CS3 :: DEVICE_WIDTH [23:23] */
-#define BCHP_NAND_CONFIG_CS3_DEVICE_WIDTH_MASK 0x00800000
-#define BCHP_NAND_CONFIG_CS3_DEVICE_WIDTH_SHIFT 23
-#define BCHP_NAND_CONFIG_CS3_DEVICE_WIDTH_DVC_WIDTH_8 0
-#define BCHP_NAND_CONFIG_CS3_DEVICE_WIDTH_DVC_WIDTH_16 1
-
-/* NAND :: CONFIG_CS3 :: reserved0 [22:22] */
-#define BCHP_NAND_CONFIG_CS3_reserved0_MASK 0x00400000
-#define BCHP_NAND_CONFIG_CS3_reserved0_SHIFT 22
-
-/* NAND :: CONFIG_CS3 :: PAGE_SIZE [21:20] */
-#define BCHP_NAND_CONFIG_CS3_PAGE_SIZE_MASK 0x00300000
-#define BCHP_NAND_CONFIG_CS3_PAGE_SIZE_SHIFT 20
-#define BCHP_NAND_CONFIG_CS3_PAGE_SIZE_PG_SIZE_512 0
-#define BCHP_NAND_CONFIG_CS3_PAGE_SIZE_PG_SIZE_2KB 1
-#define BCHP_NAND_CONFIG_CS3_PAGE_SIZE_PG_SIZE_4KB 2
-#define BCHP_NAND_CONFIG_CS3_PAGE_SIZE_PG_SIZE_8KB 3
-
-/* NAND :: CONFIG_CS3 :: reserved1 [19:19] */
-#define BCHP_NAND_CONFIG_CS3_reserved1_MASK 0x00080000
-#define BCHP_NAND_CONFIG_CS3_reserved1_SHIFT 19
-
-/* NAND :: CONFIG_CS3 :: FUL_ADR_BYTES [18:16] */
-#define BCHP_NAND_CONFIG_CS3_FUL_ADR_BYTES_MASK 0x00070000
-#define BCHP_NAND_CONFIG_CS3_FUL_ADR_BYTES_SHIFT 16
-
-/* NAND :: CONFIG_CS3 :: reserved2 [15:15] */
-#define BCHP_NAND_CONFIG_CS3_reserved2_MASK 0x00008000
-#define BCHP_NAND_CONFIG_CS3_reserved2_SHIFT 15
-
-/* NAND :: CONFIG_CS3 :: COL_ADR_BYTES [14:12] */
-#define BCHP_NAND_CONFIG_CS3_COL_ADR_BYTES_MASK 0x00007000
-#define BCHP_NAND_CONFIG_CS3_COL_ADR_BYTES_SHIFT 12
-
-/* NAND :: CONFIG_CS3 :: reserved3 [11:11] */
-#define BCHP_NAND_CONFIG_CS3_reserved3_MASK 0x00000800
-#define BCHP_NAND_CONFIG_CS3_reserved3_SHIFT 11
-
-/* NAND :: CONFIG_CS3 :: BLK_ADR_BYTES [10:08] */
-#define BCHP_NAND_CONFIG_CS3_BLK_ADR_BYTES_MASK 0x00000700
-#define BCHP_NAND_CONFIG_CS3_BLK_ADR_BYTES_SHIFT 8
-
-/* NAND :: CONFIG_CS3 :: reserved4 [07:00] */
-#define BCHP_NAND_CONFIG_CS3_reserved4_MASK 0x000000ff
-#define BCHP_NAND_CONFIG_CS3_reserved4_SHIFT 0
-
-/***************************************************************************
- *TIMING_1_CS3 - Nand Flash Timing Parameters 1
- ***************************************************************************/
-/* NAND :: TIMING_1_CS3 :: tWP [31:28] */
-#define BCHP_NAND_TIMING_1_CS3_tWP_MASK 0xf0000000
-#define BCHP_NAND_TIMING_1_CS3_tWP_SHIFT 28
-#define BCHP_NAND_TIMING_1_CS3_tWP_DEFAULT 0x00000006
-
-/* NAND :: TIMING_1_CS3 :: tWH [27:24] */
-#define BCHP_NAND_TIMING_1_CS3_tWH_MASK 0x0f000000
-#define BCHP_NAND_TIMING_1_CS3_tWH_SHIFT 24
-#define BCHP_NAND_TIMING_1_CS3_tWH_DEFAULT 0x00000005
-
-/* NAND :: TIMING_1_CS3 :: tRP [23:20] */
-#define BCHP_NAND_TIMING_1_CS3_tRP_MASK 0x00f00000
-#define BCHP_NAND_TIMING_1_CS3_tRP_SHIFT 20
-#define BCHP_NAND_TIMING_1_CS3_tRP_DEFAULT 0x00000007
-
-/* NAND :: TIMING_1_CS3 :: tREH [19:16] */
-#define BCHP_NAND_TIMING_1_CS3_tREH_MASK 0x000f0000
-#define BCHP_NAND_TIMING_1_CS3_tREH_SHIFT 16
-#define BCHP_NAND_TIMING_1_CS3_tREH_DEFAULT 0x00000004
-
-/* NAND :: TIMING_1_CS3 :: tCS [15:12] */
-#define BCHP_NAND_TIMING_1_CS3_tCS_MASK 0x0000f000
-#define BCHP_NAND_TIMING_1_CS3_tCS_SHIFT 12
-#define BCHP_NAND_TIMING_1_CS3_tCS_DEFAULT 0x00000008
-
-/* NAND :: TIMING_1_CS3 :: tCLH [11:08] */
-#define BCHP_NAND_TIMING_1_CS3_tCLH_MASK 0x00000f00
-#define BCHP_NAND_TIMING_1_CS3_tCLH_SHIFT 8
-#define BCHP_NAND_TIMING_1_CS3_tCLH_DEFAULT 0x00000004
-
-/* NAND :: TIMING_1_CS3 :: tALH [07:04] */
-#define BCHP_NAND_TIMING_1_CS3_tALH_MASK 0x000000f0
-#define BCHP_NAND_TIMING_1_CS3_tALH_SHIFT 4
-#define BCHP_NAND_TIMING_1_CS3_tALH_DEFAULT 0x00000005
-
-/* NAND :: TIMING_1_CS3 :: tADL [03:00] */
-#define BCHP_NAND_TIMING_1_CS3_tADL_MASK 0x0000000f
-#define BCHP_NAND_TIMING_1_CS3_tADL_SHIFT 0
-#define BCHP_NAND_TIMING_1_CS3_tADL_DEFAULT 0x0000000b
-
-/***************************************************************************
- *TIMING_2_CS3 - Nand Flash Timing Parameters 2
- ***************************************************************************/
-/* NAND :: TIMING_2_CS3 :: CLK_SELECT [31:31] */
-#define BCHP_NAND_TIMING_2_CS3_CLK_SELECT_MASK 0x80000000
-#define BCHP_NAND_TIMING_2_CS3_CLK_SELECT_SHIFT 31
-#define BCHP_NAND_TIMING_2_CS3_CLK_SELECT_DEFAULT 0x00000000
-#define BCHP_NAND_TIMING_2_CS3_CLK_SELECT_CLK_108 0
-#define BCHP_NAND_TIMING_2_CS3_CLK_SELECT_CLK_216 1
-
-/* NAND :: TIMING_2_CS3 :: reserved0 [30:13] */
-#define BCHP_NAND_TIMING_2_CS3_reserved0_MASK 0x7fffe000
-#define BCHP_NAND_TIMING_2_CS3_reserved0_SHIFT 13
-
-/* NAND :: TIMING_2_CS3 :: tWB [12:09] */
-#define BCHP_NAND_TIMING_2_CS3_tWB_MASK 0x00001e00
-#define BCHP_NAND_TIMING_2_CS3_tWB_SHIFT 9
-#define BCHP_NAND_TIMING_2_CS3_tWB_DEFAULT 0x0000000f
-
-/* NAND :: TIMING_2_CS3 :: tWHR [08:04] */
-#define BCHP_NAND_TIMING_2_CS3_tWHR_MASK 0x000001f0
-#define BCHP_NAND_TIMING_2_CS3_tWHR_SHIFT 4
-#define BCHP_NAND_TIMING_2_CS3_tWHR_DEFAULT 0x00000009
-
-/* NAND :: TIMING_2_CS3 :: tREAD [03:00] */
-#define BCHP_NAND_TIMING_2_CS3_tREAD_MASK 0x0000000f
-#define BCHP_NAND_TIMING_2_CS3_tREAD_SHIFT 0
-#define BCHP_NAND_TIMING_2_CS3_tREAD_DEFAULT 0x00000006
-
-/***************************************************************************
- *ACC_CONTROL_CS4 - Nand Flash Access Control
- ***************************************************************************/
-/* NAND :: ACC_CONTROL_CS4 :: RD_ECC_EN [31:31] */
-#define BCHP_NAND_ACC_CONTROL_CS4_RD_ECC_EN_MASK 0x80000000
-#define BCHP_NAND_ACC_CONTROL_CS4_RD_ECC_EN_SHIFT 31
-#define BCHP_NAND_ACC_CONTROL_CS4_RD_ECC_EN_DEFAULT 0x00000001
-
-/* NAND :: ACC_CONTROL_CS4 :: WR_ECC_EN [30:30] */
-#define BCHP_NAND_ACC_CONTROL_CS4_WR_ECC_EN_MASK 0x40000000
-#define BCHP_NAND_ACC_CONTROL_CS4_WR_ECC_EN_SHIFT 30
-#define BCHP_NAND_ACC_CONTROL_CS4_WR_ECC_EN_DEFAULT 0x00000001
-
-/* NAND :: ACC_CONTROL_CS4 :: CE_CARE [29:29] */
-#define BCHP_NAND_ACC_CONTROL_CS4_CE_CARE_MASK 0x20000000
-#define BCHP_NAND_ACC_CONTROL_CS4_CE_CARE_SHIFT 29
-#define BCHP_NAND_ACC_CONTROL_CS4_CE_CARE_DEFAULT 0x00000000
-
-/* NAND :: ACC_CONTROL_CS4 :: reserved0 [28:28] */
-#define BCHP_NAND_ACC_CONTROL_CS4_reserved0_MASK 0x10000000
-#define BCHP_NAND_ACC_CONTROL_CS4_reserved0_SHIFT 28
-
-/* NAND :: ACC_CONTROL_CS4 :: RD_ERASED_ECC_EN [27:27] */
-#define BCHP_NAND_ACC_CONTROL_CS4_RD_ERASED_ECC_EN_MASK 0x08000000
-#define BCHP_NAND_ACC_CONTROL_CS4_RD_ERASED_ECC_EN_SHIFT 27
-#define BCHP_NAND_ACC_CONTROL_CS4_RD_ERASED_ECC_EN_DEFAULT 0x00000000
-
-/* NAND :: ACC_CONTROL_CS4 :: PARTIAL_PAGE_EN [26:26] */
-#define BCHP_NAND_ACC_CONTROL_CS4_PARTIAL_PAGE_EN_MASK 0x04000000
-#define BCHP_NAND_ACC_CONTROL_CS4_PARTIAL_PAGE_EN_SHIFT 26
-#define BCHP_NAND_ACC_CONTROL_CS4_PARTIAL_PAGE_EN_DEFAULT 0x00000000
-
-/* NAND :: ACC_CONTROL_CS4 :: WR_PREEMPT_EN [25:25] */
-#define BCHP_NAND_ACC_CONTROL_CS4_WR_PREEMPT_EN_MASK 0x02000000
-#define BCHP_NAND_ACC_CONTROL_CS4_WR_PREEMPT_EN_SHIFT 25
-#define BCHP_NAND_ACC_CONTROL_CS4_WR_PREEMPT_EN_DEFAULT 0x00000001
-
-/* NAND :: ACC_CONTROL_CS4 :: PAGE_HIT_EN [24:24] */
-#define BCHP_NAND_ACC_CONTROL_CS4_PAGE_HIT_EN_MASK 0x01000000
-#define BCHP_NAND_ACC_CONTROL_CS4_PAGE_HIT_EN_SHIFT 24
-#define BCHP_NAND_ACC_CONTROL_CS4_PAGE_HIT_EN_DEFAULT 0x00000001
-
-/* NAND :: ACC_CONTROL_CS4 :: PREFETCH_EN [23:23] */
-#define BCHP_NAND_ACC_CONTROL_CS4_PREFETCH_EN_MASK 0x00800000
-#define BCHP_NAND_ACC_CONTROL_CS4_PREFETCH_EN_SHIFT 23
-#define BCHP_NAND_ACC_CONTROL_CS4_PREFETCH_EN_DEFAULT 0x00000000
-
-/* NAND :: ACC_CONTROL_CS4 :: CACHE_MODE_EN [22:22] */
-#define BCHP_NAND_ACC_CONTROL_CS4_CACHE_MODE_EN_MASK 0x00400000
-#define BCHP_NAND_ACC_CONTROL_CS4_CACHE_MODE_EN_SHIFT 22
-#define BCHP_NAND_ACC_CONTROL_CS4_CACHE_MODE_EN_DEFAULT 0x00000000
-
-/* NAND :: ACC_CONTROL_CS4 :: reserved1 [21:21] */
-#define BCHP_NAND_ACC_CONTROL_CS4_reserved1_MASK 0x00200000
-#define BCHP_NAND_ACC_CONTROL_CS4_reserved1_SHIFT 21
-
-/* NAND :: ACC_CONTROL_CS4 :: ECC_LEVEL [20:16] */
-#define BCHP_NAND_ACC_CONTROL_CS4_ECC_LEVEL_MASK 0x001f0000
-#define BCHP_NAND_ACC_CONTROL_CS4_ECC_LEVEL_SHIFT 16
-#define BCHP_NAND_ACC_CONTROL_CS4_ECC_LEVEL_DEFAULT 0x0000000f
-
-/* NAND :: ACC_CONTROL_CS4 :: reserved2 [15:08] */
-#define BCHP_NAND_ACC_CONTROL_CS4_reserved2_MASK 0x0000ff00
-#define BCHP_NAND_ACC_CONTROL_CS4_reserved2_SHIFT 8
-
-/* NAND :: ACC_CONTROL_CS4 :: SECTOR_SIZE_1K [07:07] */
-#define BCHP_NAND_ACC_CONTROL_CS4_SECTOR_SIZE_1K_MASK 0x00000080
-#define BCHP_NAND_ACC_CONTROL_CS4_SECTOR_SIZE_1K_SHIFT 7
-#define BCHP_NAND_ACC_CONTROL_CS4_SECTOR_SIZE_1K_DEFAULT 0x00000000
-
-/* NAND :: ACC_CONTROL_CS4 :: SPARE_AREA_SIZE [06:00] */
-#define BCHP_NAND_ACC_CONTROL_CS4_SPARE_AREA_SIZE_MASK 0x0000007f
-#define BCHP_NAND_ACC_CONTROL_CS4_SPARE_AREA_SIZE_SHIFT 0
-#define BCHP_NAND_ACC_CONTROL_CS4_SPARE_AREA_SIZE_DEFAULT 0x00000010
-
-/***************************************************************************
- *CONFIG_CS4 - Nand Flash Config
- ***************************************************************************/
-/* NAND :: CONFIG_CS4 :: CONFIG_LOCK [31:31] */
-#define BCHP_NAND_CONFIG_CS4_CONFIG_LOCK_MASK 0x80000000
-#define BCHP_NAND_CONFIG_CS4_CONFIG_LOCK_SHIFT 31
-#define BCHP_NAND_CONFIG_CS4_CONFIG_LOCK_DEFAULT 0x00000000
-
-/* NAND :: CONFIG_CS4 :: BLOCK_SIZE [30:28] */
-#define BCHP_NAND_CONFIG_CS4_BLOCK_SIZE_MASK 0x70000000
-#define BCHP_NAND_CONFIG_CS4_BLOCK_SIZE_SHIFT 28
-#define BCHP_NAND_CONFIG_CS4_BLOCK_SIZE_BK_SIZE_2048KB 6
-#define BCHP_NAND_CONFIG_CS4_BLOCK_SIZE_BK_SIZE_1024KB 5
-#define BCHP_NAND_CONFIG_CS4_BLOCK_SIZE_BK_SIZE_512KB 4
-#define BCHP_NAND_CONFIG_CS4_BLOCK_SIZE_BK_SIZE_256KB 3
-#define BCHP_NAND_CONFIG_CS4_BLOCK_SIZE_BK_SIZE_128KB 2
-#define BCHP_NAND_CONFIG_CS4_BLOCK_SIZE_BK_SIZE_16KB 1
-#define BCHP_NAND_CONFIG_CS4_BLOCK_SIZE_BK_SIZE_8KB 0
-
-/* NAND :: CONFIG_CS4 :: DEVICE_SIZE [27:24] */
-#define BCHP_NAND_CONFIG_CS4_DEVICE_SIZE_MASK 0x0f000000
-#define BCHP_NAND_CONFIG_CS4_DEVICE_SIZE_SHIFT 24
-#define BCHP_NAND_CONFIG_CS4_DEVICE_SIZE_DVC_SIZE_4MB 0
-#define BCHP_NAND_CONFIG_CS4_DEVICE_SIZE_DVC_SIZE_8MB 1
-#define BCHP_NAND_CONFIG_CS4_DEVICE_SIZE_DVC_SIZE_16MB 2
-#define BCHP_NAND_CONFIG_CS4_DEVICE_SIZE_DVC_SIZE_32MB 3
-#define BCHP_NAND_CONFIG_CS4_DEVICE_SIZE_DVC_SIZE_64MB 4
-#define BCHP_NAND_CONFIG_CS4_DEVICE_SIZE_DVC_SIZE_128MB 5
-#define BCHP_NAND_CONFIG_CS4_DEVICE_SIZE_DVC_SIZE_256MB 6
-#define BCHP_NAND_CONFIG_CS4_DEVICE_SIZE_DVC_SIZE_512MB 7
-#define BCHP_NAND_CONFIG_CS4_DEVICE_SIZE_DVC_SIZE_1GB 8
-#define BCHP_NAND_CONFIG_CS4_DEVICE_SIZE_DVC_SIZE_2GB 9
-#define BCHP_NAND_CONFIG_CS4_DEVICE_SIZE_DVC_SIZE_4GB 10
-#define BCHP_NAND_CONFIG_CS4_DEVICE_SIZE_DVC_SIZE_8GB 11
-#define BCHP_NAND_CONFIG_CS4_DEVICE_SIZE_DVC_SIZE_16GB 12
-#define BCHP_NAND_CONFIG_CS4_DEVICE_SIZE_DVC_SIZE_32GB 13
-#define BCHP_NAND_CONFIG_CS4_DEVICE_SIZE_DVC_SIZE_64GB 14
-#define BCHP_NAND_CONFIG_CS4_DEVICE_SIZE_DVC_SIZE_128GB 15
-
-/* NAND :: CONFIG_CS4 :: DEVICE_WIDTH [23:23] */
-#define BCHP_NAND_CONFIG_CS4_DEVICE_WIDTH_MASK 0x00800000
-#define BCHP_NAND_CONFIG_CS4_DEVICE_WIDTH_SHIFT 23
-#define BCHP_NAND_CONFIG_CS4_DEVICE_WIDTH_DVC_WIDTH_8 0
-#define BCHP_NAND_CONFIG_CS4_DEVICE_WIDTH_DVC_WIDTH_16 1
-
-/* NAND :: CONFIG_CS4 :: reserved0 [22:22] */
-#define BCHP_NAND_CONFIG_CS4_reserved0_MASK 0x00400000
-#define BCHP_NAND_CONFIG_CS4_reserved0_SHIFT 22
-
-/* NAND :: CONFIG_CS4 :: PAGE_SIZE [21:20] */
-#define BCHP_NAND_CONFIG_CS4_PAGE_SIZE_MASK 0x00300000
-#define BCHP_NAND_CONFIG_CS4_PAGE_SIZE_SHIFT 20
-#define BCHP_NAND_CONFIG_CS4_PAGE_SIZE_PG_SIZE_512 0
-#define BCHP_NAND_CONFIG_CS4_PAGE_SIZE_PG_SIZE_2KB 1
-#define BCHP_NAND_CONFIG_CS4_PAGE_SIZE_PG_SIZE_4KB 2
-#define BCHP_NAND_CONFIG_CS4_PAGE_SIZE_PG_SIZE_8KB 3
-
-/* NAND :: CONFIG_CS4 :: reserved1 [19:19] */
-#define BCHP_NAND_CONFIG_CS4_reserved1_MASK 0x00080000
-#define BCHP_NAND_CONFIG_CS4_reserved1_SHIFT 19
-
-/* NAND :: CONFIG_CS4 :: FUL_ADR_BYTES [18:16] */
-#define BCHP_NAND_CONFIG_CS4_FUL_ADR_BYTES_MASK 0x00070000
-#define BCHP_NAND_CONFIG_CS4_FUL_ADR_BYTES_SHIFT 16
-
-/* NAND :: CONFIG_CS4 :: reserved2 [15:15] */
-#define BCHP_NAND_CONFIG_CS4_reserved2_MASK 0x00008000
-#define BCHP_NAND_CONFIG_CS4_reserved2_SHIFT 15
-
-/* NAND :: CONFIG_CS4 :: COL_ADR_BYTES [14:12] */
-#define BCHP_NAND_CONFIG_CS4_COL_ADR_BYTES_MASK 0x00007000
-#define BCHP_NAND_CONFIG_CS4_COL_ADR_BYTES_SHIFT 12
-
-/* NAND :: CONFIG_CS4 :: reserved3 [11:11] */
-#define BCHP_NAND_CONFIG_CS4_reserved3_MASK 0x00000800
-#define BCHP_NAND_CONFIG_CS4_reserved3_SHIFT 11
-
-/* NAND :: CONFIG_CS4 :: BLK_ADR_BYTES [10:08] */
-#define BCHP_NAND_CONFIG_CS4_BLK_ADR_BYTES_MASK 0x00000700
-#define BCHP_NAND_CONFIG_CS4_BLK_ADR_BYTES_SHIFT 8
-
-/* NAND :: CONFIG_CS4 :: reserved4 [07:00] */
-#define BCHP_NAND_CONFIG_CS4_reserved4_MASK 0x000000ff
-#define BCHP_NAND_CONFIG_CS4_reserved4_SHIFT 0
-
-/***************************************************************************
- *TIMING_1_CS4 - Nand Flash Timing Parameters 1
- ***************************************************************************/
-/* NAND :: TIMING_1_CS4 :: tWP [31:28] */
-#define BCHP_NAND_TIMING_1_CS4_tWP_MASK 0xf0000000
-#define BCHP_NAND_TIMING_1_CS4_tWP_SHIFT 28
-#define BCHP_NAND_TIMING_1_CS4_tWP_DEFAULT 0x00000006
-
-/* NAND :: TIMING_1_CS4 :: tWH [27:24] */
-#define BCHP_NAND_TIMING_1_CS4_tWH_MASK 0x0f000000
-#define BCHP_NAND_TIMING_1_CS4_tWH_SHIFT 24
-#define BCHP_NAND_TIMING_1_CS4_tWH_DEFAULT 0x00000005
-
-/* NAND :: TIMING_1_CS4 :: tRP [23:20] */
-#define BCHP_NAND_TIMING_1_CS4_tRP_MASK 0x00f00000
-#define BCHP_NAND_TIMING_1_CS4_tRP_SHIFT 20
-#define BCHP_NAND_TIMING_1_CS4_tRP_DEFAULT 0x00000007
-
-/* NAND :: TIMING_1_CS4 :: tREH [19:16] */
-#define BCHP_NAND_TIMING_1_CS4_tREH_MASK 0x000f0000
-#define BCHP_NAND_TIMING_1_CS4_tREH_SHIFT 16
-#define BCHP_NAND_TIMING_1_CS4_tREH_DEFAULT 0x00000004
-
-/* NAND :: TIMING_1_CS4 :: tCS [15:12] */
-#define BCHP_NAND_TIMING_1_CS4_tCS_MASK 0x0000f000
-#define BCHP_NAND_TIMING_1_CS4_tCS_SHIFT 12
-#define BCHP_NAND_TIMING_1_CS4_tCS_DEFAULT 0x00000008
-
-/* NAND :: TIMING_1_CS4 :: tCLH [11:08] */
-#define BCHP_NAND_TIMING_1_CS4_tCLH_MASK 0x00000f00
-#define BCHP_NAND_TIMING_1_CS4_tCLH_SHIFT 8
-#define BCHP_NAND_TIMING_1_CS4_tCLH_DEFAULT 0x00000004
-
-/* NAND :: TIMING_1_CS4 :: tALH [07:04] */
-#define BCHP_NAND_TIMING_1_CS4_tALH_MASK 0x000000f0
-#define BCHP_NAND_TIMING_1_CS4_tALH_SHIFT 4
-#define BCHP_NAND_TIMING_1_CS4_tALH_DEFAULT 0x00000005
-
-/* NAND :: TIMING_1_CS4 :: tADL [03:00] */
-#define BCHP_NAND_TIMING_1_CS4_tADL_MASK 0x0000000f
-#define BCHP_NAND_TIMING_1_CS4_tADL_SHIFT 0
-#define BCHP_NAND_TIMING_1_CS4_tADL_DEFAULT 0x0000000b
-
-/***************************************************************************
- *TIMING_2_CS4 - Nand Flash Timing Parameters 2
- ***************************************************************************/
-/* NAND :: TIMING_2_CS4 :: CLK_SELECT [31:31] */
-#define BCHP_NAND_TIMING_2_CS4_CLK_SELECT_MASK 0x80000000
-#define BCHP_NAND_TIMING_2_CS4_CLK_SELECT_SHIFT 31
-#define BCHP_NAND_TIMING_2_CS4_CLK_SELECT_DEFAULT 0x00000000
-#define BCHP_NAND_TIMING_2_CS4_CLK_SELECT_CLK_108 0
-#define BCHP_NAND_TIMING_2_CS4_CLK_SELECT_CLK_216 1
-
-/* NAND :: TIMING_2_CS4 :: reserved0 [30:13] */
-#define BCHP_NAND_TIMING_2_CS4_reserved0_MASK 0x7fffe000
-#define BCHP_NAND_TIMING_2_CS4_reserved0_SHIFT 13
-
-/* NAND :: TIMING_2_CS4 :: tWB [12:09] */
-#define BCHP_NAND_TIMING_2_CS4_tWB_MASK 0x00001e00
-#define BCHP_NAND_TIMING_2_CS4_tWB_SHIFT 9
-#define BCHP_NAND_TIMING_2_CS4_tWB_DEFAULT 0x0000000f
-
-/* NAND :: TIMING_2_CS4 :: tWHR [08:04] */
-#define BCHP_NAND_TIMING_2_CS4_tWHR_MASK 0x000001f0
-#define BCHP_NAND_TIMING_2_CS4_tWHR_SHIFT 4
-#define BCHP_NAND_TIMING_2_CS4_tWHR_DEFAULT 0x00000009
-
-/* NAND :: TIMING_2_CS4 :: tREAD [03:00] */
-#define BCHP_NAND_TIMING_2_CS4_tREAD_MASK 0x0000000f
-#define BCHP_NAND_TIMING_2_CS4_tREAD_SHIFT 0
-#define BCHP_NAND_TIMING_2_CS4_tREAD_DEFAULT 0x00000006
-
-/***************************************************************************
- *ACC_CONTROL_CS5 - Nand Flash Access Control
- ***************************************************************************/
-/* NAND :: ACC_CONTROL_CS5 :: RD_ECC_EN [31:31] */
-#define BCHP_NAND_ACC_CONTROL_CS5_RD_ECC_EN_MASK 0x80000000
-#define BCHP_NAND_ACC_CONTROL_CS5_RD_ECC_EN_SHIFT 31
-#define BCHP_NAND_ACC_CONTROL_CS5_RD_ECC_EN_DEFAULT 0x00000001
-
-/* NAND :: ACC_CONTROL_CS5 :: WR_ECC_EN [30:30] */
-#define BCHP_NAND_ACC_CONTROL_CS5_WR_ECC_EN_MASK 0x40000000
-#define BCHP_NAND_ACC_CONTROL_CS5_WR_ECC_EN_SHIFT 30
-#define BCHP_NAND_ACC_CONTROL_CS5_WR_ECC_EN_DEFAULT 0x00000001
-
-/* NAND :: ACC_CONTROL_CS5 :: CE_CARE [29:29] */
-#define BCHP_NAND_ACC_CONTROL_CS5_CE_CARE_MASK 0x20000000
-#define BCHP_NAND_ACC_CONTROL_CS5_CE_CARE_SHIFT 29
-#define BCHP_NAND_ACC_CONTROL_CS5_CE_CARE_DEFAULT 0x00000000
-
-/* NAND :: ACC_CONTROL_CS5 :: reserved0 [28:28] */
-#define BCHP_NAND_ACC_CONTROL_CS5_reserved0_MASK 0x10000000
-#define BCHP_NAND_ACC_CONTROL_CS5_reserved0_SHIFT 28
-
-/* NAND :: ACC_CONTROL_CS5 :: RD_ERASED_ECC_EN [27:27] */
-#define BCHP_NAND_ACC_CONTROL_CS5_RD_ERASED_ECC_EN_MASK 0x08000000
-#define BCHP_NAND_ACC_CONTROL_CS5_RD_ERASED_ECC_EN_SHIFT 27
-#define BCHP_NAND_ACC_CONTROL_CS5_RD_ERASED_ECC_EN_DEFAULT 0x00000000
-
-/* NAND :: ACC_CONTROL_CS5 :: PARTIAL_PAGE_EN [26:26] */
-#define BCHP_NAND_ACC_CONTROL_CS5_PARTIAL_PAGE_EN_MASK 0x04000000
-#define BCHP_NAND_ACC_CONTROL_CS5_PARTIAL_PAGE_EN_SHIFT 26
-#define BCHP_NAND_ACC_CONTROL_CS5_PARTIAL_PAGE_EN_DEFAULT 0x00000000
-
-/* NAND :: ACC_CONTROL_CS5 :: WR_PREEMPT_EN [25:25] */
-#define BCHP_NAND_ACC_CONTROL_CS5_WR_PREEMPT_EN_MASK 0x02000000
-#define BCHP_NAND_ACC_CONTROL_CS5_WR_PREEMPT_EN_SHIFT 25
-#define BCHP_NAND_ACC_CONTROL_CS5_WR_PREEMPT_EN_DEFAULT 0x00000001
-
-/* NAND :: ACC_CONTROL_CS5 :: PAGE_HIT_EN [24:24] */
-#define BCHP_NAND_ACC_CONTROL_CS5_PAGE_HIT_EN_MASK 0x01000000
-#define BCHP_NAND_ACC_CONTROL_CS5_PAGE_HIT_EN_SHIFT 24
-#define BCHP_NAND_ACC_CONTROL_CS5_PAGE_HIT_EN_DEFAULT 0x00000001
-
-/* NAND :: ACC_CONTROL_CS5 :: PREFETCH_EN [23:23] */
-#define BCHP_NAND_ACC_CONTROL_CS5_PREFETCH_EN_MASK 0x00800000
-#define BCHP_NAND_ACC_CONTROL_CS5_PREFETCH_EN_SHIFT 23
-#define BCHP_NAND_ACC_CONTROL_CS5_PREFETCH_EN_DEFAULT 0x00000000
-
-/* NAND :: ACC_CONTROL_CS5 :: CACHE_MODE_EN [22:22] */
-#define BCHP_NAND_ACC_CONTROL_CS5_CACHE_MODE_EN_MASK 0x00400000
-#define BCHP_NAND_ACC_CONTROL_CS5_CACHE_MODE_EN_SHIFT 22
-#define BCHP_NAND_ACC_CONTROL_CS5_CACHE_MODE_EN_DEFAULT 0x00000000
-
-/* NAND :: ACC_CONTROL_CS5 :: reserved1 [21:21] */
-#define BCHP_NAND_ACC_CONTROL_CS5_reserved1_MASK 0x00200000
-#define BCHP_NAND_ACC_CONTROL_CS5_reserved1_SHIFT 21
-
-/* NAND :: ACC_CONTROL_CS5 :: ECC_LEVEL [20:16] */
-#define BCHP_NAND_ACC_CONTROL_CS5_ECC_LEVEL_MASK 0x001f0000
-#define BCHP_NAND_ACC_CONTROL_CS5_ECC_LEVEL_SHIFT 16
-#define BCHP_NAND_ACC_CONTROL_CS5_ECC_LEVEL_DEFAULT 0x0000000f
-
-/* NAND :: ACC_CONTROL_CS5 :: reserved2 [15:08] */
-#define BCHP_NAND_ACC_CONTROL_CS5_reserved2_MASK 0x0000ff00
-#define BCHP_NAND_ACC_CONTROL_CS5_reserved2_SHIFT 8
-
-/* NAND :: ACC_CONTROL_CS5 :: SECTOR_SIZE_1K [07:07] */
-#define BCHP_NAND_ACC_CONTROL_CS5_SECTOR_SIZE_1K_MASK 0x00000080
-#define BCHP_NAND_ACC_CONTROL_CS5_SECTOR_SIZE_1K_SHIFT 7
-#define BCHP_NAND_ACC_CONTROL_CS5_SECTOR_SIZE_1K_DEFAULT 0x00000000
-
-/* NAND :: ACC_CONTROL_CS5 :: SPARE_AREA_SIZE [06:00] */
-#define BCHP_NAND_ACC_CONTROL_CS5_SPARE_AREA_SIZE_MASK 0x0000007f
-#define BCHP_NAND_ACC_CONTROL_CS5_SPARE_AREA_SIZE_SHIFT 0
-#define BCHP_NAND_ACC_CONTROL_CS5_SPARE_AREA_SIZE_DEFAULT 0x00000010
-
-/***************************************************************************
- *CONFIG_CS5 - Nand Flash Config
- ***************************************************************************/
-/* NAND :: CONFIG_CS5 :: CONFIG_LOCK [31:31] */
-#define BCHP_NAND_CONFIG_CS5_CONFIG_LOCK_MASK 0x80000000
-#define BCHP_NAND_CONFIG_CS5_CONFIG_LOCK_SHIFT 31
-#define BCHP_NAND_CONFIG_CS5_CONFIG_LOCK_DEFAULT 0x00000000
-
-/* NAND :: CONFIG_CS5 :: BLOCK_SIZE [30:28] */
-#define BCHP_NAND_CONFIG_CS5_BLOCK_SIZE_MASK 0x70000000
-#define BCHP_NAND_CONFIG_CS5_BLOCK_SIZE_SHIFT 28
-#define BCHP_NAND_CONFIG_CS5_BLOCK_SIZE_BK_SIZE_2048KB 6
-#define BCHP_NAND_CONFIG_CS5_BLOCK_SIZE_BK_SIZE_1024KB 5
-#define BCHP_NAND_CONFIG_CS5_BLOCK_SIZE_BK_SIZE_512KB 4
-#define BCHP_NAND_CONFIG_CS5_BLOCK_SIZE_BK_SIZE_256KB 3
-#define BCHP_NAND_CONFIG_CS5_BLOCK_SIZE_BK_SIZE_128KB 2
-#define BCHP_NAND_CONFIG_CS5_BLOCK_SIZE_BK_SIZE_16KB 1
-#define BCHP_NAND_CONFIG_CS5_BLOCK_SIZE_BK_SIZE_8KB 0
-
-/* NAND :: CONFIG_CS5 :: DEVICE_SIZE [27:24] */
-#define BCHP_NAND_CONFIG_CS5_DEVICE_SIZE_MASK 0x0f000000
-#define BCHP_NAND_CONFIG_CS5_DEVICE_SIZE_SHIFT 24
-#define BCHP_NAND_CONFIG_CS5_DEVICE_SIZE_DVC_SIZE_4MB 0
-#define BCHP_NAND_CONFIG_CS5_DEVICE_SIZE_DVC_SIZE_8MB 1
-#define BCHP_NAND_CONFIG_CS5_DEVICE_SIZE_DVC_SIZE_16MB 2
-#define BCHP_NAND_CONFIG_CS5_DEVICE_SIZE_DVC_SIZE_32MB 3
-#define BCHP_NAND_CONFIG_CS5_DEVICE_SIZE_DVC_SIZE_64MB 4
-#define BCHP_NAND_CONFIG_CS5_DEVICE_SIZE_DVC_SIZE_128MB 5
-#define BCHP_NAND_CONFIG_CS5_DEVICE_SIZE_DVC_SIZE_256MB 6
-#define BCHP_NAND_CONFIG_CS5_DEVICE_SIZE_DVC_SIZE_512MB 7
-#define BCHP_NAND_CONFIG_CS5_DEVICE_SIZE_DVC_SIZE_1GB 8
-#define BCHP_NAND_CONFIG_CS5_DEVICE_SIZE_DVC_SIZE_2GB 9
-#define BCHP_NAND_CONFIG_CS5_DEVICE_SIZE_DVC_SIZE_4GB 10
-#define BCHP_NAND_CONFIG_CS5_DEVICE_SIZE_DVC_SIZE_8GB 11
-#define BCHP_NAND_CONFIG_CS5_DEVICE_SIZE_DVC_SIZE_16GB 12
-#define BCHP_NAND_CONFIG_CS5_DEVICE_SIZE_DVC_SIZE_32GB 13
-#define BCHP_NAND_CONFIG_CS5_DEVICE_SIZE_DVC_SIZE_64GB 14
-#define BCHP_NAND_CONFIG_CS5_DEVICE_SIZE_DVC_SIZE_128GB 15
-
-/* NAND :: CONFIG_CS5 :: DEVICE_WIDTH [23:23] */
-#define BCHP_NAND_CONFIG_CS5_DEVICE_WIDTH_MASK 0x00800000
-#define BCHP_NAND_CONFIG_CS5_DEVICE_WIDTH_SHIFT 23
-#define BCHP_NAND_CONFIG_CS5_DEVICE_WIDTH_DVC_WIDTH_8 0
-#define BCHP_NAND_CONFIG_CS5_DEVICE_WIDTH_DVC_WIDTH_16 1
-
-/* NAND :: CONFIG_CS5 :: reserved0 [22:22] */
-#define BCHP_NAND_CONFIG_CS5_reserved0_MASK 0x00400000
-#define BCHP_NAND_CONFIG_CS5_reserved0_SHIFT 22
-
-/* NAND :: CONFIG_CS5 :: PAGE_SIZE [21:20] */
-#define BCHP_NAND_CONFIG_CS5_PAGE_SIZE_MASK 0x00300000
-#define BCHP_NAND_CONFIG_CS5_PAGE_SIZE_SHIFT 20
-#define BCHP_NAND_CONFIG_CS5_PAGE_SIZE_PG_SIZE_512 0
-#define BCHP_NAND_CONFIG_CS5_PAGE_SIZE_PG_SIZE_2KB 1
-#define BCHP_NAND_CONFIG_CS5_PAGE_SIZE_PG_SIZE_4KB 2
-#define BCHP_NAND_CONFIG_CS5_PAGE_SIZE_PG_SIZE_8KB 3
-
-/* NAND :: CONFIG_CS5 :: reserved1 [19:19] */
-#define BCHP_NAND_CONFIG_CS5_reserved1_MASK 0x00080000
-#define BCHP_NAND_CONFIG_CS5_reserved1_SHIFT 19
-
-/* NAND :: CONFIG_CS5 :: FUL_ADR_BYTES [18:16] */
-#define BCHP_NAND_CONFIG_CS5_FUL_ADR_BYTES_MASK 0x00070000
-#define BCHP_NAND_CONFIG_CS5_FUL_ADR_BYTES_SHIFT 16
-
-/* NAND :: CONFIG_CS5 :: reserved2 [15:15] */
-#define BCHP_NAND_CONFIG_CS5_reserved2_MASK 0x00008000
-#define BCHP_NAND_CONFIG_CS5_reserved2_SHIFT 15
-
-/* NAND :: CONFIG_CS5 :: COL_ADR_BYTES [14:12] */
-#define BCHP_NAND_CONFIG_CS5_COL_ADR_BYTES_MASK 0x00007000
-#define BCHP_NAND_CONFIG_CS5_COL_ADR_BYTES_SHIFT 12
-
-/* NAND :: CONFIG_CS5 :: reserved3 [11:11] */
-#define BCHP_NAND_CONFIG_CS5_reserved3_MASK 0x00000800
-#define BCHP_NAND_CONFIG_CS5_reserved3_SHIFT 11
-
-/* NAND :: CONFIG_CS5 :: BLK_ADR_BYTES [10:08] */
-#define BCHP_NAND_CONFIG_CS5_BLK_ADR_BYTES_MASK 0x00000700
-#define BCHP_NAND_CONFIG_CS5_BLK_ADR_BYTES_SHIFT 8
-
-/* NAND :: CONFIG_CS5 :: reserved4 [07:00] */
-#define BCHP_NAND_CONFIG_CS5_reserved4_MASK 0x000000ff
-#define BCHP_NAND_CONFIG_CS5_reserved4_SHIFT 0
-
-/***************************************************************************
- *TIMING_1_CS5 - Nand Flash Timing Parameters 1
- ***************************************************************************/
-/* NAND :: TIMING_1_CS5 :: tWP [31:28] */
-#define BCHP_NAND_TIMING_1_CS5_tWP_MASK 0xf0000000
-#define BCHP_NAND_TIMING_1_CS5_tWP_SHIFT 28
-#define BCHP_NAND_TIMING_1_CS5_tWP_DEFAULT 0x00000006
-
-/* NAND :: TIMING_1_CS5 :: tWH [27:24] */
-#define BCHP_NAND_TIMING_1_CS5_tWH_MASK 0x0f000000
-#define BCHP_NAND_TIMING_1_CS5_tWH_SHIFT 24
-#define BCHP_NAND_TIMING_1_CS5_tWH_DEFAULT 0x00000005
-
-/* NAND :: TIMING_1_CS5 :: tRP [23:20] */
-#define BCHP_NAND_TIMING_1_CS5_tRP_MASK 0x00f00000
-#define BCHP_NAND_TIMING_1_CS5_tRP_SHIFT 20
-#define BCHP_NAND_TIMING_1_CS5_tRP_DEFAULT 0x00000007
-
-/* NAND :: TIMING_1_CS5 :: tREH [19:16] */
-#define BCHP_NAND_TIMING_1_CS5_tREH_MASK 0x000f0000
-#define BCHP_NAND_TIMING_1_CS5_tREH_SHIFT 16
-#define BCHP_NAND_TIMING_1_CS5_tREH_DEFAULT 0x00000004
-
-/* NAND :: TIMING_1_CS5 :: tCS [15:12] */
-#define BCHP_NAND_TIMING_1_CS5_tCS_MASK 0x0000f000
-#define BCHP_NAND_TIMING_1_CS5_tCS_SHIFT 12
-#define BCHP_NAND_TIMING_1_CS5_tCS_DEFAULT 0x00000008
-
-/* NAND :: TIMING_1_CS5 :: tCLH [11:08] */
-#define BCHP_NAND_TIMING_1_CS5_tCLH_MASK 0x00000f00
-#define BCHP_NAND_TIMING_1_CS5_tCLH_SHIFT 8
-#define BCHP_NAND_TIMING_1_CS5_tCLH_DEFAULT 0x00000004
-
-/* NAND :: TIMING_1_CS5 :: tALH [07:04] */
-#define BCHP_NAND_TIMING_1_CS5_tALH_MASK 0x000000f0
-#define BCHP_NAND_TIMING_1_CS5_tALH_SHIFT 4
-#define BCHP_NAND_TIMING_1_CS5_tALH_DEFAULT 0x00000005
-
-/* NAND :: TIMING_1_CS5 :: tADL [03:00] */
-#define BCHP_NAND_TIMING_1_CS5_tADL_MASK 0x0000000f
-#define BCHP_NAND_TIMING_1_CS5_tADL_SHIFT 0
-#define BCHP_NAND_TIMING_1_CS5_tADL_DEFAULT 0x0000000b
-
-/***************************************************************************
- *TIMING_2_CS5 - Nand Flash Timing Parameters 2
- ***************************************************************************/
-/* NAND :: TIMING_2_CS5 :: CLK_SELECT [31:31] */
-#define BCHP_NAND_TIMING_2_CS5_CLK_SELECT_MASK 0x80000000
-#define BCHP_NAND_TIMING_2_CS5_CLK_SELECT_SHIFT 31
-#define BCHP_NAND_TIMING_2_CS5_CLK_SELECT_DEFAULT 0x00000000
-#define BCHP_NAND_TIMING_2_CS5_CLK_SELECT_CLK_108 0
-#define BCHP_NAND_TIMING_2_CS5_CLK_SELECT_CLK_216 1
-
-/* NAND :: TIMING_2_CS5 :: reserved0 [30:13] */
-#define BCHP_NAND_TIMING_2_CS5_reserved0_MASK 0x7fffe000
-#define BCHP_NAND_TIMING_2_CS5_reserved0_SHIFT 13
-
-/* NAND :: TIMING_2_CS5 :: tWB [12:09] */
-#define BCHP_NAND_TIMING_2_CS5_tWB_MASK 0x00001e00
-#define BCHP_NAND_TIMING_2_CS5_tWB_SHIFT 9
-#define BCHP_NAND_TIMING_2_CS5_tWB_DEFAULT 0x0000000f
-
-/* NAND :: TIMING_2_CS5 :: tWHR [08:04] */
-#define BCHP_NAND_TIMING_2_CS5_tWHR_MASK 0x000001f0
-#define BCHP_NAND_TIMING_2_CS5_tWHR_SHIFT 4
-#define BCHP_NAND_TIMING_2_CS5_tWHR_DEFAULT 0x00000009
-
-/* NAND :: TIMING_2_CS5 :: tREAD [03:00] */
-#define BCHP_NAND_TIMING_2_CS5_tREAD_MASK 0x0000000f
-#define BCHP_NAND_TIMING_2_CS5_tREAD_SHIFT 0
-#define BCHP_NAND_TIMING_2_CS5_tREAD_DEFAULT 0x00000006
-
-/***************************************************************************
- *ACC_CONTROL_CS6 - Nand Flash Access Control
- ***************************************************************************/
-/* NAND :: ACC_CONTROL_CS6 :: RD_ECC_EN [31:31] */
-#define BCHP_NAND_ACC_CONTROL_CS6_RD_ECC_EN_MASK 0x80000000
-#define BCHP_NAND_ACC_CONTROL_CS6_RD_ECC_EN_SHIFT 31
-#define BCHP_NAND_ACC_CONTROL_CS6_RD_ECC_EN_DEFAULT 0x00000001
-
-/* NAND :: ACC_CONTROL_CS6 :: WR_ECC_EN [30:30] */
-#define BCHP_NAND_ACC_CONTROL_CS6_WR_ECC_EN_MASK 0x40000000
-#define BCHP_NAND_ACC_CONTROL_CS6_WR_ECC_EN_SHIFT 30
-#define BCHP_NAND_ACC_CONTROL_CS6_WR_ECC_EN_DEFAULT 0x00000001
-
-/* NAND :: ACC_CONTROL_CS6 :: CE_CARE [29:29] */
-#define BCHP_NAND_ACC_CONTROL_CS6_CE_CARE_MASK 0x20000000
-#define BCHP_NAND_ACC_CONTROL_CS6_CE_CARE_SHIFT 29
-#define BCHP_NAND_ACC_CONTROL_CS6_CE_CARE_DEFAULT 0x00000000
-
-/* NAND :: ACC_CONTROL_CS6 :: reserved0 [28:28] */
-#define BCHP_NAND_ACC_CONTROL_CS6_reserved0_MASK 0x10000000
-#define BCHP_NAND_ACC_CONTROL_CS6_reserved0_SHIFT 28
-
-/* NAND :: ACC_CONTROL_CS6 :: RD_ERASED_ECC_EN [27:27] */
-#define BCHP_NAND_ACC_CONTROL_CS6_RD_ERASED_ECC_EN_MASK 0x08000000
-#define BCHP_NAND_ACC_CONTROL_CS6_RD_ERASED_ECC_EN_SHIFT 27
-#define BCHP_NAND_ACC_CONTROL_CS6_RD_ERASED_ECC_EN_DEFAULT 0x00000000
-
-/* NAND :: ACC_CONTROL_CS6 :: PARTIAL_PAGE_EN [26:26] */
-#define BCHP_NAND_ACC_CONTROL_CS6_PARTIAL_PAGE_EN_MASK 0x04000000
-#define BCHP_NAND_ACC_CONTROL_CS6_PARTIAL_PAGE_EN_SHIFT 26
-#define BCHP_NAND_ACC_CONTROL_CS6_PARTIAL_PAGE_EN_DEFAULT 0x00000000
-
-/* NAND :: ACC_CONTROL_CS6 :: WR_PREEMPT_EN [25:25] */
-#define BCHP_NAND_ACC_CONTROL_CS6_WR_PREEMPT_EN_MASK 0x02000000
-#define BCHP_NAND_ACC_CONTROL_CS6_WR_PREEMPT_EN_SHIFT 25
-#define BCHP_NAND_ACC_CONTROL_CS6_WR_PREEMPT_EN_DEFAULT 0x00000001
-
-/* NAND :: ACC_CONTROL_CS6 :: PAGE_HIT_EN [24:24] */
-#define BCHP_NAND_ACC_CONTROL_CS6_PAGE_HIT_EN_MASK 0x01000000
-#define BCHP_NAND_ACC_CONTROL_CS6_PAGE_HIT_EN_SHIFT 24
-#define BCHP_NAND_ACC_CONTROL_CS6_PAGE_HIT_EN_DEFAULT 0x00000001
-
-/* NAND :: ACC_CONTROL_CS6 :: PREFETCH_EN [23:23] */
-#define BCHP_NAND_ACC_CONTROL_CS6_PREFETCH_EN_MASK 0x00800000
-#define BCHP_NAND_ACC_CONTROL_CS6_PREFETCH_EN_SHIFT 23
-#define BCHP_NAND_ACC_CONTROL_CS6_PREFETCH_EN_DEFAULT 0x00000000
-
-/* NAND :: ACC_CONTROL_CS6 :: CACHE_MODE_EN [22:22] */
-#define BCHP_NAND_ACC_CONTROL_CS6_CACHE_MODE_EN_MASK 0x00400000
-#define BCHP_NAND_ACC_CONTROL_CS6_CACHE_MODE_EN_SHIFT 22
-#define BCHP_NAND_ACC_CONTROL_CS6_CACHE_MODE_EN_DEFAULT 0x00000000
-
-/* NAND :: ACC_CONTROL_CS6 :: reserved1 [21:21] */
-#define BCHP_NAND_ACC_CONTROL_CS6_reserved1_MASK 0x00200000
-#define BCHP_NAND_ACC_CONTROL_CS6_reserved1_SHIFT 21
-
-/* NAND :: ACC_CONTROL_CS6 :: ECC_LEVEL [20:16] */
-#define BCHP_NAND_ACC_CONTROL_CS6_ECC_LEVEL_MASK 0x001f0000
-#define BCHP_NAND_ACC_CONTROL_CS6_ECC_LEVEL_SHIFT 16
-#define BCHP_NAND_ACC_CONTROL_CS6_ECC_LEVEL_DEFAULT 0x0000000f
-
-/* NAND :: ACC_CONTROL_CS6 :: reserved2 [15:08] */
-#define BCHP_NAND_ACC_CONTROL_CS6_reserved2_MASK 0x0000ff00
-#define BCHP_NAND_ACC_CONTROL_CS6_reserved2_SHIFT 8
-
-/* NAND :: ACC_CONTROL_CS6 :: SECTOR_SIZE_1K [07:07] */
-#define BCHP_NAND_ACC_CONTROL_CS6_SECTOR_SIZE_1K_MASK 0x00000080
-#define BCHP_NAND_ACC_CONTROL_CS6_SECTOR_SIZE_1K_SHIFT 7
-#define BCHP_NAND_ACC_CONTROL_CS6_SECTOR_SIZE_1K_DEFAULT 0x00000000
-
-/* NAND :: ACC_CONTROL_CS6 :: SPARE_AREA_SIZE [06:00] */
-#define BCHP_NAND_ACC_CONTROL_CS6_SPARE_AREA_SIZE_MASK 0x0000007f
-#define BCHP_NAND_ACC_CONTROL_CS6_SPARE_AREA_SIZE_SHIFT 0
-#define BCHP_NAND_ACC_CONTROL_CS6_SPARE_AREA_SIZE_DEFAULT 0x00000010
-
-/***************************************************************************
- *CONFIG_CS6 - Nand Flash Config
- ***************************************************************************/
-/* NAND :: CONFIG_CS6 :: CONFIG_LOCK [31:31] */
-#define BCHP_NAND_CONFIG_CS6_CONFIG_LOCK_MASK 0x80000000
-#define BCHP_NAND_CONFIG_CS6_CONFIG_LOCK_SHIFT 31
-#define BCHP_NAND_CONFIG_CS6_CONFIG_LOCK_DEFAULT 0x00000000
-
-/* NAND :: CONFIG_CS6 :: BLOCK_SIZE [30:28] */
-#define BCHP_NAND_CONFIG_CS6_BLOCK_SIZE_MASK 0x70000000
-#define BCHP_NAND_CONFIG_CS6_BLOCK_SIZE_SHIFT 28
-#define BCHP_NAND_CONFIG_CS6_BLOCK_SIZE_BK_SIZE_2048KB 6
-#define BCHP_NAND_CONFIG_CS6_BLOCK_SIZE_BK_SIZE_1024KB 5
-#define BCHP_NAND_CONFIG_CS6_BLOCK_SIZE_BK_SIZE_512KB 4
-#define BCHP_NAND_CONFIG_CS6_BLOCK_SIZE_BK_SIZE_256KB 3
-#define BCHP_NAND_CONFIG_CS6_BLOCK_SIZE_BK_SIZE_128KB 2
-#define BCHP_NAND_CONFIG_CS6_BLOCK_SIZE_BK_SIZE_16KB 1
-#define BCHP_NAND_CONFIG_CS6_BLOCK_SIZE_BK_SIZE_8KB 0
-
-/* NAND :: CONFIG_CS6 :: DEVICE_SIZE [27:24] */
-#define BCHP_NAND_CONFIG_CS6_DEVICE_SIZE_MASK 0x0f000000
-#define BCHP_NAND_CONFIG_CS6_DEVICE_SIZE_SHIFT 24
-#define BCHP_NAND_CONFIG_CS6_DEVICE_SIZE_DVC_SIZE_4MB 0
-#define BCHP_NAND_CONFIG_CS6_DEVICE_SIZE_DVC_SIZE_8MB 1
-#define BCHP_NAND_CONFIG_CS6_DEVICE_SIZE_DVC_SIZE_16MB 2
-#define BCHP_NAND_CONFIG_CS6_DEVICE_SIZE_DVC_SIZE_32MB 3
-#define BCHP_NAND_CONFIG_CS6_DEVICE_SIZE_DVC_SIZE_64MB 4
-#define BCHP_NAND_CONFIG_CS6_DEVICE_SIZE_DVC_SIZE_128MB 5
-#define BCHP_NAND_CONFIG_CS6_DEVICE_SIZE_DVC_SIZE_256MB 6
-#define BCHP_NAND_CONFIG_CS6_DEVICE_SIZE_DVC_SIZE_512MB 7
-#define BCHP_NAND_CONFIG_CS6_DEVICE_SIZE_DVC_SIZE_1GB 8
-#define BCHP_NAND_CONFIG_CS6_DEVICE_SIZE_DVC_SIZE_2GB 9
-#define BCHP_NAND_CONFIG_CS6_DEVICE_SIZE_DVC_SIZE_4GB 10
-#define BCHP_NAND_CONFIG_CS6_DEVICE_SIZE_DVC_SIZE_8GB 11
-#define BCHP_NAND_CONFIG_CS6_DEVICE_SIZE_DVC_SIZE_16GB 12
-#define BCHP_NAND_CONFIG_CS6_DEVICE_SIZE_DVC_SIZE_32GB 13
-#define BCHP_NAND_CONFIG_CS6_DEVICE_SIZE_DVC_SIZE_64GB 14
-#define BCHP_NAND_CONFIG_CS6_DEVICE_SIZE_DVC_SIZE_128GB 15
-
-/* NAND :: CONFIG_CS6 :: DEVICE_WIDTH [23:23] */
-#define BCHP_NAND_CONFIG_CS6_DEVICE_WIDTH_MASK 0x00800000
-#define BCHP_NAND_CONFIG_CS6_DEVICE_WIDTH_SHIFT 23
-#define BCHP_NAND_CONFIG_CS6_DEVICE_WIDTH_DVC_WIDTH_8 0
-#define BCHP_NAND_CONFIG_CS6_DEVICE_WIDTH_DVC_WIDTH_16 1
-
-/* NAND :: CONFIG_CS6 :: reserved0 [22:22] */
-#define BCHP_NAND_CONFIG_CS6_reserved0_MASK 0x00400000
-#define BCHP_NAND_CONFIG_CS6_reserved0_SHIFT 22
-
-/* NAND :: CONFIG_CS6 :: PAGE_SIZE [21:20] */
-#define BCHP_NAND_CONFIG_CS6_PAGE_SIZE_MASK 0x00300000
-#define BCHP_NAND_CONFIG_CS6_PAGE_SIZE_SHIFT 20
-#define BCHP_NAND_CONFIG_CS6_PAGE_SIZE_PG_SIZE_512 0
-#define BCHP_NAND_CONFIG_CS6_PAGE_SIZE_PG_SIZE_2KB 1
-#define BCHP_NAND_CONFIG_CS6_PAGE_SIZE_PG_SIZE_4KB 2
-#define BCHP_NAND_CONFIG_CS6_PAGE_SIZE_PG_SIZE_8KB 3
-
-/* NAND :: CONFIG_CS6 :: reserved1 [19:19] */
-#define BCHP_NAND_CONFIG_CS6_reserved1_MASK 0x00080000
-#define BCHP_NAND_CONFIG_CS6_reserved1_SHIFT 19
-
-/* NAND :: CONFIG_CS6 :: FUL_ADR_BYTES [18:16] */
-#define BCHP_NAND_CONFIG_CS6_FUL_ADR_BYTES_MASK 0x00070000
-#define BCHP_NAND_CONFIG_CS6_FUL_ADR_BYTES_SHIFT 16
-
-/* NAND :: CONFIG_CS6 :: reserved2 [15:15] */
-#define BCHP_NAND_CONFIG_CS6_reserved2_MASK 0x00008000
-#define BCHP_NAND_CONFIG_CS6_reserved2_SHIFT 15
-
-/* NAND :: CONFIG_CS6 :: COL_ADR_BYTES [14:12] */
-#define BCHP_NAND_CONFIG_CS6_COL_ADR_BYTES_MASK 0x00007000
-#define BCHP_NAND_CONFIG_CS6_COL_ADR_BYTES_SHIFT 12
-
-/* NAND :: CONFIG_CS6 :: reserved3 [11:11] */
-#define BCHP_NAND_CONFIG_CS6_reserved3_MASK 0x00000800
-#define BCHP_NAND_CONFIG_CS6_reserved3_SHIFT 11
-
-/* NAND :: CONFIG_CS6 :: BLK_ADR_BYTES [10:08] */
-#define BCHP_NAND_CONFIG_CS6_BLK_ADR_BYTES_MASK 0x00000700
-#define BCHP_NAND_CONFIG_CS6_BLK_ADR_BYTES_SHIFT 8
-
-/* NAND :: CONFIG_CS6 :: reserved4 [07:00] */
-#define BCHP_NAND_CONFIG_CS6_reserved4_MASK 0x000000ff
-#define BCHP_NAND_CONFIG_CS6_reserved4_SHIFT 0
-
-/***************************************************************************
- *TIMING_1_CS6 - Nand Flash Timing Parameters 1
- ***************************************************************************/
-/* NAND :: TIMING_1_CS6 :: tWP [31:28] */
-#define BCHP_NAND_TIMING_1_CS6_tWP_MASK 0xf0000000
-#define BCHP_NAND_TIMING_1_CS6_tWP_SHIFT 28
-#define BCHP_NAND_TIMING_1_CS6_tWP_DEFAULT 0x00000006
-
-/* NAND :: TIMING_1_CS6 :: tWH [27:24] */
-#define BCHP_NAND_TIMING_1_CS6_tWH_MASK 0x0f000000
-#define BCHP_NAND_TIMING_1_CS6_tWH_SHIFT 24
-#define BCHP_NAND_TIMING_1_CS6_tWH_DEFAULT 0x00000005
-
-/* NAND :: TIMING_1_CS6 :: tRP [23:20] */
-#define BCHP_NAND_TIMING_1_CS6_tRP_MASK 0x00f00000
-#define BCHP_NAND_TIMING_1_CS6_tRP_SHIFT 20
-#define BCHP_NAND_TIMING_1_CS6_tRP_DEFAULT 0x00000007
-
-/* NAND :: TIMING_1_CS6 :: tREH [19:16] */
-#define BCHP_NAND_TIMING_1_CS6_tREH_MASK 0x000f0000
-#define BCHP_NAND_TIMING_1_CS6_tREH_SHIFT 16
-#define BCHP_NAND_TIMING_1_CS6_tREH_DEFAULT 0x00000004
-
-/* NAND :: TIMING_1_CS6 :: tCS [15:12] */
-#define BCHP_NAND_TIMING_1_CS6_tCS_MASK 0x0000f000
-#define BCHP_NAND_TIMING_1_CS6_tCS_SHIFT 12
-#define BCHP_NAND_TIMING_1_CS6_tCS_DEFAULT 0x00000008
-
-/* NAND :: TIMING_1_CS6 :: tCLH [11:08] */
-#define BCHP_NAND_TIMING_1_CS6_tCLH_MASK 0x00000f00
-#define BCHP_NAND_TIMING_1_CS6_tCLH_SHIFT 8
-#define BCHP_NAND_TIMING_1_CS6_tCLH_DEFAULT 0x00000004
-
-/* NAND :: TIMING_1_CS6 :: tALH [07:04] */
-#define BCHP_NAND_TIMING_1_CS6_tALH_MASK 0x000000f0
-#define BCHP_NAND_TIMING_1_CS6_tALH_SHIFT 4
-#define BCHP_NAND_TIMING_1_CS6_tALH_DEFAULT 0x00000005
-
-/* NAND :: TIMING_1_CS6 :: tADL [03:00] */
-#define BCHP_NAND_TIMING_1_CS6_tADL_MASK 0x0000000f
-#define BCHP_NAND_TIMING_1_CS6_tADL_SHIFT 0
-#define BCHP_NAND_TIMING_1_CS6_tADL_DEFAULT 0x0000000b
-
-/***************************************************************************
- *TIMING_2_CS6 - Nand Flash Timing Parameters 2
- ***************************************************************************/
-/* NAND :: TIMING_2_CS6 :: CLK_SELECT [31:31] */
-#define BCHP_NAND_TIMING_2_CS6_CLK_SELECT_MASK 0x80000000
-#define BCHP_NAND_TIMING_2_CS6_CLK_SELECT_SHIFT 31
-#define BCHP_NAND_TIMING_2_CS6_CLK_SELECT_DEFAULT 0x00000000
-#define BCHP_NAND_TIMING_2_CS6_CLK_SELECT_CLK_108 0
-#define BCHP_NAND_TIMING_2_CS6_CLK_SELECT_CLK_216 1
-
-/* NAND :: TIMING_2_CS6 :: reserved0 [30:13] */
-#define BCHP_NAND_TIMING_2_CS6_reserved0_MASK 0x7fffe000
-#define BCHP_NAND_TIMING_2_CS6_reserved0_SHIFT 13
-
-/* NAND :: TIMING_2_CS6 :: tWB [12:09] */
-#define BCHP_NAND_TIMING_2_CS6_tWB_MASK 0x00001e00
-#define BCHP_NAND_TIMING_2_CS6_tWB_SHIFT 9
-#define BCHP_NAND_TIMING_2_CS6_tWB_DEFAULT 0x0000000f
-
-/* NAND :: TIMING_2_CS6 :: tWHR [08:04] */
-#define BCHP_NAND_TIMING_2_CS6_tWHR_MASK 0x000001f0
-#define BCHP_NAND_TIMING_2_CS6_tWHR_SHIFT 4
-#define BCHP_NAND_TIMING_2_CS6_tWHR_DEFAULT 0x00000009
-
-/* NAND :: TIMING_2_CS6 :: tREAD [03:00] */
-#define BCHP_NAND_TIMING_2_CS6_tREAD_MASK 0x0000000f
-#define BCHP_NAND_TIMING_2_CS6_tREAD_SHIFT 0
-#define BCHP_NAND_TIMING_2_CS6_tREAD_DEFAULT 0x00000006
-
-/***************************************************************************
- *CORR_STAT_THRESHOLD - Correctable Error Reporting Threshold
- ***************************************************************************/
-/* NAND :: CORR_STAT_THRESHOLD :: reserved0 [31:30] */
-#define BCHP_NAND_CORR_STAT_THRESHOLD_reserved0_MASK 0xc0000000
-#define BCHP_NAND_CORR_STAT_THRESHOLD_reserved0_SHIFT 30
-
-/* NAND :: CORR_STAT_THRESHOLD :: CORR_STAT_THRESHOLD_CS4 [29:24] */
-#define BCHP_NAND_CORR_STAT_THRESHOLD_CORR_STAT_THRESHOLD_CS4_MASK 0x3f000000
-#define BCHP_NAND_CORR_STAT_THRESHOLD_CORR_STAT_THRESHOLD_CS4_SHIFT 24
-#define BCHP_NAND_CORR_STAT_THRESHOLD_CORR_STAT_THRESHOLD_CS4_DEFAULT 0x00000001
-
-/* NAND :: CORR_STAT_THRESHOLD :: CORR_STAT_THRESHOLD_CS3 [23:18] */
-#define BCHP_NAND_CORR_STAT_THRESHOLD_CORR_STAT_THRESHOLD_CS3_MASK 0x00fc0000
-#define BCHP_NAND_CORR_STAT_THRESHOLD_CORR_STAT_THRESHOLD_CS3_SHIFT 18
-#define BCHP_NAND_CORR_STAT_THRESHOLD_CORR_STAT_THRESHOLD_CS3_DEFAULT 0x00000001
-
-/* NAND :: CORR_STAT_THRESHOLD :: CORR_STAT_THRESHOLD_CS2 [17:12] */
-#define BCHP_NAND_CORR_STAT_THRESHOLD_CORR_STAT_THRESHOLD_CS2_MASK 0x0003f000
-#define BCHP_NAND_CORR_STAT_THRESHOLD_CORR_STAT_THRESHOLD_CS2_SHIFT 12
-#define BCHP_NAND_CORR_STAT_THRESHOLD_CORR_STAT_THRESHOLD_CS2_DEFAULT 0x00000001
-
-/* NAND :: CORR_STAT_THRESHOLD :: CORR_STAT_THRESHOLD_CS1 [11:06] */
-#define BCHP_NAND_CORR_STAT_THRESHOLD_CORR_STAT_THRESHOLD_CS1_MASK 0x00000fc0
-#define BCHP_NAND_CORR_STAT_THRESHOLD_CORR_STAT_THRESHOLD_CS1_SHIFT 6
-#define BCHP_NAND_CORR_STAT_THRESHOLD_CORR_STAT_THRESHOLD_CS1_DEFAULT 0x00000001
-
-/* NAND :: CORR_STAT_THRESHOLD :: CORR_STAT_THRESHOLD_CS0 [05:00] */
-#define BCHP_NAND_CORR_STAT_THRESHOLD_CORR_STAT_THRESHOLD_CS0_MASK 0x0000003f
-#define BCHP_NAND_CORR_STAT_THRESHOLD_CORR_STAT_THRESHOLD_CS0_SHIFT 0
-#define BCHP_NAND_CORR_STAT_THRESHOLD_CORR_STAT_THRESHOLD_CS0_DEFAULT 0x00000001
-
-/***************************************************************************
- *CORR_STAT_THRESHOLD_EXT - Correctable Error Reporting Threshold
- ***************************************************************************/
-/* NAND :: CORR_STAT_THRESHOLD_EXT :: reserved0 [31:12] */
-#define BCHP_NAND_CORR_STAT_THRESHOLD_EXT_reserved0_MASK 0xfffff000
-#define BCHP_NAND_CORR_STAT_THRESHOLD_EXT_reserved0_SHIFT 12
-
-/* NAND :: CORR_STAT_THRESHOLD_EXT :: CORR_STAT_THRESHOLD_CS6 [11:06] */
-#define BCHP_NAND_CORR_STAT_THRESHOLD_EXT_CORR_STAT_THRESHOLD_CS6_MASK 0x00000fc0
-#define BCHP_NAND_CORR_STAT_THRESHOLD_EXT_CORR_STAT_THRESHOLD_CS6_SHIFT 6
-#define BCHP_NAND_CORR_STAT_THRESHOLD_EXT_CORR_STAT_THRESHOLD_CS6_DEFAULT 0x00000001
-
-/* NAND :: CORR_STAT_THRESHOLD_EXT :: CORR_STAT_THRESHOLD_CS5 [05:00] */
-#define BCHP_NAND_CORR_STAT_THRESHOLD_EXT_CORR_STAT_THRESHOLD_CS5_MASK 0x0000003f
-#define BCHP_NAND_CORR_STAT_THRESHOLD_EXT_CORR_STAT_THRESHOLD_CS5_SHIFT 0
-#define BCHP_NAND_CORR_STAT_THRESHOLD_EXT_CORR_STAT_THRESHOLD_CS5_DEFAULT 0x00000001
-
-/***************************************************************************
- *BLK_WR_PROTECT - Block Write Protect Enable and Size for EBI_CS0b
- ***************************************************************************/
-/* NAND :: BLK_WR_PROTECT :: BLK_END_ADDR [31:00] */
-#define BCHP_NAND_BLK_WR_PROTECT_BLK_END_ADDR_MASK 0xffffffff
-#define BCHP_NAND_BLK_WR_PROTECT_BLK_END_ADDR_SHIFT 0
-#define BCHP_NAND_BLK_WR_PROTECT_BLK_END_ADDR_DEFAULT 0x00000000
-
-/***************************************************************************
- *MULTIPLANE_OPCODES_1 - Nand Flash Multiplane Customerized Opcodes
- ***************************************************************************/
-/* NAND :: MULTIPLANE_OPCODES_1 :: ERASE_CYC2_OPCODE [31:24] */
-#define BCHP_NAND_MULTIPLANE_OPCODES_1_ERASE_CYC2_OPCODE_MASK 0xff000000
-#define BCHP_NAND_MULTIPLANE_OPCODES_1_ERASE_CYC2_OPCODE_SHIFT 24
-#define BCHP_NAND_MULTIPLANE_OPCODES_1_ERASE_CYC2_OPCODE_DEFAULT 0x000000d1
-
-/* NAND :: MULTIPLANE_OPCODES_1 :: READ_STATUS_OPCODE [23:16] */
-#define BCHP_NAND_MULTIPLANE_OPCODES_1_READ_STATUS_OPCODE_MASK 0x00ff0000
-#define BCHP_NAND_MULTIPLANE_OPCODES_1_READ_STATUS_OPCODE_SHIFT 16
-#define BCHP_NAND_MULTIPLANE_OPCODES_1_READ_STATUS_OPCODE_DEFAULT 0x00000070
-
-/* NAND :: MULTIPLANE_OPCODES_1 :: PROG_ODD_PLANE_OPCODE [15:08] */
-#define BCHP_NAND_MULTIPLANE_OPCODES_1_PROG_ODD_PLANE_OPCODE_MASK 0x0000ff00
-#define BCHP_NAND_MULTIPLANE_OPCODES_1_PROG_ODD_PLANE_OPCODE_SHIFT 8
-#define BCHP_NAND_MULTIPLANE_OPCODES_1_PROG_ODD_PLANE_OPCODE_DEFAULT 0x00000080
-
-/* NAND :: MULTIPLANE_OPCODES_1 :: PROG_TR_OPCODE [07:00] */
-#define BCHP_NAND_MULTIPLANE_OPCODES_1_PROG_TR_OPCODE_MASK 0x000000ff
-#define BCHP_NAND_MULTIPLANE_OPCODES_1_PROG_TR_OPCODE_SHIFT 0
-#define BCHP_NAND_MULTIPLANE_OPCODES_1_PROG_TR_OPCODE_DEFAULT 0x00000010
-
-/***************************************************************************
- *MULTIPLANE_OPCODES_2 - Nand Flash Multiplane Customerized Opcodes
- ***************************************************************************/
-/* NAND :: MULTIPLANE_OPCODES_2 :: PROG_CACHE_TR_OPCODE [31:24] */
-#define BCHP_NAND_MULTIPLANE_OPCODES_2_PROG_CACHE_TR_OPCODE_MASK 0xff000000
-#define BCHP_NAND_MULTIPLANE_OPCODES_2_PROG_CACHE_TR_OPCODE_SHIFT 24
-#define BCHP_NAND_MULTIPLANE_OPCODES_2_PROG_CACHE_TR_OPCODE_DEFAULT 0x00000015
-
-/* NAND :: MULTIPLANE_OPCODES_2 :: TWO_PLANE_READ_STATUS_OPCODE [23:16] */
-#define BCHP_NAND_MULTIPLANE_OPCODES_2_TWO_PLANE_READ_STATUS_OPCODE_MASK 0x00ff0000
-#define BCHP_NAND_MULTIPLANE_OPCODES_2_TWO_PLANE_READ_STATUS_OPCODE_SHIFT 16
-#define BCHP_NAND_MULTIPLANE_OPCODES_2_TWO_PLANE_READ_STATUS_OPCODE_DEFAULT 0x00000078
-
-/* NAND :: MULTIPLANE_OPCODES_2 :: READ_OPCODE [15:08] */
-#define BCHP_NAND_MULTIPLANE_OPCODES_2_READ_OPCODE_MASK 0x0000ff00
-#define BCHP_NAND_MULTIPLANE_OPCODES_2_READ_OPCODE_SHIFT 8
-#define BCHP_NAND_MULTIPLANE_OPCODES_2_READ_OPCODE_DEFAULT 0x00000000
-
-/* NAND :: MULTIPLANE_OPCODES_2 :: READ_RAND_OPCODE [07:00] */
-#define BCHP_NAND_MULTIPLANE_OPCODES_2_READ_RAND_OPCODE_MASK 0x000000ff
-#define BCHP_NAND_MULTIPLANE_OPCODES_2_READ_RAND_OPCODE_SHIFT 0
-#define BCHP_NAND_MULTIPLANE_OPCODES_2_READ_RAND_OPCODE_DEFAULT 0x00000000
-
-/***************************************************************************
- *MULTIPLANE_CTRL - Nand Flash Multiplane Control
- ***************************************************************************/
-/* NAND :: MULTIPLANE_CTRL :: ERASE_CYC2_OP_ENABLE [31:31] */
-#define BCHP_NAND_MULTIPLANE_CTRL_ERASE_CYC2_OP_ENABLE_MASK 0x80000000
-#define BCHP_NAND_MULTIPLANE_CTRL_ERASE_CYC2_OP_ENABLE_SHIFT 31
-#define BCHP_NAND_MULTIPLANE_CTRL_ERASE_CYC2_OP_ENABLE_DEFAULT 0x00000000
-
-/* NAND :: MULTIPLANE_CTRL :: READ_ADR_SIZE [30:30] */
-#define BCHP_NAND_MULTIPLANE_CTRL_READ_ADR_SIZE_MASK 0x40000000
-#define BCHP_NAND_MULTIPLANE_CTRL_READ_ADR_SIZE_SHIFT 30
-#define BCHP_NAND_MULTIPLANE_CTRL_READ_ADR_SIZE_DEFAULT 0x00000000
-
-/* NAND :: MULTIPLANE_CTRL :: READ_CYC_ADR_FLAG [29:29] */
-#define BCHP_NAND_MULTIPLANE_CTRL_READ_CYC_ADR_FLAG_MASK 0x20000000
-#define BCHP_NAND_MULTIPLANE_CTRL_READ_CYC_ADR_FLAG_SHIFT 29
-#define BCHP_NAND_MULTIPLANE_CTRL_READ_CYC_ADR_FLAG_DEFAULT 0x00000000
-
-/* NAND :: MULTIPLANE_CTRL :: READ_NEXT_PAGE_FLAG [28:28] */
-#define BCHP_NAND_MULTIPLANE_CTRL_READ_NEXT_PAGE_FLAG_MASK 0x10000000
-#define BCHP_NAND_MULTIPLANE_CTRL_READ_NEXT_PAGE_FLAG_SHIFT 28
-#define BCHP_NAND_MULTIPLANE_CTRL_READ_NEXT_PAGE_FLAG_DEFAULT 0x00000000
-
-/* NAND :: MULTIPLANE_CTRL :: reserved0 [27:00] */
-#define BCHP_NAND_MULTIPLANE_CTRL_reserved0_MASK 0x0fffffff
-#define BCHP_NAND_MULTIPLANE_CTRL_reserved0_SHIFT 0
-
-/***************************************************************************
- *UNCORR_ERROR_COUNT - Read Uncorrectable Event Count
- ***************************************************************************/
-/* NAND :: UNCORR_ERROR_COUNT :: UNCORR_ERROR_COUNT [31:00] */
-#define BCHP_NAND_UNCORR_ERROR_COUNT_UNCORR_ERROR_COUNT_MASK 0xffffffff
-#define BCHP_NAND_UNCORR_ERROR_COUNT_UNCORR_ERROR_COUNT_SHIFT 0
-#define BCHP_NAND_UNCORR_ERROR_COUNT_UNCORR_ERROR_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *CORR_ERROR_COUNT - Read Error Count
- ***************************************************************************/
-/* NAND :: CORR_ERROR_COUNT :: CORR_ERROR_COUNT [31:00] */
-#define BCHP_NAND_CORR_ERROR_COUNT_CORR_ERROR_COUNT_MASK 0xffffffff
-#define BCHP_NAND_CORR_ERROR_COUNT_CORR_ERROR_COUNT_SHIFT 0
-#define BCHP_NAND_CORR_ERROR_COUNT_CORR_ERROR_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *READ_ERROR_COUNT - Read Error Count
- ***************************************************************************/
-/* NAND :: READ_ERROR_COUNT :: READ_ERROR_COUNT [31:00] */
-#define BCHP_NAND_READ_ERROR_COUNT_READ_ERROR_COUNT_MASK 0xffffffff
-#define BCHP_NAND_READ_ERROR_COUNT_READ_ERROR_COUNT_SHIFT 0
-#define BCHP_NAND_READ_ERROR_COUNT_READ_ERROR_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *BLOCK_LOCK_STATUS - Nand Flash Block Lock Status
- ***************************************************************************/
-/* NAND :: BLOCK_LOCK_STATUS :: reserved0 [31:08] */
-#define BCHP_NAND_BLOCK_LOCK_STATUS_reserved0_MASK 0xffffff00
-#define BCHP_NAND_BLOCK_LOCK_STATUS_reserved0_SHIFT 8
-
-/* NAND :: BLOCK_LOCK_STATUS :: STATUS [07:00] */
-#define BCHP_NAND_BLOCK_LOCK_STATUS_STATUS_MASK 0x000000ff
-#define BCHP_NAND_BLOCK_LOCK_STATUS_STATUS_SHIFT 0
-#define BCHP_NAND_BLOCK_LOCK_STATUS_STATUS_DEFAULT 0x00000000
-
-/***************************************************************************
- *ECC_CORR_EXT_ADDR - ECC Correctable Error Extended Address
- ***************************************************************************/
-/* NAND :: ECC_CORR_EXT_ADDR :: reserved0 [31:19] */
-#define BCHP_NAND_ECC_CORR_EXT_ADDR_reserved0_MASK 0xfff80000
-#define BCHP_NAND_ECC_CORR_EXT_ADDR_reserved0_SHIFT 19
-
-/* NAND :: ECC_CORR_EXT_ADDR :: CS_SEL [18:16] */
-#define BCHP_NAND_ECC_CORR_EXT_ADDR_CS_SEL_MASK 0x00070000
-#define BCHP_NAND_ECC_CORR_EXT_ADDR_CS_SEL_SHIFT 16
-#define BCHP_NAND_ECC_CORR_EXT_ADDR_CS_SEL_DEFAULT 0x00000000
-
-/* NAND :: ECC_CORR_EXT_ADDR :: EXT_ADDRESS [15:00] */
-#define BCHP_NAND_ECC_CORR_EXT_ADDR_EXT_ADDRESS_MASK 0x0000ffff
-#define BCHP_NAND_ECC_CORR_EXT_ADDR_EXT_ADDRESS_SHIFT 0
-#define BCHP_NAND_ECC_CORR_EXT_ADDR_EXT_ADDRESS_DEFAULT 0x00000000
-
-/***************************************************************************
- *ECC_CORR_ADDR - ECC Correctable Error Address
- ***************************************************************************/
-/* NAND :: ECC_CORR_ADDR :: ADDRESS [31:00] */
-#define BCHP_NAND_ECC_CORR_ADDR_ADDRESS_MASK 0xffffffff
-#define BCHP_NAND_ECC_CORR_ADDR_ADDRESS_SHIFT 0
-#define BCHP_NAND_ECC_CORR_ADDR_ADDRESS_DEFAULT 0x00000000
-
-/***************************************************************************
- *ECC_UNC_EXT_ADDR - ECC Uncorrectable Error Extended Address
- ***************************************************************************/
-/* NAND :: ECC_UNC_EXT_ADDR :: reserved0 [31:19] */
-#define BCHP_NAND_ECC_UNC_EXT_ADDR_reserved0_MASK 0xfff80000
-#define BCHP_NAND_ECC_UNC_EXT_ADDR_reserved0_SHIFT 19
-
-/* NAND :: ECC_UNC_EXT_ADDR :: CS_SEL [18:16] */
-#define BCHP_NAND_ECC_UNC_EXT_ADDR_CS_SEL_MASK 0x00070000
-#define BCHP_NAND_ECC_UNC_EXT_ADDR_CS_SEL_SHIFT 16
-#define BCHP_NAND_ECC_UNC_EXT_ADDR_CS_SEL_DEFAULT 0x00000000
-
-/* NAND :: ECC_UNC_EXT_ADDR :: EXT_ADDRESS [15:00] */
-#define BCHP_NAND_ECC_UNC_EXT_ADDR_EXT_ADDRESS_MASK 0x0000ffff
-#define BCHP_NAND_ECC_UNC_EXT_ADDR_EXT_ADDRESS_SHIFT 0
-#define BCHP_NAND_ECC_UNC_EXT_ADDR_EXT_ADDRESS_DEFAULT 0x00000000
-
-/***************************************************************************
- *ECC_UNC_ADDR - ECC Uncorrectable Error Address
- ***************************************************************************/
-/* NAND :: ECC_UNC_ADDR :: ADDRESS [31:00] */
-#define BCHP_NAND_ECC_UNC_ADDR_ADDRESS_MASK 0xffffffff
-#define BCHP_NAND_ECC_UNC_ADDR_ADDRESS_SHIFT 0
-#define BCHP_NAND_ECC_UNC_ADDR_ADDRESS_DEFAULT 0x00000000
-
-/***************************************************************************
- *FLASH_READ_EXT_ADDR - Flash Read Data Extended Address
- ***************************************************************************/
-/* NAND :: FLASH_READ_EXT_ADDR :: reserved0 [31:19] */
-#define BCHP_NAND_FLASH_READ_EXT_ADDR_reserved0_MASK 0xfff80000
-#define BCHP_NAND_FLASH_READ_EXT_ADDR_reserved0_SHIFT 19
-
-/* NAND :: FLASH_READ_EXT_ADDR :: CS_SEL [18:16] */
-#define BCHP_NAND_FLASH_READ_EXT_ADDR_CS_SEL_MASK 0x00070000
-#define BCHP_NAND_FLASH_READ_EXT_ADDR_CS_SEL_SHIFT 16
-#define BCHP_NAND_FLASH_READ_EXT_ADDR_CS_SEL_DEFAULT 0x00000000
-
-/* NAND :: FLASH_READ_EXT_ADDR :: EXT_ADDRESS [15:00] */
-#define BCHP_NAND_FLASH_READ_EXT_ADDR_EXT_ADDRESS_MASK 0x0000ffff
-#define BCHP_NAND_FLASH_READ_EXT_ADDR_EXT_ADDRESS_SHIFT 0
-#define BCHP_NAND_FLASH_READ_EXT_ADDR_EXT_ADDRESS_DEFAULT 0x00000000
-
-/***************************************************************************
- *FLASH_READ_ADDR - Flash Read Data Address
- ***************************************************************************/
-/* NAND :: FLASH_READ_ADDR :: ADDRESS [31:00] */
-#define BCHP_NAND_FLASH_READ_ADDR_ADDRESS_MASK 0xffffffff
-#define BCHP_NAND_FLASH_READ_ADDR_ADDRESS_SHIFT 0
-#define BCHP_NAND_FLASH_READ_ADDR_ADDRESS_DEFAULT 0x00000000
-
-/***************************************************************************
- *PROGRAM_PAGE_EXT_ADDR - Page Program Extended Address
- ***************************************************************************/
-/* NAND :: PROGRAM_PAGE_EXT_ADDR :: reserved0 [31:19] */
-#define BCHP_NAND_PROGRAM_PAGE_EXT_ADDR_reserved0_MASK 0xfff80000
-#define BCHP_NAND_PROGRAM_PAGE_EXT_ADDR_reserved0_SHIFT 19
-
-/* NAND :: PROGRAM_PAGE_EXT_ADDR :: CS_SEL [18:16] */
-#define BCHP_NAND_PROGRAM_PAGE_EXT_ADDR_CS_SEL_MASK 0x00070000
-#define BCHP_NAND_PROGRAM_PAGE_EXT_ADDR_CS_SEL_SHIFT 16
-#define BCHP_NAND_PROGRAM_PAGE_EXT_ADDR_CS_SEL_DEFAULT 0x00000000
-
-/* NAND :: PROGRAM_PAGE_EXT_ADDR :: EXT_ADDRESS [15:00] */
-#define BCHP_NAND_PROGRAM_PAGE_EXT_ADDR_EXT_ADDRESS_MASK 0x0000ffff
-#define BCHP_NAND_PROGRAM_PAGE_EXT_ADDR_EXT_ADDRESS_SHIFT 0
-#define BCHP_NAND_PROGRAM_PAGE_EXT_ADDR_EXT_ADDRESS_DEFAULT 0x00000000
-
-/***************************************************************************
- *PROGRAM_PAGE_ADDR - Page Program Address
- ***************************************************************************/
-/* NAND :: PROGRAM_PAGE_ADDR :: ADDRESS [31:00] */
-#define BCHP_NAND_PROGRAM_PAGE_ADDR_ADDRESS_MASK 0xffffffff
-#define BCHP_NAND_PROGRAM_PAGE_ADDR_ADDRESS_SHIFT 0
-#define BCHP_NAND_PROGRAM_PAGE_ADDR_ADDRESS_DEFAULT 0x00000000
-
-/***************************************************************************
- *COPY_BACK_EXT_ADDR - Copy Back Extended Address
- ***************************************************************************/
-/* NAND :: COPY_BACK_EXT_ADDR :: reserved0 [31:19] */
-#define BCHP_NAND_COPY_BACK_EXT_ADDR_reserved0_MASK 0xfff80000
-#define BCHP_NAND_COPY_BACK_EXT_ADDR_reserved0_SHIFT 19
-
-/* NAND :: COPY_BACK_EXT_ADDR :: CS_SEL [18:16] */
-#define BCHP_NAND_COPY_BACK_EXT_ADDR_CS_SEL_MASK 0x00070000
-#define BCHP_NAND_COPY_BACK_EXT_ADDR_CS_SEL_SHIFT 16
-#define BCHP_NAND_COPY_BACK_EXT_ADDR_CS_SEL_DEFAULT 0x00000000
-
-/* NAND :: COPY_BACK_EXT_ADDR :: EXT_ADDRESS [15:00] */
-#define BCHP_NAND_COPY_BACK_EXT_ADDR_EXT_ADDRESS_MASK 0x0000ffff
-#define BCHP_NAND_COPY_BACK_EXT_ADDR_EXT_ADDRESS_SHIFT 0
-#define BCHP_NAND_COPY_BACK_EXT_ADDR_EXT_ADDRESS_DEFAULT 0x00000000
-
-/***************************************************************************
- *COPY_BACK_ADDR - Copy Back Address
- ***************************************************************************/
-/* NAND :: COPY_BACK_ADDR :: ADDRESS [31:00] */
-#define BCHP_NAND_COPY_BACK_ADDR_ADDRESS_MASK 0xffffffff
-#define BCHP_NAND_COPY_BACK_ADDR_ADDRESS_SHIFT 0
-#define BCHP_NAND_COPY_BACK_ADDR_ADDRESS_DEFAULT 0x00000000
-
-/***************************************************************************
- *BLOCK_ERASE_EXT_ADDR - Block Erase Extended Address
- ***************************************************************************/
-/* NAND :: BLOCK_ERASE_EXT_ADDR :: reserved0 [31:19] */
-#define BCHP_NAND_BLOCK_ERASE_EXT_ADDR_reserved0_MASK 0xfff80000
-#define BCHP_NAND_BLOCK_ERASE_EXT_ADDR_reserved0_SHIFT 19
-
-/* NAND :: BLOCK_ERASE_EXT_ADDR :: CS_SEL [18:16] */
-#define BCHP_NAND_BLOCK_ERASE_EXT_ADDR_CS_SEL_MASK 0x00070000
-#define BCHP_NAND_BLOCK_ERASE_EXT_ADDR_CS_SEL_SHIFT 16
-#define BCHP_NAND_BLOCK_ERASE_EXT_ADDR_CS_SEL_DEFAULT 0x00000000
-
-/* NAND :: BLOCK_ERASE_EXT_ADDR :: EXT_ADDRESS [15:00] */
-#define BCHP_NAND_BLOCK_ERASE_EXT_ADDR_EXT_ADDRESS_MASK 0x0000ffff
-#define BCHP_NAND_BLOCK_ERASE_EXT_ADDR_EXT_ADDRESS_SHIFT 0
-#define BCHP_NAND_BLOCK_ERASE_EXT_ADDR_EXT_ADDRESS_DEFAULT 0x00000000
-
-/***************************************************************************
- *BLOCK_ERASE_ADDR - Block Erase Address
- ***************************************************************************/
-/* NAND :: BLOCK_ERASE_ADDR :: ADDRESS [31:00] */
-#define BCHP_NAND_BLOCK_ERASE_ADDR_ADDRESS_MASK 0xffffffff
-#define BCHP_NAND_BLOCK_ERASE_ADDR_ADDRESS_SHIFT 0
-#define BCHP_NAND_BLOCK_ERASE_ADDR_ADDRESS_DEFAULT 0x00000000
-
-/***************************************************************************
- *INV_READ_EXT_ADDR - Flash Invalid Data Extended Address
- ***************************************************************************/
-/* NAND :: INV_READ_EXT_ADDR :: reserved0 [31:19] */
-#define BCHP_NAND_INV_READ_EXT_ADDR_reserved0_MASK 0xfff80000
-#define BCHP_NAND_INV_READ_EXT_ADDR_reserved0_SHIFT 19
-
-/* NAND :: INV_READ_EXT_ADDR :: CS_SEL [18:16] */
-#define BCHP_NAND_INV_READ_EXT_ADDR_CS_SEL_MASK 0x00070000
-#define BCHP_NAND_INV_READ_EXT_ADDR_CS_SEL_SHIFT 16
-#define BCHP_NAND_INV_READ_EXT_ADDR_CS_SEL_DEFAULT 0x00000000
-
-/* NAND :: INV_READ_EXT_ADDR :: EXT_ADDRESS [15:00] */
-#define BCHP_NAND_INV_READ_EXT_ADDR_EXT_ADDRESS_MASK 0x0000ffff
-#define BCHP_NAND_INV_READ_EXT_ADDR_EXT_ADDRESS_SHIFT 0
-#define BCHP_NAND_INV_READ_EXT_ADDR_EXT_ADDRESS_DEFAULT 0x00000000
-
-/***************************************************************************
- *INV_READ_ADDR - Flash Invalid Data Address
- ***************************************************************************/
-/* NAND :: INV_READ_ADDR :: ADDRESS [31:00] */
-#define BCHP_NAND_INV_READ_ADDR_ADDRESS_MASK 0xffffffff
-#define BCHP_NAND_INV_READ_ADDR_ADDRESS_SHIFT 0
-#define BCHP_NAND_INV_READ_ADDR_ADDRESS_DEFAULT 0x00000000
-
-/***************************************************************************
- *INIT_STATUS - Initialization status
- ***************************************************************************/
-/* NAND :: INIT_STATUS :: ONFI_INIT_DONE [31:31] */
-#define BCHP_NAND_INIT_STATUS_ONFI_INIT_DONE_MASK 0x80000000
-#define BCHP_NAND_INIT_STATUS_ONFI_INIT_DONE_SHIFT 31
-
-/* NAND :: INIT_STATUS :: DEVICE_ID_INIT_DONE [30:30] */
-#define BCHP_NAND_INIT_STATUS_DEVICE_ID_INIT_DONE_MASK 0x40000000
-#define BCHP_NAND_INIT_STATUS_DEVICE_ID_INIT_DONE_SHIFT 30
-
-/* NAND :: INIT_STATUS :: INIT_SUCCESS [29:29] */
-#define BCHP_NAND_INIT_STATUS_INIT_SUCCESS_MASK 0x20000000
-#define BCHP_NAND_INIT_STATUS_INIT_SUCCESS_SHIFT 29
-
-/* NAND :: INIT_STATUS :: INIT_FAIL [28:28] */
-#define BCHP_NAND_INIT_STATUS_INIT_FAIL_MASK 0x10000000
-#define BCHP_NAND_INIT_STATUS_INIT_FAIL_SHIFT 28
-
-/* NAND :: INIT_STATUS :: INIT_BLANK [27:27] */
-#define BCHP_NAND_INIT_STATUS_INIT_BLANK_MASK 0x08000000
-#define BCHP_NAND_INIT_STATUS_INIT_BLANK_SHIFT 27
-
-/* NAND :: INIT_STATUS :: INIT_TIMEOUT [26:26] */
-#define BCHP_NAND_INIT_STATUS_INIT_TIMEOUT_MASK 0x04000000
-#define BCHP_NAND_INIT_STATUS_INIT_TIMEOUT_SHIFT 26
-
-/* NAND :: INIT_STATUS :: INIT_UNC_ERROR [25:25] */
-#define BCHP_NAND_INIT_STATUS_INIT_UNC_ERROR_MASK 0x02000000
-#define BCHP_NAND_INIT_STATUS_INIT_UNC_ERROR_SHIFT 25
-
-/* NAND :: INIT_STATUS :: INIT_CORR_ERROR [24:24] */
-#define BCHP_NAND_INIT_STATUS_INIT_CORR_ERROR_MASK 0x01000000
-#define BCHP_NAND_INIT_STATUS_INIT_CORR_ERROR_SHIFT 24
-
-/* NAND :: INIT_STATUS :: PARAMETER_READY [23:23] */
-#define BCHP_NAND_INIT_STATUS_PARAMETER_READY_MASK 0x00800000
-#define BCHP_NAND_INIT_STATUS_PARAMETER_READY_SHIFT 23
-
-/* NAND :: INIT_STATUS :: AUTHENTICATION_FAIL [22:22] */
-#define BCHP_NAND_INIT_STATUS_AUTHENTICATION_FAIL_MASK 0x00400000
-#define BCHP_NAND_INIT_STATUS_AUTHENTICATION_FAIL_SHIFT 22
-
-/* NAND :: INIT_STATUS :: reserved0 [21:00] */
-#define BCHP_NAND_INIT_STATUS_reserved0_MASK 0x003fffff
-#define BCHP_NAND_INIT_STATUS_reserved0_SHIFT 0
-
-/***************************************************************************
- *ONFI_STATUS - ONFI Status
- ***************************************************************************/
-/* NAND :: ONFI_STATUS :: ONFI_DEBUG_SEL [31:28] */
-#define BCHP_NAND_ONFI_STATUS_ONFI_DEBUG_SEL_MASK 0xf0000000
-#define BCHP_NAND_ONFI_STATUS_ONFI_DEBUG_SEL_SHIFT 28
-#define BCHP_NAND_ONFI_STATUS_ONFI_DEBUG_SEL_DEFAULT 0x00000000
-
-/* NAND :: ONFI_STATUS :: ONFI_detected [27:27] */
-#define BCHP_NAND_ONFI_STATUS_ONFI_detected_MASK 0x08000000
-#define BCHP_NAND_ONFI_STATUS_ONFI_detected_SHIFT 27
-
-/* NAND :: ONFI_STATUS :: reserved0 [26:06] */
-#define BCHP_NAND_ONFI_STATUS_reserved0_MASK 0x07ffffc0
-#define BCHP_NAND_ONFI_STATUS_reserved0_SHIFT 6
-
-/* NAND :: ONFI_STATUS :: ONFI_BAD_IDENT_PG2 [05:05] */
-#define BCHP_NAND_ONFI_STATUS_ONFI_BAD_IDENT_PG2_MASK 0x00000020
-#define BCHP_NAND_ONFI_STATUS_ONFI_BAD_IDENT_PG2_SHIFT 5
-
-/* NAND :: ONFI_STATUS :: ONFI_BAD_IDENT_PG1 [04:04] */
-#define BCHP_NAND_ONFI_STATUS_ONFI_BAD_IDENT_PG1_MASK 0x00000010
-#define BCHP_NAND_ONFI_STATUS_ONFI_BAD_IDENT_PG1_SHIFT 4
-
-/* NAND :: ONFI_STATUS :: ONFI_BAD_IDENT_PG0 [03:03] */
-#define BCHP_NAND_ONFI_STATUS_ONFI_BAD_IDENT_PG0_MASK 0x00000008
-#define BCHP_NAND_ONFI_STATUS_ONFI_BAD_IDENT_PG0_SHIFT 3
-
-/* NAND :: ONFI_STATUS :: ONFI_CRC_ERROR_PG2 [02:02] */
-#define BCHP_NAND_ONFI_STATUS_ONFI_CRC_ERROR_PG2_MASK 0x00000004
-#define BCHP_NAND_ONFI_STATUS_ONFI_CRC_ERROR_PG2_SHIFT 2
-
-/* NAND :: ONFI_STATUS :: ONFI_CRC_ERROR_PG1 [01:01] */
-#define BCHP_NAND_ONFI_STATUS_ONFI_CRC_ERROR_PG1_MASK 0x00000002
-#define BCHP_NAND_ONFI_STATUS_ONFI_CRC_ERROR_PG1_SHIFT 1
-
-/* NAND :: ONFI_STATUS :: ONFI_CRC_ERROR_PG0 [00:00] */
-#define BCHP_NAND_ONFI_STATUS_ONFI_CRC_ERROR_PG0_MASK 0x00000001
-#define BCHP_NAND_ONFI_STATUS_ONFI_CRC_ERROR_PG0_SHIFT 0
-
-/***************************************************************************
- *ONFI_DEBUG_DATA - ONFI Debug Data
- ***************************************************************************/
-/* NAND :: ONFI_DEBUG_DATA :: ONFI_DEBUG_DATA [31:00] */
-#define BCHP_NAND_ONFI_DEBUG_DATA_ONFI_DEBUG_DATA_MASK 0xffffffff
-#define BCHP_NAND_ONFI_DEBUG_DATA_ONFI_DEBUG_DATA_SHIFT 0
-
-/***************************************************************************
- *SEMAPHORE - Semaphore
- ***************************************************************************/
-/* NAND :: SEMAPHORE :: reserved0 [31:08] */
-#define BCHP_NAND_SEMAPHORE_reserved0_MASK 0xffffff00
-#define BCHP_NAND_SEMAPHORE_reserved0_SHIFT 8
-
-/* NAND :: SEMAPHORE :: semaphore_ctrl [07:00] */
-#define BCHP_NAND_SEMAPHORE_semaphore_ctrl_MASK 0x000000ff
-#define BCHP_NAND_SEMAPHORE_semaphore_ctrl_SHIFT 0
-#define BCHP_NAND_SEMAPHORE_semaphore_ctrl_DEFAULT 0x00000000
-
-/***************************************************************************
- *FLASH_DEVICE_ID - Nand Flash Device ID
- ***************************************************************************/
-/* NAND :: FLASH_DEVICE_ID :: BYTE_0 [31:24] */
-#define BCHP_NAND_FLASH_DEVICE_ID_BYTE_0_MASK 0xff000000
-#define BCHP_NAND_FLASH_DEVICE_ID_BYTE_0_SHIFT 24
-
-/* NAND :: FLASH_DEVICE_ID :: BYTE_1 [23:16] */
-#define BCHP_NAND_FLASH_DEVICE_ID_BYTE_1_MASK 0x00ff0000
-#define BCHP_NAND_FLASH_DEVICE_ID_BYTE_1_SHIFT 16
-
-/* NAND :: FLASH_DEVICE_ID :: BYTE_2 [15:08] */
-#define BCHP_NAND_FLASH_DEVICE_ID_BYTE_2_MASK 0x0000ff00
-#define BCHP_NAND_FLASH_DEVICE_ID_BYTE_2_SHIFT 8
-
-/* NAND :: FLASH_DEVICE_ID :: BYTE_3 [07:00] */
-#define BCHP_NAND_FLASH_DEVICE_ID_BYTE_3_MASK 0x000000ff
-#define BCHP_NAND_FLASH_DEVICE_ID_BYTE_3_SHIFT 0
-
-/***************************************************************************
- *FLASH_DEVICE_ID_EXT - Nand Flash Extended Device ID
- ***************************************************************************/
-/* NAND :: FLASH_DEVICE_ID_EXT :: BYTE_4 [31:24] */
-#define BCHP_NAND_FLASH_DEVICE_ID_EXT_BYTE_4_MASK 0xff000000
-#define BCHP_NAND_FLASH_DEVICE_ID_EXT_BYTE_4_SHIFT 24
-
-/* NAND :: FLASH_DEVICE_ID_EXT :: BYTE_5 [23:16] */
-#define BCHP_NAND_FLASH_DEVICE_ID_EXT_BYTE_5_MASK 0x00ff0000
-#define BCHP_NAND_FLASH_DEVICE_ID_EXT_BYTE_5_SHIFT 16
-
-/* NAND :: FLASH_DEVICE_ID_EXT :: BYTE_6 [15:08] */
-#define BCHP_NAND_FLASH_DEVICE_ID_EXT_BYTE_6_MASK 0x0000ff00
-#define BCHP_NAND_FLASH_DEVICE_ID_EXT_BYTE_6_SHIFT 8
-
-/* NAND :: FLASH_DEVICE_ID_EXT :: BYTE_7 [07:00] */
-#define BCHP_NAND_FLASH_DEVICE_ID_EXT_BYTE_7_MASK 0x000000ff
-#define BCHP_NAND_FLASH_DEVICE_ID_EXT_BYTE_7_SHIFT 0
-
-/***************************************************************************
- *LL_RDDATA - Nand Flash Low Level Read Data
- ***************************************************************************/
-/* NAND :: LL_RDDATA :: reserved0 [31:16] */
-#define BCHP_NAND_LL_RDDATA_reserved0_MASK 0xffff0000
-#define BCHP_NAND_LL_RDDATA_reserved0_SHIFT 16
-
-/* NAND :: LL_RDDATA :: DATA [15:00] */
-#define BCHP_NAND_LL_RDDATA_DATA_MASK 0x0000ffff
-#define BCHP_NAND_LL_RDDATA_DATA_SHIFT 0
-#define BCHP_NAND_LL_RDDATA_DATA_DEFAULT 0x00000000
-
-/***************************************************************************
- *SPARE_AREA_READ_OFS_0 - Nand Flash Spare Area Read Bytes 0-3
- ***************************************************************************/
-/* NAND :: SPARE_AREA_READ_OFS_0 :: BYTE_OFS_0 [31:24] */
-#define BCHP_NAND_SPARE_AREA_READ_OFS_0_BYTE_OFS_0_MASK 0xff000000
-#define BCHP_NAND_SPARE_AREA_READ_OFS_0_BYTE_OFS_0_SHIFT 24
-#define BCHP_NAND_SPARE_AREA_READ_OFS_0_BYTE_OFS_0_DEFAULT 0x000000ff
-
-/* NAND :: SPARE_AREA_READ_OFS_0 :: BYTE_OFS_1 [23:16] */
-#define BCHP_NAND_SPARE_AREA_READ_OFS_0_BYTE_OFS_1_MASK 0x00ff0000
-#define BCHP_NAND_SPARE_AREA_READ_OFS_0_BYTE_OFS_1_SHIFT 16
-#define BCHP_NAND_SPARE_AREA_READ_OFS_0_BYTE_OFS_1_DEFAULT 0x000000ff
-
-/* NAND :: SPARE_AREA_READ_OFS_0 :: BYTE_OFS_2 [15:08] */
-#define BCHP_NAND_SPARE_AREA_READ_OFS_0_BYTE_OFS_2_MASK 0x0000ff00
-#define BCHP_NAND_SPARE_AREA_READ_OFS_0_BYTE_OFS_2_SHIFT 8
-#define BCHP_NAND_SPARE_AREA_READ_OFS_0_BYTE_OFS_2_DEFAULT 0x000000ff
-
-/* NAND :: SPARE_AREA_READ_OFS_0 :: BYTE_OFS_3 [07:00] */
-#define BCHP_NAND_SPARE_AREA_READ_OFS_0_BYTE_OFS_3_MASK 0x000000ff
-#define BCHP_NAND_SPARE_AREA_READ_OFS_0_BYTE_OFS_3_SHIFT 0
-#define BCHP_NAND_SPARE_AREA_READ_OFS_0_BYTE_OFS_3_DEFAULT 0x000000ff
-
-/***************************************************************************
- *SPARE_AREA_READ_OFS_4 - Nand Flash Spare Area Read Bytes 4-7
- ***************************************************************************/
-/* NAND :: SPARE_AREA_READ_OFS_4 :: BYTE_OFS_4 [31:24] */
-#define BCHP_NAND_SPARE_AREA_READ_OFS_4_BYTE_OFS_4_MASK 0xff000000
-#define BCHP_NAND_SPARE_AREA_READ_OFS_4_BYTE_OFS_4_SHIFT 24
-#define BCHP_NAND_SPARE_AREA_READ_OFS_4_BYTE_OFS_4_DEFAULT 0x000000ff
-
-/* NAND :: SPARE_AREA_READ_OFS_4 :: BYTE_OFS_5 [23:16] */
-#define BCHP_NAND_SPARE_AREA_READ_OFS_4_BYTE_OFS_5_MASK 0x00ff0000
-#define BCHP_NAND_SPARE_AREA_READ_OFS_4_BYTE_OFS_5_SHIFT 16
-#define BCHP_NAND_SPARE_AREA_READ_OFS_4_BYTE_OFS_5_DEFAULT 0x000000ff
-
-/* NAND :: SPARE_AREA_READ_OFS_4 :: BYTE_OFS_6 [15:08] */
-#define BCHP_NAND_SPARE_AREA_READ_OFS_4_BYTE_OFS_6_MASK 0x0000ff00
-#define BCHP_NAND_SPARE_AREA_READ_OFS_4_BYTE_OFS_6_SHIFT 8
-#define BCHP_NAND_SPARE_AREA_READ_OFS_4_BYTE_OFS_6_DEFAULT 0x000000ff
-
-/* NAND :: SPARE_AREA_READ_OFS_4 :: BYTE_OFS_7 [07:00] */
-#define BCHP_NAND_SPARE_AREA_READ_OFS_4_BYTE_OFS_7_MASK 0x000000ff
-#define BCHP_NAND_SPARE_AREA_READ_OFS_4_BYTE_OFS_7_SHIFT 0
-#define BCHP_NAND_SPARE_AREA_READ_OFS_4_BYTE_OFS_7_DEFAULT 0x000000ff
-
-/***************************************************************************
- *SPARE_AREA_READ_OFS_8 - Nand Flash Spare Area Read Bytes 8-11
- ***************************************************************************/
-/* NAND :: SPARE_AREA_READ_OFS_8 :: BYTE_OFS_8 [31:24] */
-#define BCHP_NAND_SPARE_AREA_READ_OFS_8_BYTE_OFS_8_MASK 0xff000000
-#define BCHP_NAND_SPARE_AREA_READ_OFS_8_BYTE_OFS_8_SHIFT 24
-#define BCHP_NAND_SPARE_AREA_READ_OFS_8_BYTE_OFS_8_DEFAULT 0x000000ff
-
-/* NAND :: SPARE_AREA_READ_OFS_8 :: BYTE_OFS_9 [23:16] */
-#define BCHP_NAND_SPARE_AREA_READ_OFS_8_BYTE_OFS_9_MASK 0x00ff0000
-#define BCHP_NAND_SPARE_AREA_READ_OFS_8_BYTE_OFS_9_SHIFT 16
-#define BCHP_NAND_SPARE_AREA_READ_OFS_8_BYTE_OFS_9_DEFAULT 0x000000ff
-
-/* NAND :: SPARE_AREA_READ_OFS_8 :: BYTE_OFS_10 [15:08] */
-#define BCHP_NAND_SPARE_AREA_READ_OFS_8_BYTE_OFS_10_MASK 0x0000ff00
-#define BCHP_NAND_SPARE_AREA_READ_OFS_8_BYTE_OFS_10_SHIFT 8
-#define BCHP_NAND_SPARE_AREA_READ_OFS_8_BYTE_OFS_10_DEFAULT 0x000000ff
-
-/* NAND :: SPARE_AREA_READ_OFS_8 :: BYTE_OFS_11 [07:00] */
-#define BCHP_NAND_SPARE_AREA_READ_OFS_8_BYTE_OFS_11_MASK 0x000000ff
-#define BCHP_NAND_SPARE_AREA_READ_OFS_8_BYTE_OFS_11_SHIFT 0
-#define BCHP_NAND_SPARE_AREA_READ_OFS_8_BYTE_OFS_11_DEFAULT 0x000000ff
-
-/***************************************************************************
- *SPARE_AREA_READ_OFS_C - Nand Flash Spare Area Read Bytes 12-15
- ***************************************************************************/
-/* NAND :: SPARE_AREA_READ_OFS_C :: BYTE_OFS_12 [31:24] */
-#define BCHP_NAND_SPARE_AREA_READ_OFS_C_BYTE_OFS_12_MASK 0xff000000
-#define BCHP_NAND_SPARE_AREA_READ_OFS_C_BYTE_OFS_12_SHIFT 24
-#define BCHP_NAND_SPARE_AREA_READ_OFS_C_BYTE_OFS_12_DEFAULT 0x000000ff
-
-/* NAND :: SPARE_AREA_READ_OFS_C :: BYTE_OFS_13 [23:16] */
-#define BCHP_NAND_SPARE_AREA_READ_OFS_C_BYTE_OFS_13_MASK 0x00ff0000
-#define BCHP_NAND_SPARE_AREA_READ_OFS_C_BYTE_OFS_13_SHIFT 16
-#define BCHP_NAND_SPARE_AREA_READ_OFS_C_BYTE_OFS_13_DEFAULT 0x000000ff
-
-/* NAND :: SPARE_AREA_READ_OFS_C :: BYTE_OFS_14 [15:08] */
-#define BCHP_NAND_SPARE_AREA_READ_OFS_C_BYTE_OFS_14_MASK 0x0000ff00
-#define BCHP_NAND_SPARE_AREA_READ_OFS_C_BYTE_OFS_14_SHIFT 8
-#define BCHP_NAND_SPARE_AREA_READ_OFS_C_BYTE_OFS_14_DEFAULT 0x000000ff
-
-/* NAND :: SPARE_AREA_READ_OFS_C :: BYTE_OFS_15 [07:00] */
-#define BCHP_NAND_SPARE_AREA_READ_OFS_C_BYTE_OFS_15_MASK 0x000000ff
-#define BCHP_NAND_SPARE_AREA_READ_OFS_C_BYTE_OFS_15_SHIFT 0
-#define BCHP_NAND_SPARE_AREA_READ_OFS_C_BYTE_OFS_15_DEFAULT 0x000000ff
-
-/***************************************************************************
- *SPARE_AREA_READ_OFS_10 - Nand Flash Spare Area Read Bytes 16-19
- ***************************************************************************/
-/* NAND :: SPARE_AREA_READ_OFS_10 :: BYTE_OFS_16 [31:24] */
-#define BCHP_NAND_SPARE_AREA_READ_OFS_10_BYTE_OFS_16_MASK 0xff000000
-#define BCHP_NAND_SPARE_AREA_READ_OFS_10_BYTE_OFS_16_SHIFT 24
-#define BCHP_NAND_SPARE_AREA_READ_OFS_10_BYTE_OFS_16_DEFAULT 0x000000ff
-
-/* NAND :: SPARE_AREA_READ_OFS_10 :: BYTE_OFS_17 [23:16] */
-#define BCHP_NAND_SPARE_AREA_READ_OFS_10_BYTE_OFS_17_MASK 0x00ff0000
-#define BCHP_NAND_SPARE_AREA_READ_OFS_10_BYTE_OFS_17_SHIFT 16
-#define BCHP_NAND_SPARE_AREA_READ_OFS_10_BYTE_OFS_17_DEFAULT 0x000000ff
-
-/* NAND :: SPARE_AREA_READ_OFS_10 :: BYTE_OFS_18 [15:08] */
-#define BCHP_NAND_SPARE_AREA_READ_OFS_10_BYTE_OFS_18_MASK 0x0000ff00
-#define BCHP_NAND_SPARE_AREA_READ_OFS_10_BYTE_OFS_18_SHIFT 8
-#define BCHP_NAND_SPARE_AREA_READ_OFS_10_BYTE_OFS_18_DEFAULT 0x000000ff
-
-/* NAND :: SPARE_AREA_READ_OFS_10 :: BYTE_OFS_19 [07:00] */
-#define BCHP_NAND_SPARE_AREA_READ_OFS_10_BYTE_OFS_19_MASK 0x000000ff
-#define BCHP_NAND_SPARE_AREA_READ_OFS_10_BYTE_OFS_19_SHIFT 0
-#define BCHP_NAND_SPARE_AREA_READ_OFS_10_BYTE_OFS_19_DEFAULT 0x000000ff
-
-/***************************************************************************
- *SPARE_AREA_READ_OFS_14 - Nand Flash Spare Area Read Bytes 20-23
- ***************************************************************************/
-/* NAND :: SPARE_AREA_READ_OFS_14 :: BYTE_OFS_20 [31:24] */
-#define BCHP_NAND_SPARE_AREA_READ_OFS_14_BYTE_OFS_20_MASK 0xff000000
-#define BCHP_NAND_SPARE_AREA_READ_OFS_14_BYTE_OFS_20_SHIFT 24
-#define BCHP_NAND_SPARE_AREA_READ_OFS_14_BYTE_OFS_20_DEFAULT 0x000000ff
-
-/* NAND :: SPARE_AREA_READ_OFS_14 :: BYTE_OFS_21 [23:16] */
-#define BCHP_NAND_SPARE_AREA_READ_OFS_14_BYTE_OFS_21_MASK 0x00ff0000
-#define BCHP_NAND_SPARE_AREA_READ_OFS_14_BYTE_OFS_21_SHIFT 16
-#define BCHP_NAND_SPARE_AREA_READ_OFS_14_BYTE_OFS_21_DEFAULT 0x000000ff
-
-/* NAND :: SPARE_AREA_READ_OFS_14 :: BYTE_OFS_22 [15:08] */
-#define BCHP_NAND_SPARE_AREA_READ_OFS_14_BYTE_OFS_22_MASK 0x0000ff00
-#define BCHP_NAND_SPARE_AREA_READ_OFS_14_BYTE_OFS_22_SHIFT 8
-#define BCHP_NAND_SPARE_AREA_READ_OFS_14_BYTE_OFS_22_DEFAULT 0x000000ff
-
-/* NAND :: SPARE_AREA_READ_OFS_14 :: BYTE_OFS_23 [07:00] */
-#define BCHP_NAND_SPARE_AREA_READ_OFS_14_BYTE_OFS_23_MASK 0x000000ff
-#define BCHP_NAND_SPARE_AREA_READ_OFS_14_BYTE_OFS_23_SHIFT 0
-#define BCHP_NAND_SPARE_AREA_READ_OFS_14_BYTE_OFS_23_DEFAULT 0x000000ff
-
-/***************************************************************************
- *SPARE_AREA_READ_OFS_18 - Nand Flash Spare Area Read Bytes 24-27
- ***************************************************************************/
-/* NAND :: SPARE_AREA_READ_OFS_18 :: BYTE_OFS_24 [31:24] */
-#define BCHP_NAND_SPARE_AREA_READ_OFS_18_BYTE_OFS_24_MASK 0xff000000
-#define BCHP_NAND_SPARE_AREA_READ_OFS_18_BYTE_OFS_24_SHIFT 24
-#define BCHP_NAND_SPARE_AREA_READ_OFS_18_BYTE_OFS_24_DEFAULT 0x000000ff
-
-/* NAND :: SPARE_AREA_READ_OFS_18 :: BYTE_OFS_25 [23:16] */
-#define BCHP_NAND_SPARE_AREA_READ_OFS_18_BYTE_OFS_25_MASK 0x00ff0000
-#define BCHP_NAND_SPARE_AREA_READ_OFS_18_BYTE_OFS_25_SHIFT 16
-#define BCHP_NAND_SPARE_AREA_READ_OFS_18_BYTE_OFS_25_DEFAULT 0x000000ff
-
-/* NAND :: SPARE_AREA_READ_OFS_18 :: BYTE_OFS_26 [15:08] */
-#define BCHP_NAND_SPARE_AREA_READ_OFS_18_BYTE_OFS_26_MASK 0x0000ff00
-#define BCHP_NAND_SPARE_AREA_READ_OFS_18_BYTE_OFS_26_SHIFT 8
-#define BCHP_NAND_SPARE_AREA_READ_OFS_18_BYTE_OFS_26_DEFAULT 0x000000ff
-
-/* NAND :: SPARE_AREA_READ_OFS_18 :: BYTE_OFS_27 [07:00] */
-#define BCHP_NAND_SPARE_AREA_READ_OFS_18_BYTE_OFS_27_MASK 0x000000ff
-#define BCHP_NAND_SPARE_AREA_READ_OFS_18_BYTE_OFS_27_SHIFT 0
-#define BCHP_NAND_SPARE_AREA_READ_OFS_18_BYTE_OFS_27_DEFAULT 0x000000ff
-
-/***************************************************************************
- *SPARE_AREA_READ_OFS_1C - Nand Flash Spare Area Read Bytes 28-31
- ***************************************************************************/
-/* NAND :: SPARE_AREA_READ_OFS_1C :: BYTE_OFS_28 [31:24] */
-#define BCHP_NAND_SPARE_AREA_READ_OFS_1C_BYTE_OFS_28_MASK 0xff000000
-#define BCHP_NAND_SPARE_AREA_READ_OFS_1C_BYTE_OFS_28_SHIFT 24
-#define BCHP_NAND_SPARE_AREA_READ_OFS_1C_BYTE_OFS_28_DEFAULT 0x000000ff
-
-/* NAND :: SPARE_AREA_READ_OFS_1C :: BYTE_OFS_29 [23:16] */
-#define BCHP_NAND_SPARE_AREA_READ_OFS_1C_BYTE_OFS_29_MASK 0x00ff0000
-#define BCHP_NAND_SPARE_AREA_READ_OFS_1C_BYTE_OFS_29_SHIFT 16
-#define BCHP_NAND_SPARE_AREA_READ_OFS_1C_BYTE_OFS_29_DEFAULT 0x000000ff
-
-/* NAND :: SPARE_AREA_READ_OFS_1C :: BYTE_OFS_30 [15:08] */
-#define BCHP_NAND_SPARE_AREA_READ_OFS_1C_BYTE_OFS_30_MASK 0x0000ff00
-#define BCHP_NAND_SPARE_AREA_READ_OFS_1C_BYTE_OFS_30_SHIFT 8
-#define BCHP_NAND_SPARE_AREA_READ_OFS_1C_BYTE_OFS_30_DEFAULT 0x000000ff
-
-/* NAND :: SPARE_AREA_READ_OFS_1C :: BYTE_OFS_31 [07:00] */
-#define BCHP_NAND_SPARE_AREA_READ_OFS_1C_BYTE_OFS_31_MASK 0x000000ff
-#define BCHP_NAND_SPARE_AREA_READ_OFS_1C_BYTE_OFS_31_SHIFT 0
-#define BCHP_NAND_SPARE_AREA_READ_OFS_1C_BYTE_OFS_31_DEFAULT 0x000000ff
-
-/***************************************************************************
- *SPARE_AREA_READ_OFS_20 - Nand Flash Spare Area Read Bytes 32-35
- ***************************************************************************/
-/* NAND :: SPARE_AREA_READ_OFS_20 :: BYTE_OFS_32 [31:24] */
-#define BCHP_NAND_SPARE_AREA_READ_OFS_20_BYTE_OFS_32_MASK 0xff000000
-#define BCHP_NAND_SPARE_AREA_READ_OFS_20_BYTE_OFS_32_SHIFT 24
-#define BCHP_NAND_SPARE_AREA_READ_OFS_20_BYTE_OFS_32_DEFAULT 0x000000ff
-
-/* NAND :: SPARE_AREA_READ_OFS_20 :: BYTE_OFS_33 [23:16] */
-#define BCHP_NAND_SPARE_AREA_READ_OFS_20_BYTE_OFS_33_MASK 0x00ff0000
-#define BCHP_NAND_SPARE_AREA_READ_OFS_20_BYTE_OFS_33_SHIFT 16
-#define BCHP_NAND_SPARE_AREA_READ_OFS_20_BYTE_OFS_33_DEFAULT 0x000000ff
-
-/* NAND :: SPARE_AREA_READ_OFS_20 :: BYTE_OFS_34 [15:08] */
-#define BCHP_NAND_SPARE_AREA_READ_OFS_20_BYTE_OFS_34_MASK 0x0000ff00
-#define BCHP_NAND_SPARE_AREA_READ_OFS_20_BYTE_OFS_34_SHIFT 8
-#define BCHP_NAND_SPARE_AREA_READ_OFS_20_BYTE_OFS_34_DEFAULT 0x000000ff
-
-/* NAND :: SPARE_AREA_READ_OFS_20 :: BYTE_OFS_35 [07:00] */
-#define BCHP_NAND_SPARE_AREA_READ_OFS_20_BYTE_OFS_35_MASK 0x000000ff
-#define BCHP_NAND_SPARE_AREA_READ_OFS_20_BYTE_OFS_35_SHIFT 0
-#define BCHP_NAND_SPARE_AREA_READ_OFS_20_BYTE_OFS_35_DEFAULT 0x000000ff
-
-/***************************************************************************
- *SPARE_AREA_READ_OFS_24 - Nand Flash Spare Area Read Bytes 36-39
- ***************************************************************************/
-/* NAND :: SPARE_AREA_READ_OFS_24 :: BYTE_OFS_36 [31:24] */
-#define BCHP_NAND_SPARE_AREA_READ_OFS_24_BYTE_OFS_36_MASK 0xff000000
-#define BCHP_NAND_SPARE_AREA_READ_OFS_24_BYTE_OFS_36_SHIFT 24
-#define BCHP_NAND_SPARE_AREA_READ_OFS_24_BYTE_OFS_36_DEFAULT 0x000000ff
-
-/* NAND :: SPARE_AREA_READ_OFS_24 :: BYTE_OFS_37 [23:16] */
-#define BCHP_NAND_SPARE_AREA_READ_OFS_24_BYTE_OFS_37_MASK 0x00ff0000
-#define BCHP_NAND_SPARE_AREA_READ_OFS_24_BYTE_OFS_37_SHIFT 16
-#define BCHP_NAND_SPARE_AREA_READ_OFS_24_BYTE_OFS_37_DEFAULT 0x000000ff
-
-/* NAND :: SPARE_AREA_READ_OFS_24 :: BYTE_OFS_38 [15:08] */
-#define BCHP_NAND_SPARE_AREA_READ_OFS_24_BYTE_OFS_38_MASK 0x0000ff00
-#define BCHP_NAND_SPARE_AREA_READ_OFS_24_BYTE_OFS_38_SHIFT 8
-#define BCHP_NAND_SPARE_AREA_READ_OFS_24_BYTE_OFS_38_DEFAULT 0x000000ff
-
-/* NAND :: SPARE_AREA_READ_OFS_24 :: BYTE_OFS_39 [07:00] */
-#define BCHP_NAND_SPARE_AREA_READ_OFS_24_BYTE_OFS_39_MASK 0x000000ff
-#define BCHP_NAND_SPARE_AREA_READ_OFS_24_BYTE_OFS_39_SHIFT 0
-#define BCHP_NAND_SPARE_AREA_READ_OFS_24_BYTE_OFS_39_DEFAULT 0x000000ff
-
-/***************************************************************************
- *SPARE_AREA_READ_OFS_28 - Nand Flash Spare Area Read Bytes 40-43
- ***************************************************************************/
-/* NAND :: SPARE_AREA_READ_OFS_28 :: BYTE_OFS_40 [31:24] */
-#define BCHP_NAND_SPARE_AREA_READ_OFS_28_BYTE_OFS_40_MASK 0xff000000
-#define BCHP_NAND_SPARE_AREA_READ_OFS_28_BYTE_OFS_40_SHIFT 24
-#define BCHP_NAND_SPARE_AREA_READ_OFS_28_BYTE_OFS_40_DEFAULT 0x000000ff
-
-/* NAND :: SPARE_AREA_READ_OFS_28 :: BYTE_OFS_41 [23:16] */
-#define BCHP_NAND_SPARE_AREA_READ_OFS_28_BYTE_OFS_41_MASK 0x00ff0000
-#define BCHP_NAND_SPARE_AREA_READ_OFS_28_BYTE_OFS_41_SHIFT 16
-#define BCHP_NAND_SPARE_AREA_READ_OFS_28_BYTE_OFS_41_DEFAULT 0x000000ff
-
-/* NAND :: SPARE_AREA_READ_OFS_28 :: BYTE_OFS_42 [15:08] */
-#define BCHP_NAND_SPARE_AREA_READ_OFS_28_BYTE_OFS_42_MASK 0x0000ff00
-#define BCHP_NAND_SPARE_AREA_READ_OFS_28_BYTE_OFS_42_SHIFT 8
-#define BCHP_NAND_SPARE_AREA_READ_OFS_28_BYTE_OFS_42_DEFAULT 0x000000ff
-
-/* NAND :: SPARE_AREA_READ_OFS_28 :: BYTE_OFS_43 [07:00] */
-#define BCHP_NAND_SPARE_AREA_READ_OFS_28_BYTE_OFS_43_MASK 0x000000ff
-#define BCHP_NAND_SPARE_AREA_READ_OFS_28_BYTE_OFS_43_SHIFT 0
-#define BCHP_NAND_SPARE_AREA_READ_OFS_28_BYTE_OFS_43_DEFAULT 0x000000ff
-
-/***************************************************************************
- *SPARE_AREA_READ_OFS_2C - Nand Flash Spare Area Read Bytes 44-47
- ***************************************************************************/
-/* NAND :: SPARE_AREA_READ_OFS_2C :: BYTE_OFS_44 [31:24] */
-#define BCHP_NAND_SPARE_AREA_READ_OFS_2C_BYTE_OFS_44_MASK 0xff000000
-#define BCHP_NAND_SPARE_AREA_READ_OFS_2C_BYTE_OFS_44_SHIFT 24
-#define BCHP_NAND_SPARE_AREA_READ_OFS_2C_BYTE_OFS_44_DEFAULT 0x000000ff
-
-/* NAND :: SPARE_AREA_READ_OFS_2C :: BYTE_OFS_45 [23:16] */
-#define BCHP_NAND_SPARE_AREA_READ_OFS_2C_BYTE_OFS_45_MASK 0x00ff0000
-#define BCHP_NAND_SPARE_AREA_READ_OFS_2C_BYTE_OFS_45_SHIFT 16
-#define BCHP_NAND_SPARE_AREA_READ_OFS_2C_BYTE_OFS_45_DEFAULT 0x000000ff
-
-/* NAND :: SPARE_AREA_READ_OFS_2C :: BYTE_OFS_46 [15:08] */
-#define BCHP_NAND_SPARE_AREA_READ_OFS_2C_BYTE_OFS_46_MASK 0x0000ff00
-#define BCHP_NAND_SPARE_AREA_READ_OFS_2C_BYTE_OFS_46_SHIFT 8
-#define BCHP_NAND_SPARE_AREA_READ_OFS_2C_BYTE_OFS_46_DEFAULT 0x000000ff
-
-/* NAND :: SPARE_AREA_READ_OFS_2C :: BYTE_OFS_47 [07:00] */
-#define BCHP_NAND_SPARE_AREA_READ_OFS_2C_BYTE_OFS_47_MASK 0x000000ff
-#define BCHP_NAND_SPARE_AREA_READ_OFS_2C_BYTE_OFS_47_SHIFT 0
-#define BCHP_NAND_SPARE_AREA_READ_OFS_2C_BYTE_OFS_47_DEFAULT 0x000000ff
-
-/***************************************************************************
- *SPARE_AREA_READ_OFS_30 - Nand Flash Spare Area Read Bytes 48-51
- ***************************************************************************/
-/* NAND :: SPARE_AREA_READ_OFS_30 :: BYTE_OFS_48 [31:24] */
-#define BCHP_NAND_SPARE_AREA_READ_OFS_30_BYTE_OFS_48_MASK 0xff000000
-#define BCHP_NAND_SPARE_AREA_READ_OFS_30_BYTE_OFS_48_SHIFT 24
-#define BCHP_NAND_SPARE_AREA_READ_OFS_30_BYTE_OFS_48_DEFAULT 0x000000ff
-
-/* NAND :: SPARE_AREA_READ_OFS_30 :: BYTE_OFS_49 [23:16] */
-#define BCHP_NAND_SPARE_AREA_READ_OFS_30_BYTE_OFS_49_MASK 0x00ff0000
-#define BCHP_NAND_SPARE_AREA_READ_OFS_30_BYTE_OFS_49_SHIFT 16
-#define BCHP_NAND_SPARE_AREA_READ_OFS_30_BYTE_OFS_49_DEFAULT 0x000000ff
-
-/* NAND :: SPARE_AREA_READ_OFS_30 :: BYTE_OFS_50 [15:08] */
-#define BCHP_NAND_SPARE_AREA_READ_OFS_30_BYTE_OFS_50_MASK 0x0000ff00
-#define BCHP_NAND_SPARE_AREA_READ_OFS_30_BYTE_OFS_50_SHIFT 8
-#define BCHP_NAND_SPARE_AREA_READ_OFS_30_BYTE_OFS_50_DEFAULT 0x000000ff
-
-/* NAND :: SPARE_AREA_READ_OFS_30 :: BYTE_OFS_51 [07:00] */
-#define BCHP_NAND_SPARE_AREA_READ_OFS_30_BYTE_OFS_51_MASK 0x000000ff
-#define BCHP_NAND_SPARE_AREA_READ_OFS_30_BYTE_OFS_51_SHIFT 0
-#define BCHP_NAND_SPARE_AREA_READ_OFS_30_BYTE_OFS_51_DEFAULT 0x000000ff
-
-/***************************************************************************
- *SPARE_AREA_READ_OFS_34 - Nand Flash Spare Area Read Bytes 52-55
- ***************************************************************************/
-/* NAND :: SPARE_AREA_READ_OFS_34 :: BYTE_OFS_52 [31:24] */
-#define BCHP_NAND_SPARE_AREA_READ_OFS_34_BYTE_OFS_52_MASK 0xff000000
-#define BCHP_NAND_SPARE_AREA_READ_OFS_34_BYTE_OFS_52_SHIFT 24
-#define BCHP_NAND_SPARE_AREA_READ_OFS_34_BYTE_OFS_52_DEFAULT 0x000000ff
-
-/* NAND :: SPARE_AREA_READ_OFS_34 :: BYTE_OFS_53 [23:16] */
-#define BCHP_NAND_SPARE_AREA_READ_OFS_34_BYTE_OFS_53_MASK 0x00ff0000
-#define BCHP_NAND_SPARE_AREA_READ_OFS_34_BYTE_OFS_53_SHIFT 16
-#define BCHP_NAND_SPARE_AREA_READ_OFS_34_BYTE_OFS_53_DEFAULT 0x000000ff
-
-/* NAND :: SPARE_AREA_READ_OFS_34 :: BYTE_OFS_54 [15:08] */
-#define BCHP_NAND_SPARE_AREA_READ_OFS_34_BYTE_OFS_54_MASK 0x0000ff00
-#define BCHP_NAND_SPARE_AREA_READ_OFS_34_BYTE_OFS_54_SHIFT 8
-#define BCHP_NAND_SPARE_AREA_READ_OFS_34_BYTE_OFS_54_DEFAULT 0x000000ff
-
-/* NAND :: SPARE_AREA_READ_OFS_34 :: BYTE_OFS_55 [07:00] */
-#define BCHP_NAND_SPARE_AREA_READ_OFS_34_BYTE_OFS_55_MASK 0x000000ff
-#define BCHP_NAND_SPARE_AREA_READ_OFS_34_BYTE_OFS_55_SHIFT 0
-#define BCHP_NAND_SPARE_AREA_READ_OFS_34_BYTE_OFS_55_DEFAULT 0x000000ff
-
-/***************************************************************************
- *SPARE_AREA_READ_OFS_38 - Nand Flash Spare Area Read Bytes 56-59
- ***************************************************************************/
-/* NAND :: SPARE_AREA_READ_OFS_38 :: BYTE_OFS_56 [31:24] */
-#define BCHP_NAND_SPARE_AREA_READ_OFS_38_BYTE_OFS_56_MASK 0xff000000
-#define BCHP_NAND_SPARE_AREA_READ_OFS_38_BYTE_OFS_56_SHIFT 24
-#define BCHP_NAND_SPARE_AREA_READ_OFS_38_BYTE_OFS_56_DEFAULT 0x000000ff
-
-/* NAND :: SPARE_AREA_READ_OFS_38 :: BYTE_OFS_57 [23:16] */
-#define BCHP_NAND_SPARE_AREA_READ_OFS_38_BYTE_OFS_57_MASK 0x00ff0000
-#define BCHP_NAND_SPARE_AREA_READ_OFS_38_BYTE_OFS_57_SHIFT 16
-#define BCHP_NAND_SPARE_AREA_READ_OFS_38_BYTE_OFS_57_DEFAULT 0x000000ff
-
-/* NAND :: SPARE_AREA_READ_OFS_38 :: BYTE_OFS_58 [15:08] */
-#define BCHP_NAND_SPARE_AREA_READ_OFS_38_BYTE_OFS_58_MASK 0x0000ff00
-#define BCHP_NAND_SPARE_AREA_READ_OFS_38_BYTE_OFS_58_SHIFT 8
-#define BCHP_NAND_SPARE_AREA_READ_OFS_38_BYTE_OFS_58_DEFAULT 0x000000ff
-
-/* NAND :: SPARE_AREA_READ_OFS_38 :: BYTE_OFS_59 [07:00] */
-#define BCHP_NAND_SPARE_AREA_READ_OFS_38_BYTE_OFS_59_MASK 0x000000ff
-#define BCHP_NAND_SPARE_AREA_READ_OFS_38_BYTE_OFS_59_SHIFT 0
-#define BCHP_NAND_SPARE_AREA_READ_OFS_38_BYTE_OFS_59_DEFAULT 0x000000ff
-
-/***************************************************************************
- *SPARE_AREA_READ_OFS_3C - Nand Flash Spare Area Read Bytes 60-63
- ***************************************************************************/
-/* NAND :: SPARE_AREA_READ_OFS_3C :: BYTE_OFS_60 [31:24] */
-#define BCHP_NAND_SPARE_AREA_READ_OFS_3C_BYTE_OFS_60_MASK 0xff000000
-#define BCHP_NAND_SPARE_AREA_READ_OFS_3C_BYTE_OFS_60_SHIFT 24
-#define BCHP_NAND_SPARE_AREA_READ_OFS_3C_BYTE_OFS_60_DEFAULT 0x000000ff
-
-/* NAND :: SPARE_AREA_READ_OFS_3C :: BYTE_OFS_61 [23:16] */
-#define BCHP_NAND_SPARE_AREA_READ_OFS_3C_BYTE_OFS_61_MASK 0x00ff0000
-#define BCHP_NAND_SPARE_AREA_READ_OFS_3C_BYTE_OFS_61_SHIFT 16
-#define BCHP_NAND_SPARE_AREA_READ_OFS_3C_BYTE_OFS_61_DEFAULT 0x000000ff
-
-/* NAND :: SPARE_AREA_READ_OFS_3C :: BYTE_OFS_62 [15:08] */
-#define BCHP_NAND_SPARE_AREA_READ_OFS_3C_BYTE_OFS_62_MASK 0x0000ff00
-#define BCHP_NAND_SPARE_AREA_READ_OFS_3C_BYTE_OFS_62_SHIFT 8
-#define BCHP_NAND_SPARE_AREA_READ_OFS_3C_BYTE_OFS_62_DEFAULT 0x000000ff
-
-/* NAND :: SPARE_AREA_READ_OFS_3C :: BYTE_OFS_63 [07:00] */
-#define BCHP_NAND_SPARE_AREA_READ_OFS_3C_BYTE_OFS_63_MASK 0x000000ff
-#define BCHP_NAND_SPARE_AREA_READ_OFS_3C_BYTE_OFS_63_SHIFT 0
-#define BCHP_NAND_SPARE_AREA_READ_OFS_3C_BYTE_OFS_63_DEFAULT 0x000000ff
-
-/***************************************************************************
- *SPARE_AREA_WRITE_OFS_0 - Nand Flash Spare Area Write Bytes 0-3
- ***************************************************************************/
-/* NAND :: SPARE_AREA_WRITE_OFS_0 :: BYTE_OFS_0 [31:24] */
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_0_BYTE_OFS_0_MASK 0xff000000
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_0_BYTE_OFS_0_SHIFT 24
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_0_BYTE_OFS_0_DEFAULT 0x000000ff
-
-/* NAND :: SPARE_AREA_WRITE_OFS_0 :: BYTE_OFS_1 [23:16] */
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_0_BYTE_OFS_1_MASK 0x00ff0000
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_0_BYTE_OFS_1_SHIFT 16
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_0_BYTE_OFS_1_DEFAULT 0x000000ff
-
-/* NAND :: SPARE_AREA_WRITE_OFS_0 :: BYTE_OFS_2 [15:08] */
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_0_BYTE_OFS_2_MASK 0x0000ff00
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_0_BYTE_OFS_2_SHIFT 8
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_0_BYTE_OFS_2_DEFAULT 0x000000ff
-
-/* NAND :: SPARE_AREA_WRITE_OFS_0 :: BYTE_OFS_3 [07:00] */
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_0_BYTE_OFS_3_MASK 0x000000ff
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_0_BYTE_OFS_3_SHIFT 0
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_0_BYTE_OFS_3_DEFAULT 0x000000ff
-
-/***************************************************************************
- *SPARE_AREA_WRITE_OFS_4 - Nand Flash Spare Area Write Bytes 4-7
- ***************************************************************************/
-/* NAND :: SPARE_AREA_WRITE_OFS_4 :: BYTE_OFS_4 [31:24] */
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_4_BYTE_OFS_4_MASK 0xff000000
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_4_BYTE_OFS_4_SHIFT 24
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_4_BYTE_OFS_4_DEFAULT 0x000000ff
-
-/* NAND :: SPARE_AREA_WRITE_OFS_4 :: BYTE_OFS_5 [23:16] */
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_4_BYTE_OFS_5_MASK 0x00ff0000
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_4_BYTE_OFS_5_SHIFT 16
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_4_BYTE_OFS_5_DEFAULT 0x000000ff
-
-/* NAND :: SPARE_AREA_WRITE_OFS_4 :: BYTE_OFS_6 [15:08] */
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_4_BYTE_OFS_6_MASK 0x0000ff00
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_4_BYTE_OFS_6_SHIFT 8
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_4_BYTE_OFS_6_DEFAULT 0x000000ff
-
-/* NAND :: SPARE_AREA_WRITE_OFS_4 :: BYTE_OFS_7 [07:00] */
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_4_BYTE_OFS_7_MASK 0x000000ff
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_4_BYTE_OFS_7_SHIFT 0
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_4_BYTE_OFS_7_DEFAULT 0x000000ff
-
-/***************************************************************************
- *SPARE_AREA_WRITE_OFS_8 - Nand Flash Spare Area Write Bytes 8-11
- ***************************************************************************/
-/* NAND :: SPARE_AREA_WRITE_OFS_8 :: BYTE_OFS_8 [31:24] */
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_8_BYTE_OFS_8_MASK 0xff000000
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_8_BYTE_OFS_8_SHIFT 24
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_8_BYTE_OFS_8_DEFAULT 0x000000ff
-
-/* NAND :: SPARE_AREA_WRITE_OFS_8 :: BYTE_OFS_9 [23:16] */
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_8_BYTE_OFS_9_MASK 0x00ff0000
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_8_BYTE_OFS_9_SHIFT 16
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_8_BYTE_OFS_9_DEFAULT 0x000000ff
-
-/* NAND :: SPARE_AREA_WRITE_OFS_8 :: BYTE_OFS_10 [15:08] */
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_8_BYTE_OFS_10_MASK 0x0000ff00
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_8_BYTE_OFS_10_SHIFT 8
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_8_BYTE_OFS_10_DEFAULT 0x000000ff
-
-/* NAND :: SPARE_AREA_WRITE_OFS_8 :: BYTE_OFS_11 [07:00] */
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_8_BYTE_OFS_11_MASK 0x000000ff
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_8_BYTE_OFS_11_SHIFT 0
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_8_BYTE_OFS_11_DEFAULT 0x000000ff
-
-/***************************************************************************
- *SPARE_AREA_WRITE_OFS_C - Nand Flash Spare Area Write Bytes 12-15
- ***************************************************************************/
-/* NAND :: SPARE_AREA_WRITE_OFS_C :: BYTE_OFS_12 [31:24] */
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_C_BYTE_OFS_12_MASK 0xff000000
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_C_BYTE_OFS_12_SHIFT 24
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_C_BYTE_OFS_12_DEFAULT 0x000000ff
-
-/* NAND :: SPARE_AREA_WRITE_OFS_C :: BYTE_OFS_13 [23:16] */
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_C_BYTE_OFS_13_MASK 0x00ff0000
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_C_BYTE_OFS_13_SHIFT 16
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_C_BYTE_OFS_13_DEFAULT 0x000000ff
-
-/* NAND :: SPARE_AREA_WRITE_OFS_C :: BYTE_OFS_14 [15:08] */
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_C_BYTE_OFS_14_MASK 0x0000ff00
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_C_BYTE_OFS_14_SHIFT 8
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_C_BYTE_OFS_14_DEFAULT 0x000000ff
-
-/* NAND :: SPARE_AREA_WRITE_OFS_C :: BYTE_OFS_15 [07:00] */
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_C_BYTE_OFS_15_MASK 0x000000ff
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_C_BYTE_OFS_15_SHIFT 0
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_C_BYTE_OFS_15_DEFAULT 0x000000ff
-
-/***************************************************************************
- *SPARE_AREA_WRITE_OFS_10 - Nand Flash Spare Area Write Bytes 16-19
- ***************************************************************************/
-/* NAND :: SPARE_AREA_WRITE_OFS_10 :: BYTE_OFS_16 [31:24] */
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_10_BYTE_OFS_16_MASK 0xff000000
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_10_BYTE_OFS_16_SHIFT 24
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_10_BYTE_OFS_16_DEFAULT 0x000000ff
-
-/* NAND :: SPARE_AREA_WRITE_OFS_10 :: BYTE_OFS_17 [23:16] */
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_10_BYTE_OFS_17_MASK 0x00ff0000
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_10_BYTE_OFS_17_SHIFT 16
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_10_BYTE_OFS_17_DEFAULT 0x000000ff
-
-/* NAND :: SPARE_AREA_WRITE_OFS_10 :: BYTE_OFS_18 [15:08] */
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_10_BYTE_OFS_18_MASK 0x0000ff00
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_10_BYTE_OFS_18_SHIFT 8
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_10_BYTE_OFS_18_DEFAULT 0x000000ff
-
-/* NAND :: SPARE_AREA_WRITE_OFS_10 :: BYTE_OFS_19 [07:00] */
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_10_BYTE_OFS_19_MASK 0x000000ff
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_10_BYTE_OFS_19_SHIFT 0
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_10_BYTE_OFS_19_DEFAULT 0x000000ff
-
-/***************************************************************************
- *SPARE_AREA_WRITE_OFS_14 - Nand Flash Spare Area Write Bytes 20-23
- ***************************************************************************/
-/* NAND :: SPARE_AREA_WRITE_OFS_14 :: BYTE_OFS_20 [31:24] */
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_14_BYTE_OFS_20_MASK 0xff000000
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_14_BYTE_OFS_20_SHIFT 24
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_14_BYTE_OFS_20_DEFAULT 0x000000ff
-
-/* NAND :: SPARE_AREA_WRITE_OFS_14 :: BYTE_OFS_21 [23:16] */
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_14_BYTE_OFS_21_MASK 0x00ff0000
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_14_BYTE_OFS_21_SHIFT 16
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_14_BYTE_OFS_21_DEFAULT 0x000000ff
-
-/* NAND :: SPARE_AREA_WRITE_OFS_14 :: BYTE_OFS_22 [15:08] */
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_14_BYTE_OFS_22_MASK 0x0000ff00
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_14_BYTE_OFS_22_SHIFT 8
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_14_BYTE_OFS_22_DEFAULT 0x000000ff
-
-/* NAND :: SPARE_AREA_WRITE_OFS_14 :: BYTE_OFS_23 [07:00] */
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_14_BYTE_OFS_23_MASK 0x000000ff
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_14_BYTE_OFS_23_SHIFT 0
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_14_BYTE_OFS_23_DEFAULT 0x000000ff
-
-/***************************************************************************
- *SPARE_AREA_WRITE_OFS_18 - Nand Flash Spare Area Write Bytes 24-27
- ***************************************************************************/
-/* NAND :: SPARE_AREA_WRITE_OFS_18 :: BYTE_OFS_24 [31:24] */
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_18_BYTE_OFS_24_MASK 0xff000000
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_18_BYTE_OFS_24_SHIFT 24
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_18_BYTE_OFS_24_DEFAULT 0x000000ff
-
-/* NAND :: SPARE_AREA_WRITE_OFS_18 :: BYTE_OFS_25 [23:16] */
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_18_BYTE_OFS_25_MASK 0x00ff0000
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_18_BYTE_OFS_25_SHIFT 16
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_18_BYTE_OFS_25_DEFAULT 0x000000ff
-
-/* NAND :: SPARE_AREA_WRITE_OFS_18 :: BYTE_OFS_26 [15:08] */
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_18_BYTE_OFS_26_MASK 0x0000ff00
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_18_BYTE_OFS_26_SHIFT 8
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_18_BYTE_OFS_26_DEFAULT 0x000000ff
-
-/* NAND :: SPARE_AREA_WRITE_OFS_18 :: BYTE_OFS_27 [07:00] */
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_18_BYTE_OFS_27_MASK 0x000000ff
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_18_BYTE_OFS_27_SHIFT 0
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_18_BYTE_OFS_27_DEFAULT 0x000000ff
-
-/***************************************************************************
- *SPARE_AREA_WRITE_OFS_1C - Nand Flash Spare Area Write Bytes 28-31
- ***************************************************************************/
-/* NAND :: SPARE_AREA_WRITE_OFS_1C :: BYTE_OFS_28 [31:24] */
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_1C_BYTE_OFS_28_MASK 0xff000000
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_1C_BYTE_OFS_28_SHIFT 24
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_1C_BYTE_OFS_28_DEFAULT 0x000000ff
-
-/* NAND :: SPARE_AREA_WRITE_OFS_1C :: BYTE_OFS_29 [23:16] */
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_1C_BYTE_OFS_29_MASK 0x00ff0000
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_1C_BYTE_OFS_29_SHIFT 16
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_1C_BYTE_OFS_29_DEFAULT 0x000000ff
-
-/* NAND :: SPARE_AREA_WRITE_OFS_1C :: BYTE_OFS_30 [15:08] */
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_1C_BYTE_OFS_30_MASK 0x0000ff00
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_1C_BYTE_OFS_30_SHIFT 8
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_1C_BYTE_OFS_30_DEFAULT 0x000000ff
-
-/* NAND :: SPARE_AREA_WRITE_OFS_1C :: BYTE_OFS_31 [07:00] */
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_1C_BYTE_OFS_31_MASK 0x000000ff
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_1C_BYTE_OFS_31_SHIFT 0
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_1C_BYTE_OFS_31_DEFAULT 0x000000ff
-
-/***************************************************************************
- *SPARE_AREA_WRITE_OFS_20 - Nand Flash Spare Area Write Bytes 32-35
- ***************************************************************************/
-/* NAND :: SPARE_AREA_WRITE_OFS_20 :: BYTE_OFS_32 [31:24] */
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_20_BYTE_OFS_32_MASK 0xff000000
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_20_BYTE_OFS_32_SHIFT 24
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_20_BYTE_OFS_32_DEFAULT 0x000000ff
-
-/* NAND :: SPARE_AREA_WRITE_OFS_20 :: BYTE_OFS_33 [23:16] */
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_20_BYTE_OFS_33_MASK 0x00ff0000
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_20_BYTE_OFS_33_SHIFT 16
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_20_BYTE_OFS_33_DEFAULT 0x000000ff
-
-/* NAND :: SPARE_AREA_WRITE_OFS_20 :: BYTE_OFS_34 [15:08] */
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_20_BYTE_OFS_34_MASK 0x0000ff00
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_20_BYTE_OFS_34_SHIFT 8
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_20_BYTE_OFS_34_DEFAULT 0x000000ff
-
-/* NAND :: SPARE_AREA_WRITE_OFS_20 :: BYTE_OFS_35 [07:00] */
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_20_BYTE_OFS_35_MASK 0x000000ff
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_20_BYTE_OFS_35_SHIFT 0
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_20_BYTE_OFS_35_DEFAULT 0x000000ff
-
-/***************************************************************************
- *SPARE_AREA_WRITE_OFS_24 - Nand Flash Spare Area Write Bytes 36-39
- ***************************************************************************/
-/* NAND :: SPARE_AREA_WRITE_OFS_24 :: BYTE_OFS_36 [31:24] */
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_24_BYTE_OFS_36_MASK 0xff000000
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_24_BYTE_OFS_36_SHIFT 24
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_24_BYTE_OFS_36_DEFAULT 0x000000ff
-
-/* NAND :: SPARE_AREA_WRITE_OFS_24 :: BYTE_OFS_37 [23:16] */
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_24_BYTE_OFS_37_MASK 0x00ff0000
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_24_BYTE_OFS_37_SHIFT 16
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_24_BYTE_OFS_37_DEFAULT 0x000000ff
-
-/* NAND :: SPARE_AREA_WRITE_OFS_24 :: BYTE_OFS_38 [15:08] */
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_24_BYTE_OFS_38_MASK 0x0000ff00
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_24_BYTE_OFS_38_SHIFT 8
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_24_BYTE_OFS_38_DEFAULT 0x000000ff
-
-/* NAND :: SPARE_AREA_WRITE_OFS_24 :: BYTE_OFS_39 [07:00] */
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_24_BYTE_OFS_39_MASK 0x000000ff
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_24_BYTE_OFS_39_SHIFT 0
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_24_BYTE_OFS_39_DEFAULT 0x000000ff
-
-/***************************************************************************
- *SPARE_AREA_WRITE_OFS_28 - Nand Flash Spare Area Write Bytes 40-43
- ***************************************************************************/
-/* NAND :: SPARE_AREA_WRITE_OFS_28 :: BYTE_OFS_40 [31:24] */
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_28_BYTE_OFS_40_MASK 0xff000000
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_28_BYTE_OFS_40_SHIFT 24
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_28_BYTE_OFS_40_DEFAULT 0x000000ff
-
-/* NAND :: SPARE_AREA_WRITE_OFS_28 :: BYTE_OFS_41 [23:16] */
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_28_BYTE_OFS_41_MASK 0x00ff0000
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_28_BYTE_OFS_41_SHIFT 16
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_28_BYTE_OFS_41_DEFAULT 0x000000ff
-
-/* NAND :: SPARE_AREA_WRITE_OFS_28 :: BYTE_OFS_42 [15:08] */
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_28_BYTE_OFS_42_MASK 0x0000ff00
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_28_BYTE_OFS_42_SHIFT 8
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_28_BYTE_OFS_42_DEFAULT 0x000000ff
-
-/* NAND :: SPARE_AREA_WRITE_OFS_28 :: BYTE_OFS_43 [07:00] */
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_28_BYTE_OFS_43_MASK 0x000000ff
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_28_BYTE_OFS_43_SHIFT 0
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_28_BYTE_OFS_43_DEFAULT 0x000000ff
-
-/***************************************************************************
- *SPARE_AREA_WRITE_OFS_2C - Nand Flash Spare Area Write Bytes 44-47
- ***************************************************************************/
-/* NAND :: SPARE_AREA_WRITE_OFS_2C :: BYTE_OFS_44 [31:24] */
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_2C_BYTE_OFS_44_MASK 0xff000000
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_2C_BYTE_OFS_44_SHIFT 24
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_2C_BYTE_OFS_44_DEFAULT 0x000000ff
-
-/* NAND :: SPARE_AREA_WRITE_OFS_2C :: BYTE_OFS_45 [23:16] */
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_2C_BYTE_OFS_45_MASK 0x00ff0000
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_2C_BYTE_OFS_45_SHIFT 16
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_2C_BYTE_OFS_45_DEFAULT 0x000000ff
-
-/* NAND :: SPARE_AREA_WRITE_OFS_2C :: BYTE_OFS_46 [15:08] */
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_2C_BYTE_OFS_46_MASK 0x0000ff00
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_2C_BYTE_OFS_46_SHIFT 8
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_2C_BYTE_OFS_46_DEFAULT 0x000000ff
-
-/* NAND :: SPARE_AREA_WRITE_OFS_2C :: BYTE_OFS_47 [07:00] */
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_2C_BYTE_OFS_47_MASK 0x000000ff
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_2C_BYTE_OFS_47_SHIFT 0
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_2C_BYTE_OFS_47_DEFAULT 0x000000ff
-
-/***************************************************************************
- *SPARE_AREA_WRITE_OFS_30 - Nand Flash Spare Area Write Bytes 48-51
- ***************************************************************************/
-/* NAND :: SPARE_AREA_WRITE_OFS_30 :: BYTE_OFS_48 [31:24] */
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_30_BYTE_OFS_48_MASK 0xff000000
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_30_BYTE_OFS_48_SHIFT 24
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_30_BYTE_OFS_48_DEFAULT 0x000000ff
-
-/* NAND :: SPARE_AREA_WRITE_OFS_30 :: BYTE_OFS_49 [23:16] */
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_30_BYTE_OFS_49_MASK 0x00ff0000
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_30_BYTE_OFS_49_SHIFT 16
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_30_BYTE_OFS_49_DEFAULT 0x000000ff
-
-/* NAND :: SPARE_AREA_WRITE_OFS_30 :: BYTE_OFS_50 [15:08] */
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_30_BYTE_OFS_50_MASK 0x0000ff00
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_30_BYTE_OFS_50_SHIFT 8
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_30_BYTE_OFS_50_DEFAULT 0x000000ff
-
-/* NAND :: SPARE_AREA_WRITE_OFS_30 :: BYTE_OFS_51 [07:00] */
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_30_BYTE_OFS_51_MASK 0x000000ff
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_30_BYTE_OFS_51_SHIFT 0
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_30_BYTE_OFS_51_DEFAULT 0x000000ff
-
-/***************************************************************************
- *SPARE_AREA_WRITE_OFS_34 - Nand Flash Spare Area Write Bytes 52-55
- ***************************************************************************/
-/* NAND :: SPARE_AREA_WRITE_OFS_34 :: BYTE_OFS_52 [31:24] */
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_34_BYTE_OFS_52_MASK 0xff000000
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_34_BYTE_OFS_52_SHIFT 24
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_34_BYTE_OFS_52_DEFAULT 0x000000ff
-
-/* NAND :: SPARE_AREA_WRITE_OFS_34 :: BYTE_OFS_53 [23:16] */
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_34_BYTE_OFS_53_MASK 0x00ff0000
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_34_BYTE_OFS_53_SHIFT 16
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_34_BYTE_OFS_53_DEFAULT 0x000000ff
-
-/* NAND :: SPARE_AREA_WRITE_OFS_34 :: BYTE_OFS_54 [15:08] */
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_34_BYTE_OFS_54_MASK 0x0000ff00
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_34_BYTE_OFS_54_SHIFT 8
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_34_BYTE_OFS_54_DEFAULT 0x000000ff
-
-/* NAND :: SPARE_AREA_WRITE_OFS_34 :: BYTE_OFS_55 [07:00] */
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_34_BYTE_OFS_55_MASK 0x000000ff
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_34_BYTE_OFS_55_SHIFT 0
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_34_BYTE_OFS_55_DEFAULT 0x000000ff
-
-/***************************************************************************
- *SPARE_AREA_WRITE_OFS_38 - Nand Flash Spare Area Write Bytes 56-59
- ***************************************************************************/
-/* NAND :: SPARE_AREA_WRITE_OFS_38 :: BYTE_OFS_56 [31:24] */
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_38_BYTE_OFS_56_MASK 0xff000000
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_38_BYTE_OFS_56_SHIFT 24
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_38_BYTE_OFS_56_DEFAULT 0x000000ff
-
-/* NAND :: SPARE_AREA_WRITE_OFS_38 :: BYTE_OFS_57 [23:16] */
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_38_BYTE_OFS_57_MASK 0x00ff0000
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_38_BYTE_OFS_57_SHIFT 16
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_38_BYTE_OFS_57_DEFAULT 0x000000ff
-
-/* NAND :: SPARE_AREA_WRITE_OFS_38 :: BYTE_OFS_58 [15:08] */
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_38_BYTE_OFS_58_MASK 0x0000ff00
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_38_BYTE_OFS_58_SHIFT 8
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_38_BYTE_OFS_58_DEFAULT 0x000000ff
-
-/* NAND :: SPARE_AREA_WRITE_OFS_38 :: BYTE_OFS_59 [07:00] */
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_38_BYTE_OFS_59_MASK 0x000000ff
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_38_BYTE_OFS_59_SHIFT 0
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_38_BYTE_OFS_59_DEFAULT 0x000000ff
-
-/***************************************************************************
- *SPARE_AREA_WRITE_OFS_3C - Nand Flash Spare Area Write Bytes 60-63
- ***************************************************************************/
-/* NAND :: SPARE_AREA_WRITE_OFS_3C :: BYTE_OFS_60 [31:24] */
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_3C_BYTE_OFS_60_MASK 0xff000000
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_3C_BYTE_OFS_60_SHIFT 24
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_3C_BYTE_OFS_60_DEFAULT 0x000000ff
-
-/* NAND :: SPARE_AREA_WRITE_OFS_3C :: BYTE_OFS_61 [23:16] */
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_3C_BYTE_OFS_61_MASK 0x00ff0000
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_3C_BYTE_OFS_61_SHIFT 16
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_3C_BYTE_OFS_61_DEFAULT 0x000000ff
-
-/* NAND :: SPARE_AREA_WRITE_OFS_3C :: BYTE_OFS_62 [15:08] */
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_3C_BYTE_OFS_62_MASK 0x0000ff00
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_3C_BYTE_OFS_62_SHIFT 8
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_3C_BYTE_OFS_62_DEFAULT 0x000000ff
-
-/* NAND :: SPARE_AREA_WRITE_OFS_3C :: BYTE_OFS_63 [07:00] */
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_3C_BYTE_OFS_63_MASK 0x000000ff
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_3C_BYTE_OFS_63_SHIFT 0
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_3C_BYTE_OFS_63_DEFAULT 0x000000ff
-
-/***************************************************************************
- *DDR_TIMING - Nand Flash DDR TIMING
- ***************************************************************************/
-/* NAND :: DDR_TIMING :: reserved0 [31:24] */
-#define BCHP_NAND_DDR_TIMING_reserved0_MASK 0xff000000
-#define BCHP_NAND_DDR_TIMING_reserved0_SHIFT 24
-
-/* NAND :: DDR_TIMING :: tCAD [23:20] */
-#define BCHP_NAND_DDR_TIMING_tCAD_MASK 0x00f00000
-#define BCHP_NAND_DDR_TIMING_tCAD_SHIFT 20
-#define BCHP_NAND_DDR_TIMING_tCAD_DEFAULT 0x00000004
-
-/* NAND :: DDR_TIMING :: reserved1 [19:17] */
-#define BCHP_NAND_DDR_TIMING_reserved1_MASK 0x000e0000
-#define BCHP_NAND_DDR_TIMING_reserved1_SHIFT 17
-
-/* NAND :: DDR_TIMING :: tWHR [16:12] */
-#define BCHP_NAND_DDR_TIMING_tWHR_MASK 0x0001f000
-#define BCHP_NAND_DDR_TIMING_tWHR_SHIFT 12
-#define BCHP_NAND_DDR_TIMING_tWHR_DEFAULT 0x00000014
-
-/* NAND :: DDR_TIMING :: tCS [11:08] */
-#define BCHP_NAND_DDR_TIMING_tCS_MASK 0x00000f00
-#define BCHP_NAND_DDR_TIMING_tCS_SHIFT 8
-#define BCHP_NAND_DDR_TIMING_tCS_DEFAULT 0x00000002
-
-/* NAND :: DDR_TIMING :: tWB [07:04] */
-#define BCHP_NAND_DDR_TIMING_tWB_MASK 0x000000f0
-#define BCHP_NAND_DDR_TIMING_tWB_SHIFT 4
-#define BCHP_NAND_DDR_TIMING_tWB_DEFAULT 0x0000000f
-
-/* NAND :: DDR_TIMING :: tADL [03:00] */
-#define BCHP_NAND_DDR_TIMING_tADL_MASK 0x0000000f
-#define BCHP_NAND_DDR_TIMING_tADL_SHIFT 0
-#define BCHP_NAND_DDR_TIMING_tADL_DEFAULT 0x00000007
-
-/***************************************************************************
- *DDR_NCDL_CALIB_CTL - Nand Flash Calibration Control for Master DLL
- ***************************************************************************/
-/* NAND :: DDR_NCDL_CALIB_CTL :: reserved0 [31:04] */
-#define BCHP_NAND_DDR_NCDL_CALIB_CTL_reserved0_MASK 0xfffffff0
-#define BCHP_NAND_DDR_NCDL_CALIB_CTL_reserved0_SHIFT 4
-
-/* NAND :: DDR_NCDL_CALIB_CTL :: CALIB_PERIODIC [03:03] */
-#define BCHP_NAND_DDR_NCDL_CALIB_CTL_CALIB_PERIODIC_MASK 0x00000008
-#define BCHP_NAND_DDR_NCDL_CALIB_CTL_CALIB_PERIODIC_SHIFT 3
-#define BCHP_NAND_DDR_NCDL_CALIB_CTL_CALIB_PERIODIC_DEFAULT 0x00000000
-
-/* NAND :: DDR_NCDL_CALIB_CTL :: CALIB_ALWAYS [02:02] */
-#define BCHP_NAND_DDR_NCDL_CALIB_CTL_CALIB_ALWAYS_MASK 0x00000004
-#define BCHP_NAND_DDR_NCDL_CALIB_CTL_CALIB_ALWAYS_SHIFT 2
-#define BCHP_NAND_DDR_NCDL_CALIB_CTL_CALIB_ALWAYS_DEFAULT 0x00000000
-
-/* NAND :: DDR_NCDL_CALIB_CTL :: CALIB_ONCE [01:01] */
-#define BCHP_NAND_DDR_NCDL_CALIB_CTL_CALIB_ONCE_MASK 0x00000002
-#define BCHP_NAND_DDR_NCDL_CALIB_CTL_CALIB_ONCE_SHIFT 1
-#define BCHP_NAND_DDR_NCDL_CALIB_CTL_CALIB_ONCE_DEFAULT 0x00000000
-
-/* NAND :: DDR_NCDL_CALIB_CTL :: CALIB_EN [00:00] */
-#define BCHP_NAND_DDR_NCDL_CALIB_CTL_CALIB_EN_MASK 0x00000001
-#define BCHP_NAND_DDR_NCDL_CALIB_CTL_CALIB_EN_SHIFT 0
-#define BCHP_NAND_DDR_NCDL_CALIB_CTL_CALIB_EN_DEFAULT 0x00000000
-
-/***************************************************************************
- *DDR_NCDL_CALIB_PERIOD - Nand Flash Calibration Period
- ***************************************************************************/
-/* NAND :: DDR_NCDL_CALIB_PERIOD :: reserved0 [31:20] */
-#define BCHP_NAND_DDR_NCDL_CALIB_PERIOD_reserved0_MASK 0xfff00000
-#define BCHP_NAND_DDR_NCDL_CALIB_PERIOD_reserved0_SHIFT 20
-
-/* NAND :: DDR_NCDL_CALIB_PERIOD :: CALIB_PERIOD [19:00] */
-#define BCHP_NAND_DDR_NCDL_CALIB_PERIOD_CALIB_PERIOD_MASK 0x000fffff
-#define BCHP_NAND_DDR_NCDL_CALIB_PERIOD_CALIB_PERIOD_SHIFT 0
-#define BCHP_NAND_DDR_NCDL_CALIB_PERIOD_CALIB_PERIOD_DEFAULT 0x00000000
-
-/***************************************************************************
- *DDR_NCDL_CALIB_STAT - Nand Flash Calibration Status for Master DLL
- ***************************************************************************/
-/* NAND :: DDR_NCDL_CALIB_STAT :: reserved0 [31:16] */
-#define BCHP_NAND_DDR_NCDL_CALIB_STAT_reserved0_MASK 0xffff0000
-#define BCHP_NAND_DDR_NCDL_CALIB_STAT_reserved0_SHIFT 16
-
-/* NAND :: DDR_NCDL_CALIB_STAT :: NCDL_PHASE [15:08] */
-#define BCHP_NAND_DDR_NCDL_CALIB_STAT_NCDL_PHASE_MASK 0x0000ff00
-#define BCHP_NAND_DDR_NCDL_CALIB_STAT_NCDL_PHASE_SHIFT 8
-#define BCHP_NAND_DDR_NCDL_CALIB_STAT_NCDL_PHASE_DEFAULT 0x00000000
-
-/* NAND :: DDR_NCDL_CALIB_STAT :: reserved1 [07:01] */
-#define BCHP_NAND_DDR_NCDL_CALIB_STAT_reserved1_MASK 0x000000fe
-#define BCHP_NAND_DDR_NCDL_CALIB_STAT_reserved1_SHIFT 1
-
-/* NAND :: DDR_NCDL_CALIB_STAT :: CALIB_LOCK [00:00] */
-#define BCHP_NAND_DDR_NCDL_CALIB_STAT_CALIB_LOCK_MASK 0x00000001
-#define BCHP_NAND_DDR_NCDL_CALIB_STAT_CALIB_LOCK_SHIFT 0
-#define BCHP_NAND_DDR_NCDL_CALIB_STAT_CALIB_LOCK_DEFAULT 0x00000000
-
-/***************************************************************************
- *DDR_NCDL_MODE - Nand Flash NCDL mode for Slave DLLs
- ***************************************************************************/
-/* NAND :: DDR_NCDL_MODE :: reserved0 [31:05] */
-#define BCHP_NAND_DDR_NCDL_MODE_reserved0_MASK 0xffffffe0
-#define BCHP_NAND_DDR_NCDL_MODE_reserved0_SHIFT 5
-
-/* NAND :: DDR_NCDL_MODE :: RDNCDL [04:04] */
-#define BCHP_NAND_DDR_NCDL_MODE_RDNCDL_MASK 0x00000010
-#define BCHP_NAND_DDR_NCDL_MODE_RDNCDL_SHIFT 4
-#define BCHP_NAND_DDR_NCDL_MODE_RDNCDL_DEFAULT 0x00000000
-
-/* NAND :: DDR_NCDL_MODE :: reserved1 [03:01] */
-#define BCHP_NAND_DDR_NCDL_MODE_reserved1_MASK 0x0000000e
-#define BCHP_NAND_DDR_NCDL_MODE_reserved1_SHIFT 1
-
-/* NAND :: DDR_NCDL_MODE :: WRNCDL [00:00] */
-#define BCHP_NAND_DDR_NCDL_MODE_WRNCDL_MASK 0x00000001
-#define BCHP_NAND_DDR_NCDL_MODE_WRNCDL_SHIFT 0
-#define BCHP_NAND_DDR_NCDL_MODE_WRNCDL_DEFAULT 0x00000000
-
-/***************************************************************************
- *DDR_NCDL_OFFSET - Nand Flash NCDL offset for Slave DLLs
- ***************************************************************************/
-/* NAND :: DDR_NCDL_OFFSET :: reserved0 [31:25] */
-#define BCHP_NAND_DDR_NCDL_OFFSET_reserved0_MASK 0xfe000000
-#define BCHP_NAND_DDR_NCDL_OFFSET_reserved0_SHIFT 25
-
-/* NAND :: DDR_NCDL_OFFSET :: RDNCDL_OFF [24:16] */
-#define BCHP_NAND_DDR_NCDL_OFFSET_RDNCDL_OFF_MASK 0x01ff0000
-#define BCHP_NAND_DDR_NCDL_OFFSET_RDNCDL_OFF_SHIFT 16
-#define BCHP_NAND_DDR_NCDL_OFFSET_RDNCDL_OFF_DEFAULT 0x00000000
-
-/* NAND :: DDR_NCDL_OFFSET :: reserved1 [15:09] */
-#define BCHP_NAND_DDR_NCDL_OFFSET_reserved1_MASK 0x0000fe00
-#define BCHP_NAND_DDR_NCDL_OFFSET_reserved1_SHIFT 9
-
-/* NAND :: DDR_NCDL_OFFSET :: WRNCDL_OFF [08:00] */
-#define BCHP_NAND_DDR_NCDL_OFFSET_WRNCDL_OFF_MASK 0x000001ff
-#define BCHP_NAND_DDR_NCDL_OFFSET_WRNCDL_OFF_SHIFT 0
-#define BCHP_NAND_DDR_NCDL_OFFSET_WRNCDL_OFF_DEFAULT 0x00000000
-
-/***************************************************************************
- *DDR_PHY_CTL - Nand Flash DDR PHY CONTROL
- ***************************************************************************/
-/* NAND :: DDR_PHY_CTL :: reserved0 [31:02] */
-#define BCHP_NAND_DDR_PHY_CTL_reserved0_MASK 0xfffffffc
-#define BCHP_NAND_DDR_PHY_CTL_reserved0_SHIFT 2
-
-/* NAND :: DDR_PHY_CTL :: DDR_MODE [01:01] */
-#define BCHP_NAND_DDR_PHY_CTL_DDR_MODE_MASK 0x00000002
-#define BCHP_NAND_DDR_PHY_CTL_DDR_MODE_SHIFT 1
-#define BCHP_NAND_DDR_PHY_CTL_DDR_MODE_DEFAULT 0x00000000
-
-/* NAND :: DDR_PHY_CTL :: reserved1 [00:00] */
-#define BCHP_NAND_DDR_PHY_CTL_reserved1_MASK 0x00000001
-#define BCHP_NAND_DDR_PHY_CTL_reserved1_SHIFT 0
-
-/***************************************************************************
- *DDR_PHY_BIST_CTL - Nand Flash DDR PHY BIST CONTROL
- ***************************************************************************/
-/* NAND :: DDR_PHY_BIST_CTL :: reserved0 [31:05] */
-#define BCHP_NAND_DDR_PHY_BIST_CTL_reserved0_MASK 0xffffffe0
-#define BCHP_NAND_DDR_PHY_BIST_CTL_reserved0_SHIFT 5
-
-/* NAND :: DDR_PHY_BIST_CTL :: BIST_CLR [04:04] */
-#define BCHP_NAND_DDR_PHY_BIST_CTL_BIST_CLR_MASK 0x00000010
-#define BCHP_NAND_DDR_PHY_BIST_CTL_BIST_CLR_SHIFT 4
-#define BCHP_NAND_DDR_PHY_BIST_CTL_BIST_CLR_DEFAULT 0x00000000
-
-/* NAND :: DDR_PHY_BIST_CTL :: reserved1 [03:01] */
-#define BCHP_NAND_DDR_PHY_BIST_CTL_reserved1_MASK 0x0000000e
-#define BCHP_NAND_DDR_PHY_BIST_CTL_reserved1_SHIFT 1
-
-/* NAND :: DDR_PHY_BIST_CTL :: BIST_START [00:00] */
-#define BCHP_NAND_DDR_PHY_BIST_CTL_BIST_START_MASK 0x00000001
-#define BCHP_NAND_DDR_PHY_BIST_CTL_BIST_START_SHIFT 0
-#define BCHP_NAND_DDR_PHY_BIST_CTL_BIST_START_DEFAULT 0x00000000
-
-/***************************************************************************
- *DDR_PHY_BIST_STAT - Nand Flash DDR PHY BIST STATUS
- ***************************************************************************/
-/* NAND :: DDR_PHY_BIST_STAT :: reserved0 [31:07] */
-#define BCHP_NAND_DDR_PHY_BIST_STAT_reserved0_MASK 0xffffff80
-#define BCHP_NAND_DDR_PHY_BIST_STAT_reserved0_SHIFT 7
-
-/* NAND :: DDR_PHY_BIST_STAT :: W1_DATA_RDPH_ERR [06:06] */
-#define BCHP_NAND_DDR_PHY_BIST_STAT_W1_DATA_RDPH_ERR_MASK 0x00000040
-#define BCHP_NAND_DDR_PHY_BIST_STAT_W1_DATA_RDPH_ERR_SHIFT 6
-
-/* NAND :: DDR_PHY_BIST_STAT :: W0_DATA_RDPH_ERR [05:05] */
-#define BCHP_NAND_DDR_PHY_BIST_STAT_W0_DATA_RDPH_ERR_MASK 0x00000020
-#define BCHP_NAND_DDR_PHY_BIST_STAT_W0_DATA_RDPH_ERR_SHIFT 5
-
-/* NAND :: DDR_PHY_BIST_STAT :: W1_DATA_WRPH_ERR [04:04] */
-#define BCHP_NAND_DDR_PHY_BIST_STAT_W1_DATA_WRPH_ERR_MASK 0x00000010
-#define BCHP_NAND_DDR_PHY_BIST_STAT_W1_DATA_WRPH_ERR_SHIFT 4
-
-/* NAND :: DDR_PHY_BIST_STAT :: W0_DATA_WRPH_ERR [03:03] */
-#define BCHP_NAND_DDR_PHY_BIST_STAT_W0_DATA_WRPH_ERR_MASK 0x00000008
-#define BCHP_NAND_DDR_PHY_BIST_STAT_W0_DATA_WRPH_ERR_SHIFT 3
-
-/* NAND :: DDR_PHY_BIST_STAT :: W1_ADDR_ERR [02:02] */
-#define BCHP_NAND_DDR_PHY_BIST_STAT_W1_ADDR_ERR_MASK 0x00000004
-#define BCHP_NAND_DDR_PHY_BIST_STAT_W1_ADDR_ERR_SHIFT 2
-
-/* NAND :: DDR_PHY_BIST_STAT :: W0_ADDR_ERR [01:01] */
-#define BCHP_NAND_DDR_PHY_BIST_STAT_W0_ADDR_ERR_MASK 0x00000002
-#define BCHP_NAND_DDR_PHY_BIST_STAT_W0_ADDR_ERR_SHIFT 1
-
-/* NAND :: DDR_PHY_BIST_STAT :: BIST_DONE [00:00] */
-#define BCHP_NAND_DDR_PHY_BIST_STAT_BIST_DONE_MASK 0x00000001
-#define BCHP_NAND_DDR_PHY_BIST_STAT_BIST_DONE_SHIFT 0
-
-/***************************************************************************
- *DDR_DIAG_STAT0 - Nand Flash DDR DIAG STATUS0
- ***************************************************************************/
-/* NAND :: DDR_DIAG_STAT0 :: DIAG_STATUS [31:00] */
-#define BCHP_NAND_DDR_DIAG_STAT0_DIAG_STATUS_MASK 0xffffffff
-#define BCHP_NAND_DDR_DIAG_STAT0_DIAG_STATUS_SHIFT 0
-
-/***************************************************************************
- *DDR_DIAG_STAT1 - Nand Flash DDR DIAG STATUS1
- ***************************************************************************/
-/* NAND :: DDR_DIAG_STAT1 :: DIAG_STATUS [31:00] */
-#define BCHP_NAND_DDR_DIAG_STAT1_DIAG_STATUS_MASK 0xffffffff
-#define BCHP_NAND_DDR_DIAG_STAT1_DIAG_STATUS_SHIFT 0
-
-/***************************************************************************
- *FLASH_CACHE%i - Flash Cache Buffer Read Access
- ***************************************************************************/
-#define BCHP_NAND_FLASH_CACHEi_ARRAY_BASE 0x203d2c00
-#define BCHP_NAND_FLASH_CACHEi_ARRAY_START 0
-#define BCHP_NAND_FLASH_CACHEi_ARRAY_END 127
-#define BCHP_NAND_FLASH_CACHEi_ARRAY_ELEMENT_SIZE 32
-
-/***************************************************************************
- *FLASH_CACHE%i - Flash Cache Buffer Read Access
- ***************************************************************************/
-/* NAND :: FLASH_CACHEi :: WORD [31:00] */
-#define BCHP_NAND_FLASH_CACHEi_WORD_MASK 0xffffffff
-#define BCHP_NAND_FLASH_CACHEi_WORD_SHIFT 0
-
-
-#endif /* #ifndef BCHP_NAND_H__ */
-
-/* End of File */
diff --git a/include/linux/brcmstb/7145a0/bchp_pcie_0_dma.h b/include/linux/brcmstb/7145a0/bchp_pcie_0_dma.h
deleted file mode 100644
index 607766c..0000000
--- a/include/linux/brcmstb/7145a0/bchp_pcie_0_dma.h
+++ /dev/null
@@ -1,735 +0,0 @@
-/***************************************************************************
- * Copyright (c) 1999-2013, Broadcom Corporation
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
- *
- * Module Description:
- * DO NOT EDIT THIS FILE DIRECTLY
- *
- * This module was generated magically with RDB from a source description
- * file. You must edit the source file for changes to be made to this file.
- *
- *
- * Date: Generated on Sat Apr 6 03:07:46 2013
- * MD5 Checksum d41d8cd98f00b204e9800998ecf8427e
- *
- * Compiled with: RDB Utility combo_header.pl
- * RDB Parser 3.0
- * unknown unknown
- * Perl Interpreter 5.008008
- * Operating System linux
- *
- * Revision History:
- *
- * $brcm_Log: $
- *
- ***************************************************************************/
-
-#ifndef BCHP_PCIE_0_DMA_H__
-#define BCHP_PCIE_0_DMA_H__
-
-/***************************************************************************
- *PCIE_0_DMA - PCI-E DMA Registers
- ***************************************************************************/
-#define BCHP_PCIE_0_DMA_TX_FIRST_DESC_L_ADDR_LIST0 0x07804400 /* Tx Descriptor List0 First Descriptor lower Address */
-#define BCHP_PCIE_0_DMA_TX_FIRST_DESC_U_ADDR_LIST0 0x07804404 /* Tx Descriptor List0 First Descriptor Upper Address */
-#define BCHP_PCIE_0_DMA_TX_FIRST_DESC_L_ADDR_LIST1 0x07804408 /* Tx Descriptor List1 First Descriptor Lower Address */
-#define BCHP_PCIE_0_DMA_TX_FIRST_DESC_U_ADDR_LIST1 0x0780440c /* Tx Descriptor List1 First Descriptor Upper Address */
-#define BCHP_PCIE_0_DMA_TX_SW_DESC_LIST_CTRL_STS 0x07804410 /* Tx Software Descriptor List Control and Status */
-#define BCHP_PCIE_0_DMA_TX_WAKE_CTRL 0x07804414 /* Tx Wake Control */
-#define BCHP_PCIE_0_DMA_TX_ERROR_STATUS 0x07804418 /* Tx Engine Error Status */
-#define BCHP_PCIE_0_DMA_TX_LIST0_CUR_DESC_L_ADDR 0x0780441c /* Tx List0 Current Descriptor Lower Address */
-#define BCHP_PCIE_0_DMA_TX_LIST0_CUR_DESC_U_ADDR 0x07804420 /* Tx List0 Current Descriptor Upper Address */
-#define BCHP_PCIE_0_DMA_TX_LIST0_CUR_BYTE_CNT 0x07804424 /* Tx List0 Current Descriptor Byte Count */
-#define BCHP_PCIE_0_DMA_TX_LIST1_CUR_DESC_L_ADDR 0x07804428 /* Tx List1 Current Descriptor Lower Address */
-#define BCHP_PCIE_0_DMA_TX_LIST1_CUR_DESC_U_ADDR 0x0780442c /* Tx List1 Current Descriptor Upper Address */
-#define BCHP_PCIE_0_DMA_TX_LIST1_CUR_BYTE_CNT 0x07804430 /* Tx List1 Current Descriptor Byte Count */
-#define BCHP_PCIE_0_DMA_RX_FIRST_DESC_L_ADDR_LIST0 0x07804434 /* Rx Descriptor List0 First Descriptor Lower Address */
-#define BCHP_PCIE_0_DMA_RX_FIRST_DESC_U_ADDR_LIST0 0x07804438 /* Rx Descriptor List0 First Descriptor Upper Address */
-#define BCHP_PCIE_0_DMA_RX_FIRST_DESC_L_ADDR_LIST1 0x0780443c /* Rx Descriptor List1 First Descriptor Lower Address */
-#define BCHP_PCIE_0_DMA_RX_FIRST_DESC_U_ADDR_LIST1 0x07804440 /* Rx Descriptor List1 First Descriptor Upper Address */
-#define BCHP_PCIE_0_DMA_RX_SW_DESC_LIST_CTRL_STS 0x07804444 /* Rx Software Descriptor List Control and Status */
-#define BCHP_PCIE_0_DMA_RX_WAKE_CTRL 0x07804448 /* Rx DMA Wake Control */
-#define BCHP_PCIE_0_DMA_RX_ERROR_STATUS 0x0780444c /* Rx Engine Error Status */
-#define BCHP_PCIE_0_DMA_RX_LIST0_CUR_DESC_L_ADDR 0x07804450 /* Rx List0 Current Descriptor Lower Address */
-#define BCHP_PCIE_0_DMA_RX_LIST0_CUR_DESC_U_ADDR 0x07804454 /* Rx List0 Current Descriptor Upper Address */
-#define BCHP_PCIE_0_DMA_RX_LIST0_CUR_BYTE_CNT 0x07804458 /* Rx List0 Current Descriptor Byte Count */
-#define BCHP_PCIE_0_DMA_RX_LIST1_CUR_DESC_L_ADDR 0x0780445c /* Rx List1 Current Descriptor Lower address */
-#define BCHP_PCIE_0_DMA_RX_LIST1_CUR_DESC_U_ADDR 0x07804460 /* Rx List1 Current Descriptor Upper address */
-#define BCHP_PCIE_0_DMA_RX_LIST1_CUR_BYTE_CNT 0x07804464 /* Rx List1 Current Descriptor Byte Count */
-#define BCHP_PCIE_0_DMA_DMA_DEBUG_OPTIONS_REG 0x07804468 /* DMA Debug Options Register */
-#define BCHP_PCIE_0_DMA_READ_CHANNEL_ERROR_STATUS 0x0780446c /* Read Channel Error Status */
-
-/***************************************************************************
- *TX_FIRST_DESC_L_ADDR_LIST0 - Tx Descriptor List0 First Descriptor lower Address
- ***************************************************************************/
-/* PCIE_0_DMA :: TX_FIRST_DESC_L_ADDR_LIST0 :: DESC_ADDR [31:05] */
-#define BCHP_PCIE_0_DMA_TX_FIRST_DESC_L_ADDR_LIST0_DESC_ADDR_MASK 0xffffffe0
-#define BCHP_PCIE_0_DMA_TX_FIRST_DESC_L_ADDR_LIST0_DESC_ADDR_SHIFT 5
-#define BCHP_PCIE_0_DMA_TX_FIRST_DESC_L_ADDR_LIST0_DESC_ADDR_DEFAULT 0x00000000
-
-/* PCIE_0_DMA :: TX_FIRST_DESC_L_ADDR_LIST0 :: reserved0 [04:01] */
-#define BCHP_PCIE_0_DMA_TX_FIRST_DESC_L_ADDR_LIST0_reserved0_MASK 0x0000001e
-#define BCHP_PCIE_0_DMA_TX_FIRST_DESC_L_ADDR_LIST0_reserved0_SHIFT 1
-
-/* PCIE_0_DMA :: TX_FIRST_DESC_L_ADDR_LIST0 :: TX_DESC_LIST0_VALID [00:00] */
-#define BCHP_PCIE_0_DMA_TX_FIRST_DESC_L_ADDR_LIST0_TX_DESC_LIST0_VALID_MASK 0x00000001
-#define BCHP_PCIE_0_DMA_TX_FIRST_DESC_L_ADDR_LIST0_TX_DESC_LIST0_VALID_SHIFT 0
-#define BCHP_PCIE_0_DMA_TX_FIRST_DESC_L_ADDR_LIST0_TX_DESC_LIST0_VALID_DEFAULT 0x00000000
-
-/***************************************************************************
- *TX_FIRST_DESC_U_ADDR_LIST0 - Tx Descriptor List0 First Descriptor Upper Address
- ***************************************************************************/
-/* PCIE_0_DMA :: TX_FIRST_DESC_U_ADDR_LIST0 :: DESC_ADDR [31:00] */
-#define BCHP_PCIE_0_DMA_TX_FIRST_DESC_U_ADDR_LIST0_DESC_ADDR_MASK 0xffffffff
-#define BCHP_PCIE_0_DMA_TX_FIRST_DESC_U_ADDR_LIST0_DESC_ADDR_SHIFT 0
-#define BCHP_PCIE_0_DMA_TX_FIRST_DESC_U_ADDR_LIST0_DESC_ADDR_DEFAULT 0x00000000
-
-/***************************************************************************
- *TX_FIRST_DESC_L_ADDR_LIST1 - Tx Descriptor List1 First Descriptor Lower Address
- ***************************************************************************/
-/* PCIE_0_DMA :: TX_FIRST_DESC_L_ADDR_LIST1 :: DESC_ADDR [31:05] */
-#define BCHP_PCIE_0_DMA_TX_FIRST_DESC_L_ADDR_LIST1_DESC_ADDR_MASK 0xffffffe0
-#define BCHP_PCIE_0_DMA_TX_FIRST_DESC_L_ADDR_LIST1_DESC_ADDR_SHIFT 5
-#define BCHP_PCIE_0_DMA_TX_FIRST_DESC_L_ADDR_LIST1_DESC_ADDR_DEFAULT 0x00000000
-
-/* PCIE_0_DMA :: TX_FIRST_DESC_L_ADDR_LIST1 :: reserved0 [04:01] */
-#define BCHP_PCIE_0_DMA_TX_FIRST_DESC_L_ADDR_LIST1_reserved0_MASK 0x0000001e
-#define BCHP_PCIE_0_DMA_TX_FIRST_DESC_L_ADDR_LIST1_reserved0_SHIFT 1
-
-/* PCIE_0_DMA :: TX_FIRST_DESC_L_ADDR_LIST1 :: TX_DESC_LIST1_VALID [00:00] */
-#define BCHP_PCIE_0_DMA_TX_FIRST_DESC_L_ADDR_LIST1_TX_DESC_LIST1_VALID_MASK 0x00000001
-#define BCHP_PCIE_0_DMA_TX_FIRST_DESC_L_ADDR_LIST1_TX_DESC_LIST1_VALID_SHIFT 0
-#define BCHP_PCIE_0_DMA_TX_FIRST_DESC_L_ADDR_LIST1_TX_DESC_LIST1_VALID_DEFAULT 0x00000000
-
-/***************************************************************************
- *TX_FIRST_DESC_U_ADDR_LIST1 - Tx Descriptor List1 First Descriptor Upper Address
- ***************************************************************************/
-/* PCIE_0_DMA :: TX_FIRST_DESC_U_ADDR_LIST1 :: DESC_ADDR [31:00] */
-#define BCHP_PCIE_0_DMA_TX_FIRST_DESC_U_ADDR_LIST1_DESC_ADDR_MASK 0xffffffff
-#define BCHP_PCIE_0_DMA_TX_FIRST_DESC_U_ADDR_LIST1_DESC_ADDR_SHIFT 0
-#define BCHP_PCIE_0_DMA_TX_FIRST_DESC_U_ADDR_LIST1_DESC_ADDR_DEFAULT 0x00000000
-
-/***************************************************************************
- *TX_SW_DESC_LIST_CTRL_STS - Tx Software Descriptor List Control and Status
- ***************************************************************************/
-/* PCIE_0_DMA :: TX_SW_DESC_LIST_CTRL_STS :: reserved0 [31:20] */
-#define BCHP_PCIE_0_DMA_TX_SW_DESC_LIST_CTRL_STS_reserved0_MASK 0xfff00000
-#define BCHP_PCIE_0_DMA_TX_SW_DESC_LIST_CTRL_STS_reserved0_SHIFT 20
-
-/* PCIE_0_DMA :: TX_SW_DESC_LIST_CTRL_STS :: BURST_SIZE_OVERRIDE [19:19] */
-#define BCHP_PCIE_0_DMA_TX_SW_DESC_LIST_CTRL_STS_BURST_SIZE_OVERRIDE_MASK 0x00080000
-#define BCHP_PCIE_0_DMA_TX_SW_DESC_LIST_CTRL_STS_BURST_SIZE_OVERRIDE_SHIFT 19
-#define BCHP_PCIE_0_DMA_TX_SW_DESC_LIST_CTRL_STS_BURST_SIZE_OVERRIDE_DEFAULT 0x00000000
-
-/* PCIE_0_DMA :: TX_SW_DESC_LIST_CTRL_STS :: BURST_SIZE_OVERRIDE_VALUE [18:16] */
-#define BCHP_PCIE_0_DMA_TX_SW_DESC_LIST_CTRL_STS_BURST_SIZE_OVERRIDE_VALUE_MASK 0x00070000
-#define BCHP_PCIE_0_DMA_TX_SW_DESC_LIST_CTRL_STS_BURST_SIZE_OVERRIDE_VALUE_SHIFT 16
-#define BCHP_PCIE_0_DMA_TX_SW_DESC_LIST_CTRL_STS_BURST_SIZE_OVERRIDE_VALUE_DEFAULT 0x00000000
-
-/* PCIE_0_DMA :: TX_SW_DESC_LIST_CTRL_STS :: reserved1 [15:14] */
-#define BCHP_PCIE_0_DMA_TX_SW_DESC_LIST_CTRL_STS_reserved1_MASK 0x0000c000
-#define BCHP_PCIE_0_DMA_TX_SW_DESC_LIST_CTRL_STS_reserved1_SHIFT 14
-
-/* PCIE_0_DMA :: TX_SW_DESC_LIST_CTRL_STS :: DESC_ENDIAN_MODE [13:12] */
-#define BCHP_PCIE_0_DMA_TX_SW_DESC_LIST_CTRL_STS_DESC_ENDIAN_MODE_MASK 0x00003000
-#define BCHP_PCIE_0_DMA_TX_SW_DESC_LIST_CTRL_STS_DESC_ENDIAN_MODE_SHIFT 12
-#define BCHP_PCIE_0_DMA_TX_SW_DESC_LIST_CTRL_STS_DESC_ENDIAN_MODE_DEFAULT 0x00000000
-
-/* PCIE_0_DMA :: TX_SW_DESC_LIST_CTRL_STS :: reserved2 [11:10] */
-#define BCHP_PCIE_0_DMA_TX_SW_DESC_LIST_CTRL_STS_reserved2_MASK 0x00000c00
-#define BCHP_PCIE_0_DMA_TX_SW_DESC_LIST_CTRL_STS_reserved2_SHIFT 10
-
-/* PCIE_0_DMA :: TX_SW_DESC_LIST_CTRL_STS :: LOCAL_DESC [09:09] */
-#define BCHP_PCIE_0_DMA_TX_SW_DESC_LIST_CTRL_STS_LOCAL_DESC_MASK 0x00000200
-#define BCHP_PCIE_0_DMA_TX_SW_DESC_LIST_CTRL_STS_LOCAL_DESC_SHIFT 9
-#define BCHP_PCIE_0_DMA_TX_SW_DESC_LIST_CTRL_STS_LOCAL_DESC_DEFAULT 0x00000000
-
-/* PCIE_0_DMA :: TX_SW_DESC_LIST_CTRL_STS :: DMA_MODE [08:08] */
-#define BCHP_PCIE_0_DMA_TX_SW_DESC_LIST_CTRL_STS_DMA_MODE_MASK 0x00000100
-#define BCHP_PCIE_0_DMA_TX_SW_DESC_LIST_CTRL_STS_DMA_MODE_SHIFT 8
-#define BCHP_PCIE_0_DMA_TX_SW_DESC_LIST_CTRL_STS_DMA_MODE_DEFAULT 0x00000000
-
-/* PCIE_0_DMA :: TX_SW_DESC_LIST_CTRL_STS :: reserved3 [07:06] */
-#define BCHP_PCIE_0_DMA_TX_SW_DESC_LIST_CTRL_STS_reserved3_MASK 0x000000c0
-#define BCHP_PCIE_0_DMA_TX_SW_DESC_LIST_CTRL_STS_reserved3_SHIFT 6
-
-/* PCIE_0_DMA :: TX_SW_DESC_LIST_CTRL_STS :: DMA_STATUS [05:04] */
-#define BCHP_PCIE_0_DMA_TX_SW_DESC_LIST_CTRL_STS_DMA_STATUS_MASK 0x00000030
-#define BCHP_PCIE_0_DMA_TX_SW_DESC_LIST_CTRL_STS_DMA_STATUS_SHIFT 4
-#define BCHP_PCIE_0_DMA_TX_SW_DESC_LIST_CTRL_STS_DMA_STATUS_DEFAULT 0x00000000
-
-/* PCIE_0_DMA :: TX_SW_DESC_LIST_CTRL_STS :: DMA_DATA_SERV_PTR [03:03] */
-#define BCHP_PCIE_0_DMA_TX_SW_DESC_LIST_CTRL_STS_DMA_DATA_SERV_PTR_MASK 0x00000008
-#define BCHP_PCIE_0_DMA_TX_SW_DESC_LIST_CTRL_STS_DMA_DATA_SERV_PTR_SHIFT 3
-#define BCHP_PCIE_0_DMA_TX_SW_DESC_LIST_CTRL_STS_DMA_DATA_SERV_PTR_DEFAULT 0x00000000
-
-/* PCIE_0_DMA :: TX_SW_DESC_LIST_CTRL_STS :: DESC_SERV_PTR [02:02] */
-#define BCHP_PCIE_0_DMA_TX_SW_DESC_LIST_CTRL_STS_DESC_SERV_PTR_MASK 0x00000004
-#define BCHP_PCIE_0_DMA_TX_SW_DESC_LIST_CTRL_STS_DESC_SERV_PTR_SHIFT 2
-#define BCHP_PCIE_0_DMA_TX_SW_DESC_LIST_CTRL_STS_DESC_SERV_PTR_DEFAULT 0x00000000
-
-/* PCIE_0_DMA :: TX_SW_DESC_LIST_CTRL_STS :: reserved4 [01:01] */
-#define BCHP_PCIE_0_DMA_TX_SW_DESC_LIST_CTRL_STS_reserved4_MASK 0x00000002
-#define BCHP_PCIE_0_DMA_TX_SW_DESC_LIST_CTRL_STS_reserved4_SHIFT 1
-
-/* PCIE_0_DMA :: TX_SW_DESC_LIST_CTRL_STS :: TX_DMA_RUN_STOP [00:00] */
-#define BCHP_PCIE_0_DMA_TX_SW_DESC_LIST_CTRL_STS_TX_DMA_RUN_STOP_MASK 0x00000001
-#define BCHP_PCIE_0_DMA_TX_SW_DESC_LIST_CTRL_STS_TX_DMA_RUN_STOP_SHIFT 0
-#define BCHP_PCIE_0_DMA_TX_SW_DESC_LIST_CTRL_STS_TX_DMA_RUN_STOP_DEFAULT 0x00000000
-
-/***************************************************************************
- *TX_WAKE_CTRL - Tx Wake Control
- ***************************************************************************/
-/* PCIE_0_DMA :: TX_WAKE_CTRL :: reserved0 [31:02] */
-#define BCHP_PCIE_0_DMA_TX_WAKE_CTRL_reserved0_MASK 0xfffffffc
-#define BCHP_PCIE_0_DMA_TX_WAKE_CTRL_reserved0_SHIFT 2
-
-/* PCIE_0_DMA :: TX_WAKE_CTRL :: WAKE_MODE [01:01] */
-#define BCHP_PCIE_0_DMA_TX_WAKE_CTRL_WAKE_MODE_MASK 0x00000002
-#define BCHP_PCIE_0_DMA_TX_WAKE_CTRL_WAKE_MODE_SHIFT 1
-#define BCHP_PCIE_0_DMA_TX_WAKE_CTRL_WAKE_MODE_DEFAULT 0x00000000
-
-/* PCIE_0_DMA :: TX_WAKE_CTRL :: WAKE [00:00] */
-#define BCHP_PCIE_0_DMA_TX_WAKE_CTRL_WAKE_MASK 0x00000001
-#define BCHP_PCIE_0_DMA_TX_WAKE_CTRL_WAKE_SHIFT 0
-#define BCHP_PCIE_0_DMA_TX_WAKE_CTRL_WAKE_DEFAULT 0x00000000
-
-/***************************************************************************
- *TX_ERROR_STATUS - Tx Engine Error Status
- ***************************************************************************/
-/* PCIE_0_DMA :: TX_ERROR_STATUS :: reserved0 [31:10] */
-#define BCHP_PCIE_0_DMA_TX_ERROR_STATUS_reserved0_MASK 0xfffffc00
-#define BCHP_PCIE_0_DMA_TX_ERROR_STATUS_reserved0_SHIFT 10
-
-/* PCIE_0_DMA :: TX_ERROR_STATUS :: TX_L1_DESC_TX_ABORT_ERRORS [09:09] */
-#define BCHP_PCIE_0_DMA_TX_ERROR_STATUS_TX_L1_DESC_TX_ABORT_ERRORS_MASK 0x00000200
-#define BCHP_PCIE_0_DMA_TX_ERROR_STATUS_TX_L1_DESC_TX_ABORT_ERRORS_SHIFT 9
-#define BCHP_PCIE_0_DMA_TX_ERROR_STATUS_TX_L1_DESC_TX_ABORT_ERRORS_DEFAULT 0x00000000
-
-/* PCIE_0_DMA :: TX_ERROR_STATUS :: reserved1 [08:08] */
-#define BCHP_PCIE_0_DMA_TX_ERROR_STATUS_reserved1_MASK 0x00000100
-#define BCHP_PCIE_0_DMA_TX_ERROR_STATUS_reserved1_SHIFT 8
-
-/* PCIE_0_DMA :: TX_ERROR_STATUS :: TX_L0_DESC_TX_ABORT_ERRORS [07:07] */
-#define BCHP_PCIE_0_DMA_TX_ERROR_STATUS_TX_L0_DESC_TX_ABORT_ERRORS_MASK 0x00000080
-#define BCHP_PCIE_0_DMA_TX_ERROR_STATUS_TX_L0_DESC_TX_ABORT_ERRORS_SHIFT 7
-#define BCHP_PCIE_0_DMA_TX_ERROR_STATUS_TX_L0_DESC_TX_ABORT_ERRORS_DEFAULT 0x00000000
-
-/* PCIE_0_DMA :: TX_ERROR_STATUS :: reserved2 [06:06] */
-#define BCHP_PCIE_0_DMA_TX_ERROR_STATUS_reserved2_MASK 0x00000040
-#define BCHP_PCIE_0_DMA_TX_ERROR_STATUS_reserved2_SHIFT 6
-
-/* PCIE_0_DMA :: TX_ERROR_STATUS :: TX_L1_DATA_TX_ABORT_ERRORS [05:05] */
-#define BCHP_PCIE_0_DMA_TX_ERROR_STATUS_TX_L1_DATA_TX_ABORT_ERRORS_MASK 0x00000020
-#define BCHP_PCIE_0_DMA_TX_ERROR_STATUS_TX_L1_DATA_TX_ABORT_ERRORS_SHIFT 5
-#define BCHP_PCIE_0_DMA_TX_ERROR_STATUS_TX_L1_DATA_TX_ABORT_ERRORS_DEFAULT 0x00000000
-
-/* PCIE_0_DMA :: TX_ERROR_STATUS :: TX_L1_REPIN_ERRORS [04:04] */
-#define BCHP_PCIE_0_DMA_TX_ERROR_STATUS_TX_L1_REPIN_ERRORS_MASK 0x00000010
-#define BCHP_PCIE_0_DMA_TX_ERROR_STATUS_TX_L1_REPIN_ERRORS_SHIFT 4
-#define BCHP_PCIE_0_DMA_TX_ERROR_STATUS_TX_L1_REPIN_ERRORS_DEFAULT 0x00000000
-
-/* PCIE_0_DMA :: TX_ERROR_STATUS :: reserved3 [03:03] */
-#define BCHP_PCIE_0_DMA_TX_ERROR_STATUS_reserved3_MASK 0x00000008
-#define BCHP_PCIE_0_DMA_TX_ERROR_STATUS_reserved3_SHIFT 3
-
-/* PCIE_0_DMA :: TX_ERROR_STATUS :: TX_L0_DATA_TX_ABORT_ERRORS [02:02] */
-#define BCHP_PCIE_0_DMA_TX_ERROR_STATUS_TX_L0_DATA_TX_ABORT_ERRORS_MASK 0x00000004
-#define BCHP_PCIE_0_DMA_TX_ERROR_STATUS_TX_L0_DATA_TX_ABORT_ERRORS_SHIFT 2
-#define BCHP_PCIE_0_DMA_TX_ERROR_STATUS_TX_L0_DATA_TX_ABORT_ERRORS_DEFAULT 0x00000000
-
-/* PCIE_0_DMA :: TX_ERROR_STATUS :: TX_L0_REPIN_ERRORS [01:01] */
-#define BCHP_PCIE_0_DMA_TX_ERROR_STATUS_TX_L0_REPIN_ERRORS_MASK 0x00000002
-#define BCHP_PCIE_0_DMA_TX_ERROR_STATUS_TX_L0_REPIN_ERRORS_SHIFT 1
-#define BCHP_PCIE_0_DMA_TX_ERROR_STATUS_TX_L0_REPIN_ERRORS_DEFAULT 0x00000000
-
-/* PCIE_0_DMA :: TX_ERROR_STATUS :: reserved4 [00:00] */
-#define BCHP_PCIE_0_DMA_TX_ERROR_STATUS_reserved4_MASK 0x00000001
-#define BCHP_PCIE_0_DMA_TX_ERROR_STATUS_reserved4_SHIFT 0
-
-/***************************************************************************
- *TX_LIST0_CUR_DESC_L_ADDR - Tx List0 Current Descriptor Lower Address
- ***************************************************************************/
-/* PCIE_0_DMA :: TX_LIST0_CUR_DESC_L_ADDR :: TX_L0_CUR_DESC_L_ADDR [31:05] */
-#define BCHP_PCIE_0_DMA_TX_LIST0_CUR_DESC_L_ADDR_TX_L0_CUR_DESC_L_ADDR_MASK 0xffffffe0
-#define BCHP_PCIE_0_DMA_TX_LIST0_CUR_DESC_L_ADDR_TX_L0_CUR_DESC_L_ADDR_SHIFT 5
-#define BCHP_PCIE_0_DMA_TX_LIST0_CUR_DESC_L_ADDR_TX_L0_CUR_DESC_L_ADDR_DEFAULT 0x00000000
-
-/* PCIE_0_DMA :: TX_LIST0_CUR_DESC_L_ADDR :: reserved0 [04:04] */
-#define BCHP_PCIE_0_DMA_TX_LIST0_CUR_DESC_L_ADDR_reserved0_MASK 0x00000010
-#define BCHP_PCIE_0_DMA_TX_LIST0_CUR_DESC_L_ADDR_reserved0_SHIFT 4
-
-/* PCIE_0_DMA :: TX_LIST0_CUR_DESC_L_ADDR :: TX_L0_CUR_LIST [03:03] */
-#define BCHP_PCIE_0_DMA_TX_LIST0_CUR_DESC_L_ADDR_TX_L0_CUR_LIST_MASK 0x00000008
-#define BCHP_PCIE_0_DMA_TX_LIST0_CUR_DESC_L_ADDR_TX_L0_CUR_LIST_SHIFT 3
-#define BCHP_PCIE_0_DMA_TX_LIST0_CUR_DESC_L_ADDR_TX_L0_CUR_LIST_DEFAULT 0x00000000
-
-/* PCIE_0_DMA :: TX_LIST0_CUR_DESC_L_ADDR :: TX_L0_CUR_IN_PROGRESS [02:02] */
-#define BCHP_PCIE_0_DMA_TX_LIST0_CUR_DESC_L_ADDR_TX_L0_CUR_IN_PROGRESS_MASK 0x00000004
-#define BCHP_PCIE_0_DMA_TX_LIST0_CUR_DESC_L_ADDR_TX_L0_CUR_IN_PROGRESS_SHIFT 2
-#define BCHP_PCIE_0_DMA_TX_LIST0_CUR_DESC_L_ADDR_TX_L0_CUR_IN_PROGRESS_DEFAULT 0x00000000
-
-/* PCIE_0_DMA :: TX_LIST0_CUR_DESC_L_ADDR :: TX_L0_CUR_STATUS [01:00] */
-#define BCHP_PCIE_0_DMA_TX_LIST0_CUR_DESC_L_ADDR_TX_L0_CUR_STATUS_MASK 0x00000003
-#define BCHP_PCIE_0_DMA_TX_LIST0_CUR_DESC_L_ADDR_TX_L0_CUR_STATUS_SHIFT 0
-#define BCHP_PCIE_0_DMA_TX_LIST0_CUR_DESC_L_ADDR_TX_L0_CUR_STATUS_DEFAULT 0x00000000
-
-/***************************************************************************
- *TX_LIST0_CUR_DESC_U_ADDR - Tx List0 Current Descriptor Upper Address
- ***************************************************************************/
-/* PCIE_0_DMA :: TX_LIST0_CUR_DESC_U_ADDR :: TX_L0_CUR_DESC_U_ADDR [31:00] */
-#define BCHP_PCIE_0_DMA_TX_LIST0_CUR_DESC_U_ADDR_TX_L0_CUR_DESC_U_ADDR_MASK 0xffffffff
-#define BCHP_PCIE_0_DMA_TX_LIST0_CUR_DESC_U_ADDR_TX_L0_CUR_DESC_U_ADDR_SHIFT 0
-#define BCHP_PCIE_0_DMA_TX_LIST0_CUR_DESC_U_ADDR_TX_L0_CUR_DESC_U_ADDR_DEFAULT 0x00000000
-
-/***************************************************************************
- *TX_LIST0_CUR_BYTE_CNT - Tx List0 Current Descriptor Byte Count
- ***************************************************************************/
-/* PCIE_0_DMA :: TX_LIST0_CUR_BYTE_CNT :: TX_L0_CUR_BYTE_CNT [31:00] */
-#define BCHP_PCIE_0_DMA_TX_LIST0_CUR_BYTE_CNT_TX_L0_CUR_BYTE_CNT_MASK 0xffffffff
-#define BCHP_PCIE_0_DMA_TX_LIST0_CUR_BYTE_CNT_TX_L0_CUR_BYTE_CNT_SHIFT 0
-#define BCHP_PCIE_0_DMA_TX_LIST0_CUR_BYTE_CNT_TX_L0_CUR_BYTE_CNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *TX_LIST1_CUR_DESC_L_ADDR - Tx List1 Current Descriptor Lower Address
- ***************************************************************************/
-/* PCIE_0_DMA :: TX_LIST1_CUR_DESC_L_ADDR :: TX_L1_CUR_DESC_L_ADDR [31:05] */
-#define BCHP_PCIE_0_DMA_TX_LIST1_CUR_DESC_L_ADDR_TX_L1_CUR_DESC_L_ADDR_MASK 0xffffffe0
-#define BCHP_PCIE_0_DMA_TX_LIST1_CUR_DESC_L_ADDR_TX_L1_CUR_DESC_L_ADDR_SHIFT 5
-#define BCHP_PCIE_0_DMA_TX_LIST1_CUR_DESC_L_ADDR_TX_L1_CUR_DESC_L_ADDR_DEFAULT 0x00000000
-
-/* PCIE_0_DMA :: TX_LIST1_CUR_DESC_L_ADDR :: reserved0 [04:04] */
-#define BCHP_PCIE_0_DMA_TX_LIST1_CUR_DESC_L_ADDR_reserved0_MASK 0x00000010
-#define BCHP_PCIE_0_DMA_TX_LIST1_CUR_DESC_L_ADDR_reserved0_SHIFT 4
-
-/* PCIE_0_DMA :: TX_LIST1_CUR_DESC_L_ADDR :: TX_L1_CUR_LIST [03:03] */
-#define BCHP_PCIE_0_DMA_TX_LIST1_CUR_DESC_L_ADDR_TX_L1_CUR_LIST_MASK 0x00000008
-#define BCHP_PCIE_0_DMA_TX_LIST1_CUR_DESC_L_ADDR_TX_L1_CUR_LIST_SHIFT 3
-#define BCHP_PCIE_0_DMA_TX_LIST1_CUR_DESC_L_ADDR_TX_L1_CUR_LIST_DEFAULT 0x00000000
-
-/* PCIE_0_DMA :: TX_LIST1_CUR_DESC_L_ADDR :: TX_L1_CUR_IN_PROGRESS [02:02] */
-#define BCHP_PCIE_0_DMA_TX_LIST1_CUR_DESC_L_ADDR_TX_L1_CUR_IN_PROGRESS_MASK 0x00000004
-#define BCHP_PCIE_0_DMA_TX_LIST1_CUR_DESC_L_ADDR_TX_L1_CUR_IN_PROGRESS_SHIFT 2
-#define BCHP_PCIE_0_DMA_TX_LIST1_CUR_DESC_L_ADDR_TX_L1_CUR_IN_PROGRESS_DEFAULT 0x00000000
-
-/* PCIE_0_DMA :: TX_LIST1_CUR_DESC_L_ADDR :: TX_L1_CUR_STATUS [01:00] */
-#define BCHP_PCIE_0_DMA_TX_LIST1_CUR_DESC_L_ADDR_TX_L1_CUR_STATUS_MASK 0x00000003
-#define BCHP_PCIE_0_DMA_TX_LIST1_CUR_DESC_L_ADDR_TX_L1_CUR_STATUS_SHIFT 0
-#define BCHP_PCIE_0_DMA_TX_LIST1_CUR_DESC_L_ADDR_TX_L1_CUR_STATUS_DEFAULT 0x00000000
-
-/***************************************************************************
- *TX_LIST1_CUR_DESC_U_ADDR - Tx List1 Current Descriptor Upper Address
- ***************************************************************************/
-/* PCIE_0_DMA :: TX_LIST1_CUR_DESC_U_ADDR :: TX_L1_CUR_DESC_U_ADDR [31:00] */
-#define BCHP_PCIE_0_DMA_TX_LIST1_CUR_DESC_U_ADDR_TX_L1_CUR_DESC_U_ADDR_MASK 0xffffffff
-#define BCHP_PCIE_0_DMA_TX_LIST1_CUR_DESC_U_ADDR_TX_L1_CUR_DESC_U_ADDR_SHIFT 0
-#define BCHP_PCIE_0_DMA_TX_LIST1_CUR_DESC_U_ADDR_TX_L1_CUR_DESC_U_ADDR_DEFAULT 0x00000000
-
-/***************************************************************************
- *TX_LIST1_CUR_BYTE_CNT - Tx List1 Current Descriptor Byte Count
- ***************************************************************************/
-/* PCIE_0_DMA :: TX_LIST1_CUR_BYTE_CNT :: TX_L1_CUR_BYTE_CNT [31:00] */
-#define BCHP_PCIE_0_DMA_TX_LIST1_CUR_BYTE_CNT_TX_L1_CUR_BYTE_CNT_MASK 0xffffffff
-#define BCHP_PCIE_0_DMA_TX_LIST1_CUR_BYTE_CNT_TX_L1_CUR_BYTE_CNT_SHIFT 0
-#define BCHP_PCIE_0_DMA_TX_LIST1_CUR_BYTE_CNT_TX_L1_CUR_BYTE_CNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *RX_FIRST_DESC_L_ADDR_LIST0 - Rx Descriptor List0 First Descriptor Lower Address
- ***************************************************************************/
-/* PCIE_0_DMA :: RX_FIRST_DESC_L_ADDR_LIST0 :: DESC_ADDR [31:05] */
-#define BCHP_PCIE_0_DMA_RX_FIRST_DESC_L_ADDR_LIST0_DESC_ADDR_MASK 0xffffffe0
-#define BCHP_PCIE_0_DMA_RX_FIRST_DESC_L_ADDR_LIST0_DESC_ADDR_SHIFT 5
-#define BCHP_PCIE_0_DMA_RX_FIRST_DESC_L_ADDR_LIST0_DESC_ADDR_DEFAULT 0x00000000
-
-/* PCIE_0_DMA :: RX_FIRST_DESC_L_ADDR_LIST0 :: reserved0 [04:01] */
-#define BCHP_PCIE_0_DMA_RX_FIRST_DESC_L_ADDR_LIST0_reserved0_MASK 0x0000001e
-#define BCHP_PCIE_0_DMA_RX_FIRST_DESC_L_ADDR_LIST0_reserved0_SHIFT 1
-
-/* PCIE_0_DMA :: RX_FIRST_DESC_L_ADDR_LIST0 :: RX_DESC_LIST0_VALID [00:00] */
-#define BCHP_PCIE_0_DMA_RX_FIRST_DESC_L_ADDR_LIST0_RX_DESC_LIST0_VALID_MASK 0x00000001
-#define BCHP_PCIE_0_DMA_RX_FIRST_DESC_L_ADDR_LIST0_RX_DESC_LIST0_VALID_SHIFT 0
-#define BCHP_PCIE_0_DMA_RX_FIRST_DESC_L_ADDR_LIST0_RX_DESC_LIST0_VALID_DEFAULT 0x00000000
-
-/***************************************************************************
- *RX_FIRST_DESC_U_ADDR_LIST0 - Rx Descriptor List0 First Descriptor Upper Address
- ***************************************************************************/
-/* PCIE_0_DMA :: RX_FIRST_DESC_U_ADDR_LIST0 :: DESC_ADDR [31:00] */
-#define BCHP_PCIE_0_DMA_RX_FIRST_DESC_U_ADDR_LIST0_DESC_ADDR_MASK 0xffffffff
-#define BCHP_PCIE_0_DMA_RX_FIRST_DESC_U_ADDR_LIST0_DESC_ADDR_SHIFT 0
-#define BCHP_PCIE_0_DMA_RX_FIRST_DESC_U_ADDR_LIST0_DESC_ADDR_DEFAULT 0x00000000
-
-/***************************************************************************
- *RX_FIRST_DESC_L_ADDR_LIST1 - Rx Descriptor List1 First Descriptor Lower Address
- ***************************************************************************/
-/* PCIE_0_DMA :: RX_FIRST_DESC_L_ADDR_LIST1 :: DESC_ADDR [31:05] */
-#define BCHP_PCIE_0_DMA_RX_FIRST_DESC_L_ADDR_LIST1_DESC_ADDR_MASK 0xffffffe0
-#define BCHP_PCIE_0_DMA_RX_FIRST_DESC_L_ADDR_LIST1_DESC_ADDR_SHIFT 5
-#define BCHP_PCIE_0_DMA_RX_FIRST_DESC_L_ADDR_LIST1_DESC_ADDR_DEFAULT 0x00000000
-
-/* PCIE_0_DMA :: RX_FIRST_DESC_L_ADDR_LIST1 :: reserved0 [04:01] */
-#define BCHP_PCIE_0_DMA_RX_FIRST_DESC_L_ADDR_LIST1_reserved0_MASK 0x0000001e
-#define BCHP_PCIE_0_DMA_RX_FIRST_DESC_L_ADDR_LIST1_reserved0_SHIFT 1
-
-/* PCIE_0_DMA :: RX_FIRST_DESC_L_ADDR_LIST1 :: RX_DESC_LIST1_VALID [00:00] */
-#define BCHP_PCIE_0_DMA_RX_FIRST_DESC_L_ADDR_LIST1_RX_DESC_LIST1_VALID_MASK 0x00000001
-#define BCHP_PCIE_0_DMA_RX_FIRST_DESC_L_ADDR_LIST1_RX_DESC_LIST1_VALID_SHIFT 0
-#define BCHP_PCIE_0_DMA_RX_FIRST_DESC_L_ADDR_LIST1_RX_DESC_LIST1_VALID_DEFAULT 0x00000000
-
-/***************************************************************************
- *RX_FIRST_DESC_U_ADDR_LIST1 - Rx Descriptor List1 First Descriptor Upper Address
- ***************************************************************************/
-/* PCIE_0_DMA :: RX_FIRST_DESC_U_ADDR_LIST1 :: DESC_ADDR [31:00] */
-#define BCHP_PCIE_0_DMA_RX_FIRST_DESC_U_ADDR_LIST1_DESC_ADDR_MASK 0xffffffff
-#define BCHP_PCIE_0_DMA_RX_FIRST_DESC_U_ADDR_LIST1_DESC_ADDR_SHIFT 0
-#define BCHP_PCIE_0_DMA_RX_FIRST_DESC_U_ADDR_LIST1_DESC_ADDR_DEFAULT 0x00000000
-
-/***************************************************************************
- *RX_SW_DESC_LIST_CTRL_STS - Rx Software Descriptor List Control and Status
- ***************************************************************************/
-/* PCIE_0_DMA :: RX_SW_DESC_LIST_CTRL_STS :: reserved0 [31:20] */
-#define BCHP_PCIE_0_DMA_RX_SW_DESC_LIST_CTRL_STS_reserved0_MASK 0xfff00000
-#define BCHP_PCIE_0_DMA_RX_SW_DESC_LIST_CTRL_STS_reserved0_SHIFT 20
-
-/* PCIE_0_DMA :: RX_SW_DESC_LIST_CTRL_STS :: BURST_SIZE_OVERRIDE [19:19] */
-#define BCHP_PCIE_0_DMA_RX_SW_DESC_LIST_CTRL_STS_BURST_SIZE_OVERRIDE_MASK 0x00080000
-#define BCHP_PCIE_0_DMA_RX_SW_DESC_LIST_CTRL_STS_BURST_SIZE_OVERRIDE_SHIFT 19
-#define BCHP_PCIE_0_DMA_RX_SW_DESC_LIST_CTRL_STS_BURST_SIZE_OVERRIDE_DEFAULT 0x00000000
-
-/* PCIE_0_DMA :: RX_SW_DESC_LIST_CTRL_STS :: BURST_SIZE_OVERRIDE_VALUE [18:16] */
-#define BCHP_PCIE_0_DMA_RX_SW_DESC_LIST_CTRL_STS_BURST_SIZE_OVERRIDE_VALUE_MASK 0x00070000
-#define BCHP_PCIE_0_DMA_RX_SW_DESC_LIST_CTRL_STS_BURST_SIZE_OVERRIDE_VALUE_SHIFT 16
-#define BCHP_PCIE_0_DMA_RX_SW_DESC_LIST_CTRL_STS_BURST_SIZE_OVERRIDE_VALUE_DEFAULT 0x00000000
-
-/* PCIE_0_DMA :: RX_SW_DESC_LIST_CTRL_STS :: reserved1 [15:14] */
-#define BCHP_PCIE_0_DMA_RX_SW_DESC_LIST_CTRL_STS_reserved1_MASK 0x0000c000
-#define BCHP_PCIE_0_DMA_RX_SW_DESC_LIST_CTRL_STS_reserved1_SHIFT 14
-
-/* PCIE_0_DMA :: RX_SW_DESC_LIST_CTRL_STS :: DESC_ENDIAN_MODE [13:12] */
-#define BCHP_PCIE_0_DMA_RX_SW_DESC_LIST_CTRL_STS_DESC_ENDIAN_MODE_MASK 0x00003000
-#define BCHP_PCIE_0_DMA_RX_SW_DESC_LIST_CTRL_STS_DESC_ENDIAN_MODE_SHIFT 12
-#define BCHP_PCIE_0_DMA_RX_SW_DESC_LIST_CTRL_STS_DESC_ENDIAN_MODE_DEFAULT 0x00000000
-
-/* PCIE_0_DMA :: RX_SW_DESC_LIST_CTRL_STS :: reserved2 [11:10] */
-#define BCHP_PCIE_0_DMA_RX_SW_DESC_LIST_CTRL_STS_reserved2_MASK 0x00000c00
-#define BCHP_PCIE_0_DMA_RX_SW_DESC_LIST_CTRL_STS_reserved2_SHIFT 10
-
-/* PCIE_0_DMA :: RX_SW_DESC_LIST_CTRL_STS :: LOCAL_DESC [09:09] */
-#define BCHP_PCIE_0_DMA_RX_SW_DESC_LIST_CTRL_STS_LOCAL_DESC_MASK 0x00000200
-#define BCHP_PCIE_0_DMA_RX_SW_DESC_LIST_CTRL_STS_LOCAL_DESC_SHIFT 9
-#define BCHP_PCIE_0_DMA_RX_SW_DESC_LIST_CTRL_STS_LOCAL_DESC_DEFAULT 0x00000000
-
-/* PCIE_0_DMA :: RX_SW_DESC_LIST_CTRL_STS :: DMA_MODE [08:08] */
-#define BCHP_PCIE_0_DMA_RX_SW_DESC_LIST_CTRL_STS_DMA_MODE_MASK 0x00000100
-#define BCHP_PCIE_0_DMA_RX_SW_DESC_LIST_CTRL_STS_DMA_MODE_SHIFT 8
-#define BCHP_PCIE_0_DMA_RX_SW_DESC_LIST_CTRL_STS_DMA_MODE_DEFAULT 0x00000000
-
-/* PCIE_0_DMA :: RX_SW_DESC_LIST_CTRL_STS :: reserved3 [07:06] */
-#define BCHP_PCIE_0_DMA_RX_SW_DESC_LIST_CTRL_STS_reserved3_MASK 0x000000c0
-#define BCHP_PCIE_0_DMA_RX_SW_DESC_LIST_CTRL_STS_reserved3_SHIFT 6
-
-/* PCIE_0_DMA :: RX_SW_DESC_LIST_CTRL_STS :: DMA_STATUS [05:04] */
-#define BCHP_PCIE_0_DMA_RX_SW_DESC_LIST_CTRL_STS_DMA_STATUS_MASK 0x00000030
-#define BCHP_PCIE_0_DMA_RX_SW_DESC_LIST_CTRL_STS_DMA_STATUS_SHIFT 4
-#define BCHP_PCIE_0_DMA_RX_SW_DESC_LIST_CTRL_STS_DMA_STATUS_DEFAULT 0x00000000
-
-/* PCIE_0_DMA :: RX_SW_DESC_LIST_CTRL_STS :: DMA_DATA_SERV_PTR [03:03] */
-#define BCHP_PCIE_0_DMA_RX_SW_DESC_LIST_CTRL_STS_DMA_DATA_SERV_PTR_MASK 0x00000008
-#define BCHP_PCIE_0_DMA_RX_SW_DESC_LIST_CTRL_STS_DMA_DATA_SERV_PTR_SHIFT 3
-#define BCHP_PCIE_0_DMA_RX_SW_DESC_LIST_CTRL_STS_DMA_DATA_SERV_PTR_DEFAULT 0x00000000
-
-/* PCIE_0_DMA :: RX_SW_DESC_LIST_CTRL_STS :: DESC_SERV_PTR [02:02] */
-#define BCHP_PCIE_0_DMA_RX_SW_DESC_LIST_CTRL_STS_DESC_SERV_PTR_MASK 0x00000004
-#define BCHP_PCIE_0_DMA_RX_SW_DESC_LIST_CTRL_STS_DESC_SERV_PTR_SHIFT 2
-#define BCHP_PCIE_0_DMA_RX_SW_DESC_LIST_CTRL_STS_DESC_SERV_PTR_DEFAULT 0x00000000
-
-/* PCIE_0_DMA :: RX_SW_DESC_LIST_CTRL_STS :: reserved4 [01:01] */
-#define BCHP_PCIE_0_DMA_RX_SW_DESC_LIST_CTRL_STS_reserved4_MASK 0x00000002
-#define BCHP_PCIE_0_DMA_RX_SW_DESC_LIST_CTRL_STS_reserved4_SHIFT 1
-
-/* PCIE_0_DMA :: RX_SW_DESC_LIST_CTRL_STS :: RX_DMA_RUN_STOP [00:00] */
-#define BCHP_PCIE_0_DMA_RX_SW_DESC_LIST_CTRL_STS_RX_DMA_RUN_STOP_MASK 0x00000001
-#define BCHP_PCIE_0_DMA_RX_SW_DESC_LIST_CTRL_STS_RX_DMA_RUN_STOP_SHIFT 0
-#define BCHP_PCIE_0_DMA_RX_SW_DESC_LIST_CTRL_STS_RX_DMA_RUN_STOP_DEFAULT 0x00000000
-
-/***************************************************************************
- *RX_WAKE_CTRL - Rx DMA Wake Control
- ***************************************************************************/
-/* PCIE_0_DMA :: RX_WAKE_CTRL :: reserved0 [31:02] */
-#define BCHP_PCIE_0_DMA_RX_WAKE_CTRL_reserved0_MASK 0xfffffffc
-#define BCHP_PCIE_0_DMA_RX_WAKE_CTRL_reserved0_SHIFT 2
-
-/* PCIE_0_DMA :: RX_WAKE_CTRL :: WAKE_MODE [01:01] */
-#define BCHP_PCIE_0_DMA_RX_WAKE_CTRL_WAKE_MODE_MASK 0x00000002
-#define BCHP_PCIE_0_DMA_RX_WAKE_CTRL_WAKE_MODE_SHIFT 1
-#define BCHP_PCIE_0_DMA_RX_WAKE_CTRL_WAKE_MODE_DEFAULT 0x00000000
-
-/* PCIE_0_DMA :: RX_WAKE_CTRL :: WAKE [00:00] */
-#define BCHP_PCIE_0_DMA_RX_WAKE_CTRL_WAKE_MASK 0x00000001
-#define BCHP_PCIE_0_DMA_RX_WAKE_CTRL_WAKE_SHIFT 0
-#define BCHP_PCIE_0_DMA_RX_WAKE_CTRL_WAKE_DEFAULT 0x00000000
-
-/***************************************************************************
- *RX_ERROR_STATUS - Rx Engine Error Status
- ***************************************************************************/
-/* PCIE_0_DMA :: RX_ERROR_STATUS :: reserved0 [31:10] */
-#define BCHP_PCIE_0_DMA_RX_ERROR_STATUS_reserved0_MASK 0xfffffc00
-#define BCHP_PCIE_0_DMA_RX_ERROR_STATUS_reserved0_SHIFT 10
-
-/* PCIE_0_DMA :: RX_ERROR_STATUS :: RX_L1_DESC_TX_ABORT_ERRORS [09:09] */
-#define BCHP_PCIE_0_DMA_RX_ERROR_STATUS_RX_L1_DESC_TX_ABORT_ERRORS_MASK 0x00000200
-#define BCHP_PCIE_0_DMA_RX_ERROR_STATUS_RX_L1_DESC_TX_ABORT_ERRORS_SHIFT 9
-#define BCHP_PCIE_0_DMA_RX_ERROR_STATUS_RX_L1_DESC_TX_ABORT_ERRORS_DEFAULT 0x00000000
-
-/* PCIE_0_DMA :: RX_ERROR_STATUS :: reserved1 [08:08] */
-#define BCHP_PCIE_0_DMA_RX_ERROR_STATUS_reserved1_MASK 0x00000100
-#define BCHP_PCIE_0_DMA_RX_ERROR_STATUS_reserved1_SHIFT 8
-
-/* PCIE_0_DMA :: RX_ERROR_STATUS :: RX_L0_DESC_TX_ABORT_ERRORS [07:07] */
-#define BCHP_PCIE_0_DMA_RX_ERROR_STATUS_RX_L0_DESC_TX_ABORT_ERRORS_MASK 0x00000080
-#define BCHP_PCIE_0_DMA_RX_ERROR_STATUS_RX_L0_DESC_TX_ABORT_ERRORS_SHIFT 7
-#define BCHP_PCIE_0_DMA_RX_ERROR_STATUS_RX_L0_DESC_TX_ABORT_ERRORS_DEFAULT 0x00000000
-
-/* PCIE_0_DMA :: RX_ERROR_STATUS :: reserved2 [06:06] */
-#define BCHP_PCIE_0_DMA_RX_ERROR_STATUS_reserved2_MASK 0x00000040
-#define BCHP_PCIE_0_DMA_RX_ERROR_STATUS_reserved2_SHIFT 6
-
-/* PCIE_0_DMA :: RX_ERROR_STATUS :: RX_L1_DATA_TX_ABORT_ERRORS [05:05] */
-#define BCHP_PCIE_0_DMA_RX_ERROR_STATUS_RX_L1_DATA_TX_ABORT_ERRORS_MASK 0x00000020
-#define BCHP_PCIE_0_DMA_RX_ERROR_STATUS_RX_L1_DATA_TX_ABORT_ERRORS_SHIFT 5
-#define BCHP_PCIE_0_DMA_RX_ERROR_STATUS_RX_L1_DATA_TX_ABORT_ERRORS_DEFAULT 0x00000000
-
-/* PCIE_0_DMA :: RX_ERROR_STATUS :: reserved3 [04:03] */
-#define BCHP_PCIE_0_DMA_RX_ERROR_STATUS_reserved3_MASK 0x00000018
-#define BCHP_PCIE_0_DMA_RX_ERROR_STATUS_reserved3_SHIFT 3
-
-/* PCIE_0_DMA :: RX_ERROR_STATUS :: RX_L0_DATA_TX_ABORT_ERRORS [02:02] */
-#define BCHP_PCIE_0_DMA_RX_ERROR_STATUS_RX_L0_DATA_TX_ABORT_ERRORS_MASK 0x00000004
-#define BCHP_PCIE_0_DMA_RX_ERROR_STATUS_RX_L0_DATA_TX_ABORT_ERRORS_SHIFT 2
-#define BCHP_PCIE_0_DMA_RX_ERROR_STATUS_RX_L0_DATA_TX_ABORT_ERRORS_DEFAULT 0x00000000
-
-/* PCIE_0_DMA :: RX_ERROR_STATUS :: reserved4 [01:00] */
-#define BCHP_PCIE_0_DMA_RX_ERROR_STATUS_reserved4_MASK 0x00000003
-#define BCHP_PCIE_0_DMA_RX_ERROR_STATUS_reserved4_SHIFT 0
-
-/***************************************************************************
- *RX_LIST0_CUR_DESC_L_ADDR - Rx List0 Current Descriptor Lower Address
- ***************************************************************************/
-/* PCIE_0_DMA :: RX_LIST0_CUR_DESC_L_ADDR :: RX_L0_CUR_DESC_L_ADDR [31:05] */
-#define BCHP_PCIE_0_DMA_RX_LIST0_CUR_DESC_L_ADDR_RX_L0_CUR_DESC_L_ADDR_MASK 0xffffffe0
-#define BCHP_PCIE_0_DMA_RX_LIST0_CUR_DESC_L_ADDR_RX_L0_CUR_DESC_L_ADDR_SHIFT 5
-#define BCHP_PCIE_0_DMA_RX_LIST0_CUR_DESC_L_ADDR_RX_L0_CUR_DESC_L_ADDR_DEFAULT 0x00000000
-
-/* PCIE_0_DMA :: RX_LIST0_CUR_DESC_L_ADDR :: reserved0 [04:04] */
-#define BCHP_PCIE_0_DMA_RX_LIST0_CUR_DESC_L_ADDR_reserved0_MASK 0x00000010
-#define BCHP_PCIE_0_DMA_RX_LIST0_CUR_DESC_L_ADDR_reserved0_SHIFT 4
-
-/* PCIE_0_DMA :: RX_LIST0_CUR_DESC_L_ADDR :: RX_L0_CUR_LIST [03:03] */
-#define BCHP_PCIE_0_DMA_RX_LIST0_CUR_DESC_L_ADDR_RX_L0_CUR_LIST_MASK 0x00000008
-#define BCHP_PCIE_0_DMA_RX_LIST0_CUR_DESC_L_ADDR_RX_L0_CUR_LIST_SHIFT 3
-#define BCHP_PCIE_0_DMA_RX_LIST0_CUR_DESC_L_ADDR_RX_L0_CUR_LIST_DEFAULT 0x00000000
-
-/* PCIE_0_DMA :: RX_LIST0_CUR_DESC_L_ADDR :: RX_L0_CUR_IN_PROGRESS [02:02] */
-#define BCHP_PCIE_0_DMA_RX_LIST0_CUR_DESC_L_ADDR_RX_L0_CUR_IN_PROGRESS_MASK 0x00000004
-#define BCHP_PCIE_0_DMA_RX_LIST0_CUR_DESC_L_ADDR_RX_L0_CUR_IN_PROGRESS_SHIFT 2
-#define BCHP_PCIE_0_DMA_RX_LIST0_CUR_DESC_L_ADDR_RX_L0_CUR_IN_PROGRESS_DEFAULT 0x00000000
-
-/* PCIE_0_DMA :: RX_LIST0_CUR_DESC_L_ADDR :: RX_L0_CUR_STATUS [01:00] */
-#define BCHP_PCIE_0_DMA_RX_LIST0_CUR_DESC_L_ADDR_RX_L0_CUR_STATUS_MASK 0x00000003
-#define BCHP_PCIE_0_DMA_RX_LIST0_CUR_DESC_L_ADDR_RX_L0_CUR_STATUS_SHIFT 0
-#define BCHP_PCIE_0_DMA_RX_LIST0_CUR_DESC_L_ADDR_RX_L0_CUR_STATUS_DEFAULT 0x00000000
-
-/***************************************************************************
- *RX_LIST0_CUR_DESC_U_ADDR - Rx List0 Current Descriptor Upper Address
- ***************************************************************************/
-/* PCIE_0_DMA :: RX_LIST0_CUR_DESC_U_ADDR :: RX_L0_CUR_DESC_U_ADDR [31:00] */
-#define BCHP_PCIE_0_DMA_RX_LIST0_CUR_DESC_U_ADDR_RX_L0_CUR_DESC_U_ADDR_MASK 0xffffffff
-#define BCHP_PCIE_0_DMA_RX_LIST0_CUR_DESC_U_ADDR_RX_L0_CUR_DESC_U_ADDR_SHIFT 0
-#define BCHP_PCIE_0_DMA_RX_LIST0_CUR_DESC_U_ADDR_RX_L0_CUR_DESC_U_ADDR_DEFAULT 0x00000000
-
-/***************************************************************************
- *RX_LIST0_CUR_BYTE_CNT - Rx List0 Current Descriptor Byte Count
- ***************************************************************************/
-/* PCIE_0_DMA :: RX_LIST0_CUR_BYTE_CNT :: RX_L0_CUR_BYTE_CNT [31:00] */
-#define BCHP_PCIE_0_DMA_RX_LIST0_CUR_BYTE_CNT_RX_L0_CUR_BYTE_CNT_MASK 0xffffffff
-#define BCHP_PCIE_0_DMA_RX_LIST0_CUR_BYTE_CNT_RX_L0_CUR_BYTE_CNT_SHIFT 0
-#define BCHP_PCIE_0_DMA_RX_LIST0_CUR_BYTE_CNT_RX_L0_CUR_BYTE_CNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *RX_LIST1_CUR_DESC_L_ADDR - Rx List1 Current Descriptor Lower address
- ***************************************************************************/
-/* PCIE_0_DMA :: RX_LIST1_CUR_DESC_L_ADDR :: RX_L1_CUR_DESC_L_ADDR [31:05] */
-#define BCHP_PCIE_0_DMA_RX_LIST1_CUR_DESC_L_ADDR_RX_L1_CUR_DESC_L_ADDR_MASK 0xffffffe0
-#define BCHP_PCIE_0_DMA_RX_LIST1_CUR_DESC_L_ADDR_RX_L1_CUR_DESC_L_ADDR_SHIFT 5
-#define BCHP_PCIE_0_DMA_RX_LIST1_CUR_DESC_L_ADDR_RX_L1_CUR_DESC_L_ADDR_DEFAULT 0x00000000
-
-/* PCIE_0_DMA :: RX_LIST1_CUR_DESC_L_ADDR :: reserved0 [04:04] */
-#define BCHP_PCIE_0_DMA_RX_LIST1_CUR_DESC_L_ADDR_reserved0_MASK 0x00000010
-#define BCHP_PCIE_0_DMA_RX_LIST1_CUR_DESC_L_ADDR_reserved0_SHIFT 4
-
-/* PCIE_0_DMA :: RX_LIST1_CUR_DESC_L_ADDR :: RX_L1_CUR_LIST [03:03] */
-#define BCHP_PCIE_0_DMA_RX_LIST1_CUR_DESC_L_ADDR_RX_L1_CUR_LIST_MASK 0x00000008
-#define BCHP_PCIE_0_DMA_RX_LIST1_CUR_DESC_L_ADDR_RX_L1_CUR_LIST_SHIFT 3
-#define BCHP_PCIE_0_DMA_RX_LIST1_CUR_DESC_L_ADDR_RX_L1_CUR_LIST_DEFAULT 0x00000000
-
-/* PCIE_0_DMA :: RX_LIST1_CUR_DESC_L_ADDR :: RX_L1_CUR_IN_PROGRESS [02:02] */
-#define BCHP_PCIE_0_DMA_RX_LIST1_CUR_DESC_L_ADDR_RX_L1_CUR_IN_PROGRESS_MASK 0x00000004
-#define BCHP_PCIE_0_DMA_RX_LIST1_CUR_DESC_L_ADDR_RX_L1_CUR_IN_PROGRESS_SHIFT 2
-#define BCHP_PCIE_0_DMA_RX_LIST1_CUR_DESC_L_ADDR_RX_L1_CUR_IN_PROGRESS_DEFAULT 0x00000000
-
-/* PCIE_0_DMA :: RX_LIST1_CUR_DESC_L_ADDR :: RX_L1_CUR_STATUS [01:00] */
-#define BCHP_PCIE_0_DMA_RX_LIST1_CUR_DESC_L_ADDR_RX_L1_CUR_STATUS_MASK 0x00000003
-#define BCHP_PCIE_0_DMA_RX_LIST1_CUR_DESC_L_ADDR_RX_L1_CUR_STATUS_SHIFT 0
-#define BCHP_PCIE_0_DMA_RX_LIST1_CUR_DESC_L_ADDR_RX_L1_CUR_STATUS_DEFAULT 0x00000000
-
-/***************************************************************************
- *RX_LIST1_CUR_DESC_U_ADDR - Rx List1 Current Descriptor Upper address
- ***************************************************************************/
-/* PCIE_0_DMA :: RX_LIST1_CUR_DESC_U_ADDR :: RX_L1_CUR_DESC_U_ADDR [31:00] */
-#define BCHP_PCIE_0_DMA_RX_LIST1_CUR_DESC_U_ADDR_RX_L1_CUR_DESC_U_ADDR_MASK 0xffffffff
-#define BCHP_PCIE_0_DMA_RX_LIST1_CUR_DESC_U_ADDR_RX_L1_CUR_DESC_U_ADDR_SHIFT 0
-#define BCHP_PCIE_0_DMA_RX_LIST1_CUR_DESC_U_ADDR_RX_L1_CUR_DESC_U_ADDR_DEFAULT 0x00000000
-
-/***************************************************************************
- *RX_LIST1_CUR_BYTE_CNT - Rx List1 Current Descriptor Byte Count
- ***************************************************************************/
-/* PCIE_0_DMA :: RX_LIST1_CUR_BYTE_CNT :: RX_L1_CUR_BYTE_CNT [31:00] */
-#define BCHP_PCIE_0_DMA_RX_LIST1_CUR_BYTE_CNT_RX_L1_CUR_BYTE_CNT_MASK 0xffffffff
-#define BCHP_PCIE_0_DMA_RX_LIST1_CUR_BYTE_CNT_RX_L1_CUR_BYTE_CNT_SHIFT 0
-#define BCHP_PCIE_0_DMA_RX_LIST1_CUR_BYTE_CNT_RX_L1_CUR_BYTE_CNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *DMA_DEBUG_OPTIONS_REG - DMA Debug Options Register
- ***************************************************************************/
-/* PCIE_0_DMA :: DMA_DEBUG_OPTIONS_REG :: DMA_DEBUG_TX_DMA_SOFT_RST [31:31] */
-#define BCHP_PCIE_0_DMA_DMA_DEBUG_OPTIONS_REG_DMA_DEBUG_TX_DMA_SOFT_RST_MASK 0x80000000
-#define BCHP_PCIE_0_DMA_DMA_DEBUG_OPTIONS_REG_DMA_DEBUG_TX_DMA_SOFT_RST_SHIFT 31
-#define BCHP_PCIE_0_DMA_DMA_DEBUG_OPTIONS_REG_DMA_DEBUG_TX_DMA_SOFT_RST_DEFAULT 0x00000000
-
-/* PCIE_0_DMA :: DMA_DEBUG_OPTIONS_REG :: DMA_DEBUG_RX_DMA_SOFT_RST [30:30] */
-#define BCHP_PCIE_0_DMA_DMA_DEBUG_OPTIONS_REG_DMA_DEBUG_RX_DMA_SOFT_RST_MASK 0x40000000
-#define BCHP_PCIE_0_DMA_DMA_DEBUG_OPTIONS_REG_DMA_DEBUG_RX_DMA_SOFT_RST_SHIFT 30
-#define BCHP_PCIE_0_DMA_DMA_DEBUG_OPTIONS_REG_DMA_DEBUG_RX_DMA_SOFT_RST_DEFAULT 0x00000000
-
-/* PCIE_0_DMA :: DMA_DEBUG_OPTIONS_REG :: DMA_DEBUG_TX_DMA_RD_Q_SOFT_RST [29:29] */
-#define BCHP_PCIE_0_DMA_DMA_DEBUG_OPTIONS_REG_DMA_DEBUG_TX_DMA_RD_Q_SOFT_RST_MASK 0x20000000
-#define BCHP_PCIE_0_DMA_DMA_DEBUG_OPTIONS_REG_DMA_DEBUG_TX_DMA_RD_Q_SOFT_RST_SHIFT 29
-#define BCHP_PCIE_0_DMA_DMA_DEBUG_OPTIONS_REG_DMA_DEBUG_TX_DMA_RD_Q_SOFT_RST_DEFAULT 0x00000000
-
-/* PCIE_0_DMA :: DMA_DEBUG_OPTIONS_REG :: DMA_DEBUG_RX_DMA_WR_Q_SOFT_RST [28:28] */
-#define BCHP_PCIE_0_DMA_DMA_DEBUG_OPTIONS_REG_DMA_DEBUG_RX_DMA_WR_Q_SOFT_RST_MASK 0x10000000
-#define BCHP_PCIE_0_DMA_DMA_DEBUG_OPTIONS_REG_DMA_DEBUG_RX_DMA_WR_Q_SOFT_RST_SHIFT 28
-#define BCHP_PCIE_0_DMA_DMA_DEBUG_OPTIONS_REG_DMA_DEBUG_RX_DMA_WR_Q_SOFT_RST_DEFAULT 0x00000000
-
-/* PCIE_0_DMA :: DMA_DEBUG_OPTIONS_REG :: RSVD_DMA_DEBUG_0 [27:10] */
-#define BCHP_PCIE_0_DMA_DMA_DEBUG_OPTIONS_REG_RSVD_DMA_DEBUG_0_MASK 0x0ffffc00
-#define BCHP_PCIE_0_DMA_DMA_DEBUG_OPTIONS_REG_RSVD_DMA_DEBUG_0_SHIFT 10
-#define BCHP_PCIE_0_DMA_DMA_DEBUG_OPTIONS_REG_RSVD_DMA_DEBUG_0_DEFAULT 0x00000000
-
-/* PCIE_0_DMA :: DMA_DEBUG_OPTIONS_REG :: DMA_DEBUG_SPQ_SNAP_PW_DIS [09:09] */
-#define BCHP_PCIE_0_DMA_DMA_DEBUG_OPTIONS_REG_DMA_DEBUG_SPQ_SNAP_PW_DIS_MASK 0x00000200
-#define BCHP_PCIE_0_DMA_DMA_DEBUG_OPTIONS_REG_DMA_DEBUG_SPQ_SNAP_PW_DIS_SHIFT 9
-#define BCHP_PCIE_0_DMA_DMA_DEBUG_OPTIONS_REG_DMA_DEBUG_SPQ_SNAP_PW_DIS_DEFAULT 0x00000000
-
-/* PCIE_0_DMA :: DMA_DEBUG_OPTIONS_REG :: DMA_DEBUG_OUTCP_Q_RO [08:08] */
-#define BCHP_PCIE_0_DMA_DMA_DEBUG_OPTIONS_REG_DMA_DEBUG_OUTCP_Q_RO_MASK 0x00000100
-#define BCHP_PCIE_0_DMA_DMA_DEBUG_OPTIONS_REG_DMA_DEBUG_OUTCP_Q_RO_SHIFT 8
-#define BCHP_PCIE_0_DMA_DMA_DEBUG_OPTIONS_REG_DMA_DEBUG_OUTCP_Q_RO_DEFAULT 0x00000000
-
-/* PCIE_0_DMA :: DMA_DEBUG_OPTIONS_REG :: DMA_DEBUG_NO_TX_DESC [07:07] */
-#define BCHP_PCIE_0_DMA_DMA_DEBUG_OPTIONS_REG_DMA_DEBUG_NO_TX_DESC_MASK 0x00000080
-#define BCHP_PCIE_0_DMA_DMA_DEBUG_OPTIONS_REG_DMA_DEBUG_NO_TX_DESC_SHIFT 7
-#define BCHP_PCIE_0_DMA_DMA_DEBUG_OPTIONS_REG_DMA_DEBUG_NO_TX_DESC_DEFAULT 0x00000000
-
-/* PCIE_0_DMA :: DMA_DEBUG_OPTIONS_REG :: DMA_DEBUG_NO_RX_DESC [06:06] */
-#define BCHP_PCIE_0_DMA_DMA_DEBUG_OPTIONS_REG_DMA_DEBUG_NO_RX_DESC_MASK 0x00000040
-#define BCHP_PCIE_0_DMA_DMA_DEBUG_OPTIONS_REG_DMA_DEBUG_NO_RX_DESC_SHIFT 6
-#define BCHP_PCIE_0_DMA_DMA_DEBUG_OPTIONS_REG_DMA_DEBUG_NO_RX_DESC_DEFAULT 0x00000000
-
-/* PCIE_0_DMA :: DMA_DEBUG_OPTIONS_REG :: DMA_DEBUG_SEL_RX_CNT [05:05] */
-#define BCHP_PCIE_0_DMA_DMA_DEBUG_OPTIONS_REG_DMA_DEBUG_SEL_RX_CNT_MASK 0x00000020
-#define BCHP_PCIE_0_DMA_DMA_DEBUG_OPTIONS_REG_DMA_DEBUG_SEL_RX_CNT_SHIFT 5
-#define BCHP_PCIE_0_DMA_DMA_DEBUG_OPTIONS_REG_DMA_DEBUG_SEL_RX_CNT_DEFAULT 0x00000000
-
-/* PCIE_0_DMA :: DMA_DEBUG_OPTIONS_REG :: DMA_DEBUG_EN_RX_DMA_XFER_CNT [04:04] */
-#define BCHP_PCIE_0_DMA_DMA_DEBUG_OPTIONS_REG_DMA_DEBUG_EN_RX_DMA_XFER_CNT_MASK 0x00000010
-#define BCHP_PCIE_0_DMA_DMA_DEBUG_OPTIONS_REG_DMA_DEBUG_EN_RX_DMA_XFER_CNT_SHIFT 4
-#define BCHP_PCIE_0_DMA_DMA_DEBUG_OPTIONS_REG_DMA_DEBUG_EN_RX_DMA_XFER_CNT_DEFAULT 0x00000000
-
-/* PCIE_0_DMA :: DMA_DEBUG_OPTIONS_REG :: DMA_DEBUG_SEL_TX_CNT [03:03] */
-#define BCHP_PCIE_0_DMA_DMA_DEBUG_OPTIONS_REG_DMA_DEBUG_SEL_TX_CNT_MASK 0x00000008
-#define BCHP_PCIE_0_DMA_DMA_DEBUG_OPTIONS_REG_DMA_DEBUG_SEL_TX_CNT_SHIFT 3
-#define BCHP_PCIE_0_DMA_DMA_DEBUG_OPTIONS_REG_DMA_DEBUG_SEL_TX_CNT_DEFAULT 0x00000000
-
-/* PCIE_0_DMA :: DMA_DEBUG_OPTIONS_REG :: DMA_DEBUG_SINGLE_RD_Q [02:02] */
-#define BCHP_PCIE_0_DMA_DMA_DEBUG_OPTIONS_REG_DMA_DEBUG_SINGLE_RD_Q_MASK 0x00000004
-#define BCHP_PCIE_0_DMA_DMA_DEBUG_OPTIONS_REG_DMA_DEBUG_SINGLE_RD_Q_SHIFT 2
-#define BCHP_PCIE_0_DMA_DMA_DEBUG_OPTIONS_REG_DMA_DEBUG_SINGLE_RD_Q_DEFAULT 0x00000000
-
-/* PCIE_0_DMA :: DMA_DEBUG_OPTIONS_REG :: DMA_DEBUG_SINGLE_WR_Q [01:01] */
-#define BCHP_PCIE_0_DMA_DMA_DEBUG_OPTIONS_REG_DMA_DEBUG_SINGLE_WR_Q_MASK 0x00000002
-#define BCHP_PCIE_0_DMA_DMA_DEBUG_OPTIONS_REG_DMA_DEBUG_SINGLE_WR_Q_SHIFT 1
-#define BCHP_PCIE_0_DMA_DMA_DEBUG_OPTIONS_REG_DMA_DEBUG_SINGLE_WR_Q_DEFAULT 0x00000000
-
-/* PCIE_0_DMA :: DMA_DEBUG_OPTIONS_REG :: DMA_DEBUG_RD_Q_RO [00:00] */
-#define BCHP_PCIE_0_DMA_DMA_DEBUG_OPTIONS_REG_DMA_DEBUG_RD_Q_RO_MASK 0x00000001
-#define BCHP_PCIE_0_DMA_DMA_DEBUG_OPTIONS_REG_DMA_DEBUG_RD_Q_RO_SHIFT 0
-#define BCHP_PCIE_0_DMA_DMA_DEBUG_OPTIONS_REG_DMA_DEBUG_RD_Q_RO_DEFAULT 0x00000000
-
-/***************************************************************************
- *READ_CHANNEL_ERROR_STATUS - Read Channel Error Status
- ***************************************************************************/
-/* PCIE_0_DMA :: READ_CHANNEL_ERROR_STATUS :: TX_ERR_STS_CHAN_7 [31:28] */
-#define BCHP_PCIE_0_DMA_READ_CHANNEL_ERROR_STATUS_TX_ERR_STS_CHAN_7_MASK 0xf0000000
-#define BCHP_PCIE_0_DMA_READ_CHANNEL_ERROR_STATUS_TX_ERR_STS_CHAN_7_SHIFT 28
-#define BCHP_PCIE_0_DMA_READ_CHANNEL_ERROR_STATUS_TX_ERR_STS_CHAN_7_DEFAULT 0x00000000
-
-/* PCIE_0_DMA :: READ_CHANNEL_ERROR_STATUS :: TX_ERR_STS_CHAN_6 [27:24] */
-#define BCHP_PCIE_0_DMA_READ_CHANNEL_ERROR_STATUS_TX_ERR_STS_CHAN_6_MASK 0x0f000000
-#define BCHP_PCIE_0_DMA_READ_CHANNEL_ERROR_STATUS_TX_ERR_STS_CHAN_6_SHIFT 24
-#define BCHP_PCIE_0_DMA_READ_CHANNEL_ERROR_STATUS_TX_ERR_STS_CHAN_6_DEFAULT 0x00000000
-
-/* PCIE_0_DMA :: READ_CHANNEL_ERROR_STATUS :: TX_ERR_STS_CHAN_5 [23:20] */
-#define BCHP_PCIE_0_DMA_READ_CHANNEL_ERROR_STATUS_TX_ERR_STS_CHAN_5_MASK 0x00f00000
-#define BCHP_PCIE_0_DMA_READ_CHANNEL_ERROR_STATUS_TX_ERR_STS_CHAN_5_SHIFT 20
-#define BCHP_PCIE_0_DMA_READ_CHANNEL_ERROR_STATUS_TX_ERR_STS_CHAN_5_DEFAULT 0x00000000
-
-/* PCIE_0_DMA :: READ_CHANNEL_ERROR_STATUS :: TX_ERR_STS_CHAN_4 [19:16] */
-#define BCHP_PCIE_0_DMA_READ_CHANNEL_ERROR_STATUS_TX_ERR_STS_CHAN_4_MASK 0x000f0000
-#define BCHP_PCIE_0_DMA_READ_CHANNEL_ERROR_STATUS_TX_ERR_STS_CHAN_4_SHIFT 16
-#define BCHP_PCIE_0_DMA_READ_CHANNEL_ERROR_STATUS_TX_ERR_STS_CHAN_4_DEFAULT 0x00000000
-
-/* PCIE_0_DMA :: READ_CHANNEL_ERROR_STATUS :: TX_ERR_STS_CHAN_3 [15:12] */
-#define BCHP_PCIE_0_DMA_READ_CHANNEL_ERROR_STATUS_TX_ERR_STS_CHAN_3_MASK 0x0000f000
-#define BCHP_PCIE_0_DMA_READ_CHANNEL_ERROR_STATUS_TX_ERR_STS_CHAN_3_SHIFT 12
-#define BCHP_PCIE_0_DMA_READ_CHANNEL_ERROR_STATUS_TX_ERR_STS_CHAN_3_DEFAULT 0x00000000
-
-/* PCIE_0_DMA :: READ_CHANNEL_ERROR_STATUS :: TX_ERR_STS_CHAN_2 [11:08] */
-#define BCHP_PCIE_0_DMA_READ_CHANNEL_ERROR_STATUS_TX_ERR_STS_CHAN_2_MASK 0x00000f00
-#define BCHP_PCIE_0_DMA_READ_CHANNEL_ERROR_STATUS_TX_ERR_STS_CHAN_2_SHIFT 8
-#define BCHP_PCIE_0_DMA_READ_CHANNEL_ERROR_STATUS_TX_ERR_STS_CHAN_2_DEFAULT 0x00000000
-
-/* PCIE_0_DMA :: READ_CHANNEL_ERROR_STATUS :: TX_ERR_STS_CHAN_1 [07:04] */
-#define BCHP_PCIE_0_DMA_READ_CHANNEL_ERROR_STATUS_TX_ERR_STS_CHAN_1_MASK 0x000000f0
-#define BCHP_PCIE_0_DMA_READ_CHANNEL_ERROR_STATUS_TX_ERR_STS_CHAN_1_SHIFT 4
-#define BCHP_PCIE_0_DMA_READ_CHANNEL_ERROR_STATUS_TX_ERR_STS_CHAN_1_DEFAULT 0x00000000
-
-/* PCIE_0_DMA :: READ_CHANNEL_ERROR_STATUS :: TX_ERR_STS_CHAN_0 [03:00] */
-#define BCHP_PCIE_0_DMA_READ_CHANNEL_ERROR_STATUS_TX_ERR_STS_CHAN_0_MASK 0x0000000f
-#define BCHP_PCIE_0_DMA_READ_CHANNEL_ERROR_STATUS_TX_ERR_STS_CHAN_0_SHIFT 0
-#define BCHP_PCIE_0_DMA_READ_CHANNEL_ERROR_STATUS_TX_ERR_STS_CHAN_0_DEFAULT 0x00000000
-
-#endif /* #ifndef BCHP_PCIE_0_DMA_H__ */
-
-/* End of File */
diff --git a/include/linux/brcmstb/7145a0/bchp_pcie_0_ext_cfg.h b/include/linux/brcmstb/7145a0/bchp_pcie_0_ext_cfg.h
deleted file mode 100644
index 7a566d3..0000000
--- a/include/linux/brcmstb/7145a0/bchp_pcie_0_ext_cfg.h
+++ /dev/null
@@ -1,116 +0,0 @@
-/***************************************************************************
- * Copyright (c) 1999-2013, Broadcom Corporation
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
- *
- * Module Description:
- * DO NOT EDIT THIS FILE DIRECTLY
- *
- * This module was generated magically with RDB from a source description
- * file. You must edit the source file for changes to be made to this file.
- *
- *
- * Date: Generated on Sat Apr 6 03:07:51 2013
- * MD5 Checksum d41d8cd98f00b204e9800998ecf8427e
- *
- * Compiled with: RDB Utility combo_header.pl
- * RDB Parser 3.0
- * unknown unknown
- * Perl Interpreter 5.008008
- * Operating System linux
- *
- * Revision History:
- *
- * $brcm_Log: $
- *
- ***************************************************************************/
-
-#ifndef BCHP_PCIE_0_EXT_CFG_H__
-#define BCHP_PCIE_0_EXT_CFG_H__
-
-/***************************************************************************
- *PCIE_0_EXT_CFG - PCIE EXTERNAL CFG Registers
- ***************************************************************************/
-#define BCHP_PCIE_0_EXT_CFG_PCIE_EXT_CFG_DATA_0 0x07808000 /* PCIe External Configuration Space Data[0] */
-#define BCHP_PCIE_0_EXT_CFG_PCIE_EXT_CFG_DATA_1023 0x07808ffc /* PCIe External Configuration Space Data[1023] */
-#define BCHP_PCIE_0_EXT_CFG_PCIE_EXT_CFG_INDEX 0x07809000 /* PCIE External Configuration Access Index */
-#define BCHP_PCIE_0_EXT_CFG_PCIE_EXT_CFG_DATA 0x07809004 /* PCIE External Configuration Access Data */
-#define BCHP_PCIE_0_EXT_CFG_SCRATCH 0x07809008 /* Scratch Register */
-
-/***************************************************************************
- *PCIE_EXT_CFG_DATA_0 - PCIe External Configuration Space Data[0]
- ***************************************************************************/
-/* PCIE_0_EXT_CFG :: PCIE_EXT_CFG_DATA_0 :: DATA [31:00] */
-#define BCHP_PCIE_0_EXT_CFG_PCIE_EXT_CFG_DATA_0_DATA_MASK 0xffffffff
-#define BCHP_PCIE_0_EXT_CFG_PCIE_EXT_CFG_DATA_0_DATA_SHIFT 0
-
-/***************************************************************************
- *PCIE_EXT_CFG_DATA_1023 - PCIe External Configuration Space Data[1023]
- ***************************************************************************/
-/* PCIE_0_EXT_CFG :: PCIE_EXT_CFG_DATA_1023 :: DATA [31:00] */
-#define BCHP_PCIE_0_EXT_CFG_PCIE_EXT_CFG_DATA_1023_DATA_MASK 0xffffffff
-#define BCHP_PCIE_0_EXT_CFG_PCIE_EXT_CFG_DATA_1023_DATA_SHIFT 0
-
-/***************************************************************************
- *PCIE_EXT_CFG_INDEX - PCIE External Configuration Access Index
- ***************************************************************************/
-/* PCIE_0_EXT_CFG :: PCIE_EXT_CFG_INDEX :: UNUSED_1 [31:28] */
-#define BCHP_PCIE_0_EXT_CFG_PCIE_EXT_CFG_INDEX_UNUSED_1_MASK 0xf0000000
-#define BCHP_PCIE_0_EXT_CFG_PCIE_EXT_CFG_INDEX_UNUSED_1_SHIFT 28
-#define BCHP_PCIE_0_EXT_CFG_PCIE_EXT_CFG_INDEX_UNUSED_1_DEFAULT 0x00000000
-
-/* PCIE_0_EXT_CFG :: PCIE_EXT_CFG_INDEX :: BUS_NUM [27:20] */
-#define BCHP_PCIE_0_EXT_CFG_PCIE_EXT_CFG_INDEX_BUS_NUM_MASK 0x0ff00000
-#define BCHP_PCIE_0_EXT_CFG_PCIE_EXT_CFG_INDEX_BUS_NUM_SHIFT 20
-#define BCHP_PCIE_0_EXT_CFG_PCIE_EXT_CFG_INDEX_BUS_NUM_DEFAULT 0x00000000
-
-/* PCIE_0_EXT_CFG :: PCIE_EXT_CFG_INDEX :: DEV_NUM [19:15] */
-#define BCHP_PCIE_0_EXT_CFG_PCIE_EXT_CFG_INDEX_DEV_NUM_MASK 0x000f8000
-#define BCHP_PCIE_0_EXT_CFG_PCIE_EXT_CFG_INDEX_DEV_NUM_SHIFT 15
-#define BCHP_PCIE_0_EXT_CFG_PCIE_EXT_CFG_INDEX_DEV_NUM_DEFAULT 0x00000000
-
-/* PCIE_0_EXT_CFG :: PCIE_EXT_CFG_INDEX :: FUNC_NUM [14:12] */
-#define BCHP_PCIE_0_EXT_CFG_PCIE_EXT_CFG_INDEX_FUNC_NUM_MASK 0x00007000
-#define BCHP_PCIE_0_EXT_CFG_PCIE_EXT_CFG_INDEX_FUNC_NUM_SHIFT 12
-#define BCHP_PCIE_0_EXT_CFG_PCIE_EXT_CFG_INDEX_FUNC_NUM_DEFAULT 0x00000000
-
-/* PCIE_0_EXT_CFG :: PCIE_EXT_CFG_INDEX :: REG_NUM [11:02] */
-#define BCHP_PCIE_0_EXT_CFG_PCIE_EXT_CFG_INDEX_REG_NUM_MASK 0x00000ffc
-#define BCHP_PCIE_0_EXT_CFG_PCIE_EXT_CFG_INDEX_REG_NUM_SHIFT 2
-#define BCHP_PCIE_0_EXT_CFG_PCIE_EXT_CFG_INDEX_REG_NUM_DEFAULT 0x00000000
-
-/* PCIE_0_EXT_CFG :: PCIE_EXT_CFG_INDEX :: UNUSED_0 [01:00] */
-#define BCHP_PCIE_0_EXT_CFG_PCIE_EXT_CFG_INDEX_UNUSED_0_MASK 0x00000003
-#define BCHP_PCIE_0_EXT_CFG_PCIE_EXT_CFG_INDEX_UNUSED_0_SHIFT 0
-#define BCHP_PCIE_0_EXT_CFG_PCIE_EXT_CFG_INDEX_UNUSED_0_DEFAULT 0x00000000
-
-/***************************************************************************
- *PCIE_EXT_CFG_DATA - PCIE External Configuration Access Data
- ***************************************************************************/
-/* PCIE_0_EXT_CFG :: PCIE_EXT_CFG_DATA :: DATA [31:00] */
-#define BCHP_PCIE_0_EXT_CFG_PCIE_EXT_CFG_DATA_DATA_MASK 0xffffffff
-#define BCHP_PCIE_0_EXT_CFG_PCIE_EXT_CFG_DATA_DATA_SHIFT 0
-#define BCHP_PCIE_0_EXT_CFG_PCIE_EXT_CFG_DATA_DATA_DEFAULT 0x00000000
-
-/***************************************************************************
- *SCRATCH - Scratch Register
- ***************************************************************************/
-/* PCIE_0_EXT_CFG :: SCRATCH :: DATA [31:00] */
-#define BCHP_PCIE_0_EXT_CFG_SCRATCH_DATA_MASK 0xffffffff
-#define BCHP_PCIE_0_EXT_CFG_SCRATCH_DATA_SHIFT 0
-#define BCHP_PCIE_0_EXT_CFG_SCRATCH_DATA_DEFAULT 0x00000000
-
-#endif /* #ifndef BCHP_PCIE_0_EXT_CFG_H__ */
-
-/* End of File */
diff --git a/include/linux/brcmstb/7145a0/bchp_pcie_0_intr2.h b/include/linux/brcmstb/7145a0/bchp_pcie_0_intr2.h
deleted file mode 100644
index 0436e55..0000000
--- a/include/linux/brcmstb/7145a0/bchp_pcie_0_intr2.h
+++ /dev/null
@@ -1,2016 +0,0 @@
-/***************************************************************************
- * Copyright (c) 1999-2013, Broadcom Corporation
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
- *
- * Module Description:
- * DO NOT EDIT THIS FILE DIRECTLY
- *
- * This module was generated magically with RDB from a source description
- * file. You must edit the source file for changes to be made to this file.
- *
- *
- * Date: Generated on Sat Apr 6 03:07:48 2013
- * MD5 Checksum d41d8cd98f00b204e9800998ecf8427e
- *
- * Compiled with: RDB Utility combo_header.pl
- * RDB Parser 3.0
- * unknown unknown
- * Perl Interpreter 5.008008
- * Operating System linux
- *
- * Revision History:
- *
- * $brcm_Log: $
- *
- ***************************************************************************/
-
-#ifndef BCHP_PCIE_0_INTR2_H__
-#define BCHP_PCIE_0_INTR2_H__
-
-/***************************************************************************
- *PCIE_0_INTR2 - PCI-E L2 Interrupt Controller Registers
- ***************************************************************************/
-#define BCHP_PCIE_0_INTR2_CPU_STATUS 0x07804300 /* CPU interrupt Status Register */
-#define BCHP_PCIE_0_INTR2_CPU_SET 0x07804304 /* CPU interrupt Set Register */
-#define BCHP_PCIE_0_INTR2_CPU_CLEAR 0x07804308 /* CPU interrupt Clear Register */
-#define BCHP_PCIE_0_INTR2_CPU_MASK_STATUS 0x0780430c /* CPU interrupt Mask Status Register */
-#define BCHP_PCIE_0_INTR2_CPU_MASK_SET 0x07804310 /* CPU interrupt Mask Set Register */
-#define BCHP_PCIE_0_INTR2_CPU_MASK_CLEAR 0x07804314 /* CPU interrupt Mask Clear Register */
-#define BCHP_PCIE_0_INTR2_PCI_STATUS 0x07804318 /* PCI interrupt Status Register */
-#define BCHP_PCIE_0_INTR2_PCI_SET 0x0780431c /* PCI interrupt Set Register */
-#define BCHP_PCIE_0_INTR2_PCI_CLEAR 0x07804320 /* PCI interrupt Clear Register */
-#define BCHP_PCIE_0_INTR2_PCI_MASK_STATUS 0x07804324 /* PCI interrupt Mask Status Register */
-#define BCHP_PCIE_0_INTR2_PCI_MASK_SET 0x07804328 /* PCI interrupt Mask Set Register */
-#define BCHP_PCIE_0_INTR2_PCI_MASK_CLEAR 0x0780432c /* PCI interrupt Mask Clear Register */
-
-/***************************************************************************
- *CPU_STATUS - CPU interrupt Status Register
- ***************************************************************************/
-/* PCIE_0_INTR2 :: CPU_STATUS :: MSI_INTR07 [31:31] */
-#define BCHP_PCIE_0_INTR2_CPU_STATUS_MSI_INTR07_MASK 0x80000000
-#define BCHP_PCIE_0_INTR2_CPU_STATUS_MSI_INTR07_SHIFT 31
-#define BCHP_PCIE_0_INTR2_CPU_STATUS_MSI_INTR07_DEFAULT 0x00000000
-
-/* PCIE_0_INTR2 :: CPU_STATUS :: MSI_INTR06 [30:30] */
-#define BCHP_PCIE_0_INTR2_CPU_STATUS_MSI_INTR06_MASK 0x40000000
-#define BCHP_PCIE_0_INTR2_CPU_STATUS_MSI_INTR06_SHIFT 30
-#define BCHP_PCIE_0_INTR2_CPU_STATUS_MSI_INTR06_DEFAULT 0x00000000
-
-/* PCIE_0_INTR2 :: CPU_STATUS :: MSI_INTR05 [29:29] */
-#define BCHP_PCIE_0_INTR2_CPU_STATUS_MSI_INTR05_MASK 0x20000000
-#define BCHP_PCIE_0_INTR2_CPU_STATUS_MSI_INTR05_SHIFT 29
-#define BCHP_PCIE_0_INTR2_CPU_STATUS_MSI_INTR05_DEFAULT 0x00000000
-
-/* PCIE_0_INTR2 :: CPU_STATUS :: MSI_INTR04 [28:28] */
-#define BCHP_PCIE_0_INTR2_CPU_STATUS_MSI_INTR04_MASK 0x10000000
-#define BCHP_PCIE_0_INTR2_CPU_STATUS_MSI_INTR04_SHIFT 28
-#define BCHP_PCIE_0_INTR2_CPU_STATUS_MSI_INTR04_DEFAULT 0x00000000
-
-/* PCIE_0_INTR2 :: CPU_STATUS :: MSI_INTR03 [27:27] */
-#define BCHP_PCIE_0_INTR2_CPU_STATUS_MSI_INTR03_MASK 0x08000000
-#define BCHP_PCIE_0_INTR2_CPU_STATUS_MSI_INTR03_SHIFT 27
-#define BCHP_PCIE_0_INTR2_CPU_STATUS_MSI_INTR03_DEFAULT 0x00000000
-
-/* PCIE_0_INTR2 :: CPU_STATUS :: MSI_INTR02 [26:26] */
-#define BCHP_PCIE_0_INTR2_CPU_STATUS_MSI_INTR02_MASK 0x04000000
-#define BCHP_PCIE_0_INTR2_CPU_STATUS_MSI_INTR02_SHIFT 26
-#define BCHP_PCIE_0_INTR2_CPU_STATUS_MSI_INTR02_DEFAULT 0x00000000
-
-/* PCIE_0_INTR2 :: CPU_STATUS :: MSI_INTR01 [25:25] */
-#define BCHP_PCIE_0_INTR2_CPU_STATUS_MSI_INTR01_MASK 0x02000000
-#define BCHP_PCIE_0_INTR2_CPU_STATUS_MSI_INTR01_SHIFT 25
-#define BCHP_PCIE_0_INTR2_CPU_STATUS_MSI_INTR01_DEFAULT 0x00000000
-
-/* PCIE_0_INTR2 :: CPU_STATUS :: MSI_INTR00 [24:24] */
-#define BCHP_PCIE_0_INTR2_CPU_STATUS_MSI_INTR00_MASK 0x01000000
-#define BCHP_PCIE_0_INTR2_CPU_STATUS_MSI_INTR00_SHIFT 24
-#define BCHP_PCIE_0_INTR2_CPU_STATUS_MSI_INTR00_DEFAULT 0x00000000
-
-/* PCIE_0_INTR2 :: CPU_STATUS :: UNASSIGNED_23 [23:23] */
-#define BCHP_PCIE_0_INTR2_CPU_STATUS_UNASSIGNED_23_MASK 0x00800000
-#define BCHP_PCIE_0_INTR2_CPU_STATUS_UNASSIGNED_23_SHIFT 23
-#define BCHP_PCIE_0_INTR2_CPU_STATUS_UNASSIGNED_23_DEFAULT 0x00000000
-
-/* PCIE_0_INTR2 :: CPU_STATUS :: UNASSIGNED_22 [22:22] */
-#define BCHP_PCIE_0_INTR2_CPU_STATUS_UNASSIGNED_22_MASK 0x00400000
-#define BCHP_PCIE_0_INTR2_CPU_STATUS_UNASSIGNED_22_SHIFT 22
-#define BCHP_PCIE_0_INTR2_CPU_STATUS_UNASSIGNED_22_DEFAULT 0x00000000
-
-/* PCIE_0_INTR2 :: CPU_STATUS :: UNASSIGNED_21 [21:21] */
-#define BCHP_PCIE_0_INTR2_CPU_STATUS_UNASSIGNED_21_MASK 0x00200000
-#define BCHP_PCIE_0_INTR2_CPU_STATUS_UNASSIGNED_21_SHIFT 21
-#define BCHP_PCIE_0_INTR2_CPU_STATUS_UNASSIGNED_21_DEFAULT 0x00000000
-
-/* PCIE_0_INTR2 :: CPU_STATUS :: UNASSIGNED_20 [20:20] */
-#define BCHP_PCIE_0_INTR2_CPU_STATUS_UNASSIGNED_20_MASK 0x00100000
-#define BCHP_PCIE_0_INTR2_CPU_STATUS_UNASSIGNED_20_SHIFT 20
-#define BCHP_PCIE_0_INTR2_CPU_STATUS_UNASSIGNED_20_DEFAULT 0x00000000
-
-/* PCIE_0_INTR2 :: CPU_STATUS :: MAILBOX_3 [19:19] */
-#define BCHP_PCIE_0_INTR2_CPU_STATUS_MAILBOX_3_MASK 0x00080000
-#define BCHP_PCIE_0_INTR2_CPU_STATUS_MAILBOX_3_SHIFT 19
-#define BCHP_PCIE_0_INTR2_CPU_STATUS_MAILBOX_3_DEFAULT 0x00000000
-
-/* PCIE_0_INTR2 :: CPU_STATUS :: MAILBOX_2 [18:18] */
-#define BCHP_PCIE_0_INTR2_CPU_STATUS_MAILBOX_2_MASK 0x00040000
-#define BCHP_PCIE_0_INTR2_CPU_STATUS_MAILBOX_2_SHIFT 18
-#define BCHP_PCIE_0_INTR2_CPU_STATUS_MAILBOX_2_DEFAULT 0x00000000
-
-/* PCIE_0_INTR2 :: CPU_STATUS :: MAILBOX_1 [17:17] */
-#define BCHP_PCIE_0_INTR2_CPU_STATUS_MAILBOX_1_MASK 0x00020000
-#define BCHP_PCIE_0_INTR2_CPU_STATUS_MAILBOX_1_SHIFT 17
-#define BCHP_PCIE_0_INTR2_CPU_STATUS_MAILBOX_1_DEFAULT 0x00000000
-
-/* PCIE_0_INTR2 :: CPU_STATUS :: MAILBOX_0 [16:16] */
-#define BCHP_PCIE_0_INTR2_CPU_STATUS_MAILBOX_0_MASK 0x00010000
-#define BCHP_PCIE_0_INTR2_CPU_STATUS_MAILBOX_0_SHIFT 16
-#define BCHP_PCIE_0_INTR2_CPU_STATUS_MAILBOX_0_DEFAULT 0x00000000
-
-/* PCIE_0_INTR2 :: CPU_STATUS :: PCIE_MSTR_FWD_ERR [15:15] */
-#define BCHP_PCIE_0_INTR2_CPU_STATUS_PCIE_MSTR_FWD_ERR_MASK 0x00008000
-#define BCHP_PCIE_0_INTR2_CPU_STATUS_PCIE_MSTR_FWD_ERR_SHIFT 15
-#define BCHP_PCIE_0_INTR2_CPU_STATUS_PCIE_MSTR_FWD_ERR_DEFAULT 0x00000000
-
-/* PCIE_0_INTR2 :: CPU_STATUS :: PCIE_MSTR_RETRY_TIMEOUT [14:14] */
-#define BCHP_PCIE_0_INTR2_CPU_STATUS_PCIE_MSTR_RETRY_TIMEOUT_MASK 0x00004000
-#define BCHP_PCIE_0_INTR2_CPU_STATUS_PCIE_MSTR_RETRY_TIMEOUT_SHIFT 14
-#define BCHP_PCIE_0_INTR2_CPU_STATUS_PCIE_MSTR_RETRY_TIMEOUT_DEFAULT 0x00000000
-
-/* PCIE_0_INTR2 :: CPU_STATUS :: PCIE_MSTR_CA_ATTN [13:13] */
-#define BCHP_PCIE_0_INTR2_CPU_STATUS_PCIE_MSTR_CA_ATTN_MASK 0x00002000
-#define BCHP_PCIE_0_INTR2_CPU_STATUS_PCIE_MSTR_CA_ATTN_SHIFT 13
-#define BCHP_PCIE_0_INTR2_CPU_STATUS_PCIE_MSTR_CA_ATTN_DEFAULT 0x00000000
-
-/* PCIE_0_INTR2 :: CPU_STATUS :: PCIE_MSTR_UR_ATTN [12:12] */
-#define BCHP_PCIE_0_INTR2_CPU_STATUS_PCIE_MSTR_UR_ATTN_MASK 0x00001000
-#define BCHP_PCIE_0_INTR2_CPU_STATUS_PCIE_MSTR_UR_ATTN_SHIFT 12
-#define BCHP_PCIE_0_INTR2_CPU_STATUS_PCIE_MSTR_UR_ATTN_DEFAULT 0x00000000
-
-/* PCIE_0_INTR2 :: CPU_STATUS :: UNASSIGNED_11 [11:11] */
-#define BCHP_PCIE_0_INTR2_CPU_STATUS_UNASSIGNED_11_MASK 0x00000800
-#define BCHP_PCIE_0_INTR2_CPU_STATUS_UNASSIGNED_11_SHIFT 11
-#define BCHP_PCIE_0_INTR2_CPU_STATUS_UNASSIGNED_11_DEFAULT 0x00000000
-
-/* PCIE_0_INTR2 :: CPU_STATUS :: UNASSIGNED_10 [10:10] */
-#define BCHP_PCIE_0_INTR2_CPU_STATUS_UNASSIGNED_10_MASK 0x00000400
-#define BCHP_PCIE_0_INTR2_CPU_STATUS_UNASSIGNED_10_SHIFT 10
-#define BCHP_PCIE_0_INTR2_CPU_STATUS_UNASSIGNED_10_DEFAULT 0x00000000
-
-/* PCIE_0_INTR2 :: CPU_STATUS :: PCIE_TGT_BAD_ACCESS [09:09] */
-#define BCHP_PCIE_0_INTR2_CPU_STATUS_PCIE_TGT_BAD_ACCESS_MASK 0x00000200
-#define BCHP_PCIE_0_INTR2_CPU_STATUS_PCIE_TGT_BAD_ACCESS_SHIFT 9
-#define BCHP_PCIE_0_INTR2_CPU_STATUS_PCIE_TGT_BAD_ACCESS_DEFAULT 0x00000000
-
-/* PCIE_0_INTR2 :: CPU_STATUS :: PCIE_TGT_BAD_ADDRESS [08:08] */
-#define BCHP_PCIE_0_INTR2_CPU_STATUS_PCIE_TGT_BAD_ADDRESS_MASK 0x00000100
-#define BCHP_PCIE_0_INTR2_CPU_STATUS_PCIE_TGT_BAD_ADDRESS_SHIFT 8
-#define BCHP_PCIE_0_INTR2_CPU_STATUS_PCIE_TGT_BAD_ADDRESS_DEFAULT 0x00000000
-
-/* PCIE_0_INTR2 :: CPU_STATUS :: L1_RX_DMA_ERR_INTR [07:07] */
-#define BCHP_PCIE_0_INTR2_CPU_STATUS_L1_RX_DMA_ERR_INTR_MASK 0x00000080
-#define BCHP_PCIE_0_INTR2_CPU_STATUS_L1_RX_DMA_ERR_INTR_SHIFT 7
-#define BCHP_PCIE_0_INTR2_CPU_STATUS_L1_RX_DMA_ERR_INTR_DEFAULT 0x00000000
-
-/* PCIE_0_INTR2 :: CPU_STATUS :: L1_RX_DMA_DONE_INTR [06:06] */
-#define BCHP_PCIE_0_INTR2_CPU_STATUS_L1_RX_DMA_DONE_INTR_MASK 0x00000040
-#define BCHP_PCIE_0_INTR2_CPU_STATUS_L1_RX_DMA_DONE_INTR_SHIFT 6
-#define BCHP_PCIE_0_INTR2_CPU_STATUS_L1_RX_DMA_DONE_INTR_DEFAULT 0x00000000
-
-/* PCIE_0_INTR2 :: CPU_STATUS :: L1_TX_DMA_ERR_INTR [05:05] */
-#define BCHP_PCIE_0_INTR2_CPU_STATUS_L1_TX_DMA_ERR_INTR_MASK 0x00000020
-#define BCHP_PCIE_0_INTR2_CPU_STATUS_L1_TX_DMA_ERR_INTR_SHIFT 5
-#define BCHP_PCIE_0_INTR2_CPU_STATUS_L1_TX_DMA_ERR_INTR_DEFAULT 0x00000000
-
-/* PCIE_0_INTR2 :: CPU_STATUS :: L1_TX_DMA_DONE_INTR [04:04] */
-#define BCHP_PCIE_0_INTR2_CPU_STATUS_L1_TX_DMA_DONE_INTR_MASK 0x00000010
-#define BCHP_PCIE_0_INTR2_CPU_STATUS_L1_TX_DMA_DONE_INTR_SHIFT 4
-#define BCHP_PCIE_0_INTR2_CPU_STATUS_L1_TX_DMA_DONE_INTR_DEFAULT 0x00000000
-
-/* PCIE_0_INTR2 :: CPU_STATUS :: L0_RX_DMA_ERR_INTR [03:03] */
-#define BCHP_PCIE_0_INTR2_CPU_STATUS_L0_RX_DMA_ERR_INTR_MASK 0x00000008
-#define BCHP_PCIE_0_INTR2_CPU_STATUS_L0_RX_DMA_ERR_INTR_SHIFT 3
-#define BCHP_PCIE_0_INTR2_CPU_STATUS_L0_RX_DMA_ERR_INTR_DEFAULT 0x00000000
-
-/* PCIE_0_INTR2 :: CPU_STATUS :: L0_RX_DMA_DONE_INTR [02:02] */
-#define BCHP_PCIE_0_INTR2_CPU_STATUS_L0_RX_DMA_DONE_INTR_MASK 0x00000004
-#define BCHP_PCIE_0_INTR2_CPU_STATUS_L0_RX_DMA_DONE_INTR_SHIFT 2
-#define BCHP_PCIE_0_INTR2_CPU_STATUS_L0_RX_DMA_DONE_INTR_DEFAULT 0x00000000
-
-/* PCIE_0_INTR2 :: CPU_STATUS :: L0_TX_DMA_ERR_INTR [01:01] */
-#define BCHP_PCIE_0_INTR2_CPU_STATUS_L0_TX_DMA_ERR_INTR_MASK 0x00000002
-#define BCHP_PCIE_0_INTR2_CPU_STATUS_L0_TX_DMA_ERR_INTR_SHIFT 1
-#define BCHP_PCIE_0_INTR2_CPU_STATUS_L0_TX_DMA_ERR_INTR_DEFAULT 0x00000000
-
-/* PCIE_0_INTR2 :: CPU_STATUS :: L0_TX_DMA_DONE_INTR [00:00] */
-#define BCHP_PCIE_0_INTR2_CPU_STATUS_L0_TX_DMA_DONE_INTR_MASK 0x00000001
-#define BCHP_PCIE_0_INTR2_CPU_STATUS_L0_TX_DMA_DONE_INTR_SHIFT 0
-#define BCHP_PCIE_0_INTR2_CPU_STATUS_L0_TX_DMA_DONE_INTR_DEFAULT 0x00000000
-
-/***************************************************************************
- *CPU_SET - CPU interrupt Set Register
- ***************************************************************************/
-/* PCIE_0_INTR2 :: CPU_SET :: MSI_INTR07 [31:31] */
-#define BCHP_PCIE_0_INTR2_CPU_SET_MSI_INTR07_MASK 0x80000000
-#define BCHP_PCIE_0_INTR2_CPU_SET_MSI_INTR07_SHIFT 31
-#define BCHP_PCIE_0_INTR2_CPU_SET_MSI_INTR07_DEFAULT 0x00000000
-
-/* PCIE_0_INTR2 :: CPU_SET :: MSI_INTR06 [30:30] */
-#define BCHP_PCIE_0_INTR2_CPU_SET_MSI_INTR06_MASK 0x40000000
-#define BCHP_PCIE_0_INTR2_CPU_SET_MSI_INTR06_SHIFT 30
-#define BCHP_PCIE_0_INTR2_CPU_SET_MSI_INTR06_DEFAULT 0x00000000
-
-/* PCIE_0_INTR2 :: CPU_SET :: MSI_INTR05 [29:29] */
-#define BCHP_PCIE_0_INTR2_CPU_SET_MSI_INTR05_MASK 0x20000000
-#define BCHP_PCIE_0_INTR2_CPU_SET_MSI_INTR05_SHIFT 29
-#define BCHP_PCIE_0_INTR2_CPU_SET_MSI_INTR05_DEFAULT 0x00000000
-
-/* PCIE_0_INTR2 :: CPU_SET :: MSI_INTR04 [28:28] */
-#define BCHP_PCIE_0_INTR2_CPU_SET_MSI_INTR04_MASK 0x10000000
-#define BCHP_PCIE_0_INTR2_CPU_SET_MSI_INTR04_SHIFT 28
-#define BCHP_PCIE_0_INTR2_CPU_SET_MSI_INTR04_DEFAULT 0x00000000
-
-/* PCIE_0_INTR2 :: CPU_SET :: MSI_INTR03 [27:27] */
-#define BCHP_PCIE_0_INTR2_CPU_SET_MSI_INTR03_MASK 0x08000000
-#define BCHP_PCIE_0_INTR2_CPU_SET_MSI_INTR03_SHIFT 27
-#define BCHP_PCIE_0_INTR2_CPU_SET_MSI_INTR03_DEFAULT 0x00000000
-
-/* PCIE_0_INTR2 :: CPU_SET :: MSI_INTR02 [26:26] */
-#define BCHP_PCIE_0_INTR2_CPU_SET_MSI_INTR02_MASK 0x04000000
-#define BCHP_PCIE_0_INTR2_CPU_SET_MSI_INTR02_SHIFT 26
-#define BCHP_PCIE_0_INTR2_CPU_SET_MSI_INTR02_DEFAULT 0x00000000
-
-/* PCIE_0_INTR2 :: CPU_SET :: MSI_INTR01 [25:25] */
-#define BCHP_PCIE_0_INTR2_CPU_SET_MSI_INTR01_MASK 0x02000000
-#define BCHP_PCIE_0_INTR2_CPU_SET_MSI_INTR01_SHIFT 25
-#define BCHP_PCIE_0_INTR2_CPU_SET_MSI_INTR01_DEFAULT 0x00000000
-
-/* PCIE_0_INTR2 :: CPU_SET :: MSI_INTR00 [24:24] */
-#define BCHP_PCIE_0_INTR2_CPU_SET_MSI_INTR00_MASK 0x01000000
-#define BCHP_PCIE_0_INTR2_CPU_SET_MSI_INTR00_SHIFT 24
-#define BCHP_PCIE_0_INTR2_CPU_SET_MSI_INTR00_DEFAULT 0x00000000
-
-/* PCIE_0_INTR2 :: CPU_SET :: UNASSIGNED_23 [23:23] */
-#define BCHP_PCIE_0_INTR2_CPU_SET_UNASSIGNED_23_MASK 0x00800000
-#define BCHP_PCIE_0_INTR2_CPU_SET_UNASSIGNED_23_SHIFT 23
-#define BCHP_PCIE_0_INTR2_CPU_SET_UNASSIGNED_23_DEFAULT 0x00000000
-
-/* PCIE_0_INTR2 :: CPU_SET :: UNASSIGNED_22 [22:22] */
-#define BCHP_PCIE_0_INTR2_CPU_SET_UNASSIGNED_22_MASK 0x00400000
-#define BCHP_PCIE_0_INTR2_CPU_SET_UNASSIGNED_22_SHIFT 22
-#define BCHP_PCIE_0_INTR2_CPU_SET_UNASSIGNED_22_DEFAULT 0x00000000
-
-/* PCIE_0_INTR2 :: CPU_SET :: UNASSIGNED_21 [21:21] */
-#define BCHP_PCIE_0_INTR2_CPU_SET_UNASSIGNED_21_MASK 0x00200000
-#define BCHP_PCIE_0_INTR2_CPU_SET_UNASSIGNED_21_SHIFT 21
-#define BCHP_PCIE_0_INTR2_CPU_SET_UNASSIGNED_21_DEFAULT 0x00000000
-
-/* PCIE_0_INTR2 :: CPU_SET :: UNASSIGNED_20 [20:20] */
-#define BCHP_PCIE_0_INTR2_CPU_SET_UNASSIGNED_20_MASK 0x00100000
-#define BCHP_PCIE_0_INTR2_CPU_SET_UNASSIGNED_20_SHIFT 20
-#define BCHP_PCIE_0_INTR2_CPU_SET_UNASSIGNED_20_DEFAULT 0x00000000
-
-/* PCIE_0_INTR2 :: CPU_SET :: MAILBOX_3 [19:19] */
-#define BCHP_PCIE_0_INTR2_CPU_SET_MAILBOX_3_MASK 0x00080000
-#define BCHP_PCIE_0_INTR2_CPU_SET_MAILBOX_3_SHIFT 19
-#define BCHP_PCIE_0_INTR2_CPU_SET_MAILBOX_3_DEFAULT 0x00000000
-
-/* PCIE_0_INTR2 :: CPU_SET :: MAILBOX_2 [18:18] */
-#define BCHP_PCIE_0_INTR2_CPU_SET_MAILBOX_2_MASK 0x00040000
-#define BCHP_PCIE_0_INTR2_CPU_SET_MAILBOX_2_SHIFT 18
-#define BCHP_PCIE_0_INTR2_CPU_SET_MAILBOX_2_DEFAULT 0x00000000
-
-/* PCIE_0_INTR2 :: CPU_SET :: MAILBOX_1 [17:17] */
-#define BCHP_PCIE_0_INTR2_CPU_SET_MAILBOX_1_MASK 0x00020000
-#define BCHP_PCIE_0_INTR2_CPU_SET_MAILBOX_1_SHIFT 17
-#define BCHP_PCIE_0_INTR2_CPU_SET_MAILBOX_1_DEFAULT 0x00000000
-
-/* PCIE_0_INTR2 :: CPU_SET :: MAILBOX_0 [16:16] */
-#define BCHP_PCIE_0_INTR2_CPU_SET_MAILBOX_0_MASK 0x00010000
-#define BCHP_PCIE_0_INTR2_CPU_SET_MAILBOX_0_SHIFT 16
-#define BCHP_PCIE_0_INTR2_CPU_SET_MAILBOX_0_DEFAULT 0x00000000
-
-/* PCIE_0_INTR2 :: CPU_SET :: PCIE_MSTR_FWD_ERR [15:15] */
-#define BCHP_PCIE_0_INTR2_CPU_SET_PCIE_MSTR_FWD_ERR_MASK 0x00008000
-#define BCHP_PCIE_0_INTR2_CPU_SET_PCIE_MSTR_FWD_ERR_SHIFT 15
-#define BCHP_PCIE_0_INTR2_CPU_SET_PCIE_MSTR_FWD_ERR_DEFAULT 0x00000000
-
-/* PCIE_0_INTR2 :: CPU_SET :: PCIE_MSTR_RETRY_TIMEOUT [14:14] */
-#define BCHP_PCIE_0_INTR2_CPU_SET_PCIE_MSTR_RETRY_TIMEOUT_MASK 0x00004000
-#define BCHP_PCIE_0_INTR2_CPU_SET_PCIE_MSTR_RETRY_TIMEOUT_SHIFT 14
-#define BCHP_PCIE_0_INTR2_CPU_SET_PCIE_MSTR_RETRY_TIMEOUT_DEFAULT 0x00000000
-
-/* PCIE_0_INTR2 :: CPU_SET :: PCIE_MSTR_CA_ATTN [13:13] */
-#define BCHP_PCIE_0_INTR2_CPU_SET_PCIE_MSTR_CA_ATTN_MASK 0x00002000
-#define BCHP_PCIE_0_INTR2_CPU_SET_PCIE_MSTR_CA_ATTN_SHIFT 13
-#define BCHP_PCIE_0_INTR2_CPU_SET_PCIE_MSTR_CA_ATTN_DEFAULT 0x00000000
-
-/* PCIE_0_INTR2 :: CPU_SET :: PCIE_MSTR_UR_ATTN [12:12] */
-#define BCHP_PCIE_0_INTR2_CPU_SET_PCIE_MSTR_UR_ATTN_MASK 0x00001000
-#define BCHP_PCIE_0_INTR2_CPU_SET_PCIE_MSTR_UR_ATTN_SHIFT 12
-#define BCHP_PCIE_0_INTR2_CPU_SET_PCIE_MSTR_UR_ATTN_DEFAULT 0x00000000
-
-/* PCIE_0_INTR2 :: CPU_SET :: UNASSIGNED_11 [11:11] */
-#define BCHP_PCIE_0_INTR2_CPU_SET_UNASSIGNED_11_MASK 0x00000800
-#define BCHP_PCIE_0_INTR2_CPU_SET_UNASSIGNED_11_SHIFT 11
-#define BCHP_PCIE_0_INTR2_CPU_SET_UNASSIGNED_11_DEFAULT 0x00000000
-
-/* PCIE_0_INTR2 :: CPU_SET :: UNASSIGNED_10 [10:10] */
-#define BCHP_PCIE_0_INTR2_CPU_SET_UNASSIGNED_10_MASK 0x00000400
-#define BCHP_PCIE_0_INTR2_CPU_SET_UNASSIGNED_10_SHIFT 10
-#define BCHP_PCIE_0_INTR2_CPU_SET_UNASSIGNED_10_DEFAULT 0x00000000
-
-/* PCIE_0_INTR2 :: CPU_SET :: PCIE_TGT_BAD_ACCESS [09:09] */
-#define BCHP_PCIE_0_INTR2_CPU_SET_PCIE_TGT_BAD_ACCESS_MASK 0x00000200
-#define BCHP_PCIE_0_INTR2_CPU_SET_PCIE_TGT_BAD_ACCESS_SHIFT 9
-#define BCHP_PCIE_0_INTR2_CPU_SET_PCIE_TGT_BAD_ACCESS_DEFAULT 0x00000000
-
-/* PCIE_0_INTR2 :: CPU_SET :: PCIE_TGT_BAD_ADDRESS [08:08] */
-#define BCHP_PCIE_0_INTR2_CPU_SET_PCIE_TGT_BAD_ADDRESS_MASK 0x00000100
-#define BCHP_PCIE_0_INTR2_CPU_SET_PCIE_TGT_BAD_ADDRESS_SHIFT 8
-#define BCHP_PCIE_0_INTR2_CPU_SET_PCIE_TGT_BAD_ADDRESS_DEFAULT 0x00000000
-
-/* PCIE_0_INTR2 :: CPU_SET :: L1_RX_DMA_ERR_INTR [07:07] */
-#define BCHP_PCIE_0_INTR2_CPU_SET_L1_RX_DMA_ERR_INTR_MASK 0x00000080
-#define BCHP_PCIE_0_INTR2_CPU_SET_L1_RX_DMA_ERR_INTR_SHIFT 7
-#define BCHP_PCIE_0_INTR2_CPU_SET_L1_RX_DMA_ERR_INTR_DEFAULT 0x00000000
-
-/* PCIE_0_INTR2 :: CPU_SET :: L1_RX_DMA_DONE_INTR [06:06] */
-#define BCHP_PCIE_0_INTR2_CPU_SET_L1_RX_DMA_DONE_INTR_MASK 0x00000040
-#define BCHP_PCIE_0_INTR2_CPU_SET_L1_RX_DMA_DONE_INTR_SHIFT 6
-#define BCHP_PCIE_0_INTR2_CPU_SET_L1_RX_DMA_DONE_INTR_DEFAULT 0x00000000
-
-/* PCIE_0_INTR2 :: CPU_SET :: L1_TX_DMA_ERR_INTR [05:05] */
-#define BCHP_PCIE_0_INTR2_CPU_SET_L1_TX_DMA_ERR_INTR_MASK 0x00000020
-#define BCHP_PCIE_0_INTR2_CPU_SET_L1_TX_DMA_ERR_INTR_SHIFT 5
-#define BCHP_PCIE_0_INTR2_CPU_SET_L1_TX_DMA_ERR_INTR_DEFAULT 0x00000000
-
-/* PCIE_0_INTR2 :: CPU_SET :: L1_TX_DMA_DONE_INTR [04:04] */
-#define BCHP_PCIE_0_INTR2_CPU_SET_L1_TX_DMA_DONE_INTR_MASK 0x00000010
-#define BCHP_PCIE_0_INTR2_CPU_SET_L1_TX_DMA_DONE_INTR_SHIFT 4
-#define BCHP_PCIE_0_INTR2_CPU_SET_L1_TX_DMA_DONE_INTR_DEFAULT 0x00000000
-
-/* PCIE_0_INTR2 :: CPU_SET :: L0_RX_DMA_ERR_INTR [03:03] */
-#define BCHP_PCIE_0_INTR2_CPU_SET_L0_RX_DMA_ERR_INTR_MASK 0x00000008
-#define BCHP_PCIE_0_INTR2_CPU_SET_L0_RX_DMA_ERR_INTR_SHIFT 3
-#define BCHP_PCIE_0_INTR2_CPU_SET_L0_RX_DMA_ERR_INTR_DEFAULT 0x00000000
-
-/* PCIE_0_INTR2 :: CPU_SET :: L0_RX_DMA_DONE_INTR [02:02] */
-#define BCHP_PCIE_0_INTR2_CPU_SET_L0_RX_DMA_DONE_INTR_MASK 0x00000004
-#define BCHP_PCIE_0_INTR2_CPU_SET_L0_RX_DMA_DONE_INTR_SHIFT 2
-#define BCHP_PCIE_0_INTR2_CPU_SET_L0_RX_DMA_DONE_INTR_DEFAULT 0x00000000
-
-/* PCIE_0_INTR2 :: CPU_SET :: L0_TX_DMA_ERR_INTR [01:01] */
-#define BCHP_PCIE_0_INTR2_CPU_SET_L0_TX_DMA_ERR_INTR_MASK 0x00000002
-#define BCHP_PCIE_0_INTR2_CPU_SET_L0_TX_DMA_ERR_INTR_SHIFT 1
-#define BCHP_PCIE_0_INTR2_CPU_SET_L0_TX_DMA_ERR_INTR_DEFAULT 0x00000000
-
-/* PCIE_0_INTR2 :: CPU_SET :: L0_TX_DMA_DONE_INTR [00:00] */
-#define BCHP_PCIE_0_INTR2_CPU_SET_L0_TX_DMA_DONE_INTR_MASK 0x00000001
-#define BCHP_PCIE_0_INTR2_CPU_SET_L0_TX_DMA_DONE_INTR_SHIFT 0
-#define BCHP_PCIE_0_INTR2_CPU_SET_L0_TX_DMA_DONE_INTR_DEFAULT 0x00000000
-
-/***************************************************************************
- *CPU_CLEAR - CPU interrupt Clear Register
- ***************************************************************************/
-/* PCIE_0_INTR2 :: CPU_CLEAR :: MSI_INTR07 [31:31] */
-#define BCHP_PCIE_0_INTR2_CPU_CLEAR_MSI_INTR07_MASK 0x80000000
-#define BCHP_PCIE_0_INTR2_CPU_CLEAR_MSI_INTR07_SHIFT 31
-#define BCHP_PCIE_0_INTR2_CPU_CLEAR_MSI_INTR07_DEFAULT 0x00000000
-
-/* PCIE_0_INTR2 :: CPU_CLEAR :: MSI_INTR06 [30:30] */
-#define BCHP_PCIE_0_INTR2_CPU_CLEAR_MSI_INTR06_MASK 0x40000000
-#define BCHP_PCIE_0_INTR2_CPU_CLEAR_MSI_INTR06_SHIFT 30
-#define BCHP_PCIE_0_INTR2_CPU_CLEAR_MSI_INTR06_DEFAULT 0x00000000
-
-/* PCIE_0_INTR2 :: CPU_CLEAR :: MSI_INTR05 [29:29] */
-#define BCHP_PCIE_0_INTR2_CPU_CLEAR_MSI_INTR05_MASK 0x20000000
-#define BCHP_PCIE_0_INTR2_CPU_CLEAR_MSI_INTR05_SHIFT 29
-#define BCHP_PCIE_0_INTR2_CPU_CLEAR_MSI_INTR05_DEFAULT 0x00000000
-
-/* PCIE_0_INTR2 :: CPU_CLEAR :: MSI_INTR04 [28:28] */
-#define BCHP_PCIE_0_INTR2_CPU_CLEAR_MSI_INTR04_MASK 0x10000000
-#define BCHP_PCIE_0_INTR2_CPU_CLEAR_MSI_INTR04_SHIFT 28
-#define BCHP_PCIE_0_INTR2_CPU_CLEAR_MSI_INTR04_DEFAULT 0x00000000
-
-/* PCIE_0_INTR2 :: CPU_CLEAR :: MSI_INTR03 [27:27] */
-#define BCHP_PCIE_0_INTR2_CPU_CLEAR_MSI_INTR03_MASK 0x08000000
-#define BCHP_PCIE_0_INTR2_CPU_CLEAR_MSI_INTR03_SHIFT 27
-#define BCHP_PCIE_0_INTR2_CPU_CLEAR_MSI_INTR03_DEFAULT 0x00000000
-
-/* PCIE_0_INTR2 :: CPU_CLEAR :: MSI_INTR02 [26:26] */
-#define BCHP_PCIE_0_INTR2_CPU_CLEAR_MSI_INTR02_MASK 0x04000000
-#define BCHP_PCIE_0_INTR2_CPU_CLEAR_MSI_INTR02_SHIFT 26
-#define BCHP_PCIE_0_INTR2_CPU_CLEAR_MSI_INTR02_DEFAULT 0x00000000
-
-/* PCIE_0_INTR2 :: CPU_CLEAR :: MSI_INTR01 [25:25] */
-#define BCHP_PCIE_0_INTR2_CPU_CLEAR_MSI_INTR01_MASK 0x02000000
-#define BCHP_PCIE_0_INTR2_CPU_CLEAR_MSI_INTR01_SHIFT 25
-#define BCHP_PCIE_0_INTR2_CPU_CLEAR_MSI_INTR01_DEFAULT 0x00000000
-
-/* PCIE_0_INTR2 :: CPU_CLEAR :: MSI_INTR00 [24:24] */
-#define BCHP_PCIE_0_INTR2_CPU_CLEAR_MSI_INTR00_MASK 0x01000000
-#define BCHP_PCIE_0_INTR2_CPU_CLEAR_MSI_INTR00_SHIFT 24
-#define BCHP_PCIE_0_INTR2_CPU_CLEAR_MSI_INTR00_DEFAULT 0x00000000
-
-/* PCIE_0_INTR2 :: CPU_CLEAR :: UNASSIGNED_23 [23:23] */
-#define BCHP_PCIE_0_INTR2_CPU_CLEAR_UNASSIGNED_23_MASK 0x00800000
-#define BCHP_PCIE_0_INTR2_CPU_CLEAR_UNASSIGNED_23_SHIFT 23
-#define BCHP_PCIE_0_INTR2_CPU_CLEAR_UNASSIGNED_23_DEFAULT 0x00000000
-
-/* PCIE_0_INTR2 :: CPU_CLEAR :: UNASSIGNED_22 [22:22] */
-#define BCHP_PCIE_0_INTR2_CPU_CLEAR_UNASSIGNED_22_MASK 0x00400000
-#define BCHP_PCIE_0_INTR2_CPU_CLEAR_UNASSIGNED_22_SHIFT 22
-#define BCHP_PCIE_0_INTR2_CPU_CLEAR_UNASSIGNED_22_DEFAULT 0x00000000
-
-/* PCIE_0_INTR2 :: CPU_CLEAR :: UNASSIGNED_21 [21:21] */
-#define BCHP_PCIE_0_INTR2_CPU_CLEAR_UNASSIGNED_21_MASK 0x00200000
-#define BCHP_PCIE_0_INTR2_CPU_CLEAR_UNASSIGNED_21_SHIFT 21
-#define BCHP_PCIE_0_INTR2_CPU_CLEAR_UNASSIGNED_21_DEFAULT 0x00000000
-
-/* PCIE_0_INTR2 :: CPU_CLEAR :: UNASSIGNED_20 [20:20] */
-#define BCHP_PCIE_0_INTR2_CPU_CLEAR_UNASSIGNED_20_MASK 0x00100000
-#define BCHP_PCIE_0_INTR2_CPU_CLEAR_UNASSIGNED_20_SHIFT 20
-#define BCHP_PCIE_0_INTR2_CPU_CLEAR_UNASSIGNED_20_DEFAULT 0x00000000
-
-/* PCIE_0_INTR2 :: CPU_CLEAR :: MAILBOX_3 [19:19] */
-#define BCHP_PCIE_0_INTR2_CPU_CLEAR_MAILBOX_3_MASK 0x00080000
-#define BCHP_PCIE_0_INTR2_CPU_CLEAR_MAILBOX_3_SHIFT 19
-#define BCHP_PCIE_0_INTR2_CPU_CLEAR_MAILBOX_3_DEFAULT 0x00000000
-
-/* PCIE_0_INTR2 :: CPU_CLEAR :: MAILBOX_2 [18:18] */
-#define BCHP_PCIE_0_INTR2_CPU_CLEAR_MAILBOX_2_MASK 0x00040000
-#define BCHP_PCIE_0_INTR2_CPU_CLEAR_MAILBOX_2_SHIFT 18
-#define BCHP_PCIE_0_INTR2_CPU_CLEAR_MAILBOX_2_DEFAULT 0x00000000
-
-/* PCIE_0_INTR2 :: CPU_CLEAR :: MAILBOX_1 [17:17] */
-#define BCHP_PCIE_0_INTR2_CPU_CLEAR_MAILBOX_1_MASK 0x00020000
-#define BCHP_PCIE_0_INTR2_CPU_CLEAR_MAILBOX_1_SHIFT 17
-#define BCHP_PCIE_0_INTR2_CPU_CLEAR_MAILBOX_1_DEFAULT 0x00000000
-
-/* PCIE_0_INTR2 :: CPU_CLEAR :: MAILBOX_0 [16:16] */
-#define BCHP_PCIE_0_INTR2_CPU_CLEAR_MAILBOX_0_MASK 0x00010000
-#define BCHP_PCIE_0_INTR2_CPU_CLEAR_MAILBOX_0_SHIFT 16
-#define BCHP_PCIE_0_INTR2_CPU_CLEAR_MAILBOX_0_DEFAULT 0x00000000
-
-/* PCIE_0_INTR2 :: CPU_CLEAR :: PCIE_MSTR_FWD_ERR [15:15] */
-#define BCHP_PCIE_0_INTR2_CPU_CLEAR_PCIE_MSTR_FWD_ERR_MASK 0x00008000
-#define BCHP_PCIE_0_INTR2_CPU_CLEAR_PCIE_MSTR_FWD_ERR_SHIFT 15
-#define BCHP_PCIE_0_INTR2_CPU_CLEAR_PCIE_MSTR_FWD_ERR_DEFAULT 0x00000000
-
-/* PCIE_0_INTR2 :: CPU_CLEAR :: PCIE_MSTR_RETRY_TIMEOUT [14:14] */
-#define BCHP_PCIE_0_INTR2_CPU_CLEAR_PCIE_MSTR_RETRY_TIMEOUT_MASK 0x00004000
-#define BCHP_PCIE_0_INTR2_CPU_CLEAR_PCIE_MSTR_RETRY_TIMEOUT_SHIFT 14
-#define BCHP_PCIE_0_INTR2_CPU_CLEAR_PCIE_MSTR_RETRY_TIMEOUT_DEFAULT 0x00000000
-
-/* PCIE_0_INTR2 :: CPU_CLEAR :: PCIE_MSTR_CA_ATTN [13:13] */
-#define BCHP_PCIE_0_INTR2_CPU_CLEAR_PCIE_MSTR_CA_ATTN_MASK 0x00002000
-#define BCHP_PCIE_0_INTR2_CPU_CLEAR_PCIE_MSTR_CA_ATTN_SHIFT 13
-#define BCHP_PCIE_0_INTR2_CPU_CLEAR_PCIE_MSTR_CA_ATTN_DEFAULT 0x00000000
-
-/* PCIE_0_INTR2 :: CPU_CLEAR :: PCIE_MSTR_UR_ATTN [12:12] */
-#define BCHP_PCIE_0_INTR2_CPU_CLEAR_PCIE_MSTR_UR_ATTN_MASK 0x00001000
-#define BCHP_PCIE_0_INTR2_CPU_CLEAR_PCIE_MSTR_UR_ATTN_SHIFT 12
-#define BCHP_PCIE_0_INTR2_CPU_CLEAR_PCIE_MSTR_UR_ATTN_DEFAULT 0x00000000
-
-/* PCIE_0_INTR2 :: CPU_CLEAR :: UNASSIGNED_11 [11:11] */
-#define BCHP_PCIE_0_INTR2_CPU_CLEAR_UNASSIGNED_11_MASK 0x00000800
-#define BCHP_PCIE_0_INTR2_CPU_CLEAR_UNASSIGNED_11_SHIFT 11
-#define BCHP_PCIE_0_INTR2_CPU_CLEAR_UNASSIGNED_11_DEFAULT 0x00000000
-
-/* PCIE_0_INTR2 :: CPU_CLEAR :: UNASSIGNED_10 [10:10] */
-#define BCHP_PCIE_0_INTR2_CPU_CLEAR_UNASSIGNED_10_MASK 0x00000400
-#define BCHP_PCIE_0_INTR2_CPU_CLEAR_UNASSIGNED_10_SHIFT 10
-#define BCHP_PCIE_0_INTR2_CPU_CLEAR_UNASSIGNED_10_DEFAULT 0x00000000
-
-/* PCIE_0_INTR2 :: CPU_CLEAR :: PCIE_TGT_BAD_ACCESS [09:09] */
-#define BCHP_PCIE_0_INTR2_CPU_CLEAR_PCIE_TGT_BAD_ACCESS_MASK 0x00000200
-#define BCHP_PCIE_0_INTR2_CPU_CLEAR_PCIE_TGT_BAD_ACCESS_SHIFT 9
-#define BCHP_PCIE_0_INTR2_CPU_CLEAR_PCIE_TGT_BAD_ACCESS_DEFAULT 0x00000000
-
-/* PCIE_0_INTR2 :: CPU_CLEAR :: PCIE_TGT_BAD_ADDRESS [08:08] */
-#define BCHP_PCIE_0_INTR2_CPU_CLEAR_PCIE_TGT_BAD_ADDRESS_MASK 0x00000100
-#define BCHP_PCIE_0_INTR2_CPU_CLEAR_PCIE_TGT_BAD_ADDRESS_SHIFT 8
-#define BCHP_PCIE_0_INTR2_CPU_CLEAR_PCIE_TGT_BAD_ADDRESS_DEFAULT 0x00000000
-
-/* PCIE_0_INTR2 :: CPU_CLEAR :: L1_RX_DMA_ERR_INTR [07:07] */
-#define BCHP_PCIE_0_INTR2_CPU_CLEAR_L1_RX_DMA_ERR_INTR_MASK 0x00000080
-#define BCHP_PCIE_0_INTR2_CPU_CLEAR_L1_RX_DMA_ERR_INTR_SHIFT 7
-#define BCHP_PCIE_0_INTR2_CPU_CLEAR_L1_RX_DMA_ERR_INTR_DEFAULT 0x00000000
-
-/* PCIE_0_INTR2 :: CPU_CLEAR :: L1_RX_DMA_DONE_INTR [06:06] */
-#define BCHP_PCIE_0_INTR2_CPU_CLEAR_L1_RX_DMA_DONE_INTR_MASK 0x00000040
-#define BCHP_PCIE_0_INTR2_CPU_CLEAR_L1_RX_DMA_DONE_INTR_SHIFT 6
-#define BCHP_PCIE_0_INTR2_CPU_CLEAR_L1_RX_DMA_DONE_INTR_DEFAULT 0x00000000
-
-/* PCIE_0_INTR2 :: CPU_CLEAR :: L1_TX_DMA_ERR_INTR [05:05] */
-#define BCHP_PCIE_0_INTR2_CPU_CLEAR_L1_TX_DMA_ERR_INTR_MASK 0x00000020
-#define BCHP_PCIE_0_INTR2_CPU_CLEAR_L1_TX_DMA_ERR_INTR_SHIFT 5
-#define BCHP_PCIE_0_INTR2_CPU_CLEAR_L1_TX_DMA_ERR_INTR_DEFAULT 0x00000000
-
-/* PCIE_0_INTR2 :: CPU_CLEAR :: L1_TX_DMA_DONE_INTR [04:04] */
-#define BCHP_PCIE_0_INTR2_CPU_CLEAR_L1_TX_DMA_DONE_INTR_MASK 0x00000010
-#define BCHP_PCIE_0_INTR2_CPU_CLEAR_L1_TX_DMA_DONE_INTR_SHIFT 4
-#define BCHP_PCIE_0_INTR2_CPU_CLEAR_L1_TX_DMA_DONE_INTR_DEFAULT 0x00000000
-
-/* PCIE_0_INTR2 :: CPU_CLEAR :: L0_RX_DMA_ERR_INTR [03:03] */
-#define BCHP_PCIE_0_INTR2_CPU_CLEAR_L0_RX_DMA_ERR_INTR_MASK 0x00000008
-#define BCHP_PCIE_0_INTR2_CPU_CLEAR_L0_RX_DMA_ERR_INTR_SHIFT 3
-#define BCHP_PCIE_0_INTR2_CPU_CLEAR_L0_RX_DMA_ERR_INTR_DEFAULT 0x00000000
-
-/* PCIE_0_INTR2 :: CPU_CLEAR :: L0_RX_DMA_DONE_INTR [02:02] */
-#define BCHP_PCIE_0_INTR2_CPU_CLEAR_L0_RX_DMA_DONE_INTR_MASK 0x00000004
-#define BCHP_PCIE_0_INTR2_CPU_CLEAR_L0_RX_DMA_DONE_INTR_SHIFT 2
-#define BCHP_PCIE_0_INTR2_CPU_CLEAR_L0_RX_DMA_DONE_INTR_DEFAULT 0x00000000
-
-/* PCIE_0_INTR2 :: CPU_CLEAR :: L0_TX_DMA_ERR_INTR [01:01] */
-#define BCHP_PCIE_0_INTR2_CPU_CLEAR_L0_TX_DMA_ERR_INTR_MASK 0x00000002
-#define BCHP_PCIE_0_INTR2_CPU_CLEAR_L0_TX_DMA_ERR_INTR_SHIFT 1
-#define BCHP_PCIE_0_INTR2_CPU_CLEAR_L0_TX_DMA_ERR_INTR_DEFAULT 0x00000000
-
-/* PCIE_0_INTR2 :: CPU_CLEAR :: L0_TX_DMA_DONE_INTR [00:00] */
-#define BCHP_PCIE_0_INTR2_CPU_CLEAR_L0_TX_DMA_DONE_INTR_MASK 0x00000001
-#define BCHP_PCIE_0_INTR2_CPU_CLEAR_L0_TX_DMA_DONE_INTR_SHIFT 0
-#define BCHP_PCIE_0_INTR2_CPU_CLEAR_L0_TX_DMA_DONE_INTR_DEFAULT 0x00000000
-
-/***************************************************************************
- *CPU_MASK_STATUS - CPU interrupt Mask Status Register
- ***************************************************************************/
-/* PCIE_0_INTR2 :: CPU_MASK_STATUS :: MSI_INTR07 [31:31] */
-#define BCHP_PCIE_0_INTR2_CPU_MASK_STATUS_MSI_INTR07_MASK 0x80000000
-#define BCHP_PCIE_0_INTR2_CPU_MASK_STATUS_MSI_INTR07_SHIFT 31
-#define BCHP_PCIE_0_INTR2_CPU_MASK_STATUS_MSI_INTR07_DEFAULT 0x00000001
-
-/* PCIE_0_INTR2 :: CPU_MASK_STATUS :: MSI_INTR06 [30:30] */
-#define BCHP_PCIE_0_INTR2_CPU_MASK_STATUS_MSI_INTR06_MASK 0x40000000
-#define BCHP_PCIE_0_INTR2_CPU_MASK_STATUS_MSI_INTR06_SHIFT 30
-#define BCHP_PCIE_0_INTR2_CPU_MASK_STATUS_MSI_INTR06_DEFAULT 0x00000001
-
-/* PCIE_0_INTR2 :: CPU_MASK_STATUS :: MSI_INTR05 [29:29] */
-#define BCHP_PCIE_0_INTR2_CPU_MASK_STATUS_MSI_INTR05_MASK 0x20000000
-#define BCHP_PCIE_0_INTR2_CPU_MASK_STATUS_MSI_INTR05_SHIFT 29
-#define BCHP_PCIE_0_INTR2_CPU_MASK_STATUS_MSI_INTR05_DEFAULT 0x00000001
-
-/* PCIE_0_INTR2 :: CPU_MASK_STATUS :: MSI_INTR04 [28:28] */
-#define BCHP_PCIE_0_INTR2_CPU_MASK_STATUS_MSI_INTR04_MASK 0x10000000
-#define BCHP_PCIE_0_INTR2_CPU_MASK_STATUS_MSI_INTR04_SHIFT 28
-#define BCHP_PCIE_0_INTR2_CPU_MASK_STATUS_MSI_INTR04_DEFAULT 0x00000001
-
-/* PCIE_0_INTR2 :: CPU_MASK_STATUS :: MSI_INTR03 [27:27] */
-#define BCHP_PCIE_0_INTR2_CPU_MASK_STATUS_MSI_INTR03_MASK 0x08000000
-#define BCHP_PCIE_0_INTR2_CPU_MASK_STATUS_MSI_INTR03_SHIFT 27
-#define BCHP_PCIE_0_INTR2_CPU_MASK_STATUS_MSI_INTR03_DEFAULT 0x00000001
-
-/* PCIE_0_INTR2 :: CPU_MASK_STATUS :: MSI_INTR02 [26:26] */
-#define BCHP_PCIE_0_INTR2_CPU_MASK_STATUS_MSI_INTR02_MASK 0x04000000
-#define BCHP_PCIE_0_INTR2_CPU_MASK_STATUS_MSI_INTR02_SHIFT 26
-#define BCHP_PCIE_0_INTR2_CPU_MASK_STATUS_MSI_INTR02_DEFAULT 0x00000001
-
-/* PCIE_0_INTR2 :: CPU_MASK_STATUS :: MSI_INTR01 [25:25] */
-#define BCHP_PCIE_0_INTR2_CPU_MASK_STATUS_MSI_INTR01_MASK 0x02000000
-#define BCHP_PCIE_0_INTR2_CPU_MASK_STATUS_MSI_INTR01_SHIFT 25
-#define BCHP_PCIE_0_INTR2_CPU_MASK_STATUS_MSI_INTR01_DEFAULT 0x00000001
-
-/* PCIE_0_INTR2 :: CPU_MASK_STATUS :: MSI_INTR00 [24:24] */
-#define BCHP_PCIE_0_INTR2_CPU_MASK_STATUS_MSI_INTR00_MASK 0x01000000
-#define BCHP_PCIE_0_INTR2_CPU_MASK_STATUS_MSI_INTR00_SHIFT 24
-#define BCHP_PCIE_0_INTR2_CPU_MASK_STATUS_MSI_INTR00_DEFAULT 0x00000001
-
-/* PCIE_0_INTR2 :: CPU_MASK_STATUS :: UNASSIGNED_23 [23:23] */
-#define BCHP_PCIE_0_INTR2_CPU_MASK_STATUS_UNASSIGNED_23_MASK 0x00800000
-#define BCHP_PCIE_0_INTR2_CPU_MASK_STATUS_UNASSIGNED_23_SHIFT 23
-#define BCHP_PCIE_0_INTR2_CPU_MASK_STATUS_UNASSIGNED_23_DEFAULT 0x00000001
-
-/* PCIE_0_INTR2 :: CPU_MASK_STATUS :: UNASSIGNED_22 [22:22] */
-#define BCHP_PCIE_0_INTR2_CPU_MASK_STATUS_UNASSIGNED_22_MASK 0x00400000
-#define BCHP_PCIE_0_INTR2_CPU_MASK_STATUS_UNASSIGNED_22_SHIFT 22
-#define BCHP_PCIE_0_INTR2_CPU_MASK_STATUS_UNASSIGNED_22_DEFAULT 0x00000001
-
-/* PCIE_0_INTR2 :: CPU_MASK_STATUS :: UNASSIGNED_21 [21:21] */
-#define BCHP_PCIE_0_INTR2_CPU_MASK_STATUS_UNASSIGNED_21_MASK 0x00200000
-#define BCHP_PCIE_0_INTR2_CPU_MASK_STATUS_UNASSIGNED_21_SHIFT 21
-#define BCHP_PCIE_0_INTR2_CPU_MASK_STATUS_UNASSIGNED_21_DEFAULT 0x00000001
-
-/* PCIE_0_INTR2 :: CPU_MASK_STATUS :: UNASSIGNED_20 [20:20] */
-#define BCHP_PCIE_0_INTR2_CPU_MASK_STATUS_UNASSIGNED_20_MASK 0x00100000
-#define BCHP_PCIE_0_INTR2_CPU_MASK_STATUS_UNASSIGNED_20_SHIFT 20
-#define BCHP_PCIE_0_INTR2_CPU_MASK_STATUS_UNASSIGNED_20_DEFAULT 0x00000001
-
-/* PCIE_0_INTR2 :: CPU_MASK_STATUS :: MAILBOX_3 [19:19] */
-#define BCHP_PCIE_0_INTR2_CPU_MASK_STATUS_MAILBOX_3_MASK 0x00080000
-#define BCHP_PCIE_0_INTR2_CPU_MASK_STATUS_MAILBOX_3_SHIFT 19
-#define BCHP_PCIE_0_INTR2_CPU_MASK_STATUS_MAILBOX_3_DEFAULT 0x00000001
-
-/* PCIE_0_INTR2 :: CPU_MASK_STATUS :: MAILBOX_2 [18:18] */
-#define BCHP_PCIE_0_INTR2_CPU_MASK_STATUS_MAILBOX_2_MASK 0x00040000
-#define BCHP_PCIE_0_INTR2_CPU_MASK_STATUS_MAILBOX_2_SHIFT 18
-#define BCHP_PCIE_0_INTR2_CPU_MASK_STATUS_MAILBOX_2_DEFAULT 0x00000001
-
-/* PCIE_0_INTR2 :: CPU_MASK_STATUS :: MAILBOX_1 [17:17] */
-#define BCHP_PCIE_0_INTR2_CPU_MASK_STATUS_MAILBOX_1_MASK 0x00020000
-#define BCHP_PCIE_0_INTR2_CPU_MASK_STATUS_MAILBOX_1_SHIFT 17
-#define BCHP_PCIE_0_INTR2_CPU_MASK_STATUS_MAILBOX_1_DEFAULT 0x00000001
-
-/* PCIE_0_INTR2 :: CPU_MASK_STATUS :: MAILBOX_0 [16:16] */
-#define BCHP_PCIE_0_INTR2_CPU_MASK_STATUS_MAILBOX_0_MASK 0x00010000
-#define BCHP_PCIE_0_INTR2_CPU_MASK_STATUS_MAILBOX_0_SHIFT 16
-#define BCHP_PCIE_0_INTR2_CPU_MASK_STATUS_MAILBOX_0_DEFAULT 0x00000001
-
-/* PCIE_0_INTR2 :: CPU_MASK_STATUS :: PCIE_MSTR_FWD_ERR [15:15] */
-#define BCHP_PCIE_0_INTR2_CPU_MASK_STATUS_PCIE_MSTR_FWD_ERR_MASK 0x00008000
-#define BCHP_PCIE_0_INTR2_CPU_MASK_STATUS_PCIE_MSTR_FWD_ERR_SHIFT 15
-#define BCHP_PCIE_0_INTR2_CPU_MASK_STATUS_PCIE_MSTR_FWD_ERR_DEFAULT 0x00000001
-
-/* PCIE_0_INTR2 :: CPU_MASK_STATUS :: PCIE_MSTR_RETRY_TIMEOUT [14:14] */
-#define BCHP_PCIE_0_INTR2_CPU_MASK_STATUS_PCIE_MSTR_RETRY_TIMEOUT_MASK 0x00004000
-#define BCHP_PCIE_0_INTR2_CPU_MASK_STATUS_PCIE_MSTR_RETRY_TIMEOUT_SHIFT 14
-#define BCHP_PCIE_0_INTR2_CPU_MASK_STATUS_PCIE_MSTR_RETRY_TIMEOUT_DEFAULT 0x00000001
-
-/* PCIE_0_INTR2 :: CPU_MASK_STATUS :: PCIE_MSTR_CA_ATTN [13:13] */
-#define BCHP_PCIE_0_INTR2_CPU_MASK_STATUS_PCIE_MSTR_CA_ATTN_MASK 0x00002000
-#define BCHP_PCIE_0_INTR2_CPU_MASK_STATUS_PCIE_MSTR_CA_ATTN_SHIFT 13
-#define BCHP_PCIE_0_INTR2_CPU_MASK_STATUS_PCIE_MSTR_CA_ATTN_DEFAULT 0x00000001
-
-/* PCIE_0_INTR2 :: CPU_MASK_STATUS :: PCIE_MSTR_UR_ATTN [12:12] */
-#define BCHP_PCIE_0_INTR2_CPU_MASK_STATUS_PCIE_MSTR_UR_ATTN_MASK 0x00001000
-#define BCHP_PCIE_0_INTR2_CPU_MASK_STATUS_PCIE_MSTR_UR_ATTN_SHIFT 12
-#define BCHP_PCIE_0_INTR2_CPU_MASK_STATUS_PCIE_MSTR_UR_ATTN_DEFAULT 0x00000001
-
-/* PCIE_0_INTR2 :: CPU_MASK_STATUS :: UNASSIGNED_11 [11:11] */
-#define BCHP_PCIE_0_INTR2_CPU_MASK_STATUS_UNASSIGNED_11_MASK 0x00000800
-#define BCHP_PCIE_0_INTR2_CPU_MASK_STATUS_UNASSIGNED_11_SHIFT 11
-#define BCHP_PCIE_0_INTR2_CPU_MASK_STATUS_UNASSIGNED_11_DEFAULT 0x00000001
-
-/* PCIE_0_INTR2 :: CPU_MASK_STATUS :: UNASSIGNED_10 [10:10] */
-#define BCHP_PCIE_0_INTR2_CPU_MASK_STATUS_UNASSIGNED_10_MASK 0x00000400
-#define BCHP_PCIE_0_INTR2_CPU_MASK_STATUS_UNASSIGNED_10_SHIFT 10
-#define BCHP_PCIE_0_INTR2_CPU_MASK_STATUS_UNASSIGNED_10_DEFAULT 0x00000001
-
-/* PCIE_0_INTR2 :: CPU_MASK_STATUS :: PCIE_TGT_BAD_ACCESS [09:09] */
-#define BCHP_PCIE_0_INTR2_CPU_MASK_STATUS_PCIE_TGT_BAD_ACCESS_MASK 0x00000200
-#define BCHP_PCIE_0_INTR2_CPU_MASK_STATUS_PCIE_TGT_BAD_ACCESS_SHIFT 9
-#define BCHP_PCIE_0_INTR2_CPU_MASK_STATUS_PCIE_TGT_BAD_ACCESS_DEFAULT 0x00000001
-
-/* PCIE_0_INTR2 :: CPU_MASK_STATUS :: PCIE_TGT_BAD_ADDRESS [08:08] */
-#define BCHP_PCIE_0_INTR2_CPU_MASK_STATUS_PCIE_TGT_BAD_ADDRESS_MASK 0x00000100
-#define BCHP_PCIE_0_INTR2_CPU_MASK_STATUS_PCIE_TGT_BAD_ADDRESS_SHIFT 8
-#define BCHP_PCIE_0_INTR2_CPU_MASK_STATUS_PCIE_TGT_BAD_ADDRESS_DEFAULT 0x00000001
-
-/* PCIE_0_INTR2 :: CPU_MASK_STATUS :: L1_RX_DMA_ERR_INTR [07:07] */
-#define BCHP_PCIE_0_INTR2_CPU_MASK_STATUS_L1_RX_DMA_ERR_INTR_MASK 0x00000080
-#define BCHP_PCIE_0_INTR2_CPU_MASK_STATUS_L1_RX_DMA_ERR_INTR_SHIFT 7
-#define BCHP_PCIE_0_INTR2_CPU_MASK_STATUS_L1_RX_DMA_ERR_INTR_DEFAULT 0x00000001
-
-/* PCIE_0_INTR2 :: CPU_MASK_STATUS :: L1_RX_DMA_DONE_INTR [06:06] */
-#define BCHP_PCIE_0_INTR2_CPU_MASK_STATUS_L1_RX_DMA_DONE_INTR_MASK 0x00000040
-#define BCHP_PCIE_0_INTR2_CPU_MASK_STATUS_L1_RX_DMA_DONE_INTR_SHIFT 6
-#define BCHP_PCIE_0_INTR2_CPU_MASK_STATUS_L1_RX_DMA_DONE_INTR_DEFAULT 0x00000001
-
-/* PCIE_0_INTR2 :: CPU_MASK_STATUS :: L1_TX_DMA_ERR_INTR [05:05] */
-#define BCHP_PCIE_0_INTR2_CPU_MASK_STATUS_L1_TX_DMA_ERR_INTR_MASK 0x00000020
-#define BCHP_PCIE_0_INTR2_CPU_MASK_STATUS_L1_TX_DMA_ERR_INTR_SHIFT 5
-#define BCHP_PCIE_0_INTR2_CPU_MASK_STATUS_L1_TX_DMA_ERR_INTR_DEFAULT 0x00000001
-
-/* PCIE_0_INTR2 :: CPU_MASK_STATUS :: L1_TX_DMA_DONE_INTR [04:04] */
-#define BCHP_PCIE_0_INTR2_CPU_MASK_STATUS_L1_TX_DMA_DONE_INTR_MASK 0x00000010
-#define BCHP_PCIE_0_INTR2_CPU_MASK_STATUS_L1_TX_DMA_DONE_INTR_SHIFT 4
-#define BCHP_PCIE_0_INTR2_CPU_MASK_STATUS_L1_TX_DMA_DONE_INTR_DEFAULT 0x00000001
-
-/* PCIE_0_INTR2 :: CPU_MASK_STATUS :: L0_RX_DMA_ERR_INTR [03:03] */
-#define BCHP_PCIE_0_INTR2_CPU_MASK_STATUS_L0_RX_DMA_ERR_INTR_MASK 0x00000008
-#define BCHP_PCIE_0_INTR2_CPU_MASK_STATUS_L0_RX_DMA_ERR_INTR_SHIFT 3
-#define BCHP_PCIE_0_INTR2_CPU_MASK_STATUS_L0_RX_DMA_ERR_INTR_DEFAULT 0x00000001
-
-/* PCIE_0_INTR2 :: CPU_MASK_STATUS :: L0_RX_DMA_DONE_INTR [02:02] */
-#define BCHP_PCIE_0_INTR2_CPU_MASK_STATUS_L0_RX_DMA_DONE_INTR_MASK 0x00000004
-#define BCHP_PCIE_0_INTR2_CPU_MASK_STATUS_L0_RX_DMA_DONE_INTR_SHIFT 2
-#define BCHP_PCIE_0_INTR2_CPU_MASK_STATUS_L0_RX_DMA_DONE_INTR_DEFAULT 0x00000001
-
-/* PCIE_0_INTR2 :: CPU_MASK_STATUS :: L0_TX_DMA_ERR_INTR [01:01] */
-#define BCHP_PCIE_0_INTR2_CPU_MASK_STATUS_L0_TX_DMA_ERR_INTR_MASK 0x00000002
-#define BCHP_PCIE_0_INTR2_CPU_MASK_STATUS_L0_TX_DMA_ERR_INTR_SHIFT 1
-#define BCHP_PCIE_0_INTR2_CPU_MASK_STATUS_L0_TX_DMA_ERR_INTR_DEFAULT 0x00000001
-
-/* PCIE_0_INTR2 :: CPU_MASK_STATUS :: L0_TX_DMA_DONE_INTR [00:00] */
-#define BCHP_PCIE_0_INTR2_CPU_MASK_STATUS_L0_TX_DMA_DONE_INTR_MASK 0x00000001
-#define BCHP_PCIE_0_INTR2_CPU_MASK_STATUS_L0_TX_DMA_DONE_INTR_SHIFT 0
-#define BCHP_PCIE_0_INTR2_CPU_MASK_STATUS_L0_TX_DMA_DONE_INTR_DEFAULT 0x00000001
-
-/***************************************************************************
- *CPU_MASK_SET - CPU interrupt Mask Set Register
- ***************************************************************************/
-/* PCIE_0_INTR2 :: CPU_MASK_SET :: MSI_INTR07 [31:31] */
-#define BCHP_PCIE_0_INTR2_CPU_MASK_SET_MSI_INTR07_MASK 0x80000000
-#define BCHP_PCIE_0_INTR2_CPU_MASK_SET_MSI_INTR07_SHIFT 31
-#define BCHP_PCIE_0_INTR2_CPU_MASK_SET_MSI_INTR07_DEFAULT 0x00000001
-
-/* PCIE_0_INTR2 :: CPU_MASK_SET :: MSI_INTR06 [30:30] */
-#define BCHP_PCIE_0_INTR2_CPU_MASK_SET_MSI_INTR06_MASK 0x40000000
-#define BCHP_PCIE_0_INTR2_CPU_MASK_SET_MSI_INTR06_SHIFT 30
-#define BCHP_PCIE_0_INTR2_CPU_MASK_SET_MSI_INTR06_DEFAULT 0x00000001
-
-/* PCIE_0_INTR2 :: CPU_MASK_SET :: MSI_INTR05 [29:29] */
-#define BCHP_PCIE_0_INTR2_CPU_MASK_SET_MSI_INTR05_MASK 0x20000000
-#define BCHP_PCIE_0_INTR2_CPU_MASK_SET_MSI_INTR05_SHIFT 29
-#define BCHP_PCIE_0_INTR2_CPU_MASK_SET_MSI_INTR05_DEFAULT 0x00000001
-
-/* PCIE_0_INTR2 :: CPU_MASK_SET :: MSI_INTR04 [28:28] */
-#define BCHP_PCIE_0_INTR2_CPU_MASK_SET_MSI_INTR04_MASK 0x10000000
-#define BCHP_PCIE_0_INTR2_CPU_MASK_SET_MSI_INTR04_SHIFT 28
-#define BCHP_PCIE_0_INTR2_CPU_MASK_SET_MSI_INTR04_DEFAULT 0x00000001
-
-/* PCIE_0_INTR2 :: CPU_MASK_SET :: MSI_INTR03 [27:27] */
-#define BCHP_PCIE_0_INTR2_CPU_MASK_SET_MSI_INTR03_MASK 0x08000000
-#define BCHP_PCIE_0_INTR2_CPU_MASK_SET_MSI_INTR03_SHIFT 27
-#define BCHP_PCIE_0_INTR2_CPU_MASK_SET_MSI_INTR03_DEFAULT 0x00000001
-
-/* PCIE_0_INTR2 :: CPU_MASK_SET :: MSI_INTR02 [26:26] */
-#define BCHP_PCIE_0_INTR2_CPU_MASK_SET_MSI_INTR02_MASK 0x04000000
-#define BCHP_PCIE_0_INTR2_CPU_MASK_SET_MSI_INTR02_SHIFT 26
-#define BCHP_PCIE_0_INTR2_CPU_MASK_SET_MSI_INTR02_DEFAULT 0x00000001
-
-/* PCIE_0_INTR2 :: CPU_MASK_SET :: MSI_INTR01 [25:25] */
-#define BCHP_PCIE_0_INTR2_CPU_MASK_SET_MSI_INTR01_MASK 0x02000000
-#define BCHP_PCIE_0_INTR2_CPU_MASK_SET_MSI_INTR01_SHIFT 25
-#define BCHP_PCIE_0_INTR2_CPU_MASK_SET_MSI_INTR01_DEFAULT 0x00000001
-
-/* PCIE_0_INTR2 :: CPU_MASK_SET :: MSI_INTR00 [24:24] */
-#define BCHP_PCIE_0_INTR2_CPU_MASK_SET_MSI_INTR00_MASK 0x01000000
-#define BCHP_PCIE_0_INTR2_CPU_MASK_SET_MSI_INTR00_SHIFT 24
-#define BCHP_PCIE_0_INTR2_CPU_MASK_SET_MSI_INTR00_DEFAULT 0x00000001
-
-/* PCIE_0_INTR2 :: CPU_MASK_SET :: UNASSIGNED_23 [23:23] */
-#define BCHP_PCIE_0_INTR2_CPU_MASK_SET_UNASSIGNED_23_MASK 0x00800000
-#define BCHP_PCIE_0_INTR2_CPU_MASK_SET_UNASSIGNED_23_SHIFT 23
-#define BCHP_PCIE_0_INTR2_CPU_MASK_SET_UNASSIGNED_23_DEFAULT 0x00000001
-
-/* PCIE_0_INTR2 :: CPU_MASK_SET :: UNASSIGNED_22 [22:22] */
-#define BCHP_PCIE_0_INTR2_CPU_MASK_SET_UNASSIGNED_22_MASK 0x00400000
-#define BCHP_PCIE_0_INTR2_CPU_MASK_SET_UNASSIGNED_22_SHIFT 22
-#define BCHP_PCIE_0_INTR2_CPU_MASK_SET_UNASSIGNED_22_DEFAULT 0x00000001
-
-/* PCIE_0_INTR2 :: CPU_MASK_SET :: UNASSIGNED_21 [21:21] */
-#define BCHP_PCIE_0_INTR2_CPU_MASK_SET_UNASSIGNED_21_MASK 0x00200000
-#define BCHP_PCIE_0_INTR2_CPU_MASK_SET_UNASSIGNED_21_SHIFT 21
-#define BCHP_PCIE_0_INTR2_CPU_MASK_SET_UNASSIGNED_21_DEFAULT 0x00000001
-
-/* PCIE_0_INTR2 :: CPU_MASK_SET :: UNASSIGNED_20 [20:20] */
-#define BCHP_PCIE_0_INTR2_CPU_MASK_SET_UNASSIGNED_20_MASK 0x00100000
-#define BCHP_PCIE_0_INTR2_CPU_MASK_SET_UNASSIGNED_20_SHIFT 20
-#define BCHP_PCIE_0_INTR2_CPU_MASK_SET_UNASSIGNED_20_DEFAULT 0x00000001
-
-/* PCIE_0_INTR2 :: CPU_MASK_SET :: MAILBOX_3 [19:19] */
-#define BCHP_PCIE_0_INTR2_CPU_MASK_SET_MAILBOX_3_MASK 0x00080000
-#define BCHP_PCIE_0_INTR2_CPU_MASK_SET_MAILBOX_3_SHIFT 19
-#define BCHP_PCIE_0_INTR2_CPU_MASK_SET_MAILBOX_3_DEFAULT 0x00000001
-
-/* PCIE_0_INTR2 :: CPU_MASK_SET :: MAILBOX_2 [18:18] */
-#define BCHP_PCIE_0_INTR2_CPU_MASK_SET_MAILBOX_2_MASK 0x00040000
-#define BCHP_PCIE_0_INTR2_CPU_MASK_SET_MAILBOX_2_SHIFT 18
-#define BCHP_PCIE_0_INTR2_CPU_MASK_SET_MAILBOX_2_DEFAULT 0x00000001
-
-/* PCIE_0_INTR2 :: CPU_MASK_SET :: MAILBOX_1 [17:17] */
-#define BCHP_PCIE_0_INTR2_CPU_MASK_SET_MAILBOX_1_MASK 0x00020000
-#define BCHP_PCIE_0_INTR2_CPU_MASK_SET_MAILBOX_1_SHIFT 17
-#define BCHP_PCIE_0_INTR2_CPU_MASK_SET_MAILBOX_1_DEFAULT 0x00000001
-
-/* PCIE_0_INTR2 :: CPU_MASK_SET :: MAILBOX_0 [16:16] */
-#define BCHP_PCIE_0_INTR2_CPU_MASK_SET_MAILBOX_0_MASK 0x00010000
-#define BCHP_PCIE_0_INTR2_CPU_MASK_SET_MAILBOX_0_SHIFT 16
-#define BCHP_PCIE_0_INTR2_CPU_MASK_SET_MAILBOX_0_DEFAULT 0x00000001
-
-/* PCIE_0_INTR2 :: CPU_MASK_SET :: PCIE_MSTR_FWD_ERR [15:15] */
-#define BCHP_PCIE_0_INTR2_CPU_MASK_SET_PCIE_MSTR_FWD_ERR_MASK 0x00008000
-#define BCHP_PCIE_0_INTR2_CPU_MASK_SET_PCIE_MSTR_FWD_ERR_SHIFT 15
-#define BCHP_PCIE_0_INTR2_CPU_MASK_SET_PCIE_MSTR_FWD_ERR_DEFAULT 0x00000001
-
-/* PCIE_0_INTR2 :: CPU_MASK_SET :: PCIE_MSTR_RETRY_TIMEOUT [14:14] */
-#define BCHP_PCIE_0_INTR2_CPU_MASK_SET_PCIE_MSTR_RETRY_TIMEOUT_MASK 0x00004000
-#define BCHP_PCIE_0_INTR2_CPU_MASK_SET_PCIE_MSTR_RETRY_TIMEOUT_SHIFT 14
-#define BCHP_PCIE_0_INTR2_CPU_MASK_SET_PCIE_MSTR_RETRY_TIMEOUT_DEFAULT 0x00000001
-
-/* PCIE_0_INTR2 :: CPU_MASK_SET :: PCIE_MSTR_CA_ATTN [13:13] */
-#define BCHP_PCIE_0_INTR2_CPU_MASK_SET_PCIE_MSTR_CA_ATTN_MASK 0x00002000
-#define BCHP_PCIE_0_INTR2_CPU_MASK_SET_PCIE_MSTR_CA_ATTN_SHIFT 13
-#define BCHP_PCIE_0_INTR2_CPU_MASK_SET_PCIE_MSTR_CA_ATTN_DEFAULT 0x00000001
-
-/* PCIE_0_INTR2 :: CPU_MASK_SET :: PCIE_MSTR_UR_ATTN [12:12] */
-#define BCHP_PCIE_0_INTR2_CPU_MASK_SET_PCIE_MSTR_UR_ATTN_MASK 0x00001000
-#define BCHP_PCIE_0_INTR2_CPU_MASK_SET_PCIE_MSTR_UR_ATTN_SHIFT 12
-#define BCHP_PCIE_0_INTR2_CPU_MASK_SET_PCIE_MSTR_UR_ATTN_DEFAULT 0x00000001
-
-/* PCIE_0_INTR2 :: CPU_MASK_SET :: UNASSIGNED_11 [11:11] */
-#define BCHP_PCIE_0_INTR2_CPU_MASK_SET_UNASSIGNED_11_MASK 0x00000800
-#define BCHP_PCIE_0_INTR2_CPU_MASK_SET_UNASSIGNED_11_SHIFT 11
-#define BCHP_PCIE_0_INTR2_CPU_MASK_SET_UNASSIGNED_11_DEFAULT 0x00000001
-
-/* PCIE_0_INTR2 :: CPU_MASK_SET :: UNASSIGNED_10 [10:10] */
-#define BCHP_PCIE_0_INTR2_CPU_MASK_SET_UNASSIGNED_10_MASK 0x00000400
-#define BCHP_PCIE_0_INTR2_CPU_MASK_SET_UNASSIGNED_10_SHIFT 10
-#define BCHP_PCIE_0_INTR2_CPU_MASK_SET_UNASSIGNED_10_DEFAULT 0x00000001
-
-/* PCIE_0_INTR2 :: CPU_MASK_SET :: PCIE_TGT_BAD_ACCESS [09:09] */
-#define BCHP_PCIE_0_INTR2_CPU_MASK_SET_PCIE_TGT_BAD_ACCESS_MASK 0x00000200
-#define BCHP_PCIE_0_INTR2_CPU_MASK_SET_PCIE_TGT_BAD_ACCESS_SHIFT 9
-#define BCHP_PCIE_0_INTR2_CPU_MASK_SET_PCIE_TGT_BAD_ACCESS_DEFAULT 0x00000001
-
-/* PCIE_0_INTR2 :: CPU_MASK_SET :: PCIE_TGT_BAD_ADDRESS [08:08] */
-#define BCHP_PCIE_0_INTR2_CPU_MASK_SET_PCIE_TGT_BAD_ADDRESS_MASK 0x00000100
-#define BCHP_PCIE_0_INTR2_CPU_MASK_SET_PCIE_TGT_BAD_ADDRESS_SHIFT 8
-#define BCHP_PCIE_0_INTR2_CPU_MASK_SET_PCIE_TGT_BAD_ADDRESS_DEFAULT 0x00000001
-
-/* PCIE_0_INTR2 :: CPU_MASK_SET :: L1_RX_DMA_ERR_INTR [07:07] */
-#define BCHP_PCIE_0_INTR2_CPU_MASK_SET_L1_RX_DMA_ERR_INTR_MASK 0x00000080
-#define BCHP_PCIE_0_INTR2_CPU_MASK_SET_L1_RX_DMA_ERR_INTR_SHIFT 7
-#define BCHP_PCIE_0_INTR2_CPU_MASK_SET_L1_RX_DMA_ERR_INTR_DEFAULT 0x00000001
-
-/* PCIE_0_INTR2 :: CPU_MASK_SET :: L1_RX_DMA_DONE_INTR [06:06] */
-#define BCHP_PCIE_0_INTR2_CPU_MASK_SET_L1_RX_DMA_DONE_INTR_MASK 0x00000040
-#define BCHP_PCIE_0_INTR2_CPU_MASK_SET_L1_RX_DMA_DONE_INTR_SHIFT 6
-#define BCHP_PCIE_0_INTR2_CPU_MASK_SET_L1_RX_DMA_DONE_INTR_DEFAULT 0x00000001
-
-/* PCIE_0_INTR2 :: CPU_MASK_SET :: L1_TX_DMA_ERR_INTR [05:05] */
-#define BCHP_PCIE_0_INTR2_CPU_MASK_SET_L1_TX_DMA_ERR_INTR_MASK 0x00000020
-#define BCHP_PCIE_0_INTR2_CPU_MASK_SET_L1_TX_DMA_ERR_INTR_SHIFT 5
-#define BCHP_PCIE_0_INTR2_CPU_MASK_SET_L1_TX_DMA_ERR_INTR_DEFAULT 0x00000001
-
-/* PCIE_0_INTR2 :: CPU_MASK_SET :: L1_TX_DMA_DONE_INTR [04:04] */
-#define BCHP_PCIE_0_INTR2_CPU_MASK_SET_L1_TX_DMA_DONE_INTR_MASK 0x00000010
-#define BCHP_PCIE_0_INTR2_CPU_MASK_SET_L1_TX_DMA_DONE_INTR_SHIFT 4
-#define BCHP_PCIE_0_INTR2_CPU_MASK_SET_L1_TX_DMA_DONE_INTR_DEFAULT 0x00000001
-
-/* PCIE_0_INTR2 :: CPU_MASK_SET :: L0_RX_DMA_ERR_INTR [03:03] */
-#define BCHP_PCIE_0_INTR2_CPU_MASK_SET_L0_RX_DMA_ERR_INTR_MASK 0x00000008
-#define BCHP_PCIE_0_INTR2_CPU_MASK_SET_L0_RX_DMA_ERR_INTR_SHIFT 3
-#define BCHP_PCIE_0_INTR2_CPU_MASK_SET_L0_RX_DMA_ERR_INTR_DEFAULT 0x00000001
-
-/* PCIE_0_INTR2 :: CPU_MASK_SET :: L0_RX_DMA_DONE_INTR [02:02] */
-#define BCHP_PCIE_0_INTR2_CPU_MASK_SET_L0_RX_DMA_DONE_INTR_MASK 0x00000004
-#define BCHP_PCIE_0_INTR2_CPU_MASK_SET_L0_RX_DMA_DONE_INTR_SHIFT 2
-#define BCHP_PCIE_0_INTR2_CPU_MASK_SET_L0_RX_DMA_DONE_INTR_DEFAULT 0x00000001
-
-/* PCIE_0_INTR2 :: CPU_MASK_SET :: L0_TX_DMA_ERR_INTR [01:01] */
-#define BCHP_PCIE_0_INTR2_CPU_MASK_SET_L0_TX_DMA_ERR_INTR_MASK 0x00000002
-#define BCHP_PCIE_0_INTR2_CPU_MASK_SET_L0_TX_DMA_ERR_INTR_SHIFT 1
-#define BCHP_PCIE_0_INTR2_CPU_MASK_SET_L0_TX_DMA_ERR_INTR_DEFAULT 0x00000001
-
-/* PCIE_0_INTR2 :: CPU_MASK_SET :: L0_TX_DMA_DONE_INTR [00:00] */
-#define BCHP_PCIE_0_INTR2_CPU_MASK_SET_L0_TX_DMA_DONE_INTR_MASK 0x00000001
-#define BCHP_PCIE_0_INTR2_CPU_MASK_SET_L0_TX_DMA_DONE_INTR_SHIFT 0
-#define BCHP_PCIE_0_INTR2_CPU_MASK_SET_L0_TX_DMA_DONE_INTR_DEFAULT 0x00000001
-
-/***************************************************************************
- *CPU_MASK_CLEAR - CPU interrupt Mask Clear Register
- ***************************************************************************/
-/* PCIE_0_INTR2 :: CPU_MASK_CLEAR :: MSI_INTR07 [31:31] */
-#define BCHP_PCIE_0_INTR2_CPU_MASK_CLEAR_MSI_INTR07_MASK 0x80000000
-#define BCHP_PCIE_0_INTR2_CPU_MASK_CLEAR_MSI_INTR07_SHIFT 31
-#define BCHP_PCIE_0_INTR2_CPU_MASK_CLEAR_MSI_INTR07_DEFAULT 0x00000001
-
-/* PCIE_0_INTR2 :: CPU_MASK_CLEAR :: MSI_INTR06 [30:30] */
-#define BCHP_PCIE_0_INTR2_CPU_MASK_CLEAR_MSI_INTR06_MASK 0x40000000
-#define BCHP_PCIE_0_INTR2_CPU_MASK_CLEAR_MSI_INTR06_SHIFT 30
-#define BCHP_PCIE_0_INTR2_CPU_MASK_CLEAR_MSI_INTR06_DEFAULT 0x00000001
-
-/* PCIE_0_INTR2 :: CPU_MASK_CLEAR :: MSI_INTR05 [29:29] */
-#define BCHP_PCIE_0_INTR2_CPU_MASK_CLEAR_MSI_INTR05_MASK 0x20000000
-#define BCHP_PCIE_0_INTR2_CPU_MASK_CLEAR_MSI_INTR05_SHIFT 29
-#define BCHP_PCIE_0_INTR2_CPU_MASK_CLEAR_MSI_INTR05_DEFAULT 0x00000001
-
-/* PCIE_0_INTR2 :: CPU_MASK_CLEAR :: MSI_INTR04 [28:28] */
-#define BCHP_PCIE_0_INTR2_CPU_MASK_CLEAR_MSI_INTR04_MASK 0x10000000
-#define BCHP_PCIE_0_INTR2_CPU_MASK_CLEAR_MSI_INTR04_SHIFT 28
-#define BCHP_PCIE_0_INTR2_CPU_MASK_CLEAR_MSI_INTR04_DEFAULT 0x00000001
-
-/* PCIE_0_INTR2 :: CPU_MASK_CLEAR :: MSI_INTR03 [27:27] */
-#define BCHP_PCIE_0_INTR2_CPU_MASK_CLEAR_MSI_INTR03_MASK 0x08000000
-#define BCHP_PCIE_0_INTR2_CPU_MASK_CLEAR_MSI_INTR03_SHIFT 27
-#define BCHP_PCIE_0_INTR2_CPU_MASK_CLEAR_MSI_INTR03_DEFAULT 0x00000001
-
-/* PCIE_0_INTR2 :: CPU_MASK_CLEAR :: MSI_INTR02 [26:26] */
-#define BCHP_PCIE_0_INTR2_CPU_MASK_CLEAR_MSI_INTR02_MASK 0x04000000
-#define BCHP_PCIE_0_INTR2_CPU_MASK_CLEAR_MSI_INTR02_SHIFT 26
-#define BCHP_PCIE_0_INTR2_CPU_MASK_CLEAR_MSI_INTR02_DEFAULT 0x00000001
-
-/* PCIE_0_INTR2 :: CPU_MASK_CLEAR :: MSI_INTR01 [25:25] */
-#define BCHP_PCIE_0_INTR2_CPU_MASK_CLEAR_MSI_INTR01_MASK 0x02000000
-#define BCHP_PCIE_0_INTR2_CPU_MASK_CLEAR_MSI_INTR01_SHIFT 25
-#define BCHP_PCIE_0_INTR2_CPU_MASK_CLEAR_MSI_INTR01_DEFAULT 0x00000001
-
-/* PCIE_0_INTR2 :: CPU_MASK_CLEAR :: MSI_INTR00 [24:24] */
-#define BCHP_PCIE_0_INTR2_CPU_MASK_CLEAR_MSI_INTR00_MASK 0x01000000
-#define BCHP_PCIE_0_INTR2_CPU_MASK_CLEAR_MSI_INTR00_SHIFT 24
-#define BCHP_PCIE_0_INTR2_CPU_MASK_CLEAR_MSI_INTR00_DEFAULT 0x00000001
-
-/* PCIE_0_INTR2 :: CPU_MASK_CLEAR :: UNASSIGNED_23 [23:23] */
-#define BCHP_PCIE_0_INTR2_CPU_MASK_CLEAR_UNASSIGNED_23_MASK 0x00800000
-#define BCHP_PCIE_0_INTR2_CPU_MASK_CLEAR_UNASSIGNED_23_SHIFT 23
-#define BCHP_PCIE_0_INTR2_CPU_MASK_CLEAR_UNASSIGNED_23_DEFAULT 0x00000001
-
-/* PCIE_0_INTR2 :: CPU_MASK_CLEAR :: UNASSIGNED_22 [22:22] */
-#define BCHP_PCIE_0_INTR2_CPU_MASK_CLEAR_UNASSIGNED_22_MASK 0x00400000
-#define BCHP_PCIE_0_INTR2_CPU_MASK_CLEAR_UNASSIGNED_22_SHIFT 22
-#define BCHP_PCIE_0_INTR2_CPU_MASK_CLEAR_UNASSIGNED_22_DEFAULT 0x00000001
-
-/* PCIE_0_INTR2 :: CPU_MASK_CLEAR :: UNASSIGNED_21 [21:21] */
-#define BCHP_PCIE_0_INTR2_CPU_MASK_CLEAR_UNASSIGNED_21_MASK 0x00200000
-#define BCHP_PCIE_0_INTR2_CPU_MASK_CLEAR_UNASSIGNED_21_SHIFT 21
-#define BCHP_PCIE_0_INTR2_CPU_MASK_CLEAR_UNASSIGNED_21_DEFAULT 0x00000001
-
-/* PCIE_0_INTR2 :: CPU_MASK_CLEAR :: UNASSIGNED_20 [20:20] */
-#define BCHP_PCIE_0_INTR2_CPU_MASK_CLEAR_UNASSIGNED_20_MASK 0x00100000
-#define BCHP_PCIE_0_INTR2_CPU_MASK_CLEAR_UNASSIGNED_20_SHIFT 20
-#define BCHP_PCIE_0_INTR2_CPU_MASK_CLEAR_UNASSIGNED_20_DEFAULT 0x00000001
-
-/* PCIE_0_INTR2 :: CPU_MASK_CLEAR :: MAILBOX_3 [19:19] */
-#define BCHP_PCIE_0_INTR2_CPU_MASK_CLEAR_MAILBOX_3_MASK 0x00080000
-#define BCHP_PCIE_0_INTR2_CPU_MASK_CLEAR_MAILBOX_3_SHIFT 19
-#define BCHP_PCIE_0_INTR2_CPU_MASK_CLEAR_MAILBOX_3_DEFAULT 0x00000001
-
-/* PCIE_0_INTR2 :: CPU_MASK_CLEAR :: MAILBOX_2 [18:18] */
-#define BCHP_PCIE_0_INTR2_CPU_MASK_CLEAR_MAILBOX_2_MASK 0x00040000
-#define BCHP_PCIE_0_INTR2_CPU_MASK_CLEAR_MAILBOX_2_SHIFT 18
-#define BCHP_PCIE_0_INTR2_CPU_MASK_CLEAR_MAILBOX_2_DEFAULT 0x00000001
-
-/* PCIE_0_INTR2 :: CPU_MASK_CLEAR :: MAILBOX_1 [17:17] */
-#define BCHP_PCIE_0_INTR2_CPU_MASK_CLEAR_MAILBOX_1_MASK 0x00020000
-#define BCHP_PCIE_0_INTR2_CPU_MASK_CLEAR_MAILBOX_1_SHIFT 17
-#define BCHP_PCIE_0_INTR2_CPU_MASK_CLEAR_MAILBOX_1_DEFAULT 0x00000001
-
-/* PCIE_0_INTR2 :: CPU_MASK_CLEAR :: MAILBOX_0 [16:16] */
-#define BCHP_PCIE_0_INTR2_CPU_MASK_CLEAR_MAILBOX_0_MASK 0x00010000
-#define BCHP_PCIE_0_INTR2_CPU_MASK_CLEAR_MAILBOX_0_SHIFT 16
-#define BCHP_PCIE_0_INTR2_CPU_MASK_CLEAR_MAILBOX_0_DEFAULT 0x00000001
-
-/* PCIE_0_INTR2 :: CPU_MASK_CLEAR :: PCIE_MSTR_FWD_ERR [15:15] */
-#define BCHP_PCIE_0_INTR2_CPU_MASK_CLEAR_PCIE_MSTR_FWD_ERR_MASK 0x00008000
-#define BCHP_PCIE_0_INTR2_CPU_MASK_CLEAR_PCIE_MSTR_FWD_ERR_SHIFT 15
-#define BCHP_PCIE_0_INTR2_CPU_MASK_CLEAR_PCIE_MSTR_FWD_ERR_DEFAULT 0x00000001
-
-/* PCIE_0_INTR2 :: CPU_MASK_CLEAR :: PCIE_MSTR_RETRY_TIMEOUT [14:14] */
-#define BCHP_PCIE_0_INTR2_CPU_MASK_CLEAR_PCIE_MSTR_RETRY_TIMEOUT_MASK 0x00004000
-#define BCHP_PCIE_0_INTR2_CPU_MASK_CLEAR_PCIE_MSTR_RETRY_TIMEOUT_SHIFT 14
-#define BCHP_PCIE_0_INTR2_CPU_MASK_CLEAR_PCIE_MSTR_RETRY_TIMEOUT_DEFAULT 0x00000001
-
-/* PCIE_0_INTR2 :: CPU_MASK_CLEAR :: PCIE_MSTR_CA_ATTN [13:13] */
-#define BCHP_PCIE_0_INTR2_CPU_MASK_CLEAR_PCIE_MSTR_CA_ATTN_MASK 0x00002000
-#define BCHP_PCIE_0_INTR2_CPU_MASK_CLEAR_PCIE_MSTR_CA_ATTN_SHIFT 13
-#define BCHP_PCIE_0_INTR2_CPU_MASK_CLEAR_PCIE_MSTR_CA_ATTN_DEFAULT 0x00000001
-
-/* PCIE_0_INTR2 :: CPU_MASK_CLEAR :: PCIE_MSTR_UR_ATTN [12:12] */
-#define BCHP_PCIE_0_INTR2_CPU_MASK_CLEAR_PCIE_MSTR_UR_ATTN_MASK 0x00001000
-#define BCHP_PCIE_0_INTR2_CPU_MASK_CLEAR_PCIE_MSTR_UR_ATTN_SHIFT 12
-#define BCHP_PCIE_0_INTR2_CPU_MASK_CLEAR_PCIE_MSTR_UR_ATTN_DEFAULT 0x00000001
-
-/* PCIE_0_INTR2 :: CPU_MASK_CLEAR :: UNASSIGNED_11 [11:11] */
-#define BCHP_PCIE_0_INTR2_CPU_MASK_CLEAR_UNASSIGNED_11_MASK 0x00000800
-#define BCHP_PCIE_0_INTR2_CPU_MASK_CLEAR_UNASSIGNED_11_SHIFT 11
-#define BCHP_PCIE_0_INTR2_CPU_MASK_CLEAR_UNASSIGNED_11_DEFAULT 0x00000001
-
-/* PCIE_0_INTR2 :: CPU_MASK_CLEAR :: UNASSIGNED_10 [10:10] */
-#define BCHP_PCIE_0_INTR2_CPU_MASK_CLEAR_UNASSIGNED_10_MASK 0x00000400
-#define BCHP_PCIE_0_INTR2_CPU_MASK_CLEAR_UNASSIGNED_10_SHIFT 10
-#define BCHP_PCIE_0_INTR2_CPU_MASK_CLEAR_UNASSIGNED_10_DEFAULT 0x00000001
-
-/* PCIE_0_INTR2 :: CPU_MASK_CLEAR :: PCIE_TGT_BAD_ACCESS [09:09] */
-#define BCHP_PCIE_0_INTR2_CPU_MASK_CLEAR_PCIE_TGT_BAD_ACCESS_MASK 0x00000200
-#define BCHP_PCIE_0_INTR2_CPU_MASK_CLEAR_PCIE_TGT_BAD_ACCESS_SHIFT 9
-#define BCHP_PCIE_0_INTR2_CPU_MASK_CLEAR_PCIE_TGT_BAD_ACCESS_DEFAULT 0x00000001
-
-/* PCIE_0_INTR2 :: CPU_MASK_CLEAR :: PCIE_TGT_BAD_ADDRESS [08:08] */
-#define BCHP_PCIE_0_INTR2_CPU_MASK_CLEAR_PCIE_TGT_BAD_ADDRESS_MASK 0x00000100
-#define BCHP_PCIE_0_INTR2_CPU_MASK_CLEAR_PCIE_TGT_BAD_ADDRESS_SHIFT 8
-#define BCHP_PCIE_0_INTR2_CPU_MASK_CLEAR_PCIE_TGT_BAD_ADDRESS_DEFAULT 0x00000001
-
-/* PCIE_0_INTR2 :: CPU_MASK_CLEAR :: L1_RX_DMA_ERR_INTR [07:07] */
-#define BCHP_PCIE_0_INTR2_CPU_MASK_CLEAR_L1_RX_DMA_ERR_INTR_MASK 0x00000080
-#define BCHP_PCIE_0_INTR2_CPU_MASK_CLEAR_L1_RX_DMA_ERR_INTR_SHIFT 7
-#define BCHP_PCIE_0_INTR2_CPU_MASK_CLEAR_L1_RX_DMA_ERR_INTR_DEFAULT 0x00000001
-
-/* PCIE_0_INTR2 :: CPU_MASK_CLEAR :: L1_RX_DMA_DONE_INTR [06:06] */
-#define BCHP_PCIE_0_INTR2_CPU_MASK_CLEAR_L1_RX_DMA_DONE_INTR_MASK 0x00000040
-#define BCHP_PCIE_0_INTR2_CPU_MASK_CLEAR_L1_RX_DMA_DONE_INTR_SHIFT 6
-#define BCHP_PCIE_0_INTR2_CPU_MASK_CLEAR_L1_RX_DMA_DONE_INTR_DEFAULT 0x00000001
-
-/* PCIE_0_INTR2 :: CPU_MASK_CLEAR :: L1_TX_DMA_ERR_INTR [05:05] */
-#define BCHP_PCIE_0_INTR2_CPU_MASK_CLEAR_L1_TX_DMA_ERR_INTR_MASK 0x00000020
-#define BCHP_PCIE_0_INTR2_CPU_MASK_CLEAR_L1_TX_DMA_ERR_INTR_SHIFT 5
-#define BCHP_PCIE_0_INTR2_CPU_MASK_CLEAR_L1_TX_DMA_ERR_INTR_DEFAULT 0x00000001
-
-/* PCIE_0_INTR2 :: CPU_MASK_CLEAR :: L1_TX_DMA_DONE_INTR [04:04] */
-#define BCHP_PCIE_0_INTR2_CPU_MASK_CLEAR_L1_TX_DMA_DONE_INTR_MASK 0x00000010
-#define BCHP_PCIE_0_INTR2_CPU_MASK_CLEAR_L1_TX_DMA_DONE_INTR_SHIFT 4
-#define BCHP_PCIE_0_INTR2_CPU_MASK_CLEAR_L1_TX_DMA_DONE_INTR_DEFAULT 0x00000001
-
-/* PCIE_0_INTR2 :: CPU_MASK_CLEAR :: L0_RX_DMA_ERR_INTR [03:03] */
-#define BCHP_PCIE_0_INTR2_CPU_MASK_CLEAR_L0_RX_DMA_ERR_INTR_MASK 0x00000008
-#define BCHP_PCIE_0_INTR2_CPU_MASK_CLEAR_L0_RX_DMA_ERR_INTR_SHIFT 3
-#define BCHP_PCIE_0_INTR2_CPU_MASK_CLEAR_L0_RX_DMA_ERR_INTR_DEFAULT 0x00000001
-
-/* PCIE_0_INTR2 :: CPU_MASK_CLEAR :: L0_RX_DMA_DONE_INTR [02:02] */
-#define BCHP_PCIE_0_INTR2_CPU_MASK_CLEAR_L0_RX_DMA_DONE_INTR_MASK 0x00000004
-#define BCHP_PCIE_0_INTR2_CPU_MASK_CLEAR_L0_RX_DMA_DONE_INTR_SHIFT 2
-#define BCHP_PCIE_0_INTR2_CPU_MASK_CLEAR_L0_RX_DMA_DONE_INTR_DEFAULT 0x00000001
-
-/* PCIE_0_INTR2 :: CPU_MASK_CLEAR :: L0_TX_DMA_ERR_INTR [01:01] */
-#define BCHP_PCIE_0_INTR2_CPU_MASK_CLEAR_L0_TX_DMA_ERR_INTR_MASK 0x00000002
-#define BCHP_PCIE_0_INTR2_CPU_MASK_CLEAR_L0_TX_DMA_ERR_INTR_SHIFT 1
-#define BCHP_PCIE_0_INTR2_CPU_MASK_CLEAR_L0_TX_DMA_ERR_INTR_DEFAULT 0x00000001
-
-/* PCIE_0_INTR2 :: CPU_MASK_CLEAR :: L0_TX_DMA_DONE_INTR [00:00] */
-#define BCHP_PCIE_0_INTR2_CPU_MASK_CLEAR_L0_TX_DMA_DONE_INTR_MASK 0x00000001
-#define BCHP_PCIE_0_INTR2_CPU_MASK_CLEAR_L0_TX_DMA_DONE_INTR_SHIFT 0
-#define BCHP_PCIE_0_INTR2_CPU_MASK_CLEAR_L0_TX_DMA_DONE_INTR_DEFAULT 0x00000001
-
-/***************************************************************************
- *PCI_STATUS - PCI interrupt Status Register
- ***************************************************************************/
-/* PCIE_0_INTR2 :: PCI_STATUS :: MSI_INTR07 [31:31] */
-#define BCHP_PCIE_0_INTR2_PCI_STATUS_MSI_INTR07_MASK 0x80000000
-#define BCHP_PCIE_0_INTR2_PCI_STATUS_MSI_INTR07_SHIFT 31
-#define BCHP_PCIE_0_INTR2_PCI_STATUS_MSI_INTR07_DEFAULT 0x00000000
-
-/* PCIE_0_INTR2 :: PCI_STATUS :: MSI_INTR06 [30:30] */
-#define BCHP_PCIE_0_INTR2_PCI_STATUS_MSI_INTR06_MASK 0x40000000
-#define BCHP_PCIE_0_INTR2_PCI_STATUS_MSI_INTR06_SHIFT 30
-#define BCHP_PCIE_0_INTR2_PCI_STATUS_MSI_INTR06_DEFAULT 0x00000000
-
-/* PCIE_0_INTR2 :: PCI_STATUS :: MSI_INTR05 [29:29] */
-#define BCHP_PCIE_0_INTR2_PCI_STATUS_MSI_INTR05_MASK 0x20000000
-#define BCHP_PCIE_0_INTR2_PCI_STATUS_MSI_INTR05_SHIFT 29
-#define BCHP_PCIE_0_INTR2_PCI_STATUS_MSI_INTR05_DEFAULT 0x00000000
-
-/* PCIE_0_INTR2 :: PCI_STATUS :: MSI_INTR04 [28:28] */
-#define BCHP_PCIE_0_INTR2_PCI_STATUS_MSI_INTR04_MASK 0x10000000
-#define BCHP_PCIE_0_INTR2_PCI_STATUS_MSI_INTR04_SHIFT 28
-#define BCHP_PCIE_0_INTR2_PCI_STATUS_MSI_INTR04_DEFAULT 0x00000000
-
-/* PCIE_0_INTR2 :: PCI_STATUS :: MSI_INTR03 [27:27] */
-#define BCHP_PCIE_0_INTR2_PCI_STATUS_MSI_INTR03_MASK 0x08000000
-#define BCHP_PCIE_0_INTR2_PCI_STATUS_MSI_INTR03_SHIFT 27
-#define BCHP_PCIE_0_INTR2_PCI_STATUS_MSI_INTR03_DEFAULT 0x00000000
-
-/* PCIE_0_INTR2 :: PCI_STATUS :: MSI_INTR02 [26:26] */
-#define BCHP_PCIE_0_INTR2_PCI_STATUS_MSI_INTR02_MASK 0x04000000
-#define BCHP_PCIE_0_INTR2_PCI_STATUS_MSI_INTR02_SHIFT 26
-#define BCHP_PCIE_0_INTR2_PCI_STATUS_MSI_INTR02_DEFAULT 0x00000000
-
-/* PCIE_0_INTR2 :: PCI_STATUS :: MSI_INTR01 [25:25] */
-#define BCHP_PCIE_0_INTR2_PCI_STATUS_MSI_INTR01_MASK 0x02000000
-#define BCHP_PCIE_0_INTR2_PCI_STATUS_MSI_INTR01_SHIFT 25
-#define BCHP_PCIE_0_INTR2_PCI_STATUS_MSI_INTR01_DEFAULT 0x00000000
-
-/* PCIE_0_INTR2 :: PCI_STATUS :: MSI_INTR00 [24:24] */
-#define BCHP_PCIE_0_INTR2_PCI_STATUS_MSI_INTR00_MASK 0x01000000
-#define BCHP_PCIE_0_INTR2_PCI_STATUS_MSI_INTR00_SHIFT 24
-#define BCHP_PCIE_0_INTR2_PCI_STATUS_MSI_INTR00_DEFAULT 0x00000000
-
-/* PCIE_0_INTR2 :: PCI_STATUS :: UNASSIGNED_23 [23:23] */
-#define BCHP_PCIE_0_INTR2_PCI_STATUS_UNASSIGNED_23_MASK 0x00800000
-#define BCHP_PCIE_0_INTR2_PCI_STATUS_UNASSIGNED_23_SHIFT 23
-#define BCHP_PCIE_0_INTR2_PCI_STATUS_UNASSIGNED_23_DEFAULT 0x00000000
-
-/* PCIE_0_INTR2 :: PCI_STATUS :: UNASSIGNED_22 [22:22] */
-#define BCHP_PCIE_0_INTR2_PCI_STATUS_UNASSIGNED_22_MASK 0x00400000
-#define BCHP_PCIE_0_INTR2_PCI_STATUS_UNASSIGNED_22_SHIFT 22
-#define BCHP_PCIE_0_INTR2_PCI_STATUS_UNASSIGNED_22_DEFAULT 0x00000000
-
-/* PCIE_0_INTR2 :: PCI_STATUS :: UNASSIGNED_21 [21:21] */
-#define BCHP_PCIE_0_INTR2_PCI_STATUS_UNASSIGNED_21_MASK 0x00200000
-#define BCHP_PCIE_0_INTR2_PCI_STATUS_UNASSIGNED_21_SHIFT 21
-#define BCHP_PCIE_0_INTR2_PCI_STATUS_UNASSIGNED_21_DEFAULT 0x00000000
-
-/* PCIE_0_INTR2 :: PCI_STATUS :: UNASSIGNED_20 [20:20] */
-#define BCHP_PCIE_0_INTR2_PCI_STATUS_UNASSIGNED_20_MASK 0x00100000
-#define BCHP_PCIE_0_INTR2_PCI_STATUS_UNASSIGNED_20_SHIFT 20
-#define BCHP_PCIE_0_INTR2_PCI_STATUS_UNASSIGNED_20_DEFAULT 0x00000000
-
-/* PCIE_0_INTR2 :: PCI_STATUS :: MAILBOX_3 [19:19] */
-#define BCHP_PCIE_0_INTR2_PCI_STATUS_MAILBOX_3_MASK 0x00080000
-#define BCHP_PCIE_0_INTR2_PCI_STATUS_MAILBOX_3_SHIFT 19
-#define BCHP_PCIE_0_INTR2_PCI_STATUS_MAILBOX_3_DEFAULT 0x00000000
-
-/* PCIE_0_INTR2 :: PCI_STATUS :: MAILBOX_2 [18:18] */
-#define BCHP_PCIE_0_INTR2_PCI_STATUS_MAILBOX_2_MASK 0x00040000
-#define BCHP_PCIE_0_INTR2_PCI_STATUS_MAILBOX_2_SHIFT 18
-#define BCHP_PCIE_0_INTR2_PCI_STATUS_MAILBOX_2_DEFAULT 0x00000000
-
-/* PCIE_0_INTR2 :: PCI_STATUS :: MAILBOX_1 [17:17] */
-#define BCHP_PCIE_0_INTR2_PCI_STATUS_MAILBOX_1_MASK 0x00020000
-#define BCHP_PCIE_0_INTR2_PCI_STATUS_MAILBOX_1_SHIFT 17
-#define BCHP_PCIE_0_INTR2_PCI_STATUS_MAILBOX_1_DEFAULT 0x00000000
-
-/* PCIE_0_INTR2 :: PCI_STATUS :: MAILBOX_0 [16:16] */
-#define BCHP_PCIE_0_INTR2_PCI_STATUS_MAILBOX_0_MASK 0x00010000
-#define BCHP_PCIE_0_INTR2_PCI_STATUS_MAILBOX_0_SHIFT 16
-#define BCHP_PCIE_0_INTR2_PCI_STATUS_MAILBOX_0_DEFAULT 0x00000000
-
-/* PCIE_0_INTR2 :: PCI_STATUS :: PCIE_MSTR_FWD_ERR [15:15] */
-#define BCHP_PCIE_0_INTR2_PCI_STATUS_PCIE_MSTR_FWD_ERR_MASK 0x00008000
-#define BCHP_PCIE_0_INTR2_PCI_STATUS_PCIE_MSTR_FWD_ERR_SHIFT 15
-#define BCHP_PCIE_0_INTR2_PCI_STATUS_PCIE_MSTR_FWD_ERR_DEFAULT 0x00000000
-
-/* PCIE_0_INTR2 :: PCI_STATUS :: PCIE_MSTR_RETRY_TIMEOUT [14:14] */
-#define BCHP_PCIE_0_INTR2_PCI_STATUS_PCIE_MSTR_RETRY_TIMEOUT_MASK 0x00004000
-#define BCHP_PCIE_0_INTR2_PCI_STATUS_PCIE_MSTR_RETRY_TIMEOUT_SHIFT 14
-#define BCHP_PCIE_0_INTR2_PCI_STATUS_PCIE_MSTR_RETRY_TIMEOUT_DEFAULT 0x00000000
-
-/* PCIE_0_INTR2 :: PCI_STATUS :: PCIE_MSTR_CA_ATTN [13:13] */
-#define BCHP_PCIE_0_INTR2_PCI_STATUS_PCIE_MSTR_CA_ATTN_MASK 0x00002000
-#define BCHP_PCIE_0_INTR2_PCI_STATUS_PCIE_MSTR_CA_ATTN_SHIFT 13
-#define BCHP_PCIE_0_INTR2_PCI_STATUS_PCIE_MSTR_CA_ATTN_DEFAULT 0x00000000
-
-/* PCIE_0_INTR2 :: PCI_STATUS :: PCIE_MSTR_UR_ATTN [12:12] */
-#define BCHP_PCIE_0_INTR2_PCI_STATUS_PCIE_MSTR_UR_ATTN_MASK 0x00001000
-#define BCHP_PCIE_0_INTR2_PCI_STATUS_PCIE_MSTR_UR_ATTN_SHIFT 12
-#define BCHP_PCIE_0_INTR2_PCI_STATUS_PCIE_MSTR_UR_ATTN_DEFAULT 0x00000000
-
-/* PCIE_0_INTR2 :: PCI_STATUS :: UNASSIGNED_11 [11:11] */
-#define BCHP_PCIE_0_INTR2_PCI_STATUS_UNASSIGNED_11_MASK 0x00000800
-#define BCHP_PCIE_0_INTR2_PCI_STATUS_UNASSIGNED_11_SHIFT 11
-#define BCHP_PCIE_0_INTR2_PCI_STATUS_UNASSIGNED_11_DEFAULT 0x00000000
-
-/* PCIE_0_INTR2 :: PCI_STATUS :: UNASSIGNED_10 [10:10] */
-#define BCHP_PCIE_0_INTR2_PCI_STATUS_UNASSIGNED_10_MASK 0x00000400
-#define BCHP_PCIE_0_INTR2_PCI_STATUS_UNASSIGNED_10_SHIFT 10
-#define BCHP_PCIE_0_INTR2_PCI_STATUS_UNASSIGNED_10_DEFAULT 0x00000000
-
-/* PCIE_0_INTR2 :: PCI_STATUS :: PCIE_TGT_BAD_ACCESS [09:09] */
-#define BCHP_PCIE_0_INTR2_PCI_STATUS_PCIE_TGT_BAD_ACCESS_MASK 0x00000200
-#define BCHP_PCIE_0_INTR2_PCI_STATUS_PCIE_TGT_BAD_ACCESS_SHIFT 9
-#define BCHP_PCIE_0_INTR2_PCI_STATUS_PCIE_TGT_BAD_ACCESS_DEFAULT 0x00000000
-
-/* PCIE_0_INTR2 :: PCI_STATUS :: PCIE_TGT_BAD_ADDRESS [08:08] */
-#define BCHP_PCIE_0_INTR2_PCI_STATUS_PCIE_TGT_BAD_ADDRESS_MASK 0x00000100
-#define BCHP_PCIE_0_INTR2_PCI_STATUS_PCIE_TGT_BAD_ADDRESS_SHIFT 8
-#define BCHP_PCIE_0_INTR2_PCI_STATUS_PCIE_TGT_BAD_ADDRESS_DEFAULT 0x00000000
-
-/* PCIE_0_INTR2 :: PCI_STATUS :: L1_RX_DMA_ERR_INTR [07:07] */
-#define BCHP_PCIE_0_INTR2_PCI_STATUS_L1_RX_DMA_ERR_INTR_MASK 0x00000080
-#define BCHP_PCIE_0_INTR2_PCI_STATUS_L1_RX_DMA_ERR_INTR_SHIFT 7
-#define BCHP_PCIE_0_INTR2_PCI_STATUS_L1_RX_DMA_ERR_INTR_DEFAULT 0x00000000
-
-/* PCIE_0_INTR2 :: PCI_STATUS :: L1_RX_DMA_DONE_INTR [06:06] */
-#define BCHP_PCIE_0_INTR2_PCI_STATUS_L1_RX_DMA_DONE_INTR_MASK 0x00000040
-#define BCHP_PCIE_0_INTR2_PCI_STATUS_L1_RX_DMA_DONE_INTR_SHIFT 6
-#define BCHP_PCIE_0_INTR2_PCI_STATUS_L1_RX_DMA_DONE_INTR_DEFAULT 0x00000000
-
-/* PCIE_0_INTR2 :: PCI_STATUS :: L1_TX_DMA_ERR_INTR [05:05] */
-#define BCHP_PCIE_0_INTR2_PCI_STATUS_L1_TX_DMA_ERR_INTR_MASK 0x00000020
-#define BCHP_PCIE_0_INTR2_PCI_STATUS_L1_TX_DMA_ERR_INTR_SHIFT 5
-#define BCHP_PCIE_0_INTR2_PCI_STATUS_L1_TX_DMA_ERR_INTR_DEFAULT 0x00000000
-
-/* PCIE_0_INTR2 :: PCI_STATUS :: L1_TX_DMA_DONE_INTR [04:04] */
-#define BCHP_PCIE_0_INTR2_PCI_STATUS_L1_TX_DMA_DONE_INTR_MASK 0x00000010
-#define BCHP_PCIE_0_INTR2_PCI_STATUS_L1_TX_DMA_DONE_INTR_SHIFT 4
-#define BCHP_PCIE_0_INTR2_PCI_STATUS_L1_TX_DMA_DONE_INTR_DEFAULT 0x00000000
-
-/* PCIE_0_INTR2 :: PCI_STATUS :: L0_RX_DMA_ERR_INTR [03:03] */
-#define BCHP_PCIE_0_INTR2_PCI_STATUS_L0_RX_DMA_ERR_INTR_MASK 0x00000008
-#define BCHP_PCIE_0_INTR2_PCI_STATUS_L0_RX_DMA_ERR_INTR_SHIFT 3
-#define BCHP_PCIE_0_INTR2_PCI_STATUS_L0_RX_DMA_ERR_INTR_DEFAULT 0x00000000
-
-/* PCIE_0_INTR2 :: PCI_STATUS :: L0_RX_DMA_DONE_INTR [02:02] */
-#define BCHP_PCIE_0_INTR2_PCI_STATUS_L0_RX_DMA_DONE_INTR_MASK 0x00000004
-#define BCHP_PCIE_0_INTR2_PCI_STATUS_L0_RX_DMA_DONE_INTR_SHIFT 2
-#define BCHP_PCIE_0_INTR2_PCI_STATUS_L0_RX_DMA_DONE_INTR_DEFAULT 0x00000000
-
-/* PCIE_0_INTR2 :: PCI_STATUS :: L0_TX_DMA_ERR_INTR [01:01] */
-#define BCHP_PCIE_0_INTR2_PCI_STATUS_L0_TX_DMA_ERR_INTR_MASK 0x00000002
-#define BCHP_PCIE_0_INTR2_PCI_STATUS_L0_TX_DMA_ERR_INTR_SHIFT 1
-#define BCHP_PCIE_0_INTR2_PCI_STATUS_L0_TX_DMA_ERR_INTR_DEFAULT 0x00000000
-
-/* PCIE_0_INTR2 :: PCI_STATUS :: L0_TX_DMA_DONE_INTR [00:00] */
-#define BCHP_PCIE_0_INTR2_PCI_STATUS_L0_TX_DMA_DONE_INTR_MASK 0x00000001
-#define BCHP_PCIE_0_INTR2_PCI_STATUS_L0_TX_DMA_DONE_INTR_SHIFT 0
-#define BCHP_PCIE_0_INTR2_PCI_STATUS_L0_TX_DMA_DONE_INTR_DEFAULT 0x00000000
-
-/***************************************************************************
- *PCI_SET - PCI interrupt Set Register
- ***************************************************************************/
-/* PCIE_0_INTR2 :: PCI_SET :: MSI_INTR07 [31:31] */
-#define BCHP_PCIE_0_INTR2_PCI_SET_MSI_INTR07_MASK 0x80000000
-#define BCHP_PCIE_0_INTR2_PCI_SET_MSI_INTR07_SHIFT 31
-#define BCHP_PCIE_0_INTR2_PCI_SET_MSI_INTR07_DEFAULT 0x00000000
-
-/* PCIE_0_INTR2 :: PCI_SET :: MSI_INTR06 [30:30] */
-#define BCHP_PCIE_0_INTR2_PCI_SET_MSI_INTR06_MASK 0x40000000
-#define BCHP_PCIE_0_INTR2_PCI_SET_MSI_INTR06_SHIFT 30
-#define BCHP_PCIE_0_INTR2_PCI_SET_MSI_INTR06_DEFAULT 0x00000000
-
-/* PCIE_0_INTR2 :: PCI_SET :: MSI_INTR05 [29:29] */
-#define BCHP_PCIE_0_INTR2_PCI_SET_MSI_INTR05_MASK 0x20000000
-#define BCHP_PCIE_0_INTR2_PCI_SET_MSI_INTR05_SHIFT 29
-#define BCHP_PCIE_0_INTR2_PCI_SET_MSI_INTR05_DEFAULT 0x00000000
-
-/* PCIE_0_INTR2 :: PCI_SET :: MSI_INTR04 [28:28] */
-#define BCHP_PCIE_0_INTR2_PCI_SET_MSI_INTR04_MASK 0x10000000
-#define BCHP_PCIE_0_INTR2_PCI_SET_MSI_INTR04_SHIFT 28
-#define BCHP_PCIE_0_INTR2_PCI_SET_MSI_INTR04_DEFAULT 0x00000000
-
-/* PCIE_0_INTR2 :: PCI_SET :: MSI_INTR03 [27:27] */
-#define BCHP_PCIE_0_INTR2_PCI_SET_MSI_INTR03_MASK 0x08000000
-#define BCHP_PCIE_0_INTR2_PCI_SET_MSI_INTR03_SHIFT 27
-#define BCHP_PCIE_0_INTR2_PCI_SET_MSI_INTR03_DEFAULT 0x00000000
-
-/* PCIE_0_INTR2 :: PCI_SET :: MSI_INTR02 [26:26] */
-#define BCHP_PCIE_0_INTR2_PCI_SET_MSI_INTR02_MASK 0x04000000
-#define BCHP_PCIE_0_INTR2_PCI_SET_MSI_INTR02_SHIFT 26
-#define BCHP_PCIE_0_INTR2_PCI_SET_MSI_INTR02_DEFAULT 0x00000000
-
-/* PCIE_0_INTR2 :: PCI_SET :: MSI_INTR01 [25:25] */
-#define BCHP_PCIE_0_INTR2_PCI_SET_MSI_INTR01_MASK 0x02000000
-#define BCHP_PCIE_0_INTR2_PCI_SET_MSI_INTR01_SHIFT 25
-#define BCHP_PCIE_0_INTR2_PCI_SET_MSI_INTR01_DEFAULT 0x00000000
-
-/* PCIE_0_INTR2 :: PCI_SET :: MSI_INTR00 [24:24] */
-#define BCHP_PCIE_0_INTR2_PCI_SET_MSI_INTR00_MASK 0x01000000
-#define BCHP_PCIE_0_INTR2_PCI_SET_MSI_INTR00_SHIFT 24
-#define BCHP_PCIE_0_INTR2_PCI_SET_MSI_INTR00_DEFAULT 0x00000000
-
-/* PCIE_0_INTR2 :: PCI_SET :: UNASSIGNED_23 [23:23] */
-#define BCHP_PCIE_0_INTR2_PCI_SET_UNASSIGNED_23_MASK 0x00800000
-#define BCHP_PCIE_0_INTR2_PCI_SET_UNASSIGNED_23_SHIFT 23
-#define BCHP_PCIE_0_INTR2_PCI_SET_UNASSIGNED_23_DEFAULT 0x00000000
-
-/* PCIE_0_INTR2 :: PCI_SET :: UNASSIGNED_22 [22:22] */
-#define BCHP_PCIE_0_INTR2_PCI_SET_UNASSIGNED_22_MASK 0x00400000
-#define BCHP_PCIE_0_INTR2_PCI_SET_UNASSIGNED_22_SHIFT 22
-#define BCHP_PCIE_0_INTR2_PCI_SET_UNASSIGNED_22_DEFAULT 0x00000000
-
-/* PCIE_0_INTR2 :: PCI_SET :: UNASSIGNED_21 [21:21] */
-#define BCHP_PCIE_0_INTR2_PCI_SET_UNASSIGNED_21_MASK 0x00200000
-#define BCHP_PCIE_0_INTR2_PCI_SET_UNASSIGNED_21_SHIFT 21
-#define BCHP_PCIE_0_INTR2_PCI_SET_UNASSIGNED_21_DEFAULT 0x00000000
-
-/* PCIE_0_INTR2 :: PCI_SET :: UNASSIGNED_20 [20:20] */
-#define BCHP_PCIE_0_INTR2_PCI_SET_UNASSIGNED_20_MASK 0x00100000
-#define BCHP_PCIE_0_INTR2_PCI_SET_UNASSIGNED_20_SHIFT 20
-#define BCHP_PCIE_0_INTR2_PCI_SET_UNASSIGNED_20_DEFAULT 0x00000000
-
-/* PCIE_0_INTR2 :: PCI_SET :: MAILBOX_3 [19:19] */
-#define BCHP_PCIE_0_INTR2_PCI_SET_MAILBOX_3_MASK 0x00080000
-#define BCHP_PCIE_0_INTR2_PCI_SET_MAILBOX_3_SHIFT 19
-#define BCHP_PCIE_0_INTR2_PCI_SET_MAILBOX_3_DEFAULT 0x00000000
-
-/* PCIE_0_INTR2 :: PCI_SET :: MAILBOX_2 [18:18] */
-#define BCHP_PCIE_0_INTR2_PCI_SET_MAILBOX_2_MASK 0x00040000
-#define BCHP_PCIE_0_INTR2_PCI_SET_MAILBOX_2_SHIFT 18
-#define BCHP_PCIE_0_INTR2_PCI_SET_MAILBOX_2_DEFAULT 0x00000000
-
-/* PCIE_0_INTR2 :: PCI_SET :: MAILBOX_1 [17:17] */
-#define BCHP_PCIE_0_INTR2_PCI_SET_MAILBOX_1_MASK 0x00020000
-#define BCHP_PCIE_0_INTR2_PCI_SET_MAILBOX_1_SHIFT 17
-#define BCHP_PCIE_0_INTR2_PCI_SET_MAILBOX_1_DEFAULT 0x00000000
-
-/* PCIE_0_INTR2 :: PCI_SET :: MAILBOX_0 [16:16] */
-#define BCHP_PCIE_0_INTR2_PCI_SET_MAILBOX_0_MASK 0x00010000
-#define BCHP_PCIE_0_INTR2_PCI_SET_MAILBOX_0_SHIFT 16
-#define BCHP_PCIE_0_INTR2_PCI_SET_MAILBOX_0_DEFAULT 0x00000000
-
-/* PCIE_0_INTR2 :: PCI_SET :: PCIE_MSTR_FWD_ERR [15:15] */
-#define BCHP_PCIE_0_INTR2_PCI_SET_PCIE_MSTR_FWD_ERR_MASK 0x00008000
-#define BCHP_PCIE_0_INTR2_PCI_SET_PCIE_MSTR_FWD_ERR_SHIFT 15
-#define BCHP_PCIE_0_INTR2_PCI_SET_PCIE_MSTR_FWD_ERR_DEFAULT 0x00000000
-
-/* PCIE_0_INTR2 :: PCI_SET :: PCIE_MSTR_RETRY_TIMEOUT [14:14] */
-#define BCHP_PCIE_0_INTR2_PCI_SET_PCIE_MSTR_RETRY_TIMEOUT_MASK 0x00004000
-#define BCHP_PCIE_0_INTR2_PCI_SET_PCIE_MSTR_RETRY_TIMEOUT_SHIFT 14
-#define BCHP_PCIE_0_INTR2_PCI_SET_PCIE_MSTR_RETRY_TIMEOUT_DEFAULT 0x00000000
-
-/* PCIE_0_INTR2 :: PCI_SET :: PCIE_MSTR_CA_ATTN [13:13] */
-#define BCHP_PCIE_0_INTR2_PCI_SET_PCIE_MSTR_CA_ATTN_MASK 0x00002000
-#define BCHP_PCIE_0_INTR2_PCI_SET_PCIE_MSTR_CA_ATTN_SHIFT 13
-#define BCHP_PCIE_0_INTR2_PCI_SET_PCIE_MSTR_CA_ATTN_DEFAULT 0x00000000
-
-/* PCIE_0_INTR2 :: PCI_SET :: PCIE_MSTR_UR_ATTN [12:12] */
-#define BCHP_PCIE_0_INTR2_PCI_SET_PCIE_MSTR_UR_ATTN_MASK 0x00001000
-#define BCHP_PCIE_0_INTR2_PCI_SET_PCIE_MSTR_UR_ATTN_SHIFT 12
-#define BCHP_PCIE_0_INTR2_PCI_SET_PCIE_MSTR_UR_ATTN_DEFAULT 0x00000000
-
-/* PCIE_0_INTR2 :: PCI_SET :: UNASSIGNED_11 [11:11] */
-#define BCHP_PCIE_0_INTR2_PCI_SET_UNASSIGNED_11_MASK 0x00000800
-#define BCHP_PCIE_0_INTR2_PCI_SET_UNASSIGNED_11_SHIFT 11
-#define BCHP_PCIE_0_INTR2_PCI_SET_UNASSIGNED_11_DEFAULT 0x00000000
-
-/* PCIE_0_INTR2 :: PCI_SET :: UNASSIGNED_10 [10:10] */
-#define BCHP_PCIE_0_INTR2_PCI_SET_UNASSIGNED_10_MASK 0x00000400
-#define BCHP_PCIE_0_INTR2_PCI_SET_UNASSIGNED_10_SHIFT 10
-#define BCHP_PCIE_0_INTR2_PCI_SET_UNASSIGNED_10_DEFAULT 0x00000000
-
-/* PCIE_0_INTR2 :: PCI_SET :: PCIE_TGT_BAD_ACCESS [09:09] */
-#define BCHP_PCIE_0_INTR2_PCI_SET_PCIE_TGT_BAD_ACCESS_MASK 0x00000200
-#define BCHP_PCIE_0_INTR2_PCI_SET_PCIE_TGT_BAD_ACCESS_SHIFT 9
-#define BCHP_PCIE_0_INTR2_PCI_SET_PCIE_TGT_BAD_ACCESS_DEFAULT 0x00000000
-
-/* PCIE_0_INTR2 :: PCI_SET :: PCIE_TGT_BAD_ADDRESS [08:08] */
-#define BCHP_PCIE_0_INTR2_PCI_SET_PCIE_TGT_BAD_ADDRESS_MASK 0x00000100
-#define BCHP_PCIE_0_INTR2_PCI_SET_PCIE_TGT_BAD_ADDRESS_SHIFT 8
-#define BCHP_PCIE_0_INTR2_PCI_SET_PCIE_TGT_BAD_ADDRESS_DEFAULT 0x00000000
-
-/* PCIE_0_INTR2 :: PCI_SET :: L1_RX_DMA_ERR_INTR [07:07] */
-#define BCHP_PCIE_0_INTR2_PCI_SET_L1_RX_DMA_ERR_INTR_MASK 0x00000080
-#define BCHP_PCIE_0_INTR2_PCI_SET_L1_RX_DMA_ERR_INTR_SHIFT 7
-#define BCHP_PCIE_0_INTR2_PCI_SET_L1_RX_DMA_ERR_INTR_DEFAULT 0x00000000
-
-/* PCIE_0_INTR2 :: PCI_SET :: L1_RX_DMA_DONE_INTR [06:06] */
-#define BCHP_PCIE_0_INTR2_PCI_SET_L1_RX_DMA_DONE_INTR_MASK 0x00000040
-#define BCHP_PCIE_0_INTR2_PCI_SET_L1_RX_DMA_DONE_INTR_SHIFT 6
-#define BCHP_PCIE_0_INTR2_PCI_SET_L1_RX_DMA_DONE_INTR_DEFAULT 0x00000000
-
-/* PCIE_0_INTR2 :: PCI_SET :: L1_TX_DMA_ERR_INTR [05:05] */
-#define BCHP_PCIE_0_INTR2_PCI_SET_L1_TX_DMA_ERR_INTR_MASK 0x00000020
-#define BCHP_PCIE_0_INTR2_PCI_SET_L1_TX_DMA_ERR_INTR_SHIFT 5
-#define BCHP_PCIE_0_INTR2_PCI_SET_L1_TX_DMA_ERR_INTR_DEFAULT 0x00000000
-
-/* PCIE_0_INTR2 :: PCI_SET :: L1_TX_DMA_DONE_INTR [04:04] */
-#define BCHP_PCIE_0_INTR2_PCI_SET_L1_TX_DMA_DONE_INTR_MASK 0x00000010
-#define BCHP_PCIE_0_INTR2_PCI_SET_L1_TX_DMA_DONE_INTR_SHIFT 4
-#define BCHP_PCIE_0_INTR2_PCI_SET_L1_TX_DMA_DONE_INTR_DEFAULT 0x00000000
-
-/* PCIE_0_INTR2 :: PCI_SET :: L0_RX_DMA_ERR_INTR [03:03] */
-#define BCHP_PCIE_0_INTR2_PCI_SET_L0_RX_DMA_ERR_INTR_MASK 0x00000008
-#define BCHP_PCIE_0_INTR2_PCI_SET_L0_RX_DMA_ERR_INTR_SHIFT 3
-#define BCHP_PCIE_0_INTR2_PCI_SET_L0_RX_DMA_ERR_INTR_DEFAULT 0x00000000
-
-/* PCIE_0_INTR2 :: PCI_SET :: L0_RX_DMA_DONE_INTR [02:02] */
-#define BCHP_PCIE_0_INTR2_PCI_SET_L0_RX_DMA_DONE_INTR_MASK 0x00000004
-#define BCHP_PCIE_0_INTR2_PCI_SET_L0_RX_DMA_DONE_INTR_SHIFT 2
-#define BCHP_PCIE_0_INTR2_PCI_SET_L0_RX_DMA_DONE_INTR_DEFAULT 0x00000000
-
-/* PCIE_0_INTR2 :: PCI_SET :: L0_TX_DMA_ERR_INTR [01:01] */
-#define BCHP_PCIE_0_INTR2_PCI_SET_L0_TX_DMA_ERR_INTR_MASK 0x00000002
-#define BCHP_PCIE_0_INTR2_PCI_SET_L0_TX_DMA_ERR_INTR_SHIFT 1
-#define BCHP_PCIE_0_INTR2_PCI_SET_L0_TX_DMA_ERR_INTR_DEFAULT 0x00000000
-
-/* PCIE_0_INTR2 :: PCI_SET :: L0_TX_DMA_DONE_INTR [00:00] */
-#define BCHP_PCIE_0_INTR2_PCI_SET_L0_TX_DMA_DONE_INTR_MASK 0x00000001
-#define BCHP_PCIE_0_INTR2_PCI_SET_L0_TX_DMA_DONE_INTR_SHIFT 0
-#define BCHP_PCIE_0_INTR2_PCI_SET_L0_TX_DMA_DONE_INTR_DEFAULT 0x00000000
-
-/***************************************************************************
- *PCI_CLEAR - PCI interrupt Clear Register
- ***************************************************************************/
-/* PCIE_0_INTR2 :: PCI_CLEAR :: MSI_INTR07 [31:31] */
-#define BCHP_PCIE_0_INTR2_PCI_CLEAR_MSI_INTR07_MASK 0x80000000
-#define BCHP_PCIE_0_INTR2_PCI_CLEAR_MSI_INTR07_SHIFT 31
-#define BCHP_PCIE_0_INTR2_PCI_CLEAR_MSI_INTR07_DEFAULT 0x00000000
-
-/* PCIE_0_INTR2 :: PCI_CLEAR :: MSI_INTR06 [30:30] */
-#define BCHP_PCIE_0_INTR2_PCI_CLEAR_MSI_INTR06_MASK 0x40000000
-#define BCHP_PCIE_0_INTR2_PCI_CLEAR_MSI_INTR06_SHIFT 30
-#define BCHP_PCIE_0_INTR2_PCI_CLEAR_MSI_INTR06_DEFAULT 0x00000000
-
-/* PCIE_0_INTR2 :: PCI_CLEAR :: MSI_INTR05 [29:29] */
-#define BCHP_PCIE_0_INTR2_PCI_CLEAR_MSI_INTR05_MASK 0x20000000
-#define BCHP_PCIE_0_INTR2_PCI_CLEAR_MSI_INTR05_SHIFT 29
-#define BCHP_PCIE_0_INTR2_PCI_CLEAR_MSI_INTR05_DEFAULT 0x00000000
-
-/* PCIE_0_INTR2 :: PCI_CLEAR :: MSI_INTR04 [28:28] */
-#define BCHP_PCIE_0_INTR2_PCI_CLEAR_MSI_INTR04_MASK 0x10000000
-#define BCHP_PCIE_0_INTR2_PCI_CLEAR_MSI_INTR04_SHIFT 28
-#define BCHP_PCIE_0_INTR2_PCI_CLEAR_MSI_INTR04_DEFAULT 0x00000000
-
-/* PCIE_0_INTR2 :: PCI_CLEAR :: MSI_INTR03 [27:27] */
-#define BCHP_PCIE_0_INTR2_PCI_CLEAR_MSI_INTR03_MASK 0x08000000
-#define BCHP_PCIE_0_INTR2_PCI_CLEAR_MSI_INTR03_SHIFT 27
-#define BCHP_PCIE_0_INTR2_PCI_CLEAR_MSI_INTR03_DEFAULT 0x00000000
-
-/* PCIE_0_INTR2 :: PCI_CLEAR :: MSI_INTR02 [26:26] */
-#define BCHP_PCIE_0_INTR2_PCI_CLEAR_MSI_INTR02_MASK 0x04000000
-#define BCHP_PCIE_0_INTR2_PCI_CLEAR_MSI_INTR02_SHIFT 26
-#define BCHP_PCIE_0_INTR2_PCI_CLEAR_MSI_INTR02_DEFAULT 0x00000000
-
-/* PCIE_0_INTR2 :: PCI_CLEAR :: MSI_INTR01 [25:25] */
-#define BCHP_PCIE_0_INTR2_PCI_CLEAR_MSI_INTR01_MASK 0x02000000
-#define BCHP_PCIE_0_INTR2_PCI_CLEAR_MSI_INTR01_SHIFT 25
-#define BCHP_PCIE_0_INTR2_PCI_CLEAR_MSI_INTR01_DEFAULT 0x00000000
-
-/* PCIE_0_INTR2 :: PCI_CLEAR :: MSI_INTR00 [24:24] */
-#define BCHP_PCIE_0_INTR2_PCI_CLEAR_MSI_INTR00_MASK 0x01000000
-#define BCHP_PCIE_0_INTR2_PCI_CLEAR_MSI_INTR00_SHIFT 24
-#define BCHP_PCIE_0_INTR2_PCI_CLEAR_MSI_INTR00_DEFAULT 0x00000000
-
-/* PCIE_0_INTR2 :: PCI_CLEAR :: UNASSIGNED_23 [23:23] */
-#define BCHP_PCIE_0_INTR2_PCI_CLEAR_UNASSIGNED_23_MASK 0x00800000
-#define BCHP_PCIE_0_INTR2_PCI_CLEAR_UNASSIGNED_23_SHIFT 23
-#define BCHP_PCIE_0_INTR2_PCI_CLEAR_UNASSIGNED_23_DEFAULT 0x00000000
-
-/* PCIE_0_INTR2 :: PCI_CLEAR :: UNASSIGNED_22 [22:22] */
-#define BCHP_PCIE_0_INTR2_PCI_CLEAR_UNASSIGNED_22_MASK 0x00400000
-#define BCHP_PCIE_0_INTR2_PCI_CLEAR_UNASSIGNED_22_SHIFT 22
-#define BCHP_PCIE_0_INTR2_PCI_CLEAR_UNASSIGNED_22_DEFAULT 0x00000000
-
-/* PCIE_0_INTR2 :: PCI_CLEAR :: UNASSIGNED_21 [21:21] */
-#define BCHP_PCIE_0_INTR2_PCI_CLEAR_UNASSIGNED_21_MASK 0x00200000
-#define BCHP_PCIE_0_INTR2_PCI_CLEAR_UNASSIGNED_21_SHIFT 21
-#define BCHP_PCIE_0_INTR2_PCI_CLEAR_UNASSIGNED_21_DEFAULT 0x00000000
-
-/* PCIE_0_INTR2 :: PCI_CLEAR :: UNASSIGNED_20 [20:20] */
-#define BCHP_PCIE_0_INTR2_PCI_CLEAR_UNASSIGNED_20_MASK 0x00100000
-#define BCHP_PCIE_0_INTR2_PCI_CLEAR_UNASSIGNED_20_SHIFT 20
-#define BCHP_PCIE_0_INTR2_PCI_CLEAR_UNASSIGNED_20_DEFAULT 0x00000000
-
-/* PCIE_0_INTR2 :: PCI_CLEAR :: MAILBOX_3 [19:19] */
-#define BCHP_PCIE_0_INTR2_PCI_CLEAR_MAILBOX_3_MASK 0x00080000
-#define BCHP_PCIE_0_INTR2_PCI_CLEAR_MAILBOX_3_SHIFT 19
-#define BCHP_PCIE_0_INTR2_PCI_CLEAR_MAILBOX_3_DEFAULT 0x00000000
-
-/* PCIE_0_INTR2 :: PCI_CLEAR :: MAILBOX_2 [18:18] */
-#define BCHP_PCIE_0_INTR2_PCI_CLEAR_MAILBOX_2_MASK 0x00040000
-#define BCHP_PCIE_0_INTR2_PCI_CLEAR_MAILBOX_2_SHIFT 18
-#define BCHP_PCIE_0_INTR2_PCI_CLEAR_MAILBOX_2_DEFAULT 0x00000000
-
-/* PCIE_0_INTR2 :: PCI_CLEAR :: MAILBOX_1 [17:17] */
-#define BCHP_PCIE_0_INTR2_PCI_CLEAR_MAILBOX_1_MASK 0x00020000
-#define BCHP_PCIE_0_INTR2_PCI_CLEAR_MAILBOX_1_SHIFT 17
-#define BCHP_PCIE_0_INTR2_PCI_CLEAR_MAILBOX_1_DEFAULT 0x00000000
-
-/* PCIE_0_INTR2 :: PCI_CLEAR :: MAILBOX_0 [16:16] */
-#define BCHP_PCIE_0_INTR2_PCI_CLEAR_MAILBOX_0_MASK 0x00010000
-#define BCHP_PCIE_0_INTR2_PCI_CLEAR_MAILBOX_0_SHIFT 16
-#define BCHP_PCIE_0_INTR2_PCI_CLEAR_MAILBOX_0_DEFAULT 0x00000000
-
-/* PCIE_0_INTR2 :: PCI_CLEAR :: PCIE_MSTR_FWD_ERR [15:15] */
-#define BCHP_PCIE_0_INTR2_PCI_CLEAR_PCIE_MSTR_FWD_ERR_MASK 0x00008000
-#define BCHP_PCIE_0_INTR2_PCI_CLEAR_PCIE_MSTR_FWD_ERR_SHIFT 15
-#define BCHP_PCIE_0_INTR2_PCI_CLEAR_PCIE_MSTR_FWD_ERR_DEFAULT 0x00000000
-
-/* PCIE_0_INTR2 :: PCI_CLEAR :: PCIE_MSTR_RETRY_TIMEOUT [14:14] */
-#define BCHP_PCIE_0_INTR2_PCI_CLEAR_PCIE_MSTR_RETRY_TIMEOUT_MASK 0x00004000
-#define BCHP_PCIE_0_INTR2_PCI_CLEAR_PCIE_MSTR_RETRY_TIMEOUT_SHIFT 14
-#define BCHP_PCIE_0_INTR2_PCI_CLEAR_PCIE_MSTR_RETRY_TIMEOUT_DEFAULT 0x00000000
-
-/* PCIE_0_INTR2 :: PCI_CLEAR :: PCIE_MSTR_CA_ATTN [13:13] */
-#define BCHP_PCIE_0_INTR2_PCI_CLEAR_PCIE_MSTR_CA_ATTN_MASK 0x00002000
-#define BCHP_PCIE_0_INTR2_PCI_CLEAR_PCIE_MSTR_CA_ATTN_SHIFT 13
-#define BCHP_PCIE_0_INTR2_PCI_CLEAR_PCIE_MSTR_CA_ATTN_DEFAULT 0x00000000
-
-/* PCIE_0_INTR2 :: PCI_CLEAR :: PCIE_MSTR_UR_ATTN [12:12] */
-#define BCHP_PCIE_0_INTR2_PCI_CLEAR_PCIE_MSTR_UR_ATTN_MASK 0x00001000
-#define BCHP_PCIE_0_INTR2_PCI_CLEAR_PCIE_MSTR_UR_ATTN_SHIFT 12
-#define BCHP_PCIE_0_INTR2_PCI_CLEAR_PCIE_MSTR_UR_ATTN_DEFAULT 0x00000000
-
-/* PCIE_0_INTR2 :: PCI_CLEAR :: UNASSIGNED_11 [11:11] */
-#define BCHP_PCIE_0_INTR2_PCI_CLEAR_UNASSIGNED_11_MASK 0x00000800
-#define BCHP_PCIE_0_INTR2_PCI_CLEAR_UNASSIGNED_11_SHIFT 11
-#define BCHP_PCIE_0_INTR2_PCI_CLEAR_UNASSIGNED_11_DEFAULT 0x00000000
-
-/* PCIE_0_INTR2 :: PCI_CLEAR :: UNASSIGNED_10 [10:10] */
-#define BCHP_PCIE_0_INTR2_PCI_CLEAR_UNASSIGNED_10_MASK 0x00000400
-#define BCHP_PCIE_0_INTR2_PCI_CLEAR_UNASSIGNED_10_SHIFT 10
-#define BCHP_PCIE_0_INTR2_PCI_CLEAR_UNASSIGNED_10_DEFAULT 0x00000000
-
-/* PCIE_0_INTR2 :: PCI_CLEAR :: PCIE_TGT_BAD_ACCESS [09:09] */
-#define BCHP_PCIE_0_INTR2_PCI_CLEAR_PCIE_TGT_BAD_ACCESS_MASK 0x00000200
-#define BCHP_PCIE_0_INTR2_PCI_CLEAR_PCIE_TGT_BAD_ACCESS_SHIFT 9
-#define BCHP_PCIE_0_INTR2_PCI_CLEAR_PCIE_TGT_BAD_ACCESS_DEFAULT 0x00000000
-
-/* PCIE_0_INTR2 :: PCI_CLEAR :: PCIE_TGT_BAD_ADDRESS [08:08] */
-#define BCHP_PCIE_0_INTR2_PCI_CLEAR_PCIE_TGT_BAD_ADDRESS_MASK 0x00000100
-#define BCHP_PCIE_0_INTR2_PCI_CLEAR_PCIE_TGT_BAD_ADDRESS_SHIFT 8
-#define BCHP_PCIE_0_INTR2_PCI_CLEAR_PCIE_TGT_BAD_ADDRESS_DEFAULT 0x00000000
-
-/* PCIE_0_INTR2 :: PCI_CLEAR :: L1_RX_DMA_ERR_INTR [07:07] */
-#define BCHP_PCIE_0_INTR2_PCI_CLEAR_L1_RX_DMA_ERR_INTR_MASK 0x00000080
-#define BCHP_PCIE_0_INTR2_PCI_CLEAR_L1_RX_DMA_ERR_INTR_SHIFT 7
-#define BCHP_PCIE_0_INTR2_PCI_CLEAR_L1_RX_DMA_ERR_INTR_DEFAULT 0x00000000
-
-/* PCIE_0_INTR2 :: PCI_CLEAR :: L1_RX_DMA_DONE_INTR [06:06] */
-#define BCHP_PCIE_0_INTR2_PCI_CLEAR_L1_RX_DMA_DONE_INTR_MASK 0x00000040
-#define BCHP_PCIE_0_INTR2_PCI_CLEAR_L1_RX_DMA_DONE_INTR_SHIFT 6
-#define BCHP_PCIE_0_INTR2_PCI_CLEAR_L1_RX_DMA_DONE_INTR_DEFAULT 0x00000000
-
-/* PCIE_0_INTR2 :: PCI_CLEAR :: L1_TX_DMA_ERR_INTR [05:05] */
-#define BCHP_PCIE_0_INTR2_PCI_CLEAR_L1_TX_DMA_ERR_INTR_MASK 0x00000020
-#define BCHP_PCIE_0_INTR2_PCI_CLEAR_L1_TX_DMA_ERR_INTR_SHIFT 5
-#define BCHP_PCIE_0_INTR2_PCI_CLEAR_L1_TX_DMA_ERR_INTR_DEFAULT 0x00000000
-
-/* PCIE_0_INTR2 :: PCI_CLEAR :: L1_TX_DMA_DONE_INTR [04:04] */
-#define BCHP_PCIE_0_INTR2_PCI_CLEAR_L1_TX_DMA_DONE_INTR_MASK 0x00000010
-#define BCHP_PCIE_0_INTR2_PCI_CLEAR_L1_TX_DMA_DONE_INTR_SHIFT 4
-#define BCHP_PCIE_0_INTR2_PCI_CLEAR_L1_TX_DMA_DONE_INTR_DEFAULT 0x00000000
-
-/* PCIE_0_INTR2 :: PCI_CLEAR :: L0_RX_DMA_ERR_INTR [03:03] */
-#define BCHP_PCIE_0_INTR2_PCI_CLEAR_L0_RX_DMA_ERR_INTR_MASK 0x00000008
-#define BCHP_PCIE_0_INTR2_PCI_CLEAR_L0_RX_DMA_ERR_INTR_SHIFT 3
-#define BCHP_PCIE_0_INTR2_PCI_CLEAR_L0_RX_DMA_ERR_INTR_DEFAULT 0x00000000
-
-/* PCIE_0_INTR2 :: PCI_CLEAR :: L0_RX_DMA_DONE_INTR [02:02] */
-#define BCHP_PCIE_0_INTR2_PCI_CLEAR_L0_RX_DMA_DONE_INTR_MASK 0x00000004
-#define BCHP_PCIE_0_INTR2_PCI_CLEAR_L0_RX_DMA_DONE_INTR_SHIFT 2
-#define BCHP_PCIE_0_INTR2_PCI_CLEAR_L0_RX_DMA_DONE_INTR_DEFAULT 0x00000000
-
-/* PCIE_0_INTR2 :: PCI_CLEAR :: L0_TX_DMA_ERR_INTR [01:01] */
-#define BCHP_PCIE_0_INTR2_PCI_CLEAR_L0_TX_DMA_ERR_INTR_MASK 0x00000002
-#define BCHP_PCIE_0_INTR2_PCI_CLEAR_L0_TX_DMA_ERR_INTR_SHIFT 1
-#define BCHP_PCIE_0_INTR2_PCI_CLEAR_L0_TX_DMA_ERR_INTR_DEFAULT 0x00000000
-
-/* PCIE_0_INTR2 :: PCI_CLEAR :: L0_TX_DMA_DONE_INTR [00:00] */
-#define BCHP_PCIE_0_INTR2_PCI_CLEAR_L0_TX_DMA_DONE_INTR_MASK 0x00000001
-#define BCHP_PCIE_0_INTR2_PCI_CLEAR_L0_TX_DMA_DONE_INTR_SHIFT 0
-#define BCHP_PCIE_0_INTR2_PCI_CLEAR_L0_TX_DMA_DONE_INTR_DEFAULT 0x00000000
-
-/***************************************************************************
- *PCI_MASK_STATUS - PCI interrupt Mask Status Register
- ***************************************************************************/
-/* PCIE_0_INTR2 :: PCI_MASK_STATUS :: MSI_INTR07 [31:31] */
-#define BCHP_PCIE_0_INTR2_PCI_MASK_STATUS_MSI_INTR07_MASK 0x80000000
-#define BCHP_PCIE_0_INTR2_PCI_MASK_STATUS_MSI_INTR07_SHIFT 31
-#define BCHP_PCIE_0_INTR2_PCI_MASK_STATUS_MSI_INTR07_DEFAULT 0x00000001
-
-/* PCIE_0_INTR2 :: PCI_MASK_STATUS :: MSI_INTR06 [30:30] */
-#define BCHP_PCIE_0_INTR2_PCI_MASK_STATUS_MSI_INTR06_MASK 0x40000000
-#define BCHP_PCIE_0_INTR2_PCI_MASK_STATUS_MSI_INTR06_SHIFT 30
-#define BCHP_PCIE_0_INTR2_PCI_MASK_STATUS_MSI_INTR06_DEFAULT 0x00000001
-
-/* PCIE_0_INTR2 :: PCI_MASK_STATUS :: MSI_INTR05 [29:29] */
-#define BCHP_PCIE_0_INTR2_PCI_MASK_STATUS_MSI_INTR05_MASK 0x20000000
-#define BCHP_PCIE_0_INTR2_PCI_MASK_STATUS_MSI_INTR05_SHIFT 29
-#define BCHP_PCIE_0_INTR2_PCI_MASK_STATUS_MSI_INTR05_DEFAULT 0x00000001
-
-/* PCIE_0_INTR2 :: PCI_MASK_STATUS :: MSI_INTR04 [28:28] */
-#define BCHP_PCIE_0_INTR2_PCI_MASK_STATUS_MSI_INTR04_MASK 0x10000000
-#define BCHP_PCIE_0_INTR2_PCI_MASK_STATUS_MSI_INTR04_SHIFT 28
-#define BCHP_PCIE_0_INTR2_PCI_MASK_STATUS_MSI_INTR04_DEFAULT 0x00000001
-
-/* PCIE_0_INTR2 :: PCI_MASK_STATUS :: MSI_INTR03 [27:27] */
-#define BCHP_PCIE_0_INTR2_PCI_MASK_STATUS_MSI_INTR03_MASK 0x08000000
-#define BCHP_PCIE_0_INTR2_PCI_MASK_STATUS_MSI_INTR03_SHIFT 27
-#define BCHP_PCIE_0_INTR2_PCI_MASK_STATUS_MSI_INTR03_DEFAULT 0x00000001
-
-/* PCIE_0_INTR2 :: PCI_MASK_STATUS :: MSI_INTR02 [26:26] */
-#define BCHP_PCIE_0_INTR2_PCI_MASK_STATUS_MSI_INTR02_MASK 0x04000000
-#define BCHP_PCIE_0_INTR2_PCI_MASK_STATUS_MSI_INTR02_SHIFT 26
-#define BCHP_PCIE_0_INTR2_PCI_MASK_STATUS_MSI_INTR02_DEFAULT 0x00000001
-
-/* PCIE_0_INTR2 :: PCI_MASK_STATUS :: MSI_INTR01 [25:25] */
-#define BCHP_PCIE_0_INTR2_PCI_MASK_STATUS_MSI_INTR01_MASK 0x02000000
-#define BCHP_PCIE_0_INTR2_PCI_MASK_STATUS_MSI_INTR01_SHIFT 25
-#define BCHP_PCIE_0_INTR2_PCI_MASK_STATUS_MSI_INTR01_DEFAULT 0x00000001
-
-/* PCIE_0_INTR2 :: PCI_MASK_STATUS :: MSI_INTR00 [24:24] */
-#define BCHP_PCIE_0_INTR2_PCI_MASK_STATUS_MSI_INTR00_MASK 0x01000000
-#define BCHP_PCIE_0_INTR2_PCI_MASK_STATUS_MSI_INTR00_SHIFT 24
-#define BCHP_PCIE_0_INTR2_PCI_MASK_STATUS_MSI_INTR00_DEFAULT 0x00000001
-
-/* PCIE_0_INTR2 :: PCI_MASK_STATUS :: UNASSIGNED_23 [23:23] */
-#define BCHP_PCIE_0_INTR2_PCI_MASK_STATUS_UNASSIGNED_23_MASK 0x00800000
-#define BCHP_PCIE_0_INTR2_PCI_MASK_STATUS_UNASSIGNED_23_SHIFT 23
-#define BCHP_PCIE_0_INTR2_PCI_MASK_STATUS_UNASSIGNED_23_DEFAULT 0x00000001
-
-/* PCIE_0_INTR2 :: PCI_MASK_STATUS :: UNASSIGNED_22 [22:22] */
-#define BCHP_PCIE_0_INTR2_PCI_MASK_STATUS_UNASSIGNED_22_MASK 0x00400000
-#define BCHP_PCIE_0_INTR2_PCI_MASK_STATUS_UNASSIGNED_22_SHIFT 22
-#define BCHP_PCIE_0_INTR2_PCI_MASK_STATUS_UNASSIGNED_22_DEFAULT 0x00000001
-
-/* PCIE_0_INTR2 :: PCI_MASK_STATUS :: UNASSIGNED_21 [21:21] */
-#define BCHP_PCIE_0_INTR2_PCI_MASK_STATUS_UNASSIGNED_21_MASK 0x00200000
-#define BCHP_PCIE_0_INTR2_PCI_MASK_STATUS_UNASSIGNED_21_SHIFT 21
-#define BCHP_PCIE_0_INTR2_PCI_MASK_STATUS_UNASSIGNED_21_DEFAULT 0x00000001
-
-/* PCIE_0_INTR2 :: PCI_MASK_STATUS :: UNASSIGNED_20 [20:20] */
-#define BCHP_PCIE_0_INTR2_PCI_MASK_STATUS_UNASSIGNED_20_MASK 0x00100000
-#define BCHP_PCIE_0_INTR2_PCI_MASK_STATUS_UNASSIGNED_20_SHIFT 20
-#define BCHP_PCIE_0_INTR2_PCI_MASK_STATUS_UNASSIGNED_20_DEFAULT 0x00000001
-
-/* PCIE_0_INTR2 :: PCI_MASK_STATUS :: MAILBOX_3 [19:19] */
-#define BCHP_PCIE_0_INTR2_PCI_MASK_STATUS_MAILBOX_3_MASK 0x00080000
-#define BCHP_PCIE_0_INTR2_PCI_MASK_STATUS_MAILBOX_3_SHIFT 19
-#define BCHP_PCIE_0_INTR2_PCI_MASK_STATUS_MAILBOX_3_DEFAULT 0x00000001
-
-/* PCIE_0_INTR2 :: PCI_MASK_STATUS :: MAILBOX_2 [18:18] */
-#define BCHP_PCIE_0_INTR2_PCI_MASK_STATUS_MAILBOX_2_MASK 0x00040000
-#define BCHP_PCIE_0_INTR2_PCI_MASK_STATUS_MAILBOX_2_SHIFT 18
-#define BCHP_PCIE_0_INTR2_PCI_MASK_STATUS_MAILBOX_2_DEFAULT 0x00000001
-
-/* PCIE_0_INTR2 :: PCI_MASK_STATUS :: MAILBOX_1 [17:17] */
-#define BCHP_PCIE_0_INTR2_PCI_MASK_STATUS_MAILBOX_1_MASK 0x00020000
-#define BCHP_PCIE_0_INTR2_PCI_MASK_STATUS_MAILBOX_1_SHIFT 17
-#define BCHP_PCIE_0_INTR2_PCI_MASK_STATUS_MAILBOX_1_DEFAULT 0x00000001
-
-/* PCIE_0_INTR2 :: PCI_MASK_STATUS :: MAILBOX_0 [16:16] */
-#define BCHP_PCIE_0_INTR2_PCI_MASK_STATUS_MAILBOX_0_MASK 0x00010000
-#define BCHP_PCIE_0_INTR2_PCI_MASK_STATUS_MAILBOX_0_SHIFT 16
-#define BCHP_PCIE_0_INTR2_PCI_MASK_STATUS_MAILBOX_0_DEFAULT 0x00000001
-
-/* PCIE_0_INTR2 :: PCI_MASK_STATUS :: PCIE_MSTR_FWD_ERR [15:15] */
-#define BCHP_PCIE_0_INTR2_PCI_MASK_STATUS_PCIE_MSTR_FWD_ERR_MASK 0x00008000
-#define BCHP_PCIE_0_INTR2_PCI_MASK_STATUS_PCIE_MSTR_FWD_ERR_SHIFT 15
-#define BCHP_PCIE_0_INTR2_PCI_MASK_STATUS_PCIE_MSTR_FWD_ERR_DEFAULT 0x00000001
-
-/* PCIE_0_INTR2 :: PCI_MASK_STATUS :: PCIE_MSTR_RETRY_TIMEOUT [14:14] */
-#define BCHP_PCIE_0_INTR2_PCI_MASK_STATUS_PCIE_MSTR_RETRY_TIMEOUT_MASK 0x00004000
-#define BCHP_PCIE_0_INTR2_PCI_MASK_STATUS_PCIE_MSTR_RETRY_TIMEOUT_SHIFT 14
-#define BCHP_PCIE_0_INTR2_PCI_MASK_STATUS_PCIE_MSTR_RETRY_TIMEOUT_DEFAULT 0x00000001
-
-/* PCIE_0_INTR2 :: PCI_MASK_STATUS :: PCIE_MSTR_CA_ATTN [13:13] */
-#define BCHP_PCIE_0_INTR2_PCI_MASK_STATUS_PCIE_MSTR_CA_ATTN_MASK 0x00002000
-#define BCHP_PCIE_0_INTR2_PCI_MASK_STATUS_PCIE_MSTR_CA_ATTN_SHIFT 13
-#define BCHP_PCIE_0_INTR2_PCI_MASK_STATUS_PCIE_MSTR_CA_ATTN_DEFAULT 0x00000001
-
-/* PCIE_0_INTR2 :: PCI_MASK_STATUS :: PCIE_MSTR_UR_ATTN [12:12] */
-#define BCHP_PCIE_0_INTR2_PCI_MASK_STATUS_PCIE_MSTR_UR_ATTN_MASK 0x00001000
-#define BCHP_PCIE_0_INTR2_PCI_MASK_STATUS_PCIE_MSTR_UR_ATTN_SHIFT 12
-#define BCHP_PCIE_0_INTR2_PCI_MASK_STATUS_PCIE_MSTR_UR_ATTN_DEFAULT 0x00000001
-
-/* PCIE_0_INTR2 :: PCI_MASK_STATUS :: UNASSIGNED_11 [11:11] */
-#define BCHP_PCIE_0_INTR2_PCI_MASK_STATUS_UNASSIGNED_11_MASK 0x00000800
-#define BCHP_PCIE_0_INTR2_PCI_MASK_STATUS_UNASSIGNED_11_SHIFT 11
-#define BCHP_PCIE_0_INTR2_PCI_MASK_STATUS_UNASSIGNED_11_DEFAULT 0x00000001
-
-/* PCIE_0_INTR2 :: PCI_MASK_STATUS :: UNASSIGNED_10 [10:10] */
-#define BCHP_PCIE_0_INTR2_PCI_MASK_STATUS_UNASSIGNED_10_MASK 0x00000400
-#define BCHP_PCIE_0_INTR2_PCI_MASK_STATUS_UNASSIGNED_10_SHIFT 10
-#define BCHP_PCIE_0_INTR2_PCI_MASK_STATUS_UNASSIGNED_10_DEFAULT 0x00000001
-
-/* PCIE_0_INTR2 :: PCI_MASK_STATUS :: PCIE_TGT_BAD_ACCESS [09:09] */
-#define BCHP_PCIE_0_INTR2_PCI_MASK_STATUS_PCIE_TGT_BAD_ACCESS_MASK 0x00000200
-#define BCHP_PCIE_0_INTR2_PCI_MASK_STATUS_PCIE_TGT_BAD_ACCESS_SHIFT 9
-#define BCHP_PCIE_0_INTR2_PCI_MASK_STATUS_PCIE_TGT_BAD_ACCESS_DEFAULT 0x00000001
-
-/* PCIE_0_INTR2 :: PCI_MASK_STATUS :: PCIE_TGT_BAD_ADDRESS [08:08] */
-#define BCHP_PCIE_0_INTR2_PCI_MASK_STATUS_PCIE_TGT_BAD_ADDRESS_MASK 0x00000100
-#define BCHP_PCIE_0_INTR2_PCI_MASK_STATUS_PCIE_TGT_BAD_ADDRESS_SHIFT 8
-#define BCHP_PCIE_0_INTR2_PCI_MASK_STATUS_PCIE_TGT_BAD_ADDRESS_DEFAULT 0x00000001
-
-/* PCIE_0_INTR2 :: PCI_MASK_STATUS :: L1_RX_DMA_ERR_INTR [07:07] */
-#define BCHP_PCIE_0_INTR2_PCI_MASK_STATUS_L1_RX_DMA_ERR_INTR_MASK 0x00000080
-#define BCHP_PCIE_0_INTR2_PCI_MASK_STATUS_L1_RX_DMA_ERR_INTR_SHIFT 7
-#define BCHP_PCIE_0_INTR2_PCI_MASK_STATUS_L1_RX_DMA_ERR_INTR_DEFAULT 0x00000001
-
-/* PCIE_0_INTR2 :: PCI_MASK_STATUS :: L1_RX_DMA_DONE_INTR [06:06] */
-#define BCHP_PCIE_0_INTR2_PCI_MASK_STATUS_L1_RX_DMA_DONE_INTR_MASK 0x00000040
-#define BCHP_PCIE_0_INTR2_PCI_MASK_STATUS_L1_RX_DMA_DONE_INTR_SHIFT 6
-#define BCHP_PCIE_0_INTR2_PCI_MASK_STATUS_L1_RX_DMA_DONE_INTR_DEFAULT 0x00000001
-
-/* PCIE_0_INTR2 :: PCI_MASK_STATUS :: L1_TX_DMA_ERR_INTR [05:05] */
-#define BCHP_PCIE_0_INTR2_PCI_MASK_STATUS_L1_TX_DMA_ERR_INTR_MASK 0x00000020
-#define BCHP_PCIE_0_INTR2_PCI_MASK_STATUS_L1_TX_DMA_ERR_INTR_SHIFT 5
-#define BCHP_PCIE_0_INTR2_PCI_MASK_STATUS_L1_TX_DMA_ERR_INTR_DEFAULT 0x00000001
-
-/* PCIE_0_INTR2 :: PCI_MASK_STATUS :: L1_TX_DMA_DONE_INTR [04:04] */
-#define BCHP_PCIE_0_INTR2_PCI_MASK_STATUS_L1_TX_DMA_DONE_INTR_MASK 0x00000010
-#define BCHP_PCIE_0_INTR2_PCI_MASK_STATUS_L1_TX_DMA_DONE_INTR_SHIFT 4
-#define BCHP_PCIE_0_INTR2_PCI_MASK_STATUS_L1_TX_DMA_DONE_INTR_DEFAULT 0x00000001
-
-/* PCIE_0_INTR2 :: PCI_MASK_STATUS :: L0_RX_DMA_ERR_INTR [03:03] */
-#define BCHP_PCIE_0_INTR2_PCI_MASK_STATUS_L0_RX_DMA_ERR_INTR_MASK 0x00000008
-#define BCHP_PCIE_0_INTR2_PCI_MASK_STATUS_L0_RX_DMA_ERR_INTR_SHIFT 3
-#define BCHP_PCIE_0_INTR2_PCI_MASK_STATUS_L0_RX_DMA_ERR_INTR_DEFAULT 0x00000001
-
-/* PCIE_0_INTR2 :: PCI_MASK_STATUS :: L0_RX_DMA_DONE_INTR [02:02] */
-#define BCHP_PCIE_0_INTR2_PCI_MASK_STATUS_L0_RX_DMA_DONE_INTR_MASK 0x00000004
-#define BCHP_PCIE_0_INTR2_PCI_MASK_STATUS_L0_RX_DMA_DONE_INTR_SHIFT 2
-#define BCHP_PCIE_0_INTR2_PCI_MASK_STATUS_L0_RX_DMA_DONE_INTR_DEFAULT 0x00000001
-
-/* PCIE_0_INTR2 :: PCI_MASK_STATUS :: L0_TX_DMA_ERR_INTR [01:01] */
-#define BCHP_PCIE_0_INTR2_PCI_MASK_STATUS_L0_TX_DMA_ERR_INTR_MASK 0x00000002
-#define BCHP_PCIE_0_INTR2_PCI_MASK_STATUS_L0_TX_DMA_ERR_INTR_SHIFT 1
-#define BCHP_PCIE_0_INTR2_PCI_MASK_STATUS_L0_TX_DMA_ERR_INTR_DEFAULT 0x00000001
-
-/* PCIE_0_INTR2 :: PCI_MASK_STATUS :: L0_TX_DMA_DONE_INTR [00:00] */
-#define BCHP_PCIE_0_INTR2_PCI_MASK_STATUS_L0_TX_DMA_DONE_INTR_MASK 0x00000001
-#define BCHP_PCIE_0_INTR2_PCI_MASK_STATUS_L0_TX_DMA_DONE_INTR_SHIFT 0
-#define BCHP_PCIE_0_INTR2_PCI_MASK_STATUS_L0_TX_DMA_DONE_INTR_DEFAULT 0x00000001
-
-/***************************************************************************
- *PCI_MASK_SET - PCI interrupt Mask Set Register
- ***************************************************************************/
-/* PCIE_0_INTR2 :: PCI_MASK_SET :: MSI_INTR07 [31:31] */
-#define BCHP_PCIE_0_INTR2_PCI_MASK_SET_MSI_INTR07_MASK 0x80000000
-#define BCHP_PCIE_0_INTR2_PCI_MASK_SET_MSI_INTR07_SHIFT 31
-#define BCHP_PCIE_0_INTR2_PCI_MASK_SET_MSI_INTR07_DEFAULT 0x00000001
-
-/* PCIE_0_INTR2 :: PCI_MASK_SET :: MSI_INTR06 [30:30] */
-#define BCHP_PCIE_0_INTR2_PCI_MASK_SET_MSI_INTR06_MASK 0x40000000
-#define BCHP_PCIE_0_INTR2_PCI_MASK_SET_MSI_INTR06_SHIFT 30
-#define BCHP_PCIE_0_INTR2_PCI_MASK_SET_MSI_INTR06_DEFAULT 0x00000001
-
-/* PCIE_0_INTR2 :: PCI_MASK_SET :: MSI_INTR05 [29:29] */
-#define BCHP_PCIE_0_INTR2_PCI_MASK_SET_MSI_INTR05_MASK 0x20000000
-#define BCHP_PCIE_0_INTR2_PCI_MASK_SET_MSI_INTR05_SHIFT 29
-#define BCHP_PCIE_0_INTR2_PCI_MASK_SET_MSI_INTR05_DEFAULT 0x00000001
-
-/* PCIE_0_INTR2 :: PCI_MASK_SET :: MSI_INTR04 [28:28] */
-#define BCHP_PCIE_0_INTR2_PCI_MASK_SET_MSI_INTR04_MASK 0x10000000
-#define BCHP_PCIE_0_INTR2_PCI_MASK_SET_MSI_INTR04_SHIFT 28
-#define BCHP_PCIE_0_INTR2_PCI_MASK_SET_MSI_INTR04_DEFAULT 0x00000001
-
-/* PCIE_0_INTR2 :: PCI_MASK_SET :: MSI_INTR03 [27:27] */
-#define BCHP_PCIE_0_INTR2_PCI_MASK_SET_MSI_INTR03_MASK 0x08000000
-#define BCHP_PCIE_0_INTR2_PCI_MASK_SET_MSI_INTR03_SHIFT 27
-#define BCHP_PCIE_0_INTR2_PCI_MASK_SET_MSI_INTR03_DEFAULT 0x00000001
-
-/* PCIE_0_INTR2 :: PCI_MASK_SET :: MSI_INTR02 [26:26] */
-#define BCHP_PCIE_0_INTR2_PCI_MASK_SET_MSI_INTR02_MASK 0x04000000
-#define BCHP_PCIE_0_INTR2_PCI_MASK_SET_MSI_INTR02_SHIFT 26
-#define BCHP_PCIE_0_INTR2_PCI_MASK_SET_MSI_INTR02_DEFAULT 0x00000001
-
-/* PCIE_0_INTR2 :: PCI_MASK_SET :: MSI_INTR01 [25:25] */
-#define BCHP_PCIE_0_INTR2_PCI_MASK_SET_MSI_INTR01_MASK 0x02000000
-#define BCHP_PCIE_0_INTR2_PCI_MASK_SET_MSI_INTR01_SHIFT 25
-#define BCHP_PCIE_0_INTR2_PCI_MASK_SET_MSI_INTR01_DEFAULT 0x00000001
-
-/* PCIE_0_INTR2 :: PCI_MASK_SET :: MSI_INTR00 [24:24] */
-#define BCHP_PCIE_0_INTR2_PCI_MASK_SET_MSI_INTR00_MASK 0x01000000
-#define BCHP_PCIE_0_INTR2_PCI_MASK_SET_MSI_INTR00_SHIFT 24
-#define BCHP_PCIE_0_INTR2_PCI_MASK_SET_MSI_INTR00_DEFAULT 0x00000001
-
-/* PCIE_0_INTR2 :: PCI_MASK_SET :: UNASSIGNED_23 [23:23] */
-#define BCHP_PCIE_0_INTR2_PCI_MASK_SET_UNASSIGNED_23_MASK 0x00800000
-#define BCHP_PCIE_0_INTR2_PCI_MASK_SET_UNASSIGNED_23_SHIFT 23
-#define BCHP_PCIE_0_INTR2_PCI_MASK_SET_UNASSIGNED_23_DEFAULT 0x00000001
-
-/* PCIE_0_INTR2 :: PCI_MASK_SET :: UNASSIGNED_22 [22:22] */
-#define BCHP_PCIE_0_INTR2_PCI_MASK_SET_UNASSIGNED_22_MASK 0x00400000
-#define BCHP_PCIE_0_INTR2_PCI_MASK_SET_UNASSIGNED_22_SHIFT 22
-#define BCHP_PCIE_0_INTR2_PCI_MASK_SET_UNASSIGNED_22_DEFAULT 0x00000001
-
-/* PCIE_0_INTR2 :: PCI_MASK_SET :: UNASSIGNED_21 [21:21] */
-#define BCHP_PCIE_0_INTR2_PCI_MASK_SET_UNASSIGNED_21_MASK 0x00200000
-#define BCHP_PCIE_0_INTR2_PCI_MASK_SET_UNASSIGNED_21_SHIFT 21
-#define BCHP_PCIE_0_INTR2_PCI_MASK_SET_UNASSIGNED_21_DEFAULT 0x00000001
-
-/* PCIE_0_INTR2 :: PCI_MASK_SET :: UNASSIGNED_20 [20:20] */
-#define BCHP_PCIE_0_INTR2_PCI_MASK_SET_UNASSIGNED_20_MASK 0x00100000
-#define BCHP_PCIE_0_INTR2_PCI_MASK_SET_UNASSIGNED_20_SHIFT 20
-#define BCHP_PCIE_0_INTR2_PCI_MASK_SET_UNASSIGNED_20_DEFAULT 0x00000001
-
-/* PCIE_0_INTR2 :: PCI_MASK_SET :: MAILBOX_3 [19:19] */
-#define BCHP_PCIE_0_INTR2_PCI_MASK_SET_MAILBOX_3_MASK 0x00080000
-#define BCHP_PCIE_0_INTR2_PCI_MASK_SET_MAILBOX_3_SHIFT 19
-#define BCHP_PCIE_0_INTR2_PCI_MASK_SET_MAILBOX_3_DEFAULT 0x00000001
-
-/* PCIE_0_INTR2 :: PCI_MASK_SET :: MAILBOX_2 [18:18] */
-#define BCHP_PCIE_0_INTR2_PCI_MASK_SET_MAILBOX_2_MASK 0x00040000
-#define BCHP_PCIE_0_INTR2_PCI_MASK_SET_MAILBOX_2_SHIFT 18
-#define BCHP_PCIE_0_INTR2_PCI_MASK_SET_MAILBOX_2_DEFAULT 0x00000001
-
-/* PCIE_0_INTR2 :: PCI_MASK_SET :: MAILBOX_1 [17:17] */
-#define BCHP_PCIE_0_INTR2_PCI_MASK_SET_MAILBOX_1_MASK 0x00020000
-#define BCHP_PCIE_0_INTR2_PCI_MASK_SET_MAILBOX_1_SHIFT 17
-#define BCHP_PCIE_0_INTR2_PCI_MASK_SET_MAILBOX_1_DEFAULT 0x00000001
-
-/* PCIE_0_INTR2 :: PCI_MASK_SET :: MAILBOX_0 [16:16] */
-#define BCHP_PCIE_0_INTR2_PCI_MASK_SET_MAILBOX_0_MASK 0x00010000
-#define BCHP_PCIE_0_INTR2_PCI_MASK_SET_MAILBOX_0_SHIFT 16
-#define BCHP_PCIE_0_INTR2_PCI_MASK_SET_MAILBOX_0_DEFAULT 0x00000001
-
-/* PCIE_0_INTR2 :: PCI_MASK_SET :: PCIE_MSTR_FWD_ERR [15:15] */
-#define BCHP_PCIE_0_INTR2_PCI_MASK_SET_PCIE_MSTR_FWD_ERR_MASK 0x00008000
-#define BCHP_PCIE_0_INTR2_PCI_MASK_SET_PCIE_MSTR_FWD_ERR_SHIFT 15
-#define BCHP_PCIE_0_INTR2_PCI_MASK_SET_PCIE_MSTR_FWD_ERR_DEFAULT 0x00000001
-
-/* PCIE_0_INTR2 :: PCI_MASK_SET :: PCIE_MSTR_RETRY_TIMEOUT [14:14] */
-#define BCHP_PCIE_0_INTR2_PCI_MASK_SET_PCIE_MSTR_RETRY_TIMEOUT_MASK 0x00004000
-#define BCHP_PCIE_0_INTR2_PCI_MASK_SET_PCIE_MSTR_RETRY_TIMEOUT_SHIFT 14
-#define BCHP_PCIE_0_INTR2_PCI_MASK_SET_PCIE_MSTR_RETRY_TIMEOUT_DEFAULT 0x00000001
-
-/* PCIE_0_INTR2 :: PCI_MASK_SET :: PCIE_MSTR_CA_ATTN [13:13] */
-#define BCHP_PCIE_0_INTR2_PCI_MASK_SET_PCIE_MSTR_CA_ATTN_MASK 0x00002000
-#define BCHP_PCIE_0_INTR2_PCI_MASK_SET_PCIE_MSTR_CA_ATTN_SHIFT 13
-#define BCHP_PCIE_0_INTR2_PCI_MASK_SET_PCIE_MSTR_CA_ATTN_DEFAULT 0x00000001
-
-/* PCIE_0_INTR2 :: PCI_MASK_SET :: PCIE_MSTR_UR_ATTN [12:12] */
-#define BCHP_PCIE_0_INTR2_PCI_MASK_SET_PCIE_MSTR_UR_ATTN_MASK 0x00001000
-#define BCHP_PCIE_0_INTR2_PCI_MASK_SET_PCIE_MSTR_UR_ATTN_SHIFT 12
-#define BCHP_PCIE_0_INTR2_PCI_MASK_SET_PCIE_MSTR_UR_ATTN_DEFAULT 0x00000001
-
-/* PCIE_0_INTR2 :: PCI_MASK_SET :: UNASSIGNED_11 [11:11] */
-#define BCHP_PCIE_0_INTR2_PCI_MASK_SET_UNASSIGNED_11_MASK 0x00000800
-#define BCHP_PCIE_0_INTR2_PCI_MASK_SET_UNASSIGNED_11_SHIFT 11
-#define BCHP_PCIE_0_INTR2_PCI_MASK_SET_UNASSIGNED_11_DEFAULT 0x00000001
-
-/* PCIE_0_INTR2 :: PCI_MASK_SET :: UNASSIGNED_10 [10:10] */
-#define BCHP_PCIE_0_INTR2_PCI_MASK_SET_UNASSIGNED_10_MASK 0x00000400
-#define BCHP_PCIE_0_INTR2_PCI_MASK_SET_UNASSIGNED_10_SHIFT 10
-#define BCHP_PCIE_0_INTR2_PCI_MASK_SET_UNASSIGNED_10_DEFAULT 0x00000001
-
-/* PCIE_0_INTR2 :: PCI_MASK_SET :: PCIE_TGT_BAD_ACCESS [09:09] */
-#define BCHP_PCIE_0_INTR2_PCI_MASK_SET_PCIE_TGT_BAD_ACCESS_MASK 0x00000200
-#define BCHP_PCIE_0_INTR2_PCI_MASK_SET_PCIE_TGT_BAD_ACCESS_SHIFT 9
-#define BCHP_PCIE_0_INTR2_PCI_MASK_SET_PCIE_TGT_BAD_ACCESS_DEFAULT 0x00000001
-
-/* PCIE_0_INTR2 :: PCI_MASK_SET :: PCIE_TGT_BAD_ADDRESS [08:08] */
-#define BCHP_PCIE_0_INTR2_PCI_MASK_SET_PCIE_TGT_BAD_ADDRESS_MASK 0x00000100
-#define BCHP_PCIE_0_INTR2_PCI_MASK_SET_PCIE_TGT_BAD_ADDRESS_SHIFT 8
-#define BCHP_PCIE_0_INTR2_PCI_MASK_SET_PCIE_TGT_BAD_ADDRESS_DEFAULT 0x00000001
-
-/* PCIE_0_INTR2 :: PCI_MASK_SET :: L1_RX_DMA_ERR_INTR [07:07] */
-#define BCHP_PCIE_0_INTR2_PCI_MASK_SET_L1_RX_DMA_ERR_INTR_MASK 0x00000080
-#define BCHP_PCIE_0_INTR2_PCI_MASK_SET_L1_RX_DMA_ERR_INTR_SHIFT 7
-#define BCHP_PCIE_0_INTR2_PCI_MASK_SET_L1_RX_DMA_ERR_INTR_DEFAULT 0x00000001
-
-/* PCIE_0_INTR2 :: PCI_MASK_SET :: L1_RX_DMA_DONE_INTR [06:06] */
-#define BCHP_PCIE_0_INTR2_PCI_MASK_SET_L1_RX_DMA_DONE_INTR_MASK 0x00000040
-#define BCHP_PCIE_0_INTR2_PCI_MASK_SET_L1_RX_DMA_DONE_INTR_SHIFT 6
-#define BCHP_PCIE_0_INTR2_PCI_MASK_SET_L1_RX_DMA_DONE_INTR_DEFAULT 0x00000001
-
-/* PCIE_0_INTR2 :: PCI_MASK_SET :: L1_TX_DMA_ERR_INTR [05:05] */
-#define BCHP_PCIE_0_INTR2_PCI_MASK_SET_L1_TX_DMA_ERR_INTR_MASK 0x00000020
-#define BCHP_PCIE_0_INTR2_PCI_MASK_SET_L1_TX_DMA_ERR_INTR_SHIFT 5
-#define BCHP_PCIE_0_INTR2_PCI_MASK_SET_L1_TX_DMA_ERR_INTR_DEFAULT 0x00000001
-
-/* PCIE_0_INTR2 :: PCI_MASK_SET :: L1_TX_DMA_DONE_INTR [04:04] */
-#define BCHP_PCIE_0_INTR2_PCI_MASK_SET_L1_TX_DMA_DONE_INTR_MASK 0x00000010
-#define BCHP_PCIE_0_INTR2_PCI_MASK_SET_L1_TX_DMA_DONE_INTR_SHIFT 4
-#define BCHP_PCIE_0_INTR2_PCI_MASK_SET_L1_TX_DMA_DONE_INTR_DEFAULT 0x00000001
-
-/* PCIE_0_INTR2 :: PCI_MASK_SET :: L0_RX_DMA_ERR_INTR [03:03] */
-#define BCHP_PCIE_0_INTR2_PCI_MASK_SET_L0_RX_DMA_ERR_INTR_MASK 0x00000008
-#define BCHP_PCIE_0_INTR2_PCI_MASK_SET_L0_RX_DMA_ERR_INTR_SHIFT 3
-#define BCHP_PCIE_0_INTR2_PCI_MASK_SET_L0_RX_DMA_ERR_INTR_DEFAULT 0x00000001
-
-/* PCIE_0_INTR2 :: PCI_MASK_SET :: L0_RX_DMA_DONE_INTR [02:02] */
-#define BCHP_PCIE_0_INTR2_PCI_MASK_SET_L0_RX_DMA_DONE_INTR_MASK 0x00000004
-#define BCHP_PCIE_0_INTR2_PCI_MASK_SET_L0_RX_DMA_DONE_INTR_SHIFT 2
-#define BCHP_PCIE_0_INTR2_PCI_MASK_SET_L0_RX_DMA_DONE_INTR_DEFAULT 0x00000001
-
-/* PCIE_0_INTR2 :: PCI_MASK_SET :: L0_TX_DMA_ERR_INTR [01:01] */
-#define BCHP_PCIE_0_INTR2_PCI_MASK_SET_L0_TX_DMA_ERR_INTR_MASK 0x00000002
-#define BCHP_PCIE_0_INTR2_PCI_MASK_SET_L0_TX_DMA_ERR_INTR_SHIFT 1
-#define BCHP_PCIE_0_INTR2_PCI_MASK_SET_L0_TX_DMA_ERR_INTR_DEFAULT 0x00000001
-
-/* PCIE_0_INTR2 :: PCI_MASK_SET :: L0_TX_DMA_DONE_INTR [00:00] */
-#define BCHP_PCIE_0_INTR2_PCI_MASK_SET_L0_TX_DMA_DONE_INTR_MASK 0x00000001
-#define BCHP_PCIE_0_INTR2_PCI_MASK_SET_L0_TX_DMA_DONE_INTR_SHIFT 0
-#define BCHP_PCIE_0_INTR2_PCI_MASK_SET_L0_TX_DMA_DONE_INTR_DEFAULT 0x00000001
-
-/***************************************************************************
- *PCI_MASK_CLEAR - PCI interrupt Mask Clear Register
- ***************************************************************************/
-/* PCIE_0_INTR2 :: PCI_MASK_CLEAR :: MSI_INTR07 [31:31] */
-#define BCHP_PCIE_0_INTR2_PCI_MASK_CLEAR_MSI_INTR07_MASK 0x80000000
-#define BCHP_PCIE_0_INTR2_PCI_MASK_CLEAR_MSI_INTR07_SHIFT 31
-#define BCHP_PCIE_0_INTR2_PCI_MASK_CLEAR_MSI_INTR07_DEFAULT 0x00000001
-
-/* PCIE_0_INTR2 :: PCI_MASK_CLEAR :: MSI_INTR06 [30:30] */
-#define BCHP_PCIE_0_INTR2_PCI_MASK_CLEAR_MSI_INTR06_MASK 0x40000000
-#define BCHP_PCIE_0_INTR2_PCI_MASK_CLEAR_MSI_INTR06_SHIFT 30
-#define BCHP_PCIE_0_INTR2_PCI_MASK_CLEAR_MSI_INTR06_DEFAULT 0x00000001
-
-/* PCIE_0_INTR2 :: PCI_MASK_CLEAR :: MSI_INTR05 [29:29] */
-#define BCHP_PCIE_0_INTR2_PCI_MASK_CLEAR_MSI_INTR05_MASK 0x20000000
-#define BCHP_PCIE_0_INTR2_PCI_MASK_CLEAR_MSI_INTR05_SHIFT 29
-#define BCHP_PCIE_0_INTR2_PCI_MASK_CLEAR_MSI_INTR05_DEFAULT 0x00000001
-
-/* PCIE_0_INTR2 :: PCI_MASK_CLEAR :: MSI_INTR04 [28:28] */
-#define BCHP_PCIE_0_INTR2_PCI_MASK_CLEAR_MSI_INTR04_MASK 0x10000000
-#define BCHP_PCIE_0_INTR2_PCI_MASK_CLEAR_MSI_INTR04_SHIFT 28
-#define BCHP_PCIE_0_INTR2_PCI_MASK_CLEAR_MSI_INTR04_DEFAULT 0x00000001
-
-/* PCIE_0_INTR2 :: PCI_MASK_CLEAR :: MSI_INTR03 [27:27] */
-#define BCHP_PCIE_0_INTR2_PCI_MASK_CLEAR_MSI_INTR03_MASK 0x08000000
-#define BCHP_PCIE_0_INTR2_PCI_MASK_CLEAR_MSI_INTR03_SHIFT 27
-#define BCHP_PCIE_0_INTR2_PCI_MASK_CLEAR_MSI_INTR03_DEFAULT 0x00000001
-
-/* PCIE_0_INTR2 :: PCI_MASK_CLEAR :: MSI_INTR02 [26:26] */
-#define BCHP_PCIE_0_INTR2_PCI_MASK_CLEAR_MSI_INTR02_MASK 0x04000000
-#define BCHP_PCIE_0_INTR2_PCI_MASK_CLEAR_MSI_INTR02_SHIFT 26
-#define BCHP_PCIE_0_INTR2_PCI_MASK_CLEAR_MSI_INTR02_DEFAULT 0x00000001
-
-/* PCIE_0_INTR2 :: PCI_MASK_CLEAR :: MSI_INTR01 [25:25] */
-#define BCHP_PCIE_0_INTR2_PCI_MASK_CLEAR_MSI_INTR01_MASK 0x02000000
-#define BCHP_PCIE_0_INTR2_PCI_MASK_CLEAR_MSI_INTR01_SHIFT 25
-#define BCHP_PCIE_0_INTR2_PCI_MASK_CLEAR_MSI_INTR01_DEFAULT 0x00000001
-
-/* PCIE_0_INTR2 :: PCI_MASK_CLEAR :: MSI_INTR00 [24:24] */
-#define BCHP_PCIE_0_INTR2_PCI_MASK_CLEAR_MSI_INTR00_MASK 0x01000000
-#define BCHP_PCIE_0_INTR2_PCI_MASK_CLEAR_MSI_INTR00_SHIFT 24
-#define BCHP_PCIE_0_INTR2_PCI_MASK_CLEAR_MSI_INTR00_DEFAULT 0x00000001
-
-/* PCIE_0_INTR2 :: PCI_MASK_CLEAR :: UNASSIGNED_23 [23:23] */
-#define BCHP_PCIE_0_INTR2_PCI_MASK_CLEAR_UNASSIGNED_23_MASK 0x00800000
-#define BCHP_PCIE_0_INTR2_PCI_MASK_CLEAR_UNASSIGNED_23_SHIFT 23
-#define BCHP_PCIE_0_INTR2_PCI_MASK_CLEAR_UNASSIGNED_23_DEFAULT 0x00000001
-
-/* PCIE_0_INTR2 :: PCI_MASK_CLEAR :: UNASSIGNED_22 [22:22] */
-#define BCHP_PCIE_0_INTR2_PCI_MASK_CLEAR_UNASSIGNED_22_MASK 0x00400000
-#define BCHP_PCIE_0_INTR2_PCI_MASK_CLEAR_UNASSIGNED_22_SHIFT 22
-#define BCHP_PCIE_0_INTR2_PCI_MASK_CLEAR_UNASSIGNED_22_DEFAULT 0x00000001
-
-/* PCIE_0_INTR2 :: PCI_MASK_CLEAR :: UNASSIGNED_21 [21:21] */
-#define BCHP_PCIE_0_INTR2_PCI_MASK_CLEAR_UNASSIGNED_21_MASK 0x00200000
-#define BCHP_PCIE_0_INTR2_PCI_MASK_CLEAR_UNASSIGNED_21_SHIFT 21
-#define BCHP_PCIE_0_INTR2_PCI_MASK_CLEAR_UNASSIGNED_21_DEFAULT 0x00000001
-
-/* PCIE_0_INTR2 :: PCI_MASK_CLEAR :: UNASSIGNED_20 [20:20] */
-#define BCHP_PCIE_0_INTR2_PCI_MASK_CLEAR_UNASSIGNED_20_MASK 0x00100000
-#define BCHP_PCIE_0_INTR2_PCI_MASK_CLEAR_UNASSIGNED_20_SHIFT 20
-#define BCHP_PCIE_0_INTR2_PCI_MASK_CLEAR_UNASSIGNED_20_DEFAULT 0x00000001
-
-/* PCIE_0_INTR2 :: PCI_MASK_CLEAR :: MAILBOX_3 [19:19] */
-#define BCHP_PCIE_0_INTR2_PCI_MASK_CLEAR_MAILBOX_3_MASK 0x00080000
-#define BCHP_PCIE_0_INTR2_PCI_MASK_CLEAR_MAILBOX_3_SHIFT 19
-#define BCHP_PCIE_0_INTR2_PCI_MASK_CLEAR_MAILBOX_3_DEFAULT 0x00000001
-
-/* PCIE_0_INTR2 :: PCI_MASK_CLEAR :: MAILBOX_2 [18:18] */
-#define BCHP_PCIE_0_INTR2_PCI_MASK_CLEAR_MAILBOX_2_MASK 0x00040000
-#define BCHP_PCIE_0_INTR2_PCI_MASK_CLEAR_MAILBOX_2_SHIFT 18
-#define BCHP_PCIE_0_INTR2_PCI_MASK_CLEAR_MAILBOX_2_DEFAULT 0x00000001
-
-/* PCIE_0_INTR2 :: PCI_MASK_CLEAR :: MAILBOX_1 [17:17] */
-#define BCHP_PCIE_0_INTR2_PCI_MASK_CLEAR_MAILBOX_1_MASK 0x00020000
-#define BCHP_PCIE_0_INTR2_PCI_MASK_CLEAR_MAILBOX_1_SHIFT 17
-#define BCHP_PCIE_0_INTR2_PCI_MASK_CLEAR_MAILBOX_1_DEFAULT 0x00000001
-
-/* PCIE_0_INTR2 :: PCI_MASK_CLEAR :: MAILBOX_0 [16:16] */
-#define BCHP_PCIE_0_INTR2_PCI_MASK_CLEAR_MAILBOX_0_MASK 0x00010000
-#define BCHP_PCIE_0_INTR2_PCI_MASK_CLEAR_MAILBOX_0_SHIFT 16
-#define BCHP_PCIE_0_INTR2_PCI_MASK_CLEAR_MAILBOX_0_DEFAULT 0x00000001
-
-/* PCIE_0_INTR2 :: PCI_MASK_CLEAR :: PCIE_MSTR_FWD_ERR [15:15] */
-#define BCHP_PCIE_0_INTR2_PCI_MASK_CLEAR_PCIE_MSTR_FWD_ERR_MASK 0x00008000
-#define BCHP_PCIE_0_INTR2_PCI_MASK_CLEAR_PCIE_MSTR_FWD_ERR_SHIFT 15
-#define BCHP_PCIE_0_INTR2_PCI_MASK_CLEAR_PCIE_MSTR_FWD_ERR_DEFAULT 0x00000001
-
-/* PCIE_0_INTR2 :: PCI_MASK_CLEAR :: PCIE_MSTR_RETRY_TIMEOUT [14:14] */
-#define BCHP_PCIE_0_INTR2_PCI_MASK_CLEAR_PCIE_MSTR_RETRY_TIMEOUT_MASK 0x00004000
-#define BCHP_PCIE_0_INTR2_PCI_MASK_CLEAR_PCIE_MSTR_RETRY_TIMEOUT_SHIFT 14
-#define BCHP_PCIE_0_INTR2_PCI_MASK_CLEAR_PCIE_MSTR_RETRY_TIMEOUT_DEFAULT 0x00000001
-
-/* PCIE_0_INTR2 :: PCI_MASK_CLEAR :: PCIE_MSTR_CA_ATTN [13:13] */
-#define BCHP_PCIE_0_INTR2_PCI_MASK_CLEAR_PCIE_MSTR_CA_ATTN_MASK 0x00002000
-#define BCHP_PCIE_0_INTR2_PCI_MASK_CLEAR_PCIE_MSTR_CA_ATTN_SHIFT 13
-#define BCHP_PCIE_0_INTR2_PCI_MASK_CLEAR_PCIE_MSTR_CA_ATTN_DEFAULT 0x00000001
-
-/* PCIE_0_INTR2 :: PCI_MASK_CLEAR :: PCIE_MSTR_UR_ATTN [12:12] */
-#define BCHP_PCIE_0_INTR2_PCI_MASK_CLEAR_PCIE_MSTR_UR_ATTN_MASK 0x00001000
-#define BCHP_PCIE_0_INTR2_PCI_MASK_CLEAR_PCIE_MSTR_UR_ATTN_SHIFT 12
-#define BCHP_PCIE_0_INTR2_PCI_MASK_CLEAR_PCIE_MSTR_UR_ATTN_DEFAULT 0x00000001
-
-/* PCIE_0_INTR2 :: PCI_MASK_CLEAR :: UNASSIGNED_11 [11:11] */
-#define BCHP_PCIE_0_INTR2_PCI_MASK_CLEAR_UNASSIGNED_11_MASK 0x00000800
-#define BCHP_PCIE_0_INTR2_PCI_MASK_CLEAR_UNASSIGNED_11_SHIFT 11
-#define BCHP_PCIE_0_INTR2_PCI_MASK_CLEAR_UNASSIGNED_11_DEFAULT 0x00000001
-
-/* PCIE_0_INTR2 :: PCI_MASK_CLEAR :: UNASSIGNED_10 [10:10] */
-#define BCHP_PCIE_0_INTR2_PCI_MASK_CLEAR_UNASSIGNED_10_MASK 0x00000400
-#define BCHP_PCIE_0_INTR2_PCI_MASK_CLEAR_UNASSIGNED_10_SHIFT 10
-#define BCHP_PCIE_0_INTR2_PCI_MASK_CLEAR_UNASSIGNED_10_DEFAULT 0x00000001
-
-/* PCIE_0_INTR2 :: PCI_MASK_CLEAR :: PCIE_TGT_BAD_ACCESS [09:09] */
-#define BCHP_PCIE_0_INTR2_PCI_MASK_CLEAR_PCIE_TGT_BAD_ACCESS_MASK 0x00000200
-#define BCHP_PCIE_0_INTR2_PCI_MASK_CLEAR_PCIE_TGT_BAD_ACCESS_SHIFT 9
-#define BCHP_PCIE_0_INTR2_PCI_MASK_CLEAR_PCIE_TGT_BAD_ACCESS_DEFAULT 0x00000001
-
-/* PCIE_0_INTR2 :: PCI_MASK_CLEAR :: PCIE_TGT_BAD_ADDRESS [08:08] */
-#define BCHP_PCIE_0_INTR2_PCI_MASK_CLEAR_PCIE_TGT_BAD_ADDRESS_MASK 0x00000100
-#define BCHP_PCIE_0_INTR2_PCI_MASK_CLEAR_PCIE_TGT_BAD_ADDRESS_SHIFT 8
-#define BCHP_PCIE_0_INTR2_PCI_MASK_CLEAR_PCIE_TGT_BAD_ADDRESS_DEFAULT 0x00000001
-
-/* PCIE_0_INTR2 :: PCI_MASK_CLEAR :: L1_RX_DMA_ERR_INTR [07:07] */
-#define BCHP_PCIE_0_INTR2_PCI_MASK_CLEAR_L1_RX_DMA_ERR_INTR_MASK 0x00000080
-#define BCHP_PCIE_0_INTR2_PCI_MASK_CLEAR_L1_RX_DMA_ERR_INTR_SHIFT 7
-#define BCHP_PCIE_0_INTR2_PCI_MASK_CLEAR_L1_RX_DMA_ERR_INTR_DEFAULT 0x00000001
-
-/* PCIE_0_INTR2 :: PCI_MASK_CLEAR :: L1_RX_DMA_DONE_INTR [06:06] */
-#define BCHP_PCIE_0_INTR2_PCI_MASK_CLEAR_L1_RX_DMA_DONE_INTR_MASK 0x00000040
-#define BCHP_PCIE_0_INTR2_PCI_MASK_CLEAR_L1_RX_DMA_DONE_INTR_SHIFT 6
-#define BCHP_PCIE_0_INTR2_PCI_MASK_CLEAR_L1_RX_DMA_DONE_INTR_DEFAULT 0x00000001
-
-/* PCIE_0_INTR2 :: PCI_MASK_CLEAR :: L1_TX_DMA_ERR_INTR [05:05] */
-#define BCHP_PCIE_0_INTR2_PCI_MASK_CLEAR_L1_TX_DMA_ERR_INTR_MASK 0x00000020
-#define BCHP_PCIE_0_INTR2_PCI_MASK_CLEAR_L1_TX_DMA_ERR_INTR_SHIFT 5
-#define BCHP_PCIE_0_INTR2_PCI_MASK_CLEAR_L1_TX_DMA_ERR_INTR_DEFAULT 0x00000001
-
-/* PCIE_0_INTR2 :: PCI_MASK_CLEAR :: L1_TX_DMA_DONE_INTR [04:04] */
-#define BCHP_PCIE_0_INTR2_PCI_MASK_CLEAR_L1_TX_DMA_DONE_INTR_MASK 0x00000010
-#define BCHP_PCIE_0_INTR2_PCI_MASK_CLEAR_L1_TX_DMA_DONE_INTR_SHIFT 4
-#define BCHP_PCIE_0_INTR2_PCI_MASK_CLEAR_L1_TX_DMA_DONE_INTR_DEFAULT 0x00000001
-
-/* PCIE_0_INTR2 :: PCI_MASK_CLEAR :: L0_RX_DMA_ERR_INTR [03:03] */
-#define BCHP_PCIE_0_INTR2_PCI_MASK_CLEAR_L0_RX_DMA_ERR_INTR_MASK 0x00000008
-#define BCHP_PCIE_0_INTR2_PCI_MASK_CLEAR_L0_RX_DMA_ERR_INTR_SHIFT 3
-#define BCHP_PCIE_0_INTR2_PCI_MASK_CLEAR_L0_RX_DMA_ERR_INTR_DEFAULT 0x00000001
-
-/* PCIE_0_INTR2 :: PCI_MASK_CLEAR :: L0_RX_DMA_DONE_INTR [02:02] */
-#define BCHP_PCIE_0_INTR2_PCI_MASK_CLEAR_L0_RX_DMA_DONE_INTR_MASK 0x00000004
-#define BCHP_PCIE_0_INTR2_PCI_MASK_CLEAR_L0_RX_DMA_DONE_INTR_SHIFT 2
-#define BCHP_PCIE_0_INTR2_PCI_MASK_CLEAR_L0_RX_DMA_DONE_INTR_DEFAULT 0x00000001
-
-/* PCIE_0_INTR2 :: PCI_MASK_CLEAR :: L0_TX_DMA_ERR_INTR [01:01] */
-#define BCHP_PCIE_0_INTR2_PCI_MASK_CLEAR_L0_TX_DMA_ERR_INTR_MASK 0x00000002
-#define BCHP_PCIE_0_INTR2_PCI_MASK_CLEAR_L0_TX_DMA_ERR_INTR_SHIFT 1
-#define BCHP_PCIE_0_INTR2_PCI_MASK_CLEAR_L0_TX_DMA_ERR_INTR_DEFAULT 0x00000001
-
-/* PCIE_0_INTR2 :: PCI_MASK_CLEAR :: L0_TX_DMA_DONE_INTR [00:00] */
-#define BCHP_PCIE_0_INTR2_PCI_MASK_CLEAR_L0_TX_DMA_DONE_INTR_MASK 0x00000001
-#define BCHP_PCIE_0_INTR2_PCI_MASK_CLEAR_L0_TX_DMA_DONE_INTR_SHIFT 0
-#define BCHP_PCIE_0_INTR2_PCI_MASK_CLEAR_L0_TX_DMA_DONE_INTR_DEFAULT 0x00000001
-
-#endif /* #ifndef BCHP_PCIE_0_INTR2_H__ */
-
-/* End of File */
diff --git a/include/linux/brcmstb/7145a0/bchp_pcie_0_misc.h b/include/linux/brcmstb/7145a0/bchp_pcie_0_misc.h
deleted file mode 100644
index 952eebd..0000000
--- a/include/linux/brcmstb/7145a0/bchp_pcie_0_misc.h
+++ /dev/null
@@ -1,974 +0,0 @@
-/***************************************************************************
- * Copyright (c) 1999-2013, Broadcom Corporation
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
- *
- * Module Description:
- * DO NOT EDIT THIS FILE DIRECTLY
- *
- * This module was generated magically with RDB from a source description
- * file. You must edit the source file for changes to be made to this file.
- *
- *
- * Date: Generated on Sat Apr 6 03:07:51 2013
- * MD5 Checksum d41d8cd98f00b204e9800998ecf8427e
- *
- * Compiled with: RDB Utility combo_header.pl
- * RDB Parser 3.0
- * unknown unknown
- * Perl Interpreter 5.008008
- * Operating System linux
- *
- * Revision History:
- *
- * $brcm_Log: $
- *
- ***************************************************************************/
-
-#ifndef BCHP_PCIE_0_MISC_H__
-#define BCHP_PCIE_0_MISC_H__
-
-/***************************************************************************
- *PCIE_0_MISC - PCI-E Miscellaneous Registers
- ***************************************************************************/
-#define BCHP_PCIE_0_MISC_RESET_CTRL 0x07804000 /* Reset Control Register */
-#define BCHP_PCIE_0_MISC_ECO_CTRL_CORE 0x07804004 /* ECO Core Reset Control Register */
-#define BCHP_PCIE_0_MISC_MISC_CTRL 0x07804008 /* MISC Control Register */
-#define BCHP_PCIE_0_MISC_CPU_2_PCIE_MEM_WIN0_LO 0x0780400c /* CPU to PCIe Memory Window 0 Low */
-#define BCHP_PCIE_0_MISC_CPU_2_PCIE_MEM_WIN0_HI 0x07804010 /* CPU to PCIe Memory Window 0 High */
-#define BCHP_PCIE_0_MISC_CPU_2_PCIE_MEM_WIN1_LO 0x07804014 /* CPU to PCIe Memory Window 1 Low */
-#define BCHP_PCIE_0_MISC_CPU_2_PCIE_MEM_WIN1_HI 0x07804018 /* CPU to PCIe Memory Window 1 High */
-#define BCHP_PCIE_0_MISC_CPU_2_PCIE_MEM_WIN2_LO 0x0780401c /* CPU to PCIe Memory Window 2 Low */
-#define BCHP_PCIE_0_MISC_CPU_2_PCIE_MEM_WIN2_HI 0x07804020 /* CPU to PCIe Memory Window 2 High */
-#define BCHP_PCIE_0_MISC_CPU_2_PCIE_MEM_WIN3_LO 0x07804024 /* CPU to PCIe Memory Window 3 Low */
-#define BCHP_PCIE_0_MISC_CPU_2_PCIE_MEM_WIN3_HI 0x07804028 /* CPU to PCIe Memory Window 3 High */
-#define BCHP_PCIE_0_MISC_RC_BAR1_CONFIG_LO 0x0780402c /* RC BAR1 Configuration Low Register */
-#define BCHP_PCIE_0_MISC_RC_BAR1_CONFIG_HI 0x07804030 /* RC BAR1 Configuration High Register */
-#define BCHP_PCIE_0_MISC_RC_BAR2_CONFIG_LO 0x07804034 /* RC BAR2 Configuration Low Register */
-#define BCHP_PCIE_0_MISC_RC_BAR2_CONFIG_HI 0x07804038 /* RC BAR2 Configuration High Register */
-#define BCHP_PCIE_0_MISC_RC_BAR3_CONFIG_LO 0x0780403c /* RC BAR3 Configuration Low Register */
-#define BCHP_PCIE_0_MISC_RC_BAR3_CONFIG_HI 0x07804040 /* RC BAR3 Configuration High Register */
-#define BCHP_PCIE_0_MISC_MSI_BAR_CONFIG_LO 0x07804044 /* Message Signaled Interrupt Base Address Low Register */
-#define BCHP_PCIE_0_MISC_MSI_BAR_CONFIG_HI 0x07804048 /* Message Signaled Interrupt Base Address High Register */
-#define BCHP_PCIE_0_MISC_MSI_DATA_CONFIG 0x0780404c /* Message Signaled Interrupt Data Configuration Register */
-#define BCHP_PCIE_0_MISC_RC_BAD_ADDRESS_LO 0x07804050 /* RC Bad Address Register Low */
-#define BCHP_PCIE_0_MISC_RC_BAD_ADDRESS_HI 0x07804054 /* RC Bad Address Register High */
-#define BCHP_PCIE_0_MISC_RC_BAD_DATA 0x07804058 /* RC Bad Data Register */
-#define BCHP_PCIE_0_MISC_RC_CONFIG_RETRY_TIMEOUT 0x0780405c /* RC Configuration Retry Timeout Register */
-#define BCHP_PCIE_0_MISC_EOI_CTRL 0x07804060 /* End of Interrupt Control Register */
-#define BCHP_PCIE_0_MISC_PCIE_CTRL 0x07804064 /* PCIe Control */
-#define BCHP_PCIE_0_MISC_PCIE_STATUS 0x07804068 /* PCIe Status */
-#define BCHP_PCIE_0_MISC_REVISION 0x0780406c /* PCIe Revision */
-#define BCHP_PCIE_0_MISC_CPU_2_PCIE_MEM_WIN0_BASE_LIMIT 0x07804070 /* CPU to PCIe Memory Window 0 base/limit */
-#define BCHP_PCIE_0_MISC_CPU_2_PCIE_MEM_WIN1_BASE_LIMIT 0x07804074 /* CPU to PCIe Memory Window 1 base/limit */
-#define BCHP_PCIE_0_MISC_CPU_2_PCIE_MEM_WIN2_BASE_LIMIT 0x07804078 /* CPU to PCIe Memory Window 2 base/limit */
-#define BCHP_PCIE_0_MISC_CPU_2_PCIE_MEM_WIN3_BASE_LIMIT 0x0780407c /* CPU to PCIe Memory Window 3 base/limit */
-#define BCHP_PCIE_0_MISC_CPU_2_PCIE_MEM_WIN0_BASE_HI 0x07804080 /* CPU to PCIe Memory Window 0 base high */
-#define BCHP_PCIE_0_MISC_CPU_2_PCIE_MEM_WIN0_LIMIT_HI 0x07804084 /* CPU to PCIe Memory Window 0 limit high */
-#define BCHP_PCIE_0_MISC_CPU_2_PCIE_MEM_WIN1_BASE_HI 0x07804088 /* CPU to PCIe Memory Window 1 base high */
-#define BCHP_PCIE_0_MISC_CPU_2_PCIE_MEM_WIN1_LIMIT_HI 0x0780408c /* CPU to PCIe Memory Window 1 limit high */
-#define BCHP_PCIE_0_MISC_CPU_2_PCIE_MEM_WIN2_BASE_HI 0x07804090 /* CPU to PCIe Memory Window 2 base high */
-#define BCHP_PCIE_0_MISC_CPU_2_PCIE_MEM_WIN2_LIMIT_HI 0x07804094 /* CPU to PCIe Memory Window 2 limit high */
-#define BCHP_PCIE_0_MISC_CPU_2_PCIE_MEM_WIN3_BASE_HI 0x07804098 /* CPU to PCIe Memory Window 3 base high */
-#define BCHP_PCIE_0_MISC_CPU_2_PCIE_MEM_WIN3_LIMIT_HI 0x0780409c /* CPU to PCIe Memory Window 3 limit high */
-#define BCHP_PCIE_0_MISC_MISC_CTRL_1 0x078040a0 /* MISC Control Register 1 */
-#define BCHP_PCIE_0_MISC_UBUS_CTRL 0x078040a4 /* UBUS Control */
-#define BCHP_PCIE_0_MISC_UBUS_TIMEOUT 0x078040a8 /* UBUS Timeout */
-#define BCHP_PCIE_0_MISC_UBUS_BAR1_CONFIG_REMAP 0x078040ac /* UBUS BAR1 System Bus Address Remap Register */
-#define BCHP_PCIE_0_MISC_UBUS_BAR1_CONFIG_REMAP_HI 0x078040b0 /* UBUS BAR2 System Bus Address Remap Register High */
-#define BCHP_PCIE_0_MISC_UBUS_BAR2_CONFIG_REMAP 0x078040b4 /* UBUS BAR2 System Bus Address Remap Register */
-#define BCHP_PCIE_0_MISC_UBUS_BAR2_CONFIG_REMAP_HI 0x078040b8 /* UBUS BAR2 System Bus Address Remap Register High */
-#define BCHP_PCIE_0_MISC_UBUS_BAR3_CONFIG_REMAP 0x078040bc /* UBUS BAR3 System Bus Address Remap Register */
-#define BCHP_PCIE_0_MISC_UBUS_BAR3_CONFIG_REMAP_HI 0x078040c0 /* UBUS BAR3 System Bus Address Remap Register High */
-#define BCHP_PCIE_0_MISC_UBUS_STATUS 0x078040c4 /* UBUS Status */
-
-/***************************************************************************
- *RESET_CTRL - Reset Control Register
- ***************************************************************************/
-/* PCIE_0_MISC :: RESET_CTRL :: reserved0 [31:01] */
-#define BCHP_PCIE_0_MISC_RESET_CTRL_reserved0_MASK 0xfffffffe
-#define BCHP_PCIE_0_MISC_RESET_CTRL_reserved0_SHIFT 1
-
-/* PCIE_0_MISC :: RESET_CTRL :: CORE_RESET [00:00] */
-#define BCHP_PCIE_0_MISC_RESET_CTRL_CORE_RESET_MASK 0x00000001
-#define BCHP_PCIE_0_MISC_RESET_CTRL_CORE_RESET_SHIFT 0
-#define BCHP_PCIE_0_MISC_RESET_CTRL_CORE_RESET_DEFAULT 0x00000000
-
-/***************************************************************************
- *ECO_CTRL_CORE - ECO Core Reset Control Register
- ***************************************************************************/
-/* PCIE_0_MISC :: ECO_CTRL_CORE :: reserved0 [31:16] */
-#define BCHP_PCIE_0_MISC_ECO_CTRL_CORE_reserved0_MASK 0xffff0000
-#define BCHP_PCIE_0_MISC_ECO_CTRL_CORE_reserved0_SHIFT 16
-
-/* PCIE_0_MISC :: ECO_CTRL_CORE :: ECO_CORE_RST_N [15:00] */
-#define BCHP_PCIE_0_MISC_ECO_CTRL_CORE_ECO_CORE_RST_N_MASK 0x0000ffff
-#define BCHP_PCIE_0_MISC_ECO_CTRL_CORE_ECO_CORE_RST_N_SHIFT 0
-#define BCHP_PCIE_0_MISC_ECO_CTRL_CORE_ECO_CORE_RST_N_DEFAULT 0x00000000
-
-/***************************************************************************
- *MISC_CTRL - MISC Control Register
- ***************************************************************************/
-/* PCIE_0_MISC :: MISC_CTRL :: SCB0_SIZE [31:27] */
-#define BCHP_PCIE_0_MISC_MISC_CTRL_SCB0_SIZE_MASK 0xf8000000
-#define BCHP_PCIE_0_MISC_MISC_CTRL_SCB0_SIZE_SHIFT 27
-#define BCHP_PCIE_0_MISC_MISC_CTRL_SCB0_SIZE_DEFAULT 0x00000000
-
-/* PCIE_0_MISC :: MISC_CTRL :: SCB1_SIZE [26:22] */
-#define BCHP_PCIE_0_MISC_MISC_CTRL_SCB1_SIZE_MASK 0x07c00000
-#define BCHP_PCIE_0_MISC_MISC_CTRL_SCB1_SIZE_SHIFT 22
-#define BCHP_PCIE_0_MISC_MISC_CTRL_SCB1_SIZE_DEFAULT 0x00000000
-
-/* PCIE_0_MISC :: MISC_CTRL :: MAX_BURST_SIZE [21:20] */
-#define BCHP_PCIE_0_MISC_MISC_CTRL_MAX_BURST_SIZE_MASK 0x00300000
-#define BCHP_PCIE_0_MISC_MISC_CTRL_MAX_BURST_SIZE_SHIFT 20
-#define BCHP_PCIE_0_MISC_MISC_CTRL_MAX_BURST_SIZE_DEFAULT 0x00000000
-
-/* PCIE_0_MISC :: MISC_CTRL :: BURST_ALIGN [19:19] */
-#define BCHP_PCIE_0_MISC_MISC_CTRL_BURST_ALIGN_MASK 0x00080000
-#define BCHP_PCIE_0_MISC_MISC_CTRL_BURST_ALIGN_SHIFT 19
-#define BCHP_PCIE_0_MISC_MISC_CTRL_BURST_ALIGN_DEFAULT 0x00000000
-
-/* PCIE_0_MISC :: MISC_CTRL :: TBD_OPTION_18 [18:18] */
-#define BCHP_PCIE_0_MISC_MISC_CTRL_TBD_OPTION_18_MASK 0x00040000
-#define BCHP_PCIE_0_MISC_MISC_CTRL_TBD_OPTION_18_SHIFT 18
-#define BCHP_PCIE_0_MISC_MISC_CTRL_TBD_OPTION_18_DEFAULT 0x00000000
-
-/* PCIE_0_MISC :: MISC_CTRL :: CSR_CFG_MODE [17:17] */
-#define BCHP_PCIE_0_MISC_MISC_CTRL_CSR_CFG_MODE_MASK 0x00020000
-#define BCHP_PCIE_0_MISC_MISC_CTRL_CSR_CFG_MODE_SHIFT 17
-#define BCHP_PCIE_0_MISC_MISC_CTRL_CSR_CFG_MODE_DEFAULT 0x00000000
-
-/* PCIE_0_MISC :: MISC_CTRL :: CSR_CFG_RETRY_EN [16:16] */
-#define BCHP_PCIE_0_MISC_MISC_CTRL_CSR_CFG_RETRY_EN_MASK 0x00010000
-#define BCHP_PCIE_0_MISC_MISC_CTRL_CSR_CFG_RETRY_EN_SHIFT 16
-#define BCHP_PCIE_0_MISC_MISC_CTRL_CSR_CFG_RETRY_EN_DEFAULT 0x00000000
-
-/* PCIE_0_MISC :: MISC_CTRL :: TBD_OPTION_15 [15:15] */
-#define BCHP_PCIE_0_MISC_MISC_CTRL_TBD_OPTION_15_MASK 0x00008000
-#define BCHP_PCIE_0_MISC_MISC_CTRL_TBD_OPTION_15_SHIFT 15
-#define BCHP_PCIE_0_MISC_MISC_CTRL_TBD_OPTION_15_DEFAULT 0x00000000
-
-/* PCIE_0_MISC :: MISC_CTRL :: TBD_OPTION_14 [14:14] */
-#define BCHP_PCIE_0_MISC_MISC_CTRL_TBD_OPTION_14_MASK 0x00004000
-#define BCHP_PCIE_0_MISC_MISC_CTRL_TBD_OPTION_14_SHIFT 14
-#define BCHP_PCIE_0_MISC_MISC_CTRL_TBD_OPTION_14_DEFAULT 0x00000000
-
-/* PCIE_0_MISC :: MISC_CTRL :: CFG_READ_UR_MODE [13:13] */
-#define BCHP_PCIE_0_MISC_MISC_CTRL_CFG_READ_UR_MODE_MASK 0x00002000
-#define BCHP_PCIE_0_MISC_MISC_CTRL_CFG_READ_UR_MODE_SHIFT 13
-#define BCHP_PCIE_0_MISC_MISC_CTRL_CFG_READ_UR_MODE_DEFAULT 0x00000000
-
-/* PCIE_0_MISC :: MISC_CTRL :: SCB_ACCESS_EN [12:12] */
-#define BCHP_PCIE_0_MISC_MISC_CTRL_SCB_ACCESS_EN_MASK 0x00001000
-#define BCHP_PCIE_0_MISC_MISC_CTRL_SCB_ACCESS_EN_SHIFT 12
-#define BCHP_PCIE_0_MISC_MISC_CTRL_SCB_ACCESS_EN_DEFAULT 0x00000000
-
-/* PCIE_0_MISC :: MISC_CTRL :: PCIE_IN_WR_COMBINE [11:11] */
-#define BCHP_PCIE_0_MISC_MISC_CTRL_PCIE_IN_WR_COMBINE_MASK 0x00000800
-#define BCHP_PCIE_0_MISC_MISC_CTRL_PCIE_IN_WR_COMBINE_SHIFT 11
-#define BCHP_PCIE_0_MISC_MISC_CTRL_PCIE_IN_WR_COMBINE_DEFAULT 0x00000000
-
-/* PCIE_0_MISC :: MISC_CTRL :: PCIE_RCB_MPS_MODE [10:10] */
-#define BCHP_PCIE_0_MISC_MISC_CTRL_PCIE_RCB_MPS_MODE_MASK 0x00000400
-#define BCHP_PCIE_0_MISC_MISC_CTRL_PCIE_RCB_MPS_MODE_SHIFT 10
-#define BCHP_PCIE_0_MISC_MISC_CTRL_PCIE_RCB_MPS_MODE_DEFAULT 0x00000000
-
-/* PCIE_0_MISC :: MISC_CTRL :: DESC_PRIORITY_EN [09:09] */
-#define BCHP_PCIE_0_MISC_MISC_CTRL_DESC_PRIORITY_EN_MASK 0x00000200
-#define BCHP_PCIE_0_MISC_MISC_CTRL_DESC_PRIORITY_EN_SHIFT 9
-#define BCHP_PCIE_0_MISC_MISC_CTRL_DESC_PRIORITY_EN_DEFAULT 0x00000000
-
-/* PCIE_0_MISC :: MISC_CTRL :: READ_PRIORITY_EN [08:08] */
-#define BCHP_PCIE_0_MISC_MISC_CTRL_READ_PRIORITY_EN_MASK 0x00000100
-#define BCHP_PCIE_0_MISC_MISC_CTRL_READ_PRIORITY_EN_SHIFT 8
-#define BCHP_PCIE_0_MISC_MISC_CTRL_READ_PRIORITY_EN_DEFAULT 0x00000000
-
-/* PCIE_0_MISC :: MISC_CTRL :: PCIE_RCB_64B_MODE [07:07] */
-#define BCHP_PCIE_0_MISC_MISC_CTRL_PCIE_RCB_64B_MODE_MASK 0x00000080
-#define BCHP_PCIE_0_MISC_MISC_CTRL_PCIE_RCB_64B_MODE_SHIFT 7
-#define BCHP_PCIE_0_MISC_MISC_CTRL_PCIE_RCB_64B_MODE_DEFAULT 0x00000000
-
-/* PCIE_0_MISC :: MISC_CTRL :: PCIE_OUT_CPL_RO [06:06] */
-#define BCHP_PCIE_0_MISC_MISC_CTRL_PCIE_OUT_CPL_RO_MASK 0x00000040
-#define BCHP_PCIE_0_MISC_MISC_CTRL_PCIE_OUT_CPL_RO_SHIFT 6
-#define BCHP_PCIE_0_MISC_MISC_CTRL_PCIE_OUT_CPL_RO_DEFAULT 0x00000000
-
-/* PCIE_0_MISC :: MISC_CTRL :: PCIE_IN_CPL_RO [05:05] */
-#define BCHP_PCIE_0_MISC_MISC_CTRL_PCIE_IN_CPL_RO_MASK 0x00000020
-#define BCHP_PCIE_0_MISC_MISC_CTRL_PCIE_IN_CPL_RO_SHIFT 5
-#define BCHP_PCIE_0_MISC_MISC_CTRL_PCIE_IN_CPL_RO_DEFAULT 0x00000000
-
-/* PCIE_0_MISC :: MISC_CTRL :: SCB2_SIZE [04:00] */
-#define BCHP_PCIE_0_MISC_MISC_CTRL_SCB2_SIZE_MASK 0x0000001f
-#define BCHP_PCIE_0_MISC_MISC_CTRL_SCB2_SIZE_SHIFT 0
-#define BCHP_PCIE_0_MISC_MISC_CTRL_SCB2_SIZE_DEFAULT 0x00000000
-
-/***************************************************************************
- *CPU_2_PCIE_MEM_WIN0_LO - CPU to PCIe Memory Window 0 Low
- ***************************************************************************/
-/* PCIE_0_MISC :: CPU_2_PCIE_MEM_WIN0_LO :: BASE_ADDR [31:20] */
-#define BCHP_PCIE_0_MISC_CPU_2_PCIE_MEM_WIN0_LO_BASE_ADDR_MASK 0xfff00000
-#define BCHP_PCIE_0_MISC_CPU_2_PCIE_MEM_WIN0_LO_BASE_ADDR_SHIFT 20
-#define BCHP_PCIE_0_MISC_CPU_2_PCIE_MEM_WIN0_LO_BASE_ADDR_DEFAULT 0x00000000
-
-/* PCIE_0_MISC :: CPU_2_PCIE_MEM_WIN0_LO :: reserved0 [19:02] */
-#define BCHP_PCIE_0_MISC_CPU_2_PCIE_MEM_WIN0_LO_reserved0_MASK 0x000ffffc
-#define BCHP_PCIE_0_MISC_CPU_2_PCIE_MEM_WIN0_LO_reserved0_SHIFT 2
-
-/* PCIE_0_MISC :: CPU_2_PCIE_MEM_WIN0_LO :: ENDIAN_MODE [01:00] */
-#define BCHP_PCIE_0_MISC_CPU_2_PCIE_MEM_WIN0_LO_ENDIAN_MODE_MASK 0x00000003
-#define BCHP_PCIE_0_MISC_CPU_2_PCIE_MEM_WIN0_LO_ENDIAN_MODE_SHIFT 0
-#define BCHP_PCIE_0_MISC_CPU_2_PCIE_MEM_WIN0_LO_ENDIAN_MODE_DEFAULT 0x00000000
-
-/***************************************************************************
- *CPU_2_PCIE_MEM_WIN0_HI - CPU to PCIe Memory Window 0 High
- ***************************************************************************/
-/* PCIE_0_MISC :: CPU_2_PCIE_MEM_WIN0_HI :: BASE_ADDR [31:00] */
-#define BCHP_PCIE_0_MISC_CPU_2_PCIE_MEM_WIN0_HI_BASE_ADDR_MASK 0xffffffff
-#define BCHP_PCIE_0_MISC_CPU_2_PCIE_MEM_WIN0_HI_BASE_ADDR_SHIFT 0
-#define BCHP_PCIE_0_MISC_CPU_2_PCIE_MEM_WIN0_HI_BASE_ADDR_DEFAULT 0x00000000
-
-/***************************************************************************
- *CPU_2_PCIE_MEM_WIN1_LO - CPU to PCIe Memory Window 1 Low
- ***************************************************************************/
-/* PCIE_0_MISC :: CPU_2_PCIE_MEM_WIN1_LO :: BASE_ADDR [31:20] */
-#define BCHP_PCIE_0_MISC_CPU_2_PCIE_MEM_WIN1_LO_BASE_ADDR_MASK 0xfff00000
-#define BCHP_PCIE_0_MISC_CPU_2_PCIE_MEM_WIN1_LO_BASE_ADDR_SHIFT 20
-#define BCHP_PCIE_0_MISC_CPU_2_PCIE_MEM_WIN1_LO_BASE_ADDR_DEFAULT 0x00000000
-
-/* PCIE_0_MISC :: CPU_2_PCIE_MEM_WIN1_LO :: reserved0 [19:02] */
-#define BCHP_PCIE_0_MISC_CPU_2_PCIE_MEM_WIN1_LO_reserved0_MASK 0x000ffffc
-#define BCHP_PCIE_0_MISC_CPU_2_PCIE_MEM_WIN1_LO_reserved0_SHIFT 2
-
-/* PCIE_0_MISC :: CPU_2_PCIE_MEM_WIN1_LO :: ENDIAN_MODE [01:00] */
-#define BCHP_PCIE_0_MISC_CPU_2_PCIE_MEM_WIN1_LO_ENDIAN_MODE_MASK 0x00000003
-#define BCHP_PCIE_0_MISC_CPU_2_PCIE_MEM_WIN1_LO_ENDIAN_MODE_SHIFT 0
-#define BCHP_PCIE_0_MISC_CPU_2_PCIE_MEM_WIN1_LO_ENDIAN_MODE_DEFAULT 0x00000000
-
-/***************************************************************************
- *CPU_2_PCIE_MEM_WIN1_HI - CPU to PCIe Memory Window 1 High
- ***************************************************************************/
-/* PCIE_0_MISC :: CPU_2_PCIE_MEM_WIN1_HI :: BASE_ADDR [31:00] */
-#define BCHP_PCIE_0_MISC_CPU_2_PCIE_MEM_WIN1_HI_BASE_ADDR_MASK 0xffffffff
-#define BCHP_PCIE_0_MISC_CPU_2_PCIE_MEM_WIN1_HI_BASE_ADDR_SHIFT 0
-#define BCHP_PCIE_0_MISC_CPU_2_PCIE_MEM_WIN1_HI_BASE_ADDR_DEFAULT 0x00000000
-
-/***************************************************************************
- *CPU_2_PCIE_MEM_WIN2_LO - CPU to PCIe Memory Window 2 Low
- ***************************************************************************/
-/* PCIE_0_MISC :: CPU_2_PCIE_MEM_WIN2_LO :: BASE_ADDR [31:20] */
-#define BCHP_PCIE_0_MISC_CPU_2_PCIE_MEM_WIN2_LO_BASE_ADDR_MASK 0xfff00000
-#define BCHP_PCIE_0_MISC_CPU_2_PCIE_MEM_WIN2_LO_BASE_ADDR_SHIFT 20
-#define BCHP_PCIE_0_MISC_CPU_2_PCIE_MEM_WIN2_LO_BASE_ADDR_DEFAULT 0x00000000
-
-/* PCIE_0_MISC :: CPU_2_PCIE_MEM_WIN2_LO :: reserved0 [19:02] */
-#define BCHP_PCIE_0_MISC_CPU_2_PCIE_MEM_WIN2_LO_reserved0_MASK 0x000ffffc
-#define BCHP_PCIE_0_MISC_CPU_2_PCIE_MEM_WIN2_LO_reserved0_SHIFT 2
-
-/* PCIE_0_MISC :: CPU_2_PCIE_MEM_WIN2_LO :: ENDIAN_MODE [01:00] */
-#define BCHP_PCIE_0_MISC_CPU_2_PCIE_MEM_WIN2_LO_ENDIAN_MODE_MASK 0x00000003
-#define BCHP_PCIE_0_MISC_CPU_2_PCIE_MEM_WIN2_LO_ENDIAN_MODE_SHIFT 0
-#define BCHP_PCIE_0_MISC_CPU_2_PCIE_MEM_WIN2_LO_ENDIAN_MODE_DEFAULT 0x00000000
-
-/***************************************************************************
- *CPU_2_PCIE_MEM_WIN2_HI - CPU to PCIe Memory Window 2 High
- ***************************************************************************/
-/* PCIE_0_MISC :: CPU_2_PCIE_MEM_WIN2_HI :: BASE_ADDR [31:00] */
-#define BCHP_PCIE_0_MISC_CPU_2_PCIE_MEM_WIN2_HI_BASE_ADDR_MASK 0xffffffff
-#define BCHP_PCIE_0_MISC_CPU_2_PCIE_MEM_WIN2_HI_BASE_ADDR_SHIFT 0
-#define BCHP_PCIE_0_MISC_CPU_2_PCIE_MEM_WIN2_HI_BASE_ADDR_DEFAULT 0x00000000
-
-/***************************************************************************
- *CPU_2_PCIE_MEM_WIN3_LO - CPU to PCIe Memory Window 3 Low
- ***************************************************************************/
-/* PCIE_0_MISC :: CPU_2_PCIE_MEM_WIN3_LO :: BASE_ADDR [31:20] */
-#define BCHP_PCIE_0_MISC_CPU_2_PCIE_MEM_WIN3_LO_BASE_ADDR_MASK 0xfff00000
-#define BCHP_PCIE_0_MISC_CPU_2_PCIE_MEM_WIN3_LO_BASE_ADDR_SHIFT 20
-#define BCHP_PCIE_0_MISC_CPU_2_PCIE_MEM_WIN3_LO_BASE_ADDR_DEFAULT 0x00000000
-
-/* PCIE_0_MISC :: CPU_2_PCIE_MEM_WIN3_LO :: reserved0 [19:02] */
-#define BCHP_PCIE_0_MISC_CPU_2_PCIE_MEM_WIN3_LO_reserved0_MASK 0x000ffffc
-#define BCHP_PCIE_0_MISC_CPU_2_PCIE_MEM_WIN3_LO_reserved0_SHIFT 2
-
-/* PCIE_0_MISC :: CPU_2_PCIE_MEM_WIN3_LO :: ENDIAN_MODE [01:00] */
-#define BCHP_PCIE_0_MISC_CPU_2_PCIE_MEM_WIN3_LO_ENDIAN_MODE_MASK 0x00000003
-#define BCHP_PCIE_0_MISC_CPU_2_PCIE_MEM_WIN3_LO_ENDIAN_MODE_SHIFT 0
-#define BCHP_PCIE_0_MISC_CPU_2_PCIE_MEM_WIN3_LO_ENDIAN_MODE_DEFAULT 0x00000000
-
-/***************************************************************************
- *CPU_2_PCIE_MEM_WIN3_HI - CPU to PCIe Memory Window 3 High
- ***************************************************************************/
-/* PCIE_0_MISC :: CPU_2_PCIE_MEM_WIN3_HI :: BASE_ADDR [31:00] */
-#define BCHP_PCIE_0_MISC_CPU_2_PCIE_MEM_WIN3_HI_BASE_ADDR_MASK 0xffffffff
-#define BCHP_PCIE_0_MISC_CPU_2_PCIE_MEM_WIN3_HI_BASE_ADDR_SHIFT 0
-#define BCHP_PCIE_0_MISC_CPU_2_PCIE_MEM_WIN3_HI_BASE_ADDR_DEFAULT 0x00000000
-
-/***************************************************************************
- *RC_BAR1_CONFIG_LO - RC BAR1 Configuration Low Register
- ***************************************************************************/
-/* PCIE_0_MISC :: RC_BAR1_CONFIG_LO :: MATCH_ADDRESS [31:12] */
-#define BCHP_PCIE_0_MISC_RC_BAR1_CONFIG_LO_MATCH_ADDRESS_MASK 0xfffff000
-#define BCHP_PCIE_0_MISC_RC_BAR1_CONFIG_LO_MATCH_ADDRESS_SHIFT 12
-#define BCHP_PCIE_0_MISC_RC_BAR1_CONFIG_LO_MATCH_ADDRESS_DEFAULT 0x00000000
-
-/* PCIE_0_MISC :: RC_BAR1_CONFIG_LO :: reserved0 [11:05] */
-#define BCHP_PCIE_0_MISC_RC_BAR1_CONFIG_LO_reserved0_MASK 0x00000fe0
-#define BCHP_PCIE_0_MISC_RC_BAR1_CONFIG_LO_reserved0_SHIFT 5
-
-/* PCIE_0_MISC :: RC_BAR1_CONFIG_LO :: SIZE [04:00] */
-#define BCHP_PCIE_0_MISC_RC_BAR1_CONFIG_LO_SIZE_MASK 0x0000001f
-#define BCHP_PCIE_0_MISC_RC_BAR1_CONFIG_LO_SIZE_SHIFT 0
-#define BCHP_PCIE_0_MISC_RC_BAR1_CONFIG_LO_SIZE_DEFAULT 0x00000000
-
-/***************************************************************************
- *RC_BAR1_CONFIG_HI - RC BAR1 Configuration High Register
- ***************************************************************************/
-/* PCIE_0_MISC :: RC_BAR1_CONFIG_HI :: MATCH_ADDRESS [31:00] */
-#define BCHP_PCIE_0_MISC_RC_BAR1_CONFIG_HI_MATCH_ADDRESS_MASK 0xffffffff
-#define BCHP_PCIE_0_MISC_RC_BAR1_CONFIG_HI_MATCH_ADDRESS_SHIFT 0
-#define BCHP_PCIE_0_MISC_RC_BAR1_CONFIG_HI_MATCH_ADDRESS_DEFAULT 0x00000000
-
-/***************************************************************************
- *RC_BAR2_CONFIG_LO - RC BAR2 Configuration Low Register
- ***************************************************************************/
-/* PCIE_0_MISC :: RC_BAR2_CONFIG_LO :: MATCH_ADDRESS [31:12] */
-#define BCHP_PCIE_0_MISC_RC_BAR2_CONFIG_LO_MATCH_ADDRESS_MASK 0xfffff000
-#define BCHP_PCIE_0_MISC_RC_BAR2_CONFIG_LO_MATCH_ADDRESS_SHIFT 12
-#define BCHP_PCIE_0_MISC_RC_BAR2_CONFIG_LO_MATCH_ADDRESS_DEFAULT 0x00000000
-
-/* PCIE_0_MISC :: RC_BAR2_CONFIG_LO :: reserved0 [11:05] */
-#define BCHP_PCIE_0_MISC_RC_BAR2_CONFIG_LO_reserved0_MASK 0x00000fe0
-#define BCHP_PCIE_0_MISC_RC_BAR2_CONFIG_LO_reserved0_SHIFT 5
-
-/* PCIE_0_MISC :: RC_BAR2_CONFIG_LO :: SIZE [04:00] */
-#define BCHP_PCIE_0_MISC_RC_BAR2_CONFIG_LO_SIZE_MASK 0x0000001f
-#define BCHP_PCIE_0_MISC_RC_BAR2_CONFIG_LO_SIZE_SHIFT 0
-#define BCHP_PCIE_0_MISC_RC_BAR2_CONFIG_LO_SIZE_DEFAULT 0x00000000
-
-/***************************************************************************
- *RC_BAR2_CONFIG_HI - RC BAR2 Configuration High Register
- ***************************************************************************/
-/* PCIE_0_MISC :: RC_BAR2_CONFIG_HI :: MATCH_ADDRESS [31:00] */
-#define BCHP_PCIE_0_MISC_RC_BAR2_CONFIG_HI_MATCH_ADDRESS_MASK 0xffffffff
-#define BCHP_PCIE_0_MISC_RC_BAR2_CONFIG_HI_MATCH_ADDRESS_SHIFT 0
-#define BCHP_PCIE_0_MISC_RC_BAR2_CONFIG_HI_MATCH_ADDRESS_DEFAULT 0x00000000
-
-/***************************************************************************
- *RC_BAR3_CONFIG_LO - RC BAR3 Configuration Low Register
- ***************************************************************************/
-/* PCIE_0_MISC :: RC_BAR3_CONFIG_LO :: MATCH_ADDRESS [31:12] */
-#define BCHP_PCIE_0_MISC_RC_BAR3_CONFIG_LO_MATCH_ADDRESS_MASK 0xfffff000
-#define BCHP_PCIE_0_MISC_RC_BAR3_CONFIG_LO_MATCH_ADDRESS_SHIFT 12
-#define BCHP_PCIE_0_MISC_RC_BAR3_CONFIG_LO_MATCH_ADDRESS_DEFAULT 0x00000000
-
-/* PCIE_0_MISC :: RC_BAR3_CONFIG_LO :: reserved0 [11:05] */
-#define BCHP_PCIE_0_MISC_RC_BAR3_CONFIG_LO_reserved0_MASK 0x00000fe0
-#define BCHP_PCIE_0_MISC_RC_BAR3_CONFIG_LO_reserved0_SHIFT 5
-
-/* PCIE_0_MISC :: RC_BAR3_CONFIG_LO :: SIZE [04:00] */
-#define BCHP_PCIE_0_MISC_RC_BAR3_CONFIG_LO_SIZE_MASK 0x0000001f
-#define BCHP_PCIE_0_MISC_RC_BAR3_CONFIG_LO_SIZE_SHIFT 0
-#define BCHP_PCIE_0_MISC_RC_BAR3_CONFIG_LO_SIZE_DEFAULT 0x00000000
-
-/***************************************************************************
- *RC_BAR3_CONFIG_HI - RC BAR3 Configuration High Register
- ***************************************************************************/
-/* PCIE_0_MISC :: RC_BAR3_CONFIG_HI :: MATCH_ADDRESS [31:00] */
-#define BCHP_PCIE_0_MISC_RC_BAR3_CONFIG_HI_MATCH_ADDRESS_MASK 0xffffffff
-#define BCHP_PCIE_0_MISC_RC_BAR3_CONFIG_HI_MATCH_ADDRESS_SHIFT 0
-#define BCHP_PCIE_0_MISC_RC_BAR3_CONFIG_HI_MATCH_ADDRESS_DEFAULT 0x00000000
-
-/***************************************************************************
- *MSI_BAR_CONFIG_LO - Message Signaled Interrupt Base Address Low Register
- ***************************************************************************/
-/* PCIE_0_MISC :: MSI_BAR_CONFIG_LO :: MATCH_ADDRESS [31:02] */
-#define BCHP_PCIE_0_MISC_MSI_BAR_CONFIG_LO_MATCH_ADDRESS_MASK 0xfffffffc
-#define BCHP_PCIE_0_MISC_MSI_BAR_CONFIG_LO_MATCH_ADDRESS_SHIFT 2
-#define BCHP_PCIE_0_MISC_MSI_BAR_CONFIG_LO_MATCH_ADDRESS_DEFAULT 0x00000000
-
-/* PCIE_0_MISC :: MSI_BAR_CONFIG_LO :: reserved0 [01:01] */
-#define BCHP_PCIE_0_MISC_MSI_BAR_CONFIG_LO_reserved0_MASK 0x00000002
-#define BCHP_PCIE_0_MISC_MSI_BAR_CONFIG_LO_reserved0_SHIFT 1
-
-/* PCIE_0_MISC :: MSI_BAR_CONFIG_LO :: ENABLE [00:00] */
-#define BCHP_PCIE_0_MISC_MSI_BAR_CONFIG_LO_ENABLE_MASK 0x00000001
-#define BCHP_PCIE_0_MISC_MSI_BAR_CONFIG_LO_ENABLE_SHIFT 0
-#define BCHP_PCIE_0_MISC_MSI_BAR_CONFIG_LO_ENABLE_DEFAULT 0x00000000
-
-/***************************************************************************
- *MSI_BAR_CONFIG_HI - Message Signaled Interrupt Base Address High Register
- ***************************************************************************/
-/* PCIE_0_MISC :: MSI_BAR_CONFIG_HI :: MATCH_ADDRESS [31:00] */
-#define BCHP_PCIE_0_MISC_MSI_BAR_CONFIG_HI_MATCH_ADDRESS_MASK 0xffffffff
-#define BCHP_PCIE_0_MISC_MSI_BAR_CONFIG_HI_MATCH_ADDRESS_SHIFT 0
-#define BCHP_PCIE_0_MISC_MSI_BAR_CONFIG_HI_MATCH_ADDRESS_DEFAULT 0x00000000
-
-/***************************************************************************
- *MSI_DATA_CONFIG - Message Signaled Interrupt Data Configuration Register
- ***************************************************************************/
-/* PCIE_0_MISC :: MSI_DATA_CONFIG :: MASK [31:16] */
-#define BCHP_PCIE_0_MISC_MSI_DATA_CONFIG_MASK_MASK 0xffff0000
-#define BCHP_PCIE_0_MISC_MSI_DATA_CONFIG_MASK_SHIFT 16
-#define BCHP_PCIE_0_MISC_MSI_DATA_CONFIG_MASK_DEFAULT 0x00000000
-
-/* PCIE_0_MISC :: MSI_DATA_CONFIG :: DATA [15:00] */
-#define BCHP_PCIE_0_MISC_MSI_DATA_CONFIG_DATA_MASK 0x0000ffff
-#define BCHP_PCIE_0_MISC_MSI_DATA_CONFIG_DATA_SHIFT 0
-#define BCHP_PCIE_0_MISC_MSI_DATA_CONFIG_DATA_DEFAULT 0x00000000
-
-/***************************************************************************
- *RC_BAD_ADDRESS_LO - RC Bad Address Register Low
- ***************************************************************************/
-/* PCIE_0_MISC :: RC_BAD_ADDRESS_LO :: ADDRESS [31:02] */
-#define BCHP_PCIE_0_MISC_RC_BAD_ADDRESS_LO_ADDRESS_MASK 0xfffffffc
-#define BCHP_PCIE_0_MISC_RC_BAD_ADDRESS_LO_ADDRESS_SHIFT 2
-#define BCHP_PCIE_0_MISC_RC_BAD_ADDRESS_LO_ADDRESS_DEFAULT 0x00000000
-
-/* PCIE_0_MISC :: RC_BAD_ADDRESS_LO :: reserved0 [01:01] */
-#define BCHP_PCIE_0_MISC_RC_BAD_ADDRESS_LO_reserved0_MASK 0x00000002
-#define BCHP_PCIE_0_MISC_RC_BAD_ADDRESS_LO_reserved0_SHIFT 1
-
-/* PCIE_0_MISC :: RC_BAD_ADDRESS_LO :: VALID [00:00] */
-#define BCHP_PCIE_0_MISC_RC_BAD_ADDRESS_LO_VALID_MASK 0x00000001
-#define BCHP_PCIE_0_MISC_RC_BAD_ADDRESS_LO_VALID_SHIFT 0
-#define BCHP_PCIE_0_MISC_RC_BAD_ADDRESS_LO_VALID_DEFAULT 0x00000000
-
-/***************************************************************************
- *RC_BAD_ADDRESS_HI - RC Bad Address Register High
- ***************************************************************************/
-/* PCIE_0_MISC :: RC_BAD_ADDRESS_HI :: ADDRESS [31:00] */
-#define BCHP_PCIE_0_MISC_RC_BAD_ADDRESS_HI_ADDRESS_MASK 0xffffffff
-#define BCHP_PCIE_0_MISC_RC_BAD_ADDRESS_HI_ADDRESS_SHIFT 0
-#define BCHP_PCIE_0_MISC_RC_BAD_ADDRESS_HI_ADDRESS_DEFAULT 0x00000000
-
-/***************************************************************************
- *RC_BAD_DATA - RC Bad Data Register
- ***************************************************************************/
-/* PCIE_0_MISC :: RC_BAD_DATA :: DATA [31:00] */
-#define BCHP_PCIE_0_MISC_RC_BAD_DATA_DATA_MASK 0xffffffff
-#define BCHP_PCIE_0_MISC_RC_BAD_DATA_DATA_SHIFT 0
-#define BCHP_PCIE_0_MISC_RC_BAD_DATA_DATA_DEFAULT 0x00000000
-
-/***************************************************************************
- *RC_CONFIG_RETRY_TIMEOUT - RC Configuration Retry Timeout Register
- ***************************************************************************/
-/* PCIE_0_MISC :: RC_CONFIG_RETRY_TIMEOUT :: TIMER_VALUE [31:00] */
-#define BCHP_PCIE_0_MISC_RC_CONFIG_RETRY_TIMEOUT_TIMER_VALUE_MASK 0xffffffff
-#define BCHP_PCIE_0_MISC_RC_CONFIG_RETRY_TIMEOUT_TIMER_VALUE_SHIFT 0
-#define BCHP_PCIE_0_MISC_RC_CONFIG_RETRY_TIMEOUT_TIMER_VALUE_DEFAULT 0x00000000
-
-/***************************************************************************
- *EOI_CTRL - End of Interrupt Control Register
- ***************************************************************************/
-/* PCIE_0_MISC :: EOI_CTRL :: reserved0 [31:01] */
-#define BCHP_PCIE_0_MISC_EOI_CTRL_reserved0_MASK 0xfffffffe
-#define BCHP_PCIE_0_MISC_EOI_CTRL_reserved0_SHIFT 1
-
-/* PCIE_0_MISC :: EOI_CTRL :: EOI [00:00] */
-#define BCHP_PCIE_0_MISC_EOI_CTRL_EOI_MASK 0x00000001
-#define BCHP_PCIE_0_MISC_EOI_CTRL_EOI_SHIFT 0
-#define BCHP_PCIE_0_MISC_EOI_CTRL_EOI_DEFAULT 0x00000000
-
-/***************************************************************************
- *PCIE_CTRL - PCIe Control
- ***************************************************************************/
-/* PCIE_0_MISC :: PCIE_CTRL :: reserved0 [31:02] */
-#define BCHP_PCIE_0_MISC_PCIE_CTRL_reserved0_MASK 0xfffffffc
-#define BCHP_PCIE_0_MISC_PCIE_CTRL_reserved0_SHIFT 2
-
-/* PCIE_0_MISC :: PCIE_CTRL :: PCIE_PME_REQUEST [01:01] */
-#define BCHP_PCIE_0_MISC_PCIE_CTRL_PCIE_PME_REQUEST_MASK 0x00000002
-#define BCHP_PCIE_0_MISC_PCIE_CTRL_PCIE_PME_REQUEST_SHIFT 1
-#define BCHP_PCIE_0_MISC_PCIE_CTRL_PCIE_PME_REQUEST_DEFAULT 0x00000000
-
-/* PCIE_0_MISC :: PCIE_CTRL :: PCIE_L23_REQUEST [00:00] */
-#define BCHP_PCIE_0_MISC_PCIE_CTRL_PCIE_L23_REQUEST_MASK 0x00000001
-#define BCHP_PCIE_0_MISC_PCIE_CTRL_PCIE_L23_REQUEST_SHIFT 0
-#define BCHP_PCIE_0_MISC_PCIE_CTRL_PCIE_L23_REQUEST_DEFAULT 0x00000000
-
-/***************************************************************************
- *PCIE_STATUS - PCIe Status
- ***************************************************************************/
-/* PCIE_0_MISC :: PCIE_STATUS :: reserved0 [31:13] */
-#define BCHP_PCIE_0_MISC_PCIE_STATUS_reserved0_MASK 0xffffe000
-#define BCHP_PCIE_0_MISC_PCIE_STATUS_reserved0_SHIFT 13
-
-/* PCIE_0_MISC :: PCIE_STATUS :: PCIE_SSC_STATUS [12:12] */
-#define BCHP_PCIE_0_MISC_PCIE_STATUS_PCIE_SSC_STATUS_MASK 0x00001000
-#define BCHP_PCIE_0_MISC_PCIE_STATUS_PCIE_SSC_STATUS_SHIFT 12
-#define BCHP_PCIE_0_MISC_PCIE_STATUS_PCIE_SSC_STATUS_DEFAULT 0x00000000
-
-/* PCIE_0_MISC :: PCIE_STATUS :: PCIE_PM_STATE [11:10] */
-#define BCHP_PCIE_0_MISC_PCIE_STATUS_PCIE_PM_STATE_MASK 0x00000c00
-#define BCHP_PCIE_0_MISC_PCIE_STATUS_PCIE_PM_STATE_SHIFT 10
-#define BCHP_PCIE_0_MISC_PCIE_STATUS_PCIE_PM_STATE_DEFAULT 0x00000000
-
-/* PCIE_0_MISC :: PCIE_STATUS :: PCIE_WAKE [09:09] */
-#define BCHP_PCIE_0_MISC_PCIE_STATUS_PCIE_WAKE_MASK 0x00000200
-#define BCHP_PCIE_0_MISC_PCIE_STATUS_PCIE_WAKE_SHIFT 9
-#define BCHP_PCIE_0_MISC_PCIE_STATUS_PCIE_WAKE_DEFAULT 0x00000000
-
-/* PCIE_0_MISC :: PCIE_STATUS :: PCIE_PME_EVENT [08:08] */
-#define BCHP_PCIE_0_MISC_PCIE_STATUS_PCIE_PME_EVENT_MASK 0x00000100
-#define BCHP_PCIE_0_MISC_PCIE_STATUS_PCIE_PME_EVENT_SHIFT 8
-#define BCHP_PCIE_0_MISC_PCIE_STATUS_PCIE_PME_EVENT_DEFAULT 0x00000000
-
-/* PCIE_0_MISC :: PCIE_STATUS :: PCIE_PORT [07:07] */
-#define BCHP_PCIE_0_MISC_PCIE_STATUS_PCIE_PORT_MASK 0x00000080
-#define BCHP_PCIE_0_MISC_PCIE_STATUS_PCIE_PORT_SHIFT 7
-
-/* PCIE_0_MISC :: PCIE_STATUS :: PCIE_LINK_IN_L23 [06:06] */
-#define BCHP_PCIE_0_MISC_PCIE_STATUS_PCIE_LINK_IN_L23_MASK 0x00000040
-#define BCHP_PCIE_0_MISC_PCIE_STATUS_PCIE_LINK_IN_L23_SHIFT 6
-#define BCHP_PCIE_0_MISC_PCIE_STATUS_PCIE_LINK_IN_L23_DEFAULT 0x00000000
-
-/* PCIE_0_MISC :: PCIE_STATUS :: PCIE_DL_ACTIVE [05:05] */
-#define BCHP_PCIE_0_MISC_PCIE_STATUS_PCIE_DL_ACTIVE_MASK 0x00000020
-#define BCHP_PCIE_0_MISC_PCIE_STATUS_PCIE_DL_ACTIVE_SHIFT 5
-#define BCHP_PCIE_0_MISC_PCIE_STATUS_PCIE_DL_ACTIVE_DEFAULT 0x00000000
-
-/* PCIE_0_MISC :: PCIE_STATUS :: PCIE_PHYLINKUP [04:04] */
-#define BCHP_PCIE_0_MISC_PCIE_STATUS_PCIE_PHYLINKUP_MASK 0x00000010
-#define BCHP_PCIE_0_MISC_PCIE_STATUS_PCIE_PHYLINKUP_SHIFT 4
-#define BCHP_PCIE_0_MISC_PCIE_STATUS_PCIE_PHYLINKUP_DEFAULT 0x00000000
-
-/* PCIE_0_MISC :: PCIE_STATUS :: PCIE_ERR_STATUS [03:00] */
-#define BCHP_PCIE_0_MISC_PCIE_STATUS_PCIE_ERR_STATUS_MASK 0x0000000f
-#define BCHP_PCIE_0_MISC_PCIE_STATUS_PCIE_ERR_STATUS_SHIFT 0
-#define BCHP_PCIE_0_MISC_PCIE_STATUS_PCIE_ERR_STATUS_DEFAULT 0x00000000
-
-/***************************************************************************
- *REVISION - PCIe Revision
- ***************************************************************************/
-/* PCIE_0_MISC :: REVISION :: reserved0 [31:16] */
-#define BCHP_PCIE_0_MISC_REVISION_reserved0_MASK 0xffff0000
-#define BCHP_PCIE_0_MISC_REVISION_reserved0_SHIFT 16
-
-/* PCIE_0_MISC :: REVISION :: MAJOR [15:08] */
-#define BCHP_PCIE_0_MISC_REVISION_MAJOR_MASK 0x0000ff00
-#define BCHP_PCIE_0_MISC_REVISION_MAJOR_SHIFT 8
-#define BCHP_PCIE_0_MISC_REVISION_MAJOR_DEFAULT 0x00000003
-
-/* PCIE_0_MISC :: REVISION :: MINOR [07:00] */
-#define BCHP_PCIE_0_MISC_REVISION_MINOR_MASK 0x000000ff
-#define BCHP_PCIE_0_MISC_REVISION_MINOR_SHIFT 0
-#define BCHP_PCIE_0_MISC_REVISION_MINOR_DEFAULT 0x00000000
-
-/***************************************************************************
- *CPU_2_PCIE_MEM_WIN0_BASE_LIMIT - CPU to PCIe Memory Window 0 base/limit
- ***************************************************************************/
-/* PCIE_0_MISC :: CPU_2_PCIE_MEM_WIN0_BASE_LIMIT :: LIMIT [31:20] */
-#define BCHP_PCIE_0_MISC_CPU_2_PCIE_MEM_WIN0_BASE_LIMIT_LIMIT_MASK 0xfff00000
-#define BCHP_PCIE_0_MISC_CPU_2_PCIE_MEM_WIN0_BASE_LIMIT_LIMIT_SHIFT 20
-#define BCHP_PCIE_0_MISC_CPU_2_PCIE_MEM_WIN0_BASE_LIMIT_LIMIT_DEFAULT 0x00000000
-
-/* PCIE_0_MISC :: CPU_2_PCIE_MEM_WIN0_BASE_LIMIT :: reserved0 [19:16] */
-#define BCHP_PCIE_0_MISC_CPU_2_PCIE_MEM_WIN0_BASE_LIMIT_reserved0_MASK 0x000f0000
-#define BCHP_PCIE_0_MISC_CPU_2_PCIE_MEM_WIN0_BASE_LIMIT_reserved0_SHIFT 16
-
-/* PCIE_0_MISC :: CPU_2_PCIE_MEM_WIN0_BASE_LIMIT :: BASE [15:04] */
-#define BCHP_PCIE_0_MISC_CPU_2_PCIE_MEM_WIN0_BASE_LIMIT_BASE_MASK 0x0000fff0
-#define BCHP_PCIE_0_MISC_CPU_2_PCIE_MEM_WIN0_BASE_LIMIT_BASE_SHIFT 4
-#define BCHP_PCIE_0_MISC_CPU_2_PCIE_MEM_WIN0_BASE_LIMIT_BASE_DEFAULT 0x00000001
-
-/* PCIE_0_MISC :: CPU_2_PCIE_MEM_WIN0_BASE_LIMIT :: reserved1 [03:00] */
-#define BCHP_PCIE_0_MISC_CPU_2_PCIE_MEM_WIN0_BASE_LIMIT_reserved1_MASK 0x0000000f
-#define BCHP_PCIE_0_MISC_CPU_2_PCIE_MEM_WIN0_BASE_LIMIT_reserved1_SHIFT 0
-
-/***************************************************************************
- *CPU_2_PCIE_MEM_WIN1_BASE_LIMIT - CPU to PCIe Memory Window 1 base/limit
- ***************************************************************************/
-/* PCIE_0_MISC :: CPU_2_PCIE_MEM_WIN1_BASE_LIMIT :: LIMIT [31:20] */
-#define BCHP_PCIE_0_MISC_CPU_2_PCIE_MEM_WIN1_BASE_LIMIT_LIMIT_MASK 0xfff00000
-#define BCHP_PCIE_0_MISC_CPU_2_PCIE_MEM_WIN1_BASE_LIMIT_LIMIT_SHIFT 20
-#define BCHP_PCIE_0_MISC_CPU_2_PCIE_MEM_WIN1_BASE_LIMIT_LIMIT_DEFAULT 0x00000000
-
-/* PCIE_0_MISC :: CPU_2_PCIE_MEM_WIN1_BASE_LIMIT :: reserved0 [19:16] */
-#define BCHP_PCIE_0_MISC_CPU_2_PCIE_MEM_WIN1_BASE_LIMIT_reserved0_MASK 0x000f0000
-#define BCHP_PCIE_0_MISC_CPU_2_PCIE_MEM_WIN1_BASE_LIMIT_reserved0_SHIFT 16
-
-/* PCIE_0_MISC :: CPU_2_PCIE_MEM_WIN1_BASE_LIMIT :: BASE [15:04] */
-#define BCHP_PCIE_0_MISC_CPU_2_PCIE_MEM_WIN1_BASE_LIMIT_BASE_MASK 0x0000fff0
-#define BCHP_PCIE_0_MISC_CPU_2_PCIE_MEM_WIN1_BASE_LIMIT_BASE_SHIFT 4
-#define BCHP_PCIE_0_MISC_CPU_2_PCIE_MEM_WIN1_BASE_LIMIT_BASE_DEFAULT 0x00000001
-
-/* PCIE_0_MISC :: CPU_2_PCIE_MEM_WIN1_BASE_LIMIT :: reserved1 [03:00] */
-#define BCHP_PCIE_0_MISC_CPU_2_PCIE_MEM_WIN1_BASE_LIMIT_reserved1_MASK 0x0000000f
-#define BCHP_PCIE_0_MISC_CPU_2_PCIE_MEM_WIN1_BASE_LIMIT_reserved1_SHIFT 0
-
-/***************************************************************************
- *CPU_2_PCIE_MEM_WIN2_BASE_LIMIT - CPU to PCIe Memory Window 2 base/limit
- ***************************************************************************/
-/* PCIE_0_MISC :: CPU_2_PCIE_MEM_WIN2_BASE_LIMIT :: LIMIT [31:20] */
-#define BCHP_PCIE_0_MISC_CPU_2_PCIE_MEM_WIN2_BASE_LIMIT_LIMIT_MASK 0xfff00000
-#define BCHP_PCIE_0_MISC_CPU_2_PCIE_MEM_WIN2_BASE_LIMIT_LIMIT_SHIFT 20
-#define BCHP_PCIE_0_MISC_CPU_2_PCIE_MEM_WIN2_BASE_LIMIT_LIMIT_DEFAULT 0x00000000
-
-/* PCIE_0_MISC :: CPU_2_PCIE_MEM_WIN2_BASE_LIMIT :: reserved0 [19:16] */
-#define BCHP_PCIE_0_MISC_CPU_2_PCIE_MEM_WIN2_BASE_LIMIT_reserved0_MASK 0x000f0000
-#define BCHP_PCIE_0_MISC_CPU_2_PCIE_MEM_WIN2_BASE_LIMIT_reserved0_SHIFT 16
-
-/* PCIE_0_MISC :: CPU_2_PCIE_MEM_WIN2_BASE_LIMIT :: BASE [15:04] */
-#define BCHP_PCIE_0_MISC_CPU_2_PCIE_MEM_WIN2_BASE_LIMIT_BASE_MASK 0x0000fff0
-#define BCHP_PCIE_0_MISC_CPU_2_PCIE_MEM_WIN2_BASE_LIMIT_BASE_SHIFT 4
-#define BCHP_PCIE_0_MISC_CPU_2_PCIE_MEM_WIN2_BASE_LIMIT_BASE_DEFAULT 0x00000001
-
-/* PCIE_0_MISC :: CPU_2_PCIE_MEM_WIN2_BASE_LIMIT :: reserved1 [03:00] */
-#define BCHP_PCIE_0_MISC_CPU_2_PCIE_MEM_WIN2_BASE_LIMIT_reserved1_MASK 0x0000000f
-#define BCHP_PCIE_0_MISC_CPU_2_PCIE_MEM_WIN2_BASE_LIMIT_reserved1_SHIFT 0
-
-/***************************************************************************
- *CPU_2_PCIE_MEM_WIN3_BASE_LIMIT - CPU to PCIe Memory Window 3 base/limit
- ***************************************************************************/
-/* PCIE_0_MISC :: CPU_2_PCIE_MEM_WIN3_BASE_LIMIT :: LIMIT [31:20] */
-#define BCHP_PCIE_0_MISC_CPU_2_PCIE_MEM_WIN3_BASE_LIMIT_LIMIT_MASK 0xfff00000
-#define BCHP_PCIE_0_MISC_CPU_2_PCIE_MEM_WIN3_BASE_LIMIT_LIMIT_SHIFT 20
-#define BCHP_PCIE_0_MISC_CPU_2_PCIE_MEM_WIN3_BASE_LIMIT_LIMIT_DEFAULT 0x00000000
-
-/* PCIE_0_MISC :: CPU_2_PCIE_MEM_WIN3_BASE_LIMIT :: reserved0 [19:16] */
-#define BCHP_PCIE_0_MISC_CPU_2_PCIE_MEM_WIN3_BASE_LIMIT_reserved0_MASK 0x000f0000
-#define BCHP_PCIE_0_MISC_CPU_2_PCIE_MEM_WIN3_BASE_LIMIT_reserved0_SHIFT 16
-
-/* PCIE_0_MISC :: CPU_2_PCIE_MEM_WIN3_BASE_LIMIT :: BASE [15:04] */
-#define BCHP_PCIE_0_MISC_CPU_2_PCIE_MEM_WIN3_BASE_LIMIT_BASE_MASK 0x0000fff0
-#define BCHP_PCIE_0_MISC_CPU_2_PCIE_MEM_WIN3_BASE_LIMIT_BASE_SHIFT 4
-#define BCHP_PCIE_0_MISC_CPU_2_PCIE_MEM_WIN3_BASE_LIMIT_BASE_DEFAULT 0x00000001
-
-/* PCIE_0_MISC :: CPU_2_PCIE_MEM_WIN3_BASE_LIMIT :: reserved1 [03:00] */
-#define BCHP_PCIE_0_MISC_CPU_2_PCIE_MEM_WIN3_BASE_LIMIT_reserved1_MASK 0x0000000f
-#define BCHP_PCIE_0_MISC_CPU_2_PCIE_MEM_WIN3_BASE_LIMIT_reserved1_SHIFT 0
-
-/***************************************************************************
- *CPU_2_PCIE_MEM_WIN0_BASE_HI - CPU to PCIe Memory Window 0 base high
- ***************************************************************************/
-/* PCIE_0_MISC :: CPU_2_PCIE_MEM_WIN0_BASE_HI :: reserved0 [31:08] */
-#define BCHP_PCIE_0_MISC_CPU_2_PCIE_MEM_WIN0_BASE_HI_reserved0_MASK 0xffffff00
-#define BCHP_PCIE_0_MISC_CPU_2_PCIE_MEM_WIN0_BASE_HI_reserved0_SHIFT 8
-
-/* PCIE_0_MISC :: CPU_2_PCIE_MEM_WIN0_BASE_HI :: BASE [07:00] */
-#define BCHP_PCIE_0_MISC_CPU_2_PCIE_MEM_WIN0_BASE_HI_BASE_MASK 0x000000ff
-#define BCHP_PCIE_0_MISC_CPU_2_PCIE_MEM_WIN0_BASE_HI_BASE_SHIFT 0
-#define BCHP_PCIE_0_MISC_CPU_2_PCIE_MEM_WIN0_BASE_HI_BASE_DEFAULT 0x00000000
-
-/***************************************************************************
- *CPU_2_PCIE_MEM_WIN0_LIMIT_HI - CPU to PCIe Memory Window 0 limit high
- ***************************************************************************/
-/* PCIE_0_MISC :: CPU_2_PCIE_MEM_WIN0_LIMIT_HI :: reserved0 [31:08] */
-#define BCHP_PCIE_0_MISC_CPU_2_PCIE_MEM_WIN0_LIMIT_HI_reserved0_MASK 0xffffff00
-#define BCHP_PCIE_0_MISC_CPU_2_PCIE_MEM_WIN0_LIMIT_HI_reserved0_SHIFT 8
-
-/* PCIE_0_MISC :: CPU_2_PCIE_MEM_WIN0_LIMIT_HI :: LIMIT [07:00] */
-#define BCHP_PCIE_0_MISC_CPU_2_PCIE_MEM_WIN0_LIMIT_HI_LIMIT_MASK 0x000000ff
-#define BCHP_PCIE_0_MISC_CPU_2_PCIE_MEM_WIN0_LIMIT_HI_LIMIT_SHIFT 0
-#define BCHP_PCIE_0_MISC_CPU_2_PCIE_MEM_WIN0_LIMIT_HI_LIMIT_DEFAULT 0x00000000
-
-/***************************************************************************
- *CPU_2_PCIE_MEM_WIN1_BASE_HI - CPU to PCIe Memory Window 1 base high
- ***************************************************************************/
-/* PCIE_0_MISC :: CPU_2_PCIE_MEM_WIN1_BASE_HI :: reserved0 [31:08] */
-#define BCHP_PCIE_0_MISC_CPU_2_PCIE_MEM_WIN1_BASE_HI_reserved0_MASK 0xffffff00
-#define BCHP_PCIE_0_MISC_CPU_2_PCIE_MEM_WIN1_BASE_HI_reserved0_SHIFT 8
-
-/* PCIE_0_MISC :: CPU_2_PCIE_MEM_WIN1_BASE_HI :: BASE [07:00] */
-#define BCHP_PCIE_0_MISC_CPU_2_PCIE_MEM_WIN1_BASE_HI_BASE_MASK 0x000000ff
-#define BCHP_PCIE_0_MISC_CPU_2_PCIE_MEM_WIN1_BASE_HI_BASE_SHIFT 0
-#define BCHP_PCIE_0_MISC_CPU_2_PCIE_MEM_WIN1_BASE_HI_BASE_DEFAULT 0x00000000
-
-/***************************************************************************
- *CPU_2_PCIE_MEM_WIN1_LIMIT_HI - CPU to PCIe Memory Window 1 limit high
- ***************************************************************************/
-/* PCIE_0_MISC :: CPU_2_PCIE_MEM_WIN1_LIMIT_HI :: reserved0 [31:08] */
-#define BCHP_PCIE_0_MISC_CPU_2_PCIE_MEM_WIN1_LIMIT_HI_reserved0_MASK 0xffffff00
-#define BCHP_PCIE_0_MISC_CPU_2_PCIE_MEM_WIN1_LIMIT_HI_reserved0_SHIFT 8
-
-/* PCIE_0_MISC :: CPU_2_PCIE_MEM_WIN1_LIMIT_HI :: LIMIT [07:00] */
-#define BCHP_PCIE_0_MISC_CPU_2_PCIE_MEM_WIN1_LIMIT_HI_LIMIT_MASK 0x000000ff
-#define BCHP_PCIE_0_MISC_CPU_2_PCIE_MEM_WIN1_LIMIT_HI_LIMIT_SHIFT 0
-#define BCHP_PCIE_0_MISC_CPU_2_PCIE_MEM_WIN1_LIMIT_HI_LIMIT_DEFAULT 0x00000000
-
-/***************************************************************************
- *CPU_2_PCIE_MEM_WIN2_BASE_HI - CPU to PCIe Memory Window 2 base high
- ***************************************************************************/
-/* PCIE_0_MISC :: CPU_2_PCIE_MEM_WIN2_BASE_HI :: reserved0 [31:08] */
-#define BCHP_PCIE_0_MISC_CPU_2_PCIE_MEM_WIN2_BASE_HI_reserved0_MASK 0xffffff00
-#define BCHP_PCIE_0_MISC_CPU_2_PCIE_MEM_WIN2_BASE_HI_reserved0_SHIFT 8
-
-/* PCIE_0_MISC :: CPU_2_PCIE_MEM_WIN2_BASE_HI :: BASE [07:00] */
-#define BCHP_PCIE_0_MISC_CPU_2_PCIE_MEM_WIN2_BASE_HI_BASE_MASK 0x000000ff
-#define BCHP_PCIE_0_MISC_CPU_2_PCIE_MEM_WIN2_BASE_HI_BASE_SHIFT 0
-#define BCHP_PCIE_0_MISC_CPU_2_PCIE_MEM_WIN2_BASE_HI_BASE_DEFAULT 0x00000000
-
-/***************************************************************************
- *CPU_2_PCIE_MEM_WIN2_LIMIT_HI - CPU to PCIe Memory Window 2 limit high
- ***************************************************************************/
-/* PCIE_0_MISC :: CPU_2_PCIE_MEM_WIN2_LIMIT_HI :: reserved0 [31:08] */
-#define BCHP_PCIE_0_MISC_CPU_2_PCIE_MEM_WIN2_LIMIT_HI_reserved0_MASK 0xffffff00
-#define BCHP_PCIE_0_MISC_CPU_2_PCIE_MEM_WIN2_LIMIT_HI_reserved0_SHIFT 8
-
-/* PCIE_0_MISC :: CPU_2_PCIE_MEM_WIN2_LIMIT_HI :: LIMIT [07:00] */
-#define BCHP_PCIE_0_MISC_CPU_2_PCIE_MEM_WIN2_LIMIT_HI_LIMIT_MASK 0x000000ff
-#define BCHP_PCIE_0_MISC_CPU_2_PCIE_MEM_WIN2_LIMIT_HI_LIMIT_SHIFT 0
-#define BCHP_PCIE_0_MISC_CPU_2_PCIE_MEM_WIN2_LIMIT_HI_LIMIT_DEFAULT 0x00000000
-
-/***************************************************************************
- *CPU_2_PCIE_MEM_WIN3_BASE_HI - CPU to PCIe Memory Window 3 base high
- ***************************************************************************/
-/* PCIE_0_MISC :: CPU_2_PCIE_MEM_WIN3_BASE_HI :: reserved0 [31:08] */
-#define BCHP_PCIE_0_MISC_CPU_2_PCIE_MEM_WIN3_BASE_HI_reserved0_MASK 0xffffff00
-#define BCHP_PCIE_0_MISC_CPU_2_PCIE_MEM_WIN3_BASE_HI_reserved0_SHIFT 8
-
-/* PCIE_0_MISC :: CPU_2_PCIE_MEM_WIN3_BASE_HI :: BASE [07:00] */
-#define BCHP_PCIE_0_MISC_CPU_2_PCIE_MEM_WIN3_BASE_HI_BASE_MASK 0x000000ff
-#define BCHP_PCIE_0_MISC_CPU_2_PCIE_MEM_WIN3_BASE_HI_BASE_SHIFT 0
-#define BCHP_PCIE_0_MISC_CPU_2_PCIE_MEM_WIN3_BASE_HI_BASE_DEFAULT 0x00000000
-
-/***************************************************************************
- *CPU_2_PCIE_MEM_WIN3_LIMIT_HI - CPU to PCIe Memory Window 3 limit high
- ***************************************************************************/
-/* PCIE_0_MISC :: CPU_2_PCIE_MEM_WIN3_LIMIT_HI :: reserved0 [31:08] */
-#define BCHP_PCIE_0_MISC_CPU_2_PCIE_MEM_WIN3_LIMIT_HI_reserved0_MASK 0xffffff00
-#define BCHP_PCIE_0_MISC_CPU_2_PCIE_MEM_WIN3_LIMIT_HI_reserved0_SHIFT 8
-
-/* PCIE_0_MISC :: CPU_2_PCIE_MEM_WIN3_LIMIT_HI :: LIMIT [07:00] */
-#define BCHP_PCIE_0_MISC_CPU_2_PCIE_MEM_WIN3_LIMIT_HI_LIMIT_MASK 0x000000ff
-#define BCHP_PCIE_0_MISC_CPU_2_PCIE_MEM_WIN3_LIMIT_HI_LIMIT_SHIFT 0
-#define BCHP_PCIE_0_MISC_CPU_2_PCIE_MEM_WIN3_LIMIT_HI_LIMIT_DEFAULT 0x00000000
-
-/***************************************************************************
- *MISC_CTRL_1 - MISC Control Register 1
- ***************************************************************************/
-/* PCIE_0_MISC :: MISC_CTRL_1 :: reserved0 [31:16] */
-#define BCHP_PCIE_0_MISC_MISC_CTRL_1_reserved0_MASK 0xffff0000
-#define BCHP_PCIE_0_MISC_MISC_CTRL_1_reserved0_SHIFT 16
-
-/* PCIE_0_MISC :: MISC_CTRL_1 :: TBD_OPTION_15_5 [15:05] */
-#define BCHP_PCIE_0_MISC_MISC_CTRL_1_TBD_OPTION_15_5_MASK 0x0000ffe0
-#define BCHP_PCIE_0_MISC_MISC_CTRL_1_TBD_OPTION_15_5_SHIFT 5
-#define BCHP_PCIE_0_MISC_MISC_CTRL_1_TBD_OPTION_15_5_DEFAULT 0x00000000
-
-/* PCIE_0_MISC :: MISC_CTRL_1 :: RELAXED_ORDERING [04:04] */
-#define BCHP_PCIE_0_MISC_MISC_CTRL_1_RELAXED_ORDERING_MASK 0x00000010
-#define BCHP_PCIE_0_MISC_MISC_CTRL_1_RELAXED_ORDERING_SHIFT 4
-#define BCHP_PCIE_0_MISC_MISC_CTRL_1_RELAXED_ORDERING_DEFAULT 0x00000000
-
-/* PCIE_0_MISC :: MISC_CTRL_1 :: NO_SNOOP [03:03] */
-#define BCHP_PCIE_0_MISC_MISC_CTRL_1_NO_SNOOP_MASK 0x00000008
-#define BCHP_PCIE_0_MISC_MISC_CTRL_1_NO_SNOOP_SHIFT 3
-#define BCHP_PCIE_0_MISC_MISC_CTRL_1_NO_SNOOP_DEFAULT 0x00000000
-
-/* PCIE_0_MISC :: MISC_CTRL_1 :: TRAFFIC_CLASS [02:00] */
-#define BCHP_PCIE_0_MISC_MISC_CTRL_1_TRAFFIC_CLASS_MASK 0x00000007
-#define BCHP_PCIE_0_MISC_MISC_CTRL_1_TRAFFIC_CLASS_SHIFT 0
-#define BCHP_PCIE_0_MISC_MISC_CTRL_1_TRAFFIC_CLASS_DEFAULT 0x00000000
-
-/***************************************************************************
- *UBUS_CTRL - UBUS Control
- ***************************************************************************/
-/* PCIE_0_MISC :: UBUS_CTRL :: TBD_OPTION_31_19 [31:19] */
-#define BCHP_PCIE_0_MISC_UBUS_CTRL_TBD_OPTION_31_19_MASK 0xfff80000
-#define BCHP_PCIE_0_MISC_UBUS_CTRL_TBD_OPTION_31_19_SHIFT 19
-#define BCHP_PCIE_0_MISC_UBUS_CTRL_TBD_OPTION_31_19_DEFAULT 0x00000000
-
-/* PCIE_0_MISC :: UBUS_CTRL :: REQOUT_PRIORITY [18:18] */
-#define BCHP_PCIE_0_MISC_UBUS_CTRL_REQOUT_PRIORITY_MASK 0x00040000
-#define BCHP_PCIE_0_MISC_UBUS_CTRL_REQOUT_PRIORITY_SHIFT 18
-#define BCHP_PCIE_0_MISC_UBUS_CTRL_REQOUT_PRIORITY_DEFAULT 0x00000000
-
-/* PCIE_0_MISC :: UBUS_CTRL :: REPOUT_PRIORITY [17:17] */
-#define BCHP_PCIE_0_MISC_UBUS_CTRL_REPOUT_PRIORITY_MASK 0x00020000
-#define BCHP_PCIE_0_MISC_UBUS_CTRL_REPOUT_PRIORITY_SHIFT 17
-#define BCHP_PCIE_0_MISC_UBUS_CTRL_REPOUT_PRIORITY_DEFAULT 0x00000000
-
-/* PCIE_0_MISC :: UBUS_CTRL :: UBUS_DMA_WR_WITH_REPLY [16:15] */
-#define BCHP_PCIE_0_MISC_UBUS_CTRL_UBUS_DMA_WR_WITH_REPLY_MASK 0x00018000
-#define BCHP_PCIE_0_MISC_UBUS_CTRL_UBUS_DMA_WR_WITH_REPLY_SHIFT 15
-#define BCHP_PCIE_0_MISC_UBUS_CTRL_UBUS_DMA_WR_WITH_REPLY_DEFAULT 0x00000000
-
-/* PCIE_0_MISC :: UBUS_CTRL :: UBUS_WR_WITH_REPLY [14:14] */
-#define BCHP_PCIE_0_MISC_UBUS_CTRL_UBUS_WR_WITH_REPLY_MASK 0x00004000
-#define BCHP_PCIE_0_MISC_UBUS_CTRL_UBUS_WR_WITH_REPLY_SHIFT 14
-#define BCHP_PCIE_0_MISC_UBUS_CTRL_UBUS_WR_WITH_REPLY_DEFAULT 0x00000000
-
-/* PCIE_0_MISC :: UBUS_CTRL :: UBUS_PCIE_REPLY_ERR_DIS [13:13] */
-#define BCHP_PCIE_0_MISC_UBUS_CTRL_UBUS_PCIE_REPLY_ERR_DIS_MASK 0x00002000
-#define BCHP_PCIE_0_MISC_UBUS_CTRL_UBUS_PCIE_REPLY_ERR_DIS_SHIFT 13
-#define BCHP_PCIE_0_MISC_UBUS_CTRL_UBUS_PCIE_REPLY_ERR_DIS_DEFAULT 0x00000000
-
-/* PCIE_0_MISC :: UBUS_CTRL :: UBUS_REG_ACCESS_RO [12:12] */
-#define BCHP_PCIE_0_MISC_UBUS_CTRL_UBUS_REG_ACCESS_RO_MASK 0x00001000
-#define BCHP_PCIE_0_MISC_UBUS_CTRL_UBUS_REG_ACCESS_RO_SHIFT 12
-#define BCHP_PCIE_0_MISC_UBUS_CTRL_UBUS_REG_ACCESS_RO_DEFAULT 0x00000000
-
-/* PCIE_0_MISC :: UBUS_CTRL :: REQIN_HDR_THRESHOLD [11:06] */
-#define BCHP_PCIE_0_MISC_UBUS_CTRL_REQIN_HDR_THRESHOLD_MASK 0x00000fc0
-#define BCHP_PCIE_0_MISC_UBUS_CTRL_REQIN_HDR_THRESHOLD_SHIFT 6
-#define BCHP_PCIE_0_MISC_UBUS_CTRL_REQIN_HDR_THRESHOLD_DEFAULT 0x00000008
-
-/* PCIE_0_MISC :: UBUS_CTRL :: REQIN_WR_DATA_THRESHOLD [05:00] */
-#define BCHP_PCIE_0_MISC_UBUS_CTRL_REQIN_WR_DATA_THRESHOLD_MASK 0x0000003f
-#define BCHP_PCIE_0_MISC_UBUS_CTRL_REQIN_WR_DATA_THRESHOLD_SHIFT 0
-#define BCHP_PCIE_0_MISC_UBUS_CTRL_REQIN_WR_DATA_THRESHOLD_DEFAULT 0x00000020
-
-/***************************************************************************
- *UBUS_TIMEOUT - UBUS Timeout
- ***************************************************************************/
-/* PCIE_0_MISC :: UBUS_TIMEOUT :: TIMER_VALUE [31:00] */
-#define BCHP_PCIE_0_MISC_UBUS_TIMEOUT_TIMER_VALUE_MASK 0xffffffff
-#define BCHP_PCIE_0_MISC_UBUS_TIMEOUT_TIMER_VALUE_SHIFT 0
-#define BCHP_PCIE_0_MISC_UBUS_TIMEOUT_TIMER_VALUE_DEFAULT 0x00080000
-
-/***************************************************************************
- *UBUS_BAR1_CONFIG_REMAP - UBUS BAR1 System Bus Address Remap Register
- ***************************************************************************/
-/* PCIE_0_MISC :: UBUS_BAR1_CONFIG_REMAP :: OFFSET [31:12] */
-#define BCHP_PCIE_0_MISC_UBUS_BAR1_CONFIG_REMAP_OFFSET_MASK 0xfffff000
-#define BCHP_PCIE_0_MISC_UBUS_BAR1_CONFIG_REMAP_OFFSET_SHIFT 12
-#define BCHP_PCIE_0_MISC_UBUS_BAR1_CONFIG_REMAP_OFFSET_DEFAULT 0x00000000
-
-/* PCIE_0_MISC :: UBUS_BAR1_CONFIG_REMAP :: reserved0 [11:04] */
-#define BCHP_PCIE_0_MISC_UBUS_BAR1_CONFIG_REMAP_reserved0_MASK 0x00000ff0
-#define BCHP_PCIE_0_MISC_UBUS_BAR1_CONFIG_REMAP_reserved0_SHIFT 4
-
-/* PCIE_0_MISC :: UBUS_BAR1_CONFIG_REMAP :: UNUSED_3_2 [03:02] */
-#define BCHP_PCIE_0_MISC_UBUS_BAR1_CONFIG_REMAP_UNUSED_3_2_MASK 0x0000000c
-#define BCHP_PCIE_0_MISC_UBUS_BAR1_CONFIG_REMAP_UNUSED_3_2_SHIFT 2
-#define BCHP_PCIE_0_MISC_UBUS_BAR1_CONFIG_REMAP_UNUSED_3_2_DEFAULT 0x00000000
-
-/* PCIE_0_MISC :: UBUS_BAR1_CONFIG_REMAP :: WR_COMBINE [01:01] */
-#define BCHP_PCIE_0_MISC_UBUS_BAR1_CONFIG_REMAP_WR_COMBINE_MASK 0x00000002
-#define BCHP_PCIE_0_MISC_UBUS_BAR1_CONFIG_REMAP_WR_COMBINE_SHIFT 1
-#define BCHP_PCIE_0_MISC_UBUS_BAR1_CONFIG_REMAP_WR_COMBINE_DEFAULT 0x00000000
-
-/* PCIE_0_MISC :: UBUS_BAR1_CONFIG_REMAP :: ACCESS_EN [00:00] */
-#define BCHP_PCIE_0_MISC_UBUS_BAR1_CONFIG_REMAP_ACCESS_EN_MASK 0x00000001
-#define BCHP_PCIE_0_MISC_UBUS_BAR1_CONFIG_REMAP_ACCESS_EN_SHIFT 0
-#define BCHP_PCIE_0_MISC_UBUS_BAR1_CONFIG_REMAP_ACCESS_EN_DEFAULT 0x00000000
-
-/***************************************************************************
- *UBUS_BAR1_CONFIG_REMAP_HI - UBUS BAR2 System Bus Address Remap Register High
- ***************************************************************************/
-/* PCIE_0_MISC :: UBUS_BAR1_CONFIG_REMAP_HI :: reserved0 [31:08] */
-#define BCHP_PCIE_0_MISC_UBUS_BAR1_CONFIG_REMAP_HI_reserved0_MASK 0xffffff00
-#define BCHP_PCIE_0_MISC_UBUS_BAR1_CONFIG_REMAP_HI_reserved0_SHIFT 8
-
-/* PCIE_0_MISC :: UBUS_BAR1_CONFIG_REMAP_HI :: OFFSET [07:00] */
-#define BCHP_PCIE_0_MISC_UBUS_BAR1_CONFIG_REMAP_HI_OFFSET_MASK 0x000000ff
-#define BCHP_PCIE_0_MISC_UBUS_BAR1_CONFIG_REMAP_HI_OFFSET_SHIFT 0
-#define BCHP_PCIE_0_MISC_UBUS_BAR1_CONFIG_REMAP_HI_OFFSET_DEFAULT 0x00000000
-
-/***************************************************************************
- *UBUS_BAR2_CONFIG_REMAP - UBUS BAR2 System Bus Address Remap Register
- ***************************************************************************/
-/* PCIE_0_MISC :: UBUS_BAR2_CONFIG_REMAP :: OFFSET [31:12] */
-#define BCHP_PCIE_0_MISC_UBUS_BAR2_CONFIG_REMAP_OFFSET_MASK 0xfffff000
-#define BCHP_PCIE_0_MISC_UBUS_BAR2_CONFIG_REMAP_OFFSET_SHIFT 12
-#define BCHP_PCIE_0_MISC_UBUS_BAR2_CONFIG_REMAP_OFFSET_DEFAULT 0x00000000
-
-/* PCIE_0_MISC :: UBUS_BAR2_CONFIG_REMAP :: reserved0 [11:04] */
-#define BCHP_PCIE_0_MISC_UBUS_BAR2_CONFIG_REMAP_reserved0_MASK 0x00000ff0
-#define BCHP_PCIE_0_MISC_UBUS_BAR2_CONFIG_REMAP_reserved0_SHIFT 4
-
-/* PCIE_0_MISC :: UBUS_BAR2_CONFIG_REMAP :: UNUSED_3_2 [03:02] */
-#define BCHP_PCIE_0_MISC_UBUS_BAR2_CONFIG_REMAP_UNUSED_3_2_MASK 0x0000000c
-#define BCHP_PCIE_0_MISC_UBUS_BAR2_CONFIG_REMAP_UNUSED_3_2_SHIFT 2
-#define BCHP_PCIE_0_MISC_UBUS_BAR2_CONFIG_REMAP_UNUSED_3_2_DEFAULT 0x00000000
-
-/* PCIE_0_MISC :: UBUS_BAR2_CONFIG_REMAP :: WR_COMBINE [01:01] */
-#define BCHP_PCIE_0_MISC_UBUS_BAR2_CONFIG_REMAP_WR_COMBINE_MASK 0x00000002
-#define BCHP_PCIE_0_MISC_UBUS_BAR2_CONFIG_REMAP_WR_COMBINE_SHIFT 1
-#define BCHP_PCIE_0_MISC_UBUS_BAR2_CONFIG_REMAP_WR_COMBINE_DEFAULT 0x00000000
-
-/* PCIE_0_MISC :: UBUS_BAR2_CONFIG_REMAP :: ACCESS_EN [00:00] */
-#define BCHP_PCIE_0_MISC_UBUS_BAR2_CONFIG_REMAP_ACCESS_EN_MASK 0x00000001
-#define BCHP_PCIE_0_MISC_UBUS_BAR2_CONFIG_REMAP_ACCESS_EN_SHIFT 0
-#define BCHP_PCIE_0_MISC_UBUS_BAR2_CONFIG_REMAP_ACCESS_EN_DEFAULT 0x00000000
-
-/***************************************************************************
- *UBUS_BAR2_CONFIG_REMAP_HI - UBUS BAR2 System Bus Address Remap Register High
- ***************************************************************************/
-/* PCIE_0_MISC :: UBUS_BAR2_CONFIG_REMAP_HI :: reserved0 [31:08] */
-#define BCHP_PCIE_0_MISC_UBUS_BAR2_CONFIG_REMAP_HI_reserved0_MASK 0xffffff00
-#define BCHP_PCIE_0_MISC_UBUS_BAR2_CONFIG_REMAP_HI_reserved0_SHIFT 8
-
-/* PCIE_0_MISC :: UBUS_BAR2_CONFIG_REMAP_HI :: OFFSET [07:00] */
-#define BCHP_PCIE_0_MISC_UBUS_BAR2_CONFIG_REMAP_HI_OFFSET_MASK 0x000000ff
-#define BCHP_PCIE_0_MISC_UBUS_BAR2_CONFIG_REMAP_HI_OFFSET_SHIFT 0
-#define BCHP_PCIE_0_MISC_UBUS_BAR2_CONFIG_REMAP_HI_OFFSET_DEFAULT 0x00000000
-
-/***************************************************************************
- *UBUS_BAR3_CONFIG_REMAP - UBUS BAR3 System Bus Address Remap Register
- ***************************************************************************/
-/* PCIE_0_MISC :: UBUS_BAR3_CONFIG_REMAP :: OFFSET [31:12] */
-#define BCHP_PCIE_0_MISC_UBUS_BAR3_CONFIG_REMAP_OFFSET_MASK 0xfffff000
-#define BCHP_PCIE_0_MISC_UBUS_BAR3_CONFIG_REMAP_OFFSET_SHIFT 12
-#define BCHP_PCIE_0_MISC_UBUS_BAR3_CONFIG_REMAP_OFFSET_DEFAULT 0x00000000
-
-/* PCIE_0_MISC :: UBUS_BAR3_CONFIG_REMAP :: reserved0 [11:04] */
-#define BCHP_PCIE_0_MISC_UBUS_BAR3_CONFIG_REMAP_reserved0_MASK 0x00000ff0
-#define BCHP_PCIE_0_MISC_UBUS_BAR3_CONFIG_REMAP_reserved0_SHIFT 4
-
-/* PCIE_0_MISC :: UBUS_BAR3_CONFIG_REMAP :: UNUSED_3_2 [03:02] */
-#define BCHP_PCIE_0_MISC_UBUS_BAR3_CONFIG_REMAP_UNUSED_3_2_MASK 0x0000000c
-#define BCHP_PCIE_0_MISC_UBUS_BAR3_CONFIG_REMAP_UNUSED_3_2_SHIFT 2
-#define BCHP_PCIE_0_MISC_UBUS_BAR3_CONFIG_REMAP_UNUSED_3_2_DEFAULT 0x00000000
-
-/* PCIE_0_MISC :: UBUS_BAR3_CONFIG_REMAP :: WR_COMBINE [01:01] */
-#define BCHP_PCIE_0_MISC_UBUS_BAR3_CONFIG_REMAP_WR_COMBINE_MASK 0x00000002
-#define BCHP_PCIE_0_MISC_UBUS_BAR3_CONFIG_REMAP_WR_COMBINE_SHIFT 1
-#define BCHP_PCIE_0_MISC_UBUS_BAR3_CONFIG_REMAP_WR_COMBINE_DEFAULT 0x00000000
-
-/* PCIE_0_MISC :: UBUS_BAR3_CONFIG_REMAP :: ACCESS_EN [00:00] */
-#define BCHP_PCIE_0_MISC_UBUS_BAR3_CONFIG_REMAP_ACCESS_EN_MASK 0x00000001
-#define BCHP_PCIE_0_MISC_UBUS_BAR3_CONFIG_REMAP_ACCESS_EN_SHIFT 0
-#define BCHP_PCIE_0_MISC_UBUS_BAR3_CONFIG_REMAP_ACCESS_EN_DEFAULT 0x00000000
-
-/***************************************************************************
- *UBUS_BAR3_CONFIG_REMAP_HI - UBUS BAR3 System Bus Address Remap Register High
- ***************************************************************************/
-/* PCIE_0_MISC :: UBUS_BAR3_CONFIG_REMAP_HI :: reserved0 [31:08] */
-#define BCHP_PCIE_0_MISC_UBUS_BAR3_CONFIG_REMAP_HI_reserved0_MASK 0xffffff00
-#define BCHP_PCIE_0_MISC_UBUS_BAR3_CONFIG_REMAP_HI_reserved0_SHIFT 8
-
-/* PCIE_0_MISC :: UBUS_BAR3_CONFIG_REMAP_HI :: OFFSET [07:00] */
-#define BCHP_PCIE_0_MISC_UBUS_BAR3_CONFIG_REMAP_HI_OFFSET_MASK 0x000000ff
-#define BCHP_PCIE_0_MISC_UBUS_BAR3_CONFIG_REMAP_HI_OFFSET_SHIFT 0
-#define BCHP_PCIE_0_MISC_UBUS_BAR3_CONFIG_REMAP_HI_OFFSET_DEFAULT 0x00000000
-
-/***************************************************************************
- *UBUS_STATUS - UBUS Status
- ***************************************************************************/
-/* PCIE_0_MISC :: UBUS_STATUS :: SLAVE_REPOUT_HSPACE [31:24] */
-#define BCHP_PCIE_0_MISC_UBUS_STATUS_SLAVE_REPOUT_HSPACE_MASK 0xff000000
-#define BCHP_PCIE_0_MISC_UBUS_STATUS_SLAVE_REPOUT_HSPACE_SHIFT 24
-#define BCHP_PCIE_0_MISC_UBUS_STATUS_SLAVE_REPOUT_HSPACE_DEFAULT 0x00000010
-
-/* PCIE_0_MISC :: UBUS_STATUS :: SLAVE_REPOUT_DSPACE [23:16] */
-#define BCHP_PCIE_0_MISC_UBUS_STATUS_SLAVE_REPOUT_DSPACE_MASK 0x00ff0000
-#define BCHP_PCIE_0_MISC_UBUS_STATUS_SLAVE_REPOUT_DSPACE_SHIFT 16
-#define BCHP_PCIE_0_MISC_UBUS_STATUS_SLAVE_REPOUT_DSPACE_DEFAULT 0x00000020
-
-/* PCIE_0_MISC :: UBUS_STATUS :: MASTER_REQOUT_HSPACE [15:08] */
-#define BCHP_PCIE_0_MISC_UBUS_STATUS_MASTER_REQOUT_HSPACE_MASK 0x0000ff00
-#define BCHP_PCIE_0_MISC_UBUS_STATUS_MASTER_REQOUT_HSPACE_SHIFT 8
-#define BCHP_PCIE_0_MISC_UBUS_STATUS_MASTER_REQOUT_HSPACE_DEFAULT 0x00000010
-
-/* PCIE_0_MISC :: UBUS_STATUS :: MASTER_REQOUT_DSPACE [07:00] */
-#define BCHP_PCIE_0_MISC_UBUS_STATUS_MASTER_REQOUT_DSPACE_MASK 0x000000ff
-#define BCHP_PCIE_0_MISC_UBUS_STATUS_MASTER_REQOUT_DSPACE_SHIFT 0
-#define BCHP_PCIE_0_MISC_UBUS_STATUS_MASTER_REQOUT_DSPACE_DEFAULT 0x00000020
-
-#endif /* #ifndef BCHP_PCIE_0_MISC_H__ */
-
-/* End of File */
diff --git a/include/linux/brcmstb/7145a0/bchp_pcie_0_misc_perst.h b/include/linux/brcmstb/7145a0/bchp_pcie_0_misc_perst.h
deleted file mode 100644
index 14610d6..0000000
--- a/include/linux/brcmstb/7145a0/bchp_pcie_0_misc_perst.h
+++ /dev/null
@@ -1,85 +0,0 @@
-/***************************************************************************
- * Copyright (c) 1999-2013, Broadcom Corporation
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
- *
- * Module Description:
- * DO NOT EDIT THIS FILE DIRECTLY
- *
- * This module was generated magically with RDB from a source description
- * file. You must edit the source file for changes to be made to this file.
- *
- *
- * Date: Generated on Sat Apr 6 03:07:47 2013
- * MD5 Checksum d41d8cd98f00b204e9800998ecf8427e
- *
- * Compiled with: RDB Utility combo_header.pl
- * RDB Parser 3.0
- * unknown unknown
- * Perl Interpreter 5.008008
- * Operating System linux
- *
- * Revision History:
- *
- * $brcm_Log: $
- *
- ***************************************************************************/
-
-#ifndef BCHP_PCIE_0_MISC_PERST_H__
-#define BCHP_PCIE_0_MISC_PERST_H__
-
-/***************************************************************************
- *PCIE_0_MISC_PERST - PCI-E Miscellaneous Registers (Fundamental reset)
- ***************************************************************************/
-#define BCHP_PCIE_0_MISC_PERST_ECO_CTRL_PERST 0x07804100 /* ECO PCIE Reset Control Register */
-#define BCHP_PCIE_0_MISC_PERST_CCE_STATUS 0x07804104 /* Config Copy Engine Status */
-
-/***************************************************************************
- *ECO_CTRL_PERST - ECO PCIE Reset Control Register
- ***************************************************************************/
-/* PCIE_0_MISC_PERST :: ECO_CTRL_PERST :: reserved0 [31:16] */
-#define BCHP_PCIE_0_MISC_PERST_ECO_CTRL_PERST_reserved0_MASK 0xffff0000
-#define BCHP_PCIE_0_MISC_PERST_ECO_CTRL_PERST_reserved0_SHIFT 16
-
-/* PCIE_0_MISC_PERST :: ECO_CTRL_PERST :: ECO_PERST_N [15:00] */
-#define BCHP_PCIE_0_MISC_PERST_ECO_CTRL_PERST_ECO_PERST_N_MASK 0x0000ffff
-#define BCHP_PCIE_0_MISC_PERST_ECO_CTRL_PERST_ECO_PERST_N_SHIFT 0
-#define BCHP_PCIE_0_MISC_PERST_ECO_CTRL_PERST_ECO_PERST_N_DEFAULT 0x00000000
-
-/***************************************************************************
- *CCE_STATUS - Config Copy Engine Status
- ***************************************************************************/
-/* PCIE_0_MISC_PERST :: CCE_STATUS :: CCE_DONE [31:31] */
-#define BCHP_PCIE_0_MISC_PERST_CCE_STATUS_CCE_DONE_MASK 0x80000000
-#define BCHP_PCIE_0_MISC_PERST_CCE_STATUS_CCE_DONE_SHIFT 31
-
-/* PCIE_0_MISC_PERST :: CCE_STATUS :: reserved0 [30:03] */
-#define BCHP_PCIE_0_MISC_PERST_CCE_STATUS_reserved0_MASK 0x7ffffff8
-#define BCHP_PCIE_0_MISC_PERST_CCE_STATUS_reserved0_SHIFT 3
-
-/* PCIE_0_MISC_PERST :: CCE_STATUS :: CCE_BAD_GISB_ACCESS [02:02] */
-#define BCHP_PCIE_0_MISC_PERST_CCE_STATUS_CCE_BAD_GISB_ACCESS_MASK 0x00000004
-#define BCHP_PCIE_0_MISC_PERST_CCE_STATUS_CCE_BAD_GISB_ACCESS_SHIFT 2
-
-/* PCIE_0_MISC_PERST :: CCE_STATUS :: CCE_BAD_I2C_ACCESS [01:01] */
-#define BCHP_PCIE_0_MISC_PERST_CCE_STATUS_CCE_BAD_I2C_ACCESS_MASK 0x00000002
-#define BCHP_PCIE_0_MISC_PERST_CCE_STATUS_CCE_BAD_I2C_ACCESS_SHIFT 1
-
-/* PCIE_0_MISC_PERST :: CCE_STATUS :: CCE_BAD_SECTION_ID [00:00] */
-#define BCHP_PCIE_0_MISC_PERST_CCE_STATUS_CCE_BAD_SECTION_ID_MASK 0x00000001
-#define BCHP_PCIE_0_MISC_PERST_CCE_STATUS_CCE_BAD_SECTION_ID_SHIFT 0
-
-#endif /* #ifndef BCHP_PCIE_0_MISC_PERST_H__ */
-
-/* End of File */
diff --git a/include/linux/brcmstb/7145a0/bchp_pcie_0_rc_cfg_pcie.h b/include/linux/brcmstb/7145a0/bchp_pcie_0_rc_cfg_pcie.h
deleted file mode 100644
index 23f40c6..0000000
--- a/include/linux/brcmstb/7145a0/bchp_pcie_0_rc_cfg_pcie.h
+++ /dev/null
@@ -1,644 +0,0 @@
-/***************************************************************************
- * Copyright (c) 1999-2013, Broadcom Corporation
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
- *
- * Module Description:
- * DO NOT EDIT THIS FILE DIRECTLY
- *
- * This module was generated magically with RDB from a source description
- * file. You must edit the source file for changes to be made to this file.
- *
- *
- * Date: Generated on Sat Apr 6 03:07:47 2013
- * MD5 Checksum d41d8cd98f00b204e9800998ecf8427e
- *
- * Compiled with: RDB Utility combo_header.pl
- * RDB Parser 3.0
- * unknown unknown
- * Perl Interpreter 5.008008
- * Operating System linux
- *
- * Revision History:
- *
- * $brcm_Log: $
- *
- ***************************************************************************/
-
-#ifndef BCHP_PCIE_0_RC_CFG_PCIE_H__
-#define BCHP_PCIE_0_RC_CFG_PCIE_H__
-
-/***************************************************************************
- *PCIE_0_RC_CFG_PCIE
- ***************************************************************************/
-#define BCHP_PCIE_0_RC_CFG_PCIE_PCIE_CAPABILITY 0x078000ac /* pcie_capability */
-#define BCHP_PCIE_0_RC_CFG_PCIE_DEVICE_CAPABILITY 0x078000b0 /* device_capability */
-#define BCHP_PCIE_0_RC_CFG_PCIE_DEVICE_STATUS_CONTROL 0x078000b4 /* device_status_control */
-#define BCHP_PCIE_0_RC_CFG_PCIE_LINK_CAPABILITY 0x078000b8 /* link_capability */
-#define BCHP_PCIE_0_RC_CFG_PCIE_LINK_STATUS_CONTROL 0x078000bc /* link_status_control */
-#define BCHP_PCIE_0_RC_CFG_PCIE_SLOT_CAPABILITY 0x078000c0 /* slot_capability */
-#define BCHP_PCIE_0_RC_CFG_PCIE_SLOT_CONTROL_STATUS 0x078000c4 /* slot_control_status */
-#define BCHP_PCIE_0_RC_CFG_PCIE_ROOT_CAP_CONTROL 0x078000c8 /* root_cap_control */
-#define BCHP_PCIE_0_RC_CFG_PCIE_ROOT_STATUS 0x078000cc /* root_status */
-#define BCHP_PCIE_0_RC_CFG_PCIE_DEVICE_CAPABILITY_2 0x078000d0 /* device_capability_2 */
-#define BCHP_PCIE_0_RC_CFG_PCIE_DEVICE_STATUS_CONTROL_2 0x078000d4 /* device_status_control_2 */
-#define BCHP_PCIE_0_RC_CFG_PCIE_LINK_CAPABILITY_2 0x078000d8 /* link_capability_2 */
-#define BCHP_PCIE_0_RC_CFG_PCIE_LINK_STATUS_CONTROL_2 0x078000dc /* link_status_control_2 */
-#define BCHP_PCIE_0_RC_CFG_PCIE_SLOT_CAPABILITY_2 0x078000e0 /* slot_capability_2 */
-#define BCHP_PCIE_0_RC_CFG_PCIE_SLOT_STATUS_CONTROL_2 0x078000e4 /* slot_status_control_2 */
-
-/***************************************************************************
- *PCIE_CAPABILITY - pcie_capability
- ***************************************************************************/
-/* PCIE_0_RC_CFG_PCIE :: PCIE_CAPABILITY :: RESERVED0 [31:30] */
-#define BCHP_PCIE_0_RC_CFG_PCIE_PCIE_CAPABILITY_RESERVED0_MASK 0xc0000000
-#define BCHP_PCIE_0_RC_CFG_PCIE_PCIE_CAPABILITY_RESERVED0_SHIFT 30
-
-/* PCIE_0_RC_CFG_PCIE :: PCIE_CAPABILITY :: MSG_NUM [29:25] */
-#define BCHP_PCIE_0_RC_CFG_PCIE_PCIE_CAPABILITY_MSG_NUM_MASK 0x3e000000
-#define BCHP_PCIE_0_RC_CFG_PCIE_PCIE_CAPABILITY_MSG_NUM_SHIFT 25
-#define BCHP_PCIE_0_RC_CFG_PCIE_PCIE_CAPABILITY_MSG_NUM_DEFAULT 0x00000000
-
-/* PCIE_0_RC_CFG_PCIE :: PCIE_CAPABILITY :: SLOT_IMPLEMENTED [24:24] */
-#define BCHP_PCIE_0_RC_CFG_PCIE_PCIE_CAPABILITY_SLOT_IMPLEMENTED_MASK 0x01000000
-#define BCHP_PCIE_0_RC_CFG_PCIE_PCIE_CAPABILITY_SLOT_IMPLEMENTED_SHIFT 24
-#define BCHP_PCIE_0_RC_CFG_PCIE_PCIE_CAPABILITY_SLOT_IMPLEMENTED_DEFAULT 0x00000000
-
-/* PCIE_0_RC_CFG_PCIE :: PCIE_CAPABILITY :: TYPE [23:20] */
-#define BCHP_PCIE_0_RC_CFG_PCIE_PCIE_CAPABILITY_TYPE_MASK 0x00f00000
-#define BCHP_PCIE_0_RC_CFG_PCIE_PCIE_CAPABILITY_TYPE_SHIFT 20
-#define BCHP_PCIE_0_RC_CFG_PCIE_PCIE_CAPABILITY_TYPE_DEFAULT 0x00000004
-
-/* PCIE_0_RC_CFG_PCIE :: PCIE_CAPABILITY :: VER [19:16] */
-#define BCHP_PCIE_0_RC_CFG_PCIE_PCIE_CAPABILITY_VER_MASK 0x000f0000
-#define BCHP_PCIE_0_RC_CFG_PCIE_PCIE_CAPABILITY_VER_SHIFT 16
-#define BCHP_PCIE_0_RC_CFG_PCIE_PCIE_CAPABILITY_VER_DEFAULT 0x00000002
-
-/* PCIE_0_RC_CFG_PCIE :: PCIE_CAPABILITY :: PCIE_NEXT_CAP_PTR [15:08] */
-#define BCHP_PCIE_0_RC_CFG_PCIE_PCIE_CAPABILITY_PCIE_NEXT_CAP_PTR_MASK 0x0000ff00
-#define BCHP_PCIE_0_RC_CFG_PCIE_PCIE_CAPABILITY_PCIE_NEXT_CAP_PTR_SHIFT 8
-#define BCHP_PCIE_0_RC_CFG_PCIE_PCIE_CAPABILITY_PCIE_NEXT_CAP_PTR_DEFAULT 0x00000000
-
-/* PCIE_0_RC_CFG_PCIE :: PCIE_CAPABILITY :: PCIE_CAP_ID [07:00] */
-#define BCHP_PCIE_0_RC_CFG_PCIE_PCIE_CAPABILITY_PCIE_CAP_ID_MASK 0x000000ff
-#define BCHP_PCIE_0_RC_CFG_PCIE_PCIE_CAPABILITY_PCIE_CAP_ID_SHIFT 0
-#define BCHP_PCIE_0_RC_CFG_PCIE_PCIE_CAPABILITY_PCIE_CAP_ID_DEFAULT 0x00000010
-
-/***************************************************************************
- *DEVICE_CAPABILITY - device_capability
- ***************************************************************************/
-/* PCIE_0_RC_CFG_PCIE :: DEVICE_CAPABILITY :: RESERVED3 [31:28] */
-#define BCHP_PCIE_0_RC_CFG_PCIE_DEVICE_CAPABILITY_RESERVED3_MASK 0xf0000000
-#define BCHP_PCIE_0_RC_CFG_PCIE_DEVICE_CAPABILITY_RESERVED3_SHIFT 28
-
-/* PCIE_0_RC_CFG_PCIE :: DEVICE_CAPABILITY :: CAPTURED_SLOT_PWR_SCALE [27:26] */
-#define BCHP_PCIE_0_RC_CFG_PCIE_DEVICE_CAPABILITY_CAPTURED_SLOT_PWR_SCALE_MASK 0x0c000000
-#define BCHP_PCIE_0_RC_CFG_PCIE_DEVICE_CAPABILITY_CAPTURED_SLOT_PWR_SCALE_SHIFT 26
-#define BCHP_PCIE_0_RC_CFG_PCIE_DEVICE_CAPABILITY_CAPTURED_SLOT_PWR_SCALE_DEFAULT 0x00000000
-
-/* PCIE_0_RC_CFG_PCIE :: DEVICE_CAPABILITY :: CAPTURED_SLOT_PWR_VAL [25:18] */
-#define BCHP_PCIE_0_RC_CFG_PCIE_DEVICE_CAPABILITY_CAPTURED_SLOT_PWR_VAL_MASK 0x03fc0000
-#define BCHP_PCIE_0_RC_CFG_PCIE_DEVICE_CAPABILITY_CAPTURED_SLOT_PWR_VAL_SHIFT 18
-#define BCHP_PCIE_0_RC_CFG_PCIE_DEVICE_CAPABILITY_CAPTURED_SLOT_PWR_VAL_DEFAULT 0x00000000
-
-/* PCIE_0_RC_CFG_PCIE :: DEVICE_CAPABILITY :: RESERVED2 [17:16] */
-#define BCHP_PCIE_0_RC_CFG_PCIE_DEVICE_CAPABILITY_RESERVED2_MASK 0x00030000
-#define BCHP_PCIE_0_RC_CFG_PCIE_DEVICE_CAPABILITY_RESERVED2_SHIFT 16
-
-/* PCIE_0_RC_CFG_PCIE :: DEVICE_CAPABILITY :: ROLE_BASED_ERR_RPT [15:15] */
-#define BCHP_PCIE_0_RC_CFG_PCIE_DEVICE_CAPABILITY_ROLE_BASED_ERR_RPT_MASK 0x00008000
-#define BCHP_PCIE_0_RC_CFG_PCIE_DEVICE_CAPABILITY_ROLE_BASED_ERR_RPT_SHIFT 15
-#define BCHP_PCIE_0_RC_CFG_PCIE_DEVICE_CAPABILITY_ROLE_BASED_ERR_RPT_DEFAULT 0x00000001
-
-/* PCIE_0_RC_CFG_PCIE :: DEVICE_CAPABILITY :: RESERVED1 [14:12] */
-#define BCHP_PCIE_0_RC_CFG_PCIE_DEVICE_CAPABILITY_RESERVED1_MASK 0x00007000
-#define BCHP_PCIE_0_RC_CFG_PCIE_DEVICE_CAPABILITY_RESERVED1_SHIFT 12
-
-/* PCIE_0_RC_CFG_PCIE :: DEVICE_CAPABILITY :: L1_ACCEPTABLE_LATENCY [11:09] */
-#define BCHP_PCIE_0_RC_CFG_PCIE_DEVICE_CAPABILITY_L1_ACCEPTABLE_LATENCY_MASK 0x00000e00
-#define BCHP_PCIE_0_RC_CFG_PCIE_DEVICE_CAPABILITY_L1_ACCEPTABLE_LATENCY_SHIFT 9
-#define BCHP_PCIE_0_RC_CFG_PCIE_DEVICE_CAPABILITY_L1_ACCEPTABLE_LATENCY_DEFAULT 0x00000000
-
-/* PCIE_0_RC_CFG_PCIE :: DEVICE_CAPABILITY :: L0S_ACCEPTABLE_LATENCY [08:06] */
-#define BCHP_PCIE_0_RC_CFG_PCIE_DEVICE_CAPABILITY_L0S_ACCEPTABLE_LATENCY_MASK 0x000001c0
-#define BCHP_PCIE_0_RC_CFG_PCIE_DEVICE_CAPABILITY_L0S_ACCEPTABLE_LATENCY_SHIFT 6
-#define BCHP_PCIE_0_RC_CFG_PCIE_DEVICE_CAPABILITY_L0S_ACCEPTABLE_LATENCY_DEFAULT 0x00000000
-
-/* PCIE_0_RC_CFG_PCIE :: DEVICE_CAPABILITY :: EXTENDED_TAG_SUPPORT [05:05] */
-#define BCHP_PCIE_0_RC_CFG_PCIE_DEVICE_CAPABILITY_EXTENDED_TAG_SUPPORT_MASK 0x00000020
-#define BCHP_PCIE_0_RC_CFG_PCIE_DEVICE_CAPABILITY_EXTENDED_TAG_SUPPORT_SHIFT 5
-#define BCHP_PCIE_0_RC_CFG_PCIE_DEVICE_CAPABILITY_EXTENDED_TAG_SUPPORT_DEFAULT 0x00000000
-
-/* PCIE_0_RC_CFG_PCIE :: DEVICE_CAPABILITY :: RESERVED0 [04:03] */
-#define BCHP_PCIE_0_RC_CFG_PCIE_DEVICE_CAPABILITY_RESERVED0_MASK 0x00000018
-#define BCHP_PCIE_0_RC_CFG_PCIE_DEVICE_CAPABILITY_RESERVED0_SHIFT 3
-
-/* PCIE_0_RC_CFG_PCIE :: DEVICE_CAPABILITY :: MAX_PL_SIZE_SUPPORTED [02:00] */
-#define BCHP_PCIE_0_RC_CFG_PCIE_DEVICE_CAPABILITY_MAX_PL_SIZE_SUPPORTED_MASK 0x00000007
-#define BCHP_PCIE_0_RC_CFG_PCIE_DEVICE_CAPABILITY_MAX_PL_SIZE_SUPPORTED_SHIFT 0
-#define BCHP_PCIE_0_RC_CFG_PCIE_DEVICE_CAPABILITY_MAX_PL_SIZE_SUPPORTED_DEFAULT 0x00000002
-
-/***************************************************************************
- *DEVICE_STATUS_CONTROL - device_status_control
- ***************************************************************************/
-/* PCIE_0_RC_CFG_PCIE :: DEVICE_STATUS_CONTROL :: RESERVED2 [31:22] */
-#define BCHP_PCIE_0_RC_CFG_PCIE_DEVICE_STATUS_CONTROL_RESERVED2_MASK 0xffc00000
-#define BCHP_PCIE_0_RC_CFG_PCIE_DEVICE_STATUS_CONTROL_RESERVED2_SHIFT 22
-
-/* PCIE_0_RC_CFG_PCIE :: DEVICE_STATUS_CONTROL :: NP_TRANSACTION_PEND [21:21] */
-#define BCHP_PCIE_0_RC_CFG_PCIE_DEVICE_STATUS_CONTROL_NP_TRANSACTION_PEND_MASK 0x00200000
-#define BCHP_PCIE_0_RC_CFG_PCIE_DEVICE_STATUS_CONTROL_NP_TRANSACTION_PEND_SHIFT 21
-#define BCHP_PCIE_0_RC_CFG_PCIE_DEVICE_STATUS_CONTROL_NP_TRANSACTION_PEND_DEFAULT 0x00000000
-
-/* PCIE_0_RC_CFG_PCIE :: DEVICE_STATUS_CONTROL :: AUX_PWR_DET [20:20] */
-#define BCHP_PCIE_0_RC_CFG_PCIE_DEVICE_STATUS_CONTROL_AUX_PWR_DET_MASK 0x00100000
-#define BCHP_PCIE_0_RC_CFG_PCIE_DEVICE_STATUS_CONTROL_AUX_PWR_DET_SHIFT 20
-#define BCHP_PCIE_0_RC_CFG_PCIE_DEVICE_STATUS_CONTROL_AUX_PWR_DET_DEFAULT 0x00000001
-
-/* PCIE_0_RC_CFG_PCIE :: DEVICE_STATUS_CONTROL :: UNSUP_REQ_DET [19:19] */
-#define BCHP_PCIE_0_RC_CFG_PCIE_DEVICE_STATUS_CONTROL_UNSUP_REQ_DET_MASK 0x00080000
-#define BCHP_PCIE_0_RC_CFG_PCIE_DEVICE_STATUS_CONTROL_UNSUP_REQ_DET_SHIFT 19
-#define BCHP_PCIE_0_RC_CFG_PCIE_DEVICE_STATUS_CONTROL_UNSUP_REQ_DET_DEFAULT 0x00000000
-
-/* PCIE_0_RC_CFG_PCIE :: DEVICE_STATUS_CONTROL :: FATAL_ERR_DET [18:18] */
-#define BCHP_PCIE_0_RC_CFG_PCIE_DEVICE_STATUS_CONTROL_FATAL_ERR_DET_MASK 0x00040000
-#define BCHP_PCIE_0_RC_CFG_PCIE_DEVICE_STATUS_CONTROL_FATAL_ERR_DET_SHIFT 18
-#define BCHP_PCIE_0_RC_CFG_PCIE_DEVICE_STATUS_CONTROL_FATAL_ERR_DET_DEFAULT 0x00000000
-
-/* PCIE_0_RC_CFG_PCIE :: DEVICE_STATUS_CONTROL :: NON_FATAL_ERR_DET [17:17] */
-#define BCHP_PCIE_0_RC_CFG_PCIE_DEVICE_STATUS_CONTROL_NON_FATAL_ERR_DET_MASK 0x00020000
-#define BCHP_PCIE_0_RC_CFG_PCIE_DEVICE_STATUS_CONTROL_NON_FATAL_ERR_DET_SHIFT 17
-#define BCHP_PCIE_0_RC_CFG_PCIE_DEVICE_STATUS_CONTROL_NON_FATAL_ERR_DET_DEFAULT 0x00000000
-
-/* PCIE_0_RC_CFG_PCIE :: DEVICE_STATUS_CONTROL :: CORR_ERR_DET [16:16] */
-#define BCHP_PCIE_0_RC_CFG_PCIE_DEVICE_STATUS_CONTROL_CORR_ERR_DET_MASK 0x00010000
-#define BCHP_PCIE_0_RC_CFG_PCIE_DEVICE_STATUS_CONTROL_CORR_ERR_DET_SHIFT 16
-#define BCHP_PCIE_0_RC_CFG_PCIE_DEVICE_STATUS_CONTROL_CORR_ERR_DET_DEFAULT 0x00000000
-
-/* PCIE_0_RC_CFG_PCIE :: DEVICE_STATUS_CONTROL :: RESERVED1 [15:15] */
-#define BCHP_PCIE_0_RC_CFG_PCIE_DEVICE_STATUS_CONTROL_RESERVED1_MASK 0x00008000
-#define BCHP_PCIE_0_RC_CFG_PCIE_DEVICE_STATUS_CONTROL_RESERVED1_SHIFT 15
-
-/* PCIE_0_RC_CFG_PCIE :: DEVICE_STATUS_CONTROL :: MAX_READ_REQ_SIZ [14:12] */
-#define BCHP_PCIE_0_RC_CFG_PCIE_DEVICE_STATUS_CONTROL_MAX_READ_REQ_SIZ_MASK 0x00007000
-#define BCHP_PCIE_0_RC_CFG_PCIE_DEVICE_STATUS_CONTROL_MAX_READ_REQ_SIZ_SHIFT 12
-#define BCHP_PCIE_0_RC_CFG_PCIE_DEVICE_STATUS_CONTROL_MAX_READ_REQ_SIZ_DEFAULT 0x00000002
-
-/* PCIE_0_RC_CFG_PCIE :: DEVICE_STATUS_CONTROL :: NO_SNOOP_ENABLE [11:11] */
-#define BCHP_PCIE_0_RC_CFG_PCIE_DEVICE_STATUS_CONTROL_NO_SNOOP_ENABLE_MASK 0x00000800
-#define BCHP_PCIE_0_RC_CFG_PCIE_DEVICE_STATUS_CONTROL_NO_SNOOP_ENABLE_SHIFT 11
-#define BCHP_PCIE_0_RC_CFG_PCIE_DEVICE_STATUS_CONTROL_NO_SNOOP_ENABLE_DEFAULT 0x00000001
-
-/* PCIE_0_RC_CFG_PCIE :: DEVICE_STATUS_CONTROL :: AUX_PWR_PM_ENA [10:10] */
-#define BCHP_PCIE_0_RC_CFG_PCIE_DEVICE_STATUS_CONTROL_AUX_PWR_PM_ENA_MASK 0x00000400
-#define BCHP_PCIE_0_RC_CFG_PCIE_DEVICE_STATUS_CONTROL_AUX_PWR_PM_ENA_SHIFT 10
-#define BCHP_PCIE_0_RC_CFG_PCIE_DEVICE_STATUS_CONTROL_AUX_PWR_PM_ENA_DEFAULT 0x00000001
-
-/* PCIE_0_RC_CFG_PCIE :: DEVICE_STATUS_CONTROL :: RESERVED0 [09:09] */
-#define BCHP_PCIE_0_RC_CFG_PCIE_DEVICE_STATUS_CONTROL_RESERVED0_MASK 0x00000200
-#define BCHP_PCIE_0_RC_CFG_PCIE_DEVICE_STATUS_CONTROL_RESERVED0_SHIFT 9
-
-/* PCIE_0_RC_CFG_PCIE :: DEVICE_STATUS_CONTROL :: EXTENDED_TAG_EN [08:08] */
-#define BCHP_PCIE_0_RC_CFG_PCIE_DEVICE_STATUS_CONTROL_EXTENDED_TAG_EN_MASK 0x00000100
-#define BCHP_PCIE_0_RC_CFG_PCIE_DEVICE_STATUS_CONTROL_EXTENDED_TAG_EN_SHIFT 8
-#define BCHP_PCIE_0_RC_CFG_PCIE_DEVICE_STATUS_CONTROL_EXTENDED_TAG_EN_DEFAULT 0x00000000
-
-/* PCIE_0_RC_CFG_PCIE :: DEVICE_STATUS_CONTROL :: MAX_PAYLOAD_SIZE [07:05] */
-#define BCHP_PCIE_0_RC_CFG_PCIE_DEVICE_STATUS_CONTROL_MAX_PAYLOAD_SIZE_MASK 0x000000e0
-#define BCHP_PCIE_0_RC_CFG_PCIE_DEVICE_STATUS_CONTROL_MAX_PAYLOAD_SIZE_SHIFT 5
-#define BCHP_PCIE_0_RC_CFG_PCIE_DEVICE_STATUS_CONTROL_MAX_PAYLOAD_SIZE_DEFAULT 0x00000000
-
-/* PCIE_0_RC_CFG_PCIE :: DEVICE_STATUS_CONTROL :: RELAX_ORDERING_ENABLE [04:04] */
-#define BCHP_PCIE_0_RC_CFG_PCIE_DEVICE_STATUS_CONTROL_RELAX_ORDERING_ENABLE_MASK 0x00000010
-#define BCHP_PCIE_0_RC_CFG_PCIE_DEVICE_STATUS_CONTROL_RELAX_ORDERING_ENABLE_SHIFT 4
-#define BCHP_PCIE_0_RC_CFG_PCIE_DEVICE_STATUS_CONTROL_RELAX_ORDERING_ENABLE_DEFAULT 0x00000001
-
-/* PCIE_0_RC_CFG_PCIE :: DEVICE_STATUS_CONTROL :: U_REQ_REPORT_EN [03:03] */
-#define BCHP_PCIE_0_RC_CFG_PCIE_DEVICE_STATUS_CONTROL_U_REQ_REPORT_EN_MASK 0x00000008
-#define BCHP_PCIE_0_RC_CFG_PCIE_DEVICE_STATUS_CONTROL_U_REQ_REPORT_EN_SHIFT 3
-#define BCHP_PCIE_0_RC_CFG_PCIE_DEVICE_STATUS_CONTROL_U_REQ_REPORT_EN_DEFAULT 0x00000000
-
-/* PCIE_0_RC_CFG_PCIE :: DEVICE_STATUS_CONTROL :: FATAL_ERR_REPORT_EN [02:02] */
-#define BCHP_PCIE_0_RC_CFG_PCIE_DEVICE_STATUS_CONTROL_FATAL_ERR_REPORT_EN_MASK 0x00000004
-#define BCHP_PCIE_0_RC_CFG_PCIE_DEVICE_STATUS_CONTROL_FATAL_ERR_REPORT_EN_SHIFT 2
-#define BCHP_PCIE_0_RC_CFG_PCIE_DEVICE_STATUS_CONTROL_FATAL_ERR_REPORT_EN_DEFAULT 0x00000000
-
-/* PCIE_0_RC_CFG_PCIE :: DEVICE_STATUS_CONTROL :: NFATAL_ERR_REPORT_EN [01:01] */
-#define BCHP_PCIE_0_RC_CFG_PCIE_DEVICE_STATUS_CONTROL_NFATAL_ERR_REPORT_EN_MASK 0x00000002
-#define BCHP_PCIE_0_RC_CFG_PCIE_DEVICE_STATUS_CONTROL_NFATAL_ERR_REPORT_EN_SHIFT 1
-#define BCHP_PCIE_0_RC_CFG_PCIE_DEVICE_STATUS_CONTROL_NFATAL_ERR_REPORT_EN_DEFAULT 0x00000000
-
-/* PCIE_0_RC_CFG_PCIE :: DEVICE_STATUS_CONTROL :: CORR_ERR_REPORT_EN [00:00] */
-#define BCHP_PCIE_0_RC_CFG_PCIE_DEVICE_STATUS_CONTROL_CORR_ERR_REPORT_EN_MASK 0x00000001
-#define BCHP_PCIE_0_RC_CFG_PCIE_DEVICE_STATUS_CONTROL_CORR_ERR_REPORT_EN_SHIFT 0
-#define BCHP_PCIE_0_RC_CFG_PCIE_DEVICE_STATUS_CONTROL_CORR_ERR_REPORT_EN_DEFAULT 0x00000000
-
-/***************************************************************************
- *LINK_CAPABILITY - link_capability
- ***************************************************************************/
-/* PCIE_0_RC_CFG_PCIE :: LINK_CAPABILITY :: PORT_NUMBER [31:24] */
-#define BCHP_PCIE_0_RC_CFG_PCIE_LINK_CAPABILITY_PORT_NUMBER_MASK 0xff000000
-#define BCHP_PCIE_0_RC_CFG_PCIE_LINK_CAPABILITY_PORT_NUMBER_SHIFT 24
-#define BCHP_PCIE_0_RC_CFG_PCIE_LINK_CAPABILITY_PORT_NUMBER_DEFAULT 0x00000000
-
-/* PCIE_0_RC_CFG_PCIE :: LINK_CAPABILITY :: RESERVED0 [23:23] */
-#define BCHP_PCIE_0_RC_CFG_PCIE_LINK_CAPABILITY_RESERVED0_MASK 0x00800000
-#define BCHP_PCIE_0_RC_CFG_PCIE_LINK_CAPABILITY_RESERVED0_SHIFT 23
-
-/* PCIE_0_RC_CFG_PCIE :: LINK_CAPABILITY :: ASPM_OPTIONALITY [22:22] */
-#define BCHP_PCIE_0_RC_CFG_PCIE_LINK_CAPABILITY_ASPM_OPTIONALITY_MASK 0x00400000
-#define BCHP_PCIE_0_RC_CFG_PCIE_LINK_CAPABILITY_ASPM_OPTIONALITY_SHIFT 22
-#define BCHP_PCIE_0_RC_CFG_PCIE_LINK_CAPABILITY_ASPM_OPTIONALITY_DEFAULT 0x00000001
-
-/* PCIE_0_RC_CFG_PCIE :: LINK_CAPABILITY :: LINK_BW_NOTIFY [21:21] */
-#define BCHP_PCIE_0_RC_CFG_PCIE_LINK_CAPABILITY_LINK_BW_NOTIFY_MASK 0x00200000
-#define BCHP_PCIE_0_RC_CFG_PCIE_LINK_CAPABILITY_LINK_BW_NOTIFY_SHIFT 21
-#define BCHP_PCIE_0_RC_CFG_PCIE_LINK_CAPABILITY_LINK_BW_NOTIFY_DEFAULT 0x00000000
-
-/* PCIE_0_RC_CFG_PCIE :: LINK_CAPABILITY :: DL_ACTIVE_REP [20:20] */
-#define BCHP_PCIE_0_RC_CFG_PCIE_LINK_CAPABILITY_DL_ACTIVE_REP_MASK 0x00100000
-#define BCHP_PCIE_0_RC_CFG_PCIE_LINK_CAPABILITY_DL_ACTIVE_REP_SHIFT 20
-#define BCHP_PCIE_0_RC_CFG_PCIE_LINK_CAPABILITY_DL_ACTIVE_REP_DEFAULT 0x00000000
-
-/* PCIE_0_RC_CFG_PCIE :: LINK_CAPABILITY :: SUR_DWN_ERR_REP [19:19] */
-#define BCHP_PCIE_0_RC_CFG_PCIE_LINK_CAPABILITY_SUR_DWN_ERR_REP_MASK 0x00080000
-#define BCHP_PCIE_0_RC_CFG_PCIE_LINK_CAPABILITY_SUR_DWN_ERR_REP_SHIFT 19
-#define BCHP_PCIE_0_RC_CFG_PCIE_LINK_CAPABILITY_SUR_DWN_ERR_REP_DEFAULT 0x00000000
-
-/* PCIE_0_RC_CFG_PCIE :: LINK_CAPABILITY :: CLK_PWR_MGMT [18:18] */
-#define BCHP_PCIE_0_RC_CFG_PCIE_LINK_CAPABILITY_CLK_PWR_MGMT_MASK 0x00040000
-#define BCHP_PCIE_0_RC_CFG_PCIE_LINK_CAPABILITY_CLK_PWR_MGMT_SHIFT 18
-#define BCHP_PCIE_0_RC_CFG_PCIE_LINK_CAPABILITY_CLK_PWR_MGMT_DEFAULT 0x00000001
-
-/* PCIE_0_RC_CFG_PCIE :: LINK_CAPABILITY :: L1_EXIT_LAT [17:15] */
-#define BCHP_PCIE_0_RC_CFG_PCIE_LINK_CAPABILITY_L1_EXIT_LAT_MASK 0x00038000
-#define BCHP_PCIE_0_RC_CFG_PCIE_LINK_CAPABILITY_L1_EXIT_LAT_SHIFT 15
-#define BCHP_PCIE_0_RC_CFG_PCIE_LINK_CAPABILITY_L1_EXIT_LAT_DEFAULT 0x00000002
-
-/* PCIE_0_RC_CFG_PCIE :: LINK_CAPABILITY :: L0S_EXIT_LAT [14:12] */
-#define BCHP_PCIE_0_RC_CFG_PCIE_LINK_CAPABILITY_L0S_EXIT_LAT_MASK 0x00007000
-#define BCHP_PCIE_0_RC_CFG_PCIE_LINK_CAPABILITY_L0S_EXIT_LAT_SHIFT 12
-#define BCHP_PCIE_0_RC_CFG_PCIE_LINK_CAPABILITY_L0S_EXIT_LAT_DEFAULT 0x00000005
-
-/* PCIE_0_RC_CFG_PCIE :: LINK_CAPABILITY :: ASPM_SUPT [11:10] */
-#define BCHP_PCIE_0_RC_CFG_PCIE_LINK_CAPABILITY_ASPM_SUPT_MASK 0x00000c00
-#define BCHP_PCIE_0_RC_CFG_PCIE_LINK_CAPABILITY_ASPM_SUPT_SHIFT 10
-#define BCHP_PCIE_0_RC_CFG_PCIE_LINK_CAPABILITY_ASPM_SUPT_DEFAULT 0x00000003
-
-/* PCIE_0_RC_CFG_PCIE :: LINK_CAPABILITY :: MAX_LINK_WIDTH [09:04] */
-#define BCHP_PCIE_0_RC_CFG_PCIE_LINK_CAPABILITY_MAX_LINK_WIDTH_MASK 0x000003f0
-#define BCHP_PCIE_0_RC_CFG_PCIE_LINK_CAPABILITY_MAX_LINK_WIDTH_SHIFT 4
-#define BCHP_PCIE_0_RC_CFG_PCIE_LINK_CAPABILITY_MAX_LINK_WIDTH_DEFAULT 0x00000001
-
-/* PCIE_0_RC_CFG_PCIE :: LINK_CAPABILITY :: MAX_LINK_SPEED [03:00] */
-#define BCHP_PCIE_0_RC_CFG_PCIE_LINK_CAPABILITY_MAX_LINK_SPEED_MASK 0x0000000f
-#define BCHP_PCIE_0_RC_CFG_PCIE_LINK_CAPABILITY_MAX_LINK_SPEED_SHIFT 0
-#define BCHP_PCIE_0_RC_CFG_PCIE_LINK_CAPABILITY_MAX_LINK_SPEED_DEFAULT 0x00000002
-
-/***************************************************************************
- *LINK_STATUS_CONTROL - link_status_control
- ***************************************************************************/
-/* PCIE_0_RC_CFG_PCIE :: LINK_STATUS_CONTROL :: RESERVED3 [31:30] */
-#define BCHP_PCIE_0_RC_CFG_PCIE_LINK_STATUS_CONTROL_RESERVED3_MASK 0xc0000000
-#define BCHP_PCIE_0_RC_CFG_PCIE_LINK_STATUS_CONTROL_RESERVED3_SHIFT 30
-
-/* PCIE_0_RC_CFG_PCIE :: LINK_STATUS_CONTROL :: DL_ACTIVE [29:29] */
-#define BCHP_PCIE_0_RC_CFG_PCIE_LINK_STATUS_CONTROL_DL_ACTIVE_MASK 0x20000000
-#define BCHP_PCIE_0_RC_CFG_PCIE_LINK_STATUS_CONTROL_DL_ACTIVE_SHIFT 29
-#define BCHP_PCIE_0_RC_CFG_PCIE_LINK_STATUS_CONTROL_DL_ACTIVE_DEFAULT 0x00000000
-
-/* PCIE_0_RC_CFG_PCIE :: LINK_STATUS_CONTROL :: SLOT_CLK_CONFIG [28:28] */
-#define BCHP_PCIE_0_RC_CFG_PCIE_LINK_STATUS_CONTROL_SLOT_CLK_CONFIG_MASK 0x10000000
-#define BCHP_PCIE_0_RC_CFG_PCIE_LINK_STATUS_CONTROL_SLOT_CLK_CONFIG_SHIFT 28
-#define BCHP_PCIE_0_RC_CFG_PCIE_LINK_STATUS_CONTROL_SLOT_CLK_CONFIG_DEFAULT 0x00000001
-
-/* PCIE_0_RC_CFG_PCIE :: LINK_STATUS_CONTROL :: LINK_TRAINING [27:27] */
-#define BCHP_PCIE_0_RC_CFG_PCIE_LINK_STATUS_CONTROL_LINK_TRAINING_MASK 0x08000000
-#define BCHP_PCIE_0_RC_CFG_PCIE_LINK_STATUS_CONTROL_LINK_TRAINING_SHIFT 27
-#define BCHP_PCIE_0_RC_CFG_PCIE_LINK_STATUS_CONTROL_LINK_TRAINING_DEFAULT 0x00000000
-
-/* PCIE_0_RC_CFG_PCIE :: LINK_STATUS_CONTROL :: RESERVED2 [26:26] */
-#define BCHP_PCIE_0_RC_CFG_PCIE_LINK_STATUS_CONTROL_RESERVED2_MASK 0x04000000
-#define BCHP_PCIE_0_RC_CFG_PCIE_LINK_STATUS_CONTROL_RESERVED2_SHIFT 26
-
-/* PCIE_0_RC_CFG_PCIE :: LINK_STATUS_CONTROL :: NEG_LINK_WIDTH [25:20] */
-#define BCHP_PCIE_0_RC_CFG_PCIE_LINK_STATUS_CONTROL_NEG_LINK_WIDTH_MASK 0x03f00000
-#define BCHP_PCIE_0_RC_CFG_PCIE_LINK_STATUS_CONTROL_NEG_LINK_WIDTH_SHIFT 20
-#define BCHP_PCIE_0_RC_CFG_PCIE_LINK_STATUS_CONTROL_NEG_LINK_WIDTH_DEFAULT 0x00000000
-
-/* PCIE_0_RC_CFG_PCIE :: LINK_STATUS_CONTROL :: NEG_LINK_SPEED [19:16] */
-#define BCHP_PCIE_0_RC_CFG_PCIE_LINK_STATUS_CONTROL_NEG_LINK_SPEED_MASK 0x000f0000
-#define BCHP_PCIE_0_RC_CFG_PCIE_LINK_STATUS_CONTROL_NEG_LINK_SPEED_SHIFT 16
-#define BCHP_PCIE_0_RC_CFG_PCIE_LINK_STATUS_CONTROL_NEG_LINK_SPEED_DEFAULT 0x00000000
-
-/* PCIE_0_RC_CFG_PCIE :: LINK_STATUS_CONTROL :: RESERVED1 [15:12] */
-#define BCHP_PCIE_0_RC_CFG_PCIE_LINK_STATUS_CONTROL_RESERVED1_MASK 0x0000f000
-#define BCHP_PCIE_0_RC_CFG_PCIE_LINK_STATUS_CONTROL_RESERVED1_SHIFT 12
-
-/* PCIE_0_RC_CFG_PCIE :: LINK_STATUS_CONTROL :: LINK_BW_INT_EN [11:11] */
-#define BCHP_PCIE_0_RC_CFG_PCIE_LINK_STATUS_CONTROL_LINK_BW_INT_EN_MASK 0x00000800
-#define BCHP_PCIE_0_RC_CFG_PCIE_LINK_STATUS_CONTROL_LINK_BW_INT_EN_SHIFT 11
-#define BCHP_PCIE_0_RC_CFG_PCIE_LINK_STATUS_CONTROL_LINK_BW_INT_EN_DEFAULT 0x00000000
-
-/* PCIE_0_RC_CFG_PCIE :: LINK_STATUS_CONTROL :: LINK_BW_MGMT_INT_EN [10:10] */
-#define BCHP_PCIE_0_RC_CFG_PCIE_LINK_STATUS_CONTROL_LINK_BW_MGMT_INT_EN_MASK 0x00000400
-#define BCHP_PCIE_0_RC_CFG_PCIE_LINK_STATUS_CONTROL_LINK_BW_MGMT_INT_EN_SHIFT 10
-#define BCHP_PCIE_0_RC_CFG_PCIE_LINK_STATUS_CONTROL_LINK_BW_MGMT_INT_EN_DEFAULT 0x00000000
-
-/* PCIE_0_RC_CFG_PCIE :: LINK_STATUS_CONTROL :: HW_AUTO_WIDTH_DIS [09:09] */
-#define BCHP_PCIE_0_RC_CFG_PCIE_LINK_STATUS_CONTROL_HW_AUTO_WIDTH_DIS_MASK 0x00000200
-#define BCHP_PCIE_0_RC_CFG_PCIE_LINK_STATUS_CONTROL_HW_AUTO_WIDTH_DIS_SHIFT 9
-#define BCHP_PCIE_0_RC_CFG_PCIE_LINK_STATUS_CONTROL_HW_AUTO_WIDTH_DIS_DEFAULT 0x00000000
-
-/* PCIE_0_RC_CFG_PCIE :: LINK_STATUS_CONTROL :: EN_CLK_PW_MGMT [08:08] */
-#define BCHP_PCIE_0_RC_CFG_PCIE_LINK_STATUS_CONTROL_EN_CLK_PW_MGMT_MASK 0x00000100
-#define BCHP_PCIE_0_RC_CFG_PCIE_LINK_STATUS_CONTROL_EN_CLK_PW_MGMT_SHIFT 8
-#define BCHP_PCIE_0_RC_CFG_PCIE_LINK_STATUS_CONTROL_EN_CLK_PW_MGMT_DEFAULT 0x00000000
-
-/* PCIE_0_RC_CFG_PCIE :: LINK_STATUS_CONTROL :: LINK_CR_EXT_SYNC [07:07] */
-#define BCHP_PCIE_0_RC_CFG_PCIE_LINK_STATUS_CONTROL_LINK_CR_EXT_SYNC_MASK 0x00000080
-#define BCHP_PCIE_0_RC_CFG_PCIE_LINK_STATUS_CONTROL_LINK_CR_EXT_SYNC_SHIFT 7
-#define BCHP_PCIE_0_RC_CFG_PCIE_LINK_STATUS_CONTROL_LINK_CR_EXT_SYNC_DEFAULT 0x00000000
-
-/* PCIE_0_RC_CFG_PCIE :: LINK_STATUS_CONTROL :: LINK_CR_COMMON_CLK [06:06] */
-#define BCHP_PCIE_0_RC_CFG_PCIE_LINK_STATUS_CONTROL_LINK_CR_COMMON_CLK_MASK 0x00000040
-#define BCHP_PCIE_0_RC_CFG_PCIE_LINK_STATUS_CONTROL_LINK_CR_COMMON_CLK_SHIFT 6
-#define BCHP_PCIE_0_RC_CFG_PCIE_LINK_STATUS_CONTROL_LINK_CR_COMMON_CLK_DEFAULT 0x00000000
-
-/* PCIE_0_RC_CFG_PCIE :: LINK_STATUS_CONTROL :: CFG_PSM_RETRAIN_LINK [05:05] */
-#define BCHP_PCIE_0_RC_CFG_PCIE_LINK_STATUS_CONTROL_CFG_PSM_RETRAIN_LINK_MASK 0x00000020
-#define BCHP_PCIE_0_RC_CFG_PCIE_LINK_STATUS_CONTROL_CFG_PSM_RETRAIN_LINK_SHIFT 5
-#define BCHP_PCIE_0_RC_CFG_PCIE_LINK_STATUS_CONTROL_CFG_PSM_RETRAIN_LINK_DEFAULT 0x00000000
-
-/* PCIE_0_RC_CFG_PCIE :: LINK_STATUS_CONTROL :: CFG_PSM_LINK_DISABLE [04:04] */
-#define BCHP_PCIE_0_RC_CFG_PCIE_LINK_STATUS_CONTROL_CFG_PSM_LINK_DISABLE_MASK 0x00000010
-#define BCHP_PCIE_0_RC_CFG_PCIE_LINK_STATUS_CONTROL_CFG_PSM_LINK_DISABLE_SHIFT 4
-#define BCHP_PCIE_0_RC_CFG_PCIE_LINK_STATUS_CONTROL_CFG_PSM_LINK_DISABLE_DEFAULT 0x00000000
-
-/* PCIE_0_RC_CFG_PCIE :: LINK_STATUS_CONTROL :: RCB [03:03] */
-#define BCHP_PCIE_0_RC_CFG_PCIE_LINK_STATUS_CONTROL_RCB_MASK 0x00000008
-#define BCHP_PCIE_0_RC_CFG_PCIE_LINK_STATUS_CONTROL_RCB_SHIFT 3
-#define BCHP_PCIE_0_RC_CFG_PCIE_LINK_STATUS_CONTROL_RCB_DEFAULT 0x00000000
-
-/* PCIE_0_RC_CFG_PCIE :: LINK_STATUS_CONTROL :: RESERVED0 [02:02] */
-#define BCHP_PCIE_0_RC_CFG_PCIE_LINK_STATUS_CONTROL_RESERVED0_MASK 0x00000004
-#define BCHP_PCIE_0_RC_CFG_PCIE_LINK_STATUS_CONTROL_RESERVED0_SHIFT 2
-
-/* PCIE_0_RC_CFG_PCIE :: LINK_STATUS_CONTROL :: ASPM_CTRL [01:00] */
-#define BCHP_PCIE_0_RC_CFG_PCIE_LINK_STATUS_CONTROL_ASPM_CTRL_MASK 0x00000003
-#define BCHP_PCIE_0_RC_CFG_PCIE_LINK_STATUS_CONTROL_ASPM_CTRL_SHIFT 0
-#define BCHP_PCIE_0_RC_CFG_PCIE_LINK_STATUS_CONTROL_ASPM_CTRL_DEFAULT 0x00000000
-
-/***************************************************************************
- *SLOT_CAPABILITY - slot_capability
- ***************************************************************************/
-/* PCIE_0_RC_CFG_PCIE :: SLOT_CAPABILITY :: PHYSICAL_SLOT_NUMBER [31:19] */
-#define BCHP_PCIE_0_RC_CFG_PCIE_SLOT_CAPABILITY_PHYSICAL_SLOT_NUMBER_MASK 0xfff80000
-#define BCHP_PCIE_0_RC_CFG_PCIE_SLOT_CAPABILITY_PHYSICAL_SLOT_NUMBER_SHIFT 19
-#define BCHP_PCIE_0_RC_CFG_PCIE_SLOT_CAPABILITY_PHYSICAL_SLOT_NUMBER_DEFAULT 0x00000000
-
-/* PCIE_0_RC_CFG_PCIE :: SLOT_CAPABILITY :: UNUSED [18:17] */
-#define BCHP_PCIE_0_RC_CFG_PCIE_SLOT_CAPABILITY_UNUSED_MASK 0x00060000
-#define BCHP_PCIE_0_RC_CFG_PCIE_SLOT_CAPABILITY_UNUSED_SHIFT 17
-#define BCHP_PCIE_0_RC_CFG_PCIE_SLOT_CAPABILITY_UNUSED_DEFAULT 0x00000000
-
-/* PCIE_0_RC_CFG_PCIE :: SLOT_CAPABILITY :: SLOT_POWER_LIMIT_SCALE [16:15] */
-#define BCHP_PCIE_0_RC_CFG_PCIE_SLOT_CAPABILITY_SLOT_POWER_LIMIT_SCALE_MASK 0x00018000
-#define BCHP_PCIE_0_RC_CFG_PCIE_SLOT_CAPABILITY_SLOT_POWER_LIMIT_SCALE_SHIFT 15
-#define BCHP_PCIE_0_RC_CFG_PCIE_SLOT_CAPABILITY_SLOT_POWER_LIMIT_SCALE_DEFAULT 0x00000000
-
-/* PCIE_0_RC_CFG_PCIE :: SLOT_CAPABILITY :: SLOT_POWER_LIMIT_VALUE [14:07] */
-#define BCHP_PCIE_0_RC_CFG_PCIE_SLOT_CAPABILITY_SLOT_POWER_LIMIT_VALUE_MASK 0x00007f80
-#define BCHP_PCIE_0_RC_CFG_PCIE_SLOT_CAPABILITY_SLOT_POWER_LIMIT_VALUE_SHIFT 7
-#define BCHP_PCIE_0_RC_CFG_PCIE_SLOT_CAPABILITY_SLOT_POWER_LIMIT_VALUE_DEFAULT 0x00000000
-
-/* PCIE_0_RC_CFG_PCIE :: SLOT_CAPABILITY :: UNUSED_2 [06:00] */
-#define BCHP_PCIE_0_RC_CFG_PCIE_SLOT_CAPABILITY_UNUSED_2_MASK 0x0000007f
-#define BCHP_PCIE_0_RC_CFG_PCIE_SLOT_CAPABILITY_UNUSED_2_SHIFT 0
-#define BCHP_PCIE_0_RC_CFG_PCIE_SLOT_CAPABILITY_UNUSED_2_DEFAULT 0x00000000
-
-/***************************************************************************
- *SLOT_CONTROL_STATUS - slot_control_status
- ***************************************************************************/
-/* PCIE_0_RC_CFG_PCIE :: SLOT_CONTROL_STATUS :: SLOT_STATUS [31:23] */
-#define BCHP_PCIE_0_RC_CFG_PCIE_SLOT_CONTROL_STATUS_SLOT_STATUS_MASK 0xff800000
-#define BCHP_PCIE_0_RC_CFG_PCIE_SLOT_CONTROL_STATUS_SLOT_STATUS_SHIFT 23
-#define BCHP_PCIE_0_RC_CFG_PCIE_SLOT_CONTROL_STATUS_SLOT_STATUS_DEFAULT 0x00000000
-
-/* PCIE_0_RC_CFG_PCIE :: SLOT_CONTROL_STATUS :: PRESENCE_DETECT [22:22] */
-#define BCHP_PCIE_0_RC_CFG_PCIE_SLOT_CONTROL_STATUS_PRESENCE_DETECT_MASK 0x00400000
-#define BCHP_PCIE_0_RC_CFG_PCIE_SLOT_CONTROL_STATUS_PRESENCE_DETECT_SHIFT 22
-#define BCHP_PCIE_0_RC_CFG_PCIE_SLOT_CONTROL_STATUS_PRESENCE_DETECT_DEFAULT 0x00000001
-
-/* PCIE_0_RC_CFG_PCIE :: SLOT_CONTROL_STATUS :: UNUSED_1 [21:16] */
-#define BCHP_PCIE_0_RC_CFG_PCIE_SLOT_CONTROL_STATUS_UNUSED_1_MASK 0x003f0000
-#define BCHP_PCIE_0_RC_CFG_PCIE_SLOT_CONTROL_STATUS_UNUSED_1_SHIFT 16
-#define BCHP_PCIE_0_RC_CFG_PCIE_SLOT_CONTROL_STATUS_UNUSED_1_DEFAULT 0x00000000
-
-/* PCIE_0_RC_CFG_PCIE :: SLOT_CONTROL_STATUS :: SLOT_CONTROL [15:00] */
-#define BCHP_PCIE_0_RC_CFG_PCIE_SLOT_CONTROL_STATUS_SLOT_CONTROL_MASK 0x0000ffff
-#define BCHP_PCIE_0_RC_CFG_PCIE_SLOT_CONTROL_STATUS_SLOT_CONTROL_SHIFT 0
-#define BCHP_PCIE_0_RC_CFG_PCIE_SLOT_CONTROL_STATUS_SLOT_CONTROL_DEFAULT 0x00000000
-
-/***************************************************************************
- *ROOT_CAP_CONTROL - root_cap_control
- ***************************************************************************/
-/* PCIE_0_RC_CFG_PCIE :: ROOT_CAP_CONTROL :: RESERVED1 [31:17] */
-#define BCHP_PCIE_0_RC_CFG_PCIE_ROOT_CAP_CONTROL_RESERVED1_MASK 0xfffe0000
-#define BCHP_PCIE_0_RC_CFG_PCIE_ROOT_CAP_CONTROL_RESERVED1_SHIFT 17
-
-/* PCIE_0_RC_CFG_PCIE :: ROOT_CAP_CONTROL :: RC_CRS_VISIBILITY [16:16] */
-#define BCHP_PCIE_0_RC_CFG_PCIE_ROOT_CAP_CONTROL_RC_CRS_VISIBILITY_MASK 0x00010000
-#define BCHP_PCIE_0_RC_CFG_PCIE_ROOT_CAP_CONTROL_RC_CRS_VISIBILITY_SHIFT 16
-#define BCHP_PCIE_0_RC_CFG_PCIE_ROOT_CAP_CONTROL_RC_CRS_VISIBILITY_DEFAULT 0x00000001
-
-/* PCIE_0_RC_CFG_PCIE :: ROOT_CAP_CONTROL :: RESERVED0 [15:05] */
-#define BCHP_PCIE_0_RC_CFG_PCIE_ROOT_CAP_CONTROL_RESERVED0_MASK 0x0000ffe0
-#define BCHP_PCIE_0_RC_CFG_PCIE_ROOT_CAP_CONTROL_RESERVED0_SHIFT 5
-
-/* PCIE_0_RC_CFG_PCIE :: ROOT_CAP_CONTROL :: RC_CRS_EN [04:04] */
-#define BCHP_PCIE_0_RC_CFG_PCIE_ROOT_CAP_CONTROL_RC_CRS_EN_MASK 0x00000010
-#define BCHP_PCIE_0_RC_CFG_PCIE_ROOT_CAP_CONTROL_RC_CRS_EN_SHIFT 4
-#define BCHP_PCIE_0_RC_CFG_PCIE_ROOT_CAP_CONTROL_RC_CRS_EN_DEFAULT 0x00000000
-
-/* PCIE_0_RC_CFG_PCIE :: ROOT_CAP_CONTROL :: RC_PME_INT_EN [03:03] */
-#define BCHP_PCIE_0_RC_CFG_PCIE_ROOT_CAP_CONTROL_RC_PME_INT_EN_MASK 0x00000008
-#define BCHP_PCIE_0_RC_CFG_PCIE_ROOT_CAP_CONTROL_RC_PME_INT_EN_SHIFT 3
-#define BCHP_PCIE_0_RC_CFG_PCIE_ROOT_CAP_CONTROL_RC_PME_INT_EN_DEFAULT 0x00000000
-
-/* PCIE_0_RC_CFG_PCIE :: ROOT_CAP_CONTROL :: RC_FATAL_SERR_EN [02:02] */
-#define BCHP_PCIE_0_RC_CFG_PCIE_ROOT_CAP_CONTROL_RC_FATAL_SERR_EN_MASK 0x00000004
-#define BCHP_PCIE_0_RC_CFG_PCIE_ROOT_CAP_CONTROL_RC_FATAL_SERR_EN_SHIFT 2
-#define BCHP_PCIE_0_RC_CFG_PCIE_ROOT_CAP_CONTROL_RC_FATAL_SERR_EN_DEFAULT 0x00000000
-
-/* PCIE_0_RC_CFG_PCIE :: ROOT_CAP_CONTROL :: RC_NONFATAL_SERR_EN [01:01] */
-#define BCHP_PCIE_0_RC_CFG_PCIE_ROOT_CAP_CONTROL_RC_NONFATAL_SERR_EN_MASK 0x00000002
-#define BCHP_PCIE_0_RC_CFG_PCIE_ROOT_CAP_CONTROL_RC_NONFATAL_SERR_EN_SHIFT 1
-#define BCHP_PCIE_0_RC_CFG_PCIE_ROOT_CAP_CONTROL_RC_NONFATAL_SERR_EN_DEFAULT 0x00000000
-
-/* PCIE_0_RC_CFG_PCIE :: ROOT_CAP_CONTROL :: RC_CORR_SERR_EN [00:00] */
-#define BCHP_PCIE_0_RC_CFG_PCIE_ROOT_CAP_CONTROL_RC_CORR_SERR_EN_MASK 0x00000001
-#define BCHP_PCIE_0_RC_CFG_PCIE_ROOT_CAP_CONTROL_RC_CORR_SERR_EN_SHIFT 0
-#define BCHP_PCIE_0_RC_CFG_PCIE_ROOT_CAP_CONTROL_RC_CORR_SERR_EN_DEFAULT 0x00000000
-
-/***************************************************************************
- *ROOT_STATUS - root_status
- ***************************************************************************/
-/* PCIE_0_RC_CFG_PCIE :: ROOT_STATUS :: RESERVED0 [31:18] */
-#define BCHP_PCIE_0_RC_CFG_PCIE_ROOT_STATUS_RESERVED0_MASK 0xfffc0000
-#define BCHP_PCIE_0_RC_CFG_PCIE_ROOT_STATUS_RESERVED0_SHIFT 18
-
-/* PCIE_0_RC_CFG_PCIE :: ROOT_STATUS :: RC_PME_PENDING [17:17] */
-#define BCHP_PCIE_0_RC_CFG_PCIE_ROOT_STATUS_RC_PME_PENDING_MASK 0x00020000
-#define BCHP_PCIE_0_RC_CFG_PCIE_ROOT_STATUS_RC_PME_PENDING_SHIFT 17
-#define BCHP_PCIE_0_RC_CFG_PCIE_ROOT_STATUS_RC_PME_PENDING_DEFAULT 0x00000000
-
-/* PCIE_0_RC_CFG_PCIE :: ROOT_STATUS :: RC_PME_STATUS [16:16] */
-#define BCHP_PCIE_0_RC_CFG_PCIE_ROOT_STATUS_RC_PME_STATUS_MASK 0x00010000
-#define BCHP_PCIE_0_RC_CFG_PCIE_ROOT_STATUS_RC_PME_STATUS_SHIFT 16
-#define BCHP_PCIE_0_RC_CFG_PCIE_ROOT_STATUS_RC_PME_STATUS_DEFAULT 0x00000000
-
-/* PCIE_0_RC_CFG_PCIE :: ROOT_STATUS :: RC_PME_REQ_ID [15:00] */
-#define BCHP_PCIE_0_RC_CFG_PCIE_ROOT_STATUS_RC_PME_REQ_ID_MASK 0x0000ffff
-#define BCHP_PCIE_0_RC_CFG_PCIE_ROOT_STATUS_RC_PME_REQ_ID_SHIFT 0
-#define BCHP_PCIE_0_RC_CFG_PCIE_ROOT_STATUS_RC_PME_REQ_ID_DEFAULT 0x00000000
-
-/***************************************************************************
- *DEVICE_CAPABILITY_2 - device_capability_2
- ***************************************************************************/
-/* PCIE_0_RC_CFG_PCIE :: DEVICE_CAPABILITY_2 :: RESERVED0 [31:05] */
-#define BCHP_PCIE_0_RC_CFG_PCIE_DEVICE_CAPABILITY_2_RESERVED0_MASK 0xffffffe0
-#define BCHP_PCIE_0_RC_CFG_PCIE_DEVICE_CAPABILITY_2_RESERVED0_SHIFT 5
-
-/* PCIE_0_RC_CFG_PCIE :: DEVICE_CAPABILITY_2 :: CMPL_TIMEOUT_DISABL_SUPPORTED [04:04] */
-#define BCHP_PCIE_0_RC_CFG_PCIE_DEVICE_CAPABILITY_2_CMPL_TIMEOUT_DISABL_SUPPORTED_MASK 0x00000010
-#define BCHP_PCIE_0_RC_CFG_PCIE_DEVICE_CAPABILITY_2_CMPL_TIMEOUT_DISABL_SUPPORTED_SHIFT 4
-#define BCHP_PCIE_0_RC_CFG_PCIE_DEVICE_CAPABILITY_2_CMPL_TIMEOUT_DISABL_SUPPORTED_DEFAULT 0x00000001
-
-/* PCIE_0_RC_CFG_PCIE :: DEVICE_CAPABILITY_2 :: CMPL_TIMEOUT_RANGES_SUPPORTED [03:00] */
-#define BCHP_PCIE_0_RC_CFG_PCIE_DEVICE_CAPABILITY_2_CMPL_TIMEOUT_RANGES_SUPPORTED_MASK 0x0000000f
-#define BCHP_PCIE_0_RC_CFG_PCIE_DEVICE_CAPABILITY_2_CMPL_TIMEOUT_RANGES_SUPPORTED_SHIFT 0
-#define BCHP_PCIE_0_RC_CFG_PCIE_DEVICE_CAPABILITY_2_CMPL_TIMEOUT_RANGES_SUPPORTED_DEFAULT 0x0000000f
-
-/***************************************************************************
- *DEVICE_STATUS_CONTROL_2 - device_status_control_2
- ***************************************************************************/
-/* PCIE_0_RC_CFG_PCIE :: DEVICE_STATUS_CONTROL_2 :: DEVICE_STATUS_2 [31:16] */
-#define BCHP_PCIE_0_RC_CFG_PCIE_DEVICE_STATUS_CONTROL_2_DEVICE_STATUS_2_MASK 0xffff0000
-#define BCHP_PCIE_0_RC_CFG_PCIE_DEVICE_STATUS_CONTROL_2_DEVICE_STATUS_2_SHIFT 16
-#define BCHP_PCIE_0_RC_CFG_PCIE_DEVICE_STATUS_CONTROL_2_DEVICE_STATUS_2_DEFAULT 0x00000000
-
-/* PCIE_0_RC_CFG_PCIE :: DEVICE_STATUS_CONTROL_2 :: RESERVED0 [15:05] */
-#define BCHP_PCIE_0_RC_CFG_PCIE_DEVICE_STATUS_CONTROL_2_RESERVED0_MASK 0x0000ffe0
-#define BCHP_PCIE_0_RC_CFG_PCIE_DEVICE_STATUS_CONTROL_2_RESERVED0_SHIFT 5
-
-/* PCIE_0_RC_CFG_PCIE :: DEVICE_STATUS_CONTROL_2 :: CMPL_TIMEOUT_DISABLE [04:04] */
-#define BCHP_PCIE_0_RC_CFG_PCIE_DEVICE_STATUS_CONTROL_2_CMPL_TIMEOUT_DISABLE_MASK 0x00000010
-#define BCHP_PCIE_0_RC_CFG_PCIE_DEVICE_STATUS_CONTROL_2_CMPL_TIMEOUT_DISABLE_SHIFT 4
-#define BCHP_PCIE_0_RC_CFG_PCIE_DEVICE_STATUS_CONTROL_2_CMPL_TIMEOUT_DISABLE_DEFAULT 0x00000000
-
-/* PCIE_0_RC_CFG_PCIE :: DEVICE_STATUS_CONTROL_2 :: CMPL_TIMEOUT_VALUE [03:00] */
-#define BCHP_PCIE_0_RC_CFG_PCIE_DEVICE_STATUS_CONTROL_2_CMPL_TIMEOUT_VALUE_MASK 0x0000000f
-#define BCHP_PCIE_0_RC_CFG_PCIE_DEVICE_STATUS_CONTROL_2_CMPL_TIMEOUT_VALUE_SHIFT 0
-#define BCHP_PCIE_0_RC_CFG_PCIE_DEVICE_STATUS_CONTROL_2_CMPL_TIMEOUT_VALUE_DEFAULT 0x00000000
-
-/***************************************************************************
- *LINK_CAPABILITY_2 - link_capability_2
- ***************************************************************************/
-/* PCIE_0_RC_CFG_PCIE :: LINK_CAPABILITY_2 :: LINK_CAPABILITY_2 [31:00] */
-#define BCHP_PCIE_0_RC_CFG_PCIE_LINK_CAPABILITY_2_LINK_CAPABILITY_2_MASK 0xffffffff
-#define BCHP_PCIE_0_RC_CFG_PCIE_LINK_CAPABILITY_2_LINK_CAPABILITY_2_SHIFT 0
-#define BCHP_PCIE_0_RC_CFG_PCIE_LINK_CAPABILITY_2_LINK_CAPABILITY_2_DEFAULT 0x00000000
-
-/***************************************************************************
- *LINK_STATUS_CONTROL_2 - link_status_control_2
- ***************************************************************************/
-/* PCIE_0_RC_CFG_PCIE :: LINK_STATUS_CONTROL_2 :: LINK_STATUS_2 [31:17] */
-#define BCHP_PCIE_0_RC_CFG_PCIE_LINK_STATUS_CONTROL_2_LINK_STATUS_2_MASK 0xfffe0000
-#define BCHP_PCIE_0_RC_CFG_PCIE_LINK_STATUS_CONTROL_2_LINK_STATUS_2_SHIFT 17
-#define BCHP_PCIE_0_RC_CFG_PCIE_LINK_STATUS_CONTROL_2_LINK_STATUS_2_DEFAULT 0x00000000
-
-/* PCIE_0_RC_CFG_PCIE :: LINK_STATUS_CONTROL_2 :: CURR_DEEMPH_LEVEL [16:16] */
-#define BCHP_PCIE_0_RC_CFG_PCIE_LINK_STATUS_CONTROL_2_CURR_DEEMPH_LEVEL_MASK 0x00010000
-#define BCHP_PCIE_0_RC_CFG_PCIE_LINK_STATUS_CONTROL_2_CURR_DEEMPH_LEVEL_SHIFT 16
-#define BCHP_PCIE_0_RC_CFG_PCIE_LINK_STATUS_CONTROL_2_CURR_DEEMPH_LEVEL_DEFAULT 0x00000000
-
-/* PCIE_0_RC_CFG_PCIE :: LINK_STATUS_CONTROL_2 :: RESERVED0 [15:13] */
-#define BCHP_PCIE_0_RC_CFG_PCIE_LINK_STATUS_CONTROL_2_RESERVED0_MASK 0x0000e000
-#define BCHP_PCIE_0_RC_CFG_PCIE_LINK_STATUS_CONTROL_2_RESERVED0_SHIFT 13
-
-/* PCIE_0_RC_CFG_PCIE :: LINK_STATUS_CONTROL_2 :: CFG_COMPLIANCE_DEEMPH [12:12] */
-#define BCHP_PCIE_0_RC_CFG_PCIE_LINK_STATUS_CONTROL_2_CFG_COMPLIANCE_DEEMPH_MASK 0x00001000
-#define BCHP_PCIE_0_RC_CFG_PCIE_LINK_STATUS_CONTROL_2_CFG_COMPLIANCE_DEEMPH_SHIFT 12
-#define BCHP_PCIE_0_RC_CFG_PCIE_LINK_STATUS_CONTROL_2_CFG_COMPLIANCE_DEEMPH_DEFAULT 0x00000000
-
-/* PCIE_0_RC_CFG_PCIE :: LINK_STATUS_CONTROL_2 :: CFG_COMPLIANCE_SOS [11:11] */
-#define BCHP_PCIE_0_RC_CFG_PCIE_LINK_STATUS_CONTROL_2_CFG_COMPLIANCE_SOS_MASK 0x00000800
-#define BCHP_PCIE_0_RC_CFG_PCIE_LINK_STATUS_CONTROL_2_CFG_COMPLIANCE_SOS_SHIFT 11
-#define BCHP_PCIE_0_RC_CFG_PCIE_LINK_STATUS_CONTROL_2_CFG_COMPLIANCE_SOS_DEFAULT 0x00000000
-
-/* PCIE_0_RC_CFG_PCIE :: LINK_STATUS_CONTROL_2 :: CFG_ENTER_MOD_COMPLIANCE [10:10] */
-#define BCHP_PCIE_0_RC_CFG_PCIE_LINK_STATUS_CONTROL_2_CFG_ENTER_MOD_COMPLIANCE_MASK 0x00000400
-#define BCHP_PCIE_0_RC_CFG_PCIE_LINK_STATUS_CONTROL_2_CFG_ENTER_MOD_COMPLIANCE_SHIFT 10
-#define BCHP_PCIE_0_RC_CFG_PCIE_LINK_STATUS_CONTROL_2_CFG_ENTER_MOD_COMPLIANCE_DEFAULT 0x00000000
-
-/* PCIE_0_RC_CFG_PCIE :: LINK_STATUS_CONTROL_2 :: CFG_TX_MARGIN [09:07] */
-#define BCHP_PCIE_0_RC_CFG_PCIE_LINK_STATUS_CONTROL_2_CFG_TX_MARGIN_MASK 0x00000380
-#define BCHP_PCIE_0_RC_CFG_PCIE_LINK_STATUS_CONTROL_2_CFG_TX_MARGIN_SHIFT 7
-#define BCHP_PCIE_0_RC_CFG_PCIE_LINK_STATUS_CONTROL_2_CFG_TX_MARGIN_DEFAULT 0x00000000
-
-/* PCIE_0_RC_CFG_PCIE :: LINK_STATUS_CONTROL_2 :: SEL_DEEMPHASIS [06:06] */
-#define BCHP_PCIE_0_RC_CFG_PCIE_LINK_STATUS_CONTROL_2_SEL_DEEMPHASIS_MASK 0x00000040
-#define BCHP_PCIE_0_RC_CFG_PCIE_LINK_STATUS_CONTROL_2_SEL_DEEMPHASIS_SHIFT 6
-#define BCHP_PCIE_0_RC_CFG_PCIE_LINK_STATUS_CONTROL_2_SEL_DEEMPHASIS_DEFAULT 0x00000000
-
-/* PCIE_0_RC_CFG_PCIE :: LINK_STATUS_CONTROL_2 :: HW_AUTO_SPEED_DISABLE [05:05] */
-#define BCHP_PCIE_0_RC_CFG_PCIE_LINK_STATUS_CONTROL_2_HW_AUTO_SPEED_DISABLE_MASK 0x00000020
-#define BCHP_PCIE_0_RC_CFG_PCIE_LINK_STATUS_CONTROL_2_HW_AUTO_SPEED_DISABLE_SHIFT 5
-#define BCHP_PCIE_0_RC_CFG_PCIE_LINK_STATUS_CONTROL_2_HW_AUTO_SPEED_DISABLE_DEFAULT 0x00000000
-
-/* PCIE_0_RC_CFG_PCIE :: LINK_STATUS_CONTROL_2 :: ENTER_COMPLIANCE [04:04] */
-#define BCHP_PCIE_0_RC_CFG_PCIE_LINK_STATUS_CONTROL_2_ENTER_COMPLIANCE_MASK 0x00000010
-#define BCHP_PCIE_0_RC_CFG_PCIE_LINK_STATUS_CONTROL_2_ENTER_COMPLIANCE_SHIFT 4
-#define BCHP_PCIE_0_RC_CFG_PCIE_LINK_STATUS_CONTROL_2_ENTER_COMPLIANCE_DEFAULT 0x00000000
-
-/* PCIE_0_RC_CFG_PCIE :: LINK_STATUS_CONTROL_2 :: TARGET_LINK_SPEED [03:00] */
-#define BCHP_PCIE_0_RC_CFG_PCIE_LINK_STATUS_CONTROL_2_TARGET_LINK_SPEED_MASK 0x0000000f
-#define BCHP_PCIE_0_RC_CFG_PCIE_LINK_STATUS_CONTROL_2_TARGET_LINK_SPEED_SHIFT 0
-#define BCHP_PCIE_0_RC_CFG_PCIE_LINK_STATUS_CONTROL_2_TARGET_LINK_SPEED_DEFAULT 0x00000001
-
-/***************************************************************************
- *SLOT_CAPABILITY_2 - slot_capability_2
- ***************************************************************************/
-/* PCIE_0_RC_CFG_PCIE :: SLOT_CAPABILITY_2 :: SLOT_CAPABILITY_2 [31:00] */
-#define BCHP_PCIE_0_RC_CFG_PCIE_SLOT_CAPABILITY_2_SLOT_CAPABILITY_2_MASK 0xffffffff
-#define BCHP_PCIE_0_RC_CFG_PCIE_SLOT_CAPABILITY_2_SLOT_CAPABILITY_2_SHIFT 0
-#define BCHP_PCIE_0_RC_CFG_PCIE_SLOT_CAPABILITY_2_SLOT_CAPABILITY_2_DEFAULT 0x00000000
-
-/***************************************************************************
- *SLOT_STATUS_CONTROL_2 - slot_status_control_2
- ***************************************************************************/
-/* PCIE_0_RC_CFG_PCIE :: SLOT_STATUS_CONTROL_2 :: SLOT_STATUS_2 [31:16] */
-#define BCHP_PCIE_0_RC_CFG_PCIE_SLOT_STATUS_CONTROL_2_SLOT_STATUS_2_MASK 0xffff0000
-#define BCHP_PCIE_0_RC_CFG_PCIE_SLOT_STATUS_CONTROL_2_SLOT_STATUS_2_SHIFT 16
-#define BCHP_PCIE_0_RC_CFG_PCIE_SLOT_STATUS_CONTROL_2_SLOT_STATUS_2_DEFAULT 0x00000000
-
-/* PCIE_0_RC_CFG_PCIE :: SLOT_STATUS_CONTROL_2 :: SLOT_CONTROL_2 [15:00] */
-#define BCHP_PCIE_0_RC_CFG_PCIE_SLOT_STATUS_CONTROL_2_SLOT_CONTROL_2_MASK 0x0000ffff
-#define BCHP_PCIE_0_RC_CFG_PCIE_SLOT_STATUS_CONTROL_2_SLOT_CONTROL_2_SHIFT 0
-#define BCHP_PCIE_0_RC_CFG_PCIE_SLOT_STATUS_CONTROL_2_SLOT_CONTROL_2_DEFAULT 0x00000000
-
-#endif /* #ifndef BCHP_PCIE_0_RC_CFG_PCIE_H__ */
-
-/* End of File */
diff --git a/include/linux/brcmstb/7145a0/bchp_pcie_0_rc_cfg_type1.h b/include/linux/brcmstb/7145a0/bchp_pcie_0_rc_cfg_type1.h
deleted file mode 100644
index 6d00c02..0000000
--- a/include/linux/brcmstb/7145a0/bchp_pcie_0_rc_cfg_type1.h
+++ /dev/null
@@ -1,526 +0,0 @@
-/***************************************************************************
- * Copyright (c) 1999-2013, Broadcom Corporation
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
- *
- * Module Description:
- * DO NOT EDIT THIS FILE DIRECTLY
- *
- * This module was generated magically with RDB from a source description
- * file. You must edit the source file for changes to be made to this file.
- *
- *
- * Date: Generated on Sat Apr 6 03:07:50 2013
- * MD5 Checksum d41d8cd98f00b204e9800998ecf8427e
- *
- * Compiled with: RDB Utility combo_header.pl
- * RDB Parser 3.0
- * unknown unknown
- * Perl Interpreter 5.008008
- * Operating System linux
- *
- * Revision History:
- *
- * $brcm_Log: $
- *
- ***************************************************************************/
-
-#ifndef BCHP_PCIE_0_RC_CFG_TYPE1_H__
-#define BCHP_PCIE_0_RC_CFG_TYPE1_H__
-
-/***************************************************************************
- *PCIE_0_RC_CFG_TYPE1
- ***************************************************************************/
-#define BCHP_PCIE_0_RC_CFG_TYPE1_DEVICE_VENDOR_ID 0x07800000 /* device_vendor_id */
-#define BCHP_PCIE_0_RC_CFG_TYPE1_STATUS_COMMAND 0x07800004 /* status_command */
-#define BCHP_PCIE_0_RC_CFG_TYPE1_REV_ID_CLASS_CODE 0x07800008 /* rev_id_class_code */
-#define BCHP_PCIE_0_RC_CFG_TYPE1_HEADERTYPE_LAT_CACHELINESIZE 0x0780000c /* headertype_lat_cachelinesize */
-#define BCHP_PCIE_0_RC_CFG_TYPE1_BAR_1 0x07800010 /* bar_1 */
-#define BCHP_PCIE_0_RC_CFG_TYPE1_BAR_2 0x07800014 /* bar_2 */
-#define BCHP_PCIE_0_RC_CFG_TYPE1_PRI_SEC_BUS_NO 0x07800018 /* pri_sec_bus_no */
-#define BCHP_PCIE_0_RC_CFG_TYPE1_SEC_STATUS_IO_BASE_LIMIT 0x0780001c /* sec_status_io_base_limit */
-#define BCHP_PCIE_0_RC_CFG_TYPE1_RC_MEM_BASE_LIMIT 0x07800020 /* rc_mem_base_limit */
-#define BCHP_PCIE_0_RC_CFG_TYPE1_RC_PREF_BASE_LIMIT 0x07800024 /* rc_pref_base_limit */
-#define BCHP_PCIE_0_RC_CFG_TYPE1_RC_PREF_BASE_HI 0x07800028 /* rc_pref_base_hi */
-#define BCHP_PCIE_0_RC_CFG_TYPE1_RC_PREF_LIM_HI 0x0780002c /* rc_pref_lim_hi */
-#define BCHP_PCIE_0_RC_CFG_TYPE1_RC_IO_BASE_LIMIT 0x07800030 /* rc_io_base_limit */
-#define BCHP_PCIE_0_RC_CFG_TYPE1_CAP_POINTER 0x07800034 /* cap_pointer */
-#define BCHP_PCIE_0_RC_CFG_TYPE1_EXP_ROM_BAR 0x07800038 /* exp_rom_bar */
-#define BCHP_PCIE_0_RC_CFG_TYPE1_BRIDGE_CONTROL 0x0780003c /* bridge_control */
-
-/***************************************************************************
- *DEVICE_VENDOR_ID - device_vendor_id
- ***************************************************************************/
-/* PCIE_0_RC_CFG_TYPE1 :: DEVICE_VENDOR_ID :: DEVICE_ID [31:16] */
-#define BCHP_PCIE_0_RC_CFG_TYPE1_DEVICE_VENDOR_ID_DEVICE_ID_MASK 0xffff0000
-#define BCHP_PCIE_0_RC_CFG_TYPE1_DEVICE_VENDOR_ID_DEVICE_ID_SHIFT 16
-
-/* PCIE_0_RC_CFG_TYPE1 :: DEVICE_VENDOR_ID :: VENDOR_ID [15:00] */
-#define BCHP_PCIE_0_RC_CFG_TYPE1_DEVICE_VENDOR_ID_VENDOR_ID_MASK 0x0000ffff
-#define BCHP_PCIE_0_RC_CFG_TYPE1_DEVICE_VENDOR_ID_VENDOR_ID_SHIFT 0
-#define BCHP_PCIE_0_RC_CFG_TYPE1_DEVICE_VENDOR_ID_VENDOR_ID_DEFAULT 0x000014e4
-
-/***************************************************************************
- *STATUS_COMMAND - status_command
- ***************************************************************************/
-/* PCIE_0_RC_CFG_TYPE1 :: STATUS_COMMAND :: PAR_ERR [31:31] */
-#define BCHP_PCIE_0_RC_CFG_TYPE1_STATUS_COMMAND_PAR_ERR_MASK 0x80000000
-#define BCHP_PCIE_0_RC_CFG_TYPE1_STATUS_COMMAND_PAR_ERR_SHIFT 31
-#define BCHP_PCIE_0_RC_CFG_TYPE1_STATUS_COMMAND_PAR_ERR_DEFAULT 0x00000000
-
-/* PCIE_0_RC_CFG_TYPE1 :: STATUS_COMMAND :: SIG_SERR [30:30] */
-#define BCHP_PCIE_0_RC_CFG_TYPE1_STATUS_COMMAND_SIG_SERR_MASK 0x40000000
-#define BCHP_PCIE_0_RC_CFG_TYPE1_STATUS_COMMAND_SIG_SERR_SHIFT 30
-#define BCHP_PCIE_0_RC_CFG_TYPE1_STATUS_COMMAND_SIG_SERR_DEFAULT 0x00000000
-
-/* PCIE_0_RC_CFG_TYPE1 :: STATUS_COMMAND :: RCV_MSTR_ABT [29:29] */
-#define BCHP_PCIE_0_RC_CFG_TYPE1_STATUS_COMMAND_RCV_MSTR_ABT_MASK 0x20000000
-#define BCHP_PCIE_0_RC_CFG_TYPE1_STATUS_COMMAND_RCV_MSTR_ABT_SHIFT 29
-#define BCHP_PCIE_0_RC_CFG_TYPE1_STATUS_COMMAND_RCV_MSTR_ABT_DEFAULT 0x00000000
-
-/* PCIE_0_RC_CFG_TYPE1 :: STATUS_COMMAND :: RCV_TGT_ABT [28:28] */
-#define BCHP_PCIE_0_RC_CFG_TYPE1_STATUS_COMMAND_RCV_TGT_ABT_MASK 0x10000000
-#define BCHP_PCIE_0_RC_CFG_TYPE1_STATUS_COMMAND_RCV_TGT_ABT_SHIFT 28
-#define BCHP_PCIE_0_RC_CFG_TYPE1_STATUS_COMMAND_RCV_TGT_ABT_DEFAULT 0x00000000
-
-/* PCIE_0_RC_CFG_TYPE1 :: STATUS_COMMAND :: SIG_TGT_ABT [27:27] */
-#define BCHP_PCIE_0_RC_CFG_TYPE1_STATUS_COMMAND_SIG_TGT_ABT_MASK 0x08000000
-#define BCHP_PCIE_0_RC_CFG_TYPE1_STATUS_COMMAND_SIG_TGT_ABT_SHIFT 27
-#define BCHP_PCIE_0_RC_CFG_TYPE1_STATUS_COMMAND_SIG_TGT_ABT_DEFAULT 0x00000000
-
-/* PCIE_0_RC_CFG_TYPE1 :: STATUS_COMMAND :: DEVSEL_TIMING [26:25] */
-#define BCHP_PCIE_0_RC_CFG_TYPE1_STATUS_COMMAND_DEVSEL_TIMING_MASK 0x06000000
-#define BCHP_PCIE_0_RC_CFG_TYPE1_STATUS_COMMAND_DEVSEL_TIMING_SHIFT 25
-#define BCHP_PCIE_0_RC_CFG_TYPE1_STATUS_COMMAND_DEVSEL_TIMING_DEFAULT 0x00000000
-
-/* PCIE_0_RC_CFG_TYPE1 :: STATUS_COMMAND :: MSTR_PERR [24:24] */
-#define BCHP_PCIE_0_RC_CFG_TYPE1_STATUS_COMMAND_MSTR_PERR_MASK 0x01000000
-#define BCHP_PCIE_0_RC_CFG_TYPE1_STATUS_COMMAND_MSTR_PERR_SHIFT 24
-#define BCHP_PCIE_0_RC_CFG_TYPE1_STATUS_COMMAND_MSTR_PERR_DEFAULT 0x00000000
-
-/* PCIE_0_RC_CFG_TYPE1 :: STATUS_COMMAND :: FAST_B2B_CAP [23:23] */
-#define BCHP_PCIE_0_RC_CFG_TYPE1_STATUS_COMMAND_FAST_B2B_CAP_MASK 0x00800000
-#define BCHP_PCIE_0_RC_CFG_TYPE1_STATUS_COMMAND_FAST_B2B_CAP_SHIFT 23
-#define BCHP_PCIE_0_RC_CFG_TYPE1_STATUS_COMMAND_FAST_B2B_CAP_DEFAULT 0x00000000
-
-/* PCIE_0_RC_CFG_TYPE1 :: STATUS_COMMAND :: RESERVED1 [22:22] */
-#define BCHP_PCIE_0_RC_CFG_TYPE1_STATUS_COMMAND_RESERVED1_MASK 0x00400000
-#define BCHP_PCIE_0_RC_CFG_TYPE1_STATUS_COMMAND_RESERVED1_SHIFT 22
-#define BCHP_PCIE_0_RC_CFG_TYPE1_STATUS_COMMAND_RESERVED1_DEFAULT 0x00000000
-
-/* PCIE_0_RC_CFG_TYPE1 :: STATUS_COMMAND :: CAP_66MHZ [21:21] */
-#define BCHP_PCIE_0_RC_CFG_TYPE1_STATUS_COMMAND_CAP_66MHZ_MASK 0x00200000
-#define BCHP_PCIE_0_RC_CFG_TYPE1_STATUS_COMMAND_CAP_66MHZ_SHIFT 21
-#define BCHP_PCIE_0_RC_CFG_TYPE1_STATUS_COMMAND_CAP_66MHZ_DEFAULT 0x00000000
-
-/* PCIE_0_RC_CFG_TYPE1 :: STATUS_COMMAND :: CAP_LIST [20:20] */
-#define BCHP_PCIE_0_RC_CFG_TYPE1_STATUS_COMMAND_CAP_LIST_MASK 0x00100000
-#define BCHP_PCIE_0_RC_CFG_TYPE1_STATUS_COMMAND_CAP_LIST_SHIFT 20
-#define BCHP_PCIE_0_RC_CFG_TYPE1_STATUS_COMMAND_CAP_LIST_DEFAULT 0x00000001
-
-/* PCIE_0_RC_CFG_TYPE1 :: STATUS_COMMAND :: INT_STATUS [19:19] */
-#define BCHP_PCIE_0_RC_CFG_TYPE1_STATUS_COMMAND_INT_STATUS_MASK 0x00080000
-#define BCHP_PCIE_0_RC_CFG_TYPE1_STATUS_COMMAND_INT_STATUS_SHIFT 19
-#define BCHP_PCIE_0_RC_CFG_TYPE1_STATUS_COMMAND_INT_STATUS_DEFAULT 0x00000000
-
-/* PCIE_0_RC_CFG_TYPE1 :: STATUS_COMMAND :: RESERVED2 [18:16] */
-#define BCHP_PCIE_0_RC_CFG_TYPE1_STATUS_COMMAND_RESERVED2_MASK 0x00070000
-#define BCHP_PCIE_0_RC_CFG_TYPE1_STATUS_COMMAND_RESERVED2_SHIFT 16
-#define BCHP_PCIE_0_RC_CFG_TYPE1_STATUS_COMMAND_RESERVED2_DEFAULT 0x00000000
-
-/* PCIE_0_RC_CFG_TYPE1 :: STATUS_COMMAND :: RESERVED [15:11] */
-#define BCHP_PCIE_0_RC_CFG_TYPE1_STATUS_COMMAND_RESERVED_MASK 0x0000f800
-#define BCHP_PCIE_0_RC_CFG_TYPE1_STATUS_COMMAND_RESERVED_SHIFT 11
-#define BCHP_PCIE_0_RC_CFG_TYPE1_STATUS_COMMAND_RESERVED_DEFAULT 0x00000000
-
-/* PCIE_0_RC_CFG_TYPE1 :: STATUS_COMMAND :: INT_DISABLE [10:10] */
-#define BCHP_PCIE_0_RC_CFG_TYPE1_STATUS_COMMAND_INT_DISABLE_MASK 0x00000400
-#define BCHP_PCIE_0_RC_CFG_TYPE1_STATUS_COMMAND_INT_DISABLE_SHIFT 10
-#define BCHP_PCIE_0_RC_CFG_TYPE1_STATUS_COMMAND_INT_DISABLE_DEFAULT 0x00000000
-
-/* PCIE_0_RC_CFG_TYPE1 :: STATUS_COMMAND :: FAST_B2B [09:09] */
-#define BCHP_PCIE_0_RC_CFG_TYPE1_STATUS_COMMAND_FAST_B2B_MASK 0x00000200
-#define BCHP_PCIE_0_RC_CFG_TYPE1_STATUS_COMMAND_FAST_B2B_SHIFT 9
-#define BCHP_PCIE_0_RC_CFG_TYPE1_STATUS_COMMAND_FAST_B2B_DEFAULT 0x00000000
-
-/* PCIE_0_RC_CFG_TYPE1 :: STATUS_COMMAND :: SERR_ENA [08:08] */
-#define BCHP_PCIE_0_RC_CFG_TYPE1_STATUS_COMMAND_SERR_ENA_MASK 0x00000100
-#define BCHP_PCIE_0_RC_CFG_TYPE1_STATUS_COMMAND_SERR_ENA_SHIFT 8
-#define BCHP_PCIE_0_RC_CFG_TYPE1_STATUS_COMMAND_SERR_ENA_DEFAULT 0x00000000
-
-/* PCIE_0_RC_CFG_TYPE1 :: STATUS_COMMAND :: STEPPING [07:07] */
-#define BCHP_PCIE_0_RC_CFG_TYPE1_STATUS_COMMAND_STEPPING_MASK 0x00000080
-#define BCHP_PCIE_0_RC_CFG_TYPE1_STATUS_COMMAND_STEPPING_SHIFT 7
-#define BCHP_PCIE_0_RC_CFG_TYPE1_STATUS_COMMAND_STEPPING_DEFAULT 0x00000000
-
-/* PCIE_0_RC_CFG_TYPE1 :: STATUS_COMMAND :: PERR_ENA [06:06] */
-#define BCHP_PCIE_0_RC_CFG_TYPE1_STATUS_COMMAND_PERR_ENA_MASK 0x00000040
-#define BCHP_PCIE_0_RC_CFG_TYPE1_STATUS_COMMAND_PERR_ENA_SHIFT 6
-#define BCHP_PCIE_0_RC_CFG_TYPE1_STATUS_COMMAND_PERR_ENA_DEFAULT 0x00000000
-
-/* PCIE_0_RC_CFG_TYPE1 :: STATUS_COMMAND :: VGA_SNOOP [05:05] */
-#define BCHP_PCIE_0_RC_CFG_TYPE1_STATUS_COMMAND_VGA_SNOOP_MASK 0x00000020
-#define BCHP_PCIE_0_RC_CFG_TYPE1_STATUS_COMMAND_VGA_SNOOP_SHIFT 5
-#define BCHP_PCIE_0_RC_CFG_TYPE1_STATUS_COMMAND_VGA_SNOOP_DEFAULT 0x00000000
-
-/* PCIE_0_RC_CFG_TYPE1 :: STATUS_COMMAND :: MWI_CYCLES [04:04] */
-#define BCHP_PCIE_0_RC_CFG_TYPE1_STATUS_COMMAND_MWI_CYCLES_MASK 0x00000010
-#define BCHP_PCIE_0_RC_CFG_TYPE1_STATUS_COMMAND_MWI_CYCLES_SHIFT 4
-#define BCHP_PCIE_0_RC_CFG_TYPE1_STATUS_COMMAND_MWI_CYCLES_DEFAULT 0x00000000
-
-/* PCIE_0_RC_CFG_TYPE1 :: STATUS_COMMAND :: SPECIAL_CYCLES [03:03] */
-#define BCHP_PCIE_0_RC_CFG_TYPE1_STATUS_COMMAND_SPECIAL_CYCLES_MASK 0x00000008
-#define BCHP_PCIE_0_RC_CFG_TYPE1_STATUS_COMMAND_SPECIAL_CYCLES_SHIFT 3
-#define BCHP_PCIE_0_RC_CFG_TYPE1_STATUS_COMMAND_SPECIAL_CYCLES_DEFAULT 0x00000000
-
-/* PCIE_0_RC_CFG_TYPE1 :: STATUS_COMMAND :: BUS_MASTER [02:02] */
-#define BCHP_PCIE_0_RC_CFG_TYPE1_STATUS_COMMAND_BUS_MASTER_MASK 0x00000004
-#define BCHP_PCIE_0_RC_CFG_TYPE1_STATUS_COMMAND_BUS_MASTER_SHIFT 2
-#define BCHP_PCIE_0_RC_CFG_TYPE1_STATUS_COMMAND_BUS_MASTER_DEFAULT 0x00000000
-
-/* PCIE_0_RC_CFG_TYPE1 :: STATUS_COMMAND :: MEM_SPACE [01:01] */
-#define BCHP_PCIE_0_RC_CFG_TYPE1_STATUS_COMMAND_MEM_SPACE_MASK 0x00000002
-#define BCHP_PCIE_0_RC_CFG_TYPE1_STATUS_COMMAND_MEM_SPACE_SHIFT 1
-#define BCHP_PCIE_0_RC_CFG_TYPE1_STATUS_COMMAND_MEM_SPACE_DEFAULT 0x00000000
-
-/* PCIE_0_RC_CFG_TYPE1 :: STATUS_COMMAND :: IO_SPACE [00:00] */
-#define BCHP_PCIE_0_RC_CFG_TYPE1_STATUS_COMMAND_IO_SPACE_MASK 0x00000001
-#define BCHP_PCIE_0_RC_CFG_TYPE1_STATUS_COMMAND_IO_SPACE_SHIFT 0
-#define BCHP_PCIE_0_RC_CFG_TYPE1_STATUS_COMMAND_IO_SPACE_DEFAULT 0x00000000
-
-/***************************************************************************
- *REV_ID_CLASS_CODE - rev_id_class_code
- ***************************************************************************/
-/* PCIE_0_RC_CFG_TYPE1 :: REV_ID_CLASS_CODE :: CLASS_CODE [31:08] */
-#define BCHP_PCIE_0_RC_CFG_TYPE1_REV_ID_CLASS_CODE_CLASS_CODE_MASK 0xffffff00
-#define BCHP_PCIE_0_RC_CFG_TYPE1_REV_ID_CLASS_CODE_CLASS_CODE_SHIFT 8
-#define BCHP_PCIE_0_RC_CFG_TYPE1_REV_ID_CLASS_CODE_CLASS_CODE_DEFAULT 0x00020000
-
-/* PCIE_0_RC_CFG_TYPE1 :: REV_ID_CLASS_CODE :: REV_ID [07:00] */
-#define BCHP_PCIE_0_RC_CFG_TYPE1_REV_ID_CLASS_CODE_REV_ID_MASK 0x000000ff
-#define BCHP_PCIE_0_RC_CFG_TYPE1_REV_ID_CLASS_CODE_REV_ID_SHIFT 0
-
-/***************************************************************************
- *HEADERTYPE_LAT_CACHELINESIZE - headertype_lat_cachelinesize
- ***************************************************************************/
-/* PCIE_0_RC_CFG_TYPE1 :: HEADERTYPE_LAT_CACHELINESIZE :: BIST [31:24] */
-#define BCHP_PCIE_0_RC_CFG_TYPE1_HEADERTYPE_LAT_CACHELINESIZE_BIST_MASK 0xff000000
-#define BCHP_PCIE_0_RC_CFG_TYPE1_HEADERTYPE_LAT_CACHELINESIZE_BIST_SHIFT 24
-#define BCHP_PCIE_0_RC_CFG_TYPE1_HEADERTYPE_LAT_CACHELINESIZE_BIST_DEFAULT 0x00000000
-
-/* PCIE_0_RC_CFG_TYPE1 :: HEADERTYPE_LAT_CACHELINESIZE :: HEADER_TYPE [23:16] */
-#define BCHP_PCIE_0_RC_CFG_TYPE1_HEADERTYPE_LAT_CACHELINESIZE_HEADER_TYPE_MASK 0x00ff0000
-#define BCHP_PCIE_0_RC_CFG_TYPE1_HEADERTYPE_LAT_CACHELINESIZE_HEADER_TYPE_SHIFT 16
-#define BCHP_PCIE_0_RC_CFG_TYPE1_HEADERTYPE_LAT_CACHELINESIZE_HEADER_TYPE_DEFAULT 0x00000001
-
-/* PCIE_0_RC_CFG_TYPE1 :: HEADERTYPE_LAT_CACHELINESIZE :: LATENCY_TIMER [15:08] */
-#define BCHP_PCIE_0_RC_CFG_TYPE1_HEADERTYPE_LAT_CACHELINESIZE_LATENCY_TIMER_MASK 0x0000ff00
-#define BCHP_PCIE_0_RC_CFG_TYPE1_HEADERTYPE_LAT_CACHELINESIZE_LATENCY_TIMER_SHIFT 8
-#define BCHP_PCIE_0_RC_CFG_TYPE1_HEADERTYPE_LAT_CACHELINESIZE_LATENCY_TIMER_DEFAULT 0x00000000
-
-/* PCIE_0_RC_CFG_TYPE1 :: HEADERTYPE_LAT_CACHELINESIZE :: CACHE_LINE_SIZE [07:00] */
-#define BCHP_PCIE_0_RC_CFG_TYPE1_HEADERTYPE_LAT_CACHELINESIZE_CACHE_LINE_SIZE_MASK 0x000000ff
-#define BCHP_PCIE_0_RC_CFG_TYPE1_HEADERTYPE_LAT_CACHELINESIZE_CACHE_LINE_SIZE_SHIFT 0
-#define BCHP_PCIE_0_RC_CFG_TYPE1_HEADERTYPE_LAT_CACHELINESIZE_CACHE_LINE_SIZE_DEFAULT 0x00000000
-
-/***************************************************************************
- *BAR_1 - bar_1
- ***************************************************************************/
-/* PCIE_0_RC_CFG_TYPE1 :: BAR_1 :: ADDRESS [31:04] */
-#define BCHP_PCIE_0_RC_CFG_TYPE1_BAR_1_ADDRESS_MASK 0xfffffff0
-#define BCHP_PCIE_0_RC_CFG_TYPE1_BAR_1_ADDRESS_SHIFT 4
-#define BCHP_PCIE_0_RC_CFG_TYPE1_BAR_1_ADDRESS_DEFAULT 0x00000000
-
-/* PCIE_0_RC_CFG_TYPE1 :: BAR_1 :: PREFETCH [03:03] */
-#define BCHP_PCIE_0_RC_CFG_TYPE1_BAR_1_PREFETCH_MASK 0x00000008
-#define BCHP_PCIE_0_RC_CFG_TYPE1_BAR_1_PREFETCH_SHIFT 3
-#define BCHP_PCIE_0_RC_CFG_TYPE1_BAR_1_PREFETCH_DEFAULT 0x00000001
-
-/* PCIE_0_RC_CFG_TYPE1 :: BAR_1 :: SPACE_TYPE [02:01] */
-#define BCHP_PCIE_0_RC_CFG_TYPE1_BAR_1_SPACE_TYPE_MASK 0x00000006
-#define BCHP_PCIE_0_RC_CFG_TYPE1_BAR_1_SPACE_TYPE_SHIFT 1
-#define BCHP_PCIE_0_RC_CFG_TYPE1_BAR_1_SPACE_TYPE_DEFAULT 0x00000002
-
-/* PCIE_0_RC_CFG_TYPE1 :: BAR_1 :: MEM_SPACE [00:00] */
-#define BCHP_PCIE_0_RC_CFG_TYPE1_BAR_1_MEM_SPACE_MASK 0x00000001
-#define BCHP_PCIE_0_RC_CFG_TYPE1_BAR_1_MEM_SPACE_SHIFT 0
-#define BCHP_PCIE_0_RC_CFG_TYPE1_BAR_1_MEM_SPACE_DEFAULT 0x00000000
-
-/***************************************************************************
- *BAR_2 - bar_2
- ***************************************************************************/
-/* PCIE_0_RC_CFG_TYPE1 :: BAR_2 :: ADDR [31:00] */
-#define BCHP_PCIE_0_RC_CFG_TYPE1_BAR_2_ADDR_MASK 0xffffffff
-#define BCHP_PCIE_0_RC_CFG_TYPE1_BAR_2_ADDR_SHIFT 0
-#define BCHP_PCIE_0_RC_CFG_TYPE1_BAR_2_ADDR_DEFAULT 0x00000000
-
-/***************************************************************************
- *PRI_SEC_BUS_NO - pri_sec_bus_no
- ***************************************************************************/
-/* PCIE_0_RC_CFG_TYPE1 :: PRI_SEC_BUS_NO :: SEC_LATENCY_TIMER [31:24] */
-#define BCHP_PCIE_0_RC_CFG_TYPE1_PRI_SEC_BUS_NO_SEC_LATENCY_TIMER_MASK 0xff000000
-#define BCHP_PCIE_0_RC_CFG_TYPE1_PRI_SEC_BUS_NO_SEC_LATENCY_TIMER_SHIFT 24
-#define BCHP_PCIE_0_RC_CFG_TYPE1_PRI_SEC_BUS_NO_SEC_LATENCY_TIMER_DEFAULT 0x00000000
-
-/* PCIE_0_RC_CFG_TYPE1 :: PRI_SEC_BUS_NO :: SUB_BUS_NO [23:16] */
-#define BCHP_PCIE_0_RC_CFG_TYPE1_PRI_SEC_BUS_NO_SUB_BUS_NO_MASK 0x00ff0000
-#define BCHP_PCIE_0_RC_CFG_TYPE1_PRI_SEC_BUS_NO_SUB_BUS_NO_SHIFT 16
-#define BCHP_PCIE_0_RC_CFG_TYPE1_PRI_SEC_BUS_NO_SUB_BUS_NO_DEFAULT 0x00000000
-
-/* PCIE_0_RC_CFG_TYPE1 :: PRI_SEC_BUS_NO :: SEC_BUS_NO [15:08] */
-#define BCHP_PCIE_0_RC_CFG_TYPE1_PRI_SEC_BUS_NO_SEC_BUS_NO_MASK 0x0000ff00
-#define BCHP_PCIE_0_RC_CFG_TYPE1_PRI_SEC_BUS_NO_SEC_BUS_NO_SHIFT 8
-#define BCHP_PCIE_0_RC_CFG_TYPE1_PRI_SEC_BUS_NO_SEC_BUS_NO_DEFAULT 0x00000000
-
-/* PCIE_0_RC_CFG_TYPE1 :: PRI_SEC_BUS_NO :: PRI_BUS_NO [07:00] */
-#define BCHP_PCIE_0_RC_CFG_TYPE1_PRI_SEC_BUS_NO_PRI_BUS_NO_MASK 0x000000ff
-#define BCHP_PCIE_0_RC_CFG_TYPE1_PRI_SEC_BUS_NO_PRI_BUS_NO_SHIFT 0
-#define BCHP_PCIE_0_RC_CFG_TYPE1_PRI_SEC_BUS_NO_PRI_BUS_NO_DEFAULT 0x00000000
-
-/***************************************************************************
- *SEC_STATUS_IO_BASE_LIMIT - sec_status_io_base_limit
- ***************************************************************************/
-/* PCIE_0_RC_CFG_TYPE1 :: SEC_STATUS_IO_BASE_LIMIT :: SEC_DETECTED_PARITY_ERROR [31:31] */
-#define BCHP_PCIE_0_RC_CFG_TYPE1_SEC_STATUS_IO_BASE_LIMIT_SEC_DETECTED_PARITY_ERROR_MASK 0x80000000
-#define BCHP_PCIE_0_RC_CFG_TYPE1_SEC_STATUS_IO_BASE_LIMIT_SEC_DETECTED_PARITY_ERROR_SHIFT 31
-#define BCHP_PCIE_0_RC_CFG_TYPE1_SEC_STATUS_IO_BASE_LIMIT_SEC_DETECTED_PARITY_ERROR_DEFAULT 0x00000000
-
-/* PCIE_0_RC_CFG_TYPE1 :: SEC_STATUS_IO_BASE_LIMIT :: SEC_RECEIVED_SYSTEM_ERROR [30:30] */
-#define BCHP_PCIE_0_RC_CFG_TYPE1_SEC_STATUS_IO_BASE_LIMIT_SEC_RECEIVED_SYSTEM_ERROR_MASK 0x40000000
-#define BCHP_PCIE_0_RC_CFG_TYPE1_SEC_STATUS_IO_BASE_LIMIT_SEC_RECEIVED_SYSTEM_ERROR_SHIFT 30
-#define BCHP_PCIE_0_RC_CFG_TYPE1_SEC_STATUS_IO_BASE_LIMIT_SEC_RECEIVED_SYSTEM_ERROR_DEFAULT 0x00000000
-
-/* PCIE_0_RC_CFG_TYPE1 :: SEC_STATUS_IO_BASE_LIMIT :: SEC_RECEIVED_MASTER_ABORT [29:29] */
-#define BCHP_PCIE_0_RC_CFG_TYPE1_SEC_STATUS_IO_BASE_LIMIT_SEC_RECEIVED_MASTER_ABORT_MASK 0x20000000
-#define BCHP_PCIE_0_RC_CFG_TYPE1_SEC_STATUS_IO_BASE_LIMIT_SEC_RECEIVED_MASTER_ABORT_SHIFT 29
-#define BCHP_PCIE_0_RC_CFG_TYPE1_SEC_STATUS_IO_BASE_LIMIT_SEC_RECEIVED_MASTER_ABORT_DEFAULT 0x00000000
-
-/* PCIE_0_RC_CFG_TYPE1 :: SEC_STATUS_IO_BASE_LIMIT :: SEC_RECEIVED_TARGET_ABORT [28:28] */
-#define BCHP_PCIE_0_RC_CFG_TYPE1_SEC_STATUS_IO_BASE_LIMIT_SEC_RECEIVED_TARGET_ABORT_MASK 0x10000000
-#define BCHP_PCIE_0_RC_CFG_TYPE1_SEC_STATUS_IO_BASE_LIMIT_SEC_RECEIVED_TARGET_ABORT_SHIFT 28
-#define BCHP_PCIE_0_RC_CFG_TYPE1_SEC_STATUS_IO_BASE_LIMIT_SEC_RECEIVED_TARGET_ABORT_DEFAULT 0x00000000
-
-/* PCIE_0_RC_CFG_TYPE1 :: SEC_STATUS_IO_BASE_LIMIT :: SEC_SIGNALED_TARGET_ABORT [27:27] */
-#define BCHP_PCIE_0_RC_CFG_TYPE1_SEC_STATUS_IO_BASE_LIMIT_SEC_SIGNALED_TARGET_ABORT_MASK 0x08000000
-#define BCHP_PCIE_0_RC_CFG_TYPE1_SEC_STATUS_IO_BASE_LIMIT_SEC_SIGNALED_TARGET_ABORT_SHIFT 27
-#define BCHP_PCIE_0_RC_CFG_TYPE1_SEC_STATUS_IO_BASE_LIMIT_SEC_SIGNALED_TARGET_ABORT_DEFAULT 0x00000000
-
-/* PCIE_0_RC_CFG_TYPE1 :: SEC_STATUS_IO_BASE_LIMIT :: DEVICE_TIMING [26:25] */
-#define BCHP_PCIE_0_RC_CFG_TYPE1_SEC_STATUS_IO_BASE_LIMIT_DEVICE_TIMING_MASK 0x06000000
-#define BCHP_PCIE_0_RC_CFG_TYPE1_SEC_STATUS_IO_BASE_LIMIT_DEVICE_TIMING_SHIFT 25
-#define BCHP_PCIE_0_RC_CFG_TYPE1_SEC_STATUS_IO_BASE_LIMIT_DEVICE_TIMING_DEFAULT 0x00000000
-
-/* PCIE_0_RC_CFG_TYPE1 :: SEC_STATUS_IO_BASE_LIMIT :: SEC_MASTER_DATA_PARITY_ERROR [24:24] */
-#define BCHP_PCIE_0_RC_CFG_TYPE1_SEC_STATUS_IO_BASE_LIMIT_SEC_MASTER_DATA_PARITY_ERROR_MASK 0x01000000
-#define BCHP_PCIE_0_RC_CFG_TYPE1_SEC_STATUS_IO_BASE_LIMIT_SEC_MASTER_DATA_PARITY_ERROR_SHIFT 24
-#define BCHP_PCIE_0_RC_CFG_TYPE1_SEC_STATUS_IO_BASE_LIMIT_SEC_MASTER_DATA_PARITY_ERROR_DEFAULT 0x00000000
-
-/* PCIE_0_RC_CFG_TYPE1 :: SEC_STATUS_IO_BASE_LIMIT :: FAST_B2B [23:23] */
-#define BCHP_PCIE_0_RC_CFG_TYPE1_SEC_STATUS_IO_BASE_LIMIT_FAST_B2B_MASK 0x00800000
-#define BCHP_PCIE_0_RC_CFG_TYPE1_SEC_STATUS_IO_BASE_LIMIT_FAST_B2B_SHIFT 23
-#define BCHP_PCIE_0_RC_CFG_TYPE1_SEC_STATUS_IO_BASE_LIMIT_FAST_B2B_DEFAULT 0x00000000
-
-/* PCIE_0_RC_CFG_TYPE1 :: SEC_STATUS_IO_BASE_LIMIT :: RESERVED3 [22:22] */
-#define BCHP_PCIE_0_RC_CFG_TYPE1_SEC_STATUS_IO_BASE_LIMIT_RESERVED3_MASK 0x00400000
-#define BCHP_PCIE_0_RC_CFG_TYPE1_SEC_STATUS_IO_BASE_LIMIT_RESERVED3_SHIFT 22
-#define BCHP_PCIE_0_RC_CFG_TYPE1_SEC_STATUS_IO_BASE_LIMIT_RESERVED3_DEFAULT 0x00000000
-
-/* PCIE_0_RC_CFG_TYPE1 :: SEC_STATUS_IO_BASE_LIMIT :: CAP_66_MHZ [21:21] */
-#define BCHP_PCIE_0_RC_CFG_TYPE1_SEC_STATUS_IO_BASE_LIMIT_CAP_66_MHZ_MASK 0x00200000
-#define BCHP_PCIE_0_RC_CFG_TYPE1_SEC_STATUS_IO_BASE_LIMIT_CAP_66_MHZ_SHIFT 21
-#define BCHP_PCIE_0_RC_CFG_TYPE1_SEC_STATUS_IO_BASE_LIMIT_CAP_66_MHZ_DEFAULT 0x00000000
-
-/* PCIE_0_RC_CFG_TYPE1 :: SEC_STATUS_IO_BASE_LIMIT :: RESERVED4 [20:16] */
-#define BCHP_PCIE_0_RC_CFG_TYPE1_SEC_STATUS_IO_BASE_LIMIT_RESERVED4_MASK 0x001f0000
-#define BCHP_PCIE_0_RC_CFG_TYPE1_SEC_STATUS_IO_BASE_LIMIT_RESERVED4_SHIFT 16
-#define BCHP_PCIE_0_RC_CFG_TYPE1_SEC_STATUS_IO_BASE_LIMIT_RESERVED4_DEFAULT 0x00000000
-
-/* PCIE_0_RC_CFG_TYPE1 :: SEC_STATUS_IO_BASE_LIMIT :: IO_LIMIT [15:08] */
-#define BCHP_PCIE_0_RC_CFG_TYPE1_SEC_STATUS_IO_BASE_LIMIT_IO_LIMIT_MASK 0x0000ff00
-#define BCHP_PCIE_0_RC_CFG_TYPE1_SEC_STATUS_IO_BASE_LIMIT_IO_LIMIT_SHIFT 8
-#define BCHP_PCIE_0_RC_CFG_TYPE1_SEC_STATUS_IO_BASE_LIMIT_IO_LIMIT_DEFAULT 0x00000000
-
-/* PCIE_0_RC_CFG_TYPE1 :: SEC_STATUS_IO_BASE_LIMIT :: IO_BASE [07:00] */
-#define BCHP_PCIE_0_RC_CFG_TYPE1_SEC_STATUS_IO_BASE_LIMIT_IO_BASE_MASK 0x000000ff
-#define BCHP_PCIE_0_RC_CFG_TYPE1_SEC_STATUS_IO_BASE_LIMIT_IO_BASE_SHIFT 0
-#define BCHP_PCIE_0_RC_CFG_TYPE1_SEC_STATUS_IO_BASE_LIMIT_IO_BASE_DEFAULT 0x00000000
-
-/***************************************************************************
- *RC_MEM_BASE_LIMIT - rc_mem_base_limit
- ***************************************************************************/
-/* PCIE_0_RC_CFG_TYPE1 :: RC_MEM_BASE_LIMIT :: RC_MEM_LIMIT [31:20] */
-#define BCHP_PCIE_0_RC_CFG_TYPE1_RC_MEM_BASE_LIMIT_RC_MEM_LIMIT_MASK 0xfff00000
-#define BCHP_PCIE_0_RC_CFG_TYPE1_RC_MEM_BASE_LIMIT_RC_MEM_LIMIT_SHIFT 20
-#define BCHP_PCIE_0_RC_CFG_TYPE1_RC_MEM_BASE_LIMIT_RC_MEM_LIMIT_DEFAULT 0x00000000
-
-/* PCIE_0_RC_CFG_TYPE1 :: RC_MEM_BASE_LIMIT :: RC_MEM_LIMIT_3TO0 [19:16] */
-#define BCHP_PCIE_0_RC_CFG_TYPE1_RC_MEM_BASE_LIMIT_RC_MEM_LIMIT_3TO0_MASK 0x000f0000
-#define BCHP_PCIE_0_RC_CFG_TYPE1_RC_MEM_BASE_LIMIT_RC_MEM_LIMIT_3TO0_SHIFT 16
-#define BCHP_PCIE_0_RC_CFG_TYPE1_RC_MEM_BASE_LIMIT_RC_MEM_LIMIT_3TO0_DEFAULT 0x00000000
-
-/* PCIE_0_RC_CFG_TYPE1 :: RC_MEM_BASE_LIMIT :: RC_MEM_BASE [15:04] */
-#define BCHP_PCIE_0_RC_CFG_TYPE1_RC_MEM_BASE_LIMIT_RC_MEM_BASE_MASK 0x0000fff0
-#define BCHP_PCIE_0_RC_CFG_TYPE1_RC_MEM_BASE_LIMIT_RC_MEM_BASE_SHIFT 4
-#define BCHP_PCIE_0_RC_CFG_TYPE1_RC_MEM_BASE_LIMIT_RC_MEM_BASE_DEFAULT 0x00000000
-
-/* PCIE_0_RC_CFG_TYPE1 :: RC_MEM_BASE_LIMIT :: RC_MEM_BASE_3TO0 [03:00] */
-#define BCHP_PCIE_0_RC_CFG_TYPE1_RC_MEM_BASE_LIMIT_RC_MEM_BASE_3TO0_MASK 0x0000000f
-#define BCHP_PCIE_0_RC_CFG_TYPE1_RC_MEM_BASE_LIMIT_RC_MEM_BASE_3TO0_SHIFT 0
-#define BCHP_PCIE_0_RC_CFG_TYPE1_RC_MEM_BASE_LIMIT_RC_MEM_BASE_3TO0_DEFAULT 0x00000000
-
-/***************************************************************************
- *RC_PREF_BASE_LIMIT - rc_pref_base_limit
- ***************************************************************************/
-/* PCIE_0_RC_CFG_TYPE1 :: RC_PREF_BASE_LIMIT :: RC_PREF_LIM [31:20] */
-#define BCHP_PCIE_0_RC_CFG_TYPE1_RC_PREF_BASE_LIMIT_RC_PREF_LIM_MASK 0xfff00000
-#define BCHP_PCIE_0_RC_CFG_TYPE1_RC_PREF_BASE_LIMIT_RC_PREF_LIM_SHIFT 20
-#define BCHP_PCIE_0_RC_CFG_TYPE1_RC_PREF_BASE_LIMIT_RC_PREF_LIM_DEFAULT 0x00000000
-
-/* PCIE_0_RC_CFG_TYPE1 :: RC_PREF_BASE_LIMIT :: RC_PREF_LIMIT_3TO0 [19:16] */
-#define BCHP_PCIE_0_RC_CFG_TYPE1_RC_PREF_BASE_LIMIT_RC_PREF_LIMIT_3TO0_MASK 0x000f0000
-#define BCHP_PCIE_0_RC_CFG_TYPE1_RC_PREF_BASE_LIMIT_RC_PREF_LIMIT_3TO0_SHIFT 16
-#define BCHP_PCIE_0_RC_CFG_TYPE1_RC_PREF_BASE_LIMIT_RC_PREF_LIMIT_3TO0_DEFAULT 0x00000001
-
-/* PCIE_0_RC_CFG_TYPE1 :: RC_PREF_BASE_LIMIT :: RC_PREF_BASE [15:04] */
-#define BCHP_PCIE_0_RC_CFG_TYPE1_RC_PREF_BASE_LIMIT_RC_PREF_BASE_MASK 0x0000fff0
-#define BCHP_PCIE_0_RC_CFG_TYPE1_RC_PREF_BASE_LIMIT_RC_PREF_BASE_SHIFT 4
-#define BCHP_PCIE_0_RC_CFG_TYPE1_RC_PREF_BASE_LIMIT_RC_PREF_BASE_DEFAULT 0x00000000
-
-/* PCIE_0_RC_CFG_TYPE1 :: RC_PREF_BASE_LIMIT :: RC_PREF_BASE_3TO0 [03:00] */
-#define BCHP_PCIE_0_RC_CFG_TYPE1_RC_PREF_BASE_LIMIT_RC_PREF_BASE_3TO0_MASK 0x0000000f
-#define BCHP_PCIE_0_RC_CFG_TYPE1_RC_PREF_BASE_LIMIT_RC_PREF_BASE_3TO0_SHIFT 0
-#define BCHP_PCIE_0_RC_CFG_TYPE1_RC_PREF_BASE_LIMIT_RC_PREF_BASE_3TO0_DEFAULT 0x00000001
-
-/***************************************************************************
- *RC_PREF_BASE_HI - rc_pref_base_hi
- ***************************************************************************/
-/* PCIE_0_RC_CFG_TYPE1 :: RC_PREF_BASE_HI :: RC_PREF_BASE_HI [31:00] */
-#define BCHP_PCIE_0_RC_CFG_TYPE1_RC_PREF_BASE_HI_RC_PREF_BASE_HI_MASK 0xffffffff
-#define BCHP_PCIE_0_RC_CFG_TYPE1_RC_PREF_BASE_HI_RC_PREF_BASE_HI_SHIFT 0
-#define BCHP_PCIE_0_RC_CFG_TYPE1_RC_PREF_BASE_HI_RC_PREF_BASE_HI_DEFAULT 0x00000000
-
-/***************************************************************************
- *RC_PREF_LIM_HI - rc_pref_lim_hi
- ***************************************************************************/
-/* PCIE_0_RC_CFG_TYPE1 :: RC_PREF_LIM_HI :: RC_PREF_BASE_HI [31:00] */
-#define BCHP_PCIE_0_RC_CFG_TYPE1_RC_PREF_LIM_HI_RC_PREF_BASE_HI_MASK 0xffffffff
-#define BCHP_PCIE_0_RC_CFG_TYPE1_RC_PREF_LIM_HI_RC_PREF_BASE_HI_SHIFT 0
-#define BCHP_PCIE_0_RC_CFG_TYPE1_RC_PREF_LIM_HI_RC_PREF_BASE_HI_DEFAULT 0x00000000
-
-/***************************************************************************
- *RC_IO_BASE_LIMIT - rc_io_base_limit
- ***************************************************************************/
-/* PCIE_0_RC_CFG_TYPE1 :: RC_IO_BASE_LIMIT :: RC_IO_LIM_HI [31:16] */
-#define BCHP_PCIE_0_RC_CFG_TYPE1_RC_IO_BASE_LIMIT_RC_IO_LIM_HI_MASK 0xffff0000
-#define BCHP_PCIE_0_RC_CFG_TYPE1_RC_IO_BASE_LIMIT_RC_IO_LIM_HI_SHIFT 16
-#define BCHP_PCIE_0_RC_CFG_TYPE1_RC_IO_BASE_LIMIT_RC_IO_LIM_HI_DEFAULT 0x00000000
-
-/* PCIE_0_RC_CFG_TYPE1 :: RC_IO_BASE_LIMIT :: RC_IO_BASE_HI [15:00] */
-#define BCHP_PCIE_0_RC_CFG_TYPE1_RC_IO_BASE_LIMIT_RC_IO_BASE_HI_MASK 0x0000ffff
-#define BCHP_PCIE_0_RC_CFG_TYPE1_RC_IO_BASE_LIMIT_RC_IO_BASE_HI_SHIFT 0
-#define BCHP_PCIE_0_RC_CFG_TYPE1_RC_IO_BASE_LIMIT_RC_IO_BASE_HI_DEFAULT 0x00000000
-
-/***************************************************************************
- *CAP_POINTER - cap_pointer
- ***************************************************************************/
-/* PCIE_0_RC_CFG_TYPE1 :: CAP_POINTER :: RESERVED0 [31:08] */
-#define BCHP_PCIE_0_RC_CFG_TYPE1_CAP_POINTER_RESERVED0_MASK 0xffffff00
-#define BCHP_PCIE_0_RC_CFG_TYPE1_CAP_POINTER_RESERVED0_SHIFT 8
-
-/* PCIE_0_RC_CFG_TYPE1 :: CAP_POINTER :: CAP_POINTER [07:00] */
-#define BCHP_PCIE_0_RC_CFG_TYPE1_CAP_POINTER_CAP_POINTER_MASK 0x000000ff
-#define BCHP_PCIE_0_RC_CFG_TYPE1_CAP_POINTER_CAP_POINTER_SHIFT 0
-#define BCHP_PCIE_0_RC_CFG_TYPE1_CAP_POINTER_CAP_POINTER_DEFAULT 0x00000048
-
-/***************************************************************************
- *EXP_ROM_BAR - exp_rom_bar
- ***************************************************************************/
-/* PCIE_0_RC_CFG_TYPE1 :: EXP_ROM_BAR :: RESERVED0 [31:08] */
-#define BCHP_PCIE_0_RC_CFG_TYPE1_EXP_ROM_BAR_RESERVED0_MASK 0xffffff00
-#define BCHP_PCIE_0_RC_CFG_TYPE1_EXP_ROM_BAR_RESERVED0_SHIFT 8
-
-/* PCIE_0_RC_CFG_TYPE1 :: EXP_ROM_BAR :: EXP_ROM_BAR [07:00] */
-#define BCHP_PCIE_0_RC_CFG_TYPE1_EXP_ROM_BAR_EXP_ROM_BAR_MASK 0x000000ff
-#define BCHP_PCIE_0_RC_CFG_TYPE1_EXP_ROM_BAR_EXP_ROM_BAR_SHIFT 0
-#define BCHP_PCIE_0_RC_CFG_TYPE1_EXP_ROM_BAR_EXP_ROM_BAR_DEFAULT 0x00000000
-
-/***************************************************************************
- *BRIDGE_CONTROL - bridge_control
- ***************************************************************************/
-/* PCIE_0_RC_CFG_TYPE1 :: BRIDGE_CONTROL :: RESERVED1 [31:28] */
-#define BCHP_PCIE_0_RC_CFG_TYPE1_BRIDGE_CONTROL_RESERVED1_MASK 0xf0000000
-#define BCHP_PCIE_0_RC_CFG_TYPE1_BRIDGE_CONTROL_RESERVED1_SHIFT 28
-
-/* PCIE_0_RC_CFG_TYPE1 :: BRIDGE_CONTROL :: DISCARD_TIMER_SERR_EN [27:27] */
-#define BCHP_PCIE_0_RC_CFG_TYPE1_BRIDGE_CONTROL_DISCARD_TIMER_SERR_EN_MASK 0x08000000
-#define BCHP_PCIE_0_RC_CFG_TYPE1_BRIDGE_CONTROL_DISCARD_TIMER_SERR_EN_SHIFT 27
-#define BCHP_PCIE_0_RC_CFG_TYPE1_BRIDGE_CONTROL_DISCARD_TIMER_SERR_EN_DEFAULT 0x00000000
-
-/* PCIE_0_RC_CFG_TYPE1 :: BRIDGE_CONTROL :: DISCARD_TIMER_STATUS [26:26] */
-#define BCHP_PCIE_0_RC_CFG_TYPE1_BRIDGE_CONTROL_DISCARD_TIMER_STATUS_MASK 0x04000000
-#define BCHP_PCIE_0_RC_CFG_TYPE1_BRIDGE_CONTROL_DISCARD_TIMER_STATUS_SHIFT 26
-#define BCHP_PCIE_0_RC_CFG_TYPE1_BRIDGE_CONTROL_DISCARD_TIMER_STATUS_DEFAULT 0x00000000
-
-/* PCIE_0_RC_CFG_TYPE1 :: BRIDGE_CONTROL :: SEC_DISCARD_TIMER [25:25] */
-#define BCHP_PCIE_0_RC_CFG_TYPE1_BRIDGE_CONTROL_SEC_DISCARD_TIMER_MASK 0x02000000
-#define BCHP_PCIE_0_RC_CFG_TYPE1_BRIDGE_CONTROL_SEC_DISCARD_TIMER_SHIFT 25
-#define BCHP_PCIE_0_RC_CFG_TYPE1_BRIDGE_CONTROL_SEC_DISCARD_TIMER_DEFAULT 0x00000000
-
-/* PCIE_0_RC_CFG_TYPE1 :: BRIDGE_CONTROL :: PRIM_DISCARD_TIMER [24:24] */
-#define BCHP_PCIE_0_RC_CFG_TYPE1_BRIDGE_CONTROL_PRIM_DISCARD_TIMER_MASK 0x01000000
-#define BCHP_PCIE_0_RC_CFG_TYPE1_BRIDGE_CONTROL_PRIM_DISCARD_TIMER_SHIFT 24
-#define BCHP_PCIE_0_RC_CFG_TYPE1_BRIDGE_CONTROL_PRIM_DISCARD_TIMER_DEFAULT 0x00000000
-
-/* PCIE_0_RC_CFG_TYPE1 :: BRIDGE_CONTROL :: FAST_B2B_EN [23:23] */
-#define BCHP_PCIE_0_RC_CFG_TYPE1_BRIDGE_CONTROL_FAST_B2B_EN_MASK 0x00800000
-#define BCHP_PCIE_0_RC_CFG_TYPE1_BRIDGE_CONTROL_FAST_B2B_EN_SHIFT 23
-#define BCHP_PCIE_0_RC_CFG_TYPE1_BRIDGE_CONTROL_FAST_B2B_EN_DEFAULT 0x00000000
-
-/* PCIE_0_RC_CFG_TYPE1 :: BRIDGE_CONTROL :: SEC_BUS_RESET [22:22] */
-#define BCHP_PCIE_0_RC_CFG_TYPE1_BRIDGE_CONTROL_SEC_BUS_RESET_MASK 0x00400000
-#define BCHP_PCIE_0_RC_CFG_TYPE1_BRIDGE_CONTROL_SEC_BUS_RESET_SHIFT 22
-#define BCHP_PCIE_0_RC_CFG_TYPE1_BRIDGE_CONTROL_SEC_BUS_RESET_DEFAULT 0x00000000
-
-/* PCIE_0_RC_CFG_TYPE1 :: BRIDGE_CONTROL :: MASTER_ABORT_MODE [21:21] */
-#define BCHP_PCIE_0_RC_CFG_TYPE1_BRIDGE_CONTROL_MASTER_ABORT_MODE_MASK 0x00200000
-#define BCHP_PCIE_0_RC_CFG_TYPE1_BRIDGE_CONTROL_MASTER_ABORT_MODE_SHIFT 21
-#define BCHP_PCIE_0_RC_CFG_TYPE1_BRIDGE_CONTROL_MASTER_ABORT_MODE_DEFAULT 0x00000000
-
-/* PCIE_0_RC_CFG_TYPE1 :: BRIDGE_CONTROL :: RESERVED0 [20:18] */
-#define BCHP_PCIE_0_RC_CFG_TYPE1_BRIDGE_CONTROL_RESERVED0_MASK 0x001c0000
-#define BCHP_PCIE_0_RC_CFG_TYPE1_BRIDGE_CONTROL_RESERVED0_SHIFT 18
-
-/* PCIE_0_RC_CFG_TYPE1 :: BRIDGE_CONTROL :: SEC_SERR_EN [17:17] */
-#define BCHP_PCIE_0_RC_CFG_TYPE1_BRIDGE_CONTROL_SEC_SERR_EN_MASK 0x00020000
-#define BCHP_PCIE_0_RC_CFG_TYPE1_BRIDGE_CONTROL_SEC_SERR_EN_SHIFT 17
-#define BCHP_PCIE_0_RC_CFG_TYPE1_BRIDGE_CONTROL_SEC_SERR_EN_DEFAULT 0x00000000
-
-/* PCIE_0_RC_CFG_TYPE1 :: BRIDGE_CONTROL :: SEC_PERR_RESP_EN [16:16] */
-#define BCHP_PCIE_0_RC_CFG_TYPE1_BRIDGE_CONTROL_SEC_PERR_RESP_EN_MASK 0x00010000
-#define BCHP_PCIE_0_RC_CFG_TYPE1_BRIDGE_CONTROL_SEC_PERR_RESP_EN_SHIFT 16
-#define BCHP_PCIE_0_RC_CFG_TYPE1_BRIDGE_CONTROL_SEC_PERR_RESP_EN_DEFAULT 0x00000000
-
-/* PCIE_0_RC_CFG_TYPE1 :: BRIDGE_CONTROL :: INT_PIN [15:08] */
-#define BCHP_PCIE_0_RC_CFG_TYPE1_BRIDGE_CONTROL_INT_PIN_MASK 0x0000ff00
-#define BCHP_PCIE_0_RC_CFG_TYPE1_BRIDGE_CONTROL_INT_PIN_SHIFT 8
-#define BCHP_PCIE_0_RC_CFG_TYPE1_BRIDGE_CONTROL_INT_PIN_DEFAULT 0x00000001
-
-/* PCIE_0_RC_CFG_TYPE1 :: BRIDGE_CONTROL :: INT_LINE [07:00] */
-#define BCHP_PCIE_0_RC_CFG_TYPE1_BRIDGE_CONTROL_INT_LINE_MASK 0x000000ff
-#define BCHP_PCIE_0_RC_CFG_TYPE1_BRIDGE_CONTROL_INT_LINE_SHIFT 0
-#define BCHP_PCIE_0_RC_CFG_TYPE1_BRIDGE_CONTROL_INT_LINE_DEFAULT 0x00000000
-
-#endif /* #ifndef BCHP_PCIE_0_RC_CFG_TYPE1_H__ */
-
-/* End of File */
diff --git a/include/linux/brcmstb/7145a0/bchp_pcie_0_rc_cfg_vendor.h b/include/linux/brcmstb/7145a0/bchp_pcie_0_rc_cfg_vendor.h
deleted file mode 100644
index 5baf48d..0000000
--- a/include/linux/brcmstb/7145a0/bchp_pcie_0_rc_cfg_vendor.h
+++ /dev/null
@@ -1,173 +0,0 @@
-/***************************************************************************
- * Copyright (c) 1999-2013, Broadcom Corporation
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
- *
- * Module Description:
- * DO NOT EDIT THIS FILE DIRECTLY
- *
- * This module was generated magically with RDB from a source description
- * file. You must edit the source file for changes to be made to this file.
- *
- *
- * Date: Generated on Sat Apr 6 03:07:45 2013
- * MD5 Checksum d41d8cd98f00b204e9800998ecf8427e
- *
- * Compiled with: RDB Utility combo_header.pl
- * RDB Parser 3.0
- * unknown unknown
- * Perl Interpreter 5.008008
- * Operating System linux
- *
- * Revision History:
- *
- * $brcm_Log: $
- *
- ***************************************************************************/
-
-#ifndef BCHP_PCIE_0_RC_CFG_VENDOR_H__
-#define BCHP_PCIE_0_RC_CFG_VENDOR_H__
-
-/***************************************************************************
- *PCIE_0_RC_CFG_VENDOR
- ***************************************************************************/
-#define BCHP_PCIE_0_RC_CFG_VENDOR_VENDOR_CAP 0x07800180 /* vendor_cap */
-#define BCHP_PCIE_0_RC_CFG_VENDOR_VENDOR_SPECIFIC_HEADER 0x07800184 /* vendor_specific_header */
-#define BCHP_PCIE_0_RC_CFG_VENDOR_VENDOR_SPECIFIC_REG1 0x07800188 /* Vendor Specific User Register 1 */
-#define BCHP_PCIE_0_RC_CFG_VENDOR_VENDOR_SPECIFIC_REG2 0x0780018c /* Vendor Specific User Register 2 */
-#define BCHP_PCIE_0_RC_CFG_VENDOR_VENDOR_SPECIFIC_REG3 0x07800190 /* Vendor Specific User Register 3 */
-#define BCHP_PCIE_0_RC_CFG_VENDOR_VENDOR_SPECIFIC_REG4 0x07800194 /* Vendor Specific User Register 4 */
-#define BCHP_PCIE_0_RC_CFG_VENDOR_VENDOR_SPECIFIC_REG5 0x07800198 /* Vendor Specific User Register 5 */
-#define BCHP_PCIE_0_RC_CFG_VENDOR_VENDOR_SPECIFIC_REG6 0x0780019c /* Vendor Specific User Register 6 */
-#define BCHP_PCIE_0_RC_CFG_VENDOR_VENDOR_SPECIFIC_REG7 0x078001a0 /* Vendor Specific User Register 7 */
-#define BCHP_PCIE_0_RC_CFG_VENDOR_VENDOR_SPECIFIC_REG8 0x078001a4 /* Vendor Specific User Register 8 */
-
-/***************************************************************************
- *VENDOR_CAP - vendor_cap
- ***************************************************************************/
-/* PCIE_0_RC_CFG_VENDOR :: VENDOR_CAP :: NEXT [31:20] */
-#define BCHP_PCIE_0_RC_CFG_VENDOR_VENDOR_CAP_NEXT_MASK 0xfff00000
-#define BCHP_PCIE_0_RC_CFG_VENDOR_VENDOR_CAP_NEXT_SHIFT 20
-#define BCHP_PCIE_0_RC_CFG_VENDOR_VENDOR_CAP_NEXT_DEFAULT 0x00000000
-
-/* PCIE_0_RC_CFG_VENDOR :: VENDOR_CAP :: CAP_VER [19:16] */
-#define BCHP_PCIE_0_RC_CFG_VENDOR_VENDOR_CAP_CAP_VER_MASK 0x000f0000
-#define BCHP_PCIE_0_RC_CFG_VENDOR_VENDOR_CAP_CAP_VER_SHIFT 16
-#define BCHP_PCIE_0_RC_CFG_VENDOR_VENDOR_CAP_CAP_VER_DEFAULT 0x00000001
-
-/* PCIE_0_RC_CFG_VENDOR :: VENDOR_CAP :: VENDOR_SPEC_CAP_ID [15:00] */
-#define BCHP_PCIE_0_RC_CFG_VENDOR_VENDOR_CAP_VENDOR_SPEC_CAP_ID_MASK 0x0000ffff
-#define BCHP_PCIE_0_RC_CFG_VENDOR_VENDOR_CAP_VENDOR_SPEC_CAP_ID_SHIFT 0
-#define BCHP_PCIE_0_RC_CFG_VENDOR_VENDOR_CAP_VENDOR_SPEC_CAP_ID_DEFAULT 0x0000000b
-
-/***************************************************************************
- *VENDOR_SPECIFIC_HEADER - vendor_specific_header
- ***************************************************************************/
-/* PCIE_0_RC_CFG_VENDOR :: VENDOR_SPECIFIC_HEADER :: VSEC_LENGTH [31:20] */
-#define BCHP_PCIE_0_RC_CFG_VENDOR_VENDOR_SPECIFIC_HEADER_VSEC_LENGTH_MASK 0xfff00000
-#define BCHP_PCIE_0_RC_CFG_VENDOR_VENDOR_SPECIFIC_HEADER_VSEC_LENGTH_SHIFT 20
-#define BCHP_PCIE_0_RC_CFG_VENDOR_VENDOR_SPECIFIC_HEADER_VSEC_LENGTH_DEFAULT 0x00000028
-
-/* PCIE_0_RC_CFG_VENDOR :: VENDOR_SPECIFIC_HEADER :: VSEC_REV [19:16] */
-#define BCHP_PCIE_0_RC_CFG_VENDOR_VENDOR_SPECIFIC_HEADER_VSEC_REV_MASK 0x000f0000
-#define BCHP_PCIE_0_RC_CFG_VENDOR_VENDOR_SPECIFIC_HEADER_VSEC_REV_SHIFT 16
-#define BCHP_PCIE_0_RC_CFG_VENDOR_VENDOR_SPECIFIC_HEADER_VSEC_REV_DEFAULT 0x00000000
-
-/* PCIE_0_RC_CFG_VENDOR :: VENDOR_SPECIFIC_HEADER :: VSEC_ID [15:00] */
-#define BCHP_PCIE_0_RC_CFG_VENDOR_VENDOR_SPECIFIC_HEADER_VSEC_ID_MASK 0x0000ffff
-#define BCHP_PCIE_0_RC_CFG_VENDOR_VENDOR_SPECIFIC_HEADER_VSEC_ID_SHIFT 0
-#define BCHP_PCIE_0_RC_CFG_VENDOR_VENDOR_SPECIFIC_HEADER_VSEC_ID_DEFAULT 0x00000000
-
-/***************************************************************************
- *VENDOR_SPECIFIC_REG1 - Vendor Specific User Register 1
- ***************************************************************************/
-/* PCIE_0_RC_CFG_VENDOR :: VENDOR_SPECIFIC_REG1 :: Undefined [31:06] */
-#define BCHP_PCIE_0_RC_CFG_VENDOR_VENDOR_SPECIFIC_REG1_Undefined_MASK 0xffffffc0
-#define BCHP_PCIE_0_RC_CFG_VENDOR_VENDOR_SPECIFIC_REG1_Undefined_SHIFT 6
-#define BCHP_PCIE_0_RC_CFG_VENDOR_VENDOR_SPECIFIC_REG1_Undefined_DEFAULT 0x00000000
-
-/* PCIE_0_RC_CFG_VENDOR :: VENDOR_SPECIFIC_REG1 :: ENDIAN_MODE_BAR3 [05:04] */
-#define BCHP_PCIE_0_RC_CFG_VENDOR_VENDOR_SPECIFIC_REG1_ENDIAN_MODE_BAR3_MASK 0x00000030
-#define BCHP_PCIE_0_RC_CFG_VENDOR_VENDOR_SPECIFIC_REG1_ENDIAN_MODE_BAR3_SHIFT 4
-#define BCHP_PCIE_0_RC_CFG_VENDOR_VENDOR_SPECIFIC_REG1_ENDIAN_MODE_BAR3_DEFAULT 0x00000000
-
-/* PCIE_0_RC_CFG_VENDOR :: VENDOR_SPECIFIC_REG1 :: ENDIAN_MODE_BAR2 [03:02] */
-#define BCHP_PCIE_0_RC_CFG_VENDOR_VENDOR_SPECIFIC_REG1_ENDIAN_MODE_BAR2_MASK 0x0000000c
-#define BCHP_PCIE_0_RC_CFG_VENDOR_VENDOR_SPECIFIC_REG1_ENDIAN_MODE_BAR2_SHIFT 2
-#define BCHP_PCIE_0_RC_CFG_VENDOR_VENDOR_SPECIFIC_REG1_ENDIAN_MODE_BAR2_DEFAULT 0x00000000
-
-/* PCIE_0_RC_CFG_VENDOR :: VENDOR_SPECIFIC_REG1 :: ENDIAN_MODE_BAR1 [01:00] */
-#define BCHP_PCIE_0_RC_CFG_VENDOR_VENDOR_SPECIFIC_REG1_ENDIAN_MODE_BAR1_MASK 0x00000003
-#define BCHP_PCIE_0_RC_CFG_VENDOR_VENDOR_SPECIFIC_REG1_ENDIAN_MODE_BAR1_SHIFT 0
-#define BCHP_PCIE_0_RC_CFG_VENDOR_VENDOR_SPECIFIC_REG1_ENDIAN_MODE_BAR1_DEFAULT 0x00000000
-
-/***************************************************************************
- *VENDOR_SPECIFIC_REG2 - Vendor Specific User Register 2
- ***************************************************************************/
-/* PCIE_0_RC_CFG_VENDOR :: VENDOR_SPECIFIC_REG2 :: Undefined [31:00] */
-#define BCHP_PCIE_0_RC_CFG_VENDOR_VENDOR_SPECIFIC_REG2_Undefined_MASK 0xffffffff
-#define BCHP_PCIE_0_RC_CFG_VENDOR_VENDOR_SPECIFIC_REG2_Undefined_SHIFT 0
-#define BCHP_PCIE_0_RC_CFG_VENDOR_VENDOR_SPECIFIC_REG2_Undefined_DEFAULT 0x00000000
-
-/***************************************************************************
- *VENDOR_SPECIFIC_REG3 - Vendor Specific User Register 3
- ***************************************************************************/
-/* PCIE_0_RC_CFG_VENDOR :: VENDOR_SPECIFIC_REG3 :: Undefined [31:00] */
-#define BCHP_PCIE_0_RC_CFG_VENDOR_VENDOR_SPECIFIC_REG3_Undefined_MASK 0xffffffff
-#define BCHP_PCIE_0_RC_CFG_VENDOR_VENDOR_SPECIFIC_REG3_Undefined_SHIFT 0
-#define BCHP_PCIE_0_RC_CFG_VENDOR_VENDOR_SPECIFIC_REG3_Undefined_DEFAULT 0x00000000
-
-/***************************************************************************
- *VENDOR_SPECIFIC_REG4 - Vendor Specific User Register 4
- ***************************************************************************/
-/* PCIE_0_RC_CFG_VENDOR :: VENDOR_SPECIFIC_REG4 :: Undefined [31:00] */
-#define BCHP_PCIE_0_RC_CFG_VENDOR_VENDOR_SPECIFIC_REG4_Undefined_MASK 0xffffffff
-#define BCHP_PCIE_0_RC_CFG_VENDOR_VENDOR_SPECIFIC_REG4_Undefined_SHIFT 0
-#define BCHP_PCIE_0_RC_CFG_VENDOR_VENDOR_SPECIFIC_REG4_Undefined_DEFAULT 0x00000000
-
-/***************************************************************************
- *VENDOR_SPECIFIC_REG5 - Vendor Specific User Register 5
- ***************************************************************************/
-/* PCIE_0_RC_CFG_VENDOR :: VENDOR_SPECIFIC_REG5 :: Undefined [31:00] */
-#define BCHP_PCIE_0_RC_CFG_VENDOR_VENDOR_SPECIFIC_REG5_Undefined_MASK 0xffffffff
-#define BCHP_PCIE_0_RC_CFG_VENDOR_VENDOR_SPECIFIC_REG5_Undefined_SHIFT 0
-#define BCHP_PCIE_0_RC_CFG_VENDOR_VENDOR_SPECIFIC_REG5_Undefined_DEFAULT 0x00000000
-
-/***************************************************************************
- *VENDOR_SPECIFIC_REG6 - Vendor Specific User Register 6
- ***************************************************************************/
-/* PCIE_0_RC_CFG_VENDOR :: VENDOR_SPECIFIC_REG6 :: Undefined [31:00] */
-#define BCHP_PCIE_0_RC_CFG_VENDOR_VENDOR_SPECIFIC_REG6_Undefined_MASK 0xffffffff
-#define BCHP_PCIE_0_RC_CFG_VENDOR_VENDOR_SPECIFIC_REG6_Undefined_SHIFT 0
-#define BCHP_PCIE_0_RC_CFG_VENDOR_VENDOR_SPECIFIC_REG6_Undefined_DEFAULT 0x00000000
-
-/***************************************************************************
- *VENDOR_SPECIFIC_REG7 - Vendor Specific User Register 7
- ***************************************************************************/
-/* PCIE_0_RC_CFG_VENDOR :: VENDOR_SPECIFIC_REG7 :: Undefined [31:00] */
-#define BCHP_PCIE_0_RC_CFG_VENDOR_VENDOR_SPECIFIC_REG7_Undefined_MASK 0xffffffff
-#define BCHP_PCIE_0_RC_CFG_VENDOR_VENDOR_SPECIFIC_REG7_Undefined_SHIFT 0
-#define BCHP_PCIE_0_RC_CFG_VENDOR_VENDOR_SPECIFIC_REG7_Undefined_DEFAULT 0x00000000
-
-/***************************************************************************
- *VENDOR_SPECIFIC_REG8 - Vendor Specific User Register 8
- ***************************************************************************/
-/* PCIE_0_RC_CFG_VENDOR :: VENDOR_SPECIFIC_REG8 :: Undefined [31:00] */
-#define BCHP_PCIE_0_RC_CFG_VENDOR_VENDOR_SPECIFIC_REG8_Undefined_MASK 0xffffffff
-#define BCHP_PCIE_0_RC_CFG_VENDOR_VENDOR_SPECIFIC_REG8_Undefined_SHIFT 0
-#define BCHP_PCIE_0_RC_CFG_VENDOR_VENDOR_SPECIFIC_REG8_Undefined_DEFAULT 0x00000000
-
-#endif /* #ifndef BCHP_PCIE_0_RC_CFG_VENDOR_H__ */
-
-/* End of File */
diff --git a/include/linux/brcmstb/7145a0/bchp_pcie_0_rgr1.h b/include/linux/brcmstb/7145a0/bchp_pcie_0_rgr1.h
deleted file mode 100644
index f8087f3..0000000
--- a/include/linux/brcmstb/7145a0/bchp_pcie_0_rgr1.h
+++ /dev/null
@@ -1,134 +0,0 @@
-/***************************************************************************
- * Copyright (c) 1999-2013, Broadcom Corporation
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
- *
- * Module Description:
- * DO NOT EDIT THIS FILE DIRECTLY
- *
- * This module was generated magically with RDB from a source description
- * file. You must edit the source file for changes to be made to this file.
- *
- *
- * Date: Generated on Sat Apr 6 03:07:50 2013
- * MD5 Checksum d41d8cd98f00b204e9800998ecf8427e
- *
- * Compiled with: RDB Utility combo_header.pl
- * RDB Parser 3.0
- * unknown unknown
- * Perl Interpreter 5.008008
- * Operating System linux
- *
- * Revision History:
- *
- * $brcm_Log: $
- *
- ***************************************************************************/
-
-#ifndef BCHP_PCIE_0_RGR1_H__
-#define BCHP_PCIE_0_RGR1_H__
-
-/***************************************************************************
- *PCIE_0_RGR1 - PCIe RBUS-GISB-RBUS Bridge Registers
- ***************************************************************************/
-#define BCHP_PCIE_0_RGR1_REVISION 0x07809200 /* RGR Bridge Revision */
-#define BCHP_PCIE_0_RGR1_CTRL 0x07809204 /* RGR Bridge Control Register */
-#define BCHP_PCIE_0_RGR1_RBUS_TIMER 0x07809208 /* RGR Bridge RBUS Timer Register */
-#define BCHP_PCIE_0_RGR1_SW_INIT_0 0x0780920c /* RGR Bridge Software Reset 0 Register */
-#define BCHP_PCIE_0_RGR1_SW_INIT_1 0x07809210 /* RGR Bridge Software Reset 1 Register */
-
-/***************************************************************************
- *REVISION - RGR Bridge Revision
- ***************************************************************************/
-/* PCIE_0_RGR1 :: REVISION :: reserved0 [31:16] */
-#define BCHP_PCIE_0_RGR1_REVISION_reserved0_MASK 0xffff0000
-#define BCHP_PCIE_0_RGR1_REVISION_reserved0_SHIFT 16
-
-/* PCIE_0_RGR1 :: REVISION :: MAJOR [15:08] */
-#define BCHP_PCIE_0_RGR1_REVISION_MAJOR_MASK 0x0000ff00
-#define BCHP_PCIE_0_RGR1_REVISION_MAJOR_SHIFT 8
-#define BCHP_PCIE_0_RGR1_REVISION_MAJOR_DEFAULT 0x00000002
-
-/* PCIE_0_RGR1 :: REVISION :: MINOR [07:00] */
-#define BCHP_PCIE_0_RGR1_REVISION_MINOR_MASK 0x000000ff
-#define BCHP_PCIE_0_RGR1_REVISION_MINOR_SHIFT 0
-#define BCHP_PCIE_0_RGR1_REVISION_MINOR_DEFAULT 0x00000000
-
-/***************************************************************************
- *CTRL - RGR Bridge Control Register
- ***************************************************************************/
-/* PCIE_0_RGR1 :: CTRL :: reserved0 [31:02] */
-#define BCHP_PCIE_0_RGR1_CTRL_reserved0_MASK 0xfffffffc
-#define BCHP_PCIE_0_RGR1_CTRL_reserved0_SHIFT 2
-
-/* PCIE_0_RGR1 :: CTRL :: rbus_error_intr [01:01] */
-#define BCHP_PCIE_0_RGR1_CTRL_rbus_error_intr_MASK 0x00000002
-#define BCHP_PCIE_0_RGR1_CTRL_rbus_error_intr_SHIFT 1
-#define BCHP_PCIE_0_RGR1_CTRL_rbus_error_intr_DEFAULT 0x00000000
-#define BCHP_PCIE_0_RGR1_CTRL_rbus_error_intr_INTR_DISABLE 0
-#define BCHP_PCIE_0_RGR1_CTRL_rbus_error_intr_INTR_ENABLE 1
-
-/* PCIE_0_RGR1 :: CTRL :: gisb_error_intr [00:00] */
-#define BCHP_PCIE_0_RGR1_CTRL_gisb_error_intr_MASK 0x00000001
-#define BCHP_PCIE_0_RGR1_CTRL_gisb_error_intr_SHIFT 0
-#define BCHP_PCIE_0_RGR1_CTRL_gisb_error_intr_DEFAULT 0x00000000
-#define BCHP_PCIE_0_RGR1_CTRL_gisb_error_intr_INTR_DISABLE 0
-#define BCHP_PCIE_0_RGR1_CTRL_gisb_error_intr_INTR_ENABLE 1
-
-/***************************************************************************
- *RBUS_TIMER - RGR Bridge RBUS Timer Register
- ***************************************************************************/
-/* PCIE_0_RGR1 :: RBUS_TIMER :: timer_value [31:00] */
-#define BCHP_PCIE_0_RGR1_RBUS_TIMER_timer_value_MASK 0xffffffff
-#define BCHP_PCIE_0_RGR1_RBUS_TIMER_timer_value_SHIFT 0
-#define BCHP_PCIE_0_RGR1_RBUS_TIMER_timer_value_DEFAULT 0x0e297d00
-
-/***************************************************************************
- *SW_INIT_0 - RGR Bridge Software Reset 0 Register
- ***************************************************************************/
-/* PCIE_0_RGR1 :: SW_INIT_0 :: reserved0 [31:01] */
-#define BCHP_PCIE_0_RGR1_SW_INIT_0_reserved0_MASK 0xfffffffe
-#define BCHP_PCIE_0_RGR1_SW_INIT_0_reserved0_SHIFT 1
-
-/* PCIE_0_RGR1 :: SW_INIT_0 :: SPARE_SW_INIT [00:00] */
-#define BCHP_PCIE_0_RGR1_SW_INIT_0_SPARE_SW_INIT_MASK 0x00000001
-#define BCHP_PCIE_0_RGR1_SW_INIT_0_SPARE_SW_INIT_SHIFT 0
-#define BCHP_PCIE_0_RGR1_SW_INIT_0_SPARE_SW_INIT_DEFAULT 0x00000000
-#define BCHP_PCIE_0_RGR1_SW_INIT_0_SPARE_SW_INIT_DEASSERT 0
-#define BCHP_PCIE_0_RGR1_SW_INIT_0_SPARE_SW_INIT_ASSERT 1
-
-/***************************************************************************
- *SW_INIT_1 - RGR Bridge Software Reset 1 Register
- ***************************************************************************/
-/* PCIE_0_RGR1 :: SW_INIT_1 :: reserved0 [31:02] */
-#define BCHP_PCIE_0_RGR1_SW_INIT_1_reserved0_MASK 0xfffffffc
-#define BCHP_PCIE_0_RGR1_SW_INIT_1_reserved0_SHIFT 2
-
-/* PCIE_0_RGR1 :: SW_INIT_1 :: PCIE_BRIDGE_SW_INIT [01:01] */
-#define BCHP_PCIE_0_RGR1_SW_INIT_1_PCIE_BRIDGE_SW_INIT_MASK 0x00000002
-#define BCHP_PCIE_0_RGR1_SW_INIT_1_PCIE_BRIDGE_SW_INIT_SHIFT 1
-#define BCHP_PCIE_0_RGR1_SW_INIT_1_PCIE_BRIDGE_SW_INIT_DEFAULT 0x00000001
-#define BCHP_PCIE_0_RGR1_SW_INIT_1_PCIE_BRIDGE_SW_INIT_DEASSERT 0
-#define BCHP_PCIE_0_RGR1_SW_INIT_1_PCIE_BRIDGE_SW_INIT_ASSERT 1
-
-/* PCIE_0_RGR1 :: SW_INIT_1 :: PCIE_SW_PERST [00:00] */
-#define BCHP_PCIE_0_RGR1_SW_INIT_1_PCIE_SW_PERST_MASK 0x00000001
-#define BCHP_PCIE_0_RGR1_SW_INIT_1_PCIE_SW_PERST_SHIFT 0
-#define BCHP_PCIE_0_RGR1_SW_INIT_1_PCIE_SW_PERST_DEFAULT 0x00000001
-#define BCHP_PCIE_0_RGR1_SW_INIT_1_PCIE_SW_PERST_DEASSERT 0
-#define BCHP_PCIE_0_RGR1_SW_INIT_1_PCIE_SW_PERST_ASSERT 1
-
-#endif /* #ifndef BCHP_PCIE_0_RGR1_H__ */
-
-/* End of File */
diff --git a/include/linux/brcmstb/7145a0/bchp_shimphy_addr_cntl_0.h b/include/linux/brcmstb/7145a0/bchp_shimphy_addr_cntl_0.h
deleted file mode 100644
index 434c737..0000000
--- a/include/linux/brcmstb/7145a0/bchp_shimphy_addr_cntl_0.h
+++ /dev/null
@@ -1,547 +0,0 @@
-/***************************************************************************
- * Copyright (c) 1999-2013, Broadcom Corporation
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
- *
- * Module Description:
- * DO NOT EDIT THIS FILE DIRECTLY
- *
- * This module was generated magically with RDB from a source description
- * file. You must edit the source file for changes to be made to this file.
- *
- *
- * Date: Generated on Sat Apr 6 03:07:50 2013
- * MD5 Checksum d41d8cd98f00b204e9800998ecf8427e
- *
- * Compiled with: RDB Utility combo_header.pl
- * RDB Parser 3.0
- * unknown unknown
- * Perl Interpreter 5.008008
- * Operating System linux
- *
- * Revision History:
- *
- * $brcm_Log: $
- *
- ***************************************************************************/
-
-#ifndef BCHP_SHIMPHY_ADDR_CNTL_0_H__
-#define BCHP_SHIMPHY_ADDR_CNTL_0_H__
-
-/***************************************************************************
- *SHIMPHY_ADDR_CNTL_0 - 0 DDR SHIMPHY Control Registers
- ***************************************************************************/
-#define BCHP_SHIMPHY_ADDR_CNTL_0_CONFIG 0x203b8000 /* SHIMPHY Config register */
-#define BCHP_SHIMPHY_ADDR_CNTL_0_SHIMPHY_REV_ID 0x203b8004 /* SHIMPHY Revision ID Register. */
-#define BCHP_SHIMPHY_ADDR_CNTL_0_RESET 0x203b8008 /* DDR soft reset register */
-#define BCHP_SHIMPHY_ADDR_CNTL_0_DFI_CONTROL 0x203b8038 /* DFI Interface Control Register */
-#define BCHP_SHIMPHY_ADDR_CNTL_0_DFI_STATUS 0x203b803c /* DFI Interface Status Register */
-#define BCHP_SHIMPHY_ADDR_CNTL_0_PHY_LPM_STAT 0x203b8040 /* PHY Power Control Status Register */
-#define BCHP_SHIMPHY_ADDR_CNTL_0_IDLE_POWER_SAVING 0x203b8048 /* DDR PHY Idle power saving Control register */
-#define BCHP_SHIMPHY_ADDR_CNTL_0_PHY_STANDBY_EXIT 0x203b804c /* DDR PHY standby exit register */
-#define BCHP_SHIMPHY_ADDR_CNTL_0_ANALOG_BYPASS_CNTRL 0x203b806c /* Analog macro register bypass control */
-#define BCHP_SHIMPHY_ADDR_CNTL_0_DDR_PLL_EXT_CLKSEL 0x203b8070 /* DDR PLL external clock select register */
-#define BCHP_SHIMPHY_ADDR_CNTL_0_TEST_MODE_CNTRL_REG 0x203b8074 /* SHIMPHY testport control register */
-#define BCHP_SHIMPHY_ADDR_CNTL_0_DISABLE_CHIP_BYPASS_PLL 0x203b807c /* DDR bypass pll mode disable register. */
-#define BCHP_SHIMPHY_ADDR_CNTL_0_VECTOR_MODE_CLK_SEL 0x203b8088 /* DDR VECTOR PLL bypass mode clock select */
-#define BCHP_SHIMPHY_ADDR_CNTL_0_DDR_PAD_CNTRL 0x203b808c /* DDR Pad control register */
-#define BCHP_SHIMPHY_ADDR_CNTL_0_CLK_GATE 0x203b8098 /* CLK_667_ENABLE Register */
-#define BCHP_SHIMPHY_ADDR_CNTL_0_SHIMPHY_STATUS 0x203b809c /* SHIMPHY Status Register */
-#define BCHP_SHIMPHY_ADDR_CNTL_0_CMD_DATA_FIFO 0x203b8028 /* Command and Data FIFO Status Register */
-#define BCHP_SHIMPHY_ADDR_CNTL_0_RD_DATAPATH 0x203b802c /* Read Datapath Status Register */
-#define BCHP_SHIMPHY_ADDR_CNTL_0_FLAG_BUS 0x203b8030 /* TP_OUT bus value Register */
-#define BCHP_SHIMPHY_ADDR_CNTL_0_MISC 0x203b8034 /* Miscellaneous Register */
-#define BCHP_SHIMPHY_ADDR_CNTL_0_SPARE0_RW 0x203b80a4 /* Spare register */
-#define BCHP_SHIMPHY_ADDR_CNTL_0_SPARE1_RW 0x203b80a8 /* Spare register */
-#define BCHP_SHIMPHY_ADDR_CNTL_0_SPARE0_RO 0x203b80ac /* Spare register */
-#define BCHP_SHIMPHY_ADDR_CNTL_0_SPARE1_RO 0x203b80b0 /* Spare register */
-#define BCHP_SHIMPHY_ADDR_CNTL_0_DDR3_RESET_CNTRL 0x203b80b4 /* FORCE_DDR3_RESET Deassert Register */
-
-/***************************************************************************
- *CONFIG - SHIMPHY Config register
- ***************************************************************************/
-/* SHIMPHY_ADDR_CNTL_0 :: CONFIG :: DFI_CLK_DISABLE [31:31] */
-#define BCHP_SHIMPHY_ADDR_CNTL_0_CONFIG_DFI_CLK_DISABLE_MASK 0x80000000
-#define BCHP_SHIMPHY_ADDR_CNTL_0_CONFIG_DFI_CLK_DISABLE_SHIFT 31
-#define BCHP_SHIMPHY_ADDR_CNTL_0_CONFIG_DFI_CLK_DISABLE_DEFAULT 0x00000000
-
-/* SHIMPHY_ADDR_CNTL_0 :: CONFIG :: DRAM_NOP_OR_DSEL_CMD [30:30] */
-#define BCHP_SHIMPHY_ADDR_CNTL_0_CONFIG_DRAM_NOP_OR_DSEL_CMD_MASK 0x40000000
-#define BCHP_SHIMPHY_ADDR_CNTL_0_CONFIG_DRAM_NOP_OR_DSEL_CMD_SHIFT 30
-#define BCHP_SHIMPHY_ADDR_CNTL_0_CONFIG_DRAM_NOP_OR_DSEL_CMD_DEFAULT 0x00000000
-
-/* SHIMPHY_ADDR_CNTL_0 :: CONFIG :: LAST_RD_STRETCH [29:29] */
-#define BCHP_SHIMPHY_ADDR_CNTL_0_CONFIG_LAST_RD_STRETCH_MASK 0x20000000
-#define BCHP_SHIMPHY_ADDR_CNTL_0_CONFIG_LAST_RD_STRETCH_SHIFT 29
-#define BCHP_SHIMPHY_ADDR_CNTL_0_CONFIG_LAST_RD_STRETCH_DEFAULT 0x00000000
-
-/* SHIMPHY_ADDR_CNTL_0 :: CONFIG :: reserved0 [28:24] */
-#define BCHP_SHIMPHY_ADDR_CNTL_0_CONFIG_reserved0_MASK 0x1f000000
-#define BCHP_SHIMPHY_ADDR_CNTL_0_CONFIG_reserved0_SHIFT 24
-
-/* SHIMPHY_ADDR_CNTL_0 :: CONFIG :: LAST_READ_LATENCY [23:16] */
-#define BCHP_SHIMPHY_ADDR_CNTL_0_CONFIG_LAST_READ_LATENCY_MASK 0x00ff0000
-#define BCHP_SHIMPHY_ADDR_CNTL_0_CONFIG_LAST_READ_LATENCY_SHIFT 16
-#define BCHP_SHIMPHY_ADDR_CNTL_0_CONFIG_LAST_READ_LATENCY_DEFAULT 0x0000000b
-
-/* SHIMPHY_ADDR_CNTL_0 :: CONFIG :: READ_LATENCY [15:08] */
-#define BCHP_SHIMPHY_ADDR_CNTL_0_CONFIG_READ_LATENCY_MASK 0x0000ff00
-#define BCHP_SHIMPHY_ADDR_CNTL_0_CONFIG_READ_LATENCY_SHIFT 8
-#define BCHP_SHIMPHY_ADDR_CNTL_0_CONFIG_READ_LATENCY_DEFAULT 0x00000007
-
-/* SHIMPHY_ADDR_CNTL_0 :: CONFIG :: reserved1 [07:06] */
-#define BCHP_SHIMPHY_ADDR_CNTL_0_CONFIG_reserved1_MASK 0x000000c0
-#define BCHP_SHIMPHY_ADDR_CNTL_0_CONFIG_reserved1_SHIFT 6
-
-/* SHIMPHY_ADDR_CNTL_0 :: CONFIG :: WRITE_LATENCY [05:00] */
-#define BCHP_SHIMPHY_ADDR_CNTL_0_CONFIG_WRITE_LATENCY_MASK 0x0000003f
-#define BCHP_SHIMPHY_ADDR_CNTL_0_CONFIG_WRITE_LATENCY_SHIFT 0
-#define BCHP_SHIMPHY_ADDR_CNTL_0_CONFIG_WRITE_LATENCY_DEFAULT 0x0000000e
-
-/***************************************************************************
- *SHIMPHY_REV_ID - SHIMPHY Revision ID Register.
- ***************************************************************************/
-/* SHIMPHY_ADDR_CNTL_0 :: SHIMPHY_REV_ID :: reserved0 [31:16] */
-#define BCHP_SHIMPHY_ADDR_CNTL_0_SHIMPHY_REV_ID_reserved0_MASK 0xffff0000
-#define BCHP_SHIMPHY_ADDR_CNTL_0_SHIMPHY_REV_ID_reserved0_SHIFT 16
-
-/* SHIMPHY_ADDR_CNTL_0 :: SHIMPHY_REV_ID :: MAJOR_ID [15:08] */
-#define BCHP_SHIMPHY_ADDR_CNTL_0_SHIMPHY_REV_ID_MAJOR_ID_MASK 0x0000ff00
-#define BCHP_SHIMPHY_ADDR_CNTL_0_SHIMPHY_REV_ID_MAJOR_ID_SHIFT 8
-#define BCHP_SHIMPHY_ADDR_CNTL_0_SHIMPHY_REV_ID_MAJOR_ID_DEFAULT 0x00000001
-
-/* SHIMPHY_ADDR_CNTL_0 :: SHIMPHY_REV_ID :: MINOR_ID [07:00] */
-#define BCHP_SHIMPHY_ADDR_CNTL_0_SHIMPHY_REV_ID_MINOR_ID_MASK 0x000000ff
-#define BCHP_SHIMPHY_ADDR_CNTL_0_SHIMPHY_REV_ID_MINOR_ID_SHIFT 0
-#define BCHP_SHIMPHY_ADDR_CNTL_0_SHIMPHY_REV_ID_MINOR_ID_DEFAULT 0x00000000
-
-/***************************************************************************
- *RESET - DDR soft reset register
- ***************************************************************************/
-/* SHIMPHY_ADDR_CNTL_0 :: RESET :: reserved0 [31:03] */
-#define BCHP_SHIMPHY_ADDR_CNTL_0_RESET_reserved0_MASK 0xfffffff8
-#define BCHP_SHIMPHY_ADDR_CNTL_0_RESET_reserved0_SHIFT 3
-
-/* SHIMPHY_ADDR_CNTL_0 :: RESET :: DATAPATH_216_RESET [02:02] */
-#define BCHP_SHIMPHY_ADDR_CNTL_0_RESET_DATAPATH_216_RESET_MASK 0x00000004
-#define BCHP_SHIMPHY_ADDR_CNTL_0_RESET_DATAPATH_216_RESET_SHIFT 2
-#define BCHP_SHIMPHY_ADDR_CNTL_0_RESET_DATAPATH_216_RESET_DEFAULT 0x00000000
-
-/* SHIMPHY_ADDR_CNTL_0 :: RESET :: DATAPATH_DDR_RESET [01:01] */
-#define BCHP_SHIMPHY_ADDR_CNTL_0_RESET_DATAPATH_DDR_RESET_MASK 0x00000002
-#define BCHP_SHIMPHY_ADDR_CNTL_0_RESET_DATAPATH_DDR_RESET_SHIFT 1
-#define BCHP_SHIMPHY_ADDR_CNTL_0_RESET_DATAPATH_DDR_RESET_DEFAULT 0x00000000
-
-/* SHIMPHY_ADDR_CNTL_0 :: RESET :: PHY_PWRUP_RSB [00:00] */
-#define BCHP_SHIMPHY_ADDR_CNTL_0_RESET_PHY_PWRUP_RSB_MASK 0x00000001
-#define BCHP_SHIMPHY_ADDR_CNTL_0_RESET_PHY_PWRUP_RSB_SHIFT 0
-#define BCHP_SHIMPHY_ADDR_CNTL_0_RESET_PHY_PWRUP_RSB_DEFAULT 0x00000000
-
-/***************************************************************************
- *DFI_CONTROL - DFI Interface Control Register
- ***************************************************************************/
-/* SHIMPHY_ADDR_CNTL_0 :: DFI_CONTROL :: reserved0 [31:10] */
-#define BCHP_SHIMPHY_ADDR_CNTL_0_DFI_CONTROL_reserved0_MASK 0xfffffc00
-#define BCHP_SHIMPHY_ADDR_CNTL_0_DFI_CONTROL_reserved0_SHIFT 10
-
-/* SHIMPHY_ADDR_CNTL_0 :: DFI_CONTROL :: TM2_MUX_SEL [09:09] */
-#define BCHP_SHIMPHY_ADDR_CNTL_0_DFI_CONTROL_TM2_MUX_SEL_MASK 0x00000200
-#define BCHP_SHIMPHY_ADDR_CNTL_0_DFI_CONTROL_TM2_MUX_SEL_SHIFT 9
-#define BCHP_SHIMPHY_ADDR_CNTL_0_DFI_CONTROL_TM2_MUX_SEL_DEFAULT 0x00000000
-
-/* SHIMPHY_ADDR_CNTL_0 :: DFI_CONTROL :: PHY_PLL_HOLD_CH [08:08] */
-#define BCHP_SHIMPHY_ADDR_CNTL_0_DFI_CONTROL_PHY_PLL_HOLD_CH_MASK 0x00000100
-#define BCHP_SHIMPHY_ADDR_CNTL_0_DFI_CONTROL_PHY_PLL_HOLD_CH_SHIFT 8
-#define BCHP_SHIMPHY_ADDR_CNTL_0_DFI_CONTROL_PHY_PLL_HOLD_CH_DEFAULT 0x00000000
-
-/* SHIMPHY_ADDR_CNTL_0 :: DFI_CONTROL :: reserved1 [07:01] */
-#define BCHP_SHIMPHY_ADDR_CNTL_0_DFI_CONTROL_reserved1_MASK 0x000000fe
-#define BCHP_SHIMPHY_ADDR_CNTL_0_DFI_CONTROL_reserved1_SHIFT 1
-
-/* SHIMPHY_ADDR_CNTL_0 :: DFI_CONTROL :: LATCH_FIRST_ERROR [00:00] */
-#define BCHP_SHIMPHY_ADDR_CNTL_0_DFI_CONTROL_LATCH_FIRST_ERROR_MASK 0x00000001
-#define BCHP_SHIMPHY_ADDR_CNTL_0_DFI_CONTROL_LATCH_FIRST_ERROR_SHIFT 0
-#define BCHP_SHIMPHY_ADDR_CNTL_0_DFI_CONTROL_LATCH_FIRST_ERROR_DEFAULT 0x00000001
-
-/***************************************************************************
- *DFI_STATUS - DFI Interface Status Register
- ***************************************************************************/
-/* SHIMPHY_ADDR_CNTL_0 :: DFI_STATUS :: reserved0 [31:18] */
-#define BCHP_SHIMPHY_ADDR_CNTL_0_DFI_STATUS_reserved0_MASK 0xfffc0000
-#define BCHP_SHIMPHY_ADDR_CNTL_0_DFI_STATUS_reserved0_SHIFT 18
-
-/* SHIMPHY_ADDR_CNTL_0 :: DFI_STATUS :: PHY_EDC_MONITOR_STATUS [17:17] */
-#define BCHP_SHIMPHY_ADDR_CNTL_0_DFI_STATUS_PHY_EDC_MONITOR_STATUS_MASK 0x00020000
-#define BCHP_SHIMPHY_ADDR_CNTL_0_DFI_STATUS_PHY_EDC_MONITOR_STATUS_SHIFT 17
-#define BCHP_SHIMPHY_ADDR_CNTL_0_DFI_STATUS_PHY_EDC_MONITOR_STATUS_DEFAULT 0x00000000
-
-/* SHIMPHY_ADDR_CNTL_0 :: DFI_STATUS :: PHY_VDL_MONITOR_STATUS [16:16] */
-#define BCHP_SHIMPHY_ADDR_CNTL_0_DFI_STATUS_PHY_VDL_MONITOR_STATUS_MASK 0x00010000
-#define BCHP_SHIMPHY_ADDR_CNTL_0_DFI_STATUS_PHY_VDL_MONITOR_STATUS_SHIFT 16
-#define BCHP_SHIMPHY_ADDR_CNTL_0_DFI_STATUS_PHY_VDL_MONITOR_STATUS_DEFAULT 0x00000000
-
-/* SHIMPHY_ADDR_CNTL_0 :: DFI_STATUS :: reserved1 [15:09] */
-#define BCHP_SHIMPHY_ADDR_CNTL_0_DFI_STATUS_reserved1_MASK 0x0000fe00
-#define BCHP_SHIMPHY_ADDR_CNTL_0_DFI_STATUS_reserved1_SHIFT 9
-
-/* SHIMPHY_ADDR_CNTL_0 :: DFI_STATUS :: ERROR_VALID [08:08] */
-#define BCHP_SHIMPHY_ADDR_CNTL_0_DFI_STATUS_ERROR_VALID_MASK 0x00000100
-#define BCHP_SHIMPHY_ADDR_CNTL_0_DFI_STATUS_ERROR_VALID_SHIFT 8
-#define BCHP_SHIMPHY_ADDR_CNTL_0_DFI_STATUS_ERROR_VALID_DEFAULT 0x00000000
-
-/* SHIMPHY_ADDR_CNTL_0 :: DFI_STATUS :: reserved2 [07:04] */
-#define BCHP_SHIMPHY_ADDR_CNTL_0_DFI_STATUS_reserved2_MASK 0x000000f0
-#define BCHP_SHIMPHY_ADDR_CNTL_0_DFI_STATUS_reserved2_SHIFT 4
-
-/* SHIMPHY_ADDR_CNTL_0 :: DFI_STATUS :: ERROR_INFO [03:00] */
-#define BCHP_SHIMPHY_ADDR_CNTL_0_DFI_STATUS_ERROR_INFO_MASK 0x0000000f
-#define BCHP_SHIMPHY_ADDR_CNTL_0_DFI_STATUS_ERROR_INFO_SHIFT 0
-#define BCHP_SHIMPHY_ADDR_CNTL_0_DFI_STATUS_ERROR_INFO_DEFAULT 0x00000000
-
-/***************************************************************************
- *PHY_LPM_STAT - PHY Power Control Status Register
- ***************************************************************************/
-/* SHIMPHY_ADDR_CNTL_0 :: PHY_LPM_STAT :: reserved0 [31:10] */
-#define BCHP_SHIMPHY_ADDR_CNTL_0_PHY_LPM_STAT_reserved0_MASK 0xfffffc00
-#define BCHP_SHIMPHY_ADDR_CNTL_0_PHY_LPM_STAT_reserved0_SHIFT 10
-
-/* SHIMPHY_ADDR_CNTL_0 :: PHY_LPM_STAT :: PHY_RBUS_IS_IDLE [09:09] */
-#define BCHP_SHIMPHY_ADDR_CNTL_0_PHY_LPM_STAT_PHY_RBUS_IS_IDLE_MASK 0x00000200
-#define BCHP_SHIMPHY_ADDR_CNTL_0_PHY_LPM_STAT_PHY_RBUS_IS_IDLE_SHIFT 9
-#define BCHP_SHIMPHY_ADDR_CNTL_0_PHY_LPM_STAT_PHY_RBUS_IS_IDLE_DEFAULT 0x00000000
-
-/* SHIMPHY_ADDR_CNTL_0 :: PHY_LPM_STAT :: PHY_IS_IDLE [08:08] */
-#define BCHP_SHIMPHY_ADDR_CNTL_0_PHY_LPM_STAT_PHY_IS_IDLE_MASK 0x00000100
-#define BCHP_SHIMPHY_ADDR_CNTL_0_PHY_LPM_STAT_PHY_IS_IDLE_SHIFT 8
-#define BCHP_SHIMPHY_ADDR_CNTL_0_PHY_LPM_STAT_PHY_IS_IDLE_DEFAULT 0x00000000
-
-/* SHIMPHY_ADDR_CNTL_0 :: PHY_LPM_STAT :: reserved1 [07:00] */
-#define BCHP_SHIMPHY_ADDR_CNTL_0_PHY_LPM_STAT_reserved1_MASK 0x000000ff
-#define BCHP_SHIMPHY_ADDR_CNTL_0_PHY_LPM_STAT_reserved1_SHIFT 0
-
-/***************************************************************************
- *IDLE_POWER_SAVING - DDR PHY Idle power saving Control register
- ***************************************************************************/
-/* SHIMPHY_ADDR_CNTL_0 :: IDLE_POWER_SAVING :: reserved0 [31:06] */
-#define BCHP_SHIMPHY_ADDR_CNTL_0_IDLE_POWER_SAVING_reserved0_MASK 0xffffffc0
-#define BCHP_SHIMPHY_ADDR_CNTL_0_IDLE_POWER_SAVING_reserved0_SHIFT 6
-
-/* SHIMPHY_ADDR_CNTL_0 :: IDLE_POWER_SAVING :: PhyAddrCntl [05:04] */
-#define BCHP_SHIMPHY_ADDR_CNTL_0_IDLE_POWER_SAVING_PhyAddrCntl_MASK 0x00000030
-#define BCHP_SHIMPHY_ADDR_CNTL_0_IDLE_POWER_SAVING_PhyAddrCntl_SHIFT 4
-#define BCHP_SHIMPHY_ADDR_CNTL_0_IDLE_POWER_SAVING_PhyAddrCntl_DEFAULT 0x00000000
-
-/* SHIMPHY_ADDR_CNTL_0 :: IDLE_POWER_SAVING :: ByteLane3 [03:03] */
-#define BCHP_SHIMPHY_ADDR_CNTL_0_IDLE_POWER_SAVING_ByteLane3_MASK 0x00000008
-#define BCHP_SHIMPHY_ADDR_CNTL_0_IDLE_POWER_SAVING_ByteLane3_SHIFT 3
-#define BCHP_SHIMPHY_ADDR_CNTL_0_IDLE_POWER_SAVING_ByteLane3_DEFAULT 0x00000000
-
-/* SHIMPHY_ADDR_CNTL_0 :: IDLE_POWER_SAVING :: ByteLane2 [02:02] */
-#define BCHP_SHIMPHY_ADDR_CNTL_0_IDLE_POWER_SAVING_ByteLane2_MASK 0x00000004
-#define BCHP_SHIMPHY_ADDR_CNTL_0_IDLE_POWER_SAVING_ByteLane2_SHIFT 2
-#define BCHP_SHIMPHY_ADDR_CNTL_0_IDLE_POWER_SAVING_ByteLane2_DEFAULT 0x00000000
-
-/* SHIMPHY_ADDR_CNTL_0 :: IDLE_POWER_SAVING :: ByteLane1 [01:01] */
-#define BCHP_SHIMPHY_ADDR_CNTL_0_IDLE_POWER_SAVING_ByteLane1_MASK 0x00000002
-#define BCHP_SHIMPHY_ADDR_CNTL_0_IDLE_POWER_SAVING_ByteLane1_SHIFT 1
-#define BCHP_SHIMPHY_ADDR_CNTL_0_IDLE_POWER_SAVING_ByteLane1_DEFAULT 0x00000000
-
-/* SHIMPHY_ADDR_CNTL_0 :: IDLE_POWER_SAVING :: ByteLane0 [00:00] */
-#define BCHP_SHIMPHY_ADDR_CNTL_0_IDLE_POWER_SAVING_ByteLane0_MASK 0x00000001
-#define BCHP_SHIMPHY_ADDR_CNTL_0_IDLE_POWER_SAVING_ByteLane0_SHIFT 0
-#define BCHP_SHIMPHY_ADDR_CNTL_0_IDLE_POWER_SAVING_ByteLane0_DEFAULT 0x00000000
-
-/***************************************************************************
- *PHY_STANDBY_EXIT - DDR PHY standby exit register
- ***************************************************************************/
-/* SHIMPHY_ADDR_CNTL_0 :: PHY_STANDBY_EXIT :: reserved0 [31:01] */
-#define BCHP_SHIMPHY_ADDR_CNTL_0_PHY_STANDBY_EXIT_reserved0_MASK 0xfffffffe
-#define BCHP_SHIMPHY_ADDR_CNTL_0_PHY_STANDBY_EXIT_reserved0_SHIFT 1
-
-/* SHIMPHY_ADDR_CNTL_0 :: PHY_STANDBY_EXIT :: ENABLE [00:00] */
-#define BCHP_SHIMPHY_ADDR_CNTL_0_PHY_STANDBY_EXIT_ENABLE_MASK 0x00000001
-#define BCHP_SHIMPHY_ADDR_CNTL_0_PHY_STANDBY_EXIT_ENABLE_SHIFT 0
-#define BCHP_SHIMPHY_ADDR_CNTL_0_PHY_STANDBY_EXIT_ENABLE_DEFAULT 0x00000001
-
-/***************************************************************************
- *ANALOG_BYPASS_CNTRL - Analog macro register bypass control
- ***************************************************************************/
-/* SHIMPHY_ADDR_CNTL_0 :: ANALOG_BYPASS_CNTRL :: reserved0 [31:01] */
-#define BCHP_SHIMPHY_ADDR_CNTL_0_ANALOG_BYPASS_CNTRL_reserved0_MASK 0xfffffffe
-#define BCHP_SHIMPHY_ADDR_CNTL_0_ANALOG_BYPASS_CNTRL_reserved0_SHIFT 1
-
-/* SHIMPHY_ADDR_CNTL_0 :: ANALOG_BYPASS_CNTRL :: BYPASS_PLL [00:00] */
-#define BCHP_SHIMPHY_ADDR_CNTL_0_ANALOG_BYPASS_CNTRL_BYPASS_PLL_MASK 0x00000001
-#define BCHP_SHIMPHY_ADDR_CNTL_0_ANALOG_BYPASS_CNTRL_BYPASS_PLL_SHIFT 0
-#define BCHP_SHIMPHY_ADDR_CNTL_0_ANALOG_BYPASS_CNTRL_BYPASS_PLL_DEFAULT 0x00000000
-
-/***************************************************************************
- *DDR_PLL_EXT_CLKSEL - DDR PLL external clock select register
- ***************************************************************************/
-/* SHIMPHY_ADDR_CNTL_0 :: DDR_PLL_EXT_CLKSEL :: reserved0 [31:01] */
-#define BCHP_SHIMPHY_ADDR_CNTL_0_DDR_PLL_EXT_CLKSEL_reserved0_MASK 0xfffffffe
-#define BCHP_SHIMPHY_ADDR_CNTL_0_DDR_PLL_EXT_CLKSEL_reserved0_SHIFT 1
-
-/* SHIMPHY_ADDR_CNTL_0 :: DDR_PLL_EXT_CLKSEL :: EXT_CLK_SEL [00:00] */
-#define BCHP_SHIMPHY_ADDR_CNTL_0_DDR_PLL_EXT_CLKSEL_EXT_CLK_SEL_MASK 0x00000001
-#define BCHP_SHIMPHY_ADDR_CNTL_0_DDR_PLL_EXT_CLKSEL_EXT_CLK_SEL_SHIFT 0
-#define BCHP_SHIMPHY_ADDR_CNTL_0_DDR_PLL_EXT_CLKSEL_EXT_CLK_SEL_DEFAULT 0x00000000
-
-/***************************************************************************
- *TEST_MODE_CNTRL_REG - SHIMPHY testport control register
- ***************************************************************************/
-/* SHIMPHY_ADDR_CNTL_0 :: TEST_MODE_CNTRL_REG :: reserved_for_eco0 [31:00] */
-#define BCHP_SHIMPHY_ADDR_CNTL_0_TEST_MODE_CNTRL_REG_reserved_for_eco0_MASK 0xffffffff
-#define BCHP_SHIMPHY_ADDR_CNTL_0_TEST_MODE_CNTRL_REG_reserved_for_eco0_SHIFT 0
-#define BCHP_SHIMPHY_ADDR_CNTL_0_TEST_MODE_CNTRL_REG_reserved_for_eco0_DEFAULT 0x00000000
-
-/***************************************************************************
- *DISABLE_CHIP_BYPASS_PLL - DDR bypass pll mode disable register.
- ***************************************************************************/
-/* SHIMPHY_ADDR_CNTL_0 :: DISABLE_CHIP_BYPASS_PLL :: reserved0 [31:01] */
-#define BCHP_SHIMPHY_ADDR_CNTL_0_DISABLE_CHIP_BYPASS_PLL_reserved0_MASK 0xfffffffe
-#define BCHP_SHIMPHY_ADDR_CNTL_0_DISABLE_CHIP_BYPASS_PLL_reserved0_SHIFT 1
-
-/* SHIMPHY_ADDR_CNTL_0 :: DISABLE_CHIP_BYPASS_PLL :: DISABLE_BYPASS_PLL [00:00] */
-#define BCHP_SHIMPHY_ADDR_CNTL_0_DISABLE_CHIP_BYPASS_PLL_DISABLE_BYPASS_PLL_MASK 0x00000001
-#define BCHP_SHIMPHY_ADDR_CNTL_0_DISABLE_CHIP_BYPASS_PLL_DISABLE_BYPASS_PLL_SHIFT 0
-#define BCHP_SHIMPHY_ADDR_CNTL_0_DISABLE_CHIP_BYPASS_PLL_DISABLE_BYPASS_PLL_DEFAULT 0x00000000
-
-/***************************************************************************
- *VECTOR_MODE_CLK_SEL - DDR VECTOR PLL bypass mode clock select
- ***************************************************************************/
-/* SHIMPHY_ADDR_CNTL_0 :: VECTOR_MODE_CLK_SEL :: reserved0 [31:01] */
-#define BCHP_SHIMPHY_ADDR_CNTL_0_VECTOR_MODE_CLK_SEL_reserved0_MASK 0xfffffffe
-#define BCHP_SHIMPHY_ADDR_CNTL_0_VECTOR_MODE_CLK_SEL_reserved0_SHIFT 1
-
-/* SHIMPHY_ADDR_CNTL_0 :: VECTOR_MODE_CLK_SEL :: SEL [00:00] */
-#define BCHP_SHIMPHY_ADDR_CNTL_0_VECTOR_MODE_CLK_SEL_SEL_MASK 0x00000001
-#define BCHP_SHIMPHY_ADDR_CNTL_0_VECTOR_MODE_CLK_SEL_SEL_SHIFT 0
-#define BCHP_SHIMPHY_ADDR_CNTL_0_VECTOR_MODE_CLK_SEL_SEL_DEFAULT 0x00000000
-
-/***************************************************************************
- *DDR_PAD_CNTRL - DDR Pad control register
- ***************************************************************************/
-/* SHIMPHY_ADDR_CNTL_0 :: DDR_PAD_CNTRL :: reserved0 [31:07] */
-#define BCHP_SHIMPHY_ADDR_CNTL_0_DDR_PAD_CNTRL_reserved0_MASK 0xffffff80
-#define BCHP_SHIMPHY_ADDR_CNTL_0_DDR_PAD_CNTRL_reserved0_SHIFT 7
-
-/* SHIMPHY_ADDR_CNTL_0 :: DDR_PAD_CNTRL :: IDDQ_MODE_ON_SELFREF [06:06] */
-#define BCHP_SHIMPHY_ADDR_CNTL_0_DDR_PAD_CNTRL_IDDQ_MODE_ON_SELFREF_MASK 0x00000040
-#define BCHP_SHIMPHY_ADDR_CNTL_0_DDR_PAD_CNTRL_IDDQ_MODE_ON_SELFREF_SHIFT 6
-#define BCHP_SHIMPHY_ADDR_CNTL_0_DDR_PAD_CNTRL_IDDQ_MODE_ON_SELFREF_DEFAULT 0x00000000
-
-/* SHIMPHY_ADDR_CNTL_0 :: DDR_PAD_CNTRL :: PHY_IDLE_ENABLE [05:05] */
-#define BCHP_SHIMPHY_ADDR_CNTL_0_DDR_PAD_CNTRL_PHY_IDLE_ENABLE_MASK 0x00000020
-#define BCHP_SHIMPHY_ADDR_CNTL_0_DDR_PAD_CNTRL_PHY_IDLE_ENABLE_SHIFT 5
-#define BCHP_SHIMPHY_ADDR_CNTL_0_DDR_PAD_CNTRL_PHY_IDLE_ENABLE_DEFAULT 0x00000000
-
-/* SHIMPHY_ADDR_CNTL_0 :: DDR_PAD_CNTRL :: HIZ_ON_SELFREF [04:04] */
-#define BCHP_SHIMPHY_ADDR_CNTL_0_DDR_PAD_CNTRL_HIZ_ON_SELFREF_MASK 0x00000010
-#define BCHP_SHIMPHY_ADDR_CNTL_0_DDR_PAD_CNTRL_HIZ_ON_SELFREF_SHIFT 4
-#define BCHP_SHIMPHY_ADDR_CNTL_0_DDR_PAD_CNTRL_HIZ_ON_SELFREF_DEFAULT 0x00000000
-
-/* SHIMPHY_ADDR_CNTL_0 :: DDR_PAD_CNTRL :: CNTRL [03:00] */
-#define BCHP_SHIMPHY_ADDR_CNTL_0_DDR_PAD_CNTRL_CNTRL_MASK 0x0000000f
-#define BCHP_SHIMPHY_ADDR_CNTL_0_DDR_PAD_CNTRL_CNTRL_SHIFT 0
-#define BCHP_SHIMPHY_ADDR_CNTL_0_DDR_PAD_CNTRL_CNTRL_DEFAULT 0x00000000
-
-/***************************************************************************
- *CLK_GATE - CLK_667_ENABLE Register
- ***************************************************************************/
-/* SHIMPHY_ADDR_CNTL_0 :: CLK_GATE :: UNUSED [31:01] */
-#define BCHP_SHIMPHY_ADDR_CNTL_0_CLK_GATE_UNUSED_MASK 0xfffffffe
-#define BCHP_SHIMPHY_ADDR_CNTL_0_CLK_GATE_UNUSED_SHIFT 1
-#define BCHP_SHIMPHY_ADDR_CNTL_0_CLK_GATE_UNUSED_DEFAULT 0x00000000
-
-/* SHIMPHY_ADDR_CNTL_0 :: CLK_GATE :: CLK_667_ENABLE [00:00] */
-#define BCHP_SHIMPHY_ADDR_CNTL_0_CLK_GATE_CLK_667_ENABLE_MASK 0x00000001
-#define BCHP_SHIMPHY_ADDR_CNTL_0_CLK_GATE_CLK_667_ENABLE_SHIFT 0
-#define BCHP_SHIMPHY_ADDR_CNTL_0_CLK_GATE_CLK_667_ENABLE_DEFAULT 0x00000000
-
-/***************************************************************************
- *SHIMPHY_STATUS - SHIMPHY Status Register
- ***************************************************************************/
-/* SHIMPHY_ADDR_CNTL_0 :: SHIMPHY_STATUS :: reserved0 [31:01] */
-#define BCHP_SHIMPHY_ADDR_CNTL_0_SHIMPHY_STATUS_reserved0_MASK 0xfffffffe
-#define BCHP_SHIMPHY_ADDR_CNTL_0_SHIMPHY_STATUS_reserved0_SHIFT 1
-
-/* SHIMPHY_ADDR_CNTL_0 :: SHIMPHY_STATUS :: READY [00:00] */
-#define BCHP_SHIMPHY_ADDR_CNTL_0_SHIMPHY_STATUS_READY_MASK 0x00000001
-#define BCHP_SHIMPHY_ADDR_CNTL_0_SHIMPHY_STATUS_READY_SHIFT 0
-#define BCHP_SHIMPHY_ADDR_CNTL_0_SHIMPHY_STATUS_READY_DEFAULT 0x00000000
-
-/***************************************************************************
- *CMD_DATA_FIFO - Command and Data FIFO Status Register
- ***************************************************************************/
-/* SHIMPHY_ADDR_CNTL_0 :: CMD_DATA_FIFO :: reserved0 [31:26] */
-#define BCHP_SHIMPHY_ADDR_CNTL_0_CMD_DATA_FIFO_reserved0_MASK 0xfc000000
-#define BCHP_SHIMPHY_ADDR_CNTL_0_CMD_DATA_FIFO_reserved0_SHIFT 26
-
-/* SHIMPHY_ADDR_CNTL_0 :: CMD_DATA_FIFO :: FIFO_FULL [25:25] */
-#define BCHP_SHIMPHY_ADDR_CNTL_0_CMD_DATA_FIFO_FIFO_FULL_MASK 0x02000000
-#define BCHP_SHIMPHY_ADDR_CNTL_0_CMD_DATA_FIFO_FIFO_FULL_SHIFT 25
-
-/* SHIMPHY_ADDR_CNTL_0 :: CMD_DATA_FIFO :: FIFO_EMPTY [24:24] */
-#define BCHP_SHIMPHY_ADDR_CNTL_0_CMD_DATA_FIFO_FIFO_EMPTY_MASK 0x01000000
-#define BCHP_SHIMPHY_ADDR_CNTL_0_CMD_DATA_FIFO_FIFO_EMPTY_SHIFT 24
-
-/* SHIMPHY_ADDR_CNTL_0 :: CMD_DATA_FIFO :: reserved1 [23:10] */
-#define BCHP_SHIMPHY_ADDR_CNTL_0_CMD_DATA_FIFO_reserved1_MASK 0x00fffc00
-#define BCHP_SHIMPHY_ADDR_CNTL_0_CMD_DATA_FIFO_reserved1_SHIFT 10
-
-/* SHIMPHY_ADDR_CNTL_0 :: CMD_DATA_FIFO :: WR_PNTR [09:05] */
-#define BCHP_SHIMPHY_ADDR_CNTL_0_CMD_DATA_FIFO_WR_PNTR_MASK 0x000003e0
-#define BCHP_SHIMPHY_ADDR_CNTL_0_CMD_DATA_FIFO_WR_PNTR_SHIFT 5
-
-/* SHIMPHY_ADDR_CNTL_0 :: CMD_DATA_FIFO :: RD_PNTR [04:00] */
-#define BCHP_SHIMPHY_ADDR_CNTL_0_CMD_DATA_FIFO_RD_PNTR_MASK 0x0000001f
-#define BCHP_SHIMPHY_ADDR_CNTL_0_CMD_DATA_FIFO_RD_PNTR_SHIFT 0
-
-/***************************************************************************
- *RD_DATAPATH - Read Datapath Status Register
- ***************************************************************************/
-/* SHIMPHY_ADDR_CNTL_0 :: RD_DATAPATH :: reserved0 [31:10] */
-#define BCHP_SHIMPHY_ADDR_CNTL_0_RD_DATAPATH_reserved0_MASK 0xfffffc00
-#define BCHP_SHIMPHY_ADDR_CNTL_0_RD_DATAPATH_reserved0_SHIFT 10
-
-/* SHIMPHY_ADDR_CNTL_0 :: RD_DATAPATH :: WR_PNTR [09:05] */
-#define BCHP_SHIMPHY_ADDR_CNTL_0_RD_DATAPATH_WR_PNTR_MASK 0x000003e0
-#define BCHP_SHIMPHY_ADDR_CNTL_0_RD_DATAPATH_WR_PNTR_SHIFT 5
-
-/* SHIMPHY_ADDR_CNTL_0 :: RD_DATAPATH :: RD_PNTR [04:00] */
-#define BCHP_SHIMPHY_ADDR_CNTL_0_RD_DATAPATH_RD_PNTR_MASK 0x0000001f
-#define BCHP_SHIMPHY_ADDR_CNTL_0_RD_DATAPATH_RD_PNTR_SHIFT 0
-
-/***************************************************************************
- *FLAG_BUS - TP_OUT bus value Register
- ***************************************************************************/
-/* SHIMPHY_ADDR_CNTL_0 :: FLAG_BUS :: FLAG_BUS [31:00] */
-#define BCHP_SHIMPHY_ADDR_CNTL_0_FLAG_BUS_FLAG_BUS_MASK 0xffffffff
-#define BCHP_SHIMPHY_ADDR_CNTL_0_FLAG_BUS_FLAG_BUS_SHIFT 0
-
-/***************************************************************************
- *MISC - Miscellaneous Register
- ***************************************************************************/
-/* SHIMPHY_ADDR_CNTL_0 :: MISC :: reserved0 [31:20] */
-#define BCHP_SHIMPHY_ADDR_CNTL_0_MISC_reserved0_MASK 0xfff00000
-#define BCHP_SHIMPHY_ADDR_CNTL_0_MISC_reserved0_SHIFT 20
-
-/* SHIMPHY_ADDR_CNTL_0 :: MISC :: ASYNC_FIFO_AF_THRESHOLD [19:15] */
-#define BCHP_SHIMPHY_ADDR_CNTL_0_MISC_ASYNC_FIFO_AF_THRESHOLD_MASK 0x000f8000
-#define BCHP_SHIMPHY_ADDR_CNTL_0_MISC_ASYNC_FIFO_AF_THRESHOLD_SHIFT 15
-#define BCHP_SHIMPHY_ADDR_CNTL_0_MISC_ASYNC_FIFO_AF_THRESHOLD_DEFAULT 0x0000000a
-
-/* SHIMPHY_ADDR_CNTL_0 :: MISC :: reserved_for_eco1 [14:12] */
-#define BCHP_SHIMPHY_ADDR_CNTL_0_MISC_reserved_for_eco1_MASK 0x00007000
-#define BCHP_SHIMPHY_ADDR_CNTL_0_MISC_reserved_for_eco1_SHIFT 12
-#define BCHP_SHIMPHY_ADDR_CNTL_0_MISC_reserved_for_eco1_DEFAULT 0x00000000
-
-/* SHIMPHY_ADDR_CNTL_0 :: MISC :: DFI_ERROR_STATUS_CLR [11:11] */
-#define BCHP_SHIMPHY_ADDR_CNTL_0_MISC_DFI_ERROR_STATUS_CLR_MASK 0x00000800
-#define BCHP_SHIMPHY_ADDR_CNTL_0_MISC_DFI_ERROR_STATUS_CLR_SHIFT 11
-#define BCHP_SHIMPHY_ADDR_CNTL_0_MISC_DFI_ERROR_STATUS_CLR_DEFAULT 0x00000000
-
-/* SHIMPHY_ADDR_CNTL_0 :: MISC :: EDC_MONTIOR_STATUS_CLR [10:10] */
-#define BCHP_SHIMPHY_ADDR_CNTL_0_MISC_EDC_MONTIOR_STATUS_CLR_MASK 0x00000400
-#define BCHP_SHIMPHY_ADDR_CNTL_0_MISC_EDC_MONTIOR_STATUS_CLR_SHIFT 10
-#define BCHP_SHIMPHY_ADDR_CNTL_0_MISC_EDC_MONTIOR_STATUS_CLR_DEFAULT 0x00000000
-
-/* SHIMPHY_ADDR_CNTL_0 :: MISC :: VDL_MONITOR_STATUS_CLR [09:09] */
-#define BCHP_SHIMPHY_ADDR_CNTL_0_MISC_VDL_MONITOR_STATUS_CLR_MASK 0x00000200
-#define BCHP_SHIMPHY_ADDR_CNTL_0_MISC_VDL_MONITOR_STATUS_CLR_SHIFT 9
-#define BCHP_SHIMPHY_ADDR_CNTL_0_MISC_VDL_MONITOR_STATUS_CLR_DEFAULT 0x00000000
-
-/* SHIMPHY_ADDR_CNTL_0 :: MISC :: FUNC1 [08:08] */
-#define BCHP_SHIMPHY_ADDR_CNTL_0_MISC_FUNC1_MASK 0x00000100
-#define BCHP_SHIMPHY_ADDR_CNTL_0_MISC_FUNC1_SHIFT 8
-#define BCHP_SHIMPHY_ADDR_CNTL_0_MISC_FUNC1_DEFAULT 0x00000000
-
-/* SHIMPHY_ADDR_CNTL_0 :: MISC :: FUNC0 [07:07] */
-#define BCHP_SHIMPHY_ADDR_CNTL_0_MISC_FUNC0_MASK 0x00000080
-#define BCHP_SHIMPHY_ADDR_CNTL_0_MISC_FUNC0_SHIFT 7
-#define BCHP_SHIMPHY_ADDR_CNTL_0_MISC_FUNC0_DEFAULT 0x00000000
-
-/* SHIMPHY_ADDR_CNTL_0 :: MISC :: C2IO_INIT_RDY_OVR [06:06] */
-#define BCHP_SHIMPHY_ADDR_CNTL_0_MISC_C2IO_INIT_RDY_OVR_MASK 0x00000040
-#define BCHP_SHIMPHY_ADDR_CNTL_0_MISC_C2IO_INIT_RDY_OVR_SHIFT 6
-#define BCHP_SHIMPHY_ADDR_CNTL_0_MISC_C2IO_INIT_RDY_OVR_DEFAULT 0x00000000
-
-/* SHIMPHY_ADDR_CNTL_0 :: MISC :: RD_FIFO_HOLD_CLR [05:05] */
-#define BCHP_SHIMPHY_ADDR_CNTL_0_MISC_RD_FIFO_HOLD_CLR_MASK 0x00000020
-#define BCHP_SHIMPHY_ADDR_CNTL_0_MISC_RD_FIFO_HOLD_CLR_SHIFT 5
-#define BCHP_SHIMPHY_ADDR_CNTL_0_MISC_RD_FIFO_HOLD_CLR_DEFAULT 0x00000000
-
-/* SHIMPHY_ADDR_CNTL_0 :: MISC :: CMD_FIFO_HOLD_CLR [04:04] */
-#define BCHP_SHIMPHY_ADDR_CNTL_0_MISC_CMD_FIFO_HOLD_CLR_MASK 0x00000010
-#define BCHP_SHIMPHY_ADDR_CNTL_0_MISC_CMD_FIFO_HOLD_CLR_SHIFT 4
-#define BCHP_SHIMPHY_ADDR_CNTL_0_MISC_CMD_FIFO_HOLD_CLR_DEFAULT 0x00000000
-
-/* SHIMPHY_ADDR_CNTL_0 :: MISC :: reserved2 [03:01] */
-#define BCHP_SHIMPHY_ADDR_CNTL_0_MISC_reserved2_MASK 0x0000000e
-#define BCHP_SHIMPHY_ADDR_CNTL_0_MISC_reserved2_SHIFT 1
-
-/* SHIMPHY_ADDR_CNTL_0 :: MISC :: DATA_OVERRUN_CLR [00:00] */
-#define BCHP_SHIMPHY_ADDR_CNTL_0_MISC_DATA_OVERRUN_CLR_MASK 0x00000001
-#define BCHP_SHIMPHY_ADDR_CNTL_0_MISC_DATA_OVERRUN_CLR_SHIFT 0
-#define BCHP_SHIMPHY_ADDR_CNTL_0_MISC_DATA_OVERRUN_CLR_DEFAULT 0x00000000
-
-/***************************************************************************
- *SPARE0_RW - Spare register
- ***************************************************************************/
-/* SHIMPHY_ADDR_CNTL_0 :: SPARE0_RW :: reserved_for_eco0 [31:00] */
-#define BCHP_SHIMPHY_ADDR_CNTL_0_SPARE0_RW_reserved_for_eco0_MASK 0xffffffff
-#define BCHP_SHIMPHY_ADDR_CNTL_0_SPARE0_RW_reserved_for_eco0_SHIFT 0
-#define BCHP_SHIMPHY_ADDR_CNTL_0_SPARE0_RW_reserved_for_eco0_DEFAULT 0x00000000
-
-/***************************************************************************
- *SPARE1_RW - Spare register
- ***************************************************************************/
-/* SHIMPHY_ADDR_CNTL_0 :: SPARE1_RW :: reserved_for_eco0 [31:00] */
-#define BCHP_SHIMPHY_ADDR_CNTL_0_SPARE1_RW_reserved_for_eco0_MASK 0xffffffff
-#define BCHP_SHIMPHY_ADDR_CNTL_0_SPARE1_RW_reserved_for_eco0_SHIFT 0
-#define BCHP_SHIMPHY_ADDR_CNTL_0_SPARE1_RW_reserved_for_eco0_DEFAULT 0x00000000
-
-/***************************************************************************
- *SPARE0_RO - Spare register
- ***************************************************************************/
-/* SHIMPHY_ADDR_CNTL_0 :: SPARE0_RO :: reserved_for_eco0 [31:00] */
-#define BCHP_SHIMPHY_ADDR_CNTL_0_SPARE0_RO_reserved_for_eco0_MASK 0xffffffff
-#define BCHP_SHIMPHY_ADDR_CNTL_0_SPARE0_RO_reserved_for_eco0_SHIFT 0
-#define BCHP_SHIMPHY_ADDR_CNTL_0_SPARE0_RO_reserved_for_eco0_DEFAULT 0x00000000
-
-/***************************************************************************
- *SPARE1_RO - Spare register
- ***************************************************************************/
-/* SHIMPHY_ADDR_CNTL_0 :: SPARE1_RO :: reserved_for_eco0 [31:00] */
-#define BCHP_SHIMPHY_ADDR_CNTL_0_SPARE1_RO_reserved_for_eco0_MASK 0xffffffff
-#define BCHP_SHIMPHY_ADDR_CNTL_0_SPARE1_RO_reserved_for_eco0_SHIFT 0
-#define BCHP_SHIMPHY_ADDR_CNTL_0_SPARE1_RO_reserved_for_eco0_DEFAULT 0x00000000
-
-/***************************************************************************
- *DDR3_RESET_CNTRL - FORCE_DDR3_RESET Deassert Register
- ***************************************************************************/
-/* SHIMPHY_ADDR_CNTL_0 :: DDR3_RESET_CNTRL :: UNUSED [31:01] */
-#define BCHP_SHIMPHY_ADDR_CNTL_0_DDR3_RESET_CNTRL_UNUSED_MASK 0xfffffffe
-#define BCHP_SHIMPHY_ADDR_CNTL_0_DDR3_RESET_CNTRL_UNUSED_SHIFT 1
-#define BCHP_SHIMPHY_ADDR_CNTL_0_DDR3_RESET_CNTRL_UNUSED_DEFAULT 0x00000000
-
-/* SHIMPHY_ADDR_CNTL_0 :: DDR3_RESET_CNTRL :: FORCE_DDR3_RESET [00:00] */
-#define BCHP_SHIMPHY_ADDR_CNTL_0_DDR3_RESET_CNTRL_FORCE_DDR3_RESET_MASK 0x00000001
-#define BCHP_SHIMPHY_ADDR_CNTL_0_DDR3_RESET_CNTRL_FORCE_DDR3_RESET_SHIFT 0
-#define BCHP_SHIMPHY_ADDR_CNTL_0_DDR3_RESET_CNTRL_FORCE_DDR3_RESET_DEFAULT 0x00000001
-
-#endif /* #ifndef BCHP_SHIMPHY_ADDR_CNTL_0_H__ */
-
-/* End of File */
diff --git a/include/linux/brcmstb/7145a0/bchp_shimphy_addr_cntl_1.h b/include/linux/brcmstb/7145a0/bchp_shimphy_addr_cntl_1.h
deleted file mode 100644
index 7f53189..0000000
--- a/include/linux/brcmstb/7145a0/bchp_shimphy_addr_cntl_1.h
+++ /dev/null
@@ -1,547 +0,0 @@
-/***************************************************************************
- * Copyright (c) 1999-2013, Broadcom Corporation
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
- *
- * Module Description:
- * DO NOT EDIT THIS FILE DIRECTLY
- *
- * This module was generated magically with RDB from a source description
- * file. You must edit the source file for changes to be made to this file.
- *
- *
- * Date: Generated on Sat Apr 6 03:07:49 2013
- * MD5 Checksum d41d8cd98f00b204e9800998ecf8427e
- *
- * Compiled with: RDB Utility combo_header.pl
- * RDB Parser 3.0
- * unknown unknown
- * Perl Interpreter 5.008008
- * Operating System linux
- *
- * Revision History:
- *
- * $brcm_Log: $
- *
- ***************************************************************************/
-
-#ifndef BCHP_SHIMPHY_ADDR_CNTL_1_H__
-#define BCHP_SHIMPHY_ADDR_CNTL_1_H__
-
-/***************************************************************************
- *SHIMPHY_ADDR_CNTL_1 - 1 DDR SHIMPHY Control Registers
- ***************************************************************************/
-#define BCHP_SHIMPHY_ADDR_CNTL_1_CONFIG 0x203c8000 /* SHIMPHY Config register */
-#define BCHP_SHIMPHY_ADDR_CNTL_1_SHIMPHY_REV_ID 0x203c8004 /* SHIMPHY Revision ID Register. */
-#define BCHP_SHIMPHY_ADDR_CNTL_1_RESET 0x203c8008 /* DDR soft reset register */
-#define BCHP_SHIMPHY_ADDR_CNTL_1_DFI_CONTROL 0x203c8038 /* DFI Interface Control Register */
-#define BCHP_SHIMPHY_ADDR_CNTL_1_DFI_STATUS 0x203c803c /* DFI Interface Status Register */
-#define BCHP_SHIMPHY_ADDR_CNTL_1_PHY_LPM_STAT 0x203c8040 /* PHY Power Control Status Register */
-#define BCHP_SHIMPHY_ADDR_CNTL_1_IDLE_POWER_SAVING 0x203c8048 /* DDR PHY Idle power saving Control register */
-#define BCHP_SHIMPHY_ADDR_CNTL_1_PHY_STANDBY_EXIT 0x203c804c /* DDR PHY standby exit register */
-#define BCHP_SHIMPHY_ADDR_CNTL_1_ANALOG_BYPASS_CNTRL 0x203c806c /* Analog macro register bypass control */
-#define BCHP_SHIMPHY_ADDR_CNTL_1_DDR_PLL_EXT_CLKSEL 0x203c8070 /* DDR PLL external clock select register */
-#define BCHP_SHIMPHY_ADDR_CNTL_1_TEST_MODE_CNTRL_REG 0x203c8074 /* SHIMPHY testport control register */
-#define BCHP_SHIMPHY_ADDR_CNTL_1_DISABLE_CHIP_BYPASS_PLL 0x203c807c /* DDR bypass pll mode disable register. */
-#define BCHP_SHIMPHY_ADDR_CNTL_1_VECTOR_MODE_CLK_SEL 0x203c8088 /* DDR VECTOR PLL bypass mode clock select */
-#define BCHP_SHIMPHY_ADDR_CNTL_1_DDR_PAD_CNTRL 0x203c808c /* DDR Pad control register */
-#define BCHP_SHIMPHY_ADDR_CNTL_1_CLK_GATE 0x203c8098 /* CLK_667_ENABLE Register */
-#define BCHP_SHIMPHY_ADDR_CNTL_1_SHIMPHY_STATUS 0x203c809c /* SHIMPHY Status Register */
-#define BCHP_SHIMPHY_ADDR_CNTL_1_CMD_DATA_FIFO 0x203c8028 /* Command and Data FIFO Status Register */
-#define BCHP_SHIMPHY_ADDR_CNTL_1_RD_DATAPATH 0x203c802c /* Read Datapath Status Register */
-#define BCHP_SHIMPHY_ADDR_CNTL_1_FLAG_BUS 0x203c8030 /* TP_OUT bus value Register */
-#define BCHP_SHIMPHY_ADDR_CNTL_1_MISC 0x203c8034 /* Miscellaneous Register */
-#define BCHP_SHIMPHY_ADDR_CNTL_1_SPARE0_RW 0x203c80a4 /* Spare register */
-#define BCHP_SHIMPHY_ADDR_CNTL_1_SPARE1_RW 0x203c80a8 /* Spare register */
-#define BCHP_SHIMPHY_ADDR_CNTL_1_SPARE0_RO 0x203c80ac /* Spare register */
-#define BCHP_SHIMPHY_ADDR_CNTL_1_SPARE1_RO 0x203c80b0 /* Spare register */
-#define BCHP_SHIMPHY_ADDR_CNTL_1_DDR3_RESET_CNTRL 0x203c80b4 /* FORCE_DDR3_RESET Deassert Register */
-
-/***************************************************************************
- *CONFIG - SHIMPHY Config register
- ***************************************************************************/
-/* SHIMPHY_ADDR_CNTL_1 :: CONFIG :: DFI_CLK_DISABLE [31:31] */
-#define BCHP_SHIMPHY_ADDR_CNTL_1_CONFIG_DFI_CLK_DISABLE_MASK 0x80000000
-#define BCHP_SHIMPHY_ADDR_CNTL_1_CONFIG_DFI_CLK_DISABLE_SHIFT 31
-#define BCHP_SHIMPHY_ADDR_CNTL_1_CONFIG_DFI_CLK_DISABLE_DEFAULT 0x00000000
-
-/* SHIMPHY_ADDR_CNTL_1 :: CONFIG :: DRAM_NOP_OR_DSEL_CMD [30:30] */
-#define BCHP_SHIMPHY_ADDR_CNTL_1_CONFIG_DRAM_NOP_OR_DSEL_CMD_MASK 0x40000000
-#define BCHP_SHIMPHY_ADDR_CNTL_1_CONFIG_DRAM_NOP_OR_DSEL_CMD_SHIFT 30
-#define BCHP_SHIMPHY_ADDR_CNTL_1_CONFIG_DRAM_NOP_OR_DSEL_CMD_DEFAULT 0x00000000
-
-/* SHIMPHY_ADDR_CNTL_1 :: CONFIG :: LAST_RD_STRETCH [29:29] */
-#define BCHP_SHIMPHY_ADDR_CNTL_1_CONFIG_LAST_RD_STRETCH_MASK 0x20000000
-#define BCHP_SHIMPHY_ADDR_CNTL_1_CONFIG_LAST_RD_STRETCH_SHIFT 29
-#define BCHP_SHIMPHY_ADDR_CNTL_1_CONFIG_LAST_RD_STRETCH_DEFAULT 0x00000000
-
-/* SHIMPHY_ADDR_CNTL_1 :: CONFIG :: reserved0 [28:24] */
-#define BCHP_SHIMPHY_ADDR_CNTL_1_CONFIG_reserved0_MASK 0x1f000000
-#define BCHP_SHIMPHY_ADDR_CNTL_1_CONFIG_reserved0_SHIFT 24
-
-/* SHIMPHY_ADDR_CNTL_1 :: CONFIG :: LAST_READ_LATENCY [23:16] */
-#define BCHP_SHIMPHY_ADDR_CNTL_1_CONFIG_LAST_READ_LATENCY_MASK 0x00ff0000
-#define BCHP_SHIMPHY_ADDR_CNTL_1_CONFIG_LAST_READ_LATENCY_SHIFT 16
-#define BCHP_SHIMPHY_ADDR_CNTL_1_CONFIG_LAST_READ_LATENCY_DEFAULT 0x0000000b
-
-/* SHIMPHY_ADDR_CNTL_1 :: CONFIG :: READ_LATENCY [15:08] */
-#define BCHP_SHIMPHY_ADDR_CNTL_1_CONFIG_READ_LATENCY_MASK 0x0000ff00
-#define BCHP_SHIMPHY_ADDR_CNTL_1_CONFIG_READ_LATENCY_SHIFT 8
-#define BCHP_SHIMPHY_ADDR_CNTL_1_CONFIG_READ_LATENCY_DEFAULT 0x00000007
-
-/* SHIMPHY_ADDR_CNTL_1 :: CONFIG :: reserved1 [07:06] */
-#define BCHP_SHIMPHY_ADDR_CNTL_1_CONFIG_reserved1_MASK 0x000000c0
-#define BCHP_SHIMPHY_ADDR_CNTL_1_CONFIG_reserved1_SHIFT 6
-
-/* SHIMPHY_ADDR_CNTL_1 :: CONFIG :: WRITE_LATENCY [05:00] */
-#define BCHP_SHIMPHY_ADDR_CNTL_1_CONFIG_WRITE_LATENCY_MASK 0x0000003f
-#define BCHP_SHIMPHY_ADDR_CNTL_1_CONFIG_WRITE_LATENCY_SHIFT 0
-#define BCHP_SHIMPHY_ADDR_CNTL_1_CONFIG_WRITE_LATENCY_DEFAULT 0x0000000e
-
-/***************************************************************************
- *SHIMPHY_REV_ID - SHIMPHY Revision ID Register.
- ***************************************************************************/
-/* SHIMPHY_ADDR_CNTL_1 :: SHIMPHY_REV_ID :: reserved0 [31:16] */
-#define BCHP_SHIMPHY_ADDR_CNTL_1_SHIMPHY_REV_ID_reserved0_MASK 0xffff0000
-#define BCHP_SHIMPHY_ADDR_CNTL_1_SHIMPHY_REV_ID_reserved0_SHIFT 16
-
-/* SHIMPHY_ADDR_CNTL_1 :: SHIMPHY_REV_ID :: MAJOR_ID [15:08] */
-#define BCHP_SHIMPHY_ADDR_CNTL_1_SHIMPHY_REV_ID_MAJOR_ID_MASK 0x0000ff00
-#define BCHP_SHIMPHY_ADDR_CNTL_1_SHIMPHY_REV_ID_MAJOR_ID_SHIFT 8
-#define BCHP_SHIMPHY_ADDR_CNTL_1_SHIMPHY_REV_ID_MAJOR_ID_DEFAULT 0x00000001
-
-/* SHIMPHY_ADDR_CNTL_1 :: SHIMPHY_REV_ID :: MINOR_ID [07:00] */
-#define BCHP_SHIMPHY_ADDR_CNTL_1_SHIMPHY_REV_ID_MINOR_ID_MASK 0x000000ff
-#define BCHP_SHIMPHY_ADDR_CNTL_1_SHIMPHY_REV_ID_MINOR_ID_SHIFT 0
-#define BCHP_SHIMPHY_ADDR_CNTL_1_SHIMPHY_REV_ID_MINOR_ID_DEFAULT 0x00000000
-
-/***************************************************************************
- *RESET - DDR soft reset register
- ***************************************************************************/
-/* SHIMPHY_ADDR_CNTL_1 :: RESET :: reserved0 [31:03] */
-#define BCHP_SHIMPHY_ADDR_CNTL_1_RESET_reserved0_MASK 0xfffffff8
-#define BCHP_SHIMPHY_ADDR_CNTL_1_RESET_reserved0_SHIFT 3
-
-/* SHIMPHY_ADDR_CNTL_1 :: RESET :: DATAPATH_216_RESET [02:02] */
-#define BCHP_SHIMPHY_ADDR_CNTL_1_RESET_DATAPATH_216_RESET_MASK 0x00000004
-#define BCHP_SHIMPHY_ADDR_CNTL_1_RESET_DATAPATH_216_RESET_SHIFT 2
-#define BCHP_SHIMPHY_ADDR_CNTL_1_RESET_DATAPATH_216_RESET_DEFAULT 0x00000000
-
-/* SHIMPHY_ADDR_CNTL_1 :: RESET :: DATAPATH_DDR_RESET [01:01] */
-#define BCHP_SHIMPHY_ADDR_CNTL_1_RESET_DATAPATH_DDR_RESET_MASK 0x00000002
-#define BCHP_SHIMPHY_ADDR_CNTL_1_RESET_DATAPATH_DDR_RESET_SHIFT 1
-#define BCHP_SHIMPHY_ADDR_CNTL_1_RESET_DATAPATH_DDR_RESET_DEFAULT 0x00000000
-
-/* SHIMPHY_ADDR_CNTL_1 :: RESET :: PHY_PWRUP_RSB [00:00] */
-#define BCHP_SHIMPHY_ADDR_CNTL_1_RESET_PHY_PWRUP_RSB_MASK 0x00000001
-#define BCHP_SHIMPHY_ADDR_CNTL_1_RESET_PHY_PWRUP_RSB_SHIFT 0
-#define BCHP_SHIMPHY_ADDR_CNTL_1_RESET_PHY_PWRUP_RSB_DEFAULT 0x00000000
-
-/***************************************************************************
- *DFI_CONTROL - DFI Interface Control Register
- ***************************************************************************/
-/* SHIMPHY_ADDR_CNTL_1 :: DFI_CONTROL :: reserved0 [31:10] */
-#define BCHP_SHIMPHY_ADDR_CNTL_1_DFI_CONTROL_reserved0_MASK 0xfffffc00
-#define BCHP_SHIMPHY_ADDR_CNTL_1_DFI_CONTROL_reserved0_SHIFT 10
-
-/* SHIMPHY_ADDR_CNTL_1 :: DFI_CONTROL :: TM2_MUX_SEL [09:09] */
-#define BCHP_SHIMPHY_ADDR_CNTL_1_DFI_CONTROL_TM2_MUX_SEL_MASK 0x00000200
-#define BCHP_SHIMPHY_ADDR_CNTL_1_DFI_CONTROL_TM2_MUX_SEL_SHIFT 9
-#define BCHP_SHIMPHY_ADDR_CNTL_1_DFI_CONTROL_TM2_MUX_SEL_DEFAULT 0x00000000
-
-/* SHIMPHY_ADDR_CNTL_1 :: DFI_CONTROL :: PHY_PLL_HOLD_CH [08:08] */
-#define BCHP_SHIMPHY_ADDR_CNTL_1_DFI_CONTROL_PHY_PLL_HOLD_CH_MASK 0x00000100
-#define BCHP_SHIMPHY_ADDR_CNTL_1_DFI_CONTROL_PHY_PLL_HOLD_CH_SHIFT 8
-#define BCHP_SHIMPHY_ADDR_CNTL_1_DFI_CONTROL_PHY_PLL_HOLD_CH_DEFAULT 0x00000000
-
-/* SHIMPHY_ADDR_CNTL_1 :: DFI_CONTROL :: reserved1 [07:01] */
-#define BCHP_SHIMPHY_ADDR_CNTL_1_DFI_CONTROL_reserved1_MASK 0x000000fe
-#define BCHP_SHIMPHY_ADDR_CNTL_1_DFI_CONTROL_reserved1_SHIFT 1
-
-/* SHIMPHY_ADDR_CNTL_1 :: DFI_CONTROL :: LATCH_FIRST_ERROR [00:00] */
-#define BCHP_SHIMPHY_ADDR_CNTL_1_DFI_CONTROL_LATCH_FIRST_ERROR_MASK 0x00000001
-#define BCHP_SHIMPHY_ADDR_CNTL_1_DFI_CONTROL_LATCH_FIRST_ERROR_SHIFT 0
-#define BCHP_SHIMPHY_ADDR_CNTL_1_DFI_CONTROL_LATCH_FIRST_ERROR_DEFAULT 0x00000001
-
-/***************************************************************************
- *DFI_STATUS - DFI Interface Status Register
- ***************************************************************************/
-/* SHIMPHY_ADDR_CNTL_1 :: DFI_STATUS :: reserved0 [31:18] */
-#define BCHP_SHIMPHY_ADDR_CNTL_1_DFI_STATUS_reserved0_MASK 0xfffc0000
-#define BCHP_SHIMPHY_ADDR_CNTL_1_DFI_STATUS_reserved0_SHIFT 18
-
-/* SHIMPHY_ADDR_CNTL_1 :: DFI_STATUS :: PHY_EDC_MONITOR_STATUS [17:17] */
-#define BCHP_SHIMPHY_ADDR_CNTL_1_DFI_STATUS_PHY_EDC_MONITOR_STATUS_MASK 0x00020000
-#define BCHP_SHIMPHY_ADDR_CNTL_1_DFI_STATUS_PHY_EDC_MONITOR_STATUS_SHIFT 17
-#define BCHP_SHIMPHY_ADDR_CNTL_1_DFI_STATUS_PHY_EDC_MONITOR_STATUS_DEFAULT 0x00000000
-
-/* SHIMPHY_ADDR_CNTL_1 :: DFI_STATUS :: PHY_VDL_MONITOR_STATUS [16:16] */
-#define BCHP_SHIMPHY_ADDR_CNTL_1_DFI_STATUS_PHY_VDL_MONITOR_STATUS_MASK 0x00010000
-#define BCHP_SHIMPHY_ADDR_CNTL_1_DFI_STATUS_PHY_VDL_MONITOR_STATUS_SHIFT 16
-#define BCHP_SHIMPHY_ADDR_CNTL_1_DFI_STATUS_PHY_VDL_MONITOR_STATUS_DEFAULT 0x00000000
-
-/* SHIMPHY_ADDR_CNTL_1 :: DFI_STATUS :: reserved1 [15:09] */
-#define BCHP_SHIMPHY_ADDR_CNTL_1_DFI_STATUS_reserved1_MASK 0x0000fe00
-#define BCHP_SHIMPHY_ADDR_CNTL_1_DFI_STATUS_reserved1_SHIFT 9
-
-/* SHIMPHY_ADDR_CNTL_1 :: DFI_STATUS :: ERROR_VALID [08:08] */
-#define BCHP_SHIMPHY_ADDR_CNTL_1_DFI_STATUS_ERROR_VALID_MASK 0x00000100
-#define BCHP_SHIMPHY_ADDR_CNTL_1_DFI_STATUS_ERROR_VALID_SHIFT 8
-#define BCHP_SHIMPHY_ADDR_CNTL_1_DFI_STATUS_ERROR_VALID_DEFAULT 0x00000000
-
-/* SHIMPHY_ADDR_CNTL_1 :: DFI_STATUS :: reserved2 [07:04] */
-#define BCHP_SHIMPHY_ADDR_CNTL_1_DFI_STATUS_reserved2_MASK 0x000000f0
-#define BCHP_SHIMPHY_ADDR_CNTL_1_DFI_STATUS_reserved2_SHIFT 4
-
-/* SHIMPHY_ADDR_CNTL_1 :: DFI_STATUS :: ERROR_INFO [03:00] */
-#define BCHP_SHIMPHY_ADDR_CNTL_1_DFI_STATUS_ERROR_INFO_MASK 0x0000000f
-#define BCHP_SHIMPHY_ADDR_CNTL_1_DFI_STATUS_ERROR_INFO_SHIFT 0
-#define BCHP_SHIMPHY_ADDR_CNTL_1_DFI_STATUS_ERROR_INFO_DEFAULT 0x00000000
-
-/***************************************************************************
- *PHY_LPM_STAT - PHY Power Control Status Register
- ***************************************************************************/
-/* SHIMPHY_ADDR_CNTL_1 :: PHY_LPM_STAT :: reserved0 [31:10] */
-#define BCHP_SHIMPHY_ADDR_CNTL_1_PHY_LPM_STAT_reserved0_MASK 0xfffffc00
-#define BCHP_SHIMPHY_ADDR_CNTL_1_PHY_LPM_STAT_reserved0_SHIFT 10
-
-/* SHIMPHY_ADDR_CNTL_1 :: PHY_LPM_STAT :: PHY_RBUS_IS_IDLE [09:09] */
-#define BCHP_SHIMPHY_ADDR_CNTL_1_PHY_LPM_STAT_PHY_RBUS_IS_IDLE_MASK 0x00000200
-#define BCHP_SHIMPHY_ADDR_CNTL_1_PHY_LPM_STAT_PHY_RBUS_IS_IDLE_SHIFT 9
-#define BCHP_SHIMPHY_ADDR_CNTL_1_PHY_LPM_STAT_PHY_RBUS_IS_IDLE_DEFAULT 0x00000000
-
-/* SHIMPHY_ADDR_CNTL_1 :: PHY_LPM_STAT :: PHY_IS_IDLE [08:08] */
-#define BCHP_SHIMPHY_ADDR_CNTL_1_PHY_LPM_STAT_PHY_IS_IDLE_MASK 0x00000100
-#define BCHP_SHIMPHY_ADDR_CNTL_1_PHY_LPM_STAT_PHY_IS_IDLE_SHIFT 8
-#define BCHP_SHIMPHY_ADDR_CNTL_1_PHY_LPM_STAT_PHY_IS_IDLE_DEFAULT 0x00000000
-
-/* SHIMPHY_ADDR_CNTL_1 :: PHY_LPM_STAT :: reserved1 [07:00] */
-#define BCHP_SHIMPHY_ADDR_CNTL_1_PHY_LPM_STAT_reserved1_MASK 0x000000ff
-#define BCHP_SHIMPHY_ADDR_CNTL_1_PHY_LPM_STAT_reserved1_SHIFT 0
-
-/***************************************************************************
- *IDLE_POWER_SAVING - DDR PHY Idle power saving Control register
- ***************************************************************************/
-/* SHIMPHY_ADDR_CNTL_1 :: IDLE_POWER_SAVING :: reserved0 [31:06] */
-#define BCHP_SHIMPHY_ADDR_CNTL_1_IDLE_POWER_SAVING_reserved0_MASK 0xffffffc0
-#define BCHP_SHIMPHY_ADDR_CNTL_1_IDLE_POWER_SAVING_reserved0_SHIFT 6
-
-/* SHIMPHY_ADDR_CNTL_1 :: IDLE_POWER_SAVING :: PhyAddrCntl [05:04] */
-#define BCHP_SHIMPHY_ADDR_CNTL_1_IDLE_POWER_SAVING_PhyAddrCntl_MASK 0x00000030
-#define BCHP_SHIMPHY_ADDR_CNTL_1_IDLE_POWER_SAVING_PhyAddrCntl_SHIFT 4
-#define BCHP_SHIMPHY_ADDR_CNTL_1_IDLE_POWER_SAVING_PhyAddrCntl_DEFAULT 0x00000000
-
-/* SHIMPHY_ADDR_CNTL_1 :: IDLE_POWER_SAVING :: ByteLane3 [03:03] */
-#define BCHP_SHIMPHY_ADDR_CNTL_1_IDLE_POWER_SAVING_ByteLane3_MASK 0x00000008
-#define BCHP_SHIMPHY_ADDR_CNTL_1_IDLE_POWER_SAVING_ByteLane3_SHIFT 3
-#define BCHP_SHIMPHY_ADDR_CNTL_1_IDLE_POWER_SAVING_ByteLane3_DEFAULT 0x00000000
-
-/* SHIMPHY_ADDR_CNTL_1 :: IDLE_POWER_SAVING :: ByteLane2 [02:02] */
-#define BCHP_SHIMPHY_ADDR_CNTL_1_IDLE_POWER_SAVING_ByteLane2_MASK 0x00000004
-#define BCHP_SHIMPHY_ADDR_CNTL_1_IDLE_POWER_SAVING_ByteLane2_SHIFT 2
-#define BCHP_SHIMPHY_ADDR_CNTL_1_IDLE_POWER_SAVING_ByteLane2_DEFAULT 0x00000000
-
-/* SHIMPHY_ADDR_CNTL_1 :: IDLE_POWER_SAVING :: ByteLane1 [01:01] */
-#define BCHP_SHIMPHY_ADDR_CNTL_1_IDLE_POWER_SAVING_ByteLane1_MASK 0x00000002
-#define BCHP_SHIMPHY_ADDR_CNTL_1_IDLE_POWER_SAVING_ByteLane1_SHIFT 1
-#define BCHP_SHIMPHY_ADDR_CNTL_1_IDLE_POWER_SAVING_ByteLane1_DEFAULT 0x00000000
-
-/* SHIMPHY_ADDR_CNTL_1 :: IDLE_POWER_SAVING :: ByteLane0 [00:00] */
-#define BCHP_SHIMPHY_ADDR_CNTL_1_IDLE_POWER_SAVING_ByteLane0_MASK 0x00000001
-#define BCHP_SHIMPHY_ADDR_CNTL_1_IDLE_POWER_SAVING_ByteLane0_SHIFT 0
-#define BCHP_SHIMPHY_ADDR_CNTL_1_IDLE_POWER_SAVING_ByteLane0_DEFAULT 0x00000000
-
-/***************************************************************************
- *PHY_STANDBY_EXIT - DDR PHY standby exit register
- ***************************************************************************/
-/* SHIMPHY_ADDR_CNTL_1 :: PHY_STANDBY_EXIT :: reserved0 [31:01] */
-#define BCHP_SHIMPHY_ADDR_CNTL_1_PHY_STANDBY_EXIT_reserved0_MASK 0xfffffffe
-#define BCHP_SHIMPHY_ADDR_CNTL_1_PHY_STANDBY_EXIT_reserved0_SHIFT 1
-
-/* SHIMPHY_ADDR_CNTL_1 :: PHY_STANDBY_EXIT :: ENABLE [00:00] */
-#define BCHP_SHIMPHY_ADDR_CNTL_1_PHY_STANDBY_EXIT_ENABLE_MASK 0x00000001
-#define BCHP_SHIMPHY_ADDR_CNTL_1_PHY_STANDBY_EXIT_ENABLE_SHIFT 0
-#define BCHP_SHIMPHY_ADDR_CNTL_1_PHY_STANDBY_EXIT_ENABLE_DEFAULT 0x00000001
-
-/***************************************************************************
- *ANALOG_BYPASS_CNTRL - Analog macro register bypass control
- ***************************************************************************/
-/* SHIMPHY_ADDR_CNTL_1 :: ANALOG_BYPASS_CNTRL :: reserved0 [31:01] */
-#define BCHP_SHIMPHY_ADDR_CNTL_1_ANALOG_BYPASS_CNTRL_reserved0_MASK 0xfffffffe
-#define BCHP_SHIMPHY_ADDR_CNTL_1_ANALOG_BYPASS_CNTRL_reserved0_SHIFT 1
-
-/* SHIMPHY_ADDR_CNTL_1 :: ANALOG_BYPASS_CNTRL :: BYPASS_PLL [00:00] */
-#define BCHP_SHIMPHY_ADDR_CNTL_1_ANALOG_BYPASS_CNTRL_BYPASS_PLL_MASK 0x00000001
-#define BCHP_SHIMPHY_ADDR_CNTL_1_ANALOG_BYPASS_CNTRL_BYPASS_PLL_SHIFT 0
-#define BCHP_SHIMPHY_ADDR_CNTL_1_ANALOG_BYPASS_CNTRL_BYPASS_PLL_DEFAULT 0x00000000
-
-/***************************************************************************
- *DDR_PLL_EXT_CLKSEL - DDR PLL external clock select register
- ***************************************************************************/
-/* SHIMPHY_ADDR_CNTL_1 :: DDR_PLL_EXT_CLKSEL :: reserved0 [31:01] */
-#define BCHP_SHIMPHY_ADDR_CNTL_1_DDR_PLL_EXT_CLKSEL_reserved0_MASK 0xfffffffe
-#define BCHP_SHIMPHY_ADDR_CNTL_1_DDR_PLL_EXT_CLKSEL_reserved0_SHIFT 1
-
-/* SHIMPHY_ADDR_CNTL_1 :: DDR_PLL_EXT_CLKSEL :: EXT_CLK_SEL [00:00] */
-#define BCHP_SHIMPHY_ADDR_CNTL_1_DDR_PLL_EXT_CLKSEL_EXT_CLK_SEL_MASK 0x00000001
-#define BCHP_SHIMPHY_ADDR_CNTL_1_DDR_PLL_EXT_CLKSEL_EXT_CLK_SEL_SHIFT 0
-#define BCHP_SHIMPHY_ADDR_CNTL_1_DDR_PLL_EXT_CLKSEL_EXT_CLK_SEL_DEFAULT 0x00000000
-
-/***************************************************************************
- *TEST_MODE_CNTRL_REG - SHIMPHY testport control register
- ***************************************************************************/
-/* SHIMPHY_ADDR_CNTL_1 :: TEST_MODE_CNTRL_REG :: reserved_for_eco0 [31:00] */
-#define BCHP_SHIMPHY_ADDR_CNTL_1_TEST_MODE_CNTRL_REG_reserved_for_eco0_MASK 0xffffffff
-#define BCHP_SHIMPHY_ADDR_CNTL_1_TEST_MODE_CNTRL_REG_reserved_for_eco0_SHIFT 0
-#define BCHP_SHIMPHY_ADDR_CNTL_1_TEST_MODE_CNTRL_REG_reserved_for_eco0_DEFAULT 0x00000000
-
-/***************************************************************************
- *DISABLE_CHIP_BYPASS_PLL - DDR bypass pll mode disable register.
- ***************************************************************************/
-/* SHIMPHY_ADDR_CNTL_1 :: DISABLE_CHIP_BYPASS_PLL :: reserved0 [31:01] */
-#define BCHP_SHIMPHY_ADDR_CNTL_1_DISABLE_CHIP_BYPASS_PLL_reserved0_MASK 0xfffffffe
-#define BCHP_SHIMPHY_ADDR_CNTL_1_DISABLE_CHIP_BYPASS_PLL_reserved0_SHIFT 1
-
-/* SHIMPHY_ADDR_CNTL_1 :: DISABLE_CHIP_BYPASS_PLL :: DISABLE_BYPASS_PLL [00:00] */
-#define BCHP_SHIMPHY_ADDR_CNTL_1_DISABLE_CHIP_BYPASS_PLL_DISABLE_BYPASS_PLL_MASK 0x00000001
-#define BCHP_SHIMPHY_ADDR_CNTL_1_DISABLE_CHIP_BYPASS_PLL_DISABLE_BYPASS_PLL_SHIFT 0
-#define BCHP_SHIMPHY_ADDR_CNTL_1_DISABLE_CHIP_BYPASS_PLL_DISABLE_BYPASS_PLL_DEFAULT 0x00000000
-
-/***************************************************************************
- *VECTOR_MODE_CLK_SEL - DDR VECTOR PLL bypass mode clock select
- ***************************************************************************/
-/* SHIMPHY_ADDR_CNTL_1 :: VECTOR_MODE_CLK_SEL :: reserved0 [31:01] */
-#define BCHP_SHIMPHY_ADDR_CNTL_1_VECTOR_MODE_CLK_SEL_reserved0_MASK 0xfffffffe
-#define BCHP_SHIMPHY_ADDR_CNTL_1_VECTOR_MODE_CLK_SEL_reserved0_SHIFT 1
-
-/* SHIMPHY_ADDR_CNTL_1 :: VECTOR_MODE_CLK_SEL :: SEL [00:00] */
-#define BCHP_SHIMPHY_ADDR_CNTL_1_VECTOR_MODE_CLK_SEL_SEL_MASK 0x00000001
-#define BCHP_SHIMPHY_ADDR_CNTL_1_VECTOR_MODE_CLK_SEL_SEL_SHIFT 0
-#define BCHP_SHIMPHY_ADDR_CNTL_1_VECTOR_MODE_CLK_SEL_SEL_DEFAULT 0x00000000
-
-/***************************************************************************
- *DDR_PAD_CNTRL - DDR Pad control register
- ***************************************************************************/
-/* SHIMPHY_ADDR_CNTL_1 :: DDR_PAD_CNTRL :: reserved0 [31:07] */
-#define BCHP_SHIMPHY_ADDR_CNTL_1_DDR_PAD_CNTRL_reserved0_MASK 0xffffff80
-#define BCHP_SHIMPHY_ADDR_CNTL_1_DDR_PAD_CNTRL_reserved0_SHIFT 7
-
-/* SHIMPHY_ADDR_CNTL_1 :: DDR_PAD_CNTRL :: IDDQ_MODE_ON_SELFREF [06:06] */
-#define BCHP_SHIMPHY_ADDR_CNTL_1_DDR_PAD_CNTRL_IDDQ_MODE_ON_SELFREF_MASK 0x00000040
-#define BCHP_SHIMPHY_ADDR_CNTL_1_DDR_PAD_CNTRL_IDDQ_MODE_ON_SELFREF_SHIFT 6
-#define BCHP_SHIMPHY_ADDR_CNTL_1_DDR_PAD_CNTRL_IDDQ_MODE_ON_SELFREF_DEFAULT 0x00000000
-
-/* SHIMPHY_ADDR_CNTL_1 :: DDR_PAD_CNTRL :: PHY_IDLE_ENABLE [05:05] */
-#define BCHP_SHIMPHY_ADDR_CNTL_1_DDR_PAD_CNTRL_PHY_IDLE_ENABLE_MASK 0x00000020
-#define BCHP_SHIMPHY_ADDR_CNTL_1_DDR_PAD_CNTRL_PHY_IDLE_ENABLE_SHIFT 5
-#define BCHP_SHIMPHY_ADDR_CNTL_1_DDR_PAD_CNTRL_PHY_IDLE_ENABLE_DEFAULT 0x00000000
-
-/* SHIMPHY_ADDR_CNTL_1 :: DDR_PAD_CNTRL :: HIZ_ON_SELFREF [04:04] */
-#define BCHP_SHIMPHY_ADDR_CNTL_1_DDR_PAD_CNTRL_HIZ_ON_SELFREF_MASK 0x00000010
-#define BCHP_SHIMPHY_ADDR_CNTL_1_DDR_PAD_CNTRL_HIZ_ON_SELFREF_SHIFT 4
-#define BCHP_SHIMPHY_ADDR_CNTL_1_DDR_PAD_CNTRL_HIZ_ON_SELFREF_DEFAULT 0x00000000
-
-/* SHIMPHY_ADDR_CNTL_1 :: DDR_PAD_CNTRL :: CNTRL [03:00] */
-#define BCHP_SHIMPHY_ADDR_CNTL_1_DDR_PAD_CNTRL_CNTRL_MASK 0x0000000f
-#define BCHP_SHIMPHY_ADDR_CNTL_1_DDR_PAD_CNTRL_CNTRL_SHIFT 0
-#define BCHP_SHIMPHY_ADDR_CNTL_1_DDR_PAD_CNTRL_CNTRL_DEFAULT 0x00000000
-
-/***************************************************************************
- *CLK_GATE - CLK_667_ENABLE Register
- ***************************************************************************/
-/* SHIMPHY_ADDR_CNTL_1 :: CLK_GATE :: UNUSED [31:01] */
-#define BCHP_SHIMPHY_ADDR_CNTL_1_CLK_GATE_UNUSED_MASK 0xfffffffe
-#define BCHP_SHIMPHY_ADDR_CNTL_1_CLK_GATE_UNUSED_SHIFT 1
-#define BCHP_SHIMPHY_ADDR_CNTL_1_CLK_GATE_UNUSED_DEFAULT 0x00000000
-
-/* SHIMPHY_ADDR_CNTL_1 :: CLK_GATE :: CLK_667_ENABLE [00:00] */
-#define BCHP_SHIMPHY_ADDR_CNTL_1_CLK_GATE_CLK_667_ENABLE_MASK 0x00000001
-#define BCHP_SHIMPHY_ADDR_CNTL_1_CLK_GATE_CLK_667_ENABLE_SHIFT 0
-#define BCHP_SHIMPHY_ADDR_CNTL_1_CLK_GATE_CLK_667_ENABLE_DEFAULT 0x00000000
-
-/***************************************************************************
- *SHIMPHY_STATUS - SHIMPHY Status Register
- ***************************************************************************/
-/* SHIMPHY_ADDR_CNTL_1 :: SHIMPHY_STATUS :: reserved0 [31:01] */
-#define BCHP_SHIMPHY_ADDR_CNTL_1_SHIMPHY_STATUS_reserved0_MASK 0xfffffffe
-#define BCHP_SHIMPHY_ADDR_CNTL_1_SHIMPHY_STATUS_reserved0_SHIFT 1
-
-/* SHIMPHY_ADDR_CNTL_1 :: SHIMPHY_STATUS :: READY [00:00] */
-#define BCHP_SHIMPHY_ADDR_CNTL_1_SHIMPHY_STATUS_READY_MASK 0x00000001
-#define BCHP_SHIMPHY_ADDR_CNTL_1_SHIMPHY_STATUS_READY_SHIFT 0
-#define BCHP_SHIMPHY_ADDR_CNTL_1_SHIMPHY_STATUS_READY_DEFAULT 0x00000000
-
-/***************************************************************************
- *CMD_DATA_FIFO - Command and Data FIFO Status Register
- ***************************************************************************/
-/* SHIMPHY_ADDR_CNTL_1 :: CMD_DATA_FIFO :: reserved0 [31:26] */
-#define BCHP_SHIMPHY_ADDR_CNTL_1_CMD_DATA_FIFO_reserved0_MASK 0xfc000000
-#define BCHP_SHIMPHY_ADDR_CNTL_1_CMD_DATA_FIFO_reserved0_SHIFT 26
-
-/* SHIMPHY_ADDR_CNTL_1 :: CMD_DATA_FIFO :: FIFO_FULL [25:25] */
-#define BCHP_SHIMPHY_ADDR_CNTL_1_CMD_DATA_FIFO_FIFO_FULL_MASK 0x02000000
-#define BCHP_SHIMPHY_ADDR_CNTL_1_CMD_DATA_FIFO_FIFO_FULL_SHIFT 25
-
-/* SHIMPHY_ADDR_CNTL_1 :: CMD_DATA_FIFO :: FIFO_EMPTY [24:24] */
-#define BCHP_SHIMPHY_ADDR_CNTL_1_CMD_DATA_FIFO_FIFO_EMPTY_MASK 0x01000000
-#define BCHP_SHIMPHY_ADDR_CNTL_1_CMD_DATA_FIFO_FIFO_EMPTY_SHIFT 24
-
-/* SHIMPHY_ADDR_CNTL_1 :: CMD_DATA_FIFO :: reserved1 [23:10] */
-#define BCHP_SHIMPHY_ADDR_CNTL_1_CMD_DATA_FIFO_reserved1_MASK 0x00fffc00
-#define BCHP_SHIMPHY_ADDR_CNTL_1_CMD_DATA_FIFO_reserved1_SHIFT 10
-
-/* SHIMPHY_ADDR_CNTL_1 :: CMD_DATA_FIFO :: WR_PNTR [09:05] */
-#define BCHP_SHIMPHY_ADDR_CNTL_1_CMD_DATA_FIFO_WR_PNTR_MASK 0x000003e0
-#define BCHP_SHIMPHY_ADDR_CNTL_1_CMD_DATA_FIFO_WR_PNTR_SHIFT 5
-
-/* SHIMPHY_ADDR_CNTL_1 :: CMD_DATA_FIFO :: RD_PNTR [04:00] */
-#define BCHP_SHIMPHY_ADDR_CNTL_1_CMD_DATA_FIFO_RD_PNTR_MASK 0x0000001f
-#define BCHP_SHIMPHY_ADDR_CNTL_1_CMD_DATA_FIFO_RD_PNTR_SHIFT 0
-
-/***************************************************************************
- *RD_DATAPATH - Read Datapath Status Register
- ***************************************************************************/
-/* SHIMPHY_ADDR_CNTL_1 :: RD_DATAPATH :: reserved0 [31:10] */
-#define BCHP_SHIMPHY_ADDR_CNTL_1_RD_DATAPATH_reserved0_MASK 0xfffffc00
-#define BCHP_SHIMPHY_ADDR_CNTL_1_RD_DATAPATH_reserved0_SHIFT 10
-
-/* SHIMPHY_ADDR_CNTL_1 :: RD_DATAPATH :: WR_PNTR [09:05] */
-#define BCHP_SHIMPHY_ADDR_CNTL_1_RD_DATAPATH_WR_PNTR_MASK 0x000003e0
-#define BCHP_SHIMPHY_ADDR_CNTL_1_RD_DATAPATH_WR_PNTR_SHIFT 5
-
-/* SHIMPHY_ADDR_CNTL_1 :: RD_DATAPATH :: RD_PNTR [04:00] */
-#define BCHP_SHIMPHY_ADDR_CNTL_1_RD_DATAPATH_RD_PNTR_MASK 0x0000001f
-#define BCHP_SHIMPHY_ADDR_CNTL_1_RD_DATAPATH_RD_PNTR_SHIFT 0
-
-/***************************************************************************
- *FLAG_BUS - TP_OUT bus value Register
- ***************************************************************************/
-/* SHIMPHY_ADDR_CNTL_1 :: FLAG_BUS :: FLAG_BUS [31:00] */
-#define BCHP_SHIMPHY_ADDR_CNTL_1_FLAG_BUS_FLAG_BUS_MASK 0xffffffff
-#define BCHP_SHIMPHY_ADDR_CNTL_1_FLAG_BUS_FLAG_BUS_SHIFT 0
-
-/***************************************************************************
- *MISC - Miscellaneous Register
- ***************************************************************************/
-/* SHIMPHY_ADDR_CNTL_1 :: MISC :: reserved0 [31:20] */
-#define BCHP_SHIMPHY_ADDR_CNTL_1_MISC_reserved0_MASK 0xfff00000
-#define BCHP_SHIMPHY_ADDR_CNTL_1_MISC_reserved0_SHIFT 20
-
-/* SHIMPHY_ADDR_CNTL_1 :: MISC :: ASYNC_FIFO_AF_THRESHOLD [19:15] */
-#define BCHP_SHIMPHY_ADDR_CNTL_1_MISC_ASYNC_FIFO_AF_THRESHOLD_MASK 0x000f8000
-#define BCHP_SHIMPHY_ADDR_CNTL_1_MISC_ASYNC_FIFO_AF_THRESHOLD_SHIFT 15
-#define BCHP_SHIMPHY_ADDR_CNTL_1_MISC_ASYNC_FIFO_AF_THRESHOLD_DEFAULT 0x0000000a
-
-/* SHIMPHY_ADDR_CNTL_1 :: MISC :: reserved_for_eco1 [14:12] */
-#define BCHP_SHIMPHY_ADDR_CNTL_1_MISC_reserved_for_eco1_MASK 0x00007000
-#define BCHP_SHIMPHY_ADDR_CNTL_1_MISC_reserved_for_eco1_SHIFT 12
-#define BCHP_SHIMPHY_ADDR_CNTL_1_MISC_reserved_for_eco1_DEFAULT 0x00000000
-
-/* SHIMPHY_ADDR_CNTL_1 :: MISC :: DFI_ERROR_STATUS_CLR [11:11] */
-#define BCHP_SHIMPHY_ADDR_CNTL_1_MISC_DFI_ERROR_STATUS_CLR_MASK 0x00000800
-#define BCHP_SHIMPHY_ADDR_CNTL_1_MISC_DFI_ERROR_STATUS_CLR_SHIFT 11
-#define BCHP_SHIMPHY_ADDR_CNTL_1_MISC_DFI_ERROR_STATUS_CLR_DEFAULT 0x00000000
-
-/* SHIMPHY_ADDR_CNTL_1 :: MISC :: EDC_MONTIOR_STATUS_CLR [10:10] */
-#define BCHP_SHIMPHY_ADDR_CNTL_1_MISC_EDC_MONTIOR_STATUS_CLR_MASK 0x00000400
-#define BCHP_SHIMPHY_ADDR_CNTL_1_MISC_EDC_MONTIOR_STATUS_CLR_SHIFT 10
-#define BCHP_SHIMPHY_ADDR_CNTL_1_MISC_EDC_MONTIOR_STATUS_CLR_DEFAULT 0x00000000
-
-/* SHIMPHY_ADDR_CNTL_1 :: MISC :: VDL_MONITOR_STATUS_CLR [09:09] */
-#define BCHP_SHIMPHY_ADDR_CNTL_1_MISC_VDL_MONITOR_STATUS_CLR_MASK 0x00000200
-#define BCHP_SHIMPHY_ADDR_CNTL_1_MISC_VDL_MONITOR_STATUS_CLR_SHIFT 9
-#define BCHP_SHIMPHY_ADDR_CNTL_1_MISC_VDL_MONITOR_STATUS_CLR_DEFAULT 0x00000000
-
-/* SHIMPHY_ADDR_CNTL_1 :: MISC :: FUNC1 [08:08] */
-#define BCHP_SHIMPHY_ADDR_CNTL_1_MISC_FUNC1_MASK 0x00000100
-#define BCHP_SHIMPHY_ADDR_CNTL_1_MISC_FUNC1_SHIFT 8
-#define BCHP_SHIMPHY_ADDR_CNTL_1_MISC_FUNC1_DEFAULT 0x00000000
-
-/* SHIMPHY_ADDR_CNTL_1 :: MISC :: FUNC0 [07:07] */
-#define BCHP_SHIMPHY_ADDR_CNTL_1_MISC_FUNC0_MASK 0x00000080
-#define BCHP_SHIMPHY_ADDR_CNTL_1_MISC_FUNC0_SHIFT 7
-#define BCHP_SHIMPHY_ADDR_CNTL_1_MISC_FUNC0_DEFAULT 0x00000000
-
-/* SHIMPHY_ADDR_CNTL_1 :: MISC :: C2IO_INIT_RDY_OVR [06:06] */
-#define BCHP_SHIMPHY_ADDR_CNTL_1_MISC_C2IO_INIT_RDY_OVR_MASK 0x00000040
-#define BCHP_SHIMPHY_ADDR_CNTL_1_MISC_C2IO_INIT_RDY_OVR_SHIFT 6
-#define BCHP_SHIMPHY_ADDR_CNTL_1_MISC_C2IO_INIT_RDY_OVR_DEFAULT 0x00000000
-
-/* SHIMPHY_ADDR_CNTL_1 :: MISC :: RD_FIFO_HOLD_CLR [05:05] */
-#define BCHP_SHIMPHY_ADDR_CNTL_1_MISC_RD_FIFO_HOLD_CLR_MASK 0x00000020
-#define BCHP_SHIMPHY_ADDR_CNTL_1_MISC_RD_FIFO_HOLD_CLR_SHIFT 5
-#define BCHP_SHIMPHY_ADDR_CNTL_1_MISC_RD_FIFO_HOLD_CLR_DEFAULT 0x00000000
-
-/* SHIMPHY_ADDR_CNTL_1 :: MISC :: CMD_FIFO_HOLD_CLR [04:04] */
-#define BCHP_SHIMPHY_ADDR_CNTL_1_MISC_CMD_FIFO_HOLD_CLR_MASK 0x00000010
-#define BCHP_SHIMPHY_ADDR_CNTL_1_MISC_CMD_FIFO_HOLD_CLR_SHIFT 4
-#define BCHP_SHIMPHY_ADDR_CNTL_1_MISC_CMD_FIFO_HOLD_CLR_DEFAULT 0x00000000
-
-/* SHIMPHY_ADDR_CNTL_1 :: MISC :: reserved2 [03:01] */
-#define BCHP_SHIMPHY_ADDR_CNTL_1_MISC_reserved2_MASK 0x0000000e
-#define BCHP_SHIMPHY_ADDR_CNTL_1_MISC_reserved2_SHIFT 1
-
-/* SHIMPHY_ADDR_CNTL_1 :: MISC :: DATA_OVERRUN_CLR [00:00] */
-#define BCHP_SHIMPHY_ADDR_CNTL_1_MISC_DATA_OVERRUN_CLR_MASK 0x00000001
-#define BCHP_SHIMPHY_ADDR_CNTL_1_MISC_DATA_OVERRUN_CLR_SHIFT 0
-#define BCHP_SHIMPHY_ADDR_CNTL_1_MISC_DATA_OVERRUN_CLR_DEFAULT 0x00000000
-
-/***************************************************************************
- *SPARE0_RW - Spare register
- ***************************************************************************/
-/* SHIMPHY_ADDR_CNTL_1 :: SPARE0_RW :: reserved_for_eco0 [31:00] */
-#define BCHP_SHIMPHY_ADDR_CNTL_1_SPARE0_RW_reserved_for_eco0_MASK 0xffffffff
-#define BCHP_SHIMPHY_ADDR_CNTL_1_SPARE0_RW_reserved_for_eco0_SHIFT 0
-#define BCHP_SHIMPHY_ADDR_CNTL_1_SPARE0_RW_reserved_for_eco0_DEFAULT 0x00000000
-
-/***************************************************************************
- *SPARE1_RW - Spare register
- ***************************************************************************/
-/* SHIMPHY_ADDR_CNTL_1 :: SPARE1_RW :: reserved_for_eco0 [31:00] */
-#define BCHP_SHIMPHY_ADDR_CNTL_1_SPARE1_RW_reserved_for_eco0_MASK 0xffffffff
-#define BCHP_SHIMPHY_ADDR_CNTL_1_SPARE1_RW_reserved_for_eco0_SHIFT 0
-#define BCHP_SHIMPHY_ADDR_CNTL_1_SPARE1_RW_reserved_for_eco0_DEFAULT 0x00000000
-
-/***************************************************************************
- *SPARE0_RO - Spare register
- ***************************************************************************/
-/* SHIMPHY_ADDR_CNTL_1 :: SPARE0_RO :: reserved_for_eco0 [31:00] */
-#define BCHP_SHIMPHY_ADDR_CNTL_1_SPARE0_RO_reserved_for_eco0_MASK 0xffffffff
-#define BCHP_SHIMPHY_ADDR_CNTL_1_SPARE0_RO_reserved_for_eco0_SHIFT 0
-#define BCHP_SHIMPHY_ADDR_CNTL_1_SPARE0_RO_reserved_for_eco0_DEFAULT 0x00000000
-
-/***************************************************************************
- *SPARE1_RO - Spare register
- ***************************************************************************/
-/* SHIMPHY_ADDR_CNTL_1 :: SPARE1_RO :: reserved_for_eco0 [31:00] */
-#define BCHP_SHIMPHY_ADDR_CNTL_1_SPARE1_RO_reserved_for_eco0_MASK 0xffffffff
-#define BCHP_SHIMPHY_ADDR_CNTL_1_SPARE1_RO_reserved_for_eco0_SHIFT 0
-#define BCHP_SHIMPHY_ADDR_CNTL_1_SPARE1_RO_reserved_for_eco0_DEFAULT 0x00000000
-
-/***************************************************************************
- *DDR3_RESET_CNTRL - FORCE_DDR3_RESET Deassert Register
- ***************************************************************************/
-/* SHIMPHY_ADDR_CNTL_1 :: DDR3_RESET_CNTRL :: UNUSED [31:01] */
-#define BCHP_SHIMPHY_ADDR_CNTL_1_DDR3_RESET_CNTRL_UNUSED_MASK 0xfffffffe
-#define BCHP_SHIMPHY_ADDR_CNTL_1_DDR3_RESET_CNTRL_UNUSED_SHIFT 1
-#define BCHP_SHIMPHY_ADDR_CNTL_1_DDR3_RESET_CNTRL_UNUSED_DEFAULT 0x00000000
-
-/* SHIMPHY_ADDR_CNTL_1 :: DDR3_RESET_CNTRL :: FORCE_DDR3_RESET [00:00] */
-#define BCHP_SHIMPHY_ADDR_CNTL_1_DDR3_RESET_CNTRL_FORCE_DDR3_RESET_MASK 0x00000001
-#define BCHP_SHIMPHY_ADDR_CNTL_1_DDR3_RESET_CNTRL_FORCE_DDR3_RESET_SHIFT 0
-#define BCHP_SHIMPHY_ADDR_CNTL_1_DDR3_RESET_CNTRL_FORCE_DDR3_RESET_DEFAULT 0x00000001
-
-#endif /* #ifndef BCHP_SHIMPHY_ADDR_CNTL_1_H__ */
-
-/* End of File */
diff --git a/include/linux/brcmstb/7145a0/bchp_sun_top_ctrl.h b/include/linux/brcmstb/7145a0/bchp_sun_top_ctrl.h
deleted file mode 100644
index af4a35d..0000000
--- a/include/linux/brcmstb/7145a0/bchp_sun_top_ctrl.h
+++ /dev/null
@@ -1,6899 +0,0 @@
-/***************************************************************************
- * Copyright (c) 1999-2013, Broadcom Corporation
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
- *
- * Module Description:
- * DO NOT EDIT THIS FILE DIRECTLY
- *
- * This module was generated magically with RDB from a source description
- * file. You must edit the source file for changes to be made to this file.
- *
- *
- * Date: Generated on Sat Apr 6 03:07:51 2013
- * MD5 Checksum d41d8cd98f00b204e9800998ecf8427e
- *
- * Compiled with: RDB Utility combo_header.pl
- * RDB Parser 3.0
- * unknown unknown
- * Perl Interpreter 5.008008
- * Operating System linux
- *
- * Revision History:
- *
- * $brcm_Log: $
- *
- ***************************************************************************/
-
-#ifndef BCHP_SUN_TOP_CTRL_H__
-#define BCHP_SUN_TOP_CTRL_H__
-
-/***************************************************************************
- *SUN_TOP_CTRL - Top Control registers
- ***************************************************************************/
-#define BCHP_SUN_TOP_CTRL_CHIP_FAMILY_ID 0x20404000 /* Chip family ID */
-#define BCHP_SUN_TOP_CTRL_PRODUCT_ID 0x20404004 /* Product Revision ID */
-#define BCHP_SUN_TOP_CTRL_BSP_FEATURE_TABLE_ADDR 0x20404008 /* BSP feature table address */
-#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0 0x2040401c /* Strapping values */
-#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_1 0x20404020 /* Strapping values */
-#define BCHP_SUN_TOP_CTRL_BOND_STATUS 0x20404024 /* Bond option value register */
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0 0x20404028 /* OTP option test register */
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1 0x2040402c /* OTP option test register */
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0 0x20404030 /* OTP option status register */
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1 0x20404034 /* OTP option status register */
-#define BCHP_SUN_TOP_CTRL_SEMAPHORE_0 0x20404038 /* Semaphore channel 0 */
-#define BCHP_SUN_TOP_CTRL_SEMAPHORE_1 0x2040403c /* Semaphore channel 1 */
-#define BCHP_SUN_TOP_CTRL_SEMAPHORE_2 0x20404040 /* Semaphore channel 2 */
-#define BCHP_SUN_TOP_CTRL_SEMAPHORE_3 0x20404044 /* Semaphore channel 3 */
-#define BCHP_SUN_TOP_CTRL_SEMAPHORE_4 0x20404048 /* Semaphore channel 4 */
-#define BCHP_SUN_TOP_CTRL_SEMAPHORE_5 0x2040404c /* Semaphore channel 5 */
-#define BCHP_SUN_TOP_CTRL_SEMAPHORE_6 0x20404050 /* Semaphore channel 6 */
-#define BCHP_SUN_TOP_CTRL_SEMAPHORE_7 0x20404054 /* Semaphore channel 7 */
-#define BCHP_SUN_TOP_CTRL_SEMAPHORE_8 0x20404058 /* Semaphore channel 8 */
-#define BCHP_SUN_TOP_CTRL_SEMAPHORE_9 0x2040405c /* Semaphore channel 9 */
-#define BCHP_SUN_TOP_CTRL_SEMAPHORE_10 0x20404060 /* Semaphore channel 10 */
-#define BCHP_SUN_TOP_CTRL_SEMAPHORE_11 0x20404064 /* Semaphore channel 11 */
-#define BCHP_SUN_TOP_CTRL_SEMAPHORE_12 0x20404068 /* Semaphore channel 12 */
-#define BCHP_SUN_TOP_CTRL_SEMAPHORE_13 0x2040406c /* Semaphore channel 13 */
-#define BCHP_SUN_TOP_CTRL_SEMAPHORE_14 0x20404070 /* Semaphore channel 14 */
-#define BCHP_SUN_TOP_CTRL_SEMAPHORE_15 0x20404074 /* Semaphore channel 15 */
-#define BCHP_SUN_TOP_CTRL_GEN_WATCHDOG_0 0x20404078 /* General watchdog timer 0 */
-#define BCHP_SUN_TOP_CTRL_GEN_WATCHDOG_1 0x2040407c /* General watchdog timer 1 */
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0 0x20404080 /* General control register 0 */
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1 0x20404084 /* General control register 1 */
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_2 0x20404088 /* General control register 2 */
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_3 0x2040408c /* General control register 3 */
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_4 0x20404090 /* General control register 4 */
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_5 0x20404094 /* General control register 5 */
-#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0 0x20404098 /* General status register 0 */
-#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_1 0x2040409c /* General status register 1 */
-#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_2 0x204040a0 /* General status register 2 */
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0 0x204040a4 /* General control register without scan 0 */
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1 0x204040a8 /* General control register without scan 1 */
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2 0x204040ac /* General control register without scan 2 */
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3 0x204040b0 /* General control register without scan 3 */
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_4 0x204040b4 /* General control register without scan 4 */
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5 0x204040b8 /* General control register without scan 5 */
-#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_3 0x204040bc /* General status register 3 */
-#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_4 0x204040c0 /* General status register 4 */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0 0x20404100 /* Pinmux control register 0 */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1 0x20404104 /* Pinmux control register 1 */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2 0x20404108 /* Pinmux control register 2 */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3 0x2040410c /* Pinmux control register 3 */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4 0x20404110 /* Pinmux control register 4 */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5 0x20404114 /* Pinmux control register 5 */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6 0x20404118 /* Pinmux control register 6 */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7 0x2040411c /* Pinmux control register 7 */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8 0x20404120 /* Pinmux control register 8 */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9 0x20404124 /* Pinmux control register 9 */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10 0x20404128 /* Pinmux control register 10 */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11 0x2040412c /* Pinmux control register 11 */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12 0x20404130 /* Pinmux control register 12 */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13 0x20404134 /* Pinmux control register 13 */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14 0x20404138 /* Pinmux control register 14 */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15 0x2040413c /* Pinmux control register 15 */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0 0x20404140 /* Pad pull-up/pull-down control register 0 */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1 0x20404144 /* Pad pull-up/pull-down control register 1 */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2 0x20404148 /* Pad pull-up/pull-down control register 2 */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3 0x2040414c /* Pad pull-up/pull-down control register 3 */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4 0x20404150 /* Pad pull-up/pull-down control register 4 */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5 0x20404154 /* Pad pull-up/pull-down control register 5 */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6 0x20404158 /* Pad pull-up/pull-down control register 6 */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7 0x2040415c /* Pad pull-up/pull-down control register 7 */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8 0x20404160 /* Pad pull-up/pull-down control register 8 */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9 0x20404164 /* Pad pull-up/pull-down control register 9 */
-#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0 0x20404168 /* Bypass clock unselect register 0 */
-#define BCHP_SUN_TOP_CTRL_RESET_CTRL 0x20404300 /* Reset control */
-#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE 0x20404304 /* Reset source enable */
-#define BCHP_SUN_TOP_CTRL_SW_MASTER_RESET 0x20404308 /* Software master reset */
-#define BCHP_SUN_TOP_CTRL_HW_RESET_EXTENSION 0x2040430c /* Hardware reset extension */
-#define BCHP_SUN_TOP_CTRL_RESET_MONITOR 0x20404310 /* Reset Monitor */
-#define BCHP_SUN_TOP_CTRL_RESET_HISTORY 0x20404314 /* Reset history */
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET 0x20404318 /* Software init 0 set */
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR 0x2040431c /* Software init 0 clear */
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS 0x20404320 /* Software init 0 status */
-#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR 0x20404324 /* Security software init 0 monitor */
-#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR 0x20404328 /* Test configuration software init 0 monitor */
-#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR 0x2040432c /* Final software init 0 monitor */
-#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET 0x20404330 /* Software init 1 set */
-#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR 0x20404334 /* Software init 1 clear */
-#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS 0x20404338 /* Software init 1 status */
-#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR 0x2040433c /* Security software init 1 monitor */
-#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR 0x20404340 /* Test configuration software init 1 monitor */
-#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR 0x20404344 /* Final software init 1 monitor */
-#define BCHP_SUN_TOP_CTRL_SW_INIT_ONE_SHOT_TRIGGER 0x20404348 /* Software init one-shot trigger */
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_WIDTH 0x2040434c /* One-shot 0 width */
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK 0x20404350 /* One-shot 0 mask for software init 0 */
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK 0x20404354 /* One-shot 0 mask for software init 1 */
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_WIDTH 0x20404358 /* One-shot 1 width */
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK 0x2040435c /* One-shot 1 mask for software init 0 */
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK 0x20404360 /* One-shot 1 mask for software init 1 */
-#define BCHP_SUN_TOP_CTRL_UNCLEARED_SCRATCH 0x20404364 /* Scratch register */
-#define BCHP_SUN_TOP_CTRL_SPARE_CTRL 0x20404368 /* Spare control bits reserved for future use */
-#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL 0x20404380 /* Test port control */
-#define BCHP_SUN_TOP_CTRL_TEST_PORT_OUT_PEEK 0x20404384 /* Testport peek register */
-#define BCHP_SUN_TOP_CTRL_TEST_PORT_OUT_POKE 0x20404388 /* Testport poke register */
-#define BCHP_SUN_TOP_CTRL_TEST_PORT_IN_PEEK 0x2040438c /* Testport peek register */
-#define BCHP_SUN_TOP_CTRL_TEST_PORT_IN_POKE 0x20404390 /* Testport poke register */
-#define BCHP_SUN_TOP_CTRL_EJTAG_INPUT_EN 0x20404394 /* EJTAG input bus enables */
-#define BCHP_SUN_TOP_CTRL_EJTAG_OUTPUT_SEL 0x20404398 /* EJTAG output select */
-#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL 0x2040439c /* UART Router select */
-#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL 0x204043a0 /* VTRAP Control */
-#define BCHP_SUN_TOP_CTRL_VTRAP_STATUS 0x204043a4 /* VTRAP Status */
-#define BCHP_SUN_TOP_CTRL_SSP_CONFIG 0x20404400 /* Serial Slave Port configuration register */
-#define BCHP_SUN_TOP_CTRL_SERS_REV 0x20404420 /* SERS Revision Register */
-#define BCHP_SUN_TOP_CTRL_SERS_CFG 0x20404424 /* SERS Configuration Register */
-#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL 0x20404514 /* Block select for RO testmode */
-#define BCHP_SUN_TOP_CTRL_TEST_CONFIGURATION 0x20404518 /* Test configuration */
-
-/***************************************************************************
- *CHIP_FAMILY_ID - Chip family ID
- ***************************************************************************/
-/* SUN_TOP_CTRL :: CHIP_FAMILY_ID :: chip_family_id [31:00] */
-#define BCHP_SUN_TOP_CTRL_CHIP_FAMILY_ID_chip_family_id_MASK 0xffffffff
-#define BCHP_SUN_TOP_CTRL_CHIP_FAMILY_ID_chip_family_id_SHIFT 0
-#define BCHP_SUN_TOP_CTRL_CHIP_FAMILY_ID_chip_family_id_DEFAULT 0x71450000
-
-/***************************************************************************
- *PRODUCT_ID - Product Revision ID
- ***************************************************************************/
-/* SUN_TOP_CTRL :: PRODUCT_ID :: product_id [31:00] */
-#define BCHP_SUN_TOP_CTRL_PRODUCT_ID_product_id_MASK 0xffffffff
-#define BCHP_SUN_TOP_CTRL_PRODUCT_ID_product_id_SHIFT 0
-#define BCHP_SUN_TOP_CTRL_PRODUCT_ID_product_id_DEFAULT 0x71450000
-
-/***************************************************************************
- *BSP_FEATURE_TABLE_ADDR - BSP feature table address
- ***************************************************************************/
-/* SUN_TOP_CTRL :: BSP_FEATURE_TABLE_ADDR :: bsp_feature_table_addr [31:00] */
-#define BCHP_SUN_TOP_CTRL_BSP_FEATURE_TABLE_ADDR_bsp_feature_table_addr_MASK 0xffffffff
-#define BCHP_SUN_TOP_CTRL_BSP_FEATURE_TABLE_ADDR_bsp_feature_table_addr_SHIFT 0
-#define BCHP_SUN_TOP_CTRL_BSP_FEATURE_TABLE_ADDR_bsp_feature_table_addr_DEFAULT 0x00000000
-
-/***************************************************************************
- *STRAP_VALUE_0 - Strapping values
- ***************************************************************************/
-/* SUN_TOP_CTRL :: STRAP_VALUE_0 :: reserved0 [31:15] */
-#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0_reserved0_MASK 0xffff8000
-#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0_reserved0_SHIFT 15
-
-/* SUN_TOP_CTRL :: STRAP_VALUE_0 :: strap_reset_outb_def_val [14:14] */
-#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0_strap_reset_outb_def_val_MASK 0x00004000
-#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0_strap_reset_outb_def_val_SHIFT 14
-#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0_strap_reset_outb_def_val_DEFAULT 0x00000001
-
-/* SUN_TOP_CTRL :: STRAP_VALUE_0 :: strap_boot_shape [13:09] */
-#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0_strap_boot_shape_MASK 0x00003e00
-#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0_strap_boot_shape_SHIFT 9
-#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0_strap_boot_shape_DEFAULT 0x00000002
-
-/* SUN_TOP_CTRL :: STRAP_VALUE_0 :: strap_rsvd_1 [08:05] */
-#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0_strap_rsvd_1_MASK 0x000001e0
-#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0_strap_rsvd_1_SHIFT 5
-#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0_strap_rsvd_1_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: STRAP_VALUE_0 :: strap_rsvd_2 [04:04] */
-#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0_strap_rsvd_2_MASK 0x00000010
-#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0_strap_rsvd_2_SHIFT 4
-#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0_strap_rsvd_2_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: STRAP_VALUE_0 :: strap_pcie0_rc_ep [03:03] */
-#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0_strap_pcie0_rc_ep_MASK 0x00000008
-#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0_strap_pcie0_rc_ep_SHIFT 3
-#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0_strap_pcie0_rc_ep_DEFAULT 0x00000001
-
-/* SUN_TOP_CTRL :: STRAP_VALUE_0 :: strap_pcie1_rc_ep [02:02] */
-#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0_strap_pcie1_rc_ep_MASK 0x00000004
-#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0_strap_pcie1_rc_ep_SHIFT 2
-#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0_strap_pcie1_rc_ep_DEFAULT 0x00000001
-
-/* SUN_TOP_CTRL :: STRAP_VALUE_0 :: strap_ebi_pad_config [01:00] */
-#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0_strap_ebi_pad_config_MASK 0x00000003
-#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0_strap_ebi_pad_config_SHIFT 0
-#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0_strap_ebi_pad_config_DEFAULT 0x00000000
-
-/***************************************************************************
- *STRAP_VALUE_1 - Strapping values
- ***************************************************************************/
-/* SUN_TOP_CTRL :: STRAP_VALUE_1 :: reserved0 [31:05] */
-#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_1_reserved0_MASK 0xffffffe0
-#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_1_reserved0_SHIFT 5
-
-/* SUN_TOP_CTRL :: STRAP_VALUE_1 :: strap_rsvd_0 [04:04] */
-#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_1_strap_rsvd_0_MASK 0x00000010
-#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_1_strap_rsvd_0_SHIFT 4
-#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_1_strap_rsvd_0_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: STRAP_VALUE_1 :: strap_xcore_bias [03:01] */
-#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_1_strap_xcore_bias_MASK 0x0000000e
-#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_1_strap_xcore_bias_SHIFT 1
-#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_1_strap_xcore_bias_DEFAULT 0x00000002
-
-/* SUN_TOP_CTRL :: STRAP_VALUE_1 :: strap_hipass_xtal [00:00] */
-#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_1_strap_hipass_xtal_MASK 0x00000001
-#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_1_strap_hipass_xtal_SHIFT 0
-#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_1_strap_hipass_xtal_DEFAULT 0x00000001
-
-/***************************************************************************
- *BOND_STATUS - Bond option value register
- ***************************************************************************/
-/* SUN_TOP_CTRL :: BOND_STATUS :: reserved0 [31:01] */
-#define BCHP_SUN_TOP_CTRL_BOND_STATUS_reserved0_MASK 0xfffffffe
-#define BCHP_SUN_TOP_CTRL_BOND_STATUS_reserved0_SHIFT 1
-
-/* SUN_TOP_CTRL :: BOND_STATUS :: bond_reserved [00:00] */
-#define BCHP_SUN_TOP_CTRL_BOND_STATUS_bond_reserved_MASK 0x00000001
-#define BCHP_SUN_TOP_CTRL_BOND_STATUS_bond_reserved_SHIFT 0
-
-/***************************************************************************
- *OTP_OPTION_TEST_0 - OTP option test register
- ***************************************************************************/
-/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_spare_16 [31:31] */
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_spare_16_MASK 0x80000000
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_spare_16_SHIFT 31
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_spare_16_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_spare_15 [30:30] */
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_spare_15_MASK 0x40000000
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_spare_15_SHIFT 30
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_spare_15_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_spare_14 [29:29] */
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_spare_14_MASK 0x20000000
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_spare_14_SHIFT 29
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_spare_14_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_spare_13 [28:28] */
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_spare_13_MASK 0x10000000
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_spare_13_SHIFT 28
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_spare_13_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_spare_12 [27:27] */
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_spare_12_MASK 0x08000000
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_spare_12_SHIFT 27
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_spare_12_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_spare_11 [26:26] */
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_spare_11_MASK 0x04000000
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_spare_11_SHIFT 26
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_spare_11_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_spare_10 [25:25] */
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_spare_10_MASK 0x02000000
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_spare_10_SHIFT 25
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_spare_10_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_spare_9 [24:24] */
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_spare_9_MASK 0x01000000
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_spare_9_SHIFT 24
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_spare_9_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_spare_8 [23:23] */
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_spare_8_MASK 0x00800000
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_spare_8_SHIFT 23
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_spare_8_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_spare_7 [22:22] */
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_spare_7_MASK 0x00400000
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_spare_7_SHIFT 22
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_spare_7_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_spare_6 [21:21] */
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_spare_6_MASK 0x00200000
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_spare_6_SHIFT 21
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_spare_6_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_spare_5 [20:20] */
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_spare_5_MASK 0x00100000
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_spare_5_SHIFT 20
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_spare_5_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_spare_4 [19:19] */
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_spare_4_MASK 0x00080000
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_spare_4_SHIFT 19
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_spare_4_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_spare_3 [18:18] */
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_spare_3_MASK 0x00040000
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_spare_3_SHIFT 18
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_spare_3_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_spare_2 [17:17] */
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_spare_2_MASK 0x00020000
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_spare_2_SHIFT 17
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_spare_2_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_spare_1 [16:16] */
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_spare_1_MASK 0x00010000
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_spare_1_SHIFT 16
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_spare_1_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_spare_0 [15:15] */
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_spare_0_MASK 0x00008000
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_spare_0_SHIFT 15
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_spare_0_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_dvp_hr_disable [14:14] */
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_dvp_hr_disable_MASK 0x00004000
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_dvp_hr_disable_SHIFT 14
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_dvp_hr_disable_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_av_output_disable [13:13] */
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_av_output_disable_MASK 0x00002000
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_av_output_disable_SHIFT 13
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_av_output_disable_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_vc4_disable [12:12] */
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_vc4_disable_MASK 0x00001000
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_vc4_disable_SHIFT 12
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_vc4_disable_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_usb_p0_disable [11:11] */
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_usb_p0_disable_MASK 0x00000800
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_usb_p0_disable_SHIFT 11
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_usb_p0_disable_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_usb_p1_disable [10:10] */
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_usb_p1_disable_MASK 0x00000400
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_usb_p1_disable_SHIFT 10
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_usb_p1_disable_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_capsense_disable [09:09] */
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_capsense_disable_MASK 0x00000200
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_capsense_disable_SHIFT 9
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_capsense_disable_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_audio_spdif_disable [08:08] */
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_audio_spdif_disable_MASK 0x00000100
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_audio_spdif_disable_SHIFT 8
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_audio_spdif_disable_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_en_testport [07:07] */
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_en_testport_MASK 0x00000080
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_en_testport_SHIFT 7
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_en_testport_DEFAULT 0x00000001
-
-/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_en_cr [06:05] */
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_en_cr_MASK 0x00000060
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_en_cr_SHIFT 5
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_en_cr_DEFAULT 0x00000003
-
-/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_rave_verify_enable [04:04] */
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_rave_verify_enable_MASK 0x00000010
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_rave_verify_enable_SHIFT 4
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_rave_verify_enable_DEFAULT 0x00000001
-
-/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_bsp_spares [03:00] */
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_bsp_spares_MASK 0x0000000f
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_bsp_spares_SHIFT 0
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_bsp_spares_DEFAULT 0x00000000
-
-/***************************************************************************
- *OTP_OPTION_TEST_1 - OTP option test register
- ***************************************************************************/
-/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_6 [31:31] */
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_6_MASK 0x80000000
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_6_SHIFT 31
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_6_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_5 [30:30] */
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_5_MASK 0x40000000
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_5_SHIFT 30
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_5_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_4 [29:29] */
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_4_MASK 0x20000000
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_4_SHIFT 29
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_4_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_3 [28:28] */
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_3_MASK 0x10000000
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_3_SHIFT 28
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_3_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_2 [27:27] */
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_2_MASK 0x08000000
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_2_SHIFT 27
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_2_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_1 [26:26] */
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_1_MASK 0x04000000
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_1_SHIFT 26
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_1_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_0 [25:25] */
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_0_MASK 0x02000000
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_0_SHIFT 25
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_0_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_security_proc_disable [24:24] */
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_security_proc_disable_MASK 0x01000000
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_security_proc_disable_SHIFT 24
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_security_proc_disable_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_host_cpu_disable [23:23] */
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_host_cpu_disable_MASK 0x00800000
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_host_cpu_disable_SHIFT 23
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_host_cpu_disable_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_macrovision_disable [22:22] */
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_macrovision_disable_MASK 0x00400000
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_macrovision_disable_SHIFT 22
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_macrovision_disable_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_gfap_disable [21:21] */
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_gfap_disable_MASK 0x00200000
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_gfap_disable_SHIFT 21
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_gfap_disable_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_rgmii_1_disable [20:20] */
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_rgmii_1_disable_MASK 0x00100000
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_rgmii_1_disable_SHIFT 20
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_rgmii_1_disable_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_pcie0_disable [19:19] */
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_pcie0_disable_MASK 0x00080000
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_pcie0_disable_SHIFT 19
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_pcie0_disable_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_pcie1_disable [18:18] */
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_pcie1_disable_MASK 0x00040000
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_pcie1_disable_SHIFT 18
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_pcie1_disable_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_sata_disable [17:17] */
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_sata_disable_MASK 0x00020000
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_sata_disable_SHIFT 17
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_sata_disable_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_moca_disable [16:16] */
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_moca_disable_MASK 0x00010000
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_moca_disable_SHIFT 16
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_moca_disable_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_moca_20_disable [15:15] */
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_moca_20_disable_MASK 0x00008000
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_moca_20_disable_SHIFT 15
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_moca_20_disable_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_4kx2k_disable [14:14] */
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_4kx2k_disable_MASK 0x00004000
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_4kx2k_disable_SHIFT 14
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_4kx2k_disable_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_vice2_0_disable [13:13] */
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_vice2_0_disable_MASK 0x00002000
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_vice2_0_disable_SHIFT 13
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_vice2_0_disable_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_vice2_1_disable [12:12] */
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_vice2_1_disable_MASK 0x00001000
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_vice2_1_disable_SHIFT 12
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_vice2_1_disable_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_hdcp_disable [11:11] */
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_hdcp_disable_MASK 0x00000800
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_hdcp_disable_SHIFT 11
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_hdcp_disable_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_hdmi_pass_thru_disable [10:10] */
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_hdmi_pass_thru_disable_MASK 0x00000400
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_hdmi_pass_thru_disable_SHIFT 10
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_hdmi_pass_thru_disable_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_gphy_trim_dac [09:06] */
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_gphy_trim_dac_MASK 0x000003c0
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_gphy_trim_dac_SHIFT 6
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_gphy_trim_dac_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_hvd0_disable [05:05] */
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_hvd0_disable_MASK 0x00000020
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_hvd0_disable_SHIFT 5
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_hvd0_disable_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_rgcpu_disable [04:04] */
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_rgcpu_disable_MASK 0x00000010
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_rgcpu_disable_SHIFT 4
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_rgcpu_disable_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_avd_disable [03:03] */
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_avd_disable_MASK 0x00000008
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_avd_disable_SHIFT 3
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_avd_disable_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_rv9_disable [02:02] */
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_rv9_disable_MASK 0x00000004
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_rv9_disable_SHIFT 2
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_rv9_disable_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_rfm_disable [01:01] */
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_rfm_disable_MASK 0x00000002
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_rfm_disable_SHIFT 1
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_rfm_disable_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_gisb_to_ubus_disable [00:00] */
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_gisb_to_ubus_disable_MASK 0x00000001
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_gisb_to_ubus_disable_SHIFT 0
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_gisb_to_ubus_disable_DEFAULT 0x00000000
-
-/***************************************************************************
- *OTP_OPTION_STATUS_0 - OTP option status register
- ***************************************************************************/
-/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_spare_16 [31:31] */
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_spare_16_MASK 0x80000000
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_spare_16_SHIFT 31
-
-/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_spare_15 [30:30] */
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_spare_15_MASK 0x40000000
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_spare_15_SHIFT 30
-
-/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_spare_14 [29:29] */
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_spare_14_MASK 0x20000000
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_spare_14_SHIFT 29
-
-/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_spare_13 [28:28] */
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_spare_13_MASK 0x10000000
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_spare_13_SHIFT 28
-
-/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_spare_12 [27:27] */
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_spare_12_MASK 0x08000000
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_spare_12_SHIFT 27
-
-/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_spare_11 [26:26] */
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_spare_11_MASK 0x04000000
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_spare_11_SHIFT 26
-
-/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_spare_10 [25:25] */
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_spare_10_MASK 0x02000000
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_spare_10_SHIFT 25
-
-/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_spare_9 [24:24] */
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_spare_9_MASK 0x01000000
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_spare_9_SHIFT 24
-
-/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_spare_8 [23:23] */
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_spare_8_MASK 0x00800000
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_spare_8_SHIFT 23
-
-/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_spare_7 [22:22] */
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_spare_7_MASK 0x00400000
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_spare_7_SHIFT 22
-
-/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_spare_6 [21:21] */
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_spare_6_MASK 0x00200000
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_spare_6_SHIFT 21
-
-/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_spare_5 [20:20] */
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_spare_5_MASK 0x00100000
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_spare_5_SHIFT 20
-
-/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_spare_4 [19:19] */
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_spare_4_MASK 0x00080000
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_spare_4_SHIFT 19
-
-/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_spare_3 [18:18] */
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_spare_3_MASK 0x00040000
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_spare_3_SHIFT 18
-
-/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_spare_2 [17:17] */
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_spare_2_MASK 0x00020000
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_spare_2_SHIFT 17
-
-/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_spare_1 [16:16] */
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_spare_1_MASK 0x00010000
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_spare_1_SHIFT 16
-
-/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_spare_0 [15:15] */
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_spare_0_MASK 0x00008000
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_spare_0_SHIFT 15
-
-/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_dvp_hr_disable [14:14] */
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_dvp_hr_disable_MASK 0x00004000
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_dvp_hr_disable_SHIFT 14
-
-/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_av_output_disable [13:13] */
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_av_output_disable_MASK 0x00002000
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_av_output_disable_SHIFT 13
-
-/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_vc4_disable [12:12] */
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_vc4_disable_MASK 0x00001000
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_vc4_disable_SHIFT 12
-
-/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_usb_p0_disable [11:11] */
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_usb_p0_disable_MASK 0x00000800
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_usb_p0_disable_SHIFT 11
-
-/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_usb_p1_disable [10:10] */
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_usb_p1_disable_MASK 0x00000400
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_usb_p1_disable_SHIFT 10
-
-/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_capsense_disable [09:09] */
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_capsense_disable_MASK 0x00000200
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_capsense_disable_SHIFT 9
-
-/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_audio_spdif_disable [08:08] */
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_audio_spdif_disable_MASK 0x00000100
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_audio_spdif_disable_SHIFT 8
-
-/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_en_testport [07:07] */
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_en_testport_MASK 0x00000080
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_en_testport_SHIFT 7
-
-/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_en_cr [06:05] */
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_en_cr_MASK 0x00000060
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_en_cr_SHIFT 5
-
-/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_rave_verify_enable [04:04] */
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_rave_verify_enable_MASK 0x00000010
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_rave_verify_enable_SHIFT 4
-
-/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_bsp_spares [03:00] */
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_bsp_spares_MASK 0x0000000f
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_bsp_spares_SHIFT 0
-
-/***************************************************************************
- *OTP_OPTION_STATUS_1 - OTP option status register
- ***************************************************************************/
-/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_6 [31:31] */
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_6_MASK 0x80000000
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_6_SHIFT 31
-
-/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_5 [30:30] */
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_5_MASK 0x40000000
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_5_SHIFT 30
-
-/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_4 [29:29] */
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_4_MASK 0x20000000
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_4_SHIFT 29
-
-/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_3 [28:28] */
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_3_MASK 0x10000000
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_3_SHIFT 28
-
-/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_2 [27:27] */
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_2_MASK 0x08000000
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_2_SHIFT 27
-
-/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_1 [26:26] */
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_1_MASK 0x04000000
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_1_SHIFT 26
-
-/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_0 [25:25] */
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_0_MASK 0x02000000
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_0_SHIFT 25
-
-/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_security_proc_disable [24:24] */
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_security_proc_disable_MASK 0x01000000
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_security_proc_disable_SHIFT 24
-
-/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_host_cpu_disable [23:23] */
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_host_cpu_disable_MASK 0x00800000
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_host_cpu_disable_SHIFT 23
-
-/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_macrovision_disable [22:22] */
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_macrovision_disable_MASK 0x00400000
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_macrovision_disable_SHIFT 22
-
-/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_gfap_disable [21:21] */
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_gfap_disable_MASK 0x00200000
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_gfap_disable_SHIFT 21
-
-/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_rgmii_1_disable [20:20] */
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_rgmii_1_disable_MASK 0x00100000
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_rgmii_1_disable_SHIFT 20
-
-/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_pcie0_disable [19:19] */
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_pcie0_disable_MASK 0x00080000
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_pcie0_disable_SHIFT 19
-
-/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_pcie1_disable [18:18] */
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_pcie1_disable_MASK 0x00040000
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_pcie1_disable_SHIFT 18
-
-/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_sata_disable [17:17] */
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_sata_disable_MASK 0x00020000
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_sata_disable_SHIFT 17
-
-/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_moca_disable [16:16] */
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_moca_disable_MASK 0x00010000
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_moca_disable_SHIFT 16
-
-/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_moca_20_disable [15:15] */
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_moca_20_disable_MASK 0x00008000
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_moca_20_disable_SHIFT 15
-
-/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_4kx2k_disable [14:14] */
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_4kx2k_disable_MASK 0x00004000
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_4kx2k_disable_SHIFT 14
-
-/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_vice2_0_disable [13:13] */
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_vice2_0_disable_MASK 0x00002000
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_vice2_0_disable_SHIFT 13
-
-/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_vice2_1_disable [12:12] */
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_vice2_1_disable_MASK 0x00001000
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_vice2_1_disable_SHIFT 12
-
-/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_hdcp_disable [11:11] */
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_hdcp_disable_MASK 0x00000800
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_hdcp_disable_SHIFT 11
-
-/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_hdmi_pass_thru_disable [10:10] */
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_hdmi_pass_thru_disable_MASK 0x00000400
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_hdmi_pass_thru_disable_SHIFT 10
-
-/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_gphy_trim_dac [09:06] */
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_gphy_trim_dac_MASK 0x000003c0
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_gphy_trim_dac_SHIFT 6
-
-/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_hvd0_disable [05:05] */
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_hvd0_disable_MASK 0x00000020
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_hvd0_disable_SHIFT 5
-
-/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_rgcpu_disable [04:04] */
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_rgcpu_disable_MASK 0x00000010
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_rgcpu_disable_SHIFT 4
-
-/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_avd_disable [03:03] */
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_avd_disable_MASK 0x00000008
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_avd_disable_SHIFT 3
-
-/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_rv9_disable [02:02] */
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_rv9_disable_MASK 0x00000004
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_rv9_disable_SHIFT 2
-
-/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_rfm_disable [01:01] */
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_rfm_disable_MASK 0x00000002
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_rfm_disable_SHIFT 1
-
-/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_gisb_to_ubus_disable [00:00] */
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_gisb_to_ubus_disable_MASK 0x00000001
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_gisb_to_ubus_disable_SHIFT 0
-
-/***************************************************************************
- *SEMAPHORE_0 - Semaphore channel 0
- ***************************************************************************/
-/* SUN_TOP_CTRL :: SEMAPHORE_0 :: reserved0 [31:08] */
-#define BCHP_SUN_TOP_CTRL_SEMAPHORE_0_reserved0_MASK 0xffffff00
-#define BCHP_SUN_TOP_CTRL_SEMAPHORE_0_reserved0_SHIFT 8
-
-/* SUN_TOP_CTRL :: SEMAPHORE_0 :: semaphore_ctrl [07:00] */
-#define BCHP_SUN_TOP_CTRL_SEMAPHORE_0_semaphore_ctrl_MASK 0x000000ff
-#define BCHP_SUN_TOP_CTRL_SEMAPHORE_0_semaphore_ctrl_SHIFT 0
-#define BCHP_SUN_TOP_CTRL_SEMAPHORE_0_semaphore_ctrl_DEFAULT 0x00000000
-
-/***************************************************************************
- *SEMAPHORE_1 - Semaphore channel 1
- ***************************************************************************/
-/* SUN_TOP_CTRL :: SEMAPHORE_1 :: reserved0 [31:08] */
-#define BCHP_SUN_TOP_CTRL_SEMAPHORE_1_reserved0_MASK 0xffffff00
-#define BCHP_SUN_TOP_CTRL_SEMAPHORE_1_reserved0_SHIFT 8
-
-/* SUN_TOP_CTRL :: SEMAPHORE_1 :: semaphore_ctrl [07:00] */
-#define BCHP_SUN_TOP_CTRL_SEMAPHORE_1_semaphore_ctrl_MASK 0x000000ff
-#define BCHP_SUN_TOP_CTRL_SEMAPHORE_1_semaphore_ctrl_SHIFT 0
-#define BCHP_SUN_TOP_CTRL_SEMAPHORE_1_semaphore_ctrl_DEFAULT 0x00000000
-
-/***************************************************************************
- *SEMAPHORE_2 - Semaphore channel 2
- ***************************************************************************/
-/* SUN_TOP_CTRL :: SEMAPHORE_2 :: reserved0 [31:08] */
-#define BCHP_SUN_TOP_CTRL_SEMAPHORE_2_reserved0_MASK 0xffffff00
-#define BCHP_SUN_TOP_CTRL_SEMAPHORE_2_reserved0_SHIFT 8
-
-/* SUN_TOP_CTRL :: SEMAPHORE_2 :: semaphore_ctrl [07:00] */
-#define BCHP_SUN_TOP_CTRL_SEMAPHORE_2_semaphore_ctrl_MASK 0x000000ff
-#define BCHP_SUN_TOP_CTRL_SEMAPHORE_2_semaphore_ctrl_SHIFT 0
-#define BCHP_SUN_TOP_CTRL_SEMAPHORE_2_semaphore_ctrl_DEFAULT 0x00000000
-
-/***************************************************************************
- *SEMAPHORE_3 - Semaphore channel 3
- ***************************************************************************/
-/* SUN_TOP_CTRL :: SEMAPHORE_3 :: reserved0 [31:08] */
-#define BCHP_SUN_TOP_CTRL_SEMAPHORE_3_reserved0_MASK 0xffffff00
-#define BCHP_SUN_TOP_CTRL_SEMAPHORE_3_reserved0_SHIFT 8
-
-/* SUN_TOP_CTRL :: SEMAPHORE_3 :: semaphore_ctrl [07:00] */
-#define BCHP_SUN_TOP_CTRL_SEMAPHORE_3_semaphore_ctrl_MASK 0x000000ff
-#define BCHP_SUN_TOP_CTRL_SEMAPHORE_3_semaphore_ctrl_SHIFT 0
-#define BCHP_SUN_TOP_CTRL_SEMAPHORE_3_semaphore_ctrl_DEFAULT 0x00000000
-
-/***************************************************************************
- *SEMAPHORE_4 - Semaphore channel 4
- ***************************************************************************/
-/* SUN_TOP_CTRL :: SEMAPHORE_4 :: reserved0 [31:08] */
-#define BCHP_SUN_TOP_CTRL_SEMAPHORE_4_reserved0_MASK 0xffffff00
-#define BCHP_SUN_TOP_CTRL_SEMAPHORE_4_reserved0_SHIFT 8
-
-/* SUN_TOP_CTRL :: SEMAPHORE_4 :: semaphore_ctrl [07:00] */
-#define BCHP_SUN_TOP_CTRL_SEMAPHORE_4_semaphore_ctrl_MASK 0x000000ff
-#define BCHP_SUN_TOP_CTRL_SEMAPHORE_4_semaphore_ctrl_SHIFT 0
-#define BCHP_SUN_TOP_CTRL_SEMAPHORE_4_semaphore_ctrl_DEFAULT 0x00000000
-
-/***************************************************************************
- *SEMAPHORE_5 - Semaphore channel 5
- ***************************************************************************/
-/* SUN_TOP_CTRL :: SEMAPHORE_5 :: reserved0 [31:08] */
-#define BCHP_SUN_TOP_CTRL_SEMAPHORE_5_reserved0_MASK 0xffffff00
-#define BCHP_SUN_TOP_CTRL_SEMAPHORE_5_reserved0_SHIFT 8
-
-/* SUN_TOP_CTRL :: SEMAPHORE_5 :: semaphore_ctrl [07:00] */
-#define BCHP_SUN_TOP_CTRL_SEMAPHORE_5_semaphore_ctrl_MASK 0x000000ff
-#define BCHP_SUN_TOP_CTRL_SEMAPHORE_5_semaphore_ctrl_SHIFT 0
-#define BCHP_SUN_TOP_CTRL_SEMAPHORE_5_semaphore_ctrl_DEFAULT 0x00000000
-
-/***************************************************************************
- *SEMAPHORE_6 - Semaphore channel 6
- ***************************************************************************/
-/* SUN_TOP_CTRL :: SEMAPHORE_6 :: reserved0 [31:08] */
-#define BCHP_SUN_TOP_CTRL_SEMAPHORE_6_reserved0_MASK 0xffffff00
-#define BCHP_SUN_TOP_CTRL_SEMAPHORE_6_reserved0_SHIFT 8
-
-/* SUN_TOP_CTRL :: SEMAPHORE_6 :: semaphore_ctrl [07:00] */
-#define BCHP_SUN_TOP_CTRL_SEMAPHORE_6_semaphore_ctrl_MASK 0x000000ff
-#define BCHP_SUN_TOP_CTRL_SEMAPHORE_6_semaphore_ctrl_SHIFT 0
-#define BCHP_SUN_TOP_CTRL_SEMAPHORE_6_semaphore_ctrl_DEFAULT 0x00000000
-
-/***************************************************************************
- *SEMAPHORE_7 - Semaphore channel 7
- ***************************************************************************/
-/* SUN_TOP_CTRL :: SEMAPHORE_7 :: reserved0 [31:08] */
-#define BCHP_SUN_TOP_CTRL_SEMAPHORE_7_reserved0_MASK 0xffffff00
-#define BCHP_SUN_TOP_CTRL_SEMAPHORE_7_reserved0_SHIFT 8
-
-/* SUN_TOP_CTRL :: SEMAPHORE_7 :: semaphore_ctrl [07:00] */
-#define BCHP_SUN_TOP_CTRL_SEMAPHORE_7_semaphore_ctrl_MASK 0x000000ff
-#define BCHP_SUN_TOP_CTRL_SEMAPHORE_7_semaphore_ctrl_SHIFT 0
-#define BCHP_SUN_TOP_CTRL_SEMAPHORE_7_semaphore_ctrl_DEFAULT 0x00000000
-
-/***************************************************************************
- *SEMAPHORE_8 - Semaphore channel 8
- ***************************************************************************/
-/* SUN_TOP_CTRL :: SEMAPHORE_8 :: reserved0 [31:08] */
-#define BCHP_SUN_TOP_CTRL_SEMAPHORE_8_reserved0_MASK 0xffffff00
-#define BCHP_SUN_TOP_CTRL_SEMAPHORE_8_reserved0_SHIFT 8
-
-/* SUN_TOP_CTRL :: SEMAPHORE_8 :: semaphore_ctrl [07:00] */
-#define BCHP_SUN_TOP_CTRL_SEMAPHORE_8_semaphore_ctrl_MASK 0x000000ff
-#define BCHP_SUN_TOP_CTRL_SEMAPHORE_8_semaphore_ctrl_SHIFT 0
-#define BCHP_SUN_TOP_CTRL_SEMAPHORE_8_semaphore_ctrl_DEFAULT 0x00000000
-
-/***************************************************************************
- *SEMAPHORE_9 - Semaphore channel 9
- ***************************************************************************/
-/* SUN_TOP_CTRL :: SEMAPHORE_9 :: reserved0 [31:08] */
-#define BCHP_SUN_TOP_CTRL_SEMAPHORE_9_reserved0_MASK 0xffffff00
-#define BCHP_SUN_TOP_CTRL_SEMAPHORE_9_reserved0_SHIFT 8
-
-/* SUN_TOP_CTRL :: SEMAPHORE_9 :: semaphore_ctrl [07:00] */
-#define BCHP_SUN_TOP_CTRL_SEMAPHORE_9_semaphore_ctrl_MASK 0x000000ff
-#define BCHP_SUN_TOP_CTRL_SEMAPHORE_9_semaphore_ctrl_SHIFT 0
-#define BCHP_SUN_TOP_CTRL_SEMAPHORE_9_semaphore_ctrl_DEFAULT 0x00000000
-
-/***************************************************************************
- *SEMAPHORE_10 - Semaphore channel 10
- ***************************************************************************/
-/* SUN_TOP_CTRL :: SEMAPHORE_10 :: reserved0 [31:08] */
-#define BCHP_SUN_TOP_CTRL_SEMAPHORE_10_reserved0_MASK 0xffffff00
-#define BCHP_SUN_TOP_CTRL_SEMAPHORE_10_reserved0_SHIFT 8
-
-/* SUN_TOP_CTRL :: SEMAPHORE_10 :: semaphore_ctrl [07:00] */
-#define BCHP_SUN_TOP_CTRL_SEMAPHORE_10_semaphore_ctrl_MASK 0x000000ff
-#define BCHP_SUN_TOP_CTRL_SEMAPHORE_10_semaphore_ctrl_SHIFT 0
-#define BCHP_SUN_TOP_CTRL_SEMAPHORE_10_semaphore_ctrl_DEFAULT 0x00000000
-
-/***************************************************************************
- *SEMAPHORE_11 - Semaphore channel 11
- ***************************************************************************/
-/* SUN_TOP_CTRL :: SEMAPHORE_11 :: reserved0 [31:08] */
-#define BCHP_SUN_TOP_CTRL_SEMAPHORE_11_reserved0_MASK 0xffffff00
-#define BCHP_SUN_TOP_CTRL_SEMAPHORE_11_reserved0_SHIFT 8
-
-/* SUN_TOP_CTRL :: SEMAPHORE_11 :: semaphore_ctrl [07:00] */
-#define BCHP_SUN_TOP_CTRL_SEMAPHORE_11_semaphore_ctrl_MASK 0x000000ff
-#define BCHP_SUN_TOP_CTRL_SEMAPHORE_11_semaphore_ctrl_SHIFT 0
-#define BCHP_SUN_TOP_CTRL_SEMAPHORE_11_semaphore_ctrl_DEFAULT 0x00000000
-
-/***************************************************************************
- *SEMAPHORE_12 - Semaphore channel 12
- ***************************************************************************/
-/* SUN_TOP_CTRL :: SEMAPHORE_12 :: reserved0 [31:08] */
-#define BCHP_SUN_TOP_CTRL_SEMAPHORE_12_reserved0_MASK 0xffffff00
-#define BCHP_SUN_TOP_CTRL_SEMAPHORE_12_reserved0_SHIFT 8
-
-/* SUN_TOP_CTRL :: SEMAPHORE_12 :: semaphore_ctrl [07:00] */
-#define BCHP_SUN_TOP_CTRL_SEMAPHORE_12_semaphore_ctrl_MASK 0x000000ff
-#define BCHP_SUN_TOP_CTRL_SEMAPHORE_12_semaphore_ctrl_SHIFT 0
-#define BCHP_SUN_TOP_CTRL_SEMAPHORE_12_semaphore_ctrl_DEFAULT 0x00000000
-
-/***************************************************************************
- *SEMAPHORE_13 - Semaphore channel 13
- ***************************************************************************/
-/* SUN_TOP_CTRL :: SEMAPHORE_13 :: reserved0 [31:08] */
-#define BCHP_SUN_TOP_CTRL_SEMAPHORE_13_reserved0_MASK 0xffffff00
-#define BCHP_SUN_TOP_CTRL_SEMAPHORE_13_reserved0_SHIFT 8
-
-/* SUN_TOP_CTRL :: SEMAPHORE_13 :: semaphore_ctrl [07:00] */
-#define BCHP_SUN_TOP_CTRL_SEMAPHORE_13_semaphore_ctrl_MASK 0x000000ff
-#define BCHP_SUN_TOP_CTRL_SEMAPHORE_13_semaphore_ctrl_SHIFT 0
-#define BCHP_SUN_TOP_CTRL_SEMAPHORE_13_semaphore_ctrl_DEFAULT 0x00000000
-
-/***************************************************************************
- *SEMAPHORE_14 - Semaphore channel 14
- ***************************************************************************/
-/* SUN_TOP_CTRL :: SEMAPHORE_14 :: reserved0 [31:08] */
-#define BCHP_SUN_TOP_CTRL_SEMAPHORE_14_reserved0_MASK 0xffffff00
-#define BCHP_SUN_TOP_CTRL_SEMAPHORE_14_reserved0_SHIFT 8
-
-/* SUN_TOP_CTRL :: SEMAPHORE_14 :: semaphore_ctrl [07:00] */
-#define BCHP_SUN_TOP_CTRL_SEMAPHORE_14_semaphore_ctrl_MASK 0x000000ff
-#define BCHP_SUN_TOP_CTRL_SEMAPHORE_14_semaphore_ctrl_SHIFT 0
-#define BCHP_SUN_TOP_CTRL_SEMAPHORE_14_semaphore_ctrl_DEFAULT 0x00000000
-
-/***************************************************************************
- *SEMAPHORE_15 - Semaphore channel 15
- ***************************************************************************/
-/* SUN_TOP_CTRL :: SEMAPHORE_15 :: reserved0 [31:08] */
-#define BCHP_SUN_TOP_CTRL_SEMAPHORE_15_reserved0_MASK 0xffffff00
-#define BCHP_SUN_TOP_CTRL_SEMAPHORE_15_reserved0_SHIFT 8
-
-/* SUN_TOP_CTRL :: SEMAPHORE_15 :: semaphore_ctrl [07:00] */
-#define BCHP_SUN_TOP_CTRL_SEMAPHORE_15_semaphore_ctrl_MASK 0x000000ff
-#define BCHP_SUN_TOP_CTRL_SEMAPHORE_15_semaphore_ctrl_SHIFT 0
-#define BCHP_SUN_TOP_CTRL_SEMAPHORE_15_semaphore_ctrl_DEFAULT 0x00000000
-
-/***************************************************************************
- *GEN_WATCHDOG_0 - General watchdog timer 0
- ***************************************************************************/
-/* SUN_TOP_CTRL :: GEN_WATCHDOG_0 :: watchdog_timeout_value [31:00] */
-#define BCHP_SUN_TOP_CTRL_GEN_WATCHDOG_0_watchdog_timeout_value_MASK 0xffffffff
-#define BCHP_SUN_TOP_CTRL_GEN_WATCHDOG_0_watchdog_timeout_value_SHIFT 0
-#define BCHP_SUN_TOP_CTRL_GEN_WATCHDOG_0_watchdog_timeout_value_DEFAULT 0x00000000
-
-/***************************************************************************
- *GEN_WATCHDOG_1 - General watchdog timer 1
- ***************************************************************************/
-/* SUN_TOP_CTRL :: GEN_WATCHDOG_1 :: watchdog_timeout_value [31:00] */
-#define BCHP_SUN_TOP_CTRL_GEN_WATCHDOG_1_watchdog_timeout_value_MASK 0xffffffff
-#define BCHP_SUN_TOP_CTRL_GEN_WATCHDOG_1_watchdog_timeout_value_SHIFT 0
-#define BCHP_SUN_TOP_CTRL_GEN_WATCHDOG_1_watchdog_timeout_value_DEFAULT 0x00000000
-
-/***************************************************************************
- *GENERAL_CTRL_0 - General control register 0
- ***************************************************************************/
-/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_31 [31:31] */
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_31_MASK 0x80000000
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_31_SHIFT 31
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_31_DEFAULT 0x00000001
-
-/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_30 [30:30] */
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_30_MASK 0x40000000
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_30_SHIFT 30
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_30_DEFAULT 0x00000001
-
-/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_29 [29:29] */
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_29_MASK 0x20000000
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_29_SHIFT 29
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_29_DEFAULT 0x00000001
-
-/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_28 [28:28] */
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_28_MASK 0x10000000
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_28_SHIFT 28
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_28_DEFAULT 0x00000001
-
-/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_27 [27:27] */
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_27_MASK 0x08000000
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_27_SHIFT 27
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_27_DEFAULT 0x00000001
-
-/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_26 [26:26] */
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_26_MASK 0x04000000
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_26_SHIFT 26
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_26_DEFAULT 0x00000001
-
-/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_25 [25:25] */
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_25_MASK 0x02000000
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_25_SHIFT 25
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_25_DEFAULT 0x00000001
-
-/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_24 [24:24] */
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_24_MASK 0x01000000
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_24_SHIFT 24
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_24_DEFAULT 0x00000001
-
-/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_23 [23:23] */
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_23_MASK 0x00800000
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_23_SHIFT 23
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_23_DEFAULT 0x00000001
-
-/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_22 [22:22] */
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_22_MASK 0x00400000
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_22_SHIFT 22
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_22_DEFAULT 0x00000001
-
-/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_21 [21:21] */
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_21_MASK 0x00200000
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_21_SHIFT 21
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_21_DEFAULT 0x00000001
-
-/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_20 [20:20] */
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_20_MASK 0x00100000
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_20_SHIFT 20
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_20_DEFAULT 0x00000001
-
-/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_19 [19:19] */
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_19_MASK 0x00080000
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_19_SHIFT 19
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_19_DEFAULT 0x00000001
-
-/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_18 [18:18] */
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_18_MASK 0x00040000
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_18_SHIFT 18
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_18_DEFAULT 0x00000001
-
-/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_17 [17:17] */
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_17_MASK 0x00020000
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_17_SHIFT 17
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_17_DEFAULT 0x00000001
-
-/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_16 [16:16] */
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_16_MASK 0x00010000
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_16_SHIFT 16
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_16_DEFAULT 0x00000001
-
-/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_15 [15:15] */
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_15_MASK 0x00008000
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_15_SHIFT 15
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_15_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_14 [14:14] */
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_14_MASK 0x00004000
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_14_SHIFT 14
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_14_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_13 [13:13] */
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_13_MASK 0x00002000
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_13_SHIFT 13
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_13_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_12 [12:12] */
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_12_MASK 0x00001000
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_12_SHIFT 12
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_12_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_11 [11:11] */
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_11_MASK 0x00000800
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_11_SHIFT 11
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_11_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_10 [10:10] */
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_10_MASK 0x00000400
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_10_SHIFT 10
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_10_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_9 [09:09] */
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_9_MASK 0x00000200
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_9_SHIFT 9
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_9_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_8 [08:08] */
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_8_MASK 0x00000100
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_8_SHIFT 8
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_8_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_7 [07:07] */
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_7_MASK 0x00000080
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_7_SHIFT 7
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_7_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_6 [06:06] */
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_6_MASK 0x00000040
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_6_SHIFT 6
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_6_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_5 [05:05] */
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_5_MASK 0x00000020
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_5_SHIFT 5
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_5_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: ana_detect_sdio_1_pd [04:04] */
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_ana_detect_sdio_1_pd_MASK 0x00000010
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_ana_detect_sdio_1_pd_SHIFT 4
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_ana_detect_sdio_1_pd_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: ana_detect_sdio_0_pd [03:03] */
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_ana_detect_sdio_0_pd_MASK 0x00000008
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_ana_detect_sdio_0_pd_SHIFT 3
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_ana_detect_sdio_0_pd_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: sdio_1_pad_modehv_override [02:02] */
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_sdio_1_pad_modehv_override_MASK 0x00000004
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_sdio_1_pad_modehv_override_SHIFT 2
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_sdio_1_pad_modehv_override_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: sdio_0_pad_modehv_override [01:01] */
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_sdio_0_pad_modehv_override_MASK 0x00000002
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_sdio_0_pad_modehv_override_SHIFT 1
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_sdio_0_pad_modehv_override_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: sata_phy_disable [00:00] */
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_sata_phy_disable_MASK 0x00000001
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_sata_phy_disable_SHIFT 0
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_sata_phy_disable_DEFAULT 0x00000001
-
-/***************************************************************************
- *GENERAL_CTRL_1 - General control register 1
- ***************************************************************************/
-/* SUN_TOP_CTRL :: GENERAL_CTRL_1 :: reserved0 [31:02] */
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_reserved0_MASK 0xfffffffc
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_reserved0_SHIFT 2
-
-/* SUN_TOP_CTRL :: GENERAL_CTRL_1 :: general_ctrl1_1 [01:01] */
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_1_MASK 0x00000002
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_1_SHIFT 1
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_1_DEFAULT 0x00000001
-
-/* SUN_TOP_CTRL :: GENERAL_CTRL_1 :: general_ctrl1_0 [00:00] */
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_0_MASK 0x00000001
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_0_SHIFT 0
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_0_DEFAULT 0x00000000
-
-/***************************************************************************
- *GENERAL_CTRL_2 - General control register 2
- ***************************************************************************/
-/* SUN_TOP_CTRL :: GENERAL_CTRL_2 :: reserved0 [31:02] */
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_2_reserved0_MASK 0xfffffffc
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_2_reserved0_SHIFT 2
-
-/* SUN_TOP_CTRL :: GENERAL_CTRL_2 :: general_ctrl2_1 [01:01] */
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_2_general_ctrl2_1_MASK 0x00000002
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_2_general_ctrl2_1_SHIFT 1
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_2_general_ctrl2_1_DEFAULT 0x00000001
-
-/* SUN_TOP_CTRL :: GENERAL_CTRL_2 :: general_ctrl2_0 [00:00] */
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_2_general_ctrl2_0_MASK 0x00000001
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_2_general_ctrl2_0_SHIFT 0
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_2_general_ctrl2_0_DEFAULT 0x00000000
-
-/***************************************************************************
- *GENERAL_CTRL_3 - General control register 3
- ***************************************************************************/
-/* SUN_TOP_CTRL :: GENERAL_CTRL_3 :: reserved0 [31:02] */
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_3_reserved0_MASK 0xfffffffc
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_3_reserved0_SHIFT 2
-
-/* SUN_TOP_CTRL :: GENERAL_CTRL_3 :: general_ctrl3_1 [01:01] */
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_3_general_ctrl3_1_MASK 0x00000002
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_3_general_ctrl3_1_SHIFT 1
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_3_general_ctrl3_1_DEFAULT 0x00000001
-
-/* SUN_TOP_CTRL :: GENERAL_CTRL_3 :: general_ctrl3_0 [00:00] */
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_3_general_ctrl3_0_MASK 0x00000001
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_3_general_ctrl3_0_SHIFT 0
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_3_general_ctrl3_0_DEFAULT 0x00000000
-
-/***************************************************************************
- *GENERAL_CTRL_4 - General control register 4
- ***************************************************************************/
-/* SUN_TOP_CTRL :: GENERAL_CTRL_4 :: reserved0 [31:02] */
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_4_reserved0_MASK 0xfffffffc
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_4_reserved0_SHIFT 2
-
-/* SUN_TOP_CTRL :: GENERAL_CTRL_4 :: general_ctrl4_1 [01:01] */
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_4_general_ctrl4_1_MASK 0x00000002
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_4_general_ctrl4_1_SHIFT 1
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_4_general_ctrl4_1_DEFAULT 0x00000001
-
-/* SUN_TOP_CTRL :: GENERAL_CTRL_4 :: general_ctrl4_0 [00:00] */
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_4_general_ctrl4_0_MASK 0x00000001
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_4_general_ctrl4_0_SHIFT 0
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_4_general_ctrl4_0_DEFAULT 0x00000000
-
-/***************************************************************************
- *GENERAL_CTRL_5 - General control register 5
- ***************************************************************************/
-/* SUN_TOP_CTRL :: GENERAL_CTRL_5 :: reserved0 [31:02] */
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_5_reserved0_MASK 0xfffffffc
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_5_reserved0_SHIFT 2
-
-/* SUN_TOP_CTRL :: GENERAL_CTRL_5 :: general_ctrl5_1 [01:01] */
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_5_general_ctrl5_1_MASK 0x00000002
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_5_general_ctrl5_1_SHIFT 1
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_5_general_ctrl5_1_DEFAULT 0x00000001
-
-/* SUN_TOP_CTRL :: GENERAL_CTRL_5 :: general_ctrl5_0 [00:00] */
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_5_general_ctrl5_0_MASK 0x00000001
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_5_general_ctrl5_0_SHIFT 0
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_5_general_ctrl5_0_DEFAULT 0x00000000
-
-/***************************************************************************
- *GENERAL_STATUS_0 - General status register 0
- ***************************************************************************/
-/* SUN_TOP_CTRL :: GENERAL_STATUS_0 :: reserved0 [31:08] */
-#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0_reserved0_MASK 0xffffff00
-#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0_reserved0_SHIFT 8
-
-/* SUN_TOP_CTRL :: GENERAL_STATUS_0 :: general_status0_7 [07:07] */
-#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0_general_status0_7_MASK 0x00000080
-#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0_general_status0_7_SHIFT 7
-
-/* SUN_TOP_CTRL :: GENERAL_STATUS_0 :: general_status0_6 [06:06] */
-#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0_general_status0_6_MASK 0x00000040
-#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0_general_status0_6_SHIFT 6
-
-/* SUN_TOP_CTRL :: GENERAL_STATUS_0 :: general_status0_5 [05:05] */
-#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0_general_status0_5_MASK 0x00000020
-#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0_general_status0_5_SHIFT 5
-
-/* SUN_TOP_CTRL :: GENERAL_STATUS_0 :: general_status0_4 [04:04] */
-#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0_general_status0_4_MASK 0x00000010
-#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0_general_status0_4_SHIFT 4
-
-/* SUN_TOP_CTRL :: GENERAL_STATUS_0 :: general_status0_3 [03:03] */
-#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0_general_status0_3_MASK 0x00000008
-#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0_general_status0_3_SHIFT 3
-
-/* SUN_TOP_CTRL :: GENERAL_STATUS_0 :: general_status0_2 [02:02] */
-#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0_general_status0_2_MASK 0x00000004
-#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0_general_status0_2_SHIFT 2
-
-/* SUN_TOP_CTRL :: GENERAL_STATUS_0 :: general_status0_1 [01:01] */
-#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0_general_status0_1_MASK 0x00000002
-#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0_general_status0_1_SHIFT 1
-
-/* SUN_TOP_CTRL :: GENERAL_STATUS_0 :: hif_strap_invalid [00:00] */
-#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0_hif_strap_invalid_MASK 0x00000001
-#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0_hif_strap_invalid_SHIFT 0
-
-/***************************************************************************
- *GENERAL_STATUS_1 - General status register 1
- ***************************************************************************/
-/* SUN_TOP_CTRL :: GENERAL_STATUS_1 :: reserved0 [31:02] */
-#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_1_reserved0_MASK 0xfffffffc
-#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_1_reserved0_SHIFT 2
-
-/* SUN_TOP_CTRL :: GENERAL_STATUS_1 :: general_status1_1 [01:01] */
-#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_1_general_status1_1_MASK 0x00000002
-#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_1_general_status1_1_SHIFT 1
-
-/* SUN_TOP_CTRL :: GENERAL_STATUS_1 :: general_status1_0 [00:00] */
-#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_1_general_status1_0_MASK 0x00000001
-#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_1_general_status1_0_SHIFT 0
-
-/***************************************************************************
- *GENERAL_STATUS_2 - General status register 2
- ***************************************************************************/
-/* SUN_TOP_CTRL :: GENERAL_STATUS_2 :: reserved0 [31:02] */
-#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_2_reserved0_MASK 0xfffffffc
-#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_2_reserved0_SHIFT 2
-
-/* SUN_TOP_CTRL :: GENERAL_STATUS_2 :: general_status2_1 [01:01] */
-#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_2_general_status2_1_MASK 0x00000002
-#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_2_general_status2_1_SHIFT 1
-
-/* SUN_TOP_CTRL :: GENERAL_STATUS_2 :: general_status2_0 [00:00] */
-#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_2_general_status2_0_MASK 0x00000001
-#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_2_general_status2_0_SHIFT 0
-
-/***************************************************************************
- *GENERAL_CTRL_NO_SCAN_0 - General control register without scan 0
- ***************************************************************************/
-/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: reserved0 [31:30] */
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_reserved0_MASK 0xc0000000
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_reserved0_SHIFT 30
-
-/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: tsio_pad_amp_en [29:29] */
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_tsio_pad_amp_en_MASK 0x20000000
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_tsio_pad_amp_en_SHIFT 29
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_tsio_pad_amp_en_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: tsio_pad_sel_gmii [28:28] */
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_tsio_pad_sel_gmii_MASK 0x10000000
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_tsio_pad_sel_gmii_SHIFT 28
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_tsio_pad_sel_gmii_DEFAULT 0x00000001
-
-/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: tsio_pad_modehv [27:27] */
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_tsio_pad_modehv_MASK 0x08000000
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_tsio_pad_modehv_SHIFT 27
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_tsio_pad_modehv_DEFAULT 0x00000001
-
-/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: tsio_pad_sel [26:24] */
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_tsio_pad_sel_MASK 0x07000000
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_tsio_pad_sel_SHIFT 24
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_tsio_pad_sel_DEFAULT 0x00000003
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_tsio_pad_sel_DRIVE_2MA 0
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_tsio_pad_sel_DRIVE_4MA 1
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_tsio_pad_sel_DRIVE_6MA 2
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_tsio_pad_sel_DRIVE_8MA 3
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_tsio_pad_sel_DRIVE_10MA 4
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_tsio_pad_sel_DRIVE_12MA 5
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_tsio_pad_sel_DRIVE_14MA 6
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_tsio_pad_sel_DRIVE_16MA 7
-
-/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: reserved1 [23:06] */
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_reserved1_MASK 0x00ffffc0
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_reserved1_SHIFT 6
-
-/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: rgmii_1_pad_amp_en [05:05] */
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_rgmii_1_pad_amp_en_MASK 0x00000020
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_rgmii_1_pad_amp_en_SHIFT 5
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_rgmii_1_pad_amp_en_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: rgmii_1_pad_sel_gmii [04:04] */
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_rgmii_1_pad_sel_gmii_MASK 0x00000010
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_rgmii_1_pad_sel_gmii_SHIFT 4
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_rgmii_1_pad_sel_gmii_DEFAULT 0x00000001
-
-/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: rgmii_1_pad_modehv [03:03] */
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_rgmii_1_pad_modehv_MASK 0x00000008
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_rgmii_1_pad_modehv_SHIFT 3
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_rgmii_1_pad_modehv_DEFAULT 0x00000001
-
-/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: rgmii_1_pad_sel [02:00] */
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_rgmii_1_pad_sel_MASK 0x00000007
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_rgmii_1_pad_sel_SHIFT 0
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_rgmii_1_pad_sel_DEFAULT 0x00000003
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_rgmii_1_pad_sel_DRIVE_2MA 0
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_rgmii_1_pad_sel_DRIVE_4MA 1
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_rgmii_1_pad_sel_DRIVE_6MA 2
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_rgmii_1_pad_sel_DRIVE_8MA 3
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_rgmii_1_pad_sel_DRIVE_10MA 4
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_rgmii_1_pad_sel_DRIVE_12MA 5
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_rgmii_1_pad_sel_DRIVE_14MA 6
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_rgmii_1_pad_sel_DRIVE_16MA 7
-
-/***************************************************************************
- *GENERAL_CTRL_NO_SCAN_1 - General control register without scan 1
- ***************************************************************************/
-/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_1 :: reserved0 [31:29] */
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_reserved0_MASK 0xe0000000
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_reserved0_SHIFT 29
-
-/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_1 :: pad_mode_gpio_060 [28:28] */
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_060_MASK 0x10000000
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_060_SHIFT 28
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_060_DEFAULT 0x00000001
-
-/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_1 :: pad_mode_gpio_059 [27:27] */
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_059_MASK 0x08000000
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_059_SHIFT 27
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_059_DEFAULT 0x00000001
-
-/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_1 :: pad_mode_gpio_058 [26:26] */
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_058_MASK 0x04000000
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_058_SHIFT 26
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_058_DEFAULT 0x00000001
-
-/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_1 :: pad_mode_gpio_057 [25:25] */
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_057_MASK 0x02000000
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_057_SHIFT 25
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_057_DEFAULT 0x00000001
-
-/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_1 :: pad_mode_gpio_056 [24:24] */
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_056_MASK 0x01000000
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_056_SHIFT 24
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_056_DEFAULT 0x00000001
-
-/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_1 :: pad_mode_gpio_055 [23:23] */
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_055_MASK 0x00800000
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_055_SHIFT 23
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_055_DEFAULT 0x00000001
-
-/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_1 :: pad_mode_gpio_054 [22:22] */
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_054_MASK 0x00400000
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_054_SHIFT 22
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_054_DEFAULT 0x00000001
-
-/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_1 :: pad_mode_gpio_053 [21:21] */
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_053_MASK 0x00200000
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_053_SHIFT 21
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_053_DEFAULT 0x00000001
-
-/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_1 :: pad_mode_gpio_052 [20:20] */
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_052_MASK 0x00100000
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_052_SHIFT 20
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_052_DEFAULT 0x00000001
-
-/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_1 :: pad_mode_gpio_051 [19:19] */
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_051_MASK 0x00080000
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_051_SHIFT 19
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_051_DEFAULT 0x00000001
-
-/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_1 :: pad_mode_gpio_050 [18:18] */
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_050_MASK 0x00040000
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_050_SHIFT 18
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_050_DEFAULT 0x00000001
-
-/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_1 :: pad_mode_gpio_049 [17:17] */
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_049_MASK 0x00020000
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_049_SHIFT 17
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_049_DEFAULT 0x00000001
-
-/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_1 :: pad_mode_gpio_048 [16:16] */
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_048_MASK 0x00010000
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_048_SHIFT 16
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_048_DEFAULT 0x00000001
-
-/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_1 :: pad_mode_gpio_047 [15:15] */
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_047_MASK 0x00008000
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_047_SHIFT 15
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_047_DEFAULT 0x00000001
-
-/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_1 :: pad_mode_gpio_046 [14:14] */
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_046_MASK 0x00004000
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_046_SHIFT 14
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_046_DEFAULT 0x00000001
-
-/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_1 :: pad_mode_gpio_045 [13:13] */
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_045_MASK 0x00002000
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_045_SHIFT 13
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_045_DEFAULT 0x00000001
-
-/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_1 :: pad_mode_gpio_044 [12:12] */
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_044_MASK 0x00001000
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_044_SHIFT 12
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_044_DEFAULT 0x00000001
-
-/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_1 :: pad_mode_gpio_043 [11:11] */
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_043_MASK 0x00000800
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_043_SHIFT 11
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_043_DEFAULT 0x00000001
-
-/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_1 :: pad_mode_gpio_042 [10:10] */
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_042_MASK 0x00000400
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_042_SHIFT 10
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_042_DEFAULT 0x00000001
-
-/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_1 :: pad_mode_gpio_041 [09:09] */
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_041_MASK 0x00000200
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_041_SHIFT 9
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_041_DEFAULT 0x00000001
-
-/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_1 :: pad_mode_gpio_040 [08:08] */
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_040_MASK 0x00000100
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_040_SHIFT 8
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_040_DEFAULT 0x00000001
-
-/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_1 :: pad_mode_gpio_039 [07:07] */
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_039_MASK 0x00000080
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_039_SHIFT 7
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_039_DEFAULT 0x00000001
-
-/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_1 :: pad_mode_gpio_038 [06:06] */
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_038_MASK 0x00000040
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_038_SHIFT 6
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_038_DEFAULT 0x00000001
-
-/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_1 :: pad_mode_gpio_037 [05:05] */
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_037_MASK 0x00000020
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_037_SHIFT 5
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_037_DEFAULT 0x00000001
-
-/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_1 :: pad_mode_gpio_036 [04:04] */
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_036_MASK 0x00000010
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_036_SHIFT 4
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_036_DEFAULT 0x00000001
-
-/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_1 :: pad_mode_gpio_035 [03:03] */
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_035_MASK 0x00000008
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_035_SHIFT 3
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_035_DEFAULT 0x00000001
-
-/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_1 :: pad_mode_gpio_034 [02:02] */
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_034_MASK 0x00000004
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_034_SHIFT 2
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_034_DEFAULT 0x00000001
-
-/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_1 :: pad_mode_gpio_033 [01:01] */
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_033_MASK 0x00000002
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_033_SHIFT 1
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_033_DEFAULT 0x00000001
-
-/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_1 :: pad_mode_gpio_032 [00:00] */
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_032_MASK 0x00000001
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_032_SHIFT 0
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_032_DEFAULT 0x00000001
-
-/***************************************************************************
- *GENERAL_CTRL_NO_SCAN_2 - General control register without scan 2
- ***************************************************************************/
-/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_2 :: reserved0 [31:28] */
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_reserved0_MASK 0xf0000000
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_reserved0_SHIFT 28
-
-/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_2 :: emmc_pad_slew [27:27] */
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_emmc_pad_slew_MASK 0x08000000
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_emmc_pad_slew_SHIFT 27
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_emmc_pad_slew_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_2 :: emmc_pad_sel [26:24] */
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_emmc_pad_sel_MASK 0x07000000
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_emmc_pad_sel_SHIFT 24
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_emmc_pad_sel_DEFAULT 0x00000003
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_emmc_pad_sel_DRIVE_2MA 0
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_emmc_pad_sel_DRIVE_4MA 1
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_emmc_pad_sel_DRIVE_6MA 2
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_emmc_pad_sel_DRIVE_8MA 3
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_emmc_pad_sel_DRIVE_10MA 4
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_emmc_pad_sel_DRIVE_12MA 5
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_emmc_pad_sel_DRIVE_14MA 6
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_emmc_pad_sel_DRIVE_16MA 7
-
-/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_2 :: bspi_pad_src [23:23] */
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_bspi_pad_src_MASK 0x00800000
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_bspi_pad_src_SHIFT 23
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_bspi_pad_src_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_2 :: bspi_pad_sel [22:20] */
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_bspi_pad_sel_MASK 0x00700000
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_bspi_pad_sel_SHIFT 20
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_bspi_pad_sel_DEFAULT 0x00000003
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_bspi_pad_sel_DRIVE_2MA 0
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_bspi_pad_sel_DRIVE_4MA 1
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_bspi_pad_sel_DRIVE_6MA 2
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_bspi_pad_sel_DRIVE_8MA 3
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_bspi_pad_sel_DRIVE_10MA 4
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_bspi_pad_sel_DRIVE_12MA 5
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_bspi_pad_sel_DRIVE_14MA 6
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_bspi_pad_sel_DRIVE_16MA 7
-
-/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_2 :: reserved1 [19:16] */
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_reserved1_MASK 0x000f0000
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_reserved1_SHIFT 16
-
-/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_2 :: ebi_3_pad_src [15:15] */
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_3_pad_src_MASK 0x00008000
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_3_pad_src_SHIFT 15
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_3_pad_src_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_2 :: ebi_3_pad_sel [14:12] */
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_3_pad_sel_MASK 0x00007000
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_3_pad_sel_SHIFT 12
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_3_pad_sel_DEFAULT 0x00000003
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_3_pad_sel_DRIVE_2MA 0
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_3_pad_sel_DRIVE_4MA 1
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_3_pad_sel_DRIVE_6MA 2
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_3_pad_sel_DRIVE_8MA 3
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_3_pad_sel_DRIVE_10MA 4
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_3_pad_sel_DRIVE_12MA 5
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_3_pad_sel_DRIVE_14MA 6
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_3_pad_sel_DRIVE_16MA 7
-
-/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_2 :: reserved2 [11:08] */
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_reserved2_MASK 0x00000f00
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_reserved2_SHIFT 8
-
-/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_2 :: ebi_1_pad_src [07:07] */
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_1_pad_src_MASK 0x00000080
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_1_pad_src_SHIFT 7
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_1_pad_src_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_2 :: ebi_1_pad_sel [06:04] */
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_1_pad_sel_MASK 0x00000070
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_1_pad_sel_SHIFT 4
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_1_pad_sel_DEFAULT 0x00000003
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_1_pad_sel_DRIVE_2MA 0
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_1_pad_sel_DRIVE_4MA 1
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_1_pad_sel_DRIVE_6MA 2
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_1_pad_sel_DRIVE_8MA 3
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_1_pad_sel_DRIVE_10MA 4
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_1_pad_sel_DRIVE_12MA 5
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_1_pad_sel_DRIVE_14MA 6
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_1_pad_sel_DRIVE_16MA 7
-
-/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_2 :: ebi_0_pad_src [03:03] */
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_0_pad_src_MASK 0x00000008
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_0_pad_src_SHIFT 3
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_0_pad_src_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_2 :: ebi_0_pad_sel [02:00] */
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_0_pad_sel_MASK 0x00000007
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_0_pad_sel_SHIFT 0
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_0_pad_sel_DEFAULT 0x00000003
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_0_pad_sel_DRIVE_2MA 0
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_0_pad_sel_DRIVE_4MA 1
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_0_pad_sel_DRIVE_6MA 2
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_0_pad_sel_DRIVE_8MA 3
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_0_pad_sel_DRIVE_10MA 4
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_0_pad_sel_DRIVE_12MA 5
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_0_pad_sel_DRIVE_14MA 6
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_0_pad_sel_DRIVE_16MA 7
-
-/***************************************************************************
- *GENERAL_CTRL_NO_SCAN_3 - General control register without scan 3
- ***************************************************************************/
-/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_3 :: reserved0 [31:05] */
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_reserved0_MASK 0xffffffe0
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_reserved0_SHIFT 5
-
-/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_3 :: pad_mode_gpio_018 [04:04] */
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_pad_mode_gpio_018_MASK 0x00000010
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_pad_mode_gpio_018_SHIFT 4
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_pad_mode_gpio_018_DEFAULT 0x00000001
-
-/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_3 :: pad_mode_gpio_017 [03:03] */
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_pad_mode_gpio_017_MASK 0x00000008
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_pad_mode_gpio_017_SHIFT 3
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_pad_mode_gpio_017_DEFAULT 0x00000001
-
-/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_3 :: pad_mode_gpio_016 [02:02] */
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_pad_mode_gpio_016_MASK 0x00000004
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_pad_mode_gpio_016_SHIFT 2
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_pad_mode_gpio_016_DEFAULT 0x00000001
-
-/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_3 :: pad_mode_gpio_015 [01:01] */
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_pad_mode_gpio_015_MASK 0x00000002
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_pad_mode_gpio_015_SHIFT 1
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_pad_mode_gpio_015_DEFAULT 0x00000001
-
-/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_3 :: pad_mode_gpio_014 [00:00] */
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_pad_mode_gpio_014_MASK 0x00000001
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_pad_mode_gpio_014_SHIFT 0
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_pad_mode_gpio_014_DEFAULT 0x00000001
-
-/***************************************************************************
- *GENERAL_CTRL_NO_SCAN_4 - General control register without scan 4
- ***************************************************************************/
-/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_4 :: reserved0 [31:02] */
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_4_reserved0_MASK 0xfffffffc
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_4_reserved0_SHIFT 2
-
-/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_4 :: general_ctrl_no_scan4_1 [01:01] */
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_4_general_ctrl_no_scan4_1_MASK 0x00000002
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_4_general_ctrl_no_scan4_1_SHIFT 1
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_4_general_ctrl_no_scan4_1_DEFAULT 0x00000001
-
-/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_4 :: general_ctrl_no_scan4_0 [00:00] */
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_4_general_ctrl_no_scan4_0_MASK 0x00000001
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_4_general_ctrl_no_scan4_0_SHIFT 0
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_4_general_ctrl_no_scan4_0_DEFAULT 0x00000000
-
-/***************************************************************************
- *GENERAL_CTRL_NO_SCAN_5 - General control register without scan 5
- ***************************************************************************/
-/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_5 :: reserved0 [31:08] */
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_reserved0_MASK 0xffffff00
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_reserved0_SHIFT 8
-
-/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_5 :: egphy_test_pin_mux_sel [07:07] */
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_egphy_test_pin_mux_sel_MASK 0x00000080
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_egphy_test_pin_mux_sel_SHIFT 7
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_egphy_test_pin_mux_sel_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_5 :: test_thp_hys_en [06:06] */
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_test_thp_hys_en_MASK 0x00000040
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_test_thp_hys_en_SHIFT 6
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_test_thp_hys_en_DEFAULT 0x00000001
-
-/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_5 :: test_thp_oeb [05:05] */
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_test_thp_oeb_MASK 0x00000020
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_test_thp_oeb_SHIFT 5
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_test_thp_oeb_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_5 :: test_thp_do [04:04] */
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_test_thp_do_MASK 0x00000010
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_test_thp_do_SHIFT 4
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_test_thp_do_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_5 :: test_drive_src [03:03] */
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_test_drive_src_MASK 0x00000008
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_test_drive_src_SHIFT 3
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_test_drive_src_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_5 :: test_drive_sel [02:00] */
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_test_drive_sel_MASK 0x00000007
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_test_drive_sel_SHIFT 0
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_test_drive_sel_DEFAULT 0x00000003
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_test_drive_sel_DRIVE_2MA 0
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_test_drive_sel_DRIVE_4MA 1
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_test_drive_sel_DRIVE_6MA 2
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_test_drive_sel_DRIVE_8MA 3
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_test_drive_sel_DRIVE_10MA 4
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_test_drive_sel_DRIVE_12MA 5
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_test_drive_sel_DRIVE_14MA 6
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_test_drive_sel_DRIVE_16MA 7
-
-/***************************************************************************
- *GENERAL_STATUS_3 - General status register 3
- ***************************************************************************/
-/* SUN_TOP_CTRL :: GENERAL_STATUS_3 :: cpu_system_counter [31:00] */
-#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_3_cpu_system_counter_MASK 0xffffffff
-#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_3_cpu_system_counter_SHIFT 0
-
-/***************************************************************************
- *GENERAL_STATUS_4 - General status register 4
- ***************************************************************************/
-/* SUN_TOP_CTRL :: GENERAL_STATUS_4 :: cpu_system_counter [31:00] */
-#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_4_cpu_system_counter_MASK 0xffffffff
-#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_4_cpu_system_counter_SHIFT 0
-
-/***************************************************************************
- *PIN_MUX_CTRL_0 - Pinmux control register 0
- ***************************************************************************/
-/* SUN_TOP_CTRL :: PIN_MUX_CTRL_0 :: ebi_data_07 [31:28] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_ebi_data_07_MASK 0xf0000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_ebi_data_07_SHIFT 28
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_ebi_data_07_DEFAULT 0x00000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_ebi_data_07_EBI_DATA_07 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_ebi_data_07_ALT_TP_IN_07 1
-
-/* SUN_TOP_CTRL :: PIN_MUX_CTRL_0 :: ebi_data_06 [27:24] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_ebi_data_06_MASK 0x0f000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_ebi_data_06_SHIFT 24
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_ebi_data_06_DEFAULT 0x00000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_ebi_data_06_EBI_DATA_06 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_ebi_data_06_ALT_TP_IN_06 1
-
-/* SUN_TOP_CTRL :: PIN_MUX_CTRL_0 :: ebi_data_05 [23:20] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_ebi_data_05_MASK 0x00f00000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_ebi_data_05_SHIFT 20
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_ebi_data_05_DEFAULT 0x00000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_ebi_data_05_EBI_DATA_05 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_ebi_data_05_ALT_TP_IN_05 1
-
-/* SUN_TOP_CTRL :: PIN_MUX_CTRL_0 :: ebi_data_04 [19:16] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_ebi_data_04_MASK 0x000f0000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_ebi_data_04_SHIFT 16
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_ebi_data_04_DEFAULT 0x00000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_ebi_data_04_EBI_DATA_04 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_ebi_data_04_ALT_TP_IN_04 1
-
-/* SUN_TOP_CTRL :: PIN_MUX_CTRL_0 :: ebi_data_03 [15:12] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_ebi_data_03_MASK 0x0000f000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_ebi_data_03_SHIFT 12
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_ebi_data_03_DEFAULT 0x00000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_ebi_data_03_EBI_DATA_03 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_ebi_data_03_ALT_TP_IN_03 1
-
-/* SUN_TOP_CTRL :: PIN_MUX_CTRL_0 :: ebi_data_02 [11:08] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_ebi_data_02_MASK 0x00000f00
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_ebi_data_02_SHIFT 8
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_ebi_data_02_DEFAULT 0x00000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_ebi_data_02_EBI_DATA_02 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_ebi_data_02_ALT_TP_IN_02 1
-
-/* SUN_TOP_CTRL :: PIN_MUX_CTRL_0 :: ebi_data_01 [07:04] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_ebi_data_01_MASK 0x000000f0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_ebi_data_01_SHIFT 4
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_ebi_data_01_DEFAULT 0x00000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_ebi_data_01_EBI_DATA_01 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_ebi_data_01_ALT_TP_IN_01 1
-
-/* SUN_TOP_CTRL :: PIN_MUX_CTRL_0 :: ebi_data_00 [03:00] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_ebi_data_00_MASK 0x0000000f
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_ebi_data_00_SHIFT 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_ebi_data_00_DEFAULT 0x00000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_ebi_data_00_EBI_DATA_00 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_ebi_data_00_ALT_TP_IN_00 1
-
-/***************************************************************************
- *PIN_MUX_CTRL_1 - Pinmux control register 1
- ***************************************************************************/
-/* SUN_TOP_CTRL :: PIN_MUX_CTRL_1 :: gpio_000 [31:28] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_000_MASK 0xf0000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_000_SHIFT 28
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_000_DEFAULT 0x00000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_000_GPIO_000 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_000_RGMII1_RX_CLK 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_000_EXT_IRQB_6 2
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_000_TP_IN_00 3
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_000_PM_GPIO_000 4
-
-/* SUN_TOP_CTRL :: PIN_MUX_CTRL_1 :: emmc1_clk [27:24] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_emmc1_clk_MASK 0x0f000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_emmc1_clk_SHIFT 24
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_emmc1_clk_DEFAULT 0x00000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_emmc1_clk_EMMC1_CLK 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_emmc1_clk_PM_EMMC1_CLK 1
-
-/* SUN_TOP_CTRL :: PIN_MUX_CTRL_1 :: emmc1_cmd [23:20] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_emmc1_cmd_MASK 0x00f00000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_emmc1_cmd_SHIFT 20
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_emmc1_cmd_DEFAULT 0x00000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_emmc1_cmd_EMMC1_CMD 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_emmc1_cmd_PM_EMMC1_CMD 1
-
-/* SUN_TOP_CTRL :: PIN_MUX_CTRL_1 :: ebi_nand_dqs [19:16] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_ebi_nand_dqs_MASK 0x000f0000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_ebi_nand_dqs_SHIFT 16
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_ebi_nand_dqs_DEFAULT 0x00000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_ebi_nand_dqs_EBI_NAND_DQS 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_ebi_nand_dqs_PM_EBI_NAND_DQS 1
-
-/* SUN_TOP_CTRL :: PIN_MUX_CTRL_1 :: ebi_waitb [15:12] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_ebi_waitb_MASK 0x0000f000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_ebi_waitb_SHIFT 12
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_ebi_waitb_DEFAULT 0x00000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_ebi_waitb_EBI_WAITB 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_ebi_waitb_PM_EBI_WAITB 1
-
-/* SUN_TOP_CTRL :: PIN_MUX_CTRL_1 :: ebi_cs2b [11:08] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_ebi_cs2b_MASK 0x00000f00
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_ebi_cs2b_SHIFT 8
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_ebi_cs2b_DEFAULT 0x00000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_ebi_cs2b_EBI_CS2B 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_ebi_cs2b_ALT_TP_IN_10 1
-
-/* SUN_TOP_CTRL :: PIN_MUX_CTRL_1 :: ebi_cs1b [07:04] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_ebi_cs1b_MASK 0x000000f0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_ebi_cs1b_SHIFT 4
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_ebi_cs1b_DEFAULT 0x00000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_ebi_cs1b_EBI_CS1B 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_ebi_cs1b_ALT_TP_IN_09 1
-
-/* SUN_TOP_CTRL :: PIN_MUX_CTRL_1 :: ebi_cs0b [03:00] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_ebi_cs0b_MASK 0x0000000f
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_ebi_cs0b_SHIFT 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_ebi_cs0b_DEFAULT 0x00000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_ebi_cs0b_EBI_CS0B 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_ebi_cs0b_ALT_TP_IN_08 1
-
-/***************************************************************************
- *PIN_MUX_CTRL_2 - Pinmux control register 2
- ***************************************************************************/
-/* SUN_TOP_CTRL :: PIN_MUX_CTRL_2 :: gpio_008 [31:28] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_008_MASK 0xf0000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_008_SHIFT 28
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_008_DEFAULT 0x00000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_008_GPIO_008 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_008_RGMII1_TXD_00 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_008_UART_RXD_1 2
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_008_SC0_PRES 3
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_008_TP_IN_08 4
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_008_PM_GPIO_008 5
-
-/* SUN_TOP_CTRL :: PIN_MUX_CTRL_2 :: gpio_007 [27:24] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_007_MASK 0x0f000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_007_SHIFT 24
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_007_DEFAULT 0x00000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_007_GPIO_007 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_007_MII_RXEN_RGMII1_RXCTL 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_007_UART_RTS_1 2
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_007_SC0_RST 3
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_007_EXT_IRQB_4 4
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_007_TP_IN_07 5
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_007_PM_GPIO_007 6
-
-/* SUN_TOP_CTRL :: PIN_MUX_CTRL_2 :: gpio_006 [23:20] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_006_MASK 0x00f00000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_006_SHIFT 20
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_006_DEFAULT 0x00000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_006_GPIO_006 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_006_RGMII1_TX_CLK 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_006_UART_CTS_1 2
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_006_SC0_CLK 3
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_006_TP_IN_06 4
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_006_PM_GPIO_006 5
-
-/* SUN_TOP_CTRL :: PIN_MUX_CTRL_2 :: gpio_005 [19:16] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_005_MASK 0x000f0000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_005_SHIFT 16
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_005_DEFAULT 0x00000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_005_GPIO_005 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_005_RGMII1_RXD_03 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_005_RMX_SYNC0 2
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_005_SC0_IO 3
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_005_TP_IN_05 4
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_005_PM_GPIO_005 5
-
-/* SUN_TOP_CTRL :: PIN_MUX_CTRL_2 :: gpio_004 [15:12] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_004_MASK 0x0000f000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_004_SHIFT 12
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_004_DEFAULT 0x00000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_004_GPIO_004 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_004_RGMII1_RXD_02 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_004_RMX_DATA0 2
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_004_SC0_VPP 3
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_004_TP_IN_04 4
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_004_PM_GPIO_004 5
-
-/* SUN_TOP_CTRL :: PIN_MUX_CTRL_2 :: gpio_003 [11:08] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_003_MASK 0x00000f00
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_003_SHIFT 8
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_003_DEFAULT 0x00000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_003_GPIO_003 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_003_RGMII1_RXD_01 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_003_RMX_CLK0 2
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_003_SC0_AUX2 3
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_003_VEC_HSYNC_0 4
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_003_TP_IN_03 5
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_003_PM_GPIO_003 6
-
-/* SUN_TOP_CTRL :: PIN_MUX_CTRL_2 :: gpio_002 [07:04] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_002_MASK 0x000000f0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_002_SHIFT 4
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_002_DEFAULT 0x00000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_002_GPIO_002 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_002_RGMII1_RXD_00 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_002_PWM_2 2
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_002_SC0_AUX1 3
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_002_TP_IN_02 4
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_002_PM_GPIO_002 5
-
-/* SUN_TOP_CTRL :: PIN_MUX_CTRL_2 :: gpio_001 [03:00] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_001_MASK 0x0000000f
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_001_SHIFT 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_001_DEFAULT 0x00000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_001_GPIO_001 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_001_MII_TXEN_RGMII1_TXCTL 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_001_IR_IN1 2
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_001_TP_IN_01 3
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_001_PM_GPIO_001 4
-
-/***************************************************************************
- *PIN_MUX_CTRL_3 - Pinmux control register 3
- ***************************************************************************/
-/* SUN_TOP_CTRL :: PIN_MUX_CTRL_3 :: gpio_016 [31:28] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_016_MASK 0xf0000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_016_SHIFT 28
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_016_DEFAULT 0x00000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_016_GPIO_016 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_016_CHIP2POD_CTX 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_016_EBI_ADDR_04 2
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_016_TP_IN_12 3
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_016_PM_GPIO_016 4
-
-/* SUN_TOP_CTRL :: PIN_MUX_CTRL_3 :: gpio_015 [27:24] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_015_MASK 0x0f000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_015_SHIFT 24
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_015_DEFAULT 0x00000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_015_GPIO_015 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_015_CHIP2POD_CRX 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_015_EBI_ADDR_08 2
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_015_ALT_TP_OUT_11 3
-
-/* SUN_TOP_CTRL :: PIN_MUX_CTRL_3 :: gpio_014 [23:20] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_014_MASK 0x00f00000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_014_SHIFT 20
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_014_DEFAULT 0x00000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_014_GPIO_014 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_014_CHIP2POD_DRX 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_014_EBI_ADDR_09 2
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_014_ALT_TP_OUT_10 3
-
-/* SUN_TOP_CTRL :: PIN_MUX_CTRL_3 :: gpio_013 [19:16] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_013_MASK 0x000f0000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_013_SHIFT 16
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_013_DEFAULT 0x00000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_013_GPIO_013 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_013_RGMII1_MDC 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_013_UART_TXD_2 2
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_013_ALT_TP_OUT_09 3
-
-/* SUN_TOP_CTRL :: PIN_MUX_CTRL_3 :: gpio_012 [15:12] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_012_MASK 0x0000f000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_012_SHIFT 12
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_012_DEFAULT 0x00000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_012_GPIO_012 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_012_RGMII1_MDIO 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_012_UART_RXD_2 2
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_012_EXT_IRQB_7 3
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_012_TP_IN_09 4
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_012_PM_GPIO_012 5
-
-/* SUN_TOP_CTRL :: PIN_MUX_CTRL_3 :: gpio_011 [11:08] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_011_MASK 0x00000f00
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_011_SHIFT 8
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_011_DEFAULT 0x00000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_011_GPIO_011 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_011_RGMII1_TXD_03 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_011_UART_RTS_2 2
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_011_VEC_VSYNC_0 3
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_011_ALT_TP_IN_31 4
-
-/* SUN_TOP_CTRL :: PIN_MUX_CTRL_3 :: gpio_010 [07:04] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_010_MASK 0x000000f0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_010_SHIFT 4
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_010_DEFAULT 0x00000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_010_GPIO_010 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_010_RGMII1_TXD_02 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_010_UART_CTS_2 2
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_010_EXT_IRQB_3 3
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_010_TP_IN_10 4
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_010_PM_GPIO_010 5
-
-/* SUN_TOP_CTRL :: PIN_MUX_CTRL_3 :: gpio_009 [03:00] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_009_MASK 0x0000000f
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_009_SHIFT 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_009_DEFAULT 0x00000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_009_GPIO_009 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_009_RGMII1_TXD_01 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_009_UART_TXD_1 2
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_009_SC0_VCC 3
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_009_TP_OUT_00 4
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_009_PM_GPIO_009 5
-
-/***************************************************************************
- *PIN_MUX_CTRL_4 - Pinmux control register 4
- ***************************************************************************/
-/* SUN_TOP_CTRL :: PIN_MUX_CTRL_4 :: gpio_024 [31:28] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_024_MASK 0xf0000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_024_SHIFT 28
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_024_DEFAULT 0x00000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_024_GPIO_024 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_024_PKT_CLK1 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_024_SDIO1_DAT1 2
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_024_VO0_656_5 3
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_024_HCPU_TRACE_RXD 4
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_024_LED_LD_13 5
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_024_TP_IN_19 6
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_024_PM_GPIO_024 7
-
-/* SUN_TOP_CTRL :: PIN_MUX_CTRL_4 :: gpio_023 [27:24] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_023_MASK 0x0f000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_023_SHIFT 24
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_023_DEFAULT 0x00000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_023_GPIO_023 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_023_PKT_VALID0 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_023_SDIO1_DAT0 2
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_023_VO0_656_4 3
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_023_HCPU_TRACE_DATA3 4
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_023_LED_LD_12 5
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_023_TP_IN_18 6
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_023_PM_GPIO_023 7
-
-/* SUN_TOP_CTRL :: PIN_MUX_CTRL_4 :: gpio_022 [23:20] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_022_MASK 0x00f00000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_022_SHIFT 20
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_022_DEFAULT 0x00000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_022_GPIO_022 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_022_PKT_ERROR0 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_022_SDIO1_CLK 2
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_022_VO0_656_3 3
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_022_HCPU_TRACE_DATA2 4
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_022_LED_LD_11 5
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_022_PM_GPIO_022 6
-
-/* SUN_TOP_CTRL :: PIN_MUX_CTRL_4 :: gpio_021 [19:16] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_021_MASK 0x000f0000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_021_SHIFT 16
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_021_DEFAULT 0x00000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_021_GPIO_021 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_021_PKT_SYNC0 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_021_SDIO1_PWR0 2
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_021_VO0_656_2 3
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_021_HCPU_TRACE_DATA1 4
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_021_LED_LD_10 5
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_021_TP_IN_17 6
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_021_PM_GPIO_021 7
-
-/* SUN_TOP_CTRL :: PIN_MUX_CTRL_4 :: gpio_020 [15:12] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_020_MASK 0x0000f000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_020_SHIFT 12
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_020_DEFAULT 0x00000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_020_GPIO_020 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_020_PKT_DATA0 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_020_SDIO1_WPROT 2
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_020_VO0_656_1 3
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_020_HCPU_TRACE_DATA0 4
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_020_LED_LD_9 5
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_020_TP_IN_16 6
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_020_PM_GPIO_020 7
-
-/* SUN_TOP_CTRL :: PIN_MUX_CTRL_4 :: gpio_019 [11:08] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_019_MASK 0x00000f00
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_019_SHIFT 8
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_019_DEFAULT 0x00000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_019_GPIO_019 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_019_PKT_CLK0 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_019_SDIO1_CMD 2
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_019_VO0_656_0 3
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_019_HCPU_TRACE_CLK 4
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_019_LED_LD_8 5
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_019_TP_IN_15 6
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_019_PM_GPIO_019 7
-
-/* SUN_TOP_CTRL :: PIN_MUX_CTRL_4 :: gpio_018 [07:04] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_018_MASK 0x000000f0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_018_SHIFT 4
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_018_DEFAULT 0x00000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_018_GPIO_018 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_018_POD2CHIP_ITX 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_018_EBI_ADDR_05 2
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_018_TP_IN_14 3
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_018_PM_GPIO_018 4
-
-/* SUN_TOP_CTRL :: PIN_MUX_CTRL_4 :: gpio_017 [03:00] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_017_MASK 0x0000000f
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_017_SHIFT 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_017_DEFAULT 0x00000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_017_GPIO_017 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_017_POD2CHIP_QTX 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_017_EBI_ADDR_07 2
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_017_TP_IN_13 3
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_017_PM_GPIO_017 4
-
-/***************************************************************************
- *PIN_MUX_CTRL_5 - Pinmux control register 5
- ***************************************************************************/
-/* SUN_TOP_CTRL :: PIN_MUX_CTRL_5 :: gpio_032 [31:28] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_032_MASK 0xf0000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_032_SHIFT 28
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_032_DEFAULT 0x00000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_032_GPIO_032 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_032_POD2CHIP_MCLKI 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_032_EBI_ADDR_14 2
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_032_SPI_S_SS0B 3
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_032_PPKT_CLK 4
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_032_SW_SPI_S_SS0B 5
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_032_TP_IN_25 6
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_032_PM_GPIO_032 7
-
-/* SUN_TOP_CTRL :: PIN_MUX_CTRL_5 :: gpio_031 [27:24] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_031_MASK 0x0f000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_031_SHIFT 24
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_031_DEFAULT 0x00000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_031_GPIO_031 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_031_UART_TXD_0 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_031_UART_RTS_1 2
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_031_TP_OUT_07 3
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_031_PM_GPIO_031 4
-
-/* SUN_TOP_CTRL :: PIN_MUX_CTRL_5 :: gpio_030 [23:20] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_030_MASK 0x00f00000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_030_SHIFT 20
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_030_DEFAULT 0x00000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_030_GPIO_030 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_030_UART_RXD_0 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_030_UART_CTS_1 2
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_030_TP_IN_23 3
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_030_PM_GPIO_030 4
-
-/* SUN_TOP_CTRL :: PIN_MUX_CTRL_5 :: gpio_029 [19:16] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_029_MASK 0x000f0000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_029_SHIFT 16
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_029_DEFAULT 0x00000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_029_GPIO_029 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_029_EXT_IRQB_0 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_029_TSIO_VCTRL 2
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_029_TP_IN_22 3
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_029_PM_GPIO_029 4
-
-/* SUN_TOP_CTRL :: PIN_MUX_CTRL_5 :: gpio_028 [15:12] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_028_MASK 0x0000f000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_028_SHIFT 12
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_028_DEFAULT 0x00000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_028_GPIO_028 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_028_PKT_VALID1 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_028_SDIO1_LED 2
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_028_EXT_IRQB_1 3
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_028_TP_IN_21 4
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_028_PM_GPIO_028 5
-
-/* SUN_TOP_CTRL :: PIN_MUX_CTRL_5 :: gpio_027 [11:08] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_027_MASK 0x00000f00
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_027_SHIFT 8
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_027_DEFAULT 0x00000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_027_GPIO_027 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_027_PKT_ERROR1 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_027_SDIO1_PRES 2
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_027_VO0_656_CLK 3
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_027_I2S_LR1_OUT 4
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_027_PM_GPIO_027 5
-
-/* SUN_TOP_CTRL :: PIN_MUX_CTRL_5 :: gpio_026 [07:04] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_026_MASK 0x000000f0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_026_SHIFT 4
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_026_DEFAULT 0x00000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_026_GPIO_026 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_026_PKT_SYNC1 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_026_SDIO1_DAT3 2
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_026_VO0_656_7 3
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_026_I2S_DATA1_OUT 4
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_026_LED_LD_15 5
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_026_ALT_TP_IN_12 6
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_026_PM_GPIO_026 7
-
-/* SUN_TOP_CTRL :: PIN_MUX_CTRL_5 :: gpio_025 [03:00] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_025_MASK 0x0000000f
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_025_SHIFT 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_025_DEFAULT 0x00000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_025_GPIO_025 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_025_PKT_DATA1 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_025_SDIO1_DAT2 2
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_025_VO0_656_6 3
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_025_I2S_CLK1_OUT 4
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_025_LED_LD_14 5
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_025_TP_IN_20 6
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_025_PM_GPIO_025 7
-
-/***************************************************************************
- *PIN_MUX_CTRL_6 - Pinmux control register 6
- ***************************************************************************/
-/* SUN_TOP_CTRL :: PIN_MUX_CTRL_6 :: gpio_040 [31:28] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_040_MASK 0xf0000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_040_SHIFT 28
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_040_DEFAULT 0x00000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_040_GPIO_040 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_040_POD2CHIP_MDI0 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_040_PPKT_DATA0 2
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_040_UART_TXD_2 3
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_040_TP_OUT_27 4
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_040_PM_GPIO_040 5
-
-/* SUN_TOP_CTRL :: PIN_MUX_CTRL_6 :: gpio_039 [27:24] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_039_MASK 0x0f000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_039_SHIFT 24
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_039_DEFAULT 0x00000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_039_GPIO_039 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_039_POD2CHIP_MIVAL 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_039_PPKT_VALID 2
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_039_UART_RXD_2 3
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_039_TP_IN_28 4
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_039_PM_GPIO_039 5
-
-/* SUN_TOP_CTRL :: PIN_MUX_CTRL_6 :: gpio_038 [23:20] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_038_MASK 0x00f00000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_038_SHIFT 20
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_038_DEFAULT 0x00000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_038_GPIO_038 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_038_POD2CHIP_MISTRT 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_038_PPKT_SYNC 2
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_038_TP_IN_27 3
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_038_PM_GPIO_038 4
-
-/* SUN_TOP_CTRL :: PIN_MUX_CTRL_6 :: gpio_037 [19:16] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_037_MASK 0x000f0000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_037_SHIFT 16
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_037_DEFAULT 0x00000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_037_GPIO_037 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_037_CHIP2POD_SCTL 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_037_EBI_ADDR_02 2
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_037_ALT_TP_OUT_14 3
-
-/* SUN_TOP_CTRL :: PIN_MUX_CTRL_6 :: gpio_036 [15:12] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_036_MASK 0x0000f000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_036_SHIFT 12
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_036_DEFAULT 0x00000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_036_GPIO_036 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_036_CHIP2POD_SDO 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_036_EBI_ADDR_00 2
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_036_VEC_VSYNC_0 3
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_036_ALT_TP_OUT_13 4
-
-/* SUN_TOP_CTRL :: PIN_MUX_CTRL_6 :: gpio_035 [11:08] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_035_MASK 0x00000f00
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_035_SHIFT 8
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_035_DEFAULT 0x00000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_035_GPIO_035 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_035_POD2CHIP_SDI 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_035_PM_GPIO_035 2
-
-/* SUN_TOP_CTRL :: PIN_MUX_CTRL_6 :: gpio_034 [07:04] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_034_MASK 0x000000f0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_034_SHIFT 4
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_034_DEFAULT 0x00000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_034_GPIO_034 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_034_CHIP2POD_SCLK 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_034_EBI_ADDR_01 2
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_034_TP_IN_26 3
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_034_PM_GPIO_034 4
-
-/* SUN_TOP_CTRL :: PIN_MUX_CTRL_6 :: gpio_033 [03:00] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_033_MASK 0x0000000f
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_033_SHIFT 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_033_DEFAULT 0x00000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_033_GPIO_033 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_033_CHIP2POD_MCLKO 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_033_EBI_ADDR_15 2
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_033_SPI_S_MISO 3
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_033_RMXP_CLK 4
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_033_SW_SPI_S_MISO 5
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_033_ALT_TP_OUT_12 6
-
-/***************************************************************************
- *PIN_MUX_CTRL_7 - Pinmux control register 7
- ***************************************************************************/
-/* SUN_TOP_CTRL :: PIN_MUX_CTRL_7 :: gpio_048 [31:28] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_048_MASK 0xf0000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_048_SHIFT 28
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_048_DEFAULT 0x00000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_048_GPIO_048 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_048_POD2CHIP_MICLK 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_048_PPKT_CLK 2
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_048_POD2CHIP_MCLKI 3
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_048_EBI_ADDR_13 4
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_048_TP_OUT_11 5
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_048_PM_GPIO_048 6
-
-/* SUN_TOP_CTRL :: PIN_MUX_CTRL_7 :: gpio_047 [27:24] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_047_MASK 0x0f000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_047_SHIFT 24
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_047_DEFAULT 0x00000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_047_GPIO_047 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_047_POD2CHIP_MDI7 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_047_PPKT_DATA7 2
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_047_I2S_DATA0_IN 3
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_047_TP_OUT_10 4
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_047_PM_GPIO_047 5
-
-/* SUN_TOP_CTRL :: PIN_MUX_CTRL_7 :: gpio_046 [23:20] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_046_MASK 0x00f00000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_046_SHIFT 20
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_046_DEFAULT 0x00000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_046_GPIO_046 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_046_POD2CHIP_MDI6 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_046_PPKT_DATA6 2
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_046_I2S_CLK0_IN 3
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_046_TP_IN_24 4
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_046_PM_GPIO_046 5
-
-/* SUN_TOP_CTRL :: PIN_MUX_CTRL_7 :: gpio_045 [19:16] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_045_MASK 0x000f0000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_045_SHIFT 16
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_045_DEFAULT 0x00000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_045_GPIO_045 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_045_POD2CHIP_MDI5 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_045_PPKT_DATA5 2
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_045_I2S_LR0_IN 3
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_045_PM_GPIO_045 4
-
-/* SUN_TOP_CTRL :: PIN_MUX_CTRL_7 :: gpio_044 [15:12] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_044_MASK 0x0000f000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_044_SHIFT 12
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_044_DEFAULT 0x00000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_044_GPIO_044 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_044_POD2CHIP_MDI4 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_044_PPKT_DATA4 2
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_044_UART_TXD_0 3
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_044_TP_OUT_08 4
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_044_PM_GPIO_044 5
-
-/* SUN_TOP_CTRL :: PIN_MUX_CTRL_7 :: gpio_043 [11:08] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_043_MASK 0x00000f00
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_043_SHIFT 8
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_043_DEFAULT 0x00000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_043_GPIO_043 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_043_POD2CHIP_MDI3 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_043_PPKT_DATA3 2
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_043_UART_RXD_0 3
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_043_TP_IN_30 4
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_043_PM_GPIO_043 5
-
-/* SUN_TOP_CTRL :: PIN_MUX_CTRL_7 :: gpio_042 [07:04] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_042_MASK 0x000000f0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_042_SHIFT 4
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_042_DEFAULT 0x00000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_042_GPIO_042 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_042_POD2CHIP_MDI2 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_042_PPKT_DATA2 2
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_042_UART_TXD_1 3
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_042_TP_OUT_09 4
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_042_PM_GPIO_042 5
-
-/* SUN_TOP_CTRL :: PIN_MUX_CTRL_7 :: gpio_041 [03:00] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_041_MASK 0x0000000f
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_041_SHIFT 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_041_DEFAULT 0x00000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_041_GPIO_041 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_041_POD2CHIP_MDI1 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_041_PPKT_DATA1 2
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_041_UART_RXD_1 3
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_041_TP_IN_29 4
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_041_PM_GPIO_041 5
-
-/***************************************************************************
- *PIN_MUX_CTRL_8 - Pinmux control register 8
- ***************************************************************************/
-/* SUN_TOP_CTRL :: PIN_MUX_CTRL_8 :: gpio_056 [31:28] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_056_MASK 0xf0000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_056_SHIFT 28
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_056_DEFAULT 0x00000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_056_GPIO_056 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_056_CHIP2POD_MDO5 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_056_RMXP_DATA5 2
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_056_SC1_VPP 3
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_056_EBI_ADDR_23 4
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_056_TP_OUT_19 5
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_056_PM_GPIO_056 6
-
-/* SUN_TOP_CTRL :: PIN_MUX_CTRL_8 :: gpio_055 [27:24] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_055_MASK 0x0f000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_055_SHIFT 24
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_055_DEFAULT 0x00000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_055_GPIO_055 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_055_CHIP2POD_MDO4 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_055_RMXP_DATA4 2
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_055_SC1_AUX2 3
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_055_EBI_ADDR_22 4
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_055_TP_OUT_18 5
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_055_PM_GPIO_055 6
-
-/* SUN_TOP_CTRL :: PIN_MUX_CTRL_8 :: gpio_054 [23:20] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_054_MASK 0x00f00000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_054_SHIFT 20
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_054_DEFAULT 0x00000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_054_GPIO_054 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_054_CHIP2POD_MDO3 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_054_RMXP_DATA3 2
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_054_SC1_AUX1 3
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_054_EBI_ADDR_21 4
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_054_TP_OUT_17 5
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_054_PM_GPIO_054 6
-
-/* SUN_TOP_CTRL :: PIN_MUX_CTRL_8 :: gpio_053 [19:16] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_053_MASK 0x000f0000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_053_SHIFT 16
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_053_DEFAULT 0x00000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_053_GPIO_053 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_053_CHIP2POD_MDO2 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_053_RMXP_DATA2 2
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_053_SC1_VCC 3
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_053_EBI_ADDR_20 4
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_053_TP_OUT_16 5
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_053_PM_GPIO_053 6
-
-/* SUN_TOP_CTRL :: PIN_MUX_CTRL_8 :: gpio_052 [15:12] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_052_MASK 0x0000f000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_052_SHIFT 12
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_052_DEFAULT 0x00000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_052_GPIO_052 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_052_CHIP2POD_MDO1 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_052_RMXP_DATA1 2
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_052_SC1_PRES 3
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_052_EBI_ADDR_19 4
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_052_TP_OUT_15 5
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_052_PM_GPIO_052 6
-
-/* SUN_TOP_CTRL :: PIN_MUX_CTRL_8 :: gpio_051 [11:08] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_051_MASK 0x00000f00
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_051_SHIFT 8
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_051_DEFAULT 0x00000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_051_GPIO_051 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_051_CHIP2POD_MDO0 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_051_RMXP_DATA0 2
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_051_SC1_RST 3
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_051_EBI_ADDR_18 4
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_051_TP_OUT_14 5
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_051_PM_GPIO_051 6
-
-/* SUN_TOP_CTRL :: PIN_MUX_CTRL_8 :: gpio_050 [07:04] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_050_MASK 0x000000f0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_050_SHIFT 4
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_050_DEFAULT 0x00000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_050_GPIO_050 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_050_CHIP2POD_MOSTRT 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_050_RMXP_SYNC 2
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_050_SC1_CLK 3
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_050_EBI_ADDR_17 4
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_050_ALT_TP_OUT_15 5
-
-/* SUN_TOP_CTRL :: PIN_MUX_CTRL_8 :: gpio_049 [03:00] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_049_MASK 0x0000000f
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_049_SHIFT 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_049_DEFAULT 0x00000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_049_GPIO_049 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_049_CHIP2POD_MOVAL 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_049_RMXP_VALID 2
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_049_SC1_IO 3
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_049_EBI_ADDR_16 4
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_049_TP_OUT_12 5
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_049_PM_GPIO_049 6
-
-/***************************************************************************
- *PIN_MUX_CTRL_9 - Pinmux control register 9
- ***************************************************************************/
-/* SUN_TOP_CTRL :: PIN_MUX_CTRL_9 :: gpio_064 [31:28] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_064_MASK 0xf0000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_064_SHIFT 28
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_064_DEFAULT 0x00000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_064_GPIO_064 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_064_SDIO0_CLK 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_064_RMX_PAUSE0 2
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_064_RCPU_TRACE_DATA2 3
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_064_PWM_2 4
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_064_ALT_TP_IN_11 5
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_064_PM_GPIO_064 6
-
-/* SUN_TOP_CTRL :: PIN_MUX_CTRL_9 :: gpio_063 [27:24] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_063_MASK 0x0f000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_063_SHIFT 24
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_063_DEFAULT 0x00000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_063_GPIO_063 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_063_SDIO0_PWR0 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_063_SC1_VPP 2
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_063_RCPU_TRACE_DATA1 3
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_063_PM_GPIO_063 4
-
-/* SUN_TOP_CTRL :: PIN_MUX_CTRL_9 :: gpio_062 [23:20] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_062_MASK 0x00f00000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_062_SHIFT 20
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_062_DEFAULT 0x00000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_062_GPIO_062 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_062_SDIO0_WPROT 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_062_SC1_AUX2 2
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_062_RCPU_TRACE_DATA0 3
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_062_TP_OUT_25 4
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_062_PM_GPIO_062 5
-
-/* SUN_TOP_CTRL :: PIN_MUX_CTRL_9 :: gpio_061 [19:16] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_061_MASK 0x000f0000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_061_SHIFT 16
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_061_DEFAULT 0x00000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_061_GPIO_061 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_061_SDIO0_CMD 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_061_SC1_AUX1 2
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_061_RCPU_TRACE_CLK 3
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_061_TP_OUT_24 4
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_061_PM_GPIO_061 5
-
-/* SUN_TOP_CTRL :: PIN_MUX_CTRL_9 :: gpio_060 [15:12] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_060_MASK 0x0000f000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_060_SHIFT 12
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_060_DEFAULT 0x00000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_060_GPIO_060 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_060_POD2CHIP_ETX 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_060_EBI_ADDR_06 2
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_060_UART_CTS_2 3
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_060_TP_OUT_23 4
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_060_PM_GPIO_060 5
-
-/* SUN_TOP_CTRL :: PIN_MUX_CTRL_9 :: gpio_059 [11:08] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_059_MASK 0x00000f00
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_059_SHIFT 8
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_059_DEFAULT 0x00000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_059_GPIO_059 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_059_CHIP2POD_MOCLK 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_059_RMXP_CLK 2
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_059_I2S_LR1_OUT 3
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_059_EBI_ADDR_12 4
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_059_CHIP2POD_MCLKO 5
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_059_TP_OUT_22 6
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_059_PM_GPIO_059 7
-
-/* SUN_TOP_CTRL :: PIN_MUX_CTRL_9 :: gpio_058 [07:04] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_058_MASK 0x000000f0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_058_SHIFT 4
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_058_DEFAULT 0x00000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_058_GPIO_058 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_058_CHIP2POD_MDO7 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_058_RMXP_DATA7 2
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_058_I2S_DATA1_OUT 3
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_058_EBI_ADDR_25 4
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_058_TP_OUT_21 5
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_058_PM_GPIO_058 6
-
-/* SUN_TOP_CTRL :: PIN_MUX_CTRL_9 :: gpio_057 [03:00] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_057_MASK 0x0000000f
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_057_SHIFT 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_057_DEFAULT 0x00000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_057_GPIO_057 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_057_CHIP2POD_MDO6 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_057_RMXP_DATA6 2
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_057_I2S_CLK1_OUT 3
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_057_EBI_ADDR_24 4
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_057_TP_OUT_20 5
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_057_PM_GPIO_057 6
-
-/***************************************************************************
- *PIN_MUX_CTRL_10 - Pinmux control register 10
- ***************************************************************************/
-/* SUN_TOP_CTRL :: PIN_MUX_CTRL_10 :: gpio_072 [31:28] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_072_MASK 0xf0000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_072_SHIFT 28
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_072_DEFAULT 0x00000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_072_GPIO_072 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_072_SC0_AUX2 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_072_SPI_M_MOSI 2
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_072_PM_GPIO_072 3
-
-/* SUN_TOP_CTRL :: PIN_MUX_CTRL_10 :: gpio_071 [27:24] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_071_MASK 0x0f000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_071_SHIFT 24
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_071_DEFAULT 0x00000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_071_GPIO_071 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_071_SC0_AUX1 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_071_SPI_M_SCK 2
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_071_PM_GPIO_071 3
-
-/* SUN_TOP_CTRL :: PIN_MUX_CTRL_10 :: gpio_070 [23:20] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_070_MASK 0x00f00000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_070_SHIFT 20
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_070_DEFAULT 0x00000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_070_GPIO_070 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_070_SDIO0_LED 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_070_PWM_3 2
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_070_EXT_IRQB_4 3
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_070_TP_OUT_31 4
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_070_PM_GPIO_070 5
-
-/* SUN_TOP_CTRL :: PIN_MUX_CTRL_10 :: gpio_069 [19:16] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_069_MASK 0x000f0000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_069_SHIFT 16
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_069_DEFAULT 0x00000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_069_GPIO_069 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_069_SDIO0_PRES 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_069_UART_CTS_1 2
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_069_EXT_IRQB_3 3
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_069_UART_TXD_0 4
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_069_TP_OUT_30 5
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_069_PM_GPIO_069 6
-
-/* SUN_TOP_CTRL :: PIN_MUX_CTRL_10 :: gpio_068 [15:12] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_068_MASK 0x0000f000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_068_SHIFT 12
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_068_DEFAULT 0x00000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_068_GPIO_068 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_068_SDIO0_DAT3 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_068_UART_RTS_1 2
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_068_EXT_IRQB_2 3
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_068_UART_RXD_0 4
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_068_TP_OUT_29 5
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_068_PM_GPIO_068 6
-
-/* SUN_TOP_CTRL :: PIN_MUX_CTRL_10 :: gpio_067 [11:08] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_067_MASK 0x00000f00
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_067_SHIFT 8
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_067_DEFAULT 0x00000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_067_GPIO_067 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_067_SDIO0_DAT2 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_067_UART_TXD_1 2
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_067_EXT_IRQB_1 3
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_067_TP_OUT_28 4
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_067_PM_GPIO_067 5
-
-/* SUN_TOP_CTRL :: PIN_MUX_CTRL_10 :: gpio_066 [07:04] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_066_MASK 0x000000f0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_066_SHIFT 4
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_066_DEFAULT 0x00000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_066_GPIO_066 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_066_SDIO0_DAT1 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_066_UART_RXD_1 2
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_066_RCPU_TRACE_RXD 3
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_066_EXT_IRQB_0 4
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_066_TP_IN_31 5
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_066_PM_GPIO_066 6
-
-/* SUN_TOP_CTRL :: PIN_MUX_CTRL_10 :: gpio_065 [03:00] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_065_MASK 0x0000000f
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_065_SHIFT 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_065_DEFAULT 0x00000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_065_GPIO_065 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_065_SDIO0_DAT0 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_065_RMX_PAUSE1 2
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_065_RCPU_TRACE_DATA3 3
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_065_IR_IN1 4
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_065_TP_OUT_26 5
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_065_PM_GPIO_065 6
-
-/***************************************************************************
- *PIN_MUX_CTRL_11 - Pinmux control register 11
- ***************************************************************************/
-/* SUN_TOP_CTRL :: PIN_MUX_CTRL_11 :: gpio_080 [31:28] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_080_MASK 0xf0000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_080_SHIFT 28
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_080_DEFAULT 0x00000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_080_GPIO_080 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_080_MII_IRQ 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_080_ALT_TP_IN_19 2
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_080_PM_GPIO_080 3
-
-/* SUN_TOP_CTRL :: PIN_MUX_CTRL_11 :: gpio_079 [27:24] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_079_MASK 0x0f000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_079_SHIFT 24
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_079_DEFAULT 0x00000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_079_GPIO_079 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_079_IR_IN1 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_079_PWM_1 2
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_079_UART_CTS_2 3
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_079_TEST_THP 4
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_079_ALT_TP_IN_18 5
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_079_PM_GPIO_079 6
-
-/* SUN_TOP_CTRL :: PIN_MUX_CTRL_11 :: gpio_078 [23:20] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_078_MASK 0x00f00000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_078_SHIFT 20
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_078_DEFAULT 0x00000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_078_GPIO_078 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_078_SC0_VCC 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_078_AUD_FS_CLK1 2
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_078_PWM_2 3
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_078_ALT_TP_IN_17 4
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_078_PM_GPIO_078 5
-
-/* SUN_TOP_CTRL :: PIN_MUX_CTRL_11 :: gpio_077 [19:16] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_077_MASK 0x000f0000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_077_SHIFT 16
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_077_DEFAULT 0x00000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_077_GPIO_077 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_077_SC0_PRES 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_077_AUD_FS_CLK0 2
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_077_VEC_VSYNC_0 3
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_077_ALT_TP_IN_16 4
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_077_PM_GPIO_077 5
-
-/* SUN_TOP_CTRL :: PIN_MUX_CTRL_11 :: gpio_076 [15:12] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_076_MASK 0x0000f000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_076_SHIFT 12
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_076_DEFAULT 0x00000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_076_GPIO_076 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_076_SC0_RST 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_076_SPI_M_SS2B 2
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_076_ALT_TP_IN_15 3
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_076_PM_GPIO_076 4
-
-/* SUN_TOP_CTRL :: PIN_MUX_CTRL_11 :: gpio_075 [11:08] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_075_MASK 0x00000f00
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_075_SHIFT 8
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_075_DEFAULT 0x00000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_075_GPIO_075 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_075_SC0_CLK 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_075_SPI_M_SS1B 2
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_075_ALT_TP_IN_14 3
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_075_PM_GPIO_075 4
-
-/* SUN_TOP_CTRL :: PIN_MUX_CTRL_11 :: gpio_074 [07:04] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_074_MASK 0x000000f0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_074_SHIFT 4
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_074_DEFAULT 0x00000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_074_GPIO_074 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_074_SC0_IO 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_074_SPI_M_SS0B 2
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_074_ALT_TP_IN_13 3
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_074_PM_GPIO_074 4
-
-/* SUN_TOP_CTRL :: PIN_MUX_CTRL_11 :: gpio_073 [03:00] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_073_MASK 0x0000000f
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_073_SHIFT 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_073_DEFAULT 0x00000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_073_GPIO_073 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_073_SC0_VPP 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_073_SPI_M_MISO 2
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_073_PM_GPIO_073 3
-
-/***************************************************************************
- *PIN_MUX_CTRL_12 - Pinmux control register 12
- ***************************************************************************/
-/* SUN_TOP_CTRL :: PIN_MUX_CTRL_12 :: gpio_088 [31:28] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_088_MASK 0xf0000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_088_SHIFT 28
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_088_DEFAULT 0x00000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_088_GPIO_088 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_088_EBI_ADDR_10 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_088_PWM_1 2
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_088_ALT_TP_IN_26 3
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_088_PM_GPIO_088 4
-
-/* SUN_TOP_CTRL :: PIN_MUX_CTRL_12 :: gpio_087 [27:24] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_087_MASK 0x0f000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_087_SHIFT 24
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_087_DEFAULT 0x00000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_087_GPIO_087 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_087_EBI_ADDR_03 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_087_PWM_0 2
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_087_ALT_TP_IN_25 3
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_087_PM_GPIO_087 4
-
-/* SUN_TOP_CTRL :: PIN_MUX_CTRL_12 :: gpio_086 [23:20] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_086_MASK 0x00f00000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_086_SHIFT 20
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_086_DEFAULT 0x00000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_086_GPIO_086 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_086_EXT_IRQB_5 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_086_SDIO1_VOLT 2
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_086_SC_EXT_CLK 3
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_086_ALT_TP_IN_24 4
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_086_PM_GPIO_086 5
-
-/* SUN_TOP_CTRL :: PIN_MUX_CTRL_12 :: gpio_085 [19:16] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_085_MASK 0x000f0000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_085_SHIFT 16
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_085_DEFAULT 0x00000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_085_GPIO_085 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_085_IR_IN1 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_085_SDIO0_VOLT 2
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_085_PWM_3 3
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_085_ALT_TP_IN_23 4
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_085_PM_GPIO_085 5
-
-/* SUN_TOP_CTRL :: PIN_MUX_CTRL_12 :: gpio_084 [15:12] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_084_MASK 0x0000f000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_084_SHIFT 12
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_084_DEFAULT 0x00000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_084_GPIO_084 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_084_MII_TX_ERR 1
-
-/* SUN_TOP_CTRL :: PIN_MUX_CTRL_12 :: gpio_083 [11:08] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_083_MASK 0x00000f00
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_083_SHIFT 8
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_083_DEFAULT 0x00000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_083_GPIO_083 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_083_MII_RX_ERR 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_083_RMX_SYNC1 2
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_083_UART_RTS_2 3
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_083_I2S_LR0_OUT 4
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_083_ALT_TP_IN_22 5
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_083_PM_GPIO_083 6
-
-/* SUN_TOP_CTRL :: PIN_MUX_CTRL_12 :: gpio_082 [07:04] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_082_MASK 0x000000f0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_082_SHIFT 4
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_082_DEFAULT 0x00000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_082_GPIO_082 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_082_MII_COL 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_082_RMX_DATA1 2
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_082_UART_RXD_2 3
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_082_I2S_DATA0_OUT 4
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_082_ALT_TP_IN_21 5
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_082_PM_GPIO_082 6
-
-/* SUN_TOP_CTRL :: PIN_MUX_CTRL_12 :: gpio_081 [03:00] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_081_MASK 0x0000000f
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_081_SHIFT 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_081_DEFAULT 0x00000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_081_GPIO_081 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_081_MII_CRS 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_081_RMX_CLK1 2
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_081_UART_TXD_2 3
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_081_I2S_CLK0_OUT 4
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_081_PWM_3 5
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_081_ALT_TP_IN_20 6
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_081_PM_GPIO_081 7
-
-/***************************************************************************
- *PIN_MUX_CTRL_13 - Pinmux control register 13
- ***************************************************************************/
-/* SUN_TOP_CTRL :: PIN_MUX_CTRL_13 :: gpio_096 [31:28] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_096_MASK 0xf0000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_096_SHIFT 28
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_096_DEFAULT 0x00000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_096_GPIO_096 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_096_SPI_M_MISO 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_096_PM_GPIO_096 2
-
-/* SUN_TOP_CTRL :: PIN_MUX_CTRL_13 :: gpio_095 [27:24] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_095_MASK 0x0f000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_095_SHIFT 24
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_095_DEFAULT 0x00000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_095_GPIO_095 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_095_SPI_M_MOSI 1
-
-/* SUN_TOP_CTRL :: PIN_MUX_CTRL_13 :: gpio_094 [23:20] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_094_MASK 0x00f00000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_094_SHIFT 20
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_094_DEFAULT 0x00000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_094_GPIO_094 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_094_SPI_M_SCK 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_094_PM_GPIO_094 2
-
-/* SUN_TOP_CTRL :: PIN_MUX_CTRL_13 :: gpio_093 [19:16] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_093_MASK 0x000f0000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_093_SHIFT 16
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_093_DEFAULT 0x00000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_093_GPIO_093 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_093_SW_LED_CLK 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_093_TP_IN_11 2
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_093_PM_GPIO_093 3
-
-/* SUN_TOP_CTRL :: PIN_MUX_CTRL_13 :: gpio_092 [15:12] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_092_MASK 0x0000f000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_092_SHIFT 12
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_092_DEFAULT 0x00000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_092_GPIO_092 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_092_SW_LED_DATA 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_092_ALT_TP_IN_30 2
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_092_PM_GPIO_092 3
-
-/* SUN_TOP_CTRL :: PIN_MUX_CTRL_13 :: gpio_091 [11:08] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_091_MASK 0x00000f00
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_091_SHIFT 8
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_091_DEFAULT 0x00000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_091_GPIO_091 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_091_EBI_RWB 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_091_ALT_TP_IN_29 2
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_091_PM_GPIO_091 3
-
-/* SUN_TOP_CTRL :: PIN_MUX_CTRL_13 :: gpio_090 [07:04] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_090_MASK 0x000000f0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_090_SHIFT 4
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_090_DEFAULT 0x00000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_090_GPIO_090 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_090_EBI_CS3B 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_090_PWM_3 2
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_090_ALT_TP_IN_28 3
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_090_PM_GPIO_090 4
-
-/* SUN_TOP_CTRL :: PIN_MUX_CTRL_13 :: gpio_089 [03:00] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_089_MASK 0x0000000f
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_089_SHIFT 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_089_DEFAULT 0x00000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_089_GPIO_089 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_089_EBI_ADDR_11 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_089_PWM_2 2
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_089_ALT_TP_IN_27 3
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_089_PM_GPIO_089 4
-
-/***************************************************************************
- *PIN_MUX_CTRL_14 - Pinmux control register 14
- ***************************************************************************/
-/* SUN_TOP_CTRL :: PIN_MUX_CTRL_14 :: sgpio_01 [31:28] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_sgpio_01_MASK 0xf0000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_sgpio_01_SHIFT 28
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_sgpio_01_DEFAULT 0x00000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_sgpio_01_SGPIO_01 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_sgpio_01_BSC_M4_SDA 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_sgpio_01_MOCA_BSC_SDA 2
-
-/* SUN_TOP_CTRL :: PIN_MUX_CTRL_14 :: sgpio_00 [27:24] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_sgpio_00_MASK 0x0f000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_sgpio_00_SHIFT 24
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_sgpio_00_DEFAULT 0x00000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_sgpio_00_SGPIO_00 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_sgpio_00_BSC_M4_SCL 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_sgpio_00_MOCA_BSC_SCL 2
-
-/* SUN_TOP_CTRL :: PIN_MUX_CTRL_14 :: gpio_102 [23:20] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_102_MASK 0x00f00000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_102_SHIFT 20
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_102_DEFAULT 0x00000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_102_GPIO_102 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_102_SDIO1_CLK_IN 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_102_PM_GPIO_102 2
-
-/* SUN_TOP_CTRL :: PIN_MUX_CTRL_14 :: gpio_101 [19:16] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_101_MASK 0x000f0000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_101_SHIFT 16
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_101_DEFAULT 0x00000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_101_GPIO_101 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_101_SDIO0_CLK_IN 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_101_PM_GPIO_101 2
-
-/* SUN_TOP_CTRL :: PIN_MUX_CTRL_14 :: gpio_100 [15:12] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_100_MASK 0x0000f000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_100_SHIFT 12
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_100_DEFAULT 0x00000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_100_GPIO_100 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_100_PWM_0 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_100_TSIO_VCTRL 2
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_100_TTX0_DATA 3
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_100_PM_GPIO_100 4
-
-/* SUN_TOP_CTRL :: PIN_MUX_CTRL_14 :: gpio_099 [11:08] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_099_MASK 0x00000f00
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_099_SHIFT 8
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_099_DEFAULT 0x00000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_099_GPIO_099 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_099_SPI_M_SS2B 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_099_IR_INT 2
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_099_TTX0_REQ 3
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_099_PWM_2 4
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_099_PM_GPIO_099 5
-
-/* SUN_TOP_CTRL :: PIN_MUX_CTRL_14 :: gpio_098 [07:04] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_098_MASK 0x000000f0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_098_SHIFT 4
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_098_DEFAULT 0x00000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_098_GPIO_098 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_098_SPI_M_SS1B 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_098_IR_IN1 2
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_098_PM_GPIO_098 3
-
-/* SUN_TOP_CTRL :: PIN_MUX_CTRL_14 :: gpio_097 [03:00] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_097_MASK 0x0000000f
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_097_SHIFT 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_097_DEFAULT 0x00000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_097_GPIO_097 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_097_SPI_M_SS0B 1
-
-/***************************************************************************
- *PIN_MUX_CTRL_15 - Pinmux control register 15
- ***************************************************************************/
-/* SUN_TOP_CTRL :: PIN_MUX_CTRL_15 :: reserved0 [31:16] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_reserved0_MASK 0xffff0000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_reserved0_SHIFT 16
-
-/* SUN_TOP_CTRL :: PIN_MUX_CTRL_15 :: bsc_s_sda [15:12] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_bsc_s_sda_MASK 0x0000f000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_bsc_s_sda_SHIFT 12
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_bsc_s_sda_DEFAULT 0x00000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_bsc_s_sda_BSC_S_SDA 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_bsc_s_sda_SW_SPI_S_MOSI 1
-
-/* SUN_TOP_CTRL :: PIN_MUX_CTRL_15 :: bsc_s_scl [11:08] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_bsc_s_scl_MASK 0x00000f00
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_bsc_s_scl_SHIFT 8
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_bsc_s_scl_DEFAULT 0x00000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_bsc_s_scl_BSC_S_SCL 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_bsc_s_scl_SW_SPI_S_SCK 1
-
-/* SUN_TOP_CTRL :: PIN_MUX_CTRL_15 :: sgpio_03 [07:04] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_sgpio_03_MASK 0x000000f0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_sgpio_03_SHIFT 4
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_sgpio_03_DEFAULT 0x00000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_sgpio_03_SGPIO_03 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_sgpio_03_BSC_M3_SDA 1
-
-/* SUN_TOP_CTRL :: PIN_MUX_CTRL_15 :: sgpio_02 [03:00] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_sgpio_02_MASK 0x0000000f
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_sgpio_02_SHIFT 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_sgpio_02_DEFAULT 0x00000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_sgpio_02_SGPIO_02 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_sgpio_02_BSC_M3_SCL 1
-
-/***************************************************************************
- *PIN_MUX_PAD_CTRL_0 - Pad pull-up/pull-down control register 0
- ***************************************************************************/
-/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_0 :: spare_pad_ctrl_0 [31:30] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_spare_pad_ctrl_0_MASK 0xc0000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_spare_pad_ctrl_0_SHIFT 30
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_spare_pad_ctrl_0_DEFAULT 0x00000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_spare_pad_ctrl_0_PULL_NONE 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_spare_pad_ctrl_0_PULL_DOWN 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_spare_pad_ctrl_0_PULL_UP 2
-
-/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_0 :: ebi_we0b_pad_ctrl [29:28] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_ebi_we0b_pad_ctrl_MASK 0x30000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_ebi_we0b_pad_ctrl_SHIFT 28
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_ebi_we0b_pad_ctrl_DEFAULT 0x00000002
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_ebi_we0b_pad_ctrl_PULL_NONE 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_ebi_we0b_pad_ctrl_PULL_DOWN 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_ebi_we0b_pad_ctrl_PULL_UP 2
-
-/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_0 :: ebi_cs2b_pad_ctrl [27:26] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_ebi_cs2b_pad_ctrl_MASK 0x0c000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_ebi_cs2b_pad_ctrl_SHIFT 26
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_ebi_cs2b_pad_ctrl_DEFAULT 0x00000002
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_ebi_cs2b_pad_ctrl_PULL_NONE 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_ebi_cs2b_pad_ctrl_PULL_DOWN 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_ebi_cs2b_pad_ctrl_PULL_UP 2
-
-/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_0 :: ebi_cs1b_pad_ctrl [25:24] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_ebi_cs1b_pad_ctrl_MASK 0x03000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_ebi_cs1b_pad_ctrl_SHIFT 24
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_ebi_cs1b_pad_ctrl_DEFAULT 0x00000002
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_ebi_cs1b_pad_ctrl_PULL_NONE 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_ebi_cs1b_pad_ctrl_PULL_DOWN 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_ebi_cs1b_pad_ctrl_PULL_UP 2
-
-/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_0 :: ebi_cs0b_pad_ctrl [23:22] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_ebi_cs0b_pad_ctrl_MASK 0x00c00000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_ebi_cs0b_pad_ctrl_SHIFT 22
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_ebi_cs0b_pad_ctrl_DEFAULT 0x00000002
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_ebi_cs0b_pad_ctrl_PULL_NONE 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_ebi_cs0b_pad_ctrl_PULL_DOWN 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_ebi_cs0b_pad_ctrl_PULL_UP 2
-
-/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_0 :: ebi_data_07_pad_ctrl [21:20] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_ebi_data_07_pad_ctrl_MASK 0x00300000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_ebi_data_07_pad_ctrl_SHIFT 20
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_ebi_data_07_pad_ctrl_DEFAULT 0x00000002
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_ebi_data_07_pad_ctrl_PULL_NONE 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_ebi_data_07_pad_ctrl_PULL_DOWN 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_ebi_data_07_pad_ctrl_PULL_UP 2
-
-/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_0 :: ebi_data_06_pad_ctrl [19:18] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_ebi_data_06_pad_ctrl_MASK 0x000c0000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_ebi_data_06_pad_ctrl_SHIFT 18
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_ebi_data_06_pad_ctrl_DEFAULT 0x00000002
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_ebi_data_06_pad_ctrl_PULL_NONE 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_ebi_data_06_pad_ctrl_PULL_DOWN 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_ebi_data_06_pad_ctrl_PULL_UP 2
-
-/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_0 :: ebi_data_05_pad_ctrl [17:16] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_ebi_data_05_pad_ctrl_MASK 0x00030000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_ebi_data_05_pad_ctrl_SHIFT 16
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_ebi_data_05_pad_ctrl_DEFAULT 0x00000002
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_ebi_data_05_pad_ctrl_PULL_NONE 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_ebi_data_05_pad_ctrl_PULL_DOWN 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_ebi_data_05_pad_ctrl_PULL_UP 2
-
-/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_0 :: ebi_data_04_pad_ctrl [15:14] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_ebi_data_04_pad_ctrl_MASK 0x0000c000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_ebi_data_04_pad_ctrl_SHIFT 14
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_ebi_data_04_pad_ctrl_DEFAULT 0x00000002
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_ebi_data_04_pad_ctrl_PULL_NONE 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_ebi_data_04_pad_ctrl_PULL_DOWN 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_ebi_data_04_pad_ctrl_PULL_UP 2
-
-/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_0 :: ebi_data_03_pad_ctrl [13:12] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_ebi_data_03_pad_ctrl_MASK 0x00003000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_ebi_data_03_pad_ctrl_SHIFT 12
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_ebi_data_03_pad_ctrl_DEFAULT 0x00000002
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_ebi_data_03_pad_ctrl_PULL_NONE 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_ebi_data_03_pad_ctrl_PULL_DOWN 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_ebi_data_03_pad_ctrl_PULL_UP 2
-
-/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_0 :: ebi_data_02_pad_ctrl [11:10] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_ebi_data_02_pad_ctrl_MASK 0x00000c00
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_ebi_data_02_pad_ctrl_SHIFT 10
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_ebi_data_02_pad_ctrl_DEFAULT 0x00000002
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_ebi_data_02_pad_ctrl_PULL_NONE 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_ebi_data_02_pad_ctrl_PULL_DOWN 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_ebi_data_02_pad_ctrl_PULL_UP 2
-
-/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_0 :: ebi_data_01_pad_ctrl [09:08] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_ebi_data_01_pad_ctrl_MASK 0x00000300
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_ebi_data_01_pad_ctrl_SHIFT 8
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_ebi_data_01_pad_ctrl_DEFAULT 0x00000002
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_ebi_data_01_pad_ctrl_PULL_NONE 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_ebi_data_01_pad_ctrl_PULL_DOWN 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_ebi_data_01_pad_ctrl_PULL_UP 2
-
-/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_0 :: ebi_data_00_pad_ctrl [07:06] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_ebi_data_00_pad_ctrl_MASK 0x000000c0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_ebi_data_00_pad_ctrl_SHIFT 6
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_ebi_data_00_pad_ctrl_DEFAULT 0x00000002
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_ebi_data_00_pad_ctrl_PULL_NONE 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_ebi_data_00_pad_ctrl_PULL_DOWN 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_ebi_data_00_pad_ctrl_PULL_UP 2
-
-/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_0 :: reserved0 [05:00] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_reserved0_MASK 0x0000003f
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_reserved0_SHIFT 0
-
-/***************************************************************************
- *PIN_MUX_PAD_CTRL_1 - Pad pull-up/pull-down control register 1
- ***************************************************************************/
-/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_1 :: spare_pad_ctrl_1 [31:30] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_spare_pad_ctrl_1_MASK 0xc0000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_spare_pad_ctrl_1_SHIFT 30
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_spare_pad_ctrl_1_DEFAULT 0x00000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_spare_pad_ctrl_1_PULL_NONE 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_spare_pad_ctrl_1_PULL_DOWN 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_spare_pad_ctrl_1_PULL_UP 2
-
-/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_1 :: emmc1_clk_pad_ctrl [29:28] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_emmc1_clk_pad_ctrl_MASK 0x30000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_emmc1_clk_pad_ctrl_SHIFT 28
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_emmc1_clk_pad_ctrl_DEFAULT 0x00000002
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_emmc1_clk_pad_ctrl_PULL_NONE 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_emmc1_clk_pad_ctrl_PULL_DOWN 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_emmc1_clk_pad_ctrl_PULL_UP 2
-
-/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_1 :: emmc1_cmd_pad_ctrl [27:26] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_emmc1_cmd_pad_ctrl_MASK 0x0c000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_emmc1_cmd_pad_ctrl_SHIFT 26
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_emmc1_cmd_pad_ctrl_DEFAULT 0x00000002
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_emmc1_cmd_pad_ctrl_PULL_NONE 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_emmc1_cmd_pad_ctrl_PULL_DOWN 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_emmc1_cmd_pad_ctrl_PULL_UP 2
-
-/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_1 :: sf_wpb_pad_ctrl [25:24] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_sf_wpb_pad_ctrl_MASK 0x03000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_sf_wpb_pad_ctrl_SHIFT 24
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_sf_wpb_pad_ctrl_DEFAULT 0x00000002
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_sf_wpb_pad_ctrl_PULL_NONE 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_sf_wpb_pad_ctrl_PULL_DOWN 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_sf_wpb_pad_ctrl_PULL_UP 2
-
-/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_1 :: sf_holdb_pad_ctrl [23:22] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_sf_holdb_pad_ctrl_MASK 0x00c00000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_sf_holdb_pad_ctrl_SHIFT 22
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_sf_holdb_pad_ctrl_DEFAULT 0x00000002
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_sf_holdb_pad_ctrl_PULL_NONE 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_sf_holdb_pad_ctrl_PULL_DOWN 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_sf_holdb_pad_ctrl_PULL_UP 2
-
-/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_1 :: sf_mosi_pad_ctrl [21:20] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_sf_mosi_pad_ctrl_MASK 0x00300000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_sf_mosi_pad_ctrl_SHIFT 20
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_sf_mosi_pad_ctrl_DEFAULT 0x00000002
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_sf_mosi_pad_ctrl_PULL_NONE 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_sf_mosi_pad_ctrl_PULL_DOWN 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_sf_mosi_pad_ctrl_PULL_UP 2
-
-/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_1 :: sf_miso_pad_ctrl [19:18] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_sf_miso_pad_ctrl_MASK 0x000c0000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_sf_miso_pad_ctrl_SHIFT 18
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_sf_miso_pad_ctrl_DEFAULT 0x00000002
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_sf_miso_pad_ctrl_PULL_NONE 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_sf_miso_pad_ctrl_PULL_DOWN 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_sf_miso_pad_ctrl_PULL_UP 2
-
-/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_1 :: sf_sck_pad_ctrl [17:16] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_sf_sck_pad_ctrl_MASK 0x00030000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_sf_sck_pad_ctrl_SHIFT 16
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_sf_sck_pad_ctrl_DEFAULT 0x00000002
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_sf_sck_pad_ctrl_PULL_NONE 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_sf_sck_pad_ctrl_PULL_DOWN 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_sf_sck_pad_ctrl_PULL_UP 2
-
-/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_1 :: ebi_nand_dqs_pad_ctrl [15:14] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_ebi_nand_dqs_pad_ctrl_MASK 0x0000c000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_ebi_nand_dqs_pad_ctrl_SHIFT 14
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_ebi_nand_dqs_pad_ctrl_DEFAULT 0x00000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_ebi_nand_dqs_pad_ctrl_PULL_NONE 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_ebi_nand_dqs_pad_ctrl_PULL_DOWN 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_ebi_nand_dqs_pad_ctrl_PULL_UP 2
-
-/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_1 :: ebi_waitb_pad_ctrl [13:12] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_ebi_waitb_pad_ctrl_MASK 0x00003000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_ebi_waitb_pad_ctrl_SHIFT 12
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_ebi_waitb_pad_ctrl_DEFAULT 0x00000002
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_ebi_waitb_pad_ctrl_PULL_NONE 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_ebi_waitb_pad_ctrl_PULL_DOWN 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_ebi_waitb_pad_ctrl_PULL_UP 2
-
-/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_1 :: ebi_wpb_pad_ctrl [11:10] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_ebi_wpb_pad_ctrl_MASK 0x00000c00
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_ebi_wpb_pad_ctrl_SHIFT 10
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_ebi_wpb_pad_ctrl_DEFAULT 0x00000001
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_ebi_wpb_pad_ctrl_PULL_NONE 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_ebi_wpb_pad_ctrl_PULL_DOWN 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_ebi_wpb_pad_ctrl_PULL_UP 2
-
-/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_1 :: ebi_nand_rbb_pad_ctrl [09:08] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_ebi_nand_rbb_pad_ctrl_MASK 0x00000300
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_ebi_nand_rbb_pad_ctrl_SHIFT 8
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_ebi_nand_rbb_pad_ctrl_DEFAULT 0x00000002
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_ebi_nand_rbb_pad_ctrl_PULL_NONE 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_ebi_nand_rbb_pad_ctrl_PULL_DOWN 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_ebi_nand_rbb_pad_ctrl_PULL_UP 2
-
-/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_1 :: ebi_dsb_pad_ctrl [07:06] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_ebi_dsb_pad_ctrl_MASK 0x000000c0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_ebi_dsb_pad_ctrl_SHIFT 6
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_ebi_dsb_pad_ctrl_DEFAULT 0x00000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_ebi_dsb_pad_ctrl_PULL_NONE 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_ebi_dsb_pad_ctrl_PULL_DOWN 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_ebi_dsb_pad_ctrl_PULL_UP 2
-
-/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_1 :: ebi_tsb_pad_ctrl [05:04] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_ebi_tsb_pad_ctrl_MASK 0x00000030
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_ebi_tsb_pad_ctrl_SHIFT 4
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_ebi_tsb_pad_ctrl_DEFAULT 0x00000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_ebi_tsb_pad_ctrl_PULL_NONE 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_ebi_tsb_pad_ctrl_PULL_DOWN 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_ebi_tsb_pad_ctrl_PULL_UP 2
-
-/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_1 :: ebi_rdb_pad_ctrl [03:02] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_ebi_rdb_pad_ctrl_MASK 0x0000000c
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_ebi_rdb_pad_ctrl_SHIFT 2
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_ebi_rdb_pad_ctrl_DEFAULT 0x00000002
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_ebi_rdb_pad_ctrl_PULL_NONE 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_ebi_rdb_pad_ctrl_PULL_DOWN 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_ebi_rdb_pad_ctrl_PULL_UP 2
-
-/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_1 :: ebi_we1b_pad_ctrl [01:00] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_ebi_we1b_pad_ctrl_MASK 0x00000003
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_ebi_we1b_pad_ctrl_SHIFT 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_ebi_we1b_pad_ctrl_DEFAULT 0x00000002
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_ebi_we1b_pad_ctrl_PULL_NONE 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_ebi_we1b_pad_ctrl_PULL_DOWN 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_ebi_we1b_pad_ctrl_PULL_UP 2
-
-/***************************************************************************
- *PIN_MUX_PAD_CTRL_2 - Pad pull-up/pull-down control register 2
- ***************************************************************************/
-/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_2 :: spare_pad_ctrl_2 [31:30] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_spare_pad_ctrl_2_MASK 0xc0000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_spare_pad_ctrl_2_SHIFT 30
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_spare_pad_ctrl_2_DEFAULT 0x00000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_spare_pad_ctrl_2_PULL_NONE 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_spare_pad_ctrl_2_PULL_DOWN 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_spare_pad_ctrl_2_PULL_UP 2
-
-/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_2 :: gpio_005_pad_ctrl [29:28] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_005_pad_ctrl_MASK 0x30000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_005_pad_ctrl_SHIFT 28
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_005_pad_ctrl_DEFAULT 0x00000001
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_005_pad_ctrl_PULL_NONE 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_005_pad_ctrl_PULL_DOWN 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_005_pad_ctrl_PULL_UP 2
-
-/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_2 :: gpio_004_pad_ctrl [27:26] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_004_pad_ctrl_MASK 0x0c000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_004_pad_ctrl_SHIFT 26
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_004_pad_ctrl_DEFAULT 0x00000001
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_004_pad_ctrl_PULL_NONE 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_004_pad_ctrl_PULL_DOWN 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_004_pad_ctrl_PULL_UP 2
-
-/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_2 :: gpio_003_pad_ctrl [25:24] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_003_pad_ctrl_MASK 0x03000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_003_pad_ctrl_SHIFT 24
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_003_pad_ctrl_DEFAULT 0x00000001
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_003_pad_ctrl_PULL_NONE 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_003_pad_ctrl_PULL_DOWN 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_003_pad_ctrl_PULL_UP 2
-
-/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_2 :: gpio_002_pad_ctrl [23:22] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_002_pad_ctrl_MASK 0x00c00000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_002_pad_ctrl_SHIFT 22
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_002_pad_ctrl_DEFAULT 0x00000001
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_002_pad_ctrl_PULL_NONE 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_002_pad_ctrl_PULL_DOWN 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_002_pad_ctrl_PULL_UP 2
-
-/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_2 :: gpio_001_pad_ctrl [21:20] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_001_pad_ctrl_MASK 0x00300000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_001_pad_ctrl_SHIFT 20
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_001_pad_ctrl_DEFAULT 0x00000001
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_001_pad_ctrl_PULL_NONE 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_001_pad_ctrl_PULL_DOWN 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_001_pad_ctrl_PULL_UP 2
-
-/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_2 :: gpio_000_pad_ctrl [19:18] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_000_pad_ctrl_MASK 0x000c0000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_000_pad_ctrl_SHIFT 18
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_000_pad_ctrl_DEFAULT 0x00000001
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_000_pad_ctrl_PULL_NONE 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_000_pad_ctrl_PULL_DOWN 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_000_pad_ctrl_PULL_UP 2
-
-/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_2 :: reserved0 [17:08] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_reserved0_MASK 0x0003ff00
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_reserved0_SHIFT 8
-
-/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_2 :: pcie1_clkreqb_pad_ctrl [07:06] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_pcie1_clkreqb_pad_ctrl_MASK 0x000000c0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_pcie1_clkreqb_pad_ctrl_SHIFT 6
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_pcie1_clkreqb_pad_ctrl_DEFAULT 0x00000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_pcie1_clkreqb_pad_ctrl_PULL_NONE 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_pcie1_clkreqb_pad_ctrl_PULL_DOWN 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_pcie1_clkreqb_pad_ctrl_PULL_UP 2
-
-/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_2 :: pcie1_rstb_pad_ctrl [05:04] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_pcie1_rstb_pad_ctrl_MASK 0x00000030
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_pcie1_rstb_pad_ctrl_SHIFT 4
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_pcie1_rstb_pad_ctrl_DEFAULT 0x00000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_pcie1_rstb_pad_ctrl_PULL_NONE 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_pcie1_rstb_pad_ctrl_PULL_DOWN 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_pcie1_rstb_pad_ctrl_PULL_UP 2
-
-/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_2 :: pcie0_clkreqb_pad_ctrl [03:02] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_pcie0_clkreqb_pad_ctrl_MASK 0x0000000c
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_pcie0_clkreqb_pad_ctrl_SHIFT 2
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_pcie0_clkreqb_pad_ctrl_DEFAULT 0x00000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_pcie0_clkreqb_pad_ctrl_PULL_NONE 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_pcie0_clkreqb_pad_ctrl_PULL_DOWN 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_pcie0_clkreqb_pad_ctrl_PULL_UP 2
-
-/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_2 :: pcie0_rstb_pad_ctrl [01:00] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_pcie0_rstb_pad_ctrl_MASK 0x00000003
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_pcie0_rstb_pad_ctrl_SHIFT 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_pcie0_rstb_pad_ctrl_DEFAULT 0x00000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_pcie0_rstb_pad_ctrl_PULL_NONE 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_pcie0_rstb_pad_ctrl_PULL_DOWN 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_pcie0_rstb_pad_ctrl_PULL_UP 2
-
-/***************************************************************************
- *PIN_MUX_PAD_CTRL_3 - Pad pull-up/pull-down control register 3
- ***************************************************************************/
-/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_3 :: spare_pad_ctrl_3 [31:30] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_spare_pad_ctrl_3_MASK 0xc0000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_spare_pad_ctrl_3_SHIFT 30
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_spare_pad_ctrl_3_DEFAULT 0x00000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_spare_pad_ctrl_3_PULL_NONE 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_spare_pad_ctrl_3_PULL_DOWN 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_spare_pad_ctrl_3_PULL_UP 2
-
-/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_3 :: gpio_020_pad_ctrl [29:28] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_020_pad_ctrl_MASK 0x30000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_020_pad_ctrl_SHIFT 28
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_020_pad_ctrl_DEFAULT 0x00000001
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_020_pad_ctrl_PULL_NONE 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_020_pad_ctrl_PULL_DOWN 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_020_pad_ctrl_PULL_UP 2
-
-/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_3 :: gpio_019_pad_ctrl [27:26] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_019_pad_ctrl_MASK 0x0c000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_019_pad_ctrl_SHIFT 26
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_019_pad_ctrl_DEFAULT 0x00000001
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_019_pad_ctrl_PULL_NONE 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_019_pad_ctrl_PULL_DOWN 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_019_pad_ctrl_PULL_UP 2
-
-/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_3 :: gpio_018_pad_ctrl [25:24] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_018_pad_ctrl_MASK 0x03000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_018_pad_ctrl_SHIFT 24
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_018_pad_ctrl_DEFAULT 0x00000001
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_018_pad_ctrl_PULL_NONE 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_018_pad_ctrl_PULL_DOWN 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_018_pad_ctrl_PULL_UP 2
-
-/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_3 :: gpio_017_pad_ctrl [23:22] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_017_pad_ctrl_MASK 0x00c00000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_017_pad_ctrl_SHIFT 22
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_017_pad_ctrl_DEFAULT 0x00000001
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_017_pad_ctrl_PULL_NONE 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_017_pad_ctrl_PULL_DOWN 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_017_pad_ctrl_PULL_UP 2
-
-/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_3 :: gpio_016_pad_ctrl [21:20] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_016_pad_ctrl_MASK 0x00300000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_016_pad_ctrl_SHIFT 20
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_016_pad_ctrl_DEFAULT 0x00000001
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_016_pad_ctrl_PULL_NONE 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_016_pad_ctrl_PULL_DOWN 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_016_pad_ctrl_PULL_UP 2
-
-/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_3 :: reserved0 [19:14] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_reserved0_MASK 0x000fc000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_reserved0_SHIFT 14
-
-/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_3 :: gpio_012_pad_ctrl [13:12] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_012_pad_ctrl_MASK 0x00003000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_012_pad_ctrl_SHIFT 12
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_012_pad_ctrl_DEFAULT 0x00000002
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_012_pad_ctrl_PULL_NONE 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_012_pad_ctrl_PULL_DOWN 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_012_pad_ctrl_PULL_UP 2
-
-/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_3 :: reserved1 [11:10] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_reserved1_MASK 0x00000c00
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_reserved1_SHIFT 10
-
-/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_3 :: gpio_010_pad_ctrl [09:08] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_010_pad_ctrl_MASK 0x00000300
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_010_pad_ctrl_SHIFT 8
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_010_pad_ctrl_DEFAULT 0x00000001
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_010_pad_ctrl_PULL_NONE 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_010_pad_ctrl_PULL_DOWN 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_010_pad_ctrl_PULL_UP 2
-
-/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_3 :: gpio_009_pad_ctrl [07:06] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_009_pad_ctrl_MASK 0x000000c0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_009_pad_ctrl_SHIFT 6
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_009_pad_ctrl_DEFAULT 0x00000001
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_009_pad_ctrl_PULL_NONE 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_009_pad_ctrl_PULL_DOWN 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_009_pad_ctrl_PULL_UP 2
-
-/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_3 :: gpio_008_pad_ctrl [05:04] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_008_pad_ctrl_MASK 0x00000030
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_008_pad_ctrl_SHIFT 4
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_008_pad_ctrl_DEFAULT 0x00000001
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_008_pad_ctrl_PULL_NONE 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_008_pad_ctrl_PULL_DOWN 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_008_pad_ctrl_PULL_UP 2
-
-/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_3 :: gpio_007_pad_ctrl [03:02] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_007_pad_ctrl_MASK 0x0000000c
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_007_pad_ctrl_SHIFT 2
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_007_pad_ctrl_DEFAULT 0x00000001
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_007_pad_ctrl_PULL_NONE 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_007_pad_ctrl_PULL_DOWN 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_007_pad_ctrl_PULL_UP 2
-
-/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_3 :: gpio_006_pad_ctrl [01:00] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_006_pad_ctrl_MASK 0x00000003
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_006_pad_ctrl_SHIFT 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_006_pad_ctrl_DEFAULT 0x00000001
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_006_pad_ctrl_PULL_NONE 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_006_pad_ctrl_PULL_DOWN 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_006_pad_ctrl_PULL_UP 2
-
-/***************************************************************************
- *PIN_MUX_PAD_CTRL_4 - Pad pull-up/pull-down control register 4
- ***************************************************************************/
-/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_4 :: spare_pad_ctrl_4 [31:30] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_spare_pad_ctrl_4_MASK 0xc0000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_spare_pad_ctrl_4_SHIFT 30
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_spare_pad_ctrl_4_DEFAULT 0x00000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_spare_pad_ctrl_4_PULL_NONE 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_spare_pad_ctrl_4_PULL_DOWN 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_spare_pad_ctrl_4_PULL_UP 2
-
-/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_4 :: gpio_035_pad_ctrl [29:28] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_035_pad_ctrl_MASK 0x30000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_035_pad_ctrl_SHIFT 28
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_035_pad_ctrl_DEFAULT 0x00000001
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_035_pad_ctrl_PULL_NONE 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_035_pad_ctrl_PULL_DOWN 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_035_pad_ctrl_PULL_UP 2
-
-/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_4 :: gpio_034_pad_ctrl [27:26] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_034_pad_ctrl_MASK 0x0c000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_034_pad_ctrl_SHIFT 26
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_034_pad_ctrl_DEFAULT 0x00000001
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_034_pad_ctrl_PULL_NONE 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_034_pad_ctrl_PULL_DOWN 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_034_pad_ctrl_PULL_UP 2
-
-/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_4 :: reserved0 [25:24] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_reserved0_MASK 0x03000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_reserved0_SHIFT 24
-
-/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_4 :: gpio_032_pad_ctrl [23:22] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_032_pad_ctrl_MASK 0x00c00000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_032_pad_ctrl_SHIFT 22
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_032_pad_ctrl_DEFAULT 0x00000001
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_032_pad_ctrl_PULL_NONE 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_032_pad_ctrl_PULL_DOWN 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_032_pad_ctrl_PULL_UP 2
-
-/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_4 :: gpio_031_pad_ctrl [21:20] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_031_pad_ctrl_MASK 0x00300000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_031_pad_ctrl_SHIFT 20
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_031_pad_ctrl_DEFAULT 0x00000001
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_031_pad_ctrl_PULL_NONE 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_031_pad_ctrl_PULL_DOWN 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_031_pad_ctrl_PULL_UP 2
-
-/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_4 :: gpio_030_pad_ctrl [19:18] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_030_pad_ctrl_MASK 0x000c0000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_030_pad_ctrl_SHIFT 18
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_030_pad_ctrl_DEFAULT 0x00000002
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_030_pad_ctrl_PULL_NONE 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_030_pad_ctrl_PULL_DOWN 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_030_pad_ctrl_PULL_UP 2
-
-/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_4 :: gpio_029_pad_ctrl [17:16] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_029_pad_ctrl_MASK 0x00030000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_029_pad_ctrl_SHIFT 16
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_029_pad_ctrl_DEFAULT 0x00000001
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_029_pad_ctrl_PULL_NONE 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_029_pad_ctrl_PULL_DOWN 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_029_pad_ctrl_PULL_UP 2
-
-/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_4 :: gpio_028_pad_ctrl [15:14] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_028_pad_ctrl_MASK 0x0000c000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_028_pad_ctrl_SHIFT 14
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_028_pad_ctrl_DEFAULT 0x00000001
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_028_pad_ctrl_PULL_NONE 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_028_pad_ctrl_PULL_DOWN 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_028_pad_ctrl_PULL_UP 2
-
-/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_4 :: gpio_027_pad_ctrl [13:12] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_027_pad_ctrl_MASK 0x00003000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_027_pad_ctrl_SHIFT 12
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_027_pad_ctrl_DEFAULT 0x00000001
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_027_pad_ctrl_PULL_NONE 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_027_pad_ctrl_PULL_DOWN 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_027_pad_ctrl_PULL_UP 2
-
-/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_4 :: gpio_026_pad_ctrl [11:10] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_026_pad_ctrl_MASK 0x00000c00
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_026_pad_ctrl_SHIFT 10
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_026_pad_ctrl_DEFAULT 0x00000001
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_026_pad_ctrl_PULL_NONE 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_026_pad_ctrl_PULL_DOWN 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_026_pad_ctrl_PULL_UP 2
-
-/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_4 :: gpio_025_pad_ctrl [09:08] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_025_pad_ctrl_MASK 0x00000300
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_025_pad_ctrl_SHIFT 8
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_025_pad_ctrl_DEFAULT 0x00000001
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_025_pad_ctrl_PULL_NONE 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_025_pad_ctrl_PULL_DOWN 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_025_pad_ctrl_PULL_UP 2
-
-/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_4 :: gpio_024_pad_ctrl [07:06] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_024_pad_ctrl_MASK 0x000000c0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_024_pad_ctrl_SHIFT 6
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_024_pad_ctrl_DEFAULT 0x00000001
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_024_pad_ctrl_PULL_NONE 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_024_pad_ctrl_PULL_DOWN 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_024_pad_ctrl_PULL_UP 2
-
-/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_4 :: gpio_023_pad_ctrl [05:04] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_023_pad_ctrl_MASK 0x00000030
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_023_pad_ctrl_SHIFT 4
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_023_pad_ctrl_DEFAULT 0x00000001
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_023_pad_ctrl_PULL_NONE 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_023_pad_ctrl_PULL_DOWN 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_023_pad_ctrl_PULL_UP 2
-
-/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_4 :: gpio_022_pad_ctrl [03:02] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_022_pad_ctrl_MASK 0x0000000c
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_022_pad_ctrl_SHIFT 2
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_022_pad_ctrl_DEFAULT 0x00000001
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_022_pad_ctrl_PULL_NONE 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_022_pad_ctrl_PULL_DOWN 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_022_pad_ctrl_PULL_UP 2
-
-/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_4 :: gpio_021_pad_ctrl [01:00] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_021_pad_ctrl_MASK 0x00000003
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_021_pad_ctrl_SHIFT 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_021_pad_ctrl_DEFAULT 0x00000001
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_021_pad_ctrl_PULL_NONE 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_021_pad_ctrl_PULL_DOWN 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_021_pad_ctrl_PULL_UP 2
-
-/***************************************************************************
- *PIN_MUX_PAD_CTRL_5 - Pad pull-up/pull-down control register 5
- ***************************************************************************/
-/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_5 :: spare_pad_ctrl_5 [31:30] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_spare_pad_ctrl_5_MASK 0xc0000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_spare_pad_ctrl_5_SHIFT 30
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_spare_pad_ctrl_5_DEFAULT 0x00000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_spare_pad_ctrl_5_PULL_NONE 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_spare_pad_ctrl_5_PULL_DOWN 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_spare_pad_ctrl_5_PULL_UP 2
-
-/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_5 :: reserved0 [29:28] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_reserved0_MASK 0x30000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_reserved0_SHIFT 28
-
-/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_5 :: gpio_049_pad_ctrl [27:26] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_049_pad_ctrl_MASK 0x0c000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_049_pad_ctrl_SHIFT 26
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_049_pad_ctrl_DEFAULT 0x00000001
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_049_pad_ctrl_PULL_NONE 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_049_pad_ctrl_PULL_DOWN 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_049_pad_ctrl_PULL_UP 2
-
-/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_5 :: gpio_048_pad_ctrl [25:24] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_048_pad_ctrl_MASK 0x03000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_048_pad_ctrl_SHIFT 24
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_048_pad_ctrl_DEFAULT 0x00000001
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_048_pad_ctrl_PULL_NONE 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_048_pad_ctrl_PULL_DOWN 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_048_pad_ctrl_PULL_UP 2
-
-/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_5 :: gpio_047_pad_ctrl [23:22] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_047_pad_ctrl_MASK 0x00c00000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_047_pad_ctrl_SHIFT 22
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_047_pad_ctrl_DEFAULT 0x00000001
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_047_pad_ctrl_PULL_NONE 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_047_pad_ctrl_PULL_DOWN 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_047_pad_ctrl_PULL_UP 2
-
-/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_5 :: gpio_046_pad_ctrl [21:20] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_046_pad_ctrl_MASK 0x00300000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_046_pad_ctrl_SHIFT 20
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_046_pad_ctrl_DEFAULT 0x00000001
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_046_pad_ctrl_PULL_NONE 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_046_pad_ctrl_PULL_DOWN 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_046_pad_ctrl_PULL_UP 2
-
-/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_5 :: gpio_045_pad_ctrl [19:18] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_045_pad_ctrl_MASK 0x000c0000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_045_pad_ctrl_SHIFT 18
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_045_pad_ctrl_DEFAULT 0x00000001
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_045_pad_ctrl_PULL_NONE 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_045_pad_ctrl_PULL_DOWN 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_045_pad_ctrl_PULL_UP 2
-
-/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_5 :: gpio_044_pad_ctrl [17:16] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_044_pad_ctrl_MASK 0x00030000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_044_pad_ctrl_SHIFT 16
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_044_pad_ctrl_DEFAULT 0x00000001
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_044_pad_ctrl_PULL_NONE 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_044_pad_ctrl_PULL_DOWN 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_044_pad_ctrl_PULL_UP 2
-
-/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_5 :: gpio_043_pad_ctrl [15:14] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_043_pad_ctrl_MASK 0x0000c000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_043_pad_ctrl_SHIFT 14
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_043_pad_ctrl_DEFAULT 0x00000001
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_043_pad_ctrl_PULL_NONE 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_043_pad_ctrl_PULL_DOWN 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_043_pad_ctrl_PULL_UP 2
-
-/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_5 :: gpio_042_pad_ctrl [13:12] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_042_pad_ctrl_MASK 0x00003000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_042_pad_ctrl_SHIFT 12
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_042_pad_ctrl_DEFAULT 0x00000001
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_042_pad_ctrl_PULL_NONE 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_042_pad_ctrl_PULL_DOWN 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_042_pad_ctrl_PULL_UP 2
-
-/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_5 :: gpio_041_pad_ctrl [11:10] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_041_pad_ctrl_MASK 0x00000c00
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_041_pad_ctrl_SHIFT 10
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_041_pad_ctrl_DEFAULT 0x00000001
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_041_pad_ctrl_PULL_NONE 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_041_pad_ctrl_PULL_DOWN 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_041_pad_ctrl_PULL_UP 2
-
-/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_5 :: gpio_040_pad_ctrl [09:08] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_040_pad_ctrl_MASK 0x00000300
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_040_pad_ctrl_SHIFT 8
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_040_pad_ctrl_DEFAULT 0x00000001
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_040_pad_ctrl_PULL_NONE 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_040_pad_ctrl_PULL_DOWN 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_040_pad_ctrl_PULL_UP 2
-
-/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_5 :: gpio_039_pad_ctrl [07:06] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_039_pad_ctrl_MASK 0x000000c0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_039_pad_ctrl_SHIFT 6
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_039_pad_ctrl_DEFAULT 0x00000001
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_039_pad_ctrl_PULL_NONE 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_039_pad_ctrl_PULL_DOWN 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_039_pad_ctrl_PULL_UP 2
-
-/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_5 :: gpio_038_pad_ctrl [05:04] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_038_pad_ctrl_MASK 0x00000030
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_038_pad_ctrl_SHIFT 4
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_038_pad_ctrl_DEFAULT 0x00000001
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_038_pad_ctrl_PULL_NONE 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_038_pad_ctrl_PULL_DOWN 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_038_pad_ctrl_PULL_UP 2
-
-/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_5 :: reserved1 [03:00] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_reserved1_MASK 0x0000000f
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_reserved1_SHIFT 0
-
-/***************************************************************************
- *PIN_MUX_PAD_CTRL_6 - Pad pull-up/pull-down control register 6
- ***************************************************************************/
-/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_6 :: spare_pad_ctrl_6 [31:30] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_spare_pad_ctrl_6_MASK 0xc0000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_spare_pad_ctrl_6_SHIFT 30
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_spare_pad_ctrl_6_DEFAULT 0x00000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_spare_pad_ctrl_6_PULL_NONE 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_spare_pad_ctrl_6_PULL_DOWN 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_spare_pad_ctrl_6_PULL_UP 2
-
-/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_6 :: gpio_065_pad_ctrl [29:28] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_065_pad_ctrl_MASK 0x30000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_065_pad_ctrl_SHIFT 28
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_065_pad_ctrl_DEFAULT 0x00000001
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_065_pad_ctrl_PULL_NONE 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_065_pad_ctrl_PULL_DOWN 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_065_pad_ctrl_PULL_UP 2
-
-/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_6 :: gpio_064_pad_ctrl [27:26] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_064_pad_ctrl_MASK 0x0c000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_064_pad_ctrl_SHIFT 26
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_064_pad_ctrl_DEFAULT 0x00000001
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_064_pad_ctrl_PULL_NONE 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_064_pad_ctrl_PULL_DOWN 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_064_pad_ctrl_PULL_UP 2
-
-/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_6 :: gpio_063_pad_ctrl [25:24] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_063_pad_ctrl_MASK 0x03000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_063_pad_ctrl_SHIFT 24
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_063_pad_ctrl_DEFAULT 0x00000001
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_063_pad_ctrl_PULL_NONE 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_063_pad_ctrl_PULL_DOWN 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_063_pad_ctrl_PULL_UP 2
-
-/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_6 :: gpio_062_pad_ctrl [23:22] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_062_pad_ctrl_MASK 0x00c00000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_062_pad_ctrl_SHIFT 22
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_062_pad_ctrl_DEFAULT 0x00000001
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_062_pad_ctrl_PULL_NONE 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_062_pad_ctrl_PULL_DOWN 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_062_pad_ctrl_PULL_UP 2
-
-/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_6 :: gpio_061_pad_ctrl [21:20] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_061_pad_ctrl_MASK 0x00300000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_061_pad_ctrl_SHIFT 20
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_061_pad_ctrl_DEFAULT 0x00000001
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_061_pad_ctrl_PULL_NONE 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_061_pad_ctrl_PULL_DOWN 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_061_pad_ctrl_PULL_UP 2
-
-/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_6 :: gpio_060_pad_ctrl [19:18] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_060_pad_ctrl_MASK 0x000c0000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_060_pad_ctrl_SHIFT 18
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_060_pad_ctrl_DEFAULT 0x00000001
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_060_pad_ctrl_PULL_NONE 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_060_pad_ctrl_PULL_DOWN 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_060_pad_ctrl_PULL_UP 2
-
-/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_6 :: gpio_059_pad_ctrl [17:16] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_059_pad_ctrl_MASK 0x00030000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_059_pad_ctrl_SHIFT 16
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_059_pad_ctrl_DEFAULT 0x00000001
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_059_pad_ctrl_PULL_NONE 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_059_pad_ctrl_PULL_DOWN 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_059_pad_ctrl_PULL_UP 2
-
-/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_6 :: gpio_058_pad_ctrl [15:14] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_058_pad_ctrl_MASK 0x0000c000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_058_pad_ctrl_SHIFT 14
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_058_pad_ctrl_DEFAULT 0x00000001
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_058_pad_ctrl_PULL_NONE 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_058_pad_ctrl_PULL_DOWN 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_058_pad_ctrl_PULL_UP 2
-
-/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_6 :: gpio_057_pad_ctrl [13:12] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_057_pad_ctrl_MASK 0x00003000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_057_pad_ctrl_SHIFT 12
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_057_pad_ctrl_DEFAULT 0x00000001
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_057_pad_ctrl_PULL_NONE 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_057_pad_ctrl_PULL_DOWN 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_057_pad_ctrl_PULL_UP 2
-
-/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_6 :: gpio_056_pad_ctrl [11:10] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_056_pad_ctrl_MASK 0x00000c00
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_056_pad_ctrl_SHIFT 10
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_056_pad_ctrl_DEFAULT 0x00000001
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_056_pad_ctrl_PULL_NONE 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_056_pad_ctrl_PULL_DOWN 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_056_pad_ctrl_PULL_UP 2
-
-/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_6 :: gpio_055_pad_ctrl [09:08] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_055_pad_ctrl_MASK 0x00000300
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_055_pad_ctrl_SHIFT 8
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_055_pad_ctrl_DEFAULT 0x00000001
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_055_pad_ctrl_PULL_NONE 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_055_pad_ctrl_PULL_DOWN 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_055_pad_ctrl_PULL_UP 2
-
-/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_6 :: gpio_054_pad_ctrl [07:06] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_054_pad_ctrl_MASK 0x000000c0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_054_pad_ctrl_SHIFT 6
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_054_pad_ctrl_DEFAULT 0x00000001
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_054_pad_ctrl_PULL_NONE 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_054_pad_ctrl_PULL_DOWN 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_054_pad_ctrl_PULL_UP 2
-
-/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_6 :: gpio_053_pad_ctrl [05:04] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_053_pad_ctrl_MASK 0x00000030
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_053_pad_ctrl_SHIFT 4
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_053_pad_ctrl_DEFAULT 0x00000001
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_053_pad_ctrl_PULL_NONE 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_053_pad_ctrl_PULL_DOWN 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_053_pad_ctrl_PULL_UP 2
-
-/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_6 :: gpio_052_pad_ctrl [03:02] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_052_pad_ctrl_MASK 0x0000000c
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_052_pad_ctrl_SHIFT 2
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_052_pad_ctrl_DEFAULT 0x00000001
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_052_pad_ctrl_PULL_NONE 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_052_pad_ctrl_PULL_DOWN 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_052_pad_ctrl_PULL_UP 2
-
-/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_6 :: gpio_051_pad_ctrl [01:00] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_051_pad_ctrl_MASK 0x00000003
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_051_pad_ctrl_SHIFT 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_051_pad_ctrl_DEFAULT 0x00000001
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_051_pad_ctrl_PULL_NONE 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_051_pad_ctrl_PULL_DOWN 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_051_pad_ctrl_PULL_UP 2
-
-/***************************************************************************
- *PIN_MUX_PAD_CTRL_7 - Pad pull-up/pull-down control register 7
- ***************************************************************************/
-/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_7 :: spare_pad_ctrl_7 [31:30] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_spare_pad_ctrl_7_MASK 0xc0000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_spare_pad_ctrl_7_SHIFT 30
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_spare_pad_ctrl_7_DEFAULT 0x00000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_spare_pad_ctrl_7_PULL_NONE 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_spare_pad_ctrl_7_PULL_DOWN 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_spare_pad_ctrl_7_PULL_UP 2
-
-/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_7 :: gpio_080_pad_ctrl [29:28] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_080_pad_ctrl_MASK 0x30000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_080_pad_ctrl_SHIFT 28
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_080_pad_ctrl_DEFAULT 0x00000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_080_pad_ctrl_PULL_NONE 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_080_pad_ctrl_PULL_DOWN 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_080_pad_ctrl_PULL_UP 2
-
-/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_7 :: gpio_079_pad_ctrl [27:26] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_079_pad_ctrl_MASK 0x0c000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_079_pad_ctrl_SHIFT 26
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_079_pad_ctrl_DEFAULT 0x00000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_079_pad_ctrl_PULL_NONE 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_079_pad_ctrl_PULL_DOWN 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_079_pad_ctrl_PULL_UP 2
-
-/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_7 :: gpio_078_pad_ctrl [25:24] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_078_pad_ctrl_MASK 0x03000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_078_pad_ctrl_SHIFT 24
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_078_pad_ctrl_DEFAULT 0x00000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_078_pad_ctrl_PULL_NONE 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_078_pad_ctrl_PULL_DOWN 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_078_pad_ctrl_PULL_UP 2
-
-/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_7 :: gpio_077_pad_ctrl [23:22] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_077_pad_ctrl_MASK 0x00c00000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_077_pad_ctrl_SHIFT 22
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_077_pad_ctrl_DEFAULT 0x00000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_077_pad_ctrl_PULL_NONE 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_077_pad_ctrl_PULL_DOWN 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_077_pad_ctrl_PULL_UP 2
-
-/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_7 :: gpio_076_pad_ctrl [21:20] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_076_pad_ctrl_MASK 0x00300000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_076_pad_ctrl_SHIFT 20
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_076_pad_ctrl_DEFAULT 0x00000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_076_pad_ctrl_PULL_NONE 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_076_pad_ctrl_PULL_DOWN 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_076_pad_ctrl_PULL_UP 2
-
-/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_7 :: gpio_075_pad_ctrl [19:18] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_075_pad_ctrl_MASK 0x000c0000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_075_pad_ctrl_SHIFT 18
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_075_pad_ctrl_DEFAULT 0x00000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_075_pad_ctrl_PULL_NONE 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_075_pad_ctrl_PULL_DOWN 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_075_pad_ctrl_PULL_UP 2
-
-/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_7 :: gpio_074_pad_ctrl [17:16] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_074_pad_ctrl_MASK 0x00030000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_074_pad_ctrl_SHIFT 16
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_074_pad_ctrl_DEFAULT 0x00000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_074_pad_ctrl_PULL_NONE 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_074_pad_ctrl_PULL_DOWN 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_074_pad_ctrl_PULL_UP 2
-
-/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_7 :: gpio_073_pad_ctrl [15:14] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_073_pad_ctrl_MASK 0x0000c000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_073_pad_ctrl_SHIFT 14
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_073_pad_ctrl_DEFAULT 0x00000001
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_073_pad_ctrl_PULL_NONE 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_073_pad_ctrl_PULL_DOWN 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_073_pad_ctrl_PULL_UP 2
-
-/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_7 :: gpio_072_pad_ctrl [13:12] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_072_pad_ctrl_MASK 0x00003000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_072_pad_ctrl_SHIFT 12
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_072_pad_ctrl_DEFAULT 0x00000001
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_072_pad_ctrl_PULL_NONE 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_072_pad_ctrl_PULL_DOWN 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_072_pad_ctrl_PULL_UP 2
-
-/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_7 :: gpio_071_pad_ctrl [11:10] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_071_pad_ctrl_MASK 0x00000c00
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_071_pad_ctrl_SHIFT 10
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_071_pad_ctrl_DEFAULT 0x00000001
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_071_pad_ctrl_PULL_NONE 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_071_pad_ctrl_PULL_DOWN 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_071_pad_ctrl_PULL_UP 2
-
-/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_7 :: gpio_070_pad_ctrl [09:08] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_070_pad_ctrl_MASK 0x00000300
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_070_pad_ctrl_SHIFT 8
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_070_pad_ctrl_DEFAULT 0x00000001
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_070_pad_ctrl_PULL_NONE 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_070_pad_ctrl_PULL_DOWN 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_070_pad_ctrl_PULL_UP 2
-
-/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_7 :: gpio_069_pad_ctrl [07:06] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_069_pad_ctrl_MASK 0x000000c0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_069_pad_ctrl_SHIFT 6
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_069_pad_ctrl_DEFAULT 0x00000001
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_069_pad_ctrl_PULL_NONE 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_069_pad_ctrl_PULL_DOWN 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_069_pad_ctrl_PULL_UP 2
-
-/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_7 :: gpio_068_pad_ctrl [05:04] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_068_pad_ctrl_MASK 0x00000030
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_068_pad_ctrl_SHIFT 4
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_068_pad_ctrl_DEFAULT 0x00000001
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_068_pad_ctrl_PULL_NONE 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_068_pad_ctrl_PULL_DOWN 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_068_pad_ctrl_PULL_UP 2
-
-/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_7 :: gpio_067_pad_ctrl [03:02] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_067_pad_ctrl_MASK 0x0000000c
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_067_pad_ctrl_SHIFT 2
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_067_pad_ctrl_DEFAULT 0x00000001
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_067_pad_ctrl_PULL_NONE 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_067_pad_ctrl_PULL_DOWN 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_067_pad_ctrl_PULL_UP 2
-
-/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_7 :: gpio_066_pad_ctrl [01:00] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_066_pad_ctrl_MASK 0x00000003
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_066_pad_ctrl_SHIFT 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_066_pad_ctrl_DEFAULT 0x00000001
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_066_pad_ctrl_PULL_NONE 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_066_pad_ctrl_PULL_DOWN 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_066_pad_ctrl_PULL_UP 2
-
-/***************************************************************************
- *PIN_MUX_PAD_CTRL_8 - Pad pull-up/pull-down control register 8
- ***************************************************************************/
-/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_8 :: spare_pad_ctrl_8 [31:30] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_spare_pad_ctrl_8_MASK 0xc0000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_spare_pad_ctrl_8_SHIFT 30
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_spare_pad_ctrl_8_DEFAULT 0x00000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_spare_pad_ctrl_8_PULL_NONE 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_spare_pad_ctrl_8_PULL_DOWN 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_spare_pad_ctrl_8_PULL_UP 2
-
-/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_8 :: reserved0 [29:28] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_reserved0_MASK 0x30000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_reserved0_SHIFT 28
-
-/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_8 :: gpio_094_pad_ctrl [27:26] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_094_pad_ctrl_MASK 0x0c000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_094_pad_ctrl_SHIFT 26
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_094_pad_ctrl_DEFAULT 0x00000001
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_094_pad_ctrl_PULL_NONE 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_094_pad_ctrl_PULL_DOWN 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_094_pad_ctrl_PULL_UP 2
-
-/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_8 :: gpio_093_pad_ctrl [25:24] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_093_pad_ctrl_MASK 0x03000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_093_pad_ctrl_SHIFT 24
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_093_pad_ctrl_DEFAULT 0x00000001
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_093_pad_ctrl_PULL_NONE 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_093_pad_ctrl_PULL_DOWN 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_093_pad_ctrl_PULL_UP 2
-
-/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_8 :: gpio_092_pad_ctrl [23:22] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_092_pad_ctrl_MASK 0x00c00000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_092_pad_ctrl_SHIFT 22
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_092_pad_ctrl_DEFAULT 0x00000001
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_092_pad_ctrl_PULL_NONE 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_092_pad_ctrl_PULL_DOWN 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_092_pad_ctrl_PULL_UP 2
-
-/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_8 :: gpio_091_pad_ctrl [21:20] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_091_pad_ctrl_MASK 0x00300000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_091_pad_ctrl_SHIFT 20
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_091_pad_ctrl_DEFAULT 0x00000001
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_091_pad_ctrl_PULL_NONE 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_091_pad_ctrl_PULL_DOWN 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_091_pad_ctrl_PULL_UP 2
-
-/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_8 :: gpio_090_pad_ctrl [19:18] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_090_pad_ctrl_MASK 0x000c0000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_090_pad_ctrl_SHIFT 18
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_090_pad_ctrl_DEFAULT 0x00000001
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_090_pad_ctrl_PULL_NONE 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_090_pad_ctrl_PULL_DOWN 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_090_pad_ctrl_PULL_UP 2
-
-/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_8 :: gpio_089_pad_ctrl [17:16] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_089_pad_ctrl_MASK 0x00030000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_089_pad_ctrl_SHIFT 16
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_089_pad_ctrl_DEFAULT 0x00000001
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_089_pad_ctrl_PULL_NONE 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_089_pad_ctrl_PULL_DOWN 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_089_pad_ctrl_PULL_UP 2
-
-/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_8 :: gpio_088_pad_ctrl [15:14] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_088_pad_ctrl_MASK 0x0000c000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_088_pad_ctrl_SHIFT 14
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_088_pad_ctrl_DEFAULT 0x00000001
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_088_pad_ctrl_PULL_NONE 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_088_pad_ctrl_PULL_DOWN 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_088_pad_ctrl_PULL_UP 2
-
-/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_8 :: gpio_087_pad_ctrl [13:12] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_087_pad_ctrl_MASK 0x00003000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_087_pad_ctrl_SHIFT 12
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_087_pad_ctrl_DEFAULT 0x00000001
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_087_pad_ctrl_PULL_NONE 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_087_pad_ctrl_PULL_DOWN 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_087_pad_ctrl_PULL_UP 2
-
-/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_8 :: gpio_086_pad_ctrl [11:10] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_086_pad_ctrl_MASK 0x00000c00
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_086_pad_ctrl_SHIFT 10
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_086_pad_ctrl_DEFAULT 0x00000001
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_086_pad_ctrl_PULL_NONE 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_086_pad_ctrl_PULL_DOWN 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_086_pad_ctrl_PULL_UP 2
-
-/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_8 :: gpio_085_pad_ctrl [09:08] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_085_pad_ctrl_MASK 0x00000300
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_085_pad_ctrl_SHIFT 8
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_085_pad_ctrl_DEFAULT 0x00000001
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_085_pad_ctrl_PULL_NONE 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_085_pad_ctrl_PULL_DOWN 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_085_pad_ctrl_PULL_UP 2
-
-/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_8 :: reserved1 [07:06] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_reserved1_MASK 0x000000c0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_reserved1_SHIFT 6
-
-/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_8 :: gpio_083_pad_ctrl [05:04] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_083_pad_ctrl_MASK 0x00000030
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_083_pad_ctrl_SHIFT 4
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_083_pad_ctrl_DEFAULT 0x00000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_083_pad_ctrl_PULL_NONE 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_083_pad_ctrl_PULL_DOWN 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_083_pad_ctrl_PULL_UP 2
-
-/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_8 :: gpio_082_pad_ctrl [03:02] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_082_pad_ctrl_MASK 0x0000000c
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_082_pad_ctrl_SHIFT 2
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_082_pad_ctrl_DEFAULT 0x00000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_082_pad_ctrl_PULL_NONE 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_082_pad_ctrl_PULL_DOWN 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_082_pad_ctrl_PULL_UP 2
-
-/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_8 :: gpio_081_pad_ctrl [01:00] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_081_pad_ctrl_MASK 0x00000003
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_081_pad_ctrl_SHIFT 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_081_pad_ctrl_DEFAULT 0x00000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_081_pad_ctrl_PULL_NONE 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_081_pad_ctrl_PULL_DOWN 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_081_pad_ctrl_PULL_UP 2
-
-/***************************************************************************
- *PIN_MUX_PAD_CTRL_9 - Pad pull-up/pull-down control register 9
- ***************************************************************************/
-/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_9 :: spare_pad_ctrl_9 [31:30] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_spare_pad_ctrl_9_MASK 0xc0000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_spare_pad_ctrl_9_SHIFT 30
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_spare_pad_ctrl_9_DEFAULT 0x00000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_spare_pad_ctrl_9_PULL_NONE 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_spare_pad_ctrl_9_PULL_DOWN 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_spare_pad_ctrl_9_PULL_UP 2
-
-/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_9 :: reserved0 [29:14] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_reserved0_MASK 0x3fffc000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_reserved0_SHIFT 14
-
-/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_9 :: gpio_102_pad_ctrl [13:12] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_102_pad_ctrl_MASK 0x00003000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_102_pad_ctrl_SHIFT 12
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_102_pad_ctrl_DEFAULT 0x00000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_102_pad_ctrl_PULL_NONE 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_102_pad_ctrl_PULL_DOWN 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_102_pad_ctrl_PULL_UP 2
-
-/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_9 :: gpio_101_pad_ctrl [11:10] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_101_pad_ctrl_MASK 0x00000c00
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_101_pad_ctrl_SHIFT 10
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_101_pad_ctrl_DEFAULT 0x00000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_101_pad_ctrl_PULL_NONE 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_101_pad_ctrl_PULL_DOWN 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_101_pad_ctrl_PULL_UP 2
-
-/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_9 :: gpio_100_pad_ctrl [09:08] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_100_pad_ctrl_MASK 0x00000300
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_100_pad_ctrl_SHIFT 8
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_100_pad_ctrl_DEFAULT 0x00000001
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_100_pad_ctrl_PULL_NONE 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_100_pad_ctrl_PULL_DOWN 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_100_pad_ctrl_PULL_UP 2
-
-/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_9 :: gpio_099_pad_ctrl [07:06] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_099_pad_ctrl_MASK 0x000000c0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_099_pad_ctrl_SHIFT 6
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_099_pad_ctrl_DEFAULT 0x00000001
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_099_pad_ctrl_PULL_NONE 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_099_pad_ctrl_PULL_DOWN 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_099_pad_ctrl_PULL_UP 2
-
-/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_9 :: gpio_098_pad_ctrl [05:04] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_098_pad_ctrl_MASK 0x00000030
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_098_pad_ctrl_SHIFT 4
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_098_pad_ctrl_DEFAULT 0x00000001
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_098_pad_ctrl_PULL_NONE 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_098_pad_ctrl_PULL_DOWN 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_098_pad_ctrl_PULL_UP 2
-
-/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_9 :: reserved1 [03:02] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_reserved1_MASK 0x0000000c
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_reserved1_SHIFT 2
-
-/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_9 :: gpio_096_pad_ctrl [01:00] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_096_pad_ctrl_MASK 0x00000003
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_096_pad_ctrl_SHIFT 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_096_pad_ctrl_DEFAULT 0x00000001
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_096_pad_ctrl_PULL_NONE 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_096_pad_ctrl_PULL_DOWN 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_096_pad_ctrl_PULL_UP 2
-
-/***************************************************************************
- *BYP_CLK_UNSELECT_0 - Bypass clock unselect register 0
- ***************************************************************************/
-/* SUN_TOP_CTRL :: BYP_CLK_UNSELECT_0 :: reserved0 [31:15] */
-#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_reserved0_MASK 0xffff8000
-#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_reserved0_SHIFT 15
-
-/* SUN_TOP_CTRL :: BYP_CLK_UNSELECT_0 :: unsel_byp_clk_on_byp_500_514p28_clk [14:14] */
-#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_byp_500_514p28_clk_MASK 0x00004000
-#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_byp_500_514p28_clk_SHIFT 14
-#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_byp_500_514p28_clk_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: BYP_CLK_UNSELECT_0 :: unsel_byp_clk_on_byp_hs_rht_clk [13:13] */
-#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_byp_hs_rht_clk_MASK 0x00002000
-#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_byp_hs_rht_clk_SHIFT 13
-#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_byp_hs_rht_clk_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: BYP_CLK_UNSELECT_0 :: unsel_byp_clk_on_gpio_073 [12:12] */
-#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_gpio_073_MASK 0x00001000
-#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_gpio_073_SHIFT 12
-#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_gpio_073_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: BYP_CLK_UNSELECT_0 :: unsel_byp_clk_on_gpio_072 [11:11] */
-#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_gpio_072_MASK 0x00000800
-#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_gpio_072_SHIFT 11
-#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_gpio_072_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: BYP_CLK_UNSELECT_0 :: unsel_byp_clk_on_gpio_071 [10:10] */
-#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_gpio_071_MASK 0x00000400
-#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_gpio_071_SHIFT 10
-#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_gpio_071_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: BYP_CLK_UNSELECT_0 :: unsel_byp_clk_on_gpio_063 [09:09] */
-#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_gpio_063_MASK 0x00000200
-#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_gpio_063_SHIFT 9
-#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_gpio_063_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: BYP_CLK_UNSELECT_0 :: unsel_byp_clk_on_gpio_035 [08:08] */
-#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_gpio_035_MASK 0x00000100
-#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_gpio_035_SHIFT 8
-#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_gpio_035_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: BYP_CLK_UNSELECT_0 :: unsel_byp_clk_on_gpio_027 [07:07] */
-#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_gpio_027_MASK 0x00000080
-#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_gpio_027_SHIFT 7
-#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_gpio_027_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: BYP_CLK_UNSELECT_0 :: unsel_byp_clk_on_sf_wpb [06:06] */
-#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_sf_wpb_MASK 0x00000040
-#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_sf_wpb_SHIFT 6
-#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_sf_wpb_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: BYP_CLK_UNSELECT_0 :: unsel_byp_clk_on_sf_holdb [05:05] */
-#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_sf_holdb_MASK 0x00000020
-#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_sf_holdb_SHIFT 5
-#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_sf_holdb_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: BYP_CLK_UNSELECT_0 :: unsel_byp_clk_on_ebi_nand_dqs [04:04] */
-#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_ebi_nand_dqs_MASK 0x00000010
-#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_ebi_nand_dqs_SHIFT 4
-#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_ebi_nand_dqs_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: BYP_CLK_UNSELECT_0 :: unsel_byp_clk_on_ebi_waitb [03:03] */
-#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_ebi_waitb_MASK 0x00000008
-#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_ebi_waitb_SHIFT 3
-#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_ebi_waitb_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: BYP_CLK_UNSELECT_0 :: unsel_byp_clk_on_ebi_dsb [02:02] */
-#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_ebi_dsb_MASK 0x00000004
-#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_ebi_dsb_SHIFT 2
-#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_ebi_dsb_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: BYP_CLK_UNSELECT_0 :: unsel_byp_clk_on_ebi_tsb [01:01] */
-#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_ebi_tsb_MASK 0x00000002
-#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_ebi_tsb_SHIFT 1
-#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_ebi_tsb_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: BYP_CLK_UNSELECT_0 :: unsel_byp_clk_on_ebi_we0b [00:00] */
-#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_ebi_we0b_MASK 0x00000001
-#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_ebi_we0b_SHIFT 0
-#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_ebi_we0b_DEFAULT 0x00000000
-
-/***************************************************************************
- *RESET_CTRL - Reset control
- ***************************************************************************/
-/* SUN_TOP_CTRL :: RESET_CTRL :: reserved0 [31:01] */
-#define BCHP_SUN_TOP_CTRL_RESET_CTRL_reserved0_MASK 0xfffffffe
-#define BCHP_SUN_TOP_CTRL_RESET_CTRL_reserved0_SHIFT 1
-
-/* SUN_TOP_CTRL :: RESET_CTRL :: clear_reset_history [00:00] */
-#define BCHP_SUN_TOP_CTRL_RESET_CTRL_clear_reset_history_MASK 0x00000001
-#define BCHP_SUN_TOP_CTRL_RESET_CTRL_clear_reset_history_SHIFT 0
-#define BCHP_SUN_TOP_CTRL_RESET_CTRL_clear_reset_history_DEFAULT 0x00000000
-
-/***************************************************************************
- *RESET_SOURCE_ENABLE - Reset source enable
- ***************************************************************************/
-/* SUN_TOP_CTRL :: RESET_SOURCE_ENABLE :: reserved0 [31:12] */
-#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_reserved0_MASK 0xfffff000
-#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_reserved0_SHIFT 12
-
-/* SUN_TOP_CTRL :: RESET_SOURCE_ENABLE :: aux_chip_level_reset_1_en_lock [11:11] */
-#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_level_reset_1_en_lock_MASK 0x00000800
-#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_level_reset_1_en_lock_SHIFT 11
-#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_level_reset_1_en_lock_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: RESET_SOURCE_ENABLE :: aux_chip_level_reset_1_enable [10:10] */
-#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_level_reset_1_enable_MASK 0x00000400
-#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_level_reset_1_enable_SHIFT 10
-#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_level_reset_1_enable_DEFAULT 0x00000001
-
-/* SUN_TOP_CTRL :: RESET_SOURCE_ENABLE :: aux_chip_level_reset_0_en_lock [09:09] */
-#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_level_reset_0_en_lock_MASK 0x00000200
-#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_level_reset_0_en_lock_SHIFT 9
-#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_level_reset_0_en_lock_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: RESET_SOURCE_ENABLE :: aux_chip_level_reset_0_enable [08:08] */
-#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_level_reset_0_enable_MASK 0x00000100
-#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_level_reset_0_enable_SHIFT 8
-#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_level_reset_0_enable_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: RESET_SOURCE_ENABLE :: aux_chip_edge_reset_1_en_lock [07:07] */
-#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_edge_reset_1_en_lock_MASK 0x00000080
-#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_edge_reset_1_en_lock_SHIFT 7
-#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_edge_reset_1_en_lock_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: RESET_SOURCE_ENABLE :: aux_chip_edge_reset_1_enable [06:06] */
-#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_edge_reset_1_enable_MASK 0x00000040
-#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_edge_reset_1_enable_SHIFT 6
-#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_edge_reset_1_enable_DEFAULT 0x00000001
-
-/* SUN_TOP_CTRL :: RESET_SOURCE_ENABLE :: aux_chip_edge_reset_0_en_lock [05:05] */
-#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_edge_reset_0_en_lock_MASK 0x00000020
-#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_edge_reset_0_en_lock_SHIFT 5
-#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_edge_reset_0_en_lock_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: RESET_SOURCE_ENABLE :: aux_chip_edge_reset_0_enable [04:04] */
-#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_edge_reset_0_enable_MASK 0x00000010
-#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_edge_reset_0_enable_SHIFT 4
-#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_edge_reset_0_enable_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: RESET_SOURCE_ENABLE :: local_sw_master_reset_en_lock [03:03] */
-#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_local_sw_master_reset_en_lock_MASK 0x00000008
-#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_local_sw_master_reset_en_lock_SHIFT 3
-#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_local_sw_master_reset_en_lock_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: RESET_SOURCE_ENABLE :: local_sw_master_reset_enable [02:02] */
-#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_local_sw_master_reset_enable_MASK 0x00000004
-#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_local_sw_master_reset_enable_SHIFT 2
-#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_local_sw_master_reset_enable_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: RESET_SOURCE_ENABLE :: sw_master_reset_en_lock [01:01] */
-#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_sw_master_reset_en_lock_MASK 0x00000002
-#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_sw_master_reset_en_lock_SHIFT 1
-#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_sw_master_reset_en_lock_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: RESET_SOURCE_ENABLE :: sw_master_reset_enable [00:00] */
-#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_sw_master_reset_enable_MASK 0x00000001
-#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_sw_master_reset_enable_SHIFT 0
-#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_sw_master_reset_enable_DEFAULT 0x00000000
-
-/***************************************************************************
- *SW_MASTER_RESET - Software master reset
- ***************************************************************************/
-/* SUN_TOP_CTRL :: SW_MASTER_RESET :: reserved0 [31:02] */
-#define BCHP_SUN_TOP_CTRL_SW_MASTER_RESET_reserved0_MASK 0xfffffffc
-#define BCHP_SUN_TOP_CTRL_SW_MASTER_RESET_reserved0_SHIFT 2
-
-/* SUN_TOP_CTRL :: SW_MASTER_RESET :: local_master_reset [01:01] */
-#define BCHP_SUN_TOP_CTRL_SW_MASTER_RESET_local_master_reset_MASK 0x00000002
-#define BCHP_SUN_TOP_CTRL_SW_MASTER_RESET_local_master_reset_SHIFT 1
-#define BCHP_SUN_TOP_CTRL_SW_MASTER_RESET_local_master_reset_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: SW_MASTER_RESET :: chip_master_reset [00:00] */
-#define BCHP_SUN_TOP_CTRL_SW_MASTER_RESET_chip_master_reset_MASK 0x00000001
-#define BCHP_SUN_TOP_CTRL_SW_MASTER_RESET_chip_master_reset_SHIFT 0
-#define BCHP_SUN_TOP_CTRL_SW_MASTER_RESET_chip_master_reset_DEFAULT 0x00000000
-
-/***************************************************************************
- *HW_RESET_EXTENSION - Hardware reset extension
- ***************************************************************************/
-/* SUN_TOP_CTRL :: HW_RESET_EXTENSION :: reserved0 [31:28] */
-#define BCHP_SUN_TOP_CTRL_HW_RESET_EXTENSION_reserved0_MASK 0xf0000000
-#define BCHP_SUN_TOP_CTRL_HW_RESET_EXTENSION_reserved0_SHIFT 28
-
-/* SUN_TOP_CTRL :: HW_RESET_EXTENSION :: hw_reset_extension [27:00] */
-#define BCHP_SUN_TOP_CTRL_HW_RESET_EXTENSION_hw_reset_extension_MASK 0x0fffffff
-#define BCHP_SUN_TOP_CTRL_HW_RESET_EXTENSION_hw_reset_extension_SHIFT 0
-#define BCHP_SUN_TOP_CTRL_HW_RESET_EXTENSION_hw_reset_extension_DEFAULT 0x00000000
-
-/***************************************************************************
- *RESET_MONITOR - Reset Monitor
- ***************************************************************************/
-/* SUN_TOP_CTRL :: RESET_MONITOR :: reserved0 [31:08] */
-#define BCHP_SUN_TOP_CTRL_RESET_MONITOR_reserved0_MASK 0xffffff00
-#define BCHP_SUN_TOP_CTRL_RESET_MONITOR_reserved0_SHIFT 8
-
-/* SUN_TOP_CTRL :: RESET_MONITOR :: cpu_sw_init_def_val [07:07] */
-#define BCHP_SUN_TOP_CTRL_RESET_MONITOR_cpu_sw_init_def_val_MASK 0x00000080
-#define BCHP_SUN_TOP_CTRL_RESET_MONITOR_cpu_sw_init_def_val_SHIFT 7
-
-/* SUN_TOP_CTRL :: RESET_MONITOR :: reset_outb_def_val [06:06] */
-#define BCHP_SUN_TOP_CTRL_RESET_MONITOR_reset_outb_def_val_MASK 0x00000040
-#define BCHP_SUN_TOP_CTRL_RESET_MONITOR_reset_outb_def_val_SHIFT 6
-
-/* SUN_TOP_CTRL :: RESET_MONITOR :: hold_cpu_in_reset_monitor [05:05] */
-#define BCHP_SUN_TOP_CTRL_RESET_MONITOR_hold_cpu_in_reset_monitor_MASK 0x00000020
-#define BCHP_SUN_TOP_CTRL_RESET_MONITOR_hold_cpu_in_reset_monitor_SHIFT 5
-
-/* SUN_TOP_CTRL :: RESET_MONITOR :: reset_outb_monitor [04:04] */
-#define BCHP_SUN_TOP_CTRL_RESET_MONITOR_reset_outb_monitor_MASK 0x00000010
-#define BCHP_SUN_TOP_CTRL_RESET_MONITOR_reset_outb_monitor_SHIFT 4
-
-/* SUN_TOP_CTRL :: RESET_MONITOR :: front_panel_reset_monitor [03:03] */
-#define BCHP_SUN_TOP_CTRL_RESET_MONITOR_front_panel_reset_monitor_MASK 0x00000008
-#define BCHP_SUN_TOP_CTRL_RESET_MONITOR_front_panel_reset_monitor_SHIFT 3
-
-/* SUN_TOP_CTRL :: RESET_MONITOR :: reset_ext_mode_monitor [02:02] */
-#define BCHP_SUN_TOP_CTRL_RESET_MONITOR_reset_ext_mode_monitor_MASK 0x00000004
-#define BCHP_SUN_TOP_CTRL_RESET_MONITOR_reset_ext_mode_monitor_SHIFT 2
-
-/* SUN_TOP_CTRL :: RESET_MONITOR :: phase5_reset_timer_monitor [01:01] */
-#define BCHP_SUN_TOP_CTRL_RESET_MONITOR_phase5_reset_timer_monitor_MASK 0x00000002
-#define BCHP_SUN_TOP_CTRL_RESET_MONITOR_phase5_reset_timer_monitor_SHIFT 1
-
-/* SUN_TOP_CTRL :: RESET_MONITOR :: phase4_reset_timer_monitor [00:00] */
-#define BCHP_SUN_TOP_CTRL_RESET_MONITOR_phase4_reset_timer_monitor_MASK 0x00000001
-#define BCHP_SUN_TOP_CTRL_RESET_MONITOR_phase4_reset_timer_monitor_SHIFT 0
-
-/***************************************************************************
- *RESET_HISTORY - Reset history
- ***************************************************************************/
-/* SUN_TOP_CTRL :: RESET_HISTORY :: reserved0 [31:30] */
-#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_reserved0_MASK 0xc0000000
-#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_reserved0_SHIFT 30
-
-/* SUN_TOP_CTRL :: RESET_HISTORY :: aux_chip_level_reset_1 [29:29] */
-#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_aux_chip_level_reset_1_MASK 0x20000000
-#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_aux_chip_level_reset_1_SHIFT 29
-
-/* SUN_TOP_CTRL :: RESET_HISTORY :: aux_chip_level_reset_0 [28:28] */
-#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_aux_chip_level_reset_0_MASK 0x10000000
-#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_aux_chip_level_reset_0_SHIFT 28
-
-/* SUN_TOP_CTRL :: RESET_HISTORY :: aux_chip_edge_reset_1 [27:27] */
-#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_aux_chip_edge_reset_1_MASK 0x08000000
-#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_aux_chip_edge_reset_1_SHIFT 27
-
-/* SUN_TOP_CTRL :: RESET_HISTORY :: aux_chip_edge_reset_0 [26:26] */
-#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_aux_chip_edge_reset_0_MASK 0x04000000
-#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_aux_chip_edge_reset_0_SHIFT 26
-
-/* SUN_TOP_CTRL :: RESET_HISTORY :: scpu_ejtag_reset [25:25] */
-#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_scpu_ejtag_reset_MASK 0x02000000
-#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_scpu_ejtag_reset_SHIFT 25
-
-/* SUN_TOP_CTRL :: RESET_HISTORY :: rg_cpu_ejtag_reset [24:24] */
-#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_rg_cpu_ejtag_reset_MASK 0x01000000
-#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_rg_cpu_ejtag_reset_SHIFT 24
-
-/* SUN_TOP_CTRL :: RESET_HISTORY :: cm_cpu_ejtag_reset [23:23] */
-#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_cm_cpu_ejtag_reset_MASK 0x00800000
-#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_cm_cpu_ejtag_reset_SHIFT 23
-
-/* SUN_TOP_CTRL :: RESET_HISTORY :: host_cpu_ejtag_reset [22:22] */
-#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_host_cpu_ejtag_reset_MASK 0x00400000
-#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_host_cpu_ejtag_reset_SHIFT 22
-
-/* SUN_TOP_CTRL :: RESET_HISTORY :: powerloss_reset [21:21] */
-#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_powerloss_reset_MASK 0x00200000
-#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_powerloss_reset_SHIFT 21
-
-/* SUN_TOP_CTRL :: RESET_HISTORY :: cm_overvoltage_1_reset [20:20] */
-#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_cm_overvoltage_1_reset_MASK 0x00100000
-#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_cm_overvoltage_1_reset_SHIFT 20
-
-/* SUN_TOP_CTRL :: RESET_HISTORY :: cm_undervoltage_1_reset [19:19] */
-#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_cm_undervoltage_1_reset_MASK 0x00080000
-#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_cm_undervoltage_1_reset_SHIFT 19
-
-/* SUN_TOP_CTRL :: RESET_HISTORY :: cm_undervoltage_0_reset [18:18] */
-#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_cm_undervoltage_0_reset_MASK 0x00040000
-#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_cm_undervoltage_0_reset_SHIFT 18
-
-/* SUN_TOP_CTRL :: RESET_HISTORY :: overvoltage_1_reset [17:17] */
-#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_overvoltage_1_reset_MASK 0x00020000
-#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_overvoltage_1_reset_SHIFT 17
-
-/* SUN_TOP_CTRL :: RESET_HISTORY :: undervoltage_1_reset [16:16] */
-#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_undervoltage_1_reset_MASK 0x00010000
-#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_undervoltage_1_reset_SHIFT 16
-
-/* SUN_TOP_CTRL :: RESET_HISTORY :: undervoltage_0_reset [15:15] */
-#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_undervoltage_0_reset_MASK 0x00008000
-#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_undervoltage_0_reset_SHIFT 15
-
-/* SUN_TOP_CTRL :: RESET_HISTORY :: cm_overtemp_reset [14:14] */
-#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_cm_overtemp_reset_MASK 0x00004000
-#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_cm_overtemp_reset_SHIFT 14
-
-/* SUN_TOP_CTRL :: RESET_HISTORY :: overtemp_reset [13:13] */
-#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_overtemp_reset_MASK 0x00002000
-#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_overtemp_reset_SHIFT 13
-
-/* SUN_TOP_CTRL :: RESET_HISTORY :: security_master_reset [12:12] */
-#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_security_master_reset_MASK 0x00001000
-#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_security_master_reset_SHIFT 12
-
-/* SUN_TOP_CTRL :: RESET_HISTORY :: aux_software_master_reset [11:11] */
-#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_aux_software_master_reset_MASK 0x00000800
-#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_aux_software_master_reset_SHIFT 11
-
-/* SUN_TOP_CTRL :: RESET_HISTORY :: local_software_master_reset [10:10] */
-#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_local_software_master_reset_MASK 0x00000400
-#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_local_software_master_reset_SHIFT 10
-
-/* SUN_TOP_CTRL :: RESET_HISTORY :: software_master_reset [09:09] */
-#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_software_master_reset_MASK 0x00000200
-#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_software_master_reset_SHIFT 9
-
-/* SUN_TOP_CTRL :: RESET_HISTORY :: pcie_1_hot_boot_reset [08:08] */
-#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_pcie_1_hot_boot_reset_MASK 0x00000100
-#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_pcie_1_hot_boot_reset_SHIFT 8
-
-/* SUN_TOP_CTRL :: RESET_HISTORY :: pcie_0_hot_boot_reset [07:07] */
-#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_pcie_0_hot_boot_reset_MASK 0x00000080
-#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_pcie_0_hot_boot_reset_SHIFT 7
-
-/* SUN_TOP_CTRL :: RESET_HISTORY :: rg_watchdog_timer_reset [06:06] */
-#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_rg_watchdog_timer_reset_MASK 0x00000040
-#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_rg_watchdog_timer_reset_SHIFT 6
-
-/* SUN_TOP_CTRL :: RESET_HISTORY :: cm_watchdog_timer_reset [05:05] */
-#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_cm_watchdog_timer_reset_MASK 0x00000020
-#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_cm_watchdog_timer_reset_SHIFT 5
-
-/* SUN_TOP_CTRL :: RESET_HISTORY :: host_watchdog_timer_reset [04:04] */
-#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_host_watchdog_timer_reset_MASK 0x00000010
-#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_host_watchdog_timer_reset_SHIFT 4
-
-/* SUN_TOP_CTRL :: RESET_HISTORY :: smartcard_insert_reset [03:03] */
-#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_smartcard_insert_reset_MASK 0x00000008
-#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_smartcard_insert_reset_SHIFT 3
-
-/* SUN_TOP_CTRL :: RESET_HISTORY :: front_panel_4sec_reset [02:02] */
-#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_front_panel_4sec_reset_MASK 0x00000004
-#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_front_panel_4sec_reset_SHIFT 2
-
-/* SUN_TOP_CTRL :: RESET_HISTORY :: main_chip_reset_input [01:01] */
-#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_main_chip_reset_input_MASK 0x00000002
-#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_main_chip_reset_input_SHIFT 1
-
-/* SUN_TOP_CTRL :: RESET_HISTORY :: power_on_reset [00:00] */
-#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_power_on_reset_MASK 0x00000001
-#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_power_on_reset_SHIFT 0
-
-/***************************************************************************
- *SW_INIT_0_SET - Software init 0 set
- ***************************************************************************/
-/* SUN_TOP_CTRL :: SW_INIT_0_SET :: rfm_sw_init [31:31] */
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_rfm_sw_init_MASK 0x80000000
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_rfm_sw_init_SHIFT 31
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_rfm_sw_init_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: SW_INIT_0_SET :: not_used_sw_init_30 [30:30] */
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_30_MASK 0x40000000
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_30_SHIFT 30
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_30_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: SW_INIT_0_SET :: sata_sw_init [29:29] */
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_sata_sw_init_MASK 0x20000000
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_sata_sw_init_SHIFT 29
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_sata_sw_init_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: SW_INIT_0_SET :: not_used_sw_init_28 [28:28] */
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_28_MASK 0x10000000
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_28_SHIFT 28
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_28_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: SW_INIT_0_SET :: not_used_sw_init_27 [27:27] */
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_27_MASK 0x08000000
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_27_SHIFT 27
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_27_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: SW_INIT_0_SET :: not_used_sw_init_26 [26:26] */
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_26_MASK 0x04000000
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_26_SHIFT 26
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_26_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: SW_INIT_0_SET :: not_used_sw_init_25 [25:25] */
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_25_MASK 0x02000000
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_25_SHIFT 25
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_25_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: SW_INIT_0_SET :: usb0_sw_init [24:24] */
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_usb0_sw_init_MASK 0x01000000
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_usb0_sw_init_SHIFT 24
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_usb0_sw_init_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: SW_INIT_0_SET :: not_used_sw_init_23 [23:23] */
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_23_MASK 0x00800000
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_23_SHIFT 23
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_23_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: SW_INIT_0_SET :: ddr1_sw_init [22:22] */
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_ddr1_sw_init_MASK 0x00400000
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_ddr1_sw_init_SHIFT 22
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_ddr1_sw_init_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: SW_INIT_0_SET :: ddr0_sw_init [21:21] */
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_ddr0_sw_init_MASK 0x00200000
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_ddr0_sw_init_SHIFT 21
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_ddr0_sw_init_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: SW_INIT_0_SET :: memc1_sw_init [20:20] */
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_memc1_sw_init_MASK 0x00100000
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_memc1_sw_init_SHIFT 20
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_memc1_sw_init_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: SW_INIT_0_SET :: memc0_sw_init [19:19] */
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_memc0_sw_init_MASK 0x00080000
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_memc0_sw_init_SHIFT 19
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_memc0_sw_init_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: SW_INIT_0_SET :: xpt_sw_init [18:18] */
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_xpt_sw_init_MASK 0x00040000
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_xpt_sw_init_SHIFT 18
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_xpt_sw_init_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: SW_INIT_0_SET :: raaga1_sw_init [17:17] */
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_raaga1_sw_init_MASK 0x00020000
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_raaga1_sw_init_SHIFT 17
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_raaga1_sw_init_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: SW_INIT_0_SET :: raaga0_sw_init [16:16] */
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_raaga0_sw_init_MASK 0x00010000
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_raaga0_sw_init_SHIFT 16
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_raaga0_sw_init_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: SW_INIT_0_SET :: aio_sw_init [15:15] */
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_aio_sw_init_MASK 0x00008000
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_aio_sw_init_SHIFT 15
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_aio_sw_init_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: SW_INIT_0_SET :: gfx_sw_init [14:14] */
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_gfx_sw_init_MASK 0x00004000
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_gfx_sw_init_SHIFT 14
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_gfx_sw_init_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: SW_INIT_0_SET :: avd1_sw_init [13:13] */
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_avd1_sw_init_MASK 0x00002000
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_avd1_sw_init_SHIFT 13
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_avd1_sw_init_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: SW_INIT_0_SET :: hvd0_sw_init [12:12] */
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_hvd0_sw_init_MASK 0x00001000
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_hvd0_sw_init_SHIFT 12
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_hvd0_sw_init_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: SW_INIT_0_SET :: dvp_hr_sw_init [11:11] */
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_dvp_hr_sw_init_MASK 0x00000800
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_dvp_hr_sw_init_SHIFT 11
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_dvp_hr_sw_init_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: SW_INIT_0_SET :: dvp_ht_sw_init [10:10] */
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_dvp_ht_sw_init_MASK 0x00000400
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_dvp_ht_sw_init_SHIFT 10
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_dvp_ht_sw_init_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: SW_INIT_0_SET :: vec_sw_init [09:09] */
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_vec_sw_init_MASK 0x00000200
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_vec_sw_init_SHIFT 9
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_vec_sw_init_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: SW_INIT_0_SET :: bvn_sw_init [08:08] */
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_bvn_sw_init_MASK 0x00000100
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_bvn_sw_init_SHIFT 8
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_bvn_sw_init_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: SW_INIT_0_SET :: not_used_sw_init_7 [07:07] */
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_7_MASK 0x00000080
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_7_SHIFT 7
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_7_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: SW_INIT_0_SET :: ebi_sw_init [06:06] */
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_ebi_sw_init_MASK 0x00000040
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_ebi_sw_init_SHIFT 6
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_ebi_sw_init_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: SW_INIT_0_SET :: not_used_sw_init_5 [05:05] */
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_5_MASK 0x00000020
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_5_SHIFT 5
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_5_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: SW_INIT_0_SET :: not_used_sw_init_4 [04:04] */
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_4_MASK 0x00000010
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_4_SHIFT 4
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_4_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: SW_INIT_0_SET :: not_used_sw_init_3 [03:03] */
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_3_MASK 0x00000008
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_3_SHIFT 3
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_3_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: SW_INIT_0_SET :: ext_sys_sw_init [02:02] */
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_ext_sys_sw_init_MASK 0x00000004
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_ext_sys_sw_init_SHIFT 2
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_ext_sys_sw_init_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: SW_INIT_0_SET :: cpu_sw_init [01:01] */
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_cpu_sw_init_MASK 0x00000002
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_cpu_sw_init_SHIFT 1
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_cpu_sw_init_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: SW_INIT_0_SET :: sys_ctrl_sw_init [00:00] */
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_sys_ctrl_sw_init_MASK 0x00000001
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_sys_ctrl_sw_init_SHIFT 0
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_sys_ctrl_sw_init_DEFAULT 0x00000000
-
-/***************************************************************************
- *SW_INIT_0_CLEAR - Software init 0 clear
- ***************************************************************************/
-/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: rfm_sw_init [31:31] */
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_rfm_sw_init_MASK 0x80000000
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_rfm_sw_init_SHIFT 31
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_rfm_sw_init_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: not_used_sw_init_30 [30:30] */
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_30_MASK 0x40000000
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_30_SHIFT 30
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_30_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: sata_sw_init [29:29] */
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_sata_sw_init_MASK 0x20000000
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_sata_sw_init_SHIFT 29
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_sata_sw_init_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: not_used_sw_init_28 [28:28] */
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_28_MASK 0x10000000
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_28_SHIFT 28
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_28_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: not_used_sw_init_27 [27:27] */
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_27_MASK 0x08000000
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_27_SHIFT 27
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_27_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: not_used_sw_init_26 [26:26] */
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_26_MASK 0x04000000
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_26_SHIFT 26
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_26_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: not_used_sw_init_25 [25:25] */
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_25_MASK 0x02000000
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_25_SHIFT 25
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_25_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: usb0_sw_init [24:24] */
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_usb0_sw_init_MASK 0x01000000
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_usb0_sw_init_SHIFT 24
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_usb0_sw_init_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: not_used_sw_init_23 [23:23] */
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_23_MASK 0x00800000
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_23_SHIFT 23
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_23_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: ddr1_sw_init [22:22] */
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_ddr1_sw_init_MASK 0x00400000
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_ddr1_sw_init_SHIFT 22
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_ddr1_sw_init_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: ddr0_sw_init [21:21] */
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_ddr0_sw_init_MASK 0x00200000
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_ddr0_sw_init_SHIFT 21
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_ddr0_sw_init_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: memc1_sw_init [20:20] */
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_memc1_sw_init_MASK 0x00100000
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_memc1_sw_init_SHIFT 20
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_memc1_sw_init_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: memc0_sw_init [19:19] */
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_memc0_sw_init_MASK 0x00080000
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_memc0_sw_init_SHIFT 19
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_memc0_sw_init_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: xpt_sw_init [18:18] */
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_xpt_sw_init_MASK 0x00040000
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_xpt_sw_init_SHIFT 18
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_xpt_sw_init_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: raaga1_sw_init [17:17] */
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_raaga1_sw_init_MASK 0x00020000
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_raaga1_sw_init_SHIFT 17
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_raaga1_sw_init_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: raaga0_sw_init [16:16] */
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_raaga0_sw_init_MASK 0x00010000
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_raaga0_sw_init_SHIFT 16
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_raaga0_sw_init_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: aio_sw_init [15:15] */
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_aio_sw_init_MASK 0x00008000
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_aio_sw_init_SHIFT 15
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_aio_sw_init_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: gfx_sw_init [14:14] */
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_gfx_sw_init_MASK 0x00004000
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_gfx_sw_init_SHIFT 14
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_gfx_sw_init_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: avd1_sw_init [13:13] */
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_avd1_sw_init_MASK 0x00002000
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_avd1_sw_init_SHIFT 13
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_avd1_sw_init_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: hvd0_sw_init [12:12] */
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_hvd0_sw_init_MASK 0x00001000
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_hvd0_sw_init_SHIFT 12
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_hvd0_sw_init_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: dvp_hr_sw_init [11:11] */
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_dvp_hr_sw_init_MASK 0x00000800
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_dvp_hr_sw_init_SHIFT 11
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_dvp_hr_sw_init_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: dvp_ht_sw_init [10:10] */
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_dvp_ht_sw_init_MASK 0x00000400
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_dvp_ht_sw_init_SHIFT 10
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_dvp_ht_sw_init_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: vec_sw_init [09:09] */
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_vec_sw_init_MASK 0x00000200
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_vec_sw_init_SHIFT 9
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_vec_sw_init_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: bvn_sw_init [08:08] */
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_bvn_sw_init_MASK 0x00000100
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_bvn_sw_init_SHIFT 8
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_bvn_sw_init_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: not_used_sw_init_7 [07:07] */
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_7_MASK 0x00000080
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_7_SHIFT 7
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_7_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: ebi_sw_init [06:06] */
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_ebi_sw_init_MASK 0x00000040
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_ebi_sw_init_SHIFT 6
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_ebi_sw_init_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: not_used_sw_init_5 [05:05] */
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_5_MASK 0x00000020
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_5_SHIFT 5
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_5_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: not_used_sw_init_4 [04:04] */
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_4_MASK 0x00000010
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_4_SHIFT 4
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_4_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: not_used_sw_init_3 [03:03] */
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_3_MASK 0x00000008
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_3_SHIFT 3
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_3_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: ext_sys_sw_init [02:02] */
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_ext_sys_sw_init_MASK 0x00000004
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_ext_sys_sw_init_SHIFT 2
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_ext_sys_sw_init_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: cpu_sw_init [01:01] */
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_cpu_sw_init_MASK 0x00000002
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_cpu_sw_init_SHIFT 1
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_cpu_sw_init_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: sys_ctrl_sw_init [00:00] */
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_sys_ctrl_sw_init_MASK 0x00000001
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_sys_ctrl_sw_init_SHIFT 0
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_sys_ctrl_sw_init_DEFAULT 0x00000000
-
-/***************************************************************************
- *SW_INIT_0_STATUS - Software init 0 status
- ***************************************************************************/
-/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: rfm_sw_init [31:31] */
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_rfm_sw_init_MASK 0x80000000
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_rfm_sw_init_SHIFT 31
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_rfm_sw_init_DEFAULT 0x00000001
-
-/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: not_used_sw_init_30 [30:30] */
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_30_MASK 0x40000000
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_30_SHIFT 30
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_30_DEFAULT 0x00000001
-
-/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: sata_sw_init [29:29] */
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_sata_sw_init_MASK 0x20000000
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_sata_sw_init_SHIFT 29
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_sata_sw_init_DEFAULT 0x00000001
-
-/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: not_used_sw_init_28 [28:28] */
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_28_MASK 0x10000000
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_28_SHIFT 28
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_28_DEFAULT 0x00000001
-
-/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: not_used_sw_init_27 [27:27] */
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_27_MASK 0x08000000
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_27_SHIFT 27
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_27_DEFAULT 0x00000001
-
-/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: not_used_sw_init_26 [26:26] */
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_26_MASK 0x04000000
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_26_SHIFT 26
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_26_DEFAULT 0x00000001
-
-/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: not_used_sw_init_25 [25:25] */
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_25_MASK 0x02000000
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_25_SHIFT 25
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_25_DEFAULT 0x00000001
-
-/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: usb0_sw_init [24:24] */
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_usb0_sw_init_MASK 0x01000000
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_usb0_sw_init_SHIFT 24
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_usb0_sw_init_DEFAULT 0x00000001
-
-/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: not_used_sw_init_23 [23:23] */
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_23_MASK 0x00800000
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_23_SHIFT 23
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_23_DEFAULT 0x00000001
-
-/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: ddr1_sw_init [22:22] */
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_ddr1_sw_init_MASK 0x00400000
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_ddr1_sw_init_SHIFT 22
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_ddr1_sw_init_DEFAULT 0x00000001
-
-/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: ddr0_sw_init [21:21] */
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_ddr0_sw_init_MASK 0x00200000
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_ddr0_sw_init_SHIFT 21
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_ddr0_sw_init_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: memc1_sw_init [20:20] */
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_memc1_sw_init_MASK 0x00100000
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_memc1_sw_init_SHIFT 20
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_memc1_sw_init_DEFAULT 0x00000001
-
-/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: memc0_sw_init [19:19] */
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_memc0_sw_init_MASK 0x00080000
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_memc0_sw_init_SHIFT 19
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_memc0_sw_init_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: xpt_sw_init [18:18] */
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_xpt_sw_init_MASK 0x00040000
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_xpt_sw_init_SHIFT 18
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_xpt_sw_init_DEFAULT 0x00000001
-
-/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: raaga1_sw_init [17:17] */
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_raaga1_sw_init_MASK 0x00020000
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_raaga1_sw_init_SHIFT 17
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_raaga1_sw_init_DEFAULT 0x00000001
-
-/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: raaga0_sw_init [16:16] */
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_raaga0_sw_init_MASK 0x00010000
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_raaga0_sw_init_SHIFT 16
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_raaga0_sw_init_DEFAULT 0x00000001
-
-/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: aio_sw_init [15:15] */
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_aio_sw_init_MASK 0x00008000
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_aio_sw_init_SHIFT 15
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_aio_sw_init_DEFAULT 0x00000001
-
-/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: gfx_sw_init [14:14] */
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_gfx_sw_init_MASK 0x00004000
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_gfx_sw_init_SHIFT 14
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_gfx_sw_init_DEFAULT 0x00000001
-
-/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: avd1_sw_init [13:13] */
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_avd1_sw_init_MASK 0x00002000
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_avd1_sw_init_SHIFT 13
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_avd1_sw_init_DEFAULT 0x00000001
-
-/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: hvd0_sw_init [12:12] */
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_hvd0_sw_init_MASK 0x00001000
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_hvd0_sw_init_SHIFT 12
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_hvd0_sw_init_DEFAULT 0x00000001
-
-/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: dvp_hr_sw_init [11:11] */
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_dvp_hr_sw_init_MASK 0x00000800
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_dvp_hr_sw_init_SHIFT 11
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_dvp_hr_sw_init_DEFAULT 0x00000001
-
-/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: dvp_ht_sw_init [10:10] */
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_dvp_ht_sw_init_MASK 0x00000400
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_dvp_ht_sw_init_SHIFT 10
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_dvp_ht_sw_init_DEFAULT 0x00000001
-
-/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: vec_sw_init [09:09] */
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_vec_sw_init_MASK 0x00000200
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_vec_sw_init_SHIFT 9
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_vec_sw_init_DEFAULT 0x00000001
-
-/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: bvn_sw_init [08:08] */
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_bvn_sw_init_MASK 0x00000100
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_bvn_sw_init_SHIFT 8
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_bvn_sw_init_DEFAULT 0x00000001
-
-/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: not_used_sw_init_7 [07:07] */
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_7_MASK 0x00000080
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_7_SHIFT 7
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_7_DEFAULT 0x00000001
-
-/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: ebi_sw_init [06:06] */
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_ebi_sw_init_MASK 0x00000040
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_ebi_sw_init_SHIFT 6
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_ebi_sw_init_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: not_used_sw_init_5 [05:05] */
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_5_MASK 0x00000020
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_5_SHIFT 5
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_5_DEFAULT 0x00000001
-
-/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: not_used_sw_init_4 [04:04] */
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_4_MASK 0x00000010
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_4_SHIFT 4
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_4_DEFAULT 0x00000001
-
-/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: not_used_sw_init_3 [03:03] */
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_3_MASK 0x00000008
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_3_SHIFT 3
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_3_DEFAULT 0x00000001
-
-/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: ext_sys_sw_init [02:02] */
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_ext_sys_sw_init_MASK 0x00000004
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_ext_sys_sw_init_SHIFT 2
-
-/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: cpu_sw_init [01:01] */
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_cpu_sw_init_MASK 0x00000002
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_cpu_sw_init_SHIFT 1
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_cpu_sw_init_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: sys_ctrl_sw_init [00:00] */
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_sys_ctrl_sw_init_MASK 0x00000001
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_sys_ctrl_sw_init_SHIFT 0
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_sys_ctrl_sw_init_DEFAULT 0x00000000
-
-/***************************************************************************
- *SEC_SW_INIT_0_MONITOR - Security software init 0 monitor
- ***************************************************************************/
-/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: rfm_sw_init [31:31] */
-#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_rfm_sw_init_MASK 0x80000000
-#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_rfm_sw_init_SHIFT 31
-
-/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: not_used_sw_init_30 [30:30] */
-#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_not_used_sw_init_30_MASK 0x40000000
-#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_not_used_sw_init_30_SHIFT 30
-
-/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: sata_sw_init [29:29] */
-#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_sata_sw_init_MASK 0x20000000
-#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_sata_sw_init_SHIFT 29
-
-/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: not_used_sw_init_28 [28:28] */
-#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_not_used_sw_init_28_MASK 0x10000000
-#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_not_used_sw_init_28_SHIFT 28
-
-/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: not_used_sw_init_27 [27:27] */
-#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_not_used_sw_init_27_MASK 0x08000000
-#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_not_used_sw_init_27_SHIFT 27
-
-/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: not_used_sw_init_26 [26:26] */
-#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_not_used_sw_init_26_MASK 0x04000000
-#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_not_used_sw_init_26_SHIFT 26
-
-/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: not_used_sw_init_25 [25:25] */
-#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_not_used_sw_init_25_MASK 0x02000000
-#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_not_used_sw_init_25_SHIFT 25
-
-/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: usb0_sw_init [24:24] */
-#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_usb0_sw_init_MASK 0x01000000
-#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_usb0_sw_init_SHIFT 24
-
-/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: not_used_sw_init_23 [23:23] */
-#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_not_used_sw_init_23_MASK 0x00800000
-#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_not_used_sw_init_23_SHIFT 23
-
-/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: ddr1_sw_init [22:22] */
-#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_ddr1_sw_init_MASK 0x00400000
-#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_ddr1_sw_init_SHIFT 22
-
-/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: ddr0_sw_init [21:21] */
-#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_ddr0_sw_init_MASK 0x00200000
-#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_ddr0_sw_init_SHIFT 21
-
-/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: memc1_sw_init [20:20] */
-#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_memc1_sw_init_MASK 0x00100000
-#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_memc1_sw_init_SHIFT 20
-
-/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: memc0_sw_init [19:19] */
-#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_memc0_sw_init_MASK 0x00080000
-#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_memc0_sw_init_SHIFT 19
-
-/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: xpt_sw_init [18:18] */
-#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_xpt_sw_init_MASK 0x00040000
-#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_xpt_sw_init_SHIFT 18
-
-/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: raaga1_sw_init [17:17] */
-#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_raaga1_sw_init_MASK 0x00020000
-#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_raaga1_sw_init_SHIFT 17
-
-/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: raaga0_sw_init [16:16] */
-#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_raaga0_sw_init_MASK 0x00010000
-#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_raaga0_sw_init_SHIFT 16
-
-/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: aio_sw_init [15:15] */
-#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_aio_sw_init_MASK 0x00008000
-#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_aio_sw_init_SHIFT 15
-
-/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: gfx_sw_init [14:14] */
-#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_gfx_sw_init_MASK 0x00004000
-#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_gfx_sw_init_SHIFT 14
-
-/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: avd1_sw_init [13:13] */
-#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_avd1_sw_init_MASK 0x00002000
-#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_avd1_sw_init_SHIFT 13
-
-/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: hvd0_sw_init [12:12] */
-#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_hvd0_sw_init_MASK 0x00001000
-#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_hvd0_sw_init_SHIFT 12
-
-/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: dvp_hr_sw_init [11:11] */
-#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_dvp_hr_sw_init_MASK 0x00000800
-#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_dvp_hr_sw_init_SHIFT 11
-
-/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: dvp_ht_sw_init [10:10] */
-#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_dvp_ht_sw_init_MASK 0x00000400
-#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_dvp_ht_sw_init_SHIFT 10
-
-/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: vec_sw_init [09:09] */
-#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_vec_sw_init_MASK 0x00000200
-#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_vec_sw_init_SHIFT 9
-
-/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: bvn_sw_init [08:08] */
-#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_bvn_sw_init_MASK 0x00000100
-#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_bvn_sw_init_SHIFT 8
-
-/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: not_used_sw_init_7 [07:07] */
-#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_not_used_sw_init_7_MASK 0x00000080
-#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_not_used_sw_init_7_SHIFT 7
-
-/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: ebi_sw_init [06:06] */
-#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_ebi_sw_init_MASK 0x00000040
-#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_ebi_sw_init_SHIFT 6
-
-/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: not_used_sw_init_5 [05:05] */
-#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_not_used_sw_init_5_MASK 0x00000020
-#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_not_used_sw_init_5_SHIFT 5
-
-/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: not_used_sw_init_4 [04:04] */
-#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_not_used_sw_init_4_MASK 0x00000010
-#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_not_used_sw_init_4_SHIFT 4
-
-/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: not_used_sw_init_3 [03:03] */
-#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_not_used_sw_init_3_MASK 0x00000008
-#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_not_used_sw_init_3_SHIFT 3
-
-/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: ext_sys_sw_init [02:02] */
-#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_ext_sys_sw_init_MASK 0x00000004
-#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_ext_sys_sw_init_SHIFT 2
-
-/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: cpu_sw_init [01:01] */
-#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_cpu_sw_init_MASK 0x00000002
-#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_cpu_sw_init_SHIFT 1
-
-/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: sys_ctrl_sw_init [00:00] */
-#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_sys_ctrl_sw_init_MASK 0x00000001
-#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_sys_ctrl_sw_init_SHIFT 0
-
-/***************************************************************************
- *TEST_CONFIG_SW_INIT_0_MONITOR - Test configuration software init 0 monitor
- ***************************************************************************/
-/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: rfm_sw_init [31:31] */
-#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_rfm_sw_init_MASK 0x80000000
-#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_rfm_sw_init_SHIFT 31
-
-/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: not_used_sw_init_30 [30:30] */
-#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_not_used_sw_init_30_MASK 0x40000000
-#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_not_used_sw_init_30_SHIFT 30
-
-/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: sata_sw_init [29:29] */
-#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_sata_sw_init_MASK 0x20000000
-#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_sata_sw_init_SHIFT 29
-
-/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: not_used_sw_init_28 [28:28] */
-#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_not_used_sw_init_28_MASK 0x10000000
-#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_not_used_sw_init_28_SHIFT 28
-
-/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: not_used_sw_init_27 [27:27] */
-#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_not_used_sw_init_27_MASK 0x08000000
-#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_not_used_sw_init_27_SHIFT 27
-
-/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: not_used_sw_init_26 [26:26] */
-#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_not_used_sw_init_26_MASK 0x04000000
-#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_not_used_sw_init_26_SHIFT 26
-
-/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: not_used_sw_init_25 [25:25] */
-#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_not_used_sw_init_25_MASK 0x02000000
-#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_not_used_sw_init_25_SHIFT 25
-
-/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: usb0_sw_init [24:24] */
-#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_usb0_sw_init_MASK 0x01000000
-#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_usb0_sw_init_SHIFT 24
-
-/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: not_used_sw_init_23 [23:23] */
-#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_not_used_sw_init_23_MASK 0x00800000
-#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_not_used_sw_init_23_SHIFT 23
-
-/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: ddr1_sw_init [22:22] */
-#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_ddr1_sw_init_MASK 0x00400000
-#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_ddr1_sw_init_SHIFT 22
-
-/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: ddr0_sw_init [21:21] */
-#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_ddr0_sw_init_MASK 0x00200000
-#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_ddr0_sw_init_SHIFT 21
-
-/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: memc1_sw_init [20:20] */
-#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_memc1_sw_init_MASK 0x00100000
-#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_memc1_sw_init_SHIFT 20
-
-/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: memc0_sw_init [19:19] */
-#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_memc0_sw_init_MASK 0x00080000
-#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_memc0_sw_init_SHIFT 19
-
-/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: xpt_sw_init [18:18] */
-#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_xpt_sw_init_MASK 0x00040000
-#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_xpt_sw_init_SHIFT 18
-
-/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: raaga1_sw_init [17:17] */
-#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_raaga1_sw_init_MASK 0x00020000
-#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_raaga1_sw_init_SHIFT 17
-
-/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: raaga0_sw_init [16:16] */
-#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_raaga0_sw_init_MASK 0x00010000
-#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_raaga0_sw_init_SHIFT 16
-
-/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: aio_sw_init [15:15] */
-#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_aio_sw_init_MASK 0x00008000
-#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_aio_sw_init_SHIFT 15
-
-/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: gfx_sw_init [14:14] */
-#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_gfx_sw_init_MASK 0x00004000
-#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_gfx_sw_init_SHIFT 14
-
-/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: avd1_sw_init [13:13] */
-#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_avd1_sw_init_MASK 0x00002000
-#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_avd1_sw_init_SHIFT 13
-
-/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: hvd0_sw_init [12:12] */
-#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_hvd0_sw_init_MASK 0x00001000
-#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_hvd0_sw_init_SHIFT 12
-
-/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: dvp_hr_sw_init [11:11] */
-#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_dvp_hr_sw_init_MASK 0x00000800
-#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_dvp_hr_sw_init_SHIFT 11
-
-/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: dvp_ht_sw_init [10:10] */
-#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_dvp_ht_sw_init_MASK 0x00000400
-#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_dvp_ht_sw_init_SHIFT 10
-
-/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: vec_sw_init [09:09] */
-#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_vec_sw_init_MASK 0x00000200
-#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_vec_sw_init_SHIFT 9
-
-/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: bvn_sw_init [08:08] */
-#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_bvn_sw_init_MASK 0x00000100
-#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_bvn_sw_init_SHIFT 8
-
-/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: not_used_sw_init_7 [07:07] */
-#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_not_used_sw_init_7_MASK 0x00000080
-#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_not_used_sw_init_7_SHIFT 7
-
-/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: ebi_sw_init [06:06] */
-#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_ebi_sw_init_MASK 0x00000040
-#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_ebi_sw_init_SHIFT 6
-
-/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: not_used_sw_init_5 [05:05] */
-#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_not_used_sw_init_5_MASK 0x00000020
-#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_not_used_sw_init_5_SHIFT 5
-
-/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: not_used_sw_init_4 [04:04] */
-#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_not_used_sw_init_4_MASK 0x00000010
-#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_not_used_sw_init_4_SHIFT 4
-
-/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: not_used_sw_init_3 [03:03] */
-#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_not_used_sw_init_3_MASK 0x00000008
-#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_not_used_sw_init_3_SHIFT 3
-
-/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: ext_sys_sw_init [02:02] */
-#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_ext_sys_sw_init_MASK 0x00000004
-#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_ext_sys_sw_init_SHIFT 2
-
-/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: cpu_sw_init [01:01] */
-#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_cpu_sw_init_MASK 0x00000002
-#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_cpu_sw_init_SHIFT 1
-
-/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: sys_ctrl_sw_init [00:00] */
-#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_sys_ctrl_sw_init_MASK 0x00000001
-#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_sys_ctrl_sw_init_SHIFT 0
-
-/***************************************************************************
- *FINAL_SW_INIT_0_MONITOR - Final software init 0 monitor
- ***************************************************************************/
-/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: rfm_sw_init [31:31] */
-#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_rfm_sw_init_MASK 0x80000000
-#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_rfm_sw_init_SHIFT 31
-
-/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: not_used_sw_init_30 [30:30] */
-#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_not_used_sw_init_30_MASK 0x40000000
-#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_not_used_sw_init_30_SHIFT 30
-
-/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: sata_sw_init [29:29] */
-#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_sata_sw_init_MASK 0x20000000
-#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_sata_sw_init_SHIFT 29
-
-/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: not_used_sw_init_28 [28:28] */
-#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_not_used_sw_init_28_MASK 0x10000000
-#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_not_used_sw_init_28_SHIFT 28
-
-/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: not_used_sw_init_27 [27:27] */
-#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_not_used_sw_init_27_MASK 0x08000000
-#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_not_used_sw_init_27_SHIFT 27
-
-/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: not_used_sw_init_26 [26:26] */
-#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_not_used_sw_init_26_MASK 0x04000000
-#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_not_used_sw_init_26_SHIFT 26
-
-/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: not_used_sw_init_25 [25:25] */
-#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_not_used_sw_init_25_MASK 0x02000000
-#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_not_used_sw_init_25_SHIFT 25
-
-/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: usb0_sw_init [24:24] */
-#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_usb0_sw_init_MASK 0x01000000
-#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_usb0_sw_init_SHIFT 24
-
-/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: not_used_sw_init_23 [23:23] */
-#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_not_used_sw_init_23_MASK 0x00800000
-#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_not_used_sw_init_23_SHIFT 23
-
-/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: ddr1_sw_init [22:22] */
-#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_ddr1_sw_init_MASK 0x00400000
-#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_ddr1_sw_init_SHIFT 22
-
-/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: ddr0_sw_init [21:21] */
-#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_ddr0_sw_init_MASK 0x00200000
-#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_ddr0_sw_init_SHIFT 21
-
-/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: memc1_sw_init [20:20] */
-#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_memc1_sw_init_MASK 0x00100000
-#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_memc1_sw_init_SHIFT 20
-
-/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: memc0_sw_init [19:19] */
-#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_memc0_sw_init_MASK 0x00080000
-#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_memc0_sw_init_SHIFT 19
-
-/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: xpt_sw_init [18:18] */
-#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_xpt_sw_init_MASK 0x00040000
-#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_xpt_sw_init_SHIFT 18
-
-/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: raaga1_sw_init [17:17] */
-#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_raaga1_sw_init_MASK 0x00020000
-#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_raaga1_sw_init_SHIFT 17
-
-/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: raaga0_sw_init [16:16] */
-#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_raaga0_sw_init_MASK 0x00010000
-#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_raaga0_sw_init_SHIFT 16
-
-/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: aio_sw_init [15:15] */
-#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_aio_sw_init_MASK 0x00008000
-#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_aio_sw_init_SHIFT 15
-
-/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: gfx_sw_init [14:14] */
-#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_gfx_sw_init_MASK 0x00004000
-#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_gfx_sw_init_SHIFT 14
-
-/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: avd1_sw_init [13:13] */
-#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_avd1_sw_init_MASK 0x00002000
-#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_avd1_sw_init_SHIFT 13
-
-/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: hvd0_sw_init [12:12] */
-#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_hvd0_sw_init_MASK 0x00001000
-#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_hvd0_sw_init_SHIFT 12
-
-/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: dvp_hr_sw_init [11:11] */
-#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_dvp_hr_sw_init_MASK 0x00000800
-#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_dvp_hr_sw_init_SHIFT 11
-
-/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: dvp_ht_sw_init [10:10] */
-#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_dvp_ht_sw_init_MASK 0x00000400
-#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_dvp_ht_sw_init_SHIFT 10
-
-/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: vec_sw_init [09:09] */
-#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_vec_sw_init_MASK 0x00000200
-#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_vec_sw_init_SHIFT 9
-
-/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: bvn_sw_init [08:08] */
-#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_bvn_sw_init_MASK 0x00000100
-#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_bvn_sw_init_SHIFT 8
-
-/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: not_used_sw_init_7 [07:07] */
-#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_not_used_sw_init_7_MASK 0x00000080
-#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_not_used_sw_init_7_SHIFT 7
-
-/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: ebi_sw_init [06:06] */
-#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_ebi_sw_init_MASK 0x00000040
-#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_ebi_sw_init_SHIFT 6
-
-/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: not_used_sw_init_5 [05:05] */
-#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_not_used_sw_init_5_MASK 0x00000020
-#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_not_used_sw_init_5_SHIFT 5
-
-/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: not_used_sw_init_4 [04:04] */
-#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_not_used_sw_init_4_MASK 0x00000010
-#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_not_used_sw_init_4_SHIFT 4
-
-/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: not_used_sw_init_3 [03:03] */
-#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_not_used_sw_init_3_MASK 0x00000008
-#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_not_used_sw_init_3_SHIFT 3
-
-/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: ext_sys_sw_init [02:02] */
-#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_ext_sys_sw_init_MASK 0x00000004
-#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_ext_sys_sw_init_SHIFT 2
-
-/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: cpu_sw_init [01:01] */
-#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_cpu_sw_init_MASK 0x00000002
-#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_cpu_sw_init_SHIFT 1
-
-/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: sys_ctrl_sw_init [00:00] */
-#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_sys_ctrl_sw_init_MASK 0x00000001
-#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_sys_ctrl_sw_init_SHIFT 0
-
-/***************************************************************************
- *SW_INIT_1_SET - Software init 1 set
- ***************************************************************************/
-/* SUN_TOP_CTRL :: SW_INIT_1_SET :: reserved0 [31:07] */
-#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_reserved0_MASK 0xffffff80
-#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_reserved0_SHIFT 7
-
-/* SUN_TOP_CTRL :: SW_INIT_1_SET :: spare1_sw_init [06:06] */
-#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_spare1_sw_init_MASK 0x00000040
-#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_spare1_sw_init_SHIFT 6
-#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_spare1_sw_init_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: SW_INIT_1_SET :: spare0_sw_init [05:05] */
-#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_spare0_sw_init_MASK 0x00000020
-#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_spare0_sw_init_SHIFT 5
-#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_spare0_sw_init_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: SW_INIT_1_SET :: m2mc1_sw_init [04:04] */
-#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_m2mc1_sw_init_MASK 0x00000010
-#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_m2mc1_sw_init_SHIFT 4
-#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_m2mc1_sw_init_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: SW_INIT_1_SET :: v3d_top_sw_init [03:03] */
-#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_v3d_top_sw_init_MASK 0x00000008
-#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_v3d_top_sw_init_SHIFT 3
-#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_v3d_top_sw_init_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: SW_INIT_1_SET :: vice21_sw_init [02:02] */
-#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_vice21_sw_init_MASK 0x00000004
-#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_vice21_sw_init_SHIFT 2
-#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_vice21_sw_init_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: SW_INIT_1_SET :: vice20_sw_init [01:01] */
-#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_vice20_sw_init_MASK 0x00000002
-#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_vice20_sw_init_SHIFT 1
-#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_vice20_sw_init_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: SW_INIT_1_SET :: sid_sw_init [00:00] */
-#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_sid_sw_init_MASK 0x00000001
-#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_sid_sw_init_SHIFT 0
-#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_sid_sw_init_DEFAULT 0x00000000
-
-/***************************************************************************
- *SW_INIT_1_CLEAR - Software init 1 clear
- ***************************************************************************/
-/* SUN_TOP_CTRL :: SW_INIT_1_CLEAR :: reserved0 [31:07] */
-#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_reserved0_MASK 0xffffff80
-#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_reserved0_SHIFT 7
-
-/* SUN_TOP_CTRL :: SW_INIT_1_CLEAR :: spare1_sw_init [06:06] */
-#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_spare1_sw_init_MASK 0x00000040
-#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_spare1_sw_init_SHIFT 6
-#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_spare1_sw_init_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: SW_INIT_1_CLEAR :: spare0_sw_init [05:05] */
-#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_spare0_sw_init_MASK 0x00000020
-#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_spare0_sw_init_SHIFT 5
-#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_spare0_sw_init_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: SW_INIT_1_CLEAR :: m2mc1_sw_init [04:04] */
-#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_m2mc1_sw_init_MASK 0x00000010
-#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_m2mc1_sw_init_SHIFT 4
-#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_m2mc1_sw_init_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: SW_INIT_1_CLEAR :: v3d_top_sw_init [03:03] */
-#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_v3d_top_sw_init_MASK 0x00000008
-#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_v3d_top_sw_init_SHIFT 3
-#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_v3d_top_sw_init_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: SW_INIT_1_CLEAR :: vice21_sw_init [02:02] */
-#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_vice21_sw_init_MASK 0x00000004
-#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_vice21_sw_init_SHIFT 2
-#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_vice21_sw_init_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: SW_INIT_1_CLEAR :: vice20_sw_init [01:01] */
-#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_vice20_sw_init_MASK 0x00000002
-#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_vice20_sw_init_SHIFT 1
-#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_vice20_sw_init_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: SW_INIT_1_CLEAR :: sid_sw_init [00:00] */
-#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_sid_sw_init_MASK 0x00000001
-#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_sid_sw_init_SHIFT 0
-#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_sid_sw_init_DEFAULT 0x00000000
-
-/***************************************************************************
- *SW_INIT_1_STATUS - Software init 1 status
- ***************************************************************************/
-/* SUN_TOP_CTRL :: SW_INIT_1_STATUS :: reserved0 [31:07] */
-#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_reserved0_MASK 0xffffff80
-#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_reserved0_SHIFT 7
-
-/* SUN_TOP_CTRL :: SW_INIT_1_STATUS :: spare1_sw_init [06:06] */
-#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_spare1_sw_init_MASK 0x00000040
-#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_spare1_sw_init_SHIFT 6
-#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_spare1_sw_init_DEFAULT 0x00000001
-
-/* SUN_TOP_CTRL :: SW_INIT_1_STATUS :: spare0_sw_init [05:05] */
-#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_spare0_sw_init_MASK 0x00000020
-#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_spare0_sw_init_SHIFT 5
-#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_spare0_sw_init_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: SW_INIT_1_STATUS :: m2mc1_sw_init [04:04] */
-#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_m2mc1_sw_init_MASK 0x00000010
-#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_m2mc1_sw_init_SHIFT 4
-#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_m2mc1_sw_init_DEFAULT 0x00000001
-
-/* SUN_TOP_CTRL :: SW_INIT_1_STATUS :: v3d_top_sw_init [03:03] */
-#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_v3d_top_sw_init_MASK 0x00000008
-#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_v3d_top_sw_init_SHIFT 3
-#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_v3d_top_sw_init_DEFAULT 0x00000001
-
-/* SUN_TOP_CTRL :: SW_INIT_1_STATUS :: vice21_sw_init [02:02] */
-#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_vice21_sw_init_MASK 0x00000004
-#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_vice21_sw_init_SHIFT 2
-#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_vice21_sw_init_DEFAULT 0x00000001
-
-/* SUN_TOP_CTRL :: SW_INIT_1_STATUS :: vice20_sw_init [01:01] */
-#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_vice20_sw_init_MASK 0x00000002
-#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_vice20_sw_init_SHIFT 1
-#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_vice20_sw_init_DEFAULT 0x00000001
-
-/* SUN_TOP_CTRL :: SW_INIT_1_STATUS :: sid_sw_init [00:00] */
-#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_sid_sw_init_MASK 0x00000001
-#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_sid_sw_init_SHIFT 0
-#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_sid_sw_init_DEFAULT 0x00000001
-
-/***************************************************************************
- *SEC_SW_INIT_1_MONITOR - Security software init 1 monitor
- ***************************************************************************/
-/* SUN_TOP_CTRL :: SEC_SW_INIT_1_MONITOR :: reserved0 [31:07] */
-#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_reserved0_MASK 0xffffff80
-#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_reserved0_SHIFT 7
-
-/* SUN_TOP_CTRL :: SEC_SW_INIT_1_MONITOR :: spare1_sw_init [06:06] */
-#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_spare1_sw_init_MASK 0x00000040
-#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_spare1_sw_init_SHIFT 6
-
-/* SUN_TOP_CTRL :: SEC_SW_INIT_1_MONITOR :: spare0_sw_init [05:05] */
-#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_spare0_sw_init_MASK 0x00000020
-#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_spare0_sw_init_SHIFT 5
-
-/* SUN_TOP_CTRL :: SEC_SW_INIT_1_MONITOR :: m2mc1_sw_init [04:04] */
-#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_m2mc1_sw_init_MASK 0x00000010
-#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_m2mc1_sw_init_SHIFT 4
-
-/* SUN_TOP_CTRL :: SEC_SW_INIT_1_MONITOR :: v3d_top_sw_init [03:03] */
-#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_v3d_top_sw_init_MASK 0x00000008
-#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_v3d_top_sw_init_SHIFT 3
-
-/* SUN_TOP_CTRL :: SEC_SW_INIT_1_MONITOR :: vice21_sw_init [02:02] */
-#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_vice21_sw_init_MASK 0x00000004
-#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_vice21_sw_init_SHIFT 2
-
-/* SUN_TOP_CTRL :: SEC_SW_INIT_1_MONITOR :: vice20_sw_init [01:01] */
-#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_vice20_sw_init_MASK 0x00000002
-#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_vice20_sw_init_SHIFT 1
-
-/* SUN_TOP_CTRL :: SEC_SW_INIT_1_MONITOR :: sid_sw_init [00:00] */
-#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_sid_sw_init_MASK 0x00000001
-#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_sid_sw_init_SHIFT 0
-
-/***************************************************************************
- *TEST_CONFIG_SW_INIT_1_MONITOR - Test configuration software init 1 monitor
- ***************************************************************************/
-/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_1_MONITOR :: reserved0 [31:07] */
-#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_reserved0_MASK 0xffffff80
-#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_reserved0_SHIFT 7
-
-/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_1_MONITOR :: spare1_sw_init [06:06] */
-#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_spare1_sw_init_MASK 0x00000040
-#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_spare1_sw_init_SHIFT 6
-
-/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_1_MONITOR :: spare0_sw_init [05:05] */
-#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_spare0_sw_init_MASK 0x00000020
-#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_spare0_sw_init_SHIFT 5
-
-/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_1_MONITOR :: m2mc1_sw_init [04:04] */
-#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_m2mc1_sw_init_MASK 0x00000010
-#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_m2mc1_sw_init_SHIFT 4
-
-/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_1_MONITOR :: v3d_top_sw_init [03:03] */
-#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_v3d_top_sw_init_MASK 0x00000008
-#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_v3d_top_sw_init_SHIFT 3
-
-/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_1_MONITOR :: vice21_sw_init [02:02] */
-#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_vice21_sw_init_MASK 0x00000004
-#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_vice21_sw_init_SHIFT 2
-
-/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_1_MONITOR :: vice20_sw_init [01:01] */
-#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_vice20_sw_init_MASK 0x00000002
-#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_vice20_sw_init_SHIFT 1
-
-/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_1_MONITOR :: sid_sw_init [00:00] */
-#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_sid_sw_init_MASK 0x00000001
-#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_sid_sw_init_SHIFT 0
-
-/***************************************************************************
- *FINAL_SW_INIT_1_MONITOR - Final software init 1 monitor
- ***************************************************************************/
-/* SUN_TOP_CTRL :: FINAL_SW_INIT_1_MONITOR :: reserved0 [31:07] */
-#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_reserved0_MASK 0xffffff80
-#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_reserved0_SHIFT 7
-
-/* SUN_TOP_CTRL :: FINAL_SW_INIT_1_MONITOR :: spare1_sw_init [06:06] */
-#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_spare1_sw_init_MASK 0x00000040
-#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_spare1_sw_init_SHIFT 6
-
-/* SUN_TOP_CTRL :: FINAL_SW_INIT_1_MONITOR :: spare0_sw_init [05:05] */
-#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_spare0_sw_init_MASK 0x00000020
-#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_spare0_sw_init_SHIFT 5
-
-/* SUN_TOP_CTRL :: FINAL_SW_INIT_1_MONITOR :: m2mc1_sw_init [04:04] */
-#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_m2mc1_sw_init_MASK 0x00000010
-#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_m2mc1_sw_init_SHIFT 4
-
-/* SUN_TOP_CTRL :: FINAL_SW_INIT_1_MONITOR :: v3d_top_sw_init [03:03] */
-#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_v3d_top_sw_init_MASK 0x00000008
-#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_v3d_top_sw_init_SHIFT 3
-
-/* SUN_TOP_CTRL :: FINAL_SW_INIT_1_MONITOR :: vice21_sw_init [02:02] */
-#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_vice21_sw_init_MASK 0x00000004
-#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_vice21_sw_init_SHIFT 2
-
-/* SUN_TOP_CTRL :: FINAL_SW_INIT_1_MONITOR :: vice20_sw_init [01:01] */
-#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_vice20_sw_init_MASK 0x00000002
-#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_vice20_sw_init_SHIFT 1
-
-/* SUN_TOP_CTRL :: FINAL_SW_INIT_1_MONITOR :: sid_sw_init [00:00] */
-#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_sid_sw_init_MASK 0x00000001
-#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_sid_sw_init_SHIFT 0
-
-/***************************************************************************
- *SW_INIT_ONE_SHOT_TRIGGER - Software init one-shot trigger
- ***************************************************************************/
-/* SUN_TOP_CTRL :: SW_INIT_ONE_SHOT_TRIGGER :: reserved0 [31:02] */
-#define BCHP_SUN_TOP_CTRL_SW_INIT_ONE_SHOT_TRIGGER_reserved0_MASK 0xfffffffc
-#define BCHP_SUN_TOP_CTRL_SW_INIT_ONE_SHOT_TRIGGER_reserved0_SHIFT 2
-
-/* SUN_TOP_CTRL :: SW_INIT_ONE_SHOT_TRIGGER :: trigger_one_shot_1 [01:01] */
-#define BCHP_SUN_TOP_CTRL_SW_INIT_ONE_SHOT_TRIGGER_trigger_one_shot_1_MASK 0x00000002
-#define BCHP_SUN_TOP_CTRL_SW_INIT_ONE_SHOT_TRIGGER_trigger_one_shot_1_SHIFT 1
-#define BCHP_SUN_TOP_CTRL_SW_INIT_ONE_SHOT_TRIGGER_trigger_one_shot_1_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: SW_INIT_ONE_SHOT_TRIGGER :: trigger_one_shot_0 [00:00] */
-#define BCHP_SUN_TOP_CTRL_SW_INIT_ONE_SHOT_TRIGGER_trigger_one_shot_0_MASK 0x00000001
-#define BCHP_SUN_TOP_CTRL_SW_INIT_ONE_SHOT_TRIGGER_trigger_one_shot_0_SHIFT 0
-#define BCHP_SUN_TOP_CTRL_SW_INIT_ONE_SHOT_TRIGGER_trigger_one_shot_0_DEFAULT 0x00000000
-
-/***************************************************************************
- *ONE_SHOT_0_SW_INIT_WIDTH - One-shot 0 width
- ***************************************************************************/
-/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_WIDTH :: reserved0 [31:28] */
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_WIDTH_reserved0_MASK 0xf0000000
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_WIDTH_reserved0_SHIFT 28
-
-/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_WIDTH :: one_shot_0_width [27:00] */
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_WIDTH_one_shot_0_width_MASK 0x0fffffff
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_WIDTH_one_shot_0_width_SHIFT 0
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_WIDTH_one_shot_0_width_DEFAULT 0x00000000
-
-/***************************************************************************
- *ONE_SHOT_0_SW_INIT_0_MASK - One-shot 0 mask for software init 0
- ***************************************************************************/
-/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: rfm_sw_init [31:31] */
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_rfm_sw_init_MASK 0x80000000
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_rfm_sw_init_SHIFT 31
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_rfm_sw_init_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: not_used_sw_init_30 [30:30] */
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_30_MASK 0x40000000
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_30_SHIFT 30
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_30_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: sata_sw_init [29:29] */
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_sata_sw_init_MASK 0x20000000
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_sata_sw_init_SHIFT 29
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_sata_sw_init_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: not_used_sw_init_28 [28:28] */
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_28_MASK 0x10000000
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_28_SHIFT 28
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_28_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: not_used_sw_init_27 [27:27] */
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_27_MASK 0x08000000
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_27_SHIFT 27
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_27_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: not_used_sw_init_26 [26:26] */
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_26_MASK 0x04000000
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_26_SHIFT 26
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_26_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: not_used_sw_init_25 [25:25] */
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_25_MASK 0x02000000
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_25_SHIFT 25
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_25_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: usb0_sw_init [24:24] */
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_usb0_sw_init_MASK 0x01000000
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_usb0_sw_init_SHIFT 24
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_usb0_sw_init_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: not_used_sw_init_23 [23:23] */
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_23_MASK 0x00800000
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_23_SHIFT 23
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_23_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: ddr1_sw_init [22:22] */
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_ddr1_sw_init_MASK 0x00400000
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_ddr1_sw_init_SHIFT 22
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_ddr1_sw_init_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: ddr0_sw_init [21:21] */
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_ddr0_sw_init_MASK 0x00200000
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_ddr0_sw_init_SHIFT 21
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_ddr0_sw_init_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: memc1_sw_init [20:20] */
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_memc1_sw_init_MASK 0x00100000
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_memc1_sw_init_SHIFT 20
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_memc1_sw_init_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: memc0_sw_init [19:19] */
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_memc0_sw_init_MASK 0x00080000
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_memc0_sw_init_SHIFT 19
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_memc0_sw_init_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: xpt_sw_init [18:18] */
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_xpt_sw_init_MASK 0x00040000
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_xpt_sw_init_SHIFT 18
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_xpt_sw_init_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: raaga1_sw_init [17:17] */
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_raaga1_sw_init_MASK 0x00020000
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_raaga1_sw_init_SHIFT 17
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_raaga1_sw_init_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: raaga0_sw_init [16:16] */
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_raaga0_sw_init_MASK 0x00010000
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_raaga0_sw_init_SHIFT 16
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_raaga0_sw_init_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: aio_sw_init [15:15] */
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_aio_sw_init_MASK 0x00008000
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_aio_sw_init_SHIFT 15
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_aio_sw_init_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: gfx_sw_init [14:14] */
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_gfx_sw_init_MASK 0x00004000
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_gfx_sw_init_SHIFT 14
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_gfx_sw_init_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: avd1_sw_init [13:13] */
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_avd1_sw_init_MASK 0x00002000
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_avd1_sw_init_SHIFT 13
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_avd1_sw_init_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: hvd0_sw_init [12:12] */
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_hvd0_sw_init_MASK 0x00001000
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_hvd0_sw_init_SHIFT 12
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_hvd0_sw_init_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: dvp_hr_sw_init [11:11] */
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_dvp_hr_sw_init_MASK 0x00000800
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_dvp_hr_sw_init_SHIFT 11
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_dvp_hr_sw_init_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: dvp_ht_sw_init [10:10] */
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_dvp_ht_sw_init_MASK 0x00000400
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_dvp_ht_sw_init_SHIFT 10
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_dvp_ht_sw_init_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: vec_sw_init [09:09] */
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_vec_sw_init_MASK 0x00000200
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_vec_sw_init_SHIFT 9
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_vec_sw_init_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: bvn_sw_init [08:08] */
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_bvn_sw_init_MASK 0x00000100
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_bvn_sw_init_SHIFT 8
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_bvn_sw_init_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: not_used_sw_init_7 [07:07] */
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_7_MASK 0x00000080
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_7_SHIFT 7
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_7_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: ebi_sw_init [06:06] */
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_ebi_sw_init_MASK 0x00000040
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_ebi_sw_init_SHIFT 6
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_ebi_sw_init_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: not_used_sw_init_5 [05:05] */
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_5_MASK 0x00000020
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_5_SHIFT 5
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_5_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: not_used_sw_init_4 [04:04] */
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_4_MASK 0x00000010
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_4_SHIFT 4
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_4_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: not_used_sw_init_3 [03:03] */
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_3_MASK 0x00000008
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_3_SHIFT 3
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_3_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: ext_sys_sw_init [02:02] */
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_ext_sys_sw_init_MASK 0x00000004
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_ext_sys_sw_init_SHIFT 2
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_ext_sys_sw_init_DEFAULT 0x00000001
-
-/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: cpu_sw_init [01:01] */
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_cpu_sw_init_MASK 0x00000002
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_cpu_sw_init_SHIFT 1
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_cpu_sw_init_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: sys_ctrl_sw_init [00:00] */
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_sys_ctrl_sw_init_MASK 0x00000001
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_sys_ctrl_sw_init_SHIFT 0
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_sys_ctrl_sw_init_DEFAULT 0x00000000
-
-/***************************************************************************
- *ONE_SHOT_0_SW_INIT_1_MASK - One-shot 0 mask for software init 1
- ***************************************************************************/
-/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_1_MASK :: reserved0 [31:07] */
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_reserved0_MASK 0xffffff80
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_reserved0_SHIFT 7
-
-/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_1_MASK :: spare1_sw_init [06:06] */
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_spare1_sw_init_MASK 0x00000040
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_spare1_sw_init_SHIFT 6
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_spare1_sw_init_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_1_MASK :: spare0_sw_init [05:05] */
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_spare0_sw_init_MASK 0x00000020
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_spare0_sw_init_SHIFT 5
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_spare0_sw_init_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_1_MASK :: m2mc1_sw_init [04:04] */
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_m2mc1_sw_init_MASK 0x00000010
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_m2mc1_sw_init_SHIFT 4
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_m2mc1_sw_init_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_1_MASK :: v3d_top_sw_init [03:03] */
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_v3d_top_sw_init_MASK 0x00000008
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_v3d_top_sw_init_SHIFT 3
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_v3d_top_sw_init_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_1_MASK :: vice21_sw_init [02:02] */
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_vice21_sw_init_MASK 0x00000004
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_vice21_sw_init_SHIFT 2
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_vice21_sw_init_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_1_MASK :: vice20_sw_init [01:01] */
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_vice20_sw_init_MASK 0x00000002
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_vice20_sw_init_SHIFT 1
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_vice20_sw_init_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_1_MASK :: sid_sw_init [00:00] */
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_sid_sw_init_MASK 0x00000001
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_sid_sw_init_SHIFT 0
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_sid_sw_init_DEFAULT 0x00000000
-
-/***************************************************************************
- *ONE_SHOT_1_SW_INIT_WIDTH - One-shot 1 width
- ***************************************************************************/
-/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_WIDTH :: reserved0 [31:28] */
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_WIDTH_reserved0_MASK 0xf0000000
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_WIDTH_reserved0_SHIFT 28
-
-/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_WIDTH :: one_shot_1_width [27:00] */
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_WIDTH_one_shot_1_width_MASK 0x0fffffff
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_WIDTH_one_shot_1_width_SHIFT 0
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_WIDTH_one_shot_1_width_DEFAULT 0x00000000
-
-/***************************************************************************
- *ONE_SHOT_1_SW_INIT_0_MASK - One-shot 1 mask for software init 0
- ***************************************************************************/
-/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: rfm_sw_init [31:31] */
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_rfm_sw_init_MASK 0x80000000
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_rfm_sw_init_SHIFT 31
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_rfm_sw_init_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: not_used_sw_init_30 [30:30] */
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_30_MASK 0x40000000
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_30_SHIFT 30
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_30_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: sata_sw_init [29:29] */
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_sata_sw_init_MASK 0x20000000
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_sata_sw_init_SHIFT 29
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_sata_sw_init_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: not_used_sw_init_28 [28:28] */
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_28_MASK 0x10000000
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_28_SHIFT 28
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_28_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: not_used_sw_init_27 [27:27] */
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_27_MASK 0x08000000
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_27_SHIFT 27
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_27_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: not_used_sw_init_26 [26:26] */
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_26_MASK 0x04000000
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_26_SHIFT 26
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_26_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: not_used_sw_init_25 [25:25] */
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_25_MASK 0x02000000
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_25_SHIFT 25
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_25_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: usb0_sw_init [24:24] */
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_usb0_sw_init_MASK 0x01000000
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_usb0_sw_init_SHIFT 24
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_usb0_sw_init_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: not_used_sw_init_23 [23:23] */
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_23_MASK 0x00800000
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_23_SHIFT 23
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_23_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: ddr1_sw_init [22:22] */
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_ddr1_sw_init_MASK 0x00400000
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_ddr1_sw_init_SHIFT 22
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_ddr1_sw_init_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: ddr0_sw_init [21:21] */
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_ddr0_sw_init_MASK 0x00200000
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_ddr0_sw_init_SHIFT 21
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_ddr0_sw_init_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: memc1_sw_init [20:20] */
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_memc1_sw_init_MASK 0x00100000
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_memc1_sw_init_SHIFT 20
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_memc1_sw_init_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: memc0_sw_init [19:19] */
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_memc0_sw_init_MASK 0x00080000
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_memc0_sw_init_SHIFT 19
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_memc0_sw_init_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: xpt_sw_init [18:18] */
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_xpt_sw_init_MASK 0x00040000
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_xpt_sw_init_SHIFT 18
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_xpt_sw_init_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: raaga1_sw_init [17:17] */
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_raaga1_sw_init_MASK 0x00020000
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_raaga1_sw_init_SHIFT 17
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_raaga1_sw_init_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: raaga0_sw_init [16:16] */
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_raaga0_sw_init_MASK 0x00010000
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_raaga0_sw_init_SHIFT 16
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_raaga0_sw_init_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: aio_sw_init [15:15] */
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_aio_sw_init_MASK 0x00008000
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_aio_sw_init_SHIFT 15
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_aio_sw_init_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: gfx_sw_init [14:14] */
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_gfx_sw_init_MASK 0x00004000
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_gfx_sw_init_SHIFT 14
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_gfx_sw_init_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: avd1_sw_init [13:13] */
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_avd1_sw_init_MASK 0x00002000
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_avd1_sw_init_SHIFT 13
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_avd1_sw_init_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: hvd0_sw_init [12:12] */
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_hvd0_sw_init_MASK 0x00001000
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_hvd0_sw_init_SHIFT 12
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_hvd0_sw_init_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: dvp_hr_sw_init [11:11] */
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_dvp_hr_sw_init_MASK 0x00000800
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_dvp_hr_sw_init_SHIFT 11
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_dvp_hr_sw_init_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: dvp_ht_sw_init [10:10] */
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_dvp_ht_sw_init_MASK 0x00000400
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_dvp_ht_sw_init_SHIFT 10
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_dvp_ht_sw_init_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: vec_sw_init [09:09] */
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_vec_sw_init_MASK 0x00000200
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_vec_sw_init_SHIFT 9
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_vec_sw_init_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: bvn_sw_init [08:08] */
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_bvn_sw_init_MASK 0x00000100
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_bvn_sw_init_SHIFT 8
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_bvn_sw_init_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: not_used_sw_init_7 [07:07] */
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_7_MASK 0x00000080
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_7_SHIFT 7
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_7_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: ebi_sw_init [06:06] */
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_ebi_sw_init_MASK 0x00000040
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_ebi_sw_init_SHIFT 6
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_ebi_sw_init_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: not_used_sw_init_5 [05:05] */
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_5_MASK 0x00000020
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_5_SHIFT 5
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_5_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: not_used_sw_init_4 [04:04] */
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_4_MASK 0x00000010
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_4_SHIFT 4
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_4_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: not_used_sw_init_3 [03:03] */
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_3_MASK 0x00000008
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_3_SHIFT 3
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_3_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: ext_sys_sw_init [02:02] */
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_ext_sys_sw_init_MASK 0x00000004
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_ext_sys_sw_init_SHIFT 2
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_ext_sys_sw_init_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: cpu_sw_init [01:01] */
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_cpu_sw_init_MASK 0x00000002
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_cpu_sw_init_SHIFT 1
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_cpu_sw_init_DEFAULT 0x00000001
-
-/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: sys_ctrl_sw_init [00:00] */
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_sys_ctrl_sw_init_MASK 0x00000001
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_sys_ctrl_sw_init_SHIFT 0
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_sys_ctrl_sw_init_DEFAULT 0x00000000
-
-/***************************************************************************
- *ONE_SHOT_1_SW_INIT_1_MASK - One-shot 1 mask for software init 1
- ***************************************************************************/
-/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_1_MASK :: reserved0 [31:07] */
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_reserved0_MASK 0xffffff80
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_reserved0_SHIFT 7
-
-/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_1_MASK :: spare1_sw_init [06:06] */
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_spare1_sw_init_MASK 0x00000040
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_spare1_sw_init_SHIFT 6
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_spare1_sw_init_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_1_MASK :: spare0_sw_init [05:05] */
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_spare0_sw_init_MASK 0x00000020
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_spare0_sw_init_SHIFT 5
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_spare0_sw_init_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_1_MASK :: m2mc1_sw_init [04:04] */
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_m2mc1_sw_init_MASK 0x00000010
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_m2mc1_sw_init_SHIFT 4
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_m2mc1_sw_init_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_1_MASK :: v3d_top_sw_init [03:03] */
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_v3d_top_sw_init_MASK 0x00000008
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_v3d_top_sw_init_SHIFT 3
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_v3d_top_sw_init_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_1_MASK :: vice21_sw_init [02:02] */
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_vice21_sw_init_MASK 0x00000004
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_vice21_sw_init_SHIFT 2
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_vice21_sw_init_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_1_MASK :: vice20_sw_init [01:01] */
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_vice20_sw_init_MASK 0x00000002
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_vice20_sw_init_SHIFT 1
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_vice20_sw_init_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_1_MASK :: sid_sw_init [00:00] */
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_sid_sw_init_MASK 0x00000001
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_sid_sw_init_SHIFT 0
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_sid_sw_init_DEFAULT 0x00000000
-
-/***************************************************************************
- *UNCLEARED_SCRATCH - Scratch register
- ***************************************************************************/
-/* SUN_TOP_CTRL :: UNCLEARED_SCRATCH :: uncleared_scratch [31:00] */
-#define BCHP_SUN_TOP_CTRL_UNCLEARED_SCRATCH_uncleared_scratch_MASK 0xffffffff
-#define BCHP_SUN_TOP_CTRL_UNCLEARED_SCRATCH_uncleared_scratch_SHIFT 0
-#define BCHP_SUN_TOP_CTRL_UNCLEARED_SCRATCH_uncleared_scratch_DEFAULT 0x00000000
-
-/***************************************************************************
- *SPARE_CTRL - Spare control bits reserved for future use
- ***************************************************************************/
-/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_31 [31:31] */
-#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_31_MASK 0x80000000
-#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_31_SHIFT 31
-#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_31_DEFAULT 0x00000001
-
-/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_30 [30:30] */
-#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_30_MASK 0x40000000
-#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_30_SHIFT 30
-#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_30_DEFAULT 0x00000001
-
-/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_29 [29:29] */
-#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_29_MASK 0x20000000
-#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_29_SHIFT 29
-#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_29_DEFAULT 0x00000001
-
-/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_28 [28:28] */
-#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_28_MASK 0x10000000
-#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_28_SHIFT 28
-#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_28_DEFAULT 0x00000001
-
-/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_27 [27:27] */
-#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_27_MASK 0x08000000
-#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_27_SHIFT 27
-#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_27_DEFAULT 0x00000001
-
-/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_26 [26:26] */
-#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_26_MASK 0x04000000
-#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_26_SHIFT 26
-#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_26_DEFAULT 0x00000001
-
-/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_25 [25:25] */
-#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_25_MASK 0x02000000
-#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_25_SHIFT 25
-#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_25_DEFAULT 0x00000001
-
-/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_24 [24:24] */
-#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_24_MASK 0x01000000
-#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_24_SHIFT 24
-#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_24_DEFAULT 0x00000001
-
-/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_23 [23:23] */
-#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_23_MASK 0x00800000
-#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_23_SHIFT 23
-#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_23_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_22 [22:22] */
-#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_22_MASK 0x00400000
-#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_22_SHIFT 22
-#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_22_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_21 [21:21] */
-#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_21_MASK 0x00200000
-#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_21_SHIFT 21
-#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_21_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_20 [20:20] */
-#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_20_MASK 0x00100000
-#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_20_SHIFT 20
-#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_20_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_19 [19:19] */
-#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_19_MASK 0x00080000
-#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_19_SHIFT 19
-#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_19_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_18 [18:18] */
-#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_18_MASK 0x00040000
-#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_18_SHIFT 18
-#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_18_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_17 [17:17] */
-#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_17_MASK 0x00020000
-#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_17_SHIFT 17
-#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_17_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_16 [16:16] */
-#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_16_MASK 0x00010000
-#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_16_SHIFT 16
-#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_16_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_15 [15:15] */
-#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_15_MASK 0x00008000
-#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_15_SHIFT 15
-#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_15_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_14 [14:14] */
-#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_14_MASK 0x00004000
-#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_14_SHIFT 14
-#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_14_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_13 [13:13] */
-#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_13_MASK 0x00002000
-#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_13_SHIFT 13
-#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_13_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_12 [12:12] */
-#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_12_MASK 0x00001000
-#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_12_SHIFT 12
-#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_12_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_11 [11:11] */
-#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_11_MASK 0x00000800
-#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_11_SHIFT 11
-#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_11_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_10 [10:10] */
-#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_10_MASK 0x00000400
-#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_10_SHIFT 10
-#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_10_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_09 [09:09] */
-#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_09_MASK 0x00000200
-#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_09_SHIFT 9
-#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_09_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_08 [08:08] */
-#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_08_MASK 0x00000100
-#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_08_SHIFT 8
-#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_08_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_07 [07:07] */
-#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_07_MASK 0x00000080
-#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_07_SHIFT 7
-#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_07_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_06 [06:06] */
-#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_06_MASK 0x00000040
-#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_06_SHIFT 6
-#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_06_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_05 [05:05] */
-#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_05_MASK 0x00000020
-#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_05_SHIFT 5
-#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_05_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_04 [04:04] */
-#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_04_MASK 0x00000010
-#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_04_SHIFT 4
-#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_04_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_03 [03:03] */
-#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_03_MASK 0x00000008
-#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_03_SHIFT 3
-#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_03_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_02 [02:02] */
-#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_02_MASK 0x00000004
-#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_02_SHIFT 2
-#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_02_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_01 [01:01] */
-#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_01_MASK 0x00000002
-#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_01_SHIFT 1
-#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_01_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_00 [00:00] */
-#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_00_MASK 0x00000001
-#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_00_SHIFT 0
-#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_00_DEFAULT 0x00000000
-
-/***************************************************************************
- *TEST_PORT_CTRL - Test port control
- ***************************************************************************/
-/* SUN_TOP_CTRL :: TEST_PORT_CTRL :: sys_ctrl_local_tp_out_sel [31:28] */
-#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sys_ctrl_local_tp_out_sel_MASK 0xf0000000
-#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sys_ctrl_local_tp_out_sel_SHIFT 28
-#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sys_ctrl_local_tp_out_sel_DEFAULT 0x00000000
-#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sys_ctrl_local_tp_out_sel_SEMAPHORE_0 0
-#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sys_ctrl_local_tp_out_sel_SEMAPHORE_1 1
-#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sys_ctrl_local_tp_out_sel_UNUSED_02 2
-#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sys_ctrl_local_tp_out_sel_MISC_TEST 3
-#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sys_ctrl_local_tp_out_sel_SSP 4
-#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sys_ctrl_local_tp_out_sel_TP_OUT_POKE_REG 5
-#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sys_ctrl_local_tp_out_sel_TP_IN 6
-#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sys_ctrl_local_tp_out_sel_UNUSED_07 7
-#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sys_ctrl_local_tp_out_sel_UNUSED_08 8
-#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sys_ctrl_local_tp_out_sel_UNUSED_09 9
-#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sys_ctrl_local_tp_out_sel_UNUSED_10 10
-#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sys_ctrl_local_tp_out_sel_UNUSED_11 11
-#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sys_ctrl_local_tp_out_sel_UPG_TP_OUT 12
-#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sys_ctrl_local_tp_out_sel_AVS_TP_OUT 13
-#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sys_ctrl_local_tp_out_sel_ICID_TP_OUT 14
-#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sys_ctrl_local_tp_out_sel_TOP_AUX_TP_OUT 15
-
-/* SUN_TOP_CTRL :: TEST_PORT_CTRL :: reserved0 [27:10] */
-#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_reserved0_MASK 0x0ffffc00
-#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_reserved0_SHIFT 10
-
-/* SUN_TOP_CTRL :: TEST_PORT_CTRL :: tp_in_source_select [09:09] */
-#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_tp_in_source_select_MASK 0x00000200
-#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_tp_in_source_select_SHIFT 9
-#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_tp_in_source_select_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: TEST_PORT_CTRL :: tp_select [08:07] */
-#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_tp_select_MASK 0x00000180
-#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_tp_select_SHIFT 7
-#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_tp_select_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: TEST_PORT_CTRL :: encoded_tp_enable [06:00] */
-#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_MASK 0x0000007f
-#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_SHIFT 0
-#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_DEFAULT 0x0000007f
-#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_GENET 0
-#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_SCPU 1
-#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_CPU 2
-#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_SATA 3
-#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_DS_TOP 4
-#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_US_TOP 5
-#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_SYS 16
-#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_CLK 17
-#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_AON 18
-#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_HIF 20
-#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_BSP 21
-#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_VEC 25
-#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_HVD0 27
-#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_AVD1 28
-#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_AIO 30
-#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_RAAGA0 31
-#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_RAAGA1 32
-#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_XPT 33
-#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_MEMC0 35
-#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_MEMC1 36
-#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_PCIE 44
-#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_USB0 45
-#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_MOCA 47
-#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_RFM 49
-#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_GFAP 50
-#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_UNIMAC_MBDMA 51
-#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_V3D_TOP 54
-
-/***************************************************************************
- *TEST_PORT_OUT_PEEK - Testport peek register
- ***************************************************************************/
-/* SUN_TOP_CTRL :: TEST_PORT_OUT_PEEK :: test_port_out_peek_value [31:00] */
-#define BCHP_SUN_TOP_CTRL_TEST_PORT_OUT_PEEK_test_port_out_peek_value_MASK 0xffffffff
-#define BCHP_SUN_TOP_CTRL_TEST_PORT_OUT_PEEK_test_port_out_peek_value_SHIFT 0
-
-/***************************************************************************
- *TEST_PORT_OUT_POKE - Testport poke register
- ***************************************************************************/
-/* SUN_TOP_CTRL :: TEST_PORT_OUT_POKE :: test_port_out_poke_value [31:00] */
-#define BCHP_SUN_TOP_CTRL_TEST_PORT_OUT_POKE_test_port_out_poke_value_MASK 0xffffffff
-#define BCHP_SUN_TOP_CTRL_TEST_PORT_OUT_POKE_test_port_out_poke_value_SHIFT 0
-#define BCHP_SUN_TOP_CTRL_TEST_PORT_OUT_POKE_test_port_out_poke_value_DEFAULT 0x00000000
-
-/***************************************************************************
- *TEST_PORT_IN_PEEK - Testport peek register
- ***************************************************************************/
-/* SUN_TOP_CTRL :: TEST_PORT_IN_PEEK :: test_port_in_peek_value [31:00] */
-#define BCHP_SUN_TOP_CTRL_TEST_PORT_IN_PEEK_test_port_in_peek_value_MASK 0xffffffff
-#define BCHP_SUN_TOP_CTRL_TEST_PORT_IN_PEEK_test_port_in_peek_value_SHIFT 0
-
-/***************************************************************************
- *TEST_PORT_IN_POKE - Testport poke register
- ***************************************************************************/
-/* SUN_TOP_CTRL :: TEST_PORT_IN_POKE :: test_port_in_poke_value [31:00] */
-#define BCHP_SUN_TOP_CTRL_TEST_PORT_IN_POKE_test_port_in_poke_value_MASK 0xffffffff
-#define BCHP_SUN_TOP_CTRL_TEST_PORT_IN_POKE_test_port_in_poke_value_SHIFT 0
-#define BCHP_SUN_TOP_CTRL_TEST_PORT_IN_POKE_test_port_in_poke_value_DEFAULT 0x00000000
-
-/***************************************************************************
- *EJTAG_INPUT_EN - EJTAG input bus enables
- ***************************************************************************/
-/* SUN_TOP_CTRL :: EJTAG_INPUT_EN :: reserved0 [31:09] */
-#define BCHP_SUN_TOP_CTRL_EJTAG_INPUT_EN_reserved0_MASK 0xfffffe00
-#define BCHP_SUN_TOP_CTRL_EJTAG_INPUT_EN_reserved0_SHIFT 9
-
-/* SUN_TOP_CTRL :: EJTAG_INPUT_EN :: ejtag_input_enable [08:00] */
-#define BCHP_SUN_TOP_CTRL_EJTAG_INPUT_EN_ejtag_input_enable_MASK 0x000001ff
-#define BCHP_SUN_TOP_CTRL_EJTAG_INPUT_EN_ejtag_input_enable_SHIFT 0
-#define BCHP_SUN_TOP_CTRL_EJTAG_INPUT_EN_ejtag_input_enable_DEFAULT 0x00000002
-#define BCHP_SUN_TOP_CTRL_EJTAG_INPUT_EN_ejtag_input_enable_DO_NOT_USE_CPU_ONE_HOT 1
-#define BCHP_SUN_TOP_CTRL_EJTAG_INPUT_EN_ejtag_input_enable_HOST_CPU_ONE_HOT 2
-#define BCHP_SUN_TOP_CTRL_EJTAG_INPUT_EN_ejtag_input_enable_VICE20_ARC0_CPU_ONE_HOT 4
-#define BCHP_SUN_TOP_CTRL_EJTAG_INPUT_EN_ejtag_input_enable_VICE20_ARC1_CPU_ONE_HOT 8
-#define BCHP_SUN_TOP_CTRL_EJTAG_INPUT_EN_ejtag_input_enable_VICE21_ARC0_CPU_ONE_HOT 16
-#define BCHP_SUN_TOP_CTRL_EJTAG_INPUT_EN_ejtag_input_enable_VICE21_ARC1_CPU_ONE_HOT 32
-#define BCHP_SUN_TOP_CTRL_EJTAG_INPUT_EN_ejtag_input_enable_AVS_CPU_ONE_HOT 64
-#define BCHP_SUN_TOP_CTRL_EJTAG_INPUT_EN_ejtag_input_enable_SCPU_CPU_ONE_HOT 128
-#define BCHP_SUN_TOP_CTRL_EJTAG_INPUT_EN_ejtag_input_enable_BSP_CPU_ONE_HOT 256
-
-/***************************************************************************
- *EJTAG_OUTPUT_SEL - EJTAG output select
- ***************************************************************************/
-/* SUN_TOP_CTRL :: EJTAG_OUTPUT_SEL :: reserved0 [31:04] */
-#define BCHP_SUN_TOP_CTRL_EJTAG_OUTPUT_SEL_reserved0_MASK 0xfffffff0
-#define BCHP_SUN_TOP_CTRL_EJTAG_OUTPUT_SEL_reserved0_SHIFT 4
-
-/* SUN_TOP_CTRL :: EJTAG_OUTPUT_SEL :: ejtag_output_sel [03:00] */
-#define BCHP_SUN_TOP_CTRL_EJTAG_OUTPUT_SEL_ejtag_output_sel_MASK 0x0000000f
-#define BCHP_SUN_TOP_CTRL_EJTAG_OUTPUT_SEL_ejtag_output_sel_SHIFT 0
-#define BCHP_SUN_TOP_CTRL_EJTAG_OUTPUT_SEL_ejtag_output_sel_DEFAULT 0x00000001
-#define BCHP_SUN_TOP_CTRL_EJTAG_OUTPUT_SEL_ejtag_output_sel_DO_NOT_USE_CPU 0
-#define BCHP_SUN_TOP_CTRL_EJTAG_OUTPUT_SEL_ejtag_output_sel_HOST_CPU 1
-#define BCHP_SUN_TOP_CTRL_EJTAG_OUTPUT_SEL_ejtag_output_sel_VICE20_ARC0_CPU 2
-#define BCHP_SUN_TOP_CTRL_EJTAG_OUTPUT_SEL_ejtag_output_sel_VICE20_ARC1_CPU 3
-#define BCHP_SUN_TOP_CTRL_EJTAG_OUTPUT_SEL_ejtag_output_sel_VICE21_ARC0_CPU 4
-#define BCHP_SUN_TOP_CTRL_EJTAG_OUTPUT_SEL_ejtag_output_sel_VICE21_ARC1_CPU 5
-#define BCHP_SUN_TOP_CTRL_EJTAG_OUTPUT_SEL_ejtag_output_sel_AVS_CPU 6
-#define BCHP_SUN_TOP_CTRL_EJTAG_OUTPUT_SEL_ejtag_output_sel_SCPU_CPU 7
-#define BCHP_SUN_TOP_CTRL_EJTAG_OUTPUT_SEL_ejtag_output_sel_BSP_CPU 8
-
-/***************************************************************************
- *UART_ROUTER_SEL - UART Router select
- ***************************************************************************/
-/* SUN_TOP_CTRL :: UART_ROUTER_SEL :: port_7_cpu_sel [31:28] */
-#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_7_cpu_sel_MASK 0xf0000000
-#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_7_cpu_sel_SHIFT 28
-#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_7_cpu_sel_DEFAULT 0x00000000
-#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_7_cpu_sel_NO_CPU 0
-#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_7_cpu_sel_AUDIO_FP0 1
-#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_7_cpu_sel_AUDIO_FP1 2
-#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_7_cpu_sel_AVD0_OL 3
-#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_7_cpu_sel_AVD0_IL 4
-#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_7_cpu_sel_AVD1_OL 5
-#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_7_cpu_sel_AVD1_IL 6
-#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_7_cpu_sel_SID 7
-#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_7_cpu_sel_VICE20_ARC0 8
-#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_7_cpu_sel_VICE20_ARC1 9
-#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_7_cpu_sel_VICE21_ARC0 10
-#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_7_cpu_sel_VICE21_ARC1 11
-#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_7_cpu_sel_AVS_TOP 12
-#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_7_cpu_sel_UNUSED_13 13
-#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_7_cpu_sel_UNUSED_14 14
-#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_7_cpu_sel_UNUSED_15 15
-
-/* SUN_TOP_CTRL :: UART_ROUTER_SEL :: port_6_cpu_sel [27:24] */
-#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_6_cpu_sel_MASK 0x0f000000
-#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_6_cpu_sel_SHIFT 24
-#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_6_cpu_sel_DEFAULT 0x00000000
-#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_6_cpu_sel_NO_CPU 0
-#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_6_cpu_sel_AUDIO_FP0 1
-#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_6_cpu_sel_AUDIO_FP1 2
-#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_6_cpu_sel_AVD0_OL 3
-#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_6_cpu_sel_AVD0_IL 4
-#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_6_cpu_sel_AVD1_OL 5
-#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_6_cpu_sel_AVD1_IL 6
-#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_6_cpu_sel_SID 7
-#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_6_cpu_sel_VICE20_ARC0 8
-#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_6_cpu_sel_VICE20_ARC1 9
-#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_6_cpu_sel_VICE21_ARC0 10
-#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_6_cpu_sel_VICE21_ARC1 11
-#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_6_cpu_sel_AVS_TOP 12
-#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_6_cpu_sel_UNUSED_13 13
-#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_6_cpu_sel_UNUSED_14 14
-#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_6_cpu_sel_UNUSED_15 15
-
-/* SUN_TOP_CTRL :: UART_ROUTER_SEL :: port_5_cpu_sel [23:20] */
-#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_5_cpu_sel_MASK 0x00f00000
-#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_5_cpu_sel_SHIFT 20
-#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_5_cpu_sel_DEFAULT 0x00000000
-#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_5_cpu_sel_NO_CPU 0
-#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_5_cpu_sel_AUDIO_FP0 1
-#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_5_cpu_sel_AUDIO_FP1 2
-#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_5_cpu_sel_AVD0_OL 3
-#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_5_cpu_sel_AVD0_IL 4
-#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_5_cpu_sel_AVD1_OL 5
-#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_5_cpu_sel_AVD1_IL 6
-#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_5_cpu_sel_SID 7
-#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_5_cpu_sel_VICE20_ARC0 8
-#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_5_cpu_sel_VICE20_ARC1 9
-#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_5_cpu_sel_VICE21_ARC0 10
-#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_5_cpu_sel_VICE21_ARC1 11
-#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_5_cpu_sel_AVS_TOP 12
-#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_5_cpu_sel_UNUSED_13 13
-#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_5_cpu_sel_UNUSED_14 14
-#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_5_cpu_sel_UNUSED_15 15
-
-/* SUN_TOP_CTRL :: UART_ROUTER_SEL :: port_4_cpu_sel [19:16] */
-#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_4_cpu_sel_MASK 0x000f0000
-#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_4_cpu_sel_SHIFT 16
-#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_4_cpu_sel_DEFAULT 0x00000000
-#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_4_cpu_sel_NO_CPU 0
-#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_4_cpu_sel_AUDIO_FP0 1
-#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_4_cpu_sel_AUDIO_FP1 2
-#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_4_cpu_sel_AVD0_OL 3
-#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_4_cpu_sel_AVD0_IL 4
-#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_4_cpu_sel_AVD1_OL 5
-#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_4_cpu_sel_AVD1_IL 6
-#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_4_cpu_sel_SID 7
-#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_4_cpu_sel_VICE20_ARC0 8
-#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_4_cpu_sel_VICE20_ARC1 9
-#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_4_cpu_sel_VICE21_ARC0 10
-#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_4_cpu_sel_VICE21_ARC1 11
-#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_4_cpu_sel_AVS_TOP 12
-#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_4_cpu_sel_UNUSED_13 13
-#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_4_cpu_sel_UNUSED_14 14
-#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_4_cpu_sel_UNUSED_15 15
-
-/* SUN_TOP_CTRL :: UART_ROUTER_SEL :: port_3_cpu_sel [15:12] */
-#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_3_cpu_sel_MASK 0x0000f000
-#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_3_cpu_sel_SHIFT 12
-#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_3_cpu_sel_DEFAULT 0x00000000
-#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_3_cpu_sel_NO_CPU 0
-#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_3_cpu_sel_AUDIO_FP0 1
-#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_3_cpu_sel_AUDIO_FP1 2
-#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_3_cpu_sel_AVD0_OL 3
-#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_3_cpu_sel_AVD0_IL 4
-#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_3_cpu_sel_AVD1_OL 5
-#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_3_cpu_sel_AVD1_IL 6
-#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_3_cpu_sel_SID 7
-#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_3_cpu_sel_VICE20_ARC0 8
-#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_3_cpu_sel_VICE20_ARC1 9
-#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_3_cpu_sel_VICE21_ARC0 10
-#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_3_cpu_sel_VICE21_ARC1 11
-#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_3_cpu_sel_AVS_TOP 12
-#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_3_cpu_sel_UNUSED_13 13
-#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_3_cpu_sel_UNUSED_14 14
-#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_3_cpu_sel_UNUSED_15 15
-
-/* SUN_TOP_CTRL :: UART_ROUTER_SEL :: port_2_cpu_sel [11:08] */
-#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_2_cpu_sel_MASK 0x00000f00
-#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_2_cpu_sel_SHIFT 8
-#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_2_cpu_sel_DEFAULT 0x00000000
-#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_2_cpu_sel_NO_CPU 0
-#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_2_cpu_sel_AUDIO_FP0 1
-#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_2_cpu_sel_AUDIO_FP1 2
-#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_2_cpu_sel_AVD0_OL 3
-#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_2_cpu_sel_AVD0_IL 4
-#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_2_cpu_sel_AVD1_OL 5
-#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_2_cpu_sel_AVD1_IL 6
-#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_2_cpu_sel_SID 7
-#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_2_cpu_sel_VICE20_ARC0 8
-#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_2_cpu_sel_VICE20_ARC1 9
-#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_2_cpu_sel_VICE21_ARC0 10
-#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_2_cpu_sel_VICE21_ARC1 11
-#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_2_cpu_sel_AVS_TOP 12
-#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_2_cpu_sel_UNUSED_13 13
-#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_2_cpu_sel_UNUSED_14 14
-#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_2_cpu_sel_UNUSED_15 15
-
-/* SUN_TOP_CTRL :: UART_ROUTER_SEL :: port_1_cpu_sel [07:04] */
-#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_1_cpu_sel_MASK 0x000000f0
-#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_1_cpu_sel_SHIFT 4
-#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_1_cpu_sel_DEFAULT 0x00000000
-#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_1_cpu_sel_NO_CPU 0
-#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_1_cpu_sel_AUDIO_FP0 1
-#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_1_cpu_sel_AUDIO_FP1 2
-#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_1_cpu_sel_AVD0_OL 3
-#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_1_cpu_sel_AVD0_IL 4
-#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_1_cpu_sel_AVD1_OL 5
-#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_1_cpu_sel_AVD1_IL 6
-#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_1_cpu_sel_SID 7
-#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_1_cpu_sel_VICE20_ARC0 8
-#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_1_cpu_sel_VICE20_ARC1 9
-#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_1_cpu_sel_VICE21_ARC0 10
-#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_1_cpu_sel_VICE21_ARC1 11
-#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_1_cpu_sel_AVS_TOP 12
-#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_1_cpu_sel_UNUSED_13 13
-#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_1_cpu_sel_UNUSED_14 14
-#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_1_cpu_sel_UNUSED_15 15
-
-/* SUN_TOP_CTRL :: UART_ROUTER_SEL :: port_0_cpu_sel [03:00] */
-#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_0_cpu_sel_MASK 0x0000000f
-#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_0_cpu_sel_SHIFT 0
-#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_0_cpu_sel_DEFAULT 0x00000000
-#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_0_cpu_sel_NO_CPU 0
-#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_0_cpu_sel_AUDIO_FP0 1
-#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_0_cpu_sel_AUDIO_FP1 2
-#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_0_cpu_sel_AVD0_OL 3
-#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_0_cpu_sel_AVD0_IL 4
-#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_0_cpu_sel_AVD1_OL 5
-#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_0_cpu_sel_AVD1_IL 6
-#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_0_cpu_sel_SID 7
-#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_0_cpu_sel_VICE20_ARC0 8
-#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_0_cpu_sel_VICE20_ARC1 9
-#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_0_cpu_sel_VICE21_ARC0 10
-#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_0_cpu_sel_VICE21_ARC1 11
-#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_0_cpu_sel_AVS_TOP 12
-#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_0_cpu_sel_UNUSED_13 13
-#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_0_cpu_sel_UNUSED_14 14
-#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_0_cpu_sel_UNUSED_15 15
-
-/***************************************************************************
- *VTRAP_CTRL - VTRAP Control
- ***************************************************************************/
-/* SUN_TOP_CTRL :: VTRAP_CTRL :: reserved0 [31:23] */
-#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_reserved0_MASK 0xff800000
-#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_reserved0_SHIFT 23
-
-/* SUN_TOP_CTRL :: VTRAP_CTRL :: vtrap_enable_max_1_threshold [22:22] */
-#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_enable_max_1_threshold_MASK 0x00400000
-#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_enable_max_1_threshold_SHIFT 22
-#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_enable_max_1_threshold_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: VTRAP_CTRL :: vtrap_enable_min_1_threshold [21:21] */
-#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_enable_min_1_threshold_MASK 0x00200000
-#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_enable_min_1_threshold_SHIFT 21
-#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_enable_min_1_threshold_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: VTRAP_CTRL :: vtrap_enable_min_0_threshold [20:20] */
-#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_enable_min_0_threshold_MASK 0x00100000
-#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_enable_min_0_threshold_SHIFT 20
-#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_enable_min_0_threshold_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: VTRAP_CTRL :: vtrap_enable_warning_1_threshold [19:19] */
-#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_enable_warning_1_threshold_MASK 0x00080000
-#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_enable_warning_1_threshold_SHIFT 19
-#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_enable_warning_1_threshold_DEFAULT 0x00000001
-
-/* SUN_TOP_CTRL :: VTRAP_CTRL :: vtrap_enable_warning_0_threshold [18:18] */
-#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_enable_warning_0_threshold_MASK 0x00040000
-#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_enable_warning_0_threshold_SHIFT 18
-#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_enable_warning_0_threshold_DEFAULT 0x00000001
-
-/* SUN_TOP_CTRL :: VTRAP_CTRL :: vtrap_vddcmon_test_trim_code [17:05] */
-#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_vddcmon_test_trim_code_MASK 0x0003ffe0
-#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_vddcmon_test_trim_code_SHIFT 5
-#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_vddcmon_test_trim_code_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: VTRAP_CTRL :: vtrap_threshold_warning_1_status_clear [04:04] */
-#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_threshold_warning_1_status_clear_MASK 0x00000010
-#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_threshold_warning_1_status_clear_SHIFT 4
-#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_threshold_warning_1_status_clear_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: VTRAP_CTRL :: vtrap_threshold_warning_0_status_clear [03:03] */
-#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_threshold_warning_0_status_clear_MASK 0x00000008
-#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_threshold_warning_0_status_clear_SHIFT 3
-#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_threshold_warning_0_status_clear_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: VTRAP_CTRL :: vtrap_threshold_min_1_status_clear [02:02] */
-#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_threshold_min_1_status_clear_MASK 0x00000004
-#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_threshold_min_1_status_clear_SHIFT 2
-#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_threshold_min_1_status_clear_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: VTRAP_CTRL :: vtrap_threshold_min_0_status_clear [01:01] */
-#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_threshold_min_0_status_clear_MASK 0x00000002
-#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_threshold_min_0_status_clear_SHIFT 1
-#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_threshold_min_0_status_clear_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: VTRAP_CTRL :: vtrap_threshold_max_1_status_clear [00:00] */
-#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_threshold_max_1_status_clear_MASK 0x00000001
-#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_threshold_max_1_status_clear_SHIFT 0
-#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_threshold_max_1_status_clear_DEFAULT 0x00000000
-
-/***************************************************************************
- *VTRAP_STATUS - VTRAP Status
- ***************************************************************************/
-/* SUN_TOP_CTRL :: VTRAP_STATUS :: reserved0 [31:05] */
-#define BCHP_SUN_TOP_CTRL_VTRAP_STATUS_reserved0_MASK 0xffffffe0
-#define BCHP_SUN_TOP_CTRL_VTRAP_STATUS_reserved0_SHIFT 5
-
-/* SUN_TOP_CTRL :: VTRAP_STATUS :: vtrap_threshold_warning_1_status [04:04] */
-#define BCHP_SUN_TOP_CTRL_VTRAP_STATUS_vtrap_threshold_warning_1_status_MASK 0x00000010
-#define BCHP_SUN_TOP_CTRL_VTRAP_STATUS_vtrap_threshold_warning_1_status_SHIFT 4
-#define BCHP_SUN_TOP_CTRL_VTRAP_STATUS_vtrap_threshold_warning_1_status_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: VTRAP_STATUS :: vtrap_threshold_warning_0_status [03:03] */
-#define BCHP_SUN_TOP_CTRL_VTRAP_STATUS_vtrap_threshold_warning_0_status_MASK 0x00000008
-#define BCHP_SUN_TOP_CTRL_VTRAP_STATUS_vtrap_threshold_warning_0_status_SHIFT 3
-#define BCHP_SUN_TOP_CTRL_VTRAP_STATUS_vtrap_threshold_warning_0_status_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: VTRAP_STATUS :: vtrap_threshold_min_1_status [02:02] */
-#define BCHP_SUN_TOP_CTRL_VTRAP_STATUS_vtrap_threshold_min_1_status_MASK 0x00000004
-#define BCHP_SUN_TOP_CTRL_VTRAP_STATUS_vtrap_threshold_min_1_status_SHIFT 2
-#define BCHP_SUN_TOP_CTRL_VTRAP_STATUS_vtrap_threshold_min_1_status_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: VTRAP_STATUS :: vtrap_threshold_min_0_status [01:01] */
-#define BCHP_SUN_TOP_CTRL_VTRAP_STATUS_vtrap_threshold_min_0_status_MASK 0x00000002
-#define BCHP_SUN_TOP_CTRL_VTRAP_STATUS_vtrap_threshold_min_0_status_SHIFT 1
-#define BCHP_SUN_TOP_CTRL_VTRAP_STATUS_vtrap_threshold_min_0_status_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: VTRAP_STATUS :: vtrap_threshold_max_1_status [00:00] */
-#define BCHP_SUN_TOP_CTRL_VTRAP_STATUS_vtrap_threshold_max_1_status_MASK 0x00000001
-#define BCHP_SUN_TOP_CTRL_VTRAP_STATUS_vtrap_threshold_max_1_status_SHIFT 0
-#define BCHP_SUN_TOP_CTRL_VTRAP_STATUS_vtrap_threshold_max_1_status_DEFAULT 0x00000000
-
-/***************************************************************************
- *SSP_CONFIG - Serial Slave Port configuration register
- ***************************************************************************/
-/* SUN_TOP_CTRL :: SSP_CONFIG :: reserved0 [31:11] */
-#define BCHP_SUN_TOP_CTRL_SSP_CONFIG_reserved0_MASK 0xfffff800
-#define BCHP_SUN_TOP_CTRL_SSP_CONFIG_reserved0_SHIFT 11
-
-/* SUN_TOP_CTRL :: SSP_CONFIG :: serial_adr_cfg [10:07] */
-#define BCHP_SUN_TOP_CTRL_SSP_CONFIG_serial_adr_cfg_MASK 0x00000780
-#define BCHP_SUN_TOP_CTRL_SSP_CONFIG_serial_adr_cfg_SHIFT 7
-#define BCHP_SUN_TOP_CTRL_SSP_CONFIG_serial_adr_cfg_DEFAULT 0x00000004
-
-/* SUN_TOP_CTRL :: SSP_CONFIG :: probe_mux_sel [06:03] */
-#define BCHP_SUN_TOP_CTRL_SSP_CONFIG_probe_mux_sel_MASK 0x00000078
-#define BCHP_SUN_TOP_CTRL_SSP_CONFIG_probe_mux_sel_SHIFT 3
-#define BCHP_SUN_TOP_CTRL_SSP_CONFIG_probe_mux_sel_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: SSP_CONFIG :: dly_disable [02:02] */
-#define BCHP_SUN_TOP_CTRL_SSP_CONFIG_dly_disable_MASK 0x00000004
-#define BCHP_SUN_TOP_CTRL_SSP_CONFIG_dly_disable_SHIFT 2
-#define BCHP_SUN_TOP_CTRL_SSP_CONFIG_dly_disable_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: SSP_CONFIG :: spi_mode [01:01] */
-#define BCHP_SUN_TOP_CTRL_SSP_CONFIG_spi_mode_MASK 0x00000002
-#define BCHP_SUN_TOP_CTRL_SSP_CONFIG_spi_mode_SHIFT 1
-
-/* SUN_TOP_CTRL :: SSP_CONFIG :: ssp_module_enable [00:00] */
-#define BCHP_SUN_TOP_CTRL_SSP_CONFIG_ssp_module_enable_MASK 0x00000001
-#define BCHP_SUN_TOP_CTRL_SSP_CONFIG_ssp_module_enable_SHIFT 0
-#define BCHP_SUN_TOP_CTRL_SSP_CONFIG_ssp_module_enable_DEFAULT 0x00000001
-
-/***************************************************************************
- *SERS_REV - SERS Revision Register
- ***************************************************************************/
-/* SUN_TOP_CTRL :: SERS_REV :: reserved0 [31:16] */
-#define BCHP_SUN_TOP_CTRL_SERS_REV_reserved0_MASK 0xffff0000
-#define BCHP_SUN_TOP_CTRL_SERS_REV_reserved0_SHIFT 16
-
-/* SUN_TOP_CTRL :: SERS_REV :: reserved_for_eco1 [15:08] */
-#define BCHP_SUN_TOP_CTRL_SERS_REV_reserved_for_eco1_MASK 0x0000ff00
-#define BCHP_SUN_TOP_CTRL_SERS_REV_reserved_for_eco1_SHIFT 8
-#define BCHP_SUN_TOP_CTRL_SERS_REV_reserved_for_eco1_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: SERS_REV :: BLOCK_SERS_REVISION [07:00] */
-#define BCHP_SUN_TOP_CTRL_SERS_REV_BLOCK_SERS_REVISION_MASK 0x000000ff
-#define BCHP_SUN_TOP_CTRL_SERS_REV_BLOCK_SERS_REVISION_SHIFT 0
-#define BCHP_SUN_TOP_CTRL_SERS_REV_BLOCK_SERS_REVISION_DEFAULT 0x00000000
-
-/***************************************************************************
- *SERS_CFG - SERS Configuration Register
- ***************************************************************************/
-/* SUN_TOP_CTRL :: SERS_CFG :: reserved_for_eco0 [31:29] */
-#define BCHP_SUN_TOP_CTRL_SERS_CFG_reserved_for_eco0_MASK 0xe0000000
-#define BCHP_SUN_TOP_CTRL_SERS_CFG_reserved_for_eco0_SHIFT 29
-#define BCHP_SUN_TOP_CTRL_SERS_CFG_reserved_for_eco0_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: SERS_CFG :: CMD_MODE [28:28] */
-#define BCHP_SUN_TOP_CTRL_SERS_CFG_CMD_MODE_MASK 0x10000000
-#define BCHP_SUN_TOP_CTRL_SERS_CFG_CMD_MODE_SHIFT 28
-#define BCHP_SUN_TOP_CTRL_SERS_CFG_CMD_MODE_DEFAULT 0x00000001
-#define BCHP_SUN_TOP_CTRL_SERS_CFG_CMD_MODE_mapped_buffer_mode 0
-#define BCHP_SUN_TOP_CTRL_SERS_CFG_CMD_MODE_cmd_fifo_mode 1
-
-/* SUN_TOP_CTRL :: SERS_CFG :: Little_Endian [27:27] */
-#define BCHP_SUN_TOP_CTRL_SERS_CFG_Little_Endian_MASK 0x08000000
-#define BCHP_SUN_TOP_CTRL_SERS_CFG_Little_Endian_SHIFT 27
-#define BCHP_SUN_TOP_CTRL_SERS_CFG_Little_Endian_DEFAULT 0x00000000
-
-/* union - case mapped_buffer_mode [26:08] */
-/* SUN_TOP_CTRL :: SERS_CFG :: mapped_buffer_mode :: W_PKT_OFFSET_4 [26:22] */
-#define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_W_PKT_OFFSET_4_MASK 0x07c00000
-#define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_W_PKT_OFFSET_4_SHIFT 22
-
-/* SUN_TOP_CTRL :: SERS_CFG :: mapped_buffer_mode :: W_PKT_OFFSET_3 [21:17] */
-#define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_W_PKT_OFFSET_3_MASK 0x003e0000
-#define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_W_PKT_OFFSET_3_SHIFT 17
-
-/* SUN_TOP_CTRL :: SERS_CFG :: mapped_buffer_mode :: W_PKT_OFFSET_2 [16:12] */
-#define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_W_PKT_OFFSET_2_MASK 0x0001f000
-#define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_W_PKT_OFFSET_2_SHIFT 12
-
-/* SUN_TOP_CTRL :: SERS_CFG :: mapped_buffer_mode :: DATA_CHG_IRQ_ONLY_4 [11:11] */
-#define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_DATA_CHG_IRQ_ONLY_4_MASK 0x00000800
-#define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_DATA_CHG_IRQ_ONLY_4_SHIFT 11
-#define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_DATA_CHG_IRQ_ONLY_4_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: SERS_CFG :: mapped_buffer_mode :: DATA_CHG_IRQ_ONLY_3 [10:10] */
-#define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_DATA_CHG_IRQ_ONLY_3_MASK 0x00000400
-#define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_DATA_CHG_IRQ_ONLY_3_SHIFT 10
-#define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_DATA_CHG_IRQ_ONLY_3_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: SERS_CFG :: mapped_buffer_mode :: DATA_CHG_IRQ_ONLY_2 [09:09] */
-#define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_DATA_CHG_IRQ_ONLY_2_MASK 0x00000200
-#define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_DATA_CHG_IRQ_ONLY_2_SHIFT 9
-#define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_DATA_CHG_IRQ_ONLY_2_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: SERS_CFG :: mapped_buffer_mode :: DATA_CHG_IRQ_ONLY_1 [08:08] */
-#define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_DATA_CHG_IRQ_ONLY_1_MASK 0x00000100
-#define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_DATA_CHG_IRQ_ONLY_1_SHIFT 8
-#define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_DATA_CHG_IRQ_ONLY_1_DEFAULT 0x00000000
-
-/* union - case cmd_fifo_mode [26:08] */
-/* SUN_TOP_CTRL :: SERS_CFG :: cmd_fifo_mode :: CMD_W_PTR [26:22] */
-#define BCHP_SUN_TOP_CTRL_SERS_CFG_cmd_fifo_mode_CMD_W_PTR_MASK 0x07c00000
-#define BCHP_SUN_TOP_CTRL_SERS_CFG_cmd_fifo_mode_CMD_W_PTR_SHIFT 22
-#define BCHP_SUN_TOP_CTRL_SERS_CFG_cmd_fifo_mode_CMD_W_PTR_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: SERS_CFG :: cmd_fifo_mode :: CMD_R_PTR [21:17] */
-#define BCHP_SUN_TOP_CTRL_SERS_CFG_cmd_fifo_mode_CMD_R_PTR_MASK 0x003e0000
-#define BCHP_SUN_TOP_CTRL_SERS_CFG_cmd_fifo_mode_CMD_R_PTR_SHIFT 17
-#define BCHP_SUN_TOP_CTRL_SERS_CFG_cmd_fifo_mode_CMD_R_PTR_DEFAULT 0x0000001f
-
-/* SUN_TOP_CTRL :: SERS_CFG :: cmd_fifo_mode :: FIFO_THRESHOLD [16:12] */
-#define BCHP_SUN_TOP_CTRL_SERS_CFG_cmd_fifo_mode_FIFO_THRESHOLD_MASK 0x0001f000
-#define BCHP_SUN_TOP_CTRL_SERS_CFG_cmd_fifo_mode_FIFO_THRESHOLD_SHIFT 12
-#define BCHP_SUN_TOP_CTRL_SERS_CFG_cmd_fifo_mode_FIFO_THRESHOLD_DEFAULT 0x00000010
-
-/* SUN_TOP_CTRL :: SERS_CFG :: cmd_fifo_mode :: NOT_USED [11:10] */
-#define BCHP_SUN_TOP_CTRL_SERS_CFG_cmd_fifo_mode_NOT_USED_MASK 0x00000c00
-#define BCHP_SUN_TOP_CTRL_SERS_CFG_cmd_fifo_mode_NOT_USED_SHIFT 10
-#define BCHP_SUN_TOP_CTRL_SERS_CFG_cmd_fifo_mode_NOT_USED_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: SERS_CFG :: cmd_fifo_mode :: CMD_FIFO_OV [09:09] */
-#define BCHP_SUN_TOP_CTRL_SERS_CFG_cmd_fifo_mode_CMD_FIFO_OV_MASK 0x00000200
-#define BCHP_SUN_TOP_CTRL_SERS_CFG_cmd_fifo_mode_CMD_FIFO_OV_SHIFT 9
-#define BCHP_SUN_TOP_CTRL_SERS_CFG_cmd_fifo_mode_CMD_FIFO_OV_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: SERS_CFG :: cmd_fifo_mode :: DROP_CMDS [08:08] */
-#define BCHP_SUN_TOP_CTRL_SERS_CFG_cmd_fifo_mode_DROP_CMDS_MASK 0x00000100
-#define BCHP_SUN_TOP_CTRL_SERS_CFG_cmd_fifo_mode_DROP_CMDS_SHIFT 8
-#define BCHP_SUN_TOP_CTRL_SERS_CFG_cmd_fifo_mode_DROP_CMDS_DEFAULT 0x00000001
-
-/* SUN_TOP_CTRL :: SERS_CFG :: SER_ADR [07:01] */
-#define BCHP_SUN_TOP_CTRL_SERS_CFG_SER_ADR_MASK 0x000000fe
-#define BCHP_SUN_TOP_CTRL_SERS_CFG_SER_ADR_SHIFT 1
-#define BCHP_SUN_TOP_CTRL_SERS_CFG_SER_ADR_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: SERS_CFG :: SOFT_SER_ADR [00:00] */
-#define BCHP_SUN_TOP_CTRL_SERS_CFG_SOFT_SER_ADR_MASK 0x00000001
-#define BCHP_SUN_TOP_CTRL_SERS_CFG_SOFT_SER_ADR_SHIFT 0
-#define BCHP_SUN_TOP_CTRL_SERS_CFG_SOFT_SER_ADR_DEFAULT 0x00000000
-
-/***************************************************************************
- *SERS_CMD_BUF_%i - Host Serial Write Command Buffer
- ***************************************************************************/
-#define BCHP_SUN_TOP_CTRL_SERS_CMD_BUF_i_ARRAY_BASE 0x20404428
-#define BCHP_SUN_TOP_CTRL_SERS_CMD_BUF_i_ARRAY_START 0
-#define BCHP_SUN_TOP_CTRL_SERS_CMD_BUF_i_ARRAY_END 7
-#define BCHP_SUN_TOP_CTRL_SERS_CMD_BUF_i_ARRAY_ELEMENT_SIZE 32
-
-/***************************************************************************
- *SERS_CMD_BUF_%i - Host Serial Write Command Buffer
- ***************************************************************************/
-/* SUN_TOP_CTRL :: SERS_CMD_BUF_i :: SERS_CMD_BUF [31:00] */
-#define BCHP_SUN_TOP_CTRL_SERS_CMD_BUF_i_SERS_CMD_BUF_MASK 0xffffffff
-#define BCHP_SUN_TOP_CTRL_SERS_CMD_BUF_i_SERS_CMD_BUF_SHIFT 0
-
-
-/***************************************************************************
- *SERS_STAT_BUF_%i - Host Serial Read Status Buffer
- ***************************************************************************/
-#define BCHP_SUN_TOP_CTRL_SERS_STAT_BUF_i_ARRAY_BASE 0x20404448
-#define BCHP_SUN_TOP_CTRL_SERS_STAT_BUF_i_ARRAY_START 0
-#define BCHP_SUN_TOP_CTRL_SERS_STAT_BUF_i_ARRAY_END 1
-#define BCHP_SUN_TOP_CTRL_SERS_STAT_BUF_i_ARRAY_ELEMENT_SIZE 32
-
-/***************************************************************************
- *SERS_STAT_BUF_%i - Host Serial Read Status Buffer
- ***************************************************************************/
-/* SUN_TOP_CTRL :: SERS_STAT_BUF_i :: SERS_STAT_BUF [31:00] */
-#define BCHP_SUN_TOP_CTRL_SERS_STAT_BUF_i_SERS_STAT_BUF_MASK 0xffffffff
-#define BCHP_SUN_TOP_CTRL_SERS_STAT_BUF_i_SERS_STAT_BUF_SHIFT 0
-
-
-/***************************************************************************
- *RO_TEST_BLOCK_SEL - Block select for RO testmode
- ***************************************************************************/
-/* SUN_TOP_CTRL :: RO_TEST_BLOCK_SEL :: reserved0 [31:05] */
-#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_reserved0_MASK 0xffffffe0
-#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_reserved0_SHIFT 5
-
-/* SUN_TOP_CTRL :: RO_TEST_BLOCK_SEL :: ro_test_pwenb [04:04] */
-#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_pwenb_MASK 0x00000010
-#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_pwenb_SHIFT 4
-#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_pwenb_DEFAULT 0x00000001
-#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_pwenb_ENABLED 0
-#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_pwenb_DISABLED 1
-
-/* SUN_TOP_CTRL :: RO_TEST_BLOCK_SEL :: ro_test_sub_block_select [03:02] */
-#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_sub_block_select_MASK 0x0000000c
-#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_sub_block_select_SHIFT 2
-#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_sub_block_select_DEFAULT 0x00000000
-#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_sub_block_select_HVT_MIN_LOAD 0
-#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_sub_block_select_HVT_MED_LOAD 1
-#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_sub_block_select_HVT_MAX_LOAD 2
-#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_sub_block_select_SVT_MIN_LOAD 3
-
-/* SUN_TOP_CTRL :: RO_TEST_BLOCK_SEL :: ro_test_block_select [01:00] */
-#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_block_select_MASK 0x00000003
-#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_block_select_SHIFT 0
-#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_block_select_DEFAULT 0x00000000
-#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_block_select_DO_NOT_USE_RO_TEST_ID 0
-#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_block_select_PROD_OSC0_RO_TEST_ID 1
-#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_block_select_PROD_OSC1_RO_TEST_ID 2
-#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_block_select_UNUSED_3_RO_TEST_ID 3
-
-/***************************************************************************
- *TEST_CONFIGURATION - Test configuration
- ***************************************************************************/
-/* SUN_TOP_CTRL :: TEST_CONFIGURATION :: reserved0 [31:04] */
-#define BCHP_SUN_TOP_CTRL_TEST_CONFIGURATION_reserved0_MASK 0xfffffff0
-#define BCHP_SUN_TOP_CTRL_TEST_CONFIGURATION_reserved0_SHIFT 4
-
-/* SUN_TOP_CTRL :: TEST_CONFIGURATION :: test_configuration [03:00] */
-#define BCHP_SUN_TOP_CTRL_TEST_CONFIGURATION_test_configuration_MASK 0x0000000f
-#define BCHP_SUN_TOP_CTRL_TEST_CONFIGURATION_test_configuration_SHIFT 0
-#define BCHP_SUN_TOP_CTRL_TEST_CONFIGURATION_test_configuration_DEFAULT 0x00000000
-
-#endif /* #ifndef BCHP_SUN_TOP_CTRL_H__ */
-
-/* End of File */
diff --git a/include/linux/brcmstb/7145a0/bchp_switch_acb.h b/include/linux/brcmstb/7145a0/bchp_switch_acb.h
deleted file mode 100644
index 248241b..0000000
--- a/include/linux/brcmstb/7145a0/bchp_switch_acb.h
+++ /dev/null
@@ -1,3151 +0,0 @@
-/***************************************************************************
- * Copyright (c) 1999-2013, Broadcom Corporation
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
- *
- * Module Description:
- * DO NOT EDIT THIS FILE DIRECTLY
- *
- * This module was generated magically with RDB from a source description
- * file. You must edit the source file for changes to be made to this file.
- *
- *
- * Date: Generated on Wed May 8 03:09:21 2013
- * MD5 Checksum d41d8cd98f00b204e9800998ecf8427e
- *
- * Compiled with: RDB Utility combo_header.pl
- * RDB Parser 3.0
- * unknown unknown
- * Perl Interpreter 5.008008
- * Operating System linux
- *
- * Revision History:
- *
- * $brcm_Log: $
- *
- ***************************************************************************/
-
-#ifndef BCHP_SWITCH_ACB_H__
-#define BCHP_SWITCH_ACB_H__
-
-/***************************************************************************
- *SWITCH_ACB
- ***************************************************************************/
-#define BCHP_SWITCH_ACB_ACB_CONTROL 0x04e40600 /* ACB Control Register */
-#define BCHP_SWITCH_ACB_ACB_XON_THRESHOLD_CONFIGURATION 0x04e40604 /* ACB XON Threshold Configuration Register */
-#define BCHP_SWITCH_ACB_ACB_QUEUE_0_CONFIGURATION 0x04e40608 /* ACB Queue 0 Configuration Register */
-#define BCHP_SWITCH_ACB_ACB_QUEUE_1_CONFIGURATION 0x04e4060c /* ACB Queue 1 Configuration Register */
-#define BCHP_SWITCH_ACB_ACB_QUEUE_2_CONFIGURATION 0x04e40610 /* ACB Queue 2 Configuration Register */
-#define BCHP_SWITCH_ACB_ACB_QUEUE_3_CONFIGURATION 0x04e40614 /* ACB Queue 3 Configuration Register */
-#define BCHP_SWITCH_ACB_ACB_QUEUE_4_CONFIGURATION 0x04e40618 /* ACB Queue 4 Configuration Register */
-#define BCHP_SWITCH_ACB_ACB_QUEUE_5_CONFIGURATION 0x04e4061c /* ACB Queue 5 Configuration Register */
-#define BCHP_SWITCH_ACB_ACB_QUEUE_6_CONFIGURATION 0x04e40620 /* ACB Queue 6 Configuration Register */
-#define BCHP_SWITCH_ACB_ACB_QUEUE_7_CONFIGURATION 0x04e40624 /* ACB Queue 7 Configuration Register */
-#define BCHP_SWITCH_ACB_ACB_QUEUE_8_CONFIGURATION 0x04e40628 /* ACB Queue 8 Configuration Register */
-#define BCHP_SWITCH_ACB_ACB_QUEUE_9_CONFIGURATION 0x04e4062c /* ACB Queue 9 Configuration Register */
-#define BCHP_SWITCH_ACB_ACB_QUEUE_10_CONFIGURATION 0x04e40630 /* ACB Queue 10 Configuration Register */
-#define BCHP_SWITCH_ACB_ACB_QUEUE_11_CONFIGURATION 0x04e40634 /* ACB Queue 11 Configuration Register */
-#define BCHP_SWITCH_ACB_ACB_QUEUE_12_CONFIGURATION 0x04e40638 /* ACB Queue 12 Configuration Register */
-#define BCHP_SWITCH_ACB_ACB_QUEUE_13_CONFIGURATION 0x04e4063c /* ACB Queue 13 Configuration Register */
-#define BCHP_SWITCH_ACB_ACB_QUEUE_14_CONFIGURATION 0x04e40640 /* ACB Queue 14 Configuration Register */
-#define BCHP_SWITCH_ACB_ACB_QUEUE_15_CONFIGURATION 0x04e40644 /* ACB Queue 15 Configuration Register */
-#define BCHP_SWITCH_ACB_ACB_QUEUE_16_CONFIGURATION 0x04e40648 /* ACB Queue 16 Configuration Register */
-#define BCHP_SWITCH_ACB_ACB_QUEUE_17_CONFIGURATION 0x04e4064c /* ACB Queue 17 Configuration Register */
-#define BCHP_SWITCH_ACB_ACB_QUEUE_18_CONFIGURATION 0x04e40650 /* ACB Queue 18 Configuration Register */
-#define BCHP_SWITCH_ACB_ACB_QUEUE_19_CONFIGURATION 0x04e40654 /* ACB Queue 19 Configuration Register */
-#define BCHP_SWITCH_ACB_ACB_QUEUE_20_CONFIGURATION 0x04e40658 /* ACB Queue 20 Configuration Register */
-#define BCHP_SWITCH_ACB_ACB_QUEUE_21_CONFIGURATION 0x04e4065c /* ACB Queue 21 Configuration Register */
-#define BCHP_SWITCH_ACB_ACB_QUEUE_22_CONFIGURATION 0x04e40660 /* ACB Queue 22 Configuration Register */
-#define BCHP_SWITCH_ACB_ACB_QUEUE_23_CONFIGURATION 0x04e40664 /* ACB Queue 23 Configuration Register */
-#define BCHP_SWITCH_ACB_ACB_QUEUE_24_CONFIGURATION 0x04e40668 /* ACB Queue 24 Configuration Register6 */
-#define BCHP_SWITCH_ACB_ACB_QUEUE_25_CONFIGURATION 0x04e4066c /* ACB Queue 25 Configuration Register */
-#define BCHP_SWITCH_ACB_ACB_QUEUE_26_CONFIGURATION 0x04e40670 /* ACB Queue 26 Configuration Register */
-#define BCHP_SWITCH_ACB_ACB_QUEUE_27_CONFIGURATION 0x04e40674 /* ACB Queue 27 Configuration Register */
-#define BCHP_SWITCH_ACB_ACB_QUEUE_28_CONFIGURATION 0x04e40678 /* ACB Queue 28 Configuration Register */
-#define BCHP_SWITCH_ACB_ACB_QUEUE_29_CONFIGURATION 0x04e4067c /* ACB Queue 29 Configuration Register */
-#define BCHP_SWITCH_ACB_ACB_QUEUE_30_CONFIGURATION 0x04e40680 /* ACB Queue 30 Configuration Register */
-#define BCHP_SWITCH_ACB_ACB_QUEUE_31_CONFIGURATION 0x04e40684 /* ACB Queue 31 Configuration Register */
-#define BCHP_SWITCH_ACB_ACB_QUEUE_32_CONFIGURATION 0x04e40688 /* ACB Queue 32 Configuration Register */
-#define BCHP_SWITCH_ACB_ACB_QUEUE_33_CONFIGURATION 0x04e4068c /* ACB Queue 33 Configuration Register */
-#define BCHP_SWITCH_ACB_ACB_QUEUE_34_CONFIGURATION 0x04e40690 /* ACB Queue 34 Configuration Register */
-#define BCHP_SWITCH_ACB_ACB_QUEUE_35_CONFIGURATION 0x04e40694 /* ACB Queue 35 Configuration Register */
-#define BCHP_SWITCH_ACB_ACB_QUEUE_36_CONFIGURATION 0x04e40698 /* ACB Queue 36 Configuration Register */
-#define BCHP_SWITCH_ACB_ACB_QUEUE_37_CONFIGURATION 0x04e4069c /* ACB Queue 37 Configuration Register */
-#define BCHP_SWITCH_ACB_ACB_QUEUE_38_CONFIGURATION 0x04e406a0 /* ACB Queue 38 Configuration Register */
-#define BCHP_SWITCH_ACB_ACB_QUEUE_39_CONFIGURATION 0x04e406a4 /* ACB Queue 39 Configuration Register */
-#define BCHP_SWITCH_ACB_ACB_QUEUE_40_CONFIGURATION 0x04e406a8 /* ACB Queue 40 Configuration Register */
-#define BCHP_SWITCH_ACB_ACB_QUEUE_41_CONFIGURATION 0x04e406ac /* ACB Queue 41 Configuration Register */
-#define BCHP_SWITCH_ACB_ACB_QUEUE_42_CONFIGURATION 0x04e406b0 /* ACB Queue 42 Configuration Register */
-#define BCHP_SWITCH_ACB_ACB_QUEUE_43_CONFIGURATION 0x04e406b4 /* ACB Queue 43 Configuration Register */
-#define BCHP_SWITCH_ACB_ACB_QUEUE_44_CONFIGURATION 0x04e406b8 /* ACB Queue 44 Configuration Register */
-#define BCHP_SWITCH_ACB_ACB_QUEUE_45_CONFIGURATION 0x04e406bc /* ACB Queue 45 Configuration Register */
-#define BCHP_SWITCH_ACB_ACB_QUEUE_46_CONFIGURATION 0x04e406c0 /* ACB Queue 46 Configuration Register */
-#define BCHP_SWITCH_ACB_ACB_QUEUE_47_CONFIGURATION 0x04e406c4 /* ACB Queue 47 Configuration Register */
-#define BCHP_SWITCH_ACB_ACB_QUEUE_48_CONFIGURATION 0x04e406c8 /* ACB Queue 48 Configuration Register */
-#define BCHP_SWITCH_ACB_ACB_QUEUE_49_CONFIGURATION 0x04e406cc /* ACB Queue 49 Configuration Register */
-#define BCHP_SWITCH_ACB_ACB_QUEUE_50_CONFIGURATION 0x04e406d0 /* ACB Queue 50 Configuration Register */
-#define BCHP_SWITCH_ACB_ACB_QUEUE_51_CONFIGURATION 0x04e406d4 /* ACB Queue 51 Configuration Register6 */
-#define BCHP_SWITCH_ACB_ACB_QUEUE_52_CONFIGURATION 0x04e406d8 /* ACB Queue 52 Configuration Register */
-#define BCHP_SWITCH_ACB_ACB_QUEUE_53_CONFIGURATION 0x04e406dc /* ACB Queue 53 Configuration Register */
-#define BCHP_SWITCH_ACB_ACB_QUEUE_54_CONFIGURATION 0x04e406e0 /* ACB Queue 54 Configuration Register */
-#define BCHP_SWITCH_ACB_ACB_QUEUE_55_CONFIGURATION 0x04e406e4 /* ACB Queue 55 Configuration Register */
-#define BCHP_SWITCH_ACB_ACB_QUEUE_56_CONFIGURATION 0x04e406e8 /* ACB Queue 56 Configuration Register */
-#define BCHP_SWITCH_ACB_ACB_QUEUE_57_CONFIGURATION 0x04e406ec /* ACB Queue 57 Configuration Register */
-#define BCHP_SWITCH_ACB_ACB_QUEUE_58_CONFIGURATION 0x04e406f0 /* ACB Queue 58 Configuration Register */
-#define BCHP_SWITCH_ACB_ACB_QUEUE_59_CONFIGURATION 0x04e406f4 /* ACB Queue 59 Configuration Register */
-#define BCHP_SWITCH_ACB_ACB_QUEUE_60_CONFIGURATION 0x04e406f8 /* ACB Queue 60 Configuration Register */
-#define BCHP_SWITCH_ACB_ACB_QUEUE_61_CONFIGURATION 0x04e406fc /* ACB Queue 61 Configuration Register */
-#define BCHP_SWITCH_ACB_ACB_QUEUE_62_CONFIGURATION 0x04e40700 /* ACB Queue 62 Configuration Register */
-#define BCHP_SWITCH_ACB_ACB_QUEUE_63_CONFIGURATION 0x04e40704 /* ACB Queue 63 Configuration Register */
-
-/***************************************************************************
- *ACB_CONTROL - ACB Control Register
- ***************************************************************************/
-/* SWITCH_ACB :: ACB_CONTROL :: reserved0 [31:01] */
-#define BCHP_SWITCH_ACB_ACB_CONTROL_reserved0_MASK 0xfffffffe
-#define BCHP_SWITCH_ACB_ACB_CONTROL_reserved0_SHIFT 1
-
-/* SWITCH_ACB :: ACB_CONTROL :: acb_en [00:00] */
-#define BCHP_SWITCH_ACB_ACB_CONTROL_acb_en_MASK 0x00000001
-#define BCHP_SWITCH_ACB_ACB_CONTROL_acb_en_SHIFT 0
-#define BCHP_SWITCH_ACB_ACB_CONTROL_acb_en_DEFAULT 0x00000000
-
-/***************************************************************************
- *ACB_XON_THRESHOLD_CONFIGURATION - ACB XON Threshold Configuration Register
- ***************************************************************************/
-/* SWITCH_ACB :: ACB_XON_THRESHOLD_CONFIGURATION :: reserved0 [31:22] */
-#define BCHP_SWITCH_ACB_ACB_XON_THRESHOLD_CONFIGURATION_reserved0_MASK 0xffc00000
-#define BCHP_SWITCH_ACB_ACB_XON_THRESHOLD_CONFIGURATION_reserved0_SHIFT 22
-
-/* SWITCH_ACB :: ACB_XON_THRESHOLD_CONFIGURATION :: total_xon_hyst [21:11] */
-#define BCHP_SWITCH_ACB_ACB_XON_THRESHOLD_CONFIGURATION_total_xon_hyst_MASK 0x003ff800
-#define BCHP_SWITCH_ACB_ACB_XON_THRESHOLD_CONFIGURATION_total_xon_hyst_SHIFT 11
-#define BCHP_SWITCH_ACB_ACB_XON_THRESHOLD_CONFIGURATION_total_xon_hyst_DEFAULT 0x00000000
-
-/* SWITCH_ACB :: ACB_XON_THRESHOLD_CONFIGURATION :: queue_xon_hyst [10:00] */
-#define BCHP_SWITCH_ACB_ACB_XON_THRESHOLD_CONFIGURATION_queue_xon_hyst_MASK 0x000007ff
-#define BCHP_SWITCH_ACB_ACB_XON_THRESHOLD_CONFIGURATION_queue_xon_hyst_SHIFT 0
-#define BCHP_SWITCH_ACB_ACB_XON_THRESHOLD_CONFIGURATION_queue_xon_hyst_DEFAULT 0x00000000
-
-/***************************************************************************
- *ACB_QUEUE_0_CONFIGURATION - ACB Queue 0 Configuration Register
- ***************************************************************************/
-/* SWITCH_ACB :: ACB_QUEUE_0_CONFIGURATION :: pessimistic_mode_en [31:31] */
-#define BCHP_SWITCH_ACB_ACB_QUEUE_0_CONFIGURATION_pessimistic_mode_en_MASK 0x80000000
-#define BCHP_SWITCH_ACB_ACB_QUEUE_0_CONFIGURATION_pessimistic_mode_en_SHIFT 31
-#define BCHP_SWITCH_ACB_ACB_QUEUE_0_CONFIGURATION_pessimistic_mode_en_DEFAULT 0x00000000
-#define BCHP_SWITCH_ACB_ACB_QUEUE_0_CONFIGURATION_pessimistic_mode_en_GISB 1
-#define BCHP_SWITCH_ACB_ACB_QUEUE_0_CONFIGURATION_pessimistic_mode_en_PORT 0
-
-/* union - case input_is_gisb [30:25] */
-/* SWITCH_ACB :: ACB_QUEUE_0_CONFIGURATION :: input_is_gisb :: pktlen [30:25] */
-#define BCHP_SWITCH_ACB_ACB_QUEUE_0_CONFIGURATION_input_is_gisb_pktlen_MASK 0x7e000000
-#define BCHP_SWITCH_ACB_ACB_QUEUE_0_CONFIGURATION_input_is_gisb_pktlen_SHIFT 25
-#define BCHP_SWITCH_ACB_ACB_QUEUE_0_CONFIGURATION_input_is_gisb_pktlen_DEFAULT 0x00000000
-
-/* union - case input_is_acb_queue_0_configuration [30:25] */
-/* SWITCH_ACB :: ACB_QUEUE_0_CONFIGURATION :: input_is_acb_queue_0_configuration :: pktlen [30:25] */
-#define BCHP_SWITCH_ACB_ACB_QUEUE_0_CONFIGURATION_input_is_acb_queue_0_configuration_pktlen_MASK 0x7e000000
-#define BCHP_SWITCH_ACB_ACB_QUEUE_0_CONFIGURATION_input_is_acb_queue_0_configuration_pktlen_SHIFT 25
-#define BCHP_SWITCH_ACB_ACB_QUEUE_0_CONFIGURATION_input_is_acb_queue_0_configuration_pktlen_DEFAULT 0x00000000
-
-/* SWITCH_ACB :: ACB_QUEUE_0_CONFIGURATION :: total_xon_en [24:24] */
-#define BCHP_SWITCH_ACB_ACB_QUEUE_0_CONFIGURATION_total_xon_en_MASK 0x01000000
-#define BCHP_SWITCH_ACB_ACB_QUEUE_0_CONFIGURATION_total_xon_en_SHIFT 24
-#define BCHP_SWITCH_ACB_ACB_QUEUE_0_CONFIGURATION_total_xon_en_DEFAULT 0x00000000
-
-/* SWITCH_ACB :: ACB_QUEUE_0_CONFIGURATION :: total_xoff_en [23:23] */
-#define BCHP_SWITCH_ACB_ACB_QUEUE_0_CONFIGURATION_total_xoff_en_MASK 0x00800000
-#define BCHP_SWITCH_ACB_ACB_QUEUE_0_CONFIGURATION_total_xoff_en_SHIFT 23
-#define BCHP_SWITCH_ACB_ACB_QUEUE_0_CONFIGURATION_total_xoff_en_DEFAULT 0x00000000
-
-/* SWITCH_ACB :: ACB_QUEUE_0_CONFIGURATION :: total_xoff_threshold [22:12] */
-#define BCHP_SWITCH_ACB_ACB_QUEUE_0_CONFIGURATION_total_xoff_threshold_MASK 0x007ff000
-#define BCHP_SWITCH_ACB_ACB_QUEUE_0_CONFIGURATION_total_xoff_threshold_SHIFT 12
-#define BCHP_SWITCH_ACB_ACB_QUEUE_0_CONFIGURATION_total_xoff_threshold_DEFAULT 0x00000000
-
-/* SWITCH_ACB :: ACB_QUEUE_0_CONFIGURATION :: xon_en [11:11] */
-#define BCHP_SWITCH_ACB_ACB_QUEUE_0_CONFIGURATION_xon_en_MASK 0x00000800
-#define BCHP_SWITCH_ACB_ACB_QUEUE_0_CONFIGURATION_xon_en_SHIFT 11
-#define BCHP_SWITCH_ACB_ACB_QUEUE_0_CONFIGURATION_xon_en_DEFAULT 0x00000000
-
-/* SWITCH_ACB :: ACB_QUEUE_0_CONFIGURATION :: xoff_threshold [10:00] */
-#define BCHP_SWITCH_ACB_ACB_QUEUE_0_CONFIGURATION_xoff_threshold_MASK 0x000007ff
-#define BCHP_SWITCH_ACB_ACB_QUEUE_0_CONFIGURATION_xoff_threshold_SHIFT 0
-#define BCHP_SWITCH_ACB_ACB_QUEUE_0_CONFIGURATION_xoff_threshold_DEFAULT 0x00000000
-
-/***************************************************************************
- *ACB_QUEUE_1_CONFIGURATION - ACB Queue 1 Configuration Register
- ***************************************************************************/
-/* SWITCH_ACB :: ACB_QUEUE_1_CONFIGURATION :: pessimistic_mode_en [31:31] */
-#define BCHP_SWITCH_ACB_ACB_QUEUE_1_CONFIGURATION_pessimistic_mode_en_MASK 0x80000000
-#define BCHP_SWITCH_ACB_ACB_QUEUE_1_CONFIGURATION_pessimistic_mode_en_SHIFT 31
-#define BCHP_SWITCH_ACB_ACB_QUEUE_1_CONFIGURATION_pessimistic_mode_en_DEFAULT 0x00000000
-#define BCHP_SWITCH_ACB_ACB_QUEUE_1_CONFIGURATION_pessimistic_mode_en_GISB 1
-#define BCHP_SWITCH_ACB_ACB_QUEUE_1_CONFIGURATION_pessimistic_mode_en_PORT 0
-
-/* union - case input_is_gisb [30:25] */
-/* SWITCH_ACB :: ACB_QUEUE_1_CONFIGURATION :: input_is_gisb :: pktlen [30:25] */
-#define BCHP_SWITCH_ACB_ACB_QUEUE_1_CONFIGURATION_input_is_gisb_pktlen_MASK 0x7e000000
-#define BCHP_SWITCH_ACB_ACB_QUEUE_1_CONFIGURATION_input_is_gisb_pktlen_SHIFT 25
-#define BCHP_SWITCH_ACB_ACB_QUEUE_1_CONFIGURATION_input_is_gisb_pktlen_DEFAULT 0x00000000
-
-/* union - case input_is_acb_queue_1_configuration [30:25] */
-/* SWITCH_ACB :: ACB_QUEUE_1_CONFIGURATION :: input_is_acb_queue_1_configuration :: pktlen [30:25] */
-#define BCHP_SWITCH_ACB_ACB_QUEUE_1_CONFIGURATION_input_is_acb_queue_1_configuration_pktlen_MASK 0x7e000000
-#define BCHP_SWITCH_ACB_ACB_QUEUE_1_CONFIGURATION_input_is_acb_queue_1_configuration_pktlen_SHIFT 25
-#define BCHP_SWITCH_ACB_ACB_QUEUE_1_CONFIGURATION_input_is_acb_queue_1_configuration_pktlen_DEFAULT 0x00000000
-
-/* SWITCH_ACB :: ACB_QUEUE_1_CONFIGURATION :: total_xon_en [24:24] */
-#define BCHP_SWITCH_ACB_ACB_QUEUE_1_CONFIGURATION_total_xon_en_MASK 0x01000000
-#define BCHP_SWITCH_ACB_ACB_QUEUE_1_CONFIGURATION_total_xon_en_SHIFT 24
-#define BCHP_SWITCH_ACB_ACB_QUEUE_1_CONFIGURATION_total_xon_en_DEFAULT 0x00000000
-
-/* SWITCH_ACB :: ACB_QUEUE_1_CONFIGURATION :: total_xoff_en [23:23] */
-#define BCHP_SWITCH_ACB_ACB_QUEUE_1_CONFIGURATION_total_xoff_en_MASK 0x00800000
-#define BCHP_SWITCH_ACB_ACB_QUEUE_1_CONFIGURATION_total_xoff_en_SHIFT 23
-#define BCHP_SWITCH_ACB_ACB_QUEUE_1_CONFIGURATION_total_xoff_en_DEFAULT 0x00000000
-
-/* SWITCH_ACB :: ACB_QUEUE_1_CONFIGURATION :: total_xoff_threshold [22:12] */
-#define BCHP_SWITCH_ACB_ACB_QUEUE_1_CONFIGURATION_total_xoff_threshold_MASK 0x007ff000
-#define BCHP_SWITCH_ACB_ACB_QUEUE_1_CONFIGURATION_total_xoff_threshold_SHIFT 12
-#define BCHP_SWITCH_ACB_ACB_QUEUE_1_CONFIGURATION_total_xoff_threshold_DEFAULT 0x00000000
-
-/* SWITCH_ACB :: ACB_QUEUE_1_CONFIGURATION :: xon_en [11:11] */
-#define BCHP_SWITCH_ACB_ACB_QUEUE_1_CONFIGURATION_xon_en_MASK 0x00000800
-#define BCHP_SWITCH_ACB_ACB_QUEUE_1_CONFIGURATION_xon_en_SHIFT 11
-#define BCHP_SWITCH_ACB_ACB_QUEUE_1_CONFIGURATION_xon_en_DEFAULT 0x00000000
-
-/* SWITCH_ACB :: ACB_QUEUE_1_CONFIGURATION :: xoff_threshold [10:00] */
-#define BCHP_SWITCH_ACB_ACB_QUEUE_1_CONFIGURATION_xoff_threshold_MASK 0x000007ff
-#define BCHP_SWITCH_ACB_ACB_QUEUE_1_CONFIGURATION_xoff_threshold_SHIFT 0
-#define BCHP_SWITCH_ACB_ACB_QUEUE_1_CONFIGURATION_xoff_threshold_DEFAULT 0x00000000
-
-/***************************************************************************
- *ACB_QUEUE_2_CONFIGURATION - ACB Queue 2 Configuration Register
- ***************************************************************************/
-/* SWITCH_ACB :: ACB_QUEUE_2_CONFIGURATION :: pessimistic_mode_en [31:31] */
-#define BCHP_SWITCH_ACB_ACB_QUEUE_2_CONFIGURATION_pessimistic_mode_en_MASK 0x80000000
-#define BCHP_SWITCH_ACB_ACB_QUEUE_2_CONFIGURATION_pessimistic_mode_en_SHIFT 31
-#define BCHP_SWITCH_ACB_ACB_QUEUE_2_CONFIGURATION_pessimistic_mode_en_DEFAULT 0x00000000
-#define BCHP_SWITCH_ACB_ACB_QUEUE_2_CONFIGURATION_pessimistic_mode_en_GISB 1
-#define BCHP_SWITCH_ACB_ACB_QUEUE_2_CONFIGURATION_pessimistic_mode_en_PORT 0
-
-/* union - case input_is_gisb [30:25] */
-/* SWITCH_ACB :: ACB_QUEUE_2_CONFIGURATION :: input_is_gisb :: pktlen [30:25] */
-#define BCHP_SWITCH_ACB_ACB_QUEUE_2_CONFIGURATION_input_is_gisb_pktlen_MASK 0x7e000000
-#define BCHP_SWITCH_ACB_ACB_QUEUE_2_CONFIGURATION_input_is_gisb_pktlen_SHIFT 25
-#define BCHP_SWITCH_ACB_ACB_QUEUE_2_CONFIGURATION_input_is_gisb_pktlen_DEFAULT 0x00000000
-
-/* union - case input_is_acb_queue_2_configuration [30:25] */
-/* SWITCH_ACB :: ACB_QUEUE_2_CONFIGURATION :: input_is_acb_queue_2_configuration :: pktlen [30:25] */
-#define BCHP_SWITCH_ACB_ACB_QUEUE_2_CONFIGURATION_input_is_acb_queue_2_configuration_pktlen_MASK 0x7e000000
-#define BCHP_SWITCH_ACB_ACB_QUEUE_2_CONFIGURATION_input_is_acb_queue_2_configuration_pktlen_SHIFT 25
-#define BCHP_SWITCH_ACB_ACB_QUEUE_2_CONFIGURATION_input_is_acb_queue_2_configuration_pktlen_DEFAULT 0x00000000
-
-/* SWITCH_ACB :: ACB_QUEUE_2_CONFIGURATION :: total_xon_en [24:24] */
-#define BCHP_SWITCH_ACB_ACB_QUEUE_2_CONFIGURATION_total_xon_en_MASK 0x01000000
-#define BCHP_SWITCH_ACB_ACB_QUEUE_2_CONFIGURATION_total_xon_en_SHIFT 24
-#define BCHP_SWITCH_ACB_ACB_QUEUE_2_CONFIGURATION_total_xon_en_DEFAULT 0x00000000
-
-/* SWITCH_ACB :: ACB_QUEUE_2_CONFIGURATION :: total_xoff_en [23:23] */
-#define BCHP_SWITCH_ACB_ACB_QUEUE_2_CONFIGURATION_total_xoff_en_MASK 0x00800000
-#define BCHP_SWITCH_ACB_ACB_QUEUE_2_CONFIGURATION_total_xoff_en_SHIFT 23
-#define BCHP_SWITCH_ACB_ACB_QUEUE_2_CONFIGURATION_total_xoff_en_DEFAULT 0x00000000
-
-/* SWITCH_ACB :: ACB_QUEUE_2_CONFIGURATION :: total_xoff_threshold [22:12] */
-#define BCHP_SWITCH_ACB_ACB_QUEUE_2_CONFIGURATION_total_xoff_threshold_MASK 0x007ff000
-#define BCHP_SWITCH_ACB_ACB_QUEUE_2_CONFIGURATION_total_xoff_threshold_SHIFT 12
-#define BCHP_SWITCH_ACB_ACB_QUEUE_2_CONFIGURATION_total_xoff_threshold_DEFAULT 0x00000000
-
-/* SWITCH_ACB :: ACB_QUEUE_2_CONFIGURATION :: xon_en [11:11] */
-#define BCHP_SWITCH_ACB_ACB_QUEUE_2_CONFIGURATION_xon_en_MASK 0x00000800
-#define BCHP_SWITCH_ACB_ACB_QUEUE_2_CONFIGURATION_xon_en_SHIFT 11
-#define BCHP_SWITCH_ACB_ACB_QUEUE_2_CONFIGURATION_xon_en_DEFAULT 0x00000000
-
-/* SWITCH_ACB :: ACB_QUEUE_2_CONFIGURATION :: xoff_threshold [10:00] */
-#define BCHP_SWITCH_ACB_ACB_QUEUE_2_CONFIGURATION_xoff_threshold_MASK 0x000007ff
-#define BCHP_SWITCH_ACB_ACB_QUEUE_2_CONFIGURATION_xoff_threshold_SHIFT 0
-#define BCHP_SWITCH_ACB_ACB_QUEUE_2_CONFIGURATION_xoff_threshold_DEFAULT 0x00000000
-
-/***************************************************************************
- *ACB_QUEUE_3_CONFIGURATION - ACB Queue 3 Configuration Register
- ***************************************************************************/
-/* SWITCH_ACB :: ACB_QUEUE_3_CONFIGURATION :: pessimistic_mode_en [31:31] */
-#define BCHP_SWITCH_ACB_ACB_QUEUE_3_CONFIGURATION_pessimistic_mode_en_MASK 0x80000000
-#define BCHP_SWITCH_ACB_ACB_QUEUE_3_CONFIGURATION_pessimistic_mode_en_SHIFT 31
-#define BCHP_SWITCH_ACB_ACB_QUEUE_3_CONFIGURATION_pessimistic_mode_en_DEFAULT 0x00000000
-#define BCHP_SWITCH_ACB_ACB_QUEUE_3_CONFIGURATION_pessimistic_mode_en_GISB 1
-#define BCHP_SWITCH_ACB_ACB_QUEUE_3_CONFIGURATION_pessimistic_mode_en_PORT 0
-
-/* union - case input_is_gisb [30:25] */
-/* SWITCH_ACB :: ACB_QUEUE_3_CONFIGURATION :: input_is_gisb :: pktlen [30:25] */
-#define BCHP_SWITCH_ACB_ACB_QUEUE_3_CONFIGURATION_input_is_gisb_pktlen_MASK 0x7e000000
-#define BCHP_SWITCH_ACB_ACB_QUEUE_3_CONFIGURATION_input_is_gisb_pktlen_SHIFT 25
-#define BCHP_SWITCH_ACB_ACB_QUEUE_3_CONFIGURATION_input_is_gisb_pktlen_DEFAULT 0x00000000
-
-/* union - case input_is_acb_queue_3_configuration [30:25] */
-/* SWITCH_ACB :: ACB_QUEUE_3_CONFIGURATION :: input_is_acb_queue_3_configuration :: pktlen [30:25] */
-#define BCHP_SWITCH_ACB_ACB_QUEUE_3_CONFIGURATION_input_is_acb_queue_3_configuration_pktlen_MASK 0x7e000000
-#define BCHP_SWITCH_ACB_ACB_QUEUE_3_CONFIGURATION_input_is_acb_queue_3_configuration_pktlen_SHIFT 25
-#define BCHP_SWITCH_ACB_ACB_QUEUE_3_CONFIGURATION_input_is_acb_queue_3_configuration_pktlen_DEFAULT 0x00000000
-
-/* SWITCH_ACB :: ACB_QUEUE_3_CONFIGURATION :: total_xon_en [24:24] */
-#define BCHP_SWITCH_ACB_ACB_QUEUE_3_CONFIGURATION_total_xon_en_MASK 0x01000000
-#define BCHP_SWITCH_ACB_ACB_QUEUE_3_CONFIGURATION_total_xon_en_SHIFT 24
-#define BCHP_SWITCH_ACB_ACB_QUEUE_3_CONFIGURATION_total_xon_en_DEFAULT 0x00000000
-
-/* SWITCH_ACB :: ACB_QUEUE_3_CONFIGURATION :: total_xoff_en [23:23] */
-#define BCHP_SWITCH_ACB_ACB_QUEUE_3_CONFIGURATION_total_xoff_en_MASK 0x00800000
-#define BCHP_SWITCH_ACB_ACB_QUEUE_3_CONFIGURATION_total_xoff_en_SHIFT 23
-#define BCHP_SWITCH_ACB_ACB_QUEUE_3_CONFIGURATION_total_xoff_en_DEFAULT 0x00000000
-
-/* SWITCH_ACB :: ACB_QUEUE_3_CONFIGURATION :: total_xoff_threshold [22:12] */
-#define BCHP_SWITCH_ACB_ACB_QUEUE_3_CONFIGURATION_total_xoff_threshold_MASK 0x007ff000
-#define BCHP_SWITCH_ACB_ACB_QUEUE_3_CONFIGURATION_total_xoff_threshold_SHIFT 12
-#define BCHP_SWITCH_ACB_ACB_QUEUE_3_CONFIGURATION_total_xoff_threshold_DEFAULT 0x00000000
-
-/* SWITCH_ACB :: ACB_QUEUE_3_CONFIGURATION :: xon_en [11:11] */
-#define BCHP_SWITCH_ACB_ACB_QUEUE_3_CONFIGURATION_xon_en_MASK 0x00000800
-#define BCHP_SWITCH_ACB_ACB_QUEUE_3_CONFIGURATION_xon_en_SHIFT 11
-#define BCHP_SWITCH_ACB_ACB_QUEUE_3_CONFIGURATION_xon_en_DEFAULT 0x00000000
-
-/* SWITCH_ACB :: ACB_QUEUE_3_CONFIGURATION :: xoff_threshold [10:00] */
-#define BCHP_SWITCH_ACB_ACB_QUEUE_3_CONFIGURATION_xoff_threshold_MASK 0x000007ff
-#define BCHP_SWITCH_ACB_ACB_QUEUE_3_CONFIGURATION_xoff_threshold_SHIFT 0
-#define BCHP_SWITCH_ACB_ACB_QUEUE_3_CONFIGURATION_xoff_threshold_DEFAULT 0x00000000
-
-/***************************************************************************
- *ACB_QUEUE_4_CONFIGURATION - ACB Queue 4 Configuration Register
- ***************************************************************************/
-/* SWITCH_ACB :: ACB_QUEUE_4_CONFIGURATION :: pessimistic_mode_en [31:31] */
-#define BCHP_SWITCH_ACB_ACB_QUEUE_4_CONFIGURATION_pessimistic_mode_en_MASK 0x80000000
-#define BCHP_SWITCH_ACB_ACB_QUEUE_4_CONFIGURATION_pessimistic_mode_en_SHIFT 31
-#define BCHP_SWITCH_ACB_ACB_QUEUE_4_CONFIGURATION_pessimistic_mode_en_DEFAULT 0x00000000
-#define BCHP_SWITCH_ACB_ACB_QUEUE_4_CONFIGURATION_pessimistic_mode_en_GISB 1
-#define BCHP_SWITCH_ACB_ACB_QUEUE_4_CONFIGURATION_pessimistic_mode_en_PORT 0
-
-/* union - case input_is_gisb [30:25] */
-/* SWITCH_ACB :: ACB_QUEUE_4_CONFIGURATION :: input_is_gisb :: pktlen [30:25] */
-#define BCHP_SWITCH_ACB_ACB_QUEUE_4_CONFIGURATION_input_is_gisb_pktlen_MASK 0x7e000000
-#define BCHP_SWITCH_ACB_ACB_QUEUE_4_CONFIGURATION_input_is_gisb_pktlen_SHIFT 25
-#define BCHP_SWITCH_ACB_ACB_QUEUE_4_CONFIGURATION_input_is_gisb_pktlen_DEFAULT 0x00000000
-
-/* union - case input_is_acb_queue_4_configuration [30:25] */
-/* SWITCH_ACB :: ACB_QUEUE_4_CONFIGURATION :: input_is_acb_queue_4_configuration :: pktlen [30:25] */
-#define BCHP_SWITCH_ACB_ACB_QUEUE_4_CONFIGURATION_input_is_acb_queue_4_configuration_pktlen_MASK 0x7e000000
-#define BCHP_SWITCH_ACB_ACB_QUEUE_4_CONFIGURATION_input_is_acb_queue_4_configuration_pktlen_SHIFT 25
-#define BCHP_SWITCH_ACB_ACB_QUEUE_4_CONFIGURATION_input_is_acb_queue_4_configuration_pktlen_DEFAULT 0x00000000
-
-/* SWITCH_ACB :: ACB_QUEUE_4_CONFIGURATION :: total_xon_en [24:24] */
-#define BCHP_SWITCH_ACB_ACB_QUEUE_4_CONFIGURATION_total_xon_en_MASK 0x01000000
-#define BCHP_SWITCH_ACB_ACB_QUEUE_4_CONFIGURATION_total_xon_en_SHIFT 24
-#define BCHP_SWITCH_ACB_ACB_QUEUE_4_CONFIGURATION_total_xon_en_DEFAULT 0x00000000
-
-/* SWITCH_ACB :: ACB_QUEUE_4_CONFIGURATION :: total_xoff_en [23:23] */
-#define BCHP_SWITCH_ACB_ACB_QUEUE_4_CONFIGURATION_total_xoff_en_MASK 0x00800000
-#define BCHP_SWITCH_ACB_ACB_QUEUE_4_CONFIGURATION_total_xoff_en_SHIFT 23
-#define BCHP_SWITCH_ACB_ACB_QUEUE_4_CONFIGURATION_total_xoff_en_DEFAULT 0x00000000
-
-/* SWITCH_ACB :: ACB_QUEUE_4_CONFIGURATION :: total_xoff_threshold [22:12] */
-#define BCHP_SWITCH_ACB_ACB_QUEUE_4_CONFIGURATION_total_xoff_threshold_MASK 0x007ff000
-#define BCHP_SWITCH_ACB_ACB_QUEUE_4_CONFIGURATION_total_xoff_threshold_SHIFT 12
-#define BCHP_SWITCH_ACB_ACB_QUEUE_4_CONFIGURATION_total_xoff_threshold_DEFAULT 0x00000000
-
-/* SWITCH_ACB :: ACB_QUEUE_4_CONFIGURATION :: xon_en [11:11] */
-#define BCHP_SWITCH_ACB_ACB_QUEUE_4_CONFIGURATION_xon_en_MASK 0x00000800
-#define BCHP_SWITCH_ACB_ACB_QUEUE_4_CONFIGURATION_xon_en_SHIFT 11
-#define BCHP_SWITCH_ACB_ACB_QUEUE_4_CONFIGURATION_xon_en_DEFAULT 0x00000000
-
-/* SWITCH_ACB :: ACB_QUEUE_4_CONFIGURATION :: xoff_threshold [10:00] */
-#define BCHP_SWITCH_ACB_ACB_QUEUE_4_CONFIGURATION_xoff_threshold_MASK 0x000007ff
-#define BCHP_SWITCH_ACB_ACB_QUEUE_4_CONFIGURATION_xoff_threshold_SHIFT 0
-#define BCHP_SWITCH_ACB_ACB_QUEUE_4_CONFIGURATION_xoff_threshold_DEFAULT 0x00000000
-
-/***************************************************************************
- *ACB_QUEUE_5_CONFIGURATION - ACB Queue 5 Configuration Register
- ***************************************************************************/
-/* SWITCH_ACB :: ACB_QUEUE_5_CONFIGURATION :: pessimistic_mode_en [31:31] */
-#define BCHP_SWITCH_ACB_ACB_QUEUE_5_CONFIGURATION_pessimistic_mode_en_MASK 0x80000000
-#define BCHP_SWITCH_ACB_ACB_QUEUE_5_CONFIGURATION_pessimistic_mode_en_SHIFT 31
-#define BCHP_SWITCH_ACB_ACB_QUEUE_5_CONFIGURATION_pessimistic_mode_en_DEFAULT 0x00000000
-#define BCHP_SWITCH_ACB_ACB_QUEUE_5_CONFIGURATION_pessimistic_mode_en_GISB 1
-#define BCHP_SWITCH_ACB_ACB_QUEUE_5_CONFIGURATION_pessimistic_mode_en_PORT 0
-
-/* union - case input_is_gisb [30:25] */
-/* SWITCH_ACB :: ACB_QUEUE_5_CONFIGURATION :: input_is_gisb :: pktlen [30:25] */
-#define BCHP_SWITCH_ACB_ACB_QUEUE_5_CONFIGURATION_input_is_gisb_pktlen_MASK 0x7e000000
-#define BCHP_SWITCH_ACB_ACB_QUEUE_5_CONFIGURATION_input_is_gisb_pktlen_SHIFT 25
-#define BCHP_SWITCH_ACB_ACB_QUEUE_5_CONFIGURATION_input_is_gisb_pktlen_DEFAULT 0x00000000
-
-/* union - case input_is_acb_queue_5_configuration [30:25] */
-/* SWITCH_ACB :: ACB_QUEUE_5_CONFIGURATION :: input_is_acb_queue_5_configuration :: pktlen [30:25] */
-#define BCHP_SWITCH_ACB_ACB_QUEUE_5_CONFIGURATION_input_is_acb_queue_5_configuration_pktlen_MASK 0x7e000000
-#define BCHP_SWITCH_ACB_ACB_QUEUE_5_CONFIGURATION_input_is_acb_queue_5_configuration_pktlen_SHIFT 25
-#define BCHP_SWITCH_ACB_ACB_QUEUE_5_CONFIGURATION_input_is_acb_queue_5_configuration_pktlen_DEFAULT 0x00000000
-
-/* SWITCH_ACB :: ACB_QUEUE_5_CONFIGURATION :: total_xon_en [24:24] */
-#define BCHP_SWITCH_ACB_ACB_QUEUE_5_CONFIGURATION_total_xon_en_MASK 0x01000000
-#define BCHP_SWITCH_ACB_ACB_QUEUE_5_CONFIGURATION_total_xon_en_SHIFT 24
-#define BCHP_SWITCH_ACB_ACB_QUEUE_5_CONFIGURATION_total_xon_en_DEFAULT 0x00000000
-
-/* SWITCH_ACB :: ACB_QUEUE_5_CONFIGURATION :: total_xoff_en [23:23] */
-#define BCHP_SWITCH_ACB_ACB_QUEUE_5_CONFIGURATION_total_xoff_en_MASK 0x00800000
-#define BCHP_SWITCH_ACB_ACB_QUEUE_5_CONFIGURATION_total_xoff_en_SHIFT 23
-#define BCHP_SWITCH_ACB_ACB_QUEUE_5_CONFIGURATION_total_xoff_en_DEFAULT 0x00000000
-
-/* SWITCH_ACB :: ACB_QUEUE_5_CONFIGURATION :: total_xoff_threshold [22:12] */
-#define BCHP_SWITCH_ACB_ACB_QUEUE_5_CONFIGURATION_total_xoff_threshold_MASK 0x007ff000
-#define BCHP_SWITCH_ACB_ACB_QUEUE_5_CONFIGURATION_total_xoff_threshold_SHIFT 12
-#define BCHP_SWITCH_ACB_ACB_QUEUE_5_CONFIGURATION_total_xoff_threshold_DEFAULT 0x00000000
-
-/* SWITCH_ACB :: ACB_QUEUE_5_CONFIGURATION :: xon_en [11:11] */
-#define BCHP_SWITCH_ACB_ACB_QUEUE_5_CONFIGURATION_xon_en_MASK 0x00000800
-#define BCHP_SWITCH_ACB_ACB_QUEUE_5_CONFIGURATION_xon_en_SHIFT 11
-#define BCHP_SWITCH_ACB_ACB_QUEUE_5_CONFIGURATION_xon_en_DEFAULT 0x00000000
-
-/* SWITCH_ACB :: ACB_QUEUE_5_CONFIGURATION :: xoff_threshold [10:00] */
-#define BCHP_SWITCH_ACB_ACB_QUEUE_5_CONFIGURATION_xoff_threshold_MASK 0x000007ff
-#define BCHP_SWITCH_ACB_ACB_QUEUE_5_CONFIGURATION_xoff_threshold_SHIFT 0
-#define BCHP_SWITCH_ACB_ACB_QUEUE_5_CONFIGURATION_xoff_threshold_DEFAULT 0x00000000
-
-/***************************************************************************
- *ACB_QUEUE_6_CONFIGURATION - ACB Queue 6 Configuration Register
- ***************************************************************************/
-/* SWITCH_ACB :: ACB_QUEUE_6_CONFIGURATION :: pessimistic_mode_en [31:31] */
-#define BCHP_SWITCH_ACB_ACB_QUEUE_6_CONFIGURATION_pessimistic_mode_en_MASK 0x80000000
-#define BCHP_SWITCH_ACB_ACB_QUEUE_6_CONFIGURATION_pessimistic_mode_en_SHIFT 31
-#define BCHP_SWITCH_ACB_ACB_QUEUE_6_CONFIGURATION_pessimistic_mode_en_DEFAULT 0x00000000
-#define BCHP_SWITCH_ACB_ACB_QUEUE_6_CONFIGURATION_pessimistic_mode_en_GISB 1
-#define BCHP_SWITCH_ACB_ACB_QUEUE_6_CONFIGURATION_pessimistic_mode_en_PORT 0
-
-/* union - case input_is_gisb [30:25] */
-/* SWITCH_ACB :: ACB_QUEUE_6_CONFIGURATION :: input_is_gisb :: pktlen [30:25] */
-#define BCHP_SWITCH_ACB_ACB_QUEUE_6_CONFIGURATION_input_is_gisb_pktlen_MASK 0x7e000000
-#define BCHP_SWITCH_ACB_ACB_QUEUE_6_CONFIGURATION_input_is_gisb_pktlen_SHIFT 25
-#define BCHP_SWITCH_ACB_ACB_QUEUE_6_CONFIGURATION_input_is_gisb_pktlen_DEFAULT 0x00000000
-
-/* union - case input_is_acb_queue_6_configuration [30:25] */
-/* SWITCH_ACB :: ACB_QUEUE_6_CONFIGURATION :: input_is_acb_queue_6_configuration :: pktlen [30:25] */
-#define BCHP_SWITCH_ACB_ACB_QUEUE_6_CONFIGURATION_input_is_acb_queue_6_configuration_pktlen_MASK 0x7e000000
-#define BCHP_SWITCH_ACB_ACB_QUEUE_6_CONFIGURATION_input_is_acb_queue_6_configuration_pktlen_SHIFT 25
-#define BCHP_SWITCH_ACB_ACB_QUEUE_6_CONFIGURATION_input_is_acb_queue_6_configuration_pktlen_DEFAULT 0x00000000
-
-/* SWITCH_ACB :: ACB_QUEUE_6_CONFIGURATION :: total_xon_en [24:24] */
-#define BCHP_SWITCH_ACB_ACB_QUEUE_6_CONFIGURATION_total_xon_en_MASK 0x01000000
-#define BCHP_SWITCH_ACB_ACB_QUEUE_6_CONFIGURATION_total_xon_en_SHIFT 24
-#define BCHP_SWITCH_ACB_ACB_QUEUE_6_CONFIGURATION_total_xon_en_DEFAULT 0x00000000
-
-/* SWITCH_ACB :: ACB_QUEUE_6_CONFIGURATION :: total_xoff_en [23:23] */
-#define BCHP_SWITCH_ACB_ACB_QUEUE_6_CONFIGURATION_total_xoff_en_MASK 0x00800000
-#define BCHP_SWITCH_ACB_ACB_QUEUE_6_CONFIGURATION_total_xoff_en_SHIFT 23
-#define BCHP_SWITCH_ACB_ACB_QUEUE_6_CONFIGURATION_total_xoff_en_DEFAULT 0x00000000
-
-/* SWITCH_ACB :: ACB_QUEUE_6_CONFIGURATION :: total_xoff_threshold [22:12] */
-#define BCHP_SWITCH_ACB_ACB_QUEUE_6_CONFIGURATION_total_xoff_threshold_MASK 0x007ff000
-#define BCHP_SWITCH_ACB_ACB_QUEUE_6_CONFIGURATION_total_xoff_threshold_SHIFT 12
-#define BCHP_SWITCH_ACB_ACB_QUEUE_6_CONFIGURATION_total_xoff_threshold_DEFAULT 0x00000000
-
-/* SWITCH_ACB :: ACB_QUEUE_6_CONFIGURATION :: xon_en [11:11] */
-#define BCHP_SWITCH_ACB_ACB_QUEUE_6_CONFIGURATION_xon_en_MASK 0x00000800
-#define BCHP_SWITCH_ACB_ACB_QUEUE_6_CONFIGURATION_xon_en_SHIFT 11
-#define BCHP_SWITCH_ACB_ACB_QUEUE_6_CONFIGURATION_xon_en_DEFAULT 0x00000000
-
-/* SWITCH_ACB :: ACB_QUEUE_6_CONFIGURATION :: xoff_threshold [10:00] */
-#define BCHP_SWITCH_ACB_ACB_QUEUE_6_CONFIGURATION_xoff_threshold_MASK 0x000007ff
-#define BCHP_SWITCH_ACB_ACB_QUEUE_6_CONFIGURATION_xoff_threshold_SHIFT 0
-#define BCHP_SWITCH_ACB_ACB_QUEUE_6_CONFIGURATION_xoff_threshold_DEFAULT 0x00000000
-
-/***************************************************************************
- *ACB_QUEUE_7_CONFIGURATION - ACB Queue 7 Configuration Register
- ***************************************************************************/
-/* SWITCH_ACB :: ACB_QUEUE_7_CONFIGURATION :: pessimistic_mode_en [31:31] */
-#define BCHP_SWITCH_ACB_ACB_QUEUE_7_CONFIGURATION_pessimistic_mode_en_MASK 0x80000000
-#define BCHP_SWITCH_ACB_ACB_QUEUE_7_CONFIGURATION_pessimistic_mode_en_SHIFT 31
-#define BCHP_SWITCH_ACB_ACB_QUEUE_7_CONFIGURATION_pessimistic_mode_en_DEFAULT 0x00000000
-#define BCHP_SWITCH_ACB_ACB_QUEUE_7_CONFIGURATION_pessimistic_mode_en_GISB 1
-#define BCHP_SWITCH_ACB_ACB_QUEUE_7_CONFIGURATION_pessimistic_mode_en_PORT 0
-
-/* union - case input_is_gisb [30:25] */
-/* SWITCH_ACB :: ACB_QUEUE_7_CONFIGURATION :: input_is_gisb :: pktlen [30:25] */
-#define BCHP_SWITCH_ACB_ACB_QUEUE_7_CONFIGURATION_input_is_gisb_pktlen_MASK 0x7e000000
-#define BCHP_SWITCH_ACB_ACB_QUEUE_7_CONFIGURATION_input_is_gisb_pktlen_SHIFT 25
-#define BCHP_SWITCH_ACB_ACB_QUEUE_7_CONFIGURATION_input_is_gisb_pktlen_DEFAULT 0x00000000
-
-/* union - case input_is_acb_queue_7_configuration [30:25] */
-/* SWITCH_ACB :: ACB_QUEUE_7_CONFIGURATION :: input_is_acb_queue_7_configuration :: pktlen [30:25] */
-#define BCHP_SWITCH_ACB_ACB_QUEUE_7_CONFIGURATION_input_is_acb_queue_7_configuration_pktlen_MASK 0x7e000000
-#define BCHP_SWITCH_ACB_ACB_QUEUE_7_CONFIGURATION_input_is_acb_queue_7_configuration_pktlen_SHIFT 25
-#define BCHP_SWITCH_ACB_ACB_QUEUE_7_CONFIGURATION_input_is_acb_queue_7_configuration_pktlen_DEFAULT 0x00000000
-
-/* SWITCH_ACB :: ACB_QUEUE_7_CONFIGURATION :: total_xon_en [24:24] */
-#define BCHP_SWITCH_ACB_ACB_QUEUE_7_CONFIGURATION_total_xon_en_MASK 0x01000000
-#define BCHP_SWITCH_ACB_ACB_QUEUE_7_CONFIGURATION_total_xon_en_SHIFT 24
-#define BCHP_SWITCH_ACB_ACB_QUEUE_7_CONFIGURATION_total_xon_en_DEFAULT 0x00000000
-
-/* SWITCH_ACB :: ACB_QUEUE_7_CONFIGURATION :: total_xoff_en [23:23] */
-#define BCHP_SWITCH_ACB_ACB_QUEUE_7_CONFIGURATION_total_xoff_en_MASK 0x00800000
-#define BCHP_SWITCH_ACB_ACB_QUEUE_7_CONFIGURATION_total_xoff_en_SHIFT 23
-#define BCHP_SWITCH_ACB_ACB_QUEUE_7_CONFIGURATION_total_xoff_en_DEFAULT 0x00000000
-
-/* SWITCH_ACB :: ACB_QUEUE_7_CONFIGURATION :: total_xoff_threshold [22:12] */
-#define BCHP_SWITCH_ACB_ACB_QUEUE_7_CONFIGURATION_total_xoff_threshold_MASK 0x007ff000
-#define BCHP_SWITCH_ACB_ACB_QUEUE_7_CONFIGURATION_total_xoff_threshold_SHIFT 12
-#define BCHP_SWITCH_ACB_ACB_QUEUE_7_CONFIGURATION_total_xoff_threshold_DEFAULT 0x00000000
-
-/* SWITCH_ACB :: ACB_QUEUE_7_CONFIGURATION :: xon_en [11:11] */
-#define BCHP_SWITCH_ACB_ACB_QUEUE_7_CONFIGURATION_xon_en_MASK 0x00000800
-#define BCHP_SWITCH_ACB_ACB_QUEUE_7_CONFIGURATION_xon_en_SHIFT 11
-#define BCHP_SWITCH_ACB_ACB_QUEUE_7_CONFIGURATION_xon_en_DEFAULT 0x00000000
-
-/* SWITCH_ACB :: ACB_QUEUE_7_CONFIGURATION :: xoff_threshold [10:00] */
-#define BCHP_SWITCH_ACB_ACB_QUEUE_7_CONFIGURATION_xoff_threshold_MASK 0x000007ff
-#define BCHP_SWITCH_ACB_ACB_QUEUE_7_CONFIGURATION_xoff_threshold_SHIFT 0
-#define BCHP_SWITCH_ACB_ACB_QUEUE_7_CONFIGURATION_xoff_threshold_DEFAULT 0x00000000
-
-/***************************************************************************
- *ACB_QUEUE_8_CONFIGURATION - ACB Queue 8 Configuration Register
- ***************************************************************************/
-/* SWITCH_ACB :: ACB_QUEUE_8_CONFIGURATION :: pessimistic_mode_en [31:31] */
-#define BCHP_SWITCH_ACB_ACB_QUEUE_8_CONFIGURATION_pessimistic_mode_en_MASK 0x80000000
-#define BCHP_SWITCH_ACB_ACB_QUEUE_8_CONFIGURATION_pessimistic_mode_en_SHIFT 31
-#define BCHP_SWITCH_ACB_ACB_QUEUE_8_CONFIGURATION_pessimistic_mode_en_DEFAULT 0x00000000
-#define BCHP_SWITCH_ACB_ACB_QUEUE_8_CONFIGURATION_pessimistic_mode_en_GISB 1
-#define BCHP_SWITCH_ACB_ACB_QUEUE_8_CONFIGURATION_pessimistic_mode_en_PORT 0
-
-/* union - case input_is_gisb [30:25] */
-/* SWITCH_ACB :: ACB_QUEUE_8_CONFIGURATION :: input_is_gisb :: pktlen [30:25] */
-#define BCHP_SWITCH_ACB_ACB_QUEUE_8_CONFIGURATION_input_is_gisb_pktlen_MASK 0x7e000000
-#define BCHP_SWITCH_ACB_ACB_QUEUE_8_CONFIGURATION_input_is_gisb_pktlen_SHIFT 25
-#define BCHP_SWITCH_ACB_ACB_QUEUE_8_CONFIGURATION_input_is_gisb_pktlen_DEFAULT 0x00000000
-
-/* union - case input_is_acb_queue_8_configuration [30:25] */
-/* SWITCH_ACB :: ACB_QUEUE_8_CONFIGURATION :: input_is_acb_queue_8_configuration :: pktlen [30:25] */
-#define BCHP_SWITCH_ACB_ACB_QUEUE_8_CONFIGURATION_input_is_acb_queue_8_configuration_pktlen_MASK 0x7e000000
-#define BCHP_SWITCH_ACB_ACB_QUEUE_8_CONFIGURATION_input_is_acb_queue_8_configuration_pktlen_SHIFT 25
-#define BCHP_SWITCH_ACB_ACB_QUEUE_8_CONFIGURATION_input_is_acb_queue_8_configuration_pktlen_DEFAULT 0x00000000
-
-/* SWITCH_ACB :: ACB_QUEUE_8_CONFIGURATION :: total_xon_en [24:24] */
-#define BCHP_SWITCH_ACB_ACB_QUEUE_8_CONFIGURATION_total_xon_en_MASK 0x01000000
-#define BCHP_SWITCH_ACB_ACB_QUEUE_8_CONFIGURATION_total_xon_en_SHIFT 24
-#define BCHP_SWITCH_ACB_ACB_QUEUE_8_CONFIGURATION_total_xon_en_DEFAULT 0x00000000
-
-/* SWITCH_ACB :: ACB_QUEUE_8_CONFIGURATION :: total_xoff_en [23:23] */
-#define BCHP_SWITCH_ACB_ACB_QUEUE_8_CONFIGURATION_total_xoff_en_MASK 0x00800000
-#define BCHP_SWITCH_ACB_ACB_QUEUE_8_CONFIGURATION_total_xoff_en_SHIFT 23
-#define BCHP_SWITCH_ACB_ACB_QUEUE_8_CONFIGURATION_total_xoff_en_DEFAULT 0x00000000
-
-/* SWITCH_ACB :: ACB_QUEUE_8_CONFIGURATION :: total_xoff_threshold [22:12] */
-#define BCHP_SWITCH_ACB_ACB_QUEUE_8_CONFIGURATION_total_xoff_threshold_MASK 0x007ff000
-#define BCHP_SWITCH_ACB_ACB_QUEUE_8_CONFIGURATION_total_xoff_threshold_SHIFT 12
-#define BCHP_SWITCH_ACB_ACB_QUEUE_8_CONFIGURATION_total_xoff_threshold_DEFAULT 0x00000000
-
-/* SWITCH_ACB :: ACB_QUEUE_8_CONFIGURATION :: xon_en [11:11] */
-#define BCHP_SWITCH_ACB_ACB_QUEUE_8_CONFIGURATION_xon_en_MASK 0x00000800
-#define BCHP_SWITCH_ACB_ACB_QUEUE_8_CONFIGURATION_xon_en_SHIFT 11
-#define BCHP_SWITCH_ACB_ACB_QUEUE_8_CONFIGURATION_xon_en_DEFAULT 0x00000000
-
-/* SWITCH_ACB :: ACB_QUEUE_8_CONFIGURATION :: xoff_threshold [10:00] */
-#define BCHP_SWITCH_ACB_ACB_QUEUE_8_CONFIGURATION_xoff_threshold_MASK 0x000007ff
-#define BCHP_SWITCH_ACB_ACB_QUEUE_8_CONFIGURATION_xoff_threshold_SHIFT 0
-#define BCHP_SWITCH_ACB_ACB_QUEUE_8_CONFIGURATION_xoff_threshold_DEFAULT 0x00000000
-
-/***************************************************************************
- *ACB_QUEUE_9_CONFIGURATION - ACB Queue 9 Configuration Register
- ***************************************************************************/
-/* SWITCH_ACB :: ACB_QUEUE_9_CONFIGURATION :: pessimistic_mode_en [31:31] */
-#define BCHP_SWITCH_ACB_ACB_QUEUE_9_CONFIGURATION_pessimistic_mode_en_MASK 0x80000000
-#define BCHP_SWITCH_ACB_ACB_QUEUE_9_CONFIGURATION_pessimistic_mode_en_SHIFT 31
-#define BCHP_SWITCH_ACB_ACB_QUEUE_9_CONFIGURATION_pessimistic_mode_en_DEFAULT 0x00000000
-#define BCHP_SWITCH_ACB_ACB_QUEUE_9_CONFIGURATION_pessimistic_mode_en_GISB 1
-#define BCHP_SWITCH_ACB_ACB_QUEUE_9_CONFIGURATION_pessimistic_mode_en_PORT 0
-
-/* union - case input_is_gisb [30:25] */
-/* SWITCH_ACB :: ACB_QUEUE_9_CONFIGURATION :: input_is_gisb :: pktlen [30:25] */
-#define BCHP_SWITCH_ACB_ACB_QUEUE_9_CONFIGURATION_input_is_gisb_pktlen_MASK 0x7e000000
-#define BCHP_SWITCH_ACB_ACB_QUEUE_9_CONFIGURATION_input_is_gisb_pktlen_SHIFT 25
-#define BCHP_SWITCH_ACB_ACB_QUEUE_9_CONFIGURATION_input_is_gisb_pktlen_DEFAULT 0x00000000
-
-/* union - case input_is_acb_queue_9_configuration [30:25] */
-/* SWITCH_ACB :: ACB_QUEUE_9_CONFIGURATION :: input_is_acb_queue_9_configuration :: pktlen [30:25] */
-#define BCHP_SWITCH_ACB_ACB_QUEUE_9_CONFIGURATION_input_is_acb_queue_9_configuration_pktlen_MASK 0x7e000000
-#define BCHP_SWITCH_ACB_ACB_QUEUE_9_CONFIGURATION_input_is_acb_queue_9_configuration_pktlen_SHIFT 25
-#define BCHP_SWITCH_ACB_ACB_QUEUE_9_CONFIGURATION_input_is_acb_queue_9_configuration_pktlen_DEFAULT 0x00000000
-
-/* SWITCH_ACB :: ACB_QUEUE_9_CONFIGURATION :: total_xon_en [24:24] */
-#define BCHP_SWITCH_ACB_ACB_QUEUE_9_CONFIGURATION_total_xon_en_MASK 0x01000000
-#define BCHP_SWITCH_ACB_ACB_QUEUE_9_CONFIGURATION_total_xon_en_SHIFT 24
-#define BCHP_SWITCH_ACB_ACB_QUEUE_9_CONFIGURATION_total_xon_en_DEFAULT 0x00000000
-
-/* SWITCH_ACB :: ACB_QUEUE_9_CONFIGURATION :: total_xoff_en [23:23] */
-#define BCHP_SWITCH_ACB_ACB_QUEUE_9_CONFIGURATION_total_xoff_en_MASK 0x00800000
-#define BCHP_SWITCH_ACB_ACB_QUEUE_9_CONFIGURATION_total_xoff_en_SHIFT 23
-#define BCHP_SWITCH_ACB_ACB_QUEUE_9_CONFIGURATION_total_xoff_en_DEFAULT 0x00000000
-
-/* SWITCH_ACB :: ACB_QUEUE_9_CONFIGURATION :: total_xoff_threshold [22:12] */
-#define BCHP_SWITCH_ACB_ACB_QUEUE_9_CONFIGURATION_total_xoff_threshold_MASK 0x007ff000
-#define BCHP_SWITCH_ACB_ACB_QUEUE_9_CONFIGURATION_total_xoff_threshold_SHIFT 12
-#define BCHP_SWITCH_ACB_ACB_QUEUE_9_CONFIGURATION_total_xoff_threshold_DEFAULT 0x00000000
-
-/* SWITCH_ACB :: ACB_QUEUE_9_CONFIGURATION :: xon_en [11:11] */
-#define BCHP_SWITCH_ACB_ACB_QUEUE_9_CONFIGURATION_xon_en_MASK 0x00000800
-#define BCHP_SWITCH_ACB_ACB_QUEUE_9_CONFIGURATION_xon_en_SHIFT 11
-#define BCHP_SWITCH_ACB_ACB_QUEUE_9_CONFIGURATION_xon_en_DEFAULT 0x00000000
-
-/* SWITCH_ACB :: ACB_QUEUE_9_CONFIGURATION :: xoff_threshold [10:00] */
-#define BCHP_SWITCH_ACB_ACB_QUEUE_9_CONFIGURATION_xoff_threshold_MASK 0x000007ff
-#define BCHP_SWITCH_ACB_ACB_QUEUE_9_CONFIGURATION_xoff_threshold_SHIFT 0
-#define BCHP_SWITCH_ACB_ACB_QUEUE_9_CONFIGURATION_xoff_threshold_DEFAULT 0x00000000
-
-/***************************************************************************
- *ACB_QUEUE_10_CONFIGURATION - ACB Queue 10 Configuration Register
- ***************************************************************************/
-/* SWITCH_ACB :: ACB_QUEUE_10_CONFIGURATION :: pessimistic_mode_en [31:31] */
-#define BCHP_SWITCH_ACB_ACB_QUEUE_10_CONFIGURATION_pessimistic_mode_en_MASK 0x80000000
-#define BCHP_SWITCH_ACB_ACB_QUEUE_10_CONFIGURATION_pessimistic_mode_en_SHIFT 31
-#define BCHP_SWITCH_ACB_ACB_QUEUE_10_CONFIGURATION_pessimistic_mode_en_DEFAULT 0x00000000
-#define BCHP_SWITCH_ACB_ACB_QUEUE_10_CONFIGURATION_pessimistic_mode_en_GISB 1
-#define BCHP_SWITCH_ACB_ACB_QUEUE_10_CONFIGURATION_pessimistic_mode_en_PORT 0
-
-/* union - case input_is_gisb [30:25] */
-/* SWITCH_ACB :: ACB_QUEUE_10_CONFIGURATION :: input_is_gisb :: pktlen [30:25] */
-#define BCHP_SWITCH_ACB_ACB_QUEUE_10_CONFIGURATION_input_is_gisb_pktlen_MASK 0x7e000000
-#define BCHP_SWITCH_ACB_ACB_QUEUE_10_CONFIGURATION_input_is_gisb_pktlen_SHIFT 25
-#define BCHP_SWITCH_ACB_ACB_QUEUE_10_CONFIGURATION_input_is_gisb_pktlen_DEFAULT 0x00000000
-
-/* union - case input_is_acb_queue_10_configuration [30:25] */
-/* SWITCH_ACB :: ACB_QUEUE_10_CONFIGURATION :: input_is_acb_queue_10_configuration :: pktlen [30:25] */
-#define BCHP_SWITCH_ACB_ACB_QUEUE_10_CONFIGURATION_input_is_acb_queue_10_configuration_pktlen_MASK 0x7e000000
-#define BCHP_SWITCH_ACB_ACB_QUEUE_10_CONFIGURATION_input_is_acb_queue_10_configuration_pktlen_SHIFT 25
-#define BCHP_SWITCH_ACB_ACB_QUEUE_10_CONFIGURATION_input_is_acb_queue_10_configuration_pktlen_DEFAULT 0x00000000
-
-/* SWITCH_ACB :: ACB_QUEUE_10_CONFIGURATION :: total_xon_en [24:24] */
-#define BCHP_SWITCH_ACB_ACB_QUEUE_10_CONFIGURATION_total_xon_en_MASK 0x01000000
-#define BCHP_SWITCH_ACB_ACB_QUEUE_10_CONFIGURATION_total_xon_en_SHIFT 24
-#define BCHP_SWITCH_ACB_ACB_QUEUE_10_CONFIGURATION_total_xon_en_DEFAULT 0x00000000
-
-/* SWITCH_ACB :: ACB_QUEUE_10_CONFIGURATION :: total_xoff_en [23:23] */
-#define BCHP_SWITCH_ACB_ACB_QUEUE_10_CONFIGURATION_total_xoff_en_MASK 0x00800000
-#define BCHP_SWITCH_ACB_ACB_QUEUE_10_CONFIGURATION_total_xoff_en_SHIFT 23
-#define BCHP_SWITCH_ACB_ACB_QUEUE_10_CONFIGURATION_total_xoff_en_DEFAULT 0x00000000
-
-/* SWITCH_ACB :: ACB_QUEUE_10_CONFIGURATION :: total_xoff_threshold [22:12] */
-#define BCHP_SWITCH_ACB_ACB_QUEUE_10_CONFIGURATION_total_xoff_threshold_MASK 0x007ff000
-#define BCHP_SWITCH_ACB_ACB_QUEUE_10_CONFIGURATION_total_xoff_threshold_SHIFT 12
-#define BCHP_SWITCH_ACB_ACB_QUEUE_10_CONFIGURATION_total_xoff_threshold_DEFAULT 0x00000000
-
-/* SWITCH_ACB :: ACB_QUEUE_10_CONFIGURATION :: xon_en [11:11] */
-#define BCHP_SWITCH_ACB_ACB_QUEUE_10_CONFIGURATION_xon_en_MASK 0x00000800
-#define BCHP_SWITCH_ACB_ACB_QUEUE_10_CONFIGURATION_xon_en_SHIFT 11
-#define BCHP_SWITCH_ACB_ACB_QUEUE_10_CONFIGURATION_xon_en_DEFAULT 0x00000000
-
-/* SWITCH_ACB :: ACB_QUEUE_10_CONFIGURATION :: xoff_threshold [10:00] */
-#define BCHP_SWITCH_ACB_ACB_QUEUE_10_CONFIGURATION_xoff_threshold_MASK 0x000007ff
-#define BCHP_SWITCH_ACB_ACB_QUEUE_10_CONFIGURATION_xoff_threshold_SHIFT 0
-#define BCHP_SWITCH_ACB_ACB_QUEUE_10_CONFIGURATION_xoff_threshold_DEFAULT 0x00000000
-
-/***************************************************************************
- *ACB_QUEUE_11_CONFIGURATION - ACB Queue 11 Configuration Register
- ***************************************************************************/
-/* SWITCH_ACB :: ACB_QUEUE_11_CONFIGURATION :: pessimistic_mode_en [31:31] */
-#define BCHP_SWITCH_ACB_ACB_QUEUE_11_CONFIGURATION_pessimistic_mode_en_MASK 0x80000000
-#define BCHP_SWITCH_ACB_ACB_QUEUE_11_CONFIGURATION_pessimistic_mode_en_SHIFT 31
-#define BCHP_SWITCH_ACB_ACB_QUEUE_11_CONFIGURATION_pessimistic_mode_en_DEFAULT 0x00000000
-#define BCHP_SWITCH_ACB_ACB_QUEUE_11_CONFIGURATION_pessimistic_mode_en_GISB 1
-#define BCHP_SWITCH_ACB_ACB_QUEUE_11_CONFIGURATION_pessimistic_mode_en_PORT 0
-
-/* union - case input_is_gisb [30:25] */
-/* SWITCH_ACB :: ACB_QUEUE_11_CONFIGURATION :: input_is_gisb :: pktlen [30:25] */
-#define BCHP_SWITCH_ACB_ACB_QUEUE_11_CONFIGURATION_input_is_gisb_pktlen_MASK 0x7e000000
-#define BCHP_SWITCH_ACB_ACB_QUEUE_11_CONFIGURATION_input_is_gisb_pktlen_SHIFT 25
-#define BCHP_SWITCH_ACB_ACB_QUEUE_11_CONFIGURATION_input_is_gisb_pktlen_DEFAULT 0x00000000
-
-/* union - case input_is_acb_queue_11_configuration [30:25] */
-/* SWITCH_ACB :: ACB_QUEUE_11_CONFIGURATION :: input_is_acb_queue_11_configuration :: pktlen [30:25] */
-#define BCHP_SWITCH_ACB_ACB_QUEUE_11_CONFIGURATION_input_is_acb_queue_11_configuration_pktlen_MASK 0x7e000000
-#define BCHP_SWITCH_ACB_ACB_QUEUE_11_CONFIGURATION_input_is_acb_queue_11_configuration_pktlen_SHIFT 25
-#define BCHP_SWITCH_ACB_ACB_QUEUE_11_CONFIGURATION_input_is_acb_queue_11_configuration_pktlen_DEFAULT 0x00000000
-
-/* SWITCH_ACB :: ACB_QUEUE_11_CONFIGURATION :: total_xon_en [24:24] */
-#define BCHP_SWITCH_ACB_ACB_QUEUE_11_CONFIGURATION_total_xon_en_MASK 0x01000000
-#define BCHP_SWITCH_ACB_ACB_QUEUE_11_CONFIGURATION_total_xon_en_SHIFT 24
-#define BCHP_SWITCH_ACB_ACB_QUEUE_11_CONFIGURATION_total_xon_en_DEFAULT 0x00000000
-
-/* SWITCH_ACB :: ACB_QUEUE_11_CONFIGURATION :: total_xoff_en [23:23] */
-#define BCHP_SWITCH_ACB_ACB_QUEUE_11_CONFIGURATION_total_xoff_en_MASK 0x00800000
-#define BCHP_SWITCH_ACB_ACB_QUEUE_11_CONFIGURATION_total_xoff_en_SHIFT 23
-#define BCHP_SWITCH_ACB_ACB_QUEUE_11_CONFIGURATION_total_xoff_en_DEFAULT 0x00000000
-
-/* SWITCH_ACB :: ACB_QUEUE_11_CONFIGURATION :: total_xoff_threshold [22:12] */
-#define BCHP_SWITCH_ACB_ACB_QUEUE_11_CONFIGURATION_total_xoff_threshold_MASK 0x007ff000
-#define BCHP_SWITCH_ACB_ACB_QUEUE_11_CONFIGURATION_total_xoff_threshold_SHIFT 12
-#define BCHP_SWITCH_ACB_ACB_QUEUE_11_CONFIGURATION_total_xoff_threshold_DEFAULT 0x00000000
-
-/* SWITCH_ACB :: ACB_QUEUE_11_CONFIGURATION :: xon_en [11:11] */
-#define BCHP_SWITCH_ACB_ACB_QUEUE_11_CONFIGURATION_xon_en_MASK 0x00000800
-#define BCHP_SWITCH_ACB_ACB_QUEUE_11_CONFIGURATION_xon_en_SHIFT 11
-#define BCHP_SWITCH_ACB_ACB_QUEUE_11_CONFIGURATION_xon_en_DEFAULT 0x00000000
-
-/* SWITCH_ACB :: ACB_QUEUE_11_CONFIGURATION :: xoff_threshold [10:00] */
-#define BCHP_SWITCH_ACB_ACB_QUEUE_11_CONFIGURATION_xoff_threshold_MASK 0x000007ff
-#define BCHP_SWITCH_ACB_ACB_QUEUE_11_CONFIGURATION_xoff_threshold_SHIFT 0
-#define BCHP_SWITCH_ACB_ACB_QUEUE_11_CONFIGURATION_xoff_threshold_DEFAULT 0x00000000
-
-/***************************************************************************
- *ACB_QUEUE_12_CONFIGURATION - ACB Queue 12 Configuration Register
- ***************************************************************************/
-/* SWITCH_ACB :: ACB_QUEUE_12_CONFIGURATION :: pessimistic_mode_en [31:31] */
-#define BCHP_SWITCH_ACB_ACB_QUEUE_12_CONFIGURATION_pessimistic_mode_en_MASK 0x80000000
-#define BCHP_SWITCH_ACB_ACB_QUEUE_12_CONFIGURATION_pessimistic_mode_en_SHIFT 31
-#define BCHP_SWITCH_ACB_ACB_QUEUE_12_CONFIGURATION_pessimistic_mode_en_DEFAULT 0x00000000
-#define BCHP_SWITCH_ACB_ACB_QUEUE_12_CONFIGURATION_pessimistic_mode_en_GISB 1
-#define BCHP_SWITCH_ACB_ACB_QUEUE_12_CONFIGURATION_pessimistic_mode_en_PORT 0
-
-/* union - case input_is_gisb [30:25] */
-/* SWITCH_ACB :: ACB_QUEUE_12_CONFIGURATION :: input_is_gisb :: pktlen [30:25] */
-#define BCHP_SWITCH_ACB_ACB_QUEUE_12_CONFIGURATION_input_is_gisb_pktlen_MASK 0x7e000000
-#define BCHP_SWITCH_ACB_ACB_QUEUE_12_CONFIGURATION_input_is_gisb_pktlen_SHIFT 25
-#define BCHP_SWITCH_ACB_ACB_QUEUE_12_CONFIGURATION_input_is_gisb_pktlen_DEFAULT 0x00000000
-
-/* union - case input_is_acb_queue_12_configuration [30:25] */
-/* SWITCH_ACB :: ACB_QUEUE_12_CONFIGURATION :: input_is_acb_queue_12_configuration :: pktlen [30:25] */
-#define BCHP_SWITCH_ACB_ACB_QUEUE_12_CONFIGURATION_input_is_acb_queue_12_configuration_pktlen_MASK 0x7e000000
-#define BCHP_SWITCH_ACB_ACB_QUEUE_12_CONFIGURATION_input_is_acb_queue_12_configuration_pktlen_SHIFT 25
-#define BCHP_SWITCH_ACB_ACB_QUEUE_12_CONFIGURATION_input_is_acb_queue_12_configuration_pktlen_DEFAULT 0x00000000
-
-/* SWITCH_ACB :: ACB_QUEUE_12_CONFIGURATION :: total_xon_en [24:24] */
-#define BCHP_SWITCH_ACB_ACB_QUEUE_12_CONFIGURATION_total_xon_en_MASK 0x01000000
-#define BCHP_SWITCH_ACB_ACB_QUEUE_12_CONFIGURATION_total_xon_en_SHIFT 24
-#define BCHP_SWITCH_ACB_ACB_QUEUE_12_CONFIGURATION_total_xon_en_DEFAULT 0x00000000
-
-/* SWITCH_ACB :: ACB_QUEUE_12_CONFIGURATION :: total_xoff_en [23:23] */
-#define BCHP_SWITCH_ACB_ACB_QUEUE_12_CONFIGURATION_total_xoff_en_MASK 0x00800000
-#define BCHP_SWITCH_ACB_ACB_QUEUE_12_CONFIGURATION_total_xoff_en_SHIFT 23
-#define BCHP_SWITCH_ACB_ACB_QUEUE_12_CONFIGURATION_total_xoff_en_DEFAULT 0x00000000
-
-/* SWITCH_ACB :: ACB_QUEUE_12_CONFIGURATION :: total_xoff_threshold [22:12] */
-#define BCHP_SWITCH_ACB_ACB_QUEUE_12_CONFIGURATION_total_xoff_threshold_MASK 0x007ff000
-#define BCHP_SWITCH_ACB_ACB_QUEUE_12_CONFIGURATION_total_xoff_threshold_SHIFT 12
-#define BCHP_SWITCH_ACB_ACB_QUEUE_12_CONFIGURATION_total_xoff_threshold_DEFAULT 0x00000000
-
-/* SWITCH_ACB :: ACB_QUEUE_12_CONFIGURATION :: xon_en [11:11] */
-#define BCHP_SWITCH_ACB_ACB_QUEUE_12_CONFIGURATION_xon_en_MASK 0x00000800
-#define BCHP_SWITCH_ACB_ACB_QUEUE_12_CONFIGURATION_xon_en_SHIFT 11
-#define BCHP_SWITCH_ACB_ACB_QUEUE_12_CONFIGURATION_xon_en_DEFAULT 0x00000000
-
-/* SWITCH_ACB :: ACB_QUEUE_12_CONFIGURATION :: xoff_threshold [10:00] */
-#define BCHP_SWITCH_ACB_ACB_QUEUE_12_CONFIGURATION_xoff_threshold_MASK 0x000007ff
-#define BCHP_SWITCH_ACB_ACB_QUEUE_12_CONFIGURATION_xoff_threshold_SHIFT 0
-#define BCHP_SWITCH_ACB_ACB_QUEUE_12_CONFIGURATION_xoff_threshold_DEFAULT 0x00000000
-
-/***************************************************************************
- *ACB_QUEUE_13_CONFIGURATION - ACB Queue 13 Configuration Register
- ***************************************************************************/
-/* SWITCH_ACB :: ACB_QUEUE_13_CONFIGURATION :: pessimistic_mode_en [31:31] */
-#define BCHP_SWITCH_ACB_ACB_QUEUE_13_CONFIGURATION_pessimistic_mode_en_MASK 0x80000000
-#define BCHP_SWITCH_ACB_ACB_QUEUE_13_CONFIGURATION_pessimistic_mode_en_SHIFT 31
-#define BCHP_SWITCH_ACB_ACB_QUEUE_13_CONFIGURATION_pessimistic_mode_en_DEFAULT 0x00000000
-#define BCHP_SWITCH_ACB_ACB_QUEUE_13_CONFIGURATION_pessimistic_mode_en_GISB 1
-#define BCHP_SWITCH_ACB_ACB_QUEUE_13_CONFIGURATION_pessimistic_mode_en_PORT 0
-
-/* union - case input_is_gisb [30:25] */
-/* SWITCH_ACB :: ACB_QUEUE_13_CONFIGURATION :: input_is_gisb :: pktlen [30:25] */
-#define BCHP_SWITCH_ACB_ACB_QUEUE_13_CONFIGURATION_input_is_gisb_pktlen_MASK 0x7e000000
-#define BCHP_SWITCH_ACB_ACB_QUEUE_13_CONFIGURATION_input_is_gisb_pktlen_SHIFT 25
-#define BCHP_SWITCH_ACB_ACB_QUEUE_13_CONFIGURATION_input_is_gisb_pktlen_DEFAULT 0x00000000
-
-/* union - case input_is_acb_queue_13_configuration [30:25] */
-/* SWITCH_ACB :: ACB_QUEUE_13_CONFIGURATION :: input_is_acb_queue_13_configuration :: pktlen [30:25] */
-#define BCHP_SWITCH_ACB_ACB_QUEUE_13_CONFIGURATION_input_is_acb_queue_13_configuration_pktlen_MASK 0x7e000000
-#define BCHP_SWITCH_ACB_ACB_QUEUE_13_CONFIGURATION_input_is_acb_queue_13_configuration_pktlen_SHIFT 25
-#define BCHP_SWITCH_ACB_ACB_QUEUE_13_CONFIGURATION_input_is_acb_queue_13_configuration_pktlen_DEFAULT 0x00000000
-
-/* SWITCH_ACB :: ACB_QUEUE_13_CONFIGURATION :: total_xon_en [24:24] */
-#define BCHP_SWITCH_ACB_ACB_QUEUE_13_CONFIGURATION_total_xon_en_MASK 0x01000000
-#define BCHP_SWITCH_ACB_ACB_QUEUE_13_CONFIGURATION_total_xon_en_SHIFT 24
-#define BCHP_SWITCH_ACB_ACB_QUEUE_13_CONFIGURATION_total_xon_en_DEFAULT 0x00000000
-
-/* SWITCH_ACB :: ACB_QUEUE_13_CONFIGURATION :: total_xoff_en [23:23] */
-#define BCHP_SWITCH_ACB_ACB_QUEUE_13_CONFIGURATION_total_xoff_en_MASK 0x00800000
-#define BCHP_SWITCH_ACB_ACB_QUEUE_13_CONFIGURATION_total_xoff_en_SHIFT 23
-#define BCHP_SWITCH_ACB_ACB_QUEUE_13_CONFIGURATION_total_xoff_en_DEFAULT 0x00000000
-
-/* SWITCH_ACB :: ACB_QUEUE_13_CONFIGURATION :: total_xoff_threshold [22:12] */
-#define BCHP_SWITCH_ACB_ACB_QUEUE_13_CONFIGURATION_total_xoff_threshold_MASK 0x007ff000
-#define BCHP_SWITCH_ACB_ACB_QUEUE_13_CONFIGURATION_total_xoff_threshold_SHIFT 12
-#define BCHP_SWITCH_ACB_ACB_QUEUE_13_CONFIGURATION_total_xoff_threshold_DEFAULT 0x00000000
-
-/* SWITCH_ACB :: ACB_QUEUE_13_CONFIGURATION :: xon_en [11:11] */
-#define BCHP_SWITCH_ACB_ACB_QUEUE_13_CONFIGURATION_xon_en_MASK 0x00000800
-#define BCHP_SWITCH_ACB_ACB_QUEUE_13_CONFIGURATION_xon_en_SHIFT 11
-#define BCHP_SWITCH_ACB_ACB_QUEUE_13_CONFIGURATION_xon_en_DEFAULT 0x00000000
-
-/* SWITCH_ACB :: ACB_QUEUE_13_CONFIGURATION :: xoff_threshold [10:00] */
-#define BCHP_SWITCH_ACB_ACB_QUEUE_13_CONFIGURATION_xoff_threshold_MASK 0x000007ff
-#define BCHP_SWITCH_ACB_ACB_QUEUE_13_CONFIGURATION_xoff_threshold_SHIFT 0
-#define BCHP_SWITCH_ACB_ACB_QUEUE_13_CONFIGURATION_xoff_threshold_DEFAULT 0x00000000
-
-/***************************************************************************
- *ACB_QUEUE_14_CONFIGURATION - ACB Queue 14 Configuration Register
- ***************************************************************************/
-/* SWITCH_ACB :: ACB_QUEUE_14_CONFIGURATION :: pessimistic_mode_en [31:31] */
-#define BCHP_SWITCH_ACB_ACB_QUEUE_14_CONFIGURATION_pessimistic_mode_en_MASK 0x80000000
-#define BCHP_SWITCH_ACB_ACB_QUEUE_14_CONFIGURATION_pessimistic_mode_en_SHIFT 31
-#define BCHP_SWITCH_ACB_ACB_QUEUE_14_CONFIGURATION_pessimistic_mode_en_DEFAULT 0x00000000
-#define BCHP_SWITCH_ACB_ACB_QUEUE_14_CONFIGURATION_pessimistic_mode_en_GISB 1
-#define BCHP_SWITCH_ACB_ACB_QUEUE_14_CONFIGURATION_pessimistic_mode_en_PORT 0
-
-/* union - case input_is_gisb [30:25] */
-/* SWITCH_ACB :: ACB_QUEUE_14_CONFIGURATION :: input_is_gisb :: pktlen [30:25] */
-#define BCHP_SWITCH_ACB_ACB_QUEUE_14_CONFIGURATION_input_is_gisb_pktlen_MASK 0x7e000000
-#define BCHP_SWITCH_ACB_ACB_QUEUE_14_CONFIGURATION_input_is_gisb_pktlen_SHIFT 25
-#define BCHP_SWITCH_ACB_ACB_QUEUE_14_CONFIGURATION_input_is_gisb_pktlen_DEFAULT 0x00000000
-
-/* union - case input_is_acb_queue_14_configuration [30:25] */
-/* SWITCH_ACB :: ACB_QUEUE_14_CONFIGURATION :: input_is_acb_queue_14_configuration :: pktlen [30:25] */
-#define BCHP_SWITCH_ACB_ACB_QUEUE_14_CONFIGURATION_input_is_acb_queue_14_configuration_pktlen_MASK 0x7e000000
-#define BCHP_SWITCH_ACB_ACB_QUEUE_14_CONFIGURATION_input_is_acb_queue_14_configuration_pktlen_SHIFT 25
-#define BCHP_SWITCH_ACB_ACB_QUEUE_14_CONFIGURATION_input_is_acb_queue_14_configuration_pktlen_DEFAULT 0x00000000
-
-/* SWITCH_ACB :: ACB_QUEUE_14_CONFIGURATION :: total_xon_en [24:24] */
-#define BCHP_SWITCH_ACB_ACB_QUEUE_14_CONFIGURATION_total_xon_en_MASK 0x01000000
-#define BCHP_SWITCH_ACB_ACB_QUEUE_14_CONFIGURATION_total_xon_en_SHIFT 24
-#define BCHP_SWITCH_ACB_ACB_QUEUE_14_CONFIGURATION_total_xon_en_DEFAULT 0x00000000
-
-/* SWITCH_ACB :: ACB_QUEUE_14_CONFIGURATION :: total_xoff_en [23:23] */
-#define BCHP_SWITCH_ACB_ACB_QUEUE_14_CONFIGURATION_total_xoff_en_MASK 0x00800000
-#define BCHP_SWITCH_ACB_ACB_QUEUE_14_CONFIGURATION_total_xoff_en_SHIFT 23
-#define BCHP_SWITCH_ACB_ACB_QUEUE_14_CONFIGURATION_total_xoff_en_DEFAULT 0x00000000
-
-/* SWITCH_ACB :: ACB_QUEUE_14_CONFIGURATION :: total_xoff_threshold [22:12] */
-#define BCHP_SWITCH_ACB_ACB_QUEUE_14_CONFIGURATION_total_xoff_threshold_MASK 0x007ff000
-#define BCHP_SWITCH_ACB_ACB_QUEUE_14_CONFIGURATION_total_xoff_threshold_SHIFT 12
-#define BCHP_SWITCH_ACB_ACB_QUEUE_14_CONFIGURATION_total_xoff_threshold_DEFAULT 0x00000000
-
-/* SWITCH_ACB :: ACB_QUEUE_14_CONFIGURATION :: xon_en [11:11] */
-#define BCHP_SWITCH_ACB_ACB_QUEUE_14_CONFIGURATION_xon_en_MASK 0x00000800
-#define BCHP_SWITCH_ACB_ACB_QUEUE_14_CONFIGURATION_xon_en_SHIFT 11
-#define BCHP_SWITCH_ACB_ACB_QUEUE_14_CONFIGURATION_xon_en_DEFAULT 0x00000000
-
-/* SWITCH_ACB :: ACB_QUEUE_14_CONFIGURATION :: xoff_threshold [10:00] */
-#define BCHP_SWITCH_ACB_ACB_QUEUE_14_CONFIGURATION_xoff_threshold_MASK 0x000007ff
-#define BCHP_SWITCH_ACB_ACB_QUEUE_14_CONFIGURATION_xoff_threshold_SHIFT 0
-#define BCHP_SWITCH_ACB_ACB_QUEUE_14_CONFIGURATION_xoff_threshold_DEFAULT 0x00000000
-
-/***************************************************************************
- *ACB_QUEUE_15_CONFIGURATION - ACB Queue 15 Configuration Register
- ***************************************************************************/
-/* SWITCH_ACB :: ACB_QUEUE_15_CONFIGURATION :: pessimistic_mode_en [31:31] */
-#define BCHP_SWITCH_ACB_ACB_QUEUE_15_CONFIGURATION_pessimistic_mode_en_MASK 0x80000000
-#define BCHP_SWITCH_ACB_ACB_QUEUE_15_CONFIGURATION_pessimistic_mode_en_SHIFT 31
-#define BCHP_SWITCH_ACB_ACB_QUEUE_15_CONFIGURATION_pessimistic_mode_en_DEFAULT 0x00000000
-#define BCHP_SWITCH_ACB_ACB_QUEUE_15_CONFIGURATION_pessimistic_mode_en_GISB 1
-#define BCHP_SWITCH_ACB_ACB_QUEUE_15_CONFIGURATION_pessimistic_mode_en_PORT 0
-
-/* union - case input_is_gisb [30:25] */
-/* SWITCH_ACB :: ACB_QUEUE_15_CONFIGURATION :: input_is_gisb :: pktlen [30:25] */
-#define BCHP_SWITCH_ACB_ACB_QUEUE_15_CONFIGURATION_input_is_gisb_pktlen_MASK 0x7e000000
-#define BCHP_SWITCH_ACB_ACB_QUEUE_15_CONFIGURATION_input_is_gisb_pktlen_SHIFT 25
-#define BCHP_SWITCH_ACB_ACB_QUEUE_15_CONFIGURATION_input_is_gisb_pktlen_DEFAULT 0x00000000
-
-/* union - case input_is_acb_queue_15_configuration [30:25] */
-/* SWITCH_ACB :: ACB_QUEUE_15_CONFIGURATION :: input_is_acb_queue_15_configuration :: pktlen [30:25] */
-#define BCHP_SWITCH_ACB_ACB_QUEUE_15_CONFIGURATION_input_is_acb_queue_15_configuration_pktlen_MASK 0x7e000000
-#define BCHP_SWITCH_ACB_ACB_QUEUE_15_CONFIGURATION_input_is_acb_queue_15_configuration_pktlen_SHIFT 25
-#define BCHP_SWITCH_ACB_ACB_QUEUE_15_CONFIGURATION_input_is_acb_queue_15_configuration_pktlen_DEFAULT 0x00000000
-
-/* SWITCH_ACB :: ACB_QUEUE_15_CONFIGURATION :: total_xon_en [24:24] */
-#define BCHP_SWITCH_ACB_ACB_QUEUE_15_CONFIGURATION_total_xon_en_MASK 0x01000000
-#define BCHP_SWITCH_ACB_ACB_QUEUE_15_CONFIGURATION_total_xon_en_SHIFT 24
-#define BCHP_SWITCH_ACB_ACB_QUEUE_15_CONFIGURATION_total_xon_en_DEFAULT 0x00000000
-
-/* SWITCH_ACB :: ACB_QUEUE_15_CONFIGURATION :: total_xoff_en [23:23] */
-#define BCHP_SWITCH_ACB_ACB_QUEUE_15_CONFIGURATION_total_xoff_en_MASK 0x00800000
-#define BCHP_SWITCH_ACB_ACB_QUEUE_15_CONFIGURATION_total_xoff_en_SHIFT 23
-#define BCHP_SWITCH_ACB_ACB_QUEUE_15_CONFIGURATION_total_xoff_en_DEFAULT 0x00000000
-
-/* SWITCH_ACB :: ACB_QUEUE_15_CONFIGURATION :: total_xoff_threshold [22:12] */
-#define BCHP_SWITCH_ACB_ACB_QUEUE_15_CONFIGURATION_total_xoff_threshold_MASK 0x007ff000
-#define BCHP_SWITCH_ACB_ACB_QUEUE_15_CONFIGURATION_total_xoff_threshold_SHIFT 12
-#define BCHP_SWITCH_ACB_ACB_QUEUE_15_CONFIGURATION_total_xoff_threshold_DEFAULT 0x00000000
-
-/* SWITCH_ACB :: ACB_QUEUE_15_CONFIGURATION :: xon_en [11:11] */
-#define BCHP_SWITCH_ACB_ACB_QUEUE_15_CONFIGURATION_xon_en_MASK 0x00000800
-#define BCHP_SWITCH_ACB_ACB_QUEUE_15_CONFIGURATION_xon_en_SHIFT 11
-#define BCHP_SWITCH_ACB_ACB_QUEUE_15_CONFIGURATION_xon_en_DEFAULT 0x00000000
-
-/* SWITCH_ACB :: ACB_QUEUE_15_CONFIGURATION :: xoff_threshold [10:00] */
-#define BCHP_SWITCH_ACB_ACB_QUEUE_15_CONFIGURATION_xoff_threshold_MASK 0x000007ff
-#define BCHP_SWITCH_ACB_ACB_QUEUE_15_CONFIGURATION_xoff_threshold_SHIFT 0
-#define BCHP_SWITCH_ACB_ACB_QUEUE_15_CONFIGURATION_xoff_threshold_DEFAULT 0x00000000
-
-/***************************************************************************
- *ACB_QUEUE_16_CONFIGURATION - ACB Queue 16 Configuration Register
- ***************************************************************************/
-/* SWITCH_ACB :: ACB_QUEUE_16_CONFIGURATION :: pessimistic_mode_en [31:31] */
-#define BCHP_SWITCH_ACB_ACB_QUEUE_16_CONFIGURATION_pessimistic_mode_en_MASK 0x80000000
-#define BCHP_SWITCH_ACB_ACB_QUEUE_16_CONFIGURATION_pessimistic_mode_en_SHIFT 31
-#define BCHP_SWITCH_ACB_ACB_QUEUE_16_CONFIGURATION_pessimistic_mode_en_DEFAULT 0x00000000
-#define BCHP_SWITCH_ACB_ACB_QUEUE_16_CONFIGURATION_pessimistic_mode_en_GISB 1
-#define BCHP_SWITCH_ACB_ACB_QUEUE_16_CONFIGURATION_pessimistic_mode_en_PORT 0
-
-/* union - case input_is_gisb [30:25] */
-/* SWITCH_ACB :: ACB_QUEUE_16_CONFIGURATION :: input_is_gisb :: pktlen [30:25] */
-#define BCHP_SWITCH_ACB_ACB_QUEUE_16_CONFIGURATION_input_is_gisb_pktlen_MASK 0x7e000000
-#define BCHP_SWITCH_ACB_ACB_QUEUE_16_CONFIGURATION_input_is_gisb_pktlen_SHIFT 25
-#define BCHP_SWITCH_ACB_ACB_QUEUE_16_CONFIGURATION_input_is_gisb_pktlen_DEFAULT 0x00000000
-
-/* union - case input_is_acb_queue_16_configuration [30:25] */
-/* SWITCH_ACB :: ACB_QUEUE_16_CONFIGURATION :: input_is_acb_queue_16_configuration :: pktlen [30:25] */
-#define BCHP_SWITCH_ACB_ACB_QUEUE_16_CONFIGURATION_input_is_acb_queue_16_configuration_pktlen_MASK 0x7e000000
-#define BCHP_SWITCH_ACB_ACB_QUEUE_16_CONFIGURATION_input_is_acb_queue_16_configuration_pktlen_SHIFT 25
-#define BCHP_SWITCH_ACB_ACB_QUEUE_16_CONFIGURATION_input_is_acb_queue_16_configuration_pktlen_DEFAULT 0x00000000
-
-/* SWITCH_ACB :: ACB_QUEUE_16_CONFIGURATION :: total_xon_en [24:24] */
-#define BCHP_SWITCH_ACB_ACB_QUEUE_16_CONFIGURATION_total_xon_en_MASK 0x01000000
-#define BCHP_SWITCH_ACB_ACB_QUEUE_16_CONFIGURATION_total_xon_en_SHIFT 24
-#define BCHP_SWITCH_ACB_ACB_QUEUE_16_CONFIGURATION_total_xon_en_DEFAULT 0x00000000
-
-/* SWITCH_ACB :: ACB_QUEUE_16_CONFIGURATION :: total_xoff_en [23:23] */
-#define BCHP_SWITCH_ACB_ACB_QUEUE_16_CONFIGURATION_total_xoff_en_MASK 0x00800000
-#define BCHP_SWITCH_ACB_ACB_QUEUE_16_CONFIGURATION_total_xoff_en_SHIFT 23
-#define BCHP_SWITCH_ACB_ACB_QUEUE_16_CONFIGURATION_total_xoff_en_DEFAULT 0x00000000
-
-/* SWITCH_ACB :: ACB_QUEUE_16_CONFIGURATION :: total_xoff_threshold [22:12] */
-#define BCHP_SWITCH_ACB_ACB_QUEUE_16_CONFIGURATION_total_xoff_threshold_MASK 0x007ff000
-#define BCHP_SWITCH_ACB_ACB_QUEUE_16_CONFIGURATION_total_xoff_threshold_SHIFT 12
-#define BCHP_SWITCH_ACB_ACB_QUEUE_16_CONFIGURATION_total_xoff_threshold_DEFAULT 0x00000000
-
-/* SWITCH_ACB :: ACB_QUEUE_16_CONFIGURATION :: xon_en [11:11] */
-#define BCHP_SWITCH_ACB_ACB_QUEUE_16_CONFIGURATION_xon_en_MASK 0x00000800
-#define BCHP_SWITCH_ACB_ACB_QUEUE_16_CONFIGURATION_xon_en_SHIFT 11
-#define BCHP_SWITCH_ACB_ACB_QUEUE_16_CONFIGURATION_xon_en_DEFAULT 0x00000000
-
-/* SWITCH_ACB :: ACB_QUEUE_16_CONFIGURATION :: xoff_threshold [10:00] */
-#define BCHP_SWITCH_ACB_ACB_QUEUE_16_CONFIGURATION_xoff_threshold_MASK 0x000007ff
-#define BCHP_SWITCH_ACB_ACB_QUEUE_16_CONFIGURATION_xoff_threshold_SHIFT 0
-#define BCHP_SWITCH_ACB_ACB_QUEUE_16_CONFIGURATION_xoff_threshold_DEFAULT 0x00000000
-
-/***************************************************************************
- *ACB_QUEUE_17_CONFIGURATION - ACB Queue 17 Configuration Register
- ***************************************************************************/
-/* SWITCH_ACB :: ACB_QUEUE_17_CONFIGURATION :: pessimistic_mode_en [31:31] */
-#define BCHP_SWITCH_ACB_ACB_QUEUE_17_CONFIGURATION_pessimistic_mode_en_MASK 0x80000000
-#define BCHP_SWITCH_ACB_ACB_QUEUE_17_CONFIGURATION_pessimistic_mode_en_SHIFT 31
-#define BCHP_SWITCH_ACB_ACB_QUEUE_17_CONFIGURATION_pessimistic_mode_en_DEFAULT 0x00000000
-#define BCHP_SWITCH_ACB_ACB_QUEUE_17_CONFIGURATION_pessimistic_mode_en_GISB 1
-#define BCHP_SWITCH_ACB_ACB_QUEUE_17_CONFIGURATION_pessimistic_mode_en_PORT 0
-
-/* union - case input_is_gisb [30:25] */
-/* SWITCH_ACB :: ACB_QUEUE_17_CONFIGURATION :: input_is_gisb :: pktlen [30:25] */
-#define BCHP_SWITCH_ACB_ACB_QUEUE_17_CONFIGURATION_input_is_gisb_pktlen_MASK 0x7e000000
-#define BCHP_SWITCH_ACB_ACB_QUEUE_17_CONFIGURATION_input_is_gisb_pktlen_SHIFT 25
-#define BCHP_SWITCH_ACB_ACB_QUEUE_17_CONFIGURATION_input_is_gisb_pktlen_DEFAULT 0x00000000
-
-/* union - case input_is_acb_queue_17_configuration [30:25] */
-/* SWITCH_ACB :: ACB_QUEUE_17_CONFIGURATION :: input_is_acb_queue_17_configuration :: pktlen [30:25] */
-#define BCHP_SWITCH_ACB_ACB_QUEUE_17_CONFIGURATION_input_is_acb_queue_17_configuration_pktlen_MASK 0x7e000000
-#define BCHP_SWITCH_ACB_ACB_QUEUE_17_CONFIGURATION_input_is_acb_queue_17_configuration_pktlen_SHIFT 25
-#define BCHP_SWITCH_ACB_ACB_QUEUE_17_CONFIGURATION_input_is_acb_queue_17_configuration_pktlen_DEFAULT 0x00000000
-
-/* SWITCH_ACB :: ACB_QUEUE_17_CONFIGURATION :: total_xon_en [24:24] */
-#define BCHP_SWITCH_ACB_ACB_QUEUE_17_CONFIGURATION_total_xon_en_MASK 0x01000000
-#define BCHP_SWITCH_ACB_ACB_QUEUE_17_CONFIGURATION_total_xon_en_SHIFT 24
-#define BCHP_SWITCH_ACB_ACB_QUEUE_17_CONFIGURATION_total_xon_en_DEFAULT 0x00000000
-
-/* SWITCH_ACB :: ACB_QUEUE_17_CONFIGURATION :: total_xoff_en [23:23] */
-#define BCHP_SWITCH_ACB_ACB_QUEUE_17_CONFIGURATION_total_xoff_en_MASK 0x00800000
-#define BCHP_SWITCH_ACB_ACB_QUEUE_17_CONFIGURATION_total_xoff_en_SHIFT 23
-#define BCHP_SWITCH_ACB_ACB_QUEUE_17_CONFIGURATION_total_xoff_en_DEFAULT 0x00000000
-
-/* SWITCH_ACB :: ACB_QUEUE_17_CONFIGURATION :: total_xoff_threshold [22:12] */
-#define BCHP_SWITCH_ACB_ACB_QUEUE_17_CONFIGURATION_total_xoff_threshold_MASK 0x007ff000
-#define BCHP_SWITCH_ACB_ACB_QUEUE_17_CONFIGURATION_total_xoff_threshold_SHIFT 12
-#define BCHP_SWITCH_ACB_ACB_QUEUE_17_CONFIGURATION_total_xoff_threshold_DEFAULT 0x00000000
-
-/* SWITCH_ACB :: ACB_QUEUE_17_CONFIGURATION :: xon_en [11:11] */
-#define BCHP_SWITCH_ACB_ACB_QUEUE_17_CONFIGURATION_xon_en_MASK 0x00000800
-#define BCHP_SWITCH_ACB_ACB_QUEUE_17_CONFIGURATION_xon_en_SHIFT 11
-#define BCHP_SWITCH_ACB_ACB_QUEUE_17_CONFIGURATION_xon_en_DEFAULT 0x00000000
-
-/* SWITCH_ACB :: ACB_QUEUE_17_CONFIGURATION :: xoff_threshold [10:00] */
-#define BCHP_SWITCH_ACB_ACB_QUEUE_17_CONFIGURATION_xoff_threshold_MASK 0x000007ff
-#define BCHP_SWITCH_ACB_ACB_QUEUE_17_CONFIGURATION_xoff_threshold_SHIFT 0
-#define BCHP_SWITCH_ACB_ACB_QUEUE_17_CONFIGURATION_xoff_threshold_DEFAULT 0x00000000
-
-/***************************************************************************
- *ACB_QUEUE_18_CONFIGURATION - ACB Queue 18 Configuration Register
- ***************************************************************************/
-/* SWITCH_ACB :: ACB_QUEUE_18_CONFIGURATION :: pessimistic_mode_en [31:31] */
-#define BCHP_SWITCH_ACB_ACB_QUEUE_18_CONFIGURATION_pessimistic_mode_en_MASK 0x80000000
-#define BCHP_SWITCH_ACB_ACB_QUEUE_18_CONFIGURATION_pessimistic_mode_en_SHIFT 31
-#define BCHP_SWITCH_ACB_ACB_QUEUE_18_CONFIGURATION_pessimistic_mode_en_DEFAULT 0x00000000
-#define BCHP_SWITCH_ACB_ACB_QUEUE_18_CONFIGURATION_pessimistic_mode_en_GISB 1
-#define BCHP_SWITCH_ACB_ACB_QUEUE_18_CONFIGURATION_pessimistic_mode_en_PORT 0
-
-/* union - case input_is_gisb [30:25] */
-/* SWITCH_ACB :: ACB_QUEUE_18_CONFIGURATION :: input_is_gisb :: pktlen [30:25] */
-#define BCHP_SWITCH_ACB_ACB_QUEUE_18_CONFIGURATION_input_is_gisb_pktlen_MASK 0x7e000000
-#define BCHP_SWITCH_ACB_ACB_QUEUE_18_CONFIGURATION_input_is_gisb_pktlen_SHIFT 25
-#define BCHP_SWITCH_ACB_ACB_QUEUE_18_CONFIGURATION_input_is_gisb_pktlen_DEFAULT 0x00000000
-
-/* union - case input_is_acb_queue_18_configuration [30:25] */
-/* SWITCH_ACB :: ACB_QUEUE_18_CONFIGURATION :: input_is_acb_queue_18_configuration :: pktlen [30:25] */
-#define BCHP_SWITCH_ACB_ACB_QUEUE_18_CONFIGURATION_input_is_acb_queue_18_configuration_pktlen_MASK 0x7e000000
-#define BCHP_SWITCH_ACB_ACB_QUEUE_18_CONFIGURATION_input_is_acb_queue_18_configuration_pktlen_SHIFT 25
-#define BCHP_SWITCH_ACB_ACB_QUEUE_18_CONFIGURATION_input_is_acb_queue_18_configuration_pktlen_DEFAULT 0x00000000
-
-/* SWITCH_ACB :: ACB_QUEUE_18_CONFIGURATION :: total_xon_en [24:24] */
-#define BCHP_SWITCH_ACB_ACB_QUEUE_18_CONFIGURATION_total_xon_en_MASK 0x01000000
-#define BCHP_SWITCH_ACB_ACB_QUEUE_18_CONFIGURATION_total_xon_en_SHIFT 24
-#define BCHP_SWITCH_ACB_ACB_QUEUE_18_CONFIGURATION_total_xon_en_DEFAULT 0x00000000
-
-/* SWITCH_ACB :: ACB_QUEUE_18_CONFIGURATION :: total_xoff_en [23:23] */
-#define BCHP_SWITCH_ACB_ACB_QUEUE_18_CONFIGURATION_total_xoff_en_MASK 0x00800000
-#define BCHP_SWITCH_ACB_ACB_QUEUE_18_CONFIGURATION_total_xoff_en_SHIFT 23
-#define BCHP_SWITCH_ACB_ACB_QUEUE_18_CONFIGURATION_total_xoff_en_DEFAULT 0x00000000
-
-/* SWITCH_ACB :: ACB_QUEUE_18_CONFIGURATION :: total_xoff_threshold [22:12] */
-#define BCHP_SWITCH_ACB_ACB_QUEUE_18_CONFIGURATION_total_xoff_threshold_MASK 0x007ff000
-#define BCHP_SWITCH_ACB_ACB_QUEUE_18_CONFIGURATION_total_xoff_threshold_SHIFT 12
-#define BCHP_SWITCH_ACB_ACB_QUEUE_18_CONFIGURATION_total_xoff_threshold_DEFAULT 0x00000000
-
-/* SWITCH_ACB :: ACB_QUEUE_18_CONFIGURATION :: xon_en [11:11] */
-#define BCHP_SWITCH_ACB_ACB_QUEUE_18_CONFIGURATION_xon_en_MASK 0x00000800
-#define BCHP_SWITCH_ACB_ACB_QUEUE_18_CONFIGURATION_xon_en_SHIFT 11
-#define BCHP_SWITCH_ACB_ACB_QUEUE_18_CONFIGURATION_xon_en_DEFAULT 0x00000000
-
-/* SWITCH_ACB :: ACB_QUEUE_18_CONFIGURATION :: xoff_threshold [10:00] */
-#define BCHP_SWITCH_ACB_ACB_QUEUE_18_CONFIGURATION_xoff_threshold_MASK 0x000007ff
-#define BCHP_SWITCH_ACB_ACB_QUEUE_18_CONFIGURATION_xoff_threshold_SHIFT 0
-#define BCHP_SWITCH_ACB_ACB_QUEUE_18_CONFIGURATION_xoff_threshold_DEFAULT 0x00000000
-
-/***************************************************************************
- *ACB_QUEUE_19_CONFIGURATION - ACB Queue 19 Configuration Register
- ***************************************************************************/
-/* SWITCH_ACB :: ACB_QUEUE_19_CONFIGURATION :: pessimistic_mode_en [31:31] */
-#define BCHP_SWITCH_ACB_ACB_QUEUE_19_CONFIGURATION_pessimistic_mode_en_MASK 0x80000000
-#define BCHP_SWITCH_ACB_ACB_QUEUE_19_CONFIGURATION_pessimistic_mode_en_SHIFT 31
-#define BCHP_SWITCH_ACB_ACB_QUEUE_19_CONFIGURATION_pessimistic_mode_en_DEFAULT 0x00000000
-#define BCHP_SWITCH_ACB_ACB_QUEUE_19_CONFIGURATION_pessimistic_mode_en_GISB 1
-#define BCHP_SWITCH_ACB_ACB_QUEUE_19_CONFIGURATION_pessimistic_mode_en_PORT 0
-
-/* union - case input_is_gisb [30:25] */
-/* SWITCH_ACB :: ACB_QUEUE_19_CONFIGURATION :: input_is_gisb :: pktlen [30:25] */
-#define BCHP_SWITCH_ACB_ACB_QUEUE_19_CONFIGURATION_input_is_gisb_pktlen_MASK 0x7e000000
-#define BCHP_SWITCH_ACB_ACB_QUEUE_19_CONFIGURATION_input_is_gisb_pktlen_SHIFT 25
-#define BCHP_SWITCH_ACB_ACB_QUEUE_19_CONFIGURATION_input_is_gisb_pktlen_DEFAULT 0x00000000
-
-/* union - case input_is_acb_queue_19_configuration [30:25] */
-/* SWITCH_ACB :: ACB_QUEUE_19_CONFIGURATION :: input_is_acb_queue_19_configuration :: pktlen [30:25] */
-#define BCHP_SWITCH_ACB_ACB_QUEUE_19_CONFIGURATION_input_is_acb_queue_19_configuration_pktlen_MASK 0x7e000000
-#define BCHP_SWITCH_ACB_ACB_QUEUE_19_CONFIGURATION_input_is_acb_queue_19_configuration_pktlen_SHIFT 25
-#define BCHP_SWITCH_ACB_ACB_QUEUE_19_CONFIGURATION_input_is_acb_queue_19_configuration_pktlen_DEFAULT 0x00000000
-
-/* SWITCH_ACB :: ACB_QUEUE_19_CONFIGURATION :: total_xon_en [24:24] */
-#define BCHP_SWITCH_ACB_ACB_QUEUE_19_CONFIGURATION_total_xon_en_MASK 0x01000000
-#define BCHP_SWITCH_ACB_ACB_QUEUE_19_CONFIGURATION_total_xon_en_SHIFT 24
-#define BCHP_SWITCH_ACB_ACB_QUEUE_19_CONFIGURATION_total_xon_en_DEFAULT 0x00000000
-
-/* SWITCH_ACB :: ACB_QUEUE_19_CONFIGURATION :: total_xoff_en [23:23] */
-#define BCHP_SWITCH_ACB_ACB_QUEUE_19_CONFIGURATION_total_xoff_en_MASK 0x00800000
-#define BCHP_SWITCH_ACB_ACB_QUEUE_19_CONFIGURATION_total_xoff_en_SHIFT 23
-#define BCHP_SWITCH_ACB_ACB_QUEUE_19_CONFIGURATION_total_xoff_en_DEFAULT 0x00000000
-
-/* SWITCH_ACB :: ACB_QUEUE_19_CONFIGURATION :: total_xoff_threshold [22:12] */
-#define BCHP_SWITCH_ACB_ACB_QUEUE_19_CONFIGURATION_total_xoff_threshold_MASK 0x007ff000
-#define BCHP_SWITCH_ACB_ACB_QUEUE_19_CONFIGURATION_total_xoff_threshold_SHIFT 12
-#define BCHP_SWITCH_ACB_ACB_QUEUE_19_CONFIGURATION_total_xoff_threshold_DEFAULT 0x00000000
-
-/* SWITCH_ACB :: ACB_QUEUE_19_CONFIGURATION :: xon_en [11:11] */
-#define BCHP_SWITCH_ACB_ACB_QUEUE_19_CONFIGURATION_xon_en_MASK 0x00000800
-#define BCHP_SWITCH_ACB_ACB_QUEUE_19_CONFIGURATION_xon_en_SHIFT 11
-#define BCHP_SWITCH_ACB_ACB_QUEUE_19_CONFIGURATION_xon_en_DEFAULT 0x00000000
-
-/* SWITCH_ACB :: ACB_QUEUE_19_CONFIGURATION :: xoff_threshold [10:00] */
-#define BCHP_SWITCH_ACB_ACB_QUEUE_19_CONFIGURATION_xoff_threshold_MASK 0x000007ff
-#define BCHP_SWITCH_ACB_ACB_QUEUE_19_CONFIGURATION_xoff_threshold_SHIFT 0
-#define BCHP_SWITCH_ACB_ACB_QUEUE_19_CONFIGURATION_xoff_threshold_DEFAULT 0x00000000
-
-/***************************************************************************
- *ACB_QUEUE_20_CONFIGURATION - ACB Queue 20 Configuration Register
- ***************************************************************************/
-/* SWITCH_ACB :: ACB_QUEUE_20_CONFIGURATION :: pessimistic_mode_en [31:31] */
-#define BCHP_SWITCH_ACB_ACB_QUEUE_20_CONFIGURATION_pessimistic_mode_en_MASK 0x80000000
-#define BCHP_SWITCH_ACB_ACB_QUEUE_20_CONFIGURATION_pessimistic_mode_en_SHIFT 31
-#define BCHP_SWITCH_ACB_ACB_QUEUE_20_CONFIGURATION_pessimistic_mode_en_DEFAULT 0x00000000
-#define BCHP_SWITCH_ACB_ACB_QUEUE_20_CONFIGURATION_pessimistic_mode_en_GISB 1
-#define BCHP_SWITCH_ACB_ACB_QUEUE_20_CONFIGURATION_pessimistic_mode_en_PORT 0
-
-/* union - case input_is_gisb [30:25] */
-/* SWITCH_ACB :: ACB_QUEUE_20_CONFIGURATION :: input_is_gisb :: pktlen [30:25] */
-#define BCHP_SWITCH_ACB_ACB_QUEUE_20_CONFIGURATION_input_is_gisb_pktlen_MASK 0x7e000000
-#define BCHP_SWITCH_ACB_ACB_QUEUE_20_CONFIGURATION_input_is_gisb_pktlen_SHIFT 25
-#define BCHP_SWITCH_ACB_ACB_QUEUE_20_CONFIGURATION_input_is_gisb_pktlen_DEFAULT 0x00000000
-
-/* union - case input_is_acb_queue_20_configuration [30:25] */
-/* SWITCH_ACB :: ACB_QUEUE_20_CONFIGURATION :: input_is_acb_queue_20_configuration :: pktlen [30:25] */
-#define BCHP_SWITCH_ACB_ACB_QUEUE_20_CONFIGURATION_input_is_acb_queue_20_configuration_pktlen_MASK 0x7e000000
-#define BCHP_SWITCH_ACB_ACB_QUEUE_20_CONFIGURATION_input_is_acb_queue_20_configuration_pktlen_SHIFT 25
-#define BCHP_SWITCH_ACB_ACB_QUEUE_20_CONFIGURATION_input_is_acb_queue_20_configuration_pktlen_DEFAULT 0x00000000
-
-/* SWITCH_ACB :: ACB_QUEUE_20_CONFIGURATION :: total_xon_en [24:24] */
-#define BCHP_SWITCH_ACB_ACB_QUEUE_20_CONFIGURATION_total_xon_en_MASK 0x01000000
-#define BCHP_SWITCH_ACB_ACB_QUEUE_20_CONFIGURATION_total_xon_en_SHIFT 24
-#define BCHP_SWITCH_ACB_ACB_QUEUE_20_CONFIGURATION_total_xon_en_DEFAULT 0x00000000
-
-/* SWITCH_ACB :: ACB_QUEUE_20_CONFIGURATION :: total_xoff_en [23:23] */
-#define BCHP_SWITCH_ACB_ACB_QUEUE_20_CONFIGURATION_total_xoff_en_MASK 0x00800000
-#define BCHP_SWITCH_ACB_ACB_QUEUE_20_CONFIGURATION_total_xoff_en_SHIFT 23
-#define BCHP_SWITCH_ACB_ACB_QUEUE_20_CONFIGURATION_total_xoff_en_DEFAULT 0x00000000
-
-/* SWITCH_ACB :: ACB_QUEUE_20_CONFIGURATION :: total_xoff_threshold [22:12] */
-#define BCHP_SWITCH_ACB_ACB_QUEUE_20_CONFIGURATION_total_xoff_threshold_MASK 0x007ff000
-#define BCHP_SWITCH_ACB_ACB_QUEUE_20_CONFIGURATION_total_xoff_threshold_SHIFT 12
-#define BCHP_SWITCH_ACB_ACB_QUEUE_20_CONFIGURATION_total_xoff_threshold_DEFAULT 0x00000000
-
-/* SWITCH_ACB :: ACB_QUEUE_20_CONFIGURATION :: xon_en [11:11] */
-#define BCHP_SWITCH_ACB_ACB_QUEUE_20_CONFIGURATION_xon_en_MASK 0x00000800
-#define BCHP_SWITCH_ACB_ACB_QUEUE_20_CONFIGURATION_xon_en_SHIFT 11
-#define BCHP_SWITCH_ACB_ACB_QUEUE_20_CONFIGURATION_xon_en_DEFAULT 0x00000000
-
-/* SWITCH_ACB :: ACB_QUEUE_20_CONFIGURATION :: xoff_threshold [10:00] */
-#define BCHP_SWITCH_ACB_ACB_QUEUE_20_CONFIGURATION_xoff_threshold_MASK 0x000007ff
-#define BCHP_SWITCH_ACB_ACB_QUEUE_20_CONFIGURATION_xoff_threshold_SHIFT 0
-#define BCHP_SWITCH_ACB_ACB_QUEUE_20_CONFIGURATION_xoff_threshold_DEFAULT 0x00000000
-
-/***************************************************************************
- *ACB_QUEUE_21_CONFIGURATION - ACB Queue 21 Configuration Register
- ***************************************************************************/
-/* SWITCH_ACB :: ACB_QUEUE_21_CONFIGURATION :: pessimistic_mode_en [31:31] */
-#define BCHP_SWITCH_ACB_ACB_QUEUE_21_CONFIGURATION_pessimistic_mode_en_MASK 0x80000000
-#define BCHP_SWITCH_ACB_ACB_QUEUE_21_CONFIGURATION_pessimistic_mode_en_SHIFT 31
-#define BCHP_SWITCH_ACB_ACB_QUEUE_21_CONFIGURATION_pessimistic_mode_en_DEFAULT 0x00000000
-#define BCHP_SWITCH_ACB_ACB_QUEUE_21_CONFIGURATION_pessimistic_mode_en_GISB 1
-#define BCHP_SWITCH_ACB_ACB_QUEUE_21_CONFIGURATION_pessimistic_mode_en_PORT 0
-
-/* union - case input_is_gisb [30:25] */
-/* SWITCH_ACB :: ACB_QUEUE_21_CONFIGURATION :: input_is_gisb :: pktlen [30:25] */
-#define BCHP_SWITCH_ACB_ACB_QUEUE_21_CONFIGURATION_input_is_gisb_pktlen_MASK 0x7e000000
-#define BCHP_SWITCH_ACB_ACB_QUEUE_21_CONFIGURATION_input_is_gisb_pktlen_SHIFT 25
-#define BCHP_SWITCH_ACB_ACB_QUEUE_21_CONFIGURATION_input_is_gisb_pktlen_DEFAULT 0x00000000
-
-/* union - case input_is_acb_queue_21_configuration [30:25] */
-/* SWITCH_ACB :: ACB_QUEUE_21_CONFIGURATION :: input_is_acb_queue_21_configuration :: pktlen [30:25] */
-#define BCHP_SWITCH_ACB_ACB_QUEUE_21_CONFIGURATION_input_is_acb_queue_21_configuration_pktlen_MASK 0x7e000000
-#define BCHP_SWITCH_ACB_ACB_QUEUE_21_CONFIGURATION_input_is_acb_queue_21_configuration_pktlen_SHIFT 25
-#define BCHP_SWITCH_ACB_ACB_QUEUE_21_CONFIGURATION_input_is_acb_queue_21_configuration_pktlen_DEFAULT 0x00000000
-
-/* SWITCH_ACB :: ACB_QUEUE_21_CONFIGURATION :: total_xon_en [24:24] */
-#define BCHP_SWITCH_ACB_ACB_QUEUE_21_CONFIGURATION_total_xon_en_MASK 0x01000000
-#define BCHP_SWITCH_ACB_ACB_QUEUE_21_CONFIGURATION_total_xon_en_SHIFT 24
-#define BCHP_SWITCH_ACB_ACB_QUEUE_21_CONFIGURATION_total_xon_en_DEFAULT 0x00000000
-
-/* SWITCH_ACB :: ACB_QUEUE_21_CONFIGURATION :: total_xoff_en [23:23] */
-#define BCHP_SWITCH_ACB_ACB_QUEUE_21_CONFIGURATION_total_xoff_en_MASK 0x00800000
-#define BCHP_SWITCH_ACB_ACB_QUEUE_21_CONFIGURATION_total_xoff_en_SHIFT 23
-#define BCHP_SWITCH_ACB_ACB_QUEUE_21_CONFIGURATION_total_xoff_en_DEFAULT 0x00000000
-
-/* SWITCH_ACB :: ACB_QUEUE_21_CONFIGURATION :: total_xoff_threshold [22:12] */
-#define BCHP_SWITCH_ACB_ACB_QUEUE_21_CONFIGURATION_total_xoff_threshold_MASK 0x007ff000
-#define BCHP_SWITCH_ACB_ACB_QUEUE_21_CONFIGURATION_total_xoff_threshold_SHIFT 12
-#define BCHP_SWITCH_ACB_ACB_QUEUE_21_CONFIGURATION_total_xoff_threshold_DEFAULT 0x00000000
-
-/* SWITCH_ACB :: ACB_QUEUE_21_CONFIGURATION :: xon_en [11:11] */
-#define BCHP_SWITCH_ACB_ACB_QUEUE_21_CONFIGURATION_xon_en_MASK 0x00000800
-#define BCHP_SWITCH_ACB_ACB_QUEUE_21_CONFIGURATION_xon_en_SHIFT 11
-#define BCHP_SWITCH_ACB_ACB_QUEUE_21_CONFIGURATION_xon_en_DEFAULT 0x00000000
-
-/* SWITCH_ACB :: ACB_QUEUE_21_CONFIGURATION :: xoff_threshold [10:00] */
-#define BCHP_SWITCH_ACB_ACB_QUEUE_21_CONFIGURATION_xoff_threshold_MASK 0x000007ff
-#define BCHP_SWITCH_ACB_ACB_QUEUE_21_CONFIGURATION_xoff_threshold_SHIFT 0
-#define BCHP_SWITCH_ACB_ACB_QUEUE_21_CONFIGURATION_xoff_threshold_DEFAULT 0x00000000
-
-/***************************************************************************
- *ACB_QUEUE_22_CONFIGURATION - ACB Queue 22 Configuration Register
- ***************************************************************************/
-/* SWITCH_ACB :: ACB_QUEUE_22_CONFIGURATION :: pessimistic_mode_en [31:31] */
-#define BCHP_SWITCH_ACB_ACB_QUEUE_22_CONFIGURATION_pessimistic_mode_en_MASK 0x80000000
-#define BCHP_SWITCH_ACB_ACB_QUEUE_22_CONFIGURATION_pessimistic_mode_en_SHIFT 31
-#define BCHP_SWITCH_ACB_ACB_QUEUE_22_CONFIGURATION_pessimistic_mode_en_DEFAULT 0x00000000
-#define BCHP_SWITCH_ACB_ACB_QUEUE_22_CONFIGURATION_pessimistic_mode_en_GISB 1
-#define BCHP_SWITCH_ACB_ACB_QUEUE_22_CONFIGURATION_pessimistic_mode_en_PORT 0
-
-/* union - case input_is_gisb [30:25] */
-/* SWITCH_ACB :: ACB_QUEUE_22_CONFIGURATION :: input_is_gisb :: pktlen [30:25] */
-#define BCHP_SWITCH_ACB_ACB_QUEUE_22_CONFIGURATION_input_is_gisb_pktlen_MASK 0x7e000000
-#define BCHP_SWITCH_ACB_ACB_QUEUE_22_CONFIGURATION_input_is_gisb_pktlen_SHIFT 25
-#define BCHP_SWITCH_ACB_ACB_QUEUE_22_CONFIGURATION_input_is_gisb_pktlen_DEFAULT 0x00000000
-
-/* union - case input_is_acb_queue_22_configuration [30:25] */
-/* SWITCH_ACB :: ACB_QUEUE_22_CONFIGURATION :: input_is_acb_queue_22_configuration :: pktlen [30:25] */
-#define BCHP_SWITCH_ACB_ACB_QUEUE_22_CONFIGURATION_input_is_acb_queue_22_configuration_pktlen_MASK 0x7e000000
-#define BCHP_SWITCH_ACB_ACB_QUEUE_22_CONFIGURATION_input_is_acb_queue_22_configuration_pktlen_SHIFT 25
-#define BCHP_SWITCH_ACB_ACB_QUEUE_22_CONFIGURATION_input_is_acb_queue_22_configuration_pktlen_DEFAULT 0x00000000
-
-/* SWITCH_ACB :: ACB_QUEUE_22_CONFIGURATION :: total_xon_en [24:24] */
-#define BCHP_SWITCH_ACB_ACB_QUEUE_22_CONFIGURATION_total_xon_en_MASK 0x01000000
-#define BCHP_SWITCH_ACB_ACB_QUEUE_22_CONFIGURATION_total_xon_en_SHIFT 24
-#define BCHP_SWITCH_ACB_ACB_QUEUE_22_CONFIGURATION_total_xon_en_DEFAULT 0x00000000
-
-/* SWITCH_ACB :: ACB_QUEUE_22_CONFIGURATION :: total_xoff_en [23:23] */
-#define BCHP_SWITCH_ACB_ACB_QUEUE_22_CONFIGURATION_total_xoff_en_MASK 0x00800000
-#define BCHP_SWITCH_ACB_ACB_QUEUE_22_CONFIGURATION_total_xoff_en_SHIFT 23
-#define BCHP_SWITCH_ACB_ACB_QUEUE_22_CONFIGURATION_total_xoff_en_DEFAULT 0x00000000
-
-/* SWITCH_ACB :: ACB_QUEUE_22_CONFIGURATION :: total_xoff_threshold [22:12] */
-#define BCHP_SWITCH_ACB_ACB_QUEUE_22_CONFIGURATION_total_xoff_threshold_MASK 0x007ff000
-#define BCHP_SWITCH_ACB_ACB_QUEUE_22_CONFIGURATION_total_xoff_threshold_SHIFT 12
-#define BCHP_SWITCH_ACB_ACB_QUEUE_22_CONFIGURATION_total_xoff_threshold_DEFAULT 0x00000000
-
-/* SWITCH_ACB :: ACB_QUEUE_22_CONFIGURATION :: xon_en [11:11] */
-#define BCHP_SWITCH_ACB_ACB_QUEUE_22_CONFIGURATION_xon_en_MASK 0x00000800
-#define BCHP_SWITCH_ACB_ACB_QUEUE_22_CONFIGURATION_xon_en_SHIFT 11
-#define BCHP_SWITCH_ACB_ACB_QUEUE_22_CONFIGURATION_xon_en_DEFAULT 0x00000000
-
-/* SWITCH_ACB :: ACB_QUEUE_22_CONFIGURATION :: xoff_threshold [10:00] */
-#define BCHP_SWITCH_ACB_ACB_QUEUE_22_CONFIGURATION_xoff_threshold_MASK 0x000007ff
-#define BCHP_SWITCH_ACB_ACB_QUEUE_22_CONFIGURATION_xoff_threshold_SHIFT 0
-#define BCHP_SWITCH_ACB_ACB_QUEUE_22_CONFIGURATION_xoff_threshold_DEFAULT 0x00000000
-
-/***************************************************************************
- *ACB_QUEUE_23_CONFIGURATION - ACB Queue 23 Configuration Register
- ***************************************************************************/
-/* SWITCH_ACB :: ACB_QUEUE_23_CONFIGURATION :: pessimistic_mode_en [31:31] */
-#define BCHP_SWITCH_ACB_ACB_QUEUE_23_CONFIGURATION_pessimistic_mode_en_MASK 0x80000000
-#define BCHP_SWITCH_ACB_ACB_QUEUE_23_CONFIGURATION_pessimistic_mode_en_SHIFT 31
-#define BCHP_SWITCH_ACB_ACB_QUEUE_23_CONFIGURATION_pessimistic_mode_en_DEFAULT 0x00000000
-#define BCHP_SWITCH_ACB_ACB_QUEUE_23_CONFIGURATION_pessimistic_mode_en_GISB 1
-#define BCHP_SWITCH_ACB_ACB_QUEUE_23_CONFIGURATION_pessimistic_mode_en_PORT 0
-
-/* union - case input_is_gisb [30:25] */
-/* SWITCH_ACB :: ACB_QUEUE_23_CONFIGURATION :: input_is_gisb :: pktlen [30:25] */
-#define BCHP_SWITCH_ACB_ACB_QUEUE_23_CONFIGURATION_input_is_gisb_pktlen_MASK 0x7e000000
-#define BCHP_SWITCH_ACB_ACB_QUEUE_23_CONFIGURATION_input_is_gisb_pktlen_SHIFT 25
-#define BCHP_SWITCH_ACB_ACB_QUEUE_23_CONFIGURATION_input_is_gisb_pktlen_DEFAULT 0x00000000
-
-/* union - case input_is_acb_queue_23_configuration [30:25] */
-/* SWITCH_ACB :: ACB_QUEUE_23_CONFIGURATION :: input_is_acb_queue_23_configuration :: pktlen [30:25] */
-#define BCHP_SWITCH_ACB_ACB_QUEUE_23_CONFIGURATION_input_is_acb_queue_23_configuration_pktlen_MASK 0x7e000000
-#define BCHP_SWITCH_ACB_ACB_QUEUE_23_CONFIGURATION_input_is_acb_queue_23_configuration_pktlen_SHIFT 25
-#define BCHP_SWITCH_ACB_ACB_QUEUE_23_CONFIGURATION_input_is_acb_queue_23_configuration_pktlen_DEFAULT 0x00000000
-
-/* SWITCH_ACB :: ACB_QUEUE_23_CONFIGURATION :: total_xon_en [24:24] */
-#define BCHP_SWITCH_ACB_ACB_QUEUE_23_CONFIGURATION_total_xon_en_MASK 0x01000000
-#define BCHP_SWITCH_ACB_ACB_QUEUE_23_CONFIGURATION_total_xon_en_SHIFT 24
-#define BCHP_SWITCH_ACB_ACB_QUEUE_23_CONFIGURATION_total_xon_en_DEFAULT 0x00000000
-
-/* SWITCH_ACB :: ACB_QUEUE_23_CONFIGURATION :: total_xoff_en [23:23] */
-#define BCHP_SWITCH_ACB_ACB_QUEUE_23_CONFIGURATION_total_xoff_en_MASK 0x00800000
-#define BCHP_SWITCH_ACB_ACB_QUEUE_23_CONFIGURATION_total_xoff_en_SHIFT 23
-#define BCHP_SWITCH_ACB_ACB_QUEUE_23_CONFIGURATION_total_xoff_en_DEFAULT 0x00000000
-
-/* SWITCH_ACB :: ACB_QUEUE_23_CONFIGURATION :: total_xoff_threshold [22:12] */
-#define BCHP_SWITCH_ACB_ACB_QUEUE_23_CONFIGURATION_total_xoff_threshold_MASK 0x007ff000
-#define BCHP_SWITCH_ACB_ACB_QUEUE_23_CONFIGURATION_total_xoff_threshold_SHIFT 12
-#define BCHP_SWITCH_ACB_ACB_QUEUE_23_CONFIGURATION_total_xoff_threshold_DEFAULT 0x00000000
-
-/* SWITCH_ACB :: ACB_QUEUE_23_CONFIGURATION :: xon_en [11:11] */
-#define BCHP_SWITCH_ACB_ACB_QUEUE_23_CONFIGURATION_xon_en_MASK 0x00000800
-#define BCHP_SWITCH_ACB_ACB_QUEUE_23_CONFIGURATION_xon_en_SHIFT 11
-#define BCHP_SWITCH_ACB_ACB_QUEUE_23_CONFIGURATION_xon_en_DEFAULT 0x00000000
-
-/* SWITCH_ACB :: ACB_QUEUE_23_CONFIGURATION :: xoff_threshold [10:00] */
-#define BCHP_SWITCH_ACB_ACB_QUEUE_23_CONFIGURATION_xoff_threshold_MASK 0x000007ff
-#define BCHP_SWITCH_ACB_ACB_QUEUE_23_CONFIGURATION_xoff_threshold_SHIFT 0
-#define BCHP_SWITCH_ACB_ACB_QUEUE_23_CONFIGURATION_xoff_threshold_DEFAULT 0x00000000
-
-/***************************************************************************
- *ACB_QUEUE_24_CONFIGURATION - ACB Queue 24 Configuration Register6
- ***************************************************************************/
-/* SWITCH_ACB :: ACB_QUEUE_24_CONFIGURATION :: pessimistic_mode_en [31:31] */
-#define BCHP_SWITCH_ACB_ACB_QUEUE_24_CONFIGURATION_pessimistic_mode_en_MASK 0x80000000
-#define BCHP_SWITCH_ACB_ACB_QUEUE_24_CONFIGURATION_pessimistic_mode_en_SHIFT 31
-#define BCHP_SWITCH_ACB_ACB_QUEUE_24_CONFIGURATION_pessimistic_mode_en_DEFAULT 0x00000000
-#define BCHP_SWITCH_ACB_ACB_QUEUE_24_CONFIGURATION_pessimistic_mode_en_GISB 1
-#define BCHP_SWITCH_ACB_ACB_QUEUE_24_CONFIGURATION_pessimistic_mode_en_PORT 0
-
-/* union - case input_is_gisb [30:25] */
-/* SWITCH_ACB :: ACB_QUEUE_24_CONFIGURATION :: input_is_gisb :: pktlen [30:25] */
-#define BCHP_SWITCH_ACB_ACB_QUEUE_24_CONFIGURATION_input_is_gisb_pktlen_MASK 0x7e000000
-#define BCHP_SWITCH_ACB_ACB_QUEUE_24_CONFIGURATION_input_is_gisb_pktlen_SHIFT 25
-#define BCHP_SWITCH_ACB_ACB_QUEUE_24_CONFIGURATION_input_is_gisb_pktlen_DEFAULT 0x00000000
-
-/* union - case input_is_acb_queue_24_configuration [30:25] */
-/* SWITCH_ACB :: ACB_QUEUE_24_CONFIGURATION :: input_is_acb_queue_24_configuration :: pktlen [30:25] */
-#define BCHP_SWITCH_ACB_ACB_QUEUE_24_CONFIGURATION_input_is_acb_queue_24_configuration_pktlen_MASK 0x7e000000
-#define BCHP_SWITCH_ACB_ACB_QUEUE_24_CONFIGURATION_input_is_acb_queue_24_configuration_pktlen_SHIFT 25
-#define BCHP_SWITCH_ACB_ACB_QUEUE_24_CONFIGURATION_input_is_acb_queue_24_configuration_pktlen_DEFAULT 0x00000000
-
-/* SWITCH_ACB :: ACB_QUEUE_24_CONFIGURATION :: total_xon_en [24:24] */
-#define BCHP_SWITCH_ACB_ACB_QUEUE_24_CONFIGURATION_total_xon_en_MASK 0x01000000
-#define BCHP_SWITCH_ACB_ACB_QUEUE_24_CONFIGURATION_total_xon_en_SHIFT 24
-#define BCHP_SWITCH_ACB_ACB_QUEUE_24_CONFIGURATION_total_xon_en_DEFAULT 0x00000000
-
-/* SWITCH_ACB :: ACB_QUEUE_24_CONFIGURATION :: total_xoff_en [23:23] */
-#define BCHP_SWITCH_ACB_ACB_QUEUE_24_CONFIGURATION_total_xoff_en_MASK 0x00800000
-#define BCHP_SWITCH_ACB_ACB_QUEUE_24_CONFIGURATION_total_xoff_en_SHIFT 23
-#define BCHP_SWITCH_ACB_ACB_QUEUE_24_CONFIGURATION_total_xoff_en_DEFAULT 0x00000000
-
-/* SWITCH_ACB :: ACB_QUEUE_24_CONFIGURATION :: total_xoff_threshold [22:12] */
-#define BCHP_SWITCH_ACB_ACB_QUEUE_24_CONFIGURATION_total_xoff_threshold_MASK 0x007ff000
-#define BCHP_SWITCH_ACB_ACB_QUEUE_24_CONFIGURATION_total_xoff_threshold_SHIFT 12
-#define BCHP_SWITCH_ACB_ACB_QUEUE_24_CONFIGURATION_total_xoff_threshold_DEFAULT 0x00000000
-
-/* SWITCH_ACB :: ACB_QUEUE_24_CONFIGURATION :: xon_en [11:11] */
-#define BCHP_SWITCH_ACB_ACB_QUEUE_24_CONFIGURATION_xon_en_MASK 0x00000800
-#define BCHP_SWITCH_ACB_ACB_QUEUE_24_CONFIGURATION_xon_en_SHIFT 11
-#define BCHP_SWITCH_ACB_ACB_QUEUE_24_CONFIGURATION_xon_en_DEFAULT 0x00000000
-
-/* SWITCH_ACB :: ACB_QUEUE_24_CONFIGURATION :: xoff_threshold [10:00] */
-#define BCHP_SWITCH_ACB_ACB_QUEUE_24_CONFIGURATION_xoff_threshold_MASK 0x000007ff
-#define BCHP_SWITCH_ACB_ACB_QUEUE_24_CONFIGURATION_xoff_threshold_SHIFT 0
-#define BCHP_SWITCH_ACB_ACB_QUEUE_24_CONFIGURATION_xoff_threshold_DEFAULT 0x00000000
-
-/***************************************************************************
- *ACB_QUEUE_25_CONFIGURATION - ACB Queue 25 Configuration Register
- ***************************************************************************/
-/* SWITCH_ACB :: ACB_QUEUE_25_CONFIGURATION :: pessimistic_mode_en [31:31] */
-#define BCHP_SWITCH_ACB_ACB_QUEUE_25_CONFIGURATION_pessimistic_mode_en_MASK 0x80000000
-#define BCHP_SWITCH_ACB_ACB_QUEUE_25_CONFIGURATION_pessimistic_mode_en_SHIFT 31
-#define BCHP_SWITCH_ACB_ACB_QUEUE_25_CONFIGURATION_pessimistic_mode_en_DEFAULT 0x00000000
-#define BCHP_SWITCH_ACB_ACB_QUEUE_25_CONFIGURATION_pessimistic_mode_en_GISB 1
-#define BCHP_SWITCH_ACB_ACB_QUEUE_25_CONFIGURATION_pessimistic_mode_en_PORT 0
-
-/* union - case input_is_gisb [30:25] */
-/* SWITCH_ACB :: ACB_QUEUE_25_CONFIGURATION :: input_is_gisb :: pktlen [30:25] */
-#define BCHP_SWITCH_ACB_ACB_QUEUE_25_CONFIGURATION_input_is_gisb_pktlen_MASK 0x7e000000
-#define BCHP_SWITCH_ACB_ACB_QUEUE_25_CONFIGURATION_input_is_gisb_pktlen_SHIFT 25
-#define BCHP_SWITCH_ACB_ACB_QUEUE_25_CONFIGURATION_input_is_gisb_pktlen_DEFAULT 0x00000000
-
-/* union - case input_is_acb_queue_25_configuration [30:25] */
-/* SWITCH_ACB :: ACB_QUEUE_25_CONFIGURATION :: input_is_acb_queue_25_configuration :: pktlen [30:25] */
-#define BCHP_SWITCH_ACB_ACB_QUEUE_25_CONFIGURATION_input_is_acb_queue_25_configuration_pktlen_MASK 0x7e000000
-#define BCHP_SWITCH_ACB_ACB_QUEUE_25_CONFIGURATION_input_is_acb_queue_25_configuration_pktlen_SHIFT 25
-#define BCHP_SWITCH_ACB_ACB_QUEUE_25_CONFIGURATION_input_is_acb_queue_25_configuration_pktlen_DEFAULT 0x00000000
-
-/* SWITCH_ACB :: ACB_QUEUE_25_CONFIGURATION :: total_xon_en [24:24] */
-#define BCHP_SWITCH_ACB_ACB_QUEUE_25_CONFIGURATION_total_xon_en_MASK 0x01000000
-#define BCHP_SWITCH_ACB_ACB_QUEUE_25_CONFIGURATION_total_xon_en_SHIFT 24
-#define BCHP_SWITCH_ACB_ACB_QUEUE_25_CONFIGURATION_total_xon_en_DEFAULT 0x00000000
-
-/* SWITCH_ACB :: ACB_QUEUE_25_CONFIGURATION :: total_xoff_en [23:23] */
-#define BCHP_SWITCH_ACB_ACB_QUEUE_25_CONFIGURATION_total_xoff_en_MASK 0x00800000
-#define BCHP_SWITCH_ACB_ACB_QUEUE_25_CONFIGURATION_total_xoff_en_SHIFT 23
-#define BCHP_SWITCH_ACB_ACB_QUEUE_25_CONFIGURATION_total_xoff_en_DEFAULT 0x00000000
-
-/* SWITCH_ACB :: ACB_QUEUE_25_CONFIGURATION :: total_xoff_threshold [22:12] */
-#define BCHP_SWITCH_ACB_ACB_QUEUE_25_CONFIGURATION_total_xoff_threshold_MASK 0x007ff000
-#define BCHP_SWITCH_ACB_ACB_QUEUE_25_CONFIGURATION_total_xoff_threshold_SHIFT 12
-#define BCHP_SWITCH_ACB_ACB_QUEUE_25_CONFIGURATION_total_xoff_threshold_DEFAULT 0x00000000
-
-/* SWITCH_ACB :: ACB_QUEUE_25_CONFIGURATION :: xon_en [11:11] */
-#define BCHP_SWITCH_ACB_ACB_QUEUE_25_CONFIGURATION_xon_en_MASK 0x00000800
-#define BCHP_SWITCH_ACB_ACB_QUEUE_25_CONFIGURATION_xon_en_SHIFT 11
-#define BCHP_SWITCH_ACB_ACB_QUEUE_25_CONFIGURATION_xon_en_DEFAULT 0x00000000
-
-/* SWITCH_ACB :: ACB_QUEUE_25_CONFIGURATION :: xoff_threshold [10:00] */
-#define BCHP_SWITCH_ACB_ACB_QUEUE_25_CONFIGURATION_xoff_threshold_MASK 0x000007ff
-#define BCHP_SWITCH_ACB_ACB_QUEUE_25_CONFIGURATION_xoff_threshold_SHIFT 0
-#define BCHP_SWITCH_ACB_ACB_QUEUE_25_CONFIGURATION_xoff_threshold_DEFAULT 0x00000000
-
-/***************************************************************************
- *ACB_QUEUE_26_CONFIGURATION - ACB Queue 26 Configuration Register
- ***************************************************************************/
-/* SWITCH_ACB :: ACB_QUEUE_26_CONFIGURATION :: pessimistic_mode_en [31:31] */
-#define BCHP_SWITCH_ACB_ACB_QUEUE_26_CONFIGURATION_pessimistic_mode_en_MASK 0x80000000
-#define BCHP_SWITCH_ACB_ACB_QUEUE_26_CONFIGURATION_pessimistic_mode_en_SHIFT 31
-#define BCHP_SWITCH_ACB_ACB_QUEUE_26_CONFIGURATION_pessimistic_mode_en_DEFAULT 0x00000000
-#define BCHP_SWITCH_ACB_ACB_QUEUE_26_CONFIGURATION_pessimistic_mode_en_GISB 1
-#define BCHP_SWITCH_ACB_ACB_QUEUE_26_CONFIGURATION_pessimistic_mode_en_PORT 0
-
-/* union - case input_is_gisb [30:25] */
-/* SWITCH_ACB :: ACB_QUEUE_26_CONFIGURATION :: input_is_gisb :: pktlen [30:25] */
-#define BCHP_SWITCH_ACB_ACB_QUEUE_26_CONFIGURATION_input_is_gisb_pktlen_MASK 0x7e000000
-#define BCHP_SWITCH_ACB_ACB_QUEUE_26_CONFIGURATION_input_is_gisb_pktlen_SHIFT 25
-#define BCHP_SWITCH_ACB_ACB_QUEUE_26_CONFIGURATION_input_is_gisb_pktlen_DEFAULT 0x00000000
-
-/* union - case input_is_acb_queue_26_configuration [30:25] */
-/* SWITCH_ACB :: ACB_QUEUE_26_CONFIGURATION :: input_is_acb_queue_26_configuration :: pktlen [30:25] */
-#define BCHP_SWITCH_ACB_ACB_QUEUE_26_CONFIGURATION_input_is_acb_queue_26_configuration_pktlen_MASK 0x7e000000
-#define BCHP_SWITCH_ACB_ACB_QUEUE_26_CONFIGURATION_input_is_acb_queue_26_configuration_pktlen_SHIFT 25
-#define BCHP_SWITCH_ACB_ACB_QUEUE_26_CONFIGURATION_input_is_acb_queue_26_configuration_pktlen_DEFAULT 0x00000000
-
-/* SWITCH_ACB :: ACB_QUEUE_26_CONFIGURATION :: total_xon_en [24:24] */
-#define BCHP_SWITCH_ACB_ACB_QUEUE_26_CONFIGURATION_total_xon_en_MASK 0x01000000
-#define BCHP_SWITCH_ACB_ACB_QUEUE_26_CONFIGURATION_total_xon_en_SHIFT 24
-#define BCHP_SWITCH_ACB_ACB_QUEUE_26_CONFIGURATION_total_xon_en_DEFAULT 0x00000000
-
-/* SWITCH_ACB :: ACB_QUEUE_26_CONFIGURATION :: total_xoff_en [23:23] */
-#define BCHP_SWITCH_ACB_ACB_QUEUE_26_CONFIGURATION_total_xoff_en_MASK 0x00800000
-#define BCHP_SWITCH_ACB_ACB_QUEUE_26_CONFIGURATION_total_xoff_en_SHIFT 23
-#define BCHP_SWITCH_ACB_ACB_QUEUE_26_CONFIGURATION_total_xoff_en_DEFAULT 0x00000000
-
-/* SWITCH_ACB :: ACB_QUEUE_26_CONFIGURATION :: total_xoff_threshold [22:12] */
-#define BCHP_SWITCH_ACB_ACB_QUEUE_26_CONFIGURATION_total_xoff_threshold_MASK 0x007ff000
-#define BCHP_SWITCH_ACB_ACB_QUEUE_26_CONFIGURATION_total_xoff_threshold_SHIFT 12
-#define BCHP_SWITCH_ACB_ACB_QUEUE_26_CONFIGURATION_total_xoff_threshold_DEFAULT 0x00000000
-
-/* SWITCH_ACB :: ACB_QUEUE_26_CONFIGURATION :: xon_en [11:11] */
-#define BCHP_SWITCH_ACB_ACB_QUEUE_26_CONFIGURATION_xon_en_MASK 0x00000800
-#define BCHP_SWITCH_ACB_ACB_QUEUE_26_CONFIGURATION_xon_en_SHIFT 11
-#define BCHP_SWITCH_ACB_ACB_QUEUE_26_CONFIGURATION_xon_en_DEFAULT 0x00000000
-
-/* SWITCH_ACB :: ACB_QUEUE_26_CONFIGURATION :: xoff_threshold [10:00] */
-#define BCHP_SWITCH_ACB_ACB_QUEUE_26_CONFIGURATION_xoff_threshold_MASK 0x000007ff
-#define BCHP_SWITCH_ACB_ACB_QUEUE_26_CONFIGURATION_xoff_threshold_SHIFT 0
-#define BCHP_SWITCH_ACB_ACB_QUEUE_26_CONFIGURATION_xoff_threshold_DEFAULT 0x00000000
-
-/***************************************************************************
- *ACB_QUEUE_27_CONFIGURATION - ACB Queue 27 Configuration Register
- ***************************************************************************/
-/* SWITCH_ACB :: ACB_QUEUE_27_CONFIGURATION :: pessimistic_mode_en [31:31] */
-#define BCHP_SWITCH_ACB_ACB_QUEUE_27_CONFIGURATION_pessimistic_mode_en_MASK 0x80000000
-#define BCHP_SWITCH_ACB_ACB_QUEUE_27_CONFIGURATION_pessimistic_mode_en_SHIFT 31
-#define BCHP_SWITCH_ACB_ACB_QUEUE_27_CONFIGURATION_pessimistic_mode_en_DEFAULT 0x00000000
-#define BCHP_SWITCH_ACB_ACB_QUEUE_27_CONFIGURATION_pessimistic_mode_en_GISB 1
-#define BCHP_SWITCH_ACB_ACB_QUEUE_27_CONFIGURATION_pessimistic_mode_en_PORT 0
-
-/* union - case input_is_gisb [30:25] */
-/* SWITCH_ACB :: ACB_QUEUE_27_CONFIGURATION :: input_is_gisb :: pktlen [30:25] */
-#define BCHP_SWITCH_ACB_ACB_QUEUE_27_CONFIGURATION_input_is_gisb_pktlen_MASK 0x7e000000
-#define BCHP_SWITCH_ACB_ACB_QUEUE_27_CONFIGURATION_input_is_gisb_pktlen_SHIFT 25
-#define BCHP_SWITCH_ACB_ACB_QUEUE_27_CONFIGURATION_input_is_gisb_pktlen_DEFAULT 0x00000000
-
-/* union - case input_is_acb_queue_27_configuration [30:25] */
-/* SWITCH_ACB :: ACB_QUEUE_27_CONFIGURATION :: input_is_acb_queue_27_configuration :: pktlen [30:25] */
-#define BCHP_SWITCH_ACB_ACB_QUEUE_27_CONFIGURATION_input_is_acb_queue_27_configuration_pktlen_MASK 0x7e000000
-#define BCHP_SWITCH_ACB_ACB_QUEUE_27_CONFIGURATION_input_is_acb_queue_27_configuration_pktlen_SHIFT 25
-#define BCHP_SWITCH_ACB_ACB_QUEUE_27_CONFIGURATION_input_is_acb_queue_27_configuration_pktlen_DEFAULT 0x00000000
-
-/* SWITCH_ACB :: ACB_QUEUE_27_CONFIGURATION :: total_xon_en [24:24] */
-#define BCHP_SWITCH_ACB_ACB_QUEUE_27_CONFIGURATION_total_xon_en_MASK 0x01000000
-#define BCHP_SWITCH_ACB_ACB_QUEUE_27_CONFIGURATION_total_xon_en_SHIFT 24
-#define BCHP_SWITCH_ACB_ACB_QUEUE_27_CONFIGURATION_total_xon_en_DEFAULT 0x00000000
-
-/* SWITCH_ACB :: ACB_QUEUE_27_CONFIGURATION :: total_xoff_en [23:23] */
-#define BCHP_SWITCH_ACB_ACB_QUEUE_27_CONFIGURATION_total_xoff_en_MASK 0x00800000
-#define BCHP_SWITCH_ACB_ACB_QUEUE_27_CONFIGURATION_total_xoff_en_SHIFT 23
-#define BCHP_SWITCH_ACB_ACB_QUEUE_27_CONFIGURATION_total_xoff_en_DEFAULT 0x00000000
-
-/* SWITCH_ACB :: ACB_QUEUE_27_CONFIGURATION :: total_xoff_threshold [22:12] */
-#define BCHP_SWITCH_ACB_ACB_QUEUE_27_CONFIGURATION_total_xoff_threshold_MASK 0x007ff000
-#define BCHP_SWITCH_ACB_ACB_QUEUE_27_CONFIGURATION_total_xoff_threshold_SHIFT 12
-#define BCHP_SWITCH_ACB_ACB_QUEUE_27_CONFIGURATION_total_xoff_threshold_DEFAULT 0x00000000
-
-/* SWITCH_ACB :: ACB_QUEUE_27_CONFIGURATION :: xon_en [11:11] */
-#define BCHP_SWITCH_ACB_ACB_QUEUE_27_CONFIGURATION_xon_en_MASK 0x00000800
-#define BCHP_SWITCH_ACB_ACB_QUEUE_27_CONFIGURATION_xon_en_SHIFT 11
-#define BCHP_SWITCH_ACB_ACB_QUEUE_27_CONFIGURATION_xon_en_DEFAULT 0x00000000
-
-/* SWITCH_ACB :: ACB_QUEUE_27_CONFIGURATION :: xoff_threshold [10:00] */
-#define BCHP_SWITCH_ACB_ACB_QUEUE_27_CONFIGURATION_xoff_threshold_MASK 0x000007ff
-#define BCHP_SWITCH_ACB_ACB_QUEUE_27_CONFIGURATION_xoff_threshold_SHIFT 0
-#define BCHP_SWITCH_ACB_ACB_QUEUE_27_CONFIGURATION_xoff_threshold_DEFAULT 0x00000000
-
-/***************************************************************************
- *ACB_QUEUE_28_CONFIGURATION - ACB Queue 28 Configuration Register
- ***************************************************************************/
-/* SWITCH_ACB :: ACB_QUEUE_28_CONFIGURATION :: pessimistic_mode_en [31:31] */
-#define BCHP_SWITCH_ACB_ACB_QUEUE_28_CONFIGURATION_pessimistic_mode_en_MASK 0x80000000
-#define BCHP_SWITCH_ACB_ACB_QUEUE_28_CONFIGURATION_pessimistic_mode_en_SHIFT 31
-#define BCHP_SWITCH_ACB_ACB_QUEUE_28_CONFIGURATION_pessimistic_mode_en_DEFAULT 0x00000000
-#define BCHP_SWITCH_ACB_ACB_QUEUE_28_CONFIGURATION_pessimistic_mode_en_GISB 1
-#define BCHP_SWITCH_ACB_ACB_QUEUE_28_CONFIGURATION_pessimistic_mode_en_PORT 0
-
-/* union - case input_is_gisb [30:25] */
-/* SWITCH_ACB :: ACB_QUEUE_28_CONFIGURATION :: input_is_gisb :: pktlen [30:25] */
-#define BCHP_SWITCH_ACB_ACB_QUEUE_28_CONFIGURATION_input_is_gisb_pktlen_MASK 0x7e000000
-#define BCHP_SWITCH_ACB_ACB_QUEUE_28_CONFIGURATION_input_is_gisb_pktlen_SHIFT 25
-#define BCHP_SWITCH_ACB_ACB_QUEUE_28_CONFIGURATION_input_is_gisb_pktlen_DEFAULT 0x00000000
-
-/* union - case input_is_acb_queue_28_configuration [30:25] */
-/* SWITCH_ACB :: ACB_QUEUE_28_CONFIGURATION :: input_is_acb_queue_28_configuration :: pktlen [30:25] */
-#define BCHP_SWITCH_ACB_ACB_QUEUE_28_CONFIGURATION_input_is_acb_queue_28_configuration_pktlen_MASK 0x7e000000
-#define BCHP_SWITCH_ACB_ACB_QUEUE_28_CONFIGURATION_input_is_acb_queue_28_configuration_pktlen_SHIFT 25
-#define BCHP_SWITCH_ACB_ACB_QUEUE_28_CONFIGURATION_input_is_acb_queue_28_configuration_pktlen_DEFAULT 0x00000000
-
-/* SWITCH_ACB :: ACB_QUEUE_28_CONFIGURATION :: total_xon_en [24:24] */
-#define BCHP_SWITCH_ACB_ACB_QUEUE_28_CONFIGURATION_total_xon_en_MASK 0x01000000
-#define BCHP_SWITCH_ACB_ACB_QUEUE_28_CONFIGURATION_total_xon_en_SHIFT 24
-#define BCHP_SWITCH_ACB_ACB_QUEUE_28_CONFIGURATION_total_xon_en_DEFAULT 0x00000000
-
-/* SWITCH_ACB :: ACB_QUEUE_28_CONFIGURATION :: total_xoff_en [23:23] */
-#define BCHP_SWITCH_ACB_ACB_QUEUE_28_CONFIGURATION_total_xoff_en_MASK 0x00800000
-#define BCHP_SWITCH_ACB_ACB_QUEUE_28_CONFIGURATION_total_xoff_en_SHIFT 23
-#define BCHP_SWITCH_ACB_ACB_QUEUE_28_CONFIGURATION_total_xoff_en_DEFAULT 0x00000000
-
-/* SWITCH_ACB :: ACB_QUEUE_28_CONFIGURATION :: total_xoff_threshold [22:12] */
-#define BCHP_SWITCH_ACB_ACB_QUEUE_28_CONFIGURATION_total_xoff_threshold_MASK 0x007ff000
-#define BCHP_SWITCH_ACB_ACB_QUEUE_28_CONFIGURATION_total_xoff_threshold_SHIFT 12
-#define BCHP_SWITCH_ACB_ACB_QUEUE_28_CONFIGURATION_total_xoff_threshold_DEFAULT 0x00000000
-
-/* SWITCH_ACB :: ACB_QUEUE_28_CONFIGURATION :: xon_en [11:11] */
-#define BCHP_SWITCH_ACB_ACB_QUEUE_28_CONFIGURATION_xon_en_MASK 0x00000800
-#define BCHP_SWITCH_ACB_ACB_QUEUE_28_CONFIGURATION_xon_en_SHIFT 11
-#define BCHP_SWITCH_ACB_ACB_QUEUE_28_CONFIGURATION_xon_en_DEFAULT 0x00000000
-
-/* SWITCH_ACB :: ACB_QUEUE_28_CONFIGURATION :: xoff_threshold [10:00] */
-#define BCHP_SWITCH_ACB_ACB_QUEUE_28_CONFIGURATION_xoff_threshold_MASK 0x000007ff
-#define BCHP_SWITCH_ACB_ACB_QUEUE_28_CONFIGURATION_xoff_threshold_SHIFT 0
-#define BCHP_SWITCH_ACB_ACB_QUEUE_28_CONFIGURATION_xoff_threshold_DEFAULT 0x00000000
-
-/***************************************************************************
- *ACB_QUEUE_29_CONFIGURATION - ACB Queue 29 Configuration Register
- ***************************************************************************/
-/* SWITCH_ACB :: ACB_QUEUE_29_CONFIGURATION :: pessimistic_mode_en [31:31] */
-#define BCHP_SWITCH_ACB_ACB_QUEUE_29_CONFIGURATION_pessimistic_mode_en_MASK 0x80000000
-#define BCHP_SWITCH_ACB_ACB_QUEUE_29_CONFIGURATION_pessimistic_mode_en_SHIFT 31
-#define BCHP_SWITCH_ACB_ACB_QUEUE_29_CONFIGURATION_pessimistic_mode_en_DEFAULT 0x00000000
-#define BCHP_SWITCH_ACB_ACB_QUEUE_29_CONFIGURATION_pessimistic_mode_en_GISB 1
-#define BCHP_SWITCH_ACB_ACB_QUEUE_29_CONFIGURATION_pessimistic_mode_en_PORT 0
-
-/* union - case input_is_gisb [30:25] */
-/* SWITCH_ACB :: ACB_QUEUE_29_CONFIGURATION :: input_is_gisb :: pktlen [30:25] */
-#define BCHP_SWITCH_ACB_ACB_QUEUE_29_CONFIGURATION_input_is_gisb_pktlen_MASK 0x7e000000
-#define BCHP_SWITCH_ACB_ACB_QUEUE_29_CONFIGURATION_input_is_gisb_pktlen_SHIFT 25
-#define BCHP_SWITCH_ACB_ACB_QUEUE_29_CONFIGURATION_input_is_gisb_pktlen_DEFAULT 0x00000000
-
-/* union - case input_is_acb_queue_29_configuration [30:25] */
-/* SWITCH_ACB :: ACB_QUEUE_29_CONFIGURATION :: input_is_acb_queue_29_configuration :: pktlen [30:25] */
-#define BCHP_SWITCH_ACB_ACB_QUEUE_29_CONFIGURATION_input_is_acb_queue_29_configuration_pktlen_MASK 0x7e000000
-#define BCHP_SWITCH_ACB_ACB_QUEUE_29_CONFIGURATION_input_is_acb_queue_29_configuration_pktlen_SHIFT 25
-#define BCHP_SWITCH_ACB_ACB_QUEUE_29_CONFIGURATION_input_is_acb_queue_29_configuration_pktlen_DEFAULT 0x00000000
-
-/* SWITCH_ACB :: ACB_QUEUE_29_CONFIGURATION :: total_xon_en [24:24] */
-#define BCHP_SWITCH_ACB_ACB_QUEUE_29_CONFIGURATION_total_xon_en_MASK 0x01000000
-#define BCHP_SWITCH_ACB_ACB_QUEUE_29_CONFIGURATION_total_xon_en_SHIFT 24
-#define BCHP_SWITCH_ACB_ACB_QUEUE_29_CONFIGURATION_total_xon_en_DEFAULT 0x00000000
-
-/* SWITCH_ACB :: ACB_QUEUE_29_CONFIGURATION :: total_xoff_en [23:23] */
-#define BCHP_SWITCH_ACB_ACB_QUEUE_29_CONFIGURATION_total_xoff_en_MASK 0x00800000
-#define BCHP_SWITCH_ACB_ACB_QUEUE_29_CONFIGURATION_total_xoff_en_SHIFT 23
-#define BCHP_SWITCH_ACB_ACB_QUEUE_29_CONFIGURATION_total_xoff_en_DEFAULT 0x00000000
-
-/* SWITCH_ACB :: ACB_QUEUE_29_CONFIGURATION :: total_xoff_threshold [22:12] */
-#define BCHP_SWITCH_ACB_ACB_QUEUE_29_CONFIGURATION_total_xoff_threshold_MASK 0x007ff000
-#define BCHP_SWITCH_ACB_ACB_QUEUE_29_CONFIGURATION_total_xoff_threshold_SHIFT 12
-#define BCHP_SWITCH_ACB_ACB_QUEUE_29_CONFIGURATION_total_xoff_threshold_DEFAULT 0x00000000
-
-/* SWITCH_ACB :: ACB_QUEUE_29_CONFIGURATION :: xon_en [11:11] */
-#define BCHP_SWITCH_ACB_ACB_QUEUE_29_CONFIGURATION_xon_en_MASK 0x00000800
-#define BCHP_SWITCH_ACB_ACB_QUEUE_29_CONFIGURATION_xon_en_SHIFT 11
-#define BCHP_SWITCH_ACB_ACB_QUEUE_29_CONFIGURATION_xon_en_DEFAULT 0x00000000
-
-/* SWITCH_ACB :: ACB_QUEUE_29_CONFIGURATION :: xoff_threshold [10:00] */
-#define BCHP_SWITCH_ACB_ACB_QUEUE_29_CONFIGURATION_xoff_threshold_MASK 0x000007ff
-#define BCHP_SWITCH_ACB_ACB_QUEUE_29_CONFIGURATION_xoff_threshold_SHIFT 0
-#define BCHP_SWITCH_ACB_ACB_QUEUE_29_CONFIGURATION_xoff_threshold_DEFAULT 0x00000000
-
-/***************************************************************************
- *ACB_QUEUE_30_CONFIGURATION - ACB Queue 30 Configuration Register
- ***************************************************************************/
-/* SWITCH_ACB :: ACB_QUEUE_30_CONFIGURATION :: pessimistic_mode_en [31:31] */
-#define BCHP_SWITCH_ACB_ACB_QUEUE_30_CONFIGURATION_pessimistic_mode_en_MASK 0x80000000
-#define BCHP_SWITCH_ACB_ACB_QUEUE_30_CONFIGURATION_pessimistic_mode_en_SHIFT 31
-#define BCHP_SWITCH_ACB_ACB_QUEUE_30_CONFIGURATION_pessimistic_mode_en_DEFAULT 0x00000000
-#define BCHP_SWITCH_ACB_ACB_QUEUE_30_CONFIGURATION_pessimistic_mode_en_GISB 1
-#define BCHP_SWITCH_ACB_ACB_QUEUE_30_CONFIGURATION_pessimistic_mode_en_PORT 0
-
-/* union - case input_is_gisb [30:25] */
-/* SWITCH_ACB :: ACB_QUEUE_30_CONFIGURATION :: input_is_gisb :: pktlen [30:25] */
-#define BCHP_SWITCH_ACB_ACB_QUEUE_30_CONFIGURATION_input_is_gisb_pktlen_MASK 0x7e000000
-#define BCHP_SWITCH_ACB_ACB_QUEUE_30_CONFIGURATION_input_is_gisb_pktlen_SHIFT 25
-#define BCHP_SWITCH_ACB_ACB_QUEUE_30_CONFIGURATION_input_is_gisb_pktlen_DEFAULT 0x00000000
-
-/* union - case input_is_acb_queue_30_configuration [30:25] */
-/* SWITCH_ACB :: ACB_QUEUE_30_CONFIGURATION :: input_is_acb_queue_30_configuration :: pktlen [30:25] */
-#define BCHP_SWITCH_ACB_ACB_QUEUE_30_CONFIGURATION_input_is_acb_queue_30_configuration_pktlen_MASK 0x7e000000
-#define BCHP_SWITCH_ACB_ACB_QUEUE_30_CONFIGURATION_input_is_acb_queue_30_configuration_pktlen_SHIFT 25
-#define BCHP_SWITCH_ACB_ACB_QUEUE_30_CONFIGURATION_input_is_acb_queue_30_configuration_pktlen_DEFAULT 0x00000000
-
-/* SWITCH_ACB :: ACB_QUEUE_30_CONFIGURATION :: total_xon_en [24:24] */
-#define BCHP_SWITCH_ACB_ACB_QUEUE_30_CONFIGURATION_total_xon_en_MASK 0x01000000
-#define BCHP_SWITCH_ACB_ACB_QUEUE_30_CONFIGURATION_total_xon_en_SHIFT 24
-#define BCHP_SWITCH_ACB_ACB_QUEUE_30_CONFIGURATION_total_xon_en_DEFAULT 0x00000000
-
-/* SWITCH_ACB :: ACB_QUEUE_30_CONFIGURATION :: total_xoff_en [23:23] */
-#define BCHP_SWITCH_ACB_ACB_QUEUE_30_CONFIGURATION_total_xoff_en_MASK 0x00800000
-#define BCHP_SWITCH_ACB_ACB_QUEUE_30_CONFIGURATION_total_xoff_en_SHIFT 23
-#define BCHP_SWITCH_ACB_ACB_QUEUE_30_CONFIGURATION_total_xoff_en_DEFAULT 0x00000000
-
-/* SWITCH_ACB :: ACB_QUEUE_30_CONFIGURATION :: total_xoff_threshold [22:12] */
-#define BCHP_SWITCH_ACB_ACB_QUEUE_30_CONFIGURATION_total_xoff_threshold_MASK 0x007ff000
-#define BCHP_SWITCH_ACB_ACB_QUEUE_30_CONFIGURATION_total_xoff_threshold_SHIFT 12
-#define BCHP_SWITCH_ACB_ACB_QUEUE_30_CONFIGURATION_total_xoff_threshold_DEFAULT 0x00000000
-
-/* SWITCH_ACB :: ACB_QUEUE_30_CONFIGURATION :: xon_en [11:11] */
-#define BCHP_SWITCH_ACB_ACB_QUEUE_30_CONFIGURATION_xon_en_MASK 0x00000800
-#define BCHP_SWITCH_ACB_ACB_QUEUE_30_CONFIGURATION_xon_en_SHIFT 11
-#define BCHP_SWITCH_ACB_ACB_QUEUE_30_CONFIGURATION_xon_en_DEFAULT 0x00000000
-
-/* SWITCH_ACB :: ACB_QUEUE_30_CONFIGURATION :: xoff_threshold [10:00] */
-#define BCHP_SWITCH_ACB_ACB_QUEUE_30_CONFIGURATION_xoff_threshold_MASK 0x000007ff
-#define BCHP_SWITCH_ACB_ACB_QUEUE_30_CONFIGURATION_xoff_threshold_SHIFT 0
-#define BCHP_SWITCH_ACB_ACB_QUEUE_30_CONFIGURATION_xoff_threshold_DEFAULT 0x00000000
-
-/***************************************************************************
- *ACB_QUEUE_31_CONFIGURATION - ACB Queue 31 Configuration Register
- ***************************************************************************/
-/* SWITCH_ACB :: ACB_QUEUE_31_CONFIGURATION :: pessimistic_mode_en [31:31] */
-#define BCHP_SWITCH_ACB_ACB_QUEUE_31_CONFIGURATION_pessimistic_mode_en_MASK 0x80000000
-#define BCHP_SWITCH_ACB_ACB_QUEUE_31_CONFIGURATION_pessimistic_mode_en_SHIFT 31
-#define BCHP_SWITCH_ACB_ACB_QUEUE_31_CONFIGURATION_pessimistic_mode_en_DEFAULT 0x00000000
-#define BCHP_SWITCH_ACB_ACB_QUEUE_31_CONFIGURATION_pessimistic_mode_en_GISB 1
-#define BCHP_SWITCH_ACB_ACB_QUEUE_31_CONFIGURATION_pessimistic_mode_en_PORT 0
-
-/* union - case input_is_gisb [30:25] */
-/* SWITCH_ACB :: ACB_QUEUE_31_CONFIGURATION :: input_is_gisb :: pktlen [30:25] */
-#define BCHP_SWITCH_ACB_ACB_QUEUE_31_CONFIGURATION_input_is_gisb_pktlen_MASK 0x7e000000
-#define BCHP_SWITCH_ACB_ACB_QUEUE_31_CONFIGURATION_input_is_gisb_pktlen_SHIFT 25
-#define BCHP_SWITCH_ACB_ACB_QUEUE_31_CONFIGURATION_input_is_gisb_pktlen_DEFAULT 0x00000000
-
-/* union - case input_is_acb_queue_31_configuration [30:25] */
-/* SWITCH_ACB :: ACB_QUEUE_31_CONFIGURATION :: input_is_acb_queue_31_configuration :: pktlen [30:25] */
-#define BCHP_SWITCH_ACB_ACB_QUEUE_31_CONFIGURATION_input_is_acb_queue_31_configuration_pktlen_MASK 0x7e000000
-#define BCHP_SWITCH_ACB_ACB_QUEUE_31_CONFIGURATION_input_is_acb_queue_31_configuration_pktlen_SHIFT 25
-#define BCHP_SWITCH_ACB_ACB_QUEUE_31_CONFIGURATION_input_is_acb_queue_31_configuration_pktlen_DEFAULT 0x00000000
-
-/* SWITCH_ACB :: ACB_QUEUE_31_CONFIGURATION :: total_xon_en [24:24] */
-#define BCHP_SWITCH_ACB_ACB_QUEUE_31_CONFIGURATION_total_xon_en_MASK 0x01000000
-#define BCHP_SWITCH_ACB_ACB_QUEUE_31_CONFIGURATION_total_xon_en_SHIFT 24
-#define BCHP_SWITCH_ACB_ACB_QUEUE_31_CONFIGURATION_total_xon_en_DEFAULT 0x00000000
-
-/* SWITCH_ACB :: ACB_QUEUE_31_CONFIGURATION :: total_xoff_en [23:23] */
-#define BCHP_SWITCH_ACB_ACB_QUEUE_31_CONFIGURATION_total_xoff_en_MASK 0x00800000
-#define BCHP_SWITCH_ACB_ACB_QUEUE_31_CONFIGURATION_total_xoff_en_SHIFT 23
-#define BCHP_SWITCH_ACB_ACB_QUEUE_31_CONFIGURATION_total_xoff_en_DEFAULT 0x00000000
-
-/* SWITCH_ACB :: ACB_QUEUE_31_CONFIGURATION :: total_xoff_threshold [22:12] */
-#define BCHP_SWITCH_ACB_ACB_QUEUE_31_CONFIGURATION_total_xoff_threshold_MASK 0x007ff000
-#define BCHP_SWITCH_ACB_ACB_QUEUE_31_CONFIGURATION_total_xoff_threshold_SHIFT 12
-#define BCHP_SWITCH_ACB_ACB_QUEUE_31_CONFIGURATION_total_xoff_threshold_DEFAULT 0x00000000
-
-/* SWITCH_ACB :: ACB_QUEUE_31_CONFIGURATION :: xon_en [11:11] */
-#define BCHP_SWITCH_ACB_ACB_QUEUE_31_CONFIGURATION_xon_en_MASK 0x00000800
-#define BCHP_SWITCH_ACB_ACB_QUEUE_31_CONFIGURATION_xon_en_SHIFT 11
-#define BCHP_SWITCH_ACB_ACB_QUEUE_31_CONFIGURATION_xon_en_DEFAULT 0x00000000
-
-/* SWITCH_ACB :: ACB_QUEUE_31_CONFIGURATION :: xoff_threshold [10:00] */
-#define BCHP_SWITCH_ACB_ACB_QUEUE_31_CONFIGURATION_xoff_threshold_MASK 0x000007ff
-#define BCHP_SWITCH_ACB_ACB_QUEUE_31_CONFIGURATION_xoff_threshold_SHIFT 0
-#define BCHP_SWITCH_ACB_ACB_QUEUE_31_CONFIGURATION_xoff_threshold_DEFAULT 0x00000000
-
-/***************************************************************************
- *ACB_QUEUE_32_CONFIGURATION - ACB Queue 32 Configuration Register
- ***************************************************************************/
-/* SWITCH_ACB :: ACB_QUEUE_32_CONFIGURATION :: pessimistic_mode_en [31:31] */
-#define BCHP_SWITCH_ACB_ACB_QUEUE_32_CONFIGURATION_pessimistic_mode_en_MASK 0x80000000
-#define BCHP_SWITCH_ACB_ACB_QUEUE_32_CONFIGURATION_pessimistic_mode_en_SHIFT 31
-#define BCHP_SWITCH_ACB_ACB_QUEUE_32_CONFIGURATION_pessimistic_mode_en_DEFAULT 0x00000000
-#define BCHP_SWITCH_ACB_ACB_QUEUE_32_CONFIGURATION_pessimistic_mode_en_GISB 1
-#define BCHP_SWITCH_ACB_ACB_QUEUE_32_CONFIGURATION_pessimistic_mode_en_PORT 0
-
-/* union - case input_is_gisb [30:25] */
-/* SWITCH_ACB :: ACB_QUEUE_32_CONFIGURATION :: input_is_gisb :: pktlen [30:25] */
-#define BCHP_SWITCH_ACB_ACB_QUEUE_32_CONFIGURATION_input_is_gisb_pktlen_MASK 0x7e000000
-#define BCHP_SWITCH_ACB_ACB_QUEUE_32_CONFIGURATION_input_is_gisb_pktlen_SHIFT 25
-#define BCHP_SWITCH_ACB_ACB_QUEUE_32_CONFIGURATION_input_is_gisb_pktlen_DEFAULT 0x00000000
-
-/* union - case input_is_acb_queue_32_configuration [30:25] */
-/* SWITCH_ACB :: ACB_QUEUE_32_CONFIGURATION :: input_is_acb_queue_32_configuration :: pktlen [30:25] */
-#define BCHP_SWITCH_ACB_ACB_QUEUE_32_CONFIGURATION_input_is_acb_queue_32_configuration_pktlen_MASK 0x7e000000
-#define BCHP_SWITCH_ACB_ACB_QUEUE_32_CONFIGURATION_input_is_acb_queue_32_configuration_pktlen_SHIFT 25
-#define BCHP_SWITCH_ACB_ACB_QUEUE_32_CONFIGURATION_input_is_acb_queue_32_configuration_pktlen_DEFAULT 0x00000000
-
-/* SWITCH_ACB :: ACB_QUEUE_32_CONFIGURATION :: total_xon_en [24:24] */
-#define BCHP_SWITCH_ACB_ACB_QUEUE_32_CONFIGURATION_total_xon_en_MASK 0x01000000
-#define BCHP_SWITCH_ACB_ACB_QUEUE_32_CONFIGURATION_total_xon_en_SHIFT 24
-#define BCHP_SWITCH_ACB_ACB_QUEUE_32_CONFIGURATION_total_xon_en_DEFAULT 0x00000000
-
-/* SWITCH_ACB :: ACB_QUEUE_32_CONFIGURATION :: total_xoff_en [23:23] */
-#define BCHP_SWITCH_ACB_ACB_QUEUE_32_CONFIGURATION_total_xoff_en_MASK 0x00800000
-#define BCHP_SWITCH_ACB_ACB_QUEUE_32_CONFIGURATION_total_xoff_en_SHIFT 23
-#define BCHP_SWITCH_ACB_ACB_QUEUE_32_CONFIGURATION_total_xoff_en_DEFAULT 0x00000000
-
-/* SWITCH_ACB :: ACB_QUEUE_32_CONFIGURATION :: total_xoff_threshold [22:12] */
-#define BCHP_SWITCH_ACB_ACB_QUEUE_32_CONFIGURATION_total_xoff_threshold_MASK 0x007ff000
-#define BCHP_SWITCH_ACB_ACB_QUEUE_32_CONFIGURATION_total_xoff_threshold_SHIFT 12
-#define BCHP_SWITCH_ACB_ACB_QUEUE_32_CONFIGURATION_total_xoff_threshold_DEFAULT 0x00000000
-
-/* SWITCH_ACB :: ACB_QUEUE_32_CONFIGURATION :: xon_en [11:11] */
-#define BCHP_SWITCH_ACB_ACB_QUEUE_32_CONFIGURATION_xon_en_MASK 0x00000800
-#define BCHP_SWITCH_ACB_ACB_QUEUE_32_CONFIGURATION_xon_en_SHIFT 11
-#define BCHP_SWITCH_ACB_ACB_QUEUE_32_CONFIGURATION_xon_en_DEFAULT 0x00000000
-
-/* SWITCH_ACB :: ACB_QUEUE_32_CONFIGURATION :: xoff_threshold [10:00] */
-#define BCHP_SWITCH_ACB_ACB_QUEUE_32_CONFIGURATION_xoff_threshold_MASK 0x000007ff
-#define BCHP_SWITCH_ACB_ACB_QUEUE_32_CONFIGURATION_xoff_threshold_SHIFT 0
-#define BCHP_SWITCH_ACB_ACB_QUEUE_32_CONFIGURATION_xoff_threshold_DEFAULT 0x00000000
-
-/***************************************************************************
- *ACB_QUEUE_33_CONFIGURATION - ACB Queue 33 Configuration Register
- ***************************************************************************/
-/* SWITCH_ACB :: ACB_QUEUE_33_CONFIGURATION :: pessimistic_mode_en [31:31] */
-#define BCHP_SWITCH_ACB_ACB_QUEUE_33_CONFIGURATION_pessimistic_mode_en_MASK 0x80000000
-#define BCHP_SWITCH_ACB_ACB_QUEUE_33_CONFIGURATION_pessimistic_mode_en_SHIFT 31
-#define BCHP_SWITCH_ACB_ACB_QUEUE_33_CONFIGURATION_pessimistic_mode_en_DEFAULT 0x00000000
-#define BCHP_SWITCH_ACB_ACB_QUEUE_33_CONFIGURATION_pessimistic_mode_en_GISB 1
-#define BCHP_SWITCH_ACB_ACB_QUEUE_33_CONFIGURATION_pessimistic_mode_en_PORT 0
-
-/* union - case input_is_gisb [30:25] */
-/* SWITCH_ACB :: ACB_QUEUE_33_CONFIGURATION :: input_is_gisb :: pktlen [30:25] */
-#define BCHP_SWITCH_ACB_ACB_QUEUE_33_CONFIGURATION_input_is_gisb_pktlen_MASK 0x7e000000
-#define BCHP_SWITCH_ACB_ACB_QUEUE_33_CONFIGURATION_input_is_gisb_pktlen_SHIFT 25
-#define BCHP_SWITCH_ACB_ACB_QUEUE_33_CONFIGURATION_input_is_gisb_pktlen_DEFAULT 0x00000000
-
-/* union - case input_is_acb_queue_33_configuration [30:25] */
-/* SWITCH_ACB :: ACB_QUEUE_33_CONFIGURATION :: input_is_acb_queue_33_configuration :: pktlen [30:25] */
-#define BCHP_SWITCH_ACB_ACB_QUEUE_33_CONFIGURATION_input_is_acb_queue_33_configuration_pktlen_MASK 0x7e000000
-#define BCHP_SWITCH_ACB_ACB_QUEUE_33_CONFIGURATION_input_is_acb_queue_33_configuration_pktlen_SHIFT 25
-#define BCHP_SWITCH_ACB_ACB_QUEUE_33_CONFIGURATION_input_is_acb_queue_33_configuration_pktlen_DEFAULT 0x00000000
-
-/* SWITCH_ACB :: ACB_QUEUE_33_CONFIGURATION :: total_xon_en [24:24] */
-#define BCHP_SWITCH_ACB_ACB_QUEUE_33_CONFIGURATION_total_xon_en_MASK 0x01000000
-#define BCHP_SWITCH_ACB_ACB_QUEUE_33_CONFIGURATION_total_xon_en_SHIFT 24
-#define BCHP_SWITCH_ACB_ACB_QUEUE_33_CONFIGURATION_total_xon_en_DEFAULT 0x00000000
-
-/* SWITCH_ACB :: ACB_QUEUE_33_CONFIGURATION :: total_xoff_en [23:23] */
-#define BCHP_SWITCH_ACB_ACB_QUEUE_33_CONFIGURATION_total_xoff_en_MASK 0x00800000
-#define BCHP_SWITCH_ACB_ACB_QUEUE_33_CONFIGURATION_total_xoff_en_SHIFT 23
-#define BCHP_SWITCH_ACB_ACB_QUEUE_33_CONFIGURATION_total_xoff_en_DEFAULT 0x00000000
-
-/* SWITCH_ACB :: ACB_QUEUE_33_CONFIGURATION :: total_xoff_threshold [22:12] */
-#define BCHP_SWITCH_ACB_ACB_QUEUE_33_CONFIGURATION_total_xoff_threshold_MASK 0x007ff000
-#define BCHP_SWITCH_ACB_ACB_QUEUE_33_CONFIGURATION_total_xoff_threshold_SHIFT 12
-#define BCHP_SWITCH_ACB_ACB_QUEUE_33_CONFIGURATION_total_xoff_threshold_DEFAULT 0x00000000
-
-/* SWITCH_ACB :: ACB_QUEUE_33_CONFIGURATION :: xon_en [11:11] */
-#define BCHP_SWITCH_ACB_ACB_QUEUE_33_CONFIGURATION_xon_en_MASK 0x00000800
-#define BCHP_SWITCH_ACB_ACB_QUEUE_33_CONFIGURATION_xon_en_SHIFT 11
-#define BCHP_SWITCH_ACB_ACB_QUEUE_33_CONFIGURATION_xon_en_DEFAULT 0x00000000
-
-/* SWITCH_ACB :: ACB_QUEUE_33_CONFIGURATION :: xoff_threshold [10:00] */
-#define BCHP_SWITCH_ACB_ACB_QUEUE_33_CONFIGURATION_xoff_threshold_MASK 0x000007ff
-#define BCHP_SWITCH_ACB_ACB_QUEUE_33_CONFIGURATION_xoff_threshold_SHIFT 0
-#define BCHP_SWITCH_ACB_ACB_QUEUE_33_CONFIGURATION_xoff_threshold_DEFAULT 0x00000000
-
-/***************************************************************************
- *ACB_QUEUE_34_CONFIGURATION - ACB Queue 34 Configuration Register
- ***************************************************************************/
-/* SWITCH_ACB :: ACB_QUEUE_34_CONFIGURATION :: pessimistic_mode_en [31:31] */
-#define BCHP_SWITCH_ACB_ACB_QUEUE_34_CONFIGURATION_pessimistic_mode_en_MASK 0x80000000
-#define BCHP_SWITCH_ACB_ACB_QUEUE_34_CONFIGURATION_pessimistic_mode_en_SHIFT 31
-#define BCHP_SWITCH_ACB_ACB_QUEUE_34_CONFIGURATION_pessimistic_mode_en_DEFAULT 0x00000000
-#define BCHP_SWITCH_ACB_ACB_QUEUE_34_CONFIGURATION_pessimistic_mode_en_GISB 1
-#define BCHP_SWITCH_ACB_ACB_QUEUE_34_CONFIGURATION_pessimistic_mode_en_PORT 0
-
-/* union - case input_is_gisb [30:25] */
-/* SWITCH_ACB :: ACB_QUEUE_34_CONFIGURATION :: input_is_gisb :: pktlen [30:25] */
-#define BCHP_SWITCH_ACB_ACB_QUEUE_34_CONFIGURATION_input_is_gisb_pktlen_MASK 0x7e000000
-#define BCHP_SWITCH_ACB_ACB_QUEUE_34_CONFIGURATION_input_is_gisb_pktlen_SHIFT 25
-#define BCHP_SWITCH_ACB_ACB_QUEUE_34_CONFIGURATION_input_is_gisb_pktlen_DEFAULT 0x00000000
-
-/* union - case input_is_acb_queue_34_configuration [30:25] */
-/* SWITCH_ACB :: ACB_QUEUE_34_CONFIGURATION :: input_is_acb_queue_34_configuration :: pktlen [30:25] */
-#define BCHP_SWITCH_ACB_ACB_QUEUE_34_CONFIGURATION_input_is_acb_queue_34_configuration_pktlen_MASK 0x7e000000
-#define BCHP_SWITCH_ACB_ACB_QUEUE_34_CONFIGURATION_input_is_acb_queue_34_configuration_pktlen_SHIFT 25
-#define BCHP_SWITCH_ACB_ACB_QUEUE_34_CONFIGURATION_input_is_acb_queue_34_configuration_pktlen_DEFAULT 0x00000000
-
-/* SWITCH_ACB :: ACB_QUEUE_34_CONFIGURATION :: total_xon_en [24:24] */
-#define BCHP_SWITCH_ACB_ACB_QUEUE_34_CONFIGURATION_total_xon_en_MASK 0x01000000
-#define BCHP_SWITCH_ACB_ACB_QUEUE_34_CONFIGURATION_total_xon_en_SHIFT 24
-#define BCHP_SWITCH_ACB_ACB_QUEUE_34_CONFIGURATION_total_xon_en_DEFAULT 0x00000000
-
-/* SWITCH_ACB :: ACB_QUEUE_34_CONFIGURATION :: total_xoff_en [23:23] */
-#define BCHP_SWITCH_ACB_ACB_QUEUE_34_CONFIGURATION_total_xoff_en_MASK 0x00800000
-#define BCHP_SWITCH_ACB_ACB_QUEUE_34_CONFIGURATION_total_xoff_en_SHIFT 23
-#define BCHP_SWITCH_ACB_ACB_QUEUE_34_CONFIGURATION_total_xoff_en_DEFAULT 0x00000000
-
-/* SWITCH_ACB :: ACB_QUEUE_34_CONFIGURATION :: total_xoff_threshold [22:12] */
-#define BCHP_SWITCH_ACB_ACB_QUEUE_34_CONFIGURATION_total_xoff_threshold_MASK 0x007ff000
-#define BCHP_SWITCH_ACB_ACB_QUEUE_34_CONFIGURATION_total_xoff_threshold_SHIFT 12
-#define BCHP_SWITCH_ACB_ACB_QUEUE_34_CONFIGURATION_total_xoff_threshold_DEFAULT 0x00000000
-
-/* SWITCH_ACB :: ACB_QUEUE_34_CONFIGURATION :: xon_en [11:11] */
-#define BCHP_SWITCH_ACB_ACB_QUEUE_34_CONFIGURATION_xon_en_MASK 0x00000800
-#define BCHP_SWITCH_ACB_ACB_QUEUE_34_CONFIGURATION_xon_en_SHIFT 11
-#define BCHP_SWITCH_ACB_ACB_QUEUE_34_CONFIGURATION_xon_en_DEFAULT 0x00000000
-
-/* SWITCH_ACB :: ACB_QUEUE_34_CONFIGURATION :: xoff_threshold [10:00] */
-#define BCHP_SWITCH_ACB_ACB_QUEUE_34_CONFIGURATION_xoff_threshold_MASK 0x000007ff
-#define BCHP_SWITCH_ACB_ACB_QUEUE_34_CONFIGURATION_xoff_threshold_SHIFT 0
-#define BCHP_SWITCH_ACB_ACB_QUEUE_34_CONFIGURATION_xoff_threshold_DEFAULT 0x00000000
-
-/***************************************************************************
- *ACB_QUEUE_35_CONFIGURATION - ACB Queue 35 Configuration Register
- ***************************************************************************/
-/* SWITCH_ACB :: ACB_QUEUE_35_CONFIGURATION :: pessimistic_mode_en [31:31] */
-#define BCHP_SWITCH_ACB_ACB_QUEUE_35_CONFIGURATION_pessimistic_mode_en_MASK 0x80000000
-#define BCHP_SWITCH_ACB_ACB_QUEUE_35_CONFIGURATION_pessimistic_mode_en_SHIFT 31
-#define BCHP_SWITCH_ACB_ACB_QUEUE_35_CONFIGURATION_pessimistic_mode_en_DEFAULT 0x00000000
-#define BCHP_SWITCH_ACB_ACB_QUEUE_35_CONFIGURATION_pessimistic_mode_en_GISB 1
-#define BCHP_SWITCH_ACB_ACB_QUEUE_35_CONFIGURATION_pessimistic_mode_en_PORT 0
-
-/* union - case input_is_gisb [30:25] */
-/* SWITCH_ACB :: ACB_QUEUE_35_CONFIGURATION :: input_is_gisb :: pktlen [30:25] */
-#define BCHP_SWITCH_ACB_ACB_QUEUE_35_CONFIGURATION_input_is_gisb_pktlen_MASK 0x7e000000
-#define BCHP_SWITCH_ACB_ACB_QUEUE_35_CONFIGURATION_input_is_gisb_pktlen_SHIFT 25
-#define BCHP_SWITCH_ACB_ACB_QUEUE_35_CONFIGURATION_input_is_gisb_pktlen_DEFAULT 0x00000000
-
-/* union - case input_is_acb_queue_35_configuration [30:25] */
-/* SWITCH_ACB :: ACB_QUEUE_35_CONFIGURATION :: input_is_acb_queue_35_configuration :: pktlen [30:25] */
-#define BCHP_SWITCH_ACB_ACB_QUEUE_35_CONFIGURATION_input_is_acb_queue_35_configuration_pktlen_MASK 0x7e000000
-#define BCHP_SWITCH_ACB_ACB_QUEUE_35_CONFIGURATION_input_is_acb_queue_35_configuration_pktlen_SHIFT 25
-#define BCHP_SWITCH_ACB_ACB_QUEUE_35_CONFIGURATION_input_is_acb_queue_35_configuration_pktlen_DEFAULT 0x00000000
-
-/* SWITCH_ACB :: ACB_QUEUE_35_CONFIGURATION :: total_xon_en [24:24] */
-#define BCHP_SWITCH_ACB_ACB_QUEUE_35_CONFIGURATION_total_xon_en_MASK 0x01000000
-#define BCHP_SWITCH_ACB_ACB_QUEUE_35_CONFIGURATION_total_xon_en_SHIFT 24
-#define BCHP_SWITCH_ACB_ACB_QUEUE_35_CONFIGURATION_total_xon_en_DEFAULT 0x00000000
-
-/* SWITCH_ACB :: ACB_QUEUE_35_CONFIGURATION :: total_xoff_en [23:23] */
-#define BCHP_SWITCH_ACB_ACB_QUEUE_35_CONFIGURATION_total_xoff_en_MASK 0x00800000
-#define BCHP_SWITCH_ACB_ACB_QUEUE_35_CONFIGURATION_total_xoff_en_SHIFT 23
-#define BCHP_SWITCH_ACB_ACB_QUEUE_35_CONFIGURATION_total_xoff_en_DEFAULT 0x00000000
-
-/* SWITCH_ACB :: ACB_QUEUE_35_CONFIGURATION :: total_xoff_threshold [22:12] */
-#define BCHP_SWITCH_ACB_ACB_QUEUE_35_CONFIGURATION_total_xoff_threshold_MASK 0x007ff000
-#define BCHP_SWITCH_ACB_ACB_QUEUE_35_CONFIGURATION_total_xoff_threshold_SHIFT 12
-#define BCHP_SWITCH_ACB_ACB_QUEUE_35_CONFIGURATION_total_xoff_threshold_DEFAULT 0x00000000
-
-/* SWITCH_ACB :: ACB_QUEUE_35_CONFIGURATION :: xon_en [11:11] */
-#define BCHP_SWITCH_ACB_ACB_QUEUE_35_CONFIGURATION_xon_en_MASK 0x00000800
-#define BCHP_SWITCH_ACB_ACB_QUEUE_35_CONFIGURATION_xon_en_SHIFT 11
-#define BCHP_SWITCH_ACB_ACB_QUEUE_35_CONFIGURATION_xon_en_DEFAULT 0x00000000
-
-/* SWITCH_ACB :: ACB_QUEUE_35_CONFIGURATION :: xoff_threshold [10:00] */
-#define BCHP_SWITCH_ACB_ACB_QUEUE_35_CONFIGURATION_xoff_threshold_MASK 0x000007ff
-#define BCHP_SWITCH_ACB_ACB_QUEUE_35_CONFIGURATION_xoff_threshold_SHIFT 0
-#define BCHP_SWITCH_ACB_ACB_QUEUE_35_CONFIGURATION_xoff_threshold_DEFAULT 0x00000000
-
-/***************************************************************************
- *ACB_QUEUE_36_CONFIGURATION - ACB Queue 36 Configuration Register
- ***************************************************************************/
-/* SWITCH_ACB :: ACB_QUEUE_36_CONFIGURATION :: pessimistic_mode_en [31:31] */
-#define BCHP_SWITCH_ACB_ACB_QUEUE_36_CONFIGURATION_pessimistic_mode_en_MASK 0x80000000
-#define BCHP_SWITCH_ACB_ACB_QUEUE_36_CONFIGURATION_pessimistic_mode_en_SHIFT 31
-#define BCHP_SWITCH_ACB_ACB_QUEUE_36_CONFIGURATION_pessimistic_mode_en_DEFAULT 0x00000000
-#define BCHP_SWITCH_ACB_ACB_QUEUE_36_CONFIGURATION_pessimistic_mode_en_GISB 1
-#define BCHP_SWITCH_ACB_ACB_QUEUE_36_CONFIGURATION_pessimistic_mode_en_PORT 0
-
-/* union - case input_is_gisb [30:25] */
-/* SWITCH_ACB :: ACB_QUEUE_36_CONFIGURATION :: input_is_gisb :: pktlen [30:25] */
-#define BCHP_SWITCH_ACB_ACB_QUEUE_36_CONFIGURATION_input_is_gisb_pktlen_MASK 0x7e000000
-#define BCHP_SWITCH_ACB_ACB_QUEUE_36_CONFIGURATION_input_is_gisb_pktlen_SHIFT 25
-#define BCHP_SWITCH_ACB_ACB_QUEUE_36_CONFIGURATION_input_is_gisb_pktlen_DEFAULT 0x00000000
-
-/* union - case input_is_acb_queue_36_configuration [30:25] */
-/* SWITCH_ACB :: ACB_QUEUE_36_CONFIGURATION :: input_is_acb_queue_36_configuration :: pktlen [30:25] */
-#define BCHP_SWITCH_ACB_ACB_QUEUE_36_CONFIGURATION_input_is_acb_queue_36_configuration_pktlen_MASK 0x7e000000
-#define BCHP_SWITCH_ACB_ACB_QUEUE_36_CONFIGURATION_input_is_acb_queue_36_configuration_pktlen_SHIFT 25
-#define BCHP_SWITCH_ACB_ACB_QUEUE_36_CONFIGURATION_input_is_acb_queue_36_configuration_pktlen_DEFAULT 0x00000000
-
-/* SWITCH_ACB :: ACB_QUEUE_36_CONFIGURATION :: total_xon_en [24:24] */
-#define BCHP_SWITCH_ACB_ACB_QUEUE_36_CONFIGURATION_total_xon_en_MASK 0x01000000
-#define BCHP_SWITCH_ACB_ACB_QUEUE_36_CONFIGURATION_total_xon_en_SHIFT 24
-#define BCHP_SWITCH_ACB_ACB_QUEUE_36_CONFIGURATION_total_xon_en_DEFAULT 0x00000000
-
-/* SWITCH_ACB :: ACB_QUEUE_36_CONFIGURATION :: total_xoff_en [23:23] */
-#define BCHP_SWITCH_ACB_ACB_QUEUE_36_CONFIGURATION_total_xoff_en_MASK 0x00800000
-#define BCHP_SWITCH_ACB_ACB_QUEUE_36_CONFIGURATION_total_xoff_en_SHIFT 23
-#define BCHP_SWITCH_ACB_ACB_QUEUE_36_CONFIGURATION_total_xoff_en_DEFAULT 0x00000000
-
-/* SWITCH_ACB :: ACB_QUEUE_36_CONFIGURATION :: total_xoff_threshold [22:12] */
-#define BCHP_SWITCH_ACB_ACB_QUEUE_36_CONFIGURATION_total_xoff_threshold_MASK 0x007ff000
-#define BCHP_SWITCH_ACB_ACB_QUEUE_36_CONFIGURATION_total_xoff_threshold_SHIFT 12
-#define BCHP_SWITCH_ACB_ACB_QUEUE_36_CONFIGURATION_total_xoff_threshold_DEFAULT 0x00000000
-
-/* SWITCH_ACB :: ACB_QUEUE_36_CONFIGURATION :: xon_en [11:11] */
-#define BCHP_SWITCH_ACB_ACB_QUEUE_36_CONFIGURATION_xon_en_MASK 0x00000800
-#define BCHP_SWITCH_ACB_ACB_QUEUE_36_CONFIGURATION_xon_en_SHIFT 11
-#define BCHP_SWITCH_ACB_ACB_QUEUE_36_CONFIGURATION_xon_en_DEFAULT 0x00000000
-
-/* SWITCH_ACB :: ACB_QUEUE_36_CONFIGURATION :: xoff_threshold [10:00] */
-#define BCHP_SWITCH_ACB_ACB_QUEUE_36_CONFIGURATION_xoff_threshold_MASK 0x000007ff
-#define BCHP_SWITCH_ACB_ACB_QUEUE_36_CONFIGURATION_xoff_threshold_SHIFT 0
-#define BCHP_SWITCH_ACB_ACB_QUEUE_36_CONFIGURATION_xoff_threshold_DEFAULT 0x00000000
-
-/***************************************************************************
- *ACB_QUEUE_37_CONFIGURATION - ACB Queue 37 Configuration Register
- ***************************************************************************/
-/* SWITCH_ACB :: ACB_QUEUE_37_CONFIGURATION :: pessimistic_mode_en [31:31] */
-#define BCHP_SWITCH_ACB_ACB_QUEUE_37_CONFIGURATION_pessimistic_mode_en_MASK 0x80000000
-#define BCHP_SWITCH_ACB_ACB_QUEUE_37_CONFIGURATION_pessimistic_mode_en_SHIFT 31
-#define BCHP_SWITCH_ACB_ACB_QUEUE_37_CONFIGURATION_pessimistic_mode_en_DEFAULT 0x00000000
-#define BCHP_SWITCH_ACB_ACB_QUEUE_37_CONFIGURATION_pessimistic_mode_en_GISB 1
-#define BCHP_SWITCH_ACB_ACB_QUEUE_37_CONFIGURATION_pessimistic_mode_en_PORT 0
-
-/* union - case input_is_gisb [30:25] */
-/* SWITCH_ACB :: ACB_QUEUE_37_CONFIGURATION :: input_is_gisb :: pktlen [30:25] */
-#define BCHP_SWITCH_ACB_ACB_QUEUE_37_CONFIGURATION_input_is_gisb_pktlen_MASK 0x7e000000
-#define BCHP_SWITCH_ACB_ACB_QUEUE_37_CONFIGURATION_input_is_gisb_pktlen_SHIFT 25
-#define BCHP_SWITCH_ACB_ACB_QUEUE_37_CONFIGURATION_input_is_gisb_pktlen_DEFAULT 0x00000000
-
-/* union - case input_is_acb_queue_37_configuration [30:25] */
-/* SWITCH_ACB :: ACB_QUEUE_37_CONFIGURATION :: input_is_acb_queue_37_configuration :: pktlen [30:25] */
-#define BCHP_SWITCH_ACB_ACB_QUEUE_37_CONFIGURATION_input_is_acb_queue_37_configuration_pktlen_MASK 0x7e000000
-#define BCHP_SWITCH_ACB_ACB_QUEUE_37_CONFIGURATION_input_is_acb_queue_37_configuration_pktlen_SHIFT 25
-#define BCHP_SWITCH_ACB_ACB_QUEUE_37_CONFIGURATION_input_is_acb_queue_37_configuration_pktlen_DEFAULT 0x00000000
-
-/* SWITCH_ACB :: ACB_QUEUE_37_CONFIGURATION :: total_xon_en [24:24] */
-#define BCHP_SWITCH_ACB_ACB_QUEUE_37_CONFIGURATION_total_xon_en_MASK 0x01000000
-#define BCHP_SWITCH_ACB_ACB_QUEUE_37_CONFIGURATION_total_xon_en_SHIFT 24
-#define BCHP_SWITCH_ACB_ACB_QUEUE_37_CONFIGURATION_total_xon_en_DEFAULT 0x00000000
-
-/* SWITCH_ACB :: ACB_QUEUE_37_CONFIGURATION :: total_xoff_en [23:23] */
-#define BCHP_SWITCH_ACB_ACB_QUEUE_37_CONFIGURATION_total_xoff_en_MASK 0x00800000
-#define BCHP_SWITCH_ACB_ACB_QUEUE_37_CONFIGURATION_total_xoff_en_SHIFT 23
-#define BCHP_SWITCH_ACB_ACB_QUEUE_37_CONFIGURATION_total_xoff_en_DEFAULT 0x00000000
-
-/* SWITCH_ACB :: ACB_QUEUE_37_CONFIGURATION :: total_xoff_threshold [22:12] */
-#define BCHP_SWITCH_ACB_ACB_QUEUE_37_CONFIGURATION_total_xoff_threshold_MASK 0x007ff000
-#define BCHP_SWITCH_ACB_ACB_QUEUE_37_CONFIGURATION_total_xoff_threshold_SHIFT 12
-#define BCHP_SWITCH_ACB_ACB_QUEUE_37_CONFIGURATION_total_xoff_threshold_DEFAULT 0x00000000
-
-/* SWITCH_ACB :: ACB_QUEUE_37_CONFIGURATION :: xon_en [11:11] */
-#define BCHP_SWITCH_ACB_ACB_QUEUE_37_CONFIGURATION_xon_en_MASK 0x00000800
-#define BCHP_SWITCH_ACB_ACB_QUEUE_37_CONFIGURATION_xon_en_SHIFT 11
-#define BCHP_SWITCH_ACB_ACB_QUEUE_37_CONFIGURATION_xon_en_DEFAULT 0x00000000
-
-/* SWITCH_ACB :: ACB_QUEUE_37_CONFIGURATION :: xoff_threshold [10:00] */
-#define BCHP_SWITCH_ACB_ACB_QUEUE_37_CONFIGURATION_xoff_threshold_MASK 0x000007ff
-#define BCHP_SWITCH_ACB_ACB_QUEUE_37_CONFIGURATION_xoff_threshold_SHIFT 0
-#define BCHP_SWITCH_ACB_ACB_QUEUE_37_CONFIGURATION_xoff_threshold_DEFAULT 0x00000000
-
-/***************************************************************************
- *ACB_QUEUE_38_CONFIGURATION - ACB Queue 38 Configuration Register
- ***************************************************************************/
-/* SWITCH_ACB :: ACB_QUEUE_38_CONFIGURATION :: pessimistic_mode_en [31:31] */
-#define BCHP_SWITCH_ACB_ACB_QUEUE_38_CONFIGURATION_pessimistic_mode_en_MASK 0x80000000
-#define BCHP_SWITCH_ACB_ACB_QUEUE_38_CONFIGURATION_pessimistic_mode_en_SHIFT 31
-#define BCHP_SWITCH_ACB_ACB_QUEUE_38_CONFIGURATION_pessimistic_mode_en_DEFAULT 0x00000000
-#define BCHP_SWITCH_ACB_ACB_QUEUE_38_CONFIGURATION_pessimistic_mode_en_GISB 1
-#define BCHP_SWITCH_ACB_ACB_QUEUE_38_CONFIGURATION_pessimistic_mode_en_PORT 0
-
-/* union - case input_is_gisb [30:25] */
-/* SWITCH_ACB :: ACB_QUEUE_38_CONFIGURATION :: input_is_gisb :: pktlen [30:25] */
-#define BCHP_SWITCH_ACB_ACB_QUEUE_38_CONFIGURATION_input_is_gisb_pktlen_MASK 0x7e000000
-#define BCHP_SWITCH_ACB_ACB_QUEUE_38_CONFIGURATION_input_is_gisb_pktlen_SHIFT 25
-#define BCHP_SWITCH_ACB_ACB_QUEUE_38_CONFIGURATION_input_is_gisb_pktlen_DEFAULT 0x00000000
-
-/* union - case input_is_acb_queue_38_configuration [30:25] */
-/* SWITCH_ACB :: ACB_QUEUE_38_CONFIGURATION :: input_is_acb_queue_38_configuration :: pktlen [30:25] */
-#define BCHP_SWITCH_ACB_ACB_QUEUE_38_CONFIGURATION_input_is_acb_queue_38_configuration_pktlen_MASK 0x7e000000
-#define BCHP_SWITCH_ACB_ACB_QUEUE_38_CONFIGURATION_input_is_acb_queue_38_configuration_pktlen_SHIFT 25
-#define BCHP_SWITCH_ACB_ACB_QUEUE_38_CONFIGURATION_input_is_acb_queue_38_configuration_pktlen_DEFAULT 0x00000000
-
-/* SWITCH_ACB :: ACB_QUEUE_38_CONFIGURATION :: total_xon_en [24:24] */
-#define BCHP_SWITCH_ACB_ACB_QUEUE_38_CONFIGURATION_total_xon_en_MASK 0x01000000
-#define BCHP_SWITCH_ACB_ACB_QUEUE_38_CONFIGURATION_total_xon_en_SHIFT 24
-#define BCHP_SWITCH_ACB_ACB_QUEUE_38_CONFIGURATION_total_xon_en_DEFAULT 0x00000000
-
-/* SWITCH_ACB :: ACB_QUEUE_38_CONFIGURATION :: total_xoff_en [23:23] */
-#define BCHP_SWITCH_ACB_ACB_QUEUE_38_CONFIGURATION_total_xoff_en_MASK 0x00800000
-#define BCHP_SWITCH_ACB_ACB_QUEUE_38_CONFIGURATION_total_xoff_en_SHIFT 23
-#define BCHP_SWITCH_ACB_ACB_QUEUE_38_CONFIGURATION_total_xoff_en_DEFAULT 0x00000000
-
-/* SWITCH_ACB :: ACB_QUEUE_38_CONFIGURATION :: total_xoff_threshold [22:12] */
-#define BCHP_SWITCH_ACB_ACB_QUEUE_38_CONFIGURATION_total_xoff_threshold_MASK 0x007ff000
-#define BCHP_SWITCH_ACB_ACB_QUEUE_38_CONFIGURATION_total_xoff_threshold_SHIFT 12
-#define BCHP_SWITCH_ACB_ACB_QUEUE_38_CONFIGURATION_total_xoff_threshold_DEFAULT 0x00000000
-
-/* SWITCH_ACB :: ACB_QUEUE_38_CONFIGURATION :: xon_en [11:11] */
-#define BCHP_SWITCH_ACB_ACB_QUEUE_38_CONFIGURATION_xon_en_MASK 0x00000800
-#define BCHP_SWITCH_ACB_ACB_QUEUE_38_CONFIGURATION_xon_en_SHIFT 11
-#define BCHP_SWITCH_ACB_ACB_QUEUE_38_CONFIGURATION_xon_en_DEFAULT 0x00000000
-
-/* SWITCH_ACB :: ACB_QUEUE_38_CONFIGURATION :: xoff_threshold [10:00] */
-#define BCHP_SWITCH_ACB_ACB_QUEUE_38_CONFIGURATION_xoff_threshold_MASK 0x000007ff
-#define BCHP_SWITCH_ACB_ACB_QUEUE_38_CONFIGURATION_xoff_threshold_SHIFT 0
-#define BCHP_SWITCH_ACB_ACB_QUEUE_38_CONFIGURATION_xoff_threshold_DEFAULT 0x00000000
-
-/***************************************************************************
- *ACB_QUEUE_39_CONFIGURATION - ACB Queue 39 Configuration Register
- ***************************************************************************/
-/* SWITCH_ACB :: ACB_QUEUE_39_CONFIGURATION :: pessimistic_mode_en [31:31] */
-#define BCHP_SWITCH_ACB_ACB_QUEUE_39_CONFIGURATION_pessimistic_mode_en_MASK 0x80000000
-#define BCHP_SWITCH_ACB_ACB_QUEUE_39_CONFIGURATION_pessimistic_mode_en_SHIFT 31
-#define BCHP_SWITCH_ACB_ACB_QUEUE_39_CONFIGURATION_pessimistic_mode_en_DEFAULT 0x00000000
-#define BCHP_SWITCH_ACB_ACB_QUEUE_39_CONFIGURATION_pessimistic_mode_en_GISB 1
-#define BCHP_SWITCH_ACB_ACB_QUEUE_39_CONFIGURATION_pessimistic_mode_en_PORT 0
-
-/* union - case input_is_gisb [30:25] */
-/* SWITCH_ACB :: ACB_QUEUE_39_CONFIGURATION :: input_is_gisb :: pktlen [30:25] */
-#define BCHP_SWITCH_ACB_ACB_QUEUE_39_CONFIGURATION_input_is_gisb_pktlen_MASK 0x7e000000
-#define BCHP_SWITCH_ACB_ACB_QUEUE_39_CONFIGURATION_input_is_gisb_pktlen_SHIFT 25
-#define BCHP_SWITCH_ACB_ACB_QUEUE_39_CONFIGURATION_input_is_gisb_pktlen_DEFAULT 0x00000000
-
-/* union - case input_is_acb_queue_39_configuration [30:25] */
-/* SWITCH_ACB :: ACB_QUEUE_39_CONFIGURATION :: input_is_acb_queue_39_configuration :: pktlen [30:25] */
-#define BCHP_SWITCH_ACB_ACB_QUEUE_39_CONFIGURATION_input_is_acb_queue_39_configuration_pktlen_MASK 0x7e000000
-#define BCHP_SWITCH_ACB_ACB_QUEUE_39_CONFIGURATION_input_is_acb_queue_39_configuration_pktlen_SHIFT 25
-#define BCHP_SWITCH_ACB_ACB_QUEUE_39_CONFIGURATION_input_is_acb_queue_39_configuration_pktlen_DEFAULT 0x00000000
-
-/* SWITCH_ACB :: ACB_QUEUE_39_CONFIGURATION :: total_xon_en [24:24] */
-#define BCHP_SWITCH_ACB_ACB_QUEUE_39_CONFIGURATION_total_xon_en_MASK 0x01000000
-#define BCHP_SWITCH_ACB_ACB_QUEUE_39_CONFIGURATION_total_xon_en_SHIFT 24
-#define BCHP_SWITCH_ACB_ACB_QUEUE_39_CONFIGURATION_total_xon_en_DEFAULT 0x00000000
-
-/* SWITCH_ACB :: ACB_QUEUE_39_CONFIGURATION :: total_xoff_en [23:23] */
-#define BCHP_SWITCH_ACB_ACB_QUEUE_39_CONFIGURATION_total_xoff_en_MASK 0x00800000
-#define BCHP_SWITCH_ACB_ACB_QUEUE_39_CONFIGURATION_total_xoff_en_SHIFT 23
-#define BCHP_SWITCH_ACB_ACB_QUEUE_39_CONFIGURATION_total_xoff_en_DEFAULT 0x00000000
-
-/* SWITCH_ACB :: ACB_QUEUE_39_CONFIGURATION :: total_xoff_threshold [22:12] */
-#define BCHP_SWITCH_ACB_ACB_QUEUE_39_CONFIGURATION_total_xoff_threshold_MASK 0x007ff000
-#define BCHP_SWITCH_ACB_ACB_QUEUE_39_CONFIGURATION_total_xoff_threshold_SHIFT 12
-#define BCHP_SWITCH_ACB_ACB_QUEUE_39_CONFIGURATION_total_xoff_threshold_DEFAULT 0x00000000
-
-/* SWITCH_ACB :: ACB_QUEUE_39_CONFIGURATION :: xon_en [11:11] */
-#define BCHP_SWITCH_ACB_ACB_QUEUE_39_CONFIGURATION_xon_en_MASK 0x00000800
-#define BCHP_SWITCH_ACB_ACB_QUEUE_39_CONFIGURATION_xon_en_SHIFT 11
-#define BCHP_SWITCH_ACB_ACB_QUEUE_39_CONFIGURATION_xon_en_DEFAULT 0x00000000
-
-/* SWITCH_ACB :: ACB_QUEUE_39_CONFIGURATION :: xoff_threshold [10:00] */
-#define BCHP_SWITCH_ACB_ACB_QUEUE_39_CONFIGURATION_xoff_threshold_MASK 0x000007ff
-#define BCHP_SWITCH_ACB_ACB_QUEUE_39_CONFIGURATION_xoff_threshold_SHIFT 0
-#define BCHP_SWITCH_ACB_ACB_QUEUE_39_CONFIGURATION_xoff_threshold_DEFAULT 0x00000000
-
-/***************************************************************************
- *ACB_QUEUE_40_CONFIGURATION - ACB Queue 40 Configuration Register
- ***************************************************************************/
-/* SWITCH_ACB :: ACB_QUEUE_40_CONFIGURATION :: pessimistic_mode_en [31:31] */
-#define BCHP_SWITCH_ACB_ACB_QUEUE_40_CONFIGURATION_pessimistic_mode_en_MASK 0x80000000
-#define BCHP_SWITCH_ACB_ACB_QUEUE_40_CONFIGURATION_pessimistic_mode_en_SHIFT 31
-#define BCHP_SWITCH_ACB_ACB_QUEUE_40_CONFIGURATION_pessimistic_mode_en_DEFAULT 0x00000000
-#define BCHP_SWITCH_ACB_ACB_QUEUE_40_CONFIGURATION_pessimistic_mode_en_GISB 1
-#define BCHP_SWITCH_ACB_ACB_QUEUE_40_CONFIGURATION_pessimistic_mode_en_PORT 0
-
-/* union - case input_is_gisb [30:25] */
-/* SWITCH_ACB :: ACB_QUEUE_40_CONFIGURATION :: input_is_gisb :: pktlen [30:25] */
-#define BCHP_SWITCH_ACB_ACB_QUEUE_40_CONFIGURATION_input_is_gisb_pktlen_MASK 0x7e000000
-#define BCHP_SWITCH_ACB_ACB_QUEUE_40_CONFIGURATION_input_is_gisb_pktlen_SHIFT 25
-#define BCHP_SWITCH_ACB_ACB_QUEUE_40_CONFIGURATION_input_is_gisb_pktlen_DEFAULT 0x00000000
-
-/* union - case input_is_acb_queue_40_configuration [30:25] */
-/* SWITCH_ACB :: ACB_QUEUE_40_CONFIGURATION :: input_is_acb_queue_40_configuration :: pktlen [30:25] */
-#define BCHP_SWITCH_ACB_ACB_QUEUE_40_CONFIGURATION_input_is_acb_queue_40_configuration_pktlen_MASK 0x7e000000
-#define BCHP_SWITCH_ACB_ACB_QUEUE_40_CONFIGURATION_input_is_acb_queue_40_configuration_pktlen_SHIFT 25
-#define BCHP_SWITCH_ACB_ACB_QUEUE_40_CONFIGURATION_input_is_acb_queue_40_configuration_pktlen_DEFAULT 0x00000000
-
-/* SWITCH_ACB :: ACB_QUEUE_40_CONFIGURATION :: total_xon_en [24:24] */
-#define BCHP_SWITCH_ACB_ACB_QUEUE_40_CONFIGURATION_total_xon_en_MASK 0x01000000
-#define BCHP_SWITCH_ACB_ACB_QUEUE_40_CONFIGURATION_total_xon_en_SHIFT 24
-#define BCHP_SWITCH_ACB_ACB_QUEUE_40_CONFIGURATION_total_xon_en_DEFAULT 0x00000000
-
-/* SWITCH_ACB :: ACB_QUEUE_40_CONFIGURATION :: total_xoff_en [23:23] */
-#define BCHP_SWITCH_ACB_ACB_QUEUE_40_CONFIGURATION_total_xoff_en_MASK 0x00800000
-#define BCHP_SWITCH_ACB_ACB_QUEUE_40_CONFIGURATION_total_xoff_en_SHIFT 23
-#define BCHP_SWITCH_ACB_ACB_QUEUE_40_CONFIGURATION_total_xoff_en_DEFAULT 0x00000000
-
-/* SWITCH_ACB :: ACB_QUEUE_40_CONFIGURATION :: total_xoff_threshold [22:12] */
-#define BCHP_SWITCH_ACB_ACB_QUEUE_40_CONFIGURATION_total_xoff_threshold_MASK 0x007ff000
-#define BCHP_SWITCH_ACB_ACB_QUEUE_40_CONFIGURATION_total_xoff_threshold_SHIFT 12
-#define BCHP_SWITCH_ACB_ACB_QUEUE_40_CONFIGURATION_total_xoff_threshold_DEFAULT 0x00000000
-
-/* SWITCH_ACB :: ACB_QUEUE_40_CONFIGURATION :: xon_en [11:11] */
-#define BCHP_SWITCH_ACB_ACB_QUEUE_40_CONFIGURATION_xon_en_MASK 0x00000800
-#define BCHP_SWITCH_ACB_ACB_QUEUE_40_CONFIGURATION_xon_en_SHIFT 11
-#define BCHP_SWITCH_ACB_ACB_QUEUE_40_CONFIGURATION_xon_en_DEFAULT 0x00000000
-
-/* SWITCH_ACB :: ACB_QUEUE_40_CONFIGURATION :: xoff_threshold [10:00] */
-#define BCHP_SWITCH_ACB_ACB_QUEUE_40_CONFIGURATION_xoff_threshold_MASK 0x000007ff
-#define BCHP_SWITCH_ACB_ACB_QUEUE_40_CONFIGURATION_xoff_threshold_SHIFT 0
-#define BCHP_SWITCH_ACB_ACB_QUEUE_40_CONFIGURATION_xoff_threshold_DEFAULT 0x00000000
-
-/***************************************************************************
- *ACB_QUEUE_41_CONFIGURATION - ACB Queue 41 Configuration Register
- ***************************************************************************/
-/* SWITCH_ACB :: ACB_QUEUE_41_CONFIGURATION :: pessimistic_mode_en [31:31] */
-#define BCHP_SWITCH_ACB_ACB_QUEUE_41_CONFIGURATION_pessimistic_mode_en_MASK 0x80000000
-#define BCHP_SWITCH_ACB_ACB_QUEUE_41_CONFIGURATION_pessimistic_mode_en_SHIFT 31
-#define BCHP_SWITCH_ACB_ACB_QUEUE_41_CONFIGURATION_pessimistic_mode_en_DEFAULT 0x00000000
-#define BCHP_SWITCH_ACB_ACB_QUEUE_41_CONFIGURATION_pessimistic_mode_en_GISB 1
-#define BCHP_SWITCH_ACB_ACB_QUEUE_41_CONFIGURATION_pessimistic_mode_en_PORT 0
-
-/* union - case input_is_gisb [30:25] */
-/* SWITCH_ACB :: ACB_QUEUE_41_CONFIGURATION :: input_is_gisb :: pktlen [30:25] */
-#define BCHP_SWITCH_ACB_ACB_QUEUE_41_CONFIGURATION_input_is_gisb_pktlen_MASK 0x7e000000
-#define BCHP_SWITCH_ACB_ACB_QUEUE_41_CONFIGURATION_input_is_gisb_pktlen_SHIFT 25
-#define BCHP_SWITCH_ACB_ACB_QUEUE_41_CONFIGURATION_input_is_gisb_pktlen_DEFAULT 0x00000000
-
-/* union - case input_is_acb_queue_41_configuration [30:25] */
-/* SWITCH_ACB :: ACB_QUEUE_41_CONFIGURATION :: input_is_acb_queue_41_configuration :: pktlen [30:25] */
-#define BCHP_SWITCH_ACB_ACB_QUEUE_41_CONFIGURATION_input_is_acb_queue_41_configuration_pktlen_MASK 0x7e000000
-#define BCHP_SWITCH_ACB_ACB_QUEUE_41_CONFIGURATION_input_is_acb_queue_41_configuration_pktlen_SHIFT 25
-#define BCHP_SWITCH_ACB_ACB_QUEUE_41_CONFIGURATION_input_is_acb_queue_41_configuration_pktlen_DEFAULT 0x00000000
-
-/* SWITCH_ACB :: ACB_QUEUE_41_CONFIGURATION :: total_xon_en [24:24] */
-#define BCHP_SWITCH_ACB_ACB_QUEUE_41_CONFIGURATION_total_xon_en_MASK 0x01000000
-#define BCHP_SWITCH_ACB_ACB_QUEUE_41_CONFIGURATION_total_xon_en_SHIFT 24
-#define BCHP_SWITCH_ACB_ACB_QUEUE_41_CONFIGURATION_total_xon_en_DEFAULT 0x00000000
-
-/* SWITCH_ACB :: ACB_QUEUE_41_CONFIGURATION :: total_xoff_en [23:23] */
-#define BCHP_SWITCH_ACB_ACB_QUEUE_41_CONFIGURATION_total_xoff_en_MASK 0x00800000
-#define BCHP_SWITCH_ACB_ACB_QUEUE_41_CONFIGURATION_total_xoff_en_SHIFT 23
-#define BCHP_SWITCH_ACB_ACB_QUEUE_41_CONFIGURATION_total_xoff_en_DEFAULT 0x00000000
-
-/* SWITCH_ACB :: ACB_QUEUE_41_CONFIGURATION :: total_xoff_threshold [22:12] */
-#define BCHP_SWITCH_ACB_ACB_QUEUE_41_CONFIGURATION_total_xoff_threshold_MASK 0x007ff000
-#define BCHP_SWITCH_ACB_ACB_QUEUE_41_CONFIGURATION_total_xoff_threshold_SHIFT 12
-#define BCHP_SWITCH_ACB_ACB_QUEUE_41_CONFIGURATION_total_xoff_threshold_DEFAULT 0x00000000
-
-/* SWITCH_ACB :: ACB_QUEUE_41_CONFIGURATION :: xon_en [11:11] */
-#define BCHP_SWITCH_ACB_ACB_QUEUE_41_CONFIGURATION_xon_en_MASK 0x00000800
-#define BCHP_SWITCH_ACB_ACB_QUEUE_41_CONFIGURATION_xon_en_SHIFT 11
-#define BCHP_SWITCH_ACB_ACB_QUEUE_41_CONFIGURATION_xon_en_DEFAULT 0x00000000
-
-/* SWITCH_ACB :: ACB_QUEUE_41_CONFIGURATION :: xoff_threshold [10:00] */
-#define BCHP_SWITCH_ACB_ACB_QUEUE_41_CONFIGURATION_xoff_threshold_MASK 0x000007ff
-#define BCHP_SWITCH_ACB_ACB_QUEUE_41_CONFIGURATION_xoff_threshold_SHIFT 0
-#define BCHP_SWITCH_ACB_ACB_QUEUE_41_CONFIGURATION_xoff_threshold_DEFAULT 0x00000000
-
-/***************************************************************************
- *ACB_QUEUE_42_CONFIGURATION - ACB Queue 42 Configuration Register
- ***************************************************************************/
-/* SWITCH_ACB :: ACB_QUEUE_42_CONFIGURATION :: pessimistic_mode_en [31:31] */
-#define BCHP_SWITCH_ACB_ACB_QUEUE_42_CONFIGURATION_pessimistic_mode_en_MASK 0x80000000
-#define BCHP_SWITCH_ACB_ACB_QUEUE_42_CONFIGURATION_pessimistic_mode_en_SHIFT 31
-#define BCHP_SWITCH_ACB_ACB_QUEUE_42_CONFIGURATION_pessimistic_mode_en_DEFAULT 0x00000000
-#define BCHP_SWITCH_ACB_ACB_QUEUE_42_CONFIGURATION_pessimistic_mode_en_GISB 1
-#define BCHP_SWITCH_ACB_ACB_QUEUE_42_CONFIGURATION_pessimistic_mode_en_PORT 0
-
-/* union - case input_is_gisb [30:25] */
-/* SWITCH_ACB :: ACB_QUEUE_42_CONFIGURATION :: input_is_gisb :: pktlen [30:25] */
-#define BCHP_SWITCH_ACB_ACB_QUEUE_42_CONFIGURATION_input_is_gisb_pktlen_MASK 0x7e000000
-#define BCHP_SWITCH_ACB_ACB_QUEUE_42_CONFIGURATION_input_is_gisb_pktlen_SHIFT 25
-#define BCHP_SWITCH_ACB_ACB_QUEUE_42_CONFIGURATION_input_is_gisb_pktlen_DEFAULT 0x00000000
-
-/* union - case input_is_acb_queue_42_configuration [30:25] */
-/* SWITCH_ACB :: ACB_QUEUE_42_CONFIGURATION :: input_is_acb_queue_42_configuration :: pktlen [30:25] */
-#define BCHP_SWITCH_ACB_ACB_QUEUE_42_CONFIGURATION_input_is_acb_queue_42_configuration_pktlen_MASK 0x7e000000
-#define BCHP_SWITCH_ACB_ACB_QUEUE_42_CONFIGURATION_input_is_acb_queue_42_configuration_pktlen_SHIFT 25
-#define BCHP_SWITCH_ACB_ACB_QUEUE_42_CONFIGURATION_input_is_acb_queue_42_configuration_pktlen_DEFAULT 0x00000000
-
-/* SWITCH_ACB :: ACB_QUEUE_42_CONFIGURATION :: total_xon_en [24:24] */
-#define BCHP_SWITCH_ACB_ACB_QUEUE_42_CONFIGURATION_total_xon_en_MASK 0x01000000
-#define BCHP_SWITCH_ACB_ACB_QUEUE_42_CONFIGURATION_total_xon_en_SHIFT 24
-#define BCHP_SWITCH_ACB_ACB_QUEUE_42_CONFIGURATION_total_xon_en_DEFAULT 0x00000000
-
-/* SWITCH_ACB :: ACB_QUEUE_42_CONFIGURATION :: total_xoff_en [23:23] */
-#define BCHP_SWITCH_ACB_ACB_QUEUE_42_CONFIGURATION_total_xoff_en_MASK 0x00800000
-#define BCHP_SWITCH_ACB_ACB_QUEUE_42_CONFIGURATION_total_xoff_en_SHIFT 23
-#define BCHP_SWITCH_ACB_ACB_QUEUE_42_CONFIGURATION_total_xoff_en_DEFAULT 0x00000000
-
-/* SWITCH_ACB :: ACB_QUEUE_42_CONFIGURATION :: total_xoff_threshold [22:12] */
-#define BCHP_SWITCH_ACB_ACB_QUEUE_42_CONFIGURATION_total_xoff_threshold_MASK 0x007ff000
-#define BCHP_SWITCH_ACB_ACB_QUEUE_42_CONFIGURATION_total_xoff_threshold_SHIFT 12
-#define BCHP_SWITCH_ACB_ACB_QUEUE_42_CONFIGURATION_total_xoff_threshold_DEFAULT 0x00000000
-
-/* SWITCH_ACB :: ACB_QUEUE_42_CONFIGURATION :: xon_en [11:11] */
-#define BCHP_SWITCH_ACB_ACB_QUEUE_42_CONFIGURATION_xon_en_MASK 0x00000800
-#define BCHP_SWITCH_ACB_ACB_QUEUE_42_CONFIGURATION_xon_en_SHIFT 11
-#define BCHP_SWITCH_ACB_ACB_QUEUE_42_CONFIGURATION_xon_en_DEFAULT 0x00000000
-
-/* SWITCH_ACB :: ACB_QUEUE_42_CONFIGURATION :: xoff_threshold [10:00] */
-#define BCHP_SWITCH_ACB_ACB_QUEUE_42_CONFIGURATION_xoff_threshold_MASK 0x000007ff
-#define BCHP_SWITCH_ACB_ACB_QUEUE_42_CONFIGURATION_xoff_threshold_SHIFT 0
-#define BCHP_SWITCH_ACB_ACB_QUEUE_42_CONFIGURATION_xoff_threshold_DEFAULT 0x00000000
-
-/***************************************************************************
- *ACB_QUEUE_43_CONFIGURATION - ACB Queue 43 Configuration Register
- ***************************************************************************/
-/* SWITCH_ACB :: ACB_QUEUE_43_CONFIGURATION :: pessimistic_mode_en [31:31] */
-#define BCHP_SWITCH_ACB_ACB_QUEUE_43_CONFIGURATION_pessimistic_mode_en_MASK 0x80000000
-#define BCHP_SWITCH_ACB_ACB_QUEUE_43_CONFIGURATION_pessimistic_mode_en_SHIFT 31
-#define BCHP_SWITCH_ACB_ACB_QUEUE_43_CONFIGURATION_pessimistic_mode_en_DEFAULT 0x00000000
-#define BCHP_SWITCH_ACB_ACB_QUEUE_43_CONFIGURATION_pessimistic_mode_en_GISB 1
-#define BCHP_SWITCH_ACB_ACB_QUEUE_43_CONFIGURATION_pessimistic_mode_en_PORT 0
-
-/* union - case input_is_gisb [30:25] */
-/* SWITCH_ACB :: ACB_QUEUE_43_CONFIGURATION :: input_is_gisb :: pktlen [30:25] */
-#define BCHP_SWITCH_ACB_ACB_QUEUE_43_CONFIGURATION_input_is_gisb_pktlen_MASK 0x7e000000
-#define BCHP_SWITCH_ACB_ACB_QUEUE_43_CONFIGURATION_input_is_gisb_pktlen_SHIFT 25
-#define BCHP_SWITCH_ACB_ACB_QUEUE_43_CONFIGURATION_input_is_gisb_pktlen_DEFAULT 0x00000000
-
-/* union - case input_is_acb_queue_43_configuration [30:25] */
-/* SWITCH_ACB :: ACB_QUEUE_43_CONFIGURATION :: input_is_acb_queue_43_configuration :: pktlen [30:25] */
-#define BCHP_SWITCH_ACB_ACB_QUEUE_43_CONFIGURATION_input_is_acb_queue_43_configuration_pktlen_MASK 0x7e000000
-#define BCHP_SWITCH_ACB_ACB_QUEUE_43_CONFIGURATION_input_is_acb_queue_43_configuration_pktlen_SHIFT 25
-#define BCHP_SWITCH_ACB_ACB_QUEUE_43_CONFIGURATION_input_is_acb_queue_43_configuration_pktlen_DEFAULT 0x00000000
-
-/* SWITCH_ACB :: ACB_QUEUE_43_CONFIGURATION :: total_xon_en [24:24] */
-#define BCHP_SWITCH_ACB_ACB_QUEUE_43_CONFIGURATION_total_xon_en_MASK 0x01000000
-#define BCHP_SWITCH_ACB_ACB_QUEUE_43_CONFIGURATION_total_xon_en_SHIFT 24
-#define BCHP_SWITCH_ACB_ACB_QUEUE_43_CONFIGURATION_total_xon_en_DEFAULT 0x00000000
-
-/* SWITCH_ACB :: ACB_QUEUE_43_CONFIGURATION :: total_xoff_en [23:23] */
-#define BCHP_SWITCH_ACB_ACB_QUEUE_43_CONFIGURATION_total_xoff_en_MASK 0x00800000
-#define BCHP_SWITCH_ACB_ACB_QUEUE_43_CONFIGURATION_total_xoff_en_SHIFT 23
-#define BCHP_SWITCH_ACB_ACB_QUEUE_43_CONFIGURATION_total_xoff_en_DEFAULT 0x00000000
-
-/* SWITCH_ACB :: ACB_QUEUE_43_CONFIGURATION :: total_xoff_threshold [22:12] */
-#define BCHP_SWITCH_ACB_ACB_QUEUE_43_CONFIGURATION_total_xoff_threshold_MASK 0x007ff000
-#define BCHP_SWITCH_ACB_ACB_QUEUE_43_CONFIGURATION_total_xoff_threshold_SHIFT 12
-#define BCHP_SWITCH_ACB_ACB_QUEUE_43_CONFIGURATION_total_xoff_threshold_DEFAULT 0x00000000
-
-/* SWITCH_ACB :: ACB_QUEUE_43_CONFIGURATION :: xon_en [11:11] */
-#define BCHP_SWITCH_ACB_ACB_QUEUE_43_CONFIGURATION_xon_en_MASK 0x00000800
-#define BCHP_SWITCH_ACB_ACB_QUEUE_43_CONFIGURATION_xon_en_SHIFT 11
-#define BCHP_SWITCH_ACB_ACB_QUEUE_43_CONFIGURATION_xon_en_DEFAULT 0x00000000
-
-/* SWITCH_ACB :: ACB_QUEUE_43_CONFIGURATION :: xoff_threshold [10:00] */
-#define BCHP_SWITCH_ACB_ACB_QUEUE_43_CONFIGURATION_xoff_threshold_MASK 0x000007ff
-#define BCHP_SWITCH_ACB_ACB_QUEUE_43_CONFIGURATION_xoff_threshold_SHIFT 0
-#define BCHP_SWITCH_ACB_ACB_QUEUE_43_CONFIGURATION_xoff_threshold_DEFAULT 0x00000000
-
-/***************************************************************************
- *ACB_QUEUE_44_CONFIGURATION - ACB Queue 44 Configuration Register
- ***************************************************************************/
-/* SWITCH_ACB :: ACB_QUEUE_44_CONFIGURATION :: pessimistic_mode_en [31:31] */
-#define BCHP_SWITCH_ACB_ACB_QUEUE_44_CONFIGURATION_pessimistic_mode_en_MASK 0x80000000
-#define BCHP_SWITCH_ACB_ACB_QUEUE_44_CONFIGURATION_pessimistic_mode_en_SHIFT 31
-#define BCHP_SWITCH_ACB_ACB_QUEUE_44_CONFIGURATION_pessimistic_mode_en_DEFAULT 0x00000000
-#define BCHP_SWITCH_ACB_ACB_QUEUE_44_CONFIGURATION_pessimistic_mode_en_GISB 1
-#define BCHP_SWITCH_ACB_ACB_QUEUE_44_CONFIGURATION_pessimistic_mode_en_PORT 0
-
-/* union - case input_is_gisb [30:25] */
-/* SWITCH_ACB :: ACB_QUEUE_44_CONFIGURATION :: input_is_gisb :: pktlen [30:25] */
-#define BCHP_SWITCH_ACB_ACB_QUEUE_44_CONFIGURATION_input_is_gisb_pktlen_MASK 0x7e000000
-#define BCHP_SWITCH_ACB_ACB_QUEUE_44_CONFIGURATION_input_is_gisb_pktlen_SHIFT 25
-#define BCHP_SWITCH_ACB_ACB_QUEUE_44_CONFIGURATION_input_is_gisb_pktlen_DEFAULT 0x00000000
-
-/* union - case input_is_acb_queue_44_configuration [30:25] */
-/* SWITCH_ACB :: ACB_QUEUE_44_CONFIGURATION :: input_is_acb_queue_44_configuration :: pktlen [30:25] */
-#define BCHP_SWITCH_ACB_ACB_QUEUE_44_CONFIGURATION_input_is_acb_queue_44_configuration_pktlen_MASK 0x7e000000
-#define BCHP_SWITCH_ACB_ACB_QUEUE_44_CONFIGURATION_input_is_acb_queue_44_configuration_pktlen_SHIFT 25
-#define BCHP_SWITCH_ACB_ACB_QUEUE_44_CONFIGURATION_input_is_acb_queue_44_configuration_pktlen_DEFAULT 0x00000000
-
-/* SWITCH_ACB :: ACB_QUEUE_44_CONFIGURATION :: total_xon_en [24:24] */
-#define BCHP_SWITCH_ACB_ACB_QUEUE_44_CONFIGURATION_total_xon_en_MASK 0x01000000
-#define BCHP_SWITCH_ACB_ACB_QUEUE_44_CONFIGURATION_total_xon_en_SHIFT 24
-#define BCHP_SWITCH_ACB_ACB_QUEUE_44_CONFIGURATION_total_xon_en_DEFAULT 0x00000000
-
-/* SWITCH_ACB :: ACB_QUEUE_44_CONFIGURATION :: total_xoff_en [23:23] */
-#define BCHP_SWITCH_ACB_ACB_QUEUE_44_CONFIGURATION_total_xoff_en_MASK 0x00800000
-#define BCHP_SWITCH_ACB_ACB_QUEUE_44_CONFIGURATION_total_xoff_en_SHIFT 23
-#define BCHP_SWITCH_ACB_ACB_QUEUE_44_CONFIGURATION_total_xoff_en_DEFAULT 0x00000000
-
-/* SWITCH_ACB :: ACB_QUEUE_44_CONFIGURATION :: total_xoff_threshold [22:12] */
-#define BCHP_SWITCH_ACB_ACB_QUEUE_44_CONFIGURATION_total_xoff_threshold_MASK 0x007ff000
-#define BCHP_SWITCH_ACB_ACB_QUEUE_44_CONFIGURATION_total_xoff_threshold_SHIFT 12
-#define BCHP_SWITCH_ACB_ACB_QUEUE_44_CONFIGURATION_total_xoff_threshold_DEFAULT 0x00000000
-
-/* SWITCH_ACB :: ACB_QUEUE_44_CONFIGURATION :: xon_en [11:11] */
-#define BCHP_SWITCH_ACB_ACB_QUEUE_44_CONFIGURATION_xon_en_MASK 0x00000800
-#define BCHP_SWITCH_ACB_ACB_QUEUE_44_CONFIGURATION_xon_en_SHIFT 11
-#define BCHP_SWITCH_ACB_ACB_QUEUE_44_CONFIGURATION_xon_en_DEFAULT 0x00000000
-
-/* SWITCH_ACB :: ACB_QUEUE_44_CONFIGURATION :: xoff_threshold [10:00] */
-#define BCHP_SWITCH_ACB_ACB_QUEUE_44_CONFIGURATION_xoff_threshold_MASK 0x000007ff
-#define BCHP_SWITCH_ACB_ACB_QUEUE_44_CONFIGURATION_xoff_threshold_SHIFT 0
-#define BCHP_SWITCH_ACB_ACB_QUEUE_44_CONFIGURATION_xoff_threshold_DEFAULT 0x00000000
-
-/***************************************************************************
- *ACB_QUEUE_45_CONFIGURATION - ACB Queue 45 Configuration Register
- ***************************************************************************/
-/* SWITCH_ACB :: ACB_QUEUE_45_CONFIGURATION :: pessimistic_mode_en [31:31] */
-#define BCHP_SWITCH_ACB_ACB_QUEUE_45_CONFIGURATION_pessimistic_mode_en_MASK 0x80000000
-#define BCHP_SWITCH_ACB_ACB_QUEUE_45_CONFIGURATION_pessimistic_mode_en_SHIFT 31
-#define BCHP_SWITCH_ACB_ACB_QUEUE_45_CONFIGURATION_pessimistic_mode_en_DEFAULT 0x00000000
-#define BCHP_SWITCH_ACB_ACB_QUEUE_45_CONFIGURATION_pessimistic_mode_en_GISB 1
-#define BCHP_SWITCH_ACB_ACB_QUEUE_45_CONFIGURATION_pessimistic_mode_en_PORT 0
-
-/* union - case input_is_gisb [30:25] */
-/* SWITCH_ACB :: ACB_QUEUE_45_CONFIGURATION :: input_is_gisb :: pktlen [30:25] */
-#define BCHP_SWITCH_ACB_ACB_QUEUE_45_CONFIGURATION_input_is_gisb_pktlen_MASK 0x7e000000
-#define BCHP_SWITCH_ACB_ACB_QUEUE_45_CONFIGURATION_input_is_gisb_pktlen_SHIFT 25
-#define BCHP_SWITCH_ACB_ACB_QUEUE_45_CONFIGURATION_input_is_gisb_pktlen_DEFAULT 0x00000000
-
-/* union - case input_is_acb_queue_45_configuration [30:25] */
-/* SWITCH_ACB :: ACB_QUEUE_45_CONFIGURATION :: input_is_acb_queue_45_configuration :: pktlen [30:25] */
-#define BCHP_SWITCH_ACB_ACB_QUEUE_45_CONFIGURATION_input_is_acb_queue_45_configuration_pktlen_MASK 0x7e000000
-#define BCHP_SWITCH_ACB_ACB_QUEUE_45_CONFIGURATION_input_is_acb_queue_45_configuration_pktlen_SHIFT 25
-#define BCHP_SWITCH_ACB_ACB_QUEUE_45_CONFIGURATION_input_is_acb_queue_45_configuration_pktlen_DEFAULT 0x00000000
-
-/* SWITCH_ACB :: ACB_QUEUE_45_CONFIGURATION :: total_xon_en [24:24] */
-#define BCHP_SWITCH_ACB_ACB_QUEUE_45_CONFIGURATION_total_xon_en_MASK 0x01000000
-#define BCHP_SWITCH_ACB_ACB_QUEUE_45_CONFIGURATION_total_xon_en_SHIFT 24
-#define BCHP_SWITCH_ACB_ACB_QUEUE_45_CONFIGURATION_total_xon_en_DEFAULT 0x00000000
-
-/* SWITCH_ACB :: ACB_QUEUE_45_CONFIGURATION :: total_xoff_en [23:23] */
-#define BCHP_SWITCH_ACB_ACB_QUEUE_45_CONFIGURATION_total_xoff_en_MASK 0x00800000
-#define BCHP_SWITCH_ACB_ACB_QUEUE_45_CONFIGURATION_total_xoff_en_SHIFT 23
-#define BCHP_SWITCH_ACB_ACB_QUEUE_45_CONFIGURATION_total_xoff_en_DEFAULT 0x00000000
-
-/* SWITCH_ACB :: ACB_QUEUE_45_CONFIGURATION :: total_xoff_threshold [22:12] */
-#define BCHP_SWITCH_ACB_ACB_QUEUE_45_CONFIGURATION_total_xoff_threshold_MASK 0x007ff000
-#define BCHP_SWITCH_ACB_ACB_QUEUE_45_CONFIGURATION_total_xoff_threshold_SHIFT 12
-#define BCHP_SWITCH_ACB_ACB_QUEUE_45_CONFIGURATION_total_xoff_threshold_DEFAULT 0x00000000
-
-/* SWITCH_ACB :: ACB_QUEUE_45_CONFIGURATION :: xon_en [11:11] */
-#define BCHP_SWITCH_ACB_ACB_QUEUE_45_CONFIGURATION_xon_en_MASK 0x00000800
-#define BCHP_SWITCH_ACB_ACB_QUEUE_45_CONFIGURATION_xon_en_SHIFT 11
-#define BCHP_SWITCH_ACB_ACB_QUEUE_45_CONFIGURATION_xon_en_DEFAULT 0x00000000
-
-/* SWITCH_ACB :: ACB_QUEUE_45_CONFIGURATION :: xoff_threshold [10:00] */
-#define BCHP_SWITCH_ACB_ACB_QUEUE_45_CONFIGURATION_xoff_threshold_MASK 0x000007ff
-#define BCHP_SWITCH_ACB_ACB_QUEUE_45_CONFIGURATION_xoff_threshold_SHIFT 0
-#define BCHP_SWITCH_ACB_ACB_QUEUE_45_CONFIGURATION_xoff_threshold_DEFAULT 0x00000000
-
-/***************************************************************************
- *ACB_QUEUE_46_CONFIGURATION - ACB Queue 46 Configuration Register
- ***************************************************************************/
-/* SWITCH_ACB :: ACB_QUEUE_46_CONFIGURATION :: pessimistic_mode_en [31:31] */
-#define BCHP_SWITCH_ACB_ACB_QUEUE_46_CONFIGURATION_pessimistic_mode_en_MASK 0x80000000
-#define BCHP_SWITCH_ACB_ACB_QUEUE_46_CONFIGURATION_pessimistic_mode_en_SHIFT 31
-#define BCHP_SWITCH_ACB_ACB_QUEUE_46_CONFIGURATION_pessimistic_mode_en_DEFAULT 0x00000000
-#define BCHP_SWITCH_ACB_ACB_QUEUE_46_CONFIGURATION_pessimistic_mode_en_GISB 1
-#define BCHP_SWITCH_ACB_ACB_QUEUE_46_CONFIGURATION_pessimistic_mode_en_PORT 0
-
-/* union - case input_is_gisb [30:25] */
-/* SWITCH_ACB :: ACB_QUEUE_46_CONFIGURATION :: input_is_gisb :: pktlen [30:25] */
-#define BCHP_SWITCH_ACB_ACB_QUEUE_46_CONFIGURATION_input_is_gisb_pktlen_MASK 0x7e000000
-#define BCHP_SWITCH_ACB_ACB_QUEUE_46_CONFIGURATION_input_is_gisb_pktlen_SHIFT 25
-#define BCHP_SWITCH_ACB_ACB_QUEUE_46_CONFIGURATION_input_is_gisb_pktlen_DEFAULT 0x00000000
-
-/* union - case input_is_acb_queue_46_configuration [30:25] */
-/* SWITCH_ACB :: ACB_QUEUE_46_CONFIGURATION :: input_is_acb_queue_46_configuration :: pktlen [30:25] */
-#define BCHP_SWITCH_ACB_ACB_QUEUE_46_CONFIGURATION_input_is_acb_queue_46_configuration_pktlen_MASK 0x7e000000
-#define BCHP_SWITCH_ACB_ACB_QUEUE_46_CONFIGURATION_input_is_acb_queue_46_configuration_pktlen_SHIFT 25
-#define BCHP_SWITCH_ACB_ACB_QUEUE_46_CONFIGURATION_input_is_acb_queue_46_configuration_pktlen_DEFAULT 0x00000000
-
-/* SWITCH_ACB :: ACB_QUEUE_46_CONFIGURATION :: total_xon_en [24:24] */
-#define BCHP_SWITCH_ACB_ACB_QUEUE_46_CONFIGURATION_total_xon_en_MASK 0x01000000
-#define BCHP_SWITCH_ACB_ACB_QUEUE_46_CONFIGURATION_total_xon_en_SHIFT 24
-#define BCHP_SWITCH_ACB_ACB_QUEUE_46_CONFIGURATION_total_xon_en_DEFAULT 0x00000000
-
-/* SWITCH_ACB :: ACB_QUEUE_46_CONFIGURATION :: total_xoff_en [23:23] */
-#define BCHP_SWITCH_ACB_ACB_QUEUE_46_CONFIGURATION_total_xoff_en_MASK 0x00800000
-#define BCHP_SWITCH_ACB_ACB_QUEUE_46_CONFIGURATION_total_xoff_en_SHIFT 23
-#define BCHP_SWITCH_ACB_ACB_QUEUE_46_CONFIGURATION_total_xoff_en_DEFAULT 0x00000000
-
-/* SWITCH_ACB :: ACB_QUEUE_46_CONFIGURATION :: total_xoff_threshold [22:12] */
-#define BCHP_SWITCH_ACB_ACB_QUEUE_46_CONFIGURATION_total_xoff_threshold_MASK 0x007ff000
-#define BCHP_SWITCH_ACB_ACB_QUEUE_46_CONFIGURATION_total_xoff_threshold_SHIFT 12
-#define BCHP_SWITCH_ACB_ACB_QUEUE_46_CONFIGURATION_total_xoff_threshold_DEFAULT 0x00000000
-
-/* SWITCH_ACB :: ACB_QUEUE_46_CONFIGURATION :: xon_en [11:11] */
-#define BCHP_SWITCH_ACB_ACB_QUEUE_46_CONFIGURATION_xon_en_MASK 0x00000800
-#define BCHP_SWITCH_ACB_ACB_QUEUE_46_CONFIGURATION_xon_en_SHIFT 11
-#define BCHP_SWITCH_ACB_ACB_QUEUE_46_CONFIGURATION_xon_en_DEFAULT 0x00000000
-
-/* SWITCH_ACB :: ACB_QUEUE_46_CONFIGURATION :: xoff_threshold [10:00] */
-#define BCHP_SWITCH_ACB_ACB_QUEUE_46_CONFIGURATION_xoff_threshold_MASK 0x000007ff
-#define BCHP_SWITCH_ACB_ACB_QUEUE_46_CONFIGURATION_xoff_threshold_SHIFT 0
-#define BCHP_SWITCH_ACB_ACB_QUEUE_46_CONFIGURATION_xoff_threshold_DEFAULT 0x00000000
-
-/***************************************************************************
- *ACB_QUEUE_47_CONFIGURATION - ACB Queue 47 Configuration Register
- ***************************************************************************/
-/* SWITCH_ACB :: ACB_QUEUE_47_CONFIGURATION :: pessimistic_mode_en [31:31] */
-#define BCHP_SWITCH_ACB_ACB_QUEUE_47_CONFIGURATION_pessimistic_mode_en_MASK 0x80000000
-#define BCHP_SWITCH_ACB_ACB_QUEUE_47_CONFIGURATION_pessimistic_mode_en_SHIFT 31
-#define BCHP_SWITCH_ACB_ACB_QUEUE_47_CONFIGURATION_pessimistic_mode_en_DEFAULT 0x00000000
-#define BCHP_SWITCH_ACB_ACB_QUEUE_47_CONFIGURATION_pessimistic_mode_en_GISB 1
-#define BCHP_SWITCH_ACB_ACB_QUEUE_47_CONFIGURATION_pessimistic_mode_en_PORT 0
-
-/* union - case input_is_gisb [30:25] */
-/* SWITCH_ACB :: ACB_QUEUE_47_CONFIGURATION :: input_is_gisb :: pktlen [30:25] */
-#define BCHP_SWITCH_ACB_ACB_QUEUE_47_CONFIGURATION_input_is_gisb_pktlen_MASK 0x7e000000
-#define BCHP_SWITCH_ACB_ACB_QUEUE_47_CONFIGURATION_input_is_gisb_pktlen_SHIFT 25
-#define BCHP_SWITCH_ACB_ACB_QUEUE_47_CONFIGURATION_input_is_gisb_pktlen_DEFAULT 0x00000000
-
-/* union - case input_is_acb_queue_47_configuration [30:25] */
-/* SWITCH_ACB :: ACB_QUEUE_47_CONFIGURATION :: input_is_acb_queue_47_configuration :: pktlen [30:25] */
-#define BCHP_SWITCH_ACB_ACB_QUEUE_47_CONFIGURATION_input_is_acb_queue_47_configuration_pktlen_MASK 0x7e000000
-#define BCHP_SWITCH_ACB_ACB_QUEUE_47_CONFIGURATION_input_is_acb_queue_47_configuration_pktlen_SHIFT 25
-#define BCHP_SWITCH_ACB_ACB_QUEUE_47_CONFIGURATION_input_is_acb_queue_47_configuration_pktlen_DEFAULT 0x00000000
-
-/* SWITCH_ACB :: ACB_QUEUE_47_CONFIGURATION :: total_xon_en [24:24] */
-#define BCHP_SWITCH_ACB_ACB_QUEUE_47_CONFIGURATION_total_xon_en_MASK 0x01000000
-#define BCHP_SWITCH_ACB_ACB_QUEUE_47_CONFIGURATION_total_xon_en_SHIFT 24
-#define BCHP_SWITCH_ACB_ACB_QUEUE_47_CONFIGURATION_total_xon_en_DEFAULT 0x00000000
-
-/* SWITCH_ACB :: ACB_QUEUE_47_CONFIGURATION :: total_xoff_en [23:23] */
-#define BCHP_SWITCH_ACB_ACB_QUEUE_47_CONFIGURATION_total_xoff_en_MASK 0x00800000
-#define BCHP_SWITCH_ACB_ACB_QUEUE_47_CONFIGURATION_total_xoff_en_SHIFT 23
-#define BCHP_SWITCH_ACB_ACB_QUEUE_47_CONFIGURATION_total_xoff_en_DEFAULT 0x00000000
-
-/* SWITCH_ACB :: ACB_QUEUE_47_CONFIGURATION :: total_xoff_threshold [22:12] */
-#define BCHP_SWITCH_ACB_ACB_QUEUE_47_CONFIGURATION_total_xoff_threshold_MASK 0x007ff000
-#define BCHP_SWITCH_ACB_ACB_QUEUE_47_CONFIGURATION_total_xoff_threshold_SHIFT 12
-#define BCHP_SWITCH_ACB_ACB_QUEUE_47_CONFIGURATION_total_xoff_threshold_DEFAULT 0x00000000
-
-/* SWITCH_ACB :: ACB_QUEUE_47_CONFIGURATION :: xon_en [11:11] */
-#define BCHP_SWITCH_ACB_ACB_QUEUE_47_CONFIGURATION_xon_en_MASK 0x00000800
-#define BCHP_SWITCH_ACB_ACB_QUEUE_47_CONFIGURATION_xon_en_SHIFT 11
-#define BCHP_SWITCH_ACB_ACB_QUEUE_47_CONFIGURATION_xon_en_DEFAULT 0x00000000
-
-/* SWITCH_ACB :: ACB_QUEUE_47_CONFIGURATION :: xoff_threshold [10:00] */
-#define BCHP_SWITCH_ACB_ACB_QUEUE_47_CONFIGURATION_xoff_threshold_MASK 0x000007ff
-#define BCHP_SWITCH_ACB_ACB_QUEUE_47_CONFIGURATION_xoff_threshold_SHIFT 0
-#define BCHP_SWITCH_ACB_ACB_QUEUE_47_CONFIGURATION_xoff_threshold_DEFAULT 0x00000000
-
-/***************************************************************************
- *ACB_QUEUE_48_CONFIGURATION - ACB Queue 48 Configuration Register
- ***************************************************************************/
-/* SWITCH_ACB :: ACB_QUEUE_48_CONFIGURATION :: pessimistic_mode_en [31:31] */
-#define BCHP_SWITCH_ACB_ACB_QUEUE_48_CONFIGURATION_pessimistic_mode_en_MASK 0x80000000
-#define BCHP_SWITCH_ACB_ACB_QUEUE_48_CONFIGURATION_pessimistic_mode_en_SHIFT 31
-#define BCHP_SWITCH_ACB_ACB_QUEUE_48_CONFIGURATION_pessimistic_mode_en_DEFAULT 0x00000000
-#define BCHP_SWITCH_ACB_ACB_QUEUE_48_CONFIGURATION_pessimistic_mode_en_GISB 1
-#define BCHP_SWITCH_ACB_ACB_QUEUE_48_CONFIGURATION_pessimistic_mode_en_PORT 0
-
-/* union - case input_is_gisb [30:25] */
-/* SWITCH_ACB :: ACB_QUEUE_48_CONFIGURATION :: input_is_gisb :: pktlen [30:25] */
-#define BCHP_SWITCH_ACB_ACB_QUEUE_48_CONFIGURATION_input_is_gisb_pktlen_MASK 0x7e000000
-#define BCHP_SWITCH_ACB_ACB_QUEUE_48_CONFIGURATION_input_is_gisb_pktlen_SHIFT 25
-#define BCHP_SWITCH_ACB_ACB_QUEUE_48_CONFIGURATION_input_is_gisb_pktlen_DEFAULT 0x00000000
-
-/* union - case input_is_acb_queue_48_configuration [30:25] */
-/* SWITCH_ACB :: ACB_QUEUE_48_CONFIGURATION :: input_is_acb_queue_48_configuration :: pktlen [30:25] */
-#define BCHP_SWITCH_ACB_ACB_QUEUE_48_CONFIGURATION_input_is_acb_queue_48_configuration_pktlen_MASK 0x7e000000
-#define BCHP_SWITCH_ACB_ACB_QUEUE_48_CONFIGURATION_input_is_acb_queue_48_configuration_pktlen_SHIFT 25
-#define BCHP_SWITCH_ACB_ACB_QUEUE_48_CONFIGURATION_input_is_acb_queue_48_configuration_pktlen_DEFAULT 0x00000000
-
-/* SWITCH_ACB :: ACB_QUEUE_48_CONFIGURATION :: total_xon_en [24:24] */
-#define BCHP_SWITCH_ACB_ACB_QUEUE_48_CONFIGURATION_total_xon_en_MASK 0x01000000
-#define BCHP_SWITCH_ACB_ACB_QUEUE_48_CONFIGURATION_total_xon_en_SHIFT 24
-#define BCHP_SWITCH_ACB_ACB_QUEUE_48_CONFIGURATION_total_xon_en_DEFAULT 0x00000000
-
-/* SWITCH_ACB :: ACB_QUEUE_48_CONFIGURATION :: total_xoff_en [23:23] */
-#define BCHP_SWITCH_ACB_ACB_QUEUE_48_CONFIGURATION_total_xoff_en_MASK 0x00800000
-#define BCHP_SWITCH_ACB_ACB_QUEUE_48_CONFIGURATION_total_xoff_en_SHIFT 23
-#define BCHP_SWITCH_ACB_ACB_QUEUE_48_CONFIGURATION_total_xoff_en_DEFAULT 0x00000000
-
-/* SWITCH_ACB :: ACB_QUEUE_48_CONFIGURATION :: total_xoff_threshold [22:12] */
-#define BCHP_SWITCH_ACB_ACB_QUEUE_48_CONFIGURATION_total_xoff_threshold_MASK 0x007ff000
-#define BCHP_SWITCH_ACB_ACB_QUEUE_48_CONFIGURATION_total_xoff_threshold_SHIFT 12
-#define BCHP_SWITCH_ACB_ACB_QUEUE_48_CONFIGURATION_total_xoff_threshold_DEFAULT 0x00000000
-
-/* SWITCH_ACB :: ACB_QUEUE_48_CONFIGURATION :: xon_en [11:11] */
-#define BCHP_SWITCH_ACB_ACB_QUEUE_48_CONFIGURATION_xon_en_MASK 0x00000800
-#define BCHP_SWITCH_ACB_ACB_QUEUE_48_CONFIGURATION_xon_en_SHIFT 11
-#define BCHP_SWITCH_ACB_ACB_QUEUE_48_CONFIGURATION_xon_en_DEFAULT 0x00000000
-
-/* SWITCH_ACB :: ACB_QUEUE_48_CONFIGURATION :: xoff_threshold [10:00] */
-#define BCHP_SWITCH_ACB_ACB_QUEUE_48_CONFIGURATION_xoff_threshold_MASK 0x000007ff
-#define BCHP_SWITCH_ACB_ACB_QUEUE_48_CONFIGURATION_xoff_threshold_SHIFT 0
-#define BCHP_SWITCH_ACB_ACB_QUEUE_48_CONFIGURATION_xoff_threshold_DEFAULT 0x00000000
-
-/***************************************************************************
- *ACB_QUEUE_49_CONFIGURATION - ACB Queue 49 Configuration Register
- ***************************************************************************/
-/* SWITCH_ACB :: ACB_QUEUE_49_CONFIGURATION :: pessimistic_mode_en [31:31] */
-#define BCHP_SWITCH_ACB_ACB_QUEUE_49_CONFIGURATION_pessimistic_mode_en_MASK 0x80000000
-#define BCHP_SWITCH_ACB_ACB_QUEUE_49_CONFIGURATION_pessimistic_mode_en_SHIFT 31
-#define BCHP_SWITCH_ACB_ACB_QUEUE_49_CONFIGURATION_pessimistic_mode_en_DEFAULT 0x00000000
-#define BCHP_SWITCH_ACB_ACB_QUEUE_49_CONFIGURATION_pessimistic_mode_en_GISB 1
-#define BCHP_SWITCH_ACB_ACB_QUEUE_49_CONFIGURATION_pessimistic_mode_en_PORT 0
-
-/* union - case input_is_gisb [30:25] */
-/* SWITCH_ACB :: ACB_QUEUE_49_CONFIGURATION :: input_is_gisb :: pktlen [30:25] */
-#define BCHP_SWITCH_ACB_ACB_QUEUE_49_CONFIGURATION_input_is_gisb_pktlen_MASK 0x7e000000
-#define BCHP_SWITCH_ACB_ACB_QUEUE_49_CONFIGURATION_input_is_gisb_pktlen_SHIFT 25
-#define BCHP_SWITCH_ACB_ACB_QUEUE_49_CONFIGURATION_input_is_gisb_pktlen_DEFAULT 0x00000000
-
-/* union - case input_is_acb_queue_49_configuration [30:25] */
-/* SWITCH_ACB :: ACB_QUEUE_49_CONFIGURATION :: input_is_acb_queue_49_configuration :: pktlen [30:25] */
-#define BCHP_SWITCH_ACB_ACB_QUEUE_49_CONFIGURATION_input_is_acb_queue_49_configuration_pktlen_MASK 0x7e000000
-#define BCHP_SWITCH_ACB_ACB_QUEUE_49_CONFIGURATION_input_is_acb_queue_49_configuration_pktlen_SHIFT 25
-#define BCHP_SWITCH_ACB_ACB_QUEUE_49_CONFIGURATION_input_is_acb_queue_49_configuration_pktlen_DEFAULT 0x00000000
-
-/* SWITCH_ACB :: ACB_QUEUE_49_CONFIGURATION :: total_xon_en [24:24] */
-#define BCHP_SWITCH_ACB_ACB_QUEUE_49_CONFIGURATION_total_xon_en_MASK 0x01000000
-#define BCHP_SWITCH_ACB_ACB_QUEUE_49_CONFIGURATION_total_xon_en_SHIFT 24
-#define BCHP_SWITCH_ACB_ACB_QUEUE_49_CONFIGURATION_total_xon_en_DEFAULT 0x00000000
-
-/* SWITCH_ACB :: ACB_QUEUE_49_CONFIGURATION :: total_xoff_en [23:23] */
-#define BCHP_SWITCH_ACB_ACB_QUEUE_49_CONFIGURATION_total_xoff_en_MASK 0x00800000
-#define BCHP_SWITCH_ACB_ACB_QUEUE_49_CONFIGURATION_total_xoff_en_SHIFT 23
-#define BCHP_SWITCH_ACB_ACB_QUEUE_49_CONFIGURATION_total_xoff_en_DEFAULT 0x00000000
-
-/* SWITCH_ACB :: ACB_QUEUE_49_CONFIGURATION :: total_xoff_threshold [22:12] */
-#define BCHP_SWITCH_ACB_ACB_QUEUE_49_CONFIGURATION_total_xoff_threshold_MASK 0x007ff000
-#define BCHP_SWITCH_ACB_ACB_QUEUE_49_CONFIGURATION_total_xoff_threshold_SHIFT 12
-#define BCHP_SWITCH_ACB_ACB_QUEUE_49_CONFIGURATION_total_xoff_threshold_DEFAULT 0x00000000
-
-/* SWITCH_ACB :: ACB_QUEUE_49_CONFIGURATION :: xon_en [11:11] */
-#define BCHP_SWITCH_ACB_ACB_QUEUE_49_CONFIGURATION_xon_en_MASK 0x00000800
-#define BCHP_SWITCH_ACB_ACB_QUEUE_49_CONFIGURATION_xon_en_SHIFT 11
-#define BCHP_SWITCH_ACB_ACB_QUEUE_49_CONFIGURATION_xon_en_DEFAULT 0x00000000
-
-/* SWITCH_ACB :: ACB_QUEUE_49_CONFIGURATION :: xoff_threshold [10:00] */
-#define BCHP_SWITCH_ACB_ACB_QUEUE_49_CONFIGURATION_xoff_threshold_MASK 0x000007ff
-#define BCHP_SWITCH_ACB_ACB_QUEUE_49_CONFIGURATION_xoff_threshold_SHIFT 0
-#define BCHP_SWITCH_ACB_ACB_QUEUE_49_CONFIGURATION_xoff_threshold_DEFAULT 0x00000000
-
-/***************************************************************************
- *ACB_QUEUE_50_CONFIGURATION - ACB Queue 50 Configuration Register
- ***************************************************************************/
-/* SWITCH_ACB :: ACB_QUEUE_50_CONFIGURATION :: pessimistic_mode_en [31:31] */
-#define BCHP_SWITCH_ACB_ACB_QUEUE_50_CONFIGURATION_pessimistic_mode_en_MASK 0x80000000
-#define BCHP_SWITCH_ACB_ACB_QUEUE_50_CONFIGURATION_pessimistic_mode_en_SHIFT 31
-#define BCHP_SWITCH_ACB_ACB_QUEUE_50_CONFIGURATION_pessimistic_mode_en_DEFAULT 0x00000000
-#define BCHP_SWITCH_ACB_ACB_QUEUE_50_CONFIGURATION_pessimistic_mode_en_GISB 1
-#define BCHP_SWITCH_ACB_ACB_QUEUE_50_CONFIGURATION_pessimistic_mode_en_PORT 0
-
-/* union - case input_is_gisb [30:25] */
-/* SWITCH_ACB :: ACB_QUEUE_50_CONFIGURATION :: input_is_gisb :: pktlen [30:25] */
-#define BCHP_SWITCH_ACB_ACB_QUEUE_50_CONFIGURATION_input_is_gisb_pktlen_MASK 0x7e000000
-#define BCHP_SWITCH_ACB_ACB_QUEUE_50_CONFIGURATION_input_is_gisb_pktlen_SHIFT 25
-#define BCHP_SWITCH_ACB_ACB_QUEUE_50_CONFIGURATION_input_is_gisb_pktlen_DEFAULT 0x00000000
-
-/* union - case input_is_acb_queue_50_configuration [30:25] */
-/* SWITCH_ACB :: ACB_QUEUE_50_CONFIGURATION :: input_is_acb_queue_50_configuration :: pktlen [30:25] */
-#define BCHP_SWITCH_ACB_ACB_QUEUE_50_CONFIGURATION_input_is_acb_queue_50_configuration_pktlen_MASK 0x7e000000
-#define BCHP_SWITCH_ACB_ACB_QUEUE_50_CONFIGURATION_input_is_acb_queue_50_configuration_pktlen_SHIFT 25
-#define BCHP_SWITCH_ACB_ACB_QUEUE_50_CONFIGURATION_input_is_acb_queue_50_configuration_pktlen_DEFAULT 0x00000000
-
-/* SWITCH_ACB :: ACB_QUEUE_50_CONFIGURATION :: total_xon_en [24:24] */
-#define BCHP_SWITCH_ACB_ACB_QUEUE_50_CONFIGURATION_total_xon_en_MASK 0x01000000
-#define BCHP_SWITCH_ACB_ACB_QUEUE_50_CONFIGURATION_total_xon_en_SHIFT 24
-#define BCHP_SWITCH_ACB_ACB_QUEUE_50_CONFIGURATION_total_xon_en_DEFAULT 0x00000000
-
-/* SWITCH_ACB :: ACB_QUEUE_50_CONFIGURATION :: total_xoff_en [23:23] */
-#define BCHP_SWITCH_ACB_ACB_QUEUE_50_CONFIGURATION_total_xoff_en_MASK 0x00800000
-#define BCHP_SWITCH_ACB_ACB_QUEUE_50_CONFIGURATION_total_xoff_en_SHIFT 23
-#define BCHP_SWITCH_ACB_ACB_QUEUE_50_CONFIGURATION_total_xoff_en_DEFAULT 0x00000000
-
-/* SWITCH_ACB :: ACB_QUEUE_50_CONFIGURATION :: total_xoff_threshold [22:12] */
-#define BCHP_SWITCH_ACB_ACB_QUEUE_50_CONFIGURATION_total_xoff_threshold_MASK 0x007ff000
-#define BCHP_SWITCH_ACB_ACB_QUEUE_50_CONFIGURATION_total_xoff_threshold_SHIFT 12
-#define BCHP_SWITCH_ACB_ACB_QUEUE_50_CONFIGURATION_total_xoff_threshold_DEFAULT 0x00000000
-
-/* SWITCH_ACB :: ACB_QUEUE_50_CONFIGURATION :: xon_en [11:11] */
-#define BCHP_SWITCH_ACB_ACB_QUEUE_50_CONFIGURATION_xon_en_MASK 0x00000800
-#define BCHP_SWITCH_ACB_ACB_QUEUE_50_CONFIGURATION_xon_en_SHIFT 11
-#define BCHP_SWITCH_ACB_ACB_QUEUE_50_CONFIGURATION_xon_en_DEFAULT 0x00000000
-
-/* SWITCH_ACB :: ACB_QUEUE_50_CONFIGURATION :: xoff_threshold [10:00] */
-#define BCHP_SWITCH_ACB_ACB_QUEUE_50_CONFIGURATION_xoff_threshold_MASK 0x000007ff
-#define BCHP_SWITCH_ACB_ACB_QUEUE_50_CONFIGURATION_xoff_threshold_SHIFT 0
-#define BCHP_SWITCH_ACB_ACB_QUEUE_50_CONFIGURATION_xoff_threshold_DEFAULT 0x00000000
-
-/***************************************************************************
- *ACB_QUEUE_51_CONFIGURATION - ACB Queue 51 Configuration Register6
- ***************************************************************************/
-/* SWITCH_ACB :: ACB_QUEUE_51_CONFIGURATION :: pessimistic_mode_en [31:31] */
-#define BCHP_SWITCH_ACB_ACB_QUEUE_51_CONFIGURATION_pessimistic_mode_en_MASK 0x80000000
-#define BCHP_SWITCH_ACB_ACB_QUEUE_51_CONFIGURATION_pessimistic_mode_en_SHIFT 31
-#define BCHP_SWITCH_ACB_ACB_QUEUE_51_CONFIGURATION_pessimistic_mode_en_DEFAULT 0x00000000
-#define BCHP_SWITCH_ACB_ACB_QUEUE_51_CONFIGURATION_pessimistic_mode_en_GISB 1
-#define BCHP_SWITCH_ACB_ACB_QUEUE_51_CONFIGURATION_pessimistic_mode_en_PORT 0
-
-/* union - case input_is_gisb [30:25] */
-/* SWITCH_ACB :: ACB_QUEUE_51_CONFIGURATION :: input_is_gisb :: pktlen [30:25] */
-#define BCHP_SWITCH_ACB_ACB_QUEUE_51_CONFIGURATION_input_is_gisb_pktlen_MASK 0x7e000000
-#define BCHP_SWITCH_ACB_ACB_QUEUE_51_CONFIGURATION_input_is_gisb_pktlen_SHIFT 25
-#define BCHP_SWITCH_ACB_ACB_QUEUE_51_CONFIGURATION_input_is_gisb_pktlen_DEFAULT 0x00000000
-
-/* union - case input_is_acb_queue_51_configuration [30:25] */
-/* SWITCH_ACB :: ACB_QUEUE_51_CONFIGURATION :: input_is_acb_queue_51_configuration :: pktlen [30:25] */
-#define BCHP_SWITCH_ACB_ACB_QUEUE_51_CONFIGURATION_input_is_acb_queue_51_configuration_pktlen_MASK 0x7e000000
-#define BCHP_SWITCH_ACB_ACB_QUEUE_51_CONFIGURATION_input_is_acb_queue_51_configuration_pktlen_SHIFT 25
-#define BCHP_SWITCH_ACB_ACB_QUEUE_51_CONFIGURATION_input_is_acb_queue_51_configuration_pktlen_DEFAULT 0x00000000
-
-/* SWITCH_ACB :: ACB_QUEUE_51_CONFIGURATION :: total_xon_en [24:24] */
-#define BCHP_SWITCH_ACB_ACB_QUEUE_51_CONFIGURATION_total_xon_en_MASK 0x01000000
-#define BCHP_SWITCH_ACB_ACB_QUEUE_51_CONFIGURATION_total_xon_en_SHIFT 24
-#define BCHP_SWITCH_ACB_ACB_QUEUE_51_CONFIGURATION_total_xon_en_DEFAULT 0x00000000
-
-/* SWITCH_ACB :: ACB_QUEUE_51_CONFIGURATION :: total_xoff_en [23:23] */
-#define BCHP_SWITCH_ACB_ACB_QUEUE_51_CONFIGURATION_total_xoff_en_MASK 0x00800000
-#define BCHP_SWITCH_ACB_ACB_QUEUE_51_CONFIGURATION_total_xoff_en_SHIFT 23
-#define BCHP_SWITCH_ACB_ACB_QUEUE_51_CONFIGURATION_total_xoff_en_DEFAULT 0x00000000
-
-/* SWITCH_ACB :: ACB_QUEUE_51_CONFIGURATION :: total_xoff_threshold [22:12] */
-#define BCHP_SWITCH_ACB_ACB_QUEUE_51_CONFIGURATION_total_xoff_threshold_MASK 0x007ff000
-#define BCHP_SWITCH_ACB_ACB_QUEUE_51_CONFIGURATION_total_xoff_threshold_SHIFT 12
-#define BCHP_SWITCH_ACB_ACB_QUEUE_51_CONFIGURATION_total_xoff_threshold_DEFAULT 0x00000000
-
-/* SWITCH_ACB :: ACB_QUEUE_51_CONFIGURATION :: xon_en [11:11] */
-#define BCHP_SWITCH_ACB_ACB_QUEUE_51_CONFIGURATION_xon_en_MASK 0x00000800
-#define BCHP_SWITCH_ACB_ACB_QUEUE_51_CONFIGURATION_xon_en_SHIFT 11
-#define BCHP_SWITCH_ACB_ACB_QUEUE_51_CONFIGURATION_xon_en_DEFAULT 0x00000000
-
-/* SWITCH_ACB :: ACB_QUEUE_51_CONFIGURATION :: xoff_threshold [10:00] */
-#define BCHP_SWITCH_ACB_ACB_QUEUE_51_CONFIGURATION_xoff_threshold_MASK 0x000007ff
-#define BCHP_SWITCH_ACB_ACB_QUEUE_51_CONFIGURATION_xoff_threshold_SHIFT 0
-#define BCHP_SWITCH_ACB_ACB_QUEUE_51_CONFIGURATION_xoff_threshold_DEFAULT 0x00000000
-
-/***************************************************************************
- *ACB_QUEUE_52_CONFIGURATION - ACB Queue 52 Configuration Register
- ***************************************************************************/
-/* SWITCH_ACB :: ACB_QUEUE_52_CONFIGURATION :: pessimistic_mode_en [31:31] */
-#define BCHP_SWITCH_ACB_ACB_QUEUE_52_CONFIGURATION_pessimistic_mode_en_MASK 0x80000000
-#define BCHP_SWITCH_ACB_ACB_QUEUE_52_CONFIGURATION_pessimistic_mode_en_SHIFT 31
-#define BCHP_SWITCH_ACB_ACB_QUEUE_52_CONFIGURATION_pessimistic_mode_en_DEFAULT 0x00000000
-#define BCHP_SWITCH_ACB_ACB_QUEUE_52_CONFIGURATION_pessimistic_mode_en_GISB 1
-#define BCHP_SWITCH_ACB_ACB_QUEUE_52_CONFIGURATION_pessimistic_mode_en_PORT 0
-
-/* union - case input_is_gisb [30:25] */
-/* SWITCH_ACB :: ACB_QUEUE_52_CONFIGURATION :: input_is_gisb :: pktlen [30:25] */
-#define BCHP_SWITCH_ACB_ACB_QUEUE_52_CONFIGURATION_input_is_gisb_pktlen_MASK 0x7e000000
-#define BCHP_SWITCH_ACB_ACB_QUEUE_52_CONFIGURATION_input_is_gisb_pktlen_SHIFT 25
-#define BCHP_SWITCH_ACB_ACB_QUEUE_52_CONFIGURATION_input_is_gisb_pktlen_DEFAULT 0x00000000
-
-/* union - case input_is_acb_queue_52_configuration [30:25] */
-/* SWITCH_ACB :: ACB_QUEUE_52_CONFIGURATION :: input_is_acb_queue_52_configuration :: pktlen [30:25] */
-#define BCHP_SWITCH_ACB_ACB_QUEUE_52_CONFIGURATION_input_is_acb_queue_52_configuration_pktlen_MASK 0x7e000000
-#define BCHP_SWITCH_ACB_ACB_QUEUE_52_CONFIGURATION_input_is_acb_queue_52_configuration_pktlen_SHIFT 25
-#define BCHP_SWITCH_ACB_ACB_QUEUE_52_CONFIGURATION_input_is_acb_queue_52_configuration_pktlen_DEFAULT 0x00000000
-
-/* SWITCH_ACB :: ACB_QUEUE_52_CONFIGURATION :: total_xon_en [24:24] */
-#define BCHP_SWITCH_ACB_ACB_QUEUE_52_CONFIGURATION_total_xon_en_MASK 0x01000000
-#define BCHP_SWITCH_ACB_ACB_QUEUE_52_CONFIGURATION_total_xon_en_SHIFT 24
-#define BCHP_SWITCH_ACB_ACB_QUEUE_52_CONFIGURATION_total_xon_en_DEFAULT 0x00000000
-
-/* SWITCH_ACB :: ACB_QUEUE_52_CONFIGURATION :: total_xoff_en [23:23] */
-#define BCHP_SWITCH_ACB_ACB_QUEUE_52_CONFIGURATION_total_xoff_en_MASK 0x00800000
-#define BCHP_SWITCH_ACB_ACB_QUEUE_52_CONFIGURATION_total_xoff_en_SHIFT 23
-#define BCHP_SWITCH_ACB_ACB_QUEUE_52_CONFIGURATION_total_xoff_en_DEFAULT 0x00000000
-
-/* SWITCH_ACB :: ACB_QUEUE_52_CONFIGURATION :: total_xoff_threshold [22:12] */
-#define BCHP_SWITCH_ACB_ACB_QUEUE_52_CONFIGURATION_total_xoff_threshold_MASK 0x007ff000
-#define BCHP_SWITCH_ACB_ACB_QUEUE_52_CONFIGURATION_total_xoff_threshold_SHIFT 12
-#define BCHP_SWITCH_ACB_ACB_QUEUE_52_CONFIGURATION_total_xoff_threshold_DEFAULT 0x00000000
-
-/* SWITCH_ACB :: ACB_QUEUE_52_CONFIGURATION :: xon_en [11:11] */
-#define BCHP_SWITCH_ACB_ACB_QUEUE_52_CONFIGURATION_xon_en_MASK 0x00000800
-#define BCHP_SWITCH_ACB_ACB_QUEUE_52_CONFIGURATION_xon_en_SHIFT 11
-#define BCHP_SWITCH_ACB_ACB_QUEUE_52_CONFIGURATION_xon_en_DEFAULT 0x00000000
-
-/* SWITCH_ACB :: ACB_QUEUE_52_CONFIGURATION :: xoff_threshold [10:00] */
-#define BCHP_SWITCH_ACB_ACB_QUEUE_52_CONFIGURATION_xoff_threshold_MASK 0x000007ff
-#define BCHP_SWITCH_ACB_ACB_QUEUE_52_CONFIGURATION_xoff_threshold_SHIFT 0
-#define BCHP_SWITCH_ACB_ACB_QUEUE_52_CONFIGURATION_xoff_threshold_DEFAULT 0x00000000
-
-/***************************************************************************
- *ACB_QUEUE_53_CONFIGURATION - ACB Queue 53 Configuration Register
- ***************************************************************************/
-/* SWITCH_ACB :: ACB_QUEUE_53_CONFIGURATION :: pessimistic_mode_en [31:31] */
-#define BCHP_SWITCH_ACB_ACB_QUEUE_53_CONFIGURATION_pessimistic_mode_en_MASK 0x80000000
-#define BCHP_SWITCH_ACB_ACB_QUEUE_53_CONFIGURATION_pessimistic_mode_en_SHIFT 31
-#define BCHP_SWITCH_ACB_ACB_QUEUE_53_CONFIGURATION_pessimistic_mode_en_DEFAULT 0x00000000
-#define BCHP_SWITCH_ACB_ACB_QUEUE_53_CONFIGURATION_pessimistic_mode_en_GISB 1
-#define BCHP_SWITCH_ACB_ACB_QUEUE_53_CONFIGURATION_pessimistic_mode_en_PORT 0
-
-/* union - case input_is_gisb [30:25] */
-/* SWITCH_ACB :: ACB_QUEUE_53_CONFIGURATION :: input_is_gisb :: pktlen [30:25] */
-#define BCHP_SWITCH_ACB_ACB_QUEUE_53_CONFIGURATION_input_is_gisb_pktlen_MASK 0x7e000000
-#define BCHP_SWITCH_ACB_ACB_QUEUE_53_CONFIGURATION_input_is_gisb_pktlen_SHIFT 25
-#define BCHP_SWITCH_ACB_ACB_QUEUE_53_CONFIGURATION_input_is_gisb_pktlen_DEFAULT 0x00000000
-
-/* union - case input_is_acb_queue_53_configuration [30:25] */
-/* SWITCH_ACB :: ACB_QUEUE_53_CONFIGURATION :: input_is_acb_queue_53_configuration :: pktlen [30:25] */
-#define BCHP_SWITCH_ACB_ACB_QUEUE_53_CONFIGURATION_input_is_acb_queue_53_configuration_pktlen_MASK 0x7e000000
-#define BCHP_SWITCH_ACB_ACB_QUEUE_53_CONFIGURATION_input_is_acb_queue_53_configuration_pktlen_SHIFT 25
-#define BCHP_SWITCH_ACB_ACB_QUEUE_53_CONFIGURATION_input_is_acb_queue_53_configuration_pktlen_DEFAULT 0x00000000
-
-/* SWITCH_ACB :: ACB_QUEUE_53_CONFIGURATION :: total_xon_en [24:24] */
-#define BCHP_SWITCH_ACB_ACB_QUEUE_53_CONFIGURATION_total_xon_en_MASK 0x01000000
-#define BCHP_SWITCH_ACB_ACB_QUEUE_53_CONFIGURATION_total_xon_en_SHIFT 24
-#define BCHP_SWITCH_ACB_ACB_QUEUE_53_CONFIGURATION_total_xon_en_DEFAULT 0x00000000
-
-/* SWITCH_ACB :: ACB_QUEUE_53_CONFIGURATION :: total_xoff_en [23:23] */
-#define BCHP_SWITCH_ACB_ACB_QUEUE_53_CONFIGURATION_total_xoff_en_MASK 0x00800000
-#define BCHP_SWITCH_ACB_ACB_QUEUE_53_CONFIGURATION_total_xoff_en_SHIFT 23
-#define BCHP_SWITCH_ACB_ACB_QUEUE_53_CONFIGURATION_total_xoff_en_DEFAULT 0x00000000
-
-/* SWITCH_ACB :: ACB_QUEUE_53_CONFIGURATION :: total_xoff_threshold [22:12] */
-#define BCHP_SWITCH_ACB_ACB_QUEUE_53_CONFIGURATION_total_xoff_threshold_MASK 0x007ff000
-#define BCHP_SWITCH_ACB_ACB_QUEUE_53_CONFIGURATION_total_xoff_threshold_SHIFT 12
-#define BCHP_SWITCH_ACB_ACB_QUEUE_53_CONFIGURATION_total_xoff_threshold_DEFAULT 0x00000000
-
-/* SWITCH_ACB :: ACB_QUEUE_53_CONFIGURATION :: xon_en [11:11] */
-#define BCHP_SWITCH_ACB_ACB_QUEUE_53_CONFIGURATION_xon_en_MASK 0x00000800
-#define BCHP_SWITCH_ACB_ACB_QUEUE_53_CONFIGURATION_xon_en_SHIFT 11
-#define BCHP_SWITCH_ACB_ACB_QUEUE_53_CONFIGURATION_xon_en_DEFAULT 0x00000000
-
-/* SWITCH_ACB :: ACB_QUEUE_53_CONFIGURATION :: xoff_threshold [10:00] */
-#define BCHP_SWITCH_ACB_ACB_QUEUE_53_CONFIGURATION_xoff_threshold_MASK 0x000007ff
-#define BCHP_SWITCH_ACB_ACB_QUEUE_53_CONFIGURATION_xoff_threshold_SHIFT 0
-#define BCHP_SWITCH_ACB_ACB_QUEUE_53_CONFIGURATION_xoff_threshold_DEFAULT 0x00000000
-
-/***************************************************************************
- *ACB_QUEUE_54_CONFIGURATION - ACB Queue 54 Configuration Register
- ***************************************************************************/
-/* SWITCH_ACB :: ACB_QUEUE_54_CONFIGURATION :: pessimistic_mode_en [31:31] */
-#define BCHP_SWITCH_ACB_ACB_QUEUE_54_CONFIGURATION_pessimistic_mode_en_MASK 0x80000000
-#define BCHP_SWITCH_ACB_ACB_QUEUE_54_CONFIGURATION_pessimistic_mode_en_SHIFT 31
-#define BCHP_SWITCH_ACB_ACB_QUEUE_54_CONFIGURATION_pessimistic_mode_en_DEFAULT 0x00000000
-#define BCHP_SWITCH_ACB_ACB_QUEUE_54_CONFIGURATION_pessimistic_mode_en_GISB 1
-#define BCHP_SWITCH_ACB_ACB_QUEUE_54_CONFIGURATION_pessimistic_mode_en_PORT 0
-
-/* union - case input_is_gisb [30:25] */
-/* SWITCH_ACB :: ACB_QUEUE_54_CONFIGURATION :: input_is_gisb :: pktlen [30:25] */
-#define BCHP_SWITCH_ACB_ACB_QUEUE_54_CONFIGURATION_input_is_gisb_pktlen_MASK 0x7e000000
-#define BCHP_SWITCH_ACB_ACB_QUEUE_54_CONFIGURATION_input_is_gisb_pktlen_SHIFT 25
-#define BCHP_SWITCH_ACB_ACB_QUEUE_54_CONFIGURATION_input_is_gisb_pktlen_DEFAULT 0x00000000
-
-/* union - case input_is_acb_queue_54_configuration [30:25] */
-/* SWITCH_ACB :: ACB_QUEUE_54_CONFIGURATION :: input_is_acb_queue_54_configuration :: pktlen [30:25] */
-#define BCHP_SWITCH_ACB_ACB_QUEUE_54_CONFIGURATION_input_is_acb_queue_54_configuration_pktlen_MASK 0x7e000000
-#define BCHP_SWITCH_ACB_ACB_QUEUE_54_CONFIGURATION_input_is_acb_queue_54_configuration_pktlen_SHIFT 25
-#define BCHP_SWITCH_ACB_ACB_QUEUE_54_CONFIGURATION_input_is_acb_queue_54_configuration_pktlen_DEFAULT 0x00000000
-
-/* SWITCH_ACB :: ACB_QUEUE_54_CONFIGURATION :: total_xon_en [24:24] */
-#define BCHP_SWITCH_ACB_ACB_QUEUE_54_CONFIGURATION_total_xon_en_MASK 0x01000000
-#define BCHP_SWITCH_ACB_ACB_QUEUE_54_CONFIGURATION_total_xon_en_SHIFT 24
-#define BCHP_SWITCH_ACB_ACB_QUEUE_54_CONFIGURATION_total_xon_en_DEFAULT 0x00000000
-
-/* SWITCH_ACB :: ACB_QUEUE_54_CONFIGURATION :: total_xoff_en [23:23] */
-#define BCHP_SWITCH_ACB_ACB_QUEUE_54_CONFIGURATION_total_xoff_en_MASK 0x00800000
-#define BCHP_SWITCH_ACB_ACB_QUEUE_54_CONFIGURATION_total_xoff_en_SHIFT 23
-#define BCHP_SWITCH_ACB_ACB_QUEUE_54_CONFIGURATION_total_xoff_en_DEFAULT 0x00000000
-
-/* SWITCH_ACB :: ACB_QUEUE_54_CONFIGURATION :: total_xoff_threshold [22:12] */
-#define BCHP_SWITCH_ACB_ACB_QUEUE_54_CONFIGURATION_total_xoff_threshold_MASK 0x007ff000
-#define BCHP_SWITCH_ACB_ACB_QUEUE_54_CONFIGURATION_total_xoff_threshold_SHIFT 12
-#define BCHP_SWITCH_ACB_ACB_QUEUE_54_CONFIGURATION_total_xoff_threshold_DEFAULT 0x00000000
-
-/* SWITCH_ACB :: ACB_QUEUE_54_CONFIGURATION :: xon_en [11:11] */
-#define BCHP_SWITCH_ACB_ACB_QUEUE_54_CONFIGURATION_xon_en_MASK 0x00000800
-#define BCHP_SWITCH_ACB_ACB_QUEUE_54_CONFIGURATION_xon_en_SHIFT 11
-#define BCHP_SWITCH_ACB_ACB_QUEUE_54_CONFIGURATION_xon_en_DEFAULT 0x00000000
-
-/* SWITCH_ACB :: ACB_QUEUE_54_CONFIGURATION :: xoff_threshold [10:00] */
-#define BCHP_SWITCH_ACB_ACB_QUEUE_54_CONFIGURATION_xoff_threshold_MASK 0x000007ff
-#define BCHP_SWITCH_ACB_ACB_QUEUE_54_CONFIGURATION_xoff_threshold_SHIFT 0
-#define BCHP_SWITCH_ACB_ACB_QUEUE_54_CONFIGURATION_xoff_threshold_DEFAULT 0x00000000
-
-/***************************************************************************
- *ACB_QUEUE_55_CONFIGURATION - ACB Queue 55 Configuration Register
- ***************************************************************************/
-/* SWITCH_ACB :: ACB_QUEUE_55_CONFIGURATION :: pessimistic_mode_en [31:31] */
-#define BCHP_SWITCH_ACB_ACB_QUEUE_55_CONFIGURATION_pessimistic_mode_en_MASK 0x80000000
-#define BCHP_SWITCH_ACB_ACB_QUEUE_55_CONFIGURATION_pessimistic_mode_en_SHIFT 31
-#define BCHP_SWITCH_ACB_ACB_QUEUE_55_CONFIGURATION_pessimistic_mode_en_DEFAULT 0x00000000
-#define BCHP_SWITCH_ACB_ACB_QUEUE_55_CONFIGURATION_pessimistic_mode_en_GISB 1
-#define BCHP_SWITCH_ACB_ACB_QUEUE_55_CONFIGURATION_pessimistic_mode_en_PORT 0
-
-/* union - case input_is_gisb [30:25] */
-/* SWITCH_ACB :: ACB_QUEUE_55_CONFIGURATION :: input_is_gisb :: pktlen [30:25] */
-#define BCHP_SWITCH_ACB_ACB_QUEUE_55_CONFIGURATION_input_is_gisb_pktlen_MASK 0x7e000000
-#define BCHP_SWITCH_ACB_ACB_QUEUE_55_CONFIGURATION_input_is_gisb_pktlen_SHIFT 25
-#define BCHP_SWITCH_ACB_ACB_QUEUE_55_CONFIGURATION_input_is_gisb_pktlen_DEFAULT 0x00000000
-
-/* union - case input_is_acb_queue_55_configuration [30:25] */
-/* SWITCH_ACB :: ACB_QUEUE_55_CONFIGURATION :: input_is_acb_queue_55_configuration :: pktlen [30:25] */
-#define BCHP_SWITCH_ACB_ACB_QUEUE_55_CONFIGURATION_input_is_acb_queue_55_configuration_pktlen_MASK 0x7e000000
-#define BCHP_SWITCH_ACB_ACB_QUEUE_55_CONFIGURATION_input_is_acb_queue_55_configuration_pktlen_SHIFT 25
-#define BCHP_SWITCH_ACB_ACB_QUEUE_55_CONFIGURATION_input_is_acb_queue_55_configuration_pktlen_DEFAULT 0x00000000
-
-/* SWITCH_ACB :: ACB_QUEUE_55_CONFIGURATION :: total_xon_en [24:24] */
-#define BCHP_SWITCH_ACB_ACB_QUEUE_55_CONFIGURATION_total_xon_en_MASK 0x01000000
-#define BCHP_SWITCH_ACB_ACB_QUEUE_55_CONFIGURATION_total_xon_en_SHIFT 24
-#define BCHP_SWITCH_ACB_ACB_QUEUE_55_CONFIGURATION_total_xon_en_DEFAULT 0x00000000
-
-/* SWITCH_ACB :: ACB_QUEUE_55_CONFIGURATION :: total_xoff_en [23:23] */
-#define BCHP_SWITCH_ACB_ACB_QUEUE_55_CONFIGURATION_total_xoff_en_MASK 0x00800000
-#define BCHP_SWITCH_ACB_ACB_QUEUE_55_CONFIGURATION_total_xoff_en_SHIFT 23
-#define BCHP_SWITCH_ACB_ACB_QUEUE_55_CONFIGURATION_total_xoff_en_DEFAULT 0x00000000
-
-/* SWITCH_ACB :: ACB_QUEUE_55_CONFIGURATION :: total_xoff_threshold [22:12] */
-#define BCHP_SWITCH_ACB_ACB_QUEUE_55_CONFIGURATION_total_xoff_threshold_MASK 0x007ff000
-#define BCHP_SWITCH_ACB_ACB_QUEUE_55_CONFIGURATION_total_xoff_threshold_SHIFT 12
-#define BCHP_SWITCH_ACB_ACB_QUEUE_55_CONFIGURATION_total_xoff_threshold_DEFAULT 0x00000000
-
-/* SWITCH_ACB :: ACB_QUEUE_55_CONFIGURATION :: xon_en [11:11] */
-#define BCHP_SWITCH_ACB_ACB_QUEUE_55_CONFIGURATION_xon_en_MASK 0x00000800
-#define BCHP_SWITCH_ACB_ACB_QUEUE_55_CONFIGURATION_xon_en_SHIFT 11
-#define BCHP_SWITCH_ACB_ACB_QUEUE_55_CONFIGURATION_xon_en_DEFAULT 0x00000000
-
-/* SWITCH_ACB :: ACB_QUEUE_55_CONFIGURATION :: xoff_threshold [10:00] */
-#define BCHP_SWITCH_ACB_ACB_QUEUE_55_CONFIGURATION_xoff_threshold_MASK 0x000007ff
-#define BCHP_SWITCH_ACB_ACB_QUEUE_55_CONFIGURATION_xoff_threshold_SHIFT 0
-#define BCHP_SWITCH_ACB_ACB_QUEUE_55_CONFIGURATION_xoff_threshold_DEFAULT 0x00000000
-
-/***************************************************************************
- *ACB_QUEUE_56_CONFIGURATION - ACB Queue 56 Configuration Register
- ***************************************************************************/
-/* SWITCH_ACB :: ACB_QUEUE_56_CONFIGURATION :: pessimistic_mode_en [31:31] */
-#define BCHP_SWITCH_ACB_ACB_QUEUE_56_CONFIGURATION_pessimistic_mode_en_MASK 0x80000000
-#define BCHP_SWITCH_ACB_ACB_QUEUE_56_CONFIGURATION_pessimistic_mode_en_SHIFT 31
-#define BCHP_SWITCH_ACB_ACB_QUEUE_56_CONFIGURATION_pessimistic_mode_en_DEFAULT 0x00000000
-#define BCHP_SWITCH_ACB_ACB_QUEUE_56_CONFIGURATION_pessimistic_mode_en_GISB 1
-#define BCHP_SWITCH_ACB_ACB_QUEUE_56_CONFIGURATION_pessimistic_mode_en_PORT 0
-
-/* union - case input_is_gisb [30:25] */
-/* SWITCH_ACB :: ACB_QUEUE_56_CONFIGURATION :: input_is_gisb :: pktlen [30:25] */
-#define BCHP_SWITCH_ACB_ACB_QUEUE_56_CONFIGURATION_input_is_gisb_pktlen_MASK 0x7e000000
-#define BCHP_SWITCH_ACB_ACB_QUEUE_56_CONFIGURATION_input_is_gisb_pktlen_SHIFT 25
-#define BCHP_SWITCH_ACB_ACB_QUEUE_56_CONFIGURATION_input_is_gisb_pktlen_DEFAULT 0x00000000
-
-/* union - case input_is_acb_queue_56_configuration [30:25] */
-/* SWITCH_ACB :: ACB_QUEUE_56_CONFIGURATION :: input_is_acb_queue_56_configuration :: pktlen [30:25] */
-#define BCHP_SWITCH_ACB_ACB_QUEUE_56_CONFIGURATION_input_is_acb_queue_56_configuration_pktlen_MASK 0x7e000000
-#define BCHP_SWITCH_ACB_ACB_QUEUE_56_CONFIGURATION_input_is_acb_queue_56_configuration_pktlen_SHIFT 25
-#define BCHP_SWITCH_ACB_ACB_QUEUE_56_CONFIGURATION_input_is_acb_queue_56_configuration_pktlen_DEFAULT 0x00000000
-
-/* SWITCH_ACB :: ACB_QUEUE_56_CONFIGURATION :: total_xon_en [24:24] */
-#define BCHP_SWITCH_ACB_ACB_QUEUE_56_CONFIGURATION_total_xon_en_MASK 0x01000000
-#define BCHP_SWITCH_ACB_ACB_QUEUE_56_CONFIGURATION_total_xon_en_SHIFT 24
-#define BCHP_SWITCH_ACB_ACB_QUEUE_56_CONFIGURATION_total_xon_en_DEFAULT 0x00000000
-
-/* SWITCH_ACB :: ACB_QUEUE_56_CONFIGURATION :: total_xoff_en [23:23] */
-#define BCHP_SWITCH_ACB_ACB_QUEUE_56_CONFIGURATION_total_xoff_en_MASK 0x00800000
-#define BCHP_SWITCH_ACB_ACB_QUEUE_56_CONFIGURATION_total_xoff_en_SHIFT 23
-#define BCHP_SWITCH_ACB_ACB_QUEUE_56_CONFIGURATION_total_xoff_en_DEFAULT 0x00000000
-
-/* SWITCH_ACB :: ACB_QUEUE_56_CONFIGURATION :: total_xoff_threshold [22:12] */
-#define BCHP_SWITCH_ACB_ACB_QUEUE_56_CONFIGURATION_total_xoff_threshold_MASK 0x007ff000
-#define BCHP_SWITCH_ACB_ACB_QUEUE_56_CONFIGURATION_total_xoff_threshold_SHIFT 12
-#define BCHP_SWITCH_ACB_ACB_QUEUE_56_CONFIGURATION_total_xoff_threshold_DEFAULT 0x00000000
-
-/* SWITCH_ACB :: ACB_QUEUE_56_CONFIGURATION :: xon_en [11:11] */
-#define BCHP_SWITCH_ACB_ACB_QUEUE_56_CONFIGURATION_xon_en_MASK 0x00000800
-#define BCHP_SWITCH_ACB_ACB_QUEUE_56_CONFIGURATION_xon_en_SHIFT 11
-#define BCHP_SWITCH_ACB_ACB_QUEUE_56_CONFIGURATION_xon_en_DEFAULT 0x00000000
-
-/* SWITCH_ACB :: ACB_QUEUE_56_CONFIGURATION :: xoff_threshold [10:00] */
-#define BCHP_SWITCH_ACB_ACB_QUEUE_56_CONFIGURATION_xoff_threshold_MASK 0x000007ff
-#define BCHP_SWITCH_ACB_ACB_QUEUE_56_CONFIGURATION_xoff_threshold_SHIFT 0
-#define BCHP_SWITCH_ACB_ACB_QUEUE_56_CONFIGURATION_xoff_threshold_DEFAULT 0x00000000
-
-/***************************************************************************
- *ACB_QUEUE_57_CONFIGURATION - ACB Queue 57 Configuration Register
- ***************************************************************************/
-/* SWITCH_ACB :: ACB_QUEUE_57_CONFIGURATION :: pessimistic_mode_en [31:31] */
-#define BCHP_SWITCH_ACB_ACB_QUEUE_57_CONFIGURATION_pessimistic_mode_en_MASK 0x80000000
-#define BCHP_SWITCH_ACB_ACB_QUEUE_57_CONFIGURATION_pessimistic_mode_en_SHIFT 31
-#define BCHP_SWITCH_ACB_ACB_QUEUE_57_CONFIGURATION_pessimistic_mode_en_DEFAULT 0x00000000
-#define BCHP_SWITCH_ACB_ACB_QUEUE_57_CONFIGURATION_pessimistic_mode_en_GISB 1
-#define BCHP_SWITCH_ACB_ACB_QUEUE_57_CONFIGURATION_pessimistic_mode_en_PORT 0
-
-/* union - case input_is_gisb [30:25] */
-/* SWITCH_ACB :: ACB_QUEUE_57_CONFIGURATION :: input_is_gisb :: pktlen [30:25] */
-#define BCHP_SWITCH_ACB_ACB_QUEUE_57_CONFIGURATION_input_is_gisb_pktlen_MASK 0x7e000000
-#define BCHP_SWITCH_ACB_ACB_QUEUE_57_CONFIGURATION_input_is_gisb_pktlen_SHIFT 25
-#define BCHP_SWITCH_ACB_ACB_QUEUE_57_CONFIGURATION_input_is_gisb_pktlen_DEFAULT 0x00000000
-
-/* union - case input_is_acb_queue_57_configuration [30:25] */
-/* SWITCH_ACB :: ACB_QUEUE_57_CONFIGURATION :: input_is_acb_queue_57_configuration :: pktlen [30:25] */
-#define BCHP_SWITCH_ACB_ACB_QUEUE_57_CONFIGURATION_input_is_acb_queue_57_configuration_pktlen_MASK 0x7e000000
-#define BCHP_SWITCH_ACB_ACB_QUEUE_57_CONFIGURATION_input_is_acb_queue_57_configuration_pktlen_SHIFT 25
-#define BCHP_SWITCH_ACB_ACB_QUEUE_57_CONFIGURATION_input_is_acb_queue_57_configuration_pktlen_DEFAULT 0x00000000
-
-/* SWITCH_ACB :: ACB_QUEUE_57_CONFIGURATION :: total_xon_en [24:24] */
-#define BCHP_SWITCH_ACB_ACB_QUEUE_57_CONFIGURATION_total_xon_en_MASK 0x01000000
-#define BCHP_SWITCH_ACB_ACB_QUEUE_57_CONFIGURATION_total_xon_en_SHIFT 24
-#define BCHP_SWITCH_ACB_ACB_QUEUE_57_CONFIGURATION_total_xon_en_DEFAULT 0x00000000
-
-/* SWITCH_ACB :: ACB_QUEUE_57_CONFIGURATION :: total_xoff_en [23:23] */
-#define BCHP_SWITCH_ACB_ACB_QUEUE_57_CONFIGURATION_total_xoff_en_MASK 0x00800000
-#define BCHP_SWITCH_ACB_ACB_QUEUE_57_CONFIGURATION_total_xoff_en_SHIFT 23
-#define BCHP_SWITCH_ACB_ACB_QUEUE_57_CONFIGURATION_total_xoff_en_DEFAULT 0x00000000
-
-/* SWITCH_ACB :: ACB_QUEUE_57_CONFIGURATION :: total_xoff_threshold [22:12] */
-#define BCHP_SWITCH_ACB_ACB_QUEUE_57_CONFIGURATION_total_xoff_threshold_MASK 0x007ff000
-#define BCHP_SWITCH_ACB_ACB_QUEUE_57_CONFIGURATION_total_xoff_threshold_SHIFT 12
-#define BCHP_SWITCH_ACB_ACB_QUEUE_57_CONFIGURATION_total_xoff_threshold_DEFAULT 0x00000000
-
-/* SWITCH_ACB :: ACB_QUEUE_57_CONFIGURATION :: xon_en [11:11] */
-#define BCHP_SWITCH_ACB_ACB_QUEUE_57_CONFIGURATION_xon_en_MASK 0x00000800
-#define BCHP_SWITCH_ACB_ACB_QUEUE_57_CONFIGURATION_xon_en_SHIFT 11
-#define BCHP_SWITCH_ACB_ACB_QUEUE_57_CONFIGURATION_xon_en_DEFAULT 0x00000000
-
-/* SWITCH_ACB :: ACB_QUEUE_57_CONFIGURATION :: xoff_threshold [10:00] */
-#define BCHP_SWITCH_ACB_ACB_QUEUE_57_CONFIGURATION_xoff_threshold_MASK 0x000007ff
-#define BCHP_SWITCH_ACB_ACB_QUEUE_57_CONFIGURATION_xoff_threshold_SHIFT 0
-#define BCHP_SWITCH_ACB_ACB_QUEUE_57_CONFIGURATION_xoff_threshold_DEFAULT 0x00000000
-
-/***************************************************************************
- *ACB_QUEUE_58_CONFIGURATION - ACB Queue 58 Configuration Register
- ***************************************************************************/
-/* SWITCH_ACB :: ACB_QUEUE_58_CONFIGURATION :: pessimistic_mode_en [31:31] */
-#define BCHP_SWITCH_ACB_ACB_QUEUE_58_CONFIGURATION_pessimistic_mode_en_MASK 0x80000000
-#define BCHP_SWITCH_ACB_ACB_QUEUE_58_CONFIGURATION_pessimistic_mode_en_SHIFT 31
-#define BCHP_SWITCH_ACB_ACB_QUEUE_58_CONFIGURATION_pessimistic_mode_en_DEFAULT 0x00000000
-#define BCHP_SWITCH_ACB_ACB_QUEUE_58_CONFIGURATION_pessimistic_mode_en_GISB 1
-#define BCHP_SWITCH_ACB_ACB_QUEUE_58_CONFIGURATION_pessimistic_mode_en_PORT 0
-
-/* union - case input_is_gisb [30:25] */
-/* SWITCH_ACB :: ACB_QUEUE_58_CONFIGURATION :: input_is_gisb :: pktlen [30:25] */
-#define BCHP_SWITCH_ACB_ACB_QUEUE_58_CONFIGURATION_input_is_gisb_pktlen_MASK 0x7e000000
-#define BCHP_SWITCH_ACB_ACB_QUEUE_58_CONFIGURATION_input_is_gisb_pktlen_SHIFT 25
-#define BCHP_SWITCH_ACB_ACB_QUEUE_58_CONFIGURATION_input_is_gisb_pktlen_DEFAULT 0x00000000
-
-/* union - case input_is_acb_queue_58_configuration [30:25] */
-/* SWITCH_ACB :: ACB_QUEUE_58_CONFIGURATION :: input_is_acb_queue_58_configuration :: pktlen [30:25] */
-#define BCHP_SWITCH_ACB_ACB_QUEUE_58_CONFIGURATION_input_is_acb_queue_58_configuration_pktlen_MASK 0x7e000000
-#define BCHP_SWITCH_ACB_ACB_QUEUE_58_CONFIGURATION_input_is_acb_queue_58_configuration_pktlen_SHIFT 25
-#define BCHP_SWITCH_ACB_ACB_QUEUE_58_CONFIGURATION_input_is_acb_queue_58_configuration_pktlen_DEFAULT 0x00000000
-
-/* SWITCH_ACB :: ACB_QUEUE_58_CONFIGURATION :: total_xon_en [24:24] */
-#define BCHP_SWITCH_ACB_ACB_QUEUE_58_CONFIGURATION_total_xon_en_MASK 0x01000000
-#define BCHP_SWITCH_ACB_ACB_QUEUE_58_CONFIGURATION_total_xon_en_SHIFT 24
-#define BCHP_SWITCH_ACB_ACB_QUEUE_58_CONFIGURATION_total_xon_en_DEFAULT 0x00000000
-
-/* SWITCH_ACB :: ACB_QUEUE_58_CONFIGURATION :: total_xoff_en [23:23] */
-#define BCHP_SWITCH_ACB_ACB_QUEUE_58_CONFIGURATION_total_xoff_en_MASK 0x00800000
-#define BCHP_SWITCH_ACB_ACB_QUEUE_58_CONFIGURATION_total_xoff_en_SHIFT 23
-#define BCHP_SWITCH_ACB_ACB_QUEUE_58_CONFIGURATION_total_xoff_en_DEFAULT 0x00000000
-
-/* SWITCH_ACB :: ACB_QUEUE_58_CONFIGURATION :: total_xoff_threshold [22:12] */
-#define BCHP_SWITCH_ACB_ACB_QUEUE_58_CONFIGURATION_total_xoff_threshold_MASK 0x007ff000
-#define BCHP_SWITCH_ACB_ACB_QUEUE_58_CONFIGURATION_total_xoff_threshold_SHIFT 12
-#define BCHP_SWITCH_ACB_ACB_QUEUE_58_CONFIGURATION_total_xoff_threshold_DEFAULT 0x00000000
-
-/* SWITCH_ACB :: ACB_QUEUE_58_CONFIGURATION :: xon_en [11:11] */
-#define BCHP_SWITCH_ACB_ACB_QUEUE_58_CONFIGURATION_xon_en_MASK 0x00000800
-#define BCHP_SWITCH_ACB_ACB_QUEUE_58_CONFIGURATION_xon_en_SHIFT 11
-#define BCHP_SWITCH_ACB_ACB_QUEUE_58_CONFIGURATION_xon_en_DEFAULT 0x00000000
-
-/* SWITCH_ACB :: ACB_QUEUE_58_CONFIGURATION :: xoff_threshold [10:00] */
-#define BCHP_SWITCH_ACB_ACB_QUEUE_58_CONFIGURATION_xoff_threshold_MASK 0x000007ff
-#define BCHP_SWITCH_ACB_ACB_QUEUE_58_CONFIGURATION_xoff_threshold_SHIFT 0
-#define BCHP_SWITCH_ACB_ACB_QUEUE_58_CONFIGURATION_xoff_threshold_DEFAULT 0x00000000
-
-/***************************************************************************
- *ACB_QUEUE_59_CONFIGURATION - ACB Queue 59 Configuration Register
- ***************************************************************************/
-/* SWITCH_ACB :: ACB_QUEUE_59_CONFIGURATION :: pessimistic_mode_en [31:31] */
-#define BCHP_SWITCH_ACB_ACB_QUEUE_59_CONFIGURATION_pessimistic_mode_en_MASK 0x80000000
-#define BCHP_SWITCH_ACB_ACB_QUEUE_59_CONFIGURATION_pessimistic_mode_en_SHIFT 31
-#define BCHP_SWITCH_ACB_ACB_QUEUE_59_CONFIGURATION_pessimistic_mode_en_DEFAULT 0x00000000
-#define BCHP_SWITCH_ACB_ACB_QUEUE_59_CONFIGURATION_pessimistic_mode_en_GISB 1
-#define BCHP_SWITCH_ACB_ACB_QUEUE_59_CONFIGURATION_pessimistic_mode_en_PORT 0
-
-/* union - case input_is_gisb [30:25] */
-/* SWITCH_ACB :: ACB_QUEUE_59_CONFIGURATION :: input_is_gisb :: pktlen [30:25] */
-#define BCHP_SWITCH_ACB_ACB_QUEUE_59_CONFIGURATION_input_is_gisb_pktlen_MASK 0x7e000000
-#define BCHP_SWITCH_ACB_ACB_QUEUE_59_CONFIGURATION_input_is_gisb_pktlen_SHIFT 25
-#define BCHP_SWITCH_ACB_ACB_QUEUE_59_CONFIGURATION_input_is_gisb_pktlen_DEFAULT 0x00000000
-
-/* union - case input_is_acb_queue_59_configuration [30:25] */
-/* SWITCH_ACB :: ACB_QUEUE_59_CONFIGURATION :: input_is_acb_queue_59_configuration :: pktlen [30:25] */
-#define BCHP_SWITCH_ACB_ACB_QUEUE_59_CONFIGURATION_input_is_acb_queue_59_configuration_pktlen_MASK 0x7e000000
-#define BCHP_SWITCH_ACB_ACB_QUEUE_59_CONFIGURATION_input_is_acb_queue_59_configuration_pktlen_SHIFT 25
-#define BCHP_SWITCH_ACB_ACB_QUEUE_59_CONFIGURATION_input_is_acb_queue_59_configuration_pktlen_DEFAULT 0x00000000
-
-/* SWITCH_ACB :: ACB_QUEUE_59_CONFIGURATION :: total_xon_en [24:24] */
-#define BCHP_SWITCH_ACB_ACB_QUEUE_59_CONFIGURATION_total_xon_en_MASK 0x01000000
-#define BCHP_SWITCH_ACB_ACB_QUEUE_59_CONFIGURATION_total_xon_en_SHIFT 24
-#define BCHP_SWITCH_ACB_ACB_QUEUE_59_CONFIGURATION_total_xon_en_DEFAULT 0x00000000
-
-/* SWITCH_ACB :: ACB_QUEUE_59_CONFIGURATION :: total_xoff_en [23:23] */
-#define BCHP_SWITCH_ACB_ACB_QUEUE_59_CONFIGURATION_total_xoff_en_MASK 0x00800000
-#define BCHP_SWITCH_ACB_ACB_QUEUE_59_CONFIGURATION_total_xoff_en_SHIFT 23
-#define BCHP_SWITCH_ACB_ACB_QUEUE_59_CONFIGURATION_total_xoff_en_DEFAULT 0x00000000
-
-/* SWITCH_ACB :: ACB_QUEUE_59_CONFIGURATION :: total_xoff_threshold [22:12] */
-#define BCHP_SWITCH_ACB_ACB_QUEUE_59_CONFIGURATION_total_xoff_threshold_MASK 0x007ff000
-#define BCHP_SWITCH_ACB_ACB_QUEUE_59_CONFIGURATION_total_xoff_threshold_SHIFT 12
-#define BCHP_SWITCH_ACB_ACB_QUEUE_59_CONFIGURATION_total_xoff_threshold_DEFAULT 0x00000000
-
-/* SWITCH_ACB :: ACB_QUEUE_59_CONFIGURATION :: xon_en [11:11] */
-#define BCHP_SWITCH_ACB_ACB_QUEUE_59_CONFIGURATION_xon_en_MASK 0x00000800
-#define BCHP_SWITCH_ACB_ACB_QUEUE_59_CONFIGURATION_xon_en_SHIFT 11
-#define BCHP_SWITCH_ACB_ACB_QUEUE_59_CONFIGURATION_xon_en_DEFAULT 0x00000000
-
-/* SWITCH_ACB :: ACB_QUEUE_59_CONFIGURATION :: xoff_threshold [10:00] */
-#define BCHP_SWITCH_ACB_ACB_QUEUE_59_CONFIGURATION_xoff_threshold_MASK 0x000007ff
-#define BCHP_SWITCH_ACB_ACB_QUEUE_59_CONFIGURATION_xoff_threshold_SHIFT 0
-#define BCHP_SWITCH_ACB_ACB_QUEUE_59_CONFIGURATION_xoff_threshold_DEFAULT 0x00000000
-
-/***************************************************************************
- *ACB_QUEUE_60_CONFIGURATION - ACB Queue 60 Configuration Register
- ***************************************************************************/
-/* SWITCH_ACB :: ACB_QUEUE_60_CONFIGURATION :: pessimistic_mode_en [31:31] */
-#define BCHP_SWITCH_ACB_ACB_QUEUE_60_CONFIGURATION_pessimistic_mode_en_MASK 0x80000000
-#define BCHP_SWITCH_ACB_ACB_QUEUE_60_CONFIGURATION_pessimistic_mode_en_SHIFT 31
-#define BCHP_SWITCH_ACB_ACB_QUEUE_60_CONFIGURATION_pessimistic_mode_en_DEFAULT 0x00000000
-#define BCHP_SWITCH_ACB_ACB_QUEUE_60_CONFIGURATION_pessimistic_mode_en_GISB 1
-#define BCHP_SWITCH_ACB_ACB_QUEUE_60_CONFIGURATION_pessimistic_mode_en_PORT 0
-
-/* union - case input_is_gisb [30:25] */
-/* SWITCH_ACB :: ACB_QUEUE_60_CONFIGURATION :: input_is_gisb :: pktlen [30:25] */
-#define BCHP_SWITCH_ACB_ACB_QUEUE_60_CONFIGURATION_input_is_gisb_pktlen_MASK 0x7e000000
-#define BCHP_SWITCH_ACB_ACB_QUEUE_60_CONFIGURATION_input_is_gisb_pktlen_SHIFT 25
-#define BCHP_SWITCH_ACB_ACB_QUEUE_60_CONFIGURATION_input_is_gisb_pktlen_DEFAULT 0x00000000
-
-/* union - case input_is_acb_queue_60_configuration [30:25] */
-/* SWITCH_ACB :: ACB_QUEUE_60_CONFIGURATION :: input_is_acb_queue_60_configuration :: pktlen [30:25] */
-#define BCHP_SWITCH_ACB_ACB_QUEUE_60_CONFIGURATION_input_is_acb_queue_60_configuration_pktlen_MASK 0x7e000000
-#define BCHP_SWITCH_ACB_ACB_QUEUE_60_CONFIGURATION_input_is_acb_queue_60_configuration_pktlen_SHIFT 25
-#define BCHP_SWITCH_ACB_ACB_QUEUE_60_CONFIGURATION_input_is_acb_queue_60_configuration_pktlen_DEFAULT 0x00000000
-
-/* SWITCH_ACB :: ACB_QUEUE_60_CONFIGURATION :: total_xon_en [24:24] */
-#define BCHP_SWITCH_ACB_ACB_QUEUE_60_CONFIGURATION_total_xon_en_MASK 0x01000000
-#define BCHP_SWITCH_ACB_ACB_QUEUE_60_CONFIGURATION_total_xon_en_SHIFT 24
-#define BCHP_SWITCH_ACB_ACB_QUEUE_60_CONFIGURATION_total_xon_en_DEFAULT 0x00000000
-
-/* SWITCH_ACB :: ACB_QUEUE_60_CONFIGURATION :: total_xoff_en [23:23] */
-#define BCHP_SWITCH_ACB_ACB_QUEUE_60_CONFIGURATION_total_xoff_en_MASK 0x00800000
-#define BCHP_SWITCH_ACB_ACB_QUEUE_60_CONFIGURATION_total_xoff_en_SHIFT 23
-#define BCHP_SWITCH_ACB_ACB_QUEUE_60_CONFIGURATION_total_xoff_en_DEFAULT 0x00000000
-
-/* SWITCH_ACB :: ACB_QUEUE_60_CONFIGURATION :: total_xoff_threshold [22:12] */
-#define BCHP_SWITCH_ACB_ACB_QUEUE_60_CONFIGURATION_total_xoff_threshold_MASK 0x007ff000
-#define BCHP_SWITCH_ACB_ACB_QUEUE_60_CONFIGURATION_total_xoff_threshold_SHIFT 12
-#define BCHP_SWITCH_ACB_ACB_QUEUE_60_CONFIGURATION_total_xoff_threshold_DEFAULT 0x00000000
-
-/* SWITCH_ACB :: ACB_QUEUE_60_CONFIGURATION :: xon_en [11:11] */
-#define BCHP_SWITCH_ACB_ACB_QUEUE_60_CONFIGURATION_xon_en_MASK 0x00000800
-#define BCHP_SWITCH_ACB_ACB_QUEUE_60_CONFIGURATION_xon_en_SHIFT 11
-#define BCHP_SWITCH_ACB_ACB_QUEUE_60_CONFIGURATION_xon_en_DEFAULT 0x00000000
-
-/* SWITCH_ACB :: ACB_QUEUE_60_CONFIGURATION :: xoff_threshold [10:00] */
-#define BCHP_SWITCH_ACB_ACB_QUEUE_60_CONFIGURATION_xoff_threshold_MASK 0x000007ff
-#define BCHP_SWITCH_ACB_ACB_QUEUE_60_CONFIGURATION_xoff_threshold_SHIFT 0
-#define BCHP_SWITCH_ACB_ACB_QUEUE_60_CONFIGURATION_xoff_threshold_DEFAULT 0x00000000
-
-/***************************************************************************
- *ACB_QUEUE_61_CONFIGURATION - ACB Queue 61 Configuration Register
- ***************************************************************************/
-/* SWITCH_ACB :: ACB_QUEUE_61_CONFIGURATION :: pessimistic_mode_en [31:31] */
-#define BCHP_SWITCH_ACB_ACB_QUEUE_61_CONFIGURATION_pessimistic_mode_en_MASK 0x80000000
-#define BCHP_SWITCH_ACB_ACB_QUEUE_61_CONFIGURATION_pessimistic_mode_en_SHIFT 31
-#define BCHP_SWITCH_ACB_ACB_QUEUE_61_CONFIGURATION_pessimistic_mode_en_DEFAULT 0x00000000
-#define BCHP_SWITCH_ACB_ACB_QUEUE_61_CONFIGURATION_pessimistic_mode_en_GISB 1
-#define BCHP_SWITCH_ACB_ACB_QUEUE_61_CONFIGURATION_pessimistic_mode_en_PORT 0
-
-/* union - case input_is_gisb [30:25] */
-/* SWITCH_ACB :: ACB_QUEUE_61_CONFIGURATION :: input_is_gisb :: pktlen [30:25] */
-#define BCHP_SWITCH_ACB_ACB_QUEUE_61_CONFIGURATION_input_is_gisb_pktlen_MASK 0x7e000000
-#define BCHP_SWITCH_ACB_ACB_QUEUE_61_CONFIGURATION_input_is_gisb_pktlen_SHIFT 25
-#define BCHP_SWITCH_ACB_ACB_QUEUE_61_CONFIGURATION_input_is_gisb_pktlen_DEFAULT 0x00000000
-
-/* union - case input_is_acb_queue_61_configuration [30:25] */
-/* SWITCH_ACB :: ACB_QUEUE_61_CONFIGURATION :: input_is_acb_queue_61_configuration :: pktlen [30:25] */
-#define BCHP_SWITCH_ACB_ACB_QUEUE_61_CONFIGURATION_input_is_acb_queue_61_configuration_pktlen_MASK 0x7e000000
-#define BCHP_SWITCH_ACB_ACB_QUEUE_61_CONFIGURATION_input_is_acb_queue_61_configuration_pktlen_SHIFT 25
-#define BCHP_SWITCH_ACB_ACB_QUEUE_61_CONFIGURATION_input_is_acb_queue_61_configuration_pktlen_DEFAULT 0x00000000
-
-/* SWITCH_ACB :: ACB_QUEUE_61_CONFIGURATION :: total_xon_en [24:24] */
-#define BCHP_SWITCH_ACB_ACB_QUEUE_61_CONFIGURATION_total_xon_en_MASK 0x01000000
-#define BCHP_SWITCH_ACB_ACB_QUEUE_61_CONFIGURATION_total_xon_en_SHIFT 24
-#define BCHP_SWITCH_ACB_ACB_QUEUE_61_CONFIGURATION_total_xon_en_DEFAULT 0x00000000
-
-/* SWITCH_ACB :: ACB_QUEUE_61_CONFIGURATION :: total_xoff_en [23:23] */
-#define BCHP_SWITCH_ACB_ACB_QUEUE_61_CONFIGURATION_total_xoff_en_MASK 0x00800000
-#define BCHP_SWITCH_ACB_ACB_QUEUE_61_CONFIGURATION_total_xoff_en_SHIFT 23
-#define BCHP_SWITCH_ACB_ACB_QUEUE_61_CONFIGURATION_total_xoff_en_DEFAULT 0x00000000
-
-/* SWITCH_ACB :: ACB_QUEUE_61_CONFIGURATION :: total_xoff_threshold [22:12] */
-#define BCHP_SWITCH_ACB_ACB_QUEUE_61_CONFIGURATION_total_xoff_threshold_MASK 0x007ff000
-#define BCHP_SWITCH_ACB_ACB_QUEUE_61_CONFIGURATION_total_xoff_threshold_SHIFT 12
-#define BCHP_SWITCH_ACB_ACB_QUEUE_61_CONFIGURATION_total_xoff_threshold_DEFAULT 0x00000000
-
-/* SWITCH_ACB :: ACB_QUEUE_61_CONFIGURATION :: xon_en [11:11] */
-#define BCHP_SWITCH_ACB_ACB_QUEUE_61_CONFIGURATION_xon_en_MASK 0x00000800
-#define BCHP_SWITCH_ACB_ACB_QUEUE_61_CONFIGURATION_xon_en_SHIFT 11
-#define BCHP_SWITCH_ACB_ACB_QUEUE_61_CONFIGURATION_xon_en_DEFAULT 0x00000000
-
-/* SWITCH_ACB :: ACB_QUEUE_61_CONFIGURATION :: xoff_threshold [10:00] */
-#define BCHP_SWITCH_ACB_ACB_QUEUE_61_CONFIGURATION_xoff_threshold_MASK 0x000007ff
-#define BCHP_SWITCH_ACB_ACB_QUEUE_61_CONFIGURATION_xoff_threshold_SHIFT 0
-#define BCHP_SWITCH_ACB_ACB_QUEUE_61_CONFIGURATION_xoff_threshold_DEFAULT 0x00000000
-
-/***************************************************************************
- *ACB_QUEUE_62_CONFIGURATION - ACB Queue 62 Configuration Register
- ***************************************************************************/
-/* SWITCH_ACB :: ACB_QUEUE_62_CONFIGURATION :: pessimistic_mode_en [31:31] */
-#define BCHP_SWITCH_ACB_ACB_QUEUE_62_CONFIGURATION_pessimistic_mode_en_MASK 0x80000000
-#define BCHP_SWITCH_ACB_ACB_QUEUE_62_CONFIGURATION_pessimistic_mode_en_SHIFT 31
-#define BCHP_SWITCH_ACB_ACB_QUEUE_62_CONFIGURATION_pessimistic_mode_en_DEFAULT 0x00000000
-#define BCHP_SWITCH_ACB_ACB_QUEUE_62_CONFIGURATION_pessimistic_mode_en_GISB 1
-#define BCHP_SWITCH_ACB_ACB_QUEUE_62_CONFIGURATION_pessimistic_mode_en_PORT 0
-
-/* union - case input_is_gisb [30:25] */
-/* SWITCH_ACB :: ACB_QUEUE_62_CONFIGURATION :: input_is_gisb :: pktlen [30:25] */
-#define BCHP_SWITCH_ACB_ACB_QUEUE_62_CONFIGURATION_input_is_gisb_pktlen_MASK 0x7e000000
-#define BCHP_SWITCH_ACB_ACB_QUEUE_62_CONFIGURATION_input_is_gisb_pktlen_SHIFT 25
-#define BCHP_SWITCH_ACB_ACB_QUEUE_62_CONFIGURATION_input_is_gisb_pktlen_DEFAULT 0x00000000
-
-/* union - case input_is_acb_queue_62_configuration [30:25] */
-/* SWITCH_ACB :: ACB_QUEUE_62_CONFIGURATION :: input_is_acb_queue_62_configuration :: pktlen [30:25] */
-#define BCHP_SWITCH_ACB_ACB_QUEUE_62_CONFIGURATION_input_is_acb_queue_62_configuration_pktlen_MASK 0x7e000000
-#define BCHP_SWITCH_ACB_ACB_QUEUE_62_CONFIGURATION_input_is_acb_queue_62_configuration_pktlen_SHIFT 25
-#define BCHP_SWITCH_ACB_ACB_QUEUE_62_CONFIGURATION_input_is_acb_queue_62_configuration_pktlen_DEFAULT 0x00000000
-
-/* SWITCH_ACB :: ACB_QUEUE_62_CONFIGURATION :: total_xon_en [24:24] */
-#define BCHP_SWITCH_ACB_ACB_QUEUE_62_CONFIGURATION_total_xon_en_MASK 0x01000000
-#define BCHP_SWITCH_ACB_ACB_QUEUE_62_CONFIGURATION_total_xon_en_SHIFT 24
-#define BCHP_SWITCH_ACB_ACB_QUEUE_62_CONFIGURATION_total_xon_en_DEFAULT 0x00000000
-
-/* SWITCH_ACB :: ACB_QUEUE_62_CONFIGURATION :: total_xoff_en [23:23] */
-#define BCHP_SWITCH_ACB_ACB_QUEUE_62_CONFIGURATION_total_xoff_en_MASK 0x00800000
-#define BCHP_SWITCH_ACB_ACB_QUEUE_62_CONFIGURATION_total_xoff_en_SHIFT 23
-#define BCHP_SWITCH_ACB_ACB_QUEUE_62_CONFIGURATION_total_xoff_en_DEFAULT 0x00000000
-
-/* SWITCH_ACB :: ACB_QUEUE_62_CONFIGURATION :: total_xoff_threshold [22:12] */
-#define BCHP_SWITCH_ACB_ACB_QUEUE_62_CONFIGURATION_total_xoff_threshold_MASK 0x007ff000
-#define BCHP_SWITCH_ACB_ACB_QUEUE_62_CONFIGURATION_total_xoff_threshold_SHIFT 12
-#define BCHP_SWITCH_ACB_ACB_QUEUE_62_CONFIGURATION_total_xoff_threshold_DEFAULT 0x00000000
-
-/* SWITCH_ACB :: ACB_QUEUE_62_CONFIGURATION :: xon_en [11:11] */
-#define BCHP_SWITCH_ACB_ACB_QUEUE_62_CONFIGURATION_xon_en_MASK 0x00000800
-#define BCHP_SWITCH_ACB_ACB_QUEUE_62_CONFIGURATION_xon_en_SHIFT 11
-#define BCHP_SWITCH_ACB_ACB_QUEUE_62_CONFIGURATION_xon_en_DEFAULT 0x00000000
-
-/* SWITCH_ACB :: ACB_QUEUE_62_CONFIGURATION :: xoff_threshold [10:00] */
-#define BCHP_SWITCH_ACB_ACB_QUEUE_62_CONFIGURATION_xoff_threshold_MASK 0x000007ff
-#define BCHP_SWITCH_ACB_ACB_QUEUE_62_CONFIGURATION_xoff_threshold_SHIFT 0
-#define BCHP_SWITCH_ACB_ACB_QUEUE_62_CONFIGURATION_xoff_threshold_DEFAULT 0x00000000
-
-/***************************************************************************
- *ACB_QUEUE_63_CONFIGURATION - ACB Queue 63 Configuration Register
- ***************************************************************************/
-/* SWITCH_ACB :: ACB_QUEUE_63_CONFIGURATION :: pessimistic_mode_en [31:31] */
-#define BCHP_SWITCH_ACB_ACB_QUEUE_63_CONFIGURATION_pessimistic_mode_en_MASK 0x80000000
-#define BCHP_SWITCH_ACB_ACB_QUEUE_63_CONFIGURATION_pessimistic_mode_en_SHIFT 31
-#define BCHP_SWITCH_ACB_ACB_QUEUE_63_CONFIGURATION_pessimistic_mode_en_DEFAULT 0x00000000
-#define BCHP_SWITCH_ACB_ACB_QUEUE_63_CONFIGURATION_pessimistic_mode_en_GISB 1
-#define BCHP_SWITCH_ACB_ACB_QUEUE_63_CONFIGURATION_pessimistic_mode_en_PORT 0
-
-/* union - case input_is_gisb [30:25] */
-/* SWITCH_ACB :: ACB_QUEUE_63_CONFIGURATION :: input_is_gisb :: pktlen [30:25] */
-#define BCHP_SWITCH_ACB_ACB_QUEUE_63_CONFIGURATION_input_is_gisb_pktlen_MASK 0x7e000000
-#define BCHP_SWITCH_ACB_ACB_QUEUE_63_CONFIGURATION_input_is_gisb_pktlen_SHIFT 25
-#define BCHP_SWITCH_ACB_ACB_QUEUE_63_CONFIGURATION_input_is_gisb_pktlen_DEFAULT 0x00000000
-
-/* union - case input_is_acb_queue_63_configuration [30:25] */
-/* SWITCH_ACB :: ACB_QUEUE_63_CONFIGURATION :: input_is_acb_queue_63_configuration :: pktlen [30:25] */
-#define BCHP_SWITCH_ACB_ACB_QUEUE_63_CONFIGURATION_input_is_acb_queue_63_configuration_pktlen_MASK 0x7e000000
-#define BCHP_SWITCH_ACB_ACB_QUEUE_63_CONFIGURATION_input_is_acb_queue_63_configuration_pktlen_SHIFT 25
-#define BCHP_SWITCH_ACB_ACB_QUEUE_63_CONFIGURATION_input_is_acb_queue_63_configuration_pktlen_DEFAULT 0x00000000
-
-/* SWITCH_ACB :: ACB_QUEUE_63_CONFIGURATION :: total_xon_en [24:24] */
-#define BCHP_SWITCH_ACB_ACB_QUEUE_63_CONFIGURATION_total_xon_en_MASK 0x01000000
-#define BCHP_SWITCH_ACB_ACB_QUEUE_63_CONFIGURATION_total_xon_en_SHIFT 24
-#define BCHP_SWITCH_ACB_ACB_QUEUE_63_CONFIGURATION_total_xon_en_DEFAULT 0x00000000
-
-/* SWITCH_ACB :: ACB_QUEUE_63_CONFIGURATION :: total_xoff_en [23:23] */
-#define BCHP_SWITCH_ACB_ACB_QUEUE_63_CONFIGURATION_total_xoff_en_MASK 0x00800000
-#define BCHP_SWITCH_ACB_ACB_QUEUE_63_CONFIGURATION_total_xoff_en_SHIFT 23
-#define BCHP_SWITCH_ACB_ACB_QUEUE_63_CONFIGURATION_total_xoff_en_DEFAULT 0x00000000
-
-/* SWITCH_ACB :: ACB_QUEUE_63_CONFIGURATION :: total_xoff_threshold [22:12] */
-#define BCHP_SWITCH_ACB_ACB_QUEUE_63_CONFIGURATION_total_xoff_threshold_MASK 0x007ff000
-#define BCHP_SWITCH_ACB_ACB_QUEUE_63_CONFIGURATION_total_xoff_threshold_SHIFT 12
-#define BCHP_SWITCH_ACB_ACB_QUEUE_63_CONFIGURATION_total_xoff_threshold_DEFAULT 0x00000000
-
-/* SWITCH_ACB :: ACB_QUEUE_63_CONFIGURATION :: xon_en [11:11] */
-#define BCHP_SWITCH_ACB_ACB_QUEUE_63_CONFIGURATION_xon_en_MASK 0x00000800
-#define BCHP_SWITCH_ACB_ACB_QUEUE_63_CONFIGURATION_xon_en_SHIFT 11
-#define BCHP_SWITCH_ACB_ACB_QUEUE_63_CONFIGURATION_xon_en_DEFAULT 0x00000000
-
-/* SWITCH_ACB :: ACB_QUEUE_63_CONFIGURATION :: xoff_threshold [10:00] */
-#define BCHP_SWITCH_ACB_ACB_QUEUE_63_CONFIGURATION_xoff_threshold_MASK 0x000007ff
-#define BCHP_SWITCH_ACB_ACB_QUEUE_63_CONFIGURATION_xoff_threshold_SHIFT 0
-#define BCHP_SWITCH_ACB_ACB_QUEUE_63_CONFIGURATION_xoff_threshold_DEFAULT 0x00000000
-
-#endif /* #ifndef BCHP_SWITCH_ACB_H__ */
-
-/* End of File */
diff --git a/include/linux/brcmstb/7145a0/bchp_switch_core.h b/include/linux/brcmstb/7145a0/bchp_switch_core.h
deleted file mode 100644
index 6c0a2cf..0000000
--- a/include/linux/brcmstb/7145a0/bchp_switch_core.h
+++ /dev/null
@@ -1,31972 +0,0 @@
-/***************************************************************************
- * Copyright (c) 1999-2014, Broadcom Corporation
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
- *
- * Module Description:
- * DO NOT EDIT THIS FILE DIRECTLY
- *
- * This module was generated magically with RDB from a source description
- * file. You must edit the source file for changes to be made to this file.
- *
- *
- * Date: Generated on Wed Sep 3 13:17:39 2014
- * Full Compile MD5 Checksum a8ee62ccf9dde43435c825f266da463d
- * (minus title and desc)
- * MD5 Checksum e373b364a1742e13a0f9eb15fd8aa94f
- *
- * Compiled with: RDB Utility combo_header.pl
- * RDB Parser 3.0
- * unknown unknown
- * Perl Interpreter 5.008005
- * Operating System linux
- *
- * Revision History:
- *
- * $brcm_Log: $
- *
- ***************************************************************************/
-
-#ifndef BCHP_SWITCH_CORE_H__
-#define BCHP_SWITCH_CORE_H__
-
-/***************************************************************************
- *SWITCH_CORE
- ***************************************************************************/
-#define BCHP_SWITCH_CORE_G_PCTL_Port_0 0x04e00000 /* Port N 10/100/1000 Control Register */
-#define BCHP_SWITCH_CORE_G_PCTL_Port_1 0x04e00004 /* Port N 10/100/1000 Control Register */
-#define BCHP_SWITCH_CORE_G_PCTL_Port_2 0x04e00008 /* Port N 10/100/1000 Control Register */
-#define BCHP_SWITCH_CORE_G_PCTL_Port_3 0x04e0000c /* Port N 10/100/1000 Control Register */
-#define BCHP_SWITCH_CORE_G_PCTL_Port_4 0x04e00010 /* Port N 10/100/1000 Control Register */
-#define BCHP_SWITCH_CORE_G_PCTL_Port_5 0x04e00014 /* Port N 10/100/1000 Control Register */
-#define BCHP_SWITCH_CORE_P7_CTL 0x04e0001c /* Port 7 Control Register */
-#define BCHP_SWITCH_CORE_IMP_CTL 0x04e00020 /* IMP Port Control Register */
-#define BCHP_SWITCH_CORE_RX_GLOBAL_CTL 0x04e00028 /* RX Global Control register(Not2Release) */
-#define BCHP_SWITCH_CORE_SWMODE 0x04e0002c /* Switch Mode Register */
-#define BCHP_SWITCH_CORE_STS_OVERRIDE_IMP 0x04e00038 /* IMP Port States Override Register */
-#define BCHP_SWITCH_CORE_DEBUG_REG 0x04e00078 /* Debug Control Register(Not2Release) */
-#define BCHP_SWITCH_CORE_RM_PINS_DEBUG 0x04e0007c /* Removed Pins Debug Register(Not2Release) */
-#define BCHP_SWITCH_CORE_NEW_CTRL 0x04e00084 /* New Control Register */
-#define BCHP_SWITCH_CORE_SWITCH_CTRL 0x04e00088 /* Switch Control Register (Not2Release) */
-#define BCHP_SWITCH_CORE_PROTECTED_SEL 0x04e00090 /* Protected Port Select Register */
-#define BCHP_SWITCH_CORE_WAN_PORT_SEL 0x04e00098 /* WAN Port select Register */
-#define BCHP_SWITCH_CORE_PAUSE_CAP 0x04e000a0 /* PAUSE Capability Register */
-#define BCHP_SWITCH_CORE_RSV_MCAST_CTRL 0x04e000bc /* Reserved Multicast Register */
-#define BCHP_SWITCH_CORE_TXQ_FLUSH_MODE 0x04e000c4 /* TxQ Flush Mode Control Register(Not2Release) */
-#define BCHP_SWITCH_CORE_ULF_DROP_MAP 0x04e000c8 /* Unicast Lookup Failed Forward Map Register */
-#define BCHP_SWITCH_CORE_MLF_DROP_MAP 0x04e000d0 /* Multicast Lookup Failed Forward Map Register */
-#define BCHP_SWITCH_CORE_MLF_IPMC_FWD_MAP 0x04e000d8 /* IPMC Forward Map Register */
-#define BCHP_SWITCH_CORE_RX_PAUSE_PASS 0x04e000e0 /* Pause pass Through for RX Register */
-#define BCHP_SWITCH_CORE_TX_PAUSE_PASS 0x04e000e8 /* Pause pass Through for TX Register */
-#define BCHP_SWITCH_CORE_DIS_LEARN 0x04e000f0 /* Disable Learning Register */
-#define BCHP_SWITCH_CORE_SFT_LRN_CTL 0x04e000f8 /* Software Learning Control */
-#define BCHP_SWITCH_CORE_LOW_POWER_EXP1 0x04e00100 /* Low Power Expansion I Register */
-#define BCHP_SWITCH_CORE_CTLREG_REG_SPARE 0x04e00150 /* Spare Register (Not2Release) */
-#define BCHP_SWITCH_CORE_STS_OVERRIDE_GMIIP_Port_0 0x04e00160 /* Port N GMII Port States Override Register */
-#define BCHP_SWITCH_CORE_STS_OVERRIDE_GMIIP_Port_1 0x04e00164 /* Port N GMII Port States Override Register */
-#define BCHP_SWITCH_CORE_STS_OVERRIDE_GMIIP_Port_2 0x04e00168 /* Port N GMII Port States Override Register */
-#define BCHP_SWITCH_CORE_STS_OVERRIDE_GMIIP_Port_3 0x04e0016c /* Port N GMII Port States Override Register */
-#define BCHP_SWITCH_CORE_STS_OVERRIDE_GMIIP_Port_4 0x04e00170 /* Port N GMII Port States Override Register */
-#define BCHP_SWITCH_CORE_STS_OVERRIDE_P5 0x04e00174 /* Port 5 GMII Port States Override Register */
-#define BCHP_SWITCH_CORE_STS_OVERRIDE_P7 0x04e0017c /* Port 7 GMII Port States Override Register */
-#define BCHP_SWITCH_CORE_WATCH_DOG_CTRL 0x04e001e4 /* Watch Dog Control Register */
-#define BCHP_SWITCH_CORE_WATCH_DOG_RPT1 0x04e001e8 /* Watch Dog Report 1 Register(Not2Release) */
-#define BCHP_SWITCH_CORE_WATCH_DOG_RPT2 0x04e001f0 /* Watch Dog Report 2 Register(Not2Release) */
-#define BCHP_SWITCH_CORE_WATCH_DOG_RPT3 0x04e001f8 /* Watch Dog Report 3 Register(Not2Release) */
-#define BCHP_SWITCH_CORE_PAUSE_FRM_CTRL 0x04e00200 /* Pause Frame Detection Control Register */
-#define BCHP_SWITCH_CORE_PAUSE_ST_ADDR 0x04e00204 /* PAUSE Frame DA Address */
-#define BCHP_SWITCH_CORE_FAST_AGE_CTRL 0x04e00220 /* Fast Ageing Control Register */
-#define BCHP_SWITCH_CORE_FAST_AGE_PORT 0x04e00224 /* Fast Ageing Port Control Register */
-#define BCHP_SWITCH_CORE_FAST_AGE_VID 0x04e00228 /* Fast Ageing VID Control Register */
-#define BCHP_SWITCH_CORE_LOW_POWER_CTRL 0x04e00378 /* LOW Power Control Register */
-#define BCHP_SWITCH_CORE_TCAM_CTRL 0x04e003a0 /* TCAM Control Register */
-#define BCHP_SWITCH_CORE_TCAM_CHKSUM_STS 0x04e003a8 /* TCAM Checksum Status Register */
-#define BCHP_SWITCH_CORE_LNKSTS 0x04e00400 /* Link Status Summary Register */
-#define BCHP_SWITCH_CORE_LNKSTSCHG 0x04e00408 /* Link Status Change Register */
-#define BCHP_SWITCH_CORE_SPDSTS 0x04e00410 /* Port Speed Summary Register */
-#define BCHP_SWITCH_CORE_DUPSTS 0x04e00420 /* Duplex status Summary Register */
-#define BCHP_SWITCH_CORE_PAUSESTS 0x04e00428 /* Pause Status Summary Register */
-#define BCHP_SWITCH_CORE_SRCADRCHG 0x04e00438 /* Source Address Change Register */
-#define BCHP_SWITCH_CORE_LSA_PORT_Port_0 0x04e00440 /* Port N Last Source Address */
-#define BCHP_SWITCH_CORE_LSA_PORT_Port_1 0x04e00458 /* Port N Last Source Address */
-#define BCHP_SWITCH_CORE_LSA_PORT_Port_2 0x04e00470 /* Port N Last Source Address */
-#define BCHP_SWITCH_CORE_LSA_PORT_Port_3 0x04e00488 /* Port N Last Source Address */
-#define BCHP_SWITCH_CORE_LSA_PORT_Port_4 0x04e004a0 /* Port N Last Source Address */
-#define BCHP_SWITCH_CORE_LSA_PORT_Port_5 0x04e004b8 /* Port N Last Source Address */
-#define BCHP_SWITCH_CORE_LSA_PORT7 0x04e004e8 /* Port 7 Last Source Address */
-#define BCHP_SWITCH_CORE_LSA_MII_PORT 0x04e00500 /* Port 8 Last Source Address */
-#define BCHP_SWITCH_CORE_BIST_STS0 0x04e00518 /* BIST Status Register 0 */
-#define BCHP_SWITCH_CORE_BIST_STS1 0x04e00530 /* BIST Status Register 1 */
-#define BCHP_SWITCH_CORE_PBPTRFIFO_0 0x04e00540 /* PBPTRFIFO Status Register 0(Not2Release) */
-#define BCHP_SWITCH_CORE_PBPTRFIFO_1 0x04e00558 /* PBPTRFIFO Status Register 1(Not2Release) */
-#define BCHP_SWITCH_CORE_STRAP_PIN_STATUS 0x04e005c0 /* Strap Pin Status Register */
-#define BCHP_SWITCH_CORE_DIRECT_INPUT_CTRL_VALUE 0x04e00600 /* Direct Input Control Value Register */
-#define BCHP_SWITCH_CORE_RESET_STATUS 0x04e00640 /* Reset Status Register */
-#define BCHP_SWITCH_CORE_ENG_DET_STS 0x04e00648 /* PHY Energy Detect Status Register */
-#define BCHP_SWITCH_CORE_ENG_DET_STS_CHG 0x04e0064c /* PHY Energy Detect Status Change Register */
-#define BCHP_SWITCH_CORE_STREG_REG_SPARE0 0x04e00680 /* Spare 0 Register (Not2Release) */
-#define BCHP_SWITCH_CORE_STREG_REG_SPARE1 0x04e00690 /* Spare 1 Register (Not2Release) */
-#define BCHP_SWITCH_CORE_GMNGCFG 0x04e00800 /* Global Management Configuration Register */
-#define BCHP_SWITCH_CORE_IMP0_PRT_ID 0x04e00804 /* IMP/IMP0 Port ID Register */
-#define BCHP_SWITCH_CORE_IMP1_PRT_ID 0x04e00808 /* IMP1 Port ID Register */
-#define BCHP_SWITCH_CORE_BRCM_HDR_CTRL 0x04e0080c /* BRCM Header Control Register */
-#define BCHP_SWITCH_CORE_SPTAGT 0x04e00818 /* Aging Time Control Register */
-#define BCHP_SWITCH_CORE_BRCM_HDR_CTRL2 0x04e00828 /* BRCM Header Control 2 Register */
-#define BCHP_SWITCH_CORE_IPG_SHRNK_CTRL 0x04e00830 /* IPG Shrink Control Register */
-#define BCHP_SWITCH_CORE_MIRCAPCTL 0x04e00840 /* Mirror Capture Control Register */
-#define BCHP_SWITCH_CORE_IGMIRCTL 0x04e00848 /* Ingress Mirror Control Register */
-#define BCHP_SWITCH_CORE_IGMIRDIV 0x04e00850 /* Ingress Mirror Divider Register */
-#define BCHP_SWITCH_CORE_IGMIRMAC 0x04e00858 /* Ingress Mirror Mac Address Register */
-#define BCHP_SWITCH_CORE_EGMIRCTL 0x04e00870 /* Egress Mirror Control Register */
-#define BCHP_SWITCH_CORE_EGMIRDIV 0x04e00878 /* Egress Mirror Divider Register */
-#define BCHP_SWITCH_CORE_EGMIRMAC 0x04e00880 /* Egress Mirror MAC Address Register */
-#define BCHP_SWITCH_CORE_MODEL_ID 0x04e008c0 /* Model ID Register (Not2Release) */
-#define BCHP_SWITCH_CORE_CHIP_REVID 0x04e00900 /* Chip Version ID Register */
-#define BCHP_SWITCH_CORE_HL_PRTC_CTRL 0x04e00940 /* High Level Protocol Control Register */
-#define BCHP_SWITCH_CORE_RST_MIB_CNT_EN 0x04e00950 /* Reset MIB Counter Enable Register */
-#define BCHP_SWITCH_CORE_IPG_SHRINK_2G_WA 0x04e00960 /* IPG Shrink 2G Workaround Register (Not2Release) */
-#define BCHP_SWITCH_CORE_MNGMODE_REG_SPARE0 0x04e009c0 /* Spare 0 Register (Not2Release) */
-#define BCHP_SWITCH_CORE_MNGMODE_REG_SPARE1 0x04e009d0 /* Spare 1 Register (Not2Release) */
-#define BCHP_SWITCH_CORE_INT_STS 0x04e00c00 /* External Host Raw Interrupt Status Register */
-#define BCHP_SWITCH_CORE_INT_EN 0x04e00c20 /* External Host Interrupt Enable Register */
-#define BCHP_SWITCH_CORE_IMP_SLEEP_TIMER 0x04e00c40 /* IMP Port(port 8) Sleep Timer Register */
-#define BCHP_SWITCH_CORE_PORT7_SLEEP_TIMER 0x04e00c48 /* Port 7 Sleep Timer Register */
-#define BCHP_SWITCH_CORE_WAN_SLEEP_TIMER 0x04e00c50 /* WAN Port Sleep Timer Register */
-#define BCHP_SWITCH_CORE_PORT_SLEEP_STS 0x04e00c60 /* Port Sleep Status Register */
-#define BCHP_SWITCH_CORE_INT_TRIGGER 0x04e00c80 /* Interrupt Trigger Register */
-#define BCHP_SWITCH_CORE_LINK_STS_INT_EN 0x04e00c90 /* Link Status Interrupt Enable Register */
-#define BCHP_SWITCH_CORE_ENG_DET_INT_EN 0x04e00ca0 /* Energy Detection Interrupt Enable Register */
-#define BCHP_SWITCH_CORE_LPI_STS_CHG_INT_EN 0x04e00ca8 /* LPI Status Change Interrupt Enable Register */
-#define BCHP_SWITCH_CORE_CPU_RESOURCE_ARBITER 0x04e00d00 /* CPU Resource Arbitor Register */
-#define BCHP_SWITCH_CORE_CPU_DATA_SHARE 0x04e00d40 /* CPU Data Share Register */
-#define BCHP_SWITCH_CORE_CPU_DATA_SHARE_1 0x04e00d60 /* CPU Data Share 1 Register */
-#define BCHP_SWITCH_CORE_MEM_ECC_ERR_INT_STS 0x04e00d80 /* Memory ECC Double-Error-Detection Interrupt Status (Not2Release) */
-#define BCHP_SWITCH_CORE_MEM_ECC_ERR_INT_EN 0x04e00d88 /* Memory ECC Double-Error-Detection Interrupt Enable (Not2Release) */
-#define BCHP_SWITCH_CORE_PORT_EVT_ECC_ERR_STS 0x04e00d90 /* Per Port EVT Table ECC Double-Error-Detection Error Status (Not2Release) */
-#define BCHP_SWITCH_CORE_PORT_MIB_ECC_ERR_STS 0x04e00d98 /* Per Port MIB Counter ECC Double-Error-Detection Error Status (Not2Release) */
-#define BCHP_SWITCH_CORE_PORT_TXQ_ECC_ERR_STS 0x04e00da0 /* Per Port TXQ ECC Double-Error-Detection Error Status (Not2Release) */
-#define BCHP_SWITCH_CORE_PROBE_BUS_CTL 0x04e00dc0 /* Probe Bus Control Registers(Not2Release) */
-#define BCHP_SWITCH_CORE_MDC_EXTEND_CTRL 0x04e00dd0 /* MDC Extend Clock Control Register (Not2Release) */
-#define BCHP_SWITCH_CORE_PPPOE_SESSION_PARSE_EN 0x04e00e00 /* PPPoE Session Packet Parsing Enable Register */
-#define BCHP_SWITCH_CORE_CTLREG_1_REG_SPARE0 0x04e00e40 /* Spare 0 Register (Not2Release) */
-#define BCHP_SWITCH_CORE_CTLREG_1_REG_SPARE1 0x04e00e50 /* Spare 1 Register (Not2Release) */
-#define BCHP_SWITCH_CORE_GARLCFG 0x04e01000 /* Global ARL Configuration Register */
-#define BCHP_SWITCH_CORE_BPDU_MCADDR 0x04e01010 /* BPDU Multicast Address Register */
-#define BCHP_SWITCH_CORE_MULTI_PORT_CTL 0x04e01038 /* Multiport Control Register */
-#define BCHP_SWITCH_CORE_MULTIPORT_ADDR0 0x04e01040 /* Multiport Address 0 Register (Default for TS) */
-#define BCHP_SWITCH_CORE_MPORTVEC0 0x04e01060 /* Multiport Vector 0 Register */
-#define BCHP_SWITCH_CORE_MULTIPORT_ADDR1 0x04e01080 /* Multiport Address 1 Register */
-#define BCHP_SWITCH_CORE_MPORTVEC1 0x04e010a0 /* Multiport Vector 1 Register */
-#define BCHP_SWITCH_CORE_MULTIPORT_ADDR2 0x04e010c0 /* Multiport Address 2 Register */
-#define BCHP_SWITCH_CORE_MPORTVEC2 0x04e010e0 /* Multiport Vector 2 Register */
-#define BCHP_SWITCH_CORE_MULTIPORT_ADDR3 0x04e01100 /* Multiport Address 3 Register */
-#define BCHP_SWITCH_CORE_MPORTVEC3 0x04e01120 /* Multiport Vector 3 Register */
-#define BCHP_SWITCH_CORE_MULTIPORT_ADDR4 0x04e01140 /* Multiport Address 4 Register */
-#define BCHP_SWITCH_CORE_MPORTVEC4 0x04e01160 /* Multiport Vector 4 Register */
-#define BCHP_SWITCH_CORE_MULTIPORT_ADDR5 0x04e01180 /* Multiport Address 5 Register */
-#define BCHP_SWITCH_CORE_MPORTVEC5 0x04e011a0 /* Multiport Vector 5 Register */
-#define BCHP_SWITCH_CORE_ARL_BIN_FULL_CNTR 0x04e011c0 /* ARL Bin Full Counter Register */
-#define BCHP_SWITCH_CORE_ARL_BIN_FULL_FWD 0x04e011d0 /* ARL Biin Full Forward Enable Register */
-#define BCHP_SWITCH_CORE_ARLCTL_REG_SPARE0 0x04e01200 /* Spare 0 Register (Not2Release) */
-#define BCHP_SWITCH_CORE_ARLCTL_REG_SPARE1 0x04e01210 /* Spare 1 Register (Not2Release) */
-#define BCHP_SWITCH_CORE_ARLA_RWCTL 0x04e01400 /* ARL Read/Write Control Register */
-#define BCHP_SWITCH_CORE_ARLA_MAC 0x04e01408 /* MAC Address Index Register */
-#define BCHP_SWITCH_CORE_ARLA_VID 0x04e01420 /* VID Index Register */
-#define BCHP_SWITCH_CORE_ARLA_MACVID_ENTRY0 0x04e01440 /* ARL MAC/VID Entry 0 Register */
-#define BCHP_SWITCH_CORE_ARLA_FWD_ENTRY0 0x04e01460 /* ARL FWD Entry 0 Register */
-#define BCHP_SWITCH_CORE_ARLA_MACVID_ENTRY1 0x04e01480 /* ARL MAC/VID Entry 1 Register */
-#define BCHP_SWITCH_CORE_ARLA_FWD_ENTRY1 0x04e014a0 /* ARL FWD Entry 1 Register */
-#define BCHP_SWITCH_CORE_ARLA_MACVID_ENTRY2 0x04e014c0 /* ARL MAC/VID Entry 2 Register */
-#define BCHP_SWITCH_CORE_ARLA_FWD_ENTRY2 0x04e014e0 /* ARL FWD Entry 2 Register */
-#define BCHP_SWITCH_CORE_ARLA_MACVID_ENTRY3 0x04e01500 /* ARL MAC/VID Entry 3 Register */
-#define BCHP_SWITCH_CORE_ARLA_FWD_ENTRY3 0x04e01520 /* ARL FWD Entry 3 Register */
-#define BCHP_SWITCH_CORE_ARLA_SRCH_CTL 0x04e01540 /* ARL Search Control Register */
-#define BCHP_SWITCH_CORE_ARLA_SRCH_ADR 0x04e01544 /* ARL Search Address Register */
-#define BCHP_SWITCH_CORE_ARLA_SRCH_RSLT_0_MACVID 0x04e01580 /* ARL Search MAC/VID Result 0 Register */
-#define BCHP_SWITCH_CORE_ARLA_SRCH_RSLT_0 0x04e015a0 /* ARL Search Result 0 Register */
-#define BCHP_SWITCH_CORE_ARLA_SRCH_RSLT_1_MACVID 0x04e015c0 /* ARL Search MAC/VID Result 1 Register */
-#define BCHP_SWITCH_CORE_ARLA_SRCH_RSLT_1 0x04e015e0 /* ARL Search Result 1 Register */
-#define BCHP_SWITCH_CORE_ARLA_VTBL_RWCTRL 0x04e01600 /* VTBL Read/Write/Clear Control Register */
-#define BCHP_SWITCH_CORE_ARLA_VTBL_ADDR 0x04e01604 /* VTBL Address Index Register */
-#define BCHP_SWITCH_CORE_ARLA_VTBL_ENTRY 0x04e0160c /* VTBL Entry Register */
-#define BCHP_SWITCH_CORE_ARLACCS_REG_SPARE0 0x04e01640 /* Spare 0 Register (Not2Release) */
-#define BCHP_SWITCH_CORE_ARLACCS_REG_SPARE1 0x04e01650 /* Spare 1 Register (Not2Release) */
-#define BCHP_SWITCH_CORE_MEM_CTRL 0x04e02000 /* Memory Debug Control RegisterNot2Release */
-#define BCHP_SWITCH_CORE_MEM_ADDR 0x04e02004 /* Memory Debug Address RegisterNot2Release */
-#define BCHP_SWITCH_CORE_MEM_DEBUG_DATA_0_0 0x04e02020 /* Memory Debug Data 0_0 RegisterNot2Release */
-#define BCHP_SWITCH_CORE_MEM_DEBUG_DATA_0_1 0x04e02040 /* Memory Debug Data 0_1 RegisterNot2Release */
-#define BCHP_SWITCH_CORE_MEM_DEBUG_DATA_1_0 0x04e02048 /* Memory Debug Data 1_0 RegisterNot2Release */
-#define BCHP_SWITCH_CORE_MEM_DEBUG_DATA_1_1 0x04e02068 /* Memory Debug Data 1_1 RegisterNot2Release */
-#define BCHP_SWITCH_CORE_MEM_FRM_ADDR 0x04e02080 /* Frame Memory Address RegisterNot2Release */
-#define BCHP_SWITCH_CORE_MEM_FRM_DATA0 0x04e020c0 /* Frame Memory Data 1st RegisterNot2Release */
-#define BCHP_SWITCH_CORE_MEM_FRM_DATA1 0x04e020e0 /* Frame Memory Data 2st RegisterNot2Release */
-#define BCHP_SWITCH_CORE_MEM_FRM_DATA2 0x04e02100 /* Frame Memory Data 3st RegisterNot2Release */
-#define BCHP_SWITCH_CORE_MEM_FRM_DATA3 0x04e02120 /* Frame Memory Data 4th RegisterNot2Release */
-#define BCHP_SWITCH_CORE_MEM_BTM_DATA0 0x04e02140 /* Buffer Tag Memory Register 0Not2Release */
-#define BCHP_SWITCH_CORE_MEM_BTM_DATA1 0x04e02160 /* Buffer Tag Memory Register 1Not2Release */
-#define BCHP_SWITCH_CORE_MEM_BFC_ADDR 0x04e02180 /* Buffer Control Memory Address RegisterNot2Release */
-#define BCHP_SWITCH_CORE_MEM_BFC_DATA 0x04e02188 /* Buffer Control Memory Data RegisterNot2Release */
-#define BCHP_SWITCH_CORE_PRS_FIFO_DEBUG_CTRL 0x04e021c0 /* PRS_FIFO Debug Control Register(Not2Release)Not2Release */
-#define BCHP_SWITCH_CORE_PRS_FIFO_DEBUG_DATA 0x04e021c4 /* PRS_FIFO Debug Data Register(Not2Release)Not2Release */
-#define BCHP_SWITCH_CORE_MEM_REG_SPARE0 0x04e022a0 /* Spare 0 Register (Not2Release)Not2Release */
-#define BCHP_SWITCH_CORE_MEM_REG_SPARE1 0x04e022b0 /* Spare 1 Register (Not2Release)Not2Release */
-#define BCHP_SWITCH_CORE_MEM_MISC_CTRL 0x04e022c0 /* Memory Misc Control RegisterNot2Release */
-#define BCHP_SWITCH_CORE_MEM_TEST_CTRL0 0x04e022d0 /* Memory Test Control 0 RegisterNot2Release */
-#define BCHP_SWITCH_CORE_MEM_TEST_CTRL1 0x04e022e0 /* Memory Test Control 1 RegisterNot2Release */
-#define BCHP_SWITCH_CORE_MEM_TEST_CTRL2 0x04e022f0 /* Memory Test Control 2 RegisterNot2Release */
-#define BCHP_SWITCH_CORE_MEM_TEST_CTRL3 0x04e02300 /* Memory Test Control 3 RegisterNot2Release */
-#define BCHP_SWITCH_CORE_MEM_TEST_CTRL4 0x04e02310 /* Memory Test Control 4 RegisterNot2Release */
-#define BCHP_SWITCH_CORE_MEM_TEST_CTRL5 0x04e02320 /* Memory Test Control 5 RegisterNot2Release */
-#define BCHP_SWITCH_CORE_MEM_PSM_VDD_CTRL 0x04e02380 /* Memory PSM_VDD Pin Control registerNot2Release */
-#define BCHP_SWITCH_CORE_PORT0_DEBUG 0x04e02400 /* PORT0 DEBUGNot2Release */
-#define BCHP_SWITCH_CORE_PORT1_DEBUG 0x04e02440 /* PORT1 DEBUGNot2Release */
-#define BCHP_SWITCH_CORE_PORT2_DEBUG 0x04e02480 /* PORT2 DEBUGNot2Release */
-#define BCHP_SWITCH_CORE_PORT3_DEBUG 0x04e024c0 /* PORT3 DEBUGNot2Release */
-#define BCHP_SWITCH_CORE_PORT4_DEBUG 0x04e02500 /* PORT4 DEBUGNot2Release */
-#define BCHP_SWITCH_CORE_PORT5_DEBUG 0x04e02540 /* PORT5 DEBUGNot2Release */
-#define BCHP_SWITCH_CORE_PORT6_DEBUG 0x04e02580 /* PORT6 DEBUGNot2Release */
-#define BCHP_SWITCH_CORE_PORT7_DEBUG 0x04e025c0 /* PORT7 DEBUGNot2Release */
-#define BCHP_SWITCH_CORE_PORT8_DEBUG 0x04e02600 /* PORT8 DEBUGNot2Release */
-#define BCHP_SWITCH_CORE_FC_DIAG_CTRL 0x04e02800 /* Flowcon Diagnosis Control RegisterNot2Release */
-#define BCHP_SWITCH_CORE_FC_CTRL_MODE 0x04e02808 /* Flow Control Mode Selection RegisterNot2Release */
-#define BCHP_SWITCH_CORE_FC_CTRL_PORT 0x04e0280c /* Flow Control Port Selection RegisterNot2Release */
-#define BCHP_SWITCH_CORE_FC_OOB_PAUSE_EN 0x04e02810 /* OOB Pause Signal Enable Register (Release2Customer)Not2Release */
-#define BCHP_SWITCH_CORE_PAUSE_TIME_MAX 0x04e02840 /* MAX Quantum Pause Time RegisterNot2Release */
-#define BCHP_SWITCH_CORE_PAUSE_TIME_MIN 0x04e02848 /* MIN Quantum Pause Time RegisterNot2Release */
-#define BCHP_SWITCH_CORE_PAUSE_TIME_RESET_THD 0x04e02850 /* Quantum Pause Threshold RegisterNot2Release */
-#define BCHP_SWITCH_CORE_PAUSE_TIME_UPDATE_PERIOD 0x04e02858 /* Quantum Pause Update Period RegisterNot2Release */
-#define BCHP_SWITCH_CORE_PAUSE_TIME_DEFAULT 0x04e02860 /* Default Quantum Pause Time RegisterNot2Release */
-#define BCHP_SWITCH_CORE_FC_MCAST_DROP_CTRL 0x04e02868 /* Multicast Drop Control RegisterNot2Release */
-#define BCHP_SWITCH_CORE_FC_PAUSE_DROP_CTRL 0x04e02870 /* Pause/Drop Control RegisterNot2Release */
-#define BCHP_SWITCH_CORE_FC_TXQ_THD_PAUSE_OFF 0x04e02878 /* TXQ Pause Off Threshold RegisterNot2Release */
-#define BCHP_SWITCH_CORE_FC_RX_RUNOFF 0x04e02880 /* RX-Based Run-Off RegisterNot2Release */
-#define BCHP_SWITCH_CORE_FC_RX_RSV_THD 0x04e02888 /* RX-Based Reserved RegisterNot2Release */
-#define BCHP_SWITCH_CORE_FC_RX_HYST_THD 0x04e02890 /* RX-Based Hysteresis RegisterNot2Release */
-#define BCHP_SWITCH_CORE_FC_RX_MAX_PTR 0x04e02898 /* RX-Based Maximum Buffer Remap RegisterNot2Release */
-#define BCHP_SWITCH_CORE_FC_SPARE_ZERO_REG 0x04e028a0 /* Flow Control Spare Zero RegisterNot2Release */
-#define BCHP_SWITCH_CORE_FC_SPARE_ONE_REG 0x04e028a8 /* Flow Control Spare One RegisterNot2Release */
-#define BCHP_SWITCH_CORE_FC_MON_TXQ_Port_0 0x04e028c0 /* Monitored TXQ N RegisterNot2Release */
-#define BCHP_SWITCH_CORE_FC_MON_TXQ_Port_1 0x04e028c8 /* Monitored TXQ N RegisterNot2Release */
-#define BCHP_SWITCH_CORE_FC_MON_TXQ_Port_2 0x04e028d0 /* Monitored TXQ N RegisterNot2Release */
-#define BCHP_SWITCH_CORE_FC_MON_TXQ_Port_3 0x04e028d8 /* Monitored TXQ N RegisterNot2Release */
-#define BCHP_SWITCH_CORE_FC_MON_TXQ_Port_4 0x04e028e0 /* Monitored TXQ N RegisterNot2Release */
-#define BCHP_SWITCH_CORE_FC_MON_TXQ_Port_5 0x04e028e8 /* Monitored TXQ N RegisterNot2Release */
-#define BCHP_SWITCH_CORE_FC_MON_TXQ_Port_6 0x04e028f0 /* Monitored TXQ N RegisterNot2Release */
-#define BCHP_SWITCH_CORE_FC_MON_TXQ_Port_7 0x04e028f8 /* Monitored TXQ N RegisterNot2Release */
-#define BCHP_SWITCH_CORE_FC_PEAK_TXQ_Port_0 0x04e02900 /* Peak TXQ N Counter RegisterNot2Release */
-#define BCHP_SWITCH_CORE_FC_PEAK_TXQ_Port_1 0x04e02908 /* Peak TXQ N Counter RegisterNot2Release */
-#define BCHP_SWITCH_CORE_FC_PEAK_TXQ_Port_2 0x04e02910 /* Peak TXQ N Counter RegisterNot2Release */
-#define BCHP_SWITCH_CORE_FC_PEAK_TXQ_Port_3 0x04e02918 /* Peak TXQ N Counter RegisterNot2Release */
-#define BCHP_SWITCH_CORE_FC_PEAK_TXQ_Port_4 0x04e02920 /* Peak TXQ N Counter RegisterNot2Release */
-#define BCHP_SWITCH_CORE_FC_PEAK_TXQ_Port_5 0x04e02928 /* Peak TXQ N Counter RegisterNot2Release */
-#define BCHP_SWITCH_CORE_FC_PEAK_TXQ_Port_6 0x04e02930 /* Peak TXQ N Counter RegisterNot2Release */
-#define BCHP_SWITCH_CORE_FC_PEAK_TXQ_Port_7 0x04e02938 /* Peak TXQ N Counter RegisterNot2Release */
-#define BCHP_SWITCH_CORE_FC_PEAK_TOTAL_USED 0x04e02940 /* Peak Total Used Count RegisterNot2Release */
-#define BCHP_SWITCH_CORE_FC_TOTAL_USED 0x04e02948 /* Total Used Count RegisterNot2Release */
-#define BCHP_SWITCH_CORE_FC_PEAK_RX_CNT 0x04e02950 /* Peak RX Counter RegisterNot2Release */
-#define BCHP_SWITCH_CORE_FC_LINK_PORTMAP 0x04e02958 /* PHY Link Information RegisterNot2Release */
-#define BCHP_SWITCH_CORE_FC_GIGA_PORTMAP 0x04e02960 /* Giga Speed Information RegisterNot2Release */
-#define BCHP_SWITCH_CORE_FC_CONG_PORTMAP_PN_Port_0 0x04e02980 /* Port N Congested PortMap RegisterNot2Release */
-#define BCHP_SWITCH_CORE_FC_CONG_PORTMAP_PN_Port_1 0x04e02988 /* Port N Congested PortMap RegisterNot2Release */
-#define BCHP_SWITCH_CORE_FC_CONG_PORTMAP_PN_Port_2 0x04e02990 /* Port N Congested PortMap RegisterNot2Release */
-#define BCHP_SWITCH_CORE_FC_CONG_PORTMAP_PN_Port_3 0x04e02998 /* Port N Congested PortMap RegisterNot2Release */
-#define BCHP_SWITCH_CORE_FC_CONG_PORTMAP_PN_Port_4 0x04e029a0 /* Port N Congested PortMap RegisterNot2Release */
-#define BCHP_SWITCH_CORE_FC_CONG_PORTMAP_PN_Port_5 0x04e029a8 /* Port N Congested PortMap RegisterNot2Release */
-#define BCHP_SWITCH_CORE_FC_CONG_PORTMAP_P7 0x04e029b8 /* Port 7 Congested PortMap RegisterNot2Release */
-#define BCHP_SWITCH_CORE_FC_CONG_PORTMAP_P8 0x04e029c0 /* Port 8 Congested PortMap RegisterNot2Release */
-#define BCHP_SWITCH_CORE_FC_PAUSE_HIS 0x04e029e0 /* Pause History RegisterNot2Release */
-#define BCHP_SWITCH_CORE_FC_TX_QUANTUM_PAUSE_HIS 0x04e029e8 /* TX Quantum Pause History RegisterNot2Release */
-#define BCHP_SWITCH_CORE_FC_RX_PAUSE_HIS 0x04e029f0 /* RX Based Pause History RegisterNot2Release */
-#define BCHP_SWITCH_CORE_FC_RXBUF_ERR_HIS 0x04e029f8 /* RX Buffer Error History RegisterNot2Release */
-#define BCHP_SWITCH_CORE_FC_TXQ_CONG_PORTMAP_PN_Port_0 0x04e02a00 /* Port N TXQ Congested PortMap RegisterNot2Release */
-#define BCHP_SWITCH_CORE_FC_TXQ_CONG_PORTMAP_PN_Port_1 0x04e02a08 /* Port N TXQ Congested PortMap RegisterNot2Release */
-#define BCHP_SWITCH_CORE_FC_TXQ_CONG_PORTMAP_PN_Port_2 0x04e02a10 /* Port N TXQ Congested PortMap RegisterNot2Release */
-#define BCHP_SWITCH_CORE_FC_TXQ_CONG_PORTMAP_PN_Port_3 0x04e02a18 /* Port N TXQ Congested PortMap RegisterNot2Release */
-#define BCHP_SWITCH_CORE_FC_TXQ_CONG_PORTMAP_PN_Port_4 0x04e02a20 /* Port N TXQ Congested PortMap RegisterNot2Release */
-#define BCHP_SWITCH_CORE_FC_TXQ_CONG_PORTMAP_PN_Port_5 0x04e02a28 /* Port N TXQ Congested PortMap RegisterNot2Release */
-#define BCHP_SWITCH_CORE_FC_TXQ_CONG_PORTMAP_P7 0x04e02a38 /* Port 7 TXQ Congested PortMap RegisterNot2Release */
-#define BCHP_SWITCH_CORE_FC_TXQ_CONG_PORTMAP_P8 0x04e02a40 /* Port 8 TXQ Congested PortMap RegisterNot2Release */
-#define BCHP_SWITCH_CORE_FC_TOTAL_CONG_PORTMAP_PN_Port_0 0x04e02a68 /* Port N Total Congested PortMap RegisterNot2Release */
-#define BCHP_SWITCH_CORE_FC_TOTAL_CONG_PORTMAP_PN_Port_1 0x04e02a70 /* Port N Total Congested PortMap RegisterNot2Release */
-#define BCHP_SWITCH_CORE_FC_TOTAL_CONG_PORTMAP_PN_Port_2 0x04e02a78 /* Port N Total Congested PortMap RegisterNot2Release */
-#define BCHP_SWITCH_CORE_FC_TOTAL_CONG_PORTMAP_PN_Port_3 0x04e02a80 /* Port N Total Congested PortMap RegisterNot2Release */
-#define BCHP_SWITCH_CORE_FC_TOTAL_CONG_PORTMAP_PN_Port_4 0x04e02a88 /* Port N Total Congested PortMap RegisterNot2Release */
-#define BCHP_SWITCH_CORE_FC_TOTAL_CONG_PORTMAP_PN_Port_5 0x04e02a90 /* Port N Total Congested PortMap RegisterNot2Release */
-#define BCHP_SWITCH_CORE_FC_TOTAL_CONG_PORTMAP_P7 0x04e02aa0 /* Port 7 Total Congested PortMap RegisterNot2Release */
-#define BCHP_SWITCH_CORE_FC_TOTAL_CONG_PORTMAP_P8 0x04e02aa8 /* Port 8 Total Congested PortMap RegisterNot2Release */
-#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_RSV_QN_Port_0 0x04e02c00 /* LAN Port Queue N Reserved Threshold RegisterNot2Release */
-#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_RSV_QN_Port_1 0x04e02c08 /* LAN Port Queue N Reserved Threshold RegisterNot2Release */
-#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_RSV_QN_Port_2 0x04e02c10 /* LAN Port Queue N Reserved Threshold RegisterNot2Release */
-#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_RSV_QN_Port_3 0x04e02c18 /* LAN Port Queue N Reserved Threshold RegisterNot2Release */
-#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_RSV_QN_Port_4 0x04e02c20 /* LAN Port Queue N Reserved Threshold RegisterNot2Release */
-#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_RSV_QN_Port_5 0x04e02c28 /* LAN Port Queue N Reserved Threshold RegisterNot2Release */
-#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_RSV_QN_Port_6 0x04e02c30 /* LAN Port Queue N Reserved Threshold RegisterNot2Release */
-#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_RSV_QN_Port_7 0x04e02c38 /* LAN Port Queue N Reserved Threshold RegisterNot2Release */
-#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_HYST_QN_Port_0 0x04e02c40 /* LAN Port Queue N Hysteresis Threshold RegisterNot2Release */
-#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_HYST_QN_Port_1 0x04e02c48 /* LAN Port Queue N Hysteresis Threshold RegisterNot2Release */
-#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_HYST_QN_Port_2 0x04e02c50 /* LAN Port Queue N Hysteresis Threshold RegisterNot2Release */
-#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_HYST_QN_Port_3 0x04e02c58 /* LAN Port Queue N Hysteresis Threshold RegisterNot2Release */
-#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_HYST_QN_Port_4 0x04e02c60 /* LAN Port Queue N Hysteresis Threshold RegisterNot2Release */
-#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_HYST_QN_Port_5 0x04e02c68 /* LAN Port Queue N Hysteresis Threshold RegisterNot2Release */
-#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_HYST_QN_Port_6 0x04e02c70 /* LAN Port Queue N Hysteresis Threshold RegisterNot2Release */
-#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_HYST_QN_Port_7 0x04e02c78 /* LAN Port Queue N Hysteresis Threshold RegisterNot2Release */
-#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_PAUSE_QN_Port_0 0x04e02c80 /* LAN Port Queue N Pause Threshold RegisterNot2Release */
-#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_PAUSE_QN_Port_1 0x04e02c88 /* LAN Port Queue N Pause Threshold RegisterNot2Release */
-#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_PAUSE_QN_Port_2 0x04e02c90 /* LAN Port Queue N Pause Threshold RegisterNot2Release */
-#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_PAUSE_QN_Port_3 0x04e02c98 /* LAN Port Queue N Pause Threshold RegisterNot2Release */
-#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_PAUSE_QN_Port_4 0x04e02ca0 /* LAN Port Queue N Pause Threshold RegisterNot2Release */
-#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_PAUSE_QN_Port_5 0x04e02ca8 /* LAN Port Queue N Pause Threshold RegisterNot2Release */
-#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_PAUSE_QN_Port_6 0x04e02cb0 /* LAN Port Queue N Pause Threshold RegisterNot2Release */
-#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_PAUSE_QN_Port_7 0x04e02cb8 /* LAN Port Queue N Pause Threshold RegisterNot2Release */
-#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_DROP_QN_Port_0 0x04e02cc0 /* LAN Port Queue N DROP Threshold RegisterNot2Release */
-#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_DROP_QN_Port_1 0x04e02cc8 /* LAN Port Queue N DROP Threshold RegisterNot2Release */
-#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_DROP_QN_Port_2 0x04e02cd0 /* LAN Port Queue N DROP Threshold RegisterNot2Release */
-#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_DROP_QN_Port_3 0x04e02cd8 /* LAN Port Queue N DROP Threshold RegisterNot2Release */
-#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_DROP_QN_Port_4 0x04e02ce0 /* LAN Port Queue N DROP Threshold RegisterNot2Release */
-#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_DROP_QN_Port_5 0x04e02ce8 /* LAN Port Queue N DROP Threshold RegisterNot2Release */
-#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_DROP_QN_Port_6 0x04e02cf0 /* LAN Port Queue N DROP Threshold RegisterNot2Release */
-#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_DROP_QN_Port_7 0x04e02cf8 /* LAN Port Queue N DROP Threshold RegisterNot2Release */
-#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_HYST_QN_Port_0 0x04e02d00 /* LAN Port Queue N Total Hysteresis Threshold RegisterNot2Release */
-#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_HYST_QN_Port_1 0x04e02d08 /* LAN Port Queue N Total Hysteresis Threshold RegisterNot2Release */
-#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_HYST_QN_Port_2 0x04e02d10 /* LAN Port Queue N Total Hysteresis Threshold RegisterNot2Release */
-#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_HYST_QN_Port_3 0x04e02d18 /* LAN Port Queue N Total Hysteresis Threshold RegisterNot2Release */
-#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_HYST_QN_Port_4 0x04e02d20 /* LAN Port Queue N Total Hysteresis Threshold RegisterNot2Release */
-#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_HYST_QN_Port_5 0x04e02d28 /* LAN Port Queue N Total Hysteresis Threshold RegisterNot2Release */
-#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_HYST_QN_Port_6 0x04e02d30 /* LAN Port Queue N Total Hysteresis Threshold RegisterNot2Release */
-#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_HYST_QN_Port_7 0x04e02d38 /* LAN Port Queue N Total Hysteresis Threshold RegisterNot2Release */
-#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_PAUSE_QN_Port_0 0x04e02d40 /* LAN Port Queue N Total Pause Threshold RegisterNot2Release */
-#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_PAUSE_QN_Port_1 0x04e02d48 /* LAN Port Queue N Total Pause Threshold RegisterNot2Release */
-#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_PAUSE_QN_Port_2 0x04e02d50 /* LAN Port Queue N Total Pause Threshold RegisterNot2Release */
-#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_PAUSE_QN_Port_3 0x04e02d58 /* LAN Port Queue N Total Pause Threshold RegisterNot2Release */
-#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_PAUSE_QN_Port_4 0x04e02d60 /* LAN Port Queue N Total Pause Threshold RegisterNot2Release */
-#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_PAUSE_QN_Port_5 0x04e02d68 /* LAN Port Queue N Total Pause Threshold RegisterNot2Release */
-#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_PAUSE_QN_Port_6 0x04e02d70 /* LAN Port Queue N Total Pause Threshold RegisterNot2Release */
-#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_PAUSE_QN_Port_7 0x04e02d78 /* LAN Port Queue N Total Pause Threshold RegisterNot2Release */
-#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_DROP_QN_Port_0 0x04e02d80 /* LAN Port Queue N Total DROP Threshold RegisterNot2Release */
-#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_DROP_QN_Port_1 0x04e02d88 /* LAN Port Queue N Total DROP Threshold RegisterNot2Release */
-#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_DROP_QN_Port_2 0x04e02d90 /* LAN Port Queue N Total DROP Threshold RegisterNot2Release */
-#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_DROP_QN_Port_3 0x04e02d98 /* LAN Port Queue N Total DROP Threshold RegisterNot2Release */
-#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_DROP_QN_Port_4 0x04e02da0 /* LAN Port Queue N Total DROP Threshold RegisterNot2Release */
-#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_DROP_QN_Port_5 0x04e02da8 /* LAN Port Queue N Total DROP Threshold RegisterNot2Release */
-#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_DROP_QN_Port_6 0x04e02db0 /* LAN Port Queue N Total DROP Threshold RegisterNot2Release */
-#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_DROP_QN_Port_7 0x04e02db8 /* LAN Port Queue N Total DROP Threshold RegisterNot2Release */
-#define BCHP_SWITCH_CORE_P0_DEBUG_MUX 0x04e03000 /* P0 DEBUG MUXNot2Release */
-#define BCHP_SWITCH_CORE_P1_DEBUG_MUX 0x04e03010 /* P1 DEBUG MUXNot2Release */
-#define BCHP_SWITCH_CORE_P2_DEBUG_MUX 0x04e03020 /* P2 DEBUG MUXNot2Release */
-#define BCHP_SWITCH_CORE_P3_DEBUG_MUX 0x04e03030 /* P3 DEBUG MUXNot2Release */
-#define BCHP_SWITCH_CORE_P4_DEBUG_MUX 0x04e03040 /* P4 DEBUG MUXNot2Release */
-#define BCHP_SWITCH_CORE_P5_DEBUG_MUX 0x04e03050 /* P5 DEBUG MUXNot2Release */
-#define BCHP_SWITCH_CORE_P6_DEBUG_MUX 0x04e03060 /* P6 DEBUG MUXNot2Release */
-#define BCHP_SWITCH_CORE_P7_DEBUG_MUX 0x04e03070 /* P7 DEBUG MUXNot2Release */
-#define BCHP_SWITCH_CORE_IMP_DEBUG_MUX 0x04e03080 /* IMP DEBUG MUXNot2Release */
-#define BCHP_SWITCH_CORE_CFP_DEBUG_BUS_0 0x04e03090 /* CFP DEBUG BUS 0Not2Release */
-#define BCHP_SWITCH_CORE_CFP_DEBUG_BUS_1 0x04e030a0 /* CFP DEBUG BUS 1Not2Release */
-#define BCHP_SWITCH_CORE_WRED_DEBUG_0 0x04e030b0 /* WRED DEBUG 0Not2Release */
-#define BCHP_SWITCH_CORE_WRED_DEBUG_1 0x04e030c0 /* WRED DEBUG 1Not2Release */
-#define BCHP_SWITCH_CORE_TOP_MISC_DEBUG_0 0x04e030d0 /* TOP MISC DEBUG 0Not2Release */
-#define BCHP_SWITCH_CORE_TOP_MISC_DEBUG_1 0x04e030e0 /* TOP MISC DEBUG 1Not2Release */
-#define BCHP_SWITCH_CORE_DIAGREG_BUFCON 0x04e030f0 /* DIAGREG BUFCONNot2Release */
-#define BCHP_SWITCH_CORE_TESTBUS_P1588 0x04e03100 /* TESTBUS P1588Not2Release */
-#define BCHP_SWITCH_CORE_FLOWCON_DEBUG_BUS 0x04e03110 /* FLOWCON DEBUG BUSNot2Release */
-#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_RSV_QN_Port_0 0x04e03400 /* IMP0 Port Queue N Reserved Threshold RegisterNot2Release */
-#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_RSV_QN_Port_1 0x04e03408 /* IMP0 Port Queue N Reserved Threshold RegisterNot2Release */
-#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_RSV_QN_Port_2 0x04e03410 /* IMP0 Port Queue N Reserved Threshold RegisterNot2Release */
-#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_RSV_QN_Port_3 0x04e03418 /* IMP0 Port Queue N Reserved Threshold RegisterNot2Release */
-#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_RSV_QN_Port_4 0x04e03420 /* IMP0 Port Queue N Reserved Threshold RegisterNot2Release */
-#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_RSV_QN_Port_5 0x04e03428 /* IMP0 Port Queue N Reserved Threshold RegisterNot2Release */
-#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_RSV_QN_Port_6 0x04e03430 /* IMP0 Port Queue N Reserved Threshold RegisterNot2Release */
-#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_RSV_QN_Port_7 0x04e03438 /* IMP0 Port Queue N Reserved Threshold RegisterNot2Release */
-#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_HYST_QN_Port_0 0x04e03440 /* IMP0 Port Queue N Hysteresis Threshold RegisterNot2Release */
-#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_HYST_QN_Port_1 0x04e03448 /* IMP0 Port Queue N Hysteresis Threshold RegisterNot2Release */
-#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_HYST_QN_Port_2 0x04e03450 /* IMP0 Port Queue N Hysteresis Threshold RegisterNot2Release */
-#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_HYST_QN_Port_3 0x04e03458 /* IMP0 Port Queue N Hysteresis Threshold RegisterNot2Release */
-#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_HYST_QN_Port_4 0x04e03460 /* IMP0 Port Queue N Hysteresis Threshold RegisterNot2Release */
-#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_HYST_QN_Port_5 0x04e03468 /* IMP0 Port Queue N Hysteresis Threshold RegisterNot2Release */
-#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_HYST_QN_Port_6 0x04e03470 /* IMP0 Port Queue N Hysteresis Threshold RegisterNot2Release */
-#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_HYST_QN_Port_7 0x04e03478 /* IMP0 Port Queue N Hysteresis Threshold RegisterNot2Release */
-#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_PAUSE_QN_Port_0 0x04e03480 /* IMP0 Port Queue N Pause Threshold RegisterNot2Release */
-#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_PAUSE_QN_Port_1 0x04e03488 /* IMP0 Port Queue N Pause Threshold RegisterNot2Release */
-#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_PAUSE_QN_Port_2 0x04e03490 /* IMP0 Port Queue N Pause Threshold RegisterNot2Release */
-#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_PAUSE_QN_Port_3 0x04e03498 /* IMP0 Port Queue N Pause Threshold RegisterNot2Release */
-#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_PAUSE_QN_Port_4 0x04e034a0 /* IMP0 Port Queue N Pause Threshold RegisterNot2Release */
-#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_PAUSE_QN_Port_5 0x04e034a8 /* IMP0 Port Queue N Pause Threshold RegisterNot2Release */
-#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_PAUSE_QN_Port_6 0x04e034b0 /* IMP0 Port Queue N Pause Threshold RegisterNot2Release */
-#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_PAUSE_QN_Port_7 0x04e034b8 /* IMP0 Port Queue N Pause Threshold RegisterNot2Release */
-#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_DROP_QN_Port_0 0x04e034c0 /* IMP0 Port Queue N DROP Threshold RegisterNot2Release */
-#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_DROP_QN_Port_1 0x04e034c8 /* IMP0 Port Queue N DROP Threshold RegisterNot2Release */
-#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_DROP_QN_Port_2 0x04e034d0 /* IMP0 Port Queue N DROP Threshold RegisterNot2Release */
-#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_DROP_QN_Port_3 0x04e034d8 /* IMP0 Port Queue N DROP Threshold RegisterNot2Release */
-#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_DROP_QN_Port_4 0x04e034e0 /* IMP0 Port Queue N DROP Threshold RegisterNot2Release */
-#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_DROP_QN_Port_5 0x04e034e8 /* IMP0 Port Queue N DROP Threshold RegisterNot2Release */
-#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_DROP_QN_Port_6 0x04e034f0 /* IMP0 Port Queue N DROP Threshold RegisterNot2Release */
-#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_DROP_QN_Port_7 0x04e034f8 /* IMP0 Port Queue N DROP Threshold RegisterNot2Release */
-#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_HYST_QN_Port_0 0x04e03500 /* IMP0 Port Queue N Total Hysteresis Threshold RegisterNot2Release */
-#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_HYST_QN_Port_1 0x04e03508 /* IMP0 Port Queue N Total Hysteresis Threshold RegisterNot2Release */
-#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_HYST_QN_Port_2 0x04e03510 /* IMP0 Port Queue N Total Hysteresis Threshold RegisterNot2Release */
-#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_HYST_QN_Port_3 0x04e03518 /* IMP0 Port Queue N Total Hysteresis Threshold RegisterNot2Release */
-#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_HYST_QN_Port_4 0x04e03520 /* IMP0 Port Queue N Total Hysteresis Threshold RegisterNot2Release */
-#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_HYST_QN_Port_5 0x04e03528 /* IMP0 Port Queue N Total Hysteresis Threshold RegisterNot2Release */
-#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_HYST_QN_Port_6 0x04e03530 /* IMP0 Port Queue N Total Hysteresis Threshold RegisterNot2Release */
-#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_HYST_QN_Port_7 0x04e03538 /* IMP0 Port Queue N Total Hysteresis Threshold RegisterNot2Release */
-#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_PAUSE_QN_Port_0 0x04e03540 /* IMP0 Port Queue N Total Pause Threshold RegisterNot2Release */
-#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_PAUSE_QN_Port_1 0x04e03548 /* IMP0 Port Queue N Total Pause Threshold RegisterNot2Release */
-#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_PAUSE_QN_Port_2 0x04e03550 /* IMP0 Port Queue N Total Pause Threshold RegisterNot2Release */
-#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_PAUSE_QN_Port_3 0x04e03558 /* IMP0 Port Queue N Total Pause Threshold RegisterNot2Release */
-#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_PAUSE_QN_Port_4 0x04e03560 /* IMP0 Port Queue N Total Pause Threshold RegisterNot2Release */
-#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_PAUSE_QN_Port_5 0x04e03568 /* IMP0 Port Queue N Total Pause Threshold RegisterNot2Release */
-#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_PAUSE_QN_Port_6 0x04e03570 /* IMP0 Port Queue N Total Pause Threshold RegisterNot2Release */
-#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_PAUSE_QN_Port_7 0x04e03578 /* IMP0 Port Queue N Total Pause Threshold RegisterNot2Release */
-#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_DROP_QN_Port_0 0x04e03580 /* IMP0 Port Queue N Total DROP Threshold RegisterNot2Release */
-#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_DROP_QN_Port_1 0x04e03588 /* IMP0 Port Queue N Total DROP Threshold RegisterNot2Release */
-#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_DROP_QN_Port_2 0x04e03590 /* IMP0 Port Queue N Total DROP Threshold RegisterNot2Release */
-#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_DROP_QN_Port_3 0x04e03598 /* IMP0 Port Queue N Total DROP Threshold RegisterNot2Release */
-#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_DROP_QN_Port_4 0x04e035a0 /* IMP0 Port Queue N Total DROP Threshold RegisterNot2Release */
-#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_DROP_QN_Port_5 0x04e035a8 /* IMP0 Port Queue N Total DROP Threshold RegisterNot2Release */
-#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_DROP_QN_Port_6 0x04e035b0 /* IMP0 Port Queue N Total DROP Threshold RegisterNot2Release */
-#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_DROP_QN_Port_7 0x04e035b8 /* IMP0 Port Queue N Total DROP Threshold RegisterNot2Release */
-#define BCHP_SWITCH_CORE_FC_IMP0_REG_SPARE0 0x04e035c0 /* Spare 0 Register (Not2Release)Not2Release */
-#define BCHP_SWITCH_CORE_FC_IMP0_REG_SPARE1 0x04e035c8 /* Spare 1 Register (Not2Release)Not2Release */
-#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_RSV_QN_Port_0 0x04e03800 /* WAN/IMP1 Port Queue N Reserved Threshold RegisterNot2Release */
-#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_RSV_QN_Port_1 0x04e03808 /* WAN/IMP1 Port Queue N Reserved Threshold RegisterNot2Release */
-#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_RSV_QN_Port_2 0x04e03810 /* WAN/IMP1 Port Queue N Reserved Threshold RegisterNot2Release */
-#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_RSV_QN_Port_3 0x04e03818 /* WAN/IMP1 Port Queue N Reserved Threshold RegisterNot2Release */
-#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_RSV_QN_Port_4 0x04e03820 /* WAN/IMP1 Port Queue N Reserved Threshold RegisterNot2Release */
-#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_RSV_QN_Port_5 0x04e03828 /* WAN/IMP1 Port Queue N Reserved Threshold RegisterNot2Release */
-#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_RSV_QN_Port_6 0x04e03830 /* WAN/IMP1 Port Queue N Reserved Threshold RegisterNot2Release */
-#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_RSV_QN_Port_7 0x04e03838 /* WAN/IMP1 Port Queue N Reserved Threshold RegisterNot2Release */
-#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_HYST_QN_Port_0 0x04e03840 /* WAN/IMP1 Port Queue N Hysteresis Threshold RegisterNot2Release */
-#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_HYST_QN_Port_1 0x04e03848 /* WAN/IMP1 Port Queue N Hysteresis Threshold RegisterNot2Release */
-#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_HYST_QN_Port_2 0x04e03850 /* WAN/IMP1 Port Queue N Hysteresis Threshold RegisterNot2Release */
-#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_HYST_QN_Port_3 0x04e03858 /* WAN/IMP1 Port Queue N Hysteresis Threshold RegisterNot2Release */
-#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_HYST_QN_Port_4 0x04e03860 /* WAN/IMP1 Port Queue N Hysteresis Threshold RegisterNot2Release */
-#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_HYST_QN_Port_5 0x04e03868 /* WAN/IMP1 Port Queue N Hysteresis Threshold RegisterNot2Release */
-#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_HYST_QN_Port_6 0x04e03870 /* WAN/IMP1 Port Queue N Hysteresis Threshold RegisterNot2Release */
-#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_HYST_QN_Port_7 0x04e03878 /* WAN/IMP1 Port Queue N Hysteresis Threshold RegisterNot2Release */
-#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_PAUSE_QN_Port_0 0x04e03880 /* WAN/IMP1 Port Queue N Pause Threshold RegisterNot2Release */
-#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_PAUSE_QN_Port_1 0x04e03888 /* WAN/IMP1 Port Queue N Pause Threshold RegisterNot2Release */
-#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_PAUSE_QN_Port_2 0x04e03890 /* WAN/IMP1 Port Queue N Pause Threshold RegisterNot2Release */
-#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_PAUSE_QN_Port_3 0x04e03898 /* WAN/IMP1 Port Queue N Pause Threshold RegisterNot2Release */
-#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_PAUSE_QN_Port_4 0x04e038a0 /* WAN/IMP1 Port Queue N Pause Threshold RegisterNot2Release */
-#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_PAUSE_QN_Port_5 0x04e038a8 /* WAN/IMP1 Port Queue N Pause Threshold RegisterNot2Release */
-#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_PAUSE_QN_Port_6 0x04e038b0 /* WAN/IMP1 Port Queue N Pause Threshold RegisterNot2Release */
-#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_PAUSE_QN_Port_7 0x04e038b8 /* WAN/IMP1 Port Queue N Pause Threshold RegisterNot2Release */
-#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_DROP_QN_Port_0 0x04e038c0 /* WAN/IMP1 Port Queue N DROP Threshold RegisterNot2Release */
-#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_DROP_QN_Port_1 0x04e038c8 /* WAN/IMP1 Port Queue N DROP Threshold RegisterNot2Release */
-#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_DROP_QN_Port_2 0x04e038d0 /* WAN/IMP1 Port Queue N DROP Threshold RegisterNot2Release */
-#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_DROP_QN_Port_3 0x04e038d8 /* WAN/IMP1 Port Queue N DROP Threshold RegisterNot2Release */
-#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_DROP_QN_Port_4 0x04e038e0 /* WAN/IMP1 Port Queue N DROP Threshold RegisterNot2Release */
-#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_DROP_QN_Port_5 0x04e038e8 /* WAN/IMP1 Port Queue N DROP Threshold RegisterNot2Release */
-#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_DROP_QN_Port_6 0x04e038f0 /* WAN/IMP1 Port Queue N DROP Threshold RegisterNot2Release */
-#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_DROP_QN_Port_7 0x04e038f8 /* WAN/IMP1 Port Queue N DROP Threshold RegisterNot2Release */
-#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_HYST_QN_Port_0 0x04e03900 /* WAN/IMP1 Port Queue N Total Hysteresis Threshold RegisterNot2Release */
-#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_HYST_QN_Port_1 0x04e03908 /* WAN/IMP1 Port Queue N Total Hysteresis Threshold RegisterNot2Release */
-#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_HYST_QN_Port_2 0x04e03910 /* WAN/IMP1 Port Queue N Total Hysteresis Threshold RegisterNot2Release */
-#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_HYST_QN_Port_3 0x04e03918 /* WAN/IMP1 Port Queue N Total Hysteresis Threshold RegisterNot2Release */
-#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_HYST_QN_Port_4 0x04e03920 /* WAN/IMP1 Port Queue N Total Hysteresis Threshold RegisterNot2Release */
-#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_HYST_QN_Port_5 0x04e03928 /* WAN/IMP1 Port Queue N Total Hysteresis Threshold RegisterNot2Release */
-#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_HYST_QN_Port_6 0x04e03930 /* WAN/IMP1 Port Queue N Total Hysteresis Threshold RegisterNot2Release */
-#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_HYST_QN_Port_7 0x04e03938 /* WAN/IMP1 Port Queue N Total Hysteresis Threshold RegisterNot2Release */
-#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_PAUSE_QN_Port_0 0x04e03940 /* WAN/IMP1 Port Queue N Total Pause Threshold RegisterNot2Release */
-#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_PAUSE_QN_Port_1 0x04e03948 /* WAN/IMP1 Port Queue N Total Pause Threshold RegisterNot2Release */
-#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_PAUSE_QN_Port_2 0x04e03950 /* WAN/IMP1 Port Queue N Total Pause Threshold RegisterNot2Release */
-#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_PAUSE_QN_Port_3 0x04e03958 /* WAN/IMP1 Port Queue N Total Pause Threshold RegisterNot2Release */
-#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_PAUSE_QN_Port_4 0x04e03960 /* WAN/IMP1 Port Queue N Total Pause Threshold RegisterNot2Release */
-#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_PAUSE_QN_Port_5 0x04e03968 /* WAN/IMP1 Port Queue N Total Pause Threshold RegisterNot2Release */
-#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_PAUSE_QN_Port_6 0x04e03970 /* WAN/IMP1 Port Queue N Total Pause Threshold RegisterNot2Release */
-#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_PAUSE_QN_Port_7 0x04e03978 /* WAN/IMP1 Port Queue N Total Pause Threshold RegisterNot2Release */
-#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_DROP_QN_Port_0 0x04e03980 /* WAN/IMP1 Port Queue N Total DROP Threshold RegisterNot2Release */
-#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_DROP_QN_Port_1 0x04e03988 /* WAN/IMP1 Port Queue N Total DROP Threshold RegisterNot2Release */
-#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_DROP_QN_Port_2 0x04e03990 /* WAN/IMP1 Port Queue N Total DROP Threshold RegisterNot2Release */
-#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_DROP_QN_Port_3 0x04e03998 /* WAN/IMP1 Port Queue N Total DROP Threshold RegisterNot2Release */
-#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_DROP_QN_Port_4 0x04e039a0 /* WAN/IMP1 Port Queue N Total DROP Threshold RegisterNot2Release */
-#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_DROP_QN_Port_5 0x04e039a8 /* WAN/IMP1 Port Queue N Total DROP Threshold RegisterNot2Release */
-#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_DROP_QN_Port_6 0x04e039b0 /* WAN/IMP1 Port Queue N Total DROP Threshold RegisterNot2Release */
-#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_DROP_QN_Port_7 0x04e039b8 /* WAN/IMP1 Port Queue N Total DROP Threshold RegisterNot2Release */
-#define BCHP_SWITCH_CORE_FC_WAN_IMP1_REG_SPARE0 0x04e039c0 /* Spare 0 Register (Not2Release)Not2Release */
-#define BCHP_SWITCH_CORE_FC_WAN_IMP1_REG_SPARE1 0x04e039c8 /* Spare 1 Register (Not2Release)Not2Release */
-#define BCHP_SWITCH_CORE_TEMP_MON_CTL 0x04e03c00 /* Temperature Monitor Control Registers(Not2Release)Not2Release */
-#define BCHP_SWITCH_CORE_TEMP_MON_RESU 0x04e03c08 /* Temperature Monitor Result Registers(Not2Release)Not2Release */
-#define BCHP_SWITCH_CORE_PEAK_TEMP_MON_RESU 0x04e03c10 /* Peak Temperature Monitor Result Registers(Not2Release)Not2Release */
-#define BCHP_SWITCH_CORE_TEMP_MON_CAL 0x04e03c18 /* Temperature Monitor Calibration Registers(Not2Release)Not2Release */
-#define BCHP_SWITCH_CORE_TEMP_MON_SPEC_CTL 0x04e03c20 /* Temperature Monitor Special Control Registers(Not2Release)Not2Release */
-#define BCHP_SWITCH_CORE_TxOctets_P0 0x04e08000 /* Tx Octets */
-#define BCHP_SWITCH_CORE_TxDropPkts_P0 0x04e08020 /* Tx Drop Packet Counter */
-#define BCHP_SWITCH_CORE_TxQPKTQ0_P0 0x04e08030 /* Tx Q0 Packet Counter */
-#define BCHP_SWITCH_CORE_TxBroadcastPkts_P0 0x04e08040 /* Tx Broadcast Packet Counter */
-#define BCHP_SWITCH_CORE_TxMulticastPkts_P0 0x04e08050 /* Tx Multicast Packet Counter */
-#define BCHP_SWITCH_CORE_TxUnicastPkts_P0 0x04e08060 /* Tx Unicast Packet Counter */
-#define BCHP_SWITCH_CORE_TxCollisions_P0 0x04e08070 /* Tx Collision Counter */
-#define BCHP_SWITCH_CORE_TxSingleCollision_P0 0x04e08080 /* Tx Single Collision Counter */
-#define BCHP_SWITCH_CORE_TxMultipleCollision_P0 0x04e08090 /* Tx Multiple collsion Counter */
-#define BCHP_SWITCH_CORE_TxDeferredTransmit_P0 0x04e080a0 /* Tx Deferred Transmit Counter */
-#define BCHP_SWITCH_CORE_TxLateCollision_P0 0x04e080b0 /* Tx Late Collision Counter */
-#define BCHP_SWITCH_CORE_TxExcessiveCollision_P0 0x04e080c0 /* Tx Excessive Collision Counter */
-#define BCHP_SWITCH_CORE_TxFrameInDisc_P0 0x04e080d0 /* Tx Fram IN Disc Counter */
-#define BCHP_SWITCH_CORE_TxPausePkts_P0 0x04e080e0 /* Tx Pause Packet Counter */
-#define BCHP_SWITCH_CORE_TxQPKTQ1_P0 0x04e080f0 /* Tx Q1 Packet Counter */
-#define BCHP_SWITCH_CORE_TxQPKTQ2_P0 0x04e08100 /* Tx Q2 Packet Counter */
-#define BCHP_SWITCH_CORE_TxQPKTQ3_P0 0x04e08110 /* Tx Q3 Packet Counter */
-#define BCHP_SWITCH_CORE_TxQPKTQ4_P0 0x04e08120 /* Tx Q4 Packet Counter */
-#define BCHP_SWITCH_CORE_TxQPKTQ5_P0 0x04e08130 /* Tx Q5 Packet Counter */
-#define BCHP_SWITCH_CORE_RxOctets_P0 0x04e08140 /* Rx Packet Octets Counter */
-#define BCHP_SWITCH_CORE_RxUndersizePkts_P0 0x04e08160 /* Rx Under Size Packet Octets Counter */
-#define BCHP_SWITCH_CORE_RxPausePkts_P0 0x04e08170 /* Rx Pause Packet Counter */
-#define BCHP_SWITCH_CORE_RxPkts64Octets_P0 0x04e08180 /* Rx 64 Bytes Octets Counter */
-#define BCHP_SWITCH_CORE_RxPkts65to127Octets_P0 0x04e08190 /* Rx 65 to 127 Bytes Octets Counter */
-#define BCHP_SWITCH_CORE_RxPkts128to255Octets_P0 0x04e081a0 /* Rx 128 to 255 Bytes Octets Counter */
-#define BCHP_SWITCH_CORE_RxPkts256to511Octets_P0 0x04e081b0 /* Rx 256 to 511 Bytes Octets Counter */
-#define BCHP_SWITCH_CORE_RxPkts512to1023Octets_P0 0x04e081c0 /* Rx 512 to 1023 Bytes Octets Counter */
-#define BCHP_SWITCH_CORE_RxPkts1024toMaxPktOctets_P0 0x04e081d0 /* Rx 1024 to MaxPkt Bytes Octets Counter */
-#define BCHP_SWITCH_CORE_RxOversizePkts_P0 0x04e081e0 /* Rx Over Size Packet Counter */
-#define BCHP_SWITCH_CORE_RxJabbers_P0 0x04e081f0 /* Rx Jabber Packet Counter */
-#define BCHP_SWITCH_CORE_RxAlignmentErrors_P0 0x04e08200 /* Rx Alignment Error Counter */
-#define BCHP_SWITCH_CORE_RxFCSErrors_P0 0x04e08210 /* Rx FCS Error Counter */
-#define BCHP_SWITCH_CORE_RxGoodOctets_P0 0x04e08220 /* Rx Good Packet Octet Counter */
-#define BCHP_SWITCH_CORE_RxDropPkts_P0 0x04e08240 /* Rx Drop Packet Counter */
-#define BCHP_SWITCH_CORE_RxUnicastPkts_P0 0x04e08250 /* Rx Unicast Packet Counter */
-#define BCHP_SWITCH_CORE_RxMulticastPkts_P0 0x04e08260 /* Rx Multicast Packet Counter */
-#define BCHP_SWITCH_CORE_RxBroadcastPkts_P0 0x04e08270 /* Rx Broadcast Packet Counter */
-#define BCHP_SWITCH_CORE_RxSAChanges_P0 0x04e08280 /* Rx SA Change Counter */
-#define BCHP_SWITCH_CORE_RxFragments_P0 0x04e08290 /* Rx Fragment Counter */
-#define BCHP_SWITCH_CORE_RxJumboPkt_P0 0x04e082a0 /* Jumbo Packet Counter */
-#define BCHP_SWITCH_CORE_RxSymblErr_P0 0x04e082b0 /* Rx Symbol Error Counter */
-#define BCHP_SWITCH_CORE_InRangeErrCount_P0 0x04e082c0 /* InRangeErrCount Counter */
-#define BCHP_SWITCH_CORE_OutRangeErrCount_P0 0x04e082d0 /* OutRangeErrCount Counter */
-#define BCHP_SWITCH_CORE_EEE_LPI_EVENT_P0 0x04e082e0 /* EEE Low-Power Idle Event Registers */
-#define BCHP_SWITCH_CORE_EEE_LPI_DURATION_P0 0x04e082f0 /* EEE Low-Power Idle Duration Registers */
-#define BCHP_SWITCH_CORE_RxDiscard_P0 0x04e08300 /* Rx Discard Counter */
-#define BCHP_SWITCH_CORE_TxQPKTQ6_P0 0x04e08320 /* Tx Q6 Packet Counter */
-#define BCHP_SWITCH_CORE_TxQPKTQ7_P0 0x04e08330 /* Tx Q7 Packet Counter */
-#define BCHP_SWITCH_CORE_TxPkts64Octets_P0 0x04e08340 /* Tx 64 Bytes Octets Counter */
-#define BCHP_SWITCH_CORE_TxPkts65to127Octets_P0 0x04e08350 /* Tx 65 to 127 Bytes Octets Counter */
-#define BCHP_SWITCH_CORE_TxPkts128to255Octets_P0 0x04e08360 /* Tx 128 to 255 Bytes Octets Counter */
-#define BCHP_SWITCH_CORE_TxPkts256to511Octets_P0 0x04e08370 /* Tx 256 to 511 Bytes Octets Counter */
-#define BCHP_SWITCH_CORE_TxPkts512to1023Octets_P0 0x04e08380 /* Tx 512 to 1023 Bytes Octets Counter */
-#define BCHP_SWITCH_CORE_TxPkts1024toMaxPktOctets_P0 0x04e08390 /* Tx 1024 to MaxPkt Bytes Octets Counter */
-#define BCHP_SWITCH_CORE_TxOctets_P1 0x04e08400 /* Tx Octets */
-#define BCHP_SWITCH_CORE_TxDropPkts_P1 0x04e08420 /* Tx Drop Packet Counter */
-#define BCHP_SWITCH_CORE_TxQPKTQ0_P1 0x04e08430 /* Tx Q0 Packet Counter */
-#define BCHP_SWITCH_CORE_TxBroadcastPkts_P1 0x04e08440 /* Tx Broadcast Packet Counter */
-#define BCHP_SWITCH_CORE_TxMulticastPkts_P1 0x04e08450 /* Tx Multicast Packet Counter */
-#define BCHP_SWITCH_CORE_TxUnicastPkts_P1 0x04e08460 /* Tx Unicast Packet Counter */
-#define BCHP_SWITCH_CORE_TxCollisions_P1 0x04e08470 /* Tx Collision Counter */
-#define BCHP_SWITCH_CORE_TxSingleCollision_P1 0x04e08480 /* Tx Single Collision Counter */
-#define BCHP_SWITCH_CORE_TxMultipleCollision_P1 0x04e08490 /* Tx Multiple collsion Counter */
-#define BCHP_SWITCH_CORE_TxDeferredTransmit_P1 0x04e084a0 /* Tx Deferred Transmit Counter */
-#define BCHP_SWITCH_CORE_TxLateCollision_P1 0x04e084b0 /* Tx Late Collision Counter */
-#define BCHP_SWITCH_CORE_TxExcessiveCollision_P1 0x04e084c0 /* Tx Excessive Collision Counter */
-#define BCHP_SWITCH_CORE_TxFrameInDisc_P1 0x04e084d0 /* Tx Fram IN Disc Counter */
-#define BCHP_SWITCH_CORE_TxPausePkts_P1 0x04e084e0 /* Tx Pause Packet Counter */
-#define BCHP_SWITCH_CORE_TxQPKTQ1_P1 0x04e084f0 /* Tx Q1 Packet Counter */
-#define BCHP_SWITCH_CORE_TxQPKTQ2_P1 0x04e08500 /* Tx Q2 Packet Counter */
-#define BCHP_SWITCH_CORE_TxQPKTQ3_P1 0x04e08510 /* Tx Q3 Packet Counter */
-#define BCHP_SWITCH_CORE_TxQPKTQ4_P1 0x04e08520 /* Tx Q4 Packet Counter */
-#define BCHP_SWITCH_CORE_TxQPKTQ5_P1 0x04e08530 /* Tx Q5 Packet Counter */
-#define BCHP_SWITCH_CORE_RxOctets_P1 0x04e08540 /* Rx Packet Octets Counter */
-#define BCHP_SWITCH_CORE_RxUndersizePkts_P1 0x04e08560 /* Rx Under Size Packet Octets Counter */
-#define BCHP_SWITCH_CORE_RxPausePkts_P1 0x04e08570 /* Rx Pause Packet Counter */
-#define BCHP_SWITCH_CORE_RxPkts64Octets_P1 0x04e08580 /* Rx 64 Bytes Octets Counter */
-#define BCHP_SWITCH_CORE_RxPkts65to127Octets_P1 0x04e08590 /* Rx 65 to 127 Bytes Octets Counter */
-#define BCHP_SWITCH_CORE_RxPkts128to255Octets_P1 0x04e085a0 /* Rx 128 to 255 Bytes Octets Counter */
-#define BCHP_SWITCH_CORE_RxPkts256to511Octets_P1 0x04e085b0 /* Rx 256 to 511 Bytes Octets Counter */
-#define BCHP_SWITCH_CORE_RxPkts512to1023Octets_P1 0x04e085c0 /* Rx 512 to 1023 Bytes Octets Counter */
-#define BCHP_SWITCH_CORE_RxPkts1024toMaxPktOctets_P1 0x04e085d0 /* Rx 1024 to MaxPkt Bytes Octets Counter */
-#define BCHP_SWITCH_CORE_RxOversizePkts_P1 0x04e085e0 /* Rx Over Size Packet Counter */
-#define BCHP_SWITCH_CORE_RxJabbers_P1 0x04e085f0 /* Rx Jabber Packet Counter */
-#define BCHP_SWITCH_CORE_RxAlignmentErrors_P1 0x04e08600 /* Rx Alignment Error Counter */
-#define BCHP_SWITCH_CORE_RxFCSErrors_P1 0x04e08610 /* Rx FCS Error Counter */
-#define BCHP_SWITCH_CORE_RxGoodOctets_P1 0x04e08620 /* Rx Good Packet Octet Counter */
-#define BCHP_SWITCH_CORE_RxDropPkts_P1 0x04e08640 /* Rx Drop Packet Counter */
-#define BCHP_SWITCH_CORE_RxUnicastPkts_P1 0x04e08650 /* Rx Unicast Packet Counter */
-#define BCHP_SWITCH_CORE_RxMulticastPkts_P1 0x04e08660 /* Rx Multicast Packet Counter */
-#define BCHP_SWITCH_CORE_RxBroadcastPkts_P1 0x04e08670 /* Rx Broadcast Packet Counter */
-#define BCHP_SWITCH_CORE_RxSAChanges_P1 0x04e08680 /* Rx SA Change Counter */
-#define BCHP_SWITCH_CORE_RxFragments_P1 0x04e08690 /* Rx Fragment Counter */
-#define BCHP_SWITCH_CORE_RxJumboPkt_P1 0x04e086a0 /* Jumbo Packet Counter */
-#define BCHP_SWITCH_CORE_RxSymblErr_P1 0x04e086b0 /* Rx Symbol Error Counter */
-#define BCHP_SWITCH_CORE_InRangeErrCount_P1 0x04e086c0 /* InRangeErrCount Counter */
-#define BCHP_SWITCH_CORE_OutRangeErrCount_P1 0x04e086d0 /* OutRangeErrCount Counter */
-#define BCHP_SWITCH_CORE_EEE_LPI_EVENT_P1 0x04e086e0 /* EEE Low-Power Idle Event Registers */
-#define BCHP_SWITCH_CORE_EEE_LPI_DURATION_P1 0x04e086f0 /* EEE Low-Power Idle Duration Registers */
-#define BCHP_SWITCH_CORE_RxDiscard_P1 0x04e08700 /* Rx Discard Counter */
-#define BCHP_SWITCH_CORE_TxQPKTQ6_P1 0x04e08720 /* Tx Q6 Packet Counter */
-#define BCHP_SWITCH_CORE_TxQPKTQ7_P1 0x04e08730 /* Tx Q7 Packet Counter */
-#define BCHP_SWITCH_CORE_TxPkts64Octets_P1 0x04e08740 /* Tx 64 Bytes Octets Counter */
-#define BCHP_SWITCH_CORE_TxPkts65to127Octets_P1 0x04e08750 /* Tx 65 to 127 Bytes Octets Counter */
-#define BCHP_SWITCH_CORE_TxPkts128to255Octets_P1 0x04e08760 /* Tx 128 to 255 Bytes Octets Counter */
-#define BCHP_SWITCH_CORE_TxPkts256to511Octets_P1 0x04e08770 /* Tx 256 to 511 Bytes Octets Counter */
-#define BCHP_SWITCH_CORE_TxPkts512to1023Octets_P1 0x04e08780 /* Tx 512 to 1023 Bytes Octets Counter */
-#define BCHP_SWITCH_CORE_TxPkts1024toMaxPktOctets_P1 0x04e08790 /* Tx 1024 to MaxPkt Bytes Octets Counter */
-#define BCHP_SWITCH_CORE_TxOctets_P2 0x04e08800 /* Tx Octets */
-#define BCHP_SWITCH_CORE_TxDropPkts_P2 0x04e08820 /* Tx Drop Packet Counter */
-#define BCHP_SWITCH_CORE_TxQPKTQ0_P2 0x04e08830 /* Tx Q0 Packet Counter */
-#define BCHP_SWITCH_CORE_TxBroadcastPkts_P2 0x04e08840 /* Tx Broadcast Packet Counter */
-#define BCHP_SWITCH_CORE_TxMulticastPkts_P2 0x04e08850 /* Tx Multicast Packet Counter */
-#define BCHP_SWITCH_CORE_TxUnicastPkts_P2 0x04e08860 /* Tx Unicast Packet Counter */
-#define BCHP_SWITCH_CORE_TxCollisions_P2 0x04e08870 /* Tx Collision Counter */
-#define BCHP_SWITCH_CORE_TxSingleCollision_P2 0x04e08880 /* Tx Single Collision Counter */
-#define BCHP_SWITCH_CORE_TxMultipleCollision_P2 0x04e08890 /* Tx Multiple collsion Counter */
-#define BCHP_SWITCH_CORE_TxDeferredTransmit_P2 0x04e088a0 /* Tx Deferred Transmit Counter */
-#define BCHP_SWITCH_CORE_TxLateCollision_P2 0x04e088b0 /* Tx Late Collision Counter */
-#define BCHP_SWITCH_CORE_TxExcessiveCollision_P2 0x04e088c0 /* Tx Excessive Collision Counter */
-#define BCHP_SWITCH_CORE_TxFrameInDisc_P2 0x04e088d0 /* Tx Fram IN Disc Counter */
-#define BCHP_SWITCH_CORE_TxPausePkts_P2 0x04e088e0 /* Tx Pause Packet Counter */
-#define BCHP_SWITCH_CORE_TxQPKTQ1_P2 0x04e088f0 /* Tx Q1 Packet Counter */
-#define BCHP_SWITCH_CORE_TxQPKTQ2_P2 0x04e08900 /* Tx Q2 Packet Counter */
-#define BCHP_SWITCH_CORE_TxQPKTQ3_P2 0x04e08910 /* Tx Q3 Packet Counter */
-#define BCHP_SWITCH_CORE_TxQPKTQ4_P2 0x04e08920 /* Tx Q4 Packet Counter */
-#define BCHP_SWITCH_CORE_TxQPKTQ5_P2 0x04e08930 /* Tx Q5 Packet Counter */
-#define BCHP_SWITCH_CORE_RxOctets_P2 0x04e08940 /* Rx Packet Octets Counter */
-#define BCHP_SWITCH_CORE_RxUndersizePkts_P2 0x04e08960 /* Rx Under Size Packet Octets Counter */
-#define BCHP_SWITCH_CORE_RxPausePkts_P2 0x04e08970 /* Rx Pause Packet Counter */
-#define BCHP_SWITCH_CORE_RxPkts64Octets_P2 0x04e08980 /* Rx 64 Bytes Octets Counter */
-#define BCHP_SWITCH_CORE_RxPkts65to127Octets_P2 0x04e08990 /* Rx 65 to 127 Bytes Octets Counter */
-#define BCHP_SWITCH_CORE_RxPkts128to255Octets_P2 0x04e089a0 /* Rx 128 to 255 Bytes Octets Counter */
-#define BCHP_SWITCH_CORE_RxPkts256to511Octets_P2 0x04e089b0 /* Rx 256 to 511 Bytes Octets Counter */
-#define BCHP_SWITCH_CORE_RxPkts512to1023Octets_P2 0x04e089c0 /* Rx 512 to 1023 Bytes Octets Counter */
-#define BCHP_SWITCH_CORE_RxPkts1024toMaxPktOctets_P2 0x04e089d0 /* Rx 1024 to MaxPkt Bytes Octets Counter */
-#define BCHP_SWITCH_CORE_RxOversizePkts_P2 0x04e089e0 /* Rx Over Size Packet Counter */
-#define BCHP_SWITCH_CORE_RxJabbers_P2 0x04e089f0 /* Rx Jabber Packet Counter */
-#define BCHP_SWITCH_CORE_RxAlignmentErrors_P2 0x04e08a00 /* Rx Alignment Error Counter */
-#define BCHP_SWITCH_CORE_RxFCSErrors_P2 0x04e08a10 /* Rx FCS Error Counter */
-#define BCHP_SWITCH_CORE_RxGoodOctets_P2 0x04e08a20 /* Rx Good Packet Octet Counter */
-#define BCHP_SWITCH_CORE_RxDropPkts_P2 0x04e08a40 /* Rx Drop Packet Counter */
-#define BCHP_SWITCH_CORE_RxUnicastPkts_P2 0x04e08a50 /* Rx Unicast Packet Counter */
-#define BCHP_SWITCH_CORE_RxMulticastPkts_P2 0x04e08a60 /* Rx Multicast Packet Counter */
-#define BCHP_SWITCH_CORE_RxBroadcastPkts_P2 0x04e08a70 /* Rx Broadcast Packet Counter */
-#define BCHP_SWITCH_CORE_RxSAChanges_P2 0x04e08a80 /* Rx SA Change Counter */
-#define BCHP_SWITCH_CORE_RxFragments_P2 0x04e08a90 /* Rx Fragment Counter */
-#define BCHP_SWITCH_CORE_RxJumboPkt_P2 0x04e08aa0 /* Jumbo Packet Counter */
-#define BCHP_SWITCH_CORE_RxSymblErr_P2 0x04e08ab0 /* Rx Symbol Error Counter */
-#define BCHP_SWITCH_CORE_InRangeErrCount_P2 0x04e08ac0 /* InRangeErrCount Counter */
-#define BCHP_SWITCH_CORE_OutRangeErrCount_P2 0x04e08ad0 /* OutRangeErrCount Counter */
-#define BCHP_SWITCH_CORE_EEE_LPI_EVENT_P2 0x04e08ae0 /* EEE Low-Power Idle Event Registers */
-#define BCHP_SWITCH_CORE_EEE_LPI_DURATION_P2 0x04e08af0 /* EEE Low-Power Idle Duration Registers */
-#define BCHP_SWITCH_CORE_RxDiscard_P2 0x04e08b00 /* Rx Discard Counter */
-#define BCHP_SWITCH_CORE_TxQPKTQ6_P2 0x04e08b20 /* Tx Q6 Packet Counter */
-#define BCHP_SWITCH_CORE_TxQPKTQ7_P2 0x04e08b30 /* Tx Q7 Packet Counter */
-#define BCHP_SWITCH_CORE_TxPkts64Octets_P2 0x04e08b40 /* Tx 64 Bytes Octets Counter */
-#define BCHP_SWITCH_CORE_TxPkts65to127Octets_P2 0x04e08b50 /* Tx 65 to 127 Bytes Octets Counter */
-#define BCHP_SWITCH_CORE_TxPkts128to255Octets_P2 0x04e08b60 /* Tx 128 to 255 Bytes Octets Counter */
-#define BCHP_SWITCH_CORE_TxPkts256to511Octets_P2 0x04e08b70 /* Tx 256 to 511 Bytes Octets Counter */
-#define BCHP_SWITCH_CORE_TxPkts512to1023Octets_P2 0x04e08b80 /* Tx 512 to 1023 Bytes Octets Counter */
-#define BCHP_SWITCH_CORE_TxPkts1024toMaxPktOctets_P2 0x04e08b90 /* Tx 1024 to MaxPkt Bytes Octets Counter */
-#define BCHP_SWITCH_CORE_TxOctets_P3 0x04e08c00 /* Tx Octets */
-#define BCHP_SWITCH_CORE_TxDropPkts_P3 0x04e08c20 /* Tx Drop Packet Counter */
-#define BCHP_SWITCH_CORE_TxQPKTQ0_P3 0x04e08c30 /* Tx Q0 Packet Counter */
-#define BCHP_SWITCH_CORE_TxBroadcastPkts_P3 0x04e08c40 /* Tx Broadcast Packet Counter */
-#define BCHP_SWITCH_CORE_TxMulticastPkts_P3 0x04e08c50 /* Tx Multicast Packet Counter */
-#define BCHP_SWITCH_CORE_TxUnicastPkts_P3 0x04e08c60 /* Tx Unicast Packet Counter */
-#define BCHP_SWITCH_CORE_TxCollisions_P3 0x04e08c70 /* Tx Collision Counter */
-#define BCHP_SWITCH_CORE_TxSingleCollision_P3 0x04e08c80 /* Tx Single Collision Counter */
-#define BCHP_SWITCH_CORE_TxMultipleCollision_P3 0x04e08c90 /* Tx Multiple collsion Counter */
-#define BCHP_SWITCH_CORE_TxDeferredTransmit_P3 0x04e08ca0 /* Tx Deferred Transmit Counter */
-#define BCHP_SWITCH_CORE_TxLateCollision_P3 0x04e08cb0 /* Tx Late Collision Counter */
-#define BCHP_SWITCH_CORE_TxExcessiveCollision_P3 0x04e08cc0 /* Tx Excessive Collision Counter */
-#define BCHP_SWITCH_CORE_TxFrameInDisc_P3 0x04e08cd0 /* Tx Fram IN Disc Counter */
-#define BCHP_SWITCH_CORE_TxPausePkts_P3 0x04e08ce0 /* Tx Pause Packet Counter */
-#define BCHP_SWITCH_CORE_TxQPKTQ1_P3 0x04e08cf0 /* Tx Q1 Packet Counter */
-#define BCHP_SWITCH_CORE_TxQPKTQ2_P3 0x04e08d00 /* Tx Q2 Packet Counter */
-#define BCHP_SWITCH_CORE_TxQPKTQ3_P3 0x04e08d10 /* Tx Q3 Packet Counter */
-#define BCHP_SWITCH_CORE_TxQPKTQ4_P3 0x04e08d20 /* Tx Q4 Packet Counter */
-#define BCHP_SWITCH_CORE_TxQPKTQ5_P3 0x04e08d30 /* Tx Q5 Packet Counter */
-#define BCHP_SWITCH_CORE_RxOctets_P3 0x04e08d40 /* Rx Packet Octets Counter */
-#define BCHP_SWITCH_CORE_RxUndersizePkts_P3 0x04e08d60 /* Rx Under Size Packet Octets Counter */
-#define BCHP_SWITCH_CORE_RxPausePkts_P3 0x04e08d70 /* Rx Pause Packet Counter */
-#define BCHP_SWITCH_CORE_RxPkts64Octets_P3 0x04e08d80 /* Rx 64 Bytes Octets Counter */
-#define BCHP_SWITCH_CORE_RxPkts65to127Octets_P3 0x04e08d90 /* Rx 65 to 127 Bytes Octets Counter */
-#define BCHP_SWITCH_CORE_RxPkts128to255Octets_P3 0x04e08da0 /* Rx 128 to 255 Bytes Octets Counter */
-#define BCHP_SWITCH_CORE_RxPkts256to511Octets_P3 0x04e08db0 /* Rx 256 to 511 Bytes Octets Counter */
-#define BCHP_SWITCH_CORE_RxPkts512to1023Octets_P3 0x04e08dc0 /* Rx 512 to 1023 Bytes Octets Counter */
-#define BCHP_SWITCH_CORE_RxPkts1024toMaxPktOctets_P3 0x04e08dd0 /* Rx 1024 to MaxPkt Bytes Octets Counter */
-#define BCHP_SWITCH_CORE_RxOversizePkts_P3 0x04e08de0 /* Rx Over Size Packet Counter */
-#define BCHP_SWITCH_CORE_RxJabbers_P3 0x04e08df0 /* Rx Jabber Packet Counter */
-#define BCHP_SWITCH_CORE_RxAlignmentErrors_P3 0x04e08e00 /* Rx Alignment Error Counter */
-#define BCHP_SWITCH_CORE_RxFCSErrors_P3 0x04e08e10 /* Rx FCS Error Counter */
-#define BCHP_SWITCH_CORE_RxGoodOctets_P3 0x04e08e20 /* Rx Good Packet Octet Counter */
-#define BCHP_SWITCH_CORE_RxDropPkts_P3 0x04e08e40 /* Rx Drop Packet Counter */
-#define BCHP_SWITCH_CORE_RxUnicastPkts_P3 0x04e08e50 /* Rx Unicast Packet Counter */
-#define BCHP_SWITCH_CORE_RxMulticastPkts_P3 0x04e08e60 /* Rx Multicast Packet Counter */
-#define BCHP_SWITCH_CORE_RxBroadcastPkts_P3 0x04e08e70 /* Rx Broadcast Packet Counter */
-#define BCHP_SWITCH_CORE_RxSAChanges_P3 0x04e08e80 /* Rx SA Change Counter */
-#define BCHP_SWITCH_CORE_RxFragments_P3 0x04e08e90 /* Rx Fragment Counter */
-#define BCHP_SWITCH_CORE_RxJumboPkt_P3 0x04e08ea0 /* Jumbo Packet Counter */
-#define BCHP_SWITCH_CORE_RxSymblErr_P3 0x04e08eb0 /* Rx Symbol Error Counter */
-#define BCHP_SWITCH_CORE_InRangeErrCount_P3 0x04e08ec0 /* InRangeErrCount Counter */
-#define BCHP_SWITCH_CORE_OutRangeErrCount_P3 0x04e08ed0 /* OutRangeErrCount Counter */
-#define BCHP_SWITCH_CORE_EEE_LPI_EVENT_P3 0x04e08ee0 /* EEE Low-Power Idle Event Registers */
-#define BCHP_SWITCH_CORE_EEE_LPI_DURATION_P3 0x04e08ef0 /* EEE Low-Power Idle Duration Registers */
-#define BCHP_SWITCH_CORE_RxDiscard_P3 0x04e08f00 /* Rx Discard Counter */
-#define BCHP_SWITCH_CORE_TxQPKTQ6_P3 0x04e08f20 /* Tx Q6 Packet Counter */
-#define BCHP_SWITCH_CORE_TxQPKTQ7_P3 0x04e08f30 /* Tx Q7 Packet Counter */
-#define BCHP_SWITCH_CORE_TxPkts64Octets_P3 0x04e08f40 /* Tx 64 Bytes Octets Counter */
-#define BCHP_SWITCH_CORE_TxPkts65to127Octets_P3 0x04e08f50 /* Tx 65 to 127 Bytes Octets Counter */
-#define BCHP_SWITCH_CORE_TxPkts128to255Octets_P3 0x04e08f60 /* Tx 128 to 255 Bytes Octets Counter */
-#define BCHP_SWITCH_CORE_TxPkts256to511Octets_P3 0x04e08f70 /* Tx 256 to 511 Bytes Octets Counter */
-#define BCHP_SWITCH_CORE_TxPkts512to1023Octets_P3 0x04e08f80 /* Tx 512 to 1023 Bytes Octets Counter */
-#define BCHP_SWITCH_CORE_TxPkts1024toMaxPktOctets_P3 0x04e08f90 /* Tx 1024 to MaxPkt Bytes Octets Counter */
-#define BCHP_SWITCH_CORE_TxOctets_P4 0x04e09000 /* Tx Octets */
-#define BCHP_SWITCH_CORE_TxDropPkts_P4 0x04e09020 /* Tx Drop Packet Counter */
-#define BCHP_SWITCH_CORE_TxQPKTQ0_P4 0x04e09030 /* Tx Q0 Packet Counter */
-#define BCHP_SWITCH_CORE_TxBroadcastPkts_P4 0x04e09040 /* Tx Broadcast Packet Counter */
-#define BCHP_SWITCH_CORE_TxMulticastPkts_P4 0x04e09050 /* Tx Multicast Packet Counter */
-#define BCHP_SWITCH_CORE_TxUnicastPkts_P4 0x04e09060 /* Tx Unicast Packet Counter */
-#define BCHP_SWITCH_CORE_TxCollisions_P4 0x04e09070 /* Tx Collision Counter */
-#define BCHP_SWITCH_CORE_TxSingleCollision_P4 0x04e09080 /* Tx Single Collision Counter */
-#define BCHP_SWITCH_CORE_TxMultipleCollision_P4 0x04e09090 /* Tx Multiple collsion Counter */
-#define BCHP_SWITCH_CORE_TxDeferredTransmit_P4 0x04e090a0 /* Tx Deferred Transmit Counter */
-#define BCHP_SWITCH_CORE_TxLateCollision_P4 0x04e090b0 /* Tx Late Collision Counter */
-#define BCHP_SWITCH_CORE_TxExcessiveCollision_P4 0x04e090c0 /* Tx Excessive Collision Counter */
-#define BCHP_SWITCH_CORE_TxFrameInDisc_P4 0x04e090d0 /* Tx Fram IN Disc Counter */
-#define BCHP_SWITCH_CORE_TxPausePkts_P4 0x04e090e0 /* Tx Pause Packet Counter */
-#define BCHP_SWITCH_CORE_TxQPKTQ1_P4 0x04e090f0 /* Tx Q1 Packet Counter */
-#define BCHP_SWITCH_CORE_TxQPKTQ2_P4 0x04e09100 /* Tx Q2 Packet Counter */
-#define BCHP_SWITCH_CORE_TxQPKTQ3_P4 0x04e09110 /* Tx Q3 Packet Counter */
-#define BCHP_SWITCH_CORE_TxQPKTQ4_P4 0x04e09120 /* Tx Q4 Packet Counter */
-#define BCHP_SWITCH_CORE_TxQPKTQ5_P4 0x04e09130 /* Tx Q5 Packet Counter */
-#define BCHP_SWITCH_CORE_RxOctets_P4 0x04e09140 /* Rx Packet Octets Counter */
-#define BCHP_SWITCH_CORE_RxUndersizePkts_P4 0x04e09160 /* Rx Under Size Packet Octets Counter */
-#define BCHP_SWITCH_CORE_RxPausePkts_P4 0x04e09170 /* Rx Pause Packet Counter */
-#define BCHP_SWITCH_CORE_RxPkts64Octets_P4 0x04e09180 /* Rx 64 Bytes Octets Counter */
-#define BCHP_SWITCH_CORE_RxPkts65to127Octets_P4 0x04e09190 /* Rx 65 to 127 Bytes Octets Counter */
-#define BCHP_SWITCH_CORE_RxPkts128to255Octets_P4 0x04e091a0 /* Rx 128 to 255 Bytes Octets Counter */
-#define BCHP_SWITCH_CORE_RxPkts256to511Octets_P4 0x04e091b0 /* Rx 256 to 511 Bytes Octets Counter */
-#define BCHP_SWITCH_CORE_RxPkts512to1023Octets_P4 0x04e091c0 /* Rx 512 to 1023 Bytes Octets Counter */
-#define BCHP_SWITCH_CORE_RxPkts1024toMaxPktOctets_P4 0x04e091d0 /* Rx 1024 to MaxPkt Bytes Octets Counter */
-#define BCHP_SWITCH_CORE_RxOversizePkts_P4 0x04e091e0 /* Rx Over Size Packet Counter */
-#define BCHP_SWITCH_CORE_RxJabbers_P4 0x04e091f0 /* Rx Jabber Packet Counter */
-#define BCHP_SWITCH_CORE_RxAlignmentErrors_P4 0x04e09200 /* Rx Alignment Error Counter */
-#define BCHP_SWITCH_CORE_RxFCSErrors_P4 0x04e09210 /* Rx FCS Error Counter */
-#define BCHP_SWITCH_CORE_RxGoodOctets_P4 0x04e09220 /* Rx Good Packet Octet Counter */
-#define BCHP_SWITCH_CORE_RxDropPkts_P4 0x04e09240 /* Rx Drop Packet Counter */
-#define BCHP_SWITCH_CORE_RxUnicastPkts_P4 0x04e09250 /* Rx Unicast Packet Counter */
-#define BCHP_SWITCH_CORE_RxMulticastPkts_P4 0x04e09260 /* Rx Multicast Packet Counter */
-#define BCHP_SWITCH_CORE_RxBroadcastPkts_P4 0x04e09270 /* Rx Broadcast Packet Counter */
-#define BCHP_SWITCH_CORE_RxSAChanges_P4 0x04e09280 /* Rx SA Change Counter */
-#define BCHP_SWITCH_CORE_RxFragments_P4 0x04e09290 /* Rx Fragment Counter */
-#define BCHP_SWITCH_CORE_RxJumboPkt_P4 0x04e092a0 /* Jumbo Packet Counter */
-#define BCHP_SWITCH_CORE_RxSymblErr_P4 0x04e092b0 /* Rx Symbol Error Counter */
-#define BCHP_SWITCH_CORE_InRangeErrCount_P4 0x04e092c0 /* InRangeErrCount Counter */
-#define BCHP_SWITCH_CORE_OutRangeErrCount_P4 0x04e092d0 /* OutRangeErrCount Counter */
-#define BCHP_SWITCH_CORE_EEE_LPI_EVENT_P4 0x04e092e0 /* EEE Low-Power Idle Event Registers */
-#define BCHP_SWITCH_CORE_EEE_LPI_DURATION_P4 0x04e092f0 /* EEE Low-Power Idle Duration Registers */
-#define BCHP_SWITCH_CORE_RxDiscard_P4 0x04e09300 /* Rx Discard Counter */
-#define BCHP_SWITCH_CORE_TxQPKTQ6_P4 0x04e09320 /* Tx Q6 Packet Counter */
-#define BCHP_SWITCH_CORE_TxQPKTQ7_P4 0x04e09330 /* Tx Q7 Packet Counter */
-#define BCHP_SWITCH_CORE_TxPkts64Octets_P4 0x04e09340 /* Tx 64 Bytes Octets Counter */
-#define BCHP_SWITCH_CORE_TxPkts65to127Octets_P4 0x04e09350 /* Tx 65 to 127 Bytes Octets Counter */
-#define BCHP_SWITCH_CORE_TxPkts128to255Octets_P4 0x04e09360 /* Tx 128 to 255 Bytes Octets Counter */
-#define BCHP_SWITCH_CORE_TxPkts256to511Octets_P4 0x04e09370 /* Tx 256 to 511 Bytes Octets Counter */
-#define BCHP_SWITCH_CORE_TxPkts512to1023Octets_P4 0x04e09380 /* Tx 512 to 1023 Bytes Octets Counter */
-#define BCHP_SWITCH_CORE_TxPkts1024toMaxPktOctets_P4 0x04e09390 /* Tx 1024 to MaxPkt Bytes Octets Counter */
-#define BCHP_SWITCH_CORE_TxOctets_P5 0x04e09400 /* Tx Octets */
-#define BCHP_SWITCH_CORE_TxDropPkts_P5 0x04e09420 /* Tx Drop Packet Counter */
-#define BCHP_SWITCH_CORE_TxQPKTQ0_P5 0x04e09430 /* Tx Q0 Packet Counter */
-#define BCHP_SWITCH_CORE_TxBroadcastPkts_P5 0x04e09440 /* Tx Broadcast Packet Counter */
-#define BCHP_SWITCH_CORE_TxMulticastPkts_P5 0x04e09450 /* Tx Multicast Packet Counter */
-#define BCHP_SWITCH_CORE_TxUnicastPkts_P5 0x04e09460 /* Tx Unicast Packet Counter */
-#define BCHP_SWITCH_CORE_TxCollisions_P5 0x04e09470 /* Tx Collision Counter */
-#define BCHP_SWITCH_CORE_TxSingleCollision_P5 0x04e09480 /* Tx Single Collision Counter */
-#define BCHP_SWITCH_CORE_TxMultipleCollision_P5 0x04e09490 /* Tx Multiple collsion Counter */
-#define BCHP_SWITCH_CORE_TxDeferredTransmit_P5 0x04e094a0 /* Tx Deferred Transmit Counter */
-#define BCHP_SWITCH_CORE_TxLateCollision_P5 0x04e094b0 /* Tx Late Collision Counter */
-#define BCHP_SWITCH_CORE_TxExcessiveCollision_P5 0x04e094c0 /* Tx Excessive Collision Counter */
-#define BCHP_SWITCH_CORE_TxFrameInDisc_P5 0x04e094d0 /* Tx Fram IN Disc Counter */
-#define BCHP_SWITCH_CORE_TxPausePkts_P5 0x04e094e0 /* Tx Pause Packet Counter */
-#define BCHP_SWITCH_CORE_TxQPKTQ1_P5 0x04e094f0 /* Tx Q1 Packet Counter */
-#define BCHP_SWITCH_CORE_TxQPKTQ2_P5 0x04e09500 /* Tx Q2 Packet Counter */
-#define BCHP_SWITCH_CORE_TxQPKTQ3_P5 0x04e09510 /* Tx Q3 Packet Counter */
-#define BCHP_SWITCH_CORE_TxQPKTQ4_P5 0x04e09520 /* Tx Q4 Packet Counter */
-#define BCHP_SWITCH_CORE_TxQPKTQ5_P5 0x04e09530 /* Tx Q5 Packet Counter */
-#define BCHP_SWITCH_CORE_RxOctets_P5 0x04e09540 /* Rx Packet Octets Counter */
-#define BCHP_SWITCH_CORE_RxUndersizePkts_P5 0x04e09560 /* Rx Under Size Packet Octets Counter */
-#define BCHP_SWITCH_CORE_RxPausePkts_P5 0x04e09570 /* Rx Pause Packet Counter */
-#define BCHP_SWITCH_CORE_RxPkts64Octets_P5 0x04e09580 /* Rx 64 Bytes Octets Counter */
-#define BCHP_SWITCH_CORE_RxPkts65to127Octets_P5 0x04e09590 /* Rx 65 to 127 Bytes Octets Counter */
-#define BCHP_SWITCH_CORE_RxPkts128to255Octets_P5 0x04e095a0 /* Rx 128 to 255 Bytes Octets Counter */
-#define BCHP_SWITCH_CORE_RxPkts256to511Octets_P5 0x04e095b0 /* Rx 256 to 511 Bytes Octets Counter */
-#define BCHP_SWITCH_CORE_RxPkts512to1023Octets_P5 0x04e095c0 /* Rx 512 to 1023 Bytes Octets Counter */
-#define BCHP_SWITCH_CORE_RxPkts1024toMaxPktOctets_P5 0x04e095d0 /* Rx 1024 to MaxPkt Bytes Octets Counter */
-#define BCHP_SWITCH_CORE_RxOversizePkts_P5 0x04e095e0 /* Rx Over Size Packet Counter */
-#define BCHP_SWITCH_CORE_RxJabbers_P5 0x04e095f0 /* Rx Jabber Packet Counter */
-#define BCHP_SWITCH_CORE_RxAlignmentErrors_P5 0x04e09600 /* Rx Alignment Error Counter */
-#define BCHP_SWITCH_CORE_RxFCSErrors_P5 0x04e09610 /* Rx FCS Error Counter */
-#define BCHP_SWITCH_CORE_RxGoodOctets_P5 0x04e09620 /* Rx Good Packet Octet Counter */
-#define BCHP_SWITCH_CORE_RxDropPkts_P5 0x04e09640 /* Rx Drop Packet Counter */
-#define BCHP_SWITCH_CORE_RxUnicastPkts_P5 0x04e09650 /* Rx Unicast Packet Counter */
-#define BCHP_SWITCH_CORE_RxMulticastPkts_P5 0x04e09660 /* Rx Multicast Packet Counter */
-#define BCHP_SWITCH_CORE_RxBroadcastPkts_P5 0x04e09670 /* Rx Broadcast Packet Counter */
-#define BCHP_SWITCH_CORE_RxSAChanges_P5 0x04e09680 /* Rx SA Change Counter */
-#define BCHP_SWITCH_CORE_RxFragments_P5 0x04e09690 /* Rx Fragment Counter */
-#define BCHP_SWITCH_CORE_RxJumboPkt_P5 0x04e096a0 /* Jumbo Packet Counter */
-#define BCHP_SWITCH_CORE_RxSymblErr_P5 0x04e096b0 /* Rx Symbol Error Counter */
-#define BCHP_SWITCH_CORE_InRangeErrCount_P5 0x04e096c0 /* InRangeErrCount Counter */
-#define BCHP_SWITCH_CORE_OutRangeErrCount_P5 0x04e096d0 /* OutRangeErrCount Counter */
-#define BCHP_SWITCH_CORE_EEE_LPI_EVENT_P5 0x04e096e0 /* EEE Low-Power Idle Event Registers */
-#define BCHP_SWITCH_CORE_EEE_LPI_DURATION_P5 0x04e096f0 /* EEE Low-Power Idle Duration Registers */
-#define BCHP_SWITCH_CORE_RxDiscard_P5 0x04e09700 /* Rx Discard Counter */
-#define BCHP_SWITCH_CORE_TxQPKTQ6_P5 0x04e09720 /* Tx Q6 Packet Counter */
-#define BCHP_SWITCH_CORE_TxQPKTQ7_P5 0x04e09730 /* Tx Q7 Packet Counter */
-#define BCHP_SWITCH_CORE_TxPkts64Octets_P5 0x04e09740 /* Tx 64 Bytes Octets Counter */
-#define BCHP_SWITCH_CORE_TxPkts65to127Octets_P5 0x04e09750 /* Tx 65 to 127 Bytes Octets Counter */
-#define BCHP_SWITCH_CORE_TxPkts128to255Octets_P5 0x04e09760 /* Tx 128 to 255 Bytes Octets Counter */
-#define BCHP_SWITCH_CORE_TxPkts256to511Octets_P5 0x04e09770 /* Tx 256 to 511 Bytes Octets Counter */
-#define BCHP_SWITCH_CORE_TxPkts512to1023Octets_P5 0x04e09780 /* Tx 512 to 1023 Bytes Octets Counter */
-#define BCHP_SWITCH_CORE_TxPkts1024toMaxPktOctets_P5 0x04e09790 /* Tx 1024 to MaxPkt Bytes Octets Counter */
-#define BCHP_SWITCH_CORE_TxOctets_P7 0x04e09c00 /* Tx Octets */
-#define BCHP_SWITCH_CORE_TxDropPkts_P7 0x04e09c20 /* Tx Drop Packet Counter */
-#define BCHP_SWITCH_CORE_TxQPKTQ0_P7 0x04e09c30 /* Tx Q0 Packet Counter */
-#define BCHP_SWITCH_CORE_TxBroadcastPkts_P7 0x04e09c40 /* Tx Broadcast Packet Counter */
-#define BCHP_SWITCH_CORE_TxMulticastPkts_P7 0x04e09c50 /* Tx Multicast Packet Counter */
-#define BCHP_SWITCH_CORE_TxUnicastPkts_P7 0x04e09c60 /* Tx Unicast Packet Counter */
-#define BCHP_SWITCH_CORE_TxCollisions_P7 0x04e09c70 /* Tx Collision Counter */
-#define BCHP_SWITCH_CORE_TxSingleCollision_P7 0x04e09c80 /* Tx Single Collision Counter */
-#define BCHP_SWITCH_CORE_TxMultipleCollision_P7 0x04e09c90 /* Tx Multiple collsion Counter */
-#define BCHP_SWITCH_CORE_TxDeferredTransmit_P7 0x04e09ca0 /* Tx Deferred Transmit Counter */
-#define BCHP_SWITCH_CORE_TxLateCollision_P7 0x04e09cb0 /* Tx Late Collision Counter */
-#define BCHP_SWITCH_CORE_TxExcessiveCollision_P7 0x04e09cc0 /* Tx Excessive Collision Counter */
-#define BCHP_SWITCH_CORE_TxFrameInDisc_P7 0x04e09cd0 /* Tx Fram IN Disc Counter */
-#define BCHP_SWITCH_CORE_TxPausePkts_P7 0x04e09ce0 /* Tx Pause Packet Counter */
-#define BCHP_SWITCH_CORE_TxQPKTQ1_P7 0x04e09cf0 /* Tx Q1 Packet Counter */
-#define BCHP_SWITCH_CORE_TxQPKTQ2_P7 0x04e09d00 /* Tx Q2 Packet Counter */
-#define BCHP_SWITCH_CORE_TxQPKTQ3_P7 0x04e09d10 /* Tx Q3 Packet Counter */
-#define BCHP_SWITCH_CORE_TxQPKTQ4_P7 0x04e09d20 /* Tx Q4 Packet Counter */
-#define BCHP_SWITCH_CORE_TxQPKTQ5_P7 0x04e09d30 /* Tx Q5 Packet Counter */
-#define BCHP_SWITCH_CORE_RxOctets_P7 0x04e09d40 /* Rx Packet Octets Counter */
-#define BCHP_SWITCH_CORE_RxUndersizePkts_P7 0x04e09d60 /* Rx Under Size Packet Octets Counter */
-#define BCHP_SWITCH_CORE_RxPausePkts_P7 0x04e09d70 /* Rx Pause Packet Counter */
-#define BCHP_SWITCH_CORE_RxPkts64Octets_P7 0x04e09d80 /* Rx 64 Bytes Octets Counter */
-#define BCHP_SWITCH_CORE_RxPkts65to127Octets_P7 0x04e09d90 /* Rx 65 to 127 Bytes Octets Counter */
-#define BCHP_SWITCH_CORE_RxPkts128to255Octets_P7 0x04e09da0 /* Rx 128 to 255 Bytes Octets Counter */
-#define BCHP_SWITCH_CORE_RxPkts256to511Octets_P7 0x04e09db0 /* Rx 256 to 511 Bytes Octets Counter */
-#define BCHP_SWITCH_CORE_RxPkts512to1023Octets_P7 0x04e09dc0 /* Rx 512 to 1023 Bytes Octets Counter */
-#define BCHP_SWITCH_CORE_RxPkts1024toMaxPktOctets_P7 0x04e09dd0 /* Rx 1024 to MaxPkt Bytes Octets Counter */
-#define BCHP_SWITCH_CORE_RxOversizePkts_P7 0x04e09de0 /* Rx Over Size Packet Counter */
-#define BCHP_SWITCH_CORE_RxJabbers_P7 0x04e09df0 /* Rx Jabber Packet Counter */
-#define BCHP_SWITCH_CORE_RxAlignmentErrors_P7 0x04e09e00 /* Rx Alignment Error Counter */
-#define BCHP_SWITCH_CORE_RxFCSErrors_P7 0x04e09e10 /* Rx FCS Error Counter */
-#define BCHP_SWITCH_CORE_RxGoodOctets_P7 0x04e09e20 /* Rx Good Packet Octet Counter */
-#define BCHP_SWITCH_CORE_RxDropPkts_P7 0x04e09e40 /* Rx Drop Packet Counter */
-#define BCHP_SWITCH_CORE_RxUnicastPkts_P7 0x04e09e50 /* Rx Unicast Packet Counter */
-#define BCHP_SWITCH_CORE_RxMulticastPkts_P7 0x04e09e60 /* Rx Multicast Packet Counter */
-#define BCHP_SWITCH_CORE_RxBroadcastPkts_P7 0x04e09e70 /* Rx Broadcast Packet Counter */
-#define BCHP_SWITCH_CORE_RxSAChanges_P7 0x04e09e80 /* Rx SA Change Counter */
-#define BCHP_SWITCH_CORE_RxFragments_P7 0x04e09e90 /* Rx Fragment Counter */
-#define BCHP_SWITCH_CORE_RxJumboPkt_P7 0x04e09ea0 /* Jumbo Packet Counter */
-#define BCHP_SWITCH_CORE_RxSymblErr_P7 0x04e09eb0 /* Rx Symbol Error Counter */
-#define BCHP_SWITCH_CORE_InRangeErrCount_P7 0x04e09ec0 /* InRangeErrCount Counter */
-#define BCHP_SWITCH_CORE_OutRangeErrCount_P7 0x04e09ed0 /* OutRangeErrCount Counter */
-#define BCHP_SWITCH_CORE_EEE_LPI_EVENT_P7 0x04e09ee0 /* EEE Low-Power Idle Event Registers */
-#define BCHP_SWITCH_CORE_EEE_LPI_DURATION_P7 0x04e09ef0 /* EEE Low-Power Idle Duration Registers */
-#define BCHP_SWITCH_CORE_RxDiscard_P7 0x04e09f00 /* Rx Discard Counter */
-#define BCHP_SWITCH_CORE_TxQPKTQ6_P7 0x04e09f20 /* Tx Q6 Packet Counter */
-#define BCHP_SWITCH_CORE_TxQPKTQ7_P7 0x04e09f30 /* Tx Q7 Packet Counter */
-#define BCHP_SWITCH_CORE_TxPkts64Octets_P7 0x04e09f40 /* Tx 64 Bytes Octets Counter */
-#define BCHP_SWITCH_CORE_TxPkts65to127Octets_P7 0x04e09f50 /* Tx 65 to 127 Bytes Octets Counter */
-#define BCHP_SWITCH_CORE_TxPkts128to255Octets_P7 0x04e09f60 /* Tx 128 to 255 Bytes Octets Counter */
-#define BCHP_SWITCH_CORE_TxPkts256to511Octets_P7 0x04e09f70 /* Tx 256 to 511 Bytes Octets Counter */
-#define BCHP_SWITCH_CORE_TxPkts512to1023Octets_P7 0x04e09f80 /* Tx 512 to 1023 Bytes Octets Counter */
-#define BCHP_SWITCH_CORE_TxPkts1024toMaxPktOctets_P7 0x04e09f90 /* Tx 1024 to MaxPkt Bytes Octets Counter */
-#define BCHP_SWITCH_CORE_TxOctets_IMP 0x04e0a000 /* Tx Octets */
-#define BCHP_SWITCH_CORE_TxDropPkts_IMP 0x04e0a020 /* Tx Drop Packet Counter */
-#define BCHP_SWITCH_CORE_TxQPKTQ0_IMP 0x04e0a030 /* Tx Q0 Packet Counter */
-#define BCHP_SWITCH_CORE_TxBroadcastPkts_IMP 0x04e0a040 /* Tx Broadcast Packet Counter */
-#define BCHP_SWITCH_CORE_TxMulticastPkts_IMP 0x04e0a050 /* Tx Multicast Packet Counter */
-#define BCHP_SWITCH_CORE_TxUnicastPkts_IMP 0x04e0a060 /* Tx Unicast Packet Counter */
-#define BCHP_SWITCH_CORE_TxCollisions_IMP 0x04e0a070 /* Tx Collision Counter */
-#define BCHP_SWITCH_CORE_TxSingleCollision_IMP 0x04e0a080 /* Tx Single Collision Counter */
-#define BCHP_SWITCH_CORE_TxMultipleCollision_IMP 0x04e0a090 /* Tx Multiple collsion Counter */
-#define BCHP_SWITCH_CORE_TxDeferredTransmit_IMP 0x04e0a0a0 /* Tx Deferred Transmit Counter */
-#define BCHP_SWITCH_CORE_TxLateCollision_IMP 0x04e0a0b0 /* Tx Late Collision Counter */
-#define BCHP_SWITCH_CORE_TxExcessiveCollision_IMP 0x04e0a0c0 /* Tx Excessive Collision Counter */
-#define BCHP_SWITCH_CORE_TxFrameInDisc_IMP 0x04e0a0d0 /* Tx Fram IN Disc Counter */
-#define BCHP_SWITCH_CORE_TxPausePkts_IMP 0x04e0a0e0 /* Tx Pause Packet Counter */
-#define BCHP_SWITCH_CORE_TxQPKTQ1_IMP 0x04e0a0f0 /* Tx Q1 Packet Counter */
-#define BCHP_SWITCH_CORE_TxQPKTQ2_IMP 0x04e0a100 /* Tx Q2 Packet Counter */
-#define BCHP_SWITCH_CORE_TxQPKTQ3_IMP 0x04e0a110 /* Tx Q3 Packet Counter */
-#define BCHP_SWITCH_CORE_TxQPKTQ4_IMP 0x04e0a120 /* Tx Q4 Packet Counter */
-#define BCHP_SWITCH_CORE_TxQPKTQ5_IMP 0x04e0a130 /* Tx Q5 Packet Counter */
-#define BCHP_SWITCH_CORE_RxOctets_IMP 0x04e0a140 /* Rx Packet Octets Counter */
-#define BCHP_SWITCH_CORE_RxUndersizePkts_IMP 0x04e0a160 /* Rx Under Size Packet Octets Counter */
-#define BCHP_SWITCH_CORE_RxPausePkts_IMP 0x04e0a170 /* Rx Pause Packet Counter */
-#define BCHP_SWITCH_CORE_RxPkts64Octets_IMP 0x04e0a180 /* Rx 64 Bytes Octets Counter */
-#define BCHP_SWITCH_CORE_RxPkts65to127Octets_IMP 0x04e0a190 /* Rx 65 to 127 Bytes Octets Counter */
-#define BCHP_SWITCH_CORE_RxPkts128to255Octets_IMP 0x04e0a1a0 /* Rx 128 to 255 Bytes Octets Counter */
-#define BCHP_SWITCH_CORE_RxPkts256to511Octets_IMP 0x04e0a1b0 /* Rx 256 to 511 Bytes Octets Counter */
-#define BCHP_SWITCH_CORE_RxPkts512to1023Octets_IMP 0x04e0a1c0 /* Rx 512 to 1023 Bytes Octets Counter */
-#define BCHP_SWITCH_CORE_RxPkts1024toMaxPktOctets_IMP 0x04e0a1d0 /* Rx 1024 to MaxPkt Bytes Octets Counter */
-#define BCHP_SWITCH_CORE_RxOversizePkts_IMP 0x04e0a1e0 /* Rx Over Size Packet Counter */
-#define BCHP_SWITCH_CORE_RxJabbers_IMP 0x04e0a1f0 /* Rx Jabber Packet Counter */
-#define BCHP_SWITCH_CORE_RxAlignmentErrors_IMP 0x04e0a200 /* Rx Alignment Error Counter */
-#define BCHP_SWITCH_CORE_RxFCSErrors_IMP 0x04e0a210 /* Rx FCS Error Counter */
-#define BCHP_SWITCH_CORE_RxGoodOctets_IMP 0x04e0a220 /* Rx Good Packet Octet Counter */
-#define BCHP_SWITCH_CORE_RxDropPkts_IMP 0x04e0a240 /* Rx Drop Packet Counter */
-#define BCHP_SWITCH_CORE_RxUnicastPkts_IMP 0x04e0a250 /* Rx Unicast Packet Counter */
-#define BCHP_SWITCH_CORE_RxMulticastPkts_IMP 0x04e0a260 /* Rx Multicast Packet Counter */
-#define BCHP_SWITCH_CORE_RxBroadcastPkts_IMP 0x04e0a270 /* Rx Broadcast Packet Counter */
-#define BCHP_SWITCH_CORE_RxSAChanges_IMP 0x04e0a280 /* Rx SA Change Counter */
-#define BCHP_SWITCH_CORE_RxFragments_IMP 0x04e0a290 /* Rx Fragment Counter */
-#define BCHP_SWITCH_CORE_RxJumboPkt_IMP 0x04e0a2a0 /* Jumbo Packet Counter */
-#define BCHP_SWITCH_CORE_RxSymblErr_IMP 0x04e0a2b0 /* Rx Symbol Error Counter */
-#define BCHP_SWITCH_CORE_InRangeErrCount_IMP 0x04e0a2c0 /* InRangeErrCount Counter */
-#define BCHP_SWITCH_CORE_OutRangeErrCount_IMP 0x04e0a2d0 /* OutRangeErrCount Counter */
-#define BCHP_SWITCH_CORE_EEE_LPI_EVENT_IMP 0x04e0a2e0 /* EEE Low-Power Idle Event Registers */
-#define BCHP_SWITCH_CORE_EEE_LPI_DURATION_IMP 0x04e0a2f0 /* EEE Low-Power Idle Duration Registers */
-#define BCHP_SWITCH_CORE_RxDiscard_IMP 0x04e0a300 /* Rx Discard Counter */
-#define BCHP_SWITCH_CORE_TxQPKTQ6_IMP 0x04e0a320 /* Tx Q6 Packet Counter */
-#define BCHP_SWITCH_CORE_TxQPKTQ7_IMP 0x04e0a330 /* Tx Q7 Packet Counter */
-#define BCHP_SWITCH_CORE_TxPkts64Octets_IMP 0x04e0a340 /* Tx 64 Bytes Octets Counter */
-#define BCHP_SWITCH_CORE_TxPkts65to127Octets_IMP 0x04e0a350 /* Tx 65 to 127 Bytes Octets Counter */
-#define BCHP_SWITCH_CORE_TxPkts128to255Octets_IMP 0x04e0a360 /* Tx 128 to 255 Bytes Octets Counter */
-#define BCHP_SWITCH_CORE_TxPkts256to511Octets_IMP 0x04e0a370 /* Tx 256 to 511 Bytes Octets Counter */
-#define BCHP_SWITCH_CORE_TxPkts512to1023Octets_IMP 0x04e0a380 /* Tx 512 to 1023 Bytes Octets Counter */
-#define BCHP_SWITCH_CORE_TxPkts1024toMaxPktOctets_IMP 0x04e0a390 /* Tx 1024 to MaxPkt Bytes Octets Counter */
-#define BCHP_SWITCH_CORE_QOS_GLOBAL_CTRL 0x04e0c000 /* QOS Global Control Register */
-#define BCHP_SWITCH_CORE_QOS_1P_EN 0x04e0c010 /* QoS 802.1P Enable Register */
-#define BCHP_SWITCH_CORE_QOS_EN_DIFFSERV 0x04e0c018 /* QOS DiffServ Enable Register */
-#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI0_Port_0 0x04e0c040 /* Port N PCP to TC Map for DEI 0 Register */
-#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI0_Port_1 0x04e0c050 /* Port N PCP to TC Map for DEI 0 Register */
-#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI0_Port_2 0x04e0c060 /* Port N PCP to TC Map for DEI 0 Register */
-#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI0_Port_3 0x04e0c070 /* Port N PCP to TC Map for DEI 0 Register */
-#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI0_Port_4 0x04e0c080 /* Port N PCP to TC Map for DEI 0 Register */
-#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI0_Port_5 0x04e0c090 /* Port N PCP to TC Map for DEI 0 Register */
-#define BCHP_SWITCH_CORE_P7_PCP2TC_DEI0 0x04e0c0a0 /* Port 7 PCP to TC Map for DEI 0 Register */
-#define BCHP_SWITCH_CORE_IMP_PCP2TC_DEI0 0x04e0c0b0 /* Port 8 (IMP) PCP to TC Map for DEI 0 Register */
-#define BCHP_SWITCH_CORE_QOS_DIFF_DSCP0 0x04e0c0c0 /* DiffServ Priority Map 0 Register */
-#define BCHP_SWITCH_CORE_QOS_DIFF_DSCP1 0x04e0c0d8 /* DiffServ Priority Map 1 Register */
-#define BCHP_SWITCH_CORE_QOS_DIFF_DSCP2 0x04e0c0f0 /* DiffServ Priority Map 2 Register */
-#define BCHP_SWITCH_CORE_QOS_DIFF_DSCP3 0x04e0c108 /* DiffServ Priority Map 3 Register */
-#define BCHP_SWITCH_CORE_PID2TC 0x04e0c120 /* Port ID to TC Map Register */
-#define BCHP_SWITCH_CORE_TC_SEL_TABLE_Port_0 0x04e0c140 /* Port N TC Select Table Register */
-#define BCHP_SWITCH_CORE_TC_SEL_TABLE_Port_1 0x04e0c148 /* Port N TC Select Table Register */
-#define BCHP_SWITCH_CORE_TC_SEL_TABLE_Port_2 0x04e0c150 /* Port N TC Select Table Register */
-#define BCHP_SWITCH_CORE_TC_SEL_TABLE_Port_3 0x04e0c158 /* Port N TC Select Table Register */
-#define BCHP_SWITCH_CORE_TC_SEL_TABLE_Port_4 0x04e0c160 /* Port N TC Select Table Register */
-#define BCHP_SWITCH_CORE_TC_SEL_TABLE_Port_5 0x04e0c168 /* Port N TC Select Table Register */
-#define BCHP_SWITCH_CORE_P7_TC_SEL_TABLE 0x04e0c178 /* Port 7 TC Select Table Register */
-#define BCHP_SWITCH_CORE_IMP_TC_SEL_TABLE 0x04e0c180 /* Port 8 TC Select Table Register */
-#define BCHP_SWITCH_CORE_CPU2COS_MAP 0x04e0c190 /* CPU to COS Mapping Register */
-#define BCHP_SWITCH_CORE_PN_TC2COS_MAP_Port_0 0x04e0c1c0 /* Port N TC to COS Mapping Register */
-#define BCHP_SWITCH_CORE_PN_TC2COS_MAP_Port_1 0x04e0c1d0 /* Port N TC to COS Mapping Register */
-#define BCHP_SWITCH_CORE_PN_TC2COS_MAP_Port_2 0x04e0c1e0 /* Port N TC to COS Mapping Register */
-#define BCHP_SWITCH_CORE_PN_TC2COS_MAP_Port_3 0x04e0c1f0 /* Port N TC to COS Mapping Register */
-#define BCHP_SWITCH_CORE_PN_TC2COS_MAP_Port_4 0x04e0c200 /* Port N TC to COS Mapping Register */
-#define BCHP_SWITCH_CORE_PN_TC2COS_MAP_Port_5 0x04e0c210 /* Port N TC to COS Mapping Register */
-#define BCHP_SWITCH_CORE_P7_TC2COS_MAP 0x04e0c230 /* Port 7 TC to COS Mapping Register */
-#define BCHP_SWITCH_CORE_IMP_TC2COS_MAP 0x04e0c240 /* Port 8 TC to COS Mapping Register */
-#define BCHP_SWITCH_CORE_QOS_REG_SPARE0 0x04e0c2a0 /* Spare 0 Register (Not2Release) */
-#define BCHP_SWITCH_CORE_QOS_REG_SPARE1 0x04e0c2b0 /* Spare 1 Register (Not2Release) */
-#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI1_Port_0 0x04e0c2c0 /* Port N PCP to TC Map for DEI 1 Register */
-#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI1_Port_1 0x04e0c2d0 /* Port N PCP to TC Map for DEI 1 Register */
-#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI1_Port_2 0x04e0c2e0 /* Port N PCP to TC Map for DEI 1 Register */
-#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI1_Port_3 0x04e0c2f0 /* Port N PCP to TC Map for DEI 1 Register */
-#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI1_Port_4 0x04e0c300 /* Port N PCP to TC Map for DEI 1 Register */
-#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI1_Port_5 0x04e0c310 /* Port N PCP to TC Map for DEI 1 Register */
-#define BCHP_SWITCH_CORE_P7_PCP2TC_DEI1 0x04e0c320 /* Port 7 PCP to TC Map for DEI 1 Register */
-#define BCHP_SWITCH_CORE_IMP_PCP2TC_DEI1 0x04e0c330 /* Port 8 (IMP) PCP to TC Map for DEI 1 Register */
-#define BCHP_SWITCH_CORE_PORT_VLAN_CTL_Port_0 0x04e0c400 /* PORT N VLAN Control Register */
-#define BCHP_SWITCH_CORE_PORT_VLAN_CTL_Port_1 0x04e0c408 /* PORT N VLAN Control Register */
-#define BCHP_SWITCH_CORE_PORT_VLAN_CTL_Port_2 0x04e0c410 /* PORT N VLAN Control Register */
-#define BCHP_SWITCH_CORE_PORT_VLAN_CTL_Port_3 0x04e0c418 /* PORT N VLAN Control Register */
-#define BCHP_SWITCH_CORE_PORT_VLAN_CTL_Port_4 0x04e0c420 /* PORT N VLAN Control Register */
-#define BCHP_SWITCH_CORE_PORT_VLAN_CTL_Port_5 0x04e0c428 /* PORT N VLAN Control Register */
-#define BCHP_SWITCH_CORE_PORT_VLAN_CTL_P7 0x04e0c438 /* PORT 7 VLAN Control Register */
-#define BCHP_SWITCH_CORE_PORT_VLAN_CTL_IMP 0x04e0c440 /* PORT 8 VLAN Control Register */
-#define BCHP_SWITCH_CORE_VLAN_REG_SPARE0 0x04e0c480 /* Spare 0 Register (Not2Release) */
-#define BCHP_SWITCH_CORE_VLAN_REG_SPARE1 0x04e0c490 /* Spare 1 Register (Not2Release) */
-#define BCHP_SWITCH_CORE_MAC_TRUNK_CTL 0x04e0c800 /* MAC Trunk Control Register */
-#define BCHP_SWITCH_CORE_TRUNK_GRP_CTL_Port_0 0x04e0c840 /* Trunk N Group Control Register */
-#define BCHP_SWITCH_CORE_TRUNK_GRP_CTL_Port_1 0x04e0c848 /* Trunk N Group Control Register */
-#define BCHP_SWITCH_CORE_TRUNK_REG_SPARE0 0x04e0c880 /* Spare 0 Register (Not2Release) */
-#define BCHP_SWITCH_CORE_TRUNK_REG_SPARE1 0x04e0c890 /* Spare 1 Register (Not2Release) */
-#define BCHP_SWITCH_CORE_VLAN_CTRL0 0x04e0d000 /* 802.1Q VLAN Control 0 Registers */
-#define BCHP_SWITCH_CORE_VLAN_CTRL1 0x04e0d004 /* 802.1Q VLAN Control 1 Registers */
-#define BCHP_SWITCH_CORE_VLAN_CTRL2 0x04e0d008 /* 802.1Q VLAN Control 2 Registers */
-#define BCHP_SWITCH_CORE_VLAN_CTRL3 0x04e0d00c /* 802.1Q VLAN Control 3 Registers */
-#define BCHP_SWITCH_CORE_VLAN_CTRL4 0x04e0d014 /* 802.1Q VLAN Control 4 Registers */
-#define BCHP_SWITCH_CORE_VLAN_CTRL5 0x04e0d018 /* 802.1Q VLAN Control 5 Registers */
-#define BCHP_SWITCH_CORE_VLAN_CTRL6 0x04e0d01c /* 802.1Q VLAN Control 6 Registers */
-#define BCHP_SWITCH_CORE_VLAN_MULTI_PORT_ADDR_CTL 0x04e0d028 /* VLAN Multiport Address Control Register */
-#define BCHP_SWITCH_CORE_DEFAULT_1Q_TAG_Port_0 0x04e0d040 /* Port N 802.1Q Default Tag Registers */
-#define BCHP_SWITCH_CORE_DEFAULT_1Q_TAG_Port_1 0x04e0d048 /* Port N 802.1Q Default Tag Registers */
-#define BCHP_SWITCH_CORE_DEFAULT_1Q_TAG_Port_2 0x04e0d050 /* Port N 802.1Q Default Tag Registers */
-#define BCHP_SWITCH_CORE_DEFAULT_1Q_TAG_Port_3 0x04e0d058 /* Port N 802.1Q Default Tag Registers */
-#define BCHP_SWITCH_CORE_DEFAULT_1Q_TAG_Port_4 0x04e0d060 /* Port N 802.1Q Default Tag Registers */
-#define BCHP_SWITCH_CORE_DEFAULT_1Q_TAG_Port_5 0x04e0d068 /* Port N 802.1Q Default Tag Registers */
-#define BCHP_SWITCH_CORE_DEFAULT_1Q_TAG_P7 0x04e0d078 /* Port 7 802.1Q Default Tag Registers */
-#define BCHP_SWITCH_CORE_DEFAULT_1Q_TAG_IMP 0x04e0d080 /* Port 8 802.1Q Default Tag Registers */
-#define BCHP_SWITCH_CORE_DTAG_TPID 0x04e0d0c0 /* Double Tagging TPID Registers */
-#define BCHP_SWITCH_CORE_ISP_SEL_PORTMAP 0x04e0d0c8 /* ISP Port Selection Portmap Registers */
-#define BCHP_SWITCH_CORE_EGRESS_VID_RMK_TBL_ACS 0x04e0d100 /* Egress VID Remarking Table Access Register */
-#define BCHP_SWITCH_CORE_EGRESS_VID_RMK_TBL_DATA 0x04e0d110 /* Egress VID Remarking Table Data Register */
-#define BCHP_SWITCH_CORE_JOIN_ALL_VLAN_EN 0x04e0d140 /* Join All VLAN Enable Register */
-#define BCHP_SWITCH_CORE_PORT_IVL_SVL_CTRL 0x04e0d148 /* Port IVL or SVL Control Register */
-#define BCHP_SWITCH_CORE_BCM8021Q_REG_SPARE0 0x04e0d180 /* Spare 0 Register (Not2Release) */
-#define BCHP_SWITCH_CORE_BCM8021Q_REG_SPARE1 0x04e0d190 /* Spare 1 Register (Not2Release) */
-#define BCHP_SWITCH_CORE_DOS_CTRL 0x04e0d800 /* DoS Control RegisterRegister */
-#define BCHP_SWITCH_CORE_MINIMUM_TCP_HDR_SZ 0x04e0d810 /* Minimum TCP Header Size Register */
-#define BCHP_SWITCH_CORE_MAX_ICMPV4_SIZE_REG 0x04e0d820 /* Maximum ICMPv4 Size Register */
-#define BCHP_SWITCH_CORE_MAX_ICMPV6_SIZE_REG 0x04e0d830 /* Maximum ICMPv6 Size Register */
-#define BCHP_SWITCH_CORE_DOS_DIS_LRN_REG 0x04e0d840 /* DoS Disable Learn Register */
-#define BCHP_SWITCH_CORE_DOS_REG_SPARE0 0x04e0d880 /* Spare 0 Register (Not2Release) */
-#define BCHP_SWITCH_CORE_DOS_REG_SPARE1 0x04e0d890 /* Spare 1 Register (Not2Release) */
-#define BCHP_SWITCH_CORE_JUMBO_PORT_MASK 0x04e10004 /* Jumbo Frame Port Mask Registers */
-#define BCHP_SWITCH_CORE_MIB_GD_FM_MAX_SIZE 0x04e10014 /* Jumbo MIB Good Frame Max Size Registers */
-#define BCHP_SWITCH_CORE_JUMBO_CTRL_REG_SPARE0 0x04e10040 /* Spare 0 Register (Not2Release) */
-#define BCHP_SWITCH_CORE_JUMBO_CTRL_REG_SPARE1 0x04e10050 /* Spare 1 Register (Not2Release) */
-#define BCHP_SWITCH_CORE_COMM_IRC_CON 0x04e10400 /* Common Ingress rate Control Configuration Registers */
-#define BCHP_SWITCH_CORE_IRC_VIRTUAL_ZERO_THD 0x04e10410 /* Ingress Rate Control Virtual Zero Threshold Register (Not2Release) */
-#define BCHP_SWITCH_CORE_IRC_ALARM_THD 0x04e10418 /* Ingress Rate Control Alarm Threshold Register (Not2Release) */
-#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P_Port_0 0x04e10440 /* Port N Receive Rate Control Registers */
-#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P_Port_1 0x04e10450 /* Port N Receive Rate Control Registers */
-#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P_Port_2 0x04e10460 /* Port N Receive Rate Control Registers */
-#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P_Port_3 0x04e10470 /* Port N Receive Rate Control Registers */
-#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P_Port_4 0x04e10480 /* Port N Receive Rate Control Registers */
-#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P_Port_5 0x04e10490 /* Port N Receive Rate Control Registers */
-#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P7 0x04e104b0 /* Port 7 Receive Rate Control Registers */
-#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_IMP 0x04e104c0 /* Port 8 Receive Rate Control Registers */
-#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_1_P_Port_0 0x04e104d0 /* Port N Receive Rate Control 1 Registers */
-#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_1_P_Port_1 0x04e104d8 /* Port N Receive Rate Control 1 Registers */
-#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_1_P_Port_2 0x04e104e0 /* Port N Receive Rate Control 1 Registers */
-#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_1_P_Port_3 0x04e104e8 /* Port N Receive Rate Control 1 Registers */
-#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_1_P_Port_4 0x04e104f0 /* Port N Receive Rate Control 1 Registers */
-#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_1_P_Port_5 0x04e104f8 /* Port N Receive Rate Control 1 Registers */
-#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_1_P7 0x04e10508 /* Port 7 Receive Rate Control 1 Register */
-#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_1_IMP 0x04e1050c /* Port 8 Receive Rate Control 1 Register */
-#define BCHP_SWITCH_CORE_BC_SUP_PKTDROP_CNT_P_Port_0 0x04e10540 /* Port N Suppressed Packet Drop Counter Register */
-#define BCHP_SWITCH_CORE_BC_SUP_PKTDROP_CNT_P_Port_1 0x04e10550 /* Port N Suppressed Packet Drop Counter Register */
-#define BCHP_SWITCH_CORE_BC_SUP_PKTDROP_CNT_P_Port_2 0x04e10560 /* Port N Suppressed Packet Drop Counter Register */
-#define BCHP_SWITCH_CORE_BC_SUP_PKTDROP_CNT_P_Port_3 0x04e10570 /* Port N Suppressed Packet Drop Counter Register */
-#define BCHP_SWITCH_CORE_BC_SUP_PKTDROP_CNT_P_Port_4 0x04e10580 /* Port N Suppressed Packet Drop Counter Register */
-#define BCHP_SWITCH_CORE_BC_SUP_PKTDROP_CNT_P_Port_5 0x04e10590 /* Port N Suppressed Packet Drop Counter Register */
-#define BCHP_SWITCH_CORE_BC_SUP_PKTDROP_CNT_P7 0x04e105b0 /* Port 7 Suppressed Packet Drop Counter Register */
-#define BCHP_SWITCH_CORE_BC_SUP_PKTDROP_CNT_IMP 0x04e105c0 /* Port 8 Suppressed Packet Drop Counter Register */
-#define BCHP_SWITCH_CORE_BC_SUPPRESS_REG_SPARE0 0x04e10740 /* Spare 0 Register (Not2Release) */
-#define BCHP_SWITCH_CORE_BC_SUPPRESS_REG_SPARE1 0x04e10750 /* Spare 1 Register (Not2Release) */
-#define BCHP_SWITCH_CORE_EAP_GLO_CON 0x04e10800 /* EAP Global Configuration Registers */
-#define BCHP_SWITCH_CORE_EAP_MULTI_ADDR_CTRL 0x04e10804 /* EAP Multiport Address Control Register */
-#define BCHP_SWITCH_CORE_EAP_DIP_Port_0 0x04e10808 /* EAP Destination IP Registers */
-#define BCHP_SWITCH_CORE_EAP_DIP_Port_1 0x04e10828 /* EAP Destination IP Registers */
-#define BCHP_SWITCH_CORE_PORT_EAP_CON_Port_0 0x04e10880 /* Port N EAP Configuration Registers */
-#define BCHP_SWITCH_CORE_PORT_EAP_CON_Port_1 0x04e108a0 /* Port N EAP Configuration Registers */
-#define BCHP_SWITCH_CORE_PORT_EAP_CON_Port_2 0x04e108c0 /* Port N EAP Configuration Registers */
-#define BCHP_SWITCH_CORE_PORT_EAP_CON_Port_3 0x04e108e0 /* Port N EAP Configuration Registers */
-#define BCHP_SWITCH_CORE_PORT_EAP_CON_Port_4 0x04e10900 /* Port N EAP Configuration Registers */
-#define BCHP_SWITCH_CORE_PORT_EAP_CON_Port_5 0x04e10920 /* Port N EAP Configuration Registers */
-#define BCHP_SWITCH_CORE_PORT_EAP_CON_P7 0x04e10960 /* Port 7 EAP Configuration Registers */
-#define BCHP_SWITCH_CORE_PORT_EAP_CON_IMP 0x04e10980 /* IMP EAP Configuration Registers */
-#define BCHP_SWITCH_CORE_IEEE8021X_REG_SPARE0 0x04e109c0 /* Spare 0 Register (Not2Release) */
-#define BCHP_SWITCH_CORE_IEEE8021X_REG_SPARE1 0x04e109d0 /* Spare 1 Register (Not2Release) */
-#define BCHP_SWITCH_CORE_MST_CON 0x04e10c00 /* MST Control Registers */
-#define BCHP_SWITCH_CORE_MST_AGE 0x04e10c08 /* MST Ageing Control Register */
-#define BCHP_SWITCH_CORE_MST_TAB_Port_0 0x04e10c40 /* MST Table N Enable Registers */
-#define BCHP_SWITCH_CORE_MST_TAB_Port_1 0x04e10c50 /* MST Table N Enable Registers */
-#define BCHP_SWITCH_CORE_MST_TAB_Port_2 0x04e10c60 /* MST Table N Enable Registers */
-#define BCHP_SWITCH_CORE_MST_TAB_Port_3 0x04e10c70 /* MST Table N Enable Registers */
-#define BCHP_SWITCH_CORE_MST_TAB_Port_4 0x04e10c80 /* MST Table N Enable Registers */
-#define BCHP_SWITCH_CORE_MST_TAB_Port_5 0x04e10c90 /* MST Table N Enable Registers */
-#define BCHP_SWITCH_CORE_MST_TAB_Port_6 0x04e10ca0 /* MST Table N Enable Registers */
-#define BCHP_SWITCH_CORE_MST_TAB_Port_7 0x04e10cb0 /* MST Table N Enable Registers */
-#define BCHP_SWITCH_CORE_SPT_MULTI_ADDR_BPS_CTRL 0x04e10d40 /* STP Multiport Address Bypass Control Register */
-#define BCHP_SWITCH_CORE_IEEE8021S_REG_SPARE0 0x04e10d80 /* Spare 0 Register (Not2Release) */
-#define BCHP_SWITCH_CORE_IEEE8021S_REG_SPARE1 0x04e10d90 /* Spare 1 Register (Not2Release) */
-#define BCHP_SWITCH_CORE_SA_LIMIT_ENABLE 0x04e11400 /* SA Limit Enable Register */
-#define BCHP_SWITCH_CORE_SA_LRN_CNTR_RST 0x04e11408 /* SA Learned Counters Reset Register */
-#define BCHP_SWITCH_CORE_SA_OVERLIMIT_CNTR_RST 0x04e11410 /* SA Over Limit Counters Reset Register */
-#define BCHP_SWITCH_CORE_TOTAL_SA_LIMIT_CTL 0x04e11440 /* Total SA Limit Control Register */
-#define BCHP_SWITCH_CORE_PORT_N_SA_LIMIT_CTL_Port_0 0x04e11448 /* Port N SA Limit Control Register */
-#define BCHP_SWITCH_CORE_PORT_N_SA_LIMIT_CTL_Port_1 0x04e11450 /* Port N SA Limit Control Register */
-#define BCHP_SWITCH_CORE_PORT_N_SA_LIMIT_CTL_Port_2 0x04e11458 /* Port N SA Limit Control Register */
-#define BCHP_SWITCH_CORE_PORT_N_SA_LIMIT_CTL_Port_3 0x04e11460 /* Port N SA Limit Control Register */
-#define BCHP_SWITCH_CORE_PORT_N_SA_LIMIT_CTL_Port_4 0x04e11468 /* Port N SA Limit Control Register */
-#define BCHP_SWITCH_CORE_PORT_N_SA_LIMIT_CTL_Port_5 0x04e11470 /* Port N SA Limit Control Register */
-#define BCHP_SWITCH_CORE_PORT_7_SA_LIMIT_CTL 0x04e11480 /* Port 7 SA Limit Control Register */
-#define BCHP_SWITCH_CORE_PORT_8_SA_LIMIT_CTL 0x04e11488 /* Port 8 SA Limit Control Register */
-#define BCHP_SWITCH_CORE_TOTAL_SA_LRN_CNTR 0x04e114c0 /* Total SA Learned Counter Register */
-#define BCHP_SWITCH_CORE_PORT_N_SA_LRN_CNTR_Port_0 0x04e114c8 /* Port N SA Learned Counter Register */
-#define BCHP_SWITCH_CORE_PORT_N_SA_LRN_CNTR_Port_1 0x04e114d0 /* Port N SA Learned Counter Register */
-#define BCHP_SWITCH_CORE_PORT_N_SA_LRN_CNTR_Port_2 0x04e114d8 /* Port N SA Learned Counter Register */
-#define BCHP_SWITCH_CORE_PORT_N_SA_LRN_CNTR_Port_3 0x04e114e0 /* Port N SA Learned Counter Register */
-#define BCHP_SWITCH_CORE_PORT_N_SA_LRN_CNTR_Port_4 0x04e114e8 /* Port N SA Learned Counter Register */
-#define BCHP_SWITCH_CORE_PORT_N_SA_LRN_CNTR_Port_5 0x04e114f0 /* Port N SA Learned Counter Register */
-#define BCHP_SWITCH_CORE_PORT_7_SA_LRN_CNTR 0x04e11500 /* Port 7 SA Learned Counter Register */
-#define BCHP_SWITCH_CORE_PORT_8_SA_LRN_CNTR 0x04e11508 /* Port 8 SA Learned Counter Register */
-#define BCHP_SWITCH_CORE_PORT_N_SA_OVERLIMIT_CNTR_Port_0 0x04e11540 /* Port N SA Over Limit Counter Register */
-#define BCHP_SWITCH_CORE_PORT_N_SA_OVERLIMIT_CNTR_Port_1 0x04e11550 /* Port N SA Over Limit Counter Register */
-#define BCHP_SWITCH_CORE_PORT_N_SA_OVERLIMIT_CNTR_Port_2 0x04e11560 /* Port N SA Over Limit Counter Register */
-#define BCHP_SWITCH_CORE_PORT_N_SA_OVERLIMIT_CNTR_Port_3 0x04e11570 /* Port N SA Over Limit Counter Register */
-#define BCHP_SWITCH_CORE_PORT_N_SA_OVERLIMIT_CNTR_Port_4 0x04e11580 /* Port N SA Over Limit Counter Register */
-#define BCHP_SWITCH_CORE_PORT_N_SA_OVERLIMIT_CNTR_Port_5 0x04e11590 /* Port N SA Over Limit Counter Register */
-#define BCHP_SWITCH_CORE_PORT_7_SA_OVERLIMIT_CNTR 0x04e115b0 /* Port 7 SA Over Limit Counter Register */
-#define BCHP_SWITCH_CORE_PORT_8_SA_OVERLIMIT_CNTR 0x04e115c0 /* Port 8 SA Over Limit Counter Register */
-#define BCHP_SWITCH_CORE_SA_OVER_LIMIT_COPY_REDIRECT 0x04e115d0 /* SA Over Limit Actions Config Register */
-#define BCHP_SWITCH_CORE_MAC_LIMIT_REG_SPARE0 0x04e11600 /* Spare 0 Register (Not2Release) */
-#define BCHP_SWITCH_CORE_MAC_LIMIT_REG_SPARE1 0x04e11610 /* Spare 1 Register (Not2Release) */
-#define BCHP_SWITCH_CORE_PN_QOS_PRI_CTL_Port_0 0x04e11800 /* Port N, QOS Priority Control Register */
-#define BCHP_SWITCH_CORE_PN_QOS_PRI_CTL_Port_1 0x04e11804 /* Port N, QOS Priority Control Register */
-#define BCHP_SWITCH_CORE_PN_QOS_PRI_CTL_Port_2 0x04e11808 /* Port N, QOS Priority Control Register */
-#define BCHP_SWITCH_CORE_PN_QOS_PRI_CTL_Port_3 0x04e1180c /* Port N, QOS Priority Control Register */
-#define BCHP_SWITCH_CORE_PN_QOS_PRI_CTL_Port_4 0x04e11810 /* Port N, QOS Priority Control Register */
-#define BCHP_SWITCH_CORE_PN_QOS_PRI_CTL_Port_5 0x04e11814 /* Port N, QOS Priority Control Register */
-#define BCHP_SWITCH_CORE_P7_QOS_PRI_CTL 0x04e1181c /* Port 7, QOS Priority Control Register */
-#define BCHP_SWITCH_CORE_IMP_QOS_PRI_CTL 0x04e11820 /* Port 8, QOS Priority Control Register */
-#define BCHP_SWITCH_CORE_PN_QOS_WEIGHT_Port_0 0x04e11840 /* Port N, QOS Weight Register */
-#define BCHP_SWITCH_CORE_PN_QOS_WEIGHT_Port_1 0x04e11860 /* Port N, QOS Weight Register */
-#define BCHP_SWITCH_CORE_PN_QOS_WEIGHT_Port_2 0x04e11880 /* Port N, QOS Weight Register */
-#define BCHP_SWITCH_CORE_PN_QOS_WEIGHT_Port_3 0x04e118a0 /* Port N, QOS Weight Register */
-#define BCHP_SWITCH_CORE_PN_QOS_WEIGHT_Port_4 0x04e118c0 /* Port N, QOS Weight Register */
-#define BCHP_SWITCH_CORE_PN_QOS_WEIGHT_Port_5 0x04e118e0 /* Port N, QOS Weight Register */
-#define BCHP_SWITCH_CORE_P7_QOS_WEIGHT 0x04e11920 /* Port 7, QOS Weight Register */
-#define BCHP_SWITCH_CORE_IMP_QOS_WEIGHT 0x04e11940 /* Port 8, QOS Weight Register */
-#define BCHP_SWITCH_CORE_PN_WDRR_PENALTY_Port_0 0x04e11980 /* Port N, WDRR Weight-Scaling Penalty Register (Not2Release) */
-#define BCHP_SWITCH_CORE_PN_WDRR_PENALTY_Port_1 0x04e11988 /* Port N, WDRR Weight-Scaling Penalty Register (Not2Release) */
-#define BCHP_SWITCH_CORE_PN_WDRR_PENALTY_Port_2 0x04e11990 /* Port N, WDRR Weight-Scaling Penalty Register (Not2Release) */
-#define BCHP_SWITCH_CORE_PN_WDRR_PENALTY_Port_3 0x04e11998 /* Port N, WDRR Weight-Scaling Penalty Register (Not2Release) */
-#define BCHP_SWITCH_CORE_PN_WDRR_PENALTY_Port_4 0x04e119a0 /* Port N, WDRR Weight-Scaling Penalty Register (Not2Release) */
-#define BCHP_SWITCH_CORE_PN_WDRR_PENALTY_Port_5 0x04e119a8 /* Port N, WDRR Weight-Scaling Penalty Register (Not2Release) */
-#define BCHP_SWITCH_CORE_P7_WDRR_PENALTY 0x04e119c0 /* Port 7, WDRR Weight-Scaling Penalty Register (Not2Release) */
-#define BCHP_SWITCH_CORE_P8_WDRR_PENALTY 0x04e119c8 /* Port 8, WDRR Weight-Scaling Penalty Register (Not2Release) */
-#define BCHP_SWITCH_CORE_SCHEDULER_REG_SPARE0 0x04e11a00 /* Spare 0 Register (Not2Release) */
-#define BCHP_SWITCH_CORE_SCHEDULER_REG_SPARE1 0x04e11a10 /* Spare 1 Register (Not2Release) */
-#define BCHP_SWITCH_CORE_PN_PORT_SHAPER_BYTE_BASED_MAX_REFRESH_Port_0 0x04e11c00 /* Port N, Byte-Based, Port Shaper Shaping Rate Configure Register */
-#define BCHP_SWITCH_CORE_PN_PORT_SHAPER_BYTE_BASED_MAX_REFRESH_Port_1 0x04e11c10 /* Port N, Byte-Based, Port Shaper Shaping Rate Configure Register */
-#define BCHP_SWITCH_CORE_PN_PORT_SHAPER_BYTE_BASED_MAX_REFRESH_Port_2 0x04e11c20 /* Port N, Byte-Based, Port Shaper Shaping Rate Configure Register */
-#define BCHP_SWITCH_CORE_PN_PORT_SHAPER_BYTE_BASED_MAX_REFRESH_Port_3 0x04e11c30 /* Port N, Byte-Based, Port Shaper Shaping Rate Configure Register */
-#define BCHP_SWITCH_CORE_PN_PORT_SHAPER_BYTE_BASED_MAX_REFRESH_Port_4 0x04e11c40 /* Port N, Byte-Based, Port Shaper Shaping Rate Configure Register */
-#define BCHP_SWITCH_CORE_PN_PORT_SHAPER_BYTE_BASED_MAX_REFRESH_Port_5 0x04e11c50 /* Port N, Byte-Based, Port Shaper Shaping Rate Configure Register */
-#define BCHP_SWITCH_CORE_P7_PORT_SHAPER_BYTE_BASED_MAX_REFRESH 0x04e11c70 /* Port 7, Byte-Based, Port Shaper Shaping Rate Configure Register */
-#define BCHP_SWITCH_CORE_IMP_PORT_SHAPER_BYTE_BASED_MAX_REFRESH 0x04e11c80 /* Port 8, Byte-Based, Port Shaper Shaping Rate Configure Register */
-#define BCHP_SWITCH_CORE_PN_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_Port_0 0x04e11cc0 /* Port N, Byte-Based, Port Shaper Burst Size Configure Register */
-#define BCHP_SWITCH_CORE_PN_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_Port_1 0x04e11cd0 /* Port N, Byte-Based, Port Shaper Burst Size Configure Register */
-#define BCHP_SWITCH_CORE_PN_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_Port_2 0x04e11ce0 /* Port N, Byte-Based, Port Shaper Burst Size Configure Register */
-#define BCHP_SWITCH_CORE_PN_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_Port_3 0x04e11cf0 /* Port N, Byte-Based, Port Shaper Burst Size Configure Register */
-#define BCHP_SWITCH_CORE_PN_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_Port_4 0x04e11d00 /* Port N, Byte-Based, Port Shaper Burst Size Configure Register */
-#define BCHP_SWITCH_CORE_PN_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_Port_5 0x04e11d10 /* Port N, Byte-Based, Port Shaper Burst Size Configure Register */
-#define BCHP_SWITCH_CORE_P7_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL 0x04e11d30 /* Port 7, Byte-Based, Port Shaper Burst Size Configure Register */
-#define BCHP_SWITCH_CORE_IMP_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL 0x04e11d40 /* Port 8, Byte-Based, Port Shaper Burst Size Configure Register */
-#define BCHP_SWITCH_CORE_PN_PORT_SHAPER_STS_Port_0 0x04e11d80 /* Port N, PORT Shaper Status Register */
-#define BCHP_SWITCH_CORE_PN_PORT_SHAPER_STS_Port_1 0x04e11d90 /* Port N, PORT Shaper Status Register */
-#define BCHP_SWITCH_CORE_PN_PORT_SHAPER_STS_Port_2 0x04e11da0 /* Port N, PORT Shaper Status Register */
-#define BCHP_SWITCH_CORE_PN_PORT_SHAPER_STS_Port_3 0x04e11db0 /* Port N, PORT Shaper Status Register */
-#define BCHP_SWITCH_CORE_PN_PORT_SHAPER_STS_Port_4 0x04e11dc0 /* Port N, PORT Shaper Status Register */
-#define BCHP_SWITCH_CORE_PN_PORT_SHAPER_STS_Port_5 0x04e11dd0 /* Port N, PORT Shaper Status Register */
-#define BCHP_SWITCH_CORE_P7_PORT_SHAPER_STS 0x04e11df0 /* Port 7, PORT Shaper Status Register */
-#define BCHP_SWITCH_CORE_IMP_PORT_SHAPER_STS 0x04e11e00 /* Port 8, PORT Shaper Status Register */
-#define BCHP_SWITCH_CORE_PN_PORT_SHAPER_PACKET_BASED_MAX_REFRESH_Port_0 0x04e11e40 /* Port N, Packet-Based, Port Shaper Shaping Rate Configure Register */
-#define BCHP_SWITCH_CORE_PN_PORT_SHAPER_PACKET_BASED_MAX_REFRESH_Port_1 0x04e11e50 /* Port N, Packet-Based, Port Shaper Shaping Rate Configure Register */
-#define BCHP_SWITCH_CORE_PN_PORT_SHAPER_PACKET_BASED_MAX_REFRESH_Port_2 0x04e11e60 /* Port N, Packet-Based, Port Shaper Shaping Rate Configure Register */
-#define BCHP_SWITCH_CORE_PN_PORT_SHAPER_PACKET_BASED_MAX_REFRESH_Port_3 0x04e11e70 /* Port N, Packet-Based, Port Shaper Shaping Rate Configure Register */
-#define BCHP_SWITCH_CORE_PN_PORT_SHAPER_PACKET_BASED_MAX_REFRESH_Port_4 0x04e11e80 /* Port N, Packet-Based, Port Shaper Shaping Rate Configure Register */
-#define BCHP_SWITCH_CORE_PN_PORT_SHAPER_PACKET_BASED_MAX_REFRESH_Port_5 0x04e11e90 /* Port N, Packet-Based, Port Shaper Shaping Rate Configure Register */
-#define BCHP_SWITCH_CORE_P7_PORT_SHAPER_PACKET_BASED_MAX_REFRESH 0x04e11eb0 /* Port 7, Packet-Based, Port Shaper Shaping Rate Configure Register */
-#define BCHP_SWITCH_CORE_IMP_PORT_SHAPER_PACKET_BASED_MAX_REFRESH 0x04e11ec0 /* Port 8, Packet-Based, Port Shaper Shaping Rate Configure Register */
-#define BCHP_SWITCH_CORE_EGRESS_SHAPER_CTLREG_REG_SPARE0 0x04e11ee0 /* Spare 0 Register (Not2Release) */
-#define BCHP_SWITCH_CORE_EGRESS_SHAPER_CTLREG_REG_SPARE1 0x04e11ef0 /* Spare 1 Register (Not2Release) */
-#define BCHP_SWITCH_CORE_PN_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_Port_0 0x04e11f00 /* Port N, Packet-Based, Port Shaper Burst Size Configure Register */
-#define BCHP_SWITCH_CORE_PN_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_Port_1 0x04e11f10 /* Port N, Packet-Based, Port Shaper Burst Size Configure Register */
-#define BCHP_SWITCH_CORE_PN_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_Port_2 0x04e11f20 /* Port N, Packet-Based, Port Shaper Burst Size Configure Register */
-#define BCHP_SWITCH_CORE_PN_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_Port_3 0x04e11f30 /* Port N, Packet-Based, Port Shaper Burst Size Configure Register */
-#define BCHP_SWITCH_CORE_PN_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_Port_4 0x04e11f40 /* Port N, Packet-Based, Port Shaper Burst Size Configure Register */
-#define BCHP_SWITCH_CORE_PN_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_Port_5 0x04e11f50 /* Port N, Packet-Based, Port Shaper Burst Size Configure Register */
-#define BCHP_SWITCH_CORE_P7_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL 0x04e11f70 /* Port 7, Packet-Based, Port Shaper Burst Size Configure Register */
-#define BCHP_SWITCH_CORE_IMP_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL 0x04e11f80 /* Port 8, Packet-Based, Port Shaper Burst Size Configure Register */
-#define BCHP_SWITCH_CORE_PORT_SHAPER_AVB_SHAPING_MODE 0x04e11f90 /* Port Shaper AVB Shaping Mode Control Register */
-#define BCHP_SWITCH_CORE_PORT_SHAPER_ENABLE 0x04e11f98 /* Port Shaper Enable Register */
-#define BCHP_SWITCH_CORE_PORT_SHAPER_BUCKET_COUNT_SELECT 0x04e11fa0 /* Port Shaper Bucket Count Select Register */
-#define BCHP_SWITCH_CORE_PORT_SHAPER_BLOCKING 0x04e11fa8 /* Port Shaper Blocking Control Register */
-#define BCHP_SWITCH_CORE_IFG_BYTES 0x04e11fb8 /* IFG Correction Control Register */
-#define BCHP_SWITCH_CORE_PN_QUEUE0_MAX_REFRESH_Port_0 0x04e12000 /* Port N, Byte-based Queue 0 Shaping Rate Configure Register */
-#define BCHP_SWITCH_CORE_PN_QUEUE0_MAX_REFRESH_Port_1 0x04e12010 /* Port N, Byte-based Queue 0 Shaping Rate Configure Register */
-#define BCHP_SWITCH_CORE_PN_QUEUE0_MAX_REFRESH_Port_2 0x04e12020 /* Port N, Byte-based Queue 0 Shaping Rate Configure Register */
-#define BCHP_SWITCH_CORE_PN_QUEUE0_MAX_REFRESH_Port_3 0x04e12030 /* Port N, Byte-based Queue 0 Shaping Rate Configure Register */
-#define BCHP_SWITCH_CORE_PN_QUEUE0_MAX_REFRESH_Port_4 0x04e12040 /* Port N, Byte-based Queue 0 Shaping Rate Configure Register */
-#define BCHP_SWITCH_CORE_PN_QUEUE0_MAX_REFRESH_Port_5 0x04e12050 /* Port N, Byte-based Queue 0 Shaping Rate Configure Register */
-#define BCHP_SWITCH_CORE_P7_QUEUE0_MAX_REFRESH 0x04e12070 /* Port 7, Byte-based Queue 0 Shaping Rate Configure Register */
-#define BCHP_SWITCH_CORE_IMP_QUEUE0_MAX_REFRESH 0x04e12080 /* Port 8, Byte-based Queue 0 Shaping Rate Configure Register */
-#define BCHP_SWITCH_CORE_PN_QUEUE0_MAX_THD_SEL_Port_0 0x04e120c0 /* Port N, Byte-based Queue 0 Burst Size Configure Register */
-#define BCHP_SWITCH_CORE_PN_QUEUE0_MAX_THD_SEL_Port_1 0x04e120d0 /* Port N, Byte-based Queue 0 Burst Size Configure Register */
-#define BCHP_SWITCH_CORE_PN_QUEUE0_MAX_THD_SEL_Port_2 0x04e120e0 /* Port N, Byte-based Queue 0 Burst Size Configure Register */
-#define BCHP_SWITCH_CORE_PN_QUEUE0_MAX_THD_SEL_Port_3 0x04e120f0 /* Port N, Byte-based Queue 0 Burst Size Configure Register */
-#define BCHP_SWITCH_CORE_PN_QUEUE0_MAX_THD_SEL_Port_4 0x04e12100 /* Port N, Byte-based Queue 0 Burst Size Configure Register */
-#define BCHP_SWITCH_CORE_PN_QUEUE0_MAX_THD_SEL_Port_5 0x04e12110 /* Port N, Byte-based Queue 0 Burst Size Configure Register */
-#define BCHP_SWITCH_CORE_P7_QUEUE0_MAX_THD_SEL 0x04e12130 /* Port 7, Byte-based Queue 0 Burst Size Configure Register */
-#define BCHP_SWITCH_CORE_IMP_QUEUE0_MAX_THD_SEL 0x04e12140 /* Port 8, Byte-based Queue 0 Burst Size Configure Register */
-#define BCHP_SWITCH_CORE_PN_QUEUE0_SHAPER_STS_Port_0 0x04e12180 /* Port N, Queue 0 Shaper Status Register */
-#define BCHP_SWITCH_CORE_PN_QUEUE0_SHAPER_STS_Port_1 0x04e12190 /* Port N, Queue 0 Shaper Status Register */
-#define BCHP_SWITCH_CORE_PN_QUEUE0_SHAPER_STS_Port_2 0x04e121a0 /* Port N, Queue 0 Shaper Status Register */
-#define BCHP_SWITCH_CORE_PN_QUEUE0_SHAPER_STS_Port_3 0x04e121b0 /* Port N, Queue 0 Shaper Status Register */
-#define BCHP_SWITCH_CORE_PN_QUEUE0_SHAPER_STS_Port_4 0x04e121c0 /* Port N, Queue 0 Shaper Status Register */
-#define BCHP_SWITCH_CORE_PN_QUEUE0_SHAPER_STS_Port_5 0x04e121d0 /* Port N, Queue 0 Shaper Status Register */
-#define BCHP_SWITCH_CORE_P7_QUEUE0_SHAPER_STS 0x04e121f0 /* Port 7, Queue 0 Shaper Status Register */
-#define BCHP_SWITCH_CORE_IMP_QUEUE0_SHAPER_STS 0x04e12200 /* Port 8, Queue 0 Shaper Status Register */
-#define BCHP_SWITCH_CORE_PN_QUEUE0_MAX_PACKET_REFRESH_Port_0 0x04e12240 /* Port N, Packet-based Queue 0 Shaping Rate Configure Register */
-#define BCHP_SWITCH_CORE_PN_QUEUE0_MAX_PACKET_REFRESH_Port_1 0x04e12250 /* Port N, Packet-based Queue 0 Shaping Rate Configure Register */
-#define BCHP_SWITCH_CORE_PN_QUEUE0_MAX_PACKET_REFRESH_Port_2 0x04e12260 /* Port N, Packet-based Queue 0 Shaping Rate Configure Register */
-#define BCHP_SWITCH_CORE_PN_QUEUE0_MAX_PACKET_REFRESH_Port_3 0x04e12270 /* Port N, Packet-based Queue 0 Shaping Rate Configure Register */
-#define BCHP_SWITCH_CORE_PN_QUEUE0_MAX_PACKET_REFRESH_Port_4 0x04e12280 /* Port N, Packet-based Queue 0 Shaping Rate Configure Register */
-#define BCHP_SWITCH_CORE_PN_QUEUE0_MAX_PACKET_REFRESH_Port_5 0x04e12290 /* Port N, Packet-based Queue 0 Shaping Rate Configure Register */
-#define BCHP_SWITCH_CORE_P7_QUEUE0_MAX_PACKET_REFRESH 0x04e122b0 /* Port 7, Packet-based Queue 0 Shaping Rate Configure Register */
-#define BCHP_SWITCH_CORE_IMP_QUEUE0_MAX_PACKET_REFRESH 0x04e122c0 /* Port 8, Packet-based Queue 0 Shaping Rate Configure Register */
-#define BCHP_SWITCH_CORE_EGRESS_SHAPER_Q0_CONFIG_REG_SPARE0 0x04e122e0 /* Spare 0 Register (Not2Release) */
-#define BCHP_SWITCH_CORE_EGRESS_SHAPER_Q0_CONFIG_REG_SPARE1 0x04e122f0 /* Spare 1 Register (Not2Release) */
-#define BCHP_SWITCH_CORE_PN_QUEUE0_MAX_PACKET_THD_SEL_Port_0 0x04e12300 /* Port N, Packet-based Queue 0 Burst Size Configure Register */
-#define BCHP_SWITCH_CORE_PN_QUEUE0_MAX_PACKET_THD_SEL_Port_1 0x04e12310 /* Port N, Packet-based Queue 0 Burst Size Configure Register */
-#define BCHP_SWITCH_CORE_PN_QUEUE0_MAX_PACKET_THD_SEL_Port_2 0x04e12320 /* Port N, Packet-based Queue 0 Burst Size Configure Register */
-#define BCHP_SWITCH_CORE_PN_QUEUE0_MAX_PACKET_THD_SEL_Port_3 0x04e12330 /* Port N, Packet-based Queue 0 Burst Size Configure Register */
-#define BCHP_SWITCH_CORE_PN_QUEUE0_MAX_PACKET_THD_SEL_Port_4 0x04e12340 /* Port N, Packet-based Queue 0 Burst Size Configure Register */
-#define BCHP_SWITCH_CORE_PN_QUEUE0_MAX_PACKET_THD_SEL_Port_5 0x04e12350 /* Port N, Packet-based Queue 0 Burst Size Configure Register */
-#define BCHP_SWITCH_CORE_P7_QUEUE0_MAX_PACKET_THD_SEL 0x04e12370 /* Port 7, Packet-based Queue 0 Burst Size Configure Register */
-#define BCHP_SWITCH_CORE_IMP_QUEUE0_MAX_PACKET_THD_SEL 0x04e12380 /* Port 8, Packet-based Queue 0 Burst Size Configure Register */
-#define BCHP_SWITCH_CORE_QUEUE0_AVB_SHAPING_MODE 0x04e12390 /* Queue 0 AVB Shaping Mode Control Register */
-#define BCHP_SWITCH_CORE_QUEUE0_SHAPER_ENABLE 0x04e12398 /* Queue 0 Shaper Enable Register */
-#define BCHP_SWITCH_CORE_QUEUE0_SHAPER_BUCKET_COUNT_SELECT 0x04e123a0 /* Queue 0 Bucket Count Select Register */
-#define BCHP_SWITCH_CORE_QUEUE0_SHAPER_BLOCKING 0x04e123a8 /* Queue 0 Shaper Blocking Control Register */
-#define BCHP_SWITCH_CORE_PN_QUEUE1_MAX_REFRESH_Port_0 0x04e12400 /* Port N, Byte-based Queue 1 Shaping Rate Configure Register */
-#define BCHP_SWITCH_CORE_PN_QUEUE1_MAX_REFRESH_Port_1 0x04e12410 /* Port N, Byte-based Queue 1 Shaping Rate Configure Register */
-#define BCHP_SWITCH_CORE_PN_QUEUE1_MAX_REFRESH_Port_2 0x04e12420 /* Port N, Byte-based Queue 1 Shaping Rate Configure Register */
-#define BCHP_SWITCH_CORE_PN_QUEUE1_MAX_REFRESH_Port_3 0x04e12430 /* Port N, Byte-based Queue 1 Shaping Rate Configure Register */
-#define BCHP_SWITCH_CORE_PN_QUEUE1_MAX_REFRESH_Port_4 0x04e12440 /* Port N, Byte-based Queue 1 Shaping Rate Configure Register */
-#define BCHP_SWITCH_CORE_PN_QUEUE1_MAX_REFRESH_Port_5 0x04e12450 /* Port N, Byte-based Queue 1 Shaping Rate Configure Register */
-#define BCHP_SWITCH_CORE_P7_QUEUE1_MAX_REFRESH 0x04e12470 /* Port 7, Byte-based Queue 1 Shaping Rate Configure Register */
-#define BCHP_SWITCH_CORE_IMP_QUEUE1_MAX_REFRESH 0x04e12480 /* Port 8, Byte-based Queue 1 Shaping Rate Configure Register */
-#define BCHP_SWITCH_CORE_PN_QUEUE1_MAX_THD_SEL_Port_0 0x04e124c0 /* Port N, Byte-based Queue 1 Burst Size Configure Register */
-#define BCHP_SWITCH_CORE_PN_QUEUE1_MAX_THD_SEL_Port_1 0x04e124d0 /* Port N, Byte-based Queue 1 Burst Size Configure Register */
-#define BCHP_SWITCH_CORE_PN_QUEUE1_MAX_THD_SEL_Port_2 0x04e124e0 /* Port N, Byte-based Queue 1 Burst Size Configure Register */
-#define BCHP_SWITCH_CORE_PN_QUEUE1_MAX_THD_SEL_Port_3 0x04e124f0 /* Port N, Byte-based Queue 1 Burst Size Configure Register */
-#define BCHP_SWITCH_CORE_PN_QUEUE1_MAX_THD_SEL_Port_4 0x04e12500 /* Port N, Byte-based Queue 1 Burst Size Configure Register */
-#define BCHP_SWITCH_CORE_PN_QUEUE1_MAX_THD_SEL_Port_5 0x04e12510 /* Port N, Byte-based Queue 1 Burst Size Configure Register */
-#define BCHP_SWITCH_CORE_P7_QUEUE1_MAX_THD_SEL 0x04e12530 /* Port 7, Byte-based Queue 1 Burst Size Configure Register */
-#define BCHP_SWITCH_CORE_IMP_QUEUE1_MAX_THD_SEL 0x04e12540 /* Port 8, Byte-based Queue 1 Burst Size Configure Register */
-#define BCHP_SWITCH_CORE_PN_QUEUE1_SHAPER_STS_Port_0 0x04e12580 /* Port N, Queue 1 Shaper Status Register */
-#define BCHP_SWITCH_CORE_PN_QUEUE1_SHAPER_STS_Port_1 0x04e12590 /* Port N, Queue 1 Shaper Status Register */
-#define BCHP_SWITCH_CORE_PN_QUEUE1_SHAPER_STS_Port_2 0x04e125a0 /* Port N, Queue 1 Shaper Status Register */
-#define BCHP_SWITCH_CORE_PN_QUEUE1_SHAPER_STS_Port_3 0x04e125b0 /* Port N, Queue 1 Shaper Status Register */
-#define BCHP_SWITCH_CORE_PN_QUEUE1_SHAPER_STS_Port_4 0x04e125c0 /* Port N, Queue 1 Shaper Status Register */
-#define BCHP_SWITCH_CORE_PN_QUEUE1_SHAPER_STS_Port_5 0x04e125d0 /* Port N, Queue 1 Shaper Status Register */
-#define BCHP_SWITCH_CORE_P7_QUEUE1_SHAPER_STS 0x04e125f0 /* Port 7, Queue 1 Shaper Status Register */
-#define BCHP_SWITCH_CORE_IMP_QUEUE1_SHAPER_STS 0x04e12600 /* Port 8, Queue 1 Shaper Status Register */
-#define BCHP_SWITCH_CORE_PN_QUEUE1_MAX_PACKET_REFRESH_Port_0 0x04e12640 /* Port N, Packet-based Queue 1 Shaping Rate Configure Register */
-#define BCHP_SWITCH_CORE_PN_QUEUE1_MAX_PACKET_REFRESH_Port_1 0x04e12650 /* Port N, Packet-based Queue 1 Shaping Rate Configure Register */
-#define BCHP_SWITCH_CORE_PN_QUEUE1_MAX_PACKET_REFRESH_Port_2 0x04e12660 /* Port N, Packet-based Queue 1 Shaping Rate Configure Register */
-#define BCHP_SWITCH_CORE_PN_QUEUE1_MAX_PACKET_REFRESH_Port_3 0x04e12670 /* Port N, Packet-based Queue 1 Shaping Rate Configure Register */
-#define BCHP_SWITCH_CORE_PN_QUEUE1_MAX_PACKET_REFRESH_Port_4 0x04e12680 /* Port N, Packet-based Queue 1 Shaping Rate Configure Register */
-#define BCHP_SWITCH_CORE_PN_QUEUE1_MAX_PACKET_REFRESH_Port_5 0x04e12690 /* Port N, Packet-based Queue 1 Shaping Rate Configure Register */
-#define BCHP_SWITCH_CORE_P7_QUEUE1_MAX_PACKET_REFRESH 0x04e126b0 /* Port 7, Packet-based Queue 1 Shaping Rate Configure Register */
-#define BCHP_SWITCH_CORE_IMP_QUEUE1_MAX_PACKET_REFRESH 0x04e126c0 /* Port 8, Packet-based Queue 1 Shaping Rate Configure Register */
-#define BCHP_SWITCH_CORE_EGRESS_SHAPER_Q1_CONFIG_REG_SPARE0 0x04e126e0 /* Spare 0 Register (Not2Release) */
-#define BCHP_SWITCH_CORE_EGRESS_SHAPER_Q1_CONFIG_REG_SPARE1 0x04e126f0 /* Spare 1 Register (Not2Release) */
-#define BCHP_SWITCH_CORE_PN_QUEUE1_MAX_PACKET_THD_SEL_Port_0 0x04e12700 /* Port N, Packet-based Queue 1 Burst Size Configure Register */
-#define BCHP_SWITCH_CORE_PN_QUEUE1_MAX_PACKET_THD_SEL_Port_1 0x04e12710 /* Port N, Packet-based Queue 1 Burst Size Configure Register */
-#define BCHP_SWITCH_CORE_PN_QUEUE1_MAX_PACKET_THD_SEL_Port_2 0x04e12720 /* Port N, Packet-based Queue 1 Burst Size Configure Register */
-#define BCHP_SWITCH_CORE_PN_QUEUE1_MAX_PACKET_THD_SEL_Port_3 0x04e12730 /* Port N, Packet-based Queue 1 Burst Size Configure Register */
-#define BCHP_SWITCH_CORE_PN_QUEUE1_MAX_PACKET_THD_SEL_Port_4 0x04e12740 /* Port N, Packet-based Queue 1 Burst Size Configure Register */
-#define BCHP_SWITCH_CORE_PN_QUEUE1_MAX_PACKET_THD_SEL_Port_5 0x04e12750 /* Port N, Packet-based Queue 1 Burst Size Configure Register */
-#define BCHP_SWITCH_CORE_P7_QUEUE1_MAX_PACKET_THD_SEL 0x04e12770 /* Port 7, Packet-based Queue 1 Burst Size Configure Register */
-#define BCHP_SWITCH_CORE_IMP_QUEUE1_MAX_PACKET_THD_SEL 0x04e12780 /* Port 8, Packet-based Queue 1 Burst Size Configure Register */
-#define BCHP_SWITCH_CORE_QUEUE1_AVB_SHAPING_MODE 0x04e12790 /* Queue 1 AVB Shaping Mode Control Register */
-#define BCHP_SWITCH_CORE_QUEUE1_SHAPER_ENABLE 0x04e12798 /* Queue 1 Shaper Enable Register */
-#define BCHP_SWITCH_CORE_QUEUE1_SHAPER_BUCKET_COUNT_SELECT 0x04e127a0 /* Queue 1 Bucket Count Select Register */
-#define BCHP_SWITCH_CORE_QUEUE1_SHAPER_BLOCKING 0x04e127a8 /* Queue 1 Shaper Blocking Control Register */
-#define BCHP_SWITCH_CORE_PN_QUEUE2_MAX_REFRESH_Port_0 0x04e12800 /* Port N, Byte-based Queue 2 Shaping Rate Configure Register */
-#define BCHP_SWITCH_CORE_PN_QUEUE2_MAX_REFRESH_Port_1 0x04e12810 /* Port N, Byte-based Queue 2 Shaping Rate Configure Register */
-#define BCHP_SWITCH_CORE_PN_QUEUE2_MAX_REFRESH_Port_2 0x04e12820 /* Port N, Byte-based Queue 2 Shaping Rate Configure Register */
-#define BCHP_SWITCH_CORE_PN_QUEUE2_MAX_REFRESH_Port_3 0x04e12830 /* Port N, Byte-based Queue 2 Shaping Rate Configure Register */
-#define BCHP_SWITCH_CORE_PN_QUEUE2_MAX_REFRESH_Port_4 0x04e12840 /* Port N, Byte-based Queue 2 Shaping Rate Configure Register */
-#define BCHP_SWITCH_CORE_PN_QUEUE2_MAX_REFRESH_Port_5 0x04e12850 /* Port N, Byte-based Queue 2 Shaping Rate Configure Register */
-#define BCHP_SWITCH_CORE_P7_QUEUE2_MAX_REFRESH 0x04e12870 /* Port 7, Byte-based Queue 2 Shaping Rate Configure Register */
-#define BCHP_SWITCH_CORE_IMP_QUEUE2_MAX_REFRESH 0x04e12880 /* Port 8, Byte-based Queue 2 Shaping Rate Configure Register */
-#define BCHP_SWITCH_CORE_PN_QUEUE2_MAX_THD_SEL_Port_0 0x04e128c0 /* Port N, Byte-based Queue 2 Burst Size Configure Register */
-#define BCHP_SWITCH_CORE_PN_QUEUE2_MAX_THD_SEL_Port_1 0x04e128d0 /* Port N, Byte-based Queue 2 Burst Size Configure Register */
-#define BCHP_SWITCH_CORE_PN_QUEUE2_MAX_THD_SEL_Port_2 0x04e128e0 /* Port N, Byte-based Queue 2 Burst Size Configure Register */
-#define BCHP_SWITCH_CORE_PN_QUEUE2_MAX_THD_SEL_Port_3 0x04e128f0 /* Port N, Byte-based Queue 2 Burst Size Configure Register */
-#define BCHP_SWITCH_CORE_PN_QUEUE2_MAX_THD_SEL_Port_4 0x04e12900 /* Port N, Byte-based Queue 2 Burst Size Configure Register */
-#define BCHP_SWITCH_CORE_PN_QUEUE2_MAX_THD_SEL_Port_5 0x04e12910 /* Port N, Byte-based Queue 2 Burst Size Configure Register */
-#define BCHP_SWITCH_CORE_P7_QUEUE2_MAX_THD_SEL 0x04e12930 /* Port 7, Byte-based Queue 2 Burst Size Configure Register */
-#define BCHP_SWITCH_CORE_IMP_QUEUE2_MAX_THD_SEL 0x04e12940 /* Port 8, Byte-based Queue 2 Burst Size Configure Register */
-#define BCHP_SWITCH_CORE_PN_QUEUE2_SHAPER_STS_Port_0 0x04e12980 /* Port N, Queue 2 Shaper Status Register */
-#define BCHP_SWITCH_CORE_PN_QUEUE2_SHAPER_STS_Port_1 0x04e12990 /* Port N, Queue 2 Shaper Status Register */
-#define BCHP_SWITCH_CORE_PN_QUEUE2_SHAPER_STS_Port_2 0x04e129a0 /* Port N, Queue 2 Shaper Status Register */
-#define BCHP_SWITCH_CORE_PN_QUEUE2_SHAPER_STS_Port_3 0x04e129b0 /* Port N, Queue 2 Shaper Status Register */
-#define BCHP_SWITCH_CORE_PN_QUEUE2_SHAPER_STS_Port_4 0x04e129c0 /* Port N, Queue 2 Shaper Status Register */
-#define BCHP_SWITCH_CORE_PN_QUEUE2_SHAPER_STS_Port_5 0x04e129d0 /* Port N, Queue 2 Shaper Status Register */
-#define BCHP_SWITCH_CORE_P7_QUEUE2_SHAPER_STS 0x04e129f0 /* Port 7, Queue 2 Shaper Status Register */
-#define BCHP_SWITCH_CORE_IMP_QUEUE2_SHAPER_STS 0x04e12a00 /* Port 8, Queue 2 Shaper Status Register */
-#define BCHP_SWITCH_CORE_PN_QUEUE2_MAX_PACKET_REFRESH_Port_0 0x04e12a40 /* Port N, Packet-based Queue 2 Shaping Rate Configure Register */
-#define BCHP_SWITCH_CORE_PN_QUEUE2_MAX_PACKET_REFRESH_Port_1 0x04e12a50 /* Port N, Packet-based Queue 2 Shaping Rate Configure Register */
-#define BCHP_SWITCH_CORE_PN_QUEUE2_MAX_PACKET_REFRESH_Port_2 0x04e12a60 /* Port N, Packet-based Queue 2 Shaping Rate Configure Register */
-#define BCHP_SWITCH_CORE_PN_QUEUE2_MAX_PACKET_REFRESH_Port_3 0x04e12a70 /* Port N, Packet-based Queue 2 Shaping Rate Configure Register */
-#define BCHP_SWITCH_CORE_PN_QUEUE2_MAX_PACKET_REFRESH_Port_4 0x04e12a80 /* Port N, Packet-based Queue 2 Shaping Rate Configure Register */
-#define BCHP_SWITCH_CORE_PN_QUEUE2_MAX_PACKET_REFRESH_Port_5 0x04e12a90 /* Port N, Packet-based Queue 2 Shaping Rate Configure Register */
-#define BCHP_SWITCH_CORE_P7_QUEUE2_MAX_PACKET_REFRESH 0x04e12ab0 /* Port 7, Packet-based Queue 2 Shaping Rate Configure Register */
-#define BCHP_SWITCH_CORE_IMP_QUEUE2_MAX_PACKET_REFRESH 0x04e12ac0 /* Port 8, Packet-based Queue 2 Shaping Rate Configure Register */
-#define BCHP_SWITCH_CORE_EGRESS_SHAPER_Q2_CONFIG_REG_SPARE0 0x04e12ae0 /* Spare 0 Register (Not2Release) */
-#define BCHP_SWITCH_CORE_EGRESS_SHAPER_Q2_CONFIG_REG_SPARE1 0x04e12af0 /* Spare 1 Register (Not2Release) */
-#define BCHP_SWITCH_CORE_PN_QUEUE2_MAX_PACKET_THD_SEL_Port_0 0x04e12b00 /* Port N, Packet-based Queue 2 Burst Size Configure Register */
-#define BCHP_SWITCH_CORE_PN_QUEUE2_MAX_PACKET_THD_SEL_Port_1 0x04e12b10 /* Port N, Packet-based Queue 2 Burst Size Configure Register */
-#define BCHP_SWITCH_CORE_PN_QUEUE2_MAX_PACKET_THD_SEL_Port_2 0x04e12b20 /* Port N, Packet-based Queue 2 Burst Size Configure Register */
-#define BCHP_SWITCH_CORE_PN_QUEUE2_MAX_PACKET_THD_SEL_Port_3 0x04e12b30 /* Port N, Packet-based Queue 2 Burst Size Configure Register */
-#define BCHP_SWITCH_CORE_PN_QUEUE2_MAX_PACKET_THD_SEL_Port_4 0x04e12b40 /* Port N, Packet-based Queue 2 Burst Size Configure Register */
-#define BCHP_SWITCH_CORE_PN_QUEUE2_MAX_PACKET_THD_SEL_Port_5 0x04e12b50 /* Port N, Packet-based Queue 2 Burst Size Configure Register */
-#define BCHP_SWITCH_CORE_P7_QUEUE2_MAX_PACKET_THD_SEL 0x04e12b70 /* Port 7, Packet-based Queue 2 Burst Size Configure Register */
-#define BCHP_SWITCH_CORE_IMP_QUEUE2_MAX_PACKET_THD_SEL 0x04e12b80 /* Port 8, Packet-based Queue 2 Burst Size Configure Register */
-#define BCHP_SWITCH_CORE_QUEUE2_AVB_SHAPING_MODE 0x04e12b90 /* Queue 2 AVB Shaping Mode Control Register */
-#define BCHP_SWITCH_CORE_QUEUE2_SHAPER_ENABLE 0x04e12b98 /* Queue 2 Shaper Enable Register */
-#define BCHP_SWITCH_CORE_QUEUE2_SHAPER_BUCKET_COUNT_SELECT 0x04e12ba0 /* Queue 2 Bucket Count Select Register */
-#define BCHP_SWITCH_CORE_QUEUE2_SHAPER_BLOCKING 0x04e12ba8 /* Queue 2 Shaper Blocking Control Register */
-#define BCHP_SWITCH_CORE_PN_QUEUE3_MAX_REFRESH_Port_0 0x04e12c00 /* Port N, Byte-based Queue 3 Shaping Rate Configure Register */
-#define BCHP_SWITCH_CORE_PN_QUEUE3_MAX_REFRESH_Port_1 0x04e12c10 /* Port N, Byte-based Queue 3 Shaping Rate Configure Register */
-#define BCHP_SWITCH_CORE_PN_QUEUE3_MAX_REFRESH_Port_2 0x04e12c20 /* Port N, Byte-based Queue 3 Shaping Rate Configure Register */
-#define BCHP_SWITCH_CORE_PN_QUEUE3_MAX_REFRESH_Port_3 0x04e12c30 /* Port N, Byte-based Queue 3 Shaping Rate Configure Register */
-#define BCHP_SWITCH_CORE_PN_QUEUE3_MAX_REFRESH_Port_4 0x04e12c40 /* Port N, Byte-based Queue 3 Shaping Rate Configure Register */
-#define BCHP_SWITCH_CORE_PN_QUEUE3_MAX_REFRESH_Port_5 0x04e12c50 /* Port N, Byte-based Queue 3 Shaping Rate Configure Register */
-#define BCHP_SWITCH_CORE_P7_QUEUE3_MAX_REFRESH 0x04e12c70 /* Port 7, Byte-based Queue 3 Shaping Rate Configure Register */
-#define BCHP_SWITCH_CORE_IMP_QUEUE3_MAX_REFRESH 0x04e12c80 /* Port 8, Byte-based Queue 3 Shaping Rate Configure Register */
-#define BCHP_SWITCH_CORE_PN_QUEUE3_MAX_THD_SEL_Port_0 0x04e12cc0 /* Port N, Byte-based Queue 3 Burst Size Configure Register */
-#define BCHP_SWITCH_CORE_PN_QUEUE3_MAX_THD_SEL_Port_1 0x04e12cd0 /* Port N, Byte-based Queue 3 Burst Size Configure Register */
-#define BCHP_SWITCH_CORE_PN_QUEUE3_MAX_THD_SEL_Port_2 0x04e12ce0 /* Port N, Byte-based Queue 3 Burst Size Configure Register */
-#define BCHP_SWITCH_CORE_PN_QUEUE3_MAX_THD_SEL_Port_3 0x04e12cf0 /* Port N, Byte-based Queue 3 Burst Size Configure Register */
-#define BCHP_SWITCH_CORE_PN_QUEUE3_MAX_THD_SEL_Port_4 0x04e12d00 /* Port N, Byte-based Queue 3 Burst Size Configure Register */
-#define BCHP_SWITCH_CORE_PN_QUEUE3_MAX_THD_SEL_Port_5 0x04e12d10 /* Port N, Byte-based Queue 3 Burst Size Configure Register */
-#define BCHP_SWITCH_CORE_P7_QUEUE3_MAX_THD_SEL 0x04e12d30 /* Port 7, Byte-based Queue 3 Burst Size Configure Register */
-#define BCHP_SWITCH_CORE_IMP_QUEUE3_MAX_THD_SEL 0x04e12d40 /* Port 8, Byte-based Queue 3 Burst Size Configure Register */
-#define BCHP_SWITCH_CORE_PN_QUEUE3_SHAPER_STS_Port_0 0x04e12d80 /* Port N, Queue 3 Shaper Status Register */
-#define BCHP_SWITCH_CORE_PN_QUEUE3_SHAPER_STS_Port_1 0x04e12d90 /* Port N, Queue 3 Shaper Status Register */
-#define BCHP_SWITCH_CORE_PN_QUEUE3_SHAPER_STS_Port_2 0x04e12da0 /* Port N, Queue 3 Shaper Status Register */
-#define BCHP_SWITCH_CORE_PN_QUEUE3_SHAPER_STS_Port_3 0x04e12db0 /* Port N, Queue 3 Shaper Status Register */
-#define BCHP_SWITCH_CORE_PN_QUEUE3_SHAPER_STS_Port_4 0x04e12dc0 /* Port N, Queue 3 Shaper Status Register */
-#define BCHP_SWITCH_CORE_PN_QUEUE3_SHAPER_STS_Port_5 0x04e12dd0 /* Port N, Queue 3 Shaper Status Register */
-#define BCHP_SWITCH_CORE_P7_QUEUE3_SHAPER_STS 0x04e12df0 /* Port 7, Queue 3 Shaper Status Register */
-#define BCHP_SWITCH_CORE_IMP_QUEUE3_SHAPER_STS 0x04e12e00 /* Port 8, Queue 3 Shaper Status Register */
-#define BCHP_SWITCH_CORE_PN_QUEUE3_MAX_PACKET_REFRESH_Port_0 0x04e12e40 /* Port N, Packet-based Queue 3 Shaping Rate Configure Register */
-#define BCHP_SWITCH_CORE_PN_QUEUE3_MAX_PACKET_REFRESH_Port_1 0x04e12e50 /* Port N, Packet-based Queue 3 Shaping Rate Configure Register */
-#define BCHP_SWITCH_CORE_PN_QUEUE3_MAX_PACKET_REFRESH_Port_2 0x04e12e60 /* Port N, Packet-based Queue 3 Shaping Rate Configure Register */
-#define BCHP_SWITCH_CORE_PN_QUEUE3_MAX_PACKET_REFRESH_Port_3 0x04e12e70 /* Port N, Packet-based Queue 3 Shaping Rate Configure Register */
-#define BCHP_SWITCH_CORE_PN_QUEUE3_MAX_PACKET_REFRESH_Port_4 0x04e12e80 /* Port N, Packet-based Queue 3 Shaping Rate Configure Register */
-#define BCHP_SWITCH_CORE_PN_QUEUE3_MAX_PACKET_REFRESH_Port_5 0x04e12e90 /* Port N, Packet-based Queue 3 Shaping Rate Configure Register */
-#define BCHP_SWITCH_CORE_P7_QUEUE3_MAX_PACKET_REFRESH 0x04e12eb0 /* Port 7, Packet-based Queue 3 Shaping Rate Configure Register */
-#define BCHP_SWITCH_CORE_IMP_QUEUE3_MAX_PACKET_REFRESH 0x04e12ec0 /* Port 8, Packet-based Queue 3 Shaping Rate Configure Register */
-#define BCHP_SWITCH_CORE_EGRESS_SHAPER_Q3_CONFIG_REG_SPARE0 0x04e12ee0 /* Spare 0 Register (Not2Release) */
-#define BCHP_SWITCH_CORE_EGRESS_SHAPER_Q3_CONFIG_REG_SPARE1 0x04e12ef0 /* Spare 1 Register (Not2Release) */
-#define BCHP_SWITCH_CORE_PN_QUEUE3_MAX_PACKET_THD_SEL_Port_0 0x04e12f00 /* Port N, Packet-based Queue 3 Burst Size Configure Register */
-#define BCHP_SWITCH_CORE_PN_QUEUE3_MAX_PACKET_THD_SEL_Port_1 0x04e12f10 /* Port N, Packet-based Queue 3 Burst Size Configure Register */
-#define BCHP_SWITCH_CORE_PN_QUEUE3_MAX_PACKET_THD_SEL_Port_2 0x04e12f20 /* Port N, Packet-based Queue 3 Burst Size Configure Register */
-#define BCHP_SWITCH_CORE_PN_QUEUE3_MAX_PACKET_THD_SEL_Port_3 0x04e12f30 /* Port N, Packet-based Queue 3 Burst Size Configure Register */
-#define BCHP_SWITCH_CORE_PN_QUEUE3_MAX_PACKET_THD_SEL_Port_4 0x04e12f40 /* Port N, Packet-based Queue 3 Burst Size Configure Register */
-#define BCHP_SWITCH_CORE_PN_QUEUE3_MAX_PACKET_THD_SEL_Port_5 0x04e12f50 /* Port N, Packet-based Queue 3 Burst Size Configure Register */
-#define BCHP_SWITCH_CORE_P7_QUEUE3_MAX_PACKET_THD_SEL 0x04e12f70 /* Port 7, Packet-based Queue 3 Burst Size Configure Register */
-#define BCHP_SWITCH_CORE_IMP_QUEUE3_MAX_PACKET_THD_SEL 0x04e12f80 /* Port 8, Packet-based Queue 3 Burst Size Configure Register */
-#define BCHP_SWITCH_CORE_QUEUE3_AVB_SHAPING_MODE 0x04e12f90 /* Queue 3 AVB Shaping Mode Control Register */
-#define BCHP_SWITCH_CORE_QUEUE3_SHAPER_ENABLE 0x04e12f98 /* Queue 3 Shaper Enable Register */
-#define BCHP_SWITCH_CORE_QUEUE3_SHAPER_BUCKET_COUNT_SELECT 0x04e12fa0 /* Queue 3 Bucket Count Select Register */
-#define BCHP_SWITCH_CORE_QUEUE3_SHAPER_BLOCKING 0x04e12fa8 /* Queue 3 Shaper Blocking Control Register */
-#define BCHP_SWITCH_CORE_PN_QUEUE4_MAX_REFRESH_Port_0 0x04e13000 /* Port N, Byte-based Queue 4 Shaping Rate Configure Register */
-#define BCHP_SWITCH_CORE_PN_QUEUE4_MAX_REFRESH_Port_1 0x04e13010 /* Port N, Byte-based Queue 4 Shaping Rate Configure Register */
-#define BCHP_SWITCH_CORE_PN_QUEUE4_MAX_REFRESH_Port_2 0x04e13020 /* Port N, Byte-based Queue 4 Shaping Rate Configure Register */
-#define BCHP_SWITCH_CORE_PN_QUEUE4_MAX_REFRESH_Port_3 0x04e13030 /* Port N, Byte-based Queue 4 Shaping Rate Configure Register */
-#define BCHP_SWITCH_CORE_PN_QUEUE4_MAX_REFRESH_Port_4 0x04e13040 /* Port N, Byte-based Queue 4 Shaping Rate Configure Register */
-#define BCHP_SWITCH_CORE_PN_QUEUE4_MAX_REFRESH_Port_5 0x04e13050 /* Port N, Byte-based Queue 4 Shaping Rate Configure Register */
-#define BCHP_SWITCH_CORE_P7_QUEUE4_MAX_REFRESH 0x04e13070 /* Port 7, Byte-based Queue 4 Shaping Rate Configure Register */
-#define BCHP_SWITCH_CORE_IMP_QUEUE4_MAX_REFRESH 0x04e13080 /* Port 8, Byte-based Queue 4 Shaping Rate Configure Register */
-#define BCHP_SWITCH_CORE_PN_QUEUE4_MAX_THD_SEL_Port_0 0x04e130c0 /* Port N, Byte-based Queue 4 Burst Size Configure Register */
-#define BCHP_SWITCH_CORE_PN_QUEUE4_MAX_THD_SEL_Port_1 0x04e130d0 /* Port N, Byte-based Queue 4 Burst Size Configure Register */
-#define BCHP_SWITCH_CORE_PN_QUEUE4_MAX_THD_SEL_Port_2 0x04e130e0 /* Port N, Byte-based Queue 4 Burst Size Configure Register */
-#define BCHP_SWITCH_CORE_PN_QUEUE4_MAX_THD_SEL_Port_3 0x04e130f0 /* Port N, Byte-based Queue 4 Burst Size Configure Register */
-#define BCHP_SWITCH_CORE_PN_QUEUE4_MAX_THD_SEL_Port_4 0x04e13100 /* Port N, Byte-based Queue 4 Burst Size Configure Register */
-#define BCHP_SWITCH_CORE_PN_QUEUE4_MAX_THD_SEL_Port_5 0x04e13110 /* Port N, Byte-based Queue 4 Burst Size Configure Register */
-#define BCHP_SWITCH_CORE_P7_QUEUE4_MAX_THD_SEL 0x04e13130 /* Port 7, Byte-based Queue 4 Burst Size Configure Register */
-#define BCHP_SWITCH_CORE_IMP_QUEUE4_MAX_THD_SEL 0x04e13140 /* Port 8, Byte-based Queue 4 Burst Size Configure Register */
-#define BCHP_SWITCH_CORE_PN_QUEUE4_SHAPER_STS_Port_0 0x04e13180 /* Port N, Queue 4 Shaper Status Register */
-#define BCHP_SWITCH_CORE_PN_QUEUE4_SHAPER_STS_Port_1 0x04e13190 /* Port N, Queue 4 Shaper Status Register */
-#define BCHP_SWITCH_CORE_PN_QUEUE4_SHAPER_STS_Port_2 0x04e131a0 /* Port N, Queue 4 Shaper Status Register */
-#define BCHP_SWITCH_CORE_PN_QUEUE4_SHAPER_STS_Port_3 0x04e131b0 /* Port N, Queue 4 Shaper Status Register */
-#define BCHP_SWITCH_CORE_PN_QUEUE4_SHAPER_STS_Port_4 0x04e131c0 /* Port N, Queue 4 Shaper Status Register */
-#define BCHP_SWITCH_CORE_PN_QUEUE4_SHAPER_STS_Port_5 0x04e131d0 /* Port N, Queue 4 Shaper Status Register */
-#define BCHP_SWITCH_CORE_P7_QUEUE4_SHAPER_STS 0x04e131f0 /* Port 7, Queue 4 Shaper Status Register */
-#define BCHP_SWITCH_CORE_IMP_QUEUE4_SHAPER_STS 0x04e13200 /* Port 8, Queue 4 Shaper Status Register */
-#define BCHP_SWITCH_CORE_PN_QUEUE4_MAX_PACKET_REFRESH_Port_0 0x04e13240 /* Port N, Packet-based Queue 4 Shaping Rate Configure Register */
-#define BCHP_SWITCH_CORE_PN_QUEUE4_MAX_PACKET_REFRESH_Port_1 0x04e13250 /* Port N, Packet-based Queue 4 Shaping Rate Configure Register */
-#define BCHP_SWITCH_CORE_PN_QUEUE4_MAX_PACKET_REFRESH_Port_2 0x04e13260 /* Port N, Packet-based Queue 4 Shaping Rate Configure Register */
-#define BCHP_SWITCH_CORE_PN_QUEUE4_MAX_PACKET_REFRESH_Port_3 0x04e13270 /* Port N, Packet-based Queue 4 Shaping Rate Configure Register */
-#define BCHP_SWITCH_CORE_PN_QUEUE4_MAX_PACKET_REFRESH_Port_4 0x04e13280 /* Port N, Packet-based Queue 4 Shaping Rate Configure Register */
-#define BCHP_SWITCH_CORE_PN_QUEUE4_MAX_PACKET_REFRESH_Port_5 0x04e13290 /* Port N, Packet-based Queue 4 Shaping Rate Configure Register */
-#define BCHP_SWITCH_CORE_P7_QUEUE4_MAX_PACKET_REFRESH 0x04e132b0 /* Port 7, Packet-based Queue 4 Shaping Rate Configure Register */
-#define BCHP_SWITCH_CORE_IMP_QUEUE4_MAX_PACKET_REFRESH 0x04e132c0 /* Port 8, Packet-based Queue 4 Shaping Rate Configure Register */
-#define BCHP_SWITCH_CORE_EGRESS_SHAPER_Q4_CONFIG_REG_SPARE0 0x04e132e0 /* Spare 0 Register (Not2Release) */
-#define BCHP_SWITCH_CORE_EGRESS_SHAPER_Q4_CONFIG_REG_SPARE1 0x04e132f0 /* Spare 1 Register (Not2Release) */
-#define BCHP_SWITCH_CORE_PN_QUEUE4_MAX_PACKET_THD_SEL_Port_0 0x04e13300 /* Port N, Packet-based Queue 4 Burst Size Configure Register */
-#define BCHP_SWITCH_CORE_PN_QUEUE4_MAX_PACKET_THD_SEL_Port_1 0x04e13310 /* Port N, Packet-based Queue 4 Burst Size Configure Register */
-#define BCHP_SWITCH_CORE_PN_QUEUE4_MAX_PACKET_THD_SEL_Port_2 0x04e13320 /* Port N, Packet-based Queue 4 Burst Size Configure Register */
-#define BCHP_SWITCH_CORE_PN_QUEUE4_MAX_PACKET_THD_SEL_Port_3 0x04e13330 /* Port N, Packet-based Queue 4 Burst Size Configure Register */
-#define BCHP_SWITCH_CORE_PN_QUEUE4_MAX_PACKET_THD_SEL_Port_4 0x04e13340 /* Port N, Packet-based Queue 4 Burst Size Configure Register */
-#define BCHP_SWITCH_CORE_PN_QUEUE4_MAX_PACKET_THD_SEL_Port_5 0x04e13350 /* Port N, Packet-based Queue 4 Burst Size Configure Register */
-#define BCHP_SWITCH_CORE_P7_QUEUE4_MAX_PACKET_THD_SEL 0x04e13370 /* Port 7, Packet-based Queue 4 Burst Size Configure Register */
-#define BCHP_SWITCH_CORE_IMP_QUEUE4_MAX_PACKET_THD_SEL 0x04e13380 /* Port 8, Packet-based Queue 4 Burst Size Configure Register */
-#define BCHP_SWITCH_CORE_QUEUE4_AVB_SHAPING_MODE 0x04e13390 /* Queue 4 AVB Shaping Mode Control Register */
-#define BCHP_SWITCH_CORE_QUEUE4_SHAPER_ENABLE 0x04e13398 /* Queue 4 Shaper Enable Register */
-#define BCHP_SWITCH_CORE_QUEUE4_SHAPER_BUCKET_COUNT_SELECT 0x04e133a0 /* Queue 4 Bucket Count Select Register */
-#define BCHP_SWITCH_CORE_QUEUE4_SHAPER_BLOCKING 0x04e133a8 /* Queue 4 Shaper Blocking Control Register */
-#define BCHP_SWITCH_CORE_PN_QUEUE5_MAX_REFRESH_Port_0 0x04e13400 /* Port N, Byte-based Queue 5 Shaping Rate Configure Register */
-#define BCHP_SWITCH_CORE_PN_QUEUE5_MAX_REFRESH_Port_1 0x04e13410 /* Port N, Byte-based Queue 5 Shaping Rate Configure Register */
-#define BCHP_SWITCH_CORE_PN_QUEUE5_MAX_REFRESH_Port_2 0x04e13420 /* Port N, Byte-based Queue 5 Shaping Rate Configure Register */
-#define BCHP_SWITCH_CORE_PN_QUEUE5_MAX_REFRESH_Port_3 0x04e13430 /* Port N, Byte-based Queue 5 Shaping Rate Configure Register */
-#define BCHP_SWITCH_CORE_PN_QUEUE5_MAX_REFRESH_Port_4 0x04e13440 /* Port N, Byte-based Queue 5 Shaping Rate Configure Register */
-#define BCHP_SWITCH_CORE_PN_QUEUE5_MAX_REFRESH_Port_5 0x04e13450 /* Port N, Byte-based Queue 5 Shaping Rate Configure Register */
-#define BCHP_SWITCH_CORE_P7_QUEUE5_MAX_REFRESH 0x04e13470 /* Port 7, Byte-based Queue 5 Shaping Rate Configure Register */
-#define BCHP_SWITCH_CORE_IMP_QUEUE5_MAX_REFRESH 0x04e13480 /* Port 8, Byte-based Queue 5 Shaping Rate Configure Register */
-#define BCHP_SWITCH_CORE_PN_QUEUE5_MAX_THD_SEL_Port_0 0x04e134c0 /* Port N, Byte-based Queue 5 Burst Size Configure Register */
-#define BCHP_SWITCH_CORE_PN_QUEUE5_MAX_THD_SEL_Port_1 0x04e134d0 /* Port N, Byte-based Queue 5 Burst Size Configure Register */
-#define BCHP_SWITCH_CORE_PN_QUEUE5_MAX_THD_SEL_Port_2 0x04e134e0 /* Port N, Byte-based Queue 5 Burst Size Configure Register */
-#define BCHP_SWITCH_CORE_PN_QUEUE5_MAX_THD_SEL_Port_3 0x04e134f0 /* Port N, Byte-based Queue 5 Burst Size Configure Register */
-#define BCHP_SWITCH_CORE_PN_QUEUE5_MAX_THD_SEL_Port_4 0x04e13500 /* Port N, Byte-based Queue 5 Burst Size Configure Register */
-#define BCHP_SWITCH_CORE_PN_QUEUE5_MAX_THD_SEL_Port_5 0x04e13510 /* Port N, Byte-based Queue 5 Burst Size Configure Register */
-#define BCHP_SWITCH_CORE_P7_QUEUE5_MAX_THD_SEL 0x04e13530 /* Port 7, Byte-based Queue 5 Burst Size Configure Register */
-#define BCHP_SWITCH_CORE_IMP_QUEUE5_MAX_THD_SEL 0x04e13540 /* Port 8, Byte-based Queue 5 Burst Size Configure Register */
-#define BCHP_SWITCH_CORE_PN_QUEUE5_SHAPER_STS_Port_0 0x04e13580 /* Port N, Queue 5 Shaper Status Register */
-#define BCHP_SWITCH_CORE_PN_QUEUE5_SHAPER_STS_Port_1 0x04e13590 /* Port N, Queue 5 Shaper Status Register */
-#define BCHP_SWITCH_CORE_PN_QUEUE5_SHAPER_STS_Port_2 0x04e135a0 /* Port N, Queue 5 Shaper Status Register */
-#define BCHP_SWITCH_CORE_PN_QUEUE5_SHAPER_STS_Port_3 0x04e135b0 /* Port N, Queue 5 Shaper Status Register */
-#define BCHP_SWITCH_CORE_PN_QUEUE5_SHAPER_STS_Port_4 0x04e135c0 /* Port N, Queue 5 Shaper Status Register */
-#define BCHP_SWITCH_CORE_PN_QUEUE5_SHAPER_STS_Port_5 0x04e135d0 /* Port N, Queue 5 Shaper Status Register */
-#define BCHP_SWITCH_CORE_P7_QUEUE5_SHAPER_STS 0x04e135f0 /* Port 7, Queue 5 Shaper Status Register */
-#define BCHP_SWITCH_CORE_IMP_QUEUE5_SHAPER_STS 0x04e13600 /* Port 8, Queue 5 Shaper Status Register */
-#define BCHP_SWITCH_CORE_PN_QUEUE5_MAX_PACKET_REFRESH_Port_0 0x04e13640 /* Port N, Packet-based Queue 5 Shaping Rate Configure Register */
-#define BCHP_SWITCH_CORE_PN_QUEUE5_MAX_PACKET_REFRESH_Port_1 0x04e13650 /* Port N, Packet-based Queue 5 Shaping Rate Configure Register */
-#define BCHP_SWITCH_CORE_PN_QUEUE5_MAX_PACKET_REFRESH_Port_2 0x04e13660 /* Port N, Packet-based Queue 5 Shaping Rate Configure Register */
-#define BCHP_SWITCH_CORE_PN_QUEUE5_MAX_PACKET_REFRESH_Port_3 0x04e13670 /* Port N, Packet-based Queue 5 Shaping Rate Configure Register */
-#define BCHP_SWITCH_CORE_PN_QUEUE5_MAX_PACKET_REFRESH_Port_4 0x04e13680 /* Port N, Packet-based Queue 5 Shaping Rate Configure Register */
-#define BCHP_SWITCH_CORE_PN_QUEUE5_MAX_PACKET_REFRESH_Port_5 0x04e13690 /* Port N, Packet-based Queue 5 Shaping Rate Configure Register */
-#define BCHP_SWITCH_CORE_P7_QUEUE5_MAX_PACKET_REFRESH 0x04e136b0 /* Port 7, Packet-based Queue 5 Shaping Rate Configure Register */
-#define BCHP_SWITCH_CORE_IMP_QUEUE5_MAX_PACKET_REFRESH 0x04e136c0 /* Port 8, Packet-based Queue 5 Shaping Rate Configure Register */
-#define BCHP_SWITCH_CORE_EGRESS_SHAPER_Q5_CONFIG_REG_SPARE0 0x04e136e0 /* Spare 0 Register (Not2Release) */
-#define BCHP_SWITCH_CORE_EGRESS_SHAPER_Q5_CONFIG_REG_SPARE1 0x04e136f0 /* Spare 1 Register (Not2Release) */
-#define BCHP_SWITCH_CORE_PN_QUEUE5_MAX_PACKET_THD_SEL_Port_0 0x04e13700 /* Port N, Packet-based Queue 5 Burst Size Configure Register */
-#define BCHP_SWITCH_CORE_PN_QUEUE5_MAX_PACKET_THD_SEL_Port_1 0x04e13710 /* Port N, Packet-based Queue 5 Burst Size Configure Register */
-#define BCHP_SWITCH_CORE_PN_QUEUE5_MAX_PACKET_THD_SEL_Port_2 0x04e13720 /* Port N, Packet-based Queue 5 Burst Size Configure Register */
-#define BCHP_SWITCH_CORE_PN_QUEUE5_MAX_PACKET_THD_SEL_Port_3 0x04e13730 /* Port N, Packet-based Queue 5 Burst Size Configure Register */
-#define BCHP_SWITCH_CORE_PN_QUEUE5_MAX_PACKET_THD_SEL_Port_4 0x04e13740 /* Port N, Packet-based Queue 5 Burst Size Configure Register */
-#define BCHP_SWITCH_CORE_PN_QUEUE5_MAX_PACKET_THD_SEL_Port_5 0x04e13750 /* Port N, Packet-based Queue 5 Burst Size Configure Register */
-#define BCHP_SWITCH_CORE_P7_QUEUE5_MAX_PACKET_THD_SEL 0x04e13770 /* Port 7, Packet-based Queue 5 Burst Size Configure Register */
-#define BCHP_SWITCH_CORE_IMP_QUEUE5_MAX_PACKET_THD_SEL 0x04e13780 /* Port 8, Packet-based Queue 5 Burst Size Configure Register */
-#define BCHP_SWITCH_CORE_QUEUE5_AVB_SHAPING_MODE 0x04e13790 /* Queue 5 AVB Shaping Mode Control Register */
-#define BCHP_SWITCH_CORE_QUEUE5_SHAPER_ENABLE 0x04e13798 /* Queue 5 Shaper Enable Register */
-#define BCHP_SWITCH_CORE_QUEUE5_SHAPER_BUCKET_COUNT_SELECT 0x04e137a0 /* Queue 5 Bucket Count Select Register */
-#define BCHP_SWITCH_CORE_QUEUE5_SHAPER_BLOCKING 0x04e137a8 /* Queue 5 Shaper Blocking Control Register */
-#define BCHP_SWITCH_CORE_PN_QUEUE6_MAX_REFRESH_Port_0 0x04e13800 /* Port N, Byte-based Queue 6 Shaping Rate Configure Register */
-#define BCHP_SWITCH_CORE_PN_QUEUE6_MAX_REFRESH_Port_1 0x04e13810 /* Port N, Byte-based Queue 6 Shaping Rate Configure Register */
-#define BCHP_SWITCH_CORE_PN_QUEUE6_MAX_REFRESH_Port_2 0x04e13820 /* Port N, Byte-based Queue 6 Shaping Rate Configure Register */
-#define BCHP_SWITCH_CORE_PN_QUEUE6_MAX_REFRESH_Port_3 0x04e13830 /* Port N, Byte-based Queue 6 Shaping Rate Configure Register */
-#define BCHP_SWITCH_CORE_PN_QUEUE6_MAX_REFRESH_Port_4 0x04e13840 /* Port N, Byte-based Queue 6 Shaping Rate Configure Register */
-#define BCHP_SWITCH_CORE_PN_QUEUE6_MAX_REFRESH_Port_5 0x04e13850 /* Port N, Byte-based Queue 6 Shaping Rate Configure Register */
-#define BCHP_SWITCH_CORE_P7_QUEUE6_MAX_REFRESH 0x04e13870 /* Port 7, Byte-based Queue 6 Shaping Rate Configure Register */
-#define BCHP_SWITCH_CORE_IMP_QUEUE6_MAX_REFRESH 0x04e13880 /* Port 8, Byte-based Queue 6 Shaping Rate Configure Register */
-#define BCHP_SWITCH_CORE_PN_QUEUE6_MAX_THD_SEL_Port_0 0x04e138c0 /* Port N, Byte-based Queue 6 Burst Size Configure Register */
-#define BCHP_SWITCH_CORE_PN_QUEUE6_MAX_THD_SEL_Port_1 0x04e138d0 /* Port N, Byte-based Queue 6 Burst Size Configure Register */
-#define BCHP_SWITCH_CORE_PN_QUEUE6_MAX_THD_SEL_Port_2 0x04e138e0 /* Port N, Byte-based Queue 6 Burst Size Configure Register */
-#define BCHP_SWITCH_CORE_PN_QUEUE6_MAX_THD_SEL_Port_3 0x04e138f0 /* Port N, Byte-based Queue 6 Burst Size Configure Register */
-#define BCHP_SWITCH_CORE_PN_QUEUE6_MAX_THD_SEL_Port_4 0x04e13900 /* Port N, Byte-based Queue 6 Burst Size Configure Register */
-#define BCHP_SWITCH_CORE_PN_QUEUE6_MAX_THD_SEL_Port_5 0x04e13910 /* Port N, Byte-based Queue 6 Burst Size Configure Register */
-#define BCHP_SWITCH_CORE_P7_QUEUE6_MAX_THD_SEL 0x04e13930 /* Port 7, Byte-based Queue 6 Burst Size Configure Register */
-#define BCHP_SWITCH_CORE_IMP_QUEUE6_MAX_THD_SEL 0x04e13940 /* Port 8, Byte-based Queue 6 Burst Size Configure Register */
-#define BCHP_SWITCH_CORE_PN_QUEUE6_SHAPER_STS_Port_0 0x04e13980 /* Port N, Queue 6 Shaper Status Register */
-#define BCHP_SWITCH_CORE_PN_QUEUE6_SHAPER_STS_Port_1 0x04e13990 /* Port N, Queue 6 Shaper Status Register */
-#define BCHP_SWITCH_CORE_PN_QUEUE6_SHAPER_STS_Port_2 0x04e139a0 /* Port N, Queue 6 Shaper Status Register */
-#define BCHP_SWITCH_CORE_PN_QUEUE6_SHAPER_STS_Port_3 0x04e139b0 /* Port N, Queue 6 Shaper Status Register */
-#define BCHP_SWITCH_CORE_PN_QUEUE6_SHAPER_STS_Port_4 0x04e139c0 /* Port N, Queue 6 Shaper Status Register */
-#define BCHP_SWITCH_CORE_PN_QUEUE6_SHAPER_STS_Port_5 0x04e139d0 /* Port N, Queue 6 Shaper Status Register */
-#define BCHP_SWITCH_CORE_P7_QUEUE6_SHAPER_STS 0x04e139f0 /* Port 7, Queue 6 Shaper Status Register */
-#define BCHP_SWITCH_CORE_IMP_QUEUE6_SHAPER_STS 0x04e13a00 /* Port 8, Queue 6 Shaper Status Register */
-#define BCHP_SWITCH_CORE_PN_QUEUE6_MAX_PACKET_REFRESH_Port_0 0x04e13a40 /* Port N, Packet-based Queue 6 Shaping Rate Configure Register */
-#define BCHP_SWITCH_CORE_PN_QUEUE6_MAX_PACKET_REFRESH_Port_1 0x04e13a50 /* Port N, Packet-based Queue 6 Shaping Rate Configure Register */
-#define BCHP_SWITCH_CORE_PN_QUEUE6_MAX_PACKET_REFRESH_Port_2 0x04e13a60 /* Port N, Packet-based Queue 6 Shaping Rate Configure Register */
-#define BCHP_SWITCH_CORE_PN_QUEUE6_MAX_PACKET_REFRESH_Port_3 0x04e13a70 /* Port N, Packet-based Queue 6 Shaping Rate Configure Register */
-#define BCHP_SWITCH_CORE_PN_QUEUE6_MAX_PACKET_REFRESH_Port_4 0x04e13a80 /* Port N, Packet-based Queue 6 Shaping Rate Configure Register */
-#define BCHP_SWITCH_CORE_PN_QUEUE6_MAX_PACKET_REFRESH_Port_5 0x04e13a90 /* Port N, Packet-based Queue 6 Shaping Rate Configure Register */
-#define BCHP_SWITCH_CORE_P7_QUEUE6_MAX_PACKET_REFRESH 0x04e13ab0 /* Port 7, Packet-based Queue 6 Shaping Rate Configure Register */
-#define BCHP_SWITCH_CORE_IMP_QUEUE6_MAX_PACKET_REFRESH 0x04e13ac0 /* Port 8, Packet-based Queue 6 Shaping Rate Configure Register */
-#define BCHP_SWITCH_CORE_EGRESS_SHAPER_Q6_CONFIG_REG_SPARE0 0x04e13ae0 /* Spare 0 Register (Not2Release) */
-#define BCHP_SWITCH_CORE_EGRESS_SHAPER_Q6_CONFIG_REG_SPARE1 0x04e13af0 /* Spare 1 Register (Not2Release) */
-#define BCHP_SWITCH_CORE_PN_QUEUE6_MAX_PACKET_THD_SEL_Port_0 0x04e13b00 /* Port N, Packet-based Queue 6 Burst Size Configure Register */
-#define BCHP_SWITCH_CORE_PN_QUEUE6_MAX_PACKET_THD_SEL_Port_1 0x04e13b10 /* Port N, Packet-based Queue 6 Burst Size Configure Register */
-#define BCHP_SWITCH_CORE_PN_QUEUE6_MAX_PACKET_THD_SEL_Port_2 0x04e13b20 /* Port N, Packet-based Queue 6 Burst Size Configure Register */
-#define BCHP_SWITCH_CORE_PN_QUEUE6_MAX_PACKET_THD_SEL_Port_3 0x04e13b30 /* Port N, Packet-based Queue 6 Burst Size Configure Register */
-#define BCHP_SWITCH_CORE_PN_QUEUE6_MAX_PACKET_THD_SEL_Port_4 0x04e13b40 /* Port N, Packet-based Queue 6 Burst Size Configure Register */
-#define BCHP_SWITCH_CORE_PN_QUEUE6_MAX_PACKET_THD_SEL_Port_5 0x04e13b50 /* Port N, Packet-based Queue 6 Burst Size Configure Register */
-#define BCHP_SWITCH_CORE_P7_QUEUE6_MAX_PACKET_THD_SEL 0x04e13b70 /* Port 7, Packet-based Queue 6 Burst Size Configure Register */
-#define BCHP_SWITCH_CORE_IMP_QUEUE6_MAX_PACKET_THD_SEL 0x04e13b80 /* Port 8, Packet-based Queue 6 Burst Size Configure Register */
-#define BCHP_SWITCH_CORE_QUEUE6_AVB_SHAPING_MODE 0x04e13b90 /* Queue 6 AVB Shaping Mode Control Register */
-#define BCHP_SWITCH_CORE_QUEUE6_SHAPER_ENABLE 0x04e13b98 /* Queue 6 Shaper Enable Register */
-#define BCHP_SWITCH_CORE_QUEUE6_SHAPER_BUCKET_COUNT_SELECT 0x04e13ba0 /* Queue 6 Bucket Count Select Register */
-#define BCHP_SWITCH_CORE_QUEUE6_SHAPER_BLOCKING 0x04e13ba8 /* Queue 6 Shaper Blocking Control Register */
-#define BCHP_SWITCH_CORE_PN_QUEUE7_MAX_REFRESH_Port_0 0x04e13c00 /* Port N, Byte-based Queue 7 Shaping Rate Configure Register */
-#define BCHP_SWITCH_CORE_PN_QUEUE7_MAX_REFRESH_Port_1 0x04e13c10 /* Port N, Byte-based Queue 7 Shaping Rate Configure Register */
-#define BCHP_SWITCH_CORE_PN_QUEUE7_MAX_REFRESH_Port_2 0x04e13c20 /* Port N, Byte-based Queue 7 Shaping Rate Configure Register */
-#define BCHP_SWITCH_CORE_PN_QUEUE7_MAX_REFRESH_Port_3 0x04e13c30 /* Port N, Byte-based Queue 7 Shaping Rate Configure Register */
-#define BCHP_SWITCH_CORE_PN_QUEUE7_MAX_REFRESH_Port_4 0x04e13c40 /* Port N, Byte-based Queue 7 Shaping Rate Configure Register */
-#define BCHP_SWITCH_CORE_PN_QUEUE7_MAX_REFRESH_Port_5 0x04e13c50 /* Port N, Byte-based Queue 7 Shaping Rate Configure Register */
-#define BCHP_SWITCH_CORE_P7_QUEUE7_MAX_REFRESH 0x04e13c70 /* Port 7, Byte-based Queue 7 Shaping Rate Configure Register */
-#define BCHP_SWITCH_CORE_IMP_QUEUE7_MAX_REFRESH 0x04e13c80 /* Port 8, Byte-based Queue 7 Shaping Rate Configure Register */
-#define BCHP_SWITCH_CORE_PN_QUEUE7_MAX_THD_SEL_Port_0 0x04e13cc0 /* Port N, Byte-based Queue 7 Burst Size Configure Register */
-#define BCHP_SWITCH_CORE_PN_QUEUE7_MAX_THD_SEL_Port_1 0x04e13cd0 /* Port N, Byte-based Queue 7 Burst Size Configure Register */
-#define BCHP_SWITCH_CORE_PN_QUEUE7_MAX_THD_SEL_Port_2 0x04e13ce0 /* Port N, Byte-based Queue 7 Burst Size Configure Register */
-#define BCHP_SWITCH_CORE_PN_QUEUE7_MAX_THD_SEL_Port_3 0x04e13cf0 /* Port N, Byte-based Queue 7 Burst Size Configure Register */
-#define BCHP_SWITCH_CORE_PN_QUEUE7_MAX_THD_SEL_Port_4 0x04e13d00 /* Port N, Byte-based Queue 7 Burst Size Configure Register */
-#define BCHP_SWITCH_CORE_PN_QUEUE7_MAX_THD_SEL_Port_5 0x04e13d10 /* Port N, Byte-based Queue 7 Burst Size Configure Register */
-#define BCHP_SWITCH_CORE_P7_QUEUE7_MAX_THD_SEL 0x04e13d30 /* Port 7, Byte-based Queue 7 Burst Size Configure Register */
-#define BCHP_SWITCH_CORE_IMP_QUEUE7_MAX_THD_SEL 0x04e13d40 /* Port 8, Byte-based Queue 7 Burst Size Configure Register */
-#define BCHP_SWITCH_CORE_PN_QUEUE7_SHAPER_STS_Port_0 0x04e13d80 /* Port N, Queue 7 Shaper Status Register */
-#define BCHP_SWITCH_CORE_PN_QUEUE7_SHAPER_STS_Port_1 0x04e13d90 /* Port N, Queue 7 Shaper Status Register */
-#define BCHP_SWITCH_CORE_PN_QUEUE7_SHAPER_STS_Port_2 0x04e13da0 /* Port N, Queue 7 Shaper Status Register */
-#define BCHP_SWITCH_CORE_PN_QUEUE7_SHAPER_STS_Port_3 0x04e13db0 /* Port N, Queue 7 Shaper Status Register */
-#define BCHP_SWITCH_CORE_PN_QUEUE7_SHAPER_STS_Port_4 0x04e13dc0 /* Port N, Queue 7 Shaper Status Register */
-#define BCHP_SWITCH_CORE_PN_QUEUE7_SHAPER_STS_Port_5 0x04e13dd0 /* Port N, Queue 7 Shaper Status Register */
-#define BCHP_SWITCH_CORE_P7_QUEUE7_SHAPER_STS 0x04e13df0 /* Port 7, Queue 7 Shaper Status Register */
-#define BCHP_SWITCH_CORE_IMP_QUEUE7_SHAPER_STS 0x04e13e00 /* Port 8, Queue 7 Shaper Status Register */
-#define BCHP_SWITCH_CORE_PN_QUEUE7_MAX_PACKET_REFRESH_Port_0 0x04e13e40 /* Port N, Packet-based Queue 7 Shaping Rate Configure Register */
-#define BCHP_SWITCH_CORE_PN_QUEUE7_MAX_PACKET_REFRESH_Port_1 0x04e13e50 /* Port N, Packet-based Queue 7 Shaping Rate Configure Register */
-#define BCHP_SWITCH_CORE_PN_QUEUE7_MAX_PACKET_REFRESH_Port_2 0x04e13e60 /* Port N, Packet-based Queue 7 Shaping Rate Configure Register */
-#define BCHP_SWITCH_CORE_PN_QUEUE7_MAX_PACKET_REFRESH_Port_3 0x04e13e70 /* Port N, Packet-based Queue 7 Shaping Rate Configure Register */
-#define BCHP_SWITCH_CORE_PN_QUEUE7_MAX_PACKET_REFRESH_Port_4 0x04e13e80 /* Port N, Packet-based Queue 7 Shaping Rate Configure Register */
-#define BCHP_SWITCH_CORE_PN_QUEUE7_MAX_PACKET_REFRESH_Port_5 0x04e13e90 /* Port N, Packet-based Queue 7 Shaping Rate Configure Register */
-#define BCHP_SWITCH_CORE_P7_QUEUE7_MAX_PACKET_REFRESH 0x04e13eb0 /* Port 7, Packet-based Queue 7 Shaping Rate Configure Register */
-#define BCHP_SWITCH_CORE_IMP_QUEUE7_MAX_PACKET_REFRESH 0x04e13ec0 /* Port 8, Packet-based Queue 7 Shaping Rate Configure Register */
-#define BCHP_SWITCH_CORE_EGRESS_SHAPER_Q7_CONFIG_REG_SPARE0 0x04e13ee0 /* Spare 0 Register (Not2Release) */
-#define BCHP_SWITCH_CORE_EGRESS_SHAPER_Q7_CONFIG_REG_SPARE1 0x04e13ef0 /* Spare 1 Register (Not2Release) */
-#define BCHP_SWITCH_CORE_PN_QUEUE7_MAX_PACKET_THD_SEL_Port_0 0x04e13f00 /* Port N, Packet-based Queue 7 Burst Size Configure Register */
-#define BCHP_SWITCH_CORE_PN_QUEUE7_MAX_PACKET_THD_SEL_Port_1 0x04e13f10 /* Port N, Packet-based Queue 7 Burst Size Configure Register */
-#define BCHP_SWITCH_CORE_PN_QUEUE7_MAX_PACKET_THD_SEL_Port_2 0x04e13f20 /* Port N, Packet-based Queue 7 Burst Size Configure Register */
-#define BCHP_SWITCH_CORE_PN_QUEUE7_MAX_PACKET_THD_SEL_Port_3 0x04e13f30 /* Port N, Packet-based Queue 7 Burst Size Configure Register */
-#define BCHP_SWITCH_CORE_PN_QUEUE7_MAX_PACKET_THD_SEL_Port_4 0x04e13f40 /* Port N, Packet-based Queue 7 Burst Size Configure Register */
-#define BCHP_SWITCH_CORE_PN_QUEUE7_MAX_PACKET_THD_SEL_Port_5 0x04e13f50 /* Port N, Packet-based Queue 7 Burst Size Configure Register */
-#define BCHP_SWITCH_CORE_P7_QUEUE7_MAX_PACKET_THD_SEL 0x04e13f70 /* Port 7, Packet-based Queue 7 Burst Size Configure Register */
-#define BCHP_SWITCH_CORE_IMP_QUEUE7_MAX_PACKET_THD_SEL 0x04e13f80 /* Port 8, Packet-based Queue 7 Burst Size Configure Register */
-#define BCHP_SWITCH_CORE_QUEUE7_AVB_SHAPING_MODE 0x04e13f90 /* Queue 7 AVB Shaping Mode Control Register */
-#define BCHP_SWITCH_CORE_QUEUE7_SHAPER_ENABLE 0x04e13f98 /* Queue 7 Shaper Enable Register */
-#define BCHP_SWITCH_CORE_QUEUE7_SHAPER_BUCKET_COUNT_SELECT 0x04e13fa0 /* Queue 7 Bucket Count Select Register */
-#define BCHP_SWITCH_CORE_QUEUE7_SHAPER_BLOCKING 0x04e13fa8 /* Queue 7 Shaper Blocking Control Register */
-#define BCHP_SWITCH_CORE_MIB_SNAPSHOT_CTL 0x04e1c000 /* MIB Snapshot Control Register */
-#define BCHP_SWITCH_CORE_S_TxOctets 0x04e1c400 /* Tx Octets */
-#define BCHP_SWITCH_CORE_S_TxDropPkts 0x04e1c420 /* Tx Drop Packet Counter */
-#define BCHP_SWITCH_CORE_S_TxQPKTQ0 0x04e1c430 /* Tx Q0 Packet Counter */
-#define BCHP_SWITCH_CORE_S_TxBroadcastPkts 0x04e1c440 /* Tx Broadcast Packet Counter */
-#define BCHP_SWITCH_CORE_S_TxMulticastPkts 0x04e1c450 /* Tx Multicast Packet Counter */
-#define BCHP_SWITCH_CORE_S_TxUnicastPkts 0x04e1c460 /* Tx Unicast Packet Counter */
-#define BCHP_SWITCH_CORE_S_TxCollisions 0x04e1c470 /* Tx Collision Counter */
-#define BCHP_SWITCH_CORE_S_TxSingleCollision 0x04e1c480 /* Tx Single Collision Counter */
-#define BCHP_SWITCH_CORE_S_TxMultipleCollision 0x04e1c490 /* Tx Multiple collsion Counter */
-#define BCHP_SWITCH_CORE_S_TxDeferredTransmit 0x04e1c4a0 /* Tx Deferred Transmit Counter */
-#define BCHP_SWITCH_CORE_S_TxLateCollision 0x04e1c4b0 /* Tx Late Collision Counter */
-#define BCHP_SWITCH_CORE_S_TxExcessiveCollision 0x04e1c4c0 /* Tx Excessive Collision Counter */
-#define BCHP_SWITCH_CORE_S_TxFrameInDisc 0x04e1c4d0 /* Tx Fram IN Disc Counter */
-#define BCHP_SWITCH_CORE_S_TxPausePkts 0x04e1c4e0 /* Tx Pause Packet Counter */
-#define BCHP_SWITCH_CORE_S_TxQPKTQ1 0x04e1c4f0 /* Tx Q1 Packet Counter */
-#define BCHP_SWITCH_CORE_S_TxQPKTQ2 0x04e1c500 /* Tx Q2 Packet Counter */
-#define BCHP_SWITCH_CORE_S_TxQPKTQ3 0x04e1c510 /* Tx Q3 Packet Counter */
-#define BCHP_SWITCH_CORE_S_TxQPKTQ4 0x04e1c520 /* Tx Q4 Packet Counter */
-#define BCHP_SWITCH_CORE_S_TxQPKTQ5 0x04e1c530 /* Tx Q5 Packet Counter */
-#define BCHP_SWITCH_CORE_S_RxOctets 0x04e1c540 /* Rx Packet Octets Counter */
-#define BCHP_SWITCH_CORE_S_RxUndersizePkts 0x04e1c560 /* Rx Under Size Packet Octets Counter */
-#define BCHP_SWITCH_CORE_S_RxPausePkts 0x04e1c570 /* Rx Pause Packet Counter */
-#define BCHP_SWITCH_CORE_S_RxPkts64Octets 0x04e1c580 /* Rx 64 Bytes Octets Counter */
-#define BCHP_SWITCH_CORE_S_RxPkts65to127Octets 0x04e1c590 /* Rx 65 to 127 Bytes Octets Counter */
-#define BCHP_SWITCH_CORE_S_RxPkts128to255Octets 0x04e1c5a0 /* Rx 128 to 255 Bytes Octets Counter */
-#define BCHP_SWITCH_CORE_S_RxPkts256to511Octets 0x04e1c5b0 /* Rx 256 to 511 Bytes Octets Counter */
-#define BCHP_SWITCH_CORE_S_RxPkts512to1023Octets 0x04e1c5c0 /* Rx 512 to 1023 Bytes Octets Counter */
-#define BCHP_SWITCH_CORE_S_RxPkts1024toMaxPktOctets 0x04e1c5d0 /* Rx 1024 to MaxPkt Bytes Octets Counter */
-#define BCHP_SWITCH_CORE_S_RxOversizePkts 0x04e1c5e0 /* Rx Over Size Packet Counter */
-#define BCHP_SWITCH_CORE_S_RxJabbers 0x04e1c5f0 /* Rx Jabber Packet Counter */
-#define BCHP_SWITCH_CORE_S_RxAlignmentErrors 0x04e1c600 /* Rx Alignment Error Counter */
-#define BCHP_SWITCH_CORE_S_RxFCSErrors 0x04e1c610 /* Rx FCS Error Counter */
-#define BCHP_SWITCH_CORE_S_RxGoodOctets 0x04e1c620 /* Rx Good Packet Octet Counter */
-#define BCHP_SWITCH_CORE_S_RxDropPkts 0x04e1c640 /* Rx Drop Packet Counter */
-#define BCHP_SWITCH_CORE_S_RxUnicastPkts 0x04e1c650 /* Rx Unicast Packet Counter */
-#define BCHP_SWITCH_CORE_S_RxMulticastPkts 0x04e1c660 /* Rx Multicast Packet Counter */
-#define BCHP_SWITCH_CORE_S_RxBroadcastPkts 0x04e1c670 /* Rx Broadcast Packet Counter */
-#define BCHP_SWITCH_CORE_S_RxSAChanges 0x04e1c680 /* Rx SA Change Counter */
-#define BCHP_SWITCH_CORE_S_RxFragments 0x04e1c690 /* Rx Fragment Counter */
-#define BCHP_SWITCH_CORE_S_RxJumboPkt 0x04e1c6a0 /* Jumbo Packet Counter */
-#define BCHP_SWITCH_CORE_S_RxSymblErr 0x04e1c6b0 /* Rx Symbol Error Counter */
-#define BCHP_SWITCH_CORE_S_InRangeErrCount 0x04e1c6c0 /* InRangeErrCount Counter */
-#define BCHP_SWITCH_CORE_S_OutRangeErrCount 0x04e1c6d0 /* OutRangeErrCount Counter */
-#define BCHP_SWITCH_CORE_S_EEE_LPI_EVENT 0x04e1c6e0 /* EEE Low-Power Idle Event Registers */
-#define BCHP_SWITCH_CORE_S_EEE_LPI_DURATION 0x04e1c6f0 /* EEE Low-Power Idle Duration Registers */
-#define BCHP_SWITCH_CORE_S_RxDiscard 0x04e1c700 /* Rx Discard Counter */
-#define BCHP_SWITCH_CORE_S_TxQPKTQ6 0x04e1c720 /* Tx Q6 Packet Counter */
-#define BCHP_SWITCH_CORE_S_TxQPKTQ7 0x04e1c730 /* Tx Q7 Packet Counter */
-#define BCHP_SWITCH_CORE_S_TxPkts64Octets 0x04e1c740 /* Tx 64 Bytes Octets Counter */
-#define BCHP_SWITCH_CORE_S_TxPkts65to127Octets 0x04e1c750 /* Tx 65 to 127 Bytes Octets Counter */
-#define BCHP_SWITCH_CORE_S_TxPkts128to255Octets 0x04e1c760 /* Tx 128 to 255 Bytes Octets Counter */
-#define BCHP_SWITCH_CORE_S_TxPkts256to511Octets 0x04e1c770 /* Tx 256 to 511 Bytes Octets Counter */
-#define BCHP_SWITCH_CORE_S_TxPkts512to1023Octets 0x04e1c780 /* Tx 512 to 1023 Bytes Octets Counter */
-#define BCHP_SWITCH_CORE_S_TxPkts1024toMaxPktOctets 0x04e1c790 /* Tx 1024 to MaxPkt Bytes Octets Counter */
-#define BCHP_SWITCH_CORE_LPDET_CFG 0x04e1c800 /* Loop Detection Configuration RegistersNot2Release */
-#define BCHP_SWITCH_CORE_DF_TIMER 0x04e1c808 /* Discovery Frame Timer RegistersNot2Release */
-#define BCHP_SWITCH_CORE_LED_PORTMAP 0x04e1c80c /* LED Waming Portmap RegistersNot2Release */
-#define BCHP_SWITCH_CORE_MODULE_ID0 0x04e1c814 /* Module ID 0 RegistersNot2Release */
-#define BCHP_SWITCH_CORE_MODULE_ID1 0x04e1c82c /* Module ID 1 RegistersNot2Release */
-#define BCHP_SWITCH_CORE_LPDET_SA 0x04e1c844 /* Loop Detect Frame SA RegistersNot2Release */
-#define BCHP_SWITCH_CORE_LPDET_REG_SPARE0 0x04e1c880 /* Spare 0 Register (Not2Release)Not2Release */
-#define BCHP_SWITCH_CORE_LPDET_REG_SPARE1 0x04e1c890 /* Spare 1 Register (Not2Release)Not2Release */
-#define BCHP_SWITCH_CORE_BPM_CTRL 0x04e1cc00 /* BPM Power Switching Control RegisterNot2Release */
-#define BCHP_SWITCH_CORE_BPM_PSM_OVR_CTRL 0x04e1cc04 /* BPM Power Switching SW Override RegisterNot2Release */
-#define BCHP_SWITCH_CORE_BPM_PSM_TIME_CFG 0x04e1cc08 /* PSM_VDD Timing Parameter Configuration RegisterNot2Release */
-#define BCHP_SWITCH_CORE_BPM_PSM_THD_CFG 0x04e1cc10 /* PSM_VDD Switching Threshold Configuration RegisterNot2Release */
-#define BCHP_SWITCH_CORE_ROW_VMASK_OVR_CTRL 0x04e1cc20 /* BUFCON Row Status Valid Mask SW Override Control RegisterNot2Release */
-#define BCHP_SWITCH_CORE_BPM_STS 0x04e1cc30 /* BPM Status RegisterNot2Release */
-#define BCHP_SWITCH_CORE_BPM_PDA_OVR_CTRL 0x04e1cc40 /* BPM PDA Switching SW Override Control RegisterNot2Release */
-#define BCHP_SWITCH_CORE_PDA_TIMEOUT_CFG 0x04e1cc48 /* BPM PDA Switching Timeout Counter RegisterNot2Release */
-#define BCHP_SWITCH_CORE_PDA_SETUP_TIME_CFG 0x04e1cc50 /* BPM PDA Switching Setup Time RegisterNot2Release */
-#define BCHP_SWITCH_CORE_PDA_HOLD_TIME_CFG 0x04e1cc58 /* BPM PDA Switching Hold Time RegisterNot2Release */
-#define BCHP_SWITCH_CORE_PBB_VBUFCNT_N_Port_0 0x04e1cc60 /* Packet Buffer Block N Valid Buffer Count RegisterNot2Release */
-#define BCHP_SWITCH_CORE_PBB_VBUFCNT_N_Port_1 0x04e1cc68 /* Packet Buffer Block N Valid Buffer Count RegisterNot2Release */
-#define BCHP_SWITCH_CORE_PBB_VBUFCNT_N_Port_2 0x04e1cc70 /* Packet Buffer Block N Valid Buffer Count RegisterNot2Release */
-#define BCHP_SWITCH_CORE_RCY_TIME_CFG 0x04e1cc78 /* Recycling Check Pulse Period Counter RegisterNot2Release */
-#define BCHP_SWITCH_CORE_PBB_PWRDWN_MON_CTRL 0x04e1cc80 /* PBB Powerdown Monitor Control RegisterNot2Release */
-#define BCHP_SWITCH_CORE_PBB_PWRDWN_MON_N_Port_0 0x04e1cca0 /* PBB Powerdown Time Monitor N RegisterNot2Release */
-#define BCHP_SWITCH_CORE_PBB_PWRDWN_MON_N_Port_1 0x04e1ccc0 /* PBB Powerdown Time Monitor N RegisterNot2Release */
-#define BCHP_SWITCH_CORE_PBB_PWRDWN_MON_N_Port_2 0x04e1cce0 /* PBB Powerdown Time Monitor N RegisterNot2Release */
-#define BCHP_SWITCH_CORE_BPM_REG_SPARE0 0x04e1cd80 /* Spare 0 Register (Not2Release)Not2Release */
-#define BCHP_SWITCH_CORE_BPM_REG_SPARE1 0x04e1cd90 /* Spare 1 Register (Not2Release)Not2Release */
-#define BCHP_SWITCH_CORE_TRREG_CTRL0 0x04e24400 /* Traffic Remarking Control 0 Register */
-#define BCHP_SWITCH_CORE_TRREG_CTRL1 0x04e24410 /* Traffic Remarking Control 1 Register */
-#define BCHP_SWITCH_CORE_TRREG_CTRL2 0x04e24420 /* Traffic Remarking Control 2 Register */
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2PCP_MAP_Port_0 0x04e24440 /* Port N, Egress TC to PCP mapping Register */
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2PCP_MAP_Port_1 0x04e24460 /* Port N, Egress TC to PCP mapping Register */
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2PCP_MAP_Port_2 0x04e24480 /* Port N, Egress TC to PCP mapping Register */
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2PCP_MAP_Port_3 0x04e244a0 /* Port N, Egress TC to PCP mapping Register */
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2PCP_MAP_Port_4 0x04e244c0 /* Port N, Egress TC to PCP mapping Register */
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2PCP_MAP_Port_5 0x04e244e0 /* Port N, Egress TC to PCP mapping Register */
-#define BCHP_SWITCH_CORE_P7_EGRESS_PKT_TC2PCP_MAP 0x04e24520 /* Port 7, Egress TC to PCP mapping Register */
-#define BCHP_SWITCH_CORE_IMP_EGRESS_PKT_TC2PCP_MAP 0x04e24540 /* Port 8, Egress TC to PCP mapping Register */
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_0 0x04e24580 /* Port N, Egress TC to CPCP mapping Register */
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_1 0x04e245a0 /* Port N, Egress TC to CPCP mapping Register */
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_2 0x04e245c0 /* Port N, Egress TC to CPCP mapping Register */
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_3 0x04e245e0 /* Port N, Egress TC to CPCP mapping Register */
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_4 0x04e24600 /* Port N, Egress TC to CPCP mapping Register */
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_5 0x04e24620 /* Port N, Egress TC to CPCP mapping Register */
-#define BCHP_SWITCH_CORE_P7_EGRESS_PKT_TC2CPCP_MAP 0x04e24660 /* Port 7, Egress TC to CPCP mapping Register */
-#define BCHP_SWITCH_CORE_IMP_EGRESS_PKT_TC2CPCP_MAP 0x04e24680 /* Port 8, Egress TC to CPCP mapping Register */
-#define BCHP_SWITCH_CORE_TRREG_REG_SPARE0 0x04e246c0 /* Spare 0 Register (Not2Release) */
-#define BCHP_SWITCH_CORE_TRREG_REG_SPARE1 0x04e246d0 /* Spare 1 Register (Not2Release) */
-#define BCHP_SWITCH_CORE_EEE_EN_CTRL 0x04e24800 /* EEE Enable Control Registers */
-#define BCHP_SWITCH_CORE_EEE_LPI_ASSERT 0x04e24808 /* EEE Low Power Assert Status Registers */
-#define BCHP_SWITCH_CORE_EEE_LPI_INDICATE 0x04e24810 /* EEE Low Power Indicate Status Registers */
-#define BCHP_SWITCH_CORE_EEE_RX_IDLE_SYMBOL 0x04e24818 /* EEE Receiving Idle Symbols Status Registers */
-#define BCHP_SWITCH_CORE_EEE_LPI_SYMBOL_TX_DISABLE 0x04e24820 /* EEE LPI Symbol Transmit Disable Registers(Not2Release) */
-#define BCHP_SWITCH_CORE_EEE_PIPELINE_TIMER 0x04e24830 /* EEE Pipeline Delay Timer Registers */
-#define BCHP_SWITCH_CORE_EEE_SLEEP_TIMER_G_Port_0 0x04e24840 /* EEE Port N Sleep Delay Timer - 1G Registers */
-#define BCHP_SWITCH_CORE_EEE_SLEEP_TIMER_G_Port_1 0x04e24850 /* EEE Port N Sleep Delay Timer - 1G Registers */
-#define BCHP_SWITCH_CORE_EEE_SLEEP_TIMER_G_Port_2 0x04e24860 /* EEE Port N Sleep Delay Timer - 1G Registers */
-#define BCHP_SWITCH_CORE_EEE_SLEEP_TIMER_G_Port_3 0x04e24870 /* EEE Port N Sleep Delay Timer - 1G Registers */
-#define BCHP_SWITCH_CORE_EEE_SLEEP_TIMER_G_Port_4 0x04e24880 /* EEE Port N Sleep Delay Timer - 1G Registers */
-#define BCHP_SWITCH_CORE_EEE_SLEEP_TIMER_G_Port_5 0x04e24890 /* EEE Port N Sleep Delay Timer - 1G Registers */
-#define BCHP_SWITCH_CORE_EEE_SLEEP_TIMER_G_P7 0x04e248b0 /* EEE Port 7 Sleep Delay Timer - 1G Registers */
-#define BCHP_SWITCH_CORE_EEE_SLEEP_TIMER_G_IMP 0x04e248c0 /* EEE Port 8(IMP) Sleep Delay Timer - 1G Registers */
-#define BCHP_SWITCH_CORE_EEE_SLEEP_TIMER_H_Port_0 0x04e248d0 /* EEE Port N Sleep Delay Timer - 100M Registers */
-#define BCHP_SWITCH_CORE_EEE_SLEEP_TIMER_H_Port_1 0x04e248e0 /* EEE Port N Sleep Delay Timer - 100M Registers */
-#define BCHP_SWITCH_CORE_EEE_SLEEP_TIMER_H_Port_2 0x04e248f0 /* EEE Port N Sleep Delay Timer - 100M Registers */
-#define BCHP_SWITCH_CORE_EEE_SLEEP_TIMER_H_Port_3 0x04e24900 /* EEE Port N Sleep Delay Timer - 100M Registers */
-#define BCHP_SWITCH_CORE_EEE_SLEEP_TIMER_H_Port_4 0x04e24910 /* EEE Port N Sleep Delay Timer - 100M Registers */
-#define BCHP_SWITCH_CORE_EEE_SLEEP_TIMER_H_Port_5 0x04e24920 /* EEE Port N Sleep Delay Timer - 100M Registers */
-#define BCHP_SWITCH_CORE_EEE_SLEEP_TIMER_H_P7 0x04e24940 /* EEE Port 7 Sleep Delay Timer - 100M Registers */
-#define BCHP_SWITCH_CORE_EEE_SLEEP_TIMER_H_IMP 0x04e24950 /* EEE Port 8(IMP) Sleep Delay Timer - 100M Registers */
-#define BCHP_SWITCH_CORE_EEE_MIN_LP_TIMER_G_Port_0 0x04e24960 /* EEE Port Minimum Low-Power Duration Timer - 1G Registers */
-#define BCHP_SWITCH_CORE_EEE_MIN_LP_TIMER_G_Port_1 0x04e24970 /* EEE Port Minimum Low-Power Duration Timer - 1G Registers */
-#define BCHP_SWITCH_CORE_EEE_MIN_LP_TIMER_G_Port_2 0x04e24980 /* EEE Port Minimum Low-Power Duration Timer - 1G Registers */
-#define BCHP_SWITCH_CORE_EEE_MIN_LP_TIMER_G_Port_3 0x04e24990 /* EEE Port Minimum Low-Power Duration Timer - 1G Registers */
-#define BCHP_SWITCH_CORE_EEE_MIN_LP_TIMER_G_Port_4 0x04e249a0 /* EEE Port Minimum Low-Power Duration Timer - 1G Registers */
-#define BCHP_SWITCH_CORE_EEE_MIN_LP_TIMER_G_Port_5 0x04e249b0 /* EEE Port Minimum Low-Power Duration Timer - 1G Registers */
-#define BCHP_SWITCH_CORE_EEE_MIN_LP_TIMER_G_P7 0x04e249d0 /* EEE Port 7 Minimum Low-Power Duration Timer Registers */
-#define BCHP_SWITCH_CORE_EEE_MIN_LP_TIMER_G_IMP 0x04e249e0 /* EEE Port 8(IMP) Minimum Low-Power Duration Timer Registers */
-#define BCHP_SWITCH_CORE_EEE_MIN_LP_TIMER_H_Port_0 0x04e249f0 /* EEE Port Minimum Low-Power Duration Timer - 100M Registers */
-#define BCHP_SWITCH_CORE_EEE_MIN_LP_TIMER_H_Port_1 0x04e24a00 /* EEE Port Minimum Low-Power Duration Timer - 100M Registers */
-#define BCHP_SWITCH_CORE_EEE_MIN_LP_TIMER_H_Port_2 0x04e24a10 /* EEE Port Minimum Low-Power Duration Timer - 100M Registers */
-#define BCHP_SWITCH_CORE_EEE_MIN_LP_TIMER_H_Port_3 0x04e24a20 /* EEE Port Minimum Low-Power Duration Timer - 100M Registers */
-#define BCHP_SWITCH_CORE_EEE_MIN_LP_TIMER_H_Port_4 0x04e24a30 /* EEE Port Minimum Low-Power Duration Timer - 100M Registers */
-#define BCHP_SWITCH_CORE_EEE_MIN_LP_TIMER_H_Port_5 0x04e24a40 /* EEE Port Minimum Low-Power Duration Timer - 100M Registers */
-#define BCHP_SWITCH_CORE_EEE_MIN_LP_TIMER_H_P7 0x04e24a60 /* EEE Port 7 Minimum Low-Power Duration Timer - 100M Registers */
-#define BCHP_SWITCH_CORE_EEE_MIN_LP_TIMER_H_IMP 0x04e24a70 /* EEE Port 8(IMP) Minimum Low-Power Duration Timer - 100M Registers */
-#define BCHP_SWITCH_CORE_EEE_WAKE_TIMER_G_Port_0 0x04e24a80 /* EEE Port N Wake Transition Timer - 1G Registers */
-#define BCHP_SWITCH_CORE_EEE_WAKE_TIMER_G_Port_1 0x04e24a88 /* EEE Port N Wake Transition Timer - 1G Registers */
-#define BCHP_SWITCH_CORE_EEE_WAKE_TIMER_G_Port_2 0x04e24a90 /* EEE Port N Wake Transition Timer - 1G Registers */
-#define BCHP_SWITCH_CORE_EEE_WAKE_TIMER_G_Port_3 0x04e24a98 /* EEE Port N Wake Transition Timer - 1G Registers */
-#define BCHP_SWITCH_CORE_EEE_WAKE_TIMER_G_Port_4 0x04e24aa0 /* EEE Port N Wake Transition Timer - 1G Registers */
-#define BCHP_SWITCH_CORE_EEE_WAKE_TIMER_G_Port_5 0x04e24aa8 /* EEE Port N Wake Transition Timer - 1G Registers */
-#define BCHP_SWITCH_CORE_EEE_WAKE_TIMER_G_P7 0x04e24ab8 /* EEE Port 7 Wake Transition Timer - 1G Registers */
-#define BCHP_SWITCH_CORE_EEE_WAKE_TIMER_G_IMP 0x04e24ac0 /* EEE Port 8(IMP) Wake Transition Timer - 1G Registers */
-#define BCHP_SWITCH_CORE_EEE_WAKE_TIMER_H_Port_0 0x04e24ac8 /* EEE Port N Wake Transition Timer - 100M Registers */
-#define BCHP_SWITCH_CORE_EEE_WAKE_TIMER_H_Port_1 0x04e24ad0 /* EEE Port N Wake Transition Timer - 100M Registers */
-#define BCHP_SWITCH_CORE_EEE_WAKE_TIMER_H_Port_2 0x04e24ad8 /* EEE Port N Wake Transition Timer - 100M Registers */
-#define BCHP_SWITCH_CORE_EEE_WAKE_TIMER_H_Port_3 0x04e24ae0 /* EEE Port N Wake Transition Timer - 100M Registers */
-#define BCHP_SWITCH_CORE_EEE_WAKE_TIMER_H_Port_4 0x04e24ae8 /* EEE Port N Wake Transition Timer - 100M Registers */
-#define BCHP_SWITCH_CORE_EEE_WAKE_TIMER_H_Port_5 0x04e24af0 /* EEE Port N Wake Transition Timer - 100M Registers */
-#define BCHP_SWITCH_CORE_EEE_WAKE_TIMER_H_P7 0x04e24b00 /* EEE Port 7 Wake Transition Timer - 100M Registers */
-#define BCHP_SWITCH_CORE_EEE_WAKE_TIMER_H_IMP 0x04e24b08 /* EEE Port 8(IMP) Wake Transition Timer - 100M Registers */
-#define BCHP_SWITCH_CORE_EEE_GLB_CONG_TH 0x04e24b10 /* EEE Global Congestion Threshold Registers */
-#define BCHP_SWITCH_CORE_EEE_TXQ_CONG_TH_Port_0 0x04e24b18 /* EEE TXQ N Congestion Threshold Registers */
-#define BCHP_SWITCH_CORE_EEE_TXQ_CONG_TH_Port_1 0x04e24b20 /* EEE TXQ N Congestion Threshold Registers */
-#define BCHP_SWITCH_CORE_EEE_TXQ_CONG_TH_Port_2 0x04e24b28 /* EEE TXQ N Congestion Threshold Registers */
-#define BCHP_SWITCH_CORE_EEE_TXQ_CONG_TH_Port_3 0x04e24b30 /* EEE TXQ N Congestion Threshold Registers */
-#define BCHP_SWITCH_CORE_EEE_TXQ_CONG_TH_Port_4 0x04e24b38 /* EEE TXQ N Congestion Threshold Registers */
-#define BCHP_SWITCH_CORE_EEE_TXQ_CONG_TH_Port_5 0x04e24b40 /* EEE TXQ N Congestion Threshold Registers */
-#define BCHP_SWITCH_CORE_EEE_PHY_CTRL 0x04e24b48 /* EEE PHY Control Registers(Not2Release) */
-#define BCHP_SWITCH_CORE_EEE_TXQ_CONG_TH6 0x04e24b4c /* EEE TXQ 6 Congestion Threshold Registers */
-#define BCHP_SWITCH_CORE_EEE_TXQ_CONG_TH7 0x04e24b54 /* EEE TXQ 7 Congestion Threshold Registers */
-#define BCHP_SWITCH_CORE_EEE_CTL_REG_SPARE0 0x04e24b6c /* Spare 0 Register (Not2Release) */
-#define BCHP_SWITCH_CORE_EEE_CTL_REG_SPARE1 0x04e24b80 /* Spare 1 Register (Not2Release) */
-#define BCHP_SWITCH_CORE_EEE_DEBUG 0x04e24b9c /* EEE Debug Registers(Not2Release) */
-#define BCHP_SWITCH_CORE_EEE_LINK_DLY_TIMER 0x04e24ba0 /* EEE Link Delay Timer Registers(Not2Release) */
-#define BCHP_SWITCH_CORE_EEE_STATE 0x04e24bb0 /* EEE Control Policy State Registers(Not2Release) */
-#define BCHP_SWITCH_CORE_RED_CONTROL 0x04e25400 /* RED Control Register */
-#define BCHP_SWITCH_CORE_TC2RED_PROFILE_TABLE 0x04e25408 /* RED Table Configuration Register */
-#define BCHP_SWITCH_CORE_RED_EGRESS_BYPASS 0x04e25410 /* RED Egress Bypass Register */
-#define BCHP_SWITCH_CORE_RED_AQD_CONTROL 0x04e25418 /* RED AQD Control Register */
-#define BCHP_SWITCH_CORE_RED_EXPONENT 0x04e25420 /* RED AQD Weighted Factor Register */
-#define BCHP_SWITCH_CORE_RED_DROP_ADD_TO_MIB 0x04e25428 /* RED Drop Add to MIB Register */
-#define BCHP_SWITCH_CORE_RED_PROFILE_DEFAULT 0x04e25440 /* Default RED profile Register */
-#define BCHP_SWITCH_CORE_WRED_REG_SPARE0 0x04e25450 /* Spare 0 Register (Not2Release) */
-#define BCHP_SWITCH_CORE_WRED_REG_SPARE1 0x04e25460 /* Spare 1 Register (Not2Release) */
-#define BCHP_SWITCH_CORE_RED_PROFILE_N_Port_0 0x04e25480 /* RED profile N Register */
-#define BCHP_SWITCH_CORE_RED_PROFILE_N_Port_1 0x04e25490 /* RED profile N Register */
-#define BCHP_SWITCH_CORE_RED_PROFILE_N_Port_2 0x04e254a0 /* RED profile N Register */
-#define BCHP_SWITCH_CORE_RED_PROFILE_N_Port_3 0x04e254b0 /* RED profile N Register */
-#define BCHP_SWITCH_CORE_RED_PROFILE_N_Port_4 0x04e254c0 /* RED profile N Register */
-#define BCHP_SWITCH_CORE_RED_PROFILE_N_Port_5 0x04e254d0 /* RED profile N Register */
-#define BCHP_SWITCH_CORE_RED_PROFILE_N_Port_6 0x04e254e0 /* RED profile N Register */
-#define BCHP_SWITCH_CORE_RED_PROFILE_N_Port_7 0x04e254f0 /* RED profile N Register */
-#define BCHP_SWITCH_CORE_RED_PROFILE_N_Port_8 0x04e25500 /* RED profile N Register */
-#define BCHP_SWITCH_CORE_RED_PROFILE_N_Port_9 0x04e25510 /* RED profile N Register */
-#define BCHP_SWITCH_CORE_RED_PROFILE_N_Port_10 0x04e25520 /* RED profile N Register */
-#define BCHP_SWITCH_CORE_RED_PROFILE_N_Port_11 0x04e25530 /* RED profile N Register */
-#define BCHP_SWITCH_CORE_RED_PROFILE_N_Port_12 0x04e25540 /* RED profile N Register */
-#define BCHP_SWITCH_CORE_RED_PROFILE_N_Port_13 0x04e25550 /* RED profile N Register */
-#define BCHP_SWITCH_CORE_RED_PROFILE_N_Port_14 0x04e25560 /* RED profile N Register */
-#define BCHP_SWITCH_CORE_RED_PROFILE_N_Port_15 0x04e25570 /* RED profile N Register */
-#define BCHP_SWITCH_CORE_RED_DROP_CNTR_RST 0x04e255b0 /* RED Drop Counter Reset Register */
-#define BCHP_SWITCH_CORE_PN_PORT_RED_PKT_DROP_CNTR_Port_0 0x04e255c0 /* PORT N RED Packet Drop Counter Register */
-#define BCHP_SWITCH_CORE_PN_PORT_RED_PKT_DROP_CNTR_Port_1 0x04e255d0 /* PORT N RED Packet Drop Counter Register */
-#define BCHP_SWITCH_CORE_PN_PORT_RED_PKT_DROP_CNTR_Port_2 0x04e255e0 /* PORT N RED Packet Drop Counter Register */
-#define BCHP_SWITCH_CORE_PN_PORT_RED_PKT_DROP_CNTR_Port_3 0x04e255f0 /* PORT N RED Packet Drop Counter Register */
-#define BCHP_SWITCH_CORE_PN_PORT_RED_PKT_DROP_CNTR_Port_4 0x04e25600 /* PORT N RED Packet Drop Counter Register */
-#define BCHP_SWITCH_CORE_PN_PORT_RED_PKT_DROP_CNTR_Port_5 0x04e25610 /* PORT N RED Packet Drop Counter Register */
-#define BCHP_SWITCH_CORE_P7_PORT_RED_PKT_DROP_CNTR 0x04e25630 /* PORT 7 RED Packet Drop Counter Register */
-#define BCHP_SWITCH_CORE_IMP_PORT_RED_PKT_DROP_CNTR 0x04e25640 /* PORT 8 RED Packet Drop Counter Register */
-#define BCHP_SWITCH_CORE_PN_PORT_RED_BYTE_DROP_CNTR_Port_0 0x04e25680 /* PORT N RED Byte Drop Counter Register */
-#define BCHP_SWITCH_CORE_PN_PORT_RED_BYTE_DROP_CNTR_Port_1 0x04e256a0 /* PORT N RED Byte Drop Counter Register */
-#define BCHP_SWITCH_CORE_PN_PORT_RED_BYTE_DROP_CNTR_Port_2 0x04e256c0 /* PORT N RED Byte Drop Counter Register */
-#define BCHP_SWITCH_CORE_PN_PORT_RED_BYTE_DROP_CNTR_Port_3 0x04e256e0 /* PORT N RED Byte Drop Counter Register */
-#define BCHP_SWITCH_CORE_PN_PORT_RED_BYTE_DROP_CNTR_Port_4 0x04e25700 /* PORT N RED Byte Drop Counter Register */
-#define BCHP_SWITCH_CORE_PN_PORT_RED_BYTE_DROP_CNTR_Port_5 0x04e25720 /* PORT N RED Byte Drop Counter Register */
-#define BCHP_SWITCH_CORE_P7_PORT_RED_BYTE_DROP_CNTR 0x04e25760 /* PORT 7 RED Byte Drop Counter Register */
-#define BCHP_SWITCH_CORE_IMP_PORT_RED_BYTE_DROP_CNTR 0x04e25780 /* PORT 8 RED Byte Drop Counter Register */
-#define BCHP_SWITCH_CORE_CFP_ACC 0x04e28000 /* CFP Access Registers */
-#define BCHP_SWITCH_CORE_RATE_METER_GLOBAL_CTL 0x04e28010 /* CFP RATE METER Global Control Registers */
-#define BCHP_SWITCH_CORE_CFP_DATA_Port_0 0x04e28040 /* CFP TCAM Data X Registers */
-#define BCHP_SWITCH_CORE_CFP_DATA_Port_1 0x04e28050 /* CFP TCAM Data X Registers */
-#define BCHP_SWITCH_CORE_CFP_DATA_Port_2 0x04e28060 /* CFP TCAM Data X Registers */
-#define BCHP_SWITCH_CORE_CFP_DATA_Port_3 0x04e28070 /* CFP TCAM Data X Registers */
-#define BCHP_SWITCH_CORE_CFP_DATA_Port_4 0x04e28080 /* CFP TCAM Data X Registers */
-#define BCHP_SWITCH_CORE_CFP_DATA_Port_5 0x04e28090 /* CFP TCAM Data X Registers */
-#define BCHP_SWITCH_CORE_CFP_DATA_Port_6 0x04e280a0 /* CFP TCAM Data X Registers */
-#define BCHP_SWITCH_CORE_CFP_DATA_Port_7 0x04e280b0 /* CFP TCAM Data X Registers */
-#define BCHP_SWITCH_CORE_CFP_MASK_Port_0 0x04e280c0 /* CFP TCAM Mask X Registers */
-#define BCHP_SWITCH_CORE_CFP_MASK_Port_1 0x04e280d0 /* CFP TCAM Mask X Registers */
-#define BCHP_SWITCH_CORE_CFP_MASK_Port_2 0x04e280e0 /* CFP TCAM Mask X Registers */
-#define BCHP_SWITCH_CORE_CFP_MASK_Port_3 0x04e280f0 /* CFP TCAM Mask X Registers */
-#define BCHP_SWITCH_CORE_CFP_MASK_Port_4 0x04e28100 /* CFP TCAM Mask X Registers */
-#define BCHP_SWITCH_CORE_CFP_MASK_Port_5 0x04e28110 /* CFP TCAM Mask X Registers */
-#define BCHP_SWITCH_CORE_CFP_MASK_Port_6 0x04e28120 /* CFP TCAM Mask X Registers */
-#define BCHP_SWITCH_CORE_CFP_MASK_Port_7 0x04e28130 /* CFP TCAM Mask X Registers */
-#define BCHP_SWITCH_CORE_ACT_POL_DATA0 0x04e28140 /* CFP Action/Policy Data 0 Registers */
-#define BCHP_SWITCH_CORE_ACT_POL_DATA1 0x04e28150 /* CFP Action/Policy Data 1 Registers */
-#define BCHP_SWITCH_CORE_ACT_POL_DATA2 0x04e28160 /* CFP Action/Policy Data 2 Registers */
-#define BCHP_SWITCH_CORE_RATE_METER0 0x04e28180 /* CFP RATE METER DATA 0 Registers */
-#define BCHP_SWITCH_CORE_RATE_METER1 0x04e28190 /* CFP RATE METER DATA 1 Registers */
-#define BCHP_SWITCH_CORE_RATE_METER2 0x04e281a0 /* CFP RATE METER DATA 2 Registers */
-#define BCHP_SWITCH_CORE_RATE_METER3 0x04e281b0 /* CFP RATE METER DATA 3 Registers */
-#define BCHP_SWITCH_CORE_RATE_METER4 0x04e281c0 /* CFP RATE METER DATA 4 Registers */
-#define BCHP_SWITCH_CORE_RATE_METER5 0x04e281d0 /* CFP RATE METER DATA 5 Registers */
-#define BCHP_SWITCH_CORE_RATE_METER6 0x04e281e0 /* CFP RATE METER DATA 6 Registers */
-#define BCHP_SWITCH_CORE_TC2COLOR 0x04e281f0 /* TC to COLOR Mapping Registers */
-#define BCHP_SWITCH_CORE_STAT_GREEN_CNTR 0x04e28200 /* Policer Green color statistic counter */
-#define BCHP_SWITCH_CORE_STAT_YELLOW_CNTR 0x04e28210 /* Policer Yellow color statistic counter */
-#define BCHP_SWITCH_CORE_STAT_RED_CNTR 0x04e28220 /* Policer RED color statistic counter */
-#define BCHP_SWITCH_CORE_TCAM_BIST_CONTROL 0x04e28280 /* TCAM BIST Control Registers (Not2Release) */
-#define BCHP_SWITCH_CORE_TCAM_BIST_STATUS 0x04e28290 /* TCAM BIST Status Registers (Not2Release) */
-#define BCHP_SWITCH_CORE_TCAM_TEST_COMPARE_STATUS 0x04e282a0 /* TCAM Test Compare Status Registers (Not2Release) */
-#define BCHP_SWITCH_CORE_CFP_REG_SPARE0 0x04e282c0 /* Spare 0 Register (Not2Release) */
-#define BCHP_SWITCH_CORE_CFP_REG_SPARE1 0x04e282d0 /* Spare 1 Register (Not2Release) */
-#define BCHP_SWITCH_CORE_CFP_CTL_REG 0x04e28400 /* CFP Control Registers */
-#define BCHP_SWITCH_CORE_UDF_0_A_0_8_Port_0 0x04e28440 /* UDFs of slice 0 for IPv4 packet Registers */
-#define BCHP_SWITCH_CORE_UDF_0_A_0_8_Port_1 0x04e28444 /* UDFs of slice 0 for IPv4 packet Registers */
-#define BCHP_SWITCH_CORE_UDF_0_A_0_8_Port_2 0x04e28448 /* UDFs of slice 0 for IPv4 packet Registers */
-#define BCHP_SWITCH_CORE_UDF_0_A_0_8_Port_3 0x04e2844c /* UDFs of slice 0 for IPv4 packet Registers */
-#define BCHP_SWITCH_CORE_UDF_0_A_0_8_Port_4 0x04e28450 /* UDFs of slice 0 for IPv4 packet Registers */
-#define BCHP_SWITCH_CORE_UDF_0_A_0_8_Port_5 0x04e28454 /* UDFs of slice 0 for IPv4 packet Registers */
-#define BCHP_SWITCH_CORE_UDF_0_A_0_8_Port_6 0x04e28458 /* UDFs of slice 0 for IPv4 packet Registers */
-#define BCHP_SWITCH_CORE_UDF_0_A_0_8_Port_7 0x04e2845c /* UDFs of slice 0 for IPv4 packet Registers */
-#define BCHP_SWITCH_CORE_UDF_0_A_0_8_Port_8 0x04e28460 /* UDFs of slice 0 for IPv4 packet Registers */
-#define BCHP_SWITCH_CORE_UDF_1_A_0_8_Port_0 0x04e28480 /* UDFs of slice 1 for IPv4 packet Registers */
-#define BCHP_SWITCH_CORE_UDF_1_A_0_8_Port_1 0x04e28484 /* UDFs of slice 1 for IPv4 packet Registers */
-#define BCHP_SWITCH_CORE_UDF_1_A_0_8_Port_2 0x04e28488 /* UDFs of slice 1 for IPv4 packet Registers */
-#define BCHP_SWITCH_CORE_UDF_1_A_0_8_Port_3 0x04e2848c /* UDFs of slice 1 for IPv4 packet Registers */
-#define BCHP_SWITCH_CORE_UDF_1_A_0_8_Port_4 0x04e28490 /* UDFs of slice 1 for IPv4 packet Registers */
-#define BCHP_SWITCH_CORE_UDF_1_A_0_8_Port_5 0x04e28494 /* UDFs of slice 1 for IPv4 packet Registers */
-#define BCHP_SWITCH_CORE_UDF_1_A_0_8_Port_6 0x04e28498 /* UDFs of slice 1 for IPv4 packet Registers */
-#define BCHP_SWITCH_CORE_UDF_1_A_0_8_Port_7 0x04e2849c /* UDFs of slice 1 for IPv4 packet Registers */
-#define BCHP_SWITCH_CORE_UDF_1_A_0_8_Port_8 0x04e284a0 /* UDFs of slice 1 for IPv4 packet Registers */
-#define BCHP_SWITCH_CORE_UDF_2_A_0_8_Port_0 0x04e284c0 /* UDFs of slice 2 for IPv4 packet Registers */
-#define BCHP_SWITCH_CORE_UDF_2_A_0_8_Port_1 0x04e284c4 /* UDFs of slice 2 for IPv4 packet Registers */
-#define BCHP_SWITCH_CORE_UDF_2_A_0_8_Port_2 0x04e284c8 /* UDFs of slice 2 for IPv4 packet Registers */
-#define BCHP_SWITCH_CORE_UDF_2_A_0_8_Port_3 0x04e284cc /* UDFs of slice 2 for IPv4 packet Registers */
-#define BCHP_SWITCH_CORE_UDF_2_A_0_8_Port_4 0x04e284d0 /* UDFs of slice 2 for IPv4 packet Registers */
-#define BCHP_SWITCH_CORE_UDF_2_A_0_8_Port_5 0x04e284d4 /* UDFs of slice 2 for IPv4 packet Registers */
-#define BCHP_SWITCH_CORE_UDF_2_A_0_8_Port_6 0x04e284d8 /* UDFs of slice 2 for IPv4 packet Registers */
-#define BCHP_SWITCH_CORE_UDF_2_A_0_8_Port_7 0x04e284dc /* UDFs of slice 2 for IPv4 packet Registers */
-#define BCHP_SWITCH_CORE_UDF_2_A_0_8_Port_8 0x04e284e0 /* UDFs of slice 2 for IPv4 packet Registers */
-#define BCHP_SWITCH_CORE_UDF_0_B_0_8_Port_0 0x04e28500 /* UDFs of slice 0 for IPv6 packet Registers */
-#define BCHP_SWITCH_CORE_UDF_0_B_0_8_Port_1 0x04e28504 /* UDFs of slice 0 for IPv6 packet Registers */
-#define BCHP_SWITCH_CORE_UDF_0_B_0_8_Port_2 0x04e28508 /* UDFs of slice 0 for IPv6 packet Registers */
-#define BCHP_SWITCH_CORE_UDF_0_B_0_8_Port_3 0x04e2850c /* UDFs of slice 0 for IPv6 packet Registers */
-#define BCHP_SWITCH_CORE_UDF_0_B_0_8_Port_4 0x04e28510 /* UDFs of slice 0 for IPv6 packet Registers */
-#define BCHP_SWITCH_CORE_UDF_0_B_0_8_Port_5 0x04e28514 /* UDFs of slice 0 for IPv6 packet Registers */
-#define BCHP_SWITCH_CORE_UDF_0_B_0_8_Port_6 0x04e28518 /* UDFs of slice 0 for IPv6 packet Registers */
-#define BCHP_SWITCH_CORE_UDF_0_B_0_8_Port_7 0x04e2851c /* UDFs of slice 0 for IPv6 packet Registers */
-#define BCHP_SWITCH_CORE_UDF_0_B_0_8_Port_8 0x04e28520 /* UDFs of slice 0 for IPv6 packet Registers */
-#define BCHP_SWITCH_CORE_UDF_1_B_0_8_Port_0 0x04e28540 /* UDFs of slice 1 for IPv6 Registers */
-#define BCHP_SWITCH_CORE_UDF_1_B_0_8_Port_1 0x04e28544 /* UDFs of slice 1 for IPv6 Registers */
-#define BCHP_SWITCH_CORE_UDF_1_B_0_8_Port_2 0x04e28548 /* UDFs of slice 1 for IPv6 Registers */
-#define BCHP_SWITCH_CORE_UDF_1_B_0_8_Port_3 0x04e2854c /* UDFs of slice 1 for IPv6 Registers */
-#define BCHP_SWITCH_CORE_UDF_1_B_0_8_Port_4 0x04e28550 /* UDFs of slice 1 for IPv6 Registers */
-#define BCHP_SWITCH_CORE_UDF_1_B_0_8_Port_5 0x04e28554 /* UDFs of slice 1 for IPv6 Registers */
-#define BCHP_SWITCH_CORE_UDF_1_B_0_8_Port_6 0x04e28558 /* UDFs of slice 1 for IPv6 Registers */
-#define BCHP_SWITCH_CORE_UDF_1_B_0_8_Port_7 0x04e2855c /* UDFs of slice 1 for IPv6 Registers */
-#define BCHP_SWITCH_CORE_UDF_1_B_0_8_Port_8 0x04e28560 /* UDFs of slice 1 for IPv6 Registers */
-#define BCHP_SWITCH_CORE_UDF_2_B_0_8_Port_0 0x04e28580 /* UDFs of slice 2 for IPv6 Registers */
-#define BCHP_SWITCH_CORE_UDF_2_B_0_8_Port_1 0x04e28584 /* UDFs of slice 2 for IPv6 Registers */
-#define BCHP_SWITCH_CORE_UDF_2_B_0_8_Port_2 0x04e28588 /* UDFs of slice 2 for IPv6 Registers */
-#define BCHP_SWITCH_CORE_UDF_2_B_0_8_Port_3 0x04e2858c /* UDFs of slice 2 for IPv6 Registers */
-#define BCHP_SWITCH_CORE_UDF_2_B_0_8_Port_4 0x04e28590 /* UDFs of slice 2 for IPv6 Registers */
-#define BCHP_SWITCH_CORE_UDF_2_B_0_8_Port_5 0x04e28594 /* UDFs of slice 2 for IPv6 Registers */
-#define BCHP_SWITCH_CORE_UDF_2_B_0_8_Port_6 0x04e28598 /* UDFs of slice 2 for IPv6 Registers */
-#define BCHP_SWITCH_CORE_UDF_2_B_0_8_Port_7 0x04e2859c /* UDFs of slice 2 for IPv6 Registers */
-#define BCHP_SWITCH_CORE_UDF_2_B_0_8_Port_8 0x04e285a0 /* UDFs of slice 2 for IPv6 Registers */
-#define BCHP_SWITCH_CORE_UDF_0_C_0_8_Port_0 0x04e285c0 /* UDFs of slice 0 for none-IP Registers */
-#define BCHP_SWITCH_CORE_UDF_0_C_0_8_Port_1 0x04e285c4 /* UDFs of slice 0 for none-IP Registers */
-#define BCHP_SWITCH_CORE_UDF_0_C_0_8_Port_2 0x04e285c8 /* UDFs of slice 0 for none-IP Registers */
-#define BCHP_SWITCH_CORE_UDF_0_C_0_8_Port_3 0x04e285cc /* UDFs of slice 0 for none-IP Registers */
-#define BCHP_SWITCH_CORE_UDF_0_C_0_8_Port_4 0x04e285d0 /* UDFs of slice 0 for none-IP Registers */
-#define BCHP_SWITCH_CORE_UDF_0_C_0_8_Port_5 0x04e285d4 /* UDFs of slice 0 for none-IP Registers */
-#define BCHP_SWITCH_CORE_UDF_0_C_0_8_Port_6 0x04e285d8 /* UDFs of slice 0 for none-IP Registers */
-#define BCHP_SWITCH_CORE_UDF_0_C_0_8_Port_7 0x04e285dc /* UDFs of slice 0 for none-IP Registers */
-#define BCHP_SWITCH_CORE_UDF_0_C_0_8_Port_8 0x04e285e0 /* UDFs of slice 0 for none-IP Registers */
-#define BCHP_SWITCH_CORE_UDF_1_C_0_8_Port_0 0x04e28600 /* UDFs of slice 1 for none-IP Registers */
-#define BCHP_SWITCH_CORE_UDF_1_C_0_8_Port_1 0x04e28604 /* UDFs of slice 1 for none-IP Registers */
-#define BCHP_SWITCH_CORE_UDF_1_C_0_8_Port_2 0x04e28608 /* UDFs of slice 1 for none-IP Registers */
-#define BCHP_SWITCH_CORE_UDF_1_C_0_8_Port_3 0x04e2860c /* UDFs of slice 1 for none-IP Registers */
-#define BCHP_SWITCH_CORE_UDF_1_C_0_8_Port_4 0x04e28610 /* UDFs of slice 1 for none-IP Registers */
-#define BCHP_SWITCH_CORE_UDF_1_C_0_8_Port_5 0x04e28614 /* UDFs of slice 1 for none-IP Registers */
-#define BCHP_SWITCH_CORE_UDF_1_C_0_8_Port_6 0x04e28618 /* UDFs of slice 1 for none-IP Registers */
-#define BCHP_SWITCH_CORE_UDF_1_C_0_8_Port_7 0x04e2861c /* UDFs of slice 1 for none-IP Registers */
-#define BCHP_SWITCH_CORE_UDF_1_C_0_8_Port_8 0x04e28620 /* UDFs of slice 1 for none-IP Registers */
-#define BCHP_SWITCH_CORE_UDF_2_C_0_8_Port_0 0x04e28640 /* UDFs of slice 2 for none-IP Registers */
-#define BCHP_SWITCH_CORE_UDF_2_C_0_8_Port_1 0x04e28644 /* UDFs of slice 2 for none-IP Registers */
-#define BCHP_SWITCH_CORE_UDF_2_C_0_8_Port_2 0x04e28648 /* UDFs of slice 2 for none-IP Registers */
-#define BCHP_SWITCH_CORE_UDF_2_C_0_8_Port_3 0x04e2864c /* UDFs of slice 2 for none-IP Registers */
-#define BCHP_SWITCH_CORE_UDF_2_C_0_8_Port_4 0x04e28650 /* UDFs of slice 2 for none-IP Registers */
-#define BCHP_SWITCH_CORE_UDF_2_C_0_8_Port_5 0x04e28654 /* UDFs of slice 2 for none-IP Registers */
-#define BCHP_SWITCH_CORE_UDF_2_C_0_8_Port_6 0x04e28658 /* UDFs of slice 2 for none-IP Registers */
-#define BCHP_SWITCH_CORE_UDF_2_C_0_8_Port_7 0x04e2865c /* UDFs of slice 2 for none-IP Registers */
-#define BCHP_SWITCH_CORE_UDF_2_C_0_8_Port_8 0x04e28660 /* UDFs of slice 2 for none-IP Registers */
-#define BCHP_SWITCH_CORE_UDF_0_D_0_11_Port_0 0x04e28680 /* UDFs for IPv6 Chain Rule Registers */
-#define BCHP_SWITCH_CORE_UDF_0_D_0_11_Port_1 0x04e28684 /* UDFs for IPv6 Chain Rule Registers */
-#define BCHP_SWITCH_CORE_UDF_0_D_0_11_Port_2 0x04e28688 /* UDFs for IPv6 Chain Rule Registers */
-#define BCHP_SWITCH_CORE_UDF_0_D_0_11_Port_3 0x04e2868c /* UDFs for IPv6 Chain Rule Registers */
-#define BCHP_SWITCH_CORE_UDF_0_D_0_11_Port_4 0x04e28690 /* UDFs for IPv6 Chain Rule Registers */
-#define BCHP_SWITCH_CORE_UDF_0_D_0_11_Port_5 0x04e28694 /* UDFs for IPv6 Chain Rule Registers */
-#define BCHP_SWITCH_CORE_UDF_0_D_0_11_Port_6 0x04e28698 /* UDFs for IPv6 Chain Rule Registers */
-#define BCHP_SWITCH_CORE_UDF_0_D_0_11_Port_7 0x04e2869c /* UDFs for IPv6 Chain Rule Registers */
-#define BCHP_SWITCH_CORE_UDF_0_D_0_11_Port_8 0x04e286a0 /* UDFs for IPv6 Chain Rule Registers */
-#define BCHP_SWITCH_CORE_UDF_0_D_0_11_Port_9 0x04e286a4 /* UDFs for IPv6 Chain Rule Registers */
-#define BCHP_SWITCH_CORE_UDF_0_D_0_11_Port_10 0x04e286a8 /* UDFs for IPv6 Chain Rule Registers */
-#define BCHP_SWITCH_CORE_UDF_0_D_0_11_Port_11 0x04e286ac /* UDFs for IPv6 Chain Rule Registers */
-#define BCHP_SWITCH_CORE_OTP_CTL_REG 0x04e38000 /* CPU OTP Control RegistersNot2Release */
-#define BCHP_SWITCH_CORE_OTP_ADDR_REG 0x04e38010 /* CPU OTP Address RegistersNot2Release */
-#define BCHP_SWITCH_CORE_OTP_STS_REG 0x04e38018 /* CPU OTP Status RegistersNot2Release */
-#define BCHP_SWITCH_CORE_OTP_WR_DATA 0x04e38020 /* CPU OTP Write Data RegistersNot2Release */
-#define BCHP_SWITCH_CORE_OTP_RD_DATA 0x04e38030 /* CPU OTP Read Data RegistersNot2Release */
-#define BCHP_SWITCH_CORE_IO_SR_CTL 0x04e38080 /* I/O Pad Slew Rate Control Register (Engineering use only)Not2Release */
-#define BCHP_SWITCH_CORE_IO_DS_SEL0 0x04e38090 /* I/O Pad Drive Strength Select 0 Register (Engineering use only)Not2Release */
-#define BCHP_SWITCH_CORE_IO_DS_SEL2 0x04e380b0 /* I/O Pad Drive Strength Select 2 Register (Engineering use only)Not2Release */
-#define BCHP_SWITCH_CORE_GMII_IO_SR_CTL 0x04e380c0 /* GMII I/O Pad Slew Rate Control Register (Engineering use only)Not2Release */
-#define BCHP_SWITCH_CORE_GMII_IO_DS_SEL0 0x04e380d0 /* GMII I/O Pad Drive Strength Select 0 Register (Engineering use only)Not2Release */
-#define BCHP_SWITCH_CORE_GMII_IO_DS_SEL1 0x04e380e0 /* GMII I/O Pad Drive Strength Select 1 Register (Engineering use only)Not2Release */
-#define BCHP_SWITCH_CORE_OTP_CTL_REG_SPARE0 0x04e38100 /* Spare 0 Register (Not2Release)Not2Release */
-#define BCHP_SWITCH_CORE_OTP_CTL_REG_SPARE1 0x04e38110 /* Spare 1 Register (Not2Release)Not2Release */
-#define BCHP_SWITCH_CORE_SPIDIO0 0x04e3ffc0 /* SPI Data I/O Registers 0 */
-#define BCHP_SWITCH_CORE_SPIDIO1 0x04e3ffc4 /* SPI Data I/O Registers 1 */
-#define BCHP_SWITCH_CORE_SPIDIO2 0x04e3ffc8 /* SPI Data I/O Registers 2 */
-#define BCHP_SWITCH_CORE_SPIDIO3 0x04e3ffcc /* SPI Data I/O Registers 3 */
-#define BCHP_SWITCH_CORE_SPIDIO4 0x04e3ffd0 /* SPI Data I/O Registers 4 */
-#define BCHP_SWITCH_CORE_SPIDIO5 0x04e3ffd4 /* SPI Data I/O Registers 5 */
-#define BCHP_SWITCH_CORE_SPIDIO6 0x04e3ffd8 /* SPI Data I/O Registers 6 */
-#define BCHP_SWITCH_CORE_SPIDIO7 0x04e3ffdc /* SPI Data I/O Registers 7 */
-#define BCHP_SWITCH_CORE_CLKSET 0x04e3ffe8 /* Clock Period Setting Registers */
-#define BCHP_SWITCH_CORE_SPISTS 0x04e3fff8 /* SPI Status Registers */
-#define BCHP_SWITCH_CORE_PAGEREG 0x04e3fffc /* PAGE Control Registers */
-
-/***************************************************************************
- *G_PCTL_Port_0 - Port N 10/100/1000 Control Register
- ***************************************************************************/
-/* SWITCH_CORE :: G_PCTL_Port_0 :: reserved_for_padding0 [31:08] */
-#define BCHP_SWITCH_CORE_G_PCTL_Port_0_reserved_for_padding0_MASK 0xffffff00
-#define BCHP_SWITCH_CORE_G_PCTL_Port_0_reserved_for_padding0_SHIFT 8
-
-/* SWITCH_CORE :: G_PCTL_Port_0 :: G_MISTP_STATE [07:05] */
-#define BCHP_SWITCH_CORE_G_PCTL_Port_0_G_MISTP_STATE_MASK 0x000000e0
-#define BCHP_SWITCH_CORE_G_PCTL_Port_0_G_MISTP_STATE_SHIFT 5
-#define BCHP_SWITCH_CORE_G_PCTL_Port_0_G_MISTP_STATE_DEFAULT 0x00000001
-
-/* SWITCH_CORE :: G_PCTL_Port_0 :: SWITCH_RESV [04:02] */
-#define BCHP_SWITCH_CORE_G_PCTL_Port_0_SWITCH_RESV_MASK 0x0000001c
-#define BCHP_SWITCH_CORE_G_PCTL_Port_0_SWITCH_RESV_SHIFT 2
-#define BCHP_SWITCH_CORE_G_PCTL_Port_0_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: G_PCTL_Port_0 :: TX_DIS [01:01] */
-#define BCHP_SWITCH_CORE_G_PCTL_Port_0_TX_DIS_MASK 0x00000002
-#define BCHP_SWITCH_CORE_G_PCTL_Port_0_TX_DIS_SHIFT 1
-#define BCHP_SWITCH_CORE_G_PCTL_Port_0_TX_DIS_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: G_PCTL_Port_0 :: RX_DIS [00:00] */
-#define BCHP_SWITCH_CORE_G_PCTL_Port_0_RX_DIS_MASK 0x00000001
-#define BCHP_SWITCH_CORE_G_PCTL_Port_0_RX_DIS_SHIFT 0
-#define BCHP_SWITCH_CORE_G_PCTL_Port_0_RX_DIS_DEFAULT 0x00000000
-
-/***************************************************************************
- *G_PCTL_Port_1 - Port N 10/100/1000 Control Register
- ***************************************************************************/
-/* SWITCH_CORE :: G_PCTL_Port_1 :: reserved_for_padding0 [31:08] */
-#define BCHP_SWITCH_CORE_G_PCTL_Port_1_reserved_for_padding0_MASK 0xffffff00
-#define BCHP_SWITCH_CORE_G_PCTL_Port_1_reserved_for_padding0_SHIFT 8
-
-/* SWITCH_CORE :: G_PCTL_Port_1 :: G_MISTP_STATE [07:05] */
-#define BCHP_SWITCH_CORE_G_PCTL_Port_1_G_MISTP_STATE_MASK 0x000000e0
-#define BCHP_SWITCH_CORE_G_PCTL_Port_1_G_MISTP_STATE_SHIFT 5
-#define BCHP_SWITCH_CORE_G_PCTL_Port_1_G_MISTP_STATE_DEFAULT 0x00000001
-
-/* SWITCH_CORE :: G_PCTL_Port_1 :: SWITCH_RESV [04:02] */
-#define BCHP_SWITCH_CORE_G_PCTL_Port_1_SWITCH_RESV_MASK 0x0000001c
-#define BCHP_SWITCH_CORE_G_PCTL_Port_1_SWITCH_RESV_SHIFT 2
-#define BCHP_SWITCH_CORE_G_PCTL_Port_1_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: G_PCTL_Port_1 :: TX_DIS [01:01] */
-#define BCHP_SWITCH_CORE_G_PCTL_Port_1_TX_DIS_MASK 0x00000002
-#define BCHP_SWITCH_CORE_G_PCTL_Port_1_TX_DIS_SHIFT 1
-#define BCHP_SWITCH_CORE_G_PCTL_Port_1_TX_DIS_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: G_PCTL_Port_1 :: RX_DIS [00:00] */
-#define BCHP_SWITCH_CORE_G_PCTL_Port_1_RX_DIS_MASK 0x00000001
-#define BCHP_SWITCH_CORE_G_PCTL_Port_1_RX_DIS_SHIFT 0
-#define BCHP_SWITCH_CORE_G_PCTL_Port_1_RX_DIS_DEFAULT 0x00000000
-
-/***************************************************************************
- *G_PCTL_Port_2 - Port N 10/100/1000 Control Register
- ***************************************************************************/
-/* SWITCH_CORE :: G_PCTL_Port_2 :: reserved_for_padding0 [31:08] */
-#define BCHP_SWITCH_CORE_G_PCTL_Port_2_reserved_for_padding0_MASK 0xffffff00
-#define BCHP_SWITCH_CORE_G_PCTL_Port_2_reserved_for_padding0_SHIFT 8
-
-/* SWITCH_CORE :: G_PCTL_Port_2 :: G_MISTP_STATE [07:05] */
-#define BCHP_SWITCH_CORE_G_PCTL_Port_2_G_MISTP_STATE_MASK 0x000000e0
-#define BCHP_SWITCH_CORE_G_PCTL_Port_2_G_MISTP_STATE_SHIFT 5
-#define BCHP_SWITCH_CORE_G_PCTL_Port_2_G_MISTP_STATE_DEFAULT 0x00000001
-
-/* SWITCH_CORE :: G_PCTL_Port_2 :: SWITCH_RESV [04:02] */
-#define BCHP_SWITCH_CORE_G_PCTL_Port_2_SWITCH_RESV_MASK 0x0000001c
-#define BCHP_SWITCH_CORE_G_PCTL_Port_2_SWITCH_RESV_SHIFT 2
-#define BCHP_SWITCH_CORE_G_PCTL_Port_2_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: G_PCTL_Port_2 :: TX_DIS [01:01] */
-#define BCHP_SWITCH_CORE_G_PCTL_Port_2_TX_DIS_MASK 0x00000002
-#define BCHP_SWITCH_CORE_G_PCTL_Port_2_TX_DIS_SHIFT 1
-#define BCHP_SWITCH_CORE_G_PCTL_Port_2_TX_DIS_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: G_PCTL_Port_2 :: RX_DIS [00:00] */
-#define BCHP_SWITCH_CORE_G_PCTL_Port_2_RX_DIS_MASK 0x00000001
-#define BCHP_SWITCH_CORE_G_PCTL_Port_2_RX_DIS_SHIFT 0
-#define BCHP_SWITCH_CORE_G_PCTL_Port_2_RX_DIS_DEFAULT 0x00000000
-
-/***************************************************************************
- *G_PCTL_Port_3 - Port N 10/100/1000 Control Register
- ***************************************************************************/
-/* SWITCH_CORE :: G_PCTL_Port_3 :: reserved_for_padding0 [31:08] */
-#define BCHP_SWITCH_CORE_G_PCTL_Port_3_reserved_for_padding0_MASK 0xffffff00
-#define BCHP_SWITCH_CORE_G_PCTL_Port_3_reserved_for_padding0_SHIFT 8
-
-/* SWITCH_CORE :: G_PCTL_Port_3 :: G_MISTP_STATE [07:05] */
-#define BCHP_SWITCH_CORE_G_PCTL_Port_3_G_MISTP_STATE_MASK 0x000000e0
-#define BCHP_SWITCH_CORE_G_PCTL_Port_3_G_MISTP_STATE_SHIFT 5
-#define BCHP_SWITCH_CORE_G_PCTL_Port_3_G_MISTP_STATE_DEFAULT 0x00000001
-
-/* SWITCH_CORE :: G_PCTL_Port_3 :: SWITCH_RESV [04:02] */
-#define BCHP_SWITCH_CORE_G_PCTL_Port_3_SWITCH_RESV_MASK 0x0000001c
-#define BCHP_SWITCH_CORE_G_PCTL_Port_3_SWITCH_RESV_SHIFT 2
-#define BCHP_SWITCH_CORE_G_PCTL_Port_3_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: G_PCTL_Port_3 :: TX_DIS [01:01] */
-#define BCHP_SWITCH_CORE_G_PCTL_Port_3_TX_DIS_MASK 0x00000002
-#define BCHP_SWITCH_CORE_G_PCTL_Port_3_TX_DIS_SHIFT 1
-#define BCHP_SWITCH_CORE_G_PCTL_Port_3_TX_DIS_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: G_PCTL_Port_3 :: RX_DIS [00:00] */
-#define BCHP_SWITCH_CORE_G_PCTL_Port_3_RX_DIS_MASK 0x00000001
-#define BCHP_SWITCH_CORE_G_PCTL_Port_3_RX_DIS_SHIFT 0
-#define BCHP_SWITCH_CORE_G_PCTL_Port_3_RX_DIS_DEFAULT 0x00000000
-
-/***************************************************************************
- *G_PCTL_Port_4 - Port N 10/100/1000 Control Register
- ***************************************************************************/
-/* SWITCH_CORE :: G_PCTL_Port_4 :: reserved_for_padding0 [31:08] */
-#define BCHP_SWITCH_CORE_G_PCTL_Port_4_reserved_for_padding0_MASK 0xffffff00
-#define BCHP_SWITCH_CORE_G_PCTL_Port_4_reserved_for_padding0_SHIFT 8
-
-/* SWITCH_CORE :: G_PCTL_Port_4 :: G_MISTP_STATE [07:05] */
-#define BCHP_SWITCH_CORE_G_PCTL_Port_4_G_MISTP_STATE_MASK 0x000000e0
-#define BCHP_SWITCH_CORE_G_PCTL_Port_4_G_MISTP_STATE_SHIFT 5
-#define BCHP_SWITCH_CORE_G_PCTL_Port_4_G_MISTP_STATE_DEFAULT 0x00000001
-
-/* SWITCH_CORE :: G_PCTL_Port_4 :: SWITCH_RESV [04:02] */
-#define BCHP_SWITCH_CORE_G_PCTL_Port_4_SWITCH_RESV_MASK 0x0000001c
-#define BCHP_SWITCH_CORE_G_PCTL_Port_4_SWITCH_RESV_SHIFT 2
-#define BCHP_SWITCH_CORE_G_PCTL_Port_4_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: G_PCTL_Port_4 :: TX_DIS [01:01] */
-#define BCHP_SWITCH_CORE_G_PCTL_Port_4_TX_DIS_MASK 0x00000002
-#define BCHP_SWITCH_CORE_G_PCTL_Port_4_TX_DIS_SHIFT 1
-#define BCHP_SWITCH_CORE_G_PCTL_Port_4_TX_DIS_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: G_PCTL_Port_4 :: RX_DIS [00:00] */
-#define BCHP_SWITCH_CORE_G_PCTL_Port_4_RX_DIS_MASK 0x00000001
-#define BCHP_SWITCH_CORE_G_PCTL_Port_4_RX_DIS_SHIFT 0
-#define BCHP_SWITCH_CORE_G_PCTL_Port_4_RX_DIS_DEFAULT 0x00000000
-
-/***************************************************************************
- *G_PCTL_Port_5 - Port N 10/100/1000 Control Register
- ***************************************************************************/
-/* SWITCH_CORE :: G_PCTL_Port_5 :: reserved_for_padding0 [31:08] */
-#define BCHP_SWITCH_CORE_G_PCTL_Port_5_reserved_for_padding0_MASK 0xffffff00
-#define BCHP_SWITCH_CORE_G_PCTL_Port_5_reserved_for_padding0_SHIFT 8
-
-/* SWITCH_CORE :: G_PCTL_Port_5 :: G_MISTP_STATE [07:05] */
-#define BCHP_SWITCH_CORE_G_PCTL_Port_5_G_MISTP_STATE_MASK 0x000000e0
-#define BCHP_SWITCH_CORE_G_PCTL_Port_5_G_MISTP_STATE_SHIFT 5
-#define BCHP_SWITCH_CORE_G_PCTL_Port_5_G_MISTP_STATE_DEFAULT 0x00000001
-
-/* SWITCH_CORE :: G_PCTL_Port_5 :: SWITCH_RESV [04:02] */
-#define BCHP_SWITCH_CORE_G_PCTL_Port_5_SWITCH_RESV_MASK 0x0000001c
-#define BCHP_SWITCH_CORE_G_PCTL_Port_5_SWITCH_RESV_SHIFT 2
-#define BCHP_SWITCH_CORE_G_PCTL_Port_5_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: G_PCTL_Port_5 :: TX_DIS [01:01] */
-#define BCHP_SWITCH_CORE_G_PCTL_Port_5_TX_DIS_MASK 0x00000002
-#define BCHP_SWITCH_CORE_G_PCTL_Port_5_TX_DIS_SHIFT 1
-#define BCHP_SWITCH_CORE_G_PCTL_Port_5_TX_DIS_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: G_PCTL_Port_5 :: RX_DIS [00:00] */
-#define BCHP_SWITCH_CORE_G_PCTL_Port_5_RX_DIS_MASK 0x00000001
-#define BCHP_SWITCH_CORE_G_PCTL_Port_5_RX_DIS_SHIFT 0
-#define BCHP_SWITCH_CORE_G_PCTL_Port_5_RX_DIS_DEFAULT 0x00000000
-
-/***************************************************************************
- *P7_CTL - Port 7 Control Register
- ***************************************************************************/
-/* SWITCH_CORE :: P7_CTL :: reserved_for_padding0 [31:08] */
-#define BCHP_SWITCH_CORE_P7_CTL_reserved_for_padding0_MASK 0xffffff00
-#define BCHP_SWITCH_CORE_P7_CTL_reserved_for_padding0_SHIFT 8
-
-/* SWITCH_CORE :: P7_CTL :: G_MISTP_STATE [07:05] */
-#define BCHP_SWITCH_CORE_P7_CTL_G_MISTP_STATE_MASK 0x000000e0
-#define BCHP_SWITCH_CORE_P7_CTL_G_MISTP_STATE_SHIFT 5
-#define BCHP_SWITCH_CORE_P7_CTL_G_MISTP_STATE_DEFAULT 0x00000001
-
-/* SWITCH_CORE :: P7_CTL :: SWITCH_RESV [04:02] */
-#define BCHP_SWITCH_CORE_P7_CTL_SWITCH_RESV_MASK 0x0000001c
-#define BCHP_SWITCH_CORE_P7_CTL_SWITCH_RESV_SHIFT 2
-#define BCHP_SWITCH_CORE_P7_CTL_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: P7_CTL :: TX_DIS [01:01] */
-#define BCHP_SWITCH_CORE_P7_CTL_TX_DIS_MASK 0x00000002
-#define BCHP_SWITCH_CORE_P7_CTL_TX_DIS_SHIFT 1
-#define BCHP_SWITCH_CORE_P7_CTL_TX_DIS_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: P7_CTL :: RX_DIS [00:00] */
-#define BCHP_SWITCH_CORE_P7_CTL_RX_DIS_MASK 0x00000001
-#define BCHP_SWITCH_CORE_P7_CTL_RX_DIS_SHIFT 0
-#define BCHP_SWITCH_CORE_P7_CTL_RX_DIS_DEFAULT 0x00000000
-
-/***************************************************************************
- *IMP_CTL - IMP Port Control Register
- ***************************************************************************/
-/* SWITCH_CORE :: IMP_CTL :: reserved_for_padding0 [31:08] */
-#define BCHP_SWITCH_CORE_IMP_CTL_reserved_for_padding0_MASK 0xffffff00
-#define BCHP_SWITCH_CORE_IMP_CTL_reserved_for_padding0_SHIFT 8
-
-/* SWITCH_CORE :: IMP_CTL :: SWITCH_RESV [07:05] */
-#define BCHP_SWITCH_CORE_IMP_CTL_SWITCH_RESV_MASK 0x000000e0
-#define BCHP_SWITCH_CORE_IMP_CTL_SWITCH_RESV_SHIFT 5
-#define BCHP_SWITCH_CORE_IMP_CTL_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: IMP_CTL :: RX_UCST_EN [04:04] */
-#define BCHP_SWITCH_CORE_IMP_CTL_RX_UCST_EN_MASK 0x00000010
-#define BCHP_SWITCH_CORE_IMP_CTL_RX_UCST_EN_SHIFT 4
-#define BCHP_SWITCH_CORE_IMP_CTL_RX_UCST_EN_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: IMP_CTL :: RX_MCST_EN [03:03] */
-#define BCHP_SWITCH_CORE_IMP_CTL_RX_MCST_EN_MASK 0x00000008
-#define BCHP_SWITCH_CORE_IMP_CTL_RX_MCST_EN_SHIFT 3
-#define BCHP_SWITCH_CORE_IMP_CTL_RX_MCST_EN_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: IMP_CTL :: RX_BCST_EN [02:02] */
-#define BCHP_SWITCH_CORE_IMP_CTL_RX_BCST_EN_MASK 0x00000004
-#define BCHP_SWITCH_CORE_IMP_CTL_RX_BCST_EN_SHIFT 2
-#define BCHP_SWITCH_CORE_IMP_CTL_RX_BCST_EN_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: IMP_CTL :: TX_DIS [01:01] */
-#define BCHP_SWITCH_CORE_IMP_CTL_TX_DIS_MASK 0x00000002
-#define BCHP_SWITCH_CORE_IMP_CTL_TX_DIS_SHIFT 1
-#define BCHP_SWITCH_CORE_IMP_CTL_TX_DIS_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: IMP_CTL :: RX_DIS [00:00] */
-#define BCHP_SWITCH_CORE_IMP_CTL_RX_DIS_MASK 0x00000001
-#define BCHP_SWITCH_CORE_IMP_CTL_RX_DIS_SHIFT 0
-#define BCHP_SWITCH_CORE_IMP_CTL_RX_DIS_DEFAULT 0x00000000
-
-/***************************************************************************
- *RX_GLOBAL_CTL - RX Global Control register(Not2Release)
- ***************************************************************************/
-/* SWITCH_CORE :: RX_GLOBAL_CTL :: reserved_for_padding0 [31:08] */
-#define BCHP_SWITCH_CORE_RX_GLOBAL_CTL_reserved_for_padding0_MASK 0xffffff00
-#define BCHP_SWITCH_CORE_RX_GLOBAL_CTL_reserved_for_padding0_SHIFT 8
-
-/* SWITCH_CORE :: RX_GLOBAL_CTL :: SWITCH_RESV [07:07] */
-#define BCHP_SWITCH_CORE_RX_GLOBAL_CTL_SWITCH_RESV_MASK 0x00000080
-#define BCHP_SWITCH_CORE_RX_GLOBAL_CTL_SWITCH_RESV_SHIFT 7
-#define BCHP_SWITCH_CORE_RX_GLOBAL_CTL_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: RX_GLOBAL_CTL :: DIS_RX_MASK [06:06] */
-#define BCHP_SWITCH_CORE_RX_GLOBAL_CTL_DIS_RX_MASK_MASK 0x00000040
-#define BCHP_SWITCH_CORE_RX_GLOBAL_CTL_DIS_RX_MASK_SHIFT 6
-#define BCHP_SWITCH_CORE_RX_GLOBAL_CTL_DIS_RX_MASK_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: RX_GLOBAL_CTL :: DIS_ECC_CHK [05:05] */
-#define BCHP_SWITCH_CORE_RX_GLOBAL_CTL_DIS_ECC_CHK_MASK 0x00000020
-#define BCHP_SWITCH_CORE_RX_GLOBAL_CTL_DIS_ECC_CHK_SHIFT 5
-#define BCHP_SWITCH_CORE_RX_GLOBAL_CTL_DIS_ECC_CHK_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: RX_GLOBAL_CTL :: DIS_CRC_CHK [04:04] */
-#define BCHP_SWITCH_CORE_RX_GLOBAL_CTL_DIS_CRC_CHK_MASK 0x00000010
-#define BCHP_SWITCH_CORE_RX_GLOBAL_CTL_DIS_CRC_CHK_SHIFT 4
-#define BCHP_SWITCH_CORE_RX_GLOBAL_CTL_DIS_CRC_CHK_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: RX_GLOBAL_CTL :: FMOK_LATENCY_CNT [03:00] */
-#define BCHP_SWITCH_CORE_RX_GLOBAL_CTL_FMOK_LATENCY_CNT_MASK 0x0000000f
-#define BCHP_SWITCH_CORE_RX_GLOBAL_CTL_FMOK_LATENCY_CNT_SHIFT 0
-#define BCHP_SWITCH_CORE_RX_GLOBAL_CTL_FMOK_LATENCY_CNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *SWMODE - Switch Mode Register
- ***************************************************************************/
-/* SWITCH_CORE :: SWMODE :: reserved_for_padding0 [31:08] */
-#define BCHP_SWITCH_CORE_SWMODE_reserved_for_padding0_MASK 0xffffff00
-#define BCHP_SWITCH_CORE_SWMODE_reserved_for_padding0_SHIFT 8
-
-/* SWITCH_CORE :: SWMODE :: SWITCH_RESV [07:05] */
-#define BCHP_SWITCH_CORE_SWMODE_SWITCH_RESV_MASK 0x000000e0
-#define BCHP_SWITCH_CORE_SWMODE_SWITCH_RESV_SHIFT 5
-#define BCHP_SWITCH_CORE_SWMODE_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: SWMODE :: NOBLKCD [04:04] */
-#define BCHP_SWITCH_CORE_SWMODE_NOBLKCD_MASK 0x00000010
-#define BCHP_SWITCH_CORE_SWMODE_NOBLKCD_SHIFT 4
-#define BCHP_SWITCH_CORE_SWMODE_NOBLKCD_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: SWMODE :: FAST_TXDESC_RERURN [03:03] */
-#define BCHP_SWITCH_CORE_SWMODE_FAST_TXDESC_RERURN_MASK 0x00000008
-#define BCHP_SWITCH_CORE_SWMODE_FAST_TXDESC_RERURN_SHIFT 3
-#define BCHP_SWITCH_CORE_SWMODE_FAST_TXDESC_RERURN_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: SWMODE :: RTRY_LMT_DIS [02:02] */
-#define BCHP_SWITCH_CORE_SWMODE_RTRY_LMT_DIS_MASK 0x00000004
-#define BCHP_SWITCH_CORE_SWMODE_RTRY_LMT_DIS_SHIFT 2
-#define BCHP_SWITCH_CORE_SWMODE_RTRY_LMT_DIS_DEFAULT 0x00000001
-
-/* SWITCH_CORE :: SWMODE :: SW_FWDG_EN [01:01] */
-#define BCHP_SWITCH_CORE_SWMODE_SW_FWDG_EN_MASK 0x00000002
-#define BCHP_SWITCH_CORE_SWMODE_SW_FWDG_EN_SHIFT 1
-#define BCHP_SWITCH_CORE_SWMODE_SW_FWDG_EN_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: SWMODE :: SW_FWDG_MODE [00:00] */
-#define BCHP_SWITCH_CORE_SWMODE_SW_FWDG_MODE_MASK 0x00000001
-#define BCHP_SWITCH_CORE_SWMODE_SW_FWDG_MODE_SHIFT 0
-#define BCHP_SWITCH_CORE_SWMODE_SW_FWDG_MODE_DEFAULT 0x00000001
-
-/***************************************************************************
- *STS_OVERRIDE_IMP - IMP Port States Override Register
- ***************************************************************************/
-/* SWITCH_CORE :: STS_OVERRIDE_IMP :: reserved_for_padding0 [31:08] */
-#define BCHP_SWITCH_CORE_STS_OVERRIDE_IMP_reserved_for_padding0_MASK 0xffffff00
-#define BCHP_SWITCH_CORE_STS_OVERRIDE_IMP_reserved_for_padding0_SHIFT 8
-
-/* SWITCH_CORE :: STS_OVERRIDE_IMP :: MII_SW_OR [07:07] */
-#define BCHP_SWITCH_CORE_STS_OVERRIDE_IMP_MII_SW_OR_MASK 0x00000080
-#define BCHP_SWITCH_CORE_STS_OVERRIDE_IMP_MII_SW_OR_SHIFT 7
-#define BCHP_SWITCH_CORE_STS_OVERRIDE_IMP_MII_SW_OR_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: STS_OVERRIDE_IMP :: GMII_SPEED_UP_2G [06:06] */
-#define BCHP_SWITCH_CORE_STS_OVERRIDE_IMP_GMII_SPEED_UP_2G_MASK 0x00000040
-#define BCHP_SWITCH_CORE_STS_OVERRIDE_IMP_GMII_SPEED_UP_2G_SHIFT 6
-#define BCHP_SWITCH_CORE_STS_OVERRIDE_IMP_GMII_SPEED_UP_2G_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: STS_OVERRIDE_IMP :: TXFLOW_CNTL [05:05] */
-#define BCHP_SWITCH_CORE_STS_OVERRIDE_IMP_TXFLOW_CNTL_MASK 0x00000020
-#define BCHP_SWITCH_CORE_STS_OVERRIDE_IMP_TXFLOW_CNTL_SHIFT 5
-#define BCHP_SWITCH_CORE_STS_OVERRIDE_IMP_TXFLOW_CNTL_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: STS_OVERRIDE_IMP :: RXFLOW_CNTL [04:04] */
-#define BCHP_SWITCH_CORE_STS_OVERRIDE_IMP_RXFLOW_CNTL_MASK 0x00000010
-#define BCHP_SWITCH_CORE_STS_OVERRIDE_IMP_RXFLOW_CNTL_SHIFT 4
-#define BCHP_SWITCH_CORE_STS_OVERRIDE_IMP_RXFLOW_CNTL_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: STS_OVERRIDE_IMP :: SPEED [03:02] */
-#define BCHP_SWITCH_CORE_STS_OVERRIDE_IMP_SPEED_MASK 0x0000000c
-#define BCHP_SWITCH_CORE_STS_OVERRIDE_IMP_SPEED_SHIFT 2
-#define BCHP_SWITCH_CORE_STS_OVERRIDE_IMP_SPEED_DEFAULT 0x00000002
-
-/* SWITCH_CORE :: STS_OVERRIDE_IMP :: DUPLX_MODE [01:01] */
-#define BCHP_SWITCH_CORE_STS_OVERRIDE_IMP_DUPLX_MODE_MASK 0x00000002
-#define BCHP_SWITCH_CORE_STS_OVERRIDE_IMP_DUPLX_MODE_SHIFT 1
-#define BCHP_SWITCH_CORE_STS_OVERRIDE_IMP_DUPLX_MODE_DEFAULT 0x00000001
-
-/* SWITCH_CORE :: STS_OVERRIDE_IMP :: LINK_STS [00:00] */
-#define BCHP_SWITCH_CORE_STS_OVERRIDE_IMP_LINK_STS_MASK 0x00000001
-#define BCHP_SWITCH_CORE_STS_OVERRIDE_IMP_LINK_STS_SHIFT 0
-#define BCHP_SWITCH_CORE_STS_OVERRIDE_IMP_LINK_STS_DEFAULT 0x00000000
-
-/***************************************************************************
- *DEBUG_REG - Debug Control Register(Not2Release)
- ***************************************************************************/
-/* SWITCH_CORE :: DEBUG_REG :: reserved_for_padding0 [31:08] */
-#define BCHP_SWITCH_CORE_DEBUG_REG_reserved_for_padding0_MASK 0xffffff00
-#define BCHP_SWITCH_CORE_DEBUG_REG_reserved_for_padding0_SHIFT 8
-
-/* SWITCH_CORE :: DEBUG_REG :: PROBE_SOC_DMU_CLK [07:07] */
-#define BCHP_SWITCH_CORE_DEBUG_REG_PROBE_SOC_DMU_CLK_MASK 0x00000080
-#define BCHP_SWITCH_CORE_DEBUG_REG_PROBE_SOC_DMU_CLK_SHIFT 7
-#define BCHP_SWITCH_CORE_DEBUG_REG_PROBE_SOC_DMU_CLK_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: DEBUG_REG :: DEBUG_SEL [06:01] */
-#define BCHP_SWITCH_CORE_DEBUG_REG_DEBUG_SEL_MASK 0x0000007e
-#define BCHP_SWITCH_CORE_DEBUG_REG_DEBUG_SEL_SHIFT 1
-#define BCHP_SWITCH_CORE_DEBUG_REG_DEBUG_SEL_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: DEBUG_REG :: EN_DEBUG [00:00] */
-#define BCHP_SWITCH_CORE_DEBUG_REG_EN_DEBUG_MASK 0x00000001
-#define BCHP_SWITCH_CORE_DEBUG_REG_EN_DEBUG_SHIFT 0
-#define BCHP_SWITCH_CORE_DEBUG_REG_EN_DEBUG_DEFAULT 0x00000000
-
-/***************************************************************************
- *RM_PINS_DEBUG - Removed Pins Debug Register(Not2Release)
- ***************************************************************************/
-/* SWITCH_CORE :: RM_PINS_DEBUG :: reserved_for_padding0 [31:08] */
-#define BCHP_SWITCH_CORE_RM_PINS_DEBUG_reserved_for_padding0_MASK 0xffffff00
-#define BCHP_SWITCH_CORE_RM_PINS_DEBUG_reserved_for_padding0_SHIFT 8
-
-/* SWITCH_CORE :: RM_PINS_DEBUG :: SWITCH_RESV [07:03] */
-#define BCHP_SWITCH_CORE_RM_PINS_DEBUG_SWITCH_RESV_MASK 0x000000f8
-#define BCHP_SWITCH_CORE_RM_PINS_DEBUG_SWITCH_RESV_SHIFT 3
-#define BCHP_SWITCH_CORE_RM_PINS_DEBUG_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: RM_PINS_DEBUG :: DIS_IMP_PIN [02:02] */
-#define BCHP_SWITCH_CORE_RM_PINS_DEBUG_DIS_IMP_PIN_MASK 0x00000004
-#define BCHP_SWITCH_CORE_RM_PINS_DEBUG_DIS_IMP_PIN_SHIFT 2
-#define BCHP_SWITCH_CORE_RM_PINS_DEBUG_DIS_IMP_PIN_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: RM_PINS_DEBUG :: ENFDXFLOW_PIN [01:01] */
-#define BCHP_SWITCH_CORE_RM_PINS_DEBUG_ENFDXFLOW_PIN_MASK 0x00000002
-#define BCHP_SWITCH_CORE_RM_PINS_DEBUG_ENFDXFLOW_PIN_SHIFT 1
-#define BCHP_SWITCH_CORE_RM_PINS_DEBUG_ENFDXFLOW_PIN_DEFAULT 0x00000001
-
-/* SWITCH_CORE :: RM_PINS_DEBUG :: ENHDXFLOW_PIN [00:00] */
-#define BCHP_SWITCH_CORE_RM_PINS_DEBUG_ENHDXFLOW_PIN_MASK 0x00000001
-#define BCHP_SWITCH_CORE_RM_PINS_DEBUG_ENHDXFLOW_PIN_SHIFT 0
-#define BCHP_SWITCH_CORE_RM_PINS_DEBUG_ENHDXFLOW_PIN_DEFAULT 0x00000001
-
-/***************************************************************************
- *NEW_CTRL - New Control Register
- ***************************************************************************/
-/* SWITCH_CORE :: NEW_CTRL :: reserved_for_padding0 [31:08] */
-#define BCHP_SWITCH_CORE_NEW_CTRL_reserved_for_padding0_MASK 0xffffff00
-#define BCHP_SWITCH_CORE_NEW_CTRL_reserved_for_padding0_SHIFT 8
-
-/* SWITCH_CORE :: NEW_CTRL :: MC_FWD_EN [07:07] */
-#define BCHP_SWITCH_CORE_NEW_CTRL_MC_FWD_EN_MASK 0x00000080
-#define BCHP_SWITCH_CORE_NEW_CTRL_MC_FWD_EN_SHIFT 7
-#define BCHP_SWITCH_CORE_NEW_CTRL_MC_FWD_EN_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: NEW_CTRL :: UC_FWD_EN [06:06] */
-#define BCHP_SWITCH_CORE_NEW_CTRL_UC_FWD_EN_MASK 0x00000040
-#define BCHP_SWITCH_CORE_NEW_CTRL_UC_FWD_EN_SHIFT 6
-#define BCHP_SWITCH_CORE_NEW_CTRL_UC_FWD_EN_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: NEW_CTRL :: EN_AUTO_PD_WAR [05:05] */
-#define BCHP_SWITCH_CORE_NEW_CTRL_EN_AUTO_PD_WAR_MASK 0x00000020
-#define BCHP_SWITCH_CORE_NEW_CTRL_EN_AUTO_PD_WAR_SHIFT 5
-#define BCHP_SWITCH_CORE_NEW_CTRL_EN_AUTO_PD_WAR_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: NEW_CTRL :: OVERRIDE_AUTO_PD_WAR [04:04] */
-#define BCHP_SWITCH_CORE_NEW_CTRL_OVERRIDE_AUTO_PD_WAR_MASK 0x00000010
-#define BCHP_SWITCH_CORE_NEW_CTRL_OVERRIDE_AUTO_PD_WAR_SHIFT 4
-#define BCHP_SWITCH_CORE_NEW_CTRL_OVERRIDE_AUTO_PD_WAR_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: NEW_CTRL :: CABLE_DIAG_LEN [03:03] */
-#define BCHP_SWITCH_CORE_NEW_CTRL_CABLE_DIAG_LEN_MASK 0x00000008
-#define BCHP_SWITCH_CORE_NEW_CTRL_CABLE_DIAG_LEN_SHIFT 3
-#define BCHP_SWITCH_CORE_NEW_CTRL_CABLE_DIAG_LEN_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: NEW_CTRL :: INRANGEERR_DISCARD [02:02] */
-#define BCHP_SWITCH_CORE_NEW_CTRL_INRANGEERR_DISCARD_MASK 0x00000004
-#define BCHP_SWITCH_CORE_NEW_CTRL_INRANGEERR_DISCARD_SHIFT 2
-#define BCHP_SWITCH_CORE_NEW_CTRL_INRANGEERR_DISCARD_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: NEW_CTRL :: OUTRANGEERR_DISCARD [01:01] */
-#define BCHP_SWITCH_CORE_NEW_CTRL_OUTRANGEERR_DISCARD_MASK 0x00000002
-#define BCHP_SWITCH_CORE_NEW_CTRL_OUTRANGEERR_DISCARD_SHIFT 1
-#define BCHP_SWITCH_CORE_NEW_CTRL_OUTRANGEERR_DISCARD_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: NEW_CTRL :: IP_MC [00:00] */
-#define BCHP_SWITCH_CORE_NEW_CTRL_IP_MC_MASK 0x00000001
-#define BCHP_SWITCH_CORE_NEW_CTRL_IP_MC_SHIFT 0
-#define BCHP_SWITCH_CORE_NEW_CTRL_IP_MC_DEFAULT 0x00000001
-
-/***************************************************************************
- *SWITCH_CTRL - Switch Control Register (Not2Release)
- ***************************************************************************/
-/* SWITCH_CORE :: SWITCH_CTRL :: reserved_for_padding0 [31:16] */
-#define BCHP_SWITCH_CORE_SWITCH_CTRL_reserved_for_padding0_MASK 0xffff0000
-#define BCHP_SWITCH_CORE_SWITCH_CTRL_reserved_for_padding0_SHIFT 16
-
-/* SWITCH_CORE :: SWITCH_CTRL :: SWITCH_RESV_1 [15:07] */
-#define BCHP_SWITCH_CORE_SWITCH_CTRL_SWITCH_RESV_1_MASK 0x0000ff80
-#define BCHP_SWITCH_CORE_SWITCH_CTRL_SWITCH_RESV_1_SHIFT 7
-#define BCHP_SWITCH_CORE_SWITCH_CTRL_SWITCH_RESV_1_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: SWITCH_CTRL :: MII_DUMB_FWDG_EN [06:06] */
-#define BCHP_SWITCH_CORE_SWITCH_CTRL_MII_DUMB_FWDG_EN_MASK 0x00000040
-#define BCHP_SWITCH_CORE_SWITCH_CTRL_MII_DUMB_FWDG_EN_SHIFT 6
-#define BCHP_SWITCH_CORE_SWITCH_CTRL_MII_DUMB_FWDG_EN_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: SWITCH_CTRL :: SWITCH_RESV_0 [05:04] */
-#define BCHP_SWITCH_CORE_SWITCH_CTRL_SWITCH_RESV_0_MASK 0x00000030
-#define BCHP_SWITCH_CORE_SWITCH_CTRL_SWITCH_RESV_0_SHIFT 4
-#define BCHP_SWITCH_CORE_SWITCH_CTRL_SWITCH_RESV_0_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: SWITCH_CTRL :: GPHY_PLLBYPASS [03:03] */
-#define BCHP_SWITCH_CORE_SWITCH_CTRL_GPHY_PLLBYPASS_MASK 0x00000008
-#define BCHP_SWITCH_CORE_SWITCH_CTRL_GPHY_PLLBYPASS_SHIFT 3
-#define BCHP_SWITCH_CORE_SWITCH_CTRL_GPHY_PLLBYPASS_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: SWITCH_CTRL :: MII3_VOL_SEL [02:02] */
-#define BCHP_SWITCH_CORE_SWITCH_CTRL_MII3_VOL_SEL_MASK 0x00000004
-#define BCHP_SWITCH_CORE_SWITCH_CTRL_MII3_VOL_SEL_SHIFT 2
-#define BCHP_SWITCH_CORE_SWITCH_CTRL_MII3_VOL_SEL_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: SWITCH_CTRL :: MII2_VOL_SEL [01:01] */
-#define BCHP_SWITCH_CORE_SWITCH_CTRL_MII2_VOL_SEL_MASK 0x00000002
-#define BCHP_SWITCH_CORE_SWITCH_CTRL_MII2_VOL_SEL_SHIFT 1
-#define BCHP_SWITCH_CORE_SWITCH_CTRL_MII2_VOL_SEL_DEFAULT 0x00000001
-
-/* SWITCH_CORE :: SWITCH_CTRL :: MII1_VOL_SEL [00:00] */
-#define BCHP_SWITCH_CORE_SWITCH_CTRL_MII1_VOL_SEL_MASK 0x00000001
-#define BCHP_SWITCH_CORE_SWITCH_CTRL_MII1_VOL_SEL_SHIFT 0
-#define BCHP_SWITCH_CORE_SWITCH_CTRL_MII1_VOL_SEL_DEFAULT 0x00000000
-
-/***************************************************************************
- *PROTECTED_SEL - Protected Port Select Register
- ***************************************************************************/
-/* SWITCH_CORE :: PROTECTED_SEL :: reserved_for_padding0 [31:16] */
-#define BCHP_SWITCH_CORE_PROTECTED_SEL_reserved_for_padding0_MASK 0xffff0000
-#define BCHP_SWITCH_CORE_PROTECTED_SEL_reserved_for_padding0_SHIFT 16
-
-/* SWITCH_CORE :: PROTECTED_SEL :: SWITCH_RESV [15:09] */
-#define BCHP_SWITCH_CORE_PROTECTED_SEL_SWITCH_RESV_MASK 0x0000fe00
-#define BCHP_SWITCH_CORE_PROTECTED_SEL_SWITCH_RESV_SHIFT 9
-#define BCHP_SWITCH_CORE_PROTECTED_SEL_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: PROTECTED_SEL :: PORT_SEL [08:00] */
-#define BCHP_SWITCH_CORE_PROTECTED_SEL_PORT_SEL_MASK 0x000001ff
-#define BCHP_SWITCH_CORE_PROTECTED_SEL_PORT_SEL_SHIFT 0
-#define BCHP_SWITCH_CORE_PROTECTED_SEL_PORT_SEL_DEFAULT 0x00000000
-
-/***************************************************************************
- *WAN_PORT_SEL - WAN Port select Register
- ***************************************************************************/
-/* SWITCH_CORE :: WAN_PORT_SEL :: reserved_for_padding0 [31:16] */
-#define BCHP_SWITCH_CORE_WAN_PORT_SEL_reserved_for_padding0_MASK 0xffff0000
-#define BCHP_SWITCH_CORE_WAN_PORT_SEL_reserved_for_padding0_SHIFT 16
-
-/* SWITCH_CORE :: WAN_PORT_SEL :: SWITCH_RESV_1 [15:10] */
-#define BCHP_SWITCH_CORE_WAN_PORT_SEL_SWITCH_RESV_1_MASK 0x0000fc00
-#define BCHP_SWITCH_CORE_WAN_PORT_SEL_SWITCH_RESV_1_SHIFT 10
-#define BCHP_SWITCH_CORE_WAN_PORT_SEL_SWITCH_RESV_1_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: WAN_PORT_SEL :: EN_MAN2WAN [09:09] */
-#define BCHP_SWITCH_CORE_WAN_PORT_SEL_EN_MAN2WAN_MASK 0x00000200
-#define BCHP_SWITCH_CORE_WAN_PORT_SEL_EN_MAN2WAN_SHIFT 9
-#define BCHP_SWITCH_CORE_WAN_PORT_SEL_EN_MAN2WAN_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: WAN_PORT_SEL :: SWITCH_RESV_0 [08:08] */
-#define BCHP_SWITCH_CORE_WAN_PORT_SEL_SWITCH_RESV_0_MASK 0x00000100
-#define BCHP_SWITCH_CORE_WAN_PORT_SEL_SWITCH_RESV_0_SHIFT 8
-#define BCHP_SWITCH_CORE_WAN_PORT_SEL_SWITCH_RESV_0_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: WAN_PORT_SEL :: WAN_SELECT [07:00] */
-#define BCHP_SWITCH_CORE_WAN_PORT_SEL_WAN_SELECT_MASK 0x000000ff
-#define BCHP_SWITCH_CORE_WAN_PORT_SEL_WAN_SELECT_SHIFT 0
-#define BCHP_SWITCH_CORE_WAN_PORT_SEL_WAN_SELECT_DEFAULT 0x00000000
-
-/***************************************************************************
- *PAUSE_CAP - PAUSE Capability Register
- ***************************************************************************/
-/* SWITCH_CORE :: PAUSE_CAP :: SWITCH_RESV_1 [31:24] */
-#define BCHP_SWITCH_CORE_PAUSE_CAP_SWITCH_RESV_1_MASK 0xff000000
-#define BCHP_SWITCH_CORE_PAUSE_CAP_SWITCH_RESV_1_SHIFT 24
-#define BCHP_SWITCH_CORE_PAUSE_CAP_SWITCH_RESV_1_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: PAUSE_CAP :: EN_OVERRIDE [23:23] */
-#define BCHP_SWITCH_CORE_PAUSE_CAP_EN_OVERRIDE_MASK 0x00800000
-#define BCHP_SWITCH_CORE_PAUSE_CAP_EN_OVERRIDE_SHIFT 23
-#define BCHP_SWITCH_CORE_PAUSE_CAP_EN_OVERRIDE_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: PAUSE_CAP :: SWITCH_RESV [22:18] */
-#define BCHP_SWITCH_CORE_PAUSE_CAP_SWITCH_RESV_MASK 0x007c0000
-#define BCHP_SWITCH_CORE_PAUSE_CAP_SWITCH_RESV_SHIFT 18
-#define BCHP_SWITCH_CORE_PAUSE_CAP_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: PAUSE_CAP :: RX_PAUSE_CAP [17:09] */
-#define BCHP_SWITCH_CORE_PAUSE_CAP_RX_PAUSE_CAP_MASK 0x0003fe00
-#define BCHP_SWITCH_CORE_PAUSE_CAP_RX_PAUSE_CAP_SHIFT 9
-#define BCHP_SWITCH_CORE_PAUSE_CAP_RX_PAUSE_CAP_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: PAUSE_CAP :: TX_PAUSE_CAP [08:00] */
-#define BCHP_SWITCH_CORE_PAUSE_CAP_TX_PAUSE_CAP_MASK 0x000001ff
-#define BCHP_SWITCH_CORE_PAUSE_CAP_TX_PAUSE_CAP_SHIFT 0
-#define BCHP_SWITCH_CORE_PAUSE_CAP_TX_PAUSE_CAP_DEFAULT 0x00000000
-
-/***************************************************************************
- *RSV_MCAST_CTRL - Reserved Multicast Register
- ***************************************************************************/
-/* SWITCH_CORE :: RSV_MCAST_CTRL :: reserved_for_padding0 [31:08] */
-#define BCHP_SWITCH_CORE_RSV_MCAST_CTRL_reserved_for_padding0_MASK 0xffffff00
-#define BCHP_SWITCH_CORE_RSV_MCAST_CTRL_reserved_for_padding0_SHIFT 8
-
-/* SWITCH_CORE :: RSV_MCAST_CTRL :: EN_RES_MUL_LEARN [07:07] */
-#define BCHP_SWITCH_CORE_RSV_MCAST_CTRL_EN_RES_MUL_LEARN_MASK 0x00000080
-#define BCHP_SWITCH_CORE_RSV_MCAST_CTRL_EN_RES_MUL_LEARN_SHIFT 7
-#define BCHP_SWITCH_CORE_RSV_MCAST_CTRL_EN_RES_MUL_LEARN_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: RSV_MCAST_CTRL :: SWITCH_RESV [06:05] */
-#define BCHP_SWITCH_CORE_RSV_MCAST_CTRL_SWITCH_RESV_MASK 0x00000060
-#define BCHP_SWITCH_CORE_RSV_MCAST_CTRL_SWITCH_RESV_SHIFT 5
-#define BCHP_SWITCH_CORE_RSV_MCAST_CTRL_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: RSV_MCAST_CTRL :: EN_MUL_4 [04:04] */
-#define BCHP_SWITCH_CORE_RSV_MCAST_CTRL_EN_MUL_4_MASK 0x00000010
-#define BCHP_SWITCH_CORE_RSV_MCAST_CTRL_EN_MUL_4_SHIFT 4
-#define BCHP_SWITCH_CORE_RSV_MCAST_CTRL_EN_MUL_4_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: RSV_MCAST_CTRL :: EN_MUL_3 [03:03] */
-#define BCHP_SWITCH_CORE_RSV_MCAST_CTRL_EN_MUL_3_MASK 0x00000008
-#define BCHP_SWITCH_CORE_RSV_MCAST_CTRL_EN_MUL_3_SHIFT 3
-#define BCHP_SWITCH_CORE_RSV_MCAST_CTRL_EN_MUL_3_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: RSV_MCAST_CTRL :: EN_MUL_2 [02:02] */
-#define BCHP_SWITCH_CORE_RSV_MCAST_CTRL_EN_MUL_2_MASK 0x00000004
-#define BCHP_SWITCH_CORE_RSV_MCAST_CTRL_EN_MUL_2_SHIFT 2
-#define BCHP_SWITCH_CORE_RSV_MCAST_CTRL_EN_MUL_2_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: RSV_MCAST_CTRL :: EN_MUL_1 [01:01] */
-#define BCHP_SWITCH_CORE_RSV_MCAST_CTRL_EN_MUL_1_MASK 0x00000002
-#define BCHP_SWITCH_CORE_RSV_MCAST_CTRL_EN_MUL_1_SHIFT 1
-#define BCHP_SWITCH_CORE_RSV_MCAST_CTRL_EN_MUL_1_DEFAULT 0x00000001
-
-/* SWITCH_CORE :: RSV_MCAST_CTRL :: EN_MUL_0 [00:00] */
-#define BCHP_SWITCH_CORE_RSV_MCAST_CTRL_EN_MUL_0_MASK 0x00000001
-#define BCHP_SWITCH_CORE_RSV_MCAST_CTRL_EN_MUL_0_SHIFT 0
-#define BCHP_SWITCH_CORE_RSV_MCAST_CTRL_EN_MUL_0_DEFAULT 0x00000000
-
-/***************************************************************************
- *TXQ_FLUSH_MODE - TxQ Flush Mode Control Register(Not2Release)
- ***************************************************************************/
-/* SWITCH_CORE :: TXQ_FLUSH_MODE :: reserved_for_padding0 [31:08] */
-#define BCHP_SWITCH_CORE_TXQ_FLUSH_MODE_reserved_for_padding0_MASK 0xffffff00
-#define BCHP_SWITCH_CORE_TXQ_FLUSH_MODE_reserved_for_padding0_SHIFT 8
-
-/* SWITCH_CORE :: TXQ_FLUSH_MODE :: EN_NEW_BOFF_SEED [07:07] */
-#define BCHP_SWITCH_CORE_TXQ_FLUSH_MODE_EN_NEW_BOFF_SEED_MASK 0x00000080
-#define BCHP_SWITCH_CORE_TXQ_FLUSH_MODE_EN_NEW_BOFF_SEED_SHIFT 7
-#define BCHP_SWITCH_CORE_TXQ_FLUSH_MODE_EN_NEW_BOFF_SEED_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: TXQ_FLUSH_MODE :: EN_LATECOl65_DROP [06:06] */
-#define BCHP_SWITCH_CORE_TXQ_FLUSH_MODE_EN_LATECOl65_DROP_MASK 0x00000040
-#define BCHP_SWITCH_CORE_TXQ_FLUSH_MODE_EN_LATECOl65_DROP_SHIFT 6
-#define BCHP_SWITCH_CORE_TXQ_FLUSH_MODE_EN_LATECOl65_DROP_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: TXQ_FLUSH_MODE :: EN_ECOL_TXFM_MASK [05:05] */
-#define BCHP_SWITCH_CORE_TXQ_FLUSH_MODE_EN_ECOL_TXFM_MASK_MASK 0x00000020
-#define BCHP_SWITCH_CORE_TXQ_FLUSH_MODE_EN_ECOL_TXFM_MASK_SHIFT 5
-#define BCHP_SWITCH_CORE_TXQ_FLUSH_MODE_EN_ECOL_TXFM_MASK_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: TXQ_FLUSH_MODE :: EN_LCOL_TXFM_MASK [04:04] */
-#define BCHP_SWITCH_CORE_TXQ_FLUSH_MODE_EN_LCOL_TXFM_MASK_MASK 0x00000010
-#define BCHP_SWITCH_CORE_TXQ_FLUSH_MODE_EN_LCOL_TXFM_MASK_SHIFT 4
-#define BCHP_SWITCH_CORE_TXQ_FLUSH_MODE_EN_LCOL_TXFM_MASK_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: TXQ_FLUSH_MODE :: EN_RELOAD_ERR_PATH [03:03] */
-#define BCHP_SWITCH_CORE_TXQ_FLUSH_MODE_EN_RELOAD_ERR_PATH_MASK 0x00000008
-#define BCHP_SWITCH_CORE_TXQ_FLUSH_MODE_EN_RELOAD_ERR_PATH_SHIFT 3
-#define BCHP_SWITCH_CORE_TXQ_FLUSH_MODE_EN_RELOAD_ERR_PATH_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: TXQ_FLUSH_MODE :: EN_LCOL_FLUSH [02:02] */
-#define BCHP_SWITCH_CORE_TXQ_FLUSH_MODE_EN_LCOL_FLUSH_MASK 0x00000004
-#define BCHP_SWITCH_CORE_TXQ_FLUSH_MODE_EN_LCOL_FLUSH_SHIFT 2
-#define BCHP_SWITCH_CORE_TXQ_FLUSH_MODE_EN_LCOL_FLUSH_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: TXQ_FLUSH_MODE :: DIS_NEW_TXDIS [01:01] */
-#define BCHP_SWITCH_CORE_TXQ_FLUSH_MODE_DIS_NEW_TXDIS_MASK 0x00000002
-#define BCHP_SWITCH_CORE_TXQ_FLUSH_MODE_DIS_NEW_TXDIS_SHIFT 1
-#define BCHP_SWITCH_CORE_TXQ_FLUSH_MODE_DIS_NEW_TXDIS_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: TXQ_FLUSH_MODE :: BYPASS_FASTTXDSC_PATH [00:00] */
-#define BCHP_SWITCH_CORE_TXQ_FLUSH_MODE_BYPASS_FASTTXDSC_PATH_MASK 0x00000001
-#define BCHP_SWITCH_CORE_TXQ_FLUSH_MODE_BYPASS_FASTTXDSC_PATH_SHIFT 0
-#define BCHP_SWITCH_CORE_TXQ_FLUSH_MODE_BYPASS_FASTTXDSC_PATH_DEFAULT 0x00000000
-
-/***************************************************************************
- *ULF_DROP_MAP - Unicast Lookup Failed Forward Map Register
- ***************************************************************************/
-/* SWITCH_CORE :: ULF_DROP_MAP :: reserved_for_padding0 [31:16] */
-#define BCHP_SWITCH_CORE_ULF_DROP_MAP_reserved_for_padding0_MASK 0xffff0000
-#define BCHP_SWITCH_CORE_ULF_DROP_MAP_reserved_for_padding0_SHIFT 16
-
-/* SWITCH_CORE :: ULF_DROP_MAP :: SWITCH_RESV [15:09] */
-#define BCHP_SWITCH_CORE_ULF_DROP_MAP_SWITCH_RESV_MASK 0x0000fe00
-#define BCHP_SWITCH_CORE_ULF_DROP_MAP_SWITCH_RESV_SHIFT 9
-#define BCHP_SWITCH_CORE_ULF_DROP_MAP_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: ULF_DROP_MAP :: UNI_LOOKUP_FAIL_FWD_MAP [08:00] */
-#define BCHP_SWITCH_CORE_ULF_DROP_MAP_UNI_LOOKUP_FAIL_FWD_MAP_MASK 0x000001ff
-#define BCHP_SWITCH_CORE_ULF_DROP_MAP_UNI_LOOKUP_FAIL_FWD_MAP_SHIFT 0
-#define BCHP_SWITCH_CORE_ULF_DROP_MAP_UNI_LOOKUP_FAIL_FWD_MAP_DEFAULT 0x00000000
-
-/***************************************************************************
- *MLF_DROP_MAP - Multicast Lookup Failed Forward Map Register
- ***************************************************************************/
-/* SWITCH_CORE :: MLF_DROP_MAP :: reserved_for_padding0 [31:16] */
-#define BCHP_SWITCH_CORE_MLF_DROP_MAP_reserved_for_padding0_MASK 0xffff0000
-#define BCHP_SWITCH_CORE_MLF_DROP_MAP_reserved_for_padding0_SHIFT 16
-
-/* SWITCH_CORE :: MLF_DROP_MAP :: SWITCH_RESV [15:09] */
-#define BCHP_SWITCH_CORE_MLF_DROP_MAP_SWITCH_RESV_MASK 0x0000fe00
-#define BCHP_SWITCH_CORE_MLF_DROP_MAP_SWITCH_RESV_SHIFT 9
-#define BCHP_SWITCH_CORE_MLF_DROP_MAP_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: MLF_DROP_MAP :: MUL_LOOKUP_FAIL_FRW_MAP [08:00] */
-#define BCHP_SWITCH_CORE_MLF_DROP_MAP_MUL_LOOKUP_FAIL_FRW_MAP_MASK 0x000001ff
-#define BCHP_SWITCH_CORE_MLF_DROP_MAP_MUL_LOOKUP_FAIL_FRW_MAP_SHIFT 0
-#define BCHP_SWITCH_CORE_MLF_DROP_MAP_MUL_LOOKUP_FAIL_FRW_MAP_DEFAULT 0x00000000
-
-/***************************************************************************
- *MLF_IPMC_FWD_MAP - IPMC Forward Map Register
- ***************************************************************************/
-/* SWITCH_CORE :: MLF_IPMC_FWD_MAP :: reserved_for_padding0 [31:16] */
-#define BCHP_SWITCH_CORE_MLF_IPMC_FWD_MAP_reserved_for_padding0_MASK 0xffff0000
-#define BCHP_SWITCH_CORE_MLF_IPMC_FWD_MAP_reserved_for_padding0_SHIFT 16
-
-/* SWITCH_CORE :: MLF_IPMC_FWD_MAP :: SWITCH_RESV [15:09] */
-#define BCHP_SWITCH_CORE_MLF_IPMC_FWD_MAP_SWITCH_RESV_MASK 0x0000fe00
-#define BCHP_SWITCH_CORE_MLF_IPMC_FWD_MAP_SWITCH_RESV_SHIFT 9
-#define BCHP_SWITCH_CORE_MLF_IPMC_FWD_MAP_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: MLF_IPMC_FWD_MAP :: MLF_IPMC_FWD_MAP [08:00] */
-#define BCHP_SWITCH_CORE_MLF_IPMC_FWD_MAP_MLF_IPMC_FWD_MAP_MASK 0x000001ff
-#define BCHP_SWITCH_CORE_MLF_IPMC_FWD_MAP_MLF_IPMC_FWD_MAP_SHIFT 0
-#define BCHP_SWITCH_CORE_MLF_IPMC_FWD_MAP_MLF_IPMC_FWD_MAP_DEFAULT 0x00000000
-
-/***************************************************************************
- *RX_PAUSE_PASS - Pause pass Through for RX Register
- ***************************************************************************/
-/* SWITCH_CORE :: RX_PAUSE_PASS :: reserved_for_padding0 [31:16] */
-#define BCHP_SWITCH_CORE_RX_PAUSE_PASS_reserved_for_padding0_MASK 0xffff0000
-#define BCHP_SWITCH_CORE_RX_PAUSE_PASS_reserved_for_padding0_SHIFT 16
-
-/* SWITCH_CORE :: RX_PAUSE_PASS :: SWITCH_RESV_1 [15:09] */
-#define BCHP_SWITCH_CORE_RX_PAUSE_PASS_SWITCH_RESV_1_MASK 0x0000fe00
-#define BCHP_SWITCH_CORE_RX_PAUSE_PASS_SWITCH_RESV_1_SHIFT 9
-#define BCHP_SWITCH_CORE_RX_PAUSE_PASS_SWITCH_RESV_1_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: RX_PAUSE_PASS :: SWITCH_RESV_0 [08:08] */
-#define BCHP_SWITCH_CORE_RX_PAUSE_PASS_SWITCH_RESV_0_MASK 0x00000100
-#define BCHP_SWITCH_CORE_RX_PAUSE_PASS_SWITCH_RESV_0_SHIFT 8
-#define BCHP_SWITCH_CORE_RX_PAUSE_PASS_SWITCH_RESV_0_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: RX_PAUSE_PASS :: RX_PAUSE_PASS [07:00] */
-#define BCHP_SWITCH_CORE_RX_PAUSE_PASS_RX_PAUSE_PASS_MASK 0x000000ff
-#define BCHP_SWITCH_CORE_RX_PAUSE_PASS_RX_PAUSE_PASS_SHIFT 0
-#define BCHP_SWITCH_CORE_RX_PAUSE_PASS_RX_PAUSE_PASS_DEFAULT 0x00000000
-
-/***************************************************************************
- *TX_PAUSE_PASS - Pause pass Through for TX Register
- ***************************************************************************/
-/* SWITCH_CORE :: TX_PAUSE_PASS :: reserved_for_padding0 [31:16] */
-#define BCHP_SWITCH_CORE_TX_PAUSE_PASS_reserved_for_padding0_MASK 0xffff0000
-#define BCHP_SWITCH_CORE_TX_PAUSE_PASS_reserved_for_padding0_SHIFT 16
-
-/* SWITCH_CORE :: TX_PAUSE_PASS :: SWITCH_RESV [15:09] */
-#define BCHP_SWITCH_CORE_TX_PAUSE_PASS_SWITCH_RESV_MASK 0x0000fe00
-#define BCHP_SWITCH_CORE_TX_PAUSE_PASS_SWITCH_RESV_SHIFT 9
-#define BCHP_SWITCH_CORE_TX_PAUSE_PASS_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: TX_PAUSE_PASS :: TX_PAUSE_PASS [08:00] */
-#define BCHP_SWITCH_CORE_TX_PAUSE_PASS_TX_PAUSE_PASS_MASK 0x000001ff
-#define BCHP_SWITCH_CORE_TX_PAUSE_PASS_TX_PAUSE_PASS_SHIFT 0
-#define BCHP_SWITCH_CORE_TX_PAUSE_PASS_TX_PAUSE_PASS_DEFAULT 0x00000000
-
-/***************************************************************************
- *DIS_LEARN - Disable Learning Register
- ***************************************************************************/
-/* SWITCH_CORE :: DIS_LEARN :: reserved_for_padding0 [31:16] */
-#define BCHP_SWITCH_CORE_DIS_LEARN_reserved_for_padding0_MASK 0xffff0000
-#define BCHP_SWITCH_CORE_DIS_LEARN_reserved_for_padding0_SHIFT 16
-
-/* SWITCH_CORE :: DIS_LEARN :: SWITCH_RESV [15:09] */
-#define BCHP_SWITCH_CORE_DIS_LEARN_SWITCH_RESV_MASK 0x0000fe00
-#define BCHP_SWITCH_CORE_DIS_LEARN_SWITCH_RESV_SHIFT 9
-#define BCHP_SWITCH_CORE_DIS_LEARN_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: DIS_LEARN :: DIS_LEARN [08:00] */
-#define BCHP_SWITCH_CORE_DIS_LEARN_DIS_LEARN_MASK 0x000001ff
-#define BCHP_SWITCH_CORE_DIS_LEARN_DIS_LEARN_SHIFT 0
-#define BCHP_SWITCH_CORE_DIS_LEARN_DIS_LEARN_DEFAULT 0x00000000
-
-/***************************************************************************
- *SFT_LRN_CTL - Software Learning Control
- ***************************************************************************/
-/* SWITCH_CORE :: SFT_LRN_CTL :: reserved_for_padding0 [31:16] */
-#define BCHP_SWITCH_CORE_SFT_LRN_CTL_reserved_for_padding0_MASK 0xffff0000
-#define BCHP_SWITCH_CORE_SFT_LRN_CTL_reserved_for_padding0_SHIFT 16
-
-/* SWITCH_CORE :: SFT_LRN_CTL :: SWITCH_RESV [15:09] */
-#define BCHP_SWITCH_CORE_SFT_LRN_CTL_SWITCH_RESV_MASK 0x0000fe00
-#define BCHP_SWITCH_CORE_SFT_LRN_CTL_SWITCH_RESV_SHIFT 9
-#define BCHP_SWITCH_CORE_SFT_LRN_CTL_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: SFT_LRN_CTL :: SW_LEARN_CNTL [08:00] */
-#define BCHP_SWITCH_CORE_SFT_LRN_CTL_SW_LEARN_CNTL_MASK 0x000001ff
-#define BCHP_SWITCH_CORE_SFT_LRN_CTL_SW_LEARN_CNTL_SHIFT 0
-#define BCHP_SWITCH_CORE_SFT_LRN_CTL_SW_LEARN_CNTL_DEFAULT 0x00000000
-
-/***************************************************************************
- *LOW_POWER_EXP1 - Low Power Expansion I Register
- ***************************************************************************/
-/* SWITCH_CORE :: LOW_POWER_EXP1 :: SWITCH_RESV_1 [31:25] */
-#define BCHP_SWITCH_CORE_LOW_POWER_EXP1_SWITCH_RESV_1_MASK 0xfe000000
-#define BCHP_SWITCH_CORE_LOW_POWER_EXP1_SWITCH_RESV_1_SHIFT 25
-#define BCHP_SWITCH_CORE_LOW_POWER_EXP1_SWITCH_RESV_1_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: LOW_POWER_EXP1 :: SLEEP_MACCLK_PORT [24:16] */
-#define BCHP_SWITCH_CORE_LOW_POWER_EXP1_SLEEP_MACCLK_PORT_MASK 0x01ff0000
-#define BCHP_SWITCH_CORE_LOW_POWER_EXP1_SLEEP_MACCLK_PORT_SHIFT 16
-#define BCHP_SWITCH_CORE_LOW_POWER_EXP1_SLEEP_MACCLK_PORT_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: LOW_POWER_EXP1 :: SWITCH_RESV_0 [15:09] */
-#define BCHP_SWITCH_CORE_LOW_POWER_EXP1_SWITCH_RESV_0_MASK 0x0000fe00
-#define BCHP_SWITCH_CORE_LOW_POWER_EXP1_SWITCH_RESV_0_SHIFT 9
-#define BCHP_SWITCH_CORE_LOW_POWER_EXP1_SWITCH_RESV_0_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: LOW_POWER_EXP1 :: SLEEP_SYSCLK_PORT [08:00] */
-#define BCHP_SWITCH_CORE_LOW_POWER_EXP1_SLEEP_SYSCLK_PORT_MASK 0x000001ff
-#define BCHP_SWITCH_CORE_LOW_POWER_EXP1_SLEEP_SYSCLK_PORT_SHIFT 0
-#define BCHP_SWITCH_CORE_LOW_POWER_EXP1_SLEEP_SYSCLK_PORT_DEFAULT 0x00000000
-
-/***************************************************************************
- *CTLREG_REG_SPARE - Spare Register (Not2Release)
- ***************************************************************************/
-/* SWITCH_CORE :: CTLREG_REG_SPARE :: CTLREG_REG_SPARE [31:00] */
-#define BCHP_SWITCH_CORE_CTLREG_REG_SPARE_CTLREG_REG_SPARE_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_CTLREG_REG_SPARE_CTLREG_REG_SPARE_SHIFT 0
-#define BCHP_SWITCH_CORE_CTLREG_REG_SPARE_CTLREG_REG_SPARE_DEFAULT 0x00000000
-
-/***************************************************************************
- *STS_OVERRIDE_GMIIP_Port_0 - Port N GMII Port States Override Register
- ***************************************************************************/
-/* SWITCH_CORE :: STS_OVERRIDE_GMIIP_Port_0 :: reserved_for_padding0 [31:08] */
-#define BCHP_SWITCH_CORE_STS_OVERRIDE_GMIIP_Port_0_reserved_for_padding0_MASK 0xffffff00
-#define BCHP_SWITCH_CORE_STS_OVERRIDE_GMIIP_Port_0_reserved_for_padding0_SHIFT 8
-
-/* SWITCH_CORE :: STS_OVERRIDE_GMIIP_Port_0 :: SWITCH_RESV_1 [07:07] */
-#define BCHP_SWITCH_CORE_STS_OVERRIDE_GMIIP_Port_0_SWITCH_RESV_1_MASK 0x00000080
-#define BCHP_SWITCH_CORE_STS_OVERRIDE_GMIIP_Port_0_SWITCH_RESV_1_SHIFT 7
-#define BCHP_SWITCH_CORE_STS_OVERRIDE_GMIIP_Port_0_SWITCH_RESV_1_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: STS_OVERRIDE_GMIIP_Port_0 :: SW_OVERRIDE [06:06] */
-#define BCHP_SWITCH_CORE_STS_OVERRIDE_GMIIP_Port_0_SW_OVERRIDE_MASK 0x00000040
-#define BCHP_SWITCH_CORE_STS_OVERRIDE_GMIIP_Port_0_SW_OVERRIDE_SHIFT 6
-#define BCHP_SWITCH_CORE_STS_OVERRIDE_GMIIP_Port_0_SW_OVERRIDE_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: STS_OVERRIDE_GMIIP_Port_0 :: TXFLOW_CNTL [05:05] */
-#define BCHP_SWITCH_CORE_STS_OVERRIDE_GMIIP_Port_0_TXFLOW_CNTL_MASK 0x00000020
-#define BCHP_SWITCH_CORE_STS_OVERRIDE_GMIIP_Port_0_TXFLOW_CNTL_SHIFT 5
-#define BCHP_SWITCH_CORE_STS_OVERRIDE_GMIIP_Port_0_TXFLOW_CNTL_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: STS_OVERRIDE_GMIIP_Port_0 :: RXFLOW_CNTL [04:04] */
-#define BCHP_SWITCH_CORE_STS_OVERRIDE_GMIIP_Port_0_RXFLOW_CNTL_MASK 0x00000010
-#define BCHP_SWITCH_CORE_STS_OVERRIDE_GMIIP_Port_0_RXFLOW_CNTL_SHIFT 4
-#define BCHP_SWITCH_CORE_STS_OVERRIDE_GMIIP_Port_0_RXFLOW_CNTL_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: STS_OVERRIDE_GMIIP_Port_0 :: SPEED [03:02] */
-#define BCHP_SWITCH_CORE_STS_OVERRIDE_GMIIP_Port_0_SPEED_MASK 0x0000000c
-#define BCHP_SWITCH_CORE_STS_OVERRIDE_GMIIP_Port_0_SPEED_SHIFT 2
-#define BCHP_SWITCH_CORE_STS_OVERRIDE_GMIIP_Port_0_SPEED_DEFAULT 0x00000002
-
-/* SWITCH_CORE :: STS_OVERRIDE_GMIIP_Port_0 :: DUPLX_MODE [01:01] */
-#define BCHP_SWITCH_CORE_STS_OVERRIDE_GMIIP_Port_0_DUPLX_MODE_MASK 0x00000002
-#define BCHP_SWITCH_CORE_STS_OVERRIDE_GMIIP_Port_0_DUPLX_MODE_SHIFT 1
-#define BCHP_SWITCH_CORE_STS_OVERRIDE_GMIIP_Port_0_DUPLX_MODE_DEFAULT 0x00000001
-
-/* SWITCH_CORE :: STS_OVERRIDE_GMIIP_Port_0 :: LINK_STS [00:00] */
-#define BCHP_SWITCH_CORE_STS_OVERRIDE_GMIIP_Port_0_LINK_STS_MASK 0x00000001
-#define BCHP_SWITCH_CORE_STS_OVERRIDE_GMIIP_Port_0_LINK_STS_SHIFT 0
-#define BCHP_SWITCH_CORE_STS_OVERRIDE_GMIIP_Port_0_LINK_STS_DEFAULT 0x00000001
-
-/***************************************************************************
- *STS_OVERRIDE_GMIIP_Port_1 - Port N GMII Port States Override Register
- ***************************************************************************/
-/* SWITCH_CORE :: STS_OVERRIDE_GMIIP_Port_1 :: reserved_for_padding0 [31:08] */
-#define BCHP_SWITCH_CORE_STS_OVERRIDE_GMIIP_Port_1_reserved_for_padding0_MASK 0xffffff00
-#define BCHP_SWITCH_CORE_STS_OVERRIDE_GMIIP_Port_1_reserved_for_padding0_SHIFT 8
-
-/* SWITCH_CORE :: STS_OVERRIDE_GMIIP_Port_1 :: SWITCH_RESV_1 [07:07] */
-#define BCHP_SWITCH_CORE_STS_OVERRIDE_GMIIP_Port_1_SWITCH_RESV_1_MASK 0x00000080
-#define BCHP_SWITCH_CORE_STS_OVERRIDE_GMIIP_Port_1_SWITCH_RESV_1_SHIFT 7
-#define BCHP_SWITCH_CORE_STS_OVERRIDE_GMIIP_Port_1_SWITCH_RESV_1_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: STS_OVERRIDE_GMIIP_Port_1 :: SW_OVERRIDE [06:06] */
-#define BCHP_SWITCH_CORE_STS_OVERRIDE_GMIIP_Port_1_SW_OVERRIDE_MASK 0x00000040
-#define BCHP_SWITCH_CORE_STS_OVERRIDE_GMIIP_Port_1_SW_OVERRIDE_SHIFT 6
-#define BCHP_SWITCH_CORE_STS_OVERRIDE_GMIIP_Port_1_SW_OVERRIDE_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: STS_OVERRIDE_GMIIP_Port_1 :: TXFLOW_CNTL [05:05] */
-#define BCHP_SWITCH_CORE_STS_OVERRIDE_GMIIP_Port_1_TXFLOW_CNTL_MASK 0x00000020
-#define BCHP_SWITCH_CORE_STS_OVERRIDE_GMIIP_Port_1_TXFLOW_CNTL_SHIFT 5
-#define BCHP_SWITCH_CORE_STS_OVERRIDE_GMIIP_Port_1_TXFLOW_CNTL_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: STS_OVERRIDE_GMIIP_Port_1 :: RXFLOW_CNTL [04:04] */
-#define BCHP_SWITCH_CORE_STS_OVERRIDE_GMIIP_Port_1_RXFLOW_CNTL_MASK 0x00000010
-#define BCHP_SWITCH_CORE_STS_OVERRIDE_GMIIP_Port_1_RXFLOW_CNTL_SHIFT 4
-#define BCHP_SWITCH_CORE_STS_OVERRIDE_GMIIP_Port_1_RXFLOW_CNTL_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: STS_OVERRIDE_GMIIP_Port_1 :: SPEED [03:02] */
-#define BCHP_SWITCH_CORE_STS_OVERRIDE_GMIIP_Port_1_SPEED_MASK 0x0000000c
-#define BCHP_SWITCH_CORE_STS_OVERRIDE_GMIIP_Port_1_SPEED_SHIFT 2
-#define BCHP_SWITCH_CORE_STS_OVERRIDE_GMIIP_Port_1_SPEED_DEFAULT 0x00000002
-
-/* SWITCH_CORE :: STS_OVERRIDE_GMIIP_Port_1 :: DUPLX_MODE [01:01] */
-#define BCHP_SWITCH_CORE_STS_OVERRIDE_GMIIP_Port_1_DUPLX_MODE_MASK 0x00000002
-#define BCHP_SWITCH_CORE_STS_OVERRIDE_GMIIP_Port_1_DUPLX_MODE_SHIFT 1
-#define BCHP_SWITCH_CORE_STS_OVERRIDE_GMIIP_Port_1_DUPLX_MODE_DEFAULT 0x00000001
-
-/* SWITCH_CORE :: STS_OVERRIDE_GMIIP_Port_1 :: LINK_STS [00:00] */
-#define BCHP_SWITCH_CORE_STS_OVERRIDE_GMIIP_Port_1_LINK_STS_MASK 0x00000001
-#define BCHP_SWITCH_CORE_STS_OVERRIDE_GMIIP_Port_1_LINK_STS_SHIFT 0
-#define BCHP_SWITCH_CORE_STS_OVERRIDE_GMIIP_Port_1_LINK_STS_DEFAULT 0x00000001
-
-/***************************************************************************
- *STS_OVERRIDE_GMIIP_Port_2 - Port N GMII Port States Override Register
- ***************************************************************************/
-/* SWITCH_CORE :: STS_OVERRIDE_GMIIP_Port_2 :: reserved_for_padding0 [31:08] */
-#define BCHP_SWITCH_CORE_STS_OVERRIDE_GMIIP_Port_2_reserved_for_padding0_MASK 0xffffff00
-#define BCHP_SWITCH_CORE_STS_OVERRIDE_GMIIP_Port_2_reserved_for_padding0_SHIFT 8
-
-/* SWITCH_CORE :: STS_OVERRIDE_GMIIP_Port_2 :: SWITCH_RESV_1 [07:07] */
-#define BCHP_SWITCH_CORE_STS_OVERRIDE_GMIIP_Port_2_SWITCH_RESV_1_MASK 0x00000080
-#define BCHP_SWITCH_CORE_STS_OVERRIDE_GMIIP_Port_2_SWITCH_RESV_1_SHIFT 7
-#define BCHP_SWITCH_CORE_STS_OVERRIDE_GMIIP_Port_2_SWITCH_RESV_1_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: STS_OVERRIDE_GMIIP_Port_2 :: SW_OVERRIDE [06:06] */
-#define BCHP_SWITCH_CORE_STS_OVERRIDE_GMIIP_Port_2_SW_OVERRIDE_MASK 0x00000040
-#define BCHP_SWITCH_CORE_STS_OVERRIDE_GMIIP_Port_2_SW_OVERRIDE_SHIFT 6
-#define BCHP_SWITCH_CORE_STS_OVERRIDE_GMIIP_Port_2_SW_OVERRIDE_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: STS_OVERRIDE_GMIIP_Port_2 :: TXFLOW_CNTL [05:05] */
-#define BCHP_SWITCH_CORE_STS_OVERRIDE_GMIIP_Port_2_TXFLOW_CNTL_MASK 0x00000020
-#define BCHP_SWITCH_CORE_STS_OVERRIDE_GMIIP_Port_2_TXFLOW_CNTL_SHIFT 5
-#define BCHP_SWITCH_CORE_STS_OVERRIDE_GMIIP_Port_2_TXFLOW_CNTL_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: STS_OVERRIDE_GMIIP_Port_2 :: RXFLOW_CNTL [04:04] */
-#define BCHP_SWITCH_CORE_STS_OVERRIDE_GMIIP_Port_2_RXFLOW_CNTL_MASK 0x00000010
-#define BCHP_SWITCH_CORE_STS_OVERRIDE_GMIIP_Port_2_RXFLOW_CNTL_SHIFT 4
-#define BCHP_SWITCH_CORE_STS_OVERRIDE_GMIIP_Port_2_RXFLOW_CNTL_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: STS_OVERRIDE_GMIIP_Port_2 :: SPEED [03:02] */
-#define BCHP_SWITCH_CORE_STS_OVERRIDE_GMIIP_Port_2_SPEED_MASK 0x0000000c
-#define BCHP_SWITCH_CORE_STS_OVERRIDE_GMIIP_Port_2_SPEED_SHIFT 2
-#define BCHP_SWITCH_CORE_STS_OVERRIDE_GMIIP_Port_2_SPEED_DEFAULT 0x00000002
-
-/* SWITCH_CORE :: STS_OVERRIDE_GMIIP_Port_2 :: DUPLX_MODE [01:01] */
-#define BCHP_SWITCH_CORE_STS_OVERRIDE_GMIIP_Port_2_DUPLX_MODE_MASK 0x00000002
-#define BCHP_SWITCH_CORE_STS_OVERRIDE_GMIIP_Port_2_DUPLX_MODE_SHIFT 1
-#define BCHP_SWITCH_CORE_STS_OVERRIDE_GMIIP_Port_2_DUPLX_MODE_DEFAULT 0x00000001
-
-/* SWITCH_CORE :: STS_OVERRIDE_GMIIP_Port_2 :: LINK_STS [00:00] */
-#define BCHP_SWITCH_CORE_STS_OVERRIDE_GMIIP_Port_2_LINK_STS_MASK 0x00000001
-#define BCHP_SWITCH_CORE_STS_OVERRIDE_GMIIP_Port_2_LINK_STS_SHIFT 0
-#define BCHP_SWITCH_CORE_STS_OVERRIDE_GMIIP_Port_2_LINK_STS_DEFAULT 0x00000001
-
-/***************************************************************************
- *STS_OVERRIDE_GMIIP_Port_3 - Port N GMII Port States Override Register
- ***************************************************************************/
-/* SWITCH_CORE :: STS_OVERRIDE_GMIIP_Port_3 :: reserved_for_padding0 [31:08] */
-#define BCHP_SWITCH_CORE_STS_OVERRIDE_GMIIP_Port_3_reserved_for_padding0_MASK 0xffffff00
-#define BCHP_SWITCH_CORE_STS_OVERRIDE_GMIIP_Port_3_reserved_for_padding0_SHIFT 8
-
-/* SWITCH_CORE :: STS_OVERRIDE_GMIIP_Port_3 :: SWITCH_RESV_1 [07:07] */
-#define BCHP_SWITCH_CORE_STS_OVERRIDE_GMIIP_Port_3_SWITCH_RESV_1_MASK 0x00000080
-#define BCHP_SWITCH_CORE_STS_OVERRIDE_GMIIP_Port_3_SWITCH_RESV_1_SHIFT 7
-#define BCHP_SWITCH_CORE_STS_OVERRIDE_GMIIP_Port_3_SWITCH_RESV_1_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: STS_OVERRIDE_GMIIP_Port_3 :: SW_OVERRIDE [06:06] */
-#define BCHP_SWITCH_CORE_STS_OVERRIDE_GMIIP_Port_3_SW_OVERRIDE_MASK 0x00000040
-#define BCHP_SWITCH_CORE_STS_OVERRIDE_GMIIP_Port_3_SW_OVERRIDE_SHIFT 6
-#define BCHP_SWITCH_CORE_STS_OVERRIDE_GMIIP_Port_3_SW_OVERRIDE_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: STS_OVERRIDE_GMIIP_Port_3 :: TXFLOW_CNTL [05:05] */
-#define BCHP_SWITCH_CORE_STS_OVERRIDE_GMIIP_Port_3_TXFLOW_CNTL_MASK 0x00000020
-#define BCHP_SWITCH_CORE_STS_OVERRIDE_GMIIP_Port_3_TXFLOW_CNTL_SHIFT 5
-#define BCHP_SWITCH_CORE_STS_OVERRIDE_GMIIP_Port_3_TXFLOW_CNTL_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: STS_OVERRIDE_GMIIP_Port_3 :: RXFLOW_CNTL [04:04] */
-#define BCHP_SWITCH_CORE_STS_OVERRIDE_GMIIP_Port_3_RXFLOW_CNTL_MASK 0x00000010
-#define BCHP_SWITCH_CORE_STS_OVERRIDE_GMIIP_Port_3_RXFLOW_CNTL_SHIFT 4
-#define BCHP_SWITCH_CORE_STS_OVERRIDE_GMIIP_Port_3_RXFLOW_CNTL_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: STS_OVERRIDE_GMIIP_Port_3 :: SPEED [03:02] */
-#define BCHP_SWITCH_CORE_STS_OVERRIDE_GMIIP_Port_3_SPEED_MASK 0x0000000c
-#define BCHP_SWITCH_CORE_STS_OVERRIDE_GMIIP_Port_3_SPEED_SHIFT 2
-#define BCHP_SWITCH_CORE_STS_OVERRIDE_GMIIP_Port_3_SPEED_DEFAULT 0x00000002
-
-/* SWITCH_CORE :: STS_OVERRIDE_GMIIP_Port_3 :: DUPLX_MODE [01:01] */
-#define BCHP_SWITCH_CORE_STS_OVERRIDE_GMIIP_Port_3_DUPLX_MODE_MASK 0x00000002
-#define BCHP_SWITCH_CORE_STS_OVERRIDE_GMIIP_Port_3_DUPLX_MODE_SHIFT 1
-#define BCHP_SWITCH_CORE_STS_OVERRIDE_GMIIP_Port_3_DUPLX_MODE_DEFAULT 0x00000001
-
-/* SWITCH_CORE :: STS_OVERRIDE_GMIIP_Port_3 :: LINK_STS [00:00] */
-#define BCHP_SWITCH_CORE_STS_OVERRIDE_GMIIP_Port_3_LINK_STS_MASK 0x00000001
-#define BCHP_SWITCH_CORE_STS_OVERRIDE_GMIIP_Port_3_LINK_STS_SHIFT 0
-#define BCHP_SWITCH_CORE_STS_OVERRIDE_GMIIP_Port_3_LINK_STS_DEFAULT 0x00000001
-
-/***************************************************************************
- *STS_OVERRIDE_GMIIP_Port_4 - Port N GMII Port States Override Register
- ***************************************************************************/
-/* SWITCH_CORE :: STS_OVERRIDE_GMIIP_Port_4 :: reserved_for_padding0 [31:08] */
-#define BCHP_SWITCH_CORE_STS_OVERRIDE_GMIIP_Port_4_reserved_for_padding0_MASK 0xffffff00
-#define BCHP_SWITCH_CORE_STS_OVERRIDE_GMIIP_Port_4_reserved_for_padding0_SHIFT 8
-
-/* SWITCH_CORE :: STS_OVERRIDE_GMIIP_Port_4 :: SWITCH_RESV_1 [07:07] */
-#define BCHP_SWITCH_CORE_STS_OVERRIDE_GMIIP_Port_4_SWITCH_RESV_1_MASK 0x00000080
-#define BCHP_SWITCH_CORE_STS_OVERRIDE_GMIIP_Port_4_SWITCH_RESV_1_SHIFT 7
-#define BCHP_SWITCH_CORE_STS_OVERRIDE_GMIIP_Port_4_SWITCH_RESV_1_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: STS_OVERRIDE_GMIIP_Port_4 :: SW_OVERRIDE [06:06] */
-#define BCHP_SWITCH_CORE_STS_OVERRIDE_GMIIP_Port_4_SW_OVERRIDE_MASK 0x00000040
-#define BCHP_SWITCH_CORE_STS_OVERRIDE_GMIIP_Port_4_SW_OVERRIDE_SHIFT 6
-#define BCHP_SWITCH_CORE_STS_OVERRIDE_GMIIP_Port_4_SW_OVERRIDE_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: STS_OVERRIDE_GMIIP_Port_4 :: TXFLOW_CNTL [05:05] */
-#define BCHP_SWITCH_CORE_STS_OVERRIDE_GMIIP_Port_4_TXFLOW_CNTL_MASK 0x00000020
-#define BCHP_SWITCH_CORE_STS_OVERRIDE_GMIIP_Port_4_TXFLOW_CNTL_SHIFT 5
-#define BCHP_SWITCH_CORE_STS_OVERRIDE_GMIIP_Port_4_TXFLOW_CNTL_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: STS_OVERRIDE_GMIIP_Port_4 :: RXFLOW_CNTL [04:04] */
-#define BCHP_SWITCH_CORE_STS_OVERRIDE_GMIIP_Port_4_RXFLOW_CNTL_MASK 0x00000010
-#define BCHP_SWITCH_CORE_STS_OVERRIDE_GMIIP_Port_4_RXFLOW_CNTL_SHIFT 4
-#define BCHP_SWITCH_CORE_STS_OVERRIDE_GMIIP_Port_4_RXFLOW_CNTL_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: STS_OVERRIDE_GMIIP_Port_4 :: SPEED [03:02] */
-#define BCHP_SWITCH_CORE_STS_OVERRIDE_GMIIP_Port_4_SPEED_MASK 0x0000000c
-#define BCHP_SWITCH_CORE_STS_OVERRIDE_GMIIP_Port_4_SPEED_SHIFT 2
-#define BCHP_SWITCH_CORE_STS_OVERRIDE_GMIIP_Port_4_SPEED_DEFAULT 0x00000002
-
-/* SWITCH_CORE :: STS_OVERRIDE_GMIIP_Port_4 :: DUPLX_MODE [01:01] */
-#define BCHP_SWITCH_CORE_STS_OVERRIDE_GMIIP_Port_4_DUPLX_MODE_MASK 0x00000002
-#define BCHP_SWITCH_CORE_STS_OVERRIDE_GMIIP_Port_4_DUPLX_MODE_SHIFT 1
-#define BCHP_SWITCH_CORE_STS_OVERRIDE_GMIIP_Port_4_DUPLX_MODE_DEFAULT 0x00000001
-
-/* SWITCH_CORE :: STS_OVERRIDE_GMIIP_Port_4 :: LINK_STS [00:00] */
-#define BCHP_SWITCH_CORE_STS_OVERRIDE_GMIIP_Port_4_LINK_STS_MASK 0x00000001
-#define BCHP_SWITCH_CORE_STS_OVERRIDE_GMIIP_Port_4_LINK_STS_SHIFT 0
-#define BCHP_SWITCH_CORE_STS_OVERRIDE_GMIIP_Port_4_LINK_STS_DEFAULT 0x00000001
-
-/***************************************************************************
- *STS_OVERRIDE_P5 - Port 5 GMII Port States Override Register
- ***************************************************************************/
-/* SWITCH_CORE :: STS_OVERRIDE_P5 :: reserved_for_padding0 [31:08] */
-#define BCHP_SWITCH_CORE_STS_OVERRIDE_P5_reserved_for_padding0_MASK 0xffffff00
-#define BCHP_SWITCH_CORE_STS_OVERRIDE_P5_reserved_for_padding0_SHIFT 8
-
-/* SWITCH_CORE :: STS_OVERRIDE_P5 :: GMII_SPEED_UP_2G [07:07] */
-#define BCHP_SWITCH_CORE_STS_OVERRIDE_P5_GMII_SPEED_UP_2G_MASK 0x00000080
-#define BCHP_SWITCH_CORE_STS_OVERRIDE_P5_GMII_SPEED_UP_2G_SHIFT 7
-#define BCHP_SWITCH_CORE_STS_OVERRIDE_P5_GMII_SPEED_UP_2G_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: STS_OVERRIDE_P5 :: SW_OVERRIDE [06:06] */
-#define BCHP_SWITCH_CORE_STS_OVERRIDE_P5_SW_OVERRIDE_MASK 0x00000040
-#define BCHP_SWITCH_CORE_STS_OVERRIDE_P5_SW_OVERRIDE_SHIFT 6
-#define BCHP_SWITCH_CORE_STS_OVERRIDE_P5_SW_OVERRIDE_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: STS_OVERRIDE_P5 :: TXFLOW_CNTL [05:05] */
-#define BCHP_SWITCH_CORE_STS_OVERRIDE_P5_TXFLOW_CNTL_MASK 0x00000020
-#define BCHP_SWITCH_CORE_STS_OVERRIDE_P5_TXFLOW_CNTL_SHIFT 5
-#define BCHP_SWITCH_CORE_STS_OVERRIDE_P5_TXFLOW_CNTL_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: STS_OVERRIDE_P5 :: RXFLOW_CNTL [04:04] */
-#define BCHP_SWITCH_CORE_STS_OVERRIDE_P5_RXFLOW_CNTL_MASK 0x00000010
-#define BCHP_SWITCH_CORE_STS_OVERRIDE_P5_RXFLOW_CNTL_SHIFT 4
-#define BCHP_SWITCH_CORE_STS_OVERRIDE_P5_RXFLOW_CNTL_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: STS_OVERRIDE_P5 :: SPEED [03:02] */
-#define BCHP_SWITCH_CORE_STS_OVERRIDE_P5_SPEED_MASK 0x0000000c
-#define BCHP_SWITCH_CORE_STS_OVERRIDE_P5_SPEED_SHIFT 2
-#define BCHP_SWITCH_CORE_STS_OVERRIDE_P5_SPEED_DEFAULT 0x00000002
-
-/* SWITCH_CORE :: STS_OVERRIDE_P5 :: DUPLX_MODE [01:01] */
-#define BCHP_SWITCH_CORE_STS_OVERRIDE_P5_DUPLX_MODE_MASK 0x00000002
-#define BCHP_SWITCH_CORE_STS_OVERRIDE_P5_DUPLX_MODE_SHIFT 1
-#define BCHP_SWITCH_CORE_STS_OVERRIDE_P5_DUPLX_MODE_DEFAULT 0x00000001
-
-/* SWITCH_CORE :: STS_OVERRIDE_P5 :: LINK_STS [00:00] */
-#define BCHP_SWITCH_CORE_STS_OVERRIDE_P5_LINK_STS_MASK 0x00000001
-#define BCHP_SWITCH_CORE_STS_OVERRIDE_P5_LINK_STS_SHIFT 0
-#define BCHP_SWITCH_CORE_STS_OVERRIDE_P5_LINK_STS_DEFAULT 0x00000000
-
-/***************************************************************************
- *STS_OVERRIDE_P7 - Port 7 GMII Port States Override Register
- ***************************************************************************/
-/* SWITCH_CORE :: STS_OVERRIDE_P7 :: reserved_for_padding0 [31:08] */
-#define BCHP_SWITCH_CORE_STS_OVERRIDE_P7_reserved_for_padding0_MASK 0xffffff00
-#define BCHP_SWITCH_CORE_STS_OVERRIDE_P7_reserved_for_padding0_SHIFT 8
-
-/* SWITCH_CORE :: STS_OVERRIDE_P7 :: GMII_SPEED_UP_2G [07:07] */
-#define BCHP_SWITCH_CORE_STS_OVERRIDE_P7_GMII_SPEED_UP_2G_MASK 0x00000080
-#define BCHP_SWITCH_CORE_STS_OVERRIDE_P7_GMII_SPEED_UP_2G_SHIFT 7
-#define BCHP_SWITCH_CORE_STS_OVERRIDE_P7_GMII_SPEED_UP_2G_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: STS_OVERRIDE_P7 :: SW_OVERRIDE [06:06] */
-#define BCHP_SWITCH_CORE_STS_OVERRIDE_P7_SW_OVERRIDE_MASK 0x00000040
-#define BCHP_SWITCH_CORE_STS_OVERRIDE_P7_SW_OVERRIDE_SHIFT 6
-#define BCHP_SWITCH_CORE_STS_OVERRIDE_P7_SW_OVERRIDE_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: STS_OVERRIDE_P7 :: TXFLOW_CNTL [05:05] */
-#define BCHP_SWITCH_CORE_STS_OVERRIDE_P7_TXFLOW_CNTL_MASK 0x00000020
-#define BCHP_SWITCH_CORE_STS_OVERRIDE_P7_TXFLOW_CNTL_SHIFT 5
-#define BCHP_SWITCH_CORE_STS_OVERRIDE_P7_TXFLOW_CNTL_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: STS_OVERRIDE_P7 :: RXFLOW_CNTL [04:04] */
-#define BCHP_SWITCH_CORE_STS_OVERRIDE_P7_RXFLOW_CNTL_MASK 0x00000010
-#define BCHP_SWITCH_CORE_STS_OVERRIDE_P7_RXFLOW_CNTL_SHIFT 4
-#define BCHP_SWITCH_CORE_STS_OVERRIDE_P7_RXFLOW_CNTL_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: STS_OVERRIDE_P7 :: SPEED [03:02] */
-#define BCHP_SWITCH_CORE_STS_OVERRIDE_P7_SPEED_MASK 0x0000000c
-#define BCHP_SWITCH_CORE_STS_OVERRIDE_P7_SPEED_SHIFT 2
-#define BCHP_SWITCH_CORE_STS_OVERRIDE_P7_SPEED_DEFAULT 0x00000002
-
-/* SWITCH_CORE :: STS_OVERRIDE_P7 :: DUPLX_MODE [01:01] */
-#define BCHP_SWITCH_CORE_STS_OVERRIDE_P7_DUPLX_MODE_MASK 0x00000002
-#define BCHP_SWITCH_CORE_STS_OVERRIDE_P7_DUPLX_MODE_SHIFT 1
-#define BCHP_SWITCH_CORE_STS_OVERRIDE_P7_DUPLX_MODE_DEFAULT 0x00000001
-
-/* SWITCH_CORE :: STS_OVERRIDE_P7 :: LINK_STS [00:00] */
-#define BCHP_SWITCH_CORE_STS_OVERRIDE_P7_LINK_STS_MASK 0x00000001
-#define BCHP_SWITCH_CORE_STS_OVERRIDE_P7_LINK_STS_SHIFT 0
-#define BCHP_SWITCH_CORE_STS_OVERRIDE_P7_LINK_STS_DEFAULT 0x00000000
-
-/***************************************************************************
- *WATCH_DOG_CTRL - Watch Dog Control Register
- ***************************************************************************/
-/* SWITCH_CORE :: WATCH_DOG_CTRL :: reserved_for_padding0 [31:08] */
-#define BCHP_SWITCH_CORE_WATCH_DOG_CTRL_reserved_for_padding0_MASK 0xffffff00
-#define BCHP_SWITCH_CORE_WATCH_DOG_CTRL_reserved_for_padding0_SHIFT 8
-
-/* SWITCH_CORE :: WATCH_DOG_CTRL :: SOFTWARE_RESET [07:07] */
-#define BCHP_SWITCH_CORE_WATCH_DOG_CTRL_SOFTWARE_RESET_MASK 0x00000080
-#define BCHP_SWITCH_CORE_WATCH_DOG_CTRL_SOFTWARE_RESET_SHIFT 7
-#define BCHP_SWITCH_CORE_WATCH_DOG_CTRL_SOFTWARE_RESET_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: WATCH_DOG_CTRL :: EN_CHIP_RST [06:06] */
-#define BCHP_SWITCH_CORE_WATCH_DOG_CTRL_EN_CHIP_RST_MASK 0x00000040
-#define BCHP_SWITCH_CORE_WATCH_DOG_CTRL_EN_CHIP_RST_SHIFT 6
-#define BCHP_SWITCH_CORE_WATCH_DOG_CTRL_EN_CHIP_RST_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: WATCH_DOG_CTRL :: SWITCH_RESV [05:05] */
-#define BCHP_SWITCH_CORE_WATCH_DOG_CTRL_SWITCH_RESV_MASK 0x00000020
-#define BCHP_SWITCH_CORE_WATCH_DOG_CTRL_SWITCH_RESV_SHIFT 5
-#define BCHP_SWITCH_CORE_WATCH_DOG_CTRL_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: WATCH_DOG_CTRL :: EN_SW_RESET [04:04] */
-#define BCHP_SWITCH_CORE_WATCH_DOG_CTRL_EN_SW_RESET_MASK 0x00000010
-#define BCHP_SWITCH_CORE_WATCH_DOG_CTRL_EN_SW_RESET_SHIFT 4
-#define BCHP_SWITCH_CORE_WATCH_DOG_CTRL_EN_SW_RESET_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: WATCH_DOG_CTRL :: EN_AUTO_RST [03:03] */
-#define BCHP_SWITCH_CORE_WATCH_DOG_CTRL_EN_AUTO_RST_MASK 0x00000008
-#define BCHP_SWITCH_CORE_WATCH_DOG_CTRL_EN_AUTO_RST_SHIFT 3
-#define BCHP_SWITCH_CORE_WATCH_DOG_CTRL_EN_AUTO_RST_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: WATCH_DOG_CTRL :: EN_RELOAD_EEPROM [02:02] */
-#define BCHP_SWITCH_CORE_WATCH_DOG_CTRL_EN_RELOAD_EEPROM_MASK 0x00000004
-#define BCHP_SWITCH_CORE_WATCH_DOG_CTRL_EN_RELOAD_EEPROM_SHIFT 2
-#define BCHP_SWITCH_CORE_WATCH_DOG_CTRL_EN_RELOAD_EEPROM_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: WATCH_DOG_CTRL :: EN_RST_REGFILE [01:01] */
-#define BCHP_SWITCH_CORE_WATCH_DOG_CTRL_EN_RST_REGFILE_MASK 0x00000002
-#define BCHP_SWITCH_CORE_WATCH_DOG_CTRL_EN_RST_REGFILE_SHIFT 1
-#define BCHP_SWITCH_CORE_WATCH_DOG_CTRL_EN_RST_REGFILE_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: WATCH_DOG_CTRL :: EN_RST_SWITCH [00:00] */
-#define BCHP_SWITCH_CORE_WATCH_DOG_CTRL_EN_RST_SWITCH_MASK 0x00000001
-#define BCHP_SWITCH_CORE_WATCH_DOG_CTRL_EN_RST_SWITCH_SHIFT 0
-#define BCHP_SWITCH_CORE_WATCH_DOG_CTRL_EN_RST_SWITCH_DEFAULT 0x00000000
-
-/***************************************************************************
- *WATCH_DOG_RPT1 - Watch Dog Report 1 Register(Not2Release)
- ***************************************************************************/
-/* SWITCH_CORE :: WATCH_DOG_RPT1 :: reserved_for_padding0 [31:16] */
-#define BCHP_SWITCH_CORE_WATCH_DOG_RPT1_reserved_for_padding0_MASK 0xffff0000
-#define BCHP_SWITCH_CORE_WATCH_DOG_RPT1_reserved_for_padding0_SHIFT 16
-
-/* SWITCH_CORE :: WATCH_DOG_RPT1 :: SWITCH_RESV [15:09] */
-#define BCHP_SWITCH_CORE_WATCH_DOG_RPT1_SWITCH_RESV_MASK 0x0000fe00
-#define BCHP_SWITCH_CORE_WATCH_DOG_RPT1_SWITCH_RESV_SHIFT 9
-#define BCHP_SWITCH_CORE_WATCH_DOG_RPT1_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: WATCH_DOG_RPT1 :: TX_PORT_HUNG_INDICATOR [08:00] */
-#define BCHP_SWITCH_CORE_WATCH_DOG_RPT1_TX_PORT_HUNG_INDICATOR_MASK 0x000001ff
-#define BCHP_SWITCH_CORE_WATCH_DOG_RPT1_TX_PORT_HUNG_INDICATOR_SHIFT 0
-#define BCHP_SWITCH_CORE_WATCH_DOG_RPT1_TX_PORT_HUNG_INDICATOR_DEFAULT 0x00000000
-
-/***************************************************************************
- *WATCH_DOG_RPT2 - Watch Dog Report 2 Register(Not2Release)
- ***************************************************************************/
-/* SWITCH_CORE :: WATCH_DOG_RPT2 :: reserved_for_padding0 [31:16] */
-#define BCHP_SWITCH_CORE_WATCH_DOG_RPT2_reserved_for_padding0_MASK 0xffff0000
-#define BCHP_SWITCH_CORE_WATCH_DOG_RPT2_reserved_for_padding0_SHIFT 16
-
-/* SWITCH_CORE :: WATCH_DOG_RPT2 :: SWITCH_RESV [15:09] */
-#define BCHP_SWITCH_CORE_WATCH_DOG_RPT2_SWITCH_RESV_MASK 0x0000fe00
-#define BCHP_SWITCH_CORE_WATCH_DOG_RPT2_SWITCH_RESV_SHIFT 9
-#define BCHP_SWITCH_CORE_WATCH_DOG_RPT2_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: WATCH_DOG_RPT2 :: RX_PORT_HUNG_INDICATOR [08:00] */
-#define BCHP_SWITCH_CORE_WATCH_DOG_RPT2_RX_PORT_HUNG_INDICATOR_MASK 0x000001ff
-#define BCHP_SWITCH_CORE_WATCH_DOG_RPT2_RX_PORT_HUNG_INDICATOR_SHIFT 0
-#define BCHP_SWITCH_CORE_WATCH_DOG_RPT2_RX_PORT_HUNG_INDICATOR_DEFAULT 0x00000000
-
-/***************************************************************************
- *WATCH_DOG_RPT3 - Watch Dog Report 3 Register(Not2Release)
- ***************************************************************************/
-/* SWITCH_CORE :: WATCH_DOG_RPT3 :: reserved_for_padding0 [31:16] */
-#define BCHP_SWITCH_CORE_WATCH_DOG_RPT3_reserved_for_padding0_MASK 0xffff0000
-#define BCHP_SWITCH_CORE_WATCH_DOG_RPT3_reserved_for_padding0_SHIFT 16
-
-/* SWITCH_CORE :: WATCH_DOG_RPT3 :: SWITCH_RESV [15:09] */
-#define BCHP_SWITCH_CORE_WATCH_DOG_RPT3_SWITCH_RESV_MASK 0x0000fe00
-#define BCHP_SWITCH_CORE_WATCH_DOG_RPT3_SWITCH_RESV_SHIFT 9
-#define BCHP_SWITCH_CORE_WATCH_DOG_RPT3_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: WATCH_DOG_RPT3 :: ARL_HUNG_INDICATOR [08:00] */
-#define BCHP_SWITCH_CORE_WATCH_DOG_RPT3_ARL_HUNG_INDICATOR_MASK 0x000001ff
-#define BCHP_SWITCH_CORE_WATCH_DOG_RPT3_ARL_HUNG_INDICATOR_SHIFT 0
-#define BCHP_SWITCH_CORE_WATCH_DOG_RPT3_ARL_HUNG_INDICATOR_DEFAULT 0x00000000
-
-/***************************************************************************
- *PAUSE_FRM_CTRL - Pause Frame Detection Control Register
- ***************************************************************************/
-/* SWITCH_CORE :: PAUSE_FRM_CTRL :: reserved_for_padding0 [31:08] */
-#define BCHP_SWITCH_CORE_PAUSE_FRM_CTRL_reserved_for_padding0_MASK 0xffffff00
-#define BCHP_SWITCH_CORE_PAUSE_FRM_CTRL_reserved_for_padding0_SHIFT 8
-
-/* SWITCH_CORE :: PAUSE_FRM_CTRL :: SWITCH_RESV_2 [07:03] */
-#define BCHP_SWITCH_CORE_PAUSE_FRM_CTRL_SWITCH_RESV_2_MASK 0x000000f8
-#define BCHP_SWITCH_CORE_PAUSE_FRM_CTRL_SWITCH_RESV_2_SHIFT 3
-#define BCHP_SWITCH_CORE_PAUSE_FRM_CTRL_SWITCH_RESV_2_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: PAUSE_FRM_CTRL :: SWITCH_RESV_1 [02:01] */
-#define BCHP_SWITCH_CORE_PAUSE_FRM_CTRL_SWITCH_RESV_1_MASK 0x00000006
-#define BCHP_SWITCH_CORE_PAUSE_FRM_CTRL_SWITCH_RESV_1_SHIFT 1
-#define BCHP_SWITCH_CORE_PAUSE_FRM_CTRL_SWITCH_RESV_1_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: PAUSE_FRM_CTRL :: PAUSE_IGNORE_DA [00:00] */
-#define BCHP_SWITCH_CORE_PAUSE_FRM_CTRL_PAUSE_IGNORE_DA_MASK 0x00000001
-#define BCHP_SWITCH_CORE_PAUSE_FRM_CTRL_PAUSE_IGNORE_DA_SHIFT 0
-#define BCHP_SWITCH_CORE_PAUSE_FRM_CTRL_PAUSE_IGNORE_DA_DEFAULT 0x00000000
-
-/***************************************************************************
- *PAUSE_ST_ADDR - PAUSE Frame DA Address
- ***************************************************************************/
-/* SWITCH_CORE :: PAUSE_ST_ADDR :: PAUSE_ST_ADDR [47:00] */
-#define BCHP_SWITCH_CORE_PAUSE_ST_ADDR_PAUSE_ST_ADDR_MASK 0x00000000ffff
-#define BCHP_SWITCH_CORE_PAUSE_ST_ADDR_PAUSE_ST_ADDR_SHIFT 0
-#define BCHP_SWITCH_CORE_PAUSE_ST_ADDR_PAUSE_ST_ADDR_DEFAULT 0x0000ffffffff
-
-/***************************************************************************
- *FAST_AGE_CTRL - Fast Ageing Control Register
- ***************************************************************************/
-/* SWITCH_CORE :: FAST_AGE_CTRL :: reserved_for_padding0 [31:08] */
-#define BCHP_SWITCH_CORE_FAST_AGE_CTRL_reserved_for_padding0_MASK 0xffffff00
-#define BCHP_SWITCH_CORE_FAST_AGE_CTRL_reserved_for_padding0_SHIFT 8
-
-/* SWITCH_CORE :: FAST_AGE_CTRL :: FAST_AGE_STR_DONE [07:07] */
-#define BCHP_SWITCH_CORE_FAST_AGE_CTRL_FAST_AGE_STR_DONE_MASK 0x00000080
-#define BCHP_SWITCH_CORE_FAST_AGE_CTRL_FAST_AGE_STR_DONE_SHIFT 7
-#define BCHP_SWITCH_CORE_FAST_AGE_CTRL_FAST_AGE_STR_DONE_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: FAST_AGE_CTRL :: SWITCH_RESV [06:06] */
-#define BCHP_SWITCH_CORE_FAST_AGE_CTRL_SWITCH_RESV_MASK 0x00000040
-#define BCHP_SWITCH_CORE_FAST_AGE_CTRL_SWITCH_RESV_SHIFT 6
-#define BCHP_SWITCH_CORE_FAST_AGE_CTRL_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: FAST_AGE_CTRL :: EN_AGE_MCAST [05:05] */
-#define BCHP_SWITCH_CORE_FAST_AGE_CTRL_EN_AGE_MCAST_MASK 0x00000020
-#define BCHP_SWITCH_CORE_FAST_AGE_CTRL_EN_AGE_MCAST_SHIFT 5
-#define BCHP_SWITCH_CORE_FAST_AGE_CTRL_EN_AGE_MCAST_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: FAST_AGE_CTRL :: EN_AGE_SPT [04:04] */
-#define BCHP_SWITCH_CORE_FAST_AGE_CTRL_EN_AGE_SPT_MASK 0x00000010
-#define BCHP_SWITCH_CORE_FAST_AGE_CTRL_EN_AGE_SPT_SHIFT 4
-#define BCHP_SWITCH_CORE_FAST_AGE_CTRL_EN_AGE_SPT_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: FAST_AGE_CTRL :: EN_AGE_VLAN [03:03] */
-#define BCHP_SWITCH_CORE_FAST_AGE_CTRL_EN_AGE_VLAN_MASK 0x00000008
-#define BCHP_SWITCH_CORE_FAST_AGE_CTRL_EN_AGE_VLAN_SHIFT 3
-#define BCHP_SWITCH_CORE_FAST_AGE_CTRL_EN_AGE_VLAN_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: FAST_AGE_CTRL :: EN_AGE_PORT [02:02] */
-#define BCHP_SWITCH_CORE_FAST_AGE_CTRL_EN_AGE_PORT_MASK 0x00000004
-#define BCHP_SWITCH_CORE_FAST_AGE_CTRL_EN_AGE_PORT_SHIFT 2
-#define BCHP_SWITCH_CORE_FAST_AGE_CTRL_EN_AGE_PORT_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: FAST_AGE_CTRL :: EN_AGE_DYNAMIC [01:01] */
-#define BCHP_SWITCH_CORE_FAST_AGE_CTRL_EN_AGE_DYNAMIC_MASK 0x00000002
-#define BCHP_SWITCH_CORE_FAST_AGE_CTRL_EN_AGE_DYNAMIC_SHIFT 1
-#define BCHP_SWITCH_CORE_FAST_AGE_CTRL_EN_AGE_DYNAMIC_DEFAULT 0x00000001
-
-/* SWITCH_CORE :: FAST_AGE_CTRL :: EN_FAST_AGE_STATIC [00:00] */
-#define BCHP_SWITCH_CORE_FAST_AGE_CTRL_EN_FAST_AGE_STATIC_MASK 0x00000001
-#define BCHP_SWITCH_CORE_FAST_AGE_CTRL_EN_FAST_AGE_STATIC_SHIFT 0
-#define BCHP_SWITCH_CORE_FAST_AGE_CTRL_EN_FAST_AGE_STATIC_DEFAULT 0x00000000
-
-/***************************************************************************
- *FAST_AGE_PORT - Fast Ageing Port Control Register
- ***************************************************************************/
-/* SWITCH_CORE :: FAST_AGE_PORT :: reserved_for_padding0 [31:08] */
-#define BCHP_SWITCH_CORE_FAST_AGE_PORT_reserved_for_padding0_MASK 0xffffff00
-#define BCHP_SWITCH_CORE_FAST_AGE_PORT_reserved_for_padding0_SHIFT 8
-
-/* SWITCH_CORE :: FAST_AGE_PORT :: SWITCH_RESV [07:04] */
-#define BCHP_SWITCH_CORE_FAST_AGE_PORT_SWITCH_RESV_MASK 0x000000f0
-#define BCHP_SWITCH_CORE_FAST_AGE_PORT_SWITCH_RESV_SHIFT 4
-#define BCHP_SWITCH_CORE_FAST_AGE_PORT_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: FAST_AGE_PORT :: AGE_PORT [03:00] */
-#define BCHP_SWITCH_CORE_FAST_AGE_PORT_AGE_PORT_MASK 0x0000000f
-#define BCHP_SWITCH_CORE_FAST_AGE_PORT_AGE_PORT_SHIFT 0
-#define BCHP_SWITCH_CORE_FAST_AGE_PORT_AGE_PORT_DEFAULT 0x00000000
-
-/***************************************************************************
- *FAST_AGE_VID - Fast Ageing VID Control Register
- ***************************************************************************/
-/* SWITCH_CORE :: FAST_AGE_VID :: reserved_for_padding0 [31:16] */
-#define BCHP_SWITCH_CORE_FAST_AGE_VID_reserved_for_padding0_MASK 0xffff0000
-#define BCHP_SWITCH_CORE_FAST_AGE_VID_reserved_for_padding0_SHIFT 16
-
-/* SWITCH_CORE :: FAST_AGE_VID :: SWITCH_RESV [15:12] */
-#define BCHP_SWITCH_CORE_FAST_AGE_VID_SWITCH_RESV_MASK 0x0000f000
-#define BCHP_SWITCH_CORE_FAST_AGE_VID_SWITCH_RESV_SHIFT 12
-#define BCHP_SWITCH_CORE_FAST_AGE_VID_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: FAST_AGE_VID :: AGE_VID [11:00] */
-#define BCHP_SWITCH_CORE_FAST_AGE_VID_AGE_VID_MASK 0x00000fff
-#define BCHP_SWITCH_CORE_FAST_AGE_VID_AGE_VID_SHIFT 0
-#define BCHP_SWITCH_CORE_FAST_AGE_VID_AGE_VID_DEFAULT 0x00000000
-
-/***************************************************************************
- *LOW_POWER_CTRL - LOW Power Control Register
- ***************************************************************************/
-/* SWITCH_CORE :: LOW_POWER_CTRL :: reserved_for_padding0 [31:16] */
-#define BCHP_SWITCH_CORE_LOW_POWER_CTRL_reserved_for_padding0_MASK 0xffff0000
-#define BCHP_SWITCH_CORE_LOW_POWER_CTRL_reserved_for_padding0_SHIFT 16
-
-/* SWITCH_CORE :: LOW_POWER_CTRL :: SLEEP_P8 [15:15] */
-#define BCHP_SWITCH_CORE_LOW_POWER_CTRL_SLEEP_P8_MASK 0x00008000
-#define BCHP_SWITCH_CORE_LOW_POWER_CTRL_SLEEP_P8_SHIFT 15
-#define BCHP_SWITCH_CORE_LOW_POWER_CTRL_SLEEP_P8_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: LOW_POWER_CTRL :: SWITCH_RESV_1 [14:13] */
-#define BCHP_SWITCH_CORE_LOW_POWER_CTRL_SWITCH_RESV_1_MASK 0x00006000
-#define BCHP_SWITCH_CORE_LOW_POWER_CTRL_SWITCH_RESV_1_SHIFT 13
-#define BCHP_SWITCH_CORE_LOW_POWER_CTRL_SWITCH_RESV_1_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: LOW_POWER_CTRL :: SLEEP_P5 [12:12] */
-#define BCHP_SWITCH_CORE_LOW_POWER_CTRL_SLEEP_P5_MASK 0x00001000
-#define BCHP_SWITCH_CORE_LOW_POWER_CTRL_SLEEP_P5_SHIFT 12
-#define BCHP_SWITCH_CORE_LOW_POWER_CTRL_SLEEP_P5_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: LOW_POWER_CTRL :: SLEEP_P4 [11:11] */
-#define BCHP_SWITCH_CORE_LOW_POWER_CTRL_SLEEP_P4_MASK 0x00000800
-#define BCHP_SWITCH_CORE_LOW_POWER_CTRL_SLEEP_P4_SHIFT 11
-#define BCHP_SWITCH_CORE_LOW_POWER_CTRL_SLEEP_P4_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: LOW_POWER_CTRL :: SWITCH_RESV_0 [10:07] */
-#define BCHP_SWITCH_CORE_LOW_POWER_CTRL_SWITCH_RESV_0_MASK 0x00000780
-#define BCHP_SWITCH_CORE_LOW_POWER_CTRL_SWITCH_RESV_0_SHIFT 7
-#define BCHP_SWITCH_CORE_LOW_POWER_CTRL_SWITCH_RESV_0_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: LOW_POWER_CTRL :: SLEEP_SYS [06:06] */
-#define BCHP_SWITCH_CORE_LOW_POWER_CTRL_SLEEP_SYS_MASK 0x00000040
-#define BCHP_SWITCH_CORE_LOW_POWER_CTRL_SLEEP_SYS_SHIFT 6
-#define BCHP_SWITCH_CORE_LOW_POWER_CTRL_SLEEP_SYS_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: LOW_POWER_CTRL :: TIMER_DISABLE [05:05] */
-#define BCHP_SWITCH_CORE_LOW_POWER_CTRL_TIMER_DISABLE_MASK 0x00000020
-#define BCHP_SWITCH_CORE_LOW_POWER_CTRL_TIMER_DISABLE_SHIFT 5
-#define BCHP_SWITCH_CORE_LOW_POWER_CTRL_TIMER_DISABLE_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: LOW_POWER_CTRL :: EN_LOW_POWER [04:04] */
-#define BCHP_SWITCH_CORE_LOW_POWER_CTRL_EN_LOW_POWER_MASK 0x00000010
-#define BCHP_SWITCH_CORE_LOW_POWER_CTRL_EN_LOW_POWER_SHIFT 4
-#define BCHP_SWITCH_CORE_LOW_POWER_CTRL_EN_LOW_POWER_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: LOW_POWER_CTRL :: LOW_POWER_DIVIDER [03:00] */
-#define BCHP_SWITCH_CORE_LOW_POWER_CTRL_LOW_POWER_DIVIDER_MASK 0x0000000f
-#define BCHP_SWITCH_CORE_LOW_POWER_CTRL_LOW_POWER_DIVIDER_SHIFT 0
-#define BCHP_SWITCH_CORE_LOW_POWER_CTRL_LOW_POWER_DIVIDER_DEFAULT 0x00000000
-
-/***************************************************************************
- *TCAM_CTRL - TCAM Control Register
- ***************************************************************************/
-/* SWITCH_CORE :: TCAM_CTRL :: reserved_for_padding0 [31:08] */
-#define BCHP_SWITCH_CORE_TCAM_CTRL_reserved_for_padding0_MASK 0xffffff00
-#define BCHP_SWITCH_CORE_TCAM_CTRL_reserved_for_padding0_SHIFT 8
-
-/* SWITCH_CORE :: TCAM_CTRL :: EN_TCAM_CHKSUM [07:07] */
-#define BCHP_SWITCH_CORE_TCAM_CTRL_EN_TCAM_CHKSUM_MASK 0x00000080
-#define BCHP_SWITCH_CORE_TCAM_CTRL_EN_TCAM_CHKSUM_SHIFT 7
-#define BCHP_SWITCH_CORE_TCAM_CTRL_EN_TCAM_CHKSUM_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: TCAM_CTRL :: SWITCH_RESV [06:00] */
-#define BCHP_SWITCH_CORE_TCAM_CTRL_SWITCH_RESV_MASK 0x0000007f
-#define BCHP_SWITCH_CORE_TCAM_CTRL_SWITCH_RESV_SHIFT 0
-#define BCHP_SWITCH_CORE_TCAM_CTRL_SWITCH_RESV_DEFAULT 0x00000000
-
-/***************************************************************************
- *TCAM_CHKSUM_STS - TCAM Checksum Status Register
- ***************************************************************************/
-/* SWITCH_CORE :: TCAM_CHKSUM_STS :: reserved_for_padding0 [31:16] */
-#define BCHP_SWITCH_CORE_TCAM_CHKSUM_STS_reserved_for_padding0_MASK 0xffff0000
-#define BCHP_SWITCH_CORE_TCAM_CHKSUM_STS_reserved_for_padding0_SHIFT 16
-
-/* SWITCH_CORE :: TCAM_CHKSUM_STS :: CFP_TCAM_CHKSUM_ERR [15:15] */
-#define BCHP_SWITCH_CORE_TCAM_CHKSUM_STS_CFP_TCAM_CHKSUM_ERR_MASK 0x00008000
-#define BCHP_SWITCH_CORE_TCAM_CHKSUM_STS_CFP_TCAM_CHKSUM_ERR_SHIFT 15
-#define BCHP_SWITCH_CORE_TCAM_CHKSUM_STS_CFP_TCAM_CHKSUM_ERR_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: TCAM_CHKSUM_STS :: SWITCH_RESV [14:08] */
-#define BCHP_SWITCH_CORE_TCAM_CHKSUM_STS_SWITCH_RESV_MASK 0x00007f00
-#define BCHP_SWITCH_CORE_TCAM_CHKSUM_STS_SWITCH_RESV_SHIFT 8
-#define BCHP_SWITCH_CORE_TCAM_CHKSUM_STS_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: TCAM_CHKSUM_STS :: CFP_TCAM_CHKSUM_ADDR [07:00] */
-#define BCHP_SWITCH_CORE_TCAM_CHKSUM_STS_CFP_TCAM_CHKSUM_ADDR_MASK 0x000000ff
-#define BCHP_SWITCH_CORE_TCAM_CHKSUM_STS_CFP_TCAM_CHKSUM_ADDR_SHIFT 0
-#define BCHP_SWITCH_CORE_TCAM_CHKSUM_STS_CFP_TCAM_CHKSUM_ADDR_DEFAULT 0x00000000
-
-/***************************************************************************
- *LNKSTS - Link Status Summary Register
- ***************************************************************************/
-/* SWITCH_CORE :: LNKSTS :: reserved_for_padding0 [31:16] */
-#define BCHP_SWITCH_CORE_LNKSTS_reserved_for_padding0_MASK 0xffff0000
-#define BCHP_SWITCH_CORE_LNKSTS_reserved_for_padding0_SHIFT 16
-
-/* SWITCH_CORE :: LNKSTS :: SWITCH_RESV [15:09] */
-#define BCHP_SWITCH_CORE_LNKSTS_SWITCH_RESV_MASK 0x0000fe00
-#define BCHP_SWITCH_CORE_LNKSTS_SWITCH_RESV_SHIFT 9
-#define BCHP_SWITCH_CORE_LNKSTS_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: LNKSTS :: LNK_STS [08:00] */
-#define BCHP_SWITCH_CORE_LNKSTS_LNK_STS_MASK 0x000001ff
-#define BCHP_SWITCH_CORE_LNKSTS_LNK_STS_SHIFT 0
-#define BCHP_SWITCH_CORE_LNKSTS_LNK_STS_DEFAULT 0x00000000
-
-/***************************************************************************
- *LNKSTSCHG - Link Status Change Register
- ***************************************************************************/
-/* SWITCH_CORE :: LNKSTSCHG :: reserved_for_padding0 [31:16] */
-#define BCHP_SWITCH_CORE_LNKSTSCHG_reserved_for_padding0_MASK 0xffff0000
-#define BCHP_SWITCH_CORE_LNKSTSCHG_reserved_for_padding0_SHIFT 16
-
-/* SWITCH_CORE :: LNKSTSCHG :: SWITCH_RESV [15:09] */
-#define BCHP_SWITCH_CORE_LNKSTSCHG_SWITCH_RESV_MASK 0x0000fe00
-#define BCHP_SWITCH_CORE_LNKSTSCHG_SWITCH_RESV_SHIFT 9
-#define BCHP_SWITCH_CORE_LNKSTSCHG_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: LNKSTSCHG :: LNK_STS_CHG [08:00] */
-#define BCHP_SWITCH_CORE_LNKSTSCHG_LNK_STS_CHG_MASK 0x000001ff
-#define BCHP_SWITCH_CORE_LNKSTSCHG_LNK_STS_CHG_SHIFT 0
-#define BCHP_SWITCH_CORE_LNKSTSCHG_LNK_STS_CHG_DEFAULT 0x000001ff
-
-/***************************************************************************
- *SPDSTS - Port Speed Summary Register
- ***************************************************************************/
-/* SWITCH_CORE :: SPDSTS :: SWITCH_RESV [31:18] */
-#define BCHP_SWITCH_CORE_SPDSTS_SWITCH_RESV_MASK 0xfffc0000
-#define BCHP_SWITCH_CORE_SPDSTS_SWITCH_RESV_SHIFT 18
-#define BCHP_SWITCH_CORE_SPDSTS_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: SPDSTS :: PORT_SPD [17:00] */
-#define BCHP_SWITCH_CORE_SPDSTS_PORT_SPD_MASK 0x0003ffff
-#define BCHP_SWITCH_CORE_SPDSTS_PORT_SPD_SHIFT 0
-#define BCHP_SWITCH_CORE_SPDSTS_PORT_SPD_DEFAULT 0x0002aaaa
-
-/***************************************************************************
- *DUPSTS - Duplex status Summary Register
- ***************************************************************************/
-/* SWITCH_CORE :: DUPSTS :: reserved_for_padding0 [31:16] */
-#define BCHP_SWITCH_CORE_DUPSTS_reserved_for_padding0_MASK 0xffff0000
-#define BCHP_SWITCH_CORE_DUPSTS_reserved_for_padding0_SHIFT 16
-
-/* SWITCH_CORE :: DUPSTS :: SWITCH_RESV [15:09] */
-#define BCHP_SWITCH_CORE_DUPSTS_SWITCH_RESV_MASK 0x0000fe00
-#define BCHP_SWITCH_CORE_DUPSTS_SWITCH_RESV_SHIFT 9
-#define BCHP_SWITCH_CORE_DUPSTS_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: DUPSTS :: DUP_STS [08:00] */
-#define BCHP_SWITCH_CORE_DUPSTS_DUP_STS_MASK 0x000001ff
-#define BCHP_SWITCH_CORE_DUPSTS_DUP_STS_SHIFT 0
-#define BCHP_SWITCH_CORE_DUPSTS_DUP_STS_DEFAULT 0x000001ff
-
-/***************************************************************************
- *PAUSESTS - Pause Status Summary Register
- ***************************************************************************/
-/* SWITCH_CORE :: PAUSESTS :: SWITCH_RESV [31:18] */
-#define BCHP_SWITCH_CORE_PAUSESTS_SWITCH_RESV_MASK 0xfffc0000
-#define BCHP_SWITCH_CORE_PAUSESTS_SWITCH_RESV_SHIFT 18
-#define BCHP_SWITCH_CORE_PAUSESTS_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: PAUSESTS :: PAUSE_STS [17:00] */
-#define BCHP_SWITCH_CORE_PAUSESTS_PAUSE_STS_MASK 0x0003ffff
-#define BCHP_SWITCH_CORE_PAUSESTS_PAUSE_STS_SHIFT 0
-#define BCHP_SWITCH_CORE_PAUSESTS_PAUSE_STS_DEFAULT 0x00024120
-
-/***************************************************************************
- *SRCADRCHG - Source Address Change Register
- ***************************************************************************/
-/* SWITCH_CORE :: SRCADRCHG :: reserved_for_padding0 [31:16] */
-#define BCHP_SWITCH_CORE_SRCADRCHG_reserved_for_padding0_MASK 0xffff0000
-#define BCHP_SWITCH_CORE_SRCADRCHG_reserved_for_padding0_SHIFT 16
-
-/* SWITCH_CORE :: SRCADRCHG :: SWITCH_RESV [15:09] */
-#define BCHP_SWITCH_CORE_SRCADRCHG_SWITCH_RESV_MASK 0x0000fe00
-#define BCHP_SWITCH_CORE_SRCADRCHG_SWITCH_RESV_SHIFT 9
-#define BCHP_SWITCH_CORE_SRCADRCHG_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: SRCADRCHG :: SRC_ADDR_CHANGE [08:00] */
-#define BCHP_SWITCH_CORE_SRCADRCHG_SRC_ADDR_CHANGE_MASK 0x000001ff
-#define BCHP_SWITCH_CORE_SRCADRCHG_SRC_ADDR_CHANGE_SHIFT 0
-#define BCHP_SWITCH_CORE_SRCADRCHG_SRC_ADDR_CHANGE_DEFAULT 0x00000000
-
-/***************************************************************************
- *LSA_PORT_Port_0 - Port N Last Source Address
- ***************************************************************************/
-/* SWITCH_CORE :: LSA_PORT_Port_0 :: LST_ADDR [47:00] */
-#define BCHP_SWITCH_CORE_LSA_PORT_Port_0_LST_ADDR_MASK 0x00000000ffff
-#define BCHP_SWITCH_CORE_LSA_PORT_Port_0_LST_ADDR_SHIFT 0
-#define BCHP_SWITCH_CORE_LSA_PORT_Port_0_LST_ADDR_DEFAULT 0x000000000000
-
-/***************************************************************************
- *LSA_PORT_Port_1 - Port N Last Source Address
- ***************************************************************************/
-/* SWITCH_CORE :: LSA_PORT_Port_1 :: LST_ADDR [47:00] */
-#define BCHP_SWITCH_CORE_LSA_PORT_Port_1_LST_ADDR_MASK 0x00000000ffff
-#define BCHP_SWITCH_CORE_LSA_PORT_Port_1_LST_ADDR_SHIFT 0
-#define BCHP_SWITCH_CORE_LSA_PORT_Port_1_LST_ADDR_DEFAULT 0x000000000000
-
-/***************************************************************************
- *LSA_PORT_Port_2 - Port N Last Source Address
- ***************************************************************************/
-/* SWITCH_CORE :: LSA_PORT_Port_2 :: LST_ADDR [47:00] */
-#define BCHP_SWITCH_CORE_LSA_PORT_Port_2_LST_ADDR_MASK 0x00000000ffff
-#define BCHP_SWITCH_CORE_LSA_PORT_Port_2_LST_ADDR_SHIFT 0
-#define BCHP_SWITCH_CORE_LSA_PORT_Port_2_LST_ADDR_DEFAULT 0x000000000000
-
-/***************************************************************************
- *LSA_PORT_Port_3 - Port N Last Source Address
- ***************************************************************************/
-/* SWITCH_CORE :: LSA_PORT_Port_3 :: LST_ADDR [47:00] */
-#define BCHP_SWITCH_CORE_LSA_PORT_Port_3_LST_ADDR_MASK 0x00000000ffff
-#define BCHP_SWITCH_CORE_LSA_PORT_Port_3_LST_ADDR_SHIFT 0
-#define BCHP_SWITCH_CORE_LSA_PORT_Port_3_LST_ADDR_DEFAULT 0x000000000000
-
-/***************************************************************************
- *LSA_PORT_Port_4 - Port N Last Source Address
- ***************************************************************************/
-/* SWITCH_CORE :: LSA_PORT_Port_4 :: LST_ADDR [47:00] */
-#define BCHP_SWITCH_CORE_LSA_PORT_Port_4_LST_ADDR_MASK 0x00000000ffff
-#define BCHP_SWITCH_CORE_LSA_PORT_Port_4_LST_ADDR_SHIFT 0
-#define BCHP_SWITCH_CORE_LSA_PORT_Port_4_LST_ADDR_DEFAULT 0x000000000000
-
-/***************************************************************************
- *LSA_PORT_Port_5 - Port N Last Source Address
- ***************************************************************************/
-/* SWITCH_CORE :: LSA_PORT_Port_5 :: LST_ADDR [47:00] */
-#define BCHP_SWITCH_CORE_LSA_PORT_Port_5_LST_ADDR_MASK 0x00000000ffff
-#define BCHP_SWITCH_CORE_LSA_PORT_Port_5_LST_ADDR_SHIFT 0
-#define BCHP_SWITCH_CORE_LSA_PORT_Port_5_LST_ADDR_DEFAULT 0x000000000000
-
-/***************************************************************************
- *LSA_PORT7 - Port 7 Last Source Address
- ***************************************************************************/
-/* SWITCH_CORE :: LSA_PORT7 :: LST_ADDR [47:00] */
-#define BCHP_SWITCH_CORE_LSA_PORT7_LST_ADDR_MASK 0x00000000ffff
-#define BCHP_SWITCH_CORE_LSA_PORT7_LST_ADDR_SHIFT 0
-#define BCHP_SWITCH_CORE_LSA_PORT7_LST_ADDR_DEFAULT 0x000000000000
-
-/***************************************************************************
- *LSA_MII_PORT - Port 8 Last Source Address
- ***************************************************************************/
-/* SWITCH_CORE :: LSA_MII_PORT :: LST_ADDR [47:00] */
-#define BCHP_SWITCH_CORE_LSA_MII_PORT_LST_ADDR_MASK 0x00000000ffff
-#define BCHP_SWITCH_CORE_LSA_MII_PORT_LST_ADDR_SHIFT 0
-#define BCHP_SWITCH_CORE_LSA_MII_PORT_LST_ADDR_DEFAULT 0x000000000000
-
-/***************************************************************************
- *BIST_STS0 - BIST Status Register 0
- ***************************************************************************/
-/* SWITCH_CORE :: BIST_STS0 :: BIST_STS0 [47:00] */
-#define BCHP_SWITCH_CORE_BIST_STS0_BIST_STS0_MASK 0x00000000ffff
-#define BCHP_SWITCH_CORE_BIST_STS0_BIST_STS0_SHIFT 0
-#define BCHP_SWITCH_CORE_BIST_STS0_BIST_STS0_DEFAULT 0x000000000000
-
-/***************************************************************************
- *BIST_STS1 - BIST Status Register 1
- ***************************************************************************/
-/* SWITCH_CORE :: BIST_STS1 :: reserved_for_padding0 [31:16] */
-#define BCHP_SWITCH_CORE_BIST_STS1_reserved_for_padding0_MASK 0xffff0000
-#define BCHP_SWITCH_CORE_BIST_STS1_reserved_for_padding0_SHIFT 16
-
-/* SWITCH_CORE :: BIST_STS1 :: BIST_STS1 [15:00] */
-#define BCHP_SWITCH_CORE_BIST_STS1_BIST_STS1_MASK 0x0000ffff
-#define BCHP_SWITCH_CORE_BIST_STS1_BIST_STS1_SHIFT 0
-#define BCHP_SWITCH_CORE_BIST_STS1_BIST_STS1_DEFAULT 0x00000000
-
-/***************************************************************************
- *PBPTRFIFO_0 - PBPTRFIFO Status Register 0(Not2Release)
- ***************************************************************************/
-/* SWITCH_CORE :: PBPTRFIFO_0 :: VALID_CNT_P5 [47:40] */
-#define BCHP_SWITCH_CORE_PBPTRFIFO_0_VALID_CNT_P5_MASK 0x00000000ff00
-#define BCHP_SWITCH_CORE_PBPTRFIFO_0_VALID_CNT_P5_SHIFT 40
-#define BCHP_SWITCH_CORE_PBPTRFIFO_0_VALID_CNT_P5_DEFAULT 0x000000000002
-
-/* SWITCH_CORE :: PBPTRFIFO_0 :: VALID_CNT_P4 [39:32] */
-#define BCHP_SWITCH_CORE_PBPTRFIFO_0_VALID_CNT_P4_MASK 0x0000000000ff
-#define BCHP_SWITCH_CORE_PBPTRFIFO_0_VALID_CNT_P4_SHIFT 32
-#define BCHP_SWITCH_CORE_PBPTRFIFO_0_VALID_CNT_P4_DEFAULT 0x000000000002
-
-/* SWITCH_CORE :: PBPTRFIFO_0 :: VALID_CNT_P3 [31:24] */
-#define BCHP_SWITCH_CORE_PBPTRFIFO_0_VALID_CNT_P3_MASK 0x0000ff000000
-#define BCHP_SWITCH_CORE_PBPTRFIFO_0_VALID_CNT_P3_SHIFT 24
-#define BCHP_SWITCH_CORE_PBPTRFIFO_0_VALID_CNT_P3_DEFAULT 0x000000000002
-
-/* SWITCH_CORE :: PBPTRFIFO_0 :: VALID_CNT_P2 [23:16] */
-#define BCHP_SWITCH_CORE_PBPTRFIFO_0_VALID_CNT_P2_MASK 0x000000ff0000
-#define BCHP_SWITCH_CORE_PBPTRFIFO_0_VALID_CNT_P2_SHIFT 16
-#define BCHP_SWITCH_CORE_PBPTRFIFO_0_VALID_CNT_P2_DEFAULT 0x000000000002
-
-/* SWITCH_CORE :: PBPTRFIFO_0 :: VALID_CNT_P1 [15:08] */
-#define BCHP_SWITCH_CORE_PBPTRFIFO_0_VALID_CNT_P1_MASK 0x00000000ff00
-#define BCHP_SWITCH_CORE_PBPTRFIFO_0_VALID_CNT_P1_SHIFT 8
-#define BCHP_SWITCH_CORE_PBPTRFIFO_0_VALID_CNT_P1_DEFAULT 0x000000000002
-
-/* SWITCH_CORE :: PBPTRFIFO_0 :: VALID_CNT_P0 [07:00] */
-#define BCHP_SWITCH_CORE_PBPTRFIFO_0_VALID_CNT_P0_MASK 0x0000000000ff
-#define BCHP_SWITCH_CORE_PBPTRFIFO_0_VALID_CNT_P0_SHIFT 0
-#define BCHP_SWITCH_CORE_PBPTRFIFO_0_VALID_CNT_P0_DEFAULT 0x000000000002
-
-/***************************************************************************
- *PBPTRFIFO_1 - PBPTRFIFO Status Register 1(Not2Release)
- ***************************************************************************/
-/* SWITCH_CORE :: PBPTRFIFO_1 :: SWITCH_RESV_1 [31:24] */
-#define BCHP_SWITCH_CORE_PBPTRFIFO_1_SWITCH_RESV_1_MASK 0xff000000
-#define BCHP_SWITCH_CORE_PBPTRFIFO_1_SWITCH_RESV_1_SHIFT 24
-#define BCHP_SWITCH_CORE_PBPTRFIFO_1_SWITCH_RESV_1_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: PBPTRFIFO_1 :: VALID_CNT_P8 [23:16] */
-#define BCHP_SWITCH_CORE_PBPTRFIFO_1_VALID_CNT_P8_MASK 0x00ff0000
-#define BCHP_SWITCH_CORE_PBPTRFIFO_1_VALID_CNT_P8_SHIFT 16
-#define BCHP_SWITCH_CORE_PBPTRFIFO_1_VALID_CNT_P8_DEFAULT 0x00000002
-
-/* SWITCH_CORE :: PBPTRFIFO_1 :: VALID_CNT_P7 [15:08] */
-#define BCHP_SWITCH_CORE_PBPTRFIFO_1_VALID_CNT_P7_MASK 0x0000ff00
-#define BCHP_SWITCH_CORE_PBPTRFIFO_1_VALID_CNT_P7_SHIFT 8
-#define BCHP_SWITCH_CORE_PBPTRFIFO_1_VALID_CNT_P7_DEFAULT 0x00000002
-
-/* SWITCH_CORE :: PBPTRFIFO_1 :: SWITCH_RESV_0 [07:00] */
-#define BCHP_SWITCH_CORE_PBPTRFIFO_1_SWITCH_RESV_0_MASK 0x000000ff
-#define BCHP_SWITCH_CORE_PBPTRFIFO_1_SWITCH_RESV_0_SHIFT 0
-#define BCHP_SWITCH_CORE_PBPTRFIFO_1_SWITCH_RESV_0_DEFAULT 0x00000000
-
-/***************************************************************************
- *STRAP_PIN_STATUS - Strap Pin Status Register
- ***************************************************************************/
-/* SWITCH_CORE :: STRAP_PIN_STATUS :: STRAP_VALUE_VECTOR [31:00] */
-#define BCHP_SWITCH_CORE_STRAP_PIN_STATUS_STRAP_VALUE_VECTOR_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_STRAP_PIN_STATUS_STRAP_VALUE_VECTOR_SHIFT 0
-#define BCHP_SWITCH_CORE_STRAP_PIN_STATUS_STRAP_VALUE_VECTOR_DEFAULT 0x000003f8
-
-/***************************************************************************
- *DIRECT_INPUT_CTRL_VALUE - Direct Input Control Value Register
- ***************************************************************************/
-/* SWITCH_CORE :: DIRECT_INPUT_CTRL_VALUE :: SWITCH_RESV [31:02] */
-#define BCHP_SWITCH_CORE_DIRECT_INPUT_CTRL_VALUE_SWITCH_RESV_MASK 0xfffffffc
-#define BCHP_SWITCH_CORE_DIRECT_INPUT_CTRL_VALUE_SWITCH_RESV_SHIFT 2
-#define BCHP_SWITCH_CORE_DIRECT_INPUT_CTRL_VALUE_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: DIRECT_INPUT_CTRL_VALUE :: DIRECT_INPUT_CTRL_VALUE [01:00] */
-#define BCHP_SWITCH_CORE_DIRECT_INPUT_CTRL_VALUE_DIRECT_INPUT_CTRL_VALUE_MASK 0x00000003
-#define BCHP_SWITCH_CORE_DIRECT_INPUT_CTRL_VALUE_DIRECT_INPUT_CTRL_VALUE_SHIFT 0
-#define BCHP_SWITCH_CORE_DIRECT_INPUT_CTRL_VALUE_DIRECT_INPUT_CTRL_VALUE_DEFAULT 0x00000000
-
-/***************************************************************************
- *RESET_STATUS - Reset Status Register
- ***************************************************************************/
-/* SWITCH_CORE :: RESET_STATUS :: reserved_for_padding0 [31:16] */
-#define BCHP_SWITCH_CORE_RESET_STATUS_reserved_for_padding0_MASK 0xffff0000
-#define BCHP_SWITCH_CORE_RESET_STATUS_reserved_for_padding0_SHIFT 16
-
-/* SWITCH_CORE :: RESET_STATUS :: SWITCH_RESV_1 [15:11] */
-#define BCHP_SWITCH_CORE_RESET_STATUS_SWITCH_RESV_1_MASK 0x0000f800
-#define BCHP_SWITCH_CORE_RESET_STATUS_SWITCH_RESV_1_SHIFT 11
-#define BCHP_SWITCH_CORE_RESET_STATUS_SWITCH_RESV_1_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: RESET_STATUS :: SOC_BOOT_DN [10:10] */
-#define BCHP_SWITCH_CORE_RESET_STATUS_SOC_BOOT_DN_MASK 0x00000400
-#define BCHP_SWITCH_CORE_RESET_STATUS_SOC_BOOT_DN_SHIFT 10
-#define BCHP_SWITCH_CORE_RESET_STATUS_SOC_BOOT_DN_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: RESET_STATUS :: SW_CORE_RST_STS [09:09] */
-#define BCHP_SWITCH_CORE_RESET_STATUS_SW_CORE_RST_STS_MASK 0x00000200
-#define BCHP_SWITCH_CORE_RESET_STATUS_SW_CORE_RST_STS_SHIFT 9
-#define BCHP_SWITCH_CORE_RESET_STATUS_SW_CORE_RST_STS_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: RESET_STATUS :: SW_REG_RST_STS [08:08] */
-#define BCHP_SWITCH_CORE_RESET_STATUS_SW_REG_RST_STS_MASK 0x00000100
-#define BCHP_SWITCH_CORE_RESET_STATUS_SW_REG_RST_STS_SHIFT 8
-#define BCHP_SWITCH_CORE_RESET_STATUS_SW_REG_RST_STS_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: RESET_STATUS :: SWITCH_RESV_0 [07:06] */
-#define BCHP_SWITCH_CORE_RESET_STATUS_SWITCH_RESV_0_MASK 0x000000c0
-#define BCHP_SWITCH_CORE_RESET_STATUS_SWITCH_RESV_0_SHIFT 6
-#define BCHP_SWITCH_CORE_RESET_STATUS_SWITCH_RESV_0_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: RESET_STATUS :: SD_RST_STS [05:05] */
-#define BCHP_SWITCH_CORE_RESET_STATUS_SD_RST_STS_MASK 0x00000020
-#define BCHP_SWITCH_CORE_RESET_STATUS_SD_RST_STS_SHIFT 5
-#define BCHP_SWITCH_CORE_RESET_STATUS_SD_RST_STS_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: RESET_STATUS :: SPHY_RST_STS [04:04] */
-#define BCHP_SWITCH_CORE_RESET_STATUS_SPHY_RST_STS_MASK 0x00000010
-#define BCHP_SWITCH_CORE_RESET_STATUS_SPHY_RST_STS_SHIFT 4
-#define BCHP_SWITCH_CORE_RESET_STATUS_SPHY_RST_STS_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: RESET_STATUS :: QPHY_RST_STS [03:00] */
-#define BCHP_SWITCH_CORE_RESET_STATUS_QPHY_RST_STS_MASK 0x0000000f
-#define BCHP_SWITCH_CORE_RESET_STATUS_QPHY_RST_STS_SHIFT 0
-#define BCHP_SWITCH_CORE_RESET_STATUS_QPHY_RST_STS_DEFAULT 0x00000000
-
-/***************************************************************************
- *ENG_DET_STS - PHY Energy Detect Status Register
- ***************************************************************************/
-/* SWITCH_CORE :: ENG_DET_STS :: reserved_for_padding0 [31:08] */
-#define BCHP_SWITCH_CORE_ENG_DET_STS_reserved_for_padding0_MASK 0xffffff00
-#define BCHP_SWITCH_CORE_ENG_DET_STS_reserved_for_padding0_SHIFT 8
-
-/* SWITCH_CORE :: ENG_DET_STS :: ENG_DET_STS [07:00] */
-#define BCHP_SWITCH_CORE_ENG_DET_STS_ENG_DET_STS_MASK 0x000000ff
-#define BCHP_SWITCH_CORE_ENG_DET_STS_ENG_DET_STS_SHIFT 0
-#define BCHP_SWITCH_CORE_ENG_DET_STS_ENG_DET_STS_DEFAULT 0x00000000
-
-/***************************************************************************
- *ENG_DET_STS_CHG - PHY Energy Detect Status Change Register
- ***************************************************************************/
-/* SWITCH_CORE :: ENG_DET_STS_CHG :: reserved_for_padding0 [31:08] */
-#define BCHP_SWITCH_CORE_ENG_DET_STS_CHG_reserved_for_padding0_MASK 0xffffff00
-#define BCHP_SWITCH_CORE_ENG_DET_STS_CHG_reserved_for_padding0_SHIFT 8
-
-/* SWITCH_CORE :: ENG_DET_STS_CHG :: ENG_DET_STS_CHG [07:00] */
-#define BCHP_SWITCH_CORE_ENG_DET_STS_CHG_ENG_DET_STS_CHG_MASK 0x000000ff
-#define BCHP_SWITCH_CORE_ENG_DET_STS_CHG_ENG_DET_STS_CHG_SHIFT 0
-#define BCHP_SWITCH_CORE_ENG_DET_STS_CHG_ENG_DET_STS_CHG_DEFAULT 0x00000000
-
-/***************************************************************************
- *STREG_REG_SPARE0 - Spare 0 Register (Not2Release)
- ***************************************************************************/
-/* SWITCH_CORE :: STREG_REG_SPARE0 :: STREG_REG_SPARE0 [31:00] */
-#define BCHP_SWITCH_CORE_STREG_REG_SPARE0_STREG_REG_SPARE0_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_STREG_REG_SPARE0_STREG_REG_SPARE0_SHIFT 0
-#define BCHP_SWITCH_CORE_STREG_REG_SPARE0_STREG_REG_SPARE0_DEFAULT 0x00000000
-
-/***************************************************************************
- *STREG_REG_SPARE1 - Spare 1 Register (Not2Release)
- ***************************************************************************/
-/* SWITCH_CORE :: STREG_REG_SPARE1 :: STREG_REG_SPARE1 [31:00] */
-#define BCHP_SWITCH_CORE_STREG_REG_SPARE1_STREG_REG_SPARE1_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_STREG_REG_SPARE1_STREG_REG_SPARE1_SHIFT 0
-#define BCHP_SWITCH_CORE_STREG_REG_SPARE1_STREG_REG_SPARE1_DEFAULT 0x00000000
-
-/***************************************************************************
- *GMNGCFG - Global Management Configuration Register
- ***************************************************************************/
-/* SWITCH_CORE :: GMNGCFG :: reserved_for_padding0 [31:08] */
-#define BCHP_SWITCH_CORE_GMNGCFG_reserved_for_padding0_MASK 0xffffff00
-#define BCHP_SWITCH_CORE_GMNGCFG_reserved_for_padding0_SHIFT 8
-
-/* SWITCH_CORE :: GMNGCFG :: FRM_MNGP [07:06] */
-#define BCHP_SWITCH_CORE_GMNGCFG_FRM_MNGP_MASK 0x000000c0
-#define BCHP_SWITCH_CORE_GMNGCFG_FRM_MNGP_SHIFT 6
-#define BCHP_SWITCH_CORE_GMNGCFG_FRM_MNGP_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: GMNGCFG :: SWITCH_RESV [05:02] */
-#define BCHP_SWITCH_CORE_GMNGCFG_SWITCH_RESV_MASK 0x0000003c
-#define BCHP_SWITCH_CORE_GMNGCFG_SWITCH_RESV_SHIFT 2
-#define BCHP_SWITCH_CORE_GMNGCFG_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: GMNGCFG :: RXBPDU_EN [01:01] */
-#define BCHP_SWITCH_CORE_GMNGCFG_RXBPDU_EN_MASK 0x00000002
-#define BCHP_SWITCH_CORE_GMNGCFG_RXBPDU_EN_SHIFT 1
-#define BCHP_SWITCH_CORE_GMNGCFG_RXBPDU_EN_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: GMNGCFG :: RST_MIB_CNT [00:00] */
-#define BCHP_SWITCH_CORE_GMNGCFG_RST_MIB_CNT_MASK 0x00000001
-#define BCHP_SWITCH_CORE_GMNGCFG_RST_MIB_CNT_SHIFT 0
-#define BCHP_SWITCH_CORE_GMNGCFG_RST_MIB_CNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *IMP0_PRT_ID - IMP/IMP0 Port ID Register
- ***************************************************************************/
-/* SWITCH_CORE :: IMP0_PRT_ID :: reserved_for_padding0 [31:08] */
-#define BCHP_SWITCH_CORE_IMP0_PRT_ID_reserved_for_padding0_MASK 0xffffff00
-#define BCHP_SWITCH_CORE_IMP0_PRT_ID_reserved_for_padding0_SHIFT 8
-
-/* SWITCH_CORE :: IMP0_PRT_ID :: SWITCH_RESV [07:04] */
-#define BCHP_SWITCH_CORE_IMP0_PRT_ID_SWITCH_RESV_MASK 0x000000f0
-#define BCHP_SWITCH_CORE_IMP0_PRT_ID_SWITCH_RESV_SHIFT 4
-#define BCHP_SWITCH_CORE_IMP0_PRT_ID_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: IMP0_PRT_ID :: IMP0_PRT_ID [03:00] */
-#define BCHP_SWITCH_CORE_IMP0_PRT_ID_IMP0_PRT_ID_MASK 0x0000000f
-#define BCHP_SWITCH_CORE_IMP0_PRT_ID_IMP0_PRT_ID_SHIFT 0
-#define BCHP_SWITCH_CORE_IMP0_PRT_ID_IMP0_PRT_ID_DEFAULT 0x00000008
-
-/***************************************************************************
- *IMP1_PRT_ID - IMP1 Port ID Register
- ***************************************************************************/
-/* SWITCH_CORE :: IMP1_PRT_ID :: reserved_for_padding0 [31:08] */
-#define BCHP_SWITCH_CORE_IMP1_PRT_ID_reserved_for_padding0_MASK 0xffffff00
-#define BCHP_SWITCH_CORE_IMP1_PRT_ID_reserved_for_padding0_SHIFT 8
-
-/* SWITCH_CORE :: IMP1_PRT_ID :: SWITCH_RESV [07:04] */
-#define BCHP_SWITCH_CORE_IMP1_PRT_ID_SWITCH_RESV_MASK 0x000000f0
-#define BCHP_SWITCH_CORE_IMP1_PRT_ID_SWITCH_RESV_SHIFT 4
-#define BCHP_SWITCH_CORE_IMP1_PRT_ID_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: IMP1_PRT_ID :: IMP1_PRT_ID [03:00] */
-#define BCHP_SWITCH_CORE_IMP1_PRT_ID_IMP1_PRT_ID_MASK 0x0000000f
-#define BCHP_SWITCH_CORE_IMP1_PRT_ID_IMP1_PRT_ID_SHIFT 0
-#define BCHP_SWITCH_CORE_IMP1_PRT_ID_IMP1_PRT_ID_DEFAULT 0x00000005
-
-/***************************************************************************
- *BRCM_HDR_CTRL - BRCM Header Control Register
- ***************************************************************************/
-/* SWITCH_CORE :: BRCM_HDR_CTRL :: reserved_for_padding0 [31:08] */
-#define BCHP_SWITCH_CORE_BRCM_HDR_CTRL_reserved_for_padding0_MASK 0xffffff00
-#define BCHP_SWITCH_CORE_BRCM_HDR_CTRL_reserved_for_padding0_SHIFT 8
-
-/* SWITCH_CORE :: BRCM_HDR_CTRL :: SWITCH_RESV [07:03] */
-#define BCHP_SWITCH_CORE_BRCM_HDR_CTRL_SWITCH_RESV_MASK 0x000000f8
-#define BCHP_SWITCH_CORE_BRCM_HDR_CTRL_SWITCH_RESV_SHIFT 3
-#define BCHP_SWITCH_CORE_BRCM_HDR_CTRL_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: BRCM_HDR_CTRL :: BRCM_HDR_EN [02:00] */
-#define BCHP_SWITCH_CORE_BRCM_HDR_CTRL_BRCM_HDR_EN_MASK 0x00000007
-#define BCHP_SWITCH_CORE_BRCM_HDR_CTRL_BRCM_HDR_EN_SHIFT 0
-#define BCHP_SWITCH_CORE_BRCM_HDR_CTRL_BRCM_HDR_EN_DEFAULT 0x00000001
-
-/***************************************************************************
- *SPTAGT - Aging Time Control Register
- ***************************************************************************/
-/* SWITCH_CORE :: SPTAGT :: SWITCH_RESV [31:21] */
-#define BCHP_SWITCH_CORE_SPTAGT_SWITCH_RESV_MASK 0xffe00000
-#define BCHP_SWITCH_CORE_SPTAGT_SWITCH_RESV_SHIFT 21
-#define BCHP_SWITCH_CORE_SPTAGT_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: SPTAGT :: AGE_CHANGE_EN [20:20] */
-#define BCHP_SWITCH_CORE_SPTAGT_AGE_CHANGE_EN_MASK 0x00100000
-#define BCHP_SWITCH_CORE_SPTAGT_AGE_CHANGE_EN_SHIFT 20
-#define BCHP_SWITCH_CORE_SPTAGT_AGE_CHANGE_EN_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: SPTAGT :: AGE_TIME [19:00] */
-#define BCHP_SWITCH_CORE_SPTAGT_AGE_TIME_MASK 0x000fffff
-#define BCHP_SWITCH_CORE_SPTAGT_AGE_TIME_SHIFT 0
-#define BCHP_SWITCH_CORE_SPTAGT_AGE_TIME_DEFAULT 0x0000012c
-
-/***************************************************************************
- *BRCM_HDR_CTRL2 - BRCM Header Control 2 Register
- ***************************************************************************/
-/* SWITCH_CORE :: BRCM_HDR_CTRL2 :: reserved_for_padding0 [31:16] */
-#define BCHP_SWITCH_CORE_BRCM_HDR_CTRL2_reserved_for_padding0_MASK 0xffff0000
-#define BCHP_SWITCH_CORE_BRCM_HDR_CTRL2_reserved_for_padding0_SHIFT 16
-
-/* SWITCH_CORE :: BRCM_HDR_CTRL2 :: SWITCH_RESV_1 [15:09] */
-#define BCHP_SWITCH_CORE_BRCM_HDR_CTRL2_SWITCH_RESV_1_MASK 0x0000fe00
-#define BCHP_SWITCH_CORE_BRCM_HDR_CTRL2_SWITCH_RESV_1_SHIFT 9
-#define BCHP_SWITCH_CORE_BRCM_HDR_CTRL2_SWITCH_RESV_1_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: BRCM_HDR_CTRL2 :: SWITCH_RESV_0 [08:05] */
-#define BCHP_SWITCH_CORE_BRCM_HDR_CTRL2_SWITCH_RESV_0_MASK 0x000001e0
-#define BCHP_SWITCH_CORE_BRCM_HDR_CTRL2_SWITCH_RESV_0_SHIFT 5
-#define BCHP_SWITCH_CORE_BRCM_HDR_CTRL2_SWITCH_RESV_0_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: BRCM_HDR_CTRL2 :: BRCM_HDR_EN [04:00] */
-#define BCHP_SWITCH_CORE_BRCM_HDR_CTRL2_BRCM_HDR_EN_MASK 0x0000001f
-#define BCHP_SWITCH_CORE_BRCM_HDR_CTRL2_BRCM_HDR_EN_SHIFT 0
-#define BCHP_SWITCH_CORE_BRCM_HDR_CTRL2_BRCM_HDR_EN_DEFAULT 0x00000000
-
-/***************************************************************************
- *IPG_SHRNK_CTRL - IPG Shrink Control Register
- ***************************************************************************/
-/* SWITCH_CORE :: IPG_SHRNK_CTRL :: SWITCH_RESV [31:18] */
-#define BCHP_SWITCH_CORE_IPG_SHRNK_CTRL_SWITCH_RESV_MASK 0xfffc0000
-#define BCHP_SWITCH_CORE_IPG_SHRNK_CTRL_SWITCH_RESV_SHIFT 18
-#define BCHP_SWITCH_CORE_IPG_SHRNK_CTRL_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: IPG_SHRNK_CTRL :: IPG_SHKCTRL [17:00] */
-#define BCHP_SWITCH_CORE_IPG_SHRNK_CTRL_IPG_SHKCTRL_MASK 0x0003ffff
-#define BCHP_SWITCH_CORE_IPG_SHRNK_CTRL_IPG_SHKCTRL_SHIFT 0
-#define BCHP_SWITCH_CORE_IPG_SHRNK_CTRL_IPG_SHKCTRL_DEFAULT 0x00000000
-
-/***************************************************************************
- *MIRCAPCTL - Mirror Capture Control Register
- ***************************************************************************/
-/* SWITCH_CORE :: MIRCAPCTL :: reserved_for_padding0 [31:16] */
-#define BCHP_SWITCH_CORE_MIRCAPCTL_reserved_for_padding0_MASK 0xffff0000
-#define BCHP_SWITCH_CORE_MIRCAPCTL_reserved_for_padding0_SHIFT 16
-
-/* SWITCH_CORE :: MIRCAPCTL :: MIR_EN [15:15] */
-#define BCHP_SWITCH_CORE_MIRCAPCTL_MIR_EN_MASK 0x00008000
-#define BCHP_SWITCH_CORE_MIRCAPCTL_MIR_EN_SHIFT 15
-#define BCHP_SWITCH_CORE_MIRCAPCTL_MIR_EN_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: MIRCAPCTL :: BLK_NOT_MIR [14:14] */
-#define BCHP_SWITCH_CORE_MIRCAPCTL_BLK_NOT_MIR_MASK 0x00004000
-#define BCHP_SWITCH_CORE_MIRCAPCTL_BLK_NOT_MIR_SHIFT 14
-#define BCHP_SWITCH_CORE_MIRCAPCTL_BLK_NOT_MIR_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: MIRCAPCTL :: SWITCH_RESV_1 [13:06] */
-#define BCHP_SWITCH_CORE_MIRCAPCTL_SWITCH_RESV_1_MASK 0x00003fc0
-#define BCHP_SWITCH_CORE_MIRCAPCTL_SWITCH_RESV_1_SHIFT 6
-#define BCHP_SWITCH_CORE_MIRCAPCTL_SWITCH_RESV_1_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: MIRCAPCTL :: SWITCH_RESV_0 [05:04] */
-#define BCHP_SWITCH_CORE_MIRCAPCTL_SWITCH_RESV_0_MASK 0x00000030
-#define BCHP_SWITCH_CORE_MIRCAPCTL_SWITCH_RESV_0_SHIFT 4
-#define BCHP_SWITCH_CORE_MIRCAPCTL_SWITCH_RESV_0_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: MIRCAPCTL :: SMIR_CAP_PORT [03:00] */
-#define BCHP_SWITCH_CORE_MIRCAPCTL_SMIR_CAP_PORT_MASK 0x0000000f
-#define BCHP_SWITCH_CORE_MIRCAPCTL_SMIR_CAP_PORT_SHIFT 0
-#define BCHP_SWITCH_CORE_MIRCAPCTL_SMIR_CAP_PORT_DEFAULT 0x00000000
-
-/***************************************************************************
- *IGMIRCTL - Ingress Mirror Control Register
- ***************************************************************************/
-/* SWITCH_CORE :: IGMIRCTL :: reserved_for_padding0 [31:16] */
-#define BCHP_SWITCH_CORE_IGMIRCTL_reserved_for_padding0_MASK 0xffff0000
-#define BCHP_SWITCH_CORE_IGMIRCTL_reserved_for_padding0_SHIFT 16
-
-/* SWITCH_CORE :: IGMIRCTL :: IN_MIR_FLTR [15:14] */
-#define BCHP_SWITCH_CORE_IGMIRCTL_IN_MIR_FLTR_MASK 0x0000c000
-#define BCHP_SWITCH_CORE_IGMIRCTL_IN_MIR_FLTR_SHIFT 14
-#define BCHP_SWITCH_CORE_IGMIRCTL_IN_MIR_FLTR_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: IGMIRCTL :: IN_DIV_EN [13:13] */
-#define BCHP_SWITCH_CORE_IGMIRCTL_IN_DIV_EN_MASK 0x00002000
-#define BCHP_SWITCH_CORE_IGMIRCTL_IN_DIV_EN_SHIFT 13
-#define BCHP_SWITCH_CORE_IGMIRCTL_IN_DIV_EN_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: IGMIRCTL :: SWITCH_RESV [12:09] */
-#define BCHP_SWITCH_CORE_IGMIRCTL_SWITCH_RESV_MASK 0x00001e00
-#define BCHP_SWITCH_CORE_IGMIRCTL_SWITCH_RESV_SHIFT 9
-#define BCHP_SWITCH_CORE_IGMIRCTL_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: IGMIRCTL :: IN_MIR_MSK [08:00] */
-#define BCHP_SWITCH_CORE_IGMIRCTL_IN_MIR_MSK_MASK 0x000001ff
-#define BCHP_SWITCH_CORE_IGMIRCTL_IN_MIR_MSK_SHIFT 0
-#define BCHP_SWITCH_CORE_IGMIRCTL_IN_MIR_MSK_DEFAULT 0x00000000
-
-/***************************************************************************
- *IGMIRDIV - Ingress Mirror Divider Register
- ***************************************************************************/
-/* SWITCH_CORE :: IGMIRDIV :: reserved_for_padding0 [31:16] */
-#define BCHP_SWITCH_CORE_IGMIRDIV_reserved_for_padding0_MASK 0xffff0000
-#define BCHP_SWITCH_CORE_IGMIRDIV_reserved_for_padding0_SHIFT 16
-
-/* SWITCH_CORE :: IGMIRDIV :: SWITCH_RESV [15:10] */
-#define BCHP_SWITCH_CORE_IGMIRDIV_SWITCH_RESV_MASK 0x0000fc00
-#define BCHP_SWITCH_CORE_IGMIRDIV_SWITCH_RESV_SHIFT 10
-#define BCHP_SWITCH_CORE_IGMIRDIV_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: IGMIRDIV :: IN_MIR_DIV [09:00] */
-#define BCHP_SWITCH_CORE_IGMIRDIV_IN_MIR_DIV_MASK 0x000003ff
-#define BCHP_SWITCH_CORE_IGMIRDIV_IN_MIR_DIV_SHIFT 0
-#define BCHP_SWITCH_CORE_IGMIRDIV_IN_MIR_DIV_DEFAULT 0x00000000
-
-/***************************************************************************
- *IGMIRMAC - Ingress Mirror Mac Address Register
- ***************************************************************************/
-/* SWITCH_CORE :: IGMIRMAC :: IN_MIR_MAC [47:00] */
-#define BCHP_SWITCH_CORE_IGMIRMAC_IN_MIR_MAC_MASK 0x00000000ffff
-#define BCHP_SWITCH_CORE_IGMIRMAC_IN_MIR_MAC_SHIFT 0
-#define BCHP_SWITCH_CORE_IGMIRMAC_IN_MIR_MAC_DEFAULT 0x000000000000
-
-/***************************************************************************
- *EGMIRCTL - Egress Mirror Control Register
- ***************************************************************************/
-/* SWITCH_CORE :: EGMIRCTL :: reserved_for_padding0 [31:16] */
-#define BCHP_SWITCH_CORE_EGMIRCTL_reserved_for_padding0_MASK 0xffff0000
-#define BCHP_SWITCH_CORE_EGMIRCTL_reserved_for_padding0_SHIFT 16
-
-/* SWITCH_CORE :: EGMIRCTL :: OUT_MIR_FLTR [15:14] */
-#define BCHP_SWITCH_CORE_EGMIRCTL_OUT_MIR_FLTR_MASK 0x0000c000
-#define BCHP_SWITCH_CORE_EGMIRCTL_OUT_MIR_FLTR_SHIFT 14
-#define BCHP_SWITCH_CORE_EGMIRCTL_OUT_MIR_FLTR_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: EGMIRCTL :: OUT_DIV_EN [13:13] */
-#define BCHP_SWITCH_CORE_EGMIRCTL_OUT_DIV_EN_MASK 0x00002000
-#define BCHP_SWITCH_CORE_EGMIRCTL_OUT_DIV_EN_SHIFT 13
-#define BCHP_SWITCH_CORE_EGMIRCTL_OUT_DIV_EN_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: EGMIRCTL :: SWITCH_RESV [12:09] */
-#define BCHP_SWITCH_CORE_EGMIRCTL_SWITCH_RESV_MASK 0x00001e00
-#define BCHP_SWITCH_CORE_EGMIRCTL_SWITCH_RESV_SHIFT 9
-#define BCHP_SWITCH_CORE_EGMIRCTL_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: EGMIRCTL :: OUT_MIR_MSK [08:00] */
-#define BCHP_SWITCH_CORE_EGMIRCTL_OUT_MIR_MSK_MASK 0x000001ff
-#define BCHP_SWITCH_CORE_EGMIRCTL_OUT_MIR_MSK_SHIFT 0
-#define BCHP_SWITCH_CORE_EGMIRCTL_OUT_MIR_MSK_DEFAULT 0x00000000
-
-/***************************************************************************
- *EGMIRDIV - Egress Mirror Divider Register
- ***************************************************************************/
-/* SWITCH_CORE :: EGMIRDIV :: reserved_for_padding0 [31:16] */
-#define BCHP_SWITCH_CORE_EGMIRDIV_reserved_for_padding0_MASK 0xffff0000
-#define BCHP_SWITCH_CORE_EGMIRDIV_reserved_for_padding0_SHIFT 16
-
-/* SWITCH_CORE :: EGMIRDIV :: SWITCH_RESV [15:10] */
-#define BCHP_SWITCH_CORE_EGMIRDIV_SWITCH_RESV_MASK 0x0000fc00
-#define BCHP_SWITCH_CORE_EGMIRDIV_SWITCH_RESV_SHIFT 10
-#define BCHP_SWITCH_CORE_EGMIRDIV_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: EGMIRDIV :: OUT_MIR_DIV [09:00] */
-#define BCHP_SWITCH_CORE_EGMIRDIV_OUT_MIR_DIV_MASK 0x000003ff
-#define BCHP_SWITCH_CORE_EGMIRDIV_OUT_MIR_DIV_SHIFT 0
-#define BCHP_SWITCH_CORE_EGMIRDIV_OUT_MIR_DIV_DEFAULT 0x00000000
-
-/***************************************************************************
- *EGMIRMAC - Egress Mirror MAC Address Register
- ***************************************************************************/
-/* SWITCH_CORE :: EGMIRMAC :: OUT_MIR_MAC [47:00] */
-#define BCHP_SWITCH_CORE_EGMIRMAC_OUT_MIR_MAC_MASK 0x00000000ffff
-#define BCHP_SWITCH_CORE_EGMIRMAC_OUT_MIR_MAC_SHIFT 0
-#define BCHP_SWITCH_CORE_EGMIRMAC_OUT_MIR_MAC_DEFAULT 0x000000000000
-
-/***************************************************************************
- *MODEL_ID - Model ID Register (Not2Release)
- ***************************************************************************/
-/* SWITCH_CORE :: MODEL_ID :: MODELID [31:00] */
-#define BCHP_SWITCH_CORE_MODEL_ID_MODELID_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_MODEL_ID_MODELID_SHIFT 0
-#define BCHP_SWITCH_CORE_MODEL_ID_MODELID_DEFAULT 0x00053012
-
-/***************************************************************************
- *CHIP_REVID - Chip Version ID Register
- ***************************************************************************/
-/* SWITCH_CORE :: CHIP_REVID :: reserved_for_padding0 [31:08] */
-#define BCHP_SWITCH_CORE_CHIP_REVID_reserved_for_padding0_MASK 0xffffff00
-#define BCHP_SWITCH_CORE_CHIP_REVID_reserved_for_padding0_SHIFT 8
-
-/* SWITCH_CORE :: CHIP_REVID :: REVID [07:00] */
-#define BCHP_SWITCH_CORE_CHIP_REVID_REVID_MASK 0x000000ff
-#define BCHP_SWITCH_CORE_CHIP_REVID_REVID_SHIFT 0
-#define BCHP_SWITCH_CORE_CHIP_REVID_REVID_DEFAULT 0x00000000
-
-/***************************************************************************
- *HL_PRTC_CTRL - High Level Protocol Control Register
- ***************************************************************************/
-/* SWITCH_CORE :: HL_PRTC_CTRL :: SWITCH_RESV_1 [31:19] */
-#define BCHP_SWITCH_CORE_HL_PRTC_CTRL_SWITCH_RESV_1_MASK 0xfff80000
-#define BCHP_SWITCH_CORE_HL_PRTC_CTRL_SWITCH_RESV_1_SHIFT 19
-#define BCHP_SWITCH_CORE_HL_PRTC_CTRL_SWITCH_RESV_1_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: HL_PRTC_CTRL :: MLD_QRY_FWD_MODE [18:18] */
-#define BCHP_SWITCH_CORE_HL_PRTC_CTRL_MLD_QRY_FWD_MODE_MASK 0x00040000
-#define BCHP_SWITCH_CORE_HL_PRTC_CTRL_MLD_QRY_FWD_MODE_SHIFT 18
-#define BCHP_SWITCH_CORE_HL_PRTC_CTRL_MLD_QRY_FWD_MODE_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: HL_PRTC_CTRL :: MLD_QRY_EN [17:17] */
-#define BCHP_SWITCH_CORE_HL_PRTC_CTRL_MLD_QRY_EN_MASK 0x00020000
-#define BCHP_SWITCH_CORE_HL_PRTC_CTRL_MLD_QRY_EN_SHIFT 17
-#define BCHP_SWITCH_CORE_HL_PRTC_CTRL_MLD_QRY_EN_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: HL_PRTC_CTRL :: MLD_RPTDONE_FWD_MODE [16:16] */
-#define BCHP_SWITCH_CORE_HL_PRTC_CTRL_MLD_RPTDONE_FWD_MODE_MASK 0x00010000
-#define BCHP_SWITCH_CORE_HL_PRTC_CTRL_MLD_RPTDONE_FWD_MODE_SHIFT 16
-#define BCHP_SWITCH_CORE_HL_PRTC_CTRL_MLD_RPTDONE_FWD_MODE_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: HL_PRTC_CTRL :: MLD_RPTDONE_EN [15:15] */
-#define BCHP_SWITCH_CORE_HL_PRTC_CTRL_MLD_RPTDONE_EN_MASK 0x00008000
-#define BCHP_SWITCH_CORE_HL_PRTC_CTRL_MLD_RPTDONE_EN_SHIFT 15
-#define BCHP_SWITCH_CORE_HL_PRTC_CTRL_MLD_RPTDONE_EN_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: HL_PRTC_CTRL :: IGMP_UKN_FWD_MODE [14:14] */
-#define BCHP_SWITCH_CORE_HL_PRTC_CTRL_IGMP_UKN_FWD_MODE_MASK 0x00004000
-#define BCHP_SWITCH_CORE_HL_PRTC_CTRL_IGMP_UKN_FWD_MODE_SHIFT 14
-#define BCHP_SWITCH_CORE_HL_PRTC_CTRL_IGMP_UKN_FWD_MODE_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: HL_PRTC_CTRL :: IGMP_UKN_EN [13:13] */
-#define BCHP_SWITCH_CORE_HL_PRTC_CTRL_IGMP_UKN_EN_MASK 0x00002000
-#define BCHP_SWITCH_CORE_HL_PRTC_CTRL_IGMP_UKN_EN_SHIFT 13
-#define BCHP_SWITCH_CORE_HL_PRTC_CTRL_IGMP_UKN_EN_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: HL_PRTC_CTRL :: IGMP_QRY_FWD_MODE [12:12] */
-#define BCHP_SWITCH_CORE_HL_PRTC_CTRL_IGMP_QRY_FWD_MODE_MASK 0x00001000
-#define BCHP_SWITCH_CORE_HL_PRTC_CTRL_IGMP_QRY_FWD_MODE_SHIFT 12
-#define BCHP_SWITCH_CORE_HL_PRTC_CTRL_IGMP_QRY_FWD_MODE_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: HL_PRTC_CTRL :: IGMP_QRY_EN [11:11] */
-#define BCHP_SWITCH_CORE_HL_PRTC_CTRL_IGMP_QRY_EN_MASK 0x00000800
-#define BCHP_SWITCH_CORE_HL_PRTC_CTRL_IGMP_QRY_EN_SHIFT 11
-#define BCHP_SWITCH_CORE_HL_PRTC_CTRL_IGMP_QRY_EN_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: HL_PRTC_CTRL :: IGMP_RPTLVE_FWD_MODE [10:10] */
-#define BCHP_SWITCH_CORE_HL_PRTC_CTRL_IGMP_RPTLVE_FWD_MODE_MASK 0x00000400
-#define BCHP_SWITCH_CORE_HL_PRTC_CTRL_IGMP_RPTLVE_FWD_MODE_SHIFT 10
-#define BCHP_SWITCH_CORE_HL_PRTC_CTRL_IGMP_RPTLVE_FWD_MODE_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: HL_PRTC_CTRL :: IGMP_RPTLVE_EN [09:09] */
-#define BCHP_SWITCH_CORE_HL_PRTC_CTRL_IGMP_RPTLVE_EN_MASK 0x00000200
-#define BCHP_SWITCH_CORE_HL_PRTC_CTRL_IGMP_RPTLVE_EN_SHIFT 9
-#define BCHP_SWITCH_CORE_HL_PRTC_CTRL_IGMP_RPTLVE_EN_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: HL_PRTC_CTRL :: IGMP_DIP_EN [08:08] */
-#define BCHP_SWITCH_CORE_HL_PRTC_CTRL_IGMP_DIP_EN_MASK 0x00000100
-#define BCHP_SWITCH_CORE_HL_PRTC_CTRL_IGMP_DIP_EN_SHIFT 8
-#define BCHP_SWITCH_CORE_HL_PRTC_CTRL_IGMP_DIP_EN_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: HL_PRTC_CTRL :: SWITCH_RESV_0 [07:06] */
-#define BCHP_SWITCH_CORE_HL_PRTC_CTRL_SWITCH_RESV_0_MASK 0x000000c0
-#define BCHP_SWITCH_CORE_HL_PRTC_CTRL_SWITCH_RESV_0_SHIFT 6
-#define BCHP_SWITCH_CORE_HL_PRTC_CTRL_SWITCH_RESV_0_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: HL_PRTC_CTRL :: ICMPv6_FWD_MODE [05:05] */
-#define BCHP_SWITCH_CORE_HL_PRTC_CTRL_ICMPv6_FWD_MODE_MASK 0x00000020
-#define BCHP_SWITCH_CORE_HL_PRTC_CTRL_ICMPv6_FWD_MODE_SHIFT 5
-#define BCHP_SWITCH_CORE_HL_PRTC_CTRL_ICMPv6_FWD_MODE_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: HL_PRTC_CTRL :: ICMPV6_EN [04:04] */
-#define BCHP_SWITCH_CORE_HL_PRTC_CTRL_ICMPV6_EN_MASK 0x00000010
-#define BCHP_SWITCH_CORE_HL_PRTC_CTRL_ICMPV6_EN_SHIFT 4
-#define BCHP_SWITCH_CORE_HL_PRTC_CTRL_ICMPV6_EN_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: HL_PRTC_CTRL :: ICMPV4_EN [03:03] */
-#define BCHP_SWITCH_CORE_HL_PRTC_CTRL_ICMPV4_EN_MASK 0x00000008
-#define BCHP_SWITCH_CORE_HL_PRTC_CTRL_ICMPV4_EN_SHIFT 3
-#define BCHP_SWITCH_CORE_HL_PRTC_CTRL_ICMPV4_EN_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: HL_PRTC_CTRL :: DHCP_EN [02:02] */
-#define BCHP_SWITCH_CORE_HL_PRTC_CTRL_DHCP_EN_MASK 0x00000004
-#define BCHP_SWITCH_CORE_HL_PRTC_CTRL_DHCP_EN_SHIFT 2
-#define BCHP_SWITCH_CORE_HL_PRTC_CTRL_DHCP_EN_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: HL_PRTC_CTRL :: RARP_EN [01:01] */
-#define BCHP_SWITCH_CORE_HL_PRTC_CTRL_RARP_EN_MASK 0x00000002
-#define BCHP_SWITCH_CORE_HL_PRTC_CTRL_RARP_EN_SHIFT 1
-#define BCHP_SWITCH_CORE_HL_PRTC_CTRL_RARP_EN_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: HL_PRTC_CTRL :: ARP_EN [00:00] */
-#define BCHP_SWITCH_CORE_HL_PRTC_CTRL_ARP_EN_MASK 0x00000001
-#define BCHP_SWITCH_CORE_HL_PRTC_CTRL_ARP_EN_SHIFT 0
-#define BCHP_SWITCH_CORE_HL_PRTC_CTRL_ARP_EN_DEFAULT 0x00000000
-
-/***************************************************************************
- *RST_MIB_CNT_EN - Reset MIB Counter Enable Register
- ***************************************************************************/
-/* SWITCH_CORE :: RST_MIB_CNT_EN :: reserved_for_padding0 [31:16] */
-#define BCHP_SWITCH_CORE_RST_MIB_CNT_EN_reserved_for_padding0_MASK 0xffff0000
-#define BCHP_SWITCH_CORE_RST_MIB_CNT_EN_reserved_for_padding0_SHIFT 16
-
-/* SWITCH_CORE :: RST_MIB_CNT_EN :: SWITCH_RESV [15:09] */
-#define BCHP_SWITCH_CORE_RST_MIB_CNT_EN_SWITCH_RESV_MASK 0x0000fe00
-#define BCHP_SWITCH_CORE_RST_MIB_CNT_EN_SWITCH_RESV_SHIFT 9
-#define BCHP_SWITCH_CORE_RST_MIB_CNT_EN_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: RST_MIB_CNT_EN :: RST_MIB_CNT_EN [08:00] */
-#define BCHP_SWITCH_CORE_RST_MIB_CNT_EN_RST_MIB_CNT_EN_MASK 0x000001ff
-#define BCHP_SWITCH_CORE_RST_MIB_CNT_EN_RST_MIB_CNT_EN_SHIFT 0
-#define BCHP_SWITCH_CORE_RST_MIB_CNT_EN_RST_MIB_CNT_EN_DEFAULT 0x000001ff
-
-/***************************************************************************
- *IPG_SHRINK_2G_WA - IPG Shrink 2G Workaround Register (Not2Release)
- ***************************************************************************/
-/* SWITCH_CORE :: IPG_SHRINK_2G_WA :: reserved_for_padding0 [31:16] */
-#define BCHP_SWITCH_CORE_IPG_SHRINK_2G_WA_reserved_for_padding0_MASK 0xffff0000
-#define BCHP_SWITCH_CORE_IPG_SHRINK_2G_WA_reserved_for_padding0_SHIFT 16
-
-/* SWITCH_CORE :: IPG_SHRINK_2G_WA :: SWITCH_RESV [15:09] */
-#define BCHP_SWITCH_CORE_IPG_SHRINK_2G_WA_SWITCH_RESV_MASK 0x0000fe00
-#define BCHP_SWITCH_CORE_IPG_SHRINK_2G_WA_SWITCH_RESV_SHIFT 9
-#define BCHP_SWITCH_CORE_IPG_SHRINK_2G_WA_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: IPG_SHRINK_2G_WA :: VLD2_COND_DIS [08:00] */
-#define BCHP_SWITCH_CORE_IPG_SHRINK_2G_WA_VLD2_COND_DIS_MASK 0x000001ff
-#define BCHP_SWITCH_CORE_IPG_SHRINK_2G_WA_VLD2_COND_DIS_SHIFT 0
-#define BCHP_SWITCH_CORE_IPG_SHRINK_2G_WA_VLD2_COND_DIS_DEFAULT 0x00000000
-
-/***************************************************************************
- *MNGMODE_REG_SPARE0 - Spare 0 Register (Not2Release)
- ***************************************************************************/
-/* SWITCH_CORE :: MNGMODE_REG_SPARE0 :: MNGMODE_REG_SPARE0 [31:00] */
-#define BCHP_SWITCH_CORE_MNGMODE_REG_SPARE0_MNGMODE_REG_SPARE0_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_MNGMODE_REG_SPARE0_MNGMODE_REG_SPARE0_SHIFT 0
-#define BCHP_SWITCH_CORE_MNGMODE_REG_SPARE0_MNGMODE_REG_SPARE0_DEFAULT 0x00000000
-
-/***************************************************************************
- *MNGMODE_REG_SPARE1 - Spare 1 Register (Not2Release)
- ***************************************************************************/
-/* SWITCH_CORE :: MNGMODE_REG_SPARE1 :: MNGMODE_REG_SPARE1 [31:00] */
-#define BCHP_SWITCH_CORE_MNGMODE_REG_SPARE1_MNGMODE_REG_SPARE1_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_MNGMODE_REG_SPARE1_MNGMODE_REG_SPARE1_SHIFT 0
-#define BCHP_SWITCH_CORE_MNGMODE_REG_SPARE1_MNGMODE_REG_SPARE1_DEFAULT 0x00000000
-
-/***************************************************************************
- *INT_STS - External Host Raw Interrupt Status Register
- ***************************************************************************/
-/* SWITCH_CORE :: INT_STS :: INT_STS [31:00] */
-#define BCHP_SWITCH_CORE_INT_STS_INT_STS_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_INT_STS_INT_STS_SHIFT 0
-#define BCHP_SWITCH_CORE_INT_STS_INT_STS_DEFAULT 0x00000000
-
-/***************************************************************************
- *INT_EN - External Host Interrupt Enable Register
- ***************************************************************************/
-/* SWITCH_CORE :: INT_EN :: INT_EN [31:00] */
-#define BCHP_SWITCH_CORE_INT_EN_INT_EN_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_INT_EN_INT_EN_SHIFT 0
-#define BCHP_SWITCH_CORE_INT_EN_INT_EN_DEFAULT 0x00000000
-
-/***************************************************************************
- *IMP_SLEEP_TIMER - IMP Port(port 8) Sleep Timer Register
- ***************************************************************************/
-/* SWITCH_CORE :: IMP_SLEEP_TIMER :: reserved_for_padding0 [31:16] */
-#define BCHP_SWITCH_CORE_IMP_SLEEP_TIMER_reserved_for_padding0_MASK 0xffff0000
-#define BCHP_SWITCH_CORE_IMP_SLEEP_TIMER_reserved_for_padding0_SHIFT 16
-
-/* SWITCH_CORE :: IMP_SLEEP_TIMER :: SWITCH_RESV [15:13] */
-#define BCHP_SWITCH_CORE_IMP_SLEEP_TIMER_SWITCH_RESV_MASK 0x0000e000
-#define BCHP_SWITCH_CORE_IMP_SLEEP_TIMER_SWITCH_RESV_SHIFT 13
-#define BCHP_SWITCH_CORE_IMP_SLEEP_TIMER_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: IMP_SLEEP_TIMER :: IMP_SLEEP_TIMER [12:00] */
-#define BCHP_SWITCH_CORE_IMP_SLEEP_TIMER_IMP_SLEEP_TIMER_MASK 0x00001fff
-#define BCHP_SWITCH_CORE_IMP_SLEEP_TIMER_IMP_SLEEP_TIMER_SHIFT 0
-#define BCHP_SWITCH_CORE_IMP_SLEEP_TIMER_IMP_SLEEP_TIMER_DEFAULT 0x00000000
-
-/***************************************************************************
- *PORT7_SLEEP_TIMER - Port 7 Sleep Timer Register
- ***************************************************************************/
-/* SWITCH_CORE :: PORT7_SLEEP_TIMER :: reserved_for_padding0 [31:16] */
-#define BCHP_SWITCH_CORE_PORT7_SLEEP_TIMER_reserved_for_padding0_MASK 0xffff0000
-#define BCHP_SWITCH_CORE_PORT7_SLEEP_TIMER_reserved_for_padding0_SHIFT 16
-
-/* SWITCH_CORE :: PORT7_SLEEP_TIMER :: SWITCH_RESV [15:13] */
-#define BCHP_SWITCH_CORE_PORT7_SLEEP_TIMER_SWITCH_RESV_MASK 0x0000e000
-#define BCHP_SWITCH_CORE_PORT7_SLEEP_TIMER_SWITCH_RESV_SHIFT 13
-#define BCHP_SWITCH_CORE_PORT7_SLEEP_TIMER_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: PORT7_SLEEP_TIMER :: PORT7_SLEEP_TIMER [12:00] */
-#define BCHP_SWITCH_CORE_PORT7_SLEEP_TIMER_PORT7_SLEEP_TIMER_MASK 0x00001fff
-#define BCHP_SWITCH_CORE_PORT7_SLEEP_TIMER_PORT7_SLEEP_TIMER_SHIFT 0
-#define BCHP_SWITCH_CORE_PORT7_SLEEP_TIMER_PORT7_SLEEP_TIMER_DEFAULT 0x00000000
-
-/***************************************************************************
- *WAN_SLEEP_TIMER - WAN Port Sleep Timer Register
- ***************************************************************************/
-/* SWITCH_CORE :: WAN_SLEEP_TIMER :: reserved_for_padding0 [31:16] */
-#define BCHP_SWITCH_CORE_WAN_SLEEP_TIMER_reserved_for_padding0_MASK 0xffff0000
-#define BCHP_SWITCH_CORE_WAN_SLEEP_TIMER_reserved_for_padding0_SHIFT 16
-
-/* SWITCH_CORE :: WAN_SLEEP_TIMER :: SWITCH_RESV [15:13] */
-#define BCHP_SWITCH_CORE_WAN_SLEEP_TIMER_SWITCH_RESV_MASK 0x0000e000
-#define BCHP_SWITCH_CORE_WAN_SLEEP_TIMER_SWITCH_RESV_SHIFT 13
-#define BCHP_SWITCH_CORE_WAN_SLEEP_TIMER_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: WAN_SLEEP_TIMER :: WAN_SLEEP_TIMER [12:00] */
-#define BCHP_SWITCH_CORE_WAN_SLEEP_TIMER_WAN_SLEEP_TIMER_MASK 0x00001fff
-#define BCHP_SWITCH_CORE_WAN_SLEEP_TIMER_WAN_SLEEP_TIMER_SHIFT 0
-#define BCHP_SWITCH_CORE_WAN_SLEEP_TIMER_WAN_SLEEP_TIMER_DEFAULT 0x00000000
-
-/***************************************************************************
- *PORT_SLEEP_STS - Port Sleep Status Register
- ***************************************************************************/
-/* SWITCH_CORE :: PORT_SLEEP_STS :: reserved_for_padding0 [31:08] */
-#define BCHP_SWITCH_CORE_PORT_SLEEP_STS_reserved_for_padding0_MASK 0xffffff00
-#define BCHP_SWITCH_CORE_PORT_SLEEP_STS_reserved_for_padding0_SHIFT 8
-
-/* SWITCH_CORE :: PORT_SLEEP_STS :: SWITCH_RESV [07:03] */
-#define BCHP_SWITCH_CORE_PORT_SLEEP_STS_SWITCH_RESV_MASK 0x000000f8
-#define BCHP_SWITCH_CORE_PORT_SLEEP_STS_SWITCH_RESV_SHIFT 3
-#define BCHP_SWITCH_CORE_PORT_SLEEP_STS_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: PORT_SLEEP_STS :: PORT7_SLEEP_STS [02:02] */
-#define BCHP_SWITCH_CORE_PORT_SLEEP_STS_PORT7_SLEEP_STS_MASK 0x00000004
-#define BCHP_SWITCH_CORE_PORT_SLEEP_STS_PORT7_SLEEP_STS_SHIFT 2
-#define BCHP_SWITCH_CORE_PORT_SLEEP_STS_PORT7_SLEEP_STS_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: PORT_SLEEP_STS :: WAN_PORT_SLEEP_STS [01:01] */
-#define BCHP_SWITCH_CORE_PORT_SLEEP_STS_WAN_PORT_SLEEP_STS_MASK 0x00000002
-#define BCHP_SWITCH_CORE_PORT_SLEEP_STS_WAN_PORT_SLEEP_STS_SHIFT 1
-#define BCHP_SWITCH_CORE_PORT_SLEEP_STS_WAN_PORT_SLEEP_STS_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: PORT_SLEEP_STS :: IMP_PORT_SLEEP_STS [00:00] */
-#define BCHP_SWITCH_CORE_PORT_SLEEP_STS_IMP_PORT_SLEEP_STS_MASK 0x00000001
-#define BCHP_SWITCH_CORE_PORT_SLEEP_STS_IMP_PORT_SLEEP_STS_SHIFT 0
-#define BCHP_SWITCH_CORE_PORT_SLEEP_STS_IMP_PORT_SLEEP_STS_DEFAULT 0x00000000
-
-/***************************************************************************
- *INT_TRIGGER - Interrupt Trigger Register
- ***************************************************************************/
-/* SWITCH_CORE :: INT_TRIGGER :: SWITCH_RESV [31:03] */
-#define BCHP_SWITCH_CORE_INT_TRIGGER_SWITCH_RESV_MASK 0xfffffff8
-#define BCHP_SWITCH_CORE_INT_TRIGGER_SWITCH_RESV_SHIFT 3
-#define BCHP_SWITCH_CORE_INT_TRIGGER_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: INT_TRIGGER :: INT_CPU_DOORBELL [02:02] */
-#define BCHP_SWITCH_CORE_INT_TRIGGER_INT_CPU_DOORBELL_MASK 0x00000004
-#define BCHP_SWITCH_CORE_INT_TRIGGER_INT_CPU_DOORBELL_SHIFT 2
-#define BCHP_SWITCH_CORE_INT_TRIGGER_INT_CPU_DOORBELL_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: INT_TRIGGER :: EXT_CPU_DOORBELL [01:01] */
-#define BCHP_SWITCH_CORE_INT_TRIGGER_EXT_CPU_DOORBELL_MASK 0x00000002
-#define BCHP_SWITCH_CORE_INT_TRIGGER_EXT_CPU_DOORBELL_SHIFT 1
-#define BCHP_SWITCH_CORE_INT_TRIGGER_EXT_CPU_DOORBELL_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: INT_TRIGGER :: EXT_CPU_INT [00:00] */
-#define BCHP_SWITCH_CORE_INT_TRIGGER_EXT_CPU_INT_MASK 0x00000001
-#define BCHP_SWITCH_CORE_INT_TRIGGER_EXT_CPU_INT_SHIFT 0
-#define BCHP_SWITCH_CORE_INT_TRIGGER_EXT_CPU_INT_DEFAULT 0x00000000
-
-/***************************************************************************
- *LINK_STS_INT_EN - Link Status Interrupt Enable Register
- ***************************************************************************/
-/* SWITCH_CORE :: LINK_STS_INT_EN :: reserved_for_padding0 [31:16] */
-#define BCHP_SWITCH_CORE_LINK_STS_INT_EN_reserved_for_padding0_MASK 0xffff0000
-#define BCHP_SWITCH_CORE_LINK_STS_INT_EN_reserved_for_padding0_SHIFT 16
-
-/* SWITCH_CORE :: LINK_STS_INT_EN :: SWITCH_RESV [15:09] */
-#define BCHP_SWITCH_CORE_LINK_STS_INT_EN_SWITCH_RESV_MASK 0x0000fe00
-#define BCHP_SWITCH_CORE_LINK_STS_INT_EN_SWITCH_RESV_SHIFT 9
-#define BCHP_SWITCH_CORE_LINK_STS_INT_EN_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: LINK_STS_INT_EN :: LINK_STS_INT_EN [08:00] */
-#define BCHP_SWITCH_CORE_LINK_STS_INT_EN_LINK_STS_INT_EN_MASK 0x000001ff
-#define BCHP_SWITCH_CORE_LINK_STS_INT_EN_LINK_STS_INT_EN_SHIFT 0
-#define BCHP_SWITCH_CORE_LINK_STS_INT_EN_LINK_STS_INT_EN_DEFAULT 0x000001ff
-
-/***************************************************************************
- *ENG_DET_INT_EN - Energy Detection Interrupt Enable Register
- ***************************************************************************/
-/* SWITCH_CORE :: ENG_DET_INT_EN :: reserved_for_padding0 [31:16] */
-#define BCHP_SWITCH_CORE_ENG_DET_INT_EN_reserved_for_padding0_MASK 0xffff0000
-#define BCHP_SWITCH_CORE_ENG_DET_INT_EN_reserved_for_padding0_SHIFT 16
-
-/* SWITCH_CORE :: ENG_DET_INT_EN :: SWITCH_RESV_1 [15:09] */
-#define BCHP_SWITCH_CORE_ENG_DET_INT_EN_SWITCH_RESV_1_MASK 0x0000fe00
-#define BCHP_SWITCH_CORE_ENG_DET_INT_EN_SWITCH_RESV_1_SHIFT 9
-#define BCHP_SWITCH_CORE_ENG_DET_INT_EN_SWITCH_RESV_1_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: ENG_DET_INT_EN :: SWITCH_RESV_0 [08:05] */
-#define BCHP_SWITCH_CORE_ENG_DET_INT_EN_SWITCH_RESV_0_MASK 0x000001e0
-#define BCHP_SWITCH_CORE_ENG_DET_INT_EN_SWITCH_RESV_0_SHIFT 5
-#define BCHP_SWITCH_CORE_ENG_DET_INT_EN_SWITCH_RESV_0_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: ENG_DET_INT_EN :: ENG_DET_INT_EN [04:00] */
-#define BCHP_SWITCH_CORE_ENG_DET_INT_EN_ENG_DET_INT_EN_MASK 0x0000001f
-#define BCHP_SWITCH_CORE_ENG_DET_INT_EN_ENG_DET_INT_EN_SHIFT 0
-#define BCHP_SWITCH_CORE_ENG_DET_INT_EN_ENG_DET_INT_EN_DEFAULT 0x00000000
-
-/***************************************************************************
- *LPI_STS_CHG_INT_EN - LPI Status Change Interrupt Enable Register
- ***************************************************************************/
-/* SWITCH_CORE :: LPI_STS_CHG_INT_EN :: reserved_for_padding0 [31:16] */
-#define BCHP_SWITCH_CORE_LPI_STS_CHG_INT_EN_reserved_for_padding0_MASK 0xffff0000
-#define BCHP_SWITCH_CORE_LPI_STS_CHG_INT_EN_reserved_for_padding0_SHIFT 16
-
-/* SWITCH_CORE :: LPI_STS_CHG_INT_EN :: SWITCH_RESV [15:09] */
-#define BCHP_SWITCH_CORE_LPI_STS_CHG_INT_EN_SWITCH_RESV_MASK 0x0000fe00
-#define BCHP_SWITCH_CORE_LPI_STS_CHG_INT_EN_SWITCH_RESV_SHIFT 9
-#define BCHP_SWITCH_CORE_LPI_STS_CHG_INT_EN_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: LPI_STS_CHG_INT_EN :: LPI_STS_CHG_INT_EN [08:00] */
-#define BCHP_SWITCH_CORE_LPI_STS_CHG_INT_EN_LPI_STS_CHG_INT_EN_MASK 0x000001ff
-#define BCHP_SWITCH_CORE_LPI_STS_CHG_INT_EN_LPI_STS_CHG_INT_EN_SHIFT 0
-#define BCHP_SWITCH_CORE_LPI_STS_CHG_INT_EN_LPI_STS_CHG_INT_EN_DEFAULT 0x000001ff
-
-/***************************************************************************
- *CPU_RESOURCE_ARBITER - CPU Resource Arbitor Register
- ***************************************************************************/
-/* SWITCH_CORE :: CPU_RESOURCE_ARBITER :: reserved_for_padding0 [31:08] */
-#define BCHP_SWITCH_CORE_CPU_RESOURCE_ARBITER_reserved_for_padding0_MASK 0xffffff00
-#define BCHP_SWITCH_CORE_CPU_RESOURCE_ARBITER_reserved_for_padding0_SHIFT 8
-
-/* SWITCH_CORE :: CPU_RESOURCE_ARBITER :: SWITCH_RESV [07:02] */
-#define BCHP_SWITCH_CORE_CPU_RESOURCE_ARBITER_SWITCH_RESV_MASK 0x000000fc
-#define BCHP_SWITCH_CORE_CPU_RESOURCE_ARBITER_SWITCH_RESV_SHIFT 2
-#define BCHP_SWITCH_CORE_CPU_RESOURCE_ARBITER_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: CPU_RESOURCE_ARBITER :: EXT_CPU_REQ [01:01] */
-#define BCHP_SWITCH_CORE_CPU_RESOURCE_ARBITER_EXT_CPU_REQ_MASK 0x00000002
-#define BCHP_SWITCH_CORE_CPU_RESOURCE_ARBITER_EXT_CPU_REQ_SHIFT 1
-#define BCHP_SWITCH_CORE_CPU_RESOURCE_ARBITER_EXT_CPU_REQ_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: CPU_RESOURCE_ARBITER :: EXT_CPU_GNT [00:00] */
-#define BCHP_SWITCH_CORE_CPU_RESOURCE_ARBITER_EXT_CPU_GNT_MASK 0x00000001
-#define BCHP_SWITCH_CORE_CPU_RESOURCE_ARBITER_EXT_CPU_GNT_SHIFT 0
-#define BCHP_SWITCH_CORE_CPU_RESOURCE_ARBITER_EXT_CPU_GNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *CPU_DATA_SHARE - CPU Data Share Register
- ***************************************************************************/
-/* SWITCH_CORE :: CPU_DATA_SHARE :: CPU_DATA_SHARE [63:00] */
-#define BCHP_SWITCH_CORE_CPU_DATA_SHARE_CPU_DATA_SHARE_MASK 0x00000000ffffffff
-#define BCHP_SWITCH_CORE_CPU_DATA_SHARE_CPU_DATA_SHARE_SHIFT 0
-#define BCHP_SWITCH_CORE_CPU_DATA_SHARE_CPU_DATA_SHARE_DEFAULT 0x0000000000000000
-
-/***************************************************************************
- *CPU_DATA_SHARE_1 - CPU Data Share 1 Register
- ***************************************************************************/
-/* SWITCH_CORE :: CPU_DATA_SHARE_1 :: CPU_DATA_SHARE [63:00] */
-#define BCHP_SWITCH_CORE_CPU_DATA_SHARE_1_CPU_DATA_SHARE_MASK 0x00000000ffffffff
-#define BCHP_SWITCH_CORE_CPU_DATA_SHARE_1_CPU_DATA_SHARE_SHIFT 0
-#define BCHP_SWITCH_CORE_CPU_DATA_SHARE_1_CPU_DATA_SHARE_DEFAULT 0x0000000000000000
-
-/***************************************************************************
- *MEM_ECC_ERR_INT_STS - Memory ECC Double-Error-Detection Interrupt Status (Not2Release)
- ***************************************************************************/
-/* SWITCH_CORE :: MEM_ECC_ERR_INT_STS :: reserved_for_padding0 [31:16] */
-#define BCHP_SWITCH_CORE_MEM_ECC_ERR_INT_STS_reserved_for_padding0_MASK 0xffff0000
-#define BCHP_SWITCH_CORE_MEM_ECC_ERR_INT_STS_reserved_for_padding0_SHIFT 16
-
-/* SWITCH_CORE :: MEM_ECC_ERR_INT_STS :: SWITCH_RESV [15:11] */
-#define BCHP_SWITCH_CORE_MEM_ECC_ERR_INT_STS_SWITCH_RESV_MASK 0x0000f800
-#define BCHP_SWITCH_CORE_MEM_ECC_ERR_INT_STS_SWITCH_RESV_SHIFT 11
-#define BCHP_SWITCH_CORE_MEM_ECC_ERR_INT_STS_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: MEM_ECC_ERR_INT_STS :: TXQ_ECC_DED_INT_STS [10:10] */
-#define BCHP_SWITCH_CORE_MEM_ECC_ERR_INT_STS_TXQ_ECC_DED_INT_STS_MASK 0x00000400
-#define BCHP_SWITCH_CORE_MEM_ECC_ERR_INT_STS_TXQ_ECC_DED_INT_STS_SHIFT 10
-#define BCHP_SWITCH_CORE_MEM_ECC_ERR_INT_STS_TXQ_ECC_DED_INT_STS_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: MEM_ECC_ERR_INT_STS :: MIB_ECC_DED_INT_STS [09:09] */
-#define BCHP_SWITCH_CORE_MEM_ECC_ERR_INT_STS_MIB_ECC_DED_INT_STS_MASK 0x00000200
-#define BCHP_SWITCH_CORE_MEM_ECC_ERR_INT_STS_MIB_ECC_DED_INT_STS_SHIFT 9
-#define BCHP_SWITCH_CORE_MEM_ECC_ERR_INT_STS_MIB_ECC_DED_INT_STS_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: MEM_ECC_ERR_INT_STS :: EVT_ECC_DED_INT_STS [08:08] */
-#define BCHP_SWITCH_CORE_MEM_ECC_ERR_INT_STS_EVT_ECC_DED_INT_STS_MASK 0x00000100
-#define BCHP_SWITCH_CORE_MEM_ECC_ERR_INT_STS_EVT_ECC_DED_INT_STS_SHIFT 8
-#define BCHP_SWITCH_CORE_MEM_ECC_ERR_INT_STS_EVT_ECC_DED_INT_STS_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: MEM_ECC_ERR_INT_STS :: STS_ECC_DED_INT_STS [07:07] */
-#define BCHP_SWITCH_CORE_MEM_ECC_ERR_INT_STS_STS_ECC_DED_INT_STS_MASK 0x00000080
-#define BCHP_SWITCH_CORE_MEM_ECC_ERR_INT_STS_STS_ECC_DED_INT_STS_SHIFT 7
-#define BCHP_SWITCH_CORE_MEM_ECC_ERR_INT_STS_STS_ECC_DED_INT_STS_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: MEM_ECC_ERR_INT_STS :: ACTRAT_ECC_DED_INT_STS [06:06] */
-#define BCHP_SWITCH_CORE_MEM_ECC_ERR_INT_STS_ACTRAT_ECC_DED_INT_STS_MASK 0x00000040
-#define BCHP_SWITCH_CORE_MEM_ECC_ERR_INT_STS_ACTRAT_ECC_DED_INT_STS_SHIFT 6
-#define BCHP_SWITCH_CORE_MEM_ECC_ERR_INT_STS_ACTRAT_ECC_DED_INT_STS_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: MEM_ECC_ERR_INT_STS :: TCS_ECC_DED_INT_STS [05:05] */
-#define BCHP_SWITCH_CORE_MEM_ECC_ERR_INT_STS_TCS_ECC_DED_INT_STS_MASK 0x00000020
-#define BCHP_SWITCH_CORE_MEM_ECC_ERR_INT_STS_TCS_ECC_DED_INT_STS_SHIFT 5
-#define BCHP_SWITCH_CORE_MEM_ECC_ERR_INT_STS_TCS_ECC_DED_INT_STS_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: MEM_ECC_ERR_INT_STS :: FM_ECC_DED_INT_STS [04:04] */
-#define BCHP_SWITCH_CORE_MEM_ECC_ERR_INT_STS_FM_ECC_DED_INT_STS_MASK 0x00000010
-#define BCHP_SWITCH_CORE_MEM_ECC_ERR_INT_STS_FM_ECC_DED_INT_STS_SHIFT 4
-#define BCHP_SWITCH_CORE_MEM_ECC_ERR_INT_STS_FM_ECC_DED_INT_STS_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: MEM_ECC_ERR_INT_STS :: BT_ECC_DED_INT_STS [03:03] */
-#define BCHP_SWITCH_CORE_MEM_ECC_ERR_INT_STS_BT_ECC_DED_INT_STS_MASK 0x00000008
-#define BCHP_SWITCH_CORE_MEM_ECC_ERR_INT_STS_BT_ECC_DED_INT_STS_SHIFT 3
-#define BCHP_SWITCH_CORE_MEM_ECC_ERR_INT_STS_BT_ECC_DED_INT_STS_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: MEM_ECC_ERR_INT_STS :: VL_ECC_DED_INT_STS [02:02] */
-#define BCHP_SWITCH_CORE_MEM_ECC_ERR_INT_STS_VL_ECC_DED_INT_STS_MASK 0x00000004
-#define BCHP_SWITCH_CORE_MEM_ECC_ERR_INT_STS_VL_ECC_DED_INT_STS_SHIFT 2
-#define BCHP_SWITCH_CORE_MEM_ECC_ERR_INT_STS_VL_ECC_DED_INT_STS_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: MEM_ECC_ERR_INT_STS :: ARL_SCON_ECC_DED_INT_STS [01:01] */
-#define BCHP_SWITCH_CORE_MEM_ECC_ERR_INT_STS_ARL_SCON_ECC_DED_INT_STS_MASK 0x00000002
-#define BCHP_SWITCH_CORE_MEM_ECC_ERR_INT_STS_ARL_SCON_ECC_DED_INT_STS_SHIFT 1
-#define BCHP_SWITCH_CORE_MEM_ECC_ERR_INT_STS_ARL_SCON_ECC_DED_INT_STS_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: MEM_ECC_ERR_INT_STS :: ARL_ATMU_ECC_DED_INT_STS [00:00] */
-#define BCHP_SWITCH_CORE_MEM_ECC_ERR_INT_STS_ARL_ATMU_ECC_DED_INT_STS_MASK 0x00000001
-#define BCHP_SWITCH_CORE_MEM_ECC_ERR_INT_STS_ARL_ATMU_ECC_DED_INT_STS_SHIFT 0
-#define BCHP_SWITCH_CORE_MEM_ECC_ERR_INT_STS_ARL_ATMU_ECC_DED_INT_STS_DEFAULT 0x00000000
-
-/***************************************************************************
- *MEM_ECC_ERR_INT_EN - Memory ECC Double-Error-Detection Interrupt Enable (Not2Release)
- ***************************************************************************/
-/* SWITCH_CORE :: MEM_ECC_ERR_INT_EN :: reserved_for_padding0 [31:16] */
-#define BCHP_SWITCH_CORE_MEM_ECC_ERR_INT_EN_reserved_for_padding0_MASK 0xffff0000
-#define BCHP_SWITCH_CORE_MEM_ECC_ERR_INT_EN_reserved_for_padding0_SHIFT 16
-
-/* SWITCH_CORE :: MEM_ECC_ERR_INT_EN :: SWITCH_RESV [15:11] */
-#define BCHP_SWITCH_CORE_MEM_ECC_ERR_INT_EN_SWITCH_RESV_MASK 0x0000f800
-#define BCHP_SWITCH_CORE_MEM_ECC_ERR_INT_EN_SWITCH_RESV_SHIFT 11
-#define BCHP_SWITCH_CORE_MEM_ECC_ERR_INT_EN_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: MEM_ECC_ERR_INT_EN :: TXQ_ECC_DED_INT_EN [10:10] */
-#define BCHP_SWITCH_CORE_MEM_ECC_ERR_INT_EN_TXQ_ECC_DED_INT_EN_MASK 0x00000400
-#define BCHP_SWITCH_CORE_MEM_ECC_ERR_INT_EN_TXQ_ECC_DED_INT_EN_SHIFT 10
-#define BCHP_SWITCH_CORE_MEM_ECC_ERR_INT_EN_TXQ_ECC_DED_INT_EN_DEFAULT 0x00000001
-
-/* SWITCH_CORE :: MEM_ECC_ERR_INT_EN :: MIB_ECC_DED_INT_EN [09:09] */
-#define BCHP_SWITCH_CORE_MEM_ECC_ERR_INT_EN_MIB_ECC_DED_INT_EN_MASK 0x00000200
-#define BCHP_SWITCH_CORE_MEM_ECC_ERR_INT_EN_MIB_ECC_DED_INT_EN_SHIFT 9
-#define BCHP_SWITCH_CORE_MEM_ECC_ERR_INT_EN_MIB_ECC_DED_INT_EN_DEFAULT 0x00000001
-
-/* SWITCH_CORE :: MEM_ECC_ERR_INT_EN :: EVT_ECC_DED_INT_EN [08:08] */
-#define BCHP_SWITCH_CORE_MEM_ECC_ERR_INT_EN_EVT_ECC_DED_INT_EN_MASK 0x00000100
-#define BCHP_SWITCH_CORE_MEM_ECC_ERR_INT_EN_EVT_ECC_DED_INT_EN_SHIFT 8
-#define BCHP_SWITCH_CORE_MEM_ECC_ERR_INT_EN_EVT_ECC_DED_INT_EN_DEFAULT 0x00000001
-
-/* SWITCH_CORE :: MEM_ECC_ERR_INT_EN :: STS_ECC_DED_INT_EN [07:07] */
-#define BCHP_SWITCH_CORE_MEM_ECC_ERR_INT_EN_STS_ECC_DED_INT_EN_MASK 0x00000080
-#define BCHP_SWITCH_CORE_MEM_ECC_ERR_INT_EN_STS_ECC_DED_INT_EN_SHIFT 7
-#define BCHP_SWITCH_CORE_MEM_ECC_ERR_INT_EN_STS_ECC_DED_INT_EN_DEFAULT 0x00000001
-
-/* SWITCH_CORE :: MEM_ECC_ERR_INT_EN :: ACTRAT_ECC_DED_INT_EN [06:06] */
-#define BCHP_SWITCH_CORE_MEM_ECC_ERR_INT_EN_ACTRAT_ECC_DED_INT_EN_MASK 0x00000040
-#define BCHP_SWITCH_CORE_MEM_ECC_ERR_INT_EN_ACTRAT_ECC_DED_INT_EN_SHIFT 6
-#define BCHP_SWITCH_CORE_MEM_ECC_ERR_INT_EN_ACTRAT_ECC_DED_INT_EN_DEFAULT 0x00000001
-
-/* SWITCH_CORE :: MEM_ECC_ERR_INT_EN :: TCS_ECC_DED_INT_EN [05:05] */
-#define BCHP_SWITCH_CORE_MEM_ECC_ERR_INT_EN_TCS_ECC_DED_INT_EN_MASK 0x00000020
-#define BCHP_SWITCH_CORE_MEM_ECC_ERR_INT_EN_TCS_ECC_DED_INT_EN_SHIFT 5
-#define BCHP_SWITCH_CORE_MEM_ECC_ERR_INT_EN_TCS_ECC_DED_INT_EN_DEFAULT 0x00000001
-
-/* SWITCH_CORE :: MEM_ECC_ERR_INT_EN :: FM_ECC_DED_INT_EN [04:04] */
-#define BCHP_SWITCH_CORE_MEM_ECC_ERR_INT_EN_FM_ECC_DED_INT_EN_MASK 0x00000010
-#define BCHP_SWITCH_CORE_MEM_ECC_ERR_INT_EN_FM_ECC_DED_INT_EN_SHIFT 4
-#define BCHP_SWITCH_CORE_MEM_ECC_ERR_INT_EN_FM_ECC_DED_INT_EN_DEFAULT 0x00000001
-
-/* SWITCH_CORE :: MEM_ECC_ERR_INT_EN :: BT_ECC_DED_INT_EN [03:03] */
-#define BCHP_SWITCH_CORE_MEM_ECC_ERR_INT_EN_BT_ECC_DED_INT_EN_MASK 0x00000008
-#define BCHP_SWITCH_CORE_MEM_ECC_ERR_INT_EN_BT_ECC_DED_INT_EN_SHIFT 3
-#define BCHP_SWITCH_CORE_MEM_ECC_ERR_INT_EN_BT_ECC_DED_INT_EN_DEFAULT 0x00000001
-
-/* SWITCH_CORE :: MEM_ECC_ERR_INT_EN :: VL_ECC_DED_INT_EN [02:02] */
-#define BCHP_SWITCH_CORE_MEM_ECC_ERR_INT_EN_VL_ECC_DED_INT_EN_MASK 0x00000004
-#define BCHP_SWITCH_CORE_MEM_ECC_ERR_INT_EN_VL_ECC_DED_INT_EN_SHIFT 2
-#define BCHP_SWITCH_CORE_MEM_ECC_ERR_INT_EN_VL_ECC_DED_INT_EN_DEFAULT 0x00000001
-
-/* SWITCH_CORE :: MEM_ECC_ERR_INT_EN :: ARL_SCON_ECC_DED_INT_EN [01:01] */
-#define BCHP_SWITCH_CORE_MEM_ECC_ERR_INT_EN_ARL_SCON_ECC_DED_INT_EN_MASK 0x00000002
-#define BCHP_SWITCH_CORE_MEM_ECC_ERR_INT_EN_ARL_SCON_ECC_DED_INT_EN_SHIFT 1
-#define BCHP_SWITCH_CORE_MEM_ECC_ERR_INT_EN_ARL_SCON_ECC_DED_INT_EN_DEFAULT 0x00000001
-
-/* SWITCH_CORE :: MEM_ECC_ERR_INT_EN :: ARL_ATMU_ECC_DED_INT_EN [00:00] */
-#define BCHP_SWITCH_CORE_MEM_ECC_ERR_INT_EN_ARL_ATMU_ECC_DED_INT_EN_MASK 0x00000001
-#define BCHP_SWITCH_CORE_MEM_ECC_ERR_INT_EN_ARL_ATMU_ECC_DED_INT_EN_SHIFT 0
-#define BCHP_SWITCH_CORE_MEM_ECC_ERR_INT_EN_ARL_ATMU_ECC_DED_INT_EN_DEFAULT 0x00000001
-
-/***************************************************************************
- *PORT_EVT_ECC_ERR_STS - Per Port EVT Table ECC Double-Error-Detection Error Status (Not2Release)
- ***************************************************************************/
-/* SWITCH_CORE :: PORT_EVT_ECC_ERR_STS :: reserved_for_padding0 [31:16] */
-#define BCHP_SWITCH_CORE_PORT_EVT_ECC_ERR_STS_reserved_for_padding0_MASK 0xffff0000
-#define BCHP_SWITCH_CORE_PORT_EVT_ECC_ERR_STS_reserved_for_padding0_SHIFT 16
-
-/* SWITCH_CORE :: PORT_EVT_ECC_ERR_STS :: SWITCH_RESV [15:09] */
-#define BCHP_SWITCH_CORE_PORT_EVT_ECC_ERR_STS_SWITCH_RESV_MASK 0x0000fe00
-#define BCHP_SWITCH_CORE_PORT_EVT_ECC_ERR_STS_SWITCH_RESV_SHIFT 9
-#define BCHP_SWITCH_CORE_PORT_EVT_ECC_ERR_STS_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: PORT_EVT_ECC_ERR_STS :: EVT_ECC_ERR_STS [08:00] */
-#define BCHP_SWITCH_CORE_PORT_EVT_ECC_ERR_STS_EVT_ECC_ERR_STS_MASK 0x000001ff
-#define BCHP_SWITCH_CORE_PORT_EVT_ECC_ERR_STS_EVT_ECC_ERR_STS_SHIFT 0
-#define BCHP_SWITCH_CORE_PORT_EVT_ECC_ERR_STS_EVT_ECC_ERR_STS_DEFAULT 0x00000000
-
-/***************************************************************************
- *PORT_MIB_ECC_ERR_STS - Per Port MIB Counter ECC Double-Error-Detection Error Status (Not2Release)
- ***************************************************************************/
-/* SWITCH_CORE :: PORT_MIB_ECC_ERR_STS :: reserved_for_padding0 [31:16] */
-#define BCHP_SWITCH_CORE_PORT_MIB_ECC_ERR_STS_reserved_for_padding0_MASK 0xffff0000
-#define BCHP_SWITCH_CORE_PORT_MIB_ECC_ERR_STS_reserved_for_padding0_SHIFT 16
-
-/* SWITCH_CORE :: PORT_MIB_ECC_ERR_STS :: SWITCH_RESV [15:10] */
-#define BCHP_SWITCH_CORE_PORT_MIB_ECC_ERR_STS_SWITCH_RESV_MASK 0x0000fc00
-#define BCHP_SWITCH_CORE_PORT_MIB_ECC_ERR_STS_SWITCH_RESV_SHIFT 10
-#define BCHP_SWITCH_CORE_PORT_MIB_ECC_ERR_STS_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: PORT_MIB_ECC_ERR_STS :: MIB_ECC_ERR_STS [09:00] */
-#define BCHP_SWITCH_CORE_PORT_MIB_ECC_ERR_STS_MIB_ECC_ERR_STS_MASK 0x000003ff
-#define BCHP_SWITCH_CORE_PORT_MIB_ECC_ERR_STS_MIB_ECC_ERR_STS_SHIFT 0
-#define BCHP_SWITCH_CORE_PORT_MIB_ECC_ERR_STS_MIB_ECC_ERR_STS_DEFAULT 0x00000000
-
-/***************************************************************************
- *PORT_TXQ_ECC_ERR_STS - Per Port TXQ ECC Double-Error-Detection Error Status (Not2Release)
- ***************************************************************************/
-/* SWITCH_CORE :: PORT_TXQ_ECC_ERR_STS :: reserved_for_padding0 [31:16] */
-#define BCHP_SWITCH_CORE_PORT_TXQ_ECC_ERR_STS_reserved_for_padding0_MASK 0xffff0000
-#define BCHP_SWITCH_CORE_PORT_TXQ_ECC_ERR_STS_reserved_for_padding0_SHIFT 16
-
-/* SWITCH_CORE :: PORT_TXQ_ECC_ERR_STS :: SWITCH_RESV [15:09] */
-#define BCHP_SWITCH_CORE_PORT_TXQ_ECC_ERR_STS_SWITCH_RESV_MASK 0x0000fe00
-#define BCHP_SWITCH_CORE_PORT_TXQ_ECC_ERR_STS_SWITCH_RESV_SHIFT 9
-#define BCHP_SWITCH_CORE_PORT_TXQ_ECC_ERR_STS_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: PORT_TXQ_ECC_ERR_STS :: TXQ_ECC_ERR_STS [08:00] */
-#define BCHP_SWITCH_CORE_PORT_TXQ_ECC_ERR_STS_TXQ_ECC_ERR_STS_MASK 0x000001ff
-#define BCHP_SWITCH_CORE_PORT_TXQ_ECC_ERR_STS_TXQ_ECC_ERR_STS_SHIFT 0
-#define BCHP_SWITCH_CORE_PORT_TXQ_ECC_ERR_STS_TXQ_ECC_ERR_STS_DEFAULT 0x00000000
-
-/***************************************************************************
- *PROBE_BUS_CTL - Probe Bus Control Registers(Not2Release)
- ***************************************************************************/
-/* SWITCH_CORE :: PROBE_BUS_CTL :: PROBE_DEBUG_CTL [31:24] */
-#define BCHP_SWITCH_CORE_PROBE_BUS_CTL_PROBE_DEBUG_CTL_MASK 0xff000000
-#define BCHP_SWITCH_CORE_PROBE_BUS_CTL_PROBE_DEBUG_CTL_SHIFT 24
-#define BCHP_SWITCH_CORE_PROBE_BUS_CTL_PROBE_DEBUG_CTL_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: PROBE_BUS_CTL :: PROBE_CLK_SEL [23:16] */
-#define BCHP_SWITCH_CORE_PROBE_BUS_CTL_PROBE_CLK_SEL_MASK 0x00ff0000
-#define BCHP_SWITCH_CORE_PROBE_BUS_CTL_PROBE_CLK_SEL_SHIFT 16
-#define BCHP_SWITCH_CORE_PROBE_BUS_CTL_PROBE_CLK_SEL_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: PROBE_BUS_CTL :: PER_PORT_DEBUG_SEL [15:08] */
-#define BCHP_SWITCH_CORE_PROBE_BUS_CTL_PER_PORT_DEBUG_SEL_MASK 0x0000ff00
-#define BCHP_SWITCH_CORE_PROBE_BUS_CTL_PER_PORT_DEBUG_SEL_SHIFT 8
-#define BCHP_SWITCH_CORE_PROBE_BUS_CTL_PER_PORT_DEBUG_SEL_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: PROBE_BUS_CTL :: PER_PORT_PROBE_SEL [07:00] */
-#define BCHP_SWITCH_CORE_PROBE_BUS_CTL_PER_PORT_PROBE_SEL_MASK 0x000000ff
-#define BCHP_SWITCH_CORE_PROBE_BUS_CTL_PER_PORT_PROBE_SEL_SHIFT 0
-#define BCHP_SWITCH_CORE_PROBE_BUS_CTL_PER_PORT_PROBE_SEL_DEFAULT 0x00000000
-
-/***************************************************************************
- *MDC_EXTEND_CTRL - MDC Extend Clock Control Register (Not2Release)
- ***************************************************************************/
-/* SWITCH_CORE :: MDC_EXTEND_CTRL :: reserved_for_padding0 [31:08] */
-#define BCHP_SWITCH_CORE_MDC_EXTEND_CTRL_reserved_for_padding0_MASK 0xffffff00
-#define BCHP_SWITCH_CORE_MDC_EXTEND_CTRL_reserved_for_padding0_SHIFT 8
-
-/* SWITCH_CORE :: MDC_EXTEND_CTRL :: SWITCH_RESV [07:01] */
-#define BCHP_SWITCH_CORE_MDC_EXTEND_CTRL_SWITCH_RESV_MASK 0x000000fe
-#define BCHP_SWITCH_CORE_MDC_EXTEND_CTRL_SWITCH_RESV_SHIFT 1
-#define BCHP_SWITCH_CORE_MDC_EXTEND_CTRL_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: MDC_EXTEND_CTRL :: EXTENDED_MDC_EN [00:00] */
-#define BCHP_SWITCH_CORE_MDC_EXTEND_CTRL_EXTENDED_MDC_EN_MASK 0x00000001
-#define BCHP_SWITCH_CORE_MDC_EXTEND_CTRL_EXTENDED_MDC_EN_SHIFT 0
-#define BCHP_SWITCH_CORE_MDC_EXTEND_CTRL_EXTENDED_MDC_EN_DEFAULT 0x00000001
-
-/***************************************************************************
- *PPPOE_SESSION_PARSE_EN - PPPoE Session Packet Parsing Enable Register
- ***************************************************************************/
-/* SWITCH_CORE :: PPPOE_SESSION_PARSE_EN :: SWITCH_RESV [31:25] */
-#define BCHP_SWITCH_CORE_PPPOE_SESSION_PARSE_EN_SWITCH_RESV_MASK 0xfe000000
-#define BCHP_SWITCH_CORE_PPPOE_SESSION_PARSE_EN_SWITCH_RESV_SHIFT 25
-#define BCHP_SWITCH_CORE_PPPOE_SESSION_PARSE_EN_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: PPPOE_SESSION_PARSE_EN :: PPPOE_SESSION_PARSE_EN [24:16] */
-#define BCHP_SWITCH_CORE_PPPOE_SESSION_PARSE_EN_PPPOE_SESSION_PARSE_EN_MASK 0x01ff0000
-#define BCHP_SWITCH_CORE_PPPOE_SESSION_PARSE_EN_PPPOE_SESSION_PARSE_EN_SHIFT 16
-#define BCHP_SWITCH_CORE_PPPOE_SESSION_PARSE_EN_PPPOE_SESSION_PARSE_EN_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: PPPOE_SESSION_PARSE_EN :: PPPOE_SESSION_ETYPE [15:00] */
-#define BCHP_SWITCH_CORE_PPPOE_SESSION_PARSE_EN_PPPOE_SESSION_ETYPE_MASK 0x0000ffff
-#define BCHP_SWITCH_CORE_PPPOE_SESSION_PARSE_EN_PPPOE_SESSION_ETYPE_SHIFT 0
-#define BCHP_SWITCH_CORE_PPPOE_SESSION_PARSE_EN_PPPOE_SESSION_ETYPE_DEFAULT 0x00008864
-
-/***************************************************************************
- *CTLREG_1_REG_SPARE0 - Spare 0 Register (Not2Release)
- ***************************************************************************/
-/* SWITCH_CORE :: CTLREG_1_REG_SPARE0 :: CTLREG_1_REG_SPARE0 [31:00] */
-#define BCHP_SWITCH_CORE_CTLREG_1_REG_SPARE0_CTLREG_1_REG_SPARE0_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_CTLREG_1_REG_SPARE0_CTLREG_1_REG_SPARE0_SHIFT 0
-#define BCHP_SWITCH_CORE_CTLREG_1_REG_SPARE0_CTLREG_1_REG_SPARE0_DEFAULT 0x00000000
-
-/***************************************************************************
- *CTLREG_1_REG_SPARE1 - Spare 1 Register (Not2Release)
- ***************************************************************************/
-/* SWITCH_CORE :: CTLREG_1_REG_SPARE1 :: CTLREG_1_REG_SPARE1 [31:00] */
-#define BCHP_SWITCH_CORE_CTLREG_1_REG_SPARE1_CTLREG_1_REG_SPARE1_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_CTLREG_1_REG_SPARE1_CTLREG_1_REG_SPARE1_SHIFT 0
-#define BCHP_SWITCH_CORE_CTLREG_1_REG_SPARE1_CTLREG_1_REG_SPARE1_DEFAULT 0x00000000
-
-/***************************************************************************
- *GARLCFG - Global ARL Configuration Register
- ***************************************************************************/
-/* SWITCH_CORE :: GARLCFG :: reserved_for_padding0 [31:08] */
-#define BCHP_SWITCH_CORE_GARLCFG_reserved_for_padding0_MASK 0xffffff00
-#define BCHP_SWITCH_CORE_GARLCFG_reserved_for_padding0_SHIFT 8
-
-/* SWITCH_CORE :: GARLCFG :: SWITCH_RESV_1 [07:03] */
-#define BCHP_SWITCH_CORE_GARLCFG_SWITCH_RESV_1_MASK 0x000000f8
-#define BCHP_SWITCH_CORE_GARLCFG_SWITCH_RESV_1_SHIFT 3
-#define BCHP_SWITCH_CORE_GARLCFG_SWITCH_RESV_1_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: GARLCFG :: AGE_ACC [02:02] */
-#define BCHP_SWITCH_CORE_GARLCFG_AGE_ACC_MASK 0x00000004
-#define BCHP_SWITCH_CORE_GARLCFG_AGE_ACC_SHIFT 2
-#define BCHP_SWITCH_CORE_GARLCFG_AGE_ACC_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: GARLCFG :: SWITCH_RESV_0 [01:01] */
-#define BCHP_SWITCH_CORE_GARLCFG_SWITCH_RESV_0_MASK 0x00000002
-#define BCHP_SWITCH_CORE_GARLCFG_SWITCH_RESV_0_SHIFT 1
-#define BCHP_SWITCH_CORE_GARLCFG_SWITCH_RESV_0_DEFAULT 0x00000001
-
-/* SWITCH_CORE :: GARLCFG :: HASH_DISABLE [00:00] */
-#define BCHP_SWITCH_CORE_GARLCFG_HASH_DISABLE_MASK 0x00000001
-#define BCHP_SWITCH_CORE_GARLCFG_HASH_DISABLE_SHIFT 0
-#define BCHP_SWITCH_CORE_GARLCFG_HASH_DISABLE_DEFAULT 0x00000000
-
-/***************************************************************************
- *BPDU_MCADDR - BPDU Multicast Address Register
- ***************************************************************************/
-/* SWITCH_CORE :: BPDU_MCADDR :: BPDU_MC_ADDR [47:00] */
-#define BCHP_SWITCH_CORE_BPDU_MCADDR_BPDU_MC_ADDR_MASK 0x00000000ffff
-#define BCHP_SWITCH_CORE_BPDU_MCADDR_BPDU_MC_ADDR_SHIFT 0
-#define BCHP_SWITCH_CORE_BPDU_MCADDR_BPDU_MC_ADDR_DEFAULT 0x0000ffffffff
-
-/***************************************************************************
- *MULTI_PORT_CTL - Multiport Control Register
- ***************************************************************************/
-/* SWITCH_CORE :: MULTI_PORT_CTL :: reserved_for_padding0 [31:16] */
-#define BCHP_SWITCH_CORE_MULTI_PORT_CTL_reserved_for_padding0_MASK 0xffff0000
-#define BCHP_SWITCH_CORE_MULTI_PORT_CTL_reserved_for_padding0_SHIFT 16
-
-/* SWITCH_CORE :: MULTI_PORT_CTL :: MPORT0_TS_EN [15:15] */
-#define BCHP_SWITCH_CORE_MULTI_PORT_CTL_MPORT0_TS_EN_MASK 0x00008000
-#define BCHP_SWITCH_CORE_MULTI_PORT_CTL_MPORT0_TS_EN_SHIFT 15
-#define BCHP_SWITCH_CORE_MULTI_PORT_CTL_MPORT0_TS_EN_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: MULTI_PORT_CTL :: MPORT_DA_HIT_EN [14:14] */
-#define BCHP_SWITCH_CORE_MULTI_PORT_CTL_MPORT_DA_HIT_EN_MASK 0x00004000
-#define BCHP_SWITCH_CORE_MULTI_PORT_CTL_MPORT_DA_HIT_EN_SHIFT 14
-#define BCHP_SWITCH_CORE_MULTI_PORT_CTL_MPORT_DA_HIT_EN_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: MULTI_PORT_CTL :: SWITCH_RESV [13:12] */
-#define BCHP_SWITCH_CORE_MULTI_PORT_CTL_SWITCH_RESV_MASK 0x00003000
-#define BCHP_SWITCH_CORE_MULTI_PORT_CTL_SWITCH_RESV_SHIFT 12
-#define BCHP_SWITCH_CORE_MULTI_PORT_CTL_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: MULTI_PORT_CTL :: MPORT_CTRL5 [11:10] */
-#define BCHP_SWITCH_CORE_MULTI_PORT_CTL_MPORT_CTRL5_MASK 0x00000c00
-#define BCHP_SWITCH_CORE_MULTI_PORT_CTL_MPORT_CTRL5_SHIFT 10
-#define BCHP_SWITCH_CORE_MULTI_PORT_CTL_MPORT_CTRL5_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: MULTI_PORT_CTL :: MPORT_CTRL4 [09:08] */
-#define BCHP_SWITCH_CORE_MULTI_PORT_CTL_MPORT_CTRL4_MASK 0x00000300
-#define BCHP_SWITCH_CORE_MULTI_PORT_CTL_MPORT_CTRL4_SHIFT 8
-#define BCHP_SWITCH_CORE_MULTI_PORT_CTL_MPORT_CTRL4_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: MULTI_PORT_CTL :: MPORT_CTRL3 [07:06] */
-#define BCHP_SWITCH_CORE_MULTI_PORT_CTL_MPORT_CTRL3_MASK 0x000000c0
-#define BCHP_SWITCH_CORE_MULTI_PORT_CTL_MPORT_CTRL3_SHIFT 6
-#define BCHP_SWITCH_CORE_MULTI_PORT_CTL_MPORT_CTRL3_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: MULTI_PORT_CTL :: MPORT_CTRL2 [05:04] */
-#define BCHP_SWITCH_CORE_MULTI_PORT_CTL_MPORT_CTRL2_MASK 0x00000030
-#define BCHP_SWITCH_CORE_MULTI_PORT_CTL_MPORT_CTRL2_SHIFT 4
-#define BCHP_SWITCH_CORE_MULTI_PORT_CTL_MPORT_CTRL2_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: MULTI_PORT_CTL :: MPORT_CTRL1 [03:02] */
-#define BCHP_SWITCH_CORE_MULTI_PORT_CTL_MPORT_CTRL1_MASK 0x0000000c
-#define BCHP_SWITCH_CORE_MULTI_PORT_CTL_MPORT_CTRL1_SHIFT 2
-#define BCHP_SWITCH_CORE_MULTI_PORT_CTL_MPORT_CTRL1_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: MULTI_PORT_CTL :: MPORT_CTRL0 [01:00] */
-#define BCHP_SWITCH_CORE_MULTI_PORT_CTL_MPORT_CTRL0_MASK 0x00000003
-#define BCHP_SWITCH_CORE_MULTI_PORT_CTL_MPORT_CTRL0_SHIFT 0
-#define BCHP_SWITCH_CORE_MULTI_PORT_CTL_MPORT_CTRL0_DEFAULT 0x00000000
-
-/***************************************************************************
- *MULTIPORT_ADDR0 - Multiport Address 0 Register (Default for TS)
- ***************************************************************************/
-/* SWITCH_CORE :: MULTIPORT_ADDR0 :: MPORT_E_TYPE [63:48] */
-#define BCHP_SWITCH_CORE_MULTIPORT_ADDR0_MPORT_E_TYPE_MASK 0x00000000ffff0000
-#define BCHP_SWITCH_CORE_MULTIPORT_ADDR0_MPORT_E_TYPE_SHIFT 48
-#define BCHP_SWITCH_CORE_MULTIPORT_ADDR0_MPORT_E_TYPE_DEFAULT 0x0000000000000000
-
-/* SWITCH_CORE :: MULTIPORT_ADDR0 :: MPORT_ADDR [47:00] */
-#define BCHP_SWITCH_CORE_MULTIPORT_ADDR0_MPORT_ADDR_MASK 0x000000000000ffff
-#define BCHP_SWITCH_CORE_MULTIPORT_ADDR0_MPORT_ADDR_SHIFT 0
-#define BCHP_SWITCH_CORE_MULTIPORT_ADDR0_MPORT_ADDR_DEFAULT 0x0000000000000000
-
-/***************************************************************************
- *MPORTVEC0 - Multiport Vector 0 Register
- ***************************************************************************/
-/* SWITCH_CORE :: MPORTVEC0 :: SWITCH_RESV [31:09] */
-#define BCHP_SWITCH_CORE_MPORTVEC0_SWITCH_RESV_MASK 0xfffffe00
-#define BCHP_SWITCH_CORE_MPORTVEC0_SWITCH_RESV_SHIFT 9
-#define BCHP_SWITCH_CORE_MPORTVEC0_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: MPORTVEC0 :: PORT_VCTR [08:00] */
-#define BCHP_SWITCH_CORE_MPORTVEC0_PORT_VCTR_MASK 0x000001ff
-#define BCHP_SWITCH_CORE_MPORTVEC0_PORT_VCTR_SHIFT 0
-#define BCHP_SWITCH_CORE_MPORTVEC0_PORT_VCTR_DEFAULT 0x00000000
-
-/***************************************************************************
- *MULTIPORT_ADDR1 - Multiport Address 1 Register
- ***************************************************************************/
-/* SWITCH_CORE :: MULTIPORT_ADDR1 :: MPORT_E_TYPE [63:48] */
-#define BCHP_SWITCH_CORE_MULTIPORT_ADDR1_MPORT_E_TYPE_MASK 0x00000000ffff0000
-#define BCHP_SWITCH_CORE_MULTIPORT_ADDR1_MPORT_E_TYPE_SHIFT 48
-#define BCHP_SWITCH_CORE_MULTIPORT_ADDR1_MPORT_E_TYPE_DEFAULT 0x0000000000000000
-
-/* SWITCH_CORE :: MULTIPORT_ADDR1 :: MPORT_ADDR [47:00] */
-#define BCHP_SWITCH_CORE_MULTIPORT_ADDR1_MPORT_ADDR_MASK 0x000000000000ffff
-#define BCHP_SWITCH_CORE_MULTIPORT_ADDR1_MPORT_ADDR_SHIFT 0
-#define BCHP_SWITCH_CORE_MULTIPORT_ADDR1_MPORT_ADDR_DEFAULT 0x0000000000000000
-
-/***************************************************************************
- *MPORTVEC1 - Multiport Vector 1 Register
- ***************************************************************************/
-/* SWITCH_CORE :: MPORTVEC1 :: SWITCH_RESV [31:09] */
-#define BCHP_SWITCH_CORE_MPORTVEC1_SWITCH_RESV_MASK 0xfffffe00
-#define BCHP_SWITCH_CORE_MPORTVEC1_SWITCH_RESV_SHIFT 9
-#define BCHP_SWITCH_CORE_MPORTVEC1_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: MPORTVEC1 :: PORT_VCTR [08:00] */
-#define BCHP_SWITCH_CORE_MPORTVEC1_PORT_VCTR_MASK 0x000001ff
-#define BCHP_SWITCH_CORE_MPORTVEC1_PORT_VCTR_SHIFT 0
-#define BCHP_SWITCH_CORE_MPORTVEC1_PORT_VCTR_DEFAULT 0x00000000
-
-/***************************************************************************
- *MULTIPORT_ADDR2 - Multiport Address 2 Register
- ***************************************************************************/
-/* SWITCH_CORE :: MULTIPORT_ADDR2 :: MPORT_E_TYPE [63:48] */
-#define BCHP_SWITCH_CORE_MULTIPORT_ADDR2_MPORT_E_TYPE_MASK 0x00000000ffff0000
-#define BCHP_SWITCH_CORE_MULTIPORT_ADDR2_MPORT_E_TYPE_SHIFT 48
-#define BCHP_SWITCH_CORE_MULTIPORT_ADDR2_MPORT_E_TYPE_DEFAULT 0x0000000000000000
-
-/* SWITCH_CORE :: MULTIPORT_ADDR2 :: MPORT_ADDR [47:00] */
-#define BCHP_SWITCH_CORE_MULTIPORT_ADDR2_MPORT_ADDR_MASK 0x000000000000ffff
-#define BCHP_SWITCH_CORE_MULTIPORT_ADDR2_MPORT_ADDR_SHIFT 0
-#define BCHP_SWITCH_CORE_MULTIPORT_ADDR2_MPORT_ADDR_DEFAULT 0x0000000000000000
-
-/***************************************************************************
- *MPORTVEC2 - Multiport Vector 2 Register
- ***************************************************************************/
-/* SWITCH_CORE :: MPORTVEC2 :: SWITCH_RESV [31:09] */
-#define BCHP_SWITCH_CORE_MPORTVEC2_SWITCH_RESV_MASK 0xfffffe00
-#define BCHP_SWITCH_CORE_MPORTVEC2_SWITCH_RESV_SHIFT 9
-#define BCHP_SWITCH_CORE_MPORTVEC2_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: MPORTVEC2 :: PORT_VCTR [08:00] */
-#define BCHP_SWITCH_CORE_MPORTVEC2_PORT_VCTR_MASK 0x000001ff
-#define BCHP_SWITCH_CORE_MPORTVEC2_PORT_VCTR_SHIFT 0
-#define BCHP_SWITCH_CORE_MPORTVEC2_PORT_VCTR_DEFAULT 0x00000000
-
-/***************************************************************************
- *MULTIPORT_ADDR3 - Multiport Address 3 Register
- ***************************************************************************/
-/* SWITCH_CORE :: MULTIPORT_ADDR3 :: MPORT_E_TYPE [63:48] */
-#define BCHP_SWITCH_CORE_MULTIPORT_ADDR3_MPORT_E_TYPE_MASK 0x00000000ffff0000
-#define BCHP_SWITCH_CORE_MULTIPORT_ADDR3_MPORT_E_TYPE_SHIFT 48
-#define BCHP_SWITCH_CORE_MULTIPORT_ADDR3_MPORT_E_TYPE_DEFAULT 0x0000000000000000
-
-/* SWITCH_CORE :: MULTIPORT_ADDR3 :: MPORT_ADDR [47:00] */
-#define BCHP_SWITCH_CORE_MULTIPORT_ADDR3_MPORT_ADDR_MASK 0x000000000000ffff
-#define BCHP_SWITCH_CORE_MULTIPORT_ADDR3_MPORT_ADDR_SHIFT 0
-#define BCHP_SWITCH_CORE_MULTIPORT_ADDR3_MPORT_ADDR_DEFAULT 0x0000000000000000
-
-/***************************************************************************
- *MPORTVEC3 - Multiport Vector 3 Register
- ***************************************************************************/
-/* SWITCH_CORE :: MPORTVEC3 :: SWITCH_RESV [31:09] */
-#define BCHP_SWITCH_CORE_MPORTVEC3_SWITCH_RESV_MASK 0xfffffe00
-#define BCHP_SWITCH_CORE_MPORTVEC3_SWITCH_RESV_SHIFT 9
-#define BCHP_SWITCH_CORE_MPORTVEC3_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: MPORTVEC3 :: PORT_VCTR [08:00] */
-#define BCHP_SWITCH_CORE_MPORTVEC3_PORT_VCTR_MASK 0x000001ff
-#define BCHP_SWITCH_CORE_MPORTVEC3_PORT_VCTR_SHIFT 0
-#define BCHP_SWITCH_CORE_MPORTVEC3_PORT_VCTR_DEFAULT 0x00000000
-
-/***************************************************************************
- *MULTIPORT_ADDR4 - Multiport Address 4 Register
- ***************************************************************************/
-/* SWITCH_CORE :: MULTIPORT_ADDR4 :: MPORT_E_TYPE [63:48] */
-#define BCHP_SWITCH_CORE_MULTIPORT_ADDR4_MPORT_E_TYPE_MASK 0x00000000ffff0000
-#define BCHP_SWITCH_CORE_MULTIPORT_ADDR4_MPORT_E_TYPE_SHIFT 48
-#define BCHP_SWITCH_CORE_MULTIPORT_ADDR4_MPORT_E_TYPE_DEFAULT 0x0000000000000000
-
-/* SWITCH_CORE :: MULTIPORT_ADDR4 :: MPORT_ADDR [47:00] */
-#define BCHP_SWITCH_CORE_MULTIPORT_ADDR4_MPORT_ADDR_MASK 0x000000000000ffff
-#define BCHP_SWITCH_CORE_MULTIPORT_ADDR4_MPORT_ADDR_SHIFT 0
-#define BCHP_SWITCH_CORE_MULTIPORT_ADDR4_MPORT_ADDR_DEFAULT 0x0000000000000000
-
-/***************************************************************************
- *MPORTVEC4 - Multiport Vector 4 Register
- ***************************************************************************/
-/* SWITCH_CORE :: MPORTVEC4 :: SWITCH_RESV [31:09] */
-#define BCHP_SWITCH_CORE_MPORTVEC4_SWITCH_RESV_MASK 0xfffffe00
-#define BCHP_SWITCH_CORE_MPORTVEC4_SWITCH_RESV_SHIFT 9
-#define BCHP_SWITCH_CORE_MPORTVEC4_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: MPORTVEC4 :: PORT_VCTR [08:00] */
-#define BCHP_SWITCH_CORE_MPORTVEC4_PORT_VCTR_MASK 0x000001ff
-#define BCHP_SWITCH_CORE_MPORTVEC4_PORT_VCTR_SHIFT 0
-#define BCHP_SWITCH_CORE_MPORTVEC4_PORT_VCTR_DEFAULT 0x00000000
-
-/***************************************************************************
- *MULTIPORT_ADDR5 - Multiport Address 5 Register
- ***************************************************************************/
-/* SWITCH_CORE :: MULTIPORT_ADDR5 :: MPORT_E_TYPE [63:48] */
-#define BCHP_SWITCH_CORE_MULTIPORT_ADDR5_MPORT_E_TYPE_MASK 0x00000000ffff0000
-#define BCHP_SWITCH_CORE_MULTIPORT_ADDR5_MPORT_E_TYPE_SHIFT 48
-#define BCHP_SWITCH_CORE_MULTIPORT_ADDR5_MPORT_E_TYPE_DEFAULT 0x0000000000000000
-
-/* SWITCH_CORE :: MULTIPORT_ADDR5 :: MPORT_ADDR [47:00] */
-#define BCHP_SWITCH_CORE_MULTIPORT_ADDR5_MPORT_ADDR_MASK 0x000000000000ffff
-#define BCHP_SWITCH_CORE_MULTIPORT_ADDR5_MPORT_ADDR_SHIFT 0
-#define BCHP_SWITCH_CORE_MULTIPORT_ADDR5_MPORT_ADDR_DEFAULT 0x0000000000000000
-
-/***************************************************************************
- *MPORTVEC5 - Multiport Vector 5 Register
- ***************************************************************************/
-/* SWITCH_CORE :: MPORTVEC5 :: SWITCH_RESV [31:09] */
-#define BCHP_SWITCH_CORE_MPORTVEC5_SWITCH_RESV_MASK 0xfffffe00
-#define BCHP_SWITCH_CORE_MPORTVEC5_SWITCH_RESV_SHIFT 9
-#define BCHP_SWITCH_CORE_MPORTVEC5_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: MPORTVEC5 :: PORT_VCTR [08:00] */
-#define BCHP_SWITCH_CORE_MPORTVEC5_PORT_VCTR_MASK 0x000001ff
-#define BCHP_SWITCH_CORE_MPORTVEC5_PORT_VCTR_SHIFT 0
-#define BCHP_SWITCH_CORE_MPORTVEC5_PORT_VCTR_DEFAULT 0x00000000
-
-/***************************************************************************
- *ARL_BIN_FULL_CNTR - ARL Bin Full Counter Register
- ***************************************************************************/
-/* SWITCH_CORE :: ARL_BIN_FULL_CNTR :: ARL_BIN_FUL_CNTR [31:00] */
-#define BCHP_SWITCH_CORE_ARL_BIN_FULL_CNTR_ARL_BIN_FUL_CNTR_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_ARL_BIN_FULL_CNTR_ARL_BIN_FUL_CNTR_SHIFT 0
-#define BCHP_SWITCH_CORE_ARL_BIN_FULL_CNTR_ARL_BIN_FUL_CNTR_DEFAULT 0x00000000
-
-/***************************************************************************
- *ARL_BIN_FULL_FWD - ARL Biin Full Forward Enable Register
- ***************************************************************************/
-/* SWITCH_CORE :: ARL_BIN_FULL_FWD :: reserved_for_padding0 [31:16] */
-#define BCHP_SWITCH_CORE_ARL_BIN_FULL_FWD_reserved_for_padding0_MASK 0xffff0000
-#define BCHP_SWITCH_CORE_ARL_BIN_FULL_FWD_reserved_for_padding0_SHIFT 16
-
-/* SWITCH_CORE :: ARL_BIN_FULL_FWD :: Reserved [15:01] */
-#define BCHP_SWITCH_CORE_ARL_BIN_FULL_FWD_Reserved_MASK 0x0000fffe
-#define BCHP_SWITCH_CORE_ARL_BIN_FULL_FWD_Reserved_SHIFT 1
-#define BCHP_SWITCH_CORE_ARL_BIN_FULL_FWD_Reserved_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: ARL_BIN_FULL_FWD :: ARL_BIN_FULL_FWD_EN [00:00] */
-#define BCHP_SWITCH_CORE_ARL_BIN_FULL_FWD_ARL_BIN_FULL_FWD_EN_MASK 0x00000001
-#define BCHP_SWITCH_CORE_ARL_BIN_FULL_FWD_ARL_BIN_FULL_FWD_EN_SHIFT 0
-#define BCHP_SWITCH_CORE_ARL_BIN_FULL_FWD_ARL_BIN_FULL_FWD_EN_DEFAULT 0x00000000
-
-/***************************************************************************
- *ARLCTL_REG_SPARE0 - Spare 0 Register (Not2Release)
- ***************************************************************************/
-/* SWITCH_CORE :: ARLCTL_REG_SPARE0 :: ARLCTL_REG_SPARE0 [31:00] */
-#define BCHP_SWITCH_CORE_ARLCTL_REG_SPARE0_ARLCTL_REG_SPARE0_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_ARLCTL_REG_SPARE0_ARLCTL_REG_SPARE0_SHIFT 0
-#define BCHP_SWITCH_CORE_ARLCTL_REG_SPARE0_ARLCTL_REG_SPARE0_DEFAULT 0x00000000
-
-/***************************************************************************
- *ARLCTL_REG_SPARE1 - Spare 1 Register (Not2Release)
- ***************************************************************************/
-/* SWITCH_CORE :: ARLCTL_REG_SPARE1 :: ARLCTL_REG_SPARE1 [31:00] */
-#define BCHP_SWITCH_CORE_ARLCTL_REG_SPARE1_ARLCTL_REG_SPARE1_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_ARLCTL_REG_SPARE1_ARLCTL_REG_SPARE1_SHIFT 0
-#define BCHP_SWITCH_CORE_ARLCTL_REG_SPARE1_ARLCTL_REG_SPARE1_DEFAULT 0x00000000
-
-/***************************************************************************
- *ARLA_RWCTL - ARL Read/Write Control Register
- ***************************************************************************/
-/* SWITCH_CORE :: ARLA_RWCTL :: reserved_for_padding0 [31:08] */
-#define BCHP_SWITCH_CORE_ARLA_RWCTL_reserved_for_padding0_MASK 0xffffff00
-#define BCHP_SWITCH_CORE_ARLA_RWCTL_reserved_for_padding0_SHIFT 8
-
-/* SWITCH_CORE :: ARLA_RWCTL :: ARL_STRTDN [07:07] */
-#define BCHP_SWITCH_CORE_ARLA_RWCTL_ARL_STRTDN_MASK 0x00000080
-#define BCHP_SWITCH_CORE_ARLA_RWCTL_ARL_STRTDN_SHIFT 7
-#define BCHP_SWITCH_CORE_ARLA_RWCTL_ARL_STRTDN_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: ARLA_RWCTL :: IVL_SVL_SELECT [06:06] */
-#define BCHP_SWITCH_CORE_ARLA_RWCTL_IVL_SVL_SELECT_MASK 0x00000040
-#define BCHP_SWITCH_CORE_ARLA_RWCTL_IVL_SVL_SELECT_SHIFT 6
-#define BCHP_SWITCH_CORE_ARLA_RWCTL_IVL_SVL_SELECT_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: ARLA_RWCTL :: SWITCH_RESV [05:01] */
-#define BCHP_SWITCH_CORE_ARLA_RWCTL_SWITCH_RESV_MASK 0x0000003e
-#define BCHP_SWITCH_CORE_ARLA_RWCTL_SWITCH_RESV_SHIFT 1
-#define BCHP_SWITCH_CORE_ARLA_RWCTL_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: ARLA_RWCTL :: ARL_RW [00:00] */
-#define BCHP_SWITCH_CORE_ARLA_RWCTL_ARL_RW_MASK 0x00000001
-#define BCHP_SWITCH_CORE_ARLA_RWCTL_ARL_RW_SHIFT 0
-#define BCHP_SWITCH_CORE_ARLA_RWCTL_ARL_RW_DEFAULT 0x00000000
-
-/***************************************************************************
- *ARLA_MAC - MAC Address Index Register
- ***************************************************************************/
-/* SWITCH_CORE :: ARLA_MAC :: MAC_ADDR_INDX [47:00] */
-#define BCHP_SWITCH_CORE_ARLA_MAC_MAC_ADDR_INDX_MASK 0x00000000ffff
-#define BCHP_SWITCH_CORE_ARLA_MAC_MAC_ADDR_INDX_SHIFT 0
-#define BCHP_SWITCH_CORE_ARLA_MAC_MAC_ADDR_INDX_DEFAULT 0x000000000000
-
-/***************************************************************************
- *ARLA_VID - VID Index Register
- ***************************************************************************/
-/* SWITCH_CORE :: ARLA_VID :: reserved_for_padding0 [31:16] */
-#define BCHP_SWITCH_CORE_ARLA_VID_reserved_for_padding0_MASK 0xffff0000
-#define BCHP_SWITCH_CORE_ARLA_VID_reserved_for_padding0_SHIFT 16
-
-/* SWITCH_CORE :: ARLA_VID :: ARLA_VIDTAB_RSRV0 [15:12] */
-#define BCHP_SWITCH_CORE_ARLA_VID_ARLA_VIDTAB_RSRV0_MASK 0x0000f000
-#define BCHP_SWITCH_CORE_ARLA_VID_ARLA_VIDTAB_RSRV0_SHIFT 12
-#define BCHP_SWITCH_CORE_ARLA_VID_ARLA_VIDTAB_RSRV0_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: ARLA_VID :: ARLA_VIDTAB_INDX [11:00] */
-#define BCHP_SWITCH_CORE_ARLA_VID_ARLA_VIDTAB_INDX_MASK 0x00000fff
-#define BCHP_SWITCH_CORE_ARLA_VID_ARLA_VIDTAB_INDX_SHIFT 0
-#define BCHP_SWITCH_CORE_ARLA_VID_ARLA_VIDTAB_INDX_DEFAULT 0x00000000
-
-/***************************************************************************
- *ARLA_MACVID_ENTRY0 - ARL MAC/VID Entry 0 Register
- ***************************************************************************/
-/* SWITCH_CORE :: ARLA_MACVID_ENTRY0 :: SWITCH_RESV [63:60] */
-#define BCHP_SWITCH_CORE_ARLA_MACVID_ENTRY0_SWITCH_RESV_MASK 0x00000000f0000000
-#define BCHP_SWITCH_CORE_ARLA_MACVID_ENTRY0_SWITCH_RESV_SHIFT 60
-#define BCHP_SWITCH_CORE_ARLA_MACVID_ENTRY0_SWITCH_RESV_DEFAULT 0x0000000000000000
-
-/* SWITCH_CORE :: ARLA_MACVID_ENTRY0 :: VID [59:48] */
-#define BCHP_SWITCH_CORE_ARLA_MACVID_ENTRY0_VID_MASK 0x000000000fff0000
-#define BCHP_SWITCH_CORE_ARLA_MACVID_ENTRY0_VID_SHIFT 48
-#define BCHP_SWITCH_CORE_ARLA_MACVID_ENTRY0_VID_DEFAULT 0x0000000000000000
-
-/* SWITCH_CORE :: ARLA_MACVID_ENTRY0 :: ARL_MACADDR [47:00] */
-#define BCHP_SWITCH_CORE_ARLA_MACVID_ENTRY0_ARL_MACADDR_MASK 0x000000000000ffff
-#define BCHP_SWITCH_CORE_ARLA_MACVID_ENTRY0_ARL_MACADDR_SHIFT 0
-#define BCHP_SWITCH_CORE_ARLA_MACVID_ENTRY0_ARL_MACADDR_DEFAULT 0x0000000000000000
-
-/***************************************************************************
- *ARLA_FWD_ENTRY0 - ARL FWD Entry 0 Register
- ***************************************************************************/
-/* SWITCH_CORE :: ARLA_FWD_ENTRY0 :: SWITCH_RESV [31:17] */
-#define BCHP_SWITCH_CORE_ARLA_FWD_ENTRY0_SWITCH_RESV_MASK 0xfffe0000
-#define BCHP_SWITCH_CORE_ARLA_FWD_ENTRY0_SWITCH_RESV_SHIFT 17
-#define BCHP_SWITCH_CORE_ARLA_FWD_ENTRY0_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: ARLA_FWD_ENTRY0 :: ARL_VALID [16:16] */
-#define BCHP_SWITCH_CORE_ARLA_FWD_ENTRY0_ARL_VALID_MASK 0x00010000
-#define BCHP_SWITCH_CORE_ARLA_FWD_ENTRY0_ARL_VALID_SHIFT 16
-#define BCHP_SWITCH_CORE_ARLA_FWD_ENTRY0_ARL_VALID_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: ARLA_FWD_ENTRY0 :: ARL_STATIC [15:15] */
-#define BCHP_SWITCH_CORE_ARLA_FWD_ENTRY0_ARL_STATIC_MASK 0x00008000
-#define BCHP_SWITCH_CORE_ARLA_FWD_ENTRY0_ARL_STATIC_SHIFT 15
-#define BCHP_SWITCH_CORE_ARLA_FWD_ENTRY0_ARL_STATIC_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: ARLA_FWD_ENTRY0 :: ARL_AGE [14:14] */
-#define BCHP_SWITCH_CORE_ARLA_FWD_ENTRY0_ARL_AGE_MASK 0x00004000
-#define BCHP_SWITCH_CORE_ARLA_FWD_ENTRY0_ARL_AGE_SHIFT 14
-#define BCHP_SWITCH_CORE_ARLA_FWD_ENTRY0_ARL_AGE_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: ARLA_FWD_ENTRY0 :: ARL_PRI [13:11] */
-#define BCHP_SWITCH_CORE_ARLA_FWD_ENTRY0_ARL_PRI_MASK 0x00003800
-#define BCHP_SWITCH_CORE_ARLA_FWD_ENTRY0_ARL_PRI_SHIFT 11
-#define BCHP_SWITCH_CORE_ARLA_FWD_ENTRY0_ARL_PRI_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: ARLA_FWD_ENTRY0 :: ARL_CON [10:09] */
-#define BCHP_SWITCH_CORE_ARLA_FWD_ENTRY0_ARL_CON_MASK 0x00000600
-#define BCHP_SWITCH_CORE_ARLA_FWD_ENTRY0_ARL_CON_SHIFT 9
-#define BCHP_SWITCH_CORE_ARLA_FWD_ENTRY0_ARL_CON_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: ARLA_FWD_ENTRY0 :: PORTID [08:00] */
-#define BCHP_SWITCH_CORE_ARLA_FWD_ENTRY0_PORTID_MASK 0x000001ff
-#define BCHP_SWITCH_CORE_ARLA_FWD_ENTRY0_PORTID_SHIFT 0
-#define BCHP_SWITCH_CORE_ARLA_FWD_ENTRY0_PORTID_DEFAULT 0x00000000
-
-/***************************************************************************
- *ARLA_MACVID_ENTRY1 - ARL MAC/VID Entry 1 Register
- ***************************************************************************/
-/* SWITCH_CORE :: ARLA_MACVID_ENTRY1 :: SWITCH_RESV [63:60] */
-#define BCHP_SWITCH_CORE_ARLA_MACVID_ENTRY1_SWITCH_RESV_MASK 0x00000000f0000000
-#define BCHP_SWITCH_CORE_ARLA_MACVID_ENTRY1_SWITCH_RESV_SHIFT 60
-#define BCHP_SWITCH_CORE_ARLA_MACVID_ENTRY1_SWITCH_RESV_DEFAULT 0x0000000000000000
-
-/* SWITCH_CORE :: ARLA_MACVID_ENTRY1 :: VID [59:48] */
-#define BCHP_SWITCH_CORE_ARLA_MACVID_ENTRY1_VID_MASK 0x000000000fff0000
-#define BCHP_SWITCH_CORE_ARLA_MACVID_ENTRY1_VID_SHIFT 48
-#define BCHP_SWITCH_CORE_ARLA_MACVID_ENTRY1_VID_DEFAULT 0x0000000000000000
-
-/* SWITCH_CORE :: ARLA_MACVID_ENTRY1 :: ARL_MACADDR [47:00] */
-#define BCHP_SWITCH_CORE_ARLA_MACVID_ENTRY1_ARL_MACADDR_MASK 0x000000000000ffff
-#define BCHP_SWITCH_CORE_ARLA_MACVID_ENTRY1_ARL_MACADDR_SHIFT 0
-#define BCHP_SWITCH_CORE_ARLA_MACVID_ENTRY1_ARL_MACADDR_DEFAULT 0x0000000000000000
-
-/***************************************************************************
- *ARLA_FWD_ENTRY1 - ARL FWD Entry 1 Register
- ***************************************************************************/
-/* SWITCH_CORE :: ARLA_FWD_ENTRY1 :: SWITCH_RESV [31:17] */
-#define BCHP_SWITCH_CORE_ARLA_FWD_ENTRY1_SWITCH_RESV_MASK 0xfffe0000
-#define BCHP_SWITCH_CORE_ARLA_FWD_ENTRY1_SWITCH_RESV_SHIFT 17
-#define BCHP_SWITCH_CORE_ARLA_FWD_ENTRY1_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: ARLA_FWD_ENTRY1 :: ARL_VALID [16:16] */
-#define BCHP_SWITCH_CORE_ARLA_FWD_ENTRY1_ARL_VALID_MASK 0x00010000
-#define BCHP_SWITCH_CORE_ARLA_FWD_ENTRY1_ARL_VALID_SHIFT 16
-#define BCHP_SWITCH_CORE_ARLA_FWD_ENTRY1_ARL_VALID_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: ARLA_FWD_ENTRY1 :: ARL_STATIC [15:15] */
-#define BCHP_SWITCH_CORE_ARLA_FWD_ENTRY1_ARL_STATIC_MASK 0x00008000
-#define BCHP_SWITCH_CORE_ARLA_FWD_ENTRY1_ARL_STATIC_SHIFT 15
-#define BCHP_SWITCH_CORE_ARLA_FWD_ENTRY1_ARL_STATIC_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: ARLA_FWD_ENTRY1 :: ARL_AGE [14:14] */
-#define BCHP_SWITCH_CORE_ARLA_FWD_ENTRY1_ARL_AGE_MASK 0x00004000
-#define BCHP_SWITCH_CORE_ARLA_FWD_ENTRY1_ARL_AGE_SHIFT 14
-#define BCHP_SWITCH_CORE_ARLA_FWD_ENTRY1_ARL_AGE_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: ARLA_FWD_ENTRY1 :: ARL_PRI [13:11] */
-#define BCHP_SWITCH_CORE_ARLA_FWD_ENTRY1_ARL_PRI_MASK 0x00003800
-#define BCHP_SWITCH_CORE_ARLA_FWD_ENTRY1_ARL_PRI_SHIFT 11
-#define BCHP_SWITCH_CORE_ARLA_FWD_ENTRY1_ARL_PRI_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: ARLA_FWD_ENTRY1 :: ARL_CON [10:09] */
-#define BCHP_SWITCH_CORE_ARLA_FWD_ENTRY1_ARL_CON_MASK 0x00000600
-#define BCHP_SWITCH_CORE_ARLA_FWD_ENTRY1_ARL_CON_SHIFT 9
-#define BCHP_SWITCH_CORE_ARLA_FWD_ENTRY1_ARL_CON_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: ARLA_FWD_ENTRY1 :: PORTID [08:00] */
-#define BCHP_SWITCH_CORE_ARLA_FWD_ENTRY1_PORTID_MASK 0x000001ff
-#define BCHP_SWITCH_CORE_ARLA_FWD_ENTRY1_PORTID_SHIFT 0
-#define BCHP_SWITCH_CORE_ARLA_FWD_ENTRY1_PORTID_DEFAULT 0x00000000
-
-/***************************************************************************
- *ARLA_MACVID_ENTRY2 - ARL MAC/VID Entry 2 Register
- ***************************************************************************/
-/* SWITCH_CORE :: ARLA_MACVID_ENTRY2 :: SWITCH_RESV [63:60] */
-#define BCHP_SWITCH_CORE_ARLA_MACVID_ENTRY2_SWITCH_RESV_MASK 0x00000000f0000000
-#define BCHP_SWITCH_CORE_ARLA_MACVID_ENTRY2_SWITCH_RESV_SHIFT 60
-#define BCHP_SWITCH_CORE_ARLA_MACVID_ENTRY2_SWITCH_RESV_DEFAULT 0x0000000000000000
-
-/* SWITCH_CORE :: ARLA_MACVID_ENTRY2 :: VID [59:48] */
-#define BCHP_SWITCH_CORE_ARLA_MACVID_ENTRY2_VID_MASK 0x000000000fff0000
-#define BCHP_SWITCH_CORE_ARLA_MACVID_ENTRY2_VID_SHIFT 48
-#define BCHP_SWITCH_CORE_ARLA_MACVID_ENTRY2_VID_DEFAULT 0x0000000000000000
-
-/* SWITCH_CORE :: ARLA_MACVID_ENTRY2 :: ARL_MACADDR [47:00] */
-#define BCHP_SWITCH_CORE_ARLA_MACVID_ENTRY2_ARL_MACADDR_MASK 0x000000000000ffff
-#define BCHP_SWITCH_CORE_ARLA_MACVID_ENTRY2_ARL_MACADDR_SHIFT 0
-#define BCHP_SWITCH_CORE_ARLA_MACVID_ENTRY2_ARL_MACADDR_DEFAULT 0x0000000000000000
-
-/***************************************************************************
- *ARLA_FWD_ENTRY2 - ARL FWD Entry 2 Register
- ***************************************************************************/
-/* SWITCH_CORE :: ARLA_FWD_ENTRY2 :: SWITCH_RESV [31:17] */
-#define BCHP_SWITCH_CORE_ARLA_FWD_ENTRY2_SWITCH_RESV_MASK 0xfffe0000
-#define BCHP_SWITCH_CORE_ARLA_FWD_ENTRY2_SWITCH_RESV_SHIFT 17
-#define BCHP_SWITCH_CORE_ARLA_FWD_ENTRY2_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: ARLA_FWD_ENTRY2 :: ARL_VALID [16:16] */
-#define BCHP_SWITCH_CORE_ARLA_FWD_ENTRY2_ARL_VALID_MASK 0x00010000
-#define BCHP_SWITCH_CORE_ARLA_FWD_ENTRY2_ARL_VALID_SHIFT 16
-#define BCHP_SWITCH_CORE_ARLA_FWD_ENTRY2_ARL_VALID_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: ARLA_FWD_ENTRY2 :: ARL_STATIC [15:15] */
-#define BCHP_SWITCH_CORE_ARLA_FWD_ENTRY2_ARL_STATIC_MASK 0x00008000
-#define BCHP_SWITCH_CORE_ARLA_FWD_ENTRY2_ARL_STATIC_SHIFT 15
-#define BCHP_SWITCH_CORE_ARLA_FWD_ENTRY2_ARL_STATIC_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: ARLA_FWD_ENTRY2 :: ARL_AGE [14:14] */
-#define BCHP_SWITCH_CORE_ARLA_FWD_ENTRY2_ARL_AGE_MASK 0x00004000
-#define BCHP_SWITCH_CORE_ARLA_FWD_ENTRY2_ARL_AGE_SHIFT 14
-#define BCHP_SWITCH_CORE_ARLA_FWD_ENTRY2_ARL_AGE_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: ARLA_FWD_ENTRY2 :: ARL_PRI [13:11] */
-#define BCHP_SWITCH_CORE_ARLA_FWD_ENTRY2_ARL_PRI_MASK 0x00003800
-#define BCHP_SWITCH_CORE_ARLA_FWD_ENTRY2_ARL_PRI_SHIFT 11
-#define BCHP_SWITCH_CORE_ARLA_FWD_ENTRY2_ARL_PRI_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: ARLA_FWD_ENTRY2 :: ARL_CON [10:09] */
-#define BCHP_SWITCH_CORE_ARLA_FWD_ENTRY2_ARL_CON_MASK 0x00000600
-#define BCHP_SWITCH_CORE_ARLA_FWD_ENTRY2_ARL_CON_SHIFT 9
-#define BCHP_SWITCH_CORE_ARLA_FWD_ENTRY2_ARL_CON_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: ARLA_FWD_ENTRY2 :: PORTID [08:00] */
-#define BCHP_SWITCH_CORE_ARLA_FWD_ENTRY2_PORTID_MASK 0x000001ff
-#define BCHP_SWITCH_CORE_ARLA_FWD_ENTRY2_PORTID_SHIFT 0
-#define BCHP_SWITCH_CORE_ARLA_FWD_ENTRY2_PORTID_DEFAULT 0x00000000
-
-/***************************************************************************
- *ARLA_MACVID_ENTRY3 - ARL MAC/VID Entry 3 Register
- ***************************************************************************/
-/* SWITCH_CORE :: ARLA_MACVID_ENTRY3 :: SWITCH_RESV [63:60] */
-#define BCHP_SWITCH_CORE_ARLA_MACVID_ENTRY3_SWITCH_RESV_MASK 0x00000000f0000000
-#define BCHP_SWITCH_CORE_ARLA_MACVID_ENTRY3_SWITCH_RESV_SHIFT 60
-#define BCHP_SWITCH_CORE_ARLA_MACVID_ENTRY3_SWITCH_RESV_DEFAULT 0x0000000000000000
-
-/* SWITCH_CORE :: ARLA_MACVID_ENTRY3 :: VID [59:48] */
-#define BCHP_SWITCH_CORE_ARLA_MACVID_ENTRY3_VID_MASK 0x000000000fff0000
-#define BCHP_SWITCH_CORE_ARLA_MACVID_ENTRY3_VID_SHIFT 48
-#define BCHP_SWITCH_CORE_ARLA_MACVID_ENTRY3_VID_DEFAULT 0x0000000000000000
-
-/* SWITCH_CORE :: ARLA_MACVID_ENTRY3 :: ARL_MACADDR [47:00] */
-#define BCHP_SWITCH_CORE_ARLA_MACVID_ENTRY3_ARL_MACADDR_MASK 0x000000000000ffff
-#define BCHP_SWITCH_CORE_ARLA_MACVID_ENTRY3_ARL_MACADDR_SHIFT 0
-#define BCHP_SWITCH_CORE_ARLA_MACVID_ENTRY3_ARL_MACADDR_DEFAULT 0x0000000000000000
-
-/***************************************************************************
- *ARLA_FWD_ENTRY3 - ARL FWD Entry 3 Register
- ***************************************************************************/
-/* SWITCH_CORE :: ARLA_FWD_ENTRY3 :: SWITCH_RESV [31:17] */
-#define BCHP_SWITCH_CORE_ARLA_FWD_ENTRY3_SWITCH_RESV_MASK 0xfffe0000
-#define BCHP_SWITCH_CORE_ARLA_FWD_ENTRY3_SWITCH_RESV_SHIFT 17
-#define BCHP_SWITCH_CORE_ARLA_FWD_ENTRY3_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: ARLA_FWD_ENTRY3 :: ARL_VALID [16:16] */
-#define BCHP_SWITCH_CORE_ARLA_FWD_ENTRY3_ARL_VALID_MASK 0x00010000
-#define BCHP_SWITCH_CORE_ARLA_FWD_ENTRY3_ARL_VALID_SHIFT 16
-#define BCHP_SWITCH_CORE_ARLA_FWD_ENTRY3_ARL_VALID_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: ARLA_FWD_ENTRY3 :: ARL_STATIC [15:15] */
-#define BCHP_SWITCH_CORE_ARLA_FWD_ENTRY3_ARL_STATIC_MASK 0x00008000
-#define BCHP_SWITCH_CORE_ARLA_FWD_ENTRY3_ARL_STATIC_SHIFT 15
-#define BCHP_SWITCH_CORE_ARLA_FWD_ENTRY3_ARL_STATIC_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: ARLA_FWD_ENTRY3 :: ARL_AGE [14:14] */
-#define BCHP_SWITCH_CORE_ARLA_FWD_ENTRY3_ARL_AGE_MASK 0x00004000
-#define BCHP_SWITCH_CORE_ARLA_FWD_ENTRY3_ARL_AGE_SHIFT 14
-#define BCHP_SWITCH_CORE_ARLA_FWD_ENTRY3_ARL_AGE_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: ARLA_FWD_ENTRY3 :: ARL_PRI [13:11] */
-#define BCHP_SWITCH_CORE_ARLA_FWD_ENTRY3_ARL_PRI_MASK 0x00003800
-#define BCHP_SWITCH_CORE_ARLA_FWD_ENTRY3_ARL_PRI_SHIFT 11
-#define BCHP_SWITCH_CORE_ARLA_FWD_ENTRY3_ARL_PRI_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: ARLA_FWD_ENTRY3 :: ARL_CON [10:09] */
-#define BCHP_SWITCH_CORE_ARLA_FWD_ENTRY3_ARL_CON_MASK 0x00000600
-#define BCHP_SWITCH_CORE_ARLA_FWD_ENTRY3_ARL_CON_SHIFT 9
-#define BCHP_SWITCH_CORE_ARLA_FWD_ENTRY3_ARL_CON_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: ARLA_FWD_ENTRY3 :: PORTID [08:00] */
-#define BCHP_SWITCH_CORE_ARLA_FWD_ENTRY3_PORTID_MASK 0x000001ff
-#define BCHP_SWITCH_CORE_ARLA_FWD_ENTRY3_PORTID_SHIFT 0
-#define BCHP_SWITCH_CORE_ARLA_FWD_ENTRY3_PORTID_DEFAULT 0x00000000
-
-/***************************************************************************
- *ARLA_SRCH_CTL - ARL Search Control Register
- ***************************************************************************/
-/* SWITCH_CORE :: ARLA_SRCH_CTL :: reserved_for_padding0 [31:08] */
-#define BCHP_SWITCH_CORE_ARLA_SRCH_CTL_reserved_for_padding0_MASK 0xffffff00
-#define BCHP_SWITCH_CORE_ARLA_SRCH_CTL_reserved_for_padding0_SHIFT 8
-
-/* SWITCH_CORE :: ARLA_SRCH_CTL :: ARLA_SRCH_STDN [07:07] */
-#define BCHP_SWITCH_CORE_ARLA_SRCH_CTL_ARLA_SRCH_STDN_MASK 0x00000080
-#define BCHP_SWITCH_CORE_ARLA_SRCH_CTL_ARLA_SRCH_STDN_SHIFT 7
-#define BCHP_SWITCH_CORE_ARLA_SRCH_CTL_ARLA_SRCH_STDN_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: ARLA_SRCH_CTL :: SWITCH_RESV [06:01] */
-#define BCHP_SWITCH_CORE_ARLA_SRCH_CTL_SWITCH_RESV_MASK 0x0000007e
-#define BCHP_SWITCH_CORE_ARLA_SRCH_CTL_SWITCH_RESV_SHIFT 1
-#define BCHP_SWITCH_CORE_ARLA_SRCH_CTL_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: ARLA_SRCH_CTL :: ARLA_SRCH_VLID [00:00] */
-#define BCHP_SWITCH_CORE_ARLA_SRCH_CTL_ARLA_SRCH_VLID_MASK 0x00000001
-#define BCHP_SWITCH_CORE_ARLA_SRCH_CTL_ARLA_SRCH_VLID_SHIFT 0
-#define BCHP_SWITCH_CORE_ARLA_SRCH_CTL_ARLA_SRCH_VLID_DEFAULT 0x00000000
-
-/***************************************************************************
- *ARLA_SRCH_ADR - ARL Search Address Register
- ***************************************************************************/
-/* SWITCH_CORE :: ARLA_SRCH_ADR :: reserved_for_padding0 [31:16] */
-#define BCHP_SWITCH_CORE_ARLA_SRCH_ADR_reserved_for_padding0_MASK 0xffff0000
-#define BCHP_SWITCH_CORE_ARLA_SRCH_ADR_reserved_for_padding0_SHIFT 16
-
-/* SWITCH_CORE :: ARLA_SRCH_ADR :: ARLA_SRCH_ADR_VALID [15:15] */
-#define BCHP_SWITCH_CORE_ARLA_SRCH_ADR_ARLA_SRCH_ADR_VALID_MASK 0x00008000
-#define BCHP_SWITCH_CORE_ARLA_SRCH_ADR_ARLA_SRCH_ADR_VALID_SHIFT 15
-#define BCHP_SWITCH_CORE_ARLA_SRCH_ADR_ARLA_SRCH_ADR_VALID_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: ARLA_SRCH_ADR :: ARLA_SRCH_ADDRESS [14:00] */
-#define BCHP_SWITCH_CORE_ARLA_SRCH_ADR_ARLA_SRCH_ADDRESS_MASK 0x00007fff
-#define BCHP_SWITCH_CORE_ARLA_SRCH_ADR_ARLA_SRCH_ADDRESS_SHIFT 0
-#define BCHP_SWITCH_CORE_ARLA_SRCH_ADR_ARLA_SRCH_ADDRESS_DEFAULT 0x00000000
-
-/***************************************************************************
- *ARLA_SRCH_RSLT_0_MACVID - ARL Search MAC/VID Result 0 Register
- ***************************************************************************/
-/* SWITCH_CORE :: ARLA_SRCH_RSLT_0_MACVID :: SWITCH_RESV [63:60] */
-#define BCHP_SWITCH_CORE_ARLA_SRCH_RSLT_0_MACVID_SWITCH_RESV_MASK 0x00000000f0000000
-#define BCHP_SWITCH_CORE_ARLA_SRCH_RSLT_0_MACVID_SWITCH_RESV_SHIFT 60
-#define BCHP_SWITCH_CORE_ARLA_SRCH_RSLT_0_MACVID_SWITCH_RESV_DEFAULT 0x0000000000000000
-
-/* SWITCH_CORE :: ARLA_SRCH_RSLT_0_MACVID :: ARLA_SRCH_RSLT_VID_0 [59:48] */
-#define BCHP_SWITCH_CORE_ARLA_SRCH_RSLT_0_MACVID_ARLA_SRCH_RSLT_VID_0_MASK 0x000000000fff0000
-#define BCHP_SWITCH_CORE_ARLA_SRCH_RSLT_0_MACVID_ARLA_SRCH_RSLT_VID_0_SHIFT 48
-#define BCHP_SWITCH_CORE_ARLA_SRCH_RSLT_0_MACVID_ARLA_SRCH_RSLT_VID_0_DEFAULT 0x0000000000000000
-
-/* SWITCH_CORE :: ARLA_SRCH_RSLT_0_MACVID :: ARLA_SRCH_MACADDR_0 [47:00] */
-#define BCHP_SWITCH_CORE_ARLA_SRCH_RSLT_0_MACVID_ARLA_SRCH_MACADDR_0_MASK 0x000000000000ffff
-#define BCHP_SWITCH_CORE_ARLA_SRCH_RSLT_0_MACVID_ARLA_SRCH_MACADDR_0_SHIFT 0
-#define BCHP_SWITCH_CORE_ARLA_SRCH_RSLT_0_MACVID_ARLA_SRCH_MACADDR_0_DEFAULT 0x0000000000000000
-
-/***************************************************************************
- *ARLA_SRCH_RSLT_0 - ARL Search Result 0 Register
- ***************************************************************************/
-/* SWITCH_CORE :: ARLA_SRCH_RSLT_0 :: SWITCH_RESV [31:17] */
-#define BCHP_SWITCH_CORE_ARLA_SRCH_RSLT_0_SWITCH_RESV_MASK 0xfffe0000
-#define BCHP_SWITCH_CORE_ARLA_SRCH_RSLT_0_SWITCH_RESV_SHIFT 17
-#define BCHP_SWITCH_CORE_ARLA_SRCH_RSLT_0_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: ARLA_SRCH_RSLT_0 :: ARLA_SRCH_RSLT_VLID_0 [16:16] */
-#define BCHP_SWITCH_CORE_ARLA_SRCH_RSLT_0_ARLA_SRCH_RSLT_VLID_0_MASK 0x00010000
-#define BCHP_SWITCH_CORE_ARLA_SRCH_RSLT_0_ARLA_SRCH_RSLT_VLID_0_SHIFT 16
-#define BCHP_SWITCH_CORE_ARLA_SRCH_RSLT_0_ARLA_SRCH_RSLT_VLID_0_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: ARLA_SRCH_RSLT_0 :: ARLA_SRCH_RSLT_STATIC_0 [15:15] */
-#define BCHP_SWITCH_CORE_ARLA_SRCH_RSLT_0_ARLA_SRCH_RSLT_STATIC_0_MASK 0x00008000
-#define BCHP_SWITCH_CORE_ARLA_SRCH_RSLT_0_ARLA_SRCH_RSLT_STATIC_0_SHIFT 15
-#define BCHP_SWITCH_CORE_ARLA_SRCH_RSLT_0_ARLA_SRCH_RSLT_STATIC_0_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: ARLA_SRCH_RSLT_0 :: ARLA_SRCH_RSLT_AGE_0 [14:14] */
-#define BCHP_SWITCH_CORE_ARLA_SRCH_RSLT_0_ARLA_SRCH_RSLT_AGE_0_MASK 0x00004000
-#define BCHP_SWITCH_CORE_ARLA_SRCH_RSLT_0_ARLA_SRCH_RSLT_AGE_0_SHIFT 14
-#define BCHP_SWITCH_CORE_ARLA_SRCH_RSLT_0_ARLA_SRCH_RSLT_AGE_0_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: ARLA_SRCH_RSLT_0 :: ARLA_SRCH_RSLT_PRI_0 [13:11] */
-#define BCHP_SWITCH_CORE_ARLA_SRCH_RSLT_0_ARLA_SRCH_RSLT_PRI_0_MASK 0x00003800
-#define BCHP_SWITCH_CORE_ARLA_SRCH_RSLT_0_ARLA_SRCH_RSLT_PRI_0_SHIFT 11
-#define BCHP_SWITCH_CORE_ARLA_SRCH_RSLT_0_ARLA_SRCH_RSLT_PRI_0_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: ARLA_SRCH_RSLT_0 :: ARL_CON_0 [10:09] */
-#define BCHP_SWITCH_CORE_ARLA_SRCH_RSLT_0_ARL_CON_0_MASK 0x00000600
-#define BCHP_SWITCH_CORE_ARLA_SRCH_RSLT_0_ARL_CON_0_SHIFT 9
-#define BCHP_SWITCH_CORE_ARLA_SRCH_RSLT_0_ARL_CON_0_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: ARLA_SRCH_RSLT_0 :: PORTID_0 [08:00] */
-#define BCHP_SWITCH_CORE_ARLA_SRCH_RSLT_0_PORTID_0_MASK 0x000001ff
-#define BCHP_SWITCH_CORE_ARLA_SRCH_RSLT_0_PORTID_0_SHIFT 0
-#define BCHP_SWITCH_CORE_ARLA_SRCH_RSLT_0_PORTID_0_DEFAULT 0x00000000
-
-/***************************************************************************
- *ARLA_SRCH_RSLT_1_MACVID - ARL Search MAC/VID Result 1 Register
- ***************************************************************************/
-/* SWITCH_CORE :: ARLA_SRCH_RSLT_1_MACVID :: SWITCH_RESV [63:60] */
-#define BCHP_SWITCH_CORE_ARLA_SRCH_RSLT_1_MACVID_SWITCH_RESV_MASK 0x00000000f0000000
-#define BCHP_SWITCH_CORE_ARLA_SRCH_RSLT_1_MACVID_SWITCH_RESV_SHIFT 60
-#define BCHP_SWITCH_CORE_ARLA_SRCH_RSLT_1_MACVID_SWITCH_RESV_DEFAULT 0x0000000000000000
-
-/* SWITCH_CORE :: ARLA_SRCH_RSLT_1_MACVID :: ARLA_SRCH_RSLT_VID_1 [59:48] */
-#define BCHP_SWITCH_CORE_ARLA_SRCH_RSLT_1_MACVID_ARLA_SRCH_RSLT_VID_1_MASK 0x000000000fff0000
-#define BCHP_SWITCH_CORE_ARLA_SRCH_RSLT_1_MACVID_ARLA_SRCH_RSLT_VID_1_SHIFT 48
-#define BCHP_SWITCH_CORE_ARLA_SRCH_RSLT_1_MACVID_ARLA_SRCH_RSLT_VID_1_DEFAULT 0x0000000000000000
-
-/* SWITCH_CORE :: ARLA_SRCH_RSLT_1_MACVID :: ARLA_SRCH_MACADDR_1 [47:00] */
-#define BCHP_SWITCH_CORE_ARLA_SRCH_RSLT_1_MACVID_ARLA_SRCH_MACADDR_1_MASK 0x000000000000ffff
-#define BCHP_SWITCH_CORE_ARLA_SRCH_RSLT_1_MACVID_ARLA_SRCH_MACADDR_1_SHIFT 0
-#define BCHP_SWITCH_CORE_ARLA_SRCH_RSLT_1_MACVID_ARLA_SRCH_MACADDR_1_DEFAULT 0x0000000000000000
-
-/***************************************************************************
- *ARLA_SRCH_RSLT_1 - ARL Search Result 1 Register
- ***************************************************************************/
-/* SWITCH_CORE :: ARLA_SRCH_RSLT_1 :: SWITCH_RESV [31:17] */
-#define BCHP_SWITCH_CORE_ARLA_SRCH_RSLT_1_SWITCH_RESV_MASK 0xfffe0000
-#define BCHP_SWITCH_CORE_ARLA_SRCH_RSLT_1_SWITCH_RESV_SHIFT 17
-#define BCHP_SWITCH_CORE_ARLA_SRCH_RSLT_1_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: ARLA_SRCH_RSLT_1 :: ARLA_SRCH_RSLT_VLID_1 [16:16] */
-#define BCHP_SWITCH_CORE_ARLA_SRCH_RSLT_1_ARLA_SRCH_RSLT_VLID_1_MASK 0x00010000
-#define BCHP_SWITCH_CORE_ARLA_SRCH_RSLT_1_ARLA_SRCH_RSLT_VLID_1_SHIFT 16
-#define BCHP_SWITCH_CORE_ARLA_SRCH_RSLT_1_ARLA_SRCH_RSLT_VLID_1_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: ARLA_SRCH_RSLT_1 :: ARLA_SRCH_RSLT_STATIC_1 [15:15] */
-#define BCHP_SWITCH_CORE_ARLA_SRCH_RSLT_1_ARLA_SRCH_RSLT_STATIC_1_MASK 0x00008000
-#define BCHP_SWITCH_CORE_ARLA_SRCH_RSLT_1_ARLA_SRCH_RSLT_STATIC_1_SHIFT 15
-#define BCHP_SWITCH_CORE_ARLA_SRCH_RSLT_1_ARLA_SRCH_RSLT_STATIC_1_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: ARLA_SRCH_RSLT_1 :: ARLA_SRCH_RSLT_AGE_1 [14:14] */
-#define BCHP_SWITCH_CORE_ARLA_SRCH_RSLT_1_ARLA_SRCH_RSLT_AGE_1_MASK 0x00004000
-#define BCHP_SWITCH_CORE_ARLA_SRCH_RSLT_1_ARLA_SRCH_RSLT_AGE_1_SHIFT 14
-#define BCHP_SWITCH_CORE_ARLA_SRCH_RSLT_1_ARLA_SRCH_RSLT_AGE_1_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: ARLA_SRCH_RSLT_1 :: ARLA_SRCH_RSLT_PRI_1 [13:11] */
-#define BCHP_SWITCH_CORE_ARLA_SRCH_RSLT_1_ARLA_SRCH_RSLT_PRI_1_MASK 0x00003800
-#define BCHP_SWITCH_CORE_ARLA_SRCH_RSLT_1_ARLA_SRCH_RSLT_PRI_1_SHIFT 11
-#define BCHP_SWITCH_CORE_ARLA_SRCH_RSLT_1_ARLA_SRCH_RSLT_PRI_1_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: ARLA_SRCH_RSLT_1 :: ARL_CON_1 [10:09] */
-#define BCHP_SWITCH_CORE_ARLA_SRCH_RSLT_1_ARL_CON_1_MASK 0x00000600
-#define BCHP_SWITCH_CORE_ARLA_SRCH_RSLT_1_ARL_CON_1_SHIFT 9
-#define BCHP_SWITCH_CORE_ARLA_SRCH_RSLT_1_ARL_CON_1_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: ARLA_SRCH_RSLT_1 :: PORTID_1 [08:00] */
-#define BCHP_SWITCH_CORE_ARLA_SRCH_RSLT_1_PORTID_1_MASK 0x000001ff
-#define BCHP_SWITCH_CORE_ARLA_SRCH_RSLT_1_PORTID_1_SHIFT 0
-#define BCHP_SWITCH_CORE_ARLA_SRCH_RSLT_1_PORTID_1_DEFAULT 0x00000000
-
-/***************************************************************************
- *ARLA_VTBL_RWCTRL - VTBL Read/Write/Clear Control Register
- ***************************************************************************/
-/* SWITCH_CORE :: ARLA_VTBL_RWCTRL :: reserved_for_padding0 [31:08] */
-#define BCHP_SWITCH_CORE_ARLA_VTBL_RWCTRL_reserved_for_padding0_MASK 0xffffff00
-#define BCHP_SWITCH_CORE_ARLA_VTBL_RWCTRL_reserved_for_padding0_SHIFT 8
-
-/* SWITCH_CORE :: ARLA_VTBL_RWCTRL :: ARLA_VTBL_STDN [07:07] */
-#define BCHP_SWITCH_CORE_ARLA_VTBL_RWCTRL_ARLA_VTBL_STDN_MASK 0x00000080
-#define BCHP_SWITCH_CORE_ARLA_VTBL_RWCTRL_ARLA_VTBL_STDN_SHIFT 7
-#define BCHP_SWITCH_CORE_ARLA_VTBL_RWCTRL_ARLA_VTBL_STDN_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: ARLA_VTBL_RWCTRL :: SWITCH_RESV [06:02] */
-#define BCHP_SWITCH_CORE_ARLA_VTBL_RWCTRL_SWITCH_RESV_MASK 0x0000007c
-#define BCHP_SWITCH_CORE_ARLA_VTBL_RWCTRL_SWITCH_RESV_SHIFT 2
-#define BCHP_SWITCH_CORE_ARLA_VTBL_RWCTRL_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: ARLA_VTBL_RWCTRL :: ARLA_VTBL_RW_CLR [01:00] */
-#define BCHP_SWITCH_CORE_ARLA_VTBL_RWCTRL_ARLA_VTBL_RW_CLR_MASK 0x00000003
-#define BCHP_SWITCH_CORE_ARLA_VTBL_RWCTRL_ARLA_VTBL_RW_CLR_SHIFT 0
-#define BCHP_SWITCH_CORE_ARLA_VTBL_RWCTRL_ARLA_VTBL_RW_CLR_DEFAULT 0x00000000
-
-/***************************************************************************
- *ARLA_VTBL_ADDR - VTBL Address Index Register
- ***************************************************************************/
-/* SWITCH_CORE :: ARLA_VTBL_ADDR :: reserved_for_padding0 [31:16] */
-#define BCHP_SWITCH_CORE_ARLA_VTBL_ADDR_reserved_for_padding0_MASK 0xffff0000
-#define BCHP_SWITCH_CORE_ARLA_VTBL_ADDR_reserved_for_padding0_SHIFT 16
-
-/* SWITCH_CORE :: ARLA_VTBL_ADDR :: SWITCH_RESV [15:12] */
-#define BCHP_SWITCH_CORE_ARLA_VTBL_ADDR_SWITCH_RESV_MASK 0x0000f000
-#define BCHP_SWITCH_CORE_ARLA_VTBL_ADDR_SWITCH_RESV_SHIFT 12
-#define BCHP_SWITCH_CORE_ARLA_VTBL_ADDR_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: ARLA_VTBL_ADDR :: VTBL_ADDR_INDEX [11:00] */
-#define BCHP_SWITCH_CORE_ARLA_VTBL_ADDR_VTBL_ADDR_INDEX_MASK 0x00000fff
-#define BCHP_SWITCH_CORE_ARLA_VTBL_ADDR_VTBL_ADDR_INDEX_SHIFT 0
-#define BCHP_SWITCH_CORE_ARLA_VTBL_ADDR_VTBL_ADDR_INDEX_DEFAULT 0x00000000
-
-/***************************************************************************
- *ARLA_VTBL_ENTRY - VTBL Entry Register
- ***************************************************************************/
-/* SWITCH_CORE :: ARLA_VTBL_ENTRY :: SWITCH_RESV [31:22] */
-#define BCHP_SWITCH_CORE_ARLA_VTBL_ENTRY_SWITCH_RESV_MASK 0xffc00000
-#define BCHP_SWITCH_CORE_ARLA_VTBL_ENTRY_SWITCH_RESV_SHIFT 22
-#define BCHP_SWITCH_CORE_ARLA_VTBL_ENTRY_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: ARLA_VTBL_ENTRY :: FWD_MODE [21:21] */
-#define BCHP_SWITCH_CORE_ARLA_VTBL_ENTRY_FWD_MODE_MASK 0x00200000
-#define BCHP_SWITCH_CORE_ARLA_VTBL_ENTRY_FWD_MODE_SHIFT 21
-#define BCHP_SWITCH_CORE_ARLA_VTBL_ENTRY_FWD_MODE_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: ARLA_VTBL_ENTRY :: MSPT_INDEX [20:18] */
-#define BCHP_SWITCH_CORE_ARLA_VTBL_ENTRY_MSPT_INDEX_MASK 0x001c0000
-#define BCHP_SWITCH_CORE_ARLA_VTBL_ENTRY_MSPT_INDEX_SHIFT 18
-#define BCHP_SWITCH_CORE_ARLA_VTBL_ENTRY_MSPT_INDEX_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: ARLA_VTBL_ENTRY :: UNTAG_MAP [17:09] */
-#define BCHP_SWITCH_CORE_ARLA_VTBL_ENTRY_UNTAG_MAP_MASK 0x0003fe00
-#define BCHP_SWITCH_CORE_ARLA_VTBL_ENTRY_UNTAG_MAP_SHIFT 9
-#define BCHP_SWITCH_CORE_ARLA_VTBL_ENTRY_UNTAG_MAP_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: ARLA_VTBL_ENTRY :: FWD_MAP [08:00] */
-#define BCHP_SWITCH_CORE_ARLA_VTBL_ENTRY_FWD_MAP_MASK 0x000001ff
-#define BCHP_SWITCH_CORE_ARLA_VTBL_ENTRY_FWD_MAP_SHIFT 0
-#define BCHP_SWITCH_CORE_ARLA_VTBL_ENTRY_FWD_MAP_DEFAULT 0x00000000
-
-/***************************************************************************
- *ARLACCS_REG_SPARE0 - Spare 0 Register (Not2Release)
- ***************************************************************************/
-/* SWITCH_CORE :: ARLACCS_REG_SPARE0 :: ARLACCS_REG_SPARE0 [31:00] */
-#define BCHP_SWITCH_CORE_ARLACCS_REG_SPARE0_ARLACCS_REG_SPARE0_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_ARLACCS_REG_SPARE0_ARLACCS_REG_SPARE0_SHIFT 0
-#define BCHP_SWITCH_CORE_ARLACCS_REG_SPARE0_ARLACCS_REG_SPARE0_DEFAULT 0x00000000
-
-/***************************************************************************
- *ARLACCS_REG_SPARE1 - Spare 1 Register (Not2Release)
- ***************************************************************************/
-/* SWITCH_CORE :: ARLACCS_REG_SPARE1 :: ARLACCS_REG_SPARE1 [31:00] */
-#define BCHP_SWITCH_CORE_ARLACCS_REG_SPARE1_ARLACCS_REG_SPARE1_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_ARLACCS_REG_SPARE1_ARLACCS_REG_SPARE1_SHIFT 0
-#define BCHP_SWITCH_CORE_ARLACCS_REG_SPARE1_ARLACCS_REG_SPARE1_DEFAULT 0x00000000
-
-/***************************************************************************
- *MEM_CTRL - Memory Debug Control RegisterNot2Release
- ***************************************************************************/
-/* SWITCH_CORE :: MEM_CTRL :: reserved_for_padding0 [31:08] */
-#define BCHP_SWITCH_CORE_MEM_CTRL_reserved_for_padding0_MASK 0xffffff00
-#define BCHP_SWITCH_CORE_MEM_CTRL_reserved_for_padding0_SHIFT 8
-
-/* SWITCH_CORE :: MEM_CTRL :: MEM_TYPE [07:06] */
-#define BCHP_SWITCH_CORE_MEM_CTRL_MEM_TYPE_MASK 0x000000c0
-#define BCHP_SWITCH_CORE_MEM_CTRL_MEM_TYPE_SHIFT 6
-#define BCHP_SWITCH_CORE_MEM_CTRL_MEM_TYPE_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: MEM_CTRL :: SWITCH_RESV_1 [05:04] */
-#define BCHP_SWITCH_CORE_MEM_CTRL_SWITCH_RESV_1_MASK 0x00000030
-#define BCHP_SWITCH_CORE_MEM_CTRL_SWITCH_RESV_1_SHIFT 4
-#define BCHP_SWITCH_CORE_MEM_CTRL_SWITCH_RESV_1_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: MEM_CTRL :: SWITCH_RESV_0 [03:00] */
-#define BCHP_SWITCH_CORE_MEM_CTRL_SWITCH_RESV_0_MASK 0x0000000f
-#define BCHP_SWITCH_CORE_MEM_CTRL_SWITCH_RESV_0_SHIFT 0
-#define BCHP_SWITCH_CORE_MEM_CTRL_SWITCH_RESV_0_DEFAULT 0x00000000
-
-/***************************************************************************
- *MEM_ADDR - Memory Debug Address RegisterNot2Release
- ***************************************************************************/
-/* SWITCH_CORE :: MEM_ADDR :: reserved_for_padding0 [31:16] */
-#define BCHP_SWITCH_CORE_MEM_ADDR_reserved_for_padding0_MASK 0xffff0000
-#define BCHP_SWITCH_CORE_MEM_ADDR_reserved_for_padding0_SHIFT 16
-
-/* SWITCH_CORE :: MEM_ADDR :: MEM_STDN [15:15] */
-#define BCHP_SWITCH_CORE_MEM_ADDR_MEM_STDN_MASK 0x00008000
-#define BCHP_SWITCH_CORE_MEM_ADDR_MEM_STDN_SHIFT 15
-#define BCHP_SWITCH_CORE_MEM_ADDR_MEM_STDN_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: MEM_ADDR :: MEM_RW [14:14] */
-#define BCHP_SWITCH_CORE_MEM_ADDR_MEM_RW_MASK 0x00004000
-#define BCHP_SWITCH_CORE_MEM_ADDR_MEM_RW_SHIFT 14
-#define BCHP_SWITCH_CORE_MEM_ADDR_MEM_RW_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: MEM_ADDR :: MEM_ADR [13:00] */
-#define BCHP_SWITCH_CORE_MEM_ADDR_MEM_ADR_MASK 0x00003fff
-#define BCHP_SWITCH_CORE_MEM_ADDR_MEM_ADR_SHIFT 0
-#define BCHP_SWITCH_CORE_MEM_ADDR_MEM_ADR_DEFAULT 0x00000000
-
-/***************************************************************************
- *MEM_DEBUG_DATA_0_0 - Memory Debug Data 0_0 RegisterNot2Release
- ***************************************************************************/
-/* SWITCH_CORE :: MEM_DEBUG_DATA_0_0 :: MEM_DAT [63:00] */
-#define BCHP_SWITCH_CORE_MEM_DEBUG_DATA_0_0_MEM_DAT_MASK 0x00000000ffffffff
-#define BCHP_SWITCH_CORE_MEM_DEBUG_DATA_0_0_MEM_DAT_SHIFT 0
-#define BCHP_SWITCH_CORE_MEM_DEBUG_DATA_0_0_MEM_DAT_DEFAULT 0x0000000000000000
-
-/***************************************************************************
- *MEM_DEBUG_DATA_0_1 - Memory Debug Data 0_1 RegisterNot2Release
- ***************************************************************************/
-/* SWITCH_CORE :: MEM_DEBUG_DATA_0_1 :: reserved_for_padding0 [31:16] */
-#define BCHP_SWITCH_CORE_MEM_DEBUG_DATA_0_1_reserved_for_padding0_MASK 0xffff0000
-#define BCHP_SWITCH_CORE_MEM_DEBUG_DATA_0_1_reserved_for_padding0_SHIFT 16
-
-/* SWITCH_CORE :: MEM_DEBUG_DATA_0_1 :: MEM_DAT [15:00] */
-#define BCHP_SWITCH_CORE_MEM_DEBUG_DATA_0_1_MEM_DAT_MASK 0x0000ffff
-#define BCHP_SWITCH_CORE_MEM_DEBUG_DATA_0_1_MEM_DAT_SHIFT 0
-#define BCHP_SWITCH_CORE_MEM_DEBUG_DATA_0_1_MEM_DAT_DEFAULT 0x00000000
-
-/***************************************************************************
- *MEM_DEBUG_DATA_1_0 - Memory Debug Data 1_0 RegisterNot2Release
- ***************************************************************************/
-/* SWITCH_CORE :: MEM_DEBUG_DATA_1_0 :: MEM_DAT [63:00] */
-#define BCHP_SWITCH_CORE_MEM_DEBUG_DATA_1_0_MEM_DAT_MASK 0x00000000ffffffff
-#define BCHP_SWITCH_CORE_MEM_DEBUG_DATA_1_0_MEM_DAT_SHIFT 0
-#define BCHP_SWITCH_CORE_MEM_DEBUG_DATA_1_0_MEM_DAT_DEFAULT 0x0000000000000000
-
-/***************************************************************************
- *MEM_DEBUG_DATA_1_1 - Memory Debug Data 1_1 RegisterNot2Release
- ***************************************************************************/
-/* SWITCH_CORE :: MEM_DEBUG_DATA_1_1 :: reserved_for_padding0 [31:16] */
-#define BCHP_SWITCH_CORE_MEM_DEBUG_DATA_1_1_reserved_for_padding0_MASK 0xffff0000
-#define BCHP_SWITCH_CORE_MEM_DEBUG_DATA_1_1_reserved_for_padding0_SHIFT 16
-
-/* SWITCH_CORE :: MEM_DEBUG_DATA_1_1 :: MEM_DAT [15:00] */
-#define BCHP_SWITCH_CORE_MEM_DEBUG_DATA_1_1_MEM_DAT_MASK 0x0000ffff
-#define BCHP_SWITCH_CORE_MEM_DEBUG_DATA_1_1_MEM_DAT_SHIFT 0
-#define BCHP_SWITCH_CORE_MEM_DEBUG_DATA_1_1_MEM_DAT_DEFAULT 0x00000000
-
-/***************************************************************************
- *MEM_FRM_ADDR - Frame Memory Address RegisterNot2Release
- ***************************************************************************/
-/* SWITCH_CORE :: MEM_FRM_ADDR :: reserved_for_padding0 [31:16] */
-#define BCHP_SWITCH_CORE_MEM_FRM_ADDR_reserved_for_padding0_MASK 0xffff0000
-#define BCHP_SWITCH_CORE_MEM_FRM_ADDR_reserved_for_padding0_SHIFT 16
-
-/* SWITCH_CORE :: MEM_FRM_ADDR :: MEM_STDN [15:15] */
-#define BCHP_SWITCH_CORE_MEM_FRM_ADDR_MEM_STDN_MASK 0x00008000
-#define BCHP_SWITCH_CORE_MEM_FRM_ADDR_MEM_STDN_SHIFT 15
-#define BCHP_SWITCH_CORE_MEM_FRM_ADDR_MEM_STDN_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: MEM_FRM_ADDR :: MEM_RW [14:14] */
-#define BCHP_SWITCH_CORE_MEM_FRM_ADDR_MEM_RW_MASK 0x00004000
-#define BCHP_SWITCH_CORE_MEM_FRM_ADDR_MEM_RW_SHIFT 14
-#define BCHP_SWITCH_CORE_MEM_FRM_ADDR_MEM_RW_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: MEM_FRM_ADDR :: MEM_ADR [13:00] */
-#define BCHP_SWITCH_CORE_MEM_FRM_ADDR_MEM_ADR_MASK 0x00003fff
-#define BCHP_SWITCH_CORE_MEM_FRM_ADDR_MEM_ADR_SHIFT 0
-#define BCHP_SWITCH_CORE_MEM_FRM_ADDR_MEM_ADR_DEFAULT 0x00000000
-
-/***************************************************************************
- *MEM_FRM_DATA0 - Frame Memory Data 1st RegisterNot2Release
- ***************************************************************************/
-/* SWITCH_CORE :: MEM_FRM_DATA0 :: MEM_DATA [63:00] */
-#define BCHP_SWITCH_CORE_MEM_FRM_DATA0_MEM_DATA_MASK 0x00000000ffffffff
-#define BCHP_SWITCH_CORE_MEM_FRM_DATA0_MEM_DATA_SHIFT 0
-#define BCHP_SWITCH_CORE_MEM_FRM_DATA0_MEM_DATA_DEFAULT 0x0000000000000000
-
-/***************************************************************************
- *MEM_FRM_DATA1 - Frame Memory Data 2st RegisterNot2Release
- ***************************************************************************/
-/* SWITCH_CORE :: MEM_FRM_DATA1 :: MEM_DATA [63:00] */
-#define BCHP_SWITCH_CORE_MEM_FRM_DATA1_MEM_DATA_MASK 0x00000000ffffffff
-#define BCHP_SWITCH_CORE_MEM_FRM_DATA1_MEM_DATA_SHIFT 0
-#define BCHP_SWITCH_CORE_MEM_FRM_DATA1_MEM_DATA_DEFAULT 0x0000000000000000
-
-/***************************************************************************
- *MEM_FRM_DATA2 - Frame Memory Data 3st RegisterNot2Release
- ***************************************************************************/
-/* SWITCH_CORE :: MEM_FRM_DATA2 :: MEM_DATA [63:00] */
-#define BCHP_SWITCH_CORE_MEM_FRM_DATA2_MEM_DATA_MASK 0x00000000ffffffff
-#define BCHP_SWITCH_CORE_MEM_FRM_DATA2_MEM_DATA_SHIFT 0
-#define BCHP_SWITCH_CORE_MEM_FRM_DATA2_MEM_DATA_DEFAULT 0x0000000000000000
-
-/***************************************************************************
- *MEM_FRM_DATA3 - Frame Memory Data 4th RegisterNot2Release
- ***************************************************************************/
-/* SWITCH_CORE :: MEM_FRM_DATA3 :: MEM_DATA [63:00] */
-#define BCHP_SWITCH_CORE_MEM_FRM_DATA3_MEM_DATA_MASK 0x00000000ffffffff
-#define BCHP_SWITCH_CORE_MEM_FRM_DATA3_MEM_DATA_SHIFT 0
-#define BCHP_SWITCH_CORE_MEM_FRM_DATA3_MEM_DATA_DEFAULT 0x0000000000000000
-
-/***************************************************************************
- *MEM_BTM_DATA0 - Buffer Tag Memory Register 0Not2Release
- ***************************************************************************/
-/* SWITCH_CORE :: MEM_BTM_DATA0 :: MEM_DATA [63:00] */
-#define BCHP_SWITCH_CORE_MEM_BTM_DATA0_MEM_DATA_MASK 0x00000000ffffffff
-#define BCHP_SWITCH_CORE_MEM_BTM_DATA0_MEM_DATA_SHIFT 0
-#define BCHP_SWITCH_CORE_MEM_BTM_DATA0_MEM_DATA_DEFAULT 0x0000000000000000
-
-/***************************************************************************
- *MEM_BTM_DATA1 - Buffer Tag Memory Register 1Not2Release
- ***************************************************************************/
-/* SWITCH_CORE :: MEM_BTM_DATA1 :: reserved_for_padding0 [31:16] */
-#define BCHP_SWITCH_CORE_MEM_BTM_DATA1_reserved_for_padding0_MASK 0xffff0000
-#define BCHP_SWITCH_CORE_MEM_BTM_DATA1_reserved_for_padding0_SHIFT 16
-
-/* SWITCH_CORE :: MEM_BTM_DATA1 :: MEM_DATA [15:00] */
-#define BCHP_SWITCH_CORE_MEM_BTM_DATA1_MEM_DATA_MASK 0x0000ffff
-#define BCHP_SWITCH_CORE_MEM_BTM_DATA1_MEM_DATA_SHIFT 0
-#define BCHP_SWITCH_CORE_MEM_BTM_DATA1_MEM_DATA_DEFAULT 0x00000000
-
-/***************************************************************************
- *MEM_BFC_ADDR - Buffer Control Memory Address RegisterNot2Release
- ***************************************************************************/
-/* SWITCH_CORE :: MEM_BFC_ADDR :: reserved_for_padding0 [31:16] */
-#define BCHP_SWITCH_CORE_MEM_BFC_ADDR_reserved_for_padding0_MASK 0xffff0000
-#define BCHP_SWITCH_CORE_MEM_BFC_ADDR_reserved_for_padding0_SHIFT 16
-
-/* SWITCH_CORE :: MEM_BFC_ADDR :: MEM_REQ [15:15] */
-#define BCHP_SWITCH_CORE_MEM_BFC_ADDR_MEM_REQ_MASK 0x00008000
-#define BCHP_SWITCH_CORE_MEM_BFC_ADDR_MEM_REQ_SHIFT 15
-#define BCHP_SWITCH_CORE_MEM_BFC_ADDR_MEM_REQ_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: MEM_BFC_ADDR :: RW_CTRL [14:14] */
-#define BCHP_SWITCH_CORE_MEM_BFC_ADDR_RW_CTRL_MASK 0x00004000
-#define BCHP_SWITCH_CORE_MEM_BFC_ADDR_RW_CTRL_SHIFT 14
-#define BCHP_SWITCH_CORE_MEM_BFC_ADDR_RW_CTRL_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: MEM_BFC_ADDR :: BFC_ADDR [13:00] */
-#define BCHP_SWITCH_CORE_MEM_BFC_ADDR_BFC_ADDR_MASK 0x00003fff
-#define BCHP_SWITCH_CORE_MEM_BFC_ADDR_BFC_ADDR_SHIFT 0
-#define BCHP_SWITCH_CORE_MEM_BFC_ADDR_BFC_ADDR_DEFAULT 0x00000000
-
-/***************************************************************************
- *MEM_BFC_DATA - Buffer Control Memory Data RegisterNot2Release
- ***************************************************************************/
-/* SWITCH_CORE :: MEM_BFC_DATA :: BFC_DATA [63:00] */
-#define BCHP_SWITCH_CORE_MEM_BFC_DATA_BFC_DATA_MASK 0x00000000ffffffff
-#define BCHP_SWITCH_CORE_MEM_BFC_DATA_BFC_DATA_SHIFT 0
-#define BCHP_SWITCH_CORE_MEM_BFC_DATA_BFC_DATA_DEFAULT 0x0000000000000000
-
-/***************************************************************************
- *PRS_FIFO_DEBUG_CTRL - PRS_FIFO Debug Control Register(Not2Release)Not2Release
- ***************************************************************************/
-/* SWITCH_CORE :: PRS_FIFO_DEBUG_CTRL :: reserved_for_padding0 [31:08] */
-#define BCHP_SWITCH_CORE_PRS_FIFO_DEBUG_CTRL_reserved_for_padding0_MASK 0xffffff00
-#define BCHP_SWITCH_CORE_PRS_FIFO_DEBUG_CTRL_reserved_for_padding0_SHIFT 8
-
-/* SWITCH_CORE :: PRS_FIFO_DEBUG_CTRL :: SWITCH_RESV [07:04] */
-#define BCHP_SWITCH_CORE_PRS_FIFO_DEBUG_CTRL_SWITCH_RESV_MASK 0x000000f0
-#define BCHP_SWITCH_CORE_PRS_FIFO_DEBUG_CTRL_SWITCH_RESV_SHIFT 4
-#define BCHP_SWITCH_CORE_PRS_FIFO_DEBUG_CTRL_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: PRS_FIFO_DEBUG_CTRL :: PRS_FIFO_DBG_CTRL [03:00] */
-#define BCHP_SWITCH_CORE_PRS_FIFO_DEBUG_CTRL_PRS_FIFO_DBG_CTRL_MASK 0x0000000f
-#define BCHP_SWITCH_CORE_PRS_FIFO_DEBUG_CTRL_PRS_FIFO_DBG_CTRL_SHIFT 0
-#define BCHP_SWITCH_CORE_PRS_FIFO_DEBUG_CTRL_PRS_FIFO_DBG_CTRL_DEFAULT 0x00000000
-
-/***************************************************************************
- *PRS_FIFO_DEBUG_DATA - PRS_FIFO Debug Data Register(Not2Release)Not2Release
- ***************************************************************************/
-/* SWITCH_CORE :: PRS_FIFO_DEBUG_DATA :: PRS_FIFO_DBG_DATA [63:00] */
-#define BCHP_SWITCH_CORE_PRS_FIFO_DEBUG_DATA_PRS_FIFO_DBG_DATA_MASK 0x00000000ffffffff
-#define BCHP_SWITCH_CORE_PRS_FIFO_DEBUG_DATA_PRS_FIFO_DBG_DATA_SHIFT 0
-#define BCHP_SWITCH_CORE_PRS_FIFO_DEBUG_DATA_PRS_FIFO_DBG_DATA_DEFAULT 0x0000000000000000
-
-/***************************************************************************
- *MEM_REG_SPARE0 - Spare 0 Register (Not2Release)Not2Release
- ***************************************************************************/
-/* SWITCH_CORE :: MEM_REG_SPARE0 :: MEM_REG_SPARE0 [31:00] */
-#define BCHP_SWITCH_CORE_MEM_REG_SPARE0_MEM_REG_SPARE0_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_MEM_REG_SPARE0_MEM_REG_SPARE0_SHIFT 0
-#define BCHP_SWITCH_CORE_MEM_REG_SPARE0_MEM_REG_SPARE0_DEFAULT 0x00000000
-
-/***************************************************************************
- *MEM_REG_SPARE1 - Spare 1 Register (Not2Release)Not2Release
- ***************************************************************************/
-/* SWITCH_CORE :: MEM_REG_SPARE1 :: MEM_REG_SPARE1 [31:00] */
-#define BCHP_SWITCH_CORE_MEM_REG_SPARE1_MEM_REG_SPARE1_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_MEM_REG_SPARE1_MEM_REG_SPARE1_SHIFT 0
-#define BCHP_SWITCH_CORE_MEM_REG_SPARE1_MEM_REG_SPARE1_DEFAULT 0x00000000
-
-/***************************************************************************
- *MEM_MISC_CTRL - Memory Misc Control RegisterNot2Release
- ***************************************************************************/
-/* SWITCH_CORE :: MEM_MISC_CTRL :: SWITCH_RESV [31:05] */
-#define BCHP_SWITCH_CORE_MEM_MISC_CTRL_SWITCH_RESV_MASK 0xffffffe0
-#define BCHP_SWITCH_CORE_MEM_MISC_CTRL_SWITCH_RESV_SHIFT 5
-#define BCHP_SWITCH_CORE_MEM_MISC_CTRL_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: MEM_MISC_CTRL :: TXQ_DCM [04:04] */
-#define BCHP_SWITCH_CORE_MEM_MISC_CTRL_TXQ_DCM_MASK 0x00000010
-#define BCHP_SWITCH_CORE_MEM_MISC_CTRL_TXQ_DCM_SHIFT 4
-#define BCHP_SWITCH_CORE_MEM_MISC_CTRL_TXQ_DCM_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: MEM_MISC_CTRL :: PB_DCM [03:03] */
-#define BCHP_SWITCH_CORE_MEM_MISC_CTRL_PB_DCM_MASK 0x00000008
-#define BCHP_SWITCH_CORE_MEM_MISC_CTRL_PB_DCM_SHIFT 3
-#define BCHP_SWITCH_CORE_MEM_MISC_CTRL_PB_DCM_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: MEM_MISC_CTRL :: BT_DCM [02:02] */
-#define BCHP_SWITCH_CORE_MEM_MISC_CTRL_BT_DCM_MASK 0x00000004
-#define BCHP_SWITCH_CORE_MEM_MISC_CTRL_BT_DCM_SHIFT 2
-#define BCHP_SWITCH_CORE_MEM_MISC_CTRL_BT_DCM_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: MEM_MISC_CTRL :: ARL_DCM [01:01] */
-#define BCHP_SWITCH_CORE_MEM_MISC_CTRL_ARL_DCM_MASK 0x00000002
-#define BCHP_SWITCH_CORE_MEM_MISC_CTRL_ARL_DCM_SHIFT 1
-#define BCHP_SWITCH_CORE_MEM_MISC_CTRL_ARL_DCM_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: MEM_MISC_CTRL :: CK_AON [00:00] */
-#define BCHP_SWITCH_CORE_MEM_MISC_CTRL_CK_AON_MASK 0x00000001
-#define BCHP_SWITCH_CORE_MEM_MISC_CTRL_CK_AON_SHIFT 0
-#define BCHP_SWITCH_CORE_MEM_MISC_CTRL_CK_AON_DEFAULT 0x00000001
-
-/***************************************************************************
- *MEM_TEST_CTRL0 - Memory Test Control 0 RegisterNot2Release
- ***************************************************************************/
-/* SWITCH_CORE :: MEM_TEST_CTRL0 :: SWITCH_RESV_1 [31:30] */
-#define BCHP_SWITCH_CORE_MEM_TEST_CTRL0_SWITCH_RESV_1_MASK 0xc0000000
-#define BCHP_SWITCH_CORE_MEM_TEST_CTRL0_SWITCH_RESV_1_SHIFT 30
-#define BCHP_SWITCH_CORE_MEM_TEST_CTRL0_SWITCH_RESV_1_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: MEM_TEST_CTRL0 :: VL_TM [29:20] */
-#define BCHP_SWITCH_CORE_MEM_TEST_CTRL0_VL_TM_MASK 0x3ff00000
-#define BCHP_SWITCH_CORE_MEM_TEST_CTRL0_VL_TM_SHIFT 20
-#define BCHP_SWITCH_CORE_MEM_TEST_CTRL0_VL_TM_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: MEM_TEST_CTRL0 :: SWITCH_RESV_0 [19:17] */
-#define BCHP_SWITCH_CORE_MEM_TEST_CTRL0_SWITCH_RESV_0_MASK 0x000e0000
-#define BCHP_SWITCH_CORE_MEM_TEST_CTRL0_SWITCH_RESV_0_SHIFT 17
-#define BCHP_SWITCH_CORE_MEM_TEST_CTRL0_SWITCH_RESV_0_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: MEM_TEST_CTRL0 :: ARL_TM [16:00] */
-#define BCHP_SWITCH_CORE_MEM_TEST_CTRL0_ARL_TM_MASK 0x0001ffff
-#define BCHP_SWITCH_CORE_MEM_TEST_CTRL0_ARL_TM_SHIFT 0
-#define BCHP_SWITCH_CORE_MEM_TEST_CTRL0_ARL_TM_DEFAULT 0x00000000
-
-/***************************************************************************
- *MEM_TEST_CTRL1 - Memory Test Control 1 RegisterNot2Release
- ***************************************************************************/
-/* SWITCH_CORE :: MEM_TEST_CTRL1 :: SWITCH_RESV_1 [31:30] */
-#define BCHP_SWITCH_CORE_MEM_TEST_CTRL1_SWITCH_RESV_1_MASK 0xc0000000
-#define BCHP_SWITCH_CORE_MEM_TEST_CTRL1_SWITCH_RESV_1_SHIFT 30
-#define BCHP_SWITCH_CORE_MEM_TEST_CTRL1_SWITCH_RESV_1_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: MEM_TEST_CTRL1 :: ACTRAT_TM [29:20] */
-#define BCHP_SWITCH_CORE_MEM_TEST_CTRL1_ACTRAT_TM_MASK 0x3ff00000
-#define BCHP_SWITCH_CORE_MEM_TEST_CTRL1_ACTRAT_TM_SHIFT 20
-#define BCHP_SWITCH_CORE_MEM_TEST_CTRL1_ACTRAT_TM_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: MEM_TEST_CTRL1 :: SWITCH_RESV_0 [19:17] */
-#define BCHP_SWITCH_CORE_MEM_TEST_CTRL1_SWITCH_RESV_0_MASK 0x000e0000
-#define BCHP_SWITCH_CORE_MEM_TEST_CTRL1_SWITCH_RESV_0_SHIFT 17
-#define BCHP_SWITCH_CORE_MEM_TEST_CTRL1_SWITCH_RESV_0_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: MEM_TEST_CTRL1 :: BT_TM [16:00] */
-#define BCHP_SWITCH_CORE_MEM_TEST_CTRL1_BT_TM_MASK 0x0001ffff
-#define BCHP_SWITCH_CORE_MEM_TEST_CTRL1_BT_TM_SHIFT 0
-#define BCHP_SWITCH_CORE_MEM_TEST_CTRL1_BT_TM_DEFAULT 0x00000000
-
-/***************************************************************************
- *MEM_TEST_CTRL2 - Memory Test Control 2 RegisterNot2Release
- ***************************************************************************/
-/* SWITCH_CORE :: MEM_TEST_CTRL2 :: SWITCH_RESV_1 [31:30] */
-#define BCHP_SWITCH_CORE_MEM_TEST_CTRL2_SWITCH_RESV_1_MASK 0xc0000000
-#define BCHP_SWITCH_CORE_MEM_TEST_CTRL2_SWITCH_RESV_1_SHIFT 30
-#define BCHP_SWITCH_CORE_MEM_TEST_CTRL2_SWITCH_RESV_1_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: MEM_TEST_CTRL2 :: STS_TM [29:20] */
-#define BCHP_SWITCH_CORE_MEM_TEST_CTRL2_STS_TM_MASK 0x3ff00000
-#define BCHP_SWITCH_CORE_MEM_TEST_CTRL2_STS_TM_SHIFT 20
-#define BCHP_SWITCH_CORE_MEM_TEST_CTRL2_STS_TM_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: MEM_TEST_CTRL2 :: SWITCH_RESV_0 [19:17] */
-#define BCHP_SWITCH_CORE_MEM_TEST_CTRL2_SWITCH_RESV_0_MASK 0x000e0000
-#define BCHP_SWITCH_CORE_MEM_TEST_CTRL2_SWITCH_RESV_0_SHIFT 17
-#define BCHP_SWITCH_CORE_MEM_TEST_CTRL2_SWITCH_RESV_0_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: MEM_TEST_CTRL2 :: PB_TM [16:00] */
-#define BCHP_SWITCH_CORE_MEM_TEST_CTRL2_PB_TM_MASK 0x0001ffff
-#define BCHP_SWITCH_CORE_MEM_TEST_CTRL2_PB_TM_SHIFT 0
-#define BCHP_SWITCH_CORE_MEM_TEST_CTRL2_PB_TM_DEFAULT 0x00000000
-
-/***************************************************************************
- *MEM_TEST_CTRL3 - Memory Test Control 3 RegisterNot2Release
- ***************************************************************************/
-/* SWITCH_CORE :: MEM_TEST_CTRL3 :: SWITCH_RESV_1 [31:30] */
-#define BCHP_SWITCH_CORE_MEM_TEST_CTRL3_SWITCH_RESV_1_MASK 0xc0000000
-#define BCHP_SWITCH_CORE_MEM_TEST_CTRL3_SWITCH_RESV_1_SHIFT 30
-#define BCHP_SWITCH_CORE_MEM_TEST_CTRL3_SWITCH_RESV_1_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: MEM_TEST_CTRL3 :: EVT_TM [29:20] */
-#define BCHP_SWITCH_CORE_MEM_TEST_CTRL3_EVT_TM_MASK 0x3ff00000
-#define BCHP_SWITCH_CORE_MEM_TEST_CTRL3_EVT_TM_SHIFT 20
-#define BCHP_SWITCH_CORE_MEM_TEST_CTRL3_EVT_TM_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: MEM_TEST_CTRL3 :: SWITCH_RESV_0 [19:17] */
-#define BCHP_SWITCH_CORE_MEM_TEST_CTRL3_SWITCH_RESV_0_MASK 0x000e0000
-#define BCHP_SWITCH_CORE_MEM_TEST_CTRL3_SWITCH_RESV_0_SHIFT 17
-#define BCHP_SWITCH_CORE_MEM_TEST_CTRL3_SWITCH_RESV_0_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: MEM_TEST_CTRL3 :: TXQ_TM [16:00] */
-#define BCHP_SWITCH_CORE_MEM_TEST_CTRL3_TXQ_TM_MASK 0x0001ffff
-#define BCHP_SWITCH_CORE_MEM_TEST_CTRL3_TXQ_TM_SHIFT 0
-#define BCHP_SWITCH_CORE_MEM_TEST_CTRL3_TXQ_TM_DEFAULT 0x00000000
-
-/***************************************************************************
- *MEM_TEST_CTRL4 - Memory Test Control 4 RegisterNot2Release
- ***************************************************************************/
-/* SWITCH_CORE :: MEM_TEST_CTRL4 :: SWITCH_RESV_1 [31:26] */
-#define BCHP_SWITCH_CORE_MEM_TEST_CTRL4_SWITCH_RESV_1_MASK 0xfc000000
-#define BCHP_SWITCH_CORE_MEM_TEST_CTRL4_SWITCH_RESV_1_SHIFT 26
-#define BCHP_SWITCH_CORE_MEM_TEST_CTRL4_SWITCH_RESV_1_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: MEM_TEST_CTRL4 :: TCAM_CHKSUM_TM [25:16] */
-#define BCHP_SWITCH_CORE_MEM_TEST_CTRL4_TCAM_CHKSUM_TM_MASK 0x03ff0000
-#define BCHP_SWITCH_CORE_MEM_TEST_CTRL4_TCAM_CHKSUM_TM_SHIFT 16
-#define BCHP_SWITCH_CORE_MEM_TEST_CTRL4_TCAM_CHKSUM_TM_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: MEM_TEST_CTRL4 :: SWITCH_RESV_0 [15:14] */
-#define BCHP_SWITCH_CORE_MEM_TEST_CTRL4_SWITCH_RESV_0_MASK 0x0000c000
-#define BCHP_SWITCH_CORE_MEM_TEST_CTRL4_SWITCH_RESV_0_SHIFT 14
-#define BCHP_SWITCH_CORE_MEM_TEST_CTRL4_SWITCH_RESV_0_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: MEM_TEST_CTRL4 :: TCAM_TM [13:00] */
-#define BCHP_SWITCH_CORE_MEM_TEST_CTRL4_TCAM_TM_MASK 0x00003fff
-#define BCHP_SWITCH_CORE_MEM_TEST_CTRL4_TCAM_TM_SHIFT 0
-#define BCHP_SWITCH_CORE_MEM_TEST_CTRL4_TCAM_TM_DEFAULT 0x00000000
-
-/***************************************************************************
- *MEM_TEST_CTRL5 - Memory Test Control 5 RegisterNot2Release
- ***************************************************************************/
-/* SWITCH_CORE :: MEM_TEST_CTRL5 :: SWITCH_RESV [31:06] */
-#define BCHP_SWITCH_CORE_MEM_TEST_CTRL5_SWITCH_RESV_MASK 0xffffffc0
-#define BCHP_SWITCH_CORE_MEM_TEST_CTRL5_SWITCH_RESV_SHIFT 6
-#define BCHP_SWITCH_CORE_MEM_TEST_CTRL5_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: MEM_TEST_CTRL5 :: MIB_TM [05:00] */
-#define BCHP_SWITCH_CORE_MEM_TEST_CTRL5_MIB_TM_MASK 0x0000003f
-#define BCHP_SWITCH_CORE_MEM_TEST_CTRL5_MIB_TM_SHIFT 0
-#define BCHP_SWITCH_CORE_MEM_TEST_CTRL5_MIB_TM_DEFAULT 0x00000000
-
-/***************************************************************************
- *MEM_PSM_VDD_CTRL - Memory PSM_VDD Pin Control registerNot2Release
- ***************************************************************************/
-/* SWITCH_CORE :: MEM_PSM_VDD_CTRL :: SWITCH_RESV [31:22] */
-#define BCHP_SWITCH_CORE_MEM_PSM_VDD_CTRL_SWITCH_RESV_MASK 0xffc00000
-#define BCHP_SWITCH_CORE_MEM_PSM_VDD_CTRL_SWITCH_RESV_SHIFT 22
-#define BCHP_SWITCH_CORE_MEM_PSM_VDD_CTRL_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: MEM_PSM_VDD_CTRL :: STS_PSM_VDD [21:20] */
-#define BCHP_SWITCH_CORE_MEM_PSM_VDD_CTRL_STS_PSM_VDD_MASK 0x00300000
-#define BCHP_SWITCH_CORE_MEM_PSM_VDD_CTRL_STS_PSM_VDD_SHIFT 20
-#define BCHP_SWITCH_CORE_MEM_PSM_VDD_CTRL_STS_PSM_VDD_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: MEM_PSM_VDD_CTRL :: ACTRAT_PSM_VDD [19:18] */
-#define BCHP_SWITCH_CORE_MEM_PSM_VDD_CTRL_ACTRAT_PSM_VDD_MASK 0x000c0000
-#define BCHP_SWITCH_CORE_MEM_PSM_VDD_CTRL_ACTRAT_PSM_VDD_SHIFT 18
-#define BCHP_SWITCH_CORE_MEM_PSM_VDD_CTRL_ACTRAT_PSM_VDD_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: MEM_PSM_VDD_CTRL :: IMP_TXQ_PSM_VDD [17:16] */
-#define BCHP_SWITCH_CORE_MEM_PSM_VDD_CTRL_IMP_TXQ_PSM_VDD_MASK 0x00030000
-#define BCHP_SWITCH_CORE_MEM_PSM_VDD_CTRL_IMP_TXQ_PSM_VDD_SHIFT 16
-#define BCHP_SWITCH_CORE_MEM_PSM_VDD_CTRL_IMP_TXQ_PSM_VDD_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: MEM_PSM_VDD_CTRL :: P7_TXQ_PSM_VDD [15:14] */
-#define BCHP_SWITCH_CORE_MEM_PSM_VDD_CTRL_P7_TXQ_PSM_VDD_MASK 0x0000c000
-#define BCHP_SWITCH_CORE_MEM_PSM_VDD_CTRL_P7_TXQ_PSM_VDD_SHIFT 14
-#define BCHP_SWITCH_CORE_MEM_PSM_VDD_CTRL_P7_TXQ_PSM_VDD_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: MEM_PSM_VDD_CTRL :: P6_TXQ_PSM_VDD [13:12] */
-#define BCHP_SWITCH_CORE_MEM_PSM_VDD_CTRL_P6_TXQ_PSM_VDD_MASK 0x00003000
-#define BCHP_SWITCH_CORE_MEM_PSM_VDD_CTRL_P6_TXQ_PSM_VDD_SHIFT 12
-#define BCHP_SWITCH_CORE_MEM_PSM_VDD_CTRL_P6_TXQ_PSM_VDD_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: MEM_PSM_VDD_CTRL :: P5_TXQ_PSM_VDD [11:10] */
-#define BCHP_SWITCH_CORE_MEM_PSM_VDD_CTRL_P5_TXQ_PSM_VDD_MASK 0x00000c00
-#define BCHP_SWITCH_CORE_MEM_PSM_VDD_CTRL_P5_TXQ_PSM_VDD_SHIFT 10
-#define BCHP_SWITCH_CORE_MEM_PSM_VDD_CTRL_P5_TXQ_PSM_VDD_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: MEM_PSM_VDD_CTRL :: P4_TXQ_PSM_VDD [09:08] */
-#define BCHP_SWITCH_CORE_MEM_PSM_VDD_CTRL_P4_TXQ_PSM_VDD_MASK 0x00000300
-#define BCHP_SWITCH_CORE_MEM_PSM_VDD_CTRL_P4_TXQ_PSM_VDD_SHIFT 8
-#define BCHP_SWITCH_CORE_MEM_PSM_VDD_CTRL_P4_TXQ_PSM_VDD_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: MEM_PSM_VDD_CTRL :: P3_TXQ_PSM_VDD [07:06] */
-#define BCHP_SWITCH_CORE_MEM_PSM_VDD_CTRL_P3_TXQ_PSM_VDD_MASK 0x000000c0
-#define BCHP_SWITCH_CORE_MEM_PSM_VDD_CTRL_P3_TXQ_PSM_VDD_SHIFT 6
-#define BCHP_SWITCH_CORE_MEM_PSM_VDD_CTRL_P3_TXQ_PSM_VDD_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: MEM_PSM_VDD_CTRL :: P2_TXQ_PSM_VDD [05:04] */
-#define BCHP_SWITCH_CORE_MEM_PSM_VDD_CTRL_P2_TXQ_PSM_VDD_MASK 0x00000030
-#define BCHP_SWITCH_CORE_MEM_PSM_VDD_CTRL_P2_TXQ_PSM_VDD_SHIFT 4
-#define BCHP_SWITCH_CORE_MEM_PSM_VDD_CTRL_P2_TXQ_PSM_VDD_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: MEM_PSM_VDD_CTRL :: P1_TXQ_PSM_VDD [03:02] */
-#define BCHP_SWITCH_CORE_MEM_PSM_VDD_CTRL_P1_TXQ_PSM_VDD_MASK 0x0000000c
-#define BCHP_SWITCH_CORE_MEM_PSM_VDD_CTRL_P1_TXQ_PSM_VDD_SHIFT 2
-#define BCHP_SWITCH_CORE_MEM_PSM_VDD_CTRL_P1_TXQ_PSM_VDD_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: MEM_PSM_VDD_CTRL :: P0_TXQ_PSM_VDD [01:00] */
-#define BCHP_SWITCH_CORE_MEM_PSM_VDD_CTRL_P0_TXQ_PSM_VDD_MASK 0x00000003
-#define BCHP_SWITCH_CORE_MEM_PSM_VDD_CTRL_P0_TXQ_PSM_VDD_SHIFT 0
-#define BCHP_SWITCH_CORE_MEM_PSM_VDD_CTRL_P0_TXQ_PSM_VDD_DEFAULT 0x00000000
-
-/***************************************************************************
- *PORT0_DEBUG - PORT0 DEBUGNot2Release
- ***************************************************************************/
-/* SWITCH_CORE :: PORT0_DEBUG :: SWITCH_RESV [31:00] */
-#define BCHP_SWITCH_CORE_PORT0_DEBUG_SWITCH_RESV_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_PORT0_DEBUG_SWITCH_RESV_SHIFT 0
-#define BCHP_SWITCH_CORE_PORT0_DEBUG_SWITCH_RESV_DEFAULT 0x00000000
-
-/***************************************************************************
- *PORT1_DEBUG - PORT1 DEBUGNot2Release
- ***************************************************************************/
-/* SWITCH_CORE :: PORT1_DEBUG :: SWITCH_RESV [31:00] */
-#define BCHP_SWITCH_CORE_PORT1_DEBUG_SWITCH_RESV_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_PORT1_DEBUG_SWITCH_RESV_SHIFT 0
-#define BCHP_SWITCH_CORE_PORT1_DEBUG_SWITCH_RESV_DEFAULT 0x00000000
-
-/***************************************************************************
- *PORT2_DEBUG - PORT2 DEBUGNot2Release
- ***************************************************************************/
-/* SWITCH_CORE :: PORT2_DEBUG :: SWITCH_RESV [31:00] */
-#define BCHP_SWITCH_CORE_PORT2_DEBUG_SWITCH_RESV_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_PORT2_DEBUG_SWITCH_RESV_SHIFT 0
-#define BCHP_SWITCH_CORE_PORT2_DEBUG_SWITCH_RESV_DEFAULT 0x00000000
-
-/***************************************************************************
- *PORT3_DEBUG - PORT3 DEBUGNot2Release
- ***************************************************************************/
-/* SWITCH_CORE :: PORT3_DEBUG :: SWITCH_RESV [31:00] */
-#define BCHP_SWITCH_CORE_PORT3_DEBUG_SWITCH_RESV_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_PORT3_DEBUG_SWITCH_RESV_SHIFT 0
-#define BCHP_SWITCH_CORE_PORT3_DEBUG_SWITCH_RESV_DEFAULT 0x00000000
-
-/***************************************************************************
- *PORT4_DEBUG - PORT4 DEBUGNot2Release
- ***************************************************************************/
-/* SWITCH_CORE :: PORT4_DEBUG :: SWITCH_RESV [31:00] */
-#define BCHP_SWITCH_CORE_PORT4_DEBUG_SWITCH_RESV_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_PORT4_DEBUG_SWITCH_RESV_SHIFT 0
-#define BCHP_SWITCH_CORE_PORT4_DEBUG_SWITCH_RESV_DEFAULT 0x00000000
-
-/***************************************************************************
- *PORT5_DEBUG - PORT5 DEBUGNot2Release
- ***************************************************************************/
-/* SWITCH_CORE :: PORT5_DEBUG :: SWITCH_RESV [31:00] */
-#define BCHP_SWITCH_CORE_PORT5_DEBUG_SWITCH_RESV_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_PORT5_DEBUG_SWITCH_RESV_SHIFT 0
-#define BCHP_SWITCH_CORE_PORT5_DEBUG_SWITCH_RESV_DEFAULT 0x00000000
-
-/***************************************************************************
- *PORT6_DEBUG - PORT6 DEBUGNot2Release
- ***************************************************************************/
-/* SWITCH_CORE :: PORT6_DEBUG :: SWITCH_RESV [31:00] */
-#define BCHP_SWITCH_CORE_PORT6_DEBUG_SWITCH_RESV_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_PORT6_DEBUG_SWITCH_RESV_SHIFT 0
-#define BCHP_SWITCH_CORE_PORT6_DEBUG_SWITCH_RESV_DEFAULT 0x00000000
-
-/***************************************************************************
- *PORT7_DEBUG - PORT7 DEBUGNot2Release
- ***************************************************************************/
-/* SWITCH_CORE :: PORT7_DEBUG :: SWITCH_RESV [31:00] */
-#define BCHP_SWITCH_CORE_PORT7_DEBUG_SWITCH_RESV_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_PORT7_DEBUG_SWITCH_RESV_SHIFT 0
-#define BCHP_SWITCH_CORE_PORT7_DEBUG_SWITCH_RESV_DEFAULT 0x00000000
-
-/***************************************************************************
- *PORT8_DEBUG - PORT8 DEBUGNot2Release
- ***************************************************************************/
-/* SWITCH_CORE :: PORT8_DEBUG :: SWITCH_RESV [31:00] */
-#define BCHP_SWITCH_CORE_PORT8_DEBUG_SWITCH_RESV_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_PORT8_DEBUG_SWITCH_RESV_SHIFT 0
-#define BCHP_SWITCH_CORE_PORT8_DEBUG_SWITCH_RESV_DEFAULT 0x00000000
-
-/***************************************************************************
- *FC_DIAG_CTRL - Flowcon Diagnosis Control RegisterNot2Release
- ***************************************************************************/
-/* SWITCH_CORE :: FC_DIAG_CTRL :: reserved_for_padding0 [31:16] */
-#define BCHP_SWITCH_CORE_FC_DIAG_CTRL_reserved_for_padding0_MASK 0xffff0000
-#define BCHP_SWITCH_CORE_FC_DIAG_CTRL_reserved_for_padding0_SHIFT 16
-
-/* SWITCH_CORE :: FC_DIAG_CTRL :: SWITCH_RESV [15:04] */
-#define BCHP_SWITCH_CORE_FC_DIAG_CTRL_SWITCH_RESV_MASK 0x0000fff0
-#define BCHP_SWITCH_CORE_FC_DIAG_CTRL_SWITCH_RESV_SHIFT 4
-#define BCHP_SWITCH_CORE_FC_DIAG_CTRL_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: FC_DIAG_CTRL :: DIAG_FLOWCON_PORT [03:00] */
-#define BCHP_SWITCH_CORE_FC_DIAG_CTRL_DIAG_FLOWCON_PORT_MASK 0x0000000f
-#define BCHP_SWITCH_CORE_FC_DIAG_CTRL_DIAG_FLOWCON_PORT_SHIFT 0
-#define BCHP_SWITCH_CORE_FC_DIAG_CTRL_DIAG_FLOWCON_PORT_DEFAULT 0x00000000
-
-/***************************************************************************
- *FC_CTRL_MODE - Flow Control Mode Selection RegisterNot2Release
- ***************************************************************************/
-/* SWITCH_CORE :: FC_CTRL_MODE :: reserved_for_padding0 [31:08] */
-#define BCHP_SWITCH_CORE_FC_CTRL_MODE_reserved_for_padding0_MASK 0xffffff00
-#define BCHP_SWITCH_CORE_FC_CTRL_MODE_reserved_for_padding0_SHIFT 8
-
-/* SWITCH_CORE :: FC_CTRL_MODE :: SWITCH_RESV [07:01] */
-#define BCHP_SWITCH_CORE_FC_CTRL_MODE_SWITCH_RESV_MASK 0x000000fe
-#define BCHP_SWITCH_CORE_FC_CTRL_MODE_SWITCH_RESV_SHIFT 1
-#define BCHP_SWITCH_CORE_FC_CTRL_MODE_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: FC_CTRL_MODE :: FC_MODE [00:00] */
-#define BCHP_SWITCH_CORE_FC_CTRL_MODE_FC_MODE_MASK 0x00000001
-#define BCHP_SWITCH_CORE_FC_CTRL_MODE_FC_MODE_SHIFT 0
-#define BCHP_SWITCH_CORE_FC_CTRL_MODE_FC_MODE_DEFAULT 0x00000000
-
-/***************************************************************************
- *FC_CTRL_PORT - Flow Control Port Selection RegisterNot2Release
- ***************************************************************************/
-/* SWITCH_CORE :: FC_CTRL_PORT :: reserved_for_padding0 [31:08] */
-#define BCHP_SWITCH_CORE_FC_CTRL_PORT_reserved_for_padding0_MASK 0xffffff00
-#define BCHP_SWITCH_CORE_FC_CTRL_PORT_reserved_for_padding0_SHIFT 8
-
-/* SWITCH_CORE :: FC_CTRL_PORT :: SWITCH_RESV [07:04] */
-#define BCHP_SWITCH_CORE_FC_CTRL_PORT_SWITCH_RESV_MASK 0x000000f0
-#define BCHP_SWITCH_CORE_FC_CTRL_PORT_SWITCH_RESV_SHIFT 4
-#define BCHP_SWITCH_CORE_FC_CTRL_PORT_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: FC_CTRL_PORT :: FC_PORT_SEL [03:00] */
-#define BCHP_SWITCH_CORE_FC_CTRL_PORT_FC_PORT_SEL_MASK 0x0000000f
-#define BCHP_SWITCH_CORE_FC_CTRL_PORT_FC_PORT_SEL_SHIFT 0
-#define BCHP_SWITCH_CORE_FC_CTRL_PORT_FC_PORT_SEL_DEFAULT 0x00000000
-
-/***************************************************************************
- *FC_OOB_PAUSE_EN - OOB Pause Signal Enable Register (Release2Customer)Not2Release
- ***************************************************************************/
-/* SWITCH_CORE :: FC_OOB_PAUSE_EN :: reserved_for_padding0 [31:16] */
-#define BCHP_SWITCH_CORE_FC_OOB_PAUSE_EN_reserved_for_padding0_MASK 0xffff0000
-#define BCHP_SWITCH_CORE_FC_OOB_PAUSE_EN_reserved_for_padding0_SHIFT 16
-
-/* SWITCH_CORE :: FC_OOB_PAUSE_EN :: SWITCH_RESV [15:09] */
-#define BCHP_SWITCH_CORE_FC_OOB_PAUSE_EN_SWITCH_RESV_MASK 0x0000fe00
-#define BCHP_SWITCH_CORE_FC_OOB_PAUSE_EN_SWITCH_RESV_SHIFT 9
-#define BCHP_SWITCH_CORE_FC_OOB_PAUSE_EN_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: FC_OOB_PAUSE_EN :: OOB_PAUSE_EN [08:00] */
-#define BCHP_SWITCH_CORE_FC_OOB_PAUSE_EN_OOB_PAUSE_EN_MASK 0x000001ff
-#define BCHP_SWITCH_CORE_FC_OOB_PAUSE_EN_OOB_PAUSE_EN_SHIFT 0
-#define BCHP_SWITCH_CORE_FC_OOB_PAUSE_EN_OOB_PAUSE_EN_DEFAULT 0x00000000
-
-/***************************************************************************
- *PAUSE_TIME_MAX - MAX Quantum Pause Time RegisterNot2Release
- ***************************************************************************/
-/* SWITCH_CORE :: PAUSE_TIME_MAX :: reserved_for_padding0 [31:16] */
-#define BCHP_SWITCH_CORE_PAUSE_TIME_MAX_reserved_for_padding0_MASK 0xffff0000
-#define BCHP_SWITCH_CORE_PAUSE_TIME_MAX_reserved_for_padding0_SHIFT 16
-
-/* SWITCH_CORE :: PAUSE_TIME_MAX :: PAUSE_TIME_MAX [15:00] */
-#define BCHP_SWITCH_CORE_PAUSE_TIME_MAX_PAUSE_TIME_MAX_MASK 0x0000ffff
-#define BCHP_SWITCH_CORE_PAUSE_TIME_MAX_PAUSE_TIME_MAX_SHIFT 0
-#define BCHP_SWITCH_CORE_PAUSE_TIME_MAX_PAUSE_TIME_MAX_DEFAULT 0x00008000
-
-/***************************************************************************
- *PAUSE_TIME_MIN - MIN Quantum Pause Time RegisterNot2Release
- ***************************************************************************/
-/* SWITCH_CORE :: PAUSE_TIME_MIN :: reserved_for_padding0 [31:16] */
-#define BCHP_SWITCH_CORE_PAUSE_TIME_MIN_reserved_for_padding0_MASK 0xffff0000
-#define BCHP_SWITCH_CORE_PAUSE_TIME_MIN_reserved_for_padding0_SHIFT 16
-
-/* SWITCH_CORE :: PAUSE_TIME_MIN :: PAUSE_TIME_MIN [15:00] */
-#define BCHP_SWITCH_CORE_PAUSE_TIME_MIN_PAUSE_TIME_MIN_MASK 0x0000ffff
-#define BCHP_SWITCH_CORE_PAUSE_TIME_MIN_PAUSE_TIME_MIN_SHIFT 0
-#define BCHP_SWITCH_CORE_PAUSE_TIME_MIN_PAUSE_TIME_MIN_DEFAULT 0x00000400
-
-/***************************************************************************
- *PAUSE_TIME_RESET_THD - Quantum Pause Threshold RegisterNot2Release
- ***************************************************************************/
-/* SWITCH_CORE :: PAUSE_TIME_RESET_THD :: reserved_for_padding0 [31:16] */
-#define BCHP_SWITCH_CORE_PAUSE_TIME_RESET_THD_reserved_for_padding0_MASK 0xffff0000
-#define BCHP_SWITCH_CORE_PAUSE_TIME_RESET_THD_reserved_for_padding0_SHIFT 16
-
-/* SWITCH_CORE :: PAUSE_TIME_RESET_THD :: SWITCH_RESV [15:11] */
-#define BCHP_SWITCH_CORE_PAUSE_TIME_RESET_THD_SWITCH_RESV_MASK 0x0000f800
-#define BCHP_SWITCH_CORE_PAUSE_TIME_RESET_THD_SWITCH_RESV_SHIFT 11
-#define BCHP_SWITCH_CORE_PAUSE_TIME_RESET_THD_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: PAUSE_TIME_RESET_THD :: PAUSE_TIME_RESET_THD [10:00] */
-#define BCHP_SWITCH_CORE_PAUSE_TIME_RESET_THD_PAUSE_TIME_RESET_THD_MASK 0x000007ff
-#define BCHP_SWITCH_CORE_PAUSE_TIME_RESET_THD_PAUSE_TIME_RESET_THD_SHIFT 0
-#define BCHP_SWITCH_CORE_PAUSE_TIME_RESET_THD_PAUSE_TIME_RESET_THD_DEFAULT 0x00000100
-
-/***************************************************************************
- *PAUSE_TIME_UPDATE_PERIOD - Quantum Pause Update Period RegisterNot2Release
- ***************************************************************************/
-/* SWITCH_CORE :: PAUSE_TIME_UPDATE_PERIOD :: reserved_for_padding0 [31:16] */
-#define BCHP_SWITCH_CORE_PAUSE_TIME_UPDATE_PERIOD_reserved_for_padding0_MASK 0xffff0000
-#define BCHP_SWITCH_CORE_PAUSE_TIME_UPDATE_PERIOD_reserved_for_padding0_SHIFT 16
-
-/* SWITCH_CORE :: PAUSE_TIME_UPDATE_PERIOD :: PAUSE_TIME_UPDATE_PERIOD [15:00] */
-#define BCHP_SWITCH_CORE_PAUSE_TIME_UPDATE_PERIOD_PAUSE_TIME_UPDATE_PERIOD_MASK 0x0000ffff
-#define BCHP_SWITCH_CORE_PAUSE_TIME_UPDATE_PERIOD_PAUSE_TIME_UPDATE_PERIOD_SHIFT 0
-#define BCHP_SWITCH_CORE_PAUSE_TIME_UPDATE_PERIOD_PAUSE_TIME_UPDATE_PERIOD_DEFAULT 0x00001000
-
-/***************************************************************************
- *PAUSE_TIME_DEFAULT - Default Quantum Pause Time RegisterNot2Release
- ***************************************************************************/
-/* SWITCH_CORE :: PAUSE_TIME_DEFAULT :: reserved_for_padding0 [31:16] */
-#define BCHP_SWITCH_CORE_PAUSE_TIME_DEFAULT_reserved_for_padding0_MASK 0xffff0000
-#define BCHP_SWITCH_CORE_PAUSE_TIME_DEFAULT_reserved_for_padding0_SHIFT 16
-
-/* SWITCH_CORE :: PAUSE_TIME_DEFAULT :: PAUSE_TIME_DEFAULT [15:00] */
-#define BCHP_SWITCH_CORE_PAUSE_TIME_DEFAULT_PAUSE_TIME_DEFAULT_MASK 0x0000ffff
-#define BCHP_SWITCH_CORE_PAUSE_TIME_DEFAULT_PAUSE_TIME_DEFAULT_SHIFT 0
-#define BCHP_SWITCH_CORE_PAUSE_TIME_DEFAULT_PAUSE_TIME_DEFAULT_DEFAULT 0x00001000
-
-/***************************************************************************
- *FC_MCAST_DROP_CTRL - Multicast Drop Control RegisterNot2Release
- ***************************************************************************/
-/* SWITCH_CORE :: FC_MCAST_DROP_CTRL :: reserved_for_padding0 [31:16] */
-#define BCHP_SWITCH_CORE_FC_MCAST_DROP_CTRL_reserved_for_padding0_MASK 0xffff0000
-#define BCHP_SWITCH_CORE_FC_MCAST_DROP_CTRL_reserved_for_padding0_SHIFT 16
-
-/* SWITCH_CORE :: FC_MCAST_DROP_CTRL :: SWITCH_RESV [15:09] */
-#define BCHP_SWITCH_CORE_FC_MCAST_DROP_CTRL_SWITCH_RESV_MASK 0x0000fe00
-#define BCHP_SWITCH_CORE_FC_MCAST_DROP_CTRL_SWITCH_RESV_SHIFT 9
-#define BCHP_SWITCH_CORE_FC_MCAST_DROP_CTRL_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: FC_MCAST_DROP_CTRL :: MCAST_PARTIAL_DROP_EN [08:00] */
-#define BCHP_SWITCH_CORE_FC_MCAST_DROP_CTRL_MCAST_PARTIAL_DROP_EN_MASK 0x000001ff
-#define BCHP_SWITCH_CORE_FC_MCAST_DROP_CTRL_MCAST_PARTIAL_DROP_EN_SHIFT 0
-#define BCHP_SWITCH_CORE_FC_MCAST_DROP_CTRL_MCAST_PARTIAL_DROP_EN_DEFAULT 0x000001ff
-
-/***************************************************************************
- *FC_PAUSE_DROP_CTRL - Pause/Drop Control RegisterNot2Release
- ***************************************************************************/
-/* SWITCH_CORE :: FC_PAUSE_DROP_CTRL :: reserved_for_padding0 [31:16] */
-#define BCHP_SWITCH_CORE_FC_PAUSE_DROP_CTRL_reserved_for_padding0_MASK 0xffff0000
-#define BCHP_SWITCH_CORE_FC_PAUSE_DROP_CTRL_reserved_for_padding0_SHIFT 16
-
-/* SWITCH_CORE :: FC_PAUSE_DROP_CTRL :: SWITCH_RESV [15:13] */
-#define BCHP_SWITCH_CORE_FC_PAUSE_DROP_CTRL_SWITCH_RESV_MASK 0x0000e000
-#define BCHP_SWITCH_CORE_FC_PAUSE_DROP_CTRL_SWITCH_RESV_SHIFT 13
-#define BCHP_SWITCH_CORE_FC_PAUSE_DROP_CTRL_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: FC_PAUSE_DROP_CTRL :: QUEUE_BASED_PAUSE_EN [12:12] */
-#define BCHP_SWITCH_CORE_FC_PAUSE_DROP_CTRL_QUEUE_BASED_PAUSE_EN_MASK 0x00001000
-#define BCHP_SWITCH_CORE_FC_PAUSE_DROP_CTRL_QUEUE_BASED_PAUSE_EN_SHIFT 12
-#define BCHP_SWITCH_CORE_FC_PAUSE_DROP_CTRL_QUEUE_BASED_PAUSE_EN_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: FC_PAUSE_DROP_CTRL :: TX_IMP0_TOTAL_PAUSE_EN [11:11] */
-#define BCHP_SWITCH_CORE_FC_PAUSE_DROP_CTRL_TX_IMP0_TOTAL_PAUSE_EN_MASK 0x00000800
-#define BCHP_SWITCH_CORE_FC_PAUSE_DROP_CTRL_TX_IMP0_TOTAL_PAUSE_EN_SHIFT 11
-#define BCHP_SWITCH_CORE_FC_PAUSE_DROP_CTRL_TX_IMP0_TOTAL_PAUSE_EN_DEFAULT 0x00000001
-
-/* SWITCH_CORE :: FC_PAUSE_DROP_CTRL :: TX_IMP0_TXQ_PAUSE_EN [10:10] */
-#define BCHP_SWITCH_CORE_FC_PAUSE_DROP_CTRL_TX_IMP0_TXQ_PAUSE_EN_MASK 0x00000400
-#define BCHP_SWITCH_CORE_FC_PAUSE_DROP_CTRL_TX_IMP0_TXQ_PAUSE_EN_SHIFT 10
-#define BCHP_SWITCH_CORE_FC_PAUSE_DROP_CTRL_TX_IMP0_TXQ_PAUSE_EN_DEFAULT 0x00000001
-
-/* SWITCH_CORE :: FC_PAUSE_DROP_CTRL :: TX_IMP1_TOTAL_PAUSE_EN [09:09] */
-#define BCHP_SWITCH_CORE_FC_PAUSE_DROP_CTRL_TX_IMP1_TOTAL_PAUSE_EN_MASK 0x00000200
-#define BCHP_SWITCH_CORE_FC_PAUSE_DROP_CTRL_TX_IMP1_TOTAL_PAUSE_EN_SHIFT 9
-#define BCHP_SWITCH_CORE_FC_PAUSE_DROP_CTRL_TX_IMP1_TOTAL_PAUSE_EN_DEFAULT 0x00000001
-
-/* SWITCH_CORE :: FC_PAUSE_DROP_CTRL :: TX_IMP1_TXQ_PAUSE_EN [08:08] */
-#define BCHP_SWITCH_CORE_FC_PAUSE_DROP_CTRL_TX_IMP1_TXQ_PAUSE_EN_MASK 0x00000100
-#define BCHP_SWITCH_CORE_FC_PAUSE_DROP_CTRL_TX_IMP1_TXQ_PAUSE_EN_SHIFT 8
-#define BCHP_SWITCH_CORE_FC_PAUSE_DROP_CTRL_TX_IMP1_TXQ_PAUSE_EN_DEFAULT 0x00000001
-
-/* SWITCH_CORE :: FC_PAUSE_DROP_CTRL :: TX_TOTAL_PAUSE_EN [07:07] */
-#define BCHP_SWITCH_CORE_FC_PAUSE_DROP_CTRL_TX_TOTAL_PAUSE_EN_MASK 0x00000080
-#define BCHP_SWITCH_CORE_FC_PAUSE_DROP_CTRL_TX_TOTAL_PAUSE_EN_SHIFT 7
-#define BCHP_SWITCH_CORE_FC_PAUSE_DROP_CTRL_TX_TOTAL_PAUSE_EN_DEFAULT 0x00000001
-
-/* SWITCH_CORE :: FC_PAUSE_DROP_CTRL :: TX_TXQ_PAUSE_EN [06:06] */
-#define BCHP_SWITCH_CORE_FC_PAUSE_DROP_CTRL_TX_TXQ_PAUSE_EN_MASK 0x00000040
-#define BCHP_SWITCH_CORE_FC_PAUSE_DROP_CTRL_TX_TXQ_PAUSE_EN_SHIFT 6
-#define BCHP_SWITCH_CORE_FC_PAUSE_DROP_CTRL_TX_TXQ_PAUSE_EN_DEFAULT 0x00000001
-
-/* SWITCH_CORE :: FC_PAUSE_DROP_CTRL :: RX_DROP_EN [05:05] */
-#define BCHP_SWITCH_CORE_FC_PAUSE_DROP_CTRL_RX_DROP_EN_MASK 0x00000020
-#define BCHP_SWITCH_CORE_FC_PAUSE_DROP_CTRL_RX_DROP_EN_SHIFT 5
-#define BCHP_SWITCH_CORE_FC_PAUSE_DROP_CTRL_RX_DROP_EN_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: FC_PAUSE_DROP_CTRL :: TX_TOTAL_DROP_EN [04:04] */
-#define BCHP_SWITCH_CORE_FC_PAUSE_DROP_CTRL_TX_TOTAL_DROP_EN_MASK 0x00000010
-#define BCHP_SWITCH_CORE_FC_PAUSE_DROP_CTRL_TX_TOTAL_DROP_EN_SHIFT 4
-#define BCHP_SWITCH_CORE_FC_PAUSE_DROP_CTRL_TX_TOTAL_DROP_EN_DEFAULT 0x00000001
-
-/* SWITCH_CORE :: FC_PAUSE_DROP_CTRL :: TX_TXQ_DROP_EN [03:03] */
-#define BCHP_SWITCH_CORE_FC_PAUSE_DROP_CTRL_TX_TXQ_DROP_EN_MASK 0x00000008
-#define BCHP_SWITCH_CORE_FC_PAUSE_DROP_CTRL_TX_TXQ_DROP_EN_SHIFT 3
-#define BCHP_SWITCH_CORE_FC_PAUSE_DROP_CTRL_TX_TXQ_DROP_EN_DEFAULT 0x00000001
-
-/* SWITCH_CORE :: FC_PAUSE_DROP_CTRL :: RX_BASED_CTRL_EN [02:02] */
-#define BCHP_SWITCH_CORE_FC_PAUSE_DROP_CTRL_RX_BASED_CTRL_EN_MASK 0x00000004
-#define BCHP_SWITCH_CORE_FC_PAUSE_DROP_CTRL_RX_BASED_CTRL_EN_SHIFT 2
-#define BCHP_SWITCH_CORE_FC_PAUSE_DROP_CTRL_RX_BASED_CTRL_EN_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: FC_PAUSE_DROP_CTRL :: TX_QUANTUM_CTRL_EN [01:01] */
-#define BCHP_SWITCH_CORE_FC_PAUSE_DROP_CTRL_TX_QUANTUM_CTRL_EN_MASK 0x00000002
-#define BCHP_SWITCH_CORE_FC_PAUSE_DROP_CTRL_TX_QUANTUM_CTRL_EN_SHIFT 1
-#define BCHP_SWITCH_CORE_FC_PAUSE_DROP_CTRL_TX_QUANTUM_CTRL_EN_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: FC_PAUSE_DROP_CTRL :: TX_BASED_CTRL_EN [00:00] */
-#define BCHP_SWITCH_CORE_FC_PAUSE_DROP_CTRL_TX_BASED_CTRL_EN_MASK 0x00000001
-#define BCHP_SWITCH_CORE_FC_PAUSE_DROP_CTRL_TX_BASED_CTRL_EN_SHIFT 0
-#define BCHP_SWITCH_CORE_FC_PAUSE_DROP_CTRL_TX_BASED_CTRL_EN_DEFAULT 0x00000001
-
-/***************************************************************************
- *FC_TXQ_THD_PAUSE_OFF - TXQ Pause Off Threshold RegisterNot2Release
- ***************************************************************************/
-/* SWITCH_CORE :: FC_TXQ_THD_PAUSE_OFF :: reserved_for_padding0 [31:16] */
-#define BCHP_SWITCH_CORE_FC_TXQ_THD_PAUSE_OFF_reserved_for_padding0_MASK 0xffff0000
-#define BCHP_SWITCH_CORE_FC_TXQ_THD_PAUSE_OFF_reserved_for_padding0_SHIFT 16
-
-/* SWITCH_CORE :: FC_TXQ_THD_PAUSE_OFF :: SWITCH_RESV [15:11] */
-#define BCHP_SWITCH_CORE_FC_TXQ_THD_PAUSE_OFF_SWITCH_RESV_MASK 0x0000f800
-#define BCHP_SWITCH_CORE_FC_TXQ_THD_PAUSE_OFF_SWITCH_RESV_SHIFT 11
-#define BCHP_SWITCH_CORE_FC_TXQ_THD_PAUSE_OFF_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: FC_TXQ_THD_PAUSE_OFF :: TXQ_THD_PAUSE_OFF [10:00] */
-#define BCHP_SWITCH_CORE_FC_TXQ_THD_PAUSE_OFF_TXQ_THD_PAUSE_OFF_MASK 0x000007ff
-#define BCHP_SWITCH_CORE_FC_TXQ_THD_PAUSE_OFF_TXQ_THD_PAUSE_OFF_SHIFT 0
-#define BCHP_SWITCH_CORE_FC_TXQ_THD_PAUSE_OFF_TXQ_THD_PAUSE_OFF_DEFAULT 0x00000008
-
-/***************************************************************************
- *FC_RX_RUNOFF - RX-Based Run-Off RegisterNot2Release
- ***************************************************************************/
-/* SWITCH_CORE :: FC_RX_RUNOFF :: reserved_for_padding0 [31:16] */
-#define BCHP_SWITCH_CORE_FC_RX_RUNOFF_reserved_for_padding0_MASK 0xffff0000
-#define BCHP_SWITCH_CORE_FC_RX_RUNOFF_reserved_for_padding0_SHIFT 16
-
-/* SWITCH_CORE :: FC_RX_RUNOFF :: SWITCH_RESV [15:11] */
-#define BCHP_SWITCH_CORE_FC_RX_RUNOFF_SWITCH_RESV_MASK 0x0000f800
-#define BCHP_SWITCH_CORE_FC_RX_RUNOFF_SWITCH_RESV_SHIFT 11
-#define BCHP_SWITCH_CORE_FC_RX_RUNOFF_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: FC_RX_RUNOFF :: RX_RUN_OFF_THD [10:00] */
-#define BCHP_SWITCH_CORE_FC_RX_RUNOFF_RX_RUN_OFF_THD_MASK 0x000007ff
-#define BCHP_SWITCH_CORE_FC_RX_RUNOFF_RX_RUN_OFF_THD_SHIFT 0
-#define BCHP_SWITCH_CORE_FC_RX_RUNOFF_RX_RUN_OFF_THD_DEFAULT 0x00000013
-
-/***************************************************************************
- *FC_RX_RSV_THD - RX-Based Reserved RegisterNot2Release
- ***************************************************************************/
-/* SWITCH_CORE :: FC_RX_RSV_THD :: reserved_for_padding0 [31:16] */
-#define BCHP_SWITCH_CORE_FC_RX_RSV_THD_reserved_for_padding0_MASK 0xffff0000
-#define BCHP_SWITCH_CORE_FC_RX_RSV_THD_reserved_for_padding0_SHIFT 16
-
-/* SWITCH_CORE :: FC_RX_RSV_THD :: SWITCH_RESV [15:11] */
-#define BCHP_SWITCH_CORE_FC_RX_RSV_THD_SWITCH_RESV_MASK 0x0000f800
-#define BCHP_SWITCH_CORE_FC_RX_RSV_THD_SWITCH_RESV_SHIFT 11
-#define BCHP_SWITCH_CORE_FC_RX_RSV_THD_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: FC_RX_RSV_THD :: RX_RSV_THD [10:00] */
-#define BCHP_SWITCH_CORE_FC_RX_RSV_THD_RX_RSV_THD_MASK 0x000007ff
-#define BCHP_SWITCH_CORE_FC_RX_RSV_THD_RX_RSV_THD_SHIFT 0
-#define BCHP_SWITCH_CORE_FC_RX_RSV_THD_RX_RSV_THD_DEFAULT 0x0000000a
-
-/***************************************************************************
- *FC_RX_HYST_THD - RX-Based Hysteresis RegisterNot2Release
- ***************************************************************************/
-/* SWITCH_CORE :: FC_RX_HYST_THD :: reserved_for_padding0 [31:16] */
-#define BCHP_SWITCH_CORE_FC_RX_HYST_THD_reserved_for_padding0_MASK 0xffff0000
-#define BCHP_SWITCH_CORE_FC_RX_HYST_THD_reserved_for_padding0_SHIFT 16
-
-/* SWITCH_CORE :: FC_RX_HYST_THD :: SWITCH_RESV [15:11] */
-#define BCHP_SWITCH_CORE_FC_RX_HYST_THD_SWITCH_RESV_MASK 0x0000f800
-#define BCHP_SWITCH_CORE_FC_RX_HYST_THD_SWITCH_RESV_SHIFT 11
-#define BCHP_SWITCH_CORE_FC_RX_HYST_THD_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: FC_RX_HYST_THD :: RX_HYST_THD [10:00] */
-#define BCHP_SWITCH_CORE_FC_RX_HYST_THD_RX_HYST_THD_MASK 0x000007ff
-#define BCHP_SWITCH_CORE_FC_RX_HYST_THD_RX_HYST_THD_SHIFT 0
-#define BCHP_SWITCH_CORE_FC_RX_HYST_THD_RX_HYST_THD_DEFAULT 0x00000014
-
-/***************************************************************************
- *FC_RX_MAX_PTR - RX-Based Maximum Buffer Remap RegisterNot2Release
- ***************************************************************************/
-/* SWITCH_CORE :: FC_RX_MAX_PTR :: reserved_for_padding0 [31:16] */
-#define BCHP_SWITCH_CORE_FC_RX_MAX_PTR_reserved_for_padding0_MASK 0xffff0000
-#define BCHP_SWITCH_CORE_FC_RX_MAX_PTR_reserved_for_padding0_SHIFT 16
-
-/* SWITCH_CORE :: FC_RX_MAX_PTR :: EN_REMAP [15:15] */
-#define BCHP_SWITCH_CORE_FC_RX_MAX_PTR_EN_REMAP_MASK 0x00008000
-#define BCHP_SWITCH_CORE_FC_RX_MAX_PTR_EN_REMAP_SHIFT 15
-#define BCHP_SWITCH_CORE_FC_RX_MAX_PTR_EN_REMAP_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: FC_RX_MAX_PTR :: SWITCH_RESV [14:11] */
-#define BCHP_SWITCH_CORE_FC_RX_MAX_PTR_SWITCH_RESV_MASK 0x00007800
-#define BCHP_SWITCH_CORE_FC_RX_MAX_PTR_SWITCH_RESV_SHIFT 11
-#define BCHP_SWITCH_CORE_FC_RX_MAX_PTR_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: FC_RX_MAX_PTR :: MAXBUF_REMAP_THD [10:00] */
-#define BCHP_SWITCH_CORE_FC_RX_MAX_PTR_MAXBUF_REMAP_THD_MASK 0x000007ff
-#define BCHP_SWITCH_CORE_FC_RX_MAX_PTR_MAXBUF_REMAP_THD_SHIFT 0
-#define BCHP_SWITCH_CORE_FC_RX_MAX_PTR_MAXBUF_REMAP_THD_DEFAULT 0x000001ea
-
-/***************************************************************************
- *FC_SPARE_ZERO_REG - Flow Control Spare Zero RegisterNot2Release
- ***************************************************************************/
-/* SWITCH_CORE :: FC_SPARE_ZERO_REG :: reserved_for_padding0 [31:16] */
-#define BCHP_SWITCH_CORE_FC_SPARE_ZERO_REG_reserved_for_padding0_MASK 0xffff0000
-#define BCHP_SWITCH_CORE_FC_SPARE_ZERO_REG_reserved_for_padding0_SHIFT 16
-
-/* SWITCH_CORE :: FC_SPARE_ZERO_REG :: SPARE_ZERO [15:00] */
-#define BCHP_SWITCH_CORE_FC_SPARE_ZERO_REG_SPARE_ZERO_MASK 0x0000ffff
-#define BCHP_SWITCH_CORE_FC_SPARE_ZERO_REG_SPARE_ZERO_SHIFT 0
-#define BCHP_SWITCH_CORE_FC_SPARE_ZERO_REG_SPARE_ZERO_DEFAULT 0x00000000
-
-/***************************************************************************
- *FC_SPARE_ONE_REG - Flow Control Spare One RegisterNot2Release
- ***************************************************************************/
-/* SWITCH_CORE :: FC_SPARE_ONE_REG :: reserved_for_padding0 [31:16] */
-#define BCHP_SWITCH_CORE_FC_SPARE_ONE_REG_reserved_for_padding0_MASK 0xffff0000
-#define BCHP_SWITCH_CORE_FC_SPARE_ONE_REG_reserved_for_padding0_SHIFT 16
-
-/* SWITCH_CORE :: FC_SPARE_ONE_REG :: SPARE_ONE [15:00] */
-#define BCHP_SWITCH_CORE_FC_SPARE_ONE_REG_SPARE_ONE_MASK 0x0000ffff
-#define BCHP_SWITCH_CORE_FC_SPARE_ONE_REG_SPARE_ONE_SHIFT 0
-#define BCHP_SWITCH_CORE_FC_SPARE_ONE_REG_SPARE_ONE_DEFAULT 0x0000ffff
-
-/***************************************************************************
- *FC_MON_TXQ_Port_0 - Monitored TXQ N RegisterNot2Release
- ***************************************************************************/
-/* SWITCH_CORE :: FC_MON_TXQ_Port_0 :: reserved_for_padding0 [31:16] */
-#define BCHP_SWITCH_CORE_FC_MON_TXQ_Port_0_reserved_for_padding0_MASK 0xffff0000
-#define BCHP_SWITCH_CORE_FC_MON_TXQ_Port_0_reserved_for_padding0_SHIFT 16
-
-/* SWITCH_CORE :: FC_MON_TXQ_Port_0 :: SWITCH_RESV [15:11] */
-#define BCHP_SWITCH_CORE_FC_MON_TXQ_Port_0_SWITCH_RESV_MASK 0x0000f800
-#define BCHP_SWITCH_CORE_FC_MON_TXQ_Port_0_SWITCH_RESV_SHIFT 11
-#define BCHP_SWITCH_CORE_FC_MON_TXQ_Port_0_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: FC_MON_TXQ_Port_0 :: MONITORED_TXQ_CNT [10:00] */
-#define BCHP_SWITCH_CORE_FC_MON_TXQ_Port_0_MONITORED_TXQ_CNT_MASK 0x000007ff
-#define BCHP_SWITCH_CORE_FC_MON_TXQ_Port_0_MONITORED_TXQ_CNT_SHIFT 0
-#define BCHP_SWITCH_CORE_FC_MON_TXQ_Port_0_MONITORED_TXQ_CNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *FC_MON_TXQ_Port_1 - Monitored TXQ N RegisterNot2Release
- ***************************************************************************/
-/* SWITCH_CORE :: FC_MON_TXQ_Port_1 :: reserved_for_padding0 [31:16] */
-#define BCHP_SWITCH_CORE_FC_MON_TXQ_Port_1_reserved_for_padding0_MASK 0xffff0000
-#define BCHP_SWITCH_CORE_FC_MON_TXQ_Port_1_reserved_for_padding0_SHIFT 16
-
-/* SWITCH_CORE :: FC_MON_TXQ_Port_1 :: SWITCH_RESV [15:11] */
-#define BCHP_SWITCH_CORE_FC_MON_TXQ_Port_1_SWITCH_RESV_MASK 0x0000f800
-#define BCHP_SWITCH_CORE_FC_MON_TXQ_Port_1_SWITCH_RESV_SHIFT 11
-#define BCHP_SWITCH_CORE_FC_MON_TXQ_Port_1_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: FC_MON_TXQ_Port_1 :: MONITORED_TXQ_CNT [10:00] */
-#define BCHP_SWITCH_CORE_FC_MON_TXQ_Port_1_MONITORED_TXQ_CNT_MASK 0x000007ff
-#define BCHP_SWITCH_CORE_FC_MON_TXQ_Port_1_MONITORED_TXQ_CNT_SHIFT 0
-#define BCHP_SWITCH_CORE_FC_MON_TXQ_Port_1_MONITORED_TXQ_CNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *FC_MON_TXQ_Port_2 - Monitored TXQ N RegisterNot2Release
- ***************************************************************************/
-/* SWITCH_CORE :: FC_MON_TXQ_Port_2 :: reserved_for_padding0 [31:16] */
-#define BCHP_SWITCH_CORE_FC_MON_TXQ_Port_2_reserved_for_padding0_MASK 0xffff0000
-#define BCHP_SWITCH_CORE_FC_MON_TXQ_Port_2_reserved_for_padding0_SHIFT 16
-
-/* SWITCH_CORE :: FC_MON_TXQ_Port_2 :: SWITCH_RESV [15:11] */
-#define BCHP_SWITCH_CORE_FC_MON_TXQ_Port_2_SWITCH_RESV_MASK 0x0000f800
-#define BCHP_SWITCH_CORE_FC_MON_TXQ_Port_2_SWITCH_RESV_SHIFT 11
-#define BCHP_SWITCH_CORE_FC_MON_TXQ_Port_2_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: FC_MON_TXQ_Port_2 :: MONITORED_TXQ_CNT [10:00] */
-#define BCHP_SWITCH_CORE_FC_MON_TXQ_Port_2_MONITORED_TXQ_CNT_MASK 0x000007ff
-#define BCHP_SWITCH_CORE_FC_MON_TXQ_Port_2_MONITORED_TXQ_CNT_SHIFT 0
-#define BCHP_SWITCH_CORE_FC_MON_TXQ_Port_2_MONITORED_TXQ_CNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *FC_MON_TXQ_Port_3 - Monitored TXQ N RegisterNot2Release
- ***************************************************************************/
-/* SWITCH_CORE :: FC_MON_TXQ_Port_3 :: reserved_for_padding0 [31:16] */
-#define BCHP_SWITCH_CORE_FC_MON_TXQ_Port_3_reserved_for_padding0_MASK 0xffff0000
-#define BCHP_SWITCH_CORE_FC_MON_TXQ_Port_3_reserved_for_padding0_SHIFT 16
-
-/* SWITCH_CORE :: FC_MON_TXQ_Port_3 :: SWITCH_RESV [15:11] */
-#define BCHP_SWITCH_CORE_FC_MON_TXQ_Port_3_SWITCH_RESV_MASK 0x0000f800
-#define BCHP_SWITCH_CORE_FC_MON_TXQ_Port_3_SWITCH_RESV_SHIFT 11
-#define BCHP_SWITCH_CORE_FC_MON_TXQ_Port_3_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: FC_MON_TXQ_Port_3 :: MONITORED_TXQ_CNT [10:00] */
-#define BCHP_SWITCH_CORE_FC_MON_TXQ_Port_3_MONITORED_TXQ_CNT_MASK 0x000007ff
-#define BCHP_SWITCH_CORE_FC_MON_TXQ_Port_3_MONITORED_TXQ_CNT_SHIFT 0
-#define BCHP_SWITCH_CORE_FC_MON_TXQ_Port_3_MONITORED_TXQ_CNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *FC_MON_TXQ_Port_4 - Monitored TXQ N RegisterNot2Release
- ***************************************************************************/
-/* SWITCH_CORE :: FC_MON_TXQ_Port_4 :: reserved_for_padding0 [31:16] */
-#define BCHP_SWITCH_CORE_FC_MON_TXQ_Port_4_reserved_for_padding0_MASK 0xffff0000
-#define BCHP_SWITCH_CORE_FC_MON_TXQ_Port_4_reserved_for_padding0_SHIFT 16
-
-/* SWITCH_CORE :: FC_MON_TXQ_Port_4 :: SWITCH_RESV [15:11] */
-#define BCHP_SWITCH_CORE_FC_MON_TXQ_Port_4_SWITCH_RESV_MASK 0x0000f800
-#define BCHP_SWITCH_CORE_FC_MON_TXQ_Port_4_SWITCH_RESV_SHIFT 11
-#define BCHP_SWITCH_CORE_FC_MON_TXQ_Port_4_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: FC_MON_TXQ_Port_4 :: MONITORED_TXQ_CNT [10:00] */
-#define BCHP_SWITCH_CORE_FC_MON_TXQ_Port_4_MONITORED_TXQ_CNT_MASK 0x000007ff
-#define BCHP_SWITCH_CORE_FC_MON_TXQ_Port_4_MONITORED_TXQ_CNT_SHIFT 0
-#define BCHP_SWITCH_CORE_FC_MON_TXQ_Port_4_MONITORED_TXQ_CNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *FC_MON_TXQ_Port_5 - Monitored TXQ N RegisterNot2Release
- ***************************************************************************/
-/* SWITCH_CORE :: FC_MON_TXQ_Port_5 :: reserved_for_padding0 [31:16] */
-#define BCHP_SWITCH_CORE_FC_MON_TXQ_Port_5_reserved_for_padding0_MASK 0xffff0000
-#define BCHP_SWITCH_CORE_FC_MON_TXQ_Port_5_reserved_for_padding0_SHIFT 16
-
-/* SWITCH_CORE :: FC_MON_TXQ_Port_5 :: SWITCH_RESV [15:11] */
-#define BCHP_SWITCH_CORE_FC_MON_TXQ_Port_5_SWITCH_RESV_MASK 0x0000f800
-#define BCHP_SWITCH_CORE_FC_MON_TXQ_Port_5_SWITCH_RESV_SHIFT 11
-#define BCHP_SWITCH_CORE_FC_MON_TXQ_Port_5_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: FC_MON_TXQ_Port_5 :: MONITORED_TXQ_CNT [10:00] */
-#define BCHP_SWITCH_CORE_FC_MON_TXQ_Port_5_MONITORED_TXQ_CNT_MASK 0x000007ff
-#define BCHP_SWITCH_CORE_FC_MON_TXQ_Port_5_MONITORED_TXQ_CNT_SHIFT 0
-#define BCHP_SWITCH_CORE_FC_MON_TXQ_Port_5_MONITORED_TXQ_CNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *FC_MON_TXQ_Port_6 - Monitored TXQ N RegisterNot2Release
- ***************************************************************************/
-/* SWITCH_CORE :: FC_MON_TXQ_Port_6 :: reserved_for_padding0 [31:16] */
-#define BCHP_SWITCH_CORE_FC_MON_TXQ_Port_6_reserved_for_padding0_MASK 0xffff0000
-#define BCHP_SWITCH_CORE_FC_MON_TXQ_Port_6_reserved_for_padding0_SHIFT 16
-
-/* SWITCH_CORE :: FC_MON_TXQ_Port_6 :: SWITCH_RESV [15:11] */
-#define BCHP_SWITCH_CORE_FC_MON_TXQ_Port_6_SWITCH_RESV_MASK 0x0000f800
-#define BCHP_SWITCH_CORE_FC_MON_TXQ_Port_6_SWITCH_RESV_SHIFT 11
-#define BCHP_SWITCH_CORE_FC_MON_TXQ_Port_6_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: FC_MON_TXQ_Port_6 :: MONITORED_TXQ_CNT [10:00] */
-#define BCHP_SWITCH_CORE_FC_MON_TXQ_Port_6_MONITORED_TXQ_CNT_MASK 0x000007ff
-#define BCHP_SWITCH_CORE_FC_MON_TXQ_Port_6_MONITORED_TXQ_CNT_SHIFT 0
-#define BCHP_SWITCH_CORE_FC_MON_TXQ_Port_6_MONITORED_TXQ_CNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *FC_MON_TXQ_Port_7 - Monitored TXQ N RegisterNot2Release
- ***************************************************************************/
-/* SWITCH_CORE :: FC_MON_TXQ_Port_7 :: reserved_for_padding0 [31:16] */
-#define BCHP_SWITCH_CORE_FC_MON_TXQ_Port_7_reserved_for_padding0_MASK 0xffff0000
-#define BCHP_SWITCH_CORE_FC_MON_TXQ_Port_7_reserved_for_padding0_SHIFT 16
-
-/* SWITCH_CORE :: FC_MON_TXQ_Port_7 :: SWITCH_RESV [15:11] */
-#define BCHP_SWITCH_CORE_FC_MON_TXQ_Port_7_SWITCH_RESV_MASK 0x0000f800
-#define BCHP_SWITCH_CORE_FC_MON_TXQ_Port_7_SWITCH_RESV_SHIFT 11
-#define BCHP_SWITCH_CORE_FC_MON_TXQ_Port_7_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: FC_MON_TXQ_Port_7 :: MONITORED_TXQ_CNT [10:00] */
-#define BCHP_SWITCH_CORE_FC_MON_TXQ_Port_7_MONITORED_TXQ_CNT_MASK 0x000007ff
-#define BCHP_SWITCH_CORE_FC_MON_TXQ_Port_7_MONITORED_TXQ_CNT_SHIFT 0
-#define BCHP_SWITCH_CORE_FC_MON_TXQ_Port_7_MONITORED_TXQ_CNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *FC_PEAK_TXQ_Port_0 - Peak TXQ N Counter RegisterNot2Release
- ***************************************************************************/
-/* SWITCH_CORE :: FC_PEAK_TXQ_Port_0 :: reserved_for_padding0 [31:16] */
-#define BCHP_SWITCH_CORE_FC_PEAK_TXQ_Port_0_reserved_for_padding0_MASK 0xffff0000
-#define BCHP_SWITCH_CORE_FC_PEAK_TXQ_Port_0_reserved_for_padding0_SHIFT 16
-
-/* SWITCH_CORE :: FC_PEAK_TXQ_Port_0 :: SWITCH_RESV [15:11] */
-#define BCHP_SWITCH_CORE_FC_PEAK_TXQ_Port_0_SWITCH_RESV_MASK 0x0000f800
-#define BCHP_SWITCH_CORE_FC_PEAK_TXQ_Port_0_SWITCH_RESV_SHIFT 11
-#define BCHP_SWITCH_CORE_FC_PEAK_TXQ_Port_0_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: FC_PEAK_TXQ_Port_0 :: PEAK_TXQ_CNT [10:00] */
-#define BCHP_SWITCH_CORE_FC_PEAK_TXQ_Port_0_PEAK_TXQ_CNT_MASK 0x000007ff
-#define BCHP_SWITCH_CORE_FC_PEAK_TXQ_Port_0_PEAK_TXQ_CNT_SHIFT 0
-#define BCHP_SWITCH_CORE_FC_PEAK_TXQ_Port_0_PEAK_TXQ_CNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *FC_PEAK_TXQ_Port_1 - Peak TXQ N Counter RegisterNot2Release
- ***************************************************************************/
-/* SWITCH_CORE :: FC_PEAK_TXQ_Port_1 :: reserved_for_padding0 [31:16] */
-#define BCHP_SWITCH_CORE_FC_PEAK_TXQ_Port_1_reserved_for_padding0_MASK 0xffff0000
-#define BCHP_SWITCH_CORE_FC_PEAK_TXQ_Port_1_reserved_for_padding0_SHIFT 16
-
-/* SWITCH_CORE :: FC_PEAK_TXQ_Port_1 :: SWITCH_RESV [15:11] */
-#define BCHP_SWITCH_CORE_FC_PEAK_TXQ_Port_1_SWITCH_RESV_MASK 0x0000f800
-#define BCHP_SWITCH_CORE_FC_PEAK_TXQ_Port_1_SWITCH_RESV_SHIFT 11
-#define BCHP_SWITCH_CORE_FC_PEAK_TXQ_Port_1_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: FC_PEAK_TXQ_Port_1 :: PEAK_TXQ_CNT [10:00] */
-#define BCHP_SWITCH_CORE_FC_PEAK_TXQ_Port_1_PEAK_TXQ_CNT_MASK 0x000007ff
-#define BCHP_SWITCH_CORE_FC_PEAK_TXQ_Port_1_PEAK_TXQ_CNT_SHIFT 0
-#define BCHP_SWITCH_CORE_FC_PEAK_TXQ_Port_1_PEAK_TXQ_CNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *FC_PEAK_TXQ_Port_2 - Peak TXQ N Counter RegisterNot2Release
- ***************************************************************************/
-/* SWITCH_CORE :: FC_PEAK_TXQ_Port_2 :: reserved_for_padding0 [31:16] */
-#define BCHP_SWITCH_CORE_FC_PEAK_TXQ_Port_2_reserved_for_padding0_MASK 0xffff0000
-#define BCHP_SWITCH_CORE_FC_PEAK_TXQ_Port_2_reserved_for_padding0_SHIFT 16
-
-/* SWITCH_CORE :: FC_PEAK_TXQ_Port_2 :: SWITCH_RESV [15:11] */
-#define BCHP_SWITCH_CORE_FC_PEAK_TXQ_Port_2_SWITCH_RESV_MASK 0x0000f800
-#define BCHP_SWITCH_CORE_FC_PEAK_TXQ_Port_2_SWITCH_RESV_SHIFT 11
-#define BCHP_SWITCH_CORE_FC_PEAK_TXQ_Port_2_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: FC_PEAK_TXQ_Port_2 :: PEAK_TXQ_CNT [10:00] */
-#define BCHP_SWITCH_CORE_FC_PEAK_TXQ_Port_2_PEAK_TXQ_CNT_MASK 0x000007ff
-#define BCHP_SWITCH_CORE_FC_PEAK_TXQ_Port_2_PEAK_TXQ_CNT_SHIFT 0
-#define BCHP_SWITCH_CORE_FC_PEAK_TXQ_Port_2_PEAK_TXQ_CNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *FC_PEAK_TXQ_Port_3 - Peak TXQ N Counter RegisterNot2Release
- ***************************************************************************/
-/* SWITCH_CORE :: FC_PEAK_TXQ_Port_3 :: reserved_for_padding0 [31:16] */
-#define BCHP_SWITCH_CORE_FC_PEAK_TXQ_Port_3_reserved_for_padding0_MASK 0xffff0000
-#define BCHP_SWITCH_CORE_FC_PEAK_TXQ_Port_3_reserved_for_padding0_SHIFT 16
-
-/* SWITCH_CORE :: FC_PEAK_TXQ_Port_3 :: SWITCH_RESV [15:11] */
-#define BCHP_SWITCH_CORE_FC_PEAK_TXQ_Port_3_SWITCH_RESV_MASK 0x0000f800
-#define BCHP_SWITCH_CORE_FC_PEAK_TXQ_Port_3_SWITCH_RESV_SHIFT 11
-#define BCHP_SWITCH_CORE_FC_PEAK_TXQ_Port_3_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: FC_PEAK_TXQ_Port_3 :: PEAK_TXQ_CNT [10:00] */
-#define BCHP_SWITCH_CORE_FC_PEAK_TXQ_Port_3_PEAK_TXQ_CNT_MASK 0x000007ff
-#define BCHP_SWITCH_CORE_FC_PEAK_TXQ_Port_3_PEAK_TXQ_CNT_SHIFT 0
-#define BCHP_SWITCH_CORE_FC_PEAK_TXQ_Port_3_PEAK_TXQ_CNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *FC_PEAK_TXQ_Port_4 - Peak TXQ N Counter RegisterNot2Release
- ***************************************************************************/
-/* SWITCH_CORE :: FC_PEAK_TXQ_Port_4 :: reserved_for_padding0 [31:16] */
-#define BCHP_SWITCH_CORE_FC_PEAK_TXQ_Port_4_reserved_for_padding0_MASK 0xffff0000
-#define BCHP_SWITCH_CORE_FC_PEAK_TXQ_Port_4_reserved_for_padding0_SHIFT 16
-
-/* SWITCH_CORE :: FC_PEAK_TXQ_Port_4 :: SWITCH_RESV [15:11] */
-#define BCHP_SWITCH_CORE_FC_PEAK_TXQ_Port_4_SWITCH_RESV_MASK 0x0000f800
-#define BCHP_SWITCH_CORE_FC_PEAK_TXQ_Port_4_SWITCH_RESV_SHIFT 11
-#define BCHP_SWITCH_CORE_FC_PEAK_TXQ_Port_4_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: FC_PEAK_TXQ_Port_4 :: PEAK_TXQ_CNT [10:00] */
-#define BCHP_SWITCH_CORE_FC_PEAK_TXQ_Port_4_PEAK_TXQ_CNT_MASK 0x000007ff
-#define BCHP_SWITCH_CORE_FC_PEAK_TXQ_Port_4_PEAK_TXQ_CNT_SHIFT 0
-#define BCHP_SWITCH_CORE_FC_PEAK_TXQ_Port_4_PEAK_TXQ_CNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *FC_PEAK_TXQ_Port_5 - Peak TXQ N Counter RegisterNot2Release
- ***************************************************************************/
-/* SWITCH_CORE :: FC_PEAK_TXQ_Port_5 :: reserved_for_padding0 [31:16] */
-#define BCHP_SWITCH_CORE_FC_PEAK_TXQ_Port_5_reserved_for_padding0_MASK 0xffff0000
-#define BCHP_SWITCH_CORE_FC_PEAK_TXQ_Port_5_reserved_for_padding0_SHIFT 16
-
-/* SWITCH_CORE :: FC_PEAK_TXQ_Port_5 :: SWITCH_RESV [15:11] */
-#define BCHP_SWITCH_CORE_FC_PEAK_TXQ_Port_5_SWITCH_RESV_MASK 0x0000f800
-#define BCHP_SWITCH_CORE_FC_PEAK_TXQ_Port_5_SWITCH_RESV_SHIFT 11
-#define BCHP_SWITCH_CORE_FC_PEAK_TXQ_Port_5_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: FC_PEAK_TXQ_Port_5 :: PEAK_TXQ_CNT [10:00] */
-#define BCHP_SWITCH_CORE_FC_PEAK_TXQ_Port_5_PEAK_TXQ_CNT_MASK 0x000007ff
-#define BCHP_SWITCH_CORE_FC_PEAK_TXQ_Port_5_PEAK_TXQ_CNT_SHIFT 0
-#define BCHP_SWITCH_CORE_FC_PEAK_TXQ_Port_5_PEAK_TXQ_CNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *FC_PEAK_TXQ_Port_6 - Peak TXQ N Counter RegisterNot2Release
- ***************************************************************************/
-/* SWITCH_CORE :: FC_PEAK_TXQ_Port_6 :: reserved_for_padding0 [31:16] */
-#define BCHP_SWITCH_CORE_FC_PEAK_TXQ_Port_6_reserved_for_padding0_MASK 0xffff0000
-#define BCHP_SWITCH_CORE_FC_PEAK_TXQ_Port_6_reserved_for_padding0_SHIFT 16
-
-/* SWITCH_CORE :: FC_PEAK_TXQ_Port_6 :: SWITCH_RESV [15:11] */
-#define BCHP_SWITCH_CORE_FC_PEAK_TXQ_Port_6_SWITCH_RESV_MASK 0x0000f800
-#define BCHP_SWITCH_CORE_FC_PEAK_TXQ_Port_6_SWITCH_RESV_SHIFT 11
-#define BCHP_SWITCH_CORE_FC_PEAK_TXQ_Port_6_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: FC_PEAK_TXQ_Port_6 :: PEAK_TXQ_CNT [10:00] */
-#define BCHP_SWITCH_CORE_FC_PEAK_TXQ_Port_6_PEAK_TXQ_CNT_MASK 0x000007ff
-#define BCHP_SWITCH_CORE_FC_PEAK_TXQ_Port_6_PEAK_TXQ_CNT_SHIFT 0
-#define BCHP_SWITCH_CORE_FC_PEAK_TXQ_Port_6_PEAK_TXQ_CNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *FC_PEAK_TXQ_Port_7 - Peak TXQ N Counter RegisterNot2Release
- ***************************************************************************/
-/* SWITCH_CORE :: FC_PEAK_TXQ_Port_7 :: reserved_for_padding0 [31:16] */
-#define BCHP_SWITCH_CORE_FC_PEAK_TXQ_Port_7_reserved_for_padding0_MASK 0xffff0000
-#define BCHP_SWITCH_CORE_FC_PEAK_TXQ_Port_7_reserved_for_padding0_SHIFT 16
-
-/* SWITCH_CORE :: FC_PEAK_TXQ_Port_7 :: SWITCH_RESV [15:11] */
-#define BCHP_SWITCH_CORE_FC_PEAK_TXQ_Port_7_SWITCH_RESV_MASK 0x0000f800
-#define BCHP_SWITCH_CORE_FC_PEAK_TXQ_Port_7_SWITCH_RESV_SHIFT 11
-#define BCHP_SWITCH_CORE_FC_PEAK_TXQ_Port_7_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: FC_PEAK_TXQ_Port_7 :: PEAK_TXQ_CNT [10:00] */
-#define BCHP_SWITCH_CORE_FC_PEAK_TXQ_Port_7_PEAK_TXQ_CNT_MASK 0x000007ff
-#define BCHP_SWITCH_CORE_FC_PEAK_TXQ_Port_7_PEAK_TXQ_CNT_SHIFT 0
-#define BCHP_SWITCH_CORE_FC_PEAK_TXQ_Port_7_PEAK_TXQ_CNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *FC_PEAK_TOTAL_USED - Peak Total Used Count RegisterNot2Release
- ***************************************************************************/
-/* SWITCH_CORE :: FC_PEAK_TOTAL_USED :: reserved_for_padding0 [31:16] */
-#define BCHP_SWITCH_CORE_FC_PEAK_TOTAL_USED_reserved_for_padding0_MASK 0xffff0000
-#define BCHP_SWITCH_CORE_FC_PEAK_TOTAL_USED_reserved_for_padding0_SHIFT 16
-
-/* SWITCH_CORE :: FC_PEAK_TOTAL_USED :: SWITCH_RESV [15:11] */
-#define BCHP_SWITCH_CORE_FC_PEAK_TOTAL_USED_SWITCH_RESV_MASK 0x0000f800
-#define BCHP_SWITCH_CORE_FC_PEAK_TOTAL_USED_SWITCH_RESV_SHIFT 11
-#define BCHP_SWITCH_CORE_FC_PEAK_TOTAL_USED_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: FC_PEAK_TOTAL_USED :: PEAK_TOTAL_USE_CNT [10:00] */
-#define BCHP_SWITCH_CORE_FC_PEAK_TOTAL_USED_PEAK_TOTAL_USE_CNT_MASK 0x000007ff
-#define BCHP_SWITCH_CORE_FC_PEAK_TOTAL_USED_PEAK_TOTAL_USE_CNT_SHIFT 0
-#define BCHP_SWITCH_CORE_FC_PEAK_TOTAL_USED_PEAK_TOTAL_USE_CNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *FC_TOTAL_USED - Total Used Count RegisterNot2Release
- ***************************************************************************/
-/* SWITCH_CORE :: FC_TOTAL_USED :: reserved_for_padding0 [31:16] */
-#define BCHP_SWITCH_CORE_FC_TOTAL_USED_reserved_for_padding0_MASK 0xffff0000
-#define BCHP_SWITCH_CORE_FC_TOTAL_USED_reserved_for_padding0_SHIFT 16
-
-/* SWITCH_CORE :: FC_TOTAL_USED :: SWITCH_RESV [15:11] */
-#define BCHP_SWITCH_CORE_FC_TOTAL_USED_SWITCH_RESV_MASK 0x0000f800
-#define BCHP_SWITCH_CORE_FC_TOTAL_USED_SWITCH_RESV_SHIFT 11
-#define BCHP_SWITCH_CORE_FC_TOTAL_USED_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: FC_TOTAL_USED :: TOTAL_USE_CNT [10:00] */
-#define BCHP_SWITCH_CORE_FC_TOTAL_USED_TOTAL_USE_CNT_MASK 0x000007ff
-#define BCHP_SWITCH_CORE_FC_TOTAL_USED_TOTAL_USE_CNT_SHIFT 0
-#define BCHP_SWITCH_CORE_FC_TOTAL_USED_TOTAL_USE_CNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *FC_PEAK_RX_CNT - Peak RX Counter RegisterNot2Release
- ***************************************************************************/
-/* SWITCH_CORE :: FC_PEAK_RX_CNT :: reserved_for_padding0 [31:16] */
-#define BCHP_SWITCH_CORE_FC_PEAK_RX_CNT_reserved_for_padding0_MASK 0xffff0000
-#define BCHP_SWITCH_CORE_FC_PEAK_RX_CNT_reserved_for_padding0_SHIFT 16
-
-/* SWITCH_CORE :: FC_PEAK_RX_CNT :: SWITCH_RESV [15:11] */
-#define BCHP_SWITCH_CORE_FC_PEAK_RX_CNT_SWITCH_RESV_MASK 0x0000f800
-#define BCHP_SWITCH_CORE_FC_PEAK_RX_CNT_SWITCH_RESV_SHIFT 11
-#define BCHP_SWITCH_CORE_FC_PEAK_RX_CNT_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: FC_PEAK_RX_CNT :: PEAK_RXBUF_CNT [10:00] */
-#define BCHP_SWITCH_CORE_FC_PEAK_RX_CNT_PEAK_RXBUF_CNT_MASK 0x000007ff
-#define BCHP_SWITCH_CORE_FC_PEAK_RX_CNT_PEAK_RXBUF_CNT_SHIFT 0
-#define BCHP_SWITCH_CORE_FC_PEAK_RX_CNT_PEAK_RXBUF_CNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *FC_LINK_PORTMAP - PHY Link Information RegisterNot2Release
- ***************************************************************************/
-/* SWITCH_CORE :: FC_LINK_PORTMAP :: reserved_for_padding0 [31:16] */
-#define BCHP_SWITCH_CORE_FC_LINK_PORTMAP_reserved_for_padding0_MASK 0xffff0000
-#define BCHP_SWITCH_CORE_FC_LINK_PORTMAP_reserved_for_padding0_SHIFT 16
-
-/* SWITCH_CORE :: FC_LINK_PORTMAP :: SWITCH_RESV [15:09] */
-#define BCHP_SWITCH_CORE_FC_LINK_PORTMAP_SWITCH_RESV_MASK 0x0000fe00
-#define BCHP_SWITCH_CORE_FC_LINK_PORTMAP_SWITCH_RESV_SHIFT 9
-#define BCHP_SWITCH_CORE_FC_LINK_PORTMAP_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: FC_LINK_PORTMAP :: LINK_PORTMAP [08:00] */
-#define BCHP_SWITCH_CORE_FC_LINK_PORTMAP_LINK_PORTMAP_MASK 0x000001ff
-#define BCHP_SWITCH_CORE_FC_LINK_PORTMAP_LINK_PORTMAP_SHIFT 0
-#define BCHP_SWITCH_CORE_FC_LINK_PORTMAP_LINK_PORTMAP_DEFAULT 0x00000000
-
-/***************************************************************************
- *FC_GIGA_PORTMAP - Giga Speed Information RegisterNot2Release
- ***************************************************************************/
-/* SWITCH_CORE :: FC_GIGA_PORTMAP :: reserved_for_padding0 [31:16] */
-#define BCHP_SWITCH_CORE_FC_GIGA_PORTMAP_reserved_for_padding0_MASK 0xffff0000
-#define BCHP_SWITCH_CORE_FC_GIGA_PORTMAP_reserved_for_padding0_SHIFT 16
-
-/* SWITCH_CORE :: FC_GIGA_PORTMAP :: SWITCH_RESV [15:09] */
-#define BCHP_SWITCH_CORE_FC_GIGA_PORTMAP_SWITCH_RESV_MASK 0x0000fe00
-#define BCHP_SWITCH_CORE_FC_GIGA_PORTMAP_SWITCH_RESV_SHIFT 9
-#define BCHP_SWITCH_CORE_FC_GIGA_PORTMAP_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: FC_GIGA_PORTMAP :: GIGA_PORTMAP [08:00] */
-#define BCHP_SWITCH_CORE_FC_GIGA_PORTMAP_GIGA_PORTMAP_MASK 0x000001ff
-#define BCHP_SWITCH_CORE_FC_GIGA_PORTMAP_GIGA_PORTMAP_SHIFT 0
-#define BCHP_SWITCH_CORE_FC_GIGA_PORTMAP_GIGA_PORTMAP_DEFAULT 0x00000000
-
-/***************************************************************************
- *FC_CONG_PORTMAP_PN_Port_0 - Port N Congested PortMap RegisterNot2Release
- ***************************************************************************/
-/* SWITCH_CORE :: FC_CONG_PORTMAP_PN_Port_0 :: reserved_for_padding0 [31:16] */
-#define BCHP_SWITCH_CORE_FC_CONG_PORTMAP_PN_Port_0_reserved_for_padding0_MASK 0xffff0000
-#define BCHP_SWITCH_CORE_FC_CONG_PORTMAP_PN_Port_0_reserved_for_padding0_SHIFT 16
-
-/* SWITCH_CORE :: FC_CONG_PORTMAP_PN_Port_0 :: CONGEST_PORTMAP [15:00] */
-#define BCHP_SWITCH_CORE_FC_CONG_PORTMAP_PN_Port_0_CONGEST_PORTMAP_MASK 0x0000ffff
-#define BCHP_SWITCH_CORE_FC_CONG_PORTMAP_PN_Port_0_CONGEST_PORTMAP_SHIFT 0
-#define BCHP_SWITCH_CORE_FC_CONG_PORTMAP_PN_Port_0_CONGEST_PORTMAP_DEFAULT 0x00000000
-
-/***************************************************************************
- *FC_CONG_PORTMAP_PN_Port_1 - Port N Congested PortMap RegisterNot2Release
- ***************************************************************************/
-/* SWITCH_CORE :: FC_CONG_PORTMAP_PN_Port_1 :: reserved_for_padding0 [31:16] */
-#define BCHP_SWITCH_CORE_FC_CONG_PORTMAP_PN_Port_1_reserved_for_padding0_MASK 0xffff0000
-#define BCHP_SWITCH_CORE_FC_CONG_PORTMAP_PN_Port_1_reserved_for_padding0_SHIFT 16
-
-/* SWITCH_CORE :: FC_CONG_PORTMAP_PN_Port_1 :: CONGEST_PORTMAP [15:00] */
-#define BCHP_SWITCH_CORE_FC_CONG_PORTMAP_PN_Port_1_CONGEST_PORTMAP_MASK 0x0000ffff
-#define BCHP_SWITCH_CORE_FC_CONG_PORTMAP_PN_Port_1_CONGEST_PORTMAP_SHIFT 0
-#define BCHP_SWITCH_CORE_FC_CONG_PORTMAP_PN_Port_1_CONGEST_PORTMAP_DEFAULT 0x00000000
-
-/***************************************************************************
- *FC_CONG_PORTMAP_PN_Port_2 - Port N Congested PortMap RegisterNot2Release
- ***************************************************************************/
-/* SWITCH_CORE :: FC_CONG_PORTMAP_PN_Port_2 :: reserved_for_padding0 [31:16] */
-#define BCHP_SWITCH_CORE_FC_CONG_PORTMAP_PN_Port_2_reserved_for_padding0_MASK 0xffff0000
-#define BCHP_SWITCH_CORE_FC_CONG_PORTMAP_PN_Port_2_reserved_for_padding0_SHIFT 16
-
-/* SWITCH_CORE :: FC_CONG_PORTMAP_PN_Port_2 :: CONGEST_PORTMAP [15:00] */
-#define BCHP_SWITCH_CORE_FC_CONG_PORTMAP_PN_Port_2_CONGEST_PORTMAP_MASK 0x0000ffff
-#define BCHP_SWITCH_CORE_FC_CONG_PORTMAP_PN_Port_2_CONGEST_PORTMAP_SHIFT 0
-#define BCHP_SWITCH_CORE_FC_CONG_PORTMAP_PN_Port_2_CONGEST_PORTMAP_DEFAULT 0x00000000
-
-/***************************************************************************
- *FC_CONG_PORTMAP_PN_Port_3 - Port N Congested PortMap RegisterNot2Release
- ***************************************************************************/
-/* SWITCH_CORE :: FC_CONG_PORTMAP_PN_Port_3 :: reserved_for_padding0 [31:16] */
-#define BCHP_SWITCH_CORE_FC_CONG_PORTMAP_PN_Port_3_reserved_for_padding0_MASK 0xffff0000
-#define BCHP_SWITCH_CORE_FC_CONG_PORTMAP_PN_Port_3_reserved_for_padding0_SHIFT 16
-
-/* SWITCH_CORE :: FC_CONG_PORTMAP_PN_Port_3 :: CONGEST_PORTMAP [15:00] */
-#define BCHP_SWITCH_CORE_FC_CONG_PORTMAP_PN_Port_3_CONGEST_PORTMAP_MASK 0x0000ffff
-#define BCHP_SWITCH_CORE_FC_CONG_PORTMAP_PN_Port_3_CONGEST_PORTMAP_SHIFT 0
-#define BCHP_SWITCH_CORE_FC_CONG_PORTMAP_PN_Port_3_CONGEST_PORTMAP_DEFAULT 0x00000000
-
-/***************************************************************************
- *FC_CONG_PORTMAP_PN_Port_4 - Port N Congested PortMap RegisterNot2Release
- ***************************************************************************/
-/* SWITCH_CORE :: FC_CONG_PORTMAP_PN_Port_4 :: reserved_for_padding0 [31:16] */
-#define BCHP_SWITCH_CORE_FC_CONG_PORTMAP_PN_Port_4_reserved_for_padding0_MASK 0xffff0000
-#define BCHP_SWITCH_CORE_FC_CONG_PORTMAP_PN_Port_4_reserved_for_padding0_SHIFT 16
-
-/* SWITCH_CORE :: FC_CONG_PORTMAP_PN_Port_4 :: CONGEST_PORTMAP [15:00] */
-#define BCHP_SWITCH_CORE_FC_CONG_PORTMAP_PN_Port_4_CONGEST_PORTMAP_MASK 0x0000ffff
-#define BCHP_SWITCH_CORE_FC_CONG_PORTMAP_PN_Port_4_CONGEST_PORTMAP_SHIFT 0
-#define BCHP_SWITCH_CORE_FC_CONG_PORTMAP_PN_Port_4_CONGEST_PORTMAP_DEFAULT 0x00000000
-
-/***************************************************************************
- *FC_CONG_PORTMAP_PN_Port_5 - Port N Congested PortMap RegisterNot2Release
- ***************************************************************************/
-/* SWITCH_CORE :: FC_CONG_PORTMAP_PN_Port_5 :: reserved_for_padding0 [31:16] */
-#define BCHP_SWITCH_CORE_FC_CONG_PORTMAP_PN_Port_5_reserved_for_padding0_MASK 0xffff0000
-#define BCHP_SWITCH_CORE_FC_CONG_PORTMAP_PN_Port_5_reserved_for_padding0_SHIFT 16
-
-/* SWITCH_CORE :: FC_CONG_PORTMAP_PN_Port_5 :: CONGEST_PORTMAP [15:00] */
-#define BCHP_SWITCH_CORE_FC_CONG_PORTMAP_PN_Port_5_CONGEST_PORTMAP_MASK 0x0000ffff
-#define BCHP_SWITCH_CORE_FC_CONG_PORTMAP_PN_Port_5_CONGEST_PORTMAP_SHIFT 0
-#define BCHP_SWITCH_CORE_FC_CONG_PORTMAP_PN_Port_5_CONGEST_PORTMAP_DEFAULT 0x00000000
-
-/***************************************************************************
- *FC_CONG_PORTMAP_P7 - Port 7 Congested PortMap RegisterNot2Release
- ***************************************************************************/
-/* SWITCH_CORE :: FC_CONG_PORTMAP_P7 :: reserved_for_padding0 [31:16] */
-#define BCHP_SWITCH_CORE_FC_CONG_PORTMAP_P7_reserved_for_padding0_MASK 0xffff0000
-#define BCHP_SWITCH_CORE_FC_CONG_PORTMAP_P7_reserved_for_padding0_SHIFT 16
-
-/* SWITCH_CORE :: FC_CONG_PORTMAP_P7 :: CONGEST_PORTMAP [15:00] */
-#define BCHP_SWITCH_CORE_FC_CONG_PORTMAP_P7_CONGEST_PORTMAP_MASK 0x0000ffff
-#define BCHP_SWITCH_CORE_FC_CONG_PORTMAP_P7_CONGEST_PORTMAP_SHIFT 0
-#define BCHP_SWITCH_CORE_FC_CONG_PORTMAP_P7_CONGEST_PORTMAP_DEFAULT 0x00000000
-
-/***************************************************************************
- *FC_CONG_PORTMAP_P8 - Port 8 Congested PortMap RegisterNot2Release
- ***************************************************************************/
-/* SWITCH_CORE :: FC_CONG_PORTMAP_P8 :: reserved_for_padding0 [31:16] */
-#define BCHP_SWITCH_CORE_FC_CONG_PORTMAP_P8_reserved_for_padding0_MASK 0xffff0000
-#define BCHP_SWITCH_CORE_FC_CONG_PORTMAP_P8_reserved_for_padding0_SHIFT 16
-
-/* SWITCH_CORE :: FC_CONG_PORTMAP_P8 :: CONGEST_PORTMAP [15:00] */
-#define BCHP_SWITCH_CORE_FC_CONG_PORTMAP_P8_CONGEST_PORTMAP_MASK 0x0000ffff
-#define BCHP_SWITCH_CORE_FC_CONG_PORTMAP_P8_CONGEST_PORTMAP_SHIFT 0
-#define BCHP_SWITCH_CORE_FC_CONG_PORTMAP_P8_CONGEST_PORTMAP_DEFAULT 0x00000000
-
-/***************************************************************************
- *FC_PAUSE_HIS - Pause History RegisterNot2Release
- ***************************************************************************/
-/* SWITCH_CORE :: FC_PAUSE_HIS :: reserved_for_padding0 [31:16] */
-#define BCHP_SWITCH_CORE_FC_PAUSE_HIS_reserved_for_padding0_MASK 0xffff0000
-#define BCHP_SWITCH_CORE_FC_PAUSE_HIS_reserved_for_padding0_SHIFT 16
-
-/* SWITCH_CORE :: FC_PAUSE_HIS :: SWITCH_RESV [15:09] */
-#define BCHP_SWITCH_CORE_FC_PAUSE_HIS_SWITCH_RESV_MASK 0x0000fe00
-#define BCHP_SWITCH_CORE_FC_PAUSE_HIS_SWITCH_RESV_SHIFT 9
-#define BCHP_SWITCH_CORE_FC_PAUSE_HIS_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: FC_PAUSE_HIS :: PAUSE_HIS [08:00] */
-#define BCHP_SWITCH_CORE_FC_PAUSE_HIS_PAUSE_HIS_MASK 0x000001ff
-#define BCHP_SWITCH_CORE_FC_PAUSE_HIS_PAUSE_HIS_SHIFT 0
-#define BCHP_SWITCH_CORE_FC_PAUSE_HIS_PAUSE_HIS_DEFAULT 0x00000000
-
-/***************************************************************************
- *FC_TX_QUANTUM_PAUSE_HIS - TX Quantum Pause History RegisterNot2Release
- ***************************************************************************/
-/* SWITCH_CORE :: FC_TX_QUANTUM_PAUSE_HIS :: reserved_for_padding0 [31:16] */
-#define BCHP_SWITCH_CORE_FC_TX_QUANTUM_PAUSE_HIS_reserved_for_padding0_MASK 0xffff0000
-#define BCHP_SWITCH_CORE_FC_TX_QUANTUM_PAUSE_HIS_reserved_for_padding0_SHIFT 16
-
-/* SWITCH_CORE :: FC_TX_QUANTUM_PAUSE_HIS :: SWITCH_RESV [15:09] */
-#define BCHP_SWITCH_CORE_FC_TX_QUANTUM_PAUSE_HIS_SWITCH_RESV_MASK 0x0000fe00
-#define BCHP_SWITCH_CORE_FC_TX_QUANTUM_PAUSE_HIS_SWITCH_RESV_SHIFT 9
-#define BCHP_SWITCH_CORE_FC_TX_QUANTUM_PAUSE_HIS_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: FC_TX_QUANTUM_PAUSE_HIS :: TX_QUANTUM_PAUSE_HIS [08:00] */
-#define BCHP_SWITCH_CORE_FC_TX_QUANTUM_PAUSE_HIS_TX_QUANTUM_PAUSE_HIS_MASK 0x000001ff
-#define BCHP_SWITCH_CORE_FC_TX_QUANTUM_PAUSE_HIS_TX_QUANTUM_PAUSE_HIS_SHIFT 0
-#define BCHP_SWITCH_CORE_FC_TX_QUANTUM_PAUSE_HIS_TX_QUANTUM_PAUSE_HIS_DEFAULT 0x00000000
-
-/***************************************************************************
- *FC_RX_PAUSE_HIS - RX Based Pause History RegisterNot2Release
- ***************************************************************************/
-/* SWITCH_CORE :: FC_RX_PAUSE_HIS :: reserved_for_padding0 [31:16] */
-#define BCHP_SWITCH_CORE_FC_RX_PAUSE_HIS_reserved_for_padding0_MASK 0xffff0000
-#define BCHP_SWITCH_CORE_FC_RX_PAUSE_HIS_reserved_for_padding0_SHIFT 16
-
-/* SWITCH_CORE :: FC_RX_PAUSE_HIS :: SWITCH_RESV [15:09] */
-#define BCHP_SWITCH_CORE_FC_RX_PAUSE_HIS_SWITCH_RESV_MASK 0x0000fe00
-#define BCHP_SWITCH_CORE_FC_RX_PAUSE_HIS_SWITCH_RESV_SHIFT 9
-#define BCHP_SWITCH_CORE_FC_RX_PAUSE_HIS_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: FC_RX_PAUSE_HIS :: RX_PAUSE_HIS [08:00] */
-#define BCHP_SWITCH_CORE_FC_RX_PAUSE_HIS_RX_PAUSE_HIS_MASK 0x000001ff
-#define BCHP_SWITCH_CORE_FC_RX_PAUSE_HIS_RX_PAUSE_HIS_SHIFT 0
-#define BCHP_SWITCH_CORE_FC_RX_PAUSE_HIS_RX_PAUSE_HIS_DEFAULT 0x00000000
-
-/***************************************************************************
- *FC_RXBUF_ERR_HIS - RX Buffer Error History RegisterNot2Release
- ***************************************************************************/
-/* SWITCH_CORE :: FC_RXBUF_ERR_HIS :: reserved_for_padding0 [31:16] */
-#define BCHP_SWITCH_CORE_FC_RXBUF_ERR_HIS_reserved_for_padding0_MASK 0xffff0000
-#define BCHP_SWITCH_CORE_FC_RXBUF_ERR_HIS_reserved_for_padding0_SHIFT 16
-
-/* SWITCH_CORE :: FC_RXBUF_ERR_HIS :: SWITCH_RESV [15:09] */
-#define BCHP_SWITCH_CORE_FC_RXBUF_ERR_HIS_SWITCH_RESV_MASK 0x0000fe00
-#define BCHP_SWITCH_CORE_FC_RXBUF_ERR_HIS_SWITCH_RESV_SHIFT 9
-#define BCHP_SWITCH_CORE_FC_RXBUF_ERR_HIS_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: FC_RXBUF_ERR_HIS :: RXBUF_ERR_HIS [08:00] */
-#define BCHP_SWITCH_CORE_FC_RXBUF_ERR_HIS_RXBUF_ERR_HIS_MASK 0x000001ff
-#define BCHP_SWITCH_CORE_FC_RXBUF_ERR_HIS_RXBUF_ERR_HIS_SHIFT 0
-#define BCHP_SWITCH_CORE_FC_RXBUF_ERR_HIS_RXBUF_ERR_HIS_DEFAULT 0x00000000
-
-/***************************************************************************
- *FC_TXQ_CONG_PORTMAP_PN_Port_0 - Port N TXQ Congested PortMap RegisterNot2Release
- ***************************************************************************/
-/* SWITCH_CORE :: FC_TXQ_CONG_PORTMAP_PN_Port_0 :: reserved_for_padding0 [31:16] */
-#define BCHP_SWITCH_CORE_FC_TXQ_CONG_PORTMAP_PN_Port_0_reserved_for_padding0_MASK 0xffff0000
-#define BCHP_SWITCH_CORE_FC_TXQ_CONG_PORTMAP_PN_Port_0_reserved_for_padding0_SHIFT 16
-
-/* SWITCH_CORE :: FC_TXQ_CONG_PORTMAP_PN_Port_0 :: TXQ_CONGEST_PORTMAP [15:00] */
-#define BCHP_SWITCH_CORE_FC_TXQ_CONG_PORTMAP_PN_Port_0_TXQ_CONGEST_PORTMAP_MASK 0x0000ffff
-#define BCHP_SWITCH_CORE_FC_TXQ_CONG_PORTMAP_PN_Port_0_TXQ_CONGEST_PORTMAP_SHIFT 0
-#define BCHP_SWITCH_CORE_FC_TXQ_CONG_PORTMAP_PN_Port_0_TXQ_CONGEST_PORTMAP_DEFAULT 0x00000000
-
-/***************************************************************************
- *FC_TXQ_CONG_PORTMAP_PN_Port_1 - Port N TXQ Congested PortMap RegisterNot2Release
- ***************************************************************************/
-/* SWITCH_CORE :: FC_TXQ_CONG_PORTMAP_PN_Port_1 :: reserved_for_padding0 [31:16] */
-#define BCHP_SWITCH_CORE_FC_TXQ_CONG_PORTMAP_PN_Port_1_reserved_for_padding0_MASK 0xffff0000
-#define BCHP_SWITCH_CORE_FC_TXQ_CONG_PORTMAP_PN_Port_1_reserved_for_padding0_SHIFT 16
-
-/* SWITCH_CORE :: FC_TXQ_CONG_PORTMAP_PN_Port_1 :: TXQ_CONGEST_PORTMAP [15:00] */
-#define BCHP_SWITCH_CORE_FC_TXQ_CONG_PORTMAP_PN_Port_1_TXQ_CONGEST_PORTMAP_MASK 0x0000ffff
-#define BCHP_SWITCH_CORE_FC_TXQ_CONG_PORTMAP_PN_Port_1_TXQ_CONGEST_PORTMAP_SHIFT 0
-#define BCHP_SWITCH_CORE_FC_TXQ_CONG_PORTMAP_PN_Port_1_TXQ_CONGEST_PORTMAP_DEFAULT 0x00000000
-
-/***************************************************************************
- *FC_TXQ_CONG_PORTMAP_PN_Port_2 - Port N TXQ Congested PortMap RegisterNot2Release
- ***************************************************************************/
-/* SWITCH_CORE :: FC_TXQ_CONG_PORTMAP_PN_Port_2 :: reserved_for_padding0 [31:16] */
-#define BCHP_SWITCH_CORE_FC_TXQ_CONG_PORTMAP_PN_Port_2_reserved_for_padding0_MASK 0xffff0000
-#define BCHP_SWITCH_CORE_FC_TXQ_CONG_PORTMAP_PN_Port_2_reserved_for_padding0_SHIFT 16
-
-/* SWITCH_CORE :: FC_TXQ_CONG_PORTMAP_PN_Port_2 :: TXQ_CONGEST_PORTMAP [15:00] */
-#define BCHP_SWITCH_CORE_FC_TXQ_CONG_PORTMAP_PN_Port_2_TXQ_CONGEST_PORTMAP_MASK 0x0000ffff
-#define BCHP_SWITCH_CORE_FC_TXQ_CONG_PORTMAP_PN_Port_2_TXQ_CONGEST_PORTMAP_SHIFT 0
-#define BCHP_SWITCH_CORE_FC_TXQ_CONG_PORTMAP_PN_Port_2_TXQ_CONGEST_PORTMAP_DEFAULT 0x00000000
-
-/***************************************************************************
- *FC_TXQ_CONG_PORTMAP_PN_Port_3 - Port N TXQ Congested PortMap RegisterNot2Release
- ***************************************************************************/
-/* SWITCH_CORE :: FC_TXQ_CONG_PORTMAP_PN_Port_3 :: reserved_for_padding0 [31:16] */
-#define BCHP_SWITCH_CORE_FC_TXQ_CONG_PORTMAP_PN_Port_3_reserved_for_padding0_MASK 0xffff0000
-#define BCHP_SWITCH_CORE_FC_TXQ_CONG_PORTMAP_PN_Port_3_reserved_for_padding0_SHIFT 16
-
-/* SWITCH_CORE :: FC_TXQ_CONG_PORTMAP_PN_Port_3 :: TXQ_CONGEST_PORTMAP [15:00] */
-#define BCHP_SWITCH_CORE_FC_TXQ_CONG_PORTMAP_PN_Port_3_TXQ_CONGEST_PORTMAP_MASK 0x0000ffff
-#define BCHP_SWITCH_CORE_FC_TXQ_CONG_PORTMAP_PN_Port_3_TXQ_CONGEST_PORTMAP_SHIFT 0
-#define BCHP_SWITCH_CORE_FC_TXQ_CONG_PORTMAP_PN_Port_3_TXQ_CONGEST_PORTMAP_DEFAULT 0x00000000
-
-/***************************************************************************
- *FC_TXQ_CONG_PORTMAP_PN_Port_4 - Port N TXQ Congested PortMap RegisterNot2Release
- ***************************************************************************/
-/* SWITCH_CORE :: FC_TXQ_CONG_PORTMAP_PN_Port_4 :: reserved_for_padding0 [31:16] */
-#define BCHP_SWITCH_CORE_FC_TXQ_CONG_PORTMAP_PN_Port_4_reserved_for_padding0_MASK 0xffff0000
-#define BCHP_SWITCH_CORE_FC_TXQ_CONG_PORTMAP_PN_Port_4_reserved_for_padding0_SHIFT 16
-
-/* SWITCH_CORE :: FC_TXQ_CONG_PORTMAP_PN_Port_4 :: TXQ_CONGEST_PORTMAP [15:00] */
-#define BCHP_SWITCH_CORE_FC_TXQ_CONG_PORTMAP_PN_Port_4_TXQ_CONGEST_PORTMAP_MASK 0x0000ffff
-#define BCHP_SWITCH_CORE_FC_TXQ_CONG_PORTMAP_PN_Port_4_TXQ_CONGEST_PORTMAP_SHIFT 0
-#define BCHP_SWITCH_CORE_FC_TXQ_CONG_PORTMAP_PN_Port_4_TXQ_CONGEST_PORTMAP_DEFAULT 0x00000000
-
-/***************************************************************************
- *FC_TXQ_CONG_PORTMAP_PN_Port_5 - Port N TXQ Congested PortMap RegisterNot2Release
- ***************************************************************************/
-/* SWITCH_CORE :: FC_TXQ_CONG_PORTMAP_PN_Port_5 :: reserved_for_padding0 [31:16] */
-#define BCHP_SWITCH_CORE_FC_TXQ_CONG_PORTMAP_PN_Port_5_reserved_for_padding0_MASK 0xffff0000
-#define BCHP_SWITCH_CORE_FC_TXQ_CONG_PORTMAP_PN_Port_5_reserved_for_padding0_SHIFT 16
-
-/* SWITCH_CORE :: FC_TXQ_CONG_PORTMAP_PN_Port_5 :: TXQ_CONGEST_PORTMAP [15:00] */
-#define BCHP_SWITCH_CORE_FC_TXQ_CONG_PORTMAP_PN_Port_5_TXQ_CONGEST_PORTMAP_MASK 0x0000ffff
-#define BCHP_SWITCH_CORE_FC_TXQ_CONG_PORTMAP_PN_Port_5_TXQ_CONGEST_PORTMAP_SHIFT 0
-#define BCHP_SWITCH_CORE_FC_TXQ_CONG_PORTMAP_PN_Port_5_TXQ_CONGEST_PORTMAP_DEFAULT 0x00000000
-
-/***************************************************************************
- *FC_TXQ_CONG_PORTMAP_P7 - Port 7 TXQ Congested PortMap RegisterNot2Release
- ***************************************************************************/
-/* SWITCH_CORE :: FC_TXQ_CONG_PORTMAP_P7 :: reserved_for_padding0 [31:16] */
-#define BCHP_SWITCH_CORE_FC_TXQ_CONG_PORTMAP_P7_reserved_for_padding0_MASK 0xffff0000
-#define BCHP_SWITCH_CORE_FC_TXQ_CONG_PORTMAP_P7_reserved_for_padding0_SHIFT 16
-
-/* SWITCH_CORE :: FC_TXQ_CONG_PORTMAP_P7 :: TXQ_CONGEST_PORTMAP [15:00] */
-#define BCHP_SWITCH_CORE_FC_TXQ_CONG_PORTMAP_P7_TXQ_CONGEST_PORTMAP_MASK 0x0000ffff
-#define BCHP_SWITCH_CORE_FC_TXQ_CONG_PORTMAP_P7_TXQ_CONGEST_PORTMAP_SHIFT 0
-#define BCHP_SWITCH_CORE_FC_TXQ_CONG_PORTMAP_P7_TXQ_CONGEST_PORTMAP_DEFAULT 0x00000000
-
-/***************************************************************************
- *FC_TXQ_CONG_PORTMAP_P8 - Port 8 TXQ Congested PortMap RegisterNot2Release
- ***************************************************************************/
-/* SWITCH_CORE :: FC_TXQ_CONG_PORTMAP_P8 :: reserved_for_padding0 [31:16] */
-#define BCHP_SWITCH_CORE_FC_TXQ_CONG_PORTMAP_P8_reserved_for_padding0_MASK 0xffff0000
-#define BCHP_SWITCH_CORE_FC_TXQ_CONG_PORTMAP_P8_reserved_for_padding0_SHIFT 16
-
-/* SWITCH_CORE :: FC_TXQ_CONG_PORTMAP_P8 :: TXQ_CONGEST_PORTMAP [15:00] */
-#define BCHP_SWITCH_CORE_FC_TXQ_CONG_PORTMAP_P8_TXQ_CONGEST_PORTMAP_MASK 0x0000ffff
-#define BCHP_SWITCH_CORE_FC_TXQ_CONG_PORTMAP_P8_TXQ_CONGEST_PORTMAP_SHIFT 0
-#define BCHP_SWITCH_CORE_FC_TXQ_CONG_PORTMAP_P8_TXQ_CONGEST_PORTMAP_DEFAULT 0x00000000
-
-/***************************************************************************
- *FC_TOTAL_CONG_PORTMAP_PN_Port_0 - Port N Total Congested PortMap RegisterNot2Release
- ***************************************************************************/
-/* SWITCH_CORE :: FC_TOTAL_CONG_PORTMAP_PN_Port_0 :: reserved_for_padding0 [31:16] */
-#define BCHP_SWITCH_CORE_FC_TOTAL_CONG_PORTMAP_PN_Port_0_reserved_for_padding0_MASK 0xffff0000
-#define BCHP_SWITCH_CORE_FC_TOTAL_CONG_PORTMAP_PN_Port_0_reserved_for_padding0_SHIFT 16
-
-/* SWITCH_CORE :: FC_TOTAL_CONG_PORTMAP_PN_Port_0 :: TOTAL_CONGEST_PORTMAP [15:00] */
-#define BCHP_SWITCH_CORE_FC_TOTAL_CONG_PORTMAP_PN_Port_0_TOTAL_CONGEST_PORTMAP_MASK 0x0000ffff
-#define BCHP_SWITCH_CORE_FC_TOTAL_CONG_PORTMAP_PN_Port_0_TOTAL_CONGEST_PORTMAP_SHIFT 0
-#define BCHP_SWITCH_CORE_FC_TOTAL_CONG_PORTMAP_PN_Port_0_TOTAL_CONGEST_PORTMAP_DEFAULT 0x00000000
-
-/***************************************************************************
- *FC_TOTAL_CONG_PORTMAP_PN_Port_1 - Port N Total Congested PortMap RegisterNot2Release
- ***************************************************************************/
-/* SWITCH_CORE :: FC_TOTAL_CONG_PORTMAP_PN_Port_1 :: reserved_for_padding0 [31:16] */
-#define BCHP_SWITCH_CORE_FC_TOTAL_CONG_PORTMAP_PN_Port_1_reserved_for_padding0_MASK 0xffff0000
-#define BCHP_SWITCH_CORE_FC_TOTAL_CONG_PORTMAP_PN_Port_1_reserved_for_padding0_SHIFT 16
-
-/* SWITCH_CORE :: FC_TOTAL_CONG_PORTMAP_PN_Port_1 :: TOTAL_CONGEST_PORTMAP [15:00] */
-#define BCHP_SWITCH_CORE_FC_TOTAL_CONG_PORTMAP_PN_Port_1_TOTAL_CONGEST_PORTMAP_MASK 0x0000ffff
-#define BCHP_SWITCH_CORE_FC_TOTAL_CONG_PORTMAP_PN_Port_1_TOTAL_CONGEST_PORTMAP_SHIFT 0
-#define BCHP_SWITCH_CORE_FC_TOTAL_CONG_PORTMAP_PN_Port_1_TOTAL_CONGEST_PORTMAP_DEFAULT 0x00000000
-
-/***************************************************************************
- *FC_TOTAL_CONG_PORTMAP_PN_Port_2 - Port N Total Congested PortMap RegisterNot2Release
- ***************************************************************************/
-/* SWITCH_CORE :: FC_TOTAL_CONG_PORTMAP_PN_Port_2 :: reserved_for_padding0 [31:16] */
-#define BCHP_SWITCH_CORE_FC_TOTAL_CONG_PORTMAP_PN_Port_2_reserved_for_padding0_MASK 0xffff0000
-#define BCHP_SWITCH_CORE_FC_TOTAL_CONG_PORTMAP_PN_Port_2_reserved_for_padding0_SHIFT 16
-
-/* SWITCH_CORE :: FC_TOTAL_CONG_PORTMAP_PN_Port_2 :: TOTAL_CONGEST_PORTMAP [15:00] */
-#define BCHP_SWITCH_CORE_FC_TOTAL_CONG_PORTMAP_PN_Port_2_TOTAL_CONGEST_PORTMAP_MASK 0x0000ffff
-#define BCHP_SWITCH_CORE_FC_TOTAL_CONG_PORTMAP_PN_Port_2_TOTAL_CONGEST_PORTMAP_SHIFT 0
-#define BCHP_SWITCH_CORE_FC_TOTAL_CONG_PORTMAP_PN_Port_2_TOTAL_CONGEST_PORTMAP_DEFAULT 0x00000000
-
-/***************************************************************************
- *FC_TOTAL_CONG_PORTMAP_PN_Port_3 - Port N Total Congested PortMap RegisterNot2Release
- ***************************************************************************/
-/* SWITCH_CORE :: FC_TOTAL_CONG_PORTMAP_PN_Port_3 :: reserved_for_padding0 [31:16] */
-#define BCHP_SWITCH_CORE_FC_TOTAL_CONG_PORTMAP_PN_Port_3_reserved_for_padding0_MASK 0xffff0000
-#define BCHP_SWITCH_CORE_FC_TOTAL_CONG_PORTMAP_PN_Port_3_reserved_for_padding0_SHIFT 16
-
-/* SWITCH_CORE :: FC_TOTAL_CONG_PORTMAP_PN_Port_3 :: TOTAL_CONGEST_PORTMAP [15:00] */
-#define BCHP_SWITCH_CORE_FC_TOTAL_CONG_PORTMAP_PN_Port_3_TOTAL_CONGEST_PORTMAP_MASK 0x0000ffff
-#define BCHP_SWITCH_CORE_FC_TOTAL_CONG_PORTMAP_PN_Port_3_TOTAL_CONGEST_PORTMAP_SHIFT 0
-#define BCHP_SWITCH_CORE_FC_TOTAL_CONG_PORTMAP_PN_Port_3_TOTAL_CONGEST_PORTMAP_DEFAULT 0x00000000
-
-/***************************************************************************
- *FC_TOTAL_CONG_PORTMAP_PN_Port_4 - Port N Total Congested PortMap RegisterNot2Release
- ***************************************************************************/
-/* SWITCH_CORE :: FC_TOTAL_CONG_PORTMAP_PN_Port_4 :: reserved_for_padding0 [31:16] */
-#define BCHP_SWITCH_CORE_FC_TOTAL_CONG_PORTMAP_PN_Port_4_reserved_for_padding0_MASK 0xffff0000
-#define BCHP_SWITCH_CORE_FC_TOTAL_CONG_PORTMAP_PN_Port_4_reserved_for_padding0_SHIFT 16
-
-/* SWITCH_CORE :: FC_TOTAL_CONG_PORTMAP_PN_Port_4 :: TOTAL_CONGEST_PORTMAP [15:00] */
-#define BCHP_SWITCH_CORE_FC_TOTAL_CONG_PORTMAP_PN_Port_4_TOTAL_CONGEST_PORTMAP_MASK 0x0000ffff
-#define BCHP_SWITCH_CORE_FC_TOTAL_CONG_PORTMAP_PN_Port_4_TOTAL_CONGEST_PORTMAP_SHIFT 0
-#define BCHP_SWITCH_CORE_FC_TOTAL_CONG_PORTMAP_PN_Port_4_TOTAL_CONGEST_PORTMAP_DEFAULT 0x00000000
-
-/***************************************************************************
- *FC_TOTAL_CONG_PORTMAP_PN_Port_5 - Port N Total Congested PortMap RegisterNot2Release
- ***************************************************************************/
-/* SWITCH_CORE :: FC_TOTAL_CONG_PORTMAP_PN_Port_5 :: reserved_for_padding0 [31:16] */
-#define BCHP_SWITCH_CORE_FC_TOTAL_CONG_PORTMAP_PN_Port_5_reserved_for_padding0_MASK 0xffff0000
-#define BCHP_SWITCH_CORE_FC_TOTAL_CONG_PORTMAP_PN_Port_5_reserved_for_padding0_SHIFT 16
-
-/* SWITCH_CORE :: FC_TOTAL_CONG_PORTMAP_PN_Port_5 :: TOTAL_CONGEST_PORTMAP [15:00] */
-#define BCHP_SWITCH_CORE_FC_TOTAL_CONG_PORTMAP_PN_Port_5_TOTAL_CONGEST_PORTMAP_MASK 0x0000ffff
-#define BCHP_SWITCH_CORE_FC_TOTAL_CONG_PORTMAP_PN_Port_5_TOTAL_CONGEST_PORTMAP_SHIFT 0
-#define BCHP_SWITCH_CORE_FC_TOTAL_CONG_PORTMAP_PN_Port_5_TOTAL_CONGEST_PORTMAP_DEFAULT 0x00000000
-
-/***************************************************************************
- *FC_TOTAL_CONG_PORTMAP_P7 - Port 7 Total Congested PortMap RegisterNot2Release
- ***************************************************************************/
-/* SWITCH_CORE :: FC_TOTAL_CONG_PORTMAP_P7 :: reserved_for_padding0 [31:16] */
-#define BCHP_SWITCH_CORE_FC_TOTAL_CONG_PORTMAP_P7_reserved_for_padding0_MASK 0xffff0000
-#define BCHP_SWITCH_CORE_FC_TOTAL_CONG_PORTMAP_P7_reserved_for_padding0_SHIFT 16
-
-/* SWITCH_CORE :: FC_TOTAL_CONG_PORTMAP_P7 :: TOTAL_CONGEST_PORTMAP [15:00] */
-#define BCHP_SWITCH_CORE_FC_TOTAL_CONG_PORTMAP_P7_TOTAL_CONGEST_PORTMAP_MASK 0x0000ffff
-#define BCHP_SWITCH_CORE_FC_TOTAL_CONG_PORTMAP_P7_TOTAL_CONGEST_PORTMAP_SHIFT 0
-#define BCHP_SWITCH_CORE_FC_TOTAL_CONG_PORTMAP_P7_TOTAL_CONGEST_PORTMAP_DEFAULT 0x00000000
-
-/***************************************************************************
- *FC_TOTAL_CONG_PORTMAP_P8 - Port 8 Total Congested PortMap RegisterNot2Release
- ***************************************************************************/
-/* SWITCH_CORE :: FC_TOTAL_CONG_PORTMAP_P8 :: reserved_for_padding0 [31:16] */
-#define BCHP_SWITCH_CORE_FC_TOTAL_CONG_PORTMAP_P8_reserved_for_padding0_MASK 0xffff0000
-#define BCHP_SWITCH_CORE_FC_TOTAL_CONG_PORTMAP_P8_reserved_for_padding0_SHIFT 16
-
-/* SWITCH_CORE :: FC_TOTAL_CONG_PORTMAP_P8 :: TOTAL_CONGEST_PORTMAP [15:00] */
-#define BCHP_SWITCH_CORE_FC_TOTAL_CONG_PORTMAP_P8_TOTAL_CONGEST_PORTMAP_MASK 0x0000ffff
-#define BCHP_SWITCH_CORE_FC_TOTAL_CONG_PORTMAP_P8_TOTAL_CONGEST_PORTMAP_SHIFT 0
-#define BCHP_SWITCH_CORE_FC_TOTAL_CONG_PORTMAP_P8_TOTAL_CONGEST_PORTMAP_DEFAULT 0x00000000
-
-/***************************************************************************
- *FC_LAN_TXQ_THD_RSV_QN_Port_0 - LAN Port Queue N Reserved Threshold RegisterNot2Release
- ***************************************************************************/
-/* SWITCH_CORE :: FC_LAN_TXQ_THD_RSV_QN_Port_0 :: reserved_for_padding0 [31:16] */
-#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_RSV_QN_Port_0_reserved_for_padding0_MASK 0xffff0000
-#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_RSV_QN_Port_0_reserved_for_padding0_SHIFT 16
-
-/* SWITCH_CORE :: FC_LAN_TXQ_THD_RSV_QN_Port_0 :: SWITCH_RESV [15:11] */
-#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_RSV_QN_Port_0_SWITCH_RESV_MASK 0x0000f800
-#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_RSV_QN_Port_0_SWITCH_RESV_SHIFT 11
-#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_RSV_QN_Port_0_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: FC_LAN_TXQ_THD_RSV_QN_Port_0 :: TXQ_RSV_THD [10:00] */
-#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_RSV_QN_Port_0_TXQ_RSV_THD_MASK 0x000007ff
-#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_RSV_QN_Port_0_TXQ_RSV_THD_SHIFT 0
-#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_RSV_QN_Port_0_TXQ_RSV_THD_DEFAULT 0x00000018
-
-/***************************************************************************
- *FC_LAN_TXQ_THD_RSV_QN_Port_1 - LAN Port Queue N Reserved Threshold RegisterNot2Release
- ***************************************************************************/
-/* SWITCH_CORE :: FC_LAN_TXQ_THD_RSV_QN_Port_1 :: reserved_for_padding0 [31:16] */
-#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_RSV_QN_Port_1_reserved_for_padding0_MASK 0xffff0000
-#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_RSV_QN_Port_1_reserved_for_padding0_SHIFT 16
-
-/* SWITCH_CORE :: FC_LAN_TXQ_THD_RSV_QN_Port_1 :: SWITCH_RESV [15:11] */
-#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_RSV_QN_Port_1_SWITCH_RESV_MASK 0x0000f800
-#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_RSV_QN_Port_1_SWITCH_RESV_SHIFT 11
-#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_RSV_QN_Port_1_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: FC_LAN_TXQ_THD_RSV_QN_Port_1 :: TXQ_RSV_THD [10:00] */
-#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_RSV_QN_Port_1_TXQ_RSV_THD_MASK 0x000007ff
-#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_RSV_QN_Port_1_TXQ_RSV_THD_SHIFT 0
-#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_RSV_QN_Port_1_TXQ_RSV_THD_DEFAULT 0x00000018
-
-/***************************************************************************
- *FC_LAN_TXQ_THD_RSV_QN_Port_2 - LAN Port Queue N Reserved Threshold RegisterNot2Release
- ***************************************************************************/
-/* SWITCH_CORE :: FC_LAN_TXQ_THD_RSV_QN_Port_2 :: reserved_for_padding0 [31:16] */
-#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_RSV_QN_Port_2_reserved_for_padding0_MASK 0xffff0000
-#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_RSV_QN_Port_2_reserved_for_padding0_SHIFT 16
-
-/* SWITCH_CORE :: FC_LAN_TXQ_THD_RSV_QN_Port_2 :: SWITCH_RESV [15:11] */
-#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_RSV_QN_Port_2_SWITCH_RESV_MASK 0x0000f800
-#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_RSV_QN_Port_2_SWITCH_RESV_SHIFT 11
-#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_RSV_QN_Port_2_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: FC_LAN_TXQ_THD_RSV_QN_Port_2 :: TXQ_RSV_THD [10:00] */
-#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_RSV_QN_Port_2_TXQ_RSV_THD_MASK 0x000007ff
-#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_RSV_QN_Port_2_TXQ_RSV_THD_SHIFT 0
-#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_RSV_QN_Port_2_TXQ_RSV_THD_DEFAULT 0x00000018
-
-/***************************************************************************
- *FC_LAN_TXQ_THD_RSV_QN_Port_3 - LAN Port Queue N Reserved Threshold RegisterNot2Release
- ***************************************************************************/
-/* SWITCH_CORE :: FC_LAN_TXQ_THD_RSV_QN_Port_3 :: reserved_for_padding0 [31:16] */
-#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_RSV_QN_Port_3_reserved_for_padding0_MASK 0xffff0000
-#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_RSV_QN_Port_3_reserved_for_padding0_SHIFT 16
-
-/* SWITCH_CORE :: FC_LAN_TXQ_THD_RSV_QN_Port_3 :: SWITCH_RESV [15:11] */
-#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_RSV_QN_Port_3_SWITCH_RESV_MASK 0x0000f800
-#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_RSV_QN_Port_3_SWITCH_RESV_SHIFT 11
-#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_RSV_QN_Port_3_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: FC_LAN_TXQ_THD_RSV_QN_Port_3 :: TXQ_RSV_THD [10:00] */
-#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_RSV_QN_Port_3_TXQ_RSV_THD_MASK 0x000007ff
-#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_RSV_QN_Port_3_TXQ_RSV_THD_SHIFT 0
-#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_RSV_QN_Port_3_TXQ_RSV_THD_DEFAULT 0x00000018
-
-/***************************************************************************
- *FC_LAN_TXQ_THD_RSV_QN_Port_4 - LAN Port Queue N Reserved Threshold RegisterNot2Release
- ***************************************************************************/
-/* SWITCH_CORE :: FC_LAN_TXQ_THD_RSV_QN_Port_4 :: reserved_for_padding0 [31:16] */
-#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_RSV_QN_Port_4_reserved_for_padding0_MASK 0xffff0000
-#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_RSV_QN_Port_4_reserved_for_padding0_SHIFT 16
-
-/* SWITCH_CORE :: FC_LAN_TXQ_THD_RSV_QN_Port_4 :: SWITCH_RESV [15:11] */
-#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_RSV_QN_Port_4_SWITCH_RESV_MASK 0x0000f800
-#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_RSV_QN_Port_4_SWITCH_RESV_SHIFT 11
-#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_RSV_QN_Port_4_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: FC_LAN_TXQ_THD_RSV_QN_Port_4 :: TXQ_RSV_THD [10:00] */
-#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_RSV_QN_Port_4_TXQ_RSV_THD_MASK 0x000007ff
-#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_RSV_QN_Port_4_TXQ_RSV_THD_SHIFT 0
-#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_RSV_QN_Port_4_TXQ_RSV_THD_DEFAULT 0x00000018
-
-/***************************************************************************
- *FC_LAN_TXQ_THD_RSV_QN_Port_5 - LAN Port Queue N Reserved Threshold RegisterNot2Release
- ***************************************************************************/
-/* SWITCH_CORE :: FC_LAN_TXQ_THD_RSV_QN_Port_5 :: reserved_for_padding0 [31:16] */
-#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_RSV_QN_Port_5_reserved_for_padding0_MASK 0xffff0000
-#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_RSV_QN_Port_5_reserved_for_padding0_SHIFT 16
-
-/* SWITCH_CORE :: FC_LAN_TXQ_THD_RSV_QN_Port_5 :: SWITCH_RESV [15:11] */
-#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_RSV_QN_Port_5_SWITCH_RESV_MASK 0x0000f800
-#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_RSV_QN_Port_5_SWITCH_RESV_SHIFT 11
-#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_RSV_QN_Port_5_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: FC_LAN_TXQ_THD_RSV_QN_Port_5 :: TXQ_RSV_THD [10:00] */
-#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_RSV_QN_Port_5_TXQ_RSV_THD_MASK 0x000007ff
-#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_RSV_QN_Port_5_TXQ_RSV_THD_SHIFT 0
-#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_RSV_QN_Port_5_TXQ_RSV_THD_DEFAULT 0x00000018
-
-/***************************************************************************
- *FC_LAN_TXQ_THD_RSV_QN_Port_6 - LAN Port Queue N Reserved Threshold RegisterNot2Release
- ***************************************************************************/
-/* SWITCH_CORE :: FC_LAN_TXQ_THD_RSV_QN_Port_6 :: reserved_for_padding0 [31:16] */
-#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_RSV_QN_Port_6_reserved_for_padding0_MASK 0xffff0000
-#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_RSV_QN_Port_6_reserved_for_padding0_SHIFT 16
-
-/* SWITCH_CORE :: FC_LAN_TXQ_THD_RSV_QN_Port_6 :: SWITCH_RESV [15:11] */
-#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_RSV_QN_Port_6_SWITCH_RESV_MASK 0x0000f800
-#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_RSV_QN_Port_6_SWITCH_RESV_SHIFT 11
-#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_RSV_QN_Port_6_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: FC_LAN_TXQ_THD_RSV_QN_Port_6 :: TXQ_RSV_THD [10:00] */
-#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_RSV_QN_Port_6_TXQ_RSV_THD_MASK 0x000007ff
-#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_RSV_QN_Port_6_TXQ_RSV_THD_SHIFT 0
-#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_RSV_QN_Port_6_TXQ_RSV_THD_DEFAULT 0x00000018
-
-/***************************************************************************
- *FC_LAN_TXQ_THD_RSV_QN_Port_7 - LAN Port Queue N Reserved Threshold RegisterNot2Release
- ***************************************************************************/
-/* SWITCH_CORE :: FC_LAN_TXQ_THD_RSV_QN_Port_7 :: reserved_for_padding0 [31:16] */
-#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_RSV_QN_Port_7_reserved_for_padding0_MASK 0xffff0000
-#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_RSV_QN_Port_7_reserved_for_padding0_SHIFT 16
-
-/* SWITCH_CORE :: FC_LAN_TXQ_THD_RSV_QN_Port_7 :: SWITCH_RESV [15:11] */
-#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_RSV_QN_Port_7_SWITCH_RESV_MASK 0x0000f800
-#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_RSV_QN_Port_7_SWITCH_RESV_SHIFT 11
-#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_RSV_QN_Port_7_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: FC_LAN_TXQ_THD_RSV_QN_Port_7 :: TXQ_RSV_THD [10:00] */
-#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_RSV_QN_Port_7_TXQ_RSV_THD_MASK 0x000007ff
-#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_RSV_QN_Port_7_TXQ_RSV_THD_SHIFT 0
-#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_RSV_QN_Port_7_TXQ_RSV_THD_DEFAULT 0x00000018
-
-/***************************************************************************
- *FC_LAN_TXQ_THD_HYST_QN_Port_0 - LAN Port Queue N Hysteresis Threshold RegisterNot2Release
- ***************************************************************************/
-/* SWITCH_CORE :: FC_LAN_TXQ_THD_HYST_QN_Port_0 :: reserved_for_padding0 [31:16] */
-#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_HYST_QN_Port_0_reserved_for_padding0_MASK 0xffff0000
-#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_HYST_QN_Port_0_reserved_for_padding0_SHIFT 16
-
-/* SWITCH_CORE :: FC_LAN_TXQ_THD_HYST_QN_Port_0 :: SWITCH_RESV [15:11] */
-#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_HYST_QN_Port_0_SWITCH_RESV_MASK 0x0000f800
-#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_HYST_QN_Port_0_SWITCH_RESV_SHIFT 11
-#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_HYST_QN_Port_0_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: FC_LAN_TXQ_THD_HYST_QN_Port_0 :: TXQ_HYST_THD [10:00] */
-#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_HYST_QN_Port_0_TXQ_HYST_THD_MASK 0x000007ff
-#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_HYST_QN_Port_0_TXQ_HYST_THD_SHIFT 0
-#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_HYST_QN_Port_0_TXQ_HYST_THD_DEFAULT 0x0000004b
-
-/***************************************************************************
- *FC_LAN_TXQ_THD_HYST_QN_Port_1 - LAN Port Queue N Hysteresis Threshold RegisterNot2Release
- ***************************************************************************/
-/* SWITCH_CORE :: FC_LAN_TXQ_THD_HYST_QN_Port_1 :: reserved_for_padding0 [31:16] */
-#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_HYST_QN_Port_1_reserved_for_padding0_MASK 0xffff0000
-#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_HYST_QN_Port_1_reserved_for_padding0_SHIFT 16
-
-/* SWITCH_CORE :: FC_LAN_TXQ_THD_HYST_QN_Port_1 :: SWITCH_RESV [15:11] */
-#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_HYST_QN_Port_1_SWITCH_RESV_MASK 0x0000f800
-#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_HYST_QN_Port_1_SWITCH_RESV_SHIFT 11
-#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_HYST_QN_Port_1_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: FC_LAN_TXQ_THD_HYST_QN_Port_1 :: TXQ_HYST_THD [10:00] */
-#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_HYST_QN_Port_1_TXQ_HYST_THD_MASK 0x000007ff
-#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_HYST_QN_Port_1_TXQ_HYST_THD_SHIFT 0
-#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_HYST_QN_Port_1_TXQ_HYST_THD_DEFAULT 0x0000004f
-
-/***************************************************************************
- *FC_LAN_TXQ_THD_HYST_QN_Port_2 - LAN Port Queue N Hysteresis Threshold RegisterNot2Release
- ***************************************************************************/
-/* SWITCH_CORE :: FC_LAN_TXQ_THD_HYST_QN_Port_2 :: reserved_for_padding0 [31:16] */
-#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_HYST_QN_Port_2_reserved_for_padding0_MASK 0xffff0000
-#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_HYST_QN_Port_2_reserved_for_padding0_SHIFT 16
-
-/* SWITCH_CORE :: FC_LAN_TXQ_THD_HYST_QN_Port_2 :: SWITCH_RESV [15:11] */
-#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_HYST_QN_Port_2_SWITCH_RESV_MASK 0x0000f800
-#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_HYST_QN_Port_2_SWITCH_RESV_SHIFT 11
-#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_HYST_QN_Port_2_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: FC_LAN_TXQ_THD_HYST_QN_Port_2 :: TXQ_HYST_THD [10:00] */
-#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_HYST_QN_Port_2_TXQ_HYST_THD_MASK 0x000007ff
-#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_HYST_QN_Port_2_TXQ_HYST_THD_SHIFT 0
-#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_HYST_QN_Port_2_TXQ_HYST_THD_DEFAULT 0x00000053
-
-/***************************************************************************
- *FC_LAN_TXQ_THD_HYST_QN_Port_3 - LAN Port Queue N Hysteresis Threshold RegisterNot2Release
- ***************************************************************************/
-/* SWITCH_CORE :: FC_LAN_TXQ_THD_HYST_QN_Port_3 :: reserved_for_padding0 [31:16] */
-#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_HYST_QN_Port_3_reserved_for_padding0_MASK 0xffff0000
-#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_HYST_QN_Port_3_reserved_for_padding0_SHIFT 16
-
-/* SWITCH_CORE :: FC_LAN_TXQ_THD_HYST_QN_Port_3 :: SWITCH_RESV [15:11] */
-#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_HYST_QN_Port_3_SWITCH_RESV_MASK 0x0000f800
-#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_HYST_QN_Port_3_SWITCH_RESV_SHIFT 11
-#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_HYST_QN_Port_3_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: FC_LAN_TXQ_THD_HYST_QN_Port_3 :: TXQ_HYST_THD [10:00] */
-#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_HYST_QN_Port_3_TXQ_HYST_THD_MASK 0x000007ff
-#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_HYST_QN_Port_3_TXQ_HYST_THD_SHIFT 0
-#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_HYST_QN_Port_3_TXQ_HYST_THD_DEFAULT 0x00000057
-
-/***************************************************************************
- *FC_LAN_TXQ_THD_HYST_QN_Port_4 - LAN Port Queue N Hysteresis Threshold RegisterNot2Release
- ***************************************************************************/
-/* SWITCH_CORE :: FC_LAN_TXQ_THD_HYST_QN_Port_4 :: reserved_for_padding0 [31:16] */
-#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_HYST_QN_Port_4_reserved_for_padding0_MASK 0xffff0000
-#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_HYST_QN_Port_4_reserved_for_padding0_SHIFT 16
-
-/* SWITCH_CORE :: FC_LAN_TXQ_THD_HYST_QN_Port_4 :: SWITCH_RESV [15:11] */
-#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_HYST_QN_Port_4_SWITCH_RESV_MASK 0x0000f800
-#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_HYST_QN_Port_4_SWITCH_RESV_SHIFT 11
-#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_HYST_QN_Port_4_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: FC_LAN_TXQ_THD_HYST_QN_Port_4 :: TXQ_HYST_THD [10:00] */
-#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_HYST_QN_Port_4_TXQ_HYST_THD_MASK 0x000007ff
-#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_HYST_QN_Port_4_TXQ_HYST_THD_SHIFT 0
-#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_HYST_QN_Port_4_TXQ_HYST_THD_DEFAULT 0x0000005b
-
-/***************************************************************************
- *FC_LAN_TXQ_THD_HYST_QN_Port_5 - LAN Port Queue N Hysteresis Threshold RegisterNot2Release
- ***************************************************************************/
-/* SWITCH_CORE :: FC_LAN_TXQ_THD_HYST_QN_Port_5 :: reserved_for_padding0 [31:16] */
-#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_HYST_QN_Port_5_reserved_for_padding0_MASK 0xffff0000
-#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_HYST_QN_Port_5_reserved_for_padding0_SHIFT 16
-
-/* SWITCH_CORE :: FC_LAN_TXQ_THD_HYST_QN_Port_5 :: SWITCH_RESV [15:11] */
-#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_HYST_QN_Port_5_SWITCH_RESV_MASK 0x0000f800
-#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_HYST_QN_Port_5_SWITCH_RESV_SHIFT 11
-#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_HYST_QN_Port_5_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: FC_LAN_TXQ_THD_HYST_QN_Port_5 :: TXQ_HYST_THD [10:00] */
-#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_HYST_QN_Port_5_TXQ_HYST_THD_MASK 0x000007ff
-#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_HYST_QN_Port_5_TXQ_HYST_THD_SHIFT 0
-#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_HYST_QN_Port_5_TXQ_HYST_THD_DEFAULT 0x0000005f
-
-/***************************************************************************
- *FC_LAN_TXQ_THD_HYST_QN_Port_6 - LAN Port Queue N Hysteresis Threshold RegisterNot2Release
- ***************************************************************************/
-/* SWITCH_CORE :: FC_LAN_TXQ_THD_HYST_QN_Port_6 :: reserved_for_padding0 [31:16] */
-#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_HYST_QN_Port_6_reserved_for_padding0_MASK 0xffff0000
-#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_HYST_QN_Port_6_reserved_for_padding0_SHIFT 16
-
-/* SWITCH_CORE :: FC_LAN_TXQ_THD_HYST_QN_Port_6 :: SWITCH_RESV [15:11] */
-#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_HYST_QN_Port_6_SWITCH_RESV_MASK 0x0000f800
-#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_HYST_QN_Port_6_SWITCH_RESV_SHIFT 11
-#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_HYST_QN_Port_6_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: FC_LAN_TXQ_THD_HYST_QN_Port_6 :: TXQ_HYST_THD [10:00] */
-#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_HYST_QN_Port_6_TXQ_HYST_THD_MASK 0x000007ff
-#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_HYST_QN_Port_6_TXQ_HYST_THD_SHIFT 0
-#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_HYST_QN_Port_6_TXQ_HYST_THD_DEFAULT 0x00000063
-
-/***************************************************************************
- *FC_LAN_TXQ_THD_HYST_QN_Port_7 - LAN Port Queue N Hysteresis Threshold RegisterNot2Release
- ***************************************************************************/
-/* SWITCH_CORE :: FC_LAN_TXQ_THD_HYST_QN_Port_7 :: reserved_for_padding0 [31:16] */
-#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_HYST_QN_Port_7_reserved_for_padding0_MASK 0xffff0000
-#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_HYST_QN_Port_7_reserved_for_padding0_SHIFT 16
-
-/* SWITCH_CORE :: FC_LAN_TXQ_THD_HYST_QN_Port_7 :: SWITCH_RESV [15:11] */
-#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_HYST_QN_Port_7_SWITCH_RESV_MASK 0x0000f800
-#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_HYST_QN_Port_7_SWITCH_RESV_SHIFT 11
-#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_HYST_QN_Port_7_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: FC_LAN_TXQ_THD_HYST_QN_Port_7 :: TXQ_HYST_THD [10:00] */
-#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_HYST_QN_Port_7_TXQ_HYST_THD_MASK 0x000007ff
-#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_HYST_QN_Port_7_TXQ_HYST_THD_SHIFT 0
-#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_HYST_QN_Port_7_TXQ_HYST_THD_DEFAULT 0x00000067
-
-/***************************************************************************
- *FC_LAN_TXQ_THD_PAUSE_QN_Port_0 - LAN Port Queue N Pause Threshold RegisterNot2Release
- ***************************************************************************/
-/* SWITCH_CORE :: FC_LAN_TXQ_THD_PAUSE_QN_Port_0 :: reserved_for_padding0 [31:16] */
-#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_PAUSE_QN_Port_0_reserved_for_padding0_MASK 0xffff0000
-#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_PAUSE_QN_Port_0_reserved_for_padding0_SHIFT 16
-
-/* SWITCH_CORE :: FC_LAN_TXQ_THD_PAUSE_QN_Port_0 :: SWITCH_RESV [15:11] */
-#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_PAUSE_QN_Port_0_SWITCH_RESV_MASK 0x0000f800
-#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_PAUSE_QN_Port_0_SWITCH_RESV_SHIFT 11
-#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_PAUSE_QN_Port_0_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: FC_LAN_TXQ_THD_PAUSE_QN_Port_0 :: TXQ_PAUSE_THD [10:00] */
-#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_PAUSE_QN_Port_0_TXQ_PAUSE_THD_MASK 0x000007ff
-#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_PAUSE_QN_Port_0_TXQ_PAUSE_THD_SHIFT 0
-#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_PAUSE_QN_Port_0_TXQ_PAUSE_THD_DEFAULT 0x00000097
-
-/***************************************************************************
- *FC_LAN_TXQ_THD_PAUSE_QN_Port_1 - LAN Port Queue N Pause Threshold RegisterNot2Release
- ***************************************************************************/
-/* SWITCH_CORE :: FC_LAN_TXQ_THD_PAUSE_QN_Port_1 :: reserved_for_padding0 [31:16] */
-#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_PAUSE_QN_Port_1_reserved_for_padding0_MASK 0xffff0000
-#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_PAUSE_QN_Port_1_reserved_for_padding0_SHIFT 16
-
-/* SWITCH_CORE :: FC_LAN_TXQ_THD_PAUSE_QN_Port_1 :: SWITCH_RESV [15:11] */
-#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_PAUSE_QN_Port_1_SWITCH_RESV_MASK 0x0000f800
-#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_PAUSE_QN_Port_1_SWITCH_RESV_SHIFT 11
-#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_PAUSE_QN_Port_1_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: FC_LAN_TXQ_THD_PAUSE_QN_Port_1 :: TXQ_PAUSE_THD [10:00] */
-#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_PAUSE_QN_Port_1_TXQ_PAUSE_THD_MASK 0x000007ff
-#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_PAUSE_QN_Port_1_TXQ_PAUSE_THD_SHIFT 0
-#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_PAUSE_QN_Port_1_TXQ_PAUSE_THD_DEFAULT 0x0000009f
-
-/***************************************************************************
- *FC_LAN_TXQ_THD_PAUSE_QN_Port_2 - LAN Port Queue N Pause Threshold RegisterNot2Release
- ***************************************************************************/
-/* SWITCH_CORE :: FC_LAN_TXQ_THD_PAUSE_QN_Port_2 :: reserved_for_padding0 [31:16] */
-#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_PAUSE_QN_Port_2_reserved_for_padding0_MASK 0xffff0000
-#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_PAUSE_QN_Port_2_reserved_for_padding0_SHIFT 16
-
-/* SWITCH_CORE :: FC_LAN_TXQ_THD_PAUSE_QN_Port_2 :: SWITCH_RESV [15:11] */
-#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_PAUSE_QN_Port_2_SWITCH_RESV_MASK 0x0000f800
-#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_PAUSE_QN_Port_2_SWITCH_RESV_SHIFT 11
-#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_PAUSE_QN_Port_2_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: FC_LAN_TXQ_THD_PAUSE_QN_Port_2 :: TXQ_PAUSE_THD [10:00] */
-#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_PAUSE_QN_Port_2_TXQ_PAUSE_THD_MASK 0x000007ff
-#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_PAUSE_QN_Port_2_TXQ_PAUSE_THD_SHIFT 0
-#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_PAUSE_QN_Port_2_TXQ_PAUSE_THD_DEFAULT 0x000000a7
-
-/***************************************************************************
- *FC_LAN_TXQ_THD_PAUSE_QN_Port_3 - LAN Port Queue N Pause Threshold RegisterNot2Release
- ***************************************************************************/
-/* SWITCH_CORE :: FC_LAN_TXQ_THD_PAUSE_QN_Port_3 :: reserved_for_padding0 [31:16] */
-#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_PAUSE_QN_Port_3_reserved_for_padding0_MASK 0xffff0000
-#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_PAUSE_QN_Port_3_reserved_for_padding0_SHIFT 16
-
-/* SWITCH_CORE :: FC_LAN_TXQ_THD_PAUSE_QN_Port_3 :: SWITCH_RESV [15:11] */
-#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_PAUSE_QN_Port_3_SWITCH_RESV_MASK 0x0000f800
-#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_PAUSE_QN_Port_3_SWITCH_RESV_SHIFT 11
-#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_PAUSE_QN_Port_3_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: FC_LAN_TXQ_THD_PAUSE_QN_Port_3 :: TXQ_PAUSE_THD [10:00] */
-#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_PAUSE_QN_Port_3_TXQ_PAUSE_THD_MASK 0x000007ff
-#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_PAUSE_QN_Port_3_TXQ_PAUSE_THD_SHIFT 0
-#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_PAUSE_QN_Port_3_TXQ_PAUSE_THD_DEFAULT 0x000000af
-
-/***************************************************************************
- *FC_LAN_TXQ_THD_PAUSE_QN_Port_4 - LAN Port Queue N Pause Threshold RegisterNot2Release
- ***************************************************************************/
-/* SWITCH_CORE :: FC_LAN_TXQ_THD_PAUSE_QN_Port_4 :: reserved_for_padding0 [31:16] */
-#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_PAUSE_QN_Port_4_reserved_for_padding0_MASK 0xffff0000
-#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_PAUSE_QN_Port_4_reserved_for_padding0_SHIFT 16
-
-/* SWITCH_CORE :: FC_LAN_TXQ_THD_PAUSE_QN_Port_4 :: SWITCH_RESV [15:11] */
-#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_PAUSE_QN_Port_4_SWITCH_RESV_MASK 0x0000f800
-#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_PAUSE_QN_Port_4_SWITCH_RESV_SHIFT 11
-#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_PAUSE_QN_Port_4_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: FC_LAN_TXQ_THD_PAUSE_QN_Port_4 :: TXQ_PAUSE_THD [10:00] */
-#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_PAUSE_QN_Port_4_TXQ_PAUSE_THD_MASK 0x000007ff
-#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_PAUSE_QN_Port_4_TXQ_PAUSE_THD_SHIFT 0
-#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_PAUSE_QN_Port_4_TXQ_PAUSE_THD_DEFAULT 0x000000b7
-
-/***************************************************************************
- *FC_LAN_TXQ_THD_PAUSE_QN_Port_5 - LAN Port Queue N Pause Threshold RegisterNot2Release
- ***************************************************************************/
-/* SWITCH_CORE :: FC_LAN_TXQ_THD_PAUSE_QN_Port_5 :: reserved_for_padding0 [31:16] */
-#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_PAUSE_QN_Port_5_reserved_for_padding0_MASK 0xffff0000
-#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_PAUSE_QN_Port_5_reserved_for_padding0_SHIFT 16
-
-/* SWITCH_CORE :: FC_LAN_TXQ_THD_PAUSE_QN_Port_5 :: SWITCH_RESV [15:11] */
-#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_PAUSE_QN_Port_5_SWITCH_RESV_MASK 0x0000f800
-#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_PAUSE_QN_Port_5_SWITCH_RESV_SHIFT 11
-#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_PAUSE_QN_Port_5_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: FC_LAN_TXQ_THD_PAUSE_QN_Port_5 :: TXQ_PAUSE_THD [10:00] */
-#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_PAUSE_QN_Port_5_TXQ_PAUSE_THD_MASK 0x000007ff
-#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_PAUSE_QN_Port_5_TXQ_PAUSE_THD_SHIFT 0
-#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_PAUSE_QN_Port_5_TXQ_PAUSE_THD_DEFAULT 0x000000bf
-
-/***************************************************************************
- *FC_LAN_TXQ_THD_PAUSE_QN_Port_6 - LAN Port Queue N Pause Threshold RegisterNot2Release
- ***************************************************************************/
-/* SWITCH_CORE :: FC_LAN_TXQ_THD_PAUSE_QN_Port_6 :: reserved_for_padding0 [31:16] */
-#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_PAUSE_QN_Port_6_reserved_for_padding0_MASK 0xffff0000
-#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_PAUSE_QN_Port_6_reserved_for_padding0_SHIFT 16
-
-/* SWITCH_CORE :: FC_LAN_TXQ_THD_PAUSE_QN_Port_6 :: SWITCH_RESV [15:11] */
-#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_PAUSE_QN_Port_6_SWITCH_RESV_MASK 0x0000f800
-#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_PAUSE_QN_Port_6_SWITCH_RESV_SHIFT 11
-#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_PAUSE_QN_Port_6_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: FC_LAN_TXQ_THD_PAUSE_QN_Port_6 :: TXQ_PAUSE_THD [10:00] */
-#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_PAUSE_QN_Port_6_TXQ_PAUSE_THD_MASK 0x000007ff
-#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_PAUSE_QN_Port_6_TXQ_PAUSE_THD_SHIFT 0
-#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_PAUSE_QN_Port_6_TXQ_PAUSE_THD_DEFAULT 0x000000c7
-
-/***************************************************************************
- *FC_LAN_TXQ_THD_PAUSE_QN_Port_7 - LAN Port Queue N Pause Threshold RegisterNot2Release
- ***************************************************************************/
-/* SWITCH_CORE :: FC_LAN_TXQ_THD_PAUSE_QN_Port_7 :: reserved_for_padding0 [31:16] */
-#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_PAUSE_QN_Port_7_reserved_for_padding0_MASK 0xffff0000
-#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_PAUSE_QN_Port_7_reserved_for_padding0_SHIFT 16
-
-/* SWITCH_CORE :: FC_LAN_TXQ_THD_PAUSE_QN_Port_7 :: SWITCH_RESV [15:11] */
-#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_PAUSE_QN_Port_7_SWITCH_RESV_MASK 0x0000f800
-#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_PAUSE_QN_Port_7_SWITCH_RESV_SHIFT 11
-#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_PAUSE_QN_Port_7_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: FC_LAN_TXQ_THD_PAUSE_QN_Port_7 :: TXQ_PAUSE_THD [10:00] */
-#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_PAUSE_QN_Port_7_TXQ_PAUSE_THD_MASK 0x000007ff
-#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_PAUSE_QN_Port_7_TXQ_PAUSE_THD_SHIFT 0
-#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_PAUSE_QN_Port_7_TXQ_PAUSE_THD_DEFAULT 0x000000cf
-
-/***************************************************************************
- *FC_LAN_TXQ_THD_DROP_QN_Port_0 - LAN Port Queue N DROP Threshold RegisterNot2Release
- ***************************************************************************/
-/* SWITCH_CORE :: FC_LAN_TXQ_THD_DROP_QN_Port_0 :: reserved_for_padding0 [31:16] */
-#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_DROP_QN_Port_0_reserved_for_padding0_MASK 0xffff0000
-#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_DROP_QN_Port_0_reserved_for_padding0_SHIFT 16
-
-/* SWITCH_CORE :: FC_LAN_TXQ_THD_DROP_QN_Port_0 :: SWITCH_RESV [15:11] */
-#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_DROP_QN_Port_0_SWITCH_RESV_MASK 0x0000f800
-#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_DROP_QN_Port_0_SWITCH_RESV_SHIFT 11
-#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_DROP_QN_Port_0_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: FC_LAN_TXQ_THD_DROP_QN_Port_0 :: TXQ_DROP_THD [10:00] */
-#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_DROP_QN_Port_0_TXQ_DROP_THD_MASK 0x000007ff
-#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_DROP_QN_Port_0_TXQ_DROP_THD_SHIFT 0
-#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_DROP_QN_Port_0_TXQ_DROP_THD_DEFAULT 0x000005cf
-
-/***************************************************************************
- *FC_LAN_TXQ_THD_DROP_QN_Port_1 - LAN Port Queue N DROP Threshold RegisterNot2Release
- ***************************************************************************/
-/* SWITCH_CORE :: FC_LAN_TXQ_THD_DROP_QN_Port_1 :: reserved_for_padding0 [31:16] */
-#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_DROP_QN_Port_1_reserved_for_padding0_MASK 0xffff0000
-#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_DROP_QN_Port_1_reserved_for_padding0_SHIFT 16
-
-/* SWITCH_CORE :: FC_LAN_TXQ_THD_DROP_QN_Port_1 :: SWITCH_RESV [15:11] */
-#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_DROP_QN_Port_1_SWITCH_RESV_MASK 0x0000f800
-#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_DROP_QN_Port_1_SWITCH_RESV_SHIFT 11
-#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_DROP_QN_Port_1_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: FC_LAN_TXQ_THD_DROP_QN_Port_1 :: TXQ_DROP_THD [10:00] */
-#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_DROP_QN_Port_1_TXQ_DROP_THD_MASK 0x000007ff
-#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_DROP_QN_Port_1_TXQ_DROP_THD_SHIFT 0
-#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_DROP_QN_Port_1_TXQ_DROP_THD_DEFAULT 0x000005cf
-
-/***************************************************************************
- *FC_LAN_TXQ_THD_DROP_QN_Port_2 - LAN Port Queue N DROP Threshold RegisterNot2Release
- ***************************************************************************/
-/* SWITCH_CORE :: FC_LAN_TXQ_THD_DROP_QN_Port_2 :: reserved_for_padding0 [31:16] */
-#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_DROP_QN_Port_2_reserved_for_padding0_MASK 0xffff0000
-#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_DROP_QN_Port_2_reserved_for_padding0_SHIFT 16
-
-/* SWITCH_CORE :: FC_LAN_TXQ_THD_DROP_QN_Port_2 :: SWITCH_RESV [15:11] */
-#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_DROP_QN_Port_2_SWITCH_RESV_MASK 0x0000f800
-#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_DROP_QN_Port_2_SWITCH_RESV_SHIFT 11
-#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_DROP_QN_Port_2_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: FC_LAN_TXQ_THD_DROP_QN_Port_2 :: TXQ_DROP_THD [10:00] */
-#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_DROP_QN_Port_2_TXQ_DROP_THD_MASK 0x000007ff
-#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_DROP_QN_Port_2_TXQ_DROP_THD_SHIFT 0
-#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_DROP_QN_Port_2_TXQ_DROP_THD_DEFAULT 0x000005cf
-
-/***************************************************************************
- *FC_LAN_TXQ_THD_DROP_QN_Port_3 - LAN Port Queue N DROP Threshold RegisterNot2Release
- ***************************************************************************/
-/* SWITCH_CORE :: FC_LAN_TXQ_THD_DROP_QN_Port_3 :: reserved_for_padding0 [31:16] */
-#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_DROP_QN_Port_3_reserved_for_padding0_MASK 0xffff0000
-#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_DROP_QN_Port_3_reserved_for_padding0_SHIFT 16
-
-/* SWITCH_CORE :: FC_LAN_TXQ_THD_DROP_QN_Port_3 :: SWITCH_RESV [15:11] */
-#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_DROP_QN_Port_3_SWITCH_RESV_MASK 0x0000f800
-#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_DROP_QN_Port_3_SWITCH_RESV_SHIFT 11
-#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_DROP_QN_Port_3_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: FC_LAN_TXQ_THD_DROP_QN_Port_3 :: TXQ_DROP_THD [10:00] */
-#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_DROP_QN_Port_3_TXQ_DROP_THD_MASK 0x000007ff
-#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_DROP_QN_Port_3_TXQ_DROP_THD_SHIFT 0
-#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_DROP_QN_Port_3_TXQ_DROP_THD_DEFAULT 0x000005cf
-
-/***************************************************************************
- *FC_LAN_TXQ_THD_DROP_QN_Port_4 - LAN Port Queue N DROP Threshold RegisterNot2Release
- ***************************************************************************/
-/* SWITCH_CORE :: FC_LAN_TXQ_THD_DROP_QN_Port_4 :: reserved_for_padding0 [31:16] */
-#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_DROP_QN_Port_4_reserved_for_padding0_MASK 0xffff0000
-#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_DROP_QN_Port_4_reserved_for_padding0_SHIFT 16
-
-/* SWITCH_CORE :: FC_LAN_TXQ_THD_DROP_QN_Port_4 :: SWITCH_RESV [15:11] */
-#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_DROP_QN_Port_4_SWITCH_RESV_MASK 0x0000f800
-#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_DROP_QN_Port_4_SWITCH_RESV_SHIFT 11
-#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_DROP_QN_Port_4_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: FC_LAN_TXQ_THD_DROP_QN_Port_4 :: TXQ_DROP_THD [10:00] */
-#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_DROP_QN_Port_4_TXQ_DROP_THD_MASK 0x000007ff
-#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_DROP_QN_Port_4_TXQ_DROP_THD_SHIFT 0
-#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_DROP_QN_Port_4_TXQ_DROP_THD_DEFAULT 0x000005cf
-
-/***************************************************************************
- *FC_LAN_TXQ_THD_DROP_QN_Port_5 - LAN Port Queue N DROP Threshold RegisterNot2Release
- ***************************************************************************/
-/* SWITCH_CORE :: FC_LAN_TXQ_THD_DROP_QN_Port_5 :: reserved_for_padding0 [31:16] */
-#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_DROP_QN_Port_5_reserved_for_padding0_MASK 0xffff0000
-#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_DROP_QN_Port_5_reserved_for_padding0_SHIFT 16
-
-/* SWITCH_CORE :: FC_LAN_TXQ_THD_DROP_QN_Port_5 :: SWITCH_RESV [15:11] */
-#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_DROP_QN_Port_5_SWITCH_RESV_MASK 0x0000f800
-#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_DROP_QN_Port_5_SWITCH_RESV_SHIFT 11
-#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_DROP_QN_Port_5_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: FC_LAN_TXQ_THD_DROP_QN_Port_5 :: TXQ_DROP_THD [10:00] */
-#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_DROP_QN_Port_5_TXQ_DROP_THD_MASK 0x000007ff
-#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_DROP_QN_Port_5_TXQ_DROP_THD_SHIFT 0
-#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_DROP_QN_Port_5_TXQ_DROP_THD_DEFAULT 0x000005cf
-
-/***************************************************************************
- *FC_LAN_TXQ_THD_DROP_QN_Port_6 - LAN Port Queue N DROP Threshold RegisterNot2Release
- ***************************************************************************/
-/* SWITCH_CORE :: FC_LAN_TXQ_THD_DROP_QN_Port_6 :: reserved_for_padding0 [31:16] */
-#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_DROP_QN_Port_6_reserved_for_padding0_MASK 0xffff0000
-#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_DROP_QN_Port_6_reserved_for_padding0_SHIFT 16
-
-/* SWITCH_CORE :: FC_LAN_TXQ_THD_DROP_QN_Port_6 :: SWITCH_RESV [15:11] */
-#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_DROP_QN_Port_6_SWITCH_RESV_MASK 0x0000f800
-#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_DROP_QN_Port_6_SWITCH_RESV_SHIFT 11
-#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_DROP_QN_Port_6_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: FC_LAN_TXQ_THD_DROP_QN_Port_6 :: TXQ_DROP_THD [10:00] */
-#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_DROP_QN_Port_6_TXQ_DROP_THD_MASK 0x000007ff
-#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_DROP_QN_Port_6_TXQ_DROP_THD_SHIFT 0
-#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_DROP_QN_Port_6_TXQ_DROP_THD_DEFAULT 0x000005ff
-
-/***************************************************************************
- *FC_LAN_TXQ_THD_DROP_QN_Port_7 - LAN Port Queue N DROP Threshold RegisterNot2Release
- ***************************************************************************/
-/* SWITCH_CORE :: FC_LAN_TXQ_THD_DROP_QN_Port_7 :: reserved_for_padding0 [31:16] */
-#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_DROP_QN_Port_7_reserved_for_padding0_MASK 0xffff0000
-#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_DROP_QN_Port_7_reserved_for_padding0_SHIFT 16
-
-/* SWITCH_CORE :: FC_LAN_TXQ_THD_DROP_QN_Port_7 :: SWITCH_RESV [15:11] */
-#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_DROP_QN_Port_7_SWITCH_RESV_MASK 0x0000f800
-#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_DROP_QN_Port_7_SWITCH_RESV_SHIFT 11
-#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_DROP_QN_Port_7_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: FC_LAN_TXQ_THD_DROP_QN_Port_7 :: TXQ_DROP_THD [10:00] */
-#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_DROP_QN_Port_7_TXQ_DROP_THD_MASK 0x000007ff
-#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_DROP_QN_Port_7_TXQ_DROP_THD_SHIFT 0
-#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_DROP_QN_Port_7_TXQ_DROP_THD_DEFAULT 0x000005ff
-
-/***************************************************************************
- *FC_LAN_TOTAL_THD_HYST_QN_Port_0 - LAN Port Queue N Total Hysteresis Threshold RegisterNot2Release
- ***************************************************************************/
-/* SWITCH_CORE :: FC_LAN_TOTAL_THD_HYST_QN_Port_0 :: reserved_for_padding0 [31:16] */
-#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_HYST_QN_Port_0_reserved_for_padding0_MASK 0xffff0000
-#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_HYST_QN_Port_0_reserved_for_padding0_SHIFT 16
-
-/* SWITCH_CORE :: FC_LAN_TOTAL_THD_HYST_QN_Port_0 :: SWITCH_RESV [15:11] */
-#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_HYST_QN_Port_0_SWITCH_RESV_MASK 0x0000f800
-#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_HYST_QN_Port_0_SWITCH_RESV_SHIFT 11
-#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_HYST_QN_Port_0_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: FC_LAN_TOTAL_THD_HYST_QN_Port_0 :: TOTAL_HYST_THD [10:00] */
-#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_HYST_QN_Port_0_TOTAL_HYST_THD_MASK 0x000007ff
-#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_HYST_QN_Port_0_TOTAL_HYST_THD_SHIFT 0
-#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_HYST_QN_Port_0_TOTAL_HYST_THD_DEFAULT 0x0000038f
-
-/***************************************************************************
- *FC_LAN_TOTAL_THD_HYST_QN_Port_1 - LAN Port Queue N Total Hysteresis Threshold RegisterNot2Release
- ***************************************************************************/
-/* SWITCH_CORE :: FC_LAN_TOTAL_THD_HYST_QN_Port_1 :: reserved_for_padding0 [31:16] */
-#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_HYST_QN_Port_1_reserved_for_padding0_MASK 0xffff0000
-#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_HYST_QN_Port_1_reserved_for_padding0_SHIFT 16
-
-/* SWITCH_CORE :: FC_LAN_TOTAL_THD_HYST_QN_Port_1 :: SWITCH_RESV [15:11] */
-#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_HYST_QN_Port_1_SWITCH_RESV_MASK 0x0000f800
-#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_HYST_QN_Port_1_SWITCH_RESV_SHIFT 11
-#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_HYST_QN_Port_1_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: FC_LAN_TOTAL_THD_HYST_QN_Port_1 :: TOTAL_HYST_THD [10:00] */
-#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_HYST_QN_Port_1_TOTAL_HYST_THD_MASK 0x000007ff
-#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_HYST_QN_Port_1_TOTAL_HYST_THD_SHIFT 0
-#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_HYST_QN_Port_1_TOTAL_HYST_THD_DEFAULT 0x0000038f
-
-/***************************************************************************
- *FC_LAN_TOTAL_THD_HYST_QN_Port_2 - LAN Port Queue N Total Hysteresis Threshold RegisterNot2Release
- ***************************************************************************/
-/* SWITCH_CORE :: FC_LAN_TOTAL_THD_HYST_QN_Port_2 :: reserved_for_padding0 [31:16] */
-#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_HYST_QN_Port_2_reserved_for_padding0_MASK 0xffff0000
-#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_HYST_QN_Port_2_reserved_for_padding0_SHIFT 16
-
-/* SWITCH_CORE :: FC_LAN_TOTAL_THD_HYST_QN_Port_2 :: SWITCH_RESV [15:11] */
-#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_HYST_QN_Port_2_SWITCH_RESV_MASK 0x0000f800
-#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_HYST_QN_Port_2_SWITCH_RESV_SHIFT 11
-#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_HYST_QN_Port_2_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: FC_LAN_TOTAL_THD_HYST_QN_Port_2 :: TOTAL_HYST_THD [10:00] */
-#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_HYST_QN_Port_2_TOTAL_HYST_THD_MASK 0x000007ff
-#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_HYST_QN_Port_2_TOTAL_HYST_THD_SHIFT 0
-#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_HYST_QN_Port_2_TOTAL_HYST_THD_DEFAULT 0x0000038f
-
-/***************************************************************************
- *FC_LAN_TOTAL_THD_HYST_QN_Port_3 - LAN Port Queue N Total Hysteresis Threshold RegisterNot2Release
- ***************************************************************************/
-/* SWITCH_CORE :: FC_LAN_TOTAL_THD_HYST_QN_Port_3 :: reserved_for_padding0 [31:16] */
-#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_HYST_QN_Port_3_reserved_for_padding0_MASK 0xffff0000
-#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_HYST_QN_Port_3_reserved_for_padding0_SHIFT 16
-
-/* SWITCH_CORE :: FC_LAN_TOTAL_THD_HYST_QN_Port_3 :: SWITCH_RESV [15:11] */
-#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_HYST_QN_Port_3_SWITCH_RESV_MASK 0x0000f800
-#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_HYST_QN_Port_3_SWITCH_RESV_SHIFT 11
-#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_HYST_QN_Port_3_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: FC_LAN_TOTAL_THD_HYST_QN_Port_3 :: TOTAL_HYST_THD [10:00] */
-#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_HYST_QN_Port_3_TOTAL_HYST_THD_MASK 0x000007ff
-#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_HYST_QN_Port_3_TOTAL_HYST_THD_SHIFT 0
-#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_HYST_QN_Port_3_TOTAL_HYST_THD_DEFAULT 0x0000038f
-
-/***************************************************************************
- *FC_LAN_TOTAL_THD_HYST_QN_Port_4 - LAN Port Queue N Total Hysteresis Threshold RegisterNot2Release
- ***************************************************************************/
-/* SWITCH_CORE :: FC_LAN_TOTAL_THD_HYST_QN_Port_4 :: reserved_for_padding0 [31:16] */
-#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_HYST_QN_Port_4_reserved_for_padding0_MASK 0xffff0000
-#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_HYST_QN_Port_4_reserved_for_padding0_SHIFT 16
-
-/* SWITCH_CORE :: FC_LAN_TOTAL_THD_HYST_QN_Port_4 :: SWITCH_RESV [15:11] */
-#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_HYST_QN_Port_4_SWITCH_RESV_MASK 0x0000f800
-#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_HYST_QN_Port_4_SWITCH_RESV_SHIFT 11
-#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_HYST_QN_Port_4_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: FC_LAN_TOTAL_THD_HYST_QN_Port_4 :: TOTAL_HYST_THD [10:00] */
-#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_HYST_QN_Port_4_TOTAL_HYST_THD_MASK 0x000007ff
-#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_HYST_QN_Port_4_TOTAL_HYST_THD_SHIFT 0
-#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_HYST_QN_Port_4_TOTAL_HYST_THD_DEFAULT 0x0000038f
-
-/***************************************************************************
- *FC_LAN_TOTAL_THD_HYST_QN_Port_5 - LAN Port Queue N Total Hysteresis Threshold RegisterNot2Release
- ***************************************************************************/
-/* SWITCH_CORE :: FC_LAN_TOTAL_THD_HYST_QN_Port_5 :: reserved_for_padding0 [31:16] */
-#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_HYST_QN_Port_5_reserved_for_padding0_MASK 0xffff0000
-#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_HYST_QN_Port_5_reserved_for_padding0_SHIFT 16
-
-/* SWITCH_CORE :: FC_LAN_TOTAL_THD_HYST_QN_Port_5 :: SWITCH_RESV [15:11] */
-#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_HYST_QN_Port_5_SWITCH_RESV_MASK 0x0000f800
-#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_HYST_QN_Port_5_SWITCH_RESV_SHIFT 11
-#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_HYST_QN_Port_5_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: FC_LAN_TOTAL_THD_HYST_QN_Port_5 :: TOTAL_HYST_THD [10:00] */
-#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_HYST_QN_Port_5_TOTAL_HYST_THD_MASK 0x000007ff
-#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_HYST_QN_Port_5_TOTAL_HYST_THD_SHIFT 0
-#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_HYST_QN_Port_5_TOTAL_HYST_THD_DEFAULT 0x0000038f
-
-/***************************************************************************
- *FC_LAN_TOTAL_THD_HYST_QN_Port_6 - LAN Port Queue N Total Hysteresis Threshold RegisterNot2Release
- ***************************************************************************/
-/* SWITCH_CORE :: FC_LAN_TOTAL_THD_HYST_QN_Port_6 :: reserved_for_padding0 [31:16] */
-#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_HYST_QN_Port_6_reserved_for_padding0_MASK 0xffff0000
-#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_HYST_QN_Port_6_reserved_for_padding0_SHIFT 16
-
-/* SWITCH_CORE :: FC_LAN_TOTAL_THD_HYST_QN_Port_6 :: SWITCH_RESV [15:11] */
-#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_HYST_QN_Port_6_SWITCH_RESV_MASK 0x0000f800
-#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_HYST_QN_Port_6_SWITCH_RESV_SHIFT 11
-#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_HYST_QN_Port_6_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: FC_LAN_TOTAL_THD_HYST_QN_Port_6 :: TOTAL_HYST_THD [10:00] */
-#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_HYST_QN_Port_6_TOTAL_HYST_THD_MASK 0x000007ff
-#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_HYST_QN_Port_6_TOTAL_HYST_THD_SHIFT 0
-#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_HYST_QN_Port_6_TOTAL_HYST_THD_DEFAULT 0x0000038f
-
-/***************************************************************************
- *FC_LAN_TOTAL_THD_HYST_QN_Port_7 - LAN Port Queue N Total Hysteresis Threshold RegisterNot2Release
- ***************************************************************************/
-/* SWITCH_CORE :: FC_LAN_TOTAL_THD_HYST_QN_Port_7 :: reserved_for_padding0 [31:16] */
-#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_HYST_QN_Port_7_reserved_for_padding0_MASK 0xffff0000
-#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_HYST_QN_Port_7_reserved_for_padding0_SHIFT 16
-
-/* SWITCH_CORE :: FC_LAN_TOTAL_THD_HYST_QN_Port_7 :: SWITCH_RESV [15:11] */
-#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_HYST_QN_Port_7_SWITCH_RESV_MASK 0x0000f800
-#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_HYST_QN_Port_7_SWITCH_RESV_SHIFT 11
-#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_HYST_QN_Port_7_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: FC_LAN_TOTAL_THD_HYST_QN_Port_7 :: TOTAL_HYST_THD [10:00] */
-#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_HYST_QN_Port_7_TOTAL_HYST_THD_MASK 0x000007ff
-#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_HYST_QN_Port_7_TOTAL_HYST_THD_SHIFT 0
-#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_HYST_QN_Port_7_TOTAL_HYST_THD_DEFAULT 0x0000038f
-
-/***************************************************************************
- *FC_LAN_TOTAL_THD_PAUSE_QN_Port_0 - LAN Port Queue N Total Pause Threshold RegisterNot2Release
- ***************************************************************************/
-/* SWITCH_CORE :: FC_LAN_TOTAL_THD_PAUSE_QN_Port_0 :: reserved_for_padding0 [31:16] */
-#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_PAUSE_QN_Port_0_reserved_for_padding0_MASK 0xffff0000
-#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_PAUSE_QN_Port_0_reserved_for_padding0_SHIFT 16
-
-/* SWITCH_CORE :: FC_LAN_TOTAL_THD_PAUSE_QN_Port_0 :: SWITCH_RESV [15:11] */
-#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_PAUSE_QN_Port_0_SWITCH_RESV_MASK 0x0000f800
-#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_PAUSE_QN_Port_0_SWITCH_RESV_SHIFT 11
-#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_PAUSE_QN_Port_0_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: FC_LAN_TOTAL_THD_PAUSE_QN_Port_0 :: TOTAL_PAUSE_THD [10:00] */
-#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_PAUSE_QN_Port_0_TOTAL_PAUSE_THD_MASK 0x000007ff
-#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_PAUSE_QN_Port_0_TOTAL_PAUSE_THD_SHIFT 0
-#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_PAUSE_QN_Port_0_TOTAL_PAUSE_THD_DEFAULT 0x0000040f
-
-/***************************************************************************
- *FC_LAN_TOTAL_THD_PAUSE_QN_Port_1 - LAN Port Queue N Total Pause Threshold RegisterNot2Release
- ***************************************************************************/
-/* SWITCH_CORE :: FC_LAN_TOTAL_THD_PAUSE_QN_Port_1 :: reserved_for_padding0 [31:16] */
-#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_PAUSE_QN_Port_1_reserved_for_padding0_MASK 0xffff0000
-#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_PAUSE_QN_Port_1_reserved_for_padding0_SHIFT 16
-
-/* SWITCH_CORE :: FC_LAN_TOTAL_THD_PAUSE_QN_Port_1 :: SWITCH_RESV [15:11] */
-#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_PAUSE_QN_Port_1_SWITCH_RESV_MASK 0x0000f800
-#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_PAUSE_QN_Port_1_SWITCH_RESV_SHIFT 11
-#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_PAUSE_QN_Port_1_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: FC_LAN_TOTAL_THD_PAUSE_QN_Port_1 :: TOTAL_PAUSE_THD [10:00] */
-#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_PAUSE_QN_Port_1_TOTAL_PAUSE_THD_MASK 0x000007ff
-#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_PAUSE_QN_Port_1_TOTAL_PAUSE_THD_SHIFT 0
-#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_PAUSE_QN_Port_1_TOTAL_PAUSE_THD_DEFAULT 0x00000417
-
-/***************************************************************************
- *FC_LAN_TOTAL_THD_PAUSE_QN_Port_2 - LAN Port Queue N Total Pause Threshold RegisterNot2Release
- ***************************************************************************/
-/* SWITCH_CORE :: FC_LAN_TOTAL_THD_PAUSE_QN_Port_2 :: reserved_for_padding0 [31:16] */
-#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_PAUSE_QN_Port_2_reserved_for_padding0_MASK 0xffff0000
-#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_PAUSE_QN_Port_2_reserved_for_padding0_SHIFT 16
-
-/* SWITCH_CORE :: FC_LAN_TOTAL_THD_PAUSE_QN_Port_2 :: SWITCH_RESV [15:11] */
-#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_PAUSE_QN_Port_2_SWITCH_RESV_MASK 0x0000f800
-#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_PAUSE_QN_Port_2_SWITCH_RESV_SHIFT 11
-#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_PAUSE_QN_Port_2_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: FC_LAN_TOTAL_THD_PAUSE_QN_Port_2 :: TOTAL_PAUSE_THD [10:00] */
-#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_PAUSE_QN_Port_2_TOTAL_PAUSE_THD_MASK 0x000007ff
-#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_PAUSE_QN_Port_2_TOTAL_PAUSE_THD_SHIFT 0
-#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_PAUSE_QN_Port_2_TOTAL_PAUSE_THD_DEFAULT 0x0000041f
-
-/***************************************************************************
- *FC_LAN_TOTAL_THD_PAUSE_QN_Port_3 - LAN Port Queue N Total Pause Threshold RegisterNot2Release
- ***************************************************************************/
-/* SWITCH_CORE :: FC_LAN_TOTAL_THD_PAUSE_QN_Port_3 :: reserved_for_padding0 [31:16] */
-#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_PAUSE_QN_Port_3_reserved_for_padding0_MASK 0xffff0000
-#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_PAUSE_QN_Port_3_reserved_for_padding0_SHIFT 16
-
-/* SWITCH_CORE :: FC_LAN_TOTAL_THD_PAUSE_QN_Port_3 :: SWITCH_RESV [15:11] */
-#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_PAUSE_QN_Port_3_SWITCH_RESV_MASK 0x0000f800
-#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_PAUSE_QN_Port_3_SWITCH_RESV_SHIFT 11
-#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_PAUSE_QN_Port_3_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: FC_LAN_TOTAL_THD_PAUSE_QN_Port_3 :: TOTAL_PAUSE_THD [10:00] */
-#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_PAUSE_QN_Port_3_TOTAL_PAUSE_THD_MASK 0x000007ff
-#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_PAUSE_QN_Port_3_TOTAL_PAUSE_THD_SHIFT 0
-#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_PAUSE_QN_Port_3_TOTAL_PAUSE_THD_DEFAULT 0x00000427
-
-/***************************************************************************
- *FC_LAN_TOTAL_THD_PAUSE_QN_Port_4 - LAN Port Queue N Total Pause Threshold RegisterNot2Release
- ***************************************************************************/
-/* SWITCH_CORE :: FC_LAN_TOTAL_THD_PAUSE_QN_Port_4 :: reserved_for_padding0 [31:16] */
-#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_PAUSE_QN_Port_4_reserved_for_padding0_MASK 0xffff0000
-#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_PAUSE_QN_Port_4_reserved_for_padding0_SHIFT 16
-
-/* SWITCH_CORE :: FC_LAN_TOTAL_THD_PAUSE_QN_Port_4 :: SWITCH_RESV [15:11] */
-#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_PAUSE_QN_Port_4_SWITCH_RESV_MASK 0x0000f800
-#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_PAUSE_QN_Port_4_SWITCH_RESV_SHIFT 11
-#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_PAUSE_QN_Port_4_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: FC_LAN_TOTAL_THD_PAUSE_QN_Port_4 :: TOTAL_PAUSE_THD [10:00] */
-#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_PAUSE_QN_Port_4_TOTAL_PAUSE_THD_MASK 0x000007ff
-#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_PAUSE_QN_Port_4_TOTAL_PAUSE_THD_SHIFT 0
-#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_PAUSE_QN_Port_4_TOTAL_PAUSE_THD_DEFAULT 0x0000042f
-
-/***************************************************************************
- *FC_LAN_TOTAL_THD_PAUSE_QN_Port_5 - LAN Port Queue N Total Pause Threshold RegisterNot2Release
- ***************************************************************************/
-/* SWITCH_CORE :: FC_LAN_TOTAL_THD_PAUSE_QN_Port_5 :: reserved_for_padding0 [31:16] */
-#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_PAUSE_QN_Port_5_reserved_for_padding0_MASK 0xffff0000
-#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_PAUSE_QN_Port_5_reserved_for_padding0_SHIFT 16
-
-/* SWITCH_CORE :: FC_LAN_TOTAL_THD_PAUSE_QN_Port_5 :: SWITCH_RESV [15:11] */
-#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_PAUSE_QN_Port_5_SWITCH_RESV_MASK 0x0000f800
-#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_PAUSE_QN_Port_5_SWITCH_RESV_SHIFT 11
-#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_PAUSE_QN_Port_5_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: FC_LAN_TOTAL_THD_PAUSE_QN_Port_5 :: TOTAL_PAUSE_THD [10:00] */
-#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_PAUSE_QN_Port_5_TOTAL_PAUSE_THD_MASK 0x000007ff
-#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_PAUSE_QN_Port_5_TOTAL_PAUSE_THD_SHIFT 0
-#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_PAUSE_QN_Port_5_TOTAL_PAUSE_THD_DEFAULT 0x00000437
-
-/***************************************************************************
- *FC_LAN_TOTAL_THD_PAUSE_QN_Port_6 - LAN Port Queue N Total Pause Threshold RegisterNot2Release
- ***************************************************************************/
-/* SWITCH_CORE :: FC_LAN_TOTAL_THD_PAUSE_QN_Port_6 :: reserved_for_padding0 [31:16] */
-#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_PAUSE_QN_Port_6_reserved_for_padding0_MASK 0xffff0000
-#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_PAUSE_QN_Port_6_reserved_for_padding0_SHIFT 16
-
-/* SWITCH_CORE :: FC_LAN_TOTAL_THD_PAUSE_QN_Port_6 :: SWITCH_RESV [15:11] */
-#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_PAUSE_QN_Port_6_SWITCH_RESV_MASK 0x0000f800
-#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_PAUSE_QN_Port_6_SWITCH_RESV_SHIFT 11
-#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_PAUSE_QN_Port_6_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: FC_LAN_TOTAL_THD_PAUSE_QN_Port_6 :: TOTAL_PAUSE_THD [10:00] */
-#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_PAUSE_QN_Port_6_TOTAL_PAUSE_THD_MASK 0x000007ff
-#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_PAUSE_QN_Port_6_TOTAL_PAUSE_THD_SHIFT 0
-#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_PAUSE_QN_Port_6_TOTAL_PAUSE_THD_DEFAULT 0x0000043f
-
-/***************************************************************************
- *FC_LAN_TOTAL_THD_PAUSE_QN_Port_7 - LAN Port Queue N Total Pause Threshold RegisterNot2Release
- ***************************************************************************/
-/* SWITCH_CORE :: FC_LAN_TOTAL_THD_PAUSE_QN_Port_7 :: reserved_for_padding0 [31:16] */
-#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_PAUSE_QN_Port_7_reserved_for_padding0_MASK 0xffff0000
-#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_PAUSE_QN_Port_7_reserved_for_padding0_SHIFT 16
-
-/* SWITCH_CORE :: FC_LAN_TOTAL_THD_PAUSE_QN_Port_7 :: SWITCH_RESV [15:11] */
-#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_PAUSE_QN_Port_7_SWITCH_RESV_MASK 0x0000f800
-#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_PAUSE_QN_Port_7_SWITCH_RESV_SHIFT 11
-#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_PAUSE_QN_Port_7_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: FC_LAN_TOTAL_THD_PAUSE_QN_Port_7 :: TOTAL_PAUSE_THD [10:00] */
-#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_PAUSE_QN_Port_7_TOTAL_PAUSE_THD_MASK 0x000007ff
-#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_PAUSE_QN_Port_7_TOTAL_PAUSE_THD_SHIFT 0
-#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_PAUSE_QN_Port_7_TOTAL_PAUSE_THD_DEFAULT 0x00000447
-
-/***************************************************************************
- *FC_LAN_TOTAL_THD_DROP_QN_Port_0 - LAN Port Queue N Total DROP Threshold RegisterNot2Release
- ***************************************************************************/
-/* SWITCH_CORE :: FC_LAN_TOTAL_THD_DROP_QN_Port_0 :: reserved_for_padding0 [31:16] */
-#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_DROP_QN_Port_0_reserved_for_padding0_MASK 0xffff0000
-#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_DROP_QN_Port_0_reserved_for_padding0_SHIFT 16
-
-/* SWITCH_CORE :: FC_LAN_TOTAL_THD_DROP_QN_Port_0 :: SWITCH_RESV [15:11] */
-#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_DROP_QN_Port_0_SWITCH_RESV_MASK 0x0000f800
-#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_DROP_QN_Port_0_SWITCH_RESV_SHIFT 11
-#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_DROP_QN_Port_0_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: FC_LAN_TOTAL_THD_DROP_QN_Port_0 :: TOTAL_DROP_THD [10:00] */
-#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_DROP_QN_Port_0_TOTAL_DROP_THD_MASK 0x000007ff
-#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_DROP_QN_Port_0_TOTAL_DROP_THD_SHIFT 0
-#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_DROP_QN_Port_0_TOTAL_DROP_THD_DEFAULT 0x0000058f
-
-/***************************************************************************
- *FC_LAN_TOTAL_THD_DROP_QN_Port_1 - LAN Port Queue N Total DROP Threshold RegisterNot2Release
- ***************************************************************************/
-/* SWITCH_CORE :: FC_LAN_TOTAL_THD_DROP_QN_Port_1 :: reserved_for_padding0 [31:16] */
-#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_DROP_QN_Port_1_reserved_for_padding0_MASK 0xffff0000
-#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_DROP_QN_Port_1_reserved_for_padding0_SHIFT 16
-
-/* SWITCH_CORE :: FC_LAN_TOTAL_THD_DROP_QN_Port_1 :: SWITCH_RESV [15:11] */
-#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_DROP_QN_Port_1_SWITCH_RESV_MASK 0x0000f800
-#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_DROP_QN_Port_1_SWITCH_RESV_SHIFT 11
-#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_DROP_QN_Port_1_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: FC_LAN_TOTAL_THD_DROP_QN_Port_1 :: TOTAL_DROP_THD [10:00] */
-#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_DROP_QN_Port_1_TOTAL_DROP_THD_MASK 0x000007ff
-#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_DROP_QN_Port_1_TOTAL_DROP_THD_SHIFT 0
-#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_DROP_QN_Port_1_TOTAL_DROP_THD_DEFAULT 0x00000597
-
-/***************************************************************************
- *FC_LAN_TOTAL_THD_DROP_QN_Port_2 - LAN Port Queue N Total DROP Threshold RegisterNot2Release
- ***************************************************************************/
-/* SWITCH_CORE :: FC_LAN_TOTAL_THD_DROP_QN_Port_2 :: reserved_for_padding0 [31:16] */
-#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_DROP_QN_Port_2_reserved_for_padding0_MASK 0xffff0000
-#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_DROP_QN_Port_2_reserved_for_padding0_SHIFT 16
-
-/* SWITCH_CORE :: FC_LAN_TOTAL_THD_DROP_QN_Port_2 :: SWITCH_RESV [15:11] */
-#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_DROP_QN_Port_2_SWITCH_RESV_MASK 0x0000f800
-#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_DROP_QN_Port_2_SWITCH_RESV_SHIFT 11
-#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_DROP_QN_Port_2_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: FC_LAN_TOTAL_THD_DROP_QN_Port_2 :: TOTAL_DROP_THD [10:00] */
-#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_DROP_QN_Port_2_TOTAL_DROP_THD_MASK 0x000007ff
-#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_DROP_QN_Port_2_TOTAL_DROP_THD_SHIFT 0
-#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_DROP_QN_Port_2_TOTAL_DROP_THD_DEFAULT 0x0000059f
-
-/***************************************************************************
- *FC_LAN_TOTAL_THD_DROP_QN_Port_3 - LAN Port Queue N Total DROP Threshold RegisterNot2Release
- ***************************************************************************/
-/* SWITCH_CORE :: FC_LAN_TOTAL_THD_DROP_QN_Port_3 :: reserved_for_padding0 [31:16] */
-#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_DROP_QN_Port_3_reserved_for_padding0_MASK 0xffff0000
-#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_DROP_QN_Port_3_reserved_for_padding0_SHIFT 16
-
-/* SWITCH_CORE :: FC_LAN_TOTAL_THD_DROP_QN_Port_3 :: SWITCH_RESV [15:11] */
-#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_DROP_QN_Port_3_SWITCH_RESV_MASK 0x0000f800
-#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_DROP_QN_Port_3_SWITCH_RESV_SHIFT 11
-#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_DROP_QN_Port_3_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: FC_LAN_TOTAL_THD_DROP_QN_Port_3 :: TOTAL_DROP_THD [10:00] */
-#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_DROP_QN_Port_3_TOTAL_DROP_THD_MASK 0x000007ff
-#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_DROP_QN_Port_3_TOTAL_DROP_THD_SHIFT 0
-#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_DROP_QN_Port_3_TOTAL_DROP_THD_DEFAULT 0x000005a7
-
-/***************************************************************************
- *FC_LAN_TOTAL_THD_DROP_QN_Port_4 - LAN Port Queue N Total DROP Threshold RegisterNot2Release
- ***************************************************************************/
-/* SWITCH_CORE :: FC_LAN_TOTAL_THD_DROP_QN_Port_4 :: reserved_for_padding0 [31:16] */
-#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_DROP_QN_Port_4_reserved_for_padding0_MASK 0xffff0000
-#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_DROP_QN_Port_4_reserved_for_padding0_SHIFT 16
-
-/* SWITCH_CORE :: FC_LAN_TOTAL_THD_DROP_QN_Port_4 :: SWITCH_RESV [15:11] */
-#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_DROP_QN_Port_4_SWITCH_RESV_MASK 0x0000f800
-#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_DROP_QN_Port_4_SWITCH_RESV_SHIFT 11
-#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_DROP_QN_Port_4_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: FC_LAN_TOTAL_THD_DROP_QN_Port_4 :: TOTAL_DROP_THD [10:00] */
-#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_DROP_QN_Port_4_TOTAL_DROP_THD_MASK 0x000007ff
-#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_DROP_QN_Port_4_TOTAL_DROP_THD_SHIFT 0
-#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_DROP_QN_Port_4_TOTAL_DROP_THD_DEFAULT 0x000005af
-
-/***************************************************************************
- *FC_LAN_TOTAL_THD_DROP_QN_Port_5 - LAN Port Queue N Total DROP Threshold RegisterNot2Release
- ***************************************************************************/
-/* SWITCH_CORE :: FC_LAN_TOTAL_THD_DROP_QN_Port_5 :: reserved_for_padding0 [31:16] */
-#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_DROP_QN_Port_5_reserved_for_padding0_MASK 0xffff0000
-#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_DROP_QN_Port_5_reserved_for_padding0_SHIFT 16
-
-/* SWITCH_CORE :: FC_LAN_TOTAL_THD_DROP_QN_Port_5 :: SWITCH_RESV [15:11] */
-#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_DROP_QN_Port_5_SWITCH_RESV_MASK 0x0000f800
-#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_DROP_QN_Port_5_SWITCH_RESV_SHIFT 11
-#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_DROP_QN_Port_5_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: FC_LAN_TOTAL_THD_DROP_QN_Port_5 :: TOTAL_DROP_THD [10:00] */
-#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_DROP_QN_Port_5_TOTAL_DROP_THD_MASK 0x000007ff
-#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_DROP_QN_Port_5_TOTAL_DROP_THD_SHIFT 0
-#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_DROP_QN_Port_5_TOTAL_DROP_THD_DEFAULT 0x000005b7
-
-/***************************************************************************
- *FC_LAN_TOTAL_THD_DROP_QN_Port_6 - LAN Port Queue N Total DROP Threshold RegisterNot2Release
- ***************************************************************************/
-/* SWITCH_CORE :: FC_LAN_TOTAL_THD_DROP_QN_Port_6 :: reserved_for_padding0 [31:16] */
-#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_DROP_QN_Port_6_reserved_for_padding0_MASK 0xffff0000
-#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_DROP_QN_Port_6_reserved_for_padding0_SHIFT 16
-
-/* SWITCH_CORE :: FC_LAN_TOTAL_THD_DROP_QN_Port_6 :: SWITCH_RESV [15:11] */
-#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_DROP_QN_Port_6_SWITCH_RESV_MASK 0x0000f800
-#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_DROP_QN_Port_6_SWITCH_RESV_SHIFT 11
-#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_DROP_QN_Port_6_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: FC_LAN_TOTAL_THD_DROP_QN_Port_6 :: TOTAL_DROP_THD [10:00] */
-#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_DROP_QN_Port_6_TOTAL_DROP_THD_MASK 0x000007ff
-#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_DROP_QN_Port_6_TOTAL_DROP_THD_SHIFT 0
-#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_DROP_QN_Port_6_TOTAL_DROP_THD_DEFAULT 0x000005bf
-
-/***************************************************************************
- *FC_LAN_TOTAL_THD_DROP_QN_Port_7 - LAN Port Queue N Total DROP Threshold RegisterNot2Release
- ***************************************************************************/
-/* SWITCH_CORE :: FC_LAN_TOTAL_THD_DROP_QN_Port_7 :: reserved_for_padding0 [31:16] */
-#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_DROP_QN_Port_7_reserved_for_padding0_MASK 0xffff0000
-#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_DROP_QN_Port_7_reserved_for_padding0_SHIFT 16
-
-/* SWITCH_CORE :: FC_LAN_TOTAL_THD_DROP_QN_Port_7 :: SWITCH_RESV [15:11] */
-#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_DROP_QN_Port_7_SWITCH_RESV_MASK 0x0000f800
-#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_DROP_QN_Port_7_SWITCH_RESV_SHIFT 11
-#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_DROP_QN_Port_7_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: FC_LAN_TOTAL_THD_DROP_QN_Port_7 :: TOTAL_DROP_THD [10:00] */
-#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_DROP_QN_Port_7_TOTAL_DROP_THD_MASK 0x000007ff
-#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_DROP_QN_Port_7_TOTAL_DROP_THD_SHIFT 0
-#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_DROP_QN_Port_7_TOTAL_DROP_THD_DEFAULT 0x000005c7
-
-/***************************************************************************
- *P0_DEBUG_MUX - P0 DEBUG MUXNot2Release
- ***************************************************************************/
-/* SWITCH_CORE :: P0_DEBUG_MUX :: SWITCH_RESV [31:00] */
-#define BCHP_SWITCH_CORE_P0_DEBUG_MUX_SWITCH_RESV_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_P0_DEBUG_MUX_SWITCH_RESV_SHIFT 0
-#define BCHP_SWITCH_CORE_P0_DEBUG_MUX_SWITCH_RESV_DEFAULT 0x00000000
-
-/***************************************************************************
- *P1_DEBUG_MUX - P1 DEBUG MUXNot2Release
- ***************************************************************************/
-/* SWITCH_CORE :: P1_DEBUG_MUX :: SWITCH_RESV [31:00] */
-#define BCHP_SWITCH_CORE_P1_DEBUG_MUX_SWITCH_RESV_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_P1_DEBUG_MUX_SWITCH_RESV_SHIFT 0
-#define BCHP_SWITCH_CORE_P1_DEBUG_MUX_SWITCH_RESV_DEFAULT 0x00000000
-
-/***************************************************************************
- *P2_DEBUG_MUX - P2 DEBUG MUXNot2Release
- ***************************************************************************/
-/* SWITCH_CORE :: P2_DEBUG_MUX :: SWITCH_RESV [31:00] */
-#define BCHP_SWITCH_CORE_P2_DEBUG_MUX_SWITCH_RESV_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_P2_DEBUG_MUX_SWITCH_RESV_SHIFT 0
-#define BCHP_SWITCH_CORE_P2_DEBUG_MUX_SWITCH_RESV_DEFAULT 0x00000000
-
-/***************************************************************************
- *P3_DEBUG_MUX - P3 DEBUG MUXNot2Release
- ***************************************************************************/
-/* SWITCH_CORE :: P3_DEBUG_MUX :: SWITCH_RESV [31:00] */
-#define BCHP_SWITCH_CORE_P3_DEBUG_MUX_SWITCH_RESV_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_P3_DEBUG_MUX_SWITCH_RESV_SHIFT 0
-#define BCHP_SWITCH_CORE_P3_DEBUG_MUX_SWITCH_RESV_DEFAULT 0x00000000
-
-/***************************************************************************
- *P4_DEBUG_MUX - P4 DEBUG MUXNot2Release
- ***************************************************************************/
-/* SWITCH_CORE :: P4_DEBUG_MUX :: SWITCH_RESV [31:00] */
-#define BCHP_SWITCH_CORE_P4_DEBUG_MUX_SWITCH_RESV_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_P4_DEBUG_MUX_SWITCH_RESV_SHIFT 0
-#define BCHP_SWITCH_CORE_P4_DEBUG_MUX_SWITCH_RESV_DEFAULT 0x00000000
-
-/***************************************************************************
- *P5_DEBUG_MUX - P5 DEBUG MUXNot2Release
- ***************************************************************************/
-/* SWITCH_CORE :: P5_DEBUG_MUX :: SWITCH_RESV [31:00] */
-#define BCHP_SWITCH_CORE_P5_DEBUG_MUX_SWITCH_RESV_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_P5_DEBUG_MUX_SWITCH_RESV_SHIFT 0
-#define BCHP_SWITCH_CORE_P5_DEBUG_MUX_SWITCH_RESV_DEFAULT 0x00000000
-
-/***************************************************************************
- *P6_DEBUG_MUX - P6 DEBUG MUXNot2Release
- ***************************************************************************/
-/* SWITCH_CORE :: P6_DEBUG_MUX :: SWITCH_RESV [31:00] */
-#define BCHP_SWITCH_CORE_P6_DEBUG_MUX_SWITCH_RESV_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_P6_DEBUG_MUX_SWITCH_RESV_SHIFT 0
-#define BCHP_SWITCH_CORE_P6_DEBUG_MUX_SWITCH_RESV_DEFAULT 0x00000000
-
-/***************************************************************************
- *P7_DEBUG_MUX - P7 DEBUG MUXNot2Release
- ***************************************************************************/
-/* SWITCH_CORE :: P7_DEBUG_MUX :: SWITCH_RESV [31:00] */
-#define BCHP_SWITCH_CORE_P7_DEBUG_MUX_SWITCH_RESV_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_P7_DEBUG_MUX_SWITCH_RESV_SHIFT 0
-#define BCHP_SWITCH_CORE_P7_DEBUG_MUX_SWITCH_RESV_DEFAULT 0x00000000
-
-/***************************************************************************
- *IMP_DEBUG_MUX - IMP DEBUG MUXNot2Release
- ***************************************************************************/
-/* SWITCH_CORE :: IMP_DEBUG_MUX :: SWITCH_RESV [31:00] */
-#define BCHP_SWITCH_CORE_IMP_DEBUG_MUX_SWITCH_RESV_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_IMP_DEBUG_MUX_SWITCH_RESV_SHIFT 0
-#define BCHP_SWITCH_CORE_IMP_DEBUG_MUX_SWITCH_RESV_DEFAULT 0x00000000
-
-/***************************************************************************
- *CFP_DEBUG_BUS_0 - CFP DEBUG BUS 0Not2Release
- ***************************************************************************/
-/* SWITCH_CORE :: CFP_DEBUG_BUS_0 :: SWITCH_RESV [31:00] */
-#define BCHP_SWITCH_CORE_CFP_DEBUG_BUS_0_SWITCH_RESV_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_CFP_DEBUG_BUS_0_SWITCH_RESV_SHIFT 0
-#define BCHP_SWITCH_CORE_CFP_DEBUG_BUS_0_SWITCH_RESV_DEFAULT 0x00000021
-
-/***************************************************************************
- *CFP_DEBUG_BUS_1 - CFP DEBUG BUS 1Not2Release
- ***************************************************************************/
-/* SWITCH_CORE :: CFP_DEBUG_BUS_1 :: SWITCH_RESV [31:00] */
-#define BCHP_SWITCH_CORE_CFP_DEBUG_BUS_1_SWITCH_RESV_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_CFP_DEBUG_BUS_1_SWITCH_RESV_SHIFT 0
-#define BCHP_SWITCH_CORE_CFP_DEBUG_BUS_1_SWITCH_RESV_DEFAULT 0x00000000
-
-/***************************************************************************
- *WRED_DEBUG_0 - WRED DEBUG 0Not2Release
- ***************************************************************************/
-/* SWITCH_CORE :: WRED_DEBUG_0 :: SWITCH_RESV [31:00] */
-#define BCHP_SWITCH_CORE_WRED_DEBUG_0_SWITCH_RESV_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_WRED_DEBUG_0_SWITCH_RESV_SHIFT 0
-#define BCHP_SWITCH_CORE_WRED_DEBUG_0_SWITCH_RESV_DEFAULT 0x00000000
-
-/***************************************************************************
- *WRED_DEBUG_1 - WRED DEBUG 1Not2Release
- ***************************************************************************/
-/* SWITCH_CORE :: WRED_DEBUG_1 :: SWITCH_RESV [31:00] */
-#define BCHP_SWITCH_CORE_WRED_DEBUG_1_SWITCH_RESV_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_WRED_DEBUG_1_SWITCH_RESV_SHIFT 0
-#define BCHP_SWITCH_CORE_WRED_DEBUG_1_SWITCH_RESV_DEFAULT 0x00000000
-
-/***************************************************************************
- *TOP_MISC_DEBUG_0 - TOP MISC DEBUG 0Not2Release
- ***************************************************************************/
-/* SWITCH_CORE :: TOP_MISC_DEBUG_0 :: SWITCH_RESV [31:00] */
-#define BCHP_SWITCH_CORE_TOP_MISC_DEBUG_0_SWITCH_RESV_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_TOP_MISC_DEBUG_0_SWITCH_RESV_SHIFT 0
-#define BCHP_SWITCH_CORE_TOP_MISC_DEBUG_0_SWITCH_RESV_DEFAULT 0x00000002
-
-/***************************************************************************
- *TOP_MISC_DEBUG_1 - TOP MISC DEBUG 1Not2Release
- ***************************************************************************/
-/* SWITCH_CORE :: TOP_MISC_DEBUG_1 :: SWITCH_RESV [31:00] */
-#define BCHP_SWITCH_CORE_TOP_MISC_DEBUG_1_SWITCH_RESV_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_TOP_MISC_DEBUG_1_SWITCH_RESV_SHIFT 0
-#define BCHP_SWITCH_CORE_TOP_MISC_DEBUG_1_SWITCH_RESV_DEFAULT 0x00000000
-
-/***************************************************************************
- *DIAGREG_BUFCON - DIAGREG BUFCONNot2Release
- ***************************************************************************/
-/* SWITCH_CORE :: DIAGREG_BUFCON :: SWITCH_RESV [31:00] */
-#define BCHP_SWITCH_CORE_DIAGREG_BUFCON_SWITCH_RESV_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_DIAGREG_BUFCON_SWITCH_RESV_SHIFT 0
-#define BCHP_SWITCH_CORE_DIAGREG_BUFCON_SWITCH_RESV_DEFAULT 0x0000fffc
-
-/***************************************************************************
- *TESTBUS_P1588 - TESTBUS P1588Not2Release
- ***************************************************************************/
-/* SWITCH_CORE :: TESTBUS_P1588 :: SWITCH_RESV [31:00] */
-#define BCHP_SWITCH_CORE_TESTBUS_P1588_SWITCH_RESV_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_TESTBUS_P1588_SWITCH_RESV_SHIFT 0
-#define BCHP_SWITCH_CORE_TESTBUS_P1588_SWITCH_RESV_DEFAULT 0x00000000
-
-/***************************************************************************
- *FLOWCON_DEBUG_BUS - FLOWCON DEBUG BUSNot2Release
- ***************************************************************************/
-/* SWITCH_CORE :: FLOWCON_DEBUG_BUS :: SWITCH_RESV [31:00] */
-#define BCHP_SWITCH_CORE_FLOWCON_DEBUG_BUS_SWITCH_RESV_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_FLOWCON_DEBUG_BUS_SWITCH_RESV_SHIFT 0
-#define BCHP_SWITCH_CORE_FLOWCON_DEBUG_BUS_SWITCH_RESV_DEFAULT 0x00000000
-
-/***************************************************************************
- *FC_IMP0_TXQ_THD_RSV_QN_Port_0 - IMP0 Port Queue N Reserved Threshold RegisterNot2Release
- ***************************************************************************/
-/* SWITCH_CORE :: FC_IMP0_TXQ_THD_RSV_QN_Port_0 :: reserved_for_padding0 [31:16] */
-#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_RSV_QN_Port_0_reserved_for_padding0_MASK 0xffff0000
-#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_RSV_QN_Port_0_reserved_for_padding0_SHIFT 16
-
-/* SWITCH_CORE :: FC_IMP0_TXQ_THD_RSV_QN_Port_0 :: SWITCH_RESV [15:11] */
-#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_RSV_QN_Port_0_SWITCH_RESV_MASK 0x0000f800
-#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_RSV_QN_Port_0_SWITCH_RESV_SHIFT 11
-#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_RSV_QN_Port_0_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: FC_IMP0_TXQ_THD_RSV_QN_Port_0 :: TXQ_RSV_THD [10:00] */
-#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_RSV_QN_Port_0_TXQ_RSV_THD_MASK 0x000007ff
-#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_RSV_QN_Port_0_TXQ_RSV_THD_SHIFT 0
-#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_RSV_QN_Port_0_TXQ_RSV_THD_DEFAULT 0x00000018
-
-/***************************************************************************
- *FC_IMP0_TXQ_THD_RSV_QN_Port_1 - IMP0 Port Queue N Reserved Threshold RegisterNot2Release
- ***************************************************************************/
-/* SWITCH_CORE :: FC_IMP0_TXQ_THD_RSV_QN_Port_1 :: reserved_for_padding0 [31:16] */
-#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_RSV_QN_Port_1_reserved_for_padding0_MASK 0xffff0000
-#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_RSV_QN_Port_1_reserved_for_padding0_SHIFT 16
-
-/* SWITCH_CORE :: FC_IMP0_TXQ_THD_RSV_QN_Port_1 :: SWITCH_RESV [15:11] */
-#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_RSV_QN_Port_1_SWITCH_RESV_MASK 0x0000f800
-#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_RSV_QN_Port_1_SWITCH_RESV_SHIFT 11
-#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_RSV_QN_Port_1_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: FC_IMP0_TXQ_THD_RSV_QN_Port_1 :: TXQ_RSV_THD [10:00] */
-#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_RSV_QN_Port_1_TXQ_RSV_THD_MASK 0x000007ff
-#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_RSV_QN_Port_1_TXQ_RSV_THD_SHIFT 0
-#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_RSV_QN_Port_1_TXQ_RSV_THD_DEFAULT 0x00000018
-
-/***************************************************************************
- *FC_IMP0_TXQ_THD_RSV_QN_Port_2 - IMP0 Port Queue N Reserved Threshold RegisterNot2Release
- ***************************************************************************/
-/* SWITCH_CORE :: FC_IMP0_TXQ_THD_RSV_QN_Port_2 :: reserved_for_padding0 [31:16] */
-#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_RSV_QN_Port_2_reserved_for_padding0_MASK 0xffff0000
-#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_RSV_QN_Port_2_reserved_for_padding0_SHIFT 16
-
-/* SWITCH_CORE :: FC_IMP0_TXQ_THD_RSV_QN_Port_2 :: SWITCH_RESV [15:11] */
-#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_RSV_QN_Port_2_SWITCH_RESV_MASK 0x0000f800
-#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_RSV_QN_Port_2_SWITCH_RESV_SHIFT 11
-#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_RSV_QN_Port_2_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: FC_IMP0_TXQ_THD_RSV_QN_Port_2 :: TXQ_RSV_THD [10:00] */
-#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_RSV_QN_Port_2_TXQ_RSV_THD_MASK 0x000007ff
-#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_RSV_QN_Port_2_TXQ_RSV_THD_SHIFT 0
-#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_RSV_QN_Port_2_TXQ_RSV_THD_DEFAULT 0x00000018
-
-/***************************************************************************
- *FC_IMP0_TXQ_THD_RSV_QN_Port_3 - IMP0 Port Queue N Reserved Threshold RegisterNot2Release
- ***************************************************************************/
-/* SWITCH_CORE :: FC_IMP0_TXQ_THD_RSV_QN_Port_3 :: reserved_for_padding0 [31:16] */
-#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_RSV_QN_Port_3_reserved_for_padding0_MASK 0xffff0000
-#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_RSV_QN_Port_3_reserved_for_padding0_SHIFT 16
-
-/* SWITCH_CORE :: FC_IMP0_TXQ_THD_RSV_QN_Port_3 :: SWITCH_RESV [15:11] */
-#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_RSV_QN_Port_3_SWITCH_RESV_MASK 0x0000f800
-#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_RSV_QN_Port_3_SWITCH_RESV_SHIFT 11
-#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_RSV_QN_Port_3_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: FC_IMP0_TXQ_THD_RSV_QN_Port_3 :: TXQ_RSV_THD [10:00] */
-#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_RSV_QN_Port_3_TXQ_RSV_THD_MASK 0x000007ff
-#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_RSV_QN_Port_3_TXQ_RSV_THD_SHIFT 0
-#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_RSV_QN_Port_3_TXQ_RSV_THD_DEFAULT 0x00000018
-
-/***************************************************************************
- *FC_IMP0_TXQ_THD_RSV_QN_Port_4 - IMP0 Port Queue N Reserved Threshold RegisterNot2Release
- ***************************************************************************/
-/* SWITCH_CORE :: FC_IMP0_TXQ_THD_RSV_QN_Port_4 :: reserved_for_padding0 [31:16] */
-#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_RSV_QN_Port_4_reserved_for_padding0_MASK 0xffff0000
-#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_RSV_QN_Port_4_reserved_for_padding0_SHIFT 16
-
-/* SWITCH_CORE :: FC_IMP0_TXQ_THD_RSV_QN_Port_4 :: SWITCH_RESV [15:11] */
-#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_RSV_QN_Port_4_SWITCH_RESV_MASK 0x0000f800
-#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_RSV_QN_Port_4_SWITCH_RESV_SHIFT 11
-#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_RSV_QN_Port_4_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: FC_IMP0_TXQ_THD_RSV_QN_Port_4 :: TXQ_RSV_THD [10:00] */
-#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_RSV_QN_Port_4_TXQ_RSV_THD_MASK 0x000007ff
-#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_RSV_QN_Port_4_TXQ_RSV_THD_SHIFT 0
-#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_RSV_QN_Port_4_TXQ_RSV_THD_DEFAULT 0x00000018
-
-/***************************************************************************
- *FC_IMP0_TXQ_THD_RSV_QN_Port_5 - IMP0 Port Queue N Reserved Threshold RegisterNot2Release
- ***************************************************************************/
-/* SWITCH_CORE :: FC_IMP0_TXQ_THD_RSV_QN_Port_5 :: reserved_for_padding0 [31:16] */
-#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_RSV_QN_Port_5_reserved_for_padding0_MASK 0xffff0000
-#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_RSV_QN_Port_5_reserved_for_padding0_SHIFT 16
-
-/* SWITCH_CORE :: FC_IMP0_TXQ_THD_RSV_QN_Port_5 :: SWITCH_RESV [15:11] */
-#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_RSV_QN_Port_5_SWITCH_RESV_MASK 0x0000f800
-#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_RSV_QN_Port_5_SWITCH_RESV_SHIFT 11
-#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_RSV_QN_Port_5_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: FC_IMP0_TXQ_THD_RSV_QN_Port_5 :: TXQ_RSV_THD [10:00] */
-#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_RSV_QN_Port_5_TXQ_RSV_THD_MASK 0x000007ff
-#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_RSV_QN_Port_5_TXQ_RSV_THD_SHIFT 0
-#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_RSV_QN_Port_5_TXQ_RSV_THD_DEFAULT 0x00000018
-
-/***************************************************************************
- *FC_IMP0_TXQ_THD_RSV_QN_Port_6 - IMP0 Port Queue N Reserved Threshold RegisterNot2Release
- ***************************************************************************/
-/* SWITCH_CORE :: FC_IMP0_TXQ_THD_RSV_QN_Port_6 :: reserved_for_padding0 [31:16] */
-#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_RSV_QN_Port_6_reserved_for_padding0_MASK 0xffff0000
-#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_RSV_QN_Port_6_reserved_for_padding0_SHIFT 16
-
-/* SWITCH_CORE :: FC_IMP0_TXQ_THD_RSV_QN_Port_6 :: SWITCH_RESV [15:11] */
-#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_RSV_QN_Port_6_SWITCH_RESV_MASK 0x0000f800
-#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_RSV_QN_Port_6_SWITCH_RESV_SHIFT 11
-#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_RSV_QN_Port_6_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: FC_IMP0_TXQ_THD_RSV_QN_Port_6 :: TXQ_RSV_THD [10:00] */
-#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_RSV_QN_Port_6_TXQ_RSV_THD_MASK 0x000007ff
-#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_RSV_QN_Port_6_TXQ_RSV_THD_SHIFT 0
-#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_RSV_QN_Port_6_TXQ_RSV_THD_DEFAULT 0x00000018
-
-/***************************************************************************
- *FC_IMP0_TXQ_THD_RSV_QN_Port_7 - IMP0 Port Queue N Reserved Threshold RegisterNot2Release
- ***************************************************************************/
-/* SWITCH_CORE :: FC_IMP0_TXQ_THD_RSV_QN_Port_7 :: reserved_for_padding0 [31:16] */
-#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_RSV_QN_Port_7_reserved_for_padding0_MASK 0xffff0000
-#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_RSV_QN_Port_7_reserved_for_padding0_SHIFT 16
-
-/* SWITCH_CORE :: FC_IMP0_TXQ_THD_RSV_QN_Port_7 :: SWITCH_RESV [15:11] */
-#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_RSV_QN_Port_7_SWITCH_RESV_MASK 0x0000f800
-#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_RSV_QN_Port_7_SWITCH_RESV_SHIFT 11
-#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_RSV_QN_Port_7_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: FC_IMP0_TXQ_THD_RSV_QN_Port_7 :: TXQ_RSV_THD [10:00] */
-#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_RSV_QN_Port_7_TXQ_RSV_THD_MASK 0x000007ff
-#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_RSV_QN_Port_7_TXQ_RSV_THD_SHIFT 0
-#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_RSV_QN_Port_7_TXQ_RSV_THD_DEFAULT 0x00000018
-
-/***************************************************************************
- *FC_IMP0_TXQ_THD_HYST_QN_Port_0 - IMP0 Port Queue N Hysteresis Threshold RegisterNot2Release
- ***************************************************************************/
-/* SWITCH_CORE :: FC_IMP0_TXQ_THD_HYST_QN_Port_0 :: reserved_for_padding0 [31:16] */
-#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_HYST_QN_Port_0_reserved_for_padding0_MASK 0xffff0000
-#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_HYST_QN_Port_0_reserved_for_padding0_SHIFT 16
-
-/* SWITCH_CORE :: FC_IMP0_TXQ_THD_HYST_QN_Port_0 :: SWITCH_RESV [15:11] */
-#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_HYST_QN_Port_0_SWITCH_RESV_MASK 0x0000f800
-#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_HYST_QN_Port_0_SWITCH_RESV_SHIFT 11
-#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_HYST_QN_Port_0_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: FC_IMP0_TXQ_THD_HYST_QN_Port_0 :: TXQ_HYST_THD [10:00] */
-#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_HYST_QN_Port_0_TXQ_HYST_THD_MASK 0x000007ff
-#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_HYST_QN_Port_0_TXQ_HYST_THD_SHIFT 0
-#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_HYST_QN_Port_0_TXQ_HYST_THD_DEFAULT 0x00000063
-
-/***************************************************************************
- *FC_IMP0_TXQ_THD_HYST_QN_Port_1 - IMP0 Port Queue N Hysteresis Threshold RegisterNot2Release
- ***************************************************************************/
-/* SWITCH_CORE :: FC_IMP0_TXQ_THD_HYST_QN_Port_1 :: reserved_for_padding0 [31:16] */
-#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_HYST_QN_Port_1_reserved_for_padding0_MASK 0xffff0000
-#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_HYST_QN_Port_1_reserved_for_padding0_SHIFT 16
-
-/* SWITCH_CORE :: FC_IMP0_TXQ_THD_HYST_QN_Port_1 :: SWITCH_RESV [15:11] */
-#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_HYST_QN_Port_1_SWITCH_RESV_MASK 0x0000f800
-#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_HYST_QN_Port_1_SWITCH_RESV_SHIFT 11
-#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_HYST_QN_Port_1_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: FC_IMP0_TXQ_THD_HYST_QN_Port_1 :: TXQ_HYST_THD [10:00] */
-#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_HYST_QN_Port_1_TXQ_HYST_THD_MASK 0x000007ff
-#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_HYST_QN_Port_1_TXQ_HYST_THD_SHIFT 0
-#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_HYST_QN_Port_1_TXQ_HYST_THD_DEFAULT 0x00000067
-
-/***************************************************************************
- *FC_IMP0_TXQ_THD_HYST_QN_Port_2 - IMP0 Port Queue N Hysteresis Threshold RegisterNot2Release
- ***************************************************************************/
-/* SWITCH_CORE :: FC_IMP0_TXQ_THD_HYST_QN_Port_2 :: reserved_for_padding0 [31:16] */
-#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_HYST_QN_Port_2_reserved_for_padding0_MASK 0xffff0000
-#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_HYST_QN_Port_2_reserved_for_padding0_SHIFT 16
-
-/* SWITCH_CORE :: FC_IMP0_TXQ_THD_HYST_QN_Port_2 :: SWITCH_RESV [15:11] */
-#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_HYST_QN_Port_2_SWITCH_RESV_MASK 0x0000f800
-#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_HYST_QN_Port_2_SWITCH_RESV_SHIFT 11
-#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_HYST_QN_Port_2_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: FC_IMP0_TXQ_THD_HYST_QN_Port_2 :: TXQ_HYST_THD [10:00] */
-#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_HYST_QN_Port_2_TXQ_HYST_THD_MASK 0x000007ff
-#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_HYST_QN_Port_2_TXQ_HYST_THD_SHIFT 0
-#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_HYST_QN_Port_2_TXQ_HYST_THD_DEFAULT 0x0000006b
-
-/***************************************************************************
- *FC_IMP0_TXQ_THD_HYST_QN_Port_3 - IMP0 Port Queue N Hysteresis Threshold RegisterNot2Release
- ***************************************************************************/
-/* SWITCH_CORE :: FC_IMP0_TXQ_THD_HYST_QN_Port_3 :: reserved_for_padding0 [31:16] */
-#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_HYST_QN_Port_3_reserved_for_padding0_MASK 0xffff0000
-#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_HYST_QN_Port_3_reserved_for_padding0_SHIFT 16
-
-/* SWITCH_CORE :: FC_IMP0_TXQ_THD_HYST_QN_Port_3 :: SWITCH_RESV [15:11] */
-#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_HYST_QN_Port_3_SWITCH_RESV_MASK 0x0000f800
-#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_HYST_QN_Port_3_SWITCH_RESV_SHIFT 11
-#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_HYST_QN_Port_3_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: FC_IMP0_TXQ_THD_HYST_QN_Port_3 :: TXQ_HYST_THD [10:00] */
-#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_HYST_QN_Port_3_TXQ_HYST_THD_MASK 0x000007ff
-#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_HYST_QN_Port_3_TXQ_HYST_THD_SHIFT 0
-#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_HYST_QN_Port_3_TXQ_HYST_THD_DEFAULT 0x0000006f
-
-/***************************************************************************
- *FC_IMP0_TXQ_THD_HYST_QN_Port_4 - IMP0 Port Queue N Hysteresis Threshold RegisterNot2Release
- ***************************************************************************/
-/* SWITCH_CORE :: FC_IMP0_TXQ_THD_HYST_QN_Port_4 :: reserved_for_padding0 [31:16] */
-#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_HYST_QN_Port_4_reserved_for_padding0_MASK 0xffff0000
-#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_HYST_QN_Port_4_reserved_for_padding0_SHIFT 16
-
-/* SWITCH_CORE :: FC_IMP0_TXQ_THD_HYST_QN_Port_4 :: SWITCH_RESV [15:11] */
-#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_HYST_QN_Port_4_SWITCH_RESV_MASK 0x0000f800
-#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_HYST_QN_Port_4_SWITCH_RESV_SHIFT 11
-#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_HYST_QN_Port_4_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: FC_IMP0_TXQ_THD_HYST_QN_Port_4 :: TXQ_HYST_THD [10:00] */
-#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_HYST_QN_Port_4_TXQ_HYST_THD_MASK 0x000007ff
-#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_HYST_QN_Port_4_TXQ_HYST_THD_SHIFT 0
-#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_HYST_QN_Port_4_TXQ_HYST_THD_DEFAULT 0x00000073
-
-/***************************************************************************
- *FC_IMP0_TXQ_THD_HYST_QN_Port_5 - IMP0 Port Queue N Hysteresis Threshold RegisterNot2Release
- ***************************************************************************/
-/* SWITCH_CORE :: FC_IMP0_TXQ_THD_HYST_QN_Port_5 :: reserved_for_padding0 [31:16] */
-#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_HYST_QN_Port_5_reserved_for_padding0_MASK 0xffff0000
-#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_HYST_QN_Port_5_reserved_for_padding0_SHIFT 16
-
-/* SWITCH_CORE :: FC_IMP0_TXQ_THD_HYST_QN_Port_5 :: SWITCH_RESV [15:11] */
-#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_HYST_QN_Port_5_SWITCH_RESV_MASK 0x0000f800
-#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_HYST_QN_Port_5_SWITCH_RESV_SHIFT 11
-#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_HYST_QN_Port_5_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: FC_IMP0_TXQ_THD_HYST_QN_Port_5 :: TXQ_HYST_THD [10:00] */
-#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_HYST_QN_Port_5_TXQ_HYST_THD_MASK 0x000007ff
-#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_HYST_QN_Port_5_TXQ_HYST_THD_SHIFT 0
-#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_HYST_QN_Port_5_TXQ_HYST_THD_DEFAULT 0x00000077
-
-/***************************************************************************
- *FC_IMP0_TXQ_THD_HYST_QN_Port_6 - IMP0 Port Queue N Hysteresis Threshold RegisterNot2Release
- ***************************************************************************/
-/* SWITCH_CORE :: FC_IMP0_TXQ_THD_HYST_QN_Port_6 :: reserved_for_padding0 [31:16] */
-#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_HYST_QN_Port_6_reserved_for_padding0_MASK 0xffff0000
-#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_HYST_QN_Port_6_reserved_for_padding0_SHIFT 16
-
-/* SWITCH_CORE :: FC_IMP0_TXQ_THD_HYST_QN_Port_6 :: SWITCH_RESV [15:11] */
-#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_HYST_QN_Port_6_SWITCH_RESV_MASK 0x0000f800
-#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_HYST_QN_Port_6_SWITCH_RESV_SHIFT 11
-#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_HYST_QN_Port_6_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: FC_IMP0_TXQ_THD_HYST_QN_Port_6 :: TXQ_HYST_THD [10:00] */
-#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_HYST_QN_Port_6_TXQ_HYST_THD_MASK 0x000007ff
-#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_HYST_QN_Port_6_TXQ_HYST_THD_SHIFT 0
-#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_HYST_QN_Port_6_TXQ_HYST_THD_DEFAULT 0x0000007b
-
-/***************************************************************************
- *FC_IMP0_TXQ_THD_HYST_QN_Port_7 - IMP0 Port Queue N Hysteresis Threshold RegisterNot2Release
- ***************************************************************************/
-/* SWITCH_CORE :: FC_IMP0_TXQ_THD_HYST_QN_Port_7 :: reserved_for_padding0 [31:16] */
-#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_HYST_QN_Port_7_reserved_for_padding0_MASK 0xffff0000
-#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_HYST_QN_Port_7_reserved_for_padding0_SHIFT 16
-
-/* SWITCH_CORE :: FC_IMP0_TXQ_THD_HYST_QN_Port_7 :: SWITCH_RESV [15:11] */
-#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_HYST_QN_Port_7_SWITCH_RESV_MASK 0x0000f800
-#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_HYST_QN_Port_7_SWITCH_RESV_SHIFT 11
-#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_HYST_QN_Port_7_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: FC_IMP0_TXQ_THD_HYST_QN_Port_7 :: TXQ_HYST_THD [10:00] */
-#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_HYST_QN_Port_7_TXQ_HYST_THD_MASK 0x000007ff
-#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_HYST_QN_Port_7_TXQ_HYST_THD_SHIFT 0
-#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_HYST_QN_Port_7_TXQ_HYST_THD_DEFAULT 0x0000007f
-
-/***************************************************************************
- *FC_IMP0_TXQ_THD_PAUSE_QN_Port_0 - IMP0 Port Queue N Pause Threshold RegisterNot2Release
- ***************************************************************************/
-/* SWITCH_CORE :: FC_IMP0_TXQ_THD_PAUSE_QN_Port_0 :: reserved_for_padding0 [31:16] */
-#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_PAUSE_QN_Port_0_reserved_for_padding0_MASK 0xffff0000
-#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_PAUSE_QN_Port_0_reserved_for_padding0_SHIFT 16
-
-/* SWITCH_CORE :: FC_IMP0_TXQ_THD_PAUSE_QN_Port_0 :: SWITCH_RESV [15:11] */
-#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_PAUSE_QN_Port_0_SWITCH_RESV_MASK 0x0000f800
-#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_PAUSE_QN_Port_0_SWITCH_RESV_SHIFT 11
-#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_PAUSE_QN_Port_0_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: FC_IMP0_TXQ_THD_PAUSE_QN_Port_0 :: TXQ_PAUSE_THD [10:00] */
-#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_PAUSE_QN_Port_0_TXQ_PAUSE_THD_MASK 0x000007ff
-#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_PAUSE_QN_Port_0_TXQ_PAUSE_THD_SHIFT 0
-#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_PAUSE_QN_Port_0_TXQ_PAUSE_THD_DEFAULT 0x000000c7
-
-/***************************************************************************
- *FC_IMP0_TXQ_THD_PAUSE_QN_Port_1 - IMP0 Port Queue N Pause Threshold RegisterNot2Release
- ***************************************************************************/
-/* SWITCH_CORE :: FC_IMP0_TXQ_THD_PAUSE_QN_Port_1 :: reserved_for_padding0 [31:16] */
-#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_PAUSE_QN_Port_1_reserved_for_padding0_MASK 0xffff0000
-#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_PAUSE_QN_Port_1_reserved_for_padding0_SHIFT 16
-
-/* SWITCH_CORE :: FC_IMP0_TXQ_THD_PAUSE_QN_Port_1 :: SWITCH_RESV [15:11] */
-#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_PAUSE_QN_Port_1_SWITCH_RESV_MASK 0x0000f800
-#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_PAUSE_QN_Port_1_SWITCH_RESV_SHIFT 11
-#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_PAUSE_QN_Port_1_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: FC_IMP0_TXQ_THD_PAUSE_QN_Port_1 :: TXQ_PAUSE_THD [10:00] */
-#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_PAUSE_QN_Port_1_TXQ_PAUSE_THD_MASK 0x000007ff
-#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_PAUSE_QN_Port_1_TXQ_PAUSE_THD_SHIFT 0
-#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_PAUSE_QN_Port_1_TXQ_PAUSE_THD_DEFAULT 0x000000cf
-
-/***************************************************************************
- *FC_IMP0_TXQ_THD_PAUSE_QN_Port_2 - IMP0 Port Queue N Pause Threshold RegisterNot2Release
- ***************************************************************************/
-/* SWITCH_CORE :: FC_IMP0_TXQ_THD_PAUSE_QN_Port_2 :: reserved_for_padding0 [31:16] */
-#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_PAUSE_QN_Port_2_reserved_for_padding0_MASK 0xffff0000
-#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_PAUSE_QN_Port_2_reserved_for_padding0_SHIFT 16
-
-/* SWITCH_CORE :: FC_IMP0_TXQ_THD_PAUSE_QN_Port_2 :: SWITCH_RESV [15:11] */
-#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_PAUSE_QN_Port_2_SWITCH_RESV_MASK 0x0000f800
-#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_PAUSE_QN_Port_2_SWITCH_RESV_SHIFT 11
-#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_PAUSE_QN_Port_2_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: FC_IMP0_TXQ_THD_PAUSE_QN_Port_2 :: TXQ_PAUSE_THD [10:00] */
-#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_PAUSE_QN_Port_2_TXQ_PAUSE_THD_MASK 0x000007ff
-#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_PAUSE_QN_Port_2_TXQ_PAUSE_THD_SHIFT 0
-#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_PAUSE_QN_Port_2_TXQ_PAUSE_THD_DEFAULT 0x000000d7
-
-/***************************************************************************
- *FC_IMP0_TXQ_THD_PAUSE_QN_Port_3 - IMP0 Port Queue N Pause Threshold RegisterNot2Release
- ***************************************************************************/
-/* SWITCH_CORE :: FC_IMP0_TXQ_THD_PAUSE_QN_Port_3 :: reserved_for_padding0 [31:16] */
-#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_PAUSE_QN_Port_3_reserved_for_padding0_MASK 0xffff0000
-#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_PAUSE_QN_Port_3_reserved_for_padding0_SHIFT 16
-
-/* SWITCH_CORE :: FC_IMP0_TXQ_THD_PAUSE_QN_Port_3 :: SWITCH_RESV [15:11] */
-#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_PAUSE_QN_Port_3_SWITCH_RESV_MASK 0x0000f800
-#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_PAUSE_QN_Port_3_SWITCH_RESV_SHIFT 11
-#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_PAUSE_QN_Port_3_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: FC_IMP0_TXQ_THD_PAUSE_QN_Port_3 :: TXQ_PAUSE_THD [10:00] */
-#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_PAUSE_QN_Port_3_TXQ_PAUSE_THD_MASK 0x000007ff
-#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_PAUSE_QN_Port_3_TXQ_PAUSE_THD_SHIFT 0
-#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_PAUSE_QN_Port_3_TXQ_PAUSE_THD_DEFAULT 0x000000df
-
-/***************************************************************************
- *FC_IMP0_TXQ_THD_PAUSE_QN_Port_4 - IMP0 Port Queue N Pause Threshold RegisterNot2Release
- ***************************************************************************/
-/* SWITCH_CORE :: FC_IMP0_TXQ_THD_PAUSE_QN_Port_4 :: reserved_for_padding0 [31:16] */
-#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_PAUSE_QN_Port_4_reserved_for_padding0_MASK 0xffff0000
-#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_PAUSE_QN_Port_4_reserved_for_padding0_SHIFT 16
-
-/* SWITCH_CORE :: FC_IMP0_TXQ_THD_PAUSE_QN_Port_4 :: SWITCH_RESV [15:11] */
-#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_PAUSE_QN_Port_4_SWITCH_RESV_MASK 0x0000f800
-#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_PAUSE_QN_Port_4_SWITCH_RESV_SHIFT 11
-#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_PAUSE_QN_Port_4_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: FC_IMP0_TXQ_THD_PAUSE_QN_Port_4 :: TXQ_PAUSE_THD [10:00] */
-#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_PAUSE_QN_Port_4_TXQ_PAUSE_THD_MASK 0x000007ff
-#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_PAUSE_QN_Port_4_TXQ_PAUSE_THD_SHIFT 0
-#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_PAUSE_QN_Port_4_TXQ_PAUSE_THD_DEFAULT 0x000000e7
-
-/***************************************************************************
- *FC_IMP0_TXQ_THD_PAUSE_QN_Port_5 - IMP0 Port Queue N Pause Threshold RegisterNot2Release
- ***************************************************************************/
-/* SWITCH_CORE :: FC_IMP0_TXQ_THD_PAUSE_QN_Port_5 :: reserved_for_padding0 [31:16] */
-#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_PAUSE_QN_Port_5_reserved_for_padding0_MASK 0xffff0000
-#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_PAUSE_QN_Port_5_reserved_for_padding0_SHIFT 16
-
-/* SWITCH_CORE :: FC_IMP0_TXQ_THD_PAUSE_QN_Port_5 :: SWITCH_RESV [15:11] */
-#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_PAUSE_QN_Port_5_SWITCH_RESV_MASK 0x0000f800
-#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_PAUSE_QN_Port_5_SWITCH_RESV_SHIFT 11
-#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_PAUSE_QN_Port_5_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: FC_IMP0_TXQ_THD_PAUSE_QN_Port_5 :: TXQ_PAUSE_THD [10:00] */
-#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_PAUSE_QN_Port_5_TXQ_PAUSE_THD_MASK 0x000007ff
-#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_PAUSE_QN_Port_5_TXQ_PAUSE_THD_SHIFT 0
-#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_PAUSE_QN_Port_5_TXQ_PAUSE_THD_DEFAULT 0x000000ef
-
-/***************************************************************************
- *FC_IMP0_TXQ_THD_PAUSE_QN_Port_6 - IMP0 Port Queue N Pause Threshold RegisterNot2Release
- ***************************************************************************/
-/* SWITCH_CORE :: FC_IMP0_TXQ_THD_PAUSE_QN_Port_6 :: reserved_for_padding0 [31:16] */
-#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_PAUSE_QN_Port_6_reserved_for_padding0_MASK 0xffff0000
-#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_PAUSE_QN_Port_6_reserved_for_padding0_SHIFT 16
-
-/* SWITCH_CORE :: FC_IMP0_TXQ_THD_PAUSE_QN_Port_6 :: SWITCH_RESV [15:11] */
-#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_PAUSE_QN_Port_6_SWITCH_RESV_MASK 0x0000f800
-#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_PAUSE_QN_Port_6_SWITCH_RESV_SHIFT 11
-#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_PAUSE_QN_Port_6_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: FC_IMP0_TXQ_THD_PAUSE_QN_Port_6 :: TXQ_PAUSE_THD [10:00] */
-#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_PAUSE_QN_Port_6_TXQ_PAUSE_THD_MASK 0x000007ff
-#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_PAUSE_QN_Port_6_TXQ_PAUSE_THD_SHIFT 0
-#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_PAUSE_QN_Port_6_TXQ_PAUSE_THD_DEFAULT 0x000000f7
-
-/***************************************************************************
- *FC_IMP0_TXQ_THD_PAUSE_QN_Port_7 - IMP0 Port Queue N Pause Threshold RegisterNot2Release
- ***************************************************************************/
-/* SWITCH_CORE :: FC_IMP0_TXQ_THD_PAUSE_QN_Port_7 :: reserved_for_padding0 [31:16] */
-#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_PAUSE_QN_Port_7_reserved_for_padding0_MASK 0xffff0000
-#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_PAUSE_QN_Port_7_reserved_for_padding0_SHIFT 16
-
-/* SWITCH_CORE :: FC_IMP0_TXQ_THD_PAUSE_QN_Port_7 :: SWITCH_RESV [15:11] */
-#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_PAUSE_QN_Port_7_SWITCH_RESV_MASK 0x0000f800
-#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_PAUSE_QN_Port_7_SWITCH_RESV_SHIFT 11
-#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_PAUSE_QN_Port_7_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: FC_IMP0_TXQ_THD_PAUSE_QN_Port_7 :: TXQ_PAUSE_THD [10:00] */
-#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_PAUSE_QN_Port_7_TXQ_PAUSE_THD_MASK 0x000007ff
-#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_PAUSE_QN_Port_7_TXQ_PAUSE_THD_SHIFT 0
-#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_PAUSE_QN_Port_7_TXQ_PAUSE_THD_DEFAULT 0x000000ff
-
-/***************************************************************************
- *FC_IMP0_TXQ_THD_DROP_QN_Port_0 - IMP0 Port Queue N DROP Threshold RegisterNot2Release
- ***************************************************************************/
-/* SWITCH_CORE :: FC_IMP0_TXQ_THD_DROP_QN_Port_0 :: reserved_for_padding0 [31:16] */
-#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_DROP_QN_Port_0_reserved_for_padding0_MASK 0xffff0000
-#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_DROP_QN_Port_0_reserved_for_padding0_SHIFT 16
-
-/* SWITCH_CORE :: FC_IMP0_TXQ_THD_DROP_QN_Port_0 :: SWITCH_RESV [15:11] */
-#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_DROP_QN_Port_0_SWITCH_RESV_MASK 0x0000f800
-#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_DROP_QN_Port_0_SWITCH_RESV_SHIFT 11
-#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_DROP_QN_Port_0_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: FC_IMP0_TXQ_THD_DROP_QN_Port_0 :: TXQ_DROP_THD [10:00] */
-#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_DROP_QN_Port_0_TXQ_DROP_THD_MASK 0x000007ff
-#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_DROP_QN_Port_0_TXQ_DROP_THD_SHIFT 0
-#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_DROP_QN_Port_0_TXQ_DROP_THD_DEFAULT 0x000005ff
-
-/***************************************************************************
- *FC_IMP0_TXQ_THD_DROP_QN_Port_1 - IMP0 Port Queue N DROP Threshold RegisterNot2Release
- ***************************************************************************/
-/* SWITCH_CORE :: FC_IMP0_TXQ_THD_DROP_QN_Port_1 :: reserved_for_padding0 [31:16] */
-#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_DROP_QN_Port_1_reserved_for_padding0_MASK 0xffff0000
-#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_DROP_QN_Port_1_reserved_for_padding0_SHIFT 16
-
-/* SWITCH_CORE :: FC_IMP0_TXQ_THD_DROP_QN_Port_1 :: SWITCH_RESV [15:11] */
-#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_DROP_QN_Port_1_SWITCH_RESV_MASK 0x0000f800
-#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_DROP_QN_Port_1_SWITCH_RESV_SHIFT 11
-#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_DROP_QN_Port_1_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: FC_IMP0_TXQ_THD_DROP_QN_Port_1 :: TXQ_DROP_THD [10:00] */
-#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_DROP_QN_Port_1_TXQ_DROP_THD_MASK 0x000007ff
-#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_DROP_QN_Port_1_TXQ_DROP_THD_SHIFT 0
-#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_DROP_QN_Port_1_TXQ_DROP_THD_DEFAULT 0x000005ff
-
-/***************************************************************************
- *FC_IMP0_TXQ_THD_DROP_QN_Port_2 - IMP0 Port Queue N DROP Threshold RegisterNot2Release
- ***************************************************************************/
-/* SWITCH_CORE :: FC_IMP0_TXQ_THD_DROP_QN_Port_2 :: reserved_for_padding0 [31:16] */
-#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_DROP_QN_Port_2_reserved_for_padding0_MASK 0xffff0000
-#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_DROP_QN_Port_2_reserved_for_padding0_SHIFT 16
-
-/* SWITCH_CORE :: FC_IMP0_TXQ_THD_DROP_QN_Port_2 :: SWITCH_RESV [15:11] */
-#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_DROP_QN_Port_2_SWITCH_RESV_MASK 0x0000f800
-#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_DROP_QN_Port_2_SWITCH_RESV_SHIFT 11
-#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_DROP_QN_Port_2_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: FC_IMP0_TXQ_THD_DROP_QN_Port_2 :: TXQ_DROP_THD [10:00] */
-#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_DROP_QN_Port_2_TXQ_DROP_THD_MASK 0x000007ff
-#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_DROP_QN_Port_2_TXQ_DROP_THD_SHIFT 0
-#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_DROP_QN_Port_2_TXQ_DROP_THD_DEFAULT 0x000005ff
-
-/***************************************************************************
- *FC_IMP0_TXQ_THD_DROP_QN_Port_3 - IMP0 Port Queue N DROP Threshold RegisterNot2Release
- ***************************************************************************/
-/* SWITCH_CORE :: FC_IMP0_TXQ_THD_DROP_QN_Port_3 :: reserved_for_padding0 [31:16] */
-#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_DROP_QN_Port_3_reserved_for_padding0_MASK 0xffff0000
-#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_DROP_QN_Port_3_reserved_for_padding0_SHIFT 16
-
-/* SWITCH_CORE :: FC_IMP0_TXQ_THD_DROP_QN_Port_3 :: SWITCH_RESV [15:11] */
-#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_DROP_QN_Port_3_SWITCH_RESV_MASK 0x0000f800
-#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_DROP_QN_Port_3_SWITCH_RESV_SHIFT 11
-#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_DROP_QN_Port_3_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: FC_IMP0_TXQ_THD_DROP_QN_Port_3 :: TXQ_DROP_THD [10:00] */
-#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_DROP_QN_Port_3_TXQ_DROP_THD_MASK 0x000007ff
-#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_DROP_QN_Port_3_TXQ_DROP_THD_SHIFT 0
-#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_DROP_QN_Port_3_TXQ_DROP_THD_DEFAULT 0x000005ff
-
-/***************************************************************************
- *FC_IMP0_TXQ_THD_DROP_QN_Port_4 - IMP0 Port Queue N DROP Threshold RegisterNot2Release
- ***************************************************************************/
-/* SWITCH_CORE :: FC_IMP0_TXQ_THD_DROP_QN_Port_4 :: reserved_for_padding0 [31:16] */
-#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_DROP_QN_Port_4_reserved_for_padding0_MASK 0xffff0000
-#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_DROP_QN_Port_4_reserved_for_padding0_SHIFT 16
-
-/* SWITCH_CORE :: FC_IMP0_TXQ_THD_DROP_QN_Port_4 :: SWITCH_RESV [15:11] */
-#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_DROP_QN_Port_4_SWITCH_RESV_MASK 0x0000f800
-#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_DROP_QN_Port_4_SWITCH_RESV_SHIFT 11
-#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_DROP_QN_Port_4_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: FC_IMP0_TXQ_THD_DROP_QN_Port_4 :: TXQ_DROP_THD [10:00] */
-#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_DROP_QN_Port_4_TXQ_DROP_THD_MASK 0x000007ff
-#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_DROP_QN_Port_4_TXQ_DROP_THD_SHIFT 0
-#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_DROP_QN_Port_4_TXQ_DROP_THD_DEFAULT 0x000005ff
-
-/***************************************************************************
- *FC_IMP0_TXQ_THD_DROP_QN_Port_5 - IMP0 Port Queue N DROP Threshold RegisterNot2Release
- ***************************************************************************/
-/* SWITCH_CORE :: FC_IMP0_TXQ_THD_DROP_QN_Port_5 :: reserved_for_padding0 [31:16] */
-#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_DROP_QN_Port_5_reserved_for_padding0_MASK 0xffff0000
-#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_DROP_QN_Port_5_reserved_for_padding0_SHIFT 16
-
-/* SWITCH_CORE :: FC_IMP0_TXQ_THD_DROP_QN_Port_5 :: SWITCH_RESV [15:11] */
-#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_DROP_QN_Port_5_SWITCH_RESV_MASK 0x0000f800
-#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_DROP_QN_Port_5_SWITCH_RESV_SHIFT 11
-#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_DROP_QN_Port_5_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: FC_IMP0_TXQ_THD_DROP_QN_Port_5 :: TXQ_DROP_THD [10:00] */
-#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_DROP_QN_Port_5_TXQ_DROP_THD_MASK 0x000007ff
-#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_DROP_QN_Port_5_TXQ_DROP_THD_SHIFT 0
-#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_DROP_QN_Port_5_TXQ_DROP_THD_DEFAULT 0x000005ff
-
-/***************************************************************************
- *FC_IMP0_TXQ_THD_DROP_QN_Port_6 - IMP0 Port Queue N DROP Threshold RegisterNot2Release
- ***************************************************************************/
-/* SWITCH_CORE :: FC_IMP0_TXQ_THD_DROP_QN_Port_6 :: reserved_for_padding0 [31:16] */
-#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_DROP_QN_Port_6_reserved_for_padding0_MASK 0xffff0000
-#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_DROP_QN_Port_6_reserved_for_padding0_SHIFT 16
-
-/* SWITCH_CORE :: FC_IMP0_TXQ_THD_DROP_QN_Port_6 :: SWITCH_RESV [15:11] */
-#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_DROP_QN_Port_6_SWITCH_RESV_MASK 0x0000f800
-#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_DROP_QN_Port_6_SWITCH_RESV_SHIFT 11
-#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_DROP_QN_Port_6_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: FC_IMP0_TXQ_THD_DROP_QN_Port_6 :: TXQ_DROP_THD [10:00] */
-#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_DROP_QN_Port_6_TXQ_DROP_THD_MASK 0x000007ff
-#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_DROP_QN_Port_6_TXQ_DROP_THD_SHIFT 0
-#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_DROP_QN_Port_6_TXQ_DROP_THD_DEFAULT 0x000005ff
-
-/***************************************************************************
- *FC_IMP0_TXQ_THD_DROP_QN_Port_7 - IMP0 Port Queue N DROP Threshold RegisterNot2Release
- ***************************************************************************/
-/* SWITCH_CORE :: FC_IMP0_TXQ_THD_DROP_QN_Port_7 :: reserved_for_padding0 [31:16] */
-#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_DROP_QN_Port_7_reserved_for_padding0_MASK 0xffff0000
-#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_DROP_QN_Port_7_reserved_for_padding0_SHIFT 16
-
-/* SWITCH_CORE :: FC_IMP0_TXQ_THD_DROP_QN_Port_7 :: SWITCH_RESV [15:11] */
-#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_DROP_QN_Port_7_SWITCH_RESV_MASK 0x0000f800
-#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_DROP_QN_Port_7_SWITCH_RESV_SHIFT 11
-#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_DROP_QN_Port_7_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: FC_IMP0_TXQ_THD_DROP_QN_Port_7 :: TXQ_DROP_THD [10:00] */
-#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_DROP_QN_Port_7_TXQ_DROP_THD_MASK 0x000007ff
-#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_DROP_QN_Port_7_TXQ_DROP_THD_SHIFT 0
-#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_DROP_QN_Port_7_TXQ_DROP_THD_DEFAULT 0x000005ff
-
-/***************************************************************************
- *FC_IMP0_TOTAL_THD_HYST_QN_Port_0 - IMP0 Port Queue N Total Hysteresis Threshold RegisterNot2Release
- ***************************************************************************/
-/* SWITCH_CORE :: FC_IMP0_TOTAL_THD_HYST_QN_Port_0 :: reserved_for_padding0 [31:16] */
-#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_HYST_QN_Port_0_reserved_for_padding0_MASK 0xffff0000
-#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_HYST_QN_Port_0_reserved_for_padding0_SHIFT 16
-
-/* SWITCH_CORE :: FC_IMP0_TOTAL_THD_HYST_QN_Port_0 :: SWITCH_RESV [15:11] */
-#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_HYST_QN_Port_0_SWITCH_RESV_MASK 0x0000f800
-#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_HYST_QN_Port_0_SWITCH_RESV_SHIFT 11
-#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_HYST_QN_Port_0_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: FC_IMP0_TOTAL_THD_HYST_QN_Port_0 :: TOTAL_HYST_THD [10:00] */
-#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_HYST_QN_Port_0_TOTAL_HYST_THD_MASK 0x000007ff
-#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_HYST_QN_Port_0_TOTAL_HYST_THD_SHIFT 0
-#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_HYST_QN_Port_0_TOTAL_HYST_THD_DEFAULT 0x000003bf
-
-/***************************************************************************
- *FC_IMP0_TOTAL_THD_HYST_QN_Port_1 - IMP0 Port Queue N Total Hysteresis Threshold RegisterNot2Release
- ***************************************************************************/
-/* SWITCH_CORE :: FC_IMP0_TOTAL_THD_HYST_QN_Port_1 :: reserved_for_padding0 [31:16] */
-#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_HYST_QN_Port_1_reserved_for_padding0_MASK 0xffff0000
-#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_HYST_QN_Port_1_reserved_for_padding0_SHIFT 16
-
-/* SWITCH_CORE :: FC_IMP0_TOTAL_THD_HYST_QN_Port_1 :: SWITCH_RESV [15:11] */
-#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_HYST_QN_Port_1_SWITCH_RESV_MASK 0x0000f800
-#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_HYST_QN_Port_1_SWITCH_RESV_SHIFT 11
-#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_HYST_QN_Port_1_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: FC_IMP0_TOTAL_THD_HYST_QN_Port_1 :: TOTAL_HYST_THD [10:00] */
-#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_HYST_QN_Port_1_TOTAL_HYST_THD_MASK 0x000007ff
-#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_HYST_QN_Port_1_TOTAL_HYST_THD_SHIFT 0
-#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_HYST_QN_Port_1_TOTAL_HYST_THD_DEFAULT 0x000003bf
-
-/***************************************************************************
- *FC_IMP0_TOTAL_THD_HYST_QN_Port_2 - IMP0 Port Queue N Total Hysteresis Threshold RegisterNot2Release
- ***************************************************************************/
-/* SWITCH_CORE :: FC_IMP0_TOTAL_THD_HYST_QN_Port_2 :: reserved_for_padding0 [31:16] */
-#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_HYST_QN_Port_2_reserved_for_padding0_MASK 0xffff0000
-#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_HYST_QN_Port_2_reserved_for_padding0_SHIFT 16
-
-/* SWITCH_CORE :: FC_IMP0_TOTAL_THD_HYST_QN_Port_2 :: SWITCH_RESV [15:11] */
-#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_HYST_QN_Port_2_SWITCH_RESV_MASK 0x0000f800
-#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_HYST_QN_Port_2_SWITCH_RESV_SHIFT 11
-#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_HYST_QN_Port_2_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: FC_IMP0_TOTAL_THD_HYST_QN_Port_2 :: TOTAL_HYST_THD [10:00] */
-#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_HYST_QN_Port_2_TOTAL_HYST_THD_MASK 0x000007ff
-#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_HYST_QN_Port_2_TOTAL_HYST_THD_SHIFT 0
-#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_HYST_QN_Port_2_TOTAL_HYST_THD_DEFAULT 0x000003bf
-
-/***************************************************************************
- *FC_IMP0_TOTAL_THD_HYST_QN_Port_3 - IMP0 Port Queue N Total Hysteresis Threshold RegisterNot2Release
- ***************************************************************************/
-/* SWITCH_CORE :: FC_IMP0_TOTAL_THD_HYST_QN_Port_3 :: reserved_for_padding0 [31:16] */
-#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_HYST_QN_Port_3_reserved_for_padding0_MASK 0xffff0000
-#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_HYST_QN_Port_3_reserved_for_padding0_SHIFT 16
-
-/* SWITCH_CORE :: FC_IMP0_TOTAL_THD_HYST_QN_Port_3 :: SWITCH_RESV [15:11] */
-#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_HYST_QN_Port_3_SWITCH_RESV_MASK 0x0000f800
-#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_HYST_QN_Port_3_SWITCH_RESV_SHIFT 11
-#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_HYST_QN_Port_3_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: FC_IMP0_TOTAL_THD_HYST_QN_Port_3 :: TOTAL_HYST_THD [10:00] */
-#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_HYST_QN_Port_3_TOTAL_HYST_THD_MASK 0x000007ff
-#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_HYST_QN_Port_3_TOTAL_HYST_THD_SHIFT 0
-#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_HYST_QN_Port_3_TOTAL_HYST_THD_DEFAULT 0x000003bf
-
-/***************************************************************************
- *FC_IMP0_TOTAL_THD_HYST_QN_Port_4 - IMP0 Port Queue N Total Hysteresis Threshold RegisterNot2Release
- ***************************************************************************/
-/* SWITCH_CORE :: FC_IMP0_TOTAL_THD_HYST_QN_Port_4 :: reserved_for_padding0 [31:16] */
-#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_HYST_QN_Port_4_reserved_for_padding0_MASK 0xffff0000
-#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_HYST_QN_Port_4_reserved_for_padding0_SHIFT 16
-
-/* SWITCH_CORE :: FC_IMP0_TOTAL_THD_HYST_QN_Port_4 :: SWITCH_RESV [15:11] */
-#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_HYST_QN_Port_4_SWITCH_RESV_MASK 0x0000f800
-#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_HYST_QN_Port_4_SWITCH_RESV_SHIFT 11
-#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_HYST_QN_Port_4_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: FC_IMP0_TOTAL_THD_HYST_QN_Port_4 :: TOTAL_HYST_THD [10:00] */
-#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_HYST_QN_Port_4_TOTAL_HYST_THD_MASK 0x000007ff
-#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_HYST_QN_Port_4_TOTAL_HYST_THD_SHIFT 0
-#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_HYST_QN_Port_4_TOTAL_HYST_THD_DEFAULT 0x000003bf
-
-/***************************************************************************
- *FC_IMP0_TOTAL_THD_HYST_QN_Port_5 - IMP0 Port Queue N Total Hysteresis Threshold RegisterNot2Release
- ***************************************************************************/
-/* SWITCH_CORE :: FC_IMP0_TOTAL_THD_HYST_QN_Port_5 :: reserved_for_padding0 [31:16] */
-#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_HYST_QN_Port_5_reserved_for_padding0_MASK 0xffff0000
-#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_HYST_QN_Port_5_reserved_for_padding0_SHIFT 16
-
-/* SWITCH_CORE :: FC_IMP0_TOTAL_THD_HYST_QN_Port_5 :: SWITCH_RESV [15:11] */
-#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_HYST_QN_Port_5_SWITCH_RESV_MASK 0x0000f800
-#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_HYST_QN_Port_5_SWITCH_RESV_SHIFT 11
-#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_HYST_QN_Port_5_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: FC_IMP0_TOTAL_THD_HYST_QN_Port_5 :: TOTAL_HYST_THD [10:00] */
-#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_HYST_QN_Port_5_TOTAL_HYST_THD_MASK 0x000007ff
-#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_HYST_QN_Port_5_TOTAL_HYST_THD_SHIFT 0
-#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_HYST_QN_Port_5_TOTAL_HYST_THD_DEFAULT 0x000003bf
-
-/***************************************************************************
- *FC_IMP0_TOTAL_THD_HYST_QN_Port_6 - IMP0 Port Queue N Total Hysteresis Threshold RegisterNot2Release
- ***************************************************************************/
-/* SWITCH_CORE :: FC_IMP0_TOTAL_THD_HYST_QN_Port_6 :: reserved_for_padding0 [31:16] */
-#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_HYST_QN_Port_6_reserved_for_padding0_MASK 0xffff0000
-#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_HYST_QN_Port_6_reserved_for_padding0_SHIFT 16
-
-/* SWITCH_CORE :: FC_IMP0_TOTAL_THD_HYST_QN_Port_6 :: SWITCH_RESV [15:11] */
-#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_HYST_QN_Port_6_SWITCH_RESV_MASK 0x0000f800
-#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_HYST_QN_Port_6_SWITCH_RESV_SHIFT 11
-#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_HYST_QN_Port_6_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: FC_IMP0_TOTAL_THD_HYST_QN_Port_6 :: TOTAL_HYST_THD [10:00] */
-#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_HYST_QN_Port_6_TOTAL_HYST_THD_MASK 0x000007ff
-#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_HYST_QN_Port_6_TOTAL_HYST_THD_SHIFT 0
-#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_HYST_QN_Port_6_TOTAL_HYST_THD_DEFAULT 0x000003bf
-
-/***************************************************************************
- *FC_IMP0_TOTAL_THD_HYST_QN_Port_7 - IMP0 Port Queue N Total Hysteresis Threshold RegisterNot2Release
- ***************************************************************************/
-/* SWITCH_CORE :: FC_IMP0_TOTAL_THD_HYST_QN_Port_7 :: reserved_for_padding0 [31:16] */
-#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_HYST_QN_Port_7_reserved_for_padding0_MASK 0xffff0000
-#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_HYST_QN_Port_7_reserved_for_padding0_SHIFT 16
-
-/* SWITCH_CORE :: FC_IMP0_TOTAL_THD_HYST_QN_Port_7 :: SWITCH_RESV [15:11] */
-#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_HYST_QN_Port_7_SWITCH_RESV_MASK 0x0000f800
-#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_HYST_QN_Port_7_SWITCH_RESV_SHIFT 11
-#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_HYST_QN_Port_7_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: FC_IMP0_TOTAL_THD_HYST_QN_Port_7 :: TOTAL_HYST_THD [10:00] */
-#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_HYST_QN_Port_7_TOTAL_HYST_THD_MASK 0x000007ff
-#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_HYST_QN_Port_7_TOTAL_HYST_THD_SHIFT 0
-#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_HYST_QN_Port_7_TOTAL_HYST_THD_DEFAULT 0x000003bf
-
-/***************************************************************************
- *FC_IMP0_TOTAL_THD_PAUSE_QN_Port_0 - IMP0 Port Queue N Total Pause Threshold RegisterNot2Release
- ***************************************************************************/
-/* SWITCH_CORE :: FC_IMP0_TOTAL_THD_PAUSE_QN_Port_0 :: reserved_for_padding0 [31:16] */
-#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_PAUSE_QN_Port_0_reserved_for_padding0_MASK 0xffff0000
-#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_PAUSE_QN_Port_0_reserved_for_padding0_SHIFT 16
-
-/* SWITCH_CORE :: FC_IMP0_TOTAL_THD_PAUSE_QN_Port_0 :: SWITCH_RESV [15:11] */
-#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_PAUSE_QN_Port_0_SWITCH_RESV_MASK 0x0000f800
-#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_PAUSE_QN_Port_0_SWITCH_RESV_SHIFT 11
-#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_PAUSE_QN_Port_0_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: FC_IMP0_TOTAL_THD_PAUSE_QN_Port_0 :: TOTAL_PAUSE_THD [10:00] */
-#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_PAUSE_QN_Port_0_TOTAL_PAUSE_THD_MASK 0x000007ff
-#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_PAUSE_QN_Port_0_TOTAL_PAUSE_THD_SHIFT 0
-#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_PAUSE_QN_Port_0_TOTAL_PAUSE_THD_DEFAULT 0x0000043f
-
-/***************************************************************************
- *FC_IMP0_TOTAL_THD_PAUSE_QN_Port_1 - IMP0 Port Queue N Total Pause Threshold RegisterNot2Release
- ***************************************************************************/
-/* SWITCH_CORE :: FC_IMP0_TOTAL_THD_PAUSE_QN_Port_1 :: reserved_for_padding0 [31:16] */
-#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_PAUSE_QN_Port_1_reserved_for_padding0_MASK 0xffff0000
-#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_PAUSE_QN_Port_1_reserved_for_padding0_SHIFT 16
-
-/* SWITCH_CORE :: FC_IMP0_TOTAL_THD_PAUSE_QN_Port_1 :: SWITCH_RESV [15:11] */
-#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_PAUSE_QN_Port_1_SWITCH_RESV_MASK 0x0000f800
-#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_PAUSE_QN_Port_1_SWITCH_RESV_SHIFT 11
-#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_PAUSE_QN_Port_1_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: FC_IMP0_TOTAL_THD_PAUSE_QN_Port_1 :: TOTAL_PAUSE_THD [10:00] */
-#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_PAUSE_QN_Port_1_TOTAL_PAUSE_THD_MASK 0x000007ff
-#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_PAUSE_QN_Port_1_TOTAL_PAUSE_THD_SHIFT 0
-#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_PAUSE_QN_Port_1_TOTAL_PAUSE_THD_DEFAULT 0x00000447
-
-/***************************************************************************
- *FC_IMP0_TOTAL_THD_PAUSE_QN_Port_2 - IMP0 Port Queue N Total Pause Threshold RegisterNot2Release
- ***************************************************************************/
-/* SWITCH_CORE :: FC_IMP0_TOTAL_THD_PAUSE_QN_Port_2 :: reserved_for_padding0 [31:16] */
-#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_PAUSE_QN_Port_2_reserved_for_padding0_MASK 0xffff0000
-#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_PAUSE_QN_Port_2_reserved_for_padding0_SHIFT 16
-
-/* SWITCH_CORE :: FC_IMP0_TOTAL_THD_PAUSE_QN_Port_2 :: SWITCH_RESV [15:11] */
-#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_PAUSE_QN_Port_2_SWITCH_RESV_MASK 0x0000f800
-#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_PAUSE_QN_Port_2_SWITCH_RESV_SHIFT 11
-#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_PAUSE_QN_Port_2_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: FC_IMP0_TOTAL_THD_PAUSE_QN_Port_2 :: TOTAL_PAUSE_THD [10:00] */
-#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_PAUSE_QN_Port_2_TOTAL_PAUSE_THD_MASK 0x000007ff
-#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_PAUSE_QN_Port_2_TOTAL_PAUSE_THD_SHIFT 0
-#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_PAUSE_QN_Port_2_TOTAL_PAUSE_THD_DEFAULT 0x0000044f
-
-/***************************************************************************
- *FC_IMP0_TOTAL_THD_PAUSE_QN_Port_3 - IMP0 Port Queue N Total Pause Threshold RegisterNot2Release
- ***************************************************************************/
-/* SWITCH_CORE :: FC_IMP0_TOTAL_THD_PAUSE_QN_Port_3 :: reserved_for_padding0 [31:16] */
-#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_PAUSE_QN_Port_3_reserved_for_padding0_MASK 0xffff0000
-#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_PAUSE_QN_Port_3_reserved_for_padding0_SHIFT 16
-
-/* SWITCH_CORE :: FC_IMP0_TOTAL_THD_PAUSE_QN_Port_3 :: SWITCH_RESV [15:11] */
-#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_PAUSE_QN_Port_3_SWITCH_RESV_MASK 0x0000f800
-#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_PAUSE_QN_Port_3_SWITCH_RESV_SHIFT 11
-#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_PAUSE_QN_Port_3_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: FC_IMP0_TOTAL_THD_PAUSE_QN_Port_3 :: TOTAL_PAUSE_THD [10:00] */
-#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_PAUSE_QN_Port_3_TOTAL_PAUSE_THD_MASK 0x000007ff
-#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_PAUSE_QN_Port_3_TOTAL_PAUSE_THD_SHIFT 0
-#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_PAUSE_QN_Port_3_TOTAL_PAUSE_THD_DEFAULT 0x00000457
-
-/***************************************************************************
- *FC_IMP0_TOTAL_THD_PAUSE_QN_Port_4 - IMP0 Port Queue N Total Pause Threshold RegisterNot2Release
- ***************************************************************************/
-/* SWITCH_CORE :: FC_IMP0_TOTAL_THD_PAUSE_QN_Port_4 :: reserved_for_padding0 [31:16] */
-#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_PAUSE_QN_Port_4_reserved_for_padding0_MASK 0xffff0000
-#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_PAUSE_QN_Port_4_reserved_for_padding0_SHIFT 16
-
-/* SWITCH_CORE :: FC_IMP0_TOTAL_THD_PAUSE_QN_Port_4 :: SWITCH_RESV [15:11] */
-#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_PAUSE_QN_Port_4_SWITCH_RESV_MASK 0x0000f800
-#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_PAUSE_QN_Port_4_SWITCH_RESV_SHIFT 11
-#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_PAUSE_QN_Port_4_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: FC_IMP0_TOTAL_THD_PAUSE_QN_Port_4 :: TOTAL_PAUSE_THD [10:00] */
-#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_PAUSE_QN_Port_4_TOTAL_PAUSE_THD_MASK 0x000007ff
-#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_PAUSE_QN_Port_4_TOTAL_PAUSE_THD_SHIFT 0
-#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_PAUSE_QN_Port_4_TOTAL_PAUSE_THD_DEFAULT 0x0000045f
-
-/***************************************************************************
- *FC_IMP0_TOTAL_THD_PAUSE_QN_Port_5 - IMP0 Port Queue N Total Pause Threshold RegisterNot2Release
- ***************************************************************************/
-/* SWITCH_CORE :: FC_IMP0_TOTAL_THD_PAUSE_QN_Port_5 :: reserved_for_padding0 [31:16] */
-#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_PAUSE_QN_Port_5_reserved_for_padding0_MASK 0xffff0000
-#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_PAUSE_QN_Port_5_reserved_for_padding0_SHIFT 16
-
-/* SWITCH_CORE :: FC_IMP0_TOTAL_THD_PAUSE_QN_Port_5 :: SWITCH_RESV [15:11] */
-#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_PAUSE_QN_Port_5_SWITCH_RESV_MASK 0x0000f800
-#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_PAUSE_QN_Port_5_SWITCH_RESV_SHIFT 11
-#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_PAUSE_QN_Port_5_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: FC_IMP0_TOTAL_THD_PAUSE_QN_Port_5 :: TOTAL_PAUSE_THD [10:00] */
-#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_PAUSE_QN_Port_5_TOTAL_PAUSE_THD_MASK 0x000007ff
-#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_PAUSE_QN_Port_5_TOTAL_PAUSE_THD_SHIFT 0
-#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_PAUSE_QN_Port_5_TOTAL_PAUSE_THD_DEFAULT 0x00000467
-
-/***************************************************************************
- *FC_IMP0_TOTAL_THD_PAUSE_QN_Port_6 - IMP0 Port Queue N Total Pause Threshold RegisterNot2Release
- ***************************************************************************/
-/* SWITCH_CORE :: FC_IMP0_TOTAL_THD_PAUSE_QN_Port_6 :: reserved_for_padding0 [31:16] */
-#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_PAUSE_QN_Port_6_reserved_for_padding0_MASK 0xffff0000
-#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_PAUSE_QN_Port_6_reserved_for_padding0_SHIFT 16
-
-/* SWITCH_CORE :: FC_IMP0_TOTAL_THD_PAUSE_QN_Port_6 :: SWITCH_RESV [15:11] */
-#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_PAUSE_QN_Port_6_SWITCH_RESV_MASK 0x0000f800
-#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_PAUSE_QN_Port_6_SWITCH_RESV_SHIFT 11
-#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_PAUSE_QN_Port_6_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: FC_IMP0_TOTAL_THD_PAUSE_QN_Port_6 :: TOTAL_PAUSE_THD [10:00] */
-#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_PAUSE_QN_Port_6_TOTAL_PAUSE_THD_MASK 0x000007ff
-#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_PAUSE_QN_Port_6_TOTAL_PAUSE_THD_SHIFT 0
-#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_PAUSE_QN_Port_6_TOTAL_PAUSE_THD_DEFAULT 0x0000046f
-
-/***************************************************************************
- *FC_IMP0_TOTAL_THD_PAUSE_QN_Port_7 - IMP0 Port Queue N Total Pause Threshold RegisterNot2Release
- ***************************************************************************/
-/* SWITCH_CORE :: FC_IMP0_TOTAL_THD_PAUSE_QN_Port_7 :: reserved_for_padding0 [31:16] */
-#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_PAUSE_QN_Port_7_reserved_for_padding0_MASK 0xffff0000
-#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_PAUSE_QN_Port_7_reserved_for_padding0_SHIFT 16
-
-/* SWITCH_CORE :: FC_IMP0_TOTAL_THD_PAUSE_QN_Port_7 :: SWITCH_RESV [15:11] */
-#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_PAUSE_QN_Port_7_SWITCH_RESV_MASK 0x0000f800
-#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_PAUSE_QN_Port_7_SWITCH_RESV_SHIFT 11
-#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_PAUSE_QN_Port_7_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: FC_IMP0_TOTAL_THD_PAUSE_QN_Port_7 :: TOTAL_PAUSE_THD [10:00] */
-#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_PAUSE_QN_Port_7_TOTAL_PAUSE_THD_MASK 0x000007ff
-#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_PAUSE_QN_Port_7_TOTAL_PAUSE_THD_SHIFT 0
-#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_PAUSE_QN_Port_7_TOTAL_PAUSE_THD_DEFAULT 0x00000477
-
-/***************************************************************************
- *FC_IMP0_TOTAL_THD_DROP_QN_Port_0 - IMP0 Port Queue N Total DROP Threshold RegisterNot2Release
- ***************************************************************************/
-/* SWITCH_CORE :: FC_IMP0_TOTAL_THD_DROP_QN_Port_0 :: reserved_for_padding0 [31:16] */
-#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_DROP_QN_Port_0_reserved_for_padding0_MASK 0xffff0000
-#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_DROP_QN_Port_0_reserved_for_padding0_SHIFT 16
-
-/* SWITCH_CORE :: FC_IMP0_TOTAL_THD_DROP_QN_Port_0 :: SWITCH_RESV [15:11] */
-#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_DROP_QN_Port_0_SWITCH_RESV_MASK 0x0000f800
-#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_DROP_QN_Port_0_SWITCH_RESV_SHIFT 11
-#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_DROP_QN_Port_0_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: FC_IMP0_TOTAL_THD_DROP_QN_Port_0 :: TOTAL_DROP_THD [10:00] */
-#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_DROP_QN_Port_0_TOTAL_DROP_THD_MASK 0x000007ff
-#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_DROP_QN_Port_0_TOTAL_DROP_THD_SHIFT 0
-#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_DROP_QN_Port_0_TOTAL_DROP_THD_DEFAULT 0x000005bf
-
-/***************************************************************************
- *FC_IMP0_TOTAL_THD_DROP_QN_Port_1 - IMP0 Port Queue N Total DROP Threshold RegisterNot2Release
- ***************************************************************************/
-/* SWITCH_CORE :: FC_IMP0_TOTAL_THD_DROP_QN_Port_1 :: reserved_for_padding0 [31:16] */
-#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_DROP_QN_Port_1_reserved_for_padding0_MASK 0xffff0000
-#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_DROP_QN_Port_1_reserved_for_padding0_SHIFT 16
-
-/* SWITCH_CORE :: FC_IMP0_TOTAL_THD_DROP_QN_Port_1 :: SWITCH_RESV [15:11] */
-#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_DROP_QN_Port_1_SWITCH_RESV_MASK 0x0000f800
-#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_DROP_QN_Port_1_SWITCH_RESV_SHIFT 11
-#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_DROP_QN_Port_1_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: FC_IMP0_TOTAL_THD_DROP_QN_Port_1 :: TOTAL_DROP_THD [10:00] */
-#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_DROP_QN_Port_1_TOTAL_DROP_THD_MASK 0x000007ff
-#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_DROP_QN_Port_1_TOTAL_DROP_THD_SHIFT 0
-#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_DROP_QN_Port_1_TOTAL_DROP_THD_DEFAULT 0x000005c7
-
-/***************************************************************************
- *FC_IMP0_TOTAL_THD_DROP_QN_Port_2 - IMP0 Port Queue N Total DROP Threshold RegisterNot2Release
- ***************************************************************************/
-/* SWITCH_CORE :: FC_IMP0_TOTAL_THD_DROP_QN_Port_2 :: reserved_for_padding0 [31:16] */
-#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_DROP_QN_Port_2_reserved_for_padding0_MASK 0xffff0000
-#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_DROP_QN_Port_2_reserved_for_padding0_SHIFT 16
-
-/* SWITCH_CORE :: FC_IMP0_TOTAL_THD_DROP_QN_Port_2 :: SWITCH_RESV [15:11] */
-#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_DROP_QN_Port_2_SWITCH_RESV_MASK 0x0000f800
-#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_DROP_QN_Port_2_SWITCH_RESV_SHIFT 11
-#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_DROP_QN_Port_2_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: FC_IMP0_TOTAL_THD_DROP_QN_Port_2 :: TOTAL_DROP_THD [10:00] */
-#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_DROP_QN_Port_2_TOTAL_DROP_THD_MASK 0x000007ff
-#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_DROP_QN_Port_2_TOTAL_DROP_THD_SHIFT 0
-#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_DROP_QN_Port_2_TOTAL_DROP_THD_DEFAULT 0x000005cf
-
-/***************************************************************************
- *FC_IMP0_TOTAL_THD_DROP_QN_Port_3 - IMP0 Port Queue N Total DROP Threshold RegisterNot2Release
- ***************************************************************************/
-/* SWITCH_CORE :: FC_IMP0_TOTAL_THD_DROP_QN_Port_3 :: reserved_for_padding0 [31:16] */
-#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_DROP_QN_Port_3_reserved_for_padding0_MASK 0xffff0000
-#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_DROP_QN_Port_3_reserved_for_padding0_SHIFT 16
-
-/* SWITCH_CORE :: FC_IMP0_TOTAL_THD_DROP_QN_Port_3 :: SWITCH_RESV [15:11] */
-#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_DROP_QN_Port_3_SWITCH_RESV_MASK 0x0000f800
-#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_DROP_QN_Port_3_SWITCH_RESV_SHIFT 11
-#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_DROP_QN_Port_3_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: FC_IMP0_TOTAL_THD_DROP_QN_Port_3 :: TOTAL_DROP_THD [10:00] */
-#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_DROP_QN_Port_3_TOTAL_DROP_THD_MASK 0x000007ff
-#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_DROP_QN_Port_3_TOTAL_DROP_THD_SHIFT 0
-#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_DROP_QN_Port_3_TOTAL_DROP_THD_DEFAULT 0x000005d7
-
-/***************************************************************************
- *FC_IMP0_TOTAL_THD_DROP_QN_Port_4 - IMP0 Port Queue N Total DROP Threshold RegisterNot2Release
- ***************************************************************************/
-/* SWITCH_CORE :: FC_IMP0_TOTAL_THD_DROP_QN_Port_4 :: reserved_for_padding0 [31:16] */
-#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_DROP_QN_Port_4_reserved_for_padding0_MASK 0xffff0000
-#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_DROP_QN_Port_4_reserved_for_padding0_SHIFT 16
-
-/* SWITCH_CORE :: FC_IMP0_TOTAL_THD_DROP_QN_Port_4 :: SWITCH_RESV [15:11] */
-#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_DROP_QN_Port_4_SWITCH_RESV_MASK 0x0000f800
-#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_DROP_QN_Port_4_SWITCH_RESV_SHIFT 11
-#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_DROP_QN_Port_4_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: FC_IMP0_TOTAL_THD_DROP_QN_Port_4 :: TOTAL_DROP_THD [10:00] */
-#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_DROP_QN_Port_4_TOTAL_DROP_THD_MASK 0x000007ff
-#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_DROP_QN_Port_4_TOTAL_DROP_THD_SHIFT 0
-#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_DROP_QN_Port_4_TOTAL_DROP_THD_DEFAULT 0x000005df
-
-/***************************************************************************
- *FC_IMP0_TOTAL_THD_DROP_QN_Port_5 - IMP0 Port Queue N Total DROP Threshold RegisterNot2Release
- ***************************************************************************/
-/* SWITCH_CORE :: FC_IMP0_TOTAL_THD_DROP_QN_Port_5 :: reserved_for_padding0 [31:16] */
-#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_DROP_QN_Port_5_reserved_for_padding0_MASK 0xffff0000
-#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_DROP_QN_Port_5_reserved_for_padding0_SHIFT 16
-
-/* SWITCH_CORE :: FC_IMP0_TOTAL_THD_DROP_QN_Port_5 :: SWITCH_RESV [15:11] */
-#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_DROP_QN_Port_5_SWITCH_RESV_MASK 0x0000f800
-#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_DROP_QN_Port_5_SWITCH_RESV_SHIFT 11
-#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_DROP_QN_Port_5_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: FC_IMP0_TOTAL_THD_DROP_QN_Port_5 :: TOTAL_DROP_THD [10:00] */
-#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_DROP_QN_Port_5_TOTAL_DROP_THD_MASK 0x000007ff
-#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_DROP_QN_Port_5_TOTAL_DROP_THD_SHIFT 0
-#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_DROP_QN_Port_5_TOTAL_DROP_THD_DEFAULT 0x000005e7
-
-/***************************************************************************
- *FC_IMP0_TOTAL_THD_DROP_QN_Port_6 - IMP0 Port Queue N Total DROP Threshold RegisterNot2Release
- ***************************************************************************/
-/* SWITCH_CORE :: FC_IMP0_TOTAL_THD_DROP_QN_Port_6 :: reserved_for_padding0 [31:16] */
-#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_DROP_QN_Port_6_reserved_for_padding0_MASK 0xffff0000
-#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_DROP_QN_Port_6_reserved_for_padding0_SHIFT 16
-
-/* SWITCH_CORE :: FC_IMP0_TOTAL_THD_DROP_QN_Port_6 :: SWITCH_RESV [15:11] */
-#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_DROP_QN_Port_6_SWITCH_RESV_MASK 0x0000f800
-#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_DROP_QN_Port_6_SWITCH_RESV_SHIFT 11
-#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_DROP_QN_Port_6_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: FC_IMP0_TOTAL_THD_DROP_QN_Port_6 :: TOTAL_DROP_THD [10:00] */
-#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_DROP_QN_Port_6_TOTAL_DROP_THD_MASK 0x000007ff
-#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_DROP_QN_Port_6_TOTAL_DROP_THD_SHIFT 0
-#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_DROP_QN_Port_6_TOTAL_DROP_THD_DEFAULT 0x000005ef
-
-/***************************************************************************
- *FC_IMP0_TOTAL_THD_DROP_QN_Port_7 - IMP0 Port Queue N Total DROP Threshold RegisterNot2Release
- ***************************************************************************/
-/* SWITCH_CORE :: FC_IMP0_TOTAL_THD_DROP_QN_Port_7 :: reserved_for_padding0 [31:16] */
-#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_DROP_QN_Port_7_reserved_for_padding0_MASK 0xffff0000
-#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_DROP_QN_Port_7_reserved_for_padding0_SHIFT 16
-
-/* SWITCH_CORE :: FC_IMP0_TOTAL_THD_DROP_QN_Port_7 :: SWITCH_RESV [15:11] */
-#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_DROP_QN_Port_7_SWITCH_RESV_MASK 0x0000f800
-#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_DROP_QN_Port_7_SWITCH_RESV_SHIFT 11
-#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_DROP_QN_Port_7_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: FC_IMP0_TOTAL_THD_DROP_QN_Port_7 :: TOTAL_DROP_THD [10:00] */
-#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_DROP_QN_Port_7_TOTAL_DROP_THD_MASK 0x000007ff
-#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_DROP_QN_Port_7_TOTAL_DROP_THD_SHIFT 0
-#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_DROP_QN_Port_7_TOTAL_DROP_THD_DEFAULT 0x000005f7
-
-/***************************************************************************
- *FC_IMP0_REG_SPARE0 - Spare 0 Register (Not2Release)Not2Release
- ***************************************************************************/
-/* SWITCH_CORE :: FC_IMP0_REG_SPARE0 :: reserved_for_padding0 [31:16] */
-#define BCHP_SWITCH_CORE_FC_IMP0_REG_SPARE0_reserved_for_padding0_MASK 0xffff0000
-#define BCHP_SWITCH_CORE_FC_IMP0_REG_SPARE0_reserved_for_padding0_SHIFT 16
-
-/* SWITCH_CORE :: FC_IMP0_REG_SPARE0 :: FC_IMP0_REG_SPARE0 [15:00] */
-#define BCHP_SWITCH_CORE_FC_IMP0_REG_SPARE0_FC_IMP0_REG_SPARE0_MASK 0x0000ffff
-#define BCHP_SWITCH_CORE_FC_IMP0_REG_SPARE0_FC_IMP0_REG_SPARE0_SHIFT 0
-#define BCHP_SWITCH_CORE_FC_IMP0_REG_SPARE0_FC_IMP0_REG_SPARE0_DEFAULT 0x00000000
-
-/***************************************************************************
- *FC_IMP0_REG_SPARE1 - Spare 1 Register (Not2Release)Not2Release
- ***************************************************************************/
-/* SWITCH_CORE :: FC_IMP0_REG_SPARE1 :: reserved_for_padding0 [31:16] */
-#define BCHP_SWITCH_CORE_FC_IMP0_REG_SPARE1_reserved_for_padding0_MASK 0xffff0000
-#define BCHP_SWITCH_CORE_FC_IMP0_REG_SPARE1_reserved_for_padding0_SHIFT 16
-
-/* SWITCH_CORE :: FC_IMP0_REG_SPARE1 :: FC_IMP0_REG_SPARE1 [15:00] */
-#define BCHP_SWITCH_CORE_FC_IMP0_REG_SPARE1_FC_IMP0_REG_SPARE1_MASK 0x0000ffff
-#define BCHP_SWITCH_CORE_FC_IMP0_REG_SPARE1_FC_IMP0_REG_SPARE1_SHIFT 0
-#define BCHP_SWITCH_CORE_FC_IMP0_REG_SPARE1_FC_IMP0_REG_SPARE1_DEFAULT 0x00000000
-
-/***************************************************************************
- *FC_WAN_IMP1_TXQ_THD_RSV_QN_Port_0 - WAN/IMP1 Port Queue N Reserved Threshold RegisterNot2Release
- ***************************************************************************/
-/* SWITCH_CORE :: FC_WAN_IMP1_TXQ_THD_RSV_QN_Port_0 :: reserved_for_padding0 [31:16] */
-#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_RSV_QN_Port_0_reserved_for_padding0_MASK 0xffff0000
-#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_RSV_QN_Port_0_reserved_for_padding0_SHIFT 16
-
-/* SWITCH_CORE :: FC_WAN_IMP1_TXQ_THD_RSV_QN_Port_0 :: SWITCH_RESV [15:11] */
-#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_RSV_QN_Port_0_SWITCH_RESV_MASK 0x0000f800
-#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_RSV_QN_Port_0_SWITCH_RESV_SHIFT 11
-#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_RSV_QN_Port_0_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: FC_WAN_IMP1_TXQ_THD_RSV_QN_Port_0 :: TXQ_RSV_THD [10:00] */
-#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_RSV_QN_Port_0_TXQ_RSV_THD_MASK 0x000007ff
-#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_RSV_QN_Port_0_TXQ_RSV_THD_SHIFT 0
-#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_RSV_QN_Port_0_TXQ_RSV_THD_DEFAULT 0x00000018
-
-/***************************************************************************
- *FC_WAN_IMP1_TXQ_THD_RSV_QN_Port_1 - WAN/IMP1 Port Queue N Reserved Threshold RegisterNot2Release
- ***************************************************************************/
-/* SWITCH_CORE :: FC_WAN_IMP1_TXQ_THD_RSV_QN_Port_1 :: reserved_for_padding0 [31:16] */
-#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_RSV_QN_Port_1_reserved_for_padding0_MASK 0xffff0000
-#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_RSV_QN_Port_1_reserved_for_padding0_SHIFT 16
-
-/* SWITCH_CORE :: FC_WAN_IMP1_TXQ_THD_RSV_QN_Port_1 :: SWITCH_RESV [15:11] */
-#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_RSV_QN_Port_1_SWITCH_RESV_MASK 0x0000f800
-#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_RSV_QN_Port_1_SWITCH_RESV_SHIFT 11
-#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_RSV_QN_Port_1_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: FC_WAN_IMP1_TXQ_THD_RSV_QN_Port_1 :: TXQ_RSV_THD [10:00] */
-#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_RSV_QN_Port_1_TXQ_RSV_THD_MASK 0x000007ff
-#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_RSV_QN_Port_1_TXQ_RSV_THD_SHIFT 0
-#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_RSV_QN_Port_1_TXQ_RSV_THD_DEFAULT 0x00000018
-
-/***************************************************************************
- *FC_WAN_IMP1_TXQ_THD_RSV_QN_Port_2 - WAN/IMP1 Port Queue N Reserved Threshold RegisterNot2Release
- ***************************************************************************/
-/* SWITCH_CORE :: FC_WAN_IMP1_TXQ_THD_RSV_QN_Port_2 :: reserved_for_padding0 [31:16] */
-#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_RSV_QN_Port_2_reserved_for_padding0_MASK 0xffff0000
-#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_RSV_QN_Port_2_reserved_for_padding0_SHIFT 16
-
-/* SWITCH_CORE :: FC_WAN_IMP1_TXQ_THD_RSV_QN_Port_2 :: SWITCH_RESV [15:11] */
-#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_RSV_QN_Port_2_SWITCH_RESV_MASK 0x0000f800
-#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_RSV_QN_Port_2_SWITCH_RESV_SHIFT 11
-#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_RSV_QN_Port_2_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: FC_WAN_IMP1_TXQ_THD_RSV_QN_Port_2 :: TXQ_RSV_THD [10:00] */
-#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_RSV_QN_Port_2_TXQ_RSV_THD_MASK 0x000007ff
-#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_RSV_QN_Port_2_TXQ_RSV_THD_SHIFT 0
-#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_RSV_QN_Port_2_TXQ_RSV_THD_DEFAULT 0x00000018
-
-/***************************************************************************
- *FC_WAN_IMP1_TXQ_THD_RSV_QN_Port_3 - WAN/IMP1 Port Queue N Reserved Threshold RegisterNot2Release
- ***************************************************************************/
-/* SWITCH_CORE :: FC_WAN_IMP1_TXQ_THD_RSV_QN_Port_3 :: reserved_for_padding0 [31:16] */
-#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_RSV_QN_Port_3_reserved_for_padding0_MASK 0xffff0000
-#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_RSV_QN_Port_3_reserved_for_padding0_SHIFT 16
-
-/* SWITCH_CORE :: FC_WAN_IMP1_TXQ_THD_RSV_QN_Port_3 :: SWITCH_RESV [15:11] */
-#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_RSV_QN_Port_3_SWITCH_RESV_MASK 0x0000f800
-#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_RSV_QN_Port_3_SWITCH_RESV_SHIFT 11
-#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_RSV_QN_Port_3_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: FC_WAN_IMP1_TXQ_THD_RSV_QN_Port_3 :: TXQ_RSV_THD [10:00] */
-#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_RSV_QN_Port_3_TXQ_RSV_THD_MASK 0x000007ff
-#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_RSV_QN_Port_3_TXQ_RSV_THD_SHIFT 0
-#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_RSV_QN_Port_3_TXQ_RSV_THD_DEFAULT 0x00000018
-
-/***************************************************************************
- *FC_WAN_IMP1_TXQ_THD_RSV_QN_Port_4 - WAN/IMP1 Port Queue N Reserved Threshold RegisterNot2Release
- ***************************************************************************/
-/* SWITCH_CORE :: FC_WAN_IMP1_TXQ_THD_RSV_QN_Port_4 :: reserved_for_padding0 [31:16] */
-#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_RSV_QN_Port_4_reserved_for_padding0_MASK 0xffff0000
-#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_RSV_QN_Port_4_reserved_for_padding0_SHIFT 16
-
-/* SWITCH_CORE :: FC_WAN_IMP1_TXQ_THD_RSV_QN_Port_4 :: SWITCH_RESV [15:11] */
-#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_RSV_QN_Port_4_SWITCH_RESV_MASK 0x0000f800
-#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_RSV_QN_Port_4_SWITCH_RESV_SHIFT 11
-#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_RSV_QN_Port_4_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: FC_WAN_IMP1_TXQ_THD_RSV_QN_Port_4 :: TXQ_RSV_THD [10:00] */
-#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_RSV_QN_Port_4_TXQ_RSV_THD_MASK 0x000007ff
-#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_RSV_QN_Port_4_TXQ_RSV_THD_SHIFT 0
-#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_RSV_QN_Port_4_TXQ_RSV_THD_DEFAULT 0x00000018
-
-/***************************************************************************
- *FC_WAN_IMP1_TXQ_THD_RSV_QN_Port_5 - WAN/IMP1 Port Queue N Reserved Threshold RegisterNot2Release
- ***************************************************************************/
-/* SWITCH_CORE :: FC_WAN_IMP1_TXQ_THD_RSV_QN_Port_5 :: reserved_for_padding0 [31:16] */
-#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_RSV_QN_Port_5_reserved_for_padding0_MASK 0xffff0000
-#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_RSV_QN_Port_5_reserved_for_padding0_SHIFT 16
-
-/* SWITCH_CORE :: FC_WAN_IMP1_TXQ_THD_RSV_QN_Port_5 :: SWITCH_RESV [15:11] */
-#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_RSV_QN_Port_5_SWITCH_RESV_MASK 0x0000f800
-#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_RSV_QN_Port_5_SWITCH_RESV_SHIFT 11
-#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_RSV_QN_Port_5_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: FC_WAN_IMP1_TXQ_THD_RSV_QN_Port_5 :: TXQ_RSV_THD [10:00] */
-#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_RSV_QN_Port_5_TXQ_RSV_THD_MASK 0x000007ff
-#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_RSV_QN_Port_5_TXQ_RSV_THD_SHIFT 0
-#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_RSV_QN_Port_5_TXQ_RSV_THD_DEFAULT 0x00000018
-
-/***************************************************************************
- *FC_WAN_IMP1_TXQ_THD_RSV_QN_Port_6 - WAN/IMP1 Port Queue N Reserved Threshold RegisterNot2Release
- ***************************************************************************/
-/* SWITCH_CORE :: FC_WAN_IMP1_TXQ_THD_RSV_QN_Port_6 :: reserved_for_padding0 [31:16] */
-#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_RSV_QN_Port_6_reserved_for_padding0_MASK 0xffff0000
-#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_RSV_QN_Port_6_reserved_for_padding0_SHIFT 16
-
-/* SWITCH_CORE :: FC_WAN_IMP1_TXQ_THD_RSV_QN_Port_6 :: SWITCH_RESV [15:11] */
-#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_RSV_QN_Port_6_SWITCH_RESV_MASK 0x0000f800
-#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_RSV_QN_Port_6_SWITCH_RESV_SHIFT 11
-#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_RSV_QN_Port_6_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: FC_WAN_IMP1_TXQ_THD_RSV_QN_Port_6 :: TXQ_RSV_THD [10:00] */
-#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_RSV_QN_Port_6_TXQ_RSV_THD_MASK 0x000007ff
-#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_RSV_QN_Port_6_TXQ_RSV_THD_SHIFT 0
-#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_RSV_QN_Port_6_TXQ_RSV_THD_DEFAULT 0x00000018
-
-/***************************************************************************
- *FC_WAN_IMP1_TXQ_THD_RSV_QN_Port_7 - WAN/IMP1 Port Queue N Reserved Threshold RegisterNot2Release
- ***************************************************************************/
-/* SWITCH_CORE :: FC_WAN_IMP1_TXQ_THD_RSV_QN_Port_7 :: reserved_for_padding0 [31:16] */
-#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_RSV_QN_Port_7_reserved_for_padding0_MASK 0xffff0000
-#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_RSV_QN_Port_7_reserved_for_padding0_SHIFT 16
-
-/* SWITCH_CORE :: FC_WAN_IMP1_TXQ_THD_RSV_QN_Port_7 :: SWITCH_RESV [15:11] */
-#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_RSV_QN_Port_7_SWITCH_RESV_MASK 0x0000f800
-#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_RSV_QN_Port_7_SWITCH_RESV_SHIFT 11
-#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_RSV_QN_Port_7_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: FC_WAN_IMP1_TXQ_THD_RSV_QN_Port_7 :: TXQ_RSV_THD [10:00] */
-#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_RSV_QN_Port_7_TXQ_RSV_THD_MASK 0x000007ff
-#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_RSV_QN_Port_7_TXQ_RSV_THD_SHIFT 0
-#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_RSV_QN_Port_7_TXQ_RSV_THD_DEFAULT 0x00000018
-
-/***************************************************************************
- *FC_WAN_IMP1_TXQ_THD_HYST_QN_Port_0 - WAN/IMP1 Port Queue N Hysteresis Threshold RegisterNot2Release
- ***************************************************************************/
-/* SWITCH_CORE :: FC_WAN_IMP1_TXQ_THD_HYST_QN_Port_0 :: reserved_for_padding0 [31:16] */
-#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_HYST_QN_Port_0_reserved_for_padding0_MASK 0xffff0000
-#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_HYST_QN_Port_0_reserved_for_padding0_SHIFT 16
-
-/* SWITCH_CORE :: FC_WAN_IMP1_TXQ_THD_HYST_QN_Port_0 :: SWITCH_RESV [15:11] */
-#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_HYST_QN_Port_0_SWITCH_RESV_MASK 0x0000f800
-#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_HYST_QN_Port_0_SWITCH_RESV_SHIFT 11
-#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_HYST_QN_Port_0_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: FC_WAN_IMP1_TXQ_THD_HYST_QN_Port_0 :: TXQ_HYST_THD [10:00] */
-#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_HYST_QN_Port_0_TXQ_HYST_THD_MASK 0x000007ff
-#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_HYST_QN_Port_0_TXQ_HYST_THD_SHIFT 0
-#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_HYST_QN_Port_0_TXQ_HYST_THD_DEFAULT 0x00000067
-
-/***************************************************************************
- *FC_WAN_IMP1_TXQ_THD_HYST_QN_Port_1 - WAN/IMP1 Port Queue N Hysteresis Threshold RegisterNot2Release
- ***************************************************************************/
-/* SWITCH_CORE :: FC_WAN_IMP1_TXQ_THD_HYST_QN_Port_1 :: reserved_for_padding0 [31:16] */
-#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_HYST_QN_Port_1_reserved_for_padding0_MASK 0xffff0000
-#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_HYST_QN_Port_1_reserved_for_padding0_SHIFT 16
-
-/* SWITCH_CORE :: FC_WAN_IMP1_TXQ_THD_HYST_QN_Port_1 :: SWITCH_RESV [15:11] */
-#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_HYST_QN_Port_1_SWITCH_RESV_MASK 0x0000f800
-#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_HYST_QN_Port_1_SWITCH_RESV_SHIFT 11
-#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_HYST_QN_Port_1_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: FC_WAN_IMP1_TXQ_THD_HYST_QN_Port_1 :: TXQ_HYST_THD [10:00] */
-#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_HYST_QN_Port_1_TXQ_HYST_THD_MASK 0x000007ff
-#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_HYST_QN_Port_1_TXQ_HYST_THD_SHIFT 0
-#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_HYST_QN_Port_1_TXQ_HYST_THD_DEFAULT 0x0000006b
-
-/***************************************************************************
- *FC_WAN_IMP1_TXQ_THD_HYST_QN_Port_2 - WAN/IMP1 Port Queue N Hysteresis Threshold RegisterNot2Release
- ***************************************************************************/
-/* SWITCH_CORE :: FC_WAN_IMP1_TXQ_THD_HYST_QN_Port_2 :: reserved_for_padding0 [31:16] */
-#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_HYST_QN_Port_2_reserved_for_padding0_MASK 0xffff0000
-#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_HYST_QN_Port_2_reserved_for_padding0_SHIFT 16
-
-/* SWITCH_CORE :: FC_WAN_IMP1_TXQ_THD_HYST_QN_Port_2 :: SWITCH_RESV [15:11] */
-#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_HYST_QN_Port_2_SWITCH_RESV_MASK 0x0000f800
-#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_HYST_QN_Port_2_SWITCH_RESV_SHIFT 11
-#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_HYST_QN_Port_2_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: FC_WAN_IMP1_TXQ_THD_HYST_QN_Port_2 :: TXQ_HYST_THD [10:00] */
-#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_HYST_QN_Port_2_TXQ_HYST_THD_MASK 0x000007ff
-#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_HYST_QN_Port_2_TXQ_HYST_THD_SHIFT 0
-#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_HYST_QN_Port_2_TXQ_HYST_THD_DEFAULT 0x0000006f
-
-/***************************************************************************
- *FC_WAN_IMP1_TXQ_THD_HYST_QN_Port_3 - WAN/IMP1 Port Queue N Hysteresis Threshold RegisterNot2Release
- ***************************************************************************/
-/* SWITCH_CORE :: FC_WAN_IMP1_TXQ_THD_HYST_QN_Port_3 :: reserved_for_padding0 [31:16] */
-#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_HYST_QN_Port_3_reserved_for_padding0_MASK 0xffff0000
-#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_HYST_QN_Port_3_reserved_for_padding0_SHIFT 16
-
-/* SWITCH_CORE :: FC_WAN_IMP1_TXQ_THD_HYST_QN_Port_3 :: SWITCH_RESV [15:11] */
-#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_HYST_QN_Port_3_SWITCH_RESV_MASK 0x0000f800
-#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_HYST_QN_Port_3_SWITCH_RESV_SHIFT 11
-#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_HYST_QN_Port_3_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: FC_WAN_IMP1_TXQ_THD_HYST_QN_Port_3 :: TXQ_HYST_THD [10:00] */
-#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_HYST_QN_Port_3_TXQ_HYST_THD_MASK 0x000007ff
-#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_HYST_QN_Port_3_TXQ_HYST_THD_SHIFT 0
-#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_HYST_QN_Port_3_TXQ_HYST_THD_DEFAULT 0x00000073
-
-/***************************************************************************
- *FC_WAN_IMP1_TXQ_THD_HYST_QN_Port_4 - WAN/IMP1 Port Queue N Hysteresis Threshold RegisterNot2Release
- ***************************************************************************/
-/* SWITCH_CORE :: FC_WAN_IMP1_TXQ_THD_HYST_QN_Port_4 :: reserved_for_padding0 [31:16] */
-#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_HYST_QN_Port_4_reserved_for_padding0_MASK 0xffff0000
-#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_HYST_QN_Port_4_reserved_for_padding0_SHIFT 16
-
-/* SWITCH_CORE :: FC_WAN_IMP1_TXQ_THD_HYST_QN_Port_4 :: SWITCH_RESV [15:11] */
-#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_HYST_QN_Port_4_SWITCH_RESV_MASK 0x0000f800
-#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_HYST_QN_Port_4_SWITCH_RESV_SHIFT 11
-#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_HYST_QN_Port_4_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: FC_WAN_IMP1_TXQ_THD_HYST_QN_Port_4 :: TXQ_HYST_THD [10:00] */
-#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_HYST_QN_Port_4_TXQ_HYST_THD_MASK 0x000007ff
-#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_HYST_QN_Port_4_TXQ_HYST_THD_SHIFT 0
-#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_HYST_QN_Port_4_TXQ_HYST_THD_DEFAULT 0x00000077
-
-/***************************************************************************
- *FC_WAN_IMP1_TXQ_THD_HYST_QN_Port_5 - WAN/IMP1 Port Queue N Hysteresis Threshold RegisterNot2Release
- ***************************************************************************/
-/* SWITCH_CORE :: FC_WAN_IMP1_TXQ_THD_HYST_QN_Port_5 :: reserved_for_padding0 [31:16] */
-#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_HYST_QN_Port_5_reserved_for_padding0_MASK 0xffff0000
-#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_HYST_QN_Port_5_reserved_for_padding0_SHIFT 16
-
-/* SWITCH_CORE :: FC_WAN_IMP1_TXQ_THD_HYST_QN_Port_5 :: SWITCH_RESV [15:11] */
-#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_HYST_QN_Port_5_SWITCH_RESV_MASK 0x0000f800
-#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_HYST_QN_Port_5_SWITCH_RESV_SHIFT 11
-#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_HYST_QN_Port_5_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: FC_WAN_IMP1_TXQ_THD_HYST_QN_Port_5 :: TXQ_HYST_THD [10:00] */
-#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_HYST_QN_Port_5_TXQ_HYST_THD_MASK 0x000007ff
-#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_HYST_QN_Port_5_TXQ_HYST_THD_SHIFT 0
-#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_HYST_QN_Port_5_TXQ_HYST_THD_DEFAULT 0x0000007b
-
-/***************************************************************************
- *FC_WAN_IMP1_TXQ_THD_HYST_QN_Port_6 - WAN/IMP1 Port Queue N Hysteresis Threshold RegisterNot2Release
- ***************************************************************************/
-/* SWITCH_CORE :: FC_WAN_IMP1_TXQ_THD_HYST_QN_Port_6 :: reserved_for_padding0 [31:16] */
-#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_HYST_QN_Port_6_reserved_for_padding0_MASK 0xffff0000
-#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_HYST_QN_Port_6_reserved_for_padding0_SHIFT 16
-
-/* SWITCH_CORE :: FC_WAN_IMP1_TXQ_THD_HYST_QN_Port_6 :: SWITCH_RESV [15:11] */
-#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_HYST_QN_Port_6_SWITCH_RESV_MASK 0x0000f800
-#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_HYST_QN_Port_6_SWITCH_RESV_SHIFT 11
-#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_HYST_QN_Port_6_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: FC_WAN_IMP1_TXQ_THD_HYST_QN_Port_6 :: TXQ_HYST_THD [10:00] */
-#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_HYST_QN_Port_6_TXQ_HYST_THD_MASK 0x000007ff
-#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_HYST_QN_Port_6_TXQ_HYST_THD_SHIFT 0
-#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_HYST_QN_Port_6_TXQ_HYST_THD_DEFAULT 0x0000007f
-
-/***************************************************************************
- *FC_WAN_IMP1_TXQ_THD_HYST_QN_Port_7 - WAN/IMP1 Port Queue N Hysteresis Threshold RegisterNot2Release
- ***************************************************************************/
-/* SWITCH_CORE :: FC_WAN_IMP1_TXQ_THD_HYST_QN_Port_7 :: reserved_for_padding0 [31:16] */
-#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_HYST_QN_Port_7_reserved_for_padding0_MASK 0xffff0000
-#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_HYST_QN_Port_7_reserved_for_padding0_SHIFT 16
-
-/* SWITCH_CORE :: FC_WAN_IMP1_TXQ_THD_HYST_QN_Port_7 :: SWITCH_RESV [15:11] */
-#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_HYST_QN_Port_7_SWITCH_RESV_MASK 0x0000f800
-#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_HYST_QN_Port_7_SWITCH_RESV_SHIFT 11
-#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_HYST_QN_Port_7_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: FC_WAN_IMP1_TXQ_THD_HYST_QN_Port_7 :: TXQ_HYST_THD [10:00] */
-#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_HYST_QN_Port_7_TXQ_HYST_THD_MASK 0x000007ff
-#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_HYST_QN_Port_7_TXQ_HYST_THD_SHIFT 0
-#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_HYST_QN_Port_7_TXQ_HYST_THD_DEFAULT 0x00000083
-
-/***************************************************************************
- *FC_WAN_IMP1_TXQ_THD_PAUSE_QN_Port_0 - WAN/IMP1 Port Queue N Pause Threshold RegisterNot2Release
- ***************************************************************************/
-/* SWITCH_CORE :: FC_WAN_IMP1_TXQ_THD_PAUSE_QN_Port_0 :: reserved_for_padding0 [31:16] */
-#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_PAUSE_QN_Port_0_reserved_for_padding0_MASK 0xffff0000
-#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_PAUSE_QN_Port_0_reserved_for_padding0_SHIFT 16
-
-/* SWITCH_CORE :: FC_WAN_IMP1_TXQ_THD_PAUSE_QN_Port_0 :: SWITCH_RESV [15:11] */
-#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_PAUSE_QN_Port_0_SWITCH_RESV_MASK 0x0000f800
-#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_PAUSE_QN_Port_0_SWITCH_RESV_SHIFT 11
-#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_PAUSE_QN_Port_0_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: FC_WAN_IMP1_TXQ_THD_PAUSE_QN_Port_0 :: TXQ_PAUSE_THD [10:00] */
-#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_PAUSE_QN_Port_0_TXQ_PAUSE_THD_MASK 0x000007ff
-#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_PAUSE_QN_Port_0_TXQ_PAUSE_THD_SHIFT 0
-#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_PAUSE_QN_Port_0_TXQ_PAUSE_THD_DEFAULT 0x000000cf
-
-/***************************************************************************
- *FC_WAN_IMP1_TXQ_THD_PAUSE_QN_Port_1 - WAN/IMP1 Port Queue N Pause Threshold RegisterNot2Release
- ***************************************************************************/
-/* SWITCH_CORE :: FC_WAN_IMP1_TXQ_THD_PAUSE_QN_Port_1 :: reserved_for_padding0 [31:16] */
-#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_PAUSE_QN_Port_1_reserved_for_padding0_MASK 0xffff0000
-#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_PAUSE_QN_Port_1_reserved_for_padding0_SHIFT 16
-
-/* SWITCH_CORE :: FC_WAN_IMP1_TXQ_THD_PAUSE_QN_Port_1 :: SWITCH_RESV [15:11] */
-#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_PAUSE_QN_Port_1_SWITCH_RESV_MASK 0x0000f800
-#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_PAUSE_QN_Port_1_SWITCH_RESV_SHIFT 11
-#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_PAUSE_QN_Port_1_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: FC_WAN_IMP1_TXQ_THD_PAUSE_QN_Port_1 :: TXQ_PAUSE_THD [10:00] */
-#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_PAUSE_QN_Port_1_TXQ_PAUSE_THD_MASK 0x000007ff
-#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_PAUSE_QN_Port_1_TXQ_PAUSE_THD_SHIFT 0
-#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_PAUSE_QN_Port_1_TXQ_PAUSE_THD_DEFAULT 0x000000d7
-
-/***************************************************************************
- *FC_WAN_IMP1_TXQ_THD_PAUSE_QN_Port_2 - WAN/IMP1 Port Queue N Pause Threshold RegisterNot2Release
- ***************************************************************************/
-/* SWITCH_CORE :: FC_WAN_IMP1_TXQ_THD_PAUSE_QN_Port_2 :: reserved_for_padding0 [31:16] */
-#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_PAUSE_QN_Port_2_reserved_for_padding0_MASK 0xffff0000
-#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_PAUSE_QN_Port_2_reserved_for_padding0_SHIFT 16
-
-/* SWITCH_CORE :: FC_WAN_IMP1_TXQ_THD_PAUSE_QN_Port_2 :: SWITCH_RESV [15:11] */
-#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_PAUSE_QN_Port_2_SWITCH_RESV_MASK 0x0000f800
-#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_PAUSE_QN_Port_2_SWITCH_RESV_SHIFT 11
-#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_PAUSE_QN_Port_2_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: FC_WAN_IMP1_TXQ_THD_PAUSE_QN_Port_2 :: TXQ_PAUSE_THD [10:00] */
-#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_PAUSE_QN_Port_2_TXQ_PAUSE_THD_MASK 0x000007ff
-#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_PAUSE_QN_Port_2_TXQ_PAUSE_THD_SHIFT 0
-#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_PAUSE_QN_Port_2_TXQ_PAUSE_THD_DEFAULT 0x000000df
-
-/***************************************************************************
- *FC_WAN_IMP1_TXQ_THD_PAUSE_QN_Port_3 - WAN/IMP1 Port Queue N Pause Threshold RegisterNot2Release
- ***************************************************************************/
-/* SWITCH_CORE :: FC_WAN_IMP1_TXQ_THD_PAUSE_QN_Port_3 :: reserved_for_padding0 [31:16] */
-#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_PAUSE_QN_Port_3_reserved_for_padding0_MASK 0xffff0000
-#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_PAUSE_QN_Port_3_reserved_for_padding0_SHIFT 16
-
-/* SWITCH_CORE :: FC_WAN_IMP1_TXQ_THD_PAUSE_QN_Port_3 :: SWITCH_RESV [15:11] */
-#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_PAUSE_QN_Port_3_SWITCH_RESV_MASK 0x0000f800
-#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_PAUSE_QN_Port_3_SWITCH_RESV_SHIFT 11
-#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_PAUSE_QN_Port_3_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: FC_WAN_IMP1_TXQ_THD_PAUSE_QN_Port_3 :: TXQ_PAUSE_THD [10:00] */
-#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_PAUSE_QN_Port_3_TXQ_PAUSE_THD_MASK 0x000007ff
-#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_PAUSE_QN_Port_3_TXQ_PAUSE_THD_SHIFT 0
-#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_PAUSE_QN_Port_3_TXQ_PAUSE_THD_DEFAULT 0x000000e7
-
-/***************************************************************************
- *FC_WAN_IMP1_TXQ_THD_PAUSE_QN_Port_4 - WAN/IMP1 Port Queue N Pause Threshold RegisterNot2Release
- ***************************************************************************/
-/* SWITCH_CORE :: FC_WAN_IMP1_TXQ_THD_PAUSE_QN_Port_4 :: reserved_for_padding0 [31:16] */
-#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_PAUSE_QN_Port_4_reserved_for_padding0_MASK 0xffff0000
-#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_PAUSE_QN_Port_4_reserved_for_padding0_SHIFT 16
-
-/* SWITCH_CORE :: FC_WAN_IMP1_TXQ_THD_PAUSE_QN_Port_4 :: SWITCH_RESV [15:11] */
-#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_PAUSE_QN_Port_4_SWITCH_RESV_MASK 0x0000f800
-#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_PAUSE_QN_Port_4_SWITCH_RESV_SHIFT 11
-#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_PAUSE_QN_Port_4_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: FC_WAN_IMP1_TXQ_THD_PAUSE_QN_Port_4 :: TXQ_PAUSE_THD [10:00] */
-#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_PAUSE_QN_Port_4_TXQ_PAUSE_THD_MASK 0x000007ff
-#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_PAUSE_QN_Port_4_TXQ_PAUSE_THD_SHIFT 0
-#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_PAUSE_QN_Port_4_TXQ_PAUSE_THD_DEFAULT 0x000000ef
-
-/***************************************************************************
- *FC_WAN_IMP1_TXQ_THD_PAUSE_QN_Port_5 - WAN/IMP1 Port Queue N Pause Threshold RegisterNot2Release
- ***************************************************************************/
-/* SWITCH_CORE :: FC_WAN_IMP1_TXQ_THD_PAUSE_QN_Port_5 :: reserved_for_padding0 [31:16] */
-#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_PAUSE_QN_Port_5_reserved_for_padding0_MASK 0xffff0000
-#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_PAUSE_QN_Port_5_reserved_for_padding0_SHIFT 16
-
-/* SWITCH_CORE :: FC_WAN_IMP1_TXQ_THD_PAUSE_QN_Port_5 :: SWITCH_RESV [15:11] */
-#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_PAUSE_QN_Port_5_SWITCH_RESV_MASK 0x0000f800
-#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_PAUSE_QN_Port_5_SWITCH_RESV_SHIFT 11
-#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_PAUSE_QN_Port_5_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: FC_WAN_IMP1_TXQ_THD_PAUSE_QN_Port_5 :: TXQ_PAUSE_THD [10:00] */
-#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_PAUSE_QN_Port_5_TXQ_PAUSE_THD_MASK 0x000007ff
-#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_PAUSE_QN_Port_5_TXQ_PAUSE_THD_SHIFT 0
-#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_PAUSE_QN_Port_5_TXQ_PAUSE_THD_DEFAULT 0x000000f7
-
-/***************************************************************************
- *FC_WAN_IMP1_TXQ_THD_PAUSE_QN_Port_6 - WAN/IMP1 Port Queue N Pause Threshold RegisterNot2Release
- ***************************************************************************/
-/* SWITCH_CORE :: FC_WAN_IMP1_TXQ_THD_PAUSE_QN_Port_6 :: reserved_for_padding0 [31:16] */
-#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_PAUSE_QN_Port_6_reserved_for_padding0_MASK 0xffff0000
-#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_PAUSE_QN_Port_6_reserved_for_padding0_SHIFT 16
-
-/* SWITCH_CORE :: FC_WAN_IMP1_TXQ_THD_PAUSE_QN_Port_6 :: SWITCH_RESV [15:11] */
-#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_PAUSE_QN_Port_6_SWITCH_RESV_MASK 0x0000f800
-#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_PAUSE_QN_Port_6_SWITCH_RESV_SHIFT 11
-#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_PAUSE_QN_Port_6_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: FC_WAN_IMP1_TXQ_THD_PAUSE_QN_Port_6 :: TXQ_PAUSE_THD [10:00] */
-#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_PAUSE_QN_Port_6_TXQ_PAUSE_THD_MASK 0x000007ff
-#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_PAUSE_QN_Port_6_TXQ_PAUSE_THD_SHIFT 0
-#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_PAUSE_QN_Port_6_TXQ_PAUSE_THD_DEFAULT 0x000000ff
-
-/***************************************************************************
- *FC_WAN_IMP1_TXQ_THD_PAUSE_QN_Port_7 - WAN/IMP1 Port Queue N Pause Threshold RegisterNot2Release
- ***************************************************************************/
-/* SWITCH_CORE :: FC_WAN_IMP1_TXQ_THD_PAUSE_QN_Port_7 :: reserved_for_padding0 [31:16] */
-#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_PAUSE_QN_Port_7_reserved_for_padding0_MASK 0xffff0000
-#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_PAUSE_QN_Port_7_reserved_for_padding0_SHIFT 16
-
-/* SWITCH_CORE :: FC_WAN_IMP1_TXQ_THD_PAUSE_QN_Port_7 :: SWITCH_RESV [15:11] */
-#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_PAUSE_QN_Port_7_SWITCH_RESV_MASK 0x0000f800
-#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_PAUSE_QN_Port_7_SWITCH_RESV_SHIFT 11
-#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_PAUSE_QN_Port_7_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: FC_WAN_IMP1_TXQ_THD_PAUSE_QN_Port_7 :: TXQ_PAUSE_THD [10:00] */
-#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_PAUSE_QN_Port_7_TXQ_PAUSE_THD_MASK 0x000007ff
-#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_PAUSE_QN_Port_7_TXQ_PAUSE_THD_SHIFT 0
-#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_PAUSE_QN_Port_7_TXQ_PAUSE_THD_DEFAULT 0x00000107
-
-/***************************************************************************
- *FC_WAN_IMP1_TXQ_THD_DROP_QN_Port_0 - WAN/IMP1 Port Queue N DROP Threshold RegisterNot2Release
- ***************************************************************************/
-/* SWITCH_CORE :: FC_WAN_IMP1_TXQ_THD_DROP_QN_Port_0 :: reserved_for_padding0 [31:16] */
-#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_DROP_QN_Port_0_reserved_for_padding0_MASK 0xffff0000
-#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_DROP_QN_Port_0_reserved_for_padding0_SHIFT 16
-
-/* SWITCH_CORE :: FC_WAN_IMP1_TXQ_THD_DROP_QN_Port_0 :: SWITCH_RESV [15:11] */
-#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_DROP_QN_Port_0_SWITCH_RESV_MASK 0x0000f800
-#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_DROP_QN_Port_0_SWITCH_RESV_SHIFT 11
-#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_DROP_QN_Port_0_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: FC_WAN_IMP1_TXQ_THD_DROP_QN_Port_0 :: TXQ_DROP_THD [10:00] */
-#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_DROP_QN_Port_0_TXQ_DROP_THD_MASK 0x000007ff
-#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_DROP_QN_Port_0_TXQ_DROP_THD_SHIFT 0
-#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_DROP_QN_Port_0_TXQ_DROP_THD_DEFAULT 0x000005ff
-
-/***************************************************************************
- *FC_WAN_IMP1_TXQ_THD_DROP_QN_Port_1 - WAN/IMP1 Port Queue N DROP Threshold RegisterNot2Release
- ***************************************************************************/
-/* SWITCH_CORE :: FC_WAN_IMP1_TXQ_THD_DROP_QN_Port_1 :: reserved_for_padding0 [31:16] */
-#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_DROP_QN_Port_1_reserved_for_padding0_MASK 0xffff0000
-#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_DROP_QN_Port_1_reserved_for_padding0_SHIFT 16
-
-/* SWITCH_CORE :: FC_WAN_IMP1_TXQ_THD_DROP_QN_Port_1 :: SWITCH_RESV [15:11] */
-#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_DROP_QN_Port_1_SWITCH_RESV_MASK 0x0000f800
-#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_DROP_QN_Port_1_SWITCH_RESV_SHIFT 11
-#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_DROP_QN_Port_1_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: FC_WAN_IMP1_TXQ_THD_DROP_QN_Port_1 :: TXQ_DROP_THD [10:00] */
-#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_DROP_QN_Port_1_TXQ_DROP_THD_MASK 0x000007ff
-#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_DROP_QN_Port_1_TXQ_DROP_THD_SHIFT 0
-#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_DROP_QN_Port_1_TXQ_DROP_THD_DEFAULT 0x000005ff
-
-/***************************************************************************
- *FC_WAN_IMP1_TXQ_THD_DROP_QN_Port_2 - WAN/IMP1 Port Queue N DROP Threshold RegisterNot2Release
- ***************************************************************************/
-/* SWITCH_CORE :: FC_WAN_IMP1_TXQ_THD_DROP_QN_Port_2 :: reserved_for_padding0 [31:16] */
-#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_DROP_QN_Port_2_reserved_for_padding0_MASK 0xffff0000
-#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_DROP_QN_Port_2_reserved_for_padding0_SHIFT 16
-
-/* SWITCH_CORE :: FC_WAN_IMP1_TXQ_THD_DROP_QN_Port_2 :: SWITCH_RESV [15:11] */
-#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_DROP_QN_Port_2_SWITCH_RESV_MASK 0x0000f800
-#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_DROP_QN_Port_2_SWITCH_RESV_SHIFT 11
-#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_DROP_QN_Port_2_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: FC_WAN_IMP1_TXQ_THD_DROP_QN_Port_2 :: TXQ_DROP_THD [10:00] */
-#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_DROP_QN_Port_2_TXQ_DROP_THD_MASK 0x000007ff
-#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_DROP_QN_Port_2_TXQ_DROP_THD_SHIFT 0
-#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_DROP_QN_Port_2_TXQ_DROP_THD_DEFAULT 0x000005ff
-
-/***************************************************************************
- *FC_WAN_IMP1_TXQ_THD_DROP_QN_Port_3 - WAN/IMP1 Port Queue N DROP Threshold RegisterNot2Release
- ***************************************************************************/
-/* SWITCH_CORE :: FC_WAN_IMP1_TXQ_THD_DROP_QN_Port_3 :: reserved_for_padding0 [31:16] */
-#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_DROP_QN_Port_3_reserved_for_padding0_MASK 0xffff0000
-#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_DROP_QN_Port_3_reserved_for_padding0_SHIFT 16
-
-/* SWITCH_CORE :: FC_WAN_IMP1_TXQ_THD_DROP_QN_Port_3 :: SWITCH_RESV [15:11] */
-#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_DROP_QN_Port_3_SWITCH_RESV_MASK 0x0000f800
-#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_DROP_QN_Port_3_SWITCH_RESV_SHIFT 11
-#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_DROP_QN_Port_3_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: FC_WAN_IMP1_TXQ_THD_DROP_QN_Port_3 :: TXQ_DROP_THD [10:00] */
-#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_DROP_QN_Port_3_TXQ_DROP_THD_MASK 0x000007ff
-#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_DROP_QN_Port_3_TXQ_DROP_THD_SHIFT 0
-#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_DROP_QN_Port_3_TXQ_DROP_THD_DEFAULT 0x000005ff
-
-/***************************************************************************
- *FC_WAN_IMP1_TXQ_THD_DROP_QN_Port_4 - WAN/IMP1 Port Queue N DROP Threshold RegisterNot2Release
- ***************************************************************************/
-/* SWITCH_CORE :: FC_WAN_IMP1_TXQ_THD_DROP_QN_Port_4 :: reserved_for_padding0 [31:16] */
-#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_DROP_QN_Port_4_reserved_for_padding0_MASK 0xffff0000
-#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_DROP_QN_Port_4_reserved_for_padding0_SHIFT 16
-
-/* SWITCH_CORE :: FC_WAN_IMP1_TXQ_THD_DROP_QN_Port_4 :: SWITCH_RESV [15:11] */
-#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_DROP_QN_Port_4_SWITCH_RESV_MASK 0x0000f800
-#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_DROP_QN_Port_4_SWITCH_RESV_SHIFT 11
-#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_DROP_QN_Port_4_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: FC_WAN_IMP1_TXQ_THD_DROP_QN_Port_4 :: TXQ_DROP_THD [10:00] */
-#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_DROP_QN_Port_4_TXQ_DROP_THD_MASK 0x000007ff
-#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_DROP_QN_Port_4_TXQ_DROP_THD_SHIFT 0
-#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_DROP_QN_Port_4_TXQ_DROP_THD_DEFAULT 0x000005ff
-
-/***************************************************************************
- *FC_WAN_IMP1_TXQ_THD_DROP_QN_Port_5 - WAN/IMP1 Port Queue N DROP Threshold RegisterNot2Release
- ***************************************************************************/
-/* SWITCH_CORE :: FC_WAN_IMP1_TXQ_THD_DROP_QN_Port_5 :: reserved_for_padding0 [31:16] */
-#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_DROP_QN_Port_5_reserved_for_padding0_MASK 0xffff0000
-#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_DROP_QN_Port_5_reserved_for_padding0_SHIFT 16
-
-/* SWITCH_CORE :: FC_WAN_IMP1_TXQ_THD_DROP_QN_Port_5 :: SWITCH_RESV [15:11] */
-#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_DROP_QN_Port_5_SWITCH_RESV_MASK 0x0000f800
-#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_DROP_QN_Port_5_SWITCH_RESV_SHIFT 11
-#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_DROP_QN_Port_5_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: FC_WAN_IMP1_TXQ_THD_DROP_QN_Port_5 :: TXQ_DROP_THD [10:00] */
-#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_DROP_QN_Port_5_TXQ_DROP_THD_MASK 0x000007ff
-#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_DROP_QN_Port_5_TXQ_DROP_THD_SHIFT 0
-#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_DROP_QN_Port_5_TXQ_DROP_THD_DEFAULT 0x000005ff
-
-/***************************************************************************
- *FC_WAN_IMP1_TXQ_THD_DROP_QN_Port_6 - WAN/IMP1 Port Queue N DROP Threshold RegisterNot2Release
- ***************************************************************************/
-/* SWITCH_CORE :: FC_WAN_IMP1_TXQ_THD_DROP_QN_Port_6 :: reserved_for_padding0 [31:16] */
-#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_DROP_QN_Port_6_reserved_for_padding0_MASK 0xffff0000
-#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_DROP_QN_Port_6_reserved_for_padding0_SHIFT 16
-
-/* SWITCH_CORE :: FC_WAN_IMP1_TXQ_THD_DROP_QN_Port_6 :: SWITCH_RESV [15:11] */
-#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_DROP_QN_Port_6_SWITCH_RESV_MASK 0x0000f800
-#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_DROP_QN_Port_6_SWITCH_RESV_SHIFT 11
-#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_DROP_QN_Port_6_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: FC_WAN_IMP1_TXQ_THD_DROP_QN_Port_6 :: TXQ_DROP_THD [10:00] */
-#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_DROP_QN_Port_6_TXQ_DROP_THD_MASK 0x000007ff
-#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_DROP_QN_Port_6_TXQ_DROP_THD_SHIFT 0
-#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_DROP_QN_Port_6_TXQ_DROP_THD_DEFAULT 0x000005ff
-
-/***************************************************************************
- *FC_WAN_IMP1_TXQ_THD_DROP_QN_Port_7 - WAN/IMP1 Port Queue N DROP Threshold RegisterNot2Release
- ***************************************************************************/
-/* SWITCH_CORE :: FC_WAN_IMP1_TXQ_THD_DROP_QN_Port_7 :: reserved_for_padding0 [31:16] */
-#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_DROP_QN_Port_7_reserved_for_padding0_MASK 0xffff0000
-#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_DROP_QN_Port_7_reserved_for_padding0_SHIFT 16
-
-/* SWITCH_CORE :: FC_WAN_IMP1_TXQ_THD_DROP_QN_Port_7 :: SWITCH_RESV [15:11] */
-#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_DROP_QN_Port_7_SWITCH_RESV_MASK 0x0000f800
-#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_DROP_QN_Port_7_SWITCH_RESV_SHIFT 11
-#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_DROP_QN_Port_7_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: FC_WAN_IMP1_TXQ_THD_DROP_QN_Port_7 :: TXQ_DROP_THD [10:00] */
-#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_DROP_QN_Port_7_TXQ_DROP_THD_MASK 0x000007ff
-#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_DROP_QN_Port_7_TXQ_DROP_THD_SHIFT 0
-#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_DROP_QN_Port_7_TXQ_DROP_THD_DEFAULT 0x000005ff
-
-/***************************************************************************
- *FC_WAN_IMP1_TOTAL_THD_HYST_QN_Port_0 - WAN/IMP1 Port Queue N Total Hysteresis Threshold RegisterNot2Release
- ***************************************************************************/
-/* SWITCH_CORE :: FC_WAN_IMP1_TOTAL_THD_HYST_QN_Port_0 :: reserved_for_padding0 [31:16] */
-#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_HYST_QN_Port_0_reserved_for_padding0_MASK 0xffff0000
-#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_HYST_QN_Port_0_reserved_for_padding0_SHIFT 16
-
-/* SWITCH_CORE :: FC_WAN_IMP1_TOTAL_THD_HYST_QN_Port_0 :: SWITCH_RESV [15:11] */
-#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_HYST_QN_Port_0_SWITCH_RESV_MASK 0x0000f800
-#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_HYST_QN_Port_0_SWITCH_RESV_SHIFT 11
-#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_HYST_QN_Port_0_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: FC_WAN_IMP1_TOTAL_THD_HYST_QN_Port_0 :: TOTAL_HYST_THD [10:00] */
-#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_HYST_QN_Port_0_TOTAL_HYST_THD_MASK 0x000007ff
-#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_HYST_QN_Port_0_TOTAL_HYST_THD_SHIFT 0
-#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_HYST_QN_Port_0_TOTAL_HYST_THD_DEFAULT 0x000003c7
-
-/***************************************************************************
- *FC_WAN_IMP1_TOTAL_THD_HYST_QN_Port_1 - WAN/IMP1 Port Queue N Total Hysteresis Threshold RegisterNot2Release
- ***************************************************************************/
-/* SWITCH_CORE :: FC_WAN_IMP1_TOTAL_THD_HYST_QN_Port_1 :: reserved_for_padding0 [31:16] */
-#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_HYST_QN_Port_1_reserved_for_padding0_MASK 0xffff0000
-#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_HYST_QN_Port_1_reserved_for_padding0_SHIFT 16
-
-/* SWITCH_CORE :: FC_WAN_IMP1_TOTAL_THD_HYST_QN_Port_1 :: SWITCH_RESV [15:11] */
-#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_HYST_QN_Port_1_SWITCH_RESV_MASK 0x0000f800
-#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_HYST_QN_Port_1_SWITCH_RESV_SHIFT 11
-#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_HYST_QN_Port_1_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: FC_WAN_IMP1_TOTAL_THD_HYST_QN_Port_1 :: TOTAL_HYST_THD [10:00] */
-#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_HYST_QN_Port_1_TOTAL_HYST_THD_MASK 0x000007ff
-#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_HYST_QN_Port_1_TOTAL_HYST_THD_SHIFT 0
-#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_HYST_QN_Port_1_TOTAL_HYST_THD_DEFAULT 0x000003c7
-
-/***************************************************************************
- *FC_WAN_IMP1_TOTAL_THD_HYST_QN_Port_2 - WAN/IMP1 Port Queue N Total Hysteresis Threshold RegisterNot2Release
- ***************************************************************************/
-/* SWITCH_CORE :: FC_WAN_IMP1_TOTAL_THD_HYST_QN_Port_2 :: reserved_for_padding0 [31:16] */
-#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_HYST_QN_Port_2_reserved_for_padding0_MASK 0xffff0000
-#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_HYST_QN_Port_2_reserved_for_padding0_SHIFT 16
-
-/* SWITCH_CORE :: FC_WAN_IMP1_TOTAL_THD_HYST_QN_Port_2 :: SWITCH_RESV [15:11] */
-#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_HYST_QN_Port_2_SWITCH_RESV_MASK 0x0000f800
-#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_HYST_QN_Port_2_SWITCH_RESV_SHIFT 11
-#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_HYST_QN_Port_2_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: FC_WAN_IMP1_TOTAL_THD_HYST_QN_Port_2 :: TOTAL_HYST_THD [10:00] */
-#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_HYST_QN_Port_2_TOTAL_HYST_THD_MASK 0x000007ff
-#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_HYST_QN_Port_2_TOTAL_HYST_THD_SHIFT 0
-#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_HYST_QN_Port_2_TOTAL_HYST_THD_DEFAULT 0x000003c7
-
-/***************************************************************************
- *FC_WAN_IMP1_TOTAL_THD_HYST_QN_Port_3 - WAN/IMP1 Port Queue N Total Hysteresis Threshold RegisterNot2Release
- ***************************************************************************/
-/* SWITCH_CORE :: FC_WAN_IMP1_TOTAL_THD_HYST_QN_Port_3 :: reserved_for_padding0 [31:16] */
-#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_HYST_QN_Port_3_reserved_for_padding0_MASK 0xffff0000
-#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_HYST_QN_Port_3_reserved_for_padding0_SHIFT 16
-
-/* SWITCH_CORE :: FC_WAN_IMP1_TOTAL_THD_HYST_QN_Port_3 :: SWITCH_RESV [15:11] */
-#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_HYST_QN_Port_3_SWITCH_RESV_MASK 0x0000f800
-#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_HYST_QN_Port_3_SWITCH_RESV_SHIFT 11
-#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_HYST_QN_Port_3_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: FC_WAN_IMP1_TOTAL_THD_HYST_QN_Port_3 :: TOTAL_HYST_THD [10:00] */
-#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_HYST_QN_Port_3_TOTAL_HYST_THD_MASK 0x000007ff
-#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_HYST_QN_Port_3_TOTAL_HYST_THD_SHIFT 0
-#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_HYST_QN_Port_3_TOTAL_HYST_THD_DEFAULT 0x000003c7
-
-/***************************************************************************
- *FC_WAN_IMP1_TOTAL_THD_HYST_QN_Port_4 - WAN/IMP1 Port Queue N Total Hysteresis Threshold RegisterNot2Release
- ***************************************************************************/
-/* SWITCH_CORE :: FC_WAN_IMP1_TOTAL_THD_HYST_QN_Port_4 :: reserved_for_padding0 [31:16] */
-#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_HYST_QN_Port_4_reserved_for_padding0_MASK 0xffff0000
-#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_HYST_QN_Port_4_reserved_for_padding0_SHIFT 16
-
-/* SWITCH_CORE :: FC_WAN_IMP1_TOTAL_THD_HYST_QN_Port_4 :: SWITCH_RESV [15:11] */
-#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_HYST_QN_Port_4_SWITCH_RESV_MASK 0x0000f800
-#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_HYST_QN_Port_4_SWITCH_RESV_SHIFT 11
-#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_HYST_QN_Port_4_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: FC_WAN_IMP1_TOTAL_THD_HYST_QN_Port_4 :: TOTAL_HYST_THD [10:00] */
-#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_HYST_QN_Port_4_TOTAL_HYST_THD_MASK 0x000007ff
-#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_HYST_QN_Port_4_TOTAL_HYST_THD_SHIFT 0
-#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_HYST_QN_Port_4_TOTAL_HYST_THD_DEFAULT 0x000003c7
-
-/***************************************************************************
- *FC_WAN_IMP1_TOTAL_THD_HYST_QN_Port_5 - WAN/IMP1 Port Queue N Total Hysteresis Threshold RegisterNot2Release
- ***************************************************************************/
-/* SWITCH_CORE :: FC_WAN_IMP1_TOTAL_THD_HYST_QN_Port_5 :: reserved_for_padding0 [31:16] */
-#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_HYST_QN_Port_5_reserved_for_padding0_MASK 0xffff0000
-#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_HYST_QN_Port_5_reserved_for_padding0_SHIFT 16
-
-/* SWITCH_CORE :: FC_WAN_IMP1_TOTAL_THD_HYST_QN_Port_5 :: SWITCH_RESV [15:11] */
-#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_HYST_QN_Port_5_SWITCH_RESV_MASK 0x0000f800
-#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_HYST_QN_Port_5_SWITCH_RESV_SHIFT 11
-#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_HYST_QN_Port_5_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: FC_WAN_IMP1_TOTAL_THD_HYST_QN_Port_5 :: TOTAL_HYST_THD [10:00] */
-#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_HYST_QN_Port_5_TOTAL_HYST_THD_MASK 0x000007ff
-#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_HYST_QN_Port_5_TOTAL_HYST_THD_SHIFT 0
-#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_HYST_QN_Port_5_TOTAL_HYST_THD_DEFAULT 0x000003c7
-
-/***************************************************************************
- *FC_WAN_IMP1_TOTAL_THD_HYST_QN_Port_6 - WAN/IMP1 Port Queue N Total Hysteresis Threshold RegisterNot2Release
- ***************************************************************************/
-/* SWITCH_CORE :: FC_WAN_IMP1_TOTAL_THD_HYST_QN_Port_6 :: reserved_for_padding0 [31:16] */
-#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_HYST_QN_Port_6_reserved_for_padding0_MASK 0xffff0000
-#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_HYST_QN_Port_6_reserved_for_padding0_SHIFT 16
-
-/* SWITCH_CORE :: FC_WAN_IMP1_TOTAL_THD_HYST_QN_Port_6 :: SWITCH_RESV [15:11] */
-#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_HYST_QN_Port_6_SWITCH_RESV_MASK 0x0000f800
-#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_HYST_QN_Port_6_SWITCH_RESV_SHIFT 11
-#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_HYST_QN_Port_6_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: FC_WAN_IMP1_TOTAL_THD_HYST_QN_Port_6 :: TOTAL_HYST_THD [10:00] */
-#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_HYST_QN_Port_6_TOTAL_HYST_THD_MASK 0x000007ff
-#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_HYST_QN_Port_6_TOTAL_HYST_THD_SHIFT 0
-#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_HYST_QN_Port_6_TOTAL_HYST_THD_DEFAULT 0x000003c7
-
-/***************************************************************************
- *FC_WAN_IMP1_TOTAL_THD_HYST_QN_Port_7 - WAN/IMP1 Port Queue N Total Hysteresis Threshold RegisterNot2Release
- ***************************************************************************/
-/* SWITCH_CORE :: FC_WAN_IMP1_TOTAL_THD_HYST_QN_Port_7 :: reserved_for_padding0 [31:16] */
-#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_HYST_QN_Port_7_reserved_for_padding0_MASK 0xffff0000
-#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_HYST_QN_Port_7_reserved_for_padding0_SHIFT 16
-
-/* SWITCH_CORE :: FC_WAN_IMP1_TOTAL_THD_HYST_QN_Port_7 :: SWITCH_RESV [15:11] */
-#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_HYST_QN_Port_7_SWITCH_RESV_MASK 0x0000f800
-#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_HYST_QN_Port_7_SWITCH_RESV_SHIFT 11
-#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_HYST_QN_Port_7_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: FC_WAN_IMP1_TOTAL_THD_HYST_QN_Port_7 :: TOTAL_HYST_THD [10:00] */
-#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_HYST_QN_Port_7_TOTAL_HYST_THD_MASK 0x000007ff
-#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_HYST_QN_Port_7_TOTAL_HYST_THD_SHIFT 0
-#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_HYST_QN_Port_7_TOTAL_HYST_THD_DEFAULT 0x000003c7
-
-/***************************************************************************
- *FC_WAN_IMP1_TOTAL_THD_PAUSE_QN_Port_0 - WAN/IMP1 Port Queue N Total Pause Threshold RegisterNot2Release
- ***************************************************************************/
-/* SWITCH_CORE :: FC_WAN_IMP1_TOTAL_THD_PAUSE_QN_Port_0 :: reserved_for_padding0 [31:16] */
-#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_PAUSE_QN_Port_0_reserved_for_padding0_MASK 0xffff0000
-#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_PAUSE_QN_Port_0_reserved_for_padding0_SHIFT 16
-
-/* SWITCH_CORE :: FC_WAN_IMP1_TOTAL_THD_PAUSE_QN_Port_0 :: SWITCH_RESV [15:11] */
-#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_PAUSE_QN_Port_0_SWITCH_RESV_MASK 0x0000f800
-#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_PAUSE_QN_Port_0_SWITCH_RESV_SHIFT 11
-#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_PAUSE_QN_Port_0_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: FC_WAN_IMP1_TOTAL_THD_PAUSE_QN_Port_0 :: TOTAL_PAUSE_THD [10:00] */
-#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_PAUSE_QN_Port_0_TOTAL_PAUSE_THD_MASK 0x000007ff
-#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_PAUSE_QN_Port_0_TOTAL_PAUSE_THD_SHIFT 0
-#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_PAUSE_QN_Port_0_TOTAL_PAUSE_THD_DEFAULT 0x00000447
-
-/***************************************************************************
- *FC_WAN_IMP1_TOTAL_THD_PAUSE_QN_Port_1 - WAN/IMP1 Port Queue N Total Pause Threshold RegisterNot2Release
- ***************************************************************************/
-/* SWITCH_CORE :: FC_WAN_IMP1_TOTAL_THD_PAUSE_QN_Port_1 :: reserved_for_padding0 [31:16] */
-#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_PAUSE_QN_Port_1_reserved_for_padding0_MASK 0xffff0000
-#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_PAUSE_QN_Port_1_reserved_for_padding0_SHIFT 16
-
-/* SWITCH_CORE :: FC_WAN_IMP1_TOTAL_THD_PAUSE_QN_Port_1 :: SWITCH_RESV [15:11] */
-#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_PAUSE_QN_Port_1_SWITCH_RESV_MASK 0x0000f800
-#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_PAUSE_QN_Port_1_SWITCH_RESV_SHIFT 11
-#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_PAUSE_QN_Port_1_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: FC_WAN_IMP1_TOTAL_THD_PAUSE_QN_Port_1 :: TOTAL_PAUSE_THD [10:00] */
-#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_PAUSE_QN_Port_1_TOTAL_PAUSE_THD_MASK 0x000007ff
-#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_PAUSE_QN_Port_1_TOTAL_PAUSE_THD_SHIFT 0
-#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_PAUSE_QN_Port_1_TOTAL_PAUSE_THD_DEFAULT 0x0000044f
-
-/***************************************************************************
- *FC_WAN_IMP1_TOTAL_THD_PAUSE_QN_Port_2 - WAN/IMP1 Port Queue N Total Pause Threshold RegisterNot2Release
- ***************************************************************************/
-/* SWITCH_CORE :: FC_WAN_IMP1_TOTAL_THD_PAUSE_QN_Port_2 :: reserved_for_padding0 [31:16] */
-#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_PAUSE_QN_Port_2_reserved_for_padding0_MASK 0xffff0000
-#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_PAUSE_QN_Port_2_reserved_for_padding0_SHIFT 16
-
-/* SWITCH_CORE :: FC_WAN_IMP1_TOTAL_THD_PAUSE_QN_Port_2 :: SWITCH_RESV [15:11] */
-#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_PAUSE_QN_Port_2_SWITCH_RESV_MASK 0x0000f800
-#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_PAUSE_QN_Port_2_SWITCH_RESV_SHIFT 11
-#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_PAUSE_QN_Port_2_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: FC_WAN_IMP1_TOTAL_THD_PAUSE_QN_Port_2 :: TOTAL_PAUSE_THD [10:00] */
-#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_PAUSE_QN_Port_2_TOTAL_PAUSE_THD_MASK 0x000007ff
-#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_PAUSE_QN_Port_2_TOTAL_PAUSE_THD_SHIFT 0
-#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_PAUSE_QN_Port_2_TOTAL_PAUSE_THD_DEFAULT 0x00000457
-
-/***************************************************************************
- *FC_WAN_IMP1_TOTAL_THD_PAUSE_QN_Port_3 - WAN/IMP1 Port Queue N Total Pause Threshold RegisterNot2Release
- ***************************************************************************/
-/* SWITCH_CORE :: FC_WAN_IMP1_TOTAL_THD_PAUSE_QN_Port_3 :: reserved_for_padding0 [31:16] */
-#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_PAUSE_QN_Port_3_reserved_for_padding0_MASK 0xffff0000
-#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_PAUSE_QN_Port_3_reserved_for_padding0_SHIFT 16
-
-/* SWITCH_CORE :: FC_WAN_IMP1_TOTAL_THD_PAUSE_QN_Port_3 :: SWITCH_RESV [15:11] */
-#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_PAUSE_QN_Port_3_SWITCH_RESV_MASK 0x0000f800
-#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_PAUSE_QN_Port_3_SWITCH_RESV_SHIFT 11
-#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_PAUSE_QN_Port_3_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: FC_WAN_IMP1_TOTAL_THD_PAUSE_QN_Port_3 :: TOTAL_PAUSE_THD [10:00] */
-#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_PAUSE_QN_Port_3_TOTAL_PAUSE_THD_MASK 0x000007ff
-#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_PAUSE_QN_Port_3_TOTAL_PAUSE_THD_SHIFT 0
-#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_PAUSE_QN_Port_3_TOTAL_PAUSE_THD_DEFAULT 0x0000045f
-
-/***************************************************************************
- *FC_WAN_IMP1_TOTAL_THD_PAUSE_QN_Port_4 - WAN/IMP1 Port Queue N Total Pause Threshold RegisterNot2Release
- ***************************************************************************/
-/* SWITCH_CORE :: FC_WAN_IMP1_TOTAL_THD_PAUSE_QN_Port_4 :: reserved_for_padding0 [31:16] */
-#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_PAUSE_QN_Port_4_reserved_for_padding0_MASK 0xffff0000
-#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_PAUSE_QN_Port_4_reserved_for_padding0_SHIFT 16
-
-/* SWITCH_CORE :: FC_WAN_IMP1_TOTAL_THD_PAUSE_QN_Port_4 :: SWITCH_RESV [15:11] */
-#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_PAUSE_QN_Port_4_SWITCH_RESV_MASK 0x0000f800
-#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_PAUSE_QN_Port_4_SWITCH_RESV_SHIFT 11
-#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_PAUSE_QN_Port_4_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: FC_WAN_IMP1_TOTAL_THD_PAUSE_QN_Port_4 :: TOTAL_PAUSE_THD [10:00] */
-#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_PAUSE_QN_Port_4_TOTAL_PAUSE_THD_MASK 0x000007ff
-#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_PAUSE_QN_Port_4_TOTAL_PAUSE_THD_SHIFT 0
-#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_PAUSE_QN_Port_4_TOTAL_PAUSE_THD_DEFAULT 0x00000467
-
-/***************************************************************************
- *FC_WAN_IMP1_TOTAL_THD_PAUSE_QN_Port_5 - WAN/IMP1 Port Queue N Total Pause Threshold RegisterNot2Release
- ***************************************************************************/
-/* SWITCH_CORE :: FC_WAN_IMP1_TOTAL_THD_PAUSE_QN_Port_5 :: reserved_for_padding0 [31:16] */
-#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_PAUSE_QN_Port_5_reserved_for_padding0_MASK 0xffff0000
-#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_PAUSE_QN_Port_5_reserved_for_padding0_SHIFT 16
-
-/* SWITCH_CORE :: FC_WAN_IMP1_TOTAL_THD_PAUSE_QN_Port_5 :: SWITCH_RESV [15:11] */
-#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_PAUSE_QN_Port_5_SWITCH_RESV_MASK 0x0000f800
-#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_PAUSE_QN_Port_5_SWITCH_RESV_SHIFT 11
-#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_PAUSE_QN_Port_5_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: FC_WAN_IMP1_TOTAL_THD_PAUSE_QN_Port_5 :: TOTAL_PAUSE_THD [10:00] */
-#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_PAUSE_QN_Port_5_TOTAL_PAUSE_THD_MASK 0x000007ff
-#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_PAUSE_QN_Port_5_TOTAL_PAUSE_THD_SHIFT 0
-#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_PAUSE_QN_Port_5_TOTAL_PAUSE_THD_DEFAULT 0x0000046f
-
-/***************************************************************************
- *FC_WAN_IMP1_TOTAL_THD_PAUSE_QN_Port_6 - WAN/IMP1 Port Queue N Total Pause Threshold RegisterNot2Release
- ***************************************************************************/
-/* SWITCH_CORE :: FC_WAN_IMP1_TOTAL_THD_PAUSE_QN_Port_6 :: reserved_for_padding0 [31:16] */
-#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_PAUSE_QN_Port_6_reserved_for_padding0_MASK 0xffff0000
-#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_PAUSE_QN_Port_6_reserved_for_padding0_SHIFT 16
-
-/* SWITCH_CORE :: FC_WAN_IMP1_TOTAL_THD_PAUSE_QN_Port_6 :: SWITCH_RESV [15:11] */
-#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_PAUSE_QN_Port_6_SWITCH_RESV_MASK 0x0000f800
-#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_PAUSE_QN_Port_6_SWITCH_RESV_SHIFT 11
-#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_PAUSE_QN_Port_6_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: FC_WAN_IMP1_TOTAL_THD_PAUSE_QN_Port_6 :: TOTAL_PAUSE_THD [10:00] */
-#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_PAUSE_QN_Port_6_TOTAL_PAUSE_THD_MASK 0x000007ff
-#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_PAUSE_QN_Port_6_TOTAL_PAUSE_THD_SHIFT 0
-#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_PAUSE_QN_Port_6_TOTAL_PAUSE_THD_DEFAULT 0x00000477
-
-/***************************************************************************
- *FC_WAN_IMP1_TOTAL_THD_PAUSE_QN_Port_7 - WAN/IMP1 Port Queue N Total Pause Threshold RegisterNot2Release
- ***************************************************************************/
-/* SWITCH_CORE :: FC_WAN_IMP1_TOTAL_THD_PAUSE_QN_Port_7 :: reserved_for_padding0 [31:16] */
-#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_PAUSE_QN_Port_7_reserved_for_padding0_MASK 0xffff0000
-#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_PAUSE_QN_Port_7_reserved_for_padding0_SHIFT 16
-
-/* SWITCH_CORE :: FC_WAN_IMP1_TOTAL_THD_PAUSE_QN_Port_7 :: SWITCH_RESV [15:11] */
-#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_PAUSE_QN_Port_7_SWITCH_RESV_MASK 0x0000f800
-#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_PAUSE_QN_Port_7_SWITCH_RESV_SHIFT 11
-#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_PAUSE_QN_Port_7_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: FC_WAN_IMP1_TOTAL_THD_PAUSE_QN_Port_7 :: TOTAL_PAUSE_THD [10:00] */
-#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_PAUSE_QN_Port_7_TOTAL_PAUSE_THD_MASK 0x000007ff
-#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_PAUSE_QN_Port_7_TOTAL_PAUSE_THD_SHIFT 0
-#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_PAUSE_QN_Port_7_TOTAL_PAUSE_THD_DEFAULT 0x0000047f
-
-/***************************************************************************
- *FC_WAN_IMP1_TOTAL_THD_DROP_QN_Port_0 - WAN/IMP1 Port Queue N Total DROP Threshold RegisterNot2Release
- ***************************************************************************/
-/* SWITCH_CORE :: FC_WAN_IMP1_TOTAL_THD_DROP_QN_Port_0 :: reserved_for_padding0 [31:16] */
-#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_DROP_QN_Port_0_reserved_for_padding0_MASK 0xffff0000
-#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_DROP_QN_Port_0_reserved_for_padding0_SHIFT 16
-
-/* SWITCH_CORE :: FC_WAN_IMP1_TOTAL_THD_DROP_QN_Port_0 :: SWITCH_RESV [15:11] */
-#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_DROP_QN_Port_0_SWITCH_RESV_MASK 0x0000f800
-#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_DROP_QN_Port_0_SWITCH_RESV_SHIFT 11
-#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_DROP_QN_Port_0_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: FC_WAN_IMP1_TOTAL_THD_DROP_QN_Port_0 :: TOTAL_DROP_THD [10:00] */
-#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_DROP_QN_Port_0_TOTAL_DROP_THD_MASK 0x000007ff
-#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_DROP_QN_Port_0_TOTAL_DROP_THD_SHIFT 0
-#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_DROP_QN_Port_0_TOTAL_DROP_THD_DEFAULT 0x000005c7
-
-/***************************************************************************
- *FC_WAN_IMP1_TOTAL_THD_DROP_QN_Port_1 - WAN/IMP1 Port Queue N Total DROP Threshold RegisterNot2Release
- ***************************************************************************/
-/* SWITCH_CORE :: FC_WAN_IMP1_TOTAL_THD_DROP_QN_Port_1 :: reserved_for_padding0 [31:16] */
-#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_DROP_QN_Port_1_reserved_for_padding0_MASK 0xffff0000
-#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_DROP_QN_Port_1_reserved_for_padding0_SHIFT 16
-
-/* SWITCH_CORE :: FC_WAN_IMP1_TOTAL_THD_DROP_QN_Port_1 :: SWITCH_RESV [15:11] */
-#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_DROP_QN_Port_1_SWITCH_RESV_MASK 0x0000f800
-#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_DROP_QN_Port_1_SWITCH_RESV_SHIFT 11
-#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_DROP_QN_Port_1_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: FC_WAN_IMP1_TOTAL_THD_DROP_QN_Port_1 :: TOTAL_DROP_THD [10:00] */
-#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_DROP_QN_Port_1_TOTAL_DROP_THD_MASK 0x000007ff
-#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_DROP_QN_Port_1_TOTAL_DROP_THD_SHIFT 0
-#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_DROP_QN_Port_1_TOTAL_DROP_THD_DEFAULT 0x000005cf
-
-/***************************************************************************
- *FC_WAN_IMP1_TOTAL_THD_DROP_QN_Port_2 - WAN/IMP1 Port Queue N Total DROP Threshold RegisterNot2Release
- ***************************************************************************/
-/* SWITCH_CORE :: FC_WAN_IMP1_TOTAL_THD_DROP_QN_Port_2 :: reserved_for_padding0 [31:16] */
-#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_DROP_QN_Port_2_reserved_for_padding0_MASK 0xffff0000
-#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_DROP_QN_Port_2_reserved_for_padding0_SHIFT 16
-
-/* SWITCH_CORE :: FC_WAN_IMP1_TOTAL_THD_DROP_QN_Port_2 :: SWITCH_RESV [15:11] */
-#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_DROP_QN_Port_2_SWITCH_RESV_MASK 0x0000f800
-#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_DROP_QN_Port_2_SWITCH_RESV_SHIFT 11
-#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_DROP_QN_Port_2_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: FC_WAN_IMP1_TOTAL_THD_DROP_QN_Port_2 :: TOTAL_DROP_THD [10:00] */
-#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_DROP_QN_Port_2_TOTAL_DROP_THD_MASK 0x000007ff
-#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_DROP_QN_Port_2_TOTAL_DROP_THD_SHIFT 0
-#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_DROP_QN_Port_2_TOTAL_DROP_THD_DEFAULT 0x000005d7
-
-/***************************************************************************
- *FC_WAN_IMP1_TOTAL_THD_DROP_QN_Port_3 - WAN/IMP1 Port Queue N Total DROP Threshold RegisterNot2Release
- ***************************************************************************/
-/* SWITCH_CORE :: FC_WAN_IMP1_TOTAL_THD_DROP_QN_Port_3 :: reserved_for_padding0 [31:16] */
-#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_DROP_QN_Port_3_reserved_for_padding0_MASK 0xffff0000
-#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_DROP_QN_Port_3_reserved_for_padding0_SHIFT 16
-
-/* SWITCH_CORE :: FC_WAN_IMP1_TOTAL_THD_DROP_QN_Port_3 :: SWITCH_RESV [15:11] */
-#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_DROP_QN_Port_3_SWITCH_RESV_MASK 0x0000f800
-#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_DROP_QN_Port_3_SWITCH_RESV_SHIFT 11
-#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_DROP_QN_Port_3_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: FC_WAN_IMP1_TOTAL_THD_DROP_QN_Port_3 :: TOTAL_DROP_THD [10:00] */
-#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_DROP_QN_Port_3_TOTAL_DROP_THD_MASK 0x000007ff
-#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_DROP_QN_Port_3_TOTAL_DROP_THD_SHIFT 0
-#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_DROP_QN_Port_3_TOTAL_DROP_THD_DEFAULT 0x000005df
-
-/***************************************************************************
- *FC_WAN_IMP1_TOTAL_THD_DROP_QN_Port_4 - WAN/IMP1 Port Queue N Total DROP Threshold RegisterNot2Release
- ***************************************************************************/
-/* SWITCH_CORE :: FC_WAN_IMP1_TOTAL_THD_DROP_QN_Port_4 :: reserved_for_padding0 [31:16] */
-#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_DROP_QN_Port_4_reserved_for_padding0_MASK 0xffff0000
-#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_DROP_QN_Port_4_reserved_for_padding0_SHIFT 16
-
-/* SWITCH_CORE :: FC_WAN_IMP1_TOTAL_THD_DROP_QN_Port_4 :: SWITCH_RESV [15:11] */
-#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_DROP_QN_Port_4_SWITCH_RESV_MASK 0x0000f800
-#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_DROP_QN_Port_4_SWITCH_RESV_SHIFT 11
-#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_DROP_QN_Port_4_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: FC_WAN_IMP1_TOTAL_THD_DROP_QN_Port_4 :: TOTAL_DROP_THD [10:00] */
-#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_DROP_QN_Port_4_TOTAL_DROP_THD_MASK 0x000007ff
-#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_DROP_QN_Port_4_TOTAL_DROP_THD_SHIFT 0
-#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_DROP_QN_Port_4_TOTAL_DROP_THD_DEFAULT 0x000005e7
-
-/***************************************************************************
- *FC_WAN_IMP1_TOTAL_THD_DROP_QN_Port_5 - WAN/IMP1 Port Queue N Total DROP Threshold RegisterNot2Release
- ***************************************************************************/
-/* SWITCH_CORE :: FC_WAN_IMP1_TOTAL_THD_DROP_QN_Port_5 :: reserved_for_padding0 [31:16] */
-#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_DROP_QN_Port_5_reserved_for_padding0_MASK 0xffff0000
-#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_DROP_QN_Port_5_reserved_for_padding0_SHIFT 16
-
-/* SWITCH_CORE :: FC_WAN_IMP1_TOTAL_THD_DROP_QN_Port_5 :: SWITCH_RESV [15:11] */
-#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_DROP_QN_Port_5_SWITCH_RESV_MASK 0x0000f800
-#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_DROP_QN_Port_5_SWITCH_RESV_SHIFT 11
-#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_DROP_QN_Port_5_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: FC_WAN_IMP1_TOTAL_THD_DROP_QN_Port_5 :: TOTAL_DROP_THD [10:00] */
-#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_DROP_QN_Port_5_TOTAL_DROP_THD_MASK 0x000007ff
-#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_DROP_QN_Port_5_TOTAL_DROP_THD_SHIFT 0
-#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_DROP_QN_Port_5_TOTAL_DROP_THD_DEFAULT 0x000005ef
-
-/***************************************************************************
- *FC_WAN_IMP1_TOTAL_THD_DROP_QN_Port_6 - WAN/IMP1 Port Queue N Total DROP Threshold RegisterNot2Release
- ***************************************************************************/
-/* SWITCH_CORE :: FC_WAN_IMP1_TOTAL_THD_DROP_QN_Port_6 :: reserved_for_padding0 [31:16] */
-#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_DROP_QN_Port_6_reserved_for_padding0_MASK 0xffff0000
-#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_DROP_QN_Port_6_reserved_for_padding0_SHIFT 16
-
-/* SWITCH_CORE :: FC_WAN_IMP1_TOTAL_THD_DROP_QN_Port_6 :: SWITCH_RESV [15:11] */
-#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_DROP_QN_Port_6_SWITCH_RESV_MASK 0x0000f800
-#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_DROP_QN_Port_6_SWITCH_RESV_SHIFT 11
-#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_DROP_QN_Port_6_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: FC_WAN_IMP1_TOTAL_THD_DROP_QN_Port_6 :: TOTAL_DROP_THD [10:00] */
-#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_DROP_QN_Port_6_TOTAL_DROP_THD_MASK 0x000007ff
-#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_DROP_QN_Port_6_TOTAL_DROP_THD_SHIFT 0
-#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_DROP_QN_Port_6_TOTAL_DROP_THD_DEFAULT 0x000005f7
-
-/***************************************************************************
- *FC_WAN_IMP1_TOTAL_THD_DROP_QN_Port_7 - WAN/IMP1 Port Queue N Total DROP Threshold RegisterNot2Release
- ***************************************************************************/
-/* SWITCH_CORE :: FC_WAN_IMP1_TOTAL_THD_DROP_QN_Port_7 :: reserved_for_padding0 [31:16] */
-#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_DROP_QN_Port_7_reserved_for_padding0_MASK 0xffff0000
-#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_DROP_QN_Port_7_reserved_for_padding0_SHIFT 16
-
-/* SWITCH_CORE :: FC_WAN_IMP1_TOTAL_THD_DROP_QN_Port_7 :: SWITCH_RESV [15:11] */
-#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_DROP_QN_Port_7_SWITCH_RESV_MASK 0x0000f800
-#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_DROP_QN_Port_7_SWITCH_RESV_SHIFT 11
-#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_DROP_QN_Port_7_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: FC_WAN_IMP1_TOTAL_THD_DROP_QN_Port_7 :: TOTAL_DROP_THD [10:00] */
-#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_DROP_QN_Port_7_TOTAL_DROP_THD_MASK 0x000007ff
-#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_DROP_QN_Port_7_TOTAL_DROP_THD_SHIFT 0
-#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_DROP_QN_Port_7_TOTAL_DROP_THD_DEFAULT 0x000005ff
-
-/***************************************************************************
- *FC_WAN_IMP1_REG_SPARE0 - Spare 0 Register (Not2Release)Not2Release
- ***************************************************************************/
-/* SWITCH_CORE :: FC_WAN_IMP1_REG_SPARE0 :: reserved_for_padding0 [31:16] */
-#define BCHP_SWITCH_CORE_FC_WAN_IMP1_REG_SPARE0_reserved_for_padding0_MASK 0xffff0000
-#define BCHP_SWITCH_CORE_FC_WAN_IMP1_REG_SPARE0_reserved_for_padding0_SHIFT 16
-
-/* SWITCH_CORE :: FC_WAN_IMP1_REG_SPARE0 :: FC_WAN_IMP1_REG_SPARE0 [15:00] */
-#define BCHP_SWITCH_CORE_FC_WAN_IMP1_REG_SPARE0_FC_WAN_IMP1_REG_SPARE0_MASK 0x0000ffff
-#define BCHP_SWITCH_CORE_FC_WAN_IMP1_REG_SPARE0_FC_WAN_IMP1_REG_SPARE0_SHIFT 0
-#define BCHP_SWITCH_CORE_FC_WAN_IMP1_REG_SPARE0_FC_WAN_IMP1_REG_SPARE0_DEFAULT 0x00000000
-
-/***************************************************************************
- *FC_WAN_IMP1_REG_SPARE1 - Spare 1 Register (Not2Release)Not2Release
- ***************************************************************************/
-/* SWITCH_CORE :: FC_WAN_IMP1_REG_SPARE1 :: reserved_for_padding0 [31:16] */
-#define BCHP_SWITCH_CORE_FC_WAN_IMP1_REG_SPARE1_reserved_for_padding0_MASK 0xffff0000
-#define BCHP_SWITCH_CORE_FC_WAN_IMP1_REG_SPARE1_reserved_for_padding0_SHIFT 16
-
-/* SWITCH_CORE :: FC_WAN_IMP1_REG_SPARE1 :: FC_WAN_IMP1_REG_SPARE1 [15:00] */
-#define BCHP_SWITCH_CORE_FC_WAN_IMP1_REG_SPARE1_FC_WAN_IMP1_REG_SPARE1_MASK 0x0000ffff
-#define BCHP_SWITCH_CORE_FC_WAN_IMP1_REG_SPARE1_FC_WAN_IMP1_REG_SPARE1_SHIFT 0
-#define BCHP_SWITCH_CORE_FC_WAN_IMP1_REG_SPARE1_FC_WAN_IMP1_REG_SPARE1_DEFAULT 0x00000000
-
-/***************************************************************************
- *TEMP_MON_CTL - Temperature Monitor Control Registers(Not2Release)Not2Release
- ***************************************************************************/
-/* SWITCH_CORE :: TEMP_MON_CTL :: reserved_for_padding0 [31:08] */
-#define BCHP_SWITCH_CORE_TEMP_MON_CTL_reserved_for_padding0_MASK 0xffffff00
-#define BCHP_SWITCH_CORE_TEMP_MON_CTL_reserved_for_padding0_SHIFT 8
-
-/* SWITCH_CORE :: TEMP_MON_CTL :: BIAS_ADJUST [07:01] */
-#define BCHP_SWITCH_CORE_TEMP_MON_CTL_BIAS_ADJUST_MASK 0x000000fe
-#define BCHP_SWITCH_CORE_TEMP_MON_CTL_BIAS_ADJUST_SHIFT 1
-#define BCHP_SWITCH_CORE_TEMP_MON_CTL_BIAS_ADJUST_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: TEMP_MON_CTL :: ADC_TEST_EN [00:00] */
-#define BCHP_SWITCH_CORE_TEMP_MON_CTL_ADC_TEST_EN_MASK 0x00000001
-#define BCHP_SWITCH_CORE_TEMP_MON_CTL_ADC_TEST_EN_SHIFT 0
-#define BCHP_SWITCH_CORE_TEMP_MON_CTL_ADC_TEST_EN_DEFAULT 0x00000001
-
-/***************************************************************************
- *TEMP_MON_RESU - Temperature Monitor Result Registers(Not2Release)Not2Release
- ***************************************************************************/
-/* SWITCH_CORE :: TEMP_MON_RESU :: reserved_for_padding0 [31:16] */
-#define BCHP_SWITCH_CORE_TEMP_MON_RESU_reserved_for_padding0_MASK 0xffff0000
-#define BCHP_SWITCH_CORE_TEMP_MON_RESU_reserved_for_padding0_SHIFT 16
-
-/* SWITCH_CORE :: TEMP_MON_RESU :: SWITCH_RESV [15:09] */
-#define BCHP_SWITCH_CORE_TEMP_MON_RESU_SWITCH_RESV_MASK 0x0000fe00
-#define BCHP_SWITCH_CORE_TEMP_MON_RESU_SWITCH_RESV_SHIFT 9
-#define BCHP_SWITCH_CORE_TEMP_MON_RESU_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: TEMP_MON_RESU :: TEMP_DATA [08:00] */
-#define BCHP_SWITCH_CORE_TEMP_MON_RESU_TEMP_DATA_MASK 0x000001ff
-#define BCHP_SWITCH_CORE_TEMP_MON_RESU_TEMP_DATA_SHIFT 0
-#define BCHP_SWITCH_CORE_TEMP_MON_RESU_TEMP_DATA_DEFAULT 0x000001ff
-
-/***************************************************************************
- *PEAK_TEMP_MON_RESU - Peak Temperature Monitor Result Registers(Not2Release)Not2Release
- ***************************************************************************/
-/* SWITCH_CORE :: PEAK_TEMP_MON_RESU :: reserved_for_padding0 [31:16] */
-#define BCHP_SWITCH_CORE_PEAK_TEMP_MON_RESU_reserved_for_padding0_MASK 0xffff0000
-#define BCHP_SWITCH_CORE_PEAK_TEMP_MON_RESU_reserved_for_padding0_SHIFT 16
-
-/* SWITCH_CORE :: PEAK_TEMP_MON_RESU :: SWITCH_RESV [15:09] */
-#define BCHP_SWITCH_CORE_PEAK_TEMP_MON_RESU_SWITCH_RESV_MASK 0x0000fe00
-#define BCHP_SWITCH_CORE_PEAK_TEMP_MON_RESU_SWITCH_RESV_SHIFT 9
-#define BCHP_SWITCH_CORE_PEAK_TEMP_MON_RESU_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: PEAK_TEMP_MON_RESU :: PEAK_TEMP_DATA [08:00] */
-#define BCHP_SWITCH_CORE_PEAK_TEMP_MON_RESU_PEAK_TEMP_DATA_MASK 0x000001ff
-#define BCHP_SWITCH_CORE_PEAK_TEMP_MON_RESU_PEAK_TEMP_DATA_SHIFT 0
-#define BCHP_SWITCH_CORE_PEAK_TEMP_MON_RESU_PEAK_TEMP_DATA_DEFAULT 0x000001ff
-
-/***************************************************************************
- *TEMP_MON_CAL - Temperature Monitor Calibration Registers(Not2Release)Not2Release
- ***************************************************************************/
-/* SWITCH_CORE :: TEMP_MON_CAL :: reserved_for_padding0 [31:16] */
-#define BCHP_SWITCH_CORE_TEMP_MON_CAL_reserved_for_padding0_MASK 0xffff0000
-#define BCHP_SWITCH_CORE_TEMP_MON_CAL_reserved_for_padding0_SHIFT 16
-
-/* SWITCH_CORE :: TEMP_MON_CAL :: SWITCH_RESV [15:09] */
-#define BCHP_SWITCH_CORE_TEMP_MON_CAL_SWITCH_RESV_MASK 0x0000fe00
-#define BCHP_SWITCH_CORE_TEMP_MON_CAL_SWITCH_RESV_SHIFT 9
-#define BCHP_SWITCH_CORE_TEMP_MON_CAL_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: TEMP_MON_CAL :: TEMP_DATA_25C [08:00] */
-#define BCHP_SWITCH_CORE_TEMP_MON_CAL_TEMP_DATA_25C_MASK 0x000001ff
-#define BCHP_SWITCH_CORE_TEMP_MON_CAL_TEMP_DATA_25C_SHIFT 0
-#define BCHP_SWITCH_CORE_TEMP_MON_CAL_TEMP_DATA_25C_DEFAULT 0x0000015a
-
-/***************************************************************************
- *TEMP_MON_SPEC_CTL - Temperature Monitor Special Control Registers(Not2Release)Not2Release
- ***************************************************************************/
-/* SWITCH_CORE :: TEMP_MON_SPEC_CTL :: reserved_for_padding0 [31:08] */
-#define BCHP_SWITCH_CORE_TEMP_MON_SPEC_CTL_reserved_for_padding0_MASK 0xffffff00
-#define BCHP_SWITCH_CORE_TEMP_MON_SPEC_CTL_reserved_for_padding0_SHIFT 8
-
-/* SWITCH_CORE :: TEMP_MON_SPEC_CTL :: SWITCH_RESV [07:01] */
-#define BCHP_SWITCH_CORE_TEMP_MON_SPEC_CTL_SWITCH_RESV_MASK 0x000000fe
-#define BCHP_SWITCH_CORE_TEMP_MON_SPEC_CTL_SWITCH_RESV_SHIFT 1
-#define BCHP_SWITCH_CORE_TEMP_MON_SPEC_CTL_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: TEMP_MON_SPEC_CTL :: TEMP_PWRDN [00:00] */
-#define BCHP_SWITCH_CORE_TEMP_MON_SPEC_CTL_TEMP_PWRDN_MASK 0x00000001
-#define BCHP_SWITCH_CORE_TEMP_MON_SPEC_CTL_TEMP_PWRDN_SHIFT 0
-#define BCHP_SWITCH_CORE_TEMP_MON_SPEC_CTL_TEMP_PWRDN_DEFAULT 0x00000000
-
-/***************************************************************************
- *TxOctets_P0 - Tx Octets
- ***************************************************************************/
-/* SWITCH_CORE :: TxOctets_P0 :: COUNT [63:00] */
-#define BCHP_SWITCH_CORE_TxOctets_P0_COUNT_MASK 0x00000000ffffffff
-#define BCHP_SWITCH_CORE_TxOctets_P0_COUNT_SHIFT 0
-#define BCHP_SWITCH_CORE_TxOctets_P0_COUNT_DEFAULT 0x0000000000000000
-
-/***************************************************************************
- *TxDropPkts_P0 - Tx Drop Packet Counter
- ***************************************************************************/
-/* SWITCH_CORE :: TxDropPkts_P0 :: COUNT [31:00] */
-#define BCHP_SWITCH_CORE_TxDropPkts_P0_COUNT_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_TxDropPkts_P0_COUNT_SHIFT 0
-#define BCHP_SWITCH_CORE_TxDropPkts_P0_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *TxQPKTQ0_P0 - Tx Q0 Packet Counter
- ***************************************************************************/
-/* SWITCH_CORE :: TxQPKTQ0_P0 :: COUNT [31:00] */
-#define BCHP_SWITCH_CORE_TxQPKTQ0_P0_COUNT_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_TxQPKTQ0_P0_COUNT_SHIFT 0
-#define BCHP_SWITCH_CORE_TxQPKTQ0_P0_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *TxBroadcastPkts_P0 - Tx Broadcast Packet Counter
- ***************************************************************************/
-/* SWITCH_CORE :: TxBroadcastPkts_P0 :: COUNT [31:00] */
-#define BCHP_SWITCH_CORE_TxBroadcastPkts_P0_COUNT_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_TxBroadcastPkts_P0_COUNT_SHIFT 0
-#define BCHP_SWITCH_CORE_TxBroadcastPkts_P0_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *TxMulticastPkts_P0 - Tx Multicast Packet Counter
- ***************************************************************************/
-/* SWITCH_CORE :: TxMulticastPkts_P0 :: COUNT [31:00] */
-#define BCHP_SWITCH_CORE_TxMulticastPkts_P0_COUNT_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_TxMulticastPkts_P0_COUNT_SHIFT 0
-#define BCHP_SWITCH_CORE_TxMulticastPkts_P0_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *TxUnicastPkts_P0 - Tx Unicast Packet Counter
- ***************************************************************************/
-/* SWITCH_CORE :: TxUnicastPkts_P0 :: COUNT [31:00] */
-#define BCHP_SWITCH_CORE_TxUnicastPkts_P0_COUNT_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_TxUnicastPkts_P0_COUNT_SHIFT 0
-#define BCHP_SWITCH_CORE_TxUnicastPkts_P0_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *TxCollisions_P0 - Tx Collision Counter
- ***************************************************************************/
-/* SWITCH_CORE :: TxCollisions_P0 :: COUNT [31:00] */
-#define BCHP_SWITCH_CORE_TxCollisions_P0_COUNT_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_TxCollisions_P0_COUNT_SHIFT 0
-#define BCHP_SWITCH_CORE_TxCollisions_P0_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *TxSingleCollision_P0 - Tx Single Collision Counter
- ***************************************************************************/
-/* SWITCH_CORE :: TxSingleCollision_P0 :: COUNT [31:00] */
-#define BCHP_SWITCH_CORE_TxSingleCollision_P0_COUNT_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_TxSingleCollision_P0_COUNT_SHIFT 0
-#define BCHP_SWITCH_CORE_TxSingleCollision_P0_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *TxMultipleCollision_P0 - Tx Multiple collsion Counter
- ***************************************************************************/
-/* SWITCH_CORE :: TxMultipleCollision_P0 :: COUNT [31:00] */
-#define BCHP_SWITCH_CORE_TxMultipleCollision_P0_COUNT_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_TxMultipleCollision_P0_COUNT_SHIFT 0
-#define BCHP_SWITCH_CORE_TxMultipleCollision_P0_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *TxDeferredTransmit_P0 - Tx Deferred Transmit Counter
- ***************************************************************************/
-/* SWITCH_CORE :: TxDeferredTransmit_P0 :: COUNT [31:00] */
-#define BCHP_SWITCH_CORE_TxDeferredTransmit_P0_COUNT_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_TxDeferredTransmit_P0_COUNT_SHIFT 0
-#define BCHP_SWITCH_CORE_TxDeferredTransmit_P0_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *TxLateCollision_P0 - Tx Late Collision Counter
- ***************************************************************************/
-/* SWITCH_CORE :: TxLateCollision_P0 :: COUNT [31:00] */
-#define BCHP_SWITCH_CORE_TxLateCollision_P0_COUNT_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_TxLateCollision_P0_COUNT_SHIFT 0
-#define BCHP_SWITCH_CORE_TxLateCollision_P0_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *TxExcessiveCollision_P0 - Tx Excessive Collision Counter
- ***************************************************************************/
-/* SWITCH_CORE :: TxExcessiveCollision_P0 :: COUNT [31:00] */
-#define BCHP_SWITCH_CORE_TxExcessiveCollision_P0_COUNT_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_TxExcessiveCollision_P0_COUNT_SHIFT 0
-#define BCHP_SWITCH_CORE_TxExcessiveCollision_P0_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *TxFrameInDisc_P0 - Tx Fram IN Disc Counter
- ***************************************************************************/
-/* SWITCH_CORE :: TxFrameInDisc_P0 :: COUNT [31:00] */
-#define BCHP_SWITCH_CORE_TxFrameInDisc_P0_COUNT_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_TxFrameInDisc_P0_COUNT_SHIFT 0
-#define BCHP_SWITCH_CORE_TxFrameInDisc_P0_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *TxPausePkts_P0 - Tx Pause Packet Counter
- ***************************************************************************/
-/* SWITCH_CORE :: TxPausePkts_P0 :: COUNT [31:00] */
-#define BCHP_SWITCH_CORE_TxPausePkts_P0_COUNT_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_TxPausePkts_P0_COUNT_SHIFT 0
-#define BCHP_SWITCH_CORE_TxPausePkts_P0_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *TxQPKTQ1_P0 - Tx Q1 Packet Counter
- ***************************************************************************/
-/* SWITCH_CORE :: TxQPKTQ1_P0 :: COUNT [31:00] */
-#define BCHP_SWITCH_CORE_TxQPKTQ1_P0_COUNT_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_TxQPKTQ1_P0_COUNT_SHIFT 0
-#define BCHP_SWITCH_CORE_TxQPKTQ1_P0_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *TxQPKTQ2_P0 - Tx Q2 Packet Counter
- ***************************************************************************/
-/* SWITCH_CORE :: TxQPKTQ2_P0 :: COUNT [31:00] */
-#define BCHP_SWITCH_CORE_TxQPKTQ2_P0_COUNT_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_TxQPKTQ2_P0_COUNT_SHIFT 0
-#define BCHP_SWITCH_CORE_TxQPKTQ2_P0_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *TxQPKTQ3_P0 - Tx Q3 Packet Counter
- ***************************************************************************/
-/* SWITCH_CORE :: TxQPKTQ3_P0 :: COUNT [31:00] */
-#define BCHP_SWITCH_CORE_TxQPKTQ3_P0_COUNT_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_TxQPKTQ3_P0_COUNT_SHIFT 0
-#define BCHP_SWITCH_CORE_TxQPKTQ3_P0_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *TxQPKTQ4_P0 - Tx Q4 Packet Counter
- ***************************************************************************/
-/* SWITCH_CORE :: TxQPKTQ4_P0 :: COUNT [31:00] */
-#define BCHP_SWITCH_CORE_TxQPKTQ4_P0_COUNT_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_TxQPKTQ4_P0_COUNT_SHIFT 0
-#define BCHP_SWITCH_CORE_TxQPKTQ4_P0_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *TxQPKTQ5_P0 - Tx Q5 Packet Counter
- ***************************************************************************/
-/* SWITCH_CORE :: TxQPKTQ5_P0 :: COUNT [31:00] */
-#define BCHP_SWITCH_CORE_TxQPKTQ5_P0_COUNT_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_TxQPKTQ5_P0_COUNT_SHIFT 0
-#define BCHP_SWITCH_CORE_TxQPKTQ5_P0_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *RxOctets_P0 - Rx Packet Octets Counter
- ***************************************************************************/
-/* SWITCH_CORE :: RxOctets_P0 :: COUNT [63:00] */
-#define BCHP_SWITCH_CORE_RxOctets_P0_COUNT_MASK 0x00000000ffffffff
-#define BCHP_SWITCH_CORE_RxOctets_P0_COUNT_SHIFT 0
-#define BCHP_SWITCH_CORE_RxOctets_P0_COUNT_DEFAULT 0x0000000000000000
-
-/***************************************************************************
- *RxUndersizePkts_P0 - Rx Under Size Packet Octets Counter
- ***************************************************************************/
-/* SWITCH_CORE :: RxUndersizePkts_P0 :: COUNT [31:00] */
-#define BCHP_SWITCH_CORE_RxUndersizePkts_P0_COUNT_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_RxUndersizePkts_P0_COUNT_SHIFT 0
-#define BCHP_SWITCH_CORE_RxUndersizePkts_P0_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *RxPausePkts_P0 - Rx Pause Packet Counter
- ***************************************************************************/
-/* SWITCH_CORE :: RxPausePkts_P0 :: COUNT [31:00] */
-#define BCHP_SWITCH_CORE_RxPausePkts_P0_COUNT_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_RxPausePkts_P0_COUNT_SHIFT 0
-#define BCHP_SWITCH_CORE_RxPausePkts_P0_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *RxPkts64Octets_P0 - Rx 64 Bytes Octets Counter
- ***************************************************************************/
-/* SWITCH_CORE :: RxPkts64Octets_P0 :: COUNT [31:00] */
-#define BCHP_SWITCH_CORE_RxPkts64Octets_P0_COUNT_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_RxPkts64Octets_P0_COUNT_SHIFT 0
-#define BCHP_SWITCH_CORE_RxPkts64Octets_P0_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *RxPkts65to127Octets_P0 - Rx 65 to 127 Bytes Octets Counter
- ***************************************************************************/
-/* SWITCH_CORE :: RxPkts65to127Octets_P0 :: COUNT [31:00] */
-#define BCHP_SWITCH_CORE_RxPkts65to127Octets_P0_COUNT_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_RxPkts65to127Octets_P0_COUNT_SHIFT 0
-#define BCHP_SWITCH_CORE_RxPkts65to127Octets_P0_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *RxPkts128to255Octets_P0 - Rx 128 to 255 Bytes Octets Counter
- ***************************************************************************/
-/* SWITCH_CORE :: RxPkts128to255Octets_P0 :: COUNT [31:00] */
-#define BCHP_SWITCH_CORE_RxPkts128to255Octets_P0_COUNT_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_RxPkts128to255Octets_P0_COUNT_SHIFT 0
-#define BCHP_SWITCH_CORE_RxPkts128to255Octets_P0_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *RxPkts256to511Octets_P0 - Rx 256 to 511 Bytes Octets Counter
- ***************************************************************************/
-/* SWITCH_CORE :: RxPkts256to511Octets_P0 :: COUNT [31:00] */
-#define BCHP_SWITCH_CORE_RxPkts256to511Octets_P0_COUNT_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_RxPkts256to511Octets_P0_COUNT_SHIFT 0
-#define BCHP_SWITCH_CORE_RxPkts256to511Octets_P0_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *RxPkts512to1023Octets_P0 - Rx 512 to 1023 Bytes Octets Counter
- ***************************************************************************/
-/* SWITCH_CORE :: RxPkts512to1023Octets_P0 :: COUNT [31:00] */
-#define BCHP_SWITCH_CORE_RxPkts512to1023Octets_P0_COUNT_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_RxPkts512to1023Octets_P0_COUNT_SHIFT 0
-#define BCHP_SWITCH_CORE_RxPkts512to1023Octets_P0_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *RxPkts1024toMaxPktOctets_P0 - Rx 1024 to MaxPkt Bytes Octets Counter
- ***************************************************************************/
-/* SWITCH_CORE :: RxPkts1024toMaxPktOctets_P0 :: COUNT [31:00] */
-#define BCHP_SWITCH_CORE_RxPkts1024toMaxPktOctets_P0_COUNT_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_RxPkts1024toMaxPktOctets_P0_COUNT_SHIFT 0
-#define BCHP_SWITCH_CORE_RxPkts1024toMaxPktOctets_P0_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *RxOversizePkts_P0 - Rx Over Size Packet Counter
- ***************************************************************************/
-/* SWITCH_CORE :: RxOversizePkts_P0 :: COUNT [31:00] */
-#define BCHP_SWITCH_CORE_RxOversizePkts_P0_COUNT_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_RxOversizePkts_P0_COUNT_SHIFT 0
-#define BCHP_SWITCH_CORE_RxOversizePkts_P0_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *RxJabbers_P0 - Rx Jabber Packet Counter
- ***************************************************************************/
-/* SWITCH_CORE :: RxJabbers_P0 :: COUNT [31:00] */
-#define BCHP_SWITCH_CORE_RxJabbers_P0_COUNT_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_RxJabbers_P0_COUNT_SHIFT 0
-#define BCHP_SWITCH_CORE_RxJabbers_P0_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *RxAlignmentErrors_P0 - Rx Alignment Error Counter
- ***************************************************************************/
-/* SWITCH_CORE :: RxAlignmentErrors_P0 :: COUNT [31:00] */
-#define BCHP_SWITCH_CORE_RxAlignmentErrors_P0_COUNT_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_RxAlignmentErrors_P0_COUNT_SHIFT 0
-#define BCHP_SWITCH_CORE_RxAlignmentErrors_P0_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *RxFCSErrors_P0 - Rx FCS Error Counter
- ***************************************************************************/
-/* SWITCH_CORE :: RxFCSErrors_P0 :: COUNT [31:00] */
-#define BCHP_SWITCH_CORE_RxFCSErrors_P0_COUNT_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_RxFCSErrors_P0_COUNT_SHIFT 0
-#define BCHP_SWITCH_CORE_RxFCSErrors_P0_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *RxGoodOctets_P0 - Rx Good Packet Octet Counter
- ***************************************************************************/
-/* SWITCH_CORE :: RxGoodOctets_P0 :: COUNT [63:00] */
-#define BCHP_SWITCH_CORE_RxGoodOctets_P0_COUNT_MASK 0x00000000ffffffff
-#define BCHP_SWITCH_CORE_RxGoodOctets_P0_COUNT_SHIFT 0
-#define BCHP_SWITCH_CORE_RxGoodOctets_P0_COUNT_DEFAULT 0x0000000000000000
-
-/***************************************************************************
- *RxDropPkts_P0 - Rx Drop Packet Counter
- ***************************************************************************/
-/* SWITCH_CORE :: RxDropPkts_P0 :: COUNT [31:00] */
-#define BCHP_SWITCH_CORE_RxDropPkts_P0_COUNT_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_RxDropPkts_P0_COUNT_SHIFT 0
-#define BCHP_SWITCH_CORE_RxDropPkts_P0_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *RxUnicastPkts_P0 - Rx Unicast Packet Counter
- ***************************************************************************/
-/* SWITCH_CORE :: RxUnicastPkts_P0 :: COUNT [31:00] */
-#define BCHP_SWITCH_CORE_RxUnicastPkts_P0_COUNT_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_RxUnicastPkts_P0_COUNT_SHIFT 0
-#define BCHP_SWITCH_CORE_RxUnicastPkts_P0_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *RxMulticastPkts_P0 - Rx Multicast Packet Counter
- ***************************************************************************/
-/* SWITCH_CORE :: RxMulticastPkts_P0 :: COUNT [31:00] */
-#define BCHP_SWITCH_CORE_RxMulticastPkts_P0_COUNT_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_RxMulticastPkts_P0_COUNT_SHIFT 0
-#define BCHP_SWITCH_CORE_RxMulticastPkts_P0_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *RxBroadcastPkts_P0 - Rx Broadcast Packet Counter
- ***************************************************************************/
-/* SWITCH_CORE :: RxBroadcastPkts_P0 :: COUNT [31:00] */
-#define BCHP_SWITCH_CORE_RxBroadcastPkts_P0_COUNT_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_RxBroadcastPkts_P0_COUNT_SHIFT 0
-#define BCHP_SWITCH_CORE_RxBroadcastPkts_P0_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *RxSAChanges_P0 - Rx SA Change Counter
- ***************************************************************************/
-/* SWITCH_CORE :: RxSAChanges_P0 :: COUNT [31:00] */
-#define BCHP_SWITCH_CORE_RxSAChanges_P0_COUNT_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_RxSAChanges_P0_COUNT_SHIFT 0
-#define BCHP_SWITCH_CORE_RxSAChanges_P0_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *RxFragments_P0 - Rx Fragment Counter
- ***************************************************************************/
-/* SWITCH_CORE :: RxFragments_P0 :: COUNT [31:00] */
-#define BCHP_SWITCH_CORE_RxFragments_P0_COUNT_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_RxFragments_P0_COUNT_SHIFT 0
-#define BCHP_SWITCH_CORE_RxFragments_P0_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *RxJumboPkt_P0 - Jumbo Packet Counter
- ***************************************************************************/
-/* SWITCH_CORE :: RxJumboPkt_P0 :: COUNT [31:00] */
-#define BCHP_SWITCH_CORE_RxJumboPkt_P0_COUNT_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_RxJumboPkt_P0_COUNT_SHIFT 0
-#define BCHP_SWITCH_CORE_RxJumboPkt_P0_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *RxSymblErr_P0 - Rx Symbol Error Counter
- ***************************************************************************/
-/* SWITCH_CORE :: RxSymblErr_P0 :: COUNT [31:00] */
-#define BCHP_SWITCH_CORE_RxSymblErr_P0_COUNT_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_RxSymblErr_P0_COUNT_SHIFT 0
-#define BCHP_SWITCH_CORE_RxSymblErr_P0_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *InRangeErrCount_P0 - InRangeErrCount Counter
- ***************************************************************************/
-/* SWITCH_CORE :: InRangeErrCount_P0 :: COUNT [31:00] */
-#define BCHP_SWITCH_CORE_InRangeErrCount_P0_COUNT_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_InRangeErrCount_P0_COUNT_SHIFT 0
-#define BCHP_SWITCH_CORE_InRangeErrCount_P0_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *OutRangeErrCount_P0 - OutRangeErrCount Counter
- ***************************************************************************/
-/* SWITCH_CORE :: OutRangeErrCount_P0 :: COUNT [31:00] */
-#define BCHP_SWITCH_CORE_OutRangeErrCount_P0_COUNT_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_OutRangeErrCount_P0_COUNT_SHIFT 0
-#define BCHP_SWITCH_CORE_OutRangeErrCount_P0_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *EEE_LPI_EVENT_P0 - EEE Low-Power Idle Event Registers
- ***************************************************************************/
-/* SWITCH_CORE :: EEE_LPI_EVENT_P0 :: COUNT [31:00] */
-#define BCHP_SWITCH_CORE_EEE_LPI_EVENT_P0_COUNT_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_EEE_LPI_EVENT_P0_COUNT_SHIFT 0
-#define BCHP_SWITCH_CORE_EEE_LPI_EVENT_P0_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *EEE_LPI_DURATION_P0 - EEE Low-Power Idle Duration Registers
- ***************************************************************************/
-/* SWITCH_CORE :: EEE_LPI_DURATION_P0 :: COUNT [31:00] */
-#define BCHP_SWITCH_CORE_EEE_LPI_DURATION_P0_COUNT_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_EEE_LPI_DURATION_P0_COUNT_SHIFT 0
-#define BCHP_SWITCH_CORE_EEE_LPI_DURATION_P0_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *RxDiscard_P0 - Rx Discard Counter
- ***************************************************************************/
-/* SWITCH_CORE :: RxDiscard_P0 :: COUNT [31:00] */
-#define BCHP_SWITCH_CORE_RxDiscard_P0_COUNT_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_RxDiscard_P0_COUNT_SHIFT 0
-#define BCHP_SWITCH_CORE_RxDiscard_P0_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *TxQPKTQ6_P0 - Tx Q6 Packet Counter
- ***************************************************************************/
-/* SWITCH_CORE :: TxQPKTQ6_P0 :: COUNT [31:00] */
-#define BCHP_SWITCH_CORE_TxQPKTQ6_P0_COUNT_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_TxQPKTQ6_P0_COUNT_SHIFT 0
-#define BCHP_SWITCH_CORE_TxQPKTQ6_P0_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *TxQPKTQ7_P0 - Tx Q7 Packet Counter
- ***************************************************************************/
-/* SWITCH_CORE :: TxQPKTQ7_P0 :: COUNT [31:00] */
-#define BCHP_SWITCH_CORE_TxQPKTQ7_P0_COUNT_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_TxQPKTQ7_P0_COUNT_SHIFT 0
-#define BCHP_SWITCH_CORE_TxQPKTQ7_P0_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *TxPkts64Octets_P0 - Tx 64 Bytes Octets Counter
- ***************************************************************************/
-/* SWITCH_CORE :: TxPkts64Octets_P0 :: COUNT [31:00] */
-#define BCHP_SWITCH_CORE_TxPkts64Octets_P0_COUNT_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_TxPkts64Octets_P0_COUNT_SHIFT 0
-#define BCHP_SWITCH_CORE_TxPkts64Octets_P0_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *TxPkts65to127Octets_P0 - Tx 65 to 127 Bytes Octets Counter
- ***************************************************************************/
-/* SWITCH_CORE :: TxPkts65to127Octets_P0 :: COUNT [31:00] */
-#define BCHP_SWITCH_CORE_TxPkts65to127Octets_P0_COUNT_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_TxPkts65to127Octets_P0_COUNT_SHIFT 0
-#define BCHP_SWITCH_CORE_TxPkts65to127Octets_P0_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *TxPkts128to255Octets_P0 - Tx 128 to 255 Bytes Octets Counter
- ***************************************************************************/
-/* SWITCH_CORE :: TxPkts128to255Octets_P0 :: COUNT [31:00] */
-#define BCHP_SWITCH_CORE_TxPkts128to255Octets_P0_COUNT_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_TxPkts128to255Octets_P0_COUNT_SHIFT 0
-#define BCHP_SWITCH_CORE_TxPkts128to255Octets_P0_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *TxPkts256to511Octets_P0 - Tx 256 to 511 Bytes Octets Counter
- ***************************************************************************/
-/* SWITCH_CORE :: TxPkts256to511Octets_P0 :: COUNT [31:00] */
-#define BCHP_SWITCH_CORE_TxPkts256to511Octets_P0_COUNT_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_TxPkts256to511Octets_P0_COUNT_SHIFT 0
-#define BCHP_SWITCH_CORE_TxPkts256to511Octets_P0_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *TxPkts512to1023Octets_P0 - Tx 512 to 1023 Bytes Octets Counter
- ***************************************************************************/
-/* SWITCH_CORE :: TxPkts512to1023Octets_P0 :: COUNT [31:00] */
-#define BCHP_SWITCH_CORE_TxPkts512to1023Octets_P0_COUNT_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_TxPkts512to1023Octets_P0_COUNT_SHIFT 0
-#define BCHP_SWITCH_CORE_TxPkts512to1023Octets_P0_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *TxPkts1024toMaxPktOctets_P0 - Tx 1024 to MaxPkt Bytes Octets Counter
- ***************************************************************************/
-/* SWITCH_CORE :: TxPkts1024toMaxPktOctets_P0 :: COUNT [31:00] */
-#define BCHP_SWITCH_CORE_TxPkts1024toMaxPktOctets_P0_COUNT_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_TxPkts1024toMaxPktOctets_P0_COUNT_SHIFT 0
-#define BCHP_SWITCH_CORE_TxPkts1024toMaxPktOctets_P0_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *TxOctets_P1 - Tx Octets
- ***************************************************************************/
-/* SWITCH_CORE :: TxOctets_P1 :: COUNT [63:00] */
-#define BCHP_SWITCH_CORE_TxOctets_P1_COUNT_MASK 0x00000000ffffffff
-#define BCHP_SWITCH_CORE_TxOctets_P1_COUNT_SHIFT 0
-#define BCHP_SWITCH_CORE_TxOctets_P1_COUNT_DEFAULT 0x0000000000000000
-
-/***************************************************************************
- *TxDropPkts_P1 - Tx Drop Packet Counter
- ***************************************************************************/
-/* SWITCH_CORE :: TxDropPkts_P1 :: COUNT [31:00] */
-#define BCHP_SWITCH_CORE_TxDropPkts_P1_COUNT_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_TxDropPkts_P1_COUNT_SHIFT 0
-#define BCHP_SWITCH_CORE_TxDropPkts_P1_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *TxQPKTQ0_P1 - Tx Q0 Packet Counter
- ***************************************************************************/
-/* SWITCH_CORE :: TxQPKTQ0_P1 :: COUNT [31:00] */
-#define BCHP_SWITCH_CORE_TxQPKTQ0_P1_COUNT_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_TxQPKTQ0_P1_COUNT_SHIFT 0
-#define BCHP_SWITCH_CORE_TxQPKTQ0_P1_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *TxBroadcastPkts_P1 - Tx Broadcast Packet Counter
- ***************************************************************************/
-/* SWITCH_CORE :: TxBroadcastPkts_P1 :: COUNT [31:00] */
-#define BCHP_SWITCH_CORE_TxBroadcastPkts_P1_COUNT_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_TxBroadcastPkts_P1_COUNT_SHIFT 0
-#define BCHP_SWITCH_CORE_TxBroadcastPkts_P1_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *TxMulticastPkts_P1 - Tx Multicast Packet Counter
- ***************************************************************************/
-/* SWITCH_CORE :: TxMulticastPkts_P1 :: COUNT [31:00] */
-#define BCHP_SWITCH_CORE_TxMulticastPkts_P1_COUNT_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_TxMulticastPkts_P1_COUNT_SHIFT 0
-#define BCHP_SWITCH_CORE_TxMulticastPkts_P1_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *TxUnicastPkts_P1 - Tx Unicast Packet Counter
- ***************************************************************************/
-/* SWITCH_CORE :: TxUnicastPkts_P1 :: COUNT [31:00] */
-#define BCHP_SWITCH_CORE_TxUnicastPkts_P1_COUNT_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_TxUnicastPkts_P1_COUNT_SHIFT 0
-#define BCHP_SWITCH_CORE_TxUnicastPkts_P1_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *TxCollisions_P1 - Tx Collision Counter
- ***************************************************************************/
-/* SWITCH_CORE :: TxCollisions_P1 :: COUNT [31:00] */
-#define BCHP_SWITCH_CORE_TxCollisions_P1_COUNT_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_TxCollisions_P1_COUNT_SHIFT 0
-#define BCHP_SWITCH_CORE_TxCollisions_P1_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *TxSingleCollision_P1 - Tx Single Collision Counter
- ***************************************************************************/
-/* SWITCH_CORE :: TxSingleCollision_P1 :: COUNT [31:00] */
-#define BCHP_SWITCH_CORE_TxSingleCollision_P1_COUNT_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_TxSingleCollision_P1_COUNT_SHIFT 0
-#define BCHP_SWITCH_CORE_TxSingleCollision_P1_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *TxMultipleCollision_P1 - Tx Multiple collsion Counter
- ***************************************************************************/
-/* SWITCH_CORE :: TxMultipleCollision_P1 :: COUNT [31:00] */
-#define BCHP_SWITCH_CORE_TxMultipleCollision_P1_COUNT_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_TxMultipleCollision_P1_COUNT_SHIFT 0
-#define BCHP_SWITCH_CORE_TxMultipleCollision_P1_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *TxDeferredTransmit_P1 - Tx Deferred Transmit Counter
- ***************************************************************************/
-/* SWITCH_CORE :: TxDeferredTransmit_P1 :: COUNT [31:00] */
-#define BCHP_SWITCH_CORE_TxDeferredTransmit_P1_COUNT_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_TxDeferredTransmit_P1_COUNT_SHIFT 0
-#define BCHP_SWITCH_CORE_TxDeferredTransmit_P1_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *TxLateCollision_P1 - Tx Late Collision Counter
- ***************************************************************************/
-/* SWITCH_CORE :: TxLateCollision_P1 :: COUNT [31:00] */
-#define BCHP_SWITCH_CORE_TxLateCollision_P1_COUNT_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_TxLateCollision_P1_COUNT_SHIFT 0
-#define BCHP_SWITCH_CORE_TxLateCollision_P1_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *TxExcessiveCollision_P1 - Tx Excessive Collision Counter
- ***************************************************************************/
-/* SWITCH_CORE :: TxExcessiveCollision_P1 :: COUNT [31:00] */
-#define BCHP_SWITCH_CORE_TxExcessiveCollision_P1_COUNT_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_TxExcessiveCollision_P1_COUNT_SHIFT 0
-#define BCHP_SWITCH_CORE_TxExcessiveCollision_P1_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *TxFrameInDisc_P1 - Tx Fram IN Disc Counter
- ***************************************************************************/
-/* SWITCH_CORE :: TxFrameInDisc_P1 :: COUNT [31:00] */
-#define BCHP_SWITCH_CORE_TxFrameInDisc_P1_COUNT_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_TxFrameInDisc_P1_COUNT_SHIFT 0
-#define BCHP_SWITCH_CORE_TxFrameInDisc_P1_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *TxPausePkts_P1 - Tx Pause Packet Counter
- ***************************************************************************/
-/* SWITCH_CORE :: TxPausePkts_P1 :: COUNT [31:00] */
-#define BCHP_SWITCH_CORE_TxPausePkts_P1_COUNT_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_TxPausePkts_P1_COUNT_SHIFT 0
-#define BCHP_SWITCH_CORE_TxPausePkts_P1_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *TxQPKTQ1_P1 - Tx Q1 Packet Counter
- ***************************************************************************/
-/* SWITCH_CORE :: TxQPKTQ1_P1 :: COUNT [31:00] */
-#define BCHP_SWITCH_CORE_TxQPKTQ1_P1_COUNT_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_TxQPKTQ1_P1_COUNT_SHIFT 0
-#define BCHP_SWITCH_CORE_TxQPKTQ1_P1_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *TxQPKTQ2_P1 - Tx Q2 Packet Counter
- ***************************************************************************/
-/* SWITCH_CORE :: TxQPKTQ2_P1 :: COUNT [31:00] */
-#define BCHP_SWITCH_CORE_TxQPKTQ2_P1_COUNT_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_TxQPKTQ2_P1_COUNT_SHIFT 0
-#define BCHP_SWITCH_CORE_TxQPKTQ2_P1_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *TxQPKTQ3_P1 - Tx Q3 Packet Counter
- ***************************************************************************/
-/* SWITCH_CORE :: TxQPKTQ3_P1 :: COUNT [31:00] */
-#define BCHP_SWITCH_CORE_TxQPKTQ3_P1_COUNT_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_TxQPKTQ3_P1_COUNT_SHIFT 0
-#define BCHP_SWITCH_CORE_TxQPKTQ3_P1_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *TxQPKTQ4_P1 - Tx Q4 Packet Counter
- ***************************************************************************/
-/* SWITCH_CORE :: TxQPKTQ4_P1 :: COUNT [31:00] */
-#define BCHP_SWITCH_CORE_TxQPKTQ4_P1_COUNT_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_TxQPKTQ4_P1_COUNT_SHIFT 0
-#define BCHP_SWITCH_CORE_TxQPKTQ4_P1_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *TxQPKTQ5_P1 - Tx Q5 Packet Counter
- ***************************************************************************/
-/* SWITCH_CORE :: TxQPKTQ5_P1 :: COUNT [31:00] */
-#define BCHP_SWITCH_CORE_TxQPKTQ5_P1_COUNT_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_TxQPKTQ5_P1_COUNT_SHIFT 0
-#define BCHP_SWITCH_CORE_TxQPKTQ5_P1_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *RxOctets_P1 - Rx Packet Octets Counter
- ***************************************************************************/
-/* SWITCH_CORE :: RxOctets_P1 :: COUNT [63:00] */
-#define BCHP_SWITCH_CORE_RxOctets_P1_COUNT_MASK 0x00000000ffffffff
-#define BCHP_SWITCH_CORE_RxOctets_P1_COUNT_SHIFT 0
-#define BCHP_SWITCH_CORE_RxOctets_P1_COUNT_DEFAULT 0x0000000000000000
-
-/***************************************************************************
- *RxUndersizePkts_P1 - Rx Under Size Packet Octets Counter
- ***************************************************************************/
-/* SWITCH_CORE :: RxUndersizePkts_P1 :: COUNT [31:00] */
-#define BCHP_SWITCH_CORE_RxUndersizePkts_P1_COUNT_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_RxUndersizePkts_P1_COUNT_SHIFT 0
-#define BCHP_SWITCH_CORE_RxUndersizePkts_P1_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *RxPausePkts_P1 - Rx Pause Packet Counter
- ***************************************************************************/
-/* SWITCH_CORE :: RxPausePkts_P1 :: COUNT [31:00] */
-#define BCHP_SWITCH_CORE_RxPausePkts_P1_COUNT_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_RxPausePkts_P1_COUNT_SHIFT 0
-#define BCHP_SWITCH_CORE_RxPausePkts_P1_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *RxPkts64Octets_P1 - Rx 64 Bytes Octets Counter
- ***************************************************************************/
-/* SWITCH_CORE :: RxPkts64Octets_P1 :: COUNT [31:00] */
-#define BCHP_SWITCH_CORE_RxPkts64Octets_P1_COUNT_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_RxPkts64Octets_P1_COUNT_SHIFT 0
-#define BCHP_SWITCH_CORE_RxPkts64Octets_P1_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *RxPkts65to127Octets_P1 - Rx 65 to 127 Bytes Octets Counter
- ***************************************************************************/
-/* SWITCH_CORE :: RxPkts65to127Octets_P1 :: COUNT [31:00] */
-#define BCHP_SWITCH_CORE_RxPkts65to127Octets_P1_COUNT_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_RxPkts65to127Octets_P1_COUNT_SHIFT 0
-#define BCHP_SWITCH_CORE_RxPkts65to127Octets_P1_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *RxPkts128to255Octets_P1 - Rx 128 to 255 Bytes Octets Counter
- ***************************************************************************/
-/* SWITCH_CORE :: RxPkts128to255Octets_P1 :: COUNT [31:00] */
-#define BCHP_SWITCH_CORE_RxPkts128to255Octets_P1_COUNT_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_RxPkts128to255Octets_P1_COUNT_SHIFT 0
-#define BCHP_SWITCH_CORE_RxPkts128to255Octets_P1_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *RxPkts256to511Octets_P1 - Rx 256 to 511 Bytes Octets Counter
- ***************************************************************************/
-/* SWITCH_CORE :: RxPkts256to511Octets_P1 :: COUNT [31:00] */
-#define BCHP_SWITCH_CORE_RxPkts256to511Octets_P1_COUNT_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_RxPkts256to511Octets_P1_COUNT_SHIFT 0
-#define BCHP_SWITCH_CORE_RxPkts256to511Octets_P1_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *RxPkts512to1023Octets_P1 - Rx 512 to 1023 Bytes Octets Counter
- ***************************************************************************/
-/* SWITCH_CORE :: RxPkts512to1023Octets_P1 :: COUNT [31:00] */
-#define BCHP_SWITCH_CORE_RxPkts512to1023Octets_P1_COUNT_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_RxPkts512to1023Octets_P1_COUNT_SHIFT 0
-#define BCHP_SWITCH_CORE_RxPkts512to1023Octets_P1_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *RxPkts1024toMaxPktOctets_P1 - Rx 1024 to MaxPkt Bytes Octets Counter
- ***************************************************************************/
-/* SWITCH_CORE :: RxPkts1024toMaxPktOctets_P1 :: COUNT [31:00] */
-#define BCHP_SWITCH_CORE_RxPkts1024toMaxPktOctets_P1_COUNT_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_RxPkts1024toMaxPktOctets_P1_COUNT_SHIFT 0
-#define BCHP_SWITCH_CORE_RxPkts1024toMaxPktOctets_P1_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *RxOversizePkts_P1 - Rx Over Size Packet Counter
- ***************************************************************************/
-/* SWITCH_CORE :: RxOversizePkts_P1 :: COUNT [31:00] */
-#define BCHP_SWITCH_CORE_RxOversizePkts_P1_COUNT_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_RxOversizePkts_P1_COUNT_SHIFT 0
-#define BCHP_SWITCH_CORE_RxOversizePkts_P1_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *RxJabbers_P1 - Rx Jabber Packet Counter
- ***************************************************************************/
-/* SWITCH_CORE :: RxJabbers_P1 :: COUNT [31:00] */
-#define BCHP_SWITCH_CORE_RxJabbers_P1_COUNT_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_RxJabbers_P1_COUNT_SHIFT 0
-#define BCHP_SWITCH_CORE_RxJabbers_P1_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *RxAlignmentErrors_P1 - Rx Alignment Error Counter
- ***************************************************************************/
-/* SWITCH_CORE :: RxAlignmentErrors_P1 :: COUNT [31:00] */
-#define BCHP_SWITCH_CORE_RxAlignmentErrors_P1_COUNT_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_RxAlignmentErrors_P1_COUNT_SHIFT 0
-#define BCHP_SWITCH_CORE_RxAlignmentErrors_P1_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *RxFCSErrors_P1 - Rx FCS Error Counter
- ***************************************************************************/
-/* SWITCH_CORE :: RxFCSErrors_P1 :: COUNT [31:00] */
-#define BCHP_SWITCH_CORE_RxFCSErrors_P1_COUNT_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_RxFCSErrors_P1_COUNT_SHIFT 0
-#define BCHP_SWITCH_CORE_RxFCSErrors_P1_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *RxGoodOctets_P1 - Rx Good Packet Octet Counter
- ***************************************************************************/
-/* SWITCH_CORE :: RxGoodOctets_P1 :: COUNT [63:00] */
-#define BCHP_SWITCH_CORE_RxGoodOctets_P1_COUNT_MASK 0x00000000ffffffff
-#define BCHP_SWITCH_CORE_RxGoodOctets_P1_COUNT_SHIFT 0
-#define BCHP_SWITCH_CORE_RxGoodOctets_P1_COUNT_DEFAULT 0x0000000000000000
-
-/***************************************************************************
- *RxDropPkts_P1 - Rx Drop Packet Counter
- ***************************************************************************/
-/* SWITCH_CORE :: RxDropPkts_P1 :: COUNT [31:00] */
-#define BCHP_SWITCH_CORE_RxDropPkts_P1_COUNT_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_RxDropPkts_P1_COUNT_SHIFT 0
-#define BCHP_SWITCH_CORE_RxDropPkts_P1_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *RxUnicastPkts_P1 - Rx Unicast Packet Counter
- ***************************************************************************/
-/* SWITCH_CORE :: RxUnicastPkts_P1 :: COUNT [31:00] */
-#define BCHP_SWITCH_CORE_RxUnicastPkts_P1_COUNT_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_RxUnicastPkts_P1_COUNT_SHIFT 0
-#define BCHP_SWITCH_CORE_RxUnicastPkts_P1_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *RxMulticastPkts_P1 - Rx Multicast Packet Counter
- ***************************************************************************/
-/* SWITCH_CORE :: RxMulticastPkts_P1 :: COUNT [31:00] */
-#define BCHP_SWITCH_CORE_RxMulticastPkts_P1_COUNT_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_RxMulticastPkts_P1_COUNT_SHIFT 0
-#define BCHP_SWITCH_CORE_RxMulticastPkts_P1_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *RxBroadcastPkts_P1 - Rx Broadcast Packet Counter
- ***************************************************************************/
-/* SWITCH_CORE :: RxBroadcastPkts_P1 :: COUNT [31:00] */
-#define BCHP_SWITCH_CORE_RxBroadcastPkts_P1_COUNT_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_RxBroadcastPkts_P1_COUNT_SHIFT 0
-#define BCHP_SWITCH_CORE_RxBroadcastPkts_P1_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *RxSAChanges_P1 - Rx SA Change Counter
- ***************************************************************************/
-/* SWITCH_CORE :: RxSAChanges_P1 :: COUNT [31:00] */
-#define BCHP_SWITCH_CORE_RxSAChanges_P1_COUNT_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_RxSAChanges_P1_COUNT_SHIFT 0
-#define BCHP_SWITCH_CORE_RxSAChanges_P1_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *RxFragments_P1 - Rx Fragment Counter
- ***************************************************************************/
-/* SWITCH_CORE :: RxFragments_P1 :: COUNT [31:00] */
-#define BCHP_SWITCH_CORE_RxFragments_P1_COUNT_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_RxFragments_P1_COUNT_SHIFT 0
-#define BCHP_SWITCH_CORE_RxFragments_P1_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *RxJumboPkt_P1 - Jumbo Packet Counter
- ***************************************************************************/
-/* SWITCH_CORE :: RxJumboPkt_P1 :: COUNT [31:00] */
-#define BCHP_SWITCH_CORE_RxJumboPkt_P1_COUNT_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_RxJumboPkt_P1_COUNT_SHIFT 0
-#define BCHP_SWITCH_CORE_RxJumboPkt_P1_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *RxSymblErr_P1 - Rx Symbol Error Counter
- ***************************************************************************/
-/* SWITCH_CORE :: RxSymblErr_P1 :: COUNT [31:00] */
-#define BCHP_SWITCH_CORE_RxSymblErr_P1_COUNT_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_RxSymblErr_P1_COUNT_SHIFT 0
-#define BCHP_SWITCH_CORE_RxSymblErr_P1_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *InRangeErrCount_P1 - InRangeErrCount Counter
- ***************************************************************************/
-/* SWITCH_CORE :: InRangeErrCount_P1 :: COUNT [31:00] */
-#define BCHP_SWITCH_CORE_InRangeErrCount_P1_COUNT_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_InRangeErrCount_P1_COUNT_SHIFT 0
-#define BCHP_SWITCH_CORE_InRangeErrCount_P1_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *OutRangeErrCount_P1 - OutRangeErrCount Counter
- ***************************************************************************/
-/* SWITCH_CORE :: OutRangeErrCount_P1 :: COUNT [31:00] */
-#define BCHP_SWITCH_CORE_OutRangeErrCount_P1_COUNT_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_OutRangeErrCount_P1_COUNT_SHIFT 0
-#define BCHP_SWITCH_CORE_OutRangeErrCount_P1_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *EEE_LPI_EVENT_P1 - EEE Low-Power Idle Event Registers
- ***************************************************************************/
-/* SWITCH_CORE :: EEE_LPI_EVENT_P1 :: COUNT [31:00] */
-#define BCHP_SWITCH_CORE_EEE_LPI_EVENT_P1_COUNT_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_EEE_LPI_EVENT_P1_COUNT_SHIFT 0
-#define BCHP_SWITCH_CORE_EEE_LPI_EVENT_P1_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *EEE_LPI_DURATION_P1 - EEE Low-Power Idle Duration Registers
- ***************************************************************************/
-/* SWITCH_CORE :: EEE_LPI_DURATION_P1 :: COUNT [31:00] */
-#define BCHP_SWITCH_CORE_EEE_LPI_DURATION_P1_COUNT_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_EEE_LPI_DURATION_P1_COUNT_SHIFT 0
-#define BCHP_SWITCH_CORE_EEE_LPI_DURATION_P1_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *RxDiscard_P1 - Rx Discard Counter
- ***************************************************************************/
-/* SWITCH_CORE :: RxDiscard_P1 :: COUNT [31:00] */
-#define BCHP_SWITCH_CORE_RxDiscard_P1_COUNT_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_RxDiscard_P1_COUNT_SHIFT 0
-#define BCHP_SWITCH_CORE_RxDiscard_P1_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *TxQPKTQ6_P1 - Tx Q6 Packet Counter
- ***************************************************************************/
-/* SWITCH_CORE :: TxQPKTQ6_P1 :: COUNT [31:00] */
-#define BCHP_SWITCH_CORE_TxQPKTQ6_P1_COUNT_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_TxQPKTQ6_P1_COUNT_SHIFT 0
-#define BCHP_SWITCH_CORE_TxQPKTQ6_P1_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *TxQPKTQ7_P1 - Tx Q7 Packet Counter
- ***************************************************************************/
-/* SWITCH_CORE :: TxQPKTQ7_P1 :: COUNT [31:00] */
-#define BCHP_SWITCH_CORE_TxQPKTQ7_P1_COUNT_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_TxQPKTQ7_P1_COUNT_SHIFT 0
-#define BCHP_SWITCH_CORE_TxQPKTQ7_P1_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *TxPkts64Octets_P1 - Tx 64 Bytes Octets Counter
- ***************************************************************************/
-/* SWITCH_CORE :: TxPkts64Octets_P1 :: COUNT [31:00] */
-#define BCHP_SWITCH_CORE_TxPkts64Octets_P1_COUNT_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_TxPkts64Octets_P1_COUNT_SHIFT 0
-#define BCHP_SWITCH_CORE_TxPkts64Octets_P1_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *TxPkts65to127Octets_P1 - Tx 65 to 127 Bytes Octets Counter
- ***************************************************************************/
-/* SWITCH_CORE :: TxPkts65to127Octets_P1 :: COUNT [31:00] */
-#define BCHP_SWITCH_CORE_TxPkts65to127Octets_P1_COUNT_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_TxPkts65to127Octets_P1_COUNT_SHIFT 0
-#define BCHP_SWITCH_CORE_TxPkts65to127Octets_P1_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *TxPkts128to255Octets_P1 - Tx 128 to 255 Bytes Octets Counter
- ***************************************************************************/
-/* SWITCH_CORE :: TxPkts128to255Octets_P1 :: COUNT [31:00] */
-#define BCHP_SWITCH_CORE_TxPkts128to255Octets_P1_COUNT_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_TxPkts128to255Octets_P1_COUNT_SHIFT 0
-#define BCHP_SWITCH_CORE_TxPkts128to255Octets_P1_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *TxPkts256to511Octets_P1 - Tx 256 to 511 Bytes Octets Counter
- ***************************************************************************/
-/* SWITCH_CORE :: TxPkts256to511Octets_P1 :: COUNT [31:00] */
-#define BCHP_SWITCH_CORE_TxPkts256to511Octets_P1_COUNT_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_TxPkts256to511Octets_P1_COUNT_SHIFT 0
-#define BCHP_SWITCH_CORE_TxPkts256to511Octets_P1_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *TxPkts512to1023Octets_P1 - Tx 512 to 1023 Bytes Octets Counter
- ***************************************************************************/
-/* SWITCH_CORE :: TxPkts512to1023Octets_P1 :: COUNT [31:00] */
-#define BCHP_SWITCH_CORE_TxPkts512to1023Octets_P1_COUNT_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_TxPkts512to1023Octets_P1_COUNT_SHIFT 0
-#define BCHP_SWITCH_CORE_TxPkts512to1023Octets_P1_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *TxPkts1024toMaxPktOctets_P1 - Tx 1024 to MaxPkt Bytes Octets Counter
- ***************************************************************************/
-/* SWITCH_CORE :: TxPkts1024toMaxPktOctets_P1 :: COUNT [31:00] */
-#define BCHP_SWITCH_CORE_TxPkts1024toMaxPktOctets_P1_COUNT_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_TxPkts1024toMaxPktOctets_P1_COUNT_SHIFT 0
-#define BCHP_SWITCH_CORE_TxPkts1024toMaxPktOctets_P1_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *TxOctets_P2 - Tx Octets
- ***************************************************************************/
-/* SWITCH_CORE :: TxOctets_P2 :: COUNT [63:00] */
-#define BCHP_SWITCH_CORE_TxOctets_P2_COUNT_MASK 0x00000000ffffffff
-#define BCHP_SWITCH_CORE_TxOctets_P2_COUNT_SHIFT 0
-#define BCHP_SWITCH_CORE_TxOctets_P2_COUNT_DEFAULT 0x0000000000000000
-
-/***************************************************************************
- *TxDropPkts_P2 - Tx Drop Packet Counter
- ***************************************************************************/
-/* SWITCH_CORE :: TxDropPkts_P2 :: COUNT [31:00] */
-#define BCHP_SWITCH_CORE_TxDropPkts_P2_COUNT_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_TxDropPkts_P2_COUNT_SHIFT 0
-#define BCHP_SWITCH_CORE_TxDropPkts_P2_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *TxQPKTQ0_P2 - Tx Q0 Packet Counter
- ***************************************************************************/
-/* SWITCH_CORE :: TxQPKTQ0_P2 :: COUNT [31:00] */
-#define BCHP_SWITCH_CORE_TxQPKTQ0_P2_COUNT_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_TxQPKTQ0_P2_COUNT_SHIFT 0
-#define BCHP_SWITCH_CORE_TxQPKTQ0_P2_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *TxBroadcastPkts_P2 - Tx Broadcast Packet Counter
- ***************************************************************************/
-/* SWITCH_CORE :: TxBroadcastPkts_P2 :: COUNT [31:00] */
-#define BCHP_SWITCH_CORE_TxBroadcastPkts_P2_COUNT_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_TxBroadcastPkts_P2_COUNT_SHIFT 0
-#define BCHP_SWITCH_CORE_TxBroadcastPkts_P2_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *TxMulticastPkts_P2 - Tx Multicast Packet Counter
- ***************************************************************************/
-/* SWITCH_CORE :: TxMulticastPkts_P2 :: COUNT [31:00] */
-#define BCHP_SWITCH_CORE_TxMulticastPkts_P2_COUNT_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_TxMulticastPkts_P2_COUNT_SHIFT 0
-#define BCHP_SWITCH_CORE_TxMulticastPkts_P2_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *TxUnicastPkts_P2 - Tx Unicast Packet Counter
- ***************************************************************************/
-/* SWITCH_CORE :: TxUnicastPkts_P2 :: COUNT [31:00] */
-#define BCHP_SWITCH_CORE_TxUnicastPkts_P2_COUNT_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_TxUnicastPkts_P2_COUNT_SHIFT 0
-#define BCHP_SWITCH_CORE_TxUnicastPkts_P2_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *TxCollisions_P2 - Tx Collision Counter
- ***************************************************************************/
-/* SWITCH_CORE :: TxCollisions_P2 :: COUNT [31:00] */
-#define BCHP_SWITCH_CORE_TxCollisions_P2_COUNT_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_TxCollisions_P2_COUNT_SHIFT 0
-#define BCHP_SWITCH_CORE_TxCollisions_P2_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *TxSingleCollision_P2 - Tx Single Collision Counter
- ***************************************************************************/
-/* SWITCH_CORE :: TxSingleCollision_P2 :: COUNT [31:00] */
-#define BCHP_SWITCH_CORE_TxSingleCollision_P2_COUNT_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_TxSingleCollision_P2_COUNT_SHIFT 0
-#define BCHP_SWITCH_CORE_TxSingleCollision_P2_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *TxMultipleCollision_P2 - Tx Multiple collsion Counter
- ***************************************************************************/
-/* SWITCH_CORE :: TxMultipleCollision_P2 :: COUNT [31:00] */
-#define BCHP_SWITCH_CORE_TxMultipleCollision_P2_COUNT_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_TxMultipleCollision_P2_COUNT_SHIFT 0
-#define BCHP_SWITCH_CORE_TxMultipleCollision_P2_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *TxDeferredTransmit_P2 - Tx Deferred Transmit Counter
- ***************************************************************************/
-/* SWITCH_CORE :: TxDeferredTransmit_P2 :: COUNT [31:00] */
-#define BCHP_SWITCH_CORE_TxDeferredTransmit_P2_COUNT_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_TxDeferredTransmit_P2_COUNT_SHIFT 0
-#define BCHP_SWITCH_CORE_TxDeferredTransmit_P2_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *TxLateCollision_P2 - Tx Late Collision Counter
- ***************************************************************************/
-/* SWITCH_CORE :: TxLateCollision_P2 :: COUNT [31:00] */
-#define BCHP_SWITCH_CORE_TxLateCollision_P2_COUNT_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_TxLateCollision_P2_COUNT_SHIFT 0
-#define BCHP_SWITCH_CORE_TxLateCollision_P2_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *TxExcessiveCollision_P2 - Tx Excessive Collision Counter
- ***************************************************************************/
-/* SWITCH_CORE :: TxExcessiveCollision_P2 :: COUNT [31:00] */
-#define BCHP_SWITCH_CORE_TxExcessiveCollision_P2_COUNT_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_TxExcessiveCollision_P2_COUNT_SHIFT 0
-#define BCHP_SWITCH_CORE_TxExcessiveCollision_P2_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *TxFrameInDisc_P2 - Tx Fram IN Disc Counter
- ***************************************************************************/
-/* SWITCH_CORE :: TxFrameInDisc_P2 :: COUNT [31:00] */
-#define BCHP_SWITCH_CORE_TxFrameInDisc_P2_COUNT_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_TxFrameInDisc_P2_COUNT_SHIFT 0
-#define BCHP_SWITCH_CORE_TxFrameInDisc_P2_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *TxPausePkts_P2 - Tx Pause Packet Counter
- ***************************************************************************/
-/* SWITCH_CORE :: TxPausePkts_P2 :: COUNT [31:00] */
-#define BCHP_SWITCH_CORE_TxPausePkts_P2_COUNT_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_TxPausePkts_P2_COUNT_SHIFT 0
-#define BCHP_SWITCH_CORE_TxPausePkts_P2_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *TxQPKTQ1_P2 - Tx Q1 Packet Counter
- ***************************************************************************/
-/* SWITCH_CORE :: TxQPKTQ1_P2 :: COUNT [31:00] */
-#define BCHP_SWITCH_CORE_TxQPKTQ1_P2_COUNT_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_TxQPKTQ1_P2_COUNT_SHIFT 0
-#define BCHP_SWITCH_CORE_TxQPKTQ1_P2_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *TxQPKTQ2_P2 - Tx Q2 Packet Counter
- ***************************************************************************/
-/* SWITCH_CORE :: TxQPKTQ2_P2 :: COUNT [31:00] */
-#define BCHP_SWITCH_CORE_TxQPKTQ2_P2_COUNT_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_TxQPKTQ2_P2_COUNT_SHIFT 0
-#define BCHP_SWITCH_CORE_TxQPKTQ2_P2_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *TxQPKTQ3_P2 - Tx Q3 Packet Counter
- ***************************************************************************/
-/* SWITCH_CORE :: TxQPKTQ3_P2 :: COUNT [31:00] */
-#define BCHP_SWITCH_CORE_TxQPKTQ3_P2_COUNT_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_TxQPKTQ3_P2_COUNT_SHIFT 0
-#define BCHP_SWITCH_CORE_TxQPKTQ3_P2_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *TxQPKTQ4_P2 - Tx Q4 Packet Counter
- ***************************************************************************/
-/* SWITCH_CORE :: TxQPKTQ4_P2 :: COUNT [31:00] */
-#define BCHP_SWITCH_CORE_TxQPKTQ4_P2_COUNT_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_TxQPKTQ4_P2_COUNT_SHIFT 0
-#define BCHP_SWITCH_CORE_TxQPKTQ4_P2_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *TxQPKTQ5_P2 - Tx Q5 Packet Counter
- ***************************************************************************/
-/* SWITCH_CORE :: TxQPKTQ5_P2 :: COUNT [31:00] */
-#define BCHP_SWITCH_CORE_TxQPKTQ5_P2_COUNT_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_TxQPKTQ5_P2_COUNT_SHIFT 0
-#define BCHP_SWITCH_CORE_TxQPKTQ5_P2_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *RxOctets_P2 - Rx Packet Octets Counter
- ***************************************************************************/
-/* SWITCH_CORE :: RxOctets_P2 :: COUNT [63:00] */
-#define BCHP_SWITCH_CORE_RxOctets_P2_COUNT_MASK 0x00000000ffffffff
-#define BCHP_SWITCH_CORE_RxOctets_P2_COUNT_SHIFT 0
-#define BCHP_SWITCH_CORE_RxOctets_P2_COUNT_DEFAULT 0x0000000000000000
-
-/***************************************************************************
- *RxUndersizePkts_P2 - Rx Under Size Packet Octets Counter
- ***************************************************************************/
-/* SWITCH_CORE :: RxUndersizePkts_P2 :: COUNT [31:00] */
-#define BCHP_SWITCH_CORE_RxUndersizePkts_P2_COUNT_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_RxUndersizePkts_P2_COUNT_SHIFT 0
-#define BCHP_SWITCH_CORE_RxUndersizePkts_P2_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *RxPausePkts_P2 - Rx Pause Packet Counter
- ***************************************************************************/
-/* SWITCH_CORE :: RxPausePkts_P2 :: COUNT [31:00] */
-#define BCHP_SWITCH_CORE_RxPausePkts_P2_COUNT_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_RxPausePkts_P2_COUNT_SHIFT 0
-#define BCHP_SWITCH_CORE_RxPausePkts_P2_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *RxPkts64Octets_P2 - Rx 64 Bytes Octets Counter
- ***************************************************************************/
-/* SWITCH_CORE :: RxPkts64Octets_P2 :: COUNT [31:00] */
-#define BCHP_SWITCH_CORE_RxPkts64Octets_P2_COUNT_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_RxPkts64Octets_P2_COUNT_SHIFT 0
-#define BCHP_SWITCH_CORE_RxPkts64Octets_P2_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *RxPkts65to127Octets_P2 - Rx 65 to 127 Bytes Octets Counter
- ***************************************************************************/
-/* SWITCH_CORE :: RxPkts65to127Octets_P2 :: COUNT [31:00] */
-#define BCHP_SWITCH_CORE_RxPkts65to127Octets_P2_COUNT_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_RxPkts65to127Octets_P2_COUNT_SHIFT 0
-#define BCHP_SWITCH_CORE_RxPkts65to127Octets_P2_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *RxPkts128to255Octets_P2 - Rx 128 to 255 Bytes Octets Counter
- ***************************************************************************/
-/* SWITCH_CORE :: RxPkts128to255Octets_P2 :: COUNT [31:00] */
-#define BCHP_SWITCH_CORE_RxPkts128to255Octets_P2_COUNT_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_RxPkts128to255Octets_P2_COUNT_SHIFT 0
-#define BCHP_SWITCH_CORE_RxPkts128to255Octets_P2_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *RxPkts256to511Octets_P2 - Rx 256 to 511 Bytes Octets Counter
- ***************************************************************************/
-/* SWITCH_CORE :: RxPkts256to511Octets_P2 :: COUNT [31:00] */
-#define BCHP_SWITCH_CORE_RxPkts256to511Octets_P2_COUNT_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_RxPkts256to511Octets_P2_COUNT_SHIFT 0
-#define BCHP_SWITCH_CORE_RxPkts256to511Octets_P2_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *RxPkts512to1023Octets_P2 - Rx 512 to 1023 Bytes Octets Counter
- ***************************************************************************/
-/* SWITCH_CORE :: RxPkts512to1023Octets_P2 :: COUNT [31:00] */
-#define BCHP_SWITCH_CORE_RxPkts512to1023Octets_P2_COUNT_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_RxPkts512to1023Octets_P2_COUNT_SHIFT 0
-#define BCHP_SWITCH_CORE_RxPkts512to1023Octets_P2_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *RxPkts1024toMaxPktOctets_P2 - Rx 1024 to MaxPkt Bytes Octets Counter
- ***************************************************************************/
-/* SWITCH_CORE :: RxPkts1024toMaxPktOctets_P2 :: COUNT [31:00] */
-#define BCHP_SWITCH_CORE_RxPkts1024toMaxPktOctets_P2_COUNT_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_RxPkts1024toMaxPktOctets_P2_COUNT_SHIFT 0
-#define BCHP_SWITCH_CORE_RxPkts1024toMaxPktOctets_P2_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *RxOversizePkts_P2 - Rx Over Size Packet Counter
- ***************************************************************************/
-/* SWITCH_CORE :: RxOversizePkts_P2 :: COUNT [31:00] */
-#define BCHP_SWITCH_CORE_RxOversizePkts_P2_COUNT_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_RxOversizePkts_P2_COUNT_SHIFT 0
-#define BCHP_SWITCH_CORE_RxOversizePkts_P2_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *RxJabbers_P2 - Rx Jabber Packet Counter
- ***************************************************************************/
-/* SWITCH_CORE :: RxJabbers_P2 :: COUNT [31:00] */
-#define BCHP_SWITCH_CORE_RxJabbers_P2_COUNT_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_RxJabbers_P2_COUNT_SHIFT 0
-#define BCHP_SWITCH_CORE_RxJabbers_P2_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *RxAlignmentErrors_P2 - Rx Alignment Error Counter
- ***************************************************************************/
-/* SWITCH_CORE :: RxAlignmentErrors_P2 :: COUNT [31:00] */
-#define BCHP_SWITCH_CORE_RxAlignmentErrors_P2_COUNT_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_RxAlignmentErrors_P2_COUNT_SHIFT 0
-#define BCHP_SWITCH_CORE_RxAlignmentErrors_P2_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *RxFCSErrors_P2 - Rx FCS Error Counter
- ***************************************************************************/
-/* SWITCH_CORE :: RxFCSErrors_P2 :: COUNT [31:00] */
-#define BCHP_SWITCH_CORE_RxFCSErrors_P2_COUNT_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_RxFCSErrors_P2_COUNT_SHIFT 0
-#define BCHP_SWITCH_CORE_RxFCSErrors_P2_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *RxGoodOctets_P2 - Rx Good Packet Octet Counter
- ***************************************************************************/
-/* SWITCH_CORE :: RxGoodOctets_P2 :: COUNT [63:00] */
-#define BCHP_SWITCH_CORE_RxGoodOctets_P2_COUNT_MASK 0x00000000ffffffff
-#define BCHP_SWITCH_CORE_RxGoodOctets_P2_COUNT_SHIFT 0
-#define BCHP_SWITCH_CORE_RxGoodOctets_P2_COUNT_DEFAULT 0x0000000000000000
-
-/***************************************************************************
- *RxDropPkts_P2 - Rx Drop Packet Counter
- ***************************************************************************/
-/* SWITCH_CORE :: RxDropPkts_P2 :: COUNT [31:00] */
-#define BCHP_SWITCH_CORE_RxDropPkts_P2_COUNT_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_RxDropPkts_P2_COUNT_SHIFT 0
-#define BCHP_SWITCH_CORE_RxDropPkts_P2_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *RxUnicastPkts_P2 - Rx Unicast Packet Counter
- ***************************************************************************/
-/* SWITCH_CORE :: RxUnicastPkts_P2 :: COUNT [31:00] */
-#define BCHP_SWITCH_CORE_RxUnicastPkts_P2_COUNT_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_RxUnicastPkts_P2_COUNT_SHIFT 0
-#define BCHP_SWITCH_CORE_RxUnicastPkts_P2_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *RxMulticastPkts_P2 - Rx Multicast Packet Counter
- ***************************************************************************/
-/* SWITCH_CORE :: RxMulticastPkts_P2 :: COUNT [31:00] */
-#define BCHP_SWITCH_CORE_RxMulticastPkts_P2_COUNT_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_RxMulticastPkts_P2_COUNT_SHIFT 0
-#define BCHP_SWITCH_CORE_RxMulticastPkts_P2_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *RxBroadcastPkts_P2 - Rx Broadcast Packet Counter
- ***************************************************************************/
-/* SWITCH_CORE :: RxBroadcastPkts_P2 :: COUNT [31:00] */
-#define BCHP_SWITCH_CORE_RxBroadcastPkts_P2_COUNT_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_RxBroadcastPkts_P2_COUNT_SHIFT 0
-#define BCHP_SWITCH_CORE_RxBroadcastPkts_P2_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *RxSAChanges_P2 - Rx SA Change Counter
- ***************************************************************************/
-/* SWITCH_CORE :: RxSAChanges_P2 :: COUNT [31:00] */
-#define BCHP_SWITCH_CORE_RxSAChanges_P2_COUNT_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_RxSAChanges_P2_COUNT_SHIFT 0
-#define BCHP_SWITCH_CORE_RxSAChanges_P2_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *RxFragments_P2 - Rx Fragment Counter
- ***************************************************************************/
-/* SWITCH_CORE :: RxFragments_P2 :: COUNT [31:00] */
-#define BCHP_SWITCH_CORE_RxFragments_P2_COUNT_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_RxFragments_P2_COUNT_SHIFT 0
-#define BCHP_SWITCH_CORE_RxFragments_P2_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *RxJumboPkt_P2 - Jumbo Packet Counter
- ***************************************************************************/
-/* SWITCH_CORE :: RxJumboPkt_P2 :: COUNT [31:00] */
-#define BCHP_SWITCH_CORE_RxJumboPkt_P2_COUNT_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_RxJumboPkt_P2_COUNT_SHIFT 0
-#define BCHP_SWITCH_CORE_RxJumboPkt_P2_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *RxSymblErr_P2 - Rx Symbol Error Counter
- ***************************************************************************/
-/* SWITCH_CORE :: RxSymblErr_P2 :: COUNT [31:00] */
-#define BCHP_SWITCH_CORE_RxSymblErr_P2_COUNT_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_RxSymblErr_P2_COUNT_SHIFT 0
-#define BCHP_SWITCH_CORE_RxSymblErr_P2_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *InRangeErrCount_P2 - InRangeErrCount Counter
- ***************************************************************************/
-/* SWITCH_CORE :: InRangeErrCount_P2 :: COUNT [31:00] */
-#define BCHP_SWITCH_CORE_InRangeErrCount_P2_COUNT_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_InRangeErrCount_P2_COUNT_SHIFT 0
-#define BCHP_SWITCH_CORE_InRangeErrCount_P2_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *OutRangeErrCount_P2 - OutRangeErrCount Counter
- ***************************************************************************/
-/* SWITCH_CORE :: OutRangeErrCount_P2 :: COUNT [31:00] */
-#define BCHP_SWITCH_CORE_OutRangeErrCount_P2_COUNT_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_OutRangeErrCount_P2_COUNT_SHIFT 0
-#define BCHP_SWITCH_CORE_OutRangeErrCount_P2_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *EEE_LPI_EVENT_P2 - EEE Low-Power Idle Event Registers
- ***************************************************************************/
-/* SWITCH_CORE :: EEE_LPI_EVENT_P2 :: COUNT [31:00] */
-#define BCHP_SWITCH_CORE_EEE_LPI_EVENT_P2_COUNT_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_EEE_LPI_EVENT_P2_COUNT_SHIFT 0
-#define BCHP_SWITCH_CORE_EEE_LPI_EVENT_P2_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *EEE_LPI_DURATION_P2 - EEE Low-Power Idle Duration Registers
- ***************************************************************************/
-/* SWITCH_CORE :: EEE_LPI_DURATION_P2 :: COUNT [31:00] */
-#define BCHP_SWITCH_CORE_EEE_LPI_DURATION_P2_COUNT_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_EEE_LPI_DURATION_P2_COUNT_SHIFT 0
-#define BCHP_SWITCH_CORE_EEE_LPI_DURATION_P2_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *RxDiscard_P2 - Rx Discard Counter
- ***************************************************************************/
-/* SWITCH_CORE :: RxDiscard_P2 :: COUNT [31:00] */
-#define BCHP_SWITCH_CORE_RxDiscard_P2_COUNT_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_RxDiscard_P2_COUNT_SHIFT 0
-#define BCHP_SWITCH_CORE_RxDiscard_P2_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *TxQPKTQ6_P2 - Tx Q6 Packet Counter
- ***************************************************************************/
-/* SWITCH_CORE :: TxQPKTQ6_P2 :: COUNT [31:00] */
-#define BCHP_SWITCH_CORE_TxQPKTQ6_P2_COUNT_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_TxQPKTQ6_P2_COUNT_SHIFT 0
-#define BCHP_SWITCH_CORE_TxQPKTQ6_P2_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *TxQPKTQ7_P2 - Tx Q7 Packet Counter
- ***************************************************************************/
-/* SWITCH_CORE :: TxQPKTQ7_P2 :: COUNT [31:00] */
-#define BCHP_SWITCH_CORE_TxQPKTQ7_P2_COUNT_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_TxQPKTQ7_P2_COUNT_SHIFT 0
-#define BCHP_SWITCH_CORE_TxQPKTQ7_P2_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *TxPkts64Octets_P2 - Tx 64 Bytes Octets Counter
- ***************************************************************************/
-/* SWITCH_CORE :: TxPkts64Octets_P2 :: COUNT [31:00] */
-#define BCHP_SWITCH_CORE_TxPkts64Octets_P2_COUNT_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_TxPkts64Octets_P2_COUNT_SHIFT 0
-#define BCHP_SWITCH_CORE_TxPkts64Octets_P2_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *TxPkts65to127Octets_P2 - Tx 65 to 127 Bytes Octets Counter
- ***************************************************************************/
-/* SWITCH_CORE :: TxPkts65to127Octets_P2 :: COUNT [31:00] */
-#define BCHP_SWITCH_CORE_TxPkts65to127Octets_P2_COUNT_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_TxPkts65to127Octets_P2_COUNT_SHIFT 0
-#define BCHP_SWITCH_CORE_TxPkts65to127Octets_P2_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *TxPkts128to255Octets_P2 - Tx 128 to 255 Bytes Octets Counter
- ***************************************************************************/
-/* SWITCH_CORE :: TxPkts128to255Octets_P2 :: COUNT [31:00] */
-#define BCHP_SWITCH_CORE_TxPkts128to255Octets_P2_COUNT_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_TxPkts128to255Octets_P2_COUNT_SHIFT 0
-#define BCHP_SWITCH_CORE_TxPkts128to255Octets_P2_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *TxPkts256to511Octets_P2 - Tx 256 to 511 Bytes Octets Counter
- ***************************************************************************/
-/* SWITCH_CORE :: TxPkts256to511Octets_P2 :: COUNT [31:00] */
-#define BCHP_SWITCH_CORE_TxPkts256to511Octets_P2_COUNT_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_TxPkts256to511Octets_P2_COUNT_SHIFT 0
-#define BCHP_SWITCH_CORE_TxPkts256to511Octets_P2_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *TxPkts512to1023Octets_P2 - Tx 512 to 1023 Bytes Octets Counter
- ***************************************************************************/
-/* SWITCH_CORE :: TxPkts512to1023Octets_P2 :: COUNT [31:00] */
-#define BCHP_SWITCH_CORE_TxPkts512to1023Octets_P2_COUNT_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_TxPkts512to1023Octets_P2_COUNT_SHIFT 0
-#define BCHP_SWITCH_CORE_TxPkts512to1023Octets_P2_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *TxPkts1024toMaxPktOctets_P2 - Tx 1024 to MaxPkt Bytes Octets Counter
- ***************************************************************************/
-/* SWITCH_CORE :: TxPkts1024toMaxPktOctets_P2 :: COUNT [31:00] */
-#define BCHP_SWITCH_CORE_TxPkts1024toMaxPktOctets_P2_COUNT_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_TxPkts1024toMaxPktOctets_P2_COUNT_SHIFT 0
-#define BCHP_SWITCH_CORE_TxPkts1024toMaxPktOctets_P2_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *TxOctets_P3 - Tx Octets
- ***************************************************************************/
-/* SWITCH_CORE :: TxOctets_P3 :: COUNT [63:00] */
-#define BCHP_SWITCH_CORE_TxOctets_P3_COUNT_MASK 0x00000000ffffffff
-#define BCHP_SWITCH_CORE_TxOctets_P3_COUNT_SHIFT 0
-#define BCHP_SWITCH_CORE_TxOctets_P3_COUNT_DEFAULT 0x0000000000000000
-
-/***************************************************************************
- *TxDropPkts_P3 - Tx Drop Packet Counter
- ***************************************************************************/
-/* SWITCH_CORE :: TxDropPkts_P3 :: COUNT [31:00] */
-#define BCHP_SWITCH_CORE_TxDropPkts_P3_COUNT_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_TxDropPkts_P3_COUNT_SHIFT 0
-#define BCHP_SWITCH_CORE_TxDropPkts_P3_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *TxQPKTQ0_P3 - Tx Q0 Packet Counter
- ***************************************************************************/
-/* SWITCH_CORE :: TxQPKTQ0_P3 :: COUNT [31:00] */
-#define BCHP_SWITCH_CORE_TxQPKTQ0_P3_COUNT_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_TxQPKTQ0_P3_COUNT_SHIFT 0
-#define BCHP_SWITCH_CORE_TxQPKTQ0_P3_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *TxBroadcastPkts_P3 - Tx Broadcast Packet Counter
- ***************************************************************************/
-/* SWITCH_CORE :: TxBroadcastPkts_P3 :: COUNT [31:00] */
-#define BCHP_SWITCH_CORE_TxBroadcastPkts_P3_COUNT_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_TxBroadcastPkts_P3_COUNT_SHIFT 0
-#define BCHP_SWITCH_CORE_TxBroadcastPkts_P3_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *TxMulticastPkts_P3 - Tx Multicast Packet Counter
- ***************************************************************************/
-/* SWITCH_CORE :: TxMulticastPkts_P3 :: COUNT [31:00] */
-#define BCHP_SWITCH_CORE_TxMulticastPkts_P3_COUNT_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_TxMulticastPkts_P3_COUNT_SHIFT 0
-#define BCHP_SWITCH_CORE_TxMulticastPkts_P3_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *TxUnicastPkts_P3 - Tx Unicast Packet Counter
- ***************************************************************************/
-/* SWITCH_CORE :: TxUnicastPkts_P3 :: COUNT [31:00] */
-#define BCHP_SWITCH_CORE_TxUnicastPkts_P3_COUNT_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_TxUnicastPkts_P3_COUNT_SHIFT 0
-#define BCHP_SWITCH_CORE_TxUnicastPkts_P3_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *TxCollisions_P3 - Tx Collision Counter
- ***************************************************************************/
-/* SWITCH_CORE :: TxCollisions_P3 :: COUNT [31:00] */
-#define BCHP_SWITCH_CORE_TxCollisions_P3_COUNT_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_TxCollisions_P3_COUNT_SHIFT 0
-#define BCHP_SWITCH_CORE_TxCollisions_P3_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *TxSingleCollision_P3 - Tx Single Collision Counter
- ***************************************************************************/
-/* SWITCH_CORE :: TxSingleCollision_P3 :: COUNT [31:00] */
-#define BCHP_SWITCH_CORE_TxSingleCollision_P3_COUNT_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_TxSingleCollision_P3_COUNT_SHIFT 0
-#define BCHP_SWITCH_CORE_TxSingleCollision_P3_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *TxMultipleCollision_P3 - Tx Multiple collsion Counter
- ***************************************************************************/
-/* SWITCH_CORE :: TxMultipleCollision_P3 :: COUNT [31:00] */
-#define BCHP_SWITCH_CORE_TxMultipleCollision_P3_COUNT_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_TxMultipleCollision_P3_COUNT_SHIFT 0
-#define BCHP_SWITCH_CORE_TxMultipleCollision_P3_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *TxDeferredTransmit_P3 - Tx Deferred Transmit Counter
- ***************************************************************************/
-/* SWITCH_CORE :: TxDeferredTransmit_P3 :: COUNT [31:00] */
-#define BCHP_SWITCH_CORE_TxDeferredTransmit_P3_COUNT_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_TxDeferredTransmit_P3_COUNT_SHIFT 0
-#define BCHP_SWITCH_CORE_TxDeferredTransmit_P3_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *TxLateCollision_P3 - Tx Late Collision Counter
- ***************************************************************************/
-/* SWITCH_CORE :: TxLateCollision_P3 :: COUNT [31:00] */
-#define BCHP_SWITCH_CORE_TxLateCollision_P3_COUNT_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_TxLateCollision_P3_COUNT_SHIFT 0
-#define BCHP_SWITCH_CORE_TxLateCollision_P3_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *TxExcessiveCollision_P3 - Tx Excessive Collision Counter
- ***************************************************************************/
-/* SWITCH_CORE :: TxExcessiveCollision_P3 :: COUNT [31:00] */
-#define BCHP_SWITCH_CORE_TxExcessiveCollision_P3_COUNT_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_TxExcessiveCollision_P3_COUNT_SHIFT 0
-#define BCHP_SWITCH_CORE_TxExcessiveCollision_P3_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *TxFrameInDisc_P3 - Tx Fram IN Disc Counter
- ***************************************************************************/
-/* SWITCH_CORE :: TxFrameInDisc_P3 :: COUNT [31:00] */
-#define BCHP_SWITCH_CORE_TxFrameInDisc_P3_COUNT_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_TxFrameInDisc_P3_COUNT_SHIFT 0
-#define BCHP_SWITCH_CORE_TxFrameInDisc_P3_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *TxPausePkts_P3 - Tx Pause Packet Counter
- ***************************************************************************/
-/* SWITCH_CORE :: TxPausePkts_P3 :: COUNT [31:00] */
-#define BCHP_SWITCH_CORE_TxPausePkts_P3_COUNT_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_TxPausePkts_P3_COUNT_SHIFT 0
-#define BCHP_SWITCH_CORE_TxPausePkts_P3_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *TxQPKTQ1_P3 - Tx Q1 Packet Counter
- ***************************************************************************/
-/* SWITCH_CORE :: TxQPKTQ1_P3 :: COUNT [31:00] */
-#define BCHP_SWITCH_CORE_TxQPKTQ1_P3_COUNT_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_TxQPKTQ1_P3_COUNT_SHIFT 0
-#define BCHP_SWITCH_CORE_TxQPKTQ1_P3_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *TxQPKTQ2_P3 - Tx Q2 Packet Counter
- ***************************************************************************/
-/* SWITCH_CORE :: TxQPKTQ2_P3 :: COUNT [31:00] */
-#define BCHP_SWITCH_CORE_TxQPKTQ2_P3_COUNT_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_TxQPKTQ2_P3_COUNT_SHIFT 0
-#define BCHP_SWITCH_CORE_TxQPKTQ2_P3_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *TxQPKTQ3_P3 - Tx Q3 Packet Counter
- ***************************************************************************/
-/* SWITCH_CORE :: TxQPKTQ3_P3 :: COUNT [31:00] */
-#define BCHP_SWITCH_CORE_TxQPKTQ3_P3_COUNT_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_TxQPKTQ3_P3_COUNT_SHIFT 0
-#define BCHP_SWITCH_CORE_TxQPKTQ3_P3_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *TxQPKTQ4_P3 - Tx Q4 Packet Counter
- ***************************************************************************/
-/* SWITCH_CORE :: TxQPKTQ4_P3 :: COUNT [31:00] */
-#define BCHP_SWITCH_CORE_TxQPKTQ4_P3_COUNT_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_TxQPKTQ4_P3_COUNT_SHIFT 0
-#define BCHP_SWITCH_CORE_TxQPKTQ4_P3_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *TxQPKTQ5_P3 - Tx Q5 Packet Counter
- ***************************************************************************/
-/* SWITCH_CORE :: TxQPKTQ5_P3 :: COUNT [31:00] */
-#define BCHP_SWITCH_CORE_TxQPKTQ5_P3_COUNT_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_TxQPKTQ5_P3_COUNT_SHIFT 0
-#define BCHP_SWITCH_CORE_TxQPKTQ5_P3_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *RxOctets_P3 - Rx Packet Octets Counter
- ***************************************************************************/
-/* SWITCH_CORE :: RxOctets_P3 :: COUNT [63:00] */
-#define BCHP_SWITCH_CORE_RxOctets_P3_COUNT_MASK 0x00000000ffffffff
-#define BCHP_SWITCH_CORE_RxOctets_P3_COUNT_SHIFT 0
-#define BCHP_SWITCH_CORE_RxOctets_P3_COUNT_DEFAULT 0x0000000000000000
-
-/***************************************************************************
- *RxUndersizePkts_P3 - Rx Under Size Packet Octets Counter
- ***************************************************************************/
-/* SWITCH_CORE :: RxUndersizePkts_P3 :: COUNT [31:00] */
-#define BCHP_SWITCH_CORE_RxUndersizePkts_P3_COUNT_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_RxUndersizePkts_P3_COUNT_SHIFT 0
-#define BCHP_SWITCH_CORE_RxUndersizePkts_P3_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *RxPausePkts_P3 - Rx Pause Packet Counter
- ***************************************************************************/
-/* SWITCH_CORE :: RxPausePkts_P3 :: COUNT [31:00] */
-#define BCHP_SWITCH_CORE_RxPausePkts_P3_COUNT_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_RxPausePkts_P3_COUNT_SHIFT 0
-#define BCHP_SWITCH_CORE_RxPausePkts_P3_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *RxPkts64Octets_P3 - Rx 64 Bytes Octets Counter
- ***************************************************************************/
-/* SWITCH_CORE :: RxPkts64Octets_P3 :: COUNT [31:00] */
-#define BCHP_SWITCH_CORE_RxPkts64Octets_P3_COUNT_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_RxPkts64Octets_P3_COUNT_SHIFT 0
-#define BCHP_SWITCH_CORE_RxPkts64Octets_P3_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *RxPkts65to127Octets_P3 - Rx 65 to 127 Bytes Octets Counter
- ***************************************************************************/
-/* SWITCH_CORE :: RxPkts65to127Octets_P3 :: COUNT [31:00] */
-#define BCHP_SWITCH_CORE_RxPkts65to127Octets_P3_COUNT_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_RxPkts65to127Octets_P3_COUNT_SHIFT 0
-#define BCHP_SWITCH_CORE_RxPkts65to127Octets_P3_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *RxPkts128to255Octets_P3 - Rx 128 to 255 Bytes Octets Counter
- ***************************************************************************/
-/* SWITCH_CORE :: RxPkts128to255Octets_P3 :: COUNT [31:00] */
-#define BCHP_SWITCH_CORE_RxPkts128to255Octets_P3_COUNT_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_RxPkts128to255Octets_P3_COUNT_SHIFT 0
-#define BCHP_SWITCH_CORE_RxPkts128to255Octets_P3_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *RxPkts256to511Octets_P3 - Rx 256 to 511 Bytes Octets Counter
- ***************************************************************************/
-/* SWITCH_CORE :: RxPkts256to511Octets_P3 :: COUNT [31:00] */
-#define BCHP_SWITCH_CORE_RxPkts256to511Octets_P3_COUNT_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_RxPkts256to511Octets_P3_COUNT_SHIFT 0
-#define BCHP_SWITCH_CORE_RxPkts256to511Octets_P3_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *RxPkts512to1023Octets_P3 - Rx 512 to 1023 Bytes Octets Counter
- ***************************************************************************/
-/* SWITCH_CORE :: RxPkts512to1023Octets_P3 :: COUNT [31:00] */
-#define BCHP_SWITCH_CORE_RxPkts512to1023Octets_P3_COUNT_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_RxPkts512to1023Octets_P3_COUNT_SHIFT 0
-#define BCHP_SWITCH_CORE_RxPkts512to1023Octets_P3_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *RxPkts1024toMaxPktOctets_P3 - Rx 1024 to MaxPkt Bytes Octets Counter
- ***************************************************************************/
-/* SWITCH_CORE :: RxPkts1024toMaxPktOctets_P3 :: COUNT [31:00] */
-#define BCHP_SWITCH_CORE_RxPkts1024toMaxPktOctets_P3_COUNT_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_RxPkts1024toMaxPktOctets_P3_COUNT_SHIFT 0
-#define BCHP_SWITCH_CORE_RxPkts1024toMaxPktOctets_P3_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *RxOversizePkts_P3 - Rx Over Size Packet Counter
- ***************************************************************************/
-/* SWITCH_CORE :: RxOversizePkts_P3 :: COUNT [31:00] */
-#define BCHP_SWITCH_CORE_RxOversizePkts_P3_COUNT_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_RxOversizePkts_P3_COUNT_SHIFT 0
-#define BCHP_SWITCH_CORE_RxOversizePkts_P3_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *RxJabbers_P3 - Rx Jabber Packet Counter
- ***************************************************************************/
-/* SWITCH_CORE :: RxJabbers_P3 :: COUNT [31:00] */
-#define BCHP_SWITCH_CORE_RxJabbers_P3_COUNT_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_RxJabbers_P3_COUNT_SHIFT 0
-#define BCHP_SWITCH_CORE_RxJabbers_P3_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *RxAlignmentErrors_P3 - Rx Alignment Error Counter
- ***************************************************************************/
-/* SWITCH_CORE :: RxAlignmentErrors_P3 :: COUNT [31:00] */
-#define BCHP_SWITCH_CORE_RxAlignmentErrors_P3_COUNT_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_RxAlignmentErrors_P3_COUNT_SHIFT 0
-#define BCHP_SWITCH_CORE_RxAlignmentErrors_P3_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *RxFCSErrors_P3 - Rx FCS Error Counter
- ***************************************************************************/
-/* SWITCH_CORE :: RxFCSErrors_P3 :: COUNT [31:00] */
-#define BCHP_SWITCH_CORE_RxFCSErrors_P3_COUNT_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_RxFCSErrors_P3_COUNT_SHIFT 0
-#define BCHP_SWITCH_CORE_RxFCSErrors_P3_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *RxGoodOctets_P3 - Rx Good Packet Octet Counter
- ***************************************************************************/
-/* SWITCH_CORE :: RxGoodOctets_P3 :: COUNT [63:00] */
-#define BCHP_SWITCH_CORE_RxGoodOctets_P3_COUNT_MASK 0x00000000ffffffff
-#define BCHP_SWITCH_CORE_RxGoodOctets_P3_COUNT_SHIFT 0
-#define BCHP_SWITCH_CORE_RxGoodOctets_P3_COUNT_DEFAULT 0x0000000000000000
-
-/***************************************************************************
- *RxDropPkts_P3 - Rx Drop Packet Counter
- ***************************************************************************/
-/* SWITCH_CORE :: RxDropPkts_P3 :: COUNT [31:00] */
-#define BCHP_SWITCH_CORE_RxDropPkts_P3_COUNT_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_RxDropPkts_P3_COUNT_SHIFT 0
-#define BCHP_SWITCH_CORE_RxDropPkts_P3_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *RxUnicastPkts_P3 - Rx Unicast Packet Counter
- ***************************************************************************/
-/* SWITCH_CORE :: RxUnicastPkts_P3 :: COUNT [31:00] */
-#define BCHP_SWITCH_CORE_RxUnicastPkts_P3_COUNT_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_RxUnicastPkts_P3_COUNT_SHIFT 0
-#define BCHP_SWITCH_CORE_RxUnicastPkts_P3_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *RxMulticastPkts_P3 - Rx Multicast Packet Counter
- ***************************************************************************/
-/* SWITCH_CORE :: RxMulticastPkts_P3 :: COUNT [31:00] */
-#define BCHP_SWITCH_CORE_RxMulticastPkts_P3_COUNT_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_RxMulticastPkts_P3_COUNT_SHIFT 0
-#define BCHP_SWITCH_CORE_RxMulticastPkts_P3_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *RxBroadcastPkts_P3 - Rx Broadcast Packet Counter
- ***************************************************************************/
-/* SWITCH_CORE :: RxBroadcastPkts_P3 :: COUNT [31:00] */
-#define BCHP_SWITCH_CORE_RxBroadcastPkts_P3_COUNT_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_RxBroadcastPkts_P3_COUNT_SHIFT 0
-#define BCHP_SWITCH_CORE_RxBroadcastPkts_P3_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *RxSAChanges_P3 - Rx SA Change Counter
- ***************************************************************************/
-/* SWITCH_CORE :: RxSAChanges_P3 :: COUNT [31:00] */
-#define BCHP_SWITCH_CORE_RxSAChanges_P3_COUNT_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_RxSAChanges_P3_COUNT_SHIFT 0
-#define BCHP_SWITCH_CORE_RxSAChanges_P3_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *RxFragments_P3 - Rx Fragment Counter
- ***************************************************************************/
-/* SWITCH_CORE :: RxFragments_P3 :: COUNT [31:00] */
-#define BCHP_SWITCH_CORE_RxFragments_P3_COUNT_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_RxFragments_P3_COUNT_SHIFT 0
-#define BCHP_SWITCH_CORE_RxFragments_P3_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *RxJumboPkt_P3 - Jumbo Packet Counter
- ***************************************************************************/
-/* SWITCH_CORE :: RxJumboPkt_P3 :: COUNT [31:00] */
-#define BCHP_SWITCH_CORE_RxJumboPkt_P3_COUNT_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_RxJumboPkt_P3_COUNT_SHIFT 0
-#define BCHP_SWITCH_CORE_RxJumboPkt_P3_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *RxSymblErr_P3 - Rx Symbol Error Counter
- ***************************************************************************/
-/* SWITCH_CORE :: RxSymblErr_P3 :: COUNT [31:00] */
-#define BCHP_SWITCH_CORE_RxSymblErr_P3_COUNT_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_RxSymblErr_P3_COUNT_SHIFT 0
-#define BCHP_SWITCH_CORE_RxSymblErr_P3_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *InRangeErrCount_P3 - InRangeErrCount Counter
- ***************************************************************************/
-/* SWITCH_CORE :: InRangeErrCount_P3 :: COUNT [31:00] */
-#define BCHP_SWITCH_CORE_InRangeErrCount_P3_COUNT_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_InRangeErrCount_P3_COUNT_SHIFT 0
-#define BCHP_SWITCH_CORE_InRangeErrCount_P3_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *OutRangeErrCount_P3 - OutRangeErrCount Counter
- ***************************************************************************/
-/* SWITCH_CORE :: OutRangeErrCount_P3 :: COUNT [31:00] */
-#define BCHP_SWITCH_CORE_OutRangeErrCount_P3_COUNT_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_OutRangeErrCount_P3_COUNT_SHIFT 0
-#define BCHP_SWITCH_CORE_OutRangeErrCount_P3_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *EEE_LPI_EVENT_P3 - EEE Low-Power Idle Event Registers
- ***************************************************************************/
-/* SWITCH_CORE :: EEE_LPI_EVENT_P3 :: COUNT [31:00] */
-#define BCHP_SWITCH_CORE_EEE_LPI_EVENT_P3_COUNT_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_EEE_LPI_EVENT_P3_COUNT_SHIFT 0
-#define BCHP_SWITCH_CORE_EEE_LPI_EVENT_P3_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *EEE_LPI_DURATION_P3 - EEE Low-Power Idle Duration Registers
- ***************************************************************************/
-/* SWITCH_CORE :: EEE_LPI_DURATION_P3 :: COUNT [31:00] */
-#define BCHP_SWITCH_CORE_EEE_LPI_DURATION_P3_COUNT_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_EEE_LPI_DURATION_P3_COUNT_SHIFT 0
-#define BCHP_SWITCH_CORE_EEE_LPI_DURATION_P3_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *RxDiscard_P3 - Rx Discard Counter
- ***************************************************************************/
-/* SWITCH_CORE :: RxDiscard_P3 :: COUNT [31:00] */
-#define BCHP_SWITCH_CORE_RxDiscard_P3_COUNT_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_RxDiscard_P3_COUNT_SHIFT 0
-#define BCHP_SWITCH_CORE_RxDiscard_P3_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *TxQPKTQ6_P3 - Tx Q6 Packet Counter
- ***************************************************************************/
-/* SWITCH_CORE :: TxQPKTQ6_P3 :: COUNT [31:00] */
-#define BCHP_SWITCH_CORE_TxQPKTQ6_P3_COUNT_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_TxQPKTQ6_P3_COUNT_SHIFT 0
-#define BCHP_SWITCH_CORE_TxQPKTQ6_P3_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *TxQPKTQ7_P3 - Tx Q7 Packet Counter
- ***************************************************************************/
-/* SWITCH_CORE :: TxQPKTQ7_P3 :: COUNT [31:00] */
-#define BCHP_SWITCH_CORE_TxQPKTQ7_P3_COUNT_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_TxQPKTQ7_P3_COUNT_SHIFT 0
-#define BCHP_SWITCH_CORE_TxQPKTQ7_P3_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *TxPkts64Octets_P3 - Tx 64 Bytes Octets Counter
- ***************************************************************************/
-/* SWITCH_CORE :: TxPkts64Octets_P3 :: COUNT [31:00] */
-#define BCHP_SWITCH_CORE_TxPkts64Octets_P3_COUNT_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_TxPkts64Octets_P3_COUNT_SHIFT 0
-#define BCHP_SWITCH_CORE_TxPkts64Octets_P3_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *TxPkts65to127Octets_P3 - Tx 65 to 127 Bytes Octets Counter
- ***************************************************************************/
-/* SWITCH_CORE :: TxPkts65to127Octets_P3 :: COUNT [31:00] */
-#define BCHP_SWITCH_CORE_TxPkts65to127Octets_P3_COUNT_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_TxPkts65to127Octets_P3_COUNT_SHIFT 0
-#define BCHP_SWITCH_CORE_TxPkts65to127Octets_P3_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *TxPkts128to255Octets_P3 - Tx 128 to 255 Bytes Octets Counter
- ***************************************************************************/
-/* SWITCH_CORE :: TxPkts128to255Octets_P3 :: COUNT [31:00] */
-#define BCHP_SWITCH_CORE_TxPkts128to255Octets_P3_COUNT_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_TxPkts128to255Octets_P3_COUNT_SHIFT 0
-#define BCHP_SWITCH_CORE_TxPkts128to255Octets_P3_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *TxPkts256to511Octets_P3 - Tx 256 to 511 Bytes Octets Counter
- ***************************************************************************/
-/* SWITCH_CORE :: TxPkts256to511Octets_P3 :: COUNT [31:00] */
-#define BCHP_SWITCH_CORE_TxPkts256to511Octets_P3_COUNT_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_TxPkts256to511Octets_P3_COUNT_SHIFT 0
-#define BCHP_SWITCH_CORE_TxPkts256to511Octets_P3_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *TxPkts512to1023Octets_P3 - Tx 512 to 1023 Bytes Octets Counter
- ***************************************************************************/
-/* SWITCH_CORE :: TxPkts512to1023Octets_P3 :: COUNT [31:00] */
-#define BCHP_SWITCH_CORE_TxPkts512to1023Octets_P3_COUNT_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_TxPkts512to1023Octets_P3_COUNT_SHIFT 0
-#define BCHP_SWITCH_CORE_TxPkts512to1023Octets_P3_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *TxPkts1024toMaxPktOctets_P3 - Tx 1024 to MaxPkt Bytes Octets Counter
- ***************************************************************************/
-/* SWITCH_CORE :: TxPkts1024toMaxPktOctets_P3 :: COUNT [31:00] */
-#define BCHP_SWITCH_CORE_TxPkts1024toMaxPktOctets_P3_COUNT_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_TxPkts1024toMaxPktOctets_P3_COUNT_SHIFT 0
-#define BCHP_SWITCH_CORE_TxPkts1024toMaxPktOctets_P3_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *TxOctets_P4 - Tx Octets
- ***************************************************************************/
-/* SWITCH_CORE :: TxOctets_P4 :: COUNT [63:00] */
-#define BCHP_SWITCH_CORE_TxOctets_P4_COUNT_MASK 0x00000000ffffffff
-#define BCHP_SWITCH_CORE_TxOctets_P4_COUNT_SHIFT 0
-#define BCHP_SWITCH_CORE_TxOctets_P4_COUNT_DEFAULT 0x0000000000000000
-
-/***************************************************************************
- *TxDropPkts_P4 - Tx Drop Packet Counter
- ***************************************************************************/
-/* SWITCH_CORE :: TxDropPkts_P4 :: COUNT [31:00] */
-#define BCHP_SWITCH_CORE_TxDropPkts_P4_COUNT_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_TxDropPkts_P4_COUNT_SHIFT 0
-#define BCHP_SWITCH_CORE_TxDropPkts_P4_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *TxQPKTQ0_P4 - Tx Q0 Packet Counter
- ***************************************************************************/
-/* SWITCH_CORE :: TxQPKTQ0_P4 :: COUNT [31:00] */
-#define BCHP_SWITCH_CORE_TxQPKTQ0_P4_COUNT_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_TxQPKTQ0_P4_COUNT_SHIFT 0
-#define BCHP_SWITCH_CORE_TxQPKTQ0_P4_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *TxBroadcastPkts_P4 - Tx Broadcast Packet Counter
- ***************************************************************************/
-/* SWITCH_CORE :: TxBroadcastPkts_P4 :: COUNT [31:00] */
-#define BCHP_SWITCH_CORE_TxBroadcastPkts_P4_COUNT_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_TxBroadcastPkts_P4_COUNT_SHIFT 0
-#define BCHP_SWITCH_CORE_TxBroadcastPkts_P4_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *TxMulticastPkts_P4 - Tx Multicast Packet Counter
- ***************************************************************************/
-/* SWITCH_CORE :: TxMulticastPkts_P4 :: COUNT [31:00] */
-#define BCHP_SWITCH_CORE_TxMulticastPkts_P4_COUNT_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_TxMulticastPkts_P4_COUNT_SHIFT 0
-#define BCHP_SWITCH_CORE_TxMulticastPkts_P4_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *TxUnicastPkts_P4 - Tx Unicast Packet Counter
- ***************************************************************************/
-/* SWITCH_CORE :: TxUnicastPkts_P4 :: COUNT [31:00] */
-#define BCHP_SWITCH_CORE_TxUnicastPkts_P4_COUNT_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_TxUnicastPkts_P4_COUNT_SHIFT 0
-#define BCHP_SWITCH_CORE_TxUnicastPkts_P4_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *TxCollisions_P4 - Tx Collision Counter
- ***************************************************************************/
-/* SWITCH_CORE :: TxCollisions_P4 :: COUNT [31:00] */
-#define BCHP_SWITCH_CORE_TxCollisions_P4_COUNT_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_TxCollisions_P4_COUNT_SHIFT 0
-#define BCHP_SWITCH_CORE_TxCollisions_P4_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *TxSingleCollision_P4 - Tx Single Collision Counter
- ***************************************************************************/
-/* SWITCH_CORE :: TxSingleCollision_P4 :: COUNT [31:00] */
-#define BCHP_SWITCH_CORE_TxSingleCollision_P4_COUNT_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_TxSingleCollision_P4_COUNT_SHIFT 0
-#define BCHP_SWITCH_CORE_TxSingleCollision_P4_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *TxMultipleCollision_P4 - Tx Multiple collsion Counter
- ***************************************************************************/
-/* SWITCH_CORE :: TxMultipleCollision_P4 :: COUNT [31:00] */
-#define BCHP_SWITCH_CORE_TxMultipleCollision_P4_COUNT_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_TxMultipleCollision_P4_COUNT_SHIFT 0
-#define BCHP_SWITCH_CORE_TxMultipleCollision_P4_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *TxDeferredTransmit_P4 - Tx Deferred Transmit Counter
- ***************************************************************************/
-/* SWITCH_CORE :: TxDeferredTransmit_P4 :: COUNT [31:00] */
-#define BCHP_SWITCH_CORE_TxDeferredTransmit_P4_COUNT_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_TxDeferredTransmit_P4_COUNT_SHIFT 0
-#define BCHP_SWITCH_CORE_TxDeferredTransmit_P4_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *TxLateCollision_P4 - Tx Late Collision Counter
- ***************************************************************************/
-/* SWITCH_CORE :: TxLateCollision_P4 :: COUNT [31:00] */
-#define BCHP_SWITCH_CORE_TxLateCollision_P4_COUNT_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_TxLateCollision_P4_COUNT_SHIFT 0
-#define BCHP_SWITCH_CORE_TxLateCollision_P4_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *TxExcessiveCollision_P4 - Tx Excessive Collision Counter
- ***************************************************************************/
-/* SWITCH_CORE :: TxExcessiveCollision_P4 :: COUNT [31:00] */
-#define BCHP_SWITCH_CORE_TxExcessiveCollision_P4_COUNT_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_TxExcessiveCollision_P4_COUNT_SHIFT 0
-#define BCHP_SWITCH_CORE_TxExcessiveCollision_P4_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *TxFrameInDisc_P4 - Tx Fram IN Disc Counter
- ***************************************************************************/
-/* SWITCH_CORE :: TxFrameInDisc_P4 :: COUNT [31:00] */
-#define BCHP_SWITCH_CORE_TxFrameInDisc_P4_COUNT_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_TxFrameInDisc_P4_COUNT_SHIFT 0
-#define BCHP_SWITCH_CORE_TxFrameInDisc_P4_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *TxPausePkts_P4 - Tx Pause Packet Counter
- ***************************************************************************/
-/* SWITCH_CORE :: TxPausePkts_P4 :: COUNT [31:00] */
-#define BCHP_SWITCH_CORE_TxPausePkts_P4_COUNT_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_TxPausePkts_P4_COUNT_SHIFT 0
-#define BCHP_SWITCH_CORE_TxPausePkts_P4_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *TxQPKTQ1_P4 - Tx Q1 Packet Counter
- ***************************************************************************/
-/* SWITCH_CORE :: TxQPKTQ1_P4 :: COUNT [31:00] */
-#define BCHP_SWITCH_CORE_TxQPKTQ1_P4_COUNT_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_TxQPKTQ1_P4_COUNT_SHIFT 0
-#define BCHP_SWITCH_CORE_TxQPKTQ1_P4_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *TxQPKTQ2_P4 - Tx Q2 Packet Counter
- ***************************************************************************/
-/* SWITCH_CORE :: TxQPKTQ2_P4 :: COUNT [31:00] */
-#define BCHP_SWITCH_CORE_TxQPKTQ2_P4_COUNT_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_TxQPKTQ2_P4_COUNT_SHIFT 0
-#define BCHP_SWITCH_CORE_TxQPKTQ2_P4_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *TxQPKTQ3_P4 - Tx Q3 Packet Counter
- ***************************************************************************/
-/* SWITCH_CORE :: TxQPKTQ3_P4 :: COUNT [31:00] */
-#define BCHP_SWITCH_CORE_TxQPKTQ3_P4_COUNT_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_TxQPKTQ3_P4_COUNT_SHIFT 0
-#define BCHP_SWITCH_CORE_TxQPKTQ3_P4_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *TxQPKTQ4_P4 - Tx Q4 Packet Counter
- ***************************************************************************/
-/* SWITCH_CORE :: TxQPKTQ4_P4 :: COUNT [31:00] */
-#define BCHP_SWITCH_CORE_TxQPKTQ4_P4_COUNT_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_TxQPKTQ4_P4_COUNT_SHIFT 0
-#define BCHP_SWITCH_CORE_TxQPKTQ4_P4_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *TxQPKTQ5_P4 - Tx Q5 Packet Counter
- ***************************************************************************/
-/* SWITCH_CORE :: TxQPKTQ5_P4 :: COUNT [31:00] */
-#define BCHP_SWITCH_CORE_TxQPKTQ5_P4_COUNT_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_TxQPKTQ5_P4_COUNT_SHIFT 0
-#define BCHP_SWITCH_CORE_TxQPKTQ5_P4_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *RxOctets_P4 - Rx Packet Octets Counter
- ***************************************************************************/
-/* SWITCH_CORE :: RxOctets_P4 :: COUNT [63:00] */
-#define BCHP_SWITCH_CORE_RxOctets_P4_COUNT_MASK 0x00000000ffffffff
-#define BCHP_SWITCH_CORE_RxOctets_P4_COUNT_SHIFT 0
-#define BCHP_SWITCH_CORE_RxOctets_P4_COUNT_DEFAULT 0x0000000000000000
-
-/***************************************************************************
- *RxUndersizePkts_P4 - Rx Under Size Packet Octets Counter
- ***************************************************************************/
-/* SWITCH_CORE :: RxUndersizePkts_P4 :: COUNT [31:00] */
-#define BCHP_SWITCH_CORE_RxUndersizePkts_P4_COUNT_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_RxUndersizePkts_P4_COUNT_SHIFT 0
-#define BCHP_SWITCH_CORE_RxUndersizePkts_P4_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *RxPausePkts_P4 - Rx Pause Packet Counter
- ***************************************************************************/
-/* SWITCH_CORE :: RxPausePkts_P4 :: COUNT [31:00] */
-#define BCHP_SWITCH_CORE_RxPausePkts_P4_COUNT_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_RxPausePkts_P4_COUNT_SHIFT 0
-#define BCHP_SWITCH_CORE_RxPausePkts_P4_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *RxPkts64Octets_P4 - Rx 64 Bytes Octets Counter
- ***************************************************************************/
-/* SWITCH_CORE :: RxPkts64Octets_P4 :: COUNT [31:00] */
-#define BCHP_SWITCH_CORE_RxPkts64Octets_P4_COUNT_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_RxPkts64Octets_P4_COUNT_SHIFT 0
-#define BCHP_SWITCH_CORE_RxPkts64Octets_P4_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *RxPkts65to127Octets_P4 - Rx 65 to 127 Bytes Octets Counter
- ***************************************************************************/
-/* SWITCH_CORE :: RxPkts65to127Octets_P4 :: COUNT [31:00] */
-#define BCHP_SWITCH_CORE_RxPkts65to127Octets_P4_COUNT_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_RxPkts65to127Octets_P4_COUNT_SHIFT 0
-#define BCHP_SWITCH_CORE_RxPkts65to127Octets_P4_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *RxPkts128to255Octets_P4 - Rx 128 to 255 Bytes Octets Counter
- ***************************************************************************/
-/* SWITCH_CORE :: RxPkts128to255Octets_P4 :: COUNT [31:00] */
-#define BCHP_SWITCH_CORE_RxPkts128to255Octets_P4_COUNT_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_RxPkts128to255Octets_P4_COUNT_SHIFT 0
-#define BCHP_SWITCH_CORE_RxPkts128to255Octets_P4_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *RxPkts256to511Octets_P4 - Rx 256 to 511 Bytes Octets Counter
- ***************************************************************************/
-/* SWITCH_CORE :: RxPkts256to511Octets_P4 :: COUNT [31:00] */
-#define BCHP_SWITCH_CORE_RxPkts256to511Octets_P4_COUNT_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_RxPkts256to511Octets_P4_COUNT_SHIFT 0
-#define BCHP_SWITCH_CORE_RxPkts256to511Octets_P4_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *RxPkts512to1023Octets_P4 - Rx 512 to 1023 Bytes Octets Counter
- ***************************************************************************/
-/* SWITCH_CORE :: RxPkts512to1023Octets_P4 :: COUNT [31:00] */
-#define BCHP_SWITCH_CORE_RxPkts512to1023Octets_P4_COUNT_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_RxPkts512to1023Octets_P4_COUNT_SHIFT 0
-#define BCHP_SWITCH_CORE_RxPkts512to1023Octets_P4_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *RxPkts1024toMaxPktOctets_P4 - Rx 1024 to MaxPkt Bytes Octets Counter
- ***************************************************************************/
-/* SWITCH_CORE :: RxPkts1024toMaxPktOctets_P4 :: COUNT [31:00] */
-#define BCHP_SWITCH_CORE_RxPkts1024toMaxPktOctets_P4_COUNT_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_RxPkts1024toMaxPktOctets_P4_COUNT_SHIFT 0
-#define BCHP_SWITCH_CORE_RxPkts1024toMaxPktOctets_P4_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *RxOversizePkts_P4 - Rx Over Size Packet Counter
- ***************************************************************************/
-/* SWITCH_CORE :: RxOversizePkts_P4 :: COUNT [31:00] */
-#define BCHP_SWITCH_CORE_RxOversizePkts_P4_COUNT_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_RxOversizePkts_P4_COUNT_SHIFT 0
-#define BCHP_SWITCH_CORE_RxOversizePkts_P4_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *RxJabbers_P4 - Rx Jabber Packet Counter
- ***************************************************************************/
-/* SWITCH_CORE :: RxJabbers_P4 :: COUNT [31:00] */
-#define BCHP_SWITCH_CORE_RxJabbers_P4_COUNT_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_RxJabbers_P4_COUNT_SHIFT 0
-#define BCHP_SWITCH_CORE_RxJabbers_P4_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *RxAlignmentErrors_P4 - Rx Alignment Error Counter
- ***************************************************************************/
-/* SWITCH_CORE :: RxAlignmentErrors_P4 :: COUNT [31:00] */
-#define BCHP_SWITCH_CORE_RxAlignmentErrors_P4_COUNT_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_RxAlignmentErrors_P4_COUNT_SHIFT 0
-#define BCHP_SWITCH_CORE_RxAlignmentErrors_P4_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *RxFCSErrors_P4 - Rx FCS Error Counter
- ***************************************************************************/
-/* SWITCH_CORE :: RxFCSErrors_P4 :: COUNT [31:00] */
-#define BCHP_SWITCH_CORE_RxFCSErrors_P4_COUNT_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_RxFCSErrors_P4_COUNT_SHIFT 0
-#define BCHP_SWITCH_CORE_RxFCSErrors_P4_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *RxGoodOctets_P4 - Rx Good Packet Octet Counter
- ***************************************************************************/
-/* SWITCH_CORE :: RxGoodOctets_P4 :: COUNT [63:00] */
-#define BCHP_SWITCH_CORE_RxGoodOctets_P4_COUNT_MASK 0x00000000ffffffff
-#define BCHP_SWITCH_CORE_RxGoodOctets_P4_COUNT_SHIFT 0
-#define BCHP_SWITCH_CORE_RxGoodOctets_P4_COUNT_DEFAULT 0x0000000000000000
-
-/***************************************************************************
- *RxDropPkts_P4 - Rx Drop Packet Counter
- ***************************************************************************/
-/* SWITCH_CORE :: RxDropPkts_P4 :: COUNT [31:00] */
-#define BCHP_SWITCH_CORE_RxDropPkts_P4_COUNT_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_RxDropPkts_P4_COUNT_SHIFT 0
-#define BCHP_SWITCH_CORE_RxDropPkts_P4_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *RxUnicastPkts_P4 - Rx Unicast Packet Counter
- ***************************************************************************/
-/* SWITCH_CORE :: RxUnicastPkts_P4 :: COUNT [31:00] */
-#define BCHP_SWITCH_CORE_RxUnicastPkts_P4_COUNT_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_RxUnicastPkts_P4_COUNT_SHIFT 0
-#define BCHP_SWITCH_CORE_RxUnicastPkts_P4_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *RxMulticastPkts_P4 - Rx Multicast Packet Counter
- ***************************************************************************/
-/* SWITCH_CORE :: RxMulticastPkts_P4 :: COUNT [31:00] */
-#define BCHP_SWITCH_CORE_RxMulticastPkts_P4_COUNT_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_RxMulticastPkts_P4_COUNT_SHIFT 0
-#define BCHP_SWITCH_CORE_RxMulticastPkts_P4_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *RxBroadcastPkts_P4 - Rx Broadcast Packet Counter
- ***************************************************************************/
-/* SWITCH_CORE :: RxBroadcastPkts_P4 :: COUNT [31:00] */
-#define BCHP_SWITCH_CORE_RxBroadcastPkts_P4_COUNT_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_RxBroadcastPkts_P4_COUNT_SHIFT 0
-#define BCHP_SWITCH_CORE_RxBroadcastPkts_P4_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *RxSAChanges_P4 - Rx SA Change Counter
- ***************************************************************************/
-/* SWITCH_CORE :: RxSAChanges_P4 :: COUNT [31:00] */
-#define BCHP_SWITCH_CORE_RxSAChanges_P4_COUNT_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_RxSAChanges_P4_COUNT_SHIFT 0
-#define BCHP_SWITCH_CORE_RxSAChanges_P4_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *RxFragments_P4 - Rx Fragment Counter
- ***************************************************************************/
-/* SWITCH_CORE :: RxFragments_P4 :: COUNT [31:00] */
-#define BCHP_SWITCH_CORE_RxFragments_P4_COUNT_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_RxFragments_P4_COUNT_SHIFT 0
-#define BCHP_SWITCH_CORE_RxFragments_P4_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *RxJumboPkt_P4 - Jumbo Packet Counter
- ***************************************************************************/
-/* SWITCH_CORE :: RxJumboPkt_P4 :: COUNT [31:00] */
-#define BCHP_SWITCH_CORE_RxJumboPkt_P4_COUNT_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_RxJumboPkt_P4_COUNT_SHIFT 0
-#define BCHP_SWITCH_CORE_RxJumboPkt_P4_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *RxSymblErr_P4 - Rx Symbol Error Counter
- ***************************************************************************/
-/* SWITCH_CORE :: RxSymblErr_P4 :: COUNT [31:00] */
-#define BCHP_SWITCH_CORE_RxSymblErr_P4_COUNT_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_RxSymblErr_P4_COUNT_SHIFT 0
-#define BCHP_SWITCH_CORE_RxSymblErr_P4_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *InRangeErrCount_P4 - InRangeErrCount Counter
- ***************************************************************************/
-/* SWITCH_CORE :: InRangeErrCount_P4 :: COUNT [31:00] */
-#define BCHP_SWITCH_CORE_InRangeErrCount_P4_COUNT_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_InRangeErrCount_P4_COUNT_SHIFT 0
-#define BCHP_SWITCH_CORE_InRangeErrCount_P4_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *OutRangeErrCount_P4 - OutRangeErrCount Counter
- ***************************************************************************/
-/* SWITCH_CORE :: OutRangeErrCount_P4 :: COUNT [31:00] */
-#define BCHP_SWITCH_CORE_OutRangeErrCount_P4_COUNT_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_OutRangeErrCount_P4_COUNT_SHIFT 0
-#define BCHP_SWITCH_CORE_OutRangeErrCount_P4_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *EEE_LPI_EVENT_P4 - EEE Low-Power Idle Event Registers
- ***************************************************************************/
-/* SWITCH_CORE :: EEE_LPI_EVENT_P4 :: COUNT [31:00] */
-#define BCHP_SWITCH_CORE_EEE_LPI_EVENT_P4_COUNT_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_EEE_LPI_EVENT_P4_COUNT_SHIFT 0
-#define BCHP_SWITCH_CORE_EEE_LPI_EVENT_P4_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *EEE_LPI_DURATION_P4 - EEE Low-Power Idle Duration Registers
- ***************************************************************************/
-/* SWITCH_CORE :: EEE_LPI_DURATION_P4 :: COUNT [31:00] */
-#define BCHP_SWITCH_CORE_EEE_LPI_DURATION_P4_COUNT_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_EEE_LPI_DURATION_P4_COUNT_SHIFT 0
-#define BCHP_SWITCH_CORE_EEE_LPI_DURATION_P4_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *RxDiscard_P4 - Rx Discard Counter
- ***************************************************************************/
-/* SWITCH_CORE :: RxDiscard_P4 :: COUNT [31:00] */
-#define BCHP_SWITCH_CORE_RxDiscard_P4_COUNT_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_RxDiscard_P4_COUNT_SHIFT 0
-#define BCHP_SWITCH_CORE_RxDiscard_P4_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *TxQPKTQ6_P4 - Tx Q6 Packet Counter
- ***************************************************************************/
-/* SWITCH_CORE :: TxQPKTQ6_P4 :: COUNT [31:00] */
-#define BCHP_SWITCH_CORE_TxQPKTQ6_P4_COUNT_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_TxQPKTQ6_P4_COUNT_SHIFT 0
-#define BCHP_SWITCH_CORE_TxQPKTQ6_P4_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *TxQPKTQ7_P4 - Tx Q7 Packet Counter
- ***************************************************************************/
-/* SWITCH_CORE :: TxQPKTQ7_P4 :: COUNT [31:00] */
-#define BCHP_SWITCH_CORE_TxQPKTQ7_P4_COUNT_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_TxQPKTQ7_P4_COUNT_SHIFT 0
-#define BCHP_SWITCH_CORE_TxQPKTQ7_P4_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *TxPkts64Octets_P4 - Tx 64 Bytes Octets Counter
- ***************************************************************************/
-/* SWITCH_CORE :: TxPkts64Octets_P4 :: COUNT [31:00] */
-#define BCHP_SWITCH_CORE_TxPkts64Octets_P4_COUNT_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_TxPkts64Octets_P4_COUNT_SHIFT 0
-#define BCHP_SWITCH_CORE_TxPkts64Octets_P4_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *TxPkts65to127Octets_P4 - Tx 65 to 127 Bytes Octets Counter
- ***************************************************************************/
-/* SWITCH_CORE :: TxPkts65to127Octets_P4 :: COUNT [31:00] */
-#define BCHP_SWITCH_CORE_TxPkts65to127Octets_P4_COUNT_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_TxPkts65to127Octets_P4_COUNT_SHIFT 0
-#define BCHP_SWITCH_CORE_TxPkts65to127Octets_P4_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *TxPkts128to255Octets_P4 - Tx 128 to 255 Bytes Octets Counter
- ***************************************************************************/
-/* SWITCH_CORE :: TxPkts128to255Octets_P4 :: COUNT [31:00] */
-#define BCHP_SWITCH_CORE_TxPkts128to255Octets_P4_COUNT_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_TxPkts128to255Octets_P4_COUNT_SHIFT 0
-#define BCHP_SWITCH_CORE_TxPkts128to255Octets_P4_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *TxPkts256to511Octets_P4 - Tx 256 to 511 Bytes Octets Counter
- ***************************************************************************/
-/* SWITCH_CORE :: TxPkts256to511Octets_P4 :: COUNT [31:00] */
-#define BCHP_SWITCH_CORE_TxPkts256to511Octets_P4_COUNT_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_TxPkts256to511Octets_P4_COUNT_SHIFT 0
-#define BCHP_SWITCH_CORE_TxPkts256to511Octets_P4_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *TxPkts512to1023Octets_P4 - Tx 512 to 1023 Bytes Octets Counter
- ***************************************************************************/
-/* SWITCH_CORE :: TxPkts512to1023Octets_P4 :: COUNT [31:00] */
-#define BCHP_SWITCH_CORE_TxPkts512to1023Octets_P4_COUNT_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_TxPkts512to1023Octets_P4_COUNT_SHIFT 0
-#define BCHP_SWITCH_CORE_TxPkts512to1023Octets_P4_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *TxPkts1024toMaxPktOctets_P4 - Tx 1024 to MaxPkt Bytes Octets Counter
- ***************************************************************************/
-/* SWITCH_CORE :: TxPkts1024toMaxPktOctets_P4 :: COUNT [31:00] */
-#define BCHP_SWITCH_CORE_TxPkts1024toMaxPktOctets_P4_COUNT_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_TxPkts1024toMaxPktOctets_P4_COUNT_SHIFT 0
-#define BCHP_SWITCH_CORE_TxPkts1024toMaxPktOctets_P4_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *TxOctets_P5 - Tx Octets
- ***************************************************************************/
-/* SWITCH_CORE :: TxOctets_P5 :: COUNT [63:00] */
-#define BCHP_SWITCH_CORE_TxOctets_P5_COUNT_MASK 0x00000000ffffffff
-#define BCHP_SWITCH_CORE_TxOctets_P5_COUNT_SHIFT 0
-#define BCHP_SWITCH_CORE_TxOctets_P5_COUNT_DEFAULT 0x0000000000000000
-
-/***************************************************************************
- *TxDropPkts_P5 - Tx Drop Packet Counter
- ***************************************************************************/
-/* SWITCH_CORE :: TxDropPkts_P5 :: COUNT [31:00] */
-#define BCHP_SWITCH_CORE_TxDropPkts_P5_COUNT_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_TxDropPkts_P5_COUNT_SHIFT 0
-#define BCHP_SWITCH_CORE_TxDropPkts_P5_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *TxQPKTQ0_P5 - Tx Q0 Packet Counter
- ***************************************************************************/
-/* SWITCH_CORE :: TxQPKTQ0_P5 :: COUNT [31:00] */
-#define BCHP_SWITCH_CORE_TxQPKTQ0_P5_COUNT_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_TxQPKTQ0_P5_COUNT_SHIFT 0
-#define BCHP_SWITCH_CORE_TxQPKTQ0_P5_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *TxBroadcastPkts_P5 - Tx Broadcast Packet Counter
- ***************************************************************************/
-/* SWITCH_CORE :: TxBroadcastPkts_P5 :: COUNT [31:00] */
-#define BCHP_SWITCH_CORE_TxBroadcastPkts_P5_COUNT_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_TxBroadcastPkts_P5_COUNT_SHIFT 0
-#define BCHP_SWITCH_CORE_TxBroadcastPkts_P5_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *TxMulticastPkts_P5 - Tx Multicast Packet Counter
- ***************************************************************************/
-/* SWITCH_CORE :: TxMulticastPkts_P5 :: COUNT [31:00] */
-#define BCHP_SWITCH_CORE_TxMulticastPkts_P5_COUNT_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_TxMulticastPkts_P5_COUNT_SHIFT 0
-#define BCHP_SWITCH_CORE_TxMulticastPkts_P5_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *TxUnicastPkts_P5 - Tx Unicast Packet Counter
- ***************************************************************************/
-/* SWITCH_CORE :: TxUnicastPkts_P5 :: COUNT [31:00] */
-#define BCHP_SWITCH_CORE_TxUnicastPkts_P5_COUNT_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_TxUnicastPkts_P5_COUNT_SHIFT 0
-#define BCHP_SWITCH_CORE_TxUnicastPkts_P5_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *TxCollisions_P5 - Tx Collision Counter
- ***************************************************************************/
-/* SWITCH_CORE :: TxCollisions_P5 :: COUNT [31:00] */
-#define BCHP_SWITCH_CORE_TxCollisions_P5_COUNT_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_TxCollisions_P5_COUNT_SHIFT 0
-#define BCHP_SWITCH_CORE_TxCollisions_P5_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *TxSingleCollision_P5 - Tx Single Collision Counter
- ***************************************************************************/
-/* SWITCH_CORE :: TxSingleCollision_P5 :: COUNT [31:00] */
-#define BCHP_SWITCH_CORE_TxSingleCollision_P5_COUNT_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_TxSingleCollision_P5_COUNT_SHIFT 0
-#define BCHP_SWITCH_CORE_TxSingleCollision_P5_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *TxMultipleCollision_P5 - Tx Multiple collsion Counter
- ***************************************************************************/
-/* SWITCH_CORE :: TxMultipleCollision_P5 :: COUNT [31:00] */
-#define BCHP_SWITCH_CORE_TxMultipleCollision_P5_COUNT_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_TxMultipleCollision_P5_COUNT_SHIFT 0
-#define BCHP_SWITCH_CORE_TxMultipleCollision_P5_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *TxDeferredTransmit_P5 - Tx Deferred Transmit Counter
- ***************************************************************************/
-/* SWITCH_CORE :: TxDeferredTransmit_P5 :: COUNT [31:00] */
-#define BCHP_SWITCH_CORE_TxDeferredTransmit_P5_COUNT_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_TxDeferredTransmit_P5_COUNT_SHIFT 0
-#define BCHP_SWITCH_CORE_TxDeferredTransmit_P5_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *TxLateCollision_P5 - Tx Late Collision Counter
- ***************************************************************************/
-/* SWITCH_CORE :: TxLateCollision_P5 :: COUNT [31:00] */
-#define BCHP_SWITCH_CORE_TxLateCollision_P5_COUNT_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_TxLateCollision_P5_COUNT_SHIFT 0
-#define BCHP_SWITCH_CORE_TxLateCollision_P5_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *TxExcessiveCollision_P5 - Tx Excessive Collision Counter
- ***************************************************************************/
-/* SWITCH_CORE :: TxExcessiveCollision_P5 :: COUNT [31:00] */
-#define BCHP_SWITCH_CORE_TxExcessiveCollision_P5_COUNT_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_TxExcessiveCollision_P5_COUNT_SHIFT 0
-#define BCHP_SWITCH_CORE_TxExcessiveCollision_P5_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *TxFrameInDisc_P5 - Tx Fram IN Disc Counter
- ***************************************************************************/
-/* SWITCH_CORE :: TxFrameInDisc_P5 :: COUNT [31:00] */
-#define BCHP_SWITCH_CORE_TxFrameInDisc_P5_COUNT_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_TxFrameInDisc_P5_COUNT_SHIFT 0
-#define BCHP_SWITCH_CORE_TxFrameInDisc_P5_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *TxPausePkts_P5 - Tx Pause Packet Counter
- ***************************************************************************/
-/* SWITCH_CORE :: TxPausePkts_P5 :: COUNT [31:00] */
-#define BCHP_SWITCH_CORE_TxPausePkts_P5_COUNT_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_TxPausePkts_P5_COUNT_SHIFT 0
-#define BCHP_SWITCH_CORE_TxPausePkts_P5_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *TxQPKTQ1_P5 - Tx Q1 Packet Counter
- ***************************************************************************/
-/* SWITCH_CORE :: TxQPKTQ1_P5 :: COUNT [31:00] */
-#define BCHP_SWITCH_CORE_TxQPKTQ1_P5_COUNT_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_TxQPKTQ1_P5_COUNT_SHIFT 0
-#define BCHP_SWITCH_CORE_TxQPKTQ1_P5_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *TxQPKTQ2_P5 - Tx Q2 Packet Counter
- ***************************************************************************/
-/* SWITCH_CORE :: TxQPKTQ2_P5 :: COUNT [31:00] */
-#define BCHP_SWITCH_CORE_TxQPKTQ2_P5_COUNT_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_TxQPKTQ2_P5_COUNT_SHIFT 0
-#define BCHP_SWITCH_CORE_TxQPKTQ2_P5_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *TxQPKTQ3_P5 - Tx Q3 Packet Counter
- ***************************************************************************/
-/* SWITCH_CORE :: TxQPKTQ3_P5 :: COUNT [31:00] */
-#define BCHP_SWITCH_CORE_TxQPKTQ3_P5_COUNT_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_TxQPKTQ3_P5_COUNT_SHIFT 0
-#define BCHP_SWITCH_CORE_TxQPKTQ3_P5_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *TxQPKTQ4_P5 - Tx Q4 Packet Counter
- ***************************************************************************/
-/* SWITCH_CORE :: TxQPKTQ4_P5 :: COUNT [31:00] */
-#define BCHP_SWITCH_CORE_TxQPKTQ4_P5_COUNT_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_TxQPKTQ4_P5_COUNT_SHIFT 0
-#define BCHP_SWITCH_CORE_TxQPKTQ4_P5_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *TxQPKTQ5_P5 - Tx Q5 Packet Counter
- ***************************************************************************/
-/* SWITCH_CORE :: TxQPKTQ5_P5 :: COUNT [31:00] */
-#define BCHP_SWITCH_CORE_TxQPKTQ5_P5_COUNT_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_TxQPKTQ5_P5_COUNT_SHIFT 0
-#define BCHP_SWITCH_CORE_TxQPKTQ5_P5_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *RxOctets_P5 - Rx Packet Octets Counter
- ***************************************************************************/
-/* SWITCH_CORE :: RxOctets_P5 :: COUNT [63:00] */
-#define BCHP_SWITCH_CORE_RxOctets_P5_COUNT_MASK 0x00000000ffffffff
-#define BCHP_SWITCH_CORE_RxOctets_P5_COUNT_SHIFT 0
-#define BCHP_SWITCH_CORE_RxOctets_P5_COUNT_DEFAULT 0x0000000000000000
-
-/***************************************************************************
- *RxUndersizePkts_P5 - Rx Under Size Packet Octets Counter
- ***************************************************************************/
-/* SWITCH_CORE :: RxUndersizePkts_P5 :: COUNT [31:00] */
-#define BCHP_SWITCH_CORE_RxUndersizePkts_P5_COUNT_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_RxUndersizePkts_P5_COUNT_SHIFT 0
-#define BCHP_SWITCH_CORE_RxUndersizePkts_P5_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *RxPausePkts_P5 - Rx Pause Packet Counter
- ***************************************************************************/
-/* SWITCH_CORE :: RxPausePkts_P5 :: COUNT [31:00] */
-#define BCHP_SWITCH_CORE_RxPausePkts_P5_COUNT_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_RxPausePkts_P5_COUNT_SHIFT 0
-#define BCHP_SWITCH_CORE_RxPausePkts_P5_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *RxPkts64Octets_P5 - Rx 64 Bytes Octets Counter
- ***************************************************************************/
-/* SWITCH_CORE :: RxPkts64Octets_P5 :: COUNT [31:00] */
-#define BCHP_SWITCH_CORE_RxPkts64Octets_P5_COUNT_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_RxPkts64Octets_P5_COUNT_SHIFT 0
-#define BCHP_SWITCH_CORE_RxPkts64Octets_P5_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *RxPkts65to127Octets_P5 - Rx 65 to 127 Bytes Octets Counter
- ***************************************************************************/
-/* SWITCH_CORE :: RxPkts65to127Octets_P5 :: COUNT [31:00] */
-#define BCHP_SWITCH_CORE_RxPkts65to127Octets_P5_COUNT_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_RxPkts65to127Octets_P5_COUNT_SHIFT 0
-#define BCHP_SWITCH_CORE_RxPkts65to127Octets_P5_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *RxPkts128to255Octets_P5 - Rx 128 to 255 Bytes Octets Counter
- ***************************************************************************/
-/* SWITCH_CORE :: RxPkts128to255Octets_P5 :: COUNT [31:00] */
-#define BCHP_SWITCH_CORE_RxPkts128to255Octets_P5_COUNT_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_RxPkts128to255Octets_P5_COUNT_SHIFT 0
-#define BCHP_SWITCH_CORE_RxPkts128to255Octets_P5_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *RxPkts256to511Octets_P5 - Rx 256 to 511 Bytes Octets Counter
- ***************************************************************************/
-/* SWITCH_CORE :: RxPkts256to511Octets_P5 :: COUNT [31:00] */
-#define BCHP_SWITCH_CORE_RxPkts256to511Octets_P5_COUNT_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_RxPkts256to511Octets_P5_COUNT_SHIFT 0
-#define BCHP_SWITCH_CORE_RxPkts256to511Octets_P5_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *RxPkts512to1023Octets_P5 - Rx 512 to 1023 Bytes Octets Counter
- ***************************************************************************/
-/* SWITCH_CORE :: RxPkts512to1023Octets_P5 :: COUNT [31:00] */
-#define BCHP_SWITCH_CORE_RxPkts512to1023Octets_P5_COUNT_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_RxPkts512to1023Octets_P5_COUNT_SHIFT 0
-#define BCHP_SWITCH_CORE_RxPkts512to1023Octets_P5_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *RxPkts1024toMaxPktOctets_P5 - Rx 1024 to MaxPkt Bytes Octets Counter
- ***************************************************************************/
-/* SWITCH_CORE :: RxPkts1024toMaxPktOctets_P5 :: COUNT [31:00] */
-#define BCHP_SWITCH_CORE_RxPkts1024toMaxPktOctets_P5_COUNT_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_RxPkts1024toMaxPktOctets_P5_COUNT_SHIFT 0
-#define BCHP_SWITCH_CORE_RxPkts1024toMaxPktOctets_P5_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *RxOversizePkts_P5 - Rx Over Size Packet Counter
- ***************************************************************************/
-/* SWITCH_CORE :: RxOversizePkts_P5 :: COUNT [31:00] */
-#define BCHP_SWITCH_CORE_RxOversizePkts_P5_COUNT_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_RxOversizePkts_P5_COUNT_SHIFT 0
-#define BCHP_SWITCH_CORE_RxOversizePkts_P5_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *RxJabbers_P5 - Rx Jabber Packet Counter
- ***************************************************************************/
-/* SWITCH_CORE :: RxJabbers_P5 :: COUNT [31:00] */
-#define BCHP_SWITCH_CORE_RxJabbers_P5_COUNT_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_RxJabbers_P5_COUNT_SHIFT 0
-#define BCHP_SWITCH_CORE_RxJabbers_P5_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *RxAlignmentErrors_P5 - Rx Alignment Error Counter
- ***************************************************************************/
-/* SWITCH_CORE :: RxAlignmentErrors_P5 :: COUNT [31:00] */
-#define BCHP_SWITCH_CORE_RxAlignmentErrors_P5_COUNT_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_RxAlignmentErrors_P5_COUNT_SHIFT 0
-#define BCHP_SWITCH_CORE_RxAlignmentErrors_P5_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *RxFCSErrors_P5 - Rx FCS Error Counter
- ***************************************************************************/
-/* SWITCH_CORE :: RxFCSErrors_P5 :: COUNT [31:00] */
-#define BCHP_SWITCH_CORE_RxFCSErrors_P5_COUNT_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_RxFCSErrors_P5_COUNT_SHIFT 0
-#define BCHP_SWITCH_CORE_RxFCSErrors_P5_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *RxGoodOctets_P5 - Rx Good Packet Octet Counter
- ***************************************************************************/
-/* SWITCH_CORE :: RxGoodOctets_P5 :: COUNT [63:00] */
-#define BCHP_SWITCH_CORE_RxGoodOctets_P5_COUNT_MASK 0x00000000ffffffff
-#define BCHP_SWITCH_CORE_RxGoodOctets_P5_COUNT_SHIFT 0
-#define BCHP_SWITCH_CORE_RxGoodOctets_P5_COUNT_DEFAULT 0x0000000000000000
-
-/***************************************************************************
- *RxDropPkts_P5 - Rx Drop Packet Counter
- ***************************************************************************/
-/* SWITCH_CORE :: RxDropPkts_P5 :: COUNT [31:00] */
-#define BCHP_SWITCH_CORE_RxDropPkts_P5_COUNT_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_RxDropPkts_P5_COUNT_SHIFT 0
-#define BCHP_SWITCH_CORE_RxDropPkts_P5_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *RxUnicastPkts_P5 - Rx Unicast Packet Counter
- ***************************************************************************/
-/* SWITCH_CORE :: RxUnicastPkts_P5 :: COUNT [31:00] */
-#define BCHP_SWITCH_CORE_RxUnicastPkts_P5_COUNT_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_RxUnicastPkts_P5_COUNT_SHIFT 0
-#define BCHP_SWITCH_CORE_RxUnicastPkts_P5_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *RxMulticastPkts_P5 - Rx Multicast Packet Counter
- ***************************************************************************/
-/* SWITCH_CORE :: RxMulticastPkts_P5 :: COUNT [31:00] */
-#define BCHP_SWITCH_CORE_RxMulticastPkts_P5_COUNT_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_RxMulticastPkts_P5_COUNT_SHIFT 0
-#define BCHP_SWITCH_CORE_RxMulticastPkts_P5_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *RxBroadcastPkts_P5 - Rx Broadcast Packet Counter
- ***************************************************************************/
-/* SWITCH_CORE :: RxBroadcastPkts_P5 :: COUNT [31:00] */
-#define BCHP_SWITCH_CORE_RxBroadcastPkts_P5_COUNT_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_RxBroadcastPkts_P5_COUNT_SHIFT 0
-#define BCHP_SWITCH_CORE_RxBroadcastPkts_P5_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *RxSAChanges_P5 - Rx SA Change Counter
- ***************************************************************************/
-/* SWITCH_CORE :: RxSAChanges_P5 :: COUNT [31:00] */
-#define BCHP_SWITCH_CORE_RxSAChanges_P5_COUNT_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_RxSAChanges_P5_COUNT_SHIFT 0
-#define BCHP_SWITCH_CORE_RxSAChanges_P5_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *RxFragments_P5 - Rx Fragment Counter
- ***************************************************************************/
-/* SWITCH_CORE :: RxFragments_P5 :: COUNT [31:00] */
-#define BCHP_SWITCH_CORE_RxFragments_P5_COUNT_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_RxFragments_P5_COUNT_SHIFT 0
-#define BCHP_SWITCH_CORE_RxFragments_P5_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *RxJumboPkt_P5 - Jumbo Packet Counter
- ***************************************************************************/
-/* SWITCH_CORE :: RxJumboPkt_P5 :: COUNT [31:00] */
-#define BCHP_SWITCH_CORE_RxJumboPkt_P5_COUNT_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_RxJumboPkt_P5_COUNT_SHIFT 0
-#define BCHP_SWITCH_CORE_RxJumboPkt_P5_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *RxSymblErr_P5 - Rx Symbol Error Counter
- ***************************************************************************/
-/* SWITCH_CORE :: RxSymblErr_P5 :: COUNT [31:00] */
-#define BCHP_SWITCH_CORE_RxSymblErr_P5_COUNT_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_RxSymblErr_P5_COUNT_SHIFT 0
-#define BCHP_SWITCH_CORE_RxSymblErr_P5_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *InRangeErrCount_P5 - InRangeErrCount Counter
- ***************************************************************************/
-/* SWITCH_CORE :: InRangeErrCount_P5 :: COUNT [31:00] */
-#define BCHP_SWITCH_CORE_InRangeErrCount_P5_COUNT_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_InRangeErrCount_P5_COUNT_SHIFT 0
-#define BCHP_SWITCH_CORE_InRangeErrCount_P5_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *OutRangeErrCount_P5 - OutRangeErrCount Counter
- ***************************************************************************/
-/* SWITCH_CORE :: OutRangeErrCount_P5 :: COUNT [31:00] */
-#define BCHP_SWITCH_CORE_OutRangeErrCount_P5_COUNT_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_OutRangeErrCount_P5_COUNT_SHIFT 0
-#define BCHP_SWITCH_CORE_OutRangeErrCount_P5_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *EEE_LPI_EVENT_P5 - EEE Low-Power Idle Event Registers
- ***************************************************************************/
-/* SWITCH_CORE :: EEE_LPI_EVENT_P5 :: COUNT [31:00] */
-#define BCHP_SWITCH_CORE_EEE_LPI_EVENT_P5_COUNT_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_EEE_LPI_EVENT_P5_COUNT_SHIFT 0
-#define BCHP_SWITCH_CORE_EEE_LPI_EVENT_P5_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *EEE_LPI_DURATION_P5 - EEE Low-Power Idle Duration Registers
- ***************************************************************************/
-/* SWITCH_CORE :: EEE_LPI_DURATION_P5 :: COUNT [31:00] */
-#define BCHP_SWITCH_CORE_EEE_LPI_DURATION_P5_COUNT_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_EEE_LPI_DURATION_P5_COUNT_SHIFT 0
-#define BCHP_SWITCH_CORE_EEE_LPI_DURATION_P5_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *RxDiscard_P5 - Rx Discard Counter
- ***************************************************************************/
-/* SWITCH_CORE :: RxDiscard_P5 :: COUNT [31:00] */
-#define BCHP_SWITCH_CORE_RxDiscard_P5_COUNT_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_RxDiscard_P5_COUNT_SHIFT 0
-#define BCHP_SWITCH_CORE_RxDiscard_P5_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *TxQPKTQ6_P5 - Tx Q6 Packet Counter
- ***************************************************************************/
-/* SWITCH_CORE :: TxQPKTQ6_P5 :: COUNT [31:00] */
-#define BCHP_SWITCH_CORE_TxQPKTQ6_P5_COUNT_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_TxQPKTQ6_P5_COUNT_SHIFT 0
-#define BCHP_SWITCH_CORE_TxQPKTQ6_P5_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *TxQPKTQ7_P5 - Tx Q7 Packet Counter
- ***************************************************************************/
-/* SWITCH_CORE :: TxQPKTQ7_P5 :: COUNT [31:00] */
-#define BCHP_SWITCH_CORE_TxQPKTQ7_P5_COUNT_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_TxQPKTQ7_P5_COUNT_SHIFT 0
-#define BCHP_SWITCH_CORE_TxQPKTQ7_P5_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *TxPkts64Octets_P5 - Tx 64 Bytes Octets Counter
- ***************************************************************************/
-/* SWITCH_CORE :: TxPkts64Octets_P5 :: COUNT [31:00] */
-#define BCHP_SWITCH_CORE_TxPkts64Octets_P5_COUNT_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_TxPkts64Octets_P5_COUNT_SHIFT 0
-#define BCHP_SWITCH_CORE_TxPkts64Octets_P5_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *TxPkts65to127Octets_P5 - Tx 65 to 127 Bytes Octets Counter
- ***************************************************************************/
-/* SWITCH_CORE :: TxPkts65to127Octets_P5 :: COUNT [31:00] */
-#define BCHP_SWITCH_CORE_TxPkts65to127Octets_P5_COUNT_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_TxPkts65to127Octets_P5_COUNT_SHIFT 0
-#define BCHP_SWITCH_CORE_TxPkts65to127Octets_P5_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *TxPkts128to255Octets_P5 - Tx 128 to 255 Bytes Octets Counter
- ***************************************************************************/
-/* SWITCH_CORE :: TxPkts128to255Octets_P5 :: COUNT [31:00] */
-#define BCHP_SWITCH_CORE_TxPkts128to255Octets_P5_COUNT_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_TxPkts128to255Octets_P5_COUNT_SHIFT 0
-#define BCHP_SWITCH_CORE_TxPkts128to255Octets_P5_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *TxPkts256to511Octets_P5 - Tx 256 to 511 Bytes Octets Counter
- ***************************************************************************/
-/* SWITCH_CORE :: TxPkts256to511Octets_P5 :: COUNT [31:00] */
-#define BCHP_SWITCH_CORE_TxPkts256to511Octets_P5_COUNT_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_TxPkts256to511Octets_P5_COUNT_SHIFT 0
-#define BCHP_SWITCH_CORE_TxPkts256to511Octets_P5_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *TxPkts512to1023Octets_P5 - Tx 512 to 1023 Bytes Octets Counter
- ***************************************************************************/
-/* SWITCH_CORE :: TxPkts512to1023Octets_P5 :: COUNT [31:00] */
-#define BCHP_SWITCH_CORE_TxPkts512to1023Octets_P5_COUNT_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_TxPkts512to1023Octets_P5_COUNT_SHIFT 0
-#define BCHP_SWITCH_CORE_TxPkts512to1023Octets_P5_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *TxPkts1024toMaxPktOctets_P5 - Tx 1024 to MaxPkt Bytes Octets Counter
- ***************************************************************************/
-/* SWITCH_CORE :: TxPkts1024toMaxPktOctets_P5 :: COUNT [31:00] */
-#define BCHP_SWITCH_CORE_TxPkts1024toMaxPktOctets_P5_COUNT_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_TxPkts1024toMaxPktOctets_P5_COUNT_SHIFT 0
-#define BCHP_SWITCH_CORE_TxPkts1024toMaxPktOctets_P5_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *TxOctets_P7 - Tx Octets
- ***************************************************************************/
-/* SWITCH_CORE :: TxOctets_P7 :: COUNT [63:00] */
-#define BCHP_SWITCH_CORE_TxOctets_P7_COUNT_MASK 0x00000000ffffffff
-#define BCHP_SWITCH_CORE_TxOctets_P7_COUNT_SHIFT 0
-#define BCHP_SWITCH_CORE_TxOctets_P7_COUNT_DEFAULT 0x0000000000000000
-
-/***************************************************************************
- *TxDropPkts_P7 - Tx Drop Packet Counter
- ***************************************************************************/
-/* SWITCH_CORE :: TxDropPkts_P7 :: COUNT [31:00] */
-#define BCHP_SWITCH_CORE_TxDropPkts_P7_COUNT_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_TxDropPkts_P7_COUNT_SHIFT 0
-#define BCHP_SWITCH_CORE_TxDropPkts_P7_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *TxQPKTQ0_P7 - Tx Q0 Packet Counter
- ***************************************************************************/
-/* SWITCH_CORE :: TxQPKTQ0_P7 :: COUNT [31:00] */
-#define BCHP_SWITCH_CORE_TxQPKTQ0_P7_COUNT_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_TxQPKTQ0_P7_COUNT_SHIFT 0
-#define BCHP_SWITCH_CORE_TxQPKTQ0_P7_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *TxBroadcastPkts_P7 - Tx Broadcast Packet Counter
- ***************************************************************************/
-/* SWITCH_CORE :: TxBroadcastPkts_P7 :: COUNT [31:00] */
-#define BCHP_SWITCH_CORE_TxBroadcastPkts_P7_COUNT_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_TxBroadcastPkts_P7_COUNT_SHIFT 0
-#define BCHP_SWITCH_CORE_TxBroadcastPkts_P7_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *TxMulticastPkts_P7 - Tx Multicast Packet Counter
- ***************************************************************************/
-/* SWITCH_CORE :: TxMulticastPkts_P7 :: COUNT [31:00] */
-#define BCHP_SWITCH_CORE_TxMulticastPkts_P7_COUNT_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_TxMulticastPkts_P7_COUNT_SHIFT 0
-#define BCHP_SWITCH_CORE_TxMulticastPkts_P7_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *TxUnicastPkts_P7 - Tx Unicast Packet Counter
- ***************************************************************************/
-/* SWITCH_CORE :: TxUnicastPkts_P7 :: COUNT [31:00] */
-#define BCHP_SWITCH_CORE_TxUnicastPkts_P7_COUNT_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_TxUnicastPkts_P7_COUNT_SHIFT 0
-#define BCHP_SWITCH_CORE_TxUnicastPkts_P7_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *TxCollisions_P7 - Tx Collision Counter
- ***************************************************************************/
-/* SWITCH_CORE :: TxCollisions_P7 :: COUNT [31:00] */
-#define BCHP_SWITCH_CORE_TxCollisions_P7_COUNT_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_TxCollisions_P7_COUNT_SHIFT 0
-#define BCHP_SWITCH_CORE_TxCollisions_P7_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *TxSingleCollision_P7 - Tx Single Collision Counter
- ***************************************************************************/
-/* SWITCH_CORE :: TxSingleCollision_P7 :: COUNT [31:00] */
-#define BCHP_SWITCH_CORE_TxSingleCollision_P7_COUNT_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_TxSingleCollision_P7_COUNT_SHIFT 0
-#define BCHP_SWITCH_CORE_TxSingleCollision_P7_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *TxMultipleCollision_P7 - Tx Multiple collsion Counter
- ***************************************************************************/
-/* SWITCH_CORE :: TxMultipleCollision_P7 :: COUNT [31:00] */
-#define BCHP_SWITCH_CORE_TxMultipleCollision_P7_COUNT_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_TxMultipleCollision_P7_COUNT_SHIFT 0
-#define BCHP_SWITCH_CORE_TxMultipleCollision_P7_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *TxDeferredTransmit_P7 - Tx Deferred Transmit Counter
- ***************************************************************************/
-/* SWITCH_CORE :: TxDeferredTransmit_P7 :: COUNT [31:00] */
-#define BCHP_SWITCH_CORE_TxDeferredTransmit_P7_COUNT_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_TxDeferredTransmit_P7_COUNT_SHIFT 0
-#define BCHP_SWITCH_CORE_TxDeferredTransmit_P7_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *TxLateCollision_P7 - Tx Late Collision Counter
- ***************************************************************************/
-/* SWITCH_CORE :: TxLateCollision_P7 :: COUNT [31:00] */
-#define BCHP_SWITCH_CORE_TxLateCollision_P7_COUNT_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_TxLateCollision_P7_COUNT_SHIFT 0
-#define BCHP_SWITCH_CORE_TxLateCollision_P7_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *TxExcessiveCollision_P7 - Tx Excessive Collision Counter
- ***************************************************************************/
-/* SWITCH_CORE :: TxExcessiveCollision_P7 :: COUNT [31:00] */
-#define BCHP_SWITCH_CORE_TxExcessiveCollision_P7_COUNT_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_TxExcessiveCollision_P7_COUNT_SHIFT 0
-#define BCHP_SWITCH_CORE_TxExcessiveCollision_P7_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *TxFrameInDisc_P7 - Tx Fram IN Disc Counter
- ***************************************************************************/
-/* SWITCH_CORE :: TxFrameInDisc_P7 :: COUNT [31:00] */
-#define BCHP_SWITCH_CORE_TxFrameInDisc_P7_COUNT_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_TxFrameInDisc_P7_COUNT_SHIFT 0
-#define BCHP_SWITCH_CORE_TxFrameInDisc_P7_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *TxPausePkts_P7 - Tx Pause Packet Counter
- ***************************************************************************/
-/* SWITCH_CORE :: TxPausePkts_P7 :: COUNT [31:00] */
-#define BCHP_SWITCH_CORE_TxPausePkts_P7_COUNT_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_TxPausePkts_P7_COUNT_SHIFT 0
-#define BCHP_SWITCH_CORE_TxPausePkts_P7_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *TxQPKTQ1_P7 - Tx Q1 Packet Counter
- ***************************************************************************/
-/* SWITCH_CORE :: TxQPKTQ1_P7 :: COUNT [31:00] */
-#define BCHP_SWITCH_CORE_TxQPKTQ1_P7_COUNT_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_TxQPKTQ1_P7_COUNT_SHIFT 0
-#define BCHP_SWITCH_CORE_TxQPKTQ1_P7_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *TxQPKTQ2_P7 - Tx Q2 Packet Counter
- ***************************************************************************/
-/* SWITCH_CORE :: TxQPKTQ2_P7 :: COUNT [31:00] */
-#define BCHP_SWITCH_CORE_TxQPKTQ2_P7_COUNT_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_TxQPKTQ2_P7_COUNT_SHIFT 0
-#define BCHP_SWITCH_CORE_TxQPKTQ2_P7_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *TxQPKTQ3_P7 - Tx Q3 Packet Counter
- ***************************************************************************/
-/* SWITCH_CORE :: TxQPKTQ3_P7 :: COUNT [31:00] */
-#define BCHP_SWITCH_CORE_TxQPKTQ3_P7_COUNT_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_TxQPKTQ3_P7_COUNT_SHIFT 0
-#define BCHP_SWITCH_CORE_TxQPKTQ3_P7_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *TxQPKTQ4_P7 - Tx Q4 Packet Counter
- ***************************************************************************/
-/* SWITCH_CORE :: TxQPKTQ4_P7 :: COUNT [31:00] */
-#define BCHP_SWITCH_CORE_TxQPKTQ4_P7_COUNT_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_TxQPKTQ4_P7_COUNT_SHIFT 0
-#define BCHP_SWITCH_CORE_TxQPKTQ4_P7_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *TxQPKTQ5_P7 - Tx Q5 Packet Counter
- ***************************************************************************/
-/* SWITCH_CORE :: TxQPKTQ5_P7 :: COUNT [31:00] */
-#define BCHP_SWITCH_CORE_TxQPKTQ5_P7_COUNT_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_TxQPKTQ5_P7_COUNT_SHIFT 0
-#define BCHP_SWITCH_CORE_TxQPKTQ5_P7_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *RxOctets_P7 - Rx Packet Octets Counter
- ***************************************************************************/
-/* SWITCH_CORE :: RxOctets_P7 :: COUNT [63:00] */
-#define BCHP_SWITCH_CORE_RxOctets_P7_COUNT_MASK 0x00000000ffffffff
-#define BCHP_SWITCH_CORE_RxOctets_P7_COUNT_SHIFT 0
-#define BCHP_SWITCH_CORE_RxOctets_P7_COUNT_DEFAULT 0x0000000000000000
-
-/***************************************************************************
- *RxUndersizePkts_P7 - Rx Under Size Packet Octets Counter
- ***************************************************************************/
-/* SWITCH_CORE :: RxUndersizePkts_P7 :: COUNT [31:00] */
-#define BCHP_SWITCH_CORE_RxUndersizePkts_P7_COUNT_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_RxUndersizePkts_P7_COUNT_SHIFT 0
-#define BCHP_SWITCH_CORE_RxUndersizePkts_P7_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *RxPausePkts_P7 - Rx Pause Packet Counter
- ***************************************************************************/
-/* SWITCH_CORE :: RxPausePkts_P7 :: COUNT [31:00] */
-#define BCHP_SWITCH_CORE_RxPausePkts_P7_COUNT_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_RxPausePkts_P7_COUNT_SHIFT 0
-#define BCHP_SWITCH_CORE_RxPausePkts_P7_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *RxPkts64Octets_P7 - Rx 64 Bytes Octets Counter
- ***************************************************************************/
-/* SWITCH_CORE :: RxPkts64Octets_P7 :: COUNT [31:00] */
-#define BCHP_SWITCH_CORE_RxPkts64Octets_P7_COUNT_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_RxPkts64Octets_P7_COUNT_SHIFT 0
-#define BCHP_SWITCH_CORE_RxPkts64Octets_P7_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *RxPkts65to127Octets_P7 - Rx 65 to 127 Bytes Octets Counter
- ***************************************************************************/
-/* SWITCH_CORE :: RxPkts65to127Octets_P7 :: COUNT [31:00] */
-#define BCHP_SWITCH_CORE_RxPkts65to127Octets_P7_COUNT_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_RxPkts65to127Octets_P7_COUNT_SHIFT 0
-#define BCHP_SWITCH_CORE_RxPkts65to127Octets_P7_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *RxPkts128to255Octets_P7 - Rx 128 to 255 Bytes Octets Counter
- ***************************************************************************/
-/* SWITCH_CORE :: RxPkts128to255Octets_P7 :: COUNT [31:00] */
-#define BCHP_SWITCH_CORE_RxPkts128to255Octets_P7_COUNT_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_RxPkts128to255Octets_P7_COUNT_SHIFT 0
-#define BCHP_SWITCH_CORE_RxPkts128to255Octets_P7_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *RxPkts256to511Octets_P7 - Rx 256 to 511 Bytes Octets Counter
- ***************************************************************************/
-/* SWITCH_CORE :: RxPkts256to511Octets_P7 :: COUNT [31:00] */
-#define BCHP_SWITCH_CORE_RxPkts256to511Octets_P7_COUNT_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_RxPkts256to511Octets_P7_COUNT_SHIFT 0
-#define BCHP_SWITCH_CORE_RxPkts256to511Octets_P7_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *RxPkts512to1023Octets_P7 - Rx 512 to 1023 Bytes Octets Counter
- ***************************************************************************/
-/* SWITCH_CORE :: RxPkts512to1023Octets_P7 :: COUNT [31:00] */
-#define BCHP_SWITCH_CORE_RxPkts512to1023Octets_P7_COUNT_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_RxPkts512to1023Octets_P7_COUNT_SHIFT 0
-#define BCHP_SWITCH_CORE_RxPkts512to1023Octets_P7_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *RxPkts1024toMaxPktOctets_P7 - Rx 1024 to MaxPkt Bytes Octets Counter
- ***************************************************************************/
-/* SWITCH_CORE :: RxPkts1024toMaxPktOctets_P7 :: COUNT [31:00] */
-#define BCHP_SWITCH_CORE_RxPkts1024toMaxPktOctets_P7_COUNT_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_RxPkts1024toMaxPktOctets_P7_COUNT_SHIFT 0
-#define BCHP_SWITCH_CORE_RxPkts1024toMaxPktOctets_P7_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *RxOversizePkts_P7 - Rx Over Size Packet Counter
- ***************************************************************************/
-/* SWITCH_CORE :: RxOversizePkts_P7 :: COUNT [31:00] */
-#define BCHP_SWITCH_CORE_RxOversizePkts_P7_COUNT_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_RxOversizePkts_P7_COUNT_SHIFT 0
-#define BCHP_SWITCH_CORE_RxOversizePkts_P7_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *RxJabbers_P7 - Rx Jabber Packet Counter
- ***************************************************************************/
-/* SWITCH_CORE :: RxJabbers_P7 :: COUNT [31:00] */
-#define BCHP_SWITCH_CORE_RxJabbers_P7_COUNT_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_RxJabbers_P7_COUNT_SHIFT 0
-#define BCHP_SWITCH_CORE_RxJabbers_P7_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *RxAlignmentErrors_P7 - Rx Alignment Error Counter
- ***************************************************************************/
-/* SWITCH_CORE :: RxAlignmentErrors_P7 :: COUNT [31:00] */
-#define BCHP_SWITCH_CORE_RxAlignmentErrors_P7_COUNT_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_RxAlignmentErrors_P7_COUNT_SHIFT 0
-#define BCHP_SWITCH_CORE_RxAlignmentErrors_P7_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *RxFCSErrors_P7 - Rx FCS Error Counter
- ***************************************************************************/
-/* SWITCH_CORE :: RxFCSErrors_P7 :: COUNT [31:00] */
-#define BCHP_SWITCH_CORE_RxFCSErrors_P7_COUNT_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_RxFCSErrors_P7_COUNT_SHIFT 0
-#define BCHP_SWITCH_CORE_RxFCSErrors_P7_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *RxGoodOctets_P7 - Rx Good Packet Octet Counter
- ***************************************************************************/
-/* SWITCH_CORE :: RxGoodOctets_P7 :: COUNT [63:00] */
-#define BCHP_SWITCH_CORE_RxGoodOctets_P7_COUNT_MASK 0x00000000ffffffff
-#define BCHP_SWITCH_CORE_RxGoodOctets_P7_COUNT_SHIFT 0
-#define BCHP_SWITCH_CORE_RxGoodOctets_P7_COUNT_DEFAULT 0x0000000000000000
-
-/***************************************************************************
- *RxDropPkts_P7 - Rx Drop Packet Counter
- ***************************************************************************/
-/* SWITCH_CORE :: RxDropPkts_P7 :: COUNT [31:00] */
-#define BCHP_SWITCH_CORE_RxDropPkts_P7_COUNT_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_RxDropPkts_P7_COUNT_SHIFT 0
-#define BCHP_SWITCH_CORE_RxDropPkts_P7_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *RxUnicastPkts_P7 - Rx Unicast Packet Counter
- ***************************************************************************/
-/* SWITCH_CORE :: RxUnicastPkts_P7 :: COUNT [31:00] */
-#define BCHP_SWITCH_CORE_RxUnicastPkts_P7_COUNT_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_RxUnicastPkts_P7_COUNT_SHIFT 0
-#define BCHP_SWITCH_CORE_RxUnicastPkts_P7_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *RxMulticastPkts_P7 - Rx Multicast Packet Counter
- ***************************************************************************/
-/* SWITCH_CORE :: RxMulticastPkts_P7 :: COUNT [31:00] */
-#define BCHP_SWITCH_CORE_RxMulticastPkts_P7_COUNT_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_RxMulticastPkts_P7_COUNT_SHIFT 0
-#define BCHP_SWITCH_CORE_RxMulticastPkts_P7_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *RxBroadcastPkts_P7 - Rx Broadcast Packet Counter
- ***************************************************************************/
-/* SWITCH_CORE :: RxBroadcastPkts_P7 :: COUNT [31:00] */
-#define BCHP_SWITCH_CORE_RxBroadcastPkts_P7_COUNT_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_RxBroadcastPkts_P7_COUNT_SHIFT 0
-#define BCHP_SWITCH_CORE_RxBroadcastPkts_P7_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *RxSAChanges_P7 - Rx SA Change Counter
- ***************************************************************************/
-/* SWITCH_CORE :: RxSAChanges_P7 :: COUNT [31:00] */
-#define BCHP_SWITCH_CORE_RxSAChanges_P7_COUNT_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_RxSAChanges_P7_COUNT_SHIFT 0
-#define BCHP_SWITCH_CORE_RxSAChanges_P7_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *RxFragments_P7 - Rx Fragment Counter
- ***************************************************************************/
-/* SWITCH_CORE :: RxFragments_P7 :: COUNT [31:00] */
-#define BCHP_SWITCH_CORE_RxFragments_P7_COUNT_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_RxFragments_P7_COUNT_SHIFT 0
-#define BCHP_SWITCH_CORE_RxFragments_P7_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *RxJumboPkt_P7 - Jumbo Packet Counter
- ***************************************************************************/
-/* SWITCH_CORE :: RxJumboPkt_P7 :: COUNT [31:00] */
-#define BCHP_SWITCH_CORE_RxJumboPkt_P7_COUNT_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_RxJumboPkt_P7_COUNT_SHIFT 0
-#define BCHP_SWITCH_CORE_RxJumboPkt_P7_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *RxSymblErr_P7 - Rx Symbol Error Counter
- ***************************************************************************/
-/* SWITCH_CORE :: RxSymblErr_P7 :: COUNT [31:00] */
-#define BCHP_SWITCH_CORE_RxSymblErr_P7_COUNT_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_RxSymblErr_P7_COUNT_SHIFT 0
-#define BCHP_SWITCH_CORE_RxSymblErr_P7_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *InRangeErrCount_P7 - InRangeErrCount Counter
- ***************************************************************************/
-/* SWITCH_CORE :: InRangeErrCount_P7 :: COUNT [31:00] */
-#define BCHP_SWITCH_CORE_InRangeErrCount_P7_COUNT_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_InRangeErrCount_P7_COUNT_SHIFT 0
-#define BCHP_SWITCH_CORE_InRangeErrCount_P7_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *OutRangeErrCount_P7 - OutRangeErrCount Counter
- ***************************************************************************/
-/* SWITCH_CORE :: OutRangeErrCount_P7 :: COUNT [31:00] */
-#define BCHP_SWITCH_CORE_OutRangeErrCount_P7_COUNT_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_OutRangeErrCount_P7_COUNT_SHIFT 0
-#define BCHP_SWITCH_CORE_OutRangeErrCount_P7_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *EEE_LPI_EVENT_P7 - EEE Low-Power Idle Event Registers
- ***************************************************************************/
-/* SWITCH_CORE :: EEE_LPI_EVENT_P7 :: COUNT [31:00] */
-#define BCHP_SWITCH_CORE_EEE_LPI_EVENT_P7_COUNT_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_EEE_LPI_EVENT_P7_COUNT_SHIFT 0
-#define BCHP_SWITCH_CORE_EEE_LPI_EVENT_P7_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *EEE_LPI_DURATION_P7 - EEE Low-Power Idle Duration Registers
- ***************************************************************************/
-/* SWITCH_CORE :: EEE_LPI_DURATION_P7 :: COUNT [31:00] */
-#define BCHP_SWITCH_CORE_EEE_LPI_DURATION_P7_COUNT_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_EEE_LPI_DURATION_P7_COUNT_SHIFT 0
-#define BCHP_SWITCH_CORE_EEE_LPI_DURATION_P7_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *RxDiscard_P7 - Rx Discard Counter
- ***************************************************************************/
-/* SWITCH_CORE :: RxDiscard_P7 :: COUNT [31:00] */
-#define BCHP_SWITCH_CORE_RxDiscard_P7_COUNT_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_RxDiscard_P7_COUNT_SHIFT 0
-#define BCHP_SWITCH_CORE_RxDiscard_P7_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *TxQPKTQ6_P7 - Tx Q6 Packet Counter
- ***************************************************************************/
-/* SWITCH_CORE :: TxQPKTQ6_P7 :: COUNT [31:00] */
-#define BCHP_SWITCH_CORE_TxQPKTQ6_P7_COUNT_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_TxQPKTQ6_P7_COUNT_SHIFT 0
-#define BCHP_SWITCH_CORE_TxQPKTQ6_P7_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *TxQPKTQ7_P7 - Tx Q7 Packet Counter
- ***************************************************************************/
-/* SWITCH_CORE :: TxQPKTQ7_P7 :: COUNT [31:00] */
-#define BCHP_SWITCH_CORE_TxQPKTQ7_P7_COUNT_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_TxQPKTQ7_P7_COUNT_SHIFT 0
-#define BCHP_SWITCH_CORE_TxQPKTQ7_P7_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *TxPkts64Octets_P7 - Tx 64 Bytes Octets Counter
- ***************************************************************************/
-/* SWITCH_CORE :: TxPkts64Octets_P7 :: COUNT [31:00] */
-#define BCHP_SWITCH_CORE_TxPkts64Octets_P7_COUNT_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_TxPkts64Octets_P7_COUNT_SHIFT 0
-#define BCHP_SWITCH_CORE_TxPkts64Octets_P7_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *TxPkts65to127Octets_P7 - Tx 65 to 127 Bytes Octets Counter
- ***************************************************************************/
-/* SWITCH_CORE :: TxPkts65to127Octets_P7 :: COUNT [31:00] */
-#define BCHP_SWITCH_CORE_TxPkts65to127Octets_P7_COUNT_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_TxPkts65to127Octets_P7_COUNT_SHIFT 0
-#define BCHP_SWITCH_CORE_TxPkts65to127Octets_P7_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *TxPkts128to255Octets_P7 - Tx 128 to 255 Bytes Octets Counter
- ***************************************************************************/
-/* SWITCH_CORE :: TxPkts128to255Octets_P7 :: COUNT [31:00] */
-#define BCHP_SWITCH_CORE_TxPkts128to255Octets_P7_COUNT_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_TxPkts128to255Octets_P7_COUNT_SHIFT 0
-#define BCHP_SWITCH_CORE_TxPkts128to255Octets_P7_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *TxPkts256to511Octets_P7 - Tx 256 to 511 Bytes Octets Counter
- ***************************************************************************/
-/* SWITCH_CORE :: TxPkts256to511Octets_P7 :: COUNT [31:00] */
-#define BCHP_SWITCH_CORE_TxPkts256to511Octets_P7_COUNT_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_TxPkts256to511Octets_P7_COUNT_SHIFT 0
-#define BCHP_SWITCH_CORE_TxPkts256to511Octets_P7_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *TxPkts512to1023Octets_P7 - Tx 512 to 1023 Bytes Octets Counter
- ***************************************************************************/
-/* SWITCH_CORE :: TxPkts512to1023Octets_P7 :: COUNT [31:00] */
-#define BCHP_SWITCH_CORE_TxPkts512to1023Octets_P7_COUNT_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_TxPkts512to1023Octets_P7_COUNT_SHIFT 0
-#define BCHP_SWITCH_CORE_TxPkts512to1023Octets_P7_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *TxPkts1024toMaxPktOctets_P7 - Tx 1024 to MaxPkt Bytes Octets Counter
- ***************************************************************************/
-/* SWITCH_CORE :: TxPkts1024toMaxPktOctets_P7 :: COUNT [31:00] */
-#define BCHP_SWITCH_CORE_TxPkts1024toMaxPktOctets_P7_COUNT_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_TxPkts1024toMaxPktOctets_P7_COUNT_SHIFT 0
-#define BCHP_SWITCH_CORE_TxPkts1024toMaxPktOctets_P7_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *TxOctets_IMP - Tx Octets
- ***************************************************************************/
-/* SWITCH_CORE :: TxOctets_IMP :: COUNT [63:00] */
-#define BCHP_SWITCH_CORE_TxOctets_IMP_COUNT_MASK 0x00000000ffffffff
-#define BCHP_SWITCH_CORE_TxOctets_IMP_COUNT_SHIFT 0
-#define BCHP_SWITCH_CORE_TxOctets_IMP_COUNT_DEFAULT 0x0000000000000000
-
-/***************************************************************************
- *TxDropPkts_IMP - Tx Drop Packet Counter
- ***************************************************************************/
-/* SWITCH_CORE :: TxDropPkts_IMP :: COUNT [31:00] */
-#define BCHP_SWITCH_CORE_TxDropPkts_IMP_COUNT_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_TxDropPkts_IMP_COUNT_SHIFT 0
-#define BCHP_SWITCH_CORE_TxDropPkts_IMP_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *TxQPKTQ0_IMP - Tx Q0 Packet Counter
- ***************************************************************************/
-/* SWITCH_CORE :: TxQPKTQ0_IMP :: COUNT [31:00] */
-#define BCHP_SWITCH_CORE_TxQPKTQ0_IMP_COUNT_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_TxQPKTQ0_IMP_COUNT_SHIFT 0
-#define BCHP_SWITCH_CORE_TxQPKTQ0_IMP_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *TxBroadcastPkts_IMP - Tx Broadcast Packet Counter
- ***************************************************************************/
-/* SWITCH_CORE :: TxBroadcastPkts_IMP :: COUNT [31:00] */
-#define BCHP_SWITCH_CORE_TxBroadcastPkts_IMP_COUNT_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_TxBroadcastPkts_IMP_COUNT_SHIFT 0
-#define BCHP_SWITCH_CORE_TxBroadcastPkts_IMP_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *TxMulticastPkts_IMP - Tx Multicast Packet Counter
- ***************************************************************************/
-/* SWITCH_CORE :: TxMulticastPkts_IMP :: COUNT [31:00] */
-#define BCHP_SWITCH_CORE_TxMulticastPkts_IMP_COUNT_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_TxMulticastPkts_IMP_COUNT_SHIFT 0
-#define BCHP_SWITCH_CORE_TxMulticastPkts_IMP_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *TxUnicastPkts_IMP - Tx Unicast Packet Counter
- ***************************************************************************/
-/* SWITCH_CORE :: TxUnicastPkts_IMP :: COUNT [31:00] */
-#define BCHP_SWITCH_CORE_TxUnicastPkts_IMP_COUNT_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_TxUnicastPkts_IMP_COUNT_SHIFT 0
-#define BCHP_SWITCH_CORE_TxUnicastPkts_IMP_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *TxCollisions_IMP - Tx Collision Counter
- ***************************************************************************/
-/* SWITCH_CORE :: TxCollisions_IMP :: COUNT [31:00] */
-#define BCHP_SWITCH_CORE_TxCollisions_IMP_COUNT_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_TxCollisions_IMP_COUNT_SHIFT 0
-#define BCHP_SWITCH_CORE_TxCollisions_IMP_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *TxSingleCollision_IMP - Tx Single Collision Counter
- ***************************************************************************/
-/* SWITCH_CORE :: TxSingleCollision_IMP :: COUNT [31:00] */
-#define BCHP_SWITCH_CORE_TxSingleCollision_IMP_COUNT_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_TxSingleCollision_IMP_COUNT_SHIFT 0
-#define BCHP_SWITCH_CORE_TxSingleCollision_IMP_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *TxMultipleCollision_IMP - Tx Multiple collsion Counter
- ***************************************************************************/
-/* SWITCH_CORE :: TxMultipleCollision_IMP :: COUNT [31:00] */
-#define BCHP_SWITCH_CORE_TxMultipleCollision_IMP_COUNT_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_TxMultipleCollision_IMP_COUNT_SHIFT 0
-#define BCHP_SWITCH_CORE_TxMultipleCollision_IMP_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *TxDeferredTransmit_IMP - Tx Deferred Transmit Counter
- ***************************************************************************/
-/* SWITCH_CORE :: TxDeferredTransmit_IMP :: COUNT [31:00] */
-#define BCHP_SWITCH_CORE_TxDeferredTransmit_IMP_COUNT_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_TxDeferredTransmit_IMP_COUNT_SHIFT 0
-#define BCHP_SWITCH_CORE_TxDeferredTransmit_IMP_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *TxLateCollision_IMP - Tx Late Collision Counter
- ***************************************************************************/
-/* SWITCH_CORE :: TxLateCollision_IMP :: COUNT [31:00] */
-#define BCHP_SWITCH_CORE_TxLateCollision_IMP_COUNT_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_TxLateCollision_IMP_COUNT_SHIFT 0
-#define BCHP_SWITCH_CORE_TxLateCollision_IMP_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *TxExcessiveCollision_IMP - Tx Excessive Collision Counter
- ***************************************************************************/
-/* SWITCH_CORE :: TxExcessiveCollision_IMP :: COUNT [31:00] */
-#define BCHP_SWITCH_CORE_TxExcessiveCollision_IMP_COUNT_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_TxExcessiveCollision_IMP_COUNT_SHIFT 0
-#define BCHP_SWITCH_CORE_TxExcessiveCollision_IMP_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *TxFrameInDisc_IMP - Tx Fram IN Disc Counter
- ***************************************************************************/
-/* SWITCH_CORE :: TxFrameInDisc_IMP :: COUNT [31:00] */
-#define BCHP_SWITCH_CORE_TxFrameInDisc_IMP_COUNT_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_TxFrameInDisc_IMP_COUNT_SHIFT 0
-#define BCHP_SWITCH_CORE_TxFrameInDisc_IMP_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *TxPausePkts_IMP - Tx Pause Packet Counter
- ***************************************************************************/
-/* SWITCH_CORE :: TxPausePkts_IMP :: COUNT [31:00] */
-#define BCHP_SWITCH_CORE_TxPausePkts_IMP_COUNT_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_TxPausePkts_IMP_COUNT_SHIFT 0
-#define BCHP_SWITCH_CORE_TxPausePkts_IMP_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *TxQPKTQ1_IMP - Tx Q1 Packet Counter
- ***************************************************************************/
-/* SWITCH_CORE :: TxQPKTQ1_IMP :: COUNT [31:00] */
-#define BCHP_SWITCH_CORE_TxQPKTQ1_IMP_COUNT_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_TxQPKTQ1_IMP_COUNT_SHIFT 0
-#define BCHP_SWITCH_CORE_TxQPKTQ1_IMP_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *TxQPKTQ2_IMP - Tx Q2 Packet Counter
- ***************************************************************************/
-/* SWITCH_CORE :: TxQPKTQ2_IMP :: COUNT [31:00] */
-#define BCHP_SWITCH_CORE_TxQPKTQ2_IMP_COUNT_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_TxQPKTQ2_IMP_COUNT_SHIFT 0
-#define BCHP_SWITCH_CORE_TxQPKTQ2_IMP_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *TxQPKTQ3_IMP - Tx Q3 Packet Counter
- ***************************************************************************/
-/* SWITCH_CORE :: TxQPKTQ3_IMP :: COUNT [31:00] */
-#define BCHP_SWITCH_CORE_TxQPKTQ3_IMP_COUNT_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_TxQPKTQ3_IMP_COUNT_SHIFT 0
-#define BCHP_SWITCH_CORE_TxQPKTQ3_IMP_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *TxQPKTQ4_IMP - Tx Q4 Packet Counter
- ***************************************************************************/
-/* SWITCH_CORE :: TxQPKTQ4_IMP :: COUNT [31:00] */
-#define BCHP_SWITCH_CORE_TxQPKTQ4_IMP_COUNT_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_TxQPKTQ4_IMP_COUNT_SHIFT 0
-#define BCHP_SWITCH_CORE_TxQPKTQ4_IMP_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *TxQPKTQ5_IMP - Tx Q5 Packet Counter
- ***************************************************************************/
-/* SWITCH_CORE :: TxQPKTQ5_IMP :: COUNT [31:00] */
-#define BCHP_SWITCH_CORE_TxQPKTQ5_IMP_COUNT_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_TxQPKTQ5_IMP_COUNT_SHIFT 0
-#define BCHP_SWITCH_CORE_TxQPKTQ5_IMP_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *RxOctets_IMP - Rx Packet Octets Counter
- ***************************************************************************/
-/* SWITCH_CORE :: RxOctets_IMP :: COUNT [63:00] */
-#define BCHP_SWITCH_CORE_RxOctets_IMP_COUNT_MASK 0x00000000ffffffff
-#define BCHP_SWITCH_CORE_RxOctets_IMP_COUNT_SHIFT 0
-#define BCHP_SWITCH_CORE_RxOctets_IMP_COUNT_DEFAULT 0x0000000000000000
-
-/***************************************************************************
- *RxUndersizePkts_IMP - Rx Under Size Packet Octets Counter
- ***************************************************************************/
-/* SWITCH_CORE :: RxUndersizePkts_IMP :: COUNT [31:00] */
-#define BCHP_SWITCH_CORE_RxUndersizePkts_IMP_COUNT_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_RxUndersizePkts_IMP_COUNT_SHIFT 0
-#define BCHP_SWITCH_CORE_RxUndersizePkts_IMP_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *RxPausePkts_IMP - Rx Pause Packet Counter
- ***************************************************************************/
-/* SWITCH_CORE :: RxPausePkts_IMP :: COUNT [31:00] */
-#define BCHP_SWITCH_CORE_RxPausePkts_IMP_COUNT_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_RxPausePkts_IMP_COUNT_SHIFT 0
-#define BCHP_SWITCH_CORE_RxPausePkts_IMP_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *RxPkts64Octets_IMP - Rx 64 Bytes Octets Counter
- ***************************************************************************/
-/* SWITCH_CORE :: RxPkts64Octets_IMP :: COUNT [31:00] */
-#define BCHP_SWITCH_CORE_RxPkts64Octets_IMP_COUNT_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_RxPkts64Octets_IMP_COUNT_SHIFT 0
-#define BCHP_SWITCH_CORE_RxPkts64Octets_IMP_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *RxPkts65to127Octets_IMP - Rx 65 to 127 Bytes Octets Counter
- ***************************************************************************/
-/* SWITCH_CORE :: RxPkts65to127Octets_IMP :: COUNT [31:00] */
-#define BCHP_SWITCH_CORE_RxPkts65to127Octets_IMP_COUNT_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_RxPkts65to127Octets_IMP_COUNT_SHIFT 0
-#define BCHP_SWITCH_CORE_RxPkts65to127Octets_IMP_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *RxPkts128to255Octets_IMP - Rx 128 to 255 Bytes Octets Counter
- ***************************************************************************/
-/* SWITCH_CORE :: RxPkts128to255Octets_IMP :: COUNT [31:00] */
-#define BCHP_SWITCH_CORE_RxPkts128to255Octets_IMP_COUNT_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_RxPkts128to255Octets_IMP_COUNT_SHIFT 0
-#define BCHP_SWITCH_CORE_RxPkts128to255Octets_IMP_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *RxPkts256to511Octets_IMP - Rx 256 to 511 Bytes Octets Counter
- ***************************************************************************/
-/* SWITCH_CORE :: RxPkts256to511Octets_IMP :: COUNT [31:00] */
-#define BCHP_SWITCH_CORE_RxPkts256to511Octets_IMP_COUNT_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_RxPkts256to511Octets_IMP_COUNT_SHIFT 0
-#define BCHP_SWITCH_CORE_RxPkts256to511Octets_IMP_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *RxPkts512to1023Octets_IMP - Rx 512 to 1023 Bytes Octets Counter
- ***************************************************************************/
-/* SWITCH_CORE :: RxPkts512to1023Octets_IMP :: COUNT [31:00] */
-#define BCHP_SWITCH_CORE_RxPkts512to1023Octets_IMP_COUNT_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_RxPkts512to1023Octets_IMP_COUNT_SHIFT 0
-#define BCHP_SWITCH_CORE_RxPkts512to1023Octets_IMP_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *RxPkts1024toMaxPktOctets_IMP - Rx 1024 to MaxPkt Bytes Octets Counter
- ***************************************************************************/
-/* SWITCH_CORE :: RxPkts1024toMaxPktOctets_IMP :: COUNT [31:00] */
-#define BCHP_SWITCH_CORE_RxPkts1024toMaxPktOctets_IMP_COUNT_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_RxPkts1024toMaxPktOctets_IMP_COUNT_SHIFT 0
-#define BCHP_SWITCH_CORE_RxPkts1024toMaxPktOctets_IMP_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *RxOversizePkts_IMP - Rx Over Size Packet Counter
- ***************************************************************************/
-/* SWITCH_CORE :: RxOversizePkts_IMP :: COUNT [31:00] */
-#define BCHP_SWITCH_CORE_RxOversizePkts_IMP_COUNT_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_RxOversizePkts_IMP_COUNT_SHIFT 0
-#define BCHP_SWITCH_CORE_RxOversizePkts_IMP_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *RxJabbers_IMP - Rx Jabber Packet Counter
- ***************************************************************************/
-/* SWITCH_CORE :: RxJabbers_IMP :: COUNT [31:00] */
-#define BCHP_SWITCH_CORE_RxJabbers_IMP_COUNT_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_RxJabbers_IMP_COUNT_SHIFT 0
-#define BCHP_SWITCH_CORE_RxJabbers_IMP_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *RxAlignmentErrors_IMP - Rx Alignment Error Counter
- ***************************************************************************/
-/* SWITCH_CORE :: RxAlignmentErrors_IMP :: COUNT [31:00] */
-#define BCHP_SWITCH_CORE_RxAlignmentErrors_IMP_COUNT_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_RxAlignmentErrors_IMP_COUNT_SHIFT 0
-#define BCHP_SWITCH_CORE_RxAlignmentErrors_IMP_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *RxFCSErrors_IMP - Rx FCS Error Counter
- ***************************************************************************/
-/* SWITCH_CORE :: RxFCSErrors_IMP :: COUNT [31:00] */
-#define BCHP_SWITCH_CORE_RxFCSErrors_IMP_COUNT_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_RxFCSErrors_IMP_COUNT_SHIFT 0
-#define BCHP_SWITCH_CORE_RxFCSErrors_IMP_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *RxGoodOctets_IMP - Rx Good Packet Octet Counter
- ***************************************************************************/
-/* SWITCH_CORE :: RxGoodOctets_IMP :: COUNT [63:00] */
-#define BCHP_SWITCH_CORE_RxGoodOctets_IMP_COUNT_MASK 0x00000000ffffffff
-#define BCHP_SWITCH_CORE_RxGoodOctets_IMP_COUNT_SHIFT 0
-#define BCHP_SWITCH_CORE_RxGoodOctets_IMP_COUNT_DEFAULT 0x0000000000000000
-
-/***************************************************************************
- *RxDropPkts_IMP - Rx Drop Packet Counter
- ***************************************************************************/
-/* SWITCH_CORE :: RxDropPkts_IMP :: COUNT [31:00] */
-#define BCHP_SWITCH_CORE_RxDropPkts_IMP_COUNT_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_RxDropPkts_IMP_COUNT_SHIFT 0
-#define BCHP_SWITCH_CORE_RxDropPkts_IMP_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *RxUnicastPkts_IMP - Rx Unicast Packet Counter
- ***************************************************************************/
-/* SWITCH_CORE :: RxUnicastPkts_IMP :: COUNT [31:00] */
-#define BCHP_SWITCH_CORE_RxUnicastPkts_IMP_COUNT_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_RxUnicastPkts_IMP_COUNT_SHIFT 0
-#define BCHP_SWITCH_CORE_RxUnicastPkts_IMP_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *RxMulticastPkts_IMP - Rx Multicast Packet Counter
- ***************************************************************************/
-/* SWITCH_CORE :: RxMulticastPkts_IMP :: COUNT [31:00] */
-#define BCHP_SWITCH_CORE_RxMulticastPkts_IMP_COUNT_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_RxMulticastPkts_IMP_COUNT_SHIFT 0
-#define BCHP_SWITCH_CORE_RxMulticastPkts_IMP_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *RxBroadcastPkts_IMP - Rx Broadcast Packet Counter
- ***************************************************************************/
-/* SWITCH_CORE :: RxBroadcastPkts_IMP :: COUNT [31:00] */
-#define BCHP_SWITCH_CORE_RxBroadcastPkts_IMP_COUNT_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_RxBroadcastPkts_IMP_COUNT_SHIFT 0
-#define BCHP_SWITCH_CORE_RxBroadcastPkts_IMP_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *RxSAChanges_IMP - Rx SA Change Counter
- ***************************************************************************/
-/* SWITCH_CORE :: RxSAChanges_IMP :: COUNT [31:00] */
-#define BCHP_SWITCH_CORE_RxSAChanges_IMP_COUNT_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_RxSAChanges_IMP_COUNT_SHIFT 0
-#define BCHP_SWITCH_CORE_RxSAChanges_IMP_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *RxFragments_IMP - Rx Fragment Counter
- ***************************************************************************/
-/* SWITCH_CORE :: RxFragments_IMP :: COUNT [31:00] */
-#define BCHP_SWITCH_CORE_RxFragments_IMP_COUNT_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_RxFragments_IMP_COUNT_SHIFT 0
-#define BCHP_SWITCH_CORE_RxFragments_IMP_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *RxJumboPkt_IMP - Jumbo Packet Counter
- ***************************************************************************/
-/* SWITCH_CORE :: RxJumboPkt_IMP :: COUNT [31:00] */
-#define BCHP_SWITCH_CORE_RxJumboPkt_IMP_COUNT_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_RxJumboPkt_IMP_COUNT_SHIFT 0
-#define BCHP_SWITCH_CORE_RxJumboPkt_IMP_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *RxSymblErr_IMP - Rx Symbol Error Counter
- ***************************************************************************/
-/* SWITCH_CORE :: RxSymblErr_IMP :: COUNT [31:00] */
-#define BCHP_SWITCH_CORE_RxSymblErr_IMP_COUNT_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_RxSymblErr_IMP_COUNT_SHIFT 0
-#define BCHP_SWITCH_CORE_RxSymblErr_IMP_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *InRangeErrCount_IMP - InRangeErrCount Counter
- ***************************************************************************/
-/* SWITCH_CORE :: InRangeErrCount_IMP :: COUNT [31:00] */
-#define BCHP_SWITCH_CORE_InRangeErrCount_IMP_COUNT_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_InRangeErrCount_IMP_COUNT_SHIFT 0
-#define BCHP_SWITCH_CORE_InRangeErrCount_IMP_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *OutRangeErrCount_IMP - OutRangeErrCount Counter
- ***************************************************************************/
-/* SWITCH_CORE :: OutRangeErrCount_IMP :: COUNT [31:00] */
-#define BCHP_SWITCH_CORE_OutRangeErrCount_IMP_COUNT_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_OutRangeErrCount_IMP_COUNT_SHIFT 0
-#define BCHP_SWITCH_CORE_OutRangeErrCount_IMP_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *EEE_LPI_EVENT_IMP - EEE Low-Power Idle Event Registers
- ***************************************************************************/
-/* SWITCH_CORE :: EEE_LPI_EVENT_IMP :: COUNT [31:00] */
-#define BCHP_SWITCH_CORE_EEE_LPI_EVENT_IMP_COUNT_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_EEE_LPI_EVENT_IMP_COUNT_SHIFT 0
-#define BCHP_SWITCH_CORE_EEE_LPI_EVENT_IMP_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *EEE_LPI_DURATION_IMP - EEE Low-Power Idle Duration Registers
- ***************************************************************************/
-/* SWITCH_CORE :: EEE_LPI_DURATION_IMP :: COUNT [31:00] */
-#define BCHP_SWITCH_CORE_EEE_LPI_DURATION_IMP_COUNT_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_EEE_LPI_DURATION_IMP_COUNT_SHIFT 0
-#define BCHP_SWITCH_CORE_EEE_LPI_DURATION_IMP_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *RxDiscard_IMP - Rx Discard Counter
- ***************************************************************************/
-/* SWITCH_CORE :: RxDiscard_IMP :: COUNT [31:00] */
-#define BCHP_SWITCH_CORE_RxDiscard_IMP_COUNT_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_RxDiscard_IMP_COUNT_SHIFT 0
-#define BCHP_SWITCH_CORE_RxDiscard_IMP_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *TxQPKTQ6_IMP - Tx Q6 Packet Counter
- ***************************************************************************/
-/* SWITCH_CORE :: TxQPKTQ6_IMP :: COUNT [31:00] */
-#define BCHP_SWITCH_CORE_TxQPKTQ6_IMP_COUNT_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_TxQPKTQ6_IMP_COUNT_SHIFT 0
-#define BCHP_SWITCH_CORE_TxQPKTQ6_IMP_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *TxQPKTQ7_IMP - Tx Q7 Packet Counter
- ***************************************************************************/
-/* SWITCH_CORE :: TxQPKTQ7_IMP :: COUNT [31:00] */
-#define BCHP_SWITCH_CORE_TxQPKTQ7_IMP_COUNT_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_TxQPKTQ7_IMP_COUNT_SHIFT 0
-#define BCHP_SWITCH_CORE_TxQPKTQ7_IMP_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *TxPkts64Octets_IMP - Tx 64 Bytes Octets Counter
- ***************************************************************************/
-/* SWITCH_CORE :: TxPkts64Octets_IMP :: COUNT [31:00] */
-#define BCHP_SWITCH_CORE_TxPkts64Octets_IMP_COUNT_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_TxPkts64Octets_IMP_COUNT_SHIFT 0
-#define BCHP_SWITCH_CORE_TxPkts64Octets_IMP_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *TxPkts65to127Octets_IMP - Tx 65 to 127 Bytes Octets Counter
- ***************************************************************************/
-/* SWITCH_CORE :: TxPkts65to127Octets_IMP :: COUNT [31:00] */
-#define BCHP_SWITCH_CORE_TxPkts65to127Octets_IMP_COUNT_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_TxPkts65to127Octets_IMP_COUNT_SHIFT 0
-#define BCHP_SWITCH_CORE_TxPkts65to127Octets_IMP_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *TxPkts128to255Octets_IMP - Tx 128 to 255 Bytes Octets Counter
- ***************************************************************************/
-/* SWITCH_CORE :: TxPkts128to255Octets_IMP :: COUNT [31:00] */
-#define BCHP_SWITCH_CORE_TxPkts128to255Octets_IMP_COUNT_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_TxPkts128to255Octets_IMP_COUNT_SHIFT 0
-#define BCHP_SWITCH_CORE_TxPkts128to255Octets_IMP_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *TxPkts256to511Octets_IMP - Tx 256 to 511 Bytes Octets Counter
- ***************************************************************************/
-/* SWITCH_CORE :: TxPkts256to511Octets_IMP :: COUNT [31:00] */
-#define BCHP_SWITCH_CORE_TxPkts256to511Octets_IMP_COUNT_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_TxPkts256to511Octets_IMP_COUNT_SHIFT 0
-#define BCHP_SWITCH_CORE_TxPkts256to511Octets_IMP_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *TxPkts512to1023Octets_IMP - Tx 512 to 1023 Bytes Octets Counter
- ***************************************************************************/
-/* SWITCH_CORE :: TxPkts512to1023Octets_IMP :: COUNT [31:00] */
-#define BCHP_SWITCH_CORE_TxPkts512to1023Octets_IMP_COUNT_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_TxPkts512to1023Octets_IMP_COUNT_SHIFT 0
-#define BCHP_SWITCH_CORE_TxPkts512to1023Octets_IMP_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *TxPkts1024toMaxPktOctets_IMP - Tx 1024 to MaxPkt Bytes Octets Counter
- ***************************************************************************/
-/* SWITCH_CORE :: TxPkts1024toMaxPktOctets_IMP :: COUNT [31:00] */
-#define BCHP_SWITCH_CORE_TxPkts1024toMaxPktOctets_IMP_COUNT_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_TxPkts1024toMaxPktOctets_IMP_COUNT_SHIFT 0
-#define BCHP_SWITCH_CORE_TxPkts1024toMaxPktOctets_IMP_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *QOS_GLOBAL_CTRL - QOS Global Control Register
- ***************************************************************************/
-/* SWITCH_CORE :: QOS_GLOBAL_CTRL :: reserved_for_padding0 [31:08] */
-#define BCHP_SWITCH_CORE_QOS_GLOBAL_CTRL_reserved_for_padding0_MASK 0xffffff00
-#define BCHP_SWITCH_CORE_QOS_GLOBAL_CTRL_reserved_for_padding0_SHIFT 8
-
-/* SWITCH_CORE :: QOS_GLOBAL_CTRL :: P8_AGGREGATION_MODE [07:07] */
-#define BCHP_SWITCH_CORE_QOS_GLOBAL_CTRL_P8_AGGREGATION_MODE_MASK 0x00000080
-#define BCHP_SWITCH_CORE_QOS_GLOBAL_CTRL_P8_AGGREGATION_MODE_SHIFT 7
-#define BCHP_SWITCH_CORE_QOS_GLOBAL_CTRL_P8_AGGREGATION_MODE_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: QOS_GLOBAL_CTRL :: SWITCH_RESV_1 [06:05] */
-#define BCHP_SWITCH_CORE_QOS_GLOBAL_CTRL_SWITCH_RESV_1_MASK 0x00000060
-#define BCHP_SWITCH_CORE_QOS_GLOBAL_CTRL_SWITCH_RESV_1_SHIFT 5
-#define BCHP_SWITCH_CORE_QOS_GLOBAL_CTRL_SWITCH_RESV_1_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: QOS_GLOBAL_CTRL :: P5_AGGREGATION_MODE [04:04] */
-#define BCHP_SWITCH_CORE_QOS_GLOBAL_CTRL_P5_AGGREGATION_MODE_MASK 0x00000010
-#define BCHP_SWITCH_CORE_QOS_GLOBAL_CTRL_P5_AGGREGATION_MODE_SHIFT 4
-#define BCHP_SWITCH_CORE_QOS_GLOBAL_CTRL_P5_AGGREGATION_MODE_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: QOS_GLOBAL_CTRL :: SWITCH_RESV_0 [03:00] */
-#define BCHP_SWITCH_CORE_QOS_GLOBAL_CTRL_SWITCH_RESV_0_MASK 0x0000000f
-#define BCHP_SWITCH_CORE_QOS_GLOBAL_CTRL_SWITCH_RESV_0_SHIFT 0
-#define BCHP_SWITCH_CORE_QOS_GLOBAL_CTRL_SWITCH_RESV_0_DEFAULT 0x00000000
-
-/***************************************************************************
- *QOS_1P_EN - QoS 802.1P Enable Register
- ***************************************************************************/
-/* SWITCH_CORE :: QOS_1P_EN :: reserved_for_padding0 [31:16] */
-#define BCHP_SWITCH_CORE_QOS_1P_EN_reserved_for_padding0_MASK 0xffff0000
-#define BCHP_SWITCH_CORE_QOS_1P_EN_reserved_for_padding0_SHIFT 16
-
-/* SWITCH_CORE :: QOS_1P_EN :: SWITCH_RESV [15:09] */
-#define BCHP_SWITCH_CORE_QOS_1P_EN_SWITCH_RESV_MASK 0x0000fe00
-#define BCHP_SWITCH_CORE_QOS_1P_EN_SWITCH_RESV_SHIFT 9
-#define BCHP_SWITCH_CORE_QOS_1P_EN_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: QOS_1P_EN :: QOS_1P_EN [08:00] */
-#define BCHP_SWITCH_CORE_QOS_1P_EN_QOS_1P_EN_MASK 0x000001ff
-#define BCHP_SWITCH_CORE_QOS_1P_EN_QOS_1P_EN_SHIFT 0
-#define BCHP_SWITCH_CORE_QOS_1P_EN_QOS_1P_EN_DEFAULT 0x00000000
-
-/***************************************************************************
- *QOS_EN_DIFFSERV - QOS DiffServ Enable Register
- ***************************************************************************/
-/* SWITCH_CORE :: QOS_EN_DIFFSERV :: reserved_for_padding0 [31:16] */
-#define BCHP_SWITCH_CORE_QOS_EN_DIFFSERV_reserved_for_padding0_MASK 0xffff0000
-#define BCHP_SWITCH_CORE_QOS_EN_DIFFSERV_reserved_for_padding0_SHIFT 16
-
-/* SWITCH_CORE :: QOS_EN_DIFFSERV :: SWITCH_RESV [15:09] */
-#define BCHP_SWITCH_CORE_QOS_EN_DIFFSERV_SWITCH_RESV_MASK 0x0000fe00
-#define BCHP_SWITCH_CORE_QOS_EN_DIFFSERV_SWITCH_RESV_SHIFT 9
-#define BCHP_SWITCH_CORE_QOS_EN_DIFFSERV_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: QOS_EN_DIFFSERV :: QOS_EN_DIFFSERV [08:00] */
-#define BCHP_SWITCH_CORE_QOS_EN_DIFFSERV_QOS_EN_DIFFSERV_MASK 0x000001ff
-#define BCHP_SWITCH_CORE_QOS_EN_DIFFSERV_QOS_EN_DIFFSERV_SHIFT 0
-#define BCHP_SWITCH_CORE_QOS_EN_DIFFSERV_QOS_EN_DIFFSERV_DEFAULT 0x00000000
-
-/***************************************************************************
- *PN_PCP2TC_DEI0_Port_0 - Port N PCP to TC Map for DEI 0 Register
- ***************************************************************************/
-/* SWITCH_CORE :: PN_PCP2TC_DEI0_Port_0 :: SWITCH_RESV [31:24] */
-#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI0_Port_0_SWITCH_RESV_MASK 0xff000000
-#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI0_Port_0_SWITCH_RESV_SHIFT 24
-#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI0_Port_0_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: PN_PCP2TC_DEI0_Port_0 :: TAG111_PRI_MAP [23:21] */
-#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI0_Port_0_TAG111_PRI_MAP_MASK 0x00e00000
-#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI0_Port_0_TAG111_PRI_MAP_SHIFT 21
-#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI0_Port_0_TAG111_PRI_MAP_DEFAULT 0x00000007
-
-/* SWITCH_CORE :: PN_PCP2TC_DEI0_Port_0 :: TAG110_PRI_MAP [20:18] */
-#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI0_Port_0_TAG110_PRI_MAP_MASK 0x001c0000
-#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI0_Port_0_TAG110_PRI_MAP_SHIFT 18
-#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI0_Port_0_TAG110_PRI_MAP_DEFAULT 0x00000006
-
-/* SWITCH_CORE :: PN_PCP2TC_DEI0_Port_0 :: TAG101_PRI_MAP [17:15] */
-#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI0_Port_0_TAG101_PRI_MAP_MASK 0x00038000
-#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI0_Port_0_TAG101_PRI_MAP_SHIFT 15
-#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI0_Port_0_TAG101_PRI_MAP_DEFAULT 0x00000005
-
-/* SWITCH_CORE :: PN_PCP2TC_DEI0_Port_0 :: TAG100_PRI_MAP [14:12] */
-#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI0_Port_0_TAG100_PRI_MAP_MASK 0x00007000
-#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI0_Port_0_TAG100_PRI_MAP_SHIFT 12
-#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI0_Port_0_TAG100_PRI_MAP_DEFAULT 0x00000004
-
-/* SWITCH_CORE :: PN_PCP2TC_DEI0_Port_0 :: TAG011_PRI_MAP [11:09] */
-#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI0_Port_0_TAG011_PRI_MAP_MASK 0x00000e00
-#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI0_Port_0_TAG011_PRI_MAP_SHIFT 9
-#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI0_Port_0_TAG011_PRI_MAP_DEFAULT 0x00000003
-
-/* SWITCH_CORE :: PN_PCP2TC_DEI0_Port_0 :: TAG010_PRI_MAP [08:06] */
-#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI0_Port_0_TAG010_PRI_MAP_MASK 0x000001c0
-#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI0_Port_0_TAG010_PRI_MAP_SHIFT 6
-#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI0_Port_0_TAG010_PRI_MAP_DEFAULT 0x00000002
-
-/* SWITCH_CORE :: PN_PCP2TC_DEI0_Port_0 :: TAG001_PRI_MAP [05:03] */
-#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI0_Port_0_TAG001_PRI_MAP_MASK 0x00000038
-#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI0_Port_0_TAG001_PRI_MAP_SHIFT 3
-#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI0_Port_0_TAG001_PRI_MAP_DEFAULT 0x00000001
-
-/* SWITCH_CORE :: PN_PCP2TC_DEI0_Port_0 :: TAG000_PRI_MAP [02:00] */
-#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI0_Port_0_TAG000_PRI_MAP_MASK 0x00000007
-#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI0_Port_0_TAG000_PRI_MAP_SHIFT 0
-#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI0_Port_0_TAG000_PRI_MAP_DEFAULT 0x00000000
-
-/***************************************************************************
- *PN_PCP2TC_DEI0_Port_1 - Port N PCP to TC Map for DEI 0 Register
- ***************************************************************************/
-/* SWITCH_CORE :: PN_PCP2TC_DEI0_Port_1 :: SWITCH_RESV [31:24] */
-#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI0_Port_1_SWITCH_RESV_MASK 0xff000000
-#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI0_Port_1_SWITCH_RESV_SHIFT 24
-#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI0_Port_1_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: PN_PCP2TC_DEI0_Port_1 :: TAG111_PRI_MAP [23:21] */
-#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI0_Port_1_TAG111_PRI_MAP_MASK 0x00e00000
-#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI0_Port_1_TAG111_PRI_MAP_SHIFT 21
-#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI0_Port_1_TAG111_PRI_MAP_DEFAULT 0x00000007
-
-/* SWITCH_CORE :: PN_PCP2TC_DEI0_Port_1 :: TAG110_PRI_MAP [20:18] */
-#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI0_Port_1_TAG110_PRI_MAP_MASK 0x001c0000
-#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI0_Port_1_TAG110_PRI_MAP_SHIFT 18
-#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI0_Port_1_TAG110_PRI_MAP_DEFAULT 0x00000006
-
-/* SWITCH_CORE :: PN_PCP2TC_DEI0_Port_1 :: TAG101_PRI_MAP [17:15] */
-#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI0_Port_1_TAG101_PRI_MAP_MASK 0x00038000
-#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI0_Port_1_TAG101_PRI_MAP_SHIFT 15
-#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI0_Port_1_TAG101_PRI_MAP_DEFAULT 0x00000005
-
-/* SWITCH_CORE :: PN_PCP2TC_DEI0_Port_1 :: TAG100_PRI_MAP [14:12] */
-#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI0_Port_1_TAG100_PRI_MAP_MASK 0x00007000
-#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI0_Port_1_TAG100_PRI_MAP_SHIFT 12
-#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI0_Port_1_TAG100_PRI_MAP_DEFAULT 0x00000004
-
-/* SWITCH_CORE :: PN_PCP2TC_DEI0_Port_1 :: TAG011_PRI_MAP [11:09] */
-#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI0_Port_1_TAG011_PRI_MAP_MASK 0x00000e00
-#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI0_Port_1_TAG011_PRI_MAP_SHIFT 9
-#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI0_Port_1_TAG011_PRI_MAP_DEFAULT 0x00000003
-
-/* SWITCH_CORE :: PN_PCP2TC_DEI0_Port_1 :: TAG010_PRI_MAP [08:06] */
-#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI0_Port_1_TAG010_PRI_MAP_MASK 0x000001c0
-#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI0_Port_1_TAG010_PRI_MAP_SHIFT 6
-#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI0_Port_1_TAG010_PRI_MAP_DEFAULT 0x00000002
-
-/* SWITCH_CORE :: PN_PCP2TC_DEI0_Port_1 :: TAG001_PRI_MAP [05:03] */
-#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI0_Port_1_TAG001_PRI_MAP_MASK 0x00000038
-#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI0_Port_1_TAG001_PRI_MAP_SHIFT 3
-#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI0_Port_1_TAG001_PRI_MAP_DEFAULT 0x00000001
-
-/* SWITCH_CORE :: PN_PCP2TC_DEI0_Port_1 :: TAG000_PRI_MAP [02:00] */
-#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI0_Port_1_TAG000_PRI_MAP_MASK 0x00000007
-#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI0_Port_1_TAG000_PRI_MAP_SHIFT 0
-#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI0_Port_1_TAG000_PRI_MAP_DEFAULT 0x00000000
-
-/***************************************************************************
- *PN_PCP2TC_DEI0_Port_2 - Port N PCP to TC Map for DEI 0 Register
- ***************************************************************************/
-/* SWITCH_CORE :: PN_PCP2TC_DEI0_Port_2 :: SWITCH_RESV [31:24] */
-#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI0_Port_2_SWITCH_RESV_MASK 0xff000000
-#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI0_Port_2_SWITCH_RESV_SHIFT 24
-#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI0_Port_2_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: PN_PCP2TC_DEI0_Port_2 :: TAG111_PRI_MAP [23:21] */
-#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI0_Port_2_TAG111_PRI_MAP_MASK 0x00e00000
-#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI0_Port_2_TAG111_PRI_MAP_SHIFT 21
-#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI0_Port_2_TAG111_PRI_MAP_DEFAULT 0x00000007
-
-/* SWITCH_CORE :: PN_PCP2TC_DEI0_Port_2 :: TAG110_PRI_MAP [20:18] */
-#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI0_Port_2_TAG110_PRI_MAP_MASK 0x001c0000
-#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI0_Port_2_TAG110_PRI_MAP_SHIFT 18
-#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI0_Port_2_TAG110_PRI_MAP_DEFAULT 0x00000006
-
-/* SWITCH_CORE :: PN_PCP2TC_DEI0_Port_2 :: TAG101_PRI_MAP [17:15] */
-#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI0_Port_2_TAG101_PRI_MAP_MASK 0x00038000
-#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI0_Port_2_TAG101_PRI_MAP_SHIFT 15
-#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI0_Port_2_TAG101_PRI_MAP_DEFAULT 0x00000005
-
-/* SWITCH_CORE :: PN_PCP2TC_DEI0_Port_2 :: TAG100_PRI_MAP [14:12] */
-#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI0_Port_2_TAG100_PRI_MAP_MASK 0x00007000
-#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI0_Port_2_TAG100_PRI_MAP_SHIFT 12
-#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI0_Port_2_TAG100_PRI_MAP_DEFAULT 0x00000004
-
-/* SWITCH_CORE :: PN_PCP2TC_DEI0_Port_2 :: TAG011_PRI_MAP [11:09] */
-#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI0_Port_2_TAG011_PRI_MAP_MASK 0x00000e00
-#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI0_Port_2_TAG011_PRI_MAP_SHIFT 9
-#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI0_Port_2_TAG011_PRI_MAP_DEFAULT 0x00000003
-
-/* SWITCH_CORE :: PN_PCP2TC_DEI0_Port_2 :: TAG010_PRI_MAP [08:06] */
-#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI0_Port_2_TAG010_PRI_MAP_MASK 0x000001c0
-#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI0_Port_2_TAG010_PRI_MAP_SHIFT 6
-#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI0_Port_2_TAG010_PRI_MAP_DEFAULT 0x00000002
-
-/* SWITCH_CORE :: PN_PCP2TC_DEI0_Port_2 :: TAG001_PRI_MAP [05:03] */
-#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI0_Port_2_TAG001_PRI_MAP_MASK 0x00000038
-#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI0_Port_2_TAG001_PRI_MAP_SHIFT 3
-#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI0_Port_2_TAG001_PRI_MAP_DEFAULT 0x00000001
-
-/* SWITCH_CORE :: PN_PCP2TC_DEI0_Port_2 :: TAG000_PRI_MAP [02:00] */
-#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI0_Port_2_TAG000_PRI_MAP_MASK 0x00000007
-#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI0_Port_2_TAG000_PRI_MAP_SHIFT 0
-#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI0_Port_2_TAG000_PRI_MAP_DEFAULT 0x00000000
-
-/***************************************************************************
- *PN_PCP2TC_DEI0_Port_3 - Port N PCP to TC Map for DEI 0 Register
- ***************************************************************************/
-/* SWITCH_CORE :: PN_PCP2TC_DEI0_Port_3 :: SWITCH_RESV [31:24] */
-#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI0_Port_3_SWITCH_RESV_MASK 0xff000000
-#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI0_Port_3_SWITCH_RESV_SHIFT 24
-#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI0_Port_3_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: PN_PCP2TC_DEI0_Port_3 :: TAG111_PRI_MAP [23:21] */
-#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI0_Port_3_TAG111_PRI_MAP_MASK 0x00e00000
-#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI0_Port_3_TAG111_PRI_MAP_SHIFT 21
-#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI0_Port_3_TAG111_PRI_MAP_DEFAULT 0x00000007
-
-/* SWITCH_CORE :: PN_PCP2TC_DEI0_Port_3 :: TAG110_PRI_MAP [20:18] */
-#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI0_Port_3_TAG110_PRI_MAP_MASK 0x001c0000
-#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI0_Port_3_TAG110_PRI_MAP_SHIFT 18
-#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI0_Port_3_TAG110_PRI_MAP_DEFAULT 0x00000006
-
-/* SWITCH_CORE :: PN_PCP2TC_DEI0_Port_3 :: TAG101_PRI_MAP [17:15] */
-#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI0_Port_3_TAG101_PRI_MAP_MASK 0x00038000
-#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI0_Port_3_TAG101_PRI_MAP_SHIFT 15
-#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI0_Port_3_TAG101_PRI_MAP_DEFAULT 0x00000005
-
-/* SWITCH_CORE :: PN_PCP2TC_DEI0_Port_3 :: TAG100_PRI_MAP [14:12] */
-#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI0_Port_3_TAG100_PRI_MAP_MASK 0x00007000
-#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI0_Port_3_TAG100_PRI_MAP_SHIFT 12
-#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI0_Port_3_TAG100_PRI_MAP_DEFAULT 0x00000004
-
-/* SWITCH_CORE :: PN_PCP2TC_DEI0_Port_3 :: TAG011_PRI_MAP [11:09] */
-#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI0_Port_3_TAG011_PRI_MAP_MASK 0x00000e00
-#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI0_Port_3_TAG011_PRI_MAP_SHIFT 9
-#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI0_Port_3_TAG011_PRI_MAP_DEFAULT 0x00000003
-
-/* SWITCH_CORE :: PN_PCP2TC_DEI0_Port_3 :: TAG010_PRI_MAP [08:06] */
-#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI0_Port_3_TAG010_PRI_MAP_MASK 0x000001c0
-#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI0_Port_3_TAG010_PRI_MAP_SHIFT 6
-#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI0_Port_3_TAG010_PRI_MAP_DEFAULT 0x00000002
-
-/* SWITCH_CORE :: PN_PCP2TC_DEI0_Port_3 :: TAG001_PRI_MAP [05:03] */
-#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI0_Port_3_TAG001_PRI_MAP_MASK 0x00000038
-#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI0_Port_3_TAG001_PRI_MAP_SHIFT 3
-#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI0_Port_3_TAG001_PRI_MAP_DEFAULT 0x00000001
-
-/* SWITCH_CORE :: PN_PCP2TC_DEI0_Port_3 :: TAG000_PRI_MAP [02:00] */
-#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI0_Port_3_TAG000_PRI_MAP_MASK 0x00000007
-#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI0_Port_3_TAG000_PRI_MAP_SHIFT 0
-#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI0_Port_3_TAG000_PRI_MAP_DEFAULT 0x00000000
-
-/***************************************************************************
- *PN_PCP2TC_DEI0_Port_4 - Port N PCP to TC Map for DEI 0 Register
- ***************************************************************************/
-/* SWITCH_CORE :: PN_PCP2TC_DEI0_Port_4 :: SWITCH_RESV [31:24] */
-#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI0_Port_4_SWITCH_RESV_MASK 0xff000000
-#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI0_Port_4_SWITCH_RESV_SHIFT 24
-#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI0_Port_4_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: PN_PCP2TC_DEI0_Port_4 :: TAG111_PRI_MAP [23:21] */
-#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI0_Port_4_TAG111_PRI_MAP_MASK 0x00e00000
-#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI0_Port_4_TAG111_PRI_MAP_SHIFT 21
-#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI0_Port_4_TAG111_PRI_MAP_DEFAULT 0x00000007
-
-/* SWITCH_CORE :: PN_PCP2TC_DEI0_Port_4 :: TAG110_PRI_MAP [20:18] */
-#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI0_Port_4_TAG110_PRI_MAP_MASK 0x001c0000
-#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI0_Port_4_TAG110_PRI_MAP_SHIFT 18
-#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI0_Port_4_TAG110_PRI_MAP_DEFAULT 0x00000006
-
-/* SWITCH_CORE :: PN_PCP2TC_DEI0_Port_4 :: TAG101_PRI_MAP [17:15] */
-#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI0_Port_4_TAG101_PRI_MAP_MASK 0x00038000
-#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI0_Port_4_TAG101_PRI_MAP_SHIFT 15
-#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI0_Port_4_TAG101_PRI_MAP_DEFAULT 0x00000005
-
-/* SWITCH_CORE :: PN_PCP2TC_DEI0_Port_4 :: TAG100_PRI_MAP [14:12] */
-#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI0_Port_4_TAG100_PRI_MAP_MASK 0x00007000
-#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI0_Port_4_TAG100_PRI_MAP_SHIFT 12
-#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI0_Port_4_TAG100_PRI_MAP_DEFAULT 0x00000004
-
-/* SWITCH_CORE :: PN_PCP2TC_DEI0_Port_4 :: TAG011_PRI_MAP [11:09] */
-#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI0_Port_4_TAG011_PRI_MAP_MASK 0x00000e00
-#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI0_Port_4_TAG011_PRI_MAP_SHIFT 9
-#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI0_Port_4_TAG011_PRI_MAP_DEFAULT 0x00000003
-
-/* SWITCH_CORE :: PN_PCP2TC_DEI0_Port_4 :: TAG010_PRI_MAP [08:06] */
-#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI0_Port_4_TAG010_PRI_MAP_MASK 0x000001c0
-#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI0_Port_4_TAG010_PRI_MAP_SHIFT 6
-#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI0_Port_4_TAG010_PRI_MAP_DEFAULT 0x00000002
-
-/* SWITCH_CORE :: PN_PCP2TC_DEI0_Port_4 :: TAG001_PRI_MAP [05:03] */
-#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI0_Port_4_TAG001_PRI_MAP_MASK 0x00000038
-#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI0_Port_4_TAG001_PRI_MAP_SHIFT 3
-#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI0_Port_4_TAG001_PRI_MAP_DEFAULT 0x00000001
-
-/* SWITCH_CORE :: PN_PCP2TC_DEI0_Port_4 :: TAG000_PRI_MAP [02:00] */
-#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI0_Port_4_TAG000_PRI_MAP_MASK 0x00000007
-#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI0_Port_4_TAG000_PRI_MAP_SHIFT 0
-#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI0_Port_4_TAG000_PRI_MAP_DEFAULT 0x00000000
-
-/***************************************************************************
- *PN_PCP2TC_DEI0_Port_5 - Port N PCP to TC Map for DEI 0 Register
- ***************************************************************************/
-/* SWITCH_CORE :: PN_PCP2TC_DEI0_Port_5 :: SWITCH_RESV [31:24] */
-#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI0_Port_5_SWITCH_RESV_MASK 0xff000000
-#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI0_Port_5_SWITCH_RESV_SHIFT 24
-#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI0_Port_5_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: PN_PCP2TC_DEI0_Port_5 :: TAG111_PRI_MAP [23:21] */
-#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI0_Port_5_TAG111_PRI_MAP_MASK 0x00e00000
-#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI0_Port_5_TAG111_PRI_MAP_SHIFT 21
-#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI0_Port_5_TAG111_PRI_MAP_DEFAULT 0x00000007
-
-/* SWITCH_CORE :: PN_PCP2TC_DEI0_Port_5 :: TAG110_PRI_MAP [20:18] */
-#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI0_Port_5_TAG110_PRI_MAP_MASK 0x001c0000
-#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI0_Port_5_TAG110_PRI_MAP_SHIFT 18
-#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI0_Port_5_TAG110_PRI_MAP_DEFAULT 0x00000006
-
-/* SWITCH_CORE :: PN_PCP2TC_DEI0_Port_5 :: TAG101_PRI_MAP [17:15] */
-#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI0_Port_5_TAG101_PRI_MAP_MASK 0x00038000
-#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI0_Port_5_TAG101_PRI_MAP_SHIFT 15
-#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI0_Port_5_TAG101_PRI_MAP_DEFAULT 0x00000005
-
-/* SWITCH_CORE :: PN_PCP2TC_DEI0_Port_5 :: TAG100_PRI_MAP [14:12] */
-#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI0_Port_5_TAG100_PRI_MAP_MASK 0x00007000
-#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI0_Port_5_TAG100_PRI_MAP_SHIFT 12
-#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI0_Port_5_TAG100_PRI_MAP_DEFAULT 0x00000004
-
-/* SWITCH_CORE :: PN_PCP2TC_DEI0_Port_5 :: TAG011_PRI_MAP [11:09] */
-#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI0_Port_5_TAG011_PRI_MAP_MASK 0x00000e00
-#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI0_Port_5_TAG011_PRI_MAP_SHIFT 9
-#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI0_Port_5_TAG011_PRI_MAP_DEFAULT 0x00000003
-
-/* SWITCH_CORE :: PN_PCP2TC_DEI0_Port_5 :: TAG010_PRI_MAP [08:06] */
-#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI0_Port_5_TAG010_PRI_MAP_MASK 0x000001c0
-#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI0_Port_5_TAG010_PRI_MAP_SHIFT 6
-#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI0_Port_5_TAG010_PRI_MAP_DEFAULT 0x00000002
-
-/* SWITCH_CORE :: PN_PCP2TC_DEI0_Port_5 :: TAG001_PRI_MAP [05:03] */
-#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI0_Port_5_TAG001_PRI_MAP_MASK 0x00000038
-#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI0_Port_5_TAG001_PRI_MAP_SHIFT 3
-#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI0_Port_5_TAG001_PRI_MAP_DEFAULT 0x00000001
-
-/* SWITCH_CORE :: PN_PCP2TC_DEI0_Port_5 :: TAG000_PRI_MAP [02:00] */
-#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI0_Port_5_TAG000_PRI_MAP_MASK 0x00000007
-#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI0_Port_5_TAG000_PRI_MAP_SHIFT 0
-#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI0_Port_5_TAG000_PRI_MAP_DEFAULT 0x00000000
-
-/***************************************************************************
- *P7_PCP2TC_DEI0 - Port 7 PCP to TC Map for DEI 0 Register
- ***************************************************************************/
-/* SWITCH_CORE :: P7_PCP2TC_DEI0 :: SWITCH_RESV [31:24] */
-#define BCHP_SWITCH_CORE_P7_PCP2TC_DEI0_SWITCH_RESV_MASK 0xff000000
-#define BCHP_SWITCH_CORE_P7_PCP2TC_DEI0_SWITCH_RESV_SHIFT 24
-#define BCHP_SWITCH_CORE_P7_PCP2TC_DEI0_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: P7_PCP2TC_DEI0 :: TAG111_PRI_MAP [23:21] */
-#define BCHP_SWITCH_CORE_P7_PCP2TC_DEI0_TAG111_PRI_MAP_MASK 0x00e00000
-#define BCHP_SWITCH_CORE_P7_PCP2TC_DEI0_TAG111_PRI_MAP_SHIFT 21
-#define BCHP_SWITCH_CORE_P7_PCP2TC_DEI0_TAG111_PRI_MAP_DEFAULT 0x00000007
-
-/* SWITCH_CORE :: P7_PCP2TC_DEI0 :: TAG110_PRI_MAP [20:18] */
-#define BCHP_SWITCH_CORE_P7_PCP2TC_DEI0_TAG110_PRI_MAP_MASK 0x001c0000
-#define BCHP_SWITCH_CORE_P7_PCP2TC_DEI0_TAG110_PRI_MAP_SHIFT 18
-#define BCHP_SWITCH_CORE_P7_PCP2TC_DEI0_TAG110_PRI_MAP_DEFAULT 0x00000006
-
-/* SWITCH_CORE :: P7_PCP2TC_DEI0 :: TAG101_PRI_MAP [17:15] */
-#define BCHP_SWITCH_CORE_P7_PCP2TC_DEI0_TAG101_PRI_MAP_MASK 0x00038000
-#define BCHP_SWITCH_CORE_P7_PCP2TC_DEI0_TAG101_PRI_MAP_SHIFT 15
-#define BCHP_SWITCH_CORE_P7_PCP2TC_DEI0_TAG101_PRI_MAP_DEFAULT 0x00000005
-
-/* SWITCH_CORE :: P7_PCP2TC_DEI0 :: TAG100_PRI_MAP [14:12] */
-#define BCHP_SWITCH_CORE_P7_PCP2TC_DEI0_TAG100_PRI_MAP_MASK 0x00007000
-#define BCHP_SWITCH_CORE_P7_PCP2TC_DEI0_TAG100_PRI_MAP_SHIFT 12
-#define BCHP_SWITCH_CORE_P7_PCP2TC_DEI0_TAG100_PRI_MAP_DEFAULT 0x00000004
-
-/* SWITCH_CORE :: P7_PCP2TC_DEI0 :: TAG011_PRI_MAP [11:09] */
-#define BCHP_SWITCH_CORE_P7_PCP2TC_DEI0_TAG011_PRI_MAP_MASK 0x00000e00
-#define BCHP_SWITCH_CORE_P7_PCP2TC_DEI0_TAG011_PRI_MAP_SHIFT 9
-#define BCHP_SWITCH_CORE_P7_PCP2TC_DEI0_TAG011_PRI_MAP_DEFAULT 0x00000003
-
-/* SWITCH_CORE :: P7_PCP2TC_DEI0 :: TAG010_PRI_MAP [08:06] */
-#define BCHP_SWITCH_CORE_P7_PCP2TC_DEI0_TAG010_PRI_MAP_MASK 0x000001c0
-#define BCHP_SWITCH_CORE_P7_PCP2TC_DEI0_TAG010_PRI_MAP_SHIFT 6
-#define BCHP_SWITCH_CORE_P7_PCP2TC_DEI0_TAG010_PRI_MAP_DEFAULT 0x00000002
-
-/* SWITCH_CORE :: P7_PCP2TC_DEI0 :: TAG001_PRI_MAP [05:03] */
-#define BCHP_SWITCH_CORE_P7_PCP2TC_DEI0_TAG001_PRI_MAP_MASK 0x00000038
-#define BCHP_SWITCH_CORE_P7_PCP2TC_DEI0_TAG001_PRI_MAP_SHIFT 3
-#define BCHP_SWITCH_CORE_P7_PCP2TC_DEI0_TAG001_PRI_MAP_DEFAULT 0x00000001
-
-/* SWITCH_CORE :: P7_PCP2TC_DEI0 :: TAG000_PRI_MAP [02:00] */
-#define BCHP_SWITCH_CORE_P7_PCP2TC_DEI0_TAG000_PRI_MAP_MASK 0x00000007
-#define BCHP_SWITCH_CORE_P7_PCP2TC_DEI0_TAG000_PRI_MAP_SHIFT 0
-#define BCHP_SWITCH_CORE_P7_PCP2TC_DEI0_TAG000_PRI_MAP_DEFAULT 0x00000000
-
-/***************************************************************************
- *IMP_PCP2TC_DEI0 - Port 8 (IMP) PCP to TC Map for DEI 0 Register
- ***************************************************************************/
-/* SWITCH_CORE :: IMP_PCP2TC_DEI0 :: SWITCH_RESV [31:24] */
-#define BCHP_SWITCH_CORE_IMP_PCP2TC_DEI0_SWITCH_RESV_MASK 0xff000000
-#define BCHP_SWITCH_CORE_IMP_PCP2TC_DEI0_SWITCH_RESV_SHIFT 24
-#define BCHP_SWITCH_CORE_IMP_PCP2TC_DEI0_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: IMP_PCP2TC_DEI0 :: TAG111_PRI_MAP [23:21] */
-#define BCHP_SWITCH_CORE_IMP_PCP2TC_DEI0_TAG111_PRI_MAP_MASK 0x00e00000
-#define BCHP_SWITCH_CORE_IMP_PCP2TC_DEI0_TAG111_PRI_MAP_SHIFT 21
-#define BCHP_SWITCH_CORE_IMP_PCP2TC_DEI0_TAG111_PRI_MAP_DEFAULT 0x00000007
-
-/* SWITCH_CORE :: IMP_PCP2TC_DEI0 :: TAG110_PRI_MAP [20:18] */
-#define BCHP_SWITCH_CORE_IMP_PCP2TC_DEI0_TAG110_PRI_MAP_MASK 0x001c0000
-#define BCHP_SWITCH_CORE_IMP_PCP2TC_DEI0_TAG110_PRI_MAP_SHIFT 18
-#define BCHP_SWITCH_CORE_IMP_PCP2TC_DEI0_TAG110_PRI_MAP_DEFAULT 0x00000006
-
-/* SWITCH_CORE :: IMP_PCP2TC_DEI0 :: TAG101_PRI_MAP [17:15] */
-#define BCHP_SWITCH_CORE_IMP_PCP2TC_DEI0_TAG101_PRI_MAP_MASK 0x00038000
-#define BCHP_SWITCH_CORE_IMP_PCP2TC_DEI0_TAG101_PRI_MAP_SHIFT 15
-#define BCHP_SWITCH_CORE_IMP_PCP2TC_DEI0_TAG101_PRI_MAP_DEFAULT 0x00000005
-
-/* SWITCH_CORE :: IMP_PCP2TC_DEI0 :: TAG100_PRI_MAP [14:12] */
-#define BCHP_SWITCH_CORE_IMP_PCP2TC_DEI0_TAG100_PRI_MAP_MASK 0x00007000
-#define BCHP_SWITCH_CORE_IMP_PCP2TC_DEI0_TAG100_PRI_MAP_SHIFT 12
-#define BCHP_SWITCH_CORE_IMP_PCP2TC_DEI0_TAG100_PRI_MAP_DEFAULT 0x00000004
-
-/* SWITCH_CORE :: IMP_PCP2TC_DEI0 :: TAG011_PRI_MAP [11:09] */
-#define BCHP_SWITCH_CORE_IMP_PCP2TC_DEI0_TAG011_PRI_MAP_MASK 0x00000e00
-#define BCHP_SWITCH_CORE_IMP_PCP2TC_DEI0_TAG011_PRI_MAP_SHIFT 9
-#define BCHP_SWITCH_CORE_IMP_PCP2TC_DEI0_TAG011_PRI_MAP_DEFAULT 0x00000003
-
-/* SWITCH_CORE :: IMP_PCP2TC_DEI0 :: TAG010_PRI_MAP [08:06] */
-#define BCHP_SWITCH_CORE_IMP_PCP2TC_DEI0_TAG010_PRI_MAP_MASK 0x000001c0
-#define BCHP_SWITCH_CORE_IMP_PCP2TC_DEI0_TAG010_PRI_MAP_SHIFT 6
-#define BCHP_SWITCH_CORE_IMP_PCP2TC_DEI0_TAG010_PRI_MAP_DEFAULT 0x00000002
-
-/* SWITCH_CORE :: IMP_PCP2TC_DEI0 :: TAG001_PRI_MAP [05:03] */
-#define BCHP_SWITCH_CORE_IMP_PCP2TC_DEI0_TAG001_PRI_MAP_MASK 0x00000038
-#define BCHP_SWITCH_CORE_IMP_PCP2TC_DEI0_TAG001_PRI_MAP_SHIFT 3
-#define BCHP_SWITCH_CORE_IMP_PCP2TC_DEI0_TAG001_PRI_MAP_DEFAULT 0x00000001
-
-/* SWITCH_CORE :: IMP_PCP2TC_DEI0 :: TAG000_PRI_MAP [02:00] */
-#define BCHP_SWITCH_CORE_IMP_PCP2TC_DEI0_TAG000_PRI_MAP_MASK 0x00000007
-#define BCHP_SWITCH_CORE_IMP_PCP2TC_DEI0_TAG000_PRI_MAP_SHIFT 0
-#define BCHP_SWITCH_CORE_IMP_PCP2TC_DEI0_TAG000_PRI_MAP_DEFAULT 0x00000000
-
-/***************************************************************************
- *QOS_DIFF_DSCP0 - DiffServ Priority Map 0 Register
- ***************************************************************************/
-/* SWITCH_CORE :: QOS_DIFF_DSCP0 :: PRI_DSCP_001111 [47:45] */
-#define BCHP_SWITCH_CORE_QOS_DIFF_DSCP0_PRI_DSCP_001111_MASK 0x00000000e000
-#define BCHP_SWITCH_CORE_QOS_DIFF_DSCP0_PRI_DSCP_001111_SHIFT 45
-#define BCHP_SWITCH_CORE_QOS_DIFF_DSCP0_PRI_DSCP_001111_DEFAULT 0x000000000000
-
-/* SWITCH_CORE :: QOS_DIFF_DSCP0 :: PRI_DSCP_001110 [44:42] */
-#define BCHP_SWITCH_CORE_QOS_DIFF_DSCP0_PRI_DSCP_001110_MASK 0x000000001c00
-#define BCHP_SWITCH_CORE_QOS_DIFF_DSCP0_PRI_DSCP_001110_SHIFT 42
-#define BCHP_SWITCH_CORE_QOS_DIFF_DSCP0_PRI_DSCP_001110_DEFAULT 0x000000000000
-
-/* SWITCH_CORE :: QOS_DIFF_DSCP0 :: PRI_DSCP_001101 [41:39] */
-#define BCHP_SWITCH_CORE_QOS_DIFF_DSCP0_PRI_DSCP_001101_MASK 0x000000000380
-#define BCHP_SWITCH_CORE_QOS_DIFF_DSCP0_PRI_DSCP_001101_SHIFT 39
-#define BCHP_SWITCH_CORE_QOS_DIFF_DSCP0_PRI_DSCP_001101_DEFAULT 0x000000000000
-
-/* SWITCH_CORE :: QOS_DIFF_DSCP0 :: PRI_DSCP_001100 [38:36] */
-#define BCHP_SWITCH_CORE_QOS_DIFF_DSCP0_PRI_DSCP_001100_MASK 0x000000000070
-#define BCHP_SWITCH_CORE_QOS_DIFF_DSCP0_PRI_DSCP_001100_SHIFT 36
-#define BCHP_SWITCH_CORE_QOS_DIFF_DSCP0_PRI_DSCP_001100_DEFAULT 0x000000000000
-
-/* SWITCH_CORE :: QOS_DIFF_DSCP0 :: PRI_DSCP_001011 [35:33] */
-#define BCHP_SWITCH_CORE_QOS_DIFF_DSCP0_PRI_DSCP_001011_MASK 0x00000000000e
-#define BCHP_SWITCH_CORE_QOS_DIFF_DSCP0_PRI_DSCP_001011_SHIFT 33
-#define BCHP_SWITCH_CORE_QOS_DIFF_DSCP0_PRI_DSCP_001011_DEFAULT 0x000000000000
-
-/* SWITCH_CORE :: QOS_DIFF_DSCP0 :: PRI_DSCP_001010 [32:30] */
-#define BCHP_SWITCH_CORE_QOS_DIFF_DSCP0_PRI_DSCP_001010_MASK 0x0000c0000000
-#define BCHP_SWITCH_CORE_QOS_DIFF_DSCP0_PRI_DSCP_001010_SHIFT 30
-#define BCHP_SWITCH_CORE_QOS_DIFF_DSCP0_PRI_DSCP_001010_DEFAULT 0x000000000000
-
-/* SWITCH_CORE :: QOS_DIFF_DSCP0 :: PRI_DSCP_001001 [29:27] */
-#define BCHP_SWITCH_CORE_QOS_DIFF_DSCP0_PRI_DSCP_001001_MASK 0x000038000000
-#define BCHP_SWITCH_CORE_QOS_DIFF_DSCP0_PRI_DSCP_001001_SHIFT 27
-#define BCHP_SWITCH_CORE_QOS_DIFF_DSCP0_PRI_DSCP_001001_DEFAULT 0x000000000000
-
-/* SWITCH_CORE :: QOS_DIFF_DSCP0 :: PRI_DSCP_001000 [26:24] */
-#define BCHP_SWITCH_CORE_QOS_DIFF_DSCP0_PRI_DSCP_001000_MASK 0x000007000000
-#define BCHP_SWITCH_CORE_QOS_DIFF_DSCP0_PRI_DSCP_001000_SHIFT 24
-#define BCHP_SWITCH_CORE_QOS_DIFF_DSCP0_PRI_DSCP_001000_DEFAULT 0x000000000000
-
-/* SWITCH_CORE :: QOS_DIFF_DSCP0 :: PRI_DSCP_000111 [23:21] */
-#define BCHP_SWITCH_CORE_QOS_DIFF_DSCP0_PRI_DSCP_000111_MASK 0x000000e00000
-#define BCHP_SWITCH_CORE_QOS_DIFF_DSCP0_PRI_DSCP_000111_SHIFT 21
-#define BCHP_SWITCH_CORE_QOS_DIFF_DSCP0_PRI_DSCP_000111_DEFAULT 0x000000000000
-
-/* SWITCH_CORE :: QOS_DIFF_DSCP0 :: PRI_DSCP_000110 [20:18] */
-#define BCHP_SWITCH_CORE_QOS_DIFF_DSCP0_PRI_DSCP_000110_MASK 0x0000001c0000
-#define BCHP_SWITCH_CORE_QOS_DIFF_DSCP0_PRI_DSCP_000110_SHIFT 18
-#define BCHP_SWITCH_CORE_QOS_DIFF_DSCP0_PRI_DSCP_000110_DEFAULT 0x000000000000
-
-/* SWITCH_CORE :: QOS_DIFF_DSCP0 :: PRI_DSCP_000101 [17:15] */
-#define BCHP_SWITCH_CORE_QOS_DIFF_DSCP0_PRI_DSCP_000101_MASK 0x000000038000
-#define BCHP_SWITCH_CORE_QOS_DIFF_DSCP0_PRI_DSCP_000101_SHIFT 15
-#define BCHP_SWITCH_CORE_QOS_DIFF_DSCP0_PRI_DSCP_000101_DEFAULT 0x000000000000
-
-/* SWITCH_CORE :: QOS_DIFF_DSCP0 :: PRI_DSCP_000100 [14:12] */
-#define BCHP_SWITCH_CORE_QOS_DIFF_DSCP0_PRI_DSCP_000100_MASK 0x000000007000
-#define BCHP_SWITCH_CORE_QOS_DIFF_DSCP0_PRI_DSCP_000100_SHIFT 12
-#define BCHP_SWITCH_CORE_QOS_DIFF_DSCP0_PRI_DSCP_000100_DEFAULT 0x000000000000
-
-/* SWITCH_CORE :: QOS_DIFF_DSCP0 :: PRI_DSCP_000011 [11:09] */
-#define BCHP_SWITCH_CORE_QOS_DIFF_DSCP0_PRI_DSCP_000011_MASK 0x000000000e00
-#define BCHP_SWITCH_CORE_QOS_DIFF_DSCP0_PRI_DSCP_000011_SHIFT 9
-#define BCHP_SWITCH_CORE_QOS_DIFF_DSCP0_PRI_DSCP_000011_DEFAULT 0x000000000000
-
-/* SWITCH_CORE :: QOS_DIFF_DSCP0 :: PRI_DSCP_000010 [08:06] */
-#define BCHP_SWITCH_CORE_QOS_DIFF_DSCP0_PRI_DSCP_000010_MASK 0x0000000001c0
-#define BCHP_SWITCH_CORE_QOS_DIFF_DSCP0_PRI_DSCP_000010_SHIFT 6
-#define BCHP_SWITCH_CORE_QOS_DIFF_DSCP0_PRI_DSCP_000010_DEFAULT 0x000000000000
-
-/* SWITCH_CORE :: QOS_DIFF_DSCP0 :: PRI_DSCP_000001 [05:03] */
-#define BCHP_SWITCH_CORE_QOS_DIFF_DSCP0_PRI_DSCP_000001_MASK 0x000000000038
-#define BCHP_SWITCH_CORE_QOS_DIFF_DSCP0_PRI_DSCP_000001_SHIFT 3
-#define BCHP_SWITCH_CORE_QOS_DIFF_DSCP0_PRI_DSCP_000001_DEFAULT 0x000000000000
-
-/* SWITCH_CORE :: QOS_DIFF_DSCP0 :: PRI_DSCP_000000 [02:00] */
-#define BCHP_SWITCH_CORE_QOS_DIFF_DSCP0_PRI_DSCP_000000_MASK 0x000000000007
-#define BCHP_SWITCH_CORE_QOS_DIFF_DSCP0_PRI_DSCP_000000_SHIFT 0
-#define BCHP_SWITCH_CORE_QOS_DIFF_DSCP0_PRI_DSCP_000000_DEFAULT 0x000000000000
-
-/***************************************************************************
- *QOS_DIFF_DSCP1 - DiffServ Priority Map 1 Register
- ***************************************************************************/
-/* SWITCH_CORE :: QOS_DIFF_DSCP1 :: PRI_DSCP_011111 [47:45] */
-#define BCHP_SWITCH_CORE_QOS_DIFF_DSCP1_PRI_DSCP_011111_MASK 0x00000000e000
-#define BCHP_SWITCH_CORE_QOS_DIFF_DSCP1_PRI_DSCP_011111_SHIFT 45
-#define BCHP_SWITCH_CORE_QOS_DIFF_DSCP1_PRI_DSCP_011111_DEFAULT 0x000000000000
-
-/* SWITCH_CORE :: QOS_DIFF_DSCP1 :: PRI_DSCP_011110 [44:42] */
-#define BCHP_SWITCH_CORE_QOS_DIFF_DSCP1_PRI_DSCP_011110_MASK 0x000000001c00
-#define BCHP_SWITCH_CORE_QOS_DIFF_DSCP1_PRI_DSCP_011110_SHIFT 42
-#define BCHP_SWITCH_CORE_QOS_DIFF_DSCP1_PRI_DSCP_011110_DEFAULT 0x000000000000
-
-/* SWITCH_CORE :: QOS_DIFF_DSCP1 :: PRI_DSCP_011101 [41:39] */
-#define BCHP_SWITCH_CORE_QOS_DIFF_DSCP1_PRI_DSCP_011101_MASK 0x000000000380
-#define BCHP_SWITCH_CORE_QOS_DIFF_DSCP1_PRI_DSCP_011101_SHIFT 39
-#define BCHP_SWITCH_CORE_QOS_DIFF_DSCP1_PRI_DSCP_011101_DEFAULT 0x000000000000
-
-/* SWITCH_CORE :: QOS_DIFF_DSCP1 :: PRI_DSCP_011100 [38:36] */
-#define BCHP_SWITCH_CORE_QOS_DIFF_DSCP1_PRI_DSCP_011100_MASK 0x000000000070
-#define BCHP_SWITCH_CORE_QOS_DIFF_DSCP1_PRI_DSCP_011100_SHIFT 36
-#define BCHP_SWITCH_CORE_QOS_DIFF_DSCP1_PRI_DSCP_011100_DEFAULT 0x000000000000
-
-/* SWITCH_CORE :: QOS_DIFF_DSCP1 :: PRI_DSCP_011011 [35:33] */
-#define BCHP_SWITCH_CORE_QOS_DIFF_DSCP1_PRI_DSCP_011011_MASK 0x00000000000e
-#define BCHP_SWITCH_CORE_QOS_DIFF_DSCP1_PRI_DSCP_011011_SHIFT 33
-#define BCHP_SWITCH_CORE_QOS_DIFF_DSCP1_PRI_DSCP_011011_DEFAULT 0x000000000000
-
-/* SWITCH_CORE :: QOS_DIFF_DSCP1 :: PRI_DSCP_011010 [32:30] */
-#define BCHP_SWITCH_CORE_QOS_DIFF_DSCP1_PRI_DSCP_011010_MASK 0x0000c0000000
-#define BCHP_SWITCH_CORE_QOS_DIFF_DSCP1_PRI_DSCP_011010_SHIFT 30
-#define BCHP_SWITCH_CORE_QOS_DIFF_DSCP1_PRI_DSCP_011010_DEFAULT 0x000000000000
-
-/* SWITCH_CORE :: QOS_DIFF_DSCP1 :: PRI_DSCP_011001 [29:27] */
-#define BCHP_SWITCH_CORE_QOS_DIFF_DSCP1_PRI_DSCP_011001_MASK 0x000038000000
-#define BCHP_SWITCH_CORE_QOS_DIFF_DSCP1_PRI_DSCP_011001_SHIFT 27
-#define BCHP_SWITCH_CORE_QOS_DIFF_DSCP1_PRI_DSCP_011001_DEFAULT 0x000000000000
-
-/* SWITCH_CORE :: QOS_DIFF_DSCP1 :: PRI_DSCP_011000 [26:24] */
-#define BCHP_SWITCH_CORE_QOS_DIFF_DSCP1_PRI_DSCP_011000_MASK 0x000007000000
-#define BCHP_SWITCH_CORE_QOS_DIFF_DSCP1_PRI_DSCP_011000_SHIFT 24
-#define BCHP_SWITCH_CORE_QOS_DIFF_DSCP1_PRI_DSCP_011000_DEFAULT 0x000000000000
-
-/* SWITCH_CORE :: QOS_DIFF_DSCP1 :: PRI_DSCP_010111 [23:21] */
-#define BCHP_SWITCH_CORE_QOS_DIFF_DSCP1_PRI_DSCP_010111_MASK 0x000000e00000
-#define BCHP_SWITCH_CORE_QOS_DIFF_DSCP1_PRI_DSCP_010111_SHIFT 21
-#define BCHP_SWITCH_CORE_QOS_DIFF_DSCP1_PRI_DSCP_010111_DEFAULT 0x000000000000
-
-/* SWITCH_CORE :: QOS_DIFF_DSCP1 :: PRI_DSCP_010110 [20:18] */
-#define BCHP_SWITCH_CORE_QOS_DIFF_DSCP1_PRI_DSCP_010110_MASK 0x0000001c0000
-#define BCHP_SWITCH_CORE_QOS_DIFF_DSCP1_PRI_DSCP_010110_SHIFT 18
-#define BCHP_SWITCH_CORE_QOS_DIFF_DSCP1_PRI_DSCP_010110_DEFAULT 0x000000000000
-
-/* SWITCH_CORE :: QOS_DIFF_DSCP1 :: PRI_DSCP_010101 [17:15] */
-#define BCHP_SWITCH_CORE_QOS_DIFF_DSCP1_PRI_DSCP_010101_MASK 0x000000038000
-#define BCHP_SWITCH_CORE_QOS_DIFF_DSCP1_PRI_DSCP_010101_SHIFT 15
-#define BCHP_SWITCH_CORE_QOS_DIFF_DSCP1_PRI_DSCP_010101_DEFAULT 0x000000000000
-
-/* SWITCH_CORE :: QOS_DIFF_DSCP1 :: PRI_DSCP_010100 [14:12] */
-#define BCHP_SWITCH_CORE_QOS_DIFF_DSCP1_PRI_DSCP_010100_MASK 0x000000007000
-#define BCHP_SWITCH_CORE_QOS_DIFF_DSCP1_PRI_DSCP_010100_SHIFT 12
-#define BCHP_SWITCH_CORE_QOS_DIFF_DSCP1_PRI_DSCP_010100_DEFAULT 0x000000000000
-
-/* SWITCH_CORE :: QOS_DIFF_DSCP1 :: PRI_DSCP_010011 [11:09] */
-#define BCHP_SWITCH_CORE_QOS_DIFF_DSCP1_PRI_DSCP_010011_MASK 0x000000000e00
-#define BCHP_SWITCH_CORE_QOS_DIFF_DSCP1_PRI_DSCP_010011_SHIFT 9
-#define BCHP_SWITCH_CORE_QOS_DIFF_DSCP1_PRI_DSCP_010011_DEFAULT 0x000000000000
-
-/* SWITCH_CORE :: QOS_DIFF_DSCP1 :: PRI_DSCP_010010 [08:06] */
-#define BCHP_SWITCH_CORE_QOS_DIFF_DSCP1_PRI_DSCP_010010_MASK 0x0000000001c0
-#define BCHP_SWITCH_CORE_QOS_DIFF_DSCP1_PRI_DSCP_010010_SHIFT 6
-#define BCHP_SWITCH_CORE_QOS_DIFF_DSCP1_PRI_DSCP_010010_DEFAULT 0x000000000000
-
-/* SWITCH_CORE :: QOS_DIFF_DSCP1 :: PRI_DSCP_010001 [05:03] */
-#define BCHP_SWITCH_CORE_QOS_DIFF_DSCP1_PRI_DSCP_010001_MASK 0x000000000038
-#define BCHP_SWITCH_CORE_QOS_DIFF_DSCP1_PRI_DSCP_010001_SHIFT 3
-#define BCHP_SWITCH_CORE_QOS_DIFF_DSCP1_PRI_DSCP_010001_DEFAULT 0x000000000000
-
-/* SWITCH_CORE :: QOS_DIFF_DSCP1 :: PRI_DSCP_010000 [02:00] */
-#define BCHP_SWITCH_CORE_QOS_DIFF_DSCP1_PRI_DSCP_010000_MASK 0x000000000007
-#define BCHP_SWITCH_CORE_QOS_DIFF_DSCP1_PRI_DSCP_010000_SHIFT 0
-#define BCHP_SWITCH_CORE_QOS_DIFF_DSCP1_PRI_DSCP_010000_DEFAULT 0x000000000000
-
-/***************************************************************************
- *QOS_DIFF_DSCP2 - DiffServ Priority Map 2 Register
- ***************************************************************************/
-/* SWITCH_CORE :: QOS_DIFF_DSCP2 :: PRI_DSCP_101111 [47:45] */
-#define BCHP_SWITCH_CORE_QOS_DIFF_DSCP2_PRI_DSCP_101111_MASK 0x00000000e000
-#define BCHP_SWITCH_CORE_QOS_DIFF_DSCP2_PRI_DSCP_101111_SHIFT 45
-#define BCHP_SWITCH_CORE_QOS_DIFF_DSCP2_PRI_DSCP_101111_DEFAULT 0x000000000000
-
-/* SWITCH_CORE :: QOS_DIFF_DSCP2 :: PRI_DSCP_101110 [44:42] */
-#define BCHP_SWITCH_CORE_QOS_DIFF_DSCP2_PRI_DSCP_101110_MASK 0x000000001c00
-#define BCHP_SWITCH_CORE_QOS_DIFF_DSCP2_PRI_DSCP_101110_SHIFT 42
-#define BCHP_SWITCH_CORE_QOS_DIFF_DSCP2_PRI_DSCP_101110_DEFAULT 0x000000000000
-
-/* SWITCH_CORE :: QOS_DIFF_DSCP2 :: PRI_DSCP_101101 [41:39] */
-#define BCHP_SWITCH_CORE_QOS_DIFF_DSCP2_PRI_DSCP_101101_MASK 0x000000000380
-#define BCHP_SWITCH_CORE_QOS_DIFF_DSCP2_PRI_DSCP_101101_SHIFT 39
-#define BCHP_SWITCH_CORE_QOS_DIFF_DSCP2_PRI_DSCP_101101_DEFAULT 0x000000000000
-
-/* SWITCH_CORE :: QOS_DIFF_DSCP2 :: PRI_DSCP_101100 [38:36] */
-#define BCHP_SWITCH_CORE_QOS_DIFF_DSCP2_PRI_DSCP_101100_MASK 0x000000000070
-#define BCHP_SWITCH_CORE_QOS_DIFF_DSCP2_PRI_DSCP_101100_SHIFT 36
-#define BCHP_SWITCH_CORE_QOS_DIFF_DSCP2_PRI_DSCP_101100_DEFAULT 0x000000000000
-
-/* SWITCH_CORE :: QOS_DIFF_DSCP2 :: PRI_DSCP_101011 [35:33] */
-#define BCHP_SWITCH_CORE_QOS_DIFF_DSCP2_PRI_DSCP_101011_MASK 0x00000000000e
-#define BCHP_SWITCH_CORE_QOS_DIFF_DSCP2_PRI_DSCP_101011_SHIFT 33
-#define BCHP_SWITCH_CORE_QOS_DIFF_DSCP2_PRI_DSCP_101011_DEFAULT 0x000000000000
-
-/* SWITCH_CORE :: QOS_DIFF_DSCP2 :: PRI_DSCP_101010 [32:30] */
-#define BCHP_SWITCH_CORE_QOS_DIFF_DSCP2_PRI_DSCP_101010_MASK 0x0000c0000000
-#define BCHP_SWITCH_CORE_QOS_DIFF_DSCP2_PRI_DSCP_101010_SHIFT 30
-#define BCHP_SWITCH_CORE_QOS_DIFF_DSCP2_PRI_DSCP_101010_DEFAULT 0x000000000000
-
-/* SWITCH_CORE :: QOS_DIFF_DSCP2 :: PRI_DSCP_101001 [29:27] */
-#define BCHP_SWITCH_CORE_QOS_DIFF_DSCP2_PRI_DSCP_101001_MASK 0x000038000000
-#define BCHP_SWITCH_CORE_QOS_DIFF_DSCP2_PRI_DSCP_101001_SHIFT 27
-#define BCHP_SWITCH_CORE_QOS_DIFF_DSCP2_PRI_DSCP_101001_DEFAULT 0x000000000000
-
-/* SWITCH_CORE :: QOS_DIFF_DSCP2 :: PRI_DSCP_101000 [26:24] */
-#define BCHP_SWITCH_CORE_QOS_DIFF_DSCP2_PRI_DSCP_101000_MASK 0x000007000000
-#define BCHP_SWITCH_CORE_QOS_DIFF_DSCP2_PRI_DSCP_101000_SHIFT 24
-#define BCHP_SWITCH_CORE_QOS_DIFF_DSCP2_PRI_DSCP_101000_DEFAULT 0x000000000000
-
-/* SWITCH_CORE :: QOS_DIFF_DSCP2 :: PRI_DSCP_100111 [23:21] */
-#define BCHP_SWITCH_CORE_QOS_DIFF_DSCP2_PRI_DSCP_100111_MASK 0x000000e00000
-#define BCHP_SWITCH_CORE_QOS_DIFF_DSCP2_PRI_DSCP_100111_SHIFT 21
-#define BCHP_SWITCH_CORE_QOS_DIFF_DSCP2_PRI_DSCP_100111_DEFAULT 0x000000000000
-
-/* SWITCH_CORE :: QOS_DIFF_DSCP2 :: PRI_DSCP_100110 [20:18] */
-#define BCHP_SWITCH_CORE_QOS_DIFF_DSCP2_PRI_DSCP_100110_MASK 0x0000001c0000
-#define BCHP_SWITCH_CORE_QOS_DIFF_DSCP2_PRI_DSCP_100110_SHIFT 18
-#define BCHP_SWITCH_CORE_QOS_DIFF_DSCP2_PRI_DSCP_100110_DEFAULT 0x000000000000
-
-/* SWITCH_CORE :: QOS_DIFF_DSCP2 :: PRI_DSCP_100101 [17:15] */
-#define BCHP_SWITCH_CORE_QOS_DIFF_DSCP2_PRI_DSCP_100101_MASK 0x000000038000
-#define BCHP_SWITCH_CORE_QOS_DIFF_DSCP2_PRI_DSCP_100101_SHIFT 15
-#define BCHP_SWITCH_CORE_QOS_DIFF_DSCP2_PRI_DSCP_100101_DEFAULT 0x000000000000
-
-/* SWITCH_CORE :: QOS_DIFF_DSCP2 :: PRI_DSCP_100100 [14:12] */
-#define BCHP_SWITCH_CORE_QOS_DIFF_DSCP2_PRI_DSCP_100100_MASK 0x000000007000
-#define BCHP_SWITCH_CORE_QOS_DIFF_DSCP2_PRI_DSCP_100100_SHIFT 12
-#define BCHP_SWITCH_CORE_QOS_DIFF_DSCP2_PRI_DSCP_100100_DEFAULT 0x000000000000
-
-/* SWITCH_CORE :: QOS_DIFF_DSCP2 :: PRI_DSCP_100011 [11:09] */
-#define BCHP_SWITCH_CORE_QOS_DIFF_DSCP2_PRI_DSCP_100011_MASK 0x000000000e00
-#define BCHP_SWITCH_CORE_QOS_DIFF_DSCP2_PRI_DSCP_100011_SHIFT 9
-#define BCHP_SWITCH_CORE_QOS_DIFF_DSCP2_PRI_DSCP_100011_DEFAULT 0x000000000000
-
-/* SWITCH_CORE :: QOS_DIFF_DSCP2 :: PRI_DSCP_100010 [08:06] */
-#define BCHP_SWITCH_CORE_QOS_DIFF_DSCP2_PRI_DSCP_100010_MASK 0x0000000001c0
-#define BCHP_SWITCH_CORE_QOS_DIFF_DSCP2_PRI_DSCP_100010_SHIFT 6
-#define BCHP_SWITCH_CORE_QOS_DIFF_DSCP2_PRI_DSCP_100010_DEFAULT 0x000000000000
-
-/* SWITCH_CORE :: QOS_DIFF_DSCP2 :: PRI_DSCP_100001 [05:03] */
-#define BCHP_SWITCH_CORE_QOS_DIFF_DSCP2_PRI_DSCP_100001_MASK 0x000000000038
-#define BCHP_SWITCH_CORE_QOS_DIFF_DSCP2_PRI_DSCP_100001_SHIFT 3
-#define BCHP_SWITCH_CORE_QOS_DIFF_DSCP2_PRI_DSCP_100001_DEFAULT 0x000000000000
-
-/* SWITCH_CORE :: QOS_DIFF_DSCP2 :: PRI_DSCP_100000 [02:00] */
-#define BCHP_SWITCH_CORE_QOS_DIFF_DSCP2_PRI_DSCP_100000_MASK 0x000000000007
-#define BCHP_SWITCH_CORE_QOS_DIFF_DSCP2_PRI_DSCP_100000_SHIFT 0
-#define BCHP_SWITCH_CORE_QOS_DIFF_DSCP2_PRI_DSCP_100000_DEFAULT 0x000000000000
-
-/***************************************************************************
- *QOS_DIFF_DSCP3 - DiffServ Priority Map 3 Register
- ***************************************************************************/
-/* SWITCH_CORE :: QOS_DIFF_DSCP3 :: PRI_DSCP_111111 [47:45] */
-#define BCHP_SWITCH_CORE_QOS_DIFF_DSCP3_PRI_DSCP_111111_MASK 0x00000000e000
-#define BCHP_SWITCH_CORE_QOS_DIFF_DSCP3_PRI_DSCP_111111_SHIFT 45
-#define BCHP_SWITCH_CORE_QOS_DIFF_DSCP3_PRI_DSCP_111111_DEFAULT 0x000000000000
-
-/* SWITCH_CORE :: QOS_DIFF_DSCP3 :: PRI_DSCP_111110 [44:42] */
-#define BCHP_SWITCH_CORE_QOS_DIFF_DSCP3_PRI_DSCP_111110_MASK 0x000000001c00
-#define BCHP_SWITCH_CORE_QOS_DIFF_DSCP3_PRI_DSCP_111110_SHIFT 42
-#define BCHP_SWITCH_CORE_QOS_DIFF_DSCP3_PRI_DSCP_111110_DEFAULT 0x000000000000
-
-/* SWITCH_CORE :: QOS_DIFF_DSCP3 :: PRI_DSCP_111101 [41:39] */
-#define BCHP_SWITCH_CORE_QOS_DIFF_DSCP3_PRI_DSCP_111101_MASK 0x000000000380
-#define BCHP_SWITCH_CORE_QOS_DIFF_DSCP3_PRI_DSCP_111101_SHIFT 39
-#define BCHP_SWITCH_CORE_QOS_DIFF_DSCP3_PRI_DSCP_111101_DEFAULT 0x000000000000
-
-/* SWITCH_CORE :: QOS_DIFF_DSCP3 :: PRI_DSCP_111100 [38:36] */
-#define BCHP_SWITCH_CORE_QOS_DIFF_DSCP3_PRI_DSCP_111100_MASK 0x000000000070
-#define BCHP_SWITCH_CORE_QOS_DIFF_DSCP3_PRI_DSCP_111100_SHIFT 36
-#define BCHP_SWITCH_CORE_QOS_DIFF_DSCP3_PRI_DSCP_111100_DEFAULT 0x000000000000
-
-/* SWITCH_CORE :: QOS_DIFF_DSCP3 :: PRI_DSCP_111011 [35:33] */
-#define BCHP_SWITCH_CORE_QOS_DIFF_DSCP3_PRI_DSCP_111011_MASK 0x00000000000e
-#define BCHP_SWITCH_CORE_QOS_DIFF_DSCP3_PRI_DSCP_111011_SHIFT 33
-#define BCHP_SWITCH_CORE_QOS_DIFF_DSCP3_PRI_DSCP_111011_DEFAULT 0x000000000000
-
-/* SWITCH_CORE :: QOS_DIFF_DSCP3 :: PRI_DSCP_111010 [32:30] */
-#define BCHP_SWITCH_CORE_QOS_DIFF_DSCP3_PRI_DSCP_111010_MASK 0x0000c0000000
-#define BCHP_SWITCH_CORE_QOS_DIFF_DSCP3_PRI_DSCP_111010_SHIFT 30
-#define BCHP_SWITCH_CORE_QOS_DIFF_DSCP3_PRI_DSCP_111010_DEFAULT 0x000000000000
-
-/* SWITCH_CORE :: QOS_DIFF_DSCP3 :: PRI_DSCP_111001 [29:27] */
-#define BCHP_SWITCH_CORE_QOS_DIFF_DSCP3_PRI_DSCP_111001_MASK 0x000038000000
-#define BCHP_SWITCH_CORE_QOS_DIFF_DSCP3_PRI_DSCP_111001_SHIFT 27
-#define BCHP_SWITCH_CORE_QOS_DIFF_DSCP3_PRI_DSCP_111001_DEFAULT 0x000000000000
-
-/* SWITCH_CORE :: QOS_DIFF_DSCP3 :: PRI_DSCP_111000 [26:24] */
-#define BCHP_SWITCH_CORE_QOS_DIFF_DSCP3_PRI_DSCP_111000_MASK 0x000007000000
-#define BCHP_SWITCH_CORE_QOS_DIFF_DSCP3_PRI_DSCP_111000_SHIFT 24
-#define BCHP_SWITCH_CORE_QOS_DIFF_DSCP3_PRI_DSCP_111000_DEFAULT 0x000000000000
-
-/* SWITCH_CORE :: QOS_DIFF_DSCP3 :: PRI_DSCP_110111 [23:21] */
-#define BCHP_SWITCH_CORE_QOS_DIFF_DSCP3_PRI_DSCP_110111_MASK 0x000000e00000
-#define BCHP_SWITCH_CORE_QOS_DIFF_DSCP3_PRI_DSCP_110111_SHIFT 21
-#define BCHP_SWITCH_CORE_QOS_DIFF_DSCP3_PRI_DSCP_110111_DEFAULT 0x000000000000
-
-/* SWITCH_CORE :: QOS_DIFF_DSCP3 :: PRI_DSCP_110110 [20:18] */
-#define BCHP_SWITCH_CORE_QOS_DIFF_DSCP3_PRI_DSCP_110110_MASK 0x0000001c0000
-#define BCHP_SWITCH_CORE_QOS_DIFF_DSCP3_PRI_DSCP_110110_SHIFT 18
-#define BCHP_SWITCH_CORE_QOS_DIFF_DSCP3_PRI_DSCP_110110_DEFAULT 0x000000000000
-
-/* SWITCH_CORE :: QOS_DIFF_DSCP3 :: PRI_DSCP_110101 [17:15] */
-#define BCHP_SWITCH_CORE_QOS_DIFF_DSCP3_PRI_DSCP_110101_MASK 0x000000038000
-#define BCHP_SWITCH_CORE_QOS_DIFF_DSCP3_PRI_DSCP_110101_SHIFT 15
-#define BCHP_SWITCH_CORE_QOS_DIFF_DSCP3_PRI_DSCP_110101_DEFAULT 0x000000000000
-
-/* SWITCH_CORE :: QOS_DIFF_DSCP3 :: PRI_DSCP_110100 [14:12] */
-#define BCHP_SWITCH_CORE_QOS_DIFF_DSCP3_PRI_DSCP_110100_MASK 0x000000007000
-#define BCHP_SWITCH_CORE_QOS_DIFF_DSCP3_PRI_DSCP_110100_SHIFT 12
-#define BCHP_SWITCH_CORE_QOS_DIFF_DSCP3_PRI_DSCP_110100_DEFAULT 0x000000000000
-
-/* SWITCH_CORE :: QOS_DIFF_DSCP3 :: PRI_DSCP_110011 [11:09] */
-#define BCHP_SWITCH_CORE_QOS_DIFF_DSCP3_PRI_DSCP_110011_MASK 0x000000000e00
-#define BCHP_SWITCH_CORE_QOS_DIFF_DSCP3_PRI_DSCP_110011_SHIFT 9
-#define BCHP_SWITCH_CORE_QOS_DIFF_DSCP3_PRI_DSCP_110011_DEFAULT 0x000000000000
-
-/* SWITCH_CORE :: QOS_DIFF_DSCP3 :: PRI_DSCP_110010 [08:06] */
-#define BCHP_SWITCH_CORE_QOS_DIFF_DSCP3_PRI_DSCP_110010_MASK 0x0000000001c0
-#define BCHP_SWITCH_CORE_QOS_DIFF_DSCP3_PRI_DSCP_110010_SHIFT 6
-#define BCHP_SWITCH_CORE_QOS_DIFF_DSCP3_PRI_DSCP_110010_DEFAULT 0x000000000000
-
-/* SWITCH_CORE :: QOS_DIFF_DSCP3 :: PRI_DSCP_110001 [05:03] */
-#define BCHP_SWITCH_CORE_QOS_DIFF_DSCP3_PRI_DSCP_110001_MASK 0x000000000038
-#define BCHP_SWITCH_CORE_QOS_DIFF_DSCP3_PRI_DSCP_110001_SHIFT 3
-#define BCHP_SWITCH_CORE_QOS_DIFF_DSCP3_PRI_DSCP_110001_DEFAULT 0x000000000000
-
-/* SWITCH_CORE :: QOS_DIFF_DSCP3 :: PRI_DSCP_110000 [02:00] */
-#define BCHP_SWITCH_CORE_QOS_DIFF_DSCP3_PRI_DSCP_110000_MASK 0x000000000007
-#define BCHP_SWITCH_CORE_QOS_DIFF_DSCP3_PRI_DSCP_110000_SHIFT 0
-#define BCHP_SWITCH_CORE_QOS_DIFF_DSCP3_PRI_DSCP_110000_DEFAULT 0x000000000000
-
-/***************************************************************************
- *PID2TC - Port ID to TC Map Register
- ***************************************************************************/
-/* SWITCH_CORE :: PID2TC :: SWITCH_RESV [31:27] */
-#define BCHP_SWITCH_CORE_PID2TC_SWITCH_RESV_MASK 0xf8000000
-#define BCHP_SWITCH_CORE_PID2TC_SWITCH_RESV_SHIFT 27
-#define BCHP_SWITCH_CORE_PID2TC_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: PID2TC :: PID2TC [26:00] */
-#define BCHP_SWITCH_CORE_PID2TC_PID2TC_MASK 0x07ffffff
-#define BCHP_SWITCH_CORE_PID2TC_PID2TC_SHIFT 0
-#define BCHP_SWITCH_CORE_PID2TC_PID2TC_DEFAULT 0x00000000
-
-/***************************************************************************
- *TC_SEL_TABLE_Port_0 - Port N TC Select Table Register
- ***************************************************************************/
-/* SWITCH_CORE :: TC_SEL_TABLE_Port_0 :: reserved_for_padding0 [31:16] */
-#define BCHP_SWITCH_CORE_TC_SEL_TABLE_Port_0_reserved_for_padding0_MASK 0xffff0000
-#define BCHP_SWITCH_CORE_TC_SEL_TABLE_Port_0_reserved_for_padding0_SHIFT 16
-
-/* SWITCH_CORE :: TC_SEL_TABLE_Port_0 :: TC_SEL_7 [15:14] */
-#define BCHP_SWITCH_CORE_TC_SEL_TABLE_Port_0_TC_SEL_7_MASK 0x0000c000
-#define BCHP_SWITCH_CORE_TC_SEL_TABLE_Port_0_TC_SEL_7_SHIFT 14
-#define BCHP_SWITCH_CORE_TC_SEL_TABLE_Port_0_TC_SEL_7_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: TC_SEL_TABLE_Port_0 :: TC_SEL_6 [13:12] */
-#define BCHP_SWITCH_CORE_TC_SEL_TABLE_Port_0_TC_SEL_6_MASK 0x00003000
-#define BCHP_SWITCH_CORE_TC_SEL_TABLE_Port_0_TC_SEL_6_SHIFT 12
-#define BCHP_SWITCH_CORE_TC_SEL_TABLE_Port_0_TC_SEL_6_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: TC_SEL_TABLE_Port_0 :: TC_SEL_5 [11:10] */
-#define BCHP_SWITCH_CORE_TC_SEL_TABLE_Port_0_TC_SEL_5_MASK 0x00000c00
-#define BCHP_SWITCH_CORE_TC_SEL_TABLE_Port_0_TC_SEL_5_SHIFT 10
-#define BCHP_SWITCH_CORE_TC_SEL_TABLE_Port_0_TC_SEL_5_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: TC_SEL_TABLE_Port_0 :: TC_SEL_4 [09:08] */
-#define BCHP_SWITCH_CORE_TC_SEL_TABLE_Port_0_TC_SEL_4_MASK 0x00000300
-#define BCHP_SWITCH_CORE_TC_SEL_TABLE_Port_0_TC_SEL_4_SHIFT 8
-#define BCHP_SWITCH_CORE_TC_SEL_TABLE_Port_0_TC_SEL_4_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: TC_SEL_TABLE_Port_0 :: TC_SEL_3 [07:06] */
-#define BCHP_SWITCH_CORE_TC_SEL_TABLE_Port_0_TC_SEL_3_MASK 0x000000c0
-#define BCHP_SWITCH_CORE_TC_SEL_TABLE_Port_0_TC_SEL_3_SHIFT 6
-#define BCHP_SWITCH_CORE_TC_SEL_TABLE_Port_0_TC_SEL_3_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: TC_SEL_TABLE_Port_0 :: TC_SEL_2 [05:04] */
-#define BCHP_SWITCH_CORE_TC_SEL_TABLE_Port_0_TC_SEL_2_MASK 0x00000030
-#define BCHP_SWITCH_CORE_TC_SEL_TABLE_Port_0_TC_SEL_2_SHIFT 4
-#define BCHP_SWITCH_CORE_TC_SEL_TABLE_Port_0_TC_SEL_2_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: TC_SEL_TABLE_Port_0 :: TC_SEL_1 [03:02] */
-#define BCHP_SWITCH_CORE_TC_SEL_TABLE_Port_0_TC_SEL_1_MASK 0x0000000c
-#define BCHP_SWITCH_CORE_TC_SEL_TABLE_Port_0_TC_SEL_1_SHIFT 2
-#define BCHP_SWITCH_CORE_TC_SEL_TABLE_Port_0_TC_SEL_1_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: TC_SEL_TABLE_Port_0 :: TC_SEL_0 [01:00] */
-#define BCHP_SWITCH_CORE_TC_SEL_TABLE_Port_0_TC_SEL_0_MASK 0x00000003
-#define BCHP_SWITCH_CORE_TC_SEL_TABLE_Port_0_TC_SEL_0_SHIFT 0
-#define BCHP_SWITCH_CORE_TC_SEL_TABLE_Port_0_TC_SEL_0_DEFAULT 0x00000000
-
-/***************************************************************************
- *TC_SEL_TABLE_Port_1 - Port N TC Select Table Register
- ***************************************************************************/
-/* SWITCH_CORE :: TC_SEL_TABLE_Port_1 :: reserved_for_padding0 [31:16] */
-#define BCHP_SWITCH_CORE_TC_SEL_TABLE_Port_1_reserved_for_padding0_MASK 0xffff0000
-#define BCHP_SWITCH_CORE_TC_SEL_TABLE_Port_1_reserved_for_padding0_SHIFT 16
-
-/* SWITCH_CORE :: TC_SEL_TABLE_Port_1 :: TC_SEL_7 [15:14] */
-#define BCHP_SWITCH_CORE_TC_SEL_TABLE_Port_1_TC_SEL_7_MASK 0x0000c000
-#define BCHP_SWITCH_CORE_TC_SEL_TABLE_Port_1_TC_SEL_7_SHIFT 14
-#define BCHP_SWITCH_CORE_TC_SEL_TABLE_Port_1_TC_SEL_7_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: TC_SEL_TABLE_Port_1 :: TC_SEL_6 [13:12] */
-#define BCHP_SWITCH_CORE_TC_SEL_TABLE_Port_1_TC_SEL_6_MASK 0x00003000
-#define BCHP_SWITCH_CORE_TC_SEL_TABLE_Port_1_TC_SEL_6_SHIFT 12
-#define BCHP_SWITCH_CORE_TC_SEL_TABLE_Port_1_TC_SEL_6_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: TC_SEL_TABLE_Port_1 :: TC_SEL_5 [11:10] */
-#define BCHP_SWITCH_CORE_TC_SEL_TABLE_Port_1_TC_SEL_5_MASK 0x00000c00
-#define BCHP_SWITCH_CORE_TC_SEL_TABLE_Port_1_TC_SEL_5_SHIFT 10
-#define BCHP_SWITCH_CORE_TC_SEL_TABLE_Port_1_TC_SEL_5_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: TC_SEL_TABLE_Port_1 :: TC_SEL_4 [09:08] */
-#define BCHP_SWITCH_CORE_TC_SEL_TABLE_Port_1_TC_SEL_4_MASK 0x00000300
-#define BCHP_SWITCH_CORE_TC_SEL_TABLE_Port_1_TC_SEL_4_SHIFT 8
-#define BCHP_SWITCH_CORE_TC_SEL_TABLE_Port_1_TC_SEL_4_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: TC_SEL_TABLE_Port_1 :: TC_SEL_3 [07:06] */
-#define BCHP_SWITCH_CORE_TC_SEL_TABLE_Port_1_TC_SEL_3_MASK 0x000000c0
-#define BCHP_SWITCH_CORE_TC_SEL_TABLE_Port_1_TC_SEL_3_SHIFT 6
-#define BCHP_SWITCH_CORE_TC_SEL_TABLE_Port_1_TC_SEL_3_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: TC_SEL_TABLE_Port_1 :: TC_SEL_2 [05:04] */
-#define BCHP_SWITCH_CORE_TC_SEL_TABLE_Port_1_TC_SEL_2_MASK 0x00000030
-#define BCHP_SWITCH_CORE_TC_SEL_TABLE_Port_1_TC_SEL_2_SHIFT 4
-#define BCHP_SWITCH_CORE_TC_SEL_TABLE_Port_1_TC_SEL_2_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: TC_SEL_TABLE_Port_1 :: TC_SEL_1 [03:02] */
-#define BCHP_SWITCH_CORE_TC_SEL_TABLE_Port_1_TC_SEL_1_MASK 0x0000000c
-#define BCHP_SWITCH_CORE_TC_SEL_TABLE_Port_1_TC_SEL_1_SHIFT 2
-#define BCHP_SWITCH_CORE_TC_SEL_TABLE_Port_1_TC_SEL_1_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: TC_SEL_TABLE_Port_1 :: TC_SEL_0 [01:00] */
-#define BCHP_SWITCH_CORE_TC_SEL_TABLE_Port_1_TC_SEL_0_MASK 0x00000003
-#define BCHP_SWITCH_CORE_TC_SEL_TABLE_Port_1_TC_SEL_0_SHIFT 0
-#define BCHP_SWITCH_CORE_TC_SEL_TABLE_Port_1_TC_SEL_0_DEFAULT 0x00000000
-
-/***************************************************************************
- *TC_SEL_TABLE_Port_2 - Port N TC Select Table Register
- ***************************************************************************/
-/* SWITCH_CORE :: TC_SEL_TABLE_Port_2 :: reserved_for_padding0 [31:16] */
-#define BCHP_SWITCH_CORE_TC_SEL_TABLE_Port_2_reserved_for_padding0_MASK 0xffff0000
-#define BCHP_SWITCH_CORE_TC_SEL_TABLE_Port_2_reserved_for_padding0_SHIFT 16
-
-/* SWITCH_CORE :: TC_SEL_TABLE_Port_2 :: TC_SEL_7 [15:14] */
-#define BCHP_SWITCH_CORE_TC_SEL_TABLE_Port_2_TC_SEL_7_MASK 0x0000c000
-#define BCHP_SWITCH_CORE_TC_SEL_TABLE_Port_2_TC_SEL_7_SHIFT 14
-#define BCHP_SWITCH_CORE_TC_SEL_TABLE_Port_2_TC_SEL_7_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: TC_SEL_TABLE_Port_2 :: TC_SEL_6 [13:12] */
-#define BCHP_SWITCH_CORE_TC_SEL_TABLE_Port_2_TC_SEL_6_MASK 0x00003000
-#define BCHP_SWITCH_CORE_TC_SEL_TABLE_Port_2_TC_SEL_6_SHIFT 12
-#define BCHP_SWITCH_CORE_TC_SEL_TABLE_Port_2_TC_SEL_6_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: TC_SEL_TABLE_Port_2 :: TC_SEL_5 [11:10] */
-#define BCHP_SWITCH_CORE_TC_SEL_TABLE_Port_2_TC_SEL_5_MASK 0x00000c00
-#define BCHP_SWITCH_CORE_TC_SEL_TABLE_Port_2_TC_SEL_5_SHIFT 10
-#define BCHP_SWITCH_CORE_TC_SEL_TABLE_Port_2_TC_SEL_5_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: TC_SEL_TABLE_Port_2 :: TC_SEL_4 [09:08] */
-#define BCHP_SWITCH_CORE_TC_SEL_TABLE_Port_2_TC_SEL_4_MASK 0x00000300
-#define BCHP_SWITCH_CORE_TC_SEL_TABLE_Port_2_TC_SEL_4_SHIFT 8
-#define BCHP_SWITCH_CORE_TC_SEL_TABLE_Port_2_TC_SEL_4_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: TC_SEL_TABLE_Port_2 :: TC_SEL_3 [07:06] */
-#define BCHP_SWITCH_CORE_TC_SEL_TABLE_Port_2_TC_SEL_3_MASK 0x000000c0
-#define BCHP_SWITCH_CORE_TC_SEL_TABLE_Port_2_TC_SEL_3_SHIFT 6
-#define BCHP_SWITCH_CORE_TC_SEL_TABLE_Port_2_TC_SEL_3_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: TC_SEL_TABLE_Port_2 :: TC_SEL_2 [05:04] */
-#define BCHP_SWITCH_CORE_TC_SEL_TABLE_Port_2_TC_SEL_2_MASK 0x00000030
-#define BCHP_SWITCH_CORE_TC_SEL_TABLE_Port_2_TC_SEL_2_SHIFT 4
-#define BCHP_SWITCH_CORE_TC_SEL_TABLE_Port_2_TC_SEL_2_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: TC_SEL_TABLE_Port_2 :: TC_SEL_1 [03:02] */
-#define BCHP_SWITCH_CORE_TC_SEL_TABLE_Port_2_TC_SEL_1_MASK 0x0000000c
-#define BCHP_SWITCH_CORE_TC_SEL_TABLE_Port_2_TC_SEL_1_SHIFT 2
-#define BCHP_SWITCH_CORE_TC_SEL_TABLE_Port_2_TC_SEL_1_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: TC_SEL_TABLE_Port_2 :: TC_SEL_0 [01:00] */
-#define BCHP_SWITCH_CORE_TC_SEL_TABLE_Port_2_TC_SEL_0_MASK 0x00000003
-#define BCHP_SWITCH_CORE_TC_SEL_TABLE_Port_2_TC_SEL_0_SHIFT 0
-#define BCHP_SWITCH_CORE_TC_SEL_TABLE_Port_2_TC_SEL_0_DEFAULT 0x00000000
-
-/***************************************************************************
- *TC_SEL_TABLE_Port_3 - Port N TC Select Table Register
- ***************************************************************************/
-/* SWITCH_CORE :: TC_SEL_TABLE_Port_3 :: reserved_for_padding0 [31:16] */
-#define BCHP_SWITCH_CORE_TC_SEL_TABLE_Port_3_reserved_for_padding0_MASK 0xffff0000
-#define BCHP_SWITCH_CORE_TC_SEL_TABLE_Port_3_reserved_for_padding0_SHIFT 16
-
-/* SWITCH_CORE :: TC_SEL_TABLE_Port_3 :: TC_SEL_7 [15:14] */
-#define BCHP_SWITCH_CORE_TC_SEL_TABLE_Port_3_TC_SEL_7_MASK 0x0000c000
-#define BCHP_SWITCH_CORE_TC_SEL_TABLE_Port_3_TC_SEL_7_SHIFT 14
-#define BCHP_SWITCH_CORE_TC_SEL_TABLE_Port_3_TC_SEL_7_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: TC_SEL_TABLE_Port_3 :: TC_SEL_6 [13:12] */
-#define BCHP_SWITCH_CORE_TC_SEL_TABLE_Port_3_TC_SEL_6_MASK 0x00003000
-#define BCHP_SWITCH_CORE_TC_SEL_TABLE_Port_3_TC_SEL_6_SHIFT 12
-#define BCHP_SWITCH_CORE_TC_SEL_TABLE_Port_3_TC_SEL_6_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: TC_SEL_TABLE_Port_3 :: TC_SEL_5 [11:10] */
-#define BCHP_SWITCH_CORE_TC_SEL_TABLE_Port_3_TC_SEL_5_MASK 0x00000c00
-#define BCHP_SWITCH_CORE_TC_SEL_TABLE_Port_3_TC_SEL_5_SHIFT 10
-#define BCHP_SWITCH_CORE_TC_SEL_TABLE_Port_3_TC_SEL_5_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: TC_SEL_TABLE_Port_3 :: TC_SEL_4 [09:08] */
-#define BCHP_SWITCH_CORE_TC_SEL_TABLE_Port_3_TC_SEL_4_MASK 0x00000300
-#define BCHP_SWITCH_CORE_TC_SEL_TABLE_Port_3_TC_SEL_4_SHIFT 8
-#define BCHP_SWITCH_CORE_TC_SEL_TABLE_Port_3_TC_SEL_4_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: TC_SEL_TABLE_Port_3 :: TC_SEL_3 [07:06] */
-#define BCHP_SWITCH_CORE_TC_SEL_TABLE_Port_3_TC_SEL_3_MASK 0x000000c0
-#define BCHP_SWITCH_CORE_TC_SEL_TABLE_Port_3_TC_SEL_3_SHIFT 6
-#define BCHP_SWITCH_CORE_TC_SEL_TABLE_Port_3_TC_SEL_3_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: TC_SEL_TABLE_Port_3 :: TC_SEL_2 [05:04] */
-#define BCHP_SWITCH_CORE_TC_SEL_TABLE_Port_3_TC_SEL_2_MASK 0x00000030
-#define BCHP_SWITCH_CORE_TC_SEL_TABLE_Port_3_TC_SEL_2_SHIFT 4
-#define BCHP_SWITCH_CORE_TC_SEL_TABLE_Port_3_TC_SEL_2_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: TC_SEL_TABLE_Port_3 :: TC_SEL_1 [03:02] */
-#define BCHP_SWITCH_CORE_TC_SEL_TABLE_Port_3_TC_SEL_1_MASK 0x0000000c
-#define BCHP_SWITCH_CORE_TC_SEL_TABLE_Port_3_TC_SEL_1_SHIFT 2
-#define BCHP_SWITCH_CORE_TC_SEL_TABLE_Port_3_TC_SEL_1_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: TC_SEL_TABLE_Port_3 :: TC_SEL_0 [01:00] */
-#define BCHP_SWITCH_CORE_TC_SEL_TABLE_Port_3_TC_SEL_0_MASK 0x00000003
-#define BCHP_SWITCH_CORE_TC_SEL_TABLE_Port_3_TC_SEL_0_SHIFT 0
-#define BCHP_SWITCH_CORE_TC_SEL_TABLE_Port_3_TC_SEL_0_DEFAULT 0x00000000
-
-/***************************************************************************
- *TC_SEL_TABLE_Port_4 - Port N TC Select Table Register
- ***************************************************************************/
-/* SWITCH_CORE :: TC_SEL_TABLE_Port_4 :: reserved_for_padding0 [31:16] */
-#define BCHP_SWITCH_CORE_TC_SEL_TABLE_Port_4_reserved_for_padding0_MASK 0xffff0000
-#define BCHP_SWITCH_CORE_TC_SEL_TABLE_Port_4_reserved_for_padding0_SHIFT 16
-
-/* SWITCH_CORE :: TC_SEL_TABLE_Port_4 :: TC_SEL_7 [15:14] */
-#define BCHP_SWITCH_CORE_TC_SEL_TABLE_Port_4_TC_SEL_7_MASK 0x0000c000
-#define BCHP_SWITCH_CORE_TC_SEL_TABLE_Port_4_TC_SEL_7_SHIFT 14
-#define BCHP_SWITCH_CORE_TC_SEL_TABLE_Port_4_TC_SEL_7_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: TC_SEL_TABLE_Port_4 :: TC_SEL_6 [13:12] */
-#define BCHP_SWITCH_CORE_TC_SEL_TABLE_Port_4_TC_SEL_6_MASK 0x00003000
-#define BCHP_SWITCH_CORE_TC_SEL_TABLE_Port_4_TC_SEL_6_SHIFT 12
-#define BCHP_SWITCH_CORE_TC_SEL_TABLE_Port_4_TC_SEL_6_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: TC_SEL_TABLE_Port_4 :: TC_SEL_5 [11:10] */
-#define BCHP_SWITCH_CORE_TC_SEL_TABLE_Port_4_TC_SEL_5_MASK 0x00000c00
-#define BCHP_SWITCH_CORE_TC_SEL_TABLE_Port_4_TC_SEL_5_SHIFT 10
-#define BCHP_SWITCH_CORE_TC_SEL_TABLE_Port_4_TC_SEL_5_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: TC_SEL_TABLE_Port_4 :: TC_SEL_4 [09:08] */
-#define BCHP_SWITCH_CORE_TC_SEL_TABLE_Port_4_TC_SEL_4_MASK 0x00000300
-#define BCHP_SWITCH_CORE_TC_SEL_TABLE_Port_4_TC_SEL_4_SHIFT 8
-#define BCHP_SWITCH_CORE_TC_SEL_TABLE_Port_4_TC_SEL_4_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: TC_SEL_TABLE_Port_4 :: TC_SEL_3 [07:06] */
-#define BCHP_SWITCH_CORE_TC_SEL_TABLE_Port_4_TC_SEL_3_MASK 0x000000c0
-#define BCHP_SWITCH_CORE_TC_SEL_TABLE_Port_4_TC_SEL_3_SHIFT 6
-#define BCHP_SWITCH_CORE_TC_SEL_TABLE_Port_4_TC_SEL_3_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: TC_SEL_TABLE_Port_4 :: TC_SEL_2 [05:04] */
-#define BCHP_SWITCH_CORE_TC_SEL_TABLE_Port_4_TC_SEL_2_MASK 0x00000030
-#define BCHP_SWITCH_CORE_TC_SEL_TABLE_Port_4_TC_SEL_2_SHIFT 4
-#define BCHP_SWITCH_CORE_TC_SEL_TABLE_Port_4_TC_SEL_2_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: TC_SEL_TABLE_Port_4 :: TC_SEL_1 [03:02] */
-#define BCHP_SWITCH_CORE_TC_SEL_TABLE_Port_4_TC_SEL_1_MASK 0x0000000c
-#define BCHP_SWITCH_CORE_TC_SEL_TABLE_Port_4_TC_SEL_1_SHIFT 2
-#define BCHP_SWITCH_CORE_TC_SEL_TABLE_Port_4_TC_SEL_1_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: TC_SEL_TABLE_Port_4 :: TC_SEL_0 [01:00] */
-#define BCHP_SWITCH_CORE_TC_SEL_TABLE_Port_4_TC_SEL_0_MASK 0x00000003
-#define BCHP_SWITCH_CORE_TC_SEL_TABLE_Port_4_TC_SEL_0_SHIFT 0
-#define BCHP_SWITCH_CORE_TC_SEL_TABLE_Port_4_TC_SEL_0_DEFAULT 0x00000000
-
-/***************************************************************************
- *TC_SEL_TABLE_Port_5 - Port N TC Select Table Register
- ***************************************************************************/
-/* SWITCH_CORE :: TC_SEL_TABLE_Port_5 :: reserved_for_padding0 [31:16] */
-#define BCHP_SWITCH_CORE_TC_SEL_TABLE_Port_5_reserved_for_padding0_MASK 0xffff0000
-#define BCHP_SWITCH_CORE_TC_SEL_TABLE_Port_5_reserved_for_padding0_SHIFT 16
-
-/* SWITCH_CORE :: TC_SEL_TABLE_Port_5 :: TC_SEL_7 [15:14] */
-#define BCHP_SWITCH_CORE_TC_SEL_TABLE_Port_5_TC_SEL_7_MASK 0x0000c000
-#define BCHP_SWITCH_CORE_TC_SEL_TABLE_Port_5_TC_SEL_7_SHIFT 14
-#define BCHP_SWITCH_CORE_TC_SEL_TABLE_Port_5_TC_SEL_7_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: TC_SEL_TABLE_Port_5 :: TC_SEL_6 [13:12] */
-#define BCHP_SWITCH_CORE_TC_SEL_TABLE_Port_5_TC_SEL_6_MASK 0x00003000
-#define BCHP_SWITCH_CORE_TC_SEL_TABLE_Port_5_TC_SEL_6_SHIFT 12
-#define BCHP_SWITCH_CORE_TC_SEL_TABLE_Port_5_TC_SEL_6_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: TC_SEL_TABLE_Port_5 :: TC_SEL_5 [11:10] */
-#define BCHP_SWITCH_CORE_TC_SEL_TABLE_Port_5_TC_SEL_5_MASK 0x00000c00
-#define BCHP_SWITCH_CORE_TC_SEL_TABLE_Port_5_TC_SEL_5_SHIFT 10
-#define BCHP_SWITCH_CORE_TC_SEL_TABLE_Port_5_TC_SEL_5_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: TC_SEL_TABLE_Port_5 :: TC_SEL_4 [09:08] */
-#define BCHP_SWITCH_CORE_TC_SEL_TABLE_Port_5_TC_SEL_4_MASK 0x00000300
-#define BCHP_SWITCH_CORE_TC_SEL_TABLE_Port_5_TC_SEL_4_SHIFT 8
-#define BCHP_SWITCH_CORE_TC_SEL_TABLE_Port_5_TC_SEL_4_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: TC_SEL_TABLE_Port_5 :: TC_SEL_3 [07:06] */
-#define BCHP_SWITCH_CORE_TC_SEL_TABLE_Port_5_TC_SEL_3_MASK 0x000000c0
-#define BCHP_SWITCH_CORE_TC_SEL_TABLE_Port_5_TC_SEL_3_SHIFT 6
-#define BCHP_SWITCH_CORE_TC_SEL_TABLE_Port_5_TC_SEL_3_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: TC_SEL_TABLE_Port_5 :: TC_SEL_2 [05:04] */
-#define BCHP_SWITCH_CORE_TC_SEL_TABLE_Port_5_TC_SEL_2_MASK 0x00000030
-#define BCHP_SWITCH_CORE_TC_SEL_TABLE_Port_5_TC_SEL_2_SHIFT 4
-#define BCHP_SWITCH_CORE_TC_SEL_TABLE_Port_5_TC_SEL_2_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: TC_SEL_TABLE_Port_5 :: TC_SEL_1 [03:02] */
-#define BCHP_SWITCH_CORE_TC_SEL_TABLE_Port_5_TC_SEL_1_MASK 0x0000000c
-#define BCHP_SWITCH_CORE_TC_SEL_TABLE_Port_5_TC_SEL_1_SHIFT 2
-#define BCHP_SWITCH_CORE_TC_SEL_TABLE_Port_5_TC_SEL_1_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: TC_SEL_TABLE_Port_5 :: TC_SEL_0 [01:00] */
-#define BCHP_SWITCH_CORE_TC_SEL_TABLE_Port_5_TC_SEL_0_MASK 0x00000003
-#define BCHP_SWITCH_CORE_TC_SEL_TABLE_Port_5_TC_SEL_0_SHIFT 0
-#define BCHP_SWITCH_CORE_TC_SEL_TABLE_Port_5_TC_SEL_0_DEFAULT 0x00000000
-
-/***************************************************************************
- *P7_TC_SEL_TABLE - Port 7 TC Select Table Register
- ***************************************************************************/
-/* SWITCH_CORE :: P7_TC_SEL_TABLE :: reserved_for_padding0 [31:16] */
-#define BCHP_SWITCH_CORE_P7_TC_SEL_TABLE_reserved_for_padding0_MASK 0xffff0000
-#define BCHP_SWITCH_CORE_P7_TC_SEL_TABLE_reserved_for_padding0_SHIFT 16
-
-/* SWITCH_CORE :: P7_TC_SEL_TABLE :: TC_SEL_7 [15:14] */
-#define BCHP_SWITCH_CORE_P7_TC_SEL_TABLE_TC_SEL_7_MASK 0x0000c000
-#define BCHP_SWITCH_CORE_P7_TC_SEL_TABLE_TC_SEL_7_SHIFT 14
-#define BCHP_SWITCH_CORE_P7_TC_SEL_TABLE_TC_SEL_7_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: P7_TC_SEL_TABLE :: TC_SEL_6 [13:12] */
-#define BCHP_SWITCH_CORE_P7_TC_SEL_TABLE_TC_SEL_6_MASK 0x00003000
-#define BCHP_SWITCH_CORE_P7_TC_SEL_TABLE_TC_SEL_6_SHIFT 12
-#define BCHP_SWITCH_CORE_P7_TC_SEL_TABLE_TC_SEL_6_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: P7_TC_SEL_TABLE :: TC_SEL_5 [11:10] */
-#define BCHP_SWITCH_CORE_P7_TC_SEL_TABLE_TC_SEL_5_MASK 0x00000c00
-#define BCHP_SWITCH_CORE_P7_TC_SEL_TABLE_TC_SEL_5_SHIFT 10
-#define BCHP_SWITCH_CORE_P7_TC_SEL_TABLE_TC_SEL_5_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: P7_TC_SEL_TABLE :: TC_SEL_4 [09:08] */
-#define BCHP_SWITCH_CORE_P7_TC_SEL_TABLE_TC_SEL_4_MASK 0x00000300
-#define BCHP_SWITCH_CORE_P7_TC_SEL_TABLE_TC_SEL_4_SHIFT 8
-#define BCHP_SWITCH_CORE_P7_TC_SEL_TABLE_TC_SEL_4_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: P7_TC_SEL_TABLE :: TC_SEL_3 [07:06] */
-#define BCHP_SWITCH_CORE_P7_TC_SEL_TABLE_TC_SEL_3_MASK 0x000000c0
-#define BCHP_SWITCH_CORE_P7_TC_SEL_TABLE_TC_SEL_3_SHIFT 6
-#define BCHP_SWITCH_CORE_P7_TC_SEL_TABLE_TC_SEL_3_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: P7_TC_SEL_TABLE :: TC_SEL_2 [05:04] */
-#define BCHP_SWITCH_CORE_P7_TC_SEL_TABLE_TC_SEL_2_MASK 0x00000030
-#define BCHP_SWITCH_CORE_P7_TC_SEL_TABLE_TC_SEL_2_SHIFT 4
-#define BCHP_SWITCH_CORE_P7_TC_SEL_TABLE_TC_SEL_2_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: P7_TC_SEL_TABLE :: TC_SEL_1 [03:02] */
-#define BCHP_SWITCH_CORE_P7_TC_SEL_TABLE_TC_SEL_1_MASK 0x0000000c
-#define BCHP_SWITCH_CORE_P7_TC_SEL_TABLE_TC_SEL_1_SHIFT 2
-#define BCHP_SWITCH_CORE_P7_TC_SEL_TABLE_TC_SEL_1_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: P7_TC_SEL_TABLE :: TC_SEL_0 [01:00] */
-#define BCHP_SWITCH_CORE_P7_TC_SEL_TABLE_TC_SEL_0_MASK 0x00000003
-#define BCHP_SWITCH_CORE_P7_TC_SEL_TABLE_TC_SEL_0_SHIFT 0
-#define BCHP_SWITCH_CORE_P7_TC_SEL_TABLE_TC_SEL_0_DEFAULT 0x00000000
-
-/***************************************************************************
- *IMP_TC_SEL_TABLE - Port 8 TC Select Table Register
- ***************************************************************************/
-/* SWITCH_CORE :: IMP_TC_SEL_TABLE :: reserved_for_padding0 [31:16] */
-#define BCHP_SWITCH_CORE_IMP_TC_SEL_TABLE_reserved_for_padding0_MASK 0xffff0000
-#define BCHP_SWITCH_CORE_IMP_TC_SEL_TABLE_reserved_for_padding0_SHIFT 16
-
-/* SWITCH_CORE :: IMP_TC_SEL_TABLE :: TC_SEL_7 [15:14] */
-#define BCHP_SWITCH_CORE_IMP_TC_SEL_TABLE_TC_SEL_7_MASK 0x0000c000
-#define BCHP_SWITCH_CORE_IMP_TC_SEL_TABLE_TC_SEL_7_SHIFT 14
-#define BCHP_SWITCH_CORE_IMP_TC_SEL_TABLE_TC_SEL_7_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: IMP_TC_SEL_TABLE :: TC_SEL_6 [13:12] */
-#define BCHP_SWITCH_CORE_IMP_TC_SEL_TABLE_TC_SEL_6_MASK 0x00003000
-#define BCHP_SWITCH_CORE_IMP_TC_SEL_TABLE_TC_SEL_6_SHIFT 12
-#define BCHP_SWITCH_CORE_IMP_TC_SEL_TABLE_TC_SEL_6_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: IMP_TC_SEL_TABLE :: TC_SEL_5 [11:10] */
-#define BCHP_SWITCH_CORE_IMP_TC_SEL_TABLE_TC_SEL_5_MASK 0x00000c00
-#define BCHP_SWITCH_CORE_IMP_TC_SEL_TABLE_TC_SEL_5_SHIFT 10
-#define BCHP_SWITCH_CORE_IMP_TC_SEL_TABLE_TC_SEL_5_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: IMP_TC_SEL_TABLE :: TC_SEL_4 [09:08] */
-#define BCHP_SWITCH_CORE_IMP_TC_SEL_TABLE_TC_SEL_4_MASK 0x00000300
-#define BCHP_SWITCH_CORE_IMP_TC_SEL_TABLE_TC_SEL_4_SHIFT 8
-#define BCHP_SWITCH_CORE_IMP_TC_SEL_TABLE_TC_SEL_4_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: IMP_TC_SEL_TABLE :: TC_SEL_3 [07:06] */
-#define BCHP_SWITCH_CORE_IMP_TC_SEL_TABLE_TC_SEL_3_MASK 0x000000c0
-#define BCHP_SWITCH_CORE_IMP_TC_SEL_TABLE_TC_SEL_3_SHIFT 6
-#define BCHP_SWITCH_CORE_IMP_TC_SEL_TABLE_TC_SEL_3_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: IMP_TC_SEL_TABLE :: TC_SEL_2 [05:04] */
-#define BCHP_SWITCH_CORE_IMP_TC_SEL_TABLE_TC_SEL_2_MASK 0x00000030
-#define BCHP_SWITCH_CORE_IMP_TC_SEL_TABLE_TC_SEL_2_SHIFT 4
-#define BCHP_SWITCH_CORE_IMP_TC_SEL_TABLE_TC_SEL_2_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: IMP_TC_SEL_TABLE :: TC_SEL_1 [03:02] */
-#define BCHP_SWITCH_CORE_IMP_TC_SEL_TABLE_TC_SEL_1_MASK 0x0000000c
-#define BCHP_SWITCH_CORE_IMP_TC_SEL_TABLE_TC_SEL_1_SHIFT 2
-#define BCHP_SWITCH_CORE_IMP_TC_SEL_TABLE_TC_SEL_1_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: IMP_TC_SEL_TABLE :: TC_SEL_0 [01:00] */
-#define BCHP_SWITCH_CORE_IMP_TC_SEL_TABLE_TC_SEL_0_MASK 0x00000003
-#define BCHP_SWITCH_CORE_IMP_TC_SEL_TABLE_TC_SEL_0_SHIFT 0
-#define BCHP_SWITCH_CORE_IMP_TC_SEL_TABLE_TC_SEL_0_DEFAULT 0x00000000
-
-/***************************************************************************
- *CPU2COS_MAP - CPU to COS Mapping Register
- ***************************************************************************/
-/* SWITCH_CORE :: CPU2COS_MAP :: SWITCH_RESV [31:18] */
-#define BCHP_SWITCH_CORE_CPU2COS_MAP_SWITCH_RESV_MASK 0xfffc0000
-#define BCHP_SWITCH_CORE_CPU2COS_MAP_SWITCH_RESV_SHIFT 18
-#define BCHP_SWITCH_CORE_CPU2COS_MAP_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: CPU2COS_MAP :: EXCPT_PRCS [17:15] */
-#define BCHP_SWITCH_CORE_CPU2COS_MAP_EXCPT_PRCS_MASK 0x00038000
-#define BCHP_SWITCH_CORE_CPU2COS_MAP_EXCPT_PRCS_SHIFT 15
-#define BCHP_SWITCH_CORE_CPU2COS_MAP_EXCPT_PRCS_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: CPU2COS_MAP :: PRTC_SNOOP [14:12] */
-#define BCHP_SWITCH_CORE_CPU2COS_MAP_PRTC_SNOOP_MASK 0x00007000
-#define BCHP_SWITCH_CORE_CPU2COS_MAP_PRTC_SNOOP_SHIFT 12
-#define BCHP_SWITCH_CORE_CPU2COS_MAP_PRTC_SNOOP_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: CPU2COS_MAP :: PRTC_TRMNT [11:09] */
-#define BCHP_SWITCH_CORE_CPU2COS_MAP_PRTC_TRMNT_MASK 0x00000e00
-#define BCHP_SWITCH_CORE_CPU2COS_MAP_PRTC_TRMNT_SHIFT 9
-#define BCHP_SWITCH_CORE_CPU2COS_MAP_PRTC_TRMNT_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: CPU2COS_MAP :: SW_FLD [08:06] */
-#define BCHP_SWITCH_CORE_CPU2COS_MAP_SW_FLD_MASK 0x000001c0
-#define BCHP_SWITCH_CORE_CPU2COS_MAP_SW_FLD_SHIFT 6
-#define BCHP_SWITCH_CORE_CPU2COS_MAP_SW_FLD_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: CPU2COS_MAP :: SA_LRN [05:03] */
-#define BCHP_SWITCH_CORE_CPU2COS_MAP_SA_LRN_MASK 0x00000038
-#define BCHP_SWITCH_CORE_CPU2COS_MAP_SA_LRN_SHIFT 3
-#define BCHP_SWITCH_CORE_CPU2COS_MAP_SA_LRN_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: CPU2COS_MAP :: MIRROR [02:00] */
-#define BCHP_SWITCH_CORE_CPU2COS_MAP_MIRROR_MASK 0x00000007
-#define BCHP_SWITCH_CORE_CPU2COS_MAP_MIRROR_SHIFT 0
-#define BCHP_SWITCH_CORE_CPU2COS_MAP_MIRROR_DEFAULT 0x00000000
-
-/***************************************************************************
- *PN_TC2COS_MAP_Port_0 - Port N TC to COS Mapping Register
- ***************************************************************************/
-/* SWITCH_CORE :: PN_TC2COS_MAP_Port_0 :: BCAST_DLF_DROP_TC [31:24] */
-#define BCHP_SWITCH_CORE_PN_TC2COS_MAP_Port_0_BCAST_DLF_DROP_TC_MASK 0xff000000
-#define BCHP_SWITCH_CORE_PN_TC2COS_MAP_Port_0_BCAST_DLF_DROP_TC_SHIFT 24
-#define BCHP_SWITCH_CORE_PN_TC2COS_MAP_Port_0_BCAST_DLF_DROP_TC_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: PN_TC2COS_MAP_Port_0 :: PRT111_TO_QID [23:21] */
-#define BCHP_SWITCH_CORE_PN_TC2COS_MAP_Port_0_PRT111_TO_QID_MASK 0x00e00000
-#define BCHP_SWITCH_CORE_PN_TC2COS_MAP_Port_0_PRT111_TO_QID_SHIFT 21
-#define BCHP_SWITCH_CORE_PN_TC2COS_MAP_Port_0_PRT111_TO_QID_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: PN_TC2COS_MAP_Port_0 :: PRT110_TO_QID [20:18] */
-#define BCHP_SWITCH_CORE_PN_TC2COS_MAP_Port_0_PRT110_TO_QID_MASK 0x001c0000
-#define BCHP_SWITCH_CORE_PN_TC2COS_MAP_Port_0_PRT110_TO_QID_SHIFT 18
-#define BCHP_SWITCH_CORE_PN_TC2COS_MAP_Port_0_PRT110_TO_QID_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: PN_TC2COS_MAP_Port_0 :: PRT101_TO_QID [17:15] */
-#define BCHP_SWITCH_CORE_PN_TC2COS_MAP_Port_0_PRT101_TO_QID_MASK 0x00038000
-#define BCHP_SWITCH_CORE_PN_TC2COS_MAP_Port_0_PRT101_TO_QID_SHIFT 15
-#define BCHP_SWITCH_CORE_PN_TC2COS_MAP_Port_0_PRT101_TO_QID_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: PN_TC2COS_MAP_Port_0 :: PRT100_TO_QID [14:12] */
-#define BCHP_SWITCH_CORE_PN_TC2COS_MAP_Port_0_PRT100_TO_QID_MASK 0x00007000
-#define BCHP_SWITCH_CORE_PN_TC2COS_MAP_Port_0_PRT100_TO_QID_SHIFT 12
-#define BCHP_SWITCH_CORE_PN_TC2COS_MAP_Port_0_PRT100_TO_QID_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: PN_TC2COS_MAP_Port_0 :: PRT011_TO_QID [11:09] */
-#define BCHP_SWITCH_CORE_PN_TC2COS_MAP_Port_0_PRT011_TO_QID_MASK 0x00000e00
-#define BCHP_SWITCH_CORE_PN_TC2COS_MAP_Port_0_PRT011_TO_QID_SHIFT 9
-#define BCHP_SWITCH_CORE_PN_TC2COS_MAP_Port_0_PRT011_TO_QID_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: PN_TC2COS_MAP_Port_0 :: PRT010_TO_QID [08:06] */
-#define BCHP_SWITCH_CORE_PN_TC2COS_MAP_Port_0_PRT010_TO_QID_MASK 0x000001c0
-#define BCHP_SWITCH_CORE_PN_TC2COS_MAP_Port_0_PRT010_TO_QID_SHIFT 6
-#define BCHP_SWITCH_CORE_PN_TC2COS_MAP_Port_0_PRT010_TO_QID_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: PN_TC2COS_MAP_Port_0 :: PRT001_TO_QID [05:03] */
-#define BCHP_SWITCH_CORE_PN_TC2COS_MAP_Port_0_PRT001_TO_QID_MASK 0x00000038
-#define BCHP_SWITCH_CORE_PN_TC2COS_MAP_Port_0_PRT001_TO_QID_SHIFT 3
-#define BCHP_SWITCH_CORE_PN_TC2COS_MAP_Port_0_PRT001_TO_QID_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: PN_TC2COS_MAP_Port_0 :: PRT000_TO_QID [02:00] */
-#define BCHP_SWITCH_CORE_PN_TC2COS_MAP_Port_0_PRT000_TO_QID_MASK 0x00000007
-#define BCHP_SWITCH_CORE_PN_TC2COS_MAP_Port_0_PRT000_TO_QID_SHIFT 0
-#define BCHP_SWITCH_CORE_PN_TC2COS_MAP_Port_0_PRT000_TO_QID_DEFAULT 0x00000000
-
-/***************************************************************************
- *PN_TC2COS_MAP_Port_1 - Port N TC to COS Mapping Register
- ***************************************************************************/
-/* SWITCH_CORE :: PN_TC2COS_MAP_Port_1 :: BCAST_DLF_DROP_TC [31:24] */
-#define BCHP_SWITCH_CORE_PN_TC2COS_MAP_Port_1_BCAST_DLF_DROP_TC_MASK 0xff000000
-#define BCHP_SWITCH_CORE_PN_TC2COS_MAP_Port_1_BCAST_DLF_DROP_TC_SHIFT 24
-#define BCHP_SWITCH_CORE_PN_TC2COS_MAP_Port_1_BCAST_DLF_DROP_TC_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: PN_TC2COS_MAP_Port_1 :: PRT111_TO_QID [23:21] */
-#define BCHP_SWITCH_CORE_PN_TC2COS_MAP_Port_1_PRT111_TO_QID_MASK 0x00e00000
-#define BCHP_SWITCH_CORE_PN_TC2COS_MAP_Port_1_PRT111_TO_QID_SHIFT 21
-#define BCHP_SWITCH_CORE_PN_TC2COS_MAP_Port_1_PRT111_TO_QID_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: PN_TC2COS_MAP_Port_1 :: PRT110_TO_QID [20:18] */
-#define BCHP_SWITCH_CORE_PN_TC2COS_MAP_Port_1_PRT110_TO_QID_MASK 0x001c0000
-#define BCHP_SWITCH_CORE_PN_TC2COS_MAP_Port_1_PRT110_TO_QID_SHIFT 18
-#define BCHP_SWITCH_CORE_PN_TC2COS_MAP_Port_1_PRT110_TO_QID_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: PN_TC2COS_MAP_Port_1 :: PRT101_TO_QID [17:15] */
-#define BCHP_SWITCH_CORE_PN_TC2COS_MAP_Port_1_PRT101_TO_QID_MASK 0x00038000
-#define BCHP_SWITCH_CORE_PN_TC2COS_MAP_Port_1_PRT101_TO_QID_SHIFT 15
-#define BCHP_SWITCH_CORE_PN_TC2COS_MAP_Port_1_PRT101_TO_QID_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: PN_TC2COS_MAP_Port_1 :: PRT100_TO_QID [14:12] */
-#define BCHP_SWITCH_CORE_PN_TC2COS_MAP_Port_1_PRT100_TO_QID_MASK 0x00007000
-#define BCHP_SWITCH_CORE_PN_TC2COS_MAP_Port_1_PRT100_TO_QID_SHIFT 12
-#define BCHP_SWITCH_CORE_PN_TC2COS_MAP_Port_1_PRT100_TO_QID_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: PN_TC2COS_MAP_Port_1 :: PRT011_TO_QID [11:09] */
-#define BCHP_SWITCH_CORE_PN_TC2COS_MAP_Port_1_PRT011_TO_QID_MASK 0x00000e00
-#define BCHP_SWITCH_CORE_PN_TC2COS_MAP_Port_1_PRT011_TO_QID_SHIFT 9
-#define BCHP_SWITCH_CORE_PN_TC2COS_MAP_Port_1_PRT011_TO_QID_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: PN_TC2COS_MAP_Port_1 :: PRT010_TO_QID [08:06] */
-#define BCHP_SWITCH_CORE_PN_TC2COS_MAP_Port_1_PRT010_TO_QID_MASK 0x000001c0
-#define BCHP_SWITCH_CORE_PN_TC2COS_MAP_Port_1_PRT010_TO_QID_SHIFT 6
-#define BCHP_SWITCH_CORE_PN_TC2COS_MAP_Port_1_PRT010_TO_QID_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: PN_TC2COS_MAP_Port_1 :: PRT001_TO_QID [05:03] */
-#define BCHP_SWITCH_CORE_PN_TC2COS_MAP_Port_1_PRT001_TO_QID_MASK 0x00000038
-#define BCHP_SWITCH_CORE_PN_TC2COS_MAP_Port_1_PRT001_TO_QID_SHIFT 3
-#define BCHP_SWITCH_CORE_PN_TC2COS_MAP_Port_1_PRT001_TO_QID_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: PN_TC2COS_MAP_Port_1 :: PRT000_TO_QID [02:00] */
-#define BCHP_SWITCH_CORE_PN_TC2COS_MAP_Port_1_PRT000_TO_QID_MASK 0x00000007
-#define BCHP_SWITCH_CORE_PN_TC2COS_MAP_Port_1_PRT000_TO_QID_SHIFT 0
-#define BCHP_SWITCH_CORE_PN_TC2COS_MAP_Port_1_PRT000_TO_QID_DEFAULT 0x00000000
-
-/***************************************************************************
- *PN_TC2COS_MAP_Port_2 - Port N TC to COS Mapping Register
- ***************************************************************************/
-/* SWITCH_CORE :: PN_TC2COS_MAP_Port_2 :: BCAST_DLF_DROP_TC [31:24] */
-#define BCHP_SWITCH_CORE_PN_TC2COS_MAP_Port_2_BCAST_DLF_DROP_TC_MASK 0xff000000
-#define BCHP_SWITCH_CORE_PN_TC2COS_MAP_Port_2_BCAST_DLF_DROP_TC_SHIFT 24
-#define BCHP_SWITCH_CORE_PN_TC2COS_MAP_Port_2_BCAST_DLF_DROP_TC_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: PN_TC2COS_MAP_Port_2 :: PRT111_TO_QID [23:21] */
-#define BCHP_SWITCH_CORE_PN_TC2COS_MAP_Port_2_PRT111_TO_QID_MASK 0x00e00000
-#define BCHP_SWITCH_CORE_PN_TC2COS_MAP_Port_2_PRT111_TO_QID_SHIFT 21
-#define BCHP_SWITCH_CORE_PN_TC2COS_MAP_Port_2_PRT111_TO_QID_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: PN_TC2COS_MAP_Port_2 :: PRT110_TO_QID [20:18] */
-#define BCHP_SWITCH_CORE_PN_TC2COS_MAP_Port_2_PRT110_TO_QID_MASK 0x001c0000
-#define BCHP_SWITCH_CORE_PN_TC2COS_MAP_Port_2_PRT110_TO_QID_SHIFT 18
-#define BCHP_SWITCH_CORE_PN_TC2COS_MAP_Port_2_PRT110_TO_QID_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: PN_TC2COS_MAP_Port_2 :: PRT101_TO_QID [17:15] */
-#define BCHP_SWITCH_CORE_PN_TC2COS_MAP_Port_2_PRT101_TO_QID_MASK 0x00038000
-#define BCHP_SWITCH_CORE_PN_TC2COS_MAP_Port_2_PRT101_TO_QID_SHIFT 15
-#define BCHP_SWITCH_CORE_PN_TC2COS_MAP_Port_2_PRT101_TO_QID_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: PN_TC2COS_MAP_Port_2 :: PRT100_TO_QID [14:12] */
-#define BCHP_SWITCH_CORE_PN_TC2COS_MAP_Port_2_PRT100_TO_QID_MASK 0x00007000
-#define BCHP_SWITCH_CORE_PN_TC2COS_MAP_Port_2_PRT100_TO_QID_SHIFT 12
-#define BCHP_SWITCH_CORE_PN_TC2COS_MAP_Port_2_PRT100_TO_QID_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: PN_TC2COS_MAP_Port_2 :: PRT011_TO_QID [11:09] */
-#define BCHP_SWITCH_CORE_PN_TC2COS_MAP_Port_2_PRT011_TO_QID_MASK 0x00000e00
-#define BCHP_SWITCH_CORE_PN_TC2COS_MAP_Port_2_PRT011_TO_QID_SHIFT 9
-#define BCHP_SWITCH_CORE_PN_TC2COS_MAP_Port_2_PRT011_TO_QID_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: PN_TC2COS_MAP_Port_2 :: PRT010_TO_QID [08:06] */
-#define BCHP_SWITCH_CORE_PN_TC2COS_MAP_Port_2_PRT010_TO_QID_MASK 0x000001c0
-#define BCHP_SWITCH_CORE_PN_TC2COS_MAP_Port_2_PRT010_TO_QID_SHIFT 6
-#define BCHP_SWITCH_CORE_PN_TC2COS_MAP_Port_2_PRT010_TO_QID_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: PN_TC2COS_MAP_Port_2 :: PRT001_TO_QID [05:03] */
-#define BCHP_SWITCH_CORE_PN_TC2COS_MAP_Port_2_PRT001_TO_QID_MASK 0x00000038
-#define BCHP_SWITCH_CORE_PN_TC2COS_MAP_Port_2_PRT001_TO_QID_SHIFT 3
-#define BCHP_SWITCH_CORE_PN_TC2COS_MAP_Port_2_PRT001_TO_QID_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: PN_TC2COS_MAP_Port_2 :: PRT000_TO_QID [02:00] */
-#define BCHP_SWITCH_CORE_PN_TC2COS_MAP_Port_2_PRT000_TO_QID_MASK 0x00000007
-#define BCHP_SWITCH_CORE_PN_TC2COS_MAP_Port_2_PRT000_TO_QID_SHIFT 0
-#define BCHP_SWITCH_CORE_PN_TC2COS_MAP_Port_2_PRT000_TO_QID_DEFAULT 0x00000000
-
-/***************************************************************************
- *PN_TC2COS_MAP_Port_3 - Port N TC to COS Mapping Register
- ***************************************************************************/
-/* SWITCH_CORE :: PN_TC2COS_MAP_Port_3 :: BCAST_DLF_DROP_TC [31:24] */
-#define BCHP_SWITCH_CORE_PN_TC2COS_MAP_Port_3_BCAST_DLF_DROP_TC_MASK 0xff000000
-#define BCHP_SWITCH_CORE_PN_TC2COS_MAP_Port_3_BCAST_DLF_DROP_TC_SHIFT 24
-#define BCHP_SWITCH_CORE_PN_TC2COS_MAP_Port_3_BCAST_DLF_DROP_TC_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: PN_TC2COS_MAP_Port_3 :: PRT111_TO_QID [23:21] */
-#define BCHP_SWITCH_CORE_PN_TC2COS_MAP_Port_3_PRT111_TO_QID_MASK 0x00e00000
-#define BCHP_SWITCH_CORE_PN_TC2COS_MAP_Port_3_PRT111_TO_QID_SHIFT 21
-#define BCHP_SWITCH_CORE_PN_TC2COS_MAP_Port_3_PRT111_TO_QID_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: PN_TC2COS_MAP_Port_3 :: PRT110_TO_QID [20:18] */
-#define BCHP_SWITCH_CORE_PN_TC2COS_MAP_Port_3_PRT110_TO_QID_MASK 0x001c0000
-#define BCHP_SWITCH_CORE_PN_TC2COS_MAP_Port_3_PRT110_TO_QID_SHIFT 18
-#define BCHP_SWITCH_CORE_PN_TC2COS_MAP_Port_3_PRT110_TO_QID_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: PN_TC2COS_MAP_Port_3 :: PRT101_TO_QID [17:15] */
-#define BCHP_SWITCH_CORE_PN_TC2COS_MAP_Port_3_PRT101_TO_QID_MASK 0x00038000
-#define BCHP_SWITCH_CORE_PN_TC2COS_MAP_Port_3_PRT101_TO_QID_SHIFT 15
-#define BCHP_SWITCH_CORE_PN_TC2COS_MAP_Port_3_PRT101_TO_QID_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: PN_TC2COS_MAP_Port_3 :: PRT100_TO_QID [14:12] */
-#define BCHP_SWITCH_CORE_PN_TC2COS_MAP_Port_3_PRT100_TO_QID_MASK 0x00007000
-#define BCHP_SWITCH_CORE_PN_TC2COS_MAP_Port_3_PRT100_TO_QID_SHIFT 12
-#define BCHP_SWITCH_CORE_PN_TC2COS_MAP_Port_3_PRT100_TO_QID_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: PN_TC2COS_MAP_Port_3 :: PRT011_TO_QID [11:09] */
-#define BCHP_SWITCH_CORE_PN_TC2COS_MAP_Port_3_PRT011_TO_QID_MASK 0x00000e00
-#define BCHP_SWITCH_CORE_PN_TC2COS_MAP_Port_3_PRT011_TO_QID_SHIFT 9
-#define BCHP_SWITCH_CORE_PN_TC2COS_MAP_Port_3_PRT011_TO_QID_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: PN_TC2COS_MAP_Port_3 :: PRT010_TO_QID [08:06] */
-#define BCHP_SWITCH_CORE_PN_TC2COS_MAP_Port_3_PRT010_TO_QID_MASK 0x000001c0
-#define BCHP_SWITCH_CORE_PN_TC2COS_MAP_Port_3_PRT010_TO_QID_SHIFT 6
-#define BCHP_SWITCH_CORE_PN_TC2COS_MAP_Port_3_PRT010_TO_QID_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: PN_TC2COS_MAP_Port_3 :: PRT001_TO_QID [05:03] */
-#define BCHP_SWITCH_CORE_PN_TC2COS_MAP_Port_3_PRT001_TO_QID_MASK 0x00000038
-#define BCHP_SWITCH_CORE_PN_TC2COS_MAP_Port_3_PRT001_TO_QID_SHIFT 3
-#define BCHP_SWITCH_CORE_PN_TC2COS_MAP_Port_3_PRT001_TO_QID_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: PN_TC2COS_MAP_Port_3 :: PRT000_TO_QID [02:00] */
-#define BCHP_SWITCH_CORE_PN_TC2COS_MAP_Port_3_PRT000_TO_QID_MASK 0x00000007
-#define BCHP_SWITCH_CORE_PN_TC2COS_MAP_Port_3_PRT000_TO_QID_SHIFT 0
-#define BCHP_SWITCH_CORE_PN_TC2COS_MAP_Port_3_PRT000_TO_QID_DEFAULT 0x00000000
-
-/***************************************************************************
- *PN_TC2COS_MAP_Port_4 - Port N TC to COS Mapping Register
- ***************************************************************************/
-/* SWITCH_CORE :: PN_TC2COS_MAP_Port_4 :: BCAST_DLF_DROP_TC [31:24] */
-#define BCHP_SWITCH_CORE_PN_TC2COS_MAP_Port_4_BCAST_DLF_DROP_TC_MASK 0xff000000
-#define BCHP_SWITCH_CORE_PN_TC2COS_MAP_Port_4_BCAST_DLF_DROP_TC_SHIFT 24
-#define BCHP_SWITCH_CORE_PN_TC2COS_MAP_Port_4_BCAST_DLF_DROP_TC_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: PN_TC2COS_MAP_Port_4 :: PRT111_TO_QID [23:21] */
-#define BCHP_SWITCH_CORE_PN_TC2COS_MAP_Port_4_PRT111_TO_QID_MASK 0x00e00000
-#define BCHP_SWITCH_CORE_PN_TC2COS_MAP_Port_4_PRT111_TO_QID_SHIFT 21
-#define BCHP_SWITCH_CORE_PN_TC2COS_MAP_Port_4_PRT111_TO_QID_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: PN_TC2COS_MAP_Port_4 :: PRT110_TO_QID [20:18] */
-#define BCHP_SWITCH_CORE_PN_TC2COS_MAP_Port_4_PRT110_TO_QID_MASK 0x001c0000
-#define BCHP_SWITCH_CORE_PN_TC2COS_MAP_Port_4_PRT110_TO_QID_SHIFT 18
-#define BCHP_SWITCH_CORE_PN_TC2COS_MAP_Port_4_PRT110_TO_QID_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: PN_TC2COS_MAP_Port_4 :: PRT101_TO_QID [17:15] */
-#define BCHP_SWITCH_CORE_PN_TC2COS_MAP_Port_4_PRT101_TO_QID_MASK 0x00038000
-#define BCHP_SWITCH_CORE_PN_TC2COS_MAP_Port_4_PRT101_TO_QID_SHIFT 15
-#define BCHP_SWITCH_CORE_PN_TC2COS_MAP_Port_4_PRT101_TO_QID_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: PN_TC2COS_MAP_Port_4 :: PRT100_TO_QID [14:12] */
-#define BCHP_SWITCH_CORE_PN_TC2COS_MAP_Port_4_PRT100_TO_QID_MASK 0x00007000
-#define BCHP_SWITCH_CORE_PN_TC2COS_MAP_Port_4_PRT100_TO_QID_SHIFT 12
-#define BCHP_SWITCH_CORE_PN_TC2COS_MAP_Port_4_PRT100_TO_QID_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: PN_TC2COS_MAP_Port_4 :: PRT011_TO_QID [11:09] */
-#define BCHP_SWITCH_CORE_PN_TC2COS_MAP_Port_4_PRT011_TO_QID_MASK 0x00000e00
-#define BCHP_SWITCH_CORE_PN_TC2COS_MAP_Port_4_PRT011_TO_QID_SHIFT 9
-#define BCHP_SWITCH_CORE_PN_TC2COS_MAP_Port_4_PRT011_TO_QID_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: PN_TC2COS_MAP_Port_4 :: PRT010_TO_QID [08:06] */
-#define BCHP_SWITCH_CORE_PN_TC2COS_MAP_Port_4_PRT010_TO_QID_MASK 0x000001c0
-#define BCHP_SWITCH_CORE_PN_TC2COS_MAP_Port_4_PRT010_TO_QID_SHIFT 6
-#define BCHP_SWITCH_CORE_PN_TC2COS_MAP_Port_4_PRT010_TO_QID_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: PN_TC2COS_MAP_Port_4 :: PRT001_TO_QID [05:03] */
-#define BCHP_SWITCH_CORE_PN_TC2COS_MAP_Port_4_PRT001_TO_QID_MASK 0x00000038
-#define BCHP_SWITCH_CORE_PN_TC2COS_MAP_Port_4_PRT001_TO_QID_SHIFT 3
-#define BCHP_SWITCH_CORE_PN_TC2COS_MAP_Port_4_PRT001_TO_QID_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: PN_TC2COS_MAP_Port_4 :: PRT000_TO_QID [02:00] */
-#define BCHP_SWITCH_CORE_PN_TC2COS_MAP_Port_4_PRT000_TO_QID_MASK 0x00000007
-#define BCHP_SWITCH_CORE_PN_TC2COS_MAP_Port_4_PRT000_TO_QID_SHIFT 0
-#define BCHP_SWITCH_CORE_PN_TC2COS_MAP_Port_4_PRT000_TO_QID_DEFAULT 0x00000000
-
-/***************************************************************************
- *PN_TC2COS_MAP_Port_5 - Port N TC to COS Mapping Register
- ***************************************************************************/
-/* SWITCH_CORE :: PN_TC2COS_MAP_Port_5 :: BCAST_DLF_DROP_TC [31:24] */
-#define BCHP_SWITCH_CORE_PN_TC2COS_MAP_Port_5_BCAST_DLF_DROP_TC_MASK 0xff000000
-#define BCHP_SWITCH_CORE_PN_TC2COS_MAP_Port_5_BCAST_DLF_DROP_TC_SHIFT 24
-#define BCHP_SWITCH_CORE_PN_TC2COS_MAP_Port_5_BCAST_DLF_DROP_TC_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: PN_TC2COS_MAP_Port_5 :: PRT111_TO_QID [23:21] */
-#define BCHP_SWITCH_CORE_PN_TC2COS_MAP_Port_5_PRT111_TO_QID_MASK 0x00e00000
-#define BCHP_SWITCH_CORE_PN_TC2COS_MAP_Port_5_PRT111_TO_QID_SHIFT 21
-#define BCHP_SWITCH_CORE_PN_TC2COS_MAP_Port_5_PRT111_TO_QID_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: PN_TC2COS_MAP_Port_5 :: PRT110_TO_QID [20:18] */
-#define BCHP_SWITCH_CORE_PN_TC2COS_MAP_Port_5_PRT110_TO_QID_MASK 0x001c0000
-#define BCHP_SWITCH_CORE_PN_TC2COS_MAP_Port_5_PRT110_TO_QID_SHIFT 18
-#define BCHP_SWITCH_CORE_PN_TC2COS_MAP_Port_5_PRT110_TO_QID_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: PN_TC2COS_MAP_Port_5 :: PRT101_TO_QID [17:15] */
-#define BCHP_SWITCH_CORE_PN_TC2COS_MAP_Port_5_PRT101_TO_QID_MASK 0x00038000
-#define BCHP_SWITCH_CORE_PN_TC2COS_MAP_Port_5_PRT101_TO_QID_SHIFT 15
-#define BCHP_SWITCH_CORE_PN_TC2COS_MAP_Port_5_PRT101_TO_QID_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: PN_TC2COS_MAP_Port_5 :: PRT100_TO_QID [14:12] */
-#define BCHP_SWITCH_CORE_PN_TC2COS_MAP_Port_5_PRT100_TO_QID_MASK 0x00007000
-#define BCHP_SWITCH_CORE_PN_TC2COS_MAP_Port_5_PRT100_TO_QID_SHIFT 12
-#define BCHP_SWITCH_CORE_PN_TC2COS_MAP_Port_5_PRT100_TO_QID_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: PN_TC2COS_MAP_Port_5 :: PRT011_TO_QID [11:09] */
-#define BCHP_SWITCH_CORE_PN_TC2COS_MAP_Port_5_PRT011_TO_QID_MASK 0x00000e00
-#define BCHP_SWITCH_CORE_PN_TC2COS_MAP_Port_5_PRT011_TO_QID_SHIFT 9
-#define BCHP_SWITCH_CORE_PN_TC2COS_MAP_Port_5_PRT011_TO_QID_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: PN_TC2COS_MAP_Port_5 :: PRT010_TO_QID [08:06] */
-#define BCHP_SWITCH_CORE_PN_TC2COS_MAP_Port_5_PRT010_TO_QID_MASK 0x000001c0
-#define BCHP_SWITCH_CORE_PN_TC2COS_MAP_Port_5_PRT010_TO_QID_SHIFT 6
-#define BCHP_SWITCH_CORE_PN_TC2COS_MAP_Port_5_PRT010_TO_QID_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: PN_TC2COS_MAP_Port_5 :: PRT001_TO_QID [05:03] */
-#define BCHP_SWITCH_CORE_PN_TC2COS_MAP_Port_5_PRT001_TO_QID_MASK 0x00000038
-#define BCHP_SWITCH_CORE_PN_TC2COS_MAP_Port_5_PRT001_TO_QID_SHIFT 3
-#define BCHP_SWITCH_CORE_PN_TC2COS_MAP_Port_5_PRT001_TO_QID_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: PN_TC2COS_MAP_Port_5 :: PRT000_TO_QID [02:00] */
-#define BCHP_SWITCH_CORE_PN_TC2COS_MAP_Port_5_PRT000_TO_QID_MASK 0x00000007
-#define BCHP_SWITCH_CORE_PN_TC2COS_MAP_Port_5_PRT000_TO_QID_SHIFT 0
-#define BCHP_SWITCH_CORE_PN_TC2COS_MAP_Port_5_PRT000_TO_QID_DEFAULT 0x00000000
-
-/***************************************************************************
- *P7_TC2COS_MAP - Port 7 TC to COS Mapping Register
- ***************************************************************************/
-/* SWITCH_CORE :: P7_TC2COS_MAP :: BCAST_DLF_DROP_TC [31:24] */
-#define BCHP_SWITCH_CORE_P7_TC2COS_MAP_BCAST_DLF_DROP_TC_MASK 0xff000000
-#define BCHP_SWITCH_CORE_P7_TC2COS_MAP_BCAST_DLF_DROP_TC_SHIFT 24
-#define BCHP_SWITCH_CORE_P7_TC2COS_MAP_BCAST_DLF_DROP_TC_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: P7_TC2COS_MAP :: PRT111_TO_QID [23:21] */
-#define BCHP_SWITCH_CORE_P7_TC2COS_MAP_PRT111_TO_QID_MASK 0x00e00000
-#define BCHP_SWITCH_CORE_P7_TC2COS_MAP_PRT111_TO_QID_SHIFT 21
-#define BCHP_SWITCH_CORE_P7_TC2COS_MAP_PRT111_TO_QID_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: P7_TC2COS_MAP :: PRT110_TO_QID [20:18] */
-#define BCHP_SWITCH_CORE_P7_TC2COS_MAP_PRT110_TO_QID_MASK 0x001c0000
-#define BCHP_SWITCH_CORE_P7_TC2COS_MAP_PRT110_TO_QID_SHIFT 18
-#define BCHP_SWITCH_CORE_P7_TC2COS_MAP_PRT110_TO_QID_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: P7_TC2COS_MAP :: PRT101_TO_QID [17:15] */
-#define BCHP_SWITCH_CORE_P7_TC2COS_MAP_PRT101_TO_QID_MASK 0x00038000
-#define BCHP_SWITCH_CORE_P7_TC2COS_MAP_PRT101_TO_QID_SHIFT 15
-#define BCHP_SWITCH_CORE_P7_TC2COS_MAP_PRT101_TO_QID_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: P7_TC2COS_MAP :: PRT100_TO_QID [14:12] */
-#define BCHP_SWITCH_CORE_P7_TC2COS_MAP_PRT100_TO_QID_MASK 0x00007000
-#define BCHP_SWITCH_CORE_P7_TC2COS_MAP_PRT100_TO_QID_SHIFT 12
-#define BCHP_SWITCH_CORE_P7_TC2COS_MAP_PRT100_TO_QID_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: P7_TC2COS_MAP :: PRT011_TO_QID [11:09] */
-#define BCHP_SWITCH_CORE_P7_TC2COS_MAP_PRT011_TO_QID_MASK 0x00000e00
-#define BCHP_SWITCH_CORE_P7_TC2COS_MAP_PRT011_TO_QID_SHIFT 9
-#define BCHP_SWITCH_CORE_P7_TC2COS_MAP_PRT011_TO_QID_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: P7_TC2COS_MAP :: PRT010_TO_QID [08:06] */
-#define BCHP_SWITCH_CORE_P7_TC2COS_MAP_PRT010_TO_QID_MASK 0x000001c0
-#define BCHP_SWITCH_CORE_P7_TC2COS_MAP_PRT010_TO_QID_SHIFT 6
-#define BCHP_SWITCH_CORE_P7_TC2COS_MAP_PRT010_TO_QID_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: P7_TC2COS_MAP :: PRT001_TO_QID [05:03] */
-#define BCHP_SWITCH_CORE_P7_TC2COS_MAP_PRT001_TO_QID_MASK 0x00000038
-#define BCHP_SWITCH_CORE_P7_TC2COS_MAP_PRT001_TO_QID_SHIFT 3
-#define BCHP_SWITCH_CORE_P7_TC2COS_MAP_PRT001_TO_QID_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: P7_TC2COS_MAP :: PRT000_TO_QID [02:00] */
-#define BCHP_SWITCH_CORE_P7_TC2COS_MAP_PRT000_TO_QID_MASK 0x00000007
-#define BCHP_SWITCH_CORE_P7_TC2COS_MAP_PRT000_TO_QID_SHIFT 0
-#define BCHP_SWITCH_CORE_P7_TC2COS_MAP_PRT000_TO_QID_DEFAULT 0x00000000
-
-/***************************************************************************
- *IMP_TC2COS_MAP - Port 8 TC to COS Mapping Register
- ***************************************************************************/
-/* SWITCH_CORE :: IMP_TC2COS_MAP :: BCAST_DLF_DROP_TC [31:24] */
-#define BCHP_SWITCH_CORE_IMP_TC2COS_MAP_BCAST_DLF_DROP_TC_MASK 0xff000000
-#define BCHP_SWITCH_CORE_IMP_TC2COS_MAP_BCAST_DLF_DROP_TC_SHIFT 24
-#define BCHP_SWITCH_CORE_IMP_TC2COS_MAP_BCAST_DLF_DROP_TC_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: IMP_TC2COS_MAP :: PRT111_TO_QID [23:21] */
-#define BCHP_SWITCH_CORE_IMP_TC2COS_MAP_PRT111_TO_QID_MASK 0x00e00000
-#define BCHP_SWITCH_CORE_IMP_TC2COS_MAP_PRT111_TO_QID_SHIFT 21
-#define BCHP_SWITCH_CORE_IMP_TC2COS_MAP_PRT111_TO_QID_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: IMP_TC2COS_MAP :: PRT110_TO_QID [20:18] */
-#define BCHP_SWITCH_CORE_IMP_TC2COS_MAP_PRT110_TO_QID_MASK 0x001c0000
-#define BCHP_SWITCH_CORE_IMP_TC2COS_MAP_PRT110_TO_QID_SHIFT 18
-#define BCHP_SWITCH_CORE_IMP_TC2COS_MAP_PRT110_TO_QID_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: IMP_TC2COS_MAP :: PRT101_TO_QID [17:15] */
-#define BCHP_SWITCH_CORE_IMP_TC2COS_MAP_PRT101_TO_QID_MASK 0x00038000
-#define BCHP_SWITCH_CORE_IMP_TC2COS_MAP_PRT101_TO_QID_SHIFT 15
-#define BCHP_SWITCH_CORE_IMP_TC2COS_MAP_PRT101_TO_QID_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: IMP_TC2COS_MAP :: PRT100_TO_QID [14:12] */
-#define BCHP_SWITCH_CORE_IMP_TC2COS_MAP_PRT100_TO_QID_MASK 0x00007000
-#define BCHP_SWITCH_CORE_IMP_TC2COS_MAP_PRT100_TO_QID_SHIFT 12
-#define BCHP_SWITCH_CORE_IMP_TC2COS_MAP_PRT100_TO_QID_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: IMP_TC2COS_MAP :: PRT011_TO_QID [11:09] */
-#define BCHP_SWITCH_CORE_IMP_TC2COS_MAP_PRT011_TO_QID_MASK 0x00000e00
-#define BCHP_SWITCH_CORE_IMP_TC2COS_MAP_PRT011_TO_QID_SHIFT 9
-#define BCHP_SWITCH_CORE_IMP_TC2COS_MAP_PRT011_TO_QID_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: IMP_TC2COS_MAP :: PRT010_TO_QID [08:06] */
-#define BCHP_SWITCH_CORE_IMP_TC2COS_MAP_PRT010_TO_QID_MASK 0x000001c0
-#define BCHP_SWITCH_CORE_IMP_TC2COS_MAP_PRT010_TO_QID_SHIFT 6
-#define BCHP_SWITCH_CORE_IMP_TC2COS_MAP_PRT010_TO_QID_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: IMP_TC2COS_MAP :: PRT001_TO_QID [05:03] */
-#define BCHP_SWITCH_CORE_IMP_TC2COS_MAP_PRT001_TO_QID_MASK 0x00000038
-#define BCHP_SWITCH_CORE_IMP_TC2COS_MAP_PRT001_TO_QID_SHIFT 3
-#define BCHP_SWITCH_CORE_IMP_TC2COS_MAP_PRT001_TO_QID_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: IMP_TC2COS_MAP :: PRT000_TO_QID [02:00] */
-#define BCHP_SWITCH_CORE_IMP_TC2COS_MAP_PRT000_TO_QID_MASK 0x00000007
-#define BCHP_SWITCH_CORE_IMP_TC2COS_MAP_PRT000_TO_QID_SHIFT 0
-#define BCHP_SWITCH_CORE_IMP_TC2COS_MAP_PRT000_TO_QID_DEFAULT 0x00000000
-
-/***************************************************************************
- *QOS_REG_SPARE0 - Spare 0 Register (Not2Release)
- ***************************************************************************/
-/* SWITCH_CORE :: QOS_REG_SPARE0 :: QOS_REG_SPARE0 [31:00] */
-#define BCHP_SWITCH_CORE_QOS_REG_SPARE0_QOS_REG_SPARE0_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_QOS_REG_SPARE0_QOS_REG_SPARE0_SHIFT 0
-#define BCHP_SWITCH_CORE_QOS_REG_SPARE0_QOS_REG_SPARE0_DEFAULT 0x00000000
-
-/***************************************************************************
- *QOS_REG_SPARE1 - Spare 1 Register (Not2Release)
- ***************************************************************************/
-/* SWITCH_CORE :: QOS_REG_SPARE1 :: QOS_REG_SPARE1 [31:00] */
-#define BCHP_SWITCH_CORE_QOS_REG_SPARE1_QOS_REG_SPARE1_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_QOS_REG_SPARE1_QOS_REG_SPARE1_SHIFT 0
-#define BCHP_SWITCH_CORE_QOS_REG_SPARE1_QOS_REG_SPARE1_DEFAULT 0x00000000
-
-/***************************************************************************
- *PN_PCP2TC_DEI1_Port_0 - Port N PCP to TC Map for DEI 1 Register
- ***************************************************************************/
-/* SWITCH_CORE :: PN_PCP2TC_DEI1_Port_0 :: SWITCH_RESV [31:24] */
-#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI1_Port_0_SWITCH_RESV_MASK 0xff000000
-#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI1_Port_0_SWITCH_RESV_SHIFT 24
-#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI1_Port_0_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: PN_PCP2TC_DEI1_Port_0 :: TAG111_PRI_MAP [23:21] */
-#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI1_Port_0_TAG111_PRI_MAP_MASK 0x00e00000
-#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI1_Port_0_TAG111_PRI_MAP_SHIFT 21
-#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI1_Port_0_TAG111_PRI_MAP_DEFAULT 0x00000007
-
-/* SWITCH_CORE :: PN_PCP2TC_DEI1_Port_0 :: TAG110_PRI_MAP [20:18] */
-#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI1_Port_0_TAG110_PRI_MAP_MASK 0x001c0000
-#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI1_Port_0_TAG110_PRI_MAP_SHIFT 18
-#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI1_Port_0_TAG110_PRI_MAP_DEFAULT 0x00000006
-
-/* SWITCH_CORE :: PN_PCP2TC_DEI1_Port_0 :: TAG101_PRI_MAP [17:15] */
-#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI1_Port_0_TAG101_PRI_MAP_MASK 0x00038000
-#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI1_Port_0_TAG101_PRI_MAP_SHIFT 15
-#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI1_Port_0_TAG101_PRI_MAP_DEFAULT 0x00000005
-
-/* SWITCH_CORE :: PN_PCP2TC_DEI1_Port_0 :: TAG100_PRI_MAP [14:12] */
-#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI1_Port_0_TAG100_PRI_MAP_MASK 0x00007000
-#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI1_Port_0_TAG100_PRI_MAP_SHIFT 12
-#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI1_Port_0_TAG100_PRI_MAP_DEFAULT 0x00000004
-
-/* SWITCH_CORE :: PN_PCP2TC_DEI1_Port_0 :: TAG011_PRI_MAP [11:09] */
-#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI1_Port_0_TAG011_PRI_MAP_MASK 0x00000e00
-#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI1_Port_0_TAG011_PRI_MAP_SHIFT 9
-#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI1_Port_0_TAG011_PRI_MAP_DEFAULT 0x00000003
-
-/* SWITCH_CORE :: PN_PCP2TC_DEI1_Port_0 :: TAG010_PRI_MAP [08:06] */
-#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI1_Port_0_TAG010_PRI_MAP_MASK 0x000001c0
-#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI1_Port_0_TAG010_PRI_MAP_SHIFT 6
-#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI1_Port_0_TAG010_PRI_MAP_DEFAULT 0x00000002
-
-/* SWITCH_CORE :: PN_PCP2TC_DEI1_Port_0 :: TAG001_PRI_MAP [05:03] */
-#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI1_Port_0_TAG001_PRI_MAP_MASK 0x00000038
-#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI1_Port_0_TAG001_PRI_MAP_SHIFT 3
-#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI1_Port_0_TAG001_PRI_MAP_DEFAULT 0x00000001
-
-/* SWITCH_CORE :: PN_PCP2TC_DEI1_Port_0 :: TAG000_PRI_MAP [02:00] */
-#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI1_Port_0_TAG000_PRI_MAP_MASK 0x00000007
-#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI1_Port_0_TAG000_PRI_MAP_SHIFT 0
-#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI1_Port_0_TAG000_PRI_MAP_DEFAULT 0x00000000
-
-/***************************************************************************
- *PN_PCP2TC_DEI1_Port_1 - Port N PCP to TC Map for DEI 1 Register
- ***************************************************************************/
-/* SWITCH_CORE :: PN_PCP2TC_DEI1_Port_1 :: SWITCH_RESV [31:24] */
-#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI1_Port_1_SWITCH_RESV_MASK 0xff000000
-#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI1_Port_1_SWITCH_RESV_SHIFT 24
-#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI1_Port_1_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: PN_PCP2TC_DEI1_Port_1 :: TAG111_PRI_MAP [23:21] */
-#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI1_Port_1_TAG111_PRI_MAP_MASK 0x00e00000
-#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI1_Port_1_TAG111_PRI_MAP_SHIFT 21
-#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI1_Port_1_TAG111_PRI_MAP_DEFAULT 0x00000007
-
-/* SWITCH_CORE :: PN_PCP2TC_DEI1_Port_1 :: TAG110_PRI_MAP [20:18] */
-#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI1_Port_1_TAG110_PRI_MAP_MASK 0x001c0000
-#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI1_Port_1_TAG110_PRI_MAP_SHIFT 18
-#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI1_Port_1_TAG110_PRI_MAP_DEFAULT 0x00000006
-
-/* SWITCH_CORE :: PN_PCP2TC_DEI1_Port_1 :: TAG101_PRI_MAP [17:15] */
-#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI1_Port_1_TAG101_PRI_MAP_MASK 0x00038000
-#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI1_Port_1_TAG101_PRI_MAP_SHIFT 15
-#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI1_Port_1_TAG101_PRI_MAP_DEFAULT 0x00000005
-
-/* SWITCH_CORE :: PN_PCP2TC_DEI1_Port_1 :: TAG100_PRI_MAP [14:12] */
-#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI1_Port_1_TAG100_PRI_MAP_MASK 0x00007000
-#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI1_Port_1_TAG100_PRI_MAP_SHIFT 12
-#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI1_Port_1_TAG100_PRI_MAP_DEFAULT 0x00000004
-
-/* SWITCH_CORE :: PN_PCP2TC_DEI1_Port_1 :: TAG011_PRI_MAP [11:09] */
-#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI1_Port_1_TAG011_PRI_MAP_MASK 0x00000e00
-#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI1_Port_1_TAG011_PRI_MAP_SHIFT 9
-#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI1_Port_1_TAG011_PRI_MAP_DEFAULT 0x00000003
-
-/* SWITCH_CORE :: PN_PCP2TC_DEI1_Port_1 :: TAG010_PRI_MAP [08:06] */
-#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI1_Port_1_TAG010_PRI_MAP_MASK 0x000001c0
-#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI1_Port_1_TAG010_PRI_MAP_SHIFT 6
-#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI1_Port_1_TAG010_PRI_MAP_DEFAULT 0x00000002
-
-/* SWITCH_CORE :: PN_PCP2TC_DEI1_Port_1 :: TAG001_PRI_MAP [05:03] */
-#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI1_Port_1_TAG001_PRI_MAP_MASK 0x00000038
-#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI1_Port_1_TAG001_PRI_MAP_SHIFT 3
-#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI1_Port_1_TAG001_PRI_MAP_DEFAULT 0x00000001
-
-/* SWITCH_CORE :: PN_PCP2TC_DEI1_Port_1 :: TAG000_PRI_MAP [02:00] */
-#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI1_Port_1_TAG000_PRI_MAP_MASK 0x00000007
-#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI1_Port_1_TAG000_PRI_MAP_SHIFT 0
-#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI1_Port_1_TAG000_PRI_MAP_DEFAULT 0x00000000
-
-/***************************************************************************
- *PN_PCP2TC_DEI1_Port_2 - Port N PCP to TC Map for DEI 1 Register
- ***************************************************************************/
-/* SWITCH_CORE :: PN_PCP2TC_DEI1_Port_2 :: SWITCH_RESV [31:24] */
-#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI1_Port_2_SWITCH_RESV_MASK 0xff000000
-#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI1_Port_2_SWITCH_RESV_SHIFT 24
-#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI1_Port_2_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: PN_PCP2TC_DEI1_Port_2 :: TAG111_PRI_MAP [23:21] */
-#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI1_Port_2_TAG111_PRI_MAP_MASK 0x00e00000
-#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI1_Port_2_TAG111_PRI_MAP_SHIFT 21
-#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI1_Port_2_TAG111_PRI_MAP_DEFAULT 0x00000007
-
-/* SWITCH_CORE :: PN_PCP2TC_DEI1_Port_2 :: TAG110_PRI_MAP [20:18] */
-#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI1_Port_2_TAG110_PRI_MAP_MASK 0x001c0000
-#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI1_Port_2_TAG110_PRI_MAP_SHIFT 18
-#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI1_Port_2_TAG110_PRI_MAP_DEFAULT 0x00000006
-
-/* SWITCH_CORE :: PN_PCP2TC_DEI1_Port_2 :: TAG101_PRI_MAP [17:15] */
-#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI1_Port_2_TAG101_PRI_MAP_MASK 0x00038000
-#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI1_Port_2_TAG101_PRI_MAP_SHIFT 15
-#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI1_Port_2_TAG101_PRI_MAP_DEFAULT 0x00000005
-
-/* SWITCH_CORE :: PN_PCP2TC_DEI1_Port_2 :: TAG100_PRI_MAP [14:12] */
-#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI1_Port_2_TAG100_PRI_MAP_MASK 0x00007000
-#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI1_Port_2_TAG100_PRI_MAP_SHIFT 12
-#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI1_Port_2_TAG100_PRI_MAP_DEFAULT 0x00000004
-
-/* SWITCH_CORE :: PN_PCP2TC_DEI1_Port_2 :: TAG011_PRI_MAP [11:09] */
-#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI1_Port_2_TAG011_PRI_MAP_MASK 0x00000e00
-#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI1_Port_2_TAG011_PRI_MAP_SHIFT 9
-#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI1_Port_2_TAG011_PRI_MAP_DEFAULT 0x00000003
-
-/* SWITCH_CORE :: PN_PCP2TC_DEI1_Port_2 :: TAG010_PRI_MAP [08:06] */
-#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI1_Port_2_TAG010_PRI_MAP_MASK 0x000001c0
-#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI1_Port_2_TAG010_PRI_MAP_SHIFT 6
-#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI1_Port_2_TAG010_PRI_MAP_DEFAULT 0x00000002
-
-/* SWITCH_CORE :: PN_PCP2TC_DEI1_Port_2 :: TAG001_PRI_MAP [05:03] */
-#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI1_Port_2_TAG001_PRI_MAP_MASK 0x00000038
-#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI1_Port_2_TAG001_PRI_MAP_SHIFT 3
-#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI1_Port_2_TAG001_PRI_MAP_DEFAULT 0x00000001
-
-/* SWITCH_CORE :: PN_PCP2TC_DEI1_Port_2 :: TAG000_PRI_MAP [02:00] */
-#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI1_Port_2_TAG000_PRI_MAP_MASK 0x00000007
-#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI1_Port_2_TAG000_PRI_MAP_SHIFT 0
-#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI1_Port_2_TAG000_PRI_MAP_DEFAULT 0x00000000
-
-/***************************************************************************
- *PN_PCP2TC_DEI1_Port_3 - Port N PCP to TC Map for DEI 1 Register
- ***************************************************************************/
-/* SWITCH_CORE :: PN_PCP2TC_DEI1_Port_3 :: SWITCH_RESV [31:24] */
-#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI1_Port_3_SWITCH_RESV_MASK 0xff000000
-#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI1_Port_3_SWITCH_RESV_SHIFT 24
-#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI1_Port_3_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: PN_PCP2TC_DEI1_Port_3 :: TAG111_PRI_MAP [23:21] */
-#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI1_Port_3_TAG111_PRI_MAP_MASK 0x00e00000
-#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI1_Port_3_TAG111_PRI_MAP_SHIFT 21
-#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI1_Port_3_TAG111_PRI_MAP_DEFAULT 0x00000007
-
-/* SWITCH_CORE :: PN_PCP2TC_DEI1_Port_3 :: TAG110_PRI_MAP [20:18] */
-#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI1_Port_3_TAG110_PRI_MAP_MASK 0x001c0000
-#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI1_Port_3_TAG110_PRI_MAP_SHIFT 18
-#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI1_Port_3_TAG110_PRI_MAP_DEFAULT 0x00000006
-
-/* SWITCH_CORE :: PN_PCP2TC_DEI1_Port_3 :: TAG101_PRI_MAP [17:15] */
-#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI1_Port_3_TAG101_PRI_MAP_MASK 0x00038000
-#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI1_Port_3_TAG101_PRI_MAP_SHIFT 15
-#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI1_Port_3_TAG101_PRI_MAP_DEFAULT 0x00000005
-
-/* SWITCH_CORE :: PN_PCP2TC_DEI1_Port_3 :: TAG100_PRI_MAP [14:12] */
-#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI1_Port_3_TAG100_PRI_MAP_MASK 0x00007000
-#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI1_Port_3_TAG100_PRI_MAP_SHIFT 12
-#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI1_Port_3_TAG100_PRI_MAP_DEFAULT 0x00000004
-
-/* SWITCH_CORE :: PN_PCP2TC_DEI1_Port_3 :: TAG011_PRI_MAP [11:09] */
-#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI1_Port_3_TAG011_PRI_MAP_MASK 0x00000e00
-#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI1_Port_3_TAG011_PRI_MAP_SHIFT 9
-#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI1_Port_3_TAG011_PRI_MAP_DEFAULT 0x00000003
-
-/* SWITCH_CORE :: PN_PCP2TC_DEI1_Port_3 :: TAG010_PRI_MAP [08:06] */
-#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI1_Port_3_TAG010_PRI_MAP_MASK 0x000001c0
-#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI1_Port_3_TAG010_PRI_MAP_SHIFT 6
-#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI1_Port_3_TAG010_PRI_MAP_DEFAULT 0x00000002
-
-/* SWITCH_CORE :: PN_PCP2TC_DEI1_Port_3 :: TAG001_PRI_MAP [05:03] */
-#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI1_Port_3_TAG001_PRI_MAP_MASK 0x00000038
-#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI1_Port_3_TAG001_PRI_MAP_SHIFT 3
-#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI1_Port_3_TAG001_PRI_MAP_DEFAULT 0x00000001
-
-/* SWITCH_CORE :: PN_PCP2TC_DEI1_Port_3 :: TAG000_PRI_MAP [02:00] */
-#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI1_Port_3_TAG000_PRI_MAP_MASK 0x00000007
-#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI1_Port_3_TAG000_PRI_MAP_SHIFT 0
-#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI1_Port_3_TAG000_PRI_MAP_DEFAULT 0x00000000
-
-/***************************************************************************
- *PN_PCP2TC_DEI1_Port_4 - Port N PCP to TC Map for DEI 1 Register
- ***************************************************************************/
-/* SWITCH_CORE :: PN_PCP2TC_DEI1_Port_4 :: SWITCH_RESV [31:24] */
-#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI1_Port_4_SWITCH_RESV_MASK 0xff000000
-#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI1_Port_4_SWITCH_RESV_SHIFT 24
-#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI1_Port_4_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: PN_PCP2TC_DEI1_Port_4 :: TAG111_PRI_MAP [23:21] */
-#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI1_Port_4_TAG111_PRI_MAP_MASK 0x00e00000
-#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI1_Port_4_TAG111_PRI_MAP_SHIFT 21
-#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI1_Port_4_TAG111_PRI_MAP_DEFAULT 0x00000007
-
-/* SWITCH_CORE :: PN_PCP2TC_DEI1_Port_4 :: TAG110_PRI_MAP [20:18] */
-#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI1_Port_4_TAG110_PRI_MAP_MASK 0x001c0000
-#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI1_Port_4_TAG110_PRI_MAP_SHIFT 18
-#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI1_Port_4_TAG110_PRI_MAP_DEFAULT 0x00000006
-
-/* SWITCH_CORE :: PN_PCP2TC_DEI1_Port_4 :: TAG101_PRI_MAP [17:15] */
-#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI1_Port_4_TAG101_PRI_MAP_MASK 0x00038000
-#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI1_Port_4_TAG101_PRI_MAP_SHIFT 15
-#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI1_Port_4_TAG101_PRI_MAP_DEFAULT 0x00000005
-
-/* SWITCH_CORE :: PN_PCP2TC_DEI1_Port_4 :: TAG100_PRI_MAP [14:12] */
-#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI1_Port_4_TAG100_PRI_MAP_MASK 0x00007000
-#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI1_Port_4_TAG100_PRI_MAP_SHIFT 12
-#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI1_Port_4_TAG100_PRI_MAP_DEFAULT 0x00000004
-
-/* SWITCH_CORE :: PN_PCP2TC_DEI1_Port_4 :: TAG011_PRI_MAP [11:09] */
-#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI1_Port_4_TAG011_PRI_MAP_MASK 0x00000e00
-#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI1_Port_4_TAG011_PRI_MAP_SHIFT 9
-#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI1_Port_4_TAG011_PRI_MAP_DEFAULT 0x00000003
-
-/* SWITCH_CORE :: PN_PCP2TC_DEI1_Port_4 :: TAG010_PRI_MAP [08:06] */
-#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI1_Port_4_TAG010_PRI_MAP_MASK 0x000001c0
-#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI1_Port_4_TAG010_PRI_MAP_SHIFT 6
-#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI1_Port_4_TAG010_PRI_MAP_DEFAULT 0x00000002
-
-/* SWITCH_CORE :: PN_PCP2TC_DEI1_Port_4 :: TAG001_PRI_MAP [05:03] */
-#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI1_Port_4_TAG001_PRI_MAP_MASK 0x00000038
-#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI1_Port_4_TAG001_PRI_MAP_SHIFT 3
-#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI1_Port_4_TAG001_PRI_MAP_DEFAULT 0x00000001
-
-/* SWITCH_CORE :: PN_PCP2TC_DEI1_Port_4 :: TAG000_PRI_MAP [02:00] */
-#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI1_Port_4_TAG000_PRI_MAP_MASK 0x00000007
-#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI1_Port_4_TAG000_PRI_MAP_SHIFT 0
-#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI1_Port_4_TAG000_PRI_MAP_DEFAULT 0x00000000
-
-/***************************************************************************
- *PN_PCP2TC_DEI1_Port_5 - Port N PCP to TC Map for DEI 1 Register
- ***************************************************************************/
-/* SWITCH_CORE :: PN_PCP2TC_DEI1_Port_5 :: SWITCH_RESV [31:24] */
-#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI1_Port_5_SWITCH_RESV_MASK 0xff000000
-#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI1_Port_5_SWITCH_RESV_SHIFT 24
-#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI1_Port_5_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: PN_PCP2TC_DEI1_Port_5 :: TAG111_PRI_MAP [23:21] */
-#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI1_Port_5_TAG111_PRI_MAP_MASK 0x00e00000
-#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI1_Port_5_TAG111_PRI_MAP_SHIFT 21
-#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI1_Port_5_TAG111_PRI_MAP_DEFAULT 0x00000007
-
-/* SWITCH_CORE :: PN_PCP2TC_DEI1_Port_5 :: TAG110_PRI_MAP [20:18] */
-#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI1_Port_5_TAG110_PRI_MAP_MASK 0x001c0000
-#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI1_Port_5_TAG110_PRI_MAP_SHIFT 18
-#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI1_Port_5_TAG110_PRI_MAP_DEFAULT 0x00000006
-
-/* SWITCH_CORE :: PN_PCP2TC_DEI1_Port_5 :: TAG101_PRI_MAP [17:15] */
-#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI1_Port_5_TAG101_PRI_MAP_MASK 0x00038000
-#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI1_Port_5_TAG101_PRI_MAP_SHIFT 15
-#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI1_Port_5_TAG101_PRI_MAP_DEFAULT 0x00000005
-
-/* SWITCH_CORE :: PN_PCP2TC_DEI1_Port_5 :: TAG100_PRI_MAP [14:12] */
-#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI1_Port_5_TAG100_PRI_MAP_MASK 0x00007000
-#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI1_Port_5_TAG100_PRI_MAP_SHIFT 12
-#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI1_Port_5_TAG100_PRI_MAP_DEFAULT 0x00000004
-
-/* SWITCH_CORE :: PN_PCP2TC_DEI1_Port_5 :: TAG011_PRI_MAP [11:09] */
-#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI1_Port_5_TAG011_PRI_MAP_MASK 0x00000e00
-#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI1_Port_5_TAG011_PRI_MAP_SHIFT 9
-#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI1_Port_5_TAG011_PRI_MAP_DEFAULT 0x00000003
-
-/* SWITCH_CORE :: PN_PCP2TC_DEI1_Port_5 :: TAG010_PRI_MAP [08:06] */
-#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI1_Port_5_TAG010_PRI_MAP_MASK 0x000001c0
-#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI1_Port_5_TAG010_PRI_MAP_SHIFT 6
-#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI1_Port_5_TAG010_PRI_MAP_DEFAULT 0x00000002
-
-/* SWITCH_CORE :: PN_PCP2TC_DEI1_Port_5 :: TAG001_PRI_MAP [05:03] */
-#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI1_Port_5_TAG001_PRI_MAP_MASK 0x00000038
-#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI1_Port_5_TAG001_PRI_MAP_SHIFT 3
-#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI1_Port_5_TAG001_PRI_MAP_DEFAULT 0x00000001
-
-/* SWITCH_CORE :: PN_PCP2TC_DEI1_Port_5 :: TAG000_PRI_MAP [02:00] */
-#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI1_Port_5_TAG000_PRI_MAP_MASK 0x00000007
-#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI1_Port_5_TAG000_PRI_MAP_SHIFT 0
-#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI1_Port_5_TAG000_PRI_MAP_DEFAULT 0x00000000
-
-/***************************************************************************
- *P7_PCP2TC_DEI1 - Port 7 PCP to TC Map for DEI 1 Register
- ***************************************************************************/
-/* SWITCH_CORE :: P7_PCP2TC_DEI1 :: SWITCH_RESV [31:24] */
-#define BCHP_SWITCH_CORE_P7_PCP2TC_DEI1_SWITCH_RESV_MASK 0xff000000
-#define BCHP_SWITCH_CORE_P7_PCP2TC_DEI1_SWITCH_RESV_SHIFT 24
-#define BCHP_SWITCH_CORE_P7_PCP2TC_DEI1_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: P7_PCP2TC_DEI1 :: TAG111_PRI_MAP [23:21] */
-#define BCHP_SWITCH_CORE_P7_PCP2TC_DEI1_TAG111_PRI_MAP_MASK 0x00e00000
-#define BCHP_SWITCH_CORE_P7_PCP2TC_DEI1_TAG111_PRI_MAP_SHIFT 21
-#define BCHP_SWITCH_CORE_P7_PCP2TC_DEI1_TAG111_PRI_MAP_DEFAULT 0x00000007
-
-/* SWITCH_CORE :: P7_PCP2TC_DEI1 :: TAG110_PRI_MAP [20:18] */
-#define BCHP_SWITCH_CORE_P7_PCP2TC_DEI1_TAG110_PRI_MAP_MASK 0x001c0000
-#define BCHP_SWITCH_CORE_P7_PCP2TC_DEI1_TAG110_PRI_MAP_SHIFT 18
-#define BCHP_SWITCH_CORE_P7_PCP2TC_DEI1_TAG110_PRI_MAP_DEFAULT 0x00000006
-
-/* SWITCH_CORE :: P7_PCP2TC_DEI1 :: TAG101_PRI_MAP [17:15] */
-#define BCHP_SWITCH_CORE_P7_PCP2TC_DEI1_TAG101_PRI_MAP_MASK 0x00038000
-#define BCHP_SWITCH_CORE_P7_PCP2TC_DEI1_TAG101_PRI_MAP_SHIFT 15
-#define BCHP_SWITCH_CORE_P7_PCP2TC_DEI1_TAG101_PRI_MAP_DEFAULT 0x00000005
-
-/* SWITCH_CORE :: P7_PCP2TC_DEI1 :: TAG100_PRI_MAP [14:12] */
-#define BCHP_SWITCH_CORE_P7_PCP2TC_DEI1_TAG100_PRI_MAP_MASK 0x00007000
-#define BCHP_SWITCH_CORE_P7_PCP2TC_DEI1_TAG100_PRI_MAP_SHIFT 12
-#define BCHP_SWITCH_CORE_P7_PCP2TC_DEI1_TAG100_PRI_MAP_DEFAULT 0x00000004
-
-/* SWITCH_CORE :: P7_PCP2TC_DEI1 :: TAG011_PRI_MAP [11:09] */
-#define BCHP_SWITCH_CORE_P7_PCP2TC_DEI1_TAG011_PRI_MAP_MASK 0x00000e00
-#define BCHP_SWITCH_CORE_P7_PCP2TC_DEI1_TAG011_PRI_MAP_SHIFT 9
-#define BCHP_SWITCH_CORE_P7_PCP2TC_DEI1_TAG011_PRI_MAP_DEFAULT 0x00000003
-
-/* SWITCH_CORE :: P7_PCP2TC_DEI1 :: TAG010_PRI_MAP [08:06] */
-#define BCHP_SWITCH_CORE_P7_PCP2TC_DEI1_TAG010_PRI_MAP_MASK 0x000001c0
-#define BCHP_SWITCH_CORE_P7_PCP2TC_DEI1_TAG010_PRI_MAP_SHIFT 6
-#define BCHP_SWITCH_CORE_P7_PCP2TC_DEI1_TAG010_PRI_MAP_DEFAULT 0x00000002
-
-/* SWITCH_CORE :: P7_PCP2TC_DEI1 :: TAG001_PRI_MAP [05:03] */
-#define BCHP_SWITCH_CORE_P7_PCP2TC_DEI1_TAG001_PRI_MAP_MASK 0x00000038
-#define BCHP_SWITCH_CORE_P7_PCP2TC_DEI1_TAG001_PRI_MAP_SHIFT 3
-#define BCHP_SWITCH_CORE_P7_PCP2TC_DEI1_TAG001_PRI_MAP_DEFAULT 0x00000001
-
-/* SWITCH_CORE :: P7_PCP2TC_DEI1 :: TAG000_PRI_MAP [02:00] */
-#define BCHP_SWITCH_CORE_P7_PCP2TC_DEI1_TAG000_PRI_MAP_MASK 0x00000007
-#define BCHP_SWITCH_CORE_P7_PCP2TC_DEI1_TAG000_PRI_MAP_SHIFT 0
-#define BCHP_SWITCH_CORE_P7_PCP2TC_DEI1_TAG000_PRI_MAP_DEFAULT 0x00000000
-
-/***************************************************************************
- *IMP_PCP2TC_DEI1 - Port 8 (IMP) PCP to TC Map for DEI 1 Register
- ***************************************************************************/
-/* SWITCH_CORE :: IMP_PCP2TC_DEI1 :: SWITCH_RESV [31:24] */
-#define BCHP_SWITCH_CORE_IMP_PCP2TC_DEI1_SWITCH_RESV_MASK 0xff000000
-#define BCHP_SWITCH_CORE_IMP_PCP2TC_DEI1_SWITCH_RESV_SHIFT 24
-#define BCHP_SWITCH_CORE_IMP_PCP2TC_DEI1_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: IMP_PCP2TC_DEI1 :: TAG111_PRI_MAP [23:21] */
-#define BCHP_SWITCH_CORE_IMP_PCP2TC_DEI1_TAG111_PRI_MAP_MASK 0x00e00000
-#define BCHP_SWITCH_CORE_IMP_PCP2TC_DEI1_TAG111_PRI_MAP_SHIFT 21
-#define BCHP_SWITCH_CORE_IMP_PCP2TC_DEI1_TAG111_PRI_MAP_DEFAULT 0x00000007
-
-/* SWITCH_CORE :: IMP_PCP2TC_DEI1 :: TAG110_PRI_MAP [20:18] */
-#define BCHP_SWITCH_CORE_IMP_PCP2TC_DEI1_TAG110_PRI_MAP_MASK 0x001c0000
-#define BCHP_SWITCH_CORE_IMP_PCP2TC_DEI1_TAG110_PRI_MAP_SHIFT 18
-#define BCHP_SWITCH_CORE_IMP_PCP2TC_DEI1_TAG110_PRI_MAP_DEFAULT 0x00000006
-
-/* SWITCH_CORE :: IMP_PCP2TC_DEI1 :: TAG101_PRI_MAP [17:15] */
-#define BCHP_SWITCH_CORE_IMP_PCP2TC_DEI1_TAG101_PRI_MAP_MASK 0x00038000
-#define BCHP_SWITCH_CORE_IMP_PCP2TC_DEI1_TAG101_PRI_MAP_SHIFT 15
-#define BCHP_SWITCH_CORE_IMP_PCP2TC_DEI1_TAG101_PRI_MAP_DEFAULT 0x00000005
-
-/* SWITCH_CORE :: IMP_PCP2TC_DEI1 :: TAG100_PRI_MAP [14:12] */
-#define BCHP_SWITCH_CORE_IMP_PCP2TC_DEI1_TAG100_PRI_MAP_MASK 0x00007000
-#define BCHP_SWITCH_CORE_IMP_PCP2TC_DEI1_TAG100_PRI_MAP_SHIFT 12
-#define BCHP_SWITCH_CORE_IMP_PCP2TC_DEI1_TAG100_PRI_MAP_DEFAULT 0x00000004
-
-/* SWITCH_CORE :: IMP_PCP2TC_DEI1 :: TAG011_PRI_MAP [11:09] */
-#define BCHP_SWITCH_CORE_IMP_PCP2TC_DEI1_TAG011_PRI_MAP_MASK 0x00000e00
-#define BCHP_SWITCH_CORE_IMP_PCP2TC_DEI1_TAG011_PRI_MAP_SHIFT 9
-#define BCHP_SWITCH_CORE_IMP_PCP2TC_DEI1_TAG011_PRI_MAP_DEFAULT 0x00000003
-
-/* SWITCH_CORE :: IMP_PCP2TC_DEI1 :: TAG010_PRI_MAP [08:06] */
-#define BCHP_SWITCH_CORE_IMP_PCP2TC_DEI1_TAG010_PRI_MAP_MASK 0x000001c0
-#define BCHP_SWITCH_CORE_IMP_PCP2TC_DEI1_TAG010_PRI_MAP_SHIFT 6
-#define BCHP_SWITCH_CORE_IMP_PCP2TC_DEI1_TAG010_PRI_MAP_DEFAULT 0x00000002
-
-/* SWITCH_CORE :: IMP_PCP2TC_DEI1 :: TAG001_PRI_MAP [05:03] */
-#define BCHP_SWITCH_CORE_IMP_PCP2TC_DEI1_TAG001_PRI_MAP_MASK 0x00000038
-#define BCHP_SWITCH_CORE_IMP_PCP2TC_DEI1_TAG001_PRI_MAP_SHIFT 3
-#define BCHP_SWITCH_CORE_IMP_PCP2TC_DEI1_TAG001_PRI_MAP_DEFAULT 0x00000001
-
-/* SWITCH_CORE :: IMP_PCP2TC_DEI1 :: TAG000_PRI_MAP [02:00] */
-#define BCHP_SWITCH_CORE_IMP_PCP2TC_DEI1_TAG000_PRI_MAP_MASK 0x00000007
-#define BCHP_SWITCH_CORE_IMP_PCP2TC_DEI1_TAG000_PRI_MAP_SHIFT 0
-#define BCHP_SWITCH_CORE_IMP_PCP2TC_DEI1_TAG000_PRI_MAP_DEFAULT 0x00000000
-
-/***************************************************************************
- *PORT_VLAN_CTL_Port_0 - PORT N VLAN Control Register
- ***************************************************************************/
-/* SWITCH_CORE :: PORT_VLAN_CTL_Port_0 :: reserved_for_padding0 [31:16] */
-#define BCHP_SWITCH_CORE_PORT_VLAN_CTL_Port_0_reserved_for_padding0_MASK 0xffff0000
-#define BCHP_SWITCH_CORE_PORT_VLAN_CTL_Port_0_reserved_for_padding0_SHIFT 16
-
-/* SWITCH_CORE :: PORT_VLAN_CTL_Port_0 :: SWITCH_RESV [15:09] */
-#define BCHP_SWITCH_CORE_PORT_VLAN_CTL_Port_0_SWITCH_RESV_MASK 0x0000fe00
-#define BCHP_SWITCH_CORE_PORT_VLAN_CTL_Port_0_SWITCH_RESV_SHIFT 9
-#define BCHP_SWITCH_CORE_PORT_VLAN_CTL_Port_0_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: PORT_VLAN_CTL_Port_0 :: PORT_EGRESS_EN [08:00] */
-#define BCHP_SWITCH_CORE_PORT_VLAN_CTL_Port_0_PORT_EGRESS_EN_MASK 0x000001ff
-#define BCHP_SWITCH_CORE_PORT_VLAN_CTL_Port_0_PORT_EGRESS_EN_SHIFT 0
-#define BCHP_SWITCH_CORE_PORT_VLAN_CTL_Port_0_PORT_EGRESS_EN_DEFAULT 0x000001ff
-
-/***************************************************************************
- *PORT_VLAN_CTL_Port_1 - PORT N VLAN Control Register
- ***************************************************************************/
-/* SWITCH_CORE :: PORT_VLAN_CTL_Port_1 :: reserved_for_padding0 [31:16] */
-#define BCHP_SWITCH_CORE_PORT_VLAN_CTL_Port_1_reserved_for_padding0_MASK 0xffff0000
-#define BCHP_SWITCH_CORE_PORT_VLAN_CTL_Port_1_reserved_for_padding0_SHIFT 16
-
-/* SWITCH_CORE :: PORT_VLAN_CTL_Port_1 :: SWITCH_RESV [15:09] */
-#define BCHP_SWITCH_CORE_PORT_VLAN_CTL_Port_1_SWITCH_RESV_MASK 0x0000fe00
-#define BCHP_SWITCH_CORE_PORT_VLAN_CTL_Port_1_SWITCH_RESV_SHIFT 9
-#define BCHP_SWITCH_CORE_PORT_VLAN_CTL_Port_1_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: PORT_VLAN_CTL_Port_1 :: PORT_EGRESS_EN [08:00] */
-#define BCHP_SWITCH_CORE_PORT_VLAN_CTL_Port_1_PORT_EGRESS_EN_MASK 0x000001ff
-#define BCHP_SWITCH_CORE_PORT_VLAN_CTL_Port_1_PORT_EGRESS_EN_SHIFT 0
-#define BCHP_SWITCH_CORE_PORT_VLAN_CTL_Port_1_PORT_EGRESS_EN_DEFAULT 0x000001ff
-
-/***************************************************************************
- *PORT_VLAN_CTL_Port_2 - PORT N VLAN Control Register
- ***************************************************************************/
-/* SWITCH_CORE :: PORT_VLAN_CTL_Port_2 :: reserved_for_padding0 [31:16] */
-#define BCHP_SWITCH_CORE_PORT_VLAN_CTL_Port_2_reserved_for_padding0_MASK 0xffff0000
-#define BCHP_SWITCH_CORE_PORT_VLAN_CTL_Port_2_reserved_for_padding0_SHIFT 16
-
-/* SWITCH_CORE :: PORT_VLAN_CTL_Port_2 :: SWITCH_RESV [15:09] */
-#define BCHP_SWITCH_CORE_PORT_VLAN_CTL_Port_2_SWITCH_RESV_MASK 0x0000fe00
-#define BCHP_SWITCH_CORE_PORT_VLAN_CTL_Port_2_SWITCH_RESV_SHIFT 9
-#define BCHP_SWITCH_CORE_PORT_VLAN_CTL_Port_2_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: PORT_VLAN_CTL_Port_2 :: PORT_EGRESS_EN [08:00] */
-#define BCHP_SWITCH_CORE_PORT_VLAN_CTL_Port_2_PORT_EGRESS_EN_MASK 0x000001ff
-#define BCHP_SWITCH_CORE_PORT_VLAN_CTL_Port_2_PORT_EGRESS_EN_SHIFT 0
-#define BCHP_SWITCH_CORE_PORT_VLAN_CTL_Port_2_PORT_EGRESS_EN_DEFAULT 0x000001ff
-
-/***************************************************************************
- *PORT_VLAN_CTL_Port_3 - PORT N VLAN Control Register
- ***************************************************************************/
-/* SWITCH_CORE :: PORT_VLAN_CTL_Port_3 :: reserved_for_padding0 [31:16] */
-#define BCHP_SWITCH_CORE_PORT_VLAN_CTL_Port_3_reserved_for_padding0_MASK 0xffff0000
-#define BCHP_SWITCH_CORE_PORT_VLAN_CTL_Port_3_reserved_for_padding0_SHIFT 16
-
-/* SWITCH_CORE :: PORT_VLAN_CTL_Port_3 :: SWITCH_RESV [15:09] */
-#define BCHP_SWITCH_CORE_PORT_VLAN_CTL_Port_3_SWITCH_RESV_MASK 0x0000fe00
-#define BCHP_SWITCH_CORE_PORT_VLAN_CTL_Port_3_SWITCH_RESV_SHIFT 9
-#define BCHP_SWITCH_CORE_PORT_VLAN_CTL_Port_3_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: PORT_VLAN_CTL_Port_3 :: PORT_EGRESS_EN [08:00] */
-#define BCHP_SWITCH_CORE_PORT_VLAN_CTL_Port_3_PORT_EGRESS_EN_MASK 0x000001ff
-#define BCHP_SWITCH_CORE_PORT_VLAN_CTL_Port_3_PORT_EGRESS_EN_SHIFT 0
-#define BCHP_SWITCH_CORE_PORT_VLAN_CTL_Port_3_PORT_EGRESS_EN_DEFAULT 0x000001ff
-
-/***************************************************************************
- *PORT_VLAN_CTL_Port_4 - PORT N VLAN Control Register
- ***************************************************************************/
-/* SWITCH_CORE :: PORT_VLAN_CTL_Port_4 :: reserved_for_padding0 [31:16] */
-#define BCHP_SWITCH_CORE_PORT_VLAN_CTL_Port_4_reserved_for_padding0_MASK 0xffff0000
-#define BCHP_SWITCH_CORE_PORT_VLAN_CTL_Port_4_reserved_for_padding0_SHIFT 16
-
-/* SWITCH_CORE :: PORT_VLAN_CTL_Port_4 :: SWITCH_RESV [15:09] */
-#define BCHP_SWITCH_CORE_PORT_VLAN_CTL_Port_4_SWITCH_RESV_MASK 0x0000fe00
-#define BCHP_SWITCH_CORE_PORT_VLAN_CTL_Port_4_SWITCH_RESV_SHIFT 9
-#define BCHP_SWITCH_CORE_PORT_VLAN_CTL_Port_4_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: PORT_VLAN_CTL_Port_4 :: PORT_EGRESS_EN [08:00] */
-#define BCHP_SWITCH_CORE_PORT_VLAN_CTL_Port_4_PORT_EGRESS_EN_MASK 0x000001ff
-#define BCHP_SWITCH_CORE_PORT_VLAN_CTL_Port_4_PORT_EGRESS_EN_SHIFT 0
-#define BCHP_SWITCH_CORE_PORT_VLAN_CTL_Port_4_PORT_EGRESS_EN_DEFAULT 0x000001ff
-
-/***************************************************************************
- *PORT_VLAN_CTL_Port_5 - PORT N VLAN Control Register
- ***************************************************************************/
-/* SWITCH_CORE :: PORT_VLAN_CTL_Port_5 :: reserved_for_padding0 [31:16] */
-#define BCHP_SWITCH_CORE_PORT_VLAN_CTL_Port_5_reserved_for_padding0_MASK 0xffff0000
-#define BCHP_SWITCH_CORE_PORT_VLAN_CTL_Port_5_reserved_for_padding0_SHIFT 16
-
-/* SWITCH_CORE :: PORT_VLAN_CTL_Port_5 :: SWITCH_RESV [15:09] */
-#define BCHP_SWITCH_CORE_PORT_VLAN_CTL_Port_5_SWITCH_RESV_MASK 0x0000fe00
-#define BCHP_SWITCH_CORE_PORT_VLAN_CTL_Port_5_SWITCH_RESV_SHIFT 9
-#define BCHP_SWITCH_CORE_PORT_VLAN_CTL_Port_5_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: PORT_VLAN_CTL_Port_5 :: PORT_EGRESS_EN [08:00] */
-#define BCHP_SWITCH_CORE_PORT_VLAN_CTL_Port_5_PORT_EGRESS_EN_MASK 0x000001ff
-#define BCHP_SWITCH_CORE_PORT_VLAN_CTL_Port_5_PORT_EGRESS_EN_SHIFT 0
-#define BCHP_SWITCH_CORE_PORT_VLAN_CTL_Port_5_PORT_EGRESS_EN_DEFAULT 0x000001ff
-
-/***************************************************************************
- *PORT_VLAN_CTL_P7 - PORT 7 VLAN Control Register
- ***************************************************************************/
-/* SWITCH_CORE :: PORT_VLAN_CTL_P7 :: reserved_for_padding0 [31:16] */
-#define BCHP_SWITCH_CORE_PORT_VLAN_CTL_P7_reserved_for_padding0_MASK 0xffff0000
-#define BCHP_SWITCH_CORE_PORT_VLAN_CTL_P7_reserved_for_padding0_SHIFT 16
-
-/* SWITCH_CORE :: PORT_VLAN_CTL_P7 :: SWITCH_RESV [15:09] */
-#define BCHP_SWITCH_CORE_PORT_VLAN_CTL_P7_SWITCH_RESV_MASK 0x0000fe00
-#define BCHP_SWITCH_CORE_PORT_VLAN_CTL_P7_SWITCH_RESV_SHIFT 9
-#define BCHP_SWITCH_CORE_PORT_VLAN_CTL_P7_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: PORT_VLAN_CTL_P7 :: PORT_EGRESS_EN [08:00] */
-#define BCHP_SWITCH_CORE_PORT_VLAN_CTL_P7_PORT_EGRESS_EN_MASK 0x000001ff
-#define BCHP_SWITCH_CORE_PORT_VLAN_CTL_P7_PORT_EGRESS_EN_SHIFT 0
-#define BCHP_SWITCH_CORE_PORT_VLAN_CTL_P7_PORT_EGRESS_EN_DEFAULT 0x000001ff
-
-/***************************************************************************
- *PORT_VLAN_CTL_IMP - PORT 8 VLAN Control Register
- ***************************************************************************/
-/* SWITCH_CORE :: PORT_VLAN_CTL_IMP :: reserved_for_padding0 [31:16] */
-#define BCHP_SWITCH_CORE_PORT_VLAN_CTL_IMP_reserved_for_padding0_MASK 0xffff0000
-#define BCHP_SWITCH_CORE_PORT_VLAN_CTL_IMP_reserved_for_padding0_SHIFT 16
-
-/* SWITCH_CORE :: PORT_VLAN_CTL_IMP :: SWITCH_RESV [15:09] */
-#define BCHP_SWITCH_CORE_PORT_VLAN_CTL_IMP_SWITCH_RESV_MASK 0x0000fe00
-#define BCHP_SWITCH_CORE_PORT_VLAN_CTL_IMP_SWITCH_RESV_SHIFT 9
-#define BCHP_SWITCH_CORE_PORT_VLAN_CTL_IMP_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: PORT_VLAN_CTL_IMP :: PORT_EGRESS_EN [08:00] */
-#define BCHP_SWITCH_CORE_PORT_VLAN_CTL_IMP_PORT_EGRESS_EN_MASK 0x000001ff
-#define BCHP_SWITCH_CORE_PORT_VLAN_CTL_IMP_PORT_EGRESS_EN_SHIFT 0
-#define BCHP_SWITCH_CORE_PORT_VLAN_CTL_IMP_PORT_EGRESS_EN_DEFAULT 0x000001ff
-
-/***************************************************************************
- *VLAN_REG_SPARE0 - Spare 0 Register (Not2Release)
- ***************************************************************************/
-/* SWITCH_CORE :: VLAN_REG_SPARE0 :: VLAN_REG_SPARE0 [31:00] */
-#define BCHP_SWITCH_CORE_VLAN_REG_SPARE0_VLAN_REG_SPARE0_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_VLAN_REG_SPARE0_VLAN_REG_SPARE0_SHIFT 0
-#define BCHP_SWITCH_CORE_VLAN_REG_SPARE0_VLAN_REG_SPARE0_DEFAULT 0x00000000
-
-/***************************************************************************
- *VLAN_REG_SPARE1 - Spare 1 Register (Not2Release)
- ***************************************************************************/
-/* SWITCH_CORE :: VLAN_REG_SPARE1 :: VLAN_REG_SPARE1 [31:00] */
-#define BCHP_SWITCH_CORE_VLAN_REG_SPARE1_VLAN_REG_SPARE1_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_VLAN_REG_SPARE1_VLAN_REG_SPARE1_SHIFT 0
-#define BCHP_SWITCH_CORE_VLAN_REG_SPARE1_VLAN_REG_SPARE1_DEFAULT 0x00000000
-
-/***************************************************************************
- *MAC_TRUNK_CTL - MAC Trunk Control Register
- ***************************************************************************/
-/* SWITCH_CORE :: MAC_TRUNK_CTL :: reserved_for_padding0 [31:08] */
-#define BCHP_SWITCH_CORE_MAC_TRUNK_CTL_reserved_for_padding0_MASK 0xffffff00
-#define BCHP_SWITCH_CORE_MAC_TRUNK_CTL_reserved_for_padding0_SHIFT 8
-
-/* SWITCH_CORE :: MAC_TRUNK_CTL :: SERVER_1 [07:04] */
-#define BCHP_SWITCH_CORE_MAC_TRUNK_CTL_SERVER_1_MASK 0x000000f0
-#define BCHP_SWITCH_CORE_MAC_TRUNK_CTL_SERVER_1_SHIFT 4
-#define BCHP_SWITCH_CORE_MAC_TRUNK_CTL_SERVER_1_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: MAC_TRUNK_CTL :: EN_TRUNK_LOCAL [03:03] */
-#define BCHP_SWITCH_CORE_MAC_TRUNK_CTL_EN_TRUNK_LOCAL_MASK 0x00000008
-#define BCHP_SWITCH_CORE_MAC_TRUNK_CTL_EN_TRUNK_LOCAL_SHIFT 3
-#define BCHP_SWITCH_CORE_MAC_TRUNK_CTL_EN_TRUNK_LOCAL_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: MAC_TRUNK_CTL :: SERVER_0 [02:02] */
-#define BCHP_SWITCH_CORE_MAC_TRUNK_CTL_SERVER_0_MASK 0x00000004
-#define BCHP_SWITCH_CORE_MAC_TRUNK_CTL_SERVER_0_SHIFT 2
-#define BCHP_SWITCH_CORE_MAC_TRUNK_CTL_SERVER_0_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: MAC_TRUNK_CTL :: HASH_SEL [01:00] */
-#define BCHP_SWITCH_CORE_MAC_TRUNK_CTL_HASH_SEL_MASK 0x00000003
-#define BCHP_SWITCH_CORE_MAC_TRUNK_CTL_HASH_SEL_SHIFT 0
-#define BCHP_SWITCH_CORE_MAC_TRUNK_CTL_HASH_SEL_DEFAULT 0x00000000
-
-/***************************************************************************
- *TRUNK_GRP_CTL_Port_0 - Trunk N Group Control Register
- ***************************************************************************/
-/* SWITCH_CORE :: TRUNK_GRP_CTL_Port_0 :: reserved_for_padding0 [31:16] */
-#define BCHP_SWITCH_CORE_TRUNK_GRP_CTL_Port_0_reserved_for_padding0_MASK 0xffff0000
-#define BCHP_SWITCH_CORE_TRUNK_GRP_CTL_Port_0_reserved_for_padding0_SHIFT 16
-
-/* SWITCH_CORE :: TRUNK_GRP_CTL_Port_0 :: SWITCH_RESV [15:09] */
-#define BCHP_SWITCH_CORE_TRUNK_GRP_CTL_Port_0_SWITCH_RESV_MASK 0x0000fe00
-#define BCHP_SWITCH_CORE_TRUNK_GRP_CTL_Port_0_SWITCH_RESV_SHIFT 9
-#define BCHP_SWITCH_CORE_TRUNK_GRP_CTL_Port_0_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: TRUNK_GRP_CTL_Port_0 :: EN_TRUNK_GRP [08:00] */
-#define BCHP_SWITCH_CORE_TRUNK_GRP_CTL_Port_0_EN_TRUNK_GRP_MASK 0x000001ff
-#define BCHP_SWITCH_CORE_TRUNK_GRP_CTL_Port_0_EN_TRUNK_GRP_SHIFT 0
-#define BCHP_SWITCH_CORE_TRUNK_GRP_CTL_Port_0_EN_TRUNK_GRP_DEFAULT 0x00000000
-
-/***************************************************************************
- *TRUNK_GRP_CTL_Port_1 - Trunk N Group Control Register
- ***************************************************************************/
-/* SWITCH_CORE :: TRUNK_GRP_CTL_Port_1 :: reserved_for_padding0 [31:16] */
-#define BCHP_SWITCH_CORE_TRUNK_GRP_CTL_Port_1_reserved_for_padding0_MASK 0xffff0000
-#define BCHP_SWITCH_CORE_TRUNK_GRP_CTL_Port_1_reserved_for_padding0_SHIFT 16
-
-/* SWITCH_CORE :: TRUNK_GRP_CTL_Port_1 :: SWITCH_RESV [15:09] */
-#define BCHP_SWITCH_CORE_TRUNK_GRP_CTL_Port_1_SWITCH_RESV_MASK 0x0000fe00
-#define BCHP_SWITCH_CORE_TRUNK_GRP_CTL_Port_1_SWITCH_RESV_SHIFT 9
-#define BCHP_SWITCH_CORE_TRUNK_GRP_CTL_Port_1_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: TRUNK_GRP_CTL_Port_1 :: EN_TRUNK_GRP [08:00] */
-#define BCHP_SWITCH_CORE_TRUNK_GRP_CTL_Port_1_EN_TRUNK_GRP_MASK 0x000001ff
-#define BCHP_SWITCH_CORE_TRUNK_GRP_CTL_Port_1_EN_TRUNK_GRP_SHIFT 0
-#define BCHP_SWITCH_CORE_TRUNK_GRP_CTL_Port_1_EN_TRUNK_GRP_DEFAULT 0x00000000
-
-/***************************************************************************
- *TRUNK_REG_SPARE0 - Spare 0 Register (Not2Release)
- ***************************************************************************/
-/* SWITCH_CORE :: TRUNK_REG_SPARE0 :: TRUNK_REG_SPARE0 [31:00] */
-#define BCHP_SWITCH_CORE_TRUNK_REG_SPARE0_TRUNK_REG_SPARE0_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_TRUNK_REG_SPARE0_TRUNK_REG_SPARE0_SHIFT 0
-#define BCHP_SWITCH_CORE_TRUNK_REG_SPARE0_TRUNK_REG_SPARE0_DEFAULT 0x00000000
-
-/***************************************************************************
- *TRUNK_REG_SPARE1 - Spare 1 Register (Not2Release)
- ***************************************************************************/
-/* SWITCH_CORE :: TRUNK_REG_SPARE1 :: TRUNK_REG_SPARE1 [31:00] */
-#define BCHP_SWITCH_CORE_TRUNK_REG_SPARE1_TRUNK_REG_SPARE1_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_TRUNK_REG_SPARE1_TRUNK_REG_SPARE1_SHIFT 0
-#define BCHP_SWITCH_CORE_TRUNK_REG_SPARE1_TRUNK_REG_SPARE1_DEFAULT 0x00000000
-
-/***************************************************************************
- *VLAN_CTRL0 - 802.1Q VLAN Control 0 Registers
- ***************************************************************************/
-/* SWITCH_CORE :: VLAN_CTRL0 :: reserved_for_padding0 [31:08] */
-#define BCHP_SWITCH_CORE_VLAN_CTRL0_reserved_for_padding0_MASK 0xffffff00
-#define BCHP_SWITCH_CORE_VLAN_CTRL0_reserved_for_padding0_SHIFT 8
-
-/* SWITCH_CORE :: VLAN_CTRL0 :: VLAN_EN [07:07] */
-#define BCHP_SWITCH_CORE_VLAN_CTRL0_VLAN_EN_MASK 0x00000080
-#define BCHP_SWITCH_CORE_VLAN_CTRL0_VLAN_EN_SHIFT 7
-#define BCHP_SWITCH_CORE_VLAN_CTRL0_VLAN_EN_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: VLAN_CTRL0 :: VLAN_LEARN_MODE [06:05] */
-#define BCHP_SWITCH_CORE_VLAN_CTRL0_VLAN_LEARN_MODE_MASK 0x00000060
-#define BCHP_SWITCH_CORE_VLAN_CTRL0_VLAN_LEARN_MODE_SHIFT 5
-#define BCHP_SWITCH_CORE_VLAN_CTRL0_VLAN_LEARN_MODE_DEFAULT 0x00000003
-
-/* SWITCH_CORE :: VLAN_CTRL0 :: SWITCH_RESV_1 [04:04] */
-#define BCHP_SWITCH_CORE_VLAN_CTRL0_SWITCH_RESV_1_MASK 0x00000010
-#define BCHP_SWITCH_CORE_VLAN_CTRL0_SWITCH_RESV_1_SHIFT 4
-#define BCHP_SWITCH_CORE_VLAN_CTRL0_SWITCH_RESV_1_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: VLAN_CTRL0 :: CHANGE_1Q_VID [03:03] */
-#define BCHP_SWITCH_CORE_VLAN_CTRL0_CHANGE_1Q_VID_MASK 0x00000008
-#define BCHP_SWITCH_CORE_VLAN_CTRL0_CHANGE_1Q_VID_SHIFT 3
-#define BCHP_SWITCH_CORE_VLAN_CTRL0_CHANGE_1Q_VID_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: VLAN_CTRL0 :: SWITCH_RESV_0 [02:02] */
-#define BCHP_SWITCH_CORE_VLAN_CTRL0_SWITCH_RESV_0_MASK 0x00000004
-#define BCHP_SWITCH_CORE_VLAN_CTRL0_SWITCH_RESV_0_SHIFT 2
-#define BCHP_SWITCH_CORE_VLAN_CTRL0_SWITCH_RESV_0_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: VLAN_CTRL0 :: CHANGE_1P_VID_OUTER [01:01] */
-#define BCHP_SWITCH_CORE_VLAN_CTRL0_CHANGE_1P_VID_OUTER_MASK 0x00000002
-#define BCHP_SWITCH_CORE_VLAN_CTRL0_CHANGE_1P_VID_OUTER_SHIFT 1
-#define BCHP_SWITCH_CORE_VLAN_CTRL0_CHANGE_1P_VID_OUTER_DEFAULT 0x00000001
-
-/* SWITCH_CORE :: VLAN_CTRL0 :: CHANGE_1P_VID_INNER [00:00] */
-#define BCHP_SWITCH_CORE_VLAN_CTRL0_CHANGE_1P_VID_INNER_MASK 0x00000001
-#define BCHP_SWITCH_CORE_VLAN_CTRL0_CHANGE_1P_VID_INNER_SHIFT 0
-#define BCHP_SWITCH_CORE_VLAN_CTRL0_CHANGE_1P_VID_INNER_DEFAULT 0x00000001
-
-/***************************************************************************
- *VLAN_CTRL1 - 802.1Q VLAN Control 1 Registers
- ***************************************************************************/
-/* SWITCH_CORE :: VLAN_CTRL1 :: reserved_for_padding0 [31:08] */
-#define BCHP_SWITCH_CORE_VLAN_CTRL1_reserved_for_padding0_MASK 0xffffff00
-#define BCHP_SWITCH_CORE_VLAN_CTRL1_reserved_for_padding0_SHIFT 8
-
-/* SWITCH_CORE :: VLAN_CTRL1 :: SWITCH_RESV_3 [07:07] */
-#define BCHP_SWITCH_CORE_VLAN_CTRL1_SWITCH_RESV_3_MASK 0x00000080
-#define BCHP_SWITCH_CORE_VLAN_CTRL1_SWITCH_RESV_3_SHIFT 7
-#define BCHP_SWITCH_CORE_VLAN_CTRL1_SWITCH_RESV_3_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: VLAN_CTRL1 :: EN_IPMC_BYPASS_UNTAG [06:06] */
-#define BCHP_SWITCH_CORE_VLAN_CTRL1_EN_IPMC_BYPASS_UNTAG_MASK 0x00000040
-#define BCHP_SWITCH_CORE_VLAN_CTRL1_EN_IPMC_BYPASS_UNTAG_SHIFT 6
-#define BCHP_SWITCH_CORE_VLAN_CTRL1_EN_IPMC_BYPASS_UNTAG_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: VLAN_CTRL1 :: EN_IPMC_BYPASS_FWDMAP [05:05] */
-#define BCHP_SWITCH_CORE_VLAN_CTRL1_EN_IPMC_BYPASS_FWDMAP_MASK 0x00000020
-#define BCHP_SWITCH_CORE_VLAN_CTRL1_EN_IPMC_BYPASS_FWDMAP_SHIFT 5
-#define BCHP_SWITCH_CORE_VLAN_CTRL1_EN_IPMC_BYPASS_FWDMAP_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: VLAN_CTRL1 :: SWITCH_RESV_2 [04:04] */
-#define BCHP_SWITCH_CORE_VLAN_CTRL1_SWITCH_RESV_2_MASK 0x00000010
-#define BCHP_SWITCH_CORE_VLAN_CTRL1_SWITCH_RESV_2_SHIFT 4
-#define BCHP_SWITCH_CORE_VLAN_CTRL1_SWITCH_RESV_2_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: VLAN_CTRL1 :: EN_RSV_MCAST_UNTAG [03:03] */
-#define BCHP_SWITCH_CORE_VLAN_CTRL1_EN_RSV_MCAST_UNTAG_MASK 0x00000008
-#define BCHP_SWITCH_CORE_VLAN_CTRL1_EN_RSV_MCAST_UNTAG_SHIFT 3
-#define BCHP_SWITCH_CORE_VLAN_CTRL1_EN_RSV_MCAST_UNTAG_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: VLAN_CTRL1 :: EN_RSV_MCAST_FWDMAP [02:02] */
-#define BCHP_SWITCH_CORE_VLAN_CTRL1_EN_RSV_MCAST_FWDMAP_MASK 0x00000004
-#define BCHP_SWITCH_CORE_VLAN_CTRL1_EN_RSV_MCAST_FWDMAP_SHIFT 2
-#define BCHP_SWITCH_CORE_VLAN_CTRL1_EN_RSV_MCAST_FWDMAP_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: VLAN_CTRL1 :: SWITCH_RESV_1 [01:01] */
-#define BCHP_SWITCH_CORE_VLAN_CTRL1_SWITCH_RESV_1_MASK 0x00000002
-#define BCHP_SWITCH_CORE_VLAN_CTRL1_SWITCH_RESV_1_SHIFT 1
-#define BCHP_SWITCH_CORE_VLAN_CTRL1_SWITCH_RESV_1_DEFAULT 0x00000001
-
-/* SWITCH_CORE :: VLAN_CTRL1 :: SWITCH_RESV_0 [00:00] */
-#define BCHP_SWITCH_CORE_VLAN_CTRL1_SWITCH_RESV_0_MASK 0x00000001
-#define BCHP_SWITCH_CORE_VLAN_CTRL1_SWITCH_RESV_0_SHIFT 0
-#define BCHP_SWITCH_CORE_VLAN_CTRL1_SWITCH_RESV_0_DEFAULT 0x00000000
-
-/***************************************************************************
- *VLAN_CTRL2 - 802.1Q VLAN Control 2 Registers
- ***************************************************************************/
-/* SWITCH_CORE :: VLAN_CTRL2 :: reserved_for_padding0 [31:08] */
-#define BCHP_SWITCH_CORE_VLAN_CTRL2_reserved_for_padding0_MASK 0xffffff00
-#define BCHP_SWITCH_CORE_VLAN_CTRL2_reserved_for_padding0_SHIFT 8
-
-/* SWITCH_CORE :: VLAN_CTRL2 :: SWITCH_RESV [07:07] */
-#define BCHP_SWITCH_CORE_VLAN_CTRL2_SWITCH_RESV_MASK 0x00000080
-#define BCHP_SWITCH_CORE_VLAN_CTRL2_SWITCH_RESV_SHIFT 7
-#define BCHP_SWITCH_CORE_VLAN_CTRL2_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: VLAN_CTRL2 :: EN_GMRP_GVRP_UNTAG_MAP [06:06] */
-#define BCHP_SWITCH_CORE_VLAN_CTRL2_EN_GMRP_GVRP_UNTAG_MAP_MASK 0x00000040
-#define BCHP_SWITCH_CORE_VLAN_CTRL2_EN_GMRP_GVRP_UNTAG_MAP_SHIFT 6
-#define BCHP_SWITCH_CORE_VLAN_CTRL2_EN_GMRP_GVRP_UNTAG_MAP_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: VLAN_CTRL2 :: EN_GMRP_GVRP_V_FWDMAP [05:05] */
-#define BCHP_SWITCH_CORE_VLAN_CTRL2_EN_GMRP_GVRP_V_FWDMAP_MASK 0x00000020
-#define BCHP_SWITCH_CORE_VLAN_CTRL2_EN_GMRP_GVRP_V_FWDMAP_SHIFT 5
-#define BCHP_SWITCH_CORE_VLAN_CTRL2_EN_GMRP_GVRP_V_FWDMAP_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: VLAN_CTRL2 :: SWITCH_RESV_2 [04:03] */
-#define BCHP_SWITCH_CORE_VLAN_CTRL2_SWITCH_RESV_2_MASK 0x00000018
-#define BCHP_SWITCH_CORE_VLAN_CTRL2_SWITCH_RESV_2_SHIFT 3
-#define BCHP_SWITCH_CORE_VLAN_CTRL2_SWITCH_RESV_2_DEFAULT 0x00000002
-
-/* SWITCH_CORE :: VLAN_CTRL2 :: EN_MIIM_BYPASS_V_FWDMAP [02:02] */
-#define BCHP_SWITCH_CORE_VLAN_CTRL2_EN_MIIM_BYPASS_V_FWDMAP_MASK 0x00000004
-#define BCHP_SWITCH_CORE_VLAN_CTRL2_EN_MIIM_BYPASS_V_FWDMAP_SHIFT 2
-#define BCHP_SWITCH_CORE_VLAN_CTRL2_EN_MIIM_BYPASS_V_FWDMAP_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: VLAN_CTRL2 :: SWITCH_RESV_0 [01:00] */
-#define BCHP_SWITCH_CORE_VLAN_CTRL2_SWITCH_RESV_0_MASK 0x00000003
-#define BCHP_SWITCH_CORE_VLAN_CTRL2_SWITCH_RESV_0_SHIFT 0
-#define BCHP_SWITCH_CORE_VLAN_CTRL2_SWITCH_RESV_0_DEFAULT 0x00000000
-
-/***************************************************************************
- *VLAN_CTRL3 - 802.1Q VLAN Control 3 Registers
- ***************************************************************************/
-/* SWITCH_CORE :: VLAN_CTRL3 :: reserved_for_padding0 [31:16] */
-#define BCHP_SWITCH_CORE_VLAN_CTRL3_reserved_for_padding0_MASK 0xffff0000
-#define BCHP_SWITCH_CORE_VLAN_CTRL3_reserved_for_padding0_SHIFT 16
-
-/* SWITCH_CORE :: VLAN_CTRL3 :: SWITCH_RESV [15:09] */
-#define BCHP_SWITCH_CORE_VLAN_CTRL3_SWITCH_RESV_MASK 0x0000fe00
-#define BCHP_SWITCH_CORE_VLAN_CTRL3_SWITCH_RESV_SHIFT 9
-#define BCHP_SWITCH_CORE_VLAN_CTRL3_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: VLAN_CTRL3 :: EN_DROP_NON1Q [08:00] */
-#define BCHP_SWITCH_CORE_VLAN_CTRL3_EN_DROP_NON1Q_MASK 0x000001ff
-#define BCHP_SWITCH_CORE_VLAN_CTRL3_EN_DROP_NON1Q_SHIFT 0
-#define BCHP_SWITCH_CORE_VLAN_CTRL3_EN_DROP_NON1Q_DEFAULT 0x00000000
-
-/***************************************************************************
- *VLAN_CTRL4 - 802.1Q VLAN Control 4 Registers
- ***************************************************************************/
-/* SWITCH_CORE :: VLAN_CTRL4 :: reserved_for_padding0 [31:08] */
-#define BCHP_SWITCH_CORE_VLAN_CTRL4_reserved_for_padding0_MASK 0xffffff00
-#define BCHP_SWITCH_CORE_VLAN_CTRL4_reserved_for_padding0_SHIFT 8
-
-/* SWITCH_CORE :: VLAN_CTRL4 :: INGR_VID_CHK [07:06] */
-#define BCHP_SWITCH_CORE_VLAN_CTRL4_INGR_VID_CHK_MASK 0x000000c0
-#define BCHP_SWITCH_CORE_VLAN_CTRL4_INGR_VID_CHK_SHIFT 6
-#define BCHP_SWITCH_CORE_VLAN_CTRL4_INGR_VID_CHK_DEFAULT 0x00000003
-
-/* SWITCH_CORE :: VLAN_CTRL4 :: EN_MGE_REV_GVRP [05:05] */
-#define BCHP_SWITCH_CORE_VLAN_CTRL4_EN_MGE_REV_GVRP_MASK 0x00000020
-#define BCHP_SWITCH_CORE_VLAN_CTRL4_EN_MGE_REV_GVRP_SHIFT 5
-#define BCHP_SWITCH_CORE_VLAN_CTRL4_EN_MGE_REV_GVRP_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: VLAN_CTRL4 :: EN_MGE_REV_GMRP [04:04] */
-#define BCHP_SWITCH_CORE_VLAN_CTRL4_EN_MGE_REV_GMRP_MASK 0x00000010
-#define BCHP_SWITCH_CORE_VLAN_CTRL4_EN_MGE_REV_GMRP_SHIFT 4
-#define BCHP_SWITCH_CORE_VLAN_CTRL4_EN_MGE_REV_GMRP_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: VLAN_CTRL4 :: EN_DOUBLE_TAG [03:02] */
-#define BCHP_SWITCH_CORE_VLAN_CTRL4_EN_DOUBLE_TAG_MASK 0x0000000c
-#define BCHP_SWITCH_CORE_VLAN_CTRL4_EN_DOUBLE_TAG_SHIFT 2
-#define BCHP_SWITCH_CORE_VLAN_CTRL4_EN_DOUBLE_TAG_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: VLAN_CTRL4 :: RESV_MCAST_FLOOD [01:01] */
-#define BCHP_SWITCH_CORE_VLAN_CTRL4_RESV_MCAST_FLOOD_MASK 0x00000002
-#define BCHP_SWITCH_CORE_VLAN_CTRL4_RESV_MCAST_FLOOD_SHIFT 1
-#define BCHP_SWITCH_CORE_VLAN_CTRL4_RESV_MCAST_FLOOD_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: VLAN_CTRL4 :: SWITCH_RESV_1 [00:00] */
-#define BCHP_SWITCH_CORE_VLAN_CTRL4_SWITCH_RESV_1_MASK 0x00000001
-#define BCHP_SWITCH_CORE_VLAN_CTRL4_SWITCH_RESV_1_SHIFT 0
-#define BCHP_SWITCH_CORE_VLAN_CTRL4_SWITCH_RESV_1_DEFAULT 0x00000000
-
-/***************************************************************************
- *VLAN_CTRL5 - 802.1Q VLAN Control 5 Registers
- ***************************************************************************/
-/* SWITCH_CORE :: VLAN_CTRL5 :: reserved_for_padding0 [31:08] */
-#define BCHP_SWITCH_CORE_VLAN_CTRL5_reserved_for_padding0_MASK 0xffffff00
-#define BCHP_SWITCH_CORE_VLAN_CTRL5_reserved_for_padding0_SHIFT 8
-
-/* SWITCH_CORE :: VLAN_CTRL5 :: SWITCH_RESV_2 [07:07] */
-#define BCHP_SWITCH_CORE_VLAN_CTRL5_SWITCH_RESV_2_MASK 0x00000080
-#define BCHP_SWITCH_CORE_VLAN_CTRL5_SWITCH_RESV_2_SHIFT 7
-#define BCHP_SWITCH_CORE_VLAN_CTRL5_SWITCH_RESV_2_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: VLAN_CTRL5 :: PRESV_NON1Q [06:06] */
-#define BCHP_SWITCH_CORE_VLAN_CTRL5_PRESV_NON1Q_MASK 0x00000040
-#define BCHP_SWITCH_CORE_VLAN_CTRL5_PRESV_NON1Q_SHIFT 6
-#define BCHP_SWITCH_CORE_VLAN_CTRL5_PRESV_NON1Q_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: VLAN_CTRL5 :: SWITCH_RESV_1 [05:05] */
-#define BCHP_SWITCH_CORE_VLAN_CTRL5_SWITCH_RESV_1_MASK 0x00000020
-#define BCHP_SWITCH_CORE_VLAN_CTRL5_SWITCH_RESV_1_SHIFT 5
-#define BCHP_SWITCH_CORE_VLAN_CTRL5_SWITCH_RESV_1_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: VLAN_CTRL5 :: EGRESS_DIR_FRM_BYPASS_TRUNK_EN [04:04] */
-#define BCHP_SWITCH_CORE_VLAN_CTRL5_EGRESS_DIR_FRM_BYPASS_TRUNK_EN_MASK 0x00000010
-#define BCHP_SWITCH_CORE_VLAN_CTRL5_EGRESS_DIR_FRM_BYPASS_TRUNK_EN_SHIFT 4
-#define BCHP_SWITCH_CORE_VLAN_CTRL5_EGRESS_DIR_FRM_BYPASS_TRUNK_EN_DEFAULT 0x00000001
-
-/* SWITCH_CORE :: VLAN_CTRL5 :: DROP_VTABLE_MISS [03:03] */
-#define BCHP_SWITCH_CORE_VLAN_CTRL5_DROP_VTABLE_MISS_MASK 0x00000008
-#define BCHP_SWITCH_CORE_VLAN_CTRL5_DROP_VTABLE_MISS_SHIFT 3
-#define BCHP_SWITCH_CORE_VLAN_CTRL5_DROP_VTABLE_MISS_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: VLAN_CTRL5 :: EN_VID_FFF_FWD [02:02] */
-#define BCHP_SWITCH_CORE_VLAN_CTRL5_EN_VID_FFF_FWD_MASK 0x00000004
-#define BCHP_SWITCH_CORE_VLAN_CTRL5_EN_VID_FFF_FWD_SHIFT 2
-#define BCHP_SWITCH_CORE_VLAN_CTRL5_EN_VID_FFF_FWD_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: VLAN_CTRL5 :: SWITCH_RESV_0 [01:01] */
-#define BCHP_SWITCH_CORE_VLAN_CTRL5_SWITCH_RESV_0_MASK 0x00000002
-#define BCHP_SWITCH_CORE_VLAN_CTRL5_SWITCH_RESV_0_SHIFT 1
-#define BCHP_SWITCH_CORE_VLAN_CTRL5_SWITCH_RESV_0_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: VLAN_CTRL5 :: EN_CPU_RX_BYP_INNER_CRCCHK [00:00] */
-#define BCHP_SWITCH_CORE_VLAN_CTRL5_EN_CPU_RX_BYP_INNER_CRCCHK_MASK 0x00000001
-#define BCHP_SWITCH_CORE_VLAN_CTRL5_EN_CPU_RX_BYP_INNER_CRCCHK_SHIFT 0
-#define BCHP_SWITCH_CORE_VLAN_CTRL5_EN_CPU_RX_BYP_INNER_CRCCHK_DEFAULT 0x00000000
-
-/***************************************************************************
- *VLAN_CTRL6 - 802.1Q VLAN Control 6 Registers
- ***************************************************************************/
-/* SWITCH_CORE :: VLAN_CTRL6 :: reserved_for_padding0 [31:08] */
-#define BCHP_SWITCH_CORE_VLAN_CTRL6_reserved_for_padding0_MASK 0xffffff00
-#define BCHP_SWITCH_CORE_VLAN_CTRL6_reserved_for_padding0_SHIFT 8
-
-/* SWITCH_CORE :: VLAN_CTRL6 :: SWITCH_RESV_1 [07:05] */
-#define BCHP_SWITCH_CORE_VLAN_CTRL6_SWITCH_RESV_1_MASK 0x000000e0
-#define BCHP_SWITCH_CORE_VLAN_CTRL6_SWITCH_RESV_1_SHIFT 5
-#define BCHP_SWITCH_CORE_VLAN_CTRL6_SWITCH_RESV_1_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: VLAN_CTRL6 :: DIS_ARL_BUST_LMT [04:04] */
-#define BCHP_SWITCH_CORE_VLAN_CTRL6_DIS_ARL_BUST_LMT_MASK 0x00000010
-#define BCHP_SWITCH_CORE_VLAN_CTRL6_DIS_ARL_BUST_LMT_SHIFT 4
-#define BCHP_SWITCH_CORE_VLAN_CTRL6_DIS_ARL_BUST_LMT_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: VLAN_CTRL6 :: SWITCH_RESV_0 [03:01] */
-#define BCHP_SWITCH_CORE_VLAN_CTRL6_SWITCH_RESV_0_MASK 0x0000000e
-#define BCHP_SWITCH_CORE_VLAN_CTRL6_SWITCH_RESV_0_SHIFT 1
-#define BCHP_SWITCH_CORE_VLAN_CTRL6_SWITCH_RESV_0_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: VLAN_CTRL6 :: STRICT_SFD_DETECT [00:00] */
-#define BCHP_SWITCH_CORE_VLAN_CTRL6_STRICT_SFD_DETECT_MASK 0x00000001
-#define BCHP_SWITCH_CORE_VLAN_CTRL6_STRICT_SFD_DETECT_SHIFT 0
-#define BCHP_SWITCH_CORE_VLAN_CTRL6_STRICT_SFD_DETECT_DEFAULT 0x00000000
-
-/***************************************************************************
- *VLAN_MULTI_PORT_ADDR_CTL - VLAN Multiport Address Control Register
- ***************************************************************************/
-/* SWITCH_CORE :: VLAN_MULTI_PORT_ADDR_CTL :: reserved_for_padding0 [31:16] */
-#define BCHP_SWITCH_CORE_VLAN_MULTI_PORT_ADDR_CTL_reserved_for_padding0_MASK 0xffff0000
-#define BCHP_SWITCH_CORE_VLAN_MULTI_PORT_ADDR_CTL_reserved_for_padding0_SHIFT 16
-
-/* SWITCH_CORE :: VLAN_MULTI_PORT_ADDR_CTL :: SWITCH_RESV [15:12] */
-#define BCHP_SWITCH_CORE_VLAN_MULTI_PORT_ADDR_CTL_SWITCH_RESV_MASK 0x0000f000
-#define BCHP_SWITCH_CORE_VLAN_MULTI_PORT_ADDR_CTL_SWITCH_RESV_SHIFT 12
-#define BCHP_SWITCH_CORE_VLAN_MULTI_PORT_ADDR_CTL_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: VLAN_MULTI_PORT_ADDR_CTL :: EN_MPORT5_UTG_MAP [11:11] */
-#define BCHP_SWITCH_CORE_VLAN_MULTI_PORT_ADDR_CTL_EN_MPORT5_UTG_MAP_MASK 0x00000800
-#define BCHP_SWITCH_CORE_VLAN_MULTI_PORT_ADDR_CTL_EN_MPORT5_UTG_MAP_SHIFT 11
-#define BCHP_SWITCH_CORE_VLAN_MULTI_PORT_ADDR_CTL_EN_MPORT5_UTG_MAP_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: VLAN_MULTI_PORT_ADDR_CTL :: EN_MPORT5_V_FWD_MAP [10:10] */
-#define BCHP_SWITCH_CORE_VLAN_MULTI_PORT_ADDR_CTL_EN_MPORT5_V_FWD_MAP_MASK 0x00000400
-#define BCHP_SWITCH_CORE_VLAN_MULTI_PORT_ADDR_CTL_EN_MPORT5_V_FWD_MAP_SHIFT 10
-#define BCHP_SWITCH_CORE_VLAN_MULTI_PORT_ADDR_CTL_EN_MPORT5_V_FWD_MAP_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: VLAN_MULTI_PORT_ADDR_CTL :: EN_MPORT4_UTG_MAP [09:09] */
-#define BCHP_SWITCH_CORE_VLAN_MULTI_PORT_ADDR_CTL_EN_MPORT4_UTG_MAP_MASK 0x00000200
-#define BCHP_SWITCH_CORE_VLAN_MULTI_PORT_ADDR_CTL_EN_MPORT4_UTG_MAP_SHIFT 9
-#define BCHP_SWITCH_CORE_VLAN_MULTI_PORT_ADDR_CTL_EN_MPORT4_UTG_MAP_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: VLAN_MULTI_PORT_ADDR_CTL :: EN_MPORT4_V_FWD_MAP [08:08] */
-#define BCHP_SWITCH_CORE_VLAN_MULTI_PORT_ADDR_CTL_EN_MPORT4_V_FWD_MAP_MASK 0x00000100
-#define BCHP_SWITCH_CORE_VLAN_MULTI_PORT_ADDR_CTL_EN_MPORT4_V_FWD_MAP_SHIFT 8
-#define BCHP_SWITCH_CORE_VLAN_MULTI_PORT_ADDR_CTL_EN_MPORT4_V_FWD_MAP_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: VLAN_MULTI_PORT_ADDR_CTL :: EN_MPORT3_UTG_MAP [07:07] */
-#define BCHP_SWITCH_CORE_VLAN_MULTI_PORT_ADDR_CTL_EN_MPORT3_UTG_MAP_MASK 0x00000080
-#define BCHP_SWITCH_CORE_VLAN_MULTI_PORT_ADDR_CTL_EN_MPORT3_UTG_MAP_SHIFT 7
-#define BCHP_SWITCH_CORE_VLAN_MULTI_PORT_ADDR_CTL_EN_MPORT3_UTG_MAP_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: VLAN_MULTI_PORT_ADDR_CTL :: EN_MPORT3_V_FWD_MAP [06:06] */
-#define BCHP_SWITCH_CORE_VLAN_MULTI_PORT_ADDR_CTL_EN_MPORT3_V_FWD_MAP_MASK 0x00000040
-#define BCHP_SWITCH_CORE_VLAN_MULTI_PORT_ADDR_CTL_EN_MPORT3_V_FWD_MAP_SHIFT 6
-#define BCHP_SWITCH_CORE_VLAN_MULTI_PORT_ADDR_CTL_EN_MPORT3_V_FWD_MAP_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: VLAN_MULTI_PORT_ADDR_CTL :: EN_MPORT2_UTG_MAP [05:05] */
-#define BCHP_SWITCH_CORE_VLAN_MULTI_PORT_ADDR_CTL_EN_MPORT2_UTG_MAP_MASK 0x00000020
-#define BCHP_SWITCH_CORE_VLAN_MULTI_PORT_ADDR_CTL_EN_MPORT2_UTG_MAP_SHIFT 5
-#define BCHP_SWITCH_CORE_VLAN_MULTI_PORT_ADDR_CTL_EN_MPORT2_UTG_MAP_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: VLAN_MULTI_PORT_ADDR_CTL :: EN_MPORT2_V_FWD_MAP [04:04] */
-#define BCHP_SWITCH_CORE_VLAN_MULTI_PORT_ADDR_CTL_EN_MPORT2_V_FWD_MAP_MASK 0x00000010
-#define BCHP_SWITCH_CORE_VLAN_MULTI_PORT_ADDR_CTL_EN_MPORT2_V_FWD_MAP_SHIFT 4
-#define BCHP_SWITCH_CORE_VLAN_MULTI_PORT_ADDR_CTL_EN_MPORT2_V_FWD_MAP_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: VLAN_MULTI_PORT_ADDR_CTL :: EN_MPORT1_UTG_MAP [03:03] */
-#define BCHP_SWITCH_CORE_VLAN_MULTI_PORT_ADDR_CTL_EN_MPORT1_UTG_MAP_MASK 0x00000008
-#define BCHP_SWITCH_CORE_VLAN_MULTI_PORT_ADDR_CTL_EN_MPORT1_UTG_MAP_SHIFT 3
-#define BCHP_SWITCH_CORE_VLAN_MULTI_PORT_ADDR_CTL_EN_MPORT1_UTG_MAP_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: VLAN_MULTI_PORT_ADDR_CTL :: EN_MPORT1_V_FWD_MAP [02:02] */
-#define BCHP_SWITCH_CORE_VLAN_MULTI_PORT_ADDR_CTL_EN_MPORT1_V_FWD_MAP_MASK 0x00000004
-#define BCHP_SWITCH_CORE_VLAN_MULTI_PORT_ADDR_CTL_EN_MPORT1_V_FWD_MAP_SHIFT 2
-#define BCHP_SWITCH_CORE_VLAN_MULTI_PORT_ADDR_CTL_EN_MPORT1_V_FWD_MAP_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: VLAN_MULTI_PORT_ADDR_CTL :: EN_MPORT0_UTG_MAP [01:01] */
-#define BCHP_SWITCH_CORE_VLAN_MULTI_PORT_ADDR_CTL_EN_MPORT0_UTG_MAP_MASK 0x00000002
-#define BCHP_SWITCH_CORE_VLAN_MULTI_PORT_ADDR_CTL_EN_MPORT0_UTG_MAP_SHIFT 1
-#define BCHP_SWITCH_CORE_VLAN_MULTI_PORT_ADDR_CTL_EN_MPORT0_UTG_MAP_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: VLAN_MULTI_PORT_ADDR_CTL :: EN_MPORT0_V_FWD_MAP [00:00] */
-#define BCHP_SWITCH_CORE_VLAN_MULTI_PORT_ADDR_CTL_EN_MPORT0_V_FWD_MAP_MASK 0x00000001
-#define BCHP_SWITCH_CORE_VLAN_MULTI_PORT_ADDR_CTL_EN_MPORT0_V_FWD_MAP_SHIFT 0
-#define BCHP_SWITCH_CORE_VLAN_MULTI_PORT_ADDR_CTL_EN_MPORT0_V_FWD_MAP_DEFAULT 0x00000000
-
-/***************************************************************************
- *DEFAULT_1Q_TAG_Port_0 - Port N 802.1Q Default Tag Registers
- ***************************************************************************/
-/* SWITCH_CORE :: DEFAULT_1Q_TAG_Port_0 :: reserved_for_padding0 [31:16] */
-#define BCHP_SWITCH_CORE_DEFAULT_1Q_TAG_Port_0_reserved_for_padding0_MASK 0xffff0000
-#define BCHP_SWITCH_CORE_DEFAULT_1Q_TAG_Port_0_reserved_for_padding0_SHIFT 16
-
-/* SWITCH_CORE :: DEFAULT_1Q_TAG_Port_0 :: PRI [15:13] */
-#define BCHP_SWITCH_CORE_DEFAULT_1Q_TAG_Port_0_PRI_MASK 0x0000e000
-#define BCHP_SWITCH_CORE_DEFAULT_1Q_TAG_Port_0_PRI_SHIFT 13
-#define BCHP_SWITCH_CORE_DEFAULT_1Q_TAG_Port_0_PRI_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: DEFAULT_1Q_TAG_Port_0 :: CFI [12:12] */
-#define BCHP_SWITCH_CORE_DEFAULT_1Q_TAG_Port_0_CFI_MASK 0x00001000
-#define BCHP_SWITCH_CORE_DEFAULT_1Q_TAG_Port_0_CFI_SHIFT 12
-#define BCHP_SWITCH_CORE_DEFAULT_1Q_TAG_Port_0_CFI_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: DEFAULT_1Q_TAG_Port_0 :: VID [11:00] */
-#define BCHP_SWITCH_CORE_DEFAULT_1Q_TAG_Port_0_VID_MASK 0x00000fff
-#define BCHP_SWITCH_CORE_DEFAULT_1Q_TAG_Port_0_VID_SHIFT 0
-#define BCHP_SWITCH_CORE_DEFAULT_1Q_TAG_Port_0_VID_DEFAULT 0x00000001
-
-/***************************************************************************
- *DEFAULT_1Q_TAG_Port_1 - Port N 802.1Q Default Tag Registers
- ***************************************************************************/
-/* SWITCH_CORE :: DEFAULT_1Q_TAG_Port_1 :: reserved_for_padding0 [31:16] */
-#define BCHP_SWITCH_CORE_DEFAULT_1Q_TAG_Port_1_reserved_for_padding0_MASK 0xffff0000
-#define BCHP_SWITCH_CORE_DEFAULT_1Q_TAG_Port_1_reserved_for_padding0_SHIFT 16
-
-/* SWITCH_CORE :: DEFAULT_1Q_TAG_Port_1 :: PRI [15:13] */
-#define BCHP_SWITCH_CORE_DEFAULT_1Q_TAG_Port_1_PRI_MASK 0x0000e000
-#define BCHP_SWITCH_CORE_DEFAULT_1Q_TAG_Port_1_PRI_SHIFT 13
-#define BCHP_SWITCH_CORE_DEFAULT_1Q_TAG_Port_1_PRI_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: DEFAULT_1Q_TAG_Port_1 :: CFI [12:12] */
-#define BCHP_SWITCH_CORE_DEFAULT_1Q_TAG_Port_1_CFI_MASK 0x00001000
-#define BCHP_SWITCH_CORE_DEFAULT_1Q_TAG_Port_1_CFI_SHIFT 12
-#define BCHP_SWITCH_CORE_DEFAULT_1Q_TAG_Port_1_CFI_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: DEFAULT_1Q_TAG_Port_1 :: VID [11:00] */
-#define BCHP_SWITCH_CORE_DEFAULT_1Q_TAG_Port_1_VID_MASK 0x00000fff
-#define BCHP_SWITCH_CORE_DEFAULT_1Q_TAG_Port_1_VID_SHIFT 0
-#define BCHP_SWITCH_CORE_DEFAULT_1Q_TAG_Port_1_VID_DEFAULT 0x00000001
-
-/***************************************************************************
- *DEFAULT_1Q_TAG_Port_2 - Port N 802.1Q Default Tag Registers
- ***************************************************************************/
-/* SWITCH_CORE :: DEFAULT_1Q_TAG_Port_2 :: reserved_for_padding0 [31:16] */
-#define BCHP_SWITCH_CORE_DEFAULT_1Q_TAG_Port_2_reserved_for_padding0_MASK 0xffff0000
-#define BCHP_SWITCH_CORE_DEFAULT_1Q_TAG_Port_2_reserved_for_padding0_SHIFT 16
-
-/* SWITCH_CORE :: DEFAULT_1Q_TAG_Port_2 :: PRI [15:13] */
-#define BCHP_SWITCH_CORE_DEFAULT_1Q_TAG_Port_2_PRI_MASK 0x0000e000
-#define BCHP_SWITCH_CORE_DEFAULT_1Q_TAG_Port_2_PRI_SHIFT 13
-#define BCHP_SWITCH_CORE_DEFAULT_1Q_TAG_Port_2_PRI_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: DEFAULT_1Q_TAG_Port_2 :: CFI [12:12] */
-#define BCHP_SWITCH_CORE_DEFAULT_1Q_TAG_Port_2_CFI_MASK 0x00001000
-#define BCHP_SWITCH_CORE_DEFAULT_1Q_TAG_Port_2_CFI_SHIFT 12
-#define BCHP_SWITCH_CORE_DEFAULT_1Q_TAG_Port_2_CFI_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: DEFAULT_1Q_TAG_Port_2 :: VID [11:00] */
-#define BCHP_SWITCH_CORE_DEFAULT_1Q_TAG_Port_2_VID_MASK 0x00000fff
-#define BCHP_SWITCH_CORE_DEFAULT_1Q_TAG_Port_2_VID_SHIFT 0
-#define BCHP_SWITCH_CORE_DEFAULT_1Q_TAG_Port_2_VID_DEFAULT 0x00000001
-
-/***************************************************************************
- *DEFAULT_1Q_TAG_Port_3 - Port N 802.1Q Default Tag Registers
- ***************************************************************************/
-/* SWITCH_CORE :: DEFAULT_1Q_TAG_Port_3 :: reserved_for_padding0 [31:16] */
-#define BCHP_SWITCH_CORE_DEFAULT_1Q_TAG_Port_3_reserved_for_padding0_MASK 0xffff0000
-#define BCHP_SWITCH_CORE_DEFAULT_1Q_TAG_Port_3_reserved_for_padding0_SHIFT 16
-
-/* SWITCH_CORE :: DEFAULT_1Q_TAG_Port_3 :: PRI [15:13] */
-#define BCHP_SWITCH_CORE_DEFAULT_1Q_TAG_Port_3_PRI_MASK 0x0000e000
-#define BCHP_SWITCH_CORE_DEFAULT_1Q_TAG_Port_3_PRI_SHIFT 13
-#define BCHP_SWITCH_CORE_DEFAULT_1Q_TAG_Port_3_PRI_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: DEFAULT_1Q_TAG_Port_3 :: CFI [12:12] */
-#define BCHP_SWITCH_CORE_DEFAULT_1Q_TAG_Port_3_CFI_MASK 0x00001000
-#define BCHP_SWITCH_CORE_DEFAULT_1Q_TAG_Port_3_CFI_SHIFT 12
-#define BCHP_SWITCH_CORE_DEFAULT_1Q_TAG_Port_3_CFI_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: DEFAULT_1Q_TAG_Port_3 :: VID [11:00] */
-#define BCHP_SWITCH_CORE_DEFAULT_1Q_TAG_Port_3_VID_MASK 0x00000fff
-#define BCHP_SWITCH_CORE_DEFAULT_1Q_TAG_Port_3_VID_SHIFT 0
-#define BCHP_SWITCH_CORE_DEFAULT_1Q_TAG_Port_3_VID_DEFAULT 0x00000001
-
-/***************************************************************************
- *DEFAULT_1Q_TAG_Port_4 - Port N 802.1Q Default Tag Registers
- ***************************************************************************/
-/* SWITCH_CORE :: DEFAULT_1Q_TAG_Port_4 :: reserved_for_padding0 [31:16] */
-#define BCHP_SWITCH_CORE_DEFAULT_1Q_TAG_Port_4_reserved_for_padding0_MASK 0xffff0000
-#define BCHP_SWITCH_CORE_DEFAULT_1Q_TAG_Port_4_reserved_for_padding0_SHIFT 16
-
-/* SWITCH_CORE :: DEFAULT_1Q_TAG_Port_4 :: PRI [15:13] */
-#define BCHP_SWITCH_CORE_DEFAULT_1Q_TAG_Port_4_PRI_MASK 0x0000e000
-#define BCHP_SWITCH_CORE_DEFAULT_1Q_TAG_Port_4_PRI_SHIFT 13
-#define BCHP_SWITCH_CORE_DEFAULT_1Q_TAG_Port_4_PRI_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: DEFAULT_1Q_TAG_Port_4 :: CFI [12:12] */
-#define BCHP_SWITCH_CORE_DEFAULT_1Q_TAG_Port_4_CFI_MASK 0x00001000
-#define BCHP_SWITCH_CORE_DEFAULT_1Q_TAG_Port_4_CFI_SHIFT 12
-#define BCHP_SWITCH_CORE_DEFAULT_1Q_TAG_Port_4_CFI_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: DEFAULT_1Q_TAG_Port_4 :: VID [11:00] */
-#define BCHP_SWITCH_CORE_DEFAULT_1Q_TAG_Port_4_VID_MASK 0x00000fff
-#define BCHP_SWITCH_CORE_DEFAULT_1Q_TAG_Port_4_VID_SHIFT 0
-#define BCHP_SWITCH_CORE_DEFAULT_1Q_TAG_Port_4_VID_DEFAULT 0x00000001
-
-/***************************************************************************
- *DEFAULT_1Q_TAG_Port_5 - Port N 802.1Q Default Tag Registers
- ***************************************************************************/
-/* SWITCH_CORE :: DEFAULT_1Q_TAG_Port_5 :: reserved_for_padding0 [31:16] */
-#define BCHP_SWITCH_CORE_DEFAULT_1Q_TAG_Port_5_reserved_for_padding0_MASK 0xffff0000
-#define BCHP_SWITCH_CORE_DEFAULT_1Q_TAG_Port_5_reserved_for_padding0_SHIFT 16
-
-/* SWITCH_CORE :: DEFAULT_1Q_TAG_Port_5 :: PRI [15:13] */
-#define BCHP_SWITCH_CORE_DEFAULT_1Q_TAG_Port_5_PRI_MASK 0x0000e000
-#define BCHP_SWITCH_CORE_DEFAULT_1Q_TAG_Port_5_PRI_SHIFT 13
-#define BCHP_SWITCH_CORE_DEFAULT_1Q_TAG_Port_5_PRI_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: DEFAULT_1Q_TAG_Port_5 :: CFI [12:12] */
-#define BCHP_SWITCH_CORE_DEFAULT_1Q_TAG_Port_5_CFI_MASK 0x00001000
-#define BCHP_SWITCH_CORE_DEFAULT_1Q_TAG_Port_5_CFI_SHIFT 12
-#define BCHP_SWITCH_CORE_DEFAULT_1Q_TAG_Port_5_CFI_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: DEFAULT_1Q_TAG_Port_5 :: VID [11:00] */
-#define BCHP_SWITCH_CORE_DEFAULT_1Q_TAG_Port_5_VID_MASK 0x00000fff
-#define BCHP_SWITCH_CORE_DEFAULT_1Q_TAG_Port_5_VID_SHIFT 0
-#define BCHP_SWITCH_CORE_DEFAULT_1Q_TAG_Port_5_VID_DEFAULT 0x00000001
-
-/***************************************************************************
- *DEFAULT_1Q_TAG_P7 - Port 7 802.1Q Default Tag Registers
- ***************************************************************************/
-/* SWITCH_CORE :: DEFAULT_1Q_TAG_P7 :: reserved_for_padding0 [31:16] */
-#define BCHP_SWITCH_CORE_DEFAULT_1Q_TAG_P7_reserved_for_padding0_MASK 0xffff0000
-#define BCHP_SWITCH_CORE_DEFAULT_1Q_TAG_P7_reserved_for_padding0_SHIFT 16
-
-/* SWITCH_CORE :: DEFAULT_1Q_TAG_P7 :: PRI [15:13] */
-#define BCHP_SWITCH_CORE_DEFAULT_1Q_TAG_P7_PRI_MASK 0x0000e000
-#define BCHP_SWITCH_CORE_DEFAULT_1Q_TAG_P7_PRI_SHIFT 13
-#define BCHP_SWITCH_CORE_DEFAULT_1Q_TAG_P7_PRI_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: DEFAULT_1Q_TAG_P7 :: CFI [12:12] */
-#define BCHP_SWITCH_CORE_DEFAULT_1Q_TAG_P7_CFI_MASK 0x00001000
-#define BCHP_SWITCH_CORE_DEFAULT_1Q_TAG_P7_CFI_SHIFT 12
-#define BCHP_SWITCH_CORE_DEFAULT_1Q_TAG_P7_CFI_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: DEFAULT_1Q_TAG_P7 :: VID [11:00] */
-#define BCHP_SWITCH_CORE_DEFAULT_1Q_TAG_P7_VID_MASK 0x00000fff
-#define BCHP_SWITCH_CORE_DEFAULT_1Q_TAG_P7_VID_SHIFT 0
-#define BCHP_SWITCH_CORE_DEFAULT_1Q_TAG_P7_VID_DEFAULT 0x00000001
-
-/***************************************************************************
- *DEFAULT_1Q_TAG_IMP - Port 8 802.1Q Default Tag Registers
- ***************************************************************************/
-/* SWITCH_CORE :: DEFAULT_1Q_TAG_IMP :: reserved_for_padding0 [31:16] */
-#define BCHP_SWITCH_CORE_DEFAULT_1Q_TAG_IMP_reserved_for_padding0_MASK 0xffff0000
-#define BCHP_SWITCH_CORE_DEFAULT_1Q_TAG_IMP_reserved_for_padding0_SHIFT 16
-
-/* SWITCH_CORE :: DEFAULT_1Q_TAG_IMP :: PRI [15:13] */
-#define BCHP_SWITCH_CORE_DEFAULT_1Q_TAG_IMP_PRI_MASK 0x0000e000
-#define BCHP_SWITCH_CORE_DEFAULT_1Q_TAG_IMP_PRI_SHIFT 13
-#define BCHP_SWITCH_CORE_DEFAULT_1Q_TAG_IMP_PRI_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: DEFAULT_1Q_TAG_IMP :: CFI [12:12] */
-#define BCHP_SWITCH_CORE_DEFAULT_1Q_TAG_IMP_CFI_MASK 0x00001000
-#define BCHP_SWITCH_CORE_DEFAULT_1Q_TAG_IMP_CFI_SHIFT 12
-#define BCHP_SWITCH_CORE_DEFAULT_1Q_TAG_IMP_CFI_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: DEFAULT_1Q_TAG_IMP :: VID [11:00] */
-#define BCHP_SWITCH_CORE_DEFAULT_1Q_TAG_IMP_VID_MASK 0x00000fff
-#define BCHP_SWITCH_CORE_DEFAULT_1Q_TAG_IMP_VID_SHIFT 0
-#define BCHP_SWITCH_CORE_DEFAULT_1Q_TAG_IMP_VID_DEFAULT 0x00000001
-
-/***************************************************************************
- *DTAG_TPID - Double Tagging TPID Registers
- ***************************************************************************/
-/* SWITCH_CORE :: DTAG_TPID :: reserved_for_padding0 [31:16] */
-#define BCHP_SWITCH_CORE_DTAG_TPID_reserved_for_padding0_MASK 0xffff0000
-#define BCHP_SWITCH_CORE_DTAG_TPID_reserved_for_padding0_SHIFT 16
-
-/* SWITCH_CORE :: DTAG_TPID :: ISP_TPID [15:00] */
-#define BCHP_SWITCH_CORE_DTAG_TPID_ISP_TPID_MASK 0x0000ffff
-#define BCHP_SWITCH_CORE_DTAG_TPID_ISP_TPID_SHIFT 0
-#define BCHP_SWITCH_CORE_DTAG_TPID_ISP_TPID_DEFAULT 0x000088a8
-
-/***************************************************************************
- *ISP_SEL_PORTMAP - ISP Port Selection Portmap Registers
- ***************************************************************************/
-/* SWITCH_CORE :: ISP_SEL_PORTMAP :: reserved_for_padding0 [31:16] */
-#define BCHP_SWITCH_CORE_ISP_SEL_PORTMAP_reserved_for_padding0_MASK 0xffff0000
-#define BCHP_SWITCH_CORE_ISP_SEL_PORTMAP_reserved_for_padding0_SHIFT 16
-
-/* SWITCH_CORE :: ISP_SEL_PORTMAP :: SWITCH_RESV [15:09] */
-#define BCHP_SWITCH_CORE_ISP_SEL_PORTMAP_SWITCH_RESV_MASK 0x0000fe00
-#define BCHP_SWITCH_CORE_ISP_SEL_PORTMAP_SWITCH_RESV_SHIFT 9
-#define BCHP_SWITCH_CORE_ISP_SEL_PORTMAP_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: ISP_SEL_PORTMAP :: ISP_PORTMAP [08:00] */
-#define BCHP_SWITCH_CORE_ISP_SEL_PORTMAP_ISP_PORTMAP_MASK 0x000001ff
-#define BCHP_SWITCH_CORE_ISP_SEL_PORTMAP_ISP_PORTMAP_SHIFT 0
-#define BCHP_SWITCH_CORE_ISP_SEL_PORTMAP_ISP_PORTMAP_DEFAULT 0x00000000
-
-/***************************************************************************
- *EGRESS_VID_RMK_TBL_ACS - Egress VID Remarking Table Access Register
- ***************************************************************************/
-/* SWITCH_CORE :: EGRESS_VID_RMK_TBL_ACS :: GLOBAL_WR_EN [31:31] */
-#define BCHP_SWITCH_CORE_EGRESS_VID_RMK_TBL_ACS_GLOBAL_WR_EN_MASK 0x80000000
-#define BCHP_SWITCH_CORE_EGRESS_VID_RMK_TBL_ACS_GLOBAL_WR_EN_SHIFT 31
-#define BCHP_SWITCH_CORE_EGRESS_VID_RMK_TBL_ACS_GLOBAL_WR_EN_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: EGRESS_VID_RMK_TBL_ACS :: SWITCH_RESV1 [30:16] */
-#define BCHP_SWITCH_CORE_EGRESS_VID_RMK_TBL_ACS_SWITCH_RESV1_MASK 0x7fff0000
-#define BCHP_SWITCH_CORE_EGRESS_VID_RMK_TBL_ACS_SWITCH_RESV1_SHIFT 16
-#define BCHP_SWITCH_CORE_EGRESS_VID_RMK_TBL_ACS_SWITCH_RESV1_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: EGRESS_VID_RMK_TBL_ACS :: TBL_ADDR [15:08] */
-#define BCHP_SWITCH_CORE_EGRESS_VID_RMK_TBL_ACS_TBL_ADDR_MASK 0x0000ff00
-#define BCHP_SWITCH_CORE_EGRESS_VID_RMK_TBL_ACS_TBL_ADDR_SHIFT 8
-#define BCHP_SWITCH_CORE_EGRESS_VID_RMK_TBL_ACS_TBL_ADDR_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: EGRESS_VID_RMK_TBL_ACS :: EGRESS_PORT [07:04] */
-#define BCHP_SWITCH_CORE_EGRESS_VID_RMK_TBL_ACS_EGRESS_PORT_MASK 0x000000f0
-#define BCHP_SWITCH_CORE_EGRESS_VID_RMK_TBL_ACS_EGRESS_PORT_SHIFT 4
-#define BCHP_SWITCH_CORE_EGRESS_VID_RMK_TBL_ACS_EGRESS_PORT_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: EGRESS_VID_RMK_TBL_ACS :: SWITCH_RESV2 [03:03] */
-#define BCHP_SWITCH_CORE_EGRESS_VID_RMK_TBL_ACS_SWITCH_RESV2_MASK 0x00000008
-#define BCHP_SWITCH_CORE_EGRESS_VID_RMK_TBL_ACS_SWITCH_RESV2_SHIFT 3
-#define BCHP_SWITCH_CORE_EGRESS_VID_RMK_TBL_ACS_SWITCH_RESV2_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: EGRESS_VID_RMK_TBL_ACS :: RESET_EVT [02:02] */
-#define BCHP_SWITCH_CORE_EGRESS_VID_RMK_TBL_ACS_RESET_EVT_MASK 0x00000004
-#define BCHP_SWITCH_CORE_EGRESS_VID_RMK_TBL_ACS_RESET_EVT_SHIFT 2
-#define BCHP_SWITCH_CORE_EGRESS_VID_RMK_TBL_ACS_RESET_EVT_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: EGRESS_VID_RMK_TBL_ACS :: OP [01:01] */
-#define BCHP_SWITCH_CORE_EGRESS_VID_RMK_TBL_ACS_OP_MASK 0x00000002
-#define BCHP_SWITCH_CORE_EGRESS_VID_RMK_TBL_ACS_OP_SHIFT 1
-#define BCHP_SWITCH_CORE_EGRESS_VID_RMK_TBL_ACS_OP_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: EGRESS_VID_RMK_TBL_ACS :: START_DONE [00:00] */
-#define BCHP_SWITCH_CORE_EGRESS_VID_RMK_TBL_ACS_START_DONE_MASK 0x00000001
-#define BCHP_SWITCH_CORE_EGRESS_VID_RMK_TBL_ACS_START_DONE_SHIFT 0
-#define BCHP_SWITCH_CORE_EGRESS_VID_RMK_TBL_ACS_START_DONE_DEFAULT 0x00000000
-
-/***************************************************************************
- *EGRESS_VID_RMK_TBL_DATA - Egress VID Remarking Table Data Register
- ***************************************************************************/
-/* SWITCH_CORE :: EGRESS_VID_RMK_TBL_DATA :: SWITCH_RESV1 [31:30] */
-#define BCHP_SWITCH_CORE_EGRESS_VID_RMK_TBL_DATA_SWITCH_RESV1_MASK 0xc0000000
-#define BCHP_SWITCH_CORE_EGRESS_VID_RMK_TBL_DATA_SWITCH_RESV1_SHIFT 30
-#define BCHP_SWITCH_CORE_EGRESS_VID_RMK_TBL_DATA_SWITCH_RESV1_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: EGRESS_VID_RMK_TBL_DATA :: OUTER_OP [29:28] */
-#define BCHP_SWITCH_CORE_EGRESS_VID_RMK_TBL_DATA_OUTER_OP_MASK 0x30000000
-#define BCHP_SWITCH_CORE_EGRESS_VID_RMK_TBL_DATA_OUTER_OP_SHIFT 28
-#define BCHP_SWITCH_CORE_EGRESS_VID_RMK_TBL_DATA_OUTER_OP_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: EGRESS_VID_RMK_TBL_DATA :: OUTER_VID [27:16] */
-#define BCHP_SWITCH_CORE_EGRESS_VID_RMK_TBL_DATA_OUTER_VID_MASK 0x0fff0000
-#define BCHP_SWITCH_CORE_EGRESS_VID_RMK_TBL_DATA_OUTER_VID_SHIFT 16
-#define BCHP_SWITCH_CORE_EGRESS_VID_RMK_TBL_DATA_OUTER_VID_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: EGRESS_VID_RMK_TBL_DATA :: SWITCH_RESV2 [15:14] */
-#define BCHP_SWITCH_CORE_EGRESS_VID_RMK_TBL_DATA_SWITCH_RESV2_MASK 0x0000c000
-#define BCHP_SWITCH_CORE_EGRESS_VID_RMK_TBL_DATA_SWITCH_RESV2_SHIFT 14
-#define BCHP_SWITCH_CORE_EGRESS_VID_RMK_TBL_DATA_SWITCH_RESV2_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: EGRESS_VID_RMK_TBL_DATA :: INNER_OP [13:12] */
-#define BCHP_SWITCH_CORE_EGRESS_VID_RMK_TBL_DATA_INNER_OP_MASK 0x00003000
-#define BCHP_SWITCH_CORE_EGRESS_VID_RMK_TBL_DATA_INNER_OP_SHIFT 12
-#define BCHP_SWITCH_CORE_EGRESS_VID_RMK_TBL_DATA_INNER_OP_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: EGRESS_VID_RMK_TBL_DATA :: INNER_VID [11:00] */
-#define BCHP_SWITCH_CORE_EGRESS_VID_RMK_TBL_DATA_INNER_VID_MASK 0x00000fff
-#define BCHP_SWITCH_CORE_EGRESS_VID_RMK_TBL_DATA_INNER_VID_SHIFT 0
-#define BCHP_SWITCH_CORE_EGRESS_VID_RMK_TBL_DATA_INNER_VID_DEFAULT 0x00000000
-
-/***************************************************************************
- *JOIN_ALL_VLAN_EN - Join All VLAN Enable Register
- ***************************************************************************/
-/* SWITCH_CORE :: JOIN_ALL_VLAN_EN :: reserved_for_padding0 [31:16] */
-#define BCHP_SWITCH_CORE_JOIN_ALL_VLAN_EN_reserved_for_padding0_MASK 0xffff0000
-#define BCHP_SWITCH_CORE_JOIN_ALL_VLAN_EN_reserved_for_padding0_SHIFT 16
-
-/* SWITCH_CORE :: JOIN_ALL_VLAN_EN :: SWITCH_RESV [15:09] */
-#define BCHP_SWITCH_CORE_JOIN_ALL_VLAN_EN_SWITCH_RESV_MASK 0x0000fe00
-#define BCHP_SWITCH_CORE_JOIN_ALL_VLAN_EN_SWITCH_RESV_SHIFT 9
-#define BCHP_SWITCH_CORE_JOIN_ALL_VLAN_EN_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: JOIN_ALL_VLAN_EN :: JOIN_ALL_VLAN_EN [08:00] */
-#define BCHP_SWITCH_CORE_JOIN_ALL_VLAN_EN_JOIN_ALL_VLAN_EN_MASK 0x000001ff
-#define BCHP_SWITCH_CORE_JOIN_ALL_VLAN_EN_JOIN_ALL_VLAN_EN_SHIFT 0
-#define BCHP_SWITCH_CORE_JOIN_ALL_VLAN_EN_JOIN_ALL_VLAN_EN_DEFAULT 0x00000000
-
-/***************************************************************************
- *PORT_IVL_SVL_CTRL - Port IVL or SVL Control Register
- ***************************************************************************/
-/* SWITCH_CORE :: PORT_IVL_SVL_CTRL :: reserved_for_padding0 [31:16] */
-#define BCHP_SWITCH_CORE_PORT_IVL_SVL_CTRL_reserved_for_padding0_MASK 0xffff0000
-#define BCHP_SWITCH_CORE_PORT_IVL_SVL_CTRL_reserved_for_padding0_SHIFT 16
-
-/* SWITCH_CORE :: PORT_IVL_SVL_CTRL :: PORT_IVL_SVL_EN [15:15] */
-#define BCHP_SWITCH_CORE_PORT_IVL_SVL_CTRL_PORT_IVL_SVL_EN_MASK 0x00008000
-#define BCHP_SWITCH_CORE_PORT_IVL_SVL_CTRL_PORT_IVL_SVL_EN_SHIFT 15
-#define BCHP_SWITCH_CORE_PORT_IVL_SVL_CTRL_PORT_IVL_SVL_EN_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: PORT_IVL_SVL_CTRL :: SWITCH_RESV [14:09] */
-#define BCHP_SWITCH_CORE_PORT_IVL_SVL_CTRL_SWITCH_RESV_MASK 0x00007e00
-#define BCHP_SWITCH_CORE_PORT_IVL_SVL_CTRL_SWITCH_RESV_SHIFT 9
-#define BCHP_SWITCH_CORE_PORT_IVL_SVL_CTRL_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: PORT_IVL_SVL_CTRL :: PORT_IVL_SVL_SEL [08:00] */
-#define BCHP_SWITCH_CORE_PORT_IVL_SVL_CTRL_PORT_IVL_SVL_SEL_MASK 0x000001ff
-#define BCHP_SWITCH_CORE_PORT_IVL_SVL_CTRL_PORT_IVL_SVL_SEL_SHIFT 0
-#define BCHP_SWITCH_CORE_PORT_IVL_SVL_CTRL_PORT_IVL_SVL_SEL_DEFAULT 0x00000000
-
-/***************************************************************************
- *BCM8021Q_REG_SPARE0 - Spare 0 Register (Not2Release)
- ***************************************************************************/
-/* SWITCH_CORE :: BCM8021Q_REG_SPARE0 :: BCM8021Q_REG_SPARE0 [31:00] */
-#define BCHP_SWITCH_CORE_BCM8021Q_REG_SPARE0_BCM8021Q_REG_SPARE0_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_BCM8021Q_REG_SPARE0_BCM8021Q_REG_SPARE0_SHIFT 0
-#define BCHP_SWITCH_CORE_BCM8021Q_REG_SPARE0_BCM8021Q_REG_SPARE0_DEFAULT 0x00000000
-
-/***************************************************************************
- *BCM8021Q_REG_SPARE1 - Spare 1 Register (Not2Release)
- ***************************************************************************/
-/* SWITCH_CORE :: BCM8021Q_REG_SPARE1 :: BCM8021Q_REG_SPARE1 [31:00] */
-#define BCHP_SWITCH_CORE_BCM8021Q_REG_SPARE1_BCM8021Q_REG_SPARE1_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_BCM8021Q_REG_SPARE1_BCM8021Q_REG_SPARE1_SHIFT 0
-#define BCHP_SWITCH_CORE_BCM8021Q_REG_SPARE1_BCM8021Q_REG_SPARE1_DEFAULT 0x00000000
-
-/***************************************************************************
- *DOS_CTRL - DoS Control RegisterRegister
- ***************************************************************************/
-/* SWITCH_CORE :: DOS_CTRL :: SWITCH_RESV_1 [31:14] */
-#define BCHP_SWITCH_CORE_DOS_CTRL_SWITCH_RESV_1_MASK 0xffffc000
-#define BCHP_SWITCH_CORE_DOS_CTRL_SWITCH_RESV_1_SHIFT 14
-#define BCHP_SWITCH_CORE_DOS_CTRL_SWITCH_RESV_1_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: DOS_CTRL :: ICMPV6_LONG_PING_DROP_EN [13:13] */
-#define BCHP_SWITCH_CORE_DOS_CTRL_ICMPV6_LONG_PING_DROP_EN_MASK 0x00002000
-#define BCHP_SWITCH_CORE_DOS_CTRL_ICMPV6_LONG_PING_DROP_EN_SHIFT 13
-#define BCHP_SWITCH_CORE_DOS_CTRL_ICMPV6_LONG_PING_DROP_EN_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: DOS_CTRL :: ICMPV4_LONG_PING_DROP_EN [12:12] */
-#define BCHP_SWITCH_CORE_DOS_CTRL_ICMPV4_LONG_PING_DROP_EN_MASK 0x00001000
-#define BCHP_SWITCH_CORE_DOS_CTRL_ICMPV4_LONG_PING_DROP_EN_SHIFT 12
-#define BCHP_SWITCH_CORE_DOS_CTRL_ICMPV4_LONG_PING_DROP_EN_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: DOS_CTRL :: ICMPV6_FRAGMENT_DROP_EN [11:11] */
-#define BCHP_SWITCH_CORE_DOS_CTRL_ICMPV6_FRAGMENT_DROP_EN_MASK 0x00000800
-#define BCHP_SWITCH_CORE_DOS_CTRL_ICMPV6_FRAGMENT_DROP_EN_SHIFT 11
-#define BCHP_SWITCH_CORE_DOS_CTRL_ICMPV6_FRAGMENT_DROP_EN_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: DOS_CTRL :: ICMPV4_FRAGMENT_DROP_EN [10:10] */
-#define BCHP_SWITCH_CORE_DOS_CTRL_ICMPV4_FRAGMENT_DROP_EN_MASK 0x00000400
-#define BCHP_SWITCH_CORE_DOS_CTRL_ICMPV4_FRAGMENT_DROP_EN_SHIFT 10
-#define BCHP_SWITCH_CORE_DOS_CTRL_ICMPV4_FRAGMENT_DROP_EN_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: DOS_CTRL :: TCP_FRAG_ERR_DROP_EN [09:09] */
-#define BCHP_SWITCH_CORE_DOS_CTRL_TCP_FRAG_ERR_DROP_EN_MASK 0x00000200
-#define BCHP_SWITCH_CORE_DOS_CTRL_TCP_FRAG_ERR_DROP_EN_SHIFT 9
-#define BCHP_SWITCH_CORE_DOS_CTRL_TCP_FRAG_ERR_DROP_EN_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: DOS_CTRL :: TCP_SHORT_HDR_DROP_EN [08:08] */
-#define BCHP_SWITCH_CORE_DOS_CTRL_TCP_SHORT_HDR_DROP_EN_MASK 0x00000100
-#define BCHP_SWITCH_CORE_DOS_CTRL_TCP_SHORT_HDR_DROP_EN_SHIFT 8
-#define BCHP_SWITCH_CORE_DOS_CTRL_TCP_SHORT_HDR_DROP_EN_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: DOS_CTRL :: TCP_SYN_ERR_DROP_EN [07:07] */
-#define BCHP_SWITCH_CORE_DOS_CTRL_TCP_SYN_ERR_DROP_EN_MASK 0x00000080
-#define BCHP_SWITCH_CORE_DOS_CTRL_TCP_SYN_ERR_DROP_EN_SHIFT 7
-#define BCHP_SWITCH_CORE_DOS_CTRL_TCP_SYN_ERR_DROP_EN_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: DOS_CTRL :: TCP_SYNFIN_SCAN_DROP_EN [06:06] */
-#define BCHP_SWITCH_CORE_DOS_CTRL_TCP_SYNFIN_SCAN_DROP_EN_MASK 0x00000040
-#define BCHP_SWITCH_CORE_DOS_CTRL_TCP_SYNFIN_SCAN_DROP_EN_SHIFT 6
-#define BCHP_SWITCH_CORE_DOS_CTRL_TCP_SYNFIN_SCAN_DROP_EN_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: DOS_CTRL :: TCP_XMASS_SCAN_DROP_EN [05:05] */
-#define BCHP_SWITCH_CORE_DOS_CTRL_TCP_XMASS_SCAN_DROP_EN_MASK 0x00000020
-#define BCHP_SWITCH_CORE_DOS_CTRL_TCP_XMASS_SCAN_DROP_EN_SHIFT 5
-#define BCHP_SWITCH_CORE_DOS_CTRL_TCP_XMASS_SCAN_DROP_EN_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: DOS_CTRL :: TCP_NULL_SCAN_DROP_EN [04:04] */
-#define BCHP_SWITCH_CORE_DOS_CTRL_TCP_NULL_SCAN_DROP_EN_MASK 0x00000010
-#define BCHP_SWITCH_CORE_DOS_CTRL_TCP_NULL_SCAN_DROP_EN_SHIFT 4
-#define BCHP_SWITCH_CORE_DOS_CTRL_TCP_NULL_SCAN_DROP_EN_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: DOS_CTRL :: UDP_BLAT_DROP_EN [03:03] */
-#define BCHP_SWITCH_CORE_DOS_CTRL_UDP_BLAT_DROP_EN_MASK 0x00000008
-#define BCHP_SWITCH_CORE_DOS_CTRL_UDP_BLAT_DROP_EN_SHIFT 3
-#define BCHP_SWITCH_CORE_DOS_CTRL_UDP_BLAT_DROP_EN_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: DOS_CTRL :: TCP_BLAT_DROP_EN [02:02] */
-#define BCHP_SWITCH_CORE_DOS_CTRL_TCP_BLAT_DROP_EN_MASK 0x00000004
-#define BCHP_SWITCH_CORE_DOS_CTRL_TCP_BLAT_DROP_EN_SHIFT 2
-#define BCHP_SWITCH_CORE_DOS_CTRL_TCP_BLAT_DROP_EN_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: DOS_CTRL :: IP_LAND_DROP_EN [01:01] */
-#define BCHP_SWITCH_CORE_DOS_CTRL_IP_LAND_DROP_EN_MASK 0x00000002
-#define BCHP_SWITCH_CORE_DOS_CTRL_IP_LAND_DROP_EN_SHIFT 1
-#define BCHP_SWITCH_CORE_DOS_CTRL_IP_LAND_DROP_EN_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: DOS_CTRL :: SWITCH_RESV_0 [00:00] */
-#define BCHP_SWITCH_CORE_DOS_CTRL_SWITCH_RESV_0_MASK 0x00000001
-#define BCHP_SWITCH_CORE_DOS_CTRL_SWITCH_RESV_0_SHIFT 0
-#define BCHP_SWITCH_CORE_DOS_CTRL_SWITCH_RESV_0_DEFAULT 0x00000001
-
-/***************************************************************************
- *MINIMUM_TCP_HDR_SZ - Minimum TCP Header Size Register
- ***************************************************************************/
-/* SWITCH_CORE :: MINIMUM_TCP_HDR_SZ :: reserved_for_padding0 [31:08] */
-#define BCHP_SWITCH_CORE_MINIMUM_TCP_HDR_SZ_reserved_for_padding0_MASK 0xffffff00
-#define BCHP_SWITCH_CORE_MINIMUM_TCP_HDR_SZ_reserved_for_padding0_SHIFT 8
-
-/* SWITCH_CORE :: MINIMUM_TCP_HDR_SZ :: MIN_TCP_HDR_SZ [07:00] */
-#define BCHP_SWITCH_CORE_MINIMUM_TCP_HDR_SZ_MIN_TCP_HDR_SZ_MASK 0x000000ff
-#define BCHP_SWITCH_CORE_MINIMUM_TCP_HDR_SZ_MIN_TCP_HDR_SZ_SHIFT 0
-#define BCHP_SWITCH_CORE_MINIMUM_TCP_HDR_SZ_MIN_TCP_HDR_SZ_DEFAULT 0x00000014
-
-/***************************************************************************
- *MAX_ICMPV4_SIZE_REG - Maximum ICMPv4 Size Register
- ***************************************************************************/
-/* SWITCH_CORE :: MAX_ICMPV4_SIZE_REG :: MAX_ICMPV4_SIZE [31:00] */
-#define BCHP_SWITCH_CORE_MAX_ICMPV4_SIZE_REG_MAX_ICMPV4_SIZE_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_MAX_ICMPV4_SIZE_REG_MAX_ICMPV4_SIZE_SHIFT 0
-#define BCHP_SWITCH_CORE_MAX_ICMPV4_SIZE_REG_MAX_ICMPV4_SIZE_DEFAULT 0x00000200
-
-/***************************************************************************
- *MAX_ICMPV6_SIZE_REG - Maximum ICMPv6 Size Register
- ***************************************************************************/
-/* SWITCH_CORE :: MAX_ICMPV6_SIZE_REG :: MAX_ICMPV6_SIZE [31:00] */
-#define BCHP_SWITCH_CORE_MAX_ICMPV6_SIZE_REG_MAX_ICMPV6_SIZE_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_MAX_ICMPV6_SIZE_REG_MAX_ICMPV6_SIZE_SHIFT 0
-#define BCHP_SWITCH_CORE_MAX_ICMPV6_SIZE_REG_MAX_ICMPV6_SIZE_DEFAULT 0x00000200
-
-/***************************************************************************
- *DOS_DIS_LRN_REG - DoS Disable Learn Register
- ***************************************************************************/
-/* SWITCH_CORE :: DOS_DIS_LRN_REG :: reserved_for_padding0 [31:08] */
-#define BCHP_SWITCH_CORE_DOS_DIS_LRN_REG_reserved_for_padding0_MASK 0xffffff00
-#define BCHP_SWITCH_CORE_DOS_DIS_LRN_REG_reserved_for_padding0_SHIFT 8
-
-/* SWITCH_CORE :: DOS_DIS_LRN_REG :: SWITCH_RESV [07:01] */
-#define BCHP_SWITCH_CORE_DOS_DIS_LRN_REG_SWITCH_RESV_MASK 0x000000fe
-#define BCHP_SWITCH_CORE_DOS_DIS_LRN_REG_SWITCH_RESV_SHIFT 1
-#define BCHP_SWITCH_CORE_DOS_DIS_LRN_REG_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: DOS_DIS_LRN_REG :: DOS_DIS_LRN [00:00] */
-#define BCHP_SWITCH_CORE_DOS_DIS_LRN_REG_DOS_DIS_LRN_MASK 0x00000001
-#define BCHP_SWITCH_CORE_DOS_DIS_LRN_REG_DOS_DIS_LRN_SHIFT 0
-#define BCHP_SWITCH_CORE_DOS_DIS_LRN_REG_DOS_DIS_LRN_DEFAULT 0x00000000
-
-/***************************************************************************
- *DOS_REG_SPARE0 - Spare 0 Register (Not2Release)
- ***************************************************************************/
-/* SWITCH_CORE :: DOS_REG_SPARE0 :: DOS_REG_SPARE0 [31:00] */
-#define BCHP_SWITCH_CORE_DOS_REG_SPARE0_DOS_REG_SPARE0_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_DOS_REG_SPARE0_DOS_REG_SPARE0_SHIFT 0
-#define BCHP_SWITCH_CORE_DOS_REG_SPARE0_DOS_REG_SPARE0_DEFAULT 0x00000000
-
-/***************************************************************************
- *DOS_REG_SPARE1 - Spare 1 Register (Not2Release)
- ***************************************************************************/
-/* SWITCH_CORE :: DOS_REG_SPARE1 :: DOS_REG_SPARE1 [31:00] */
-#define BCHP_SWITCH_CORE_DOS_REG_SPARE1_DOS_REG_SPARE1_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_DOS_REG_SPARE1_DOS_REG_SPARE1_SHIFT 0
-#define BCHP_SWITCH_CORE_DOS_REG_SPARE1_DOS_REG_SPARE1_DEFAULT 0x00000000
-
-/***************************************************************************
- *JUMBO_PORT_MASK - Jumbo Frame Port Mask Registers
- ***************************************************************************/
-/* SWITCH_CORE :: JUMBO_PORT_MASK :: SWITCH_RESV_1 [31:25] */
-#define BCHP_SWITCH_CORE_JUMBO_PORT_MASK_SWITCH_RESV_1_MASK 0xfe000000
-#define BCHP_SWITCH_CORE_JUMBO_PORT_MASK_SWITCH_RESV_1_SHIFT 25
-#define BCHP_SWITCH_CORE_JUMBO_PORT_MASK_SWITCH_RESV_1_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: JUMBO_PORT_MASK :: EN_10_100_JUMBO [24:24] */
-#define BCHP_SWITCH_CORE_JUMBO_PORT_MASK_EN_10_100_JUMBO_MASK 0x01000000
-#define BCHP_SWITCH_CORE_JUMBO_PORT_MASK_EN_10_100_JUMBO_SHIFT 24
-#define BCHP_SWITCH_CORE_JUMBO_PORT_MASK_EN_10_100_JUMBO_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: JUMBO_PORT_MASK :: SWITCH_RESV_0 [23:09] */
-#define BCHP_SWITCH_CORE_JUMBO_PORT_MASK_SWITCH_RESV_0_MASK 0x00fffe00
-#define BCHP_SWITCH_CORE_JUMBO_PORT_MASK_SWITCH_RESV_0_SHIFT 9
-#define BCHP_SWITCH_CORE_JUMBO_PORT_MASK_SWITCH_RESV_0_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: JUMBO_PORT_MASK :: JUMBO_FM_PORT_MASK [08:00] */
-#define BCHP_SWITCH_CORE_JUMBO_PORT_MASK_JUMBO_FM_PORT_MASK_MASK 0x000001ff
-#define BCHP_SWITCH_CORE_JUMBO_PORT_MASK_JUMBO_FM_PORT_MASK_SHIFT 0
-#define BCHP_SWITCH_CORE_JUMBO_PORT_MASK_JUMBO_FM_PORT_MASK_DEFAULT 0x00000000
-
-/***************************************************************************
- *MIB_GD_FM_MAX_SIZE - Jumbo MIB Good Frame Max Size Registers
- ***************************************************************************/
-/* SWITCH_CORE :: MIB_GD_FM_MAX_SIZE :: reserved_for_padding0 [31:16] */
-#define BCHP_SWITCH_CORE_MIB_GD_FM_MAX_SIZE_reserved_for_padding0_MASK 0xffff0000
-#define BCHP_SWITCH_CORE_MIB_GD_FM_MAX_SIZE_reserved_for_padding0_SHIFT 16
-
-/* SWITCH_CORE :: MIB_GD_FM_MAX_SIZE :: SWITCH_RESV [15:14] */
-#define BCHP_SWITCH_CORE_MIB_GD_FM_MAX_SIZE_SWITCH_RESV_MASK 0x0000c000
-#define BCHP_SWITCH_CORE_MIB_GD_FM_MAX_SIZE_SWITCH_RESV_SHIFT 14
-#define BCHP_SWITCH_CORE_MIB_GD_FM_MAX_SIZE_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: MIB_GD_FM_MAX_SIZE :: MAX_SIZE [13:00] */
-#define BCHP_SWITCH_CORE_MIB_GD_FM_MAX_SIZE_MAX_SIZE_MASK 0x00003fff
-#define BCHP_SWITCH_CORE_MIB_GD_FM_MAX_SIZE_MAX_SIZE_SHIFT 0
-#define BCHP_SWITCH_CORE_MIB_GD_FM_MAX_SIZE_MAX_SIZE_DEFAULT 0x000007d0
-
-/***************************************************************************
- *JUMBO_CTRL_REG_SPARE0 - Spare 0 Register (Not2Release)
- ***************************************************************************/
-/* SWITCH_CORE :: JUMBO_CTRL_REG_SPARE0 :: JUMBO_CTRL_REG_SPARE0 [31:00] */
-#define BCHP_SWITCH_CORE_JUMBO_CTRL_REG_SPARE0_JUMBO_CTRL_REG_SPARE0_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_JUMBO_CTRL_REG_SPARE0_JUMBO_CTRL_REG_SPARE0_SHIFT 0
-#define BCHP_SWITCH_CORE_JUMBO_CTRL_REG_SPARE0_JUMBO_CTRL_REG_SPARE0_DEFAULT 0x00000000
-
-/***************************************************************************
- *JUMBO_CTRL_REG_SPARE1 - Spare 1 Register (Not2Release)
- ***************************************************************************/
-/* SWITCH_CORE :: JUMBO_CTRL_REG_SPARE1 :: JUMBO_CTRL_REG_SPARE1 [31:00] */
-#define BCHP_SWITCH_CORE_JUMBO_CTRL_REG_SPARE1_JUMBO_CTRL_REG_SPARE1_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_JUMBO_CTRL_REG_SPARE1_JUMBO_CTRL_REG_SPARE1_SHIFT 0
-#define BCHP_SWITCH_CORE_JUMBO_CTRL_REG_SPARE1_JUMBO_CTRL_REG_SPARE1_DEFAULT 0x00000000
-
-/***************************************************************************
- *COMM_IRC_CON - Common Ingress rate Control Configuration Registers
- ***************************************************************************/
-/* SWITCH_CORE :: COMM_IRC_CON :: SWITCH_RESV_2 [31:18] */
-#define BCHP_SWITCH_CORE_COMM_IRC_CON_SWITCH_RESV_2_MASK 0xfffc0000
-#define BCHP_SWITCH_CORE_COMM_IRC_CON_SWITCH_RESV_2_SHIFT 18
-#define BCHP_SWITCH_CORE_COMM_IRC_CON_SWITCH_RESV_2_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: COMM_IRC_CON :: RATE_TYPE1 [17:17] */
-#define BCHP_SWITCH_CORE_COMM_IRC_CON_RATE_TYPE1_MASK 0x00020000
-#define BCHP_SWITCH_CORE_COMM_IRC_CON_RATE_TYPE1_SHIFT 17
-#define BCHP_SWITCH_CORE_COMM_IRC_CON_RATE_TYPE1_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: COMM_IRC_CON :: SWITCH_RESV_1 [16:09] */
-#define BCHP_SWITCH_CORE_COMM_IRC_CON_SWITCH_RESV_1_MASK 0x0001fe00
-#define BCHP_SWITCH_CORE_COMM_IRC_CON_SWITCH_RESV_1_SHIFT 9
-#define BCHP_SWITCH_CORE_COMM_IRC_CON_SWITCH_RESV_1_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: COMM_IRC_CON :: RATE_TYPE0 [08:08] */
-#define BCHP_SWITCH_CORE_COMM_IRC_CON_RATE_TYPE0_MASK 0x00000100
-#define BCHP_SWITCH_CORE_COMM_IRC_CON_RATE_TYPE0_SHIFT 8
-#define BCHP_SWITCH_CORE_COMM_IRC_CON_RATE_TYPE0_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: COMM_IRC_CON :: SWITCH_RESV_0 [07:00] */
-#define BCHP_SWITCH_CORE_COMM_IRC_CON_SWITCH_RESV_0_MASK 0x000000ff
-#define BCHP_SWITCH_CORE_COMM_IRC_CON_SWITCH_RESV_0_SHIFT 0
-#define BCHP_SWITCH_CORE_COMM_IRC_CON_SWITCH_RESV_0_DEFAULT 0x00000000
-
-/***************************************************************************
- *IRC_VIRTUAL_ZERO_THD - Ingress Rate Control Virtual Zero Threshold Register (Not2Release)
- ***************************************************************************/
-/* SWITCH_CORE :: IRC_VIRTUAL_ZERO_THD :: reserved_for_padding0 [31:16] */
-#define BCHP_SWITCH_CORE_IRC_VIRTUAL_ZERO_THD_reserved_for_padding0_MASK 0xffff0000
-#define BCHP_SWITCH_CORE_IRC_VIRTUAL_ZERO_THD_reserved_for_padding0_SHIFT 16
-
-/* SWITCH_CORE :: IRC_VIRTUAL_ZERO_THD :: IRC_VIRTUAL_ZERO_THD [15:00] */
-#define BCHP_SWITCH_CORE_IRC_VIRTUAL_ZERO_THD_IRC_VIRTUAL_ZERO_THD_MASK 0x0000ffff
-#define BCHP_SWITCH_CORE_IRC_VIRTUAL_ZERO_THD_IRC_VIRTUAL_ZERO_THD_SHIFT 0
-#define BCHP_SWITCH_CORE_IRC_VIRTUAL_ZERO_THD_IRC_VIRTUAL_ZERO_THD_DEFAULT 0x00002fff
-
-/***************************************************************************
- *IRC_ALARM_THD - Ingress Rate Control Alarm Threshold Register (Not2Release)
- ***************************************************************************/
-/* SWITCH_CORE :: IRC_ALARM_THD :: reserved_for_padding0 [31:16] */
-#define BCHP_SWITCH_CORE_IRC_ALARM_THD_reserved_for_padding0_MASK 0xffff0000
-#define BCHP_SWITCH_CORE_IRC_ALARM_THD_reserved_for_padding0_SHIFT 16
-
-/* SWITCH_CORE :: IRC_ALARM_THD :: IRC_ALARM_THD [15:00] */
-#define BCHP_SWITCH_CORE_IRC_ALARM_THD_IRC_ALARM_THD_MASK 0x0000ffff
-#define BCHP_SWITCH_CORE_IRC_ALARM_THD_IRC_ALARM_THD_SHIFT 0
-#define BCHP_SWITCH_CORE_IRC_ALARM_THD_IRC_ALARM_THD_DEFAULT 0x00000bff
-
-/***************************************************************************
- *BC_SUP_RATECTRL_P_Port_0 - Port N Receive Rate Control Registers
- ***************************************************************************/
-/* SWITCH_CORE :: BC_SUP_RATECTRL_P_Port_0 :: SWITCH_RESV_1 [31:31] */
-#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P_Port_0_SWITCH_RESV_1_MASK 0x80000000
-#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P_Port_0_SWITCH_RESV_1_SHIFT 31
-#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P_Port_0_SWITCH_RESV_1_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: BC_SUP_RATECTRL_P_Port_0 :: BUCKET_MODE1 [30:30] */
-#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P_Port_0_BUCKET_MODE1_MASK 0x40000000
-#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P_Port_0_BUCKET_MODE1_SHIFT 30
-#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P_Port_0_BUCKET_MODE1_DEFAULT 0x00000001
-
-/* SWITCH_CORE :: BC_SUP_RATECTRL_P_Port_0 :: BUCKET_MODE0 [29:29] */
-#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P_Port_0_BUCKET_MODE0_MASK 0x20000000
-#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P_Port_0_BUCKET_MODE0_SHIFT 29
-#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P_Port_0_BUCKET_MODE0_DEFAULT 0x00000001
-
-/* SWITCH_CORE :: BC_SUP_RATECTRL_P_Port_0 :: SWITCH_RESV_0 [28:24] */
-#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P_Port_0_SWITCH_RESV_0_MASK 0x1f000000
-#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P_Port_0_SWITCH_RESV_0_SHIFT 24
-#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P_Port_0_SWITCH_RESV_0_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: BC_SUP_RATECTRL_P_Port_0 :: EN_BUCKET1 [23:23] */
-#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P_Port_0_EN_BUCKET1_MASK 0x00800000
-#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P_Port_0_EN_BUCKET1_SHIFT 23
-#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P_Port_0_EN_BUCKET1_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: BC_SUP_RATECTRL_P_Port_0 :: EN_BUCKET0 [22:22] */
-#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P_Port_0_EN_BUCKET0_MASK 0x00400000
-#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P_Port_0_EN_BUCKET0_SHIFT 22
-#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P_Port_0_EN_BUCKET0_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: BC_SUP_RATECTRL_P_Port_0 :: BUCKET1_SIZE [21:19] */
-#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P_Port_0_BUCKET1_SIZE_MASK 0x00380000
-#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P_Port_0_BUCKET1_SIZE_SHIFT 19
-#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P_Port_0_BUCKET1_SIZE_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: BC_SUP_RATECTRL_P_Port_0 :: BUCKET1_REF_CNT [18:11] */
-#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P_Port_0_BUCKET1_REF_CNT_MASK 0x0007f800
-#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P_Port_0_BUCKET1_REF_CNT_SHIFT 11
-#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P_Port_0_BUCKET1_REF_CNT_DEFAULT 0x00000010
-
-/* SWITCH_CORE :: BC_SUP_RATECTRL_P_Port_0 :: BUCKET0_SIZE [10:08] */
-#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P_Port_0_BUCKET0_SIZE_MASK 0x00000700
-#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P_Port_0_BUCKET0_SIZE_SHIFT 8
-#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P_Port_0_BUCKET0_SIZE_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: BC_SUP_RATECTRL_P_Port_0 :: BUCKET0_REF_CNT [07:00] */
-#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P_Port_0_BUCKET0_REF_CNT_MASK 0x000000ff
-#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P_Port_0_BUCKET0_REF_CNT_SHIFT 0
-#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P_Port_0_BUCKET0_REF_CNT_DEFAULT 0x00000010
-
-/***************************************************************************
- *BC_SUP_RATECTRL_P_Port_1 - Port N Receive Rate Control Registers
- ***************************************************************************/
-/* SWITCH_CORE :: BC_SUP_RATECTRL_P_Port_1 :: SWITCH_RESV_1 [31:31] */
-#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P_Port_1_SWITCH_RESV_1_MASK 0x80000000
-#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P_Port_1_SWITCH_RESV_1_SHIFT 31
-#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P_Port_1_SWITCH_RESV_1_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: BC_SUP_RATECTRL_P_Port_1 :: BUCKET_MODE1 [30:30] */
-#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P_Port_1_BUCKET_MODE1_MASK 0x40000000
-#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P_Port_1_BUCKET_MODE1_SHIFT 30
-#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P_Port_1_BUCKET_MODE1_DEFAULT 0x00000001
-
-/* SWITCH_CORE :: BC_SUP_RATECTRL_P_Port_1 :: BUCKET_MODE0 [29:29] */
-#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P_Port_1_BUCKET_MODE0_MASK 0x20000000
-#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P_Port_1_BUCKET_MODE0_SHIFT 29
-#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P_Port_1_BUCKET_MODE0_DEFAULT 0x00000001
-
-/* SWITCH_CORE :: BC_SUP_RATECTRL_P_Port_1 :: SWITCH_RESV_0 [28:24] */
-#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P_Port_1_SWITCH_RESV_0_MASK 0x1f000000
-#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P_Port_1_SWITCH_RESV_0_SHIFT 24
-#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P_Port_1_SWITCH_RESV_0_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: BC_SUP_RATECTRL_P_Port_1 :: EN_BUCKET1 [23:23] */
-#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P_Port_1_EN_BUCKET1_MASK 0x00800000
-#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P_Port_1_EN_BUCKET1_SHIFT 23
-#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P_Port_1_EN_BUCKET1_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: BC_SUP_RATECTRL_P_Port_1 :: EN_BUCKET0 [22:22] */
-#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P_Port_1_EN_BUCKET0_MASK 0x00400000
-#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P_Port_1_EN_BUCKET0_SHIFT 22
-#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P_Port_1_EN_BUCKET0_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: BC_SUP_RATECTRL_P_Port_1 :: BUCKET1_SIZE [21:19] */
-#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P_Port_1_BUCKET1_SIZE_MASK 0x00380000
-#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P_Port_1_BUCKET1_SIZE_SHIFT 19
-#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P_Port_1_BUCKET1_SIZE_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: BC_SUP_RATECTRL_P_Port_1 :: BUCKET1_REF_CNT [18:11] */
-#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P_Port_1_BUCKET1_REF_CNT_MASK 0x0007f800
-#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P_Port_1_BUCKET1_REF_CNT_SHIFT 11
-#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P_Port_1_BUCKET1_REF_CNT_DEFAULT 0x00000010
-
-/* SWITCH_CORE :: BC_SUP_RATECTRL_P_Port_1 :: BUCKET0_SIZE [10:08] */
-#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P_Port_1_BUCKET0_SIZE_MASK 0x00000700
-#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P_Port_1_BUCKET0_SIZE_SHIFT 8
-#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P_Port_1_BUCKET0_SIZE_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: BC_SUP_RATECTRL_P_Port_1 :: BUCKET0_REF_CNT [07:00] */
-#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P_Port_1_BUCKET0_REF_CNT_MASK 0x000000ff
-#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P_Port_1_BUCKET0_REF_CNT_SHIFT 0
-#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P_Port_1_BUCKET0_REF_CNT_DEFAULT 0x00000010
-
-/***************************************************************************
- *BC_SUP_RATECTRL_P_Port_2 - Port N Receive Rate Control Registers
- ***************************************************************************/
-/* SWITCH_CORE :: BC_SUP_RATECTRL_P_Port_2 :: SWITCH_RESV_1 [31:31] */
-#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P_Port_2_SWITCH_RESV_1_MASK 0x80000000
-#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P_Port_2_SWITCH_RESV_1_SHIFT 31
-#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P_Port_2_SWITCH_RESV_1_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: BC_SUP_RATECTRL_P_Port_2 :: BUCKET_MODE1 [30:30] */
-#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P_Port_2_BUCKET_MODE1_MASK 0x40000000
-#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P_Port_2_BUCKET_MODE1_SHIFT 30
-#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P_Port_2_BUCKET_MODE1_DEFAULT 0x00000001
-
-/* SWITCH_CORE :: BC_SUP_RATECTRL_P_Port_2 :: BUCKET_MODE0 [29:29] */
-#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P_Port_2_BUCKET_MODE0_MASK 0x20000000
-#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P_Port_2_BUCKET_MODE0_SHIFT 29
-#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P_Port_2_BUCKET_MODE0_DEFAULT 0x00000001
-
-/* SWITCH_CORE :: BC_SUP_RATECTRL_P_Port_2 :: SWITCH_RESV_0 [28:24] */
-#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P_Port_2_SWITCH_RESV_0_MASK 0x1f000000
-#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P_Port_2_SWITCH_RESV_0_SHIFT 24
-#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P_Port_2_SWITCH_RESV_0_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: BC_SUP_RATECTRL_P_Port_2 :: EN_BUCKET1 [23:23] */
-#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P_Port_2_EN_BUCKET1_MASK 0x00800000
-#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P_Port_2_EN_BUCKET1_SHIFT 23
-#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P_Port_2_EN_BUCKET1_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: BC_SUP_RATECTRL_P_Port_2 :: EN_BUCKET0 [22:22] */
-#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P_Port_2_EN_BUCKET0_MASK 0x00400000
-#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P_Port_2_EN_BUCKET0_SHIFT 22
-#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P_Port_2_EN_BUCKET0_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: BC_SUP_RATECTRL_P_Port_2 :: BUCKET1_SIZE [21:19] */
-#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P_Port_2_BUCKET1_SIZE_MASK 0x00380000
-#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P_Port_2_BUCKET1_SIZE_SHIFT 19
-#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P_Port_2_BUCKET1_SIZE_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: BC_SUP_RATECTRL_P_Port_2 :: BUCKET1_REF_CNT [18:11] */
-#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P_Port_2_BUCKET1_REF_CNT_MASK 0x0007f800
-#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P_Port_2_BUCKET1_REF_CNT_SHIFT 11
-#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P_Port_2_BUCKET1_REF_CNT_DEFAULT 0x00000010
-
-/* SWITCH_CORE :: BC_SUP_RATECTRL_P_Port_2 :: BUCKET0_SIZE [10:08] */
-#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P_Port_2_BUCKET0_SIZE_MASK 0x00000700
-#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P_Port_2_BUCKET0_SIZE_SHIFT 8
-#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P_Port_2_BUCKET0_SIZE_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: BC_SUP_RATECTRL_P_Port_2 :: BUCKET0_REF_CNT [07:00] */
-#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P_Port_2_BUCKET0_REF_CNT_MASK 0x000000ff
-#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P_Port_2_BUCKET0_REF_CNT_SHIFT 0
-#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P_Port_2_BUCKET0_REF_CNT_DEFAULT 0x00000010
-
-/***************************************************************************
- *BC_SUP_RATECTRL_P_Port_3 - Port N Receive Rate Control Registers
- ***************************************************************************/
-/* SWITCH_CORE :: BC_SUP_RATECTRL_P_Port_3 :: SWITCH_RESV_1 [31:31] */
-#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P_Port_3_SWITCH_RESV_1_MASK 0x80000000
-#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P_Port_3_SWITCH_RESV_1_SHIFT 31
-#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P_Port_3_SWITCH_RESV_1_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: BC_SUP_RATECTRL_P_Port_3 :: BUCKET_MODE1 [30:30] */
-#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P_Port_3_BUCKET_MODE1_MASK 0x40000000
-#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P_Port_3_BUCKET_MODE1_SHIFT 30
-#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P_Port_3_BUCKET_MODE1_DEFAULT 0x00000001
-
-/* SWITCH_CORE :: BC_SUP_RATECTRL_P_Port_3 :: BUCKET_MODE0 [29:29] */
-#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P_Port_3_BUCKET_MODE0_MASK 0x20000000
-#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P_Port_3_BUCKET_MODE0_SHIFT 29
-#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P_Port_3_BUCKET_MODE0_DEFAULT 0x00000001
-
-/* SWITCH_CORE :: BC_SUP_RATECTRL_P_Port_3 :: SWITCH_RESV_0 [28:24] */
-#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P_Port_3_SWITCH_RESV_0_MASK 0x1f000000
-#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P_Port_3_SWITCH_RESV_0_SHIFT 24
-#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P_Port_3_SWITCH_RESV_0_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: BC_SUP_RATECTRL_P_Port_3 :: EN_BUCKET1 [23:23] */
-#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P_Port_3_EN_BUCKET1_MASK 0x00800000
-#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P_Port_3_EN_BUCKET1_SHIFT 23
-#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P_Port_3_EN_BUCKET1_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: BC_SUP_RATECTRL_P_Port_3 :: EN_BUCKET0 [22:22] */
-#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P_Port_3_EN_BUCKET0_MASK 0x00400000
-#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P_Port_3_EN_BUCKET0_SHIFT 22
-#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P_Port_3_EN_BUCKET0_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: BC_SUP_RATECTRL_P_Port_3 :: BUCKET1_SIZE [21:19] */
-#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P_Port_3_BUCKET1_SIZE_MASK 0x00380000
-#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P_Port_3_BUCKET1_SIZE_SHIFT 19
-#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P_Port_3_BUCKET1_SIZE_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: BC_SUP_RATECTRL_P_Port_3 :: BUCKET1_REF_CNT [18:11] */
-#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P_Port_3_BUCKET1_REF_CNT_MASK 0x0007f800
-#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P_Port_3_BUCKET1_REF_CNT_SHIFT 11
-#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P_Port_3_BUCKET1_REF_CNT_DEFAULT 0x00000010
-
-/* SWITCH_CORE :: BC_SUP_RATECTRL_P_Port_3 :: BUCKET0_SIZE [10:08] */
-#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P_Port_3_BUCKET0_SIZE_MASK 0x00000700
-#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P_Port_3_BUCKET0_SIZE_SHIFT 8
-#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P_Port_3_BUCKET0_SIZE_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: BC_SUP_RATECTRL_P_Port_3 :: BUCKET0_REF_CNT [07:00] */
-#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P_Port_3_BUCKET0_REF_CNT_MASK 0x000000ff
-#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P_Port_3_BUCKET0_REF_CNT_SHIFT 0
-#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P_Port_3_BUCKET0_REF_CNT_DEFAULT 0x00000010
-
-/***************************************************************************
- *BC_SUP_RATECTRL_P_Port_4 - Port N Receive Rate Control Registers
- ***************************************************************************/
-/* SWITCH_CORE :: BC_SUP_RATECTRL_P_Port_4 :: SWITCH_RESV_1 [31:31] */
-#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P_Port_4_SWITCH_RESV_1_MASK 0x80000000
-#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P_Port_4_SWITCH_RESV_1_SHIFT 31
-#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P_Port_4_SWITCH_RESV_1_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: BC_SUP_RATECTRL_P_Port_4 :: BUCKET_MODE1 [30:30] */
-#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P_Port_4_BUCKET_MODE1_MASK 0x40000000
-#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P_Port_4_BUCKET_MODE1_SHIFT 30
-#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P_Port_4_BUCKET_MODE1_DEFAULT 0x00000001
-
-/* SWITCH_CORE :: BC_SUP_RATECTRL_P_Port_4 :: BUCKET_MODE0 [29:29] */
-#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P_Port_4_BUCKET_MODE0_MASK 0x20000000
-#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P_Port_4_BUCKET_MODE0_SHIFT 29
-#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P_Port_4_BUCKET_MODE0_DEFAULT 0x00000001
-
-/* SWITCH_CORE :: BC_SUP_RATECTRL_P_Port_4 :: SWITCH_RESV_0 [28:24] */
-#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P_Port_4_SWITCH_RESV_0_MASK 0x1f000000
-#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P_Port_4_SWITCH_RESV_0_SHIFT 24
-#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P_Port_4_SWITCH_RESV_0_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: BC_SUP_RATECTRL_P_Port_4 :: EN_BUCKET1 [23:23] */
-#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P_Port_4_EN_BUCKET1_MASK 0x00800000
-#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P_Port_4_EN_BUCKET1_SHIFT 23
-#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P_Port_4_EN_BUCKET1_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: BC_SUP_RATECTRL_P_Port_4 :: EN_BUCKET0 [22:22] */
-#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P_Port_4_EN_BUCKET0_MASK 0x00400000
-#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P_Port_4_EN_BUCKET0_SHIFT 22
-#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P_Port_4_EN_BUCKET0_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: BC_SUP_RATECTRL_P_Port_4 :: BUCKET1_SIZE [21:19] */
-#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P_Port_4_BUCKET1_SIZE_MASK 0x00380000
-#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P_Port_4_BUCKET1_SIZE_SHIFT 19
-#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P_Port_4_BUCKET1_SIZE_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: BC_SUP_RATECTRL_P_Port_4 :: BUCKET1_REF_CNT [18:11] */
-#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P_Port_4_BUCKET1_REF_CNT_MASK 0x0007f800
-#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P_Port_4_BUCKET1_REF_CNT_SHIFT 11
-#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P_Port_4_BUCKET1_REF_CNT_DEFAULT 0x00000010
-
-/* SWITCH_CORE :: BC_SUP_RATECTRL_P_Port_4 :: BUCKET0_SIZE [10:08] */
-#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P_Port_4_BUCKET0_SIZE_MASK 0x00000700
-#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P_Port_4_BUCKET0_SIZE_SHIFT 8
-#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P_Port_4_BUCKET0_SIZE_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: BC_SUP_RATECTRL_P_Port_4 :: BUCKET0_REF_CNT [07:00] */
-#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P_Port_4_BUCKET0_REF_CNT_MASK 0x000000ff
-#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P_Port_4_BUCKET0_REF_CNT_SHIFT 0
-#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P_Port_4_BUCKET0_REF_CNT_DEFAULT 0x00000010
-
-/***************************************************************************
- *BC_SUP_RATECTRL_P_Port_5 - Port N Receive Rate Control Registers
- ***************************************************************************/
-/* SWITCH_CORE :: BC_SUP_RATECTRL_P_Port_5 :: SWITCH_RESV_1 [31:31] */
-#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P_Port_5_SWITCH_RESV_1_MASK 0x80000000
-#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P_Port_5_SWITCH_RESV_1_SHIFT 31
-#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P_Port_5_SWITCH_RESV_1_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: BC_SUP_RATECTRL_P_Port_5 :: BUCKET_MODE1 [30:30] */
-#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P_Port_5_BUCKET_MODE1_MASK 0x40000000
-#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P_Port_5_BUCKET_MODE1_SHIFT 30
-#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P_Port_5_BUCKET_MODE1_DEFAULT 0x00000001
-
-/* SWITCH_CORE :: BC_SUP_RATECTRL_P_Port_5 :: BUCKET_MODE0 [29:29] */
-#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P_Port_5_BUCKET_MODE0_MASK 0x20000000
-#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P_Port_5_BUCKET_MODE0_SHIFT 29
-#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P_Port_5_BUCKET_MODE0_DEFAULT 0x00000001
-
-/* SWITCH_CORE :: BC_SUP_RATECTRL_P_Port_5 :: SWITCH_RESV_0 [28:24] */
-#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P_Port_5_SWITCH_RESV_0_MASK 0x1f000000
-#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P_Port_5_SWITCH_RESV_0_SHIFT 24
-#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P_Port_5_SWITCH_RESV_0_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: BC_SUP_RATECTRL_P_Port_5 :: EN_BUCKET1 [23:23] */
-#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P_Port_5_EN_BUCKET1_MASK 0x00800000
-#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P_Port_5_EN_BUCKET1_SHIFT 23
-#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P_Port_5_EN_BUCKET1_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: BC_SUP_RATECTRL_P_Port_5 :: EN_BUCKET0 [22:22] */
-#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P_Port_5_EN_BUCKET0_MASK 0x00400000
-#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P_Port_5_EN_BUCKET0_SHIFT 22
-#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P_Port_5_EN_BUCKET0_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: BC_SUP_RATECTRL_P_Port_5 :: BUCKET1_SIZE [21:19] */
-#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P_Port_5_BUCKET1_SIZE_MASK 0x00380000
-#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P_Port_5_BUCKET1_SIZE_SHIFT 19
-#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P_Port_5_BUCKET1_SIZE_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: BC_SUP_RATECTRL_P_Port_5 :: BUCKET1_REF_CNT [18:11] */
-#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P_Port_5_BUCKET1_REF_CNT_MASK 0x0007f800
-#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P_Port_5_BUCKET1_REF_CNT_SHIFT 11
-#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P_Port_5_BUCKET1_REF_CNT_DEFAULT 0x00000010
-
-/* SWITCH_CORE :: BC_SUP_RATECTRL_P_Port_5 :: BUCKET0_SIZE [10:08] */
-#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P_Port_5_BUCKET0_SIZE_MASK 0x00000700
-#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P_Port_5_BUCKET0_SIZE_SHIFT 8
-#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P_Port_5_BUCKET0_SIZE_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: BC_SUP_RATECTRL_P_Port_5 :: BUCKET0_REF_CNT [07:00] */
-#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P_Port_5_BUCKET0_REF_CNT_MASK 0x000000ff
-#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P_Port_5_BUCKET0_REF_CNT_SHIFT 0
-#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P_Port_5_BUCKET0_REF_CNT_DEFAULT 0x00000010
-
-/***************************************************************************
- *BC_SUP_RATECTRL_P7 - Port 7 Receive Rate Control Registers
- ***************************************************************************/
-/* SWITCH_CORE :: BC_SUP_RATECTRL_P7 :: SWITCH_RESV_1 [31:31] */
-#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P7_SWITCH_RESV_1_MASK 0x80000000
-#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P7_SWITCH_RESV_1_SHIFT 31
-#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P7_SWITCH_RESV_1_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: BC_SUP_RATECTRL_P7 :: BUCKET_MODE1 [30:30] */
-#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P7_BUCKET_MODE1_MASK 0x40000000
-#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P7_BUCKET_MODE1_SHIFT 30
-#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P7_BUCKET_MODE1_DEFAULT 0x00000001
-
-/* SWITCH_CORE :: BC_SUP_RATECTRL_P7 :: BUCKET_MODE0 [29:29] */
-#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P7_BUCKET_MODE0_MASK 0x20000000
-#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P7_BUCKET_MODE0_SHIFT 29
-#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P7_BUCKET_MODE0_DEFAULT 0x00000001
-
-/* SWITCH_CORE :: BC_SUP_RATECTRL_P7 :: SWITCH_RESV_0 [28:24] */
-#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P7_SWITCH_RESV_0_MASK 0x1f000000
-#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P7_SWITCH_RESV_0_SHIFT 24
-#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P7_SWITCH_RESV_0_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: BC_SUP_RATECTRL_P7 :: EN_BUCKET1 [23:23] */
-#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P7_EN_BUCKET1_MASK 0x00800000
-#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P7_EN_BUCKET1_SHIFT 23
-#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P7_EN_BUCKET1_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: BC_SUP_RATECTRL_P7 :: EN_BUCKET0 [22:22] */
-#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P7_EN_BUCKET0_MASK 0x00400000
-#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P7_EN_BUCKET0_SHIFT 22
-#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P7_EN_BUCKET0_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: BC_SUP_RATECTRL_P7 :: BUCKET1_SIZE [21:19] */
-#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P7_BUCKET1_SIZE_MASK 0x00380000
-#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P7_BUCKET1_SIZE_SHIFT 19
-#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P7_BUCKET1_SIZE_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: BC_SUP_RATECTRL_P7 :: BUCKET1_REF_CNT [18:11] */
-#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P7_BUCKET1_REF_CNT_MASK 0x0007f800
-#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P7_BUCKET1_REF_CNT_SHIFT 11
-#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P7_BUCKET1_REF_CNT_DEFAULT 0x00000010
-
-/* SWITCH_CORE :: BC_SUP_RATECTRL_P7 :: BUCKET0_SIZE [10:08] */
-#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P7_BUCKET0_SIZE_MASK 0x00000700
-#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P7_BUCKET0_SIZE_SHIFT 8
-#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P7_BUCKET0_SIZE_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: BC_SUP_RATECTRL_P7 :: BUCKET0_REF_CNT [07:00] */
-#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P7_BUCKET0_REF_CNT_MASK 0x000000ff
-#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P7_BUCKET0_REF_CNT_SHIFT 0
-#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P7_BUCKET0_REF_CNT_DEFAULT 0x00000010
-
-/***************************************************************************
- *BC_SUP_RATECTRL_IMP - Port 8 Receive Rate Control Registers
- ***************************************************************************/
-/* SWITCH_CORE :: BC_SUP_RATECTRL_IMP :: SWITCH_RESV_1 [31:31] */
-#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_IMP_SWITCH_RESV_1_MASK 0x80000000
-#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_IMP_SWITCH_RESV_1_SHIFT 31
-#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_IMP_SWITCH_RESV_1_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: BC_SUP_RATECTRL_IMP :: BUCKET_MODE1 [30:30] */
-#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_IMP_BUCKET_MODE1_MASK 0x40000000
-#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_IMP_BUCKET_MODE1_SHIFT 30
-#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_IMP_BUCKET_MODE1_DEFAULT 0x00000001
-
-/* SWITCH_CORE :: BC_SUP_RATECTRL_IMP :: BUCKET_MODE0 [29:29] */
-#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_IMP_BUCKET_MODE0_MASK 0x20000000
-#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_IMP_BUCKET_MODE0_SHIFT 29
-#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_IMP_BUCKET_MODE0_DEFAULT 0x00000001
-
-/* SWITCH_CORE :: BC_SUP_RATECTRL_IMP :: SWITCH_RESV_0 [28:24] */
-#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_IMP_SWITCH_RESV_0_MASK 0x1f000000
-#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_IMP_SWITCH_RESV_0_SHIFT 24
-#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_IMP_SWITCH_RESV_0_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: BC_SUP_RATECTRL_IMP :: EN_BUCKET1 [23:23] */
-#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_IMP_EN_BUCKET1_MASK 0x00800000
-#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_IMP_EN_BUCKET1_SHIFT 23
-#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_IMP_EN_BUCKET1_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: BC_SUP_RATECTRL_IMP :: EN_BUCKET0 [22:22] */
-#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_IMP_EN_BUCKET0_MASK 0x00400000
-#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_IMP_EN_BUCKET0_SHIFT 22
-#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_IMP_EN_BUCKET0_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: BC_SUP_RATECTRL_IMP :: BUCKET1_SIZE [21:19] */
-#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_IMP_BUCKET1_SIZE_MASK 0x00380000
-#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_IMP_BUCKET1_SIZE_SHIFT 19
-#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_IMP_BUCKET1_SIZE_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: BC_SUP_RATECTRL_IMP :: BUCKET1_REF_CNT [18:11] */
-#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_IMP_BUCKET1_REF_CNT_MASK 0x0007f800
-#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_IMP_BUCKET1_REF_CNT_SHIFT 11
-#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_IMP_BUCKET1_REF_CNT_DEFAULT 0x00000010
-
-/* SWITCH_CORE :: BC_SUP_RATECTRL_IMP :: BUCKET0_SIZE [10:08] */
-#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_IMP_BUCKET0_SIZE_MASK 0x00000700
-#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_IMP_BUCKET0_SIZE_SHIFT 8
-#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_IMP_BUCKET0_SIZE_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: BC_SUP_RATECTRL_IMP :: BUCKET0_REF_CNT [07:00] */
-#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_IMP_BUCKET0_REF_CNT_MASK 0x000000ff
-#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_IMP_BUCKET0_REF_CNT_SHIFT 0
-#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_IMP_BUCKET0_REF_CNT_DEFAULT 0x00000010
-
-/***************************************************************************
- *BC_SUP_RATECTRL_1_P_Port_0 - Port N Receive Rate Control 1 Registers
- ***************************************************************************/
-/* SWITCH_CORE :: BC_SUP_RATECTRL_1_P_Port_0 :: reserved_for_padding0 [31:16] */
-#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_1_P_Port_0_reserved_for_padding0_MASK 0xffff0000
-#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_1_P_Port_0_reserved_for_padding0_SHIFT 16
-
-/* SWITCH_CORE :: BC_SUP_RATECTRL_1_P_Port_0 :: IFG_BYTES1 [15:15] */
-#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_1_P_Port_0_IFG_BYTES1_MASK 0x00008000
-#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_1_P_Port_0_IFG_BYTES1_SHIFT 15
-#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_1_P_Port_0_IFG_BYTES1_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: BC_SUP_RATECTRL_1_P_Port_0 :: PKT_MSK1 [14:08] */
-#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_1_P_Port_0_PKT_MSK1_MASK 0x00007f00
-#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_1_P_Port_0_PKT_MSK1_SHIFT 8
-#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_1_P_Port_0_PKT_MSK1_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: BC_SUP_RATECTRL_1_P_Port_0 :: IFG_BYTES0 [07:07] */
-#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_1_P_Port_0_IFG_BYTES0_MASK 0x00000080
-#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_1_P_Port_0_IFG_BYTES0_SHIFT 7
-#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_1_P_Port_0_IFG_BYTES0_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: BC_SUP_RATECTRL_1_P_Port_0 :: PKT_MSK0 [06:00] */
-#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_1_P_Port_0_PKT_MSK0_MASK 0x0000007f
-#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_1_P_Port_0_PKT_MSK0_SHIFT 0
-#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_1_P_Port_0_PKT_MSK0_DEFAULT 0x00000000
-
-/***************************************************************************
- *BC_SUP_RATECTRL_1_P_Port_1 - Port N Receive Rate Control 1 Registers
- ***************************************************************************/
-/* SWITCH_CORE :: BC_SUP_RATECTRL_1_P_Port_1 :: reserved_for_padding0 [31:16] */
-#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_1_P_Port_1_reserved_for_padding0_MASK 0xffff0000
-#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_1_P_Port_1_reserved_for_padding0_SHIFT 16
-
-/* SWITCH_CORE :: BC_SUP_RATECTRL_1_P_Port_1 :: IFG_BYTES1 [15:15] */
-#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_1_P_Port_1_IFG_BYTES1_MASK 0x00008000
-#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_1_P_Port_1_IFG_BYTES1_SHIFT 15
-#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_1_P_Port_1_IFG_BYTES1_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: BC_SUP_RATECTRL_1_P_Port_1 :: PKT_MSK1 [14:08] */
-#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_1_P_Port_1_PKT_MSK1_MASK 0x00007f00
-#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_1_P_Port_1_PKT_MSK1_SHIFT 8
-#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_1_P_Port_1_PKT_MSK1_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: BC_SUP_RATECTRL_1_P_Port_1 :: IFG_BYTES0 [07:07] */
-#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_1_P_Port_1_IFG_BYTES0_MASK 0x00000080
-#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_1_P_Port_1_IFG_BYTES0_SHIFT 7
-#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_1_P_Port_1_IFG_BYTES0_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: BC_SUP_RATECTRL_1_P_Port_1 :: PKT_MSK0 [06:00] */
-#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_1_P_Port_1_PKT_MSK0_MASK 0x0000007f
-#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_1_P_Port_1_PKT_MSK0_SHIFT 0
-#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_1_P_Port_1_PKT_MSK0_DEFAULT 0x00000000
-
-/***************************************************************************
- *BC_SUP_RATECTRL_1_P_Port_2 - Port N Receive Rate Control 1 Registers
- ***************************************************************************/
-/* SWITCH_CORE :: BC_SUP_RATECTRL_1_P_Port_2 :: reserved_for_padding0 [31:16] */
-#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_1_P_Port_2_reserved_for_padding0_MASK 0xffff0000
-#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_1_P_Port_2_reserved_for_padding0_SHIFT 16
-
-/* SWITCH_CORE :: BC_SUP_RATECTRL_1_P_Port_2 :: IFG_BYTES1 [15:15] */
-#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_1_P_Port_2_IFG_BYTES1_MASK 0x00008000
-#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_1_P_Port_2_IFG_BYTES1_SHIFT 15
-#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_1_P_Port_2_IFG_BYTES1_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: BC_SUP_RATECTRL_1_P_Port_2 :: PKT_MSK1 [14:08] */
-#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_1_P_Port_2_PKT_MSK1_MASK 0x00007f00
-#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_1_P_Port_2_PKT_MSK1_SHIFT 8
-#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_1_P_Port_2_PKT_MSK1_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: BC_SUP_RATECTRL_1_P_Port_2 :: IFG_BYTES0 [07:07] */
-#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_1_P_Port_2_IFG_BYTES0_MASK 0x00000080
-#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_1_P_Port_2_IFG_BYTES0_SHIFT 7
-#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_1_P_Port_2_IFG_BYTES0_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: BC_SUP_RATECTRL_1_P_Port_2 :: PKT_MSK0 [06:00] */
-#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_1_P_Port_2_PKT_MSK0_MASK 0x0000007f
-#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_1_P_Port_2_PKT_MSK0_SHIFT 0
-#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_1_P_Port_2_PKT_MSK0_DEFAULT 0x00000000
-
-/***************************************************************************
- *BC_SUP_RATECTRL_1_P_Port_3 - Port N Receive Rate Control 1 Registers
- ***************************************************************************/
-/* SWITCH_CORE :: BC_SUP_RATECTRL_1_P_Port_3 :: reserved_for_padding0 [31:16] */
-#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_1_P_Port_3_reserved_for_padding0_MASK 0xffff0000
-#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_1_P_Port_3_reserved_for_padding0_SHIFT 16
-
-/* SWITCH_CORE :: BC_SUP_RATECTRL_1_P_Port_3 :: IFG_BYTES1 [15:15] */
-#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_1_P_Port_3_IFG_BYTES1_MASK 0x00008000
-#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_1_P_Port_3_IFG_BYTES1_SHIFT 15
-#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_1_P_Port_3_IFG_BYTES1_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: BC_SUP_RATECTRL_1_P_Port_3 :: PKT_MSK1 [14:08] */
-#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_1_P_Port_3_PKT_MSK1_MASK 0x00007f00
-#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_1_P_Port_3_PKT_MSK1_SHIFT 8
-#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_1_P_Port_3_PKT_MSK1_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: BC_SUP_RATECTRL_1_P_Port_3 :: IFG_BYTES0 [07:07] */
-#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_1_P_Port_3_IFG_BYTES0_MASK 0x00000080
-#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_1_P_Port_3_IFG_BYTES0_SHIFT 7
-#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_1_P_Port_3_IFG_BYTES0_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: BC_SUP_RATECTRL_1_P_Port_3 :: PKT_MSK0 [06:00] */
-#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_1_P_Port_3_PKT_MSK0_MASK 0x0000007f
-#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_1_P_Port_3_PKT_MSK0_SHIFT 0
-#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_1_P_Port_3_PKT_MSK0_DEFAULT 0x00000000
-
-/***************************************************************************
- *BC_SUP_RATECTRL_1_P_Port_4 - Port N Receive Rate Control 1 Registers
- ***************************************************************************/
-/* SWITCH_CORE :: BC_SUP_RATECTRL_1_P_Port_4 :: reserved_for_padding0 [31:16] */
-#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_1_P_Port_4_reserved_for_padding0_MASK 0xffff0000
-#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_1_P_Port_4_reserved_for_padding0_SHIFT 16
-
-/* SWITCH_CORE :: BC_SUP_RATECTRL_1_P_Port_4 :: IFG_BYTES1 [15:15] */
-#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_1_P_Port_4_IFG_BYTES1_MASK 0x00008000
-#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_1_P_Port_4_IFG_BYTES1_SHIFT 15
-#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_1_P_Port_4_IFG_BYTES1_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: BC_SUP_RATECTRL_1_P_Port_4 :: PKT_MSK1 [14:08] */
-#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_1_P_Port_4_PKT_MSK1_MASK 0x00007f00
-#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_1_P_Port_4_PKT_MSK1_SHIFT 8
-#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_1_P_Port_4_PKT_MSK1_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: BC_SUP_RATECTRL_1_P_Port_4 :: IFG_BYTES0 [07:07] */
-#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_1_P_Port_4_IFG_BYTES0_MASK 0x00000080
-#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_1_P_Port_4_IFG_BYTES0_SHIFT 7
-#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_1_P_Port_4_IFG_BYTES0_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: BC_SUP_RATECTRL_1_P_Port_4 :: PKT_MSK0 [06:00] */
-#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_1_P_Port_4_PKT_MSK0_MASK 0x0000007f
-#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_1_P_Port_4_PKT_MSK0_SHIFT 0
-#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_1_P_Port_4_PKT_MSK0_DEFAULT 0x00000000
-
-/***************************************************************************
- *BC_SUP_RATECTRL_1_P_Port_5 - Port N Receive Rate Control 1 Registers
- ***************************************************************************/
-/* SWITCH_CORE :: BC_SUP_RATECTRL_1_P_Port_5 :: reserved_for_padding0 [31:16] */
-#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_1_P_Port_5_reserved_for_padding0_MASK 0xffff0000
-#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_1_P_Port_5_reserved_for_padding0_SHIFT 16
-
-/* SWITCH_CORE :: BC_SUP_RATECTRL_1_P_Port_5 :: IFG_BYTES1 [15:15] */
-#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_1_P_Port_5_IFG_BYTES1_MASK 0x00008000
-#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_1_P_Port_5_IFG_BYTES1_SHIFT 15
-#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_1_P_Port_5_IFG_BYTES1_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: BC_SUP_RATECTRL_1_P_Port_5 :: PKT_MSK1 [14:08] */
-#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_1_P_Port_5_PKT_MSK1_MASK 0x00007f00
-#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_1_P_Port_5_PKT_MSK1_SHIFT 8
-#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_1_P_Port_5_PKT_MSK1_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: BC_SUP_RATECTRL_1_P_Port_5 :: IFG_BYTES0 [07:07] */
-#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_1_P_Port_5_IFG_BYTES0_MASK 0x00000080
-#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_1_P_Port_5_IFG_BYTES0_SHIFT 7
-#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_1_P_Port_5_IFG_BYTES0_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: BC_SUP_RATECTRL_1_P_Port_5 :: PKT_MSK0 [06:00] */
-#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_1_P_Port_5_PKT_MSK0_MASK 0x0000007f
-#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_1_P_Port_5_PKT_MSK0_SHIFT 0
-#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_1_P_Port_5_PKT_MSK0_DEFAULT 0x00000000
-
-/***************************************************************************
- *BC_SUP_RATECTRL_1_P7 - Port 7 Receive Rate Control 1 Register
- ***************************************************************************/
-/* SWITCH_CORE :: BC_SUP_RATECTRL_1_P7 :: reserved_for_padding0 [31:16] */
-#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_1_P7_reserved_for_padding0_MASK 0xffff0000
-#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_1_P7_reserved_for_padding0_SHIFT 16
-
-/* SWITCH_CORE :: BC_SUP_RATECTRL_1_P7 :: IFG_BYTES1 [15:15] */
-#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_1_P7_IFG_BYTES1_MASK 0x00008000
-#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_1_P7_IFG_BYTES1_SHIFT 15
-#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_1_P7_IFG_BYTES1_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: BC_SUP_RATECTRL_1_P7 :: PKT_MSK1 [14:08] */
-#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_1_P7_PKT_MSK1_MASK 0x00007f00
-#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_1_P7_PKT_MSK1_SHIFT 8
-#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_1_P7_PKT_MSK1_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: BC_SUP_RATECTRL_1_P7 :: IFG_BYTES0 [07:07] */
-#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_1_P7_IFG_BYTES0_MASK 0x00000080
-#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_1_P7_IFG_BYTES0_SHIFT 7
-#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_1_P7_IFG_BYTES0_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: BC_SUP_RATECTRL_1_P7 :: PKT_MSK0 [06:00] */
-#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_1_P7_PKT_MSK0_MASK 0x0000007f
-#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_1_P7_PKT_MSK0_SHIFT 0
-#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_1_P7_PKT_MSK0_DEFAULT 0x00000000
-
-/***************************************************************************
- *BC_SUP_RATECTRL_1_IMP - Port 8 Receive Rate Control 1 Register
- ***************************************************************************/
-/* SWITCH_CORE :: BC_SUP_RATECTRL_1_IMP :: reserved_for_padding0 [31:16] */
-#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_1_IMP_reserved_for_padding0_MASK 0xffff0000
-#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_1_IMP_reserved_for_padding0_SHIFT 16
-
-/* SWITCH_CORE :: BC_SUP_RATECTRL_1_IMP :: IFG_BYTES1 [15:15] */
-#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_1_IMP_IFG_BYTES1_MASK 0x00008000
-#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_1_IMP_IFG_BYTES1_SHIFT 15
-#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_1_IMP_IFG_BYTES1_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: BC_SUP_RATECTRL_1_IMP :: PKT_MSK1 [14:08] */
-#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_1_IMP_PKT_MSK1_MASK 0x00007f00
-#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_1_IMP_PKT_MSK1_SHIFT 8
-#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_1_IMP_PKT_MSK1_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: BC_SUP_RATECTRL_1_IMP :: IFG_BYTES0 [07:07] */
-#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_1_IMP_IFG_BYTES0_MASK 0x00000080
-#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_1_IMP_IFG_BYTES0_SHIFT 7
-#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_1_IMP_IFG_BYTES0_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: BC_SUP_RATECTRL_1_IMP :: PKT_MSK0 [06:00] */
-#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_1_IMP_PKT_MSK0_MASK 0x0000007f
-#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_1_IMP_PKT_MSK0_SHIFT 0
-#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_1_IMP_PKT_MSK0_DEFAULT 0x00000000
-
-/***************************************************************************
- *BC_SUP_PKTDROP_CNT_P_Port_0 - Port N Suppressed Packet Drop Counter Register
- ***************************************************************************/
-/* SWITCH_CORE :: BC_SUP_PKTDROP_CNT_P_Port_0 :: PK_DROP_CNT [31:00] */
-#define BCHP_SWITCH_CORE_BC_SUP_PKTDROP_CNT_P_Port_0_PK_DROP_CNT_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_BC_SUP_PKTDROP_CNT_P_Port_0_PK_DROP_CNT_SHIFT 0
-#define BCHP_SWITCH_CORE_BC_SUP_PKTDROP_CNT_P_Port_0_PK_DROP_CNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *BC_SUP_PKTDROP_CNT_P_Port_1 - Port N Suppressed Packet Drop Counter Register
- ***************************************************************************/
-/* SWITCH_CORE :: BC_SUP_PKTDROP_CNT_P_Port_1 :: PK_DROP_CNT [31:00] */
-#define BCHP_SWITCH_CORE_BC_SUP_PKTDROP_CNT_P_Port_1_PK_DROP_CNT_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_BC_SUP_PKTDROP_CNT_P_Port_1_PK_DROP_CNT_SHIFT 0
-#define BCHP_SWITCH_CORE_BC_SUP_PKTDROP_CNT_P_Port_1_PK_DROP_CNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *BC_SUP_PKTDROP_CNT_P_Port_2 - Port N Suppressed Packet Drop Counter Register
- ***************************************************************************/
-/* SWITCH_CORE :: BC_SUP_PKTDROP_CNT_P_Port_2 :: PK_DROP_CNT [31:00] */
-#define BCHP_SWITCH_CORE_BC_SUP_PKTDROP_CNT_P_Port_2_PK_DROP_CNT_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_BC_SUP_PKTDROP_CNT_P_Port_2_PK_DROP_CNT_SHIFT 0
-#define BCHP_SWITCH_CORE_BC_SUP_PKTDROP_CNT_P_Port_2_PK_DROP_CNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *BC_SUP_PKTDROP_CNT_P_Port_3 - Port N Suppressed Packet Drop Counter Register
- ***************************************************************************/
-/* SWITCH_CORE :: BC_SUP_PKTDROP_CNT_P_Port_3 :: PK_DROP_CNT [31:00] */
-#define BCHP_SWITCH_CORE_BC_SUP_PKTDROP_CNT_P_Port_3_PK_DROP_CNT_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_BC_SUP_PKTDROP_CNT_P_Port_3_PK_DROP_CNT_SHIFT 0
-#define BCHP_SWITCH_CORE_BC_SUP_PKTDROP_CNT_P_Port_3_PK_DROP_CNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *BC_SUP_PKTDROP_CNT_P_Port_4 - Port N Suppressed Packet Drop Counter Register
- ***************************************************************************/
-/* SWITCH_CORE :: BC_SUP_PKTDROP_CNT_P_Port_4 :: PK_DROP_CNT [31:00] */
-#define BCHP_SWITCH_CORE_BC_SUP_PKTDROP_CNT_P_Port_4_PK_DROP_CNT_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_BC_SUP_PKTDROP_CNT_P_Port_4_PK_DROP_CNT_SHIFT 0
-#define BCHP_SWITCH_CORE_BC_SUP_PKTDROP_CNT_P_Port_4_PK_DROP_CNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *BC_SUP_PKTDROP_CNT_P_Port_5 - Port N Suppressed Packet Drop Counter Register
- ***************************************************************************/
-/* SWITCH_CORE :: BC_SUP_PKTDROP_CNT_P_Port_5 :: PK_DROP_CNT [31:00] */
-#define BCHP_SWITCH_CORE_BC_SUP_PKTDROP_CNT_P_Port_5_PK_DROP_CNT_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_BC_SUP_PKTDROP_CNT_P_Port_5_PK_DROP_CNT_SHIFT 0
-#define BCHP_SWITCH_CORE_BC_SUP_PKTDROP_CNT_P_Port_5_PK_DROP_CNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *BC_SUP_PKTDROP_CNT_P7 - Port 7 Suppressed Packet Drop Counter Register
- ***************************************************************************/
-/* SWITCH_CORE :: BC_SUP_PKTDROP_CNT_P7 :: PK_DROP_CNT [31:00] */
-#define BCHP_SWITCH_CORE_BC_SUP_PKTDROP_CNT_P7_PK_DROP_CNT_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_BC_SUP_PKTDROP_CNT_P7_PK_DROP_CNT_SHIFT 0
-#define BCHP_SWITCH_CORE_BC_SUP_PKTDROP_CNT_P7_PK_DROP_CNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *BC_SUP_PKTDROP_CNT_IMP - Port 8 Suppressed Packet Drop Counter Register
- ***************************************************************************/
-/* SWITCH_CORE :: BC_SUP_PKTDROP_CNT_IMP :: PK_DROP_CNT [31:00] */
-#define BCHP_SWITCH_CORE_BC_SUP_PKTDROP_CNT_IMP_PK_DROP_CNT_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_BC_SUP_PKTDROP_CNT_IMP_PK_DROP_CNT_SHIFT 0
-#define BCHP_SWITCH_CORE_BC_SUP_PKTDROP_CNT_IMP_PK_DROP_CNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *BC_SUPPRESS_REG_SPARE0 - Spare 0 Register (Not2Release)
- ***************************************************************************/
-/* SWITCH_CORE :: BC_SUPPRESS_REG_SPARE0 :: BC_SUPPRESS_REG_SPARE0 [31:00] */
-#define BCHP_SWITCH_CORE_BC_SUPPRESS_REG_SPARE0_BC_SUPPRESS_REG_SPARE0_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_BC_SUPPRESS_REG_SPARE0_BC_SUPPRESS_REG_SPARE0_SHIFT 0
-#define BCHP_SWITCH_CORE_BC_SUPPRESS_REG_SPARE0_BC_SUPPRESS_REG_SPARE0_DEFAULT 0x00000000
-
-/***************************************************************************
- *BC_SUPPRESS_REG_SPARE1 - Spare 1 Register (Not2Release)
- ***************************************************************************/
-/* SWITCH_CORE :: BC_SUPPRESS_REG_SPARE1 :: BC_SUPPRESS_REG_SPARE1 [31:00] */
-#define BCHP_SWITCH_CORE_BC_SUPPRESS_REG_SPARE1_BC_SUPPRESS_REG_SPARE1_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_BC_SUPPRESS_REG_SPARE1_BC_SUPPRESS_REG_SPARE1_SHIFT 0
-#define BCHP_SWITCH_CORE_BC_SUPPRESS_REG_SPARE1_BC_SUPPRESS_REG_SPARE1_DEFAULT 0x00000000
-
-/***************************************************************************
- *EAP_GLO_CON - EAP Global Configuration Registers
- ***************************************************************************/
-/* SWITCH_CORE :: EAP_GLO_CON :: reserved_for_padding0 [31:08] */
-#define BCHP_SWITCH_CORE_EAP_GLO_CON_reserved_for_padding0_MASK 0xffffff00
-#define BCHP_SWITCH_CORE_EAP_GLO_CON_reserved_for_padding0_SHIFT 8
-
-/* SWITCH_CORE :: EAP_GLO_CON :: SWITCH_RESV_0 [07:07] */
-#define BCHP_SWITCH_CORE_EAP_GLO_CON_SWITCH_RESV_0_MASK 0x00000080
-#define BCHP_SWITCH_CORE_EAP_GLO_CON_SWITCH_RESV_0_SHIFT 7
-#define BCHP_SWITCH_CORE_EAP_GLO_CON_SWITCH_RESV_0_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: EAP_GLO_CON :: EN_RARP [06:06] */
-#define BCHP_SWITCH_CORE_EAP_GLO_CON_EN_RARP_MASK 0x00000040
-#define BCHP_SWITCH_CORE_EAP_GLO_CON_EN_RARP_SHIFT 6
-#define BCHP_SWITCH_CORE_EAP_GLO_CON_EN_RARP_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: EAP_GLO_CON :: EN_BPDU [05:05] */
-#define BCHP_SWITCH_CORE_EAP_GLO_CON_EN_BPDU_MASK 0x00000020
-#define BCHP_SWITCH_CORE_EAP_GLO_CON_EN_BPDU_SHIFT 5
-#define BCHP_SWITCH_CORE_EAP_GLO_CON_EN_BPDU_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: EAP_GLO_CON :: EN_RMC [04:04] */
-#define BCHP_SWITCH_CORE_EAP_GLO_CON_EN_RMC_MASK 0x00000010
-#define BCHP_SWITCH_CORE_EAP_GLO_CON_EN_RMC_SHIFT 4
-#define BCHP_SWITCH_CORE_EAP_GLO_CON_EN_RMC_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: EAP_GLO_CON :: EN_DHCP [03:03] */
-#define BCHP_SWITCH_CORE_EAP_GLO_CON_EN_DHCP_MASK 0x00000008
-#define BCHP_SWITCH_CORE_EAP_GLO_CON_EN_DHCP_SHIFT 3
-#define BCHP_SWITCH_CORE_EAP_GLO_CON_EN_DHCP_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: EAP_GLO_CON :: EN_ARP [02:02] */
-#define BCHP_SWITCH_CORE_EAP_GLO_CON_EN_ARP_MASK 0x00000004
-#define BCHP_SWITCH_CORE_EAP_GLO_CON_EN_ARP_SHIFT 2
-#define BCHP_SWITCH_CORE_EAP_GLO_CON_EN_ARP_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: EAP_GLO_CON :: EN_2_DIP [01:01] */
-#define BCHP_SWITCH_CORE_EAP_GLO_CON_EN_2_DIP_MASK 0x00000002
-#define BCHP_SWITCH_CORE_EAP_GLO_CON_EN_2_DIP_SHIFT 1
-#define BCHP_SWITCH_CORE_EAP_GLO_CON_EN_2_DIP_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: EAP_GLO_CON :: SWITCH_RESV [00:00] */
-#define BCHP_SWITCH_CORE_EAP_GLO_CON_SWITCH_RESV_MASK 0x00000001
-#define BCHP_SWITCH_CORE_EAP_GLO_CON_SWITCH_RESV_SHIFT 0
-#define BCHP_SWITCH_CORE_EAP_GLO_CON_SWITCH_RESV_DEFAULT 0x00000000
-
-/***************************************************************************
- *EAP_MULTI_ADDR_CTRL - EAP Multiport Address Control Register
- ***************************************************************************/
-/* SWITCH_CORE :: EAP_MULTI_ADDR_CTRL :: reserved_for_padding0 [31:08] */
-#define BCHP_SWITCH_CORE_EAP_MULTI_ADDR_CTRL_reserved_for_padding0_MASK 0xffffff00
-#define BCHP_SWITCH_CORE_EAP_MULTI_ADDR_CTRL_reserved_for_padding0_SHIFT 8
-
-/* SWITCH_CORE :: EAP_MULTI_ADDR_CTRL :: SWITCH_RESV [07:06] */
-#define BCHP_SWITCH_CORE_EAP_MULTI_ADDR_CTRL_SWITCH_RESV_MASK 0x000000c0
-#define BCHP_SWITCH_CORE_EAP_MULTI_ADDR_CTRL_SWITCH_RESV_SHIFT 6
-#define BCHP_SWITCH_CORE_EAP_MULTI_ADDR_CTRL_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: EAP_MULTI_ADDR_CTRL :: EN_MPORT5 [05:05] */
-#define BCHP_SWITCH_CORE_EAP_MULTI_ADDR_CTRL_EN_MPORT5_MASK 0x00000020
-#define BCHP_SWITCH_CORE_EAP_MULTI_ADDR_CTRL_EN_MPORT5_SHIFT 5
-#define BCHP_SWITCH_CORE_EAP_MULTI_ADDR_CTRL_EN_MPORT5_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: EAP_MULTI_ADDR_CTRL :: EN_MPORT4 [04:04] */
-#define BCHP_SWITCH_CORE_EAP_MULTI_ADDR_CTRL_EN_MPORT4_MASK 0x00000010
-#define BCHP_SWITCH_CORE_EAP_MULTI_ADDR_CTRL_EN_MPORT4_SHIFT 4
-#define BCHP_SWITCH_CORE_EAP_MULTI_ADDR_CTRL_EN_MPORT4_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: EAP_MULTI_ADDR_CTRL :: EN_MPORT3 [03:03] */
-#define BCHP_SWITCH_CORE_EAP_MULTI_ADDR_CTRL_EN_MPORT3_MASK 0x00000008
-#define BCHP_SWITCH_CORE_EAP_MULTI_ADDR_CTRL_EN_MPORT3_SHIFT 3
-#define BCHP_SWITCH_CORE_EAP_MULTI_ADDR_CTRL_EN_MPORT3_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: EAP_MULTI_ADDR_CTRL :: EN_MPORT2 [02:02] */
-#define BCHP_SWITCH_CORE_EAP_MULTI_ADDR_CTRL_EN_MPORT2_MASK 0x00000004
-#define BCHP_SWITCH_CORE_EAP_MULTI_ADDR_CTRL_EN_MPORT2_SHIFT 2
-#define BCHP_SWITCH_CORE_EAP_MULTI_ADDR_CTRL_EN_MPORT2_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: EAP_MULTI_ADDR_CTRL :: EN_MPORT1 [01:01] */
-#define BCHP_SWITCH_CORE_EAP_MULTI_ADDR_CTRL_EN_MPORT1_MASK 0x00000002
-#define BCHP_SWITCH_CORE_EAP_MULTI_ADDR_CTRL_EN_MPORT1_SHIFT 1
-#define BCHP_SWITCH_CORE_EAP_MULTI_ADDR_CTRL_EN_MPORT1_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: EAP_MULTI_ADDR_CTRL :: EN_MPORT0 [00:00] */
-#define BCHP_SWITCH_CORE_EAP_MULTI_ADDR_CTRL_EN_MPORT0_MASK 0x00000001
-#define BCHP_SWITCH_CORE_EAP_MULTI_ADDR_CTRL_EN_MPORT0_SHIFT 0
-#define BCHP_SWITCH_CORE_EAP_MULTI_ADDR_CTRL_EN_MPORT0_DEFAULT 0x00000000
-
-/***************************************************************************
- *EAP_DIP_Port_0 - EAP Destination IP Registers
- ***************************************************************************/
-/* SWITCH_CORE :: EAP_DIP_Port_0 :: DIP_SUB_REG [63:32] */
-#define BCHP_SWITCH_CORE_EAP_DIP_Port_0_DIP_SUB_REG_MASK 0x00000000ffffffff
-#define BCHP_SWITCH_CORE_EAP_DIP_Port_0_DIP_SUB_REG_SHIFT 32
-#define BCHP_SWITCH_CORE_EAP_DIP_Port_0_DIP_SUB_REG_DEFAULT 0x0000000000000000
-
-/* SWITCH_CORE :: EAP_DIP_Port_0 :: DIP_MASK_REG [31:00] */
-#define BCHP_SWITCH_CORE_EAP_DIP_Port_0_DIP_MASK_REG_MASK 0x00000000ffffffff
-#define BCHP_SWITCH_CORE_EAP_DIP_Port_0_DIP_MASK_REG_SHIFT 0
-#define BCHP_SWITCH_CORE_EAP_DIP_Port_0_DIP_MASK_REG_DEFAULT 0x0000000000000000
-
-/***************************************************************************
- *EAP_DIP_Port_1 - EAP Destination IP Registers
- ***************************************************************************/
-/* SWITCH_CORE :: EAP_DIP_Port_1 :: DIP_SUB_REG [63:32] */
-#define BCHP_SWITCH_CORE_EAP_DIP_Port_1_DIP_SUB_REG_MASK 0x00000000ffffffff
-#define BCHP_SWITCH_CORE_EAP_DIP_Port_1_DIP_SUB_REG_SHIFT 32
-#define BCHP_SWITCH_CORE_EAP_DIP_Port_1_DIP_SUB_REG_DEFAULT 0x0000000000000000
-
-/* SWITCH_CORE :: EAP_DIP_Port_1 :: DIP_MASK_REG [31:00] */
-#define BCHP_SWITCH_CORE_EAP_DIP_Port_1_DIP_MASK_REG_MASK 0x00000000ffffffff
-#define BCHP_SWITCH_CORE_EAP_DIP_Port_1_DIP_MASK_REG_SHIFT 0
-#define BCHP_SWITCH_CORE_EAP_DIP_Port_1_DIP_MASK_REG_DEFAULT 0x0000000000000000
-
-/***************************************************************************
- *PORT_EAP_CON_Port_0 - Port N EAP Configuration Registers
- ***************************************************************************/
-/* SWITCH_CORE :: PORT_EAP_CON_Port_0 :: SWITCH_RESV [63:53] */
-#define BCHP_SWITCH_CORE_PORT_EAP_CON_Port_0_SWITCH_RESV_MASK 0x00000000ffe00000
-#define BCHP_SWITCH_CORE_PORT_EAP_CON_Port_0_SWITCH_RESV_SHIFT 53
-#define BCHP_SWITCH_CORE_PORT_EAP_CON_Port_0_SWITCH_RESV_DEFAULT 0x0000000000000000
-
-/* SWITCH_CORE :: PORT_EAP_CON_Port_0 :: EAP_MODE [52:51] */
-#define BCHP_SWITCH_CORE_PORT_EAP_CON_Port_0_EAP_MODE_MASK 0x0000000000180000
-#define BCHP_SWITCH_CORE_PORT_EAP_CON_Port_0_EAP_MODE_SHIFT 51
-#define BCHP_SWITCH_CORE_PORT_EAP_CON_Port_0_EAP_MODE_DEFAULT 0x0000000000000000
-
-/* SWITCH_CORE :: PORT_EAP_CON_Port_0 :: EAP_BLK_MODE [50:49] */
-#define BCHP_SWITCH_CORE_PORT_EAP_CON_Port_0_EAP_BLK_MODE_MASK 0x0000000000060000
-#define BCHP_SWITCH_CORE_PORT_EAP_CON_Port_0_EAP_BLK_MODE_SHIFT 49
-#define BCHP_SWITCH_CORE_PORT_EAP_CON_Port_0_EAP_BLK_MODE_DEFAULT 0x0000000000000000
-
-/* SWITCH_CORE :: PORT_EAP_CON_Port_0 :: EAP_EN_UNI_DA [48:48] */
-#define BCHP_SWITCH_CORE_PORT_EAP_CON_Port_0_EAP_EN_UNI_DA_MASK 0x0000000000010000
-#define BCHP_SWITCH_CORE_PORT_EAP_CON_Port_0_EAP_EN_UNI_DA_SHIFT 48
-#define BCHP_SWITCH_CORE_PORT_EAP_CON_Port_0_EAP_EN_UNI_DA_DEFAULT 0x0000000000000000
-
-/* SWITCH_CORE :: PORT_EAP_CON_Port_0 :: EAP_UNI_DA [47:00] */
-#define BCHP_SWITCH_CORE_PORT_EAP_CON_Port_0_EAP_UNI_DA_MASK 0x000000000000ffff
-#define BCHP_SWITCH_CORE_PORT_EAP_CON_Port_0_EAP_UNI_DA_SHIFT 0
-#define BCHP_SWITCH_CORE_PORT_EAP_CON_Port_0_EAP_UNI_DA_DEFAULT 0x0000000000000000
-
-/***************************************************************************
- *PORT_EAP_CON_Port_1 - Port N EAP Configuration Registers
- ***************************************************************************/
-/* SWITCH_CORE :: PORT_EAP_CON_Port_1 :: SWITCH_RESV [63:53] */
-#define BCHP_SWITCH_CORE_PORT_EAP_CON_Port_1_SWITCH_RESV_MASK 0x00000000ffe00000
-#define BCHP_SWITCH_CORE_PORT_EAP_CON_Port_1_SWITCH_RESV_SHIFT 53
-#define BCHP_SWITCH_CORE_PORT_EAP_CON_Port_1_SWITCH_RESV_DEFAULT 0x0000000000000000
-
-/* SWITCH_CORE :: PORT_EAP_CON_Port_1 :: EAP_MODE [52:51] */
-#define BCHP_SWITCH_CORE_PORT_EAP_CON_Port_1_EAP_MODE_MASK 0x0000000000180000
-#define BCHP_SWITCH_CORE_PORT_EAP_CON_Port_1_EAP_MODE_SHIFT 51
-#define BCHP_SWITCH_CORE_PORT_EAP_CON_Port_1_EAP_MODE_DEFAULT 0x0000000000000000
-
-/* SWITCH_CORE :: PORT_EAP_CON_Port_1 :: EAP_BLK_MODE [50:49] */
-#define BCHP_SWITCH_CORE_PORT_EAP_CON_Port_1_EAP_BLK_MODE_MASK 0x0000000000060000
-#define BCHP_SWITCH_CORE_PORT_EAP_CON_Port_1_EAP_BLK_MODE_SHIFT 49
-#define BCHP_SWITCH_CORE_PORT_EAP_CON_Port_1_EAP_BLK_MODE_DEFAULT 0x0000000000000000
-
-/* SWITCH_CORE :: PORT_EAP_CON_Port_1 :: EAP_EN_UNI_DA [48:48] */
-#define BCHP_SWITCH_CORE_PORT_EAP_CON_Port_1_EAP_EN_UNI_DA_MASK 0x0000000000010000
-#define BCHP_SWITCH_CORE_PORT_EAP_CON_Port_1_EAP_EN_UNI_DA_SHIFT 48
-#define BCHP_SWITCH_CORE_PORT_EAP_CON_Port_1_EAP_EN_UNI_DA_DEFAULT 0x0000000000000000
-
-/* SWITCH_CORE :: PORT_EAP_CON_Port_1 :: EAP_UNI_DA [47:00] */
-#define BCHP_SWITCH_CORE_PORT_EAP_CON_Port_1_EAP_UNI_DA_MASK 0x000000000000ffff
-#define BCHP_SWITCH_CORE_PORT_EAP_CON_Port_1_EAP_UNI_DA_SHIFT 0
-#define BCHP_SWITCH_CORE_PORT_EAP_CON_Port_1_EAP_UNI_DA_DEFAULT 0x0000000000000000
-
-/***************************************************************************
- *PORT_EAP_CON_Port_2 - Port N EAP Configuration Registers
- ***************************************************************************/
-/* SWITCH_CORE :: PORT_EAP_CON_Port_2 :: SWITCH_RESV [63:53] */
-#define BCHP_SWITCH_CORE_PORT_EAP_CON_Port_2_SWITCH_RESV_MASK 0x00000000ffe00000
-#define BCHP_SWITCH_CORE_PORT_EAP_CON_Port_2_SWITCH_RESV_SHIFT 53
-#define BCHP_SWITCH_CORE_PORT_EAP_CON_Port_2_SWITCH_RESV_DEFAULT 0x0000000000000000
-
-/* SWITCH_CORE :: PORT_EAP_CON_Port_2 :: EAP_MODE [52:51] */
-#define BCHP_SWITCH_CORE_PORT_EAP_CON_Port_2_EAP_MODE_MASK 0x0000000000180000
-#define BCHP_SWITCH_CORE_PORT_EAP_CON_Port_2_EAP_MODE_SHIFT 51
-#define BCHP_SWITCH_CORE_PORT_EAP_CON_Port_2_EAP_MODE_DEFAULT 0x0000000000000000
-
-/* SWITCH_CORE :: PORT_EAP_CON_Port_2 :: EAP_BLK_MODE [50:49] */
-#define BCHP_SWITCH_CORE_PORT_EAP_CON_Port_2_EAP_BLK_MODE_MASK 0x0000000000060000
-#define BCHP_SWITCH_CORE_PORT_EAP_CON_Port_2_EAP_BLK_MODE_SHIFT 49
-#define BCHP_SWITCH_CORE_PORT_EAP_CON_Port_2_EAP_BLK_MODE_DEFAULT 0x0000000000000000
-
-/* SWITCH_CORE :: PORT_EAP_CON_Port_2 :: EAP_EN_UNI_DA [48:48] */
-#define BCHP_SWITCH_CORE_PORT_EAP_CON_Port_2_EAP_EN_UNI_DA_MASK 0x0000000000010000
-#define BCHP_SWITCH_CORE_PORT_EAP_CON_Port_2_EAP_EN_UNI_DA_SHIFT 48
-#define BCHP_SWITCH_CORE_PORT_EAP_CON_Port_2_EAP_EN_UNI_DA_DEFAULT 0x0000000000000000
-
-/* SWITCH_CORE :: PORT_EAP_CON_Port_2 :: EAP_UNI_DA [47:00] */
-#define BCHP_SWITCH_CORE_PORT_EAP_CON_Port_2_EAP_UNI_DA_MASK 0x000000000000ffff
-#define BCHP_SWITCH_CORE_PORT_EAP_CON_Port_2_EAP_UNI_DA_SHIFT 0
-#define BCHP_SWITCH_CORE_PORT_EAP_CON_Port_2_EAP_UNI_DA_DEFAULT 0x0000000000000000
-
-/***************************************************************************
- *PORT_EAP_CON_Port_3 - Port N EAP Configuration Registers
- ***************************************************************************/
-/* SWITCH_CORE :: PORT_EAP_CON_Port_3 :: SWITCH_RESV [63:53] */
-#define BCHP_SWITCH_CORE_PORT_EAP_CON_Port_3_SWITCH_RESV_MASK 0x00000000ffe00000
-#define BCHP_SWITCH_CORE_PORT_EAP_CON_Port_3_SWITCH_RESV_SHIFT 53
-#define BCHP_SWITCH_CORE_PORT_EAP_CON_Port_3_SWITCH_RESV_DEFAULT 0x0000000000000000
-
-/* SWITCH_CORE :: PORT_EAP_CON_Port_3 :: EAP_MODE [52:51] */
-#define BCHP_SWITCH_CORE_PORT_EAP_CON_Port_3_EAP_MODE_MASK 0x0000000000180000
-#define BCHP_SWITCH_CORE_PORT_EAP_CON_Port_3_EAP_MODE_SHIFT 51
-#define BCHP_SWITCH_CORE_PORT_EAP_CON_Port_3_EAP_MODE_DEFAULT 0x0000000000000000
-
-/* SWITCH_CORE :: PORT_EAP_CON_Port_3 :: EAP_BLK_MODE [50:49] */
-#define BCHP_SWITCH_CORE_PORT_EAP_CON_Port_3_EAP_BLK_MODE_MASK 0x0000000000060000
-#define BCHP_SWITCH_CORE_PORT_EAP_CON_Port_3_EAP_BLK_MODE_SHIFT 49
-#define BCHP_SWITCH_CORE_PORT_EAP_CON_Port_3_EAP_BLK_MODE_DEFAULT 0x0000000000000000
-
-/* SWITCH_CORE :: PORT_EAP_CON_Port_3 :: EAP_EN_UNI_DA [48:48] */
-#define BCHP_SWITCH_CORE_PORT_EAP_CON_Port_3_EAP_EN_UNI_DA_MASK 0x0000000000010000
-#define BCHP_SWITCH_CORE_PORT_EAP_CON_Port_3_EAP_EN_UNI_DA_SHIFT 48
-#define BCHP_SWITCH_CORE_PORT_EAP_CON_Port_3_EAP_EN_UNI_DA_DEFAULT 0x0000000000000000
-
-/* SWITCH_CORE :: PORT_EAP_CON_Port_3 :: EAP_UNI_DA [47:00] */
-#define BCHP_SWITCH_CORE_PORT_EAP_CON_Port_3_EAP_UNI_DA_MASK 0x000000000000ffff
-#define BCHP_SWITCH_CORE_PORT_EAP_CON_Port_3_EAP_UNI_DA_SHIFT 0
-#define BCHP_SWITCH_CORE_PORT_EAP_CON_Port_3_EAP_UNI_DA_DEFAULT 0x0000000000000000
-
-/***************************************************************************
- *PORT_EAP_CON_Port_4 - Port N EAP Configuration Registers
- ***************************************************************************/
-/* SWITCH_CORE :: PORT_EAP_CON_Port_4 :: SWITCH_RESV [63:53] */
-#define BCHP_SWITCH_CORE_PORT_EAP_CON_Port_4_SWITCH_RESV_MASK 0x00000000ffe00000
-#define BCHP_SWITCH_CORE_PORT_EAP_CON_Port_4_SWITCH_RESV_SHIFT 53
-#define BCHP_SWITCH_CORE_PORT_EAP_CON_Port_4_SWITCH_RESV_DEFAULT 0x0000000000000000
-
-/* SWITCH_CORE :: PORT_EAP_CON_Port_4 :: EAP_MODE [52:51] */
-#define BCHP_SWITCH_CORE_PORT_EAP_CON_Port_4_EAP_MODE_MASK 0x0000000000180000
-#define BCHP_SWITCH_CORE_PORT_EAP_CON_Port_4_EAP_MODE_SHIFT 51
-#define BCHP_SWITCH_CORE_PORT_EAP_CON_Port_4_EAP_MODE_DEFAULT 0x0000000000000000
-
-/* SWITCH_CORE :: PORT_EAP_CON_Port_4 :: EAP_BLK_MODE [50:49] */
-#define BCHP_SWITCH_CORE_PORT_EAP_CON_Port_4_EAP_BLK_MODE_MASK 0x0000000000060000
-#define BCHP_SWITCH_CORE_PORT_EAP_CON_Port_4_EAP_BLK_MODE_SHIFT 49
-#define BCHP_SWITCH_CORE_PORT_EAP_CON_Port_4_EAP_BLK_MODE_DEFAULT 0x0000000000000000
-
-/* SWITCH_CORE :: PORT_EAP_CON_Port_4 :: EAP_EN_UNI_DA [48:48] */
-#define BCHP_SWITCH_CORE_PORT_EAP_CON_Port_4_EAP_EN_UNI_DA_MASK 0x0000000000010000
-#define BCHP_SWITCH_CORE_PORT_EAP_CON_Port_4_EAP_EN_UNI_DA_SHIFT 48
-#define BCHP_SWITCH_CORE_PORT_EAP_CON_Port_4_EAP_EN_UNI_DA_DEFAULT 0x0000000000000000
-
-/* SWITCH_CORE :: PORT_EAP_CON_Port_4 :: EAP_UNI_DA [47:00] */
-#define BCHP_SWITCH_CORE_PORT_EAP_CON_Port_4_EAP_UNI_DA_MASK 0x000000000000ffff
-#define BCHP_SWITCH_CORE_PORT_EAP_CON_Port_4_EAP_UNI_DA_SHIFT 0
-#define BCHP_SWITCH_CORE_PORT_EAP_CON_Port_4_EAP_UNI_DA_DEFAULT 0x0000000000000000
-
-/***************************************************************************
- *PORT_EAP_CON_Port_5 - Port N EAP Configuration Registers
- ***************************************************************************/
-/* SWITCH_CORE :: PORT_EAP_CON_Port_5 :: SWITCH_RESV [63:53] */
-#define BCHP_SWITCH_CORE_PORT_EAP_CON_Port_5_SWITCH_RESV_MASK 0x00000000ffe00000
-#define BCHP_SWITCH_CORE_PORT_EAP_CON_Port_5_SWITCH_RESV_SHIFT 53
-#define BCHP_SWITCH_CORE_PORT_EAP_CON_Port_5_SWITCH_RESV_DEFAULT 0x0000000000000000
-
-/* SWITCH_CORE :: PORT_EAP_CON_Port_5 :: EAP_MODE [52:51] */
-#define BCHP_SWITCH_CORE_PORT_EAP_CON_Port_5_EAP_MODE_MASK 0x0000000000180000
-#define BCHP_SWITCH_CORE_PORT_EAP_CON_Port_5_EAP_MODE_SHIFT 51
-#define BCHP_SWITCH_CORE_PORT_EAP_CON_Port_5_EAP_MODE_DEFAULT 0x0000000000000000
-
-/* SWITCH_CORE :: PORT_EAP_CON_Port_5 :: EAP_BLK_MODE [50:49] */
-#define BCHP_SWITCH_CORE_PORT_EAP_CON_Port_5_EAP_BLK_MODE_MASK 0x0000000000060000
-#define BCHP_SWITCH_CORE_PORT_EAP_CON_Port_5_EAP_BLK_MODE_SHIFT 49
-#define BCHP_SWITCH_CORE_PORT_EAP_CON_Port_5_EAP_BLK_MODE_DEFAULT 0x0000000000000000
-
-/* SWITCH_CORE :: PORT_EAP_CON_Port_5 :: EAP_EN_UNI_DA [48:48] */
-#define BCHP_SWITCH_CORE_PORT_EAP_CON_Port_5_EAP_EN_UNI_DA_MASK 0x0000000000010000
-#define BCHP_SWITCH_CORE_PORT_EAP_CON_Port_5_EAP_EN_UNI_DA_SHIFT 48
-#define BCHP_SWITCH_CORE_PORT_EAP_CON_Port_5_EAP_EN_UNI_DA_DEFAULT 0x0000000000000000
-
-/* SWITCH_CORE :: PORT_EAP_CON_Port_5 :: EAP_UNI_DA [47:00] */
-#define BCHP_SWITCH_CORE_PORT_EAP_CON_Port_5_EAP_UNI_DA_MASK 0x000000000000ffff
-#define BCHP_SWITCH_CORE_PORT_EAP_CON_Port_5_EAP_UNI_DA_SHIFT 0
-#define BCHP_SWITCH_CORE_PORT_EAP_CON_Port_5_EAP_UNI_DA_DEFAULT 0x0000000000000000
-
-/***************************************************************************
- *PORT_EAP_CON_P7 - Port 7 EAP Configuration Registers
- ***************************************************************************/
-/* SWITCH_CORE :: PORT_EAP_CON_P7 :: SWITCH_RESV [63:53] */
-#define BCHP_SWITCH_CORE_PORT_EAP_CON_P7_SWITCH_RESV_MASK 0x00000000ffe00000
-#define BCHP_SWITCH_CORE_PORT_EAP_CON_P7_SWITCH_RESV_SHIFT 53
-#define BCHP_SWITCH_CORE_PORT_EAP_CON_P7_SWITCH_RESV_DEFAULT 0x0000000000000000
-
-/* SWITCH_CORE :: PORT_EAP_CON_P7 :: EAP_MODE [52:51] */
-#define BCHP_SWITCH_CORE_PORT_EAP_CON_P7_EAP_MODE_MASK 0x0000000000180000
-#define BCHP_SWITCH_CORE_PORT_EAP_CON_P7_EAP_MODE_SHIFT 51
-#define BCHP_SWITCH_CORE_PORT_EAP_CON_P7_EAP_MODE_DEFAULT 0x0000000000000000
-
-/* SWITCH_CORE :: PORT_EAP_CON_P7 :: EAP_BLK_MODE [50:49] */
-#define BCHP_SWITCH_CORE_PORT_EAP_CON_P7_EAP_BLK_MODE_MASK 0x0000000000060000
-#define BCHP_SWITCH_CORE_PORT_EAP_CON_P7_EAP_BLK_MODE_SHIFT 49
-#define BCHP_SWITCH_CORE_PORT_EAP_CON_P7_EAP_BLK_MODE_DEFAULT 0x0000000000000000
-
-/* SWITCH_CORE :: PORT_EAP_CON_P7 :: EAP_EN_UNI_DA [48:48] */
-#define BCHP_SWITCH_CORE_PORT_EAP_CON_P7_EAP_EN_UNI_DA_MASK 0x0000000000010000
-#define BCHP_SWITCH_CORE_PORT_EAP_CON_P7_EAP_EN_UNI_DA_SHIFT 48
-#define BCHP_SWITCH_CORE_PORT_EAP_CON_P7_EAP_EN_UNI_DA_DEFAULT 0x0000000000000000
-
-/* SWITCH_CORE :: PORT_EAP_CON_P7 :: EAP_UNI_DA [47:00] */
-#define BCHP_SWITCH_CORE_PORT_EAP_CON_P7_EAP_UNI_DA_MASK 0x000000000000ffff
-#define BCHP_SWITCH_CORE_PORT_EAP_CON_P7_EAP_UNI_DA_SHIFT 0
-#define BCHP_SWITCH_CORE_PORT_EAP_CON_P7_EAP_UNI_DA_DEFAULT 0x0000000000000000
-
-/***************************************************************************
- *PORT_EAP_CON_IMP - IMP EAP Configuration Registers
- ***************************************************************************/
-/* SWITCH_CORE :: PORT_EAP_CON_IMP :: SWITCH_RESV [63:53] */
-#define BCHP_SWITCH_CORE_PORT_EAP_CON_IMP_SWITCH_RESV_MASK 0x00000000ffe00000
-#define BCHP_SWITCH_CORE_PORT_EAP_CON_IMP_SWITCH_RESV_SHIFT 53
-#define BCHP_SWITCH_CORE_PORT_EAP_CON_IMP_SWITCH_RESV_DEFAULT 0x0000000000000000
-
-/* SWITCH_CORE :: PORT_EAP_CON_IMP :: EAP_MODE [52:51] */
-#define BCHP_SWITCH_CORE_PORT_EAP_CON_IMP_EAP_MODE_MASK 0x0000000000180000
-#define BCHP_SWITCH_CORE_PORT_EAP_CON_IMP_EAP_MODE_SHIFT 51
-#define BCHP_SWITCH_CORE_PORT_EAP_CON_IMP_EAP_MODE_DEFAULT 0x0000000000000000
-
-/* SWITCH_CORE :: PORT_EAP_CON_IMP :: EAP_BLK_MODE [50:49] */
-#define BCHP_SWITCH_CORE_PORT_EAP_CON_IMP_EAP_BLK_MODE_MASK 0x0000000000060000
-#define BCHP_SWITCH_CORE_PORT_EAP_CON_IMP_EAP_BLK_MODE_SHIFT 49
-#define BCHP_SWITCH_CORE_PORT_EAP_CON_IMP_EAP_BLK_MODE_DEFAULT 0x0000000000000000
-
-/* SWITCH_CORE :: PORT_EAP_CON_IMP :: EAP_EN_UNI_DA [48:48] */
-#define BCHP_SWITCH_CORE_PORT_EAP_CON_IMP_EAP_EN_UNI_DA_MASK 0x0000000000010000
-#define BCHP_SWITCH_CORE_PORT_EAP_CON_IMP_EAP_EN_UNI_DA_SHIFT 48
-#define BCHP_SWITCH_CORE_PORT_EAP_CON_IMP_EAP_EN_UNI_DA_DEFAULT 0x0000000000000000
-
-/* SWITCH_CORE :: PORT_EAP_CON_IMP :: EAP_UNI_DA [47:00] */
-#define BCHP_SWITCH_CORE_PORT_EAP_CON_IMP_EAP_UNI_DA_MASK 0x000000000000ffff
-#define BCHP_SWITCH_CORE_PORT_EAP_CON_IMP_EAP_UNI_DA_SHIFT 0
-#define BCHP_SWITCH_CORE_PORT_EAP_CON_IMP_EAP_UNI_DA_DEFAULT 0x0000000000000000
-
-/***************************************************************************
- *IEEE8021X_REG_SPARE0 - Spare 0 Register (Not2Release)
- ***************************************************************************/
-/* SWITCH_CORE :: IEEE8021X_REG_SPARE0 :: IEEE8021X_REG_SPARE0 [31:00] */
-#define BCHP_SWITCH_CORE_IEEE8021X_REG_SPARE0_IEEE8021X_REG_SPARE0_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_IEEE8021X_REG_SPARE0_IEEE8021X_REG_SPARE0_SHIFT 0
-#define BCHP_SWITCH_CORE_IEEE8021X_REG_SPARE0_IEEE8021X_REG_SPARE0_DEFAULT 0x00000000
-
-/***************************************************************************
- *IEEE8021X_REG_SPARE1 - Spare 1 Register (Not2Release)
- ***************************************************************************/
-/* SWITCH_CORE :: IEEE8021X_REG_SPARE1 :: IEEE8021X_REG_SPARE1 [31:00] */
-#define BCHP_SWITCH_CORE_IEEE8021X_REG_SPARE1_IEEE8021X_REG_SPARE1_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_IEEE8021X_REG_SPARE1_IEEE8021X_REG_SPARE1_SHIFT 0
-#define BCHP_SWITCH_CORE_IEEE8021X_REG_SPARE1_IEEE8021X_REG_SPARE1_DEFAULT 0x00000000
-
-/***************************************************************************
- *MST_CON - MST Control Registers
- ***************************************************************************/
-/* SWITCH_CORE :: MST_CON :: reserved_for_padding0 [31:08] */
-#define BCHP_SWITCH_CORE_MST_CON_reserved_for_padding0_MASK 0xffffff00
-#define BCHP_SWITCH_CORE_MST_CON_reserved_for_padding0_SHIFT 8
-
-/* SWITCH_CORE :: MST_CON :: SWITCH_RESV [07:01] */
-#define BCHP_SWITCH_CORE_MST_CON_SWITCH_RESV_MASK 0x000000fe
-#define BCHP_SWITCH_CORE_MST_CON_SWITCH_RESV_SHIFT 1
-#define BCHP_SWITCH_CORE_MST_CON_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: MST_CON :: EN_802_1S [00:00] */
-#define BCHP_SWITCH_CORE_MST_CON_EN_802_1S_MASK 0x00000001
-#define BCHP_SWITCH_CORE_MST_CON_EN_802_1S_SHIFT 0
-#define BCHP_SWITCH_CORE_MST_CON_EN_802_1S_DEFAULT 0x00000000
-
-/***************************************************************************
- *MST_AGE - MST Ageing Control Register
- ***************************************************************************/
-/* SWITCH_CORE :: MST_AGE :: SWITCH_RESV [31:08] */
-#define BCHP_SWITCH_CORE_MST_AGE_SWITCH_RESV_MASK 0xffffff00
-#define BCHP_SWITCH_CORE_MST_AGE_SWITCH_RESV_SHIFT 8
-#define BCHP_SWITCH_CORE_MST_AGE_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: MST_AGE :: AGE_EN_PRT [07:00] */
-#define BCHP_SWITCH_CORE_MST_AGE_AGE_EN_PRT_MASK 0x000000ff
-#define BCHP_SWITCH_CORE_MST_AGE_AGE_EN_PRT_SHIFT 0
-#define BCHP_SWITCH_CORE_MST_AGE_AGE_EN_PRT_DEFAULT 0x00000000
-
-/***************************************************************************
- *MST_TAB_Port_0 - MST Table N Enable Registers
- ***************************************************************************/
-/* SWITCH_CORE :: MST_TAB_Port_0 :: MST_TAB_RSRV [31:27] */
-#define BCHP_SWITCH_CORE_MST_TAB_Port_0_MST_TAB_RSRV_MASK 0xf8000000
-#define BCHP_SWITCH_CORE_MST_TAB_Port_0_MST_TAB_RSRV_SHIFT 27
-#define BCHP_SWITCH_CORE_MST_TAB_Port_0_MST_TAB_RSRV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: MST_TAB_Port_0 :: SWITCH_RESV_1 [26:24] */
-#define BCHP_SWITCH_CORE_MST_TAB_Port_0_SWITCH_RESV_1_MASK 0x07000000
-#define BCHP_SWITCH_CORE_MST_TAB_Port_0_SWITCH_RESV_1_SHIFT 24
-#define BCHP_SWITCH_CORE_MST_TAB_Port_0_SWITCH_RESV_1_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: MST_TAB_Port_0 :: SPT_STA7 [23:21] */
-#define BCHP_SWITCH_CORE_MST_TAB_Port_0_SPT_STA7_MASK 0x00e00000
-#define BCHP_SWITCH_CORE_MST_TAB_Port_0_SPT_STA7_SHIFT 21
-#define BCHP_SWITCH_CORE_MST_TAB_Port_0_SPT_STA7_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: MST_TAB_Port_0 :: SWITCH_RESV_0 [20:18] */
-#define BCHP_SWITCH_CORE_MST_TAB_Port_0_SWITCH_RESV_0_MASK 0x001c0000
-#define BCHP_SWITCH_CORE_MST_TAB_Port_0_SWITCH_RESV_0_SHIFT 18
-#define BCHP_SWITCH_CORE_MST_TAB_Port_0_SWITCH_RESV_0_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: MST_TAB_Port_0 :: SPT_STA5 [17:15] */
-#define BCHP_SWITCH_CORE_MST_TAB_Port_0_SPT_STA5_MASK 0x00038000
-#define BCHP_SWITCH_CORE_MST_TAB_Port_0_SPT_STA5_SHIFT 15
-#define BCHP_SWITCH_CORE_MST_TAB_Port_0_SPT_STA5_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: MST_TAB_Port_0 :: SPT_STA4 [14:12] */
-#define BCHP_SWITCH_CORE_MST_TAB_Port_0_SPT_STA4_MASK 0x00007000
-#define BCHP_SWITCH_CORE_MST_TAB_Port_0_SPT_STA4_SHIFT 12
-#define BCHP_SWITCH_CORE_MST_TAB_Port_0_SPT_STA4_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: MST_TAB_Port_0 :: SPT_STA3 [11:09] */
-#define BCHP_SWITCH_CORE_MST_TAB_Port_0_SPT_STA3_MASK 0x00000e00
-#define BCHP_SWITCH_CORE_MST_TAB_Port_0_SPT_STA3_SHIFT 9
-#define BCHP_SWITCH_CORE_MST_TAB_Port_0_SPT_STA3_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: MST_TAB_Port_0 :: SPT_STA2 [08:06] */
-#define BCHP_SWITCH_CORE_MST_TAB_Port_0_SPT_STA2_MASK 0x000001c0
-#define BCHP_SWITCH_CORE_MST_TAB_Port_0_SPT_STA2_SHIFT 6
-#define BCHP_SWITCH_CORE_MST_TAB_Port_0_SPT_STA2_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: MST_TAB_Port_0 :: SPT_STA1 [05:03] */
-#define BCHP_SWITCH_CORE_MST_TAB_Port_0_SPT_STA1_MASK 0x00000038
-#define BCHP_SWITCH_CORE_MST_TAB_Port_0_SPT_STA1_SHIFT 3
-#define BCHP_SWITCH_CORE_MST_TAB_Port_0_SPT_STA1_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: MST_TAB_Port_0 :: SPT_STA0 [02:00] */
-#define BCHP_SWITCH_CORE_MST_TAB_Port_0_SPT_STA0_MASK 0x00000007
-#define BCHP_SWITCH_CORE_MST_TAB_Port_0_SPT_STA0_SHIFT 0
-#define BCHP_SWITCH_CORE_MST_TAB_Port_0_SPT_STA0_DEFAULT 0x00000000
-
-/***************************************************************************
- *MST_TAB_Port_1 - MST Table N Enable Registers
- ***************************************************************************/
-/* SWITCH_CORE :: MST_TAB_Port_1 :: MST_TAB_RSRV [31:27] */
-#define BCHP_SWITCH_CORE_MST_TAB_Port_1_MST_TAB_RSRV_MASK 0xf8000000
-#define BCHP_SWITCH_CORE_MST_TAB_Port_1_MST_TAB_RSRV_SHIFT 27
-#define BCHP_SWITCH_CORE_MST_TAB_Port_1_MST_TAB_RSRV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: MST_TAB_Port_1 :: SWITCH_RESV_1 [26:24] */
-#define BCHP_SWITCH_CORE_MST_TAB_Port_1_SWITCH_RESV_1_MASK 0x07000000
-#define BCHP_SWITCH_CORE_MST_TAB_Port_1_SWITCH_RESV_1_SHIFT 24
-#define BCHP_SWITCH_CORE_MST_TAB_Port_1_SWITCH_RESV_1_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: MST_TAB_Port_1 :: SPT_STA7 [23:21] */
-#define BCHP_SWITCH_CORE_MST_TAB_Port_1_SPT_STA7_MASK 0x00e00000
-#define BCHP_SWITCH_CORE_MST_TAB_Port_1_SPT_STA7_SHIFT 21
-#define BCHP_SWITCH_CORE_MST_TAB_Port_1_SPT_STA7_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: MST_TAB_Port_1 :: SWITCH_RESV_0 [20:18] */
-#define BCHP_SWITCH_CORE_MST_TAB_Port_1_SWITCH_RESV_0_MASK 0x001c0000
-#define BCHP_SWITCH_CORE_MST_TAB_Port_1_SWITCH_RESV_0_SHIFT 18
-#define BCHP_SWITCH_CORE_MST_TAB_Port_1_SWITCH_RESV_0_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: MST_TAB_Port_1 :: SPT_STA5 [17:15] */
-#define BCHP_SWITCH_CORE_MST_TAB_Port_1_SPT_STA5_MASK 0x00038000
-#define BCHP_SWITCH_CORE_MST_TAB_Port_1_SPT_STA5_SHIFT 15
-#define BCHP_SWITCH_CORE_MST_TAB_Port_1_SPT_STA5_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: MST_TAB_Port_1 :: SPT_STA4 [14:12] */
-#define BCHP_SWITCH_CORE_MST_TAB_Port_1_SPT_STA4_MASK 0x00007000
-#define BCHP_SWITCH_CORE_MST_TAB_Port_1_SPT_STA4_SHIFT 12
-#define BCHP_SWITCH_CORE_MST_TAB_Port_1_SPT_STA4_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: MST_TAB_Port_1 :: SPT_STA3 [11:09] */
-#define BCHP_SWITCH_CORE_MST_TAB_Port_1_SPT_STA3_MASK 0x00000e00
-#define BCHP_SWITCH_CORE_MST_TAB_Port_1_SPT_STA3_SHIFT 9
-#define BCHP_SWITCH_CORE_MST_TAB_Port_1_SPT_STA3_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: MST_TAB_Port_1 :: SPT_STA2 [08:06] */
-#define BCHP_SWITCH_CORE_MST_TAB_Port_1_SPT_STA2_MASK 0x000001c0
-#define BCHP_SWITCH_CORE_MST_TAB_Port_1_SPT_STA2_SHIFT 6
-#define BCHP_SWITCH_CORE_MST_TAB_Port_1_SPT_STA2_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: MST_TAB_Port_1 :: SPT_STA1 [05:03] */
-#define BCHP_SWITCH_CORE_MST_TAB_Port_1_SPT_STA1_MASK 0x00000038
-#define BCHP_SWITCH_CORE_MST_TAB_Port_1_SPT_STA1_SHIFT 3
-#define BCHP_SWITCH_CORE_MST_TAB_Port_1_SPT_STA1_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: MST_TAB_Port_1 :: SPT_STA0 [02:00] */
-#define BCHP_SWITCH_CORE_MST_TAB_Port_1_SPT_STA0_MASK 0x00000007
-#define BCHP_SWITCH_CORE_MST_TAB_Port_1_SPT_STA0_SHIFT 0
-#define BCHP_SWITCH_CORE_MST_TAB_Port_1_SPT_STA0_DEFAULT 0x00000000
-
-/***************************************************************************
- *MST_TAB_Port_2 - MST Table N Enable Registers
- ***************************************************************************/
-/* SWITCH_CORE :: MST_TAB_Port_2 :: MST_TAB_RSRV [31:27] */
-#define BCHP_SWITCH_CORE_MST_TAB_Port_2_MST_TAB_RSRV_MASK 0xf8000000
-#define BCHP_SWITCH_CORE_MST_TAB_Port_2_MST_TAB_RSRV_SHIFT 27
-#define BCHP_SWITCH_CORE_MST_TAB_Port_2_MST_TAB_RSRV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: MST_TAB_Port_2 :: SWITCH_RESV_1 [26:24] */
-#define BCHP_SWITCH_CORE_MST_TAB_Port_2_SWITCH_RESV_1_MASK 0x07000000
-#define BCHP_SWITCH_CORE_MST_TAB_Port_2_SWITCH_RESV_1_SHIFT 24
-#define BCHP_SWITCH_CORE_MST_TAB_Port_2_SWITCH_RESV_1_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: MST_TAB_Port_2 :: SPT_STA7 [23:21] */
-#define BCHP_SWITCH_CORE_MST_TAB_Port_2_SPT_STA7_MASK 0x00e00000
-#define BCHP_SWITCH_CORE_MST_TAB_Port_2_SPT_STA7_SHIFT 21
-#define BCHP_SWITCH_CORE_MST_TAB_Port_2_SPT_STA7_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: MST_TAB_Port_2 :: SWITCH_RESV_0 [20:18] */
-#define BCHP_SWITCH_CORE_MST_TAB_Port_2_SWITCH_RESV_0_MASK 0x001c0000
-#define BCHP_SWITCH_CORE_MST_TAB_Port_2_SWITCH_RESV_0_SHIFT 18
-#define BCHP_SWITCH_CORE_MST_TAB_Port_2_SWITCH_RESV_0_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: MST_TAB_Port_2 :: SPT_STA5 [17:15] */
-#define BCHP_SWITCH_CORE_MST_TAB_Port_2_SPT_STA5_MASK 0x00038000
-#define BCHP_SWITCH_CORE_MST_TAB_Port_2_SPT_STA5_SHIFT 15
-#define BCHP_SWITCH_CORE_MST_TAB_Port_2_SPT_STA5_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: MST_TAB_Port_2 :: SPT_STA4 [14:12] */
-#define BCHP_SWITCH_CORE_MST_TAB_Port_2_SPT_STA4_MASK 0x00007000
-#define BCHP_SWITCH_CORE_MST_TAB_Port_2_SPT_STA4_SHIFT 12
-#define BCHP_SWITCH_CORE_MST_TAB_Port_2_SPT_STA4_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: MST_TAB_Port_2 :: SPT_STA3 [11:09] */
-#define BCHP_SWITCH_CORE_MST_TAB_Port_2_SPT_STA3_MASK 0x00000e00
-#define BCHP_SWITCH_CORE_MST_TAB_Port_2_SPT_STA3_SHIFT 9
-#define BCHP_SWITCH_CORE_MST_TAB_Port_2_SPT_STA3_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: MST_TAB_Port_2 :: SPT_STA2 [08:06] */
-#define BCHP_SWITCH_CORE_MST_TAB_Port_2_SPT_STA2_MASK 0x000001c0
-#define BCHP_SWITCH_CORE_MST_TAB_Port_2_SPT_STA2_SHIFT 6
-#define BCHP_SWITCH_CORE_MST_TAB_Port_2_SPT_STA2_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: MST_TAB_Port_2 :: SPT_STA1 [05:03] */
-#define BCHP_SWITCH_CORE_MST_TAB_Port_2_SPT_STA1_MASK 0x00000038
-#define BCHP_SWITCH_CORE_MST_TAB_Port_2_SPT_STA1_SHIFT 3
-#define BCHP_SWITCH_CORE_MST_TAB_Port_2_SPT_STA1_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: MST_TAB_Port_2 :: SPT_STA0 [02:00] */
-#define BCHP_SWITCH_CORE_MST_TAB_Port_2_SPT_STA0_MASK 0x00000007
-#define BCHP_SWITCH_CORE_MST_TAB_Port_2_SPT_STA0_SHIFT 0
-#define BCHP_SWITCH_CORE_MST_TAB_Port_2_SPT_STA0_DEFAULT 0x00000000
-
-/***************************************************************************
- *MST_TAB_Port_3 - MST Table N Enable Registers
- ***************************************************************************/
-/* SWITCH_CORE :: MST_TAB_Port_3 :: MST_TAB_RSRV [31:27] */
-#define BCHP_SWITCH_CORE_MST_TAB_Port_3_MST_TAB_RSRV_MASK 0xf8000000
-#define BCHP_SWITCH_CORE_MST_TAB_Port_3_MST_TAB_RSRV_SHIFT 27
-#define BCHP_SWITCH_CORE_MST_TAB_Port_3_MST_TAB_RSRV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: MST_TAB_Port_3 :: SWITCH_RESV_1 [26:24] */
-#define BCHP_SWITCH_CORE_MST_TAB_Port_3_SWITCH_RESV_1_MASK 0x07000000
-#define BCHP_SWITCH_CORE_MST_TAB_Port_3_SWITCH_RESV_1_SHIFT 24
-#define BCHP_SWITCH_CORE_MST_TAB_Port_3_SWITCH_RESV_1_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: MST_TAB_Port_3 :: SPT_STA7 [23:21] */
-#define BCHP_SWITCH_CORE_MST_TAB_Port_3_SPT_STA7_MASK 0x00e00000
-#define BCHP_SWITCH_CORE_MST_TAB_Port_3_SPT_STA7_SHIFT 21
-#define BCHP_SWITCH_CORE_MST_TAB_Port_3_SPT_STA7_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: MST_TAB_Port_3 :: SWITCH_RESV_0 [20:18] */
-#define BCHP_SWITCH_CORE_MST_TAB_Port_3_SWITCH_RESV_0_MASK 0x001c0000
-#define BCHP_SWITCH_CORE_MST_TAB_Port_3_SWITCH_RESV_0_SHIFT 18
-#define BCHP_SWITCH_CORE_MST_TAB_Port_3_SWITCH_RESV_0_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: MST_TAB_Port_3 :: SPT_STA5 [17:15] */
-#define BCHP_SWITCH_CORE_MST_TAB_Port_3_SPT_STA5_MASK 0x00038000
-#define BCHP_SWITCH_CORE_MST_TAB_Port_3_SPT_STA5_SHIFT 15
-#define BCHP_SWITCH_CORE_MST_TAB_Port_3_SPT_STA5_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: MST_TAB_Port_3 :: SPT_STA4 [14:12] */
-#define BCHP_SWITCH_CORE_MST_TAB_Port_3_SPT_STA4_MASK 0x00007000
-#define BCHP_SWITCH_CORE_MST_TAB_Port_3_SPT_STA4_SHIFT 12
-#define BCHP_SWITCH_CORE_MST_TAB_Port_3_SPT_STA4_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: MST_TAB_Port_3 :: SPT_STA3 [11:09] */
-#define BCHP_SWITCH_CORE_MST_TAB_Port_3_SPT_STA3_MASK 0x00000e00
-#define BCHP_SWITCH_CORE_MST_TAB_Port_3_SPT_STA3_SHIFT 9
-#define BCHP_SWITCH_CORE_MST_TAB_Port_3_SPT_STA3_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: MST_TAB_Port_3 :: SPT_STA2 [08:06] */
-#define BCHP_SWITCH_CORE_MST_TAB_Port_3_SPT_STA2_MASK 0x000001c0
-#define BCHP_SWITCH_CORE_MST_TAB_Port_3_SPT_STA2_SHIFT 6
-#define BCHP_SWITCH_CORE_MST_TAB_Port_3_SPT_STA2_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: MST_TAB_Port_3 :: SPT_STA1 [05:03] */
-#define BCHP_SWITCH_CORE_MST_TAB_Port_3_SPT_STA1_MASK 0x00000038
-#define BCHP_SWITCH_CORE_MST_TAB_Port_3_SPT_STA1_SHIFT 3
-#define BCHP_SWITCH_CORE_MST_TAB_Port_3_SPT_STA1_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: MST_TAB_Port_3 :: SPT_STA0 [02:00] */
-#define BCHP_SWITCH_CORE_MST_TAB_Port_3_SPT_STA0_MASK 0x00000007
-#define BCHP_SWITCH_CORE_MST_TAB_Port_3_SPT_STA0_SHIFT 0
-#define BCHP_SWITCH_CORE_MST_TAB_Port_3_SPT_STA0_DEFAULT 0x00000000
-
-/***************************************************************************
- *MST_TAB_Port_4 - MST Table N Enable Registers
- ***************************************************************************/
-/* SWITCH_CORE :: MST_TAB_Port_4 :: MST_TAB_RSRV [31:27] */
-#define BCHP_SWITCH_CORE_MST_TAB_Port_4_MST_TAB_RSRV_MASK 0xf8000000
-#define BCHP_SWITCH_CORE_MST_TAB_Port_4_MST_TAB_RSRV_SHIFT 27
-#define BCHP_SWITCH_CORE_MST_TAB_Port_4_MST_TAB_RSRV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: MST_TAB_Port_4 :: SWITCH_RESV_1 [26:24] */
-#define BCHP_SWITCH_CORE_MST_TAB_Port_4_SWITCH_RESV_1_MASK 0x07000000
-#define BCHP_SWITCH_CORE_MST_TAB_Port_4_SWITCH_RESV_1_SHIFT 24
-#define BCHP_SWITCH_CORE_MST_TAB_Port_4_SWITCH_RESV_1_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: MST_TAB_Port_4 :: SPT_STA7 [23:21] */
-#define BCHP_SWITCH_CORE_MST_TAB_Port_4_SPT_STA7_MASK 0x00e00000
-#define BCHP_SWITCH_CORE_MST_TAB_Port_4_SPT_STA7_SHIFT 21
-#define BCHP_SWITCH_CORE_MST_TAB_Port_4_SPT_STA7_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: MST_TAB_Port_4 :: SWITCH_RESV_0 [20:18] */
-#define BCHP_SWITCH_CORE_MST_TAB_Port_4_SWITCH_RESV_0_MASK 0x001c0000
-#define BCHP_SWITCH_CORE_MST_TAB_Port_4_SWITCH_RESV_0_SHIFT 18
-#define BCHP_SWITCH_CORE_MST_TAB_Port_4_SWITCH_RESV_0_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: MST_TAB_Port_4 :: SPT_STA5 [17:15] */
-#define BCHP_SWITCH_CORE_MST_TAB_Port_4_SPT_STA5_MASK 0x00038000
-#define BCHP_SWITCH_CORE_MST_TAB_Port_4_SPT_STA5_SHIFT 15
-#define BCHP_SWITCH_CORE_MST_TAB_Port_4_SPT_STA5_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: MST_TAB_Port_4 :: SPT_STA4 [14:12] */
-#define BCHP_SWITCH_CORE_MST_TAB_Port_4_SPT_STA4_MASK 0x00007000
-#define BCHP_SWITCH_CORE_MST_TAB_Port_4_SPT_STA4_SHIFT 12
-#define BCHP_SWITCH_CORE_MST_TAB_Port_4_SPT_STA4_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: MST_TAB_Port_4 :: SPT_STA3 [11:09] */
-#define BCHP_SWITCH_CORE_MST_TAB_Port_4_SPT_STA3_MASK 0x00000e00
-#define BCHP_SWITCH_CORE_MST_TAB_Port_4_SPT_STA3_SHIFT 9
-#define BCHP_SWITCH_CORE_MST_TAB_Port_4_SPT_STA3_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: MST_TAB_Port_4 :: SPT_STA2 [08:06] */
-#define BCHP_SWITCH_CORE_MST_TAB_Port_4_SPT_STA2_MASK 0x000001c0
-#define BCHP_SWITCH_CORE_MST_TAB_Port_4_SPT_STA2_SHIFT 6
-#define BCHP_SWITCH_CORE_MST_TAB_Port_4_SPT_STA2_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: MST_TAB_Port_4 :: SPT_STA1 [05:03] */
-#define BCHP_SWITCH_CORE_MST_TAB_Port_4_SPT_STA1_MASK 0x00000038
-#define BCHP_SWITCH_CORE_MST_TAB_Port_4_SPT_STA1_SHIFT 3
-#define BCHP_SWITCH_CORE_MST_TAB_Port_4_SPT_STA1_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: MST_TAB_Port_4 :: SPT_STA0 [02:00] */
-#define BCHP_SWITCH_CORE_MST_TAB_Port_4_SPT_STA0_MASK 0x00000007
-#define BCHP_SWITCH_CORE_MST_TAB_Port_4_SPT_STA0_SHIFT 0
-#define BCHP_SWITCH_CORE_MST_TAB_Port_4_SPT_STA0_DEFAULT 0x00000000
-
-/***************************************************************************
- *MST_TAB_Port_5 - MST Table N Enable Registers
- ***************************************************************************/
-/* SWITCH_CORE :: MST_TAB_Port_5 :: MST_TAB_RSRV [31:27] */
-#define BCHP_SWITCH_CORE_MST_TAB_Port_5_MST_TAB_RSRV_MASK 0xf8000000
-#define BCHP_SWITCH_CORE_MST_TAB_Port_5_MST_TAB_RSRV_SHIFT 27
-#define BCHP_SWITCH_CORE_MST_TAB_Port_5_MST_TAB_RSRV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: MST_TAB_Port_5 :: SWITCH_RESV_1 [26:24] */
-#define BCHP_SWITCH_CORE_MST_TAB_Port_5_SWITCH_RESV_1_MASK 0x07000000
-#define BCHP_SWITCH_CORE_MST_TAB_Port_5_SWITCH_RESV_1_SHIFT 24
-#define BCHP_SWITCH_CORE_MST_TAB_Port_5_SWITCH_RESV_1_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: MST_TAB_Port_5 :: SPT_STA7 [23:21] */
-#define BCHP_SWITCH_CORE_MST_TAB_Port_5_SPT_STA7_MASK 0x00e00000
-#define BCHP_SWITCH_CORE_MST_TAB_Port_5_SPT_STA7_SHIFT 21
-#define BCHP_SWITCH_CORE_MST_TAB_Port_5_SPT_STA7_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: MST_TAB_Port_5 :: SWITCH_RESV_0 [20:18] */
-#define BCHP_SWITCH_CORE_MST_TAB_Port_5_SWITCH_RESV_0_MASK 0x001c0000
-#define BCHP_SWITCH_CORE_MST_TAB_Port_5_SWITCH_RESV_0_SHIFT 18
-#define BCHP_SWITCH_CORE_MST_TAB_Port_5_SWITCH_RESV_0_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: MST_TAB_Port_5 :: SPT_STA5 [17:15] */
-#define BCHP_SWITCH_CORE_MST_TAB_Port_5_SPT_STA5_MASK 0x00038000
-#define BCHP_SWITCH_CORE_MST_TAB_Port_5_SPT_STA5_SHIFT 15
-#define BCHP_SWITCH_CORE_MST_TAB_Port_5_SPT_STA5_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: MST_TAB_Port_5 :: SPT_STA4 [14:12] */
-#define BCHP_SWITCH_CORE_MST_TAB_Port_5_SPT_STA4_MASK 0x00007000
-#define BCHP_SWITCH_CORE_MST_TAB_Port_5_SPT_STA4_SHIFT 12
-#define BCHP_SWITCH_CORE_MST_TAB_Port_5_SPT_STA4_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: MST_TAB_Port_5 :: SPT_STA3 [11:09] */
-#define BCHP_SWITCH_CORE_MST_TAB_Port_5_SPT_STA3_MASK 0x00000e00
-#define BCHP_SWITCH_CORE_MST_TAB_Port_5_SPT_STA3_SHIFT 9
-#define BCHP_SWITCH_CORE_MST_TAB_Port_5_SPT_STA3_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: MST_TAB_Port_5 :: SPT_STA2 [08:06] */
-#define BCHP_SWITCH_CORE_MST_TAB_Port_5_SPT_STA2_MASK 0x000001c0
-#define BCHP_SWITCH_CORE_MST_TAB_Port_5_SPT_STA2_SHIFT 6
-#define BCHP_SWITCH_CORE_MST_TAB_Port_5_SPT_STA2_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: MST_TAB_Port_5 :: SPT_STA1 [05:03] */
-#define BCHP_SWITCH_CORE_MST_TAB_Port_5_SPT_STA1_MASK 0x00000038
-#define BCHP_SWITCH_CORE_MST_TAB_Port_5_SPT_STA1_SHIFT 3
-#define BCHP_SWITCH_CORE_MST_TAB_Port_5_SPT_STA1_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: MST_TAB_Port_5 :: SPT_STA0 [02:00] */
-#define BCHP_SWITCH_CORE_MST_TAB_Port_5_SPT_STA0_MASK 0x00000007
-#define BCHP_SWITCH_CORE_MST_TAB_Port_5_SPT_STA0_SHIFT 0
-#define BCHP_SWITCH_CORE_MST_TAB_Port_5_SPT_STA0_DEFAULT 0x00000000
-
-/***************************************************************************
- *MST_TAB_Port_6 - MST Table N Enable Registers
- ***************************************************************************/
-/* SWITCH_CORE :: MST_TAB_Port_6 :: MST_TAB_RSRV [31:27] */
-#define BCHP_SWITCH_CORE_MST_TAB_Port_6_MST_TAB_RSRV_MASK 0xf8000000
-#define BCHP_SWITCH_CORE_MST_TAB_Port_6_MST_TAB_RSRV_SHIFT 27
-#define BCHP_SWITCH_CORE_MST_TAB_Port_6_MST_TAB_RSRV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: MST_TAB_Port_6 :: SWITCH_RESV_1 [26:24] */
-#define BCHP_SWITCH_CORE_MST_TAB_Port_6_SWITCH_RESV_1_MASK 0x07000000
-#define BCHP_SWITCH_CORE_MST_TAB_Port_6_SWITCH_RESV_1_SHIFT 24
-#define BCHP_SWITCH_CORE_MST_TAB_Port_6_SWITCH_RESV_1_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: MST_TAB_Port_6 :: SPT_STA7 [23:21] */
-#define BCHP_SWITCH_CORE_MST_TAB_Port_6_SPT_STA7_MASK 0x00e00000
-#define BCHP_SWITCH_CORE_MST_TAB_Port_6_SPT_STA7_SHIFT 21
-#define BCHP_SWITCH_CORE_MST_TAB_Port_6_SPT_STA7_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: MST_TAB_Port_6 :: SWITCH_RESV_0 [20:18] */
-#define BCHP_SWITCH_CORE_MST_TAB_Port_6_SWITCH_RESV_0_MASK 0x001c0000
-#define BCHP_SWITCH_CORE_MST_TAB_Port_6_SWITCH_RESV_0_SHIFT 18
-#define BCHP_SWITCH_CORE_MST_TAB_Port_6_SWITCH_RESV_0_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: MST_TAB_Port_6 :: SPT_STA5 [17:15] */
-#define BCHP_SWITCH_CORE_MST_TAB_Port_6_SPT_STA5_MASK 0x00038000
-#define BCHP_SWITCH_CORE_MST_TAB_Port_6_SPT_STA5_SHIFT 15
-#define BCHP_SWITCH_CORE_MST_TAB_Port_6_SPT_STA5_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: MST_TAB_Port_6 :: SPT_STA4 [14:12] */
-#define BCHP_SWITCH_CORE_MST_TAB_Port_6_SPT_STA4_MASK 0x00007000
-#define BCHP_SWITCH_CORE_MST_TAB_Port_6_SPT_STA4_SHIFT 12
-#define BCHP_SWITCH_CORE_MST_TAB_Port_6_SPT_STA4_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: MST_TAB_Port_6 :: SPT_STA3 [11:09] */
-#define BCHP_SWITCH_CORE_MST_TAB_Port_6_SPT_STA3_MASK 0x00000e00
-#define BCHP_SWITCH_CORE_MST_TAB_Port_6_SPT_STA3_SHIFT 9
-#define BCHP_SWITCH_CORE_MST_TAB_Port_6_SPT_STA3_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: MST_TAB_Port_6 :: SPT_STA2 [08:06] */
-#define BCHP_SWITCH_CORE_MST_TAB_Port_6_SPT_STA2_MASK 0x000001c0
-#define BCHP_SWITCH_CORE_MST_TAB_Port_6_SPT_STA2_SHIFT 6
-#define BCHP_SWITCH_CORE_MST_TAB_Port_6_SPT_STA2_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: MST_TAB_Port_6 :: SPT_STA1 [05:03] */
-#define BCHP_SWITCH_CORE_MST_TAB_Port_6_SPT_STA1_MASK 0x00000038
-#define BCHP_SWITCH_CORE_MST_TAB_Port_6_SPT_STA1_SHIFT 3
-#define BCHP_SWITCH_CORE_MST_TAB_Port_6_SPT_STA1_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: MST_TAB_Port_6 :: SPT_STA0 [02:00] */
-#define BCHP_SWITCH_CORE_MST_TAB_Port_6_SPT_STA0_MASK 0x00000007
-#define BCHP_SWITCH_CORE_MST_TAB_Port_6_SPT_STA0_SHIFT 0
-#define BCHP_SWITCH_CORE_MST_TAB_Port_6_SPT_STA0_DEFAULT 0x00000000
-
-/***************************************************************************
- *MST_TAB_Port_7 - MST Table N Enable Registers
- ***************************************************************************/
-/* SWITCH_CORE :: MST_TAB_Port_7 :: MST_TAB_RSRV [31:27] */
-#define BCHP_SWITCH_CORE_MST_TAB_Port_7_MST_TAB_RSRV_MASK 0xf8000000
-#define BCHP_SWITCH_CORE_MST_TAB_Port_7_MST_TAB_RSRV_SHIFT 27
-#define BCHP_SWITCH_CORE_MST_TAB_Port_7_MST_TAB_RSRV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: MST_TAB_Port_7 :: SWITCH_RESV_1 [26:24] */
-#define BCHP_SWITCH_CORE_MST_TAB_Port_7_SWITCH_RESV_1_MASK 0x07000000
-#define BCHP_SWITCH_CORE_MST_TAB_Port_7_SWITCH_RESV_1_SHIFT 24
-#define BCHP_SWITCH_CORE_MST_TAB_Port_7_SWITCH_RESV_1_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: MST_TAB_Port_7 :: SPT_STA7 [23:21] */
-#define BCHP_SWITCH_CORE_MST_TAB_Port_7_SPT_STA7_MASK 0x00e00000
-#define BCHP_SWITCH_CORE_MST_TAB_Port_7_SPT_STA7_SHIFT 21
-#define BCHP_SWITCH_CORE_MST_TAB_Port_7_SPT_STA7_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: MST_TAB_Port_7 :: SWITCH_RESV_0 [20:18] */
-#define BCHP_SWITCH_CORE_MST_TAB_Port_7_SWITCH_RESV_0_MASK 0x001c0000
-#define BCHP_SWITCH_CORE_MST_TAB_Port_7_SWITCH_RESV_0_SHIFT 18
-#define BCHP_SWITCH_CORE_MST_TAB_Port_7_SWITCH_RESV_0_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: MST_TAB_Port_7 :: SPT_STA5 [17:15] */
-#define BCHP_SWITCH_CORE_MST_TAB_Port_7_SPT_STA5_MASK 0x00038000
-#define BCHP_SWITCH_CORE_MST_TAB_Port_7_SPT_STA5_SHIFT 15
-#define BCHP_SWITCH_CORE_MST_TAB_Port_7_SPT_STA5_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: MST_TAB_Port_7 :: SPT_STA4 [14:12] */
-#define BCHP_SWITCH_CORE_MST_TAB_Port_7_SPT_STA4_MASK 0x00007000
-#define BCHP_SWITCH_CORE_MST_TAB_Port_7_SPT_STA4_SHIFT 12
-#define BCHP_SWITCH_CORE_MST_TAB_Port_7_SPT_STA4_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: MST_TAB_Port_7 :: SPT_STA3 [11:09] */
-#define BCHP_SWITCH_CORE_MST_TAB_Port_7_SPT_STA3_MASK 0x00000e00
-#define BCHP_SWITCH_CORE_MST_TAB_Port_7_SPT_STA3_SHIFT 9
-#define BCHP_SWITCH_CORE_MST_TAB_Port_7_SPT_STA3_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: MST_TAB_Port_7 :: SPT_STA2 [08:06] */
-#define BCHP_SWITCH_CORE_MST_TAB_Port_7_SPT_STA2_MASK 0x000001c0
-#define BCHP_SWITCH_CORE_MST_TAB_Port_7_SPT_STA2_SHIFT 6
-#define BCHP_SWITCH_CORE_MST_TAB_Port_7_SPT_STA2_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: MST_TAB_Port_7 :: SPT_STA1 [05:03] */
-#define BCHP_SWITCH_CORE_MST_TAB_Port_7_SPT_STA1_MASK 0x00000038
-#define BCHP_SWITCH_CORE_MST_TAB_Port_7_SPT_STA1_SHIFT 3
-#define BCHP_SWITCH_CORE_MST_TAB_Port_7_SPT_STA1_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: MST_TAB_Port_7 :: SPT_STA0 [02:00] */
-#define BCHP_SWITCH_CORE_MST_TAB_Port_7_SPT_STA0_MASK 0x00000007
-#define BCHP_SWITCH_CORE_MST_TAB_Port_7_SPT_STA0_SHIFT 0
-#define BCHP_SWITCH_CORE_MST_TAB_Port_7_SPT_STA0_DEFAULT 0x00000000
-
-/***************************************************************************
- *SPT_MULTI_ADDR_BPS_CTRL - STP Multiport Address Bypass Control Register
- ***************************************************************************/
-/* SWITCH_CORE :: SPT_MULTI_ADDR_BPS_CTRL :: reserved_for_padding0 [31:16] */
-#define BCHP_SWITCH_CORE_SPT_MULTI_ADDR_BPS_CTRL_reserved_for_padding0_MASK 0xffff0000
-#define BCHP_SWITCH_CORE_SPT_MULTI_ADDR_BPS_CTRL_reserved_for_padding0_SHIFT 16
-
-/* SWITCH_CORE :: SPT_MULTI_ADDR_BPS_CTRL :: SWITCH_RESV [15:06] */
-#define BCHP_SWITCH_CORE_SPT_MULTI_ADDR_BPS_CTRL_SWITCH_RESV_MASK 0x0000ffc0
-#define BCHP_SWITCH_CORE_SPT_MULTI_ADDR_BPS_CTRL_SWITCH_RESV_SHIFT 6
-#define BCHP_SWITCH_CORE_SPT_MULTI_ADDR_BPS_CTRL_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: SPT_MULTI_ADDR_BPS_CTRL :: EN_MPORT5_BYPASS_SPT [05:05] */
-#define BCHP_SWITCH_CORE_SPT_MULTI_ADDR_BPS_CTRL_EN_MPORT5_BYPASS_SPT_MASK 0x00000020
-#define BCHP_SWITCH_CORE_SPT_MULTI_ADDR_BPS_CTRL_EN_MPORT5_BYPASS_SPT_SHIFT 5
-#define BCHP_SWITCH_CORE_SPT_MULTI_ADDR_BPS_CTRL_EN_MPORT5_BYPASS_SPT_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: SPT_MULTI_ADDR_BPS_CTRL :: EN_MPORT4_BYPASS_SPT [04:04] */
-#define BCHP_SWITCH_CORE_SPT_MULTI_ADDR_BPS_CTRL_EN_MPORT4_BYPASS_SPT_MASK 0x00000010
-#define BCHP_SWITCH_CORE_SPT_MULTI_ADDR_BPS_CTRL_EN_MPORT4_BYPASS_SPT_SHIFT 4
-#define BCHP_SWITCH_CORE_SPT_MULTI_ADDR_BPS_CTRL_EN_MPORT4_BYPASS_SPT_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: SPT_MULTI_ADDR_BPS_CTRL :: EN_MPORT3_BYPASS_SPT [03:03] */
-#define BCHP_SWITCH_CORE_SPT_MULTI_ADDR_BPS_CTRL_EN_MPORT3_BYPASS_SPT_MASK 0x00000008
-#define BCHP_SWITCH_CORE_SPT_MULTI_ADDR_BPS_CTRL_EN_MPORT3_BYPASS_SPT_SHIFT 3
-#define BCHP_SWITCH_CORE_SPT_MULTI_ADDR_BPS_CTRL_EN_MPORT3_BYPASS_SPT_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: SPT_MULTI_ADDR_BPS_CTRL :: EN_MPORT2_BYPASS_SPT [02:02] */
-#define BCHP_SWITCH_CORE_SPT_MULTI_ADDR_BPS_CTRL_EN_MPORT2_BYPASS_SPT_MASK 0x00000004
-#define BCHP_SWITCH_CORE_SPT_MULTI_ADDR_BPS_CTRL_EN_MPORT2_BYPASS_SPT_SHIFT 2
-#define BCHP_SWITCH_CORE_SPT_MULTI_ADDR_BPS_CTRL_EN_MPORT2_BYPASS_SPT_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: SPT_MULTI_ADDR_BPS_CTRL :: EN_MPORT1_BYPASS_SPT [01:01] */
-#define BCHP_SWITCH_CORE_SPT_MULTI_ADDR_BPS_CTRL_EN_MPORT1_BYPASS_SPT_MASK 0x00000002
-#define BCHP_SWITCH_CORE_SPT_MULTI_ADDR_BPS_CTRL_EN_MPORT1_BYPASS_SPT_SHIFT 1
-#define BCHP_SWITCH_CORE_SPT_MULTI_ADDR_BPS_CTRL_EN_MPORT1_BYPASS_SPT_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: SPT_MULTI_ADDR_BPS_CTRL :: EN_MPORT0_BYPASS_SPT [00:00] */
-#define BCHP_SWITCH_CORE_SPT_MULTI_ADDR_BPS_CTRL_EN_MPORT0_BYPASS_SPT_MASK 0x00000001
-#define BCHP_SWITCH_CORE_SPT_MULTI_ADDR_BPS_CTRL_EN_MPORT0_BYPASS_SPT_SHIFT 0
-#define BCHP_SWITCH_CORE_SPT_MULTI_ADDR_BPS_CTRL_EN_MPORT0_BYPASS_SPT_DEFAULT 0x00000000
-
-/***************************************************************************
- *IEEE8021S_REG_SPARE0 - Spare 0 Register (Not2Release)
- ***************************************************************************/
-/* SWITCH_CORE :: IEEE8021S_REG_SPARE0 :: IEEE8021S_REG_SPARE0 [31:00] */
-#define BCHP_SWITCH_CORE_IEEE8021S_REG_SPARE0_IEEE8021S_REG_SPARE0_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_IEEE8021S_REG_SPARE0_IEEE8021S_REG_SPARE0_SHIFT 0
-#define BCHP_SWITCH_CORE_IEEE8021S_REG_SPARE0_IEEE8021S_REG_SPARE0_DEFAULT 0x00000000
-
-/***************************************************************************
- *IEEE8021S_REG_SPARE1 - Spare 1 Register (Not2Release)
- ***************************************************************************/
-/* SWITCH_CORE :: IEEE8021S_REG_SPARE1 :: IEEE8021S_REG_SPARE1 [31:00] */
-#define BCHP_SWITCH_CORE_IEEE8021S_REG_SPARE1_IEEE8021S_REG_SPARE1_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_IEEE8021S_REG_SPARE1_IEEE8021S_REG_SPARE1_SHIFT 0
-#define BCHP_SWITCH_CORE_IEEE8021S_REG_SPARE1_IEEE8021S_REG_SPARE1_DEFAULT 0x00000000
-
-/***************************************************************************
- *SA_LIMIT_ENABLE - SA Limit Enable Register
- ***************************************************************************/
-/* SWITCH_CORE :: SA_LIMIT_ENABLE :: reserved_for_padding0 [31:16] */
-#define BCHP_SWITCH_CORE_SA_LIMIT_ENABLE_reserved_for_padding0_MASK 0xffff0000
-#define BCHP_SWITCH_CORE_SA_LIMIT_ENABLE_reserved_for_padding0_SHIFT 16
-
-/* SWITCH_CORE :: SA_LIMIT_ENABLE :: SWITCH_RESV [15:09] */
-#define BCHP_SWITCH_CORE_SA_LIMIT_ENABLE_SWITCH_RESV_MASK 0x0000fe00
-#define BCHP_SWITCH_CORE_SA_LIMIT_ENABLE_SWITCH_RESV_SHIFT 9
-#define BCHP_SWITCH_CORE_SA_LIMIT_ENABLE_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: SA_LIMIT_ENABLE :: SA_LIMIT_EN [08:00] */
-#define BCHP_SWITCH_CORE_SA_LIMIT_ENABLE_SA_LIMIT_EN_MASK 0x000001ff
-#define BCHP_SWITCH_CORE_SA_LIMIT_ENABLE_SA_LIMIT_EN_SHIFT 0
-#define BCHP_SWITCH_CORE_SA_LIMIT_ENABLE_SA_LIMIT_EN_DEFAULT 0x00000000
-
-/***************************************************************************
- *SA_LRN_CNTR_RST - SA Learned Counters Reset Register
- ***************************************************************************/
-/* SWITCH_CORE :: SA_LRN_CNTR_RST :: reserved_for_padding0 [31:16] */
-#define BCHP_SWITCH_CORE_SA_LRN_CNTR_RST_reserved_for_padding0_MASK 0xffff0000
-#define BCHP_SWITCH_CORE_SA_LRN_CNTR_RST_reserved_for_padding0_SHIFT 16
-
-/* SWITCH_CORE :: SA_LRN_CNTR_RST :: TOTAL_SA_LRN_CNTR_RST [15:15] */
-#define BCHP_SWITCH_CORE_SA_LRN_CNTR_RST_TOTAL_SA_LRN_CNTR_RST_MASK 0x00008000
-#define BCHP_SWITCH_CORE_SA_LRN_CNTR_RST_TOTAL_SA_LRN_CNTR_RST_SHIFT 15
-#define BCHP_SWITCH_CORE_SA_LRN_CNTR_RST_TOTAL_SA_LRN_CNTR_RST_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: SA_LRN_CNTR_RST :: SWITCH_RESV [14:09] */
-#define BCHP_SWITCH_CORE_SA_LRN_CNTR_RST_SWITCH_RESV_MASK 0x00007e00
-#define BCHP_SWITCH_CORE_SA_LRN_CNTR_RST_SWITCH_RESV_SHIFT 9
-#define BCHP_SWITCH_CORE_SA_LRN_CNTR_RST_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: SA_LRN_CNTR_RST :: PORT_SA_LRN_CNTR_RST [08:00] */
-#define BCHP_SWITCH_CORE_SA_LRN_CNTR_RST_PORT_SA_LRN_CNTR_RST_MASK 0x000001ff
-#define BCHP_SWITCH_CORE_SA_LRN_CNTR_RST_PORT_SA_LRN_CNTR_RST_SHIFT 0
-#define BCHP_SWITCH_CORE_SA_LRN_CNTR_RST_PORT_SA_LRN_CNTR_RST_DEFAULT 0x00000000
-
-/***************************************************************************
- *SA_OVERLIMIT_CNTR_RST - SA Over Limit Counters Reset Register
- ***************************************************************************/
-/* SWITCH_CORE :: SA_OVERLIMIT_CNTR_RST :: reserved_for_padding0 [31:16] */
-#define BCHP_SWITCH_CORE_SA_OVERLIMIT_CNTR_RST_reserved_for_padding0_MASK 0xffff0000
-#define BCHP_SWITCH_CORE_SA_OVERLIMIT_CNTR_RST_reserved_for_padding0_SHIFT 16
-
-/* SWITCH_CORE :: SA_OVERLIMIT_CNTR_RST :: SWITCH_RESV [15:09] */
-#define BCHP_SWITCH_CORE_SA_OVERLIMIT_CNTR_RST_SWITCH_RESV_MASK 0x0000fe00
-#define BCHP_SWITCH_CORE_SA_OVERLIMIT_CNTR_RST_SWITCH_RESV_SHIFT 9
-#define BCHP_SWITCH_CORE_SA_OVERLIMIT_CNTR_RST_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: SA_OVERLIMIT_CNTR_RST :: PORT_SA_OVER_LIMIT_CNTR_RST [08:00] */
-#define BCHP_SWITCH_CORE_SA_OVERLIMIT_CNTR_RST_PORT_SA_OVER_LIMIT_CNTR_RST_MASK 0x000001ff
-#define BCHP_SWITCH_CORE_SA_OVERLIMIT_CNTR_RST_PORT_SA_OVER_LIMIT_CNTR_RST_SHIFT 0
-#define BCHP_SWITCH_CORE_SA_OVERLIMIT_CNTR_RST_PORT_SA_OVER_LIMIT_CNTR_RST_DEFAULT 0x00000000
-
-/***************************************************************************
- *TOTAL_SA_LIMIT_CTL - Total SA Limit Control Register
- ***************************************************************************/
-/* SWITCH_CORE :: TOTAL_SA_LIMIT_CTL :: reserved_for_padding0 [31:16] */
-#define BCHP_SWITCH_CORE_TOTAL_SA_LIMIT_CTL_reserved_for_padding0_MASK 0xffff0000
-#define BCHP_SWITCH_CORE_TOTAL_SA_LIMIT_CTL_reserved_for_padding0_SHIFT 16
-
-/* SWITCH_CORE :: TOTAL_SA_LIMIT_CTL :: SWITCH_RESV [15:13] */
-#define BCHP_SWITCH_CORE_TOTAL_SA_LIMIT_CTL_SWITCH_RESV_MASK 0x0000e000
-#define BCHP_SWITCH_CORE_TOTAL_SA_LIMIT_CTL_SWITCH_RESV_SHIFT 13
-#define BCHP_SWITCH_CORE_TOTAL_SA_LIMIT_CTL_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: TOTAL_SA_LIMIT_CTL :: TOTAL_SA_LRN_CNT_LIM [12:00] */
-#define BCHP_SWITCH_CORE_TOTAL_SA_LIMIT_CTL_TOTAL_SA_LRN_CNT_LIM_MASK 0x00001fff
-#define BCHP_SWITCH_CORE_TOTAL_SA_LIMIT_CTL_TOTAL_SA_LRN_CNT_LIM_SHIFT 0
-#define BCHP_SWITCH_CORE_TOTAL_SA_LIMIT_CTL_TOTAL_SA_LRN_CNT_LIM_DEFAULT 0x00001000
-
-/***************************************************************************
- *PORT_N_SA_LIMIT_CTL_Port_0 - Port N SA Limit Control Register
- ***************************************************************************/
-/* SWITCH_CORE :: PORT_N_SA_LIMIT_CTL_Port_0 :: reserved_for_padding0 [31:16] */
-#define BCHP_SWITCH_CORE_PORT_N_SA_LIMIT_CTL_Port_0_reserved_for_padding0_MASK 0xffff0000
-#define BCHP_SWITCH_CORE_PORT_N_SA_LIMIT_CTL_Port_0_reserved_for_padding0_SHIFT 16
-
-/* SWITCH_CORE :: PORT_N_SA_LIMIT_CTL_Port_0 :: OVER_LIMIT_ACTIONS [15:14] */
-#define BCHP_SWITCH_CORE_PORT_N_SA_LIMIT_CTL_Port_0_OVER_LIMIT_ACTIONS_MASK 0x0000c000
-#define BCHP_SWITCH_CORE_PORT_N_SA_LIMIT_CTL_Port_0_OVER_LIMIT_ACTIONS_SHIFT 14
-#define BCHP_SWITCH_CORE_PORT_N_SA_LIMIT_CTL_Port_0_OVER_LIMIT_ACTIONS_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: PORT_N_SA_LIMIT_CTL_Port_0 :: SWITCH_RESV [13:13] */
-#define BCHP_SWITCH_CORE_PORT_N_SA_LIMIT_CTL_Port_0_SWITCH_RESV_MASK 0x00002000
-#define BCHP_SWITCH_CORE_PORT_N_SA_LIMIT_CTL_Port_0_SWITCH_RESV_SHIFT 13
-#define BCHP_SWITCH_CORE_PORT_N_SA_LIMIT_CTL_Port_0_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: PORT_N_SA_LIMIT_CTL_Port_0 :: SA_LRN_CNT_LIM [12:00] */
-#define BCHP_SWITCH_CORE_PORT_N_SA_LIMIT_CTL_Port_0_SA_LRN_CNT_LIM_MASK 0x00001fff
-#define BCHP_SWITCH_CORE_PORT_N_SA_LIMIT_CTL_Port_0_SA_LRN_CNT_LIM_SHIFT 0
-#define BCHP_SWITCH_CORE_PORT_N_SA_LIMIT_CTL_Port_0_SA_LRN_CNT_LIM_DEFAULT 0x00000400
-
-/***************************************************************************
- *PORT_N_SA_LIMIT_CTL_Port_1 - Port N SA Limit Control Register
- ***************************************************************************/
-/* SWITCH_CORE :: PORT_N_SA_LIMIT_CTL_Port_1 :: reserved_for_padding0 [31:16] */
-#define BCHP_SWITCH_CORE_PORT_N_SA_LIMIT_CTL_Port_1_reserved_for_padding0_MASK 0xffff0000
-#define BCHP_SWITCH_CORE_PORT_N_SA_LIMIT_CTL_Port_1_reserved_for_padding0_SHIFT 16
-
-/* SWITCH_CORE :: PORT_N_SA_LIMIT_CTL_Port_1 :: OVER_LIMIT_ACTIONS [15:14] */
-#define BCHP_SWITCH_CORE_PORT_N_SA_LIMIT_CTL_Port_1_OVER_LIMIT_ACTIONS_MASK 0x0000c000
-#define BCHP_SWITCH_CORE_PORT_N_SA_LIMIT_CTL_Port_1_OVER_LIMIT_ACTIONS_SHIFT 14
-#define BCHP_SWITCH_CORE_PORT_N_SA_LIMIT_CTL_Port_1_OVER_LIMIT_ACTIONS_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: PORT_N_SA_LIMIT_CTL_Port_1 :: SWITCH_RESV [13:13] */
-#define BCHP_SWITCH_CORE_PORT_N_SA_LIMIT_CTL_Port_1_SWITCH_RESV_MASK 0x00002000
-#define BCHP_SWITCH_CORE_PORT_N_SA_LIMIT_CTL_Port_1_SWITCH_RESV_SHIFT 13
-#define BCHP_SWITCH_CORE_PORT_N_SA_LIMIT_CTL_Port_1_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: PORT_N_SA_LIMIT_CTL_Port_1 :: SA_LRN_CNT_LIM [12:00] */
-#define BCHP_SWITCH_CORE_PORT_N_SA_LIMIT_CTL_Port_1_SA_LRN_CNT_LIM_MASK 0x00001fff
-#define BCHP_SWITCH_CORE_PORT_N_SA_LIMIT_CTL_Port_1_SA_LRN_CNT_LIM_SHIFT 0
-#define BCHP_SWITCH_CORE_PORT_N_SA_LIMIT_CTL_Port_1_SA_LRN_CNT_LIM_DEFAULT 0x00000400
-
-/***************************************************************************
- *PORT_N_SA_LIMIT_CTL_Port_2 - Port N SA Limit Control Register
- ***************************************************************************/
-/* SWITCH_CORE :: PORT_N_SA_LIMIT_CTL_Port_2 :: reserved_for_padding0 [31:16] */
-#define BCHP_SWITCH_CORE_PORT_N_SA_LIMIT_CTL_Port_2_reserved_for_padding0_MASK 0xffff0000
-#define BCHP_SWITCH_CORE_PORT_N_SA_LIMIT_CTL_Port_2_reserved_for_padding0_SHIFT 16
-
-/* SWITCH_CORE :: PORT_N_SA_LIMIT_CTL_Port_2 :: OVER_LIMIT_ACTIONS [15:14] */
-#define BCHP_SWITCH_CORE_PORT_N_SA_LIMIT_CTL_Port_2_OVER_LIMIT_ACTIONS_MASK 0x0000c000
-#define BCHP_SWITCH_CORE_PORT_N_SA_LIMIT_CTL_Port_2_OVER_LIMIT_ACTIONS_SHIFT 14
-#define BCHP_SWITCH_CORE_PORT_N_SA_LIMIT_CTL_Port_2_OVER_LIMIT_ACTIONS_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: PORT_N_SA_LIMIT_CTL_Port_2 :: SWITCH_RESV [13:13] */
-#define BCHP_SWITCH_CORE_PORT_N_SA_LIMIT_CTL_Port_2_SWITCH_RESV_MASK 0x00002000
-#define BCHP_SWITCH_CORE_PORT_N_SA_LIMIT_CTL_Port_2_SWITCH_RESV_SHIFT 13
-#define BCHP_SWITCH_CORE_PORT_N_SA_LIMIT_CTL_Port_2_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: PORT_N_SA_LIMIT_CTL_Port_2 :: SA_LRN_CNT_LIM [12:00] */
-#define BCHP_SWITCH_CORE_PORT_N_SA_LIMIT_CTL_Port_2_SA_LRN_CNT_LIM_MASK 0x00001fff
-#define BCHP_SWITCH_CORE_PORT_N_SA_LIMIT_CTL_Port_2_SA_LRN_CNT_LIM_SHIFT 0
-#define BCHP_SWITCH_CORE_PORT_N_SA_LIMIT_CTL_Port_2_SA_LRN_CNT_LIM_DEFAULT 0x00000400
-
-/***************************************************************************
- *PORT_N_SA_LIMIT_CTL_Port_3 - Port N SA Limit Control Register
- ***************************************************************************/
-/* SWITCH_CORE :: PORT_N_SA_LIMIT_CTL_Port_3 :: reserved_for_padding0 [31:16] */
-#define BCHP_SWITCH_CORE_PORT_N_SA_LIMIT_CTL_Port_3_reserved_for_padding0_MASK 0xffff0000
-#define BCHP_SWITCH_CORE_PORT_N_SA_LIMIT_CTL_Port_3_reserved_for_padding0_SHIFT 16
-
-/* SWITCH_CORE :: PORT_N_SA_LIMIT_CTL_Port_3 :: OVER_LIMIT_ACTIONS [15:14] */
-#define BCHP_SWITCH_CORE_PORT_N_SA_LIMIT_CTL_Port_3_OVER_LIMIT_ACTIONS_MASK 0x0000c000
-#define BCHP_SWITCH_CORE_PORT_N_SA_LIMIT_CTL_Port_3_OVER_LIMIT_ACTIONS_SHIFT 14
-#define BCHP_SWITCH_CORE_PORT_N_SA_LIMIT_CTL_Port_3_OVER_LIMIT_ACTIONS_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: PORT_N_SA_LIMIT_CTL_Port_3 :: SWITCH_RESV [13:13] */
-#define BCHP_SWITCH_CORE_PORT_N_SA_LIMIT_CTL_Port_3_SWITCH_RESV_MASK 0x00002000
-#define BCHP_SWITCH_CORE_PORT_N_SA_LIMIT_CTL_Port_3_SWITCH_RESV_SHIFT 13
-#define BCHP_SWITCH_CORE_PORT_N_SA_LIMIT_CTL_Port_3_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: PORT_N_SA_LIMIT_CTL_Port_3 :: SA_LRN_CNT_LIM [12:00] */
-#define BCHP_SWITCH_CORE_PORT_N_SA_LIMIT_CTL_Port_3_SA_LRN_CNT_LIM_MASK 0x00001fff
-#define BCHP_SWITCH_CORE_PORT_N_SA_LIMIT_CTL_Port_3_SA_LRN_CNT_LIM_SHIFT 0
-#define BCHP_SWITCH_CORE_PORT_N_SA_LIMIT_CTL_Port_3_SA_LRN_CNT_LIM_DEFAULT 0x00000400
-
-/***************************************************************************
- *PORT_N_SA_LIMIT_CTL_Port_4 - Port N SA Limit Control Register
- ***************************************************************************/
-/* SWITCH_CORE :: PORT_N_SA_LIMIT_CTL_Port_4 :: reserved_for_padding0 [31:16] */
-#define BCHP_SWITCH_CORE_PORT_N_SA_LIMIT_CTL_Port_4_reserved_for_padding0_MASK 0xffff0000
-#define BCHP_SWITCH_CORE_PORT_N_SA_LIMIT_CTL_Port_4_reserved_for_padding0_SHIFT 16
-
-/* SWITCH_CORE :: PORT_N_SA_LIMIT_CTL_Port_4 :: OVER_LIMIT_ACTIONS [15:14] */
-#define BCHP_SWITCH_CORE_PORT_N_SA_LIMIT_CTL_Port_4_OVER_LIMIT_ACTIONS_MASK 0x0000c000
-#define BCHP_SWITCH_CORE_PORT_N_SA_LIMIT_CTL_Port_4_OVER_LIMIT_ACTIONS_SHIFT 14
-#define BCHP_SWITCH_CORE_PORT_N_SA_LIMIT_CTL_Port_4_OVER_LIMIT_ACTIONS_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: PORT_N_SA_LIMIT_CTL_Port_4 :: SWITCH_RESV [13:13] */
-#define BCHP_SWITCH_CORE_PORT_N_SA_LIMIT_CTL_Port_4_SWITCH_RESV_MASK 0x00002000
-#define BCHP_SWITCH_CORE_PORT_N_SA_LIMIT_CTL_Port_4_SWITCH_RESV_SHIFT 13
-#define BCHP_SWITCH_CORE_PORT_N_SA_LIMIT_CTL_Port_4_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: PORT_N_SA_LIMIT_CTL_Port_4 :: SA_LRN_CNT_LIM [12:00] */
-#define BCHP_SWITCH_CORE_PORT_N_SA_LIMIT_CTL_Port_4_SA_LRN_CNT_LIM_MASK 0x00001fff
-#define BCHP_SWITCH_CORE_PORT_N_SA_LIMIT_CTL_Port_4_SA_LRN_CNT_LIM_SHIFT 0
-#define BCHP_SWITCH_CORE_PORT_N_SA_LIMIT_CTL_Port_4_SA_LRN_CNT_LIM_DEFAULT 0x00000400
-
-/***************************************************************************
- *PORT_N_SA_LIMIT_CTL_Port_5 - Port N SA Limit Control Register
- ***************************************************************************/
-/* SWITCH_CORE :: PORT_N_SA_LIMIT_CTL_Port_5 :: reserved_for_padding0 [31:16] */
-#define BCHP_SWITCH_CORE_PORT_N_SA_LIMIT_CTL_Port_5_reserved_for_padding0_MASK 0xffff0000
-#define BCHP_SWITCH_CORE_PORT_N_SA_LIMIT_CTL_Port_5_reserved_for_padding0_SHIFT 16
-
-/* SWITCH_CORE :: PORT_N_SA_LIMIT_CTL_Port_5 :: OVER_LIMIT_ACTIONS [15:14] */
-#define BCHP_SWITCH_CORE_PORT_N_SA_LIMIT_CTL_Port_5_OVER_LIMIT_ACTIONS_MASK 0x0000c000
-#define BCHP_SWITCH_CORE_PORT_N_SA_LIMIT_CTL_Port_5_OVER_LIMIT_ACTIONS_SHIFT 14
-#define BCHP_SWITCH_CORE_PORT_N_SA_LIMIT_CTL_Port_5_OVER_LIMIT_ACTIONS_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: PORT_N_SA_LIMIT_CTL_Port_5 :: SWITCH_RESV [13:13] */
-#define BCHP_SWITCH_CORE_PORT_N_SA_LIMIT_CTL_Port_5_SWITCH_RESV_MASK 0x00002000
-#define BCHP_SWITCH_CORE_PORT_N_SA_LIMIT_CTL_Port_5_SWITCH_RESV_SHIFT 13
-#define BCHP_SWITCH_CORE_PORT_N_SA_LIMIT_CTL_Port_5_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: PORT_N_SA_LIMIT_CTL_Port_5 :: SA_LRN_CNT_LIM [12:00] */
-#define BCHP_SWITCH_CORE_PORT_N_SA_LIMIT_CTL_Port_5_SA_LRN_CNT_LIM_MASK 0x00001fff
-#define BCHP_SWITCH_CORE_PORT_N_SA_LIMIT_CTL_Port_5_SA_LRN_CNT_LIM_SHIFT 0
-#define BCHP_SWITCH_CORE_PORT_N_SA_LIMIT_CTL_Port_5_SA_LRN_CNT_LIM_DEFAULT 0x00000400
-
-/***************************************************************************
- *PORT_7_SA_LIMIT_CTL - Port 7 SA Limit Control Register
- ***************************************************************************/
-/* SWITCH_CORE :: PORT_7_SA_LIMIT_CTL :: reserved_for_padding0 [31:16] */
-#define BCHP_SWITCH_CORE_PORT_7_SA_LIMIT_CTL_reserved_for_padding0_MASK 0xffff0000
-#define BCHP_SWITCH_CORE_PORT_7_SA_LIMIT_CTL_reserved_for_padding0_SHIFT 16
-
-/* SWITCH_CORE :: PORT_7_SA_LIMIT_CTL :: OVER_LIMIT_ACTIONS [15:14] */
-#define BCHP_SWITCH_CORE_PORT_7_SA_LIMIT_CTL_OVER_LIMIT_ACTIONS_MASK 0x0000c000
-#define BCHP_SWITCH_CORE_PORT_7_SA_LIMIT_CTL_OVER_LIMIT_ACTIONS_SHIFT 14
-#define BCHP_SWITCH_CORE_PORT_7_SA_LIMIT_CTL_OVER_LIMIT_ACTIONS_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: PORT_7_SA_LIMIT_CTL :: SWITCH_RESV [13:13] */
-#define BCHP_SWITCH_CORE_PORT_7_SA_LIMIT_CTL_SWITCH_RESV_MASK 0x00002000
-#define BCHP_SWITCH_CORE_PORT_7_SA_LIMIT_CTL_SWITCH_RESV_SHIFT 13
-#define BCHP_SWITCH_CORE_PORT_7_SA_LIMIT_CTL_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: PORT_7_SA_LIMIT_CTL :: SA_LRN_CNT_LIM [12:00] */
-#define BCHP_SWITCH_CORE_PORT_7_SA_LIMIT_CTL_SA_LRN_CNT_LIM_MASK 0x00001fff
-#define BCHP_SWITCH_CORE_PORT_7_SA_LIMIT_CTL_SA_LRN_CNT_LIM_SHIFT 0
-#define BCHP_SWITCH_CORE_PORT_7_SA_LIMIT_CTL_SA_LRN_CNT_LIM_DEFAULT 0x00000400
-
-/***************************************************************************
- *PORT_8_SA_LIMIT_CTL - Port 8 SA Limit Control Register
- ***************************************************************************/
-/* SWITCH_CORE :: PORT_8_SA_LIMIT_CTL :: reserved_for_padding0 [31:16] */
-#define BCHP_SWITCH_CORE_PORT_8_SA_LIMIT_CTL_reserved_for_padding0_MASK 0xffff0000
-#define BCHP_SWITCH_CORE_PORT_8_SA_LIMIT_CTL_reserved_for_padding0_SHIFT 16
-
-/* SWITCH_CORE :: PORT_8_SA_LIMIT_CTL :: OVER_LIMIT_ACTIONS [15:14] */
-#define BCHP_SWITCH_CORE_PORT_8_SA_LIMIT_CTL_OVER_LIMIT_ACTIONS_MASK 0x0000c000
-#define BCHP_SWITCH_CORE_PORT_8_SA_LIMIT_CTL_OVER_LIMIT_ACTIONS_SHIFT 14
-#define BCHP_SWITCH_CORE_PORT_8_SA_LIMIT_CTL_OVER_LIMIT_ACTIONS_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: PORT_8_SA_LIMIT_CTL :: SWITCH_RESV [13:13] */
-#define BCHP_SWITCH_CORE_PORT_8_SA_LIMIT_CTL_SWITCH_RESV_MASK 0x00002000
-#define BCHP_SWITCH_CORE_PORT_8_SA_LIMIT_CTL_SWITCH_RESV_SHIFT 13
-#define BCHP_SWITCH_CORE_PORT_8_SA_LIMIT_CTL_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: PORT_8_SA_LIMIT_CTL :: SA_LRN_CNT_LIM [12:00] */
-#define BCHP_SWITCH_CORE_PORT_8_SA_LIMIT_CTL_SA_LRN_CNT_LIM_MASK 0x00001fff
-#define BCHP_SWITCH_CORE_PORT_8_SA_LIMIT_CTL_SA_LRN_CNT_LIM_SHIFT 0
-#define BCHP_SWITCH_CORE_PORT_8_SA_LIMIT_CTL_SA_LRN_CNT_LIM_DEFAULT 0x00000400
-
-/***************************************************************************
- *TOTAL_SA_LRN_CNTR - Total SA Learned Counter Register
- ***************************************************************************/
-/* SWITCH_CORE :: TOTAL_SA_LRN_CNTR :: reserved_for_padding0 [31:16] */
-#define BCHP_SWITCH_CORE_TOTAL_SA_LRN_CNTR_reserved_for_padding0_MASK 0xffff0000
-#define BCHP_SWITCH_CORE_TOTAL_SA_LRN_CNTR_reserved_for_padding0_SHIFT 16
-
-/* SWITCH_CORE :: TOTAL_SA_LRN_CNTR :: SWITCH_RESV [15:13] */
-#define BCHP_SWITCH_CORE_TOTAL_SA_LRN_CNTR_SWITCH_RESV_MASK 0x0000e000
-#define BCHP_SWITCH_CORE_TOTAL_SA_LRN_CNTR_SWITCH_RESV_SHIFT 13
-#define BCHP_SWITCH_CORE_TOTAL_SA_LRN_CNTR_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: TOTAL_SA_LRN_CNTR :: TOTAL_SA_LRN_CNT_NO [12:00] */
-#define BCHP_SWITCH_CORE_TOTAL_SA_LRN_CNTR_TOTAL_SA_LRN_CNT_NO_MASK 0x00001fff
-#define BCHP_SWITCH_CORE_TOTAL_SA_LRN_CNTR_TOTAL_SA_LRN_CNT_NO_SHIFT 0
-#define BCHP_SWITCH_CORE_TOTAL_SA_LRN_CNTR_TOTAL_SA_LRN_CNT_NO_DEFAULT 0x00000000
-
-/***************************************************************************
- *PORT_N_SA_LRN_CNTR_Port_0 - Port N SA Learned Counter Register
- ***************************************************************************/
-/* SWITCH_CORE :: PORT_N_SA_LRN_CNTR_Port_0 :: reserved_for_padding0 [31:16] */
-#define BCHP_SWITCH_CORE_PORT_N_SA_LRN_CNTR_Port_0_reserved_for_padding0_MASK 0xffff0000
-#define BCHP_SWITCH_CORE_PORT_N_SA_LRN_CNTR_Port_0_reserved_for_padding0_SHIFT 16
-
-/* SWITCH_CORE :: PORT_N_SA_LRN_CNTR_Port_0 :: SWITCH_RESV [15:13] */
-#define BCHP_SWITCH_CORE_PORT_N_SA_LRN_CNTR_Port_0_SWITCH_RESV_MASK 0x0000e000
-#define BCHP_SWITCH_CORE_PORT_N_SA_LRN_CNTR_Port_0_SWITCH_RESV_SHIFT 13
-#define BCHP_SWITCH_CORE_PORT_N_SA_LRN_CNTR_Port_0_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: PORT_N_SA_LRN_CNTR_Port_0 :: SA_LRN_CNT_NO [12:00] */
-#define BCHP_SWITCH_CORE_PORT_N_SA_LRN_CNTR_Port_0_SA_LRN_CNT_NO_MASK 0x00001fff
-#define BCHP_SWITCH_CORE_PORT_N_SA_LRN_CNTR_Port_0_SA_LRN_CNT_NO_SHIFT 0
-#define BCHP_SWITCH_CORE_PORT_N_SA_LRN_CNTR_Port_0_SA_LRN_CNT_NO_DEFAULT 0x00000000
-
-/***************************************************************************
- *PORT_N_SA_LRN_CNTR_Port_1 - Port N SA Learned Counter Register
- ***************************************************************************/
-/* SWITCH_CORE :: PORT_N_SA_LRN_CNTR_Port_1 :: reserved_for_padding0 [31:16] */
-#define BCHP_SWITCH_CORE_PORT_N_SA_LRN_CNTR_Port_1_reserved_for_padding0_MASK 0xffff0000
-#define BCHP_SWITCH_CORE_PORT_N_SA_LRN_CNTR_Port_1_reserved_for_padding0_SHIFT 16
-
-/* SWITCH_CORE :: PORT_N_SA_LRN_CNTR_Port_1 :: SWITCH_RESV [15:13] */
-#define BCHP_SWITCH_CORE_PORT_N_SA_LRN_CNTR_Port_1_SWITCH_RESV_MASK 0x0000e000
-#define BCHP_SWITCH_CORE_PORT_N_SA_LRN_CNTR_Port_1_SWITCH_RESV_SHIFT 13
-#define BCHP_SWITCH_CORE_PORT_N_SA_LRN_CNTR_Port_1_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: PORT_N_SA_LRN_CNTR_Port_1 :: SA_LRN_CNT_NO [12:00] */
-#define BCHP_SWITCH_CORE_PORT_N_SA_LRN_CNTR_Port_1_SA_LRN_CNT_NO_MASK 0x00001fff
-#define BCHP_SWITCH_CORE_PORT_N_SA_LRN_CNTR_Port_1_SA_LRN_CNT_NO_SHIFT 0
-#define BCHP_SWITCH_CORE_PORT_N_SA_LRN_CNTR_Port_1_SA_LRN_CNT_NO_DEFAULT 0x00000000
-
-/***************************************************************************
- *PORT_N_SA_LRN_CNTR_Port_2 - Port N SA Learned Counter Register
- ***************************************************************************/
-/* SWITCH_CORE :: PORT_N_SA_LRN_CNTR_Port_2 :: reserved_for_padding0 [31:16] */
-#define BCHP_SWITCH_CORE_PORT_N_SA_LRN_CNTR_Port_2_reserved_for_padding0_MASK 0xffff0000
-#define BCHP_SWITCH_CORE_PORT_N_SA_LRN_CNTR_Port_2_reserved_for_padding0_SHIFT 16
-
-/* SWITCH_CORE :: PORT_N_SA_LRN_CNTR_Port_2 :: SWITCH_RESV [15:13] */
-#define BCHP_SWITCH_CORE_PORT_N_SA_LRN_CNTR_Port_2_SWITCH_RESV_MASK 0x0000e000
-#define BCHP_SWITCH_CORE_PORT_N_SA_LRN_CNTR_Port_2_SWITCH_RESV_SHIFT 13
-#define BCHP_SWITCH_CORE_PORT_N_SA_LRN_CNTR_Port_2_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: PORT_N_SA_LRN_CNTR_Port_2 :: SA_LRN_CNT_NO [12:00] */
-#define BCHP_SWITCH_CORE_PORT_N_SA_LRN_CNTR_Port_2_SA_LRN_CNT_NO_MASK 0x00001fff
-#define BCHP_SWITCH_CORE_PORT_N_SA_LRN_CNTR_Port_2_SA_LRN_CNT_NO_SHIFT 0
-#define BCHP_SWITCH_CORE_PORT_N_SA_LRN_CNTR_Port_2_SA_LRN_CNT_NO_DEFAULT 0x00000000
-
-/***************************************************************************
- *PORT_N_SA_LRN_CNTR_Port_3 - Port N SA Learned Counter Register
- ***************************************************************************/
-/* SWITCH_CORE :: PORT_N_SA_LRN_CNTR_Port_3 :: reserved_for_padding0 [31:16] */
-#define BCHP_SWITCH_CORE_PORT_N_SA_LRN_CNTR_Port_3_reserved_for_padding0_MASK 0xffff0000
-#define BCHP_SWITCH_CORE_PORT_N_SA_LRN_CNTR_Port_3_reserved_for_padding0_SHIFT 16
-
-/* SWITCH_CORE :: PORT_N_SA_LRN_CNTR_Port_3 :: SWITCH_RESV [15:13] */
-#define BCHP_SWITCH_CORE_PORT_N_SA_LRN_CNTR_Port_3_SWITCH_RESV_MASK 0x0000e000
-#define BCHP_SWITCH_CORE_PORT_N_SA_LRN_CNTR_Port_3_SWITCH_RESV_SHIFT 13
-#define BCHP_SWITCH_CORE_PORT_N_SA_LRN_CNTR_Port_3_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: PORT_N_SA_LRN_CNTR_Port_3 :: SA_LRN_CNT_NO [12:00] */
-#define BCHP_SWITCH_CORE_PORT_N_SA_LRN_CNTR_Port_3_SA_LRN_CNT_NO_MASK 0x00001fff
-#define BCHP_SWITCH_CORE_PORT_N_SA_LRN_CNTR_Port_3_SA_LRN_CNT_NO_SHIFT 0
-#define BCHP_SWITCH_CORE_PORT_N_SA_LRN_CNTR_Port_3_SA_LRN_CNT_NO_DEFAULT 0x00000000
-
-/***************************************************************************
- *PORT_N_SA_LRN_CNTR_Port_4 - Port N SA Learned Counter Register
- ***************************************************************************/
-/* SWITCH_CORE :: PORT_N_SA_LRN_CNTR_Port_4 :: reserved_for_padding0 [31:16] */
-#define BCHP_SWITCH_CORE_PORT_N_SA_LRN_CNTR_Port_4_reserved_for_padding0_MASK 0xffff0000
-#define BCHP_SWITCH_CORE_PORT_N_SA_LRN_CNTR_Port_4_reserved_for_padding0_SHIFT 16
-
-/* SWITCH_CORE :: PORT_N_SA_LRN_CNTR_Port_4 :: SWITCH_RESV [15:13] */
-#define BCHP_SWITCH_CORE_PORT_N_SA_LRN_CNTR_Port_4_SWITCH_RESV_MASK 0x0000e000
-#define BCHP_SWITCH_CORE_PORT_N_SA_LRN_CNTR_Port_4_SWITCH_RESV_SHIFT 13
-#define BCHP_SWITCH_CORE_PORT_N_SA_LRN_CNTR_Port_4_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: PORT_N_SA_LRN_CNTR_Port_4 :: SA_LRN_CNT_NO [12:00] */
-#define BCHP_SWITCH_CORE_PORT_N_SA_LRN_CNTR_Port_4_SA_LRN_CNT_NO_MASK 0x00001fff
-#define BCHP_SWITCH_CORE_PORT_N_SA_LRN_CNTR_Port_4_SA_LRN_CNT_NO_SHIFT 0
-#define BCHP_SWITCH_CORE_PORT_N_SA_LRN_CNTR_Port_4_SA_LRN_CNT_NO_DEFAULT 0x00000000
-
-/***************************************************************************
- *PORT_N_SA_LRN_CNTR_Port_5 - Port N SA Learned Counter Register
- ***************************************************************************/
-/* SWITCH_CORE :: PORT_N_SA_LRN_CNTR_Port_5 :: reserved_for_padding0 [31:16] */
-#define BCHP_SWITCH_CORE_PORT_N_SA_LRN_CNTR_Port_5_reserved_for_padding0_MASK 0xffff0000
-#define BCHP_SWITCH_CORE_PORT_N_SA_LRN_CNTR_Port_5_reserved_for_padding0_SHIFT 16
-
-/* SWITCH_CORE :: PORT_N_SA_LRN_CNTR_Port_5 :: SWITCH_RESV [15:13] */
-#define BCHP_SWITCH_CORE_PORT_N_SA_LRN_CNTR_Port_5_SWITCH_RESV_MASK 0x0000e000
-#define BCHP_SWITCH_CORE_PORT_N_SA_LRN_CNTR_Port_5_SWITCH_RESV_SHIFT 13
-#define BCHP_SWITCH_CORE_PORT_N_SA_LRN_CNTR_Port_5_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: PORT_N_SA_LRN_CNTR_Port_5 :: SA_LRN_CNT_NO [12:00] */
-#define BCHP_SWITCH_CORE_PORT_N_SA_LRN_CNTR_Port_5_SA_LRN_CNT_NO_MASK 0x00001fff
-#define BCHP_SWITCH_CORE_PORT_N_SA_LRN_CNTR_Port_5_SA_LRN_CNT_NO_SHIFT 0
-#define BCHP_SWITCH_CORE_PORT_N_SA_LRN_CNTR_Port_5_SA_LRN_CNT_NO_DEFAULT 0x00000000
-
-/***************************************************************************
- *PORT_7_SA_LRN_CNTR - Port 7 SA Learned Counter Register
- ***************************************************************************/
-/* SWITCH_CORE :: PORT_7_SA_LRN_CNTR :: reserved_for_padding0 [31:16] */
-#define BCHP_SWITCH_CORE_PORT_7_SA_LRN_CNTR_reserved_for_padding0_MASK 0xffff0000
-#define BCHP_SWITCH_CORE_PORT_7_SA_LRN_CNTR_reserved_for_padding0_SHIFT 16
-
-/* SWITCH_CORE :: PORT_7_SA_LRN_CNTR :: SWITCH_RESV [15:13] */
-#define BCHP_SWITCH_CORE_PORT_7_SA_LRN_CNTR_SWITCH_RESV_MASK 0x0000e000
-#define BCHP_SWITCH_CORE_PORT_7_SA_LRN_CNTR_SWITCH_RESV_SHIFT 13
-#define BCHP_SWITCH_CORE_PORT_7_SA_LRN_CNTR_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: PORT_7_SA_LRN_CNTR :: SA_LRN_CNT_NO [12:00] */
-#define BCHP_SWITCH_CORE_PORT_7_SA_LRN_CNTR_SA_LRN_CNT_NO_MASK 0x00001fff
-#define BCHP_SWITCH_CORE_PORT_7_SA_LRN_CNTR_SA_LRN_CNT_NO_SHIFT 0
-#define BCHP_SWITCH_CORE_PORT_7_SA_LRN_CNTR_SA_LRN_CNT_NO_DEFAULT 0x00000000
-
-/***************************************************************************
- *PORT_8_SA_LRN_CNTR - Port 8 SA Learned Counter Register
- ***************************************************************************/
-/* SWITCH_CORE :: PORT_8_SA_LRN_CNTR :: reserved_for_padding0 [31:16] */
-#define BCHP_SWITCH_CORE_PORT_8_SA_LRN_CNTR_reserved_for_padding0_MASK 0xffff0000
-#define BCHP_SWITCH_CORE_PORT_8_SA_LRN_CNTR_reserved_for_padding0_SHIFT 16
-
-/* SWITCH_CORE :: PORT_8_SA_LRN_CNTR :: SWITCH_RESV [15:13] */
-#define BCHP_SWITCH_CORE_PORT_8_SA_LRN_CNTR_SWITCH_RESV_MASK 0x0000e000
-#define BCHP_SWITCH_CORE_PORT_8_SA_LRN_CNTR_SWITCH_RESV_SHIFT 13
-#define BCHP_SWITCH_CORE_PORT_8_SA_LRN_CNTR_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: PORT_8_SA_LRN_CNTR :: SA_LRN_CNT_NO [12:00] */
-#define BCHP_SWITCH_CORE_PORT_8_SA_LRN_CNTR_SA_LRN_CNT_NO_MASK 0x00001fff
-#define BCHP_SWITCH_CORE_PORT_8_SA_LRN_CNTR_SA_LRN_CNT_NO_SHIFT 0
-#define BCHP_SWITCH_CORE_PORT_8_SA_LRN_CNTR_SA_LRN_CNT_NO_DEFAULT 0x00000000
-
-/***************************************************************************
- *PORT_N_SA_OVERLIMIT_CNTR_Port_0 - Port N SA Over Limit Counter Register
- ***************************************************************************/
-/* SWITCH_CORE :: PORT_N_SA_OVERLIMIT_CNTR_Port_0 :: SA_OVER_LIMIT_CNTR [31:00] */
-#define BCHP_SWITCH_CORE_PORT_N_SA_OVERLIMIT_CNTR_Port_0_SA_OVER_LIMIT_CNTR_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_PORT_N_SA_OVERLIMIT_CNTR_Port_0_SA_OVER_LIMIT_CNTR_SHIFT 0
-#define BCHP_SWITCH_CORE_PORT_N_SA_OVERLIMIT_CNTR_Port_0_SA_OVER_LIMIT_CNTR_DEFAULT 0x00000000
-
-/***************************************************************************
- *PORT_N_SA_OVERLIMIT_CNTR_Port_1 - Port N SA Over Limit Counter Register
- ***************************************************************************/
-/* SWITCH_CORE :: PORT_N_SA_OVERLIMIT_CNTR_Port_1 :: SA_OVER_LIMIT_CNTR [31:00] */
-#define BCHP_SWITCH_CORE_PORT_N_SA_OVERLIMIT_CNTR_Port_1_SA_OVER_LIMIT_CNTR_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_PORT_N_SA_OVERLIMIT_CNTR_Port_1_SA_OVER_LIMIT_CNTR_SHIFT 0
-#define BCHP_SWITCH_CORE_PORT_N_SA_OVERLIMIT_CNTR_Port_1_SA_OVER_LIMIT_CNTR_DEFAULT 0x00000000
-
-/***************************************************************************
- *PORT_N_SA_OVERLIMIT_CNTR_Port_2 - Port N SA Over Limit Counter Register
- ***************************************************************************/
-/* SWITCH_CORE :: PORT_N_SA_OVERLIMIT_CNTR_Port_2 :: SA_OVER_LIMIT_CNTR [31:00] */
-#define BCHP_SWITCH_CORE_PORT_N_SA_OVERLIMIT_CNTR_Port_2_SA_OVER_LIMIT_CNTR_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_PORT_N_SA_OVERLIMIT_CNTR_Port_2_SA_OVER_LIMIT_CNTR_SHIFT 0
-#define BCHP_SWITCH_CORE_PORT_N_SA_OVERLIMIT_CNTR_Port_2_SA_OVER_LIMIT_CNTR_DEFAULT 0x00000000
-
-/***************************************************************************
- *PORT_N_SA_OVERLIMIT_CNTR_Port_3 - Port N SA Over Limit Counter Register
- ***************************************************************************/
-/* SWITCH_CORE :: PORT_N_SA_OVERLIMIT_CNTR_Port_3 :: SA_OVER_LIMIT_CNTR [31:00] */
-#define BCHP_SWITCH_CORE_PORT_N_SA_OVERLIMIT_CNTR_Port_3_SA_OVER_LIMIT_CNTR_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_PORT_N_SA_OVERLIMIT_CNTR_Port_3_SA_OVER_LIMIT_CNTR_SHIFT 0
-#define BCHP_SWITCH_CORE_PORT_N_SA_OVERLIMIT_CNTR_Port_3_SA_OVER_LIMIT_CNTR_DEFAULT 0x00000000
-
-/***************************************************************************
- *PORT_N_SA_OVERLIMIT_CNTR_Port_4 - Port N SA Over Limit Counter Register
- ***************************************************************************/
-/* SWITCH_CORE :: PORT_N_SA_OVERLIMIT_CNTR_Port_4 :: SA_OVER_LIMIT_CNTR [31:00] */
-#define BCHP_SWITCH_CORE_PORT_N_SA_OVERLIMIT_CNTR_Port_4_SA_OVER_LIMIT_CNTR_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_PORT_N_SA_OVERLIMIT_CNTR_Port_4_SA_OVER_LIMIT_CNTR_SHIFT 0
-#define BCHP_SWITCH_CORE_PORT_N_SA_OVERLIMIT_CNTR_Port_4_SA_OVER_LIMIT_CNTR_DEFAULT 0x00000000
-
-/***************************************************************************
- *PORT_N_SA_OVERLIMIT_CNTR_Port_5 - Port N SA Over Limit Counter Register
- ***************************************************************************/
-/* SWITCH_CORE :: PORT_N_SA_OVERLIMIT_CNTR_Port_5 :: SA_OVER_LIMIT_CNTR [31:00] */
-#define BCHP_SWITCH_CORE_PORT_N_SA_OVERLIMIT_CNTR_Port_5_SA_OVER_LIMIT_CNTR_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_PORT_N_SA_OVERLIMIT_CNTR_Port_5_SA_OVER_LIMIT_CNTR_SHIFT 0
-#define BCHP_SWITCH_CORE_PORT_N_SA_OVERLIMIT_CNTR_Port_5_SA_OVER_LIMIT_CNTR_DEFAULT 0x00000000
-
-/***************************************************************************
- *PORT_7_SA_OVERLIMIT_CNTR - Port 7 SA Over Limit Counter Register
- ***************************************************************************/
-/* SWITCH_CORE :: PORT_7_SA_OVERLIMIT_CNTR :: SA_OVER_LIMIT_CNTR [31:00] */
-#define BCHP_SWITCH_CORE_PORT_7_SA_OVERLIMIT_CNTR_SA_OVER_LIMIT_CNTR_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_PORT_7_SA_OVERLIMIT_CNTR_SA_OVER_LIMIT_CNTR_SHIFT 0
-#define BCHP_SWITCH_CORE_PORT_7_SA_OVERLIMIT_CNTR_SA_OVER_LIMIT_CNTR_DEFAULT 0x00000000
-
-/***************************************************************************
- *PORT_8_SA_OVERLIMIT_CNTR - Port 8 SA Over Limit Counter Register
- ***************************************************************************/
-/* SWITCH_CORE :: PORT_8_SA_OVERLIMIT_CNTR :: SA_OVER_LIMIT_CNTR [31:00] */
-#define BCHP_SWITCH_CORE_PORT_8_SA_OVERLIMIT_CNTR_SA_OVER_LIMIT_CNTR_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_PORT_8_SA_OVERLIMIT_CNTR_SA_OVER_LIMIT_CNTR_SHIFT 0
-#define BCHP_SWITCH_CORE_PORT_8_SA_OVERLIMIT_CNTR_SA_OVER_LIMIT_CNTR_DEFAULT 0x00000000
-
-/***************************************************************************
- *SA_OVER_LIMIT_COPY_REDIRECT - SA Over Limit Actions Config Register
- ***************************************************************************/
-/* SWITCH_CORE :: SA_OVER_LIMIT_COPY_REDIRECT :: reserved_for_padding0 [31:16] */
-#define BCHP_SWITCH_CORE_SA_OVER_LIMIT_COPY_REDIRECT_reserved_for_padding0_MASK 0xffff0000
-#define BCHP_SWITCH_CORE_SA_OVER_LIMIT_COPY_REDIRECT_reserved_for_padding0_SHIFT 16
-
-/* SWITCH_CORE :: SA_OVER_LIMIT_COPY_REDIRECT :: SWITCH_RESV [15:04] */
-#define BCHP_SWITCH_CORE_SA_OVER_LIMIT_COPY_REDIRECT_SWITCH_RESV_MASK 0x0000fff0
-#define BCHP_SWITCH_CORE_SA_OVER_LIMIT_COPY_REDIRECT_SWITCH_RESV_SHIFT 4
-#define BCHP_SWITCH_CORE_SA_OVER_LIMIT_COPY_REDIRECT_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: SA_OVER_LIMIT_COPY_REDIRECT :: COPY_REDIRECT_PORT_ID [03:00] */
-#define BCHP_SWITCH_CORE_SA_OVER_LIMIT_COPY_REDIRECT_COPY_REDIRECT_PORT_ID_MASK 0x0000000f
-#define BCHP_SWITCH_CORE_SA_OVER_LIMIT_COPY_REDIRECT_COPY_REDIRECT_PORT_ID_SHIFT 0
-#define BCHP_SWITCH_CORE_SA_OVER_LIMIT_COPY_REDIRECT_COPY_REDIRECT_PORT_ID_DEFAULT 0x00000008
-
-/***************************************************************************
- *MAC_LIMIT_REG_SPARE0 - Spare 0 Register (Not2Release)
- ***************************************************************************/
-/* SWITCH_CORE :: MAC_LIMIT_REG_SPARE0 :: MAC_LIMIT_REG_SPARE0 [31:00] */
-#define BCHP_SWITCH_CORE_MAC_LIMIT_REG_SPARE0_MAC_LIMIT_REG_SPARE0_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_MAC_LIMIT_REG_SPARE0_MAC_LIMIT_REG_SPARE0_SHIFT 0
-#define BCHP_SWITCH_CORE_MAC_LIMIT_REG_SPARE0_MAC_LIMIT_REG_SPARE0_DEFAULT 0x00000000
-
-/***************************************************************************
- *MAC_LIMIT_REG_SPARE1 - Spare 1 Register (Not2Release)
- ***************************************************************************/
-/* SWITCH_CORE :: MAC_LIMIT_REG_SPARE1 :: MAC_LIMIT_REG_SPARE1 [31:00] */
-#define BCHP_SWITCH_CORE_MAC_LIMIT_REG_SPARE1_MAC_LIMIT_REG_SPARE1_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_MAC_LIMIT_REG_SPARE1_MAC_LIMIT_REG_SPARE1_SHIFT 0
-#define BCHP_SWITCH_CORE_MAC_LIMIT_REG_SPARE1_MAC_LIMIT_REG_SPARE1_DEFAULT 0x00000000
-
-/***************************************************************************
- *PN_QOS_PRI_CTL_Port_0 - Port N, QOS Priority Control Register
- ***************************************************************************/
-/* SWITCH_CORE :: PN_QOS_PRI_CTL_Port_0 :: reserved_for_padding0 [31:08] */
-#define BCHP_SWITCH_CORE_PN_QOS_PRI_CTL_Port_0_reserved_for_padding0_MASK 0xffffff00
-#define BCHP_SWITCH_CORE_PN_QOS_PRI_CTL_Port_0_reserved_for_padding0_SHIFT 8
-
-/* SWITCH_CORE :: PN_QOS_PRI_CTL_Port_0 :: TXQ_EMPTY_STATUS_SELECT [07:07] */
-#define BCHP_SWITCH_CORE_PN_QOS_PRI_CTL_Port_0_TXQ_EMPTY_STATUS_SELECT_MASK 0x00000080
-#define BCHP_SWITCH_CORE_PN_QOS_PRI_CTL_Port_0_TXQ_EMPTY_STATUS_SELECT_SHIFT 7
-#define BCHP_SWITCH_CORE_PN_QOS_PRI_CTL_Port_0_TXQ_EMPTY_STATUS_SELECT_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: PN_QOS_PRI_CTL_Port_0 :: SWITCH_RESV [06:06] */
-#define BCHP_SWITCH_CORE_PN_QOS_PRI_CTL_Port_0_SWITCH_RESV_MASK 0x00000040
-#define BCHP_SWITCH_CORE_PN_QOS_PRI_CTL_Port_0_SWITCH_RESV_SHIFT 6
-#define BCHP_SWITCH_CORE_PN_QOS_PRI_CTL_Port_0_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: PN_QOS_PRI_CTL_Port_0 :: NEGATIVE_CREDIT_CLR_DISABLE [05:05] */
-#define BCHP_SWITCH_CORE_PN_QOS_PRI_CTL_Port_0_NEGATIVE_CREDIT_CLR_DISABLE_MASK 0x00000020
-#define BCHP_SWITCH_CORE_PN_QOS_PRI_CTL_Port_0_NEGATIVE_CREDIT_CLR_DISABLE_SHIFT 5
-#define BCHP_SWITCH_CORE_PN_QOS_PRI_CTL_Port_0_NEGATIVE_CREDIT_CLR_DISABLE_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: PN_QOS_PRI_CTL_Port_0 :: ROUNDROBIN_BURST_MODE_ENABLE [04:04] */
-#define BCHP_SWITCH_CORE_PN_QOS_PRI_CTL_Port_0_ROUNDROBIN_BURST_MODE_ENABLE_MASK 0x00000010
-#define BCHP_SWITCH_CORE_PN_QOS_PRI_CTL_Port_0_ROUNDROBIN_BURST_MODE_ENABLE_SHIFT 4
-#define BCHP_SWITCH_CORE_PN_QOS_PRI_CTL_Port_0_ROUNDROBIN_BURST_MODE_ENABLE_DEFAULT 0x00000001
-
-/* SWITCH_CORE :: PN_QOS_PRI_CTL_Port_0 :: WDRR_GRANULARITY [03:03] */
-#define BCHP_SWITCH_CORE_PN_QOS_PRI_CTL_Port_0_WDRR_GRANULARITY_MASK 0x00000008
-#define BCHP_SWITCH_CORE_PN_QOS_PRI_CTL_Port_0_WDRR_GRANULARITY_SHIFT 3
-#define BCHP_SWITCH_CORE_PN_QOS_PRI_CTL_Port_0_WDRR_GRANULARITY_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: PN_QOS_PRI_CTL_Port_0 :: SCHEDULER_SELECT [02:00] */
-#define BCHP_SWITCH_CORE_PN_QOS_PRI_CTL_Port_0_SCHEDULER_SELECT_MASK 0x00000007
-#define BCHP_SWITCH_CORE_PN_QOS_PRI_CTL_Port_0_SCHEDULER_SELECT_SHIFT 0
-#define BCHP_SWITCH_CORE_PN_QOS_PRI_CTL_Port_0_SCHEDULER_SELECT_DEFAULT 0x00000000
-
-/***************************************************************************
- *PN_QOS_PRI_CTL_Port_1 - Port N, QOS Priority Control Register
- ***************************************************************************/
-/* SWITCH_CORE :: PN_QOS_PRI_CTL_Port_1 :: reserved_for_padding0 [31:08] */
-#define BCHP_SWITCH_CORE_PN_QOS_PRI_CTL_Port_1_reserved_for_padding0_MASK 0xffffff00
-#define BCHP_SWITCH_CORE_PN_QOS_PRI_CTL_Port_1_reserved_for_padding0_SHIFT 8
-
-/* SWITCH_CORE :: PN_QOS_PRI_CTL_Port_1 :: TXQ_EMPTY_STATUS_SELECT [07:07] */
-#define BCHP_SWITCH_CORE_PN_QOS_PRI_CTL_Port_1_TXQ_EMPTY_STATUS_SELECT_MASK 0x00000080
-#define BCHP_SWITCH_CORE_PN_QOS_PRI_CTL_Port_1_TXQ_EMPTY_STATUS_SELECT_SHIFT 7
-#define BCHP_SWITCH_CORE_PN_QOS_PRI_CTL_Port_1_TXQ_EMPTY_STATUS_SELECT_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: PN_QOS_PRI_CTL_Port_1 :: SWITCH_RESV [06:06] */
-#define BCHP_SWITCH_CORE_PN_QOS_PRI_CTL_Port_1_SWITCH_RESV_MASK 0x00000040
-#define BCHP_SWITCH_CORE_PN_QOS_PRI_CTL_Port_1_SWITCH_RESV_SHIFT 6
-#define BCHP_SWITCH_CORE_PN_QOS_PRI_CTL_Port_1_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: PN_QOS_PRI_CTL_Port_1 :: NEGATIVE_CREDIT_CLR_DISABLE [05:05] */
-#define BCHP_SWITCH_CORE_PN_QOS_PRI_CTL_Port_1_NEGATIVE_CREDIT_CLR_DISABLE_MASK 0x00000020
-#define BCHP_SWITCH_CORE_PN_QOS_PRI_CTL_Port_1_NEGATIVE_CREDIT_CLR_DISABLE_SHIFT 5
-#define BCHP_SWITCH_CORE_PN_QOS_PRI_CTL_Port_1_NEGATIVE_CREDIT_CLR_DISABLE_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: PN_QOS_PRI_CTL_Port_1 :: ROUNDROBIN_BURST_MODE_ENABLE [04:04] */
-#define BCHP_SWITCH_CORE_PN_QOS_PRI_CTL_Port_1_ROUNDROBIN_BURST_MODE_ENABLE_MASK 0x00000010
-#define BCHP_SWITCH_CORE_PN_QOS_PRI_CTL_Port_1_ROUNDROBIN_BURST_MODE_ENABLE_SHIFT 4
-#define BCHP_SWITCH_CORE_PN_QOS_PRI_CTL_Port_1_ROUNDROBIN_BURST_MODE_ENABLE_DEFAULT 0x00000001
-
-/* SWITCH_CORE :: PN_QOS_PRI_CTL_Port_1 :: WDRR_GRANULARITY [03:03] */
-#define BCHP_SWITCH_CORE_PN_QOS_PRI_CTL_Port_1_WDRR_GRANULARITY_MASK 0x00000008
-#define BCHP_SWITCH_CORE_PN_QOS_PRI_CTL_Port_1_WDRR_GRANULARITY_SHIFT 3
-#define BCHP_SWITCH_CORE_PN_QOS_PRI_CTL_Port_1_WDRR_GRANULARITY_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: PN_QOS_PRI_CTL_Port_1 :: SCHEDULER_SELECT [02:00] */
-#define BCHP_SWITCH_CORE_PN_QOS_PRI_CTL_Port_1_SCHEDULER_SELECT_MASK 0x00000007
-#define BCHP_SWITCH_CORE_PN_QOS_PRI_CTL_Port_1_SCHEDULER_SELECT_SHIFT 0
-#define BCHP_SWITCH_CORE_PN_QOS_PRI_CTL_Port_1_SCHEDULER_SELECT_DEFAULT 0x00000000
-
-/***************************************************************************
- *PN_QOS_PRI_CTL_Port_2 - Port N, QOS Priority Control Register
- ***************************************************************************/
-/* SWITCH_CORE :: PN_QOS_PRI_CTL_Port_2 :: reserved_for_padding0 [31:08] */
-#define BCHP_SWITCH_CORE_PN_QOS_PRI_CTL_Port_2_reserved_for_padding0_MASK 0xffffff00
-#define BCHP_SWITCH_CORE_PN_QOS_PRI_CTL_Port_2_reserved_for_padding0_SHIFT 8
-
-/* SWITCH_CORE :: PN_QOS_PRI_CTL_Port_2 :: TXQ_EMPTY_STATUS_SELECT [07:07] */
-#define BCHP_SWITCH_CORE_PN_QOS_PRI_CTL_Port_2_TXQ_EMPTY_STATUS_SELECT_MASK 0x00000080
-#define BCHP_SWITCH_CORE_PN_QOS_PRI_CTL_Port_2_TXQ_EMPTY_STATUS_SELECT_SHIFT 7
-#define BCHP_SWITCH_CORE_PN_QOS_PRI_CTL_Port_2_TXQ_EMPTY_STATUS_SELECT_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: PN_QOS_PRI_CTL_Port_2 :: SWITCH_RESV [06:06] */
-#define BCHP_SWITCH_CORE_PN_QOS_PRI_CTL_Port_2_SWITCH_RESV_MASK 0x00000040
-#define BCHP_SWITCH_CORE_PN_QOS_PRI_CTL_Port_2_SWITCH_RESV_SHIFT 6
-#define BCHP_SWITCH_CORE_PN_QOS_PRI_CTL_Port_2_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: PN_QOS_PRI_CTL_Port_2 :: NEGATIVE_CREDIT_CLR_DISABLE [05:05] */
-#define BCHP_SWITCH_CORE_PN_QOS_PRI_CTL_Port_2_NEGATIVE_CREDIT_CLR_DISABLE_MASK 0x00000020
-#define BCHP_SWITCH_CORE_PN_QOS_PRI_CTL_Port_2_NEGATIVE_CREDIT_CLR_DISABLE_SHIFT 5
-#define BCHP_SWITCH_CORE_PN_QOS_PRI_CTL_Port_2_NEGATIVE_CREDIT_CLR_DISABLE_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: PN_QOS_PRI_CTL_Port_2 :: ROUNDROBIN_BURST_MODE_ENABLE [04:04] */
-#define BCHP_SWITCH_CORE_PN_QOS_PRI_CTL_Port_2_ROUNDROBIN_BURST_MODE_ENABLE_MASK 0x00000010
-#define BCHP_SWITCH_CORE_PN_QOS_PRI_CTL_Port_2_ROUNDROBIN_BURST_MODE_ENABLE_SHIFT 4
-#define BCHP_SWITCH_CORE_PN_QOS_PRI_CTL_Port_2_ROUNDROBIN_BURST_MODE_ENABLE_DEFAULT 0x00000001
-
-/* SWITCH_CORE :: PN_QOS_PRI_CTL_Port_2 :: WDRR_GRANULARITY [03:03] */
-#define BCHP_SWITCH_CORE_PN_QOS_PRI_CTL_Port_2_WDRR_GRANULARITY_MASK 0x00000008
-#define BCHP_SWITCH_CORE_PN_QOS_PRI_CTL_Port_2_WDRR_GRANULARITY_SHIFT 3
-#define BCHP_SWITCH_CORE_PN_QOS_PRI_CTL_Port_2_WDRR_GRANULARITY_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: PN_QOS_PRI_CTL_Port_2 :: SCHEDULER_SELECT [02:00] */
-#define BCHP_SWITCH_CORE_PN_QOS_PRI_CTL_Port_2_SCHEDULER_SELECT_MASK 0x00000007
-#define BCHP_SWITCH_CORE_PN_QOS_PRI_CTL_Port_2_SCHEDULER_SELECT_SHIFT 0
-#define BCHP_SWITCH_CORE_PN_QOS_PRI_CTL_Port_2_SCHEDULER_SELECT_DEFAULT 0x00000000
-
-/***************************************************************************
- *PN_QOS_PRI_CTL_Port_3 - Port N, QOS Priority Control Register
- ***************************************************************************/
-/* SWITCH_CORE :: PN_QOS_PRI_CTL_Port_3 :: reserved_for_padding0 [31:08] */
-#define BCHP_SWITCH_CORE_PN_QOS_PRI_CTL_Port_3_reserved_for_padding0_MASK 0xffffff00
-#define BCHP_SWITCH_CORE_PN_QOS_PRI_CTL_Port_3_reserved_for_padding0_SHIFT 8
-
-/* SWITCH_CORE :: PN_QOS_PRI_CTL_Port_3 :: TXQ_EMPTY_STATUS_SELECT [07:07] */
-#define BCHP_SWITCH_CORE_PN_QOS_PRI_CTL_Port_3_TXQ_EMPTY_STATUS_SELECT_MASK 0x00000080
-#define BCHP_SWITCH_CORE_PN_QOS_PRI_CTL_Port_3_TXQ_EMPTY_STATUS_SELECT_SHIFT 7
-#define BCHP_SWITCH_CORE_PN_QOS_PRI_CTL_Port_3_TXQ_EMPTY_STATUS_SELECT_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: PN_QOS_PRI_CTL_Port_3 :: SWITCH_RESV [06:06] */
-#define BCHP_SWITCH_CORE_PN_QOS_PRI_CTL_Port_3_SWITCH_RESV_MASK 0x00000040
-#define BCHP_SWITCH_CORE_PN_QOS_PRI_CTL_Port_3_SWITCH_RESV_SHIFT 6
-#define BCHP_SWITCH_CORE_PN_QOS_PRI_CTL_Port_3_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: PN_QOS_PRI_CTL_Port_3 :: NEGATIVE_CREDIT_CLR_DISABLE [05:05] */
-#define BCHP_SWITCH_CORE_PN_QOS_PRI_CTL_Port_3_NEGATIVE_CREDIT_CLR_DISABLE_MASK 0x00000020
-#define BCHP_SWITCH_CORE_PN_QOS_PRI_CTL_Port_3_NEGATIVE_CREDIT_CLR_DISABLE_SHIFT 5
-#define BCHP_SWITCH_CORE_PN_QOS_PRI_CTL_Port_3_NEGATIVE_CREDIT_CLR_DISABLE_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: PN_QOS_PRI_CTL_Port_3 :: ROUNDROBIN_BURST_MODE_ENABLE [04:04] */
-#define BCHP_SWITCH_CORE_PN_QOS_PRI_CTL_Port_3_ROUNDROBIN_BURST_MODE_ENABLE_MASK 0x00000010
-#define BCHP_SWITCH_CORE_PN_QOS_PRI_CTL_Port_3_ROUNDROBIN_BURST_MODE_ENABLE_SHIFT 4
-#define BCHP_SWITCH_CORE_PN_QOS_PRI_CTL_Port_3_ROUNDROBIN_BURST_MODE_ENABLE_DEFAULT 0x00000001
-
-/* SWITCH_CORE :: PN_QOS_PRI_CTL_Port_3 :: WDRR_GRANULARITY [03:03] */
-#define BCHP_SWITCH_CORE_PN_QOS_PRI_CTL_Port_3_WDRR_GRANULARITY_MASK 0x00000008
-#define BCHP_SWITCH_CORE_PN_QOS_PRI_CTL_Port_3_WDRR_GRANULARITY_SHIFT 3
-#define BCHP_SWITCH_CORE_PN_QOS_PRI_CTL_Port_3_WDRR_GRANULARITY_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: PN_QOS_PRI_CTL_Port_3 :: SCHEDULER_SELECT [02:00] */
-#define BCHP_SWITCH_CORE_PN_QOS_PRI_CTL_Port_3_SCHEDULER_SELECT_MASK 0x00000007
-#define BCHP_SWITCH_CORE_PN_QOS_PRI_CTL_Port_3_SCHEDULER_SELECT_SHIFT 0
-#define BCHP_SWITCH_CORE_PN_QOS_PRI_CTL_Port_3_SCHEDULER_SELECT_DEFAULT 0x00000000
-
-/***************************************************************************
- *PN_QOS_PRI_CTL_Port_4 - Port N, QOS Priority Control Register
- ***************************************************************************/
-/* SWITCH_CORE :: PN_QOS_PRI_CTL_Port_4 :: reserved_for_padding0 [31:08] */
-#define BCHP_SWITCH_CORE_PN_QOS_PRI_CTL_Port_4_reserved_for_padding0_MASK 0xffffff00
-#define BCHP_SWITCH_CORE_PN_QOS_PRI_CTL_Port_4_reserved_for_padding0_SHIFT 8
-
-/* SWITCH_CORE :: PN_QOS_PRI_CTL_Port_4 :: TXQ_EMPTY_STATUS_SELECT [07:07] */
-#define BCHP_SWITCH_CORE_PN_QOS_PRI_CTL_Port_4_TXQ_EMPTY_STATUS_SELECT_MASK 0x00000080
-#define BCHP_SWITCH_CORE_PN_QOS_PRI_CTL_Port_4_TXQ_EMPTY_STATUS_SELECT_SHIFT 7
-#define BCHP_SWITCH_CORE_PN_QOS_PRI_CTL_Port_4_TXQ_EMPTY_STATUS_SELECT_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: PN_QOS_PRI_CTL_Port_4 :: SWITCH_RESV [06:06] */
-#define BCHP_SWITCH_CORE_PN_QOS_PRI_CTL_Port_4_SWITCH_RESV_MASK 0x00000040
-#define BCHP_SWITCH_CORE_PN_QOS_PRI_CTL_Port_4_SWITCH_RESV_SHIFT 6
-#define BCHP_SWITCH_CORE_PN_QOS_PRI_CTL_Port_4_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: PN_QOS_PRI_CTL_Port_4 :: NEGATIVE_CREDIT_CLR_DISABLE [05:05] */
-#define BCHP_SWITCH_CORE_PN_QOS_PRI_CTL_Port_4_NEGATIVE_CREDIT_CLR_DISABLE_MASK 0x00000020
-#define BCHP_SWITCH_CORE_PN_QOS_PRI_CTL_Port_4_NEGATIVE_CREDIT_CLR_DISABLE_SHIFT 5
-#define BCHP_SWITCH_CORE_PN_QOS_PRI_CTL_Port_4_NEGATIVE_CREDIT_CLR_DISABLE_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: PN_QOS_PRI_CTL_Port_4 :: ROUNDROBIN_BURST_MODE_ENABLE [04:04] */
-#define BCHP_SWITCH_CORE_PN_QOS_PRI_CTL_Port_4_ROUNDROBIN_BURST_MODE_ENABLE_MASK 0x00000010
-#define BCHP_SWITCH_CORE_PN_QOS_PRI_CTL_Port_4_ROUNDROBIN_BURST_MODE_ENABLE_SHIFT 4
-#define BCHP_SWITCH_CORE_PN_QOS_PRI_CTL_Port_4_ROUNDROBIN_BURST_MODE_ENABLE_DEFAULT 0x00000001
-
-/* SWITCH_CORE :: PN_QOS_PRI_CTL_Port_4 :: WDRR_GRANULARITY [03:03] */
-#define BCHP_SWITCH_CORE_PN_QOS_PRI_CTL_Port_4_WDRR_GRANULARITY_MASK 0x00000008
-#define BCHP_SWITCH_CORE_PN_QOS_PRI_CTL_Port_4_WDRR_GRANULARITY_SHIFT 3
-#define BCHP_SWITCH_CORE_PN_QOS_PRI_CTL_Port_4_WDRR_GRANULARITY_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: PN_QOS_PRI_CTL_Port_4 :: SCHEDULER_SELECT [02:00] */
-#define BCHP_SWITCH_CORE_PN_QOS_PRI_CTL_Port_4_SCHEDULER_SELECT_MASK 0x00000007
-#define BCHP_SWITCH_CORE_PN_QOS_PRI_CTL_Port_4_SCHEDULER_SELECT_SHIFT 0
-#define BCHP_SWITCH_CORE_PN_QOS_PRI_CTL_Port_4_SCHEDULER_SELECT_DEFAULT 0x00000000
-
-/***************************************************************************
- *PN_QOS_PRI_CTL_Port_5 - Port N, QOS Priority Control Register
- ***************************************************************************/
-/* SWITCH_CORE :: PN_QOS_PRI_CTL_Port_5 :: reserved_for_padding0 [31:08] */
-#define BCHP_SWITCH_CORE_PN_QOS_PRI_CTL_Port_5_reserved_for_padding0_MASK 0xffffff00
-#define BCHP_SWITCH_CORE_PN_QOS_PRI_CTL_Port_5_reserved_for_padding0_SHIFT 8
-
-/* SWITCH_CORE :: PN_QOS_PRI_CTL_Port_5 :: TXQ_EMPTY_STATUS_SELECT [07:07] */
-#define BCHP_SWITCH_CORE_PN_QOS_PRI_CTL_Port_5_TXQ_EMPTY_STATUS_SELECT_MASK 0x00000080
-#define BCHP_SWITCH_CORE_PN_QOS_PRI_CTL_Port_5_TXQ_EMPTY_STATUS_SELECT_SHIFT 7
-#define BCHP_SWITCH_CORE_PN_QOS_PRI_CTL_Port_5_TXQ_EMPTY_STATUS_SELECT_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: PN_QOS_PRI_CTL_Port_5 :: SWITCH_RESV [06:06] */
-#define BCHP_SWITCH_CORE_PN_QOS_PRI_CTL_Port_5_SWITCH_RESV_MASK 0x00000040
-#define BCHP_SWITCH_CORE_PN_QOS_PRI_CTL_Port_5_SWITCH_RESV_SHIFT 6
-#define BCHP_SWITCH_CORE_PN_QOS_PRI_CTL_Port_5_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: PN_QOS_PRI_CTL_Port_5 :: NEGATIVE_CREDIT_CLR_DISABLE [05:05] */
-#define BCHP_SWITCH_CORE_PN_QOS_PRI_CTL_Port_5_NEGATIVE_CREDIT_CLR_DISABLE_MASK 0x00000020
-#define BCHP_SWITCH_CORE_PN_QOS_PRI_CTL_Port_5_NEGATIVE_CREDIT_CLR_DISABLE_SHIFT 5
-#define BCHP_SWITCH_CORE_PN_QOS_PRI_CTL_Port_5_NEGATIVE_CREDIT_CLR_DISABLE_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: PN_QOS_PRI_CTL_Port_5 :: ROUNDROBIN_BURST_MODE_ENABLE [04:04] */
-#define BCHP_SWITCH_CORE_PN_QOS_PRI_CTL_Port_5_ROUNDROBIN_BURST_MODE_ENABLE_MASK 0x00000010
-#define BCHP_SWITCH_CORE_PN_QOS_PRI_CTL_Port_5_ROUNDROBIN_BURST_MODE_ENABLE_SHIFT 4
-#define BCHP_SWITCH_CORE_PN_QOS_PRI_CTL_Port_5_ROUNDROBIN_BURST_MODE_ENABLE_DEFAULT 0x00000001
-
-/* SWITCH_CORE :: PN_QOS_PRI_CTL_Port_5 :: WDRR_GRANULARITY [03:03] */
-#define BCHP_SWITCH_CORE_PN_QOS_PRI_CTL_Port_5_WDRR_GRANULARITY_MASK 0x00000008
-#define BCHP_SWITCH_CORE_PN_QOS_PRI_CTL_Port_5_WDRR_GRANULARITY_SHIFT 3
-#define BCHP_SWITCH_CORE_PN_QOS_PRI_CTL_Port_5_WDRR_GRANULARITY_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: PN_QOS_PRI_CTL_Port_5 :: SCHEDULER_SELECT [02:00] */
-#define BCHP_SWITCH_CORE_PN_QOS_PRI_CTL_Port_5_SCHEDULER_SELECT_MASK 0x00000007
-#define BCHP_SWITCH_CORE_PN_QOS_PRI_CTL_Port_5_SCHEDULER_SELECT_SHIFT 0
-#define BCHP_SWITCH_CORE_PN_QOS_PRI_CTL_Port_5_SCHEDULER_SELECT_DEFAULT 0x00000000
-
-/***************************************************************************
- *P7_QOS_PRI_CTL - Port 7, QOS Priority Control Register
- ***************************************************************************/
-/* SWITCH_CORE :: P7_QOS_PRI_CTL :: reserved_for_padding0 [31:08] */
-#define BCHP_SWITCH_CORE_P7_QOS_PRI_CTL_reserved_for_padding0_MASK 0xffffff00
-#define BCHP_SWITCH_CORE_P7_QOS_PRI_CTL_reserved_for_padding0_SHIFT 8
-
-/* SWITCH_CORE :: P7_QOS_PRI_CTL :: TXQ_EMPTY_STATUS_SELECT [07:07] */
-#define BCHP_SWITCH_CORE_P7_QOS_PRI_CTL_TXQ_EMPTY_STATUS_SELECT_MASK 0x00000080
-#define BCHP_SWITCH_CORE_P7_QOS_PRI_CTL_TXQ_EMPTY_STATUS_SELECT_SHIFT 7
-#define BCHP_SWITCH_CORE_P7_QOS_PRI_CTL_TXQ_EMPTY_STATUS_SELECT_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: P7_QOS_PRI_CTL :: SWITCH_RESV [06:06] */
-#define BCHP_SWITCH_CORE_P7_QOS_PRI_CTL_SWITCH_RESV_MASK 0x00000040
-#define BCHP_SWITCH_CORE_P7_QOS_PRI_CTL_SWITCH_RESV_SHIFT 6
-#define BCHP_SWITCH_CORE_P7_QOS_PRI_CTL_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: P7_QOS_PRI_CTL :: NEGATIVE_CREDIT_CLR_DISABLE [05:05] */
-#define BCHP_SWITCH_CORE_P7_QOS_PRI_CTL_NEGATIVE_CREDIT_CLR_DISABLE_MASK 0x00000020
-#define BCHP_SWITCH_CORE_P7_QOS_PRI_CTL_NEGATIVE_CREDIT_CLR_DISABLE_SHIFT 5
-#define BCHP_SWITCH_CORE_P7_QOS_PRI_CTL_NEGATIVE_CREDIT_CLR_DISABLE_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: P7_QOS_PRI_CTL :: ROUNDROBIN_BURST_MODE_ENABLE [04:04] */
-#define BCHP_SWITCH_CORE_P7_QOS_PRI_CTL_ROUNDROBIN_BURST_MODE_ENABLE_MASK 0x00000010
-#define BCHP_SWITCH_CORE_P7_QOS_PRI_CTL_ROUNDROBIN_BURST_MODE_ENABLE_SHIFT 4
-#define BCHP_SWITCH_CORE_P7_QOS_PRI_CTL_ROUNDROBIN_BURST_MODE_ENABLE_DEFAULT 0x00000001
-
-/* SWITCH_CORE :: P7_QOS_PRI_CTL :: WDRR_GRANULARITY [03:03] */
-#define BCHP_SWITCH_CORE_P7_QOS_PRI_CTL_WDRR_GRANULARITY_MASK 0x00000008
-#define BCHP_SWITCH_CORE_P7_QOS_PRI_CTL_WDRR_GRANULARITY_SHIFT 3
-#define BCHP_SWITCH_CORE_P7_QOS_PRI_CTL_WDRR_GRANULARITY_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: P7_QOS_PRI_CTL :: SCHEDULER_SELECT [02:00] */
-#define BCHP_SWITCH_CORE_P7_QOS_PRI_CTL_SCHEDULER_SELECT_MASK 0x00000007
-#define BCHP_SWITCH_CORE_P7_QOS_PRI_CTL_SCHEDULER_SELECT_SHIFT 0
-#define BCHP_SWITCH_CORE_P7_QOS_PRI_CTL_SCHEDULER_SELECT_DEFAULT 0x00000000
-
-/***************************************************************************
- *IMP_QOS_PRI_CTL - Port 8, QOS Priority Control Register
- ***************************************************************************/
-/* SWITCH_CORE :: IMP_QOS_PRI_CTL :: reserved_for_padding0 [31:08] */
-#define BCHP_SWITCH_CORE_IMP_QOS_PRI_CTL_reserved_for_padding0_MASK 0xffffff00
-#define BCHP_SWITCH_CORE_IMP_QOS_PRI_CTL_reserved_for_padding0_SHIFT 8
-
-/* SWITCH_CORE :: IMP_QOS_PRI_CTL :: TXQ_EMPTY_STATUS_SELECT [07:07] */
-#define BCHP_SWITCH_CORE_IMP_QOS_PRI_CTL_TXQ_EMPTY_STATUS_SELECT_MASK 0x00000080
-#define BCHP_SWITCH_CORE_IMP_QOS_PRI_CTL_TXQ_EMPTY_STATUS_SELECT_SHIFT 7
-#define BCHP_SWITCH_CORE_IMP_QOS_PRI_CTL_TXQ_EMPTY_STATUS_SELECT_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: IMP_QOS_PRI_CTL :: SWITCH_RESV [06:06] */
-#define BCHP_SWITCH_CORE_IMP_QOS_PRI_CTL_SWITCH_RESV_MASK 0x00000040
-#define BCHP_SWITCH_CORE_IMP_QOS_PRI_CTL_SWITCH_RESV_SHIFT 6
-#define BCHP_SWITCH_CORE_IMP_QOS_PRI_CTL_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: IMP_QOS_PRI_CTL :: NEGATIVE_CREDIT_CLR_DISABLE [05:05] */
-#define BCHP_SWITCH_CORE_IMP_QOS_PRI_CTL_NEGATIVE_CREDIT_CLR_DISABLE_MASK 0x00000020
-#define BCHP_SWITCH_CORE_IMP_QOS_PRI_CTL_NEGATIVE_CREDIT_CLR_DISABLE_SHIFT 5
-#define BCHP_SWITCH_CORE_IMP_QOS_PRI_CTL_NEGATIVE_CREDIT_CLR_DISABLE_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: IMP_QOS_PRI_CTL :: ROUNDROBIN_BURST_MODE_ENABLE [04:04] */
-#define BCHP_SWITCH_CORE_IMP_QOS_PRI_CTL_ROUNDROBIN_BURST_MODE_ENABLE_MASK 0x00000010
-#define BCHP_SWITCH_CORE_IMP_QOS_PRI_CTL_ROUNDROBIN_BURST_MODE_ENABLE_SHIFT 4
-#define BCHP_SWITCH_CORE_IMP_QOS_PRI_CTL_ROUNDROBIN_BURST_MODE_ENABLE_DEFAULT 0x00000001
-
-/* SWITCH_CORE :: IMP_QOS_PRI_CTL :: WDRR_GRANULARITY [03:03] */
-#define BCHP_SWITCH_CORE_IMP_QOS_PRI_CTL_WDRR_GRANULARITY_MASK 0x00000008
-#define BCHP_SWITCH_CORE_IMP_QOS_PRI_CTL_WDRR_GRANULARITY_SHIFT 3
-#define BCHP_SWITCH_CORE_IMP_QOS_PRI_CTL_WDRR_GRANULARITY_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: IMP_QOS_PRI_CTL :: SCHEDULER_SELECT [02:00] */
-#define BCHP_SWITCH_CORE_IMP_QOS_PRI_CTL_SCHEDULER_SELECT_MASK 0x00000007
-#define BCHP_SWITCH_CORE_IMP_QOS_PRI_CTL_SCHEDULER_SELECT_SHIFT 0
-#define BCHP_SWITCH_CORE_IMP_QOS_PRI_CTL_SCHEDULER_SELECT_DEFAULT 0x00000000
-
-/***************************************************************************
- *PN_QOS_WEIGHT_Port_0 - Port N, QOS Weight Register
- ***************************************************************************/
-/* SWITCH_CORE :: PN_QOS_WEIGHT_Port_0 :: Q7_WEIGHT [63:56] */
-#define BCHP_SWITCH_CORE_PN_QOS_WEIGHT_Port_0_Q7_WEIGHT_MASK 0x00000000ff000000
-#define BCHP_SWITCH_CORE_PN_QOS_WEIGHT_Port_0_Q7_WEIGHT_SHIFT 56
-#define BCHP_SWITCH_CORE_PN_QOS_WEIGHT_Port_0_Q7_WEIGHT_DEFAULT 0x0000000000000001
-
-/* SWITCH_CORE :: PN_QOS_WEIGHT_Port_0 :: Q6_WEIGHT [55:48] */
-#define BCHP_SWITCH_CORE_PN_QOS_WEIGHT_Port_0_Q6_WEIGHT_MASK 0x0000000000ff0000
-#define BCHP_SWITCH_CORE_PN_QOS_WEIGHT_Port_0_Q6_WEIGHT_SHIFT 48
-#define BCHP_SWITCH_CORE_PN_QOS_WEIGHT_Port_0_Q6_WEIGHT_DEFAULT 0x0000000000000001
-
-/* SWITCH_CORE :: PN_QOS_WEIGHT_Port_0 :: Q5_WEIGHT [47:40] */
-#define BCHP_SWITCH_CORE_PN_QOS_WEIGHT_Port_0_Q5_WEIGHT_MASK 0x000000000000ff00
-#define BCHP_SWITCH_CORE_PN_QOS_WEIGHT_Port_0_Q5_WEIGHT_SHIFT 40
-#define BCHP_SWITCH_CORE_PN_QOS_WEIGHT_Port_0_Q5_WEIGHT_DEFAULT 0x0000000000000001
-
-/* SWITCH_CORE :: PN_QOS_WEIGHT_Port_0 :: Q4_WEIGHT [39:32] */
-#define BCHP_SWITCH_CORE_PN_QOS_WEIGHT_Port_0_Q4_WEIGHT_MASK 0x00000000000000ff
-#define BCHP_SWITCH_CORE_PN_QOS_WEIGHT_Port_0_Q4_WEIGHT_SHIFT 32
-#define BCHP_SWITCH_CORE_PN_QOS_WEIGHT_Port_0_Q4_WEIGHT_DEFAULT 0x0000000000000001
-
-/* SWITCH_CORE :: PN_QOS_WEIGHT_Port_0 :: Q3_WEIGHT [31:24] */
-#define BCHP_SWITCH_CORE_PN_QOS_WEIGHT_Port_0_Q3_WEIGHT_MASK 0x00000000ff000000
-#define BCHP_SWITCH_CORE_PN_QOS_WEIGHT_Port_0_Q3_WEIGHT_SHIFT 24
-#define BCHP_SWITCH_CORE_PN_QOS_WEIGHT_Port_0_Q3_WEIGHT_DEFAULT 0x0000000000000001
-
-/* SWITCH_CORE :: PN_QOS_WEIGHT_Port_0 :: Q2_WEIGHT [23:16] */
-#define BCHP_SWITCH_CORE_PN_QOS_WEIGHT_Port_0_Q2_WEIGHT_MASK 0x0000000000ff0000
-#define BCHP_SWITCH_CORE_PN_QOS_WEIGHT_Port_0_Q2_WEIGHT_SHIFT 16
-#define BCHP_SWITCH_CORE_PN_QOS_WEIGHT_Port_0_Q2_WEIGHT_DEFAULT 0x0000000000000001
-
-/* SWITCH_CORE :: PN_QOS_WEIGHT_Port_0 :: Q1_WEIGHT [15:08] */
-#define BCHP_SWITCH_CORE_PN_QOS_WEIGHT_Port_0_Q1_WEIGHT_MASK 0x000000000000ff00
-#define BCHP_SWITCH_CORE_PN_QOS_WEIGHT_Port_0_Q1_WEIGHT_SHIFT 8
-#define BCHP_SWITCH_CORE_PN_QOS_WEIGHT_Port_0_Q1_WEIGHT_DEFAULT 0x0000000000000001
-
-/* SWITCH_CORE :: PN_QOS_WEIGHT_Port_0 :: Q0_WEIGHT [07:00] */
-#define BCHP_SWITCH_CORE_PN_QOS_WEIGHT_Port_0_Q0_WEIGHT_MASK 0x00000000000000ff
-#define BCHP_SWITCH_CORE_PN_QOS_WEIGHT_Port_0_Q0_WEIGHT_SHIFT 0
-#define BCHP_SWITCH_CORE_PN_QOS_WEIGHT_Port_0_Q0_WEIGHT_DEFAULT 0x0000000000000001
-
-/***************************************************************************
- *PN_QOS_WEIGHT_Port_1 - Port N, QOS Weight Register
- ***************************************************************************/
-/* SWITCH_CORE :: PN_QOS_WEIGHT_Port_1 :: Q7_WEIGHT [63:56] */
-#define BCHP_SWITCH_CORE_PN_QOS_WEIGHT_Port_1_Q7_WEIGHT_MASK 0x00000000ff000000
-#define BCHP_SWITCH_CORE_PN_QOS_WEIGHT_Port_1_Q7_WEIGHT_SHIFT 56
-#define BCHP_SWITCH_CORE_PN_QOS_WEIGHT_Port_1_Q7_WEIGHT_DEFAULT 0x0000000000000001
-
-/* SWITCH_CORE :: PN_QOS_WEIGHT_Port_1 :: Q6_WEIGHT [55:48] */
-#define BCHP_SWITCH_CORE_PN_QOS_WEIGHT_Port_1_Q6_WEIGHT_MASK 0x0000000000ff0000
-#define BCHP_SWITCH_CORE_PN_QOS_WEIGHT_Port_1_Q6_WEIGHT_SHIFT 48
-#define BCHP_SWITCH_CORE_PN_QOS_WEIGHT_Port_1_Q6_WEIGHT_DEFAULT 0x0000000000000001
-
-/* SWITCH_CORE :: PN_QOS_WEIGHT_Port_1 :: Q5_WEIGHT [47:40] */
-#define BCHP_SWITCH_CORE_PN_QOS_WEIGHT_Port_1_Q5_WEIGHT_MASK 0x000000000000ff00
-#define BCHP_SWITCH_CORE_PN_QOS_WEIGHT_Port_1_Q5_WEIGHT_SHIFT 40
-#define BCHP_SWITCH_CORE_PN_QOS_WEIGHT_Port_1_Q5_WEIGHT_DEFAULT 0x0000000000000001
-
-/* SWITCH_CORE :: PN_QOS_WEIGHT_Port_1 :: Q4_WEIGHT [39:32] */
-#define BCHP_SWITCH_CORE_PN_QOS_WEIGHT_Port_1_Q4_WEIGHT_MASK 0x00000000000000ff
-#define BCHP_SWITCH_CORE_PN_QOS_WEIGHT_Port_1_Q4_WEIGHT_SHIFT 32
-#define BCHP_SWITCH_CORE_PN_QOS_WEIGHT_Port_1_Q4_WEIGHT_DEFAULT 0x0000000000000001
-
-/* SWITCH_CORE :: PN_QOS_WEIGHT_Port_1 :: Q3_WEIGHT [31:24] */
-#define BCHP_SWITCH_CORE_PN_QOS_WEIGHT_Port_1_Q3_WEIGHT_MASK 0x00000000ff000000
-#define BCHP_SWITCH_CORE_PN_QOS_WEIGHT_Port_1_Q3_WEIGHT_SHIFT 24
-#define BCHP_SWITCH_CORE_PN_QOS_WEIGHT_Port_1_Q3_WEIGHT_DEFAULT 0x0000000000000001
-
-/* SWITCH_CORE :: PN_QOS_WEIGHT_Port_1 :: Q2_WEIGHT [23:16] */
-#define BCHP_SWITCH_CORE_PN_QOS_WEIGHT_Port_1_Q2_WEIGHT_MASK 0x0000000000ff0000
-#define BCHP_SWITCH_CORE_PN_QOS_WEIGHT_Port_1_Q2_WEIGHT_SHIFT 16
-#define BCHP_SWITCH_CORE_PN_QOS_WEIGHT_Port_1_Q2_WEIGHT_DEFAULT 0x0000000000000001
-
-/* SWITCH_CORE :: PN_QOS_WEIGHT_Port_1 :: Q1_WEIGHT [15:08] */
-#define BCHP_SWITCH_CORE_PN_QOS_WEIGHT_Port_1_Q1_WEIGHT_MASK 0x000000000000ff00
-#define BCHP_SWITCH_CORE_PN_QOS_WEIGHT_Port_1_Q1_WEIGHT_SHIFT 8
-#define BCHP_SWITCH_CORE_PN_QOS_WEIGHT_Port_1_Q1_WEIGHT_DEFAULT 0x0000000000000001
-
-/* SWITCH_CORE :: PN_QOS_WEIGHT_Port_1 :: Q0_WEIGHT [07:00] */
-#define BCHP_SWITCH_CORE_PN_QOS_WEIGHT_Port_1_Q0_WEIGHT_MASK 0x00000000000000ff
-#define BCHP_SWITCH_CORE_PN_QOS_WEIGHT_Port_1_Q0_WEIGHT_SHIFT 0
-#define BCHP_SWITCH_CORE_PN_QOS_WEIGHT_Port_1_Q0_WEIGHT_DEFAULT 0x0000000000000001
-
-/***************************************************************************
- *PN_QOS_WEIGHT_Port_2 - Port N, QOS Weight Register
- ***************************************************************************/
-/* SWITCH_CORE :: PN_QOS_WEIGHT_Port_2 :: Q7_WEIGHT [63:56] */
-#define BCHP_SWITCH_CORE_PN_QOS_WEIGHT_Port_2_Q7_WEIGHT_MASK 0x00000000ff000000
-#define BCHP_SWITCH_CORE_PN_QOS_WEIGHT_Port_2_Q7_WEIGHT_SHIFT 56
-#define BCHP_SWITCH_CORE_PN_QOS_WEIGHT_Port_2_Q7_WEIGHT_DEFAULT 0x0000000000000001
-
-/* SWITCH_CORE :: PN_QOS_WEIGHT_Port_2 :: Q6_WEIGHT [55:48] */
-#define BCHP_SWITCH_CORE_PN_QOS_WEIGHT_Port_2_Q6_WEIGHT_MASK 0x0000000000ff0000
-#define BCHP_SWITCH_CORE_PN_QOS_WEIGHT_Port_2_Q6_WEIGHT_SHIFT 48
-#define BCHP_SWITCH_CORE_PN_QOS_WEIGHT_Port_2_Q6_WEIGHT_DEFAULT 0x0000000000000001
-
-/* SWITCH_CORE :: PN_QOS_WEIGHT_Port_2 :: Q5_WEIGHT [47:40] */
-#define BCHP_SWITCH_CORE_PN_QOS_WEIGHT_Port_2_Q5_WEIGHT_MASK 0x000000000000ff00
-#define BCHP_SWITCH_CORE_PN_QOS_WEIGHT_Port_2_Q5_WEIGHT_SHIFT 40
-#define BCHP_SWITCH_CORE_PN_QOS_WEIGHT_Port_2_Q5_WEIGHT_DEFAULT 0x0000000000000001
-
-/* SWITCH_CORE :: PN_QOS_WEIGHT_Port_2 :: Q4_WEIGHT [39:32] */
-#define BCHP_SWITCH_CORE_PN_QOS_WEIGHT_Port_2_Q4_WEIGHT_MASK 0x00000000000000ff
-#define BCHP_SWITCH_CORE_PN_QOS_WEIGHT_Port_2_Q4_WEIGHT_SHIFT 32
-#define BCHP_SWITCH_CORE_PN_QOS_WEIGHT_Port_2_Q4_WEIGHT_DEFAULT 0x0000000000000001
-
-/* SWITCH_CORE :: PN_QOS_WEIGHT_Port_2 :: Q3_WEIGHT [31:24] */
-#define BCHP_SWITCH_CORE_PN_QOS_WEIGHT_Port_2_Q3_WEIGHT_MASK 0x00000000ff000000
-#define BCHP_SWITCH_CORE_PN_QOS_WEIGHT_Port_2_Q3_WEIGHT_SHIFT 24
-#define BCHP_SWITCH_CORE_PN_QOS_WEIGHT_Port_2_Q3_WEIGHT_DEFAULT 0x0000000000000001
-
-/* SWITCH_CORE :: PN_QOS_WEIGHT_Port_2 :: Q2_WEIGHT [23:16] */
-#define BCHP_SWITCH_CORE_PN_QOS_WEIGHT_Port_2_Q2_WEIGHT_MASK 0x0000000000ff0000
-#define BCHP_SWITCH_CORE_PN_QOS_WEIGHT_Port_2_Q2_WEIGHT_SHIFT 16
-#define BCHP_SWITCH_CORE_PN_QOS_WEIGHT_Port_2_Q2_WEIGHT_DEFAULT 0x0000000000000001
-
-/* SWITCH_CORE :: PN_QOS_WEIGHT_Port_2 :: Q1_WEIGHT [15:08] */
-#define BCHP_SWITCH_CORE_PN_QOS_WEIGHT_Port_2_Q1_WEIGHT_MASK 0x000000000000ff00
-#define BCHP_SWITCH_CORE_PN_QOS_WEIGHT_Port_2_Q1_WEIGHT_SHIFT 8
-#define BCHP_SWITCH_CORE_PN_QOS_WEIGHT_Port_2_Q1_WEIGHT_DEFAULT 0x0000000000000001
-
-/* SWITCH_CORE :: PN_QOS_WEIGHT_Port_2 :: Q0_WEIGHT [07:00] */
-#define BCHP_SWITCH_CORE_PN_QOS_WEIGHT_Port_2_Q0_WEIGHT_MASK 0x00000000000000ff
-#define BCHP_SWITCH_CORE_PN_QOS_WEIGHT_Port_2_Q0_WEIGHT_SHIFT 0
-#define BCHP_SWITCH_CORE_PN_QOS_WEIGHT_Port_2_Q0_WEIGHT_DEFAULT 0x0000000000000001
-
-/***************************************************************************
- *PN_QOS_WEIGHT_Port_3 - Port N, QOS Weight Register
- ***************************************************************************/
-/* SWITCH_CORE :: PN_QOS_WEIGHT_Port_3 :: Q7_WEIGHT [63:56] */
-#define BCHP_SWITCH_CORE_PN_QOS_WEIGHT_Port_3_Q7_WEIGHT_MASK 0x00000000ff000000
-#define BCHP_SWITCH_CORE_PN_QOS_WEIGHT_Port_3_Q7_WEIGHT_SHIFT 56
-#define BCHP_SWITCH_CORE_PN_QOS_WEIGHT_Port_3_Q7_WEIGHT_DEFAULT 0x0000000000000001
-
-/* SWITCH_CORE :: PN_QOS_WEIGHT_Port_3 :: Q6_WEIGHT [55:48] */
-#define BCHP_SWITCH_CORE_PN_QOS_WEIGHT_Port_3_Q6_WEIGHT_MASK 0x0000000000ff0000
-#define BCHP_SWITCH_CORE_PN_QOS_WEIGHT_Port_3_Q6_WEIGHT_SHIFT 48
-#define BCHP_SWITCH_CORE_PN_QOS_WEIGHT_Port_3_Q6_WEIGHT_DEFAULT 0x0000000000000001
-
-/* SWITCH_CORE :: PN_QOS_WEIGHT_Port_3 :: Q5_WEIGHT [47:40] */
-#define BCHP_SWITCH_CORE_PN_QOS_WEIGHT_Port_3_Q5_WEIGHT_MASK 0x000000000000ff00
-#define BCHP_SWITCH_CORE_PN_QOS_WEIGHT_Port_3_Q5_WEIGHT_SHIFT 40
-#define BCHP_SWITCH_CORE_PN_QOS_WEIGHT_Port_3_Q5_WEIGHT_DEFAULT 0x0000000000000001
-
-/* SWITCH_CORE :: PN_QOS_WEIGHT_Port_3 :: Q4_WEIGHT [39:32] */
-#define BCHP_SWITCH_CORE_PN_QOS_WEIGHT_Port_3_Q4_WEIGHT_MASK 0x00000000000000ff
-#define BCHP_SWITCH_CORE_PN_QOS_WEIGHT_Port_3_Q4_WEIGHT_SHIFT 32
-#define BCHP_SWITCH_CORE_PN_QOS_WEIGHT_Port_3_Q4_WEIGHT_DEFAULT 0x0000000000000001
-
-/* SWITCH_CORE :: PN_QOS_WEIGHT_Port_3 :: Q3_WEIGHT [31:24] */
-#define BCHP_SWITCH_CORE_PN_QOS_WEIGHT_Port_3_Q3_WEIGHT_MASK 0x00000000ff000000
-#define BCHP_SWITCH_CORE_PN_QOS_WEIGHT_Port_3_Q3_WEIGHT_SHIFT 24
-#define BCHP_SWITCH_CORE_PN_QOS_WEIGHT_Port_3_Q3_WEIGHT_DEFAULT 0x0000000000000001
-
-/* SWITCH_CORE :: PN_QOS_WEIGHT_Port_3 :: Q2_WEIGHT [23:16] */
-#define BCHP_SWITCH_CORE_PN_QOS_WEIGHT_Port_3_Q2_WEIGHT_MASK 0x0000000000ff0000
-#define BCHP_SWITCH_CORE_PN_QOS_WEIGHT_Port_3_Q2_WEIGHT_SHIFT 16
-#define BCHP_SWITCH_CORE_PN_QOS_WEIGHT_Port_3_Q2_WEIGHT_DEFAULT 0x0000000000000001
-
-/* SWITCH_CORE :: PN_QOS_WEIGHT_Port_3 :: Q1_WEIGHT [15:08] */
-#define BCHP_SWITCH_CORE_PN_QOS_WEIGHT_Port_3_Q1_WEIGHT_MASK 0x000000000000ff00
-#define BCHP_SWITCH_CORE_PN_QOS_WEIGHT_Port_3_Q1_WEIGHT_SHIFT 8
-#define BCHP_SWITCH_CORE_PN_QOS_WEIGHT_Port_3_Q1_WEIGHT_DEFAULT 0x0000000000000001
-
-/* SWITCH_CORE :: PN_QOS_WEIGHT_Port_3 :: Q0_WEIGHT [07:00] */
-#define BCHP_SWITCH_CORE_PN_QOS_WEIGHT_Port_3_Q0_WEIGHT_MASK 0x00000000000000ff
-#define BCHP_SWITCH_CORE_PN_QOS_WEIGHT_Port_3_Q0_WEIGHT_SHIFT 0
-#define BCHP_SWITCH_CORE_PN_QOS_WEIGHT_Port_3_Q0_WEIGHT_DEFAULT 0x0000000000000001
-
-/***************************************************************************
- *PN_QOS_WEIGHT_Port_4 - Port N, QOS Weight Register
- ***************************************************************************/
-/* SWITCH_CORE :: PN_QOS_WEIGHT_Port_4 :: Q7_WEIGHT [63:56] */
-#define BCHP_SWITCH_CORE_PN_QOS_WEIGHT_Port_4_Q7_WEIGHT_MASK 0x00000000ff000000
-#define BCHP_SWITCH_CORE_PN_QOS_WEIGHT_Port_4_Q7_WEIGHT_SHIFT 56
-#define BCHP_SWITCH_CORE_PN_QOS_WEIGHT_Port_4_Q7_WEIGHT_DEFAULT 0x0000000000000001
-
-/* SWITCH_CORE :: PN_QOS_WEIGHT_Port_4 :: Q6_WEIGHT [55:48] */
-#define BCHP_SWITCH_CORE_PN_QOS_WEIGHT_Port_4_Q6_WEIGHT_MASK 0x0000000000ff0000
-#define BCHP_SWITCH_CORE_PN_QOS_WEIGHT_Port_4_Q6_WEIGHT_SHIFT 48
-#define BCHP_SWITCH_CORE_PN_QOS_WEIGHT_Port_4_Q6_WEIGHT_DEFAULT 0x0000000000000001
-
-/* SWITCH_CORE :: PN_QOS_WEIGHT_Port_4 :: Q5_WEIGHT [47:40] */
-#define BCHP_SWITCH_CORE_PN_QOS_WEIGHT_Port_4_Q5_WEIGHT_MASK 0x000000000000ff00
-#define BCHP_SWITCH_CORE_PN_QOS_WEIGHT_Port_4_Q5_WEIGHT_SHIFT 40
-#define BCHP_SWITCH_CORE_PN_QOS_WEIGHT_Port_4_Q5_WEIGHT_DEFAULT 0x0000000000000001
-
-/* SWITCH_CORE :: PN_QOS_WEIGHT_Port_4 :: Q4_WEIGHT [39:32] */
-#define BCHP_SWITCH_CORE_PN_QOS_WEIGHT_Port_4_Q4_WEIGHT_MASK 0x00000000000000ff
-#define BCHP_SWITCH_CORE_PN_QOS_WEIGHT_Port_4_Q4_WEIGHT_SHIFT 32
-#define BCHP_SWITCH_CORE_PN_QOS_WEIGHT_Port_4_Q4_WEIGHT_DEFAULT 0x0000000000000001
-
-/* SWITCH_CORE :: PN_QOS_WEIGHT_Port_4 :: Q3_WEIGHT [31:24] */
-#define BCHP_SWITCH_CORE_PN_QOS_WEIGHT_Port_4_Q3_WEIGHT_MASK 0x00000000ff000000
-#define BCHP_SWITCH_CORE_PN_QOS_WEIGHT_Port_4_Q3_WEIGHT_SHIFT 24
-#define BCHP_SWITCH_CORE_PN_QOS_WEIGHT_Port_4_Q3_WEIGHT_DEFAULT 0x0000000000000001
-
-/* SWITCH_CORE :: PN_QOS_WEIGHT_Port_4 :: Q2_WEIGHT [23:16] */
-#define BCHP_SWITCH_CORE_PN_QOS_WEIGHT_Port_4_Q2_WEIGHT_MASK 0x0000000000ff0000
-#define BCHP_SWITCH_CORE_PN_QOS_WEIGHT_Port_4_Q2_WEIGHT_SHIFT 16
-#define BCHP_SWITCH_CORE_PN_QOS_WEIGHT_Port_4_Q2_WEIGHT_DEFAULT 0x0000000000000001
-
-/* SWITCH_CORE :: PN_QOS_WEIGHT_Port_4 :: Q1_WEIGHT [15:08] */
-#define BCHP_SWITCH_CORE_PN_QOS_WEIGHT_Port_4_Q1_WEIGHT_MASK 0x000000000000ff00
-#define BCHP_SWITCH_CORE_PN_QOS_WEIGHT_Port_4_Q1_WEIGHT_SHIFT 8
-#define BCHP_SWITCH_CORE_PN_QOS_WEIGHT_Port_4_Q1_WEIGHT_DEFAULT 0x0000000000000001
-
-/* SWITCH_CORE :: PN_QOS_WEIGHT_Port_4 :: Q0_WEIGHT [07:00] */
-#define BCHP_SWITCH_CORE_PN_QOS_WEIGHT_Port_4_Q0_WEIGHT_MASK 0x00000000000000ff
-#define BCHP_SWITCH_CORE_PN_QOS_WEIGHT_Port_4_Q0_WEIGHT_SHIFT 0
-#define BCHP_SWITCH_CORE_PN_QOS_WEIGHT_Port_4_Q0_WEIGHT_DEFAULT 0x0000000000000001
-
-/***************************************************************************
- *PN_QOS_WEIGHT_Port_5 - Port N, QOS Weight Register
- ***************************************************************************/
-/* SWITCH_CORE :: PN_QOS_WEIGHT_Port_5 :: Q7_WEIGHT [63:56] */
-#define BCHP_SWITCH_CORE_PN_QOS_WEIGHT_Port_5_Q7_WEIGHT_MASK 0x00000000ff000000
-#define BCHP_SWITCH_CORE_PN_QOS_WEIGHT_Port_5_Q7_WEIGHT_SHIFT 56
-#define BCHP_SWITCH_CORE_PN_QOS_WEIGHT_Port_5_Q7_WEIGHT_DEFAULT 0x0000000000000001
-
-/* SWITCH_CORE :: PN_QOS_WEIGHT_Port_5 :: Q6_WEIGHT [55:48] */
-#define BCHP_SWITCH_CORE_PN_QOS_WEIGHT_Port_5_Q6_WEIGHT_MASK 0x0000000000ff0000
-#define BCHP_SWITCH_CORE_PN_QOS_WEIGHT_Port_5_Q6_WEIGHT_SHIFT 48
-#define BCHP_SWITCH_CORE_PN_QOS_WEIGHT_Port_5_Q6_WEIGHT_DEFAULT 0x0000000000000001
-
-/* SWITCH_CORE :: PN_QOS_WEIGHT_Port_5 :: Q5_WEIGHT [47:40] */
-#define BCHP_SWITCH_CORE_PN_QOS_WEIGHT_Port_5_Q5_WEIGHT_MASK 0x000000000000ff00
-#define BCHP_SWITCH_CORE_PN_QOS_WEIGHT_Port_5_Q5_WEIGHT_SHIFT 40
-#define BCHP_SWITCH_CORE_PN_QOS_WEIGHT_Port_5_Q5_WEIGHT_DEFAULT 0x0000000000000001
-
-/* SWITCH_CORE :: PN_QOS_WEIGHT_Port_5 :: Q4_WEIGHT [39:32] */
-#define BCHP_SWITCH_CORE_PN_QOS_WEIGHT_Port_5_Q4_WEIGHT_MASK 0x00000000000000ff
-#define BCHP_SWITCH_CORE_PN_QOS_WEIGHT_Port_5_Q4_WEIGHT_SHIFT 32
-#define BCHP_SWITCH_CORE_PN_QOS_WEIGHT_Port_5_Q4_WEIGHT_DEFAULT 0x0000000000000001
-
-/* SWITCH_CORE :: PN_QOS_WEIGHT_Port_5 :: Q3_WEIGHT [31:24] */
-#define BCHP_SWITCH_CORE_PN_QOS_WEIGHT_Port_5_Q3_WEIGHT_MASK 0x00000000ff000000
-#define BCHP_SWITCH_CORE_PN_QOS_WEIGHT_Port_5_Q3_WEIGHT_SHIFT 24
-#define BCHP_SWITCH_CORE_PN_QOS_WEIGHT_Port_5_Q3_WEIGHT_DEFAULT 0x0000000000000001
-
-/* SWITCH_CORE :: PN_QOS_WEIGHT_Port_5 :: Q2_WEIGHT [23:16] */
-#define BCHP_SWITCH_CORE_PN_QOS_WEIGHT_Port_5_Q2_WEIGHT_MASK 0x0000000000ff0000
-#define BCHP_SWITCH_CORE_PN_QOS_WEIGHT_Port_5_Q2_WEIGHT_SHIFT 16
-#define BCHP_SWITCH_CORE_PN_QOS_WEIGHT_Port_5_Q2_WEIGHT_DEFAULT 0x0000000000000001
-
-/* SWITCH_CORE :: PN_QOS_WEIGHT_Port_5 :: Q1_WEIGHT [15:08] */
-#define BCHP_SWITCH_CORE_PN_QOS_WEIGHT_Port_5_Q1_WEIGHT_MASK 0x000000000000ff00
-#define BCHP_SWITCH_CORE_PN_QOS_WEIGHT_Port_5_Q1_WEIGHT_SHIFT 8
-#define BCHP_SWITCH_CORE_PN_QOS_WEIGHT_Port_5_Q1_WEIGHT_DEFAULT 0x0000000000000001
-
-/* SWITCH_CORE :: PN_QOS_WEIGHT_Port_5 :: Q0_WEIGHT [07:00] */
-#define BCHP_SWITCH_CORE_PN_QOS_WEIGHT_Port_5_Q0_WEIGHT_MASK 0x00000000000000ff
-#define BCHP_SWITCH_CORE_PN_QOS_WEIGHT_Port_5_Q0_WEIGHT_SHIFT 0
-#define BCHP_SWITCH_CORE_PN_QOS_WEIGHT_Port_5_Q0_WEIGHT_DEFAULT 0x0000000000000001
-
-/***************************************************************************
- *P7_QOS_WEIGHT - Port 7, QOS Weight Register
- ***************************************************************************/
-/* SWITCH_CORE :: P7_QOS_WEIGHT :: Q7_WEIGHT [63:56] */
-#define BCHP_SWITCH_CORE_P7_QOS_WEIGHT_Q7_WEIGHT_MASK 0x00000000ff000000
-#define BCHP_SWITCH_CORE_P7_QOS_WEIGHT_Q7_WEIGHT_SHIFT 56
-#define BCHP_SWITCH_CORE_P7_QOS_WEIGHT_Q7_WEIGHT_DEFAULT 0x0000000000000001
-
-/* SWITCH_CORE :: P7_QOS_WEIGHT :: Q6_WEIGHT [55:48] */
-#define BCHP_SWITCH_CORE_P7_QOS_WEIGHT_Q6_WEIGHT_MASK 0x0000000000ff0000
-#define BCHP_SWITCH_CORE_P7_QOS_WEIGHT_Q6_WEIGHT_SHIFT 48
-#define BCHP_SWITCH_CORE_P7_QOS_WEIGHT_Q6_WEIGHT_DEFAULT 0x0000000000000001
-
-/* SWITCH_CORE :: P7_QOS_WEIGHT :: Q5_WEIGHT [47:40] */
-#define BCHP_SWITCH_CORE_P7_QOS_WEIGHT_Q5_WEIGHT_MASK 0x000000000000ff00
-#define BCHP_SWITCH_CORE_P7_QOS_WEIGHT_Q5_WEIGHT_SHIFT 40
-#define BCHP_SWITCH_CORE_P7_QOS_WEIGHT_Q5_WEIGHT_DEFAULT 0x0000000000000001
-
-/* SWITCH_CORE :: P7_QOS_WEIGHT :: Q4_WEIGHT [39:32] */
-#define BCHP_SWITCH_CORE_P7_QOS_WEIGHT_Q4_WEIGHT_MASK 0x00000000000000ff
-#define BCHP_SWITCH_CORE_P7_QOS_WEIGHT_Q4_WEIGHT_SHIFT 32
-#define BCHP_SWITCH_CORE_P7_QOS_WEIGHT_Q4_WEIGHT_DEFAULT 0x0000000000000001
-
-/* SWITCH_CORE :: P7_QOS_WEIGHT :: Q3_WEIGHT [31:24] */
-#define BCHP_SWITCH_CORE_P7_QOS_WEIGHT_Q3_WEIGHT_MASK 0x00000000ff000000
-#define BCHP_SWITCH_CORE_P7_QOS_WEIGHT_Q3_WEIGHT_SHIFT 24
-#define BCHP_SWITCH_CORE_P7_QOS_WEIGHT_Q3_WEIGHT_DEFAULT 0x0000000000000001
-
-/* SWITCH_CORE :: P7_QOS_WEIGHT :: Q2_WEIGHT [23:16] */
-#define BCHP_SWITCH_CORE_P7_QOS_WEIGHT_Q2_WEIGHT_MASK 0x0000000000ff0000
-#define BCHP_SWITCH_CORE_P7_QOS_WEIGHT_Q2_WEIGHT_SHIFT 16
-#define BCHP_SWITCH_CORE_P7_QOS_WEIGHT_Q2_WEIGHT_DEFAULT 0x0000000000000001
-
-/* SWITCH_CORE :: P7_QOS_WEIGHT :: Q1_WEIGHT [15:08] */
-#define BCHP_SWITCH_CORE_P7_QOS_WEIGHT_Q1_WEIGHT_MASK 0x000000000000ff00
-#define BCHP_SWITCH_CORE_P7_QOS_WEIGHT_Q1_WEIGHT_SHIFT 8
-#define BCHP_SWITCH_CORE_P7_QOS_WEIGHT_Q1_WEIGHT_DEFAULT 0x0000000000000001
-
-/* SWITCH_CORE :: P7_QOS_WEIGHT :: Q0_WEIGHT [07:00] */
-#define BCHP_SWITCH_CORE_P7_QOS_WEIGHT_Q0_WEIGHT_MASK 0x00000000000000ff
-#define BCHP_SWITCH_CORE_P7_QOS_WEIGHT_Q0_WEIGHT_SHIFT 0
-#define BCHP_SWITCH_CORE_P7_QOS_WEIGHT_Q0_WEIGHT_DEFAULT 0x0000000000000001
-
-/***************************************************************************
- *IMP_QOS_WEIGHT - Port 8, QOS Weight Register
- ***************************************************************************/
-/* SWITCH_CORE :: IMP_QOS_WEIGHT :: Q7_WEIGHT [63:56] */
-#define BCHP_SWITCH_CORE_IMP_QOS_WEIGHT_Q7_WEIGHT_MASK 0x00000000ff000000
-#define BCHP_SWITCH_CORE_IMP_QOS_WEIGHT_Q7_WEIGHT_SHIFT 56
-#define BCHP_SWITCH_CORE_IMP_QOS_WEIGHT_Q7_WEIGHT_DEFAULT 0x0000000000000001
-
-/* SWITCH_CORE :: IMP_QOS_WEIGHT :: Q6_WEIGHT [55:48] */
-#define BCHP_SWITCH_CORE_IMP_QOS_WEIGHT_Q6_WEIGHT_MASK 0x0000000000ff0000
-#define BCHP_SWITCH_CORE_IMP_QOS_WEIGHT_Q6_WEIGHT_SHIFT 48
-#define BCHP_SWITCH_CORE_IMP_QOS_WEIGHT_Q6_WEIGHT_DEFAULT 0x0000000000000001
-
-/* SWITCH_CORE :: IMP_QOS_WEIGHT :: Q5_WEIGHT [47:40] */
-#define BCHP_SWITCH_CORE_IMP_QOS_WEIGHT_Q5_WEIGHT_MASK 0x000000000000ff00
-#define BCHP_SWITCH_CORE_IMP_QOS_WEIGHT_Q5_WEIGHT_SHIFT 40
-#define BCHP_SWITCH_CORE_IMP_QOS_WEIGHT_Q5_WEIGHT_DEFAULT 0x0000000000000001
-
-/* SWITCH_CORE :: IMP_QOS_WEIGHT :: Q4_WEIGHT [39:32] */
-#define BCHP_SWITCH_CORE_IMP_QOS_WEIGHT_Q4_WEIGHT_MASK 0x00000000000000ff
-#define BCHP_SWITCH_CORE_IMP_QOS_WEIGHT_Q4_WEIGHT_SHIFT 32
-#define BCHP_SWITCH_CORE_IMP_QOS_WEIGHT_Q4_WEIGHT_DEFAULT 0x0000000000000001
-
-/* SWITCH_CORE :: IMP_QOS_WEIGHT :: Q3_WEIGHT [31:24] */
-#define BCHP_SWITCH_CORE_IMP_QOS_WEIGHT_Q3_WEIGHT_MASK 0x00000000ff000000
-#define BCHP_SWITCH_CORE_IMP_QOS_WEIGHT_Q3_WEIGHT_SHIFT 24
-#define BCHP_SWITCH_CORE_IMP_QOS_WEIGHT_Q3_WEIGHT_DEFAULT 0x0000000000000001
-
-/* SWITCH_CORE :: IMP_QOS_WEIGHT :: Q2_WEIGHT [23:16] */
-#define BCHP_SWITCH_CORE_IMP_QOS_WEIGHT_Q2_WEIGHT_MASK 0x0000000000ff0000
-#define BCHP_SWITCH_CORE_IMP_QOS_WEIGHT_Q2_WEIGHT_SHIFT 16
-#define BCHP_SWITCH_CORE_IMP_QOS_WEIGHT_Q2_WEIGHT_DEFAULT 0x0000000000000001
-
-/* SWITCH_CORE :: IMP_QOS_WEIGHT :: Q1_WEIGHT [15:08] */
-#define BCHP_SWITCH_CORE_IMP_QOS_WEIGHT_Q1_WEIGHT_MASK 0x000000000000ff00
-#define BCHP_SWITCH_CORE_IMP_QOS_WEIGHT_Q1_WEIGHT_SHIFT 8
-#define BCHP_SWITCH_CORE_IMP_QOS_WEIGHT_Q1_WEIGHT_DEFAULT 0x0000000000000001
-
-/* SWITCH_CORE :: IMP_QOS_WEIGHT :: Q0_WEIGHT [07:00] */
-#define BCHP_SWITCH_CORE_IMP_QOS_WEIGHT_Q0_WEIGHT_MASK 0x00000000000000ff
-#define BCHP_SWITCH_CORE_IMP_QOS_WEIGHT_Q0_WEIGHT_SHIFT 0
-#define BCHP_SWITCH_CORE_IMP_QOS_WEIGHT_Q0_WEIGHT_DEFAULT 0x0000000000000001
-
-/***************************************************************************
- *PN_WDRR_PENALTY_Port_0 - Port N, WDRR Weight-Scaling Penalty Register (Not2Release)
- ***************************************************************************/
-/* SWITCH_CORE :: PN_WDRR_PENALTY_Port_0 :: reserved_for_padding0 [31:16] */
-#define BCHP_SWITCH_CORE_PN_WDRR_PENALTY_Port_0_reserved_for_padding0_MASK 0xffff0000
-#define BCHP_SWITCH_CORE_PN_WDRR_PENALTY_Port_0_reserved_for_padding0_SHIFT 16
-
-/* SWITCH_CORE :: PN_WDRR_PENALTY_Port_0 :: PEAK_ITERATION_CYCLES [15:08] */
-#define BCHP_SWITCH_CORE_PN_WDRR_PENALTY_Port_0_PEAK_ITERATION_CYCLES_MASK 0x0000ff00
-#define BCHP_SWITCH_CORE_PN_WDRR_PENALTY_Port_0_PEAK_ITERATION_CYCLES_SHIFT 8
-#define BCHP_SWITCH_CORE_PN_WDRR_PENALTY_Port_0_PEAK_ITERATION_CYCLES_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: PN_WDRR_PENALTY_Port_0 :: PEAK_BACK2BACK_PENALTY [07:00] */
-#define BCHP_SWITCH_CORE_PN_WDRR_PENALTY_Port_0_PEAK_BACK2BACK_PENALTY_MASK 0x000000ff
-#define BCHP_SWITCH_CORE_PN_WDRR_PENALTY_Port_0_PEAK_BACK2BACK_PENALTY_SHIFT 0
-#define BCHP_SWITCH_CORE_PN_WDRR_PENALTY_Port_0_PEAK_BACK2BACK_PENALTY_DEFAULT 0x00000000
-
-/***************************************************************************
- *PN_WDRR_PENALTY_Port_1 - Port N, WDRR Weight-Scaling Penalty Register (Not2Release)
- ***************************************************************************/
-/* SWITCH_CORE :: PN_WDRR_PENALTY_Port_1 :: reserved_for_padding0 [31:16] */
-#define BCHP_SWITCH_CORE_PN_WDRR_PENALTY_Port_1_reserved_for_padding0_MASK 0xffff0000
-#define BCHP_SWITCH_CORE_PN_WDRR_PENALTY_Port_1_reserved_for_padding0_SHIFT 16
-
-/* SWITCH_CORE :: PN_WDRR_PENALTY_Port_1 :: PEAK_ITERATION_CYCLES [15:08] */
-#define BCHP_SWITCH_CORE_PN_WDRR_PENALTY_Port_1_PEAK_ITERATION_CYCLES_MASK 0x0000ff00
-#define BCHP_SWITCH_CORE_PN_WDRR_PENALTY_Port_1_PEAK_ITERATION_CYCLES_SHIFT 8
-#define BCHP_SWITCH_CORE_PN_WDRR_PENALTY_Port_1_PEAK_ITERATION_CYCLES_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: PN_WDRR_PENALTY_Port_1 :: PEAK_BACK2BACK_PENALTY [07:00] */
-#define BCHP_SWITCH_CORE_PN_WDRR_PENALTY_Port_1_PEAK_BACK2BACK_PENALTY_MASK 0x000000ff
-#define BCHP_SWITCH_CORE_PN_WDRR_PENALTY_Port_1_PEAK_BACK2BACK_PENALTY_SHIFT 0
-#define BCHP_SWITCH_CORE_PN_WDRR_PENALTY_Port_1_PEAK_BACK2BACK_PENALTY_DEFAULT 0x00000000
-
-/***************************************************************************
- *PN_WDRR_PENALTY_Port_2 - Port N, WDRR Weight-Scaling Penalty Register (Not2Release)
- ***************************************************************************/
-/* SWITCH_CORE :: PN_WDRR_PENALTY_Port_2 :: reserved_for_padding0 [31:16] */
-#define BCHP_SWITCH_CORE_PN_WDRR_PENALTY_Port_2_reserved_for_padding0_MASK 0xffff0000
-#define BCHP_SWITCH_CORE_PN_WDRR_PENALTY_Port_2_reserved_for_padding0_SHIFT 16
-
-/* SWITCH_CORE :: PN_WDRR_PENALTY_Port_2 :: PEAK_ITERATION_CYCLES [15:08] */
-#define BCHP_SWITCH_CORE_PN_WDRR_PENALTY_Port_2_PEAK_ITERATION_CYCLES_MASK 0x0000ff00
-#define BCHP_SWITCH_CORE_PN_WDRR_PENALTY_Port_2_PEAK_ITERATION_CYCLES_SHIFT 8
-#define BCHP_SWITCH_CORE_PN_WDRR_PENALTY_Port_2_PEAK_ITERATION_CYCLES_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: PN_WDRR_PENALTY_Port_2 :: PEAK_BACK2BACK_PENALTY [07:00] */
-#define BCHP_SWITCH_CORE_PN_WDRR_PENALTY_Port_2_PEAK_BACK2BACK_PENALTY_MASK 0x000000ff
-#define BCHP_SWITCH_CORE_PN_WDRR_PENALTY_Port_2_PEAK_BACK2BACK_PENALTY_SHIFT 0
-#define BCHP_SWITCH_CORE_PN_WDRR_PENALTY_Port_2_PEAK_BACK2BACK_PENALTY_DEFAULT 0x00000000
-
-/***************************************************************************
- *PN_WDRR_PENALTY_Port_3 - Port N, WDRR Weight-Scaling Penalty Register (Not2Release)
- ***************************************************************************/
-/* SWITCH_CORE :: PN_WDRR_PENALTY_Port_3 :: reserved_for_padding0 [31:16] */
-#define BCHP_SWITCH_CORE_PN_WDRR_PENALTY_Port_3_reserved_for_padding0_MASK 0xffff0000
-#define BCHP_SWITCH_CORE_PN_WDRR_PENALTY_Port_3_reserved_for_padding0_SHIFT 16
-
-/* SWITCH_CORE :: PN_WDRR_PENALTY_Port_3 :: PEAK_ITERATION_CYCLES [15:08] */
-#define BCHP_SWITCH_CORE_PN_WDRR_PENALTY_Port_3_PEAK_ITERATION_CYCLES_MASK 0x0000ff00
-#define BCHP_SWITCH_CORE_PN_WDRR_PENALTY_Port_3_PEAK_ITERATION_CYCLES_SHIFT 8
-#define BCHP_SWITCH_CORE_PN_WDRR_PENALTY_Port_3_PEAK_ITERATION_CYCLES_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: PN_WDRR_PENALTY_Port_3 :: PEAK_BACK2BACK_PENALTY [07:00] */
-#define BCHP_SWITCH_CORE_PN_WDRR_PENALTY_Port_3_PEAK_BACK2BACK_PENALTY_MASK 0x000000ff
-#define BCHP_SWITCH_CORE_PN_WDRR_PENALTY_Port_3_PEAK_BACK2BACK_PENALTY_SHIFT 0
-#define BCHP_SWITCH_CORE_PN_WDRR_PENALTY_Port_3_PEAK_BACK2BACK_PENALTY_DEFAULT 0x00000000
-
-/***************************************************************************
- *PN_WDRR_PENALTY_Port_4 - Port N, WDRR Weight-Scaling Penalty Register (Not2Release)
- ***************************************************************************/
-/* SWITCH_CORE :: PN_WDRR_PENALTY_Port_4 :: reserved_for_padding0 [31:16] */
-#define BCHP_SWITCH_CORE_PN_WDRR_PENALTY_Port_4_reserved_for_padding0_MASK 0xffff0000
-#define BCHP_SWITCH_CORE_PN_WDRR_PENALTY_Port_4_reserved_for_padding0_SHIFT 16
-
-/* SWITCH_CORE :: PN_WDRR_PENALTY_Port_4 :: PEAK_ITERATION_CYCLES [15:08] */
-#define BCHP_SWITCH_CORE_PN_WDRR_PENALTY_Port_4_PEAK_ITERATION_CYCLES_MASK 0x0000ff00
-#define BCHP_SWITCH_CORE_PN_WDRR_PENALTY_Port_4_PEAK_ITERATION_CYCLES_SHIFT 8
-#define BCHP_SWITCH_CORE_PN_WDRR_PENALTY_Port_4_PEAK_ITERATION_CYCLES_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: PN_WDRR_PENALTY_Port_4 :: PEAK_BACK2BACK_PENALTY [07:00] */
-#define BCHP_SWITCH_CORE_PN_WDRR_PENALTY_Port_4_PEAK_BACK2BACK_PENALTY_MASK 0x000000ff
-#define BCHP_SWITCH_CORE_PN_WDRR_PENALTY_Port_4_PEAK_BACK2BACK_PENALTY_SHIFT 0
-#define BCHP_SWITCH_CORE_PN_WDRR_PENALTY_Port_4_PEAK_BACK2BACK_PENALTY_DEFAULT 0x00000000
-
-/***************************************************************************
- *PN_WDRR_PENALTY_Port_5 - Port N, WDRR Weight-Scaling Penalty Register (Not2Release)
- ***************************************************************************/
-/* SWITCH_CORE :: PN_WDRR_PENALTY_Port_5 :: reserved_for_padding0 [31:16] */
-#define BCHP_SWITCH_CORE_PN_WDRR_PENALTY_Port_5_reserved_for_padding0_MASK 0xffff0000
-#define BCHP_SWITCH_CORE_PN_WDRR_PENALTY_Port_5_reserved_for_padding0_SHIFT 16
-
-/* SWITCH_CORE :: PN_WDRR_PENALTY_Port_5 :: PEAK_ITERATION_CYCLES [15:08] */
-#define BCHP_SWITCH_CORE_PN_WDRR_PENALTY_Port_5_PEAK_ITERATION_CYCLES_MASK 0x0000ff00
-#define BCHP_SWITCH_CORE_PN_WDRR_PENALTY_Port_5_PEAK_ITERATION_CYCLES_SHIFT 8
-#define BCHP_SWITCH_CORE_PN_WDRR_PENALTY_Port_5_PEAK_ITERATION_CYCLES_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: PN_WDRR_PENALTY_Port_5 :: PEAK_BACK2BACK_PENALTY [07:00] */
-#define BCHP_SWITCH_CORE_PN_WDRR_PENALTY_Port_5_PEAK_BACK2BACK_PENALTY_MASK 0x000000ff
-#define BCHP_SWITCH_CORE_PN_WDRR_PENALTY_Port_5_PEAK_BACK2BACK_PENALTY_SHIFT 0
-#define BCHP_SWITCH_CORE_PN_WDRR_PENALTY_Port_5_PEAK_BACK2BACK_PENALTY_DEFAULT 0x00000000
-
-/***************************************************************************
- *P7_WDRR_PENALTY - Port 7, WDRR Weight-Scaling Penalty Register (Not2Release)
- ***************************************************************************/
-/* SWITCH_CORE :: P7_WDRR_PENALTY :: reserved_for_padding0 [31:16] */
-#define BCHP_SWITCH_CORE_P7_WDRR_PENALTY_reserved_for_padding0_MASK 0xffff0000
-#define BCHP_SWITCH_CORE_P7_WDRR_PENALTY_reserved_for_padding0_SHIFT 16
-
-/* SWITCH_CORE :: P7_WDRR_PENALTY :: PEAK_ITERATION_CYCLES [15:08] */
-#define BCHP_SWITCH_CORE_P7_WDRR_PENALTY_PEAK_ITERATION_CYCLES_MASK 0x0000ff00
-#define BCHP_SWITCH_CORE_P7_WDRR_PENALTY_PEAK_ITERATION_CYCLES_SHIFT 8
-#define BCHP_SWITCH_CORE_P7_WDRR_PENALTY_PEAK_ITERATION_CYCLES_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: P7_WDRR_PENALTY :: PEAK_BACK2BACK_PENALTY [07:00] */
-#define BCHP_SWITCH_CORE_P7_WDRR_PENALTY_PEAK_BACK2BACK_PENALTY_MASK 0x000000ff
-#define BCHP_SWITCH_CORE_P7_WDRR_PENALTY_PEAK_BACK2BACK_PENALTY_SHIFT 0
-#define BCHP_SWITCH_CORE_P7_WDRR_PENALTY_PEAK_BACK2BACK_PENALTY_DEFAULT 0x00000000
-
-/***************************************************************************
- *P8_WDRR_PENALTY - Port 8, WDRR Weight-Scaling Penalty Register (Not2Release)
- ***************************************************************************/
-/* SWITCH_CORE :: P8_WDRR_PENALTY :: reserved_for_padding0 [31:16] */
-#define BCHP_SWITCH_CORE_P8_WDRR_PENALTY_reserved_for_padding0_MASK 0xffff0000
-#define BCHP_SWITCH_CORE_P8_WDRR_PENALTY_reserved_for_padding0_SHIFT 16
-
-/* SWITCH_CORE :: P8_WDRR_PENALTY :: PEAK_ITERATION_CYCLES [15:08] */
-#define BCHP_SWITCH_CORE_P8_WDRR_PENALTY_PEAK_ITERATION_CYCLES_MASK 0x0000ff00
-#define BCHP_SWITCH_CORE_P8_WDRR_PENALTY_PEAK_ITERATION_CYCLES_SHIFT 8
-#define BCHP_SWITCH_CORE_P8_WDRR_PENALTY_PEAK_ITERATION_CYCLES_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: P8_WDRR_PENALTY :: PEAK_BACK2BACK_PENALTY [07:00] */
-#define BCHP_SWITCH_CORE_P8_WDRR_PENALTY_PEAK_BACK2BACK_PENALTY_MASK 0x000000ff
-#define BCHP_SWITCH_CORE_P8_WDRR_PENALTY_PEAK_BACK2BACK_PENALTY_SHIFT 0
-#define BCHP_SWITCH_CORE_P8_WDRR_PENALTY_PEAK_BACK2BACK_PENALTY_DEFAULT 0x00000000
-
-/***************************************************************************
- *SCHEDULER_REG_SPARE0 - Spare 0 Register (Not2Release)
- ***************************************************************************/
-/* SWITCH_CORE :: SCHEDULER_REG_SPARE0 :: SCHEDULER_REG_SPARE0 [31:00] */
-#define BCHP_SWITCH_CORE_SCHEDULER_REG_SPARE0_SCHEDULER_REG_SPARE0_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_SCHEDULER_REG_SPARE0_SCHEDULER_REG_SPARE0_SHIFT 0
-#define BCHP_SWITCH_CORE_SCHEDULER_REG_SPARE0_SCHEDULER_REG_SPARE0_DEFAULT 0x00000000
-
-/***************************************************************************
- *SCHEDULER_REG_SPARE1 - Spare 1 Register (Not2Release)
- ***************************************************************************/
-/* SWITCH_CORE :: SCHEDULER_REG_SPARE1 :: SCHEDULER_REG_SPARE1 [31:00] */
-#define BCHP_SWITCH_CORE_SCHEDULER_REG_SPARE1_SCHEDULER_REG_SPARE1_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_SCHEDULER_REG_SPARE1_SCHEDULER_REG_SPARE1_SHIFT 0
-#define BCHP_SWITCH_CORE_SCHEDULER_REG_SPARE1_SCHEDULER_REG_SPARE1_DEFAULT 0x00000000
-
-/***************************************************************************
- *PN_PORT_SHAPER_BYTE_BASED_MAX_REFRESH_Port_0 - Port N, Byte-Based, Port Shaper Shaping Rate Configure Register
- ***************************************************************************/
-/* SWITCH_CORE :: PN_PORT_SHAPER_BYTE_BASED_MAX_REFRESH_Port_0 :: SWITCH_RESV [31:18] */
-#define BCHP_SWITCH_CORE_PN_PORT_SHAPER_BYTE_BASED_MAX_REFRESH_Port_0_SWITCH_RESV_MASK 0xfffc0000
-#define BCHP_SWITCH_CORE_PN_PORT_SHAPER_BYTE_BASED_MAX_REFRESH_Port_0_SWITCH_RESV_SHIFT 18
-#define BCHP_SWITCH_CORE_PN_PORT_SHAPER_BYTE_BASED_MAX_REFRESH_Port_0_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: PN_PORT_SHAPER_BYTE_BASED_MAX_REFRESH_Port_0 :: MAX_REFRESH [17:00] */
-#define BCHP_SWITCH_CORE_PN_PORT_SHAPER_BYTE_BASED_MAX_REFRESH_Port_0_MAX_REFRESH_MASK 0x0003ffff
-#define BCHP_SWITCH_CORE_PN_PORT_SHAPER_BYTE_BASED_MAX_REFRESH_Port_0_MAX_REFRESH_SHIFT 0
-#define BCHP_SWITCH_CORE_PN_PORT_SHAPER_BYTE_BASED_MAX_REFRESH_Port_0_MAX_REFRESH_DEFAULT 0x00000000
-
-/***************************************************************************
- *PN_PORT_SHAPER_BYTE_BASED_MAX_REFRESH_Port_1 - Port N, Byte-Based, Port Shaper Shaping Rate Configure Register
- ***************************************************************************/
-/* SWITCH_CORE :: PN_PORT_SHAPER_BYTE_BASED_MAX_REFRESH_Port_1 :: SWITCH_RESV [31:18] */
-#define BCHP_SWITCH_CORE_PN_PORT_SHAPER_BYTE_BASED_MAX_REFRESH_Port_1_SWITCH_RESV_MASK 0xfffc0000
-#define BCHP_SWITCH_CORE_PN_PORT_SHAPER_BYTE_BASED_MAX_REFRESH_Port_1_SWITCH_RESV_SHIFT 18
-#define BCHP_SWITCH_CORE_PN_PORT_SHAPER_BYTE_BASED_MAX_REFRESH_Port_1_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: PN_PORT_SHAPER_BYTE_BASED_MAX_REFRESH_Port_1 :: MAX_REFRESH [17:00] */
-#define BCHP_SWITCH_CORE_PN_PORT_SHAPER_BYTE_BASED_MAX_REFRESH_Port_1_MAX_REFRESH_MASK 0x0003ffff
-#define BCHP_SWITCH_CORE_PN_PORT_SHAPER_BYTE_BASED_MAX_REFRESH_Port_1_MAX_REFRESH_SHIFT 0
-#define BCHP_SWITCH_CORE_PN_PORT_SHAPER_BYTE_BASED_MAX_REFRESH_Port_1_MAX_REFRESH_DEFAULT 0x00000000
-
-/***************************************************************************
- *PN_PORT_SHAPER_BYTE_BASED_MAX_REFRESH_Port_2 - Port N, Byte-Based, Port Shaper Shaping Rate Configure Register
- ***************************************************************************/
-/* SWITCH_CORE :: PN_PORT_SHAPER_BYTE_BASED_MAX_REFRESH_Port_2 :: SWITCH_RESV [31:18] */
-#define BCHP_SWITCH_CORE_PN_PORT_SHAPER_BYTE_BASED_MAX_REFRESH_Port_2_SWITCH_RESV_MASK 0xfffc0000
-#define BCHP_SWITCH_CORE_PN_PORT_SHAPER_BYTE_BASED_MAX_REFRESH_Port_2_SWITCH_RESV_SHIFT 18
-#define BCHP_SWITCH_CORE_PN_PORT_SHAPER_BYTE_BASED_MAX_REFRESH_Port_2_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: PN_PORT_SHAPER_BYTE_BASED_MAX_REFRESH_Port_2 :: MAX_REFRESH [17:00] */
-#define BCHP_SWITCH_CORE_PN_PORT_SHAPER_BYTE_BASED_MAX_REFRESH_Port_2_MAX_REFRESH_MASK 0x0003ffff
-#define BCHP_SWITCH_CORE_PN_PORT_SHAPER_BYTE_BASED_MAX_REFRESH_Port_2_MAX_REFRESH_SHIFT 0
-#define BCHP_SWITCH_CORE_PN_PORT_SHAPER_BYTE_BASED_MAX_REFRESH_Port_2_MAX_REFRESH_DEFAULT 0x00000000
-
-/***************************************************************************
- *PN_PORT_SHAPER_BYTE_BASED_MAX_REFRESH_Port_3 - Port N, Byte-Based, Port Shaper Shaping Rate Configure Register
- ***************************************************************************/
-/* SWITCH_CORE :: PN_PORT_SHAPER_BYTE_BASED_MAX_REFRESH_Port_3 :: SWITCH_RESV [31:18] */
-#define BCHP_SWITCH_CORE_PN_PORT_SHAPER_BYTE_BASED_MAX_REFRESH_Port_3_SWITCH_RESV_MASK 0xfffc0000
-#define BCHP_SWITCH_CORE_PN_PORT_SHAPER_BYTE_BASED_MAX_REFRESH_Port_3_SWITCH_RESV_SHIFT 18
-#define BCHP_SWITCH_CORE_PN_PORT_SHAPER_BYTE_BASED_MAX_REFRESH_Port_3_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: PN_PORT_SHAPER_BYTE_BASED_MAX_REFRESH_Port_3 :: MAX_REFRESH [17:00] */
-#define BCHP_SWITCH_CORE_PN_PORT_SHAPER_BYTE_BASED_MAX_REFRESH_Port_3_MAX_REFRESH_MASK 0x0003ffff
-#define BCHP_SWITCH_CORE_PN_PORT_SHAPER_BYTE_BASED_MAX_REFRESH_Port_3_MAX_REFRESH_SHIFT 0
-#define BCHP_SWITCH_CORE_PN_PORT_SHAPER_BYTE_BASED_MAX_REFRESH_Port_3_MAX_REFRESH_DEFAULT 0x00000000
-
-/***************************************************************************
- *PN_PORT_SHAPER_BYTE_BASED_MAX_REFRESH_Port_4 - Port N, Byte-Based, Port Shaper Shaping Rate Configure Register
- ***************************************************************************/
-/* SWITCH_CORE :: PN_PORT_SHAPER_BYTE_BASED_MAX_REFRESH_Port_4 :: SWITCH_RESV [31:18] */
-#define BCHP_SWITCH_CORE_PN_PORT_SHAPER_BYTE_BASED_MAX_REFRESH_Port_4_SWITCH_RESV_MASK 0xfffc0000
-#define BCHP_SWITCH_CORE_PN_PORT_SHAPER_BYTE_BASED_MAX_REFRESH_Port_4_SWITCH_RESV_SHIFT 18
-#define BCHP_SWITCH_CORE_PN_PORT_SHAPER_BYTE_BASED_MAX_REFRESH_Port_4_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: PN_PORT_SHAPER_BYTE_BASED_MAX_REFRESH_Port_4 :: MAX_REFRESH [17:00] */
-#define BCHP_SWITCH_CORE_PN_PORT_SHAPER_BYTE_BASED_MAX_REFRESH_Port_4_MAX_REFRESH_MASK 0x0003ffff
-#define BCHP_SWITCH_CORE_PN_PORT_SHAPER_BYTE_BASED_MAX_REFRESH_Port_4_MAX_REFRESH_SHIFT 0
-#define BCHP_SWITCH_CORE_PN_PORT_SHAPER_BYTE_BASED_MAX_REFRESH_Port_4_MAX_REFRESH_DEFAULT 0x00000000
-
-/***************************************************************************
- *PN_PORT_SHAPER_BYTE_BASED_MAX_REFRESH_Port_5 - Port N, Byte-Based, Port Shaper Shaping Rate Configure Register
- ***************************************************************************/
-/* SWITCH_CORE :: PN_PORT_SHAPER_BYTE_BASED_MAX_REFRESH_Port_5 :: SWITCH_RESV [31:18] */
-#define BCHP_SWITCH_CORE_PN_PORT_SHAPER_BYTE_BASED_MAX_REFRESH_Port_5_SWITCH_RESV_MASK 0xfffc0000
-#define BCHP_SWITCH_CORE_PN_PORT_SHAPER_BYTE_BASED_MAX_REFRESH_Port_5_SWITCH_RESV_SHIFT 18
-#define BCHP_SWITCH_CORE_PN_PORT_SHAPER_BYTE_BASED_MAX_REFRESH_Port_5_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: PN_PORT_SHAPER_BYTE_BASED_MAX_REFRESH_Port_5 :: MAX_REFRESH [17:00] */
-#define BCHP_SWITCH_CORE_PN_PORT_SHAPER_BYTE_BASED_MAX_REFRESH_Port_5_MAX_REFRESH_MASK 0x0003ffff
-#define BCHP_SWITCH_CORE_PN_PORT_SHAPER_BYTE_BASED_MAX_REFRESH_Port_5_MAX_REFRESH_SHIFT 0
-#define BCHP_SWITCH_CORE_PN_PORT_SHAPER_BYTE_BASED_MAX_REFRESH_Port_5_MAX_REFRESH_DEFAULT 0x00000000
-
-/***************************************************************************
- *P7_PORT_SHAPER_BYTE_BASED_MAX_REFRESH - Port 7, Byte-Based, Port Shaper Shaping Rate Configure Register
- ***************************************************************************/
-/* SWITCH_CORE :: P7_PORT_SHAPER_BYTE_BASED_MAX_REFRESH :: SWITCH_RESV [31:18] */
-#define BCHP_SWITCH_CORE_P7_PORT_SHAPER_BYTE_BASED_MAX_REFRESH_SWITCH_RESV_MASK 0xfffc0000
-#define BCHP_SWITCH_CORE_P7_PORT_SHAPER_BYTE_BASED_MAX_REFRESH_SWITCH_RESV_SHIFT 18
-#define BCHP_SWITCH_CORE_P7_PORT_SHAPER_BYTE_BASED_MAX_REFRESH_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: P7_PORT_SHAPER_BYTE_BASED_MAX_REFRESH :: MAX_REFRESH [17:00] */
-#define BCHP_SWITCH_CORE_P7_PORT_SHAPER_BYTE_BASED_MAX_REFRESH_MAX_REFRESH_MASK 0x0003ffff
-#define BCHP_SWITCH_CORE_P7_PORT_SHAPER_BYTE_BASED_MAX_REFRESH_MAX_REFRESH_SHIFT 0
-#define BCHP_SWITCH_CORE_P7_PORT_SHAPER_BYTE_BASED_MAX_REFRESH_MAX_REFRESH_DEFAULT 0x00000000
-
-/***************************************************************************
- *IMP_PORT_SHAPER_BYTE_BASED_MAX_REFRESH - Port 8, Byte-Based, Port Shaper Shaping Rate Configure Register
- ***************************************************************************/
-/* SWITCH_CORE :: IMP_PORT_SHAPER_BYTE_BASED_MAX_REFRESH :: SWITCH_RESV [31:18] */
-#define BCHP_SWITCH_CORE_IMP_PORT_SHAPER_BYTE_BASED_MAX_REFRESH_SWITCH_RESV_MASK 0xfffc0000
-#define BCHP_SWITCH_CORE_IMP_PORT_SHAPER_BYTE_BASED_MAX_REFRESH_SWITCH_RESV_SHIFT 18
-#define BCHP_SWITCH_CORE_IMP_PORT_SHAPER_BYTE_BASED_MAX_REFRESH_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: IMP_PORT_SHAPER_BYTE_BASED_MAX_REFRESH :: MAX_REFRESH [17:00] */
-#define BCHP_SWITCH_CORE_IMP_PORT_SHAPER_BYTE_BASED_MAX_REFRESH_MAX_REFRESH_MASK 0x0003ffff
-#define BCHP_SWITCH_CORE_IMP_PORT_SHAPER_BYTE_BASED_MAX_REFRESH_MAX_REFRESH_SHIFT 0
-#define BCHP_SWITCH_CORE_IMP_PORT_SHAPER_BYTE_BASED_MAX_REFRESH_MAX_REFRESH_DEFAULT 0x00000000
-
-/***************************************************************************
- *PN_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_Port_0 - Port N, Byte-Based, Port Shaper Burst Size Configure Register
- ***************************************************************************/
-/* SWITCH_CORE :: PN_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_Port_0 :: SWITCH_RESV [31:18] */
-#define BCHP_SWITCH_CORE_PN_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_Port_0_SWITCH_RESV_MASK 0xfffc0000
-#define BCHP_SWITCH_CORE_PN_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_Port_0_SWITCH_RESV_SHIFT 18
-#define BCHP_SWITCH_CORE_PN_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_Port_0_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: PN_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_Port_0 :: MAX_THD_SEL [17:00] */
-#define BCHP_SWITCH_CORE_PN_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_Port_0_MAX_THD_SEL_MASK 0x0003ffff
-#define BCHP_SWITCH_CORE_PN_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_Port_0_MAX_THD_SEL_SHIFT 0
-#define BCHP_SWITCH_CORE_PN_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_Port_0_MAX_THD_SEL_DEFAULT 0x00000000
-
-/***************************************************************************
- *PN_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_Port_1 - Port N, Byte-Based, Port Shaper Burst Size Configure Register
- ***************************************************************************/
-/* SWITCH_CORE :: PN_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_Port_1 :: SWITCH_RESV [31:18] */
-#define BCHP_SWITCH_CORE_PN_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_Port_1_SWITCH_RESV_MASK 0xfffc0000
-#define BCHP_SWITCH_CORE_PN_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_Port_1_SWITCH_RESV_SHIFT 18
-#define BCHP_SWITCH_CORE_PN_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_Port_1_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: PN_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_Port_1 :: MAX_THD_SEL [17:00] */
-#define BCHP_SWITCH_CORE_PN_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_Port_1_MAX_THD_SEL_MASK 0x0003ffff
-#define BCHP_SWITCH_CORE_PN_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_Port_1_MAX_THD_SEL_SHIFT 0
-#define BCHP_SWITCH_CORE_PN_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_Port_1_MAX_THD_SEL_DEFAULT 0x00000000
-
-/***************************************************************************
- *PN_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_Port_2 - Port N, Byte-Based, Port Shaper Burst Size Configure Register
- ***************************************************************************/
-/* SWITCH_CORE :: PN_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_Port_2 :: SWITCH_RESV [31:18] */
-#define BCHP_SWITCH_CORE_PN_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_Port_2_SWITCH_RESV_MASK 0xfffc0000
-#define BCHP_SWITCH_CORE_PN_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_Port_2_SWITCH_RESV_SHIFT 18
-#define BCHP_SWITCH_CORE_PN_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_Port_2_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: PN_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_Port_2 :: MAX_THD_SEL [17:00] */
-#define BCHP_SWITCH_CORE_PN_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_Port_2_MAX_THD_SEL_MASK 0x0003ffff
-#define BCHP_SWITCH_CORE_PN_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_Port_2_MAX_THD_SEL_SHIFT 0
-#define BCHP_SWITCH_CORE_PN_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_Port_2_MAX_THD_SEL_DEFAULT 0x00000000
-
-/***************************************************************************
- *PN_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_Port_3 - Port N, Byte-Based, Port Shaper Burst Size Configure Register
- ***************************************************************************/
-/* SWITCH_CORE :: PN_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_Port_3 :: SWITCH_RESV [31:18] */
-#define BCHP_SWITCH_CORE_PN_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_Port_3_SWITCH_RESV_MASK 0xfffc0000
-#define BCHP_SWITCH_CORE_PN_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_Port_3_SWITCH_RESV_SHIFT 18
-#define BCHP_SWITCH_CORE_PN_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_Port_3_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: PN_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_Port_3 :: MAX_THD_SEL [17:00] */
-#define BCHP_SWITCH_CORE_PN_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_Port_3_MAX_THD_SEL_MASK 0x0003ffff
-#define BCHP_SWITCH_CORE_PN_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_Port_3_MAX_THD_SEL_SHIFT 0
-#define BCHP_SWITCH_CORE_PN_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_Port_3_MAX_THD_SEL_DEFAULT 0x00000000
-
-/***************************************************************************
- *PN_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_Port_4 - Port N, Byte-Based, Port Shaper Burst Size Configure Register
- ***************************************************************************/
-/* SWITCH_CORE :: PN_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_Port_4 :: SWITCH_RESV [31:18] */
-#define BCHP_SWITCH_CORE_PN_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_Port_4_SWITCH_RESV_MASK 0xfffc0000
-#define BCHP_SWITCH_CORE_PN_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_Port_4_SWITCH_RESV_SHIFT 18
-#define BCHP_SWITCH_CORE_PN_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_Port_4_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: PN_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_Port_4 :: MAX_THD_SEL [17:00] */
-#define BCHP_SWITCH_CORE_PN_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_Port_4_MAX_THD_SEL_MASK 0x0003ffff
-#define BCHP_SWITCH_CORE_PN_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_Port_4_MAX_THD_SEL_SHIFT 0
-#define BCHP_SWITCH_CORE_PN_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_Port_4_MAX_THD_SEL_DEFAULT 0x00000000
-
-/***************************************************************************
- *PN_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_Port_5 - Port N, Byte-Based, Port Shaper Burst Size Configure Register
- ***************************************************************************/
-/* SWITCH_CORE :: PN_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_Port_5 :: SWITCH_RESV [31:18] */
-#define BCHP_SWITCH_CORE_PN_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_Port_5_SWITCH_RESV_MASK 0xfffc0000
-#define BCHP_SWITCH_CORE_PN_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_Port_5_SWITCH_RESV_SHIFT 18
-#define BCHP_SWITCH_CORE_PN_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_Port_5_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: PN_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_Port_5 :: MAX_THD_SEL [17:00] */
-#define BCHP_SWITCH_CORE_PN_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_Port_5_MAX_THD_SEL_MASK 0x0003ffff
-#define BCHP_SWITCH_CORE_PN_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_Port_5_MAX_THD_SEL_SHIFT 0
-#define BCHP_SWITCH_CORE_PN_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_Port_5_MAX_THD_SEL_DEFAULT 0x00000000
-
-/***************************************************************************
- *P7_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL - Port 7, Byte-Based, Port Shaper Burst Size Configure Register
- ***************************************************************************/
-/* SWITCH_CORE :: P7_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL :: SWITCH_RESV [31:18] */
-#define BCHP_SWITCH_CORE_P7_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_SWITCH_RESV_MASK 0xfffc0000
-#define BCHP_SWITCH_CORE_P7_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_SWITCH_RESV_SHIFT 18
-#define BCHP_SWITCH_CORE_P7_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: P7_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL :: MAX_THD_SEL [17:00] */
-#define BCHP_SWITCH_CORE_P7_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_MAX_THD_SEL_MASK 0x0003ffff
-#define BCHP_SWITCH_CORE_P7_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_MAX_THD_SEL_SHIFT 0
-#define BCHP_SWITCH_CORE_P7_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_MAX_THD_SEL_DEFAULT 0x00000000
-
-/***************************************************************************
- *IMP_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL - Port 8, Byte-Based, Port Shaper Burst Size Configure Register
- ***************************************************************************/
-/* SWITCH_CORE :: IMP_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL :: SWITCH_RESV [31:18] */
-#define BCHP_SWITCH_CORE_IMP_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_SWITCH_RESV_MASK 0xfffc0000
-#define BCHP_SWITCH_CORE_IMP_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_SWITCH_RESV_SHIFT 18
-#define BCHP_SWITCH_CORE_IMP_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: IMP_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL :: MAX_THD_SEL [17:00] */
-#define BCHP_SWITCH_CORE_IMP_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_MAX_THD_SEL_MASK 0x0003ffff
-#define BCHP_SWITCH_CORE_IMP_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_MAX_THD_SEL_SHIFT 0
-#define BCHP_SWITCH_CORE_IMP_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_MAX_THD_SEL_DEFAULT 0x00000000
-
-/***************************************************************************
- *PN_PORT_SHAPER_STS_Port_0 - Port N, PORT Shaper Status Register
- ***************************************************************************/
-/* SWITCH_CORE :: PN_PORT_SHAPER_STS_Port_0 :: IN_PROFILE_FLAG [31:31] */
-#define BCHP_SWITCH_CORE_PN_PORT_SHAPER_STS_Port_0_IN_PROFILE_FLAG_MASK 0x80000000
-#define BCHP_SWITCH_CORE_PN_PORT_SHAPER_STS_Port_0_IN_PROFILE_FLAG_SHIFT 31
-#define BCHP_SWITCH_CORE_PN_PORT_SHAPER_STS_Port_0_IN_PROFILE_FLAG_DEFAULT 0x00000001
-
-/* SWITCH_CORE :: PN_PORT_SHAPER_STS_Port_0 :: SWITCH_RESV [30:29] */
-#define BCHP_SWITCH_CORE_PN_PORT_SHAPER_STS_Port_0_SWITCH_RESV_MASK 0x60000000
-#define BCHP_SWITCH_CORE_PN_PORT_SHAPER_STS_Port_0_SWITCH_RESV_SHIFT 29
-#define BCHP_SWITCH_CORE_PN_PORT_SHAPER_STS_Port_0_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: PN_PORT_SHAPER_STS_Port_0 :: BUCKET_CNT [28:00] */
-#define BCHP_SWITCH_CORE_PN_PORT_SHAPER_STS_Port_0_BUCKET_CNT_MASK 0x1fffffff
-#define BCHP_SWITCH_CORE_PN_PORT_SHAPER_STS_Port_0_BUCKET_CNT_SHIFT 0
-#define BCHP_SWITCH_CORE_PN_PORT_SHAPER_STS_Port_0_BUCKET_CNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *PN_PORT_SHAPER_STS_Port_1 - Port N, PORT Shaper Status Register
- ***************************************************************************/
-/* SWITCH_CORE :: PN_PORT_SHAPER_STS_Port_1 :: IN_PROFILE_FLAG [31:31] */
-#define BCHP_SWITCH_CORE_PN_PORT_SHAPER_STS_Port_1_IN_PROFILE_FLAG_MASK 0x80000000
-#define BCHP_SWITCH_CORE_PN_PORT_SHAPER_STS_Port_1_IN_PROFILE_FLAG_SHIFT 31
-#define BCHP_SWITCH_CORE_PN_PORT_SHAPER_STS_Port_1_IN_PROFILE_FLAG_DEFAULT 0x00000001
-
-/* SWITCH_CORE :: PN_PORT_SHAPER_STS_Port_1 :: SWITCH_RESV [30:29] */
-#define BCHP_SWITCH_CORE_PN_PORT_SHAPER_STS_Port_1_SWITCH_RESV_MASK 0x60000000
-#define BCHP_SWITCH_CORE_PN_PORT_SHAPER_STS_Port_1_SWITCH_RESV_SHIFT 29
-#define BCHP_SWITCH_CORE_PN_PORT_SHAPER_STS_Port_1_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: PN_PORT_SHAPER_STS_Port_1 :: BUCKET_CNT [28:00] */
-#define BCHP_SWITCH_CORE_PN_PORT_SHAPER_STS_Port_1_BUCKET_CNT_MASK 0x1fffffff
-#define BCHP_SWITCH_CORE_PN_PORT_SHAPER_STS_Port_1_BUCKET_CNT_SHIFT 0
-#define BCHP_SWITCH_CORE_PN_PORT_SHAPER_STS_Port_1_BUCKET_CNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *PN_PORT_SHAPER_STS_Port_2 - Port N, PORT Shaper Status Register
- ***************************************************************************/
-/* SWITCH_CORE :: PN_PORT_SHAPER_STS_Port_2 :: IN_PROFILE_FLAG [31:31] */
-#define BCHP_SWITCH_CORE_PN_PORT_SHAPER_STS_Port_2_IN_PROFILE_FLAG_MASK 0x80000000
-#define BCHP_SWITCH_CORE_PN_PORT_SHAPER_STS_Port_2_IN_PROFILE_FLAG_SHIFT 31
-#define BCHP_SWITCH_CORE_PN_PORT_SHAPER_STS_Port_2_IN_PROFILE_FLAG_DEFAULT 0x00000001
-
-/* SWITCH_CORE :: PN_PORT_SHAPER_STS_Port_2 :: SWITCH_RESV [30:29] */
-#define BCHP_SWITCH_CORE_PN_PORT_SHAPER_STS_Port_2_SWITCH_RESV_MASK 0x60000000
-#define BCHP_SWITCH_CORE_PN_PORT_SHAPER_STS_Port_2_SWITCH_RESV_SHIFT 29
-#define BCHP_SWITCH_CORE_PN_PORT_SHAPER_STS_Port_2_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: PN_PORT_SHAPER_STS_Port_2 :: BUCKET_CNT [28:00] */
-#define BCHP_SWITCH_CORE_PN_PORT_SHAPER_STS_Port_2_BUCKET_CNT_MASK 0x1fffffff
-#define BCHP_SWITCH_CORE_PN_PORT_SHAPER_STS_Port_2_BUCKET_CNT_SHIFT 0
-#define BCHP_SWITCH_CORE_PN_PORT_SHAPER_STS_Port_2_BUCKET_CNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *PN_PORT_SHAPER_STS_Port_3 - Port N, PORT Shaper Status Register
- ***************************************************************************/
-/* SWITCH_CORE :: PN_PORT_SHAPER_STS_Port_3 :: IN_PROFILE_FLAG [31:31] */
-#define BCHP_SWITCH_CORE_PN_PORT_SHAPER_STS_Port_3_IN_PROFILE_FLAG_MASK 0x80000000
-#define BCHP_SWITCH_CORE_PN_PORT_SHAPER_STS_Port_3_IN_PROFILE_FLAG_SHIFT 31
-#define BCHP_SWITCH_CORE_PN_PORT_SHAPER_STS_Port_3_IN_PROFILE_FLAG_DEFAULT 0x00000001
-
-/* SWITCH_CORE :: PN_PORT_SHAPER_STS_Port_3 :: SWITCH_RESV [30:29] */
-#define BCHP_SWITCH_CORE_PN_PORT_SHAPER_STS_Port_3_SWITCH_RESV_MASK 0x60000000
-#define BCHP_SWITCH_CORE_PN_PORT_SHAPER_STS_Port_3_SWITCH_RESV_SHIFT 29
-#define BCHP_SWITCH_CORE_PN_PORT_SHAPER_STS_Port_3_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: PN_PORT_SHAPER_STS_Port_3 :: BUCKET_CNT [28:00] */
-#define BCHP_SWITCH_CORE_PN_PORT_SHAPER_STS_Port_3_BUCKET_CNT_MASK 0x1fffffff
-#define BCHP_SWITCH_CORE_PN_PORT_SHAPER_STS_Port_3_BUCKET_CNT_SHIFT 0
-#define BCHP_SWITCH_CORE_PN_PORT_SHAPER_STS_Port_3_BUCKET_CNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *PN_PORT_SHAPER_STS_Port_4 - Port N, PORT Shaper Status Register
- ***************************************************************************/
-/* SWITCH_CORE :: PN_PORT_SHAPER_STS_Port_4 :: IN_PROFILE_FLAG [31:31] */
-#define BCHP_SWITCH_CORE_PN_PORT_SHAPER_STS_Port_4_IN_PROFILE_FLAG_MASK 0x80000000
-#define BCHP_SWITCH_CORE_PN_PORT_SHAPER_STS_Port_4_IN_PROFILE_FLAG_SHIFT 31
-#define BCHP_SWITCH_CORE_PN_PORT_SHAPER_STS_Port_4_IN_PROFILE_FLAG_DEFAULT 0x00000001
-
-/* SWITCH_CORE :: PN_PORT_SHAPER_STS_Port_4 :: SWITCH_RESV [30:29] */
-#define BCHP_SWITCH_CORE_PN_PORT_SHAPER_STS_Port_4_SWITCH_RESV_MASK 0x60000000
-#define BCHP_SWITCH_CORE_PN_PORT_SHAPER_STS_Port_4_SWITCH_RESV_SHIFT 29
-#define BCHP_SWITCH_CORE_PN_PORT_SHAPER_STS_Port_4_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: PN_PORT_SHAPER_STS_Port_4 :: BUCKET_CNT [28:00] */
-#define BCHP_SWITCH_CORE_PN_PORT_SHAPER_STS_Port_4_BUCKET_CNT_MASK 0x1fffffff
-#define BCHP_SWITCH_CORE_PN_PORT_SHAPER_STS_Port_4_BUCKET_CNT_SHIFT 0
-#define BCHP_SWITCH_CORE_PN_PORT_SHAPER_STS_Port_4_BUCKET_CNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *PN_PORT_SHAPER_STS_Port_5 - Port N, PORT Shaper Status Register
- ***************************************************************************/
-/* SWITCH_CORE :: PN_PORT_SHAPER_STS_Port_5 :: IN_PROFILE_FLAG [31:31] */
-#define BCHP_SWITCH_CORE_PN_PORT_SHAPER_STS_Port_5_IN_PROFILE_FLAG_MASK 0x80000000
-#define BCHP_SWITCH_CORE_PN_PORT_SHAPER_STS_Port_5_IN_PROFILE_FLAG_SHIFT 31
-#define BCHP_SWITCH_CORE_PN_PORT_SHAPER_STS_Port_5_IN_PROFILE_FLAG_DEFAULT 0x00000001
-
-/* SWITCH_CORE :: PN_PORT_SHAPER_STS_Port_5 :: SWITCH_RESV [30:29] */
-#define BCHP_SWITCH_CORE_PN_PORT_SHAPER_STS_Port_5_SWITCH_RESV_MASK 0x60000000
-#define BCHP_SWITCH_CORE_PN_PORT_SHAPER_STS_Port_5_SWITCH_RESV_SHIFT 29
-#define BCHP_SWITCH_CORE_PN_PORT_SHAPER_STS_Port_5_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: PN_PORT_SHAPER_STS_Port_5 :: BUCKET_CNT [28:00] */
-#define BCHP_SWITCH_CORE_PN_PORT_SHAPER_STS_Port_5_BUCKET_CNT_MASK 0x1fffffff
-#define BCHP_SWITCH_CORE_PN_PORT_SHAPER_STS_Port_5_BUCKET_CNT_SHIFT 0
-#define BCHP_SWITCH_CORE_PN_PORT_SHAPER_STS_Port_5_BUCKET_CNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *P7_PORT_SHAPER_STS - Port 7, PORT Shaper Status Register
- ***************************************************************************/
-/* SWITCH_CORE :: P7_PORT_SHAPER_STS :: IN_PROFILE_FLAG [31:31] */
-#define BCHP_SWITCH_CORE_P7_PORT_SHAPER_STS_IN_PROFILE_FLAG_MASK 0x80000000
-#define BCHP_SWITCH_CORE_P7_PORT_SHAPER_STS_IN_PROFILE_FLAG_SHIFT 31
-#define BCHP_SWITCH_CORE_P7_PORT_SHAPER_STS_IN_PROFILE_FLAG_DEFAULT 0x00000001
-
-/* SWITCH_CORE :: P7_PORT_SHAPER_STS :: SWITCH_RESV [30:29] */
-#define BCHP_SWITCH_CORE_P7_PORT_SHAPER_STS_SWITCH_RESV_MASK 0x60000000
-#define BCHP_SWITCH_CORE_P7_PORT_SHAPER_STS_SWITCH_RESV_SHIFT 29
-#define BCHP_SWITCH_CORE_P7_PORT_SHAPER_STS_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: P7_PORT_SHAPER_STS :: BUCKET_CNT [28:00] */
-#define BCHP_SWITCH_CORE_P7_PORT_SHAPER_STS_BUCKET_CNT_MASK 0x1fffffff
-#define BCHP_SWITCH_CORE_P7_PORT_SHAPER_STS_BUCKET_CNT_SHIFT 0
-#define BCHP_SWITCH_CORE_P7_PORT_SHAPER_STS_BUCKET_CNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *IMP_PORT_SHAPER_STS - Port 8, PORT Shaper Status Register
- ***************************************************************************/
-/* SWITCH_CORE :: IMP_PORT_SHAPER_STS :: IN_PROFILE_FLAG [31:31] */
-#define BCHP_SWITCH_CORE_IMP_PORT_SHAPER_STS_IN_PROFILE_FLAG_MASK 0x80000000
-#define BCHP_SWITCH_CORE_IMP_PORT_SHAPER_STS_IN_PROFILE_FLAG_SHIFT 31
-#define BCHP_SWITCH_CORE_IMP_PORT_SHAPER_STS_IN_PROFILE_FLAG_DEFAULT 0x00000001
-
-/* SWITCH_CORE :: IMP_PORT_SHAPER_STS :: SWITCH_RESV [30:29] */
-#define BCHP_SWITCH_CORE_IMP_PORT_SHAPER_STS_SWITCH_RESV_MASK 0x60000000
-#define BCHP_SWITCH_CORE_IMP_PORT_SHAPER_STS_SWITCH_RESV_SHIFT 29
-#define BCHP_SWITCH_CORE_IMP_PORT_SHAPER_STS_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: IMP_PORT_SHAPER_STS :: BUCKET_CNT [28:00] */
-#define BCHP_SWITCH_CORE_IMP_PORT_SHAPER_STS_BUCKET_CNT_MASK 0x1fffffff
-#define BCHP_SWITCH_CORE_IMP_PORT_SHAPER_STS_BUCKET_CNT_SHIFT 0
-#define BCHP_SWITCH_CORE_IMP_PORT_SHAPER_STS_BUCKET_CNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *PN_PORT_SHAPER_PACKET_BASED_MAX_REFRESH_Port_0 - Port N, Packet-Based, Port Shaper Shaping Rate Configure Register
- ***************************************************************************/
-/* SWITCH_CORE :: PN_PORT_SHAPER_PACKET_BASED_MAX_REFRESH_Port_0 :: SWITCH_RESV [31:18] */
-#define BCHP_SWITCH_CORE_PN_PORT_SHAPER_PACKET_BASED_MAX_REFRESH_Port_0_SWITCH_RESV_MASK 0xfffc0000
-#define BCHP_SWITCH_CORE_PN_PORT_SHAPER_PACKET_BASED_MAX_REFRESH_Port_0_SWITCH_RESV_SHIFT 18
-#define BCHP_SWITCH_CORE_PN_PORT_SHAPER_PACKET_BASED_MAX_REFRESH_Port_0_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: PN_PORT_SHAPER_PACKET_BASED_MAX_REFRESH_Port_0 :: MAX_REFRESH [17:00] */
-#define BCHP_SWITCH_CORE_PN_PORT_SHAPER_PACKET_BASED_MAX_REFRESH_Port_0_MAX_REFRESH_MASK 0x0003ffff
-#define BCHP_SWITCH_CORE_PN_PORT_SHAPER_PACKET_BASED_MAX_REFRESH_Port_0_MAX_REFRESH_SHIFT 0
-#define BCHP_SWITCH_CORE_PN_PORT_SHAPER_PACKET_BASED_MAX_REFRESH_Port_0_MAX_REFRESH_DEFAULT 0x00000000
-
-/***************************************************************************
- *PN_PORT_SHAPER_PACKET_BASED_MAX_REFRESH_Port_1 - Port N, Packet-Based, Port Shaper Shaping Rate Configure Register
- ***************************************************************************/
-/* SWITCH_CORE :: PN_PORT_SHAPER_PACKET_BASED_MAX_REFRESH_Port_1 :: SWITCH_RESV [31:18] */
-#define BCHP_SWITCH_CORE_PN_PORT_SHAPER_PACKET_BASED_MAX_REFRESH_Port_1_SWITCH_RESV_MASK 0xfffc0000
-#define BCHP_SWITCH_CORE_PN_PORT_SHAPER_PACKET_BASED_MAX_REFRESH_Port_1_SWITCH_RESV_SHIFT 18
-#define BCHP_SWITCH_CORE_PN_PORT_SHAPER_PACKET_BASED_MAX_REFRESH_Port_1_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: PN_PORT_SHAPER_PACKET_BASED_MAX_REFRESH_Port_1 :: MAX_REFRESH [17:00] */
-#define BCHP_SWITCH_CORE_PN_PORT_SHAPER_PACKET_BASED_MAX_REFRESH_Port_1_MAX_REFRESH_MASK 0x0003ffff
-#define BCHP_SWITCH_CORE_PN_PORT_SHAPER_PACKET_BASED_MAX_REFRESH_Port_1_MAX_REFRESH_SHIFT 0
-#define BCHP_SWITCH_CORE_PN_PORT_SHAPER_PACKET_BASED_MAX_REFRESH_Port_1_MAX_REFRESH_DEFAULT 0x00000000
-
-/***************************************************************************
- *PN_PORT_SHAPER_PACKET_BASED_MAX_REFRESH_Port_2 - Port N, Packet-Based, Port Shaper Shaping Rate Configure Register
- ***************************************************************************/
-/* SWITCH_CORE :: PN_PORT_SHAPER_PACKET_BASED_MAX_REFRESH_Port_2 :: SWITCH_RESV [31:18] */
-#define BCHP_SWITCH_CORE_PN_PORT_SHAPER_PACKET_BASED_MAX_REFRESH_Port_2_SWITCH_RESV_MASK 0xfffc0000
-#define BCHP_SWITCH_CORE_PN_PORT_SHAPER_PACKET_BASED_MAX_REFRESH_Port_2_SWITCH_RESV_SHIFT 18
-#define BCHP_SWITCH_CORE_PN_PORT_SHAPER_PACKET_BASED_MAX_REFRESH_Port_2_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: PN_PORT_SHAPER_PACKET_BASED_MAX_REFRESH_Port_2 :: MAX_REFRESH [17:00] */
-#define BCHP_SWITCH_CORE_PN_PORT_SHAPER_PACKET_BASED_MAX_REFRESH_Port_2_MAX_REFRESH_MASK 0x0003ffff
-#define BCHP_SWITCH_CORE_PN_PORT_SHAPER_PACKET_BASED_MAX_REFRESH_Port_2_MAX_REFRESH_SHIFT 0
-#define BCHP_SWITCH_CORE_PN_PORT_SHAPER_PACKET_BASED_MAX_REFRESH_Port_2_MAX_REFRESH_DEFAULT 0x00000000
-
-/***************************************************************************
- *PN_PORT_SHAPER_PACKET_BASED_MAX_REFRESH_Port_3 - Port N, Packet-Based, Port Shaper Shaping Rate Configure Register
- ***************************************************************************/
-/* SWITCH_CORE :: PN_PORT_SHAPER_PACKET_BASED_MAX_REFRESH_Port_3 :: SWITCH_RESV [31:18] */
-#define BCHP_SWITCH_CORE_PN_PORT_SHAPER_PACKET_BASED_MAX_REFRESH_Port_3_SWITCH_RESV_MASK 0xfffc0000
-#define BCHP_SWITCH_CORE_PN_PORT_SHAPER_PACKET_BASED_MAX_REFRESH_Port_3_SWITCH_RESV_SHIFT 18
-#define BCHP_SWITCH_CORE_PN_PORT_SHAPER_PACKET_BASED_MAX_REFRESH_Port_3_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: PN_PORT_SHAPER_PACKET_BASED_MAX_REFRESH_Port_3 :: MAX_REFRESH [17:00] */
-#define BCHP_SWITCH_CORE_PN_PORT_SHAPER_PACKET_BASED_MAX_REFRESH_Port_3_MAX_REFRESH_MASK 0x0003ffff
-#define BCHP_SWITCH_CORE_PN_PORT_SHAPER_PACKET_BASED_MAX_REFRESH_Port_3_MAX_REFRESH_SHIFT 0
-#define BCHP_SWITCH_CORE_PN_PORT_SHAPER_PACKET_BASED_MAX_REFRESH_Port_3_MAX_REFRESH_DEFAULT 0x00000000
-
-/***************************************************************************
- *PN_PORT_SHAPER_PACKET_BASED_MAX_REFRESH_Port_4 - Port N, Packet-Based, Port Shaper Shaping Rate Configure Register
- ***************************************************************************/
-/* SWITCH_CORE :: PN_PORT_SHAPER_PACKET_BASED_MAX_REFRESH_Port_4 :: SWITCH_RESV [31:18] */
-#define BCHP_SWITCH_CORE_PN_PORT_SHAPER_PACKET_BASED_MAX_REFRESH_Port_4_SWITCH_RESV_MASK 0xfffc0000
-#define BCHP_SWITCH_CORE_PN_PORT_SHAPER_PACKET_BASED_MAX_REFRESH_Port_4_SWITCH_RESV_SHIFT 18
-#define BCHP_SWITCH_CORE_PN_PORT_SHAPER_PACKET_BASED_MAX_REFRESH_Port_4_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: PN_PORT_SHAPER_PACKET_BASED_MAX_REFRESH_Port_4 :: MAX_REFRESH [17:00] */
-#define BCHP_SWITCH_CORE_PN_PORT_SHAPER_PACKET_BASED_MAX_REFRESH_Port_4_MAX_REFRESH_MASK 0x0003ffff
-#define BCHP_SWITCH_CORE_PN_PORT_SHAPER_PACKET_BASED_MAX_REFRESH_Port_4_MAX_REFRESH_SHIFT 0
-#define BCHP_SWITCH_CORE_PN_PORT_SHAPER_PACKET_BASED_MAX_REFRESH_Port_4_MAX_REFRESH_DEFAULT 0x00000000
-
-/***************************************************************************
- *PN_PORT_SHAPER_PACKET_BASED_MAX_REFRESH_Port_5 - Port N, Packet-Based, Port Shaper Shaping Rate Configure Register
- ***************************************************************************/
-/* SWITCH_CORE :: PN_PORT_SHAPER_PACKET_BASED_MAX_REFRESH_Port_5 :: SWITCH_RESV [31:18] */
-#define BCHP_SWITCH_CORE_PN_PORT_SHAPER_PACKET_BASED_MAX_REFRESH_Port_5_SWITCH_RESV_MASK 0xfffc0000
-#define BCHP_SWITCH_CORE_PN_PORT_SHAPER_PACKET_BASED_MAX_REFRESH_Port_5_SWITCH_RESV_SHIFT 18
-#define BCHP_SWITCH_CORE_PN_PORT_SHAPER_PACKET_BASED_MAX_REFRESH_Port_5_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: PN_PORT_SHAPER_PACKET_BASED_MAX_REFRESH_Port_5 :: MAX_REFRESH [17:00] */
-#define BCHP_SWITCH_CORE_PN_PORT_SHAPER_PACKET_BASED_MAX_REFRESH_Port_5_MAX_REFRESH_MASK 0x0003ffff
-#define BCHP_SWITCH_CORE_PN_PORT_SHAPER_PACKET_BASED_MAX_REFRESH_Port_5_MAX_REFRESH_SHIFT 0
-#define BCHP_SWITCH_CORE_PN_PORT_SHAPER_PACKET_BASED_MAX_REFRESH_Port_5_MAX_REFRESH_DEFAULT 0x00000000
-
-/***************************************************************************
- *P7_PORT_SHAPER_PACKET_BASED_MAX_REFRESH - Port 7, Packet-Based, Port Shaper Shaping Rate Configure Register
- ***************************************************************************/
-/* SWITCH_CORE :: P7_PORT_SHAPER_PACKET_BASED_MAX_REFRESH :: SWITCH_RESV [31:18] */
-#define BCHP_SWITCH_CORE_P7_PORT_SHAPER_PACKET_BASED_MAX_REFRESH_SWITCH_RESV_MASK 0xfffc0000
-#define BCHP_SWITCH_CORE_P7_PORT_SHAPER_PACKET_BASED_MAX_REFRESH_SWITCH_RESV_SHIFT 18
-#define BCHP_SWITCH_CORE_P7_PORT_SHAPER_PACKET_BASED_MAX_REFRESH_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: P7_PORT_SHAPER_PACKET_BASED_MAX_REFRESH :: MAX_REFRESH [17:00] */
-#define BCHP_SWITCH_CORE_P7_PORT_SHAPER_PACKET_BASED_MAX_REFRESH_MAX_REFRESH_MASK 0x0003ffff
-#define BCHP_SWITCH_CORE_P7_PORT_SHAPER_PACKET_BASED_MAX_REFRESH_MAX_REFRESH_SHIFT 0
-#define BCHP_SWITCH_CORE_P7_PORT_SHAPER_PACKET_BASED_MAX_REFRESH_MAX_REFRESH_DEFAULT 0x00000000
-
-/***************************************************************************
- *IMP_PORT_SHAPER_PACKET_BASED_MAX_REFRESH - Port 8, Packet-Based, Port Shaper Shaping Rate Configure Register
- ***************************************************************************/
-/* SWITCH_CORE :: IMP_PORT_SHAPER_PACKET_BASED_MAX_REFRESH :: SWITCH_RESV [31:18] */
-#define BCHP_SWITCH_CORE_IMP_PORT_SHAPER_PACKET_BASED_MAX_REFRESH_SWITCH_RESV_MASK 0xfffc0000
-#define BCHP_SWITCH_CORE_IMP_PORT_SHAPER_PACKET_BASED_MAX_REFRESH_SWITCH_RESV_SHIFT 18
-#define BCHP_SWITCH_CORE_IMP_PORT_SHAPER_PACKET_BASED_MAX_REFRESH_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: IMP_PORT_SHAPER_PACKET_BASED_MAX_REFRESH :: MAX_REFRESH [17:00] */
-#define BCHP_SWITCH_CORE_IMP_PORT_SHAPER_PACKET_BASED_MAX_REFRESH_MAX_REFRESH_MASK 0x0003ffff
-#define BCHP_SWITCH_CORE_IMP_PORT_SHAPER_PACKET_BASED_MAX_REFRESH_MAX_REFRESH_SHIFT 0
-#define BCHP_SWITCH_CORE_IMP_PORT_SHAPER_PACKET_BASED_MAX_REFRESH_MAX_REFRESH_DEFAULT 0x00000000
-
-/***************************************************************************
- *EGRESS_SHAPER_CTLREG_REG_SPARE0 - Spare 0 Register (Not2Release)
- ***************************************************************************/
-/* SWITCH_CORE :: EGRESS_SHAPER_CTLREG_REG_SPARE0 :: EGRESS_SHAPER_CTLREG_REG_SPARE0 [31:00] */
-#define BCHP_SWITCH_CORE_EGRESS_SHAPER_CTLREG_REG_SPARE0_EGRESS_SHAPER_CTLREG_REG_SPARE0_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_EGRESS_SHAPER_CTLREG_REG_SPARE0_EGRESS_SHAPER_CTLREG_REG_SPARE0_SHIFT 0
-#define BCHP_SWITCH_CORE_EGRESS_SHAPER_CTLREG_REG_SPARE0_EGRESS_SHAPER_CTLREG_REG_SPARE0_DEFAULT 0x00000000
-
-/***************************************************************************
- *EGRESS_SHAPER_CTLREG_REG_SPARE1 - Spare 1 Register (Not2Release)
- ***************************************************************************/
-/* SWITCH_CORE :: EGRESS_SHAPER_CTLREG_REG_SPARE1 :: EGRESS_SHAPER_CTLREG_REG_SPARE1 [31:00] */
-#define BCHP_SWITCH_CORE_EGRESS_SHAPER_CTLREG_REG_SPARE1_EGRESS_SHAPER_CTLREG_REG_SPARE1_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_EGRESS_SHAPER_CTLREG_REG_SPARE1_EGRESS_SHAPER_CTLREG_REG_SPARE1_SHIFT 0
-#define BCHP_SWITCH_CORE_EGRESS_SHAPER_CTLREG_REG_SPARE1_EGRESS_SHAPER_CTLREG_REG_SPARE1_DEFAULT 0x00000000
-
-/***************************************************************************
- *PN_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_Port_0 - Port N, Packet-Based, Port Shaper Burst Size Configure Register
- ***************************************************************************/
-/* SWITCH_CORE :: PN_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_Port_0 :: SWITCH_RESV [31:18] */
-#define BCHP_SWITCH_CORE_PN_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_Port_0_SWITCH_RESV_MASK 0xfffc0000
-#define BCHP_SWITCH_CORE_PN_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_Port_0_SWITCH_RESV_SHIFT 18
-#define BCHP_SWITCH_CORE_PN_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_Port_0_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: PN_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_Port_0 :: MAX_THD_SEL [17:00] */
-#define BCHP_SWITCH_CORE_PN_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_Port_0_MAX_THD_SEL_MASK 0x0003ffff
-#define BCHP_SWITCH_CORE_PN_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_Port_0_MAX_THD_SEL_SHIFT 0
-#define BCHP_SWITCH_CORE_PN_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_Port_0_MAX_THD_SEL_DEFAULT 0x00000000
-
-/***************************************************************************
- *PN_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_Port_1 - Port N, Packet-Based, Port Shaper Burst Size Configure Register
- ***************************************************************************/
-/* SWITCH_CORE :: PN_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_Port_1 :: SWITCH_RESV [31:18] */
-#define BCHP_SWITCH_CORE_PN_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_Port_1_SWITCH_RESV_MASK 0xfffc0000
-#define BCHP_SWITCH_CORE_PN_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_Port_1_SWITCH_RESV_SHIFT 18
-#define BCHP_SWITCH_CORE_PN_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_Port_1_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: PN_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_Port_1 :: MAX_THD_SEL [17:00] */
-#define BCHP_SWITCH_CORE_PN_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_Port_1_MAX_THD_SEL_MASK 0x0003ffff
-#define BCHP_SWITCH_CORE_PN_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_Port_1_MAX_THD_SEL_SHIFT 0
-#define BCHP_SWITCH_CORE_PN_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_Port_1_MAX_THD_SEL_DEFAULT 0x00000000
-
-/***************************************************************************
- *PN_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_Port_2 - Port N, Packet-Based, Port Shaper Burst Size Configure Register
- ***************************************************************************/
-/* SWITCH_CORE :: PN_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_Port_2 :: SWITCH_RESV [31:18] */
-#define BCHP_SWITCH_CORE_PN_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_Port_2_SWITCH_RESV_MASK 0xfffc0000
-#define BCHP_SWITCH_CORE_PN_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_Port_2_SWITCH_RESV_SHIFT 18
-#define BCHP_SWITCH_CORE_PN_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_Port_2_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: PN_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_Port_2 :: MAX_THD_SEL [17:00] */
-#define BCHP_SWITCH_CORE_PN_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_Port_2_MAX_THD_SEL_MASK 0x0003ffff
-#define BCHP_SWITCH_CORE_PN_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_Port_2_MAX_THD_SEL_SHIFT 0
-#define BCHP_SWITCH_CORE_PN_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_Port_2_MAX_THD_SEL_DEFAULT 0x00000000
-
-/***************************************************************************
- *PN_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_Port_3 - Port N, Packet-Based, Port Shaper Burst Size Configure Register
- ***************************************************************************/
-/* SWITCH_CORE :: PN_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_Port_3 :: SWITCH_RESV [31:18] */
-#define BCHP_SWITCH_CORE_PN_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_Port_3_SWITCH_RESV_MASK 0xfffc0000
-#define BCHP_SWITCH_CORE_PN_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_Port_3_SWITCH_RESV_SHIFT 18
-#define BCHP_SWITCH_CORE_PN_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_Port_3_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: PN_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_Port_3 :: MAX_THD_SEL [17:00] */
-#define BCHP_SWITCH_CORE_PN_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_Port_3_MAX_THD_SEL_MASK 0x0003ffff
-#define BCHP_SWITCH_CORE_PN_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_Port_3_MAX_THD_SEL_SHIFT 0
-#define BCHP_SWITCH_CORE_PN_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_Port_3_MAX_THD_SEL_DEFAULT 0x00000000
-
-/***************************************************************************
- *PN_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_Port_4 - Port N, Packet-Based, Port Shaper Burst Size Configure Register
- ***************************************************************************/
-/* SWITCH_CORE :: PN_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_Port_4 :: SWITCH_RESV [31:18] */
-#define BCHP_SWITCH_CORE_PN_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_Port_4_SWITCH_RESV_MASK 0xfffc0000
-#define BCHP_SWITCH_CORE_PN_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_Port_4_SWITCH_RESV_SHIFT 18
-#define BCHP_SWITCH_CORE_PN_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_Port_4_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: PN_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_Port_4 :: MAX_THD_SEL [17:00] */
-#define BCHP_SWITCH_CORE_PN_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_Port_4_MAX_THD_SEL_MASK 0x0003ffff
-#define BCHP_SWITCH_CORE_PN_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_Port_4_MAX_THD_SEL_SHIFT 0
-#define BCHP_SWITCH_CORE_PN_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_Port_4_MAX_THD_SEL_DEFAULT 0x00000000
-
-/***************************************************************************
- *PN_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_Port_5 - Port N, Packet-Based, Port Shaper Burst Size Configure Register
- ***************************************************************************/
-/* SWITCH_CORE :: PN_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_Port_5 :: SWITCH_RESV [31:18] */
-#define BCHP_SWITCH_CORE_PN_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_Port_5_SWITCH_RESV_MASK 0xfffc0000
-#define BCHP_SWITCH_CORE_PN_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_Port_5_SWITCH_RESV_SHIFT 18
-#define BCHP_SWITCH_CORE_PN_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_Port_5_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: PN_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_Port_5 :: MAX_THD_SEL [17:00] */
-#define BCHP_SWITCH_CORE_PN_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_Port_5_MAX_THD_SEL_MASK 0x0003ffff
-#define BCHP_SWITCH_CORE_PN_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_Port_5_MAX_THD_SEL_SHIFT 0
-#define BCHP_SWITCH_CORE_PN_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_Port_5_MAX_THD_SEL_DEFAULT 0x00000000
-
-/***************************************************************************
- *P7_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL - Port 7, Packet-Based, Port Shaper Burst Size Configure Register
- ***************************************************************************/
-/* SWITCH_CORE :: P7_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL :: SWITCH_RESV [31:18] */
-#define BCHP_SWITCH_CORE_P7_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_SWITCH_RESV_MASK 0xfffc0000
-#define BCHP_SWITCH_CORE_P7_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_SWITCH_RESV_SHIFT 18
-#define BCHP_SWITCH_CORE_P7_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: P7_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL :: MAX_THD_SEL [17:00] */
-#define BCHP_SWITCH_CORE_P7_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_MAX_THD_SEL_MASK 0x0003ffff
-#define BCHP_SWITCH_CORE_P7_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_MAX_THD_SEL_SHIFT 0
-#define BCHP_SWITCH_CORE_P7_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_MAX_THD_SEL_DEFAULT 0x00000000
-
-/***************************************************************************
- *IMP_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL - Port 8, Packet-Based, Port Shaper Burst Size Configure Register
- ***************************************************************************/
-/* SWITCH_CORE :: IMP_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL :: SWITCH_RESV [31:18] */
-#define BCHP_SWITCH_CORE_IMP_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_SWITCH_RESV_MASK 0xfffc0000
-#define BCHP_SWITCH_CORE_IMP_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_SWITCH_RESV_SHIFT 18
-#define BCHP_SWITCH_CORE_IMP_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: IMP_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL :: MAX_THD_SEL [17:00] */
-#define BCHP_SWITCH_CORE_IMP_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_MAX_THD_SEL_MASK 0x0003ffff
-#define BCHP_SWITCH_CORE_IMP_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_MAX_THD_SEL_SHIFT 0
-#define BCHP_SWITCH_CORE_IMP_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_MAX_THD_SEL_DEFAULT 0x00000000
-
-/***************************************************************************
- *PORT_SHAPER_AVB_SHAPING_MODE - Port Shaper AVB Shaping Mode Control Register
- ***************************************************************************/
-/* SWITCH_CORE :: PORT_SHAPER_AVB_SHAPING_MODE :: reserved_for_padding0 [31:16] */
-#define BCHP_SWITCH_CORE_PORT_SHAPER_AVB_SHAPING_MODE_reserved_for_padding0_MASK 0xffff0000
-#define BCHP_SWITCH_CORE_PORT_SHAPER_AVB_SHAPING_MODE_reserved_for_padding0_SHIFT 16
-
-/* SWITCH_CORE :: PORT_SHAPER_AVB_SHAPING_MODE :: SWITCH_RESV [15:09] */
-#define BCHP_SWITCH_CORE_PORT_SHAPER_AVB_SHAPING_MODE_SWITCH_RESV_MASK 0x0000fe00
-#define BCHP_SWITCH_CORE_PORT_SHAPER_AVB_SHAPING_MODE_SWITCH_RESV_SHIFT 9
-#define BCHP_SWITCH_CORE_PORT_SHAPER_AVB_SHAPING_MODE_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: PORT_SHAPER_AVB_SHAPING_MODE :: PORT_SHAPER_AVB_SHAPING_MODE [08:00] */
-#define BCHP_SWITCH_CORE_PORT_SHAPER_AVB_SHAPING_MODE_PORT_SHAPER_AVB_SHAPING_MODE_MASK 0x000001ff
-#define BCHP_SWITCH_CORE_PORT_SHAPER_AVB_SHAPING_MODE_PORT_SHAPER_AVB_SHAPING_MODE_SHIFT 0
-#define BCHP_SWITCH_CORE_PORT_SHAPER_AVB_SHAPING_MODE_PORT_SHAPER_AVB_SHAPING_MODE_DEFAULT 0x00000000
-
-/***************************************************************************
- *PORT_SHAPER_ENABLE - Port Shaper Enable Register
- ***************************************************************************/
-/* SWITCH_CORE :: PORT_SHAPER_ENABLE :: reserved_for_padding0 [31:16] */
-#define BCHP_SWITCH_CORE_PORT_SHAPER_ENABLE_reserved_for_padding0_MASK 0xffff0000
-#define BCHP_SWITCH_CORE_PORT_SHAPER_ENABLE_reserved_for_padding0_SHIFT 16
-
-/* SWITCH_CORE :: PORT_SHAPER_ENABLE :: SWITCH_RESV [15:09] */
-#define BCHP_SWITCH_CORE_PORT_SHAPER_ENABLE_SWITCH_RESV_MASK 0x0000fe00
-#define BCHP_SWITCH_CORE_PORT_SHAPER_ENABLE_SWITCH_RESV_SHIFT 9
-#define BCHP_SWITCH_CORE_PORT_SHAPER_ENABLE_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: PORT_SHAPER_ENABLE :: PORT_SHAPER_ENABLE [08:00] */
-#define BCHP_SWITCH_CORE_PORT_SHAPER_ENABLE_PORT_SHAPER_ENABLE_MASK 0x000001ff
-#define BCHP_SWITCH_CORE_PORT_SHAPER_ENABLE_PORT_SHAPER_ENABLE_SHIFT 0
-#define BCHP_SWITCH_CORE_PORT_SHAPER_ENABLE_PORT_SHAPER_ENABLE_DEFAULT 0x00000000
-
-/***************************************************************************
- *PORT_SHAPER_BUCKET_COUNT_SELECT - Port Shaper Bucket Count Select Register
- ***************************************************************************/
-/* SWITCH_CORE :: PORT_SHAPER_BUCKET_COUNT_SELECT :: reserved_for_padding0 [31:16] */
-#define BCHP_SWITCH_CORE_PORT_SHAPER_BUCKET_COUNT_SELECT_reserved_for_padding0_MASK 0xffff0000
-#define BCHP_SWITCH_CORE_PORT_SHAPER_BUCKET_COUNT_SELECT_reserved_for_padding0_SHIFT 16
-
-/* SWITCH_CORE :: PORT_SHAPER_BUCKET_COUNT_SELECT :: SWITCH_RESV [15:09] */
-#define BCHP_SWITCH_CORE_PORT_SHAPER_BUCKET_COUNT_SELECT_SWITCH_RESV_MASK 0x0000fe00
-#define BCHP_SWITCH_CORE_PORT_SHAPER_BUCKET_COUNT_SELECT_SWITCH_RESV_SHIFT 9
-#define BCHP_SWITCH_CORE_PORT_SHAPER_BUCKET_COUNT_SELECT_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: PORT_SHAPER_BUCKET_COUNT_SELECT :: PORT_SHAPER_BUCKET_COUNT_SELECT [08:00] */
-#define BCHP_SWITCH_CORE_PORT_SHAPER_BUCKET_COUNT_SELECT_PORT_SHAPER_BUCKET_COUNT_SELECT_MASK 0x000001ff
-#define BCHP_SWITCH_CORE_PORT_SHAPER_BUCKET_COUNT_SELECT_PORT_SHAPER_BUCKET_COUNT_SELECT_SHIFT 0
-#define BCHP_SWITCH_CORE_PORT_SHAPER_BUCKET_COUNT_SELECT_PORT_SHAPER_BUCKET_COUNT_SELECT_DEFAULT 0x00000000
-
-/***************************************************************************
- *PORT_SHAPER_BLOCKING - Port Shaper Blocking Control Register
- ***************************************************************************/
-/* SWITCH_CORE :: PORT_SHAPER_BLOCKING :: reserved_for_padding0 [31:16] */
-#define BCHP_SWITCH_CORE_PORT_SHAPER_BLOCKING_reserved_for_padding0_MASK 0xffff0000
-#define BCHP_SWITCH_CORE_PORT_SHAPER_BLOCKING_reserved_for_padding0_SHIFT 16
-
-/* SWITCH_CORE :: PORT_SHAPER_BLOCKING :: SWITCH_RESV [15:09] */
-#define BCHP_SWITCH_CORE_PORT_SHAPER_BLOCKING_SWITCH_RESV_MASK 0x0000fe00
-#define BCHP_SWITCH_CORE_PORT_SHAPER_BLOCKING_SWITCH_RESV_SHIFT 9
-#define BCHP_SWITCH_CORE_PORT_SHAPER_BLOCKING_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: PORT_SHAPER_BLOCKING :: PORT_SHAPER_BLOCKING [08:00] */
-#define BCHP_SWITCH_CORE_PORT_SHAPER_BLOCKING_PORT_SHAPER_BLOCKING_MASK 0x000001ff
-#define BCHP_SWITCH_CORE_PORT_SHAPER_BLOCKING_PORT_SHAPER_BLOCKING_SHIFT 0
-#define BCHP_SWITCH_CORE_PORT_SHAPER_BLOCKING_PORT_SHAPER_BLOCKING_DEFAULT 0x00000000
-
-/***************************************************************************
- *IFG_BYTES - IFG Correction Control Register
- ***************************************************************************/
-/* SWITCH_CORE :: IFG_BYTES :: reserved_for_padding0 [31:16] */
-#define BCHP_SWITCH_CORE_IFG_BYTES_reserved_for_padding0_MASK 0xffff0000
-#define BCHP_SWITCH_CORE_IFG_BYTES_reserved_for_padding0_SHIFT 16
-
-/* SWITCH_CORE :: IFG_BYTES :: SWITCH_RESV [15:09] */
-#define BCHP_SWITCH_CORE_IFG_BYTES_SWITCH_RESV_MASK 0x0000fe00
-#define BCHP_SWITCH_CORE_IFG_BYTES_SWITCH_RESV_SHIFT 9
-#define BCHP_SWITCH_CORE_IFG_BYTES_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: IFG_BYTES :: IFG_BYTES [08:00] */
-#define BCHP_SWITCH_CORE_IFG_BYTES_IFG_BYTES_MASK 0x000001ff
-#define BCHP_SWITCH_CORE_IFG_BYTES_IFG_BYTES_SHIFT 0
-#define BCHP_SWITCH_CORE_IFG_BYTES_IFG_BYTES_DEFAULT 0x00000000
-
-/***************************************************************************
- *PN_QUEUE0_MAX_REFRESH_Port_0 - Port N, Byte-based Queue 0 Shaping Rate Configure Register
- ***************************************************************************/
-/* SWITCH_CORE :: PN_QUEUE0_MAX_REFRESH_Port_0 :: SWITCH_RESV [31:18] */
-#define BCHP_SWITCH_CORE_PN_QUEUE0_MAX_REFRESH_Port_0_SWITCH_RESV_MASK 0xfffc0000
-#define BCHP_SWITCH_CORE_PN_QUEUE0_MAX_REFRESH_Port_0_SWITCH_RESV_SHIFT 18
-#define BCHP_SWITCH_CORE_PN_QUEUE0_MAX_REFRESH_Port_0_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: PN_QUEUE0_MAX_REFRESH_Port_0 :: MAX_REFRESH [17:00] */
-#define BCHP_SWITCH_CORE_PN_QUEUE0_MAX_REFRESH_Port_0_MAX_REFRESH_MASK 0x0003ffff
-#define BCHP_SWITCH_CORE_PN_QUEUE0_MAX_REFRESH_Port_0_MAX_REFRESH_SHIFT 0
-#define BCHP_SWITCH_CORE_PN_QUEUE0_MAX_REFRESH_Port_0_MAX_REFRESH_DEFAULT 0x00000000
-
-/***************************************************************************
- *PN_QUEUE0_MAX_REFRESH_Port_1 - Port N, Byte-based Queue 0 Shaping Rate Configure Register
- ***************************************************************************/
-/* SWITCH_CORE :: PN_QUEUE0_MAX_REFRESH_Port_1 :: SWITCH_RESV [31:18] */
-#define BCHP_SWITCH_CORE_PN_QUEUE0_MAX_REFRESH_Port_1_SWITCH_RESV_MASK 0xfffc0000
-#define BCHP_SWITCH_CORE_PN_QUEUE0_MAX_REFRESH_Port_1_SWITCH_RESV_SHIFT 18
-#define BCHP_SWITCH_CORE_PN_QUEUE0_MAX_REFRESH_Port_1_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: PN_QUEUE0_MAX_REFRESH_Port_1 :: MAX_REFRESH [17:00] */
-#define BCHP_SWITCH_CORE_PN_QUEUE0_MAX_REFRESH_Port_1_MAX_REFRESH_MASK 0x0003ffff
-#define BCHP_SWITCH_CORE_PN_QUEUE0_MAX_REFRESH_Port_1_MAX_REFRESH_SHIFT 0
-#define BCHP_SWITCH_CORE_PN_QUEUE0_MAX_REFRESH_Port_1_MAX_REFRESH_DEFAULT 0x00000000
-
-/***************************************************************************
- *PN_QUEUE0_MAX_REFRESH_Port_2 - Port N, Byte-based Queue 0 Shaping Rate Configure Register
- ***************************************************************************/
-/* SWITCH_CORE :: PN_QUEUE0_MAX_REFRESH_Port_2 :: SWITCH_RESV [31:18] */
-#define BCHP_SWITCH_CORE_PN_QUEUE0_MAX_REFRESH_Port_2_SWITCH_RESV_MASK 0xfffc0000
-#define BCHP_SWITCH_CORE_PN_QUEUE0_MAX_REFRESH_Port_2_SWITCH_RESV_SHIFT 18
-#define BCHP_SWITCH_CORE_PN_QUEUE0_MAX_REFRESH_Port_2_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: PN_QUEUE0_MAX_REFRESH_Port_2 :: MAX_REFRESH [17:00] */
-#define BCHP_SWITCH_CORE_PN_QUEUE0_MAX_REFRESH_Port_2_MAX_REFRESH_MASK 0x0003ffff
-#define BCHP_SWITCH_CORE_PN_QUEUE0_MAX_REFRESH_Port_2_MAX_REFRESH_SHIFT 0
-#define BCHP_SWITCH_CORE_PN_QUEUE0_MAX_REFRESH_Port_2_MAX_REFRESH_DEFAULT 0x00000000
-
-/***************************************************************************
- *PN_QUEUE0_MAX_REFRESH_Port_3 - Port N, Byte-based Queue 0 Shaping Rate Configure Register
- ***************************************************************************/
-/* SWITCH_CORE :: PN_QUEUE0_MAX_REFRESH_Port_3 :: SWITCH_RESV [31:18] */
-#define BCHP_SWITCH_CORE_PN_QUEUE0_MAX_REFRESH_Port_3_SWITCH_RESV_MASK 0xfffc0000
-#define BCHP_SWITCH_CORE_PN_QUEUE0_MAX_REFRESH_Port_3_SWITCH_RESV_SHIFT 18
-#define BCHP_SWITCH_CORE_PN_QUEUE0_MAX_REFRESH_Port_3_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: PN_QUEUE0_MAX_REFRESH_Port_3 :: MAX_REFRESH [17:00] */
-#define BCHP_SWITCH_CORE_PN_QUEUE0_MAX_REFRESH_Port_3_MAX_REFRESH_MASK 0x0003ffff
-#define BCHP_SWITCH_CORE_PN_QUEUE0_MAX_REFRESH_Port_3_MAX_REFRESH_SHIFT 0
-#define BCHP_SWITCH_CORE_PN_QUEUE0_MAX_REFRESH_Port_3_MAX_REFRESH_DEFAULT 0x00000000
-
-/***************************************************************************
- *PN_QUEUE0_MAX_REFRESH_Port_4 - Port N, Byte-based Queue 0 Shaping Rate Configure Register
- ***************************************************************************/
-/* SWITCH_CORE :: PN_QUEUE0_MAX_REFRESH_Port_4 :: SWITCH_RESV [31:18] */
-#define BCHP_SWITCH_CORE_PN_QUEUE0_MAX_REFRESH_Port_4_SWITCH_RESV_MASK 0xfffc0000
-#define BCHP_SWITCH_CORE_PN_QUEUE0_MAX_REFRESH_Port_4_SWITCH_RESV_SHIFT 18
-#define BCHP_SWITCH_CORE_PN_QUEUE0_MAX_REFRESH_Port_4_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: PN_QUEUE0_MAX_REFRESH_Port_4 :: MAX_REFRESH [17:00] */
-#define BCHP_SWITCH_CORE_PN_QUEUE0_MAX_REFRESH_Port_4_MAX_REFRESH_MASK 0x0003ffff
-#define BCHP_SWITCH_CORE_PN_QUEUE0_MAX_REFRESH_Port_4_MAX_REFRESH_SHIFT 0
-#define BCHP_SWITCH_CORE_PN_QUEUE0_MAX_REFRESH_Port_4_MAX_REFRESH_DEFAULT 0x00000000
-
-/***************************************************************************
- *PN_QUEUE0_MAX_REFRESH_Port_5 - Port N, Byte-based Queue 0 Shaping Rate Configure Register
- ***************************************************************************/
-/* SWITCH_CORE :: PN_QUEUE0_MAX_REFRESH_Port_5 :: SWITCH_RESV [31:18] */
-#define BCHP_SWITCH_CORE_PN_QUEUE0_MAX_REFRESH_Port_5_SWITCH_RESV_MASK 0xfffc0000
-#define BCHP_SWITCH_CORE_PN_QUEUE0_MAX_REFRESH_Port_5_SWITCH_RESV_SHIFT 18
-#define BCHP_SWITCH_CORE_PN_QUEUE0_MAX_REFRESH_Port_5_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: PN_QUEUE0_MAX_REFRESH_Port_5 :: MAX_REFRESH [17:00] */
-#define BCHP_SWITCH_CORE_PN_QUEUE0_MAX_REFRESH_Port_5_MAX_REFRESH_MASK 0x0003ffff
-#define BCHP_SWITCH_CORE_PN_QUEUE0_MAX_REFRESH_Port_5_MAX_REFRESH_SHIFT 0
-#define BCHP_SWITCH_CORE_PN_QUEUE0_MAX_REFRESH_Port_5_MAX_REFRESH_DEFAULT 0x00000000
-
-/***************************************************************************
- *P7_QUEUE0_MAX_REFRESH - Port 7, Byte-based Queue 0 Shaping Rate Configure Register
- ***************************************************************************/
-/* SWITCH_CORE :: P7_QUEUE0_MAX_REFRESH :: SWITCH_RESV [31:18] */
-#define BCHP_SWITCH_CORE_P7_QUEUE0_MAX_REFRESH_SWITCH_RESV_MASK 0xfffc0000
-#define BCHP_SWITCH_CORE_P7_QUEUE0_MAX_REFRESH_SWITCH_RESV_SHIFT 18
-#define BCHP_SWITCH_CORE_P7_QUEUE0_MAX_REFRESH_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: P7_QUEUE0_MAX_REFRESH :: MAX_REFRESH [17:00] */
-#define BCHP_SWITCH_CORE_P7_QUEUE0_MAX_REFRESH_MAX_REFRESH_MASK 0x0003ffff
-#define BCHP_SWITCH_CORE_P7_QUEUE0_MAX_REFRESH_MAX_REFRESH_SHIFT 0
-#define BCHP_SWITCH_CORE_P7_QUEUE0_MAX_REFRESH_MAX_REFRESH_DEFAULT 0x00000000
-
-/***************************************************************************
- *IMP_QUEUE0_MAX_REFRESH - Port 8, Byte-based Queue 0 Shaping Rate Configure Register
- ***************************************************************************/
-/* SWITCH_CORE :: IMP_QUEUE0_MAX_REFRESH :: SWITCH_RESV [31:18] */
-#define BCHP_SWITCH_CORE_IMP_QUEUE0_MAX_REFRESH_SWITCH_RESV_MASK 0xfffc0000
-#define BCHP_SWITCH_CORE_IMP_QUEUE0_MAX_REFRESH_SWITCH_RESV_SHIFT 18
-#define BCHP_SWITCH_CORE_IMP_QUEUE0_MAX_REFRESH_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: IMP_QUEUE0_MAX_REFRESH :: MAX_REFRESH [17:00] */
-#define BCHP_SWITCH_CORE_IMP_QUEUE0_MAX_REFRESH_MAX_REFRESH_MASK 0x0003ffff
-#define BCHP_SWITCH_CORE_IMP_QUEUE0_MAX_REFRESH_MAX_REFRESH_SHIFT 0
-#define BCHP_SWITCH_CORE_IMP_QUEUE0_MAX_REFRESH_MAX_REFRESH_DEFAULT 0x00000000
-
-/***************************************************************************
- *PN_QUEUE0_MAX_THD_SEL_Port_0 - Port N, Byte-based Queue 0 Burst Size Configure Register
- ***************************************************************************/
-/* SWITCH_CORE :: PN_QUEUE0_MAX_THD_SEL_Port_0 :: SWITCH_RESV [31:18] */
-#define BCHP_SWITCH_CORE_PN_QUEUE0_MAX_THD_SEL_Port_0_SWITCH_RESV_MASK 0xfffc0000
-#define BCHP_SWITCH_CORE_PN_QUEUE0_MAX_THD_SEL_Port_0_SWITCH_RESV_SHIFT 18
-#define BCHP_SWITCH_CORE_PN_QUEUE0_MAX_THD_SEL_Port_0_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: PN_QUEUE0_MAX_THD_SEL_Port_0 :: MAX_THD_SEL [17:00] */
-#define BCHP_SWITCH_CORE_PN_QUEUE0_MAX_THD_SEL_Port_0_MAX_THD_SEL_MASK 0x0003ffff
-#define BCHP_SWITCH_CORE_PN_QUEUE0_MAX_THD_SEL_Port_0_MAX_THD_SEL_SHIFT 0
-#define BCHP_SWITCH_CORE_PN_QUEUE0_MAX_THD_SEL_Port_0_MAX_THD_SEL_DEFAULT 0x00000000
-
-/***************************************************************************
- *PN_QUEUE0_MAX_THD_SEL_Port_1 - Port N, Byte-based Queue 0 Burst Size Configure Register
- ***************************************************************************/
-/* SWITCH_CORE :: PN_QUEUE0_MAX_THD_SEL_Port_1 :: SWITCH_RESV [31:18] */
-#define BCHP_SWITCH_CORE_PN_QUEUE0_MAX_THD_SEL_Port_1_SWITCH_RESV_MASK 0xfffc0000
-#define BCHP_SWITCH_CORE_PN_QUEUE0_MAX_THD_SEL_Port_1_SWITCH_RESV_SHIFT 18
-#define BCHP_SWITCH_CORE_PN_QUEUE0_MAX_THD_SEL_Port_1_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: PN_QUEUE0_MAX_THD_SEL_Port_1 :: MAX_THD_SEL [17:00] */
-#define BCHP_SWITCH_CORE_PN_QUEUE0_MAX_THD_SEL_Port_1_MAX_THD_SEL_MASK 0x0003ffff
-#define BCHP_SWITCH_CORE_PN_QUEUE0_MAX_THD_SEL_Port_1_MAX_THD_SEL_SHIFT 0
-#define BCHP_SWITCH_CORE_PN_QUEUE0_MAX_THD_SEL_Port_1_MAX_THD_SEL_DEFAULT 0x00000000
-
-/***************************************************************************
- *PN_QUEUE0_MAX_THD_SEL_Port_2 - Port N, Byte-based Queue 0 Burst Size Configure Register
- ***************************************************************************/
-/* SWITCH_CORE :: PN_QUEUE0_MAX_THD_SEL_Port_2 :: SWITCH_RESV [31:18] */
-#define BCHP_SWITCH_CORE_PN_QUEUE0_MAX_THD_SEL_Port_2_SWITCH_RESV_MASK 0xfffc0000
-#define BCHP_SWITCH_CORE_PN_QUEUE0_MAX_THD_SEL_Port_2_SWITCH_RESV_SHIFT 18
-#define BCHP_SWITCH_CORE_PN_QUEUE0_MAX_THD_SEL_Port_2_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: PN_QUEUE0_MAX_THD_SEL_Port_2 :: MAX_THD_SEL [17:00] */
-#define BCHP_SWITCH_CORE_PN_QUEUE0_MAX_THD_SEL_Port_2_MAX_THD_SEL_MASK 0x0003ffff
-#define BCHP_SWITCH_CORE_PN_QUEUE0_MAX_THD_SEL_Port_2_MAX_THD_SEL_SHIFT 0
-#define BCHP_SWITCH_CORE_PN_QUEUE0_MAX_THD_SEL_Port_2_MAX_THD_SEL_DEFAULT 0x00000000
-
-/***************************************************************************
- *PN_QUEUE0_MAX_THD_SEL_Port_3 - Port N, Byte-based Queue 0 Burst Size Configure Register
- ***************************************************************************/
-/* SWITCH_CORE :: PN_QUEUE0_MAX_THD_SEL_Port_3 :: SWITCH_RESV [31:18] */
-#define BCHP_SWITCH_CORE_PN_QUEUE0_MAX_THD_SEL_Port_3_SWITCH_RESV_MASK 0xfffc0000
-#define BCHP_SWITCH_CORE_PN_QUEUE0_MAX_THD_SEL_Port_3_SWITCH_RESV_SHIFT 18
-#define BCHP_SWITCH_CORE_PN_QUEUE0_MAX_THD_SEL_Port_3_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: PN_QUEUE0_MAX_THD_SEL_Port_3 :: MAX_THD_SEL [17:00] */
-#define BCHP_SWITCH_CORE_PN_QUEUE0_MAX_THD_SEL_Port_3_MAX_THD_SEL_MASK 0x0003ffff
-#define BCHP_SWITCH_CORE_PN_QUEUE0_MAX_THD_SEL_Port_3_MAX_THD_SEL_SHIFT 0
-#define BCHP_SWITCH_CORE_PN_QUEUE0_MAX_THD_SEL_Port_3_MAX_THD_SEL_DEFAULT 0x00000000
-
-/***************************************************************************
- *PN_QUEUE0_MAX_THD_SEL_Port_4 - Port N, Byte-based Queue 0 Burst Size Configure Register
- ***************************************************************************/
-/* SWITCH_CORE :: PN_QUEUE0_MAX_THD_SEL_Port_4 :: SWITCH_RESV [31:18] */
-#define BCHP_SWITCH_CORE_PN_QUEUE0_MAX_THD_SEL_Port_4_SWITCH_RESV_MASK 0xfffc0000
-#define BCHP_SWITCH_CORE_PN_QUEUE0_MAX_THD_SEL_Port_4_SWITCH_RESV_SHIFT 18
-#define BCHP_SWITCH_CORE_PN_QUEUE0_MAX_THD_SEL_Port_4_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: PN_QUEUE0_MAX_THD_SEL_Port_4 :: MAX_THD_SEL [17:00] */
-#define BCHP_SWITCH_CORE_PN_QUEUE0_MAX_THD_SEL_Port_4_MAX_THD_SEL_MASK 0x0003ffff
-#define BCHP_SWITCH_CORE_PN_QUEUE0_MAX_THD_SEL_Port_4_MAX_THD_SEL_SHIFT 0
-#define BCHP_SWITCH_CORE_PN_QUEUE0_MAX_THD_SEL_Port_4_MAX_THD_SEL_DEFAULT 0x00000000
-
-/***************************************************************************
- *PN_QUEUE0_MAX_THD_SEL_Port_5 - Port N, Byte-based Queue 0 Burst Size Configure Register
- ***************************************************************************/
-/* SWITCH_CORE :: PN_QUEUE0_MAX_THD_SEL_Port_5 :: SWITCH_RESV [31:18] */
-#define BCHP_SWITCH_CORE_PN_QUEUE0_MAX_THD_SEL_Port_5_SWITCH_RESV_MASK 0xfffc0000
-#define BCHP_SWITCH_CORE_PN_QUEUE0_MAX_THD_SEL_Port_5_SWITCH_RESV_SHIFT 18
-#define BCHP_SWITCH_CORE_PN_QUEUE0_MAX_THD_SEL_Port_5_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: PN_QUEUE0_MAX_THD_SEL_Port_5 :: MAX_THD_SEL [17:00] */
-#define BCHP_SWITCH_CORE_PN_QUEUE0_MAX_THD_SEL_Port_5_MAX_THD_SEL_MASK 0x0003ffff
-#define BCHP_SWITCH_CORE_PN_QUEUE0_MAX_THD_SEL_Port_5_MAX_THD_SEL_SHIFT 0
-#define BCHP_SWITCH_CORE_PN_QUEUE0_MAX_THD_SEL_Port_5_MAX_THD_SEL_DEFAULT 0x00000000
-
-/***************************************************************************
- *P7_QUEUE0_MAX_THD_SEL - Port 7, Byte-based Queue 0 Burst Size Configure Register
- ***************************************************************************/
-/* SWITCH_CORE :: P7_QUEUE0_MAX_THD_SEL :: SWITCH_RESV [31:18] */
-#define BCHP_SWITCH_CORE_P7_QUEUE0_MAX_THD_SEL_SWITCH_RESV_MASK 0xfffc0000
-#define BCHP_SWITCH_CORE_P7_QUEUE0_MAX_THD_SEL_SWITCH_RESV_SHIFT 18
-#define BCHP_SWITCH_CORE_P7_QUEUE0_MAX_THD_SEL_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: P7_QUEUE0_MAX_THD_SEL :: MAX_THD_SEL [17:00] */
-#define BCHP_SWITCH_CORE_P7_QUEUE0_MAX_THD_SEL_MAX_THD_SEL_MASK 0x0003ffff
-#define BCHP_SWITCH_CORE_P7_QUEUE0_MAX_THD_SEL_MAX_THD_SEL_SHIFT 0
-#define BCHP_SWITCH_CORE_P7_QUEUE0_MAX_THD_SEL_MAX_THD_SEL_DEFAULT 0x00000000
-
-/***************************************************************************
- *IMP_QUEUE0_MAX_THD_SEL - Port 8, Byte-based Queue 0 Burst Size Configure Register
- ***************************************************************************/
-/* SWITCH_CORE :: IMP_QUEUE0_MAX_THD_SEL :: SWITCH_RESV [31:18] */
-#define BCHP_SWITCH_CORE_IMP_QUEUE0_MAX_THD_SEL_SWITCH_RESV_MASK 0xfffc0000
-#define BCHP_SWITCH_CORE_IMP_QUEUE0_MAX_THD_SEL_SWITCH_RESV_SHIFT 18
-#define BCHP_SWITCH_CORE_IMP_QUEUE0_MAX_THD_SEL_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: IMP_QUEUE0_MAX_THD_SEL :: MAX_THD_SEL [17:00] */
-#define BCHP_SWITCH_CORE_IMP_QUEUE0_MAX_THD_SEL_MAX_THD_SEL_MASK 0x0003ffff
-#define BCHP_SWITCH_CORE_IMP_QUEUE0_MAX_THD_SEL_MAX_THD_SEL_SHIFT 0
-#define BCHP_SWITCH_CORE_IMP_QUEUE0_MAX_THD_SEL_MAX_THD_SEL_DEFAULT 0x00000000
-
-/***************************************************************************
- *PN_QUEUE0_SHAPER_STS_Port_0 - Port N, Queue 0 Shaper Status Register
- ***************************************************************************/
-/* SWITCH_CORE :: PN_QUEUE0_SHAPER_STS_Port_0 :: IN_PROFILE_FLAG [31:31] */
-#define BCHP_SWITCH_CORE_PN_QUEUE0_SHAPER_STS_Port_0_IN_PROFILE_FLAG_MASK 0x80000000
-#define BCHP_SWITCH_CORE_PN_QUEUE0_SHAPER_STS_Port_0_IN_PROFILE_FLAG_SHIFT 31
-#define BCHP_SWITCH_CORE_PN_QUEUE0_SHAPER_STS_Port_0_IN_PROFILE_FLAG_DEFAULT 0x00000001
-
-/* SWITCH_CORE :: PN_QUEUE0_SHAPER_STS_Port_0 :: SWITCH_RESV [30:29] */
-#define BCHP_SWITCH_CORE_PN_QUEUE0_SHAPER_STS_Port_0_SWITCH_RESV_MASK 0x60000000
-#define BCHP_SWITCH_CORE_PN_QUEUE0_SHAPER_STS_Port_0_SWITCH_RESV_SHIFT 29
-#define BCHP_SWITCH_CORE_PN_QUEUE0_SHAPER_STS_Port_0_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: PN_QUEUE0_SHAPER_STS_Port_0 :: BUCKET_CNT [28:00] */
-#define BCHP_SWITCH_CORE_PN_QUEUE0_SHAPER_STS_Port_0_BUCKET_CNT_MASK 0x1fffffff
-#define BCHP_SWITCH_CORE_PN_QUEUE0_SHAPER_STS_Port_0_BUCKET_CNT_SHIFT 0
-#define BCHP_SWITCH_CORE_PN_QUEUE0_SHAPER_STS_Port_0_BUCKET_CNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *PN_QUEUE0_SHAPER_STS_Port_1 - Port N, Queue 0 Shaper Status Register
- ***************************************************************************/
-/* SWITCH_CORE :: PN_QUEUE0_SHAPER_STS_Port_1 :: IN_PROFILE_FLAG [31:31] */
-#define BCHP_SWITCH_CORE_PN_QUEUE0_SHAPER_STS_Port_1_IN_PROFILE_FLAG_MASK 0x80000000
-#define BCHP_SWITCH_CORE_PN_QUEUE0_SHAPER_STS_Port_1_IN_PROFILE_FLAG_SHIFT 31
-#define BCHP_SWITCH_CORE_PN_QUEUE0_SHAPER_STS_Port_1_IN_PROFILE_FLAG_DEFAULT 0x00000001
-
-/* SWITCH_CORE :: PN_QUEUE0_SHAPER_STS_Port_1 :: SWITCH_RESV [30:29] */
-#define BCHP_SWITCH_CORE_PN_QUEUE0_SHAPER_STS_Port_1_SWITCH_RESV_MASK 0x60000000
-#define BCHP_SWITCH_CORE_PN_QUEUE0_SHAPER_STS_Port_1_SWITCH_RESV_SHIFT 29
-#define BCHP_SWITCH_CORE_PN_QUEUE0_SHAPER_STS_Port_1_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: PN_QUEUE0_SHAPER_STS_Port_1 :: BUCKET_CNT [28:00] */
-#define BCHP_SWITCH_CORE_PN_QUEUE0_SHAPER_STS_Port_1_BUCKET_CNT_MASK 0x1fffffff
-#define BCHP_SWITCH_CORE_PN_QUEUE0_SHAPER_STS_Port_1_BUCKET_CNT_SHIFT 0
-#define BCHP_SWITCH_CORE_PN_QUEUE0_SHAPER_STS_Port_1_BUCKET_CNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *PN_QUEUE0_SHAPER_STS_Port_2 - Port N, Queue 0 Shaper Status Register
- ***************************************************************************/
-/* SWITCH_CORE :: PN_QUEUE0_SHAPER_STS_Port_2 :: IN_PROFILE_FLAG [31:31] */
-#define BCHP_SWITCH_CORE_PN_QUEUE0_SHAPER_STS_Port_2_IN_PROFILE_FLAG_MASK 0x80000000
-#define BCHP_SWITCH_CORE_PN_QUEUE0_SHAPER_STS_Port_2_IN_PROFILE_FLAG_SHIFT 31
-#define BCHP_SWITCH_CORE_PN_QUEUE0_SHAPER_STS_Port_2_IN_PROFILE_FLAG_DEFAULT 0x00000001
-
-/* SWITCH_CORE :: PN_QUEUE0_SHAPER_STS_Port_2 :: SWITCH_RESV [30:29] */
-#define BCHP_SWITCH_CORE_PN_QUEUE0_SHAPER_STS_Port_2_SWITCH_RESV_MASK 0x60000000
-#define BCHP_SWITCH_CORE_PN_QUEUE0_SHAPER_STS_Port_2_SWITCH_RESV_SHIFT 29
-#define BCHP_SWITCH_CORE_PN_QUEUE0_SHAPER_STS_Port_2_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: PN_QUEUE0_SHAPER_STS_Port_2 :: BUCKET_CNT [28:00] */
-#define BCHP_SWITCH_CORE_PN_QUEUE0_SHAPER_STS_Port_2_BUCKET_CNT_MASK 0x1fffffff
-#define BCHP_SWITCH_CORE_PN_QUEUE0_SHAPER_STS_Port_2_BUCKET_CNT_SHIFT 0
-#define BCHP_SWITCH_CORE_PN_QUEUE0_SHAPER_STS_Port_2_BUCKET_CNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *PN_QUEUE0_SHAPER_STS_Port_3 - Port N, Queue 0 Shaper Status Register
- ***************************************************************************/
-/* SWITCH_CORE :: PN_QUEUE0_SHAPER_STS_Port_3 :: IN_PROFILE_FLAG [31:31] */
-#define BCHP_SWITCH_CORE_PN_QUEUE0_SHAPER_STS_Port_3_IN_PROFILE_FLAG_MASK 0x80000000
-#define BCHP_SWITCH_CORE_PN_QUEUE0_SHAPER_STS_Port_3_IN_PROFILE_FLAG_SHIFT 31
-#define BCHP_SWITCH_CORE_PN_QUEUE0_SHAPER_STS_Port_3_IN_PROFILE_FLAG_DEFAULT 0x00000001
-
-/* SWITCH_CORE :: PN_QUEUE0_SHAPER_STS_Port_3 :: SWITCH_RESV [30:29] */
-#define BCHP_SWITCH_CORE_PN_QUEUE0_SHAPER_STS_Port_3_SWITCH_RESV_MASK 0x60000000
-#define BCHP_SWITCH_CORE_PN_QUEUE0_SHAPER_STS_Port_3_SWITCH_RESV_SHIFT 29
-#define BCHP_SWITCH_CORE_PN_QUEUE0_SHAPER_STS_Port_3_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: PN_QUEUE0_SHAPER_STS_Port_3 :: BUCKET_CNT [28:00] */
-#define BCHP_SWITCH_CORE_PN_QUEUE0_SHAPER_STS_Port_3_BUCKET_CNT_MASK 0x1fffffff
-#define BCHP_SWITCH_CORE_PN_QUEUE0_SHAPER_STS_Port_3_BUCKET_CNT_SHIFT 0
-#define BCHP_SWITCH_CORE_PN_QUEUE0_SHAPER_STS_Port_3_BUCKET_CNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *PN_QUEUE0_SHAPER_STS_Port_4 - Port N, Queue 0 Shaper Status Register
- ***************************************************************************/
-/* SWITCH_CORE :: PN_QUEUE0_SHAPER_STS_Port_4 :: IN_PROFILE_FLAG [31:31] */
-#define BCHP_SWITCH_CORE_PN_QUEUE0_SHAPER_STS_Port_4_IN_PROFILE_FLAG_MASK 0x80000000
-#define BCHP_SWITCH_CORE_PN_QUEUE0_SHAPER_STS_Port_4_IN_PROFILE_FLAG_SHIFT 31
-#define BCHP_SWITCH_CORE_PN_QUEUE0_SHAPER_STS_Port_4_IN_PROFILE_FLAG_DEFAULT 0x00000001
-
-/* SWITCH_CORE :: PN_QUEUE0_SHAPER_STS_Port_4 :: SWITCH_RESV [30:29] */
-#define BCHP_SWITCH_CORE_PN_QUEUE0_SHAPER_STS_Port_4_SWITCH_RESV_MASK 0x60000000
-#define BCHP_SWITCH_CORE_PN_QUEUE0_SHAPER_STS_Port_4_SWITCH_RESV_SHIFT 29
-#define BCHP_SWITCH_CORE_PN_QUEUE0_SHAPER_STS_Port_4_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: PN_QUEUE0_SHAPER_STS_Port_4 :: BUCKET_CNT [28:00] */
-#define BCHP_SWITCH_CORE_PN_QUEUE0_SHAPER_STS_Port_4_BUCKET_CNT_MASK 0x1fffffff
-#define BCHP_SWITCH_CORE_PN_QUEUE0_SHAPER_STS_Port_4_BUCKET_CNT_SHIFT 0
-#define BCHP_SWITCH_CORE_PN_QUEUE0_SHAPER_STS_Port_4_BUCKET_CNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *PN_QUEUE0_SHAPER_STS_Port_5 - Port N, Queue 0 Shaper Status Register
- ***************************************************************************/
-/* SWITCH_CORE :: PN_QUEUE0_SHAPER_STS_Port_5 :: IN_PROFILE_FLAG [31:31] */
-#define BCHP_SWITCH_CORE_PN_QUEUE0_SHAPER_STS_Port_5_IN_PROFILE_FLAG_MASK 0x80000000
-#define BCHP_SWITCH_CORE_PN_QUEUE0_SHAPER_STS_Port_5_IN_PROFILE_FLAG_SHIFT 31
-#define BCHP_SWITCH_CORE_PN_QUEUE0_SHAPER_STS_Port_5_IN_PROFILE_FLAG_DEFAULT 0x00000001
-
-/* SWITCH_CORE :: PN_QUEUE0_SHAPER_STS_Port_5 :: SWITCH_RESV [30:29] */
-#define BCHP_SWITCH_CORE_PN_QUEUE0_SHAPER_STS_Port_5_SWITCH_RESV_MASK 0x60000000
-#define BCHP_SWITCH_CORE_PN_QUEUE0_SHAPER_STS_Port_5_SWITCH_RESV_SHIFT 29
-#define BCHP_SWITCH_CORE_PN_QUEUE0_SHAPER_STS_Port_5_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: PN_QUEUE0_SHAPER_STS_Port_5 :: BUCKET_CNT [28:00] */
-#define BCHP_SWITCH_CORE_PN_QUEUE0_SHAPER_STS_Port_5_BUCKET_CNT_MASK 0x1fffffff
-#define BCHP_SWITCH_CORE_PN_QUEUE0_SHAPER_STS_Port_5_BUCKET_CNT_SHIFT 0
-#define BCHP_SWITCH_CORE_PN_QUEUE0_SHAPER_STS_Port_5_BUCKET_CNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *P7_QUEUE0_SHAPER_STS - Port 7, Queue 0 Shaper Status Register
- ***************************************************************************/
-/* SWITCH_CORE :: P7_QUEUE0_SHAPER_STS :: IN_PROFILE_FLAG [31:31] */
-#define BCHP_SWITCH_CORE_P7_QUEUE0_SHAPER_STS_IN_PROFILE_FLAG_MASK 0x80000000
-#define BCHP_SWITCH_CORE_P7_QUEUE0_SHAPER_STS_IN_PROFILE_FLAG_SHIFT 31
-#define BCHP_SWITCH_CORE_P7_QUEUE0_SHAPER_STS_IN_PROFILE_FLAG_DEFAULT 0x00000001
-
-/* SWITCH_CORE :: P7_QUEUE0_SHAPER_STS :: SWITCH_RESV [30:29] */
-#define BCHP_SWITCH_CORE_P7_QUEUE0_SHAPER_STS_SWITCH_RESV_MASK 0x60000000
-#define BCHP_SWITCH_CORE_P7_QUEUE0_SHAPER_STS_SWITCH_RESV_SHIFT 29
-#define BCHP_SWITCH_CORE_P7_QUEUE0_SHAPER_STS_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: P7_QUEUE0_SHAPER_STS :: BUCKET_CNT [28:00] */
-#define BCHP_SWITCH_CORE_P7_QUEUE0_SHAPER_STS_BUCKET_CNT_MASK 0x1fffffff
-#define BCHP_SWITCH_CORE_P7_QUEUE0_SHAPER_STS_BUCKET_CNT_SHIFT 0
-#define BCHP_SWITCH_CORE_P7_QUEUE0_SHAPER_STS_BUCKET_CNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *IMP_QUEUE0_SHAPER_STS - Port 8, Queue 0 Shaper Status Register
- ***************************************************************************/
-/* SWITCH_CORE :: IMP_QUEUE0_SHAPER_STS :: IN_PROFILE_FLAG [31:31] */
-#define BCHP_SWITCH_CORE_IMP_QUEUE0_SHAPER_STS_IN_PROFILE_FLAG_MASK 0x80000000
-#define BCHP_SWITCH_CORE_IMP_QUEUE0_SHAPER_STS_IN_PROFILE_FLAG_SHIFT 31
-#define BCHP_SWITCH_CORE_IMP_QUEUE0_SHAPER_STS_IN_PROFILE_FLAG_DEFAULT 0x00000001
-
-/* SWITCH_CORE :: IMP_QUEUE0_SHAPER_STS :: SWITCH_RESV [30:29] */
-#define BCHP_SWITCH_CORE_IMP_QUEUE0_SHAPER_STS_SWITCH_RESV_MASK 0x60000000
-#define BCHP_SWITCH_CORE_IMP_QUEUE0_SHAPER_STS_SWITCH_RESV_SHIFT 29
-#define BCHP_SWITCH_CORE_IMP_QUEUE0_SHAPER_STS_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: IMP_QUEUE0_SHAPER_STS :: BUCKET_CNT [28:00] */
-#define BCHP_SWITCH_CORE_IMP_QUEUE0_SHAPER_STS_BUCKET_CNT_MASK 0x1fffffff
-#define BCHP_SWITCH_CORE_IMP_QUEUE0_SHAPER_STS_BUCKET_CNT_SHIFT 0
-#define BCHP_SWITCH_CORE_IMP_QUEUE0_SHAPER_STS_BUCKET_CNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *PN_QUEUE0_MAX_PACKET_REFRESH_Port_0 - Port N, Packet-based Queue 0 Shaping Rate Configure Register
- ***************************************************************************/
-/* SWITCH_CORE :: PN_QUEUE0_MAX_PACKET_REFRESH_Port_0 :: SWITCH_RESV [31:18] */
-#define BCHP_SWITCH_CORE_PN_QUEUE0_MAX_PACKET_REFRESH_Port_0_SWITCH_RESV_MASK 0xfffc0000
-#define BCHP_SWITCH_CORE_PN_QUEUE0_MAX_PACKET_REFRESH_Port_0_SWITCH_RESV_SHIFT 18
-#define BCHP_SWITCH_CORE_PN_QUEUE0_MAX_PACKET_REFRESH_Port_0_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: PN_QUEUE0_MAX_PACKET_REFRESH_Port_0 :: MAX_REFRESH [17:00] */
-#define BCHP_SWITCH_CORE_PN_QUEUE0_MAX_PACKET_REFRESH_Port_0_MAX_REFRESH_MASK 0x0003ffff
-#define BCHP_SWITCH_CORE_PN_QUEUE0_MAX_PACKET_REFRESH_Port_0_MAX_REFRESH_SHIFT 0
-#define BCHP_SWITCH_CORE_PN_QUEUE0_MAX_PACKET_REFRESH_Port_0_MAX_REFRESH_DEFAULT 0x00000000
-
-/***************************************************************************
- *PN_QUEUE0_MAX_PACKET_REFRESH_Port_1 - Port N, Packet-based Queue 0 Shaping Rate Configure Register
- ***************************************************************************/
-/* SWITCH_CORE :: PN_QUEUE0_MAX_PACKET_REFRESH_Port_1 :: SWITCH_RESV [31:18] */
-#define BCHP_SWITCH_CORE_PN_QUEUE0_MAX_PACKET_REFRESH_Port_1_SWITCH_RESV_MASK 0xfffc0000
-#define BCHP_SWITCH_CORE_PN_QUEUE0_MAX_PACKET_REFRESH_Port_1_SWITCH_RESV_SHIFT 18
-#define BCHP_SWITCH_CORE_PN_QUEUE0_MAX_PACKET_REFRESH_Port_1_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: PN_QUEUE0_MAX_PACKET_REFRESH_Port_1 :: MAX_REFRESH [17:00] */
-#define BCHP_SWITCH_CORE_PN_QUEUE0_MAX_PACKET_REFRESH_Port_1_MAX_REFRESH_MASK 0x0003ffff
-#define BCHP_SWITCH_CORE_PN_QUEUE0_MAX_PACKET_REFRESH_Port_1_MAX_REFRESH_SHIFT 0
-#define BCHP_SWITCH_CORE_PN_QUEUE0_MAX_PACKET_REFRESH_Port_1_MAX_REFRESH_DEFAULT 0x00000000
-
-/***************************************************************************
- *PN_QUEUE0_MAX_PACKET_REFRESH_Port_2 - Port N, Packet-based Queue 0 Shaping Rate Configure Register
- ***************************************************************************/
-/* SWITCH_CORE :: PN_QUEUE0_MAX_PACKET_REFRESH_Port_2 :: SWITCH_RESV [31:18] */
-#define BCHP_SWITCH_CORE_PN_QUEUE0_MAX_PACKET_REFRESH_Port_2_SWITCH_RESV_MASK 0xfffc0000
-#define BCHP_SWITCH_CORE_PN_QUEUE0_MAX_PACKET_REFRESH_Port_2_SWITCH_RESV_SHIFT 18
-#define BCHP_SWITCH_CORE_PN_QUEUE0_MAX_PACKET_REFRESH_Port_2_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: PN_QUEUE0_MAX_PACKET_REFRESH_Port_2 :: MAX_REFRESH [17:00] */
-#define BCHP_SWITCH_CORE_PN_QUEUE0_MAX_PACKET_REFRESH_Port_2_MAX_REFRESH_MASK 0x0003ffff
-#define BCHP_SWITCH_CORE_PN_QUEUE0_MAX_PACKET_REFRESH_Port_2_MAX_REFRESH_SHIFT 0
-#define BCHP_SWITCH_CORE_PN_QUEUE0_MAX_PACKET_REFRESH_Port_2_MAX_REFRESH_DEFAULT 0x00000000
-
-/***************************************************************************
- *PN_QUEUE0_MAX_PACKET_REFRESH_Port_3 - Port N, Packet-based Queue 0 Shaping Rate Configure Register
- ***************************************************************************/
-/* SWITCH_CORE :: PN_QUEUE0_MAX_PACKET_REFRESH_Port_3 :: SWITCH_RESV [31:18] */
-#define BCHP_SWITCH_CORE_PN_QUEUE0_MAX_PACKET_REFRESH_Port_3_SWITCH_RESV_MASK 0xfffc0000
-#define BCHP_SWITCH_CORE_PN_QUEUE0_MAX_PACKET_REFRESH_Port_3_SWITCH_RESV_SHIFT 18
-#define BCHP_SWITCH_CORE_PN_QUEUE0_MAX_PACKET_REFRESH_Port_3_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: PN_QUEUE0_MAX_PACKET_REFRESH_Port_3 :: MAX_REFRESH [17:00] */
-#define BCHP_SWITCH_CORE_PN_QUEUE0_MAX_PACKET_REFRESH_Port_3_MAX_REFRESH_MASK 0x0003ffff
-#define BCHP_SWITCH_CORE_PN_QUEUE0_MAX_PACKET_REFRESH_Port_3_MAX_REFRESH_SHIFT 0
-#define BCHP_SWITCH_CORE_PN_QUEUE0_MAX_PACKET_REFRESH_Port_3_MAX_REFRESH_DEFAULT 0x00000000
-
-/***************************************************************************
- *PN_QUEUE0_MAX_PACKET_REFRESH_Port_4 - Port N, Packet-based Queue 0 Shaping Rate Configure Register
- ***************************************************************************/
-/* SWITCH_CORE :: PN_QUEUE0_MAX_PACKET_REFRESH_Port_4 :: SWITCH_RESV [31:18] */
-#define BCHP_SWITCH_CORE_PN_QUEUE0_MAX_PACKET_REFRESH_Port_4_SWITCH_RESV_MASK 0xfffc0000
-#define BCHP_SWITCH_CORE_PN_QUEUE0_MAX_PACKET_REFRESH_Port_4_SWITCH_RESV_SHIFT 18
-#define BCHP_SWITCH_CORE_PN_QUEUE0_MAX_PACKET_REFRESH_Port_4_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: PN_QUEUE0_MAX_PACKET_REFRESH_Port_4 :: MAX_REFRESH [17:00] */
-#define BCHP_SWITCH_CORE_PN_QUEUE0_MAX_PACKET_REFRESH_Port_4_MAX_REFRESH_MASK 0x0003ffff
-#define BCHP_SWITCH_CORE_PN_QUEUE0_MAX_PACKET_REFRESH_Port_4_MAX_REFRESH_SHIFT 0
-#define BCHP_SWITCH_CORE_PN_QUEUE0_MAX_PACKET_REFRESH_Port_4_MAX_REFRESH_DEFAULT 0x00000000
-
-/***************************************************************************
- *PN_QUEUE0_MAX_PACKET_REFRESH_Port_5 - Port N, Packet-based Queue 0 Shaping Rate Configure Register
- ***************************************************************************/
-/* SWITCH_CORE :: PN_QUEUE0_MAX_PACKET_REFRESH_Port_5 :: SWITCH_RESV [31:18] */
-#define BCHP_SWITCH_CORE_PN_QUEUE0_MAX_PACKET_REFRESH_Port_5_SWITCH_RESV_MASK 0xfffc0000
-#define BCHP_SWITCH_CORE_PN_QUEUE0_MAX_PACKET_REFRESH_Port_5_SWITCH_RESV_SHIFT 18
-#define BCHP_SWITCH_CORE_PN_QUEUE0_MAX_PACKET_REFRESH_Port_5_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: PN_QUEUE0_MAX_PACKET_REFRESH_Port_5 :: MAX_REFRESH [17:00] */
-#define BCHP_SWITCH_CORE_PN_QUEUE0_MAX_PACKET_REFRESH_Port_5_MAX_REFRESH_MASK 0x0003ffff
-#define BCHP_SWITCH_CORE_PN_QUEUE0_MAX_PACKET_REFRESH_Port_5_MAX_REFRESH_SHIFT 0
-#define BCHP_SWITCH_CORE_PN_QUEUE0_MAX_PACKET_REFRESH_Port_5_MAX_REFRESH_DEFAULT 0x00000000
-
-/***************************************************************************
- *P7_QUEUE0_MAX_PACKET_REFRESH - Port 7, Packet-based Queue 0 Shaping Rate Configure Register
- ***************************************************************************/
-/* SWITCH_CORE :: P7_QUEUE0_MAX_PACKET_REFRESH :: SWITCH_RESV [31:18] */
-#define BCHP_SWITCH_CORE_P7_QUEUE0_MAX_PACKET_REFRESH_SWITCH_RESV_MASK 0xfffc0000
-#define BCHP_SWITCH_CORE_P7_QUEUE0_MAX_PACKET_REFRESH_SWITCH_RESV_SHIFT 18
-#define BCHP_SWITCH_CORE_P7_QUEUE0_MAX_PACKET_REFRESH_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: P7_QUEUE0_MAX_PACKET_REFRESH :: MAX_REFRESH [17:00] */
-#define BCHP_SWITCH_CORE_P7_QUEUE0_MAX_PACKET_REFRESH_MAX_REFRESH_MASK 0x0003ffff
-#define BCHP_SWITCH_CORE_P7_QUEUE0_MAX_PACKET_REFRESH_MAX_REFRESH_SHIFT 0
-#define BCHP_SWITCH_CORE_P7_QUEUE0_MAX_PACKET_REFRESH_MAX_REFRESH_DEFAULT 0x00000000
-
-/***************************************************************************
- *IMP_QUEUE0_MAX_PACKET_REFRESH - Port 8, Packet-based Queue 0 Shaping Rate Configure Register
- ***************************************************************************/
-/* SWITCH_CORE :: IMP_QUEUE0_MAX_PACKET_REFRESH :: SWITCH_RESV [31:18] */
-#define BCHP_SWITCH_CORE_IMP_QUEUE0_MAX_PACKET_REFRESH_SWITCH_RESV_MASK 0xfffc0000
-#define BCHP_SWITCH_CORE_IMP_QUEUE0_MAX_PACKET_REFRESH_SWITCH_RESV_SHIFT 18
-#define BCHP_SWITCH_CORE_IMP_QUEUE0_MAX_PACKET_REFRESH_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: IMP_QUEUE0_MAX_PACKET_REFRESH :: MAX_REFRESH [17:00] */
-#define BCHP_SWITCH_CORE_IMP_QUEUE0_MAX_PACKET_REFRESH_MAX_REFRESH_MASK 0x0003ffff
-#define BCHP_SWITCH_CORE_IMP_QUEUE0_MAX_PACKET_REFRESH_MAX_REFRESH_SHIFT 0
-#define BCHP_SWITCH_CORE_IMP_QUEUE0_MAX_PACKET_REFRESH_MAX_REFRESH_DEFAULT 0x00000000
-
-/***************************************************************************
- *EGRESS_SHAPER_Q0_CONFIG_REG_SPARE0 - Spare 0 Register (Not2Release)
- ***************************************************************************/
-/* SWITCH_CORE :: EGRESS_SHAPER_Q0_CONFIG_REG_SPARE0 :: EGRESS_SHAPER_Q0_CONFIG_REG_SPARE0 [31:00] */
-#define BCHP_SWITCH_CORE_EGRESS_SHAPER_Q0_CONFIG_REG_SPARE0_EGRESS_SHAPER_Q0_CONFIG_REG_SPARE0_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_EGRESS_SHAPER_Q0_CONFIG_REG_SPARE0_EGRESS_SHAPER_Q0_CONFIG_REG_SPARE0_SHIFT 0
-#define BCHP_SWITCH_CORE_EGRESS_SHAPER_Q0_CONFIG_REG_SPARE0_EGRESS_SHAPER_Q0_CONFIG_REG_SPARE0_DEFAULT 0x00000000
-
-/***************************************************************************
- *EGRESS_SHAPER_Q0_CONFIG_REG_SPARE1 - Spare 1 Register (Not2Release)
- ***************************************************************************/
-/* SWITCH_CORE :: EGRESS_SHAPER_Q0_CONFIG_REG_SPARE1 :: EGRESS_SHAPER_Q0_CONFIG_REG_SPARE1 [31:00] */
-#define BCHP_SWITCH_CORE_EGRESS_SHAPER_Q0_CONFIG_REG_SPARE1_EGRESS_SHAPER_Q0_CONFIG_REG_SPARE1_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_EGRESS_SHAPER_Q0_CONFIG_REG_SPARE1_EGRESS_SHAPER_Q0_CONFIG_REG_SPARE1_SHIFT 0
-#define BCHP_SWITCH_CORE_EGRESS_SHAPER_Q0_CONFIG_REG_SPARE1_EGRESS_SHAPER_Q0_CONFIG_REG_SPARE1_DEFAULT 0x00000000
-
-/***************************************************************************
- *PN_QUEUE0_MAX_PACKET_THD_SEL_Port_0 - Port N, Packet-based Queue 0 Burst Size Configure Register
- ***************************************************************************/
-/* SWITCH_CORE :: PN_QUEUE0_MAX_PACKET_THD_SEL_Port_0 :: SWITCH_RESV [31:18] */
-#define BCHP_SWITCH_CORE_PN_QUEUE0_MAX_PACKET_THD_SEL_Port_0_SWITCH_RESV_MASK 0xfffc0000
-#define BCHP_SWITCH_CORE_PN_QUEUE0_MAX_PACKET_THD_SEL_Port_0_SWITCH_RESV_SHIFT 18
-#define BCHP_SWITCH_CORE_PN_QUEUE0_MAX_PACKET_THD_SEL_Port_0_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: PN_QUEUE0_MAX_PACKET_THD_SEL_Port_0 :: MAX_THD_SEL [17:00] */
-#define BCHP_SWITCH_CORE_PN_QUEUE0_MAX_PACKET_THD_SEL_Port_0_MAX_THD_SEL_MASK 0x0003ffff
-#define BCHP_SWITCH_CORE_PN_QUEUE0_MAX_PACKET_THD_SEL_Port_0_MAX_THD_SEL_SHIFT 0
-#define BCHP_SWITCH_CORE_PN_QUEUE0_MAX_PACKET_THD_SEL_Port_0_MAX_THD_SEL_DEFAULT 0x00000000
-
-/***************************************************************************
- *PN_QUEUE0_MAX_PACKET_THD_SEL_Port_1 - Port N, Packet-based Queue 0 Burst Size Configure Register
- ***************************************************************************/
-/* SWITCH_CORE :: PN_QUEUE0_MAX_PACKET_THD_SEL_Port_1 :: SWITCH_RESV [31:18] */
-#define BCHP_SWITCH_CORE_PN_QUEUE0_MAX_PACKET_THD_SEL_Port_1_SWITCH_RESV_MASK 0xfffc0000
-#define BCHP_SWITCH_CORE_PN_QUEUE0_MAX_PACKET_THD_SEL_Port_1_SWITCH_RESV_SHIFT 18
-#define BCHP_SWITCH_CORE_PN_QUEUE0_MAX_PACKET_THD_SEL_Port_1_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: PN_QUEUE0_MAX_PACKET_THD_SEL_Port_1 :: MAX_THD_SEL [17:00] */
-#define BCHP_SWITCH_CORE_PN_QUEUE0_MAX_PACKET_THD_SEL_Port_1_MAX_THD_SEL_MASK 0x0003ffff
-#define BCHP_SWITCH_CORE_PN_QUEUE0_MAX_PACKET_THD_SEL_Port_1_MAX_THD_SEL_SHIFT 0
-#define BCHP_SWITCH_CORE_PN_QUEUE0_MAX_PACKET_THD_SEL_Port_1_MAX_THD_SEL_DEFAULT 0x00000000
-
-/***************************************************************************
- *PN_QUEUE0_MAX_PACKET_THD_SEL_Port_2 - Port N, Packet-based Queue 0 Burst Size Configure Register
- ***************************************************************************/
-/* SWITCH_CORE :: PN_QUEUE0_MAX_PACKET_THD_SEL_Port_2 :: SWITCH_RESV [31:18] */
-#define BCHP_SWITCH_CORE_PN_QUEUE0_MAX_PACKET_THD_SEL_Port_2_SWITCH_RESV_MASK 0xfffc0000
-#define BCHP_SWITCH_CORE_PN_QUEUE0_MAX_PACKET_THD_SEL_Port_2_SWITCH_RESV_SHIFT 18
-#define BCHP_SWITCH_CORE_PN_QUEUE0_MAX_PACKET_THD_SEL_Port_2_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: PN_QUEUE0_MAX_PACKET_THD_SEL_Port_2 :: MAX_THD_SEL [17:00] */
-#define BCHP_SWITCH_CORE_PN_QUEUE0_MAX_PACKET_THD_SEL_Port_2_MAX_THD_SEL_MASK 0x0003ffff
-#define BCHP_SWITCH_CORE_PN_QUEUE0_MAX_PACKET_THD_SEL_Port_2_MAX_THD_SEL_SHIFT 0
-#define BCHP_SWITCH_CORE_PN_QUEUE0_MAX_PACKET_THD_SEL_Port_2_MAX_THD_SEL_DEFAULT 0x00000000
-
-/***************************************************************************
- *PN_QUEUE0_MAX_PACKET_THD_SEL_Port_3 - Port N, Packet-based Queue 0 Burst Size Configure Register
- ***************************************************************************/
-/* SWITCH_CORE :: PN_QUEUE0_MAX_PACKET_THD_SEL_Port_3 :: SWITCH_RESV [31:18] */
-#define BCHP_SWITCH_CORE_PN_QUEUE0_MAX_PACKET_THD_SEL_Port_3_SWITCH_RESV_MASK 0xfffc0000
-#define BCHP_SWITCH_CORE_PN_QUEUE0_MAX_PACKET_THD_SEL_Port_3_SWITCH_RESV_SHIFT 18
-#define BCHP_SWITCH_CORE_PN_QUEUE0_MAX_PACKET_THD_SEL_Port_3_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: PN_QUEUE0_MAX_PACKET_THD_SEL_Port_3 :: MAX_THD_SEL [17:00] */
-#define BCHP_SWITCH_CORE_PN_QUEUE0_MAX_PACKET_THD_SEL_Port_3_MAX_THD_SEL_MASK 0x0003ffff
-#define BCHP_SWITCH_CORE_PN_QUEUE0_MAX_PACKET_THD_SEL_Port_3_MAX_THD_SEL_SHIFT 0
-#define BCHP_SWITCH_CORE_PN_QUEUE0_MAX_PACKET_THD_SEL_Port_3_MAX_THD_SEL_DEFAULT 0x00000000
-
-/***************************************************************************
- *PN_QUEUE0_MAX_PACKET_THD_SEL_Port_4 - Port N, Packet-based Queue 0 Burst Size Configure Register
- ***************************************************************************/
-/* SWITCH_CORE :: PN_QUEUE0_MAX_PACKET_THD_SEL_Port_4 :: SWITCH_RESV [31:18] */
-#define BCHP_SWITCH_CORE_PN_QUEUE0_MAX_PACKET_THD_SEL_Port_4_SWITCH_RESV_MASK 0xfffc0000
-#define BCHP_SWITCH_CORE_PN_QUEUE0_MAX_PACKET_THD_SEL_Port_4_SWITCH_RESV_SHIFT 18
-#define BCHP_SWITCH_CORE_PN_QUEUE0_MAX_PACKET_THD_SEL_Port_4_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: PN_QUEUE0_MAX_PACKET_THD_SEL_Port_4 :: MAX_THD_SEL [17:00] */
-#define BCHP_SWITCH_CORE_PN_QUEUE0_MAX_PACKET_THD_SEL_Port_4_MAX_THD_SEL_MASK 0x0003ffff
-#define BCHP_SWITCH_CORE_PN_QUEUE0_MAX_PACKET_THD_SEL_Port_4_MAX_THD_SEL_SHIFT 0
-#define BCHP_SWITCH_CORE_PN_QUEUE0_MAX_PACKET_THD_SEL_Port_4_MAX_THD_SEL_DEFAULT 0x00000000
-
-/***************************************************************************
- *PN_QUEUE0_MAX_PACKET_THD_SEL_Port_5 - Port N, Packet-based Queue 0 Burst Size Configure Register
- ***************************************************************************/
-/* SWITCH_CORE :: PN_QUEUE0_MAX_PACKET_THD_SEL_Port_5 :: SWITCH_RESV [31:18] */
-#define BCHP_SWITCH_CORE_PN_QUEUE0_MAX_PACKET_THD_SEL_Port_5_SWITCH_RESV_MASK 0xfffc0000
-#define BCHP_SWITCH_CORE_PN_QUEUE0_MAX_PACKET_THD_SEL_Port_5_SWITCH_RESV_SHIFT 18
-#define BCHP_SWITCH_CORE_PN_QUEUE0_MAX_PACKET_THD_SEL_Port_5_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: PN_QUEUE0_MAX_PACKET_THD_SEL_Port_5 :: MAX_THD_SEL [17:00] */
-#define BCHP_SWITCH_CORE_PN_QUEUE0_MAX_PACKET_THD_SEL_Port_5_MAX_THD_SEL_MASK 0x0003ffff
-#define BCHP_SWITCH_CORE_PN_QUEUE0_MAX_PACKET_THD_SEL_Port_5_MAX_THD_SEL_SHIFT 0
-#define BCHP_SWITCH_CORE_PN_QUEUE0_MAX_PACKET_THD_SEL_Port_5_MAX_THD_SEL_DEFAULT 0x00000000
-
-/***************************************************************************
- *P7_QUEUE0_MAX_PACKET_THD_SEL - Port 7, Packet-based Queue 0 Burst Size Configure Register
- ***************************************************************************/
-/* SWITCH_CORE :: P7_QUEUE0_MAX_PACKET_THD_SEL :: SWITCH_RESV [31:18] */
-#define BCHP_SWITCH_CORE_P7_QUEUE0_MAX_PACKET_THD_SEL_SWITCH_RESV_MASK 0xfffc0000
-#define BCHP_SWITCH_CORE_P7_QUEUE0_MAX_PACKET_THD_SEL_SWITCH_RESV_SHIFT 18
-#define BCHP_SWITCH_CORE_P7_QUEUE0_MAX_PACKET_THD_SEL_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: P7_QUEUE0_MAX_PACKET_THD_SEL :: MAX_THD_SEL [17:00] */
-#define BCHP_SWITCH_CORE_P7_QUEUE0_MAX_PACKET_THD_SEL_MAX_THD_SEL_MASK 0x0003ffff
-#define BCHP_SWITCH_CORE_P7_QUEUE0_MAX_PACKET_THD_SEL_MAX_THD_SEL_SHIFT 0
-#define BCHP_SWITCH_CORE_P7_QUEUE0_MAX_PACKET_THD_SEL_MAX_THD_SEL_DEFAULT 0x00000000
-
-/***************************************************************************
- *IMP_QUEUE0_MAX_PACKET_THD_SEL - Port 8, Packet-based Queue 0 Burst Size Configure Register
- ***************************************************************************/
-/* SWITCH_CORE :: IMP_QUEUE0_MAX_PACKET_THD_SEL :: SWITCH_RESV [31:18] */
-#define BCHP_SWITCH_CORE_IMP_QUEUE0_MAX_PACKET_THD_SEL_SWITCH_RESV_MASK 0xfffc0000
-#define BCHP_SWITCH_CORE_IMP_QUEUE0_MAX_PACKET_THD_SEL_SWITCH_RESV_SHIFT 18
-#define BCHP_SWITCH_CORE_IMP_QUEUE0_MAX_PACKET_THD_SEL_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: IMP_QUEUE0_MAX_PACKET_THD_SEL :: MAX_THD_SEL [17:00] */
-#define BCHP_SWITCH_CORE_IMP_QUEUE0_MAX_PACKET_THD_SEL_MAX_THD_SEL_MASK 0x0003ffff
-#define BCHP_SWITCH_CORE_IMP_QUEUE0_MAX_PACKET_THD_SEL_MAX_THD_SEL_SHIFT 0
-#define BCHP_SWITCH_CORE_IMP_QUEUE0_MAX_PACKET_THD_SEL_MAX_THD_SEL_DEFAULT 0x00000000
-
-/***************************************************************************
- *QUEUE0_AVB_SHAPING_MODE - Queue 0 AVB Shaping Mode Control Register
- ***************************************************************************/
-/* SWITCH_CORE :: QUEUE0_AVB_SHAPING_MODE :: reserved_for_padding0 [31:16] */
-#define BCHP_SWITCH_CORE_QUEUE0_AVB_SHAPING_MODE_reserved_for_padding0_MASK 0xffff0000
-#define BCHP_SWITCH_CORE_QUEUE0_AVB_SHAPING_MODE_reserved_for_padding0_SHIFT 16
-
-/* SWITCH_CORE :: QUEUE0_AVB_SHAPING_MODE :: SWITCH_RESV [15:09] */
-#define BCHP_SWITCH_CORE_QUEUE0_AVB_SHAPING_MODE_SWITCH_RESV_MASK 0x0000fe00
-#define BCHP_SWITCH_CORE_QUEUE0_AVB_SHAPING_MODE_SWITCH_RESV_SHIFT 9
-#define BCHP_SWITCH_CORE_QUEUE0_AVB_SHAPING_MODE_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: QUEUE0_AVB_SHAPING_MODE :: QUEUE0_AVB_SHAPING_MODE [08:00] */
-#define BCHP_SWITCH_CORE_QUEUE0_AVB_SHAPING_MODE_QUEUE0_AVB_SHAPING_MODE_MASK 0x000001ff
-#define BCHP_SWITCH_CORE_QUEUE0_AVB_SHAPING_MODE_QUEUE0_AVB_SHAPING_MODE_SHIFT 0
-#define BCHP_SWITCH_CORE_QUEUE0_AVB_SHAPING_MODE_QUEUE0_AVB_SHAPING_MODE_DEFAULT 0x00000000
-
-/***************************************************************************
- *QUEUE0_SHAPER_ENABLE - Queue 0 Shaper Enable Register
- ***************************************************************************/
-/* SWITCH_CORE :: QUEUE0_SHAPER_ENABLE :: reserved_for_padding0 [31:16] */
-#define BCHP_SWITCH_CORE_QUEUE0_SHAPER_ENABLE_reserved_for_padding0_MASK 0xffff0000
-#define BCHP_SWITCH_CORE_QUEUE0_SHAPER_ENABLE_reserved_for_padding0_SHIFT 16
-
-/* SWITCH_CORE :: QUEUE0_SHAPER_ENABLE :: SWITCH_RESV [15:09] */
-#define BCHP_SWITCH_CORE_QUEUE0_SHAPER_ENABLE_SWITCH_RESV_MASK 0x0000fe00
-#define BCHP_SWITCH_CORE_QUEUE0_SHAPER_ENABLE_SWITCH_RESV_SHIFT 9
-#define BCHP_SWITCH_CORE_QUEUE0_SHAPER_ENABLE_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: QUEUE0_SHAPER_ENABLE :: QUEUE0_SHAPER_ENABLE [08:00] */
-#define BCHP_SWITCH_CORE_QUEUE0_SHAPER_ENABLE_QUEUE0_SHAPER_ENABLE_MASK 0x000001ff
-#define BCHP_SWITCH_CORE_QUEUE0_SHAPER_ENABLE_QUEUE0_SHAPER_ENABLE_SHIFT 0
-#define BCHP_SWITCH_CORE_QUEUE0_SHAPER_ENABLE_QUEUE0_SHAPER_ENABLE_DEFAULT 0x00000000
-
-/***************************************************************************
- *QUEUE0_SHAPER_BUCKET_COUNT_SELECT - Queue 0 Bucket Count Select Register
- ***************************************************************************/
-/* SWITCH_CORE :: QUEUE0_SHAPER_BUCKET_COUNT_SELECT :: reserved_for_padding0 [31:16] */
-#define BCHP_SWITCH_CORE_QUEUE0_SHAPER_BUCKET_COUNT_SELECT_reserved_for_padding0_MASK 0xffff0000
-#define BCHP_SWITCH_CORE_QUEUE0_SHAPER_BUCKET_COUNT_SELECT_reserved_for_padding0_SHIFT 16
-
-/* SWITCH_CORE :: QUEUE0_SHAPER_BUCKET_COUNT_SELECT :: SWITCH_RESV [15:09] */
-#define BCHP_SWITCH_CORE_QUEUE0_SHAPER_BUCKET_COUNT_SELECT_SWITCH_RESV_MASK 0x0000fe00
-#define BCHP_SWITCH_CORE_QUEUE0_SHAPER_BUCKET_COUNT_SELECT_SWITCH_RESV_SHIFT 9
-#define BCHP_SWITCH_CORE_QUEUE0_SHAPER_BUCKET_COUNT_SELECT_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: QUEUE0_SHAPER_BUCKET_COUNT_SELECT :: QUEUE0_SHAPER_BUCKET_COUNT_SELECT [08:00] */
-#define BCHP_SWITCH_CORE_QUEUE0_SHAPER_BUCKET_COUNT_SELECT_QUEUE0_SHAPER_BUCKET_COUNT_SELECT_MASK 0x000001ff
-#define BCHP_SWITCH_CORE_QUEUE0_SHAPER_BUCKET_COUNT_SELECT_QUEUE0_SHAPER_BUCKET_COUNT_SELECT_SHIFT 0
-#define BCHP_SWITCH_CORE_QUEUE0_SHAPER_BUCKET_COUNT_SELECT_QUEUE0_SHAPER_BUCKET_COUNT_SELECT_DEFAULT 0x00000000
-
-/***************************************************************************
- *QUEUE0_SHAPER_BLOCKING - Queue 0 Shaper Blocking Control Register
- ***************************************************************************/
-/* SWITCH_CORE :: QUEUE0_SHAPER_BLOCKING :: reserved_for_padding0 [31:16] */
-#define BCHP_SWITCH_CORE_QUEUE0_SHAPER_BLOCKING_reserved_for_padding0_MASK 0xffff0000
-#define BCHP_SWITCH_CORE_QUEUE0_SHAPER_BLOCKING_reserved_for_padding0_SHIFT 16
-
-/* SWITCH_CORE :: QUEUE0_SHAPER_BLOCKING :: SWITCH_RESV [15:09] */
-#define BCHP_SWITCH_CORE_QUEUE0_SHAPER_BLOCKING_SWITCH_RESV_MASK 0x0000fe00
-#define BCHP_SWITCH_CORE_QUEUE0_SHAPER_BLOCKING_SWITCH_RESV_SHIFT 9
-#define BCHP_SWITCH_CORE_QUEUE0_SHAPER_BLOCKING_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: QUEUE0_SHAPER_BLOCKING :: QUEUE0_SHAPER_BLOCKING [08:00] */
-#define BCHP_SWITCH_CORE_QUEUE0_SHAPER_BLOCKING_QUEUE0_SHAPER_BLOCKING_MASK 0x000001ff
-#define BCHP_SWITCH_CORE_QUEUE0_SHAPER_BLOCKING_QUEUE0_SHAPER_BLOCKING_SHIFT 0
-#define BCHP_SWITCH_CORE_QUEUE0_SHAPER_BLOCKING_QUEUE0_SHAPER_BLOCKING_DEFAULT 0x00000000
-
-/***************************************************************************
- *PN_QUEUE1_MAX_REFRESH_Port_0 - Port N, Byte-based Queue 1 Shaping Rate Configure Register
- ***************************************************************************/
-/* SWITCH_CORE :: PN_QUEUE1_MAX_REFRESH_Port_0 :: SWITCH_RESV [31:18] */
-#define BCHP_SWITCH_CORE_PN_QUEUE1_MAX_REFRESH_Port_0_SWITCH_RESV_MASK 0xfffc0000
-#define BCHP_SWITCH_CORE_PN_QUEUE1_MAX_REFRESH_Port_0_SWITCH_RESV_SHIFT 18
-#define BCHP_SWITCH_CORE_PN_QUEUE1_MAX_REFRESH_Port_0_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: PN_QUEUE1_MAX_REFRESH_Port_0 :: MAX_REFRESH [17:00] */
-#define BCHP_SWITCH_CORE_PN_QUEUE1_MAX_REFRESH_Port_0_MAX_REFRESH_MASK 0x0003ffff
-#define BCHP_SWITCH_CORE_PN_QUEUE1_MAX_REFRESH_Port_0_MAX_REFRESH_SHIFT 0
-#define BCHP_SWITCH_CORE_PN_QUEUE1_MAX_REFRESH_Port_0_MAX_REFRESH_DEFAULT 0x00000000
-
-/***************************************************************************
- *PN_QUEUE1_MAX_REFRESH_Port_1 - Port N, Byte-based Queue 1 Shaping Rate Configure Register
- ***************************************************************************/
-/* SWITCH_CORE :: PN_QUEUE1_MAX_REFRESH_Port_1 :: SWITCH_RESV [31:18] */
-#define BCHP_SWITCH_CORE_PN_QUEUE1_MAX_REFRESH_Port_1_SWITCH_RESV_MASK 0xfffc0000
-#define BCHP_SWITCH_CORE_PN_QUEUE1_MAX_REFRESH_Port_1_SWITCH_RESV_SHIFT 18
-#define BCHP_SWITCH_CORE_PN_QUEUE1_MAX_REFRESH_Port_1_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: PN_QUEUE1_MAX_REFRESH_Port_1 :: MAX_REFRESH [17:00] */
-#define BCHP_SWITCH_CORE_PN_QUEUE1_MAX_REFRESH_Port_1_MAX_REFRESH_MASK 0x0003ffff
-#define BCHP_SWITCH_CORE_PN_QUEUE1_MAX_REFRESH_Port_1_MAX_REFRESH_SHIFT 0
-#define BCHP_SWITCH_CORE_PN_QUEUE1_MAX_REFRESH_Port_1_MAX_REFRESH_DEFAULT 0x00000000
-
-/***************************************************************************
- *PN_QUEUE1_MAX_REFRESH_Port_2 - Port N, Byte-based Queue 1 Shaping Rate Configure Register
- ***************************************************************************/
-/* SWITCH_CORE :: PN_QUEUE1_MAX_REFRESH_Port_2 :: SWITCH_RESV [31:18] */
-#define BCHP_SWITCH_CORE_PN_QUEUE1_MAX_REFRESH_Port_2_SWITCH_RESV_MASK 0xfffc0000
-#define BCHP_SWITCH_CORE_PN_QUEUE1_MAX_REFRESH_Port_2_SWITCH_RESV_SHIFT 18
-#define BCHP_SWITCH_CORE_PN_QUEUE1_MAX_REFRESH_Port_2_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: PN_QUEUE1_MAX_REFRESH_Port_2 :: MAX_REFRESH [17:00] */
-#define BCHP_SWITCH_CORE_PN_QUEUE1_MAX_REFRESH_Port_2_MAX_REFRESH_MASK 0x0003ffff
-#define BCHP_SWITCH_CORE_PN_QUEUE1_MAX_REFRESH_Port_2_MAX_REFRESH_SHIFT 0
-#define BCHP_SWITCH_CORE_PN_QUEUE1_MAX_REFRESH_Port_2_MAX_REFRESH_DEFAULT 0x00000000
-
-/***************************************************************************
- *PN_QUEUE1_MAX_REFRESH_Port_3 - Port N, Byte-based Queue 1 Shaping Rate Configure Register
- ***************************************************************************/
-/* SWITCH_CORE :: PN_QUEUE1_MAX_REFRESH_Port_3 :: SWITCH_RESV [31:18] */
-#define BCHP_SWITCH_CORE_PN_QUEUE1_MAX_REFRESH_Port_3_SWITCH_RESV_MASK 0xfffc0000
-#define BCHP_SWITCH_CORE_PN_QUEUE1_MAX_REFRESH_Port_3_SWITCH_RESV_SHIFT 18
-#define BCHP_SWITCH_CORE_PN_QUEUE1_MAX_REFRESH_Port_3_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: PN_QUEUE1_MAX_REFRESH_Port_3 :: MAX_REFRESH [17:00] */
-#define BCHP_SWITCH_CORE_PN_QUEUE1_MAX_REFRESH_Port_3_MAX_REFRESH_MASK 0x0003ffff
-#define BCHP_SWITCH_CORE_PN_QUEUE1_MAX_REFRESH_Port_3_MAX_REFRESH_SHIFT 0
-#define BCHP_SWITCH_CORE_PN_QUEUE1_MAX_REFRESH_Port_3_MAX_REFRESH_DEFAULT 0x00000000
-
-/***************************************************************************
- *PN_QUEUE1_MAX_REFRESH_Port_4 - Port N, Byte-based Queue 1 Shaping Rate Configure Register
- ***************************************************************************/
-/* SWITCH_CORE :: PN_QUEUE1_MAX_REFRESH_Port_4 :: SWITCH_RESV [31:18] */
-#define BCHP_SWITCH_CORE_PN_QUEUE1_MAX_REFRESH_Port_4_SWITCH_RESV_MASK 0xfffc0000
-#define BCHP_SWITCH_CORE_PN_QUEUE1_MAX_REFRESH_Port_4_SWITCH_RESV_SHIFT 18
-#define BCHP_SWITCH_CORE_PN_QUEUE1_MAX_REFRESH_Port_4_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: PN_QUEUE1_MAX_REFRESH_Port_4 :: MAX_REFRESH [17:00] */
-#define BCHP_SWITCH_CORE_PN_QUEUE1_MAX_REFRESH_Port_4_MAX_REFRESH_MASK 0x0003ffff
-#define BCHP_SWITCH_CORE_PN_QUEUE1_MAX_REFRESH_Port_4_MAX_REFRESH_SHIFT 0
-#define BCHP_SWITCH_CORE_PN_QUEUE1_MAX_REFRESH_Port_4_MAX_REFRESH_DEFAULT 0x00000000
-
-/***************************************************************************
- *PN_QUEUE1_MAX_REFRESH_Port_5 - Port N, Byte-based Queue 1 Shaping Rate Configure Register
- ***************************************************************************/
-/* SWITCH_CORE :: PN_QUEUE1_MAX_REFRESH_Port_5 :: SWITCH_RESV [31:18] */
-#define BCHP_SWITCH_CORE_PN_QUEUE1_MAX_REFRESH_Port_5_SWITCH_RESV_MASK 0xfffc0000
-#define BCHP_SWITCH_CORE_PN_QUEUE1_MAX_REFRESH_Port_5_SWITCH_RESV_SHIFT 18
-#define BCHP_SWITCH_CORE_PN_QUEUE1_MAX_REFRESH_Port_5_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: PN_QUEUE1_MAX_REFRESH_Port_5 :: MAX_REFRESH [17:00] */
-#define BCHP_SWITCH_CORE_PN_QUEUE1_MAX_REFRESH_Port_5_MAX_REFRESH_MASK 0x0003ffff
-#define BCHP_SWITCH_CORE_PN_QUEUE1_MAX_REFRESH_Port_5_MAX_REFRESH_SHIFT 0
-#define BCHP_SWITCH_CORE_PN_QUEUE1_MAX_REFRESH_Port_5_MAX_REFRESH_DEFAULT 0x00000000
-
-/***************************************************************************
- *P7_QUEUE1_MAX_REFRESH - Port 7, Byte-based Queue 1 Shaping Rate Configure Register
- ***************************************************************************/
-/* SWITCH_CORE :: P7_QUEUE1_MAX_REFRESH :: SWITCH_RESV [31:18] */
-#define BCHP_SWITCH_CORE_P7_QUEUE1_MAX_REFRESH_SWITCH_RESV_MASK 0xfffc0000
-#define BCHP_SWITCH_CORE_P7_QUEUE1_MAX_REFRESH_SWITCH_RESV_SHIFT 18
-#define BCHP_SWITCH_CORE_P7_QUEUE1_MAX_REFRESH_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: P7_QUEUE1_MAX_REFRESH :: MAX_REFRESH [17:00] */
-#define BCHP_SWITCH_CORE_P7_QUEUE1_MAX_REFRESH_MAX_REFRESH_MASK 0x0003ffff
-#define BCHP_SWITCH_CORE_P7_QUEUE1_MAX_REFRESH_MAX_REFRESH_SHIFT 0
-#define BCHP_SWITCH_CORE_P7_QUEUE1_MAX_REFRESH_MAX_REFRESH_DEFAULT 0x00000000
-
-/***************************************************************************
- *IMP_QUEUE1_MAX_REFRESH - Port 8, Byte-based Queue 1 Shaping Rate Configure Register
- ***************************************************************************/
-/* SWITCH_CORE :: IMP_QUEUE1_MAX_REFRESH :: SWITCH_RESV [31:18] */
-#define BCHP_SWITCH_CORE_IMP_QUEUE1_MAX_REFRESH_SWITCH_RESV_MASK 0xfffc0000
-#define BCHP_SWITCH_CORE_IMP_QUEUE1_MAX_REFRESH_SWITCH_RESV_SHIFT 18
-#define BCHP_SWITCH_CORE_IMP_QUEUE1_MAX_REFRESH_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: IMP_QUEUE1_MAX_REFRESH :: MAX_REFRESH [17:00] */
-#define BCHP_SWITCH_CORE_IMP_QUEUE1_MAX_REFRESH_MAX_REFRESH_MASK 0x0003ffff
-#define BCHP_SWITCH_CORE_IMP_QUEUE1_MAX_REFRESH_MAX_REFRESH_SHIFT 0
-#define BCHP_SWITCH_CORE_IMP_QUEUE1_MAX_REFRESH_MAX_REFRESH_DEFAULT 0x00000000
-
-/***************************************************************************
- *PN_QUEUE1_MAX_THD_SEL_Port_0 - Port N, Byte-based Queue 1 Burst Size Configure Register
- ***************************************************************************/
-/* SWITCH_CORE :: PN_QUEUE1_MAX_THD_SEL_Port_0 :: SWITCH_RESV [31:18] */
-#define BCHP_SWITCH_CORE_PN_QUEUE1_MAX_THD_SEL_Port_0_SWITCH_RESV_MASK 0xfffc0000
-#define BCHP_SWITCH_CORE_PN_QUEUE1_MAX_THD_SEL_Port_0_SWITCH_RESV_SHIFT 18
-#define BCHP_SWITCH_CORE_PN_QUEUE1_MAX_THD_SEL_Port_0_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: PN_QUEUE1_MAX_THD_SEL_Port_0 :: MAX_THD_SEL [17:00] */
-#define BCHP_SWITCH_CORE_PN_QUEUE1_MAX_THD_SEL_Port_0_MAX_THD_SEL_MASK 0x0003ffff
-#define BCHP_SWITCH_CORE_PN_QUEUE1_MAX_THD_SEL_Port_0_MAX_THD_SEL_SHIFT 0
-#define BCHP_SWITCH_CORE_PN_QUEUE1_MAX_THD_SEL_Port_0_MAX_THD_SEL_DEFAULT 0x00000000
-
-/***************************************************************************
- *PN_QUEUE1_MAX_THD_SEL_Port_1 - Port N, Byte-based Queue 1 Burst Size Configure Register
- ***************************************************************************/
-/* SWITCH_CORE :: PN_QUEUE1_MAX_THD_SEL_Port_1 :: SWITCH_RESV [31:18] */
-#define BCHP_SWITCH_CORE_PN_QUEUE1_MAX_THD_SEL_Port_1_SWITCH_RESV_MASK 0xfffc0000
-#define BCHP_SWITCH_CORE_PN_QUEUE1_MAX_THD_SEL_Port_1_SWITCH_RESV_SHIFT 18
-#define BCHP_SWITCH_CORE_PN_QUEUE1_MAX_THD_SEL_Port_1_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: PN_QUEUE1_MAX_THD_SEL_Port_1 :: MAX_THD_SEL [17:00] */
-#define BCHP_SWITCH_CORE_PN_QUEUE1_MAX_THD_SEL_Port_1_MAX_THD_SEL_MASK 0x0003ffff
-#define BCHP_SWITCH_CORE_PN_QUEUE1_MAX_THD_SEL_Port_1_MAX_THD_SEL_SHIFT 0
-#define BCHP_SWITCH_CORE_PN_QUEUE1_MAX_THD_SEL_Port_1_MAX_THD_SEL_DEFAULT 0x00000000
-
-/***************************************************************************
- *PN_QUEUE1_MAX_THD_SEL_Port_2 - Port N, Byte-based Queue 1 Burst Size Configure Register
- ***************************************************************************/
-/* SWITCH_CORE :: PN_QUEUE1_MAX_THD_SEL_Port_2 :: SWITCH_RESV [31:18] */
-#define BCHP_SWITCH_CORE_PN_QUEUE1_MAX_THD_SEL_Port_2_SWITCH_RESV_MASK 0xfffc0000
-#define BCHP_SWITCH_CORE_PN_QUEUE1_MAX_THD_SEL_Port_2_SWITCH_RESV_SHIFT 18
-#define BCHP_SWITCH_CORE_PN_QUEUE1_MAX_THD_SEL_Port_2_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: PN_QUEUE1_MAX_THD_SEL_Port_2 :: MAX_THD_SEL [17:00] */
-#define BCHP_SWITCH_CORE_PN_QUEUE1_MAX_THD_SEL_Port_2_MAX_THD_SEL_MASK 0x0003ffff
-#define BCHP_SWITCH_CORE_PN_QUEUE1_MAX_THD_SEL_Port_2_MAX_THD_SEL_SHIFT 0
-#define BCHP_SWITCH_CORE_PN_QUEUE1_MAX_THD_SEL_Port_2_MAX_THD_SEL_DEFAULT 0x00000000
-
-/***************************************************************************
- *PN_QUEUE1_MAX_THD_SEL_Port_3 - Port N, Byte-based Queue 1 Burst Size Configure Register
- ***************************************************************************/
-/* SWITCH_CORE :: PN_QUEUE1_MAX_THD_SEL_Port_3 :: SWITCH_RESV [31:18] */
-#define BCHP_SWITCH_CORE_PN_QUEUE1_MAX_THD_SEL_Port_3_SWITCH_RESV_MASK 0xfffc0000
-#define BCHP_SWITCH_CORE_PN_QUEUE1_MAX_THD_SEL_Port_3_SWITCH_RESV_SHIFT 18
-#define BCHP_SWITCH_CORE_PN_QUEUE1_MAX_THD_SEL_Port_3_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: PN_QUEUE1_MAX_THD_SEL_Port_3 :: MAX_THD_SEL [17:00] */
-#define BCHP_SWITCH_CORE_PN_QUEUE1_MAX_THD_SEL_Port_3_MAX_THD_SEL_MASK 0x0003ffff
-#define BCHP_SWITCH_CORE_PN_QUEUE1_MAX_THD_SEL_Port_3_MAX_THD_SEL_SHIFT 0
-#define BCHP_SWITCH_CORE_PN_QUEUE1_MAX_THD_SEL_Port_3_MAX_THD_SEL_DEFAULT 0x00000000
-
-/***************************************************************************
- *PN_QUEUE1_MAX_THD_SEL_Port_4 - Port N, Byte-based Queue 1 Burst Size Configure Register
- ***************************************************************************/
-/* SWITCH_CORE :: PN_QUEUE1_MAX_THD_SEL_Port_4 :: SWITCH_RESV [31:18] */
-#define BCHP_SWITCH_CORE_PN_QUEUE1_MAX_THD_SEL_Port_4_SWITCH_RESV_MASK 0xfffc0000
-#define BCHP_SWITCH_CORE_PN_QUEUE1_MAX_THD_SEL_Port_4_SWITCH_RESV_SHIFT 18
-#define BCHP_SWITCH_CORE_PN_QUEUE1_MAX_THD_SEL_Port_4_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: PN_QUEUE1_MAX_THD_SEL_Port_4 :: MAX_THD_SEL [17:00] */
-#define BCHP_SWITCH_CORE_PN_QUEUE1_MAX_THD_SEL_Port_4_MAX_THD_SEL_MASK 0x0003ffff
-#define BCHP_SWITCH_CORE_PN_QUEUE1_MAX_THD_SEL_Port_4_MAX_THD_SEL_SHIFT 0
-#define BCHP_SWITCH_CORE_PN_QUEUE1_MAX_THD_SEL_Port_4_MAX_THD_SEL_DEFAULT 0x00000000
-
-/***************************************************************************
- *PN_QUEUE1_MAX_THD_SEL_Port_5 - Port N, Byte-based Queue 1 Burst Size Configure Register
- ***************************************************************************/
-/* SWITCH_CORE :: PN_QUEUE1_MAX_THD_SEL_Port_5 :: SWITCH_RESV [31:18] */
-#define BCHP_SWITCH_CORE_PN_QUEUE1_MAX_THD_SEL_Port_5_SWITCH_RESV_MASK 0xfffc0000
-#define BCHP_SWITCH_CORE_PN_QUEUE1_MAX_THD_SEL_Port_5_SWITCH_RESV_SHIFT 18
-#define BCHP_SWITCH_CORE_PN_QUEUE1_MAX_THD_SEL_Port_5_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: PN_QUEUE1_MAX_THD_SEL_Port_5 :: MAX_THD_SEL [17:00] */
-#define BCHP_SWITCH_CORE_PN_QUEUE1_MAX_THD_SEL_Port_5_MAX_THD_SEL_MASK 0x0003ffff
-#define BCHP_SWITCH_CORE_PN_QUEUE1_MAX_THD_SEL_Port_5_MAX_THD_SEL_SHIFT 0
-#define BCHP_SWITCH_CORE_PN_QUEUE1_MAX_THD_SEL_Port_5_MAX_THD_SEL_DEFAULT 0x00000000
-
-/***************************************************************************
- *P7_QUEUE1_MAX_THD_SEL - Port 7, Byte-based Queue 1 Burst Size Configure Register
- ***************************************************************************/
-/* SWITCH_CORE :: P7_QUEUE1_MAX_THD_SEL :: SWITCH_RESV [31:18] */
-#define BCHP_SWITCH_CORE_P7_QUEUE1_MAX_THD_SEL_SWITCH_RESV_MASK 0xfffc0000
-#define BCHP_SWITCH_CORE_P7_QUEUE1_MAX_THD_SEL_SWITCH_RESV_SHIFT 18
-#define BCHP_SWITCH_CORE_P7_QUEUE1_MAX_THD_SEL_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: P7_QUEUE1_MAX_THD_SEL :: MAX_THD_SEL [17:00] */
-#define BCHP_SWITCH_CORE_P7_QUEUE1_MAX_THD_SEL_MAX_THD_SEL_MASK 0x0003ffff
-#define BCHP_SWITCH_CORE_P7_QUEUE1_MAX_THD_SEL_MAX_THD_SEL_SHIFT 0
-#define BCHP_SWITCH_CORE_P7_QUEUE1_MAX_THD_SEL_MAX_THD_SEL_DEFAULT 0x00000000
-
-/***************************************************************************
- *IMP_QUEUE1_MAX_THD_SEL - Port 8, Byte-based Queue 1 Burst Size Configure Register
- ***************************************************************************/
-/* SWITCH_CORE :: IMP_QUEUE1_MAX_THD_SEL :: SWITCH_RESV [31:18] */
-#define BCHP_SWITCH_CORE_IMP_QUEUE1_MAX_THD_SEL_SWITCH_RESV_MASK 0xfffc0000
-#define BCHP_SWITCH_CORE_IMP_QUEUE1_MAX_THD_SEL_SWITCH_RESV_SHIFT 18
-#define BCHP_SWITCH_CORE_IMP_QUEUE1_MAX_THD_SEL_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: IMP_QUEUE1_MAX_THD_SEL :: MAX_THD_SEL [17:00] */
-#define BCHP_SWITCH_CORE_IMP_QUEUE1_MAX_THD_SEL_MAX_THD_SEL_MASK 0x0003ffff
-#define BCHP_SWITCH_CORE_IMP_QUEUE1_MAX_THD_SEL_MAX_THD_SEL_SHIFT 0
-#define BCHP_SWITCH_CORE_IMP_QUEUE1_MAX_THD_SEL_MAX_THD_SEL_DEFAULT 0x00000000
-
-/***************************************************************************
- *PN_QUEUE1_SHAPER_STS_Port_0 - Port N, Queue 1 Shaper Status Register
- ***************************************************************************/
-/* SWITCH_CORE :: PN_QUEUE1_SHAPER_STS_Port_0 :: IN_PROFILE_FLAG [31:31] */
-#define BCHP_SWITCH_CORE_PN_QUEUE1_SHAPER_STS_Port_0_IN_PROFILE_FLAG_MASK 0x80000000
-#define BCHP_SWITCH_CORE_PN_QUEUE1_SHAPER_STS_Port_0_IN_PROFILE_FLAG_SHIFT 31
-#define BCHP_SWITCH_CORE_PN_QUEUE1_SHAPER_STS_Port_0_IN_PROFILE_FLAG_DEFAULT 0x00000001
-
-/* SWITCH_CORE :: PN_QUEUE1_SHAPER_STS_Port_0 :: SWITCH_RESV [30:29] */
-#define BCHP_SWITCH_CORE_PN_QUEUE1_SHAPER_STS_Port_0_SWITCH_RESV_MASK 0x60000000
-#define BCHP_SWITCH_CORE_PN_QUEUE1_SHAPER_STS_Port_0_SWITCH_RESV_SHIFT 29
-#define BCHP_SWITCH_CORE_PN_QUEUE1_SHAPER_STS_Port_0_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: PN_QUEUE1_SHAPER_STS_Port_0 :: BUCKET_CNT [28:00] */
-#define BCHP_SWITCH_CORE_PN_QUEUE1_SHAPER_STS_Port_0_BUCKET_CNT_MASK 0x1fffffff
-#define BCHP_SWITCH_CORE_PN_QUEUE1_SHAPER_STS_Port_0_BUCKET_CNT_SHIFT 0
-#define BCHP_SWITCH_CORE_PN_QUEUE1_SHAPER_STS_Port_0_BUCKET_CNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *PN_QUEUE1_SHAPER_STS_Port_1 - Port N, Queue 1 Shaper Status Register
- ***************************************************************************/
-/* SWITCH_CORE :: PN_QUEUE1_SHAPER_STS_Port_1 :: IN_PROFILE_FLAG [31:31] */
-#define BCHP_SWITCH_CORE_PN_QUEUE1_SHAPER_STS_Port_1_IN_PROFILE_FLAG_MASK 0x80000000
-#define BCHP_SWITCH_CORE_PN_QUEUE1_SHAPER_STS_Port_1_IN_PROFILE_FLAG_SHIFT 31
-#define BCHP_SWITCH_CORE_PN_QUEUE1_SHAPER_STS_Port_1_IN_PROFILE_FLAG_DEFAULT 0x00000001
-
-/* SWITCH_CORE :: PN_QUEUE1_SHAPER_STS_Port_1 :: SWITCH_RESV [30:29] */
-#define BCHP_SWITCH_CORE_PN_QUEUE1_SHAPER_STS_Port_1_SWITCH_RESV_MASK 0x60000000
-#define BCHP_SWITCH_CORE_PN_QUEUE1_SHAPER_STS_Port_1_SWITCH_RESV_SHIFT 29
-#define BCHP_SWITCH_CORE_PN_QUEUE1_SHAPER_STS_Port_1_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: PN_QUEUE1_SHAPER_STS_Port_1 :: BUCKET_CNT [28:00] */
-#define BCHP_SWITCH_CORE_PN_QUEUE1_SHAPER_STS_Port_1_BUCKET_CNT_MASK 0x1fffffff
-#define BCHP_SWITCH_CORE_PN_QUEUE1_SHAPER_STS_Port_1_BUCKET_CNT_SHIFT 0
-#define BCHP_SWITCH_CORE_PN_QUEUE1_SHAPER_STS_Port_1_BUCKET_CNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *PN_QUEUE1_SHAPER_STS_Port_2 - Port N, Queue 1 Shaper Status Register
- ***************************************************************************/
-/* SWITCH_CORE :: PN_QUEUE1_SHAPER_STS_Port_2 :: IN_PROFILE_FLAG [31:31] */
-#define BCHP_SWITCH_CORE_PN_QUEUE1_SHAPER_STS_Port_2_IN_PROFILE_FLAG_MASK 0x80000000
-#define BCHP_SWITCH_CORE_PN_QUEUE1_SHAPER_STS_Port_2_IN_PROFILE_FLAG_SHIFT 31
-#define BCHP_SWITCH_CORE_PN_QUEUE1_SHAPER_STS_Port_2_IN_PROFILE_FLAG_DEFAULT 0x00000001
-
-/* SWITCH_CORE :: PN_QUEUE1_SHAPER_STS_Port_2 :: SWITCH_RESV [30:29] */
-#define BCHP_SWITCH_CORE_PN_QUEUE1_SHAPER_STS_Port_2_SWITCH_RESV_MASK 0x60000000
-#define BCHP_SWITCH_CORE_PN_QUEUE1_SHAPER_STS_Port_2_SWITCH_RESV_SHIFT 29
-#define BCHP_SWITCH_CORE_PN_QUEUE1_SHAPER_STS_Port_2_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: PN_QUEUE1_SHAPER_STS_Port_2 :: BUCKET_CNT [28:00] */
-#define BCHP_SWITCH_CORE_PN_QUEUE1_SHAPER_STS_Port_2_BUCKET_CNT_MASK 0x1fffffff
-#define BCHP_SWITCH_CORE_PN_QUEUE1_SHAPER_STS_Port_2_BUCKET_CNT_SHIFT 0
-#define BCHP_SWITCH_CORE_PN_QUEUE1_SHAPER_STS_Port_2_BUCKET_CNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *PN_QUEUE1_SHAPER_STS_Port_3 - Port N, Queue 1 Shaper Status Register
- ***************************************************************************/
-/* SWITCH_CORE :: PN_QUEUE1_SHAPER_STS_Port_3 :: IN_PROFILE_FLAG [31:31] */
-#define BCHP_SWITCH_CORE_PN_QUEUE1_SHAPER_STS_Port_3_IN_PROFILE_FLAG_MASK 0x80000000
-#define BCHP_SWITCH_CORE_PN_QUEUE1_SHAPER_STS_Port_3_IN_PROFILE_FLAG_SHIFT 31
-#define BCHP_SWITCH_CORE_PN_QUEUE1_SHAPER_STS_Port_3_IN_PROFILE_FLAG_DEFAULT 0x00000001
-
-/* SWITCH_CORE :: PN_QUEUE1_SHAPER_STS_Port_3 :: SWITCH_RESV [30:29] */
-#define BCHP_SWITCH_CORE_PN_QUEUE1_SHAPER_STS_Port_3_SWITCH_RESV_MASK 0x60000000
-#define BCHP_SWITCH_CORE_PN_QUEUE1_SHAPER_STS_Port_3_SWITCH_RESV_SHIFT 29
-#define BCHP_SWITCH_CORE_PN_QUEUE1_SHAPER_STS_Port_3_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: PN_QUEUE1_SHAPER_STS_Port_3 :: BUCKET_CNT [28:00] */
-#define BCHP_SWITCH_CORE_PN_QUEUE1_SHAPER_STS_Port_3_BUCKET_CNT_MASK 0x1fffffff
-#define BCHP_SWITCH_CORE_PN_QUEUE1_SHAPER_STS_Port_3_BUCKET_CNT_SHIFT 0
-#define BCHP_SWITCH_CORE_PN_QUEUE1_SHAPER_STS_Port_3_BUCKET_CNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *PN_QUEUE1_SHAPER_STS_Port_4 - Port N, Queue 1 Shaper Status Register
- ***************************************************************************/
-/* SWITCH_CORE :: PN_QUEUE1_SHAPER_STS_Port_4 :: IN_PROFILE_FLAG [31:31] */
-#define BCHP_SWITCH_CORE_PN_QUEUE1_SHAPER_STS_Port_4_IN_PROFILE_FLAG_MASK 0x80000000
-#define BCHP_SWITCH_CORE_PN_QUEUE1_SHAPER_STS_Port_4_IN_PROFILE_FLAG_SHIFT 31
-#define BCHP_SWITCH_CORE_PN_QUEUE1_SHAPER_STS_Port_4_IN_PROFILE_FLAG_DEFAULT 0x00000001
-
-/* SWITCH_CORE :: PN_QUEUE1_SHAPER_STS_Port_4 :: SWITCH_RESV [30:29] */
-#define BCHP_SWITCH_CORE_PN_QUEUE1_SHAPER_STS_Port_4_SWITCH_RESV_MASK 0x60000000
-#define BCHP_SWITCH_CORE_PN_QUEUE1_SHAPER_STS_Port_4_SWITCH_RESV_SHIFT 29
-#define BCHP_SWITCH_CORE_PN_QUEUE1_SHAPER_STS_Port_4_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: PN_QUEUE1_SHAPER_STS_Port_4 :: BUCKET_CNT [28:00] */
-#define BCHP_SWITCH_CORE_PN_QUEUE1_SHAPER_STS_Port_4_BUCKET_CNT_MASK 0x1fffffff
-#define BCHP_SWITCH_CORE_PN_QUEUE1_SHAPER_STS_Port_4_BUCKET_CNT_SHIFT 0
-#define BCHP_SWITCH_CORE_PN_QUEUE1_SHAPER_STS_Port_4_BUCKET_CNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *PN_QUEUE1_SHAPER_STS_Port_5 - Port N, Queue 1 Shaper Status Register
- ***************************************************************************/
-/* SWITCH_CORE :: PN_QUEUE1_SHAPER_STS_Port_5 :: IN_PROFILE_FLAG [31:31] */
-#define BCHP_SWITCH_CORE_PN_QUEUE1_SHAPER_STS_Port_5_IN_PROFILE_FLAG_MASK 0x80000000
-#define BCHP_SWITCH_CORE_PN_QUEUE1_SHAPER_STS_Port_5_IN_PROFILE_FLAG_SHIFT 31
-#define BCHP_SWITCH_CORE_PN_QUEUE1_SHAPER_STS_Port_5_IN_PROFILE_FLAG_DEFAULT 0x00000001
-
-/* SWITCH_CORE :: PN_QUEUE1_SHAPER_STS_Port_5 :: SWITCH_RESV [30:29] */
-#define BCHP_SWITCH_CORE_PN_QUEUE1_SHAPER_STS_Port_5_SWITCH_RESV_MASK 0x60000000
-#define BCHP_SWITCH_CORE_PN_QUEUE1_SHAPER_STS_Port_5_SWITCH_RESV_SHIFT 29
-#define BCHP_SWITCH_CORE_PN_QUEUE1_SHAPER_STS_Port_5_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: PN_QUEUE1_SHAPER_STS_Port_5 :: BUCKET_CNT [28:00] */
-#define BCHP_SWITCH_CORE_PN_QUEUE1_SHAPER_STS_Port_5_BUCKET_CNT_MASK 0x1fffffff
-#define BCHP_SWITCH_CORE_PN_QUEUE1_SHAPER_STS_Port_5_BUCKET_CNT_SHIFT 0
-#define BCHP_SWITCH_CORE_PN_QUEUE1_SHAPER_STS_Port_5_BUCKET_CNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *P7_QUEUE1_SHAPER_STS - Port 7, Queue 1 Shaper Status Register
- ***************************************************************************/
-/* SWITCH_CORE :: P7_QUEUE1_SHAPER_STS :: IN_PROFILE_FLAG [31:31] */
-#define BCHP_SWITCH_CORE_P7_QUEUE1_SHAPER_STS_IN_PROFILE_FLAG_MASK 0x80000000
-#define BCHP_SWITCH_CORE_P7_QUEUE1_SHAPER_STS_IN_PROFILE_FLAG_SHIFT 31
-#define BCHP_SWITCH_CORE_P7_QUEUE1_SHAPER_STS_IN_PROFILE_FLAG_DEFAULT 0x00000001
-
-/* SWITCH_CORE :: P7_QUEUE1_SHAPER_STS :: SWITCH_RESV [30:29] */
-#define BCHP_SWITCH_CORE_P7_QUEUE1_SHAPER_STS_SWITCH_RESV_MASK 0x60000000
-#define BCHP_SWITCH_CORE_P7_QUEUE1_SHAPER_STS_SWITCH_RESV_SHIFT 29
-#define BCHP_SWITCH_CORE_P7_QUEUE1_SHAPER_STS_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: P7_QUEUE1_SHAPER_STS :: BUCKET_CNT [28:00] */
-#define BCHP_SWITCH_CORE_P7_QUEUE1_SHAPER_STS_BUCKET_CNT_MASK 0x1fffffff
-#define BCHP_SWITCH_CORE_P7_QUEUE1_SHAPER_STS_BUCKET_CNT_SHIFT 0
-#define BCHP_SWITCH_CORE_P7_QUEUE1_SHAPER_STS_BUCKET_CNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *IMP_QUEUE1_SHAPER_STS - Port 8, Queue 1 Shaper Status Register
- ***************************************************************************/
-/* SWITCH_CORE :: IMP_QUEUE1_SHAPER_STS :: IN_PROFILE_FLAG [31:31] */
-#define BCHP_SWITCH_CORE_IMP_QUEUE1_SHAPER_STS_IN_PROFILE_FLAG_MASK 0x80000000
-#define BCHP_SWITCH_CORE_IMP_QUEUE1_SHAPER_STS_IN_PROFILE_FLAG_SHIFT 31
-#define BCHP_SWITCH_CORE_IMP_QUEUE1_SHAPER_STS_IN_PROFILE_FLAG_DEFAULT 0x00000001
-
-/* SWITCH_CORE :: IMP_QUEUE1_SHAPER_STS :: SWITCH_RESV [30:29] */
-#define BCHP_SWITCH_CORE_IMP_QUEUE1_SHAPER_STS_SWITCH_RESV_MASK 0x60000000
-#define BCHP_SWITCH_CORE_IMP_QUEUE1_SHAPER_STS_SWITCH_RESV_SHIFT 29
-#define BCHP_SWITCH_CORE_IMP_QUEUE1_SHAPER_STS_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: IMP_QUEUE1_SHAPER_STS :: BUCKET_CNT [28:00] */
-#define BCHP_SWITCH_CORE_IMP_QUEUE1_SHAPER_STS_BUCKET_CNT_MASK 0x1fffffff
-#define BCHP_SWITCH_CORE_IMP_QUEUE1_SHAPER_STS_BUCKET_CNT_SHIFT 0
-#define BCHP_SWITCH_CORE_IMP_QUEUE1_SHAPER_STS_BUCKET_CNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *PN_QUEUE1_MAX_PACKET_REFRESH_Port_0 - Port N, Packet-based Queue 1 Shaping Rate Configure Register
- ***************************************************************************/
-/* SWITCH_CORE :: PN_QUEUE1_MAX_PACKET_REFRESH_Port_0 :: SWITCH_RESV [31:18] */
-#define BCHP_SWITCH_CORE_PN_QUEUE1_MAX_PACKET_REFRESH_Port_0_SWITCH_RESV_MASK 0xfffc0000
-#define BCHP_SWITCH_CORE_PN_QUEUE1_MAX_PACKET_REFRESH_Port_0_SWITCH_RESV_SHIFT 18
-#define BCHP_SWITCH_CORE_PN_QUEUE1_MAX_PACKET_REFRESH_Port_0_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: PN_QUEUE1_MAX_PACKET_REFRESH_Port_0 :: MAX_REFRESH [17:00] */
-#define BCHP_SWITCH_CORE_PN_QUEUE1_MAX_PACKET_REFRESH_Port_0_MAX_REFRESH_MASK 0x0003ffff
-#define BCHP_SWITCH_CORE_PN_QUEUE1_MAX_PACKET_REFRESH_Port_0_MAX_REFRESH_SHIFT 0
-#define BCHP_SWITCH_CORE_PN_QUEUE1_MAX_PACKET_REFRESH_Port_0_MAX_REFRESH_DEFAULT 0x00000000
-
-/***************************************************************************
- *PN_QUEUE1_MAX_PACKET_REFRESH_Port_1 - Port N, Packet-based Queue 1 Shaping Rate Configure Register
- ***************************************************************************/
-/* SWITCH_CORE :: PN_QUEUE1_MAX_PACKET_REFRESH_Port_1 :: SWITCH_RESV [31:18] */
-#define BCHP_SWITCH_CORE_PN_QUEUE1_MAX_PACKET_REFRESH_Port_1_SWITCH_RESV_MASK 0xfffc0000
-#define BCHP_SWITCH_CORE_PN_QUEUE1_MAX_PACKET_REFRESH_Port_1_SWITCH_RESV_SHIFT 18
-#define BCHP_SWITCH_CORE_PN_QUEUE1_MAX_PACKET_REFRESH_Port_1_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: PN_QUEUE1_MAX_PACKET_REFRESH_Port_1 :: MAX_REFRESH [17:00] */
-#define BCHP_SWITCH_CORE_PN_QUEUE1_MAX_PACKET_REFRESH_Port_1_MAX_REFRESH_MASK 0x0003ffff
-#define BCHP_SWITCH_CORE_PN_QUEUE1_MAX_PACKET_REFRESH_Port_1_MAX_REFRESH_SHIFT 0
-#define BCHP_SWITCH_CORE_PN_QUEUE1_MAX_PACKET_REFRESH_Port_1_MAX_REFRESH_DEFAULT 0x00000000
-
-/***************************************************************************
- *PN_QUEUE1_MAX_PACKET_REFRESH_Port_2 - Port N, Packet-based Queue 1 Shaping Rate Configure Register
- ***************************************************************************/
-/* SWITCH_CORE :: PN_QUEUE1_MAX_PACKET_REFRESH_Port_2 :: SWITCH_RESV [31:18] */
-#define BCHP_SWITCH_CORE_PN_QUEUE1_MAX_PACKET_REFRESH_Port_2_SWITCH_RESV_MASK 0xfffc0000
-#define BCHP_SWITCH_CORE_PN_QUEUE1_MAX_PACKET_REFRESH_Port_2_SWITCH_RESV_SHIFT 18
-#define BCHP_SWITCH_CORE_PN_QUEUE1_MAX_PACKET_REFRESH_Port_2_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: PN_QUEUE1_MAX_PACKET_REFRESH_Port_2 :: MAX_REFRESH [17:00] */
-#define BCHP_SWITCH_CORE_PN_QUEUE1_MAX_PACKET_REFRESH_Port_2_MAX_REFRESH_MASK 0x0003ffff
-#define BCHP_SWITCH_CORE_PN_QUEUE1_MAX_PACKET_REFRESH_Port_2_MAX_REFRESH_SHIFT 0
-#define BCHP_SWITCH_CORE_PN_QUEUE1_MAX_PACKET_REFRESH_Port_2_MAX_REFRESH_DEFAULT 0x00000000
-
-/***************************************************************************
- *PN_QUEUE1_MAX_PACKET_REFRESH_Port_3 - Port N, Packet-based Queue 1 Shaping Rate Configure Register
- ***************************************************************************/
-/* SWITCH_CORE :: PN_QUEUE1_MAX_PACKET_REFRESH_Port_3 :: SWITCH_RESV [31:18] */
-#define BCHP_SWITCH_CORE_PN_QUEUE1_MAX_PACKET_REFRESH_Port_3_SWITCH_RESV_MASK 0xfffc0000
-#define BCHP_SWITCH_CORE_PN_QUEUE1_MAX_PACKET_REFRESH_Port_3_SWITCH_RESV_SHIFT 18
-#define BCHP_SWITCH_CORE_PN_QUEUE1_MAX_PACKET_REFRESH_Port_3_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: PN_QUEUE1_MAX_PACKET_REFRESH_Port_3 :: MAX_REFRESH [17:00] */
-#define BCHP_SWITCH_CORE_PN_QUEUE1_MAX_PACKET_REFRESH_Port_3_MAX_REFRESH_MASK 0x0003ffff
-#define BCHP_SWITCH_CORE_PN_QUEUE1_MAX_PACKET_REFRESH_Port_3_MAX_REFRESH_SHIFT 0
-#define BCHP_SWITCH_CORE_PN_QUEUE1_MAX_PACKET_REFRESH_Port_3_MAX_REFRESH_DEFAULT 0x00000000
-
-/***************************************************************************
- *PN_QUEUE1_MAX_PACKET_REFRESH_Port_4 - Port N, Packet-based Queue 1 Shaping Rate Configure Register
- ***************************************************************************/
-/* SWITCH_CORE :: PN_QUEUE1_MAX_PACKET_REFRESH_Port_4 :: SWITCH_RESV [31:18] */
-#define BCHP_SWITCH_CORE_PN_QUEUE1_MAX_PACKET_REFRESH_Port_4_SWITCH_RESV_MASK 0xfffc0000
-#define BCHP_SWITCH_CORE_PN_QUEUE1_MAX_PACKET_REFRESH_Port_4_SWITCH_RESV_SHIFT 18
-#define BCHP_SWITCH_CORE_PN_QUEUE1_MAX_PACKET_REFRESH_Port_4_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: PN_QUEUE1_MAX_PACKET_REFRESH_Port_4 :: MAX_REFRESH [17:00] */
-#define BCHP_SWITCH_CORE_PN_QUEUE1_MAX_PACKET_REFRESH_Port_4_MAX_REFRESH_MASK 0x0003ffff
-#define BCHP_SWITCH_CORE_PN_QUEUE1_MAX_PACKET_REFRESH_Port_4_MAX_REFRESH_SHIFT 0
-#define BCHP_SWITCH_CORE_PN_QUEUE1_MAX_PACKET_REFRESH_Port_4_MAX_REFRESH_DEFAULT 0x00000000
-
-/***************************************************************************
- *PN_QUEUE1_MAX_PACKET_REFRESH_Port_5 - Port N, Packet-based Queue 1 Shaping Rate Configure Register
- ***************************************************************************/
-/* SWITCH_CORE :: PN_QUEUE1_MAX_PACKET_REFRESH_Port_5 :: SWITCH_RESV [31:18] */
-#define BCHP_SWITCH_CORE_PN_QUEUE1_MAX_PACKET_REFRESH_Port_5_SWITCH_RESV_MASK 0xfffc0000
-#define BCHP_SWITCH_CORE_PN_QUEUE1_MAX_PACKET_REFRESH_Port_5_SWITCH_RESV_SHIFT 18
-#define BCHP_SWITCH_CORE_PN_QUEUE1_MAX_PACKET_REFRESH_Port_5_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: PN_QUEUE1_MAX_PACKET_REFRESH_Port_5 :: MAX_REFRESH [17:00] */
-#define BCHP_SWITCH_CORE_PN_QUEUE1_MAX_PACKET_REFRESH_Port_5_MAX_REFRESH_MASK 0x0003ffff
-#define BCHP_SWITCH_CORE_PN_QUEUE1_MAX_PACKET_REFRESH_Port_5_MAX_REFRESH_SHIFT 0
-#define BCHP_SWITCH_CORE_PN_QUEUE1_MAX_PACKET_REFRESH_Port_5_MAX_REFRESH_DEFAULT 0x00000000
-
-/***************************************************************************
- *P7_QUEUE1_MAX_PACKET_REFRESH - Port 7, Packet-based Queue 1 Shaping Rate Configure Register
- ***************************************************************************/
-/* SWITCH_CORE :: P7_QUEUE1_MAX_PACKET_REFRESH :: SWITCH_RESV [31:18] */
-#define BCHP_SWITCH_CORE_P7_QUEUE1_MAX_PACKET_REFRESH_SWITCH_RESV_MASK 0xfffc0000
-#define BCHP_SWITCH_CORE_P7_QUEUE1_MAX_PACKET_REFRESH_SWITCH_RESV_SHIFT 18
-#define BCHP_SWITCH_CORE_P7_QUEUE1_MAX_PACKET_REFRESH_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: P7_QUEUE1_MAX_PACKET_REFRESH :: MAX_REFRESH [17:00] */
-#define BCHP_SWITCH_CORE_P7_QUEUE1_MAX_PACKET_REFRESH_MAX_REFRESH_MASK 0x0003ffff
-#define BCHP_SWITCH_CORE_P7_QUEUE1_MAX_PACKET_REFRESH_MAX_REFRESH_SHIFT 0
-#define BCHP_SWITCH_CORE_P7_QUEUE1_MAX_PACKET_REFRESH_MAX_REFRESH_DEFAULT 0x00000000
-
-/***************************************************************************
- *IMP_QUEUE1_MAX_PACKET_REFRESH - Port 8, Packet-based Queue 1 Shaping Rate Configure Register
- ***************************************************************************/
-/* SWITCH_CORE :: IMP_QUEUE1_MAX_PACKET_REFRESH :: SWITCH_RESV [31:18] */
-#define BCHP_SWITCH_CORE_IMP_QUEUE1_MAX_PACKET_REFRESH_SWITCH_RESV_MASK 0xfffc0000
-#define BCHP_SWITCH_CORE_IMP_QUEUE1_MAX_PACKET_REFRESH_SWITCH_RESV_SHIFT 18
-#define BCHP_SWITCH_CORE_IMP_QUEUE1_MAX_PACKET_REFRESH_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: IMP_QUEUE1_MAX_PACKET_REFRESH :: MAX_REFRESH [17:00] */
-#define BCHP_SWITCH_CORE_IMP_QUEUE1_MAX_PACKET_REFRESH_MAX_REFRESH_MASK 0x0003ffff
-#define BCHP_SWITCH_CORE_IMP_QUEUE1_MAX_PACKET_REFRESH_MAX_REFRESH_SHIFT 0
-#define BCHP_SWITCH_CORE_IMP_QUEUE1_MAX_PACKET_REFRESH_MAX_REFRESH_DEFAULT 0x00000000
-
-/***************************************************************************
- *EGRESS_SHAPER_Q1_CONFIG_REG_SPARE0 - Spare 0 Register (Not2Release)
- ***************************************************************************/
-/* SWITCH_CORE :: EGRESS_SHAPER_Q1_CONFIG_REG_SPARE0 :: EGRESS_SHAPER_Q1_CONFIG_REG_SPARE0 [31:00] */
-#define BCHP_SWITCH_CORE_EGRESS_SHAPER_Q1_CONFIG_REG_SPARE0_EGRESS_SHAPER_Q1_CONFIG_REG_SPARE0_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_EGRESS_SHAPER_Q1_CONFIG_REG_SPARE0_EGRESS_SHAPER_Q1_CONFIG_REG_SPARE0_SHIFT 0
-#define BCHP_SWITCH_CORE_EGRESS_SHAPER_Q1_CONFIG_REG_SPARE0_EGRESS_SHAPER_Q1_CONFIG_REG_SPARE0_DEFAULT 0x00000000
-
-/***************************************************************************
- *EGRESS_SHAPER_Q1_CONFIG_REG_SPARE1 - Spare 1 Register (Not2Release)
- ***************************************************************************/
-/* SWITCH_CORE :: EGRESS_SHAPER_Q1_CONFIG_REG_SPARE1 :: EGRESS_SHAPER_Q1_CONFIG_REG_SPARE1 [31:00] */
-#define BCHP_SWITCH_CORE_EGRESS_SHAPER_Q1_CONFIG_REG_SPARE1_EGRESS_SHAPER_Q1_CONFIG_REG_SPARE1_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_EGRESS_SHAPER_Q1_CONFIG_REG_SPARE1_EGRESS_SHAPER_Q1_CONFIG_REG_SPARE1_SHIFT 0
-#define BCHP_SWITCH_CORE_EGRESS_SHAPER_Q1_CONFIG_REG_SPARE1_EGRESS_SHAPER_Q1_CONFIG_REG_SPARE1_DEFAULT 0x00000000
-
-/***************************************************************************
- *PN_QUEUE1_MAX_PACKET_THD_SEL_Port_0 - Port N, Packet-based Queue 1 Burst Size Configure Register
- ***************************************************************************/
-/* SWITCH_CORE :: PN_QUEUE1_MAX_PACKET_THD_SEL_Port_0 :: SWITCH_RESV [31:18] */
-#define BCHP_SWITCH_CORE_PN_QUEUE1_MAX_PACKET_THD_SEL_Port_0_SWITCH_RESV_MASK 0xfffc0000
-#define BCHP_SWITCH_CORE_PN_QUEUE1_MAX_PACKET_THD_SEL_Port_0_SWITCH_RESV_SHIFT 18
-#define BCHP_SWITCH_CORE_PN_QUEUE1_MAX_PACKET_THD_SEL_Port_0_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: PN_QUEUE1_MAX_PACKET_THD_SEL_Port_0 :: MAX_THD_SEL [17:00] */
-#define BCHP_SWITCH_CORE_PN_QUEUE1_MAX_PACKET_THD_SEL_Port_0_MAX_THD_SEL_MASK 0x0003ffff
-#define BCHP_SWITCH_CORE_PN_QUEUE1_MAX_PACKET_THD_SEL_Port_0_MAX_THD_SEL_SHIFT 0
-#define BCHP_SWITCH_CORE_PN_QUEUE1_MAX_PACKET_THD_SEL_Port_0_MAX_THD_SEL_DEFAULT 0x00000000
-
-/***************************************************************************
- *PN_QUEUE1_MAX_PACKET_THD_SEL_Port_1 - Port N, Packet-based Queue 1 Burst Size Configure Register
- ***************************************************************************/
-/* SWITCH_CORE :: PN_QUEUE1_MAX_PACKET_THD_SEL_Port_1 :: SWITCH_RESV [31:18] */
-#define BCHP_SWITCH_CORE_PN_QUEUE1_MAX_PACKET_THD_SEL_Port_1_SWITCH_RESV_MASK 0xfffc0000
-#define BCHP_SWITCH_CORE_PN_QUEUE1_MAX_PACKET_THD_SEL_Port_1_SWITCH_RESV_SHIFT 18
-#define BCHP_SWITCH_CORE_PN_QUEUE1_MAX_PACKET_THD_SEL_Port_1_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: PN_QUEUE1_MAX_PACKET_THD_SEL_Port_1 :: MAX_THD_SEL [17:00] */
-#define BCHP_SWITCH_CORE_PN_QUEUE1_MAX_PACKET_THD_SEL_Port_1_MAX_THD_SEL_MASK 0x0003ffff
-#define BCHP_SWITCH_CORE_PN_QUEUE1_MAX_PACKET_THD_SEL_Port_1_MAX_THD_SEL_SHIFT 0
-#define BCHP_SWITCH_CORE_PN_QUEUE1_MAX_PACKET_THD_SEL_Port_1_MAX_THD_SEL_DEFAULT 0x00000000
-
-/***************************************************************************
- *PN_QUEUE1_MAX_PACKET_THD_SEL_Port_2 - Port N, Packet-based Queue 1 Burst Size Configure Register
- ***************************************************************************/
-/* SWITCH_CORE :: PN_QUEUE1_MAX_PACKET_THD_SEL_Port_2 :: SWITCH_RESV [31:18] */
-#define BCHP_SWITCH_CORE_PN_QUEUE1_MAX_PACKET_THD_SEL_Port_2_SWITCH_RESV_MASK 0xfffc0000
-#define BCHP_SWITCH_CORE_PN_QUEUE1_MAX_PACKET_THD_SEL_Port_2_SWITCH_RESV_SHIFT 18
-#define BCHP_SWITCH_CORE_PN_QUEUE1_MAX_PACKET_THD_SEL_Port_2_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: PN_QUEUE1_MAX_PACKET_THD_SEL_Port_2 :: MAX_THD_SEL [17:00] */
-#define BCHP_SWITCH_CORE_PN_QUEUE1_MAX_PACKET_THD_SEL_Port_2_MAX_THD_SEL_MASK 0x0003ffff
-#define BCHP_SWITCH_CORE_PN_QUEUE1_MAX_PACKET_THD_SEL_Port_2_MAX_THD_SEL_SHIFT 0
-#define BCHP_SWITCH_CORE_PN_QUEUE1_MAX_PACKET_THD_SEL_Port_2_MAX_THD_SEL_DEFAULT 0x00000000
-
-/***************************************************************************
- *PN_QUEUE1_MAX_PACKET_THD_SEL_Port_3 - Port N, Packet-based Queue 1 Burst Size Configure Register
- ***************************************************************************/
-/* SWITCH_CORE :: PN_QUEUE1_MAX_PACKET_THD_SEL_Port_3 :: SWITCH_RESV [31:18] */
-#define BCHP_SWITCH_CORE_PN_QUEUE1_MAX_PACKET_THD_SEL_Port_3_SWITCH_RESV_MASK 0xfffc0000
-#define BCHP_SWITCH_CORE_PN_QUEUE1_MAX_PACKET_THD_SEL_Port_3_SWITCH_RESV_SHIFT 18
-#define BCHP_SWITCH_CORE_PN_QUEUE1_MAX_PACKET_THD_SEL_Port_3_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: PN_QUEUE1_MAX_PACKET_THD_SEL_Port_3 :: MAX_THD_SEL [17:00] */
-#define BCHP_SWITCH_CORE_PN_QUEUE1_MAX_PACKET_THD_SEL_Port_3_MAX_THD_SEL_MASK 0x0003ffff
-#define BCHP_SWITCH_CORE_PN_QUEUE1_MAX_PACKET_THD_SEL_Port_3_MAX_THD_SEL_SHIFT 0
-#define BCHP_SWITCH_CORE_PN_QUEUE1_MAX_PACKET_THD_SEL_Port_3_MAX_THD_SEL_DEFAULT 0x00000000
-
-/***************************************************************************
- *PN_QUEUE1_MAX_PACKET_THD_SEL_Port_4 - Port N, Packet-based Queue 1 Burst Size Configure Register
- ***************************************************************************/
-/* SWITCH_CORE :: PN_QUEUE1_MAX_PACKET_THD_SEL_Port_4 :: SWITCH_RESV [31:18] */
-#define BCHP_SWITCH_CORE_PN_QUEUE1_MAX_PACKET_THD_SEL_Port_4_SWITCH_RESV_MASK 0xfffc0000
-#define BCHP_SWITCH_CORE_PN_QUEUE1_MAX_PACKET_THD_SEL_Port_4_SWITCH_RESV_SHIFT 18
-#define BCHP_SWITCH_CORE_PN_QUEUE1_MAX_PACKET_THD_SEL_Port_4_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: PN_QUEUE1_MAX_PACKET_THD_SEL_Port_4 :: MAX_THD_SEL [17:00] */
-#define BCHP_SWITCH_CORE_PN_QUEUE1_MAX_PACKET_THD_SEL_Port_4_MAX_THD_SEL_MASK 0x0003ffff
-#define BCHP_SWITCH_CORE_PN_QUEUE1_MAX_PACKET_THD_SEL_Port_4_MAX_THD_SEL_SHIFT 0
-#define BCHP_SWITCH_CORE_PN_QUEUE1_MAX_PACKET_THD_SEL_Port_4_MAX_THD_SEL_DEFAULT 0x00000000
-
-/***************************************************************************
- *PN_QUEUE1_MAX_PACKET_THD_SEL_Port_5 - Port N, Packet-based Queue 1 Burst Size Configure Register
- ***************************************************************************/
-/* SWITCH_CORE :: PN_QUEUE1_MAX_PACKET_THD_SEL_Port_5 :: SWITCH_RESV [31:18] */
-#define BCHP_SWITCH_CORE_PN_QUEUE1_MAX_PACKET_THD_SEL_Port_5_SWITCH_RESV_MASK 0xfffc0000
-#define BCHP_SWITCH_CORE_PN_QUEUE1_MAX_PACKET_THD_SEL_Port_5_SWITCH_RESV_SHIFT 18
-#define BCHP_SWITCH_CORE_PN_QUEUE1_MAX_PACKET_THD_SEL_Port_5_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: PN_QUEUE1_MAX_PACKET_THD_SEL_Port_5 :: MAX_THD_SEL [17:00] */
-#define BCHP_SWITCH_CORE_PN_QUEUE1_MAX_PACKET_THD_SEL_Port_5_MAX_THD_SEL_MASK 0x0003ffff
-#define BCHP_SWITCH_CORE_PN_QUEUE1_MAX_PACKET_THD_SEL_Port_5_MAX_THD_SEL_SHIFT 0
-#define BCHP_SWITCH_CORE_PN_QUEUE1_MAX_PACKET_THD_SEL_Port_5_MAX_THD_SEL_DEFAULT 0x00000000
-
-/***************************************************************************
- *P7_QUEUE1_MAX_PACKET_THD_SEL - Port 7, Packet-based Queue 1 Burst Size Configure Register
- ***************************************************************************/
-/* SWITCH_CORE :: P7_QUEUE1_MAX_PACKET_THD_SEL :: SWITCH_RESV [31:18] */
-#define BCHP_SWITCH_CORE_P7_QUEUE1_MAX_PACKET_THD_SEL_SWITCH_RESV_MASK 0xfffc0000
-#define BCHP_SWITCH_CORE_P7_QUEUE1_MAX_PACKET_THD_SEL_SWITCH_RESV_SHIFT 18
-#define BCHP_SWITCH_CORE_P7_QUEUE1_MAX_PACKET_THD_SEL_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: P7_QUEUE1_MAX_PACKET_THD_SEL :: MAX_THD_SEL [17:00] */
-#define BCHP_SWITCH_CORE_P7_QUEUE1_MAX_PACKET_THD_SEL_MAX_THD_SEL_MASK 0x0003ffff
-#define BCHP_SWITCH_CORE_P7_QUEUE1_MAX_PACKET_THD_SEL_MAX_THD_SEL_SHIFT 0
-#define BCHP_SWITCH_CORE_P7_QUEUE1_MAX_PACKET_THD_SEL_MAX_THD_SEL_DEFAULT 0x00000000
-
-/***************************************************************************
- *IMP_QUEUE1_MAX_PACKET_THD_SEL - Port 8, Packet-based Queue 1 Burst Size Configure Register
- ***************************************************************************/
-/* SWITCH_CORE :: IMP_QUEUE1_MAX_PACKET_THD_SEL :: SWITCH_RESV [31:18] */
-#define BCHP_SWITCH_CORE_IMP_QUEUE1_MAX_PACKET_THD_SEL_SWITCH_RESV_MASK 0xfffc0000
-#define BCHP_SWITCH_CORE_IMP_QUEUE1_MAX_PACKET_THD_SEL_SWITCH_RESV_SHIFT 18
-#define BCHP_SWITCH_CORE_IMP_QUEUE1_MAX_PACKET_THD_SEL_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: IMP_QUEUE1_MAX_PACKET_THD_SEL :: MAX_THD_SEL [17:00] */
-#define BCHP_SWITCH_CORE_IMP_QUEUE1_MAX_PACKET_THD_SEL_MAX_THD_SEL_MASK 0x0003ffff
-#define BCHP_SWITCH_CORE_IMP_QUEUE1_MAX_PACKET_THD_SEL_MAX_THD_SEL_SHIFT 0
-#define BCHP_SWITCH_CORE_IMP_QUEUE1_MAX_PACKET_THD_SEL_MAX_THD_SEL_DEFAULT 0x00000000
-
-/***************************************************************************
- *QUEUE1_AVB_SHAPING_MODE - Queue 1 AVB Shaping Mode Control Register
- ***************************************************************************/
-/* SWITCH_CORE :: QUEUE1_AVB_SHAPING_MODE :: reserved_for_padding0 [31:16] */
-#define BCHP_SWITCH_CORE_QUEUE1_AVB_SHAPING_MODE_reserved_for_padding0_MASK 0xffff0000
-#define BCHP_SWITCH_CORE_QUEUE1_AVB_SHAPING_MODE_reserved_for_padding0_SHIFT 16
-
-/* SWITCH_CORE :: QUEUE1_AVB_SHAPING_MODE :: SWITCH_RESV [15:09] */
-#define BCHP_SWITCH_CORE_QUEUE1_AVB_SHAPING_MODE_SWITCH_RESV_MASK 0x0000fe00
-#define BCHP_SWITCH_CORE_QUEUE1_AVB_SHAPING_MODE_SWITCH_RESV_SHIFT 9
-#define BCHP_SWITCH_CORE_QUEUE1_AVB_SHAPING_MODE_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: QUEUE1_AVB_SHAPING_MODE :: QUEUE1_AVB_SHAPING_MODE [08:00] */
-#define BCHP_SWITCH_CORE_QUEUE1_AVB_SHAPING_MODE_QUEUE1_AVB_SHAPING_MODE_MASK 0x000001ff
-#define BCHP_SWITCH_CORE_QUEUE1_AVB_SHAPING_MODE_QUEUE1_AVB_SHAPING_MODE_SHIFT 0
-#define BCHP_SWITCH_CORE_QUEUE1_AVB_SHAPING_MODE_QUEUE1_AVB_SHAPING_MODE_DEFAULT 0x00000000
-
-/***************************************************************************
- *QUEUE1_SHAPER_ENABLE - Queue 1 Shaper Enable Register
- ***************************************************************************/
-/* SWITCH_CORE :: QUEUE1_SHAPER_ENABLE :: reserved_for_padding0 [31:16] */
-#define BCHP_SWITCH_CORE_QUEUE1_SHAPER_ENABLE_reserved_for_padding0_MASK 0xffff0000
-#define BCHP_SWITCH_CORE_QUEUE1_SHAPER_ENABLE_reserved_for_padding0_SHIFT 16
-
-/* SWITCH_CORE :: QUEUE1_SHAPER_ENABLE :: SWITCH_RESV [15:09] */
-#define BCHP_SWITCH_CORE_QUEUE1_SHAPER_ENABLE_SWITCH_RESV_MASK 0x0000fe00
-#define BCHP_SWITCH_CORE_QUEUE1_SHAPER_ENABLE_SWITCH_RESV_SHIFT 9
-#define BCHP_SWITCH_CORE_QUEUE1_SHAPER_ENABLE_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: QUEUE1_SHAPER_ENABLE :: QUEUE1_SHAPER_ENABLE [08:00] */
-#define BCHP_SWITCH_CORE_QUEUE1_SHAPER_ENABLE_QUEUE1_SHAPER_ENABLE_MASK 0x000001ff
-#define BCHP_SWITCH_CORE_QUEUE1_SHAPER_ENABLE_QUEUE1_SHAPER_ENABLE_SHIFT 0
-#define BCHP_SWITCH_CORE_QUEUE1_SHAPER_ENABLE_QUEUE1_SHAPER_ENABLE_DEFAULT 0x00000000
-
-/***************************************************************************
- *QUEUE1_SHAPER_BUCKET_COUNT_SELECT - Queue 1 Bucket Count Select Register
- ***************************************************************************/
-/* SWITCH_CORE :: QUEUE1_SHAPER_BUCKET_COUNT_SELECT :: reserved_for_padding0 [31:16] */
-#define BCHP_SWITCH_CORE_QUEUE1_SHAPER_BUCKET_COUNT_SELECT_reserved_for_padding0_MASK 0xffff0000
-#define BCHP_SWITCH_CORE_QUEUE1_SHAPER_BUCKET_COUNT_SELECT_reserved_for_padding0_SHIFT 16
-
-/* SWITCH_CORE :: QUEUE1_SHAPER_BUCKET_COUNT_SELECT :: SWITCH_RESV [15:09] */
-#define BCHP_SWITCH_CORE_QUEUE1_SHAPER_BUCKET_COUNT_SELECT_SWITCH_RESV_MASK 0x0000fe00
-#define BCHP_SWITCH_CORE_QUEUE1_SHAPER_BUCKET_COUNT_SELECT_SWITCH_RESV_SHIFT 9
-#define BCHP_SWITCH_CORE_QUEUE1_SHAPER_BUCKET_COUNT_SELECT_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: QUEUE1_SHAPER_BUCKET_COUNT_SELECT :: QUEUE1_SHAPER_BUCKET_COUNT_SELECT [08:00] */
-#define BCHP_SWITCH_CORE_QUEUE1_SHAPER_BUCKET_COUNT_SELECT_QUEUE1_SHAPER_BUCKET_COUNT_SELECT_MASK 0x000001ff
-#define BCHP_SWITCH_CORE_QUEUE1_SHAPER_BUCKET_COUNT_SELECT_QUEUE1_SHAPER_BUCKET_COUNT_SELECT_SHIFT 0
-#define BCHP_SWITCH_CORE_QUEUE1_SHAPER_BUCKET_COUNT_SELECT_QUEUE1_SHAPER_BUCKET_COUNT_SELECT_DEFAULT 0x00000000
-
-/***************************************************************************
- *QUEUE1_SHAPER_BLOCKING - Queue 1 Shaper Blocking Control Register
- ***************************************************************************/
-/* SWITCH_CORE :: QUEUE1_SHAPER_BLOCKING :: reserved_for_padding0 [31:16] */
-#define BCHP_SWITCH_CORE_QUEUE1_SHAPER_BLOCKING_reserved_for_padding0_MASK 0xffff0000
-#define BCHP_SWITCH_CORE_QUEUE1_SHAPER_BLOCKING_reserved_for_padding0_SHIFT 16
-
-/* SWITCH_CORE :: QUEUE1_SHAPER_BLOCKING :: SWITCH_RESV [15:09] */
-#define BCHP_SWITCH_CORE_QUEUE1_SHAPER_BLOCKING_SWITCH_RESV_MASK 0x0000fe00
-#define BCHP_SWITCH_CORE_QUEUE1_SHAPER_BLOCKING_SWITCH_RESV_SHIFT 9
-#define BCHP_SWITCH_CORE_QUEUE1_SHAPER_BLOCKING_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: QUEUE1_SHAPER_BLOCKING :: QUEUE1_SHAPER_BLOCKING [08:00] */
-#define BCHP_SWITCH_CORE_QUEUE1_SHAPER_BLOCKING_QUEUE1_SHAPER_BLOCKING_MASK 0x000001ff
-#define BCHP_SWITCH_CORE_QUEUE1_SHAPER_BLOCKING_QUEUE1_SHAPER_BLOCKING_SHIFT 0
-#define BCHP_SWITCH_CORE_QUEUE1_SHAPER_BLOCKING_QUEUE1_SHAPER_BLOCKING_DEFAULT 0x00000000
-
-/***************************************************************************
- *PN_QUEUE2_MAX_REFRESH_Port_0 - Port N, Byte-based Queue 2 Shaping Rate Configure Register
- ***************************************************************************/
-/* SWITCH_CORE :: PN_QUEUE2_MAX_REFRESH_Port_0 :: SWITCH_RESV [31:18] */
-#define BCHP_SWITCH_CORE_PN_QUEUE2_MAX_REFRESH_Port_0_SWITCH_RESV_MASK 0xfffc0000
-#define BCHP_SWITCH_CORE_PN_QUEUE2_MAX_REFRESH_Port_0_SWITCH_RESV_SHIFT 18
-#define BCHP_SWITCH_CORE_PN_QUEUE2_MAX_REFRESH_Port_0_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: PN_QUEUE2_MAX_REFRESH_Port_0 :: MAX_REFRESH [17:00] */
-#define BCHP_SWITCH_CORE_PN_QUEUE2_MAX_REFRESH_Port_0_MAX_REFRESH_MASK 0x0003ffff
-#define BCHP_SWITCH_CORE_PN_QUEUE2_MAX_REFRESH_Port_0_MAX_REFRESH_SHIFT 0
-#define BCHP_SWITCH_CORE_PN_QUEUE2_MAX_REFRESH_Port_0_MAX_REFRESH_DEFAULT 0x00000000
-
-/***************************************************************************
- *PN_QUEUE2_MAX_REFRESH_Port_1 - Port N, Byte-based Queue 2 Shaping Rate Configure Register
- ***************************************************************************/
-/* SWITCH_CORE :: PN_QUEUE2_MAX_REFRESH_Port_1 :: SWITCH_RESV [31:18] */
-#define BCHP_SWITCH_CORE_PN_QUEUE2_MAX_REFRESH_Port_1_SWITCH_RESV_MASK 0xfffc0000
-#define BCHP_SWITCH_CORE_PN_QUEUE2_MAX_REFRESH_Port_1_SWITCH_RESV_SHIFT 18
-#define BCHP_SWITCH_CORE_PN_QUEUE2_MAX_REFRESH_Port_1_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: PN_QUEUE2_MAX_REFRESH_Port_1 :: MAX_REFRESH [17:00] */
-#define BCHP_SWITCH_CORE_PN_QUEUE2_MAX_REFRESH_Port_1_MAX_REFRESH_MASK 0x0003ffff
-#define BCHP_SWITCH_CORE_PN_QUEUE2_MAX_REFRESH_Port_1_MAX_REFRESH_SHIFT 0
-#define BCHP_SWITCH_CORE_PN_QUEUE2_MAX_REFRESH_Port_1_MAX_REFRESH_DEFAULT 0x00000000
-
-/***************************************************************************
- *PN_QUEUE2_MAX_REFRESH_Port_2 - Port N, Byte-based Queue 2 Shaping Rate Configure Register
- ***************************************************************************/
-/* SWITCH_CORE :: PN_QUEUE2_MAX_REFRESH_Port_2 :: SWITCH_RESV [31:18] */
-#define BCHP_SWITCH_CORE_PN_QUEUE2_MAX_REFRESH_Port_2_SWITCH_RESV_MASK 0xfffc0000
-#define BCHP_SWITCH_CORE_PN_QUEUE2_MAX_REFRESH_Port_2_SWITCH_RESV_SHIFT 18
-#define BCHP_SWITCH_CORE_PN_QUEUE2_MAX_REFRESH_Port_2_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: PN_QUEUE2_MAX_REFRESH_Port_2 :: MAX_REFRESH [17:00] */
-#define BCHP_SWITCH_CORE_PN_QUEUE2_MAX_REFRESH_Port_2_MAX_REFRESH_MASK 0x0003ffff
-#define BCHP_SWITCH_CORE_PN_QUEUE2_MAX_REFRESH_Port_2_MAX_REFRESH_SHIFT 0
-#define BCHP_SWITCH_CORE_PN_QUEUE2_MAX_REFRESH_Port_2_MAX_REFRESH_DEFAULT 0x00000000
-
-/***************************************************************************
- *PN_QUEUE2_MAX_REFRESH_Port_3 - Port N, Byte-based Queue 2 Shaping Rate Configure Register
- ***************************************************************************/
-/* SWITCH_CORE :: PN_QUEUE2_MAX_REFRESH_Port_3 :: SWITCH_RESV [31:18] */
-#define BCHP_SWITCH_CORE_PN_QUEUE2_MAX_REFRESH_Port_3_SWITCH_RESV_MASK 0xfffc0000
-#define BCHP_SWITCH_CORE_PN_QUEUE2_MAX_REFRESH_Port_3_SWITCH_RESV_SHIFT 18
-#define BCHP_SWITCH_CORE_PN_QUEUE2_MAX_REFRESH_Port_3_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: PN_QUEUE2_MAX_REFRESH_Port_3 :: MAX_REFRESH [17:00] */
-#define BCHP_SWITCH_CORE_PN_QUEUE2_MAX_REFRESH_Port_3_MAX_REFRESH_MASK 0x0003ffff
-#define BCHP_SWITCH_CORE_PN_QUEUE2_MAX_REFRESH_Port_3_MAX_REFRESH_SHIFT 0
-#define BCHP_SWITCH_CORE_PN_QUEUE2_MAX_REFRESH_Port_3_MAX_REFRESH_DEFAULT 0x00000000
-
-/***************************************************************************
- *PN_QUEUE2_MAX_REFRESH_Port_4 - Port N, Byte-based Queue 2 Shaping Rate Configure Register
- ***************************************************************************/
-/* SWITCH_CORE :: PN_QUEUE2_MAX_REFRESH_Port_4 :: SWITCH_RESV [31:18] */
-#define BCHP_SWITCH_CORE_PN_QUEUE2_MAX_REFRESH_Port_4_SWITCH_RESV_MASK 0xfffc0000
-#define BCHP_SWITCH_CORE_PN_QUEUE2_MAX_REFRESH_Port_4_SWITCH_RESV_SHIFT 18
-#define BCHP_SWITCH_CORE_PN_QUEUE2_MAX_REFRESH_Port_4_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: PN_QUEUE2_MAX_REFRESH_Port_4 :: MAX_REFRESH [17:00] */
-#define BCHP_SWITCH_CORE_PN_QUEUE2_MAX_REFRESH_Port_4_MAX_REFRESH_MASK 0x0003ffff
-#define BCHP_SWITCH_CORE_PN_QUEUE2_MAX_REFRESH_Port_4_MAX_REFRESH_SHIFT 0
-#define BCHP_SWITCH_CORE_PN_QUEUE2_MAX_REFRESH_Port_4_MAX_REFRESH_DEFAULT 0x00000000
-
-/***************************************************************************
- *PN_QUEUE2_MAX_REFRESH_Port_5 - Port N, Byte-based Queue 2 Shaping Rate Configure Register
- ***************************************************************************/
-/* SWITCH_CORE :: PN_QUEUE2_MAX_REFRESH_Port_5 :: SWITCH_RESV [31:18] */
-#define BCHP_SWITCH_CORE_PN_QUEUE2_MAX_REFRESH_Port_5_SWITCH_RESV_MASK 0xfffc0000
-#define BCHP_SWITCH_CORE_PN_QUEUE2_MAX_REFRESH_Port_5_SWITCH_RESV_SHIFT 18
-#define BCHP_SWITCH_CORE_PN_QUEUE2_MAX_REFRESH_Port_5_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: PN_QUEUE2_MAX_REFRESH_Port_5 :: MAX_REFRESH [17:00] */
-#define BCHP_SWITCH_CORE_PN_QUEUE2_MAX_REFRESH_Port_5_MAX_REFRESH_MASK 0x0003ffff
-#define BCHP_SWITCH_CORE_PN_QUEUE2_MAX_REFRESH_Port_5_MAX_REFRESH_SHIFT 0
-#define BCHP_SWITCH_CORE_PN_QUEUE2_MAX_REFRESH_Port_5_MAX_REFRESH_DEFAULT 0x00000000
-
-/***************************************************************************
- *P7_QUEUE2_MAX_REFRESH - Port 7, Byte-based Queue 2 Shaping Rate Configure Register
- ***************************************************************************/
-/* SWITCH_CORE :: P7_QUEUE2_MAX_REFRESH :: SWITCH_RESV [31:18] */
-#define BCHP_SWITCH_CORE_P7_QUEUE2_MAX_REFRESH_SWITCH_RESV_MASK 0xfffc0000
-#define BCHP_SWITCH_CORE_P7_QUEUE2_MAX_REFRESH_SWITCH_RESV_SHIFT 18
-#define BCHP_SWITCH_CORE_P7_QUEUE2_MAX_REFRESH_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: P7_QUEUE2_MAX_REFRESH :: MAX_REFRESH [17:00] */
-#define BCHP_SWITCH_CORE_P7_QUEUE2_MAX_REFRESH_MAX_REFRESH_MASK 0x0003ffff
-#define BCHP_SWITCH_CORE_P7_QUEUE2_MAX_REFRESH_MAX_REFRESH_SHIFT 0
-#define BCHP_SWITCH_CORE_P7_QUEUE2_MAX_REFRESH_MAX_REFRESH_DEFAULT 0x00000000
-
-/***************************************************************************
- *IMP_QUEUE2_MAX_REFRESH - Port 8, Byte-based Queue 2 Shaping Rate Configure Register
- ***************************************************************************/
-/* SWITCH_CORE :: IMP_QUEUE2_MAX_REFRESH :: SWITCH_RESV [31:18] */
-#define BCHP_SWITCH_CORE_IMP_QUEUE2_MAX_REFRESH_SWITCH_RESV_MASK 0xfffc0000
-#define BCHP_SWITCH_CORE_IMP_QUEUE2_MAX_REFRESH_SWITCH_RESV_SHIFT 18
-#define BCHP_SWITCH_CORE_IMP_QUEUE2_MAX_REFRESH_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: IMP_QUEUE2_MAX_REFRESH :: MAX_REFRESH [17:00] */
-#define BCHP_SWITCH_CORE_IMP_QUEUE2_MAX_REFRESH_MAX_REFRESH_MASK 0x0003ffff
-#define BCHP_SWITCH_CORE_IMP_QUEUE2_MAX_REFRESH_MAX_REFRESH_SHIFT 0
-#define BCHP_SWITCH_CORE_IMP_QUEUE2_MAX_REFRESH_MAX_REFRESH_DEFAULT 0x00000000
-
-/***************************************************************************
- *PN_QUEUE2_MAX_THD_SEL_Port_0 - Port N, Byte-based Queue 2 Burst Size Configure Register
- ***************************************************************************/
-/* SWITCH_CORE :: PN_QUEUE2_MAX_THD_SEL_Port_0 :: SWITCH_RESV [31:18] */
-#define BCHP_SWITCH_CORE_PN_QUEUE2_MAX_THD_SEL_Port_0_SWITCH_RESV_MASK 0xfffc0000
-#define BCHP_SWITCH_CORE_PN_QUEUE2_MAX_THD_SEL_Port_0_SWITCH_RESV_SHIFT 18
-#define BCHP_SWITCH_CORE_PN_QUEUE2_MAX_THD_SEL_Port_0_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: PN_QUEUE2_MAX_THD_SEL_Port_0 :: MAX_THD_SEL [17:00] */
-#define BCHP_SWITCH_CORE_PN_QUEUE2_MAX_THD_SEL_Port_0_MAX_THD_SEL_MASK 0x0003ffff
-#define BCHP_SWITCH_CORE_PN_QUEUE2_MAX_THD_SEL_Port_0_MAX_THD_SEL_SHIFT 0
-#define BCHP_SWITCH_CORE_PN_QUEUE2_MAX_THD_SEL_Port_0_MAX_THD_SEL_DEFAULT 0x00000000
-
-/***************************************************************************
- *PN_QUEUE2_MAX_THD_SEL_Port_1 - Port N, Byte-based Queue 2 Burst Size Configure Register
- ***************************************************************************/
-/* SWITCH_CORE :: PN_QUEUE2_MAX_THD_SEL_Port_1 :: SWITCH_RESV [31:18] */
-#define BCHP_SWITCH_CORE_PN_QUEUE2_MAX_THD_SEL_Port_1_SWITCH_RESV_MASK 0xfffc0000
-#define BCHP_SWITCH_CORE_PN_QUEUE2_MAX_THD_SEL_Port_1_SWITCH_RESV_SHIFT 18
-#define BCHP_SWITCH_CORE_PN_QUEUE2_MAX_THD_SEL_Port_1_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: PN_QUEUE2_MAX_THD_SEL_Port_1 :: MAX_THD_SEL [17:00] */
-#define BCHP_SWITCH_CORE_PN_QUEUE2_MAX_THD_SEL_Port_1_MAX_THD_SEL_MASK 0x0003ffff
-#define BCHP_SWITCH_CORE_PN_QUEUE2_MAX_THD_SEL_Port_1_MAX_THD_SEL_SHIFT 0
-#define BCHP_SWITCH_CORE_PN_QUEUE2_MAX_THD_SEL_Port_1_MAX_THD_SEL_DEFAULT 0x00000000
-
-/***************************************************************************
- *PN_QUEUE2_MAX_THD_SEL_Port_2 - Port N, Byte-based Queue 2 Burst Size Configure Register
- ***************************************************************************/
-/* SWITCH_CORE :: PN_QUEUE2_MAX_THD_SEL_Port_2 :: SWITCH_RESV [31:18] */
-#define BCHP_SWITCH_CORE_PN_QUEUE2_MAX_THD_SEL_Port_2_SWITCH_RESV_MASK 0xfffc0000
-#define BCHP_SWITCH_CORE_PN_QUEUE2_MAX_THD_SEL_Port_2_SWITCH_RESV_SHIFT 18
-#define BCHP_SWITCH_CORE_PN_QUEUE2_MAX_THD_SEL_Port_2_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: PN_QUEUE2_MAX_THD_SEL_Port_2 :: MAX_THD_SEL [17:00] */
-#define BCHP_SWITCH_CORE_PN_QUEUE2_MAX_THD_SEL_Port_2_MAX_THD_SEL_MASK 0x0003ffff
-#define BCHP_SWITCH_CORE_PN_QUEUE2_MAX_THD_SEL_Port_2_MAX_THD_SEL_SHIFT 0
-#define BCHP_SWITCH_CORE_PN_QUEUE2_MAX_THD_SEL_Port_2_MAX_THD_SEL_DEFAULT 0x00000000
-
-/***************************************************************************
- *PN_QUEUE2_MAX_THD_SEL_Port_3 - Port N, Byte-based Queue 2 Burst Size Configure Register
- ***************************************************************************/
-/* SWITCH_CORE :: PN_QUEUE2_MAX_THD_SEL_Port_3 :: SWITCH_RESV [31:18] */
-#define BCHP_SWITCH_CORE_PN_QUEUE2_MAX_THD_SEL_Port_3_SWITCH_RESV_MASK 0xfffc0000
-#define BCHP_SWITCH_CORE_PN_QUEUE2_MAX_THD_SEL_Port_3_SWITCH_RESV_SHIFT 18
-#define BCHP_SWITCH_CORE_PN_QUEUE2_MAX_THD_SEL_Port_3_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: PN_QUEUE2_MAX_THD_SEL_Port_3 :: MAX_THD_SEL [17:00] */
-#define BCHP_SWITCH_CORE_PN_QUEUE2_MAX_THD_SEL_Port_3_MAX_THD_SEL_MASK 0x0003ffff
-#define BCHP_SWITCH_CORE_PN_QUEUE2_MAX_THD_SEL_Port_3_MAX_THD_SEL_SHIFT 0
-#define BCHP_SWITCH_CORE_PN_QUEUE2_MAX_THD_SEL_Port_3_MAX_THD_SEL_DEFAULT 0x00000000
-
-/***************************************************************************
- *PN_QUEUE2_MAX_THD_SEL_Port_4 - Port N, Byte-based Queue 2 Burst Size Configure Register
- ***************************************************************************/
-/* SWITCH_CORE :: PN_QUEUE2_MAX_THD_SEL_Port_4 :: SWITCH_RESV [31:18] */
-#define BCHP_SWITCH_CORE_PN_QUEUE2_MAX_THD_SEL_Port_4_SWITCH_RESV_MASK 0xfffc0000
-#define BCHP_SWITCH_CORE_PN_QUEUE2_MAX_THD_SEL_Port_4_SWITCH_RESV_SHIFT 18
-#define BCHP_SWITCH_CORE_PN_QUEUE2_MAX_THD_SEL_Port_4_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: PN_QUEUE2_MAX_THD_SEL_Port_4 :: MAX_THD_SEL [17:00] */
-#define BCHP_SWITCH_CORE_PN_QUEUE2_MAX_THD_SEL_Port_4_MAX_THD_SEL_MASK 0x0003ffff
-#define BCHP_SWITCH_CORE_PN_QUEUE2_MAX_THD_SEL_Port_4_MAX_THD_SEL_SHIFT 0
-#define BCHP_SWITCH_CORE_PN_QUEUE2_MAX_THD_SEL_Port_4_MAX_THD_SEL_DEFAULT 0x00000000
-
-/***************************************************************************
- *PN_QUEUE2_MAX_THD_SEL_Port_5 - Port N, Byte-based Queue 2 Burst Size Configure Register
- ***************************************************************************/
-/* SWITCH_CORE :: PN_QUEUE2_MAX_THD_SEL_Port_5 :: SWITCH_RESV [31:18] */
-#define BCHP_SWITCH_CORE_PN_QUEUE2_MAX_THD_SEL_Port_5_SWITCH_RESV_MASK 0xfffc0000
-#define BCHP_SWITCH_CORE_PN_QUEUE2_MAX_THD_SEL_Port_5_SWITCH_RESV_SHIFT 18
-#define BCHP_SWITCH_CORE_PN_QUEUE2_MAX_THD_SEL_Port_5_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: PN_QUEUE2_MAX_THD_SEL_Port_5 :: MAX_THD_SEL [17:00] */
-#define BCHP_SWITCH_CORE_PN_QUEUE2_MAX_THD_SEL_Port_5_MAX_THD_SEL_MASK 0x0003ffff
-#define BCHP_SWITCH_CORE_PN_QUEUE2_MAX_THD_SEL_Port_5_MAX_THD_SEL_SHIFT 0
-#define BCHP_SWITCH_CORE_PN_QUEUE2_MAX_THD_SEL_Port_5_MAX_THD_SEL_DEFAULT 0x00000000
-
-/***************************************************************************
- *P7_QUEUE2_MAX_THD_SEL - Port 7, Byte-based Queue 2 Burst Size Configure Register
- ***************************************************************************/
-/* SWITCH_CORE :: P7_QUEUE2_MAX_THD_SEL :: SWITCH_RESV [31:18] */
-#define BCHP_SWITCH_CORE_P7_QUEUE2_MAX_THD_SEL_SWITCH_RESV_MASK 0xfffc0000
-#define BCHP_SWITCH_CORE_P7_QUEUE2_MAX_THD_SEL_SWITCH_RESV_SHIFT 18
-#define BCHP_SWITCH_CORE_P7_QUEUE2_MAX_THD_SEL_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: P7_QUEUE2_MAX_THD_SEL :: MAX_THD_SEL [17:00] */
-#define BCHP_SWITCH_CORE_P7_QUEUE2_MAX_THD_SEL_MAX_THD_SEL_MASK 0x0003ffff
-#define BCHP_SWITCH_CORE_P7_QUEUE2_MAX_THD_SEL_MAX_THD_SEL_SHIFT 0
-#define BCHP_SWITCH_CORE_P7_QUEUE2_MAX_THD_SEL_MAX_THD_SEL_DEFAULT 0x00000000
-
-/***************************************************************************
- *IMP_QUEUE2_MAX_THD_SEL - Port 8, Byte-based Queue 2 Burst Size Configure Register
- ***************************************************************************/
-/* SWITCH_CORE :: IMP_QUEUE2_MAX_THD_SEL :: SWITCH_RESV [31:18] */
-#define BCHP_SWITCH_CORE_IMP_QUEUE2_MAX_THD_SEL_SWITCH_RESV_MASK 0xfffc0000
-#define BCHP_SWITCH_CORE_IMP_QUEUE2_MAX_THD_SEL_SWITCH_RESV_SHIFT 18
-#define BCHP_SWITCH_CORE_IMP_QUEUE2_MAX_THD_SEL_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: IMP_QUEUE2_MAX_THD_SEL :: MAX_THD_SEL [17:00] */
-#define BCHP_SWITCH_CORE_IMP_QUEUE2_MAX_THD_SEL_MAX_THD_SEL_MASK 0x0003ffff
-#define BCHP_SWITCH_CORE_IMP_QUEUE2_MAX_THD_SEL_MAX_THD_SEL_SHIFT 0
-#define BCHP_SWITCH_CORE_IMP_QUEUE2_MAX_THD_SEL_MAX_THD_SEL_DEFAULT 0x00000000
-
-/***************************************************************************
- *PN_QUEUE2_SHAPER_STS_Port_0 - Port N, Queue 2 Shaper Status Register
- ***************************************************************************/
-/* SWITCH_CORE :: PN_QUEUE2_SHAPER_STS_Port_0 :: IN_PROFILE_FLAG [31:31] */
-#define BCHP_SWITCH_CORE_PN_QUEUE2_SHAPER_STS_Port_0_IN_PROFILE_FLAG_MASK 0x80000000
-#define BCHP_SWITCH_CORE_PN_QUEUE2_SHAPER_STS_Port_0_IN_PROFILE_FLAG_SHIFT 31
-#define BCHP_SWITCH_CORE_PN_QUEUE2_SHAPER_STS_Port_0_IN_PROFILE_FLAG_DEFAULT 0x00000001
-
-/* SWITCH_CORE :: PN_QUEUE2_SHAPER_STS_Port_0 :: SWITCH_RESV [30:29] */
-#define BCHP_SWITCH_CORE_PN_QUEUE2_SHAPER_STS_Port_0_SWITCH_RESV_MASK 0x60000000
-#define BCHP_SWITCH_CORE_PN_QUEUE2_SHAPER_STS_Port_0_SWITCH_RESV_SHIFT 29
-#define BCHP_SWITCH_CORE_PN_QUEUE2_SHAPER_STS_Port_0_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: PN_QUEUE2_SHAPER_STS_Port_0 :: BUCKET_CNT [28:00] */
-#define BCHP_SWITCH_CORE_PN_QUEUE2_SHAPER_STS_Port_0_BUCKET_CNT_MASK 0x1fffffff
-#define BCHP_SWITCH_CORE_PN_QUEUE2_SHAPER_STS_Port_0_BUCKET_CNT_SHIFT 0
-#define BCHP_SWITCH_CORE_PN_QUEUE2_SHAPER_STS_Port_0_BUCKET_CNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *PN_QUEUE2_SHAPER_STS_Port_1 - Port N, Queue 2 Shaper Status Register
- ***************************************************************************/
-/* SWITCH_CORE :: PN_QUEUE2_SHAPER_STS_Port_1 :: IN_PROFILE_FLAG [31:31] */
-#define BCHP_SWITCH_CORE_PN_QUEUE2_SHAPER_STS_Port_1_IN_PROFILE_FLAG_MASK 0x80000000
-#define BCHP_SWITCH_CORE_PN_QUEUE2_SHAPER_STS_Port_1_IN_PROFILE_FLAG_SHIFT 31
-#define BCHP_SWITCH_CORE_PN_QUEUE2_SHAPER_STS_Port_1_IN_PROFILE_FLAG_DEFAULT 0x00000001
-
-/* SWITCH_CORE :: PN_QUEUE2_SHAPER_STS_Port_1 :: SWITCH_RESV [30:29] */
-#define BCHP_SWITCH_CORE_PN_QUEUE2_SHAPER_STS_Port_1_SWITCH_RESV_MASK 0x60000000
-#define BCHP_SWITCH_CORE_PN_QUEUE2_SHAPER_STS_Port_1_SWITCH_RESV_SHIFT 29
-#define BCHP_SWITCH_CORE_PN_QUEUE2_SHAPER_STS_Port_1_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: PN_QUEUE2_SHAPER_STS_Port_1 :: BUCKET_CNT [28:00] */
-#define BCHP_SWITCH_CORE_PN_QUEUE2_SHAPER_STS_Port_1_BUCKET_CNT_MASK 0x1fffffff
-#define BCHP_SWITCH_CORE_PN_QUEUE2_SHAPER_STS_Port_1_BUCKET_CNT_SHIFT 0
-#define BCHP_SWITCH_CORE_PN_QUEUE2_SHAPER_STS_Port_1_BUCKET_CNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *PN_QUEUE2_SHAPER_STS_Port_2 - Port N, Queue 2 Shaper Status Register
- ***************************************************************************/
-/* SWITCH_CORE :: PN_QUEUE2_SHAPER_STS_Port_2 :: IN_PROFILE_FLAG [31:31] */
-#define BCHP_SWITCH_CORE_PN_QUEUE2_SHAPER_STS_Port_2_IN_PROFILE_FLAG_MASK 0x80000000
-#define BCHP_SWITCH_CORE_PN_QUEUE2_SHAPER_STS_Port_2_IN_PROFILE_FLAG_SHIFT 31
-#define BCHP_SWITCH_CORE_PN_QUEUE2_SHAPER_STS_Port_2_IN_PROFILE_FLAG_DEFAULT 0x00000001
-
-/* SWITCH_CORE :: PN_QUEUE2_SHAPER_STS_Port_2 :: SWITCH_RESV [30:29] */
-#define BCHP_SWITCH_CORE_PN_QUEUE2_SHAPER_STS_Port_2_SWITCH_RESV_MASK 0x60000000
-#define BCHP_SWITCH_CORE_PN_QUEUE2_SHAPER_STS_Port_2_SWITCH_RESV_SHIFT 29
-#define BCHP_SWITCH_CORE_PN_QUEUE2_SHAPER_STS_Port_2_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: PN_QUEUE2_SHAPER_STS_Port_2 :: BUCKET_CNT [28:00] */
-#define BCHP_SWITCH_CORE_PN_QUEUE2_SHAPER_STS_Port_2_BUCKET_CNT_MASK 0x1fffffff
-#define BCHP_SWITCH_CORE_PN_QUEUE2_SHAPER_STS_Port_2_BUCKET_CNT_SHIFT 0
-#define BCHP_SWITCH_CORE_PN_QUEUE2_SHAPER_STS_Port_2_BUCKET_CNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *PN_QUEUE2_SHAPER_STS_Port_3 - Port N, Queue 2 Shaper Status Register
- ***************************************************************************/
-/* SWITCH_CORE :: PN_QUEUE2_SHAPER_STS_Port_3 :: IN_PROFILE_FLAG [31:31] */
-#define BCHP_SWITCH_CORE_PN_QUEUE2_SHAPER_STS_Port_3_IN_PROFILE_FLAG_MASK 0x80000000
-#define BCHP_SWITCH_CORE_PN_QUEUE2_SHAPER_STS_Port_3_IN_PROFILE_FLAG_SHIFT 31
-#define BCHP_SWITCH_CORE_PN_QUEUE2_SHAPER_STS_Port_3_IN_PROFILE_FLAG_DEFAULT 0x00000001
-
-/* SWITCH_CORE :: PN_QUEUE2_SHAPER_STS_Port_3 :: SWITCH_RESV [30:29] */
-#define BCHP_SWITCH_CORE_PN_QUEUE2_SHAPER_STS_Port_3_SWITCH_RESV_MASK 0x60000000
-#define BCHP_SWITCH_CORE_PN_QUEUE2_SHAPER_STS_Port_3_SWITCH_RESV_SHIFT 29
-#define BCHP_SWITCH_CORE_PN_QUEUE2_SHAPER_STS_Port_3_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: PN_QUEUE2_SHAPER_STS_Port_3 :: BUCKET_CNT [28:00] */
-#define BCHP_SWITCH_CORE_PN_QUEUE2_SHAPER_STS_Port_3_BUCKET_CNT_MASK 0x1fffffff
-#define BCHP_SWITCH_CORE_PN_QUEUE2_SHAPER_STS_Port_3_BUCKET_CNT_SHIFT 0
-#define BCHP_SWITCH_CORE_PN_QUEUE2_SHAPER_STS_Port_3_BUCKET_CNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *PN_QUEUE2_SHAPER_STS_Port_4 - Port N, Queue 2 Shaper Status Register
- ***************************************************************************/
-/* SWITCH_CORE :: PN_QUEUE2_SHAPER_STS_Port_4 :: IN_PROFILE_FLAG [31:31] */
-#define BCHP_SWITCH_CORE_PN_QUEUE2_SHAPER_STS_Port_4_IN_PROFILE_FLAG_MASK 0x80000000
-#define BCHP_SWITCH_CORE_PN_QUEUE2_SHAPER_STS_Port_4_IN_PROFILE_FLAG_SHIFT 31
-#define BCHP_SWITCH_CORE_PN_QUEUE2_SHAPER_STS_Port_4_IN_PROFILE_FLAG_DEFAULT 0x00000001
-
-/* SWITCH_CORE :: PN_QUEUE2_SHAPER_STS_Port_4 :: SWITCH_RESV [30:29] */
-#define BCHP_SWITCH_CORE_PN_QUEUE2_SHAPER_STS_Port_4_SWITCH_RESV_MASK 0x60000000
-#define BCHP_SWITCH_CORE_PN_QUEUE2_SHAPER_STS_Port_4_SWITCH_RESV_SHIFT 29
-#define BCHP_SWITCH_CORE_PN_QUEUE2_SHAPER_STS_Port_4_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: PN_QUEUE2_SHAPER_STS_Port_4 :: BUCKET_CNT [28:00] */
-#define BCHP_SWITCH_CORE_PN_QUEUE2_SHAPER_STS_Port_4_BUCKET_CNT_MASK 0x1fffffff
-#define BCHP_SWITCH_CORE_PN_QUEUE2_SHAPER_STS_Port_4_BUCKET_CNT_SHIFT 0
-#define BCHP_SWITCH_CORE_PN_QUEUE2_SHAPER_STS_Port_4_BUCKET_CNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *PN_QUEUE2_SHAPER_STS_Port_5 - Port N, Queue 2 Shaper Status Register
- ***************************************************************************/
-/* SWITCH_CORE :: PN_QUEUE2_SHAPER_STS_Port_5 :: IN_PROFILE_FLAG [31:31] */
-#define BCHP_SWITCH_CORE_PN_QUEUE2_SHAPER_STS_Port_5_IN_PROFILE_FLAG_MASK 0x80000000
-#define BCHP_SWITCH_CORE_PN_QUEUE2_SHAPER_STS_Port_5_IN_PROFILE_FLAG_SHIFT 31
-#define BCHP_SWITCH_CORE_PN_QUEUE2_SHAPER_STS_Port_5_IN_PROFILE_FLAG_DEFAULT 0x00000001
-
-/* SWITCH_CORE :: PN_QUEUE2_SHAPER_STS_Port_5 :: SWITCH_RESV [30:29] */
-#define BCHP_SWITCH_CORE_PN_QUEUE2_SHAPER_STS_Port_5_SWITCH_RESV_MASK 0x60000000
-#define BCHP_SWITCH_CORE_PN_QUEUE2_SHAPER_STS_Port_5_SWITCH_RESV_SHIFT 29
-#define BCHP_SWITCH_CORE_PN_QUEUE2_SHAPER_STS_Port_5_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: PN_QUEUE2_SHAPER_STS_Port_5 :: BUCKET_CNT [28:00] */
-#define BCHP_SWITCH_CORE_PN_QUEUE2_SHAPER_STS_Port_5_BUCKET_CNT_MASK 0x1fffffff
-#define BCHP_SWITCH_CORE_PN_QUEUE2_SHAPER_STS_Port_5_BUCKET_CNT_SHIFT 0
-#define BCHP_SWITCH_CORE_PN_QUEUE2_SHAPER_STS_Port_5_BUCKET_CNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *P7_QUEUE2_SHAPER_STS - Port 7, Queue 2 Shaper Status Register
- ***************************************************************************/
-/* SWITCH_CORE :: P7_QUEUE2_SHAPER_STS :: IN_PROFILE_FLAG [31:31] */
-#define BCHP_SWITCH_CORE_P7_QUEUE2_SHAPER_STS_IN_PROFILE_FLAG_MASK 0x80000000
-#define BCHP_SWITCH_CORE_P7_QUEUE2_SHAPER_STS_IN_PROFILE_FLAG_SHIFT 31
-#define BCHP_SWITCH_CORE_P7_QUEUE2_SHAPER_STS_IN_PROFILE_FLAG_DEFAULT 0x00000001
-
-/* SWITCH_CORE :: P7_QUEUE2_SHAPER_STS :: SWITCH_RESV [30:29] */
-#define BCHP_SWITCH_CORE_P7_QUEUE2_SHAPER_STS_SWITCH_RESV_MASK 0x60000000
-#define BCHP_SWITCH_CORE_P7_QUEUE2_SHAPER_STS_SWITCH_RESV_SHIFT 29
-#define BCHP_SWITCH_CORE_P7_QUEUE2_SHAPER_STS_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: P7_QUEUE2_SHAPER_STS :: BUCKET_CNT [28:00] */
-#define BCHP_SWITCH_CORE_P7_QUEUE2_SHAPER_STS_BUCKET_CNT_MASK 0x1fffffff
-#define BCHP_SWITCH_CORE_P7_QUEUE2_SHAPER_STS_BUCKET_CNT_SHIFT 0
-#define BCHP_SWITCH_CORE_P7_QUEUE2_SHAPER_STS_BUCKET_CNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *IMP_QUEUE2_SHAPER_STS - Port 8, Queue 2 Shaper Status Register
- ***************************************************************************/
-/* SWITCH_CORE :: IMP_QUEUE2_SHAPER_STS :: IN_PROFILE_FLAG [31:31] */
-#define BCHP_SWITCH_CORE_IMP_QUEUE2_SHAPER_STS_IN_PROFILE_FLAG_MASK 0x80000000
-#define BCHP_SWITCH_CORE_IMP_QUEUE2_SHAPER_STS_IN_PROFILE_FLAG_SHIFT 31
-#define BCHP_SWITCH_CORE_IMP_QUEUE2_SHAPER_STS_IN_PROFILE_FLAG_DEFAULT 0x00000001
-
-/* SWITCH_CORE :: IMP_QUEUE2_SHAPER_STS :: SWITCH_RESV [30:29] */
-#define BCHP_SWITCH_CORE_IMP_QUEUE2_SHAPER_STS_SWITCH_RESV_MASK 0x60000000
-#define BCHP_SWITCH_CORE_IMP_QUEUE2_SHAPER_STS_SWITCH_RESV_SHIFT 29
-#define BCHP_SWITCH_CORE_IMP_QUEUE2_SHAPER_STS_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: IMP_QUEUE2_SHAPER_STS :: BUCKET_CNT [28:00] */
-#define BCHP_SWITCH_CORE_IMP_QUEUE2_SHAPER_STS_BUCKET_CNT_MASK 0x1fffffff
-#define BCHP_SWITCH_CORE_IMP_QUEUE2_SHAPER_STS_BUCKET_CNT_SHIFT 0
-#define BCHP_SWITCH_CORE_IMP_QUEUE2_SHAPER_STS_BUCKET_CNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *PN_QUEUE2_MAX_PACKET_REFRESH_Port_0 - Port N, Packet-based Queue 2 Shaping Rate Configure Register
- ***************************************************************************/
-/* SWITCH_CORE :: PN_QUEUE2_MAX_PACKET_REFRESH_Port_0 :: SWITCH_RESV [31:18] */
-#define BCHP_SWITCH_CORE_PN_QUEUE2_MAX_PACKET_REFRESH_Port_0_SWITCH_RESV_MASK 0xfffc0000
-#define BCHP_SWITCH_CORE_PN_QUEUE2_MAX_PACKET_REFRESH_Port_0_SWITCH_RESV_SHIFT 18
-#define BCHP_SWITCH_CORE_PN_QUEUE2_MAX_PACKET_REFRESH_Port_0_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: PN_QUEUE2_MAX_PACKET_REFRESH_Port_0 :: MAX_REFRESH [17:00] */
-#define BCHP_SWITCH_CORE_PN_QUEUE2_MAX_PACKET_REFRESH_Port_0_MAX_REFRESH_MASK 0x0003ffff
-#define BCHP_SWITCH_CORE_PN_QUEUE2_MAX_PACKET_REFRESH_Port_0_MAX_REFRESH_SHIFT 0
-#define BCHP_SWITCH_CORE_PN_QUEUE2_MAX_PACKET_REFRESH_Port_0_MAX_REFRESH_DEFAULT 0x00000000
-
-/***************************************************************************
- *PN_QUEUE2_MAX_PACKET_REFRESH_Port_1 - Port N, Packet-based Queue 2 Shaping Rate Configure Register
- ***************************************************************************/
-/* SWITCH_CORE :: PN_QUEUE2_MAX_PACKET_REFRESH_Port_1 :: SWITCH_RESV [31:18] */
-#define BCHP_SWITCH_CORE_PN_QUEUE2_MAX_PACKET_REFRESH_Port_1_SWITCH_RESV_MASK 0xfffc0000
-#define BCHP_SWITCH_CORE_PN_QUEUE2_MAX_PACKET_REFRESH_Port_1_SWITCH_RESV_SHIFT 18
-#define BCHP_SWITCH_CORE_PN_QUEUE2_MAX_PACKET_REFRESH_Port_1_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: PN_QUEUE2_MAX_PACKET_REFRESH_Port_1 :: MAX_REFRESH [17:00] */
-#define BCHP_SWITCH_CORE_PN_QUEUE2_MAX_PACKET_REFRESH_Port_1_MAX_REFRESH_MASK 0x0003ffff
-#define BCHP_SWITCH_CORE_PN_QUEUE2_MAX_PACKET_REFRESH_Port_1_MAX_REFRESH_SHIFT 0
-#define BCHP_SWITCH_CORE_PN_QUEUE2_MAX_PACKET_REFRESH_Port_1_MAX_REFRESH_DEFAULT 0x00000000
-
-/***************************************************************************
- *PN_QUEUE2_MAX_PACKET_REFRESH_Port_2 - Port N, Packet-based Queue 2 Shaping Rate Configure Register
- ***************************************************************************/
-/* SWITCH_CORE :: PN_QUEUE2_MAX_PACKET_REFRESH_Port_2 :: SWITCH_RESV [31:18] */
-#define BCHP_SWITCH_CORE_PN_QUEUE2_MAX_PACKET_REFRESH_Port_2_SWITCH_RESV_MASK 0xfffc0000
-#define BCHP_SWITCH_CORE_PN_QUEUE2_MAX_PACKET_REFRESH_Port_2_SWITCH_RESV_SHIFT 18
-#define BCHP_SWITCH_CORE_PN_QUEUE2_MAX_PACKET_REFRESH_Port_2_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: PN_QUEUE2_MAX_PACKET_REFRESH_Port_2 :: MAX_REFRESH [17:00] */
-#define BCHP_SWITCH_CORE_PN_QUEUE2_MAX_PACKET_REFRESH_Port_2_MAX_REFRESH_MASK 0x0003ffff
-#define BCHP_SWITCH_CORE_PN_QUEUE2_MAX_PACKET_REFRESH_Port_2_MAX_REFRESH_SHIFT 0
-#define BCHP_SWITCH_CORE_PN_QUEUE2_MAX_PACKET_REFRESH_Port_2_MAX_REFRESH_DEFAULT 0x00000000
-
-/***************************************************************************
- *PN_QUEUE2_MAX_PACKET_REFRESH_Port_3 - Port N, Packet-based Queue 2 Shaping Rate Configure Register
- ***************************************************************************/
-/* SWITCH_CORE :: PN_QUEUE2_MAX_PACKET_REFRESH_Port_3 :: SWITCH_RESV [31:18] */
-#define BCHP_SWITCH_CORE_PN_QUEUE2_MAX_PACKET_REFRESH_Port_3_SWITCH_RESV_MASK 0xfffc0000
-#define BCHP_SWITCH_CORE_PN_QUEUE2_MAX_PACKET_REFRESH_Port_3_SWITCH_RESV_SHIFT 18
-#define BCHP_SWITCH_CORE_PN_QUEUE2_MAX_PACKET_REFRESH_Port_3_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: PN_QUEUE2_MAX_PACKET_REFRESH_Port_3 :: MAX_REFRESH [17:00] */
-#define BCHP_SWITCH_CORE_PN_QUEUE2_MAX_PACKET_REFRESH_Port_3_MAX_REFRESH_MASK 0x0003ffff
-#define BCHP_SWITCH_CORE_PN_QUEUE2_MAX_PACKET_REFRESH_Port_3_MAX_REFRESH_SHIFT 0
-#define BCHP_SWITCH_CORE_PN_QUEUE2_MAX_PACKET_REFRESH_Port_3_MAX_REFRESH_DEFAULT 0x00000000
-
-/***************************************************************************
- *PN_QUEUE2_MAX_PACKET_REFRESH_Port_4 - Port N, Packet-based Queue 2 Shaping Rate Configure Register
- ***************************************************************************/
-/* SWITCH_CORE :: PN_QUEUE2_MAX_PACKET_REFRESH_Port_4 :: SWITCH_RESV [31:18] */
-#define BCHP_SWITCH_CORE_PN_QUEUE2_MAX_PACKET_REFRESH_Port_4_SWITCH_RESV_MASK 0xfffc0000
-#define BCHP_SWITCH_CORE_PN_QUEUE2_MAX_PACKET_REFRESH_Port_4_SWITCH_RESV_SHIFT 18
-#define BCHP_SWITCH_CORE_PN_QUEUE2_MAX_PACKET_REFRESH_Port_4_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: PN_QUEUE2_MAX_PACKET_REFRESH_Port_4 :: MAX_REFRESH [17:00] */
-#define BCHP_SWITCH_CORE_PN_QUEUE2_MAX_PACKET_REFRESH_Port_4_MAX_REFRESH_MASK 0x0003ffff
-#define BCHP_SWITCH_CORE_PN_QUEUE2_MAX_PACKET_REFRESH_Port_4_MAX_REFRESH_SHIFT 0
-#define BCHP_SWITCH_CORE_PN_QUEUE2_MAX_PACKET_REFRESH_Port_4_MAX_REFRESH_DEFAULT 0x00000000
-
-/***************************************************************************
- *PN_QUEUE2_MAX_PACKET_REFRESH_Port_5 - Port N, Packet-based Queue 2 Shaping Rate Configure Register
- ***************************************************************************/
-/* SWITCH_CORE :: PN_QUEUE2_MAX_PACKET_REFRESH_Port_5 :: SWITCH_RESV [31:18] */
-#define BCHP_SWITCH_CORE_PN_QUEUE2_MAX_PACKET_REFRESH_Port_5_SWITCH_RESV_MASK 0xfffc0000
-#define BCHP_SWITCH_CORE_PN_QUEUE2_MAX_PACKET_REFRESH_Port_5_SWITCH_RESV_SHIFT 18
-#define BCHP_SWITCH_CORE_PN_QUEUE2_MAX_PACKET_REFRESH_Port_5_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: PN_QUEUE2_MAX_PACKET_REFRESH_Port_5 :: MAX_REFRESH [17:00] */
-#define BCHP_SWITCH_CORE_PN_QUEUE2_MAX_PACKET_REFRESH_Port_5_MAX_REFRESH_MASK 0x0003ffff
-#define BCHP_SWITCH_CORE_PN_QUEUE2_MAX_PACKET_REFRESH_Port_5_MAX_REFRESH_SHIFT 0
-#define BCHP_SWITCH_CORE_PN_QUEUE2_MAX_PACKET_REFRESH_Port_5_MAX_REFRESH_DEFAULT 0x00000000
-
-/***************************************************************************
- *P7_QUEUE2_MAX_PACKET_REFRESH - Port 7, Packet-based Queue 2 Shaping Rate Configure Register
- ***************************************************************************/
-/* SWITCH_CORE :: P7_QUEUE2_MAX_PACKET_REFRESH :: SWITCH_RESV [31:18] */
-#define BCHP_SWITCH_CORE_P7_QUEUE2_MAX_PACKET_REFRESH_SWITCH_RESV_MASK 0xfffc0000
-#define BCHP_SWITCH_CORE_P7_QUEUE2_MAX_PACKET_REFRESH_SWITCH_RESV_SHIFT 18
-#define BCHP_SWITCH_CORE_P7_QUEUE2_MAX_PACKET_REFRESH_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: P7_QUEUE2_MAX_PACKET_REFRESH :: MAX_REFRESH [17:00] */
-#define BCHP_SWITCH_CORE_P7_QUEUE2_MAX_PACKET_REFRESH_MAX_REFRESH_MASK 0x0003ffff
-#define BCHP_SWITCH_CORE_P7_QUEUE2_MAX_PACKET_REFRESH_MAX_REFRESH_SHIFT 0
-#define BCHP_SWITCH_CORE_P7_QUEUE2_MAX_PACKET_REFRESH_MAX_REFRESH_DEFAULT 0x00000000
-
-/***************************************************************************
- *IMP_QUEUE2_MAX_PACKET_REFRESH - Port 8, Packet-based Queue 2 Shaping Rate Configure Register
- ***************************************************************************/
-/* SWITCH_CORE :: IMP_QUEUE2_MAX_PACKET_REFRESH :: SWITCH_RESV [31:18] */
-#define BCHP_SWITCH_CORE_IMP_QUEUE2_MAX_PACKET_REFRESH_SWITCH_RESV_MASK 0xfffc0000
-#define BCHP_SWITCH_CORE_IMP_QUEUE2_MAX_PACKET_REFRESH_SWITCH_RESV_SHIFT 18
-#define BCHP_SWITCH_CORE_IMP_QUEUE2_MAX_PACKET_REFRESH_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: IMP_QUEUE2_MAX_PACKET_REFRESH :: MAX_REFRESH [17:00] */
-#define BCHP_SWITCH_CORE_IMP_QUEUE2_MAX_PACKET_REFRESH_MAX_REFRESH_MASK 0x0003ffff
-#define BCHP_SWITCH_CORE_IMP_QUEUE2_MAX_PACKET_REFRESH_MAX_REFRESH_SHIFT 0
-#define BCHP_SWITCH_CORE_IMP_QUEUE2_MAX_PACKET_REFRESH_MAX_REFRESH_DEFAULT 0x00000000
-
-/***************************************************************************
- *EGRESS_SHAPER_Q2_CONFIG_REG_SPARE0 - Spare 0 Register (Not2Release)
- ***************************************************************************/
-/* SWITCH_CORE :: EGRESS_SHAPER_Q2_CONFIG_REG_SPARE0 :: EGRESS_SHAPER_Q2_CONFIG_REG_SPARE0 [31:00] */
-#define BCHP_SWITCH_CORE_EGRESS_SHAPER_Q2_CONFIG_REG_SPARE0_EGRESS_SHAPER_Q2_CONFIG_REG_SPARE0_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_EGRESS_SHAPER_Q2_CONFIG_REG_SPARE0_EGRESS_SHAPER_Q2_CONFIG_REG_SPARE0_SHIFT 0
-#define BCHP_SWITCH_CORE_EGRESS_SHAPER_Q2_CONFIG_REG_SPARE0_EGRESS_SHAPER_Q2_CONFIG_REG_SPARE0_DEFAULT 0x00000000
-
-/***************************************************************************
- *EGRESS_SHAPER_Q2_CONFIG_REG_SPARE1 - Spare 1 Register (Not2Release)
- ***************************************************************************/
-/* SWITCH_CORE :: EGRESS_SHAPER_Q2_CONFIG_REG_SPARE1 :: EGRESS_SHAPER_Q2_CONFIG_REG_SPARE1 [31:00] */
-#define BCHP_SWITCH_CORE_EGRESS_SHAPER_Q2_CONFIG_REG_SPARE1_EGRESS_SHAPER_Q2_CONFIG_REG_SPARE1_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_EGRESS_SHAPER_Q2_CONFIG_REG_SPARE1_EGRESS_SHAPER_Q2_CONFIG_REG_SPARE1_SHIFT 0
-#define BCHP_SWITCH_CORE_EGRESS_SHAPER_Q2_CONFIG_REG_SPARE1_EGRESS_SHAPER_Q2_CONFIG_REG_SPARE1_DEFAULT 0x00000000
-
-/***************************************************************************
- *PN_QUEUE2_MAX_PACKET_THD_SEL_Port_0 - Port N, Packet-based Queue 2 Burst Size Configure Register
- ***************************************************************************/
-/* SWITCH_CORE :: PN_QUEUE2_MAX_PACKET_THD_SEL_Port_0 :: SWITCH_RESV [31:18] */
-#define BCHP_SWITCH_CORE_PN_QUEUE2_MAX_PACKET_THD_SEL_Port_0_SWITCH_RESV_MASK 0xfffc0000
-#define BCHP_SWITCH_CORE_PN_QUEUE2_MAX_PACKET_THD_SEL_Port_0_SWITCH_RESV_SHIFT 18
-#define BCHP_SWITCH_CORE_PN_QUEUE2_MAX_PACKET_THD_SEL_Port_0_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: PN_QUEUE2_MAX_PACKET_THD_SEL_Port_0 :: MAX_THD_SEL [17:00] */
-#define BCHP_SWITCH_CORE_PN_QUEUE2_MAX_PACKET_THD_SEL_Port_0_MAX_THD_SEL_MASK 0x0003ffff
-#define BCHP_SWITCH_CORE_PN_QUEUE2_MAX_PACKET_THD_SEL_Port_0_MAX_THD_SEL_SHIFT 0
-#define BCHP_SWITCH_CORE_PN_QUEUE2_MAX_PACKET_THD_SEL_Port_0_MAX_THD_SEL_DEFAULT 0x00000000
-
-/***************************************************************************
- *PN_QUEUE2_MAX_PACKET_THD_SEL_Port_1 - Port N, Packet-based Queue 2 Burst Size Configure Register
- ***************************************************************************/
-/* SWITCH_CORE :: PN_QUEUE2_MAX_PACKET_THD_SEL_Port_1 :: SWITCH_RESV [31:18] */
-#define BCHP_SWITCH_CORE_PN_QUEUE2_MAX_PACKET_THD_SEL_Port_1_SWITCH_RESV_MASK 0xfffc0000
-#define BCHP_SWITCH_CORE_PN_QUEUE2_MAX_PACKET_THD_SEL_Port_1_SWITCH_RESV_SHIFT 18
-#define BCHP_SWITCH_CORE_PN_QUEUE2_MAX_PACKET_THD_SEL_Port_1_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: PN_QUEUE2_MAX_PACKET_THD_SEL_Port_1 :: MAX_THD_SEL [17:00] */
-#define BCHP_SWITCH_CORE_PN_QUEUE2_MAX_PACKET_THD_SEL_Port_1_MAX_THD_SEL_MASK 0x0003ffff
-#define BCHP_SWITCH_CORE_PN_QUEUE2_MAX_PACKET_THD_SEL_Port_1_MAX_THD_SEL_SHIFT 0
-#define BCHP_SWITCH_CORE_PN_QUEUE2_MAX_PACKET_THD_SEL_Port_1_MAX_THD_SEL_DEFAULT 0x00000000
-
-/***************************************************************************
- *PN_QUEUE2_MAX_PACKET_THD_SEL_Port_2 - Port N, Packet-based Queue 2 Burst Size Configure Register
- ***************************************************************************/
-/* SWITCH_CORE :: PN_QUEUE2_MAX_PACKET_THD_SEL_Port_2 :: SWITCH_RESV [31:18] */
-#define BCHP_SWITCH_CORE_PN_QUEUE2_MAX_PACKET_THD_SEL_Port_2_SWITCH_RESV_MASK 0xfffc0000
-#define BCHP_SWITCH_CORE_PN_QUEUE2_MAX_PACKET_THD_SEL_Port_2_SWITCH_RESV_SHIFT 18
-#define BCHP_SWITCH_CORE_PN_QUEUE2_MAX_PACKET_THD_SEL_Port_2_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: PN_QUEUE2_MAX_PACKET_THD_SEL_Port_2 :: MAX_THD_SEL [17:00] */
-#define BCHP_SWITCH_CORE_PN_QUEUE2_MAX_PACKET_THD_SEL_Port_2_MAX_THD_SEL_MASK 0x0003ffff
-#define BCHP_SWITCH_CORE_PN_QUEUE2_MAX_PACKET_THD_SEL_Port_2_MAX_THD_SEL_SHIFT 0
-#define BCHP_SWITCH_CORE_PN_QUEUE2_MAX_PACKET_THD_SEL_Port_2_MAX_THD_SEL_DEFAULT 0x00000000
-
-/***************************************************************************
- *PN_QUEUE2_MAX_PACKET_THD_SEL_Port_3 - Port N, Packet-based Queue 2 Burst Size Configure Register
- ***************************************************************************/
-/* SWITCH_CORE :: PN_QUEUE2_MAX_PACKET_THD_SEL_Port_3 :: SWITCH_RESV [31:18] */
-#define BCHP_SWITCH_CORE_PN_QUEUE2_MAX_PACKET_THD_SEL_Port_3_SWITCH_RESV_MASK 0xfffc0000
-#define BCHP_SWITCH_CORE_PN_QUEUE2_MAX_PACKET_THD_SEL_Port_3_SWITCH_RESV_SHIFT 18
-#define BCHP_SWITCH_CORE_PN_QUEUE2_MAX_PACKET_THD_SEL_Port_3_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: PN_QUEUE2_MAX_PACKET_THD_SEL_Port_3 :: MAX_THD_SEL [17:00] */
-#define BCHP_SWITCH_CORE_PN_QUEUE2_MAX_PACKET_THD_SEL_Port_3_MAX_THD_SEL_MASK 0x0003ffff
-#define BCHP_SWITCH_CORE_PN_QUEUE2_MAX_PACKET_THD_SEL_Port_3_MAX_THD_SEL_SHIFT 0
-#define BCHP_SWITCH_CORE_PN_QUEUE2_MAX_PACKET_THD_SEL_Port_3_MAX_THD_SEL_DEFAULT 0x00000000
-
-/***************************************************************************
- *PN_QUEUE2_MAX_PACKET_THD_SEL_Port_4 - Port N, Packet-based Queue 2 Burst Size Configure Register
- ***************************************************************************/
-/* SWITCH_CORE :: PN_QUEUE2_MAX_PACKET_THD_SEL_Port_4 :: SWITCH_RESV [31:18] */
-#define BCHP_SWITCH_CORE_PN_QUEUE2_MAX_PACKET_THD_SEL_Port_4_SWITCH_RESV_MASK 0xfffc0000
-#define BCHP_SWITCH_CORE_PN_QUEUE2_MAX_PACKET_THD_SEL_Port_4_SWITCH_RESV_SHIFT 18
-#define BCHP_SWITCH_CORE_PN_QUEUE2_MAX_PACKET_THD_SEL_Port_4_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: PN_QUEUE2_MAX_PACKET_THD_SEL_Port_4 :: MAX_THD_SEL [17:00] */
-#define BCHP_SWITCH_CORE_PN_QUEUE2_MAX_PACKET_THD_SEL_Port_4_MAX_THD_SEL_MASK 0x0003ffff
-#define BCHP_SWITCH_CORE_PN_QUEUE2_MAX_PACKET_THD_SEL_Port_4_MAX_THD_SEL_SHIFT 0
-#define BCHP_SWITCH_CORE_PN_QUEUE2_MAX_PACKET_THD_SEL_Port_4_MAX_THD_SEL_DEFAULT 0x00000000
-
-/***************************************************************************
- *PN_QUEUE2_MAX_PACKET_THD_SEL_Port_5 - Port N, Packet-based Queue 2 Burst Size Configure Register
- ***************************************************************************/
-/* SWITCH_CORE :: PN_QUEUE2_MAX_PACKET_THD_SEL_Port_5 :: SWITCH_RESV [31:18] */
-#define BCHP_SWITCH_CORE_PN_QUEUE2_MAX_PACKET_THD_SEL_Port_5_SWITCH_RESV_MASK 0xfffc0000
-#define BCHP_SWITCH_CORE_PN_QUEUE2_MAX_PACKET_THD_SEL_Port_5_SWITCH_RESV_SHIFT 18
-#define BCHP_SWITCH_CORE_PN_QUEUE2_MAX_PACKET_THD_SEL_Port_5_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: PN_QUEUE2_MAX_PACKET_THD_SEL_Port_5 :: MAX_THD_SEL [17:00] */
-#define BCHP_SWITCH_CORE_PN_QUEUE2_MAX_PACKET_THD_SEL_Port_5_MAX_THD_SEL_MASK 0x0003ffff
-#define BCHP_SWITCH_CORE_PN_QUEUE2_MAX_PACKET_THD_SEL_Port_5_MAX_THD_SEL_SHIFT 0
-#define BCHP_SWITCH_CORE_PN_QUEUE2_MAX_PACKET_THD_SEL_Port_5_MAX_THD_SEL_DEFAULT 0x00000000
-
-/***************************************************************************
- *P7_QUEUE2_MAX_PACKET_THD_SEL - Port 7, Packet-based Queue 2 Burst Size Configure Register
- ***************************************************************************/
-/* SWITCH_CORE :: P7_QUEUE2_MAX_PACKET_THD_SEL :: SWITCH_RESV [31:18] */
-#define BCHP_SWITCH_CORE_P7_QUEUE2_MAX_PACKET_THD_SEL_SWITCH_RESV_MASK 0xfffc0000
-#define BCHP_SWITCH_CORE_P7_QUEUE2_MAX_PACKET_THD_SEL_SWITCH_RESV_SHIFT 18
-#define BCHP_SWITCH_CORE_P7_QUEUE2_MAX_PACKET_THD_SEL_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: P7_QUEUE2_MAX_PACKET_THD_SEL :: MAX_THD_SEL [17:00] */
-#define BCHP_SWITCH_CORE_P7_QUEUE2_MAX_PACKET_THD_SEL_MAX_THD_SEL_MASK 0x0003ffff
-#define BCHP_SWITCH_CORE_P7_QUEUE2_MAX_PACKET_THD_SEL_MAX_THD_SEL_SHIFT 0
-#define BCHP_SWITCH_CORE_P7_QUEUE2_MAX_PACKET_THD_SEL_MAX_THD_SEL_DEFAULT 0x00000000
-
-/***************************************************************************
- *IMP_QUEUE2_MAX_PACKET_THD_SEL - Port 8, Packet-based Queue 2 Burst Size Configure Register
- ***************************************************************************/
-/* SWITCH_CORE :: IMP_QUEUE2_MAX_PACKET_THD_SEL :: SWITCH_RESV [31:18] */
-#define BCHP_SWITCH_CORE_IMP_QUEUE2_MAX_PACKET_THD_SEL_SWITCH_RESV_MASK 0xfffc0000
-#define BCHP_SWITCH_CORE_IMP_QUEUE2_MAX_PACKET_THD_SEL_SWITCH_RESV_SHIFT 18
-#define BCHP_SWITCH_CORE_IMP_QUEUE2_MAX_PACKET_THD_SEL_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: IMP_QUEUE2_MAX_PACKET_THD_SEL :: MAX_THD_SEL [17:00] */
-#define BCHP_SWITCH_CORE_IMP_QUEUE2_MAX_PACKET_THD_SEL_MAX_THD_SEL_MASK 0x0003ffff
-#define BCHP_SWITCH_CORE_IMP_QUEUE2_MAX_PACKET_THD_SEL_MAX_THD_SEL_SHIFT 0
-#define BCHP_SWITCH_CORE_IMP_QUEUE2_MAX_PACKET_THD_SEL_MAX_THD_SEL_DEFAULT 0x00000000
-
-/***************************************************************************
- *QUEUE2_AVB_SHAPING_MODE - Queue 2 AVB Shaping Mode Control Register
- ***************************************************************************/
-/* SWITCH_CORE :: QUEUE2_AVB_SHAPING_MODE :: reserved_for_padding0 [31:16] */
-#define BCHP_SWITCH_CORE_QUEUE2_AVB_SHAPING_MODE_reserved_for_padding0_MASK 0xffff0000
-#define BCHP_SWITCH_CORE_QUEUE2_AVB_SHAPING_MODE_reserved_for_padding0_SHIFT 16
-
-/* SWITCH_CORE :: QUEUE2_AVB_SHAPING_MODE :: SWITCH_RESV [15:09] */
-#define BCHP_SWITCH_CORE_QUEUE2_AVB_SHAPING_MODE_SWITCH_RESV_MASK 0x0000fe00
-#define BCHP_SWITCH_CORE_QUEUE2_AVB_SHAPING_MODE_SWITCH_RESV_SHIFT 9
-#define BCHP_SWITCH_CORE_QUEUE2_AVB_SHAPING_MODE_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: QUEUE2_AVB_SHAPING_MODE :: QUEUE2_AVB_SHAPING_MODE [08:00] */
-#define BCHP_SWITCH_CORE_QUEUE2_AVB_SHAPING_MODE_QUEUE2_AVB_SHAPING_MODE_MASK 0x000001ff
-#define BCHP_SWITCH_CORE_QUEUE2_AVB_SHAPING_MODE_QUEUE2_AVB_SHAPING_MODE_SHIFT 0
-#define BCHP_SWITCH_CORE_QUEUE2_AVB_SHAPING_MODE_QUEUE2_AVB_SHAPING_MODE_DEFAULT 0x00000000
-
-/***************************************************************************
- *QUEUE2_SHAPER_ENABLE - Queue 2 Shaper Enable Register
- ***************************************************************************/
-/* SWITCH_CORE :: QUEUE2_SHAPER_ENABLE :: reserved_for_padding0 [31:16] */
-#define BCHP_SWITCH_CORE_QUEUE2_SHAPER_ENABLE_reserved_for_padding0_MASK 0xffff0000
-#define BCHP_SWITCH_CORE_QUEUE2_SHAPER_ENABLE_reserved_for_padding0_SHIFT 16
-
-/* SWITCH_CORE :: QUEUE2_SHAPER_ENABLE :: SWITCH_RESV [15:09] */
-#define BCHP_SWITCH_CORE_QUEUE2_SHAPER_ENABLE_SWITCH_RESV_MASK 0x0000fe00
-#define BCHP_SWITCH_CORE_QUEUE2_SHAPER_ENABLE_SWITCH_RESV_SHIFT 9
-#define BCHP_SWITCH_CORE_QUEUE2_SHAPER_ENABLE_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: QUEUE2_SHAPER_ENABLE :: QUEUE2_SHAPER_ENABLE [08:00] */
-#define BCHP_SWITCH_CORE_QUEUE2_SHAPER_ENABLE_QUEUE2_SHAPER_ENABLE_MASK 0x000001ff
-#define BCHP_SWITCH_CORE_QUEUE2_SHAPER_ENABLE_QUEUE2_SHAPER_ENABLE_SHIFT 0
-#define BCHP_SWITCH_CORE_QUEUE2_SHAPER_ENABLE_QUEUE2_SHAPER_ENABLE_DEFAULT 0x00000000
-
-/***************************************************************************
- *QUEUE2_SHAPER_BUCKET_COUNT_SELECT - Queue 2 Bucket Count Select Register
- ***************************************************************************/
-/* SWITCH_CORE :: QUEUE2_SHAPER_BUCKET_COUNT_SELECT :: reserved_for_padding0 [31:16] */
-#define BCHP_SWITCH_CORE_QUEUE2_SHAPER_BUCKET_COUNT_SELECT_reserved_for_padding0_MASK 0xffff0000
-#define BCHP_SWITCH_CORE_QUEUE2_SHAPER_BUCKET_COUNT_SELECT_reserved_for_padding0_SHIFT 16
-
-/* SWITCH_CORE :: QUEUE2_SHAPER_BUCKET_COUNT_SELECT :: SWITCH_RESV [15:09] */
-#define BCHP_SWITCH_CORE_QUEUE2_SHAPER_BUCKET_COUNT_SELECT_SWITCH_RESV_MASK 0x0000fe00
-#define BCHP_SWITCH_CORE_QUEUE2_SHAPER_BUCKET_COUNT_SELECT_SWITCH_RESV_SHIFT 9
-#define BCHP_SWITCH_CORE_QUEUE2_SHAPER_BUCKET_COUNT_SELECT_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: QUEUE2_SHAPER_BUCKET_COUNT_SELECT :: QUEUE2_SHAPER_BUCKET_COUNT_SELECT [08:00] */
-#define BCHP_SWITCH_CORE_QUEUE2_SHAPER_BUCKET_COUNT_SELECT_QUEUE2_SHAPER_BUCKET_COUNT_SELECT_MASK 0x000001ff
-#define BCHP_SWITCH_CORE_QUEUE2_SHAPER_BUCKET_COUNT_SELECT_QUEUE2_SHAPER_BUCKET_COUNT_SELECT_SHIFT 0
-#define BCHP_SWITCH_CORE_QUEUE2_SHAPER_BUCKET_COUNT_SELECT_QUEUE2_SHAPER_BUCKET_COUNT_SELECT_DEFAULT 0x00000000
-
-/***************************************************************************
- *QUEUE2_SHAPER_BLOCKING - Queue 2 Shaper Blocking Control Register
- ***************************************************************************/
-/* SWITCH_CORE :: QUEUE2_SHAPER_BLOCKING :: reserved_for_padding0 [31:16] */
-#define BCHP_SWITCH_CORE_QUEUE2_SHAPER_BLOCKING_reserved_for_padding0_MASK 0xffff0000
-#define BCHP_SWITCH_CORE_QUEUE2_SHAPER_BLOCKING_reserved_for_padding0_SHIFT 16
-
-/* SWITCH_CORE :: QUEUE2_SHAPER_BLOCKING :: SWITCH_RESV [15:09] */
-#define BCHP_SWITCH_CORE_QUEUE2_SHAPER_BLOCKING_SWITCH_RESV_MASK 0x0000fe00
-#define BCHP_SWITCH_CORE_QUEUE2_SHAPER_BLOCKING_SWITCH_RESV_SHIFT 9
-#define BCHP_SWITCH_CORE_QUEUE2_SHAPER_BLOCKING_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: QUEUE2_SHAPER_BLOCKING :: QUEUE2_SHAPER_BLOCKING [08:00] */
-#define BCHP_SWITCH_CORE_QUEUE2_SHAPER_BLOCKING_QUEUE2_SHAPER_BLOCKING_MASK 0x000001ff
-#define BCHP_SWITCH_CORE_QUEUE2_SHAPER_BLOCKING_QUEUE2_SHAPER_BLOCKING_SHIFT 0
-#define BCHP_SWITCH_CORE_QUEUE2_SHAPER_BLOCKING_QUEUE2_SHAPER_BLOCKING_DEFAULT 0x00000000
-
-/***************************************************************************
- *PN_QUEUE3_MAX_REFRESH_Port_0 - Port N, Byte-based Queue 3 Shaping Rate Configure Register
- ***************************************************************************/
-/* SWITCH_CORE :: PN_QUEUE3_MAX_REFRESH_Port_0 :: SWITCH_RESV [31:18] */
-#define BCHP_SWITCH_CORE_PN_QUEUE3_MAX_REFRESH_Port_0_SWITCH_RESV_MASK 0xfffc0000
-#define BCHP_SWITCH_CORE_PN_QUEUE3_MAX_REFRESH_Port_0_SWITCH_RESV_SHIFT 18
-#define BCHP_SWITCH_CORE_PN_QUEUE3_MAX_REFRESH_Port_0_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: PN_QUEUE3_MAX_REFRESH_Port_0 :: MAX_REFRESH [17:00] */
-#define BCHP_SWITCH_CORE_PN_QUEUE3_MAX_REFRESH_Port_0_MAX_REFRESH_MASK 0x0003ffff
-#define BCHP_SWITCH_CORE_PN_QUEUE3_MAX_REFRESH_Port_0_MAX_REFRESH_SHIFT 0
-#define BCHP_SWITCH_CORE_PN_QUEUE3_MAX_REFRESH_Port_0_MAX_REFRESH_DEFAULT 0x00000000
-
-/***************************************************************************
- *PN_QUEUE3_MAX_REFRESH_Port_1 - Port N, Byte-based Queue 3 Shaping Rate Configure Register
- ***************************************************************************/
-/* SWITCH_CORE :: PN_QUEUE3_MAX_REFRESH_Port_1 :: SWITCH_RESV [31:18] */
-#define BCHP_SWITCH_CORE_PN_QUEUE3_MAX_REFRESH_Port_1_SWITCH_RESV_MASK 0xfffc0000
-#define BCHP_SWITCH_CORE_PN_QUEUE3_MAX_REFRESH_Port_1_SWITCH_RESV_SHIFT 18
-#define BCHP_SWITCH_CORE_PN_QUEUE3_MAX_REFRESH_Port_1_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: PN_QUEUE3_MAX_REFRESH_Port_1 :: MAX_REFRESH [17:00] */
-#define BCHP_SWITCH_CORE_PN_QUEUE3_MAX_REFRESH_Port_1_MAX_REFRESH_MASK 0x0003ffff
-#define BCHP_SWITCH_CORE_PN_QUEUE3_MAX_REFRESH_Port_1_MAX_REFRESH_SHIFT 0
-#define BCHP_SWITCH_CORE_PN_QUEUE3_MAX_REFRESH_Port_1_MAX_REFRESH_DEFAULT 0x00000000
-
-/***************************************************************************
- *PN_QUEUE3_MAX_REFRESH_Port_2 - Port N, Byte-based Queue 3 Shaping Rate Configure Register
- ***************************************************************************/
-/* SWITCH_CORE :: PN_QUEUE3_MAX_REFRESH_Port_2 :: SWITCH_RESV [31:18] */
-#define BCHP_SWITCH_CORE_PN_QUEUE3_MAX_REFRESH_Port_2_SWITCH_RESV_MASK 0xfffc0000
-#define BCHP_SWITCH_CORE_PN_QUEUE3_MAX_REFRESH_Port_2_SWITCH_RESV_SHIFT 18
-#define BCHP_SWITCH_CORE_PN_QUEUE3_MAX_REFRESH_Port_2_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: PN_QUEUE3_MAX_REFRESH_Port_2 :: MAX_REFRESH [17:00] */
-#define BCHP_SWITCH_CORE_PN_QUEUE3_MAX_REFRESH_Port_2_MAX_REFRESH_MASK 0x0003ffff
-#define BCHP_SWITCH_CORE_PN_QUEUE3_MAX_REFRESH_Port_2_MAX_REFRESH_SHIFT 0
-#define BCHP_SWITCH_CORE_PN_QUEUE3_MAX_REFRESH_Port_2_MAX_REFRESH_DEFAULT 0x00000000
-
-/***************************************************************************
- *PN_QUEUE3_MAX_REFRESH_Port_3 - Port N, Byte-based Queue 3 Shaping Rate Configure Register
- ***************************************************************************/
-/* SWITCH_CORE :: PN_QUEUE3_MAX_REFRESH_Port_3 :: SWITCH_RESV [31:18] */
-#define BCHP_SWITCH_CORE_PN_QUEUE3_MAX_REFRESH_Port_3_SWITCH_RESV_MASK 0xfffc0000
-#define BCHP_SWITCH_CORE_PN_QUEUE3_MAX_REFRESH_Port_3_SWITCH_RESV_SHIFT 18
-#define BCHP_SWITCH_CORE_PN_QUEUE3_MAX_REFRESH_Port_3_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: PN_QUEUE3_MAX_REFRESH_Port_3 :: MAX_REFRESH [17:00] */
-#define BCHP_SWITCH_CORE_PN_QUEUE3_MAX_REFRESH_Port_3_MAX_REFRESH_MASK 0x0003ffff
-#define BCHP_SWITCH_CORE_PN_QUEUE3_MAX_REFRESH_Port_3_MAX_REFRESH_SHIFT 0
-#define BCHP_SWITCH_CORE_PN_QUEUE3_MAX_REFRESH_Port_3_MAX_REFRESH_DEFAULT 0x00000000
-
-/***************************************************************************
- *PN_QUEUE3_MAX_REFRESH_Port_4 - Port N, Byte-based Queue 3 Shaping Rate Configure Register
- ***************************************************************************/
-/* SWITCH_CORE :: PN_QUEUE3_MAX_REFRESH_Port_4 :: SWITCH_RESV [31:18] */
-#define BCHP_SWITCH_CORE_PN_QUEUE3_MAX_REFRESH_Port_4_SWITCH_RESV_MASK 0xfffc0000
-#define BCHP_SWITCH_CORE_PN_QUEUE3_MAX_REFRESH_Port_4_SWITCH_RESV_SHIFT 18
-#define BCHP_SWITCH_CORE_PN_QUEUE3_MAX_REFRESH_Port_4_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: PN_QUEUE3_MAX_REFRESH_Port_4 :: MAX_REFRESH [17:00] */
-#define BCHP_SWITCH_CORE_PN_QUEUE3_MAX_REFRESH_Port_4_MAX_REFRESH_MASK 0x0003ffff
-#define BCHP_SWITCH_CORE_PN_QUEUE3_MAX_REFRESH_Port_4_MAX_REFRESH_SHIFT 0
-#define BCHP_SWITCH_CORE_PN_QUEUE3_MAX_REFRESH_Port_4_MAX_REFRESH_DEFAULT 0x00000000
-
-/***************************************************************************
- *PN_QUEUE3_MAX_REFRESH_Port_5 - Port N, Byte-based Queue 3 Shaping Rate Configure Register
- ***************************************************************************/
-/* SWITCH_CORE :: PN_QUEUE3_MAX_REFRESH_Port_5 :: SWITCH_RESV [31:18] */
-#define BCHP_SWITCH_CORE_PN_QUEUE3_MAX_REFRESH_Port_5_SWITCH_RESV_MASK 0xfffc0000
-#define BCHP_SWITCH_CORE_PN_QUEUE3_MAX_REFRESH_Port_5_SWITCH_RESV_SHIFT 18
-#define BCHP_SWITCH_CORE_PN_QUEUE3_MAX_REFRESH_Port_5_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: PN_QUEUE3_MAX_REFRESH_Port_5 :: MAX_REFRESH [17:00] */
-#define BCHP_SWITCH_CORE_PN_QUEUE3_MAX_REFRESH_Port_5_MAX_REFRESH_MASK 0x0003ffff
-#define BCHP_SWITCH_CORE_PN_QUEUE3_MAX_REFRESH_Port_5_MAX_REFRESH_SHIFT 0
-#define BCHP_SWITCH_CORE_PN_QUEUE3_MAX_REFRESH_Port_5_MAX_REFRESH_DEFAULT 0x00000000
-
-/***************************************************************************
- *P7_QUEUE3_MAX_REFRESH - Port 7, Byte-based Queue 3 Shaping Rate Configure Register
- ***************************************************************************/
-/* SWITCH_CORE :: P7_QUEUE3_MAX_REFRESH :: SWITCH_RESV [31:18] */
-#define BCHP_SWITCH_CORE_P7_QUEUE3_MAX_REFRESH_SWITCH_RESV_MASK 0xfffc0000
-#define BCHP_SWITCH_CORE_P7_QUEUE3_MAX_REFRESH_SWITCH_RESV_SHIFT 18
-#define BCHP_SWITCH_CORE_P7_QUEUE3_MAX_REFRESH_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: P7_QUEUE3_MAX_REFRESH :: MAX_REFRESH [17:00] */
-#define BCHP_SWITCH_CORE_P7_QUEUE3_MAX_REFRESH_MAX_REFRESH_MASK 0x0003ffff
-#define BCHP_SWITCH_CORE_P7_QUEUE3_MAX_REFRESH_MAX_REFRESH_SHIFT 0
-#define BCHP_SWITCH_CORE_P7_QUEUE3_MAX_REFRESH_MAX_REFRESH_DEFAULT 0x00000000
-
-/***************************************************************************
- *IMP_QUEUE3_MAX_REFRESH - Port 8, Byte-based Queue 3 Shaping Rate Configure Register
- ***************************************************************************/
-/* SWITCH_CORE :: IMP_QUEUE3_MAX_REFRESH :: SWITCH_RESV [31:18] */
-#define BCHP_SWITCH_CORE_IMP_QUEUE3_MAX_REFRESH_SWITCH_RESV_MASK 0xfffc0000
-#define BCHP_SWITCH_CORE_IMP_QUEUE3_MAX_REFRESH_SWITCH_RESV_SHIFT 18
-#define BCHP_SWITCH_CORE_IMP_QUEUE3_MAX_REFRESH_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: IMP_QUEUE3_MAX_REFRESH :: MAX_REFRESH [17:00] */
-#define BCHP_SWITCH_CORE_IMP_QUEUE3_MAX_REFRESH_MAX_REFRESH_MASK 0x0003ffff
-#define BCHP_SWITCH_CORE_IMP_QUEUE3_MAX_REFRESH_MAX_REFRESH_SHIFT 0
-#define BCHP_SWITCH_CORE_IMP_QUEUE3_MAX_REFRESH_MAX_REFRESH_DEFAULT 0x00000000
-
-/***************************************************************************
- *PN_QUEUE3_MAX_THD_SEL_Port_0 - Port N, Byte-based Queue 3 Burst Size Configure Register
- ***************************************************************************/
-/* SWITCH_CORE :: PN_QUEUE3_MAX_THD_SEL_Port_0 :: SWITCH_RESV [31:18] */
-#define BCHP_SWITCH_CORE_PN_QUEUE3_MAX_THD_SEL_Port_0_SWITCH_RESV_MASK 0xfffc0000
-#define BCHP_SWITCH_CORE_PN_QUEUE3_MAX_THD_SEL_Port_0_SWITCH_RESV_SHIFT 18
-#define BCHP_SWITCH_CORE_PN_QUEUE3_MAX_THD_SEL_Port_0_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: PN_QUEUE3_MAX_THD_SEL_Port_0 :: MAX_THD_SEL [17:00] */
-#define BCHP_SWITCH_CORE_PN_QUEUE3_MAX_THD_SEL_Port_0_MAX_THD_SEL_MASK 0x0003ffff
-#define BCHP_SWITCH_CORE_PN_QUEUE3_MAX_THD_SEL_Port_0_MAX_THD_SEL_SHIFT 0
-#define BCHP_SWITCH_CORE_PN_QUEUE3_MAX_THD_SEL_Port_0_MAX_THD_SEL_DEFAULT 0x00000000
-
-/***************************************************************************
- *PN_QUEUE3_MAX_THD_SEL_Port_1 - Port N, Byte-based Queue 3 Burst Size Configure Register
- ***************************************************************************/
-/* SWITCH_CORE :: PN_QUEUE3_MAX_THD_SEL_Port_1 :: SWITCH_RESV [31:18] */
-#define BCHP_SWITCH_CORE_PN_QUEUE3_MAX_THD_SEL_Port_1_SWITCH_RESV_MASK 0xfffc0000
-#define BCHP_SWITCH_CORE_PN_QUEUE3_MAX_THD_SEL_Port_1_SWITCH_RESV_SHIFT 18
-#define BCHP_SWITCH_CORE_PN_QUEUE3_MAX_THD_SEL_Port_1_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: PN_QUEUE3_MAX_THD_SEL_Port_1 :: MAX_THD_SEL [17:00] */
-#define BCHP_SWITCH_CORE_PN_QUEUE3_MAX_THD_SEL_Port_1_MAX_THD_SEL_MASK 0x0003ffff
-#define BCHP_SWITCH_CORE_PN_QUEUE3_MAX_THD_SEL_Port_1_MAX_THD_SEL_SHIFT 0
-#define BCHP_SWITCH_CORE_PN_QUEUE3_MAX_THD_SEL_Port_1_MAX_THD_SEL_DEFAULT 0x00000000
-
-/***************************************************************************
- *PN_QUEUE3_MAX_THD_SEL_Port_2 - Port N, Byte-based Queue 3 Burst Size Configure Register
- ***************************************************************************/
-/* SWITCH_CORE :: PN_QUEUE3_MAX_THD_SEL_Port_2 :: SWITCH_RESV [31:18] */
-#define BCHP_SWITCH_CORE_PN_QUEUE3_MAX_THD_SEL_Port_2_SWITCH_RESV_MASK 0xfffc0000
-#define BCHP_SWITCH_CORE_PN_QUEUE3_MAX_THD_SEL_Port_2_SWITCH_RESV_SHIFT 18
-#define BCHP_SWITCH_CORE_PN_QUEUE3_MAX_THD_SEL_Port_2_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: PN_QUEUE3_MAX_THD_SEL_Port_2 :: MAX_THD_SEL [17:00] */
-#define BCHP_SWITCH_CORE_PN_QUEUE3_MAX_THD_SEL_Port_2_MAX_THD_SEL_MASK 0x0003ffff
-#define BCHP_SWITCH_CORE_PN_QUEUE3_MAX_THD_SEL_Port_2_MAX_THD_SEL_SHIFT 0
-#define BCHP_SWITCH_CORE_PN_QUEUE3_MAX_THD_SEL_Port_2_MAX_THD_SEL_DEFAULT 0x00000000
-
-/***************************************************************************
- *PN_QUEUE3_MAX_THD_SEL_Port_3 - Port N, Byte-based Queue 3 Burst Size Configure Register
- ***************************************************************************/
-/* SWITCH_CORE :: PN_QUEUE3_MAX_THD_SEL_Port_3 :: SWITCH_RESV [31:18] */
-#define BCHP_SWITCH_CORE_PN_QUEUE3_MAX_THD_SEL_Port_3_SWITCH_RESV_MASK 0xfffc0000
-#define BCHP_SWITCH_CORE_PN_QUEUE3_MAX_THD_SEL_Port_3_SWITCH_RESV_SHIFT 18
-#define BCHP_SWITCH_CORE_PN_QUEUE3_MAX_THD_SEL_Port_3_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: PN_QUEUE3_MAX_THD_SEL_Port_3 :: MAX_THD_SEL [17:00] */
-#define BCHP_SWITCH_CORE_PN_QUEUE3_MAX_THD_SEL_Port_3_MAX_THD_SEL_MASK 0x0003ffff
-#define BCHP_SWITCH_CORE_PN_QUEUE3_MAX_THD_SEL_Port_3_MAX_THD_SEL_SHIFT 0
-#define BCHP_SWITCH_CORE_PN_QUEUE3_MAX_THD_SEL_Port_3_MAX_THD_SEL_DEFAULT 0x00000000
-
-/***************************************************************************
- *PN_QUEUE3_MAX_THD_SEL_Port_4 - Port N, Byte-based Queue 3 Burst Size Configure Register
- ***************************************************************************/
-/* SWITCH_CORE :: PN_QUEUE3_MAX_THD_SEL_Port_4 :: SWITCH_RESV [31:18] */
-#define BCHP_SWITCH_CORE_PN_QUEUE3_MAX_THD_SEL_Port_4_SWITCH_RESV_MASK 0xfffc0000
-#define BCHP_SWITCH_CORE_PN_QUEUE3_MAX_THD_SEL_Port_4_SWITCH_RESV_SHIFT 18
-#define BCHP_SWITCH_CORE_PN_QUEUE3_MAX_THD_SEL_Port_4_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: PN_QUEUE3_MAX_THD_SEL_Port_4 :: MAX_THD_SEL [17:00] */
-#define BCHP_SWITCH_CORE_PN_QUEUE3_MAX_THD_SEL_Port_4_MAX_THD_SEL_MASK 0x0003ffff
-#define BCHP_SWITCH_CORE_PN_QUEUE3_MAX_THD_SEL_Port_4_MAX_THD_SEL_SHIFT 0
-#define BCHP_SWITCH_CORE_PN_QUEUE3_MAX_THD_SEL_Port_4_MAX_THD_SEL_DEFAULT 0x00000000
-
-/***************************************************************************
- *PN_QUEUE3_MAX_THD_SEL_Port_5 - Port N, Byte-based Queue 3 Burst Size Configure Register
- ***************************************************************************/
-/* SWITCH_CORE :: PN_QUEUE3_MAX_THD_SEL_Port_5 :: SWITCH_RESV [31:18] */
-#define BCHP_SWITCH_CORE_PN_QUEUE3_MAX_THD_SEL_Port_5_SWITCH_RESV_MASK 0xfffc0000
-#define BCHP_SWITCH_CORE_PN_QUEUE3_MAX_THD_SEL_Port_5_SWITCH_RESV_SHIFT 18
-#define BCHP_SWITCH_CORE_PN_QUEUE3_MAX_THD_SEL_Port_5_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: PN_QUEUE3_MAX_THD_SEL_Port_5 :: MAX_THD_SEL [17:00] */
-#define BCHP_SWITCH_CORE_PN_QUEUE3_MAX_THD_SEL_Port_5_MAX_THD_SEL_MASK 0x0003ffff
-#define BCHP_SWITCH_CORE_PN_QUEUE3_MAX_THD_SEL_Port_5_MAX_THD_SEL_SHIFT 0
-#define BCHP_SWITCH_CORE_PN_QUEUE3_MAX_THD_SEL_Port_5_MAX_THD_SEL_DEFAULT 0x00000000
-
-/***************************************************************************
- *P7_QUEUE3_MAX_THD_SEL - Port 7, Byte-based Queue 3 Burst Size Configure Register
- ***************************************************************************/
-/* SWITCH_CORE :: P7_QUEUE3_MAX_THD_SEL :: SWITCH_RESV [31:18] */
-#define BCHP_SWITCH_CORE_P7_QUEUE3_MAX_THD_SEL_SWITCH_RESV_MASK 0xfffc0000
-#define BCHP_SWITCH_CORE_P7_QUEUE3_MAX_THD_SEL_SWITCH_RESV_SHIFT 18
-#define BCHP_SWITCH_CORE_P7_QUEUE3_MAX_THD_SEL_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: P7_QUEUE3_MAX_THD_SEL :: MAX_THD_SEL [17:00] */
-#define BCHP_SWITCH_CORE_P7_QUEUE3_MAX_THD_SEL_MAX_THD_SEL_MASK 0x0003ffff
-#define BCHP_SWITCH_CORE_P7_QUEUE3_MAX_THD_SEL_MAX_THD_SEL_SHIFT 0
-#define BCHP_SWITCH_CORE_P7_QUEUE3_MAX_THD_SEL_MAX_THD_SEL_DEFAULT 0x00000000
-
-/***************************************************************************
- *IMP_QUEUE3_MAX_THD_SEL - Port 8, Byte-based Queue 3 Burst Size Configure Register
- ***************************************************************************/
-/* SWITCH_CORE :: IMP_QUEUE3_MAX_THD_SEL :: SWITCH_RESV [31:18] */
-#define BCHP_SWITCH_CORE_IMP_QUEUE3_MAX_THD_SEL_SWITCH_RESV_MASK 0xfffc0000
-#define BCHP_SWITCH_CORE_IMP_QUEUE3_MAX_THD_SEL_SWITCH_RESV_SHIFT 18
-#define BCHP_SWITCH_CORE_IMP_QUEUE3_MAX_THD_SEL_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: IMP_QUEUE3_MAX_THD_SEL :: MAX_THD_SEL [17:00] */
-#define BCHP_SWITCH_CORE_IMP_QUEUE3_MAX_THD_SEL_MAX_THD_SEL_MASK 0x0003ffff
-#define BCHP_SWITCH_CORE_IMP_QUEUE3_MAX_THD_SEL_MAX_THD_SEL_SHIFT 0
-#define BCHP_SWITCH_CORE_IMP_QUEUE3_MAX_THD_SEL_MAX_THD_SEL_DEFAULT 0x00000000
-
-/***************************************************************************
- *PN_QUEUE3_SHAPER_STS_Port_0 - Port N, Queue 3 Shaper Status Register
- ***************************************************************************/
-/* SWITCH_CORE :: PN_QUEUE3_SHAPER_STS_Port_0 :: IN_PROFILE_FLAG [31:31] */
-#define BCHP_SWITCH_CORE_PN_QUEUE3_SHAPER_STS_Port_0_IN_PROFILE_FLAG_MASK 0x80000000
-#define BCHP_SWITCH_CORE_PN_QUEUE3_SHAPER_STS_Port_0_IN_PROFILE_FLAG_SHIFT 31
-#define BCHP_SWITCH_CORE_PN_QUEUE3_SHAPER_STS_Port_0_IN_PROFILE_FLAG_DEFAULT 0x00000001
-
-/* SWITCH_CORE :: PN_QUEUE3_SHAPER_STS_Port_0 :: SWITCH_RESV [30:29] */
-#define BCHP_SWITCH_CORE_PN_QUEUE3_SHAPER_STS_Port_0_SWITCH_RESV_MASK 0x60000000
-#define BCHP_SWITCH_CORE_PN_QUEUE3_SHAPER_STS_Port_0_SWITCH_RESV_SHIFT 29
-#define BCHP_SWITCH_CORE_PN_QUEUE3_SHAPER_STS_Port_0_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: PN_QUEUE3_SHAPER_STS_Port_0 :: BUCKET_CNT [28:00] */
-#define BCHP_SWITCH_CORE_PN_QUEUE3_SHAPER_STS_Port_0_BUCKET_CNT_MASK 0x1fffffff
-#define BCHP_SWITCH_CORE_PN_QUEUE3_SHAPER_STS_Port_0_BUCKET_CNT_SHIFT 0
-#define BCHP_SWITCH_CORE_PN_QUEUE3_SHAPER_STS_Port_0_BUCKET_CNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *PN_QUEUE3_SHAPER_STS_Port_1 - Port N, Queue 3 Shaper Status Register
- ***************************************************************************/
-/* SWITCH_CORE :: PN_QUEUE3_SHAPER_STS_Port_1 :: IN_PROFILE_FLAG [31:31] */
-#define BCHP_SWITCH_CORE_PN_QUEUE3_SHAPER_STS_Port_1_IN_PROFILE_FLAG_MASK 0x80000000
-#define BCHP_SWITCH_CORE_PN_QUEUE3_SHAPER_STS_Port_1_IN_PROFILE_FLAG_SHIFT 31
-#define BCHP_SWITCH_CORE_PN_QUEUE3_SHAPER_STS_Port_1_IN_PROFILE_FLAG_DEFAULT 0x00000001
-
-/* SWITCH_CORE :: PN_QUEUE3_SHAPER_STS_Port_1 :: SWITCH_RESV [30:29] */
-#define BCHP_SWITCH_CORE_PN_QUEUE3_SHAPER_STS_Port_1_SWITCH_RESV_MASK 0x60000000
-#define BCHP_SWITCH_CORE_PN_QUEUE3_SHAPER_STS_Port_1_SWITCH_RESV_SHIFT 29
-#define BCHP_SWITCH_CORE_PN_QUEUE3_SHAPER_STS_Port_1_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: PN_QUEUE3_SHAPER_STS_Port_1 :: BUCKET_CNT [28:00] */
-#define BCHP_SWITCH_CORE_PN_QUEUE3_SHAPER_STS_Port_1_BUCKET_CNT_MASK 0x1fffffff
-#define BCHP_SWITCH_CORE_PN_QUEUE3_SHAPER_STS_Port_1_BUCKET_CNT_SHIFT 0
-#define BCHP_SWITCH_CORE_PN_QUEUE3_SHAPER_STS_Port_1_BUCKET_CNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *PN_QUEUE3_SHAPER_STS_Port_2 - Port N, Queue 3 Shaper Status Register
- ***************************************************************************/
-/* SWITCH_CORE :: PN_QUEUE3_SHAPER_STS_Port_2 :: IN_PROFILE_FLAG [31:31] */
-#define BCHP_SWITCH_CORE_PN_QUEUE3_SHAPER_STS_Port_2_IN_PROFILE_FLAG_MASK 0x80000000
-#define BCHP_SWITCH_CORE_PN_QUEUE3_SHAPER_STS_Port_2_IN_PROFILE_FLAG_SHIFT 31
-#define BCHP_SWITCH_CORE_PN_QUEUE3_SHAPER_STS_Port_2_IN_PROFILE_FLAG_DEFAULT 0x00000001
-
-/* SWITCH_CORE :: PN_QUEUE3_SHAPER_STS_Port_2 :: SWITCH_RESV [30:29] */
-#define BCHP_SWITCH_CORE_PN_QUEUE3_SHAPER_STS_Port_2_SWITCH_RESV_MASK 0x60000000
-#define BCHP_SWITCH_CORE_PN_QUEUE3_SHAPER_STS_Port_2_SWITCH_RESV_SHIFT 29
-#define BCHP_SWITCH_CORE_PN_QUEUE3_SHAPER_STS_Port_2_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: PN_QUEUE3_SHAPER_STS_Port_2 :: BUCKET_CNT [28:00] */
-#define BCHP_SWITCH_CORE_PN_QUEUE3_SHAPER_STS_Port_2_BUCKET_CNT_MASK 0x1fffffff
-#define BCHP_SWITCH_CORE_PN_QUEUE3_SHAPER_STS_Port_2_BUCKET_CNT_SHIFT 0
-#define BCHP_SWITCH_CORE_PN_QUEUE3_SHAPER_STS_Port_2_BUCKET_CNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *PN_QUEUE3_SHAPER_STS_Port_3 - Port N, Queue 3 Shaper Status Register
- ***************************************************************************/
-/* SWITCH_CORE :: PN_QUEUE3_SHAPER_STS_Port_3 :: IN_PROFILE_FLAG [31:31] */
-#define BCHP_SWITCH_CORE_PN_QUEUE3_SHAPER_STS_Port_3_IN_PROFILE_FLAG_MASK 0x80000000
-#define BCHP_SWITCH_CORE_PN_QUEUE3_SHAPER_STS_Port_3_IN_PROFILE_FLAG_SHIFT 31
-#define BCHP_SWITCH_CORE_PN_QUEUE3_SHAPER_STS_Port_3_IN_PROFILE_FLAG_DEFAULT 0x00000001
-
-/* SWITCH_CORE :: PN_QUEUE3_SHAPER_STS_Port_3 :: SWITCH_RESV [30:29] */
-#define BCHP_SWITCH_CORE_PN_QUEUE3_SHAPER_STS_Port_3_SWITCH_RESV_MASK 0x60000000
-#define BCHP_SWITCH_CORE_PN_QUEUE3_SHAPER_STS_Port_3_SWITCH_RESV_SHIFT 29
-#define BCHP_SWITCH_CORE_PN_QUEUE3_SHAPER_STS_Port_3_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: PN_QUEUE3_SHAPER_STS_Port_3 :: BUCKET_CNT [28:00] */
-#define BCHP_SWITCH_CORE_PN_QUEUE3_SHAPER_STS_Port_3_BUCKET_CNT_MASK 0x1fffffff
-#define BCHP_SWITCH_CORE_PN_QUEUE3_SHAPER_STS_Port_3_BUCKET_CNT_SHIFT 0
-#define BCHP_SWITCH_CORE_PN_QUEUE3_SHAPER_STS_Port_3_BUCKET_CNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *PN_QUEUE3_SHAPER_STS_Port_4 - Port N, Queue 3 Shaper Status Register
- ***************************************************************************/
-/* SWITCH_CORE :: PN_QUEUE3_SHAPER_STS_Port_4 :: IN_PROFILE_FLAG [31:31] */
-#define BCHP_SWITCH_CORE_PN_QUEUE3_SHAPER_STS_Port_4_IN_PROFILE_FLAG_MASK 0x80000000
-#define BCHP_SWITCH_CORE_PN_QUEUE3_SHAPER_STS_Port_4_IN_PROFILE_FLAG_SHIFT 31
-#define BCHP_SWITCH_CORE_PN_QUEUE3_SHAPER_STS_Port_4_IN_PROFILE_FLAG_DEFAULT 0x00000001
-
-/* SWITCH_CORE :: PN_QUEUE3_SHAPER_STS_Port_4 :: SWITCH_RESV [30:29] */
-#define BCHP_SWITCH_CORE_PN_QUEUE3_SHAPER_STS_Port_4_SWITCH_RESV_MASK 0x60000000
-#define BCHP_SWITCH_CORE_PN_QUEUE3_SHAPER_STS_Port_4_SWITCH_RESV_SHIFT 29
-#define BCHP_SWITCH_CORE_PN_QUEUE3_SHAPER_STS_Port_4_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: PN_QUEUE3_SHAPER_STS_Port_4 :: BUCKET_CNT [28:00] */
-#define BCHP_SWITCH_CORE_PN_QUEUE3_SHAPER_STS_Port_4_BUCKET_CNT_MASK 0x1fffffff
-#define BCHP_SWITCH_CORE_PN_QUEUE3_SHAPER_STS_Port_4_BUCKET_CNT_SHIFT 0
-#define BCHP_SWITCH_CORE_PN_QUEUE3_SHAPER_STS_Port_4_BUCKET_CNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *PN_QUEUE3_SHAPER_STS_Port_5 - Port N, Queue 3 Shaper Status Register
- ***************************************************************************/
-/* SWITCH_CORE :: PN_QUEUE3_SHAPER_STS_Port_5 :: IN_PROFILE_FLAG [31:31] */
-#define BCHP_SWITCH_CORE_PN_QUEUE3_SHAPER_STS_Port_5_IN_PROFILE_FLAG_MASK 0x80000000
-#define BCHP_SWITCH_CORE_PN_QUEUE3_SHAPER_STS_Port_5_IN_PROFILE_FLAG_SHIFT 31
-#define BCHP_SWITCH_CORE_PN_QUEUE3_SHAPER_STS_Port_5_IN_PROFILE_FLAG_DEFAULT 0x00000001
-
-/* SWITCH_CORE :: PN_QUEUE3_SHAPER_STS_Port_5 :: SWITCH_RESV [30:29] */
-#define BCHP_SWITCH_CORE_PN_QUEUE3_SHAPER_STS_Port_5_SWITCH_RESV_MASK 0x60000000
-#define BCHP_SWITCH_CORE_PN_QUEUE3_SHAPER_STS_Port_5_SWITCH_RESV_SHIFT 29
-#define BCHP_SWITCH_CORE_PN_QUEUE3_SHAPER_STS_Port_5_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: PN_QUEUE3_SHAPER_STS_Port_5 :: BUCKET_CNT [28:00] */
-#define BCHP_SWITCH_CORE_PN_QUEUE3_SHAPER_STS_Port_5_BUCKET_CNT_MASK 0x1fffffff
-#define BCHP_SWITCH_CORE_PN_QUEUE3_SHAPER_STS_Port_5_BUCKET_CNT_SHIFT 0
-#define BCHP_SWITCH_CORE_PN_QUEUE3_SHAPER_STS_Port_5_BUCKET_CNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *P7_QUEUE3_SHAPER_STS - Port 7, Queue 3 Shaper Status Register
- ***************************************************************************/
-/* SWITCH_CORE :: P7_QUEUE3_SHAPER_STS :: IN_PROFILE_FLAG [31:31] */
-#define BCHP_SWITCH_CORE_P7_QUEUE3_SHAPER_STS_IN_PROFILE_FLAG_MASK 0x80000000
-#define BCHP_SWITCH_CORE_P7_QUEUE3_SHAPER_STS_IN_PROFILE_FLAG_SHIFT 31
-#define BCHP_SWITCH_CORE_P7_QUEUE3_SHAPER_STS_IN_PROFILE_FLAG_DEFAULT 0x00000001
-
-/* SWITCH_CORE :: P7_QUEUE3_SHAPER_STS :: SWITCH_RESV [30:29] */
-#define BCHP_SWITCH_CORE_P7_QUEUE3_SHAPER_STS_SWITCH_RESV_MASK 0x60000000
-#define BCHP_SWITCH_CORE_P7_QUEUE3_SHAPER_STS_SWITCH_RESV_SHIFT 29
-#define BCHP_SWITCH_CORE_P7_QUEUE3_SHAPER_STS_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: P7_QUEUE3_SHAPER_STS :: BUCKET_CNT [28:00] */
-#define BCHP_SWITCH_CORE_P7_QUEUE3_SHAPER_STS_BUCKET_CNT_MASK 0x1fffffff
-#define BCHP_SWITCH_CORE_P7_QUEUE3_SHAPER_STS_BUCKET_CNT_SHIFT 0
-#define BCHP_SWITCH_CORE_P7_QUEUE3_SHAPER_STS_BUCKET_CNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *IMP_QUEUE3_SHAPER_STS - Port 8, Queue 3 Shaper Status Register
- ***************************************************************************/
-/* SWITCH_CORE :: IMP_QUEUE3_SHAPER_STS :: IN_PROFILE_FLAG [31:31] */
-#define BCHP_SWITCH_CORE_IMP_QUEUE3_SHAPER_STS_IN_PROFILE_FLAG_MASK 0x80000000
-#define BCHP_SWITCH_CORE_IMP_QUEUE3_SHAPER_STS_IN_PROFILE_FLAG_SHIFT 31
-#define BCHP_SWITCH_CORE_IMP_QUEUE3_SHAPER_STS_IN_PROFILE_FLAG_DEFAULT 0x00000001
-
-/* SWITCH_CORE :: IMP_QUEUE3_SHAPER_STS :: SWITCH_RESV [30:29] */
-#define BCHP_SWITCH_CORE_IMP_QUEUE3_SHAPER_STS_SWITCH_RESV_MASK 0x60000000
-#define BCHP_SWITCH_CORE_IMP_QUEUE3_SHAPER_STS_SWITCH_RESV_SHIFT 29
-#define BCHP_SWITCH_CORE_IMP_QUEUE3_SHAPER_STS_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: IMP_QUEUE3_SHAPER_STS :: BUCKET_CNT [28:00] */
-#define BCHP_SWITCH_CORE_IMP_QUEUE3_SHAPER_STS_BUCKET_CNT_MASK 0x1fffffff
-#define BCHP_SWITCH_CORE_IMP_QUEUE3_SHAPER_STS_BUCKET_CNT_SHIFT 0
-#define BCHP_SWITCH_CORE_IMP_QUEUE3_SHAPER_STS_BUCKET_CNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *PN_QUEUE3_MAX_PACKET_REFRESH_Port_0 - Port N, Packet-based Queue 3 Shaping Rate Configure Register
- ***************************************************************************/
-/* SWITCH_CORE :: PN_QUEUE3_MAX_PACKET_REFRESH_Port_0 :: SWITCH_RESV [31:18] */
-#define BCHP_SWITCH_CORE_PN_QUEUE3_MAX_PACKET_REFRESH_Port_0_SWITCH_RESV_MASK 0xfffc0000
-#define BCHP_SWITCH_CORE_PN_QUEUE3_MAX_PACKET_REFRESH_Port_0_SWITCH_RESV_SHIFT 18
-#define BCHP_SWITCH_CORE_PN_QUEUE3_MAX_PACKET_REFRESH_Port_0_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: PN_QUEUE3_MAX_PACKET_REFRESH_Port_0 :: MAX_REFRESH [17:00] */
-#define BCHP_SWITCH_CORE_PN_QUEUE3_MAX_PACKET_REFRESH_Port_0_MAX_REFRESH_MASK 0x0003ffff
-#define BCHP_SWITCH_CORE_PN_QUEUE3_MAX_PACKET_REFRESH_Port_0_MAX_REFRESH_SHIFT 0
-#define BCHP_SWITCH_CORE_PN_QUEUE3_MAX_PACKET_REFRESH_Port_0_MAX_REFRESH_DEFAULT 0x00000000
-
-/***************************************************************************
- *PN_QUEUE3_MAX_PACKET_REFRESH_Port_1 - Port N, Packet-based Queue 3 Shaping Rate Configure Register
- ***************************************************************************/
-/* SWITCH_CORE :: PN_QUEUE3_MAX_PACKET_REFRESH_Port_1 :: SWITCH_RESV [31:18] */
-#define BCHP_SWITCH_CORE_PN_QUEUE3_MAX_PACKET_REFRESH_Port_1_SWITCH_RESV_MASK 0xfffc0000
-#define BCHP_SWITCH_CORE_PN_QUEUE3_MAX_PACKET_REFRESH_Port_1_SWITCH_RESV_SHIFT 18
-#define BCHP_SWITCH_CORE_PN_QUEUE3_MAX_PACKET_REFRESH_Port_1_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: PN_QUEUE3_MAX_PACKET_REFRESH_Port_1 :: MAX_REFRESH [17:00] */
-#define BCHP_SWITCH_CORE_PN_QUEUE3_MAX_PACKET_REFRESH_Port_1_MAX_REFRESH_MASK 0x0003ffff
-#define BCHP_SWITCH_CORE_PN_QUEUE3_MAX_PACKET_REFRESH_Port_1_MAX_REFRESH_SHIFT 0
-#define BCHP_SWITCH_CORE_PN_QUEUE3_MAX_PACKET_REFRESH_Port_1_MAX_REFRESH_DEFAULT 0x00000000
-
-/***************************************************************************
- *PN_QUEUE3_MAX_PACKET_REFRESH_Port_2 - Port N, Packet-based Queue 3 Shaping Rate Configure Register
- ***************************************************************************/
-/* SWITCH_CORE :: PN_QUEUE3_MAX_PACKET_REFRESH_Port_2 :: SWITCH_RESV [31:18] */
-#define BCHP_SWITCH_CORE_PN_QUEUE3_MAX_PACKET_REFRESH_Port_2_SWITCH_RESV_MASK 0xfffc0000
-#define BCHP_SWITCH_CORE_PN_QUEUE3_MAX_PACKET_REFRESH_Port_2_SWITCH_RESV_SHIFT 18
-#define BCHP_SWITCH_CORE_PN_QUEUE3_MAX_PACKET_REFRESH_Port_2_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: PN_QUEUE3_MAX_PACKET_REFRESH_Port_2 :: MAX_REFRESH [17:00] */
-#define BCHP_SWITCH_CORE_PN_QUEUE3_MAX_PACKET_REFRESH_Port_2_MAX_REFRESH_MASK 0x0003ffff
-#define BCHP_SWITCH_CORE_PN_QUEUE3_MAX_PACKET_REFRESH_Port_2_MAX_REFRESH_SHIFT 0
-#define BCHP_SWITCH_CORE_PN_QUEUE3_MAX_PACKET_REFRESH_Port_2_MAX_REFRESH_DEFAULT 0x00000000
-
-/***************************************************************************
- *PN_QUEUE3_MAX_PACKET_REFRESH_Port_3 - Port N, Packet-based Queue 3 Shaping Rate Configure Register
- ***************************************************************************/
-/* SWITCH_CORE :: PN_QUEUE3_MAX_PACKET_REFRESH_Port_3 :: SWITCH_RESV [31:18] */
-#define BCHP_SWITCH_CORE_PN_QUEUE3_MAX_PACKET_REFRESH_Port_3_SWITCH_RESV_MASK 0xfffc0000
-#define BCHP_SWITCH_CORE_PN_QUEUE3_MAX_PACKET_REFRESH_Port_3_SWITCH_RESV_SHIFT 18
-#define BCHP_SWITCH_CORE_PN_QUEUE3_MAX_PACKET_REFRESH_Port_3_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: PN_QUEUE3_MAX_PACKET_REFRESH_Port_3 :: MAX_REFRESH [17:00] */
-#define BCHP_SWITCH_CORE_PN_QUEUE3_MAX_PACKET_REFRESH_Port_3_MAX_REFRESH_MASK 0x0003ffff
-#define BCHP_SWITCH_CORE_PN_QUEUE3_MAX_PACKET_REFRESH_Port_3_MAX_REFRESH_SHIFT 0
-#define BCHP_SWITCH_CORE_PN_QUEUE3_MAX_PACKET_REFRESH_Port_3_MAX_REFRESH_DEFAULT 0x00000000
-
-/***************************************************************************
- *PN_QUEUE3_MAX_PACKET_REFRESH_Port_4 - Port N, Packet-based Queue 3 Shaping Rate Configure Register
- ***************************************************************************/
-/* SWITCH_CORE :: PN_QUEUE3_MAX_PACKET_REFRESH_Port_4 :: SWITCH_RESV [31:18] */
-#define BCHP_SWITCH_CORE_PN_QUEUE3_MAX_PACKET_REFRESH_Port_4_SWITCH_RESV_MASK 0xfffc0000
-#define BCHP_SWITCH_CORE_PN_QUEUE3_MAX_PACKET_REFRESH_Port_4_SWITCH_RESV_SHIFT 18
-#define BCHP_SWITCH_CORE_PN_QUEUE3_MAX_PACKET_REFRESH_Port_4_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: PN_QUEUE3_MAX_PACKET_REFRESH_Port_4 :: MAX_REFRESH [17:00] */
-#define BCHP_SWITCH_CORE_PN_QUEUE3_MAX_PACKET_REFRESH_Port_4_MAX_REFRESH_MASK 0x0003ffff
-#define BCHP_SWITCH_CORE_PN_QUEUE3_MAX_PACKET_REFRESH_Port_4_MAX_REFRESH_SHIFT 0
-#define BCHP_SWITCH_CORE_PN_QUEUE3_MAX_PACKET_REFRESH_Port_4_MAX_REFRESH_DEFAULT 0x00000000
-
-/***************************************************************************
- *PN_QUEUE3_MAX_PACKET_REFRESH_Port_5 - Port N, Packet-based Queue 3 Shaping Rate Configure Register
- ***************************************************************************/
-/* SWITCH_CORE :: PN_QUEUE3_MAX_PACKET_REFRESH_Port_5 :: SWITCH_RESV [31:18] */
-#define BCHP_SWITCH_CORE_PN_QUEUE3_MAX_PACKET_REFRESH_Port_5_SWITCH_RESV_MASK 0xfffc0000
-#define BCHP_SWITCH_CORE_PN_QUEUE3_MAX_PACKET_REFRESH_Port_5_SWITCH_RESV_SHIFT 18
-#define BCHP_SWITCH_CORE_PN_QUEUE3_MAX_PACKET_REFRESH_Port_5_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: PN_QUEUE3_MAX_PACKET_REFRESH_Port_5 :: MAX_REFRESH [17:00] */
-#define BCHP_SWITCH_CORE_PN_QUEUE3_MAX_PACKET_REFRESH_Port_5_MAX_REFRESH_MASK 0x0003ffff
-#define BCHP_SWITCH_CORE_PN_QUEUE3_MAX_PACKET_REFRESH_Port_5_MAX_REFRESH_SHIFT 0
-#define BCHP_SWITCH_CORE_PN_QUEUE3_MAX_PACKET_REFRESH_Port_5_MAX_REFRESH_DEFAULT 0x00000000
-
-/***************************************************************************
- *P7_QUEUE3_MAX_PACKET_REFRESH - Port 7, Packet-based Queue 3 Shaping Rate Configure Register
- ***************************************************************************/
-/* SWITCH_CORE :: P7_QUEUE3_MAX_PACKET_REFRESH :: SWITCH_RESV [31:18] */
-#define BCHP_SWITCH_CORE_P7_QUEUE3_MAX_PACKET_REFRESH_SWITCH_RESV_MASK 0xfffc0000
-#define BCHP_SWITCH_CORE_P7_QUEUE3_MAX_PACKET_REFRESH_SWITCH_RESV_SHIFT 18
-#define BCHP_SWITCH_CORE_P7_QUEUE3_MAX_PACKET_REFRESH_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: P7_QUEUE3_MAX_PACKET_REFRESH :: MAX_REFRESH [17:00] */
-#define BCHP_SWITCH_CORE_P7_QUEUE3_MAX_PACKET_REFRESH_MAX_REFRESH_MASK 0x0003ffff
-#define BCHP_SWITCH_CORE_P7_QUEUE3_MAX_PACKET_REFRESH_MAX_REFRESH_SHIFT 0
-#define BCHP_SWITCH_CORE_P7_QUEUE3_MAX_PACKET_REFRESH_MAX_REFRESH_DEFAULT 0x00000000
-
-/***************************************************************************
- *IMP_QUEUE3_MAX_PACKET_REFRESH - Port 8, Packet-based Queue 3 Shaping Rate Configure Register
- ***************************************************************************/
-/* SWITCH_CORE :: IMP_QUEUE3_MAX_PACKET_REFRESH :: SWITCH_RESV [31:18] */
-#define BCHP_SWITCH_CORE_IMP_QUEUE3_MAX_PACKET_REFRESH_SWITCH_RESV_MASK 0xfffc0000
-#define BCHP_SWITCH_CORE_IMP_QUEUE3_MAX_PACKET_REFRESH_SWITCH_RESV_SHIFT 18
-#define BCHP_SWITCH_CORE_IMP_QUEUE3_MAX_PACKET_REFRESH_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: IMP_QUEUE3_MAX_PACKET_REFRESH :: MAX_REFRESH [17:00] */
-#define BCHP_SWITCH_CORE_IMP_QUEUE3_MAX_PACKET_REFRESH_MAX_REFRESH_MASK 0x0003ffff
-#define BCHP_SWITCH_CORE_IMP_QUEUE3_MAX_PACKET_REFRESH_MAX_REFRESH_SHIFT 0
-#define BCHP_SWITCH_CORE_IMP_QUEUE3_MAX_PACKET_REFRESH_MAX_REFRESH_DEFAULT 0x00000000
-
-/***************************************************************************
- *EGRESS_SHAPER_Q3_CONFIG_REG_SPARE0 - Spare 0 Register (Not2Release)
- ***************************************************************************/
-/* SWITCH_CORE :: EGRESS_SHAPER_Q3_CONFIG_REG_SPARE0 :: EGRESS_SHAPER_Q3_CONFIG_REG_SPARE0 [31:00] */
-#define BCHP_SWITCH_CORE_EGRESS_SHAPER_Q3_CONFIG_REG_SPARE0_EGRESS_SHAPER_Q3_CONFIG_REG_SPARE0_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_EGRESS_SHAPER_Q3_CONFIG_REG_SPARE0_EGRESS_SHAPER_Q3_CONFIG_REG_SPARE0_SHIFT 0
-#define BCHP_SWITCH_CORE_EGRESS_SHAPER_Q3_CONFIG_REG_SPARE0_EGRESS_SHAPER_Q3_CONFIG_REG_SPARE0_DEFAULT 0x00000000
-
-/***************************************************************************
- *EGRESS_SHAPER_Q3_CONFIG_REG_SPARE1 - Spare 1 Register (Not2Release)
- ***************************************************************************/
-/* SWITCH_CORE :: EGRESS_SHAPER_Q3_CONFIG_REG_SPARE1 :: EGRESS_SHAPER_Q3_CONFIG_REG_SPARE1 [31:00] */
-#define BCHP_SWITCH_CORE_EGRESS_SHAPER_Q3_CONFIG_REG_SPARE1_EGRESS_SHAPER_Q3_CONFIG_REG_SPARE1_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_EGRESS_SHAPER_Q3_CONFIG_REG_SPARE1_EGRESS_SHAPER_Q3_CONFIG_REG_SPARE1_SHIFT 0
-#define BCHP_SWITCH_CORE_EGRESS_SHAPER_Q3_CONFIG_REG_SPARE1_EGRESS_SHAPER_Q3_CONFIG_REG_SPARE1_DEFAULT 0x00000000
-
-/***************************************************************************
- *PN_QUEUE3_MAX_PACKET_THD_SEL_Port_0 - Port N, Packet-based Queue 3 Burst Size Configure Register
- ***************************************************************************/
-/* SWITCH_CORE :: PN_QUEUE3_MAX_PACKET_THD_SEL_Port_0 :: SWITCH_RESV [31:18] */
-#define BCHP_SWITCH_CORE_PN_QUEUE3_MAX_PACKET_THD_SEL_Port_0_SWITCH_RESV_MASK 0xfffc0000
-#define BCHP_SWITCH_CORE_PN_QUEUE3_MAX_PACKET_THD_SEL_Port_0_SWITCH_RESV_SHIFT 18
-#define BCHP_SWITCH_CORE_PN_QUEUE3_MAX_PACKET_THD_SEL_Port_0_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: PN_QUEUE3_MAX_PACKET_THD_SEL_Port_0 :: MAX_THD_SEL [17:00] */
-#define BCHP_SWITCH_CORE_PN_QUEUE3_MAX_PACKET_THD_SEL_Port_0_MAX_THD_SEL_MASK 0x0003ffff
-#define BCHP_SWITCH_CORE_PN_QUEUE3_MAX_PACKET_THD_SEL_Port_0_MAX_THD_SEL_SHIFT 0
-#define BCHP_SWITCH_CORE_PN_QUEUE3_MAX_PACKET_THD_SEL_Port_0_MAX_THD_SEL_DEFAULT 0x00000000
-
-/***************************************************************************
- *PN_QUEUE3_MAX_PACKET_THD_SEL_Port_1 - Port N, Packet-based Queue 3 Burst Size Configure Register
- ***************************************************************************/
-/* SWITCH_CORE :: PN_QUEUE3_MAX_PACKET_THD_SEL_Port_1 :: SWITCH_RESV [31:18] */
-#define BCHP_SWITCH_CORE_PN_QUEUE3_MAX_PACKET_THD_SEL_Port_1_SWITCH_RESV_MASK 0xfffc0000
-#define BCHP_SWITCH_CORE_PN_QUEUE3_MAX_PACKET_THD_SEL_Port_1_SWITCH_RESV_SHIFT 18
-#define BCHP_SWITCH_CORE_PN_QUEUE3_MAX_PACKET_THD_SEL_Port_1_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: PN_QUEUE3_MAX_PACKET_THD_SEL_Port_1 :: MAX_THD_SEL [17:00] */
-#define BCHP_SWITCH_CORE_PN_QUEUE3_MAX_PACKET_THD_SEL_Port_1_MAX_THD_SEL_MASK 0x0003ffff
-#define BCHP_SWITCH_CORE_PN_QUEUE3_MAX_PACKET_THD_SEL_Port_1_MAX_THD_SEL_SHIFT 0
-#define BCHP_SWITCH_CORE_PN_QUEUE3_MAX_PACKET_THD_SEL_Port_1_MAX_THD_SEL_DEFAULT 0x00000000
-
-/***************************************************************************
- *PN_QUEUE3_MAX_PACKET_THD_SEL_Port_2 - Port N, Packet-based Queue 3 Burst Size Configure Register
- ***************************************************************************/
-/* SWITCH_CORE :: PN_QUEUE3_MAX_PACKET_THD_SEL_Port_2 :: SWITCH_RESV [31:18] */
-#define BCHP_SWITCH_CORE_PN_QUEUE3_MAX_PACKET_THD_SEL_Port_2_SWITCH_RESV_MASK 0xfffc0000
-#define BCHP_SWITCH_CORE_PN_QUEUE3_MAX_PACKET_THD_SEL_Port_2_SWITCH_RESV_SHIFT 18
-#define BCHP_SWITCH_CORE_PN_QUEUE3_MAX_PACKET_THD_SEL_Port_2_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: PN_QUEUE3_MAX_PACKET_THD_SEL_Port_2 :: MAX_THD_SEL [17:00] */
-#define BCHP_SWITCH_CORE_PN_QUEUE3_MAX_PACKET_THD_SEL_Port_2_MAX_THD_SEL_MASK 0x0003ffff
-#define BCHP_SWITCH_CORE_PN_QUEUE3_MAX_PACKET_THD_SEL_Port_2_MAX_THD_SEL_SHIFT 0
-#define BCHP_SWITCH_CORE_PN_QUEUE3_MAX_PACKET_THD_SEL_Port_2_MAX_THD_SEL_DEFAULT 0x00000000
-
-/***************************************************************************
- *PN_QUEUE3_MAX_PACKET_THD_SEL_Port_3 - Port N, Packet-based Queue 3 Burst Size Configure Register
- ***************************************************************************/
-/* SWITCH_CORE :: PN_QUEUE3_MAX_PACKET_THD_SEL_Port_3 :: SWITCH_RESV [31:18] */
-#define BCHP_SWITCH_CORE_PN_QUEUE3_MAX_PACKET_THD_SEL_Port_3_SWITCH_RESV_MASK 0xfffc0000
-#define BCHP_SWITCH_CORE_PN_QUEUE3_MAX_PACKET_THD_SEL_Port_3_SWITCH_RESV_SHIFT 18
-#define BCHP_SWITCH_CORE_PN_QUEUE3_MAX_PACKET_THD_SEL_Port_3_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: PN_QUEUE3_MAX_PACKET_THD_SEL_Port_3 :: MAX_THD_SEL [17:00] */
-#define BCHP_SWITCH_CORE_PN_QUEUE3_MAX_PACKET_THD_SEL_Port_3_MAX_THD_SEL_MASK 0x0003ffff
-#define BCHP_SWITCH_CORE_PN_QUEUE3_MAX_PACKET_THD_SEL_Port_3_MAX_THD_SEL_SHIFT 0
-#define BCHP_SWITCH_CORE_PN_QUEUE3_MAX_PACKET_THD_SEL_Port_3_MAX_THD_SEL_DEFAULT 0x00000000
-
-/***************************************************************************
- *PN_QUEUE3_MAX_PACKET_THD_SEL_Port_4 - Port N, Packet-based Queue 3 Burst Size Configure Register
- ***************************************************************************/
-/* SWITCH_CORE :: PN_QUEUE3_MAX_PACKET_THD_SEL_Port_4 :: SWITCH_RESV [31:18] */
-#define BCHP_SWITCH_CORE_PN_QUEUE3_MAX_PACKET_THD_SEL_Port_4_SWITCH_RESV_MASK 0xfffc0000
-#define BCHP_SWITCH_CORE_PN_QUEUE3_MAX_PACKET_THD_SEL_Port_4_SWITCH_RESV_SHIFT 18
-#define BCHP_SWITCH_CORE_PN_QUEUE3_MAX_PACKET_THD_SEL_Port_4_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: PN_QUEUE3_MAX_PACKET_THD_SEL_Port_4 :: MAX_THD_SEL [17:00] */
-#define BCHP_SWITCH_CORE_PN_QUEUE3_MAX_PACKET_THD_SEL_Port_4_MAX_THD_SEL_MASK 0x0003ffff
-#define BCHP_SWITCH_CORE_PN_QUEUE3_MAX_PACKET_THD_SEL_Port_4_MAX_THD_SEL_SHIFT 0
-#define BCHP_SWITCH_CORE_PN_QUEUE3_MAX_PACKET_THD_SEL_Port_4_MAX_THD_SEL_DEFAULT 0x00000000
-
-/***************************************************************************
- *PN_QUEUE3_MAX_PACKET_THD_SEL_Port_5 - Port N, Packet-based Queue 3 Burst Size Configure Register
- ***************************************************************************/
-/* SWITCH_CORE :: PN_QUEUE3_MAX_PACKET_THD_SEL_Port_5 :: SWITCH_RESV [31:18] */
-#define BCHP_SWITCH_CORE_PN_QUEUE3_MAX_PACKET_THD_SEL_Port_5_SWITCH_RESV_MASK 0xfffc0000
-#define BCHP_SWITCH_CORE_PN_QUEUE3_MAX_PACKET_THD_SEL_Port_5_SWITCH_RESV_SHIFT 18
-#define BCHP_SWITCH_CORE_PN_QUEUE3_MAX_PACKET_THD_SEL_Port_5_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: PN_QUEUE3_MAX_PACKET_THD_SEL_Port_5 :: MAX_THD_SEL [17:00] */
-#define BCHP_SWITCH_CORE_PN_QUEUE3_MAX_PACKET_THD_SEL_Port_5_MAX_THD_SEL_MASK 0x0003ffff
-#define BCHP_SWITCH_CORE_PN_QUEUE3_MAX_PACKET_THD_SEL_Port_5_MAX_THD_SEL_SHIFT 0
-#define BCHP_SWITCH_CORE_PN_QUEUE3_MAX_PACKET_THD_SEL_Port_5_MAX_THD_SEL_DEFAULT 0x00000000
-
-/***************************************************************************
- *P7_QUEUE3_MAX_PACKET_THD_SEL - Port 7, Packet-based Queue 3 Burst Size Configure Register
- ***************************************************************************/
-/* SWITCH_CORE :: P7_QUEUE3_MAX_PACKET_THD_SEL :: SWITCH_RESV [31:18] */
-#define BCHP_SWITCH_CORE_P7_QUEUE3_MAX_PACKET_THD_SEL_SWITCH_RESV_MASK 0xfffc0000
-#define BCHP_SWITCH_CORE_P7_QUEUE3_MAX_PACKET_THD_SEL_SWITCH_RESV_SHIFT 18
-#define BCHP_SWITCH_CORE_P7_QUEUE3_MAX_PACKET_THD_SEL_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: P7_QUEUE3_MAX_PACKET_THD_SEL :: MAX_THD_SEL [17:00] */
-#define BCHP_SWITCH_CORE_P7_QUEUE3_MAX_PACKET_THD_SEL_MAX_THD_SEL_MASK 0x0003ffff
-#define BCHP_SWITCH_CORE_P7_QUEUE3_MAX_PACKET_THD_SEL_MAX_THD_SEL_SHIFT 0
-#define BCHP_SWITCH_CORE_P7_QUEUE3_MAX_PACKET_THD_SEL_MAX_THD_SEL_DEFAULT 0x00000000
-
-/***************************************************************************
- *IMP_QUEUE3_MAX_PACKET_THD_SEL - Port 8, Packet-based Queue 3 Burst Size Configure Register
- ***************************************************************************/
-/* SWITCH_CORE :: IMP_QUEUE3_MAX_PACKET_THD_SEL :: SWITCH_RESV [31:18] */
-#define BCHP_SWITCH_CORE_IMP_QUEUE3_MAX_PACKET_THD_SEL_SWITCH_RESV_MASK 0xfffc0000
-#define BCHP_SWITCH_CORE_IMP_QUEUE3_MAX_PACKET_THD_SEL_SWITCH_RESV_SHIFT 18
-#define BCHP_SWITCH_CORE_IMP_QUEUE3_MAX_PACKET_THD_SEL_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: IMP_QUEUE3_MAX_PACKET_THD_SEL :: MAX_THD_SEL [17:00] */
-#define BCHP_SWITCH_CORE_IMP_QUEUE3_MAX_PACKET_THD_SEL_MAX_THD_SEL_MASK 0x0003ffff
-#define BCHP_SWITCH_CORE_IMP_QUEUE3_MAX_PACKET_THD_SEL_MAX_THD_SEL_SHIFT 0
-#define BCHP_SWITCH_CORE_IMP_QUEUE3_MAX_PACKET_THD_SEL_MAX_THD_SEL_DEFAULT 0x00000000
-
-/***************************************************************************
- *QUEUE3_AVB_SHAPING_MODE - Queue 3 AVB Shaping Mode Control Register
- ***************************************************************************/
-/* SWITCH_CORE :: QUEUE3_AVB_SHAPING_MODE :: reserved_for_padding0 [31:16] */
-#define BCHP_SWITCH_CORE_QUEUE3_AVB_SHAPING_MODE_reserved_for_padding0_MASK 0xffff0000
-#define BCHP_SWITCH_CORE_QUEUE3_AVB_SHAPING_MODE_reserved_for_padding0_SHIFT 16
-
-/* SWITCH_CORE :: QUEUE3_AVB_SHAPING_MODE :: SWITCH_RESV [15:09] */
-#define BCHP_SWITCH_CORE_QUEUE3_AVB_SHAPING_MODE_SWITCH_RESV_MASK 0x0000fe00
-#define BCHP_SWITCH_CORE_QUEUE3_AVB_SHAPING_MODE_SWITCH_RESV_SHIFT 9
-#define BCHP_SWITCH_CORE_QUEUE3_AVB_SHAPING_MODE_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: QUEUE3_AVB_SHAPING_MODE :: QUEUE3_AVB_SHAPING_MODE [08:00] */
-#define BCHP_SWITCH_CORE_QUEUE3_AVB_SHAPING_MODE_QUEUE3_AVB_SHAPING_MODE_MASK 0x000001ff
-#define BCHP_SWITCH_CORE_QUEUE3_AVB_SHAPING_MODE_QUEUE3_AVB_SHAPING_MODE_SHIFT 0
-#define BCHP_SWITCH_CORE_QUEUE3_AVB_SHAPING_MODE_QUEUE3_AVB_SHAPING_MODE_DEFAULT 0x00000000
-
-/***************************************************************************
- *QUEUE3_SHAPER_ENABLE - Queue 3 Shaper Enable Register
- ***************************************************************************/
-/* SWITCH_CORE :: QUEUE3_SHAPER_ENABLE :: reserved_for_padding0 [31:16] */
-#define BCHP_SWITCH_CORE_QUEUE3_SHAPER_ENABLE_reserved_for_padding0_MASK 0xffff0000
-#define BCHP_SWITCH_CORE_QUEUE3_SHAPER_ENABLE_reserved_for_padding0_SHIFT 16
-
-/* SWITCH_CORE :: QUEUE3_SHAPER_ENABLE :: SWITCH_RESV [15:09] */
-#define BCHP_SWITCH_CORE_QUEUE3_SHAPER_ENABLE_SWITCH_RESV_MASK 0x0000fe00
-#define BCHP_SWITCH_CORE_QUEUE3_SHAPER_ENABLE_SWITCH_RESV_SHIFT 9
-#define BCHP_SWITCH_CORE_QUEUE3_SHAPER_ENABLE_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: QUEUE3_SHAPER_ENABLE :: QUEUE3_SHAPER_ENABLE [08:00] */
-#define BCHP_SWITCH_CORE_QUEUE3_SHAPER_ENABLE_QUEUE3_SHAPER_ENABLE_MASK 0x000001ff
-#define BCHP_SWITCH_CORE_QUEUE3_SHAPER_ENABLE_QUEUE3_SHAPER_ENABLE_SHIFT 0
-#define BCHP_SWITCH_CORE_QUEUE3_SHAPER_ENABLE_QUEUE3_SHAPER_ENABLE_DEFAULT 0x00000000
-
-/***************************************************************************
- *QUEUE3_SHAPER_BUCKET_COUNT_SELECT - Queue 3 Bucket Count Select Register
- ***************************************************************************/
-/* SWITCH_CORE :: QUEUE3_SHAPER_BUCKET_COUNT_SELECT :: reserved_for_padding0 [31:16] */
-#define BCHP_SWITCH_CORE_QUEUE3_SHAPER_BUCKET_COUNT_SELECT_reserved_for_padding0_MASK 0xffff0000
-#define BCHP_SWITCH_CORE_QUEUE3_SHAPER_BUCKET_COUNT_SELECT_reserved_for_padding0_SHIFT 16
-
-/* SWITCH_CORE :: QUEUE3_SHAPER_BUCKET_COUNT_SELECT :: SWITCH_RESV [15:09] */
-#define BCHP_SWITCH_CORE_QUEUE3_SHAPER_BUCKET_COUNT_SELECT_SWITCH_RESV_MASK 0x0000fe00
-#define BCHP_SWITCH_CORE_QUEUE3_SHAPER_BUCKET_COUNT_SELECT_SWITCH_RESV_SHIFT 9
-#define BCHP_SWITCH_CORE_QUEUE3_SHAPER_BUCKET_COUNT_SELECT_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: QUEUE3_SHAPER_BUCKET_COUNT_SELECT :: QUEUE3_SHAPER_BUCKET_COUNT_SELECT [08:00] */
-#define BCHP_SWITCH_CORE_QUEUE3_SHAPER_BUCKET_COUNT_SELECT_QUEUE3_SHAPER_BUCKET_COUNT_SELECT_MASK 0x000001ff
-#define BCHP_SWITCH_CORE_QUEUE3_SHAPER_BUCKET_COUNT_SELECT_QUEUE3_SHAPER_BUCKET_COUNT_SELECT_SHIFT 0
-#define BCHP_SWITCH_CORE_QUEUE3_SHAPER_BUCKET_COUNT_SELECT_QUEUE3_SHAPER_BUCKET_COUNT_SELECT_DEFAULT 0x00000000
-
-/***************************************************************************
- *QUEUE3_SHAPER_BLOCKING - Queue 3 Shaper Blocking Control Register
- ***************************************************************************/
-/* SWITCH_CORE :: QUEUE3_SHAPER_BLOCKING :: reserved_for_padding0 [31:16] */
-#define BCHP_SWITCH_CORE_QUEUE3_SHAPER_BLOCKING_reserved_for_padding0_MASK 0xffff0000
-#define BCHP_SWITCH_CORE_QUEUE3_SHAPER_BLOCKING_reserved_for_padding0_SHIFT 16
-
-/* SWITCH_CORE :: QUEUE3_SHAPER_BLOCKING :: SWITCH_RESV [15:09] */
-#define BCHP_SWITCH_CORE_QUEUE3_SHAPER_BLOCKING_SWITCH_RESV_MASK 0x0000fe00
-#define BCHP_SWITCH_CORE_QUEUE3_SHAPER_BLOCKING_SWITCH_RESV_SHIFT 9
-#define BCHP_SWITCH_CORE_QUEUE3_SHAPER_BLOCKING_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: QUEUE3_SHAPER_BLOCKING :: QUEUE3_SHAPER_BLOCKING [08:00] */
-#define BCHP_SWITCH_CORE_QUEUE3_SHAPER_BLOCKING_QUEUE3_SHAPER_BLOCKING_MASK 0x000001ff
-#define BCHP_SWITCH_CORE_QUEUE3_SHAPER_BLOCKING_QUEUE3_SHAPER_BLOCKING_SHIFT 0
-#define BCHP_SWITCH_CORE_QUEUE3_SHAPER_BLOCKING_QUEUE3_SHAPER_BLOCKING_DEFAULT 0x00000000
-
-/***************************************************************************
- *PN_QUEUE4_MAX_REFRESH_Port_0 - Port N, Byte-based Queue 4 Shaping Rate Configure Register
- ***************************************************************************/
-/* SWITCH_CORE :: PN_QUEUE4_MAX_REFRESH_Port_0 :: SWITCH_RESV [31:18] */
-#define BCHP_SWITCH_CORE_PN_QUEUE4_MAX_REFRESH_Port_0_SWITCH_RESV_MASK 0xfffc0000
-#define BCHP_SWITCH_CORE_PN_QUEUE4_MAX_REFRESH_Port_0_SWITCH_RESV_SHIFT 18
-#define BCHP_SWITCH_CORE_PN_QUEUE4_MAX_REFRESH_Port_0_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: PN_QUEUE4_MAX_REFRESH_Port_0 :: MAX_REFRESH [17:00] */
-#define BCHP_SWITCH_CORE_PN_QUEUE4_MAX_REFRESH_Port_0_MAX_REFRESH_MASK 0x0003ffff
-#define BCHP_SWITCH_CORE_PN_QUEUE4_MAX_REFRESH_Port_0_MAX_REFRESH_SHIFT 0
-#define BCHP_SWITCH_CORE_PN_QUEUE4_MAX_REFRESH_Port_0_MAX_REFRESH_DEFAULT 0x00000000
-
-/***************************************************************************
- *PN_QUEUE4_MAX_REFRESH_Port_1 - Port N, Byte-based Queue 4 Shaping Rate Configure Register
- ***************************************************************************/
-/* SWITCH_CORE :: PN_QUEUE4_MAX_REFRESH_Port_1 :: SWITCH_RESV [31:18] */
-#define BCHP_SWITCH_CORE_PN_QUEUE4_MAX_REFRESH_Port_1_SWITCH_RESV_MASK 0xfffc0000
-#define BCHP_SWITCH_CORE_PN_QUEUE4_MAX_REFRESH_Port_1_SWITCH_RESV_SHIFT 18
-#define BCHP_SWITCH_CORE_PN_QUEUE4_MAX_REFRESH_Port_1_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: PN_QUEUE4_MAX_REFRESH_Port_1 :: MAX_REFRESH [17:00] */
-#define BCHP_SWITCH_CORE_PN_QUEUE4_MAX_REFRESH_Port_1_MAX_REFRESH_MASK 0x0003ffff
-#define BCHP_SWITCH_CORE_PN_QUEUE4_MAX_REFRESH_Port_1_MAX_REFRESH_SHIFT 0
-#define BCHP_SWITCH_CORE_PN_QUEUE4_MAX_REFRESH_Port_1_MAX_REFRESH_DEFAULT 0x00000000
-
-/***************************************************************************
- *PN_QUEUE4_MAX_REFRESH_Port_2 - Port N, Byte-based Queue 4 Shaping Rate Configure Register
- ***************************************************************************/
-/* SWITCH_CORE :: PN_QUEUE4_MAX_REFRESH_Port_2 :: SWITCH_RESV [31:18] */
-#define BCHP_SWITCH_CORE_PN_QUEUE4_MAX_REFRESH_Port_2_SWITCH_RESV_MASK 0xfffc0000
-#define BCHP_SWITCH_CORE_PN_QUEUE4_MAX_REFRESH_Port_2_SWITCH_RESV_SHIFT 18
-#define BCHP_SWITCH_CORE_PN_QUEUE4_MAX_REFRESH_Port_2_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: PN_QUEUE4_MAX_REFRESH_Port_2 :: MAX_REFRESH [17:00] */
-#define BCHP_SWITCH_CORE_PN_QUEUE4_MAX_REFRESH_Port_2_MAX_REFRESH_MASK 0x0003ffff
-#define BCHP_SWITCH_CORE_PN_QUEUE4_MAX_REFRESH_Port_2_MAX_REFRESH_SHIFT 0
-#define BCHP_SWITCH_CORE_PN_QUEUE4_MAX_REFRESH_Port_2_MAX_REFRESH_DEFAULT 0x00000000
-
-/***************************************************************************
- *PN_QUEUE4_MAX_REFRESH_Port_3 - Port N, Byte-based Queue 4 Shaping Rate Configure Register
- ***************************************************************************/
-/* SWITCH_CORE :: PN_QUEUE4_MAX_REFRESH_Port_3 :: SWITCH_RESV [31:18] */
-#define BCHP_SWITCH_CORE_PN_QUEUE4_MAX_REFRESH_Port_3_SWITCH_RESV_MASK 0xfffc0000
-#define BCHP_SWITCH_CORE_PN_QUEUE4_MAX_REFRESH_Port_3_SWITCH_RESV_SHIFT 18
-#define BCHP_SWITCH_CORE_PN_QUEUE4_MAX_REFRESH_Port_3_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: PN_QUEUE4_MAX_REFRESH_Port_3 :: MAX_REFRESH [17:00] */
-#define BCHP_SWITCH_CORE_PN_QUEUE4_MAX_REFRESH_Port_3_MAX_REFRESH_MASK 0x0003ffff
-#define BCHP_SWITCH_CORE_PN_QUEUE4_MAX_REFRESH_Port_3_MAX_REFRESH_SHIFT 0
-#define BCHP_SWITCH_CORE_PN_QUEUE4_MAX_REFRESH_Port_3_MAX_REFRESH_DEFAULT 0x00000000
-
-/***************************************************************************
- *PN_QUEUE4_MAX_REFRESH_Port_4 - Port N, Byte-based Queue 4 Shaping Rate Configure Register
- ***************************************************************************/
-/* SWITCH_CORE :: PN_QUEUE4_MAX_REFRESH_Port_4 :: SWITCH_RESV [31:18] */
-#define BCHP_SWITCH_CORE_PN_QUEUE4_MAX_REFRESH_Port_4_SWITCH_RESV_MASK 0xfffc0000
-#define BCHP_SWITCH_CORE_PN_QUEUE4_MAX_REFRESH_Port_4_SWITCH_RESV_SHIFT 18
-#define BCHP_SWITCH_CORE_PN_QUEUE4_MAX_REFRESH_Port_4_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: PN_QUEUE4_MAX_REFRESH_Port_4 :: MAX_REFRESH [17:00] */
-#define BCHP_SWITCH_CORE_PN_QUEUE4_MAX_REFRESH_Port_4_MAX_REFRESH_MASK 0x0003ffff
-#define BCHP_SWITCH_CORE_PN_QUEUE4_MAX_REFRESH_Port_4_MAX_REFRESH_SHIFT 0
-#define BCHP_SWITCH_CORE_PN_QUEUE4_MAX_REFRESH_Port_4_MAX_REFRESH_DEFAULT 0x00000000
-
-/***************************************************************************
- *PN_QUEUE4_MAX_REFRESH_Port_5 - Port N, Byte-based Queue 4 Shaping Rate Configure Register
- ***************************************************************************/
-/* SWITCH_CORE :: PN_QUEUE4_MAX_REFRESH_Port_5 :: SWITCH_RESV [31:18] */
-#define BCHP_SWITCH_CORE_PN_QUEUE4_MAX_REFRESH_Port_5_SWITCH_RESV_MASK 0xfffc0000
-#define BCHP_SWITCH_CORE_PN_QUEUE4_MAX_REFRESH_Port_5_SWITCH_RESV_SHIFT 18
-#define BCHP_SWITCH_CORE_PN_QUEUE4_MAX_REFRESH_Port_5_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: PN_QUEUE4_MAX_REFRESH_Port_5 :: MAX_REFRESH [17:00] */
-#define BCHP_SWITCH_CORE_PN_QUEUE4_MAX_REFRESH_Port_5_MAX_REFRESH_MASK 0x0003ffff
-#define BCHP_SWITCH_CORE_PN_QUEUE4_MAX_REFRESH_Port_5_MAX_REFRESH_SHIFT 0
-#define BCHP_SWITCH_CORE_PN_QUEUE4_MAX_REFRESH_Port_5_MAX_REFRESH_DEFAULT 0x00000000
-
-/***************************************************************************
- *P7_QUEUE4_MAX_REFRESH - Port 7, Byte-based Queue 4 Shaping Rate Configure Register
- ***************************************************************************/
-/* SWITCH_CORE :: P7_QUEUE4_MAX_REFRESH :: SWITCH_RESV [31:18] */
-#define BCHP_SWITCH_CORE_P7_QUEUE4_MAX_REFRESH_SWITCH_RESV_MASK 0xfffc0000
-#define BCHP_SWITCH_CORE_P7_QUEUE4_MAX_REFRESH_SWITCH_RESV_SHIFT 18
-#define BCHP_SWITCH_CORE_P7_QUEUE4_MAX_REFRESH_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: P7_QUEUE4_MAX_REFRESH :: MAX_REFRESH [17:00] */
-#define BCHP_SWITCH_CORE_P7_QUEUE4_MAX_REFRESH_MAX_REFRESH_MASK 0x0003ffff
-#define BCHP_SWITCH_CORE_P7_QUEUE4_MAX_REFRESH_MAX_REFRESH_SHIFT 0
-#define BCHP_SWITCH_CORE_P7_QUEUE4_MAX_REFRESH_MAX_REFRESH_DEFAULT 0x00000000
-
-/***************************************************************************
- *IMP_QUEUE4_MAX_REFRESH - Port 8, Byte-based Queue 4 Shaping Rate Configure Register
- ***************************************************************************/
-/* SWITCH_CORE :: IMP_QUEUE4_MAX_REFRESH :: SWITCH_RESV [31:18] */
-#define BCHP_SWITCH_CORE_IMP_QUEUE4_MAX_REFRESH_SWITCH_RESV_MASK 0xfffc0000
-#define BCHP_SWITCH_CORE_IMP_QUEUE4_MAX_REFRESH_SWITCH_RESV_SHIFT 18
-#define BCHP_SWITCH_CORE_IMP_QUEUE4_MAX_REFRESH_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: IMP_QUEUE4_MAX_REFRESH :: MAX_REFRESH [17:00] */
-#define BCHP_SWITCH_CORE_IMP_QUEUE4_MAX_REFRESH_MAX_REFRESH_MASK 0x0003ffff
-#define BCHP_SWITCH_CORE_IMP_QUEUE4_MAX_REFRESH_MAX_REFRESH_SHIFT 0
-#define BCHP_SWITCH_CORE_IMP_QUEUE4_MAX_REFRESH_MAX_REFRESH_DEFAULT 0x00000000
-
-/***************************************************************************
- *PN_QUEUE4_MAX_THD_SEL_Port_0 - Port N, Byte-based Queue 4 Burst Size Configure Register
- ***************************************************************************/
-/* SWITCH_CORE :: PN_QUEUE4_MAX_THD_SEL_Port_0 :: SWITCH_RESV [31:18] */
-#define BCHP_SWITCH_CORE_PN_QUEUE4_MAX_THD_SEL_Port_0_SWITCH_RESV_MASK 0xfffc0000
-#define BCHP_SWITCH_CORE_PN_QUEUE4_MAX_THD_SEL_Port_0_SWITCH_RESV_SHIFT 18
-#define BCHP_SWITCH_CORE_PN_QUEUE4_MAX_THD_SEL_Port_0_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: PN_QUEUE4_MAX_THD_SEL_Port_0 :: MAX_THD_SEL [17:00] */
-#define BCHP_SWITCH_CORE_PN_QUEUE4_MAX_THD_SEL_Port_0_MAX_THD_SEL_MASK 0x0003ffff
-#define BCHP_SWITCH_CORE_PN_QUEUE4_MAX_THD_SEL_Port_0_MAX_THD_SEL_SHIFT 0
-#define BCHP_SWITCH_CORE_PN_QUEUE4_MAX_THD_SEL_Port_0_MAX_THD_SEL_DEFAULT 0x00000000
-
-/***************************************************************************
- *PN_QUEUE4_MAX_THD_SEL_Port_1 - Port N, Byte-based Queue 4 Burst Size Configure Register
- ***************************************************************************/
-/* SWITCH_CORE :: PN_QUEUE4_MAX_THD_SEL_Port_1 :: SWITCH_RESV [31:18] */
-#define BCHP_SWITCH_CORE_PN_QUEUE4_MAX_THD_SEL_Port_1_SWITCH_RESV_MASK 0xfffc0000
-#define BCHP_SWITCH_CORE_PN_QUEUE4_MAX_THD_SEL_Port_1_SWITCH_RESV_SHIFT 18
-#define BCHP_SWITCH_CORE_PN_QUEUE4_MAX_THD_SEL_Port_1_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: PN_QUEUE4_MAX_THD_SEL_Port_1 :: MAX_THD_SEL [17:00] */
-#define BCHP_SWITCH_CORE_PN_QUEUE4_MAX_THD_SEL_Port_1_MAX_THD_SEL_MASK 0x0003ffff
-#define BCHP_SWITCH_CORE_PN_QUEUE4_MAX_THD_SEL_Port_1_MAX_THD_SEL_SHIFT 0
-#define BCHP_SWITCH_CORE_PN_QUEUE4_MAX_THD_SEL_Port_1_MAX_THD_SEL_DEFAULT 0x00000000
-
-/***************************************************************************
- *PN_QUEUE4_MAX_THD_SEL_Port_2 - Port N, Byte-based Queue 4 Burst Size Configure Register
- ***************************************************************************/
-/* SWITCH_CORE :: PN_QUEUE4_MAX_THD_SEL_Port_2 :: SWITCH_RESV [31:18] */
-#define BCHP_SWITCH_CORE_PN_QUEUE4_MAX_THD_SEL_Port_2_SWITCH_RESV_MASK 0xfffc0000
-#define BCHP_SWITCH_CORE_PN_QUEUE4_MAX_THD_SEL_Port_2_SWITCH_RESV_SHIFT 18
-#define BCHP_SWITCH_CORE_PN_QUEUE4_MAX_THD_SEL_Port_2_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: PN_QUEUE4_MAX_THD_SEL_Port_2 :: MAX_THD_SEL [17:00] */
-#define BCHP_SWITCH_CORE_PN_QUEUE4_MAX_THD_SEL_Port_2_MAX_THD_SEL_MASK 0x0003ffff
-#define BCHP_SWITCH_CORE_PN_QUEUE4_MAX_THD_SEL_Port_2_MAX_THD_SEL_SHIFT 0
-#define BCHP_SWITCH_CORE_PN_QUEUE4_MAX_THD_SEL_Port_2_MAX_THD_SEL_DEFAULT 0x00000000
-
-/***************************************************************************
- *PN_QUEUE4_MAX_THD_SEL_Port_3 - Port N, Byte-based Queue 4 Burst Size Configure Register
- ***************************************************************************/
-/* SWITCH_CORE :: PN_QUEUE4_MAX_THD_SEL_Port_3 :: SWITCH_RESV [31:18] */
-#define BCHP_SWITCH_CORE_PN_QUEUE4_MAX_THD_SEL_Port_3_SWITCH_RESV_MASK 0xfffc0000
-#define BCHP_SWITCH_CORE_PN_QUEUE4_MAX_THD_SEL_Port_3_SWITCH_RESV_SHIFT 18
-#define BCHP_SWITCH_CORE_PN_QUEUE4_MAX_THD_SEL_Port_3_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: PN_QUEUE4_MAX_THD_SEL_Port_3 :: MAX_THD_SEL [17:00] */
-#define BCHP_SWITCH_CORE_PN_QUEUE4_MAX_THD_SEL_Port_3_MAX_THD_SEL_MASK 0x0003ffff
-#define BCHP_SWITCH_CORE_PN_QUEUE4_MAX_THD_SEL_Port_3_MAX_THD_SEL_SHIFT 0
-#define BCHP_SWITCH_CORE_PN_QUEUE4_MAX_THD_SEL_Port_3_MAX_THD_SEL_DEFAULT 0x00000000
-
-/***************************************************************************
- *PN_QUEUE4_MAX_THD_SEL_Port_4 - Port N, Byte-based Queue 4 Burst Size Configure Register
- ***************************************************************************/
-/* SWITCH_CORE :: PN_QUEUE4_MAX_THD_SEL_Port_4 :: SWITCH_RESV [31:18] */
-#define BCHP_SWITCH_CORE_PN_QUEUE4_MAX_THD_SEL_Port_4_SWITCH_RESV_MASK 0xfffc0000
-#define BCHP_SWITCH_CORE_PN_QUEUE4_MAX_THD_SEL_Port_4_SWITCH_RESV_SHIFT 18
-#define BCHP_SWITCH_CORE_PN_QUEUE4_MAX_THD_SEL_Port_4_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: PN_QUEUE4_MAX_THD_SEL_Port_4 :: MAX_THD_SEL [17:00] */
-#define BCHP_SWITCH_CORE_PN_QUEUE4_MAX_THD_SEL_Port_4_MAX_THD_SEL_MASK 0x0003ffff
-#define BCHP_SWITCH_CORE_PN_QUEUE4_MAX_THD_SEL_Port_4_MAX_THD_SEL_SHIFT 0
-#define BCHP_SWITCH_CORE_PN_QUEUE4_MAX_THD_SEL_Port_4_MAX_THD_SEL_DEFAULT 0x00000000
-
-/***************************************************************************
- *PN_QUEUE4_MAX_THD_SEL_Port_5 - Port N, Byte-based Queue 4 Burst Size Configure Register
- ***************************************************************************/
-/* SWITCH_CORE :: PN_QUEUE4_MAX_THD_SEL_Port_5 :: SWITCH_RESV [31:18] */
-#define BCHP_SWITCH_CORE_PN_QUEUE4_MAX_THD_SEL_Port_5_SWITCH_RESV_MASK 0xfffc0000
-#define BCHP_SWITCH_CORE_PN_QUEUE4_MAX_THD_SEL_Port_5_SWITCH_RESV_SHIFT 18
-#define BCHP_SWITCH_CORE_PN_QUEUE4_MAX_THD_SEL_Port_5_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: PN_QUEUE4_MAX_THD_SEL_Port_5 :: MAX_THD_SEL [17:00] */
-#define BCHP_SWITCH_CORE_PN_QUEUE4_MAX_THD_SEL_Port_5_MAX_THD_SEL_MASK 0x0003ffff
-#define BCHP_SWITCH_CORE_PN_QUEUE4_MAX_THD_SEL_Port_5_MAX_THD_SEL_SHIFT 0
-#define BCHP_SWITCH_CORE_PN_QUEUE4_MAX_THD_SEL_Port_5_MAX_THD_SEL_DEFAULT 0x00000000
-
-/***************************************************************************
- *P7_QUEUE4_MAX_THD_SEL - Port 7, Byte-based Queue 4 Burst Size Configure Register
- ***************************************************************************/
-/* SWITCH_CORE :: P7_QUEUE4_MAX_THD_SEL :: SWITCH_RESV [31:18] */
-#define BCHP_SWITCH_CORE_P7_QUEUE4_MAX_THD_SEL_SWITCH_RESV_MASK 0xfffc0000
-#define BCHP_SWITCH_CORE_P7_QUEUE4_MAX_THD_SEL_SWITCH_RESV_SHIFT 18
-#define BCHP_SWITCH_CORE_P7_QUEUE4_MAX_THD_SEL_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: P7_QUEUE4_MAX_THD_SEL :: MAX_THD_SEL [17:00] */
-#define BCHP_SWITCH_CORE_P7_QUEUE4_MAX_THD_SEL_MAX_THD_SEL_MASK 0x0003ffff
-#define BCHP_SWITCH_CORE_P7_QUEUE4_MAX_THD_SEL_MAX_THD_SEL_SHIFT 0
-#define BCHP_SWITCH_CORE_P7_QUEUE4_MAX_THD_SEL_MAX_THD_SEL_DEFAULT 0x00000000
-
-/***************************************************************************
- *IMP_QUEUE4_MAX_THD_SEL - Port 8, Byte-based Queue 4 Burst Size Configure Register
- ***************************************************************************/
-/* SWITCH_CORE :: IMP_QUEUE4_MAX_THD_SEL :: SWITCH_RESV [31:18] */
-#define BCHP_SWITCH_CORE_IMP_QUEUE4_MAX_THD_SEL_SWITCH_RESV_MASK 0xfffc0000
-#define BCHP_SWITCH_CORE_IMP_QUEUE4_MAX_THD_SEL_SWITCH_RESV_SHIFT 18
-#define BCHP_SWITCH_CORE_IMP_QUEUE4_MAX_THD_SEL_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: IMP_QUEUE4_MAX_THD_SEL :: MAX_THD_SEL [17:00] */
-#define BCHP_SWITCH_CORE_IMP_QUEUE4_MAX_THD_SEL_MAX_THD_SEL_MASK 0x0003ffff
-#define BCHP_SWITCH_CORE_IMP_QUEUE4_MAX_THD_SEL_MAX_THD_SEL_SHIFT 0
-#define BCHP_SWITCH_CORE_IMP_QUEUE4_MAX_THD_SEL_MAX_THD_SEL_DEFAULT 0x00000000
-
-/***************************************************************************
- *PN_QUEUE4_SHAPER_STS_Port_0 - Port N, Queue 4 Shaper Status Register
- ***************************************************************************/
-/* SWITCH_CORE :: PN_QUEUE4_SHAPER_STS_Port_0 :: IN_PROFILE_FLAG [31:31] */
-#define BCHP_SWITCH_CORE_PN_QUEUE4_SHAPER_STS_Port_0_IN_PROFILE_FLAG_MASK 0x80000000
-#define BCHP_SWITCH_CORE_PN_QUEUE4_SHAPER_STS_Port_0_IN_PROFILE_FLAG_SHIFT 31
-#define BCHP_SWITCH_CORE_PN_QUEUE4_SHAPER_STS_Port_0_IN_PROFILE_FLAG_DEFAULT 0x00000001
-
-/* SWITCH_CORE :: PN_QUEUE4_SHAPER_STS_Port_0 :: SWITCH_RESV [30:29] */
-#define BCHP_SWITCH_CORE_PN_QUEUE4_SHAPER_STS_Port_0_SWITCH_RESV_MASK 0x60000000
-#define BCHP_SWITCH_CORE_PN_QUEUE4_SHAPER_STS_Port_0_SWITCH_RESV_SHIFT 29
-#define BCHP_SWITCH_CORE_PN_QUEUE4_SHAPER_STS_Port_0_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: PN_QUEUE4_SHAPER_STS_Port_0 :: BUCKET_CNT [28:00] */
-#define BCHP_SWITCH_CORE_PN_QUEUE4_SHAPER_STS_Port_0_BUCKET_CNT_MASK 0x1fffffff
-#define BCHP_SWITCH_CORE_PN_QUEUE4_SHAPER_STS_Port_0_BUCKET_CNT_SHIFT 0
-#define BCHP_SWITCH_CORE_PN_QUEUE4_SHAPER_STS_Port_0_BUCKET_CNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *PN_QUEUE4_SHAPER_STS_Port_1 - Port N, Queue 4 Shaper Status Register
- ***************************************************************************/
-/* SWITCH_CORE :: PN_QUEUE4_SHAPER_STS_Port_1 :: IN_PROFILE_FLAG [31:31] */
-#define BCHP_SWITCH_CORE_PN_QUEUE4_SHAPER_STS_Port_1_IN_PROFILE_FLAG_MASK 0x80000000
-#define BCHP_SWITCH_CORE_PN_QUEUE4_SHAPER_STS_Port_1_IN_PROFILE_FLAG_SHIFT 31
-#define BCHP_SWITCH_CORE_PN_QUEUE4_SHAPER_STS_Port_1_IN_PROFILE_FLAG_DEFAULT 0x00000001
-
-/* SWITCH_CORE :: PN_QUEUE4_SHAPER_STS_Port_1 :: SWITCH_RESV [30:29] */
-#define BCHP_SWITCH_CORE_PN_QUEUE4_SHAPER_STS_Port_1_SWITCH_RESV_MASK 0x60000000
-#define BCHP_SWITCH_CORE_PN_QUEUE4_SHAPER_STS_Port_1_SWITCH_RESV_SHIFT 29
-#define BCHP_SWITCH_CORE_PN_QUEUE4_SHAPER_STS_Port_1_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: PN_QUEUE4_SHAPER_STS_Port_1 :: BUCKET_CNT [28:00] */
-#define BCHP_SWITCH_CORE_PN_QUEUE4_SHAPER_STS_Port_1_BUCKET_CNT_MASK 0x1fffffff
-#define BCHP_SWITCH_CORE_PN_QUEUE4_SHAPER_STS_Port_1_BUCKET_CNT_SHIFT 0
-#define BCHP_SWITCH_CORE_PN_QUEUE4_SHAPER_STS_Port_1_BUCKET_CNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *PN_QUEUE4_SHAPER_STS_Port_2 - Port N, Queue 4 Shaper Status Register
- ***************************************************************************/
-/* SWITCH_CORE :: PN_QUEUE4_SHAPER_STS_Port_2 :: IN_PROFILE_FLAG [31:31] */
-#define BCHP_SWITCH_CORE_PN_QUEUE4_SHAPER_STS_Port_2_IN_PROFILE_FLAG_MASK 0x80000000
-#define BCHP_SWITCH_CORE_PN_QUEUE4_SHAPER_STS_Port_2_IN_PROFILE_FLAG_SHIFT 31
-#define BCHP_SWITCH_CORE_PN_QUEUE4_SHAPER_STS_Port_2_IN_PROFILE_FLAG_DEFAULT 0x00000001
-
-/* SWITCH_CORE :: PN_QUEUE4_SHAPER_STS_Port_2 :: SWITCH_RESV [30:29] */
-#define BCHP_SWITCH_CORE_PN_QUEUE4_SHAPER_STS_Port_2_SWITCH_RESV_MASK 0x60000000
-#define BCHP_SWITCH_CORE_PN_QUEUE4_SHAPER_STS_Port_2_SWITCH_RESV_SHIFT 29
-#define BCHP_SWITCH_CORE_PN_QUEUE4_SHAPER_STS_Port_2_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: PN_QUEUE4_SHAPER_STS_Port_2 :: BUCKET_CNT [28:00] */
-#define BCHP_SWITCH_CORE_PN_QUEUE4_SHAPER_STS_Port_2_BUCKET_CNT_MASK 0x1fffffff
-#define BCHP_SWITCH_CORE_PN_QUEUE4_SHAPER_STS_Port_2_BUCKET_CNT_SHIFT 0
-#define BCHP_SWITCH_CORE_PN_QUEUE4_SHAPER_STS_Port_2_BUCKET_CNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *PN_QUEUE4_SHAPER_STS_Port_3 - Port N, Queue 4 Shaper Status Register
- ***************************************************************************/
-/* SWITCH_CORE :: PN_QUEUE4_SHAPER_STS_Port_3 :: IN_PROFILE_FLAG [31:31] */
-#define BCHP_SWITCH_CORE_PN_QUEUE4_SHAPER_STS_Port_3_IN_PROFILE_FLAG_MASK 0x80000000
-#define BCHP_SWITCH_CORE_PN_QUEUE4_SHAPER_STS_Port_3_IN_PROFILE_FLAG_SHIFT 31
-#define BCHP_SWITCH_CORE_PN_QUEUE4_SHAPER_STS_Port_3_IN_PROFILE_FLAG_DEFAULT 0x00000001
-
-/* SWITCH_CORE :: PN_QUEUE4_SHAPER_STS_Port_3 :: SWITCH_RESV [30:29] */
-#define BCHP_SWITCH_CORE_PN_QUEUE4_SHAPER_STS_Port_3_SWITCH_RESV_MASK 0x60000000
-#define BCHP_SWITCH_CORE_PN_QUEUE4_SHAPER_STS_Port_3_SWITCH_RESV_SHIFT 29
-#define BCHP_SWITCH_CORE_PN_QUEUE4_SHAPER_STS_Port_3_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: PN_QUEUE4_SHAPER_STS_Port_3 :: BUCKET_CNT [28:00] */
-#define BCHP_SWITCH_CORE_PN_QUEUE4_SHAPER_STS_Port_3_BUCKET_CNT_MASK 0x1fffffff
-#define BCHP_SWITCH_CORE_PN_QUEUE4_SHAPER_STS_Port_3_BUCKET_CNT_SHIFT 0
-#define BCHP_SWITCH_CORE_PN_QUEUE4_SHAPER_STS_Port_3_BUCKET_CNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *PN_QUEUE4_SHAPER_STS_Port_4 - Port N, Queue 4 Shaper Status Register
- ***************************************************************************/
-/* SWITCH_CORE :: PN_QUEUE4_SHAPER_STS_Port_4 :: IN_PROFILE_FLAG [31:31] */
-#define BCHP_SWITCH_CORE_PN_QUEUE4_SHAPER_STS_Port_4_IN_PROFILE_FLAG_MASK 0x80000000
-#define BCHP_SWITCH_CORE_PN_QUEUE4_SHAPER_STS_Port_4_IN_PROFILE_FLAG_SHIFT 31
-#define BCHP_SWITCH_CORE_PN_QUEUE4_SHAPER_STS_Port_4_IN_PROFILE_FLAG_DEFAULT 0x00000001
-
-/* SWITCH_CORE :: PN_QUEUE4_SHAPER_STS_Port_4 :: SWITCH_RESV [30:29] */
-#define BCHP_SWITCH_CORE_PN_QUEUE4_SHAPER_STS_Port_4_SWITCH_RESV_MASK 0x60000000
-#define BCHP_SWITCH_CORE_PN_QUEUE4_SHAPER_STS_Port_4_SWITCH_RESV_SHIFT 29
-#define BCHP_SWITCH_CORE_PN_QUEUE4_SHAPER_STS_Port_4_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: PN_QUEUE4_SHAPER_STS_Port_4 :: BUCKET_CNT [28:00] */
-#define BCHP_SWITCH_CORE_PN_QUEUE4_SHAPER_STS_Port_4_BUCKET_CNT_MASK 0x1fffffff
-#define BCHP_SWITCH_CORE_PN_QUEUE4_SHAPER_STS_Port_4_BUCKET_CNT_SHIFT 0
-#define BCHP_SWITCH_CORE_PN_QUEUE4_SHAPER_STS_Port_4_BUCKET_CNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *PN_QUEUE4_SHAPER_STS_Port_5 - Port N, Queue 4 Shaper Status Register
- ***************************************************************************/
-/* SWITCH_CORE :: PN_QUEUE4_SHAPER_STS_Port_5 :: IN_PROFILE_FLAG [31:31] */
-#define BCHP_SWITCH_CORE_PN_QUEUE4_SHAPER_STS_Port_5_IN_PROFILE_FLAG_MASK 0x80000000
-#define BCHP_SWITCH_CORE_PN_QUEUE4_SHAPER_STS_Port_5_IN_PROFILE_FLAG_SHIFT 31
-#define BCHP_SWITCH_CORE_PN_QUEUE4_SHAPER_STS_Port_5_IN_PROFILE_FLAG_DEFAULT 0x00000001
-
-/* SWITCH_CORE :: PN_QUEUE4_SHAPER_STS_Port_5 :: SWITCH_RESV [30:29] */
-#define BCHP_SWITCH_CORE_PN_QUEUE4_SHAPER_STS_Port_5_SWITCH_RESV_MASK 0x60000000
-#define BCHP_SWITCH_CORE_PN_QUEUE4_SHAPER_STS_Port_5_SWITCH_RESV_SHIFT 29
-#define BCHP_SWITCH_CORE_PN_QUEUE4_SHAPER_STS_Port_5_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: PN_QUEUE4_SHAPER_STS_Port_5 :: BUCKET_CNT [28:00] */
-#define BCHP_SWITCH_CORE_PN_QUEUE4_SHAPER_STS_Port_5_BUCKET_CNT_MASK 0x1fffffff
-#define BCHP_SWITCH_CORE_PN_QUEUE4_SHAPER_STS_Port_5_BUCKET_CNT_SHIFT 0
-#define BCHP_SWITCH_CORE_PN_QUEUE4_SHAPER_STS_Port_5_BUCKET_CNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *P7_QUEUE4_SHAPER_STS - Port 7, Queue 4 Shaper Status Register
- ***************************************************************************/
-/* SWITCH_CORE :: P7_QUEUE4_SHAPER_STS :: IN_PROFILE_FLAG [31:31] */
-#define BCHP_SWITCH_CORE_P7_QUEUE4_SHAPER_STS_IN_PROFILE_FLAG_MASK 0x80000000
-#define BCHP_SWITCH_CORE_P7_QUEUE4_SHAPER_STS_IN_PROFILE_FLAG_SHIFT 31
-#define BCHP_SWITCH_CORE_P7_QUEUE4_SHAPER_STS_IN_PROFILE_FLAG_DEFAULT 0x00000001
-
-/* SWITCH_CORE :: P7_QUEUE4_SHAPER_STS :: SWITCH_RESV [30:29] */
-#define BCHP_SWITCH_CORE_P7_QUEUE4_SHAPER_STS_SWITCH_RESV_MASK 0x60000000
-#define BCHP_SWITCH_CORE_P7_QUEUE4_SHAPER_STS_SWITCH_RESV_SHIFT 29
-#define BCHP_SWITCH_CORE_P7_QUEUE4_SHAPER_STS_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: P7_QUEUE4_SHAPER_STS :: BUCKET_CNT [28:00] */
-#define BCHP_SWITCH_CORE_P7_QUEUE4_SHAPER_STS_BUCKET_CNT_MASK 0x1fffffff
-#define BCHP_SWITCH_CORE_P7_QUEUE4_SHAPER_STS_BUCKET_CNT_SHIFT 0
-#define BCHP_SWITCH_CORE_P7_QUEUE4_SHAPER_STS_BUCKET_CNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *IMP_QUEUE4_SHAPER_STS - Port 8, Queue 4 Shaper Status Register
- ***************************************************************************/
-/* SWITCH_CORE :: IMP_QUEUE4_SHAPER_STS :: IN_PROFILE_FLAG [31:31] */
-#define BCHP_SWITCH_CORE_IMP_QUEUE4_SHAPER_STS_IN_PROFILE_FLAG_MASK 0x80000000
-#define BCHP_SWITCH_CORE_IMP_QUEUE4_SHAPER_STS_IN_PROFILE_FLAG_SHIFT 31
-#define BCHP_SWITCH_CORE_IMP_QUEUE4_SHAPER_STS_IN_PROFILE_FLAG_DEFAULT 0x00000001
-
-/* SWITCH_CORE :: IMP_QUEUE4_SHAPER_STS :: SWITCH_RESV [30:29] */
-#define BCHP_SWITCH_CORE_IMP_QUEUE4_SHAPER_STS_SWITCH_RESV_MASK 0x60000000
-#define BCHP_SWITCH_CORE_IMP_QUEUE4_SHAPER_STS_SWITCH_RESV_SHIFT 29
-#define BCHP_SWITCH_CORE_IMP_QUEUE4_SHAPER_STS_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: IMP_QUEUE4_SHAPER_STS :: BUCKET_CNT [28:00] */
-#define BCHP_SWITCH_CORE_IMP_QUEUE4_SHAPER_STS_BUCKET_CNT_MASK 0x1fffffff
-#define BCHP_SWITCH_CORE_IMP_QUEUE4_SHAPER_STS_BUCKET_CNT_SHIFT 0
-#define BCHP_SWITCH_CORE_IMP_QUEUE4_SHAPER_STS_BUCKET_CNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *PN_QUEUE4_MAX_PACKET_REFRESH_Port_0 - Port N, Packet-based Queue 4 Shaping Rate Configure Register
- ***************************************************************************/
-/* SWITCH_CORE :: PN_QUEUE4_MAX_PACKET_REFRESH_Port_0 :: SWITCH_RESV [31:18] */
-#define BCHP_SWITCH_CORE_PN_QUEUE4_MAX_PACKET_REFRESH_Port_0_SWITCH_RESV_MASK 0xfffc0000
-#define BCHP_SWITCH_CORE_PN_QUEUE4_MAX_PACKET_REFRESH_Port_0_SWITCH_RESV_SHIFT 18
-#define BCHP_SWITCH_CORE_PN_QUEUE4_MAX_PACKET_REFRESH_Port_0_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: PN_QUEUE4_MAX_PACKET_REFRESH_Port_0 :: MAX_REFRESH [17:00] */
-#define BCHP_SWITCH_CORE_PN_QUEUE4_MAX_PACKET_REFRESH_Port_0_MAX_REFRESH_MASK 0x0003ffff
-#define BCHP_SWITCH_CORE_PN_QUEUE4_MAX_PACKET_REFRESH_Port_0_MAX_REFRESH_SHIFT 0
-#define BCHP_SWITCH_CORE_PN_QUEUE4_MAX_PACKET_REFRESH_Port_0_MAX_REFRESH_DEFAULT 0x00000000
-
-/***************************************************************************
- *PN_QUEUE4_MAX_PACKET_REFRESH_Port_1 - Port N, Packet-based Queue 4 Shaping Rate Configure Register
- ***************************************************************************/
-/* SWITCH_CORE :: PN_QUEUE4_MAX_PACKET_REFRESH_Port_1 :: SWITCH_RESV [31:18] */
-#define BCHP_SWITCH_CORE_PN_QUEUE4_MAX_PACKET_REFRESH_Port_1_SWITCH_RESV_MASK 0xfffc0000
-#define BCHP_SWITCH_CORE_PN_QUEUE4_MAX_PACKET_REFRESH_Port_1_SWITCH_RESV_SHIFT 18
-#define BCHP_SWITCH_CORE_PN_QUEUE4_MAX_PACKET_REFRESH_Port_1_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: PN_QUEUE4_MAX_PACKET_REFRESH_Port_1 :: MAX_REFRESH [17:00] */
-#define BCHP_SWITCH_CORE_PN_QUEUE4_MAX_PACKET_REFRESH_Port_1_MAX_REFRESH_MASK 0x0003ffff
-#define BCHP_SWITCH_CORE_PN_QUEUE4_MAX_PACKET_REFRESH_Port_1_MAX_REFRESH_SHIFT 0
-#define BCHP_SWITCH_CORE_PN_QUEUE4_MAX_PACKET_REFRESH_Port_1_MAX_REFRESH_DEFAULT 0x00000000
-
-/***************************************************************************
- *PN_QUEUE4_MAX_PACKET_REFRESH_Port_2 - Port N, Packet-based Queue 4 Shaping Rate Configure Register
- ***************************************************************************/
-/* SWITCH_CORE :: PN_QUEUE4_MAX_PACKET_REFRESH_Port_2 :: SWITCH_RESV [31:18] */
-#define BCHP_SWITCH_CORE_PN_QUEUE4_MAX_PACKET_REFRESH_Port_2_SWITCH_RESV_MASK 0xfffc0000
-#define BCHP_SWITCH_CORE_PN_QUEUE4_MAX_PACKET_REFRESH_Port_2_SWITCH_RESV_SHIFT 18
-#define BCHP_SWITCH_CORE_PN_QUEUE4_MAX_PACKET_REFRESH_Port_2_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: PN_QUEUE4_MAX_PACKET_REFRESH_Port_2 :: MAX_REFRESH [17:00] */
-#define BCHP_SWITCH_CORE_PN_QUEUE4_MAX_PACKET_REFRESH_Port_2_MAX_REFRESH_MASK 0x0003ffff
-#define BCHP_SWITCH_CORE_PN_QUEUE4_MAX_PACKET_REFRESH_Port_2_MAX_REFRESH_SHIFT 0
-#define BCHP_SWITCH_CORE_PN_QUEUE4_MAX_PACKET_REFRESH_Port_2_MAX_REFRESH_DEFAULT 0x00000000
-
-/***************************************************************************
- *PN_QUEUE4_MAX_PACKET_REFRESH_Port_3 - Port N, Packet-based Queue 4 Shaping Rate Configure Register
- ***************************************************************************/
-/* SWITCH_CORE :: PN_QUEUE4_MAX_PACKET_REFRESH_Port_3 :: SWITCH_RESV [31:18] */
-#define BCHP_SWITCH_CORE_PN_QUEUE4_MAX_PACKET_REFRESH_Port_3_SWITCH_RESV_MASK 0xfffc0000
-#define BCHP_SWITCH_CORE_PN_QUEUE4_MAX_PACKET_REFRESH_Port_3_SWITCH_RESV_SHIFT 18
-#define BCHP_SWITCH_CORE_PN_QUEUE4_MAX_PACKET_REFRESH_Port_3_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: PN_QUEUE4_MAX_PACKET_REFRESH_Port_3 :: MAX_REFRESH [17:00] */
-#define BCHP_SWITCH_CORE_PN_QUEUE4_MAX_PACKET_REFRESH_Port_3_MAX_REFRESH_MASK 0x0003ffff
-#define BCHP_SWITCH_CORE_PN_QUEUE4_MAX_PACKET_REFRESH_Port_3_MAX_REFRESH_SHIFT 0
-#define BCHP_SWITCH_CORE_PN_QUEUE4_MAX_PACKET_REFRESH_Port_3_MAX_REFRESH_DEFAULT 0x00000000
-
-/***************************************************************************
- *PN_QUEUE4_MAX_PACKET_REFRESH_Port_4 - Port N, Packet-based Queue 4 Shaping Rate Configure Register
- ***************************************************************************/
-/* SWITCH_CORE :: PN_QUEUE4_MAX_PACKET_REFRESH_Port_4 :: SWITCH_RESV [31:18] */
-#define BCHP_SWITCH_CORE_PN_QUEUE4_MAX_PACKET_REFRESH_Port_4_SWITCH_RESV_MASK 0xfffc0000
-#define BCHP_SWITCH_CORE_PN_QUEUE4_MAX_PACKET_REFRESH_Port_4_SWITCH_RESV_SHIFT 18
-#define BCHP_SWITCH_CORE_PN_QUEUE4_MAX_PACKET_REFRESH_Port_4_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: PN_QUEUE4_MAX_PACKET_REFRESH_Port_4 :: MAX_REFRESH [17:00] */
-#define BCHP_SWITCH_CORE_PN_QUEUE4_MAX_PACKET_REFRESH_Port_4_MAX_REFRESH_MASK 0x0003ffff
-#define BCHP_SWITCH_CORE_PN_QUEUE4_MAX_PACKET_REFRESH_Port_4_MAX_REFRESH_SHIFT 0
-#define BCHP_SWITCH_CORE_PN_QUEUE4_MAX_PACKET_REFRESH_Port_4_MAX_REFRESH_DEFAULT 0x00000000
-
-/***************************************************************************
- *PN_QUEUE4_MAX_PACKET_REFRESH_Port_5 - Port N, Packet-based Queue 4 Shaping Rate Configure Register
- ***************************************************************************/
-/* SWITCH_CORE :: PN_QUEUE4_MAX_PACKET_REFRESH_Port_5 :: SWITCH_RESV [31:18] */
-#define BCHP_SWITCH_CORE_PN_QUEUE4_MAX_PACKET_REFRESH_Port_5_SWITCH_RESV_MASK 0xfffc0000
-#define BCHP_SWITCH_CORE_PN_QUEUE4_MAX_PACKET_REFRESH_Port_5_SWITCH_RESV_SHIFT 18
-#define BCHP_SWITCH_CORE_PN_QUEUE4_MAX_PACKET_REFRESH_Port_5_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: PN_QUEUE4_MAX_PACKET_REFRESH_Port_5 :: MAX_REFRESH [17:00] */
-#define BCHP_SWITCH_CORE_PN_QUEUE4_MAX_PACKET_REFRESH_Port_5_MAX_REFRESH_MASK 0x0003ffff
-#define BCHP_SWITCH_CORE_PN_QUEUE4_MAX_PACKET_REFRESH_Port_5_MAX_REFRESH_SHIFT 0
-#define BCHP_SWITCH_CORE_PN_QUEUE4_MAX_PACKET_REFRESH_Port_5_MAX_REFRESH_DEFAULT 0x00000000
-
-/***************************************************************************
- *P7_QUEUE4_MAX_PACKET_REFRESH - Port 7, Packet-based Queue 4 Shaping Rate Configure Register
- ***************************************************************************/
-/* SWITCH_CORE :: P7_QUEUE4_MAX_PACKET_REFRESH :: SWITCH_RESV [31:18] */
-#define BCHP_SWITCH_CORE_P7_QUEUE4_MAX_PACKET_REFRESH_SWITCH_RESV_MASK 0xfffc0000
-#define BCHP_SWITCH_CORE_P7_QUEUE4_MAX_PACKET_REFRESH_SWITCH_RESV_SHIFT 18
-#define BCHP_SWITCH_CORE_P7_QUEUE4_MAX_PACKET_REFRESH_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: P7_QUEUE4_MAX_PACKET_REFRESH :: MAX_REFRESH [17:00] */
-#define BCHP_SWITCH_CORE_P7_QUEUE4_MAX_PACKET_REFRESH_MAX_REFRESH_MASK 0x0003ffff
-#define BCHP_SWITCH_CORE_P7_QUEUE4_MAX_PACKET_REFRESH_MAX_REFRESH_SHIFT 0
-#define BCHP_SWITCH_CORE_P7_QUEUE4_MAX_PACKET_REFRESH_MAX_REFRESH_DEFAULT 0x00000000
-
-/***************************************************************************
- *IMP_QUEUE4_MAX_PACKET_REFRESH - Port 8, Packet-based Queue 4 Shaping Rate Configure Register
- ***************************************************************************/
-/* SWITCH_CORE :: IMP_QUEUE4_MAX_PACKET_REFRESH :: SWITCH_RESV [31:18] */
-#define BCHP_SWITCH_CORE_IMP_QUEUE4_MAX_PACKET_REFRESH_SWITCH_RESV_MASK 0xfffc0000
-#define BCHP_SWITCH_CORE_IMP_QUEUE4_MAX_PACKET_REFRESH_SWITCH_RESV_SHIFT 18
-#define BCHP_SWITCH_CORE_IMP_QUEUE4_MAX_PACKET_REFRESH_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: IMP_QUEUE4_MAX_PACKET_REFRESH :: MAX_REFRESH [17:00] */
-#define BCHP_SWITCH_CORE_IMP_QUEUE4_MAX_PACKET_REFRESH_MAX_REFRESH_MASK 0x0003ffff
-#define BCHP_SWITCH_CORE_IMP_QUEUE4_MAX_PACKET_REFRESH_MAX_REFRESH_SHIFT 0
-#define BCHP_SWITCH_CORE_IMP_QUEUE4_MAX_PACKET_REFRESH_MAX_REFRESH_DEFAULT 0x00000000
-
-/***************************************************************************
- *EGRESS_SHAPER_Q4_CONFIG_REG_SPARE0 - Spare 0 Register (Not2Release)
- ***************************************************************************/
-/* SWITCH_CORE :: EGRESS_SHAPER_Q4_CONFIG_REG_SPARE0 :: EGRESS_SHAPER_Q4_CONFIG_REG_SPARE0 [31:00] */
-#define BCHP_SWITCH_CORE_EGRESS_SHAPER_Q4_CONFIG_REG_SPARE0_EGRESS_SHAPER_Q4_CONFIG_REG_SPARE0_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_EGRESS_SHAPER_Q4_CONFIG_REG_SPARE0_EGRESS_SHAPER_Q4_CONFIG_REG_SPARE0_SHIFT 0
-#define BCHP_SWITCH_CORE_EGRESS_SHAPER_Q4_CONFIG_REG_SPARE0_EGRESS_SHAPER_Q4_CONFIG_REG_SPARE0_DEFAULT 0x00000000
-
-/***************************************************************************
- *EGRESS_SHAPER_Q4_CONFIG_REG_SPARE1 - Spare 1 Register (Not2Release)
- ***************************************************************************/
-/* SWITCH_CORE :: EGRESS_SHAPER_Q4_CONFIG_REG_SPARE1 :: EGRESS_SHAPER_Q4_CONFIG_REG_SPARE1 [31:00] */
-#define BCHP_SWITCH_CORE_EGRESS_SHAPER_Q4_CONFIG_REG_SPARE1_EGRESS_SHAPER_Q4_CONFIG_REG_SPARE1_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_EGRESS_SHAPER_Q4_CONFIG_REG_SPARE1_EGRESS_SHAPER_Q4_CONFIG_REG_SPARE1_SHIFT 0
-#define BCHP_SWITCH_CORE_EGRESS_SHAPER_Q4_CONFIG_REG_SPARE1_EGRESS_SHAPER_Q4_CONFIG_REG_SPARE1_DEFAULT 0x00000000
-
-/***************************************************************************
- *PN_QUEUE4_MAX_PACKET_THD_SEL_Port_0 - Port N, Packet-based Queue 4 Burst Size Configure Register
- ***************************************************************************/
-/* SWITCH_CORE :: PN_QUEUE4_MAX_PACKET_THD_SEL_Port_0 :: SWITCH_RESV [31:18] */
-#define BCHP_SWITCH_CORE_PN_QUEUE4_MAX_PACKET_THD_SEL_Port_0_SWITCH_RESV_MASK 0xfffc0000
-#define BCHP_SWITCH_CORE_PN_QUEUE4_MAX_PACKET_THD_SEL_Port_0_SWITCH_RESV_SHIFT 18
-#define BCHP_SWITCH_CORE_PN_QUEUE4_MAX_PACKET_THD_SEL_Port_0_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: PN_QUEUE4_MAX_PACKET_THD_SEL_Port_0 :: MAX_THD_SEL [17:00] */
-#define BCHP_SWITCH_CORE_PN_QUEUE4_MAX_PACKET_THD_SEL_Port_0_MAX_THD_SEL_MASK 0x0003ffff
-#define BCHP_SWITCH_CORE_PN_QUEUE4_MAX_PACKET_THD_SEL_Port_0_MAX_THD_SEL_SHIFT 0
-#define BCHP_SWITCH_CORE_PN_QUEUE4_MAX_PACKET_THD_SEL_Port_0_MAX_THD_SEL_DEFAULT 0x00000000
-
-/***************************************************************************
- *PN_QUEUE4_MAX_PACKET_THD_SEL_Port_1 - Port N, Packet-based Queue 4 Burst Size Configure Register
- ***************************************************************************/
-/* SWITCH_CORE :: PN_QUEUE4_MAX_PACKET_THD_SEL_Port_1 :: SWITCH_RESV [31:18] */
-#define BCHP_SWITCH_CORE_PN_QUEUE4_MAX_PACKET_THD_SEL_Port_1_SWITCH_RESV_MASK 0xfffc0000
-#define BCHP_SWITCH_CORE_PN_QUEUE4_MAX_PACKET_THD_SEL_Port_1_SWITCH_RESV_SHIFT 18
-#define BCHP_SWITCH_CORE_PN_QUEUE4_MAX_PACKET_THD_SEL_Port_1_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: PN_QUEUE4_MAX_PACKET_THD_SEL_Port_1 :: MAX_THD_SEL [17:00] */
-#define BCHP_SWITCH_CORE_PN_QUEUE4_MAX_PACKET_THD_SEL_Port_1_MAX_THD_SEL_MASK 0x0003ffff
-#define BCHP_SWITCH_CORE_PN_QUEUE4_MAX_PACKET_THD_SEL_Port_1_MAX_THD_SEL_SHIFT 0
-#define BCHP_SWITCH_CORE_PN_QUEUE4_MAX_PACKET_THD_SEL_Port_1_MAX_THD_SEL_DEFAULT 0x00000000
-
-/***************************************************************************
- *PN_QUEUE4_MAX_PACKET_THD_SEL_Port_2 - Port N, Packet-based Queue 4 Burst Size Configure Register
- ***************************************************************************/
-/* SWITCH_CORE :: PN_QUEUE4_MAX_PACKET_THD_SEL_Port_2 :: SWITCH_RESV [31:18] */
-#define BCHP_SWITCH_CORE_PN_QUEUE4_MAX_PACKET_THD_SEL_Port_2_SWITCH_RESV_MASK 0xfffc0000
-#define BCHP_SWITCH_CORE_PN_QUEUE4_MAX_PACKET_THD_SEL_Port_2_SWITCH_RESV_SHIFT 18
-#define BCHP_SWITCH_CORE_PN_QUEUE4_MAX_PACKET_THD_SEL_Port_2_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: PN_QUEUE4_MAX_PACKET_THD_SEL_Port_2 :: MAX_THD_SEL [17:00] */
-#define BCHP_SWITCH_CORE_PN_QUEUE4_MAX_PACKET_THD_SEL_Port_2_MAX_THD_SEL_MASK 0x0003ffff
-#define BCHP_SWITCH_CORE_PN_QUEUE4_MAX_PACKET_THD_SEL_Port_2_MAX_THD_SEL_SHIFT 0
-#define BCHP_SWITCH_CORE_PN_QUEUE4_MAX_PACKET_THD_SEL_Port_2_MAX_THD_SEL_DEFAULT 0x00000000
-
-/***************************************************************************
- *PN_QUEUE4_MAX_PACKET_THD_SEL_Port_3 - Port N, Packet-based Queue 4 Burst Size Configure Register
- ***************************************************************************/
-/* SWITCH_CORE :: PN_QUEUE4_MAX_PACKET_THD_SEL_Port_3 :: SWITCH_RESV [31:18] */
-#define BCHP_SWITCH_CORE_PN_QUEUE4_MAX_PACKET_THD_SEL_Port_3_SWITCH_RESV_MASK 0xfffc0000
-#define BCHP_SWITCH_CORE_PN_QUEUE4_MAX_PACKET_THD_SEL_Port_3_SWITCH_RESV_SHIFT 18
-#define BCHP_SWITCH_CORE_PN_QUEUE4_MAX_PACKET_THD_SEL_Port_3_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: PN_QUEUE4_MAX_PACKET_THD_SEL_Port_3 :: MAX_THD_SEL [17:00] */
-#define BCHP_SWITCH_CORE_PN_QUEUE4_MAX_PACKET_THD_SEL_Port_3_MAX_THD_SEL_MASK 0x0003ffff
-#define BCHP_SWITCH_CORE_PN_QUEUE4_MAX_PACKET_THD_SEL_Port_3_MAX_THD_SEL_SHIFT 0
-#define BCHP_SWITCH_CORE_PN_QUEUE4_MAX_PACKET_THD_SEL_Port_3_MAX_THD_SEL_DEFAULT 0x00000000
-
-/***************************************************************************
- *PN_QUEUE4_MAX_PACKET_THD_SEL_Port_4 - Port N, Packet-based Queue 4 Burst Size Configure Register
- ***************************************************************************/
-/* SWITCH_CORE :: PN_QUEUE4_MAX_PACKET_THD_SEL_Port_4 :: SWITCH_RESV [31:18] */
-#define BCHP_SWITCH_CORE_PN_QUEUE4_MAX_PACKET_THD_SEL_Port_4_SWITCH_RESV_MASK 0xfffc0000
-#define BCHP_SWITCH_CORE_PN_QUEUE4_MAX_PACKET_THD_SEL_Port_4_SWITCH_RESV_SHIFT 18
-#define BCHP_SWITCH_CORE_PN_QUEUE4_MAX_PACKET_THD_SEL_Port_4_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: PN_QUEUE4_MAX_PACKET_THD_SEL_Port_4 :: MAX_THD_SEL [17:00] */
-#define BCHP_SWITCH_CORE_PN_QUEUE4_MAX_PACKET_THD_SEL_Port_4_MAX_THD_SEL_MASK 0x0003ffff
-#define BCHP_SWITCH_CORE_PN_QUEUE4_MAX_PACKET_THD_SEL_Port_4_MAX_THD_SEL_SHIFT 0
-#define BCHP_SWITCH_CORE_PN_QUEUE4_MAX_PACKET_THD_SEL_Port_4_MAX_THD_SEL_DEFAULT 0x00000000
-
-/***************************************************************************
- *PN_QUEUE4_MAX_PACKET_THD_SEL_Port_5 - Port N, Packet-based Queue 4 Burst Size Configure Register
- ***************************************************************************/
-/* SWITCH_CORE :: PN_QUEUE4_MAX_PACKET_THD_SEL_Port_5 :: SWITCH_RESV [31:18] */
-#define BCHP_SWITCH_CORE_PN_QUEUE4_MAX_PACKET_THD_SEL_Port_5_SWITCH_RESV_MASK 0xfffc0000
-#define BCHP_SWITCH_CORE_PN_QUEUE4_MAX_PACKET_THD_SEL_Port_5_SWITCH_RESV_SHIFT 18
-#define BCHP_SWITCH_CORE_PN_QUEUE4_MAX_PACKET_THD_SEL_Port_5_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: PN_QUEUE4_MAX_PACKET_THD_SEL_Port_5 :: MAX_THD_SEL [17:00] */
-#define BCHP_SWITCH_CORE_PN_QUEUE4_MAX_PACKET_THD_SEL_Port_5_MAX_THD_SEL_MASK 0x0003ffff
-#define BCHP_SWITCH_CORE_PN_QUEUE4_MAX_PACKET_THD_SEL_Port_5_MAX_THD_SEL_SHIFT 0
-#define BCHP_SWITCH_CORE_PN_QUEUE4_MAX_PACKET_THD_SEL_Port_5_MAX_THD_SEL_DEFAULT 0x00000000
-
-/***************************************************************************
- *P7_QUEUE4_MAX_PACKET_THD_SEL - Port 7, Packet-based Queue 4 Burst Size Configure Register
- ***************************************************************************/
-/* SWITCH_CORE :: P7_QUEUE4_MAX_PACKET_THD_SEL :: SWITCH_RESV [31:18] */
-#define BCHP_SWITCH_CORE_P7_QUEUE4_MAX_PACKET_THD_SEL_SWITCH_RESV_MASK 0xfffc0000
-#define BCHP_SWITCH_CORE_P7_QUEUE4_MAX_PACKET_THD_SEL_SWITCH_RESV_SHIFT 18
-#define BCHP_SWITCH_CORE_P7_QUEUE4_MAX_PACKET_THD_SEL_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: P7_QUEUE4_MAX_PACKET_THD_SEL :: MAX_THD_SEL [17:00] */
-#define BCHP_SWITCH_CORE_P7_QUEUE4_MAX_PACKET_THD_SEL_MAX_THD_SEL_MASK 0x0003ffff
-#define BCHP_SWITCH_CORE_P7_QUEUE4_MAX_PACKET_THD_SEL_MAX_THD_SEL_SHIFT 0
-#define BCHP_SWITCH_CORE_P7_QUEUE4_MAX_PACKET_THD_SEL_MAX_THD_SEL_DEFAULT 0x00000000
-
-/***************************************************************************
- *IMP_QUEUE4_MAX_PACKET_THD_SEL - Port 8, Packet-based Queue 4 Burst Size Configure Register
- ***************************************************************************/
-/* SWITCH_CORE :: IMP_QUEUE4_MAX_PACKET_THD_SEL :: SWITCH_RESV [31:18] */
-#define BCHP_SWITCH_CORE_IMP_QUEUE4_MAX_PACKET_THD_SEL_SWITCH_RESV_MASK 0xfffc0000
-#define BCHP_SWITCH_CORE_IMP_QUEUE4_MAX_PACKET_THD_SEL_SWITCH_RESV_SHIFT 18
-#define BCHP_SWITCH_CORE_IMP_QUEUE4_MAX_PACKET_THD_SEL_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: IMP_QUEUE4_MAX_PACKET_THD_SEL :: MAX_THD_SEL [17:00] */
-#define BCHP_SWITCH_CORE_IMP_QUEUE4_MAX_PACKET_THD_SEL_MAX_THD_SEL_MASK 0x0003ffff
-#define BCHP_SWITCH_CORE_IMP_QUEUE4_MAX_PACKET_THD_SEL_MAX_THD_SEL_SHIFT 0
-#define BCHP_SWITCH_CORE_IMP_QUEUE4_MAX_PACKET_THD_SEL_MAX_THD_SEL_DEFAULT 0x00000000
-
-/***************************************************************************
- *QUEUE4_AVB_SHAPING_MODE - Queue 4 AVB Shaping Mode Control Register
- ***************************************************************************/
-/* SWITCH_CORE :: QUEUE4_AVB_SHAPING_MODE :: reserved_for_padding0 [31:16] */
-#define BCHP_SWITCH_CORE_QUEUE4_AVB_SHAPING_MODE_reserved_for_padding0_MASK 0xffff0000
-#define BCHP_SWITCH_CORE_QUEUE4_AVB_SHAPING_MODE_reserved_for_padding0_SHIFT 16
-
-/* SWITCH_CORE :: QUEUE4_AVB_SHAPING_MODE :: SWITCH_RESV [15:09] */
-#define BCHP_SWITCH_CORE_QUEUE4_AVB_SHAPING_MODE_SWITCH_RESV_MASK 0x0000fe00
-#define BCHP_SWITCH_CORE_QUEUE4_AVB_SHAPING_MODE_SWITCH_RESV_SHIFT 9
-#define BCHP_SWITCH_CORE_QUEUE4_AVB_SHAPING_MODE_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: QUEUE4_AVB_SHAPING_MODE :: QUEUE4_AVB_SHAPING_MODE [08:00] */
-#define BCHP_SWITCH_CORE_QUEUE4_AVB_SHAPING_MODE_QUEUE4_AVB_SHAPING_MODE_MASK 0x000001ff
-#define BCHP_SWITCH_CORE_QUEUE4_AVB_SHAPING_MODE_QUEUE4_AVB_SHAPING_MODE_SHIFT 0
-#define BCHP_SWITCH_CORE_QUEUE4_AVB_SHAPING_MODE_QUEUE4_AVB_SHAPING_MODE_DEFAULT 0x00000000
-
-/***************************************************************************
- *QUEUE4_SHAPER_ENABLE - Queue 4 Shaper Enable Register
- ***************************************************************************/
-/* SWITCH_CORE :: QUEUE4_SHAPER_ENABLE :: reserved_for_padding0 [31:16] */
-#define BCHP_SWITCH_CORE_QUEUE4_SHAPER_ENABLE_reserved_for_padding0_MASK 0xffff0000
-#define BCHP_SWITCH_CORE_QUEUE4_SHAPER_ENABLE_reserved_for_padding0_SHIFT 16
-
-/* SWITCH_CORE :: QUEUE4_SHAPER_ENABLE :: SWITCH_RESV [15:09] */
-#define BCHP_SWITCH_CORE_QUEUE4_SHAPER_ENABLE_SWITCH_RESV_MASK 0x0000fe00
-#define BCHP_SWITCH_CORE_QUEUE4_SHAPER_ENABLE_SWITCH_RESV_SHIFT 9
-#define BCHP_SWITCH_CORE_QUEUE4_SHAPER_ENABLE_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: QUEUE4_SHAPER_ENABLE :: QUEUE4_SHAPER_ENABLE [08:00] */
-#define BCHP_SWITCH_CORE_QUEUE4_SHAPER_ENABLE_QUEUE4_SHAPER_ENABLE_MASK 0x000001ff
-#define BCHP_SWITCH_CORE_QUEUE4_SHAPER_ENABLE_QUEUE4_SHAPER_ENABLE_SHIFT 0
-#define BCHP_SWITCH_CORE_QUEUE4_SHAPER_ENABLE_QUEUE4_SHAPER_ENABLE_DEFAULT 0x00000000
-
-/***************************************************************************
- *QUEUE4_SHAPER_BUCKET_COUNT_SELECT - Queue 4 Bucket Count Select Register
- ***************************************************************************/
-/* SWITCH_CORE :: QUEUE4_SHAPER_BUCKET_COUNT_SELECT :: reserved_for_padding0 [31:16] */
-#define BCHP_SWITCH_CORE_QUEUE4_SHAPER_BUCKET_COUNT_SELECT_reserved_for_padding0_MASK 0xffff0000
-#define BCHP_SWITCH_CORE_QUEUE4_SHAPER_BUCKET_COUNT_SELECT_reserved_for_padding0_SHIFT 16
-
-/* SWITCH_CORE :: QUEUE4_SHAPER_BUCKET_COUNT_SELECT :: SWITCH_RESV [15:09] */
-#define BCHP_SWITCH_CORE_QUEUE4_SHAPER_BUCKET_COUNT_SELECT_SWITCH_RESV_MASK 0x0000fe00
-#define BCHP_SWITCH_CORE_QUEUE4_SHAPER_BUCKET_COUNT_SELECT_SWITCH_RESV_SHIFT 9
-#define BCHP_SWITCH_CORE_QUEUE4_SHAPER_BUCKET_COUNT_SELECT_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: QUEUE4_SHAPER_BUCKET_COUNT_SELECT :: QUEUE4_SHAPER_BUCKET_COUNT_SELECT [08:00] */
-#define BCHP_SWITCH_CORE_QUEUE4_SHAPER_BUCKET_COUNT_SELECT_QUEUE4_SHAPER_BUCKET_COUNT_SELECT_MASK 0x000001ff
-#define BCHP_SWITCH_CORE_QUEUE4_SHAPER_BUCKET_COUNT_SELECT_QUEUE4_SHAPER_BUCKET_COUNT_SELECT_SHIFT 0
-#define BCHP_SWITCH_CORE_QUEUE4_SHAPER_BUCKET_COUNT_SELECT_QUEUE4_SHAPER_BUCKET_COUNT_SELECT_DEFAULT 0x00000000
-
-/***************************************************************************
- *QUEUE4_SHAPER_BLOCKING - Queue 4 Shaper Blocking Control Register
- ***************************************************************************/
-/* SWITCH_CORE :: QUEUE4_SHAPER_BLOCKING :: reserved_for_padding0 [31:16] */
-#define BCHP_SWITCH_CORE_QUEUE4_SHAPER_BLOCKING_reserved_for_padding0_MASK 0xffff0000
-#define BCHP_SWITCH_CORE_QUEUE4_SHAPER_BLOCKING_reserved_for_padding0_SHIFT 16
-
-/* SWITCH_CORE :: QUEUE4_SHAPER_BLOCKING :: SWITCH_RESV [15:09] */
-#define BCHP_SWITCH_CORE_QUEUE4_SHAPER_BLOCKING_SWITCH_RESV_MASK 0x0000fe00
-#define BCHP_SWITCH_CORE_QUEUE4_SHAPER_BLOCKING_SWITCH_RESV_SHIFT 9
-#define BCHP_SWITCH_CORE_QUEUE4_SHAPER_BLOCKING_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: QUEUE4_SHAPER_BLOCKING :: QUEUE4_SHAPER_BLOCKING [08:00] */
-#define BCHP_SWITCH_CORE_QUEUE4_SHAPER_BLOCKING_QUEUE4_SHAPER_BLOCKING_MASK 0x000001ff
-#define BCHP_SWITCH_CORE_QUEUE4_SHAPER_BLOCKING_QUEUE4_SHAPER_BLOCKING_SHIFT 0
-#define BCHP_SWITCH_CORE_QUEUE4_SHAPER_BLOCKING_QUEUE4_SHAPER_BLOCKING_DEFAULT 0x00000000
-
-/***************************************************************************
- *PN_QUEUE5_MAX_REFRESH_Port_0 - Port N, Byte-based Queue 5 Shaping Rate Configure Register
- ***************************************************************************/
-/* SWITCH_CORE :: PN_QUEUE5_MAX_REFRESH_Port_0 :: SWITCH_RESV [31:18] */
-#define BCHP_SWITCH_CORE_PN_QUEUE5_MAX_REFRESH_Port_0_SWITCH_RESV_MASK 0xfffc0000
-#define BCHP_SWITCH_CORE_PN_QUEUE5_MAX_REFRESH_Port_0_SWITCH_RESV_SHIFT 18
-#define BCHP_SWITCH_CORE_PN_QUEUE5_MAX_REFRESH_Port_0_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: PN_QUEUE5_MAX_REFRESH_Port_0 :: MAX_REFRESH [17:00] */
-#define BCHP_SWITCH_CORE_PN_QUEUE5_MAX_REFRESH_Port_0_MAX_REFRESH_MASK 0x0003ffff
-#define BCHP_SWITCH_CORE_PN_QUEUE5_MAX_REFRESH_Port_0_MAX_REFRESH_SHIFT 0
-#define BCHP_SWITCH_CORE_PN_QUEUE5_MAX_REFRESH_Port_0_MAX_REFRESH_DEFAULT 0x00000000
-
-/***************************************************************************
- *PN_QUEUE5_MAX_REFRESH_Port_1 - Port N, Byte-based Queue 5 Shaping Rate Configure Register
- ***************************************************************************/
-/* SWITCH_CORE :: PN_QUEUE5_MAX_REFRESH_Port_1 :: SWITCH_RESV [31:18] */
-#define BCHP_SWITCH_CORE_PN_QUEUE5_MAX_REFRESH_Port_1_SWITCH_RESV_MASK 0xfffc0000
-#define BCHP_SWITCH_CORE_PN_QUEUE5_MAX_REFRESH_Port_1_SWITCH_RESV_SHIFT 18
-#define BCHP_SWITCH_CORE_PN_QUEUE5_MAX_REFRESH_Port_1_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: PN_QUEUE5_MAX_REFRESH_Port_1 :: MAX_REFRESH [17:00] */
-#define BCHP_SWITCH_CORE_PN_QUEUE5_MAX_REFRESH_Port_1_MAX_REFRESH_MASK 0x0003ffff
-#define BCHP_SWITCH_CORE_PN_QUEUE5_MAX_REFRESH_Port_1_MAX_REFRESH_SHIFT 0
-#define BCHP_SWITCH_CORE_PN_QUEUE5_MAX_REFRESH_Port_1_MAX_REFRESH_DEFAULT 0x00000000
-
-/***************************************************************************
- *PN_QUEUE5_MAX_REFRESH_Port_2 - Port N, Byte-based Queue 5 Shaping Rate Configure Register
- ***************************************************************************/
-/* SWITCH_CORE :: PN_QUEUE5_MAX_REFRESH_Port_2 :: SWITCH_RESV [31:18] */
-#define BCHP_SWITCH_CORE_PN_QUEUE5_MAX_REFRESH_Port_2_SWITCH_RESV_MASK 0xfffc0000
-#define BCHP_SWITCH_CORE_PN_QUEUE5_MAX_REFRESH_Port_2_SWITCH_RESV_SHIFT 18
-#define BCHP_SWITCH_CORE_PN_QUEUE5_MAX_REFRESH_Port_2_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: PN_QUEUE5_MAX_REFRESH_Port_2 :: MAX_REFRESH [17:00] */
-#define BCHP_SWITCH_CORE_PN_QUEUE5_MAX_REFRESH_Port_2_MAX_REFRESH_MASK 0x0003ffff
-#define BCHP_SWITCH_CORE_PN_QUEUE5_MAX_REFRESH_Port_2_MAX_REFRESH_SHIFT 0
-#define BCHP_SWITCH_CORE_PN_QUEUE5_MAX_REFRESH_Port_2_MAX_REFRESH_DEFAULT 0x00000000
-
-/***************************************************************************
- *PN_QUEUE5_MAX_REFRESH_Port_3 - Port N, Byte-based Queue 5 Shaping Rate Configure Register
- ***************************************************************************/
-/* SWITCH_CORE :: PN_QUEUE5_MAX_REFRESH_Port_3 :: SWITCH_RESV [31:18] */
-#define BCHP_SWITCH_CORE_PN_QUEUE5_MAX_REFRESH_Port_3_SWITCH_RESV_MASK 0xfffc0000
-#define BCHP_SWITCH_CORE_PN_QUEUE5_MAX_REFRESH_Port_3_SWITCH_RESV_SHIFT 18
-#define BCHP_SWITCH_CORE_PN_QUEUE5_MAX_REFRESH_Port_3_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: PN_QUEUE5_MAX_REFRESH_Port_3 :: MAX_REFRESH [17:00] */
-#define BCHP_SWITCH_CORE_PN_QUEUE5_MAX_REFRESH_Port_3_MAX_REFRESH_MASK 0x0003ffff
-#define BCHP_SWITCH_CORE_PN_QUEUE5_MAX_REFRESH_Port_3_MAX_REFRESH_SHIFT 0
-#define BCHP_SWITCH_CORE_PN_QUEUE5_MAX_REFRESH_Port_3_MAX_REFRESH_DEFAULT 0x00000000
-
-/***************************************************************************
- *PN_QUEUE5_MAX_REFRESH_Port_4 - Port N, Byte-based Queue 5 Shaping Rate Configure Register
- ***************************************************************************/
-/* SWITCH_CORE :: PN_QUEUE5_MAX_REFRESH_Port_4 :: SWITCH_RESV [31:18] */
-#define BCHP_SWITCH_CORE_PN_QUEUE5_MAX_REFRESH_Port_4_SWITCH_RESV_MASK 0xfffc0000
-#define BCHP_SWITCH_CORE_PN_QUEUE5_MAX_REFRESH_Port_4_SWITCH_RESV_SHIFT 18
-#define BCHP_SWITCH_CORE_PN_QUEUE5_MAX_REFRESH_Port_4_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: PN_QUEUE5_MAX_REFRESH_Port_4 :: MAX_REFRESH [17:00] */
-#define BCHP_SWITCH_CORE_PN_QUEUE5_MAX_REFRESH_Port_4_MAX_REFRESH_MASK 0x0003ffff
-#define BCHP_SWITCH_CORE_PN_QUEUE5_MAX_REFRESH_Port_4_MAX_REFRESH_SHIFT 0
-#define BCHP_SWITCH_CORE_PN_QUEUE5_MAX_REFRESH_Port_4_MAX_REFRESH_DEFAULT 0x00000000
-
-/***************************************************************************
- *PN_QUEUE5_MAX_REFRESH_Port_5 - Port N, Byte-based Queue 5 Shaping Rate Configure Register
- ***************************************************************************/
-/* SWITCH_CORE :: PN_QUEUE5_MAX_REFRESH_Port_5 :: SWITCH_RESV [31:18] */
-#define BCHP_SWITCH_CORE_PN_QUEUE5_MAX_REFRESH_Port_5_SWITCH_RESV_MASK 0xfffc0000
-#define BCHP_SWITCH_CORE_PN_QUEUE5_MAX_REFRESH_Port_5_SWITCH_RESV_SHIFT 18
-#define BCHP_SWITCH_CORE_PN_QUEUE5_MAX_REFRESH_Port_5_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: PN_QUEUE5_MAX_REFRESH_Port_5 :: MAX_REFRESH [17:00] */
-#define BCHP_SWITCH_CORE_PN_QUEUE5_MAX_REFRESH_Port_5_MAX_REFRESH_MASK 0x0003ffff
-#define BCHP_SWITCH_CORE_PN_QUEUE5_MAX_REFRESH_Port_5_MAX_REFRESH_SHIFT 0
-#define BCHP_SWITCH_CORE_PN_QUEUE5_MAX_REFRESH_Port_5_MAX_REFRESH_DEFAULT 0x00000000
-
-/***************************************************************************
- *P7_QUEUE5_MAX_REFRESH - Port 7, Byte-based Queue 5 Shaping Rate Configure Register
- ***************************************************************************/
-/* SWITCH_CORE :: P7_QUEUE5_MAX_REFRESH :: SWITCH_RESV [31:18] */
-#define BCHP_SWITCH_CORE_P7_QUEUE5_MAX_REFRESH_SWITCH_RESV_MASK 0xfffc0000
-#define BCHP_SWITCH_CORE_P7_QUEUE5_MAX_REFRESH_SWITCH_RESV_SHIFT 18
-#define BCHP_SWITCH_CORE_P7_QUEUE5_MAX_REFRESH_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: P7_QUEUE5_MAX_REFRESH :: MAX_REFRESH [17:00] */
-#define BCHP_SWITCH_CORE_P7_QUEUE5_MAX_REFRESH_MAX_REFRESH_MASK 0x0003ffff
-#define BCHP_SWITCH_CORE_P7_QUEUE5_MAX_REFRESH_MAX_REFRESH_SHIFT 0
-#define BCHP_SWITCH_CORE_P7_QUEUE5_MAX_REFRESH_MAX_REFRESH_DEFAULT 0x00000000
-
-/***************************************************************************
- *IMP_QUEUE5_MAX_REFRESH - Port 8, Byte-based Queue 5 Shaping Rate Configure Register
- ***************************************************************************/
-/* SWITCH_CORE :: IMP_QUEUE5_MAX_REFRESH :: SWITCH_RESV [31:18] */
-#define BCHP_SWITCH_CORE_IMP_QUEUE5_MAX_REFRESH_SWITCH_RESV_MASK 0xfffc0000
-#define BCHP_SWITCH_CORE_IMP_QUEUE5_MAX_REFRESH_SWITCH_RESV_SHIFT 18
-#define BCHP_SWITCH_CORE_IMP_QUEUE5_MAX_REFRESH_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: IMP_QUEUE5_MAX_REFRESH :: MAX_REFRESH [17:00] */
-#define BCHP_SWITCH_CORE_IMP_QUEUE5_MAX_REFRESH_MAX_REFRESH_MASK 0x0003ffff
-#define BCHP_SWITCH_CORE_IMP_QUEUE5_MAX_REFRESH_MAX_REFRESH_SHIFT 0
-#define BCHP_SWITCH_CORE_IMP_QUEUE5_MAX_REFRESH_MAX_REFRESH_DEFAULT 0x00000000
-
-/***************************************************************************
- *PN_QUEUE5_MAX_THD_SEL_Port_0 - Port N, Byte-based Queue 5 Burst Size Configure Register
- ***************************************************************************/
-/* SWITCH_CORE :: PN_QUEUE5_MAX_THD_SEL_Port_0 :: SWITCH_RESV [31:18] */
-#define BCHP_SWITCH_CORE_PN_QUEUE5_MAX_THD_SEL_Port_0_SWITCH_RESV_MASK 0xfffc0000
-#define BCHP_SWITCH_CORE_PN_QUEUE5_MAX_THD_SEL_Port_0_SWITCH_RESV_SHIFT 18
-#define BCHP_SWITCH_CORE_PN_QUEUE5_MAX_THD_SEL_Port_0_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: PN_QUEUE5_MAX_THD_SEL_Port_0 :: MAX_THD_SEL [17:00] */
-#define BCHP_SWITCH_CORE_PN_QUEUE5_MAX_THD_SEL_Port_0_MAX_THD_SEL_MASK 0x0003ffff
-#define BCHP_SWITCH_CORE_PN_QUEUE5_MAX_THD_SEL_Port_0_MAX_THD_SEL_SHIFT 0
-#define BCHP_SWITCH_CORE_PN_QUEUE5_MAX_THD_SEL_Port_0_MAX_THD_SEL_DEFAULT 0x00000000
-
-/***************************************************************************
- *PN_QUEUE5_MAX_THD_SEL_Port_1 - Port N, Byte-based Queue 5 Burst Size Configure Register
- ***************************************************************************/
-/* SWITCH_CORE :: PN_QUEUE5_MAX_THD_SEL_Port_1 :: SWITCH_RESV [31:18] */
-#define BCHP_SWITCH_CORE_PN_QUEUE5_MAX_THD_SEL_Port_1_SWITCH_RESV_MASK 0xfffc0000
-#define BCHP_SWITCH_CORE_PN_QUEUE5_MAX_THD_SEL_Port_1_SWITCH_RESV_SHIFT 18
-#define BCHP_SWITCH_CORE_PN_QUEUE5_MAX_THD_SEL_Port_1_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: PN_QUEUE5_MAX_THD_SEL_Port_1 :: MAX_THD_SEL [17:00] */
-#define BCHP_SWITCH_CORE_PN_QUEUE5_MAX_THD_SEL_Port_1_MAX_THD_SEL_MASK 0x0003ffff
-#define BCHP_SWITCH_CORE_PN_QUEUE5_MAX_THD_SEL_Port_1_MAX_THD_SEL_SHIFT 0
-#define BCHP_SWITCH_CORE_PN_QUEUE5_MAX_THD_SEL_Port_1_MAX_THD_SEL_DEFAULT 0x00000000
-
-/***************************************************************************
- *PN_QUEUE5_MAX_THD_SEL_Port_2 - Port N, Byte-based Queue 5 Burst Size Configure Register
- ***************************************************************************/
-/* SWITCH_CORE :: PN_QUEUE5_MAX_THD_SEL_Port_2 :: SWITCH_RESV [31:18] */
-#define BCHP_SWITCH_CORE_PN_QUEUE5_MAX_THD_SEL_Port_2_SWITCH_RESV_MASK 0xfffc0000
-#define BCHP_SWITCH_CORE_PN_QUEUE5_MAX_THD_SEL_Port_2_SWITCH_RESV_SHIFT 18
-#define BCHP_SWITCH_CORE_PN_QUEUE5_MAX_THD_SEL_Port_2_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: PN_QUEUE5_MAX_THD_SEL_Port_2 :: MAX_THD_SEL [17:00] */
-#define BCHP_SWITCH_CORE_PN_QUEUE5_MAX_THD_SEL_Port_2_MAX_THD_SEL_MASK 0x0003ffff
-#define BCHP_SWITCH_CORE_PN_QUEUE5_MAX_THD_SEL_Port_2_MAX_THD_SEL_SHIFT 0
-#define BCHP_SWITCH_CORE_PN_QUEUE5_MAX_THD_SEL_Port_2_MAX_THD_SEL_DEFAULT 0x00000000
-
-/***************************************************************************
- *PN_QUEUE5_MAX_THD_SEL_Port_3 - Port N, Byte-based Queue 5 Burst Size Configure Register
- ***************************************************************************/
-/* SWITCH_CORE :: PN_QUEUE5_MAX_THD_SEL_Port_3 :: SWITCH_RESV [31:18] */
-#define BCHP_SWITCH_CORE_PN_QUEUE5_MAX_THD_SEL_Port_3_SWITCH_RESV_MASK 0xfffc0000
-#define BCHP_SWITCH_CORE_PN_QUEUE5_MAX_THD_SEL_Port_3_SWITCH_RESV_SHIFT 18
-#define BCHP_SWITCH_CORE_PN_QUEUE5_MAX_THD_SEL_Port_3_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: PN_QUEUE5_MAX_THD_SEL_Port_3 :: MAX_THD_SEL [17:00] */
-#define BCHP_SWITCH_CORE_PN_QUEUE5_MAX_THD_SEL_Port_3_MAX_THD_SEL_MASK 0x0003ffff
-#define BCHP_SWITCH_CORE_PN_QUEUE5_MAX_THD_SEL_Port_3_MAX_THD_SEL_SHIFT 0
-#define BCHP_SWITCH_CORE_PN_QUEUE5_MAX_THD_SEL_Port_3_MAX_THD_SEL_DEFAULT 0x00000000
-
-/***************************************************************************
- *PN_QUEUE5_MAX_THD_SEL_Port_4 - Port N, Byte-based Queue 5 Burst Size Configure Register
- ***************************************************************************/
-/* SWITCH_CORE :: PN_QUEUE5_MAX_THD_SEL_Port_4 :: SWITCH_RESV [31:18] */
-#define BCHP_SWITCH_CORE_PN_QUEUE5_MAX_THD_SEL_Port_4_SWITCH_RESV_MASK 0xfffc0000
-#define BCHP_SWITCH_CORE_PN_QUEUE5_MAX_THD_SEL_Port_4_SWITCH_RESV_SHIFT 18
-#define BCHP_SWITCH_CORE_PN_QUEUE5_MAX_THD_SEL_Port_4_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: PN_QUEUE5_MAX_THD_SEL_Port_4 :: MAX_THD_SEL [17:00] */
-#define BCHP_SWITCH_CORE_PN_QUEUE5_MAX_THD_SEL_Port_4_MAX_THD_SEL_MASK 0x0003ffff
-#define BCHP_SWITCH_CORE_PN_QUEUE5_MAX_THD_SEL_Port_4_MAX_THD_SEL_SHIFT 0
-#define BCHP_SWITCH_CORE_PN_QUEUE5_MAX_THD_SEL_Port_4_MAX_THD_SEL_DEFAULT 0x00000000
-
-/***************************************************************************
- *PN_QUEUE5_MAX_THD_SEL_Port_5 - Port N, Byte-based Queue 5 Burst Size Configure Register
- ***************************************************************************/
-/* SWITCH_CORE :: PN_QUEUE5_MAX_THD_SEL_Port_5 :: SWITCH_RESV [31:18] */
-#define BCHP_SWITCH_CORE_PN_QUEUE5_MAX_THD_SEL_Port_5_SWITCH_RESV_MASK 0xfffc0000
-#define BCHP_SWITCH_CORE_PN_QUEUE5_MAX_THD_SEL_Port_5_SWITCH_RESV_SHIFT 18
-#define BCHP_SWITCH_CORE_PN_QUEUE5_MAX_THD_SEL_Port_5_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: PN_QUEUE5_MAX_THD_SEL_Port_5 :: MAX_THD_SEL [17:00] */
-#define BCHP_SWITCH_CORE_PN_QUEUE5_MAX_THD_SEL_Port_5_MAX_THD_SEL_MASK 0x0003ffff
-#define BCHP_SWITCH_CORE_PN_QUEUE5_MAX_THD_SEL_Port_5_MAX_THD_SEL_SHIFT 0
-#define BCHP_SWITCH_CORE_PN_QUEUE5_MAX_THD_SEL_Port_5_MAX_THD_SEL_DEFAULT 0x00000000
-
-/***************************************************************************
- *P7_QUEUE5_MAX_THD_SEL - Port 7, Byte-based Queue 5 Burst Size Configure Register
- ***************************************************************************/
-/* SWITCH_CORE :: P7_QUEUE5_MAX_THD_SEL :: SWITCH_RESV [31:18] */
-#define BCHP_SWITCH_CORE_P7_QUEUE5_MAX_THD_SEL_SWITCH_RESV_MASK 0xfffc0000
-#define BCHP_SWITCH_CORE_P7_QUEUE5_MAX_THD_SEL_SWITCH_RESV_SHIFT 18
-#define BCHP_SWITCH_CORE_P7_QUEUE5_MAX_THD_SEL_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: P7_QUEUE5_MAX_THD_SEL :: MAX_THD_SEL [17:00] */
-#define BCHP_SWITCH_CORE_P7_QUEUE5_MAX_THD_SEL_MAX_THD_SEL_MASK 0x0003ffff
-#define BCHP_SWITCH_CORE_P7_QUEUE5_MAX_THD_SEL_MAX_THD_SEL_SHIFT 0
-#define BCHP_SWITCH_CORE_P7_QUEUE5_MAX_THD_SEL_MAX_THD_SEL_DEFAULT 0x00000000
-
-/***************************************************************************
- *IMP_QUEUE5_MAX_THD_SEL - Port 8, Byte-based Queue 5 Burst Size Configure Register
- ***************************************************************************/
-/* SWITCH_CORE :: IMP_QUEUE5_MAX_THD_SEL :: SWITCH_RESV [31:18] */
-#define BCHP_SWITCH_CORE_IMP_QUEUE5_MAX_THD_SEL_SWITCH_RESV_MASK 0xfffc0000
-#define BCHP_SWITCH_CORE_IMP_QUEUE5_MAX_THD_SEL_SWITCH_RESV_SHIFT 18
-#define BCHP_SWITCH_CORE_IMP_QUEUE5_MAX_THD_SEL_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: IMP_QUEUE5_MAX_THD_SEL :: MAX_THD_SEL [17:00] */
-#define BCHP_SWITCH_CORE_IMP_QUEUE5_MAX_THD_SEL_MAX_THD_SEL_MASK 0x0003ffff
-#define BCHP_SWITCH_CORE_IMP_QUEUE5_MAX_THD_SEL_MAX_THD_SEL_SHIFT 0
-#define BCHP_SWITCH_CORE_IMP_QUEUE5_MAX_THD_SEL_MAX_THD_SEL_DEFAULT 0x00000000
-
-/***************************************************************************
- *PN_QUEUE5_SHAPER_STS_Port_0 - Port N, Queue 5 Shaper Status Register
- ***************************************************************************/
-/* SWITCH_CORE :: PN_QUEUE5_SHAPER_STS_Port_0 :: IN_PROFILE_FLAG [31:31] */
-#define BCHP_SWITCH_CORE_PN_QUEUE5_SHAPER_STS_Port_0_IN_PROFILE_FLAG_MASK 0x80000000
-#define BCHP_SWITCH_CORE_PN_QUEUE5_SHAPER_STS_Port_0_IN_PROFILE_FLAG_SHIFT 31
-#define BCHP_SWITCH_CORE_PN_QUEUE5_SHAPER_STS_Port_0_IN_PROFILE_FLAG_DEFAULT 0x00000001
-
-/* SWITCH_CORE :: PN_QUEUE5_SHAPER_STS_Port_0 :: SWITCH_RESV [30:29] */
-#define BCHP_SWITCH_CORE_PN_QUEUE5_SHAPER_STS_Port_0_SWITCH_RESV_MASK 0x60000000
-#define BCHP_SWITCH_CORE_PN_QUEUE5_SHAPER_STS_Port_0_SWITCH_RESV_SHIFT 29
-#define BCHP_SWITCH_CORE_PN_QUEUE5_SHAPER_STS_Port_0_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: PN_QUEUE5_SHAPER_STS_Port_0 :: BUCKET_CNT [28:00] */
-#define BCHP_SWITCH_CORE_PN_QUEUE5_SHAPER_STS_Port_0_BUCKET_CNT_MASK 0x1fffffff
-#define BCHP_SWITCH_CORE_PN_QUEUE5_SHAPER_STS_Port_0_BUCKET_CNT_SHIFT 0
-#define BCHP_SWITCH_CORE_PN_QUEUE5_SHAPER_STS_Port_0_BUCKET_CNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *PN_QUEUE5_SHAPER_STS_Port_1 - Port N, Queue 5 Shaper Status Register
- ***************************************************************************/
-/* SWITCH_CORE :: PN_QUEUE5_SHAPER_STS_Port_1 :: IN_PROFILE_FLAG [31:31] */
-#define BCHP_SWITCH_CORE_PN_QUEUE5_SHAPER_STS_Port_1_IN_PROFILE_FLAG_MASK 0x80000000
-#define BCHP_SWITCH_CORE_PN_QUEUE5_SHAPER_STS_Port_1_IN_PROFILE_FLAG_SHIFT 31
-#define BCHP_SWITCH_CORE_PN_QUEUE5_SHAPER_STS_Port_1_IN_PROFILE_FLAG_DEFAULT 0x00000001
-
-/* SWITCH_CORE :: PN_QUEUE5_SHAPER_STS_Port_1 :: SWITCH_RESV [30:29] */
-#define BCHP_SWITCH_CORE_PN_QUEUE5_SHAPER_STS_Port_1_SWITCH_RESV_MASK 0x60000000
-#define BCHP_SWITCH_CORE_PN_QUEUE5_SHAPER_STS_Port_1_SWITCH_RESV_SHIFT 29
-#define BCHP_SWITCH_CORE_PN_QUEUE5_SHAPER_STS_Port_1_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: PN_QUEUE5_SHAPER_STS_Port_1 :: BUCKET_CNT [28:00] */
-#define BCHP_SWITCH_CORE_PN_QUEUE5_SHAPER_STS_Port_1_BUCKET_CNT_MASK 0x1fffffff
-#define BCHP_SWITCH_CORE_PN_QUEUE5_SHAPER_STS_Port_1_BUCKET_CNT_SHIFT 0
-#define BCHP_SWITCH_CORE_PN_QUEUE5_SHAPER_STS_Port_1_BUCKET_CNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *PN_QUEUE5_SHAPER_STS_Port_2 - Port N, Queue 5 Shaper Status Register
- ***************************************************************************/
-/* SWITCH_CORE :: PN_QUEUE5_SHAPER_STS_Port_2 :: IN_PROFILE_FLAG [31:31] */
-#define BCHP_SWITCH_CORE_PN_QUEUE5_SHAPER_STS_Port_2_IN_PROFILE_FLAG_MASK 0x80000000
-#define BCHP_SWITCH_CORE_PN_QUEUE5_SHAPER_STS_Port_2_IN_PROFILE_FLAG_SHIFT 31
-#define BCHP_SWITCH_CORE_PN_QUEUE5_SHAPER_STS_Port_2_IN_PROFILE_FLAG_DEFAULT 0x00000001
-
-/* SWITCH_CORE :: PN_QUEUE5_SHAPER_STS_Port_2 :: SWITCH_RESV [30:29] */
-#define BCHP_SWITCH_CORE_PN_QUEUE5_SHAPER_STS_Port_2_SWITCH_RESV_MASK 0x60000000
-#define BCHP_SWITCH_CORE_PN_QUEUE5_SHAPER_STS_Port_2_SWITCH_RESV_SHIFT 29
-#define BCHP_SWITCH_CORE_PN_QUEUE5_SHAPER_STS_Port_2_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: PN_QUEUE5_SHAPER_STS_Port_2 :: BUCKET_CNT [28:00] */
-#define BCHP_SWITCH_CORE_PN_QUEUE5_SHAPER_STS_Port_2_BUCKET_CNT_MASK 0x1fffffff
-#define BCHP_SWITCH_CORE_PN_QUEUE5_SHAPER_STS_Port_2_BUCKET_CNT_SHIFT 0
-#define BCHP_SWITCH_CORE_PN_QUEUE5_SHAPER_STS_Port_2_BUCKET_CNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *PN_QUEUE5_SHAPER_STS_Port_3 - Port N, Queue 5 Shaper Status Register
- ***************************************************************************/
-/* SWITCH_CORE :: PN_QUEUE5_SHAPER_STS_Port_3 :: IN_PROFILE_FLAG [31:31] */
-#define BCHP_SWITCH_CORE_PN_QUEUE5_SHAPER_STS_Port_3_IN_PROFILE_FLAG_MASK 0x80000000
-#define BCHP_SWITCH_CORE_PN_QUEUE5_SHAPER_STS_Port_3_IN_PROFILE_FLAG_SHIFT 31
-#define BCHP_SWITCH_CORE_PN_QUEUE5_SHAPER_STS_Port_3_IN_PROFILE_FLAG_DEFAULT 0x00000001
-
-/* SWITCH_CORE :: PN_QUEUE5_SHAPER_STS_Port_3 :: SWITCH_RESV [30:29] */
-#define BCHP_SWITCH_CORE_PN_QUEUE5_SHAPER_STS_Port_3_SWITCH_RESV_MASK 0x60000000
-#define BCHP_SWITCH_CORE_PN_QUEUE5_SHAPER_STS_Port_3_SWITCH_RESV_SHIFT 29
-#define BCHP_SWITCH_CORE_PN_QUEUE5_SHAPER_STS_Port_3_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: PN_QUEUE5_SHAPER_STS_Port_3 :: BUCKET_CNT [28:00] */
-#define BCHP_SWITCH_CORE_PN_QUEUE5_SHAPER_STS_Port_3_BUCKET_CNT_MASK 0x1fffffff
-#define BCHP_SWITCH_CORE_PN_QUEUE5_SHAPER_STS_Port_3_BUCKET_CNT_SHIFT 0
-#define BCHP_SWITCH_CORE_PN_QUEUE5_SHAPER_STS_Port_3_BUCKET_CNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *PN_QUEUE5_SHAPER_STS_Port_4 - Port N, Queue 5 Shaper Status Register
- ***************************************************************************/
-/* SWITCH_CORE :: PN_QUEUE5_SHAPER_STS_Port_4 :: IN_PROFILE_FLAG [31:31] */
-#define BCHP_SWITCH_CORE_PN_QUEUE5_SHAPER_STS_Port_4_IN_PROFILE_FLAG_MASK 0x80000000
-#define BCHP_SWITCH_CORE_PN_QUEUE5_SHAPER_STS_Port_4_IN_PROFILE_FLAG_SHIFT 31
-#define BCHP_SWITCH_CORE_PN_QUEUE5_SHAPER_STS_Port_4_IN_PROFILE_FLAG_DEFAULT 0x00000001
-
-/* SWITCH_CORE :: PN_QUEUE5_SHAPER_STS_Port_4 :: SWITCH_RESV [30:29] */
-#define BCHP_SWITCH_CORE_PN_QUEUE5_SHAPER_STS_Port_4_SWITCH_RESV_MASK 0x60000000
-#define BCHP_SWITCH_CORE_PN_QUEUE5_SHAPER_STS_Port_4_SWITCH_RESV_SHIFT 29
-#define BCHP_SWITCH_CORE_PN_QUEUE5_SHAPER_STS_Port_4_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: PN_QUEUE5_SHAPER_STS_Port_4 :: BUCKET_CNT [28:00] */
-#define BCHP_SWITCH_CORE_PN_QUEUE5_SHAPER_STS_Port_4_BUCKET_CNT_MASK 0x1fffffff
-#define BCHP_SWITCH_CORE_PN_QUEUE5_SHAPER_STS_Port_4_BUCKET_CNT_SHIFT 0
-#define BCHP_SWITCH_CORE_PN_QUEUE5_SHAPER_STS_Port_4_BUCKET_CNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *PN_QUEUE5_SHAPER_STS_Port_5 - Port N, Queue 5 Shaper Status Register
- ***************************************************************************/
-/* SWITCH_CORE :: PN_QUEUE5_SHAPER_STS_Port_5 :: IN_PROFILE_FLAG [31:31] */
-#define BCHP_SWITCH_CORE_PN_QUEUE5_SHAPER_STS_Port_5_IN_PROFILE_FLAG_MASK 0x80000000
-#define BCHP_SWITCH_CORE_PN_QUEUE5_SHAPER_STS_Port_5_IN_PROFILE_FLAG_SHIFT 31
-#define BCHP_SWITCH_CORE_PN_QUEUE5_SHAPER_STS_Port_5_IN_PROFILE_FLAG_DEFAULT 0x00000001
-
-/* SWITCH_CORE :: PN_QUEUE5_SHAPER_STS_Port_5 :: SWITCH_RESV [30:29] */
-#define BCHP_SWITCH_CORE_PN_QUEUE5_SHAPER_STS_Port_5_SWITCH_RESV_MASK 0x60000000
-#define BCHP_SWITCH_CORE_PN_QUEUE5_SHAPER_STS_Port_5_SWITCH_RESV_SHIFT 29
-#define BCHP_SWITCH_CORE_PN_QUEUE5_SHAPER_STS_Port_5_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: PN_QUEUE5_SHAPER_STS_Port_5 :: BUCKET_CNT [28:00] */
-#define BCHP_SWITCH_CORE_PN_QUEUE5_SHAPER_STS_Port_5_BUCKET_CNT_MASK 0x1fffffff
-#define BCHP_SWITCH_CORE_PN_QUEUE5_SHAPER_STS_Port_5_BUCKET_CNT_SHIFT 0
-#define BCHP_SWITCH_CORE_PN_QUEUE5_SHAPER_STS_Port_5_BUCKET_CNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *P7_QUEUE5_SHAPER_STS - Port 7, Queue 5 Shaper Status Register
- ***************************************************************************/
-/* SWITCH_CORE :: P7_QUEUE5_SHAPER_STS :: IN_PROFILE_FLAG [31:31] */
-#define BCHP_SWITCH_CORE_P7_QUEUE5_SHAPER_STS_IN_PROFILE_FLAG_MASK 0x80000000
-#define BCHP_SWITCH_CORE_P7_QUEUE5_SHAPER_STS_IN_PROFILE_FLAG_SHIFT 31
-#define BCHP_SWITCH_CORE_P7_QUEUE5_SHAPER_STS_IN_PROFILE_FLAG_DEFAULT 0x00000001
-
-/* SWITCH_CORE :: P7_QUEUE5_SHAPER_STS :: SWITCH_RESV [30:29] */
-#define BCHP_SWITCH_CORE_P7_QUEUE5_SHAPER_STS_SWITCH_RESV_MASK 0x60000000
-#define BCHP_SWITCH_CORE_P7_QUEUE5_SHAPER_STS_SWITCH_RESV_SHIFT 29
-#define BCHP_SWITCH_CORE_P7_QUEUE5_SHAPER_STS_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: P7_QUEUE5_SHAPER_STS :: BUCKET_CNT [28:00] */
-#define BCHP_SWITCH_CORE_P7_QUEUE5_SHAPER_STS_BUCKET_CNT_MASK 0x1fffffff
-#define BCHP_SWITCH_CORE_P7_QUEUE5_SHAPER_STS_BUCKET_CNT_SHIFT 0
-#define BCHP_SWITCH_CORE_P7_QUEUE5_SHAPER_STS_BUCKET_CNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *IMP_QUEUE5_SHAPER_STS - Port 8, Queue 5 Shaper Status Register
- ***************************************************************************/
-/* SWITCH_CORE :: IMP_QUEUE5_SHAPER_STS :: IN_PROFILE_FLAG [31:31] */
-#define BCHP_SWITCH_CORE_IMP_QUEUE5_SHAPER_STS_IN_PROFILE_FLAG_MASK 0x80000000
-#define BCHP_SWITCH_CORE_IMP_QUEUE5_SHAPER_STS_IN_PROFILE_FLAG_SHIFT 31
-#define BCHP_SWITCH_CORE_IMP_QUEUE5_SHAPER_STS_IN_PROFILE_FLAG_DEFAULT 0x00000001
-
-/* SWITCH_CORE :: IMP_QUEUE5_SHAPER_STS :: SWITCH_RESV [30:29] */
-#define BCHP_SWITCH_CORE_IMP_QUEUE5_SHAPER_STS_SWITCH_RESV_MASK 0x60000000
-#define BCHP_SWITCH_CORE_IMP_QUEUE5_SHAPER_STS_SWITCH_RESV_SHIFT 29
-#define BCHP_SWITCH_CORE_IMP_QUEUE5_SHAPER_STS_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: IMP_QUEUE5_SHAPER_STS :: BUCKET_CNT [28:00] */
-#define BCHP_SWITCH_CORE_IMP_QUEUE5_SHAPER_STS_BUCKET_CNT_MASK 0x1fffffff
-#define BCHP_SWITCH_CORE_IMP_QUEUE5_SHAPER_STS_BUCKET_CNT_SHIFT 0
-#define BCHP_SWITCH_CORE_IMP_QUEUE5_SHAPER_STS_BUCKET_CNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *PN_QUEUE5_MAX_PACKET_REFRESH_Port_0 - Port N, Packet-based Queue 5 Shaping Rate Configure Register
- ***************************************************************************/
-/* SWITCH_CORE :: PN_QUEUE5_MAX_PACKET_REFRESH_Port_0 :: SWITCH_RESV [31:18] */
-#define BCHP_SWITCH_CORE_PN_QUEUE5_MAX_PACKET_REFRESH_Port_0_SWITCH_RESV_MASK 0xfffc0000
-#define BCHP_SWITCH_CORE_PN_QUEUE5_MAX_PACKET_REFRESH_Port_0_SWITCH_RESV_SHIFT 18
-#define BCHP_SWITCH_CORE_PN_QUEUE5_MAX_PACKET_REFRESH_Port_0_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: PN_QUEUE5_MAX_PACKET_REFRESH_Port_0 :: MAX_REFRESH [17:00] */
-#define BCHP_SWITCH_CORE_PN_QUEUE5_MAX_PACKET_REFRESH_Port_0_MAX_REFRESH_MASK 0x0003ffff
-#define BCHP_SWITCH_CORE_PN_QUEUE5_MAX_PACKET_REFRESH_Port_0_MAX_REFRESH_SHIFT 0
-#define BCHP_SWITCH_CORE_PN_QUEUE5_MAX_PACKET_REFRESH_Port_0_MAX_REFRESH_DEFAULT 0x00000000
-
-/***************************************************************************
- *PN_QUEUE5_MAX_PACKET_REFRESH_Port_1 - Port N, Packet-based Queue 5 Shaping Rate Configure Register
- ***************************************************************************/
-/* SWITCH_CORE :: PN_QUEUE5_MAX_PACKET_REFRESH_Port_1 :: SWITCH_RESV [31:18] */
-#define BCHP_SWITCH_CORE_PN_QUEUE5_MAX_PACKET_REFRESH_Port_1_SWITCH_RESV_MASK 0xfffc0000
-#define BCHP_SWITCH_CORE_PN_QUEUE5_MAX_PACKET_REFRESH_Port_1_SWITCH_RESV_SHIFT 18
-#define BCHP_SWITCH_CORE_PN_QUEUE5_MAX_PACKET_REFRESH_Port_1_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: PN_QUEUE5_MAX_PACKET_REFRESH_Port_1 :: MAX_REFRESH [17:00] */
-#define BCHP_SWITCH_CORE_PN_QUEUE5_MAX_PACKET_REFRESH_Port_1_MAX_REFRESH_MASK 0x0003ffff
-#define BCHP_SWITCH_CORE_PN_QUEUE5_MAX_PACKET_REFRESH_Port_1_MAX_REFRESH_SHIFT 0
-#define BCHP_SWITCH_CORE_PN_QUEUE5_MAX_PACKET_REFRESH_Port_1_MAX_REFRESH_DEFAULT 0x00000000
-
-/***************************************************************************
- *PN_QUEUE5_MAX_PACKET_REFRESH_Port_2 - Port N, Packet-based Queue 5 Shaping Rate Configure Register
- ***************************************************************************/
-/* SWITCH_CORE :: PN_QUEUE5_MAX_PACKET_REFRESH_Port_2 :: SWITCH_RESV [31:18] */
-#define BCHP_SWITCH_CORE_PN_QUEUE5_MAX_PACKET_REFRESH_Port_2_SWITCH_RESV_MASK 0xfffc0000
-#define BCHP_SWITCH_CORE_PN_QUEUE5_MAX_PACKET_REFRESH_Port_2_SWITCH_RESV_SHIFT 18
-#define BCHP_SWITCH_CORE_PN_QUEUE5_MAX_PACKET_REFRESH_Port_2_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: PN_QUEUE5_MAX_PACKET_REFRESH_Port_2 :: MAX_REFRESH [17:00] */
-#define BCHP_SWITCH_CORE_PN_QUEUE5_MAX_PACKET_REFRESH_Port_2_MAX_REFRESH_MASK 0x0003ffff
-#define BCHP_SWITCH_CORE_PN_QUEUE5_MAX_PACKET_REFRESH_Port_2_MAX_REFRESH_SHIFT 0
-#define BCHP_SWITCH_CORE_PN_QUEUE5_MAX_PACKET_REFRESH_Port_2_MAX_REFRESH_DEFAULT 0x00000000
-
-/***************************************************************************
- *PN_QUEUE5_MAX_PACKET_REFRESH_Port_3 - Port N, Packet-based Queue 5 Shaping Rate Configure Register
- ***************************************************************************/
-/* SWITCH_CORE :: PN_QUEUE5_MAX_PACKET_REFRESH_Port_3 :: SWITCH_RESV [31:18] */
-#define BCHP_SWITCH_CORE_PN_QUEUE5_MAX_PACKET_REFRESH_Port_3_SWITCH_RESV_MASK 0xfffc0000
-#define BCHP_SWITCH_CORE_PN_QUEUE5_MAX_PACKET_REFRESH_Port_3_SWITCH_RESV_SHIFT 18
-#define BCHP_SWITCH_CORE_PN_QUEUE5_MAX_PACKET_REFRESH_Port_3_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: PN_QUEUE5_MAX_PACKET_REFRESH_Port_3 :: MAX_REFRESH [17:00] */
-#define BCHP_SWITCH_CORE_PN_QUEUE5_MAX_PACKET_REFRESH_Port_3_MAX_REFRESH_MASK 0x0003ffff
-#define BCHP_SWITCH_CORE_PN_QUEUE5_MAX_PACKET_REFRESH_Port_3_MAX_REFRESH_SHIFT 0
-#define BCHP_SWITCH_CORE_PN_QUEUE5_MAX_PACKET_REFRESH_Port_3_MAX_REFRESH_DEFAULT 0x00000000
-
-/***************************************************************************
- *PN_QUEUE5_MAX_PACKET_REFRESH_Port_4 - Port N, Packet-based Queue 5 Shaping Rate Configure Register
- ***************************************************************************/
-/* SWITCH_CORE :: PN_QUEUE5_MAX_PACKET_REFRESH_Port_4 :: SWITCH_RESV [31:18] */
-#define BCHP_SWITCH_CORE_PN_QUEUE5_MAX_PACKET_REFRESH_Port_4_SWITCH_RESV_MASK 0xfffc0000
-#define BCHP_SWITCH_CORE_PN_QUEUE5_MAX_PACKET_REFRESH_Port_4_SWITCH_RESV_SHIFT 18
-#define BCHP_SWITCH_CORE_PN_QUEUE5_MAX_PACKET_REFRESH_Port_4_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: PN_QUEUE5_MAX_PACKET_REFRESH_Port_4 :: MAX_REFRESH [17:00] */
-#define BCHP_SWITCH_CORE_PN_QUEUE5_MAX_PACKET_REFRESH_Port_4_MAX_REFRESH_MASK 0x0003ffff
-#define BCHP_SWITCH_CORE_PN_QUEUE5_MAX_PACKET_REFRESH_Port_4_MAX_REFRESH_SHIFT 0
-#define BCHP_SWITCH_CORE_PN_QUEUE5_MAX_PACKET_REFRESH_Port_4_MAX_REFRESH_DEFAULT 0x00000000
-
-/***************************************************************************
- *PN_QUEUE5_MAX_PACKET_REFRESH_Port_5 - Port N, Packet-based Queue 5 Shaping Rate Configure Register
- ***************************************************************************/
-/* SWITCH_CORE :: PN_QUEUE5_MAX_PACKET_REFRESH_Port_5 :: SWITCH_RESV [31:18] */
-#define BCHP_SWITCH_CORE_PN_QUEUE5_MAX_PACKET_REFRESH_Port_5_SWITCH_RESV_MASK 0xfffc0000
-#define BCHP_SWITCH_CORE_PN_QUEUE5_MAX_PACKET_REFRESH_Port_5_SWITCH_RESV_SHIFT 18
-#define BCHP_SWITCH_CORE_PN_QUEUE5_MAX_PACKET_REFRESH_Port_5_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: PN_QUEUE5_MAX_PACKET_REFRESH_Port_5 :: MAX_REFRESH [17:00] */
-#define BCHP_SWITCH_CORE_PN_QUEUE5_MAX_PACKET_REFRESH_Port_5_MAX_REFRESH_MASK 0x0003ffff
-#define BCHP_SWITCH_CORE_PN_QUEUE5_MAX_PACKET_REFRESH_Port_5_MAX_REFRESH_SHIFT 0
-#define BCHP_SWITCH_CORE_PN_QUEUE5_MAX_PACKET_REFRESH_Port_5_MAX_REFRESH_DEFAULT 0x00000000
-
-/***************************************************************************
- *P7_QUEUE5_MAX_PACKET_REFRESH - Port 7, Packet-based Queue 5 Shaping Rate Configure Register
- ***************************************************************************/
-/* SWITCH_CORE :: P7_QUEUE5_MAX_PACKET_REFRESH :: SWITCH_RESV [31:18] */
-#define BCHP_SWITCH_CORE_P7_QUEUE5_MAX_PACKET_REFRESH_SWITCH_RESV_MASK 0xfffc0000
-#define BCHP_SWITCH_CORE_P7_QUEUE5_MAX_PACKET_REFRESH_SWITCH_RESV_SHIFT 18
-#define BCHP_SWITCH_CORE_P7_QUEUE5_MAX_PACKET_REFRESH_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: P7_QUEUE5_MAX_PACKET_REFRESH :: MAX_REFRESH [17:00] */
-#define BCHP_SWITCH_CORE_P7_QUEUE5_MAX_PACKET_REFRESH_MAX_REFRESH_MASK 0x0003ffff
-#define BCHP_SWITCH_CORE_P7_QUEUE5_MAX_PACKET_REFRESH_MAX_REFRESH_SHIFT 0
-#define BCHP_SWITCH_CORE_P7_QUEUE5_MAX_PACKET_REFRESH_MAX_REFRESH_DEFAULT 0x00000000
-
-/***************************************************************************
- *IMP_QUEUE5_MAX_PACKET_REFRESH - Port 8, Packet-based Queue 5 Shaping Rate Configure Register
- ***************************************************************************/
-/* SWITCH_CORE :: IMP_QUEUE5_MAX_PACKET_REFRESH :: SWITCH_RESV [31:18] */
-#define BCHP_SWITCH_CORE_IMP_QUEUE5_MAX_PACKET_REFRESH_SWITCH_RESV_MASK 0xfffc0000
-#define BCHP_SWITCH_CORE_IMP_QUEUE5_MAX_PACKET_REFRESH_SWITCH_RESV_SHIFT 18
-#define BCHP_SWITCH_CORE_IMP_QUEUE5_MAX_PACKET_REFRESH_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: IMP_QUEUE5_MAX_PACKET_REFRESH :: MAX_REFRESH [17:00] */
-#define BCHP_SWITCH_CORE_IMP_QUEUE5_MAX_PACKET_REFRESH_MAX_REFRESH_MASK 0x0003ffff
-#define BCHP_SWITCH_CORE_IMP_QUEUE5_MAX_PACKET_REFRESH_MAX_REFRESH_SHIFT 0
-#define BCHP_SWITCH_CORE_IMP_QUEUE5_MAX_PACKET_REFRESH_MAX_REFRESH_DEFAULT 0x00000000
-
-/***************************************************************************
- *EGRESS_SHAPER_Q5_CONFIG_REG_SPARE0 - Spare 0 Register (Not2Release)
- ***************************************************************************/
-/* SWITCH_CORE :: EGRESS_SHAPER_Q5_CONFIG_REG_SPARE0 :: EGRESS_SHAPER_Q5_CONFIG_REG_SPARE0 [31:00] */
-#define BCHP_SWITCH_CORE_EGRESS_SHAPER_Q5_CONFIG_REG_SPARE0_EGRESS_SHAPER_Q5_CONFIG_REG_SPARE0_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_EGRESS_SHAPER_Q5_CONFIG_REG_SPARE0_EGRESS_SHAPER_Q5_CONFIG_REG_SPARE0_SHIFT 0
-#define BCHP_SWITCH_CORE_EGRESS_SHAPER_Q5_CONFIG_REG_SPARE0_EGRESS_SHAPER_Q5_CONFIG_REG_SPARE0_DEFAULT 0x00000000
-
-/***************************************************************************
- *EGRESS_SHAPER_Q5_CONFIG_REG_SPARE1 - Spare 1 Register (Not2Release)
- ***************************************************************************/
-/* SWITCH_CORE :: EGRESS_SHAPER_Q5_CONFIG_REG_SPARE1 :: EGRESS_SHAPER_Q5_CONFIG_REG_SPARE1 [31:00] */
-#define BCHP_SWITCH_CORE_EGRESS_SHAPER_Q5_CONFIG_REG_SPARE1_EGRESS_SHAPER_Q5_CONFIG_REG_SPARE1_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_EGRESS_SHAPER_Q5_CONFIG_REG_SPARE1_EGRESS_SHAPER_Q5_CONFIG_REG_SPARE1_SHIFT 0
-#define BCHP_SWITCH_CORE_EGRESS_SHAPER_Q5_CONFIG_REG_SPARE1_EGRESS_SHAPER_Q5_CONFIG_REG_SPARE1_DEFAULT 0x00000000
-
-/***************************************************************************
- *PN_QUEUE5_MAX_PACKET_THD_SEL_Port_0 - Port N, Packet-based Queue 5 Burst Size Configure Register
- ***************************************************************************/
-/* SWITCH_CORE :: PN_QUEUE5_MAX_PACKET_THD_SEL_Port_0 :: SWITCH_RESV [31:18] */
-#define BCHP_SWITCH_CORE_PN_QUEUE5_MAX_PACKET_THD_SEL_Port_0_SWITCH_RESV_MASK 0xfffc0000
-#define BCHP_SWITCH_CORE_PN_QUEUE5_MAX_PACKET_THD_SEL_Port_0_SWITCH_RESV_SHIFT 18
-#define BCHP_SWITCH_CORE_PN_QUEUE5_MAX_PACKET_THD_SEL_Port_0_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: PN_QUEUE5_MAX_PACKET_THD_SEL_Port_0 :: MAX_THD_SEL [17:00] */
-#define BCHP_SWITCH_CORE_PN_QUEUE5_MAX_PACKET_THD_SEL_Port_0_MAX_THD_SEL_MASK 0x0003ffff
-#define BCHP_SWITCH_CORE_PN_QUEUE5_MAX_PACKET_THD_SEL_Port_0_MAX_THD_SEL_SHIFT 0
-#define BCHP_SWITCH_CORE_PN_QUEUE5_MAX_PACKET_THD_SEL_Port_0_MAX_THD_SEL_DEFAULT 0x00000000
-
-/***************************************************************************
- *PN_QUEUE5_MAX_PACKET_THD_SEL_Port_1 - Port N, Packet-based Queue 5 Burst Size Configure Register
- ***************************************************************************/
-/* SWITCH_CORE :: PN_QUEUE5_MAX_PACKET_THD_SEL_Port_1 :: SWITCH_RESV [31:18] */
-#define BCHP_SWITCH_CORE_PN_QUEUE5_MAX_PACKET_THD_SEL_Port_1_SWITCH_RESV_MASK 0xfffc0000
-#define BCHP_SWITCH_CORE_PN_QUEUE5_MAX_PACKET_THD_SEL_Port_1_SWITCH_RESV_SHIFT 18
-#define BCHP_SWITCH_CORE_PN_QUEUE5_MAX_PACKET_THD_SEL_Port_1_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: PN_QUEUE5_MAX_PACKET_THD_SEL_Port_1 :: MAX_THD_SEL [17:00] */
-#define BCHP_SWITCH_CORE_PN_QUEUE5_MAX_PACKET_THD_SEL_Port_1_MAX_THD_SEL_MASK 0x0003ffff
-#define BCHP_SWITCH_CORE_PN_QUEUE5_MAX_PACKET_THD_SEL_Port_1_MAX_THD_SEL_SHIFT 0
-#define BCHP_SWITCH_CORE_PN_QUEUE5_MAX_PACKET_THD_SEL_Port_1_MAX_THD_SEL_DEFAULT 0x00000000
-
-/***************************************************************************
- *PN_QUEUE5_MAX_PACKET_THD_SEL_Port_2 - Port N, Packet-based Queue 5 Burst Size Configure Register
- ***************************************************************************/
-/* SWITCH_CORE :: PN_QUEUE5_MAX_PACKET_THD_SEL_Port_2 :: SWITCH_RESV [31:18] */
-#define BCHP_SWITCH_CORE_PN_QUEUE5_MAX_PACKET_THD_SEL_Port_2_SWITCH_RESV_MASK 0xfffc0000
-#define BCHP_SWITCH_CORE_PN_QUEUE5_MAX_PACKET_THD_SEL_Port_2_SWITCH_RESV_SHIFT 18
-#define BCHP_SWITCH_CORE_PN_QUEUE5_MAX_PACKET_THD_SEL_Port_2_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: PN_QUEUE5_MAX_PACKET_THD_SEL_Port_2 :: MAX_THD_SEL [17:00] */
-#define BCHP_SWITCH_CORE_PN_QUEUE5_MAX_PACKET_THD_SEL_Port_2_MAX_THD_SEL_MASK 0x0003ffff
-#define BCHP_SWITCH_CORE_PN_QUEUE5_MAX_PACKET_THD_SEL_Port_2_MAX_THD_SEL_SHIFT 0
-#define BCHP_SWITCH_CORE_PN_QUEUE5_MAX_PACKET_THD_SEL_Port_2_MAX_THD_SEL_DEFAULT 0x00000000
-
-/***************************************************************************
- *PN_QUEUE5_MAX_PACKET_THD_SEL_Port_3 - Port N, Packet-based Queue 5 Burst Size Configure Register
- ***************************************************************************/
-/* SWITCH_CORE :: PN_QUEUE5_MAX_PACKET_THD_SEL_Port_3 :: SWITCH_RESV [31:18] */
-#define BCHP_SWITCH_CORE_PN_QUEUE5_MAX_PACKET_THD_SEL_Port_3_SWITCH_RESV_MASK 0xfffc0000
-#define BCHP_SWITCH_CORE_PN_QUEUE5_MAX_PACKET_THD_SEL_Port_3_SWITCH_RESV_SHIFT 18
-#define BCHP_SWITCH_CORE_PN_QUEUE5_MAX_PACKET_THD_SEL_Port_3_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: PN_QUEUE5_MAX_PACKET_THD_SEL_Port_3 :: MAX_THD_SEL [17:00] */
-#define BCHP_SWITCH_CORE_PN_QUEUE5_MAX_PACKET_THD_SEL_Port_3_MAX_THD_SEL_MASK 0x0003ffff
-#define BCHP_SWITCH_CORE_PN_QUEUE5_MAX_PACKET_THD_SEL_Port_3_MAX_THD_SEL_SHIFT 0
-#define BCHP_SWITCH_CORE_PN_QUEUE5_MAX_PACKET_THD_SEL_Port_3_MAX_THD_SEL_DEFAULT 0x00000000
-
-/***************************************************************************
- *PN_QUEUE5_MAX_PACKET_THD_SEL_Port_4 - Port N, Packet-based Queue 5 Burst Size Configure Register
- ***************************************************************************/
-/* SWITCH_CORE :: PN_QUEUE5_MAX_PACKET_THD_SEL_Port_4 :: SWITCH_RESV [31:18] */
-#define BCHP_SWITCH_CORE_PN_QUEUE5_MAX_PACKET_THD_SEL_Port_4_SWITCH_RESV_MASK 0xfffc0000
-#define BCHP_SWITCH_CORE_PN_QUEUE5_MAX_PACKET_THD_SEL_Port_4_SWITCH_RESV_SHIFT 18
-#define BCHP_SWITCH_CORE_PN_QUEUE5_MAX_PACKET_THD_SEL_Port_4_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: PN_QUEUE5_MAX_PACKET_THD_SEL_Port_4 :: MAX_THD_SEL [17:00] */
-#define BCHP_SWITCH_CORE_PN_QUEUE5_MAX_PACKET_THD_SEL_Port_4_MAX_THD_SEL_MASK 0x0003ffff
-#define BCHP_SWITCH_CORE_PN_QUEUE5_MAX_PACKET_THD_SEL_Port_4_MAX_THD_SEL_SHIFT 0
-#define BCHP_SWITCH_CORE_PN_QUEUE5_MAX_PACKET_THD_SEL_Port_4_MAX_THD_SEL_DEFAULT 0x00000000
-
-/***************************************************************************
- *PN_QUEUE5_MAX_PACKET_THD_SEL_Port_5 - Port N, Packet-based Queue 5 Burst Size Configure Register
- ***************************************************************************/
-/* SWITCH_CORE :: PN_QUEUE5_MAX_PACKET_THD_SEL_Port_5 :: SWITCH_RESV [31:18] */
-#define BCHP_SWITCH_CORE_PN_QUEUE5_MAX_PACKET_THD_SEL_Port_5_SWITCH_RESV_MASK 0xfffc0000
-#define BCHP_SWITCH_CORE_PN_QUEUE5_MAX_PACKET_THD_SEL_Port_5_SWITCH_RESV_SHIFT 18
-#define BCHP_SWITCH_CORE_PN_QUEUE5_MAX_PACKET_THD_SEL_Port_5_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: PN_QUEUE5_MAX_PACKET_THD_SEL_Port_5 :: MAX_THD_SEL [17:00] */
-#define BCHP_SWITCH_CORE_PN_QUEUE5_MAX_PACKET_THD_SEL_Port_5_MAX_THD_SEL_MASK 0x0003ffff
-#define BCHP_SWITCH_CORE_PN_QUEUE5_MAX_PACKET_THD_SEL_Port_5_MAX_THD_SEL_SHIFT 0
-#define BCHP_SWITCH_CORE_PN_QUEUE5_MAX_PACKET_THD_SEL_Port_5_MAX_THD_SEL_DEFAULT 0x00000000
-
-/***************************************************************************
- *P7_QUEUE5_MAX_PACKET_THD_SEL - Port 7, Packet-based Queue 5 Burst Size Configure Register
- ***************************************************************************/
-/* SWITCH_CORE :: P7_QUEUE5_MAX_PACKET_THD_SEL :: SWITCH_RESV [31:18] */
-#define BCHP_SWITCH_CORE_P7_QUEUE5_MAX_PACKET_THD_SEL_SWITCH_RESV_MASK 0xfffc0000
-#define BCHP_SWITCH_CORE_P7_QUEUE5_MAX_PACKET_THD_SEL_SWITCH_RESV_SHIFT 18
-#define BCHP_SWITCH_CORE_P7_QUEUE5_MAX_PACKET_THD_SEL_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: P7_QUEUE5_MAX_PACKET_THD_SEL :: MAX_THD_SEL [17:00] */
-#define BCHP_SWITCH_CORE_P7_QUEUE5_MAX_PACKET_THD_SEL_MAX_THD_SEL_MASK 0x0003ffff
-#define BCHP_SWITCH_CORE_P7_QUEUE5_MAX_PACKET_THD_SEL_MAX_THD_SEL_SHIFT 0
-#define BCHP_SWITCH_CORE_P7_QUEUE5_MAX_PACKET_THD_SEL_MAX_THD_SEL_DEFAULT 0x00000000
-
-/***************************************************************************
- *IMP_QUEUE5_MAX_PACKET_THD_SEL - Port 8, Packet-based Queue 5 Burst Size Configure Register
- ***************************************************************************/
-/* SWITCH_CORE :: IMP_QUEUE5_MAX_PACKET_THD_SEL :: SWITCH_RESV [31:18] */
-#define BCHP_SWITCH_CORE_IMP_QUEUE5_MAX_PACKET_THD_SEL_SWITCH_RESV_MASK 0xfffc0000
-#define BCHP_SWITCH_CORE_IMP_QUEUE5_MAX_PACKET_THD_SEL_SWITCH_RESV_SHIFT 18
-#define BCHP_SWITCH_CORE_IMP_QUEUE5_MAX_PACKET_THD_SEL_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: IMP_QUEUE5_MAX_PACKET_THD_SEL :: MAX_THD_SEL [17:00] */
-#define BCHP_SWITCH_CORE_IMP_QUEUE5_MAX_PACKET_THD_SEL_MAX_THD_SEL_MASK 0x0003ffff
-#define BCHP_SWITCH_CORE_IMP_QUEUE5_MAX_PACKET_THD_SEL_MAX_THD_SEL_SHIFT 0
-#define BCHP_SWITCH_CORE_IMP_QUEUE5_MAX_PACKET_THD_SEL_MAX_THD_SEL_DEFAULT 0x00000000
-
-/***************************************************************************
- *QUEUE5_AVB_SHAPING_MODE - Queue 5 AVB Shaping Mode Control Register
- ***************************************************************************/
-/* SWITCH_CORE :: QUEUE5_AVB_SHAPING_MODE :: reserved_for_padding0 [31:16] */
-#define BCHP_SWITCH_CORE_QUEUE5_AVB_SHAPING_MODE_reserved_for_padding0_MASK 0xffff0000
-#define BCHP_SWITCH_CORE_QUEUE5_AVB_SHAPING_MODE_reserved_for_padding0_SHIFT 16
-
-/* SWITCH_CORE :: QUEUE5_AVB_SHAPING_MODE :: SWITCH_RESV [15:09] */
-#define BCHP_SWITCH_CORE_QUEUE5_AVB_SHAPING_MODE_SWITCH_RESV_MASK 0x0000fe00
-#define BCHP_SWITCH_CORE_QUEUE5_AVB_SHAPING_MODE_SWITCH_RESV_SHIFT 9
-#define BCHP_SWITCH_CORE_QUEUE5_AVB_SHAPING_MODE_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: QUEUE5_AVB_SHAPING_MODE :: QUEUE5_AVB_SHAPING_MODE [08:00] */
-#define BCHP_SWITCH_CORE_QUEUE5_AVB_SHAPING_MODE_QUEUE5_AVB_SHAPING_MODE_MASK 0x000001ff
-#define BCHP_SWITCH_CORE_QUEUE5_AVB_SHAPING_MODE_QUEUE5_AVB_SHAPING_MODE_SHIFT 0
-#define BCHP_SWITCH_CORE_QUEUE5_AVB_SHAPING_MODE_QUEUE5_AVB_SHAPING_MODE_DEFAULT 0x00000000
-
-/***************************************************************************
- *QUEUE5_SHAPER_ENABLE - Queue 5 Shaper Enable Register
- ***************************************************************************/
-/* SWITCH_CORE :: QUEUE5_SHAPER_ENABLE :: reserved_for_padding0 [31:16] */
-#define BCHP_SWITCH_CORE_QUEUE5_SHAPER_ENABLE_reserved_for_padding0_MASK 0xffff0000
-#define BCHP_SWITCH_CORE_QUEUE5_SHAPER_ENABLE_reserved_for_padding0_SHIFT 16
-
-/* SWITCH_CORE :: QUEUE5_SHAPER_ENABLE :: SWITCH_RESV [15:09] */
-#define BCHP_SWITCH_CORE_QUEUE5_SHAPER_ENABLE_SWITCH_RESV_MASK 0x0000fe00
-#define BCHP_SWITCH_CORE_QUEUE5_SHAPER_ENABLE_SWITCH_RESV_SHIFT 9
-#define BCHP_SWITCH_CORE_QUEUE5_SHAPER_ENABLE_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: QUEUE5_SHAPER_ENABLE :: QUEUE5_SHAPER_ENABLE [08:00] */
-#define BCHP_SWITCH_CORE_QUEUE5_SHAPER_ENABLE_QUEUE5_SHAPER_ENABLE_MASK 0x000001ff
-#define BCHP_SWITCH_CORE_QUEUE5_SHAPER_ENABLE_QUEUE5_SHAPER_ENABLE_SHIFT 0
-#define BCHP_SWITCH_CORE_QUEUE5_SHAPER_ENABLE_QUEUE5_SHAPER_ENABLE_DEFAULT 0x00000000
-
-/***************************************************************************
- *QUEUE5_SHAPER_BUCKET_COUNT_SELECT - Queue 5 Bucket Count Select Register
- ***************************************************************************/
-/* SWITCH_CORE :: QUEUE5_SHAPER_BUCKET_COUNT_SELECT :: reserved_for_padding0 [31:16] */
-#define BCHP_SWITCH_CORE_QUEUE5_SHAPER_BUCKET_COUNT_SELECT_reserved_for_padding0_MASK 0xffff0000
-#define BCHP_SWITCH_CORE_QUEUE5_SHAPER_BUCKET_COUNT_SELECT_reserved_for_padding0_SHIFT 16
-
-/* SWITCH_CORE :: QUEUE5_SHAPER_BUCKET_COUNT_SELECT :: SWITCH_RESV [15:09] */
-#define BCHP_SWITCH_CORE_QUEUE5_SHAPER_BUCKET_COUNT_SELECT_SWITCH_RESV_MASK 0x0000fe00
-#define BCHP_SWITCH_CORE_QUEUE5_SHAPER_BUCKET_COUNT_SELECT_SWITCH_RESV_SHIFT 9
-#define BCHP_SWITCH_CORE_QUEUE5_SHAPER_BUCKET_COUNT_SELECT_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: QUEUE5_SHAPER_BUCKET_COUNT_SELECT :: QUEUE5_SHAPER_BUCKET_COUNT_SELECT [08:00] */
-#define BCHP_SWITCH_CORE_QUEUE5_SHAPER_BUCKET_COUNT_SELECT_QUEUE5_SHAPER_BUCKET_COUNT_SELECT_MASK 0x000001ff
-#define BCHP_SWITCH_CORE_QUEUE5_SHAPER_BUCKET_COUNT_SELECT_QUEUE5_SHAPER_BUCKET_COUNT_SELECT_SHIFT 0
-#define BCHP_SWITCH_CORE_QUEUE5_SHAPER_BUCKET_COUNT_SELECT_QUEUE5_SHAPER_BUCKET_COUNT_SELECT_DEFAULT 0x00000000
-
-/***************************************************************************
- *QUEUE5_SHAPER_BLOCKING - Queue 5 Shaper Blocking Control Register
- ***************************************************************************/
-/* SWITCH_CORE :: QUEUE5_SHAPER_BLOCKING :: reserved_for_padding0 [31:16] */
-#define BCHP_SWITCH_CORE_QUEUE5_SHAPER_BLOCKING_reserved_for_padding0_MASK 0xffff0000
-#define BCHP_SWITCH_CORE_QUEUE5_SHAPER_BLOCKING_reserved_for_padding0_SHIFT 16
-
-/* SWITCH_CORE :: QUEUE5_SHAPER_BLOCKING :: SWITCH_RESV [15:09] */
-#define BCHP_SWITCH_CORE_QUEUE5_SHAPER_BLOCKING_SWITCH_RESV_MASK 0x0000fe00
-#define BCHP_SWITCH_CORE_QUEUE5_SHAPER_BLOCKING_SWITCH_RESV_SHIFT 9
-#define BCHP_SWITCH_CORE_QUEUE5_SHAPER_BLOCKING_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: QUEUE5_SHAPER_BLOCKING :: QUEUE5_SHAPER_BLOCKING [08:00] */
-#define BCHP_SWITCH_CORE_QUEUE5_SHAPER_BLOCKING_QUEUE5_SHAPER_BLOCKING_MASK 0x000001ff
-#define BCHP_SWITCH_CORE_QUEUE5_SHAPER_BLOCKING_QUEUE5_SHAPER_BLOCKING_SHIFT 0
-#define BCHP_SWITCH_CORE_QUEUE5_SHAPER_BLOCKING_QUEUE5_SHAPER_BLOCKING_DEFAULT 0x00000000
-
-/***************************************************************************
- *PN_QUEUE6_MAX_REFRESH_Port_0 - Port N, Byte-based Queue 6 Shaping Rate Configure Register
- ***************************************************************************/
-/* SWITCH_CORE :: PN_QUEUE6_MAX_REFRESH_Port_0 :: SWITCH_RESV [31:18] */
-#define BCHP_SWITCH_CORE_PN_QUEUE6_MAX_REFRESH_Port_0_SWITCH_RESV_MASK 0xfffc0000
-#define BCHP_SWITCH_CORE_PN_QUEUE6_MAX_REFRESH_Port_0_SWITCH_RESV_SHIFT 18
-#define BCHP_SWITCH_CORE_PN_QUEUE6_MAX_REFRESH_Port_0_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: PN_QUEUE6_MAX_REFRESH_Port_0 :: MAX_REFRESH [17:00] */
-#define BCHP_SWITCH_CORE_PN_QUEUE6_MAX_REFRESH_Port_0_MAX_REFRESH_MASK 0x0003ffff
-#define BCHP_SWITCH_CORE_PN_QUEUE6_MAX_REFRESH_Port_0_MAX_REFRESH_SHIFT 0
-#define BCHP_SWITCH_CORE_PN_QUEUE6_MAX_REFRESH_Port_0_MAX_REFRESH_DEFAULT 0x00000000
-
-/***************************************************************************
- *PN_QUEUE6_MAX_REFRESH_Port_1 - Port N, Byte-based Queue 6 Shaping Rate Configure Register
- ***************************************************************************/
-/* SWITCH_CORE :: PN_QUEUE6_MAX_REFRESH_Port_1 :: SWITCH_RESV [31:18] */
-#define BCHP_SWITCH_CORE_PN_QUEUE6_MAX_REFRESH_Port_1_SWITCH_RESV_MASK 0xfffc0000
-#define BCHP_SWITCH_CORE_PN_QUEUE6_MAX_REFRESH_Port_1_SWITCH_RESV_SHIFT 18
-#define BCHP_SWITCH_CORE_PN_QUEUE6_MAX_REFRESH_Port_1_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: PN_QUEUE6_MAX_REFRESH_Port_1 :: MAX_REFRESH [17:00] */
-#define BCHP_SWITCH_CORE_PN_QUEUE6_MAX_REFRESH_Port_1_MAX_REFRESH_MASK 0x0003ffff
-#define BCHP_SWITCH_CORE_PN_QUEUE6_MAX_REFRESH_Port_1_MAX_REFRESH_SHIFT 0
-#define BCHP_SWITCH_CORE_PN_QUEUE6_MAX_REFRESH_Port_1_MAX_REFRESH_DEFAULT 0x00000000
-
-/***************************************************************************
- *PN_QUEUE6_MAX_REFRESH_Port_2 - Port N, Byte-based Queue 6 Shaping Rate Configure Register
- ***************************************************************************/
-/* SWITCH_CORE :: PN_QUEUE6_MAX_REFRESH_Port_2 :: SWITCH_RESV [31:18] */
-#define BCHP_SWITCH_CORE_PN_QUEUE6_MAX_REFRESH_Port_2_SWITCH_RESV_MASK 0xfffc0000
-#define BCHP_SWITCH_CORE_PN_QUEUE6_MAX_REFRESH_Port_2_SWITCH_RESV_SHIFT 18
-#define BCHP_SWITCH_CORE_PN_QUEUE6_MAX_REFRESH_Port_2_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: PN_QUEUE6_MAX_REFRESH_Port_2 :: MAX_REFRESH [17:00] */
-#define BCHP_SWITCH_CORE_PN_QUEUE6_MAX_REFRESH_Port_2_MAX_REFRESH_MASK 0x0003ffff
-#define BCHP_SWITCH_CORE_PN_QUEUE6_MAX_REFRESH_Port_2_MAX_REFRESH_SHIFT 0
-#define BCHP_SWITCH_CORE_PN_QUEUE6_MAX_REFRESH_Port_2_MAX_REFRESH_DEFAULT 0x00000000
-
-/***************************************************************************
- *PN_QUEUE6_MAX_REFRESH_Port_3 - Port N, Byte-based Queue 6 Shaping Rate Configure Register
- ***************************************************************************/
-/* SWITCH_CORE :: PN_QUEUE6_MAX_REFRESH_Port_3 :: SWITCH_RESV [31:18] */
-#define BCHP_SWITCH_CORE_PN_QUEUE6_MAX_REFRESH_Port_3_SWITCH_RESV_MASK 0xfffc0000
-#define BCHP_SWITCH_CORE_PN_QUEUE6_MAX_REFRESH_Port_3_SWITCH_RESV_SHIFT 18
-#define BCHP_SWITCH_CORE_PN_QUEUE6_MAX_REFRESH_Port_3_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: PN_QUEUE6_MAX_REFRESH_Port_3 :: MAX_REFRESH [17:00] */
-#define BCHP_SWITCH_CORE_PN_QUEUE6_MAX_REFRESH_Port_3_MAX_REFRESH_MASK 0x0003ffff
-#define BCHP_SWITCH_CORE_PN_QUEUE6_MAX_REFRESH_Port_3_MAX_REFRESH_SHIFT 0
-#define BCHP_SWITCH_CORE_PN_QUEUE6_MAX_REFRESH_Port_3_MAX_REFRESH_DEFAULT 0x00000000
-
-/***************************************************************************
- *PN_QUEUE6_MAX_REFRESH_Port_4 - Port N, Byte-based Queue 6 Shaping Rate Configure Register
- ***************************************************************************/
-/* SWITCH_CORE :: PN_QUEUE6_MAX_REFRESH_Port_4 :: SWITCH_RESV [31:18] */
-#define BCHP_SWITCH_CORE_PN_QUEUE6_MAX_REFRESH_Port_4_SWITCH_RESV_MASK 0xfffc0000
-#define BCHP_SWITCH_CORE_PN_QUEUE6_MAX_REFRESH_Port_4_SWITCH_RESV_SHIFT 18
-#define BCHP_SWITCH_CORE_PN_QUEUE6_MAX_REFRESH_Port_4_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: PN_QUEUE6_MAX_REFRESH_Port_4 :: MAX_REFRESH [17:00] */
-#define BCHP_SWITCH_CORE_PN_QUEUE6_MAX_REFRESH_Port_4_MAX_REFRESH_MASK 0x0003ffff
-#define BCHP_SWITCH_CORE_PN_QUEUE6_MAX_REFRESH_Port_4_MAX_REFRESH_SHIFT 0
-#define BCHP_SWITCH_CORE_PN_QUEUE6_MAX_REFRESH_Port_4_MAX_REFRESH_DEFAULT 0x00000000
-
-/***************************************************************************
- *PN_QUEUE6_MAX_REFRESH_Port_5 - Port N, Byte-based Queue 6 Shaping Rate Configure Register
- ***************************************************************************/
-/* SWITCH_CORE :: PN_QUEUE6_MAX_REFRESH_Port_5 :: SWITCH_RESV [31:18] */
-#define BCHP_SWITCH_CORE_PN_QUEUE6_MAX_REFRESH_Port_5_SWITCH_RESV_MASK 0xfffc0000
-#define BCHP_SWITCH_CORE_PN_QUEUE6_MAX_REFRESH_Port_5_SWITCH_RESV_SHIFT 18
-#define BCHP_SWITCH_CORE_PN_QUEUE6_MAX_REFRESH_Port_5_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: PN_QUEUE6_MAX_REFRESH_Port_5 :: MAX_REFRESH [17:00] */
-#define BCHP_SWITCH_CORE_PN_QUEUE6_MAX_REFRESH_Port_5_MAX_REFRESH_MASK 0x0003ffff
-#define BCHP_SWITCH_CORE_PN_QUEUE6_MAX_REFRESH_Port_5_MAX_REFRESH_SHIFT 0
-#define BCHP_SWITCH_CORE_PN_QUEUE6_MAX_REFRESH_Port_5_MAX_REFRESH_DEFAULT 0x00000000
-
-/***************************************************************************
- *P7_QUEUE6_MAX_REFRESH - Port 7, Byte-based Queue 6 Shaping Rate Configure Register
- ***************************************************************************/
-/* SWITCH_CORE :: P7_QUEUE6_MAX_REFRESH :: SWITCH_RESV [31:18] */
-#define BCHP_SWITCH_CORE_P7_QUEUE6_MAX_REFRESH_SWITCH_RESV_MASK 0xfffc0000
-#define BCHP_SWITCH_CORE_P7_QUEUE6_MAX_REFRESH_SWITCH_RESV_SHIFT 18
-#define BCHP_SWITCH_CORE_P7_QUEUE6_MAX_REFRESH_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: P7_QUEUE6_MAX_REFRESH :: MAX_REFRESH [17:00] */
-#define BCHP_SWITCH_CORE_P7_QUEUE6_MAX_REFRESH_MAX_REFRESH_MASK 0x0003ffff
-#define BCHP_SWITCH_CORE_P7_QUEUE6_MAX_REFRESH_MAX_REFRESH_SHIFT 0
-#define BCHP_SWITCH_CORE_P7_QUEUE6_MAX_REFRESH_MAX_REFRESH_DEFAULT 0x00000000
-
-/***************************************************************************
- *IMP_QUEUE6_MAX_REFRESH - Port 8, Byte-based Queue 6 Shaping Rate Configure Register
- ***************************************************************************/
-/* SWITCH_CORE :: IMP_QUEUE6_MAX_REFRESH :: SWITCH_RESV [31:18] */
-#define BCHP_SWITCH_CORE_IMP_QUEUE6_MAX_REFRESH_SWITCH_RESV_MASK 0xfffc0000
-#define BCHP_SWITCH_CORE_IMP_QUEUE6_MAX_REFRESH_SWITCH_RESV_SHIFT 18
-#define BCHP_SWITCH_CORE_IMP_QUEUE6_MAX_REFRESH_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: IMP_QUEUE6_MAX_REFRESH :: MAX_REFRESH [17:00] */
-#define BCHP_SWITCH_CORE_IMP_QUEUE6_MAX_REFRESH_MAX_REFRESH_MASK 0x0003ffff
-#define BCHP_SWITCH_CORE_IMP_QUEUE6_MAX_REFRESH_MAX_REFRESH_SHIFT 0
-#define BCHP_SWITCH_CORE_IMP_QUEUE6_MAX_REFRESH_MAX_REFRESH_DEFAULT 0x00000000
-
-/***************************************************************************
- *PN_QUEUE6_MAX_THD_SEL_Port_0 - Port N, Byte-based Queue 6 Burst Size Configure Register
- ***************************************************************************/
-/* SWITCH_CORE :: PN_QUEUE6_MAX_THD_SEL_Port_0 :: SWITCH_RESV [31:18] */
-#define BCHP_SWITCH_CORE_PN_QUEUE6_MAX_THD_SEL_Port_0_SWITCH_RESV_MASK 0xfffc0000
-#define BCHP_SWITCH_CORE_PN_QUEUE6_MAX_THD_SEL_Port_0_SWITCH_RESV_SHIFT 18
-#define BCHP_SWITCH_CORE_PN_QUEUE6_MAX_THD_SEL_Port_0_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: PN_QUEUE6_MAX_THD_SEL_Port_0 :: MAX_THD_SEL [17:00] */
-#define BCHP_SWITCH_CORE_PN_QUEUE6_MAX_THD_SEL_Port_0_MAX_THD_SEL_MASK 0x0003ffff
-#define BCHP_SWITCH_CORE_PN_QUEUE6_MAX_THD_SEL_Port_0_MAX_THD_SEL_SHIFT 0
-#define BCHP_SWITCH_CORE_PN_QUEUE6_MAX_THD_SEL_Port_0_MAX_THD_SEL_DEFAULT 0x00000000
-
-/***************************************************************************
- *PN_QUEUE6_MAX_THD_SEL_Port_1 - Port N, Byte-based Queue 6 Burst Size Configure Register
- ***************************************************************************/
-/* SWITCH_CORE :: PN_QUEUE6_MAX_THD_SEL_Port_1 :: SWITCH_RESV [31:18] */
-#define BCHP_SWITCH_CORE_PN_QUEUE6_MAX_THD_SEL_Port_1_SWITCH_RESV_MASK 0xfffc0000
-#define BCHP_SWITCH_CORE_PN_QUEUE6_MAX_THD_SEL_Port_1_SWITCH_RESV_SHIFT 18
-#define BCHP_SWITCH_CORE_PN_QUEUE6_MAX_THD_SEL_Port_1_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: PN_QUEUE6_MAX_THD_SEL_Port_1 :: MAX_THD_SEL [17:00] */
-#define BCHP_SWITCH_CORE_PN_QUEUE6_MAX_THD_SEL_Port_1_MAX_THD_SEL_MASK 0x0003ffff
-#define BCHP_SWITCH_CORE_PN_QUEUE6_MAX_THD_SEL_Port_1_MAX_THD_SEL_SHIFT 0
-#define BCHP_SWITCH_CORE_PN_QUEUE6_MAX_THD_SEL_Port_1_MAX_THD_SEL_DEFAULT 0x00000000
-
-/***************************************************************************
- *PN_QUEUE6_MAX_THD_SEL_Port_2 - Port N, Byte-based Queue 6 Burst Size Configure Register
- ***************************************************************************/
-/* SWITCH_CORE :: PN_QUEUE6_MAX_THD_SEL_Port_2 :: SWITCH_RESV [31:18] */
-#define BCHP_SWITCH_CORE_PN_QUEUE6_MAX_THD_SEL_Port_2_SWITCH_RESV_MASK 0xfffc0000
-#define BCHP_SWITCH_CORE_PN_QUEUE6_MAX_THD_SEL_Port_2_SWITCH_RESV_SHIFT 18
-#define BCHP_SWITCH_CORE_PN_QUEUE6_MAX_THD_SEL_Port_2_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: PN_QUEUE6_MAX_THD_SEL_Port_2 :: MAX_THD_SEL [17:00] */
-#define BCHP_SWITCH_CORE_PN_QUEUE6_MAX_THD_SEL_Port_2_MAX_THD_SEL_MASK 0x0003ffff
-#define BCHP_SWITCH_CORE_PN_QUEUE6_MAX_THD_SEL_Port_2_MAX_THD_SEL_SHIFT 0
-#define BCHP_SWITCH_CORE_PN_QUEUE6_MAX_THD_SEL_Port_2_MAX_THD_SEL_DEFAULT 0x00000000
-
-/***************************************************************************
- *PN_QUEUE6_MAX_THD_SEL_Port_3 - Port N, Byte-based Queue 6 Burst Size Configure Register
- ***************************************************************************/
-/* SWITCH_CORE :: PN_QUEUE6_MAX_THD_SEL_Port_3 :: SWITCH_RESV [31:18] */
-#define BCHP_SWITCH_CORE_PN_QUEUE6_MAX_THD_SEL_Port_3_SWITCH_RESV_MASK 0xfffc0000
-#define BCHP_SWITCH_CORE_PN_QUEUE6_MAX_THD_SEL_Port_3_SWITCH_RESV_SHIFT 18
-#define BCHP_SWITCH_CORE_PN_QUEUE6_MAX_THD_SEL_Port_3_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: PN_QUEUE6_MAX_THD_SEL_Port_3 :: MAX_THD_SEL [17:00] */
-#define BCHP_SWITCH_CORE_PN_QUEUE6_MAX_THD_SEL_Port_3_MAX_THD_SEL_MASK 0x0003ffff
-#define BCHP_SWITCH_CORE_PN_QUEUE6_MAX_THD_SEL_Port_3_MAX_THD_SEL_SHIFT 0
-#define BCHP_SWITCH_CORE_PN_QUEUE6_MAX_THD_SEL_Port_3_MAX_THD_SEL_DEFAULT 0x00000000
-
-/***************************************************************************
- *PN_QUEUE6_MAX_THD_SEL_Port_4 - Port N, Byte-based Queue 6 Burst Size Configure Register
- ***************************************************************************/
-/* SWITCH_CORE :: PN_QUEUE6_MAX_THD_SEL_Port_4 :: SWITCH_RESV [31:18] */
-#define BCHP_SWITCH_CORE_PN_QUEUE6_MAX_THD_SEL_Port_4_SWITCH_RESV_MASK 0xfffc0000
-#define BCHP_SWITCH_CORE_PN_QUEUE6_MAX_THD_SEL_Port_4_SWITCH_RESV_SHIFT 18
-#define BCHP_SWITCH_CORE_PN_QUEUE6_MAX_THD_SEL_Port_4_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: PN_QUEUE6_MAX_THD_SEL_Port_4 :: MAX_THD_SEL [17:00] */
-#define BCHP_SWITCH_CORE_PN_QUEUE6_MAX_THD_SEL_Port_4_MAX_THD_SEL_MASK 0x0003ffff
-#define BCHP_SWITCH_CORE_PN_QUEUE6_MAX_THD_SEL_Port_4_MAX_THD_SEL_SHIFT 0
-#define BCHP_SWITCH_CORE_PN_QUEUE6_MAX_THD_SEL_Port_4_MAX_THD_SEL_DEFAULT 0x00000000
-
-/***************************************************************************
- *PN_QUEUE6_MAX_THD_SEL_Port_5 - Port N, Byte-based Queue 6 Burst Size Configure Register
- ***************************************************************************/
-/* SWITCH_CORE :: PN_QUEUE6_MAX_THD_SEL_Port_5 :: SWITCH_RESV [31:18] */
-#define BCHP_SWITCH_CORE_PN_QUEUE6_MAX_THD_SEL_Port_5_SWITCH_RESV_MASK 0xfffc0000
-#define BCHP_SWITCH_CORE_PN_QUEUE6_MAX_THD_SEL_Port_5_SWITCH_RESV_SHIFT 18
-#define BCHP_SWITCH_CORE_PN_QUEUE6_MAX_THD_SEL_Port_5_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: PN_QUEUE6_MAX_THD_SEL_Port_5 :: MAX_THD_SEL [17:00] */
-#define BCHP_SWITCH_CORE_PN_QUEUE6_MAX_THD_SEL_Port_5_MAX_THD_SEL_MASK 0x0003ffff
-#define BCHP_SWITCH_CORE_PN_QUEUE6_MAX_THD_SEL_Port_5_MAX_THD_SEL_SHIFT 0
-#define BCHP_SWITCH_CORE_PN_QUEUE6_MAX_THD_SEL_Port_5_MAX_THD_SEL_DEFAULT 0x00000000
-
-/***************************************************************************
- *P7_QUEUE6_MAX_THD_SEL - Port 7, Byte-based Queue 6 Burst Size Configure Register
- ***************************************************************************/
-/* SWITCH_CORE :: P7_QUEUE6_MAX_THD_SEL :: SWITCH_RESV [31:18] */
-#define BCHP_SWITCH_CORE_P7_QUEUE6_MAX_THD_SEL_SWITCH_RESV_MASK 0xfffc0000
-#define BCHP_SWITCH_CORE_P7_QUEUE6_MAX_THD_SEL_SWITCH_RESV_SHIFT 18
-#define BCHP_SWITCH_CORE_P7_QUEUE6_MAX_THD_SEL_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: P7_QUEUE6_MAX_THD_SEL :: MAX_THD_SEL [17:00] */
-#define BCHP_SWITCH_CORE_P7_QUEUE6_MAX_THD_SEL_MAX_THD_SEL_MASK 0x0003ffff
-#define BCHP_SWITCH_CORE_P7_QUEUE6_MAX_THD_SEL_MAX_THD_SEL_SHIFT 0
-#define BCHP_SWITCH_CORE_P7_QUEUE6_MAX_THD_SEL_MAX_THD_SEL_DEFAULT 0x00000000
-
-/***************************************************************************
- *IMP_QUEUE6_MAX_THD_SEL - Port 8, Byte-based Queue 6 Burst Size Configure Register
- ***************************************************************************/
-/* SWITCH_CORE :: IMP_QUEUE6_MAX_THD_SEL :: SWITCH_RESV [31:18] */
-#define BCHP_SWITCH_CORE_IMP_QUEUE6_MAX_THD_SEL_SWITCH_RESV_MASK 0xfffc0000
-#define BCHP_SWITCH_CORE_IMP_QUEUE6_MAX_THD_SEL_SWITCH_RESV_SHIFT 18
-#define BCHP_SWITCH_CORE_IMP_QUEUE6_MAX_THD_SEL_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: IMP_QUEUE6_MAX_THD_SEL :: MAX_THD_SEL [17:00] */
-#define BCHP_SWITCH_CORE_IMP_QUEUE6_MAX_THD_SEL_MAX_THD_SEL_MASK 0x0003ffff
-#define BCHP_SWITCH_CORE_IMP_QUEUE6_MAX_THD_SEL_MAX_THD_SEL_SHIFT 0
-#define BCHP_SWITCH_CORE_IMP_QUEUE6_MAX_THD_SEL_MAX_THD_SEL_DEFAULT 0x00000000
-
-/***************************************************************************
- *PN_QUEUE6_SHAPER_STS_Port_0 - Port N, Queue 6 Shaper Status Register
- ***************************************************************************/
-/* SWITCH_CORE :: PN_QUEUE6_SHAPER_STS_Port_0 :: IN_PROFILE_FLAG [31:31] */
-#define BCHP_SWITCH_CORE_PN_QUEUE6_SHAPER_STS_Port_0_IN_PROFILE_FLAG_MASK 0x80000000
-#define BCHP_SWITCH_CORE_PN_QUEUE6_SHAPER_STS_Port_0_IN_PROFILE_FLAG_SHIFT 31
-#define BCHP_SWITCH_CORE_PN_QUEUE6_SHAPER_STS_Port_0_IN_PROFILE_FLAG_DEFAULT 0x00000001
-
-/* SWITCH_CORE :: PN_QUEUE6_SHAPER_STS_Port_0 :: SWITCH_RESV [30:29] */
-#define BCHP_SWITCH_CORE_PN_QUEUE6_SHAPER_STS_Port_0_SWITCH_RESV_MASK 0x60000000
-#define BCHP_SWITCH_CORE_PN_QUEUE6_SHAPER_STS_Port_0_SWITCH_RESV_SHIFT 29
-#define BCHP_SWITCH_CORE_PN_QUEUE6_SHAPER_STS_Port_0_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: PN_QUEUE6_SHAPER_STS_Port_0 :: BUCKET_CNT [28:00] */
-#define BCHP_SWITCH_CORE_PN_QUEUE6_SHAPER_STS_Port_0_BUCKET_CNT_MASK 0x1fffffff
-#define BCHP_SWITCH_CORE_PN_QUEUE6_SHAPER_STS_Port_0_BUCKET_CNT_SHIFT 0
-#define BCHP_SWITCH_CORE_PN_QUEUE6_SHAPER_STS_Port_0_BUCKET_CNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *PN_QUEUE6_SHAPER_STS_Port_1 - Port N, Queue 6 Shaper Status Register
- ***************************************************************************/
-/* SWITCH_CORE :: PN_QUEUE6_SHAPER_STS_Port_1 :: IN_PROFILE_FLAG [31:31] */
-#define BCHP_SWITCH_CORE_PN_QUEUE6_SHAPER_STS_Port_1_IN_PROFILE_FLAG_MASK 0x80000000
-#define BCHP_SWITCH_CORE_PN_QUEUE6_SHAPER_STS_Port_1_IN_PROFILE_FLAG_SHIFT 31
-#define BCHP_SWITCH_CORE_PN_QUEUE6_SHAPER_STS_Port_1_IN_PROFILE_FLAG_DEFAULT 0x00000001
-
-/* SWITCH_CORE :: PN_QUEUE6_SHAPER_STS_Port_1 :: SWITCH_RESV [30:29] */
-#define BCHP_SWITCH_CORE_PN_QUEUE6_SHAPER_STS_Port_1_SWITCH_RESV_MASK 0x60000000
-#define BCHP_SWITCH_CORE_PN_QUEUE6_SHAPER_STS_Port_1_SWITCH_RESV_SHIFT 29
-#define BCHP_SWITCH_CORE_PN_QUEUE6_SHAPER_STS_Port_1_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: PN_QUEUE6_SHAPER_STS_Port_1 :: BUCKET_CNT [28:00] */
-#define BCHP_SWITCH_CORE_PN_QUEUE6_SHAPER_STS_Port_1_BUCKET_CNT_MASK 0x1fffffff
-#define BCHP_SWITCH_CORE_PN_QUEUE6_SHAPER_STS_Port_1_BUCKET_CNT_SHIFT 0
-#define BCHP_SWITCH_CORE_PN_QUEUE6_SHAPER_STS_Port_1_BUCKET_CNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *PN_QUEUE6_SHAPER_STS_Port_2 - Port N, Queue 6 Shaper Status Register
- ***************************************************************************/
-/* SWITCH_CORE :: PN_QUEUE6_SHAPER_STS_Port_2 :: IN_PROFILE_FLAG [31:31] */
-#define BCHP_SWITCH_CORE_PN_QUEUE6_SHAPER_STS_Port_2_IN_PROFILE_FLAG_MASK 0x80000000
-#define BCHP_SWITCH_CORE_PN_QUEUE6_SHAPER_STS_Port_2_IN_PROFILE_FLAG_SHIFT 31
-#define BCHP_SWITCH_CORE_PN_QUEUE6_SHAPER_STS_Port_2_IN_PROFILE_FLAG_DEFAULT 0x00000001
-
-/* SWITCH_CORE :: PN_QUEUE6_SHAPER_STS_Port_2 :: SWITCH_RESV [30:29] */
-#define BCHP_SWITCH_CORE_PN_QUEUE6_SHAPER_STS_Port_2_SWITCH_RESV_MASK 0x60000000
-#define BCHP_SWITCH_CORE_PN_QUEUE6_SHAPER_STS_Port_2_SWITCH_RESV_SHIFT 29
-#define BCHP_SWITCH_CORE_PN_QUEUE6_SHAPER_STS_Port_2_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: PN_QUEUE6_SHAPER_STS_Port_2 :: BUCKET_CNT [28:00] */
-#define BCHP_SWITCH_CORE_PN_QUEUE6_SHAPER_STS_Port_2_BUCKET_CNT_MASK 0x1fffffff
-#define BCHP_SWITCH_CORE_PN_QUEUE6_SHAPER_STS_Port_2_BUCKET_CNT_SHIFT 0
-#define BCHP_SWITCH_CORE_PN_QUEUE6_SHAPER_STS_Port_2_BUCKET_CNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *PN_QUEUE6_SHAPER_STS_Port_3 - Port N, Queue 6 Shaper Status Register
- ***************************************************************************/
-/* SWITCH_CORE :: PN_QUEUE6_SHAPER_STS_Port_3 :: IN_PROFILE_FLAG [31:31] */
-#define BCHP_SWITCH_CORE_PN_QUEUE6_SHAPER_STS_Port_3_IN_PROFILE_FLAG_MASK 0x80000000
-#define BCHP_SWITCH_CORE_PN_QUEUE6_SHAPER_STS_Port_3_IN_PROFILE_FLAG_SHIFT 31
-#define BCHP_SWITCH_CORE_PN_QUEUE6_SHAPER_STS_Port_3_IN_PROFILE_FLAG_DEFAULT 0x00000001
-
-/* SWITCH_CORE :: PN_QUEUE6_SHAPER_STS_Port_3 :: SWITCH_RESV [30:29] */
-#define BCHP_SWITCH_CORE_PN_QUEUE6_SHAPER_STS_Port_3_SWITCH_RESV_MASK 0x60000000
-#define BCHP_SWITCH_CORE_PN_QUEUE6_SHAPER_STS_Port_3_SWITCH_RESV_SHIFT 29
-#define BCHP_SWITCH_CORE_PN_QUEUE6_SHAPER_STS_Port_3_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: PN_QUEUE6_SHAPER_STS_Port_3 :: BUCKET_CNT [28:00] */
-#define BCHP_SWITCH_CORE_PN_QUEUE6_SHAPER_STS_Port_3_BUCKET_CNT_MASK 0x1fffffff
-#define BCHP_SWITCH_CORE_PN_QUEUE6_SHAPER_STS_Port_3_BUCKET_CNT_SHIFT 0
-#define BCHP_SWITCH_CORE_PN_QUEUE6_SHAPER_STS_Port_3_BUCKET_CNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *PN_QUEUE6_SHAPER_STS_Port_4 - Port N, Queue 6 Shaper Status Register
- ***************************************************************************/
-/* SWITCH_CORE :: PN_QUEUE6_SHAPER_STS_Port_4 :: IN_PROFILE_FLAG [31:31] */
-#define BCHP_SWITCH_CORE_PN_QUEUE6_SHAPER_STS_Port_4_IN_PROFILE_FLAG_MASK 0x80000000
-#define BCHP_SWITCH_CORE_PN_QUEUE6_SHAPER_STS_Port_4_IN_PROFILE_FLAG_SHIFT 31
-#define BCHP_SWITCH_CORE_PN_QUEUE6_SHAPER_STS_Port_4_IN_PROFILE_FLAG_DEFAULT 0x00000001
-
-/* SWITCH_CORE :: PN_QUEUE6_SHAPER_STS_Port_4 :: SWITCH_RESV [30:29] */
-#define BCHP_SWITCH_CORE_PN_QUEUE6_SHAPER_STS_Port_4_SWITCH_RESV_MASK 0x60000000
-#define BCHP_SWITCH_CORE_PN_QUEUE6_SHAPER_STS_Port_4_SWITCH_RESV_SHIFT 29
-#define BCHP_SWITCH_CORE_PN_QUEUE6_SHAPER_STS_Port_4_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: PN_QUEUE6_SHAPER_STS_Port_4 :: BUCKET_CNT [28:00] */
-#define BCHP_SWITCH_CORE_PN_QUEUE6_SHAPER_STS_Port_4_BUCKET_CNT_MASK 0x1fffffff
-#define BCHP_SWITCH_CORE_PN_QUEUE6_SHAPER_STS_Port_4_BUCKET_CNT_SHIFT 0
-#define BCHP_SWITCH_CORE_PN_QUEUE6_SHAPER_STS_Port_4_BUCKET_CNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *PN_QUEUE6_SHAPER_STS_Port_5 - Port N, Queue 6 Shaper Status Register
- ***************************************************************************/
-/* SWITCH_CORE :: PN_QUEUE6_SHAPER_STS_Port_5 :: IN_PROFILE_FLAG [31:31] */
-#define BCHP_SWITCH_CORE_PN_QUEUE6_SHAPER_STS_Port_5_IN_PROFILE_FLAG_MASK 0x80000000
-#define BCHP_SWITCH_CORE_PN_QUEUE6_SHAPER_STS_Port_5_IN_PROFILE_FLAG_SHIFT 31
-#define BCHP_SWITCH_CORE_PN_QUEUE6_SHAPER_STS_Port_5_IN_PROFILE_FLAG_DEFAULT 0x00000001
-
-/* SWITCH_CORE :: PN_QUEUE6_SHAPER_STS_Port_5 :: SWITCH_RESV [30:29] */
-#define BCHP_SWITCH_CORE_PN_QUEUE6_SHAPER_STS_Port_5_SWITCH_RESV_MASK 0x60000000
-#define BCHP_SWITCH_CORE_PN_QUEUE6_SHAPER_STS_Port_5_SWITCH_RESV_SHIFT 29
-#define BCHP_SWITCH_CORE_PN_QUEUE6_SHAPER_STS_Port_5_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: PN_QUEUE6_SHAPER_STS_Port_5 :: BUCKET_CNT [28:00] */
-#define BCHP_SWITCH_CORE_PN_QUEUE6_SHAPER_STS_Port_5_BUCKET_CNT_MASK 0x1fffffff
-#define BCHP_SWITCH_CORE_PN_QUEUE6_SHAPER_STS_Port_5_BUCKET_CNT_SHIFT 0
-#define BCHP_SWITCH_CORE_PN_QUEUE6_SHAPER_STS_Port_5_BUCKET_CNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *P7_QUEUE6_SHAPER_STS - Port 7, Queue 6 Shaper Status Register
- ***************************************************************************/
-/* SWITCH_CORE :: P7_QUEUE6_SHAPER_STS :: IN_PROFILE_FLAG [31:31] */
-#define BCHP_SWITCH_CORE_P7_QUEUE6_SHAPER_STS_IN_PROFILE_FLAG_MASK 0x80000000
-#define BCHP_SWITCH_CORE_P7_QUEUE6_SHAPER_STS_IN_PROFILE_FLAG_SHIFT 31
-#define BCHP_SWITCH_CORE_P7_QUEUE6_SHAPER_STS_IN_PROFILE_FLAG_DEFAULT 0x00000001
-
-/* SWITCH_CORE :: P7_QUEUE6_SHAPER_STS :: SWITCH_RESV [30:29] */
-#define BCHP_SWITCH_CORE_P7_QUEUE6_SHAPER_STS_SWITCH_RESV_MASK 0x60000000
-#define BCHP_SWITCH_CORE_P7_QUEUE6_SHAPER_STS_SWITCH_RESV_SHIFT 29
-#define BCHP_SWITCH_CORE_P7_QUEUE6_SHAPER_STS_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: P7_QUEUE6_SHAPER_STS :: BUCKET_CNT [28:00] */
-#define BCHP_SWITCH_CORE_P7_QUEUE6_SHAPER_STS_BUCKET_CNT_MASK 0x1fffffff
-#define BCHP_SWITCH_CORE_P7_QUEUE6_SHAPER_STS_BUCKET_CNT_SHIFT 0
-#define BCHP_SWITCH_CORE_P7_QUEUE6_SHAPER_STS_BUCKET_CNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *IMP_QUEUE6_SHAPER_STS - Port 8, Queue 6 Shaper Status Register
- ***************************************************************************/
-/* SWITCH_CORE :: IMP_QUEUE6_SHAPER_STS :: IN_PROFILE_FLAG [31:31] */
-#define BCHP_SWITCH_CORE_IMP_QUEUE6_SHAPER_STS_IN_PROFILE_FLAG_MASK 0x80000000
-#define BCHP_SWITCH_CORE_IMP_QUEUE6_SHAPER_STS_IN_PROFILE_FLAG_SHIFT 31
-#define BCHP_SWITCH_CORE_IMP_QUEUE6_SHAPER_STS_IN_PROFILE_FLAG_DEFAULT 0x00000001
-
-/* SWITCH_CORE :: IMP_QUEUE6_SHAPER_STS :: SWITCH_RESV [30:29] */
-#define BCHP_SWITCH_CORE_IMP_QUEUE6_SHAPER_STS_SWITCH_RESV_MASK 0x60000000
-#define BCHP_SWITCH_CORE_IMP_QUEUE6_SHAPER_STS_SWITCH_RESV_SHIFT 29
-#define BCHP_SWITCH_CORE_IMP_QUEUE6_SHAPER_STS_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: IMP_QUEUE6_SHAPER_STS :: BUCKET_CNT [28:00] */
-#define BCHP_SWITCH_CORE_IMP_QUEUE6_SHAPER_STS_BUCKET_CNT_MASK 0x1fffffff
-#define BCHP_SWITCH_CORE_IMP_QUEUE6_SHAPER_STS_BUCKET_CNT_SHIFT 0
-#define BCHP_SWITCH_CORE_IMP_QUEUE6_SHAPER_STS_BUCKET_CNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *PN_QUEUE6_MAX_PACKET_REFRESH_Port_0 - Port N, Packet-based Queue 6 Shaping Rate Configure Register
- ***************************************************************************/
-/* SWITCH_CORE :: PN_QUEUE6_MAX_PACKET_REFRESH_Port_0 :: SWITCH_RESV [31:18] */
-#define BCHP_SWITCH_CORE_PN_QUEUE6_MAX_PACKET_REFRESH_Port_0_SWITCH_RESV_MASK 0xfffc0000
-#define BCHP_SWITCH_CORE_PN_QUEUE6_MAX_PACKET_REFRESH_Port_0_SWITCH_RESV_SHIFT 18
-#define BCHP_SWITCH_CORE_PN_QUEUE6_MAX_PACKET_REFRESH_Port_0_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: PN_QUEUE6_MAX_PACKET_REFRESH_Port_0 :: MAX_REFRESH [17:00] */
-#define BCHP_SWITCH_CORE_PN_QUEUE6_MAX_PACKET_REFRESH_Port_0_MAX_REFRESH_MASK 0x0003ffff
-#define BCHP_SWITCH_CORE_PN_QUEUE6_MAX_PACKET_REFRESH_Port_0_MAX_REFRESH_SHIFT 0
-#define BCHP_SWITCH_CORE_PN_QUEUE6_MAX_PACKET_REFRESH_Port_0_MAX_REFRESH_DEFAULT 0x00000000
-
-/***************************************************************************
- *PN_QUEUE6_MAX_PACKET_REFRESH_Port_1 - Port N, Packet-based Queue 6 Shaping Rate Configure Register
- ***************************************************************************/
-/* SWITCH_CORE :: PN_QUEUE6_MAX_PACKET_REFRESH_Port_1 :: SWITCH_RESV [31:18] */
-#define BCHP_SWITCH_CORE_PN_QUEUE6_MAX_PACKET_REFRESH_Port_1_SWITCH_RESV_MASK 0xfffc0000
-#define BCHP_SWITCH_CORE_PN_QUEUE6_MAX_PACKET_REFRESH_Port_1_SWITCH_RESV_SHIFT 18
-#define BCHP_SWITCH_CORE_PN_QUEUE6_MAX_PACKET_REFRESH_Port_1_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: PN_QUEUE6_MAX_PACKET_REFRESH_Port_1 :: MAX_REFRESH [17:00] */
-#define BCHP_SWITCH_CORE_PN_QUEUE6_MAX_PACKET_REFRESH_Port_1_MAX_REFRESH_MASK 0x0003ffff
-#define BCHP_SWITCH_CORE_PN_QUEUE6_MAX_PACKET_REFRESH_Port_1_MAX_REFRESH_SHIFT 0
-#define BCHP_SWITCH_CORE_PN_QUEUE6_MAX_PACKET_REFRESH_Port_1_MAX_REFRESH_DEFAULT 0x00000000
-
-/***************************************************************************
- *PN_QUEUE6_MAX_PACKET_REFRESH_Port_2 - Port N, Packet-based Queue 6 Shaping Rate Configure Register
- ***************************************************************************/
-/* SWITCH_CORE :: PN_QUEUE6_MAX_PACKET_REFRESH_Port_2 :: SWITCH_RESV [31:18] */
-#define BCHP_SWITCH_CORE_PN_QUEUE6_MAX_PACKET_REFRESH_Port_2_SWITCH_RESV_MASK 0xfffc0000
-#define BCHP_SWITCH_CORE_PN_QUEUE6_MAX_PACKET_REFRESH_Port_2_SWITCH_RESV_SHIFT 18
-#define BCHP_SWITCH_CORE_PN_QUEUE6_MAX_PACKET_REFRESH_Port_2_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: PN_QUEUE6_MAX_PACKET_REFRESH_Port_2 :: MAX_REFRESH [17:00] */
-#define BCHP_SWITCH_CORE_PN_QUEUE6_MAX_PACKET_REFRESH_Port_2_MAX_REFRESH_MASK 0x0003ffff
-#define BCHP_SWITCH_CORE_PN_QUEUE6_MAX_PACKET_REFRESH_Port_2_MAX_REFRESH_SHIFT 0
-#define BCHP_SWITCH_CORE_PN_QUEUE6_MAX_PACKET_REFRESH_Port_2_MAX_REFRESH_DEFAULT 0x00000000
-
-/***************************************************************************
- *PN_QUEUE6_MAX_PACKET_REFRESH_Port_3 - Port N, Packet-based Queue 6 Shaping Rate Configure Register
- ***************************************************************************/
-/* SWITCH_CORE :: PN_QUEUE6_MAX_PACKET_REFRESH_Port_3 :: SWITCH_RESV [31:18] */
-#define BCHP_SWITCH_CORE_PN_QUEUE6_MAX_PACKET_REFRESH_Port_3_SWITCH_RESV_MASK 0xfffc0000
-#define BCHP_SWITCH_CORE_PN_QUEUE6_MAX_PACKET_REFRESH_Port_3_SWITCH_RESV_SHIFT 18
-#define BCHP_SWITCH_CORE_PN_QUEUE6_MAX_PACKET_REFRESH_Port_3_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: PN_QUEUE6_MAX_PACKET_REFRESH_Port_3 :: MAX_REFRESH [17:00] */
-#define BCHP_SWITCH_CORE_PN_QUEUE6_MAX_PACKET_REFRESH_Port_3_MAX_REFRESH_MASK 0x0003ffff
-#define BCHP_SWITCH_CORE_PN_QUEUE6_MAX_PACKET_REFRESH_Port_3_MAX_REFRESH_SHIFT 0
-#define BCHP_SWITCH_CORE_PN_QUEUE6_MAX_PACKET_REFRESH_Port_3_MAX_REFRESH_DEFAULT 0x00000000
-
-/***************************************************************************
- *PN_QUEUE6_MAX_PACKET_REFRESH_Port_4 - Port N, Packet-based Queue 6 Shaping Rate Configure Register
- ***************************************************************************/
-/* SWITCH_CORE :: PN_QUEUE6_MAX_PACKET_REFRESH_Port_4 :: SWITCH_RESV [31:18] */
-#define BCHP_SWITCH_CORE_PN_QUEUE6_MAX_PACKET_REFRESH_Port_4_SWITCH_RESV_MASK 0xfffc0000
-#define BCHP_SWITCH_CORE_PN_QUEUE6_MAX_PACKET_REFRESH_Port_4_SWITCH_RESV_SHIFT 18
-#define BCHP_SWITCH_CORE_PN_QUEUE6_MAX_PACKET_REFRESH_Port_4_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: PN_QUEUE6_MAX_PACKET_REFRESH_Port_4 :: MAX_REFRESH [17:00] */
-#define BCHP_SWITCH_CORE_PN_QUEUE6_MAX_PACKET_REFRESH_Port_4_MAX_REFRESH_MASK 0x0003ffff
-#define BCHP_SWITCH_CORE_PN_QUEUE6_MAX_PACKET_REFRESH_Port_4_MAX_REFRESH_SHIFT 0
-#define BCHP_SWITCH_CORE_PN_QUEUE6_MAX_PACKET_REFRESH_Port_4_MAX_REFRESH_DEFAULT 0x00000000
-
-/***************************************************************************
- *PN_QUEUE6_MAX_PACKET_REFRESH_Port_5 - Port N, Packet-based Queue 6 Shaping Rate Configure Register
- ***************************************************************************/
-/* SWITCH_CORE :: PN_QUEUE6_MAX_PACKET_REFRESH_Port_5 :: SWITCH_RESV [31:18] */
-#define BCHP_SWITCH_CORE_PN_QUEUE6_MAX_PACKET_REFRESH_Port_5_SWITCH_RESV_MASK 0xfffc0000
-#define BCHP_SWITCH_CORE_PN_QUEUE6_MAX_PACKET_REFRESH_Port_5_SWITCH_RESV_SHIFT 18
-#define BCHP_SWITCH_CORE_PN_QUEUE6_MAX_PACKET_REFRESH_Port_5_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: PN_QUEUE6_MAX_PACKET_REFRESH_Port_5 :: MAX_REFRESH [17:00] */
-#define BCHP_SWITCH_CORE_PN_QUEUE6_MAX_PACKET_REFRESH_Port_5_MAX_REFRESH_MASK 0x0003ffff
-#define BCHP_SWITCH_CORE_PN_QUEUE6_MAX_PACKET_REFRESH_Port_5_MAX_REFRESH_SHIFT 0
-#define BCHP_SWITCH_CORE_PN_QUEUE6_MAX_PACKET_REFRESH_Port_5_MAX_REFRESH_DEFAULT 0x00000000
-
-/***************************************************************************
- *P7_QUEUE6_MAX_PACKET_REFRESH - Port 7, Packet-based Queue 6 Shaping Rate Configure Register
- ***************************************************************************/
-/* SWITCH_CORE :: P7_QUEUE6_MAX_PACKET_REFRESH :: SWITCH_RESV [31:18] */
-#define BCHP_SWITCH_CORE_P7_QUEUE6_MAX_PACKET_REFRESH_SWITCH_RESV_MASK 0xfffc0000
-#define BCHP_SWITCH_CORE_P7_QUEUE6_MAX_PACKET_REFRESH_SWITCH_RESV_SHIFT 18
-#define BCHP_SWITCH_CORE_P7_QUEUE6_MAX_PACKET_REFRESH_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: P7_QUEUE6_MAX_PACKET_REFRESH :: MAX_REFRESH [17:00] */
-#define BCHP_SWITCH_CORE_P7_QUEUE6_MAX_PACKET_REFRESH_MAX_REFRESH_MASK 0x0003ffff
-#define BCHP_SWITCH_CORE_P7_QUEUE6_MAX_PACKET_REFRESH_MAX_REFRESH_SHIFT 0
-#define BCHP_SWITCH_CORE_P7_QUEUE6_MAX_PACKET_REFRESH_MAX_REFRESH_DEFAULT 0x00000000
-
-/***************************************************************************
- *IMP_QUEUE6_MAX_PACKET_REFRESH - Port 8, Packet-based Queue 6 Shaping Rate Configure Register
- ***************************************************************************/
-/* SWITCH_CORE :: IMP_QUEUE6_MAX_PACKET_REFRESH :: SWITCH_RESV [31:18] */
-#define BCHP_SWITCH_CORE_IMP_QUEUE6_MAX_PACKET_REFRESH_SWITCH_RESV_MASK 0xfffc0000
-#define BCHP_SWITCH_CORE_IMP_QUEUE6_MAX_PACKET_REFRESH_SWITCH_RESV_SHIFT 18
-#define BCHP_SWITCH_CORE_IMP_QUEUE6_MAX_PACKET_REFRESH_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: IMP_QUEUE6_MAX_PACKET_REFRESH :: MAX_REFRESH [17:00] */
-#define BCHP_SWITCH_CORE_IMP_QUEUE6_MAX_PACKET_REFRESH_MAX_REFRESH_MASK 0x0003ffff
-#define BCHP_SWITCH_CORE_IMP_QUEUE6_MAX_PACKET_REFRESH_MAX_REFRESH_SHIFT 0
-#define BCHP_SWITCH_CORE_IMP_QUEUE6_MAX_PACKET_REFRESH_MAX_REFRESH_DEFAULT 0x00000000
-
-/***************************************************************************
- *EGRESS_SHAPER_Q6_CONFIG_REG_SPARE0 - Spare 0 Register (Not2Release)
- ***************************************************************************/
-/* SWITCH_CORE :: EGRESS_SHAPER_Q6_CONFIG_REG_SPARE0 :: EGRESS_SHAPER_Q6_CONFIG_REG_SPARE0 [31:00] */
-#define BCHP_SWITCH_CORE_EGRESS_SHAPER_Q6_CONFIG_REG_SPARE0_EGRESS_SHAPER_Q6_CONFIG_REG_SPARE0_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_EGRESS_SHAPER_Q6_CONFIG_REG_SPARE0_EGRESS_SHAPER_Q6_CONFIG_REG_SPARE0_SHIFT 0
-#define BCHP_SWITCH_CORE_EGRESS_SHAPER_Q6_CONFIG_REG_SPARE0_EGRESS_SHAPER_Q6_CONFIG_REG_SPARE0_DEFAULT 0x00000000
-
-/***************************************************************************
- *EGRESS_SHAPER_Q6_CONFIG_REG_SPARE1 - Spare 1 Register (Not2Release)
- ***************************************************************************/
-/* SWITCH_CORE :: EGRESS_SHAPER_Q6_CONFIG_REG_SPARE1 :: EGRESS_SHAPER_Q6_CONFIG_REG_SPARE1 [31:00] */
-#define BCHP_SWITCH_CORE_EGRESS_SHAPER_Q6_CONFIG_REG_SPARE1_EGRESS_SHAPER_Q6_CONFIG_REG_SPARE1_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_EGRESS_SHAPER_Q6_CONFIG_REG_SPARE1_EGRESS_SHAPER_Q6_CONFIG_REG_SPARE1_SHIFT 0
-#define BCHP_SWITCH_CORE_EGRESS_SHAPER_Q6_CONFIG_REG_SPARE1_EGRESS_SHAPER_Q6_CONFIG_REG_SPARE1_DEFAULT 0x00000000
-
-/***************************************************************************
- *PN_QUEUE6_MAX_PACKET_THD_SEL_Port_0 - Port N, Packet-based Queue 6 Burst Size Configure Register
- ***************************************************************************/
-/* SWITCH_CORE :: PN_QUEUE6_MAX_PACKET_THD_SEL_Port_0 :: SWITCH_RESV [31:18] */
-#define BCHP_SWITCH_CORE_PN_QUEUE6_MAX_PACKET_THD_SEL_Port_0_SWITCH_RESV_MASK 0xfffc0000
-#define BCHP_SWITCH_CORE_PN_QUEUE6_MAX_PACKET_THD_SEL_Port_0_SWITCH_RESV_SHIFT 18
-#define BCHP_SWITCH_CORE_PN_QUEUE6_MAX_PACKET_THD_SEL_Port_0_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: PN_QUEUE6_MAX_PACKET_THD_SEL_Port_0 :: MAX_THD_SEL [17:00] */
-#define BCHP_SWITCH_CORE_PN_QUEUE6_MAX_PACKET_THD_SEL_Port_0_MAX_THD_SEL_MASK 0x0003ffff
-#define BCHP_SWITCH_CORE_PN_QUEUE6_MAX_PACKET_THD_SEL_Port_0_MAX_THD_SEL_SHIFT 0
-#define BCHP_SWITCH_CORE_PN_QUEUE6_MAX_PACKET_THD_SEL_Port_0_MAX_THD_SEL_DEFAULT 0x00000000
-
-/***************************************************************************
- *PN_QUEUE6_MAX_PACKET_THD_SEL_Port_1 - Port N, Packet-based Queue 6 Burst Size Configure Register
- ***************************************************************************/
-/* SWITCH_CORE :: PN_QUEUE6_MAX_PACKET_THD_SEL_Port_1 :: SWITCH_RESV [31:18] */
-#define BCHP_SWITCH_CORE_PN_QUEUE6_MAX_PACKET_THD_SEL_Port_1_SWITCH_RESV_MASK 0xfffc0000
-#define BCHP_SWITCH_CORE_PN_QUEUE6_MAX_PACKET_THD_SEL_Port_1_SWITCH_RESV_SHIFT 18
-#define BCHP_SWITCH_CORE_PN_QUEUE6_MAX_PACKET_THD_SEL_Port_1_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: PN_QUEUE6_MAX_PACKET_THD_SEL_Port_1 :: MAX_THD_SEL [17:00] */
-#define BCHP_SWITCH_CORE_PN_QUEUE6_MAX_PACKET_THD_SEL_Port_1_MAX_THD_SEL_MASK 0x0003ffff
-#define BCHP_SWITCH_CORE_PN_QUEUE6_MAX_PACKET_THD_SEL_Port_1_MAX_THD_SEL_SHIFT 0
-#define BCHP_SWITCH_CORE_PN_QUEUE6_MAX_PACKET_THD_SEL_Port_1_MAX_THD_SEL_DEFAULT 0x00000000
-
-/***************************************************************************
- *PN_QUEUE6_MAX_PACKET_THD_SEL_Port_2 - Port N, Packet-based Queue 6 Burst Size Configure Register
- ***************************************************************************/
-/* SWITCH_CORE :: PN_QUEUE6_MAX_PACKET_THD_SEL_Port_2 :: SWITCH_RESV [31:18] */
-#define BCHP_SWITCH_CORE_PN_QUEUE6_MAX_PACKET_THD_SEL_Port_2_SWITCH_RESV_MASK 0xfffc0000
-#define BCHP_SWITCH_CORE_PN_QUEUE6_MAX_PACKET_THD_SEL_Port_2_SWITCH_RESV_SHIFT 18
-#define BCHP_SWITCH_CORE_PN_QUEUE6_MAX_PACKET_THD_SEL_Port_2_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: PN_QUEUE6_MAX_PACKET_THD_SEL_Port_2 :: MAX_THD_SEL [17:00] */
-#define BCHP_SWITCH_CORE_PN_QUEUE6_MAX_PACKET_THD_SEL_Port_2_MAX_THD_SEL_MASK 0x0003ffff
-#define BCHP_SWITCH_CORE_PN_QUEUE6_MAX_PACKET_THD_SEL_Port_2_MAX_THD_SEL_SHIFT 0
-#define BCHP_SWITCH_CORE_PN_QUEUE6_MAX_PACKET_THD_SEL_Port_2_MAX_THD_SEL_DEFAULT 0x00000000
-
-/***************************************************************************
- *PN_QUEUE6_MAX_PACKET_THD_SEL_Port_3 - Port N, Packet-based Queue 6 Burst Size Configure Register
- ***************************************************************************/
-/* SWITCH_CORE :: PN_QUEUE6_MAX_PACKET_THD_SEL_Port_3 :: SWITCH_RESV [31:18] */
-#define BCHP_SWITCH_CORE_PN_QUEUE6_MAX_PACKET_THD_SEL_Port_3_SWITCH_RESV_MASK 0xfffc0000
-#define BCHP_SWITCH_CORE_PN_QUEUE6_MAX_PACKET_THD_SEL_Port_3_SWITCH_RESV_SHIFT 18
-#define BCHP_SWITCH_CORE_PN_QUEUE6_MAX_PACKET_THD_SEL_Port_3_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: PN_QUEUE6_MAX_PACKET_THD_SEL_Port_3 :: MAX_THD_SEL [17:00] */
-#define BCHP_SWITCH_CORE_PN_QUEUE6_MAX_PACKET_THD_SEL_Port_3_MAX_THD_SEL_MASK 0x0003ffff
-#define BCHP_SWITCH_CORE_PN_QUEUE6_MAX_PACKET_THD_SEL_Port_3_MAX_THD_SEL_SHIFT 0
-#define BCHP_SWITCH_CORE_PN_QUEUE6_MAX_PACKET_THD_SEL_Port_3_MAX_THD_SEL_DEFAULT 0x00000000
-
-/***************************************************************************
- *PN_QUEUE6_MAX_PACKET_THD_SEL_Port_4 - Port N, Packet-based Queue 6 Burst Size Configure Register
- ***************************************************************************/
-/* SWITCH_CORE :: PN_QUEUE6_MAX_PACKET_THD_SEL_Port_4 :: SWITCH_RESV [31:18] */
-#define BCHP_SWITCH_CORE_PN_QUEUE6_MAX_PACKET_THD_SEL_Port_4_SWITCH_RESV_MASK 0xfffc0000
-#define BCHP_SWITCH_CORE_PN_QUEUE6_MAX_PACKET_THD_SEL_Port_4_SWITCH_RESV_SHIFT 18
-#define BCHP_SWITCH_CORE_PN_QUEUE6_MAX_PACKET_THD_SEL_Port_4_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: PN_QUEUE6_MAX_PACKET_THD_SEL_Port_4 :: MAX_THD_SEL [17:00] */
-#define BCHP_SWITCH_CORE_PN_QUEUE6_MAX_PACKET_THD_SEL_Port_4_MAX_THD_SEL_MASK 0x0003ffff
-#define BCHP_SWITCH_CORE_PN_QUEUE6_MAX_PACKET_THD_SEL_Port_4_MAX_THD_SEL_SHIFT 0
-#define BCHP_SWITCH_CORE_PN_QUEUE6_MAX_PACKET_THD_SEL_Port_4_MAX_THD_SEL_DEFAULT 0x00000000
-
-/***************************************************************************
- *PN_QUEUE6_MAX_PACKET_THD_SEL_Port_5 - Port N, Packet-based Queue 6 Burst Size Configure Register
- ***************************************************************************/
-/* SWITCH_CORE :: PN_QUEUE6_MAX_PACKET_THD_SEL_Port_5 :: SWITCH_RESV [31:18] */
-#define BCHP_SWITCH_CORE_PN_QUEUE6_MAX_PACKET_THD_SEL_Port_5_SWITCH_RESV_MASK 0xfffc0000
-#define BCHP_SWITCH_CORE_PN_QUEUE6_MAX_PACKET_THD_SEL_Port_5_SWITCH_RESV_SHIFT 18
-#define BCHP_SWITCH_CORE_PN_QUEUE6_MAX_PACKET_THD_SEL_Port_5_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: PN_QUEUE6_MAX_PACKET_THD_SEL_Port_5 :: MAX_THD_SEL [17:00] */
-#define BCHP_SWITCH_CORE_PN_QUEUE6_MAX_PACKET_THD_SEL_Port_5_MAX_THD_SEL_MASK 0x0003ffff
-#define BCHP_SWITCH_CORE_PN_QUEUE6_MAX_PACKET_THD_SEL_Port_5_MAX_THD_SEL_SHIFT 0
-#define BCHP_SWITCH_CORE_PN_QUEUE6_MAX_PACKET_THD_SEL_Port_5_MAX_THD_SEL_DEFAULT 0x00000000
-
-/***************************************************************************
- *P7_QUEUE6_MAX_PACKET_THD_SEL - Port 7, Packet-based Queue 6 Burst Size Configure Register
- ***************************************************************************/
-/* SWITCH_CORE :: P7_QUEUE6_MAX_PACKET_THD_SEL :: SWITCH_RESV [31:18] */
-#define BCHP_SWITCH_CORE_P7_QUEUE6_MAX_PACKET_THD_SEL_SWITCH_RESV_MASK 0xfffc0000
-#define BCHP_SWITCH_CORE_P7_QUEUE6_MAX_PACKET_THD_SEL_SWITCH_RESV_SHIFT 18
-#define BCHP_SWITCH_CORE_P7_QUEUE6_MAX_PACKET_THD_SEL_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: P7_QUEUE6_MAX_PACKET_THD_SEL :: MAX_THD_SEL [17:00] */
-#define BCHP_SWITCH_CORE_P7_QUEUE6_MAX_PACKET_THD_SEL_MAX_THD_SEL_MASK 0x0003ffff
-#define BCHP_SWITCH_CORE_P7_QUEUE6_MAX_PACKET_THD_SEL_MAX_THD_SEL_SHIFT 0
-#define BCHP_SWITCH_CORE_P7_QUEUE6_MAX_PACKET_THD_SEL_MAX_THD_SEL_DEFAULT 0x00000000
-
-/***************************************************************************
- *IMP_QUEUE6_MAX_PACKET_THD_SEL - Port 8, Packet-based Queue 6 Burst Size Configure Register
- ***************************************************************************/
-/* SWITCH_CORE :: IMP_QUEUE6_MAX_PACKET_THD_SEL :: SWITCH_RESV [31:18] */
-#define BCHP_SWITCH_CORE_IMP_QUEUE6_MAX_PACKET_THD_SEL_SWITCH_RESV_MASK 0xfffc0000
-#define BCHP_SWITCH_CORE_IMP_QUEUE6_MAX_PACKET_THD_SEL_SWITCH_RESV_SHIFT 18
-#define BCHP_SWITCH_CORE_IMP_QUEUE6_MAX_PACKET_THD_SEL_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: IMP_QUEUE6_MAX_PACKET_THD_SEL :: MAX_THD_SEL [17:00] */
-#define BCHP_SWITCH_CORE_IMP_QUEUE6_MAX_PACKET_THD_SEL_MAX_THD_SEL_MASK 0x0003ffff
-#define BCHP_SWITCH_CORE_IMP_QUEUE6_MAX_PACKET_THD_SEL_MAX_THD_SEL_SHIFT 0
-#define BCHP_SWITCH_CORE_IMP_QUEUE6_MAX_PACKET_THD_SEL_MAX_THD_SEL_DEFAULT 0x00000000
-
-/***************************************************************************
- *QUEUE6_AVB_SHAPING_MODE - Queue 6 AVB Shaping Mode Control Register
- ***************************************************************************/
-/* SWITCH_CORE :: QUEUE6_AVB_SHAPING_MODE :: reserved_for_padding0 [31:16] */
-#define BCHP_SWITCH_CORE_QUEUE6_AVB_SHAPING_MODE_reserved_for_padding0_MASK 0xffff0000
-#define BCHP_SWITCH_CORE_QUEUE6_AVB_SHAPING_MODE_reserved_for_padding0_SHIFT 16
-
-/* SWITCH_CORE :: QUEUE6_AVB_SHAPING_MODE :: SWITCH_RESV [15:09] */
-#define BCHP_SWITCH_CORE_QUEUE6_AVB_SHAPING_MODE_SWITCH_RESV_MASK 0x0000fe00
-#define BCHP_SWITCH_CORE_QUEUE6_AVB_SHAPING_MODE_SWITCH_RESV_SHIFT 9
-#define BCHP_SWITCH_CORE_QUEUE6_AVB_SHAPING_MODE_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: QUEUE6_AVB_SHAPING_MODE :: QUEUE6_AVB_SHAPING_MODE [08:00] */
-#define BCHP_SWITCH_CORE_QUEUE6_AVB_SHAPING_MODE_QUEUE6_AVB_SHAPING_MODE_MASK 0x000001ff
-#define BCHP_SWITCH_CORE_QUEUE6_AVB_SHAPING_MODE_QUEUE6_AVB_SHAPING_MODE_SHIFT 0
-#define BCHP_SWITCH_CORE_QUEUE6_AVB_SHAPING_MODE_QUEUE6_AVB_SHAPING_MODE_DEFAULT 0x00000000
-
-/***************************************************************************
- *QUEUE6_SHAPER_ENABLE - Queue 6 Shaper Enable Register
- ***************************************************************************/
-/* SWITCH_CORE :: QUEUE6_SHAPER_ENABLE :: reserved_for_padding0 [31:16] */
-#define BCHP_SWITCH_CORE_QUEUE6_SHAPER_ENABLE_reserved_for_padding0_MASK 0xffff0000
-#define BCHP_SWITCH_CORE_QUEUE6_SHAPER_ENABLE_reserved_for_padding0_SHIFT 16
-
-/* SWITCH_CORE :: QUEUE6_SHAPER_ENABLE :: SWITCH_RESV [15:09] */
-#define BCHP_SWITCH_CORE_QUEUE6_SHAPER_ENABLE_SWITCH_RESV_MASK 0x0000fe00
-#define BCHP_SWITCH_CORE_QUEUE6_SHAPER_ENABLE_SWITCH_RESV_SHIFT 9
-#define BCHP_SWITCH_CORE_QUEUE6_SHAPER_ENABLE_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: QUEUE6_SHAPER_ENABLE :: QUEUE6_SHAPER_ENABLE [08:00] */
-#define BCHP_SWITCH_CORE_QUEUE6_SHAPER_ENABLE_QUEUE6_SHAPER_ENABLE_MASK 0x000001ff
-#define BCHP_SWITCH_CORE_QUEUE6_SHAPER_ENABLE_QUEUE6_SHAPER_ENABLE_SHIFT 0
-#define BCHP_SWITCH_CORE_QUEUE6_SHAPER_ENABLE_QUEUE6_SHAPER_ENABLE_DEFAULT 0x00000000
-
-/***************************************************************************
- *QUEUE6_SHAPER_BUCKET_COUNT_SELECT - Queue 6 Bucket Count Select Register
- ***************************************************************************/
-/* SWITCH_CORE :: QUEUE6_SHAPER_BUCKET_COUNT_SELECT :: reserved_for_padding0 [31:16] */
-#define BCHP_SWITCH_CORE_QUEUE6_SHAPER_BUCKET_COUNT_SELECT_reserved_for_padding0_MASK 0xffff0000
-#define BCHP_SWITCH_CORE_QUEUE6_SHAPER_BUCKET_COUNT_SELECT_reserved_for_padding0_SHIFT 16
-
-/* SWITCH_CORE :: QUEUE6_SHAPER_BUCKET_COUNT_SELECT :: SWITCH_RESV [15:09] */
-#define BCHP_SWITCH_CORE_QUEUE6_SHAPER_BUCKET_COUNT_SELECT_SWITCH_RESV_MASK 0x0000fe00
-#define BCHP_SWITCH_CORE_QUEUE6_SHAPER_BUCKET_COUNT_SELECT_SWITCH_RESV_SHIFT 9
-#define BCHP_SWITCH_CORE_QUEUE6_SHAPER_BUCKET_COUNT_SELECT_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: QUEUE6_SHAPER_BUCKET_COUNT_SELECT :: QUEUE6_SHAPER_BUCKET_COUNT_SELECT [08:00] */
-#define BCHP_SWITCH_CORE_QUEUE6_SHAPER_BUCKET_COUNT_SELECT_QUEUE6_SHAPER_BUCKET_COUNT_SELECT_MASK 0x000001ff
-#define BCHP_SWITCH_CORE_QUEUE6_SHAPER_BUCKET_COUNT_SELECT_QUEUE6_SHAPER_BUCKET_COUNT_SELECT_SHIFT 0
-#define BCHP_SWITCH_CORE_QUEUE6_SHAPER_BUCKET_COUNT_SELECT_QUEUE6_SHAPER_BUCKET_COUNT_SELECT_DEFAULT 0x00000000
-
-/***************************************************************************
- *QUEUE6_SHAPER_BLOCKING - Queue 6 Shaper Blocking Control Register
- ***************************************************************************/
-/* SWITCH_CORE :: QUEUE6_SHAPER_BLOCKING :: reserved_for_padding0 [31:16] */
-#define BCHP_SWITCH_CORE_QUEUE6_SHAPER_BLOCKING_reserved_for_padding0_MASK 0xffff0000
-#define BCHP_SWITCH_CORE_QUEUE6_SHAPER_BLOCKING_reserved_for_padding0_SHIFT 16
-
-/* SWITCH_CORE :: QUEUE6_SHAPER_BLOCKING :: SWITCH_RESV [15:09] */
-#define BCHP_SWITCH_CORE_QUEUE6_SHAPER_BLOCKING_SWITCH_RESV_MASK 0x0000fe00
-#define BCHP_SWITCH_CORE_QUEUE6_SHAPER_BLOCKING_SWITCH_RESV_SHIFT 9
-#define BCHP_SWITCH_CORE_QUEUE6_SHAPER_BLOCKING_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: QUEUE6_SHAPER_BLOCKING :: QUEUE6_SHAPER_BLOCKING [08:00] */
-#define BCHP_SWITCH_CORE_QUEUE6_SHAPER_BLOCKING_QUEUE6_SHAPER_BLOCKING_MASK 0x000001ff
-#define BCHP_SWITCH_CORE_QUEUE6_SHAPER_BLOCKING_QUEUE6_SHAPER_BLOCKING_SHIFT 0
-#define BCHP_SWITCH_CORE_QUEUE6_SHAPER_BLOCKING_QUEUE6_SHAPER_BLOCKING_DEFAULT 0x00000000
-
-/***************************************************************************
- *PN_QUEUE7_MAX_REFRESH_Port_0 - Port N, Byte-based Queue 7 Shaping Rate Configure Register
- ***************************************************************************/
-/* SWITCH_CORE :: PN_QUEUE7_MAX_REFRESH_Port_0 :: SWITCH_RESV [31:18] */
-#define BCHP_SWITCH_CORE_PN_QUEUE7_MAX_REFRESH_Port_0_SWITCH_RESV_MASK 0xfffc0000
-#define BCHP_SWITCH_CORE_PN_QUEUE7_MAX_REFRESH_Port_0_SWITCH_RESV_SHIFT 18
-#define BCHP_SWITCH_CORE_PN_QUEUE7_MAX_REFRESH_Port_0_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: PN_QUEUE7_MAX_REFRESH_Port_0 :: MAX_REFRESH [17:00] */
-#define BCHP_SWITCH_CORE_PN_QUEUE7_MAX_REFRESH_Port_0_MAX_REFRESH_MASK 0x0003ffff
-#define BCHP_SWITCH_CORE_PN_QUEUE7_MAX_REFRESH_Port_0_MAX_REFRESH_SHIFT 0
-#define BCHP_SWITCH_CORE_PN_QUEUE7_MAX_REFRESH_Port_0_MAX_REFRESH_DEFAULT 0x00000000
-
-/***************************************************************************
- *PN_QUEUE7_MAX_REFRESH_Port_1 - Port N, Byte-based Queue 7 Shaping Rate Configure Register
- ***************************************************************************/
-/* SWITCH_CORE :: PN_QUEUE7_MAX_REFRESH_Port_1 :: SWITCH_RESV [31:18] */
-#define BCHP_SWITCH_CORE_PN_QUEUE7_MAX_REFRESH_Port_1_SWITCH_RESV_MASK 0xfffc0000
-#define BCHP_SWITCH_CORE_PN_QUEUE7_MAX_REFRESH_Port_1_SWITCH_RESV_SHIFT 18
-#define BCHP_SWITCH_CORE_PN_QUEUE7_MAX_REFRESH_Port_1_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: PN_QUEUE7_MAX_REFRESH_Port_1 :: MAX_REFRESH [17:00] */
-#define BCHP_SWITCH_CORE_PN_QUEUE7_MAX_REFRESH_Port_1_MAX_REFRESH_MASK 0x0003ffff
-#define BCHP_SWITCH_CORE_PN_QUEUE7_MAX_REFRESH_Port_1_MAX_REFRESH_SHIFT 0
-#define BCHP_SWITCH_CORE_PN_QUEUE7_MAX_REFRESH_Port_1_MAX_REFRESH_DEFAULT 0x00000000
-
-/***************************************************************************
- *PN_QUEUE7_MAX_REFRESH_Port_2 - Port N, Byte-based Queue 7 Shaping Rate Configure Register
- ***************************************************************************/
-/* SWITCH_CORE :: PN_QUEUE7_MAX_REFRESH_Port_2 :: SWITCH_RESV [31:18] */
-#define BCHP_SWITCH_CORE_PN_QUEUE7_MAX_REFRESH_Port_2_SWITCH_RESV_MASK 0xfffc0000
-#define BCHP_SWITCH_CORE_PN_QUEUE7_MAX_REFRESH_Port_2_SWITCH_RESV_SHIFT 18
-#define BCHP_SWITCH_CORE_PN_QUEUE7_MAX_REFRESH_Port_2_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: PN_QUEUE7_MAX_REFRESH_Port_2 :: MAX_REFRESH [17:00] */
-#define BCHP_SWITCH_CORE_PN_QUEUE7_MAX_REFRESH_Port_2_MAX_REFRESH_MASK 0x0003ffff
-#define BCHP_SWITCH_CORE_PN_QUEUE7_MAX_REFRESH_Port_2_MAX_REFRESH_SHIFT 0
-#define BCHP_SWITCH_CORE_PN_QUEUE7_MAX_REFRESH_Port_2_MAX_REFRESH_DEFAULT 0x00000000
-
-/***************************************************************************
- *PN_QUEUE7_MAX_REFRESH_Port_3 - Port N, Byte-based Queue 7 Shaping Rate Configure Register
- ***************************************************************************/
-/* SWITCH_CORE :: PN_QUEUE7_MAX_REFRESH_Port_3 :: SWITCH_RESV [31:18] */
-#define BCHP_SWITCH_CORE_PN_QUEUE7_MAX_REFRESH_Port_3_SWITCH_RESV_MASK 0xfffc0000
-#define BCHP_SWITCH_CORE_PN_QUEUE7_MAX_REFRESH_Port_3_SWITCH_RESV_SHIFT 18
-#define BCHP_SWITCH_CORE_PN_QUEUE7_MAX_REFRESH_Port_3_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: PN_QUEUE7_MAX_REFRESH_Port_3 :: MAX_REFRESH [17:00] */
-#define BCHP_SWITCH_CORE_PN_QUEUE7_MAX_REFRESH_Port_3_MAX_REFRESH_MASK 0x0003ffff
-#define BCHP_SWITCH_CORE_PN_QUEUE7_MAX_REFRESH_Port_3_MAX_REFRESH_SHIFT 0
-#define BCHP_SWITCH_CORE_PN_QUEUE7_MAX_REFRESH_Port_3_MAX_REFRESH_DEFAULT 0x00000000
-
-/***************************************************************************
- *PN_QUEUE7_MAX_REFRESH_Port_4 - Port N, Byte-based Queue 7 Shaping Rate Configure Register
- ***************************************************************************/
-/* SWITCH_CORE :: PN_QUEUE7_MAX_REFRESH_Port_4 :: SWITCH_RESV [31:18] */
-#define BCHP_SWITCH_CORE_PN_QUEUE7_MAX_REFRESH_Port_4_SWITCH_RESV_MASK 0xfffc0000
-#define BCHP_SWITCH_CORE_PN_QUEUE7_MAX_REFRESH_Port_4_SWITCH_RESV_SHIFT 18
-#define BCHP_SWITCH_CORE_PN_QUEUE7_MAX_REFRESH_Port_4_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: PN_QUEUE7_MAX_REFRESH_Port_4 :: MAX_REFRESH [17:00] */
-#define BCHP_SWITCH_CORE_PN_QUEUE7_MAX_REFRESH_Port_4_MAX_REFRESH_MASK 0x0003ffff
-#define BCHP_SWITCH_CORE_PN_QUEUE7_MAX_REFRESH_Port_4_MAX_REFRESH_SHIFT 0
-#define BCHP_SWITCH_CORE_PN_QUEUE7_MAX_REFRESH_Port_4_MAX_REFRESH_DEFAULT 0x00000000
-
-/***************************************************************************
- *PN_QUEUE7_MAX_REFRESH_Port_5 - Port N, Byte-based Queue 7 Shaping Rate Configure Register
- ***************************************************************************/
-/* SWITCH_CORE :: PN_QUEUE7_MAX_REFRESH_Port_5 :: SWITCH_RESV [31:18] */
-#define BCHP_SWITCH_CORE_PN_QUEUE7_MAX_REFRESH_Port_5_SWITCH_RESV_MASK 0xfffc0000
-#define BCHP_SWITCH_CORE_PN_QUEUE7_MAX_REFRESH_Port_5_SWITCH_RESV_SHIFT 18
-#define BCHP_SWITCH_CORE_PN_QUEUE7_MAX_REFRESH_Port_5_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: PN_QUEUE7_MAX_REFRESH_Port_5 :: MAX_REFRESH [17:00] */
-#define BCHP_SWITCH_CORE_PN_QUEUE7_MAX_REFRESH_Port_5_MAX_REFRESH_MASK 0x0003ffff
-#define BCHP_SWITCH_CORE_PN_QUEUE7_MAX_REFRESH_Port_5_MAX_REFRESH_SHIFT 0
-#define BCHP_SWITCH_CORE_PN_QUEUE7_MAX_REFRESH_Port_5_MAX_REFRESH_DEFAULT 0x00000000
-
-/***************************************************************************
- *P7_QUEUE7_MAX_REFRESH - Port 7, Byte-based Queue 7 Shaping Rate Configure Register
- ***************************************************************************/
-/* SWITCH_CORE :: P7_QUEUE7_MAX_REFRESH :: SWITCH_RESV [31:18] */
-#define BCHP_SWITCH_CORE_P7_QUEUE7_MAX_REFRESH_SWITCH_RESV_MASK 0xfffc0000
-#define BCHP_SWITCH_CORE_P7_QUEUE7_MAX_REFRESH_SWITCH_RESV_SHIFT 18
-#define BCHP_SWITCH_CORE_P7_QUEUE7_MAX_REFRESH_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: P7_QUEUE7_MAX_REFRESH :: MAX_REFRESH [17:00] */
-#define BCHP_SWITCH_CORE_P7_QUEUE7_MAX_REFRESH_MAX_REFRESH_MASK 0x0003ffff
-#define BCHP_SWITCH_CORE_P7_QUEUE7_MAX_REFRESH_MAX_REFRESH_SHIFT 0
-#define BCHP_SWITCH_CORE_P7_QUEUE7_MAX_REFRESH_MAX_REFRESH_DEFAULT 0x00000000
-
-/***************************************************************************
- *IMP_QUEUE7_MAX_REFRESH - Port 8, Byte-based Queue 7 Shaping Rate Configure Register
- ***************************************************************************/
-/* SWITCH_CORE :: IMP_QUEUE7_MAX_REFRESH :: SWITCH_RESV [31:18] */
-#define BCHP_SWITCH_CORE_IMP_QUEUE7_MAX_REFRESH_SWITCH_RESV_MASK 0xfffc0000
-#define BCHP_SWITCH_CORE_IMP_QUEUE7_MAX_REFRESH_SWITCH_RESV_SHIFT 18
-#define BCHP_SWITCH_CORE_IMP_QUEUE7_MAX_REFRESH_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: IMP_QUEUE7_MAX_REFRESH :: MAX_REFRESH [17:00] */
-#define BCHP_SWITCH_CORE_IMP_QUEUE7_MAX_REFRESH_MAX_REFRESH_MASK 0x0003ffff
-#define BCHP_SWITCH_CORE_IMP_QUEUE7_MAX_REFRESH_MAX_REFRESH_SHIFT 0
-#define BCHP_SWITCH_CORE_IMP_QUEUE7_MAX_REFRESH_MAX_REFRESH_DEFAULT 0x00000000
-
-/***************************************************************************
- *PN_QUEUE7_MAX_THD_SEL_Port_0 - Port N, Byte-based Queue 7 Burst Size Configure Register
- ***************************************************************************/
-/* SWITCH_CORE :: PN_QUEUE7_MAX_THD_SEL_Port_0 :: SWITCH_RESV [31:18] */
-#define BCHP_SWITCH_CORE_PN_QUEUE7_MAX_THD_SEL_Port_0_SWITCH_RESV_MASK 0xfffc0000
-#define BCHP_SWITCH_CORE_PN_QUEUE7_MAX_THD_SEL_Port_0_SWITCH_RESV_SHIFT 18
-#define BCHP_SWITCH_CORE_PN_QUEUE7_MAX_THD_SEL_Port_0_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: PN_QUEUE7_MAX_THD_SEL_Port_0 :: MAX_THD_SEL [17:00] */
-#define BCHP_SWITCH_CORE_PN_QUEUE7_MAX_THD_SEL_Port_0_MAX_THD_SEL_MASK 0x0003ffff
-#define BCHP_SWITCH_CORE_PN_QUEUE7_MAX_THD_SEL_Port_0_MAX_THD_SEL_SHIFT 0
-#define BCHP_SWITCH_CORE_PN_QUEUE7_MAX_THD_SEL_Port_0_MAX_THD_SEL_DEFAULT 0x00000000
-
-/***************************************************************************
- *PN_QUEUE7_MAX_THD_SEL_Port_1 - Port N, Byte-based Queue 7 Burst Size Configure Register
- ***************************************************************************/
-/* SWITCH_CORE :: PN_QUEUE7_MAX_THD_SEL_Port_1 :: SWITCH_RESV [31:18] */
-#define BCHP_SWITCH_CORE_PN_QUEUE7_MAX_THD_SEL_Port_1_SWITCH_RESV_MASK 0xfffc0000
-#define BCHP_SWITCH_CORE_PN_QUEUE7_MAX_THD_SEL_Port_1_SWITCH_RESV_SHIFT 18
-#define BCHP_SWITCH_CORE_PN_QUEUE7_MAX_THD_SEL_Port_1_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: PN_QUEUE7_MAX_THD_SEL_Port_1 :: MAX_THD_SEL [17:00] */
-#define BCHP_SWITCH_CORE_PN_QUEUE7_MAX_THD_SEL_Port_1_MAX_THD_SEL_MASK 0x0003ffff
-#define BCHP_SWITCH_CORE_PN_QUEUE7_MAX_THD_SEL_Port_1_MAX_THD_SEL_SHIFT 0
-#define BCHP_SWITCH_CORE_PN_QUEUE7_MAX_THD_SEL_Port_1_MAX_THD_SEL_DEFAULT 0x00000000
-
-/***************************************************************************
- *PN_QUEUE7_MAX_THD_SEL_Port_2 - Port N, Byte-based Queue 7 Burst Size Configure Register
- ***************************************************************************/
-/* SWITCH_CORE :: PN_QUEUE7_MAX_THD_SEL_Port_2 :: SWITCH_RESV [31:18] */
-#define BCHP_SWITCH_CORE_PN_QUEUE7_MAX_THD_SEL_Port_2_SWITCH_RESV_MASK 0xfffc0000
-#define BCHP_SWITCH_CORE_PN_QUEUE7_MAX_THD_SEL_Port_2_SWITCH_RESV_SHIFT 18
-#define BCHP_SWITCH_CORE_PN_QUEUE7_MAX_THD_SEL_Port_2_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: PN_QUEUE7_MAX_THD_SEL_Port_2 :: MAX_THD_SEL [17:00] */
-#define BCHP_SWITCH_CORE_PN_QUEUE7_MAX_THD_SEL_Port_2_MAX_THD_SEL_MASK 0x0003ffff
-#define BCHP_SWITCH_CORE_PN_QUEUE7_MAX_THD_SEL_Port_2_MAX_THD_SEL_SHIFT 0
-#define BCHP_SWITCH_CORE_PN_QUEUE7_MAX_THD_SEL_Port_2_MAX_THD_SEL_DEFAULT 0x00000000
-
-/***************************************************************************
- *PN_QUEUE7_MAX_THD_SEL_Port_3 - Port N, Byte-based Queue 7 Burst Size Configure Register
- ***************************************************************************/
-/* SWITCH_CORE :: PN_QUEUE7_MAX_THD_SEL_Port_3 :: SWITCH_RESV [31:18] */
-#define BCHP_SWITCH_CORE_PN_QUEUE7_MAX_THD_SEL_Port_3_SWITCH_RESV_MASK 0xfffc0000
-#define BCHP_SWITCH_CORE_PN_QUEUE7_MAX_THD_SEL_Port_3_SWITCH_RESV_SHIFT 18
-#define BCHP_SWITCH_CORE_PN_QUEUE7_MAX_THD_SEL_Port_3_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: PN_QUEUE7_MAX_THD_SEL_Port_3 :: MAX_THD_SEL [17:00] */
-#define BCHP_SWITCH_CORE_PN_QUEUE7_MAX_THD_SEL_Port_3_MAX_THD_SEL_MASK 0x0003ffff
-#define BCHP_SWITCH_CORE_PN_QUEUE7_MAX_THD_SEL_Port_3_MAX_THD_SEL_SHIFT 0
-#define BCHP_SWITCH_CORE_PN_QUEUE7_MAX_THD_SEL_Port_3_MAX_THD_SEL_DEFAULT 0x00000000
-
-/***************************************************************************
- *PN_QUEUE7_MAX_THD_SEL_Port_4 - Port N, Byte-based Queue 7 Burst Size Configure Register
- ***************************************************************************/
-/* SWITCH_CORE :: PN_QUEUE7_MAX_THD_SEL_Port_4 :: SWITCH_RESV [31:18] */
-#define BCHP_SWITCH_CORE_PN_QUEUE7_MAX_THD_SEL_Port_4_SWITCH_RESV_MASK 0xfffc0000
-#define BCHP_SWITCH_CORE_PN_QUEUE7_MAX_THD_SEL_Port_4_SWITCH_RESV_SHIFT 18
-#define BCHP_SWITCH_CORE_PN_QUEUE7_MAX_THD_SEL_Port_4_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: PN_QUEUE7_MAX_THD_SEL_Port_4 :: MAX_THD_SEL [17:00] */
-#define BCHP_SWITCH_CORE_PN_QUEUE7_MAX_THD_SEL_Port_4_MAX_THD_SEL_MASK 0x0003ffff
-#define BCHP_SWITCH_CORE_PN_QUEUE7_MAX_THD_SEL_Port_4_MAX_THD_SEL_SHIFT 0
-#define BCHP_SWITCH_CORE_PN_QUEUE7_MAX_THD_SEL_Port_4_MAX_THD_SEL_DEFAULT 0x00000000
-
-/***************************************************************************
- *PN_QUEUE7_MAX_THD_SEL_Port_5 - Port N, Byte-based Queue 7 Burst Size Configure Register
- ***************************************************************************/
-/* SWITCH_CORE :: PN_QUEUE7_MAX_THD_SEL_Port_5 :: SWITCH_RESV [31:18] */
-#define BCHP_SWITCH_CORE_PN_QUEUE7_MAX_THD_SEL_Port_5_SWITCH_RESV_MASK 0xfffc0000
-#define BCHP_SWITCH_CORE_PN_QUEUE7_MAX_THD_SEL_Port_5_SWITCH_RESV_SHIFT 18
-#define BCHP_SWITCH_CORE_PN_QUEUE7_MAX_THD_SEL_Port_5_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: PN_QUEUE7_MAX_THD_SEL_Port_5 :: MAX_THD_SEL [17:00] */
-#define BCHP_SWITCH_CORE_PN_QUEUE7_MAX_THD_SEL_Port_5_MAX_THD_SEL_MASK 0x0003ffff
-#define BCHP_SWITCH_CORE_PN_QUEUE7_MAX_THD_SEL_Port_5_MAX_THD_SEL_SHIFT 0
-#define BCHP_SWITCH_CORE_PN_QUEUE7_MAX_THD_SEL_Port_5_MAX_THD_SEL_DEFAULT 0x00000000
-
-/***************************************************************************
- *P7_QUEUE7_MAX_THD_SEL - Port 7, Byte-based Queue 7 Burst Size Configure Register
- ***************************************************************************/
-/* SWITCH_CORE :: P7_QUEUE7_MAX_THD_SEL :: SWITCH_RESV [31:18] */
-#define BCHP_SWITCH_CORE_P7_QUEUE7_MAX_THD_SEL_SWITCH_RESV_MASK 0xfffc0000
-#define BCHP_SWITCH_CORE_P7_QUEUE7_MAX_THD_SEL_SWITCH_RESV_SHIFT 18
-#define BCHP_SWITCH_CORE_P7_QUEUE7_MAX_THD_SEL_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: P7_QUEUE7_MAX_THD_SEL :: MAX_THD_SEL [17:00] */
-#define BCHP_SWITCH_CORE_P7_QUEUE7_MAX_THD_SEL_MAX_THD_SEL_MASK 0x0003ffff
-#define BCHP_SWITCH_CORE_P7_QUEUE7_MAX_THD_SEL_MAX_THD_SEL_SHIFT 0
-#define BCHP_SWITCH_CORE_P7_QUEUE7_MAX_THD_SEL_MAX_THD_SEL_DEFAULT 0x00000000
-
-/***************************************************************************
- *IMP_QUEUE7_MAX_THD_SEL - Port 8, Byte-based Queue 7 Burst Size Configure Register
- ***************************************************************************/
-/* SWITCH_CORE :: IMP_QUEUE7_MAX_THD_SEL :: SWITCH_RESV [31:18] */
-#define BCHP_SWITCH_CORE_IMP_QUEUE7_MAX_THD_SEL_SWITCH_RESV_MASK 0xfffc0000
-#define BCHP_SWITCH_CORE_IMP_QUEUE7_MAX_THD_SEL_SWITCH_RESV_SHIFT 18
-#define BCHP_SWITCH_CORE_IMP_QUEUE7_MAX_THD_SEL_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: IMP_QUEUE7_MAX_THD_SEL :: MAX_THD_SEL [17:00] */
-#define BCHP_SWITCH_CORE_IMP_QUEUE7_MAX_THD_SEL_MAX_THD_SEL_MASK 0x0003ffff
-#define BCHP_SWITCH_CORE_IMP_QUEUE7_MAX_THD_SEL_MAX_THD_SEL_SHIFT 0
-#define BCHP_SWITCH_CORE_IMP_QUEUE7_MAX_THD_SEL_MAX_THD_SEL_DEFAULT 0x00000000
-
-/***************************************************************************
- *PN_QUEUE7_SHAPER_STS_Port_0 - Port N, Queue 7 Shaper Status Register
- ***************************************************************************/
-/* SWITCH_CORE :: PN_QUEUE7_SHAPER_STS_Port_0 :: IN_PROFILE_FLAG [31:31] */
-#define BCHP_SWITCH_CORE_PN_QUEUE7_SHAPER_STS_Port_0_IN_PROFILE_FLAG_MASK 0x80000000
-#define BCHP_SWITCH_CORE_PN_QUEUE7_SHAPER_STS_Port_0_IN_PROFILE_FLAG_SHIFT 31
-#define BCHP_SWITCH_CORE_PN_QUEUE7_SHAPER_STS_Port_0_IN_PROFILE_FLAG_DEFAULT 0x00000001
-
-/* SWITCH_CORE :: PN_QUEUE7_SHAPER_STS_Port_0 :: SWITCH_RESV [30:29] */
-#define BCHP_SWITCH_CORE_PN_QUEUE7_SHAPER_STS_Port_0_SWITCH_RESV_MASK 0x60000000
-#define BCHP_SWITCH_CORE_PN_QUEUE7_SHAPER_STS_Port_0_SWITCH_RESV_SHIFT 29
-#define BCHP_SWITCH_CORE_PN_QUEUE7_SHAPER_STS_Port_0_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: PN_QUEUE7_SHAPER_STS_Port_0 :: BUCKET_CNT [28:00] */
-#define BCHP_SWITCH_CORE_PN_QUEUE7_SHAPER_STS_Port_0_BUCKET_CNT_MASK 0x1fffffff
-#define BCHP_SWITCH_CORE_PN_QUEUE7_SHAPER_STS_Port_0_BUCKET_CNT_SHIFT 0
-#define BCHP_SWITCH_CORE_PN_QUEUE7_SHAPER_STS_Port_0_BUCKET_CNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *PN_QUEUE7_SHAPER_STS_Port_1 - Port N, Queue 7 Shaper Status Register
- ***************************************************************************/
-/* SWITCH_CORE :: PN_QUEUE7_SHAPER_STS_Port_1 :: IN_PROFILE_FLAG [31:31] */
-#define BCHP_SWITCH_CORE_PN_QUEUE7_SHAPER_STS_Port_1_IN_PROFILE_FLAG_MASK 0x80000000
-#define BCHP_SWITCH_CORE_PN_QUEUE7_SHAPER_STS_Port_1_IN_PROFILE_FLAG_SHIFT 31
-#define BCHP_SWITCH_CORE_PN_QUEUE7_SHAPER_STS_Port_1_IN_PROFILE_FLAG_DEFAULT 0x00000001
-
-/* SWITCH_CORE :: PN_QUEUE7_SHAPER_STS_Port_1 :: SWITCH_RESV [30:29] */
-#define BCHP_SWITCH_CORE_PN_QUEUE7_SHAPER_STS_Port_1_SWITCH_RESV_MASK 0x60000000
-#define BCHP_SWITCH_CORE_PN_QUEUE7_SHAPER_STS_Port_1_SWITCH_RESV_SHIFT 29
-#define BCHP_SWITCH_CORE_PN_QUEUE7_SHAPER_STS_Port_1_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: PN_QUEUE7_SHAPER_STS_Port_1 :: BUCKET_CNT [28:00] */
-#define BCHP_SWITCH_CORE_PN_QUEUE7_SHAPER_STS_Port_1_BUCKET_CNT_MASK 0x1fffffff
-#define BCHP_SWITCH_CORE_PN_QUEUE7_SHAPER_STS_Port_1_BUCKET_CNT_SHIFT 0
-#define BCHP_SWITCH_CORE_PN_QUEUE7_SHAPER_STS_Port_1_BUCKET_CNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *PN_QUEUE7_SHAPER_STS_Port_2 - Port N, Queue 7 Shaper Status Register
- ***************************************************************************/
-/* SWITCH_CORE :: PN_QUEUE7_SHAPER_STS_Port_2 :: IN_PROFILE_FLAG [31:31] */
-#define BCHP_SWITCH_CORE_PN_QUEUE7_SHAPER_STS_Port_2_IN_PROFILE_FLAG_MASK 0x80000000
-#define BCHP_SWITCH_CORE_PN_QUEUE7_SHAPER_STS_Port_2_IN_PROFILE_FLAG_SHIFT 31
-#define BCHP_SWITCH_CORE_PN_QUEUE7_SHAPER_STS_Port_2_IN_PROFILE_FLAG_DEFAULT 0x00000001
-
-/* SWITCH_CORE :: PN_QUEUE7_SHAPER_STS_Port_2 :: SWITCH_RESV [30:29] */
-#define BCHP_SWITCH_CORE_PN_QUEUE7_SHAPER_STS_Port_2_SWITCH_RESV_MASK 0x60000000
-#define BCHP_SWITCH_CORE_PN_QUEUE7_SHAPER_STS_Port_2_SWITCH_RESV_SHIFT 29
-#define BCHP_SWITCH_CORE_PN_QUEUE7_SHAPER_STS_Port_2_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: PN_QUEUE7_SHAPER_STS_Port_2 :: BUCKET_CNT [28:00] */
-#define BCHP_SWITCH_CORE_PN_QUEUE7_SHAPER_STS_Port_2_BUCKET_CNT_MASK 0x1fffffff
-#define BCHP_SWITCH_CORE_PN_QUEUE7_SHAPER_STS_Port_2_BUCKET_CNT_SHIFT 0
-#define BCHP_SWITCH_CORE_PN_QUEUE7_SHAPER_STS_Port_2_BUCKET_CNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *PN_QUEUE7_SHAPER_STS_Port_3 - Port N, Queue 7 Shaper Status Register
- ***************************************************************************/
-/* SWITCH_CORE :: PN_QUEUE7_SHAPER_STS_Port_3 :: IN_PROFILE_FLAG [31:31] */
-#define BCHP_SWITCH_CORE_PN_QUEUE7_SHAPER_STS_Port_3_IN_PROFILE_FLAG_MASK 0x80000000
-#define BCHP_SWITCH_CORE_PN_QUEUE7_SHAPER_STS_Port_3_IN_PROFILE_FLAG_SHIFT 31
-#define BCHP_SWITCH_CORE_PN_QUEUE7_SHAPER_STS_Port_3_IN_PROFILE_FLAG_DEFAULT 0x00000001
-
-/* SWITCH_CORE :: PN_QUEUE7_SHAPER_STS_Port_3 :: SWITCH_RESV [30:29] */
-#define BCHP_SWITCH_CORE_PN_QUEUE7_SHAPER_STS_Port_3_SWITCH_RESV_MASK 0x60000000
-#define BCHP_SWITCH_CORE_PN_QUEUE7_SHAPER_STS_Port_3_SWITCH_RESV_SHIFT 29
-#define BCHP_SWITCH_CORE_PN_QUEUE7_SHAPER_STS_Port_3_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: PN_QUEUE7_SHAPER_STS_Port_3 :: BUCKET_CNT [28:00] */
-#define BCHP_SWITCH_CORE_PN_QUEUE7_SHAPER_STS_Port_3_BUCKET_CNT_MASK 0x1fffffff
-#define BCHP_SWITCH_CORE_PN_QUEUE7_SHAPER_STS_Port_3_BUCKET_CNT_SHIFT 0
-#define BCHP_SWITCH_CORE_PN_QUEUE7_SHAPER_STS_Port_3_BUCKET_CNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *PN_QUEUE7_SHAPER_STS_Port_4 - Port N, Queue 7 Shaper Status Register
- ***************************************************************************/
-/* SWITCH_CORE :: PN_QUEUE7_SHAPER_STS_Port_4 :: IN_PROFILE_FLAG [31:31] */
-#define BCHP_SWITCH_CORE_PN_QUEUE7_SHAPER_STS_Port_4_IN_PROFILE_FLAG_MASK 0x80000000
-#define BCHP_SWITCH_CORE_PN_QUEUE7_SHAPER_STS_Port_4_IN_PROFILE_FLAG_SHIFT 31
-#define BCHP_SWITCH_CORE_PN_QUEUE7_SHAPER_STS_Port_4_IN_PROFILE_FLAG_DEFAULT 0x00000001
-
-/* SWITCH_CORE :: PN_QUEUE7_SHAPER_STS_Port_4 :: SWITCH_RESV [30:29] */
-#define BCHP_SWITCH_CORE_PN_QUEUE7_SHAPER_STS_Port_4_SWITCH_RESV_MASK 0x60000000
-#define BCHP_SWITCH_CORE_PN_QUEUE7_SHAPER_STS_Port_4_SWITCH_RESV_SHIFT 29
-#define BCHP_SWITCH_CORE_PN_QUEUE7_SHAPER_STS_Port_4_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: PN_QUEUE7_SHAPER_STS_Port_4 :: BUCKET_CNT [28:00] */
-#define BCHP_SWITCH_CORE_PN_QUEUE7_SHAPER_STS_Port_4_BUCKET_CNT_MASK 0x1fffffff
-#define BCHP_SWITCH_CORE_PN_QUEUE7_SHAPER_STS_Port_4_BUCKET_CNT_SHIFT 0
-#define BCHP_SWITCH_CORE_PN_QUEUE7_SHAPER_STS_Port_4_BUCKET_CNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *PN_QUEUE7_SHAPER_STS_Port_5 - Port N, Queue 7 Shaper Status Register
- ***************************************************************************/
-/* SWITCH_CORE :: PN_QUEUE7_SHAPER_STS_Port_5 :: IN_PROFILE_FLAG [31:31] */
-#define BCHP_SWITCH_CORE_PN_QUEUE7_SHAPER_STS_Port_5_IN_PROFILE_FLAG_MASK 0x80000000
-#define BCHP_SWITCH_CORE_PN_QUEUE7_SHAPER_STS_Port_5_IN_PROFILE_FLAG_SHIFT 31
-#define BCHP_SWITCH_CORE_PN_QUEUE7_SHAPER_STS_Port_5_IN_PROFILE_FLAG_DEFAULT 0x00000001
-
-/* SWITCH_CORE :: PN_QUEUE7_SHAPER_STS_Port_5 :: SWITCH_RESV [30:29] */
-#define BCHP_SWITCH_CORE_PN_QUEUE7_SHAPER_STS_Port_5_SWITCH_RESV_MASK 0x60000000
-#define BCHP_SWITCH_CORE_PN_QUEUE7_SHAPER_STS_Port_5_SWITCH_RESV_SHIFT 29
-#define BCHP_SWITCH_CORE_PN_QUEUE7_SHAPER_STS_Port_5_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: PN_QUEUE7_SHAPER_STS_Port_5 :: BUCKET_CNT [28:00] */
-#define BCHP_SWITCH_CORE_PN_QUEUE7_SHAPER_STS_Port_5_BUCKET_CNT_MASK 0x1fffffff
-#define BCHP_SWITCH_CORE_PN_QUEUE7_SHAPER_STS_Port_5_BUCKET_CNT_SHIFT 0
-#define BCHP_SWITCH_CORE_PN_QUEUE7_SHAPER_STS_Port_5_BUCKET_CNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *P7_QUEUE7_SHAPER_STS - Port 7, Queue 7 Shaper Status Register
- ***************************************************************************/
-/* SWITCH_CORE :: P7_QUEUE7_SHAPER_STS :: IN_PROFILE_FLAG [31:31] */
-#define BCHP_SWITCH_CORE_P7_QUEUE7_SHAPER_STS_IN_PROFILE_FLAG_MASK 0x80000000
-#define BCHP_SWITCH_CORE_P7_QUEUE7_SHAPER_STS_IN_PROFILE_FLAG_SHIFT 31
-#define BCHP_SWITCH_CORE_P7_QUEUE7_SHAPER_STS_IN_PROFILE_FLAG_DEFAULT 0x00000001
-
-/* SWITCH_CORE :: P7_QUEUE7_SHAPER_STS :: SWITCH_RESV [30:29] */
-#define BCHP_SWITCH_CORE_P7_QUEUE7_SHAPER_STS_SWITCH_RESV_MASK 0x60000000
-#define BCHP_SWITCH_CORE_P7_QUEUE7_SHAPER_STS_SWITCH_RESV_SHIFT 29
-#define BCHP_SWITCH_CORE_P7_QUEUE7_SHAPER_STS_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: P7_QUEUE7_SHAPER_STS :: BUCKET_CNT [28:00] */
-#define BCHP_SWITCH_CORE_P7_QUEUE7_SHAPER_STS_BUCKET_CNT_MASK 0x1fffffff
-#define BCHP_SWITCH_CORE_P7_QUEUE7_SHAPER_STS_BUCKET_CNT_SHIFT 0
-#define BCHP_SWITCH_CORE_P7_QUEUE7_SHAPER_STS_BUCKET_CNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *IMP_QUEUE7_SHAPER_STS - Port 8, Queue 7 Shaper Status Register
- ***************************************************************************/
-/* SWITCH_CORE :: IMP_QUEUE7_SHAPER_STS :: IN_PROFILE_FLAG [31:31] */
-#define BCHP_SWITCH_CORE_IMP_QUEUE7_SHAPER_STS_IN_PROFILE_FLAG_MASK 0x80000000
-#define BCHP_SWITCH_CORE_IMP_QUEUE7_SHAPER_STS_IN_PROFILE_FLAG_SHIFT 31
-#define BCHP_SWITCH_CORE_IMP_QUEUE7_SHAPER_STS_IN_PROFILE_FLAG_DEFAULT 0x00000001
-
-/* SWITCH_CORE :: IMP_QUEUE7_SHAPER_STS :: SWITCH_RESV [30:29] */
-#define BCHP_SWITCH_CORE_IMP_QUEUE7_SHAPER_STS_SWITCH_RESV_MASK 0x60000000
-#define BCHP_SWITCH_CORE_IMP_QUEUE7_SHAPER_STS_SWITCH_RESV_SHIFT 29
-#define BCHP_SWITCH_CORE_IMP_QUEUE7_SHAPER_STS_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: IMP_QUEUE7_SHAPER_STS :: BUCKET_CNT [28:00] */
-#define BCHP_SWITCH_CORE_IMP_QUEUE7_SHAPER_STS_BUCKET_CNT_MASK 0x1fffffff
-#define BCHP_SWITCH_CORE_IMP_QUEUE7_SHAPER_STS_BUCKET_CNT_SHIFT 0
-#define BCHP_SWITCH_CORE_IMP_QUEUE7_SHAPER_STS_BUCKET_CNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *PN_QUEUE7_MAX_PACKET_REFRESH_Port_0 - Port N, Packet-based Queue 7 Shaping Rate Configure Register
- ***************************************************************************/
-/* SWITCH_CORE :: PN_QUEUE7_MAX_PACKET_REFRESH_Port_0 :: SWITCH_RESV [31:18] */
-#define BCHP_SWITCH_CORE_PN_QUEUE7_MAX_PACKET_REFRESH_Port_0_SWITCH_RESV_MASK 0xfffc0000
-#define BCHP_SWITCH_CORE_PN_QUEUE7_MAX_PACKET_REFRESH_Port_0_SWITCH_RESV_SHIFT 18
-#define BCHP_SWITCH_CORE_PN_QUEUE7_MAX_PACKET_REFRESH_Port_0_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: PN_QUEUE7_MAX_PACKET_REFRESH_Port_0 :: MAX_REFRESH [17:00] */
-#define BCHP_SWITCH_CORE_PN_QUEUE7_MAX_PACKET_REFRESH_Port_0_MAX_REFRESH_MASK 0x0003ffff
-#define BCHP_SWITCH_CORE_PN_QUEUE7_MAX_PACKET_REFRESH_Port_0_MAX_REFRESH_SHIFT 0
-#define BCHP_SWITCH_CORE_PN_QUEUE7_MAX_PACKET_REFRESH_Port_0_MAX_REFRESH_DEFAULT 0x00000000
-
-/***************************************************************************
- *PN_QUEUE7_MAX_PACKET_REFRESH_Port_1 - Port N, Packet-based Queue 7 Shaping Rate Configure Register
- ***************************************************************************/
-/* SWITCH_CORE :: PN_QUEUE7_MAX_PACKET_REFRESH_Port_1 :: SWITCH_RESV [31:18] */
-#define BCHP_SWITCH_CORE_PN_QUEUE7_MAX_PACKET_REFRESH_Port_1_SWITCH_RESV_MASK 0xfffc0000
-#define BCHP_SWITCH_CORE_PN_QUEUE7_MAX_PACKET_REFRESH_Port_1_SWITCH_RESV_SHIFT 18
-#define BCHP_SWITCH_CORE_PN_QUEUE7_MAX_PACKET_REFRESH_Port_1_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: PN_QUEUE7_MAX_PACKET_REFRESH_Port_1 :: MAX_REFRESH [17:00] */
-#define BCHP_SWITCH_CORE_PN_QUEUE7_MAX_PACKET_REFRESH_Port_1_MAX_REFRESH_MASK 0x0003ffff
-#define BCHP_SWITCH_CORE_PN_QUEUE7_MAX_PACKET_REFRESH_Port_1_MAX_REFRESH_SHIFT 0
-#define BCHP_SWITCH_CORE_PN_QUEUE7_MAX_PACKET_REFRESH_Port_1_MAX_REFRESH_DEFAULT 0x00000000
-
-/***************************************************************************
- *PN_QUEUE7_MAX_PACKET_REFRESH_Port_2 - Port N, Packet-based Queue 7 Shaping Rate Configure Register
- ***************************************************************************/
-/* SWITCH_CORE :: PN_QUEUE7_MAX_PACKET_REFRESH_Port_2 :: SWITCH_RESV [31:18] */
-#define BCHP_SWITCH_CORE_PN_QUEUE7_MAX_PACKET_REFRESH_Port_2_SWITCH_RESV_MASK 0xfffc0000
-#define BCHP_SWITCH_CORE_PN_QUEUE7_MAX_PACKET_REFRESH_Port_2_SWITCH_RESV_SHIFT 18
-#define BCHP_SWITCH_CORE_PN_QUEUE7_MAX_PACKET_REFRESH_Port_2_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: PN_QUEUE7_MAX_PACKET_REFRESH_Port_2 :: MAX_REFRESH [17:00] */
-#define BCHP_SWITCH_CORE_PN_QUEUE7_MAX_PACKET_REFRESH_Port_2_MAX_REFRESH_MASK 0x0003ffff
-#define BCHP_SWITCH_CORE_PN_QUEUE7_MAX_PACKET_REFRESH_Port_2_MAX_REFRESH_SHIFT 0
-#define BCHP_SWITCH_CORE_PN_QUEUE7_MAX_PACKET_REFRESH_Port_2_MAX_REFRESH_DEFAULT 0x00000000
-
-/***************************************************************************
- *PN_QUEUE7_MAX_PACKET_REFRESH_Port_3 - Port N, Packet-based Queue 7 Shaping Rate Configure Register
- ***************************************************************************/
-/* SWITCH_CORE :: PN_QUEUE7_MAX_PACKET_REFRESH_Port_3 :: SWITCH_RESV [31:18] */
-#define BCHP_SWITCH_CORE_PN_QUEUE7_MAX_PACKET_REFRESH_Port_3_SWITCH_RESV_MASK 0xfffc0000
-#define BCHP_SWITCH_CORE_PN_QUEUE7_MAX_PACKET_REFRESH_Port_3_SWITCH_RESV_SHIFT 18
-#define BCHP_SWITCH_CORE_PN_QUEUE7_MAX_PACKET_REFRESH_Port_3_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: PN_QUEUE7_MAX_PACKET_REFRESH_Port_3 :: MAX_REFRESH [17:00] */
-#define BCHP_SWITCH_CORE_PN_QUEUE7_MAX_PACKET_REFRESH_Port_3_MAX_REFRESH_MASK 0x0003ffff
-#define BCHP_SWITCH_CORE_PN_QUEUE7_MAX_PACKET_REFRESH_Port_3_MAX_REFRESH_SHIFT 0
-#define BCHP_SWITCH_CORE_PN_QUEUE7_MAX_PACKET_REFRESH_Port_3_MAX_REFRESH_DEFAULT 0x00000000
-
-/***************************************************************************
- *PN_QUEUE7_MAX_PACKET_REFRESH_Port_4 - Port N, Packet-based Queue 7 Shaping Rate Configure Register
- ***************************************************************************/
-/* SWITCH_CORE :: PN_QUEUE7_MAX_PACKET_REFRESH_Port_4 :: SWITCH_RESV [31:18] */
-#define BCHP_SWITCH_CORE_PN_QUEUE7_MAX_PACKET_REFRESH_Port_4_SWITCH_RESV_MASK 0xfffc0000
-#define BCHP_SWITCH_CORE_PN_QUEUE7_MAX_PACKET_REFRESH_Port_4_SWITCH_RESV_SHIFT 18
-#define BCHP_SWITCH_CORE_PN_QUEUE7_MAX_PACKET_REFRESH_Port_4_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: PN_QUEUE7_MAX_PACKET_REFRESH_Port_4 :: MAX_REFRESH [17:00] */
-#define BCHP_SWITCH_CORE_PN_QUEUE7_MAX_PACKET_REFRESH_Port_4_MAX_REFRESH_MASK 0x0003ffff
-#define BCHP_SWITCH_CORE_PN_QUEUE7_MAX_PACKET_REFRESH_Port_4_MAX_REFRESH_SHIFT 0
-#define BCHP_SWITCH_CORE_PN_QUEUE7_MAX_PACKET_REFRESH_Port_4_MAX_REFRESH_DEFAULT 0x00000000
-
-/***************************************************************************
- *PN_QUEUE7_MAX_PACKET_REFRESH_Port_5 - Port N, Packet-based Queue 7 Shaping Rate Configure Register
- ***************************************************************************/
-/* SWITCH_CORE :: PN_QUEUE7_MAX_PACKET_REFRESH_Port_5 :: SWITCH_RESV [31:18] */
-#define BCHP_SWITCH_CORE_PN_QUEUE7_MAX_PACKET_REFRESH_Port_5_SWITCH_RESV_MASK 0xfffc0000
-#define BCHP_SWITCH_CORE_PN_QUEUE7_MAX_PACKET_REFRESH_Port_5_SWITCH_RESV_SHIFT 18
-#define BCHP_SWITCH_CORE_PN_QUEUE7_MAX_PACKET_REFRESH_Port_5_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: PN_QUEUE7_MAX_PACKET_REFRESH_Port_5 :: MAX_REFRESH [17:00] */
-#define BCHP_SWITCH_CORE_PN_QUEUE7_MAX_PACKET_REFRESH_Port_5_MAX_REFRESH_MASK 0x0003ffff
-#define BCHP_SWITCH_CORE_PN_QUEUE7_MAX_PACKET_REFRESH_Port_5_MAX_REFRESH_SHIFT 0
-#define BCHP_SWITCH_CORE_PN_QUEUE7_MAX_PACKET_REFRESH_Port_5_MAX_REFRESH_DEFAULT 0x00000000
-
-/***************************************************************************
- *P7_QUEUE7_MAX_PACKET_REFRESH - Port 7, Packet-based Queue 7 Shaping Rate Configure Register
- ***************************************************************************/
-/* SWITCH_CORE :: P7_QUEUE7_MAX_PACKET_REFRESH :: SWITCH_RESV [31:18] */
-#define BCHP_SWITCH_CORE_P7_QUEUE7_MAX_PACKET_REFRESH_SWITCH_RESV_MASK 0xfffc0000
-#define BCHP_SWITCH_CORE_P7_QUEUE7_MAX_PACKET_REFRESH_SWITCH_RESV_SHIFT 18
-#define BCHP_SWITCH_CORE_P7_QUEUE7_MAX_PACKET_REFRESH_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: P7_QUEUE7_MAX_PACKET_REFRESH :: MAX_REFRESH [17:00] */
-#define BCHP_SWITCH_CORE_P7_QUEUE7_MAX_PACKET_REFRESH_MAX_REFRESH_MASK 0x0003ffff
-#define BCHP_SWITCH_CORE_P7_QUEUE7_MAX_PACKET_REFRESH_MAX_REFRESH_SHIFT 0
-#define BCHP_SWITCH_CORE_P7_QUEUE7_MAX_PACKET_REFRESH_MAX_REFRESH_DEFAULT 0x00000000
-
-/***************************************************************************
- *IMP_QUEUE7_MAX_PACKET_REFRESH - Port 8, Packet-based Queue 7 Shaping Rate Configure Register
- ***************************************************************************/
-/* SWITCH_CORE :: IMP_QUEUE7_MAX_PACKET_REFRESH :: SWITCH_RESV [31:18] */
-#define BCHP_SWITCH_CORE_IMP_QUEUE7_MAX_PACKET_REFRESH_SWITCH_RESV_MASK 0xfffc0000
-#define BCHP_SWITCH_CORE_IMP_QUEUE7_MAX_PACKET_REFRESH_SWITCH_RESV_SHIFT 18
-#define BCHP_SWITCH_CORE_IMP_QUEUE7_MAX_PACKET_REFRESH_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: IMP_QUEUE7_MAX_PACKET_REFRESH :: MAX_REFRESH [17:00] */
-#define BCHP_SWITCH_CORE_IMP_QUEUE7_MAX_PACKET_REFRESH_MAX_REFRESH_MASK 0x0003ffff
-#define BCHP_SWITCH_CORE_IMP_QUEUE7_MAX_PACKET_REFRESH_MAX_REFRESH_SHIFT 0
-#define BCHP_SWITCH_CORE_IMP_QUEUE7_MAX_PACKET_REFRESH_MAX_REFRESH_DEFAULT 0x00000000
-
-/***************************************************************************
- *EGRESS_SHAPER_Q7_CONFIG_REG_SPARE0 - Spare 0 Register (Not2Release)
- ***************************************************************************/
-/* SWITCH_CORE :: EGRESS_SHAPER_Q7_CONFIG_REG_SPARE0 :: EGRESS_SHAPER_Q7_CONFIG_REG_SPARE0 [31:00] */
-#define BCHP_SWITCH_CORE_EGRESS_SHAPER_Q7_CONFIG_REG_SPARE0_EGRESS_SHAPER_Q7_CONFIG_REG_SPARE0_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_EGRESS_SHAPER_Q7_CONFIG_REG_SPARE0_EGRESS_SHAPER_Q7_CONFIG_REG_SPARE0_SHIFT 0
-#define BCHP_SWITCH_CORE_EGRESS_SHAPER_Q7_CONFIG_REG_SPARE0_EGRESS_SHAPER_Q7_CONFIG_REG_SPARE0_DEFAULT 0x00000000
-
-/***************************************************************************
- *EGRESS_SHAPER_Q7_CONFIG_REG_SPARE1 - Spare 1 Register (Not2Release)
- ***************************************************************************/
-/* SWITCH_CORE :: EGRESS_SHAPER_Q7_CONFIG_REG_SPARE1 :: EGRESS_SHAPER_Q7_CONFIG_REG_SPARE1 [31:00] */
-#define BCHP_SWITCH_CORE_EGRESS_SHAPER_Q7_CONFIG_REG_SPARE1_EGRESS_SHAPER_Q7_CONFIG_REG_SPARE1_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_EGRESS_SHAPER_Q7_CONFIG_REG_SPARE1_EGRESS_SHAPER_Q7_CONFIG_REG_SPARE1_SHIFT 0
-#define BCHP_SWITCH_CORE_EGRESS_SHAPER_Q7_CONFIG_REG_SPARE1_EGRESS_SHAPER_Q7_CONFIG_REG_SPARE1_DEFAULT 0x00000000
-
-/***************************************************************************
- *PN_QUEUE7_MAX_PACKET_THD_SEL_Port_0 - Port N, Packet-based Queue 7 Burst Size Configure Register
- ***************************************************************************/
-/* SWITCH_CORE :: PN_QUEUE7_MAX_PACKET_THD_SEL_Port_0 :: SWITCH_RESV [31:18] */
-#define BCHP_SWITCH_CORE_PN_QUEUE7_MAX_PACKET_THD_SEL_Port_0_SWITCH_RESV_MASK 0xfffc0000
-#define BCHP_SWITCH_CORE_PN_QUEUE7_MAX_PACKET_THD_SEL_Port_0_SWITCH_RESV_SHIFT 18
-#define BCHP_SWITCH_CORE_PN_QUEUE7_MAX_PACKET_THD_SEL_Port_0_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: PN_QUEUE7_MAX_PACKET_THD_SEL_Port_0 :: MAX_THD_SEL [17:00] */
-#define BCHP_SWITCH_CORE_PN_QUEUE7_MAX_PACKET_THD_SEL_Port_0_MAX_THD_SEL_MASK 0x0003ffff
-#define BCHP_SWITCH_CORE_PN_QUEUE7_MAX_PACKET_THD_SEL_Port_0_MAX_THD_SEL_SHIFT 0
-#define BCHP_SWITCH_CORE_PN_QUEUE7_MAX_PACKET_THD_SEL_Port_0_MAX_THD_SEL_DEFAULT 0x00000000
-
-/***************************************************************************
- *PN_QUEUE7_MAX_PACKET_THD_SEL_Port_1 - Port N, Packet-based Queue 7 Burst Size Configure Register
- ***************************************************************************/
-/* SWITCH_CORE :: PN_QUEUE7_MAX_PACKET_THD_SEL_Port_1 :: SWITCH_RESV [31:18] */
-#define BCHP_SWITCH_CORE_PN_QUEUE7_MAX_PACKET_THD_SEL_Port_1_SWITCH_RESV_MASK 0xfffc0000
-#define BCHP_SWITCH_CORE_PN_QUEUE7_MAX_PACKET_THD_SEL_Port_1_SWITCH_RESV_SHIFT 18
-#define BCHP_SWITCH_CORE_PN_QUEUE7_MAX_PACKET_THD_SEL_Port_1_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: PN_QUEUE7_MAX_PACKET_THD_SEL_Port_1 :: MAX_THD_SEL [17:00] */
-#define BCHP_SWITCH_CORE_PN_QUEUE7_MAX_PACKET_THD_SEL_Port_1_MAX_THD_SEL_MASK 0x0003ffff
-#define BCHP_SWITCH_CORE_PN_QUEUE7_MAX_PACKET_THD_SEL_Port_1_MAX_THD_SEL_SHIFT 0
-#define BCHP_SWITCH_CORE_PN_QUEUE7_MAX_PACKET_THD_SEL_Port_1_MAX_THD_SEL_DEFAULT 0x00000000
-
-/***************************************************************************
- *PN_QUEUE7_MAX_PACKET_THD_SEL_Port_2 - Port N, Packet-based Queue 7 Burst Size Configure Register
- ***************************************************************************/
-/* SWITCH_CORE :: PN_QUEUE7_MAX_PACKET_THD_SEL_Port_2 :: SWITCH_RESV [31:18] */
-#define BCHP_SWITCH_CORE_PN_QUEUE7_MAX_PACKET_THD_SEL_Port_2_SWITCH_RESV_MASK 0xfffc0000
-#define BCHP_SWITCH_CORE_PN_QUEUE7_MAX_PACKET_THD_SEL_Port_2_SWITCH_RESV_SHIFT 18
-#define BCHP_SWITCH_CORE_PN_QUEUE7_MAX_PACKET_THD_SEL_Port_2_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: PN_QUEUE7_MAX_PACKET_THD_SEL_Port_2 :: MAX_THD_SEL [17:00] */
-#define BCHP_SWITCH_CORE_PN_QUEUE7_MAX_PACKET_THD_SEL_Port_2_MAX_THD_SEL_MASK 0x0003ffff
-#define BCHP_SWITCH_CORE_PN_QUEUE7_MAX_PACKET_THD_SEL_Port_2_MAX_THD_SEL_SHIFT 0
-#define BCHP_SWITCH_CORE_PN_QUEUE7_MAX_PACKET_THD_SEL_Port_2_MAX_THD_SEL_DEFAULT 0x00000000
-
-/***************************************************************************
- *PN_QUEUE7_MAX_PACKET_THD_SEL_Port_3 - Port N, Packet-based Queue 7 Burst Size Configure Register
- ***************************************************************************/
-/* SWITCH_CORE :: PN_QUEUE7_MAX_PACKET_THD_SEL_Port_3 :: SWITCH_RESV [31:18] */
-#define BCHP_SWITCH_CORE_PN_QUEUE7_MAX_PACKET_THD_SEL_Port_3_SWITCH_RESV_MASK 0xfffc0000
-#define BCHP_SWITCH_CORE_PN_QUEUE7_MAX_PACKET_THD_SEL_Port_3_SWITCH_RESV_SHIFT 18
-#define BCHP_SWITCH_CORE_PN_QUEUE7_MAX_PACKET_THD_SEL_Port_3_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: PN_QUEUE7_MAX_PACKET_THD_SEL_Port_3 :: MAX_THD_SEL [17:00] */
-#define BCHP_SWITCH_CORE_PN_QUEUE7_MAX_PACKET_THD_SEL_Port_3_MAX_THD_SEL_MASK 0x0003ffff
-#define BCHP_SWITCH_CORE_PN_QUEUE7_MAX_PACKET_THD_SEL_Port_3_MAX_THD_SEL_SHIFT 0
-#define BCHP_SWITCH_CORE_PN_QUEUE7_MAX_PACKET_THD_SEL_Port_3_MAX_THD_SEL_DEFAULT 0x00000000
-
-/***************************************************************************
- *PN_QUEUE7_MAX_PACKET_THD_SEL_Port_4 - Port N, Packet-based Queue 7 Burst Size Configure Register
- ***************************************************************************/
-/* SWITCH_CORE :: PN_QUEUE7_MAX_PACKET_THD_SEL_Port_4 :: SWITCH_RESV [31:18] */
-#define BCHP_SWITCH_CORE_PN_QUEUE7_MAX_PACKET_THD_SEL_Port_4_SWITCH_RESV_MASK 0xfffc0000
-#define BCHP_SWITCH_CORE_PN_QUEUE7_MAX_PACKET_THD_SEL_Port_4_SWITCH_RESV_SHIFT 18
-#define BCHP_SWITCH_CORE_PN_QUEUE7_MAX_PACKET_THD_SEL_Port_4_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: PN_QUEUE7_MAX_PACKET_THD_SEL_Port_4 :: MAX_THD_SEL [17:00] */
-#define BCHP_SWITCH_CORE_PN_QUEUE7_MAX_PACKET_THD_SEL_Port_4_MAX_THD_SEL_MASK 0x0003ffff
-#define BCHP_SWITCH_CORE_PN_QUEUE7_MAX_PACKET_THD_SEL_Port_4_MAX_THD_SEL_SHIFT 0
-#define BCHP_SWITCH_CORE_PN_QUEUE7_MAX_PACKET_THD_SEL_Port_4_MAX_THD_SEL_DEFAULT 0x00000000
-
-/***************************************************************************
- *PN_QUEUE7_MAX_PACKET_THD_SEL_Port_5 - Port N, Packet-based Queue 7 Burst Size Configure Register
- ***************************************************************************/
-/* SWITCH_CORE :: PN_QUEUE7_MAX_PACKET_THD_SEL_Port_5 :: SWITCH_RESV [31:18] */
-#define BCHP_SWITCH_CORE_PN_QUEUE7_MAX_PACKET_THD_SEL_Port_5_SWITCH_RESV_MASK 0xfffc0000
-#define BCHP_SWITCH_CORE_PN_QUEUE7_MAX_PACKET_THD_SEL_Port_5_SWITCH_RESV_SHIFT 18
-#define BCHP_SWITCH_CORE_PN_QUEUE7_MAX_PACKET_THD_SEL_Port_5_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: PN_QUEUE7_MAX_PACKET_THD_SEL_Port_5 :: MAX_THD_SEL [17:00] */
-#define BCHP_SWITCH_CORE_PN_QUEUE7_MAX_PACKET_THD_SEL_Port_5_MAX_THD_SEL_MASK 0x0003ffff
-#define BCHP_SWITCH_CORE_PN_QUEUE7_MAX_PACKET_THD_SEL_Port_5_MAX_THD_SEL_SHIFT 0
-#define BCHP_SWITCH_CORE_PN_QUEUE7_MAX_PACKET_THD_SEL_Port_5_MAX_THD_SEL_DEFAULT 0x00000000
-
-/***************************************************************************
- *P7_QUEUE7_MAX_PACKET_THD_SEL - Port 7, Packet-based Queue 7 Burst Size Configure Register
- ***************************************************************************/
-/* SWITCH_CORE :: P7_QUEUE7_MAX_PACKET_THD_SEL :: SWITCH_RESV [31:18] */
-#define BCHP_SWITCH_CORE_P7_QUEUE7_MAX_PACKET_THD_SEL_SWITCH_RESV_MASK 0xfffc0000
-#define BCHP_SWITCH_CORE_P7_QUEUE7_MAX_PACKET_THD_SEL_SWITCH_RESV_SHIFT 18
-#define BCHP_SWITCH_CORE_P7_QUEUE7_MAX_PACKET_THD_SEL_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: P7_QUEUE7_MAX_PACKET_THD_SEL :: MAX_THD_SEL [17:00] */
-#define BCHP_SWITCH_CORE_P7_QUEUE7_MAX_PACKET_THD_SEL_MAX_THD_SEL_MASK 0x0003ffff
-#define BCHP_SWITCH_CORE_P7_QUEUE7_MAX_PACKET_THD_SEL_MAX_THD_SEL_SHIFT 0
-#define BCHP_SWITCH_CORE_P7_QUEUE7_MAX_PACKET_THD_SEL_MAX_THD_SEL_DEFAULT 0x00000000
-
-/***************************************************************************
- *IMP_QUEUE7_MAX_PACKET_THD_SEL - Port 8, Packet-based Queue 7 Burst Size Configure Register
- ***************************************************************************/
-/* SWITCH_CORE :: IMP_QUEUE7_MAX_PACKET_THD_SEL :: SWITCH_RESV [31:18] */
-#define BCHP_SWITCH_CORE_IMP_QUEUE7_MAX_PACKET_THD_SEL_SWITCH_RESV_MASK 0xfffc0000
-#define BCHP_SWITCH_CORE_IMP_QUEUE7_MAX_PACKET_THD_SEL_SWITCH_RESV_SHIFT 18
-#define BCHP_SWITCH_CORE_IMP_QUEUE7_MAX_PACKET_THD_SEL_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: IMP_QUEUE7_MAX_PACKET_THD_SEL :: MAX_THD_SEL [17:00] */
-#define BCHP_SWITCH_CORE_IMP_QUEUE7_MAX_PACKET_THD_SEL_MAX_THD_SEL_MASK 0x0003ffff
-#define BCHP_SWITCH_CORE_IMP_QUEUE7_MAX_PACKET_THD_SEL_MAX_THD_SEL_SHIFT 0
-#define BCHP_SWITCH_CORE_IMP_QUEUE7_MAX_PACKET_THD_SEL_MAX_THD_SEL_DEFAULT 0x00000000
-
-/***************************************************************************
- *QUEUE7_AVB_SHAPING_MODE - Queue 7 AVB Shaping Mode Control Register
- ***************************************************************************/
-/* SWITCH_CORE :: QUEUE7_AVB_SHAPING_MODE :: reserved_for_padding0 [31:16] */
-#define BCHP_SWITCH_CORE_QUEUE7_AVB_SHAPING_MODE_reserved_for_padding0_MASK 0xffff0000
-#define BCHP_SWITCH_CORE_QUEUE7_AVB_SHAPING_MODE_reserved_for_padding0_SHIFT 16
-
-/* SWITCH_CORE :: QUEUE7_AVB_SHAPING_MODE :: SWITCH_RESV [15:09] */
-#define BCHP_SWITCH_CORE_QUEUE7_AVB_SHAPING_MODE_SWITCH_RESV_MASK 0x0000fe00
-#define BCHP_SWITCH_CORE_QUEUE7_AVB_SHAPING_MODE_SWITCH_RESV_SHIFT 9
-#define BCHP_SWITCH_CORE_QUEUE7_AVB_SHAPING_MODE_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: QUEUE7_AVB_SHAPING_MODE :: QUEUE7_AVB_SHAPING_MODE [08:00] */
-#define BCHP_SWITCH_CORE_QUEUE7_AVB_SHAPING_MODE_QUEUE7_AVB_SHAPING_MODE_MASK 0x000001ff
-#define BCHP_SWITCH_CORE_QUEUE7_AVB_SHAPING_MODE_QUEUE7_AVB_SHAPING_MODE_SHIFT 0
-#define BCHP_SWITCH_CORE_QUEUE7_AVB_SHAPING_MODE_QUEUE7_AVB_SHAPING_MODE_DEFAULT 0x00000000
-
-/***************************************************************************
- *QUEUE7_SHAPER_ENABLE - Queue 7 Shaper Enable Register
- ***************************************************************************/
-/* SWITCH_CORE :: QUEUE7_SHAPER_ENABLE :: reserved_for_padding0 [31:16] */
-#define BCHP_SWITCH_CORE_QUEUE7_SHAPER_ENABLE_reserved_for_padding0_MASK 0xffff0000
-#define BCHP_SWITCH_CORE_QUEUE7_SHAPER_ENABLE_reserved_for_padding0_SHIFT 16
-
-/* SWITCH_CORE :: QUEUE7_SHAPER_ENABLE :: SWITCH_RESV [15:09] */
-#define BCHP_SWITCH_CORE_QUEUE7_SHAPER_ENABLE_SWITCH_RESV_MASK 0x0000fe00
-#define BCHP_SWITCH_CORE_QUEUE7_SHAPER_ENABLE_SWITCH_RESV_SHIFT 9
-#define BCHP_SWITCH_CORE_QUEUE7_SHAPER_ENABLE_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: QUEUE7_SHAPER_ENABLE :: QUEUE7_SHAPER_ENABLE [08:00] */
-#define BCHP_SWITCH_CORE_QUEUE7_SHAPER_ENABLE_QUEUE7_SHAPER_ENABLE_MASK 0x000001ff
-#define BCHP_SWITCH_CORE_QUEUE7_SHAPER_ENABLE_QUEUE7_SHAPER_ENABLE_SHIFT 0
-#define BCHP_SWITCH_CORE_QUEUE7_SHAPER_ENABLE_QUEUE7_SHAPER_ENABLE_DEFAULT 0x00000000
-
-/***************************************************************************
- *QUEUE7_SHAPER_BUCKET_COUNT_SELECT - Queue 7 Bucket Count Select Register
- ***************************************************************************/
-/* SWITCH_CORE :: QUEUE7_SHAPER_BUCKET_COUNT_SELECT :: reserved_for_padding0 [31:16] */
-#define BCHP_SWITCH_CORE_QUEUE7_SHAPER_BUCKET_COUNT_SELECT_reserved_for_padding0_MASK 0xffff0000
-#define BCHP_SWITCH_CORE_QUEUE7_SHAPER_BUCKET_COUNT_SELECT_reserved_for_padding0_SHIFT 16
-
-/* SWITCH_CORE :: QUEUE7_SHAPER_BUCKET_COUNT_SELECT :: SWITCH_RESV [15:09] */
-#define BCHP_SWITCH_CORE_QUEUE7_SHAPER_BUCKET_COUNT_SELECT_SWITCH_RESV_MASK 0x0000fe00
-#define BCHP_SWITCH_CORE_QUEUE7_SHAPER_BUCKET_COUNT_SELECT_SWITCH_RESV_SHIFT 9
-#define BCHP_SWITCH_CORE_QUEUE7_SHAPER_BUCKET_COUNT_SELECT_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: QUEUE7_SHAPER_BUCKET_COUNT_SELECT :: QUEUE7_SHAPER_BUCKET_COUNT_SELECT [08:00] */
-#define BCHP_SWITCH_CORE_QUEUE7_SHAPER_BUCKET_COUNT_SELECT_QUEUE7_SHAPER_BUCKET_COUNT_SELECT_MASK 0x000001ff
-#define BCHP_SWITCH_CORE_QUEUE7_SHAPER_BUCKET_COUNT_SELECT_QUEUE7_SHAPER_BUCKET_COUNT_SELECT_SHIFT 0
-#define BCHP_SWITCH_CORE_QUEUE7_SHAPER_BUCKET_COUNT_SELECT_QUEUE7_SHAPER_BUCKET_COUNT_SELECT_DEFAULT 0x00000000
-
-/***************************************************************************
- *QUEUE7_SHAPER_BLOCKING - Queue 7 Shaper Blocking Control Register
- ***************************************************************************/
-/* SWITCH_CORE :: QUEUE7_SHAPER_BLOCKING :: reserved_for_padding0 [31:16] */
-#define BCHP_SWITCH_CORE_QUEUE7_SHAPER_BLOCKING_reserved_for_padding0_MASK 0xffff0000
-#define BCHP_SWITCH_CORE_QUEUE7_SHAPER_BLOCKING_reserved_for_padding0_SHIFT 16
-
-/* SWITCH_CORE :: QUEUE7_SHAPER_BLOCKING :: SWITCH_RESV [15:09] */
-#define BCHP_SWITCH_CORE_QUEUE7_SHAPER_BLOCKING_SWITCH_RESV_MASK 0x0000fe00
-#define BCHP_SWITCH_CORE_QUEUE7_SHAPER_BLOCKING_SWITCH_RESV_SHIFT 9
-#define BCHP_SWITCH_CORE_QUEUE7_SHAPER_BLOCKING_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: QUEUE7_SHAPER_BLOCKING :: QUEUE7_SHAPER_BLOCKING [08:00] */
-#define BCHP_SWITCH_CORE_QUEUE7_SHAPER_BLOCKING_QUEUE7_SHAPER_BLOCKING_MASK 0x000001ff
-#define BCHP_SWITCH_CORE_QUEUE7_SHAPER_BLOCKING_QUEUE7_SHAPER_BLOCKING_SHIFT 0
-#define BCHP_SWITCH_CORE_QUEUE7_SHAPER_BLOCKING_QUEUE7_SHAPER_BLOCKING_DEFAULT 0x00000000
-
-/***************************************************************************
- *MIB_SNAPSHOT_CTL - MIB Snapshot Control Register
- ***************************************************************************/
-/* SWITCH_CORE :: MIB_SNAPSHOT_CTL :: reserved_for_padding0 [31:08] */
-#define BCHP_SWITCH_CORE_MIB_SNAPSHOT_CTL_reserved_for_padding0_MASK 0xffffff00
-#define BCHP_SWITCH_CORE_MIB_SNAPSHOT_CTL_reserved_for_padding0_SHIFT 8
-
-/* SWITCH_CORE :: MIB_SNAPSHOT_CTL :: SNAPSHOT_STDONE [07:07] */
-#define BCHP_SWITCH_CORE_MIB_SNAPSHOT_CTL_SNAPSHOT_STDONE_MASK 0x00000080
-#define BCHP_SWITCH_CORE_MIB_SNAPSHOT_CTL_SNAPSHOT_STDONE_SHIFT 7
-#define BCHP_SWITCH_CORE_MIB_SNAPSHOT_CTL_SNAPSHOT_STDONE_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: MIB_SNAPSHOT_CTL :: SNAPSHOT_MIRROR [06:06] */
-#define BCHP_SWITCH_CORE_MIB_SNAPSHOT_CTL_SNAPSHOT_MIRROR_MASK 0x00000040
-#define BCHP_SWITCH_CORE_MIB_SNAPSHOT_CTL_SNAPSHOT_MIRROR_SHIFT 6
-#define BCHP_SWITCH_CORE_MIB_SNAPSHOT_CTL_SNAPSHOT_MIRROR_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: MIB_SNAPSHOT_CTL :: SWITCH_RESV [05:05] */
-#define BCHP_SWITCH_CORE_MIB_SNAPSHOT_CTL_SWITCH_RESV_MASK 0x00000020
-#define BCHP_SWITCH_CORE_MIB_SNAPSHOT_CTL_SWITCH_RESV_SHIFT 5
-#define BCHP_SWITCH_CORE_MIB_SNAPSHOT_CTL_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: MIB_SNAPSHOT_CTL :: RST_MIB_SNAPSHOT_CNT_EN [04:04] */
-#define BCHP_SWITCH_CORE_MIB_SNAPSHOT_CTL_RST_MIB_SNAPSHOT_CNT_EN_MASK 0x00000010
-#define BCHP_SWITCH_CORE_MIB_SNAPSHOT_CTL_RST_MIB_SNAPSHOT_CNT_EN_SHIFT 4
-#define BCHP_SWITCH_CORE_MIB_SNAPSHOT_CTL_RST_MIB_SNAPSHOT_CNT_EN_DEFAULT 0x00000001
-
-/* SWITCH_CORE :: MIB_SNAPSHOT_CTL :: SNAPSHOT_PORT [03:00] */
-#define BCHP_SWITCH_CORE_MIB_SNAPSHOT_CTL_SNAPSHOT_PORT_MASK 0x0000000f
-#define BCHP_SWITCH_CORE_MIB_SNAPSHOT_CTL_SNAPSHOT_PORT_SHIFT 0
-#define BCHP_SWITCH_CORE_MIB_SNAPSHOT_CTL_SNAPSHOT_PORT_DEFAULT 0x00000000
-
-/***************************************************************************
- *S_TxOctets - Tx Octets
- ***************************************************************************/
-/* SWITCH_CORE :: S_TxOctets :: COUNT [63:00] */
-#define BCHP_SWITCH_CORE_S_TxOctets_COUNT_MASK 0x00000000ffffffff
-#define BCHP_SWITCH_CORE_S_TxOctets_COUNT_SHIFT 0
-#define BCHP_SWITCH_CORE_S_TxOctets_COUNT_DEFAULT 0x0000000000000000
-
-/***************************************************************************
- *S_TxDropPkts - Tx Drop Packet Counter
- ***************************************************************************/
-/* SWITCH_CORE :: S_TxDropPkts :: COUNT [31:00] */
-#define BCHP_SWITCH_CORE_S_TxDropPkts_COUNT_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_S_TxDropPkts_COUNT_SHIFT 0
-#define BCHP_SWITCH_CORE_S_TxDropPkts_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *S_TxQPKTQ0 - Tx Q0 Packet Counter
- ***************************************************************************/
-/* SWITCH_CORE :: S_TxQPKTQ0 :: COUNT [31:00] */
-#define BCHP_SWITCH_CORE_S_TxQPKTQ0_COUNT_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_S_TxQPKTQ0_COUNT_SHIFT 0
-#define BCHP_SWITCH_CORE_S_TxQPKTQ0_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *S_TxBroadcastPkts - Tx Broadcast Packet Counter
- ***************************************************************************/
-/* SWITCH_CORE :: S_TxBroadcastPkts :: COUNT [31:00] */
-#define BCHP_SWITCH_CORE_S_TxBroadcastPkts_COUNT_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_S_TxBroadcastPkts_COUNT_SHIFT 0
-#define BCHP_SWITCH_CORE_S_TxBroadcastPkts_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *S_TxMulticastPkts - Tx Multicast Packet Counter
- ***************************************************************************/
-/* SWITCH_CORE :: S_TxMulticastPkts :: COUNT [31:00] */
-#define BCHP_SWITCH_CORE_S_TxMulticastPkts_COUNT_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_S_TxMulticastPkts_COUNT_SHIFT 0
-#define BCHP_SWITCH_CORE_S_TxMulticastPkts_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *S_TxUnicastPkts - Tx Unicast Packet Counter
- ***************************************************************************/
-/* SWITCH_CORE :: S_TxUnicastPkts :: COUNT [31:00] */
-#define BCHP_SWITCH_CORE_S_TxUnicastPkts_COUNT_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_S_TxUnicastPkts_COUNT_SHIFT 0
-#define BCHP_SWITCH_CORE_S_TxUnicastPkts_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *S_TxCollisions - Tx Collision Counter
- ***************************************************************************/
-/* SWITCH_CORE :: S_TxCollisions :: COUNT [31:00] */
-#define BCHP_SWITCH_CORE_S_TxCollisions_COUNT_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_S_TxCollisions_COUNT_SHIFT 0
-#define BCHP_SWITCH_CORE_S_TxCollisions_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *S_TxSingleCollision - Tx Single Collision Counter
- ***************************************************************************/
-/* SWITCH_CORE :: S_TxSingleCollision :: COUNT [31:00] */
-#define BCHP_SWITCH_CORE_S_TxSingleCollision_COUNT_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_S_TxSingleCollision_COUNT_SHIFT 0
-#define BCHP_SWITCH_CORE_S_TxSingleCollision_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *S_TxMultipleCollision - Tx Multiple collsion Counter
- ***************************************************************************/
-/* SWITCH_CORE :: S_TxMultipleCollision :: COUNT [31:00] */
-#define BCHP_SWITCH_CORE_S_TxMultipleCollision_COUNT_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_S_TxMultipleCollision_COUNT_SHIFT 0
-#define BCHP_SWITCH_CORE_S_TxMultipleCollision_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *S_TxDeferredTransmit - Tx Deferred Transmit Counter
- ***************************************************************************/
-/* SWITCH_CORE :: S_TxDeferredTransmit :: COUNT [31:00] */
-#define BCHP_SWITCH_CORE_S_TxDeferredTransmit_COUNT_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_S_TxDeferredTransmit_COUNT_SHIFT 0
-#define BCHP_SWITCH_CORE_S_TxDeferredTransmit_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *S_TxLateCollision - Tx Late Collision Counter
- ***************************************************************************/
-/* SWITCH_CORE :: S_TxLateCollision :: COUNT [31:00] */
-#define BCHP_SWITCH_CORE_S_TxLateCollision_COUNT_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_S_TxLateCollision_COUNT_SHIFT 0
-#define BCHP_SWITCH_CORE_S_TxLateCollision_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *S_TxExcessiveCollision - Tx Excessive Collision Counter
- ***************************************************************************/
-/* SWITCH_CORE :: S_TxExcessiveCollision :: COUNT [31:00] */
-#define BCHP_SWITCH_CORE_S_TxExcessiveCollision_COUNT_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_S_TxExcessiveCollision_COUNT_SHIFT 0
-#define BCHP_SWITCH_CORE_S_TxExcessiveCollision_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *S_TxFrameInDisc - Tx Fram IN Disc Counter
- ***************************************************************************/
-/* SWITCH_CORE :: S_TxFrameInDisc :: COUNT [31:00] */
-#define BCHP_SWITCH_CORE_S_TxFrameInDisc_COUNT_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_S_TxFrameInDisc_COUNT_SHIFT 0
-#define BCHP_SWITCH_CORE_S_TxFrameInDisc_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *S_TxPausePkts - Tx Pause Packet Counter
- ***************************************************************************/
-/* SWITCH_CORE :: S_TxPausePkts :: COUNT [31:00] */
-#define BCHP_SWITCH_CORE_S_TxPausePkts_COUNT_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_S_TxPausePkts_COUNT_SHIFT 0
-#define BCHP_SWITCH_CORE_S_TxPausePkts_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *S_TxQPKTQ1 - Tx Q1 Packet Counter
- ***************************************************************************/
-/* SWITCH_CORE :: S_TxQPKTQ1 :: COUNT [31:00] */
-#define BCHP_SWITCH_CORE_S_TxQPKTQ1_COUNT_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_S_TxQPKTQ1_COUNT_SHIFT 0
-#define BCHP_SWITCH_CORE_S_TxQPKTQ1_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *S_TxQPKTQ2 - Tx Q2 Packet Counter
- ***************************************************************************/
-/* SWITCH_CORE :: S_TxQPKTQ2 :: COUNT [31:00] */
-#define BCHP_SWITCH_CORE_S_TxQPKTQ2_COUNT_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_S_TxQPKTQ2_COUNT_SHIFT 0
-#define BCHP_SWITCH_CORE_S_TxQPKTQ2_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *S_TxQPKTQ3 - Tx Q3 Packet Counter
- ***************************************************************************/
-/* SWITCH_CORE :: S_TxQPKTQ3 :: COUNT [31:00] */
-#define BCHP_SWITCH_CORE_S_TxQPKTQ3_COUNT_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_S_TxQPKTQ3_COUNT_SHIFT 0
-#define BCHP_SWITCH_CORE_S_TxQPKTQ3_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *S_TxQPKTQ4 - Tx Q4 Packet Counter
- ***************************************************************************/
-/* SWITCH_CORE :: S_TxQPKTQ4 :: COUNT [31:00] */
-#define BCHP_SWITCH_CORE_S_TxQPKTQ4_COUNT_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_S_TxQPKTQ4_COUNT_SHIFT 0
-#define BCHP_SWITCH_CORE_S_TxQPKTQ4_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *S_TxQPKTQ5 - Tx Q5 Packet Counter
- ***************************************************************************/
-/* SWITCH_CORE :: S_TxQPKTQ5 :: COUNT [31:00] */
-#define BCHP_SWITCH_CORE_S_TxQPKTQ5_COUNT_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_S_TxQPKTQ5_COUNT_SHIFT 0
-#define BCHP_SWITCH_CORE_S_TxQPKTQ5_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *S_RxOctets - Rx Packet Octets Counter
- ***************************************************************************/
-/* SWITCH_CORE :: S_RxOctets :: COUNT [63:00] */
-#define BCHP_SWITCH_CORE_S_RxOctets_COUNT_MASK 0x00000000ffffffff
-#define BCHP_SWITCH_CORE_S_RxOctets_COUNT_SHIFT 0
-#define BCHP_SWITCH_CORE_S_RxOctets_COUNT_DEFAULT 0x0000000000000000
-
-/***************************************************************************
- *S_RxUndersizePkts - Rx Under Size Packet Octets Counter
- ***************************************************************************/
-/* SWITCH_CORE :: S_RxUndersizePkts :: COUNT [31:00] */
-#define BCHP_SWITCH_CORE_S_RxUndersizePkts_COUNT_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_S_RxUndersizePkts_COUNT_SHIFT 0
-#define BCHP_SWITCH_CORE_S_RxUndersizePkts_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *S_RxPausePkts - Rx Pause Packet Counter
- ***************************************************************************/
-/* SWITCH_CORE :: S_RxPausePkts :: COUNT [31:00] */
-#define BCHP_SWITCH_CORE_S_RxPausePkts_COUNT_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_S_RxPausePkts_COUNT_SHIFT 0
-#define BCHP_SWITCH_CORE_S_RxPausePkts_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *S_RxPkts64Octets - Rx 64 Bytes Octets Counter
- ***************************************************************************/
-/* SWITCH_CORE :: S_RxPkts64Octets :: COUNT [31:00] */
-#define BCHP_SWITCH_CORE_S_RxPkts64Octets_COUNT_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_S_RxPkts64Octets_COUNT_SHIFT 0
-#define BCHP_SWITCH_CORE_S_RxPkts64Octets_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *S_RxPkts65to127Octets - Rx 65 to 127 Bytes Octets Counter
- ***************************************************************************/
-/* SWITCH_CORE :: S_RxPkts65to127Octets :: COUNT [31:00] */
-#define BCHP_SWITCH_CORE_S_RxPkts65to127Octets_COUNT_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_S_RxPkts65to127Octets_COUNT_SHIFT 0
-#define BCHP_SWITCH_CORE_S_RxPkts65to127Octets_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *S_RxPkts128to255Octets - Rx 128 to 255 Bytes Octets Counter
- ***************************************************************************/
-/* SWITCH_CORE :: S_RxPkts128to255Octets :: COUNT [31:00] */
-#define BCHP_SWITCH_CORE_S_RxPkts128to255Octets_COUNT_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_S_RxPkts128to255Octets_COUNT_SHIFT 0
-#define BCHP_SWITCH_CORE_S_RxPkts128to255Octets_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *S_RxPkts256to511Octets - Rx 256 to 511 Bytes Octets Counter
- ***************************************************************************/
-/* SWITCH_CORE :: S_RxPkts256to511Octets :: COUNT [31:00] */
-#define BCHP_SWITCH_CORE_S_RxPkts256to511Octets_COUNT_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_S_RxPkts256to511Octets_COUNT_SHIFT 0
-#define BCHP_SWITCH_CORE_S_RxPkts256to511Octets_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *S_RxPkts512to1023Octets - Rx 512 to 1023 Bytes Octets Counter
- ***************************************************************************/
-/* SWITCH_CORE :: S_RxPkts512to1023Octets :: COUNT [31:00] */
-#define BCHP_SWITCH_CORE_S_RxPkts512to1023Octets_COUNT_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_S_RxPkts512to1023Octets_COUNT_SHIFT 0
-#define BCHP_SWITCH_CORE_S_RxPkts512to1023Octets_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *S_RxPkts1024toMaxPktOctets - Rx 1024 to MaxPkt Bytes Octets Counter
- ***************************************************************************/
-/* SWITCH_CORE :: S_RxPkts1024toMaxPktOctets :: COUNT [31:00] */
-#define BCHP_SWITCH_CORE_S_RxPkts1024toMaxPktOctets_COUNT_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_S_RxPkts1024toMaxPktOctets_COUNT_SHIFT 0
-#define BCHP_SWITCH_CORE_S_RxPkts1024toMaxPktOctets_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *S_RxOversizePkts - Rx Over Size Packet Counter
- ***************************************************************************/
-/* SWITCH_CORE :: S_RxOversizePkts :: COUNT [31:00] */
-#define BCHP_SWITCH_CORE_S_RxOversizePkts_COUNT_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_S_RxOversizePkts_COUNT_SHIFT 0
-#define BCHP_SWITCH_CORE_S_RxOversizePkts_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *S_RxJabbers - Rx Jabber Packet Counter
- ***************************************************************************/
-/* SWITCH_CORE :: S_RxJabbers :: COUNT [31:00] */
-#define BCHP_SWITCH_CORE_S_RxJabbers_COUNT_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_S_RxJabbers_COUNT_SHIFT 0
-#define BCHP_SWITCH_CORE_S_RxJabbers_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *S_RxAlignmentErrors - Rx Alignment Error Counter
- ***************************************************************************/
-/* SWITCH_CORE :: S_RxAlignmentErrors :: COUNT [31:00] */
-#define BCHP_SWITCH_CORE_S_RxAlignmentErrors_COUNT_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_S_RxAlignmentErrors_COUNT_SHIFT 0
-#define BCHP_SWITCH_CORE_S_RxAlignmentErrors_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *S_RxFCSErrors - Rx FCS Error Counter
- ***************************************************************************/
-/* SWITCH_CORE :: S_RxFCSErrors :: COUNT [31:00] */
-#define BCHP_SWITCH_CORE_S_RxFCSErrors_COUNT_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_S_RxFCSErrors_COUNT_SHIFT 0
-#define BCHP_SWITCH_CORE_S_RxFCSErrors_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *S_RxGoodOctets - Rx Good Packet Octet Counter
- ***************************************************************************/
-/* SWITCH_CORE :: S_RxGoodOctets :: COUNT [63:00] */
-#define BCHP_SWITCH_CORE_S_RxGoodOctets_COUNT_MASK 0x00000000ffffffff
-#define BCHP_SWITCH_CORE_S_RxGoodOctets_COUNT_SHIFT 0
-#define BCHP_SWITCH_CORE_S_RxGoodOctets_COUNT_DEFAULT 0x0000000000000000
-
-/***************************************************************************
- *S_RxDropPkts - Rx Drop Packet Counter
- ***************************************************************************/
-/* SWITCH_CORE :: S_RxDropPkts :: COUNT [31:00] */
-#define BCHP_SWITCH_CORE_S_RxDropPkts_COUNT_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_S_RxDropPkts_COUNT_SHIFT 0
-#define BCHP_SWITCH_CORE_S_RxDropPkts_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *S_RxUnicastPkts - Rx Unicast Packet Counter
- ***************************************************************************/
-/* SWITCH_CORE :: S_RxUnicastPkts :: COUNT [31:00] */
-#define BCHP_SWITCH_CORE_S_RxUnicastPkts_COUNT_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_S_RxUnicastPkts_COUNT_SHIFT 0
-#define BCHP_SWITCH_CORE_S_RxUnicastPkts_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *S_RxMulticastPkts - Rx Multicast Packet Counter
- ***************************************************************************/
-/* SWITCH_CORE :: S_RxMulticastPkts :: COUNT [31:00] */
-#define BCHP_SWITCH_CORE_S_RxMulticastPkts_COUNT_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_S_RxMulticastPkts_COUNT_SHIFT 0
-#define BCHP_SWITCH_CORE_S_RxMulticastPkts_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *S_RxBroadcastPkts - Rx Broadcast Packet Counter
- ***************************************************************************/
-/* SWITCH_CORE :: S_RxBroadcastPkts :: COUNT [31:00] */
-#define BCHP_SWITCH_CORE_S_RxBroadcastPkts_COUNT_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_S_RxBroadcastPkts_COUNT_SHIFT 0
-#define BCHP_SWITCH_CORE_S_RxBroadcastPkts_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *S_RxSAChanges - Rx SA Change Counter
- ***************************************************************************/
-/* SWITCH_CORE :: S_RxSAChanges :: COUNT [31:00] */
-#define BCHP_SWITCH_CORE_S_RxSAChanges_COUNT_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_S_RxSAChanges_COUNT_SHIFT 0
-#define BCHP_SWITCH_CORE_S_RxSAChanges_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *S_RxFragments - Rx Fragment Counter
- ***************************************************************************/
-/* SWITCH_CORE :: S_RxFragments :: COUNT [31:00] */
-#define BCHP_SWITCH_CORE_S_RxFragments_COUNT_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_S_RxFragments_COUNT_SHIFT 0
-#define BCHP_SWITCH_CORE_S_RxFragments_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *S_RxJumboPkt - Jumbo Packet Counter
- ***************************************************************************/
-/* SWITCH_CORE :: S_RxJumboPkt :: COUNT [31:00] */
-#define BCHP_SWITCH_CORE_S_RxJumboPkt_COUNT_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_S_RxJumboPkt_COUNT_SHIFT 0
-#define BCHP_SWITCH_CORE_S_RxJumboPkt_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *S_RxSymblErr - Rx Symbol Error Counter
- ***************************************************************************/
-/* SWITCH_CORE :: S_RxSymblErr :: COUNT [31:00] */
-#define BCHP_SWITCH_CORE_S_RxSymblErr_COUNT_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_S_RxSymblErr_COUNT_SHIFT 0
-#define BCHP_SWITCH_CORE_S_RxSymblErr_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *S_InRangeErrCount - InRangeErrCount Counter
- ***************************************************************************/
-/* SWITCH_CORE :: S_InRangeErrCount :: COUNT [31:00] */
-#define BCHP_SWITCH_CORE_S_InRangeErrCount_COUNT_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_S_InRangeErrCount_COUNT_SHIFT 0
-#define BCHP_SWITCH_CORE_S_InRangeErrCount_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *S_OutRangeErrCount - OutRangeErrCount Counter
- ***************************************************************************/
-/* SWITCH_CORE :: S_OutRangeErrCount :: COUNT [31:00] */
-#define BCHP_SWITCH_CORE_S_OutRangeErrCount_COUNT_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_S_OutRangeErrCount_COUNT_SHIFT 0
-#define BCHP_SWITCH_CORE_S_OutRangeErrCount_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *S_EEE_LPI_EVENT - EEE Low-Power Idle Event Registers
- ***************************************************************************/
-/* SWITCH_CORE :: S_EEE_LPI_EVENT :: COUNT [31:00] */
-#define BCHP_SWITCH_CORE_S_EEE_LPI_EVENT_COUNT_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_S_EEE_LPI_EVENT_COUNT_SHIFT 0
-#define BCHP_SWITCH_CORE_S_EEE_LPI_EVENT_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *S_EEE_LPI_DURATION - EEE Low-Power Idle Duration Registers
- ***************************************************************************/
-/* SWITCH_CORE :: S_EEE_LPI_DURATION :: COUNT [31:00] */
-#define BCHP_SWITCH_CORE_S_EEE_LPI_DURATION_COUNT_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_S_EEE_LPI_DURATION_COUNT_SHIFT 0
-#define BCHP_SWITCH_CORE_S_EEE_LPI_DURATION_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *S_RxDiscard - Rx Discard Counter
- ***************************************************************************/
-/* SWITCH_CORE :: S_RxDiscard :: COUNT [31:00] */
-#define BCHP_SWITCH_CORE_S_RxDiscard_COUNT_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_S_RxDiscard_COUNT_SHIFT 0
-#define BCHP_SWITCH_CORE_S_RxDiscard_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *S_TxQPKTQ6 - Tx Q6 Packet Counter
- ***************************************************************************/
-/* SWITCH_CORE :: S_TxQPKTQ6 :: COUNT [31:00] */
-#define BCHP_SWITCH_CORE_S_TxQPKTQ6_COUNT_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_S_TxQPKTQ6_COUNT_SHIFT 0
-#define BCHP_SWITCH_CORE_S_TxQPKTQ6_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *S_TxQPKTQ7 - Tx Q7 Packet Counter
- ***************************************************************************/
-/* SWITCH_CORE :: S_TxQPKTQ7 :: COUNT [31:00] */
-#define BCHP_SWITCH_CORE_S_TxQPKTQ7_COUNT_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_S_TxQPKTQ7_COUNT_SHIFT 0
-#define BCHP_SWITCH_CORE_S_TxQPKTQ7_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *S_TxPkts64Octets - Tx 64 Bytes Octets Counter
- ***************************************************************************/
-/* SWITCH_CORE :: S_TxPkts64Octets :: COUNT [31:00] */
-#define BCHP_SWITCH_CORE_S_TxPkts64Octets_COUNT_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_S_TxPkts64Octets_COUNT_SHIFT 0
-#define BCHP_SWITCH_CORE_S_TxPkts64Octets_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *S_TxPkts65to127Octets - Tx 65 to 127 Bytes Octets Counter
- ***************************************************************************/
-/* SWITCH_CORE :: S_TxPkts65to127Octets :: COUNT [31:00] */
-#define BCHP_SWITCH_CORE_S_TxPkts65to127Octets_COUNT_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_S_TxPkts65to127Octets_COUNT_SHIFT 0
-#define BCHP_SWITCH_CORE_S_TxPkts65to127Octets_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *S_TxPkts128to255Octets - Tx 128 to 255 Bytes Octets Counter
- ***************************************************************************/
-/* SWITCH_CORE :: S_TxPkts128to255Octets :: COUNT [31:00] */
-#define BCHP_SWITCH_CORE_S_TxPkts128to255Octets_COUNT_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_S_TxPkts128to255Octets_COUNT_SHIFT 0
-#define BCHP_SWITCH_CORE_S_TxPkts128to255Octets_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *S_TxPkts256to511Octets - Tx 256 to 511 Bytes Octets Counter
- ***************************************************************************/
-/* SWITCH_CORE :: S_TxPkts256to511Octets :: COUNT [31:00] */
-#define BCHP_SWITCH_CORE_S_TxPkts256to511Octets_COUNT_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_S_TxPkts256to511Octets_COUNT_SHIFT 0
-#define BCHP_SWITCH_CORE_S_TxPkts256to511Octets_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *S_TxPkts512to1023Octets - Tx 512 to 1023 Bytes Octets Counter
- ***************************************************************************/
-/* SWITCH_CORE :: S_TxPkts512to1023Octets :: COUNT [31:00] */
-#define BCHP_SWITCH_CORE_S_TxPkts512to1023Octets_COUNT_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_S_TxPkts512to1023Octets_COUNT_SHIFT 0
-#define BCHP_SWITCH_CORE_S_TxPkts512to1023Octets_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *S_TxPkts1024toMaxPktOctets - Tx 1024 to MaxPkt Bytes Octets Counter
- ***************************************************************************/
-/* SWITCH_CORE :: S_TxPkts1024toMaxPktOctets :: COUNT [31:00] */
-#define BCHP_SWITCH_CORE_S_TxPkts1024toMaxPktOctets_COUNT_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_S_TxPkts1024toMaxPktOctets_COUNT_SHIFT 0
-#define BCHP_SWITCH_CORE_S_TxPkts1024toMaxPktOctets_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *LPDET_CFG - Loop Detection Configuration RegistersNot2Release
- ***************************************************************************/
-/* SWITCH_CORE :: LPDET_CFG :: reserved_for_padding0 [31:16] */
-#define BCHP_SWITCH_CORE_LPDET_CFG_reserved_for_padding0_MASK 0xffff0000
-#define BCHP_SWITCH_CORE_LPDET_CFG_reserved_for_padding0_SHIFT 16
-
-/* SWITCH_CORE :: LPDET_CFG :: SWITCH_RESV [15:15] */
-#define BCHP_SWITCH_CORE_LPDET_CFG_SWITCH_RESV_MASK 0x00008000
-#define BCHP_SWITCH_CORE_LPDET_CFG_SWITCH_RESV_SHIFT 15
-#define BCHP_SWITCH_CORE_LPDET_CFG_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: LPDET_CFG :: DFQ_SEL2 [14:14] */
-#define BCHP_SWITCH_CORE_LPDET_CFG_DFQ_SEL2_MASK 0x00004000
-#define BCHP_SWITCH_CORE_LPDET_CFG_DFQ_SEL2_SHIFT 14
-#define BCHP_SWITCH_CORE_LPDET_CFG_DFQ_SEL2_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: LPDET_CFG :: EN_TXPASS [13:13] */
-#define BCHP_SWITCH_CORE_LPDET_CFG_EN_TXPASS_MASK 0x00002000
-#define BCHP_SWITCH_CORE_LPDET_CFG_EN_TXPASS_SHIFT 13
-#define BCHP_SWITCH_CORE_LPDET_CFG_EN_TXPASS_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: LPDET_CFG :: EN_LPDET [12:12] */
-#define BCHP_SWITCH_CORE_LPDET_CFG_EN_LPDET_MASK 0x00001000
-#define BCHP_SWITCH_CORE_LPDET_CFG_EN_LPDET_SHIFT 12
-#define BCHP_SWITCH_CORE_LPDET_CFG_EN_LPDET_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: LPDET_CFG :: LOOP_IMP_SEL [11:11] */
-#define BCHP_SWITCH_CORE_LPDET_CFG_LOOP_IMP_SEL_MASK 0x00000800
-#define BCHP_SWITCH_CORE_LPDET_CFG_LOOP_IMP_SEL_SHIFT 11
-#define BCHP_SWITCH_CORE_LPDET_CFG_LOOP_IMP_SEL_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: LPDET_CFG :: LED_RST_CTL [10:03] */
-#define BCHP_SWITCH_CORE_LPDET_CFG_LED_RST_CTL_MASK 0x000007f8
-#define BCHP_SWITCH_CORE_LPDET_CFG_LED_RST_CTL_SHIFT 3
-#define BCHP_SWITCH_CORE_LPDET_CFG_LED_RST_CTL_DEFAULT 0x00000004
-
-/* SWITCH_CORE :: LPDET_CFG :: OV_PAUSE_ON [02:02] */
-#define BCHP_SWITCH_CORE_LPDET_CFG_OV_PAUSE_ON_MASK 0x00000004
-#define BCHP_SWITCH_CORE_LPDET_CFG_OV_PAUSE_ON_SHIFT 2
-#define BCHP_SWITCH_CORE_LPDET_CFG_OV_PAUSE_ON_DEFAULT 0x00000001
-
-/* SWITCH_CORE :: LPDET_CFG :: DFQ_SEL [01:00] */
-#define BCHP_SWITCH_CORE_LPDET_CFG_DFQ_SEL_MASK 0x00000003
-#define BCHP_SWITCH_CORE_LPDET_CFG_DFQ_SEL_SHIFT 0
-#define BCHP_SWITCH_CORE_LPDET_CFG_DFQ_SEL_DEFAULT 0x00000001
-
-/***************************************************************************
- *DF_TIMER - Discovery Frame Timer RegistersNot2Release
- ***************************************************************************/
-/* SWITCH_CORE :: DF_TIMER :: reserved_for_padding0 [31:08] */
-#define BCHP_SWITCH_CORE_DF_TIMER_reserved_for_padding0_MASK 0xffffff00
-#define BCHP_SWITCH_CORE_DF_TIMER_reserved_for_padding0_SHIFT 8
-
-/* SWITCH_CORE :: DF_TIMER :: SWITCH_RESV [07:04] */
-#define BCHP_SWITCH_CORE_DF_TIMER_SWITCH_RESV_MASK 0x000000f0
-#define BCHP_SWITCH_CORE_DF_TIMER_SWITCH_RESV_SHIFT 4
-#define BCHP_SWITCH_CORE_DF_TIMER_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: DF_TIMER :: DF_TIME [03:00] */
-#define BCHP_SWITCH_CORE_DF_TIMER_DF_TIME_MASK 0x0000000f
-#define BCHP_SWITCH_CORE_DF_TIMER_DF_TIME_SHIFT 0
-#define BCHP_SWITCH_CORE_DF_TIMER_DF_TIME_DEFAULT 0x00000000
-
-/***************************************************************************
- *LED_PORTMAP - LED Waming Portmap RegistersNot2Release
- ***************************************************************************/
-/* SWITCH_CORE :: LED_PORTMAP :: reserved_for_padding0 [31:16] */
-#define BCHP_SWITCH_CORE_LED_PORTMAP_reserved_for_padding0_MASK 0xffff0000
-#define BCHP_SWITCH_CORE_LED_PORTMAP_reserved_for_padding0_SHIFT 16
-
-/* SWITCH_CORE :: LED_PORTMAP :: SWITCH_RESV [15:09] */
-#define BCHP_SWITCH_CORE_LED_PORTMAP_SWITCH_RESV_MASK 0x0000fe00
-#define BCHP_SWITCH_CORE_LED_PORTMAP_SWITCH_RESV_SHIFT 9
-#define BCHP_SWITCH_CORE_LED_PORTMAP_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: LED_PORTMAP :: LED_WARNING_PORTMAP [08:00] */
-#define BCHP_SWITCH_CORE_LED_PORTMAP_LED_WARNING_PORTMAP_MASK 0x000001ff
-#define BCHP_SWITCH_CORE_LED_PORTMAP_LED_WARNING_PORTMAP_SHIFT 0
-#define BCHP_SWITCH_CORE_LED_PORTMAP_LED_WARNING_PORTMAP_DEFAULT 0x00000000
-
-/***************************************************************************
- *MODULE_ID0 - Module ID 0 RegistersNot2Release
- ***************************************************************************/
-/* SWITCH_CORE :: MODULE_ID0 :: MID_SA [47:00] */
-#define BCHP_SWITCH_CORE_MODULE_ID0_MID_SA_MASK 0x00000000ffff
-#define BCHP_SWITCH_CORE_MODULE_ID0_MID_SA_SHIFT 0
-#define BCHP_SWITCH_CORE_MODULE_ID0_MID_SA_DEFAULT 0x000000000000
-
-/***************************************************************************
- *MODULE_ID1 - Module ID 1 RegistersNot2Release
- ***************************************************************************/
-/* SWITCH_CORE :: MODULE_ID1 :: MID_AVAIL [47:47] */
-#define BCHP_SWITCH_CORE_MODULE_ID1_MID_AVAIL_MASK 0x000000008000
-#define BCHP_SWITCH_CORE_MODULE_ID1_MID_AVAIL_SHIFT 47
-#define BCHP_SWITCH_CORE_MODULE_ID1_MID_AVAIL_DEFAULT 0x000000000000
-
-/* SWITCH_CORE :: MODULE_ID1 :: SWITCH_RESV [46:40] */
-#define BCHP_SWITCH_CORE_MODULE_ID1_SWITCH_RESV_MASK 0x000000007f00
-#define BCHP_SWITCH_CORE_MODULE_ID1_SWITCH_RESV_SHIFT 40
-#define BCHP_SWITCH_CORE_MODULE_ID1_SWITCH_RESV_DEFAULT 0x000000000000
-
-/* SWITCH_CORE :: MODULE_ID1 :: MID_PORTNUM [39:32] */
-#define BCHP_SWITCH_CORE_MODULE_ID1_MID_PORTNUM_MASK 0x0000000000ff
-#define BCHP_SWITCH_CORE_MODULE_ID1_MID_PORTNUM_SHIFT 32
-#define BCHP_SWITCH_CORE_MODULE_ID1_MID_PORTNUM_DEFAULT 0x000000000000
-
-/* SWITCH_CORE :: MODULE_ID1 :: MID_CRC [31:00] */
-#define BCHP_SWITCH_CORE_MODULE_ID1_MID_CRC_MASK 0x0000ffffffff
-#define BCHP_SWITCH_CORE_MODULE_ID1_MID_CRC_SHIFT 0
-#define BCHP_SWITCH_CORE_MODULE_ID1_MID_CRC_DEFAULT 0x000000000000
-
-/***************************************************************************
- *LPDET_SA - Loop Detect Frame SA RegistersNot2Release
- ***************************************************************************/
-/* SWITCH_CORE :: LPDET_SA :: LPDET_SA [47:00] */
-#define BCHP_SWITCH_CORE_LPDET_SA_LPDET_SA_MASK 0x00000000ffff
-#define BCHP_SWITCH_CORE_LPDET_SA_LPDET_SA_SHIFT 0
-#define BCHP_SWITCH_CORE_LPDET_SA_LPDET_SA_DEFAULT 0x0000ffffffff
-
-/***************************************************************************
- *LPDET_REG_SPARE0 - Spare 0 Register (Not2Release)Not2Release
- ***************************************************************************/
-/* SWITCH_CORE :: LPDET_REG_SPARE0 :: LPDET_REG_SPARE0 [31:00] */
-#define BCHP_SWITCH_CORE_LPDET_REG_SPARE0_LPDET_REG_SPARE0_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_LPDET_REG_SPARE0_LPDET_REG_SPARE0_SHIFT 0
-#define BCHP_SWITCH_CORE_LPDET_REG_SPARE0_LPDET_REG_SPARE0_DEFAULT 0x00000000
-
-/***************************************************************************
- *LPDET_REG_SPARE1 - Spare 1 Register (Not2Release)Not2Release
- ***************************************************************************/
-/* SWITCH_CORE :: LPDET_REG_SPARE1 :: LPDET_REG_SPARE1 [31:00] */
-#define BCHP_SWITCH_CORE_LPDET_REG_SPARE1_LPDET_REG_SPARE1_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_LPDET_REG_SPARE1_LPDET_REG_SPARE1_SHIFT 0
-#define BCHP_SWITCH_CORE_LPDET_REG_SPARE1_LPDET_REG_SPARE1_DEFAULT 0x00000000
-
-/***************************************************************************
- *BPM_CTRL - BPM Power Switching Control RegisterNot2Release
- ***************************************************************************/
-/* SWITCH_CORE :: BPM_CTRL :: reserved_for_padding0 [31:08] */
-#define BCHP_SWITCH_CORE_BPM_CTRL_reserved_for_padding0_MASK 0xffffff00
-#define BCHP_SWITCH_CORE_BPM_CTRL_reserved_for_padding0_SHIFT 8
-
-/* SWITCH_CORE :: BPM_CTRL :: SWITCH_RESV [07:05] */
-#define BCHP_SWITCH_CORE_BPM_CTRL_SWITCH_RESV_MASK 0x000000e0
-#define BCHP_SWITCH_CORE_BPM_CTRL_SWITCH_RESV_SHIFT 5
-#define BCHP_SWITCH_CORE_BPM_CTRL_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: BPM_CTRL :: RX_PORT_KEEP2PAGE [04:04] */
-#define BCHP_SWITCH_CORE_BPM_CTRL_RX_PORT_KEEP2PAGE_MASK 0x00000010
-#define BCHP_SWITCH_CORE_BPM_CTRL_RX_PORT_KEEP2PAGE_SHIFT 4
-#define BCHP_SWITCH_CORE_BPM_CTRL_RX_PORT_KEEP2PAGE_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: BPM_CTRL :: PDA_CHG_OPT [03:03] */
-#define BCHP_SWITCH_CORE_BPM_CTRL_PDA_CHG_OPT_MASK 0x00000008
-#define BCHP_SWITCH_CORE_BPM_CTRL_PDA_CHG_OPT_SHIFT 3
-#define BCHP_SWITCH_CORE_BPM_CTRL_PDA_CHG_OPT_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: BPM_CTRL :: BFCFIFO_RECYCLE_EN [02:02] */
-#define BCHP_SWITCH_CORE_BPM_CTRL_BFCFIFO_RECYCLE_EN_MASK 0x00000004
-#define BCHP_SWITCH_CORE_BPM_CTRL_BFCFIFO_RECYCLE_EN_SHIFT 2
-#define BCHP_SWITCH_CORE_BPM_CTRL_BFCFIFO_RECYCLE_EN_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: BPM_CTRL :: PTR_RECYCLE_EN [01:01] */
-#define BCHP_SWITCH_CORE_BPM_CTRL_PTR_RECYCLE_EN_MASK 0x00000002
-#define BCHP_SWITCH_CORE_BPM_CTRL_PTR_RECYCLE_EN_SHIFT 1
-#define BCHP_SWITCH_CORE_BPM_CTRL_PTR_RECYCLE_EN_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: BPM_CTRL :: PSM_SW_EN [00:00] */
-#define BCHP_SWITCH_CORE_BPM_CTRL_PSM_SW_EN_MASK 0x00000001
-#define BCHP_SWITCH_CORE_BPM_CTRL_PSM_SW_EN_SHIFT 0
-#define BCHP_SWITCH_CORE_BPM_CTRL_PSM_SW_EN_DEFAULT 0x00000000
-
-/***************************************************************************
- *BPM_PSM_OVR_CTRL - BPM Power Switching SW Override RegisterNot2Release
- ***************************************************************************/
-/* SWITCH_CORE :: BPM_PSM_OVR_CTRL :: reserved_for_padding0 [31:08] */
-#define BCHP_SWITCH_CORE_BPM_PSM_OVR_CTRL_reserved_for_padding0_MASK 0xffffff00
-#define BCHP_SWITCH_CORE_BPM_PSM_OVR_CTRL_reserved_for_padding0_SHIFT 8
-
-/* SWITCH_CORE :: BPM_PSM_OVR_CTRL :: PSM_SW_OVERRIDE_EN [07:07] */
-#define BCHP_SWITCH_CORE_BPM_PSM_OVR_CTRL_PSM_SW_OVERRIDE_EN_MASK 0x00000080
-#define BCHP_SWITCH_CORE_BPM_PSM_OVR_CTRL_PSM_SW_OVERRIDE_EN_SHIFT 7
-#define BCHP_SWITCH_CORE_BPM_PSM_OVR_CTRL_PSM_SW_OVERRIDE_EN_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: BPM_PSM_OVR_CTRL :: SWITCH_RESV [06:03] */
-#define BCHP_SWITCH_CORE_BPM_PSM_OVR_CTRL_SWITCH_RESV_MASK 0x00000078
-#define BCHP_SWITCH_CORE_BPM_PSM_OVR_CTRL_SWITCH_RESV_SHIFT 3
-#define BCHP_SWITCH_CORE_BPM_PSM_OVR_CTRL_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: BPM_PSM_OVR_CTRL :: PSM_SW_OVERRIDE [02:00] */
-#define BCHP_SWITCH_CORE_BPM_PSM_OVR_CTRL_PSM_SW_OVERRIDE_MASK 0x00000007
-#define BCHP_SWITCH_CORE_BPM_PSM_OVR_CTRL_PSM_SW_OVERRIDE_SHIFT 0
-#define BCHP_SWITCH_CORE_BPM_PSM_OVR_CTRL_PSM_SW_OVERRIDE_DEFAULT 0x00000000
-
-/***************************************************************************
- *BPM_PSM_TIME_CFG - PSM_VDD Timing Parameter Configuration RegisterNot2Release
- ***************************************************************************/
-/* SWITCH_CORE :: BPM_PSM_TIME_CFG :: reserved_for_padding0 [31:16] */
-#define BCHP_SWITCH_CORE_BPM_PSM_TIME_CFG_reserved_for_padding0_MASK 0xffff0000
-#define BCHP_SWITCH_CORE_BPM_PSM_TIME_CFG_reserved_for_padding0_SHIFT 16
-
-/* SWITCH_CORE :: BPM_PSM_TIME_CFG :: DPSM_CNT [15:08] */
-#define BCHP_SWITCH_CORE_BPM_PSM_TIME_CFG_DPSM_CNT_MASK 0x0000ff00
-#define BCHP_SWITCH_CORE_BPM_PSM_TIME_CFG_DPSM_CNT_SHIFT 8
-#define BCHP_SWITCH_CORE_BPM_PSM_TIME_CFG_DPSM_CNT_DEFAULT 0x00000017
-
-/* SWITCH_CORE :: BPM_PSM_TIME_CFG :: MPSM_CNT [07:00] */
-#define BCHP_SWITCH_CORE_BPM_PSM_TIME_CFG_MPSM_CNT_MASK 0x000000ff
-#define BCHP_SWITCH_CORE_BPM_PSM_TIME_CFG_MPSM_CNT_SHIFT 0
-#define BCHP_SWITCH_CORE_BPM_PSM_TIME_CFG_MPSM_CNT_DEFAULT 0x00000002
-
-/***************************************************************************
- *BPM_PSM_THD_CFG - PSM_VDD Switching Threshold Configuration RegisterNot2Release
- ***************************************************************************/
-/* SWITCH_CORE :: BPM_PSM_THD_CFG :: SWITCH_RESV_1 [31:28] */
-#define BCHP_SWITCH_CORE_BPM_PSM_THD_CFG_SWITCH_RESV_1_MASK 0xf0000000
-#define BCHP_SWITCH_CORE_BPM_PSM_THD_CFG_SWITCH_RESV_1_SHIFT 28
-#define BCHP_SWITCH_CORE_BPM_PSM_THD_CFG_SWITCH_RESV_1_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: BPM_PSM_THD_CFG :: PSM_ON_THD [27:16] */
-#define BCHP_SWITCH_CORE_BPM_PSM_THD_CFG_PSM_ON_THD_MASK 0x0fff0000
-#define BCHP_SWITCH_CORE_BPM_PSM_THD_CFG_PSM_ON_THD_SHIFT 16
-#define BCHP_SWITCH_CORE_BPM_PSM_THD_CFG_PSM_ON_THD_DEFAULT 0x00000027
-
-/* SWITCH_CORE :: BPM_PSM_THD_CFG :: SWITCH_RESV_0 [15:12] */
-#define BCHP_SWITCH_CORE_BPM_PSM_THD_CFG_SWITCH_RESV_0_MASK 0x0000f000
-#define BCHP_SWITCH_CORE_BPM_PSM_THD_CFG_SWITCH_RESV_0_SHIFT 12
-#define BCHP_SWITCH_CORE_BPM_PSM_THD_CFG_SWITCH_RESV_0_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: BPM_PSM_THD_CFG :: PSM_OFF_THD [11:00] */
-#define BCHP_SWITCH_CORE_BPM_PSM_THD_CFG_PSM_OFF_THD_MASK 0x00000fff
-#define BCHP_SWITCH_CORE_BPM_PSM_THD_CFG_PSM_OFF_THD_SHIFT 0
-#define BCHP_SWITCH_CORE_BPM_PSM_THD_CFG_PSM_OFF_THD_DEFAULT 0x00000050
-
-/***************************************************************************
- *ROW_VMASK_OVR_CTRL - BUFCON Row Status Valid Mask SW Override Control RegisterNot2Release
- ***************************************************************************/
-/* SWITCH_CORE :: ROW_VMASK_OVR_CTRL :: reserved_for_padding0 [31:16] */
-#define BCHP_SWITCH_CORE_ROW_VMASK_OVR_CTRL_reserved_for_padding0_MASK 0xffff0000
-#define BCHP_SWITCH_CORE_ROW_VMASK_OVR_CTRL_reserved_for_padding0_SHIFT 16
-
-/* SWITCH_CORE :: ROW_VMASK_OVR_CTRL :: OVERRIDE_EN [15:15] */
-#define BCHP_SWITCH_CORE_ROW_VMASK_OVR_CTRL_OVERRIDE_EN_MASK 0x00008000
-#define BCHP_SWITCH_CORE_ROW_VMASK_OVR_CTRL_OVERRIDE_EN_SHIFT 15
-#define BCHP_SWITCH_CORE_ROW_VMASK_OVR_CTRL_OVERRIDE_EN_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: ROW_VMASK_OVR_CTRL :: SWITCH_RESV [14:12] */
-#define BCHP_SWITCH_CORE_ROW_VMASK_OVR_CTRL_SWITCH_RESV_MASK 0x00007000
-#define BCHP_SWITCH_CORE_ROW_VMASK_OVR_CTRL_SWITCH_RESV_SHIFT 12
-#define BCHP_SWITCH_CORE_ROW_VMASK_OVR_CTRL_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: ROW_VMASK_OVR_CTRL :: OVERRIDE_VAL [11:00] */
-#define BCHP_SWITCH_CORE_ROW_VMASK_OVR_CTRL_OVERRIDE_VAL_MASK 0x00000fff
-#define BCHP_SWITCH_CORE_ROW_VMASK_OVR_CTRL_OVERRIDE_VAL_SHIFT 0
-#define BCHP_SWITCH_CORE_ROW_VMASK_OVR_CTRL_OVERRIDE_VAL_DEFAULT 0x00000fff
-
-/***************************************************************************
- *BPM_STS - BPM Status RegisterNot2Release
- ***************************************************************************/
-/* SWITCH_CORE :: BPM_STS :: PBB_PWR_STS [31:29] */
-#define BCHP_SWITCH_CORE_BPM_STS_PBB_PWR_STS_MASK 0xe0000000
-#define BCHP_SWITCH_CORE_BPM_STS_PBB_PWR_STS_SHIFT 29
-#define BCHP_SWITCH_CORE_BPM_STS_PBB_PWR_STS_DEFAULT 0x00000007
-
-/* SWITCH_CORE :: BPM_STS :: SWITCH_RESV_1 [28:28] */
-#define BCHP_SWITCH_CORE_BPM_STS_SWITCH_RESV_1_MASK 0x10000000
-#define BCHP_SWITCH_CORE_BPM_STS_SWITCH_RESV_1_SHIFT 28
-#define BCHP_SWITCH_CORE_BPM_STS_SWITCH_RESV_1_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: BPM_STS :: ROW_USE_STS [27:16] */
-#define BCHP_SWITCH_CORE_BPM_STS_ROW_USE_STS_MASK 0x0fff0000
-#define BCHP_SWITCH_CORE_BPM_STS_ROW_USE_STS_SHIFT 16
-#define BCHP_SWITCH_CORE_BPM_STS_ROW_USE_STS_DEFAULT 0x00000001
-
-/* SWITCH_CORE :: BPM_STS :: SWITCH_RESV_0 [15:14] */
-#define BCHP_SWITCH_CORE_BPM_STS_SWITCH_RESV_0_MASK 0x0000c000
-#define BCHP_SWITCH_CORE_BPM_STS_SWITCH_RESV_0_SHIFT 14
-#define BCHP_SWITCH_CORE_BPM_STS_SWITCH_RESV_0_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: BPM_STS :: CUR_PBB [13:12] */
-#define BCHP_SWITCH_CORE_BPM_STS_CUR_PBB_MASK 0x00003000
-#define BCHP_SWITCH_CORE_BPM_STS_CUR_PBB_SHIFT 12
-#define BCHP_SWITCH_CORE_BPM_STS_CUR_PBB_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: BPM_STS :: ROW_VMASK [11:00] */
-#define BCHP_SWITCH_CORE_BPM_STS_ROW_VMASK_MASK 0x00000fff
-#define BCHP_SWITCH_CORE_BPM_STS_ROW_VMASK_SHIFT 0
-#define BCHP_SWITCH_CORE_BPM_STS_ROW_VMASK_DEFAULT 0x00000fff
-
-/***************************************************************************
- *BPM_PDA_OVR_CTRL - BPM PDA Switching SW Override Control RegisterNot2Release
- ***************************************************************************/
-/* SWITCH_CORE :: BPM_PDA_OVR_CTRL :: reserved_for_padding0 [31:16] */
-#define BCHP_SWITCH_CORE_BPM_PDA_OVR_CTRL_reserved_for_padding0_MASK 0xffff0000
-#define BCHP_SWITCH_CORE_BPM_PDA_OVR_CTRL_reserved_for_padding0_SHIFT 16
-
-/* SWITCH_CORE :: BPM_PDA_OVR_CTRL :: OVERRIDE_EN [15:15] */
-#define BCHP_SWITCH_CORE_BPM_PDA_OVR_CTRL_OVERRIDE_EN_MASK 0x00008000
-#define BCHP_SWITCH_CORE_BPM_PDA_OVR_CTRL_OVERRIDE_EN_SHIFT 15
-#define BCHP_SWITCH_CORE_BPM_PDA_OVR_CTRL_OVERRIDE_EN_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: BPM_PDA_OVR_CTRL :: OVERRIDE_DONE [14:14] */
-#define BCHP_SWITCH_CORE_BPM_PDA_OVR_CTRL_OVERRIDE_DONE_MASK 0x00004000
-#define BCHP_SWITCH_CORE_BPM_PDA_OVR_CTRL_OVERRIDE_DONE_SHIFT 14
-#define BCHP_SWITCH_CORE_BPM_PDA_OVR_CTRL_OVERRIDE_DONE_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: BPM_PDA_OVR_CTRL :: SWITCH_RESV [13:12] */
-#define BCHP_SWITCH_CORE_BPM_PDA_OVR_CTRL_SWITCH_RESV_MASK 0x00003000
-#define BCHP_SWITCH_CORE_BPM_PDA_OVR_CTRL_SWITCH_RESV_SHIFT 12
-#define BCHP_SWITCH_CORE_BPM_PDA_OVR_CTRL_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: BPM_PDA_OVR_CTRL :: OVERRIDE_VAL [11:00] */
-#define BCHP_SWITCH_CORE_BPM_PDA_OVR_CTRL_OVERRIDE_VAL_MASK 0x00000fff
-#define BCHP_SWITCH_CORE_BPM_PDA_OVR_CTRL_OVERRIDE_VAL_SHIFT 0
-#define BCHP_SWITCH_CORE_BPM_PDA_OVR_CTRL_OVERRIDE_VAL_DEFAULT 0x00000000
-
-/***************************************************************************
- *PDA_TIMEOUT_CFG - BPM PDA Switching Timeout Counter RegisterNot2Release
- ***************************************************************************/
-/* SWITCH_CORE :: PDA_TIMEOUT_CFG :: reserved_for_padding0 [31:16] */
-#define BCHP_SWITCH_CORE_PDA_TIMEOUT_CFG_reserved_for_padding0_MASK 0xffff0000
-#define BCHP_SWITCH_CORE_PDA_TIMEOUT_CFG_reserved_for_padding0_SHIFT 16
-
-/* SWITCH_CORE :: PDA_TIMEOUT_CFG :: PDA_TIMEOUT_CNT [15:00] */
-#define BCHP_SWITCH_CORE_PDA_TIMEOUT_CFG_PDA_TIMEOUT_CNT_MASK 0x0000ffff
-#define BCHP_SWITCH_CORE_PDA_TIMEOUT_CFG_PDA_TIMEOUT_CNT_SHIFT 0
-#define BCHP_SWITCH_CORE_PDA_TIMEOUT_CFG_PDA_TIMEOUT_CNT_DEFAULT 0x00000100
-
-/***************************************************************************
- *PDA_SETUP_TIME_CFG - BPM PDA Switching Setup Time RegisterNot2Release
- ***************************************************************************/
-/* SWITCH_CORE :: PDA_SETUP_TIME_CFG :: reserved_for_padding0 [31:16] */
-#define BCHP_SWITCH_CORE_PDA_SETUP_TIME_CFG_reserved_for_padding0_MASK 0xffff0000
-#define BCHP_SWITCH_CORE_PDA_SETUP_TIME_CFG_reserved_for_padding0_SHIFT 16
-
-/* SWITCH_CORE :: PDA_SETUP_TIME_CFG :: SWITCH_RESV [15:11] */
-#define BCHP_SWITCH_CORE_PDA_SETUP_TIME_CFG_SWITCH_RESV_MASK 0x0000f800
-#define BCHP_SWITCH_CORE_PDA_SETUP_TIME_CFG_SWITCH_RESV_SHIFT 11
-#define BCHP_SWITCH_CORE_PDA_SETUP_TIME_CFG_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: PDA_SETUP_TIME_CFG :: SETUP_TIME [10:00] */
-#define BCHP_SWITCH_CORE_PDA_SETUP_TIME_CFG_SETUP_TIME_MASK 0x000007ff
-#define BCHP_SWITCH_CORE_PDA_SETUP_TIME_CFG_SETUP_TIME_SHIFT 0
-#define BCHP_SWITCH_CORE_PDA_SETUP_TIME_CFG_SETUP_TIME_DEFAULT 0x00000001
-
-/***************************************************************************
- *PDA_HOLD_TIME_CFG - BPM PDA Switching Hold Time RegisterNot2Release
- ***************************************************************************/
-/* SWITCH_CORE :: PDA_HOLD_TIME_CFG :: reserved_for_padding0 [31:16] */
-#define BCHP_SWITCH_CORE_PDA_HOLD_TIME_CFG_reserved_for_padding0_MASK 0xffff0000
-#define BCHP_SWITCH_CORE_PDA_HOLD_TIME_CFG_reserved_for_padding0_SHIFT 16
-
-/* SWITCH_CORE :: PDA_HOLD_TIME_CFG :: SWITCH_RESV [15:11] */
-#define BCHP_SWITCH_CORE_PDA_HOLD_TIME_CFG_SWITCH_RESV_MASK 0x0000f800
-#define BCHP_SWITCH_CORE_PDA_HOLD_TIME_CFG_SWITCH_RESV_SHIFT 11
-#define BCHP_SWITCH_CORE_PDA_HOLD_TIME_CFG_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: PDA_HOLD_TIME_CFG :: HOLD_TIME [10:00] */
-#define BCHP_SWITCH_CORE_PDA_HOLD_TIME_CFG_HOLD_TIME_MASK 0x000007ff
-#define BCHP_SWITCH_CORE_PDA_HOLD_TIME_CFG_HOLD_TIME_SHIFT 0
-#define BCHP_SWITCH_CORE_PDA_HOLD_TIME_CFG_HOLD_TIME_DEFAULT 0x00000001
-
-/***************************************************************************
- *PBB_VBUFCNT_N_Port_0 - Packet Buffer Block N Valid Buffer Count RegisterNot2Release
- ***************************************************************************/
-/* SWITCH_CORE :: PBB_VBUFCNT_N_Port_0 :: reserved_for_padding0 [31:16] */
-#define BCHP_SWITCH_CORE_PBB_VBUFCNT_N_Port_0_reserved_for_padding0_MASK 0xffff0000
-#define BCHP_SWITCH_CORE_PBB_VBUFCNT_N_Port_0_reserved_for_padding0_SHIFT 16
-
-/* SWITCH_CORE :: PBB_VBUFCNT_N_Port_0 :: SWITCH_RESV [15:10] */
-#define BCHP_SWITCH_CORE_PBB_VBUFCNT_N_Port_0_SWITCH_RESV_MASK 0x0000fc00
-#define BCHP_SWITCH_CORE_PBB_VBUFCNT_N_Port_0_SWITCH_RESV_SHIFT 10
-#define BCHP_SWITCH_CORE_PBB_VBUFCNT_N_Port_0_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: PBB_VBUFCNT_N_Port_0 :: VALID_BUF_CNT [09:00] */
-#define BCHP_SWITCH_CORE_PBB_VBUFCNT_N_Port_0_VALID_BUF_CNT_MASK 0x000003ff
-#define BCHP_SWITCH_CORE_PBB_VBUFCNT_N_Port_0_VALID_BUF_CNT_SHIFT 0
-#define BCHP_SWITCH_CORE_PBB_VBUFCNT_N_Port_0_VALID_BUF_CNT_DEFAULT 0x00000200
-
-/***************************************************************************
- *PBB_VBUFCNT_N_Port_1 - Packet Buffer Block N Valid Buffer Count RegisterNot2Release
- ***************************************************************************/
-/* SWITCH_CORE :: PBB_VBUFCNT_N_Port_1 :: reserved_for_padding0 [31:16] */
-#define BCHP_SWITCH_CORE_PBB_VBUFCNT_N_Port_1_reserved_for_padding0_MASK 0xffff0000
-#define BCHP_SWITCH_CORE_PBB_VBUFCNT_N_Port_1_reserved_for_padding0_SHIFT 16
-
-/* SWITCH_CORE :: PBB_VBUFCNT_N_Port_1 :: SWITCH_RESV [15:10] */
-#define BCHP_SWITCH_CORE_PBB_VBUFCNT_N_Port_1_SWITCH_RESV_MASK 0x0000fc00
-#define BCHP_SWITCH_CORE_PBB_VBUFCNT_N_Port_1_SWITCH_RESV_SHIFT 10
-#define BCHP_SWITCH_CORE_PBB_VBUFCNT_N_Port_1_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: PBB_VBUFCNT_N_Port_1 :: VALID_BUF_CNT [09:00] */
-#define BCHP_SWITCH_CORE_PBB_VBUFCNT_N_Port_1_VALID_BUF_CNT_MASK 0x000003ff
-#define BCHP_SWITCH_CORE_PBB_VBUFCNT_N_Port_1_VALID_BUF_CNT_SHIFT 0
-#define BCHP_SWITCH_CORE_PBB_VBUFCNT_N_Port_1_VALID_BUF_CNT_DEFAULT 0x00000200
-
-/***************************************************************************
- *PBB_VBUFCNT_N_Port_2 - Packet Buffer Block N Valid Buffer Count RegisterNot2Release
- ***************************************************************************/
-/* SWITCH_CORE :: PBB_VBUFCNT_N_Port_2 :: reserved_for_padding0 [31:16] */
-#define BCHP_SWITCH_CORE_PBB_VBUFCNT_N_Port_2_reserved_for_padding0_MASK 0xffff0000
-#define BCHP_SWITCH_CORE_PBB_VBUFCNT_N_Port_2_reserved_for_padding0_SHIFT 16
-
-/* SWITCH_CORE :: PBB_VBUFCNT_N_Port_2 :: SWITCH_RESV [15:10] */
-#define BCHP_SWITCH_CORE_PBB_VBUFCNT_N_Port_2_SWITCH_RESV_MASK 0x0000fc00
-#define BCHP_SWITCH_CORE_PBB_VBUFCNT_N_Port_2_SWITCH_RESV_SHIFT 10
-#define BCHP_SWITCH_CORE_PBB_VBUFCNT_N_Port_2_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: PBB_VBUFCNT_N_Port_2 :: VALID_BUF_CNT [09:00] */
-#define BCHP_SWITCH_CORE_PBB_VBUFCNT_N_Port_2_VALID_BUF_CNT_MASK 0x000003ff
-#define BCHP_SWITCH_CORE_PBB_VBUFCNT_N_Port_2_VALID_BUF_CNT_SHIFT 0
-#define BCHP_SWITCH_CORE_PBB_VBUFCNT_N_Port_2_VALID_BUF_CNT_DEFAULT 0x00000200
-
-/***************************************************************************
- *RCY_TIME_CFG - Recycling Check Pulse Period Counter RegisterNot2Release
- ***************************************************************************/
-/* SWITCH_CORE :: RCY_TIME_CFG :: reserved_for_padding0 [31:16] */
-#define BCHP_SWITCH_CORE_RCY_TIME_CFG_reserved_for_padding0_MASK 0xffff0000
-#define BCHP_SWITCH_CORE_RCY_TIME_CFG_reserved_for_padding0_SHIFT 16
-
-/* SWITCH_CORE :: RCY_TIME_CFG :: CHK_TIME [15:00] */
-#define BCHP_SWITCH_CORE_RCY_TIME_CFG_CHK_TIME_MASK 0x0000ffff
-#define BCHP_SWITCH_CORE_RCY_TIME_CFG_CHK_TIME_SHIFT 0
-#define BCHP_SWITCH_CORE_RCY_TIME_CFG_CHK_TIME_DEFAULT 0x00000020
-
-/***************************************************************************
- *PBB_PWRDWN_MON_CTRL - PBB Powerdown Monitor Control RegisterNot2Release
- ***************************************************************************/
-/* SWITCH_CORE :: PBB_PWRDWN_MON_CTRL :: reserved_for_padding0 [31:16] */
-#define BCHP_SWITCH_CORE_PBB_PWRDWN_MON_CTRL_reserved_for_padding0_MASK 0xffff0000
-#define BCHP_SWITCH_CORE_PBB_PWRDWN_MON_CTRL_reserved_for_padding0_SHIFT 16
-
-/* SWITCH_CORE :: PBB_PWRDWN_MON_CTRL :: MON_PERIOD [15:08] */
-#define BCHP_SWITCH_CORE_PBB_PWRDWN_MON_CTRL_MON_PERIOD_MASK 0x0000ff00
-#define BCHP_SWITCH_CORE_PBB_PWRDWN_MON_CTRL_MON_PERIOD_SHIFT 8
-#define BCHP_SWITCH_CORE_PBB_PWRDWN_MON_CTRL_MON_PERIOD_DEFAULT 0x00000001
-
-/* SWITCH_CORE :: PBB_PWRDWN_MON_CTRL :: MON_TIME_UNIT [07:03] */
-#define BCHP_SWITCH_CORE_PBB_PWRDWN_MON_CTRL_MON_TIME_UNIT_MASK 0x000000f8
-#define BCHP_SWITCH_CORE_PBB_PWRDWN_MON_CTRL_MON_TIME_UNIT_SHIFT 3
-#define BCHP_SWITCH_CORE_PBB_PWRDWN_MON_CTRL_MON_TIME_UNIT_DEFAULT 0x00000001
-
-/* SWITCH_CORE :: PBB_PWRDWN_MON_CTRL :: MON_DONE [02:02] */
-#define BCHP_SWITCH_CORE_PBB_PWRDWN_MON_CTRL_MON_DONE_MASK 0x00000004
-#define BCHP_SWITCH_CORE_PBB_PWRDWN_MON_CTRL_MON_DONE_SHIFT 2
-#define BCHP_SWITCH_CORE_PBB_PWRDWN_MON_CTRL_MON_DONE_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: PBB_PWRDWN_MON_CTRL :: MON_CLR [01:01] */
-#define BCHP_SWITCH_CORE_PBB_PWRDWN_MON_CTRL_MON_CLR_MASK 0x00000002
-#define BCHP_SWITCH_CORE_PBB_PWRDWN_MON_CTRL_MON_CLR_SHIFT 1
-#define BCHP_SWITCH_CORE_PBB_PWRDWN_MON_CTRL_MON_CLR_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: PBB_PWRDWN_MON_CTRL :: MON_EN [00:00] */
-#define BCHP_SWITCH_CORE_PBB_PWRDWN_MON_CTRL_MON_EN_MASK 0x00000001
-#define BCHP_SWITCH_CORE_PBB_PWRDWN_MON_CTRL_MON_EN_SHIFT 0
-#define BCHP_SWITCH_CORE_PBB_PWRDWN_MON_CTRL_MON_EN_DEFAULT 0x00000000
-
-/***************************************************************************
- *PBB_PWRDWN_MON_N_Port_0 - PBB Powerdown Time Monitor N RegisterNot2Release
- ***************************************************************************/
-/* SWITCH_CORE :: PBB_PWRDWN_MON_N_Port_0 :: PWRDWN_CNT [63:00] */
-#define BCHP_SWITCH_CORE_PBB_PWRDWN_MON_N_Port_0_PWRDWN_CNT_MASK 0x00000000ffffffff
-#define BCHP_SWITCH_CORE_PBB_PWRDWN_MON_N_Port_0_PWRDWN_CNT_SHIFT 0
-#define BCHP_SWITCH_CORE_PBB_PWRDWN_MON_N_Port_0_PWRDWN_CNT_DEFAULT 0x0000000000000000
-
-/***************************************************************************
- *PBB_PWRDWN_MON_N_Port_1 - PBB Powerdown Time Monitor N RegisterNot2Release
- ***************************************************************************/
-/* SWITCH_CORE :: PBB_PWRDWN_MON_N_Port_1 :: PWRDWN_CNT [63:00] */
-#define BCHP_SWITCH_CORE_PBB_PWRDWN_MON_N_Port_1_PWRDWN_CNT_MASK 0x00000000ffffffff
-#define BCHP_SWITCH_CORE_PBB_PWRDWN_MON_N_Port_1_PWRDWN_CNT_SHIFT 0
-#define BCHP_SWITCH_CORE_PBB_PWRDWN_MON_N_Port_1_PWRDWN_CNT_DEFAULT 0x0000000000000000
-
-/***************************************************************************
- *PBB_PWRDWN_MON_N_Port_2 - PBB Powerdown Time Monitor N RegisterNot2Release
- ***************************************************************************/
-/* SWITCH_CORE :: PBB_PWRDWN_MON_N_Port_2 :: PWRDWN_CNT [63:00] */
-#define BCHP_SWITCH_CORE_PBB_PWRDWN_MON_N_Port_2_PWRDWN_CNT_MASK 0x00000000ffffffff
-#define BCHP_SWITCH_CORE_PBB_PWRDWN_MON_N_Port_2_PWRDWN_CNT_SHIFT 0
-#define BCHP_SWITCH_CORE_PBB_PWRDWN_MON_N_Port_2_PWRDWN_CNT_DEFAULT 0x0000000000000000
-
-/***************************************************************************
- *BPM_REG_SPARE0 - Spare 0 Register (Not2Release)Not2Release
- ***************************************************************************/
-/* SWITCH_CORE :: BPM_REG_SPARE0 :: BPM_REG_SPARE0 [31:00] */
-#define BCHP_SWITCH_CORE_BPM_REG_SPARE0_BPM_REG_SPARE0_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_BPM_REG_SPARE0_BPM_REG_SPARE0_SHIFT 0
-#define BCHP_SWITCH_CORE_BPM_REG_SPARE0_BPM_REG_SPARE0_DEFAULT 0x00000000
-
-/***************************************************************************
- *BPM_REG_SPARE1 - Spare 1 Register (Not2Release)Not2Release
- ***************************************************************************/
-/* SWITCH_CORE :: BPM_REG_SPARE1 :: BPM_REG_SPARE1 [31:00] */
-#define BCHP_SWITCH_CORE_BPM_REG_SPARE1_BPM_REG_SPARE1_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_BPM_REG_SPARE1_BPM_REG_SPARE1_SHIFT 0
-#define BCHP_SWITCH_CORE_BPM_REG_SPARE1_BPM_REG_SPARE1_DEFAULT 0x00000000
-
-/***************************************************************************
- *TRREG_CTRL0 - Traffic Remarking Control 0 Register
- ***************************************************************************/
-/* SWITCH_CORE :: TRREG_CTRL0 :: SWITCH_RESV_1 [31:25] */
-#define BCHP_SWITCH_CORE_TRREG_CTRL0_SWITCH_RESV_1_MASK 0xfe000000
-#define BCHP_SWITCH_CORE_TRREG_CTRL0_SWITCH_RESV_1_SHIFT 25
-#define BCHP_SWITCH_CORE_TRREG_CTRL0_SWITCH_RESV_1_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: TRREG_CTRL0 :: PCP_RMK_EN [24:16] */
-#define BCHP_SWITCH_CORE_TRREG_CTRL0_PCP_RMK_EN_MASK 0x01ff0000
-#define BCHP_SWITCH_CORE_TRREG_CTRL0_PCP_RMK_EN_SHIFT 16
-#define BCHP_SWITCH_CORE_TRREG_CTRL0_PCP_RMK_EN_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: TRREG_CTRL0 :: SWITCH_RESV_0 [15:09] */
-#define BCHP_SWITCH_CORE_TRREG_CTRL0_SWITCH_RESV_0_MASK 0x0000fe00
-#define BCHP_SWITCH_CORE_TRREG_CTRL0_SWITCH_RESV_0_SHIFT 9
-#define BCHP_SWITCH_CORE_TRREG_CTRL0_SWITCH_RESV_0_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: TRREG_CTRL0 :: CFI_RMK_EN [08:00] */
-#define BCHP_SWITCH_CORE_TRREG_CTRL0_CFI_RMK_EN_MASK 0x000001ff
-#define BCHP_SWITCH_CORE_TRREG_CTRL0_CFI_RMK_EN_SHIFT 0
-#define BCHP_SWITCH_CORE_TRREG_CTRL0_CFI_RMK_EN_DEFAULT 0x00000000
-
-/***************************************************************************
- *TRREG_CTRL1 - Traffic Remarking Control 1 Register
- ***************************************************************************/
-/* SWITCH_CORE :: TRREG_CTRL1 :: SWITCH_RESV_1 [31:25] */
-#define BCHP_SWITCH_CORE_TRREG_CTRL1_SWITCH_RESV_1_MASK 0xfe000000
-#define BCHP_SWITCH_CORE_TRREG_CTRL1_SWITCH_RESV_1_SHIFT 25
-#define BCHP_SWITCH_CORE_TRREG_CTRL1_SWITCH_RESV_1_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: TRREG_CTRL1 :: DEI_RMK_EN [24:16] */
-#define BCHP_SWITCH_CORE_TRREG_CTRL1_DEI_RMK_EN_MASK 0x01ff0000
-#define BCHP_SWITCH_CORE_TRREG_CTRL1_DEI_RMK_EN_SHIFT 16
-#define BCHP_SWITCH_CORE_TRREG_CTRL1_DEI_RMK_EN_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: TRREG_CTRL1 :: PPPOE_DSCP_RMK_EN [15:15] */
-#define BCHP_SWITCH_CORE_TRREG_CTRL1_PPPOE_DSCP_RMK_EN_MASK 0x00008000
-#define BCHP_SWITCH_CORE_TRREG_CTRL1_PPPOE_DSCP_RMK_EN_SHIFT 15
-#define BCHP_SWITCH_CORE_TRREG_CTRL1_PPPOE_DSCP_RMK_EN_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: TRREG_CTRL1 :: SWITCH_RESV_0 [14:09] */
-#define BCHP_SWITCH_CORE_TRREG_CTRL1_SWITCH_RESV_0_MASK 0x00007e00
-#define BCHP_SWITCH_CORE_TRREG_CTRL1_SWITCH_RESV_0_SHIFT 9
-#define BCHP_SWITCH_CORE_TRREG_CTRL1_SWITCH_RESV_0_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: TRREG_CTRL1 :: DSCP_RMK_EN [08:00] */
-#define BCHP_SWITCH_CORE_TRREG_CTRL1_DSCP_RMK_EN_MASK 0x000001ff
-#define BCHP_SWITCH_CORE_TRREG_CTRL1_DSCP_RMK_EN_SHIFT 0
-#define BCHP_SWITCH_CORE_TRREG_CTRL1_DSCP_RMK_EN_DEFAULT 0x000001ff
-
-/***************************************************************************
- *TRREG_CTRL2 - Traffic Remarking Control 2 Register
- ***************************************************************************/
-/* SWITCH_CORE :: TRREG_CTRL2 :: SWITCH_RESV_1 [31:25] */
-#define BCHP_SWITCH_CORE_TRREG_CTRL2_SWITCH_RESV_1_MASK 0xfe000000
-#define BCHP_SWITCH_CORE_TRREG_CTRL2_SWITCH_RESV_1_SHIFT 25
-#define BCHP_SWITCH_CORE_TRREG_CTRL2_SWITCH_RESV_1_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: TRREG_CTRL2 :: C_PCP_RMK_EN [24:16] */
-#define BCHP_SWITCH_CORE_TRREG_CTRL2_C_PCP_RMK_EN_MASK 0x01ff0000
-#define BCHP_SWITCH_CORE_TRREG_CTRL2_C_PCP_RMK_EN_SHIFT 16
-#define BCHP_SWITCH_CORE_TRREG_CTRL2_C_PCP_RMK_EN_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: TRREG_CTRL2 :: SWITCH_RESV_0 [15:09] */
-#define BCHP_SWITCH_CORE_TRREG_CTRL2_SWITCH_RESV_0_MASK 0x0000fe00
-#define BCHP_SWITCH_CORE_TRREG_CTRL2_SWITCH_RESV_0_SHIFT 9
-#define BCHP_SWITCH_CORE_TRREG_CTRL2_SWITCH_RESV_0_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: TRREG_CTRL2 :: S_PCP_RMK_EN [08:00] */
-#define BCHP_SWITCH_CORE_TRREG_CTRL2_S_PCP_RMK_EN_MASK 0x000001ff
-#define BCHP_SWITCH_CORE_TRREG_CTRL2_S_PCP_RMK_EN_SHIFT 0
-#define BCHP_SWITCH_CORE_TRREG_CTRL2_S_PCP_RMK_EN_DEFAULT 0x00000000
-
-/***************************************************************************
- *PN_EGRESS_PKT_TC2PCP_MAP_Port_0 - Port N, Egress TC to PCP mapping Register
- ***************************************************************************/
-/* SWITCH_CORE :: PN_EGRESS_PKT_TC2PCP_MAP_Port_0 :: PCP_FOR_RV1_TC7 [63:60] */
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2PCP_MAP_Port_0_PCP_FOR_RV1_TC7_MASK 0x00000000f0000000
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2PCP_MAP_Port_0_PCP_FOR_RV1_TC7_SHIFT 60
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2PCP_MAP_Port_0_PCP_FOR_RV1_TC7_DEFAULT 0x000000000000000f
-
-/* SWITCH_CORE :: PN_EGRESS_PKT_TC2PCP_MAP_Port_0 :: PCP_FOR_RV1_TC6 [59:56] */
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2PCP_MAP_Port_0_PCP_FOR_RV1_TC6_MASK 0x000000000f000000
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2PCP_MAP_Port_0_PCP_FOR_RV1_TC6_SHIFT 56
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2PCP_MAP_Port_0_PCP_FOR_RV1_TC6_DEFAULT 0x000000000000000e
-
-/* SWITCH_CORE :: PN_EGRESS_PKT_TC2PCP_MAP_Port_0 :: PCP_FOR_RV1_TC5 [55:52] */
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2PCP_MAP_Port_0_PCP_FOR_RV1_TC5_MASK 0x0000000000f00000
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2PCP_MAP_Port_0_PCP_FOR_RV1_TC5_SHIFT 52
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2PCP_MAP_Port_0_PCP_FOR_RV1_TC5_DEFAULT 0x000000000000000d
-
-/* SWITCH_CORE :: PN_EGRESS_PKT_TC2PCP_MAP_Port_0 :: PCP_FOR_RV1_TC4 [51:48] */
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2PCP_MAP_Port_0_PCP_FOR_RV1_TC4_MASK 0x00000000000f0000
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2PCP_MAP_Port_0_PCP_FOR_RV1_TC4_SHIFT 48
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2PCP_MAP_Port_0_PCP_FOR_RV1_TC4_DEFAULT 0x000000000000000c
-
-/* SWITCH_CORE :: PN_EGRESS_PKT_TC2PCP_MAP_Port_0 :: PCP_FOR_RV1_TC3 [47:44] */
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2PCP_MAP_Port_0_PCP_FOR_RV1_TC3_MASK 0x000000000000f000
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2PCP_MAP_Port_0_PCP_FOR_RV1_TC3_SHIFT 44
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2PCP_MAP_Port_0_PCP_FOR_RV1_TC3_DEFAULT 0x000000000000000b
-
-/* SWITCH_CORE :: PN_EGRESS_PKT_TC2PCP_MAP_Port_0 :: PCP_FOR_RV1_TC2 [43:40] */
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2PCP_MAP_Port_0_PCP_FOR_RV1_TC2_MASK 0x0000000000000f00
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2PCP_MAP_Port_0_PCP_FOR_RV1_TC2_SHIFT 40
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2PCP_MAP_Port_0_PCP_FOR_RV1_TC2_DEFAULT 0x000000000000000a
-
-/* SWITCH_CORE :: PN_EGRESS_PKT_TC2PCP_MAP_Port_0 :: PCP_FOR_RV1_TC1 [39:36] */
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2PCP_MAP_Port_0_PCP_FOR_RV1_TC1_MASK 0x00000000000000f0
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2PCP_MAP_Port_0_PCP_FOR_RV1_TC1_SHIFT 36
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2PCP_MAP_Port_0_PCP_FOR_RV1_TC1_DEFAULT 0x0000000000000009
-
-/* SWITCH_CORE :: PN_EGRESS_PKT_TC2PCP_MAP_Port_0 :: PCP_FOR_RV1_TC0 [35:32] */
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2PCP_MAP_Port_0_PCP_FOR_RV1_TC0_MASK 0x000000000000000f
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2PCP_MAP_Port_0_PCP_FOR_RV1_TC0_SHIFT 32
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2PCP_MAP_Port_0_PCP_FOR_RV1_TC0_DEFAULT 0x0000000000000008
-
-/* SWITCH_CORE :: PN_EGRESS_PKT_TC2PCP_MAP_Port_0 :: PCP_FOR_RV0_TC7 [31:28] */
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2PCP_MAP_Port_0_PCP_FOR_RV0_TC7_MASK 0x00000000f0000000
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2PCP_MAP_Port_0_PCP_FOR_RV0_TC7_SHIFT 28
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2PCP_MAP_Port_0_PCP_FOR_RV0_TC7_DEFAULT 0x0000000000000007
-
-/* SWITCH_CORE :: PN_EGRESS_PKT_TC2PCP_MAP_Port_0 :: PCP_FOR_RV0_TC6 [27:24] */
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2PCP_MAP_Port_0_PCP_FOR_RV0_TC6_MASK 0x000000000f000000
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2PCP_MAP_Port_0_PCP_FOR_RV0_TC6_SHIFT 24
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2PCP_MAP_Port_0_PCP_FOR_RV0_TC6_DEFAULT 0x0000000000000006
-
-/* SWITCH_CORE :: PN_EGRESS_PKT_TC2PCP_MAP_Port_0 :: PCP_FOR_RV0_TC5 [23:20] */
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2PCP_MAP_Port_0_PCP_FOR_RV0_TC5_MASK 0x0000000000f00000
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2PCP_MAP_Port_0_PCP_FOR_RV0_TC5_SHIFT 20
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2PCP_MAP_Port_0_PCP_FOR_RV0_TC5_DEFAULT 0x0000000000000005
-
-/* SWITCH_CORE :: PN_EGRESS_PKT_TC2PCP_MAP_Port_0 :: PCP_FOR_RV0_TC4 [19:16] */
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2PCP_MAP_Port_0_PCP_FOR_RV0_TC4_MASK 0x00000000000f0000
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2PCP_MAP_Port_0_PCP_FOR_RV0_TC4_SHIFT 16
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2PCP_MAP_Port_0_PCP_FOR_RV0_TC4_DEFAULT 0x0000000000000004
-
-/* SWITCH_CORE :: PN_EGRESS_PKT_TC2PCP_MAP_Port_0 :: PCP_FOR_RV0_TC3 [15:12] */
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2PCP_MAP_Port_0_PCP_FOR_RV0_TC3_MASK 0x000000000000f000
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2PCP_MAP_Port_0_PCP_FOR_RV0_TC3_SHIFT 12
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2PCP_MAP_Port_0_PCP_FOR_RV0_TC3_DEFAULT 0x0000000000000003
-
-/* SWITCH_CORE :: PN_EGRESS_PKT_TC2PCP_MAP_Port_0 :: PCP_FOR_RV0_TC2 [11:08] */
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2PCP_MAP_Port_0_PCP_FOR_RV0_TC2_MASK 0x0000000000000f00
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2PCP_MAP_Port_0_PCP_FOR_RV0_TC2_SHIFT 8
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2PCP_MAP_Port_0_PCP_FOR_RV0_TC2_DEFAULT 0x0000000000000002
-
-/* SWITCH_CORE :: PN_EGRESS_PKT_TC2PCP_MAP_Port_0 :: PCP_FOR_RV0_TC1 [07:04] */
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2PCP_MAP_Port_0_PCP_FOR_RV0_TC1_MASK 0x00000000000000f0
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2PCP_MAP_Port_0_PCP_FOR_RV0_TC1_SHIFT 4
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2PCP_MAP_Port_0_PCP_FOR_RV0_TC1_DEFAULT 0x0000000000000001
-
-/* SWITCH_CORE :: PN_EGRESS_PKT_TC2PCP_MAP_Port_0 :: PCP_FOR_RV0_TC0 [03:00] */
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2PCP_MAP_Port_0_PCP_FOR_RV0_TC0_MASK 0x000000000000000f
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2PCP_MAP_Port_0_PCP_FOR_RV0_TC0_SHIFT 0
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2PCP_MAP_Port_0_PCP_FOR_RV0_TC0_DEFAULT 0x0000000000000000
-
-/***************************************************************************
- *PN_EGRESS_PKT_TC2PCP_MAP_Port_1 - Port N, Egress TC to PCP mapping Register
- ***************************************************************************/
-/* SWITCH_CORE :: PN_EGRESS_PKT_TC2PCP_MAP_Port_1 :: PCP_FOR_RV1_TC7 [63:60] */
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2PCP_MAP_Port_1_PCP_FOR_RV1_TC7_MASK 0x00000000f0000000
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2PCP_MAP_Port_1_PCP_FOR_RV1_TC7_SHIFT 60
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2PCP_MAP_Port_1_PCP_FOR_RV1_TC7_DEFAULT 0x000000000000000f
-
-/* SWITCH_CORE :: PN_EGRESS_PKT_TC2PCP_MAP_Port_1 :: PCP_FOR_RV1_TC6 [59:56] */
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2PCP_MAP_Port_1_PCP_FOR_RV1_TC6_MASK 0x000000000f000000
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2PCP_MAP_Port_1_PCP_FOR_RV1_TC6_SHIFT 56
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2PCP_MAP_Port_1_PCP_FOR_RV1_TC6_DEFAULT 0x000000000000000e
-
-/* SWITCH_CORE :: PN_EGRESS_PKT_TC2PCP_MAP_Port_1 :: PCP_FOR_RV1_TC5 [55:52] */
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2PCP_MAP_Port_1_PCP_FOR_RV1_TC5_MASK 0x0000000000f00000
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2PCP_MAP_Port_1_PCP_FOR_RV1_TC5_SHIFT 52
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2PCP_MAP_Port_1_PCP_FOR_RV1_TC5_DEFAULT 0x000000000000000d
-
-/* SWITCH_CORE :: PN_EGRESS_PKT_TC2PCP_MAP_Port_1 :: PCP_FOR_RV1_TC4 [51:48] */
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2PCP_MAP_Port_1_PCP_FOR_RV1_TC4_MASK 0x00000000000f0000
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2PCP_MAP_Port_1_PCP_FOR_RV1_TC4_SHIFT 48
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2PCP_MAP_Port_1_PCP_FOR_RV1_TC4_DEFAULT 0x000000000000000c
-
-/* SWITCH_CORE :: PN_EGRESS_PKT_TC2PCP_MAP_Port_1 :: PCP_FOR_RV1_TC3 [47:44] */
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2PCP_MAP_Port_1_PCP_FOR_RV1_TC3_MASK 0x000000000000f000
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2PCP_MAP_Port_1_PCP_FOR_RV1_TC3_SHIFT 44
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2PCP_MAP_Port_1_PCP_FOR_RV1_TC3_DEFAULT 0x000000000000000b
-
-/* SWITCH_CORE :: PN_EGRESS_PKT_TC2PCP_MAP_Port_1 :: PCP_FOR_RV1_TC2 [43:40] */
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2PCP_MAP_Port_1_PCP_FOR_RV1_TC2_MASK 0x0000000000000f00
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2PCP_MAP_Port_1_PCP_FOR_RV1_TC2_SHIFT 40
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2PCP_MAP_Port_1_PCP_FOR_RV1_TC2_DEFAULT 0x000000000000000a
-
-/* SWITCH_CORE :: PN_EGRESS_PKT_TC2PCP_MAP_Port_1 :: PCP_FOR_RV1_TC1 [39:36] */
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2PCP_MAP_Port_1_PCP_FOR_RV1_TC1_MASK 0x00000000000000f0
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2PCP_MAP_Port_1_PCP_FOR_RV1_TC1_SHIFT 36
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2PCP_MAP_Port_1_PCP_FOR_RV1_TC1_DEFAULT 0x0000000000000009
-
-/* SWITCH_CORE :: PN_EGRESS_PKT_TC2PCP_MAP_Port_1 :: PCP_FOR_RV1_TC0 [35:32] */
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2PCP_MAP_Port_1_PCP_FOR_RV1_TC0_MASK 0x000000000000000f
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2PCP_MAP_Port_1_PCP_FOR_RV1_TC0_SHIFT 32
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2PCP_MAP_Port_1_PCP_FOR_RV1_TC0_DEFAULT 0x0000000000000008
-
-/* SWITCH_CORE :: PN_EGRESS_PKT_TC2PCP_MAP_Port_1 :: PCP_FOR_RV0_TC7 [31:28] */
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2PCP_MAP_Port_1_PCP_FOR_RV0_TC7_MASK 0x00000000f0000000
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2PCP_MAP_Port_1_PCP_FOR_RV0_TC7_SHIFT 28
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2PCP_MAP_Port_1_PCP_FOR_RV0_TC7_DEFAULT 0x0000000000000007
-
-/* SWITCH_CORE :: PN_EGRESS_PKT_TC2PCP_MAP_Port_1 :: PCP_FOR_RV0_TC6 [27:24] */
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2PCP_MAP_Port_1_PCP_FOR_RV0_TC6_MASK 0x000000000f000000
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2PCP_MAP_Port_1_PCP_FOR_RV0_TC6_SHIFT 24
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2PCP_MAP_Port_1_PCP_FOR_RV0_TC6_DEFAULT 0x0000000000000006
-
-/* SWITCH_CORE :: PN_EGRESS_PKT_TC2PCP_MAP_Port_1 :: PCP_FOR_RV0_TC5 [23:20] */
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2PCP_MAP_Port_1_PCP_FOR_RV0_TC5_MASK 0x0000000000f00000
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2PCP_MAP_Port_1_PCP_FOR_RV0_TC5_SHIFT 20
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2PCP_MAP_Port_1_PCP_FOR_RV0_TC5_DEFAULT 0x0000000000000005
-
-/* SWITCH_CORE :: PN_EGRESS_PKT_TC2PCP_MAP_Port_1 :: PCP_FOR_RV0_TC4 [19:16] */
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2PCP_MAP_Port_1_PCP_FOR_RV0_TC4_MASK 0x00000000000f0000
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2PCP_MAP_Port_1_PCP_FOR_RV0_TC4_SHIFT 16
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2PCP_MAP_Port_1_PCP_FOR_RV0_TC4_DEFAULT 0x0000000000000004
-
-/* SWITCH_CORE :: PN_EGRESS_PKT_TC2PCP_MAP_Port_1 :: PCP_FOR_RV0_TC3 [15:12] */
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2PCP_MAP_Port_1_PCP_FOR_RV0_TC3_MASK 0x000000000000f000
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2PCP_MAP_Port_1_PCP_FOR_RV0_TC3_SHIFT 12
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2PCP_MAP_Port_1_PCP_FOR_RV0_TC3_DEFAULT 0x0000000000000003
-
-/* SWITCH_CORE :: PN_EGRESS_PKT_TC2PCP_MAP_Port_1 :: PCP_FOR_RV0_TC2 [11:08] */
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2PCP_MAP_Port_1_PCP_FOR_RV0_TC2_MASK 0x0000000000000f00
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2PCP_MAP_Port_1_PCP_FOR_RV0_TC2_SHIFT 8
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2PCP_MAP_Port_1_PCP_FOR_RV0_TC2_DEFAULT 0x0000000000000002
-
-/* SWITCH_CORE :: PN_EGRESS_PKT_TC2PCP_MAP_Port_1 :: PCP_FOR_RV0_TC1 [07:04] */
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2PCP_MAP_Port_1_PCP_FOR_RV0_TC1_MASK 0x00000000000000f0
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2PCP_MAP_Port_1_PCP_FOR_RV0_TC1_SHIFT 4
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2PCP_MAP_Port_1_PCP_FOR_RV0_TC1_DEFAULT 0x0000000000000001
-
-/* SWITCH_CORE :: PN_EGRESS_PKT_TC2PCP_MAP_Port_1 :: PCP_FOR_RV0_TC0 [03:00] */
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2PCP_MAP_Port_1_PCP_FOR_RV0_TC0_MASK 0x000000000000000f
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2PCP_MAP_Port_1_PCP_FOR_RV0_TC0_SHIFT 0
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2PCP_MAP_Port_1_PCP_FOR_RV0_TC0_DEFAULT 0x0000000000000000
-
-/***************************************************************************
- *PN_EGRESS_PKT_TC2PCP_MAP_Port_2 - Port N, Egress TC to PCP mapping Register
- ***************************************************************************/
-/* SWITCH_CORE :: PN_EGRESS_PKT_TC2PCP_MAP_Port_2 :: PCP_FOR_RV1_TC7 [63:60] */
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2PCP_MAP_Port_2_PCP_FOR_RV1_TC7_MASK 0x00000000f0000000
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2PCP_MAP_Port_2_PCP_FOR_RV1_TC7_SHIFT 60
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2PCP_MAP_Port_2_PCP_FOR_RV1_TC7_DEFAULT 0x000000000000000f
-
-/* SWITCH_CORE :: PN_EGRESS_PKT_TC2PCP_MAP_Port_2 :: PCP_FOR_RV1_TC6 [59:56] */
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2PCP_MAP_Port_2_PCP_FOR_RV1_TC6_MASK 0x000000000f000000
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2PCP_MAP_Port_2_PCP_FOR_RV1_TC6_SHIFT 56
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2PCP_MAP_Port_2_PCP_FOR_RV1_TC6_DEFAULT 0x000000000000000e
-
-/* SWITCH_CORE :: PN_EGRESS_PKT_TC2PCP_MAP_Port_2 :: PCP_FOR_RV1_TC5 [55:52] */
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2PCP_MAP_Port_2_PCP_FOR_RV1_TC5_MASK 0x0000000000f00000
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2PCP_MAP_Port_2_PCP_FOR_RV1_TC5_SHIFT 52
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2PCP_MAP_Port_2_PCP_FOR_RV1_TC5_DEFAULT 0x000000000000000d
-
-/* SWITCH_CORE :: PN_EGRESS_PKT_TC2PCP_MAP_Port_2 :: PCP_FOR_RV1_TC4 [51:48] */
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2PCP_MAP_Port_2_PCP_FOR_RV1_TC4_MASK 0x00000000000f0000
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2PCP_MAP_Port_2_PCP_FOR_RV1_TC4_SHIFT 48
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2PCP_MAP_Port_2_PCP_FOR_RV1_TC4_DEFAULT 0x000000000000000c
-
-/* SWITCH_CORE :: PN_EGRESS_PKT_TC2PCP_MAP_Port_2 :: PCP_FOR_RV1_TC3 [47:44] */
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2PCP_MAP_Port_2_PCP_FOR_RV1_TC3_MASK 0x000000000000f000
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2PCP_MAP_Port_2_PCP_FOR_RV1_TC3_SHIFT 44
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2PCP_MAP_Port_2_PCP_FOR_RV1_TC3_DEFAULT 0x000000000000000b
-
-/* SWITCH_CORE :: PN_EGRESS_PKT_TC2PCP_MAP_Port_2 :: PCP_FOR_RV1_TC2 [43:40] */
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2PCP_MAP_Port_2_PCP_FOR_RV1_TC2_MASK 0x0000000000000f00
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2PCP_MAP_Port_2_PCP_FOR_RV1_TC2_SHIFT 40
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2PCP_MAP_Port_2_PCP_FOR_RV1_TC2_DEFAULT 0x000000000000000a
-
-/* SWITCH_CORE :: PN_EGRESS_PKT_TC2PCP_MAP_Port_2 :: PCP_FOR_RV1_TC1 [39:36] */
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2PCP_MAP_Port_2_PCP_FOR_RV1_TC1_MASK 0x00000000000000f0
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2PCP_MAP_Port_2_PCP_FOR_RV1_TC1_SHIFT 36
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2PCP_MAP_Port_2_PCP_FOR_RV1_TC1_DEFAULT 0x0000000000000009
-
-/* SWITCH_CORE :: PN_EGRESS_PKT_TC2PCP_MAP_Port_2 :: PCP_FOR_RV1_TC0 [35:32] */
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2PCP_MAP_Port_2_PCP_FOR_RV1_TC0_MASK 0x000000000000000f
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2PCP_MAP_Port_2_PCP_FOR_RV1_TC0_SHIFT 32
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2PCP_MAP_Port_2_PCP_FOR_RV1_TC0_DEFAULT 0x0000000000000008
-
-/* SWITCH_CORE :: PN_EGRESS_PKT_TC2PCP_MAP_Port_2 :: PCP_FOR_RV0_TC7 [31:28] */
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2PCP_MAP_Port_2_PCP_FOR_RV0_TC7_MASK 0x00000000f0000000
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2PCP_MAP_Port_2_PCP_FOR_RV0_TC7_SHIFT 28
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2PCP_MAP_Port_2_PCP_FOR_RV0_TC7_DEFAULT 0x0000000000000007
-
-/* SWITCH_CORE :: PN_EGRESS_PKT_TC2PCP_MAP_Port_2 :: PCP_FOR_RV0_TC6 [27:24] */
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2PCP_MAP_Port_2_PCP_FOR_RV0_TC6_MASK 0x000000000f000000
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2PCP_MAP_Port_2_PCP_FOR_RV0_TC6_SHIFT 24
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2PCP_MAP_Port_2_PCP_FOR_RV0_TC6_DEFAULT 0x0000000000000006
-
-/* SWITCH_CORE :: PN_EGRESS_PKT_TC2PCP_MAP_Port_2 :: PCP_FOR_RV0_TC5 [23:20] */
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2PCP_MAP_Port_2_PCP_FOR_RV0_TC5_MASK 0x0000000000f00000
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2PCP_MAP_Port_2_PCP_FOR_RV0_TC5_SHIFT 20
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2PCP_MAP_Port_2_PCP_FOR_RV0_TC5_DEFAULT 0x0000000000000005
-
-/* SWITCH_CORE :: PN_EGRESS_PKT_TC2PCP_MAP_Port_2 :: PCP_FOR_RV0_TC4 [19:16] */
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2PCP_MAP_Port_2_PCP_FOR_RV0_TC4_MASK 0x00000000000f0000
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2PCP_MAP_Port_2_PCP_FOR_RV0_TC4_SHIFT 16
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2PCP_MAP_Port_2_PCP_FOR_RV0_TC4_DEFAULT 0x0000000000000004
-
-/* SWITCH_CORE :: PN_EGRESS_PKT_TC2PCP_MAP_Port_2 :: PCP_FOR_RV0_TC3 [15:12] */
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2PCP_MAP_Port_2_PCP_FOR_RV0_TC3_MASK 0x000000000000f000
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2PCP_MAP_Port_2_PCP_FOR_RV0_TC3_SHIFT 12
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2PCP_MAP_Port_2_PCP_FOR_RV0_TC3_DEFAULT 0x0000000000000003
-
-/* SWITCH_CORE :: PN_EGRESS_PKT_TC2PCP_MAP_Port_2 :: PCP_FOR_RV0_TC2 [11:08] */
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2PCP_MAP_Port_2_PCP_FOR_RV0_TC2_MASK 0x0000000000000f00
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2PCP_MAP_Port_2_PCP_FOR_RV0_TC2_SHIFT 8
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2PCP_MAP_Port_2_PCP_FOR_RV0_TC2_DEFAULT 0x0000000000000002
-
-/* SWITCH_CORE :: PN_EGRESS_PKT_TC2PCP_MAP_Port_2 :: PCP_FOR_RV0_TC1 [07:04] */
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2PCP_MAP_Port_2_PCP_FOR_RV0_TC1_MASK 0x00000000000000f0
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2PCP_MAP_Port_2_PCP_FOR_RV0_TC1_SHIFT 4
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2PCP_MAP_Port_2_PCP_FOR_RV0_TC1_DEFAULT 0x0000000000000001
-
-/* SWITCH_CORE :: PN_EGRESS_PKT_TC2PCP_MAP_Port_2 :: PCP_FOR_RV0_TC0 [03:00] */
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2PCP_MAP_Port_2_PCP_FOR_RV0_TC0_MASK 0x000000000000000f
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2PCP_MAP_Port_2_PCP_FOR_RV0_TC0_SHIFT 0
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2PCP_MAP_Port_2_PCP_FOR_RV0_TC0_DEFAULT 0x0000000000000000
-
-/***************************************************************************
- *PN_EGRESS_PKT_TC2PCP_MAP_Port_3 - Port N, Egress TC to PCP mapping Register
- ***************************************************************************/
-/* SWITCH_CORE :: PN_EGRESS_PKT_TC2PCP_MAP_Port_3 :: PCP_FOR_RV1_TC7 [63:60] */
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2PCP_MAP_Port_3_PCP_FOR_RV1_TC7_MASK 0x00000000f0000000
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2PCP_MAP_Port_3_PCP_FOR_RV1_TC7_SHIFT 60
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2PCP_MAP_Port_3_PCP_FOR_RV1_TC7_DEFAULT 0x000000000000000f
-
-/* SWITCH_CORE :: PN_EGRESS_PKT_TC2PCP_MAP_Port_3 :: PCP_FOR_RV1_TC6 [59:56] */
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2PCP_MAP_Port_3_PCP_FOR_RV1_TC6_MASK 0x000000000f000000
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2PCP_MAP_Port_3_PCP_FOR_RV1_TC6_SHIFT 56
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2PCP_MAP_Port_3_PCP_FOR_RV1_TC6_DEFAULT 0x000000000000000e
-
-/* SWITCH_CORE :: PN_EGRESS_PKT_TC2PCP_MAP_Port_3 :: PCP_FOR_RV1_TC5 [55:52] */
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2PCP_MAP_Port_3_PCP_FOR_RV1_TC5_MASK 0x0000000000f00000
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2PCP_MAP_Port_3_PCP_FOR_RV1_TC5_SHIFT 52
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2PCP_MAP_Port_3_PCP_FOR_RV1_TC5_DEFAULT 0x000000000000000d
-
-/* SWITCH_CORE :: PN_EGRESS_PKT_TC2PCP_MAP_Port_3 :: PCP_FOR_RV1_TC4 [51:48] */
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2PCP_MAP_Port_3_PCP_FOR_RV1_TC4_MASK 0x00000000000f0000
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2PCP_MAP_Port_3_PCP_FOR_RV1_TC4_SHIFT 48
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2PCP_MAP_Port_3_PCP_FOR_RV1_TC4_DEFAULT 0x000000000000000c
-
-/* SWITCH_CORE :: PN_EGRESS_PKT_TC2PCP_MAP_Port_3 :: PCP_FOR_RV1_TC3 [47:44] */
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2PCP_MAP_Port_3_PCP_FOR_RV1_TC3_MASK 0x000000000000f000
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2PCP_MAP_Port_3_PCP_FOR_RV1_TC3_SHIFT 44
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2PCP_MAP_Port_3_PCP_FOR_RV1_TC3_DEFAULT 0x000000000000000b
-
-/* SWITCH_CORE :: PN_EGRESS_PKT_TC2PCP_MAP_Port_3 :: PCP_FOR_RV1_TC2 [43:40] */
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2PCP_MAP_Port_3_PCP_FOR_RV1_TC2_MASK 0x0000000000000f00
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2PCP_MAP_Port_3_PCP_FOR_RV1_TC2_SHIFT 40
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2PCP_MAP_Port_3_PCP_FOR_RV1_TC2_DEFAULT 0x000000000000000a
-
-/* SWITCH_CORE :: PN_EGRESS_PKT_TC2PCP_MAP_Port_3 :: PCP_FOR_RV1_TC1 [39:36] */
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2PCP_MAP_Port_3_PCP_FOR_RV1_TC1_MASK 0x00000000000000f0
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2PCP_MAP_Port_3_PCP_FOR_RV1_TC1_SHIFT 36
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2PCP_MAP_Port_3_PCP_FOR_RV1_TC1_DEFAULT 0x0000000000000009
-
-/* SWITCH_CORE :: PN_EGRESS_PKT_TC2PCP_MAP_Port_3 :: PCP_FOR_RV1_TC0 [35:32] */
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2PCP_MAP_Port_3_PCP_FOR_RV1_TC0_MASK 0x000000000000000f
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2PCP_MAP_Port_3_PCP_FOR_RV1_TC0_SHIFT 32
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2PCP_MAP_Port_3_PCP_FOR_RV1_TC0_DEFAULT 0x0000000000000008
-
-/* SWITCH_CORE :: PN_EGRESS_PKT_TC2PCP_MAP_Port_3 :: PCP_FOR_RV0_TC7 [31:28] */
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2PCP_MAP_Port_3_PCP_FOR_RV0_TC7_MASK 0x00000000f0000000
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2PCP_MAP_Port_3_PCP_FOR_RV0_TC7_SHIFT 28
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2PCP_MAP_Port_3_PCP_FOR_RV0_TC7_DEFAULT 0x0000000000000007
-
-/* SWITCH_CORE :: PN_EGRESS_PKT_TC2PCP_MAP_Port_3 :: PCP_FOR_RV0_TC6 [27:24] */
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2PCP_MAP_Port_3_PCP_FOR_RV0_TC6_MASK 0x000000000f000000
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2PCP_MAP_Port_3_PCP_FOR_RV0_TC6_SHIFT 24
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2PCP_MAP_Port_3_PCP_FOR_RV0_TC6_DEFAULT 0x0000000000000006
-
-/* SWITCH_CORE :: PN_EGRESS_PKT_TC2PCP_MAP_Port_3 :: PCP_FOR_RV0_TC5 [23:20] */
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2PCP_MAP_Port_3_PCP_FOR_RV0_TC5_MASK 0x0000000000f00000
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2PCP_MAP_Port_3_PCP_FOR_RV0_TC5_SHIFT 20
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2PCP_MAP_Port_3_PCP_FOR_RV0_TC5_DEFAULT 0x0000000000000005
-
-/* SWITCH_CORE :: PN_EGRESS_PKT_TC2PCP_MAP_Port_3 :: PCP_FOR_RV0_TC4 [19:16] */
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2PCP_MAP_Port_3_PCP_FOR_RV0_TC4_MASK 0x00000000000f0000
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2PCP_MAP_Port_3_PCP_FOR_RV0_TC4_SHIFT 16
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2PCP_MAP_Port_3_PCP_FOR_RV0_TC4_DEFAULT 0x0000000000000004
-
-/* SWITCH_CORE :: PN_EGRESS_PKT_TC2PCP_MAP_Port_3 :: PCP_FOR_RV0_TC3 [15:12] */
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2PCP_MAP_Port_3_PCP_FOR_RV0_TC3_MASK 0x000000000000f000
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2PCP_MAP_Port_3_PCP_FOR_RV0_TC3_SHIFT 12
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2PCP_MAP_Port_3_PCP_FOR_RV0_TC3_DEFAULT 0x0000000000000003
-
-/* SWITCH_CORE :: PN_EGRESS_PKT_TC2PCP_MAP_Port_3 :: PCP_FOR_RV0_TC2 [11:08] */
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2PCP_MAP_Port_3_PCP_FOR_RV0_TC2_MASK 0x0000000000000f00
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2PCP_MAP_Port_3_PCP_FOR_RV0_TC2_SHIFT 8
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2PCP_MAP_Port_3_PCP_FOR_RV0_TC2_DEFAULT 0x0000000000000002
-
-/* SWITCH_CORE :: PN_EGRESS_PKT_TC2PCP_MAP_Port_3 :: PCP_FOR_RV0_TC1 [07:04] */
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2PCP_MAP_Port_3_PCP_FOR_RV0_TC1_MASK 0x00000000000000f0
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2PCP_MAP_Port_3_PCP_FOR_RV0_TC1_SHIFT 4
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2PCP_MAP_Port_3_PCP_FOR_RV0_TC1_DEFAULT 0x0000000000000001
-
-/* SWITCH_CORE :: PN_EGRESS_PKT_TC2PCP_MAP_Port_3 :: PCP_FOR_RV0_TC0 [03:00] */
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2PCP_MAP_Port_3_PCP_FOR_RV0_TC0_MASK 0x000000000000000f
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2PCP_MAP_Port_3_PCP_FOR_RV0_TC0_SHIFT 0
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2PCP_MAP_Port_3_PCP_FOR_RV0_TC0_DEFAULT 0x0000000000000000
-
-/***************************************************************************
- *PN_EGRESS_PKT_TC2PCP_MAP_Port_4 - Port N, Egress TC to PCP mapping Register
- ***************************************************************************/
-/* SWITCH_CORE :: PN_EGRESS_PKT_TC2PCP_MAP_Port_4 :: PCP_FOR_RV1_TC7 [63:60] */
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2PCP_MAP_Port_4_PCP_FOR_RV1_TC7_MASK 0x00000000f0000000
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2PCP_MAP_Port_4_PCP_FOR_RV1_TC7_SHIFT 60
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2PCP_MAP_Port_4_PCP_FOR_RV1_TC7_DEFAULT 0x000000000000000f
-
-/* SWITCH_CORE :: PN_EGRESS_PKT_TC2PCP_MAP_Port_4 :: PCP_FOR_RV1_TC6 [59:56] */
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2PCP_MAP_Port_4_PCP_FOR_RV1_TC6_MASK 0x000000000f000000
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2PCP_MAP_Port_4_PCP_FOR_RV1_TC6_SHIFT 56
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2PCP_MAP_Port_4_PCP_FOR_RV1_TC6_DEFAULT 0x000000000000000e
-
-/* SWITCH_CORE :: PN_EGRESS_PKT_TC2PCP_MAP_Port_4 :: PCP_FOR_RV1_TC5 [55:52] */
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2PCP_MAP_Port_4_PCP_FOR_RV1_TC5_MASK 0x0000000000f00000
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2PCP_MAP_Port_4_PCP_FOR_RV1_TC5_SHIFT 52
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2PCP_MAP_Port_4_PCP_FOR_RV1_TC5_DEFAULT 0x000000000000000d
-
-/* SWITCH_CORE :: PN_EGRESS_PKT_TC2PCP_MAP_Port_4 :: PCP_FOR_RV1_TC4 [51:48] */
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2PCP_MAP_Port_4_PCP_FOR_RV1_TC4_MASK 0x00000000000f0000
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2PCP_MAP_Port_4_PCP_FOR_RV1_TC4_SHIFT 48
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2PCP_MAP_Port_4_PCP_FOR_RV1_TC4_DEFAULT 0x000000000000000c
-
-/* SWITCH_CORE :: PN_EGRESS_PKT_TC2PCP_MAP_Port_4 :: PCP_FOR_RV1_TC3 [47:44] */
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2PCP_MAP_Port_4_PCP_FOR_RV1_TC3_MASK 0x000000000000f000
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2PCP_MAP_Port_4_PCP_FOR_RV1_TC3_SHIFT 44
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2PCP_MAP_Port_4_PCP_FOR_RV1_TC3_DEFAULT 0x000000000000000b
-
-/* SWITCH_CORE :: PN_EGRESS_PKT_TC2PCP_MAP_Port_4 :: PCP_FOR_RV1_TC2 [43:40] */
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2PCP_MAP_Port_4_PCP_FOR_RV1_TC2_MASK 0x0000000000000f00
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2PCP_MAP_Port_4_PCP_FOR_RV1_TC2_SHIFT 40
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2PCP_MAP_Port_4_PCP_FOR_RV1_TC2_DEFAULT 0x000000000000000a
-
-/* SWITCH_CORE :: PN_EGRESS_PKT_TC2PCP_MAP_Port_4 :: PCP_FOR_RV1_TC1 [39:36] */
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2PCP_MAP_Port_4_PCP_FOR_RV1_TC1_MASK 0x00000000000000f0
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2PCP_MAP_Port_4_PCP_FOR_RV1_TC1_SHIFT 36
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2PCP_MAP_Port_4_PCP_FOR_RV1_TC1_DEFAULT 0x0000000000000009
-
-/* SWITCH_CORE :: PN_EGRESS_PKT_TC2PCP_MAP_Port_4 :: PCP_FOR_RV1_TC0 [35:32] */
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2PCP_MAP_Port_4_PCP_FOR_RV1_TC0_MASK 0x000000000000000f
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2PCP_MAP_Port_4_PCP_FOR_RV1_TC0_SHIFT 32
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2PCP_MAP_Port_4_PCP_FOR_RV1_TC0_DEFAULT 0x0000000000000008
-
-/* SWITCH_CORE :: PN_EGRESS_PKT_TC2PCP_MAP_Port_4 :: PCP_FOR_RV0_TC7 [31:28] */
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2PCP_MAP_Port_4_PCP_FOR_RV0_TC7_MASK 0x00000000f0000000
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2PCP_MAP_Port_4_PCP_FOR_RV0_TC7_SHIFT 28
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2PCP_MAP_Port_4_PCP_FOR_RV0_TC7_DEFAULT 0x0000000000000007
-
-/* SWITCH_CORE :: PN_EGRESS_PKT_TC2PCP_MAP_Port_4 :: PCP_FOR_RV0_TC6 [27:24] */
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2PCP_MAP_Port_4_PCP_FOR_RV0_TC6_MASK 0x000000000f000000
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2PCP_MAP_Port_4_PCP_FOR_RV0_TC6_SHIFT 24
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2PCP_MAP_Port_4_PCP_FOR_RV0_TC6_DEFAULT 0x0000000000000006
-
-/* SWITCH_CORE :: PN_EGRESS_PKT_TC2PCP_MAP_Port_4 :: PCP_FOR_RV0_TC5 [23:20] */
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2PCP_MAP_Port_4_PCP_FOR_RV0_TC5_MASK 0x0000000000f00000
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2PCP_MAP_Port_4_PCP_FOR_RV0_TC5_SHIFT 20
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2PCP_MAP_Port_4_PCP_FOR_RV0_TC5_DEFAULT 0x0000000000000005
-
-/* SWITCH_CORE :: PN_EGRESS_PKT_TC2PCP_MAP_Port_4 :: PCP_FOR_RV0_TC4 [19:16] */
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2PCP_MAP_Port_4_PCP_FOR_RV0_TC4_MASK 0x00000000000f0000
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2PCP_MAP_Port_4_PCP_FOR_RV0_TC4_SHIFT 16
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2PCP_MAP_Port_4_PCP_FOR_RV0_TC4_DEFAULT 0x0000000000000004
-
-/* SWITCH_CORE :: PN_EGRESS_PKT_TC2PCP_MAP_Port_4 :: PCP_FOR_RV0_TC3 [15:12] */
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2PCP_MAP_Port_4_PCP_FOR_RV0_TC3_MASK 0x000000000000f000
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2PCP_MAP_Port_4_PCP_FOR_RV0_TC3_SHIFT 12
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2PCP_MAP_Port_4_PCP_FOR_RV0_TC3_DEFAULT 0x0000000000000003
-
-/* SWITCH_CORE :: PN_EGRESS_PKT_TC2PCP_MAP_Port_4 :: PCP_FOR_RV0_TC2 [11:08] */
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2PCP_MAP_Port_4_PCP_FOR_RV0_TC2_MASK 0x0000000000000f00
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2PCP_MAP_Port_4_PCP_FOR_RV0_TC2_SHIFT 8
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2PCP_MAP_Port_4_PCP_FOR_RV0_TC2_DEFAULT 0x0000000000000002
-
-/* SWITCH_CORE :: PN_EGRESS_PKT_TC2PCP_MAP_Port_4 :: PCP_FOR_RV0_TC1 [07:04] */
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2PCP_MAP_Port_4_PCP_FOR_RV0_TC1_MASK 0x00000000000000f0
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2PCP_MAP_Port_4_PCP_FOR_RV0_TC1_SHIFT 4
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2PCP_MAP_Port_4_PCP_FOR_RV0_TC1_DEFAULT 0x0000000000000001
-
-/* SWITCH_CORE :: PN_EGRESS_PKT_TC2PCP_MAP_Port_4 :: PCP_FOR_RV0_TC0 [03:00] */
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2PCP_MAP_Port_4_PCP_FOR_RV0_TC0_MASK 0x000000000000000f
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2PCP_MAP_Port_4_PCP_FOR_RV0_TC0_SHIFT 0
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2PCP_MAP_Port_4_PCP_FOR_RV0_TC0_DEFAULT 0x0000000000000000
-
-/***************************************************************************
- *PN_EGRESS_PKT_TC2PCP_MAP_Port_5 - Port N, Egress TC to PCP mapping Register
- ***************************************************************************/
-/* SWITCH_CORE :: PN_EGRESS_PKT_TC2PCP_MAP_Port_5 :: PCP_FOR_RV1_TC7 [63:60] */
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2PCP_MAP_Port_5_PCP_FOR_RV1_TC7_MASK 0x00000000f0000000
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2PCP_MAP_Port_5_PCP_FOR_RV1_TC7_SHIFT 60
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2PCP_MAP_Port_5_PCP_FOR_RV1_TC7_DEFAULT 0x000000000000000f
-
-/* SWITCH_CORE :: PN_EGRESS_PKT_TC2PCP_MAP_Port_5 :: PCP_FOR_RV1_TC6 [59:56] */
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2PCP_MAP_Port_5_PCP_FOR_RV1_TC6_MASK 0x000000000f000000
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2PCP_MAP_Port_5_PCP_FOR_RV1_TC6_SHIFT 56
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2PCP_MAP_Port_5_PCP_FOR_RV1_TC6_DEFAULT 0x000000000000000e
-
-/* SWITCH_CORE :: PN_EGRESS_PKT_TC2PCP_MAP_Port_5 :: PCP_FOR_RV1_TC5 [55:52] */
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2PCP_MAP_Port_5_PCP_FOR_RV1_TC5_MASK 0x0000000000f00000
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2PCP_MAP_Port_5_PCP_FOR_RV1_TC5_SHIFT 52
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2PCP_MAP_Port_5_PCP_FOR_RV1_TC5_DEFAULT 0x000000000000000d
-
-/* SWITCH_CORE :: PN_EGRESS_PKT_TC2PCP_MAP_Port_5 :: PCP_FOR_RV1_TC4 [51:48] */
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2PCP_MAP_Port_5_PCP_FOR_RV1_TC4_MASK 0x00000000000f0000
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2PCP_MAP_Port_5_PCP_FOR_RV1_TC4_SHIFT 48
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2PCP_MAP_Port_5_PCP_FOR_RV1_TC4_DEFAULT 0x000000000000000c
-
-/* SWITCH_CORE :: PN_EGRESS_PKT_TC2PCP_MAP_Port_5 :: PCP_FOR_RV1_TC3 [47:44] */
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2PCP_MAP_Port_5_PCP_FOR_RV1_TC3_MASK 0x000000000000f000
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2PCP_MAP_Port_5_PCP_FOR_RV1_TC3_SHIFT 44
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2PCP_MAP_Port_5_PCP_FOR_RV1_TC3_DEFAULT 0x000000000000000b
-
-/* SWITCH_CORE :: PN_EGRESS_PKT_TC2PCP_MAP_Port_5 :: PCP_FOR_RV1_TC2 [43:40] */
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2PCP_MAP_Port_5_PCP_FOR_RV1_TC2_MASK 0x0000000000000f00
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2PCP_MAP_Port_5_PCP_FOR_RV1_TC2_SHIFT 40
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2PCP_MAP_Port_5_PCP_FOR_RV1_TC2_DEFAULT 0x000000000000000a
-
-/* SWITCH_CORE :: PN_EGRESS_PKT_TC2PCP_MAP_Port_5 :: PCP_FOR_RV1_TC1 [39:36] */
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2PCP_MAP_Port_5_PCP_FOR_RV1_TC1_MASK 0x00000000000000f0
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2PCP_MAP_Port_5_PCP_FOR_RV1_TC1_SHIFT 36
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2PCP_MAP_Port_5_PCP_FOR_RV1_TC1_DEFAULT 0x0000000000000009
-
-/* SWITCH_CORE :: PN_EGRESS_PKT_TC2PCP_MAP_Port_5 :: PCP_FOR_RV1_TC0 [35:32] */
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2PCP_MAP_Port_5_PCP_FOR_RV1_TC0_MASK 0x000000000000000f
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2PCP_MAP_Port_5_PCP_FOR_RV1_TC0_SHIFT 32
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2PCP_MAP_Port_5_PCP_FOR_RV1_TC0_DEFAULT 0x0000000000000008
-
-/* SWITCH_CORE :: PN_EGRESS_PKT_TC2PCP_MAP_Port_5 :: PCP_FOR_RV0_TC7 [31:28] */
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2PCP_MAP_Port_5_PCP_FOR_RV0_TC7_MASK 0x00000000f0000000
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2PCP_MAP_Port_5_PCP_FOR_RV0_TC7_SHIFT 28
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2PCP_MAP_Port_5_PCP_FOR_RV0_TC7_DEFAULT 0x0000000000000007
-
-/* SWITCH_CORE :: PN_EGRESS_PKT_TC2PCP_MAP_Port_5 :: PCP_FOR_RV0_TC6 [27:24] */
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2PCP_MAP_Port_5_PCP_FOR_RV0_TC6_MASK 0x000000000f000000
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2PCP_MAP_Port_5_PCP_FOR_RV0_TC6_SHIFT 24
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2PCP_MAP_Port_5_PCP_FOR_RV0_TC6_DEFAULT 0x0000000000000006
-
-/* SWITCH_CORE :: PN_EGRESS_PKT_TC2PCP_MAP_Port_5 :: PCP_FOR_RV0_TC5 [23:20] */
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2PCP_MAP_Port_5_PCP_FOR_RV0_TC5_MASK 0x0000000000f00000
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2PCP_MAP_Port_5_PCP_FOR_RV0_TC5_SHIFT 20
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2PCP_MAP_Port_5_PCP_FOR_RV0_TC5_DEFAULT 0x0000000000000005
-
-/* SWITCH_CORE :: PN_EGRESS_PKT_TC2PCP_MAP_Port_5 :: PCP_FOR_RV0_TC4 [19:16] */
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2PCP_MAP_Port_5_PCP_FOR_RV0_TC4_MASK 0x00000000000f0000
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2PCP_MAP_Port_5_PCP_FOR_RV0_TC4_SHIFT 16
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2PCP_MAP_Port_5_PCP_FOR_RV0_TC4_DEFAULT 0x0000000000000004
-
-/* SWITCH_CORE :: PN_EGRESS_PKT_TC2PCP_MAP_Port_5 :: PCP_FOR_RV0_TC3 [15:12] */
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2PCP_MAP_Port_5_PCP_FOR_RV0_TC3_MASK 0x000000000000f000
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2PCP_MAP_Port_5_PCP_FOR_RV0_TC3_SHIFT 12
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2PCP_MAP_Port_5_PCP_FOR_RV0_TC3_DEFAULT 0x0000000000000003
-
-/* SWITCH_CORE :: PN_EGRESS_PKT_TC2PCP_MAP_Port_5 :: PCP_FOR_RV0_TC2 [11:08] */
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2PCP_MAP_Port_5_PCP_FOR_RV0_TC2_MASK 0x0000000000000f00
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2PCP_MAP_Port_5_PCP_FOR_RV0_TC2_SHIFT 8
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2PCP_MAP_Port_5_PCP_FOR_RV0_TC2_DEFAULT 0x0000000000000002
-
-/* SWITCH_CORE :: PN_EGRESS_PKT_TC2PCP_MAP_Port_5 :: PCP_FOR_RV0_TC1 [07:04] */
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2PCP_MAP_Port_5_PCP_FOR_RV0_TC1_MASK 0x00000000000000f0
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2PCP_MAP_Port_5_PCP_FOR_RV0_TC1_SHIFT 4
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2PCP_MAP_Port_5_PCP_FOR_RV0_TC1_DEFAULT 0x0000000000000001
-
-/* SWITCH_CORE :: PN_EGRESS_PKT_TC2PCP_MAP_Port_5 :: PCP_FOR_RV0_TC0 [03:00] */
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2PCP_MAP_Port_5_PCP_FOR_RV0_TC0_MASK 0x000000000000000f
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2PCP_MAP_Port_5_PCP_FOR_RV0_TC0_SHIFT 0
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2PCP_MAP_Port_5_PCP_FOR_RV0_TC0_DEFAULT 0x0000000000000000
-
-/***************************************************************************
- *P7_EGRESS_PKT_TC2PCP_MAP - Port 7, Egress TC to PCP mapping Register
- ***************************************************************************/
-/* SWITCH_CORE :: P7_EGRESS_PKT_TC2PCP_MAP :: PCP_FOR_RV1_TC7 [63:60] */
-#define BCHP_SWITCH_CORE_P7_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC7_MASK 0x00000000f0000000
-#define BCHP_SWITCH_CORE_P7_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC7_SHIFT 60
-#define BCHP_SWITCH_CORE_P7_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC7_DEFAULT 0x000000000000000f
-
-/* SWITCH_CORE :: P7_EGRESS_PKT_TC2PCP_MAP :: PCP_FOR_RV1_TC6 [59:56] */
-#define BCHP_SWITCH_CORE_P7_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC6_MASK 0x000000000f000000
-#define BCHP_SWITCH_CORE_P7_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC6_SHIFT 56
-#define BCHP_SWITCH_CORE_P7_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC6_DEFAULT 0x000000000000000e
-
-/* SWITCH_CORE :: P7_EGRESS_PKT_TC2PCP_MAP :: PCP_FOR_RV1_TC5 [55:52] */
-#define BCHP_SWITCH_CORE_P7_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC5_MASK 0x0000000000f00000
-#define BCHP_SWITCH_CORE_P7_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC5_SHIFT 52
-#define BCHP_SWITCH_CORE_P7_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC5_DEFAULT 0x000000000000000d
-
-/* SWITCH_CORE :: P7_EGRESS_PKT_TC2PCP_MAP :: PCP_FOR_RV1_TC4 [51:48] */
-#define BCHP_SWITCH_CORE_P7_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC4_MASK 0x00000000000f0000
-#define BCHP_SWITCH_CORE_P7_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC4_SHIFT 48
-#define BCHP_SWITCH_CORE_P7_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC4_DEFAULT 0x000000000000000c
-
-/* SWITCH_CORE :: P7_EGRESS_PKT_TC2PCP_MAP :: PCP_FOR_RV1_TC3 [47:44] */
-#define BCHP_SWITCH_CORE_P7_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC3_MASK 0x000000000000f000
-#define BCHP_SWITCH_CORE_P7_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC3_SHIFT 44
-#define BCHP_SWITCH_CORE_P7_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC3_DEFAULT 0x000000000000000b
-
-/* SWITCH_CORE :: P7_EGRESS_PKT_TC2PCP_MAP :: PCP_FOR_RV1_TC2 [43:40] */
-#define BCHP_SWITCH_CORE_P7_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC2_MASK 0x0000000000000f00
-#define BCHP_SWITCH_CORE_P7_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC2_SHIFT 40
-#define BCHP_SWITCH_CORE_P7_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC2_DEFAULT 0x000000000000000a
-
-/* SWITCH_CORE :: P7_EGRESS_PKT_TC2PCP_MAP :: PCP_FOR_RV1_TC1 [39:36] */
-#define BCHP_SWITCH_CORE_P7_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC1_MASK 0x00000000000000f0
-#define BCHP_SWITCH_CORE_P7_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC1_SHIFT 36
-#define BCHP_SWITCH_CORE_P7_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC1_DEFAULT 0x0000000000000009
-
-/* SWITCH_CORE :: P7_EGRESS_PKT_TC2PCP_MAP :: PCP_FOR_RV1_TC0 [35:32] */
-#define BCHP_SWITCH_CORE_P7_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC0_MASK 0x000000000000000f
-#define BCHP_SWITCH_CORE_P7_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC0_SHIFT 32
-#define BCHP_SWITCH_CORE_P7_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC0_DEFAULT 0x0000000000000008
-
-/* SWITCH_CORE :: P7_EGRESS_PKT_TC2PCP_MAP :: PCP_FOR_RV0_TC7 [31:28] */
-#define BCHP_SWITCH_CORE_P7_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC7_MASK 0x00000000f0000000
-#define BCHP_SWITCH_CORE_P7_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC7_SHIFT 28
-#define BCHP_SWITCH_CORE_P7_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC7_DEFAULT 0x0000000000000007
-
-/* SWITCH_CORE :: P7_EGRESS_PKT_TC2PCP_MAP :: PCP_FOR_RV0_TC6 [27:24] */
-#define BCHP_SWITCH_CORE_P7_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC6_MASK 0x000000000f000000
-#define BCHP_SWITCH_CORE_P7_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC6_SHIFT 24
-#define BCHP_SWITCH_CORE_P7_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC6_DEFAULT 0x0000000000000006
-
-/* SWITCH_CORE :: P7_EGRESS_PKT_TC2PCP_MAP :: PCP_FOR_RV0_TC5 [23:20] */
-#define BCHP_SWITCH_CORE_P7_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC5_MASK 0x0000000000f00000
-#define BCHP_SWITCH_CORE_P7_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC5_SHIFT 20
-#define BCHP_SWITCH_CORE_P7_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC5_DEFAULT 0x0000000000000005
-
-/* SWITCH_CORE :: P7_EGRESS_PKT_TC2PCP_MAP :: PCP_FOR_RV0_TC4 [19:16] */
-#define BCHP_SWITCH_CORE_P7_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC4_MASK 0x00000000000f0000
-#define BCHP_SWITCH_CORE_P7_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC4_SHIFT 16
-#define BCHP_SWITCH_CORE_P7_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC4_DEFAULT 0x0000000000000004
-
-/* SWITCH_CORE :: P7_EGRESS_PKT_TC2PCP_MAP :: PCP_FOR_RV0_TC3 [15:12] */
-#define BCHP_SWITCH_CORE_P7_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC3_MASK 0x000000000000f000
-#define BCHP_SWITCH_CORE_P7_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC3_SHIFT 12
-#define BCHP_SWITCH_CORE_P7_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC3_DEFAULT 0x0000000000000003
-
-/* SWITCH_CORE :: P7_EGRESS_PKT_TC2PCP_MAP :: PCP_FOR_RV0_TC2 [11:08] */
-#define BCHP_SWITCH_CORE_P7_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC2_MASK 0x0000000000000f00
-#define BCHP_SWITCH_CORE_P7_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC2_SHIFT 8
-#define BCHP_SWITCH_CORE_P7_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC2_DEFAULT 0x0000000000000002
-
-/* SWITCH_CORE :: P7_EGRESS_PKT_TC2PCP_MAP :: PCP_FOR_RV0_TC1 [07:04] */
-#define BCHP_SWITCH_CORE_P7_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC1_MASK 0x00000000000000f0
-#define BCHP_SWITCH_CORE_P7_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC1_SHIFT 4
-#define BCHP_SWITCH_CORE_P7_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC1_DEFAULT 0x0000000000000001
-
-/* SWITCH_CORE :: P7_EGRESS_PKT_TC2PCP_MAP :: PCP_FOR_RV0_TC0 [03:00] */
-#define BCHP_SWITCH_CORE_P7_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC0_MASK 0x000000000000000f
-#define BCHP_SWITCH_CORE_P7_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC0_SHIFT 0
-#define BCHP_SWITCH_CORE_P7_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC0_DEFAULT 0x0000000000000000
-
-/***************************************************************************
- *IMP_EGRESS_PKT_TC2PCP_MAP - Port 8, Egress TC to PCP mapping Register
- ***************************************************************************/
-/* SWITCH_CORE :: IMP_EGRESS_PKT_TC2PCP_MAP :: PCP_FOR_RV1_TC7 [63:60] */
-#define BCHP_SWITCH_CORE_IMP_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC7_MASK 0x00000000f0000000
-#define BCHP_SWITCH_CORE_IMP_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC7_SHIFT 60
-#define BCHP_SWITCH_CORE_IMP_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC7_DEFAULT 0x000000000000000f
-
-/* SWITCH_CORE :: IMP_EGRESS_PKT_TC2PCP_MAP :: PCP_FOR_RV1_TC6 [59:56] */
-#define BCHP_SWITCH_CORE_IMP_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC6_MASK 0x000000000f000000
-#define BCHP_SWITCH_CORE_IMP_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC6_SHIFT 56
-#define BCHP_SWITCH_CORE_IMP_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC6_DEFAULT 0x000000000000000e
-
-/* SWITCH_CORE :: IMP_EGRESS_PKT_TC2PCP_MAP :: PCP_FOR_RV1_TC5 [55:52] */
-#define BCHP_SWITCH_CORE_IMP_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC5_MASK 0x0000000000f00000
-#define BCHP_SWITCH_CORE_IMP_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC5_SHIFT 52
-#define BCHP_SWITCH_CORE_IMP_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC5_DEFAULT 0x000000000000000d
-
-/* SWITCH_CORE :: IMP_EGRESS_PKT_TC2PCP_MAP :: PCP_FOR_RV1_TC4 [51:48] */
-#define BCHP_SWITCH_CORE_IMP_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC4_MASK 0x00000000000f0000
-#define BCHP_SWITCH_CORE_IMP_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC4_SHIFT 48
-#define BCHP_SWITCH_CORE_IMP_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC4_DEFAULT 0x000000000000000c
-
-/* SWITCH_CORE :: IMP_EGRESS_PKT_TC2PCP_MAP :: PCP_FOR_RV1_TC3 [47:44] */
-#define BCHP_SWITCH_CORE_IMP_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC3_MASK 0x000000000000f000
-#define BCHP_SWITCH_CORE_IMP_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC3_SHIFT 44
-#define BCHP_SWITCH_CORE_IMP_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC3_DEFAULT 0x000000000000000b
-
-/* SWITCH_CORE :: IMP_EGRESS_PKT_TC2PCP_MAP :: PCP_FOR_RV1_TC2 [43:40] */
-#define BCHP_SWITCH_CORE_IMP_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC2_MASK 0x0000000000000f00
-#define BCHP_SWITCH_CORE_IMP_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC2_SHIFT 40
-#define BCHP_SWITCH_CORE_IMP_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC2_DEFAULT 0x000000000000000a
-
-/* SWITCH_CORE :: IMP_EGRESS_PKT_TC2PCP_MAP :: PCP_FOR_RV1_TC1 [39:36] */
-#define BCHP_SWITCH_CORE_IMP_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC1_MASK 0x00000000000000f0
-#define BCHP_SWITCH_CORE_IMP_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC1_SHIFT 36
-#define BCHP_SWITCH_CORE_IMP_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC1_DEFAULT 0x0000000000000009
-
-/* SWITCH_CORE :: IMP_EGRESS_PKT_TC2PCP_MAP :: PCP_FOR_RV1_TC0 [35:32] */
-#define BCHP_SWITCH_CORE_IMP_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC0_MASK 0x000000000000000f
-#define BCHP_SWITCH_CORE_IMP_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC0_SHIFT 32
-#define BCHP_SWITCH_CORE_IMP_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC0_DEFAULT 0x0000000000000008
-
-/* SWITCH_CORE :: IMP_EGRESS_PKT_TC2PCP_MAP :: PCP_FOR_RV0_TC7 [31:28] */
-#define BCHP_SWITCH_CORE_IMP_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC7_MASK 0x00000000f0000000
-#define BCHP_SWITCH_CORE_IMP_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC7_SHIFT 28
-#define BCHP_SWITCH_CORE_IMP_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC7_DEFAULT 0x0000000000000007
-
-/* SWITCH_CORE :: IMP_EGRESS_PKT_TC2PCP_MAP :: PCP_FOR_RV0_TC6 [27:24] */
-#define BCHP_SWITCH_CORE_IMP_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC6_MASK 0x000000000f000000
-#define BCHP_SWITCH_CORE_IMP_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC6_SHIFT 24
-#define BCHP_SWITCH_CORE_IMP_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC6_DEFAULT 0x0000000000000006
-
-/* SWITCH_CORE :: IMP_EGRESS_PKT_TC2PCP_MAP :: PCP_FOR_RV0_TC5 [23:20] */
-#define BCHP_SWITCH_CORE_IMP_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC5_MASK 0x0000000000f00000
-#define BCHP_SWITCH_CORE_IMP_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC5_SHIFT 20
-#define BCHP_SWITCH_CORE_IMP_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC5_DEFAULT 0x0000000000000005
-
-/* SWITCH_CORE :: IMP_EGRESS_PKT_TC2PCP_MAP :: PCP_FOR_RV0_TC4 [19:16] */
-#define BCHP_SWITCH_CORE_IMP_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC4_MASK 0x00000000000f0000
-#define BCHP_SWITCH_CORE_IMP_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC4_SHIFT 16
-#define BCHP_SWITCH_CORE_IMP_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC4_DEFAULT 0x0000000000000004
-
-/* SWITCH_CORE :: IMP_EGRESS_PKT_TC2PCP_MAP :: PCP_FOR_RV0_TC3 [15:12] */
-#define BCHP_SWITCH_CORE_IMP_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC3_MASK 0x000000000000f000
-#define BCHP_SWITCH_CORE_IMP_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC3_SHIFT 12
-#define BCHP_SWITCH_CORE_IMP_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC3_DEFAULT 0x0000000000000003
-
-/* SWITCH_CORE :: IMP_EGRESS_PKT_TC2PCP_MAP :: PCP_FOR_RV0_TC2 [11:08] */
-#define BCHP_SWITCH_CORE_IMP_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC2_MASK 0x0000000000000f00
-#define BCHP_SWITCH_CORE_IMP_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC2_SHIFT 8
-#define BCHP_SWITCH_CORE_IMP_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC2_DEFAULT 0x0000000000000002
-
-/* SWITCH_CORE :: IMP_EGRESS_PKT_TC2PCP_MAP :: PCP_FOR_RV0_TC1 [07:04] */
-#define BCHP_SWITCH_CORE_IMP_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC1_MASK 0x00000000000000f0
-#define BCHP_SWITCH_CORE_IMP_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC1_SHIFT 4
-#define BCHP_SWITCH_CORE_IMP_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC1_DEFAULT 0x0000000000000001
-
-/* SWITCH_CORE :: IMP_EGRESS_PKT_TC2PCP_MAP :: PCP_FOR_RV0_TC0 [03:00] */
-#define BCHP_SWITCH_CORE_IMP_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC0_MASK 0x000000000000000f
-#define BCHP_SWITCH_CORE_IMP_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC0_SHIFT 0
-#define BCHP_SWITCH_CORE_IMP_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC0_DEFAULT 0x0000000000000000
-
-/***************************************************************************
- *PN_EGRESS_PKT_TC2CPCP_MAP_Port_0 - Port N, Egress TC to CPCP mapping Register
- ***************************************************************************/
-/* SWITCH_CORE :: PN_EGRESS_PKT_TC2CPCP_MAP_Port_0 :: SWITCH_RESV_15 [63:63] */
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_0_SWITCH_RESV_15_MASK 0x0000000080000000
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_0_SWITCH_RESV_15_SHIFT 63
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_0_SWITCH_RESV_15_DEFAULT 0x0000000000000000
-
-/* SWITCH_CORE :: PN_EGRESS_PKT_TC2CPCP_MAP_Port_0 :: CPCP_FOR_RV1_TC7 [62:60] */
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_0_CPCP_FOR_RV1_TC7_MASK 0x0000000070000000
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_0_CPCP_FOR_RV1_TC7_SHIFT 60
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_0_CPCP_FOR_RV1_TC7_DEFAULT 0x0000000000000007
-
-/* SWITCH_CORE :: PN_EGRESS_PKT_TC2CPCP_MAP_Port_0 :: SWITCH_RESV_14 [59:59] */
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_0_SWITCH_RESV_14_MASK 0x0000000008000000
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_0_SWITCH_RESV_14_SHIFT 59
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_0_SWITCH_RESV_14_DEFAULT 0x0000000000000000
-
-/* SWITCH_CORE :: PN_EGRESS_PKT_TC2CPCP_MAP_Port_0 :: CPCP_FOR_RV1_TC6 [58:56] */
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_0_CPCP_FOR_RV1_TC6_MASK 0x0000000007000000
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_0_CPCP_FOR_RV1_TC6_SHIFT 56
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_0_CPCP_FOR_RV1_TC6_DEFAULT 0x0000000000000006
-
-/* SWITCH_CORE :: PN_EGRESS_PKT_TC2CPCP_MAP_Port_0 :: SWITCH_RESV_13 [55:55] */
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_0_SWITCH_RESV_13_MASK 0x0000000000800000
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_0_SWITCH_RESV_13_SHIFT 55
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_0_SWITCH_RESV_13_DEFAULT 0x0000000000000000
-
-/* SWITCH_CORE :: PN_EGRESS_PKT_TC2CPCP_MAP_Port_0 :: CPCP_FOR_RV1_TC5 [54:52] */
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_0_CPCP_FOR_RV1_TC5_MASK 0x0000000000700000
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_0_CPCP_FOR_RV1_TC5_SHIFT 52
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_0_CPCP_FOR_RV1_TC5_DEFAULT 0x0000000000000005
-
-/* SWITCH_CORE :: PN_EGRESS_PKT_TC2CPCP_MAP_Port_0 :: SWITCH_RESV_12 [51:51] */
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_0_SWITCH_RESV_12_MASK 0x0000000000080000
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_0_SWITCH_RESV_12_SHIFT 51
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_0_SWITCH_RESV_12_DEFAULT 0x0000000000000000
-
-/* SWITCH_CORE :: PN_EGRESS_PKT_TC2CPCP_MAP_Port_0 :: CPCP_FOR_RV1_TC4 [50:48] */
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_0_CPCP_FOR_RV1_TC4_MASK 0x0000000000070000
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_0_CPCP_FOR_RV1_TC4_SHIFT 48
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_0_CPCP_FOR_RV1_TC4_DEFAULT 0x0000000000000004
-
-/* SWITCH_CORE :: PN_EGRESS_PKT_TC2CPCP_MAP_Port_0 :: SWITCH_RESV_11 [47:47] */
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_0_SWITCH_RESV_11_MASK 0x0000000000008000
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_0_SWITCH_RESV_11_SHIFT 47
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_0_SWITCH_RESV_11_DEFAULT 0x0000000000000000
-
-/* SWITCH_CORE :: PN_EGRESS_PKT_TC2CPCP_MAP_Port_0 :: CPCP_FOR_RV1_TC3 [46:44] */
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_0_CPCP_FOR_RV1_TC3_MASK 0x0000000000007000
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_0_CPCP_FOR_RV1_TC3_SHIFT 44
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_0_CPCP_FOR_RV1_TC3_DEFAULT 0x0000000000000003
-
-/* SWITCH_CORE :: PN_EGRESS_PKT_TC2CPCP_MAP_Port_0 :: SWITCH_RESV_10 [43:43] */
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_0_SWITCH_RESV_10_MASK 0x0000000000000800
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_0_SWITCH_RESV_10_SHIFT 43
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_0_SWITCH_RESV_10_DEFAULT 0x0000000000000000
-
-/* SWITCH_CORE :: PN_EGRESS_PKT_TC2CPCP_MAP_Port_0 :: CPCP_FOR_RV1_TC2 [42:40] */
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_0_CPCP_FOR_RV1_TC2_MASK 0x0000000000000700
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_0_CPCP_FOR_RV1_TC2_SHIFT 40
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_0_CPCP_FOR_RV1_TC2_DEFAULT 0x0000000000000002
-
-/* SWITCH_CORE :: PN_EGRESS_PKT_TC2CPCP_MAP_Port_0 :: SWITCH_RESV_9 [39:39] */
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_0_SWITCH_RESV_9_MASK 0x0000000000000080
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_0_SWITCH_RESV_9_SHIFT 39
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_0_SWITCH_RESV_9_DEFAULT 0x0000000000000000
-
-/* SWITCH_CORE :: PN_EGRESS_PKT_TC2CPCP_MAP_Port_0 :: CPCP_FOR_RV1_TC1 [38:36] */
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_0_CPCP_FOR_RV1_TC1_MASK 0x0000000000000070
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_0_CPCP_FOR_RV1_TC1_SHIFT 36
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_0_CPCP_FOR_RV1_TC1_DEFAULT 0x0000000000000001
-
-/* SWITCH_CORE :: PN_EGRESS_PKT_TC2CPCP_MAP_Port_0 :: SWITCH_RESV_8 [35:35] */
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_0_SWITCH_RESV_8_MASK 0x0000000000000008
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_0_SWITCH_RESV_8_SHIFT 35
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_0_SWITCH_RESV_8_DEFAULT 0x0000000000000000
-
-/* SWITCH_CORE :: PN_EGRESS_PKT_TC2CPCP_MAP_Port_0 :: CPCP_FOR_RV1_TC0 [34:32] */
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_0_CPCP_FOR_RV1_TC0_MASK 0x0000000000000007
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_0_CPCP_FOR_RV1_TC0_SHIFT 32
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_0_CPCP_FOR_RV1_TC0_DEFAULT 0x0000000000000000
-
-/* SWITCH_CORE :: PN_EGRESS_PKT_TC2CPCP_MAP_Port_0 :: SWITCH_RESV_7 [31:31] */
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_0_SWITCH_RESV_7_MASK 0x0000000080000000
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_0_SWITCH_RESV_7_SHIFT 31
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_0_SWITCH_RESV_7_DEFAULT 0x0000000000000000
-
-/* SWITCH_CORE :: PN_EGRESS_PKT_TC2CPCP_MAP_Port_0 :: CPCP_FOR_RV0_TC7 [30:28] */
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_0_CPCP_FOR_RV0_TC7_MASK 0x0000000070000000
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_0_CPCP_FOR_RV0_TC7_SHIFT 28
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_0_CPCP_FOR_RV0_TC7_DEFAULT 0x0000000000000007
-
-/* SWITCH_CORE :: PN_EGRESS_PKT_TC2CPCP_MAP_Port_0 :: SWITCH_RESV_6 [27:27] */
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_0_SWITCH_RESV_6_MASK 0x0000000008000000
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_0_SWITCH_RESV_6_SHIFT 27
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_0_SWITCH_RESV_6_DEFAULT 0x0000000000000000
-
-/* SWITCH_CORE :: PN_EGRESS_PKT_TC2CPCP_MAP_Port_0 :: CPCP_FOR_RV0_TC6 [26:24] */
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_0_CPCP_FOR_RV0_TC6_MASK 0x0000000007000000
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_0_CPCP_FOR_RV0_TC6_SHIFT 24
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_0_CPCP_FOR_RV0_TC6_DEFAULT 0x0000000000000006
-
-/* SWITCH_CORE :: PN_EGRESS_PKT_TC2CPCP_MAP_Port_0 :: SWITCH_RESV_5 [23:23] */
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_0_SWITCH_RESV_5_MASK 0x0000000000800000
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_0_SWITCH_RESV_5_SHIFT 23
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_0_SWITCH_RESV_5_DEFAULT 0x0000000000000000
-
-/* SWITCH_CORE :: PN_EGRESS_PKT_TC2CPCP_MAP_Port_0 :: CPCP_FOR_RV0_TC5 [22:20] */
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_0_CPCP_FOR_RV0_TC5_MASK 0x0000000000700000
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_0_CPCP_FOR_RV0_TC5_SHIFT 20
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_0_CPCP_FOR_RV0_TC5_DEFAULT 0x0000000000000005
-
-/* SWITCH_CORE :: PN_EGRESS_PKT_TC2CPCP_MAP_Port_0 :: SWITCH_RESV_4 [19:19] */
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_0_SWITCH_RESV_4_MASK 0x0000000000080000
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_0_SWITCH_RESV_4_SHIFT 19
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_0_SWITCH_RESV_4_DEFAULT 0x0000000000000000
-
-/* SWITCH_CORE :: PN_EGRESS_PKT_TC2CPCP_MAP_Port_0 :: CPCP_FOR_RV0_TC4 [18:16] */
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_0_CPCP_FOR_RV0_TC4_MASK 0x0000000000070000
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_0_CPCP_FOR_RV0_TC4_SHIFT 16
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_0_CPCP_FOR_RV0_TC4_DEFAULT 0x0000000000000004
-
-/* SWITCH_CORE :: PN_EGRESS_PKT_TC2CPCP_MAP_Port_0 :: SWITCH_RESV_3 [15:15] */
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_0_SWITCH_RESV_3_MASK 0x0000000000008000
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_0_SWITCH_RESV_3_SHIFT 15
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_0_SWITCH_RESV_3_DEFAULT 0x0000000000000000
-
-/* SWITCH_CORE :: PN_EGRESS_PKT_TC2CPCP_MAP_Port_0 :: CPCP_FOR_RV0_TC3 [14:12] */
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_0_CPCP_FOR_RV0_TC3_MASK 0x0000000000007000
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_0_CPCP_FOR_RV0_TC3_SHIFT 12
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_0_CPCP_FOR_RV0_TC3_DEFAULT 0x0000000000000003
-
-/* SWITCH_CORE :: PN_EGRESS_PKT_TC2CPCP_MAP_Port_0 :: SWITCH_RESV_2 [11:11] */
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_0_SWITCH_RESV_2_MASK 0x0000000000000800
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_0_SWITCH_RESV_2_SHIFT 11
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_0_SWITCH_RESV_2_DEFAULT 0x0000000000000000
-
-/* SWITCH_CORE :: PN_EGRESS_PKT_TC2CPCP_MAP_Port_0 :: CPCP_FOR_RV0_TC2 [10:08] */
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_0_CPCP_FOR_RV0_TC2_MASK 0x0000000000000700
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_0_CPCP_FOR_RV0_TC2_SHIFT 8
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_0_CPCP_FOR_RV0_TC2_DEFAULT 0x0000000000000002
-
-/* SWITCH_CORE :: PN_EGRESS_PKT_TC2CPCP_MAP_Port_0 :: SWITCH_RESV_1 [07:07] */
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_0_SWITCH_RESV_1_MASK 0x0000000000000080
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_0_SWITCH_RESV_1_SHIFT 7
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_0_SWITCH_RESV_1_DEFAULT 0x0000000000000000
-
-/* SWITCH_CORE :: PN_EGRESS_PKT_TC2CPCP_MAP_Port_0 :: CPCP_FOR_RV0_TC1 [06:04] */
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_0_CPCP_FOR_RV0_TC1_MASK 0x0000000000000070
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_0_CPCP_FOR_RV0_TC1_SHIFT 4
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_0_CPCP_FOR_RV0_TC1_DEFAULT 0x0000000000000001
-
-/* SWITCH_CORE :: PN_EGRESS_PKT_TC2CPCP_MAP_Port_0 :: SWITCH_RESV_0 [03:03] */
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_0_SWITCH_RESV_0_MASK 0x0000000000000008
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_0_SWITCH_RESV_0_SHIFT 3
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_0_SWITCH_RESV_0_DEFAULT 0x0000000000000000
-
-/* SWITCH_CORE :: PN_EGRESS_PKT_TC2CPCP_MAP_Port_0 :: CPCP_FOR_RV0_TC0 [02:00] */
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_0_CPCP_FOR_RV0_TC0_MASK 0x0000000000000007
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_0_CPCP_FOR_RV0_TC0_SHIFT 0
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_0_CPCP_FOR_RV0_TC0_DEFAULT 0x0000000000000000
-
-/***************************************************************************
- *PN_EGRESS_PKT_TC2CPCP_MAP_Port_1 - Port N, Egress TC to CPCP mapping Register
- ***************************************************************************/
-/* SWITCH_CORE :: PN_EGRESS_PKT_TC2CPCP_MAP_Port_1 :: SWITCH_RESV_15 [63:63] */
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_1_SWITCH_RESV_15_MASK 0x0000000080000000
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_1_SWITCH_RESV_15_SHIFT 63
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_1_SWITCH_RESV_15_DEFAULT 0x0000000000000000
-
-/* SWITCH_CORE :: PN_EGRESS_PKT_TC2CPCP_MAP_Port_1 :: CPCP_FOR_RV1_TC7 [62:60] */
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_1_CPCP_FOR_RV1_TC7_MASK 0x0000000070000000
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_1_CPCP_FOR_RV1_TC7_SHIFT 60
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_1_CPCP_FOR_RV1_TC7_DEFAULT 0x0000000000000007
-
-/* SWITCH_CORE :: PN_EGRESS_PKT_TC2CPCP_MAP_Port_1 :: SWITCH_RESV_14 [59:59] */
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_1_SWITCH_RESV_14_MASK 0x0000000008000000
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_1_SWITCH_RESV_14_SHIFT 59
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_1_SWITCH_RESV_14_DEFAULT 0x0000000000000000
-
-/* SWITCH_CORE :: PN_EGRESS_PKT_TC2CPCP_MAP_Port_1 :: CPCP_FOR_RV1_TC6 [58:56] */
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_1_CPCP_FOR_RV1_TC6_MASK 0x0000000007000000
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_1_CPCP_FOR_RV1_TC6_SHIFT 56
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_1_CPCP_FOR_RV1_TC6_DEFAULT 0x0000000000000006
-
-/* SWITCH_CORE :: PN_EGRESS_PKT_TC2CPCP_MAP_Port_1 :: SWITCH_RESV_13 [55:55] */
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_1_SWITCH_RESV_13_MASK 0x0000000000800000
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_1_SWITCH_RESV_13_SHIFT 55
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_1_SWITCH_RESV_13_DEFAULT 0x0000000000000000
-
-/* SWITCH_CORE :: PN_EGRESS_PKT_TC2CPCP_MAP_Port_1 :: CPCP_FOR_RV1_TC5 [54:52] */
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_1_CPCP_FOR_RV1_TC5_MASK 0x0000000000700000
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_1_CPCP_FOR_RV1_TC5_SHIFT 52
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_1_CPCP_FOR_RV1_TC5_DEFAULT 0x0000000000000005
-
-/* SWITCH_CORE :: PN_EGRESS_PKT_TC2CPCP_MAP_Port_1 :: SWITCH_RESV_12 [51:51] */
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_1_SWITCH_RESV_12_MASK 0x0000000000080000
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_1_SWITCH_RESV_12_SHIFT 51
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_1_SWITCH_RESV_12_DEFAULT 0x0000000000000000
-
-/* SWITCH_CORE :: PN_EGRESS_PKT_TC2CPCP_MAP_Port_1 :: CPCP_FOR_RV1_TC4 [50:48] */
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_1_CPCP_FOR_RV1_TC4_MASK 0x0000000000070000
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_1_CPCP_FOR_RV1_TC4_SHIFT 48
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_1_CPCP_FOR_RV1_TC4_DEFAULT 0x0000000000000004
-
-/* SWITCH_CORE :: PN_EGRESS_PKT_TC2CPCP_MAP_Port_1 :: SWITCH_RESV_11 [47:47] */
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_1_SWITCH_RESV_11_MASK 0x0000000000008000
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_1_SWITCH_RESV_11_SHIFT 47
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_1_SWITCH_RESV_11_DEFAULT 0x0000000000000000
-
-/* SWITCH_CORE :: PN_EGRESS_PKT_TC2CPCP_MAP_Port_1 :: CPCP_FOR_RV1_TC3 [46:44] */
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_1_CPCP_FOR_RV1_TC3_MASK 0x0000000000007000
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_1_CPCP_FOR_RV1_TC3_SHIFT 44
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_1_CPCP_FOR_RV1_TC3_DEFAULT 0x0000000000000003
-
-/* SWITCH_CORE :: PN_EGRESS_PKT_TC2CPCP_MAP_Port_1 :: SWITCH_RESV_10 [43:43] */
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_1_SWITCH_RESV_10_MASK 0x0000000000000800
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_1_SWITCH_RESV_10_SHIFT 43
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_1_SWITCH_RESV_10_DEFAULT 0x0000000000000000
-
-/* SWITCH_CORE :: PN_EGRESS_PKT_TC2CPCP_MAP_Port_1 :: CPCP_FOR_RV1_TC2 [42:40] */
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_1_CPCP_FOR_RV1_TC2_MASK 0x0000000000000700
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_1_CPCP_FOR_RV1_TC2_SHIFT 40
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_1_CPCP_FOR_RV1_TC2_DEFAULT 0x0000000000000002
-
-/* SWITCH_CORE :: PN_EGRESS_PKT_TC2CPCP_MAP_Port_1 :: SWITCH_RESV_9 [39:39] */
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_1_SWITCH_RESV_9_MASK 0x0000000000000080
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_1_SWITCH_RESV_9_SHIFT 39
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_1_SWITCH_RESV_9_DEFAULT 0x0000000000000000
-
-/* SWITCH_CORE :: PN_EGRESS_PKT_TC2CPCP_MAP_Port_1 :: CPCP_FOR_RV1_TC1 [38:36] */
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_1_CPCP_FOR_RV1_TC1_MASK 0x0000000000000070
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_1_CPCP_FOR_RV1_TC1_SHIFT 36
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_1_CPCP_FOR_RV1_TC1_DEFAULT 0x0000000000000001
-
-/* SWITCH_CORE :: PN_EGRESS_PKT_TC2CPCP_MAP_Port_1 :: SWITCH_RESV_8 [35:35] */
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_1_SWITCH_RESV_8_MASK 0x0000000000000008
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_1_SWITCH_RESV_8_SHIFT 35
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_1_SWITCH_RESV_8_DEFAULT 0x0000000000000000
-
-/* SWITCH_CORE :: PN_EGRESS_PKT_TC2CPCP_MAP_Port_1 :: CPCP_FOR_RV1_TC0 [34:32] */
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_1_CPCP_FOR_RV1_TC0_MASK 0x0000000000000007
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_1_CPCP_FOR_RV1_TC0_SHIFT 32
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_1_CPCP_FOR_RV1_TC0_DEFAULT 0x0000000000000000
-
-/* SWITCH_CORE :: PN_EGRESS_PKT_TC2CPCP_MAP_Port_1 :: SWITCH_RESV_7 [31:31] */
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_1_SWITCH_RESV_7_MASK 0x0000000080000000
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_1_SWITCH_RESV_7_SHIFT 31
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_1_SWITCH_RESV_7_DEFAULT 0x0000000000000000
-
-/* SWITCH_CORE :: PN_EGRESS_PKT_TC2CPCP_MAP_Port_1 :: CPCP_FOR_RV0_TC7 [30:28] */
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_1_CPCP_FOR_RV0_TC7_MASK 0x0000000070000000
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_1_CPCP_FOR_RV0_TC7_SHIFT 28
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_1_CPCP_FOR_RV0_TC7_DEFAULT 0x0000000000000007
-
-/* SWITCH_CORE :: PN_EGRESS_PKT_TC2CPCP_MAP_Port_1 :: SWITCH_RESV_6 [27:27] */
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_1_SWITCH_RESV_6_MASK 0x0000000008000000
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_1_SWITCH_RESV_6_SHIFT 27
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_1_SWITCH_RESV_6_DEFAULT 0x0000000000000000
-
-/* SWITCH_CORE :: PN_EGRESS_PKT_TC2CPCP_MAP_Port_1 :: CPCP_FOR_RV0_TC6 [26:24] */
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_1_CPCP_FOR_RV0_TC6_MASK 0x0000000007000000
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_1_CPCP_FOR_RV0_TC6_SHIFT 24
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_1_CPCP_FOR_RV0_TC6_DEFAULT 0x0000000000000006
-
-/* SWITCH_CORE :: PN_EGRESS_PKT_TC2CPCP_MAP_Port_1 :: SWITCH_RESV_5 [23:23] */
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_1_SWITCH_RESV_5_MASK 0x0000000000800000
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_1_SWITCH_RESV_5_SHIFT 23
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_1_SWITCH_RESV_5_DEFAULT 0x0000000000000000
-
-/* SWITCH_CORE :: PN_EGRESS_PKT_TC2CPCP_MAP_Port_1 :: CPCP_FOR_RV0_TC5 [22:20] */
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_1_CPCP_FOR_RV0_TC5_MASK 0x0000000000700000
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_1_CPCP_FOR_RV0_TC5_SHIFT 20
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_1_CPCP_FOR_RV0_TC5_DEFAULT 0x0000000000000005
-
-/* SWITCH_CORE :: PN_EGRESS_PKT_TC2CPCP_MAP_Port_1 :: SWITCH_RESV_4 [19:19] */
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_1_SWITCH_RESV_4_MASK 0x0000000000080000
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_1_SWITCH_RESV_4_SHIFT 19
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_1_SWITCH_RESV_4_DEFAULT 0x0000000000000000
-
-/* SWITCH_CORE :: PN_EGRESS_PKT_TC2CPCP_MAP_Port_1 :: CPCP_FOR_RV0_TC4 [18:16] */
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_1_CPCP_FOR_RV0_TC4_MASK 0x0000000000070000
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_1_CPCP_FOR_RV0_TC4_SHIFT 16
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_1_CPCP_FOR_RV0_TC4_DEFAULT 0x0000000000000004
-
-/* SWITCH_CORE :: PN_EGRESS_PKT_TC2CPCP_MAP_Port_1 :: SWITCH_RESV_3 [15:15] */
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_1_SWITCH_RESV_3_MASK 0x0000000000008000
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_1_SWITCH_RESV_3_SHIFT 15
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_1_SWITCH_RESV_3_DEFAULT 0x0000000000000000
-
-/* SWITCH_CORE :: PN_EGRESS_PKT_TC2CPCP_MAP_Port_1 :: CPCP_FOR_RV0_TC3 [14:12] */
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_1_CPCP_FOR_RV0_TC3_MASK 0x0000000000007000
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_1_CPCP_FOR_RV0_TC3_SHIFT 12
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_1_CPCP_FOR_RV0_TC3_DEFAULT 0x0000000000000003
-
-/* SWITCH_CORE :: PN_EGRESS_PKT_TC2CPCP_MAP_Port_1 :: SWITCH_RESV_2 [11:11] */
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_1_SWITCH_RESV_2_MASK 0x0000000000000800
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_1_SWITCH_RESV_2_SHIFT 11
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_1_SWITCH_RESV_2_DEFAULT 0x0000000000000000
-
-/* SWITCH_CORE :: PN_EGRESS_PKT_TC2CPCP_MAP_Port_1 :: CPCP_FOR_RV0_TC2 [10:08] */
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_1_CPCP_FOR_RV0_TC2_MASK 0x0000000000000700
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_1_CPCP_FOR_RV0_TC2_SHIFT 8
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_1_CPCP_FOR_RV0_TC2_DEFAULT 0x0000000000000002
-
-/* SWITCH_CORE :: PN_EGRESS_PKT_TC2CPCP_MAP_Port_1 :: SWITCH_RESV_1 [07:07] */
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_1_SWITCH_RESV_1_MASK 0x0000000000000080
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_1_SWITCH_RESV_1_SHIFT 7
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_1_SWITCH_RESV_1_DEFAULT 0x0000000000000000
-
-/* SWITCH_CORE :: PN_EGRESS_PKT_TC2CPCP_MAP_Port_1 :: CPCP_FOR_RV0_TC1 [06:04] */
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_1_CPCP_FOR_RV0_TC1_MASK 0x0000000000000070
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_1_CPCP_FOR_RV0_TC1_SHIFT 4
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_1_CPCP_FOR_RV0_TC1_DEFAULT 0x0000000000000001
-
-/* SWITCH_CORE :: PN_EGRESS_PKT_TC2CPCP_MAP_Port_1 :: SWITCH_RESV_0 [03:03] */
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_1_SWITCH_RESV_0_MASK 0x0000000000000008
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_1_SWITCH_RESV_0_SHIFT 3
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_1_SWITCH_RESV_0_DEFAULT 0x0000000000000000
-
-/* SWITCH_CORE :: PN_EGRESS_PKT_TC2CPCP_MAP_Port_1 :: CPCP_FOR_RV0_TC0 [02:00] */
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_1_CPCP_FOR_RV0_TC0_MASK 0x0000000000000007
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_1_CPCP_FOR_RV0_TC0_SHIFT 0
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_1_CPCP_FOR_RV0_TC0_DEFAULT 0x0000000000000000
-
-/***************************************************************************
- *PN_EGRESS_PKT_TC2CPCP_MAP_Port_2 - Port N, Egress TC to CPCP mapping Register
- ***************************************************************************/
-/* SWITCH_CORE :: PN_EGRESS_PKT_TC2CPCP_MAP_Port_2 :: SWITCH_RESV_15 [63:63] */
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_2_SWITCH_RESV_15_MASK 0x0000000080000000
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_2_SWITCH_RESV_15_SHIFT 63
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_2_SWITCH_RESV_15_DEFAULT 0x0000000000000000
-
-/* SWITCH_CORE :: PN_EGRESS_PKT_TC2CPCP_MAP_Port_2 :: CPCP_FOR_RV1_TC7 [62:60] */
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_2_CPCP_FOR_RV1_TC7_MASK 0x0000000070000000
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_2_CPCP_FOR_RV1_TC7_SHIFT 60
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_2_CPCP_FOR_RV1_TC7_DEFAULT 0x0000000000000007
-
-/* SWITCH_CORE :: PN_EGRESS_PKT_TC2CPCP_MAP_Port_2 :: SWITCH_RESV_14 [59:59] */
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_2_SWITCH_RESV_14_MASK 0x0000000008000000
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_2_SWITCH_RESV_14_SHIFT 59
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_2_SWITCH_RESV_14_DEFAULT 0x0000000000000000
-
-/* SWITCH_CORE :: PN_EGRESS_PKT_TC2CPCP_MAP_Port_2 :: CPCP_FOR_RV1_TC6 [58:56] */
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_2_CPCP_FOR_RV1_TC6_MASK 0x0000000007000000
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_2_CPCP_FOR_RV1_TC6_SHIFT 56
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_2_CPCP_FOR_RV1_TC6_DEFAULT 0x0000000000000006
-
-/* SWITCH_CORE :: PN_EGRESS_PKT_TC2CPCP_MAP_Port_2 :: SWITCH_RESV_13 [55:55] */
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_2_SWITCH_RESV_13_MASK 0x0000000000800000
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_2_SWITCH_RESV_13_SHIFT 55
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_2_SWITCH_RESV_13_DEFAULT 0x0000000000000000
-
-/* SWITCH_CORE :: PN_EGRESS_PKT_TC2CPCP_MAP_Port_2 :: CPCP_FOR_RV1_TC5 [54:52] */
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_2_CPCP_FOR_RV1_TC5_MASK 0x0000000000700000
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_2_CPCP_FOR_RV1_TC5_SHIFT 52
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_2_CPCP_FOR_RV1_TC5_DEFAULT 0x0000000000000005
-
-/* SWITCH_CORE :: PN_EGRESS_PKT_TC2CPCP_MAP_Port_2 :: SWITCH_RESV_12 [51:51] */
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_2_SWITCH_RESV_12_MASK 0x0000000000080000
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_2_SWITCH_RESV_12_SHIFT 51
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_2_SWITCH_RESV_12_DEFAULT 0x0000000000000000
-
-/* SWITCH_CORE :: PN_EGRESS_PKT_TC2CPCP_MAP_Port_2 :: CPCP_FOR_RV1_TC4 [50:48] */
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_2_CPCP_FOR_RV1_TC4_MASK 0x0000000000070000
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_2_CPCP_FOR_RV1_TC4_SHIFT 48
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_2_CPCP_FOR_RV1_TC4_DEFAULT 0x0000000000000004
-
-/* SWITCH_CORE :: PN_EGRESS_PKT_TC2CPCP_MAP_Port_2 :: SWITCH_RESV_11 [47:47] */
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_2_SWITCH_RESV_11_MASK 0x0000000000008000
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_2_SWITCH_RESV_11_SHIFT 47
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_2_SWITCH_RESV_11_DEFAULT 0x0000000000000000
-
-/* SWITCH_CORE :: PN_EGRESS_PKT_TC2CPCP_MAP_Port_2 :: CPCP_FOR_RV1_TC3 [46:44] */
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_2_CPCP_FOR_RV1_TC3_MASK 0x0000000000007000
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_2_CPCP_FOR_RV1_TC3_SHIFT 44
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_2_CPCP_FOR_RV1_TC3_DEFAULT 0x0000000000000003
-
-/* SWITCH_CORE :: PN_EGRESS_PKT_TC2CPCP_MAP_Port_2 :: SWITCH_RESV_10 [43:43] */
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_2_SWITCH_RESV_10_MASK 0x0000000000000800
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_2_SWITCH_RESV_10_SHIFT 43
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_2_SWITCH_RESV_10_DEFAULT 0x0000000000000000
-
-/* SWITCH_CORE :: PN_EGRESS_PKT_TC2CPCP_MAP_Port_2 :: CPCP_FOR_RV1_TC2 [42:40] */
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_2_CPCP_FOR_RV1_TC2_MASK 0x0000000000000700
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_2_CPCP_FOR_RV1_TC2_SHIFT 40
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_2_CPCP_FOR_RV1_TC2_DEFAULT 0x0000000000000002
-
-/* SWITCH_CORE :: PN_EGRESS_PKT_TC2CPCP_MAP_Port_2 :: SWITCH_RESV_9 [39:39] */
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_2_SWITCH_RESV_9_MASK 0x0000000000000080
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_2_SWITCH_RESV_9_SHIFT 39
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_2_SWITCH_RESV_9_DEFAULT 0x0000000000000000
-
-/* SWITCH_CORE :: PN_EGRESS_PKT_TC2CPCP_MAP_Port_2 :: CPCP_FOR_RV1_TC1 [38:36] */
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_2_CPCP_FOR_RV1_TC1_MASK 0x0000000000000070
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_2_CPCP_FOR_RV1_TC1_SHIFT 36
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_2_CPCP_FOR_RV1_TC1_DEFAULT 0x0000000000000001
-
-/* SWITCH_CORE :: PN_EGRESS_PKT_TC2CPCP_MAP_Port_2 :: SWITCH_RESV_8 [35:35] */
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_2_SWITCH_RESV_8_MASK 0x0000000000000008
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_2_SWITCH_RESV_8_SHIFT 35
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_2_SWITCH_RESV_8_DEFAULT 0x0000000000000000
-
-/* SWITCH_CORE :: PN_EGRESS_PKT_TC2CPCP_MAP_Port_2 :: CPCP_FOR_RV1_TC0 [34:32] */
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_2_CPCP_FOR_RV1_TC0_MASK 0x0000000000000007
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_2_CPCP_FOR_RV1_TC0_SHIFT 32
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_2_CPCP_FOR_RV1_TC0_DEFAULT 0x0000000000000000
-
-/* SWITCH_CORE :: PN_EGRESS_PKT_TC2CPCP_MAP_Port_2 :: SWITCH_RESV_7 [31:31] */
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_2_SWITCH_RESV_7_MASK 0x0000000080000000
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_2_SWITCH_RESV_7_SHIFT 31
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_2_SWITCH_RESV_7_DEFAULT 0x0000000000000000
-
-/* SWITCH_CORE :: PN_EGRESS_PKT_TC2CPCP_MAP_Port_2 :: CPCP_FOR_RV0_TC7 [30:28] */
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_2_CPCP_FOR_RV0_TC7_MASK 0x0000000070000000
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_2_CPCP_FOR_RV0_TC7_SHIFT 28
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_2_CPCP_FOR_RV0_TC7_DEFAULT 0x0000000000000007
-
-/* SWITCH_CORE :: PN_EGRESS_PKT_TC2CPCP_MAP_Port_2 :: SWITCH_RESV_6 [27:27] */
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_2_SWITCH_RESV_6_MASK 0x0000000008000000
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_2_SWITCH_RESV_6_SHIFT 27
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_2_SWITCH_RESV_6_DEFAULT 0x0000000000000000
-
-/* SWITCH_CORE :: PN_EGRESS_PKT_TC2CPCP_MAP_Port_2 :: CPCP_FOR_RV0_TC6 [26:24] */
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_2_CPCP_FOR_RV0_TC6_MASK 0x0000000007000000
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_2_CPCP_FOR_RV0_TC6_SHIFT 24
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_2_CPCP_FOR_RV0_TC6_DEFAULT 0x0000000000000006
-
-/* SWITCH_CORE :: PN_EGRESS_PKT_TC2CPCP_MAP_Port_2 :: SWITCH_RESV_5 [23:23] */
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_2_SWITCH_RESV_5_MASK 0x0000000000800000
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_2_SWITCH_RESV_5_SHIFT 23
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_2_SWITCH_RESV_5_DEFAULT 0x0000000000000000
-
-/* SWITCH_CORE :: PN_EGRESS_PKT_TC2CPCP_MAP_Port_2 :: CPCP_FOR_RV0_TC5 [22:20] */
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_2_CPCP_FOR_RV0_TC5_MASK 0x0000000000700000
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_2_CPCP_FOR_RV0_TC5_SHIFT 20
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_2_CPCP_FOR_RV0_TC5_DEFAULT 0x0000000000000005
-
-/* SWITCH_CORE :: PN_EGRESS_PKT_TC2CPCP_MAP_Port_2 :: SWITCH_RESV_4 [19:19] */
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_2_SWITCH_RESV_4_MASK 0x0000000000080000
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_2_SWITCH_RESV_4_SHIFT 19
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_2_SWITCH_RESV_4_DEFAULT 0x0000000000000000
-
-/* SWITCH_CORE :: PN_EGRESS_PKT_TC2CPCP_MAP_Port_2 :: CPCP_FOR_RV0_TC4 [18:16] */
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_2_CPCP_FOR_RV0_TC4_MASK 0x0000000000070000
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_2_CPCP_FOR_RV0_TC4_SHIFT 16
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_2_CPCP_FOR_RV0_TC4_DEFAULT 0x0000000000000004
-
-/* SWITCH_CORE :: PN_EGRESS_PKT_TC2CPCP_MAP_Port_2 :: SWITCH_RESV_3 [15:15] */
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_2_SWITCH_RESV_3_MASK 0x0000000000008000
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_2_SWITCH_RESV_3_SHIFT 15
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_2_SWITCH_RESV_3_DEFAULT 0x0000000000000000
-
-/* SWITCH_CORE :: PN_EGRESS_PKT_TC2CPCP_MAP_Port_2 :: CPCP_FOR_RV0_TC3 [14:12] */
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_2_CPCP_FOR_RV0_TC3_MASK 0x0000000000007000
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_2_CPCP_FOR_RV0_TC3_SHIFT 12
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_2_CPCP_FOR_RV0_TC3_DEFAULT 0x0000000000000003
-
-/* SWITCH_CORE :: PN_EGRESS_PKT_TC2CPCP_MAP_Port_2 :: SWITCH_RESV_2 [11:11] */
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_2_SWITCH_RESV_2_MASK 0x0000000000000800
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_2_SWITCH_RESV_2_SHIFT 11
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_2_SWITCH_RESV_2_DEFAULT 0x0000000000000000
-
-/* SWITCH_CORE :: PN_EGRESS_PKT_TC2CPCP_MAP_Port_2 :: CPCP_FOR_RV0_TC2 [10:08] */
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_2_CPCP_FOR_RV0_TC2_MASK 0x0000000000000700
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_2_CPCP_FOR_RV0_TC2_SHIFT 8
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_2_CPCP_FOR_RV0_TC2_DEFAULT 0x0000000000000002
-
-/* SWITCH_CORE :: PN_EGRESS_PKT_TC2CPCP_MAP_Port_2 :: SWITCH_RESV_1 [07:07] */
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_2_SWITCH_RESV_1_MASK 0x0000000000000080
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_2_SWITCH_RESV_1_SHIFT 7
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_2_SWITCH_RESV_1_DEFAULT 0x0000000000000000
-
-/* SWITCH_CORE :: PN_EGRESS_PKT_TC2CPCP_MAP_Port_2 :: CPCP_FOR_RV0_TC1 [06:04] */
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_2_CPCP_FOR_RV0_TC1_MASK 0x0000000000000070
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_2_CPCP_FOR_RV0_TC1_SHIFT 4
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_2_CPCP_FOR_RV0_TC1_DEFAULT 0x0000000000000001
-
-/* SWITCH_CORE :: PN_EGRESS_PKT_TC2CPCP_MAP_Port_2 :: SWITCH_RESV_0 [03:03] */
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_2_SWITCH_RESV_0_MASK 0x0000000000000008
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_2_SWITCH_RESV_0_SHIFT 3
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_2_SWITCH_RESV_0_DEFAULT 0x0000000000000000
-
-/* SWITCH_CORE :: PN_EGRESS_PKT_TC2CPCP_MAP_Port_2 :: CPCP_FOR_RV0_TC0 [02:00] */
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_2_CPCP_FOR_RV0_TC0_MASK 0x0000000000000007
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_2_CPCP_FOR_RV0_TC0_SHIFT 0
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_2_CPCP_FOR_RV0_TC0_DEFAULT 0x0000000000000000
-
-/***************************************************************************
- *PN_EGRESS_PKT_TC2CPCP_MAP_Port_3 - Port N, Egress TC to CPCP mapping Register
- ***************************************************************************/
-/* SWITCH_CORE :: PN_EGRESS_PKT_TC2CPCP_MAP_Port_3 :: SWITCH_RESV_15 [63:63] */
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_3_SWITCH_RESV_15_MASK 0x0000000080000000
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_3_SWITCH_RESV_15_SHIFT 63
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_3_SWITCH_RESV_15_DEFAULT 0x0000000000000000
-
-/* SWITCH_CORE :: PN_EGRESS_PKT_TC2CPCP_MAP_Port_3 :: CPCP_FOR_RV1_TC7 [62:60] */
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_3_CPCP_FOR_RV1_TC7_MASK 0x0000000070000000
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_3_CPCP_FOR_RV1_TC7_SHIFT 60
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_3_CPCP_FOR_RV1_TC7_DEFAULT 0x0000000000000007
-
-/* SWITCH_CORE :: PN_EGRESS_PKT_TC2CPCP_MAP_Port_3 :: SWITCH_RESV_14 [59:59] */
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_3_SWITCH_RESV_14_MASK 0x0000000008000000
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_3_SWITCH_RESV_14_SHIFT 59
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_3_SWITCH_RESV_14_DEFAULT 0x0000000000000000
-
-/* SWITCH_CORE :: PN_EGRESS_PKT_TC2CPCP_MAP_Port_3 :: CPCP_FOR_RV1_TC6 [58:56] */
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_3_CPCP_FOR_RV1_TC6_MASK 0x0000000007000000
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_3_CPCP_FOR_RV1_TC6_SHIFT 56
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_3_CPCP_FOR_RV1_TC6_DEFAULT 0x0000000000000006
-
-/* SWITCH_CORE :: PN_EGRESS_PKT_TC2CPCP_MAP_Port_3 :: SWITCH_RESV_13 [55:55] */
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_3_SWITCH_RESV_13_MASK 0x0000000000800000
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_3_SWITCH_RESV_13_SHIFT 55
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_3_SWITCH_RESV_13_DEFAULT 0x0000000000000000
-
-/* SWITCH_CORE :: PN_EGRESS_PKT_TC2CPCP_MAP_Port_3 :: CPCP_FOR_RV1_TC5 [54:52] */
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_3_CPCP_FOR_RV1_TC5_MASK 0x0000000000700000
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_3_CPCP_FOR_RV1_TC5_SHIFT 52
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_3_CPCP_FOR_RV1_TC5_DEFAULT 0x0000000000000005
-
-/* SWITCH_CORE :: PN_EGRESS_PKT_TC2CPCP_MAP_Port_3 :: SWITCH_RESV_12 [51:51] */
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_3_SWITCH_RESV_12_MASK 0x0000000000080000
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_3_SWITCH_RESV_12_SHIFT 51
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_3_SWITCH_RESV_12_DEFAULT 0x0000000000000000
-
-/* SWITCH_CORE :: PN_EGRESS_PKT_TC2CPCP_MAP_Port_3 :: CPCP_FOR_RV1_TC4 [50:48] */
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_3_CPCP_FOR_RV1_TC4_MASK 0x0000000000070000
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_3_CPCP_FOR_RV1_TC4_SHIFT 48
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_3_CPCP_FOR_RV1_TC4_DEFAULT 0x0000000000000004
-
-/* SWITCH_CORE :: PN_EGRESS_PKT_TC2CPCP_MAP_Port_3 :: SWITCH_RESV_11 [47:47] */
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_3_SWITCH_RESV_11_MASK 0x0000000000008000
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_3_SWITCH_RESV_11_SHIFT 47
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_3_SWITCH_RESV_11_DEFAULT 0x0000000000000000
-
-/* SWITCH_CORE :: PN_EGRESS_PKT_TC2CPCP_MAP_Port_3 :: CPCP_FOR_RV1_TC3 [46:44] */
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_3_CPCP_FOR_RV1_TC3_MASK 0x0000000000007000
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_3_CPCP_FOR_RV1_TC3_SHIFT 44
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_3_CPCP_FOR_RV1_TC3_DEFAULT 0x0000000000000003
-
-/* SWITCH_CORE :: PN_EGRESS_PKT_TC2CPCP_MAP_Port_3 :: SWITCH_RESV_10 [43:43] */
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_3_SWITCH_RESV_10_MASK 0x0000000000000800
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_3_SWITCH_RESV_10_SHIFT 43
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_3_SWITCH_RESV_10_DEFAULT 0x0000000000000000
-
-/* SWITCH_CORE :: PN_EGRESS_PKT_TC2CPCP_MAP_Port_3 :: CPCP_FOR_RV1_TC2 [42:40] */
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_3_CPCP_FOR_RV1_TC2_MASK 0x0000000000000700
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_3_CPCP_FOR_RV1_TC2_SHIFT 40
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_3_CPCP_FOR_RV1_TC2_DEFAULT 0x0000000000000002
-
-/* SWITCH_CORE :: PN_EGRESS_PKT_TC2CPCP_MAP_Port_3 :: SWITCH_RESV_9 [39:39] */
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_3_SWITCH_RESV_9_MASK 0x0000000000000080
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_3_SWITCH_RESV_9_SHIFT 39
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_3_SWITCH_RESV_9_DEFAULT 0x0000000000000000
-
-/* SWITCH_CORE :: PN_EGRESS_PKT_TC2CPCP_MAP_Port_3 :: CPCP_FOR_RV1_TC1 [38:36] */
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_3_CPCP_FOR_RV1_TC1_MASK 0x0000000000000070
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_3_CPCP_FOR_RV1_TC1_SHIFT 36
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_3_CPCP_FOR_RV1_TC1_DEFAULT 0x0000000000000001
-
-/* SWITCH_CORE :: PN_EGRESS_PKT_TC2CPCP_MAP_Port_3 :: SWITCH_RESV_8 [35:35] */
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_3_SWITCH_RESV_8_MASK 0x0000000000000008
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_3_SWITCH_RESV_8_SHIFT 35
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_3_SWITCH_RESV_8_DEFAULT 0x0000000000000000
-
-/* SWITCH_CORE :: PN_EGRESS_PKT_TC2CPCP_MAP_Port_3 :: CPCP_FOR_RV1_TC0 [34:32] */
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_3_CPCP_FOR_RV1_TC0_MASK 0x0000000000000007
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_3_CPCP_FOR_RV1_TC0_SHIFT 32
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_3_CPCP_FOR_RV1_TC0_DEFAULT 0x0000000000000000
-
-/* SWITCH_CORE :: PN_EGRESS_PKT_TC2CPCP_MAP_Port_3 :: SWITCH_RESV_7 [31:31] */
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_3_SWITCH_RESV_7_MASK 0x0000000080000000
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_3_SWITCH_RESV_7_SHIFT 31
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_3_SWITCH_RESV_7_DEFAULT 0x0000000000000000
-
-/* SWITCH_CORE :: PN_EGRESS_PKT_TC2CPCP_MAP_Port_3 :: CPCP_FOR_RV0_TC7 [30:28] */
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_3_CPCP_FOR_RV0_TC7_MASK 0x0000000070000000
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_3_CPCP_FOR_RV0_TC7_SHIFT 28
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_3_CPCP_FOR_RV0_TC7_DEFAULT 0x0000000000000007
-
-/* SWITCH_CORE :: PN_EGRESS_PKT_TC2CPCP_MAP_Port_3 :: SWITCH_RESV_6 [27:27] */
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_3_SWITCH_RESV_6_MASK 0x0000000008000000
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_3_SWITCH_RESV_6_SHIFT 27
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_3_SWITCH_RESV_6_DEFAULT 0x0000000000000000
-
-/* SWITCH_CORE :: PN_EGRESS_PKT_TC2CPCP_MAP_Port_3 :: CPCP_FOR_RV0_TC6 [26:24] */
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_3_CPCP_FOR_RV0_TC6_MASK 0x0000000007000000
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_3_CPCP_FOR_RV0_TC6_SHIFT 24
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_3_CPCP_FOR_RV0_TC6_DEFAULT 0x0000000000000006
-
-/* SWITCH_CORE :: PN_EGRESS_PKT_TC2CPCP_MAP_Port_3 :: SWITCH_RESV_5 [23:23] */
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_3_SWITCH_RESV_5_MASK 0x0000000000800000
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_3_SWITCH_RESV_5_SHIFT 23
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_3_SWITCH_RESV_5_DEFAULT 0x0000000000000000
-
-/* SWITCH_CORE :: PN_EGRESS_PKT_TC2CPCP_MAP_Port_3 :: CPCP_FOR_RV0_TC5 [22:20] */
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_3_CPCP_FOR_RV0_TC5_MASK 0x0000000000700000
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_3_CPCP_FOR_RV0_TC5_SHIFT 20
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_3_CPCP_FOR_RV0_TC5_DEFAULT 0x0000000000000005
-
-/* SWITCH_CORE :: PN_EGRESS_PKT_TC2CPCP_MAP_Port_3 :: SWITCH_RESV_4 [19:19] */
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_3_SWITCH_RESV_4_MASK 0x0000000000080000
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_3_SWITCH_RESV_4_SHIFT 19
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_3_SWITCH_RESV_4_DEFAULT 0x0000000000000000
-
-/* SWITCH_CORE :: PN_EGRESS_PKT_TC2CPCP_MAP_Port_3 :: CPCP_FOR_RV0_TC4 [18:16] */
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_3_CPCP_FOR_RV0_TC4_MASK 0x0000000000070000
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_3_CPCP_FOR_RV0_TC4_SHIFT 16
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_3_CPCP_FOR_RV0_TC4_DEFAULT 0x0000000000000004
-
-/* SWITCH_CORE :: PN_EGRESS_PKT_TC2CPCP_MAP_Port_3 :: SWITCH_RESV_3 [15:15] */
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_3_SWITCH_RESV_3_MASK 0x0000000000008000
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_3_SWITCH_RESV_3_SHIFT 15
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_3_SWITCH_RESV_3_DEFAULT 0x0000000000000000
-
-/* SWITCH_CORE :: PN_EGRESS_PKT_TC2CPCP_MAP_Port_3 :: CPCP_FOR_RV0_TC3 [14:12] */
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_3_CPCP_FOR_RV0_TC3_MASK 0x0000000000007000
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_3_CPCP_FOR_RV0_TC3_SHIFT 12
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_3_CPCP_FOR_RV0_TC3_DEFAULT 0x0000000000000003
-
-/* SWITCH_CORE :: PN_EGRESS_PKT_TC2CPCP_MAP_Port_3 :: SWITCH_RESV_2 [11:11] */
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_3_SWITCH_RESV_2_MASK 0x0000000000000800
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_3_SWITCH_RESV_2_SHIFT 11
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_3_SWITCH_RESV_2_DEFAULT 0x0000000000000000
-
-/* SWITCH_CORE :: PN_EGRESS_PKT_TC2CPCP_MAP_Port_3 :: CPCP_FOR_RV0_TC2 [10:08] */
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_3_CPCP_FOR_RV0_TC2_MASK 0x0000000000000700
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_3_CPCP_FOR_RV0_TC2_SHIFT 8
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_3_CPCP_FOR_RV0_TC2_DEFAULT 0x0000000000000002
-
-/* SWITCH_CORE :: PN_EGRESS_PKT_TC2CPCP_MAP_Port_3 :: SWITCH_RESV_1 [07:07] */
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_3_SWITCH_RESV_1_MASK 0x0000000000000080
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_3_SWITCH_RESV_1_SHIFT 7
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_3_SWITCH_RESV_1_DEFAULT 0x0000000000000000
-
-/* SWITCH_CORE :: PN_EGRESS_PKT_TC2CPCP_MAP_Port_3 :: CPCP_FOR_RV0_TC1 [06:04] */
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_3_CPCP_FOR_RV0_TC1_MASK 0x0000000000000070
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_3_CPCP_FOR_RV0_TC1_SHIFT 4
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_3_CPCP_FOR_RV0_TC1_DEFAULT 0x0000000000000001
-
-/* SWITCH_CORE :: PN_EGRESS_PKT_TC2CPCP_MAP_Port_3 :: SWITCH_RESV_0 [03:03] */
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_3_SWITCH_RESV_0_MASK 0x0000000000000008
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_3_SWITCH_RESV_0_SHIFT 3
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_3_SWITCH_RESV_0_DEFAULT 0x0000000000000000
-
-/* SWITCH_CORE :: PN_EGRESS_PKT_TC2CPCP_MAP_Port_3 :: CPCP_FOR_RV0_TC0 [02:00] */
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_3_CPCP_FOR_RV0_TC0_MASK 0x0000000000000007
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_3_CPCP_FOR_RV0_TC0_SHIFT 0
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_3_CPCP_FOR_RV0_TC0_DEFAULT 0x0000000000000000
-
-/***************************************************************************
- *PN_EGRESS_PKT_TC2CPCP_MAP_Port_4 - Port N, Egress TC to CPCP mapping Register
- ***************************************************************************/
-/* SWITCH_CORE :: PN_EGRESS_PKT_TC2CPCP_MAP_Port_4 :: SWITCH_RESV_15 [63:63] */
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_4_SWITCH_RESV_15_MASK 0x0000000080000000
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_4_SWITCH_RESV_15_SHIFT 63
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_4_SWITCH_RESV_15_DEFAULT 0x0000000000000000
-
-/* SWITCH_CORE :: PN_EGRESS_PKT_TC2CPCP_MAP_Port_4 :: CPCP_FOR_RV1_TC7 [62:60] */
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_4_CPCP_FOR_RV1_TC7_MASK 0x0000000070000000
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_4_CPCP_FOR_RV1_TC7_SHIFT 60
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_4_CPCP_FOR_RV1_TC7_DEFAULT 0x0000000000000007
-
-/* SWITCH_CORE :: PN_EGRESS_PKT_TC2CPCP_MAP_Port_4 :: SWITCH_RESV_14 [59:59] */
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_4_SWITCH_RESV_14_MASK 0x0000000008000000
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_4_SWITCH_RESV_14_SHIFT 59
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_4_SWITCH_RESV_14_DEFAULT 0x0000000000000000
-
-/* SWITCH_CORE :: PN_EGRESS_PKT_TC2CPCP_MAP_Port_4 :: CPCP_FOR_RV1_TC6 [58:56] */
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_4_CPCP_FOR_RV1_TC6_MASK 0x0000000007000000
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_4_CPCP_FOR_RV1_TC6_SHIFT 56
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_4_CPCP_FOR_RV1_TC6_DEFAULT 0x0000000000000006
-
-/* SWITCH_CORE :: PN_EGRESS_PKT_TC2CPCP_MAP_Port_4 :: SWITCH_RESV_13 [55:55] */
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_4_SWITCH_RESV_13_MASK 0x0000000000800000
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_4_SWITCH_RESV_13_SHIFT 55
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_4_SWITCH_RESV_13_DEFAULT 0x0000000000000000
-
-/* SWITCH_CORE :: PN_EGRESS_PKT_TC2CPCP_MAP_Port_4 :: CPCP_FOR_RV1_TC5 [54:52] */
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_4_CPCP_FOR_RV1_TC5_MASK 0x0000000000700000
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_4_CPCP_FOR_RV1_TC5_SHIFT 52
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_4_CPCP_FOR_RV1_TC5_DEFAULT 0x0000000000000005
-
-/* SWITCH_CORE :: PN_EGRESS_PKT_TC2CPCP_MAP_Port_4 :: SWITCH_RESV_12 [51:51] */
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_4_SWITCH_RESV_12_MASK 0x0000000000080000
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_4_SWITCH_RESV_12_SHIFT 51
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_4_SWITCH_RESV_12_DEFAULT 0x0000000000000000
-
-/* SWITCH_CORE :: PN_EGRESS_PKT_TC2CPCP_MAP_Port_4 :: CPCP_FOR_RV1_TC4 [50:48] */
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_4_CPCP_FOR_RV1_TC4_MASK 0x0000000000070000
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_4_CPCP_FOR_RV1_TC4_SHIFT 48
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_4_CPCP_FOR_RV1_TC4_DEFAULT 0x0000000000000004
-
-/* SWITCH_CORE :: PN_EGRESS_PKT_TC2CPCP_MAP_Port_4 :: SWITCH_RESV_11 [47:47] */
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_4_SWITCH_RESV_11_MASK 0x0000000000008000
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_4_SWITCH_RESV_11_SHIFT 47
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_4_SWITCH_RESV_11_DEFAULT 0x0000000000000000
-
-/* SWITCH_CORE :: PN_EGRESS_PKT_TC2CPCP_MAP_Port_4 :: CPCP_FOR_RV1_TC3 [46:44] */
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_4_CPCP_FOR_RV1_TC3_MASK 0x0000000000007000
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_4_CPCP_FOR_RV1_TC3_SHIFT 44
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_4_CPCP_FOR_RV1_TC3_DEFAULT 0x0000000000000003
-
-/* SWITCH_CORE :: PN_EGRESS_PKT_TC2CPCP_MAP_Port_4 :: SWITCH_RESV_10 [43:43] */
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_4_SWITCH_RESV_10_MASK 0x0000000000000800
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_4_SWITCH_RESV_10_SHIFT 43
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_4_SWITCH_RESV_10_DEFAULT 0x0000000000000000
-
-/* SWITCH_CORE :: PN_EGRESS_PKT_TC2CPCP_MAP_Port_4 :: CPCP_FOR_RV1_TC2 [42:40] */
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_4_CPCP_FOR_RV1_TC2_MASK 0x0000000000000700
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_4_CPCP_FOR_RV1_TC2_SHIFT 40
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_4_CPCP_FOR_RV1_TC2_DEFAULT 0x0000000000000002
-
-/* SWITCH_CORE :: PN_EGRESS_PKT_TC2CPCP_MAP_Port_4 :: SWITCH_RESV_9 [39:39] */
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_4_SWITCH_RESV_9_MASK 0x0000000000000080
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_4_SWITCH_RESV_9_SHIFT 39
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_4_SWITCH_RESV_9_DEFAULT 0x0000000000000000
-
-/* SWITCH_CORE :: PN_EGRESS_PKT_TC2CPCP_MAP_Port_4 :: CPCP_FOR_RV1_TC1 [38:36] */
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_4_CPCP_FOR_RV1_TC1_MASK 0x0000000000000070
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_4_CPCP_FOR_RV1_TC1_SHIFT 36
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_4_CPCP_FOR_RV1_TC1_DEFAULT 0x0000000000000001
-
-/* SWITCH_CORE :: PN_EGRESS_PKT_TC2CPCP_MAP_Port_4 :: SWITCH_RESV_8 [35:35] */
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_4_SWITCH_RESV_8_MASK 0x0000000000000008
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_4_SWITCH_RESV_8_SHIFT 35
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_4_SWITCH_RESV_8_DEFAULT 0x0000000000000000
-
-/* SWITCH_CORE :: PN_EGRESS_PKT_TC2CPCP_MAP_Port_4 :: CPCP_FOR_RV1_TC0 [34:32] */
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_4_CPCP_FOR_RV1_TC0_MASK 0x0000000000000007
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_4_CPCP_FOR_RV1_TC0_SHIFT 32
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_4_CPCP_FOR_RV1_TC0_DEFAULT 0x0000000000000000
-
-/* SWITCH_CORE :: PN_EGRESS_PKT_TC2CPCP_MAP_Port_4 :: SWITCH_RESV_7 [31:31] */
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_4_SWITCH_RESV_7_MASK 0x0000000080000000
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_4_SWITCH_RESV_7_SHIFT 31
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_4_SWITCH_RESV_7_DEFAULT 0x0000000000000000
-
-/* SWITCH_CORE :: PN_EGRESS_PKT_TC2CPCP_MAP_Port_4 :: CPCP_FOR_RV0_TC7 [30:28] */
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_4_CPCP_FOR_RV0_TC7_MASK 0x0000000070000000
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_4_CPCP_FOR_RV0_TC7_SHIFT 28
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_4_CPCP_FOR_RV0_TC7_DEFAULT 0x0000000000000007
-
-/* SWITCH_CORE :: PN_EGRESS_PKT_TC2CPCP_MAP_Port_4 :: SWITCH_RESV_6 [27:27] */
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_4_SWITCH_RESV_6_MASK 0x0000000008000000
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_4_SWITCH_RESV_6_SHIFT 27
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_4_SWITCH_RESV_6_DEFAULT 0x0000000000000000
-
-/* SWITCH_CORE :: PN_EGRESS_PKT_TC2CPCP_MAP_Port_4 :: CPCP_FOR_RV0_TC6 [26:24] */
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_4_CPCP_FOR_RV0_TC6_MASK 0x0000000007000000
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_4_CPCP_FOR_RV0_TC6_SHIFT 24
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_4_CPCP_FOR_RV0_TC6_DEFAULT 0x0000000000000006
-
-/* SWITCH_CORE :: PN_EGRESS_PKT_TC2CPCP_MAP_Port_4 :: SWITCH_RESV_5 [23:23] */
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_4_SWITCH_RESV_5_MASK 0x0000000000800000
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_4_SWITCH_RESV_5_SHIFT 23
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_4_SWITCH_RESV_5_DEFAULT 0x0000000000000000
-
-/* SWITCH_CORE :: PN_EGRESS_PKT_TC2CPCP_MAP_Port_4 :: CPCP_FOR_RV0_TC5 [22:20] */
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_4_CPCP_FOR_RV0_TC5_MASK 0x0000000000700000
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_4_CPCP_FOR_RV0_TC5_SHIFT 20
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_4_CPCP_FOR_RV0_TC5_DEFAULT 0x0000000000000005
-
-/* SWITCH_CORE :: PN_EGRESS_PKT_TC2CPCP_MAP_Port_4 :: SWITCH_RESV_4 [19:19] */
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_4_SWITCH_RESV_4_MASK 0x0000000000080000
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_4_SWITCH_RESV_4_SHIFT 19
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_4_SWITCH_RESV_4_DEFAULT 0x0000000000000000
-
-/* SWITCH_CORE :: PN_EGRESS_PKT_TC2CPCP_MAP_Port_4 :: CPCP_FOR_RV0_TC4 [18:16] */
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_4_CPCP_FOR_RV0_TC4_MASK 0x0000000000070000
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_4_CPCP_FOR_RV0_TC4_SHIFT 16
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_4_CPCP_FOR_RV0_TC4_DEFAULT 0x0000000000000004
-
-/* SWITCH_CORE :: PN_EGRESS_PKT_TC2CPCP_MAP_Port_4 :: SWITCH_RESV_3 [15:15] */
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_4_SWITCH_RESV_3_MASK 0x0000000000008000
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_4_SWITCH_RESV_3_SHIFT 15
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_4_SWITCH_RESV_3_DEFAULT 0x0000000000000000
-
-/* SWITCH_CORE :: PN_EGRESS_PKT_TC2CPCP_MAP_Port_4 :: CPCP_FOR_RV0_TC3 [14:12] */
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_4_CPCP_FOR_RV0_TC3_MASK 0x0000000000007000
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_4_CPCP_FOR_RV0_TC3_SHIFT 12
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_4_CPCP_FOR_RV0_TC3_DEFAULT 0x0000000000000003
-
-/* SWITCH_CORE :: PN_EGRESS_PKT_TC2CPCP_MAP_Port_4 :: SWITCH_RESV_2 [11:11] */
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_4_SWITCH_RESV_2_MASK 0x0000000000000800
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_4_SWITCH_RESV_2_SHIFT 11
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_4_SWITCH_RESV_2_DEFAULT 0x0000000000000000
-
-/* SWITCH_CORE :: PN_EGRESS_PKT_TC2CPCP_MAP_Port_4 :: CPCP_FOR_RV0_TC2 [10:08] */
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_4_CPCP_FOR_RV0_TC2_MASK 0x0000000000000700
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_4_CPCP_FOR_RV0_TC2_SHIFT 8
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_4_CPCP_FOR_RV0_TC2_DEFAULT 0x0000000000000002
-
-/* SWITCH_CORE :: PN_EGRESS_PKT_TC2CPCP_MAP_Port_4 :: SWITCH_RESV_1 [07:07] */
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_4_SWITCH_RESV_1_MASK 0x0000000000000080
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_4_SWITCH_RESV_1_SHIFT 7
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_4_SWITCH_RESV_1_DEFAULT 0x0000000000000000
-
-/* SWITCH_CORE :: PN_EGRESS_PKT_TC2CPCP_MAP_Port_4 :: CPCP_FOR_RV0_TC1 [06:04] */
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_4_CPCP_FOR_RV0_TC1_MASK 0x0000000000000070
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_4_CPCP_FOR_RV0_TC1_SHIFT 4
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_4_CPCP_FOR_RV0_TC1_DEFAULT 0x0000000000000001
-
-/* SWITCH_CORE :: PN_EGRESS_PKT_TC2CPCP_MAP_Port_4 :: SWITCH_RESV_0 [03:03] */
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_4_SWITCH_RESV_0_MASK 0x0000000000000008
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_4_SWITCH_RESV_0_SHIFT 3
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_4_SWITCH_RESV_0_DEFAULT 0x0000000000000000
-
-/* SWITCH_CORE :: PN_EGRESS_PKT_TC2CPCP_MAP_Port_4 :: CPCP_FOR_RV0_TC0 [02:00] */
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_4_CPCP_FOR_RV0_TC0_MASK 0x0000000000000007
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_4_CPCP_FOR_RV0_TC0_SHIFT 0
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_4_CPCP_FOR_RV0_TC0_DEFAULT 0x0000000000000000
-
-/***************************************************************************
- *PN_EGRESS_PKT_TC2CPCP_MAP_Port_5 - Port N, Egress TC to CPCP mapping Register
- ***************************************************************************/
-/* SWITCH_CORE :: PN_EGRESS_PKT_TC2CPCP_MAP_Port_5 :: SWITCH_RESV_15 [63:63] */
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_5_SWITCH_RESV_15_MASK 0x0000000080000000
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_5_SWITCH_RESV_15_SHIFT 63
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_5_SWITCH_RESV_15_DEFAULT 0x0000000000000000
-
-/* SWITCH_CORE :: PN_EGRESS_PKT_TC2CPCP_MAP_Port_5 :: CPCP_FOR_RV1_TC7 [62:60] */
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_5_CPCP_FOR_RV1_TC7_MASK 0x0000000070000000
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_5_CPCP_FOR_RV1_TC7_SHIFT 60
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_5_CPCP_FOR_RV1_TC7_DEFAULT 0x0000000000000007
-
-/* SWITCH_CORE :: PN_EGRESS_PKT_TC2CPCP_MAP_Port_5 :: SWITCH_RESV_14 [59:59] */
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_5_SWITCH_RESV_14_MASK 0x0000000008000000
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_5_SWITCH_RESV_14_SHIFT 59
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_5_SWITCH_RESV_14_DEFAULT 0x0000000000000000
-
-/* SWITCH_CORE :: PN_EGRESS_PKT_TC2CPCP_MAP_Port_5 :: CPCP_FOR_RV1_TC6 [58:56] */
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_5_CPCP_FOR_RV1_TC6_MASK 0x0000000007000000
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_5_CPCP_FOR_RV1_TC6_SHIFT 56
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_5_CPCP_FOR_RV1_TC6_DEFAULT 0x0000000000000006
-
-/* SWITCH_CORE :: PN_EGRESS_PKT_TC2CPCP_MAP_Port_5 :: SWITCH_RESV_13 [55:55] */
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_5_SWITCH_RESV_13_MASK 0x0000000000800000
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_5_SWITCH_RESV_13_SHIFT 55
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_5_SWITCH_RESV_13_DEFAULT 0x0000000000000000
-
-/* SWITCH_CORE :: PN_EGRESS_PKT_TC2CPCP_MAP_Port_5 :: CPCP_FOR_RV1_TC5 [54:52] */
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_5_CPCP_FOR_RV1_TC5_MASK 0x0000000000700000
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_5_CPCP_FOR_RV1_TC5_SHIFT 52
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_5_CPCP_FOR_RV1_TC5_DEFAULT 0x0000000000000005
-
-/* SWITCH_CORE :: PN_EGRESS_PKT_TC2CPCP_MAP_Port_5 :: SWITCH_RESV_12 [51:51] */
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_5_SWITCH_RESV_12_MASK 0x0000000000080000
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_5_SWITCH_RESV_12_SHIFT 51
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_5_SWITCH_RESV_12_DEFAULT 0x0000000000000000
-
-/* SWITCH_CORE :: PN_EGRESS_PKT_TC2CPCP_MAP_Port_5 :: CPCP_FOR_RV1_TC4 [50:48] */
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_5_CPCP_FOR_RV1_TC4_MASK 0x0000000000070000
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_5_CPCP_FOR_RV1_TC4_SHIFT 48
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_5_CPCP_FOR_RV1_TC4_DEFAULT 0x0000000000000004
-
-/* SWITCH_CORE :: PN_EGRESS_PKT_TC2CPCP_MAP_Port_5 :: SWITCH_RESV_11 [47:47] */
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_5_SWITCH_RESV_11_MASK 0x0000000000008000
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_5_SWITCH_RESV_11_SHIFT 47
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_5_SWITCH_RESV_11_DEFAULT 0x0000000000000000
-
-/* SWITCH_CORE :: PN_EGRESS_PKT_TC2CPCP_MAP_Port_5 :: CPCP_FOR_RV1_TC3 [46:44] */
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_5_CPCP_FOR_RV1_TC3_MASK 0x0000000000007000
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_5_CPCP_FOR_RV1_TC3_SHIFT 44
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_5_CPCP_FOR_RV1_TC3_DEFAULT 0x0000000000000003
-
-/* SWITCH_CORE :: PN_EGRESS_PKT_TC2CPCP_MAP_Port_5 :: SWITCH_RESV_10 [43:43] */
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_5_SWITCH_RESV_10_MASK 0x0000000000000800
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_5_SWITCH_RESV_10_SHIFT 43
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_5_SWITCH_RESV_10_DEFAULT 0x0000000000000000
-
-/* SWITCH_CORE :: PN_EGRESS_PKT_TC2CPCP_MAP_Port_5 :: CPCP_FOR_RV1_TC2 [42:40] */
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_5_CPCP_FOR_RV1_TC2_MASK 0x0000000000000700
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_5_CPCP_FOR_RV1_TC2_SHIFT 40
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_5_CPCP_FOR_RV1_TC2_DEFAULT 0x0000000000000002
-
-/* SWITCH_CORE :: PN_EGRESS_PKT_TC2CPCP_MAP_Port_5 :: SWITCH_RESV_9 [39:39] */
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_5_SWITCH_RESV_9_MASK 0x0000000000000080
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_5_SWITCH_RESV_9_SHIFT 39
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_5_SWITCH_RESV_9_DEFAULT 0x0000000000000000
-
-/* SWITCH_CORE :: PN_EGRESS_PKT_TC2CPCP_MAP_Port_5 :: CPCP_FOR_RV1_TC1 [38:36] */
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_5_CPCP_FOR_RV1_TC1_MASK 0x0000000000000070
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_5_CPCP_FOR_RV1_TC1_SHIFT 36
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_5_CPCP_FOR_RV1_TC1_DEFAULT 0x0000000000000001
-
-/* SWITCH_CORE :: PN_EGRESS_PKT_TC2CPCP_MAP_Port_5 :: SWITCH_RESV_8 [35:35] */
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_5_SWITCH_RESV_8_MASK 0x0000000000000008
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_5_SWITCH_RESV_8_SHIFT 35
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_5_SWITCH_RESV_8_DEFAULT 0x0000000000000000
-
-/* SWITCH_CORE :: PN_EGRESS_PKT_TC2CPCP_MAP_Port_5 :: CPCP_FOR_RV1_TC0 [34:32] */
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_5_CPCP_FOR_RV1_TC0_MASK 0x0000000000000007
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_5_CPCP_FOR_RV1_TC0_SHIFT 32
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_5_CPCP_FOR_RV1_TC0_DEFAULT 0x0000000000000000
-
-/* SWITCH_CORE :: PN_EGRESS_PKT_TC2CPCP_MAP_Port_5 :: SWITCH_RESV_7 [31:31] */
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_5_SWITCH_RESV_7_MASK 0x0000000080000000
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_5_SWITCH_RESV_7_SHIFT 31
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_5_SWITCH_RESV_7_DEFAULT 0x0000000000000000
-
-/* SWITCH_CORE :: PN_EGRESS_PKT_TC2CPCP_MAP_Port_5 :: CPCP_FOR_RV0_TC7 [30:28] */
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_5_CPCP_FOR_RV0_TC7_MASK 0x0000000070000000
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_5_CPCP_FOR_RV0_TC7_SHIFT 28
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_5_CPCP_FOR_RV0_TC7_DEFAULT 0x0000000000000007
-
-/* SWITCH_CORE :: PN_EGRESS_PKT_TC2CPCP_MAP_Port_5 :: SWITCH_RESV_6 [27:27] */
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_5_SWITCH_RESV_6_MASK 0x0000000008000000
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_5_SWITCH_RESV_6_SHIFT 27
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_5_SWITCH_RESV_6_DEFAULT 0x0000000000000000
-
-/* SWITCH_CORE :: PN_EGRESS_PKT_TC2CPCP_MAP_Port_5 :: CPCP_FOR_RV0_TC6 [26:24] */
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_5_CPCP_FOR_RV0_TC6_MASK 0x0000000007000000
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_5_CPCP_FOR_RV0_TC6_SHIFT 24
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_5_CPCP_FOR_RV0_TC6_DEFAULT 0x0000000000000006
-
-/* SWITCH_CORE :: PN_EGRESS_PKT_TC2CPCP_MAP_Port_5 :: SWITCH_RESV_5 [23:23] */
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_5_SWITCH_RESV_5_MASK 0x0000000000800000
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_5_SWITCH_RESV_5_SHIFT 23
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_5_SWITCH_RESV_5_DEFAULT 0x0000000000000000
-
-/* SWITCH_CORE :: PN_EGRESS_PKT_TC2CPCP_MAP_Port_5 :: CPCP_FOR_RV0_TC5 [22:20] */
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_5_CPCP_FOR_RV0_TC5_MASK 0x0000000000700000
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_5_CPCP_FOR_RV0_TC5_SHIFT 20
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_5_CPCP_FOR_RV0_TC5_DEFAULT 0x0000000000000005
-
-/* SWITCH_CORE :: PN_EGRESS_PKT_TC2CPCP_MAP_Port_5 :: SWITCH_RESV_4 [19:19] */
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_5_SWITCH_RESV_4_MASK 0x0000000000080000
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_5_SWITCH_RESV_4_SHIFT 19
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_5_SWITCH_RESV_4_DEFAULT 0x0000000000000000
-
-/* SWITCH_CORE :: PN_EGRESS_PKT_TC2CPCP_MAP_Port_5 :: CPCP_FOR_RV0_TC4 [18:16] */
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_5_CPCP_FOR_RV0_TC4_MASK 0x0000000000070000
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_5_CPCP_FOR_RV0_TC4_SHIFT 16
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_5_CPCP_FOR_RV0_TC4_DEFAULT 0x0000000000000004
-
-/* SWITCH_CORE :: PN_EGRESS_PKT_TC2CPCP_MAP_Port_5 :: SWITCH_RESV_3 [15:15] */
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_5_SWITCH_RESV_3_MASK 0x0000000000008000
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_5_SWITCH_RESV_3_SHIFT 15
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_5_SWITCH_RESV_3_DEFAULT 0x0000000000000000
-
-/* SWITCH_CORE :: PN_EGRESS_PKT_TC2CPCP_MAP_Port_5 :: CPCP_FOR_RV0_TC3 [14:12] */
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_5_CPCP_FOR_RV0_TC3_MASK 0x0000000000007000
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_5_CPCP_FOR_RV0_TC3_SHIFT 12
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_5_CPCP_FOR_RV0_TC3_DEFAULT 0x0000000000000003
-
-/* SWITCH_CORE :: PN_EGRESS_PKT_TC2CPCP_MAP_Port_5 :: SWITCH_RESV_2 [11:11] */
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_5_SWITCH_RESV_2_MASK 0x0000000000000800
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_5_SWITCH_RESV_2_SHIFT 11
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_5_SWITCH_RESV_2_DEFAULT 0x0000000000000000
-
-/* SWITCH_CORE :: PN_EGRESS_PKT_TC2CPCP_MAP_Port_5 :: CPCP_FOR_RV0_TC2 [10:08] */
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_5_CPCP_FOR_RV0_TC2_MASK 0x0000000000000700
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_5_CPCP_FOR_RV0_TC2_SHIFT 8
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_5_CPCP_FOR_RV0_TC2_DEFAULT 0x0000000000000002
-
-/* SWITCH_CORE :: PN_EGRESS_PKT_TC2CPCP_MAP_Port_5 :: SWITCH_RESV_1 [07:07] */
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_5_SWITCH_RESV_1_MASK 0x0000000000000080
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_5_SWITCH_RESV_1_SHIFT 7
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_5_SWITCH_RESV_1_DEFAULT 0x0000000000000000
-
-/* SWITCH_CORE :: PN_EGRESS_PKT_TC2CPCP_MAP_Port_5 :: CPCP_FOR_RV0_TC1 [06:04] */
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_5_CPCP_FOR_RV0_TC1_MASK 0x0000000000000070
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_5_CPCP_FOR_RV0_TC1_SHIFT 4
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_5_CPCP_FOR_RV0_TC1_DEFAULT 0x0000000000000001
-
-/* SWITCH_CORE :: PN_EGRESS_PKT_TC2CPCP_MAP_Port_5 :: SWITCH_RESV_0 [03:03] */
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_5_SWITCH_RESV_0_MASK 0x0000000000000008
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_5_SWITCH_RESV_0_SHIFT 3
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_5_SWITCH_RESV_0_DEFAULT 0x0000000000000000
-
-/* SWITCH_CORE :: PN_EGRESS_PKT_TC2CPCP_MAP_Port_5 :: CPCP_FOR_RV0_TC0 [02:00] */
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_5_CPCP_FOR_RV0_TC0_MASK 0x0000000000000007
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_5_CPCP_FOR_RV0_TC0_SHIFT 0
-#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_5_CPCP_FOR_RV0_TC0_DEFAULT 0x0000000000000000
-
-/***************************************************************************
- *P7_EGRESS_PKT_TC2CPCP_MAP - Port 7, Egress TC to CPCP mapping Register
- ***************************************************************************/
-/* SWITCH_CORE :: P7_EGRESS_PKT_TC2CPCP_MAP :: SWITCH_RESV_15 [63:63] */
-#define BCHP_SWITCH_CORE_P7_EGRESS_PKT_TC2CPCP_MAP_SWITCH_RESV_15_MASK 0x0000000080000000
-#define BCHP_SWITCH_CORE_P7_EGRESS_PKT_TC2CPCP_MAP_SWITCH_RESV_15_SHIFT 63
-#define BCHP_SWITCH_CORE_P7_EGRESS_PKT_TC2CPCP_MAP_SWITCH_RESV_15_DEFAULT 0x0000000000000000
-
-/* SWITCH_CORE :: P7_EGRESS_PKT_TC2CPCP_MAP :: CPCP_FOR_RV1_TC7 [62:60] */
-#define BCHP_SWITCH_CORE_P7_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC7_MASK 0x0000000070000000
-#define BCHP_SWITCH_CORE_P7_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC7_SHIFT 60
-#define BCHP_SWITCH_CORE_P7_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC7_DEFAULT 0x0000000000000007
-
-/* SWITCH_CORE :: P7_EGRESS_PKT_TC2CPCP_MAP :: SWITCH_RESV_14 [59:59] */
-#define BCHP_SWITCH_CORE_P7_EGRESS_PKT_TC2CPCP_MAP_SWITCH_RESV_14_MASK 0x0000000008000000
-#define BCHP_SWITCH_CORE_P7_EGRESS_PKT_TC2CPCP_MAP_SWITCH_RESV_14_SHIFT 59
-#define BCHP_SWITCH_CORE_P7_EGRESS_PKT_TC2CPCP_MAP_SWITCH_RESV_14_DEFAULT 0x0000000000000000
-
-/* SWITCH_CORE :: P7_EGRESS_PKT_TC2CPCP_MAP :: CPCP_FOR_RV1_TC6 [58:56] */
-#define BCHP_SWITCH_CORE_P7_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC6_MASK 0x0000000007000000
-#define BCHP_SWITCH_CORE_P7_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC6_SHIFT 56
-#define BCHP_SWITCH_CORE_P7_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC6_DEFAULT 0x0000000000000006
-
-/* SWITCH_CORE :: P7_EGRESS_PKT_TC2CPCP_MAP :: SWITCH_RESV_13 [55:55] */
-#define BCHP_SWITCH_CORE_P7_EGRESS_PKT_TC2CPCP_MAP_SWITCH_RESV_13_MASK 0x0000000000800000
-#define BCHP_SWITCH_CORE_P7_EGRESS_PKT_TC2CPCP_MAP_SWITCH_RESV_13_SHIFT 55
-#define BCHP_SWITCH_CORE_P7_EGRESS_PKT_TC2CPCP_MAP_SWITCH_RESV_13_DEFAULT 0x0000000000000000
-
-/* SWITCH_CORE :: P7_EGRESS_PKT_TC2CPCP_MAP :: CPCP_FOR_RV1_TC5 [54:52] */
-#define BCHP_SWITCH_CORE_P7_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC5_MASK 0x0000000000700000
-#define BCHP_SWITCH_CORE_P7_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC5_SHIFT 52
-#define BCHP_SWITCH_CORE_P7_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC5_DEFAULT 0x0000000000000005
-
-/* SWITCH_CORE :: P7_EGRESS_PKT_TC2CPCP_MAP :: SWITCH_RESV_12 [51:51] */
-#define BCHP_SWITCH_CORE_P7_EGRESS_PKT_TC2CPCP_MAP_SWITCH_RESV_12_MASK 0x0000000000080000
-#define BCHP_SWITCH_CORE_P7_EGRESS_PKT_TC2CPCP_MAP_SWITCH_RESV_12_SHIFT 51
-#define BCHP_SWITCH_CORE_P7_EGRESS_PKT_TC2CPCP_MAP_SWITCH_RESV_12_DEFAULT 0x0000000000000000
-
-/* SWITCH_CORE :: P7_EGRESS_PKT_TC2CPCP_MAP :: CPCP_FOR_RV1_TC4 [50:48] */
-#define BCHP_SWITCH_CORE_P7_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC4_MASK 0x0000000000070000
-#define BCHP_SWITCH_CORE_P7_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC4_SHIFT 48
-#define BCHP_SWITCH_CORE_P7_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC4_DEFAULT 0x0000000000000004
-
-/* SWITCH_CORE :: P7_EGRESS_PKT_TC2CPCP_MAP :: SWITCH_RESV_11 [47:47] */
-#define BCHP_SWITCH_CORE_P7_EGRESS_PKT_TC2CPCP_MAP_SWITCH_RESV_11_MASK 0x0000000000008000
-#define BCHP_SWITCH_CORE_P7_EGRESS_PKT_TC2CPCP_MAP_SWITCH_RESV_11_SHIFT 47
-#define BCHP_SWITCH_CORE_P7_EGRESS_PKT_TC2CPCP_MAP_SWITCH_RESV_11_DEFAULT 0x0000000000000000
-
-/* SWITCH_CORE :: P7_EGRESS_PKT_TC2CPCP_MAP :: CPCP_FOR_RV1_TC3 [46:44] */
-#define BCHP_SWITCH_CORE_P7_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC3_MASK 0x0000000000007000
-#define BCHP_SWITCH_CORE_P7_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC3_SHIFT 44
-#define BCHP_SWITCH_CORE_P7_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC3_DEFAULT 0x0000000000000003
-
-/* SWITCH_CORE :: P7_EGRESS_PKT_TC2CPCP_MAP :: SWITCH_RESV_10 [43:43] */
-#define BCHP_SWITCH_CORE_P7_EGRESS_PKT_TC2CPCP_MAP_SWITCH_RESV_10_MASK 0x0000000000000800
-#define BCHP_SWITCH_CORE_P7_EGRESS_PKT_TC2CPCP_MAP_SWITCH_RESV_10_SHIFT 43
-#define BCHP_SWITCH_CORE_P7_EGRESS_PKT_TC2CPCP_MAP_SWITCH_RESV_10_DEFAULT 0x0000000000000000
-
-/* SWITCH_CORE :: P7_EGRESS_PKT_TC2CPCP_MAP :: CPCP_FOR_RV1_TC2 [42:40] */
-#define BCHP_SWITCH_CORE_P7_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC2_MASK 0x0000000000000700
-#define BCHP_SWITCH_CORE_P7_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC2_SHIFT 40
-#define BCHP_SWITCH_CORE_P7_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC2_DEFAULT 0x0000000000000002
-
-/* SWITCH_CORE :: P7_EGRESS_PKT_TC2CPCP_MAP :: SWITCH_RESV_9 [39:39] */
-#define BCHP_SWITCH_CORE_P7_EGRESS_PKT_TC2CPCP_MAP_SWITCH_RESV_9_MASK 0x0000000000000080
-#define BCHP_SWITCH_CORE_P7_EGRESS_PKT_TC2CPCP_MAP_SWITCH_RESV_9_SHIFT 39
-#define BCHP_SWITCH_CORE_P7_EGRESS_PKT_TC2CPCP_MAP_SWITCH_RESV_9_DEFAULT 0x0000000000000000
-
-/* SWITCH_CORE :: P7_EGRESS_PKT_TC2CPCP_MAP :: CPCP_FOR_RV1_TC1 [38:36] */
-#define BCHP_SWITCH_CORE_P7_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC1_MASK 0x0000000000000070
-#define BCHP_SWITCH_CORE_P7_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC1_SHIFT 36
-#define BCHP_SWITCH_CORE_P7_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC1_DEFAULT 0x0000000000000001
-
-/* SWITCH_CORE :: P7_EGRESS_PKT_TC2CPCP_MAP :: SWITCH_RESV_8 [35:35] */
-#define BCHP_SWITCH_CORE_P7_EGRESS_PKT_TC2CPCP_MAP_SWITCH_RESV_8_MASK 0x0000000000000008
-#define BCHP_SWITCH_CORE_P7_EGRESS_PKT_TC2CPCP_MAP_SWITCH_RESV_8_SHIFT 35
-#define BCHP_SWITCH_CORE_P7_EGRESS_PKT_TC2CPCP_MAP_SWITCH_RESV_8_DEFAULT 0x0000000000000000
-
-/* SWITCH_CORE :: P7_EGRESS_PKT_TC2CPCP_MAP :: CPCP_FOR_RV1_TC0 [34:32] */
-#define BCHP_SWITCH_CORE_P7_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC0_MASK 0x0000000000000007
-#define BCHP_SWITCH_CORE_P7_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC0_SHIFT 32
-#define BCHP_SWITCH_CORE_P7_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC0_DEFAULT 0x0000000000000000
-
-/* SWITCH_CORE :: P7_EGRESS_PKT_TC2CPCP_MAP :: SWITCH_RESV_7 [31:31] */
-#define BCHP_SWITCH_CORE_P7_EGRESS_PKT_TC2CPCP_MAP_SWITCH_RESV_7_MASK 0x0000000080000000
-#define BCHP_SWITCH_CORE_P7_EGRESS_PKT_TC2CPCP_MAP_SWITCH_RESV_7_SHIFT 31
-#define BCHP_SWITCH_CORE_P7_EGRESS_PKT_TC2CPCP_MAP_SWITCH_RESV_7_DEFAULT 0x0000000000000000
-
-/* SWITCH_CORE :: P7_EGRESS_PKT_TC2CPCP_MAP :: CPCP_FOR_RV0_TC7 [30:28] */
-#define BCHP_SWITCH_CORE_P7_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC7_MASK 0x0000000070000000
-#define BCHP_SWITCH_CORE_P7_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC7_SHIFT 28
-#define BCHP_SWITCH_CORE_P7_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC7_DEFAULT 0x0000000000000007
-
-/* SWITCH_CORE :: P7_EGRESS_PKT_TC2CPCP_MAP :: SWITCH_RESV_6 [27:27] */
-#define BCHP_SWITCH_CORE_P7_EGRESS_PKT_TC2CPCP_MAP_SWITCH_RESV_6_MASK 0x0000000008000000
-#define BCHP_SWITCH_CORE_P7_EGRESS_PKT_TC2CPCP_MAP_SWITCH_RESV_6_SHIFT 27
-#define BCHP_SWITCH_CORE_P7_EGRESS_PKT_TC2CPCP_MAP_SWITCH_RESV_6_DEFAULT 0x0000000000000000
-
-/* SWITCH_CORE :: P7_EGRESS_PKT_TC2CPCP_MAP :: CPCP_FOR_RV0_TC6 [26:24] */
-#define BCHP_SWITCH_CORE_P7_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC6_MASK 0x0000000007000000
-#define BCHP_SWITCH_CORE_P7_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC6_SHIFT 24
-#define BCHP_SWITCH_CORE_P7_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC6_DEFAULT 0x0000000000000006
-
-/* SWITCH_CORE :: P7_EGRESS_PKT_TC2CPCP_MAP :: SWITCH_RESV_5 [23:23] */
-#define BCHP_SWITCH_CORE_P7_EGRESS_PKT_TC2CPCP_MAP_SWITCH_RESV_5_MASK 0x0000000000800000
-#define BCHP_SWITCH_CORE_P7_EGRESS_PKT_TC2CPCP_MAP_SWITCH_RESV_5_SHIFT 23
-#define BCHP_SWITCH_CORE_P7_EGRESS_PKT_TC2CPCP_MAP_SWITCH_RESV_5_DEFAULT 0x0000000000000000
-
-/* SWITCH_CORE :: P7_EGRESS_PKT_TC2CPCP_MAP :: CPCP_FOR_RV0_TC5 [22:20] */
-#define BCHP_SWITCH_CORE_P7_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC5_MASK 0x0000000000700000
-#define BCHP_SWITCH_CORE_P7_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC5_SHIFT 20
-#define BCHP_SWITCH_CORE_P7_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC5_DEFAULT 0x0000000000000005
-
-/* SWITCH_CORE :: P7_EGRESS_PKT_TC2CPCP_MAP :: SWITCH_RESV_4 [19:19] */
-#define BCHP_SWITCH_CORE_P7_EGRESS_PKT_TC2CPCP_MAP_SWITCH_RESV_4_MASK 0x0000000000080000
-#define BCHP_SWITCH_CORE_P7_EGRESS_PKT_TC2CPCP_MAP_SWITCH_RESV_4_SHIFT 19
-#define BCHP_SWITCH_CORE_P7_EGRESS_PKT_TC2CPCP_MAP_SWITCH_RESV_4_DEFAULT 0x0000000000000000
-
-/* SWITCH_CORE :: P7_EGRESS_PKT_TC2CPCP_MAP :: CPCP_FOR_RV0_TC4 [18:16] */
-#define BCHP_SWITCH_CORE_P7_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC4_MASK 0x0000000000070000
-#define BCHP_SWITCH_CORE_P7_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC4_SHIFT 16
-#define BCHP_SWITCH_CORE_P7_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC4_DEFAULT 0x0000000000000004
-
-/* SWITCH_CORE :: P7_EGRESS_PKT_TC2CPCP_MAP :: SWITCH_RESV_3 [15:15] */
-#define BCHP_SWITCH_CORE_P7_EGRESS_PKT_TC2CPCP_MAP_SWITCH_RESV_3_MASK 0x0000000000008000
-#define BCHP_SWITCH_CORE_P7_EGRESS_PKT_TC2CPCP_MAP_SWITCH_RESV_3_SHIFT 15
-#define BCHP_SWITCH_CORE_P7_EGRESS_PKT_TC2CPCP_MAP_SWITCH_RESV_3_DEFAULT 0x0000000000000000
-
-/* SWITCH_CORE :: P7_EGRESS_PKT_TC2CPCP_MAP :: CPCP_FOR_RV0_TC3 [14:12] */
-#define BCHP_SWITCH_CORE_P7_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC3_MASK 0x0000000000007000
-#define BCHP_SWITCH_CORE_P7_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC3_SHIFT 12
-#define BCHP_SWITCH_CORE_P7_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC3_DEFAULT 0x0000000000000003
-
-/* SWITCH_CORE :: P7_EGRESS_PKT_TC2CPCP_MAP :: SWITCH_RESV_2 [11:11] */
-#define BCHP_SWITCH_CORE_P7_EGRESS_PKT_TC2CPCP_MAP_SWITCH_RESV_2_MASK 0x0000000000000800
-#define BCHP_SWITCH_CORE_P7_EGRESS_PKT_TC2CPCP_MAP_SWITCH_RESV_2_SHIFT 11
-#define BCHP_SWITCH_CORE_P7_EGRESS_PKT_TC2CPCP_MAP_SWITCH_RESV_2_DEFAULT 0x0000000000000000
-
-/* SWITCH_CORE :: P7_EGRESS_PKT_TC2CPCP_MAP :: CPCP_FOR_RV0_TC2 [10:08] */
-#define BCHP_SWITCH_CORE_P7_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC2_MASK 0x0000000000000700
-#define BCHP_SWITCH_CORE_P7_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC2_SHIFT 8
-#define BCHP_SWITCH_CORE_P7_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC2_DEFAULT 0x0000000000000002
-
-/* SWITCH_CORE :: P7_EGRESS_PKT_TC2CPCP_MAP :: SWITCH_RESV_1 [07:07] */
-#define BCHP_SWITCH_CORE_P7_EGRESS_PKT_TC2CPCP_MAP_SWITCH_RESV_1_MASK 0x0000000000000080
-#define BCHP_SWITCH_CORE_P7_EGRESS_PKT_TC2CPCP_MAP_SWITCH_RESV_1_SHIFT 7
-#define BCHP_SWITCH_CORE_P7_EGRESS_PKT_TC2CPCP_MAP_SWITCH_RESV_1_DEFAULT 0x0000000000000000
-
-/* SWITCH_CORE :: P7_EGRESS_PKT_TC2CPCP_MAP :: CPCP_FOR_RV0_TC1 [06:04] */
-#define BCHP_SWITCH_CORE_P7_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC1_MASK 0x0000000000000070
-#define BCHP_SWITCH_CORE_P7_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC1_SHIFT 4
-#define BCHP_SWITCH_CORE_P7_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC1_DEFAULT 0x0000000000000001
-
-/* SWITCH_CORE :: P7_EGRESS_PKT_TC2CPCP_MAP :: SWITCH_RESV_0 [03:03] */
-#define BCHP_SWITCH_CORE_P7_EGRESS_PKT_TC2CPCP_MAP_SWITCH_RESV_0_MASK 0x0000000000000008
-#define BCHP_SWITCH_CORE_P7_EGRESS_PKT_TC2CPCP_MAP_SWITCH_RESV_0_SHIFT 3
-#define BCHP_SWITCH_CORE_P7_EGRESS_PKT_TC2CPCP_MAP_SWITCH_RESV_0_DEFAULT 0x0000000000000000
-
-/* SWITCH_CORE :: P7_EGRESS_PKT_TC2CPCP_MAP :: CPCP_FOR_RV0_TC0 [02:00] */
-#define BCHP_SWITCH_CORE_P7_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC0_MASK 0x0000000000000007
-#define BCHP_SWITCH_CORE_P7_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC0_SHIFT 0
-#define BCHP_SWITCH_CORE_P7_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC0_DEFAULT 0x0000000000000000
-
-/***************************************************************************
- *IMP_EGRESS_PKT_TC2CPCP_MAP - Port 8, Egress TC to CPCP mapping Register
- ***************************************************************************/
-/* SWITCH_CORE :: IMP_EGRESS_PKT_TC2CPCP_MAP :: SWITCH_RESV_15 [63:63] */
-#define BCHP_SWITCH_CORE_IMP_EGRESS_PKT_TC2CPCP_MAP_SWITCH_RESV_15_MASK 0x0000000080000000
-#define BCHP_SWITCH_CORE_IMP_EGRESS_PKT_TC2CPCP_MAP_SWITCH_RESV_15_SHIFT 63
-#define BCHP_SWITCH_CORE_IMP_EGRESS_PKT_TC2CPCP_MAP_SWITCH_RESV_15_DEFAULT 0x0000000000000000
-
-/* SWITCH_CORE :: IMP_EGRESS_PKT_TC2CPCP_MAP :: CPCP_FOR_RV1_TC7 [62:60] */
-#define BCHP_SWITCH_CORE_IMP_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC7_MASK 0x0000000070000000
-#define BCHP_SWITCH_CORE_IMP_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC7_SHIFT 60
-#define BCHP_SWITCH_CORE_IMP_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC7_DEFAULT 0x0000000000000007
-
-/* SWITCH_CORE :: IMP_EGRESS_PKT_TC2CPCP_MAP :: SWITCH_RESV_14 [59:59] */
-#define BCHP_SWITCH_CORE_IMP_EGRESS_PKT_TC2CPCP_MAP_SWITCH_RESV_14_MASK 0x0000000008000000
-#define BCHP_SWITCH_CORE_IMP_EGRESS_PKT_TC2CPCP_MAP_SWITCH_RESV_14_SHIFT 59
-#define BCHP_SWITCH_CORE_IMP_EGRESS_PKT_TC2CPCP_MAP_SWITCH_RESV_14_DEFAULT 0x0000000000000000
-
-/* SWITCH_CORE :: IMP_EGRESS_PKT_TC2CPCP_MAP :: CPCP_FOR_RV1_TC6 [58:56] */
-#define BCHP_SWITCH_CORE_IMP_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC6_MASK 0x0000000007000000
-#define BCHP_SWITCH_CORE_IMP_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC6_SHIFT 56
-#define BCHP_SWITCH_CORE_IMP_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC6_DEFAULT 0x0000000000000006
-
-/* SWITCH_CORE :: IMP_EGRESS_PKT_TC2CPCP_MAP :: SWITCH_RESV_13 [55:55] */
-#define BCHP_SWITCH_CORE_IMP_EGRESS_PKT_TC2CPCP_MAP_SWITCH_RESV_13_MASK 0x0000000000800000
-#define BCHP_SWITCH_CORE_IMP_EGRESS_PKT_TC2CPCP_MAP_SWITCH_RESV_13_SHIFT 55
-#define BCHP_SWITCH_CORE_IMP_EGRESS_PKT_TC2CPCP_MAP_SWITCH_RESV_13_DEFAULT 0x0000000000000000
-
-/* SWITCH_CORE :: IMP_EGRESS_PKT_TC2CPCP_MAP :: CPCP_FOR_RV1_TC5 [54:52] */
-#define BCHP_SWITCH_CORE_IMP_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC5_MASK 0x0000000000700000
-#define BCHP_SWITCH_CORE_IMP_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC5_SHIFT 52
-#define BCHP_SWITCH_CORE_IMP_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC5_DEFAULT 0x0000000000000005
-
-/* SWITCH_CORE :: IMP_EGRESS_PKT_TC2CPCP_MAP :: SWITCH_RESV_12 [51:51] */
-#define BCHP_SWITCH_CORE_IMP_EGRESS_PKT_TC2CPCP_MAP_SWITCH_RESV_12_MASK 0x0000000000080000
-#define BCHP_SWITCH_CORE_IMP_EGRESS_PKT_TC2CPCP_MAP_SWITCH_RESV_12_SHIFT 51
-#define BCHP_SWITCH_CORE_IMP_EGRESS_PKT_TC2CPCP_MAP_SWITCH_RESV_12_DEFAULT 0x0000000000000000
-
-/* SWITCH_CORE :: IMP_EGRESS_PKT_TC2CPCP_MAP :: CPCP_FOR_RV1_TC4 [50:48] */
-#define BCHP_SWITCH_CORE_IMP_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC4_MASK 0x0000000000070000
-#define BCHP_SWITCH_CORE_IMP_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC4_SHIFT 48
-#define BCHP_SWITCH_CORE_IMP_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC4_DEFAULT 0x0000000000000004
-
-/* SWITCH_CORE :: IMP_EGRESS_PKT_TC2CPCP_MAP :: SWITCH_RESV_11 [47:47] */
-#define BCHP_SWITCH_CORE_IMP_EGRESS_PKT_TC2CPCP_MAP_SWITCH_RESV_11_MASK 0x0000000000008000
-#define BCHP_SWITCH_CORE_IMP_EGRESS_PKT_TC2CPCP_MAP_SWITCH_RESV_11_SHIFT 47
-#define BCHP_SWITCH_CORE_IMP_EGRESS_PKT_TC2CPCP_MAP_SWITCH_RESV_11_DEFAULT 0x0000000000000000
-
-/* SWITCH_CORE :: IMP_EGRESS_PKT_TC2CPCP_MAP :: CPCP_FOR_RV1_TC3 [46:44] */
-#define BCHP_SWITCH_CORE_IMP_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC3_MASK 0x0000000000007000
-#define BCHP_SWITCH_CORE_IMP_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC3_SHIFT 44
-#define BCHP_SWITCH_CORE_IMP_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC3_DEFAULT 0x0000000000000003
-
-/* SWITCH_CORE :: IMP_EGRESS_PKT_TC2CPCP_MAP :: SWITCH_RESV_10 [43:43] */
-#define BCHP_SWITCH_CORE_IMP_EGRESS_PKT_TC2CPCP_MAP_SWITCH_RESV_10_MASK 0x0000000000000800
-#define BCHP_SWITCH_CORE_IMP_EGRESS_PKT_TC2CPCP_MAP_SWITCH_RESV_10_SHIFT 43
-#define BCHP_SWITCH_CORE_IMP_EGRESS_PKT_TC2CPCP_MAP_SWITCH_RESV_10_DEFAULT 0x0000000000000000
-
-/* SWITCH_CORE :: IMP_EGRESS_PKT_TC2CPCP_MAP :: CPCP_FOR_RV1_TC2 [42:40] */
-#define BCHP_SWITCH_CORE_IMP_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC2_MASK 0x0000000000000700
-#define BCHP_SWITCH_CORE_IMP_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC2_SHIFT 40
-#define BCHP_SWITCH_CORE_IMP_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC2_DEFAULT 0x0000000000000002
-
-/* SWITCH_CORE :: IMP_EGRESS_PKT_TC2CPCP_MAP :: SWITCH_RESV_9 [39:39] */
-#define BCHP_SWITCH_CORE_IMP_EGRESS_PKT_TC2CPCP_MAP_SWITCH_RESV_9_MASK 0x0000000000000080
-#define BCHP_SWITCH_CORE_IMP_EGRESS_PKT_TC2CPCP_MAP_SWITCH_RESV_9_SHIFT 39
-#define BCHP_SWITCH_CORE_IMP_EGRESS_PKT_TC2CPCP_MAP_SWITCH_RESV_9_DEFAULT 0x0000000000000000
-
-/* SWITCH_CORE :: IMP_EGRESS_PKT_TC2CPCP_MAP :: CPCP_FOR_RV1_TC1 [38:36] */
-#define BCHP_SWITCH_CORE_IMP_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC1_MASK 0x0000000000000070
-#define BCHP_SWITCH_CORE_IMP_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC1_SHIFT 36
-#define BCHP_SWITCH_CORE_IMP_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC1_DEFAULT 0x0000000000000001
-
-/* SWITCH_CORE :: IMP_EGRESS_PKT_TC2CPCP_MAP :: SWITCH_RESV_8 [35:35] */
-#define BCHP_SWITCH_CORE_IMP_EGRESS_PKT_TC2CPCP_MAP_SWITCH_RESV_8_MASK 0x0000000000000008
-#define BCHP_SWITCH_CORE_IMP_EGRESS_PKT_TC2CPCP_MAP_SWITCH_RESV_8_SHIFT 35
-#define BCHP_SWITCH_CORE_IMP_EGRESS_PKT_TC2CPCP_MAP_SWITCH_RESV_8_DEFAULT 0x0000000000000000
-
-/* SWITCH_CORE :: IMP_EGRESS_PKT_TC2CPCP_MAP :: CPCP_FOR_RV1_TC0 [34:32] */
-#define BCHP_SWITCH_CORE_IMP_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC0_MASK 0x0000000000000007
-#define BCHP_SWITCH_CORE_IMP_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC0_SHIFT 32
-#define BCHP_SWITCH_CORE_IMP_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC0_DEFAULT 0x0000000000000000
-
-/* SWITCH_CORE :: IMP_EGRESS_PKT_TC2CPCP_MAP :: SWITCH_RESV_7 [31:31] */
-#define BCHP_SWITCH_CORE_IMP_EGRESS_PKT_TC2CPCP_MAP_SWITCH_RESV_7_MASK 0x0000000080000000
-#define BCHP_SWITCH_CORE_IMP_EGRESS_PKT_TC2CPCP_MAP_SWITCH_RESV_7_SHIFT 31
-#define BCHP_SWITCH_CORE_IMP_EGRESS_PKT_TC2CPCP_MAP_SWITCH_RESV_7_DEFAULT 0x0000000000000000
-
-/* SWITCH_CORE :: IMP_EGRESS_PKT_TC2CPCP_MAP :: CPCP_FOR_RV0_TC7 [30:28] */
-#define BCHP_SWITCH_CORE_IMP_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC7_MASK 0x0000000070000000
-#define BCHP_SWITCH_CORE_IMP_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC7_SHIFT 28
-#define BCHP_SWITCH_CORE_IMP_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC7_DEFAULT 0x0000000000000007
-
-/* SWITCH_CORE :: IMP_EGRESS_PKT_TC2CPCP_MAP :: SWITCH_RESV_6 [27:27] */
-#define BCHP_SWITCH_CORE_IMP_EGRESS_PKT_TC2CPCP_MAP_SWITCH_RESV_6_MASK 0x0000000008000000
-#define BCHP_SWITCH_CORE_IMP_EGRESS_PKT_TC2CPCP_MAP_SWITCH_RESV_6_SHIFT 27
-#define BCHP_SWITCH_CORE_IMP_EGRESS_PKT_TC2CPCP_MAP_SWITCH_RESV_6_DEFAULT 0x0000000000000000
-
-/* SWITCH_CORE :: IMP_EGRESS_PKT_TC2CPCP_MAP :: CPCP_FOR_RV0_TC6 [26:24] */
-#define BCHP_SWITCH_CORE_IMP_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC6_MASK 0x0000000007000000
-#define BCHP_SWITCH_CORE_IMP_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC6_SHIFT 24
-#define BCHP_SWITCH_CORE_IMP_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC6_DEFAULT 0x0000000000000006
-
-/* SWITCH_CORE :: IMP_EGRESS_PKT_TC2CPCP_MAP :: SWITCH_RESV_5 [23:23] */
-#define BCHP_SWITCH_CORE_IMP_EGRESS_PKT_TC2CPCP_MAP_SWITCH_RESV_5_MASK 0x0000000000800000
-#define BCHP_SWITCH_CORE_IMP_EGRESS_PKT_TC2CPCP_MAP_SWITCH_RESV_5_SHIFT 23
-#define BCHP_SWITCH_CORE_IMP_EGRESS_PKT_TC2CPCP_MAP_SWITCH_RESV_5_DEFAULT 0x0000000000000000
-
-/* SWITCH_CORE :: IMP_EGRESS_PKT_TC2CPCP_MAP :: CPCP_FOR_RV0_TC5 [22:20] */
-#define BCHP_SWITCH_CORE_IMP_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC5_MASK 0x0000000000700000
-#define BCHP_SWITCH_CORE_IMP_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC5_SHIFT 20
-#define BCHP_SWITCH_CORE_IMP_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC5_DEFAULT 0x0000000000000005
-
-/* SWITCH_CORE :: IMP_EGRESS_PKT_TC2CPCP_MAP :: SWITCH_RESV_4 [19:19] */
-#define BCHP_SWITCH_CORE_IMP_EGRESS_PKT_TC2CPCP_MAP_SWITCH_RESV_4_MASK 0x0000000000080000
-#define BCHP_SWITCH_CORE_IMP_EGRESS_PKT_TC2CPCP_MAP_SWITCH_RESV_4_SHIFT 19
-#define BCHP_SWITCH_CORE_IMP_EGRESS_PKT_TC2CPCP_MAP_SWITCH_RESV_4_DEFAULT 0x0000000000000000
-
-/* SWITCH_CORE :: IMP_EGRESS_PKT_TC2CPCP_MAP :: CPCP_FOR_RV0_TC4 [18:16] */
-#define BCHP_SWITCH_CORE_IMP_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC4_MASK 0x0000000000070000
-#define BCHP_SWITCH_CORE_IMP_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC4_SHIFT 16
-#define BCHP_SWITCH_CORE_IMP_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC4_DEFAULT 0x0000000000000004
-
-/* SWITCH_CORE :: IMP_EGRESS_PKT_TC2CPCP_MAP :: SWITCH_RESV_3 [15:15] */
-#define BCHP_SWITCH_CORE_IMP_EGRESS_PKT_TC2CPCP_MAP_SWITCH_RESV_3_MASK 0x0000000000008000
-#define BCHP_SWITCH_CORE_IMP_EGRESS_PKT_TC2CPCP_MAP_SWITCH_RESV_3_SHIFT 15
-#define BCHP_SWITCH_CORE_IMP_EGRESS_PKT_TC2CPCP_MAP_SWITCH_RESV_3_DEFAULT 0x0000000000000000
-
-/* SWITCH_CORE :: IMP_EGRESS_PKT_TC2CPCP_MAP :: CPCP_FOR_RV0_TC3 [14:12] */
-#define BCHP_SWITCH_CORE_IMP_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC3_MASK 0x0000000000007000
-#define BCHP_SWITCH_CORE_IMP_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC3_SHIFT 12
-#define BCHP_SWITCH_CORE_IMP_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC3_DEFAULT 0x0000000000000003
-
-/* SWITCH_CORE :: IMP_EGRESS_PKT_TC2CPCP_MAP :: SWITCH_RESV_2 [11:11] */
-#define BCHP_SWITCH_CORE_IMP_EGRESS_PKT_TC2CPCP_MAP_SWITCH_RESV_2_MASK 0x0000000000000800
-#define BCHP_SWITCH_CORE_IMP_EGRESS_PKT_TC2CPCP_MAP_SWITCH_RESV_2_SHIFT 11
-#define BCHP_SWITCH_CORE_IMP_EGRESS_PKT_TC2CPCP_MAP_SWITCH_RESV_2_DEFAULT 0x0000000000000000
-
-/* SWITCH_CORE :: IMP_EGRESS_PKT_TC2CPCP_MAP :: CPCP_FOR_RV0_TC2 [10:08] */
-#define BCHP_SWITCH_CORE_IMP_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC2_MASK 0x0000000000000700
-#define BCHP_SWITCH_CORE_IMP_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC2_SHIFT 8
-#define BCHP_SWITCH_CORE_IMP_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC2_DEFAULT 0x0000000000000002
-
-/* SWITCH_CORE :: IMP_EGRESS_PKT_TC2CPCP_MAP :: SWITCH_RESV_1 [07:07] */
-#define BCHP_SWITCH_CORE_IMP_EGRESS_PKT_TC2CPCP_MAP_SWITCH_RESV_1_MASK 0x0000000000000080
-#define BCHP_SWITCH_CORE_IMP_EGRESS_PKT_TC2CPCP_MAP_SWITCH_RESV_1_SHIFT 7
-#define BCHP_SWITCH_CORE_IMP_EGRESS_PKT_TC2CPCP_MAP_SWITCH_RESV_1_DEFAULT 0x0000000000000000
-
-/* SWITCH_CORE :: IMP_EGRESS_PKT_TC2CPCP_MAP :: CPCP_FOR_RV0_TC1 [06:04] */
-#define BCHP_SWITCH_CORE_IMP_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC1_MASK 0x0000000000000070
-#define BCHP_SWITCH_CORE_IMP_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC1_SHIFT 4
-#define BCHP_SWITCH_CORE_IMP_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC1_DEFAULT 0x0000000000000001
-
-/* SWITCH_CORE :: IMP_EGRESS_PKT_TC2CPCP_MAP :: SWITCH_RESV_0 [03:03] */
-#define BCHP_SWITCH_CORE_IMP_EGRESS_PKT_TC2CPCP_MAP_SWITCH_RESV_0_MASK 0x0000000000000008
-#define BCHP_SWITCH_CORE_IMP_EGRESS_PKT_TC2CPCP_MAP_SWITCH_RESV_0_SHIFT 3
-#define BCHP_SWITCH_CORE_IMP_EGRESS_PKT_TC2CPCP_MAP_SWITCH_RESV_0_DEFAULT 0x0000000000000000
-
-/* SWITCH_CORE :: IMP_EGRESS_PKT_TC2CPCP_MAP :: CPCP_FOR_RV0_TC0 [02:00] */
-#define BCHP_SWITCH_CORE_IMP_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC0_MASK 0x0000000000000007
-#define BCHP_SWITCH_CORE_IMP_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC0_SHIFT 0
-#define BCHP_SWITCH_CORE_IMP_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC0_DEFAULT 0x0000000000000000
-
-/***************************************************************************
- *TRREG_REG_SPARE0 - Spare 0 Register (Not2Release)
- ***************************************************************************/
-/* SWITCH_CORE :: TRREG_REG_SPARE0 :: TRREG_REG_SPARE0 [31:00] */
-#define BCHP_SWITCH_CORE_TRREG_REG_SPARE0_TRREG_REG_SPARE0_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_TRREG_REG_SPARE0_TRREG_REG_SPARE0_SHIFT 0
-#define BCHP_SWITCH_CORE_TRREG_REG_SPARE0_TRREG_REG_SPARE0_DEFAULT 0x00000000
-
-/***************************************************************************
- *TRREG_REG_SPARE1 - Spare 1 Register (Not2Release)
- ***************************************************************************/
-/* SWITCH_CORE :: TRREG_REG_SPARE1 :: TRREG_REG_SPARE1 [31:00] */
-#define BCHP_SWITCH_CORE_TRREG_REG_SPARE1_TRREG_REG_SPARE1_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_TRREG_REG_SPARE1_TRREG_REG_SPARE1_SHIFT 0
-#define BCHP_SWITCH_CORE_TRREG_REG_SPARE1_TRREG_REG_SPARE1_DEFAULT 0x00000000
-
-/***************************************************************************
- *EEE_EN_CTRL - EEE Enable Control Registers
- ***************************************************************************/
-/* SWITCH_CORE :: EEE_EN_CTRL :: reserved_for_padding0 [31:16] */
-#define BCHP_SWITCH_CORE_EEE_EN_CTRL_reserved_for_padding0_MASK 0xffff0000
-#define BCHP_SWITCH_CORE_EEE_EN_CTRL_reserved_for_padding0_SHIFT 16
-
-/* SWITCH_CORE :: EEE_EN_CTRL :: SWITCH_RESV [15:09] */
-#define BCHP_SWITCH_CORE_EEE_EN_CTRL_SWITCH_RESV_MASK 0x0000fe00
-#define BCHP_SWITCH_CORE_EEE_EN_CTRL_SWITCH_RESV_SHIFT 9
-#define BCHP_SWITCH_CORE_EEE_EN_CTRL_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: EEE_EN_CTRL :: EN_EEE [08:00] */
-#define BCHP_SWITCH_CORE_EEE_EN_CTRL_EN_EEE_MASK 0x000001ff
-#define BCHP_SWITCH_CORE_EEE_EN_CTRL_EN_EEE_SHIFT 0
-#define BCHP_SWITCH_CORE_EEE_EN_CTRL_EN_EEE_DEFAULT 0x00000000
-
-/***************************************************************************
- *EEE_LPI_ASSERT - EEE Low Power Assert Status Registers
- ***************************************************************************/
-/* SWITCH_CORE :: EEE_LPI_ASSERT :: reserved_for_padding0 [31:16] */
-#define BCHP_SWITCH_CORE_EEE_LPI_ASSERT_reserved_for_padding0_MASK 0xffff0000
-#define BCHP_SWITCH_CORE_EEE_LPI_ASSERT_reserved_for_padding0_SHIFT 16
-
-/* SWITCH_CORE :: EEE_LPI_ASSERT :: SWITCH_RESV [15:09] */
-#define BCHP_SWITCH_CORE_EEE_LPI_ASSERT_SWITCH_RESV_MASK 0x0000fe00
-#define BCHP_SWITCH_CORE_EEE_LPI_ASSERT_SWITCH_RESV_SHIFT 9
-#define BCHP_SWITCH_CORE_EEE_LPI_ASSERT_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: EEE_LPI_ASSERT :: LPI_ASSERT [08:00] */
-#define BCHP_SWITCH_CORE_EEE_LPI_ASSERT_LPI_ASSERT_MASK 0x000001ff
-#define BCHP_SWITCH_CORE_EEE_LPI_ASSERT_LPI_ASSERT_SHIFT 0
-#define BCHP_SWITCH_CORE_EEE_LPI_ASSERT_LPI_ASSERT_DEFAULT 0x00000000
-
-/***************************************************************************
- *EEE_LPI_INDICATE - EEE Low Power Indicate Status Registers
- ***************************************************************************/
-/* SWITCH_CORE :: EEE_LPI_INDICATE :: reserved_for_padding0 [31:16] */
-#define BCHP_SWITCH_CORE_EEE_LPI_INDICATE_reserved_for_padding0_MASK 0xffff0000
-#define BCHP_SWITCH_CORE_EEE_LPI_INDICATE_reserved_for_padding0_SHIFT 16
-
-/* SWITCH_CORE :: EEE_LPI_INDICATE :: SWITCH_RESV [15:09] */
-#define BCHP_SWITCH_CORE_EEE_LPI_INDICATE_SWITCH_RESV_MASK 0x0000fe00
-#define BCHP_SWITCH_CORE_EEE_LPI_INDICATE_SWITCH_RESV_SHIFT 9
-#define BCHP_SWITCH_CORE_EEE_LPI_INDICATE_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: EEE_LPI_INDICATE :: LPI_INDICATE [08:00] */
-#define BCHP_SWITCH_CORE_EEE_LPI_INDICATE_LPI_INDICATE_MASK 0x000001ff
-#define BCHP_SWITCH_CORE_EEE_LPI_INDICATE_LPI_INDICATE_SHIFT 0
-#define BCHP_SWITCH_CORE_EEE_LPI_INDICATE_LPI_INDICATE_DEFAULT 0x00000000
-
-/***************************************************************************
- *EEE_RX_IDLE_SYMBOL - EEE Receiving Idle Symbols Status Registers
- ***************************************************************************/
-/* SWITCH_CORE :: EEE_RX_IDLE_SYMBOL :: reserved_for_padding0 [31:16] */
-#define BCHP_SWITCH_CORE_EEE_RX_IDLE_SYMBOL_reserved_for_padding0_MASK 0xffff0000
-#define BCHP_SWITCH_CORE_EEE_RX_IDLE_SYMBOL_reserved_for_padding0_SHIFT 16
-
-/* SWITCH_CORE :: EEE_RX_IDLE_SYMBOL :: SWITCH_RESV [15:09] */
-#define BCHP_SWITCH_CORE_EEE_RX_IDLE_SYMBOL_SWITCH_RESV_MASK 0x0000fe00
-#define BCHP_SWITCH_CORE_EEE_RX_IDLE_SYMBOL_SWITCH_RESV_SHIFT 9
-#define BCHP_SWITCH_CORE_EEE_RX_IDLE_SYMBOL_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: EEE_RX_IDLE_SYMBOL :: RX_IDLE_SYMBOL [08:00] */
-#define BCHP_SWITCH_CORE_EEE_RX_IDLE_SYMBOL_RX_IDLE_SYMBOL_MASK 0x000001ff
-#define BCHP_SWITCH_CORE_EEE_RX_IDLE_SYMBOL_RX_IDLE_SYMBOL_SHIFT 0
-#define BCHP_SWITCH_CORE_EEE_RX_IDLE_SYMBOL_RX_IDLE_SYMBOL_DEFAULT 0x00000000
-
-/***************************************************************************
- *EEE_LPI_SYMBOL_TX_DISABLE - EEE LPI Symbol Transmit Disable Registers(Not2Release)
- ***************************************************************************/
-/* SWITCH_CORE :: EEE_LPI_SYMBOL_TX_DISABLE :: reserved_for_padding0 [31:16] */
-#define BCHP_SWITCH_CORE_EEE_LPI_SYMBOL_TX_DISABLE_reserved_for_padding0_MASK 0xffff0000
-#define BCHP_SWITCH_CORE_EEE_LPI_SYMBOL_TX_DISABLE_reserved_for_padding0_SHIFT 16
-
-/* SWITCH_CORE :: EEE_LPI_SYMBOL_TX_DISABLE :: SWITCH_RESV [15:09] */
-#define BCHP_SWITCH_CORE_EEE_LPI_SYMBOL_TX_DISABLE_SWITCH_RESV_MASK 0x0000fe00
-#define BCHP_SWITCH_CORE_EEE_LPI_SYMBOL_TX_DISABLE_SWITCH_RESV_SHIFT 9
-#define BCHP_SWITCH_CORE_EEE_LPI_SYMBOL_TX_DISABLE_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: EEE_LPI_SYMBOL_TX_DISABLE :: EEE_LPI_SYMBOL_TX_DISABLE [08:00] */
-#define BCHP_SWITCH_CORE_EEE_LPI_SYMBOL_TX_DISABLE_EEE_LPI_SYMBOL_TX_DISABLE_MASK 0x000001ff
-#define BCHP_SWITCH_CORE_EEE_LPI_SYMBOL_TX_DISABLE_EEE_LPI_SYMBOL_TX_DISABLE_SHIFT 0
-#define BCHP_SWITCH_CORE_EEE_LPI_SYMBOL_TX_DISABLE_EEE_LPI_SYMBOL_TX_DISABLE_DEFAULT 0x00000000
-
-/***************************************************************************
- *EEE_PIPELINE_TIMER - EEE Pipeline Delay Timer Registers
- ***************************************************************************/
-/* SWITCH_CORE :: EEE_PIPELINE_TIMER :: PIPELINE_TIMER [31:00] */
-#define BCHP_SWITCH_CORE_EEE_PIPELINE_TIMER_PIPELINE_TIMER_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_EEE_PIPELINE_TIMER_PIPELINE_TIMER_SHIFT 0
-#define BCHP_SWITCH_CORE_EEE_PIPELINE_TIMER_PIPELINE_TIMER_DEFAULT 0x00000020
-
-/***************************************************************************
- *EEE_SLEEP_TIMER_G_Port_0 - EEE Port N Sleep Delay Timer - 1G Registers
- ***************************************************************************/
-/* SWITCH_CORE :: EEE_SLEEP_TIMER_G_Port_0 :: SLEEP_TIMER_G [31:00] */
-#define BCHP_SWITCH_CORE_EEE_SLEEP_TIMER_G_Port_0_SLEEP_TIMER_G_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_EEE_SLEEP_TIMER_G_Port_0_SLEEP_TIMER_G_SHIFT 0
-#define BCHP_SWITCH_CORE_EEE_SLEEP_TIMER_G_Port_0_SLEEP_TIMER_G_DEFAULT 0x00000190
-
-/***************************************************************************
- *EEE_SLEEP_TIMER_G_Port_1 - EEE Port N Sleep Delay Timer - 1G Registers
- ***************************************************************************/
-/* SWITCH_CORE :: EEE_SLEEP_TIMER_G_Port_1 :: SLEEP_TIMER_G [31:00] */
-#define BCHP_SWITCH_CORE_EEE_SLEEP_TIMER_G_Port_1_SLEEP_TIMER_G_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_EEE_SLEEP_TIMER_G_Port_1_SLEEP_TIMER_G_SHIFT 0
-#define BCHP_SWITCH_CORE_EEE_SLEEP_TIMER_G_Port_1_SLEEP_TIMER_G_DEFAULT 0x00000190
-
-/***************************************************************************
- *EEE_SLEEP_TIMER_G_Port_2 - EEE Port N Sleep Delay Timer - 1G Registers
- ***************************************************************************/
-/* SWITCH_CORE :: EEE_SLEEP_TIMER_G_Port_2 :: SLEEP_TIMER_G [31:00] */
-#define BCHP_SWITCH_CORE_EEE_SLEEP_TIMER_G_Port_2_SLEEP_TIMER_G_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_EEE_SLEEP_TIMER_G_Port_2_SLEEP_TIMER_G_SHIFT 0
-#define BCHP_SWITCH_CORE_EEE_SLEEP_TIMER_G_Port_2_SLEEP_TIMER_G_DEFAULT 0x00000190
-
-/***************************************************************************
- *EEE_SLEEP_TIMER_G_Port_3 - EEE Port N Sleep Delay Timer - 1G Registers
- ***************************************************************************/
-/* SWITCH_CORE :: EEE_SLEEP_TIMER_G_Port_3 :: SLEEP_TIMER_G [31:00] */
-#define BCHP_SWITCH_CORE_EEE_SLEEP_TIMER_G_Port_3_SLEEP_TIMER_G_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_EEE_SLEEP_TIMER_G_Port_3_SLEEP_TIMER_G_SHIFT 0
-#define BCHP_SWITCH_CORE_EEE_SLEEP_TIMER_G_Port_3_SLEEP_TIMER_G_DEFAULT 0x00000190
-
-/***************************************************************************
- *EEE_SLEEP_TIMER_G_Port_4 - EEE Port N Sleep Delay Timer - 1G Registers
- ***************************************************************************/
-/* SWITCH_CORE :: EEE_SLEEP_TIMER_G_Port_4 :: SLEEP_TIMER_G [31:00] */
-#define BCHP_SWITCH_CORE_EEE_SLEEP_TIMER_G_Port_4_SLEEP_TIMER_G_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_EEE_SLEEP_TIMER_G_Port_4_SLEEP_TIMER_G_SHIFT 0
-#define BCHP_SWITCH_CORE_EEE_SLEEP_TIMER_G_Port_4_SLEEP_TIMER_G_DEFAULT 0x00000190
-
-/***************************************************************************
- *EEE_SLEEP_TIMER_G_Port_5 - EEE Port N Sleep Delay Timer - 1G Registers
- ***************************************************************************/
-/* SWITCH_CORE :: EEE_SLEEP_TIMER_G_Port_5 :: SLEEP_TIMER_G [31:00] */
-#define BCHP_SWITCH_CORE_EEE_SLEEP_TIMER_G_Port_5_SLEEP_TIMER_G_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_EEE_SLEEP_TIMER_G_Port_5_SLEEP_TIMER_G_SHIFT 0
-#define BCHP_SWITCH_CORE_EEE_SLEEP_TIMER_G_Port_5_SLEEP_TIMER_G_DEFAULT 0x00000190
-
-/***************************************************************************
- *EEE_SLEEP_TIMER_G_P7 - EEE Port 7 Sleep Delay Timer - 1G Registers
- ***************************************************************************/
-/* SWITCH_CORE :: EEE_SLEEP_TIMER_G_P7 :: SLEEP_TIMER_G [31:00] */
-#define BCHP_SWITCH_CORE_EEE_SLEEP_TIMER_G_P7_SLEEP_TIMER_G_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_EEE_SLEEP_TIMER_G_P7_SLEEP_TIMER_G_SHIFT 0
-#define BCHP_SWITCH_CORE_EEE_SLEEP_TIMER_G_P7_SLEEP_TIMER_G_DEFAULT 0x00000190
-
-/***************************************************************************
- *EEE_SLEEP_TIMER_G_IMP - EEE Port 8(IMP) Sleep Delay Timer - 1G Registers
- ***************************************************************************/
-/* SWITCH_CORE :: EEE_SLEEP_TIMER_G_IMP :: SLEEP_TIMER_G_IMP [31:00] */
-#define BCHP_SWITCH_CORE_EEE_SLEEP_TIMER_G_IMP_SLEEP_TIMER_G_IMP_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_EEE_SLEEP_TIMER_G_IMP_SLEEP_TIMER_G_IMP_SHIFT 0
-#define BCHP_SWITCH_CORE_EEE_SLEEP_TIMER_G_IMP_SLEEP_TIMER_G_IMP_DEFAULT 0x00000190
-
-/***************************************************************************
- *EEE_SLEEP_TIMER_H_Port_0 - EEE Port N Sleep Delay Timer - 100M Registers
- ***************************************************************************/
-/* SWITCH_CORE :: EEE_SLEEP_TIMER_H_Port_0 :: SLEEP_TIMER_H [31:00] */
-#define BCHP_SWITCH_CORE_EEE_SLEEP_TIMER_H_Port_0_SLEEP_TIMER_H_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_EEE_SLEEP_TIMER_H_Port_0_SLEEP_TIMER_H_SHIFT 0
-#define BCHP_SWITCH_CORE_EEE_SLEEP_TIMER_H_Port_0_SLEEP_TIMER_H_DEFAULT 0x00000fa0
-
-/***************************************************************************
- *EEE_SLEEP_TIMER_H_Port_1 - EEE Port N Sleep Delay Timer - 100M Registers
- ***************************************************************************/
-/* SWITCH_CORE :: EEE_SLEEP_TIMER_H_Port_1 :: SLEEP_TIMER_H [31:00] */
-#define BCHP_SWITCH_CORE_EEE_SLEEP_TIMER_H_Port_1_SLEEP_TIMER_H_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_EEE_SLEEP_TIMER_H_Port_1_SLEEP_TIMER_H_SHIFT 0
-#define BCHP_SWITCH_CORE_EEE_SLEEP_TIMER_H_Port_1_SLEEP_TIMER_H_DEFAULT 0x00000fa0
-
-/***************************************************************************
- *EEE_SLEEP_TIMER_H_Port_2 - EEE Port N Sleep Delay Timer - 100M Registers
- ***************************************************************************/
-/* SWITCH_CORE :: EEE_SLEEP_TIMER_H_Port_2 :: SLEEP_TIMER_H [31:00] */
-#define BCHP_SWITCH_CORE_EEE_SLEEP_TIMER_H_Port_2_SLEEP_TIMER_H_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_EEE_SLEEP_TIMER_H_Port_2_SLEEP_TIMER_H_SHIFT 0
-#define BCHP_SWITCH_CORE_EEE_SLEEP_TIMER_H_Port_2_SLEEP_TIMER_H_DEFAULT 0x00000fa0
-
-/***************************************************************************
- *EEE_SLEEP_TIMER_H_Port_3 - EEE Port N Sleep Delay Timer - 100M Registers
- ***************************************************************************/
-/* SWITCH_CORE :: EEE_SLEEP_TIMER_H_Port_3 :: SLEEP_TIMER_H [31:00] */
-#define BCHP_SWITCH_CORE_EEE_SLEEP_TIMER_H_Port_3_SLEEP_TIMER_H_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_EEE_SLEEP_TIMER_H_Port_3_SLEEP_TIMER_H_SHIFT 0
-#define BCHP_SWITCH_CORE_EEE_SLEEP_TIMER_H_Port_3_SLEEP_TIMER_H_DEFAULT 0x00000fa0
-
-/***************************************************************************
- *EEE_SLEEP_TIMER_H_Port_4 - EEE Port N Sleep Delay Timer - 100M Registers
- ***************************************************************************/
-/* SWITCH_CORE :: EEE_SLEEP_TIMER_H_Port_4 :: SLEEP_TIMER_H [31:00] */
-#define BCHP_SWITCH_CORE_EEE_SLEEP_TIMER_H_Port_4_SLEEP_TIMER_H_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_EEE_SLEEP_TIMER_H_Port_4_SLEEP_TIMER_H_SHIFT 0
-#define BCHP_SWITCH_CORE_EEE_SLEEP_TIMER_H_Port_4_SLEEP_TIMER_H_DEFAULT 0x00000fa0
-
-/***************************************************************************
- *EEE_SLEEP_TIMER_H_Port_5 - EEE Port N Sleep Delay Timer - 100M Registers
- ***************************************************************************/
-/* SWITCH_CORE :: EEE_SLEEP_TIMER_H_Port_5 :: SLEEP_TIMER_H [31:00] */
-#define BCHP_SWITCH_CORE_EEE_SLEEP_TIMER_H_Port_5_SLEEP_TIMER_H_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_EEE_SLEEP_TIMER_H_Port_5_SLEEP_TIMER_H_SHIFT 0
-#define BCHP_SWITCH_CORE_EEE_SLEEP_TIMER_H_Port_5_SLEEP_TIMER_H_DEFAULT 0x00000fa0
-
-/***************************************************************************
- *EEE_SLEEP_TIMER_H_P7 - EEE Port 7 Sleep Delay Timer - 100M Registers
- ***************************************************************************/
-/* SWITCH_CORE :: EEE_SLEEP_TIMER_H_P7 :: SLEEP_TIMER_H [31:00] */
-#define BCHP_SWITCH_CORE_EEE_SLEEP_TIMER_H_P7_SLEEP_TIMER_H_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_EEE_SLEEP_TIMER_H_P7_SLEEP_TIMER_H_SHIFT 0
-#define BCHP_SWITCH_CORE_EEE_SLEEP_TIMER_H_P7_SLEEP_TIMER_H_DEFAULT 0x00000fa0
-
-/***************************************************************************
- *EEE_SLEEP_TIMER_H_IMP - EEE Port 8(IMP) Sleep Delay Timer - 100M Registers
- ***************************************************************************/
-/* SWITCH_CORE :: EEE_SLEEP_TIMER_H_IMP :: SLEEP_TIMER_H_IMP [31:00] */
-#define BCHP_SWITCH_CORE_EEE_SLEEP_TIMER_H_IMP_SLEEP_TIMER_H_IMP_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_EEE_SLEEP_TIMER_H_IMP_SLEEP_TIMER_H_IMP_SHIFT 0
-#define BCHP_SWITCH_CORE_EEE_SLEEP_TIMER_H_IMP_SLEEP_TIMER_H_IMP_DEFAULT 0x00000fa0
-
-/***************************************************************************
- *EEE_MIN_LP_TIMER_G_Port_0 - EEE Port Minimum Low-Power Duration Timer - 1G Registers
- ***************************************************************************/
-/* SWITCH_CORE :: EEE_MIN_LP_TIMER_G_Port_0 :: MIN_LP_TIMER_G [31:00] */
-#define BCHP_SWITCH_CORE_EEE_MIN_LP_TIMER_G_Port_0_MIN_LP_TIMER_G_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_EEE_MIN_LP_TIMER_G_Port_0_MIN_LP_TIMER_G_SHIFT 0
-#define BCHP_SWITCH_CORE_EEE_MIN_LP_TIMER_G_Port_0_MIN_LP_TIMER_G_DEFAULT 0x00000032
-
-/***************************************************************************
- *EEE_MIN_LP_TIMER_G_Port_1 - EEE Port Minimum Low-Power Duration Timer - 1G Registers
- ***************************************************************************/
-/* SWITCH_CORE :: EEE_MIN_LP_TIMER_G_Port_1 :: MIN_LP_TIMER_G [31:00] */
-#define BCHP_SWITCH_CORE_EEE_MIN_LP_TIMER_G_Port_1_MIN_LP_TIMER_G_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_EEE_MIN_LP_TIMER_G_Port_1_MIN_LP_TIMER_G_SHIFT 0
-#define BCHP_SWITCH_CORE_EEE_MIN_LP_TIMER_G_Port_1_MIN_LP_TIMER_G_DEFAULT 0x00000032
-
-/***************************************************************************
- *EEE_MIN_LP_TIMER_G_Port_2 - EEE Port Minimum Low-Power Duration Timer - 1G Registers
- ***************************************************************************/
-/* SWITCH_CORE :: EEE_MIN_LP_TIMER_G_Port_2 :: MIN_LP_TIMER_G [31:00] */
-#define BCHP_SWITCH_CORE_EEE_MIN_LP_TIMER_G_Port_2_MIN_LP_TIMER_G_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_EEE_MIN_LP_TIMER_G_Port_2_MIN_LP_TIMER_G_SHIFT 0
-#define BCHP_SWITCH_CORE_EEE_MIN_LP_TIMER_G_Port_2_MIN_LP_TIMER_G_DEFAULT 0x00000032
-
-/***************************************************************************
- *EEE_MIN_LP_TIMER_G_Port_3 - EEE Port Minimum Low-Power Duration Timer - 1G Registers
- ***************************************************************************/
-/* SWITCH_CORE :: EEE_MIN_LP_TIMER_G_Port_3 :: MIN_LP_TIMER_G [31:00] */
-#define BCHP_SWITCH_CORE_EEE_MIN_LP_TIMER_G_Port_3_MIN_LP_TIMER_G_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_EEE_MIN_LP_TIMER_G_Port_3_MIN_LP_TIMER_G_SHIFT 0
-#define BCHP_SWITCH_CORE_EEE_MIN_LP_TIMER_G_Port_3_MIN_LP_TIMER_G_DEFAULT 0x00000032
-
-/***************************************************************************
- *EEE_MIN_LP_TIMER_G_Port_4 - EEE Port Minimum Low-Power Duration Timer - 1G Registers
- ***************************************************************************/
-/* SWITCH_CORE :: EEE_MIN_LP_TIMER_G_Port_4 :: MIN_LP_TIMER_G [31:00] */
-#define BCHP_SWITCH_CORE_EEE_MIN_LP_TIMER_G_Port_4_MIN_LP_TIMER_G_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_EEE_MIN_LP_TIMER_G_Port_4_MIN_LP_TIMER_G_SHIFT 0
-#define BCHP_SWITCH_CORE_EEE_MIN_LP_TIMER_G_Port_4_MIN_LP_TIMER_G_DEFAULT 0x00000032
-
-/***************************************************************************
- *EEE_MIN_LP_TIMER_G_Port_5 - EEE Port Minimum Low-Power Duration Timer - 1G Registers
- ***************************************************************************/
-/* SWITCH_CORE :: EEE_MIN_LP_TIMER_G_Port_5 :: MIN_LP_TIMER_G [31:00] */
-#define BCHP_SWITCH_CORE_EEE_MIN_LP_TIMER_G_Port_5_MIN_LP_TIMER_G_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_EEE_MIN_LP_TIMER_G_Port_5_MIN_LP_TIMER_G_SHIFT 0
-#define BCHP_SWITCH_CORE_EEE_MIN_LP_TIMER_G_Port_5_MIN_LP_TIMER_G_DEFAULT 0x00000032
-
-/***************************************************************************
- *EEE_MIN_LP_TIMER_G_P7 - EEE Port 7 Minimum Low-Power Duration Timer Registers
- ***************************************************************************/
-/* SWITCH_CORE :: EEE_MIN_LP_TIMER_G_P7 :: MIN_LP_TIMER_G [31:00] */
-#define BCHP_SWITCH_CORE_EEE_MIN_LP_TIMER_G_P7_MIN_LP_TIMER_G_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_EEE_MIN_LP_TIMER_G_P7_MIN_LP_TIMER_G_SHIFT 0
-#define BCHP_SWITCH_CORE_EEE_MIN_LP_TIMER_G_P7_MIN_LP_TIMER_G_DEFAULT 0x00000032
-
-/***************************************************************************
- *EEE_MIN_LP_TIMER_G_IMP - EEE Port 8(IMP) Minimum Low-Power Duration Timer Registers
- ***************************************************************************/
-/* SWITCH_CORE :: EEE_MIN_LP_TIMER_G_IMP :: MIN_LP_TIMER_G_IMP [31:00] */
-#define BCHP_SWITCH_CORE_EEE_MIN_LP_TIMER_G_IMP_MIN_LP_TIMER_G_IMP_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_EEE_MIN_LP_TIMER_G_IMP_MIN_LP_TIMER_G_IMP_SHIFT 0
-#define BCHP_SWITCH_CORE_EEE_MIN_LP_TIMER_G_IMP_MIN_LP_TIMER_G_IMP_DEFAULT 0x00000032
-
-/***************************************************************************
- *EEE_MIN_LP_TIMER_H_Port_0 - EEE Port Minimum Low-Power Duration Timer - 100M Registers
- ***************************************************************************/
-/* SWITCH_CORE :: EEE_MIN_LP_TIMER_H_Port_0 :: MIN_LP_TIMER_H [31:00] */
-#define BCHP_SWITCH_CORE_EEE_MIN_LP_TIMER_H_Port_0_MIN_LP_TIMER_H_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_EEE_MIN_LP_TIMER_H_Port_0_MIN_LP_TIMER_H_SHIFT 0
-#define BCHP_SWITCH_CORE_EEE_MIN_LP_TIMER_H_Port_0_MIN_LP_TIMER_H_DEFAULT 0x000001f4
-
-/***************************************************************************
- *EEE_MIN_LP_TIMER_H_Port_1 - EEE Port Minimum Low-Power Duration Timer - 100M Registers
- ***************************************************************************/
-/* SWITCH_CORE :: EEE_MIN_LP_TIMER_H_Port_1 :: MIN_LP_TIMER_H [31:00] */
-#define BCHP_SWITCH_CORE_EEE_MIN_LP_TIMER_H_Port_1_MIN_LP_TIMER_H_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_EEE_MIN_LP_TIMER_H_Port_1_MIN_LP_TIMER_H_SHIFT 0
-#define BCHP_SWITCH_CORE_EEE_MIN_LP_TIMER_H_Port_1_MIN_LP_TIMER_H_DEFAULT 0x000001f4
-
-/***************************************************************************
- *EEE_MIN_LP_TIMER_H_Port_2 - EEE Port Minimum Low-Power Duration Timer - 100M Registers
- ***************************************************************************/
-/* SWITCH_CORE :: EEE_MIN_LP_TIMER_H_Port_2 :: MIN_LP_TIMER_H [31:00] */
-#define BCHP_SWITCH_CORE_EEE_MIN_LP_TIMER_H_Port_2_MIN_LP_TIMER_H_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_EEE_MIN_LP_TIMER_H_Port_2_MIN_LP_TIMER_H_SHIFT 0
-#define BCHP_SWITCH_CORE_EEE_MIN_LP_TIMER_H_Port_2_MIN_LP_TIMER_H_DEFAULT 0x000001f4
-
-/***************************************************************************
- *EEE_MIN_LP_TIMER_H_Port_3 - EEE Port Minimum Low-Power Duration Timer - 100M Registers
- ***************************************************************************/
-/* SWITCH_CORE :: EEE_MIN_LP_TIMER_H_Port_3 :: MIN_LP_TIMER_H [31:00] */
-#define BCHP_SWITCH_CORE_EEE_MIN_LP_TIMER_H_Port_3_MIN_LP_TIMER_H_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_EEE_MIN_LP_TIMER_H_Port_3_MIN_LP_TIMER_H_SHIFT 0
-#define BCHP_SWITCH_CORE_EEE_MIN_LP_TIMER_H_Port_3_MIN_LP_TIMER_H_DEFAULT 0x000001f4
-
-/***************************************************************************
- *EEE_MIN_LP_TIMER_H_Port_4 - EEE Port Minimum Low-Power Duration Timer - 100M Registers
- ***************************************************************************/
-/* SWITCH_CORE :: EEE_MIN_LP_TIMER_H_Port_4 :: MIN_LP_TIMER_H [31:00] */
-#define BCHP_SWITCH_CORE_EEE_MIN_LP_TIMER_H_Port_4_MIN_LP_TIMER_H_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_EEE_MIN_LP_TIMER_H_Port_4_MIN_LP_TIMER_H_SHIFT 0
-#define BCHP_SWITCH_CORE_EEE_MIN_LP_TIMER_H_Port_4_MIN_LP_TIMER_H_DEFAULT 0x000001f4
-
-/***************************************************************************
- *EEE_MIN_LP_TIMER_H_Port_5 - EEE Port Minimum Low-Power Duration Timer - 100M Registers
- ***************************************************************************/
-/* SWITCH_CORE :: EEE_MIN_LP_TIMER_H_Port_5 :: MIN_LP_TIMER_H [31:00] */
-#define BCHP_SWITCH_CORE_EEE_MIN_LP_TIMER_H_Port_5_MIN_LP_TIMER_H_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_EEE_MIN_LP_TIMER_H_Port_5_MIN_LP_TIMER_H_SHIFT 0
-#define BCHP_SWITCH_CORE_EEE_MIN_LP_TIMER_H_Port_5_MIN_LP_TIMER_H_DEFAULT 0x000001f4
-
-/***************************************************************************
- *EEE_MIN_LP_TIMER_H_P7 - EEE Port 7 Minimum Low-Power Duration Timer - 100M Registers
- ***************************************************************************/
-/* SWITCH_CORE :: EEE_MIN_LP_TIMER_H_P7 :: MIN_LP_TIMER_H [31:00] */
-#define BCHP_SWITCH_CORE_EEE_MIN_LP_TIMER_H_P7_MIN_LP_TIMER_H_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_EEE_MIN_LP_TIMER_H_P7_MIN_LP_TIMER_H_SHIFT 0
-#define BCHP_SWITCH_CORE_EEE_MIN_LP_TIMER_H_P7_MIN_LP_TIMER_H_DEFAULT 0x000001f4
-
-/***************************************************************************
- *EEE_MIN_LP_TIMER_H_IMP - EEE Port 8(IMP) Minimum Low-Power Duration Timer - 100M Registers
- ***************************************************************************/
-/* SWITCH_CORE :: EEE_MIN_LP_TIMER_H_IMP :: MIN_LP_TIMER_H_IMP [31:00] */
-#define BCHP_SWITCH_CORE_EEE_MIN_LP_TIMER_H_IMP_MIN_LP_TIMER_H_IMP_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_EEE_MIN_LP_TIMER_H_IMP_MIN_LP_TIMER_H_IMP_SHIFT 0
-#define BCHP_SWITCH_CORE_EEE_MIN_LP_TIMER_H_IMP_MIN_LP_TIMER_H_IMP_DEFAULT 0x000001f4
-
-/***************************************************************************
- *EEE_WAKE_TIMER_G_Port_0 - EEE Port N Wake Transition Timer - 1G Registers
- ***************************************************************************/
-/* SWITCH_CORE :: EEE_WAKE_TIMER_G_Port_0 :: reserved_for_padding0 [31:16] */
-#define BCHP_SWITCH_CORE_EEE_WAKE_TIMER_G_Port_0_reserved_for_padding0_MASK 0xffff0000
-#define BCHP_SWITCH_CORE_EEE_WAKE_TIMER_G_Port_0_reserved_for_padding0_SHIFT 16
-
-/* SWITCH_CORE :: EEE_WAKE_TIMER_G_Port_0 :: WAKE_TIMER_G [15:00] */
-#define BCHP_SWITCH_CORE_EEE_WAKE_TIMER_G_Port_0_WAKE_TIMER_G_MASK 0x0000ffff
-#define BCHP_SWITCH_CORE_EEE_WAKE_TIMER_G_Port_0_WAKE_TIMER_G_SHIFT 0
-#define BCHP_SWITCH_CORE_EEE_WAKE_TIMER_G_Port_0_WAKE_TIMER_G_DEFAULT 0x00000011
-
-/***************************************************************************
- *EEE_WAKE_TIMER_G_Port_1 - EEE Port N Wake Transition Timer - 1G Registers
- ***************************************************************************/
-/* SWITCH_CORE :: EEE_WAKE_TIMER_G_Port_1 :: reserved_for_padding0 [31:16] */
-#define BCHP_SWITCH_CORE_EEE_WAKE_TIMER_G_Port_1_reserved_for_padding0_MASK 0xffff0000
-#define BCHP_SWITCH_CORE_EEE_WAKE_TIMER_G_Port_1_reserved_for_padding0_SHIFT 16
-
-/* SWITCH_CORE :: EEE_WAKE_TIMER_G_Port_1 :: WAKE_TIMER_G [15:00] */
-#define BCHP_SWITCH_CORE_EEE_WAKE_TIMER_G_Port_1_WAKE_TIMER_G_MASK 0x0000ffff
-#define BCHP_SWITCH_CORE_EEE_WAKE_TIMER_G_Port_1_WAKE_TIMER_G_SHIFT 0
-#define BCHP_SWITCH_CORE_EEE_WAKE_TIMER_G_Port_1_WAKE_TIMER_G_DEFAULT 0x00000011
-
-/***************************************************************************
- *EEE_WAKE_TIMER_G_Port_2 - EEE Port N Wake Transition Timer - 1G Registers
- ***************************************************************************/
-/* SWITCH_CORE :: EEE_WAKE_TIMER_G_Port_2 :: reserved_for_padding0 [31:16] */
-#define BCHP_SWITCH_CORE_EEE_WAKE_TIMER_G_Port_2_reserved_for_padding0_MASK 0xffff0000
-#define BCHP_SWITCH_CORE_EEE_WAKE_TIMER_G_Port_2_reserved_for_padding0_SHIFT 16
-
-/* SWITCH_CORE :: EEE_WAKE_TIMER_G_Port_2 :: WAKE_TIMER_G [15:00] */
-#define BCHP_SWITCH_CORE_EEE_WAKE_TIMER_G_Port_2_WAKE_TIMER_G_MASK 0x0000ffff
-#define BCHP_SWITCH_CORE_EEE_WAKE_TIMER_G_Port_2_WAKE_TIMER_G_SHIFT 0
-#define BCHP_SWITCH_CORE_EEE_WAKE_TIMER_G_Port_2_WAKE_TIMER_G_DEFAULT 0x00000011
-
-/***************************************************************************
- *EEE_WAKE_TIMER_G_Port_3 - EEE Port N Wake Transition Timer - 1G Registers
- ***************************************************************************/
-/* SWITCH_CORE :: EEE_WAKE_TIMER_G_Port_3 :: reserved_for_padding0 [31:16] */
-#define BCHP_SWITCH_CORE_EEE_WAKE_TIMER_G_Port_3_reserved_for_padding0_MASK 0xffff0000
-#define BCHP_SWITCH_CORE_EEE_WAKE_TIMER_G_Port_3_reserved_for_padding0_SHIFT 16
-
-/* SWITCH_CORE :: EEE_WAKE_TIMER_G_Port_3 :: WAKE_TIMER_G [15:00] */
-#define BCHP_SWITCH_CORE_EEE_WAKE_TIMER_G_Port_3_WAKE_TIMER_G_MASK 0x0000ffff
-#define BCHP_SWITCH_CORE_EEE_WAKE_TIMER_G_Port_3_WAKE_TIMER_G_SHIFT 0
-#define BCHP_SWITCH_CORE_EEE_WAKE_TIMER_G_Port_3_WAKE_TIMER_G_DEFAULT 0x00000011
-
-/***************************************************************************
- *EEE_WAKE_TIMER_G_Port_4 - EEE Port N Wake Transition Timer - 1G Registers
- ***************************************************************************/
-/* SWITCH_CORE :: EEE_WAKE_TIMER_G_Port_4 :: reserved_for_padding0 [31:16] */
-#define BCHP_SWITCH_CORE_EEE_WAKE_TIMER_G_Port_4_reserved_for_padding0_MASK 0xffff0000
-#define BCHP_SWITCH_CORE_EEE_WAKE_TIMER_G_Port_4_reserved_for_padding0_SHIFT 16
-
-/* SWITCH_CORE :: EEE_WAKE_TIMER_G_Port_4 :: WAKE_TIMER_G [15:00] */
-#define BCHP_SWITCH_CORE_EEE_WAKE_TIMER_G_Port_4_WAKE_TIMER_G_MASK 0x0000ffff
-#define BCHP_SWITCH_CORE_EEE_WAKE_TIMER_G_Port_4_WAKE_TIMER_G_SHIFT 0
-#define BCHP_SWITCH_CORE_EEE_WAKE_TIMER_G_Port_4_WAKE_TIMER_G_DEFAULT 0x00000011
-
-/***************************************************************************
- *EEE_WAKE_TIMER_G_Port_5 - EEE Port N Wake Transition Timer - 1G Registers
- ***************************************************************************/
-/* SWITCH_CORE :: EEE_WAKE_TIMER_G_Port_5 :: reserved_for_padding0 [31:16] */
-#define BCHP_SWITCH_CORE_EEE_WAKE_TIMER_G_Port_5_reserved_for_padding0_MASK 0xffff0000
-#define BCHP_SWITCH_CORE_EEE_WAKE_TIMER_G_Port_5_reserved_for_padding0_SHIFT 16
-
-/* SWITCH_CORE :: EEE_WAKE_TIMER_G_Port_5 :: WAKE_TIMER_G [15:00] */
-#define BCHP_SWITCH_CORE_EEE_WAKE_TIMER_G_Port_5_WAKE_TIMER_G_MASK 0x0000ffff
-#define BCHP_SWITCH_CORE_EEE_WAKE_TIMER_G_Port_5_WAKE_TIMER_G_SHIFT 0
-#define BCHP_SWITCH_CORE_EEE_WAKE_TIMER_G_Port_5_WAKE_TIMER_G_DEFAULT 0x00000011
-
-/***************************************************************************
- *EEE_WAKE_TIMER_G_P7 - EEE Port 7 Wake Transition Timer - 1G Registers
- ***************************************************************************/
-/* SWITCH_CORE :: EEE_WAKE_TIMER_G_P7 :: reserved_for_padding0 [31:16] */
-#define BCHP_SWITCH_CORE_EEE_WAKE_TIMER_G_P7_reserved_for_padding0_MASK 0xffff0000
-#define BCHP_SWITCH_CORE_EEE_WAKE_TIMER_G_P7_reserved_for_padding0_SHIFT 16
-
-/* SWITCH_CORE :: EEE_WAKE_TIMER_G_P7 :: WAKE_TIMER_G [15:00] */
-#define BCHP_SWITCH_CORE_EEE_WAKE_TIMER_G_P7_WAKE_TIMER_G_MASK 0x0000ffff
-#define BCHP_SWITCH_CORE_EEE_WAKE_TIMER_G_P7_WAKE_TIMER_G_SHIFT 0
-#define BCHP_SWITCH_CORE_EEE_WAKE_TIMER_G_P7_WAKE_TIMER_G_DEFAULT 0x00000011
-
-/***************************************************************************
- *EEE_WAKE_TIMER_G_IMP - EEE Port 8(IMP) Wake Transition Timer - 1G Registers
- ***************************************************************************/
-/* SWITCH_CORE :: EEE_WAKE_TIMER_G_IMP :: reserved_for_padding0 [31:16] */
-#define BCHP_SWITCH_CORE_EEE_WAKE_TIMER_G_IMP_reserved_for_padding0_MASK 0xffff0000
-#define BCHP_SWITCH_CORE_EEE_WAKE_TIMER_G_IMP_reserved_for_padding0_SHIFT 16
-
-/* SWITCH_CORE :: EEE_WAKE_TIMER_G_IMP :: WAKE_TIMER_G_IMP [15:00] */
-#define BCHP_SWITCH_CORE_EEE_WAKE_TIMER_G_IMP_WAKE_TIMER_G_IMP_MASK 0x0000ffff
-#define BCHP_SWITCH_CORE_EEE_WAKE_TIMER_G_IMP_WAKE_TIMER_G_IMP_SHIFT 0
-#define BCHP_SWITCH_CORE_EEE_WAKE_TIMER_G_IMP_WAKE_TIMER_G_IMP_DEFAULT 0x00000011
-
-/***************************************************************************
- *EEE_WAKE_TIMER_H_Port_0 - EEE Port N Wake Transition Timer - 100M Registers
- ***************************************************************************/
-/* SWITCH_CORE :: EEE_WAKE_TIMER_H_Port_0 :: reserved_for_padding0 [31:16] */
-#define BCHP_SWITCH_CORE_EEE_WAKE_TIMER_H_Port_0_reserved_for_padding0_MASK 0xffff0000
-#define BCHP_SWITCH_CORE_EEE_WAKE_TIMER_H_Port_0_reserved_for_padding0_SHIFT 16
-
-/* SWITCH_CORE :: EEE_WAKE_TIMER_H_Port_0 :: WAKE_TIMER_H [15:00] */
-#define BCHP_SWITCH_CORE_EEE_WAKE_TIMER_H_Port_0_WAKE_TIMER_H_MASK 0x0000ffff
-#define BCHP_SWITCH_CORE_EEE_WAKE_TIMER_H_Port_0_WAKE_TIMER_H_SHIFT 0
-#define BCHP_SWITCH_CORE_EEE_WAKE_TIMER_H_Port_0_WAKE_TIMER_H_DEFAULT 0x00000024
-
-/***************************************************************************
- *EEE_WAKE_TIMER_H_Port_1 - EEE Port N Wake Transition Timer - 100M Registers
- ***************************************************************************/
-/* SWITCH_CORE :: EEE_WAKE_TIMER_H_Port_1 :: reserved_for_padding0 [31:16] */
-#define BCHP_SWITCH_CORE_EEE_WAKE_TIMER_H_Port_1_reserved_for_padding0_MASK 0xffff0000
-#define BCHP_SWITCH_CORE_EEE_WAKE_TIMER_H_Port_1_reserved_for_padding0_SHIFT 16
-
-/* SWITCH_CORE :: EEE_WAKE_TIMER_H_Port_1 :: WAKE_TIMER_H [15:00] */
-#define BCHP_SWITCH_CORE_EEE_WAKE_TIMER_H_Port_1_WAKE_TIMER_H_MASK 0x0000ffff
-#define BCHP_SWITCH_CORE_EEE_WAKE_TIMER_H_Port_1_WAKE_TIMER_H_SHIFT 0
-#define BCHP_SWITCH_CORE_EEE_WAKE_TIMER_H_Port_1_WAKE_TIMER_H_DEFAULT 0x00000024
-
-/***************************************************************************
- *EEE_WAKE_TIMER_H_Port_2 - EEE Port N Wake Transition Timer - 100M Registers
- ***************************************************************************/
-/* SWITCH_CORE :: EEE_WAKE_TIMER_H_Port_2 :: reserved_for_padding0 [31:16] */
-#define BCHP_SWITCH_CORE_EEE_WAKE_TIMER_H_Port_2_reserved_for_padding0_MASK 0xffff0000
-#define BCHP_SWITCH_CORE_EEE_WAKE_TIMER_H_Port_2_reserved_for_padding0_SHIFT 16
-
-/* SWITCH_CORE :: EEE_WAKE_TIMER_H_Port_2 :: WAKE_TIMER_H [15:00] */
-#define BCHP_SWITCH_CORE_EEE_WAKE_TIMER_H_Port_2_WAKE_TIMER_H_MASK 0x0000ffff
-#define BCHP_SWITCH_CORE_EEE_WAKE_TIMER_H_Port_2_WAKE_TIMER_H_SHIFT 0
-#define BCHP_SWITCH_CORE_EEE_WAKE_TIMER_H_Port_2_WAKE_TIMER_H_DEFAULT 0x00000024
-
-/***************************************************************************
- *EEE_WAKE_TIMER_H_Port_3 - EEE Port N Wake Transition Timer - 100M Registers
- ***************************************************************************/
-/* SWITCH_CORE :: EEE_WAKE_TIMER_H_Port_3 :: reserved_for_padding0 [31:16] */
-#define BCHP_SWITCH_CORE_EEE_WAKE_TIMER_H_Port_3_reserved_for_padding0_MASK 0xffff0000
-#define BCHP_SWITCH_CORE_EEE_WAKE_TIMER_H_Port_3_reserved_for_padding0_SHIFT 16
-
-/* SWITCH_CORE :: EEE_WAKE_TIMER_H_Port_3 :: WAKE_TIMER_H [15:00] */
-#define BCHP_SWITCH_CORE_EEE_WAKE_TIMER_H_Port_3_WAKE_TIMER_H_MASK 0x0000ffff
-#define BCHP_SWITCH_CORE_EEE_WAKE_TIMER_H_Port_3_WAKE_TIMER_H_SHIFT 0
-#define BCHP_SWITCH_CORE_EEE_WAKE_TIMER_H_Port_3_WAKE_TIMER_H_DEFAULT 0x00000024
-
-/***************************************************************************
- *EEE_WAKE_TIMER_H_Port_4 - EEE Port N Wake Transition Timer - 100M Registers
- ***************************************************************************/
-/* SWITCH_CORE :: EEE_WAKE_TIMER_H_Port_4 :: reserved_for_padding0 [31:16] */
-#define BCHP_SWITCH_CORE_EEE_WAKE_TIMER_H_Port_4_reserved_for_padding0_MASK 0xffff0000
-#define BCHP_SWITCH_CORE_EEE_WAKE_TIMER_H_Port_4_reserved_for_padding0_SHIFT 16
-
-/* SWITCH_CORE :: EEE_WAKE_TIMER_H_Port_4 :: WAKE_TIMER_H [15:00] */
-#define BCHP_SWITCH_CORE_EEE_WAKE_TIMER_H_Port_4_WAKE_TIMER_H_MASK 0x0000ffff
-#define BCHP_SWITCH_CORE_EEE_WAKE_TIMER_H_Port_4_WAKE_TIMER_H_SHIFT 0
-#define BCHP_SWITCH_CORE_EEE_WAKE_TIMER_H_Port_4_WAKE_TIMER_H_DEFAULT 0x00000024
-
-/***************************************************************************
- *EEE_WAKE_TIMER_H_Port_5 - EEE Port N Wake Transition Timer - 100M Registers
- ***************************************************************************/
-/* SWITCH_CORE :: EEE_WAKE_TIMER_H_Port_5 :: reserved_for_padding0 [31:16] */
-#define BCHP_SWITCH_CORE_EEE_WAKE_TIMER_H_Port_5_reserved_for_padding0_MASK 0xffff0000
-#define BCHP_SWITCH_CORE_EEE_WAKE_TIMER_H_Port_5_reserved_for_padding0_SHIFT 16
-
-/* SWITCH_CORE :: EEE_WAKE_TIMER_H_Port_5 :: WAKE_TIMER_H [15:00] */
-#define BCHP_SWITCH_CORE_EEE_WAKE_TIMER_H_Port_5_WAKE_TIMER_H_MASK 0x0000ffff
-#define BCHP_SWITCH_CORE_EEE_WAKE_TIMER_H_Port_5_WAKE_TIMER_H_SHIFT 0
-#define BCHP_SWITCH_CORE_EEE_WAKE_TIMER_H_Port_5_WAKE_TIMER_H_DEFAULT 0x00000024
-
-/***************************************************************************
- *EEE_WAKE_TIMER_H_P7 - EEE Port 7 Wake Transition Timer - 100M Registers
- ***************************************************************************/
-/* SWITCH_CORE :: EEE_WAKE_TIMER_H_P7 :: reserved_for_padding0 [31:16] */
-#define BCHP_SWITCH_CORE_EEE_WAKE_TIMER_H_P7_reserved_for_padding0_MASK 0xffff0000
-#define BCHP_SWITCH_CORE_EEE_WAKE_TIMER_H_P7_reserved_for_padding0_SHIFT 16
-
-/* SWITCH_CORE :: EEE_WAKE_TIMER_H_P7 :: WAKE_TIMER_H [15:00] */
-#define BCHP_SWITCH_CORE_EEE_WAKE_TIMER_H_P7_WAKE_TIMER_H_MASK 0x0000ffff
-#define BCHP_SWITCH_CORE_EEE_WAKE_TIMER_H_P7_WAKE_TIMER_H_SHIFT 0
-#define BCHP_SWITCH_CORE_EEE_WAKE_TIMER_H_P7_WAKE_TIMER_H_DEFAULT 0x00000024
-
-/***************************************************************************
- *EEE_WAKE_TIMER_H_IMP - EEE Port 8(IMP) Wake Transition Timer - 100M Registers
- ***************************************************************************/
-/* SWITCH_CORE :: EEE_WAKE_TIMER_H_IMP :: reserved_for_padding0 [31:16] */
-#define BCHP_SWITCH_CORE_EEE_WAKE_TIMER_H_IMP_reserved_for_padding0_MASK 0xffff0000
-#define BCHP_SWITCH_CORE_EEE_WAKE_TIMER_H_IMP_reserved_for_padding0_SHIFT 16
-
-/* SWITCH_CORE :: EEE_WAKE_TIMER_H_IMP :: WAKE_TIMER_H_IMP [15:00] */
-#define BCHP_SWITCH_CORE_EEE_WAKE_TIMER_H_IMP_WAKE_TIMER_H_IMP_MASK 0x0000ffff
-#define BCHP_SWITCH_CORE_EEE_WAKE_TIMER_H_IMP_WAKE_TIMER_H_IMP_SHIFT 0
-#define BCHP_SWITCH_CORE_EEE_WAKE_TIMER_H_IMP_WAKE_TIMER_H_IMP_DEFAULT 0x00000024
-
-/***************************************************************************
- *EEE_GLB_CONG_TH - EEE Global Congestion Threshold Registers
- ***************************************************************************/
-/* SWITCH_CORE :: EEE_GLB_CONG_TH :: reserved_for_padding0 [31:16] */
-#define BCHP_SWITCH_CORE_EEE_GLB_CONG_TH_reserved_for_padding0_MASK 0xffff0000
-#define BCHP_SWITCH_CORE_EEE_GLB_CONG_TH_reserved_for_padding0_SHIFT 16
-
-/* SWITCH_CORE :: EEE_GLB_CONG_TH :: SWITCH_RESV [15:11] */
-#define BCHP_SWITCH_CORE_EEE_GLB_CONG_TH_SWITCH_RESV_MASK 0x0000f800
-#define BCHP_SWITCH_CORE_EEE_GLB_CONG_TH_SWITCH_RESV_SHIFT 11
-#define BCHP_SWITCH_CORE_EEE_GLB_CONG_TH_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: EEE_GLB_CONG_TH :: GLB_CONG_TH [10:00] */
-#define BCHP_SWITCH_CORE_EEE_GLB_CONG_TH_GLB_CONG_TH_MASK 0x000007ff
-#define BCHP_SWITCH_CORE_EEE_GLB_CONG_TH_GLB_CONG_TH_SHIFT 0
-#define BCHP_SWITCH_CORE_EEE_GLB_CONG_TH_GLB_CONG_TH_DEFAULT 0x00000300
-
-/***************************************************************************
- *EEE_TXQ_CONG_TH_Port_0 - EEE TXQ N Congestion Threshold Registers
- ***************************************************************************/
-/* SWITCH_CORE :: EEE_TXQ_CONG_TH_Port_0 :: reserved_for_padding0 [31:16] */
-#define BCHP_SWITCH_CORE_EEE_TXQ_CONG_TH_Port_0_reserved_for_padding0_MASK 0xffff0000
-#define BCHP_SWITCH_CORE_EEE_TXQ_CONG_TH_Port_0_reserved_for_padding0_SHIFT 16
-
-/* SWITCH_CORE :: EEE_TXQ_CONG_TH_Port_0 :: SWITCH_RESV [15:11] */
-#define BCHP_SWITCH_CORE_EEE_TXQ_CONG_TH_Port_0_SWITCH_RESV_MASK 0x0000f800
-#define BCHP_SWITCH_CORE_EEE_TXQ_CONG_TH_Port_0_SWITCH_RESV_SHIFT 11
-#define BCHP_SWITCH_CORE_EEE_TXQ_CONG_TH_Port_0_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: EEE_TXQ_CONG_TH_Port_0 :: TXQ_CONG_TH [10:00] */
-#define BCHP_SWITCH_CORE_EEE_TXQ_CONG_TH_Port_0_TXQ_CONG_TH_MASK 0x000007ff
-#define BCHP_SWITCH_CORE_EEE_TXQ_CONG_TH_Port_0_TXQ_CONG_TH_SHIFT 0
-#define BCHP_SWITCH_CORE_EEE_TXQ_CONG_TH_Port_0_TXQ_CONG_TH_DEFAULT 0x00000050
-
-/***************************************************************************
- *EEE_TXQ_CONG_TH_Port_1 - EEE TXQ N Congestion Threshold Registers
- ***************************************************************************/
-/* SWITCH_CORE :: EEE_TXQ_CONG_TH_Port_1 :: reserved_for_padding0 [31:16] */
-#define BCHP_SWITCH_CORE_EEE_TXQ_CONG_TH_Port_1_reserved_for_padding0_MASK 0xffff0000
-#define BCHP_SWITCH_CORE_EEE_TXQ_CONG_TH_Port_1_reserved_for_padding0_SHIFT 16
-
-/* SWITCH_CORE :: EEE_TXQ_CONG_TH_Port_1 :: SWITCH_RESV [15:11] */
-#define BCHP_SWITCH_CORE_EEE_TXQ_CONG_TH_Port_1_SWITCH_RESV_MASK 0x0000f800
-#define BCHP_SWITCH_CORE_EEE_TXQ_CONG_TH_Port_1_SWITCH_RESV_SHIFT 11
-#define BCHP_SWITCH_CORE_EEE_TXQ_CONG_TH_Port_1_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: EEE_TXQ_CONG_TH_Port_1 :: TXQ_CONG_TH [10:00] */
-#define BCHP_SWITCH_CORE_EEE_TXQ_CONG_TH_Port_1_TXQ_CONG_TH_MASK 0x000007ff
-#define BCHP_SWITCH_CORE_EEE_TXQ_CONG_TH_Port_1_TXQ_CONG_TH_SHIFT 0
-#define BCHP_SWITCH_CORE_EEE_TXQ_CONG_TH_Port_1_TXQ_CONG_TH_DEFAULT 0x00000050
-
-/***************************************************************************
- *EEE_TXQ_CONG_TH_Port_2 - EEE TXQ N Congestion Threshold Registers
- ***************************************************************************/
-/* SWITCH_CORE :: EEE_TXQ_CONG_TH_Port_2 :: reserved_for_padding0 [31:16] */
-#define BCHP_SWITCH_CORE_EEE_TXQ_CONG_TH_Port_2_reserved_for_padding0_MASK 0xffff0000
-#define BCHP_SWITCH_CORE_EEE_TXQ_CONG_TH_Port_2_reserved_for_padding0_SHIFT 16
-
-/* SWITCH_CORE :: EEE_TXQ_CONG_TH_Port_2 :: SWITCH_RESV [15:11] */
-#define BCHP_SWITCH_CORE_EEE_TXQ_CONG_TH_Port_2_SWITCH_RESV_MASK 0x0000f800
-#define BCHP_SWITCH_CORE_EEE_TXQ_CONG_TH_Port_2_SWITCH_RESV_SHIFT 11
-#define BCHP_SWITCH_CORE_EEE_TXQ_CONG_TH_Port_2_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: EEE_TXQ_CONG_TH_Port_2 :: TXQ_CONG_TH [10:00] */
-#define BCHP_SWITCH_CORE_EEE_TXQ_CONG_TH_Port_2_TXQ_CONG_TH_MASK 0x000007ff
-#define BCHP_SWITCH_CORE_EEE_TXQ_CONG_TH_Port_2_TXQ_CONG_TH_SHIFT 0
-#define BCHP_SWITCH_CORE_EEE_TXQ_CONG_TH_Port_2_TXQ_CONG_TH_DEFAULT 0x00000050
-
-/***************************************************************************
- *EEE_TXQ_CONG_TH_Port_3 - EEE TXQ N Congestion Threshold Registers
- ***************************************************************************/
-/* SWITCH_CORE :: EEE_TXQ_CONG_TH_Port_3 :: reserved_for_padding0 [31:16] */
-#define BCHP_SWITCH_CORE_EEE_TXQ_CONG_TH_Port_3_reserved_for_padding0_MASK 0xffff0000
-#define BCHP_SWITCH_CORE_EEE_TXQ_CONG_TH_Port_3_reserved_for_padding0_SHIFT 16
-
-/* SWITCH_CORE :: EEE_TXQ_CONG_TH_Port_3 :: SWITCH_RESV [15:11] */
-#define BCHP_SWITCH_CORE_EEE_TXQ_CONG_TH_Port_3_SWITCH_RESV_MASK 0x0000f800
-#define BCHP_SWITCH_CORE_EEE_TXQ_CONG_TH_Port_3_SWITCH_RESV_SHIFT 11
-#define BCHP_SWITCH_CORE_EEE_TXQ_CONG_TH_Port_3_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: EEE_TXQ_CONG_TH_Port_3 :: TXQ_CONG_TH [10:00] */
-#define BCHP_SWITCH_CORE_EEE_TXQ_CONG_TH_Port_3_TXQ_CONG_TH_MASK 0x000007ff
-#define BCHP_SWITCH_CORE_EEE_TXQ_CONG_TH_Port_3_TXQ_CONG_TH_SHIFT 0
-#define BCHP_SWITCH_CORE_EEE_TXQ_CONG_TH_Port_3_TXQ_CONG_TH_DEFAULT 0x00000050
-
-/***************************************************************************
- *EEE_TXQ_CONG_TH_Port_4 - EEE TXQ N Congestion Threshold Registers
- ***************************************************************************/
-/* SWITCH_CORE :: EEE_TXQ_CONG_TH_Port_4 :: reserved_for_padding0 [31:16] */
-#define BCHP_SWITCH_CORE_EEE_TXQ_CONG_TH_Port_4_reserved_for_padding0_MASK 0xffff0000
-#define BCHP_SWITCH_CORE_EEE_TXQ_CONG_TH_Port_4_reserved_for_padding0_SHIFT 16
-
-/* SWITCH_CORE :: EEE_TXQ_CONG_TH_Port_4 :: SWITCH_RESV [15:11] */
-#define BCHP_SWITCH_CORE_EEE_TXQ_CONG_TH_Port_4_SWITCH_RESV_MASK 0x0000f800
-#define BCHP_SWITCH_CORE_EEE_TXQ_CONG_TH_Port_4_SWITCH_RESV_SHIFT 11
-#define BCHP_SWITCH_CORE_EEE_TXQ_CONG_TH_Port_4_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: EEE_TXQ_CONG_TH_Port_4 :: TXQ_CONG_TH [10:00] */
-#define BCHP_SWITCH_CORE_EEE_TXQ_CONG_TH_Port_4_TXQ_CONG_TH_MASK 0x000007ff
-#define BCHP_SWITCH_CORE_EEE_TXQ_CONG_TH_Port_4_TXQ_CONG_TH_SHIFT 0
-#define BCHP_SWITCH_CORE_EEE_TXQ_CONG_TH_Port_4_TXQ_CONG_TH_DEFAULT 0x00000050
-
-/***************************************************************************
- *EEE_TXQ_CONG_TH_Port_5 - EEE TXQ N Congestion Threshold Registers
- ***************************************************************************/
-/* SWITCH_CORE :: EEE_TXQ_CONG_TH_Port_5 :: reserved_for_padding0 [31:16] */
-#define BCHP_SWITCH_CORE_EEE_TXQ_CONG_TH_Port_5_reserved_for_padding0_MASK 0xffff0000
-#define BCHP_SWITCH_CORE_EEE_TXQ_CONG_TH_Port_5_reserved_for_padding0_SHIFT 16
-
-/* SWITCH_CORE :: EEE_TXQ_CONG_TH_Port_5 :: SWITCH_RESV [15:11] */
-#define BCHP_SWITCH_CORE_EEE_TXQ_CONG_TH_Port_5_SWITCH_RESV_MASK 0x0000f800
-#define BCHP_SWITCH_CORE_EEE_TXQ_CONG_TH_Port_5_SWITCH_RESV_SHIFT 11
-#define BCHP_SWITCH_CORE_EEE_TXQ_CONG_TH_Port_5_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: EEE_TXQ_CONG_TH_Port_5 :: TXQ_CONG_TH [10:00] */
-#define BCHP_SWITCH_CORE_EEE_TXQ_CONG_TH_Port_5_TXQ_CONG_TH_MASK 0x000007ff
-#define BCHP_SWITCH_CORE_EEE_TXQ_CONG_TH_Port_5_TXQ_CONG_TH_SHIFT 0
-#define BCHP_SWITCH_CORE_EEE_TXQ_CONG_TH_Port_5_TXQ_CONG_TH_DEFAULT 0x00000001
-
-/***************************************************************************
- *EEE_PHY_CTRL - EEE PHY Control Registers(Not2Release)
- ***************************************************************************/
-/* SWITCH_CORE :: EEE_PHY_CTRL :: reserved_for_padding0 [31:08] */
-#define BCHP_SWITCH_CORE_EEE_PHY_CTRL_reserved_for_padding0_MASK 0xffffff00
-#define BCHP_SWITCH_CORE_EEE_PHY_CTRL_reserved_for_padding0_SHIFT 8
-
-/* SWITCH_CORE :: EEE_PHY_CTRL :: SWITCH_RESV [07:04] */
-#define BCHP_SWITCH_CORE_EEE_PHY_CTRL_SWITCH_RESV_MASK 0x000000f0
-#define BCHP_SWITCH_CORE_EEE_PHY_CTRL_SWITCH_RESV_SHIFT 4
-#define BCHP_SWITCH_CORE_EEE_PHY_CTRL_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: EEE_PHY_CTRL :: EEE_100BASE_TX [03:03] */
-#define BCHP_SWITCH_CORE_EEE_PHY_CTRL_EEE_100BASE_TX_MASK 0x00000008
-#define BCHP_SWITCH_CORE_EEE_PHY_CTRL_EEE_100BASE_TX_SHIFT 3
-#define BCHP_SWITCH_CORE_EEE_PHY_CTRL_EEE_100BASE_TX_DEFAULT 0x00000001
-
-/* SWITCH_CORE :: EEE_PHY_CTRL :: EEE_1000BASE_TX [02:02] */
-#define BCHP_SWITCH_CORE_EEE_PHY_CTRL_EEE_1000BASE_TX_MASK 0x00000004
-#define BCHP_SWITCH_CORE_EEE_PHY_CTRL_EEE_1000BASE_TX_SHIFT 2
-#define BCHP_SWITCH_CORE_EEE_PHY_CTRL_EEE_1000BASE_TX_DEFAULT 0x00000001
-
-/* SWITCH_CORE :: EEE_PHY_CTRL :: EN_PHY_LPI [01:01] */
-#define BCHP_SWITCH_CORE_EEE_PHY_CTRL_EN_PHY_LPI_MASK 0x00000002
-#define BCHP_SWITCH_CORE_EEE_PHY_CTRL_EN_PHY_LPI_SHIFT 1
-#define BCHP_SWITCH_CORE_EEE_PHY_CTRL_EN_PHY_LPI_DEFAULT 0x00000001
-
-/* SWITCH_CORE :: EEE_PHY_CTRL :: EN_BIAS_10BTE [00:00] */
-#define BCHP_SWITCH_CORE_EEE_PHY_CTRL_EN_BIAS_10BTE_MASK 0x00000001
-#define BCHP_SWITCH_CORE_EEE_PHY_CTRL_EN_BIAS_10BTE_SHIFT 0
-#define BCHP_SWITCH_CORE_EEE_PHY_CTRL_EN_BIAS_10BTE_DEFAULT 0x00000000
-
-/***************************************************************************
- *EEE_TXQ_CONG_TH6 - EEE TXQ 6 Congestion Threshold Registers
- ***************************************************************************/
-/* SWITCH_CORE :: EEE_TXQ_CONG_TH6 :: reserved_for_padding0 [31:16] */
-#define BCHP_SWITCH_CORE_EEE_TXQ_CONG_TH6_reserved_for_padding0_MASK 0xffff0000
-#define BCHP_SWITCH_CORE_EEE_TXQ_CONG_TH6_reserved_for_padding0_SHIFT 16
-
-/* SWITCH_CORE :: EEE_TXQ_CONG_TH6 :: SWITCH_RESV [15:11] */
-#define BCHP_SWITCH_CORE_EEE_TXQ_CONG_TH6_SWITCH_RESV_MASK 0x0000f800
-#define BCHP_SWITCH_CORE_EEE_TXQ_CONG_TH6_SWITCH_RESV_SHIFT 11
-#define BCHP_SWITCH_CORE_EEE_TXQ_CONG_TH6_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: EEE_TXQ_CONG_TH6 :: TXQ_CONG_TH [10:00] */
-#define BCHP_SWITCH_CORE_EEE_TXQ_CONG_TH6_TXQ_CONG_TH_MASK 0x000007ff
-#define BCHP_SWITCH_CORE_EEE_TXQ_CONG_TH6_TXQ_CONG_TH_SHIFT 0
-#define BCHP_SWITCH_CORE_EEE_TXQ_CONG_TH6_TXQ_CONG_TH_DEFAULT 0x00000001
-
-/***************************************************************************
- *EEE_TXQ_CONG_TH7 - EEE TXQ 7 Congestion Threshold Registers
- ***************************************************************************/
-/* SWITCH_CORE :: EEE_TXQ_CONG_TH7 :: reserved_for_padding0 [31:16] */
-#define BCHP_SWITCH_CORE_EEE_TXQ_CONG_TH7_reserved_for_padding0_MASK 0xffff0000
-#define BCHP_SWITCH_CORE_EEE_TXQ_CONG_TH7_reserved_for_padding0_SHIFT 16
-
-/* SWITCH_CORE :: EEE_TXQ_CONG_TH7 :: SWITCH_RESV [15:11] */
-#define BCHP_SWITCH_CORE_EEE_TXQ_CONG_TH7_SWITCH_RESV_MASK 0x0000f800
-#define BCHP_SWITCH_CORE_EEE_TXQ_CONG_TH7_SWITCH_RESV_SHIFT 11
-#define BCHP_SWITCH_CORE_EEE_TXQ_CONG_TH7_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: EEE_TXQ_CONG_TH7 :: TXQ_CONG_TH [10:00] */
-#define BCHP_SWITCH_CORE_EEE_TXQ_CONG_TH7_TXQ_CONG_TH_MASK 0x000007ff
-#define BCHP_SWITCH_CORE_EEE_TXQ_CONG_TH7_TXQ_CONG_TH_SHIFT 0
-#define BCHP_SWITCH_CORE_EEE_TXQ_CONG_TH7_TXQ_CONG_TH_DEFAULT 0x00000001
-
-/***************************************************************************
- *EEE_CTL_REG_SPARE0 - Spare 0 Register (Not2Release)
- ***************************************************************************/
-/* SWITCH_CORE :: EEE_CTL_REG_SPARE0 :: EEE_CTL_REG_SPARE0 [31:00] */
-#define BCHP_SWITCH_CORE_EEE_CTL_REG_SPARE0_EEE_CTL_REG_SPARE0_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_EEE_CTL_REG_SPARE0_EEE_CTL_REG_SPARE0_SHIFT 0
-#define BCHP_SWITCH_CORE_EEE_CTL_REG_SPARE0_EEE_CTL_REG_SPARE0_DEFAULT 0x00000000
-
-/***************************************************************************
- *EEE_CTL_REG_SPARE1 - Spare 1 Register (Not2Release)
- ***************************************************************************/
-/* SWITCH_CORE :: EEE_CTL_REG_SPARE1 :: EEE_CTL_REG_SPARE1 [31:00] */
-#define BCHP_SWITCH_CORE_EEE_CTL_REG_SPARE1_EEE_CTL_REG_SPARE1_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_EEE_CTL_REG_SPARE1_EEE_CTL_REG_SPARE1_SHIFT 0
-#define BCHP_SWITCH_CORE_EEE_CTL_REG_SPARE1_EEE_CTL_REG_SPARE1_DEFAULT 0x00000000
-
-/***************************************************************************
- *EEE_DEBUG - EEE Debug Registers(Not2Release)
- ***************************************************************************/
-/* SWITCH_CORE :: EEE_DEBUG :: reserved_for_padding0 [31:08] */
-#define BCHP_SWITCH_CORE_EEE_DEBUG_reserved_for_padding0_MASK 0xffffff00
-#define BCHP_SWITCH_CORE_EEE_DEBUG_reserved_for_padding0_SHIFT 8
-
-/* SWITCH_CORE :: EEE_DEBUG :: SWITCH_RESV [07:02] */
-#define BCHP_SWITCH_CORE_EEE_DEBUG_SWITCH_RESV_MASK 0x000000fc
-#define BCHP_SWITCH_CORE_EEE_DEBUG_SWITCH_RESV_SHIFT 2
-#define BCHP_SWITCH_CORE_EEE_DEBUG_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: EEE_DEBUG :: DIS_EXIT_LPI_FLOW_CON_TX [01:01] */
-#define BCHP_SWITCH_CORE_EEE_DEBUG_DIS_EXIT_LPI_FLOW_CON_TX_MASK 0x00000002
-#define BCHP_SWITCH_CORE_EEE_DEBUG_DIS_EXIT_LPI_FLOW_CON_TX_SHIFT 1
-#define BCHP_SWITCH_CORE_EEE_DEBUG_DIS_EXIT_LPI_FLOW_CON_TX_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: EEE_DEBUG :: DIS_EMPTY_FLOW_CON [00:00] */
-#define BCHP_SWITCH_CORE_EEE_DEBUG_DIS_EMPTY_FLOW_CON_MASK 0x00000001
-#define BCHP_SWITCH_CORE_EEE_DEBUG_DIS_EMPTY_FLOW_CON_SHIFT 0
-#define BCHP_SWITCH_CORE_EEE_DEBUG_DIS_EMPTY_FLOW_CON_DEFAULT 0x00000000
-
-/***************************************************************************
- *EEE_LINK_DLY_TIMER - EEE Link Delay Timer Registers(Not2Release)
- ***************************************************************************/
-/* SWITCH_CORE :: EEE_LINK_DLY_TIMER :: LINK_DLY_TIMER [31:00] */
-#define BCHP_SWITCH_CORE_EEE_LINK_DLY_TIMER_LINK_DLY_TIMER_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_EEE_LINK_DLY_TIMER_LINK_DLY_TIMER_SHIFT 0
-#define BCHP_SWITCH_CORE_EEE_LINK_DLY_TIMER_LINK_DLY_TIMER_DEFAULT 0x000f4240
-
-/***************************************************************************
- *EEE_STATE - EEE Control Policy State Registers(Not2Release)
- ***************************************************************************/
-/* SWITCH_CORE :: EEE_STATE :: SWITCH_RESV [31:27] */
-#define BCHP_SWITCH_CORE_EEE_STATE_SWITCH_RESV_MASK 0xf8000000
-#define BCHP_SWITCH_CORE_EEE_STATE_SWITCH_RESV_SHIFT 27
-#define BCHP_SWITCH_CORE_EEE_STATE_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: EEE_STATE :: EEE_STATE [26:00] */
-#define BCHP_SWITCH_CORE_EEE_STATE_EEE_STATE_MASK 0x07ffffff
-#define BCHP_SWITCH_CORE_EEE_STATE_EEE_STATE_SHIFT 0
-#define BCHP_SWITCH_CORE_EEE_STATE_EEE_STATE_DEFAULT 0x00000000
-
-/***************************************************************************
- *RED_CONTROL - RED Control Register
- ***************************************************************************/
-/* SWITCH_CORE :: RED_CONTROL :: reserved_for_padding0 [31:16] */
-#define BCHP_SWITCH_CORE_RED_CONTROL_reserved_for_padding0_MASK 0xffff0000
-#define BCHP_SWITCH_CORE_RED_CONTROL_reserved_for_padding0_SHIFT 16
-
-/* SWITCH_CORE :: RED_CONTROL :: SWITCH_RESV [15:09] */
-#define BCHP_SWITCH_CORE_RED_CONTROL_SWITCH_RESV_MASK 0x0000fe00
-#define BCHP_SWITCH_CORE_RED_CONTROL_SWITCH_RESV_SHIFT 9
-#define BCHP_SWITCH_CORE_RED_CONTROL_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: RED_CONTROL :: RED_EN [08:00] */
-#define BCHP_SWITCH_CORE_RED_CONTROL_RED_EN_MASK 0x000001ff
-#define BCHP_SWITCH_CORE_RED_CONTROL_RED_EN_SHIFT 0
-#define BCHP_SWITCH_CORE_RED_CONTROL_RED_EN_DEFAULT 0x00000000
-
-/***************************************************************************
- *TC2RED_PROFILE_TABLE - RED Table Configuration Register
- ***************************************************************************/
-/* SWITCH_CORE :: TC2RED_PROFILE_TABLE :: reserved_for_padding0 [31:16] */
-#define BCHP_SWITCH_CORE_TC2RED_PROFILE_TABLE_reserved_for_padding0_MASK 0xffff0000
-#define BCHP_SWITCH_CORE_TC2RED_PROFILE_TABLE_reserved_for_padding0_SHIFT 16
-
-/* SWITCH_CORE :: TC2RED_PROFILE_TABLE :: TC2RED_TABLE_WR_RD [15:15] */
-#define BCHP_SWITCH_CORE_TC2RED_PROFILE_TABLE_TC2RED_TABLE_WR_RD_MASK 0x00008000
-#define BCHP_SWITCH_CORE_TC2RED_PROFILE_TABLE_TC2RED_TABLE_WR_RD_SHIFT 15
-#define BCHP_SWITCH_CORE_TC2RED_PROFILE_TABLE_TC2RED_TABLE_WR_RD_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: TC2RED_PROFILE_TABLE :: SWITCH_RESV [14:13] */
-#define BCHP_SWITCH_CORE_TC2RED_PROFILE_TABLE_SWITCH_RESV_MASK 0x00006000
-#define BCHP_SWITCH_CORE_TC2RED_PROFILE_TABLE_SWITCH_RESV_SHIFT 13
-#define BCHP_SWITCH_CORE_TC2RED_PROFILE_TABLE_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: TC2RED_PROFILE_TABLE :: TC2RED_TABLE_ADDR [12:04] */
-#define BCHP_SWITCH_CORE_TC2RED_PROFILE_TABLE_TC2RED_TABLE_ADDR_MASK 0x00001ff0
-#define BCHP_SWITCH_CORE_TC2RED_PROFILE_TABLE_TC2RED_TABLE_ADDR_SHIFT 4
-#define BCHP_SWITCH_CORE_TC2RED_PROFILE_TABLE_TC2RED_TABLE_ADDR_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: TC2RED_PROFILE_TABLE :: TC2RED_TABLE_DATA [03:00] */
-#define BCHP_SWITCH_CORE_TC2RED_PROFILE_TABLE_TC2RED_TABLE_DATA_MASK 0x0000000f
-#define BCHP_SWITCH_CORE_TC2RED_PROFILE_TABLE_TC2RED_TABLE_DATA_SHIFT 0
-#define BCHP_SWITCH_CORE_TC2RED_PROFILE_TABLE_TC2RED_TABLE_DATA_DEFAULT 0x00000000
-
-/***************************************************************************
- *RED_EGRESS_BYPASS - RED Egress Bypass Register
- ***************************************************************************/
-/* SWITCH_CORE :: RED_EGRESS_BYPASS :: reserved_for_padding0 [31:16] */
-#define BCHP_SWITCH_CORE_RED_EGRESS_BYPASS_reserved_for_padding0_MASK 0xffff0000
-#define BCHP_SWITCH_CORE_RED_EGRESS_BYPASS_reserved_for_padding0_SHIFT 16
-
-/* SWITCH_CORE :: RED_EGRESS_BYPASS :: SWITCH_RESV [15:09] */
-#define BCHP_SWITCH_CORE_RED_EGRESS_BYPASS_SWITCH_RESV_MASK 0x0000fe00
-#define BCHP_SWITCH_CORE_RED_EGRESS_BYPASS_SWITCH_RESV_SHIFT 9
-#define BCHP_SWITCH_CORE_RED_EGRESS_BYPASS_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: RED_EGRESS_BYPASS :: RED_EGRESS_BYPASS [08:00] */
-#define BCHP_SWITCH_CORE_RED_EGRESS_BYPASS_RED_EGRESS_BYPASS_MASK 0x000001ff
-#define BCHP_SWITCH_CORE_RED_EGRESS_BYPASS_RED_EGRESS_BYPASS_SHIFT 0
-#define BCHP_SWITCH_CORE_RED_EGRESS_BYPASS_RED_EGRESS_BYPASS_DEFAULT 0x00000080
-
-/***************************************************************************
- *RED_AQD_CONTROL - RED AQD Control Register
- ***************************************************************************/
-/* SWITCH_CORE :: RED_AQD_CONTROL :: reserved_for_padding0 [31:16] */
-#define BCHP_SWITCH_CORE_RED_AQD_CONTROL_reserved_for_padding0_MASK 0xffff0000
-#define BCHP_SWITCH_CORE_RED_AQD_CONTROL_reserved_for_padding0_SHIFT 16
-
-/* SWITCH_CORE :: RED_AQD_CONTROL :: SWITCH_RESV_2 [15:12] */
-#define BCHP_SWITCH_CORE_RED_AQD_CONTROL_SWITCH_RESV_2_MASK 0x0000f000
-#define BCHP_SWITCH_CORE_RED_AQD_CONTROL_SWITCH_RESV_2_SHIFT 12
-#define BCHP_SWITCH_CORE_RED_AQD_CONTROL_SWITCH_RESV_2_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: RED_AQD_CONTROL :: AQD_PERIOD [11:08] */
-#define BCHP_SWITCH_CORE_RED_AQD_CONTROL_AQD_PERIOD_MASK 0x00000f00
-#define BCHP_SWITCH_CORE_RED_AQD_CONTROL_AQD_PERIOD_SHIFT 8
-#define BCHP_SWITCH_CORE_RED_AQD_CONTROL_AQD_PERIOD_DEFAULT 0x00000008
-
-/* SWITCH_CORE :: RED_AQD_CONTROL :: SWITCH_RESV_1 [07:06] */
-#define BCHP_SWITCH_CORE_RED_AQD_CONTROL_SWITCH_RESV_1_MASK 0x000000c0
-#define BCHP_SWITCH_CORE_RED_AQD_CONTROL_SWITCH_RESV_1_SHIFT 6
-#define BCHP_SWITCH_CORE_RED_AQD_CONTROL_SWITCH_RESV_1_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: RED_AQD_CONTROL :: AQD_RST [05:05] */
-#define BCHP_SWITCH_CORE_RED_AQD_CONTROL_AQD_RST_MASK 0x00000020
-#define BCHP_SWITCH_CORE_RED_AQD_CONTROL_AQD_RST_SHIFT 5
-#define BCHP_SWITCH_CORE_RED_AQD_CONTROL_AQD_RST_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: RED_AQD_CONTROL :: RED_FAST_CORR [04:04] */
-#define BCHP_SWITCH_CORE_RED_AQD_CONTROL_RED_FAST_CORR_MASK 0x00000010
-#define BCHP_SWITCH_CORE_RED_AQD_CONTROL_RED_FAST_CORR_SHIFT 4
-#define BCHP_SWITCH_CORE_RED_AQD_CONTROL_RED_FAST_CORR_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: RED_AQD_CONTROL :: SWITCH_RESV_0 [03:00] */
-#define BCHP_SWITCH_CORE_RED_AQD_CONTROL_SWITCH_RESV_0_MASK 0x0000000f
-#define BCHP_SWITCH_CORE_RED_AQD_CONTROL_SWITCH_RESV_0_SHIFT 0
-#define BCHP_SWITCH_CORE_RED_AQD_CONTROL_SWITCH_RESV_0_DEFAULT 0x00000000
-
-/***************************************************************************
- *RED_EXPONENT - RED AQD Weighted Factor Register
- ***************************************************************************/
-/* SWITCH_CORE :: RED_EXPONENT :: reserved_for_padding0 [31:16] */
-#define BCHP_SWITCH_CORE_RED_EXPONENT_reserved_for_padding0_MASK 0xffff0000
-#define BCHP_SWITCH_CORE_RED_EXPONENT_reserved_for_padding0_SHIFT 16
-
-/* SWITCH_CORE :: RED_EXPONENT :: SWITCH_RESV [15:08] */
-#define BCHP_SWITCH_CORE_RED_EXPONENT_SWITCH_RESV_MASK 0x0000ff00
-#define BCHP_SWITCH_CORE_RED_EXPONENT_SWITCH_RESV_SHIFT 8
-#define BCHP_SWITCH_CORE_RED_EXPONENT_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: RED_EXPONENT :: RED_EXPONENT [07:00] */
-#define BCHP_SWITCH_CORE_RED_EXPONENT_RED_EXPONENT_MASK 0x000000ff
-#define BCHP_SWITCH_CORE_RED_EXPONENT_RED_EXPONENT_SHIFT 0
-#define BCHP_SWITCH_CORE_RED_EXPONENT_RED_EXPONENT_DEFAULT 0x00000005
-
-/***************************************************************************
- *RED_DROP_ADD_TO_MIB - RED Drop Add to MIB Register
- ***************************************************************************/
-/* SWITCH_CORE :: RED_DROP_ADD_TO_MIB :: reserved_for_padding0 [31:16] */
-#define BCHP_SWITCH_CORE_RED_DROP_ADD_TO_MIB_reserved_for_padding0_MASK 0xffff0000
-#define BCHP_SWITCH_CORE_RED_DROP_ADD_TO_MIB_reserved_for_padding0_SHIFT 16
-
-/* SWITCH_CORE :: RED_DROP_ADD_TO_MIB :: SWITCH_RESV [15:09] */
-#define BCHP_SWITCH_CORE_RED_DROP_ADD_TO_MIB_SWITCH_RESV_MASK 0x0000fe00
-#define BCHP_SWITCH_CORE_RED_DROP_ADD_TO_MIB_SWITCH_RESV_SHIFT 9
-#define BCHP_SWITCH_CORE_RED_DROP_ADD_TO_MIB_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: RED_DROP_ADD_TO_MIB :: RED_DROP_ADD_TO_MIB [08:00] */
-#define BCHP_SWITCH_CORE_RED_DROP_ADD_TO_MIB_RED_DROP_ADD_TO_MIB_MASK 0x000001ff
-#define BCHP_SWITCH_CORE_RED_DROP_ADD_TO_MIB_RED_DROP_ADD_TO_MIB_SHIFT 0
-#define BCHP_SWITCH_CORE_RED_DROP_ADD_TO_MIB_RED_DROP_ADD_TO_MIB_DEFAULT 0x000001ff
-
-/***************************************************************************
- *RED_PROFILE_DEFAULT - Default RED profile Register
- ***************************************************************************/
-/* SWITCH_CORE :: RED_PROFILE_DEFAULT :: SWITCH_RESV [31:04] */
-#define BCHP_SWITCH_CORE_RED_PROFILE_DEFAULT_SWITCH_RESV_MASK 0xfffffff0
-#define BCHP_SWITCH_CORE_RED_PROFILE_DEFAULT_SWITCH_RESV_SHIFT 4
-#define BCHP_SWITCH_CORE_RED_PROFILE_DEFAULT_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: RED_PROFILE_DEFAULT :: RED_PROFILE_DEFAULT [03:00] */
-#define BCHP_SWITCH_CORE_RED_PROFILE_DEFAULT_RED_PROFILE_DEFAULT_MASK 0x0000000f
-#define BCHP_SWITCH_CORE_RED_PROFILE_DEFAULT_RED_PROFILE_DEFAULT_SHIFT 0
-#define BCHP_SWITCH_CORE_RED_PROFILE_DEFAULT_RED_PROFILE_DEFAULT_DEFAULT 0x00000000
-
-/***************************************************************************
- *WRED_REG_SPARE0 - Spare 0 Register (Not2Release)
- ***************************************************************************/
-/* SWITCH_CORE :: WRED_REG_SPARE0 :: WRED_REG_SPARE0 [31:00] */
-#define BCHP_SWITCH_CORE_WRED_REG_SPARE0_WRED_REG_SPARE0_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_WRED_REG_SPARE0_WRED_REG_SPARE0_SHIFT 0
-#define BCHP_SWITCH_CORE_WRED_REG_SPARE0_WRED_REG_SPARE0_DEFAULT 0x00000000
-
-/***************************************************************************
- *WRED_REG_SPARE1 - Spare 1 Register (Not2Release)
- ***************************************************************************/
-/* SWITCH_CORE :: WRED_REG_SPARE1 :: WRED_REG_SPARE1 [31:00] */
-#define BCHP_SWITCH_CORE_WRED_REG_SPARE1_WRED_REG_SPARE1_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_WRED_REG_SPARE1_WRED_REG_SPARE1_SHIFT 0
-#define BCHP_SWITCH_CORE_WRED_REG_SPARE1_WRED_REG_SPARE1_DEFAULT 0x00000000
-
-/***************************************************************************
- *RED_PROFILE_N_Port_0 - RED profile N Register
- ***************************************************************************/
-/* SWITCH_CORE :: RED_PROFILE_N_Port_0 :: SWITCH_RESV [31:26] */
-#define BCHP_SWITCH_CORE_RED_PROFILE_N_Port_0_SWITCH_RESV_MASK 0xfc000000
-#define BCHP_SWITCH_CORE_RED_PROFILE_N_Port_0_SWITCH_RESV_SHIFT 26
-#define BCHP_SWITCH_CORE_RED_PROFILE_N_Port_0_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: RED_PROFILE_N_Port_0 :: RED_DROP_PROB [25:22] */
-#define BCHP_SWITCH_CORE_RED_PROFILE_N_Port_0_RED_DROP_PROB_MASK 0x03c00000
-#define BCHP_SWITCH_CORE_RED_PROFILE_N_Port_0_RED_DROP_PROB_SHIFT 22
-#define BCHP_SWITCH_CORE_RED_PROFILE_N_Port_0_RED_DROP_PROB_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: RED_PROFILE_N_Port_0 :: RED_MAX_THD [21:11] */
-#define BCHP_SWITCH_CORE_RED_PROFILE_N_Port_0_RED_MAX_THD_MASK 0x003ff800
-#define BCHP_SWITCH_CORE_RED_PROFILE_N_Port_0_RED_MAX_THD_SHIFT 11
-#define BCHP_SWITCH_CORE_RED_PROFILE_N_Port_0_RED_MAX_THD_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: RED_PROFILE_N_Port_0 :: RED_MIN_THD [10:00] */
-#define BCHP_SWITCH_CORE_RED_PROFILE_N_Port_0_RED_MIN_THD_MASK 0x000007ff
-#define BCHP_SWITCH_CORE_RED_PROFILE_N_Port_0_RED_MIN_THD_SHIFT 0
-#define BCHP_SWITCH_CORE_RED_PROFILE_N_Port_0_RED_MIN_THD_DEFAULT 0x00000000
-
-/***************************************************************************
- *RED_PROFILE_N_Port_1 - RED profile N Register
- ***************************************************************************/
-/* SWITCH_CORE :: RED_PROFILE_N_Port_1 :: SWITCH_RESV [31:26] */
-#define BCHP_SWITCH_CORE_RED_PROFILE_N_Port_1_SWITCH_RESV_MASK 0xfc000000
-#define BCHP_SWITCH_CORE_RED_PROFILE_N_Port_1_SWITCH_RESV_SHIFT 26
-#define BCHP_SWITCH_CORE_RED_PROFILE_N_Port_1_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: RED_PROFILE_N_Port_1 :: RED_DROP_PROB [25:22] */
-#define BCHP_SWITCH_CORE_RED_PROFILE_N_Port_1_RED_DROP_PROB_MASK 0x03c00000
-#define BCHP_SWITCH_CORE_RED_PROFILE_N_Port_1_RED_DROP_PROB_SHIFT 22
-#define BCHP_SWITCH_CORE_RED_PROFILE_N_Port_1_RED_DROP_PROB_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: RED_PROFILE_N_Port_1 :: RED_MAX_THD [21:11] */
-#define BCHP_SWITCH_CORE_RED_PROFILE_N_Port_1_RED_MAX_THD_MASK 0x003ff800
-#define BCHP_SWITCH_CORE_RED_PROFILE_N_Port_1_RED_MAX_THD_SHIFT 11
-#define BCHP_SWITCH_CORE_RED_PROFILE_N_Port_1_RED_MAX_THD_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: RED_PROFILE_N_Port_1 :: RED_MIN_THD [10:00] */
-#define BCHP_SWITCH_CORE_RED_PROFILE_N_Port_1_RED_MIN_THD_MASK 0x000007ff
-#define BCHP_SWITCH_CORE_RED_PROFILE_N_Port_1_RED_MIN_THD_SHIFT 0
-#define BCHP_SWITCH_CORE_RED_PROFILE_N_Port_1_RED_MIN_THD_DEFAULT 0x00000000
-
-/***************************************************************************
- *RED_PROFILE_N_Port_2 - RED profile N Register
- ***************************************************************************/
-/* SWITCH_CORE :: RED_PROFILE_N_Port_2 :: SWITCH_RESV [31:26] */
-#define BCHP_SWITCH_CORE_RED_PROFILE_N_Port_2_SWITCH_RESV_MASK 0xfc000000
-#define BCHP_SWITCH_CORE_RED_PROFILE_N_Port_2_SWITCH_RESV_SHIFT 26
-#define BCHP_SWITCH_CORE_RED_PROFILE_N_Port_2_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: RED_PROFILE_N_Port_2 :: RED_DROP_PROB [25:22] */
-#define BCHP_SWITCH_CORE_RED_PROFILE_N_Port_2_RED_DROP_PROB_MASK 0x03c00000
-#define BCHP_SWITCH_CORE_RED_PROFILE_N_Port_2_RED_DROP_PROB_SHIFT 22
-#define BCHP_SWITCH_CORE_RED_PROFILE_N_Port_2_RED_DROP_PROB_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: RED_PROFILE_N_Port_2 :: RED_MAX_THD [21:11] */
-#define BCHP_SWITCH_CORE_RED_PROFILE_N_Port_2_RED_MAX_THD_MASK 0x003ff800
-#define BCHP_SWITCH_CORE_RED_PROFILE_N_Port_2_RED_MAX_THD_SHIFT 11
-#define BCHP_SWITCH_CORE_RED_PROFILE_N_Port_2_RED_MAX_THD_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: RED_PROFILE_N_Port_2 :: RED_MIN_THD [10:00] */
-#define BCHP_SWITCH_CORE_RED_PROFILE_N_Port_2_RED_MIN_THD_MASK 0x000007ff
-#define BCHP_SWITCH_CORE_RED_PROFILE_N_Port_2_RED_MIN_THD_SHIFT 0
-#define BCHP_SWITCH_CORE_RED_PROFILE_N_Port_2_RED_MIN_THD_DEFAULT 0x00000000
-
-/***************************************************************************
- *RED_PROFILE_N_Port_3 - RED profile N Register
- ***************************************************************************/
-/* SWITCH_CORE :: RED_PROFILE_N_Port_3 :: SWITCH_RESV [31:26] */
-#define BCHP_SWITCH_CORE_RED_PROFILE_N_Port_3_SWITCH_RESV_MASK 0xfc000000
-#define BCHP_SWITCH_CORE_RED_PROFILE_N_Port_3_SWITCH_RESV_SHIFT 26
-#define BCHP_SWITCH_CORE_RED_PROFILE_N_Port_3_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: RED_PROFILE_N_Port_3 :: RED_DROP_PROB [25:22] */
-#define BCHP_SWITCH_CORE_RED_PROFILE_N_Port_3_RED_DROP_PROB_MASK 0x03c00000
-#define BCHP_SWITCH_CORE_RED_PROFILE_N_Port_3_RED_DROP_PROB_SHIFT 22
-#define BCHP_SWITCH_CORE_RED_PROFILE_N_Port_3_RED_DROP_PROB_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: RED_PROFILE_N_Port_3 :: RED_MAX_THD [21:11] */
-#define BCHP_SWITCH_CORE_RED_PROFILE_N_Port_3_RED_MAX_THD_MASK 0x003ff800
-#define BCHP_SWITCH_CORE_RED_PROFILE_N_Port_3_RED_MAX_THD_SHIFT 11
-#define BCHP_SWITCH_CORE_RED_PROFILE_N_Port_3_RED_MAX_THD_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: RED_PROFILE_N_Port_3 :: RED_MIN_THD [10:00] */
-#define BCHP_SWITCH_CORE_RED_PROFILE_N_Port_3_RED_MIN_THD_MASK 0x000007ff
-#define BCHP_SWITCH_CORE_RED_PROFILE_N_Port_3_RED_MIN_THD_SHIFT 0
-#define BCHP_SWITCH_CORE_RED_PROFILE_N_Port_3_RED_MIN_THD_DEFAULT 0x00000000
-
-/***************************************************************************
- *RED_PROFILE_N_Port_4 - RED profile N Register
- ***************************************************************************/
-/* SWITCH_CORE :: RED_PROFILE_N_Port_4 :: SWITCH_RESV [31:26] */
-#define BCHP_SWITCH_CORE_RED_PROFILE_N_Port_4_SWITCH_RESV_MASK 0xfc000000
-#define BCHP_SWITCH_CORE_RED_PROFILE_N_Port_4_SWITCH_RESV_SHIFT 26
-#define BCHP_SWITCH_CORE_RED_PROFILE_N_Port_4_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: RED_PROFILE_N_Port_4 :: RED_DROP_PROB [25:22] */
-#define BCHP_SWITCH_CORE_RED_PROFILE_N_Port_4_RED_DROP_PROB_MASK 0x03c00000
-#define BCHP_SWITCH_CORE_RED_PROFILE_N_Port_4_RED_DROP_PROB_SHIFT 22
-#define BCHP_SWITCH_CORE_RED_PROFILE_N_Port_4_RED_DROP_PROB_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: RED_PROFILE_N_Port_4 :: RED_MAX_THD [21:11] */
-#define BCHP_SWITCH_CORE_RED_PROFILE_N_Port_4_RED_MAX_THD_MASK 0x003ff800
-#define BCHP_SWITCH_CORE_RED_PROFILE_N_Port_4_RED_MAX_THD_SHIFT 11
-#define BCHP_SWITCH_CORE_RED_PROFILE_N_Port_4_RED_MAX_THD_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: RED_PROFILE_N_Port_4 :: RED_MIN_THD [10:00] */
-#define BCHP_SWITCH_CORE_RED_PROFILE_N_Port_4_RED_MIN_THD_MASK 0x000007ff
-#define BCHP_SWITCH_CORE_RED_PROFILE_N_Port_4_RED_MIN_THD_SHIFT 0
-#define BCHP_SWITCH_CORE_RED_PROFILE_N_Port_4_RED_MIN_THD_DEFAULT 0x00000000
-
-/***************************************************************************
- *RED_PROFILE_N_Port_5 - RED profile N Register
- ***************************************************************************/
-/* SWITCH_CORE :: RED_PROFILE_N_Port_5 :: SWITCH_RESV [31:26] */
-#define BCHP_SWITCH_CORE_RED_PROFILE_N_Port_5_SWITCH_RESV_MASK 0xfc000000
-#define BCHP_SWITCH_CORE_RED_PROFILE_N_Port_5_SWITCH_RESV_SHIFT 26
-#define BCHP_SWITCH_CORE_RED_PROFILE_N_Port_5_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: RED_PROFILE_N_Port_5 :: RED_DROP_PROB [25:22] */
-#define BCHP_SWITCH_CORE_RED_PROFILE_N_Port_5_RED_DROP_PROB_MASK 0x03c00000
-#define BCHP_SWITCH_CORE_RED_PROFILE_N_Port_5_RED_DROP_PROB_SHIFT 22
-#define BCHP_SWITCH_CORE_RED_PROFILE_N_Port_5_RED_DROP_PROB_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: RED_PROFILE_N_Port_5 :: RED_MAX_THD [21:11] */
-#define BCHP_SWITCH_CORE_RED_PROFILE_N_Port_5_RED_MAX_THD_MASK 0x003ff800
-#define BCHP_SWITCH_CORE_RED_PROFILE_N_Port_5_RED_MAX_THD_SHIFT 11
-#define BCHP_SWITCH_CORE_RED_PROFILE_N_Port_5_RED_MAX_THD_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: RED_PROFILE_N_Port_5 :: RED_MIN_THD [10:00] */
-#define BCHP_SWITCH_CORE_RED_PROFILE_N_Port_5_RED_MIN_THD_MASK 0x000007ff
-#define BCHP_SWITCH_CORE_RED_PROFILE_N_Port_5_RED_MIN_THD_SHIFT 0
-#define BCHP_SWITCH_CORE_RED_PROFILE_N_Port_5_RED_MIN_THD_DEFAULT 0x00000000
-
-/***************************************************************************
- *RED_PROFILE_N_Port_6 - RED profile N Register
- ***************************************************************************/
-/* SWITCH_CORE :: RED_PROFILE_N_Port_6 :: SWITCH_RESV [31:26] */
-#define BCHP_SWITCH_CORE_RED_PROFILE_N_Port_6_SWITCH_RESV_MASK 0xfc000000
-#define BCHP_SWITCH_CORE_RED_PROFILE_N_Port_6_SWITCH_RESV_SHIFT 26
-#define BCHP_SWITCH_CORE_RED_PROFILE_N_Port_6_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: RED_PROFILE_N_Port_6 :: RED_DROP_PROB [25:22] */
-#define BCHP_SWITCH_CORE_RED_PROFILE_N_Port_6_RED_DROP_PROB_MASK 0x03c00000
-#define BCHP_SWITCH_CORE_RED_PROFILE_N_Port_6_RED_DROP_PROB_SHIFT 22
-#define BCHP_SWITCH_CORE_RED_PROFILE_N_Port_6_RED_DROP_PROB_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: RED_PROFILE_N_Port_6 :: RED_MAX_THD [21:11] */
-#define BCHP_SWITCH_CORE_RED_PROFILE_N_Port_6_RED_MAX_THD_MASK 0x003ff800
-#define BCHP_SWITCH_CORE_RED_PROFILE_N_Port_6_RED_MAX_THD_SHIFT 11
-#define BCHP_SWITCH_CORE_RED_PROFILE_N_Port_6_RED_MAX_THD_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: RED_PROFILE_N_Port_6 :: RED_MIN_THD [10:00] */
-#define BCHP_SWITCH_CORE_RED_PROFILE_N_Port_6_RED_MIN_THD_MASK 0x000007ff
-#define BCHP_SWITCH_CORE_RED_PROFILE_N_Port_6_RED_MIN_THD_SHIFT 0
-#define BCHP_SWITCH_CORE_RED_PROFILE_N_Port_6_RED_MIN_THD_DEFAULT 0x00000000
-
-/***************************************************************************
- *RED_PROFILE_N_Port_7 - RED profile N Register
- ***************************************************************************/
-/* SWITCH_CORE :: RED_PROFILE_N_Port_7 :: SWITCH_RESV [31:26] */
-#define BCHP_SWITCH_CORE_RED_PROFILE_N_Port_7_SWITCH_RESV_MASK 0xfc000000
-#define BCHP_SWITCH_CORE_RED_PROFILE_N_Port_7_SWITCH_RESV_SHIFT 26
-#define BCHP_SWITCH_CORE_RED_PROFILE_N_Port_7_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: RED_PROFILE_N_Port_7 :: RED_DROP_PROB [25:22] */
-#define BCHP_SWITCH_CORE_RED_PROFILE_N_Port_7_RED_DROP_PROB_MASK 0x03c00000
-#define BCHP_SWITCH_CORE_RED_PROFILE_N_Port_7_RED_DROP_PROB_SHIFT 22
-#define BCHP_SWITCH_CORE_RED_PROFILE_N_Port_7_RED_DROP_PROB_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: RED_PROFILE_N_Port_7 :: RED_MAX_THD [21:11] */
-#define BCHP_SWITCH_CORE_RED_PROFILE_N_Port_7_RED_MAX_THD_MASK 0x003ff800
-#define BCHP_SWITCH_CORE_RED_PROFILE_N_Port_7_RED_MAX_THD_SHIFT 11
-#define BCHP_SWITCH_CORE_RED_PROFILE_N_Port_7_RED_MAX_THD_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: RED_PROFILE_N_Port_7 :: RED_MIN_THD [10:00] */
-#define BCHP_SWITCH_CORE_RED_PROFILE_N_Port_7_RED_MIN_THD_MASK 0x000007ff
-#define BCHP_SWITCH_CORE_RED_PROFILE_N_Port_7_RED_MIN_THD_SHIFT 0
-#define BCHP_SWITCH_CORE_RED_PROFILE_N_Port_7_RED_MIN_THD_DEFAULT 0x00000000
-
-/***************************************************************************
- *RED_PROFILE_N_Port_8 - RED profile N Register
- ***************************************************************************/
-/* SWITCH_CORE :: RED_PROFILE_N_Port_8 :: SWITCH_RESV [31:26] */
-#define BCHP_SWITCH_CORE_RED_PROFILE_N_Port_8_SWITCH_RESV_MASK 0xfc000000
-#define BCHP_SWITCH_CORE_RED_PROFILE_N_Port_8_SWITCH_RESV_SHIFT 26
-#define BCHP_SWITCH_CORE_RED_PROFILE_N_Port_8_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: RED_PROFILE_N_Port_8 :: RED_DROP_PROB [25:22] */
-#define BCHP_SWITCH_CORE_RED_PROFILE_N_Port_8_RED_DROP_PROB_MASK 0x03c00000
-#define BCHP_SWITCH_CORE_RED_PROFILE_N_Port_8_RED_DROP_PROB_SHIFT 22
-#define BCHP_SWITCH_CORE_RED_PROFILE_N_Port_8_RED_DROP_PROB_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: RED_PROFILE_N_Port_8 :: RED_MAX_THD [21:11] */
-#define BCHP_SWITCH_CORE_RED_PROFILE_N_Port_8_RED_MAX_THD_MASK 0x003ff800
-#define BCHP_SWITCH_CORE_RED_PROFILE_N_Port_8_RED_MAX_THD_SHIFT 11
-#define BCHP_SWITCH_CORE_RED_PROFILE_N_Port_8_RED_MAX_THD_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: RED_PROFILE_N_Port_8 :: RED_MIN_THD [10:00] */
-#define BCHP_SWITCH_CORE_RED_PROFILE_N_Port_8_RED_MIN_THD_MASK 0x000007ff
-#define BCHP_SWITCH_CORE_RED_PROFILE_N_Port_8_RED_MIN_THD_SHIFT 0
-#define BCHP_SWITCH_CORE_RED_PROFILE_N_Port_8_RED_MIN_THD_DEFAULT 0x00000000
-
-/***************************************************************************
- *RED_PROFILE_N_Port_9 - RED profile N Register
- ***************************************************************************/
-/* SWITCH_CORE :: RED_PROFILE_N_Port_9 :: SWITCH_RESV [31:26] */
-#define BCHP_SWITCH_CORE_RED_PROFILE_N_Port_9_SWITCH_RESV_MASK 0xfc000000
-#define BCHP_SWITCH_CORE_RED_PROFILE_N_Port_9_SWITCH_RESV_SHIFT 26
-#define BCHP_SWITCH_CORE_RED_PROFILE_N_Port_9_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: RED_PROFILE_N_Port_9 :: RED_DROP_PROB [25:22] */
-#define BCHP_SWITCH_CORE_RED_PROFILE_N_Port_9_RED_DROP_PROB_MASK 0x03c00000
-#define BCHP_SWITCH_CORE_RED_PROFILE_N_Port_9_RED_DROP_PROB_SHIFT 22
-#define BCHP_SWITCH_CORE_RED_PROFILE_N_Port_9_RED_DROP_PROB_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: RED_PROFILE_N_Port_9 :: RED_MAX_THD [21:11] */
-#define BCHP_SWITCH_CORE_RED_PROFILE_N_Port_9_RED_MAX_THD_MASK 0x003ff800
-#define BCHP_SWITCH_CORE_RED_PROFILE_N_Port_9_RED_MAX_THD_SHIFT 11
-#define BCHP_SWITCH_CORE_RED_PROFILE_N_Port_9_RED_MAX_THD_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: RED_PROFILE_N_Port_9 :: RED_MIN_THD [10:00] */
-#define BCHP_SWITCH_CORE_RED_PROFILE_N_Port_9_RED_MIN_THD_MASK 0x000007ff
-#define BCHP_SWITCH_CORE_RED_PROFILE_N_Port_9_RED_MIN_THD_SHIFT 0
-#define BCHP_SWITCH_CORE_RED_PROFILE_N_Port_9_RED_MIN_THD_DEFAULT 0x00000000
-
-/***************************************************************************
- *RED_PROFILE_N_Port_10 - RED profile N Register
- ***************************************************************************/
-/* SWITCH_CORE :: RED_PROFILE_N_Port_10 :: SWITCH_RESV [31:26] */
-#define BCHP_SWITCH_CORE_RED_PROFILE_N_Port_10_SWITCH_RESV_MASK 0xfc000000
-#define BCHP_SWITCH_CORE_RED_PROFILE_N_Port_10_SWITCH_RESV_SHIFT 26
-#define BCHP_SWITCH_CORE_RED_PROFILE_N_Port_10_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: RED_PROFILE_N_Port_10 :: RED_DROP_PROB [25:22] */
-#define BCHP_SWITCH_CORE_RED_PROFILE_N_Port_10_RED_DROP_PROB_MASK 0x03c00000
-#define BCHP_SWITCH_CORE_RED_PROFILE_N_Port_10_RED_DROP_PROB_SHIFT 22
-#define BCHP_SWITCH_CORE_RED_PROFILE_N_Port_10_RED_DROP_PROB_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: RED_PROFILE_N_Port_10 :: RED_MAX_THD [21:11] */
-#define BCHP_SWITCH_CORE_RED_PROFILE_N_Port_10_RED_MAX_THD_MASK 0x003ff800
-#define BCHP_SWITCH_CORE_RED_PROFILE_N_Port_10_RED_MAX_THD_SHIFT 11
-#define BCHP_SWITCH_CORE_RED_PROFILE_N_Port_10_RED_MAX_THD_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: RED_PROFILE_N_Port_10 :: RED_MIN_THD [10:00] */
-#define BCHP_SWITCH_CORE_RED_PROFILE_N_Port_10_RED_MIN_THD_MASK 0x000007ff
-#define BCHP_SWITCH_CORE_RED_PROFILE_N_Port_10_RED_MIN_THD_SHIFT 0
-#define BCHP_SWITCH_CORE_RED_PROFILE_N_Port_10_RED_MIN_THD_DEFAULT 0x00000000
-
-/***************************************************************************
- *RED_PROFILE_N_Port_11 - RED profile N Register
- ***************************************************************************/
-/* SWITCH_CORE :: RED_PROFILE_N_Port_11 :: SWITCH_RESV [31:26] */
-#define BCHP_SWITCH_CORE_RED_PROFILE_N_Port_11_SWITCH_RESV_MASK 0xfc000000
-#define BCHP_SWITCH_CORE_RED_PROFILE_N_Port_11_SWITCH_RESV_SHIFT 26
-#define BCHP_SWITCH_CORE_RED_PROFILE_N_Port_11_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: RED_PROFILE_N_Port_11 :: RED_DROP_PROB [25:22] */
-#define BCHP_SWITCH_CORE_RED_PROFILE_N_Port_11_RED_DROP_PROB_MASK 0x03c00000
-#define BCHP_SWITCH_CORE_RED_PROFILE_N_Port_11_RED_DROP_PROB_SHIFT 22
-#define BCHP_SWITCH_CORE_RED_PROFILE_N_Port_11_RED_DROP_PROB_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: RED_PROFILE_N_Port_11 :: RED_MAX_THD [21:11] */
-#define BCHP_SWITCH_CORE_RED_PROFILE_N_Port_11_RED_MAX_THD_MASK 0x003ff800
-#define BCHP_SWITCH_CORE_RED_PROFILE_N_Port_11_RED_MAX_THD_SHIFT 11
-#define BCHP_SWITCH_CORE_RED_PROFILE_N_Port_11_RED_MAX_THD_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: RED_PROFILE_N_Port_11 :: RED_MIN_THD [10:00] */
-#define BCHP_SWITCH_CORE_RED_PROFILE_N_Port_11_RED_MIN_THD_MASK 0x000007ff
-#define BCHP_SWITCH_CORE_RED_PROFILE_N_Port_11_RED_MIN_THD_SHIFT 0
-#define BCHP_SWITCH_CORE_RED_PROFILE_N_Port_11_RED_MIN_THD_DEFAULT 0x00000000
-
-/***************************************************************************
- *RED_PROFILE_N_Port_12 - RED profile N Register
- ***************************************************************************/
-/* SWITCH_CORE :: RED_PROFILE_N_Port_12 :: SWITCH_RESV [31:26] */
-#define BCHP_SWITCH_CORE_RED_PROFILE_N_Port_12_SWITCH_RESV_MASK 0xfc000000
-#define BCHP_SWITCH_CORE_RED_PROFILE_N_Port_12_SWITCH_RESV_SHIFT 26
-#define BCHP_SWITCH_CORE_RED_PROFILE_N_Port_12_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: RED_PROFILE_N_Port_12 :: RED_DROP_PROB [25:22] */
-#define BCHP_SWITCH_CORE_RED_PROFILE_N_Port_12_RED_DROP_PROB_MASK 0x03c00000
-#define BCHP_SWITCH_CORE_RED_PROFILE_N_Port_12_RED_DROP_PROB_SHIFT 22
-#define BCHP_SWITCH_CORE_RED_PROFILE_N_Port_12_RED_DROP_PROB_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: RED_PROFILE_N_Port_12 :: RED_MAX_THD [21:11] */
-#define BCHP_SWITCH_CORE_RED_PROFILE_N_Port_12_RED_MAX_THD_MASK 0x003ff800
-#define BCHP_SWITCH_CORE_RED_PROFILE_N_Port_12_RED_MAX_THD_SHIFT 11
-#define BCHP_SWITCH_CORE_RED_PROFILE_N_Port_12_RED_MAX_THD_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: RED_PROFILE_N_Port_12 :: RED_MIN_THD [10:00] */
-#define BCHP_SWITCH_CORE_RED_PROFILE_N_Port_12_RED_MIN_THD_MASK 0x000007ff
-#define BCHP_SWITCH_CORE_RED_PROFILE_N_Port_12_RED_MIN_THD_SHIFT 0
-#define BCHP_SWITCH_CORE_RED_PROFILE_N_Port_12_RED_MIN_THD_DEFAULT 0x00000000
-
-/***************************************************************************
- *RED_PROFILE_N_Port_13 - RED profile N Register
- ***************************************************************************/
-/* SWITCH_CORE :: RED_PROFILE_N_Port_13 :: SWITCH_RESV [31:26] */
-#define BCHP_SWITCH_CORE_RED_PROFILE_N_Port_13_SWITCH_RESV_MASK 0xfc000000
-#define BCHP_SWITCH_CORE_RED_PROFILE_N_Port_13_SWITCH_RESV_SHIFT 26
-#define BCHP_SWITCH_CORE_RED_PROFILE_N_Port_13_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: RED_PROFILE_N_Port_13 :: RED_DROP_PROB [25:22] */
-#define BCHP_SWITCH_CORE_RED_PROFILE_N_Port_13_RED_DROP_PROB_MASK 0x03c00000
-#define BCHP_SWITCH_CORE_RED_PROFILE_N_Port_13_RED_DROP_PROB_SHIFT 22
-#define BCHP_SWITCH_CORE_RED_PROFILE_N_Port_13_RED_DROP_PROB_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: RED_PROFILE_N_Port_13 :: RED_MAX_THD [21:11] */
-#define BCHP_SWITCH_CORE_RED_PROFILE_N_Port_13_RED_MAX_THD_MASK 0x003ff800
-#define BCHP_SWITCH_CORE_RED_PROFILE_N_Port_13_RED_MAX_THD_SHIFT 11
-#define BCHP_SWITCH_CORE_RED_PROFILE_N_Port_13_RED_MAX_THD_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: RED_PROFILE_N_Port_13 :: RED_MIN_THD [10:00] */
-#define BCHP_SWITCH_CORE_RED_PROFILE_N_Port_13_RED_MIN_THD_MASK 0x000007ff
-#define BCHP_SWITCH_CORE_RED_PROFILE_N_Port_13_RED_MIN_THD_SHIFT 0
-#define BCHP_SWITCH_CORE_RED_PROFILE_N_Port_13_RED_MIN_THD_DEFAULT 0x00000000
-
-/***************************************************************************
- *RED_PROFILE_N_Port_14 - RED profile N Register
- ***************************************************************************/
-/* SWITCH_CORE :: RED_PROFILE_N_Port_14 :: SWITCH_RESV [31:26] */
-#define BCHP_SWITCH_CORE_RED_PROFILE_N_Port_14_SWITCH_RESV_MASK 0xfc000000
-#define BCHP_SWITCH_CORE_RED_PROFILE_N_Port_14_SWITCH_RESV_SHIFT 26
-#define BCHP_SWITCH_CORE_RED_PROFILE_N_Port_14_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: RED_PROFILE_N_Port_14 :: RED_DROP_PROB [25:22] */
-#define BCHP_SWITCH_CORE_RED_PROFILE_N_Port_14_RED_DROP_PROB_MASK 0x03c00000
-#define BCHP_SWITCH_CORE_RED_PROFILE_N_Port_14_RED_DROP_PROB_SHIFT 22
-#define BCHP_SWITCH_CORE_RED_PROFILE_N_Port_14_RED_DROP_PROB_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: RED_PROFILE_N_Port_14 :: RED_MAX_THD [21:11] */
-#define BCHP_SWITCH_CORE_RED_PROFILE_N_Port_14_RED_MAX_THD_MASK 0x003ff800
-#define BCHP_SWITCH_CORE_RED_PROFILE_N_Port_14_RED_MAX_THD_SHIFT 11
-#define BCHP_SWITCH_CORE_RED_PROFILE_N_Port_14_RED_MAX_THD_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: RED_PROFILE_N_Port_14 :: RED_MIN_THD [10:00] */
-#define BCHP_SWITCH_CORE_RED_PROFILE_N_Port_14_RED_MIN_THD_MASK 0x000007ff
-#define BCHP_SWITCH_CORE_RED_PROFILE_N_Port_14_RED_MIN_THD_SHIFT 0
-#define BCHP_SWITCH_CORE_RED_PROFILE_N_Port_14_RED_MIN_THD_DEFAULT 0x00000000
-
-/***************************************************************************
- *RED_PROFILE_N_Port_15 - RED profile N Register
- ***************************************************************************/
-/* SWITCH_CORE :: RED_PROFILE_N_Port_15 :: SWITCH_RESV [31:26] */
-#define BCHP_SWITCH_CORE_RED_PROFILE_N_Port_15_SWITCH_RESV_MASK 0xfc000000
-#define BCHP_SWITCH_CORE_RED_PROFILE_N_Port_15_SWITCH_RESV_SHIFT 26
-#define BCHP_SWITCH_CORE_RED_PROFILE_N_Port_15_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: RED_PROFILE_N_Port_15 :: RED_DROP_PROB [25:22] */
-#define BCHP_SWITCH_CORE_RED_PROFILE_N_Port_15_RED_DROP_PROB_MASK 0x03c00000
-#define BCHP_SWITCH_CORE_RED_PROFILE_N_Port_15_RED_DROP_PROB_SHIFT 22
-#define BCHP_SWITCH_CORE_RED_PROFILE_N_Port_15_RED_DROP_PROB_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: RED_PROFILE_N_Port_15 :: RED_MAX_THD [21:11] */
-#define BCHP_SWITCH_CORE_RED_PROFILE_N_Port_15_RED_MAX_THD_MASK 0x003ff800
-#define BCHP_SWITCH_CORE_RED_PROFILE_N_Port_15_RED_MAX_THD_SHIFT 11
-#define BCHP_SWITCH_CORE_RED_PROFILE_N_Port_15_RED_MAX_THD_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: RED_PROFILE_N_Port_15 :: RED_MIN_THD [10:00] */
-#define BCHP_SWITCH_CORE_RED_PROFILE_N_Port_15_RED_MIN_THD_MASK 0x000007ff
-#define BCHP_SWITCH_CORE_RED_PROFILE_N_Port_15_RED_MIN_THD_SHIFT 0
-#define BCHP_SWITCH_CORE_RED_PROFILE_N_Port_15_RED_MIN_THD_DEFAULT 0x00000000
-
-/***************************************************************************
- *RED_DROP_CNTR_RST - RED Drop Counter Reset Register
- ***************************************************************************/
-/* SWITCH_CORE :: RED_DROP_CNTR_RST :: reserved_for_padding0 [31:16] */
-#define BCHP_SWITCH_CORE_RED_DROP_CNTR_RST_reserved_for_padding0_MASK 0xffff0000
-#define BCHP_SWITCH_CORE_RED_DROP_CNTR_RST_reserved_for_padding0_SHIFT 16
-
-/* SWITCH_CORE :: RED_DROP_CNTR_RST :: SWITCH_RESV [15:09] */
-#define BCHP_SWITCH_CORE_RED_DROP_CNTR_RST_SWITCH_RESV_MASK 0x0000fe00
-#define BCHP_SWITCH_CORE_RED_DROP_CNTR_RST_SWITCH_RESV_SHIFT 9
-#define BCHP_SWITCH_CORE_RED_DROP_CNTR_RST_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: RED_DROP_CNTR_RST :: RED_DROP_CNTR_RST [08:00] */
-#define BCHP_SWITCH_CORE_RED_DROP_CNTR_RST_RED_DROP_CNTR_RST_MASK 0x000001ff
-#define BCHP_SWITCH_CORE_RED_DROP_CNTR_RST_RED_DROP_CNTR_RST_SHIFT 0
-#define BCHP_SWITCH_CORE_RED_DROP_CNTR_RST_RED_DROP_CNTR_RST_DEFAULT 0x00000000
-
-/***************************************************************************
- *PN_PORT_RED_PKT_DROP_CNTR_Port_0 - PORT N RED Packet Drop Counter Register
- ***************************************************************************/
-/* SWITCH_CORE :: PN_PORT_RED_PKT_DROP_CNTR_Port_0 :: RED_PKT_DROP_CNTR [31:00] */
-#define BCHP_SWITCH_CORE_PN_PORT_RED_PKT_DROP_CNTR_Port_0_RED_PKT_DROP_CNTR_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_PN_PORT_RED_PKT_DROP_CNTR_Port_0_RED_PKT_DROP_CNTR_SHIFT 0
-#define BCHP_SWITCH_CORE_PN_PORT_RED_PKT_DROP_CNTR_Port_0_RED_PKT_DROP_CNTR_DEFAULT 0x00000000
-
-/***************************************************************************
- *PN_PORT_RED_PKT_DROP_CNTR_Port_1 - PORT N RED Packet Drop Counter Register
- ***************************************************************************/
-/* SWITCH_CORE :: PN_PORT_RED_PKT_DROP_CNTR_Port_1 :: RED_PKT_DROP_CNTR [31:00] */
-#define BCHP_SWITCH_CORE_PN_PORT_RED_PKT_DROP_CNTR_Port_1_RED_PKT_DROP_CNTR_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_PN_PORT_RED_PKT_DROP_CNTR_Port_1_RED_PKT_DROP_CNTR_SHIFT 0
-#define BCHP_SWITCH_CORE_PN_PORT_RED_PKT_DROP_CNTR_Port_1_RED_PKT_DROP_CNTR_DEFAULT 0x00000000
-
-/***************************************************************************
- *PN_PORT_RED_PKT_DROP_CNTR_Port_2 - PORT N RED Packet Drop Counter Register
- ***************************************************************************/
-/* SWITCH_CORE :: PN_PORT_RED_PKT_DROP_CNTR_Port_2 :: RED_PKT_DROP_CNTR [31:00] */
-#define BCHP_SWITCH_CORE_PN_PORT_RED_PKT_DROP_CNTR_Port_2_RED_PKT_DROP_CNTR_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_PN_PORT_RED_PKT_DROP_CNTR_Port_2_RED_PKT_DROP_CNTR_SHIFT 0
-#define BCHP_SWITCH_CORE_PN_PORT_RED_PKT_DROP_CNTR_Port_2_RED_PKT_DROP_CNTR_DEFAULT 0x00000000
-
-/***************************************************************************
- *PN_PORT_RED_PKT_DROP_CNTR_Port_3 - PORT N RED Packet Drop Counter Register
- ***************************************************************************/
-/* SWITCH_CORE :: PN_PORT_RED_PKT_DROP_CNTR_Port_3 :: RED_PKT_DROP_CNTR [31:00] */
-#define BCHP_SWITCH_CORE_PN_PORT_RED_PKT_DROP_CNTR_Port_3_RED_PKT_DROP_CNTR_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_PN_PORT_RED_PKT_DROP_CNTR_Port_3_RED_PKT_DROP_CNTR_SHIFT 0
-#define BCHP_SWITCH_CORE_PN_PORT_RED_PKT_DROP_CNTR_Port_3_RED_PKT_DROP_CNTR_DEFAULT 0x00000000
-
-/***************************************************************************
- *PN_PORT_RED_PKT_DROP_CNTR_Port_4 - PORT N RED Packet Drop Counter Register
- ***************************************************************************/
-/* SWITCH_CORE :: PN_PORT_RED_PKT_DROP_CNTR_Port_4 :: RED_PKT_DROP_CNTR [31:00] */
-#define BCHP_SWITCH_CORE_PN_PORT_RED_PKT_DROP_CNTR_Port_4_RED_PKT_DROP_CNTR_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_PN_PORT_RED_PKT_DROP_CNTR_Port_4_RED_PKT_DROP_CNTR_SHIFT 0
-#define BCHP_SWITCH_CORE_PN_PORT_RED_PKT_DROP_CNTR_Port_4_RED_PKT_DROP_CNTR_DEFAULT 0x00000000
-
-/***************************************************************************
- *PN_PORT_RED_PKT_DROP_CNTR_Port_5 - PORT N RED Packet Drop Counter Register
- ***************************************************************************/
-/* SWITCH_CORE :: PN_PORT_RED_PKT_DROP_CNTR_Port_5 :: RED_PKT_DROP_CNTR [31:00] */
-#define BCHP_SWITCH_CORE_PN_PORT_RED_PKT_DROP_CNTR_Port_5_RED_PKT_DROP_CNTR_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_PN_PORT_RED_PKT_DROP_CNTR_Port_5_RED_PKT_DROP_CNTR_SHIFT 0
-#define BCHP_SWITCH_CORE_PN_PORT_RED_PKT_DROP_CNTR_Port_5_RED_PKT_DROP_CNTR_DEFAULT 0x00000000
-
-/***************************************************************************
- *P7_PORT_RED_PKT_DROP_CNTR - PORT 7 RED Packet Drop Counter Register
- ***************************************************************************/
-/* SWITCH_CORE :: P7_PORT_RED_PKT_DROP_CNTR :: RED_PKT_DROP_CNTR [31:00] */
-#define BCHP_SWITCH_CORE_P7_PORT_RED_PKT_DROP_CNTR_RED_PKT_DROP_CNTR_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_P7_PORT_RED_PKT_DROP_CNTR_RED_PKT_DROP_CNTR_SHIFT 0
-#define BCHP_SWITCH_CORE_P7_PORT_RED_PKT_DROP_CNTR_RED_PKT_DROP_CNTR_DEFAULT 0x00000000
-
-/***************************************************************************
- *IMP_PORT_RED_PKT_DROP_CNTR - PORT 8 RED Packet Drop Counter Register
- ***************************************************************************/
-/* SWITCH_CORE :: IMP_PORT_RED_PKT_DROP_CNTR :: RED_PKT_DROP_CNTR [31:00] */
-#define BCHP_SWITCH_CORE_IMP_PORT_RED_PKT_DROP_CNTR_RED_PKT_DROP_CNTR_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_IMP_PORT_RED_PKT_DROP_CNTR_RED_PKT_DROP_CNTR_SHIFT 0
-#define BCHP_SWITCH_CORE_IMP_PORT_RED_PKT_DROP_CNTR_RED_PKT_DROP_CNTR_DEFAULT 0x00000000
-
-/***************************************************************************
- *PN_PORT_RED_BYTE_DROP_CNTR_Port_0 - PORT N RED Byte Drop Counter Register
- ***************************************************************************/
-/* SWITCH_CORE :: PN_PORT_RED_BYTE_DROP_CNTR_Port_0 :: RED_BYTE_DROP_CNTR [63:00] */
-#define BCHP_SWITCH_CORE_PN_PORT_RED_BYTE_DROP_CNTR_Port_0_RED_BYTE_DROP_CNTR_MASK 0x00000000ffffffff
-#define BCHP_SWITCH_CORE_PN_PORT_RED_BYTE_DROP_CNTR_Port_0_RED_BYTE_DROP_CNTR_SHIFT 0
-#define BCHP_SWITCH_CORE_PN_PORT_RED_BYTE_DROP_CNTR_Port_0_RED_BYTE_DROP_CNTR_DEFAULT 0x0000000000000000
-
-/***************************************************************************
- *PN_PORT_RED_BYTE_DROP_CNTR_Port_1 - PORT N RED Byte Drop Counter Register
- ***************************************************************************/
-/* SWITCH_CORE :: PN_PORT_RED_BYTE_DROP_CNTR_Port_1 :: RED_BYTE_DROP_CNTR [63:00] */
-#define BCHP_SWITCH_CORE_PN_PORT_RED_BYTE_DROP_CNTR_Port_1_RED_BYTE_DROP_CNTR_MASK 0x00000000ffffffff
-#define BCHP_SWITCH_CORE_PN_PORT_RED_BYTE_DROP_CNTR_Port_1_RED_BYTE_DROP_CNTR_SHIFT 0
-#define BCHP_SWITCH_CORE_PN_PORT_RED_BYTE_DROP_CNTR_Port_1_RED_BYTE_DROP_CNTR_DEFAULT 0x0000000000000000
-
-/***************************************************************************
- *PN_PORT_RED_BYTE_DROP_CNTR_Port_2 - PORT N RED Byte Drop Counter Register
- ***************************************************************************/
-/* SWITCH_CORE :: PN_PORT_RED_BYTE_DROP_CNTR_Port_2 :: RED_BYTE_DROP_CNTR [63:00] */
-#define BCHP_SWITCH_CORE_PN_PORT_RED_BYTE_DROP_CNTR_Port_2_RED_BYTE_DROP_CNTR_MASK 0x00000000ffffffff
-#define BCHP_SWITCH_CORE_PN_PORT_RED_BYTE_DROP_CNTR_Port_2_RED_BYTE_DROP_CNTR_SHIFT 0
-#define BCHP_SWITCH_CORE_PN_PORT_RED_BYTE_DROP_CNTR_Port_2_RED_BYTE_DROP_CNTR_DEFAULT 0x0000000000000000
-
-/***************************************************************************
- *PN_PORT_RED_BYTE_DROP_CNTR_Port_3 - PORT N RED Byte Drop Counter Register
- ***************************************************************************/
-/* SWITCH_CORE :: PN_PORT_RED_BYTE_DROP_CNTR_Port_3 :: RED_BYTE_DROP_CNTR [63:00] */
-#define BCHP_SWITCH_CORE_PN_PORT_RED_BYTE_DROP_CNTR_Port_3_RED_BYTE_DROP_CNTR_MASK 0x00000000ffffffff
-#define BCHP_SWITCH_CORE_PN_PORT_RED_BYTE_DROP_CNTR_Port_3_RED_BYTE_DROP_CNTR_SHIFT 0
-#define BCHP_SWITCH_CORE_PN_PORT_RED_BYTE_DROP_CNTR_Port_3_RED_BYTE_DROP_CNTR_DEFAULT 0x0000000000000000
-
-/***************************************************************************
- *PN_PORT_RED_BYTE_DROP_CNTR_Port_4 - PORT N RED Byte Drop Counter Register
- ***************************************************************************/
-/* SWITCH_CORE :: PN_PORT_RED_BYTE_DROP_CNTR_Port_4 :: RED_BYTE_DROP_CNTR [63:00] */
-#define BCHP_SWITCH_CORE_PN_PORT_RED_BYTE_DROP_CNTR_Port_4_RED_BYTE_DROP_CNTR_MASK 0x00000000ffffffff
-#define BCHP_SWITCH_CORE_PN_PORT_RED_BYTE_DROP_CNTR_Port_4_RED_BYTE_DROP_CNTR_SHIFT 0
-#define BCHP_SWITCH_CORE_PN_PORT_RED_BYTE_DROP_CNTR_Port_4_RED_BYTE_DROP_CNTR_DEFAULT 0x0000000000000000
-
-/***************************************************************************
- *PN_PORT_RED_BYTE_DROP_CNTR_Port_5 - PORT N RED Byte Drop Counter Register
- ***************************************************************************/
-/* SWITCH_CORE :: PN_PORT_RED_BYTE_DROP_CNTR_Port_5 :: RED_BYTE_DROP_CNTR [63:00] */
-#define BCHP_SWITCH_CORE_PN_PORT_RED_BYTE_DROP_CNTR_Port_5_RED_BYTE_DROP_CNTR_MASK 0x00000000ffffffff
-#define BCHP_SWITCH_CORE_PN_PORT_RED_BYTE_DROP_CNTR_Port_5_RED_BYTE_DROP_CNTR_SHIFT 0
-#define BCHP_SWITCH_CORE_PN_PORT_RED_BYTE_DROP_CNTR_Port_5_RED_BYTE_DROP_CNTR_DEFAULT 0x0000000000000000
-
-/***************************************************************************
- *P7_PORT_RED_BYTE_DROP_CNTR - PORT 7 RED Byte Drop Counter Register
- ***************************************************************************/
-/* SWITCH_CORE :: P7_PORT_RED_BYTE_DROP_CNTR :: RED_BYTE_DROP_CNTR [63:00] */
-#define BCHP_SWITCH_CORE_P7_PORT_RED_BYTE_DROP_CNTR_RED_BYTE_DROP_CNTR_MASK 0x00000000ffffffff
-#define BCHP_SWITCH_CORE_P7_PORT_RED_BYTE_DROP_CNTR_RED_BYTE_DROP_CNTR_SHIFT 0
-#define BCHP_SWITCH_CORE_P7_PORT_RED_BYTE_DROP_CNTR_RED_BYTE_DROP_CNTR_DEFAULT 0x0000000000000000
-
-/***************************************************************************
- *IMP_PORT_RED_BYTE_DROP_CNTR - PORT 8 RED Byte Drop Counter Register
- ***************************************************************************/
-/* SWITCH_CORE :: IMP_PORT_RED_BYTE_DROP_CNTR :: RED_BYTE_DROP_CNTR [63:00] */
-#define BCHP_SWITCH_CORE_IMP_PORT_RED_BYTE_DROP_CNTR_RED_BYTE_DROP_CNTR_MASK 0x00000000ffffffff
-#define BCHP_SWITCH_CORE_IMP_PORT_RED_BYTE_DROP_CNTR_RED_BYTE_DROP_CNTR_SHIFT 0
-#define BCHP_SWITCH_CORE_IMP_PORT_RED_BYTE_DROP_CNTR_RED_BYTE_DROP_CNTR_DEFAULT 0x0000000000000000
-
-/***************************************************************************
- *CFP_ACC - CFP Access Registers
- ***************************************************************************/
-/* SWITCH_CORE :: CFP_ACC :: RD_STS [31:28] */
-#define BCHP_SWITCH_CORE_CFP_ACC_RD_STS_MASK 0xf0000000
-#define BCHP_SWITCH_CORE_CFP_ACC_RD_STS_SHIFT 28
-#define BCHP_SWITCH_CORE_CFP_ACC_RD_STS_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: CFP_ACC :: SERCH_STS [27:27] */
-#define BCHP_SWITCH_CORE_CFP_ACC_SERCH_STS_MASK 0x08000000
-#define BCHP_SWITCH_CORE_CFP_ACC_SERCH_STS_SHIFT 27
-#define BCHP_SWITCH_CORE_CFP_ACC_SERCH_STS_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: CFP_ACC :: SWITCH_RESV_1 [26:24] */
-#define BCHP_SWITCH_CORE_CFP_ACC_SWITCH_RESV_1_MASK 0x07000000
-#define BCHP_SWITCH_CORE_CFP_ACC_SWITCH_RESV_1_SHIFT 24
-#define BCHP_SWITCH_CORE_CFP_ACC_SWITCH_RESV_1_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: CFP_ACC :: XCESS_ADDR [23:16] */
-#define BCHP_SWITCH_CORE_CFP_ACC_XCESS_ADDR_MASK 0x00ff0000
-#define BCHP_SWITCH_CORE_CFP_ACC_XCESS_ADDR_SHIFT 16
-#define BCHP_SWITCH_CORE_CFP_ACC_XCESS_ADDR_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: CFP_ACC :: TCAM_RST [15:15] */
-#define BCHP_SWITCH_CORE_CFP_ACC_TCAM_RST_MASK 0x00008000
-#define BCHP_SWITCH_CORE_CFP_ACC_TCAM_RST_SHIFT 15
-#define BCHP_SWITCH_CORE_CFP_ACC_TCAM_RST_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: CFP_ACC :: RAM_SEL [14:10] */
-#define BCHP_SWITCH_CORE_CFP_ACC_RAM_SEL_MASK 0x00007c00
-#define BCHP_SWITCH_CORE_CFP_ACC_RAM_SEL_SHIFT 10
-#define BCHP_SWITCH_CORE_CFP_ACC_RAM_SEL_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: CFP_ACC :: SWITCH_RESV_0 [09:06] */
-#define BCHP_SWITCH_CORE_CFP_ACC_SWITCH_RESV_0_MASK 0x000003c0
-#define BCHP_SWITCH_CORE_CFP_ACC_SWITCH_RESV_0_SHIFT 6
-#define BCHP_SWITCH_CORE_CFP_ACC_SWITCH_RESV_0_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: CFP_ACC :: KEY_0_1_RAW_ENC [05:05] */
-#define BCHP_SWITCH_CORE_CFP_ACC_KEY_0_1_RAW_ENC_MASK 0x00000020
-#define BCHP_SWITCH_CORE_CFP_ACC_KEY_0_1_RAW_ENC_SHIFT 5
-#define BCHP_SWITCH_CORE_CFP_ACC_KEY_0_1_RAW_ENC_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: CFP_ACC :: CFP_RAM_CLEAR [04:04] */
-#define BCHP_SWITCH_CORE_CFP_ACC_CFP_RAM_CLEAR_MASK 0x00000010
-#define BCHP_SWITCH_CORE_CFP_ACC_CFP_RAM_CLEAR_SHIFT 4
-#define BCHP_SWITCH_CORE_CFP_ACC_CFP_RAM_CLEAR_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: CFP_ACC :: OP_SEL [03:01] */
-#define BCHP_SWITCH_CORE_CFP_ACC_OP_SEL_MASK 0x0000000e
-#define BCHP_SWITCH_CORE_CFP_ACC_OP_SEL_SHIFT 1
-#define BCHP_SWITCH_CORE_CFP_ACC_OP_SEL_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: CFP_ACC :: OP_STR_DONE [00:00] */
-#define BCHP_SWITCH_CORE_CFP_ACC_OP_STR_DONE_MASK 0x00000001
-#define BCHP_SWITCH_CORE_CFP_ACC_OP_STR_DONE_SHIFT 0
-#define BCHP_SWITCH_CORE_CFP_ACC_OP_STR_DONE_DEFAULT 0x00000000
-
-/***************************************************************************
- *RATE_METER_GLOBAL_CTL - CFP RATE METER Global Control Registers
- ***************************************************************************/
-/* SWITCH_CORE :: RATE_METER_GLOBAL_CTL :: reserved_for_padding0 [31:16] */
-#define BCHP_SWITCH_CORE_RATE_METER_GLOBAL_CTL_reserved_for_padding0_MASK 0xffff0000
-#define BCHP_SWITCH_CORE_RATE_METER_GLOBAL_CTL_reserved_for_padding0_SHIFT 16
-
-/* SWITCH_CORE :: RATE_METER_GLOBAL_CTL :: SWITCH_RESV [15:03] */
-#define BCHP_SWITCH_CORE_RATE_METER_GLOBAL_CTL_SWITCH_RESV_MASK 0x0000fff8
-#define BCHP_SWITCH_CORE_RATE_METER_GLOBAL_CTL_SWITCH_RESV_SHIFT 3
-#define BCHP_SWITCH_CORE_RATE_METER_GLOBAL_CTL_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: RATE_METER_GLOBAL_CTL :: RATE_REFRESH_EN [02:02] */
-#define BCHP_SWITCH_CORE_RATE_METER_GLOBAL_CTL_RATE_REFRESH_EN_MASK 0x00000004
-#define BCHP_SWITCH_CORE_RATE_METER_GLOBAL_CTL_RATE_REFRESH_EN_SHIFT 2
-#define BCHP_SWITCH_CORE_RATE_METER_GLOBAL_CTL_RATE_REFRESH_EN_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: RATE_METER_GLOBAL_CTL :: PKT_LEN_CORR [01:00] */
-#define BCHP_SWITCH_CORE_RATE_METER_GLOBAL_CTL_PKT_LEN_CORR_MASK 0x00000003
-#define BCHP_SWITCH_CORE_RATE_METER_GLOBAL_CTL_PKT_LEN_CORR_SHIFT 0
-#define BCHP_SWITCH_CORE_RATE_METER_GLOBAL_CTL_PKT_LEN_CORR_DEFAULT 0x00000000
-
-/***************************************************************************
- *CFP_DATA_Port_0 - CFP TCAM Data X Registers
- ***************************************************************************/
-/* SWITCH_CORE :: CFP_DATA_Port_0 :: TCAM_DATA [31:00] */
-#define BCHP_SWITCH_CORE_CFP_DATA_Port_0_TCAM_DATA_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_CFP_DATA_Port_0_TCAM_DATA_SHIFT 0
-#define BCHP_SWITCH_CORE_CFP_DATA_Port_0_TCAM_DATA_DEFAULT 0x00000000
-
-/***************************************************************************
- *CFP_DATA_Port_1 - CFP TCAM Data X Registers
- ***************************************************************************/
-/* SWITCH_CORE :: CFP_DATA_Port_1 :: TCAM_DATA [31:00] */
-#define BCHP_SWITCH_CORE_CFP_DATA_Port_1_TCAM_DATA_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_CFP_DATA_Port_1_TCAM_DATA_SHIFT 0
-#define BCHP_SWITCH_CORE_CFP_DATA_Port_1_TCAM_DATA_DEFAULT 0x00000000
-
-/***************************************************************************
- *CFP_DATA_Port_2 - CFP TCAM Data X Registers
- ***************************************************************************/
-/* SWITCH_CORE :: CFP_DATA_Port_2 :: TCAM_DATA [31:00] */
-#define BCHP_SWITCH_CORE_CFP_DATA_Port_2_TCAM_DATA_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_CFP_DATA_Port_2_TCAM_DATA_SHIFT 0
-#define BCHP_SWITCH_CORE_CFP_DATA_Port_2_TCAM_DATA_DEFAULT 0x00000000
-
-/***************************************************************************
- *CFP_DATA_Port_3 - CFP TCAM Data X Registers
- ***************************************************************************/
-/* SWITCH_CORE :: CFP_DATA_Port_3 :: TCAM_DATA [31:00] */
-#define BCHP_SWITCH_CORE_CFP_DATA_Port_3_TCAM_DATA_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_CFP_DATA_Port_3_TCAM_DATA_SHIFT 0
-#define BCHP_SWITCH_CORE_CFP_DATA_Port_3_TCAM_DATA_DEFAULT 0x00000000
-
-/***************************************************************************
- *CFP_DATA_Port_4 - CFP TCAM Data X Registers
- ***************************************************************************/
-/* SWITCH_CORE :: CFP_DATA_Port_4 :: TCAM_DATA [31:00] */
-#define BCHP_SWITCH_CORE_CFP_DATA_Port_4_TCAM_DATA_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_CFP_DATA_Port_4_TCAM_DATA_SHIFT 0
-#define BCHP_SWITCH_CORE_CFP_DATA_Port_4_TCAM_DATA_DEFAULT 0x00000000
-
-/***************************************************************************
- *CFP_DATA_Port_5 - CFP TCAM Data X Registers
- ***************************************************************************/
-/* SWITCH_CORE :: CFP_DATA_Port_5 :: TCAM_DATA [31:00] */
-#define BCHP_SWITCH_CORE_CFP_DATA_Port_5_TCAM_DATA_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_CFP_DATA_Port_5_TCAM_DATA_SHIFT 0
-#define BCHP_SWITCH_CORE_CFP_DATA_Port_5_TCAM_DATA_DEFAULT 0x00000000
-
-/***************************************************************************
- *CFP_DATA_Port_6 - CFP TCAM Data X Registers
- ***************************************************************************/
-/* SWITCH_CORE :: CFP_DATA_Port_6 :: TCAM_DATA [31:00] */
-#define BCHP_SWITCH_CORE_CFP_DATA_Port_6_TCAM_DATA_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_CFP_DATA_Port_6_TCAM_DATA_SHIFT 0
-#define BCHP_SWITCH_CORE_CFP_DATA_Port_6_TCAM_DATA_DEFAULT 0x00000000
-
-/***************************************************************************
- *CFP_DATA_Port_7 - CFP TCAM Data X Registers
- ***************************************************************************/
-/* SWITCH_CORE :: CFP_DATA_Port_7 :: TCAM_DATA [31:00] */
-#define BCHP_SWITCH_CORE_CFP_DATA_Port_7_TCAM_DATA_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_CFP_DATA_Port_7_TCAM_DATA_SHIFT 0
-#define BCHP_SWITCH_CORE_CFP_DATA_Port_7_TCAM_DATA_DEFAULT 0x00000000
-
-/***************************************************************************
- *CFP_MASK_Port_0 - CFP TCAM Mask X Registers
- ***************************************************************************/
-/* SWITCH_CORE :: CFP_MASK_Port_0 :: TCAM_MASK [31:00] */
-#define BCHP_SWITCH_CORE_CFP_MASK_Port_0_TCAM_MASK_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_CFP_MASK_Port_0_TCAM_MASK_SHIFT 0
-#define BCHP_SWITCH_CORE_CFP_MASK_Port_0_TCAM_MASK_DEFAULT 0x00000000
-
-/***************************************************************************
- *CFP_MASK_Port_1 - CFP TCAM Mask X Registers
- ***************************************************************************/
-/* SWITCH_CORE :: CFP_MASK_Port_1 :: TCAM_MASK [31:00] */
-#define BCHP_SWITCH_CORE_CFP_MASK_Port_1_TCAM_MASK_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_CFP_MASK_Port_1_TCAM_MASK_SHIFT 0
-#define BCHP_SWITCH_CORE_CFP_MASK_Port_1_TCAM_MASK_DEFAULT 0x00000000
-
-/***************************************************************************
- *CFP_MASK_Port_2 - CFP TCAM Mask X Registers
- ***************************************************************************/
-/* SWITCH_CORE :: CFP_MASK_Port_2 :: TCAM_MASK [31:00] */
-#define BCHP_SWITCH_CORE_CFP_MASK_Port_2_TCAM_MASK_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_CFP_MASK_Port_2_TCAM_MASK_SHIFT 0
-#define BCHP_SWITCH_CORE_CFP_MASK_Port_2_TCAM_MASK_DEFAULT 0x00000000
-
-/***************************************************************************
- *CFP_MASK_Port_3 - CFP TCAM Mask X Registers
- ***************************************************************************/
-/* SWITCH_CORE :: CFP_MASK_Port_3 :: TCAM_MASK [31:00] */
-#define BCHP_SWITCH_CORE_CFP_MASK_Port_3_TCAM_MASK_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_CFP_MASK_Port_3_TCAM_MASK_SHIFT 0
-#define BCHP_SWITCH_CORE_CFP_MASK_Port_3_TCAM_MASK_DEFAULT 0x00000000
-
-/***************************************************************************
- *CFP_MASK_Port_4 - CFP TCAM Mask X Registers
- ***************************************************************************/
-/* SWITCH_CORE :: CFP_MASK_Port_4 :: TCAM_MASK [31:00] */
-#define BCHP_SWITCH_CORE_CFP_MASK_Port_4_TCAM_MASK_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_CFP_MASK_Port_4_TCAM_MASK_SHIFT 0
-#define BCHP_SWITCH_CORE_CFP_MASK_Port_4_TCAM_MASK_DEFAULT 0x00000000
-
-/***************************************************************************
- *CFP_MASK_Port_5 - CFP TCAM Mask X Registers
- ***************************************************************************/
-/* SWITCH_CORE :: CFP_MASK_Port_5 :: TCAM_MASK [31:00] */
-#define BCHP_SWITCH_CORE_CFP_MASK_Port_5_TCAM_MASK_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_CFP_MASK_Port_5_TCAM_MASK_SHIFT 0
-#define BCHP_SWITCH_CORE_CFP_MASK_Port_5_TCAM_MASK_DEFAULT 0x00000000
-
-/***************************************************************************
- *CFP_MASK_Port_6 - CFP TCAM Mask X Registers
- ***************************************************************************/
-/* SWITCH_CORE :: CFP_MASK_Port_6 :: TCAM_MASK [31:00] */
-#define BCHP_SWITCH_CORE_CFP_MASK_Port_6_TCAM_MASK_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_CFP_MASK_Port_6_TCAM_MASK_SHIFT 0
-#define BCHP_SWITCH_CORE_CFP_MASK_Port_6_TCAM_MASK_DEFAULT 0x00000000
-
-/***************************************************************************
- *CFP_MASK_Port_7 - CFP TCAM Mask X Registers
- ***************************************************************************/
-/* SWITCH_CORE :: CFP_MASK_Port_7 :: TCAM_MASK [31:00] */
-#define BCHP_SWITCH_CORE_CFP_MASK_Port_7_TCAM_MASK_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_CFP_MASK_Port_7_TCAM_MASK_SHIFT 0
-#define BCHP_SWITCH_CORE_CFP_MASK_Port_7_TCAM_MASK_DEFAULT 0x00000000
-
-/***************************************************************************
- *ACT_POL_DATA0 - CFP Action/Policy Data 0 Registers
- ***************************************************************************/
-/* SWITCH_CORE :: ACT_POL_DATA0 :: NEW_DSCP_IB [31:26] */
-#define BCHP_SWITCH_CORE_ACT_POL_DATA0_NEW_DSCP_IB_MASK 0xfc000000
-#define BCHP_SWITCH_CORE_ACT_POL_DATA0_NEW_DSCP_IB_SHIFT 26
-#define BCHP_SWITCH_CORE_ACT_POL_DATA0_NEW_DSCP_IB_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: ACT_POL_DATA0 :: CHANGE_FWRD_MAP_IB [25:24] */
-#define BCHP_SWITCH_CORE_ACT_POL_DATA0_CHANGE_FWRD_MAP_IB_MASK 0x03000000
-#define BCHP_SWITCH_CORE_ACT_POL_DATA0_CHANGE_FWRD_MAP_IB_SHIFT 24
-#define BCHP_SWITCH_CORE_ACT_POL_DATA0_CHANGE_FWRD_MAP_IB_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: ACT_POL_DATA0 :: DST_MAP_IB [23:14] */
-#define BCHP_SWITCH_CORE_ACT_POL_DATA0_DST_MAP_IB_MASK 0x00ffc000
-#define BCHP_SWITCH_CORE_ACT_POL_DATA0_DST_MAP_IB_SHIFT 14
-#define BCHP_SWITCH_CORE_ACT_POL_DATA0_DST_MAP_IB_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: ACT_POL_DATA0 :: CHANGE_TC [13:13] */
-#define BCHP_SWITCH_CORE_ACT_POL_DATA0_CHANGE_TC_MASK 0x00002000
-#define BCHP_SWITCH_CORE_ACT_POL_DATA0_CHANGE_TC_SHIFT 13
-#define BCHP_SWITCH_CORE_ACT_POL_DATA0_CHANGE_TC_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: ACT_POL_DATA0 :: NEW_TC [12:10] */
-#define BCHP_SWITCH_CORE_ACT_POL_DATA0_NEW_TC_MASK 0x00001c00
-#define BCHP_SWITCH_CORE_ACT_POL_DATA0_NEW_TC_SHIFT 10
-#define BCHP_SWITCH_CORE_ACT_POL_DATA0_NEW_TC_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: ACT_POL_DATA0 :: LOOP_BK_EN [09:09] */
-#define BCHP_SWITCH_CORE_ACT_POL_DATA0_LOOP_BK_EN_MASK 0x00000200
-#define BCHP_SWITCH_CORE_ACT_POL_DATA0_LOOP_BK_EN_SHIFT 9
-#define BCHP_SWITCH_CORE_ACT_POL_DATA0_LOOP_BK_EN_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: ACT_POL_DATA0 :: REASON_CODE [08:03] */
-#define BCHP_SWITCH_CORE_ACT_POL_DATA0_REASON_CODE_MASK 0x000001f8
-#define BCHP_SWITCH_CORE_ACT_POL_DATA0_REASON_CODE_SHIFT 3
-#define BCHP_SWITCH_CORE_ACT_POL_DATA0_REASON_CODE_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: ACT_POL_DATA0 :: STP_BYP [02:02] */
-#define BCHP_SWITCH_CORE_ACT_POL_DATA0_STP_BYP_MASK 0x00000004
-#define BCHP_SWITCH_CORE_ACT_POL_DATA0_STP_BYP_SHIFT 2
-#define BCHP_SWITCH_CORE_ACT_POL_DATA0_STP_BYP_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: ACT_POL_DATA0 :: EAP_BYP [01:01] */
-#define BCHP_SWITCH_CORE_ACT_POL_DATA0_EAP_BYP_MASK 0x00000002
-#define BCHP_SWITCH_CORE_ACT_POL_DATA0_EAP_BYP_SHIFT 1
-#define BCHP_SWITCH_CORE_ACT_POL_DATA0_EAP_BYP_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: ACT_POL_DATA0 :: VLAN_BYP [00:00] */
-#define BCHP_SWITCH_CORE_ACT_POL_DATA0_VLAN_BYP_MASK 0x00000001
-#define BCHP_SWITCH_CORE_ACT_POL_DATA0_VLAN_BYP_SHIFT 0
-#define BCHP_SWITCH_CORE_ACT_POL_DATA0_VLAN_BYP_DEFAULT 0x00000000
-
-/***************************************************************************
- *ACT_POL_DATA1 - CFP Action/Policy Data 1 Registers
- ***************************************************************************/
-/* SWITCH_CORE :: ACT_POL_DATA1 :: RED_DEFAULT [31:31] */
-#define BCHP_SWITCH_CORE_ACT_POL_DATA1_RED_DEFAULT_MASK 0x80000000
-#define BCHP_SWITCH_CORE_ACT_POL_DATA1_RED_DEFAULT_SHIFT 31
-#define BCHP_SWITCH_CORE_ACT_POL_DATA1_RED_DEFAULT_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: ACT_POL_DATA1 :: NEW_COLOR [30:29] */
-#define BCHP_SWITCH_CORE_ACT_POL_DATA1_NEW_COLOR_MASK 0x60000000
-#define BCHP_SWITCH_CORE_ACT_POL_DATA1_NEW_COLOR_SHIFT 29
-#define BCHP_SWITCH_CORE_ACT_POL_DATA1_NEW_COLOR_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: ACT_POL_DATA1 :: CHANGE_COLOR [28:28] */
-#define BCHP_SWITCH_CORE_ACT_POL_DATA1_CHANGE_COLOR_MASK 0x10000000
-#define BCHP_SWITCH_CORE_ACT_POL_DATA1_CHANGE_COLOR_SHIFT 28
-#define BCHP_SWITCH_CORE_ACT_POL_DATA1_CHANGE_COLOR_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: ACT_POL_DATA1 :: CHAIN_ID [27:20] */
-#define BCHP_SWITCH_CORE_ACT_POL_DATA1_CHAIN_ID_MASK 0x0ff00000
-#define BCHP_SWITCH_CORE_ACT_POL_DATA1_CHAIN_ID_SHIFT 20
-#define BCHP_SWITCH_CORE_ACT_POL_DATA1_CHAIN_ID_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: ACT_POL_DATA1 :: CHANGE_DSCP_OB [19:19] */
-#define BCHP_SWITCH_CORE_ACT_POL_DATA1_CHANGE_DSCP_OB_MASK 0x00080000
-#define BCHP_SWITCH_CORE_ACT_POL_DATA1_CHANGE_DSCP_OB_SHIFT 19
-#define BCHP_SWITCH_CORE_ACT_POL_DATA1_CHANGE_DSCP_OB_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: ACT_POL_DATA1 :: NEW_DSCP_OB [18:13] */
-#define BCHP_SWITCH_CORE_ACT_POL_DATA1_NEW_DSCP_OB_MASK 0x0007e000
-#define BCHP_SWITCH_CORE_ACT_POL_DATA1_NEW_DSCP_OB_SHIFT 13
-#define BCHP_SWITCH_CORE_ACT_POL_DATA1_NEW_DSCP_OB_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: ACT_POL_DATA1 :: CHANGE_FWRD_MAP_OB [12:11] */
-#define BCHP_SWITCH_CORE_ACT_POL_DATA1_CHANGE_FWRD_MAP_OB_MASK 0x00001800
-#define BCHP_SWITCH_CORE_ACT_POL_DATA1_CHANGE_FWRD_MAP_OB_SHIFT 11
-#define BCHP_SWITCH_CORE_ACT_POL_DATA1_CHANGE_FWRD_MAP_OB_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: ACT_POL_DATA1 :: DST_MAP_OB [10:01] */
-#define BCHP_SWITCH_CORE_ACT_POL_DATA1_DST_MAP_OB_MASK 0x000007fe
-#define BCHP_SWITCH_CORE_ACT_POL_DATA1_DST_MAP_OB_SHIFT 1
-#define BCHP_SWITCH_CORE_ACT_POL_DATA1_DST_MAP_OB_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: ACT_POL_DATA1 :: CHANGE_DSCP_IB [00:00] */
-#define BCHP_SWITCH_CORE_ACT_POL_DATA1_CHANGE_DSCP_IB_MASK 0x00000001
-#define BCHP_SWITCH_CORE_ACT_POL_DATA1_CHANGE_DSCP_IB_SHIFT 0
-#define BCHP_SWITCH_CORE_ACT_POL_DATA1_CHANGE_DSCP_IB_DEFAULT 0x00000000
-
-/***************************************************************************
- *ACT_POL_DATA2 - CFP Action/Policy Data 2 Registers
- ***************************************************************************/
-/* SWITCH_CORE :: ACT_POL_DATA2 :: SWITCH_RESV [31:08] */
-#define BCHP_SWITCH_CORE_ACT_POL_DATA2_SWITCH_RESV_MASK 0xffffff00
-#define BCHP_SWITCH_CORE_ACT_POL_DATA2_SWITCH_RESV_SHIFT 8
-#define BCHP_SWITCH_CORE_ACT_POL_DATA2_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: ACT_POL_DATA2 :: DEI_RMK_DISABLE [07:07] */
-#define BCHP_SWITCH_CORE_ACT_POL_DATA2_DEI_RMK_DISABLE_MASK 0x00000080
-#define BCHP_SWITCH_CORE_ACT_POL_DATA2_DEI_RMK_DISABLE_SHIFT 7
-#define BCHP_SWITCH_CORE_ACT_POL_DATA2_DEI_RMK_DISABLE_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: ACT_POL_DATA2 :: CPCP_RMK_DISABLE [06:06] */
-#define BCHP_SWITCH_CORE_ACT_POL_DATA2_CPCP_RMK_DISABLE_MASK 0x00000040
-#define BCHP_SWITCH_CORE_ACT_POL_DATA2_CPCP_RMK_DISABLE_SHIFT 6
-#define BCHP_SWITCH_CORE_ACT_POL_DATA2_CPCP_RMK_DISABLE_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: ACT_POL_DATA2 :: SPCP_RMK_DISABLE [05:05] */
-#define BCHP_SWITCH_CORE_ACT_POL_DATA2_SPCP_RMK_DISABLE_MASK 0x00000020
-#define BCHP_SWITCH_CORE_ACT_POL_DATA2_SPCP_RMK_DISABLE_SHIFT 5
-#define BCHP_SWITCH_CORE_ACT_POL_DATA2_SPCP_RMK_DISABLE_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: ACT_POL_DATA2 :: NEW_TC_O [04:02] */
-#define BCHP_SWITCH_CORE_ACT_POL_DATA2_NEW_TC_O_MASK 0x0000001c
-#define BCHP_SWITCH_CORE_ACT_POL_DATA2_NEW_TC_O_SHIFT 2
-#define BCHP_SWITCH_CORE_ACT_POL_DATA2_NEW_TC_O_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: ACT_POL_DATA2 :: CHANGE_TC_O [01:01] */
-#define BCHP_SWITCH_CORE_ACT_POL_DATA2_CHANGE_TC_O_MASK 0x00000002
-#define BCHP_SWITCH_CORE_ACT_POL_DATA2_CHANGE_TC_O_SHIFT 1
-#define BCHP_SWITCH_CORE_ACT_POL_DATA2_CHANGE_TC_O_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: ACT_POL_DATA2 :: MAC_LIMIT_BYPASS [00:00] */
-#define BCHP_SWITCH_CORE_ACT_POL_DATA2_MAC_LIMIT_BYPASS_MASK 0x00000001
-#define BCHP_SWITCH_CORE_ACT_POL_DATA2_MAC_LIMIT_BYPASS_SHIFT 0
-#define BCHP_SWITCH_CORE_ACT_POL_DATA2_MAC_LIMIT_BYPASS_DEFAULT 0x00000000
-
-/***************************************************************************
- *RATE_METER0 - CFP RATE METER DATA 0 Registers
- ***************************************************************************/
-/* SWITCH_CORE :: RATE_METER0 :: SWITCH_RESV [31:05] */
-#define BCHP_SWITCH_CORE_RATE_METER0_SWITCH_RESV_MASK 0xffffffe0
-#define BCHP_SWITCH_CORE_RATE_METER0_SWITCH_RESV_SHIFT 5
-#define BCHP_SWITCH_CORE_RATE_METER0_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: RATE_METER0 :: POLICER_MODE [04:03] */
-#define BCHP_SWITCH_CORE_RATE_METER0_POLICER_MODE_MASK 0x00000018
-#define BCHP_SWITCH_CORE_RATE_METER0_POLICER_MODE_SHIFT 3
-#define BCHP_SWITCH_CORE_RATE_METER0_POLICER_MODE_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: RATE_METER0 :: CF [02:02] */
-#define BCHP_SWITCH_CORE_RATE_METER0_CF_MASK 0x00000004
-#define BCHP_SWITCH_CORE_RATE_METER0_CF_SHIFT 2
-#define BCHP_SWITCH_CORE_RATE_METER0_CF_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: RATE_METER0 :: POLICER_ACTION [01:01] */
-#define BCHP_SWITCH_CORE_RATE_METER0_POLICER_ACTION_MASK 0x00000002
-#define BCHP_SWITCH_CORE_RATE_METER0_POLICER_ACTION_SHIFT 1
-#define BCHP_SWITCH_CORE_RATE_METER0_POLICER_ACTION_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: RATE_METER0 :: CM [00:00] */
-#define BCHP_SWITCH_CORE_RATE_METER0_CM_MASK 0x00000001
-#define BCHP_SWITCH_CORE_RATE_METER0_CM_SHIFT 0
-#define BCHP_SWITCH_CORE_RATE_METER0_CM_DEFAULT 0x00000000
-
-/***************************************************************************
- *RATE_METER1 - CFP RATE METER DATA 1 Registers
- ***************************************************************************/
-/* SWITCH_CORE :: RATE_METER1 :: SWITCH_RESV [31:23] */
-#define BCHP_SWITCH_CORE_RATE_METER1_SWITCH_RESV_MASK 0xff800000
-#define BCHP_SWITCH_CORE_RATE_METER1_SWITCH_RESV_SHIFT 23
-#define BCHP_SWITCH_CORE_RATE_METER1_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: RATE_METER1 :: EIR_TK_BKT [22:00] */
-#define BCHP_SWITCH_CORE_RATE_METER1_EIR_TK_BKT_MASK 0x007fffff
-#define BCHP_SWITCH_CORE_RATE_METER1_EIR_TK_BKT_SHIFT 0
-#define BCHP_SWITCH_CORE_RATE_METER1_EIR_TK_BKT_DEFAULT 0x00000000
-
-/***************************************************************************
- *RATE_METER2 - CFP RATE METER DATA 2 Registers
- ***************************************************************************/
-/* SWITCH_CORE :: RATE_METER2 :: SWITCH_RESV [31:20] */
-#define BCHP_SWITCH_CORE_RATE_METER2_SWITCH_RESV_MASK 0xfff00000
-#define BCHP_SWITCH_CORE_RATE_METER2_SWITCH_RESV_SHIFT 20
-#define BCHP_SWITCH_CORE_RATE_METER2_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: RATE_METER2 :: EIR_BKT_SIZE [19:00] */
-#define BCHP_SWITCH_CORE_RATE_METER2_EIR_BKT_SIZE_MASK 0x000fffff
-#define BCHP_SWITCH_CORE_RATE_METER2_EIR_BKT_SIZE_SHIFT 0
-#define BCHP_SWITCH_CORE_RATE_METER2_EIR_BKT_SIZE_DEFAULT 0x00000000
-
-/***************************************************************************
- *RATE_METER3 - CFP RATE METER DATA 3 Registers
- ***************************************************************************/
-/* SWITCH_CORE :: RATE_METER3 :: SWITCH_RESV [31:19] */
-#define BCHP_SWITCH_CORE_RATE_METER3_SWITCH_RESV_MASK 0xfff80000
-#define BCHP_SWITCH_CORE_RATE_METER3_SWITCH_RESV_SHIFT 19
-#define BCHP_SWITCH_CORE_RATE_METER3_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: RATE_METER3 :: EIR_REF_CNT [18:00] */
-#define BCHP_SWITCH_CORE_RATE_METER3_EIR_REF_CNT_MASK 0x0007ffff
-#define BCHP_SWITCH_CORE_RATE_METER3_EIR_REF_CNT_SHIFT 0
-#define BCHP_SWITCH_CORE_RATE_METER3_EIR_REF_CNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *RATE_METER4 - CFP RATE METER DATA 4 Registers
- ***************************************************************************/
-/* SWITCH_CORE :: RATE_METER4 :: SWITCH_RESV [31:23] */
-#define BCHP_SWITCH_CORE_RATE_METER4_SWITCH_RESV_MASK 0xff800000
-#define BCHP_SWITCH_CORE_RATE_METER4_SWITCH_RESV_SHIFT 23
-#define BCHP_SWITCH_CORE_RATE_METER4_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: RATE_METER4 :: CIR_TK_BKT [22:00] */
-#define BCHP_SWITCH_CORE_RATE_METER4_CIR_TK_BKT_MASK 0x007fffff
-#define BCHP_SWITCH_CORE_RATE_METER4_CIR_TK_BKT_SHIFT 0
-#define BCHP_SWITCH_CORE_RATE_METER4_CIR_TK_BKT_DEFAULT 0x00000000
-
-/***************************************************************************
- *RATE_METER5 - CFP RATE METER DATA 5 Registers
- ***************************************************************************/
-/* SWITCH_CORE :: RATE_METER5 :: SWITCH_RESV [31:20] */
-#define BCHP_SWITCH_CORE_RATE_METER5_SWITCH_RESV_MASK 0xfff00000
-#define BCHP_SWITCH_CORE_RATE_METER5_SWITCH_RESV_SHIFT 20
-#define BCHP_SWITCH_CORE_RATE_METER5_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: RATE_METER5 :: CIR_BKT_SIZE [19:00] */
-#define BCHP_SWITCH_CORE_RATE_METER5_CIR_BKT_SIZE_MASK 0x000fffff
-#define BCHP_SWITCH_CORE_RATE_METER5_CIR_BKT_SIZE_SHIFT 0
-#define BCHP_SWITCH_CORE_RATE_METER5_CIR_BKT_SIZE_DEFAULT 0x00000000
-
-/***************************************************************************
- *RATE_METER6 - CFP RATE METER DATA 6 Registers
- ***************************************************************************/
-/* SWITCH_CORE :: RATE_METER6 :: SWITCH_RESV [31:19] */
-#define BCHP_SWITCH_CORE_RATE_METER6_SWITCH_RESV_MASK 0xfff80000
-#define BCHP_SWITCH_CORE_RATE_METER6_SWITCH_RESV_SHIFT 19
-#define BCHP_SWITCH_CORE_RATE_METER6_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: RATE_METER6 :: CIR_REF_CNT [18:00] */
-#define BCHP_SWITCH_CORE_RATE_METER6_CIR_REF_CNT_MASK 0x0007ffff
-#define BCHP_SWITCH_CORE_RATE_METER6_CIR_REF_CNT_SHIFT 0
-#define BCHP_SWITCH_CORE_RATE_METER6_CIR_REF_CNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *TC2COLOR - TC to COLOR Mapping Registers
- ***************************************************************************/
-/* SWITCH_CORE :: TC2COLOR :: reserved_for_padding0 [31:16] */
-#define BCHP_SWITCH_CORE_TC2COLOR_reserved_for_padding0_MASK 0xffff0000
-#define BCHP_SWITCH_CORE_TC2COLOR_reserved_for_padding0_SHIFT 16
-
-/* SWITCH_CORE :: TC2COLOR :: SWITCH_RESV [15:11] */
-#define BCHP_SWITCH_CORE_TC2COLOR_SWITCH_RESV_MASK 0x0000f800
-#define BCHP_SWITCH_CORE_TC2COLOR_SWITCH_RESV_SHIFT 11
-#define BCHP_SWITCH_CORE_TC2COLOR_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: TC2COLOR :: TC2COLOR_MAP_COLOR [10:09] */
-#define BCHP_SWITCH_CORE_TC2COLOR_TC2COLOR_MAP_COLOR_MASK 0x00000600
-#define BCHP_SWITCH_CORE_TC2COLOR_TC2COLOR_MAP_COLOR_SHIFT 9
-#define BCHP_SWITCH_CORE_TC2COLOR_TC2COLOR_MAP_COLOR_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: TC2COLOR :: TC2COLOR_MAP_DEI [08:08] */
-#define BCHP_SWITCH_CORE_TC2COLOR_TC2COLOR_MAP_DEI_MASK 0x00000100
-#define BCHP_SWITCH_CORE_TC2COLOR_TC2COLOR_MAP_DEI_SHIFT 8
-#define BCHP_SWITCH_CORE_TC2COLOR_TC2COLOR_MAP_DEI_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: TC2COLOR :: TC2COLOR_MAP_TC [07:05] */
-#define BCHP_SWITCH_CORE_TC2COLOR_TC2COLOR_MAP_TC_MASK 0x000000e0
-#define BCHP_SWITCH_CORE_TC2COLOR_TC2COLOR_MAP_TC_SHIFT 5
-#define BCHP_SWITCH_CORE_TC2COLOR_TC2COLOR_MAP_TC_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: TC2COLOR :: TC2COLOR_MAP_ING_PORT [04:01] */
-#define BCHP_SWITCH_CORE_TC2COLOR_TC2COLOR_MAP_ING_PORT_MASK 0x0000001e
-#define BCHP_SWITCH_CORE_TC2COLOR_TC2COLOR_MAP_ING_PORT_SHIFT 1
-#define BCHP_SWITCH_CORE_TC2COLOR_TC2COLOR_MAP_ING_PORT_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: TC2COLOR :: TC2COLOR_MAP_RW [00:00] */
-#define BCHP_SWITCH_CORE_TC2COLOR_TC2COLOR_MAP_RW_MASK 0x00000001
-#define BCHP_SWITCH_CORE_TC2COLOR_TC2COLOR_MAP_RW_SHIFT 0
-#define BCHP_SWITCH_CORE_TC2COLOR_TC2COLOR_MAP_RW_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_GREEN_CNTR - Policer Green color statistic counter
- ***************************************************************************/
-/* SWITCH_CORE :: STAT_GREEN_CNTR :: GREEN_CNTR [31:00] */
-#define BCHP_SWITCH_CORE_STAT_GREEN_CNTR_GREEN_CNTR_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_STAT_GREEN_CNTR_GREEN_CNTR_SHIFT 0
-#define BCHP_SWITCH_CORE_STAT_GREEN_CNTR_GREEN_CNTR_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_YELLOW_CNTR - Policer Yellow color statistic counter
- ***************************************************************************/
-/* SWITCH_CORE :: STAT_YELLOW_CNTR :: YELLOW_CNTR [31:00] */
-#define BCHP_SWITCH_CORE_STAT_YELLOW_CNTR_YELLOW_CNTR_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_STAT_YELLOW_CNTR_YELLOW_CNTR_SHIFT 0
-#define BCHP_SWITCH_CORE_STAT_YELLOW_CNTR_YELLOW_CNTR_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_RED_CNTR - Policer RED color statistic counter
- ***************************************************************************/
-/* SWITCH_CORE :: STAT_RED_CNTR :: RED_CNTR [31:00] */
-#define BCHP_SWITCH_CORE_STAT_RED_CNTR_RED_CNTR_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_STAT_RED_CNTR_RED_CNTR_SHIFT 0
-#define BCHP_SWITCH_CORE_STAT_RED_CNTR_RED_CNTR_DEFAULT 0x00000000
-
-/***************************************************************************
- *TCAM_BIST_CONTROL - TCAM BIST Control Registers (Not2Release)
- ***************************************************************************/
-/* SWITCH_CORE :: TCAM_BIST_CONTROL :: TCAM_BIST_DONE [31:31] */
-#define BCHP_SWITCH_CORE_TCAM_BIST_CONTROL_TCAM_BIST_DONE_MASK 0x80000000
-#define BCHP_SWITCH_CORE_TCAM_BIST_CONTROL_TCAM_BIST_DONE_SHIFT 31
-#define BCHP_SWITCH_CORE_TCAM_BIST_CONTROL_TCAM_BIST_DONE_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: TCAM_BIST_CONTROL :: SWITCH_RESV_1 [30:17] */
-#define BCHP_SWITCH_CORE_TCAM_BIST_CONTROL_SWITCH_RESV_1_MASK 0x7ffe0000
-#define BCHP_SWITCH_CORE_TCAM_BIST_CONTROL_SWITCH_RESV_1_SHIFT 17
-#define BCHP_SWITCH_CORE_TCAM_BIST_CONTROL_SWITCH_RESV_1_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: TCAM_BIST_CONTROL :: TCAM_TEST_COMPARE [16:16] */
-#define BCHP_SWITCH_CORE_TCAM_BIST_CONTROL_TCAM_TEST_COMPARE_MASK 0x00010000
-#define BCHP_SWITCH_CORE_TCAM_BIST_CONTROL_TCAM_TEST_COMPARE_SHIFT 16
-#define BCHP_SWITCH_CORE_TCAM_BIST_CONTROL_TCAM_TEST_COMPARE_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: TCAM_BIST_CONTROL :: TCAM_BIST_SKIP_ERR_CNT [15:08] */
-#define BCHP_SWITCH_CORE_TCAM_BIST_CONTROL_TCAM_BIST_SKIP_ERR_CNT_MASK 0x0000ff00
-#define BCHP_SWITCH_CORE_TCAM_BIST_CONTROL_TCAM_BIST_SKIP_ERR_CNT_SHIFT 8
-#define BCHP_SWITCH_CORE_TCAM_BIST_CONTROL_TCAM_BIST_SKIP_ERR_CNT_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: TCAM_BIST_CONTROL :: TCAM_BIST_STATUS_SEL [07:04] */
-#define BCHP_SWITCH_CORE_TCAM_BIST_CONTROL_TCAM_BIST_STATUS_SEL_MASK 0x000000f0
-#define BCHP_SWITCH_CORE_TCAM_BIST_CONTROL_TCAM_BIST_STATUS_SEL_SHIFT 4
-#define BCHP_SWITCH_CORE_TCAM_BIST_CONTROL_TCAM_BIST_STATUS_SEL_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: TCAM_BIST_CONTROL :: SWITCH_RESV_0 [03:02] */
-#define BCHP_SWITCH_CORE_TCAM_BIST_CONTROL_SWITCH_RESV_0_MASK 0x0000000c
-#define BCHP_SWITCH_CORE_TCAM_BIST_CONTROL_SWITCH_RESV_0_SHIFT 2
-#define BCHP_SWITCH_CORE_TCAM_BIST_CONTROL_SWITCH_RESV_0_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: TCAM_BIST_CONTROL :: TCAM_SEL [01:01] */
-#define BCHP_SWITCH_CORE_TCAM_BIST_CONTROL_TCAM_SEL_MASK 0x00000002
-#define BCHP_SWITCH_CORE_TCAM_BIST_CONTROL_TCAM_SEL_SHIFT 1
-#define BCHP_SWITCH_CORE_TCAM_BIST_CONTROL_TCAM_SEL_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: TCAM_BIST_CONTROL :: TCAM_BIST_EN [00:00] */
-#define BCHP_SWITCH_CORE_TCAM_BIST_CONTROL_TCAM_BIST_EN_MASK 0x00000001
-#define BCHP_SWITCH_CORE_TCAM_BIST_CONTROL_TCAM_BIST_EN_SHIFT 0
-#define BCHP_SWITCH_CORE_TCAM_BIST_CONTROL_TCAM_BIST_EN_DEFAULT 0x00000000
-
-/***************************************************************************
- *TCAM_BIST_STATUS - TCAM BIST Status Registers (Not2Release)
- ***************************************************************************/
-/* SWITCH_CORE :: TCAM_BIST_STATUS :: SWITCH_RESV [31:16] */
-#define BCHP_SWITCH_CORE_TCAM_BIST_STATUS_SWITCH_RESV_MASK 0xffff0000
-#define BCHP_SWITCH_CORE_TCAM_BIST_STATUS_SWITCH_RESV_SHIFT 16
-#define BCHP_SWITCH_CORE_TCAM_BIST_STATUS_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: TCAM_BIST_STATUS :: TCAM_BIST_STATUS [15:00] */
-#define BCHP_SWITCH_CORE_TCAM_BIST_STATUS_TCAM_BIST_STATUS_MASK 0x0000ffff
-#define BCHP_SWITCH_CORE_TCAM_BIST_STATUS_TCAM_BIST_STATUS_SHIFT 0
-#define BCHP_SWITCH_CORE_TCAM_BIST_STATUS_TCAM_BIST_STATUS_DEFAULT 0x00000000
-
-/***************************************************************************
- *TCAM_TEST_COMPARE_STATUS - TCAM Test Compare Status Registers (Not2Release)
- ***************************************************************************/
-/* SWITCH_CORE :: TCAM_TEST_COMPARE_STATUS :: SWITCH_RESV_1 [31:16] */
-#define BCHP_SWITCH_CORE_TCAM_TEST_COMPARE_STATUS_SWITCH_RESV_1_MASK 0xffff0000
-#define BCHP_SWITCH_CORE_TCAM_TEST_COMPARE_STATUS_SWITCH_RESV_1_SHIFT 16
-#define BCHP_SWITCH_CORE_TCAM_TEST_COMPARE_STATUS_SWITCH_RESV_1_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: TCAM_TEST_COMPARE_STATUS :: TCAM_HIT [15:15] */
-#define BCHP_SWITCH_CORE_TCAM_TEST_COMPARE_STATUS_TCAM_HIT_MASK 0x00008000
-#define BCHP_SWITCH_CORE_TCAM_TEST_COMPARE_STATUS_TCAM_HIT_SHIFT 15
-#define BCHP_SWITCH_CORE_TCAM_TEST_COMPARE_STATUS_TCAM_HIT_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: TCAM_TEST_COMPARE_STATUS :: SWITCH_RESV_0 [14:07] */
-#define BCHP_SWITCH_CORE_TCAM_TEST_COMPARE_STATUS_SWITCH_RESV_0_MASK 0x00007f80
-#define BCHP_SWITCH_CORE_TCAM_TEST_COMPARE_STATUS_SWITCH_RESV_0_SHIFT 7
-#define BCHP_SWITCH_CORE_TCAM_TEST_COMPARE_STATUS_SWITCH_RESV_0_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: TCAM_TEST_COMPARE_STATUS :: TCAM_HIT_ADDR [06:00] */
-#define BCHP_SWITCH_CORE_TCAM_TEST_COMPARE_STATUS_TCAM_HIT_ADDR_MASK 0x0000007f
-#define BCHP_SWITCH_CORE_TCAM_TEST_COMPARE_STATUS_TCAM_HIT_ADDR_SHIFT 0
-#define BCHP_SWITCH_CORE_TCAM_TEST_COMPARE_STATUS_TCAM_HIT_ADDR_DEFAULT 0x00000000
-
-/***************************************************************************
- *CFP_REG_SPARE0 - Spare 0 Register (Not2Release)
- ***************************************************************************/
-/* SWITCH_CORE :: CFP_REG_SPARE0 :: CFP_REG_SPARE0 [31:00] */
-#define BCHP_SWITCH_CORE_CFP_REG_SPARE0_CFP_REG_SPARE0_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_CFP_REG_SPARE0_CFP_REG_SPARE0_SHIFT 0
-#define BCHP_SWITCH_CORE_CFP_REG_SPARE0_CFP_REG_SPARE0_DEFAULT 0x00000000
-
-/***************************************************************************
- *CFP_REG_SPARE1 - Spare 1 Register (Not2Release)
- ***************************************************************************/
-/* SWITCH_CORE :: CFP_REG_SPARE1 :: CFP_REG_SPARE1 [31:00] */
-#define BCHP_SWITCH_CORE_CFP_REG_SPARE1_CFP_REG_SPARE1_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_CFP_REG_SPARE1_CFP_REG_SPARE1_SHIFT 0
-#define BCHP_SWITCH_CORE_CFP_REG_SPARE1_CFP_REG_SPARE1_DEFAULT 0x00000000
-
-/***************************************************************************
- *CFP_CTL_REG - CFP Control Registers
- ***************************************************************************/
-/* SWITCH_CORE :: CFP_CTL_REG :: reserved_for_padding0 [31:16] */
-#define BCHP_SWITCH_CORE_CFP_CTL_REG_reserved_for_padding0_MASK 0xffff0000
-#define BCHP_SWITCH_CORE_CFP_CTL_REG_reserved_for_padding0_SHIFT 16
-
-/* SWITCH_CORE :: CFP_CTL_REG :: SWITCH_RESV [15:09] */
-#define BCHP_SWITCH_CORE_CFP_CTL_REG_SWITCH_RESV_MASK 0x0000fe00
-#define BCHP_SWITCH_CORE_CFP_CTL_REG_SWITCH_RESV_SHIFT 9
-#define BCHP_SWITCH_CORE_CFP_CTL_REG_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: CFP_CTL_REG :: CFP_EN_MAP [08:00] */
-#define BCHP_SWITCH_CORE_CFP_CTL_REG_CFP_EN_MAP_MASK 0x000001ff
-#define BCHP_SWITCH_CORE_CFP_CTL_REG_CFP_EN_MAP_SHIFT 0
-#define BCHP_SWITCH_CORE_CFP_CTL_REG_CFP_EN_MAP_DEFAULT 0x00000000
-
-/***************************************************************************
- *UDF_0_A_0_8_Port_0 - UDFs of slice 0 for IPv4 packet Registers
- ***************************************************************************/
-/* SWITCH_CORE :: UDF_0_A_0_8_Port_0 :: reserved_for_padding0 [31:08] */
-#define BCHP_SWITCH_CORE_UDF_0_A_0_8_Port_0_reserved_for_padding0_MASK 0xffffff00
-#define BCHP_SWITCH_CORE_UDF_0_A_0_8_Port_0_reserved_for_padding0_SHIFT 8
-
-/* SWITCH_CORE :: UDF_0_A_0_8_Port_0 :: CFG_UDF_0_A_0_8 [07:00] */
-#define BCHP_SWITCH_CORE_UDF_0_A_0_8_Port_0_CFG_UDF_0_A_0_8_MASK 0x000000ff
-#define BCHP_SWITCH_CORE_UDF_0_A_0_8_Port_0_CFG_UDF_0_A_0_8_SHIFT 0
-#define BCHP_SWITCH_CORE_UDF_0_A_0_8_Port_0_CFG_UDF_0_A_0_8_DEFAULT 0x00000000
-
-/***************************************************************************
- *UDF_0_A_0_8_Port_1 - UDFs of slice 0 for IPv4 packet Registers
- ***************************************************************************/
-/* SWITCH_CORE :: UDF_0_A_0_8_Port_1 :: reserved_for_padding0 [31:08] */
-#define BCHP_SWITCH_CORE_UDF_0_A_0_8_Port_1_reserved_for_padding0_MASK 0xffffff00
-#define BCHP_SWITCH_CORE_UDF_0_A_0_8_Port_1_reserved_for_padding0_SHIFT 8
-
-/* SWITCH_CORE :: UDF_0_A_0_8_Port_1 :: CFG_UDF_0_A_0_8 [07:00] */
-#define BCHP_SWITCH_CORE_UDF_0_A_0_8_Port_1_CFG_UDF_0_A_0_8_MASK 0x000000ff
-#define BCHP_SWITCH_CORE_UDF_0_A_0_8_Port_1_CFG_UDF_0_A_0_8_SHIFT 0
-#define BCHP_SWITCH_CORE_UDF_0_A_0_8_Port_1_CFG_UDF_0_A_0_8_DEFAULT 0x00000000
-
-/***************************************************************************
- *UDF_0_A_0_8_Port_2 - UDFs of slice 0 for IPv4 packet Registers
- ***************************************************************************/
-/* SWITCH_CORE :: UDF_0_A_0_8_Port_2 :: reserved_for_padding0 [31:08] */
-#define BCHP_SWITCH_CORE_UDF_0_A_0_8_Port_2_reserved_for_padding0_MASK 0xffffff00
-#define BCHP_SWITCH_CORE_UDF_0_A_0_8_Port_2_reserved_for_padding0_SHIFT 8
-
-/* SWITCH_CORE :: UDF_0_A_0_8_Port_2 :: CFG_UDF_0_A_0_8 [07:00] */
-#define BCHP_SWITCH_CORE_UDF_0_A_0_8_Port_2_CFG_UDF_0_A_0_8_MASK 0x000000ff
-#define BCHP_SWITCH_CORE_UDF_0_A_0_8_Port_2_CFG_UDF_0_A_0_8_SHIFT 0
-#define BCHP_SWITCH_CORE_UDF_0_A_0_8_Port_2_CFG_UDF_0_A_0_8_DEFAULT 0x00000000
-
-/***************************************************************************
- *UDF_0_A_0_8_Port_3 - UDFs of slice 0 for IPv4 packet Registers
- ***************************************************************************/
-/* SWITCH_CORE :: UDF_0_A_0_8_Port_3 :: reserved_for_padding0 [31:08] */
-#define BCHP_SWITCH_CORE_UDF_0_A_0_8_Port_3_reserved_for_padding0_MASK 0xffffff00
-#define BCHP_SWITCH_CORE_UDF_0_A_0_8_Port_3_reserved_for_padding0_SHIFT 8
-
-/* SWITCH_CORE :: UDF_0_A_0_8_Port_3 :: CFG_UDF_0_A_0_8 [07:00] */
-#define BCHP_SWITCH_CORE_UDF_0_A_0_8_Port_3_CFG_UDF_0_A_0_8_MASK 0x000000ff
-#define BCHP_SWITCH_CORE_UDF_0_A_0_8_Port_3_CFG_UDF_0_A_0_8_SHIFT 0
-#define BCHP_SWITCH_CORE_UDF_0_A_0_8_Port_3_CFG_UDF_0_A_0_8_DEFAULT 0x00000000
-
-/***************************************************************************
- *UDF_0_A_0_8_Port_4 - UDFs of slice 0 for IPv4 packet Registers
- ***************************************************************************/
-/* SWITCH_CORE :: UDF_0_A_0_8_Port_4 :: reserved_for_padding0 [31:08] */
-#define BCHP_SWITCH_CORE_UDF_0_A_0_8_Port_4_reserved_for_padding0_MASK 0xffffff00
-#define BCHP_SWITCH_CORE_UDF_0_A_0_8_Port_4_reserved_for_padding0_SHIFT 8
-
-/* SWITCH_CORE :: UDF_0_A_0_8_Port_4 :: CFG_UDF_0_A_0_8 [07:00] */
-#define BCHP_SWITCH_CORE_UDF_0_A_0_8_Port_4_CFG_UDF_0_A_0_8_MASK 0x000000ff
-#define BCHP_SWITCH_CORE_UDF_0_A_0_8_Port_4_CFG_UDF_0_A_0_8_SHIFT 0
-#define BCHP_SWITCH_CORE_UDF_0_A_0_8_Port_4_CFG_UDF_0_A_0_8_DEFAULT 0x00000000
-
-/***************************************************************************
- *UDF_0_A_0_8_Port_5 - UDFs of slice 0 for IPv4 packet Registers
- ***************************************************************************/
-/* SWITCH_CORE :: UDF_0_A_0_8_Port_5 :: reserved_for_padding0 [31:08] */
-#define BCHP_SWITCH_CORE_UDF_0_A_0_8_Port_5_reserved_for_padding0_MASK 0xffffff00
-#define BCHP_SWITCH_CORE_UDF_0_A_0_8_Port_5_reserved_for_padding0_SHIFT 8
-
-/* SWITCH_CORE :: UDF_0_A_0_8_Port_5 :: CFG_UDF_0_A_0_8 [07:00] */
-#define BCHP_SWITCH_CORE_UDF_0_A_0_8_Port_5_CFG_UDF_0_A_0_8_MASK 0x000000ff
-#define BCHP_SWITCH_CORE_UDF_0_A_0_8_Port_5_CFG_UDF_0_A_0_8_SHIFT 0
-#define BCHP_SWITCH_CORE_UDF_0_A_0_8_Port_5_CFG_UDF_0_A_0_8_DEFAULT 0x00000000
-
-/***************************************************************************
- *UDF_0_A_0_8_Port_6 - UDFs of slice 0 for IPv4 packet Registers
- ***************************************************************************/
-/* SWITCH_CORE :: UDF_0_A_0_8_Port_6 :: reserved_for_padding0 [31:08] */
-#define BCHP_SWITCH_CORE_UDF_0_A_0_8_Port_6_reserved_for_padding0_MASK 0xffffff00
-#define BCHP_SWITCH_CORE_UDF_0_A_0_8_Port_6_reserved_for_padding0_SHIFT 8
-
-/* SWITCH_CORE :: UDF_0_A_0_8_Port_6 :: CFG_UDF_0_A_0_8 [07:00] */
-#define BCHP_SWITCH_CORE_UDF_0_A_0_8_Port_6_CFG_UDF_0_A_0_8_MASK 0x000000ff
-#define BCHP_SWITCH_CORE_UDF_0_A_0_8_Port_6_CFG_UDF_0_A_0_8_SHIFT 0
-#define BCHP_SWITCH_CORE_UDF_0_A_0_8_Port_6_CFG_UDF_0_A_0_8_DEFAULT 0x00000000
-
-/***************************************************************************
- *UDF_0_A_0_8_Port_7 - UDFs of slice 0 for IPv4 packet Registers
- ***************************************************************************/
-/* SWITCH_CORE :: UDF_0_A_0_8_Port_7 :: reserved_for_padding0 [31:08] */
-#define BCHP_SWITCH_CORE_UDF_0_A_0_8_Port_7_reserved_for_padding0_MASK 0xffffff00
-#define BCHP_SWITCH_CORE_UDF_0_A_0_8_Port_7_reserved_for_padding0_SHIFT 8
-
-/* SWITCH_CORE :: UDF_0_A_0_8_Port_7 :: CFG_UDF_0_A_0_8 [07:00] */
-#define BCHP_SWITCH_CORE_UDF_0_A_0_8_Port_7_CFG_UDF_0_A_0_8_MASK 0x000000ff
-#define BCHP_SWITCH_CORE_UDF_0_A_0_8_Port_7_CFG_UDF_0_A_0_8_SHIFT 0
-#define BCHP_SWITCH_CORE_UDF_0_A_0_8_Port_7_CFG_UDF_0_A_0_8_DEFAULT 0x00000000
-
-/***************************************************************************
- *UDF_0_A_0_8_Port_8 - UDFs of slice 0 for IPv4 packet Registers
- ***************************************************************************/
-/* SWITCH_CORE :: UDF_0_A_0_8_Port_8 :: reserved_for_padding0 [31:08] */
-#define BCHP_SWITCH_CORE_UDF_0_A_0_8_Port_8_reserved_for_padding0_MASK 0xffffff00
-#define BCHP_SWITCH_CORE_UDF_0_A_0_8_Port_8_reserved_for_padding0_SHIFT 8
-
-/* SWITCH_CORE :: UDF_0_A_0_8_Port_8 :: CFG_UDF_0_A_0_8 [07:00] */
-#define BCHP_SWITCH_CORE_UDF_0_A_0_8_Port_8_CFG_UDF_0_A_0_8_MASK 0x000000ff
-#define BCHP_SWITCH_CORE_UDF_0_A_0_8_Port_8_CFG_UDF_0_A_0_8_SHIFT 0
-#define BCHP_SWITCH_CORE_UDF_0_A_0_8_Port_8_CFG_UDF_0_A_0_8_DEFAULT 0x00000000
-
-/***************************************************************************
- *UDF_1_A_0_8_Port_0 - UDFs of slice 1 for IPv4 packet Registers
- ***************************************************************************/
-/* SWITCH_CORE :: UDF_1_A_0_8_Port_0 :: reserved_for_padding0 [31:08] */
-#define BCHP_SWITCH_CORE_UDF_1_A_0_8_Port_0_reserved_for_padding0_MASK 0xffffff00
-#define BCHP_SWITCH_CORE_UDF_1_A_0_8_Port_0_reserved_for_padding0_SHIFT 8
-
-/* SWITCH_CORE :: UDF_1_A_0_8_Port_0 :: CFG_UDF_1_A_0_8 [07:00] */
-#define BCHP_SWITCH_CORE_UDF_1_A_0_8_Port_0_CFG_UDF_1_A_0_8_MASK 0x000000ff
-#define BCHP_SWITCH_CORE_UDF_1_A_0_8_Port_0_CFG_UDF_1_A_0_8_SHIFT 0
-#define BCHP_SWITCH_CORE_UDF_1_A_0_8_Port_0_CFG_UDF_1_A_0_8_DEFAULT 0x00000000
-
-/***************************************************************************
- *UDF_1_A_0_8_Port_1 - UDFs of slice 1 for IPv4 packet Registers
- ***************************************************************************/
-/* SWITCH_CORE :: UDF_1_A_0_8_Port_1 :: reserved_for_padding0 [31:08] */
-#define BCHP_SWITCH_CORE_UDF_1_A_0_8_Port_1_reserved_for_padding0_MASK 0xffffff00
-#define BCHP_SWITCH_CORE_UDF_1_A_0_8_Port_1_reserved_for_padding0_SHIFT 8
-
-/* SWITCH_CORE :: UDF_1_A_0_8_Port_1 :: CFG_UDF_1_A_0_8 [07:00] */
-#define BCHP_SWITCH_CORE_UDF_1_A_0_8_Port_1_CFG_UDF_1_A_0_8_MASK 0x000000ff
-#define BCHP_SWITCH_CORE_UDF_1_A_0_8_Port_1_CFG_UDF_1_A_0_8_SHIFT 0
-#define BCHP_SWITCH_CORE_UDF_1_A_0_8_Port_1_CFG_UDF_1_A_0_8_DEFAULT 0x00000000
-
-/***************************************************************************
- *UDF_1_A_0_8_Port_2 - UDFs of slice 1 for IPv4 packet Registers
- ***************************************************************************/
-/* SWITCH_CORE :: UDF_1_A_0_8_Port_2 :: reserved_for_padding0 [31:08] */
-#define BCHP_SWITCH_CORE_UDF_1_A_0_8_Port_2_reserved_for_padding0_MASK 0xffffff00
-#define BCHP_SWITCH_CORE_UDF_1_A_0_8_Port_2_reserved_for_padding0_SHIFT 8
-
-/* SWITCH_CORE :: UDF_1_A_0_8_Port_2 :: CFG_UDF_1_A_0_8 [07:00] */
-#define BCHP_SWITCH_CORE_UDF_1_A_0_8_Port_2_CFG_UDF_1_A_0_8_MASK 0x000000ff
-#define BCHP_SWITCH_CORE_UDF_1_A_0_8_Port_2_CFG_UDF_1_A_0_8_SHIFT 0
-#define BCHP_SWITCH_CORE_UDF_1_A_0_8_Port_2_CFG_UDF_1_A_0_8_DEFAULT 0x00000000
-
-/***************************************************************************
- *UDF_1_A_0_8_Port_3 - UDFs of slice 1 for IPv4 packet Registers
- ***************************************************************************/
-/* SWITCH_CORE :: UDF_1_A_0_8_Port_3 :: reserved_for_padding0 [31:08] */
-#define BCHP_SWITCH_CORE_UDF_1_A_0_8_Port_3_reserved_for_padding0_MASK 0xffffff00
-#define BCHP_SWITCH_CORE_UDF_1_A_0_8_Port_3_reserved_for_padding0_SHIFT 8
-
-/* SWITCH_CORE :: UDF_1_A_0_8_Port_3 :: CFG_UDF_1_A_0_8 [07:00] */
-#define BCHP_SWITCH_CORE_UDF_1_A_0_8_Port_3_CFG_UDF_1_A_0_8_MASK 0x000000ff
-#define BCHP_SWITCH_CORE_UDF_1_A_0_8_Port_3_CFG_UDF_1_A_0_8_SHIFT 0
-#define BCHP_SWITCH_CORE_UDF_1_A_0_8_Port_3_CFG_UDF_1_A_0_8_DEFAULT 0x00000000
-
-/***************************************************************************
- *UDF_1_A_0_8_Port_4 - UDFs of slice 1 for IPv4 packet Registers
- ***************************************************************************/
-/* SWITCH_CORE :: UDF_1_A_0_8_Port_4 :: reserved_for_padding0 [31:08] */
-#define BCHP_SWITCH_CORE_UDF_1_A_0_8_Port_4_reserved_for_padding0_MASK 0xffffff00
-#define BCHP_SWITCH_CORE_UDF_1_A_0_8_Port_4_reserved_for_padding0_SHIFT 8
-
-/* SWITCH_CORE :: UDF_1_A_0_8_Port_4 :: CFG_UDF_1_A_0_8 [07:00] */
-#define BCHP_SWITCH_CORE_UDF_1_A_0_8_Port_4_CFG_UDF_1_A_0_8_MASK 0x000000ff
-#define BCHP_SWITCH_CORE_UDF_1_A_0_8_Port_4_CFG_UDF_1_A_0_8_SHIFT 0
-#define BCHP_SWITCH_CORE_UDF_1_A_0_8_Port_4_CFG_UDF_1_A_0_8_DEFAULT 0x00000000
-
-/***************************************************************************
- *UDF_1_A_0_8_Port_5 - UDFs of slice 1 for IPv4 packet Registers
- ***************************************************************************/
-/* SWITCH_CORE :: UDF_1_A_0_8_Port_5 :: reserved_for_padding0 [31:08] */
-#define BCHP_SWITCH_CORE_UDF_1_A_0_8_Port_5_reserved_for_padding0_MASK 0xffffff00
-#define BCHP_SWITCH_CORE_UDF_1_A_0_8_Port_5_reserved_for_padding0_SHIFT 8
-
-/* SWITCH_CORE :: UDF_1_A_0_8_Port_5 :: CFG_UDF_1_A_0_8 [07:00] */
-#define BCHP_SWITCH_CORE_UDF_1_A_0_8_Port_5_CFG_UDF_1_A_0_8_MASK 0x000000ff
-#define BCHP_SWITCH_CORE_UDF_1_A_0_8_Port_5_CFG_UDF_1_A_0_8_SHIFT 0
-#define BCHP_SWITCH_CORE_UDF_1_A_0_8_Port_5_CFG_UDF_1_A_0_8_DEFAULT 0x00000000
-
-/***************************************************************************
- *UDF_1_A_0_8_Port_6 - UDFs of slice 1 for IPv4 packet Registers
- ***************************************************************************/
-/* SWITCH_CORE :: UDF_1_A_0_8_Port_6 :: reserved_for_padding0 [31:08] */
-#define BCHP_SWITCH_CORE_UDF_1_A_0_8_Port_6_reserved_for_padding0_MASK 0xffffff00
-#define BCHP_SWITCH_CORE_UDF_1_A_0_8_Port_6_reserved_for_padding0_SHIFT 8
-
-/* SWITCH_CORE :: UDF_1_A_0_8_Port_6 :: CFG_UDF_1_A_0_8 [07:00] */
-#define BCHP_SWITCH_CORE_UDF_1_A_0_8_Port_6_CFG_UDF_1_A_0_8_MASK 0x000000ff
-#define BCHP_SWITCH_CORE_UDF_1_A_0_8_Port_6_CFG_UDF_1_A_0_8_SHIFT 0
-#define BCHP_SWITCH_CORE_UDF_1_A_0_8_Port_6_CFG_UDF_1_A_0_8_DEFAULT 0x00000000
-
-/***************************************************************************
- *UDF_1_A_0_8_Port_7 - UDFs of slice 1 for IPv4 packet Registers
- ***************************************************************************/
-/* SWITCH_CORE :: UDF_1_A_0_8_Port_7 :: reserved_for_padding0 [31:08] */
-#define BCHP_SWITCH_CORE_UDF_1_A_0_8_Port_7_reserved_for_padding0_MASK 0xffffff00
-#define BCHP_SWITCH_CORE_UDF_1_A_0_8_Port_7_reserved_for_padding0_SHIFT 8
-
-/* SWITCH_CORE :: UDF_1_A_0_8_Port_7 :: CFG_UDF_1_A_0_8 [07:00] */
-#define BCHP_SWITCH_CORE_UDF_1_A_0_8_Port_7_CFG_UDF_1_A_0_8_MASK 0x000000ff
-#define BCHP_SWITCH_CORE_UDF_1_A_0_8_Port_7_CFG_UDF_1_A_0_8_SHIFT 0
-#define BCHP_SWITCH_CORE_UDF_1_A_0_8_Port_7_CFG_UDF_1_A_0_8_DEFAULT 0x00000000
-
-/***************************************************************************
- *UDF_1_A_0_8_Port_8 - UDFs of slice 1 for IPv4 packet Registers
- ***************************************************************************/
-/* SWITCH_CORE :: UDF_1_A_0_8_Port_8 :: reserved_for_padding0 [31:08] */
-#define BCHP_SWITCH_CORE_UDF_1_A_0_8_Port_8_reserved_for_padding0_MASK 0xffffff00
-#define BCHP_SWITCH_CORE_UDF_1_A_0_8_Port_8_reserved_for_padding0_SHIFT 8
-
-/* SWITCH_CORE :: UDF_1_A_0_8_Port_8 :: CFG_UDF_1_A_0_8 [07:00] */
-#define BCHP_SWITCH_CORE_UDF_1_A_0_8_Port_8_CFG_UDF_1_A_0_8_MASK 0x000000ff
-#define BCHP_SWITCH_CORE_UDF_1_A_0_8_Port_8_CFG_UDF_1_A_0_8_SHIFT 0
-#define BCHP_SWITCH_CORE_UDF_1_A_0_8_Port_8_CFG_UDF_1_A_0_8_DEFAULT 0x00000000
-
-/***************************************************************************
- *UDF_2_A_0_8_Port_0 - UDFs of slice 2 for IPv4 packet Registers
- ***************************************************************************/
-/* SWITCH_CORE :: UDF_2_A_0_8_Port_0 :: reserved_for_padding0 [31:08] */
-#define BCHP_SWITCH_CORE_UDF_2_A_0_8_Port_0_reserved_for_padding0_MASK 0xffffff00
-#define BCHP_SWITCH_CORE_UDF_2_A_0_8_Port_0_reserved_for_padding0_SHIFT 8
-
-/* SWITCH_CORE :: UDF_2_A_0_8_Port_0 :: CFG_UDF_2_A_0_8 [07:00] */
-#define BCHP_SWITCH_CORE_UDF_2_A_0_8_Port_0_CFG_UDF_2_A_0_8_MASK 0x000000ff
-#define BCHP_SWITCH_CORE_UDF_2_A_0_8_Port_0_CFG_UDF_2_A_0_8_SHIFT 0
-#define BCHP_SWITCH_CORE_UDF_2_A_0_8_Port_0_CFG_UDF_2_A_0_8_DEFAULT 0x00000000
-
-/***************************************************************************
- *UDF_2_A_0_8_Port_1 - UDFs of slice 2 for IPv4 packet Registers
- ***************************************************************************/
-/* SWITCH_CORE :: UDF_2_A_0_8_Port_1 :: reserved_for_padding0 [31:08] */
-#define BCHP_SWITCH_CORE_UDF_2_A_0_8_Port_1_reserved_for_padding0_MASK 0xffffff00
-#define BCHP_SWITCH_CORE_UDF_2_A_0_8_Port_1_reserved_for_padding0_SHIFT 8
-
-/* SWITCH_CORE :: UDF_2_A_0_8_Port_1 :: CFG_UDF_2_A_0_8 [07:00] */
-#define BCHP_SWITCH_CORE_UDF_2_A_0_8_Port_1_CFG_UDF_2_A_0_8_MASK 0x000000ff
-#define BCHP_SWITCH_CORE_UDF_2_A_0_8_Port_1_CFG_UDF_2_A_0_8_SHIFT 0
-#define BCHP_SWITCH_CORE_UDF_2_A_0_8_Port_1_CFG_UDF_2_A_0_8_DEFAULT 0x00000000
-
-/***************************************************************************
- *UDF_2_A_0_8_Port_2 - UDFs of slice 2 for IPv4 packet Registers
- ***************************************************************************/
-/* SWITCH_CORE :: UDF_2_A_0_8_Port_2 :: reserved_for_padding0 [31:08] */
-#define BCHP_SWITCH_CORE_UDF_2_A_0_8_Port_2_reserved_for_padding0_MASK 0xffffff00
-#define BCHP_SWITCH_CORE_UDF_2_A_0_8_Port_2_reserved_for_padding0_SHIFT 8
-
-/* SWITCH_CORE :: UDF_2_A_0_8_Port_2 :: CFG_UDF_2_A_0_8 [07:00] */
-#define BCHP_SWITCH_CORE_UDF_2_A_0_8_Port_2_CFG_UDF_2_A_0_8_MASK 0x000000ff
-#define BCHP_SWITCH_CORE_UDF_2_A_0_8_Port_2_CFG_UDF_2_A_0_8_SHIFT 0
-#define BCHP_SWITCH_CORE_UDF_2_A_0_8_Port_2_CFG_UDF_2_A_0_8_DEFAULT 0x00000000
-
-/***************************************************************************
- *UDF_2_A_0_8_Port_3 - UDFs of slice 2 for IPv4 packet Registers
- ***************************************************************************/
-/* SWITCH_CORE :: UDF_2_A_0_8_Port_3 :: reserved_for_padding0 [31:08] */
-#define BCHP_SWITCH_CORE_UDF_2_A_0_8_Port_3_reserved_for_padding0_MASK 0xffffff00
-#define BCHP_SWITCH_CORE_UDF_2_A_0_8_Port_3_reserved_for_padding0_SHIFT 8
-
-/* SWITCH_CORE :: UDF_2_A_0_8_Port_3 :: CFG_UDF_2_A_0_8 [07:00] */
-#define BCHP_SWITCH_CORE_UDF_2_A_0_8_Port_3_CFG_UDF_2_A_0_8_MASK 0x000000ff
-#define BCHP_SWITCH_CORE_UDF_2_A_0_8_Port_3_CFG_UDF_2_A_0_8_SHIFT 0
-#define BCHP_SWITCH_CORE_UDF_2_A_0_8_Port_3_CFG_UDF_2_A_0_8_DEFAULT 0x00000000
-
-/***************************************************************************
- *UDF_2_A_0_8_Port_4 - UDFs of slice 2 for IPv4 packet Registers
- ***************************************************************************/
-/* SWITCH_CORE :: UDF_2_A_0_8_Port_4 :: reserved_for_padding0 [31:08] */
-#define BCHP_SWITCH_CORE_UDF_2_A_0_8_Port_4_reserved_for_padding0_MASK 0xffffff00
-#define BCHP_SWITCH_CORE_UDF_2_A_0_8_Port_4_reserved_for_padding0_SHIFT 8
-
-/* SWITCH_CORE :: UDF_2_A_0_8_Port_4 :: CFG_UDF_2_A_0_8 [07:00] */
-#define BCHP_SWITCH_CORE_UDF_2_A_0_8_Port_4_CFG_UDF_2_A_0_8_MASK 0x000000ff
-#define BCHP_SWITCH_CORE_UDF_2_A_0_8_Port_4_CFG_UDF_2_A_0_8_SHIFT 0
-#define BCHP_SWITCH_CORE_UDF_2_A_0_8_Port_4_CFG_UDF_2_A_0_8_DEFAULT 0x00000000
-
-/***************************************************************************
- *UDF_2_A_0_8_Port_5 - UDFs of slice 2 for IPv4 packet Registers
- ***************************************************************************/
-/* SWITCH_CORE :: UDF_2_A_0_8_Port_5 :: reserved_for_padding0 [31:08] */
-#define BCHP_SWITCH_CORE_UDF_2_A_0_8_Port_5_reserved_for_padding0_MASK 0xffffff00
-#define BCHP_SWITCH_CORE_UDF_2_A_0_8_Port_5_reserved_for_padding0_SHIFT 8
-
-/* SWITCH_CORE :: UDF_2_A_0_8_Port_5 :: CFG_UDF_2_A_0_8 [07:00] */
-#define BCHP_SWITCH_CORE_UDF_2_A_0_8_Port_5_CFG_UDF_2_A_0_8_MASK 0x000000ff
-#define BCHP_SWITCH_CORE_UDF_2_A_0_8_Port_5_CFG_UDF_2_A_0_8_SHIFT 0
-#define BCHP_SWITCH_CORE_UDF_2_A_0_8_Port_5_CFG_UDF_2_A_0_8_DEFAULT 0x00000000
-
-/***************************************************************************
- *UDF_2_A_0_8_Port_6 - UDFs of slice 2 for IPv4 packet Registers
- ***************************************************************************/
-/* SWITCH_CORE :: UDF_2_A_0_8_Port_6 :: reserved_for_padding0 [31:08] */
-#define BCHP_SWITCH_CORE_UDF_2_A_0_8_Port_6_reserved_for_padding0_MASK 0xffffff00
-#define BCHP_SWITCH_CORE_UDF_2_A_0_8_Port_6_reserved_for_padding0_SHIFT 8
-
-/* SWITCH_CORE :: UDF_2_A_0_8_Port_6 :: CFG_UDF_2_A_0_8 [07:00] */
-#define BCHP_SWITCH_CORE_UDF_2_A_0_8_Port_6_CFG_UDF_2_A_0_8_MASK 0x000000ff
-#define BCHP_SWITCH_CORE_UDF_2_A_0_8_Port_6_CFG_UDF_2_A_0_8_SHIFT 0
-#define BCHP_SWITCH_CORE_UDF_2_A_0_8_Port_6_CFG_UDF_2_A_0_8_DEFAULT 0x00000000
-
-/***************************************************************************
- *UDF_2_A_0_8_Port_7 - UDFs of slice 2 for IPv4 packet Registers
- ***************************************************************************/
-/* SWITCH_CORE :: UDF_2_A_0_8_Port_7 :: reserved_for_padding0 [31:08] */
-#define BCHP_SWITCH_CORE_UDF_2_A_0_8_Port_7_reserved_for_padding0_MASK 0xffffff00
-#define BCHP_SWITCH_CORE_UDF_2_A_0_8_Port_7_reserved_for_padding0_SHIFT 8
-
-/* SWITCH_CORE :: UDF_2_A_0_8_Port_7 :: CFG_UDF_2_A_0_8 [07:00] */
-#define BCHP_SWITCH_CORE_UDF_2_A_0_8_Port_7_CFG_UDF_2_A_0_8_MASK 0x000000ff
-#define BCHP_SWITCH_CORE_UDF_2_A_0_8_Port_7_CFG_UDF_2_A_0_8_SHIFT 0
-#define BCHP_SWITCH_CORE_UDF_2_A_0_8_Port_7_CFG_UDF_2_A_0_8_DEFAULT 0x00000000
-
-/***************************************************************************
- *UDF_2_A_0_8_Port_8 - UDFs of slice 2 for IPv4 packet Registers
- ***************************************************************************/
-/* SWITCH_CORE :: UDF_2_A_0_8_Port_8 :: reserved_for_padding0 [31:08] */
-#define BCHP_SWITCH_CORE_UDF_2_A_0_8_Port_8_reserved_for_padding0_MASK 0xffffff00
-#define BCHP_SWITCH_CORE_UDF_2_A_0_8_Port_8_reserved_for_padding0_SHIFT 8
-
-/* SWITCH_CORE :: UDF_2_A_0_8_Port_8 :: CFG_UDF_2_A_0_8 [07:00] */
-#define BCHP_SWITCH_CORE_UDF_2_A_0_8_Port_8_CFG_UDF_2_A_0_8_MASK 0x000000ff
-#define BCHP_SWITCH_CORE_UDF_2_A_0_8_Port_8_CFG_UDF_2_A_0_8_SHIFT 0
-#define BCHP_SWITCH_CORE_UDF_2_A_0_8_Port_8_CFG_UDF_2_A_0_8_DEFAULT 0x00000000
-
-/***************************************************************************
- *UDF_0_B_0_8_Port_0 - UDFs of slice 0 for IPv6 packet Registers
- ***************************************************************************/
-/* SWITCH_CORE :: UDF_0_B_0_8_Port_0 :: reserved_for_padding0 [31:08] */
-#define BCHP_SWITCH_CORE_UDF_0_B_0_8_Port_0_reserved_for_padding0_MASK 0xffffff00
-#define BCHP_SWITCH_CORE_UDF_0_B_0_8_Port_0_reserved_for_padding0_SHIFT 8
-
-/* SWITCH_CORE :: UDF_0_B_0_8_Port_0 :: CFG_UDF_0_B_0_8 [07:00] */
-#define BCHP_SWITCH_CORE_UDF_0_B_0_8_Port_0_CFG_UDF_0_B_0_8_MASK 0x000000ff
-#define BCHP_SWITCH_CORE_UDF_0_B_0_8_Port_0_CFG_UDF_0_B_0_8_SHIFT 0
-#define BCHP_SWITCH_CORE_UDF_0_B_0_8_Port_0_CFG_UDF_0_B_0_8_DEFAULT 0x00000000
-
-/***************************************************************************
- *UDF_0_B_0_8_Port_1 - UDFs of slice 0 for IPv6 packet Registers
- ***************************************************************************/
-/* SWITCH_CORE :: UDF_0_B_0_8_Port_1 :: reserved_for_padding0 [31:08] */
-#define BCHP_SWITCH_CORE_UDF_0_B_0_8_Port_1_reserved_for_padding0_MASK 0xffffff00
-#define BCHP_SWITCH_CORE_UDF_0_B_0_8_Port_1_reserved_for_padding0_SHIFT 8
-
-/* SWITCH_CORE :: UDF_0_B_0_8_Port_1 :: CFG_UDF_0_B_0_8 [07:00] */
-#define BCHP_SWITCH_CORE_UDF_0_B_0_8_Port_1_CFG_UDF_0_B_0_8_MASK 0x000000ff
-#define BCHP_SWITCH_CORE_UDF_0_B_0_8_Port_1_CFG_UDF_0_B_0_8_SHIFT 0
-#define BCHP_SWITCH_CORE_UDF_0_B_0_8_Port_1_CFG_UDF_0_B_0_8_DEFAULT 0x00000000
-
-/***************************************************************************
- *UDF_0_B_0_8_Port_2 - UDFs of slice 0 for IPv6 packet Registers
- ***************************************************************************/
-/* SWITCH_CORE :: UDF_0_B_0_8_Port_2 :: reserved_for_padding0 [31:08] */
-#define BCHP_SWITCH_CORE_UDF_0_B_0_8_Port_2_reserved_for_padding0_MASK 0xffffff00
-#define BCHP_SWITCH_CORE_UDF_0_B_0_8_Port_2_reserved_for_padding0_SHIFT 8
-
-/* SWITCH_CORE :: UDF_0_B_0_8_Port_2 :: CFG_UDF_0_B_0_8 [07:00] */
-#define BCHP_SWITCH_CORE_UDF_0_B_0_8_Port_2_CFG_UDF_0_B_0_8_MASK 0x000000ff
-#define BCHP_SWITCH_CORE_UDF_0_B_0_8_Port_2_CFG_UDF_0_B_0_8_SHIFT 0
-#define BCHP_SWITCH_CORE_UDF_0_B_0_8_Port_2_CFG_UDF_0_B_0_8_DEFAULT 0x00000000
-
-/***************************************************************************
- *UDF_0_B_0_8_Port_3 - UDFs of slice 0 for IPv6 packet Registers
- ***************************************************************************/
-/* SWITCH_CORE :: UDF_0_B_0_8_Port_3 :: reserved_for_padding0 [31:08] */
-#define BCHP_SWITCH_CORE_UDF_0_B_0_8_Port_3_reserved_for_padding0_MASK 0xffffff00
-#define BCHP_SWITCH_CORE_UDF_0_B_0_8_Port_3_reserved_for_padding0_SHIFT 8
-
-/* SWITCH_CORE :: UDF_0_B_0_8_Port_3 :: CFG_UDF_0_B_0_8 [07:00] */
-#define BCHP_SWITCH_CORE_UDF_0_B_0_8_Port_3_CFG_UDF_0_B_0_8_MASK 0x000000ff
-#define BCHP_SWITCH_CORE_UDF_0_B_0_8_Port_3_CFG_UDF_0_B_0_8_SHIFT 0
-#define BCHP_SWITCH_CORE_UDF_0_B_0_8_Port_3_CFG_UDF_0_B_0_8_DEFAULT 0x00000000
-
-/***************************************************************************
- *UDF_0_B_0_8_Port_4 - UDFs of slice 0 for IPv6 packet Registers
- ***************************************************************************/
-/* SWITCH_CORE :: UDF_0_B_0_8_Port_4 :: reserved_for_padding0 [31:08] */
-#define BCHP_SWITCH_CORE_UDF_0_B_0_8_Port_4_reserved_for_padding0_MASK 0xffffff00
-#define BCHP_SWITCH_CORE_UDF_0_B_0_8_Port_4_reserved_for_padding0_SHIFT 8
-
-/* SWITCH_CORE :: UDF_0_B_0_8_Port_4 :: CFG_UDF_0_B_0_8 [07:00] */
-#define BCHP_SWITCH_CORE_UDF_0_B_0_8_Port_4_CFG_UDF_0_B_0_8_MASK 0x000000ff
-#define BCHP_SWITCH_CORE_UDF_0_B_0_8_Port_4_CFG_UDF_0_B_0_8_SHIFT 0
-#define BCHP_SWITCH_CORE_UDF_0_B_0_8_Port_4_CFG_UDF_0_B_0_8_DEFAULT 0x00000000
-
-/***************************************************************************
- *UDF_0_B_0_8_Port_5 - UDFs of slice 0 for IPv6 packet Registers
- ***************************************************************************/
-/* SWITCH_CORE :: UDF_0_B_0_8_Port_5 :: reserved_for_padding0 [31:08] */
-#define BCHP_SWITCH_CORE_UDF_0_B_0_8_Port_5_reserved_for_padding0_MASK 0xffffff00
-#define BCHP_SWITCH_CORE_UDF_0_B_0_8_Port_5_reserved_for_padding0_SHIFT 8
-
-/* SWITCH_CORE :: UDF_0_B_0_8_Port_5 :: CFG_UDF_0_B_0_8 [07:00] */
-#define BCHP_SWITCH_CORE_UDF_0_B_0_8_Port_5_CFG_UDF_0_B_0_8_MASK 0x000000ff
-#define BCHP_SWITCH_CORE_UDF_0_B_0_8_Port_5_CFG_UDF_0_B_0_8_SHIFT 0
-#define BCHP_SWITCH_CORE_UDF_0_B_0_8_Port_5_CFG_UDF_0_B_0_8_DEFAULT 0x00000000
-
-/***************************************************************************
- *UDF_0_B_0_8_Port_6 - UDFs of slice 0 for IPv6 packet Registers
- ***************************************************************************/
-/* SWITCH_CORE :: UDF_0_B_0_8_Port_6 :: reserved_for_padding0 [31:08] */
-#define BCHP_SWITCH_CORE_UDF_0_B_0_8_Port_6_reserved_for_padding0_MASK 0xffffff00
-#define BCHP_SWITCH_CORE_UDF_0_B_0_8_Port_6_reserved_for_padding0_SHIFT 8
-
-/* SWITCH_CORE :: UDF_0_B_0_8_Port_6 :: CFG_UDF_0_B_0_8 [07:00] */
-#define BCHP_SWITCH_CORE_UDF_0_B_0_8_Port_6_CFG_UDF_0_B_0_8_MASK 0x000000ff
-#define BCHP_SWITCH_CORE_UDF_0_B_0_8_Port_6_CFG_UDF_0_B_0_8_SHIFT 0
-#define BCHP_SWITCH_CORE_UDF_0_B_0_8_Port_6_CFG_UDF_0_B_0_8_DEFAULT 0x00000000
-
-/***************************************************************************
- *UDF_0_B_0_8_Port_7 - UDFs of slice 0 for IPv6 packet Registers
- ***************************************************************************/
-/* SWITCH_CORE :: UDF_0_B_0_8_Port_7 :: reserved_for_padding0 [31:08] */
-#define BCHP_SWITCH_CORE_UDF_0_B_0_8_Port_7_reserved_for_padding0_MASK 0xffffff00
-#define BCHP_SWITCH_CORE_UDF_0_B_0_8_Port_7_reserved_for_padding0_SHIFT 8
-
-/* SWITCH_CORE :: UDF_0_B_0_8_Port_7 :: CFG_UDF_0_B_0_8 [07:00] */
-#define BCHP_SWITCH_CORE_UDF_0_B_0_8_Port_7_CFG_UDF_0_B_0_8_MASK 0x000000ff
-#define BCHP_SWITCH_CORE_UDF_0_B_0_8_Port_7_CFG_UDF_0_B_0_8_SHIFT 0
-#define BCHP_SWITCH_CORE_UDF_0_B_0_8_Port_7_CFG_UDF_0_B_0_8_DEFAULT 0x00000000
-
-/***************************************************************************
- *UDF_0_B_0_8_Port_8 - UDFs of slice 0 for IPv6 packet Registers
- ***************************************************************************/
-/* SWITCH_CORE :: UDF_0_B_0_8_Port_8 :: reserved_for_padding0 [31:08] */
-#define BCHP_SWITCH_CORE_UDF_0_B_0_8_Port_8_reserved_for_padding0_MASK 0xffffff00
-#define BCHP_SWITCH_CORE_UDF_0_B_0_8_Port_8_reserved_for_padding0_SHIFT 8
-
-/* SWITCH_CORE :: UDF_0_B_0_8_Port_8 :: CFG_UDF_0_B_0_8 [07:00] */
-#define BCHP_SWITCH_CORE_UDF_0_B_0_8_Port_8_CFG_UDF_0_B_0_8_MASK 0x000000ff
-#define BCHP_SWITCH_CORE_UDF_0_B_0_8_Port_8_CFG_UDF_0_B_0_8_SHIFT 0
-#define BCHP_SWITCH_CORE_UDF_0_B_0_8_Port_8_CFG_UDF_0_B_0_8_DEFAULT 0x00000000
-
-/***************************************************************************
- *UDF_1_B_0_8_Port_0 - UDFs of slice 1 for IPv6 Registers
- ***************************************************************************/
-/* SWITCH_CORE :: UDF_1_B_0_8_Port_0 :: reserved_for_padding0 [31:08] */
-#define BCHP_SWITCH_CORE_UDF_1_B_0_8_Port_0_reserved_for_padding0_MASK 0xffffff00
-#define BCHP_SWITCH_CORE_UDF_1_B_0_8_Port_0_reserved_for_padding0_SHIFT 8
-
-/* SWITCH_CORE :: UDF_1_B_0_8_Port_0 :: CFG_UDF_1_B_0_8 [07:00] */
-#define BCHP_SWITCH_CORE_UDF_1_B_0_8_Port_0_CFG_UDF_1_B_0_8_MASK 0x000000ff
-#define BCHP_SWITCH_CORE_UDF_1_B_0_8_Port_0_CFG_UDF_1_B_0_8_SHIFT 0
-#define BCHP_SWITCH_CORE_UDF_1_B_0_8_Port_0_CFG_UDF_1_B_0_8_DEFAULT 0x00000000
-
-/***************************************************************************
- *UDF_1_B_0_8_Port_1 - UDFs of slice 1 for IPv6 Registers
- ***************************************************************************/
-/* SWITCH_CORE :: UDF_1_B_0_8_Port_1 :: reserved_for_padding0 [31:08] */
-#define BCHP_SWITCH_CORE_UDF_1_B_0_8_Port_1_reserved_for_padding0_MASK 0xffffff00
-#define BCHP_SWITCH_CORE_UDF_1_B_0_8_Port_1_reserved_for_padding0_SHIFT 8
-
-/* SWITCH_CORE :: UDF_1_B_0_8_Port_1 :: CFG_UDF_1_B_0_8 [07:00] */
-#define BCHP_SWITCH_CORE_UDF_1_B_0_8_Port_1_CFG_UDF_1_B_0_8_MASK 0x000000ff
-#define BCHP_SWITCH_CORE_UDF_1_B_0_8_Port_1_CFG_UDF_1_B_0_8_SHIFT 0
-#define BCHP_SWITCH_CORE_UDF_1_B_0_8_Port_1_CFG_UDF_1_B_0_8_DEFAULT 0x00000000
-
-/***************************************************************************
- *UDF_1_B_0_8_Port_2 - UDFs of slice 1 for IPv6 Registers
- ***************************************************************************/
-/* SWITCH_CORE :: UDF_1_B_0_8_Port_2 :: reserved_for_padding0 [31:08] */
-#define BCHP_SWITCH_CORE_UDF_1_B_0_8_Port_2_reserved_for_padding0_MASK 0xffffff00
-#define BCHP_SWITCH_CORE_UDF_1_B_0_8_Port_2_reserved_for_padding0_SHIFT 8
-
-/* SWITCH_CORE :: UDF_1_B_0_8_Port_2 :: CFG_UDF_1_B_0_8 [07:00] */
-#define BCHP_SWITCH_CORE_UDF_1_B_0_8_Port_2_CFG_UDF_1_B_0_8_MASK 0x000000ff
-#define BCHP_SWITCH_CORE_UDF_1_B_0_8_Port_2_CFG_UDF_1_B_0_8_SHIFT 0
-#define BCHP_SWITCH_CORE_UDF_1_B_0_8_Port_2_CFG_UDF_1_B_0_8_DEFAULT 0x00000000
-
-/***************************************************************************
- *UDF_1_B_0_8_Port_3 - UDFs of slice 1 for IPv6 Registers
- ***************************************************************************/
-/* SWITCH_CORE :: UDF_1_B_0_8_Port_3 :: reserved_for_padding0 [31:08] */
-#define BCHP_SWITCH_CORE_UDF_1_B_0_8_Port_3_reserved_for_padding0_MASK 0xffffff00
-#define BCHP_SWITCH_CORE_UDF_1_B_0_8_Port_3_reserved_for_padding0_SHIFT 8
-
-/* SWITCH_CORE :: UDF_1_B_0_8_Port_3 :: CFG_UDF_1_B_0_8 [07:00] */
-#define BCHP_SWITCH_CORE_UDF_1_B_0_8_Port_3_CFG_UDF_1_B_0_8_MASK 0x000000ff
-#define BCHP_SWITCH_CORE_UDF_1_B_0_8_Port_3_CFG_UDF_1_B_0_8_SHIFT 0
-#define BCHP_SWITCH_CORE_UDF_1_B_0_8_Port_3_CFG_UDF_1_B_0_8_DEFAULT 0x00000000
-
-/***************************************************************************
- *UDF_1_B_0_8_Port_4 - UDFs of slice 1 for IPv6 Registers
- ***************************************************************************/
-/* SWITCH_CORE :: UDF_1_B_0_8_Port_4 :: reserved_for_padding0 [31:08] */
-#define BCHP_SWITCH_CORE_UDF_1_B_0_8_Port_4_reserved_for_padding0_MASK 0xffffff00
-#define BCHP_SWITCH_CORE_UDF_1_B_0_8_Port_4_reserved_for_padding0_SHIFT 8
-
-/* SWITCH_CORE :: UDF_1_B_0_8_Port_4 :: CFG_UDF_1_B_0_8 [07:00] */
-#define BCHP_SWITCH_CORE_UDF_1_B_0_8_Port_4_CFG_UDF_1_B_0_8_MASK 0x000000ff
-#define BCHP_SWITCH_CORE_UDF_1_B_0_8_Port_4_CFG_UDF_1_B_0_8_SHIFT 0
-#define BCHP_SWITCH_CORE_UDF_1_B_0_8_Port_4_CFG_UDF_1_B_0_8_DEFAULT 0x00000000
-
-/***************************************************************************
- *UDF_1_B_0_8_Port_5 - UDFs of slice 1 for IPv6 Registers
- ***************************************************************************/
-/* SWITCH_CORE :: UDF_1_B_0_8_Port_5 :: reserved_for_padding0 [31:08] */
-#define BCHP_SWITCH_CORE_UDF_1_B_0_8_Port_5_reserved_for_padding0_MASK 0xffffff00
-#define BCHP_SWITCH_CORE_UDF_1_B_0_8_Port_5_reserved_for_padding0_SHIFT 8
-
-/* SWITCH_CORE :: UDF_1_B_0_8_Port_5 :: CFG_UDF_1_B_0_8 [07:00] */
-#define BCHP_SWITCH_CORE_UDF_1_B_0_8_Port_5_CFG_UDF_1_B_0_8_MASK 0x000000ff
-#define BCHP_SWITCH_CORE_UDF_1_B_0_8_Port_5_CFG_UDF_1_B_0_8_SHIFT 0
-#define BCHP_SWITCH_CORE_UDF_1_B_0_8_Port_5_CFG_UDF_1_B_0_8_DEFAULT 0x00000000
-
-/***************************************************************************
- *UDF_1_B_0_8_Port_6 - UDFs of slice 1 for IPv6 Registers
- ***************************************************************************/
-/* SWITCH_CORE :: UDF_1_B_0_8_Port_6 :: reserved_for_padding0 [31:08] */
-#define BCHP_SWITCH_CORE_UDF_1_B_0_8_Port_6_reserved_for_padding0_MASK 0xffffff00
-#define BCHP_SWITCH_CORE_UDF_1_B_0_8_Port_6_reserved_for_padding0_SHIFT 8
-
-/* SWITCH_CORE :: UDF_1_B_0_8_Port_6 :: CFG_UDF_1_B_0_8 [07:00] */
-#define BCHP_SWITCH_CORE_UDF_1_B_0_8_Port_6_CFG_UDF_1_B_0_8_MASK 0x000000ff
-#define BCHP_SWITCH_CORE_UDF_1_B_0_8_Port_6_CFG_UDF_1_B_0_8_SHIFT 0
-#define BCHP_SWITCH_CORE_UDF_1_B_0_8_Port_6_CFG_UDF_1_B_0_8_DEFAULT 0x00000000
-
-/***************************************************************************
- *UDF_1_B_0_8_Port_7 - UDFs of slice 1 for IPv6 Registers
- ***************************************************************************/
-/* SWITCH_CORE :: UDF_1_B_0_8_Port_7 :: reserved_for_padding0 [31:08] */
-#define BCHP_SWITCH_CORE_UDF_1_B_0_8_Port_7_reserved_for_padding0_MASK 0xffffff00
-#define BCHP_SWITCH_CORE_UDF_1_B_0_8_Port_7_reserved_for_padding0_SHIFT 8
-
-/* SWITCH_CORE :: UDF_1_B_0_8_Port_7 :: CFG_UDF_1_B_0_8 [07:00] */
-#define BCHP_SWITCH_CORE_UDF_1_B_0_8_Port_7_CFG_UDF_1_B_0_8_MASK 0x000000ff
-#define BCHP_SWITCH_CORE_UDF_1_B_0_8_Port_7_CFG_UDF_1_B_0_8_SHIFT 0
-#define BCHP_SWITCH_CORE_UDF_1_B_0_8_Port_7_CFG_UDF_1_B_0_8_DEFAULT 0x00000000
-
-/***************************************************************************
- *UDF_1_B_0_8_Port_8 - UDFs of slice 1 for IPv6 Registers
- ***************************************************************************/
-/* SWITCH_CORE :: UDF_1_B_0_8_Port_8 :: reserved_for_padding0 [31:08] */
-#define BCHP_SWITCH_CORE_UDF_1_B_0_8_Port_8_reserved_for_padding0_MASK 0xffffff00
-#define BCHP_SWITCH_CORE_UDF_1_B_0_8_Port_8_reserved_for_padding0_SHIFT 8
-
-/* SWITCH_CORE :: UDF_1_B_0_8_Port_8 :: CFG_UDF_1_B_0_8 [07:00] */
-#define BCHP_SWITCH_CORE_UDF_1_B_0_8_Port_8_CFG_UDF_1_B_0_8_MASK 0x000000ff
-#define BCHP_SWITCH_CORE_UDF_1_B_0_8_Port_8_CFG_UDF_1_B_0_8_SHIFT 0
-#define BCHP_SWITCH_CORE_UDF_1_B_0_8_Port_8_CFG_UDF_1_B_0_8_DEFAULT 0x00000000
-
-/***************************************************************************
- *UDF_2_B_0_8_Port_0 - UDFs of slice 2 for IPv6 Registers
- ***************************************************************************/
-/* SWITCH_CORE :: UDF_2_B_0_8_Port_0 :: reserved_for_padding0 [31:08] */
-#define BCHP_SWITCH_CORE_UDF_2_B_0_8_Port_0_reserved_for_padding0_MASK 0xffffff00
-#define BCHP_SWITCH_CORE_UDF_2_B_0_8_Port_0_reserved_for_padding0_SHIFT 8
-
-/* SWITCH_CORE :: UDF_2_B_0_8_Port_0 :: CFG_UDF_2_B_0_8 [07:00] */
-#define BCHP_SWITCH_CORE_UDF_2_B_0_8_Port_0_CFG_UDF_2_B_0_8_MASK 0x000000ff
-#define BCHP_SWITCH_CORE_UDF_2_B_0_8_Port_0_CFG_UDF_2_B_0_8_SHIFT 0
-#define BCHP_SWITCH_CORE_UDF_2_B_0_8_Port_0_CFG_UDF_2_B_0_8_DEFAULT 0x00000000
-
-/***************************************************************************
- *UDF_2_B_0_8_Port_1 - UDFs of slice 2 for IPv6 Registers
- ***************************************************************************/
-/* SWITCH_CORE :: UDF_2_B_0_8_Port_1 :: reserved_for_padding0 [31:08] */
-#define BCHP_SWITCH_CORE_UDF_2_B_0_8_Port_1_reserved_for_padding0_MASK 0xffffff00
-#define BCHP_SWITCH_CORE_UDF_2_B_0_8_Port_1_reserved_for_padding0_SHIFT 8
-
-/* SWITCH_CORE :: UDF_2_B_0_8_Port_1 :: CFG_UDF_2_B_0_8 [07:00] */
-#define BCHP_SWITCH_CORE_UDF_2_B_0_8_Port_1_CFG_UDF_2_B_0_8_MASK 0x000000ff
-#define BCHP_SWITCH_CORE_UDF_2_B_0_8_Port_1_CFG_UDF_2_B_0_8_SHIFT 0
-#define BCHP_SWITCH_CORE_UDF_2_B_0_8_Port_1_CFG_UDF_2_B_0_8_DEFAULT 0x00000000
-
-/***************************************************************************
- *UDF_2_B_0_8_Port_2 - UDFs of slice 2 for IPv6 Registers
- ***************************************************************************/
-/* SWITCH_CORE :: UDF_2_B_0_8_Port_2 :: reserved_for_padding0 [31:08] */
-#define BCHP_SWITCH_CORE_UDF_2_B_0_8_Port_2_reserved_for_padding0_MASK 0xffffff00
-#define BCHP_SWITCH_CORE_UDF_2_B_0_8_Port_2_reserved_for_padding0_SHIFT 8
-
-/* SWITCH_CORE :: UDF_2_B_0_8_Port_2 :: CFG_UDF_2_B_0_8 [07:00] */
-#define BCHP_SWITCH_CORE_UDF_2_B_0_8_Port_2_CFG_UDF_2_B_0_8_MASK 0x000000ff
-#define BCHP_SWITCH_CORE_UDF_2_B_0_8_Port_2_CFG_UDF_2_B_0_8_SHIFT 0
-#define BCHP_SWITCH_CORE_UDF_2_B_0_8_Port_2_CFG_UDF_2_B_0_8_DEFAULT 0x00000000
-
-/***************************************************************************
- *UDF_2_B_0_8_Port_3 - UDFs of slice 2 for IPv6 Registers
- ***************************************************************************/
-/* SWITCH_CORE :: UDF_2_B_0_8_Port_3 :: reserved_for_padding0 [31:08] */
-#define BCHP_SWITCH_CORE_UDF_2_B_0_8_Port_3_reserved_for_padding0_MASK 0xffffff00
-#define BCHP_SWITCH_CORE_UDF_2_B_0_8_Port_3_reserved_for_padding0_SHIFT 8
-
-/* SWITCH_CORE :: UDF_2_B_0_8_Port_3 :: CFG_UDF_2_B_0_8 [07:00] */
-#define BCHP_SWITCH_CORE_UDF_2_B_0_8_Port_3_CFG_UDF_2_B_0_8_MASK 0x000000ff
-#define BCHP_SWITCH_CORE_UDF_2_B_0_8_Port_3_CFG_UDF_2_B_0_8_SHIFT 0
-#define BCHP_SWITCH_CORE_UDF_2_B_0_8_Port_3_CFG_UDF_2_B_0_8_DEFAULT 0x00000000
-
-/***************************************************************************
- *UDF_2_B_0_8_Port_4 - UDFs of slice 2 for IPv6 Registers
- ***************************************************************************/
-/* SWITCH_CORE :: UDF_2_B_0_8_Port_4 :: reserved_for_padding0 [31:08] */
-#define BCHP_SWITCH_CORE_UDF_2_B_0_8_Port_4_reserved_for_padding0_MASK 0xffffff00
-#define BCHP_SWITCH_CORE_UDF_2_B_0_8_Port_4_reserved_for_padding0_SHIFT 8
-
-/* SWITCH_CORE :: UDF_2_B_0_8_Port_4 :: CFG_UDF_2_B_0_8 [07:00] */
-#define BCHP_SWITCH_CORE_UDF_2_B_0_8_Port_4_CFG_UDF_2_B_0_8_MASK 0x000000ff
-#define BCHP_SWITCH_CORE_UDF_2_B_0_8_Port_4_CFG_UDF_2_B_0_8_SHIFT 0
-#define BCHP_SWITCH_CORE_UDF_2_B_0_8_Port_4_CFG_UDF_2_B_0_8_DEFAULT 0x00000000
-
-/***************************************************************************
- *UDF_2_B_0_8_Port_5 - UDFs of slice 2 for IPv6 Registers
- ***************************************************************************/
-/* SWITCH_CORE :: UDF_2_B_0_8_Port_5 :: reserved_for_padding0 [31:08] */
-#define BCHP_SWITCH_CORE_UDF_2_B_0_8_Port_5_reserved_for_padding0_MASK 0xffffff00
-#define BCHP_SWITCH_CORE_UDF_2_B_0_8_Port_5_reserved_for_padding0_SHIFT 8
-
-/* SWITCH_CORE :: UDF_2_B_0_8_Port_5 :: CFG_UDF_2_B_0_8 [07:00] */
-#define BCHP_SWITCH_CORE_UDF_2_B_0_8_Port_5_CFG_UDF_2_B_0_8_MASK 0x000000ff
-#define BCHP_SWITCH_CORE_UDF_2_B_0_8_Port_5_CFG_UDF_2_B_0_8_SHIFT 0
-#define BCHP_SWITCH_CORE_UDF_2_B_0_8_Port_5_CFG_UDF_2_B_0_8_DEFAULT 0x00000000
-
-/***************************************************************************
- *UDF_2_B_0_8_Port_6 - UDFs of slice 2 for IPv6 Registers
- ***************************************************************************/
-/* SWITCH_CORE :: UDF_2_B_0_8_Port_6 :: reserved_for_padding0 [31:08] */
-#define BCHP_SWITCH_CORE_UDF_2_B_0_8_Port_6_reserved_for_padding0_MASK 0xffffff00
-#define BCHP_SWITCH_CORE_UDF_2_B_0_8_Port_6_reserved_for_padding0_SHIFT 8
-
-/* SWITCH_CORE :: UDF_2_B_0_8_Port_6 :: CFG_UDF_2_B_0_8 [07:00] */
-#define BCHP_SWITCH_CORE_UDF_2_B_0_8_Port_6_CFG_UDF_2_B_0_8_MASK 0x000000ff
-#define BCHP_SWITCH_CORE_UDF_2_B_0_8_Port_6_CFG_UDF_2_B_0_8_SHIFT 0
-#define BCHP_SWITCH_CORE_UDF_2_B_0_8_Port_6_CFG_UDF_2_B_0_8_DEFAULT 0x00000000
-
-/***************************************************************************
- *UDF_2_B_0_8_Port_7 - UDFs of slice 2 for IPv6 Registers
- ***************************************************************************/
-/* SWITCH_CORE :: UDF_2_B_0_8_Port_7 :: reserved_for_padding0 [31:08] */
-#define BCHP_SWITCH_CORE_UDF_2_B_0_8_Port_7_reserved_for_padding0_MASK 0xffffff00
-#define BCHP_SWITCH_CORE_UDF_2_B_0_8_Port_7_reserved_for_padding0_SHIFT 8
-
-/* SWITCH_CORE :: UDF_2_B_0_8_Port_7 :: CFG_UDF_2_B_0_8 [07:00] */
-#define BCHP_SWITCH_CORE_UDF_2_B_0_8_Port_7_CFG_UDF_2_B_0_8_MASK 0x000000ff
-#define BCHP_SWITCH_CORE_UDF_2_B_0_8_Port_7_CFG_UDF_2_B_0_8_SHIFT 0
-#define BCHP_SWITCH_CORE_UDF_2_B_0_8_Port_7_CFG_UDF_2_B_0_8_DEFAULT 0x00000000
-
-/***************************************************************************
- *UDF_2_B_0_8_Port_8 - UDFs of slice 2 for IPv6 Registers
- ***************************************************************************/
-/* SWITCH_CORE :: UDF_2_B_0_8_Port_8 :: reserved_for_padding0 [31:08] */
-#define BCHP_SWITCH_CORE_UDF_2_B_0_8_Port_8_reserved_for_padding0_MASK 0xffffff00
-#define BCHP_SWITCH_CORE_UDF_2_B_0_8_Port_8_reserved_for_padding0_SHIFT 8
-
-/* SWITCH_CORE :: UDF_2_B_0_8_Port_8 :: CFG_UDF_2_B_0_8 [07:00] */
-#define BCHP_SWITCH_CORE_UDF_2_B_0_8_Port_8_CFG_UDF_2_B_0_8_MASK 0x000000ff
-#define BCHP_SWITCH_CORE_UDF_2_B_0_8_Port_8_CFG_UDF_2_B_0_8_SHIFT 0
-#define BCHP_SWITCH_CORE_UDF_2_B_0_8_Port_8_CFG_UDF_2_B_0_8_DEFAULT 0x00000000
-
-/***************************************************************************
- *UDF_0_C_0_8_Port_0 - UDFs of slice 0 for none-IP Registers
- ***************************************************************************/
-/* SWITCH_CORE :: UDF_0_C_0_8_Port_0 :: reserved_for_padding0 [31:08] */
-#define BCHP_SWITCH_CORE_UDF_0_C_0_8_Port_0_reserved_for_padding0_MASK 0xffffff00
-#define BCHP_SWITCH_CORE_UDF_0_C_0_8_Port_0_reserved_for_padding0_SHIFT 8
-
-/* SWITCH_CORE :: UDF_0_C_0_8_Port_0 :: CFG_UDF_0_C_0_8 [07:00] */
-#define BCHP_SWITCH_CORE_UDF_0_C_0_8_Port_0_CFG_UDF_0_C_0_8_MASK 0x000000ff
-#define BCHP_SWITCH_CORE_UDF_0_C_0_8_Port_0_CFG_UDF_0_C_0_8_SHIFT 0
-#define BCHP_SWITCH_CORE_UDF_0_C_0_8_Port_0_CFG_UDF_0_C_0_8_DEFAULT 0x00000000
-
-/***************************************************************************
- *UDF_0_C_0_8_Port_1 - UDFs of slice 0 for none-IP Registers
- ***************************************************************************/
-/* SWITCH_CORE :: UDF_0_C_0_8_Port_1 :: reserved_for_padding0 [31:08] */
-#define BCHP_SWITCH_CORE_UDF_0_C_0_8_Port_1_reserved_for_padding0_MASK 0xffffff00
-#define BCHP_SWITCH_CORE_UDF_0_C_0_8_Port_1_reserved_for_padding0_SHIFT 8
-
-/* SWITCH_CORE :: UDF_0_C_0_8_Port_1 :: CFG_UDF_0_C_0_8 [07:00] */
-#define BCHP_SWITCH_CORE_UDF_0_C_0_8_Port_1_CFG_UDF_0_C_0_8_MASK 0x000000ff
-#define BCHP_SWITCH_CORE_UDF_0_C_0_8_Port_1_CFG_UDF_0_C_0_8_SHIFT 0
-#define BCHP_SWITCH_CORE_UDF_0_C_0_8_Port_1_CFG_UDF_0_C_0_8_DEFAULT 0x00000000
-
-/***************************************************************************
- *UDF_0_C_0_8_Port_2 - UDFs of slice 0 for none-IP Registers
- ***************************************************************************/
-/* SWITCH_CORE :: UDF_0_C_0_8_Port_2 :: reserved_for_padding0 [31:08] */
-#define BCHP_SWITCH_CORE_UDF_0_C_0_8_Port_2_reserved_for_padding0_MASK 0xffffff00
-#define BCHP_SWITCH_CORE_UDF_0_C_0_8_Port_2_reserved_for_padding0_SHIFT 8
-
-/* SWITCH_CORE :: UDF_0_C_0_8_Port_2 :: CFG_UDF_0_C_0_8 [07:00] */
-#define BCHP_SWITCH_CORE_UDF_0_C_0_8_Port_2_CFG_UDF_0_C_0_8_MASK 0x000000ff
-#define BCHP_SWITCH_CORE_UDF_0_C_0_8_Port_2_CFG_UDF_0_C_0_8_SHIFT 0
-#define BCHP_SWITCH_CORE_UDF_0_C_0_8_Port_2_CFG_UDF_0_C_0_8_DEFAULT 0x00000000
-
-/***************************************************************************
- *UDF_0_C_0_8_Port_3 - UDFs of slice 0 for none-IP Registers
- ***************************************************************************/
-/* SWITCH_CORE :: UDF_0_C_0_8_Port_3 :: reserved_for_padding0 [31:08] */
-#define BCHP_SWITCH_CORE_UDF_0_C_0_8_Port_3_reserved_for_padding0_MASK 0xffffff00
-#define BCHP_SWITCH_CORE_UDF_0_C_0_8_Port_3_reserved_for_padding0_SHIFT 8
-
-/* SWITCH_CORE :: UDF_0_C_0_8_Port_3 :: CFG_UDF_0_C_0_8 [07:00] */
-#define BCHP_SWITCH_CORE_UDF_0_C_0_8_Port_3_CFG_UDF_0_C_0_8_MASK 0x000000ff
-#define BCHP_SWITCH_CORE_UDF_0_C_0_8_Port_3_CFG_UDF_0_C_0_8_SHIFT 0
-#define BCHP_SWITCH_CORE_UDF_0_C_0_8_Port_3_CFG_UDF_0_C_0_8_DEFAULT 0x00000000
-
-/***************************************************************************
- *UDF_0_C_0_8_Port_4 - UDFs of slice 0 for none-IP Registers
- ***************************************************************************/
-/* SWITCH_CORE :: UDF_0_C_0_8_Port_4 :: reserved_for_padding0 [31:08] */
-#define BCHP_SWITCH_CORE_UDF_0_C_0_8_Port_4_reserved_for_padding0_MASK 0xffffff00
-#define BCHP_SWITCH_CORE_UDF_0_C_0_8_Port_4_reserved_for_padding0_SHIFT 8
-
-/* SWITCH_CORE :: UDF_0_C_0_8_Port_4 :: CFG_UDF_0_C_0_8 [07:00] */
-#define BCHP_SWITCH_CORE_UDF_0_C_0_8_Port_4_CFG_UDF_0_C_0_8_MASK 0x000000ff
-#define BCHP_SWITCH_CORE_UDF_0_C_0_8_Port_4_CFG_UDF_0_C_0_8_SHIFT 0
-#define BCHP_SWITCH_CORE_UDF_0_C_0_8_Port_4_CFG_UDF_0_C_0_8_DEFAULT 0x00000000
-
-/***************************************************************************
- *UDF_0_C_0_8_Port_5 - UDFs of slice 0 for none-IP Registers
- ***************************************************************************/
-/* SWITCH_CORE :: UDF_0_C_0_8_Port_5 :: reserved_for_padding0 [31:08] */
-#define BCHP_SWITCH_CORE_UDF_0_C_0_8_Port_5_reserved_for_padding0_MASK 0xffffff00
-#define BCHP_SWITCH_CORE_UDF_0_C_0_8_Port_5_reserved_for_padding0_SHIFT 8
-
-/* SWITCH_CORE :: UDF_0_C_0_8_Port_5 :: CFG_UDF_0_C_0_8 [07:00] */
-#define BCHP_SWITCH_CORE_UDF_0_C_0_8_Port_5_CFG_UDF_0_C_0_8_MASK 0x000000ff
-#define BCHP_SWITCH_CORE_UDF_0_C_0_8_Port_5_CFG_UDF_0_C_0_8_SHIFT 0
-#define BCHP_SWITCH_CORE_UDF_0_C_0_8_Port_5_CFG_UDF_0_C_0_8_DEFAULT 0x00000000
-
-/***************************************************************************
- *UDF_0_C_0_8_Port_6 - UDFs of slice 0 for none-IP Registers
- ***************************************************************************/
-/* SWITCH_CORE :: UDF_0_C_0_8_Port_6 :: reserved_for_padding0 [31:08] */
-#define BCHP_SWITCH_CORE_UDF_0_C_0_8_Port_6_reserved_for_padding0_MASK 0xffffff00
-#define BCHP_SWITCH_CORE_UDF_0_C_0_8_Port_6_reserved_for_padding0_SHIFT 8
-
-/* SWITCH_CORE :: UDF_0_C_0_8_Port_6 :: CFG_UDF_0_C_0_8 [07:00] */
-#define BCHP_SWITCH_CORE_UDF_0_C_0_8_Port_6_CFG_UDF_0_C_0_8_MASK 0x000000ff
-#define BCHP_SWITCH_CORE_UDF_0_C_0_8_Port_6_CFG_UDF_0_C_0_8_SHIFT 0
-#define BCHP_SWITCH_CORE_UDF_0_C_0_8_Port_6_CFG_UDF_0_C_0_8_DEFAULT 0x00000000
-
-/***************************************************************************
- *UDF_0_C_0_8_Port_7 - UDFs of slice 0 for none-IP Registers
- ***************************************************************************/
-/* SWITCH_CORE :: UDF_0_C_0_8_Port_7 :: reserved_for_padding0 [31:08] */
-#define BCHP_SWITCH_CORE_UDF_0_C_0_8_Port_7_reserved_for_padding0_MASK 0xffffff00
-#define BCHP_SWITCH_CORE_UDF_0_C_0_8_Port_7_reserved_for_padding0_SHIFT 8
-
-/* SWITCH_CORE :: UDF_0_C_0_8_Port_7 :: CFG_UDF_0_C_0_8 [07:00] */
-#define BCHP_SWITCH_CORE_UDF_0_C_0_8_Port_7_CFG_UDF_0_C_0_8_MASK 0x000000ff
-#define BCHP_SWITCH_CORE_UDF_0_C_0_8_Port_7_CFG_UDF_0_C_0_8_SHIFT 0
-#define BCHP_SWITCH_CORE_UDF_0_C_0_8_Port_7_CFG_UDF_0_C_0_8_DEFAULT 0x00000000
-
-/***************************************************************************
- *UDF_0_C_0_8_Port_8 - UDFs of slice 0 for none-IP Registers
- ***************************************************************************/
-/* SWITCH_CORE :: UDF_0_C_0_8_Port_8 :: reserved_for_padding0 [31:08] */
-#define BCHP_SWITCH_CORE_UDF_0_C_0_8_Port_8_reserved_for_padding0_MASK 0xffffff00
-#define BCHP_SWITCH_CORE_UDF_0_C_0_8_Port_8_reserved_for_padding0_SHIFT 8
-
-/* SWITCH_CORE :: UDF_0_C_0_8_Port_8 :: CFG_UDF_0_C_0_8 [07:00] */
-#define BCHP_SWITCH_CORE_UDF_0_C_0_8_Port_8_CFG_UDF_0_C_0_8_MASK 0x000000ff
-#define BCHP_SWITCH_CORE_UDF_0_C_0_8_Port_8_CFG_UDF_0_C_0_8_SHIFT 0
-#define BCHP_SWITCH_CORE_UDF_0_C_0_8_Port_8_CFG_UDF_0_C_0_8_DEFAULT 0x00000000
-
-/***************************************************************************
- *UDF_1_C_0_8_Port_0 - UDFs of slice 1 for none-IP Registers
- ***************************************************************************/
-/* SWITCH_CORE :: UDF_1_C_0_8_Port_0 :: reserved_for_padding0 [31:08] */
-#define BCHP_SWITCH_CORE_UDF_1_C_0_8_Port_0_reserved_for_padding0_MASK 0xffffff00
-#define BCHP_SWITCH_CORE_UDF_1_C_0_8_Port_0_reserved_for_padding0_SHIFT 8
-
-/* SWITCH_CORE :: UDF_1_C_0_8_Port_0 :: CFG_UDF_1_C_0_8 [07:00] */
-#define BCHP_SWITCH_CORE_UDF_1_C_0_8_Port_0_CFG_UDF_1_C_0_8_MASK 0x000000ff
-#define BCHP_SWITCH_CORE_UDF_1_C_0_8_Port_0_CFG_UDF_1_C_0_8_SHIFT 0
-#define BCHP_SWITCH_CORE_UDF_1_C_0_8_Port_0_CFG_UDF_1_C_0_8_DEFAULT 0x00000000
-
-/***************************************************************************
- *UDF_1_C_0_8_Port_1 - UDFs of slice 1 for none-IP Registers
- ***************************************************************************/
-/* SWITCH_CORE :: UDF_1_C_0_8_Port_1 :: reserved_for_padding0 [31:08] */
-#define BCHP_SWITCH_CORE_UDF_1_C_0_8_Port_1_reserved_for_padding0_MASK 0xffffff00
-#define BCHP_SWITCH_CORE_UDF_1_C_0_8_Port_1_reserved_for_padding0_SHIFT 8
-
-/* SWITCH_CORE :: UDF_1_C_0_8_Port_1 :: CFG_UDF_1_C_0_8 [07:00] */
-#define BCHP_SWITCH_CORE_UDF_1_C_0_8_Port_1_CFG_UDF_1_C_0_8_MASK 0x000000ff
-#define BCHP_SWITCH_CORE_UDF_1_C_0_8_Port_1_CFG_UDF_1_C_0_8_SHIFT 0
-#define BCHP_SWITCH_CORE_UDF_1_C_0_8_Port_1_CFG_UDF_1_C_0_8_DEFAULT 0x00000000
-
-/***************************************************************************
- *UDF_1_C_0_8_Port_2 - UDFs of slice 1 for none-IP Registers
- ***************************************************************************/
-/* SWITCH_CORE :: UDF_1_C_0_8_Port_2 :: reserved_for_padding0 [31:08] */
-#define BCHP_SWITCH_CORE_UDF_1_C_0_8_Port_2_reserved_for_padding0_MASK 0xffffff00
-#define BCHP_SWITCH_CORE_UDF_1_C_0_8_Port_2_reserved_for_padding0_SHIFT 8
-
-/* SWITCH_CORE :: UDF_1_C_0_8_Port_2 :: CFG_UDF_1_C_0_8 [07:00] */
-#define BCHP_SWITCH_CORE_UDF_1_C_0_8_Port_2_CFG_UDF_1_C_0_8_MASK 0x000000ff
-#define BCHP_SWITCH_CORE_UDF_1_C_0_8_Port_2_CFG_UDF_1_C_0_8_SHIFT 0
-#define BCHP_SWITCH_CORE_UDF_1_C_0_8_Port_2_CFG_UDF_1_C_0_8_DEFAULT 0x00000000
-
-/***************************************************************************
- *UDF_1_C_0_8_Port_3 - UDFs of slice 1 for none-IP Registers
- ***************************************************************************/
-/* SWITCH_CORE :: UDF_1_C_0_8_Port_3 :: reserved_for_padding0 [31:08] */
-#define BCHP_SWITCH_CORE_UDF_1_C_0_8_Port_3_reserved_for_padding0_MASK 0xffffff00
-#define BCHP_SWITCH_CORE_UDF_1_C_0_8_Port_3_reserved_for_padding0_SHIFT 8
-
-/* SWITCH_CORE :: UDF_1_C_0_8_Port_3 :: CFG_UDF_1_C_0_8 [07:00] */
-#define BCHP_SWITCH_CORE_UDF_1_C_0_8_Port_3_CFG_UDF_1_C_0_8_MASK 0x000000ff
-#define BCHP_SWITCH_CORE_UDF_1_C_0_8_Port_3_CFG_UDF_1_C_0_8_SHIFT 0
-#define BCHP_SWITCH_CORE_UDF_1_C_0_8_Port_3_CFG_UDF_1_C_0_8_DEFAULT 0x00000000
-
-/***************************************************************************
- *UDF_1_C_0_8_Port_4 - UDFs of slice 1 for none-IP Registers
- ***************************************************************************/
-/* SWITCH_CORE :: UDF_1_C_0_8_Port_4 :: reserved_for_padding0 [31:08] */
-#define BCHP_SWITCH_CORE_UDF_1_C_0_8_Port_4_reserved_for_padding0_MASK 0xffffff00
-#define BCHP_SWITCH_CORE_UDF_1_C_0_8_Port_4_reserved_for_padding0_SHIFT 8
-
-/* SWITCH_CORE :: UDF_1_C_0_8_Port_4 :: CFG_UDF_1_C_0_8 [07:00] */
-#define BCHP_SWITCH_CORE_UDF_1_C_0_8_Port_4_CFG_UDF_1_C_0_8_MASK 0x000000ff
-#define BCHP_SWITCH_CORE_UDF_1_C_0_8_Port_4_CFG_UDF_1_C_0_8_SHIFT 0
-#define BCHP_SWITCH_CORE_UDF_1_C_0_8_Port_4_CFG_UDF_1_C_0_8_DEFAULT 0x00000000
-
-/***************************************************************************
- *UDF_1_C_0_8_Port_5 - UDFs of slice 1 for none-IP Registers
- ***************************************************************************/
-/* SWITCH_CORE :: UDF_1_C_0_8_Port_5 :: reserved_for_padding0 [31:08] */
-#define BCHP_SWITCH_CORE_UDF_1_C_0_8_Port_5_reserved_for_padding0_MASK 0xffffff00
-#define BCHP_SWITCH_CORE_UDF_1_C_0_8_Port_5_reserved_for_padding0_SHIFT 8
-
-/* SWITCH_CORE :: UDF_1_C_0_8_Port_5 :: CFG_UDF_1_C_0_8 [07:00] */
-#define BCHP_SWITCH_CORE_UDF_1_C_0_8_Port_5_CFG_UDF_1_C_0_8_MASK 0x000000ff
-#define BCHP_SWITCH_CORE_UDF_1_C_0_8_Port_5_CFG_UDF_1_C_0_8_SHIFT 0
-#define BCHP_SWITCH_CORE_UDF_1_C_0_8_Port_5_CFG_UDF_1_C_0_8_DEFAULT 0x00000000
-
-/***************************************************************************
- *UDF_1_C_0_8_Port_6 - UDFs of slice 1 for none-IP Registers
- ***************************************************************************/
-/* SWITCH_CORE :: UDF_1_C_0_8_Port_6 :: reserved_for_padding0 [31:08] */
-#define BCHP_SWITCH_CORE_UDF_1_C_0_8_Port_6_reserved_for_padding0_MASK 0xffffff00
-#define BCHP_SWITCH_CORE_UDF_1_C_0_8_Port_6_reserved_for_padding0_SHIFT 8
-
-/* SWITCH_CORE :: UDF_1_C_0_8_Port_6 :: CFG_UDF_1_C_0_8 [07:00] */
-#define BCHP_SWITCH_CORE_UDF_1_C_0_8_Port_6_CFG_UDF_1_C_0_8_MASK 0x000000ff
-#define BCHP_SWITCH_CORE_UDF_1_C_0_8_Port_6_CFG_UDF_1_C_0_8_SHIFT 0
-#define BCHP_SWITCH_CORE_UDF_1_C_0_8_Port_6_CFG_UDF_1_C_0_8_DEFAULT 0x00000000
-
-/***************************************************************************
- *UDF_1_C_0_8_Port_7 - UDFs of slice 1 for none-IP Registers
- ***************************************************************************/
-/* SWITCH_CORE :: UDF_1_C_0_8_Port_7 :: reserved_for_padding0 [31:08] */
-#define BCHP_SWITCH_CORE_UDF_1_C_0_8_Port_7_reserved_for_padding0_MASK 0xffffff00
-#define BCHP_SWITCH_CORE_UDF_1_C_0_8_Port_7_reserved_for_padding0_SHIFT 8
-
-/* SWITCH_CORE :: UDF_1_C_0_8_Port_7 :: CFG_UDF_1_C_0_8 [07:00] */
-#define BCHP_SWITCH_CORE_UDF_1_C_0_8_Port_7_CFG_UDF_1_C_0_8_MASK 0x000000ff
-#define BCHP_SWITCH_CORE_UDF_1_C_0_8_Port_7_CFG_UDF_1_C_0_8_SHIFT 0
-#define BCHP_SWITCH_CORE_UDF_1_C_0_8_Port_7_CFG_UDF_1_C_0_8_DEFAULT 0x00000000
-
-/***************************************************************************
- *UDF_1_C_0_8_Port_8 - UDFs of slice 1 for none-IP Registers
- ***************************************************************************/
-/* SWITCH_CORE :: UDF_1_C_0_8_Port_8 :: reserved_for_padding0 [31:08] */
-#define BCHP_SWITCH_CORE_UDF_1_C_0_8_Port_8_reserved_for_padding0_MASK 0xffffff00
-#define BCHP_SWITCH_CORE_UDF_1_C_0_8_Port_8_reserved_for_padding0_SHIFT 8
-
-/* SWITCH_CORE :: UDF_1_C_0_8_Port_8 :: CFG_UDF_1_C_0_8 [07:00] */
-#define BCHP_SWITCH_CORE_UDF_1_C_0_8_Port_8_CFG_UDF_1_C_0_8_MASK 0x000000ff
-#define BCHP_SWITCH_CORE_UDF_1_C_0_8_Port_8_CFG_UDF_1_C_0_8_SHIFT 0
-#define BCHP_SWITCH_CORE_UDF_1_C_0_8_Port_8_CFG_UDF_1_C_0_8_DEFAULT 0x00000000
-
-/***************************************************************************
- *UDF_2_C_0_8_Port_0 - UDFs of slice 2 for none-IP Registers
- ***************************************************************************/
-/* SWITCH_CORE :: UDF_2_C_0_8_Port_0 :: reserved_for_padding0 [31:08] */
-#define BCHP_SWITCH_CORE_UDF_2_C_0_8_Port_0_reserved_for_padding0_MASK 0xffffff00
-#define BCHP_SWITCH_CORE_UDF_2_C_0_8_Port_0_reserved_for_padding0_SHIFT 8
-
-/* SWITCH_CORE :: UDF_2_C_0_8_Port_0 :: CFG_UDF_1_C_0_8 [07:00] */
-#define BCHP_SWITCH_CORE_UDF_2_C_0_8_Port_0_CFG_UDF_1_C_0_8_MASK 0x000000ff
-#define BCHP_SWITCH_CORE_UDF_2_C_0_8_Port_0_CFG_UDF_1_C_0_8_SHIFT 0
-#define BCHP_SWITCH_CORE_UDF_2_C_0_8_Port_0_CFG_UDF_1_C_0_8_DEFAULT 0x00000000
-
-/***************************************************************************
- *UDF_2_C_0_8_Port_1 - UDFs of slice 2 for none-IP Registers
- ***************************************************************************/
-/* SWITCH_CORE :: UDF_2_C_0_8_Port_1 :: reserved_for_padding0 [31:08] */
-#define BCHP_SWITCH_CORE_UDF_2_C_0_8_Port_1_reserved_for_padding0_MASK 0xffffff00
-#define BCHP_SWITCH_CORE_UDF_2_C_0_8_Port_1_reserved_for_padding0_SHIFT 8
-
-/* SWITCH_CORE :: UDF_2_C_0_8_Port_1 :: CFG_UDF_1_C_0_8 [07:00] */
-#define BCHP_SWITCH_CORE_UDF_2_C_0_8_Port_1_CFG_UDF_1_C_0_8_MASK 0x000000ff
-#define BCHP_SWITCH_CORE_UDF_2_C_0_8_Port_1_CFG_UDF_1_C_0_8_SHIFT 0
-#define BCHP_SWITCH_CORE_UDF_2_C_0_8_Port_1_CFG_UDF_1_C_0_8_DEFAULT 0x00000000
-
-/***************************************************************************
- *UDF_2_C_0_8_Port_2 - UDFs of slice 2 for none-IP Registers
- ***************************************************************************/
-/* SWITCH_CORE :: UDF_2_C_0_8_Port_2 :: reserved_for_padding0 [31:08] */
-#define BCHP_SWITCH_CORE_UDF_2_C_0_8_Port_2_reserved_for_padding0_MASK 0xffffff00
-#define BCHP_SWITCH_CORE_UDF_2_C_0_8_Port_2_reserved_for_padding0_SHIFT 8
-
-/* SWITCH_CORE :: UDF_2_C_0_8_Port_2 :: CFG_UDF_1_C_0_8 [07:00] */
-#define BCHP_SWITCH_CORE_UDF_2_C_0_8_Port_2_CFG_UDF_1_C_0_8_MASK 0x000000ff
-#define BCHP_SWITCH_CORE_UDF_2_C_0_8_Port_2_CFG_UDF_1_C_0_8_SHIFT 0
-#define BCHP_SWITCH_CORE_UDF_2_C_0_8_Port_2_CFG_UDF_1_C_0_8_DEFAULT 0x00000000
-
-/***************************************************************************
- *UDF_2_C_0_8_Port_3 - UDFs of slice 2 for none-IP Registers
- ***************************************************************************/
-/* SWITCH_CORE :: UDF_2_C_0_8_Port_3 :: reserved_for_padding0 [31:08] */
-#define BCHP_SWITCH_CORE_UDF_2_C_0_8_Port_3_reserved_for_padding0_MASK 0xffffff00
-#define BCHP_SWITCH_CORE_UDF_2_C_0_8_Port_3_reserved_for_padding0_SHIFT 8
-
-/* SWITCH_CORE :: UDF_2_C_0_8_Port_3 :: CFG_UDF_1_C_0_8 [07:00] */
-#define BCHP_SWITCH_CORE_UDF_2_C_0_8_Port_3_CFG_UDF_1_C_0_8_MASK 0x000000ff
-#define BCHP_SWITCH_CORE_UDF_2_C_0_8_Port_3_CFG_UDF_1_C_0_8_SHIFT 0
-#define BCHP_SWITCH_CORE_UDF_2_C_0_8_Port_3_CFG_UDF_1_C_0_8_DEFAULT 0x00000000
-
-/***************************************************************************
- *UDF_2_C_0_8_Port_4 - UDFs of slice 2 for none-IP Registers
- ***************************************************************************/
-/* SWITCH_CORE :: UDF_2_C_0_8_Port_4 :: reserved_for_padding0 [31:08] */
-#define BCHP_SWITCH_CORE_UDF_2_C_0_8_Port_4_reserved_for_padding0_MASK 0xffffff00
-#define BCHP_SWITCH_CORE_UDF_2_C_0_8_Port_4_reserved_for_padding0_SHIFT 8
-
-/* SWITCH_CORE :: UDF_2_C_0_8_Port_4 :: CFG_UDF_1_C_0_8 [07:00] */
-#define BCHP_SWITCH_CORE_UDF_2_C_0_8_Port_4_CFG_UDF_1_C_0_8_MASK 0x000000ff
-#define BCHP_SWITCH_CORE_UDF_2_C_0_8_Port_4_CFG_UDF_1_C_0_8_SHIFT 0
-#define BCHP_SWITCH_CORE_UDF_2_C_0_8_Port_4_CFG_UDF_1_C_0_8_DEFAULT 0x00000000
-
-/***************************************************************************
- *UDF_2_C_0_8_Port_5 - UDFs of slice 2 for none-IP Registers
- ***************************************************************************/
-/* SWITCH_CORE :: UDF_2_C_0_8_Port_5 :: reserved_for_padding0 [31:08] */
-#define BCHP_SWITCH_CORE_UDF_2_C_0_8_Port_5_reserved_for_padding0_MASK 0xffffff00
-#define BCHP_SWITCH_CORE_UDF_2_C_0_8_Port_5_reserved_for_padding0_SHIFT 8
-
-/* SWITCH_CORE :: UDF_2_C_0_8_Port_5 :: CFG_UDF_1_C_0_8 [07:00] */
-#define BCHP_SWITCH_CORE_UDF_2_C_0_8_Port_5_CFG_UDF_1_C_0_8_MASK 0x000000ff
-#define BCHP_SWITCH_CORE_UDF_2_C_0_8_Port_5_CFG_UDF_1_C_0_8_SHIFT 0
-#define BCHP_SWITCH_CORE_UDF_2_C_0_8_Port_5_CFG_UDF_1_C_0_8_DEFAULT 0x00000000
-
-/***************************************************************************
- *UDF_2_C_0_8_Port_6 - UDFs of slice 2 for none-IP Registers
- ***************************************************************************/
-/* SWITCH_CORE :: UDF_2_C_0_8_Port_6 :: reserved_for_padding0 [31:08] */
-#define BCHP_SWITCH_CORE_UDF_2_C_0_8_Port_6_reserved_for_padding0_MASK 0xffffff00
-#define BCHP_SWITCH_CORE_UDF_2_C_0_8_Port_6_reserved_for_padding0_SHIFT 8
-
-/* SWITCH_CORE :: UDF_2_C_0_8_Port_6 :: CFG_UDF_1_C_0_8 [07:00] */
-#define BCHP_SWITCH_CORE_UDF_2_C_0_8_Port_6_CFG_UDF_1_C_0_8_MASK 0x000000ff
-#define BCHP_SWITCH_CORE_UDF_2_C_0_8_Port_6_CFG_UDF_1_C_0_8_SHIFT 0
-#define BCHP_SWITCH_CORE_UDF_2_C_0_8_Port_6_CFG_UDF_1_C_0_8_DEFAULT 0x00000000
-
-/***************************************************************************
- *UDF_2_C_0_8_Port_7 - UDFs of slice 2 for none-IP Registers
- ***************************************************************************/
-/* SWITCH_CORE :: UDF_2_C_0_8_Port_7 :: reserved_for_padding0 [31:08] */
-#define BCHP_SWITCH_CORE_UDF_2_C_0_8_Port_7_reserved_for_padding0_MASK 0xffffff00
-#define BCHP_SWITCH_CORE_UDF_2_C_0_8_Port_7_reserved_for_padding0_SHIFT 8
-
-/* SWITCH_CORE :: UDF_2_C_0_8_Port_7 :: CFG_UDF_1_C_0_8 [07:00] */
-#define BCHP_SWITCH_CORE_UDF_2_C_0_8_Port_7_CFG_UDF_1_C_0_8_MASK 0x000000ff
-#define BCHP_SWITCH_CORE_UDF_2_C_0_8_Port_7_CFG_UDF_1_C_0_8_SHIFT 0
-#define BCHP_SWITCH_CORE_UDF_2_C_0_8_Port_7_CFG_UDF_1_C_0_8_DEFAULT 0x00000000
-
-/***************************************************************************
- *UDF_2_C_0_8_Port_8 - UDFs of slice 2 for none-IP Registers
- ***************************************************************************/
-/* SWITCH_CORE :: UDF_2_C_0_8_Port_8 :: reserved_for_padding0 [31:08] */
-#define BCHP_SWITCH_CORE_UDF_2_C_0_8_Port_8_reserved_for_padding0_MASK 0xffffff00
-#define BCHP_SWITCH_CORE_UDF_2_C_0_8_Port_8_reserved_for_padding0_SHIFT 8
-
-/* SWITCH_CORE :: UDF_2_C_0_8_Port_8 :: CFG_UDF_1_C_0_8 [07:00] */
-#define BCHP_SWITCH_CORE_UDF_2_C_0_8_Port_8_CFG_UDF_1_C_0_8_MASK 0x000000ff
-#define BCHP_SWITCH_CORE_UDF_2_C_0_8_Port_8_CFG_UDF_1_C_0_8_SHIFT 0
-#define BCHP_SWITCH_CORE_UDF_2_C_0_8_Port_8_CFG_UDF_1_C_0_8_DEFAULT 0x00000000
-
-/***************************************************************************
- *UDF_0_D_0_11_Port_0 - UDFs for IPv6 Chain Rule Registers
- ***************************************************************************/
-/* SWITCH_CORE :: UDF_0_D_0_11_Port_0 :: reserved_for_padding0 [31:08] */
-#define BCHP_SWITCH_CORE_UDF_0_D_0_11_Port_0_reserved_for_padding0_MASK 0xffffff00
-#define BCHP_SWITCH_CORE_UDF_0_D_0_11_Port_0_reserved_for_padding0_SHIFT 8
-
-/* SWITCH_CORE :: UDF_0_D_0_11_Port_0 :: CFG_UDF_0_D_0_11 [07:00] */
-#define BCHP_SWITCH_CORE_UDF_0_D_0_11_Port_0_CFG_UDF_0_D_0_11_MASK 0x000000ff
-#define BCHP_SWITCH_CORE_UDF_0_D_0_11_Port_0_CFG_UDF_0_D_0_11_SHIFT 0
-#define BCHP_SWITCH_CORE_UDF_0_D_0_11_Port_0_CFG_UDF_0_D_0_11_DEFAULT 0x00000000
-
-/***************************************************************************
- *UDF_0_D_0_11_Port_1 - UDFs for IPv6 Chain Rule Registers
- ***************************************************************************/
-/* SWITCH_CORE :: UDF_0_D_0_11_Port_1 :: reserved_for_padding0 [31:08] */
-#define BCHP_SWITCH_CORE_UDF_0_D_0_11_Port_1_reserved_for_padding0_MASK 0xffffff00
-#define BCHP_SWITCH_CORE_UDF_0_D_0_11_Port_1_reserved_for_padding0_SHIFT 8
-
-/* SWITCH_CORE :: UDF_0_D_0_11_Port_1 :: CFG_UDF_0_D_0_11 [07:00] */
-#define BCHP_SWITCH_CORE_UDF_0_D_0_11_Port_1_CFG_UDF_0_D_0_11_MASK 0x000000ff
-#define BCHP_SWITCH_CORE_UDF_0_D_0_11_Port_1_CFG_UDF_0_D_0_11_SHIFT 0
-#define BCHP_SWITCH_CORE_UDF_0_D_0_11_Port_1_CFG_UDF_0_D_0_11_DEFAULT 0x00000000
-
-/***************************************************************************
- *UDF_0_D_0_11_Port_2 - UDFs for IPv6 Chain Rule Registers
- ***************************************************************************/
-/* SWITCH_CORE :: UDF_0_D_0_11_Port_2 :: reserved_for_padding0 [31:08] */
-#define BCHP_SWITCH_CORE_UDF_0_D_0_11_Port_2_reserved_for_padding0_MASK 0xffffff00
-#define BCHP_SWITCH_CORE_UDF_0_D_0_11_Port_2_reserved_for_padding0_SHIFT 8
-
-/* SWITCH_CORE :: UDF_0_D_0_11_Port_2 :: CFG_UDF_0_D_0_11 [07:00] */
-#define BCHP_SWITCH_CORE_UDF_0_D_0_11_Port_2_CFG_UDF_0_D_0_11_MASK 0x000000ff
-#define BCHP_SWITCH_CORE_UDF_0_D_0_11_Port_2_CFG_UDF_0_D_0_11_SHIFT 0
-#define BCHP_SWITCH_CORE_UDF_0_D_0_11_Port_2_CFG_UDF_0_D_0_11_DEFAULT 0x00000000
-
-/***************************************************************************
- *UDF_0_D_0_11_Port_3 - UDFs for IPv6 Chain Rule Registers
- ***************************************************************************/
-/* SWITCH_CORE :: UDF_0_D_0_11_Port_3 :: reserved_for_padding0 [31:08] */
-#define BCHP_SWITCH_CORE_UDF_0_D_0_11_Port_3_reserved_for_padding0_MASK 0xffffff00
-#define BCHP_SWITCH_CORE_UDF_0_D_0_11_Port_3_reserved_for_padding0_SHIFT 8
-
-/* SWITCH_CORE :: UDF_0_D_0_11_Port_3 :: CFG_UDF_0_D_0_11 [07:00] */
-#define BCHP_SWITCH_CORE_UDF_0_D_0_11_Port_3_CFG_UDF_0_D_0_11_MASK 0x000000ff
-#define BCHP_SWITCH_CORE_UDF_0_D_0_11_Port_3_CFG_UDF_0_D_0_11_SHIFT 0
-#define BCHP_SWITCH_CORE_UDF_0_D_0_11_Port_3_CFG_UDF_0_D_0_11_DEFAULT 0x00000000
-
-/***************************************************************************
- *UDF_0_D_0_11_Port_4 - UDFs for IPv6 Chain Rule Registers
- ***************************************************************************/
-/* SWITCH_CORE :: UDF_0_D_0_11_Port_4 :: reserved_for_padding0 [31:08] */
-#define BCHP_SWITCH_CORE_UDF_0_D_0_11_Port_4_reserved_for_padding0_MASK 0xffffff00
-#define BCHP_SWITCH_CORE_UDF_0_D_0_11_Port_4_reserved_for_padding0_SHIFT 8
-
-/* SWITCH_CORE :: UDF_0_D_0_11_Port_4 :: CFG_UDF_0_D_0_11 [07:00] */
-#define BCHP_SWITCH_CORE_UDF_0_D_0_11_Port_4_CFG_UDF_0_D_0_11_MASK 0x000000ff
-#define BCHP_SWITCH_CORE_UDF_0_D_0_11_Port_4_CFG_UDF_0_D_0_11_SHIFT 0
-#define BCHP_SWITCH_CORE_UDF_0_D_0_11_Port_4_CFG_UDF_0_D_0_11_DEFAULT 0x00000000
-
-/***************************************************************************
- *UDF_0_D_0_11_Port_5 - UDFs for IPv6 Chain Rule Registers
- ***************************************************************************/
-/* SWITCH_CORE :: UDF_0_D_0_11_Port_5 :: reserved_for_padding0 [31:08] */
-#define BCHP_SWITCH_CORE_UDF_0_D_0_11_Port_5_reserved_for_padding0_MASK 0xffffff00
-#define BCHP_SWITCH_CORE_UDF_0_D_0_11_Port_5_reserved_for_padding0_SHIFT 8
-
-/* SWITCH_CORE :: UDF_0_D_0_11_Port_5 :: CFG_UDF_0_D_0_11 [07:00] */
-#define BCHP_SWITCH_CORE_UDF_0_D_0_11_Port_5_CFG_UDF_0_D_0_11_MASK 0x000000ff
-#define BCHP_SWITCH_CORE_UDF_0_D_0_11_Port_5_CFG_UDF_0_D_0_11_SHIFT 0
-#define BCHP_SWITCH_CORE_UDF_0_D_0_11_Port_5_CFG_UDF_0_D_0_11_DEFAULT 0x00000000
-
-/***************************************************************************
- *UDF_0_D_0_11_Port_6 - UDFs for IPv6 Chain Rule Registers
- ***************************************************************************/
-/* SWITCH_CORE :: UDF_0_D_0_11_Port_6 :: reserved_for_padding0 [31:08] */
-#define BCHP_SWITCH_CORE_UDF_0_D_0_11_Port_6_reserved_for_padding0_MASK 0xffffff00
-#define BCHP_SWITCH_CORE_UDF_0_D_0_11_Port_6_reserved_for_padding0_SHIFT 8
-
-/* SWITCH_CORE :: UDF_0_D_0_11_Port_6 :: CFG_UDF_0_D_0_11 [07:00] */
-#define BCHP_SWITCH_CORE_UDF_0_D_0_11_Port_6_CFG_UDF_0_D_0_11_MASK 0x000000ff
-#define BCHP_SWITCH_CORE_UDF_0_D_0_11_Port_6_CFG_UDF_0_D_0_11_SHIFT 0
-#define BCHP_SWITCH_CORE_UDF_0_D_0_11_Port_6_CFG_UDF_0_D_0_11_DEFAULT 0x00000000
-
-/***************************************************************************
- *UDF_0_D_0_11_Port_7 - UDFs for IPv6 Chain Rule Registers
- ***************************************************************************/
-/* SWITCH_CORE :: UDF_0_D_0_11_Port_7 :: reserved_for_padding0 [31:08] */
-#define BCHP_SWITCH_CORE_UDF_0_D_0_11_Port_7_reserved_for_padding0_MASK 0xffffff00
-#define BCHP_SWITCH_CORE_UDF_0_D_0_11_Port_7_reserved_for_padding0_SHIFT 8
-
-/* SWITCH_CORE :: UDF_0_D_0_11_Port_7 :: CFG_UDF_0_D_0_11 [07:00] */
-#define BCHP_SWITCH_CORE_UDF_0_D_0_11_Port_7_CFG_UDF_0_D_0_11_MASK 0x000000ff
-#define BCHP_SWITCH_CORE_UDF_0_D_0_11_Port_7_CFG_UDF_0_D_0_11_SHIFT 0
-#define BCHP_SWITCH_CORE_UDF_0_D_0_11_Port_7_CFG_UDF_0_D_0_11_DEFAULT 0x00000000
-
-/***************************************************************************
- *UDF_0_D_0_11_Port_8 - UDFs for IPv6 Chain Rule Registers
- ***************************************************************************/
-/* SWITCH_CORE :: UDF_0_D_0_11_Port_8 :: reserved_for_padding0 [31:08] */
-#define BCHP_SWITCH_CORE_UDF_0_D_0_11_Port_8_reserved_for_padding0_MASK 0xffffff00
-#define BCHP_SWITCH_CORE_UDF_0_D_0_11_Port_8_reserved_for_padding0_SHIFT 8
-
-/* SWITCH_CORE :: UDF_0_D_0_11_Port_8 :: CFG_UDF_0_D_0_11 [07:00] */
-#define BCHP_SWITCH_CORE_UDF_0_D_0_11_Port_8_CFG_UDF_0_D_0_11_MASK 0x000000ff
-#define BCHP_SWITCH_CORE_UDF_0_D_0_11_Port_8_CFG_UDF_0_D_0_11_SHIFT 0
-#define BCHP_SWITCH_CORE_UDF_0_D_0_11_Port_8_CFG_UDF_0_D_0_11_DEFAULT 0x00000000
-
-/***************************************************************************
- *UDF_0_D_0_11_Port_9 - UDFs for IPv6 Chain Rule Registers
- ***************************************************************************/
-/* SWITCH_CORE :: UDF_0_D_0_11_Port_9 :: reserved_for_padding0 [31:08] */
-#define BCHP_SWITCH_CORE_UDF_0_D_0_11_Port_9_reserved_for_padding0_MASK 0xffffff00
-#define BCHP_SWITCH_CORE_UDF_0_D_0_11_Port_9_reserved_for_padding0_SHIFT 8
-
-/* SWITCH_CORE :: UDF_0_D_0_11_Port_9 :: CFG_UDF_0_D_0_11 [07:00] */
-#define BCHP_SWITCH_CORE_UDF_0_D_0_11_Port_9_CFG_UDF_0_D_0_11_MASK 0x000000ff
-#define BCHP_SWITCH_CORE_UDF_0_D_0_11_Port_9_CFG_UDF_0_D_0_11_SHIFT 0
-#define BCHP_SWITCH_CORE_UDF_0_D_0_11_Port_9_CFG_UDF_0_D_0_11_DEFAULT 0x00000000
-
-/***************************************************************************
- *UDF_0_D_0_11_Port_10 - UDFs for IPv6 Chain Rule Registers
- ***************************************************************************/
-/* SWITCH_CORE :: UDF_0_D_0_11_Port_10 :: reserved_for_padding0 [31:08] */
-#define BCHP_SWITCH_CORE_UDF_0_D_0_11_Port_10_reserved_for_padding0_MASK 0xffffff00
-#define BCHP_SWITCH_CORE_UDF_0_D_0_11_Port_10_reserved_for_padding0_SHIFT 8
-
-/* SWITCH_CORE :: UDF_0_D_0_11_Port_10 :: CFG_UDF_0_D_0_11 [07:00] */
-#define BCHP_SWITCH_CORE_UDF_0_D_0_11_Port_10_CFG_UDF_0_D_0_11_MASK 0x000000ff
-#define BCHP_SWITCH_CORE_UDF_0_D_0_11_Port_10_CFG_UDF_0_D_0_11_SHIFT 0
-#define BCHP_SWITCH_CORE_UDF_0_D_0_11_Port_10_CFG_UDF_0_D_0_11_DEFAULT 0x00000000
-
-/***************************************************************************
- *UDF_0_D_0_11_Port_11 - UDFs for IPv6 Chain Rule Registers
- ***************************************************************************/
-/* SWITCH_CORE :: UDF_0_D_0_11_Port_11 :: reserved_for_padding0 [31:08] */
-#define BCHP_SWITCH_CORE_UDF_0_D_0_11_Port_11_reserved_for_padding0_MASK 0xffffff00
-#define BCHP_SWITCH_CORE_UDF_0_D_0_11_Port_11_reserved_for_padding0_SHIFT 8
-
-/* SWITCH_CORE :: UDF_0_D_0_11_Port_11 :: CFG_UDF_0_D_0_11 [07:00] */
-#define BCHP_SWITCH_CORE_UDF_0_D_0_11_Port_11_CFG_UDF_0_D_0_11_MASK 0x000000ff
-#define BCHP_SWITCH_CORE_UDF_0_D_0_11_Port_11_CFG_UDF_0_D_0_11_SHIFT 0
-#define BCHP_SWITCH_CORE_UDF_0_D_0_11_Port_11_CFG_UDF_0_D_0_11_DEFAULT 0x00000000
-
-/***************************************************************************
- *OTP_CTL_REG - CPU OTP Control RegistersNot2Release
- ***************************************************************************/
-/* SWITCH_CORE :: OTP_CTL_REG :: BYPASS_OTP_CLK [31:31] */
-#define BCHP_SWITCH_CORE_OTP_CTL_REG_BYPASS_OTP_CLK_MASK 0x80000000
-#define BCHP_SWITCH_CORE_OTP_CTL_REG_BYPASS_OTP_CLK_SHIFT 31
-#define BCHP_SWITCH_CORE_OTP_CTL_REG_BYPASS_OTP_CLK_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: OTP_CTL_REG :: SWITCH_RESV [30:29] */
-#define BCHP_SWITCH_CORE_OTP_CTL_REG_SWITCH_RESV_MASK 0x60000000
-#define BCHP_SWITCH_CORE_OTP_CTL_REG_SWITCH_RESV_SHIFT 29
-#define BCHP_SWITCH_CORE_OTP_CTL_REG_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: OTP_CTL_REG :: CPU_DEBUG_SEL [28:25] */
-#define BCHP_SWITCH_CORE_OTP_CTL_REG_CPU_DEBUG_SEL_MASK 0x1e000000
-#define BCHP_SWITCH_CORE_OTP_CTL_REG_CPU_DEBUG_SEL_SHIFT 25
-#define BCHP_SWITCH_CORE_OTP_CTL_REG_CPU_DEBUG_SEL_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: OTP_CTL_REG :: BURST_STAT_SEL [24:24] */
-#define BCHP_SWITCH_CORE_OTP_CTL_REG_BURST_STAT_SEL_MASK 0x01000000
-#define BCHP_SWITCH_CORE_OTP_CTL_REG_BURST_STAT_SEL_SHIFT 24
-#define BCHP_SWITCH_CORE_OTP_CTL_REG_BURST_STAT_SEL_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: OTP_CTL_REG :: ACCESS_MODE [23:22] */
-#define BCHP_SWITCH_CORE_OTP_CTL_REG_ACCESS_MODE_MASK 0x00c00000
-#define BCHP_SWITCH_CORE_OTP_CTL_REG_ACCESS_MODE_SHIFT 22
-#define BCHP_SWITCH_CORE_OTP_CTL_REG_ACCESS_MODE_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: OTP_CTL_REG :: OTP_PROG_EN [21:21] */
-#define BCHP_SWITCH_CORE_OTP_CTL_REG_OTP_PROG_EN_MASK 0x00200000
-#define BCHP_SWITCH_CORE_OTP_CTL_REG_OTP_PROG_EN_SHIFT 21
-#define BCHP_SWITCH_CORE_OTP_CTL_REG_OTP_PROG_EN_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: OTP_CTL_REG :: OTP_DEBUG_MODE [20:20] */
-#define BCHP_SWITCH_CORE_OTP_CTL_REG_OTP_DEBUG_MODE_MASK 0x00100000
-#define BCHP_SWITCH_CORE_OTP_CTL_REG_OTP_DEBUG_MODE_SHIFT 20
-#define BCHP_SWITCH_CORE_OTP_CTL_REG_OTP_DEBUG_MODE_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: OTP_CTL_REG :: WRP_CONTINUE_ON_FAIL [19:19] */
-#define BCHP_SWITCH_CORE_OTP_CTL_REG_WRP_CONTINUE_ON_FAIL_MASK 0x00080000
-#define BCHP_SWITCH_CORE_OTP_CTL_REG_WRP_CONTINUE_ON_FAIL_SHIFT 19
-#define BCHP_SWITCH_CORE_OTP_CTL_REG_WRP_CONTINUE_ON_FAIL_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: OTP_CTL_REG :: WRP_TIME_MARGIN [18:16] */
-#define BCHP_SWITCH_CORE_OTP_CTL_REG_WRP_TIME_MARGIN_MASK 0x00070000
-#define BCHP_SWITCH_CORE_OTP_CTL_REG_WRP_TIME_MARGIN_SHIFT 16
-#define BCHP_SWITCH_CORE_OTP_CTL_REG_WRP_TIME_MARGIN_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: OTP_CTL_REG :: WRP_SADBYP [15:15] */
-#define BCHP_SWITCH_CORE_OTP_CTL_REG_WRP_SADBYP_MASK 0x00008000
-#define BCHP_SWITCH_CORE_OTP_CTL_REG_WRP_SADBYP_SHIFT 15
-#define BCHP_SWITCH_CORE_OTP_CTL_REG_WRP_SADBYP_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: OTP_CTL_REG :: UNUSED [14:14] */
-#define BCHP_SWITCH_CORE_OTP_CTL_REG_UNUSED_MASK 0x00004000
-#define BCHP_SWITCH_CORE_OTP_CTL_REG_UNUSED_SHIFT 14
-#define BCHP_SWITCH_CORE_OTP_CTL_REG_UNUSED_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: OTP_CTL_REG :: WRP_PBYP [13:13] */
-#define BCHP_SWITCH_CORE_OTP_CTL_REG_WRP_PBYP_MASK 0x00002000
-#define BCHP_SWITCH_CORE_OTP_CTL_REG_WRP_PBYP_SHIFT 13
-#define BCHP_SWITCH_CORE_OTP_CTL_REG_WRP_PBYP_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: OTP_CTL_REG :: WRP_PCOUNT [12:10] */
-#define BCHP_SWITCH_CORE_OTP_CTL_REG_WRP_PCOUNT_MASK 0x00001c00
-#define BCHP_SWITCH_CORE_OTP_CTL_REG_WRP_PCOUNT_SHIFT 10
-#define BCHP_SWITCH_CORE_OTP_CTL_REG_WRP_PCOUNT_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: OTP_CTL_REG :: WRP_VSEL [09:06] */
-#define BCHP_SWITCH_CORE_OTP_CTL_REG_WRP_VSEL_MASK 0x000003c0
-#define BCHP_SWITCH_CORE_OTP_CTL_REG_WRP_VSEL_SHIFT 6
-#define BCHP_SWITCH_CORE_OTP_CTL_REG_WRP_VSEL_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: OTP_CTL_REG :: WRP_PROG_SEL [05:05] */
-#define BCHP_SWITCH_CORE_OTP_CTL_REG_WRP_PROG_SEL_MASK 0x00000020
-#define BCHP_SWITCH_CORE_OTP_CTL_REG_WRP_PROG_SEL_SHIFT 5
-#define BCHP_SWITCH_CORE_OTP_CTL_REG_WRP_PROG_SEL_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: OTP_CTL_REG :: COMMAND [04:01] */
-#define BCHP_SWITCH_CORE_OTP_CTL_REG_COMMAND_MASK 0x0000001e
-#define BCHP_SWITCH_CORE_OTP_CTL_REG_COMMAND_SHIFT 1
-#define BCHP_SWITCH_CORE_OTP_CTL_REG_COMMAND_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: OTP_CTL_REG :: START [00:00] */
-#define BCHP_SWITCH_CORE_OTP_CTL_REG_START_MASK 0x00000001
-#define BCHP_SWITCH_CORE_OTP_CTL_REG_START_SHIFT 0
-#define BCHP_SWITCH_CORE_OTP_CTL_REG_START_DEFAULT 0x00000000
-
-/***************************************************************************
- *OTP_ADDR_REG - CPU OTP Address RegistersNot2Release
- ***************************************************************************/
-/* SWITCH_CORE :: OTP_ADDR_REG :: reserved_for_padding0 [31:16] */
-#define BCHP_SWITCH_CORE_OTP_ADDR_REG_reserved_for_padding0_MASK 0xffff0000
-#define BCHP_SWITCH_CORE_OTP_ADDR_REG_reserved_for_padding0_SHIFT 16
-
-/* SWITCH_CORE :: OTP_ADDR_REG :: CPU_ADDR [15:00] */
-#define BCHP_SWITCH_CORE_OTP_ADDR_REG_CPU_ADDR_MASK 0x0000ffff
-#define BCHP_SWITCH_CORE_OTP_ADDR_REG_CPU_ADDR_SHIFT 0
-#define BCHP_SWITCH_CORE_OTP_ADDR_REG_CPU_ADDR_DEFAULT 0x00000000
-
-/***************************************************************************
- *OTP_STS_REG - CPU OTP Status RegistersNot2Release
- ***************************************************************************/
-/* SWITCH_CORE :: OTP_STS_REG :: reserved_for_padding0 [31:16] */
-#define BCHP_SWITCH_CORE_OTP_STS_REG_reserved_for_padding0_MASK 0xffff0000
-#define BCHP_SWITCH_CORE_OTP_STS_REG_reserved_for_padding0_SHIFT 16
-
-/* SWITCH_CORE :: OTP_STS_REG :: UNUSED_0 [15:12] */
-#define BCHP_SWITCH_CORE_OTP_STS_REG_UNUSED_0_MASK 0x0000f000
-#define BCHP_SWITCH_CORE_OTP_STS_REG_UNUSED_0_SHIFT 12
-#define BCHP_SWITCH_CORE_OTP_STS_REG_UNUSED_0_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: OTP_STS_REG :: CONTROL_ERR [11:11] */
-#define BCHP_SWITCH_CORE_OTP_STS_REG_CONTROL_ERR_MASK 0x00000800
-#define BCHP_SWITCH_CORE_OTP_STS_REG_CONTROL_ERR_SHIFT 11
-#define BCHP_SWITCH_CORE_OTP_STS_REG_CONTROL_ERR_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: OTP_STS_REG :: WRP_ERROR [10:10] */
-#define BCHP_SWITCH_CORE_OTP_STS_REG_WRP_ERROR_MASK 0x00000400
-#define BCHP_SWITCH_CORE_OTP_STS_REG_WRP_ERROR_SHIFT 10
-#define BCHP_SWITCH_CORE_OTP_STS_REG_WRP_ERROR_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: OTP_STS_REG :: INVALID_COMMAND [09:09] */
-#define BCHP_SWITCH_CORE_OTP_STS_REG_INVALID_COMMAND_MASK 0x00000200
-#define BCHP_SWITCH_CORE_OTP_STS_REG_INVALID_COMMAND_SHIFT 9
-#define BCHP_SWITCH_CORE_OTP_STS_REG_INVALID_COMMAND_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: OTP_STS_REG :: UNUSED_1 [08:08] */
-#define BCHP_SWITCH_CORE_OTP_STS_REG_UNUSED_1_MASK 0x00000100
-#define BCHP_SWITCH_CORE_OTP_STS_REG_UNUSED_1_SHIFT 8
-#define BCHP_SWITCH_CORE_OTP_STS_REG_UNUSED_1_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: OTP_STS_REG :: INIT_WAIT_DONE [07:07] */
-#define BCHP_SWITCH_CORE_OTP_STS_REG_INIT_WAIT_DONE_MASK 0x00000080
-#define BCHP_SWITCH_CORE_OTP_STS_REG_INIT_WAIT_DONE_SHIFT 7
-#define BCHP_SWITCH_CORE_OTP_STS_REG_INIT_WAIT_DONE_DEFAULT 0x00000001
-
-/* SWITCH_CORE :: OTP_STS_REG :: PROG_BLOCKED [06:06] */
-#define BCHP_SWITCH_CORE_OTP_STS_REG_PROG_BLOCKED_MASK 0x00000040
-#define BCHP_SWITCH_CORE_OTP_STS_REG_PROG_BLOCKED_SHIFT 6
-#define BCHP_SWITCH_CORE_OTP_STS_REG_PROG_BLOCKED_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: OTP_STS_REG :: INVALID_PROG_REQ [05:05] */
-#define BCHP_SWITCH_CORE_OTP_STS_REG_INVALID_PROG_REQ_MASK 0x00000020
-#define BCHP_SWITCH_CORE_OTP_STS_REG_INVALID_PROG_REQ_SHIFT 5
-#define BCHP_SWITCH_CORE_OTP_STS_REG_INVALID_PROG_REQ_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: OTP_STS_REG :: WRP_FAIL [04:04] */
-#define BCHP_SWITCH_CORE_OTP_STS_REG_WRP_FAIL_MASK 0x00000010
-#define BCHP_SWITCH_CORE_OTP_STS_REG_WRP_FAIL_SHIFT 4
-#define BCHP_SWITCH_CORE_OTP_STS_REG_WRP_FAIL_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: OTP_STS_REG :: WRP_BUSY [03:03] */
-#define BCHP_SWITCH_CORE_OTP_STS_REG_WRP_BUSY_MASK 0x00000008
-#define BCHP_SWITCH_CORE_OTP_STS_REG_WRP_BUSY_SHIFT 3
-#define BCHP_SWITCH_CORE_OTP_STS_REG_WRP_BUSY_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: OTP_STS_REG :: WRP_DOUT [02:02] */
-#define BCHP_SWITCH_CORE_OTP_STS_REG_WRP_DOUT_MASK 0x00000004
-#define BCHP_SWITCH_CORE_OTP_STS_REG_WRP_DOUT_SHIFT 2
-#define BCHP_SWITCH_CORE_OTP_STS_REG_WRP_DOUT_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: OTP_STS_REG :: WRP_DATA_READY [01:01] */
-#define BCHP_SWITCH_CORE_OTP_STS_REG_WRP_DATA_READY_MASK 0x00000002
-#define BCHP_SWITCH_CORE_OTP_STS_REG_WRP_DATA_READY_SHIFT 1
-#define BCHP_SWITCH_CORE_OTP_STS_REG_WRP_DATA_READY_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: OTP_STS_REG :: COMMAND_DONE [00:00] */
-#define BCHP_SWITCH_CORE_OTP_STS_REG_COMMAND_DONE_MASK 0x00000001
-#define BCHP_SWITCH_CORE_OTP_STS_REG_COMMAND_DONE_SHIFT 0
-#define BCHP_SWITCH_CORE_OTP_STS_REG_COMMAND_DONE_DEFAULT 0x00000000
-
-/***************************************************************************
- *OTP_WR_DATA - CPU OTP Write Data RegistersNot2Release
- ***************************************************************************/
-/* SWITCH_CORE :: OTP_WR_DATA :: CPU_WR_DATA [31:00] */
-#define BCHP_SWITCH_CORE_OTP_WR_DATA_CPU_WR_DATA_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_OTP_WR_DATA_CPU_WR_DATA_SHIFT 0
-#define BCHP_SWITCH_CORE_OTP_WR_DATA_CPU_WR_DATA_DEFAULT 0x00000000
-
-/***************************************************************************
- *OTP_RD_DATA - CPU OTP Read Data RegistersNot2Release
- ***************************************************************************/
-/* SWITCH_CORE :: OTP_RD_DATA :: CPU_RD_DATA [31:00] */
-#define BCHP_SWITCH_CORE_OTP_RD_DATA_CPU_RD_DATA_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_OTP_RD_DATA_CPU_RD_DATA_SHIFT 0
-#define BCHP_SWITCH_CORE_OTP_RD_DATA_CPU_RD_DATA_DEFAULT 0x00000000
-
-/***************************************************************************
- *IO_SR_CTL - I/O Pad Slew Rate Control Register (Engineering use only)Not2Release
- ***************************************************************************/
-/* SWITCH_CORE :: IO_SR_CTL :: SWITCH_RESV [31:19] */
-#define BCHP_SWITCH_CORE_IO_SR_CTL_SWITCH_RESV_MASK 0xfff80000
-#define BCHP_SWITCH_CORE_IO_SR_CTL_SWITCH_RESV_SHIFT 19
-#define BCHP_SWITCH_CORE_IO_SR_CTL_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: IO_SR_CTL :: IO_SR_CTL [18:00] */
-#define BCHP_SWITCH_CORE_IO_SR_CTL_IO_SR_CTL_MASK 0x0007ffff
-#define BCHP_SWITCH_CORE_IO_SR_CTL_IO_SR_CTL_SHIFT 0
-#define BCHP_SWITCH_CORE_IO_SR_CTL_IO_SR_CTL_DEFAULT 0x00000600
-
-/***************************************************************************
- *IO_DS_SEL0 - I/O Pad Drive Strength Select 0 Register (Engineering use only)Not2Release
- ***************************************************************************/
-/* SWITCH_CORE :: IO_DS_SEL0 :: SWITCH_RESV [31:19] */
-#define BCHP_SWITCH_CORE_IO_DS_SEL0_SWITCH_RESV_MASK 0xfff80000
-#define BCHP_SWITCH_CORE_IO_DS_SEL0_SWITCH_RESV_SHIFT 19
-#define BCHP_SWITCH_CORE_IO_DS_SEL0_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: IO_DS_SEL0 :: IO_DS_SEL0 [18:00] */
-#define BCHP_SWITCH_CORE_IO_DS_SEL0_IO_DS_SEL0_MASK 0x0007ffff
-#define BCHP_SWITCH_CORE_IO_DS_SEL0_IO_DS_SEL0_SHIFT 0
-#define BCHP_SWITCH_CORE_IO_DS_SEL0_IO_DS_SEL0_DEFAULT 0x0007ffff
-
-/***************************************************************************
- *IO_DS_SEL2 - I/O Pad Drive Strength Select 2 Register (Engineering use only)Not2Release
- ***************************************************************************/
-/* SWITCH_CORE :: IO_DS_SEL2 :: SWITCH_RESV [31:19] */
-#define BCHP_SWITCH_CORE_IO_DS_SEL2_SWITCH_RESV_MASK 0xfff80000
-#define BCHP_SWITCH_CORE_IO_DS_SEL2_SWITCH_RESV_SHIFT 19
-#define BCHP_SWITCH_CORE_IO_DS_SEL2_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: IO_DS_SEL2 :: IO_DS_SEL2 [18:00] */
-#define BCHP_SWITCH_CORE_IO_DS_SEL2_IO_DS_SEL2_MASK 0x0007ffff
-#define BCHP_SWITCH_CORE_IO_DS_SEL2_IO_DS_SEL2_SHIFT 0
-#define BCHP_SWITCH_CORE_IO_DS_SEL2_IO_DS_SEL2_DEFAULT 0x0007ffff
-
-/***************************************************************************
- *GMII_IO_SR_CTL - GMII I/O Pad Slew Rate Control Register (Engineering use only)Not2Release
- ***************************************************************************/
-/* SWITCH_CORE :: GMII_IO_SR_CTL :: SWITCH_RESV [31:03] */
-#define BCHP_SWITCH_CORE_GMII_IO_SR_CTL_SWITCH_RESV_MASK 0xfffffff8
-#define BCHP_SWITCH_CORE_GMII_IO_SR_CTL_SWITCH_RESV_SHIFT 3
-#define BCHP_SWITCH_CORE_GMII_IO_SR_CTL_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: GMII_IO_SR_CTL :: GMII_IO_SR_CTL [02:00] */
-#define BCHP_SWITCH_CORE_GMII_IO_SR_CTL_GMII_IO_SR_CTL_MASK 0x00000007
-#define BCHP_SWITCH_CORE_GMII_IO_SR_CTL_GMII_IO_SR_CTL_SHIFT 0
-#define BCHP_SWITCH_CORE_GMII_IO_SR_CTL_GMII_IO_SR_CTL_DEFAULT 0x00000000
-
-/***************************************************************************
- *GMII_IO_DS_SEL0 - GMII I/O Pad Drive Strength Select 0 Register (Engineering use only)Not2Release
- ***************************************************************************/
-/* SWITCH_CORE :: GMII_IO_DS_SEL0 :: SWITCH_RESV [31:03] */
-#define BCHP_SWITCH_CORE_GMII_IO_DS_SEL0_SWITCH_RESV_MASK 0xfffffff8
-#define BCHP_SWITCH_CORE_GMII_IO_DS_SEL0_SWITCH_RESV_SHIFT 3
-#define BCHP_SWITCH_CORE_GMII_IO_DS_SEL0_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: GMII_IO_DS_SEL0 :: GMII_IO_DS_SEL0 [02:00] */
-#define BCHP_SWITCH_CORE_GMII_IO_DS_SEL0_GMII_IO_DS_SEL0_MASK 0x00000007
-#define BCHP_SWITCH_CORE_GMII_IO_DS_SEL0_GMII_IO_DS_SEL0_SHIFT 0
-#define BCHP_SWITCH_CORE_GMII_IO_DS_SEL0_GMII_IO_DS_SEL0_DEFAULT 0x00000007
-
-/***************************************************************************
- *GMII_IO_DS_SEL1 - GMII I/O Pad Drive Strength Select 1 Register (Engineering use only)Not2Release
- ***************************************************************************/
-/* SWITCH_CORE :: GMII_IO_DS_SEL1 :: SWITCH_RESV [31:03] */
-#define BCHP_SWITCH_CORE_GMII_IO_DS_SEL1_SWITCH_RESV_MASK 0xfffffff8
-#define BCHP_SWITCH_CORE_GMII_IO_DS_SEL1_SWITCH_RESV_SHIFT 3
-#define BCHP_SWITCH_CORE_GMII_IO_DS_SEL1_SWITCH_RESV_DEFAULT 0x00000000
-
-/* SWITCH_CORE :: GMII_IO_DS_SEL1 :: GMII_IO_DS_SEL1 [02:00] */
-#define BCHP_SWITCH_CORE_GMII_IO_DS_SEL1_GMII_IO_DS_SEL1_MASK 0x00000007
-#define BCHP_SWITCH_CORE_GMII_IO_DS_SEL1_GMII_IO_DS_SEL1_SHIFT 0
-#define BCHP_SWITCH_CORE_GMII_IO_DS_SEL1_GMII_IO_DS_SEL1_DEFAULT 0x00000007
-
-/***************************************************************************
- *OTP_CTL_REG_SPARE0 - Spare 0 Register (Not2Release)Not2Release
- ***************************************************************************/
-/* SWITCH_CORE :: OTP_CTL_REG_SPARE0 :: OTP_CTL_REG_SPARE0 [31:00] */
-#define BCHP_SWITCH_CORE_OTP_CTL_REG_SPARE0_OTP_CTL_REG_SPARE0_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_OTP_CTL_REG_SPARE0_OTP_CTL_REG_SPARE0_SHIFT 0
-#define BCHP_SWITCH_CORE_OTP_CTL_REG_SPARE0_OTP_CTL_REG_SPARE0_DEFAULT 0x00000000
-
-/***************************************************************************
- *OTP_CTL_REG_SPARE1 - Spare 1 Register (Not2Release)Not2Release
- ***************************************************************************/
-/* SWITCH_CORE :: OTP_CTL_REG_SPARE1 :: OTP_CTL_REG_SPARE1 [31:00] */
-#define BCHP_SWITCH_CORE_OTP_CTL_REG_SPARE1_OTP_CTL_REG_SPARE1_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_OTP_CTL_REG_SPARE1_OTP_CTL_REG_SPARE1_SHIFT 0
-#define BCHP_SWITCH_CORE_OTP_CTL_REG_SPARE1_OTP_CTL_REG_SPARE1_DEFAULT 0x00000000
-
-/***************************************************************************
- *SPIDIO0 - SPI Data I/O Registers 0
- ***************************************************************************/
-/* SWITCH_CORE :: SPIDIO0 :: reserved_for_padding0 [31:08] */
-#define BCHP_SWITCH_CORE_SPIDIO0_reserved_for_padding0_MASK 0xffffff00
-#define BCHP_SWITCH_CORE_SPIDIO0_reserved_for_padding0_SHIFT 8
-
-/* SWITCH_CORE :: SPIDIO0 :: SWITCH_RESV [07:00] */
-#define BCHP_SWITCH_CORE_SPIDIO0_SWITCH_RESV_MASK 0x000000ff
-#define BCHP_SWITCH_CORE_SPIDIO0_SWITCH_RESV_SHIFT 0
-#define BCHP_SWITCH_CORE_SPIDIO0_SWITCH_RESV_DEFAULT 0x00000000
-
-/***************************************************************************
- *SPIDIO1 - SPI Data I/O Registers 1
- ***************************************************************************/
-/* SWITCH_CORE :: SPIDIO1 :: reserved_for_padding0 [31:08] */
-#define BCHP_SWITCH_CORE_SPIDIO1_reserved_for_padding0_MASK 0xffffff00
-#define BCHP_SWITCH_CORE_SPIDIO1_reserved_for_padding0_SHIFT 8
-
-/* SWITCH_CORE :: SPIDIO1 :: SWITCH_RESV [07:00] */
-#define BCHP_SWITCH_CORE_SPIDIO1_SWITCH_RESV_MASK 0x000000ff
-#define BCHP_SWITCH_CORE_SPIDIO1_SWITCH_RESV_SHIFT 0
-#define BCHP_SWITCH_CORE_SPIDIO1_SWITCH_RESV_DEFAULT 0x00000000
-
-/***************************************************************************
- *SPIDIO2 - SPI Data I/O Registers 2
- ***************************************************************************/
-/* SWITCH_CORE :: SPIDIO2 :: reserved_for_padding0 [31:08] */
-#define BCHP_SWITCH_CORE_SPIDIO2_reserved_for_padding0_MASK 0xffffff00
-#define BCHP_SWITCH_CORE_SPIDIO2_reserved_for_padding0_SHIFT 8
-
-/* SWITCH_CORE :: SPIDIO2 :: SWITCH_RESV [07:00] */
-#define BCHP_SWITCH_CORE_SPIDIO2_SWITCH_RESV_MASK 0x000000ff
-#define BCHP_SWITCH_CORE_SPIDIO2_SWITCH_RESV_SHIFT 0
-#define BCHP_SWITCH_CORE_SPIDIO2_SWITCH_RESV_DEFAULT 0x00000000
-
-/***************************************************************************
- *SPIDIO3 - SPI Data I/O Registers 3
- ***************************************************************************/
-/* SWITCH_CORE :: SPIDIO3 :: reserved_for_padding0 [31:08] */
-#define BCHP_SWITCH_CORE_SPIDIO3_reserved_for_padding0_MASK 0xffffff00
-#define BCHP_SWITCH_CORE_SPIDIO3_reserved_for_padding0_SHIFT 8
-
-/* SWITCH_CORE :: SPIDIO3 :: SWITCH_RESV [07:00] */
-#define BCHP_SWITCH_CORE_SPIDIO3_SWITCH_RESV_MASK 0x000000ff
-#define BCHP_SWITCH_CORE_SPIDIO3_SWITCH_RESV_SHIFT 0
-#define BCHP_SWITCH_CORE_SPIDIO3_SWITCH_RESV_DEFAULT 0x00000000
-
-/***************************************************************************
- *SPIDIO4 - SPI Data I/O Registers 4
- ***************************************************************************/
-/* SWITCH_CORE :: SPIDIO4 :: reserved_for_padding0 [31:08] */
-#define BCHP_SWITCH_CORE_SPIDIO4_reserved_for_padding0_MASK 0xffffff00
-#define BCHP_SWITCH_CORE_SPIDIO4_reserved_for_padding0_SHIFT 8
-
-/* SWITCH_CORE :: SPIDIO4 :: SWITCH_RESV [07:00] */
-#define BCHP_SWITCH_CORE_SPIDIO4_SWITCH_RESV_MASK 0x000000ff
-#define BCHP_SWITCH_CORE_SPIDIO4_SWITCH_RESV_SHIFT 0
-#define BCHP_SWITCH_CORE_SPIDIO4_SWITCH_RESV_DEFAULT 0x00000000
-
-/***************************************************************************
- *SPIDIO5 - SPI Data I/O Registers 5
- ***************************************************************************/
-/* SWITCH_CORE :: SPIDIO5 :: reserved_for_padding0 [31:08] */
-#define BCHP_SWITCH_CORE_SPIDIO5_reserved_for_padding0_MASK 0xffffff00
-#define BCHP_SWITCH_CORE_SPIDIO5_reserved_for_padding0_SHIFT 8
-
-/* SWITCH_CORE :: SPIDIO5 :: SWITCH_RESV [07:00] */
-#define BCHP_SWITCH_CORE_SPIDIO5_SWITCH_RESV_MASK 0x000000ff
-#define BCHP_SWITCH_CORE_SPIDIO5_SWITCH_RESV_SHIFT 0
-#define BCHP_SWITCH_CORE_SPIDIO5_SWITCH_RESV_DEFAULT 0x00000000
-
-/***************************************************************************
- *SPIDIO6 - SPI Data I/O Registers 6
- ***************************************************************************/
-/* SWITCH_CORE :: SPIDIO6 :: reserved_for_padding0 [31:08] */
-#define BCHP_SWITCH_CORE_SPIDIO6_reserved_for_padding0_MASK 0xffffff00
-#define BCHP_SWITCH_CORE_SPIDIO6_reserved_for_padding0_SHIFT 8
-
-/* SWITCH_CORE :: SPIDIO6 :: SWITCH_RESV [07:00] */
-#define BCHP_SWITCH_CORE_SPIDIO6_SWITCH_RESV_MASK 0x000000ff
-#define BCHP_SWITCH_CORE_SPIDIO6_SWITCH_RESV_SHIFT 0
-#define BCHP_SWITCH_CORE_SPIDIO6_SWITCH_RESV_DEFAULT 0x00000000
-
-/***************************************************************************
- *SPIDIO7 - SPI Data I/O Registers 7
- ***************************************************************************/
-/* SWITCH_CORE :: SPIDIO7 :: reserved_for_padding0 [31:08] */
-#define BCHP_SWITCH_CORE_SPIDIO7_reserved_for_padding0_MASK 0xffffff00
-#define BCHP_SWITCH_CORE_SPIDIO7_reserved_for_padding0_SHIFT 8
-
-/* SWITCH_CORE :: SPIDIO7 :: SWITCH_RESV [07:00] */
-#define BCHP_SWITCH_CORE_SPIDIO7_SWITCH_RESV_MASK 0x000000ff
-#define BCHP_SWITCH_CORE_SPIDIO7_SWITCH_RESV_SHIFT 0
-#define BCHP_SWITCH_CORE_SPIDIO7_SWITCH_RESV_DEFAULT 0x00000000
-
-/***************************************************************************
- *CLKSET - Clock Period Setting Registers
- ***************************************************************************/
-/* SWITCH_CORE :: CLKSET :: SWITCH_RESV [31:00] */
-#define BCHP_SWITCH_CORE_CLKSET_SWITCH_RESV_MASK 0xffffffff
-#define BCHP_SWITCH_CORE_CLKSET_SWITCH_RESV_SHIFT 0
-#define BCHP_SWITCH_CORE_CLKSET_SWITCH_RESV_DEFAULT 0x00000000
-
-/***************************************************************************
- *SPISTS - SPI Status Registers
- ***************************************************************************/
-/* SWITCH_CORE :: SPISTS :: reserved_for_padding0 [31:08] */
-#define BCHP_SWITCH_CORE_SPISTS_reserved_for_padding0_MASK 0xffffff00
-#define BCHP_SWITCH_CORE_SPISTS_reserved_for_padding0_SHIFT 8
-
-/* SWITCH_CORE :: SPISTS :: SWITCH_RESV [07:00] */
-#define BCHP_SWITCH_CORE_SPISTS_SWITCH_RESV_MASK 0x000000ff
-#define BCHP_SWITCH_CORE_SPISTS_SWITCH_RESV_SHIFT 0
-#define BCHP_SWITCH_CORE_SPISTS_SWITCH_RESV_DEFAULT 0x00000000
-
-/***************************************************************************
- *PAGEREG - PAGE Control Registers
- ***************************************************************************/
-/* SWITCH_CORE :: PAGEREG :: reserved_for_padding0 [31:08] */
-#define BCHP_SWITCH_CORE_PAGEREG_reserved_for_padding0_MASK 0xffffff00
-#define BCHP_SWITCH_CORE_PAGEREG_reserved_for_padding0_SHIFT 8
-
-/* SWITCH_CORE :: PAGEREG :: SWITCH_RESV [07:00] */
-#define BCHP_SWITCH_CORE_PAGEREG_SWITCH_RESV_MASK 0x000000ff
-#define BCHP_SWITCH_CORE_PAGEREG_SWITCH_RESV_SHIFT 0
-#define BCHP_SWITCH_CORE_PAGEREG_SWITCH_RESV_DEFAULT 0x00000000
-
-#endif /* #ifndef BCHP_SWITCH_CORE_H__ */
-
-/* End of File */
diff --git a/include/linux/brcmstb/7145a0/bchp_switch_fcb.h b/include/linux/brcmstb/7145a0/bchp_switch_fcb.h
deleted file mode 100644
index 51e9e9e..0000000
--- a/include/linux/brcmstb/7145a0/bchp_switch_fcb.h
+++ /dev/null
@@ -1,404 +0,0 @@
-/***************************************************************************
- * Copyright (c) 1999-2013, Broadcom Corporation
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
- *
- * Module Description:
- * DO NOT EDIT THIS FILE DIRECTLY
- *
- * This module was generated magically with RDB from a source description
- * file. You must edit the source file for changes to be made to this file.
- *
- *
- * Date: Generated on Wed May 8 03:09:25 2013
- * MD5 Checksum d41d8cd98f00b204e9800998ecf8427e
- *
- * Compiled with: RDB Utility combo_header.pl
- * RDB Parser 3.0
- * unknown unknown
- * Perl Interpreter 5.008008
- * Operating System linux
- *
- * Revision History:
- *
- * $brcm_Log: $
- *
- ***************************************************************************/
-
-#ifndef BCHP_SWITCH_FCB_H__
-#define BCHP_SWITCH_FCB_H__
-
-/***************************************************************************
- *SWITCH_FCB
- ***************************************************************************/
-#define BCHP_SWITCH_FCB_FCB_CONTROL 0x04e40400 /* Tx Pause Enable Register */
-#define BCHP_SWITCH_FCB_P8_FAILOVER_RELEASE_CONTROL 0x04e40404 /* P8 Failover Release Control Register */
-#define BCHP_SWITCH_FCB_P8_RELEASE_TIMEOUT 0x04e40408 /* P8 Failover Release Control Register */
-#define BCHP_SWITCH_FCB_P5_FAILOVER_RELEASE_CONTROL 0x04e4040c /* P5 Failover Release Control Register */
-#define BCHP_SWITCH_FCB_P5_RELEASE_TIMEOUT 0x04e40410 /* P5 Release Timeout Register */
-#define BCHP_SWITCH_FCB_P5_RELEASE_DELAY_TIMEOUT 0x04e40414 /* P5 Release Delay Timeout Register */
-#define BCHP_SWITCH_FCB_P4_FAILOVER_RELEASE_CONTROL 0x04e40418 /* P4 Failover Release Control Register */
-#define BCHP_SWITCH_FCB_P4_RELEASE_TIMEOUT 0x04e4041c /* P4 Release Timeout Register */
-#define BCHP_SWITCH_FCB_P4_RELEASE_DELAY_TIMEOUT 0x04e40420 /* P4 Release Delay Timeout Register */
-#define BCHP_SWITCH_FCB_LAN_FAILOVER_RELEASE_CONTROL 0x04e40424 /* LAN Failover Release Control Register */
-#define BCHP_SWITCH_FCB_LAN_RELEASE_TIMEOUT 0x04e40428 /* LAN Release Timeout Register */
-#define BCHP_SWITCH_FCB_LAN_RELEASE_DELAY_TIMEOUT 0x04e4042c /* LAN Release Delay Timeout Register */
-
-/***************************************************************************
- *FCB_CONTROL - Tx Pause Enable Register
- ***************************************************************************/
-/* SWITCH_FCB :: FCB_CONTROL :: reserved0 [31:10] */
-#define BCHP_SWITCH_FCB_FCB_CONTROL_reserved0_MASK 0xfffffc00
-#define BCHP_SWITCH_FCB_FCB_CONTROL_reserved0_SHIFT 10
-
-/* SWITCH_FCB :: FCB_CONTROL :: fcb_en [09:09] */
-#define BCHP_SWITCH_FCB_FCB_CONTROL_fcb_en_MASK 0x00000200
-#define BCHP_SWITCH_FCB_FCB_CONTROL_fcb_en_SHIFT 9
-#define BCHP_SWITCH_FCB_FCB_CONTROL_fcb_en_DEFAULT 0x00000000
-
-/* SWITCH_FCB :: FCB_CONTROL :: failover_dis [08:00] */
-#define BCHP_SWITCH_FCB_FCB_CONTROL_failover_dis_MASK 0x000001ff
-#define BCHP_SWITCH_FCB_FCB_CONTROL_failover_dis_SHIFT 0
-#define BCHP_SWITCH_FCB_FCB_CONTROL_failover_dis_DEFAULT 0x00000000
-
-/***************************************************************************
- *P8_FAILOVER_RELEASE_CONTROL - P8 Failover Release Control Register
- ***************************************************************************/
-/* SWITCH_FCB :: P8_FAILOVER_RELEASE_CONTROL :: reserved0 [31:24] */
-#define BCHP_SWITCH_FCB_P8_FAILOVER_RELEASE_CONTROL_reserved0_MASK 0xff000000
-#define BCHP_SWITCH_FCB_P8_FAILOVER_RELEASE_CONTROL_reserved0_SHIFT 24
-
-/* SWITCH_FCB :: P8_FAILOVER_RELEASE_CONTROL :: queue_release_mask [23:16] */
-#define BCHP_SWITCH_FCB_P8_FAILOVER_RELEASE_CONTROL_queue_release_mask_MASK 0x00ff0000
-#define BCHP_SWITCH_FCB_P8_FAILOVER_RELEASE_CONTROL_queue_release_mask_SHIFT 16
-#define BCHP_SWITCH_FCB_P8_FAILOVER_RELEASE_CONTROL_queue_release_mask_DEFAULT 0x00000000
-
-/* SWITCH_FCB :: P8_FAILOVER_RELEASE_CONTROL :: Q7_release_state [15:14] */
-#define BCHP_SWITCH_FCB_P8_FAILOVER_RELEASE_CONTROL_Q7_release_state_MASK 0x0000c000
-#define BCHP_SWITCH_FCB_P8_FAILOVER_RELEASE_CONTROL_Q7_release_state_SHIFT 14
-#define BCHP_SWITCH_FCB_P8_FAILOVER_RELEASE_CONTROL_Q7_release_state_DEFAULT 0x00000001
-
-/* SWITCH_FCB :: P8_FAILOVER_RELEASE_CONTROL :: Q6_release_state [13:12] */
-#define BCHP_SWITCH_FCB_P8_FAILOVER_RELEASE_CONTROL_Q6_release_state_MASK 0x00003000
-#define BCHP_SWITCH_FCB_P8_FAILOVER_RELEASE_CONTROL_Q6_release_state_SHIFT 12
-#define BCHP_SWITCH_FCB_P8_FAILOVER_RELEASE_CONTROL_Q6_release_state_DEFAULT 0x00000001
-
-/* SWITCH_FCB :: P8_FAILOVER_RELEASE_CONTROL :: Q5_release_state [11:10] */
-#define BCHP_SWITCH_FCB_P8_FAILOVER_RELEASE_CONTROL_Q5_release_state_MASK 0x00000c00
-#define BCHP_SWITCH_FCB_P8_FAILOVER_RELEASE_CONTROL_Q5_release_state_SHIFT 10
-#define BCHP_SWITCH_FCB_P8_FAILOVER_RELEASE_CONTROL_Q5_release_state_DEFAULT 0x00000001
-
-/* SWITCH_FCB :: P8_FAILOVER_RELEASE_CONTROL :: Q4_release_state [09:08] */
-#define BCHP_SWITCH_FCB_P8_FAILOVER_RELEASE_CONTROL_Q4_release_state_MASK 0x00000300
-#define BCHP_SWITCH_FCB_P8_FAILOVER_RELEASE_CONTROL_Q4_release_state_SHIFT 8
-#define BCHP_SWITCH_FCB_P8_FAILOVER_RELEASE_CONTROL_Q4_release_state_DEFAULT 0x00000001
-
-/* SWITCH_FCB :: P8_FAILOVER_RELEASE_CONTROL :: Q3_release_state [07:06] */
-#define BCHP_SWITCH_FCB_P8_FAILOVER_RELEASE_CONTROL_Q3_release_state_MASK 0x000000c0
-#define BCHP_SWITCH_FCB_P8_FAILOVER_RELEASE_CONTROL_Q3_release_state_SHIFT 6
-#define BCHP_SWITCH_FCB_P8_FAILOVER_RELEASE_CONTROL_Q3_release_state_DEFAULT 0x00000001
-
-/* SWITCH_FCB :: P8_FAILOVER_RELEASE_CONTROL :: Q2_release_state [05:04] */
-#define BCHP_SWITCH_FCB_P8_FAILOVER_RELEASE_CONTROL_Q2_release_state_MASK 0x00000030
-#define BCHP_SWITCH_FCB_P8_FAILOVER_RELEASE_CONTROL_Q2_release_state_SHIFT 4
-#define BCHP_SWITCH_FCB_P8_FAILOVER_RELEASE_CONTROL_Q2_release_state_DEFAULT 0x00000001
-
-/* SWITCH_FCB :: P8_FAILOVER_RELEASE_CONTROL :: Q1_release_state [03:02] */
-#define BCHP_SWITCH_FCB_P8_FAILOVER_RELEASE_CONTROL_Q1_release_state_MASK 0x0000000c
-#define BCHP_SWITCH_FCB_P8_FAILOVER_RELEASE_CONTROL_Q1_release_state_SHIFT 2
-#define BCHP_SWITCH_FCB_P8_FAILOVER_RELEASE_CONTROL_Q1_release_state_DEFAULT 0x00000001
-
-/* SWITCH_FCB :: P8_FAILOVER_RELEASE_CONTROL :: Q0_release_state [01:00] */
-#define BCHP_SWITCH_FCB_P8_FAILOVER_RELEASE_CONTROL_Q0_release_state_MASK 0x00000003
-#define BCHP_SWITCH_FCB_P8_FAILOVER_RELEASE_CONTROL_Q0_release_state_SHIFT 0
-#define BCHP_SWITCH_FCB_P8_FAILOVER_RELEASE_CONTROL_Q0_release_state_DEFAULT 0x00000001
-
-/***************************************************************************
- *P8_RELEASE_TIMEOUT - P8 Failover Release Control Register
- ***************************************************************************/
-/* SWITCH_FCB :: P8_RELEASE_TIMEOUT :: reserved0 [31:17] */
-#define BCHP_SWITCH_FCB_P8_RELEASE_TIMEOUT_reserved0_MASK 0xfffe0000
-#define BCHP_SWITCH_FCB_P8_RELEASE_TIMEOUT_reserved0_SHIFT 17
-
-/* SWITCH_FCB :: P8_RELEASE_TIMEOUT :: release_timer_en [16:16] */
-#define BCHP_SWITCH_FCB_P8_RELEASE_TIMEOUT_release_timer_en_MASK 0x00010000
-#define BCHP_SWITCH_FCB_P8_RELEASE_TIMEOUT_release_timer_en_SHIFT 16
-#define BCHP_SWITCH_FCB_P8_RELEASE_TIMEOUT_release_timer_en_DEFAULT 0x00000000
-
-/* SWITCH_FCB :: P8_RELEASE_TIMEOUT :: release_timeout [15:00] */
-#define BCHP_SWITCH_FCB_P8_RELEASE_TIMEOUT_release_timeout_MASK 0x0000ffff
-#define BCHP_SWITCH_FCB_P8_RELEASE_TIMEOUT_release_timeout_SHIFT 0
-#define BCHP_SWITCH_FCB_P8_RELEASE_TIMEOUT_release_timeout_DEFAULT 0x000001ff
-
-/***************************************************************************
- *P5_FAILOVER_RELEASE_CONTROL - P5 Failover Release Control Register
- ***************************************************************************/
-/* SWITCH_FCB :: P5_FAILOVER_RELEASE_CONTROL :: reserved0 [31:24] */
-#define BCHP_SWITCH_FCB_P5_FAILOVER_RELEASE_CONTROL_reserved0_MASK 0xff000000
-#define BCHP_SWITCH_FCB_P5_FAILOVER_RELEASE_CONTROL_reserved0_SHIFT 24
-
-/* SWITCH_FCB :: P5_FAILOVER_RELEASE_CONTROL :: queue_release_mask [23:16] */
-#define BCHP_SWITCH_FCB_P5_FAILOVER_RELEASE_CONTROL_queue_release_mask_MASK 0x00ff0000
-#define BCHP_SWITCH_FCB_P5_FAILOVER_RELEASE_CONTROL_queue_release_mask_SHIFT 16
-#define BCHP_SWITCH_FCB_P5_FAILOVER_RELEASE_CONTROL_queue_release_mask_DEFAULT 0x00000000
-
-/* SWITCH_FCB :: P5_FAILOVER_RELEASE_CONTROL :: Q7_release_state [15:14] */
-#define BCHP_SWITCH_FCB_P5_FAILOVER_RELEASE_CONTROL_Q7_release_state_MASK 0x0000c000
-#define BCHP_SWITCH_FCB_P5_FAILOVER_RELEASE_CONTROL_Q7_release_state_SHIFT 14
-#define BCHP_SWITCH_FCB_P5_FAILOVER_RELEASE_CONTROL_Q7_release_state_DEFAULT 0x00000001
-
-/* SWITCH_FCB :: P5_FAILOVER_RELEASE_CONTROL :: Q6_release_state [13:12] */
-#define BCHP_SWITCH_FCB_P5_FAILOVER_RELEASE_CONTROL_Q6_release_state_MASK 0x00003000
-#define BCHP_SWITCH_FCB_P5_FAILOVER_RELEASE_CONTROL_Q6_release_state_SHIFT 12
-#define BCHP_SWITCH_FCB_P5_FAILOVER_RELEASE_CONTROL_Q6_release_state_DEFAULT 0x00000001
-
-/* SWITCH_FCB :: P5_FAILOVER_RELEASE_CONTROL :: Q5_release_state [11:10] */
-#define BCHP_SWITCH_FCB_P5_FAILOVER_RELEASE_CONTROL_Q5_release_state_MASK 0x00000c00
-#define BCHP_SWITCH_FCB_P5_FAILOVER_RELEASE_CONTROL_Q5_release_state_SHIFT 10
-#define BCHP_SWITCH_FCB_P5_FAILOVER_RELEASE_CONTROL_Q5_release_state_DEFAULT 0x00000001
-
-/* SWITCH_FCB :: P5_FAILOVER_RELEASE_CONTROL :: Q4_release_state [09:08] */
-#define BCHP_SWITCH_FCB_P5_FAILOVER_RELEASE_CONTROL_Q4_release_state_MASK 0x00000300
-#define BCHP_SWITCH_FCB_P5_FAILOVER_RELEASE_CONTROL_Q4_release_state_SHIFT 8
-#define BCHP_SWITCH_FCB_P5_FAILOVER_RELEASE_CONTROL_Q4_release_state_DEFAULT 0x00000001
-
-/* SWITCH_FCB :: P5_FAILOVER_RELEASE_CONTROL :: Q3_release_state [07:06] */
-#define BCHP_SWITCH_FCB_P5_FAILOVER_RELEASE_CONTROL_Q3_release_state_MASK 0x000000c0
-#define BCHP_SWITCH_FCB_P5_FAILOVER_RELEASE_CONTROL_Q3_release_state_SHIFT 6
-#define BCHP_SWITCH_FCB_P5_FAILOVER_RELEASE_CONTROL_Q3_release_state_DEFAULT 0x00000001
-
-/* SWITCH_FCB :: P5_FAILOVER_RELEASE_CONTROL :: Q2_release_state [05:04] */
-#define BCHP_SWITCH_FCB_P5_FAILOVER_RELEASE_CONTROL_Q2_release_state_MASK 0x00000030
-#define BCHP_SWITCH_FCB_P5_FAILOVER_RELEASE_CONTROL_Q2_release_state_SHIFT 4
-#define BCHP_SWITCH_FCB_P5_FAILOVER_RELEASE_CONTROL_Q2_release_state_DEFAULT 0x00000001
-
-/* SWITCH_FCB :: P5_FAILOVER_RELEASE_CONTROL :: Q1_release_state [03:02] */
-#define BCHP_SWITCH_FCB_P5_FAILOVER_RELEASE_CONTROL_Q1_release_state_MASK 0x0000000c
-#define BCHP_SWITCH_FCB_P5_FAILOVER_RELEASE_CONTROL_Q1_release_state_SHIFT 2
-#define BCHP_SWITCH_FCB_P5_FAILOVER_RELEASE_CONTROL_Q1_release_state_DEFAULT 0x00000001
-
-/* SWITCH_FCB :: P5_FAILOVER_RELEASE_CONTROL :: Q0_release_state [01:00] */
-#define BCHP_SWITCH_FCB_P5_FAILOVER_RELEASE_CONTROL_Q0_release_state_MASK 0x00000003
-#define BCHP_SWITCH_FCB_P5_FAILOVER_RELEASE_CONTROL_Q0_release_state_SHIFT 0
-#define BCHP_SWITCH_FCB_P5_FAILOVER_RELEASE_CONTROL_Q0_release_state_DEFAULT 0x00000001
-
-/***************************************************************************
- *P5_RELEASE_TIMEOUT - P5 Release Timeout Register
- ***************************************************************************/
-/* SWITCH_FCB :: P5_RELEASE_TIMEOUT :: reserved0 [31:17] */
-#define BCHP_SWITCH_FCB_P5_RELEASE_TIMEOUT_reserved0_MASK 0xfffe0000
-#define BCHP_SWITCH_FCB_P5_RELEASE_TIMEOUT_reserved0_SHIFT 17
-
-/* SWITCH_FCB :: P5_RELEASE_TIMEOUT :: release_timer_en [16:16] */
-#define BCHP_SWITCH_FCB_P5_RELEASE_TIMEOUT_release_timer_en_MASK 0x00010000
-#define BCHP_SWITCH_FCB_P5_RELEASE_TIMEOUT_release_timer_en_SHIFT 16
-#define BCHP_SWITCH_FCB_P5_RELEASE_TIMEOUT_release_timer_en_DEFAULT 0x00000000
-
-/* SWITCH_FCB :: P5_RELEASE_TIMEOUT :: release_timeout [15:00] */
-#define BCHP_SWITCH_FCB_P5_RELEASE_TIMEOUT_release_timeout_MASK 0x0000ffff
-#define BCHP_SWITCH_FCB_P5_RELEASE_TIMEOUT_release_timeout_SHIFT 0
-#define BCHP_SWITCH_FCB_P5_RELEASE_TIMEOUT_release_timeout_DEFAULT 0x000001ff
-
-/***************************************************************************
- *P5_RELEASE_DELAY_TIMEOUT - P5 Release Delay Timeout Register
- ***************************************************************************/
-/* SWITCH_FCB :: P5_RELEASE_DELAY_TIMEOUT :: reserved0 [31:09] */
-#define BCHP_SWITCH_FCB_P5_RELEASE_DELAY_TIMEOUT_reserved0_MASK 0xfffffe00
-#define BCHP_SWITCH_FCB_P5_RELEASE_DELAY_TIMEOUT_reserved0_SHIFT 9
-
-/* SWITCH_FCB :: P5_RELEASE_DELAY_TIMEOUT :: release_timer_en [08:08] */
-#define BCHP_SWITCH_FCB_P5_RELEASE_DELAY_TIMEOUT_release_timer_en_MASK 0x00000100
-#define BCHP_SWITCH_FCB_P5_RELEASE_DELAY_TIMEOUT_release_timer_en_SHIFT 8
-#define BCHP_SWITCH_FCB_P5_RELEASE_DELAY_TIMEOUT_release_timer_en_DEFAULT 0x00000000
-
-/* SWITCH_FCB :: P5_RELEASE_DELAY_TIMEOUT :: release_timeout [07:00] */
-#define BCHP_SWITCH_FCB_P5_RELEASE_DELAY_TIMEOUT_release_timeout_MASK 0x000000ff
-#define BCHP_SWITCH_FCB_P5_RELEASE_DELAY_TIMEOUT_release_timeout_SHIFT 0
-#define BCHP_SWITCH_FCB_P5_RELEASE_DELAY_TIMEOUT_release_timeout_DEFAULT 0x0000000f
-
-/***************************************************************************
- *P4_FAILOVER_RELEASE_CONTROL - P4 Failover Release Control Register
- ***************************************************************************/
-/* SWITCH_FCB :: P4_FAILOVER_RELEASE_CONTROL :: reserved0 [31:24] */
-#define BCHP_SWITCH_FCB_P4_FAILOVER_RELEASE_CONTROL_reserved0_MASK 0xff000000
-#define BCHP_SWITCH_FCB_P4_FAILOVER_RELEASE_CONTROL_reserved0_SHIFT 24
-
-/* SWITCH_FCB :: P4_FAILOVER_RELEASE_CONTROL :: queue_release_mask [23:16] */
-#define BCHP_SWITCH_FCB_P4_FAILOVER_RELEASE_CONTROL_queue_release_mask_MASK 0x00ff0000
-#define BCHP_SWITCH_FCB_P4_FAILOVER_RELEASE_CONTROL_queue_release_mask_SHIFT 16
-#define BCHP_SWITCH_FCB_P4_FAILOVER_RELEASE_CONTROL_queue_release_mask_DEFAULT 0x00000000
-
-/* SWITCH_FCB :: P4_FAILOVER_RELEASE_CONTROL :: Q7_release_state [15:14] */
-#define BCHP_SWITCH_FCB_P4_FAILOVER_RELEASE_CONTROL_Q7_release_state_MASK 0x0000c000
-#define BCHP_SWITCH_FCB_P4_FAILOVER_RELEASE_CONTROL_Q7_release_state_SHIFT 14
-#define BCHP_SWITCH_FCB_P4_FAILOVER_RELEASE_CONTROL_Q7_release_state_DEFAULT 0x00000001
-
-/* SWITCH_FCB :: P4_FAILOVER_RELEASE_CONTROL :: Q6_release_state [13:12] */
-#define BCHP_SWITCH_FCB_P4_FAILOVER_RELEASE_CONTROL_Q6_release_state_MASK 0x00003000
-#define BCHP_SWITCH_FCB_P4_FAILOVER_RELEASE_CONTROL_Q6_release_state_SHIFT 12
-#define BCHP_SWITCH_FCB_P4_FAILOVER_RELEASE_CONTROL_Q6_release_state_DEFAULT 0x00000001
-
-/* SWITCH_FCB :: P4_FAILOVER_RELEASE_CONTROL :: Q5_release_state [11:10] */
-#define BCHP_SWITCH_FCB_P4_FAILOVER_RELEASE_CONTROL_Q5_release_state_MASK 0x00000c00
-#define BCHP_SWITCH_FCB_P4_FAILOVER_RELEASE_CONTROL_Q5_release_state_SHIFT 10
-#define BCHP_SWITCH_FCB_P4_FAILOVER_RELEASE_CONTROL_Q5_release_state_DEFAULT 0x00000001
-
-/* SWITCH_FCB :: P4_FAILOVER_RELEASE_CONTROL :: Q4_release_state [09:08] */
-#define BCHP_SWITCH_FCB_P4_FAILOVER_RELEASE_CONTROL_Q4_release_state_MASK 0x00000300
-#define BCHP_SWITCH_FCB_P4_FAILOVER_RELEASE_CONTROL_Q4_release_state_SHIFT 8
-#define BCHP_SWITCH_FCB_P4_FAILOVER_RELEASE_CONTROL_Q4_release_state_DEFAULT 0x00000001
-
-/* SWITCH_FCB :: P4_FAILOVER_RELEASE_CONTROL :: Q3_release_state [07:06] */
-#define BCHP_SWITCH_FCB_P4_FAILOVER_RELEASE_CONTROL_Q3_release_state_MASK 0x000000c0
-#define BCHP_SWITCH_FCB_P4_FAILOVER_RELEASE_CONTROL_Q3_release_state_SHIFT 6
-#define BCHP_SWITCH_FCB_P4_FAILOVER_RELEASE_CONTROL_Q3_release_state_DEFAULT 0x00000001
-
-/* SWITCH_FCB :: P4_FAILOVER_RELEASE_CONTROL :: Q2_release_state [05:04] */
-#define BCHP_SWITCH_FCB_P4_FAILOVER_RELEASE_CONTROL_Q2_release_state_MASK 0x00000030
-#define BCHP_SWITCH_FCB_P4_FAILOVER_RELEASE_CONTROL_Q2_release_state_SHIFT 4
-#define BCHP_SWITCH_FCB_P4_FAILOVER_RELEASE_CONTROL_Q2_release_state_DEFAULT 0x00000001
-
-/* SWITCH_FCB :: P4_FAILOVER_RELEASE_CONTROL :: Q1_release_state [03:02] */
-#define BCHP_SWITCH_FCB_P4_FAILOVER_RELEASE_CONTROL_Q1_release_state_MASK 0x0000000c
-#define BCHP_SWITCH_FCB_P4_FAILOVER_RELEASE_CONTROL_Q1_release_state_SHIFT 2
-#define BCHP_SWITCH_FCB_P4_FAILOVER_RELEASE_CONTROL_Q1_release_state_DEFAULT 0x00000001
-
-/* SWITCH_FCB :: P4_FAILOVER_RELEASE_CONTROL :: Q0_release_state [01:00] */
-#define BCHP_SWITCH_FCB_P4_FAILOVER_RELEASE_CONTROL_Q0_release_state_MASK 0x00000003
-#define BCHP_SWITCH_FCB_P4_FAILOVER_RELEASE_CONTROL_Q0_release_state_SHIFT 0
-#define BCHP_SWITCH_FCB_P4_FAILOVER_RELEASE_CONTROL_Q0_release_state_DEFAULT 0x00000001
-
-/***************************************************************************
- *P4_RELEASE_TIMEOUT - P4 Release Timeout Register
- ***************************************************************************/
-/* SWITCH_FCB :: P4_RELEASE_TIMEOUT :: reserved0 [31:17] */
-#define BCHP_SWITCH_FCB_P4_RELEASE_TIMEOUT_reserved0_MASK 0xfffe0000
-#define BCHP_SWITCH_FCB_P4_RELEASE_TIMEOUT_reserved0_SHIFT 17
-
-/* SWITCH_FCB :: P4_RELEASE_TIMEOUT :: release_timer_en [16:16] */
-#define BCHP_SWITCH_FCB_P4_RELEASE_TIMEOUT_release_timer_en_MASK 0x00010000
-#define BCHP_SWITCH_FCB_P4_RELEASE_TIMEOUT_release_timer_en_SHIFT 16
-#define BCHP_SWITCH_FCB_P4_RELEASE_TIMEOUT_release_timer_en_DEFAULT 0x00000000
-
-/* SWITCH_FCB :: P4_RELEASE_TIMEOUT :: release_timeout [15:00] */
-#define BCHP_SWITCH_FCB_P4_RELEASE_TIMEOUT_release_timeout_MASK 0x0000ffff
-#define BCHP_SWITCH_FCB_P4_RELEASE_TIMEOUT_release_timeout_SHIFT 0
-#define BCHP_SWITCH_FCB_P4_RELEASE_TIMEOUT_release_timeout_DEFAULT 0x000001ff
-
-/***************************************************************************
- *P4_RELEASE_DELAY_TIMEOUT - P4 Release Delay Timeout Register
- ***************************************************************************/
-/* SWITCH_FCB :: P4_RELEASE_DELAY_TIMEOUT :: reserved0 [31:09] */
-#define BCHP_SWITCH_FCB_P4_RELEASE_DELAY_TIMEOUT_reserved0_MASK 0xfffffe00
-#define BCHP_SWITCH_FCB_P4_RELEASE_DELAY_TIMEOUT_reserved0_SHIFT 9
-
-/* SWITCH_FCB :: P4_RELEASE_DELAY_TIMEOUT :: release_timer_en [08:08] */
-#define BCHP_SWITCH_FCB_P4_RELEASE_DELAY_TIMEOUT_release_timer_en_MASK 0x00000100
-#define BCHP_SWITCH_FCB_P4_RELEASE_DELAY_TIMEOUT_release_timer_en_SHIFT 8
-#define BCHP_SWITCH_FCB_P4_RELEASE_DELAY_TIMEOUT_release_timer_en_DEFAULT 0x00000000
-
-/* SWITCH_FCB :: P4_RELEASE_DELAY_TIMEOUT :: release_timeout [07:00] */
-#define BCHP_SWITCH_FCB_P4_RELEASE_DELAY_TIMEOUT_release_timeout_MASK 0x000000ff
-#define BCHP_SWITCH_FCB_P4_RELEASE_DELAY_TIMEOUT_release_timeout_SHIFT 0
-#define BCHP_SWITCH_FCB_P4_RELEASE_DELAY_TIMEOUT_release_timeout_DEFAULT 0x0000000f
-
-/***************************************************************************
- *LAN_FAILOVER_RELEASE_CONTROL - LAN Failover Release Control Register
- ***************************************************************************/
-/* SWITCH_FCB :: LAN_FAILOVER_RELEASE_CONTROL :: reserved0 [31:24] */
-#define BCHP_SWITCH_FCB_LAN_FAILOVER_RELEASE_CONTROL_reserved0_MASK 0xff000000
-#define BCHP_SWITCH_FCB_LAN_FAILOVER_RELEASE_CONTROL_reserved0_SHIFT 24
-
-/* SWITCH_FCB :: LAN_FAILOVER_RELEASE_CONTROL :: queue_release_mask [23:16] */
-#define BCHP_SWITCH_FCB_LAN_FAILOVER_RELEASE_CONTROL_queue_release_mask_MASK 0x00ff0000
-#define BCHP_SWITCH_FCB_LAN_FAILOVER_RELEASE_CONTROL_queue_release_mask_SHIFT 16
-#define BCHP_SWITCH_FCB_LAN_FAILOVER_RELEASE_CONTROL_queue_release_mask_DEFAULT 0x00000000
-
-/* SWITCH_FCB :: LAN_FAILOVER_RELEASE_CONTROL :: Q7_release_state [15:14] */
-#define BCHP_SWITCH_FCB_LAN_FAILOVER_RELEASE_CONTROL_Q7_release_state_MASK 0x0000c000
-#define BCHP_SWITCH_FCB_LAN_FAILOVER_RELEASE_CONTROL_Q7_release_state_SHIFT 14
-#define BCHP_SWITCH_FCB_LAN_FAILOVER_RELEASE_CONTROL_Q7_release_state_DEFAULT 0x00000001
-
-/* SWITCH_FCB :: LAN_FAILOVER_RELEASE_CONTROL :: Q6_release_state [13:12] */
-#define BCHP_SWITCH_FCB_LAN_FAILOVER_RELEASE_CONTROL_Q6_release_state_MASK 0x00003000
-#define BCHP_SWITCH_FCB_LAN_FAILOVER_RELEASE_CONTROL_Q6_release_state_SHIFT 12
-#define BCHP_SWITCH_FCB_LAN_FAILOVER_RELEASE_CONTROL_Q6_release_state_DEFAULT 0x00000001
-
-/* SWITCH_FCB :: LAN_FAILOVER_RELEASE_CONTROL :: Q5_release_state [11:10] */
-#define BCHP_SWITCH_FCB_LAN_FAILOVER_RELEASE_CONTROL_Q5_release_state_MASK 0x00000c00
-#define BCHP_SWITCH_FCB_LAN_FAILOVER_RELEASE_CONTROL_Q5_release_state_SHIFT 10
-#define BCHP_SWITCH_FCB_LAN_FAILOVER_RELEASE_CONTROL_Q5_release_state_DEFAULT 0x00000001
-
-/* SWITCH_FCB :: LAN_FAILOVER_RELEASE_CONTROL :: Q4_release_state [09:08] */
-#define BCHP_SWITCH_FCB_LAN_FAILOVER_RELEASE_CONTROL_Q4_release_state_MASK 0x00000300
-#define BCHP_SWITCH_FCB_LAN_FAILOVER_RELEASE_CONTROL_Q4_release_state_SHIFT 8
-#define BCHP_SWITCH_FCB_LAN_FAILOVER_RELEASE_CONTROL_Q4_release_state_DEFAULT 0x00000001
-
-/* SWITCH_FCB :: LAN_FAILOVER_RELEASE_CONTROL :: Q3_release_state [07:06] */
-#define BCHP_SWITCH_FCB_LAN_FAILOVER_RELEASE_CONTROL_Q3_release_state_MASK 0x000000c0
-#define BCHP_SWITCH_FCB_LAN_FAILOVER_RELEASE_CONTROL_Q3_release_state_SHIFT 6
-#define BCHP_SWITCH_FCB_LAN_FAILOVER_RELEASE_CONTROL_Q3_release_state_DEFAULT 0x00000001
-
-/* SWITCH_FCB :: LAN_FAILOVER_RELEASE_CONTROL :: Q2_release_state [05:04] */
-#define BCHP_SWITCH_FCB_LAN_FAILOVER_RELEASE_CONTROL_Q2_release_state_MASK 0x00000030
-#define BCHP_SWITCH_FCB_LAN_FAILOVER_RELEASE_CONTROL_Q2_release_state_SHIFT 4
-#define BCHP_SWITCH_FCB_LAN_FAILOVER_RELEASE_CONTROL_Q2_release_state_DEFAULT 0x00000001
-
-/* SWITCH_FCB :: LAN_FAILOVER_RELEASE_CONTROL :: Q1_release_state [03:02] */
-#define BCHP_SWITCH_FCB_LAN_FAILOVER_RELEASE_CONTROL_Q1_release_state_MASK 0x0000000c
-#define BCHP_SWITCH_FCB_LAN_FAILOVER_RELEASE_CONTROL_Q1_release_state_SHIFT 2
-#define BCHP_SWITCH_FCB_LAN_FAILOVER_RELEASE_CONTROL_Q1_release_state_DEFAULT 0x00000001
-
-/* SWITCH_FCB :: LAN_FAILOVER_RELEASE_CONTROL :: Q0_release_state [01:00] */
-#define BCHP_SWITCH_FCB_LAN_FAILOVER_RELEASE_CONTROL_Q0_release_state_MASK 0x00000003
-#define BCHP_SWITCH_FCB_LAN_FAILOVER_RELEASE_CONTROL_Q0_release_state_SHIFT 0
-#define BCHP_SWITCH_FCB_LAN_FAILOVER_RELEASE_CONTROL_Q0_release_state_DEFAULT 0x00000001
-
-/***************************************************************************
- *LAN_RELEASE_TIMEOUT - LAN Release Timeout Register
- ***************************************************************************/
-/* SWITCH_FCB :: LAN_RELEASE_TIMEOUT :: reserved0 [31:17] */
-#define BCHP_SWITCH_FCB_LAN_RELEASE_TIMEOUT_reserved0_MASK 0xfffe0000
-#define BCHP_SWITCH_FCB_LAN_RELEASE_TIMEOUT_reserved0_SHIFT 17
-
-/* SWITCH_FCB :: LAN_RELEASE_TIMEOUT :: release_timer_en [16:16] */
-#define BCHP_SWITCH_FCB_LAN_RELEASE_TIMEOUT_release_timer_en_MASK 0x00010000
-#define BCHP_SWITCH_FCB_LAN_RELEASE_TIMEOUT_release_timer_en_SHIFT 16
-#define BCHP_SWITCH_FCB_LAN_RELEASE_TIMEOUT_release_timer_en_DEFAULT 0x00000000
-
-/* SWITCH_FCB :: LAN_RELEASE_TIMEOUT :: release_timeout [15:00] */
-#define BCHP_SWITCH_FCB_LAN_RELEASE_TIMEOUT_release_timeout_MASK 0x0000ffff
-#define BCHP_SWITCH_FCB_LAN_RELEASE_TIMEOUT_release_timeout_SHIFT 0
-#define BCHP_SWITCH_FCB_LAN_RELEASE_TIMEOUT_release_timeout_DEFAULT 0x000001ff
-
-/***************************************************************************
- *LAN_RELEASE_DELAY_TIMEOUT - LAN Release Delay Timeout Register
- ***************************************************************************/
-/* SWITCH_FCB :: LAN_RELEASE_DELAY_TIMEOUT :: reserved0 [31:09] */
-#define BCHP_SWITCH_FCB_LAN_RELEASE_DELAY_TIMEOUT_reserved0_MASK 0xfffffe00
-#define BCHP_SWITCH_FCB_LAN_RELEASE_DELAY_TIMEOUT_reserved0_SHIFT 9
-
-/* SWITCH_FCB :: LAN_RELEASE_DELAY_TIMEOUT :: release_timer_en [08:08] */
-#define BCHP_SWITCH_FCB_LAN_RELEASE_DELAY_TIMEOUT_release_timer_en_MASK 0x00000100
-#define BCHP_SWITCH_FCB_LAN_RELEASE_DELAY_TIMEOUT_release_timer_en_SHIFT 8
-#define BCHP_SWITCH_FCB_LAN_RELEASE_DELAY_TIMEOUT_release_timer_en_DEFAULT 0x00000000
-
-/* SWITCH_FCB :: LAN_RELEASE_DELAY_TIMEOUT :: release_timeout [07:00] */
-#define BCHP_SWITCH_FCB_LAN_RELEASE_DELAY_TIMEOUT_release_timeout_MASK 0x000000ff
-#define BCHP_SWITCH_FCB_LAN_RELEASE_DELAY_TIMEOUT_release_timeout_SHIFT 0
-#define BCHP_SWITCH_FCB_LAN_RELEASE_DELAY_TIMEOUT_release_timeout_DEFAULT 0x0000000f
-
-#endif /* #ifndef BCHP_SWITCH_FCB_H__ */
-
-/* End of File */
diff --git a/include/linux/brcmstb/7145a0/bchp_switch_indir_rw.h b/include/linux/brcmstb/7145a0/bchp_switch_indir_rw.h
deleted file mode 100644
index ef58b16..0000000
--- a/include/linux/brcmstb/7145a0/bchp_switch_indir_rw.h
+++ /dev/null
@@ -1,140 +0,0 @@
-/***************************************************************************
- * Copyright (c) 1999-2013, Broadcom Corporation
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
- *
- * Module Description:
- * DO NOT EDIT THIS FILE DIRECTLY
- *
- * This module was generated magically with RDB from a source description
- * file. You must edit the source file for changes to be made to this file.
- *
- *
- * Date: Generated on Wed May 8 03:09:20 2013
- * MD5 Checksum d41d8cd98f00b204e9800998ecf8427e
- *
- * Compiled with: RDB Utility combo_header.pl
- * RDB Parser 3.0
- * unknown unknown
- * Perl Interpreter 5.008008
- * Operating System linux
- *
- * Revision History:
- *
- * $brcm_Log: $
- *
- ***************************************************************************/
-
-#ifndef BCHP_SWITCH_INDIR_RW_H__
-#define BCHP_SWITCH_INDIR_RW_H__
-
-/***************************************************************************
- *SWITCH_INDIR_RW
- ***************************************************************************/
-#define BCHP_SWITCH_INDIR_RW_INDIR_ADDR_REG_0 0x04e40300 /* Indirect Address Register 0 */
-#define BCHP_SWITCH_INDIR_RW_INDIR_DATA_LOW_REG_0 0x04e40304 /* Indirect Data Low Register 0 */
-#define BCHP_SWITCH_INDIR_RW_INDIR_DATA_HIGH_REG_0 0x04e40308 /* Indirect Data High Register 0 */
-#define BCHP_SWITCH_INDIR_RW_INDIR_ADDR_REG_1 0x04e4030c /* Indirect Address Register 1 */
-#define BCHP_SWITCH_INDIR_RW_INDIR_DATA_LOW_REG_1 0x04e40310 /* Indirect Data Low Register 1 */
-#define BCHP_SWITCH_INDIR_RW_INDIR_DATA_HIGH_REG_1 0x04e40314 /* Indirect Data High Register 1 */
-
-/***************************************************************************
- *INDIR_ADDR_REG_0 - Indirect Address Register 0
- ***************************************************************************/
-/* SWITCH_INDIR_RW :: INDIR_ADDR_REG_0 :: reserved0 [31:18] */
-#define BCHP_SWITCH_INDIR_RW_INDIR_ADDR_REG_0_reserved0_MASK 0xfffc0000
-#define BCHP_SWITCH_INDIR_RW_INDIR_ADDR_REG_0_reserved0_SHIFT 18
-
-/* SWITCH_INDIR_RW :: INDIR_ADDR_REG_0 :: start_busy [17:17] */
-#define BCHP_SWITCH_INDIR_RW_INDIR_ADDR_REG_0_start_busy_MASK 0x00020000
-#define BCHP_SWITCH_INDIR_RW_INDIR_ADDR_REG_0_start_busy_SHIFT 17
-#define BCHP_SWITCH_INDIR_RW_INDIR_ADDR_REG_0_start_busy_DEFAULT 0x00000000
-
-/* SWITCH_INDIR_RW :: INDIR_ADDR_REG_0 :: r_w [16:16] */
-#define BCHP_SWITCH_INDIR_RW_INDIR_ADDR_REG_0_r_w_MASK 0x00010000
-#define BCHP_SWITCH_INDIR_RW_INDIR_ADDR_REG_0_r_w_SHIFT 16
-#define BCHP_SWITCH_INDIR_RW_INDIR_ADDR_REG_0_r_w_DEFAULT 0x00000000
-
-/* SWITCH_INDIR_RW :: INDIR_ADDR_REG_0 :: reg_page [15:08] */
-#define BCHP_SWITCH_INDIR_RW_INDIR_ADDR_REG_0_reg_page_MASK 0x0000ff00
-#define BCHP_SWITCH_INDIR_RW_INDIR_ADDR_REG_0_reg_page_SHIFT 8
-#define BCHP_SWITCH_INDIR_RW_INDIR_ADDR_REG_0_reg_page_DEFAULT 0x00000000
-
-/* SWITCH_INDIR_RW :: INDIR_ADDR_REG_0 :: reg_offset [07:00] */
-#define BCHP_SWITCH_INDIR_RW_INDIR_ADDR_REG_0_reg_offset_MASK 0x000000ff
-#define BCHP_SWITCH_INDIR_RW_INDIR_ADDR_REG_0_reg_offset_SHIFT 0
-#define BCHP_SWITCH_INDIR_RW_INDIR_ADDR_REG_0_reg_offset_DEFAULT 0x00000000
-
-/***************************************************************************
- *INDIR_DATA_LOW_REG_0 - Indirect Data Low Register 0
- ***************************************************************************/
-/* SWITCH_INDIR_RW :: INDIR_DATA_LOW_REG_0 :: data_low [31:00] */
-#define BCHP_SWITCH_INDIR_RW_INDIR_DATA_LOW_REG_0_data_low_MASK 0xffffffff
-#define BCHP_SWITCH_INDIR_RW_INDIR_DATA_LOW_REG_0_data_low_SHIFT 0
-#define BCHP_SWITCH_INDIR_RW_INDIR_DATA_LOW_REG_0_data_low_DEFAULT 0x00000000
-
-/***************************************************************************
- *INDIR_DATA_HIGH_REG_0 - Indirect Data High Register 0
- ***************************************************************************/
-/* SWITCH_INDIR_RW :: INDIR_DATA_HIGH_REG_0 :: data_high [31:00] */
-#define BCHP_SWITCH_INDIR_RW_INDIR_DATA_HIGH_REG_0_data_high_MASK 0xffffffff
-#define BCHP_SWITCH_INDIR_RW_INDIR_DATA_HIGH_REG_0_data_high_SHIFT 0
-#define BCHP_SWITCH_INDIR_RW_INDIR_DATA_HIGH_REG_0_data_high_DEFAULT 0x00000000
-
-/***************************************************************************
- *INDIR_ADDR_REG_1 - Indirect Address Register 1
- ***************************************************************************/
-/* SWITCH_INDIR_RW :: INDIR_ADDR_REG_1 :: reserved0 [31:18] */
-#define BCHP_SWITCH_INDIR_RW_INDIR_ADDR_REG_1_reserved0_MASK 0xfffc0000
-#define BCHP_SWITCH_INDIR_RW_INDIR_ADDR_REG_1_reserved0_SHIFT 18
-
-/* SWITCH_INDIR_RW :: INDIR_ADDR_REG_1 :: start_busy [17:17] */
-#define BCHP_SWITCH_INDIR_RW_INDIR_ADDR_REG_1_start_busy_MASK 0x00020000
-#define BCHP_SWITCH_INDIR_RW_INDIR_ADDR_REG_1_start_busy_SHIFT 17
-#define BCHP_SWITCH_INDIR_RW_INDIR_ADDR_REG_1_start_busy_DEFAULT 0x00000000
-
-/* SWITCH_INDIR_RW :: INDIR_ADDR_REG_1 :: r_w [16:16] */
-#define BCHP_SWITCH_INDIR_RW_INDIR_ADDR_REG_1_r_w_MASK 0x00010000
-#define BCHP_SWITCH_INDIR_RW_INDIR_ADDR_REG_1_r_w_SHIFT 16
-#define BCHP_SWITCH_INDIR_RW_INDIR_ADDR_REG_1_r_w_DEFAULT 0x00000000
-
-/* SWITCH_INDIR_RW :: INDIR_ADDR_REG_1 :: reg_page [15:08] */
-#define BCHP_SWITCH_INDIR_RW_INDIR_ADDR_REG_1_reg_page_MASK 0x0000ff00
-#define BCHP_SWITCH_INDIR_RW_INDIR_ADDR_REG_1_reg_page_SHIFT 8
-#define BCHP_SWITCH_INDIR_RW_INDIR_ADDR_REG_1_reg_page_DEFAULT 0x00000000
-
-/* SWITCH_INDIR_RW :: INDIR_ADDR_REG_1 :: reg_offset [07:00] */
-#define BCHP_SWITCH_INDIR_RW_INDIR_ADDR_REG_1_reg_offset_MASK 0x000000ff
-#define BCHP_SWITCH_INDIR_RW_INDIR_ADDR_REG_1_reg_offset_SHIFT 0
-#define BCHP_SWITCH_INDIR_RW_INDIR_ADDR_REG_1_reg_offset_DEFAULT 0x00000000
-
-/***************************************************************************
- *INDIR_DATA_LOW_REG_1 - Indirect Data Low Register 1
- ***************************************************************************/
-/* SWITCH_INDIR_RW :: INDIR_DATA_LOW_REG_1 :: data_low [31:00] */
-#define BCHP_SWITCH_INDIR_RW_INDIR_DATA_LOW_REG_1_data_low_MASK 0xffffffff
-#define BCHP_SWITCH_INDIR_RW_INDIR_DATA_LOW_REG_1_data_low_SHIFT 0
-#define BCHP_SWITCH_INDIR_RW_INDIR_DATA_LOW_REG_1_data_low_DEFAULT 0x00000000
-
-/***************************************************************************
- *INDIR_DATA_HIGH_REG_1 - Indirect Data High Register 1
- ***************************************************************************/
-/* SWITCH_INDIR_RW :: INDIR_DATA_HIGH_REG_1 :: data_high [31:00] */
-#define BCHP_SWITCH_INDIR_RW_INDIR_DATA_HIGH_REG_1_data_high_MASK 0xffffffff
-#define BCHP_SWITCH_INDIR_RW_INDIR_DATA_HIGH_REG_1_data_high_SHIFT 0
-#define BCHP_SWITCH_INDIR_RW_INDIR_DATA_HIGH_REG_1_data_high_DEFAULT 0x00000000
-
-#endif /* #ifndef BCHP_SWITCH_INDIR_RW_H__ */
-
-/* End of File */
diff --git a/include/linux/brcmstb/7145a0/bchp_switch_intrl2_0.h b/include/linux/brcmstb/7145a0/bchp_switch_intrl2_0.h
deleted file mode 100644
index 798691c..0000000
--- a/include/linux/brcmstb/7145a0/bchp_switch_intrl2_0.h
+++ /dev/null
@@ -1,1164 +0,0 @@
-/***************************************************************************
- * Copyright (c) 1999-2013, Broadcom Corporation
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
- *
- * Module Description:
- * DO NOT EDIT THIS FILE DIRECTLY
- *
- * This module was generated magically with RDB from a source description
- * file. You must edit the source file for changes to be made to this file.
- *
- *
- * Date: Generated on Wed May 8 03:09:21 2013
- * MD5 Checksum d41d8cd98f00b204e9800998ecf8427e
- *
- * Compiled with: RDB Utility combo_header.pl
- * RDB Parser 3.0
- * unknown unknown
- * Perl Interpreter 5.008008
- * Operating System linux
- *
- * Revision History:
- *
- * $brcm_Log: $
- *
- ***************************************************************************/
-
-#ifndef BCHP_SWITCH_INTRL2_0_H__
-#define BCHP_SWITCH_INTRL2_0_H__
-
-/***************************************************************************
- *SWITCH_INTRL2_0
- ***************************************************************************/
-#define BCHP_SWITCH_INTRL2_0_CPU_STATUS 0x04e40340 /* CPU interrupt Status Register */
-#define BCHP_SWITCH_INTRL2_0_CPU_SET 0x04e40344 /* CPU interrupt Set Register */
-#define BCHP_SWITCH_INTRL2_0_CPU_CLEAR 0x04e40348 /* CPU interrupt Clear Register */
-#define BCHP_SWITCH_INTRL2_0_CPU_MASK_STATUS 0x04e4034c /* CPU interrupt Mask Status Register */
-#define BCHP_SWITCH_INTRL2_0_CPU_MASK_SET 0x04e40350 /* CPU interrupt Mask Set Register */
-#define BCHP_SWITCH_INTRL2_0_CPU_MASK_CLEAR 0x04e40354 /* CPU interrupt Mask Clear Register */
-#define BCHP_SWITCH_INTRL2_0_PCI_STATUS 0x04e40358 /* PCI interrupt Status Register */
-#define BCHP_SWITCH_INTRL2_0_PCI_SET 0x04e4035c /* PCI interrupt Set Register */
-#define BCHP_SWITCH_INTRL2_0_PCI_CLEAR 0x04e40360 /* PCI interrupt Clear Register */
-#define BCHP_SWITCH_INTRL2_0_PCI_MASK_STATUS 0x04e40364 /* PCI interrupt Mask Status Register */
-#define BCHP_SWITCH_INTRL2_0_PCI_MASK_SET 0x04e40368 /* PCI interrupt Mask Set Register */
-#define BCHP_SWITCH_INTRL2_0_PCI_MASK_CLEAR 0x04e4036c /* PCI interrupt Mask Clear Register */
-
-/***************************************************************************
- *CPU_STATUS - CPU interrupt Status Register
- ***************************************************************************/
-/* SWITCH_INTRL2_0 :: CPU_STATUS :: reserved0 [31:17] */
-#define BCHP_SWITCH_INTRL2_0_CPU_STATUS_reserved0_MASK 0xfffe0000
-#define BCHP_SWITCH_INTRL2_0_CPU_STATUS_reserved0_SHIFT 17
-
-/* SWITCH_INTRL2_0 :: CPU_STATUS :: failover_off_intr [16:16] */
-#define BCHP_SWITCH_INTRL2_0_CPU_STATUS_failover_off_intr_MASK 0x00010000
-#define BCHP_SWITCH_INTRL2_0_CPU_STATUS_failover_off_intr_SHIFT 16
-#define BCHP_SWITCH_INTRL2_0_CPU_STATUS_failover_off_intr_DEFAULT 0x00000000
-
-/* SWITCH_INTRL2_0 :: CPU_STATUS :: failover_on_intr [15:15] */
-#define BCHP_SWITCH_INTRL2_0_CPU_STATUS_failover_on_intr_MASK 0x00008000
-#define BCHP_SWITCH_INTRL2_0_CPU_STATUS_failover_on_intr_SHIFT 15
-#define BCHP_SWITCH_INTRL2_0_CPU_STATUS_failover_on_intr_DEFAULT 0x00000000
-
-/* SWITCH_INTRL2_0 :: CPU_STATUS :: ubus_err_intr [14:14] */
-#define BCHP_SWITCH_INTRL2_0_CPU_STATUS_ubus_err_intr_MASK 0x00004000
-#define BCHP_SWITCH_INTRL2_0_CPU_STATUS_ubus_err_intr_SHIFT 14
-#define BCHP_SWITCH_INTRL2_0_CPU_STATUS_ubus_err_intr_DEFAULT 0x00000000
-
-/* SWITCH_INTRL2_0 :: CPU_STATUS :: gisb_err_intr [13:13] */
-#define BCHP_SWITCH_INTRL2_0_CPU_STATUS_gisb_err_intr_MASK 0x00002000
-#define BCHP_SWITCH_INTRL2_0_CPU_STATUS_gisb_err_intr_SHIFT 13
-#define BCHP_SWITCH_INTRL2_0_CPU_STATUS_gisb_err_intr_DEFAULT 0x00000000
-
-/* SWITCH_INTRL2_0 :: CPU_STATUS :: mdio_done_intr [12:12] */
-#define BCHP_SWITCH_INTRL2_0_CPU_STATUS_mdio_done_intr_MASK 0x00001000
-#define BCHP_SWITCH_INTRL2_0_CPU_STATUS_mdio_done_intr_SHIFT 12
-#define BCHP_SWITCH_INTRL2_0_CPU_STATUS_mdio_done_intr_DEFAULT 0x00000000
-
-/* SWITCH_INTRL2_0 :: CPU_STATUS :: mdio_err_up_intr [11:11] */
-#define BCHP_SWITCH_INTRL2_0_CPU_STATUS_mdio_err_up_intr_MASK 0x00000800
-#define BCHP_SWITCH_INTRL2_0_CPU_STATUS_mdio_err_up_intr_SHIFT 11
-#define BCHP_SWITCH_INTRL2_0_CPU_STATUS_mdio_err_up_intr_DEFAULT 0x00000000
-
-/* SWITCH_INTRL2_0 :: CPU_STATUS :: 1588_intr [10:10] */
-#define BCHP_SWITCH_INTRL2_0_CPU_STATUS_1588_intr_MASK 0x00000400
-#define BCHP_SWITCH_INTRL2_0_CPU_STATUS_1588_intr_SHIFT 10
-#define BCHP_SWITCH_INTRL2_0_CPU_STATUS_1588_intr_DEFAULT 0x00000000
-
-/* SWITCH_INTRL2_0 :: CPU_STATUS :: p7_cpu_wake_timer_intr [09:09] */
-#define BCHP_SWITCH_INTRL2_0_CPU_STATUS_p7_cpu_wake_timer_intr_MASK 0x00000200
-#define BCHP_SWITCH_INTRL2_0_CPU_STATUS_p7_cpu_wake_timer_intr_SHIFT 9
-#define BCHP_SWITCH_INTRL2_0_CPU_STATUS_p7_cpu_wake_timer_intr_DEFAULT 0x00000000
-
-/* SWITCH_INTRL2_0 :: CPU_STATUS :: p8_cpu_wake_timer_intr [08:08] */
-#define BCHP_SWITCH_INTRL2_0_CPU_STATUS_p8_cpu_wake_timer_intr_MASK 0x00000100
-#define BCHP_SWITCH_INTRL2_0_CPU_STATUS_p8_cpu_wake_timer_intr_SHIFT 8
-#define BCHP_SWITCH_INTRL2_0_CPU_STATUS_p8_cpu_wake_timer_intr_DEFAULT 0x00000000
-
-/* SWITCH_INTRL2_0 :: CPU_STATUS :: p5_cpu_wake_timer_intr [07:07] */
-#define BCHP_SWITCH_INTRL2_0_CPU_STATUS_p5_cpu_wake_timer_intr_MASK 0x00000080
-#define BCHP_SWITCH_INTRL2_0_CPU_STATUS_p5_cpu_wake_timer_intr_SHIFT 7
-#define BCHP_SWITCH_INTRL2_0_CPU_STATUS_p5_cpu_wake_timer_intr_DEFAULT 0x00000000
-
-/* SWITCH_INTRL2_0 :: CPU_STATUS :: eee_lpi_intr [06:06] */
-#define BCHP_SWITCH_INTRL2_0_CPU_STATUS_eee_lpi_intr_MASK 0x00000040
-#define BCHP_SWITCH_INTRL2_0_CPU_STATUS_eee_lpi_intr_SHIFT 6
-#define BCHP_SWITCH_INTRL2_0_CPU_STATUS_eee_lpi_intr_DEFAULT 0x00000000
-
-/* SWITCH_INTRL2_0 :: CPU_STATUS :: memory_double_err_intr [05:05] */
-#define BCHP_SWITCH_INTRL2_0_CPU_STATUS_memory_double_err_intr_MASK 0x00000020
-#define BCHP_SWITCH_INTRL2_0_CPU_STATUS_memory_double_err_intr_SHIFT 5
-#define BCHP_SWITCH_INTRL2_0_CPU_STATUS_memory_double_err_intr_DEFAULT 0x00000000
-
-/* SWITCH_INTRL2_0 :: CPU_STATUS :: p0_gphy_intr [04:04] */
-#define BCHP_SWITCH_INTRL2_0_CPU_STATUS_p0_gphy_intr_MASK 0x00000010
-#define BCHP_SWITCH_INTRL2_0_CPU_STATUS_p0_gphy_intr_SHIFT 4
-#define BCHP_SWITCH_INTRL2_0_CPU_STATUS_p0_gphy_intr_DEFAULT 0x00000000
-
-/* SWITCH_INTRL2_0 :: CPU_STATUS :: p0_energy_off_intr [03:03] */
-#define BCHP_SWITCH_INTRL2_0_CPU_STATUS_p0_energy_off_intr_MASK 0x00000008
-#define BCHP_SWITCH_INTRL2_0_CPU_STATUS_p0_energy_off_intr_SHIFT 3
-#define BCHP_SWITCH_INTRL2_0_CPU_STATUS_p0_energy_off_intr_DEFAULT 0x00000000
-
-/* SWITCH_INTRL2_0 :: CPU_STATUS :: p0_energy_on_intr [02:02] */
-#define BCHP_SWITCH_INTRL2_0_CPU_STATUS_p0_energy_on_intr_MASK 0x00000004
-#define BCHP_SWITCH_INTRL2_0_CPU_STATUS_p0_energy_on_intr_SHIFT 2
-#define BCHP_SWITCH_INTRL2_0_CPU_STATUS_p0_energy_on_intr_DEFAULT 0x00000000
-
-/* SWITCH_INTRL2_0 :: CPU_STATUS :: p0_link_down_intr [01:01] */
-#define BCHP_SWITCH_INTRL2_0_CPU_STATUS_p0_link_down_intr_MASK 0x00000002
-#define BCHP_SWITCH_INTRL2_0_CPU_STATUS_p0_link_down_intr_SHIFT 1
-#define BCHP_SWITCH_INTRL2_0_CPU_STATUS_p0_link_down_intr_DEFAULT 0x00000000
-
-/* SWITCH_INTRL2_0 :: CPU_STATUS :: p0_link_up_intr [00:00] */
-#define BCHP_SWITCH_INTRL2_0_CPU_STATUS_p0_link_up_intr_MASK 0x00000001
-#define BCHP_SWITCH_INTRL2_0_CPU_STATUS_p0_link_up_intr_SHIFT 0
-#define BCHP_SWITCH_INTRL2_0_CPU_STATUS_p0_link_up_intr_DEFAULT 0x00000000
-
-/***************************************************************************
- *CPU_SET - CPU interrupt Set Register
- ***************************************************************************/
-/* SWITCH_INTRL2_0 :: CPU_SET :: reserved0 [31:17] */
-#define BCHP_SWITCH_INTRL2_0_CPU_SET_reserved0_MASK 0xfffe0000
-#define BCHP_SWITCH_INTRL2_0_CPU_SET_reserved0_SHIFT 17
-
-/* SWITCH_INTRL2_0 :: CPU_SET :: failover_off_intr [16:16] */
-#define BCHP_SWITCH_INTRL2_0_CPU_SET_failover_off_intr_MASK 0x00010000
-#define BCHP_SWITCH_INTRL2_0_CPU_SET_failover_off_intr_SHIFT 16
-#define BCHP_SWITCH_INTRL2_0_CPU_SET_failover_off_intr_DEFAULT 0x00000000
-
-/* SWITCH_INTRL2_0 :: CPU_SET :: failover_on_intr [15:15] */
-#define BCHP_SWITCH_INTRL2_0_CPU_SET_failover_on_intr_MASK 0x00008000
-#define BCHP_SWITCH_INTRL2_0_CPU_SET_failover_on_intr_SHIFT 15
-#define BCHP_SWITCH_INTRL2_0_CPU_SET_failover_on_intr_DEFAULT 0x00000000
-
-/* SWITCH_INTRL2_0 :: CPU_SET :: ubus_err_intr [14:14] */
-#define BCHP_SWITCH_INTRL2_0_CPU_SET_ubus_err_intr_MASK 0x00004000
-#define BCHP_SWITCH_INTRL2_0_CPU_SET_ubus_err_intr_SHIFT 14
-#define BCHP_SWITCH_INTRL2_0_CPU_SET_ubus_err_intr_DEFAULT 0x00000000
-
-/* SWITCH_INTRL2_0 :: CPU_SET :: gisb_err_intr [13:13] */
-#define BCHP_SWITCH_INTRL2_0_CPU_SET_gisb_err_intr_MASK 0x00002000
-#define BCHP_SWITCH_INTRL2_0_CPU_SET_gisb_err_intr_SHIFT 13
-#define BCHP_SWITCH_INTRL2_0_CPU_SET_gisb_err_intr_DEFAULT 0x00000000
-
-/* SWITCH_INTRL2_0 :: CPU_SET :: mdio_done_intr [12:12] */
-#define BCHP_SWITCH_INTRL2_0_CPU_SET_mdio_done_intr_MASK 0x00001000
-#define BCHP_SWITCH_INTRL2_0_CPU_SET_mdio_done_intr_SHIFT 12
-#define BCHP_SWITCH_INTRL2_0_CPU_SET_mdio_done_intr_DEFAULT 0x00000000
-
-/* SWITCH_INTRL2_0 :: CPU_SET :: mdio_err_up_intr [11:11] */
-#define BCHP_SWITCH_INTRL2_0_CPU_SET_mdio_err_up_intr_MASK 0x00000800
-#define BCHP_SWITCH_INTRL2_0_CPU_SET_mdio_err_up_intr_SHIFT 11
-#define BCHP_SWITCH_INTRL2_0_CPU_SET_mdio_err_up_intr_DEFAULT 0x00000000
-
-/* SWITCH_INTRL2_0 :: CPU_SET :: 1588_intr [10:10] */
-#define BCHP_SWITCH_INTRL2_0_CPU_SET_1588_intr_MASK 0x00000400
-#define BCHP_SWITCH_INTRL2_0_CPU_SET_1588_intr_SHIFT 10
-#define BCHP_SWITCH_INTRL2_0_CPU_SET_1588_intr_DEFAULT 0x00000000
-
-/* SWITCH_INTRL2_0 :: CPU_SET :: p7_cpu_wake_timer_intr [09:09] */
-#define BCHP_SWITCH_INTRL2_0_CPU_SET_p7_cpu_wake_timer_intr_MASK 0x00000200
-#define BCHP_SWITCH_INTRL2_0_CPU_SET_p7_cpu_wake_timer_intr_SHIFT 9
-#define BCHP_SWITCH_INTRL2_0_CPU_SET_p7_cpu_wake_timer_intr_DEFAULT 0x00000000
-
-/* SWITCH_INTRL2_0 :: CPU_SET :: p8_cpu_wake_timer_intr [08:08] */
-#define BCHP_SWITCH_INTRL2_0_CPU_SET_p8_cpu_wake_timer_intr_MASK 0x00000100
-#define BCHP_SWITCH_INTRL2_0_CPU_SET_p8_cpu_wake_timer_intr_SHIFT 8
-#define BCHP_SWITCH_INTRL2_0_CPU_SET_p8_cpu_wake_timer_intr_DEFAULT 0x00000000
-
-/* SWITCH_INTRL2_0 :: CPU_SET :: p5_cpu_wake_timer_intr [07:07] */
-#define BCHP_SWITCH_INTRL2_0_CPU_SET_p5_cpu_wake_timer_intr_MASK 0x00000080
-#define BCHP_SWITCH_INTRL2_0_CPU_SET_p5_cpu_wake_timer_intr_SHIFT 7
-#define BCHP_SWITCH_INTRL2_0_CPU_SET_p5_cpu_wake_timer_intr_DEFAULT 0x00000000
-
-/* SWITCH_INTRL2_0 :: CPU_SET :: eee_lpi_intr [06:06] */
-#define BCHP_SWITCH_INTRL2_0_CPU_SET_eee_lpi_intr_MASK 0x00000040
-#define BCHP_SWITCH_INTRL2_0_CPU_SET_eee_lpi_intr_SHIFT 6
-#define BCHP_SWITCH_INTRL2_0_CPU_SET_eee_lpi_intr_DEFAULT 0x00000000
-
-/* SWITCH_INTRL2_0 :: CPU_SET :: memory_double_err_intr [05:05] */
-#define BCHP_SWITCH_INTRL2_0_CPU_SET_memory_double_err_intr_MASK 0x00000020
-#define BCHP_SWITCH_INTRL2_0_CPU_SET_memory_double_err_intr_SHIFT 5
-#define BCHP_SWITCH_INTRL2_0_CPU_SET_memory_double_err_intr_DEFAULT 0x00000000
-
-/* SWITCH_INTRL2_0 :: CPU_SET :: p0_gphy_intr [04:04] */
-#define BCHP_SWITCH_INTRL2_0_CPU_SET_p0_gphy_intr_MASK 0x00000010
-#define BCHP_SWITCH_INTRL2_0_CPU_SET_p0_gphy_intr_SHIFT 4
-#define BCHP_SWITCH_INTRL2_0_CPU_SET_p0_gphy_intr_DEFAULT 0x00000000
-
-/* SWITCH_INTRL2_0 :: CPU_SET :: p0_energy_off_intr [03:03] */
-#define BCHP_SWITCH_INTRL2_0_CPU_SET_p0_energy_off_intr_MASK 0x00000008
-#define BCHP_SWITCH_INTRL2_0_CPU_SET_p0_energy_off_intr_SHIFT 3
-#define BCHP_SWITCH_INTRL2_0_CPU_SET_p0_energy_off_intr_DEFAULT 0x00000000
-
-/* SWITCH_INTRL2_0 :: CPU_SET :: p0_energy_on_intr [02:02] */
-#define BCHP_SWITCH_INTRL2_0_CPU_SET_p0_energy_on_intr_MASK 0x00000004
-#define BCHP_SWITCH_INTRL2_0_CPU_SET_p0_energy_on_intr_SHIFT 2
-#define BCHP_SWITCH_INTRL2_0_CPU_SET_p0_energy_on_intr_DEFAULT 0x00000000
-
-/* SWITCH_INTRL2_0 :: CPU_SET :: p0_link_down_intr [01:01] */
-#define BCHP_SWITCH_INTRL2_0_CPU_SET_p0_link_down_intr_MASK 0x00000002
-#define BCHP_SWITCH_INTRL2_0_CPU_SET_p0_link_down_intr_SHIFT 1
-#define BCHP_SWITCH_INTRL2_0_CPU_SET_p0_link_down_intr_DEFAULT 0x00000000
-
-/* SWITCH_INTRL2_0 :: CPU_SET :: p0_link_up_intr [00:00] */
-#define BCHP_SWITCH_INTRL2_0_CPU_SET_p0_link_up_intr_MASK 0x00000001
-#define BCHP_SWITCH_INTRL2_0_CPU_SET_p0_link_up_intr_SHIFT 0
-#define BCHP_SWITCH_INTRL2_0_CPU_SET_p0_link_up_intr_DEFAULT 0x00000000
-
-/***************************************************************************
- *CPU_CLEAR - CPU interrupt Clear Register
- ***************************************************************************/
-/* SWITCH_INTRL2_0 :: CPU_CLEAR :: reserved0 [31:17] */
-#define BCHP_SWITCH_INTRL2_0_CPU_CLEAR_reserved0_MASK 0xfffe0000
-#define BCHP_SWITCH_INTRL2_0_CPU_CLEAR_reserved0_SHIFT 17
-
-/* SWITCH_INTRL2_0 :: CPU_CLEAR :: failover_off_intr [16:16] */
-#define BCHP_SWITCH_INTRL2_0_CPU_CLEAR_failover_off_intr_MASK 0x00010000
-#define BCHP_SWITCH_INTRL2_0_CPU_CLEAR_failover_off_intr_SHIFT 16
-#define BCHP_SWITCH_INTRL2_0_CPU_CLEAR_failover_off_intr_DEFAULT 0x00000000
-
-/* SWITCH_INTRL2_0 :: CPU_CLEAR :: failover_on_intr [15:15] */
-#define BCHP_SWITCH_INTRL2_0_CPU_CLEAR_failover_on_intr_MASK 0x00008000
-#define BCHP_SWITCH_INTRL2_0_CPU_CLEAR_failover_on_intr_SHIFT 15
-#define BCHP_SWITCH_INTRL2_0_CPU_CLEAR_failover_on_intr_DEFAULT 0x00000000
-
-/* SWITCH_INTRL2_0 :: CPU_CLEAR :: ubus_err_intr [14:14] */
-#define BCHP_SWITCH_INTRL2_0_CPU_CLEAR_ubus_err_intr_MASK 0x00004000
-#define BCHP_SWITCH_INTRL2_0_CPU_CLEAR_ubus_err_intr_SHIFT 14
-#define BCHP_SWITCH_INTRL2_0_CPU_CLEAR_ubus_err_intr_DEFAULT 0x00000000
-
-/* SWITCH_INTRL2_0 :: CPU_CLEAR :: gisb_err_intr [13:13] */
-#define BCHP_SWITCH_INTRL2_0_CPU_CLEAR_gisb_err_intr_MASK 0x00002000
-#define BCHP_SWITCH_INTRL2_0_CPU_CLEAR_gisb_err_intr_SHIFT 13
-#define BCHP_SWITCH_INTRL2_0_CPU_CLEAR_gisb_err_intr_DEFAULT 0x00000000
-
-/* SWITCH_INTRL2_0 :: CPU_CLEAR :: mdio_done_intr [12:12] */
-#define BCHP_SWITCH_INTRL2_0_CPU_CLEAR_mdio_done_intr_MASK 0x00001000
-#define BCHP_SWITCH_INTRL2_0_CPU_CLEAR_mdio_done_intr_SHIFT 12
-#define BCHP_SWITCH_INTRL2_0_CPU_CLEAR_mdio_done_intr_DEFAULT 0x00000000
-
-/* SWITCH_INTRL2_0 :: CPU_CLEAR :: mdio_err_up_intr [11:11] */
-#define BCHP_SWITCH_INTRL2_0_CPU_CLEAR_mdio_err_up_intr_MASK 0x00000800
-#define BCHP_SWITCH_INTRL2_0_CPU_CLEAR_mdio_err_up_intr_SHIFT 11
-#define BCHP_SWITCH_INTRL2_0_CPU_CLEAR_mdio_err_up_intr_DEFAULT 0x00000000
-
-/* SWITCH_INTRL2_0 :: CPU_CLEAR :: 1588_intr [10:10] */
-#define BCHP_SWITCH_INTRL2_0_CPU_CLEAR_1588_intr_MASK 0x00000400
-#define BCHP_SWITCH_INTRL2_0_CPU_CLEAR_1588_intr_SHIFT 10
-#define BCHP_SWITCH_INTRL2_0_CPU_CLEAR_1588_intr_DEFAULT 0x00000000
-
-/* SWITCH_INTRL2_0 :: CPU_CLEAR :: p7_cpu_wake_timer_intr [09:09] */
-#define BCHP_SWITCH_INTRL2_0_CPU_CLEAR_p7_cpu_wake_timer_intr_MASK 0x00000200
-#define BCHP_SWITCH_INTRL2_0_CPU_CLEAR_p7_cpu_wake_timer_intr_SHIFT 9
-#define BCHP_SWITCH_INTRL2_0_CPU_CLEAR_p7_cpu_wake_timer_intr_DEFAULT 0x00000000
-
-/* SWITCH_INTRL2_0 :: CPU_CLEAR :: p8_cpu_wake_timer_intr [08:08] */
-#define BCHP_SWITCH_INTRL2_0_CPU_CLEAR_p8_cpu_wake_timer_intr_MASK 0x00000100
-#define BCHP_SWITCH_INTRL2_0_CPU_CLEAR_p8_cpu_wake_timer_intr_SHIFT 8
-#define BCHP_SWITCH_INTRL2_0_CPU_CLEAR_p8_cpu_wake_timer_intr_DEFAULT 0x00000000
-
-/* SWITCH_INTRL2_0 :: CPU_CLEAR :: p5_cpu_wake_timer_intr [07:07] */
-#define BCHP_SWITCH_INTRL2_0_CPU_CLEAR_p5_cpu_wake_timer_intr_MASK 0x00000080
-#define BCHP_SWITCH_INTRL2_0_CPU_CLEAR_p5_cpu_wake_timer_intr_SHIFT 7
-#define BCHP_SWITCH_INTRL2_0_CPU_CLEAR_p5_cpu_wake_timer_intr_DEFAULT 0x00000000
-
-/* SWITCH_INTRL2_0 :: CPU_CLEAR :: eee_lpi_intr [06:06] */
-#define BCHP_SWITCH_INTRL2_0_CPU_CLEAR_eee_lpi_intr_MASK 0x00000040
-#define BCHP_SWITCH_INTRL2_0_CPU_CLEAR_eee_lpi_intr_SHIFT 6
-#define BCHP_SWITCH_INTRL2_0_CPU_CLEAR_eee_lpi_intr_DEFAULT 0x00000000
-
-/* SWITCH_INTRL2_0 :: CPU_CLEAR :: memory_double_err_intr [05:05] */
-#define BCHP_SWITCH_INTRL2_0_CPU_CLEAR_memory_double_err_intr_MASK 0x00000020
-#define BCHP_SWITCH_INTRL2_0_CPU_CLEAR_memory_double_err_intr_SHIFT 5
-#define BCHP_SWITCH_INTRL2_0_CPU_CLEAR_memory_double_err_intr_DEFAULT 0x00000000
-
-/* SWITCH_INTRL2_0 :: CPU_CLEAR :: p0_gphy_intr [04:04] */
-#define BCHP_SWITCH_INTRL2_0_CPU_CLEAR_p0_gphy_intr_MASK 0x00000010
-#define BCHP_SWITCH_INTRL2_0_CPU_CLEAR_p0_gphy_intr_SHIFT 4
-#define BCHP_SWITCH_INTRL2_0_CPU_CLEAR_p0_gphy_intr_DEFAULT 0x00000000
-
-/* SWITCH_INTRL2_0 :: CPU_CLEAR :: p0_energy_off_intr [03:03] */
-#define BCHP_SWITCH_INTRL2_0_CPU_CLEAR_p0_energy_off_intr_MASK 0x00000008
-#define BCHP_SWITCH_INTRL2_0_CPU_CLEAR_p0_energy_off_intr_SHIFT 3
-#define BCHP_SWITCH_INTRL2_0_CPU_CLEAR_p0_energy_off_intr_DEFAULT 0x00000000
-
-/* SWITCH_INTRL2_0 :: CPU_CLEAR :: p0_energy_on_intr [02:02] */
-#define BCHP_SWITCH_INTRL2_0_CPU_CLEAR_p0_energy_on_intr_MASK 0x00000004
-#define BCHP_SWITCH_INTRL2_0_CPU_CLEAR_p0_energy_on_intr_SHIFT 2
-#define BCHP_SWITCH_INTRL2_0_CPU_CLEAR_p0_energy_on_intr_DEFAULT 0x00000000
-
-/* SWITCH_INTRL2_0 :: CPU_CLEAR :: p0_link_down_intr [01:01] */
-#define BCHP_SWITCH_INTRL2_0_CPU_CLEAR_p0_link_down_intr_MASK 0x00000002
-#define BCHP_SWITCH_INTRL2_0_CPU_CLEAR_p0_link_down_intr_SHIFT 1
-#define BCHP_SWITCH_INTRL2_0_CPU_CLEAR_p0_link_down_intr_DEFAULT 0x00000000
-
-/* SWITCH_INTRL2_0 :: CPU_CLEAR :: p0_link_up_intr [00:00] */
-#define BCHP_SWITCH_INTRL2_0_CPU_CLEAR_p0_link_up_intr_MASK 0x00000001
-#define BCHP_SWITCH_INTRL2_0_CPU_CLEAR_p0_link_up_intr_SHIFT 0
-#define BCHP_SWITCH_INTRL2_0_CPU_CLEAR_p0_link_up_intr_DEFAULT 0x00000000
-
-/***************************************************************************
- *CPU_MASK_STATUS - CPU interrupt Mask Status Register
- ***************************************************************************/
-/* SWITCH_INTRL2_0 :: CPU_MASK_STATUS :: reserved0 [31:17] */
-#define BCHP_SWITCH_INTRL2_0_CPU_MASK_STATUS_reserved0_MASK 0xfffe0000
-#define BCHP_SWITCH_INTRL2_0_CPU_MASK_STATUS_reserved0_SHIFT 17
-
-/* SWITCH_INTRL2_0 :: CPU_MASK_STATUS :: failover_off_intr_mask [16:16] */
-#define BCHP_SWITCH_INTRL2_0_CPU_MASK_STATUS_failover_off_intr_mask_MASK 0x00010000
-#define BCHP_SWITCH_INTRL2_0_CPU_MASK_STATUS_failover_off_intr_mask_SHIFT 16
-#define BCHP_SWITCH_INTRL2_0_CPU_MASK_STATUS_failover_off_intr_mask_DEFAULT 0x00000001
-
-/* SWITCH_INTRL2_0 :: CPU_MASK_STATUS :: failover_on_intr_mask [15:15] */
-#define BCHP_SWITCH_INTRL2_0_CPU_MASK_STATUS_failover_on_intr_mask_MASK 0x00008000
-#define BCHP_SWITCH_INTRL2_0_CPU_MASK_STATUS_failover_on_intr_mask_SHIFT 15
-#define BCHP_SWITCH_INTRL2_0_CPU_MASK_STATUS_failover_on_intr_mask_DEFAULT 0x00000001
-
-/* SWITCH_INTRL2_0 :: CPU_MASK_STATUS :: ubus_err_intr_mask [14:14] */
-#define BCHP_SWITCH_INTRL2_0_CPU_MASK_STATUS_ubus_err_intr_mask_MASK 0x00004000
-#define BCHP_SWITCH_INTRL2_0_CPU_MASK_STATUS_ubus_err_intr_mask_SHIFT 14
-#define BCHP_SWITCH_INTRL2_0_CPU_MASK_STATUS_ubus_err_intr_mask_DEFAULT 0x00000001
-
-/* SWITCH_INTRL2_0 :: CPU_MASK_STATUS :: gisb_err_intr_mask [13:13] */
-#define BCHP_SWITCH_INTRL2_0_CPU_MASK_STATUS_gisb_err_intr_mask_MASK 0x00002000
-#define BCHP_SWITCH_INTRL2_0_CPU_MASK_STATUS_gisb_err_intr_mask_SHIFT 13
-#define BCHP_SWITCH_INTRL2_0_CPU_MASK_STATUS_gisb_err_intr_mask_DEFAULT 0x00000001
-
-/* SWITCH_INTRL2_0 :: CPU_MASK_STATUS :: mdio_done_intr_mask [12:12] */
-#define BCHP_SWITCH_INTRL2_0_CPU_MASK_STATUS_mdio_done_intr_mask_MASK 0x00001000
-#define BCHP_SWITCH_INTRL2_0_CPU_MASK_STATUS_mdio_done_intr_mask_SHIFT 12
-#define BCHP_SWITCH_INTRL2_0_CPU_MASK_STATUS_mdio_done_intr_mask_DEFAULT 0x00000001
-
-/* SWITCH_INTRL2_0 :: CPU_MASK_STATUS :: mdio_err_intr_mask [11:11] */
-#define BCHP_SWITCH_INTRL2_0_CPU_MASK_STATUS_mdio_err_intr_mask_MASK 0x00000800
-#define BCHP_SWITCH_INTRL2_0_CPU_MASK_STATUS_mdio_err_intr_mask_SHIFT 11
-#define BCHP_SWITCH_INTRL2_0_CPU_MASK_STATUS_mdio_err_intr_mask_DEFAULT 0x00000001
-
-/* SWITCH_INTRL2_0 :: CPU_MASK_STATUS :: 1588_intr_mask [10:10] */
-#define BCHP_SWITCH_INTRL2_0_CPU_MASK_STATUS_1588_intr_mask_MASK 0x00000400
-#define BCHP_SWITCH_INTRL2_0_CPU_MASK_STATUS_1588_intr_mask_SHIFT 10
-#define BCHP_SWITCH_INTRL2_0_CPU_MASK_STATUS_1588_intr_mask_DEFAULT 0x00000001
-
-/* SWITCH_INTRL2_0 :: CPU_MASK_STATUS :: p7_cpu_wake_timer_intr_mask [09:09] */
-#define BCHP_SWITCH_INTRL2_0_CPU_MASK_STATUS_p7_cpu_wake_timer_intr_mask_MASK 0x00000200
-#define BCHP_SWITCH_INTRL2_0_CPU_MASK_STATUS_p7_cpu_wake_timer_intr_mask_SHIFT 9
-#define BCHP_SWITCH_INTRL2_0_CPU_MASK_STATUS_p7_cpu_wake_timer_intr_mask_DEFAULT 0x00000001
-
-/* SWITCH_INTRL2_0 :: CPU_MASK_STATUS :: p8_cpu_wake_timer_intr_mask [08:08] */
-#define BCHP_SWITCH_INTRL2_0_CPU_MASK_STATUS_p8_cpu_wake_timer_intr_mask_MASK 0x00000100
-#define BCHP_SWITCH_INTRL2_0_CPU_MASK_STATUS_p8_cpu_wake_timer_intr_mask_SHIFT 8
-#define BCHP_SWITCH_INTRL2_0_CPU_MASK_STATUS_p8_cpu_wake_timer_intr_mask_DEFAULT 0x00000001
-
-/* SWITCH_INTRL2_0 :: CPU_MASK_STATUS :: p5_cpu_wake_timer_intr_mask [07:07] */
-#define BCHP_SWITCH_INTRL2_0_CPU_MASK_STATUS_p5_cpu_wake_timer_intr_mask_MASK 0x00000080
-#define BCHP_SWITCH_INTRL2_0_CPU_MASK_STATUS_p5_cpu_wake_timer_intr_mask_SHIFT 7
-#define BCHP_SWITCH_INTRL2_0_CPU_MASK_STATUS_p5_cpu_wake_timer_intr_mask_DEFAULT 0x00000001
-
-/* SWITCH_INTRL2_0 :: CPU_MASK_STATUS :: eee_lpi_intr_mask [06:06] */
-#define BCHP_SWITCH_INTRL2_0_CPU_MASK_STATUS_eee_lpi_intr_mask_MASK 0x00000040
-#define BCHP_SWITCH_INTRL2_0_CPU_MASK_STATUS_eee_lpi_intr_mask_SHIFT 6
-#define BCHP_SWITCH_INTRL2_0_CPU_MASK_STATUS_eee_lpi_intr_mask_DEFAULT 0x00000001
-
-/* SWITCH_INTRL2_0 :: CPU_MASK_STATUS :: memory_double_err_intr_mask [05:05] */
-#define BCHP_SWITCH_INTRL2_0_CPU_MASK_STATUS_memory_double_err_intr_mask_MASK 0x00000020
-#define BCHP_SWITCH_INTRL2_0_CPU_MASK_STATUS_memory_double_err_intr_mask_SHIFT 5
-#define BCHP_SWITCH_INTRL2_0_CPU_MASK_STATUS_memory_double_err_intr_mask_DEFAULT 0x00000001
-
-/* SWITCH_INTRL2_0 :: CPU_MASK_STATUS :: p0_gphy_intr_mask [04:04] */
-#define BCHP_SWITCH_INTRL2_0_CPU_MASK_STATUS_p0_gphy_intr_mask_MASK 0x00000010
-#define BCHP_SWITCH_INTRL2_0_CPU_MASK_STATUS_p0_gphy_intr_mask_SHIFT 4
-#define BCHP_SWITCH_INTRL2_0_CPU_MASK_STATUS_p0_gphy_intr_mask_DEFAULT 0x00000001
-
-/* SWITCH_INTRL2_0 :: CPU_MASK_STATUS :: p0_energy_off_intr_mask [03:03] */
-#define BCHP_SWITCH_INTRL2_0_CPU_MASK_STATUS_p0_energy_off_intr_mask_MASK 0x00000008
-#define BCHP_SWITCH_INTRL2_0_CPU_MASK_STATUS_p0_energy_off_intr_mask_SHIFT 3
-#define BCHP_SWITCH_INTRL2_0_CPU_MASK_STATUS_p0_energy_off_intr_mask_DEFAULT 0x00000001
-
-/* SWITCH_INTRL2_0 :: CPU_MASK_STATUS :: p0_energy_on_intr_mask [02:02] */
-#define BCHP_SWITCH_INTRL2_0_CPU_MASK_STATUS_p0_energy_on_intr_mask_MASK 0x00000004
-#define BCHP_SWITCH_INTRL2_0_CPU_MASK_STATUS_p0_energy_on_intr_mask_SHIFT 2
-#define BCHP_SWITCH_INTRL2_0_CPU_MASK_STATUS_p0_energy_on_intr_mask_DEFAULT 0x00000001
-
-/* SWITCH_INTRL2_0 :: CPU_MASK_STATUS :: p0_link_down_intr_mask [01:01] */
-#define BCHP_SWITCH_INTRL2_0_CPU_MASK_STATUS_p0_link_down_intr_mask_MASK 0x00000002
-#define BCHP_SWITCH_INTRL2_0_CPU_MASK_STATUS_p0_link_down_intr_mask_SHIFT 1
-#define BCHP_SWITCH_INTRL2_0_CPU_MASK_STATUS_p0_link_down_intr_mask_DEFAULT 0x00000001
-
-/* SWITCH_INTRL2_0 :: CPU_MASK_STATUS :: p0_link_up_intr_mask [00:00] */
-#define BCHP_SWITCH_INTRL2_0_CPU_MASK_STATUS_p0_link_up_intr_mask_MASK 0x00000001
-#define BCHP_SWITCH_INTRL2_0_CPU_MASK_STATUS_p0_link_up_intr_mask_SHIFT 0
-#define BCHP_SWITCH_INTRL2_0_CPU_MASK_STATUS_p0_link_up_intr_mask_DEFAULT 0x00000001
-
-/***************************************************************************
- *CPU_MASK_SET - CPU interrupt Mask Set Register
- ***************************************************************************/
-/* SWITCH_INTRL2_0 :: CPU_MASK_SET :: reserved0 [31:17] */
-#define BCHP_SWITCH_INTRL2_0_CPU_MASK_SET_reserved0_MASK 0xfffe0000
-#define BCHP_SWITCH_INTRL2_0_CPU_MASK_SET_reserved0_SHIFT 17
-
-/* SWITCH_INTRL2_0 :: CPU_MASK_SET :: failover_off_intr_mask [16:16] */
-#define BCHP_SWITCH_INTRL2_0_CPU_MASK_SET_failover_off_intr_mask_MASK 0x00010000
-#define BCHP_SWITCH_INTRL2_0_CPU_MASK_SET_failover_off_intr_mask_SHIFT 16
-#define BCHP_SWITCH_INTRL2_0_CPU_MASK_SET_failover_off_intr_mask_DEFAULT 0x00000001
-
-/* SWITCH_INTRL2_0 :: CPU_MASK_SET :: failover_on_intr_mask [15:15] */
-#define BCHP_SWITCH_INTRL2_0_CPU_MASK_SET_failover_on_intr_mask_MASK 0x00008000
-#define BCHP_SWITCH_INTRL2_0_CPU_MASK_SET_failover_on_intr_mask_SHIFT 15
-#define BCHP_SWITCH_INTRL2_0_CPU_MASK_SET_failover_on_intr_mask_DEFAULT 0x00000001
-
-/* SWITCH_INTRL2_0 :: CPU_MASK_SET :: ubus_err_intr_mask [14:14] */
-#define BCHP_SWITCH_INTRL2_0_CPU_MASK_SET_ubus_err_intr_mask_MASK 0x00004000
-#define BCHP_SWITCH_INTRL2_0_CPU_MASK_SET_ubus_err_intr_mask_SHIFT 14
-#define BCHP_SWITCH_INTRL2_0_CPU_MASK_SET_ubus_err_intr_mask_DEFAULT 0x00000001
-
-/* SWITCH_INTRL2_0 :: CPU_MASK_SET :: gisb_err_intr_mask [13:13] */
-#define BCHP_SWITCH_INTRL2_0_CPU_MASK_SET_gisb_err_intr_mask_MASK 0x00002000
-#define BCHP_SWITCH_INTRL2_0_CPU_MASK_SET_gisb_err_intr_mask_SHIFT 13
-#define BCHP_SWITCH_INTRL2_0_CPU_MASK_SET_gisb_err_intr_mask_DEFAULT 0x00000001
-
-/* SWITCH_INTRL2_0 :: CPU_MASK_SET :: mdio_done_intr_mask [12:12] */
-#define BCHP_SWITCH_INTRL2_0_CPU_MASK_SET_mdio_done_intr_mask_MASK 0x00001000
-#define BCHP_SWITCH_INTRL2_0_CPU_MASK_SET_mdio_done_intr_mask_SHIFT 12
-#define BCHP_SWITCH_INTRL2_0_CPU_MASK_SET_mdio_done_intr_mask_DEFAULT 0x00000001
-
-/* SWITCH_INTRL2_0 :: CPU_MASK_SET :: mdio_err_intr_mask [11:11] */
-#define BCHP_SWITCH_INTRL2_0_CPU_MASK_SET_mdio_err_intr_mask_MASK 0x00000800
-#define BCHP_SWITCH_INTRL2_0_CPU_MASK_SET_mdio_err_intr_mask_SHIFT 11
-#define BCHP_SWITCH_INTRL2_0_CPU_MASK_SET_mdio_err_intr_mask_DEFAULT 0x00000001
-
-/* SWITCH_INTRL2_0 :: CPU_MASK_SET :: 1588_intr_mask [10:10] */
-#define BCHP_SWITCH_INTRL2_0_CPU_MASK_SET_1588_intr_mask_MASK 0x00000400
-#define BCHP_SWITCH_INTRL2_0_CPU_MASK_SET_1588_intr_mask_SHIFT 10
-#define BCHP_SWITCH_INTRL2_0_CPU_MASK_SET_1588_intr_mask_DEFAULT 0x00000001
-
-/* SWITCH_INTRL2_0 :: CPU_MASK_SET :: p7_cpu_wake_timer_intr_mask [09:09] */
-#define BCHP_SWITCH_INTRL2_0_CPU_MASK_SET_p7_cpu_wake_timer_intr_mask_MASK 0x00000200
-#define BCHP_SWITCH_INTRL2_0_CPU_MASK_SET_p7_cpu_wake_timer_intr_mask_SHIFT 9
-#define BCHP_SWITCH_INTRL2_0_CPU_MASK_SET_p7_cpu_wake_timer_intr_mask_DEFAULT 0x00000001
-
-/* SWITCH_INTRL2_0 :: CPU_MASK_SET :: p8_cpu_wake_timer_intr_mask [08:08] */
-#define BCHP_SWITCH_INTRL2_0_CPU_MASK_SET_p8_cpu_wake_timer_intr_mask_MASK 0x00000100
-#define BCHP_SWITCH_INTRL2_0_CPU_MASK_SET_p8_cpu_wake_timer_intr_mask_SHIFT 8
-#define BCHP_SWITCH_INTRL2_0_CPU_MASK_SET_p8_cpu_wake_timer_intr_mask_DEFAULT 0x00000001
-
-/* SWITCH_INTRL2_0 :: CPU_MASK_SET :: p5_cpu_wake_timer_intr_mask [07:07] */
-#define BCHP_SWITCH_INTRL2_0_CPU_MASK_SET_p5_cpu_wake_timer_intr_mask_MASK 0x00000080
-#define BCHP_SWITCH_INTRL2_0_CPU_MASK_SET_p5_cpu_wake_timer_intr_mask_SHIFT 7
-#define BCHP_SWITCH_INTRL2_0_CPU_MASK_SET_p5_cpu_wake_timer_intr_mask_DEFAULT 0x00000001
-
-/* SWITCH_INTRL2_0 :: CPU_MASK_SET :: eee_lpi_intr_mask [06:06] */
-#define BCHP_SWITCH_INTRL2_0_CPU_MASK_SET_eee_lpi_intr_mask_MASK 0x00000040
-#define BCHP_SWITCH_INTRL2_0_CPU_MASK_SET_eee_lpi_intr_mask_SHIFT 6
-#define BCHP_SWITCH_INTRL2_0_CPU_MASK_SET_eee_lpi_intr_mask_DEFAULT 0x00000001
-
-/* SWITCH_INTRL2_0 :: CPU_MASK_SET :: memory_double_err_intr_mask [05:05] */
-#define BCHP_SWITCH_INTRL2_0_CPU_MASK_SET_memory_double_err_intr_mask_MASK 0x00000020
-#define BCHP_SWITCH_INTRL2_0_CPU_MASK_SET_memory_double_err_intr_mask_SHIFT 5
-#define BCHP_SWITCH_INTRL2_0_CPU_MASK_SET_memory_double_err_intr_mask_DEFAULT 0x00000001
-
-/* SWITCH_INTRL2_0 :: CPU_MASK_SET :: p0_gphy_intr_mask [04:04] */
-#define BCHP_SWITCH_INTRL2_0_CPU_MASK_SET_p0_gphy_intr_mask_MASK 0x00000010
-#define BCHP_SWITCH_INTRL2_0_CPU_MASK_SET_p0_gphy_intr_mask_SHIFT 4
-#define BCHP_SWITCH_INTRL2_0_CPU_MASK_SET_p0_gphy_intr_mask_DEFAULT 0x00000001
-
-/* SWITCH_INTRL2_0 :: CPU_MASK_SET :: p0_energy_off_intr_mask [03:03] */
-#define BCHP_SWITCH_INTRL2_0_CPU_MASK_SET_p0_energy_off_intr_mask_MASK 0x00000008
-#define BCHP_SWITCH_INTRL2_0_CPU_MASK_SET_p0_energy_off_intr_mask_SHIFT 3
-#define BCHP_SWITCH_INTRL2_0_CPU_MASK_SET_p0_energy_off_intr_mask_DEFAULT 0x00000001
-
-/* SWITCH_INTRL2_0 :: CPU_MASK_SET :: p0_energy_on_intr_mask [02:02] */
-#define BCHP_SWITCH_INTRL2_0_CPU_MASK_SET_p0_energy_on_intr_mask_MASK 0x00000004
-#define BCHP_SWITCH_INTRL2_0_CPU_MASK_SET_p0_energy_on_intr_mask_SHIFT 2
-#define BCHP_SWITCH_INTRL2_0_CPU_MASK_SET_p0_energy_on_intr_mask_DEFAULT 0x00000001
-
-/* SWITCH_INTRL2_0 :: CPU_MASK_SET :: p0_link_down_intr_mask [01:01] */
-#define BCHP_SWITCH_INTRL2_0_CPU_MASK_SET_p0_link_down_intr_mask_MASK 0x00000002
-#define BCHP_SWITCH_INTRL2_0_CPU_MASK_SET_p0_link_down_intr_mask_SHIFT 1
-#define BCHP_SWITCH_INTRL2_0_CPU_MASK_SET_p0_link_down_intr_mask_DEFAULT 0x00000001
-
-/* SWITCH_INTRL2_0 :: CPU_MASK_SET :: p0_link_up_intr_mask [00:00] */
-#define BCHP_SWITCH_INTRL2_0_CPU_MASK_SET_p0_link_up_intr_mask_MASK 0x00000001
-#define BCHP_SWITCH_INTRL2_0_CPU_MASK_SET_p0_link_up_intr_mask_SHIFT 0
-#define BCHP_SWITCH_INTRL2_0_CPU_MASK_SET_p0_link_up_intr_mask_DEFAULT 0x00000001
-
-/***************************************************************************
- *CPU_MASK_CLEAR - CPU interrupt Mask Clear Register
- ***************************************************************************/
-/* SWITCH_INTRL2_0 :: CPU_MASK_CLEAR :: reserved0 [31:17] */
-#define BCHP_SWITCH_INTRL2_0_CPU_MASK_CLEAR_reserved0_MASK 0xfffe0000
-#define BCHP_SWITCH_INTRL2_0_CPU_MASK_CLEAR_reserved0_SHIFT 17
-
-/* SWITCH_INTRL2_0 :: CPU_MASK_CLEAR :: failover_off_intr_mask [16:16] */
-#define BCHP_SWITCH_INTRL2_0_CPU_MASK_CLEAR_failover_off_intr_mask_MASK 0x00010000
-#define BCHP_SWITCH_INTRL2_0_CPU_MASK_CLEAR_failover_off_intr_mask_SHIFT 16
-#define BCHP_SWITCH_INTRL2_0_CPU_MASK_CLEAR_failover_off_intr_mask_DEFAULT 0x00000001
-
-/* SWITCH_INTRL2_0 :: CPU_MASK_CLEAR :: failover_on_intr_mask [15:15] */
-#define BCHP_SWITCH_INTRL2_0_CPU_MASK_CLEAR_failover_on_intr_mask_MASK 0x00008000
-#define BCHP_SWITCH_INTRL2_0_CPU_MASK_CLEAR_failover_on_intr_mask_SHIFT 15
-#define BCHP_SWITCH_INTRL2_0_CPU_MASK_CLEAR_failover_on_intr_mask_DEFAULT 0x00000001
-
-/* SWITCH_INTRL2_0 :: CPU_MASK_CLEAR :: ubus_err_intr_mask [14:14] */
-#define BCHP_SWITCH_INTRL2_0_CPU_MASK_CLEAR_ubus_err_intr_mask_MASK 0x00004000
-#define BCHP_SWITCH_INTRL2_0_CPU_MASK_CLEAR_ubus_err_intr_mask_SHIFT 14
-#define BCHP_SWITCH_INTRL2_0_CPU_MASK_CLEAR_ubus_err_intr_mask_DEFAULT 0x00000001
-
-/* SWITCH_INTRL2_0 :: CPU_MASK_CLEAR :: gisb_err_intr_mask [13:13] */
-#define BCHP_SWITCH_INTRL2_0_CPU_MASK_CLEAR_gisb_err_intr_mask_MASK 0x00002000
-#define BCHP_SWITCH_INTRL2_0_CPU_MASK_CLEAR_gisb_err_intr_mask_SHIFT 13
-#define BCHP_SWITCH_INTRL2_0_CPU_MASK_CLEAR_gisb_err_intr_mask_DEFAULT 0x00000001
-
-/* SWITCH_INTRL2_0 :: CPU_MASK_CLEAR :: mdio_done_intr_mask [12:12] */
-#define BCHP_SWITCH_INTRL2_0_CPU_MASK_CLEAR_mdio_done_intr_mask_MASK 0x00001000
-#define BCHP_SWITCH_INTRL2_0_CPU_MASK_CLEAR_mdio_done_intr_mask_SHIFT 12
-#define BCHP_SWITCH_INTRL2_0_CPU_MASK_CLEAR_mdio_done_intr_mask_DEFAULT 0x00000001
-
-/* SWITCH_INTRL2_0 :: CPU_MASK_CLEAR :: mdio_err_intr_mask [11:11] */
-#define BCHP_SWITCH_INTRL2_0_CPU_MASK_CLEAR_mdio_err_intr_mask_MASK 0x00000800
-#define BCHP_SWITCH_INTRL2_0_CPU_MASK_CLEAR_mdio_err_intr_mask_SHIFT 11
-#define BCHP_SWITCH_INTRL2_0_CPU_MASK_CLEAR_mdio_err_intr_mask_DEFAULT 0x00000001
-
-/* SWITCH_INTRL2_0 :: CPU_MASK_CLEAR :: 1588_intr_mask [10:10] */
-#define BCHP_SWITCH_INTRL2_0_CPU_MASK_CLEAR_1588_intr_mask_MASK 0x00000400
-#define BCHP_SWITCH_INTRL2_0_CPU_MASK_CLEAR_1588_intr_mask_SHIFT 10
-#define BCHP_SWITCH_INTRL2_0_CPU_MASK_CLEAR_1588_intr_mask_DEFAULT 0x00000001
-
-/* SWITCH_INTRL2_0 :: CPU_MASK_CLEAR :: p7_cpu_wake_timer_intr_mask [09:09] */
-#define BCHP_SWITCH_INTRL2_0_CPU_MASK_CLEAR_p7_cpu_wake_timer_intr_mask_MASK 0x00000200
-#define BCHP_SWITCH_INTRL2_0_CPU_MASK_CLEAR_p7_cpu_wake_timer_intr_mask_SHIFT 9
-#define BCHP_SWITCH_INTRL2_0_CPU_MASK_CLEAR_p7_cpu_wake_timer_intr_mask_DEFAULT 0x00000001
-
-/* SWITCH_INTRL2_0 :: CPU_MASK_CLEAR :: p8_cpu_wake_timer_intr_mask [08:08] */
-#define BCHP_SWITCH_INTRL2_0_CPU_MASK_CLEAR_p8_cpu_wake_timer_intr_mask_MASK 0x00000100
-#define BCHP_SWITCH_INTRL2_0_CPU_MASK_CLEAR_p8_cpu_wake_timer_intr_mask_SHIFT 8
-#define BCHP_SWITCH_INTRL2_0_CPU_MASK_CLEAR_p8_cpu_wake_timer_intr_mask_DEFAULT 0x00000001
-
-/* SWITCH_INTRL2_0 :: CPU_MASK_CLEAR :: p5_cpu_wake_timer_intr_mask [07:07] */
-#define BCHP_SWITCH_INTRL2_0_CPU_MASK_CLEAR_p5_cpu_wake_timer_intr_mask_MASK 0x00000080
-#define BCHP_SWITCH_INTRL2_0_CPU_MASK_CLEAR_p5_cpu_wake_timer_intr_mask_SHIFT 7
-#define BCHP_SWITCH_INTRL2_0_CPU_MASK_CLEAR_p5_cpu_wake_timer_intr_mask_DEFAULT 0x00000001
-
-/* SWITCH_INTRL2_0 :: CPU_MASK_CLEAR :: eee_lpi_intr_mask [06:06] */
-#define BCHP_SWITCH_INTRL2_0_CPU_MASK_CLEAR_eee_lpi_intr_mask_MASK 0x00000040
-#define BCHP_SWITCH_INTRL2_0_CPU_MASK_CLEAR_eee_lpi_intr_mask_SHIFT 6
-#define BCHP_SWITCH_INTRL2_0_CPU_MASK_CLEAR_eee_lpi_intr_mask_DEFAULT 0x00000001
-
-/* SWITCH_INTRL2_0 :: CPU_MASK_CLEAR :: memory_double_err_intr_mask [05:05] */
-#define BCHP_SWITCH_INTRL2_0_CPU_MASK_CLEAR_memory_double_err_intr_mask_MASK 0x00000020
-#define BCHP_SWITCH_INTRL2_0_CPU_MASK_CLEAR_memory_double_err_intr_mask_SHIFT 5
-#define BCHP_SWITCH_INTRL2_0_CPU_MASK_CLEAR_memory_double_err_intr_mask_DEFAULT 0x00000001
-
-/* SWITCH_INTRL2_0 :: CPU_MASK_CLEAR :: p0_gphy_intr_mask [04:04] */
-#define BCHP_SWITCH_INTRL2_0_CPU_MASK_CLEAR_p0_gphy_intr_mask_MASK 0x00000010
-#define BCHP_SWITCH_INTRL2_0_CPU_MASK_CLEAR_p0_gphy_intr_mask_SHIFT 4
-#define BCHP_SWITCH_INTRL2_0_CPU_MASK_CLEAR_p0_gphy_intr_mask_DEFAULT 0x00000001
-
-/* SWITCH_INTRL2_0 :: CPU_MASK_CLEAR :: p0_energy_off_intr_mask [03:03] */
-#define BCHP_SWITCH_INTRL2_0_CPU_MASK_CLEAR_p0_energy_off_intr_mask_MASK 0x00000008
-#define BCHP_SWITCH_INTRL2_0_CPU_MASK_CLEAR_p0_energy_off_intr_mask_SHIFT 3
-#define BCHP_SWITCH_INTRL2_0_CPU_MASK_CLEAR_p0_energy_off_intr_mask_DEFAULT 0x00000001
-
-/* SWITCH_INTRL2_0 :: CPU_MASK_CLEAR :: p0_energy_on_intr_mask [02:02] */
-#define BCHP_SWITCH_INTRL2_0_CPU_MASK_CLEAR_p0_energy_on_intr_mask_MASK 0x00000004
-#define BCHP_SWITCH_INTRL2_0_CPU_MASK_CLEAR_p0_energy_on_intr_mask_SHIFT 2
-#define BCHP_SWITCH_INTRL2_0_CPU_MASK_CLEAR_p0_energy_on_intr_mask_DEFAULT 0x00000001
-
-/* SWITCH_INTRL2_0 :: CPU_MASK_CLEAR :: p0_link_down_intr_mask [01:01] */
-#define BCHP_SWITCH_INTRL2_0_CPU_MASK_CLEAR_p0_link_down_intr_mask_MASK 0x00000002
-#define BCHP_SWITCH_INTRL2_0_CPU_MASK_CLEAR_p0_link_down_intr_mask_SHIFT 1
-#define BCHP_SWITCH_INTRL2_0_CPU_MASK_CLEAR_p0_link_down_intr_mask_DEFAULT 0x00000001
-
-/* SWITCH_INTRL2_0 :: CPU_MASK_CLEAR :: p0_link_up_intr_mask [00:00] */
-#define BCHP_SWITCH_INTRL2_0_CPU_MASK_CLEAR_p0_link_up_intr_mask_MASK 0x00000001
-#define BCHP_SWITCH_INTRL2_0_CPU_MASK_CLEAR_p0_link_up_intr_mask_SHIFT 0
-#define BCHP_SWITCH_INTRL2_0_CPU_MASK_CLEAR_p0_link_up_intr_mask_DEFAULT 0x00000001
-
-/***************************************************************************
- *PCI_STATUS - PCI interrupt Status Register
- ***************************************************************************/
-/* SWITCH_INTRL2_0 :: PCI_STATUS :: reserved0 [31:17] */
-#define BCHP_SWITCH_INTRL2_0_PCI_STATUS_reserved0_MASK 0xfffe0000
-#define BCHP_SWITCH_INTRL2_0_PCI_STATUS_reserved0_SHIFT 17
-
-/* SWITCH_INTRL2_0 :: PCI_STATUS :: failover_off_intr [16:16] */
-#define BCHP_SWITCH_INTRL2_0_PCI_STATUS_failover_off_intr_MASK 0x00010000
-#define BCHP_SWITCH_INTRL2_0_PCI_STATUS_failover_off_intr_SHIFT 16
-#define BCHP_SWITCH_INTRL2_0_PCI_STATUS_failover_off_intr_DEFAULT 0x00000000
-
-/* SWITCH_INTRL2_0 :: PCI_STATUS :: failover_on_intr [15:15] */
-#define BCHP_SWITCH_INTRL2_0_PCI_STATUS_failover_on_intr_MASK 0x00008000
-#define BCHP_SWITCH_INTRL2_0_PCI_STATUS_failover_on_intr_SHIFT 15
-#define BCHP_SWITCH_INTRL2_0_PCI_STATUS_failover_on_intr_DEFAULT 0x00000000
-
-/* SWITCH_INTRL2_0 :: PCI_STATUS :: ubus_err_intr [14:14] */
-#define BCHP_SWITCH_INTRL2_0_PCI_STATUS_ubus_err_intr_MASK 0x00004000
-#define BCHP_SWITCH_INTRL2_0_PCI_STATUS_ubus_err_intr_SHIFT 14
-#define BCHP_SWITCH_INTRL2_0_PCI_STATUS_ubus_err_intr_DEFAULT 0x00000000
-
-/* SWITCH_INTRL2_0 :: PCI_STATUS :: gisb_err_intr [13:13] */
-#define BCHP_SWITCH_INTRL2_0_PCI_STATUS_gisb_err_intr_MASK 0x00002000
-#define BCHP_SWITCH_INTRL2_0_PCI_STATUS_gisb_err_intr_SHIFT 13
-#define BCHP_SWITCH_INTRL2_0_PCI_STATUS_gisb_err_intr_DEFAULT 0x00000000
-
-/* SWITCH_INTRL2_0 :: PCI_STATUS :: mdio_done_intr [12:12] */
-#define BCHP_SWITCH_INTRL2_0_PCI_STATUS_mdio_done_intr_MASK 0x00001000
-#define BCHP_SWITCH_INTRL2_0_PCI_STATUS_mdio_done_intr_SHIFT 12
-#define BCHP_SWITCH_INTRL2_0_PCI_STATUS_mdio_done_intr_DEFAULT 0x00000000
-
-/* SWITCH_INTRL2_0 :: PCI_STATUS :: mdio_err_up_intr [11:11] */
-#define BCHP_SWITCH_INTRL2_0_PCI_STATUS_mdio_err_up_intr_MASK 0x00000800
-#define BCHP_SWITCH_INTRL2_0_PCI_STATUS_mdio_err_up_intr_SHIFT 11
-#define BCHP_SWITCH_INTRL2_0_PCI_STATUS_mdio_err_up_intr_DEFAULT 0x00000000
-
-/* SWITCH_INTRL2_0 :: PCI_STATUS :: 1588_intr [10:10] */
-#define BCHP_SWITCH_INTRL2_0_PCI_STATUS_1588_intr_MASK 0x00000400
-#define BCHP_SWITCH_INTRL2_0_PCI_STATUS_1588_intr_SHIFT 10
-#define BCHP_SWITCH_INTRL2_0_PCI_STATUS_1588_intr_DEFAULT 0x00000000
-
-/* SWITCH_INTRL2_0 :: PCI_STATUS :: p7_cpu_wake_timer_intr [09:09] */
-#define BCHP_SWITCH_INTRL2_0_PCI_STATUS_p7_cpu_wake_timer_intr_MASK 0x00000200
-#define BCHP_SWITCH_INTRL2_0_PCI_STATUS_p7_cpu_wake_timer_intr_SHIFT 9
-#define BCHP_SWITCH_INTRL2_0_PCI_STATUS_p7_cpu_wake_timer_intr_DEFAULT 0x00000000
-
-/* SWITCH_INTRL2_0 :: PCI_STATUS :: p8_cpu_wake_timer_intr [08:08] */
-#define BCHP_SWITCH_INTRL2_0_PCI_STATUS_p8_cpu_wake_timer_intr_MASK 0x00000100
-#define BCHP_SWITCH_INTRL2_0_PCI_STATUS_p8_cpu_wake_timer_intr_SHIFT 8
-#define BCHP_SWITCH_INTRL2_0_PCI_STATUS_p8_cpu_wake_timer_intr_DEFAULT 0x00000000
-
-/* SWITCH_INTRL2_0 :: PCI_STATUS :: p5_cpu_wake_timer_intr [07:07] */
-#define BCHP_SWITCH_INTRL2_0_PCI_STATUS_p5_cpu_wake_timer_intr_MASK 0x00000080
-#define BCHP_SWITCH_INTRL2_0_PCI_STATUS_p5_cpu_wake_timer_intr_SHIFT 7
-#define BCHP_SWITCH_INTRL2_0_PCI_STATUS_p5_cpu_wake_timer_intr_DEFAULT 0x00000000
-
-/* SWITCH_INTRL2_0 :: PCI_STATUS :: eee_lpi_intr [06:06] */
-#define BCHP_SWITCH_INTRL2_0_PCI_STATUS_eee_lpi_intr_MASK 0x00000040
-#define BCHP_SWITCH_INTRL2_0_PCI_STATUS_eee_lpi_intr_SHIFT 6
-#define BCHP_SWITCH_INTRL2_0_PCI_STATUS_eee_lpi_intr_DEFAULT 0x00000000
-
-/* SWITCH_INTRL2_0 :: PCI_STATUS :: memory_double_err_intr [05:05] */
-#define BCHP_SWITCH_INTRL2_0_PCI_STATUS_memory_double_err_intr_MASK 0x00000020
-#define BCHP_SWITCH_INTRL2_0_PCI_STATUS_memory_double_err_intr_SHIFT 5
-#define BCHP_SWITCH_INTRL2_0_PCI_STATUS_memory_double_err_intr_DEFAULT 0x00000000
-
-/* SWITCH_INTRL2_0 :: PCI_STATUS :: p0_gphy_intr [04:04] */
-#define BCHP_SWITCH_INTRL2_0_PCI_STATUS_p0_gphy_intr_MASK 0x00000010
-#define BCHP_SWITCH_INTRL2_0_PCI_STATUS_p0_gphy_intr_SHIFT 4
-#define BCHP_SWITCH_INTRL2_0_PCI_STATUS_p0_gphy_intr_DEFAULT 0x00000000
-
-/* SWITCH_INTRL2_0 :: PCI_STATUS :: p0_energy_off_intr [03:03] */
-#define BCHP_SWITCH_INTRL2_0_PCI_STATUS_p0_energy_off_intr_MASK 0x00000008
-#define BCHP_SWITCH_INTRL2_0_PCI_STATUS_p0_energy_off_intr_SHIFT 3
-#define BCHP_SWITCH_INTRL2_0_PCI_STATUS_p0_energy_off_intr_DEFAULT 0x00000000
-
-/* SWITCH_INTRL2_0 :: PCI_STATUS :: p0_energy_on_intr [02:02] */
-#define BCHP_SWITCH_INTRL2_0_PCI_STATUS_p0_energy_on_intr_MASK 0x00000004
-#define BCHP_SWITCH_INTRL2_0_PCI_STATUS_p0_energy_on_intr_SHIFT 2
-#define BCHP_SWITCH_INTRL2_0_PCI_STATUS_p0_energy_on_intr_DEFAULT 0x00000000
-
-/* SWITCH_INTRL2_0 :: PCI_STATUS :: p0_link_down_intr [01:01] */
-#define BCHP_SWITCH_INTRL2_0_PCI_STATUS_p0_link_down_intr_MASK 0x00000002
-#define BCHP_SWITCH_INTRL2_0_PCI_STATUS_p0_link_down_intr_SHIFT 1
-#define BCHP_SWITCH_INTRL2_0_PCI_STATUS_p0_link_down_intr_DEFAULT 0x00000000
-
-/* SWITCH_INTRL2_0 :: PCI_STATUS :: p0_link_up_intr [00:00] */
-#define BCHP_SWITCH_INTRL2_0_PCI_STATUS_p0_link_up_intr_MASK 0x00000001
-#define BCHP_SWITCH_INTRL2_0_PCI_STATUS_p0_link_up_intr_SHIFT 0
-#define BCHP_SWITCH_INTRL2_0_PCI_STATUS_p0_link_up_intr_DEFAULT 0x00000000
-
-/***************************************************************************
- *PCI_SET - PCI interrupt Set Register
- ***************************************************************************/
-/* SWITCH_INTRL2_0 :: PCI_SET :: reserved0 [31:17] */
-#define BCHP_SWITCH_INTRL2_0_PCI_SET_reserved0_MASK 0xfffe0000
-#define BCHP_SWITCH_INTRL2_0_PCI_SET_reserved0_SHIFT 17
-
-/* SWITCH_INTRL2_0 :: PCI_SET :: failover_off_intr [16:16] */
-#define BCHP_SWITCH_INTRL2_0_PCI_SET_failover_off_intr_MASK 0x00010000
-#define BCHP_SWITCH_INTRL2_0_PCI_SET_failover_off_intr_SHIFT 16
-#define BCHP_SWITCH_INTRL2_0_PCI_SET_failover_off_intr_DEFAULT 0x00000000
-
-/* SWITCH_INTRL2_0 :: PCI_SET :: failover_on_intr [15:15] */
-#define BCHP_SWITCH_INTRL2_0_PCI_SET_failover_on_intr_MASK 0x00008000
-#define BCHP_SWITCH_INTRL2_0_PCI_SET_failover_on_intr_SHIFT 15
-#define BCHP_SWITCH_INTRL2_0_PCI_SET_failover_on_intr_DEFAULT 0x00000000
-
-/* SWITCH_INTRL2_0 :: PCI_SET :: ubus_err_intr [14:14] */
-#define BCHP_SWITCH_INTRL2_0_PCI_SET_ubus_err_intr_MASK 0x00004000
-#define BCHP_SWITCH_INTRL2_0_PCI_SET_ubus_err_intr_SHIFT 14
-#define BCHP_SWITCH_INTRL2_0_PCI_SET_ubus_err_intr_DEFAULT 0x00000000
-
-/* SWITCH_INTRL2_0 :: PCI_SET :: gisb_err_intr [13:13] */
-#define BCHP_SWITCH_INTRL2_0_PCI_SET_gisb_err_intr_MASK 0x00002000
-#define BCHP_SWITCH_INTRL2_0_PCI_SET_gisb_err_intr_SHIFT 13
-#define BCHP_SWITCH_INTRL2_0_PCI_SET_gisb_err_intr_DEFAULT 0x00000000
-
-/* SWITCH_INTRL2_0 :: PCI_SET :: mdio_done_intr [12:12] */
-#define BCHP_SWITCH_INTRL2_0_PCI_SET_mdio_done_intr_MASK 0x00001000
-#define BCHP_SWITCH_INTRL2_0_PCI_SET_mdio_done_intr_SHIFT 12
-#define BCHP_SWITCH_INTRL2_0_PCI_SET_mdio_done_intr_DEFAULT 0x00000000
-
-/* SWITCH_INTRL2_0 :: PCI_SET :: mdio_err_up_intr [11:11] */
-#define BCHP_SWITCH_INTRL2_0_PCI_SET_mdio_err_up_intr_MASK 0x00000800
-#define BCHP_SWITCH_INTRL2_0_PCI_SET_mdio_err_up_intr_SHIFT 11
-#define BCHP_SWITCH_INTRL2_0_PCI_SET_mdio_err_up_intr_DEFAULT 0x00000000
-
-/* SWITCH_INTRL2_0 :: PCI_SET :: 1588_intr [10:10] */
-#define BCHP_SWITCH_INTRL2_0_PCI_SET_1588_intr_MASK 0x00000400
-#define BCHP_SWITCH_INTRL2_0_PCI_SET_1588_intr_SHIFT 10
-#define BCHP_SWITCH_INTRL2_0_PCI_SET_1588_intr_DEFAULT 0x00000000
-
-/* SWITCH_INTRL2_0 :: PCI_SET :: p7_cpu_wake_timer_intr [09:09] */
-#define BCHP_SWITCH_INTRL2_0_PCI_SET_p7_cpu_wake_timer_intr_MASK 0x00000200
-#define BCHP_SWITCH_INTRL2_0_PCI_SET_p7_cpu_wake_timer_intr_SHIFT 9
-#define BCHP_SWITCH_INTRL2_0_PCI_SET_p7_cpu_wake_timer_intr_DEFAULT 0x00000000
-
-/* SWITCH_INTRL2_0 :: PCI_SET :: p8_cpu_wake_timer_intr [08:08] */
-#define BCHP_SWITCH_INTRL2_0_PCI_SET_p8_cpu_wake_timer_intr_MASK 0x00000100
-#define BCHP_SWITCH_INTRL2_0_PCI_SET_p8_cpu_wake_timer_intr_SHIFT 8
-#define BCHP_SWITCH_INTRL2_0_PCI_SET_p8_cpu_wake_timer_intr_DEFAULT 0x00000000
-
-/* SWITCH_INTRL2_0 :: PCI_SET :: p5_cpu_wake_timer_intr [07:07] */
-#define BCHP_SWITCH_INTRL2_0_PCI_SET_p5_cpu_wake_timer_intr_MASK 0x00000080
-#define BCHP_SWITCH_INTRL2_0_PCI_SET_p5_cpu_wake_timer_intr_SHIFT 7
-#define BCHP_SWITCH_INTRL2_0_PCI_SET_p5_cpu_wake_timer_intr_DEFAULT 0x00000000
-
-/* SWITCH_INTRL2_0 :: PCI_SET :: eee_lpi_intr [06:06] */
-#define BCHP_SWITCH_INTRL2_0_PCI_SET_eee_lpi_intr_MASK 0x00000040
-#define BCHP_SWITCH_INTRL2_0_PCI_SET_eee_lpi_intr_SHIFT 6
-#define BCHP_SWITCH_INTRL2_0_PCI_SET_eee_lpi_intr_DEFAULT 0x00000000
-
-/* SWITCH_INTRL2_0 :: PCI_SET :: memory_double_err_intr [05:05] */
-#define BCHP_SWITCH_INTRL2_0_PCI_SET_memory_double_err_intr_MASK 0x00000020
-#define BCHP_SWITCH_INTRL2_0_PCI_SET_memory_double_err_intr_SHIFT 5
-#define BCHP_SWITCH_INTRL2_0_PCI_SET_memory_double_err_intr_DEFAULT 0x00000000
-
-/* SWITCH_INTRL2_0 :: PCI_SET :: p0_gphy_intr [04:04] */
-#define BCHP_SWITCH_INTRL2_0_PCI_SET_p0_gphy_intr_MASK 0x00000010
-#define BCHP_SWITCH_INTRL2_0_PCI_SET_p0_gphy_intr_SHIFT 4
-#define BCHP_SWITCH_INTRL2_0_PCI_SET_p0_gphy_intr_DEFAULT 0x00000000
-
-/* SWITCH_INTRL2_0 :: PCI_SET :: p0_energy_off_intr [03:03] */
-#define BCHP_SWITCH_INTRL2_0_PCI_SET_p0_energy_off_intr_MASK 0x00000008
-#define BCHP_SWITCH_INTRL2_0_PCI_SET_p0_energy_off_intr_SHIFT 3
-#define BCHP_SWITCH_INTRL2_0_PCI_SET_p0_energy_off_intr_DEFAULT 0x00000000
-
-/* SWITCH_INTRL2_0 :: PCI_SET :: p0_energy_on_intr [02:02] */
-#define BCHP_SWITCH_INTRL2_0_PCI_SET_p0_energy_on_intr_MASK 0x00000004
-#define BCHP_SWITCH_INTRL2_0_PCI_SET_p0_energy_on_intr_SHIFT 2
-#define BCHP_SWITCH_INTRL2_0_PCI_SET_p0_energy_on_intr_DEFAULT 0x00000000
-
-/* SWITCH_INTRL2_0 :: PCI_SET :: p0_link_down_intr [01:01] */
-#define BCHP_SWITCH_INTRL2_0_PCI_SET_p0_link_down_intr_MASK 0x00000002
-#define BCHP_SWITCH_INTRL2_0_PCI_SET_p0_link_down_intr_SHIFT 1
-#define BCHP_SWITCH_INTRL2_0_PCI_SET_p0_link_down_intr_DEFAULT 0x00000000
-
-/* SWITCH_INTRL2_0 :: PCI_SET :: p0_link_up_intr [00:00] */
-#define BCHP_SWITCH_INTRL2_0_PCI_SET_p0_link_up_intr_MASK 0x00000001
-#define BCHP_SWITCH_INTRL2_0_PCI_SET_p0_link_up_intr_SHIFT 0
-#define BCHP_SWITCH_INTRL2_0_PCI_SET_p0_link_up_intr_DEFAULT 0x00000000
-
-/***************************************************************************
- *PCI_CLEAR - PCI interrupt Clear Register
- ***************************************************************************/
-/* SWITCH_INTRL2_0 :: PCI_CLEAR :: reserved0 [31:17] */
-#define BCHP_SWITCH_INTRL2_0_PCI_CLEAR_reserved0_MASK 0xfffe0000
-#define BCHP_SWITCH_INTRL2_0_PCI_CLEAR_reserved0_SHIFT 17
-
-/* SWITCH_INTRL2_0 :: PCI_CLEAR :: failover_off_intr [16:16] */
-#define BCHP_SWITCH_INTRL2_0_PCI_CLEAR_failover_off_intr_MASK 0x00010000
-#define BCHP_SWITCH_INTRL2_0_PCI_CLEAR_failover_off_intr_SHIFT 16
-#define BCHP_SWITCH_INTRL2_0_PCI_CLEAR_failover_off_intr_DEFAULT 0x00000000
-
-/* SWITCH_INTRL2_0 :: PCI_CLEAR :: failover_on_intr [15:15] */
-#define BCHP_SWITCH_INTRL2_0_PCI_CLEAR_failover_on_intr_MASK 0x00008000
-#define BCHP_SWITCH_INTRL2_0_PCI_CLEAR_failover_on_intr_SHIFT 15
-#define BCHP_SWITCH_INTRL2_0_PCI_CLEAR_failover_on_intr_DEFAULT 0x00000000
-
-/* SWITCH_INTRL2_0 :: PCI_CLEAR :: ubus_err_intr [14:14] */
-#define BCHP_SWITCH_INTRL2_0_PCI_CLEAR_ubus_err_intr_MASK 0x00004000
-#define BCHP_SWITCH_INTRL2_0_PCI_CLEAR_ubus_err_intr_SHIFT 14
-#define BCHP_SWITCH_INTRL2_0_PCI_CLEAR_ubus_err_intr_DEFAULT 0x00000000
-
-/* SWITCH_INTRL2_0 :: PCI_CLEAR :: gisb_err_intr [13:13] */
-#define BCHP_SWITCH_INTRL2_0_PCI_CLEAR_gisb_err_intr_MASK 0x00002000
-#define BCHP_SWITCH_INTRL2_0_PCI_CLEAR_gisb_err_intr_SHIFT 13
-#define BCHP_SWITCH_INTRL2_0_PCI_CLEAR_gisb_err_intr_DEFAULT 0x00000000
-
-/* SWITCH_INTRL2_0 :: PCI_CLEAR :: mdio_done_intr [12:12] */
-#define BCHP_SWITCH_INTRL2_0_PCI_CLEAR_mdio_done_intr_MASK 0x00001000
-#define BCHP_SWITCH_INTRL2_0_PCI_CLEAR_mdio_done_intr_SHIFT 12
-#define BCHP_SWITCH_INTRL2_0_PCI_CLEAR_mdio_done_intr_DEFAULT 0x00000000
-
-/* SWITCH_INTRL2_0 :: PCI_CLEAR :: mdio_err_up_intr [11:11] */
-#define BCHP_SWITCH_INTRL2_0_PCI_CLEAR_mdio_err_up_intr_MASK 0x00000800
-#define BCHP_SWITCH_INTRL2_0_PCI_CLEAR_mdio_err_up_intr_SHIFT 11
-#define BCHP_SWITCH_INTRL2_0_PCI_CLEAR_mdio_err_up_intr_DEFAULT 0x00000000
-
-/* SWITCH_INTRL2_0 :: PCI_CLEAR :: 1588_intr [10:10] */
-#define BCHP_SWITCH_INTRL2_0_PCI_CLEAR_1588_intr_MASK 0x00000400
-#define BCHP_SWITCH_INTRL2_0_PCI_CLEAR_1588_intr_SHIFT 10
-#define BCHP_SWITCH_INTRL2_0_PCI_CLEAR_1588_intr_DEFAULT 0x00000000
-
-/* SWITCH_INTRL2_0 :: PCI_CLEAR :: p7_cpu_wake_timer_intr [09:09] */
-#define BCHP_SWITCH_INTRL2_0_PCI_CLEAR_p7_cpu_wake_timer_intr_MASK 0x00000200
-#define BCHP_SWITCH_INTRL2_0_PCI_CLEAR_p7_cpu_wake_timer_intr_SHIFT 9
-#define BCHP_SWITCH_INTRL2_0_PCI_CLEAR_p7_cpu_wake_timer_intr_DEFAULT 0x00000000
-
-/* SWITCH_INTRL2_0 :: PCI_CLEAR :: p8_cpu_wake_timer_intr [08:08] */
-#define BCHP_SWITCH_INTRL2_0_PCI_CLEAR_p8_cpu_wake_timer_intr_MASK 0x00000100
-#define BCHP_SWITCH_INTRL2_0_PCI_CLEAR_p8_cpu_wake_timer_intr_SHIFT 8
-#define BCHP_SWITCH_INTRL2_0_PCI_CLEAR_p8_cpu_wake_timer_intr_DEFAULT 0x00000000
-
-/* SWITCH_INTRL2_0 :: PCI_CLEAR :: p5_cpu_wake_timer_intr [07:07] */
-#define BCHP_SWITCH_INTRL2_0_PCI_CLEAR_p5_cpu_wake_timer_intr_MASK 0x00000080
-#define BCHP_SWITCH_INTRL2_0_PCI_CLEAR_p5_cpu_wake_timer_intr_SHIFT 7
-#define BCHP_SWITCH_INTRL2_0_PCI_CLEAR_p5_cpu_wake_timer_intr_DEFAULT 0x00000000
-
-/* SWITCH_INTRL2_0 :: PCI_CLEAR :: eee_lpi_intr [06:06] */
-#define BCHP_SWITCH_INTRL2_0_PCI_CLEAR_eee_lpi_intr_MASK 0x00000040
-#define BCHP_SWITCH_INTRL2_0_PCI_CLEAR_eee_lpi_intr_SHIFT 6
-#define BCHP_SWITCH_INTRL2_0_PCI_CLEAR_eee_lpi_intr_DEFAULT 0x00000000
-
-/* SWITCH_INTRL2_0 :: PCI_CLEAR :: memory_double_err_intr [05:05] */
-#define BCHP_SWITCH_INTRL2_0_PCI_CLEAR_memory_double_err_intr_MASK 0x00000020
-#define BCHP_SWITCH_INTRL2_0_PCI_CLEAR_memory_double_err_intr_SHIFT 5
-#define BCHP_SWITCH_INTRL2_0_PCI_CLEAR_memory_double_err_intr_DEFAULT 0x00000000
-
-/* SWITCH_INTRL2_0 :: PCI_CLEAR :: p0_gphy_intr [04:04] */
-#define BCHP_SWITCH_INTRL2_0_PCI_CLEAR_p0_gphy_intr_MASK 0x00000010
-#define BCHP_SWITCH_INTRL2_0_PCI_CLEAR_p0_gphy_intr_SHIFT 4
-#define BCHP_SWITCH_INTRL2_0_PCI_CLEAR_p0_gphy_intr_DEFAULT 0x00000000
-
-/* SWITCH_INTRL2_0 :: PCI_CLEAR :: p0_energy_off_intr [03:03] */
-#define BCHP_SWITCH_INTRL2_0_PCI_CLEAR_p0_energy_off_intr_MASK 0x00000008
-#define BCHP_SWITCH_INTRL2_0_PCI_CLEAR_p0_energy_off_intr_SHIFT 3
-#define BCHP_SWITCH_INTRL2_0_PCI_CLEAR_p0_energy_off_intr_DEFAULT 0x00000000
-
-/* SWITCH_INTRL2_0 :: PCI_CLEAR :: p0_energy_on_intr [02:02] */
-#define BCHP_SWITCH_INTRL2_0_PCI_CLEAR_p0_energy_on_intr_MASK 0x00000004
-#define BCHP_SWITCH_INTRL2_0_PCI_CLEAR_p0_energy_on_intr_SHIFT 2
-#define BCHP_SWITCH_INTRL2_0_PCI_CLEAR_p0_energy_on_intr_DEFAULT 0x00000000
-
-/* SWITCH_INTRL2_0 :: PCI_CLEAR :: p0_link_down_intr [01:01] */
-#define BCHP_SWITCH_INTRL2_0_PCI_CLEAR_p0_link_down_intr_MASK 0x00000002
-#define BCHP_SWITCH_INTRL2_0_PCI_CLEAR_p0_link_down_intr_SHIFT 1
-#define BCHP_SWITCH_INTRL2_0_PCI_CLEAR_p0_link_down_intr_DEFAULT 0x00000000
-
-/* SWITCH_INTRL2_0 :: PCI_CLEAR :: p0_link_up_intr [00:00] */
-#define BCHP_SWITCH_INTRL2_0_PCI_CLEAR_p0_link_up_intr_MASK 0x00000001
-#define BCHP_SWITCH_INTRL2_0_PCI_CLEAR_p0_link_up_intr_SHIFT 0
-#define BCHP_SWITCH_INTRL2_0_PCI_CLEAR_p0_link_up_intr_DEFAULT 0x00000000
-
-/***************************************************************************
- *PCI_MASK_STATUS - PCI interrupt Mask Status Register
- ***************************************************************************/
-/* SWITCH_INTRL2_0 :: PCI_MASK_STATUS :: reserved0 [31:17] */
-#define BCHP_SWITCH_INTRL2_0_PCI_MASK_STATUS_reserved0_MASK 0xfffe0000
-#define BCHP_SWITCH_INTRL2_0_PCI_MASK_STATUS_reserved0_SHIFT 17
-
-/* SWITCH_INTRL2_0 :: PCI_MASK_STATUS :: failover_off_intr_mask [16:16] */
-#define BCHP_SWITCH_INTRL2_0_PCI_MASK_STATUS_failover_off_intr_mask_MASK 0x00010000
-#define BCHP_SWITCH_INTRL2_0_PCI_MASK_STATUS_failover_off_intr_mask_SHIFT 16
-#define BCHP_SWITCH_INTRL2_0_PCI_MASK_STATUS_failover_off_intr_mask_DEFAULT 0x00000001
-
-/* SWITCH_INTRL2_0 :: PCI_MASK_STATUS :: failover_on_intr_mask [15:15] */
-#define BCHP_SWITCH_INTRL2_0_PCI_MASK_STATUS_failover_on_intr_mask_MASK 0x00008000
-#define BCHP_SWITCH_INTRL2_0_PCI_MASK_STATUS_failover_on_intr_mask_SHIFT 15
-#define BCHP_SWITCH_INTRL2_0_PCI_MASK_STATUS_failover_on_intr_mask_DEFAULT 0x00000001
-
-/* SWITCH_INTRL2_0 :: PCI_MASK_STATUS :: ubus_err_intr_mask [14:14] */
-#define BCHP_SWITCH_INTRL2_0_PCI_MASK_STATUS_ubus_err_intr_mask_MASK 0x00004000
-#define BCHP_SWITCH_INTRL2_0_PCI_MASK_STATUS_ubus_err_intr_mask_SHIFT 14
-#define BCHP_SWITCH_INTRL2_0_PCI_MASK_STATUS_ubus_err_intr_mask_DEFAULT 0x00000001
-
-/* SWITCH_INTRL2_0 :: PCI_MASK_STATUS :: gisb_err_intr_mask [13:13] */
-#define BCHP_SWITCH_INTRL2_0_PCI_MASK_STATUS_gisb_err_intr_mask_MASK 0x00002000
-#define BCHP_SWITCH_INTRL2_0_PCI_MASK_STATUS_gisb_err_intr_mask_SHIFT 13
-#define BCHP_SWITCH_INTRL2_0_PCI_MASK_STATUS_gisb_err_intr_mask_DEFAULT 0x00000001
-
-/* SWITCH_INTRL2_0 :: PCI_MASK_STATUS :: mdio_done_intr_mask [12:12] */
-#define BCHP_SWITCH_INTRL2_0_PCI_MASK_STATUS_mdio_done_intr_mask_MASK 0x00001000
-#define BCHP_SWITCH_INTRL2_0_PCI_MASK_STATUS_mdio_done_intr_mask_SHIFT 12
-#define BCHP_SWITCH_INTRL2_0_PCI_MASK_STATUS_mdio_done_intr_mask_DEFAULT 0x00000001
-
-/* SWITCH_INTRL2_0 :: PCI_MASK_STATUS :: mdio_err_intr_mask [11:11] */
-#define BCHP_SWITCH_INTRL2_0_PCI_MASK_STATUS_mdio_err_intr_mask_MASK 0x00000800
-#define BCHP_SWITCH_INTRL2_0_PCI_MASK_STATUS_mdio_err_intr_mask_SHIFT 11
-#define BCHP_SWITCH_INTRL2_0_PCI_MASK_STATUS_mdio_err_intr_mask_DEFAULT 0x00000001
-
-/* SWITCH_INTRL2_0 :: PCI_MASK_STATUS :: 1588_intr_mask [10:10] */
-#define BCHP_SWITCH_INTRL2_0_PCI_MASK_STATUS_1588_intr_mask_MASK 0x00000400
-#define BCHP_SWITCH_INTRL2_0_PCI_MASK_STATUS_1588_intr_mask_SHIFT 10
-#define BCHP_SWITCH_INTRL2_0_PCI_MASK_STATUS_1588_intr_mask_DEFAULT 0x00000001
-
-/* SWITCH_INTRL2_0 :: PCI_MASK_STATUS :: p7_cpu_wake_timer_intr_mask [09:09] */
-#define BCHP_SWITCH_INTRL2_0_PCI_MASK_STATUS_p7_cpu_wake_timer_intr_mask_MASK 0x00000200
-#define BCHP_SWITCH_INTRL2_0_PCI_MASK_STATUS_p7_cpu_wake_timer_intr_mask_SHIFT 9
-#define BCHP_SWITCH_INTRL2_0_PCI_MASK_STATUS_p7_cpu_wake_timer_intr_mask_DEFAULT 0x00000001
-
-/* SWITCH_INTRL2_0 :: PCI_MASK_STATUS :: p8_cpu_wake_timer_intr_mask [08:08] */
-#define BCHP_SWITCH_INTRL2_0_PCI_MASK_STATUS_p8_cpu_wake_timer_intr_mask_MASK 0x00000100
-#define BCHP_SWITCH_INTRL2_0_PCI_MASK_STATUS_p8_cpu_wake_timer_intr_mask_SHIFT 8
-#define BCHP_SWITCH_INTRL2_0_PCI_MASK_STATUS_p8_cpu_wake_timer_intr_mask_DEFAULT 0x00000001
-
-/* SWITCH_INTRL2_0 :: PCI_MASK_STATUS :: p5_cpu_wake_timer_intr_mask [07:07] */
-#define BCHP_SWITCH_INTRL2_0_PCI_MASK_STATUS_p5_cpu_wake_timer_intr_mask_MASK 0x00000080
-#define BCHP_SWITCH_INTRL2_0_PCI_MASK_STATUS_p5_cpu_wake_timer_intr_mask_SHIFT 7
-#define BCHP_SWITCH_INTRL2_0_PCI_MASK_STATUS_p5_cpu_wake_timer_intr_mask_DEFAULT 0x00000001
-
-/* SWITCH_INTRL2_0 :: PCI_MASK_STATUS :: eee_lpi_intr_mask [06:06] */
-#define BCHP_SWITCH_INTRL2_0_PCI_MASK_STATUS_eee_lpi_intr_mask_MASK 0x00000040
-#define BCHP_SWITCH_INTRL2_0_PCI_MASK_STATUS_eee_lpi_intr_mask_SHIFT 6
-#define BCHP_SWITCH_INTRL2_0_PCI_MASK_STATUS_eee_lpi_intr_mask_DEFAULT 0x00000001
-
-/* SWITCH_INTRL2_0 :: PCI_MASK_STATUS :: memory_double_err_intr_mask [05:05] */
-#define BCHP_SWITCH_INTRL2_0_PCI_MASK_STATUS_memory_double_err_intr_mask_MASK 0x00000020
-#define BCHP_SWITCH_INTRL2_0_PCI_MASK_STATUS_memory_double_err_intr_mask_SHIFT 5
-#define BCHP_SWITCH_INTRL2_0_PCI_MASK_STATUS_memory_double_err_intr_mask_DEFAULT 0x00000001
-
-/* SWITCH_INTRL2_0 :: PCI_MASK_STATUS :: p0_gphy_intr_mask [04:04] */
-#define BCHP_SWITCH_INTRL2_0_PCI_MASK_STATUS_p0_gphy_intr_mask_MASK 0x00000010
-#define BCHP_SWITCH_INTRL2_0_PCI_MASK_STATUS_p0_gphy_intr_mask_SHIFT 4
-#define BCHP_SWITCH_INTRL2_0_PCI_MASK_STATUS_p0_gphy_intr_mask_DEFAULT 0x00000001
-
-/* SWITCH_INTRL2_0 :: PCI_MASK_STATUS :: p0_energy_off_intr_mask [03:03] */
-#define BCHP_SWITCH_INTRL2_0_PCI_MASK_STATUS_p0_energy_off_intr_mask_MASK 0x00000008
-#define BCHP_SWITCH_INTRL2_0_PCI_MASK_STATUS_p0_energy_off_intr_mask_SHIFT 3
-#define BCHP_SWITCH_INTRL2_0_PCI_MASK_STATUS_p0_energy_off_intr_mask_DEFAULT 0x00000001
-
-/* SWITCH_INTRL2_0 :: PCI_MASK_STATUS :: p0_energy_on_intr_mask [02:02] */
-#define BCHP_SWITCH_INTRL2_0_PCI_MASK_STATUS_p0_energy_on_intr_mask_MASK 0x00000004
-#define BCHP_SWITCH_INTRL2_0_PCI_MASK_STATUS_p0_energy_on_intr_mask_SHIFT 2
-#define BCHP_SWITCH_INTRL2_0_PCI_MASK_STATUS_p0_energy_on_intr_mask_DEFAULT 0x00000001
-
-/* SWITCH_INTRL2_0 :: PCI_MASK_STATUS :: p0_link_down_intr_mask [01:01] */
-#define BCHP_SWITCH_INTRL2_0_PCI_MASK_STATUS_p0_link_down_intr_mask_MASK 0x00000002
-#define BCHP_SWITCH_INTRL2_0_PCI_MASK_STATUS_p0_link_down_intr_mask_SHIFT 1
-#define BCHP_SWITCH_INTRL2_0_PCI_MASK_STATUS_p0_link_down_intr_mask_DEFAULT 0x00000001
-
-/* SWITCH_INTRL2_0 :: PCI_MASK_STATUS :: p0_link_up_intr_mask [00:00] */
-#define BCHP_SWITCH_INTRL2_0_PCI_MASK_STATUS_p0_link_up_intr_mask_MASK 0x00000001
-#define BCHP_SWITCH_INTRL2_0_PCI_MASK_STATUS_p0_link_up_intr_mask_SHIFT 0
-#define BCHP_SWITCH_INTRL2_0_PCI_MASK_STATUS_p0_link_up_intr_mask_DEFAULT 0x00000001
-
-/***************************************************************************
- *PCI_MASK_SET - PCI interrupt Mask Set Register
- ***************************************************************************/
-/* SWITCH_INTRL2_0 :: PCI_MASK_SET :: reserved0 [31:17] */
-#define BCHP_SWITCH_INTRL2_0_PCI_MASK_SET_reserved0_MASK 0xfffe0000
-#define BCHP_SWITCH_INTRL2_0_PCI_MASK_SET_reserved0_SHIFT 17
-
-/* SWITCH_INTRL2_0 :: PCI_MASK_SET :: failover_off_intr_mask [16:16] */
-#define BCHP_SWITCH_INTRL2_0_PCI_MASK_SET_failover_off_intr_mask_MASK 0x00010000
-#define BCHP_SWITCH_INTRL2_0_PCI_MASK_SET_failover_off_intr_mask_SHIFT 16
-#define BCHP_SWITCH_INTRL2_0_PCI_MASK_SET_failover_off_intr_mask_DEFAULT 0x00000001
-
-/* SWITCH_INTRL2_0 :: PCI_MASK_SET :: failover_on_intr_mask [15:15] */
-#define BCHP_SWITCH_INTRL2_0_PCI_MASK_SET_failover_on_intr_mask_MASK 0x00008000
-#define BCHP_SWITCH_INTRL2_0_PCI_MASK_SET_failover_on_intr_mask_SHIFT 15
-#define BCHP_SWITCH_INTRL2_0_PCI_MASK_SET_failover_on_intr_mask_DEFAULT 0x00000001
-
-/* SWITCH_INTRL2_0 :: PCI_MASK_SET :: ubus_err_intr_mask [14:14] */
-#define BCHP_SWITCH_INTRL2_0_PCI_MASK_SET_ubus_err_intr_mask_MASK 0x00004000
-#define BCHP_SWITCH_INTRL2_0_PCI_MASK_SET_ubus_err_intr_mask_SHIFT 14
-#define BCHP_SWITCH_INTRL2_0_PCI_MASK_SET_ubus_err_intr_mask_DEFAULT 0x00000001
-
-/* SWITCH_INTRL2_0 :: PCI_MASK_SET :: gisb_err_intr_mask [13:13] */
-#define BCHP_SWITCH_INTRL2_0_PCI_MASK_SET_gisb_err_intr_mask_MASK 0x00002000
-#define BCHP_SWITCH_INTRL2_0_PCI_MASK_SET_gisb_err_intr_mask_SHIFT 13
-#define BCHP_SWITCH_INTRL2_0_PCI_MASK_SET_gisb_err_intr_mask_DEFAULT 0x00000001
-
-/* SWITCH_INTRL2_0 :: PCI_MASK_SET :: mdio_done_intr_mask [12:12] */
-#define BCHP_SWITCH_INTRL2_0_PCI_MASK_SET_mdio_done_intr_mask_MASK 0x00001000
-#define BCHP_SWITCH_INTRL2_0_PCI_MASK_SET_mdio_done_intr_mask_SHIFT 12
-#define BCHP_SWITCH_INTRL2_0_PCI_MASK_SET_mdio_done_intr_mask_DEFAULT 0x00000001
-
-/* SWITCH_INTRL2_0 :: PCI_MASK_SET :: mdio_err_intr_mask [11:11] */
-#define BCHP_SWITCH_INTRL2_0_PCI_MASK_SET_mdio_err_intr_mask_MASK 0x00000800
-#define BCHP_SWITCH_INTRL2_0_PCI_MASK_SET_mdio_err_intr_mask_SHIFT 11
-#define BCHP_SWITCH_INTRL2_0_PCI_MASK_SET_mdio_err_intr_mask_DEFAULT 0x00000001
-
-/* SWITCH_INTRL2_0 :: PCI_MASK_SET :: 1588_intr_mask [10:10] */
-#define BCHP_SWITCH_INTRL2_0_PCI_MASK_SET_1588_intr_mask_MASK 0x00000400
-#define BCHP_SWITCH_INTRL2_0_PCI_MASK_SET_1588_intr_mask_SHIFT 10
-#define BCHP_SWITCH_INTRL2_0_PCI_MASK_SET_1588_intr_mask_DEFAULT 0x00000001
-
-/* SWITCH_INTRL2_0 :: PCI_MASK_SET :: p7_cpu_wake_timer_intr_mask [09:09] */
-#define BCHP_SWITCH_INTRL2_0_PCI_MASK_SET_p7_cpu_wake_timer_intr_mask_MASK 0x00000200
-#define BCHP_SWITCH_INTRL2_0_PCI_MASK_SET_p7_cpu_wake_timer_intr_mask_SHIFT 9
-#define BCHP_SWITCH_INTRL2_0_PCI_MASK_SET_p7_cpu_wake_timer_intr_mask_DEFAULT 0x00000001
-
-/* SWITCH_INTRL2_0 :: PCI_MASK_SET :: p8_cpu_wake_timer_intr_mask [08:08] */
-#define BCHP_SWITCH_INTRL2_0_PCI_MASK_SET_p8_cpu_wake_timer_intr_mask_MASK 0x00000100
-#define BCHP_SWITCH_INTRL2_0_PCI_MASK_SET_p8_cpu_wake_timer_intr_mask_SHIFT 8
-#define BCHP_SWITCH_INTRL2_0_PCI_MASK_SET_p8_cpu_wake_timer_intr_mask_DEFAULT 0x00000001
-
-/* SWITCH_INTRL2_0 :: PCI_MASK_SET :: p5_cpu_wake_timer_intr_mask [07:07] */
-#define BCHP_SWITCH_INTRL2_0_PCI_MASK_SET_p5_cpu_wake_timer_intr_mask_MASK 0x00000080
-#define BCHP_SWITCH_INTRL2_0_PCI_MASK_SET_p5_cpu_wake_timer_intr_mask_SHIFT 7
-#define BCHP_SWITCH_INTRL2_0_PCI_MASK_SET_p5_cpu_wake_timer_intr_mask_DEFAULT 0x00000001
-
-/* SWITCH_INTRL2_0 :: PCI_MASK_SET :: eee_lpi_intr_mask [06:06] */
-#define BCHP_SWITCH_INTRL2_0_PCI_MASK_SET_eee_lpi_intr_mask_MASK 0x00000040
-#define BCHP_SWITCH_INTRL2_0_PCI_MASK_SET_eee_lpi_intr_mask_SHIFT 6
-#define BCHP_SWITCH_INTRL2_0_PCI_MASK_SET_eee_lpi_intr_mask_DEFAULT 0x00000001
-
-/* SWITCH_INTRL2_0 :: PCI_MASK_SET :: memory_double_err_intr_mask [05:05] */
-#define BCHP_SWITCH_INTRL2_0_PCI_MASK_SET_memory_double_err_intr_mask_MASK 0x00000020
-#define BCHP_SWITCH_INTRL2_0_PCI_MASK_SET_memory_double_err_intr_mask_SHIFT 5
-#define BCHP_SWITCH_INTRL2_0_PCI_MASK_SET_memory_double_err_intr_mask_DEFAULT 0x00000001
-
-/* SWITCH_INTRL2_0 :: PCI_MASK_SET :: p0_gphy_intr_mask [04:04] */
-#define BCHP_SWITCH_INTRL2_0_PCI_MASK_SET_p0_gphy_intr_mask_MASK 0x00000010
-#define BCHP_SWITCH_INTRL2_0_PCI_MASK_SET_p0_gphy_intr_mask_SHIFT 4
-#define BCHP_SWITCH_INTRL2_0_PCI_MASK_SET_p0_gphy_intr_mask_DEFAULT 0x00000001
-
-/* SWITCH_INTRL2_0 :: PCI_MASK_SET :: p0_energy_off_intr_mask [03:03] */
-#define BCHP_SWITCH_INTRL2_0_PCI_MASK_SET_p0_energy_off_intr_mask_MASK 0x00000008
-#define BCHP_SWITCH_INTRL2_0_PCI_MASK_SET_p0_energy_off_intr_mask_SHIFT 3
-#define BCHP_SWITCH_INTRL2_0_PCI_MASK_SET_p0_energy_off_intr_mask_DEFAULT 0x00000001
-
-/* SWITCH_INTRL2_0 :: PCI_MASK_SET :: p0_energy_on_intr_mask [02:02] */
-#define BCHP_SWITCH_INTRL2_0_PCI_MASK_SET_p0_energy_on_intr_mask_MASK 0x00000004
-#define BCHP_SWITCH_INTRL2_0_PCI_MASK_SET_p0_energy_on_intr_mask_SHIFT 2
-#define BCHP_SWITCH_INTRL2_0_PCI_MASK_SET_p0_energy_on_intr_mask_DEFAULT 0x00000001
-
-/* SWITCH_INTRL2_0 :: PCI_MASK_SET :: p0_link_down_intr_mask [01:01] */
-#define BCHP_SWITCH_INTRL2_0_PCI_MASK_SET_p0_link_down_intr_mask_MASK 0x00000002
-#define BCHP_SWITCH_INTRL2_0_PCI_MASK_SET_p0_link_down_intr_mask_SHIFT 1
-#define BCHP_SWITCH_INTRL2_0_PCI_MASK_SET_p0_link_down_intr_mask_DEFAULT 0x00000001
-
-/* SWITCH_INTRL2_0 :: PCI_MASK_SET :: p0_link_up_intr_mask [00:00] */
-#define BCHP_SWITCH_INTRL2_0_PCI_MASK_SET_p0_link_up_intr_mask_MASK 0x00000001
-#define BCHP_SWITCH_INTRL2_0_PCI_MASK_SET_p0_link_up_intr_mask_SHIFT 0
-#define BCHP_SWITCH_INTRL2_0_PCI_MASK_SET_p0_link_up_intr_mask_DEFAULT 0x00000001
-
-/***************************************************************************
- *PCI_MASK_CLEAR - PCI interrupt Mask Clear Register
- ***************************************************************************/
-/* SWITCH_INTRL2_0 :: PCI_MASK_CLEAR :: reserved0 [31:17] */
-#define BCHP_SWITCH_INTRL2_0_PCI_MASK_CLEAR_reserved0_MASK 0xfffe0000
-#define BCHP_SWITCH_INTRL2_0_PCI_MASK_CLEAR_reserved0_SHIFT 17
-
-/* SWITCH_INTRL2_0 :: PCI_MASK_CLEAR :: failover_off_intr_mask [16:16] */
-#define BCHP_SWITCH_INTRL2_0_PCI_MASK_CLEAR_failover_off_intr_mask_MASK 0x00010000
-#define BCHP_SWITCH_INTRL2_0_PCI_MASK_CLEAR_failover_off_intr_mask_SHIFT 16
-#define BCHP_SWITCH_INTRL2_0_PCI_MASK_CLEAR_failover_off_intr_mask_DEFAULT 0x00000001
-
-/* SWITCH_INTRL2_0 :: PCI_MASK_CLEAR :: failover_on_intr_mask [15:15] */
-#define BCHP_SWITCH_INTRL2_0_PCI_MASK_CLEAR_failover_on_intr_mask_MASK 0x00008000
-#define BCHP_SWITCH_INTRL2_0_PCI_MASK_CLEAR_failover_on_intr_mask_SHIFT 15
-#define BCHP_SWITCH_INTRL2_0_PCI_MASK_CLEAR_failover_on_intr_mask_DEFAULT 0x00000001
-
-/* SWITCH_INTRL2_0 :: PCI_MASK_CLEAR :: ubus_err_intr_mask [14:14] */
-#define BCHP_SWITCH_INTRL2_0_PCI_MASK_CLEAR_ubus_err_intr_mask_MASK 0x00004000
-#define BCHP_SWITCH_INTRL2_0_PCI_MASK_CLEAR_ubus_err_intr_mask_SHIFT 14
-#define BCHP_SWITCH_INTRL2_0_PCI_MASK_CLEAR_ubus_err_intr_mask_DEFAULT 0x00000001
-
-/* SWITCH_INTRL2_0 :: PCI_MASK_CLEAR :: gisb_err_intr_mask [13:13] */
-#define BCHP_SWITCH_INTRL2_0_PCI_MASK_CLEAR_gisb_err_intr_mask_MASK 0x00002000
-#define BCHP_SWITCH_INTRL2_0_PCI_MASK_CLEAR_gisb_err_intr_mask_SHIFT 13
-#define BCHP_SWITCH_INTRL2_0_PCI_MASK_CLEAR_gisb_err_intr_mask_DEFAULT 0x00000001
-
-/* SWITCH_INTRL2_0 :: PCI_MASK_CLEAR :: mdio_done_intr_mask [12:12] */
-#define BCHP_SWITCH_INTRL2_0_PCI_MASK_CLEAR_mdio_done_intr_mask_MASK 0x00001000
-#define BCHP_SWITCH_INTRL2_0_PCI_MASK_CLEAR_mdio_done_intr_mask_SHIFT 12
-#define BCHP_SWITCH_INTRL2_0_PCI_MASK_CLEAR_mdio_done_intr_mask_DEFAULT 0x00000001
-
-/* SWITCH_INTRL2_0 :: PCI_MASK_CLEAR :: mdio_err_intr_mask [11:11] */
-#define BCHP_SWITCH_INTRL2_0_PCI_MASK_CLEAR_mdio_err_intr_mask_MASK 0x00000800
-#define BCHP_SWITCH_INTRL2_0_PCI_MASK_CLEAR_mdio_err_intr_mask_SHIFT 11
-#define BCHP_SWITCH_INTRL2_0_PCI_MASK_CLEAR_mdio_err_intr_mask_DEFAULT 0x00000001
-
-/* SWITCH_INTRL2_0 :: PCI_MASK_CLEAR :: 1588_intr_mask [10:10] */
-#define BCHP_SWITCH_INTRL2_0_PCI_MASK_CLEAR_1588_intr_mask_MASK 0x00000400
-#define BCHP_SWITCH_INTRL2_0_PCI_MASK_CLEAR_1588_intr_mask_SHIFT 10
-#define BCHP_SWITCH_INTRL2_0_PCI_MASK_CLEAR_1588_intr_mask_DEFAULT 0x00000001
-
-/* SWITCH_INTRL2_0 :: PCI_MASK_CLEAR :: p7_cpu_wake_timer_intr_mask [09:09] */
-#define BCHP_SWITCH_INTRL2_0_PCI_MASK_CLEAR_p7_cpu_wake_timer_intr_mask_MASK 0x00000200
-#define BCHP_SWITCH_INTRL2_0_PCI_MASK_CLEAR_p7_cpu_wake_timer_intr_mask_SHIFT 9
-#define BCHP_SWITCH_INTRL2_0_PCI_MASK_CLEAR_p7_cpu_wake_timer_intr_mask_DEFAULT 0x00000001
-
-/* SWITCH_INTRL2_0 :: PCI_MASK_CLEAR :: p8_cpu_wake_timer_intr_mask [08:08] */
-#define BCHP_SWITCH_INTRL2_0_PCI_MASK_CLEAR_p8_cpu_wake_timer_intr_mask_MASK 0x00000100
-#define BCHP_SWITCH_INTRL2_0_PCI_MASK_CLEAR_p8_cpu_wake_timer_intr_mask_SHIFT 8
-#define BCHP_SWITCH_INTRL2_0_PCI_MASK_CLEAR_p8_cpu_wake_timer_intr_mask_DEFAULT 0x00000001
-
-/* SWITCH_INTRL2_0 :: PCI_MASK_CLEAR :: p5_cpu_wake_timer_intr_mask [07:07] */
-#define BCHP_SWITCH_INTRL2_0_PCI_MASK_CLEAR_p5_cpu_wake_timer_intr_mask_MASK 0x00000080
-#define BCHP_SWITCH_INTRL2_0_PCI_MASK_CLEAR_p5_cpu_wake_timer_intr_mask_SHIFT 7
-#define BCHP_SWITCH_INTRL2_0_PCI_MASK_CLEAR_p5_cpu_wake_timer_intr_mask_DEFAULT 0x00000001
-
-/* SWITCH_INTRL2_0 :: PCI_MASK_CLEAR :: eee_lpi_intr_mask [06:06] */
-#define BCHP_SWITCH_INTRL2_0_PCI_MASK_CLEAR_eee_lpi_intr_mask_MASK 0x00000040
-#define BCHP_SWITCH_INTRL2_0_PCI_MASK_CLEAR_eee_lpi_intr_mask_SHIFT 6
-#define BCHP_SWITCH_INTRL2_0_PCI_MASK_CLEAR_eee_lpi_intr_mask_DEFAULT 0x00000001
-
-/* SWITCH_INTRL2_0 :: PCI_MASK_CLEAR :: memory_double_err_intr_mask [05:05] */
-#define BCHP_SWITCH_INTRL2_0_PCI_MASK_CLEAR_memory_double_err_intr_mask_MASK 0x00000020
-#define BCHP_SWITCH_INTRL2_0_PCI_MASK_CLEAR_memory_double_err_intr_mask_SHIFT 5
-#define BCHP_SWITCH_INTRL2_0_PCI_MASK_CLEAR_memory_double_err_intr_mask_DEFAULT 0x00000001
-
-/* SWITCH_INTRL2_0 :: PCI_MASK_CLEAR :: p0_gphy_intr_mask [04:04] */
-#define BCHP_SWITCH_INTRL2_0_PCI_MASK_CLEAR_p0_gphy_intr_mask_MASK 0x00000010
-#define BCHP_SWITCH_INTRL2_0_PCI_MASK_CLEAR_p0_gphy_intr_mask_SHIFT 4
-#define BCHP_SWITCH_INTRL2_0_PCI_MASK_CLEAR_p0_gphy_intr_mask_DEFAULT 0x00000001
-
-/* SWITCH_INTRL2_0 :: PCI_MASK_CLEAR :: p0_energy_off_intr_mask [03:03] */
-#define BCHP_SWITCH_INTRL2_0_PCI_MASK_CLEAR_p0_energy_off_intr_mask_MASK 0x00000008
-#define BCHP_SWITCH_INTRL2_0_PCI_MASK_CLEAR_p0_energy_off_intr_mask_SHIFT 3
-#define BCHP_SWITCH_INTRL2_0_PCI_MASK_CLEAR_p0_energy_off_intr_mask_DEFAULT 0x00000001
-
-/* SWITCH_INTRL2_0 :: PCI_MASK_CLEAR :: p0_energy_on_intr_mask [02:02] */
-#define BCHP_SWITCH_INTRL2_0_PCI_MASK_CLEAR_p0_energy_on_intr_mask_MASK 0x00000004
-#define BCHP_SWITCH_INTRL2_0_PCI_MASK_CLEAR_p0_energy_on_intr_mask_SHIFT 2
-#define BCHP_SWITCH_INTRL2_0_PCI_MASK_CLEAR_p0_energy_on_intr_mask_DEFAULT 0x00000001
-
-/* SWITCH_INTRL2_0 :: PCI_MASK_CLEAR :: p0_link_down_intr_mask [01:01] */
-#define BCHP_SWITCH_INTRL2_0_PCI_MASK_CLEAR_p0_link_down_intr_mask_MASK 0x00000002
-#define BCHP_SWITCH_INTRL2_0_PCI_MASK_CLEAR_p0_link_down_intr_mask_SHIFT 1
-#define BCHP_SWITCH_INTRL2_0_PCI_MASK_CLEAR_p0_link_down_intr_mask_DEFAULT 0x00000001
-
-/* SWITCH_INTRL2_0 :: PCI_MASK_CLEAR :: p0_link_up_intr_mask [00:00] */
-#define BCHP_SWITCH_INTRL2_0_PCI_MASK_CLEAR_p0_link_up_intr_mask_MASK 0x00000001
-#define BCHP_SWITCH_INTRL2_0_PCI_MASK_CLEAR_p0_link_up_intr_mask_SHIFT 0
-#define BCHP_SWITCH_INTRL2_0_PCI_MASK_CLEAR_p0_link_up_intr_mask_DEFAULT 0x00000001
-
-#endif /* #ifndef BCHP_SWITCH_INTRL2_0_H__ */
-
-/* End of File */
diff --git a/include/linux/brcmstb/7145a0/bchp_switch_intrl2_1.h b/include/linux/brcmstb/7145a0/bchp_switch_intrl2_1.h
deleted file mode 100644
index 7fc688d..0000000
--- a/include/linux/brcmstb/7145a0/bchp_switch_intrl2_1.h
+++ /dev/null
@@ -1,1944 +0,0 @@
-/***************************************************************************
- * Copyright (c) 1999-2013, Broadcom Corporation
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
- *
- * Module Description:
- * DO NOT EDIT THIS FILE DIRECTLY
- *
- * This module was generated magically with RDB from a source description
- * file. You must edit the source file for changes to be made to this file.
- *
- *
- * Date: Generated on Wed May 8 03:09:25 2013
- * MD5 Checksum d41d8cd98f00b204e9800998ecf8427e
- *
- * Compiled with: RDB Utility combo_header.pl
- * RDB Parser 3.0
- * unknown unknown
- * Perl Interpreter 5.008008
- * Operating System linux
- *
- * Revision History:
- *
- * $brcm_Log: $
- *
- ***************************************************************************/
-
-#ifndef BCHP_SWITCH_INTRL2_1_H__
-#define BCHP_SWITCH_INTRL2_1_H__
-
-/***************************************************************************
- *SWITCH_INTRL2_1
- ***************************************************************************/
-#define BCHP_SWITCH_INTRL2_1_CPU_STATUS 0x04e40380 /* CPU interrupt Status Register */
-#define BCHP_SWITCH_INTRL2_1_CPU_SET 0x04e40384 /* CPU interrupt Set Register */
-#define BCHP_SWITCH_INTRL2_1_CPU_CLEAR 0x04e40388 /* CPU interrupt Clear Register */
-#define BCHP_SWITCH_INTRL2_1_CPU_MASK_STATUS 0x04e4038c /* CPU interrupt Mask Status Register */
-#define BCHP_SWITCH_INTRL2_1_CPU_MASK_SET 0x04e40390 /* CPU interrupt Mask Set Register */
-#define BCHP_SWITCH_INTRL2_1_CPU_MASK_CLEAR 0x04e40394 /* CPU interrupt Mask Clear Register */
-#define BCHP_SWITCH_INTRL2_1_PCI_STATUS 0x04e40398 /* PCI interrupt Status Register */
-#define BCHP_SWITCH_INTRL2_1_PCI_SET 0x04e4039c /* PCI interrupt Set Register */
-#define BCHP_SWITCH_INTRL2_1_PCI_CLEAR 0x04e403a0 /* PCI interrupt Clear Register */
-#define BCHP_SWITCH_INTRL2_1_PCI_MASK_STATUS 0x04e403a4 /* PCI interrupt Mask Status Register */
-#define BCHP_SWITCH_INTRL2_1_PCI_MASK_SET 0x04e403a8 /* PCI interrupt Mask Set Register */
-#define BCHP_SWITCH_INTRL2_1_PCI_MASK_CLEAR 0x04e403ac /* PCI interrupt Mask Clear Register */
-
-/***************************************************************************
- *CPU_STATUS - CPU interrupt Status Register
- ***************************************************************************/
-/* SWITCH_INTRL2_1 :: CPU_STATUS :: reserved0 [31:30] */
-#define BCHP_SWITCH_INTRL2_1_CPU_STATUS_reserved0_MASK 0xc0000000
-#define BCHP_SWITCH_INTRL2_1_CPU_STATUS_reserved0_SHIFT 30
-
-/* SWITCH_INTRL2_1 :: CPU_STATUS :: p1_gphy_intr [29:29] */
-#define BCHP_SWITCH_INTRL2_1_CPU_STATUS_p1_gphy_intr_MASK 0x20000000
-#define BCHP_SWITCH_INTRL2_1_CPU_STATUS_p1_gphy_intr_SHIFT 29
-#define BCHP_SWITCH_INTRL2_1_CPU_STATUS_p1_gphy_intr_DEFAULT 0x00000000
-
-/* SWITCH_INTRL2_1 :: CPU_STATUS :: p1_energy_off_intr [28:28] */
-#define BCHP_SWITCH_INTRL2_1_CPU_STATUS_p1_energy_off_intr_MASK 0x10000000
-#define BCHP_SWITCH_INTRL2_1_CPU_STATUS_p1_energy_off_intr_SHIFT 28
-#define BCHP_SWITCH_INTRL2_1_CPU_STATUS_p1_energy_off_intr_DEFAULT 0x00000000
-
-/* SWITCH_INTRL2_1 :: CPU_STATUS :: p1_energy_on_intr [27:27] */
-#define BCHP_SWITCH_INTRL2_1_CPU_STATUS_p1_energy_on_intr_MASK 0x08000000
-#define BCHP_SWITCH_INTRL2_1_CPU_STATUS_p1_energy_on_intr_SHIFT 27
-#define BCHP_SWITCH_INTRL2_1_CPU_STATUS_p1_energy_on_intr_DEFAULT 0x00000000
-
-/* SWITCH_INTRL2_1 :: CPU_STATUS :: p1_link_down_intr [26:26] */
-#define BCHP_SWITCH_INTRL2_1_CPU_STATUS_p1_link_down_intr_MASK 0x04000000
-#define BCHP_SWITCH_INTRL2_1_CPU_STATUS_p1_link_down_intr_SHIFT 26
-#define BCHP_SWITCH_INTRL2_1_CPU_STATUS_p1_link_down_intr_DEFAULT 0x00000000
-
-/* SWITCH_INTRL2_1 :: CPU_STATUS :: p1_link_up_intr [25:25] */
-#define BCHP_SWITCH_INTRL2_1_CPU_STATUS_p1_link_up_intr_MASK 0x02000000
-#define BCHP_SWITCH_INTRL2_1_CPU_STATUS_p1_link_up_intr_SHIFT 25
-#define BCHP_SWITCH_INTRL2_1_CPU_STATUS_p1_link_up_intr_DEFAULT 0x00000000
-
-/* SWITCH_INTRL2_1 :: CPU_STATUS :: p2_gphy_intr [24:24] */
-#define BCHP_SWITCH_INTRL2_1_CPU_STATUS_p2_gphy_intr_MASK 0x01000000
-#define BCHP_SWITCH_INTRL2_1_CPU_STATUS_p2_gphy_intr_SHIFT 24
-#define BCHP_SWITCH_INTRL2_1_CPU_STATUS_p2_gphy_intr_DEFAULT 0x00000000
-
-/* SWITCH_INTRL2_1 :: CPU_STATUS :: p2_energy_off_intr [23:23] */
-#define BCHP_SWITCH_INTRL2_1_CPU_STATUS_p2_energy_off_intr_MASK 0x00800000
-#define BCHP_SWITCH_INTRL2_1_CPU_STATUS_p2_energy_off_intr_SHIFT 23
-#define BCHP_SWITCH_INTRL2_1_CPU_STATUS_p2_energy_off_intr_DEFAULT 0x00000000
-
-/* SWITCH_INTRL2_1 :: CPU_STATUS :: p2_energy_on_intr [22:22] */
-#define BCHP_SWITCH_INTRL2_1_CPU_STATUS_p2_energy_on_intr_MASK 0x00400000
-#define BCHP_SWITCH_INTRL2_1_CPU_STATUS_p2_energy_on_intr_SHIFT 22
-#define BCHP_SWITCH_INTRL2_1_CPU_STATUS_p2_energy_on_intr_DEFAULT 0x00000000
-
-/* SWITCH_INTRL2_1 :: CPU_STATUS :: p2_link_down_intr [21:21] */
-#define BCHP_SWITCH_INTRL2_1_CPU_STATUS_p2_link_down_intr_MASK 0x00200000
-#define BCHP_SWITCH_INTRL2_1_CPU_STATUS_p2_link_down_intr_SHIFT 21
-#define BCHP_SWITCH_INTRL2_1_CPU_STATUS_p2_link_down_intr_DEFAULT 0x00000000
-
-/* SWITCH_INTRL2_1 :: CPU_STATUS :: p2_link_up_intr [20:20] */
-#define BCHP_SWITCH_INTRL2_1_CPU_STATUS_p2_link_up_intr_MASK 0x00100000
-#define BCHP_SWITCH_INTRL2_1_CPU_STATUS_p2_link_up_intr_SHIFT 20
-#define BCHP_SWITCH_INTRL2_1_CPU_STATUS_p2_link_up_intr_DEFAULT 0x00000000
-
-/* SWITCH_INTRL2_1 :: CPU_STATUS :: p3_gphy_intr [19:19] */
-#define BCHP_SWITCH_INTRL2_1_CPU_STATUS_p3_gphy_intr_MASK 0x00080000
-#define BCHP_SWITCH_INTRL2_1_CPU_STATUS_p3_gphy_intr_SHIFT 19
-#define BCHP_SWITCH_INTRL2_1_CPU_STATUS_p3_gphy_intr_DEFAULT 0x00000000
-
-/* SWITCH_INTRL2_1 :: CPU_STATUS :: p3_energy_off_intr [18:18] */
-#define BCHP_SWITCH_INTRL2_1_CPU_STATUS_p3_energy_off_intr_MASK 0x00040000
-#define BCHP_SWITCH_INTRL2_1_CPU_STATUS_p3_energy_off_intr_SHIFT 18
-#define BCHP_SWITCH_INTRL2_1_CPU_STATUS_p3_energy_off_intr_DEFAULT 0x00000000
-
-/* SWITCH_INTRL2_1 :: CPU_STATUS :: p3_energy_on_intr [17:17] */
-#define BCHP_SWITCH_INTRL2_1_CPU_STATUS_p3_energy_on_intr_MASK 0x00020000
-#define BCHP_SWITCH_INTRL2_1_CPU_STATUS_p3_energy_on_intr_SHIFT 17
-#define BCHP_SWITCH_INTRL2_1_CPU_STATUS_p3_energy_on_intr_DEFAULT 0x00000000
-
-/* SWITCH_INTRL2_1 :: CPU_STATUS :: p3_link_down_intr [16:16] */
-#define BCHP_SWITCH_INTRL2_1_CPU_STATUS_p3_link_down_intr_MASK 0x00010000
-#define BCHP_SWITCH_INTRL2_1_CPU_STATUS_p3_link_down_intr_SHIFT 16
-#define BCHP_SWITCH_INTRL2_1_CPU_STATUS_p3_link_down_intr_DEFAULT 0x00000000
-
-/* SWITCH_INTRL2_1 :: CPU_STATUS :: p3_link_up_intr [15:15] */
-#define BCHP_SWITCH_INTRL2_1_CPU_STATUS_p3_link_up_intr_MASK 0x00008000
-#define BCHP_SWITCH_INTRL2_1_CPU_STATUS_p3_link_up_intr_SHIFT 15
-#define BCHP_SWITCH_INTRL2_1_CPU_STATUS_p3_link_up_intr_DEFAULT 0x00000000
-
-/* SWITCH_INTRL2_1 :: CPU_STATUS :: p4_gphy_intr [14:14] */
-#define BCHP_SWITCH_INTRL2_1_CPU_STATUS_p4_gphy_intr_MASK 0x00004000
-#define BCHP_SWITCH_INTRL2_1_CPU_STATUS_p4_gphy_intr_SHIFT 14
-#define BCHP_SWITCH_INTRL2_1_CPU_STATUS_p4_gphy_intr_DEFAULT 0x00000000
-
-/* SWITCH_INTRL2_1 :: CPU_STATUS :: p4_energy_off_intr [13:13] */
-#define BCHP_SWITCH_INTRL2_1_CPU_STATUS_p4_energy_off_intr_MASK 0x00002000
-#define BCHP_SWITCH_INTRL2_1_CPU_STATUS_p4_energy_off_intr_SHIFT 13
-#define BCHP_SWITCH_INTRL2_1_CPU_STATUS_p4_energy_off_intr_DEFAULT 0x00000000
-
-/* SWITCH_INTRL2_1 :: CPU_STATUS :: p4_energy_on_intr [12:12] */
-#define BCHP_SWITCH_INTRL2_1_CPU_STATUS_p4_energy_on_intr_MASK 0x00001000
-#define BCHP_SWITCH_INTRL2_1_CPU_STATUS_p4_energy_on_intr_SHIFT 12
-#define BCHP_SWITCH_INTRL2_1_CPU_STATUS_p4_energy_on_intr_DEFAULT 0x00000000
-
-/* SWITCH_INTRL2_1 :: CPU_STATUS :: p4_link_down_intr [11:11] */
-#define BCHP_SWITCH_INTRL2_1_CPU_STATUS_p4_link_down_intr_MASK 0x00000800
-#define BCHP_SWITCH_INTRL2_1_CPU_STATUS_p4_link_down_intr_SHIFT 11
-#define BCHP_SWITCH_INTRL2_1_CPU_STATUS_p4_link_down_intr_DEFAULT 0x00000000
-
-/* SWITCH_INTRL2_1 :: CPU_STATUS :: p4_link_up_intr [10:10] */
-#define BCHP_SWITCH_INTRL2_1_CPU_STATUS_p4_link_up_intr_MASK 0x00000400
-#define BCHP_SWITCH_INTRL2_1_CPU_STATUS_p4_link_up_intr_SHIFT 10
-#define BCHP_SWITCH_INTRL2_1_CPU_STATUS_p4_link_up_intr_DEFAULT 0x00000000
-
-/* SWITCH_INTRL2_1 :: CPU_STATUS :: p5_gphy_intr [09:09] */
-#define BCHP_SWITCH_INTRL2_1_CPU_STATUS_p5_gphy_intr_MASK 0x00000200
-#define BCHP_SWITCH_INTRL2_1_CPU_STATUS_p5_gphy_intr_SHIFT 9
-#define BCHP_SWITCH_INTRL2_1_CPU_STATUS_p5_gphy_intr_DEFAULT 0x00000000
-
-/* SWITCH_INTRL2_1 :: CPU_STATUS :: p5_energy_off_intr [08:08] */
-#define BCHP_SWITCH_INTRL2_1_CPU_STATUS_p5_energy_off_intr_MASK 0x00000100
-#define BCHP_SWITCH_INTRL2_1_CPU_STATUS_p5_energy_off_intr_SHIFT 8
-#define BCHP_SWITCH_INTRL2_1_CPU_STATUS_p5_energy_off_intr_DEFAULT 0x00000000
-
-/* SWITCH_INTRL2_1 :: CPU_STATUS :: p5_energy_on_intr [07:07] */
-#define BCHP_SWITCH_INTRL2_1_CPU_STATUS_p5_energy_on_intr_MASK 0x00000080
-#define BCHP_SWITCH_INTRL2_1_CPU_STATUS_p5_energy_on_intr_SHIFT 7
-#define BCHP_SWITCH_INTRL2_1_CPU_STATUS_p5_energy_on_intr_DEFAULT 0x00000000
-
-/* SWITCH_INTRL2_1 :: CPU_STATUS :: p5_link_down_intr [06:06] */
-#define BCHP_SWITCH_INTRL2_1_CPU_STATUS_p5_link_down_intr_MASK 0x00000040
-#define BCHP_SWITCH_INTRL2_1_CPU_STATUS_p5_link_down_intr_SHIFT 6
-#define BCHP_SWITCH_INTRL2_1_CPU_STATUS_p5_link_down_intr_DEFAULT 0x00000000
-
-/* SWITCH_INTRL2_1 :: CPU_STATUS :: p5_link_up_intr [05:05] */
-#define BCHP_SWITCH_INTRL2_1_CPU_STATUS_p5_link_up_intr_MASK 0x00000020
-#define BCHP_SWITCH_INTRL2_1_CPU_STATUS_p5_link_up_intr_SHIFT 5
-#define BCHP_SWITCH_INTRL2_1_CPU_STATUS_p5_link_up_intr_DEFAULT 0x00000000
-
-/* SWITCH_INTRL2_1 :: CPU_STATUS :: p7_gphy_intr [04:04] */
-#define BCHP_SWITCH_INTRL2_1_CPU_STATUS_p7_gphy_intr_MASK 0x00000010
-#define BCHP_SWITCH_INTRL2_1_CPU_STATUS_p7_gphy_intr_SHIFT 4
-#define BCHP_SWITCH_INTRL2_1_CPU_STATUS_p7_gphy_intr_DEFAULT 0x00000000
-
-/* SWITCH_INTRL2_1 :: CPU_STATUS :: p7_energy_off_intr [03:03] */
-#define BCHP_SWITCH_INTRL2_1_CPU_STATUS_p7_energy_off_intr_MASK 0x00000008
-#define BCHP_SWITCH_INTRL2_1_CPU_STATUS_p7_energy_off_intr_SHIFT 3
-#define BCHP_SWITCH_INTRL2_1_CPU_STATUS_p7_energy_off_intr_DEFAULT 0x00000000
-
-/* SWITCH_INTRL2_1 :: CPU_STATUS :: p7_energy_on_intr [02:02] */
-#define BCHP_SWITCH_INTRL2_1_CPU_STATUS_p7_energy_on_intr_MASK 0x00000004
-#define BCHP_SWITCH_INTRL2_1_CPU_STATUS_p7_energy_on_intr_SHIFT 2
-#define BCHP_SWITCH_INTRL2_1_CPU_STATUS_p7_energy_on_intr_DEFAULT 0x00000000
-
-/* SWITCH_INTRL2_1 :: CPU_STATUS :: p7_link_down_intr [01:01] */
-#define BCHP_SWITCH_INTRL2_1_CPU_STATUS_p7_link_down_intr_MASK 0x00000002
-#define BCHP_SWITCH_INTRL2_1_CPU_STATUS_p7_link_down_intr_SHIFT 1
-#define BCHP_SWITCH_INTRL2_1_CPU_STATUS_p7_link_down_intr_DEFAULT 0x00000000
-
-/* SWITCH_INTRL2_1 :: CPU_STATUS :: p7_link_up_intr [00:00] */
-#define BCHP_SWITCH_INTRL2_1_CPU_STATUS_p7_link_up_intr_MASK 0x00000001
-#define BCHP_SWITCH_INTRL2_1_CPU_STATUS_p7_link_up_intr_SHIFT 0
-#define BCHP_SWITCH_INTRL2_1_CPU_STATUS_p7_link_up_intr_DEFAULT 0x00000000
-
-/***************************************************************************
- *CPU_SET - CPU interrupt Set Register
- ***************************************************************************/
-/* SWITCH_INTRL2_1 :: CPU_SET :: reserved0 [31:30] */
-#define BCHP_SWITCH_INTRL2_1_CPU_SET_reserved0_MASK 0xc0000000
-#define BCHP_SWITCH_INTRL2_1_CPU_SET_reserved0_SHIFT 30
-
-/* SWITCH_INTRL2_1 :: CPU_SET :: p1_gphy_intr [29:29] */
-#define BCHP_SWITCH_INTRL2_1_CPU_SET_p1_gphy_intr_MASK 0x20000000
-#define BCHP_SWITCH_INTRL2_1_CPU_SET_p1_gphy_intr_SHIFT 29
-#define BCHP_SWITCH_INTRL2_1_CPU_SET_p1_gphy_intr_DEFAULT 0x00000000
-
-/* SWITCH_INTRL2_1 :: CPU_SET :: p1_energy_off_intr [28:28] */
-#define BCHP_SWITCH_INTRL2_1_CPU_SET_p1_energy_off_intr_MASK 0x10000000
-#define BCHP_SWITCH_INTRL2_1_CPU_SET_p1_energy_off_intr_SHIFT 28
-#define BCHP_SWITCH_INTRL2_1_CPU_SET_p1_energy_off_intr_DEFAULT 0x00000000
-
-/* SWITCH_INTRL2_1 :: CPU_SET :: p1_energy_on_intr [27:27] */
-#define BCHP_SWITCH_INTRL2_1_CPU_SET_p1_energy_on_intr_MASK 0x08000000
-#define BCHP_SWITCH_INTRL2_1_CPU_SET_p1_energy_on_intr_SHIFT 27
-#define BCHP_SWITCH_INTRL2_1_CPU_SET_p1_energy_on_intr_DEFAULT 0x00000000
-
-/* SWITCH_INTRL2_1 :: CPU_SET :: p1_link_down_intr [26:26] */
-#define BCHP_SWITCH_INTRL2_1_CPU_SET_p1_link_down_intr_MASK 0x04000000
-#define BCHP_SWITCH_INTRL2_1_CPU_SET_p1_link_down_intr_SHIFT 26
-#define BCHP_SWITCH_INTRL2_1_CPU_SET_p1_link_down_intr_DEFAULT 0x00000000
-
-/* SWITCH_INTRL2_1 :: CPU_SET :: p1_link_up_intr [25:25] */
-#define BCHP_SWITCH_INTRL2_1_CPU_SET_p1_link_up_intr_MASK 0x02000000
-#define BCHP_SWITCH_INTRL2_1_CPU_SET_p1_link_up_intr_SHIFT 25
-#define BCHP_SWITCH_INTRL2_1_CPU_SET_p1_link_up_intr_DEFAULT 0x00000000
-
-/* SWITCH_INTRL2_1 :: CPU_SET :: p2_gphy_intr [24:24] */
-#define BCHP_SWITCH_INTRL2_1_CPU_SET_p2_gphy_intr_MASK 0x01000000
-#define BCHP_SWITCH_INTRL2_1_CPU_SET_p2_gphy_intr_SHIFT 24
-#define BCHP_SWITCH_INTRL2_1_CPU_SET_p2_gphy_intr_DEFAULT 0x00000000
-
-/* SWITCH_INTRL2_1 :: CPU_SET :: p2_energy_off_intr [23:23] */
-#define BCHP_SWITCH_INTRL2_1_CPU_SET_p2_energy_off_intr_MASK 0x00800000
-#define BCHP_SWITCH_INTRL2_1_CPU_SET_p2_energy_off_intr_SHIFT 23
-#define BCHP_SWITCH_INTRL2_1_CPU_SET_p2_energy_off_intr_DEFAULT 0x00000000
-
-/* SWITCH_INTRL2_1 :: CPU_SET :: p2_energy_on_intr [22:22] */
-#define BCHP_SWITCH_INTRL2_1_CPU_SET_p2_energy_on_intr_MASK 0x00400000
-#define BCHP_SWITCH_INTRL2_1_CPU_SET_p2_energy_on_intr_SHIFT 22
-#define BCHP_SWITCH_INTRL2_1_CPU_SET_p2_energy_on_intr_DEFAULT 0x00000000
-
-/* SWITCH_INTRL2_1 :: CPU_SET :: p2_link_down_intr [21:21] */
-#define BCHP_SWITCH_INTRL2_1_CPU_SET_p2_link_down_intr_MASK 0x00200000
-#define BCHP_SWITCH_INTRL2_1_CPU_SET_p2_link_down_intr_SHIFT 21
-#define BCHP_SWITCH_INTRL2_1_CPU_SET_p2_link_down_intr_DEFAULT 0x00000000
-
-/* SWITCH_INTRL2_1 :: CPU_SET :: p2_link_up_intr [20:20] */
-#define BCHP_SWITCH_INTRL2_1_CPU_SET_p2_link_up_intr_MASK 0x00100000
-#define BCHP_SWITCH_INTRL2_1_CPU_SET_p2_link_up_intr_SHIFT 20
-#define BCHP_SWITCH_INTRL2_1_CPU_SET_p2_link_up_intr_DEFAULT 0x00000000
-
-/* SWITCH_INTRL2_1 :: CPU_SET :: p3_gphy_intr [19:19] */
-#define BCHP_SWITCH_INTRL2_1_CPU_SET_p3_gphy_intr_MASK 0x00080000
-#define BCHP_SWITCH_INTRL2_1_CPU_SET_p3_gphy_intr_SHIFT 19
-#define BCHP_SWITCH_INTRL2_1_CPU_SET_p3_gphy_intr_DEFAULT 0x00000000
-
-/* SWITCH_INTRL2_1 :: CPU_SET :: p3_energy_off_intr [18:18] */
-#define BCHP_SWITCH_INTRL2_1_CPU_SET_p3_energy_off_intr_MASK 0x00040000
-#define BCHP_SWITCH_INTRL2_1_CPU_SET_p3_energy_off_intr_SHIFT 18
-#define BCHP_SWITCH_INTRL2_1_CPU_SET_p3_energy_off_intr_DEFAULT 0x00000000
-
-/* SWITCH_INTRL2_1 :: CPU_SET :: p3_energy_on_intr [17:17] */
-#define BCHP_SWITCH_INTRL2_1_CPU_SET_p3_energy_on_intr_MASK 0x00020000
-#define BCHP_SWITCH_INTRL2_1_CPU_SET_p3_energy_on_intr_SHIFT 17
-#define BCHP_SWITCH_INTRL2_1_CPU_SET_p3_energy_on_intr_DEFAULT 0x00000000
-
-/* SWITCH_INTRL2_1 :: CPU_SET :: p3_link_down_intr [16:16] */
-#define BCHP_SWITCH_INTRL2_1_CPU_SET_p3_link_down_intr_MASK 0x00010000
-#define BCHP_SWITCH_INTRL2_1_CPU_SET_p3_link_down_intr_SHIFT 16
-#define BCHP_SWITCH_INTRL2_1_CPU_SET_p3_link_down_intr_DEFAULT 0x00000000
-
-/* SWITCH_INTRL2_1 :: CPU_SET :: p3_link_up_intr [15:15] */
-#define BCHP_SWITCH_INTRL2_1_CPU_SET_p3_link_up_intr_MASK 0x00008000
-#define BCHP_SWITCH_INTRL2_1_CPU_SET_p3_link_up_intr_SHIFT 15
-#define BCHP_SWITCH_INTRL2_1_CPU_SET_p3_link_up_intr_DEFAULT 0x00000000
-
-/* SWITCH_INTRL2_1 :: CPU_SET :: p4_gphy_intr [14:14] */
-#define BCHP_SWITCH_INTRL2_1_CPU_SET_p4_gphy_intr_MASK 0x00004000
-#define BCHP_SWITCH_INTRL2_1_CPU_SET_p4_gphy_intr_SHIFT 14
-#define BCHP_SWITCH_INTRL2_1_CPU_SET_p4_gphy_intr_DEFAULT 0x00000000
-
-/* SWITCH_INTRL2_1 :: CPU_SET :: p4_energy_off_intr [13:13] */
-#define BCHP_SWITCH_INTRL2_1_CPU_SET_p4_energy_off_intr_MASK 0x00002000
-#define BCHP_SWITCH_INTRL2_1_CPU_SET_p4_energy_off_intr_SHIFT 13
-#define BCHP_SWITCH_INTRL2_1_CPU_SET_p4_energy_off_intr_DEFAULT 0x00000000
-
-/* SWITCH_INTRL2_1 :: CPU_SET :: p4_energy_on_intr [12:12] */
-#define BCHP_SWITCH_INTRL2_1_CPU_SET_p4_energy_on_intr_MASK 0x00001000
-#define BCHP_SWITCH_INTRL2_1_CPU_SET_p4_energy_on_intr_SHIFT 12
-#define BCHP_SWITCH_INTRL2_1_CPU_SET_p4_energy_on_intr_DEFAULT 0x00000000
-
-/* SWITCH_INTRL2_1 :: CPU_SET :: p4_link_down_intr [11:11] */
-#define BCHP_SWITCH_INTRL2_1_CPU_SET_p4_link_down_intr_MASK 0x00000800
-#define BCHP_SWITCH_INTRL2_1_CPU_SET_p4_link_down_intr_SHIFT 11
-#define BCHP_SWITCH_INTRL2_1_CPU_SET_p4_link_down_intr_DEFAULT 0x00000000
-
-/* SWITCH_INTRL2_1 :: CPU_SET :: p4_link_up_intr [10:10] */
-#define BCHP_SWITCH_INTRL2_1_CPU_SET_p4_link_up_intr_MASK 0x00000400
-#define BCHP_SWITCH_INTRL2_1_CPU_SET_p4_link_up_intr_SHIFT 10
-#define BCHP_SWITCH_INTRL2_1_CPU_SET_p4_link_up_intr_DEFAULT 0x00000000
-
-/* SWITCH_INTRL2_1 :: CPU_SET :: p5_gphy_intr [09:09] */
-#define BCHP_SWITCH_INTRL2_1_CPU_SET_p5_gphy_intr_MASK 0x00000200
-#define BCHP_SWITCH_INTRL2_1_CPU_SET_p5_gphy_intr_SHIFT 9
-#define BCHP_SWITCH_INTRL2_1_CPU_SET_p5_gphy_intr_DEFAULT 0x00000000
-
-/* SWITCH_INTRL2_1 :: CPU_SET :: p5_energy_off_intr [08:08] */
-#define BCHP_SWITCH_INTRL2_1_CPU_SET_p5_energy_off_intr_MASK 0x00000100
-#define BCHP_SWITCH_INTRL2_1_CPU_SET_p5_energy_off_intr_SHIFT 8
-#define BCHP_SWITCH_INTRL2_1_CPU_SET_p5_energy_off_intr_DEFAULT 0x00000000
-
-/* SWITCH_INTRL2_1 :: CPU_SET :: p5_energy_on_intr [07:07] */
-#define BCHP_SWITCH_INTRL2_1_CPU_SET_p5_energy_on_intr_MASK 0x00000080
-#define BCHP_SWITCH_INTRL2_1_CPU_SET_p5_energy_on_intr_SHIFT 7
-#define BCHP_SWITCH_INTRL2_1_CPU_SET_p5_energy_on_intr_DEFAULT 0x00000000
-
-/* SWITCH_INTRL2_1 :: CPU_SET :: p5_link_down_intr [06:06] */
-#define BCHP_SWITCH_INTRL2_1_CPU_SET_p5_link_down_intr_MASK 0x00000040
-#define BCHP_SWITCH_INTRL2_1_CPU_SET_p5_link_down_intr_SHIFT 6
-#define BCHP_SWITCH_INTRL2_1_CPU_SET_p5_link_down_intr_DEFAULT 0x00000000
-
-/* SWITCH_INTRL2_1 :: CPU_SET :: p5_link_up_intr [05:05] */
-#define BCHP_SWITCH_INTRL2_1_CPU_SET_p5_link_up_intr_MASK 0x00000020
-#define BCHP_SWITCH_INTRL2_1_CPU_SET_p5_link_up_intr_SHIFT 5
-#define BCHP_SWITCH_INTRL2_1_CPU_SET_p5_link_up_intr_DEFAULT 0x00000000
-
-/* SWITCH_INTRL2_1 :: CPU_SET :: p7_gphy_intr [04:04] */
-#define BCHP_SWITCH_INTRL2_1_CPU_SET_p7_gphy_intr_MASK 0x00000010
-#define BCHP_SWITCH_INTRL2_1_CPU_SET_p7_gphy_intr_SHIFT 4
-#define BCHP_SWITCH_INTRL2_1_CPU_SET_p7_gphy_intr_DEFAULT 0x00000000
-
-/* SWITCH_INTRL2_1 :: CPU_SET :: p7_energy_off_intr [03:03] */
-#define BCHP_SWITCH_INTRL2_1_CPU_SET_p7_energy_off_intr_MASK 0x00000008
-#define BCHP_SWITCH_INTRL2_1_CPU_SET_p7_energy_off_intr_SHIFT 3
-#define BCHP_SWITCH_INTRL2_1_CPU_SET_p7_energy_off_intr_DEFAULT 0x00000000
-
-/* SWITCH_INTRL2_1 :: CPU_SET :: p7_energy_on_intr [02:02] */
-#define BCHP_SWITCH_INTRL2_1_CPU_SET_p7_energy_on_intr_MASK 0x00000004
-#define BCHP_SWITCH_INTRL2_1_CPU_SET_p7_energy_on_intr_SHIFT 2
-#define BCHP_SWITCH_INTRL2_1_CPU_SET_p7_energy_on_intr_DEFAULT 0x00000000
-
-/* SWITCH_INTRL2_1 :: CPU_SET :: p7_link_down_intr [01:01] */
-#define BCHP_SWITCH_INTRL2_1_CPU_SET_p7_link_down_intr_MASK 0x00000002
-#define BCHP_SWITCH_INTRL2_1_CPU_SET_p7_link_down_intr_SHIFT 1
-#define BCHP_SWITCH_INTRL2_1_CPU_SET_p7_link_down_intr_DEFAULT 0x00000000
-
-/* SWITCH_INTRL2_1 :: CPU_SET :: p7_link_up_intr [00:00] */
-#define BCHP_SWITCH_INTRL2_1_CPU_SET_p7_link_up_intr_MASK 0x00000001
-#define BCHP_SWITCH_INTRL2_1_CPU_SET_p7_link_up_intr_SHIFT 0
-#define BCHP_SWITCH_INTRL2_1_CPU_SET_p7_link_up_intr_DEFAULT 0x00000000
-
-/***************************************************************************
- *CPU_CLEAR - CPU interrupt Clear Register
- ***************************************************************************/
-/* SWITCH_INTRL2_1 :: CPU_CLEAR :: reserved0 [31:30] */
-#define BCHP_SWITCH_INTRL2_1_CPU_CLEAR_reserved0_MASK 0xc0000000
-#define BCHP_SWITCH_INTRL2_1_CPU_CLEAR_reserved0_SHIFT 30
-
-/* SWITCH_INTRL2_1 :: CPU_CLEAR :: p1_gphy_intr [29:29] */
-#define BCHP_SWITCH_INTRL2_1_CPU_CLEAR_p1_gphy_intr_MASK 0x20000000
-#define BCHP_SWITCH_INTRL2_1_CPU_CLEAR_p1_gphy_intr_SHIFT 29
-#define BCHP_SWITCH_INTRL2_1_CPU_CLEAR_p1_gphy_intr_DEFAULT 0x00000000
-
-/* SWITCH_INTRL2_1 :: CPU_CLEAR :: p1_energy_off_intr [28:28] */
-#define BCHP_SWITCH_INTRL2_1_CPU_CLEAR_p1_energy_off_intr_MASK 0x10000000
-#define BCHP_SWITCH_INTRL2_1_CPU_CLEAR_p1_energy_off_intr_SHIFT 28
-#define BCHP_SWITCH_INTRL2_1_CPU_CLEAR_p1_energy_off_intr_DEFAULT 0x00000000
-
-/* SWITCH_INTRL2_1 :: CPU_CLEAR :: p1_energy_on_intr [27:27] */
-#define BCHP_SWITCH_INTRL2_1_CPU_CLEAR_p1_energy_on_intr_MASK 0x08000000
-#define BCHP_SWITCH_INTRL2_1_CPU_CLEAR_p1_energy_on_intr_SHIFT 27
-#define BCHP_SWITCH_INTRL2_1_CPU_CLEAR_p1_energy_on_intr_DEFAULT 0x00000000
-
-/* SWITCH_INTRL2_1 :: CPU_CLEAR :: p1_link_down_intr [26:26] */
-#define BCHP_SWITCH_INTRL2_1_CPU_CLEAR_p1_link_down_intr_MASK 0x04000000
-#define BCHP_SWITCH_INTRL2_1_CPU_CLEAR_p1_link_down_intr_SHIFT 26
-#define BCHP_SWITCH_INTRL2_1_CPU_CLEAR_p1_link_down_intr_DEFAULT 0x00000000
-
-/* SWITCH_INTRL2_1 :: CPU_CLEAR :: p1_link_up_intr [25:25] */
-#define BCHP_SWITCH_INTRL2_1_CPU_CLEAR_p1_link_up_intr_MASK 0x02000000
-#define BCHP_SWITCH_INTRL2_1_CPU_CLEAR_p1_link_up_intr_SHIFT 25
-#define BCHP_SWITCH_INTRL2_1_CPU_CLEAR_p1_link_up_intr_DEFAULT 0x00000000
-
-/* SWITCH_INTRL2_1 :: CPU_CLEAR :: p2_gphy_intr [24:24] */
-#define BCHP_SWITCH_INTRL2_1_CPU_CLEAR_p2_gphy_intr_MASK 0x01000000
-#define BCHP_SWITCH_INTRL2_1_CPU_CLEAR_p2_gphy_intr_SHIFT 24
-#define BCHP_SWITCH_INTRL2_1_CPU_CLEAR_p2_gphy_intr_DEFAULT 0x00000000
-
-/* SWITCH_INTRL2_1 :: CPU_CLEAR :: p2_energy_off_intr [23:23] */
-#define BCHP_SWITCH_INTRL2_1_CPU_CLEAR_p2_energy_off_intr_MASK 0x00800000
-#define BCHP_SWITCH_INTRL2_1_CPU_CLEAR_p2_energy_off_intr_SHIFT 23
-#define BCHP_SWITCH_INTRL2_1_CPU_CLEAR_p2_energy_off_intr_DEFAULT 0x00000000
-
-/* SWITCH_INTRL2_1 :: CPU_CLEAR :: p2_energy_on_intr [22:22] */
-#define BCHP_SWITCH_INTRL2_1_CPU_CLEAR_p2_energy_on_intr_MASK 0x00400000
-#define BCHP_SWITCH_INTRL2_1_CPU_CLEAR_p2_energy_on_intr_SHIFT 22
-#define BCHP_SWITCH_INTRL2_1_CPU_CLEAR_p2_energy_on_intr_DEFAULT 0x00000000
-
-/* SWITCH_INTRL2_1 :: CPU_CLEAR :: p2_link_down_intr [21:21] */
-#define BCHP_SWITCH_INTRL2_1_CPU_CLEAR_p2_link_down_intr_MASK 0x00200000
-#define BCHP_SWITCH_INTRL2_1_CPU_CLEAR_p2_link_down_intr_SHIFT 21
-#define BCHP_SWITCH_INTRL2_1_CPU_CLEAR_p2_link_down_intr_DEFAULT 0x00000000
-
-/* SWITCH_INTRL2_1 :: CPU_CLEAR :: p2_link_up_intr [20:20] */
-#define BCHP_SWITCH_INTRL2_1_CPU_CLEAR_p2_link_up_intr_MASK 0x00100000
-#define BCHP_SWITCH_INTRL2_1_CPU_CLEAR_p2_link_up_intr_SHIFT 20
-#define BCHP_SWITCH_INTRL2_1_CPU_CLEAR_p2_link_up_intr_DEFAULT 0x00000000
-
-/* SWITCH_INTRL2_1 :: CPU_CLEAR :: p3_gphy_intr [19:19] */
-#define BCHP_SWITCH_INTRL2_1_CPU_CLEAR_p3_gphy_intr_MASK 0x00080000
-#define BCHP_SWITCH_INTRL2_1_CPU_CLEAR_p3_gphy_intr_SHIFT 19
-#define BCHP_SWITCH_INTRL2_1_CPU_CLEAR_p3_gphy_intr_DEFAULT 0x00000000
-
-/* SWITCH_INTRL2_1 :: CPU_CLEAR :: p3_energy_off_intr [18:18] */
-#define BCHP_SWITCH_INTRL2_1_CPU_CLEAR_p3_energy_off_intr_MASK 0x00040000
-#define BCHP_SWITCH_INTRL2_1_CPU_CLEAR_p3_energy_off_intr_SHIFT 18
-#define BCHP_SWITCH_INTRL2_1_CPU_CLEAR_p3_energy_off_intr_DEFAULT 0x00000000
-
-/* SWITCH_INTRL2_1 :: CPU_CLEAR :: p3_energy_on_intr [17:17] */
-#define BCHP_SWITCH_INTRL2_1_CPU_CLEAR_p3_energy_on_intr_MASK 0x00020000
-#define BCHP_SWITCH_INTRL2_1_CPU_CLEAR_p3_energy_on_intr_SHIFT 17
-#define BCHP_SWITCH_INTRL2_1_CPU_CLEAR_p3_energy_on_intr_DEFAULT 0x00000000
-
-/* SWITCH_INTRL2_1 :: CPU_CLEAR :: p3_link_down_intr [16:16] */
-#define BCHP_SWITCH_INTRL2_1_CPU_CLEAR_p3_link_down_intr_MASK 0x00010000
-#define BCHP_SWITCH_INTRL2_1_CPU_CLEAR_p3_link_down_intr_SHIFT 16
-#define BCHP_SWITCH_INTRL2_1_CPU_CLEAR_p3_link_down_intr_DEFAULT 0x00000000
-
-/* SWITCH_INTRL2_1 :: CPU_CLEAR :: p3_link_up_intr [15:15] */
-#define BCHP_SWITCH_INTRL2_1_CPU_CLEAR_p3_link_up_intr_MASK 0x00008000
-#define BCHP_SWITCH_INTRL2_1_CPU_CLEAR_p3_link_up_intr_SHIFT 15
-#define BCHP_SWITCH_INTRL2_1_CPU_CLEAR_p3_link_up_intr_DEFAULT 0x00000000
-
-/* SWITCH_INTRL2_1 :: CPU_CLEAR :: p4_gphy_intr [14:14] */
-#define BCHP_SWITCH_INTRL2_1_CPU_CLEAR_p4_gphy_intr_MASK 0x00004000
-#define BCHP_SWITCH_INTRL2_1_CPU_CLEAR_p4_gphy_intr_SHIFT 14
-#define BCHP_SWITCH_INTRL2_1_CPU_CLEAR_p4_gphy_intr_DEFAULT 0x00000000
-
-/* SWITCH_INTRL2_1 :: CPU_CLEAR :: p4_energy_off_intr [13:13] */
-#define BCHP_SWITCH_INTRL2_1_CPU_CLEAR_p4_energy_off_intr_MASK 0x00002000
-#define BCHP_SWITCH_INTRL2_1_CPU_CLEAR_p4_energy_off_intr_SHIFT 13
-#define BCHP_SWITCH_INTRL2_1_CPU_CLEAR_p4_energy_off_intr_DEFAULT 0x00000000
-
-/* SWITCH_INTRL2_1 :: CPU_CLEAR :: p4_energy_on_intr [12:12] */
-#define BCHP_SWITCH_INTRL2_1_CPU_CLEAR_p4_energy_on_intr_MASK 0x00001000
-#define BCHP_SWITCH_INTRL2_1_CPU_CLEAR_p4_energy_on_intr_SHIFT 12
-#define BCHP_SWITCH_INTRL2_1_CPU_CLEAR_p4_energy_on_intr_DEFAULT 0x00000000
-
-/* SWITCH_INTRL2_1 :: CPU_CLEAR :: p4_link_down_intr [11:11] */
-#define BCHP_SWITCH_INTRL2_1_CPU_CLEAR_p4_link_down_intr_MASK 0x00000800
-#define BCHP_SWITCH_INTRL2_1_CPU_CLEAR_p4_link_down_intr_SHIFT 11
-#define BCHP_SWITCH_INTRL2_1_CPU_CLEAR_p4_link_down_intr_DEFAULT 0x00000000
-
-/* SWITCH_INTRL2_1 :: CPU_CLEAR :: p4_link_up_intr [10:10] */
-#define BCHP_SWITCH_INTRL2_1_CPU_CLEAR_p4_link_up_intr_MASK 0x00000400
-#define BCHP_SWITCH_INTRL2_1_CPU_CLEAR_p4_link_up_intr_SHIFT 10
-#define BCHP_SWITCH_INTRL2_1_CPU_CLEAR_p4_link_up_intr_DEFAULT 0x00000000
-
-/* SWITCH_INTRL2_1 :: CPU_CLEAR :: p5_gphy_intr [09:09] */
-#define BCHP_SWITCH_INTRL2_1_CPU_CLEAR_p5_gphy_intr_MASK 0x00000200
-#define BCHP_SWITCH_INTRL2_1_CPU_CLEAR_p5_gphy_intr_SHIFT 9
-#define BCHP_SWITCH_INTRL2_1_CPU_CLEAR_p5_gphy_intr_DEFAULT 0x00000000
-
-/* SWITCH_INTRL2_1 :: CPU_CLEAR :: p5_energy_off_intr [08:08] */
-#define BCHP_SWITCH_INTRL2_1_CPU_CLEAR_p5_energy_off_intr_MASK 0x00000100
-#define BCHP_SWITCH_INTRL2_1_CPU_CLEAR_p5_energy_off_intr_SHIFT 8
-#define BCHP_SWITCH_INTRL2_1_CPU_CLEAR_p5_energy_off_intr_DEFAULT 0x00000000
-
-/* SWITCH_INTRL2_1 :: CPU_CLEAR :: p5_energy_on_intr [07:07] */
-#define BCHP_SWITCH_INTRL2_1_CPU_CLEAR_p5_energy_on_intr_MASK 0x00000080
-#define BCHP_SWITCH_INTRL2_1_CPU_CLEAR_p5_energy_on_intr_SHIFT 7
-#define BCHP_SWITCH_INTRL2_1_CPU_CLEAR_p5_energy_on_intr_DEFAULT 0x00000000
-
-/* SWITCH_INTRL2_1 :: CPU_CLEAR :: p5_link_down_intr [06:06] */
-#define BCHP_SWITCH_INTRL2_1_CPU_CLEAR_p5_link_down_intr_MASK 0x00000040
-#define BCHP_SWITCH_INTRL2_1_CPU_CLEAR_p5_link_down_intr_SHIFT 6
-#define BCHP_SWITCH_INTRL2_1_CPU_CLEAR_p5_link_down_intr_DEFAULT 0x00000000
-
-/* SWITCH_INTRL2_1 :: CPU_CLEAR :: p5_link_up_intr [05:05] */
-#define BCHP_SWITCH_INTRL2_1_CPU_CLEAR_p5_link_up_intr_MASK 0x00000020
-#define BCHP_SWITCH_INTRL2_1_CPU_CLEAR_p5_link_up_intr_SHIFT 5
-#define BCHP_SWITCH_INTRL2_1_CPU_CLEAR_p5_link_up_intr_DEFAULT 0x00000000
-
-/* SWITCH_INTRL2_1 :: CPU_CLEAR :: p7_gphy_intr [04:04] */
-#define BCHP_SWITCH_INTRL2_1_CPU_CLEAR_p7_gphy_intr_MASK 0x00000010
-#define BCHP_SWITCH_INTRL2_1_CPU_CLEAR_p7_gphy_intr_SHIFT 4
-#define BCHP_SWITCH_INTRL2_1_CPU_CLEAR_p7_gphy_intr_DEFAULT 0x00000000
-
-/* SWITCH_INTRL2_1 :: CPU_CLEAR :: p7_energy_off_intr [03:03] */
-#define BCHP_SWITCH_INTRL2_1_CPU_CLEAR_p7_energy_off_intr_MASK 0x00000008
-#define BCHP_SWITCH_INTRL2_1_CPU_CLEAR_p7_energy_off_intr_SHIFT 3
-#define BCHP_SWITCH_INTRL2_1_CPU_CLEAR_p7_energy_off_intr_DEFAULT 0x00000000
-
-/* SWITCH_INTRL2_1 :: CPU_CLEAR :: p7_energy_on_intr [02:02] */
-#define BCHP_SWITCH_INTRL2_1_CPU_CLEAR_p7_energy_on_intr_MASK 0x00000004
-#define BCHP_SWITCH_INTRL2_1_CPU_CLEAR_p7_energy_on_intr_SHIFT 2
-#define BCHP_SWITCH_INTRL2_1_CPU_CLEAR_p7_energy_on_intr_DEFAULT 0x00000000
-
-/* SWITCH_INTRL2_1 :: CPU_CLEAR :: p7_link_down_intr [01:01] */
-#define BCHP_SWITCH_INTRL2_1_CPU_CLEAR_p7_link_down_intr_MASK 0x00000002
-#define BCHP_SWITCH_INTRL2_1_CPU_CLEAR_p7_link_down_intr_SHIFT 1
-#define BCHP_SWITCH_INTRL2_1_CPU_CLEAR_p7_link_down_intr_DEFAULT 0x00000000
-
-/* SWITCH_INTRL2_1 :: CPU_CLEAR :: p7_link_up_intr [00:00] */
-#define BCHP_SWITCH_INTRL2_1_CPU_CLEAR_p7_link_up_intr_MASK 0x00000001
-#define BCHP_SWITCH_INTRL2_1_CPU_CLEAR_p7_link_up_intr_SHIFT 0
-#define BCHP_SWITCH_INTRL2_1_CPU_CLEAR_p7_link_up_intr_DEFAULT 0x00000000
-
-/***************************************************************************
- *CPU_MASK_STATUS - CPU interrupt Mask Status Register
- ***************************************************************************/
-/* SWITCH_INTRL2_1 :: CPU_MASK_STATUS :: reserved0 [31:30] */
-#define BCHP_SWITCH_INTRL2_1_CPU_MASK_STATUS_reserved0_MASK 0xc0000000
-#define BCHP_SWITCH_INTRL2_1_CPU_MASK_STATUS_reserved0_SHIFT 30
-
-/* SWITCH_INTRL2_1 :: CPU_MASK_STATUS :: p1_gphy_intr_mask [29:29] */
-#define BCHP_SWITCH_INTRL2_1_CPU_MASK_STATUS_p1_gphy_intr_mask_MASK 0x20000000
-#define BCHP_SWITCH_INTRL2_1_CPU_MASK_STATUS_p1_gphy_intr_mask_SHIFT 29
-#define BCHP_SWITCH_INTRL2_1_CPU_MASK_STATUS_p1_gphy_intr_mask_DEFAULT 0x00000001
-
-/* SWITCH_INTRL2_1 :: CPU_MASK_STATUS :: p1_energy_off_intr_mask [28:28] */
-#define BCHP_SWITCH_INTRL2_1_CPU_MASK_STATUS_p1_energy_off_intr_mask_MASK 0x10000000
-#define BCHP_SWITCH_INTRL2_1_CPU_MASK_STATUS_p1_energy_off_intr_mask_SHIFT 28
-#define BCHP_SWITCH_INTRL2_1_CPU_MASK_STATUS_p1_energy_off_intr_mask_DEFAULT 0x00000001
-
-/* SWITCH_INTRL2_1 :: CPU_MASK_STATUS :: p1_energy_on_intr_mask [27:27] */
-#define BCHP_SWITCH_INTRL2_1_CPU_MASK_STATUS_p1_energy_on_intr_mask_MASK 0x08000000
-#define BCHP_SWITCH_INTRL2_1_CPU_MASK_STATUS_p1_energy_on_intr_mask_SHIFT 27
-#define BCHP_SWITCH_INTRL2_1_CPU_MASK_STATUS_p1_energy_on_intr_mask_DEFAULT 0x00000001
-
-/* SWITCH_INTRL2_1 :: CPU_MASK_STATUS :: p1_link_down_intr_mask [26:26] */
-#define BCHP_SWITCH_INTRL2_1_CPU_MASK_STATUS_p1_link_down_intr_mask_MASK 0x04000000
-#define BCHP_SWITCH_INTRL2_1_CPU_MASK_STATUS_p1_link_down_intr_mask_SHIFT 26
-#define BCHP_SWITCH_INTRL2_1_CPU_MASK_STATUS_p1_link_down_intr_mask_DEFAULT 0x00000001
-
-/* SWITCH_INTRL2_1 :: CPU_MASK_STATUS :: p1_link_up_intr_mask [25:25] */
-#define BCHP_SWITCH_INTRL2_1_CPU_MASK_STATUS_p1_link_up_intr_mask_MASK 0x02000000
-#define BCHP_SWITCH_INTRL2_1_CPU_MASK_STATUS_p1_link_up_intr_mask_SHIFT 25
-#define BCHP_SWITCH_INTRL2_1_CPU_MASK_STATUS_p1_link_up_intr_mask_DEFAULT 0x00000001
-
-/* SWITCH_INTRL2_1 :: CPU_MASK_STATUS :: p2_gphy_intr_mask [24:24] */
-#define BCHP_SWITCH_INTRL2_1_CPU_MASK_STATUS_p2_gphy_intr_mask_MASK 0x01000000
-#define BCHP_SWITCH_INTRL2_1_CPU_MASK_STATUS_p2_gphy_intr_mask_SHIFT 24
-#define BCHP_SWITCH_INTRL2_1_CPU_MASK_STATUS_p2_gphy_intr_mask_DEFAULT 0x00000001
-
-/* SWITCH_INTRL2_1 :: CPU_MASK_STATUS :: p2_energy_off_intr_mask [23:23] */
-#define BCHP_SWITCH_INTRL2_1_CPU_MASK_STATUS_p2_energy_off_intr_mask_MASK 0x00800000
-#define BCHP_SWITCH_INTRL2_1_CPU_MASK_STATUS_p2_energy_off_intr_mask_SHIFT 23
-#define BCHP_SWITCH_INTRL2_1_CPU_MASK_STATUS_p2_energy_off_intr_mask_DEFAULT 0x00000001
-
-/* SWITCH_INTRL2_1 :: CPU_MASK_STATUS :: p2_energy_on_intr_mask [22:22] */
-#define BCHP_SWITCH_INTRL2_1_CPU_MASK_STATUS_p2_energy_on_intr_mask_MASK 0x00400000
-#define BCHP_SWITCH_INTRL2_1_CPU_MASK_STATUS_p2_energy_on_intr_mask_SHIFT 22
-#define BCHP_SWITCH_INTRL2_1_CPU_MASK_STATUS_p2_energy_on_intr_mask_DEFAULT 0x00000001
-
-/* SWITCH_INTRL2_1 :: CPU_MASK_STATUS :: p2_link_down_intr_mask [21:21] */
-#define BCHP_SWITCH_INTRL2_1_CPU_MASK_STATUS_p2_link_down_intr_mask_MASK 0x00200000
-#define BCHP_SWITCH_INTRL2_1_CPU_MASK_STATUS_p2_link_down_intr_mask_SHIFT 21
-#define BCHP_SWITCH_INTRL2_1_CPU_MASK_STATUS_p2_link_down_intr_mask_DEFAULT 0x00000001
-
-/* SWITCH_INTRL2_1 :: CPU_MASK_STATUS :: p2_link_up_intr_mask [20:20] */
-#define BCHP_SWITCH_INTRL2_1_CPU_MASK_STATUS_p2_link_up_intr_mask_MASK 0x00100000
-#define BCHP_SWITCH_INTRL2_1_CPU_MASK_STATUS_p2_link_up_intr_mask_SHIFT 20
-#define BCHP_SWITCH_INTRL2_1_CPU_MASK_STATUS_p2_link_up_intr_mask_DEFAULT 0x00000001
-
-/* SWITCH_INTRL2_1 :: CPU_MASK_STATUS :: p3_gphy_intr_mask [19:19] */
-#define BCHP_SWITCH_INTRL2_1_CPU_MASK_STATUS_p3_gphy_intr_mask_MASK 0x00080000
-#define BCHP_SWITCH_INTRL2_1_CPU_MASK_STATUS_p3_gphy_intr_mask_SHIFT 19
-#define BCHP_SWITCH_INTRL2_1_CPU_MASK_STATUS_p3_gphy_intr_mask_DEFAULT 0x00000001
-
-/* SWITCH_INTRL2_1 :: CPU_MASK_STATUS :: p3_energy_off_intr_mask [18:18] */
-#define BCHP_SWITCH_INTRL2_1_CPU_MASK_STATUS_p3_energy_off_intr_mask_MASK 0x00040000
-#define BCHP_SWITCH_INTRL2_1_CPU_MASK_STATUS_p3_energy_off_intr_mask_SHIFT 18
-#define BCHP_SWITCH_INTRL2_1_CPU_MASK_STATUS_p3_energy_off_intr_mask_DEFAULT 0x00000001
-
-/* SWITCH_INTRL2_1 :: CPU_MASK_STATUS :: p3_energy_on_intr_mask [17:17] */
-#define BCHP_SWITCH_INTRL2_1_CPU_MASK_STATUS_p3_energy_on_intr_mask_MASK 0x00020000
-#define BCHP_SWITCH_INTRL2_1_CPU_MASK_STATUS_p3_energy_on_intr_mask_SHIFT 17
-#define BCHP_SWITCH_INTRL2_1_CPU_MASK_STATUS_p3_energy_on_intr_mask_DEFAULT 0x00000001
-
-/* SWITCH_INTRL2_1 :: CPU_MASK_STATUS :: p3_link_down_intr_mask [16:16] */
-#define BCHP_SWITCH_INTRL2_1_CPU_MASK_STATUS_p3_link_down_intr_mask_MASK 0x00010000
-#define BCHP_SWITCH_INTRL2_1_CPU_MASK_STATUS_p3_link_down_intr_mask_SHIFT 16
-#define BCHP_SWITCH_INTRL2_1_CPU_MASK_STATUS_p3_link_down_intr_mask_DEFAULT 0x00000001
-
-/* SWITCH_INTRL2_1 :: CPU_MASK_STATUS :: p3_link_up_intr_mask [15:15] */
-#define BCHP_SWITCH_INTRL2_1_CPU_MASK_STATUS_p3_link_up_intr_mask_MASK 0x00008000
-#define BCHP_SWITCH_INTRL2_1_CPU_MASK_STATUS_p3_link_up_intr_mask_SHIFT 15
-#define BCHP_SWITCH_INTRL2_1_CPU_MASK_STATUS_p3_link_up_intr_mask_DEFAULT 0x00000001
-
-/* SWITCH_INTRL2_1 :: CPU_MASK_STATUS :: p4_gphy_intr_mask [14:14] */
-#define BCHP_SWITCH_INTRL2_1_CPU_MASK_STATUS_p4_gphy_intr_mask_MASK 0x00004000
-#define BCHP_SWITCH_INTRL2_1_CPU_MASK_STATUS_p4_gphy_intr_mask_SHIFT 14
-#define BCHP_SWITCH_INTRL2_1_CPU_MASK_STATUS_p4_gphy_intr_mask_DEFAULT 0x00000001
-
-/* SWITCH_INTRL2_1 :: CPU_MASK_STATUS :: p4_energy_off_intr_mask [13:13] */
-#define BCHP_SWITCH_INTRL2_1_CPU_MASK_STATUS_p4_energy_off_intr_mask_MASK 0x00002000
-#define BCHP_SWITCH_INTRL2_1_CPU_MASK_STATUS_p4_energy_off_intr_mask_SHIFT 13
-#define BCHP_SWITCH_INTRL2_1_CPU_MASK_STATUS_p4_energy_off_intr_mask_DEFAULT 0x00000001
-
-/* SWITCH_INTRL2_1 :: CPU_MASK_STATUS :: p4_energy_on_intr_mask [12:12] */
-#define BCHP_SWITCH_INTRL2_1_CPU_MASK_STATUS_p4_energy_on_intr_mask_MASK 0x00001000
-#define BCHP_SWITCH_INTRL2_1_CPU_MASK_STATUS_p4_energy_on_intr_mask_SHIFT 12
-#define BCHP_SWITCH_INTRL2_1_CPU_MASK_STATUS_p4_energy_on_intr_mask_DEFAULT 0x00000001
-
-/* SWITCH_INTRL2_1 :: CPU_MASK_STATUS :: p4_link_down_intr_mask [11:11] */
-#define BCHP_SWITCH_INTRL2_1_CPU_MASK_STATUS_p4_link_down_intr_mask_MASK 0x00000800
-#define BCHP_SWITCH_INTRL2_1_CPU_MASK_STATUS_p4_link_down_intr_mask_SHIFT 11
-#define BCHP_SWITCH_INTRL2_1_CPU_MASK_STATUS_p4_link_down_intr_mask_DEFAULT 0x00000001
-
-/* SWITCH_INTRL2_1 :: CPU_MASK_STATUS :: p4_link_up_intr_mask [10:10] */
-#define BCHP_SWITCH_INTRL2_1_CPU_MASK_STATUS_p4_link_up_intr_mask_MASK 0x00000400
-#define BCHP_SWITCH_INTRL2_1_CPU_MASK_STATUS_p4_link_up_intr_mask_SHIFT 10
-#define BCHP_SWITCH_INTRL2_1_CPU_MASK_STATUS_p4_link_up_intr_mask_DEFAULT 0x00000001
-
-/* SWITCH_INTRL2_1 :: CPU_MASK_STATUS :: p5_gphy_intr_mask [09:09] */
-#define BCHP_SWITCH_INTRL2_1_CPU_MASK_STATUS_p5_gphy_intr_mask_MASK 0x00000200
-#define BCHP_SWITCH_INTRL2_1_CPU_MASK_STATUS_p5_gphy_intr_mask_SHIFT 9
-#define BCHP_SWITCH_INTRL2_1_CPU_MASK_STATUS_p5_gphy_intr_mask_DEFAULT 0x00000001
-
-/* SWITCH_INTRL2_1 :: CPU_MASK_STATUS :: p5_energy_off_intr_mask [08:08] */
-#define BCHP_SWITCH_INTRL2_1_CPU_MASK_STATUS_p5_energy_off_intr_mask_MASK 0x00000100
-#define BCHP_SWITCH_INTRL2_1_CPU_MASK_STATUS_p5_energy_off_intr_mask_SHIFT 8
-#define BCHP_SWITCH_INTRL2_1_CPU_MASK_STATUS_p5_energy_off_intr_mask_DEFAULT 0x00000001
-
-/* SWITCH_INTRL2_1 :: CPU_MASK_STATUS :: p5_energy_on_intr_mask [07:07] */
-#define BCHP_SWITCH_INTRL2_1_CPU_MASK_STATUS_p5_energy_on_intr_mask_MASK 0x00000080
-#define BCHP_SWITCH_INTRL2_1_CPU_MASK_STATUS_p5_energy_on_intr_mask_SHIFT 7
-#define BCHP_SWITCH_INTRL2_1_CPU_MASK_STATUS_p5_energy_on_intr_mask_DEFAULT 0x00000001
-
-/* SWITCH_INTRL2_1 :: CPU_MASK_STATUS :: p5_link_down_intr_mask [06:06] */
-#define BCHP_SWITCH_INTRL2_1_CPU_MASK_STATUS_p5_link_down_intr_mask_MASK 0x00000040
-#define BCHP_SWITCH_INTRL2_1_CPU_MASK_STATUS_p5_link_down_intr_mask_SHIFT 6
-#define BCHP_SWITCH_INTRL2_1_CPU_MASK_STATUS_p5_link_down_intr_mask_DEFAULT 0x00000001
-
-/* SWITCH_INTRL2_1 :: CPU_MASK_STATUS :: p5_link_up_intr_mask [05:05] */
-#define BCHP_SWITCH_INTRL2_1_CPU_MASK_STATUS_p5_link_up_intr_mask_MASK 0x00000020
-#define BCHP_SWITCH_INTRL2_1_CPU_MASK_STATUS_p5_link_up_intr_mask_SHIFT 5
-#define BCHP_SWITCH_INTRL2_1_CPU_MASK_STATUS_p5_link_up_intr_mask_DEFAULT 0x00000001
-
-/* SWITCH_INTRL2_1 :: CPU_MASK_STATUS :: p7_gphy_intr_mask [04:04] */
-#define BCHP_SWITCH_INTRL2_1_CPU_MASK_STATUS_p7_gphy_intr_mask_MASK 0x00000010
-#define BCHP_SWITCH_INTRL2_1_CPU_MASK_STATUS_p7_gphy_intr_mask_SHIFT 4
-#define BCHP_SWITCH_INTRL2_1_CPU_MASK_STATUS_p7_gphy_intr_mask_DEFAULT 0x00000001
-
-/* SWITCH_INTRL2_1 :: CPU_MASK_STATUS :: p7_energy_off_intr_mask [03:03] */
-#define BCHP_SWITCH_INTRL2_1_CPU_MASK_STATUS_p7_energy_off_intr_mask_MASK 0x00000008
-#define BCHP_SWITCH_INTRL2_1_CPU_MASK_STATUS_p7_energy_off_intr_mask_SHIFT 3
-#define BCHP_SWITCH_INTRL2_1_CPU_MASK_STATUS_p7_energy_off_intr_mask_DEFAULT 0x00000001
-
-/* SWITCH_INTRL2_1 :: CPU_MASK_STATUS :: p7_energy_on_intr_mask [02:02] */
-#define BCHP_SWITCH_INTRL2_1_CPU_MASK_STATUS_p7_energy_on_intr_mask_MASK 0x00000004
-#define BCHP_SWITCH_INTRL2_1_CPU_MASK_STATUS_p7_energy_on_intr_mask_SHIFT 2
-#define BCHP_SWITCH_INTRL2_1_CPU_MASK_STATUS_p7_energy_on_intr_mask_DEFAULT 0x00000001
-
-/* SWITCH_INTRL2_1 :: CPU_MASK_STATUS :: p7_link_down_intr_mask [01:01] */
-#define BCHP_SWITCH_INTRL2_1_CPU_MASK_STATUS_p7_link_down_intr_mask_MASK 0x00000002
-#define BCHP_SWITCH_INTRL2_1_CPU_MASK_STATUS_p7_link_down_intr_mask_SHIFT 1
-#define BCHP_SWITCH_INTRL2_1_CPU_MASK_STATUS_p7_link_down_intr_mask_DEFAULT 0x00000001
-
-/* SWITCH_INTRL2_1 :: CPU_MASK_STATUS :: p7_link_up_intr_mask [00:00] */
-#define BCHP_SWITCH_INTRL2_1_CPU_MASK_STATUS_p7_link_up_intr_mask_MASK 0x00000001
-#define BCHP_SWITCH_INTRL2_1_CPU_MASK_STATUS_p7_link_up_intr_mask_SHIFT 0
-#define BCHP_SWITCH_INTRL2_1_CPU_MASK_STATUS_p7_link_up_intr_mask_DEFAULT 0x00000001
-
-/***************************************************************************
- *CPU_MASK_SET - CPU interrupt Mask Set Register
- ***************************************************************************/
-/* SWITCH_INTRL2_1 :: CPU_MASK_SET :: reserved0 [31:30] */
-#define BCHP_SWITCH_INTRL2_1_CPU_MASK_SET_reserved0_MASK 0xc0000000
-#define BCHP_SWITCH_INTRL2_1_CPU_MASK_SET_reserved0_SHIFT 30
-
-/* SWITCH_INTRL2_1 :: CPU_MASK_SET :: p1_gphy_intr_mask [29:29] */
-#define BCHP_SWITCH_INTRL2_1_CPU_MASK_SET_p1_gphy_intr_mask_MASK 0x20000000
-#define BCHP_SWITCH_INTRL2_1_CPU_MASK_SET_p1_gphy_intr_mask_SHIFT 29
-#define BCHP_SWITCH_INTRL2_1_CPU_MASK_SET_p1_gphy_intr_mask_DEFAULT 0x00000001
-
-/* SWITCH_INTRL2_1 :: CPU_MASK_SET :: p1_energy_off_intr_mask [28:28] */
-#define BCHP_SWITCH_INTRL2_1_CPU_MASK_SET_p1_energy_off_intr_mask_MASK 0x10000000
-#define BCHP_SWITCH_INTRL2_1_CPU_MASK_SET_p1_energy_off_intr_mask_SHIFT 28
-#define BCHP_SWITCH_INTRL2_1_CPU_MASK_SET_p1_energy_off_intr_mask_DEFAULT 0x00000001
-
-/* SWITCH_INTRL2_1 :: CPU_MASK_SET :: p1_energy_on_intr_mask [27:27] */
-#define BCHP_SWITCH_INTRL2_1_CPU_MASK_SET_p1_energy_on_intr_mask_MASK 0x08000000
-#define BCHP_SWITCH_INTRL2_1_CPU_MASK_SET_p1_energy_on_intr_mask_SHIFT 27
-#define BCHP_SWITCH_INTRL2_1_CPU_MASK_SET_p1_energy_on_intr_mask_DEFAULT 0x00000001
-
-/* SWITCH_INTRL2_1 :: CPU_MASK_SET :: p1_link_down_intr_mask [26:26] */
-#define BCHP_SWITCH_INTRL2_1_CPU_MASK_SET_p1_link_down_intr_mask_MASK 0x04000000
-#define BCHP_SWITCH_INTRL2_1_CPU_MASK_SET_p1_link_down_intr_mask_SHIFT 26
-#define BCHP_SWITCH_INTRL2_1_CPU_MASK_SET_p1_link_down_intr_mask_DEFAULT 0x00000001
-
-/* SWITCH_INTRL2_1 :: CPU_MASK_SET :: p1_link_up_intr_mask [25:25] */
-#define BCHP_SWITCH_INTRL2_1_CPU_MASK_SET_p1_link_up_intr_mask_MASK 0x02000000
-#define BCHP_SWITCH_INTRL2_1_CPU_MASK_SET_p1_link_up_intr_mask_SHIFT 25
-#define BCHP_SWITCH_INTRL2_1_CPU_MASK_SET_p1_link_up_intr_mask_DEFAULT 0x00000001
-
-/* SWITCH_INTRL2_1 :: CPU_MASK_SET :: p2_gphy_intr_mask [24:24] */
-#define BCHP_SWITCH_INTRL2_1_CPU_MASK_SET_p2_gphy_intr_mask_MASK 0x01000000
-#define BCHP_SWITCH_INTRL2_1_CPU_MASK_SET_p2_gphy_intr_mask_SHIFT 24
-#define BCHP_SWITCH_INTRL2_1_CPU_MASK_SET_p2_gphy_intr_mask_DEFAULT 0x00000001
-
-/* SWITCH_INTRL2_1 :: CPU_MASK_SET :: p2_energy_off_intr_mask [23:23] */
-#define BCHP_SWITCH_INTRL2_1_CPU_MASK_SET_p2_energy_off_intr_mask_MASK 0x00800000
-#define BCHP_SWITCH_INTRL2_1_CPU_MASK_SET_p2_energy_off_intr_mask_SHIFT 23
-#define BCHP_SWITCH_INTRL2_1_CPU_MASK_SET_p2_energy_off_intr_mask_DEFAULT 0x00000001
-
-/* SWITCH_INTRL2_1 :: CPU_MASK_SET :: p2_energy_on_intr_mask [22:22] */
-#define BCHP_SWITCH_INTRL2_1_CPU_MASK_SET_p2_energy_on_intr_mask_MASK 0x00400000
-#define BCHP_SWITCH_INTRL2_1_CPU_MASK_SET_p2_energy_on_intr_mask_SHIFT 22
-#define BCHP_SWITCH_INTRL2_1_CPU_MASK_SET_p2_energy_on_intr_mask_DEFAULT 0x00000001
-
-/* SWITCH_INTRL2_1 :: CPU_MASK_SET :: p2_link_down_intr_mask [21:21] */
-#define BCHP_SWITCH_INTRL2_1_CPU_MASK_SET_p2_link_down_intr_mask_MASK 0x00200000
-#define BCHP_SWITCH_INTRL2_1_CPU_MASK_SET_p2_link_down_intr_mask_SHIFT 21
-#define BCHP_SWITCH_INTRL2_1_CPU_MASK_SET_p2_link_down_intr_mask_DEFAULT 0x00000001
-
-/* SWITCH_INTRL2_1 :: CPU_MASK_SET :: p2_link_up_intr_mask [20:20] */
-#define BCHP_SWITCH_INTRL2_1_CPU_MASK_SET_p2_link_up_intr_mask_MASK 0x00100000
-#define BCHP_SWITCH_INTRL2_1_CPU_MASK_SET_p2_link_up_intr_mask_SHIFT 20
-#define BCHP_SWITCH_INTRL2_1_CPU_MASK_SET_p2_link_up_intr_mask_DEFAULT 0x00000001
-
-/* SWITCH_INTRL2_1 :: CPU_MASK_SET :: p3_gphy_intr_mask [19:19] */
-#define BCHP_SWITCH_INTRL2_1_CPU_MASK_SET_p3_gphy_intr_mask_MASK 0x00080000
-#define BCHP_SWITCH_INTRL2_1_CPU_MASK_SET_p3_gphy_intr_mask_SHIFT 19
-#define BCHP_SWITCH_INTRL2_1_CPU_MASK_SET_p3_gphy_intr_mask_DEFAULT 0x00000001
-
-/* SWITCH_INTRL2_1 :: CPU_MASK_SET :: p3_energy_off_intr_mask [18:18] */
-#define BCHP_SWITCH_INTRL2_1_CPU_MASK_SET_p3_energy_off_intr_mask_MASK 0x00040000
-#define BCHP_SWITCH_INTRL2_1_CPU_MASK_SET_p3_energy_off_intr_mask_SHIFT 18
-#define BCHP_SWITCH_INTRL2_1_CPU_MASK_SET_p3_energy_off_intr_mask_DEFAULT 0x00000001
-
-/* SWITCH_INTRL2_1 :: CPU_MASK_SET :: p3_energy_on_intr_mask [17:17] */
-#define BCHP_SWITCH_INTRL2_1_CPU_MASK_SET_p3_energy_on_intr_mask_MASK 0x00020000
-#define BCHP_SWITCH_INTRL2_1_CPU_MASK_SET_p3_energy_on_intr_mask_SHIFT 17
-#define BCHP_SWITCH_INTRL2_1_CPU_MASK_SET_p3_energy_on_intr_mask_DEFAULT 0x00000001
-
-/* SWITCH_INTRL2_1 :: CPU_MASK_SET :: p3_link_down_intr_mask [16:16] */
-#define BCHP_SWITCH_INTRL2_1_CPU_MASK_SET_p3_link_down_intr_mask_MASK 0x00010000
-#define BCHP_SWITCH_INTRL2_1_CPU_MASK_SET_p3_link_down_intr_mask_SHIFT 16
-#define BCHP_SWITCH_INTRL2_1_CPU_MASK_SET_p3_link_down_intr_mask_DEFAULT 0x00000001
-
-/* SWITCH_INTRL2_1 :: CPU_MASK_SET :: p3_link_up_intr_mask [15:15] */
-#define BCHP_SWITCH_INTRL2_1_CPU_MASK_SET_p3_link_up_intr_mask_MASK 0x00008000
-#define BCHP_SWITCH_INTRL2_1_CPU_MASK_SET_p3_link_up_intr_mask_SHIFT 15
-#define BCHP_SWITCH_INTRL2_1_CPU_MASK_SET_p3_link_up_intr_mask_DEFAULT 0x00000001
-
-/* SWITCH_INTRL2_1 :: CPU_MASK_SET :: p4_gphy_intr_mask [14:14] */
-#define BCHP_SWITCH_INTRL2_1_CPU_MASK_SET_p4_gphy_intr_mask_MASK 0x00004000
-#define BCHP_SWITCH_INTRL2_1_CPU_MASK_SET_p4_gphy_intr_mask_SHIFT 14
-#define BCHP_SWITCH_INTRL2_1_CPU_MASK_SET_p4_gphy_intr_mask_DEFAULT 0x00000001
-
-/* SWITCH_INTRL2_1 :: CPU_MASK_SET :: p4_energy_off_intr_mask [13:13] */
-#define BCHP_SWITCH_INTRL2_1_CPU_MASK_SET_p4_energy_off_intr_mask_MASK 0x00002000
-#define BCHP_SWITCH_INTRL2_1_CPU_MASK_SET_p4_energy_off_intr_mask_SHIFT 13
-#define BCHP_SWITCH_INTRL2_1_CPU_MASK_SET_p4_energy_off_intr_mask_DEFAULT 0x00000001
-
-/* SWITCH_INTRL2_1 :: CPU_MASK_SET :: p4_energy_on_intr_mask [12:12] */
-#define BCHP_SWITCH_INTRL2_1_CPU_MASK_SET_p4_energy_on_intr_mask_MASK 0x00001000
-#define BCHP_SWITCH_INTRL2_1_CPU_MASK_SET_p4_energy_on_intr_mask_SHIFT 12
-#define BCHP_SWITCH_INTRL2_1_CPU_MASK_SET_p4_energy_on_intr_mask_DEFAULT 0x00000001
-
-/* SWITCH_INTRL2_1 :: CPU_MASK_SET :: p4_link_down_intr_mask [11:11] */
-#define BCHP_SWITCH_INTRL2_1_CPU_MASK_SET_p4_link_down_intr_mask_MASK 0x00000800
-#define BCHP_SWITCH_INTRL2_1_CPU_MASK_SET_p4_link_down_intr_mask_SHIFT 11
-#define BCHP_SWITCH_INTRL2_1_CPU_MASK_SET_p4_link_down_intr_mask_DEFAULT 0x00000001
-
-/* SWITCH_INTRL2_1 :: CPU_MASK_SET :: p4_link_up_intr_mask [10:10] */
-#define BCHP_SWITCH_INTRL2_1_CPU_MASK_SET_p4_link_up_intr_mask_MASK 0x00000400
-#define BCHP_SWITCH_INTRL2_1_CPU_MASK_SET_p4_link_up_intr_mask_SHIFT 10
-#define BCHP_SWITCH_INTRL2_1_CPU_MASK_SET_p4_link_up_intr_mask_DEFAULT 0x00000001
-
-/* SWITCH_INTRL2_1 :: CPU_MASK_SET :: p5_gphy_intr_mask [09:09] */
-#define BCHP_SWITCH_INTRL2_1_CPU_MASK_SET_p5_gphy_intr_mask_MASK 0x00000200
-#define BCHP_SWITCH_INTRL2_1_CPU_MASK_SET_p5_gphy_intr_mask_SHIFT 9
-#define BCHP_SWITCH_INTRL2_1_CPU_MASK_SET_p5_gphy_intr_mask_DEFAULT 0x00000001
-
-/* SWITCH_INTRL2_1 :: CPU_MASK_SET :: p5_energy_off_intr_mask [08:08] */
-#define BCHP_SWITCH_INTRL2_1_CPU_MASK_SET_p5_energy_off_intr_mask_MASK 0x00000100
-#define BCHP_SWITCH_INTRL2_1_CPU_MASK_SET_p5_energy_off_intr_mask_SHIFT 8
-#define BCHP_SWITCH_INTRL2_1_CPU_MASK_SET_p5_energy_off_intr_mask_DEFAULT 0x00000001
-
-/* SWITCH_INTRL2_1 :: CPU_MASK_SET :: p5_energy_on_intr_mask [07:07] */
-#define BCHP_SWITCH_INTRL2_1_CPU_MASK_SET_p5_energy_on_intr_mask_MASK 0x00000080
-#define BCHP_SWITCH_INTRL2_1_CPU_MASK_SET_p5_energy_on_intr_mask_SHIFT 7
-#define BCHP_SWITCH_INTRL2_1_CPU_MASK_SET_p5_energy_on_intr_mask_DEFAULT 0x00000001
-
-/* SWITCH_INTRL2_1 :: CPU_MASK_SET :: p5_link_down_intr_mask [06:06] */
-#define BCHP_SWITCH_INTRL2_1_CPU_MASK_SET_p5_link_down_intr_mask_MASK 0x00000040
-#define BCHP_SWITCH_INTRL2_1_CPU_MASK_SET_p5_link_down_intr_mask_SHIFT 6
-#define BCHP_SWITCH_INTRL2_1_CPU_MASK_SET_p5_link_down_intr_mask_DEFAULT 0x00000001
-
-/* SWITCH_INTRL2_1 :: CPU_MASK_SET :: p5_link_up_intr_mask [05:05] */
-#define BCHP_SWITCH_INTRL2_1_CPU_MASK_SET_p5_link_up_intr_mask_MASK 0x00000020
-#define BCHP_SWITCH_INTRL2_1_CPU_MASK_SET_p5_link_up_intr_mask_SHIFT 5
-#define BCHP_SWITCH_INTRL2_1_CPU_MASK_SET_p5_link_up_intr_mask_DEFAULT 0x00000001
-
-/* SWITCH_INTRL2_1 :: CPU_MASK_SET :: p7_gphy_intr_mask [04:04] */
-#define BCHP_SWITCH_INTRL2_1_CPU_MASK_SET_p7_gphy_intr_mask_MASK 0x00000010
-#define BCHP_SWITCH_INTRL2_1_CPU_MASK_SET_p7_gphy_intr_mask_SHIFT 4
-#define BCHP_SWITCH_INTRL2_1_CPU_MASK_SET_p7_gphy_intr_mask_DEFAULT 0x00000001
-
-/* SWITCH_INTRL2_1 :: CPU_MASK_SET :: p7_energy_off_intr_mask [03:03] */
-#define BCHP_SWITCH_INTRL2_1_CPU_MASK_SET_p7_energy_off_intr_mask_MASK 0x00000008
-#define BCHP_SWITCH_INTRL2_1_CPU_MASK_SET_p7_energy_off_intr_mask_SHIFT 3
-#define BCHP_SWITCH_INTRL2_1_CPU_MASK_SET_p7_energy_off_intr_mask_DEFAULT 0x00000001
-
-/* SWITCH_INTRL2_1 :: CPU_MASK_SET :: p7_energy_on_intr_mask [02:02] */
-#define BCHP_SWITCH_INTRL2_1_CPU_MASK_SET_p7_energy_on_intr_mask_MASK 0x00000004
-#define BCHP_SWITCH_INTRL2_1_CPU_MASK_SET_p7_energy_on_intr_mask_SHIFT 2
-#define BCHP_SWITCH_INTRL2_1_CPU_MASK_SET_p7_energy_on_intr_mask_DEFAULT 0x00000001
-
-/* SWITCH_INTRL2_1 :: CPU_MASK_SET :: p7_link_down_intr_mask [01:01] */
-#define BCHP_SWITCH_INTRL2_1_CPU_MASK_SET_p7_link_down_intr_mask_MASK 0x00000002
-#define BCHP_SWITCH_INTRL2_1_CPU_MASK_SET_p7_link_down_intr_mask_SHIFT 1
-#define BCHP_SWITCH_INTRL2_1_CPU_MASK_SET_p7_link_down_intr_mask_DEFAULT 0x00000001
-
-/* SWITCH_INTRL2_1 :: CPU_MASK_SET :: p7_link_up_intr_mask [00:00] */
-#define BCHP_SWITCH_INTRL2_1_CPU_MASK_SET_p7_link_up_intr_mask_MASK 0x00000001
-#define BCHP_SWITCH_INTRL2_1_CPU_MASK_SET_p7_link_up_intr_mask_SHIFT 0
-#define BCHP_SWITCH_INTRL2_1_CPU_MASK_SET_p7_link_up_intr_mask_DEFAULT 0x00000001
-
-/***************************************************************************
- *CPU_MASK_CLEAR - CPU interrupt Mask Clear Register
- ***************************************************************************/
-/* SWITCH_INTRL2_1 :: CPU_MASK_CLEAR :: reserved0 [31:30] */
-#define BCHP_SWITCH_INTRL2_1_CPU_MASK_CLEAR_reserved0_MASK 0xc0000000
-#define BCHP_SWITCH_INTRL2_1_CPU_MASK_CLEAR_reserved0_SHIFT 30
-
-/* SWITCH_INTRL2_1 :: CPU_MASK_CLEAR :: p1_gphy_intr_mask [29:29] */
-#define BCHP_SWITCH_INTRL2_1_CPU_MASK_CLEAR_p1_gphy_intr_mask_MASK 0x20000000
-#define BCHP_SWITCH_INTRL2_1_CPU_MASK_CLEAR_p1_gphy_intr_mask_SHIFT 29
-#define BCHP_SWITCH_INTRL2_1_CPU_MASK_CLEAR_p1_gphy_intr_mask_DEFAULT 0x00000001
-
-/* SWITCH_INTRL2_1 :: CPU_MASK_CLEAR :: p1_energy_off_intr_mask [28:28] */
-#define BCHP_SWITCH_INTRL2_1_CPU_MASK_CLEAR_p1_energy_off_intr_mask_MASK 0x10000000
-#define BCHP_SWITCH_INTRL2_1_CPU_MASK_CLEAR_p1_energy_off_intr_mask_SHIFT 28
-#define BCHP_SWITCH_INTRL2_1_CPU_MASK_CLEAR_p1_energy_off_intr_mask_DEFAULT 0x00000001
-
-/* SWITCH_INTRL2_1 :: CPU_MASK_CLEAR :: p1_energy_on_intr_mask [27:27] */
-#define BCHP_SWITCH_INTRL2_1_CPU_MASK_CLEAR_p1_energy_on_intr_mask_MASK 0x08000000
-#define BCHP_SWITCH_INTRL2_1_CPU_MASK_CLEAR_p1_energy_on_intr_mask_SHIFT 27
-#define BCHP_SWITCH_INTRL2_1_CPU_MASK_CLEAR_p1_energy_on_intr_mask_DEFAULT 0x00000001
-
-/* SWITCH_INTRL2_1 :: CPU_MASK_CLEAR :: p1_link_down_intr_mask [26:26] */
-#define BCHP_SWITCH_INTRL2_1_CPU_MASK_CLEAR_p1_link_down_intr_mask_MASK 0x04000000
-#define BCHP_SWITCH_INTRL2_1_CPU_MASK_CLEAR_p1_link_down_intr_mask_SHIFT 26
-#define BCHP_SWITCH_INTRL2_1_CPU_MASK_CLEAR_p1_link_down_intr_mask_DEFAULT 0x00000001
-
-/* SWITCH_INTRL2_1 :: CPU_MASK_CLEAR :: p1_link_up_intr_mask [25:25] */
-#define BCHP_SWITCH_INTRL2_1_CPU_MASK_CLEAR_p1_link_up_intr_mask_MASK 0x02000000
-#define BCHP_SWITCH_INTRL2_1_CPU_MASK_CLEAR_p1_link_up_intr_mask_SHIFT 25
-#define BCHP_SWITCH_INTRL2_1_CPU_MASK_CLEAR_p1_link_up_intr_mask_DEFAULT 0x00000001
-
-/* SWITCH_INTRL2_1 :: CPU_MASK_CLEAR :: p2_gphy_intr_mask [24:24] */
-#define BCHP_SWITCH_INTRL2_1_CPU_MASK_CLEAR_p2_gphy_intr_mask_MASK 0x01000000
-#define BCHP_SWITCH_INTRL2_1_CPU_MASK_CLEAR_p2_gphy_intr_mask_SHIFT 24
-#define BCHP_SWITCH_INTRL2_1_CPU_MASK_CLEAR_p2_gphy_intr_mask_DEFAULT 0x00000001
-
-/* SWITCH_INTRL2_1 :: CPU_MASK_CLEAR :: p2_energy_off_intr_mask [23:23] */
-#define BCHP_SWITCH_INTRL2_1_CPU_MASK_CLEAR_p2_energy_off_intr_mask_MASK 0x00800000
-#define BCHP_SWITCH_INTRL2_1_CPU_MASK_CLEAR_p2_energy_off_intr_mask_SHIFT 23
-#define BCHP_SWITCH_INTRL2_1_CPU_MASK_CLEAR_p2_energy_off_intr_mask_DEFAULT 0x00000001
-
-/* SWITCH_INTRL2_1 :: CPU_MASK_CLEAR :: p2_energy_on_intr_mask [22:22] */
-#define BCHP_SWITCH_INTRL2_1_CPU_MASK_CLEAR_p2_energy_on_intr_mask_MASK 0x00400000
-#define BCHP_SWITCH_INTRL2_1_CPU_MASK_CLEAR_p2_energy_on_intr_mask_SHIFT 22
-#define BCHP_SWITCH_INTRL2_1_CPU_MASK_CLEAR_p2_energy_on_intr_mask_DEFAULT 0x00000001
-
-/* SWITCH_INTRL2_1 :: CPU_MASK_CLEAR :: p2_link_down_intr_mask [21:21] */
-#define BCHP_SWITCH_INTRL2_1_CPU_MASK_CLEAR_p2_link_down_intr_mask_MASK 0x00200000
-#define BCHP_SWITCH_INTRL2_1_CPU_MASK_CLEAR_p2_link_down_intr_mask_SHIFT 21
-#define BCHP_SWITCH_INTRL2_1_CPU_MASK_CLEAR_p2_link_down_intr_mask_DEFAULT 0x00000001
-
-/* SWITCH_INTRL2_1 :: CPU_MASK_CLEAR :: p2_link_up_intr_mask [20:20] */
-#define BCHP_SWITCH_INTRL2_1_CPU_MASK_CLEAR_p2_link_up_intr_mask_MASK 0x00100000
-#define BCHP_SWITCH_INTRL2_1_CPU_MASK_CLEAR_p2_link_up_intr_mask_SHIFT 20
-#define BCHP_SWITCH_INTRL2_1_CPU_MASK_CLEAR_p2_link_up_intr_mask_DEFAULT 0x00000001
-
-/* SWITCH_INTRL2_1 :: CPU_MASK_CLEAR :: p3_gphy_intr_mask [19:19] */
-#define BCHP_SWITCH_INTRL2_1_CPU_MASK_CLEAR_p3_gphy_intr_mask_MASK 0x00080000
-#define BCHP_SWITCH_INTRL2_1_CPU_MASK_CLEAR_p3_gphy_intr_mask_SHIFT 19
-#define BCHP_SWITCH_INTRL2_1_CPU_MASK_CLEAR_p3_gphy_intr_mask_DEFAULT 0x00000001
-
-/* SWITCH_INTRL2_1 :: CPU_MASK_CLEAR :: p3_energy_off_intr_mask [18:18] */
-#define BCHP_SWITCH_INTRL2_1_CPU_MASK_CLEAR_p3_energy_off_intr_mask_MASK 0x00040000
-#define BCHP_SWITCH_INTRL2_1_CPU_MASK_CLEAR_p3_energy_off_intr_mask_SHIFT 18
-#define BCHP_SWITCH_INTRL2_1_CPU_MASK_CLEAR_p3_energy_off_intr_mask_DEFAULT 0x00000001
-
-/* SWITCH_INTRL2_1 :: CPU_MASK_CLEAR :: p3_energy_on_intr_mask [17:17] */
-#define BCHP_SWITCH_INTRL2_1_CPU_MASK_CLEAR_p3_energy_on_intr_mask_MASK 0x00020000
-#define BCHP_SWITCH_INTRL2_1_CPU_MASK_CLEAR_p3_energy_on_intr_mask_SHIFT 17
-#define BCHP_SWITCH_INTRL2_1_CPU_MASK_CLEAR_p3_energy_on_intr_mask_DEFAULT 0x00000001
-
-/* SWITCH_INTRL2_1 :: CPU_MASK_CLEAR :: p3_link_down_intr_mask [16:16] */
-#define BCHP_SWITCH_INTRL2_1_CPU_MASK_CLEAR_p3_link_down_intr_mask_MASK 0x00010000
-#define BCHP_SWITCH_INTRL2_1_CPU_MASK_CLEAR_p3_link_down_intr_mask_SHIFT 16
-#define BCHP_SWITCH_INTRL2_1_CPU_MASK_CLEAR_p3_link_down_intr_mask_DEFAULT 0x00000001
-
-/* SWITCH_INTRL2_1 :: CPU_MASK_CLEAR :: p3_link_up_intr_mask [15:15] */
-#define BCHP_SWITCH_INTRL2_1_CPU_MASK_CLEAR_p3_link_up_intr_mask_MASK 0x00008000
-#define BCHP_SWITCH_INTRL2_1_CPU_MASK_CLEAR_p3_link_up_intr_mask_SHIFT 15
-#define BCHP_SWITCH_INTRL2_1_CPU_MASK_CLEAR_p3_link_up_intr_mask_DEFAULT 0x00000001
-
-/* SWITCH_INTRL2_1 :: CPU_MASK_CLEAR :: p4_gphy_intr_mask [14:14] */
-#define BCHP_SWITCH_INTRL2_1_CPU_MASK_CLEAR_p4_gphy_intr_mask_MASK 0x00004000
-#define BCHP_SWITCH_INTRL2_1_CPU_MASK_CLEAR_p4_gphy_intr_mask_SHIFT 14
-#define BCHP_SWITCH_INTRL2_1_CPU_MASK_CLEAR_p4_gphy_intr_mask_DEFAULT 0x00000001
-
-/* SWITCH_INTRL2_1 :: CPU_MASK_CLEAR :: p4_energy_off_intr_mask [13:13] */
-#define BCHP_SWITCH_INTRL2_1_CPU_MASK_CLEAR_p4_energy_off_intr_mask_MASK 0x00002000
-#define BCHP_SWITCH_INTRL2_1_CPU_MASK_CLEAR_p4_energy_off_intr_mask_SHIFT 13
-#define BCHP_SWITCH_INTRL2_1_CPU_MASK_CLEAR_p4_energy_off_intr_mask_DEFAULT 0x00000001
-
-/* SWITCH_INTRL2_1 :: CPU_MASK_CLEAR :: p4_energy_on_intr_mask [12:12] */
-#define BCHP_SWITCH_INTRL2_1_CPU_MASK_CLEAR_p4_energy_on_intr_mask_MASK 0x00001000
-#define BCHP_SWITCH_INTRL2_1_CPU_MASK_CLEAR_p4_energy_on_intr_mask_SHIFT 12
-#define BCHP_SWITCH_INTRL2_1_CPU_MASK_CLEAR_p4_energy_on_intr_mask_DEFAULT 0x00000001
-
-/* SWITCH_INTRL2_1 :: CPU_MASK_CLEAR :: p4_link_down_intr_mask [11:11] */
-#define BCHP_SWITCH_INTRL2_1_CPU_MASK_CLEAR_p4_link_down_intr_mask_MASK 0x00000800
-#define BCHP_SWITCH_INTRL2_1_CPU_MASK_CLEAR_p4_link_down_intr_mask_SHIFT 11
-#define BCHP_SWITCH_INTRL2_1_CPU_MASK_CLEAR_p4_link_down_intr_mask_DEFAULT 0x00000001
-
-/* SWITCH_INTRL2_1 :: CPU_MASK_CLEAR :: p4_link_up_intr_mask [10:10] */
-#define BCHP_SWITCH_INTRL2_1_CPU_MASK_CLEAR_p4_link_up_intr_mask_MASK 0x00000400
-#define BCHP_SWITCH_INTRL2_1_CPU_MASK_CLEAR_p4_link_up_intr_mask_SHIFT 10
-#define BCHP_SWITCH_INTRL2_1_CPU_MASK_CLEAR_p4_link_up_intr_mask_DEFAULT 0x00000001
-
-/* SWITCH_INTRL2_1 :: CPU_MASK_CLEAR :: p5_gphy_intr_mask [09:09] */
-#define BCHP_SWITCH_INTRL2_1_CPU_MASK_CLEAR_p5_gphy_intr_mask_MASK 0x00000200
-#define BCHP_SWITCH_INTRL2_1_CPU_MASK_CLEAR_p5_gphy_intr_mask_SHIFT 9
-#define BCHP_SWITCH_INTRL2_1_CPU_MASK_CLEAR_p5_gphy_intr_mask_DEFAULT 0x00000001
-
-/* SWITCH_INTRL2_1 :: CPU_MASK_CLEAR :: p5_energy_off_intr_mask [08:08] */
-#define BCHP_SWITCH_INTRL2_1_CPU_MASK_CLEAR_p5_energy_off_intr_mask_MASK 0x00000100
-#define BCHP_SWITCH_INTRL2_1_CPU_MASK_CLEAR_p5_energy_off_intr_mask_SHIFT 8
-#define BCHP_SWITCH_INTRL2_1_CPU_MASK_CLEAR_p5_energy_off_intr_mask_DEFAULT 0x00000001
-
-/* SWITCH_INTRL2_1 :: CPU_MASK_CLEAR :: p5_energy_on_intr_mask [07:07] */
-#define BCHP_SWITCH_INTRL2_1_CPU_MASK_CLEAR_p5_energy_on_intr_mask_MASK 0x00000080
-#define BCHP_SWITCH_INTRL2_1_CPU_MASK_CLEAR_p5_energy_on_intr_mask_SHIFT 7
-#define BCHP_SWITCH_INTRL2_1_CPU_MASK_CLEAR_p5_energy_on_intr_mask_DEFAULT 0x00000001
-
-/* SWITCH_INTRL2_1 :: CPU_MASK_CLEAR :: p5_link_down_intr_mask [06:06] */
-#define BCHP_SWITCH_INTRL2_1_CPU_MASK_CLEAR_p5_link_down_intr_mask_MASK 0x00000040
-#define BCHP_SWITCH_INTRL2_1_CPU_MASK_CLEAR_p5_link_down_intr_mask_SHIFT 6
-#define BCHP_SWITCH_INTRL2_1_CPU_MASK_CLEAR_p5_link_down_intr_mask_DEFAULT 0x00000001
-
-/* SWITCH_INTRL2_1 :: CPU_MASK_CLEAR :: p5_link_up_intr_mask [05:05] */
-#define BCHP_SWITCH_INTRL2_1_CPU_MASK_CLEAR_p5_link_up_intr_mask_MASK 0x00000020
-#define BCHP_SWITCH_INTRL2_1_CPU_MASK_CLEAR_p5_link_up_intr_mask_SHIFT 5
-#define BCHP_SWITCH_INTRL2_1_CPU_MASK_CLEAR_p5_link_up_intr_mask_DEFAULT 0x00000001
-
-/* SWITCH_INTRL2_1 :: CPU_MASK_CLEAR :: p7_gphy_intr_mask [04:04] */
-#define BCHP_SWITCH_INTRL2_1_CPU_MASK_CLEAR_p7_gphy_intr_mask_MASK 0x00000010
-#define BCHP_SWITCH_INTRL2_1_CPU_MASK_CLEAR_p7_gphy_intr_mask_SHIFT 4
-#define BCHP_SWITCH_INTRL2_1_CPU_MASK_CLEAR_p7_gphy_intr_mask_DEFAULT 0x00000001
-
-/* SWITCH_INTRL2_1 :: CPU_MASK_CLEAR :: p7_energy_off_intr_mask [03:03] */
-#define BCHP_SWITCH_INTRL2_1_CPU_MASK_CLEAR_p7_energy_off_intr_mask_MASK 0x00000008
-#define BCHP_SWITCH_INTRL2_1_CPU_MASK_CLEAR_p7_energy_off_intr_mask_SHIFT 3
-#define BCHP_SWITCH_INTRL2_1_CPU_MASK_CLEAR_p7_energy_off_intr_mask_DEFAULT 0x00000001
-
-/* SWITCH_INTRL2_1 :: CPU_MASK_CLEAR :: p7_energy_on_intr_mask [02:02] */
-#define BCHP_SWITCH_INTRL2_1_CPU_MASK_CLEAR_p7_energy_on_intr_mask_MASK 0x00000004
-#define BCHP_SWITCH_INTRL2_1_CPU_MASK_CLEAR_p7_energy_on_intr_mask_SHIFT 2
-#define BCHP_SWITCH_INTRL2_1_CPU_MASK_CLEAR_p7_energy_on_intr_mask_DEFAULT 0x00000001
-
-/* SWITCH_INTRL2_1 :: CPU_MASK_CLEAR :: p7_link_down_intr_mask [01:01] */
-#define BCHP_SWITCH_INTRL2_1_CPU_MASK_CLEAR_p7_link_down_intr_mask_MASK 0x00000002
-#define BCHP_SWITCH_INTRL2_1_CPU_MASK_CLEAR_p7_link_down_intr_mask_SHIFT 1
-#define BCHP_SWITCH_INTRL2_1_CPU_MASK_CLEAR_p7_link_down_intr_mask_DEFAULT 0x00000001
-
-/* SWITCH_INTRL2_1 :: CPU_MASK_CLEAR :: p7_link_up_intr_mask [00:00] */
-#define BCHP_SWITCH_INTRL2_1_CPU_MASK_CLEAR_p7_link_up_intr_mask_MASK 0x00000001
-#define BCHP_SWITCH_INTRL2_1_CPU_MASK_CLEAR_p7_link_up_intr_mask_SHIFT 0
-#define BCHP_SWITCH_INTRL2_1_CPU_MASK_CLEAR_p7_link_up_intr_mask_DEFAULT 0x00000001
-
-/***************************************************************************
- *PCI_STATUS - PCI interrupt Status Register
- ***************************************************************************/
-/* SWITCH_INTRL2_1 :: PCI_STATUS :: reserved0 [31:30] */
-#define BCHP_SWITCH_INTRL2_1_PCI_STATUS_reserved0_MASK 0xc0000000
-#define BCHP_SWITCH_INTRL2_1_PCI_STATUS_reserved0_SHIFT 30
-
-/* SWITCH_INTRL2_1 :: PCI_STATUS :: p1_gphy_intr [29:29] */
-#define BCHP_SWITCH_INTRL2_1_PCI_STATUS_p1_gphy_intr_MASK 0x20000000
-#define BCHP_SWITCH_INTRL2_1_PCI_STATUS_p1_gphy_intr_SHIFT 29
-#define BCHP_SWITCH_INTRL2_1_PCI_STATUS_p1_gphy_intr_DEFAULT 0x00000000
-
-/* SWITCH_INTRL2_1 :: PCI_STATUS :: p1_energy_off_intr [28:28] */
-#define BCHP_SWITCH_INTRL2_1_PCI_STATUS_p1_energy_off_intr_MASK 0x10000000
-#define BCHP_SWITCH_INTRL2_1_PCI_STATUS_p1_energy_off_intr_SHIFT 28
-#define BCHP_SWITCH_INTRL2_1_PCI_STATUS_p1_energy_off_intr_DEFAULT 0x00000000
-
-/* SWITCH_INTRL2_1 :: PCI_STATUS :: p1_energy_on_intr [27:27] */
-#define BCHP_SWITCH_INTRL2_1_PCI_STATUS_p1_energy_on_intr_MASK 0x08000000
-#define BCHP_SWITCH_INTRL2_1_PCI_STATUS_p1_energy_on_intr_SHIFT 27
-#define BCHP_SWITCH_INTRL2_1_PCI_STATUS_p1_energy_on_intr_DEFAULT 0x00000000
-
-/* SWITCH_INTRL2_1 :: PCI_STATUS :: p1_link_down_intr [26:26] */
-#define BCHP_SWITCH_INTRL2_1_PCI_STATUS_p1_link_down_intr_MASK 0x04000000
-#define BCHP_SWITCH_INTRL2_1_PCI_STATUS_p1_link_down_intr_SHIFT 26
-#define BCHP_SWITCH_INTRL2_1_PCI_STATUS_p1_link_down_intr_DEFAULT 0x00000000
-
-/* SWITCH_INTRL2_1 :: PCI_STATUS :: p1_link_up_intr [25:25] */
-#define BCHP_SWITCH_INTRL2_1_PCI_STATUS_p1_link_up_intr_MASK 0x02000000
-#define BCHP_SWITCH_INTRL2_1_PCI_STATUS_p1_link_up_intr_SHIFT 25
-#define BCHP_SWITCH_INTRL2_1_PCI_STATUS_p1_link_up_intr_DEFAULT 0x00000000
-
-/* SWITCH_INTRL2_1 :: PCI_STATUS :: p2_gphy_intr [24:24] */
-#define BCHP_SWITCH_INTRL2_1_PCI_STATUS_p2_gphy_intr_MASK 0x01000000
-#define BCHP_SWITCH_INTRL2_1_PCI_STATUS_p2_gphy_intr_SHIFT 24
-#define BCHP_SWITCH_INTRL2_1_PCI_STATUS_p2_gphy_intr_DEFAULT 0x00000000
-
-/* SWITCH_INTRL2_1 :: PCI_STATUS :: p2_energy_off_intr [23:23] */
-#define BCHP_SWITCH_INTRL2_1_PCI_STATUS_p2_energy_off_intr_MASK 0x00800000
-#define BCHP_SWITCH_INTRL2_1_PCI_STATUS_p2_energy_off_intr_SHIFT 23
-#define BCHP_SWITCH_INTRL2_1_PCI_STATUS_p2_energy_off_intr_DEFAULT 0x00000000
-
-/* SWITCH_INTRL2_1 :: PCI_STATUS :: p2_energy_on_intr [22:22] */
-#define BCHP_SWITCH_INTRL2_1_PCI_STATUS_p2_energy_on_intr_MASK 0x00400000
-#define BCHP_SWITCH_INTRL2_1_PCI_STATUS_p2_energy_on_intr_SHIFT 22
-#define BCHP_SWITCH_INTRL2_1_PCI_STATUS_p2_energy_on_intr_DEFAULT 0x00000000
-
-/* SWITCH_INTRL2_1 :: PCI_STATUS :: p2_link_down_intr [21:21] */
-#define BCHP_SWITCH_INTRL2_1_PCI_STATUS_p2_link_down_intr_MASK 0x00200000
-#define BCHP_SWITCH_INTRL2_1_PCI_STATUS_p2_link_down_intr_SHIFT 21
-#define BCHP_SWITCH_INTRL2_1_PCI_STATUS_p2_link_down_intr_DEFAULT 0x00000000
-
-/* SWITCH_INTRL2_1 :: PCI_STATUS :: p2_link_up_intr [20:20] */
-#define BCHP_SWITCH_INTRL2_1_PCI_STATUS_p2_link_up_intr_MASK 0x00100000
-#define BCHP_SWITCH_INTRL2_1_PCI_STATUS_p2_link_up_intr_SHIFT 20
-#define BCHP_SWITCH_INTRL2_1_PCI_STATUS_p2_link_up_intr_DEFAULT 0x00000000
-
-/* SWITCH_INTRL2_1 :: PCI_STATUS :: p3_gphy_intr [19:19] */
-#define BCHP_SWITCH_INTRL2_1_PCI_STATUS_p3_gphy_intr_MASK 0x00080000
-#define BCHP_SWITCH_INTRL2_1_PCI_STATUS_p3_gphy_intr_SHIFT 19
-#define BCHP_SWITCH_INTRL2_1_PCI_STATUS_p3_gphy_intr_DEFAULT 0x00000000
-
-/* SWITCH_INTRL2_1 :: PCI_STATUS :: p3_energy_off_intr [18:18] */
-#define BCHP_SWITCH_INTRL2_1_PCI_STATUS_p3_energy_off_intr_MASK 0x00040000
-#define BCHP_SWITCH_INTRL2_1_PCI_STATUS_p3_energy_off_intr_SHIFT 18
-#define BCHP_SWITCH_INTRL2_1_PCI_STATUS_p3_energy_off_intr_DEFAULT 0x00000000
-
-/* SWITCH_INTRL2_1 :: PCI_STATUS :: p3_energy_on_intr [17:17] */
-#define BCHP_SWITCH_INTRL2_1_PCI_STATUS_p3_energy_on_intr_MASK 0x00020000
-#define BCHP_SWITCH_INTRL2_1_PCI_STATUS_p3_energy_on_intr_SHIFT 17
-#define BCHP_SWITCH_INTRL2_1_PCI_STATUS_p3_energy_on_intr_DEFAULT 0x00000000
-
-/* SWITCH_INTRL2_1 :: PCI_STATUS :: p3_link_down_intr [16:16] */
-#define BCHP_SWITCH_INTRL2_1_PCI_STATUS_p3_link_down_intr_MASK 0x00010000
-#define BCHP_SWITCH_INTRL2_1_PCI_STATUS_p3_link_down_intr_SHIFT 16
-#define BCHP_SWITCH_INTRL2_1_PCI_STATUS_p3_link_down_intr_DEFAULT 0x00000000
-
-/* SWITCH_INTRL2_1 :: PCI_STATUS :: p3_link_up_intr [15:15] */
-#define BCHP_SWITCH_INTRL2_1_PCI_STATUS_p3_link_up_intr_MASK 0x00008000
-#define BCHP_SWITCH_INTRL2_1_PCI_STATUS_p3_link_up_intr_SHIFT 15
-#define BCHP_SWITCH_INTRL2_1_PCI_STATUS_p3_link_up_intr_DEFAULT 0x00000000
-
-/* SWITCH_INTRL2_1 :: PCI_STATUS :: p4_gphy_intr [14:14] */
-#define BCHP_SWITCH_INTRL2_1_PCI_STATUS_p4_gphy_intr_MASK 0x00004000
-#define BCHP_SWITCH_INTRL2_1_PCI_STATUS_p4_gphy_intr_SHIFT 14
-#define BCHP_SWITCH_INTRL2_1_PCI_STATUS_p4_gphy_intr_DEFAULT 0x00000000
-
-/* SWITCH_INTRL2_1 :: PCI_STATUS :: p4_energy_off_intr [13:13] */
-#define BCHP_SWITCH_INTRL2_1_PCI_STATUS_p4_energy_off_intr_MASK 0x00002000
-#define BCHP_SWITCH_INTRL2_1_PCI_STATUS_p4_energy_off_intr_SHIFT 13
-#define BCHP_SWITCH_INTRL2_1_PCI_STATUS_p4_energy_off_intr_DEFAULT 0x00000000
-
-/* SWITCH_INTRL2_1 :: PCI_STATUS :: p4_energy_on_intr [12:12] */
-#define BCHP_SWITCH_INTRL2_1_PCI_STATUS_p4_energy_on_intr_MASK 0x00001000
-#define BCHP_SWITCH_INTRL2_1_PCI_STATUS_p4_energy_on_intr_SHIFT 12
-#define BCHP_SWITCH_INTRL2_1_PCI_STATUS_p4_energy_on_intr_DEFAULT 0x00000000
-
-/* SWITCH_INTRL2_1 :: PCI_STATUS :: p4_link_down_intr [11:11] */
-#define BCHP_SWITCH_INTRL2_1_PCI_STATUS_p4_link_down_intr_MASK 0x00000800
-#define BCHP_SWITCH_INTRL2_1_PCI_STATUS_p4_link_down_intr_SHIFT 11
-#define BCHP_SWITCH_INTRL2_1_PCI_STATUS_p4_link_down_intr_DEFAULT 0x00000000
-
-/* SWITCH_INTRL2_1 :: PCI_STATUS :: p4_link_up_intr [10:10] */
-#define BCHP_SWITCH_INTRL2_1_PCI_STATUS_p4_link_up_intr_MASK 0x00000400
-#define BCHP_SWITCH_INTRL2_1_PCI_STATUS_p4_link_up_intr_SHIFT 10
-#define BCHP_SWITCH_INTRL2_1_PCI_STATUS_p4_link_up_intr_DEFAULT 0x00000000
-
-/* SWITCH_INTRL2_1 :: PCI_STATUS :: p5_gphy_intr [09:09] */
-#define BCHP_SWITCH_INTRL2_1_PCI_STATUS_p5_gphy_intr_MASK 0x00000200
-#define BCHP_SWITCH_INTRL2_1_PCI_STATUS_p5_gphy_intr_SHIFT 9
-#define BCHP_SWITCH_INTRL2_1_PCI_STATUS_p5_gphy_intr_DEFAULT 0x00000000
-
-/* SWITCH_INTRL2_1 :: PCI_STATUS :: p5_energy_off_intr [08:08] */
-#define BCHP_SWITCH_INTRL2_1_PCI_STATUS_p5_energy_off_intr_MASK 0x00000100
-#define BCHP_SWITCH_INTRL2_1_PCI_STATUS_p5_energy_off_intr_SHIFT 8
-#define BCHP_SWITCH_INTRL2_1_PCI_STATUS_p5_energy_off_intr_DEFAULT 0x00000000
-
-/* SWITCH_INTRL2_1 :: PCI_STATUS :: p5_energy_on_intr [07:07] */
-#define BCHP_SWITCH_INTRL2_1_PCI_STATUS_p5_energy_on_intr_MASK 0x00000080
-#define BCHP_SWITCH_INTRL2_1_PCI_STATUS_p5_energy_on_intr_SHIFT 7
-#define BCHP_SWITCH_INTRL2_1_PCI_STATUS_p5_energy_on_intr_DEFAULT 0x00000000
-
-/* SWITCH_INTRL2_1 :: PCI_STATUS :: p5_link_down_intr [06:06] */
-#define BCHP_SWITCH_INTRL2_1_PCI_STATUS_p5_link_down_intr_MASK 0x00000040
-#define BCHP_SWITCH_INTRL2_1_PCI_STATUS_p5_link_down_intr_SHIFT 6
-#define BCHP_SWITCH_INTRL2_1_PCI_STATUS_p5_link_down_intr_DEFAULT 0x00000000
-
-/* SWITCH_INTRL2_1 :: PCI_STATUS :: p5_link_up_intr [05:05] */
-#define BCHP_SWITCH_INTRL2_1_PCI_STATUS_p5_link_up_intr_MASK 0x00000020
-#define BCHP_SWITCH_INTRL2_1_PCI_STATUS_p5_link_up_intr_SHIFT 5
-#define BCHP_SWITCH_INTRL2_1_PCI_STATUS_p5_link_up_intr_DEFAULT 0x00000000
-
-/* SWITCH_INTRL2_1 :: PCI_STATUS :: p7_gphy_intr [04:04] */
-#define BCHP_SWITCH_INTRL2_1_PCI_STATUS_p7_gphy_intr_MASK 0x00000010
-#define BCHP_SWITCH_INTRL2_1_PCI_STATUS_p7_gphy_intr_SHIFT 4
-#define BCHP_SWITCH_INTRL2_1_PCI_STATUS_p7_gphy_intr_DEFAULT 0x00000000
-
-/* SWITCH_INTRL2_1 :: PCI_STATUS :: p7_energy_off_intr [03:03] */
-#define BCHP_SWITCH_INTRL2_1_PCI_STATUS_p7_energy_off_intr_MASK 0x00000008
-#define BCHP_SWITCH_INTRL2_1_PCI_STATUS_p7_energy_off_intr_SHIFT 3
-#define BCHP_SWITCH_INTRL2_1_PCI_STATUS_p7_energy_off_intr_DEFAULT 0x00000000
-
-/* SWITCH_INTRL2_1 :: PCI_STATUS :: p7_energy_on_intr [02:02] */
-#define BCHP_SWITCH_INTRL2_1_PCI_STATUS_p7_energy_on_intr_MASK 0x00000004
-#define BCHP_SWITCH_INTRL2_1_PCI_STATUS_p7_energy_on_intr_SHIFT 2
-#define BCHP_SWITCH_INTRL2_1_PCI_STATUS_p7_energy_on_intr_DEFAULT 0x00000000
-
-/* SWITCH_INTRL2_1 :: PCI_STATUS :: p7_link_down_intr [01:01] */
-#define BCHP_SWITCH_INTRL2_1_PCI_STATUS_p7_link_down_intr_MASK 0x00000002
-#define BCHP_SWITCH_INTRL2_1_PCI_STATUS_p7_link_down_intr_SHIFT 1
-#define BCHP_SWITCH_INTRL2_1_PCI_STATUS_p7_link_down_intr_DEFAULT 0x00000000
-
-/* SWITCH_INTRL2_1 :: PCI_STATUS :: p7_link_up_intr [00:00] */
-#define BCHP_SWITCH_INTRL2_1_PCI_STATUS_p7_link_up_intr_MASK 0x00000001
-#define BCHP_SWITCH_INTRL2_1_PCI_STATUS_p7_link_up_intr_SHIFT 0
-#define BCHP_SWITCH_INTRL2_1_PCI_STATUS_p7_link_up_intr_DEFAULT 0x00000000
-
-/***************************************************************************
- *PCI_SET - PCI interrupt Set Register
- ***************************************************************************/
-/* SWITCH_INTRL2_1 :: PCI_SET :: reserved0 [31:30] */
-#define BCHP_SWITCH_INTRL2_1_PCI_SET_reserved0_MASK 0xc0000000
-#define BCHP_SWITCH_INTRL2_1_PCI_SET_reserved0_SHIFT 30
-
-/* SWITCH_INTRL2_1 :: PCI_SET :: p1_gphy_intr [29:29] */
-#define BCHP_SWITCH_INTRL2_1_PCI_SET_p1_gphy_intr_MASK 0x20000000
-#define BCHP_SWITCH_INTRL2_1_PCI_SET_p1_gphy_intr_SHIFT 29
-#define BCHP_SWITCH_INTRL2_1_PCI_SET_p1_gphy_intr_DEFAULT 0x00000000
-
-/* SWITCH_INTRL2_1 :: PCI_SET :: p1_energy_off_intr [28:28] */
-#define BCHP_SWITCH_INTRL2_1_PCI_SET_p1_energy_off_intr_MASK 0x10000000
-#define BCHP_SWITCH_INTRL2_1_PCI_SET_p1_energy_off_intr_SHIFT 28
-#define BCHP_SWITCH_INTRL2_1_PCI_SET_p1_energy_off_intr_DEFAULT 0x00000000
-
-/* SWITCH_INTRL2_1 :: PCI_SET :: p1_energy_on_intr [27:27] */
-#define BCHP_SWITCH_INTRL2_1_PCI_SET_p1_energy_on_intr_MASK 0x08000000
-#define BCHP_SWITCH_INTRL2_1_PCI_SET_p1_energy_on_intr_SHIFT 27
-#define BCHP_SWITCH_INTRL2_1_PCI_SET_p1_energy_on_intr_DEFAULT 0x00000000
-
-/* SWITCH_INTRL2_1 :: PCI_SET :: p1_link_down_intr [26:26] */
-#define BCHP_SWITCH_INTRL2_1_PCI_SET_p1_link_down_intr_MASK 0x04000000
-#define BCHP_SWITCH_INTRL2_1_PCI_SET_p1_link_down_intr_SHIFT 26
-#define BCHP_SWITCH_INTRL2_1_PCI_SET_p1_link_down_intr_DEFAULT 0x00000000
-
-/* SWITCH_INTRL2_1 :: PCI_SET :: p1_link_up_intr [25:25] */
-#define BCHP_SWITCH_INTRL2_1_PCI_SET_p1_link_up_intr_MASK 0x02000000
-#define BCHP_SWITCH_INTRL2_1_PCI_SET_p1_link_up_intr_SHIFT 25
-#define BCHP_SWITCH_INTRL2_1_PCI_SET_p1_link_up_intr_DEFAULT 0x00000000
-
-/* SWITCH_INTRL2_1 :: PCI_SET :: p2_gphy_intr [24:24] */
-#define BCHP_SWITCH_INTRL2_1_PCI_SET_p2_gphy_intr_MASK 0x01000000
-#define BCHP_SWITCH_INTRL2_1_PCI_SET_p2_gphy_intr_SHIFT 24
-#define BCHP_SWITCH_INTRL2_1_PCI_SET_p2_gphy_intr_DEFAULT 0x00000000
-
-/* SWITCH_INTRL2_1 :: PCI_SET :: p2_energy_off_intr [23:23] */
-#define BCHP_SWITCH_INTRL2_1_PCI_SET_p2_energy_off_intr_MASK 0x00800000
-#define BCHP_SWITCH_INTRL2_1_PCI_SET_p2_energy_off_intr_SHIFT 23
-#define BCHP_SWITCH_INTRL2_1_PCI_SET_p2_energy_off_intr_DEFAULT 0x00000000
-
-/* SWITCH_INTRL2_1 :: PCI_SET :: p2_energy_on_intr [22:22] */
-#define BCHP_SWITCH_INTRL2_1_PCI_SET_p2_energy_on_intr_MASK 0x00400000
-#define BCHP_SWITCH_INTRL2_1_PCI_SET_p2_energy_on_intr_SHIFT 22
-#define BCHP_SWITCH_INTRL2_1_PCI_SET_p2_energy_on_intr_DEFAULT 0x00000000
-
-/* SWITCH_INTRL2_1 :: PCI_SET :: p2_link_down_intr [21:21] */
-#define BCHP_SWITCH_INTRL2_1_PCI_SET_p2_link_down_intr_MASK 0x00200000
-#define BCHP_SWITCH_INTRL2_1_PCI_SET_p2_link_down_intr_SHIFT 21
-#define BCHP_SWITCH_INTRL2_1_PCI_SET_p2_link_down_intr_DEFAULT 0x00000000
-
-/* SWITCH_INTRL2_1 :: PCI_SET :: p2_link_up_intr [20:20] */
-#define BCHP_SWITCH_INTRL2_1_PCI_SET_p2_link_up_intr_MASK 0x00100000
-#define BCHP_SWITCH_INTRL2_1_PCI_SET_p2_link_up_intr_SHIFT 20
-#define BCHP_SWITCH_INTRL2_1_PCI_SET_p2_link_up_intr_DEFAULT 0x00000000
-
-/* SWITCH_INTRL2_1 :: PCI_SET :: p3_gphy_intr [19:19] */
-#define BCHP_SWITCH_INTRL2_1_PCI_SET_p3_gphy_intr_MASK 0x00080000
-#define BCHP_SWITCH_INTRL2_1_PCI_SET_p3_gphy_intr_SHIFT 19
-#define BCHP_SWITCH_INTRL2_1_PCI_SET_p3_gphy_intr_DEFAULT 0x00000000
-
-/* SWITCH_INTRL2_1 :: PCI_SET :: p3_energy_off_intr [18:18] */
-#define BCHP_SWITCH_INTRL2_1_PCI_SET_p3_energy_off_intr_MASK 0x00040000
-#define BCHP_SWITCH_INTRL2_1_PCI_SET_p3_energy_off_intr_SHIFT 18
-#define BCHP_SWITCH_INTRL2_1_PCI_SET_p3_energy_off_intr_DEFAULT 0x00000000
-
-/* SWITCH_INTRL2_1 :: PCI_SET :: p3_energy_on_intr [17:17] */
-#define BCHP_SWITCH_INTRL2_1_PCI_SET_p3_energy_on_intr_MASK 0x00020000
-#define BCHP_SWITCH_INTRL2_1_PCI_SET_p3_energy_on_intr_SHIFT 17
-#define BCHP_SWITCH_INTRL2_1_PCI_SET_p3_energy_on_intr_DEFAULT 0x00000000
-
-/* SWITCH_INTRL2_1 :: PCI_SET :: p3_link_down_intr [16:16] */
-#define BCHP_SWITCH_INTRL2_1_PCI_SET_p3_link_down_intr_MASK 0x00010000
-#define BCHP_SWITCH_INTRL2_1_PCI_SET_p3_link_down_intr_SHIFT 16
-#define BCHP_SWITCH_INTRL2_1_PCI_SET_p3_link_down_intr_DEFAULT 0x00000000
-
-/* SWITCH_INTRL2_1 :: PCI_SET :: p3_link_up_intr [15:15] */
-#define BCHP_SWITCH_INTRL2_1_PCI_SET_p3_link_up_intr_MASK 0x00008000
-#define BCHP_SWITCH_INTRL2_1_PCI_SET_p3_link_up_intr_SHIFT 15
-#define BCHP_SWITCH_INTRL2_1_PCI_SET_p3_link_up_intr_DEFAULT 0x00000000
-
-/* SWITCH_INTRL2_1 :: PCI_SET :: p4_gphy_intr [14:14] */
-#define BCHP_SWITCH_INTRL2_1_PCI_SET_p4_gphy_intr_MASK 0x00004000
-#define BCHP_SWITCH_INTRL2_1_PCI_SET_p4_gphy_intr_SHIFT 14
-#define BCHP_SWITCH_INTRL2_1_PCI_SET_p4_gphy_intr_DEFAULT 0x00000000
-
-/* SWITCH_INTRL2_1 :: PCI_SET :: p4_energy_off_intr [13:13] */
-#define BCHP_SWITCH_INTRL2_1_PCI_SET_p4_energy_off_intr_MASK 0x00002000
-#define BCHP_SWITCH_INTRL2_1_PCI_SET_p4_energy_off_intr_SHIFT 13
-#define BCHP_SWITCH_INTRL2_1_PCI_SET_p4_energy_off_intr_DEFAULT 0x00000000
-
-/* SWITCH_INTRL2_1 :: PCI_SET :: p4_energy_on_intr [12:12] */
-#define BCHP_SWITCH_INTRL2_1_PCI_SET_p4_energy_on_intr_MASK 0x00001000
-#define BCHP_SWITCH_INTRL2_1_PCI_SET_p4_energy_on_intr_SHIFT 12
-#define BCHP_SWITCH_INTRL2_1_PCI_SET_p4_energy_on_intr_DEFAULT 0x00000000
-
-/* SWITCH_INTRL2_1 :: PCI_SET :: p4_link_down_intr [11:11] */
-#define BCHP_SWITCH_INTRL2_1_PCI_SET_p4_link_down_intr_MASK 0x00000800
-#define BCHP_SWITCH_INTRL2_1_PCI_SET_p4_link_down_intr_SHIFT 11
-#define BCHP_SWITCH_INTRL2_1_PCI_SET_p4_link_down_intr_DEFAULT 0x00000000
-
-/* SWITCH_INTRL2_1 :: PCI_SET :: p4_link_up_intr [10:10] */
-#define BCHP_SWITCH_INTRL2_1_PCI_SET_p4_link_up_intr_MASK 0x00000400
-#define BCHP_SWITCH_INTRL2_1_PCI_SET_p4_link_up_intr_SHIFT 10
-#define BCHP_SWITCH_INTRL2_1_PCI_SET_p4_link_up_intr_DEFAULT 0x00000000
-
-/* SWITCH_INTRL2_1 :: PCI_SET :: p5_gphy_intr [09:09] */
-#define BCHP_SWITCH_INTRL2_1_PCI_SET_p5_gphy_intr_MASK 0x00000200
-#define BCHP_SWITCH_INTRL2_1_PCI_SET_p5_gphy_intr_SHIFT 9
-#define BCHP_SWITCH_INTRL2_1_PCI_SET_p5_gphy_intr_DEFAULT 0x00000000
-
-/* SWITCH_INTRL2_1 :: PCI_SET :: p5_energy_off_intr [08:08] */
-#define BCHP_SWITCH_INTRL2_1_PCI_SET_p5_energy_off_intr_MASK 0x00000100
-#define BCHP_SWITCH_INTRL2_1_PCI_SET_p5_energy_off_intr_SHIFT 8
-#define BCHP_SWITCH_INTRL2_1_PCI_SET_p5_energy_off_intr_DEFAULT 0x00000000
-
-/* SWITCH_INTRL2_1 :: PCI_SET :: p5_energy_on_intr [07:07] */
-#define BCHP_SWITCH_INTRL2_1_PCI_SET_p5_energy_on_intr_MASK 0x00000080
-#define BCHP_SWITCH_INTRL2_1_PCI_SET_p5_energy_on_intr_SHIFT 7
-#define BCHP_SWITCH_INTRL2_1_PCI_SET_p5_energy_on_intr_DEFAULT 0x00000000
-
-/* SWITCH_INTRL2_1 :: PCI_SET :: p5_link_down_intr [06:06] */
-#define BCHP_SWITCH_INTRL2_1_PCI_SET_p5_link_down_intr_MASK 0x00000040
-#define BCHP_SWITCH_INTRL2_1_PCI_SET_p5_link_down_intr_SHIFT 6
-#define BCHP_SWITCH_INTRL2_1_PCI_SET_p5_link_down_intr_DEFAULT 0x00000000
-
-/* SWITCH_INTRL2_1 :: PCI_SET :: p5_link_up_intr [05:05] */
-#define BCHP_SWITCH_INTRL2_1_PCI_SET_p5_link_up_intr_MASK 0x00000020
-#define BCHP_SWITCH_INTRL2_1_PCI_SET_p5_link_up_intr_SHIFT 5
-#define BCHP_SWITCH_INTRL2_1_PCI_SET_p5_link_up_intr_DEFAULT 0x00000000
-
-/* SWITCH_INTRL2_1 :: PCI_SET :: p7_gphy_intr [04:04] */
-#define BCHP_SWITCH_INTRL2_1_PCI_SET_p7_gphy_intr_MASK 0x00000010
-#define BCHP_SWITCH_INTRL2_1_PCI_SET_p7_gphy_intr_SHIFT 4
-#define BCHP_SWITCH_INTRL2_1_PCI_SET_p7_gphy_intr_DEFAULT 0x00000000
-
-/* SWITCH_INTRL2_1 :: PCI_SET :: p7_energy_off_intr [03:03] */
-#define BCHP_SWITCH_INTRL2_1_PCI_SET_p7_energy_off_intr_MASK 0x00000008
-#define BCHP_SWITCH_INTRL2_1_PCI_SET_p7_energy_off_intr_SHIFT 3
-#define BCHP_SWITCH_INTRL2_1_PCI_SET_p7_energy_off_intr_DEFAULT 0x00000000
-
-/* SWITCH_INTRL2_1 :: PCI_SET :: p7_energy_on_intr [02:02] */
-#define BCHP_SWITCH_INTRL2_1_PCI_SET_p7_energy_on_intr_MASK 0x00000004
-#define BCHP_SWITCH_INTRL2_1_PCI_SET_p7_energy_on_intr_SHIFT 2
-#define BCHP_SWITCH_INTRL2_1_PCI_SET_p7_energy_on_intr_DEFAULT 0x00000000
-
-/* SWITCH_INTRL2_1 :: PCI_SET :: p7_link_down_intr [01:01] */
-#define BCHP_SWITCH_INTRL2_1_PCI_SET_p7_link_down_intr_MASK 0x00000002
-#define BCHP_SWITCH_INTRL2_1_PCI_SET_p7_link_down_intr_SHIFT 1
-#define BCHP_SWITCH_INTRL2_1_PCI_SET_p7_link_down_intr_DEFAULT 0x00000000
-
-/* SWITCH_INTRL2_1 :: PCI_SET :: p7_link_up_intr [00:00] */
-#define BCHP_SWITCH_INTRL2_1_PCI_SET_p7_link_up_intr_MASK 0x00000001
-#define BCHP_SWITCH_INTRL2_1_PCI_SET_p7_link_up_intr_SHIFT 0
-#define BCHP_SWITCH_INTRL2_1_PCI_SET_p7_link_up_intr_DEFAULT 0x00000000
-
-/***************************************************************************
- *PCI_CLEAR - PCI interrupt Clear Register
- ***************************************************************************/
-/* SWITCH_INTRL2_1 :: PCI_CLEAR :: reserved0 [31:30] */
-#define BCHP_SWITCH_INTRL2_1_PCI_CLEAR_reserved0_MASK 0xc0000000
-#define BCHP_SWITCH_INTRL2_1_PCI_CLEAR_reserved0_SHIFT 30
-
-/* SWITCH_INTRL2_1 :: PCI_CLEAR :: p1_gphy_intr [29:29] */
-#define BCHP_SWITCH_INTRL2_1_PCI_CLEAR_p1_gphy_intr_MASK 0x20000000
-#define BCHP_SWITCH_INTRL2_1_PCI_CLEAR_p1_gphy_intr_SHIFT 29
-#define BCHP_SWITCH_INTRL2_1_PCI_CLEAR_p1_gphy_intr_DEFAULT 0x00000000
-
-/* SWITCH_INTRL2_1 :: PCI_CLEAR :: p1_energy_off_intr [28:28] */
-#define BCHP_SWITCH_INTRL2_1_PCI_CLEAR_p1_energy_off_intr_MASK 0x10000000
-#define BCHP_SWITCH_INTRL2_1_PCI_CLEAR_p1_energy_off_intr_SHIFT 28
-#define BCHP_SWITCH_INTRL2_1_PCI_CLEAR_p1_energy_off_intr_DEFAULT 0x00000000
-
-/* SWITCH_INTRL2_1 :: PCI_CLEAR :: p1_energy_on_intr [27:27] */
-#define BCHP_SWITCH_INTRL2_1_PCI_CLEAR_p1_energy_on_intr_MASK 0x08000000
-#define BCHP_SWITCH_INTRL2_1_PCI_CLEAR_p1_energy_on_intr_SHIFT 27
-#define BCHP_SWITCH_INTRL2_1_PCI_CLEAR_p1_energy_on_intr_DEFAULT 0x00000000
-
-/* SWITCH_INTRL2_1 :: PCI_CLEAR :: p1_link_down_intr [26:26] */
-#define BCHP_SWITCH_INTRL2_1_PCI_CLEAR_p1_link_down_intr_MASK 0x04000000
-#define BCHP_SWITCH_INTRL2_1_PCI_CLEAR_p1_link_down_intr_SHIFT 26
-#define BCHP_SWITCH_INTRL2_1_PCI_CLEAR_p1_link_down_intr_DEFAULT 0x00000000
-
-/* SWITCH_INTRL2_1 :: PCI_CLEAR :: p1_link_up_intr [25:25] */
-#define BCHP_SWITCH_INTRL2_1_PCI_CLEAR_p1_link_up_intr_MASK 0x02000000
-#define BCHP_SWITCH_INTRL2_1_PCI_CLEAR_p1_link_up_intr_SHIFT 25
-#define BCHP_SWITCH_INTRL2_1_PCI_CLEAR_p1_link_up_intr_DEFAULT 0x00000000
-
-/* SWITCH_INTRL2_1 :: PCI_CLEAR :: p2_gphy_intr [24:24] */
-#define BCHP_SWITCH_INTRL2_1_PCI_CLEAR_p2_gphy_intr_MASK 0x01000000
-#define BCHP_SWITCH_INTRL2_1_PCI_CLEAR_p2_gphy_intr_SHIFT 24
-#define BCHP_SWITCH_INTRL2_1_PCI_CLEAR_p2_gphy_intr_DEFAULT 0x00000000
-
-/* SWITCH_INTRL2_1 :: PCI_CLEAR :: p2_energy_off_intr [23:23] */
-#define BCHP_SWITCH_INTRL2_1_PCI_CLEAR_p2_energy_off_intr_MASK 0x00800000
-#define BCHP_SWITCH_INTRL2_1_PCI_CLEAR_p2_energy_off_intr_SHIFT 23
-#define BCHP_SWITCH_INTRL2_1_PCI_CLEAR_p2_energy_off_intr_DEFAULT 0x00000000
-
-/* SWITCH_INTRL2_1 :: PCI_CLEAR :: p2_energy_on_intr [22:22] */
-#define BCHP_SWITCH_INTRL2_1_PCI_CLEAR_p2_energy_on_intr_MASK 0x00400000
-#define BCHP_SWITCH_INTRL2_1_PCI_CLEAR_p2_energy_on_intr_SHIFT 22
-#define BCHP_SWITCH_INTRL2_1_PCI_CLEAR_p2_energy_on_intr_DEFAULT 0x00000000
-
-/* SWITCH_INTRL2_1 :: PCI_CLEAR :: p2_link_down_intr [21:21] */
-#define BCHP_SWITCH_INTRL2_1_PCI_CLEAR_p2_link_down_intr_MASK 0x00200000
-#define BCHP_SWITCH_INTRL2_1_PCI_CLEAR_p2_link_down_intr_SHIFT 21
-#define BCHP_SWITCH_INTRL2_1_PCI_CLEAR_p2_link_down_intr_DEFAULT 0x00000000
-
-/* SWITCH_INTRL2_1 :: PCI_CLEAR :: p2_link_up_intr [20:20] */
-#define BCHP_SWITCH_INTRL2_1_PCI_CLEAR_p2_link_up_intr_MASK 0x00100000
-#define BCHP_SWITCH_INTRL2_1_PCI_CLEAR_p2_link_up_intr_SHIFT 20
-#define BCHP_SWITCH_INTRL2_1_PCI_CLEAR_p2_link_up_intr_DEFAULT 0x00000000
-
-/* SWITCH_INTRL2_1 :: PCI_CLEAR :: p3_gphy_intr [19:19] */
-#define BCHP_SWITCH_INTRL2_1_PCI_CLEAR_p3_gphy_intr_MASK 0x00080000
-#define BCHP_SWITCH_INTRL2_1_PCI_CLEAR_p3_gphy_intr_SHIFT 19
-#define BCHP_SWITCH_INTRL2_1_PCI_CLEAR_p3_gphy_intr_DEFAULT 0x00000000
-
-/* SWITCH_INTRL2_1 :: PCI_CLEAR :: p3_energy_off_intr [18:18] */
-#define BCHP_SWITCH_INTRL2_1_PCI_CLEAR_p3_energy_off_intr_MASK 0x00040000
-#define BCHP_SWITCH_INTRL2_1_PCI_CLEAR_p3_energy_off_intr_SHIFT 18
-#define BCHP_SWITCH_INTRL2_1_PCI_CLEAR_p3_energy_off_intr_DEFAULT 0x00000000
-
-/* SWITCH_INTRL2_1 :: PCI_CLEAR :: p3_energy_on_intr [17:17] */
-#define BCHP_SWITCH_INTRL2_1_PCI_CLEAR_p3_energy_on_intr_MASK 0x00020000
-#define BCHP_SWITCH_INTRL2_1_PCI_CLEAR_p3_energy_on_intr_SHIFT 17
-#define BCHP_SWITCH_INTRL2_1_PCI_CLEAR_p3_energy_on_intr_DEFAULT 0x00000000
-
-/* SWITCH_INTRL2_1 :: PCI_CLEAR :: p3_link_down_intr [16:16] */
-#define BCHP_SWITCH_INTRL2_1_PCI_CLEAR_p3_link_down_intr_MASK 0x00010000
-#define BCHP_SWITCH_INTRL2_1_PCI_CLEAR_p3_link_down_intr_SHIFT 16
-#define BCHP_SWITCH_INTRL2_1_PCI_CLEAR_p3_link_down_intr_DEFAULT 0x00000000
-
-/* SWITCH_INTRL2_1 :: PCI_CLEAR :: p3_link_up_intr [15:15] */
-#define BCHP_SWITCH_INTRL2_1_PCI_CLEAR_p3_link_up_intr_MASK 0x00008000
-#define BCHP_SWITCH_INTRL2_1_PCI_CLEAR_p3_link_up_intr_SHIFT 15
-#define BCHP_SWITCH_INTRL2_1_PCI_CLEAR_p3_link_up_intr_DEFAULT 0x00000000
-
-/* SWITCH_INTRL2_1 :: PCI_CLEAR :: p4_gphy_intr [14:14] */
-#define BCHP_SWITCH_INTRL2_1_PCI_CLEAR_p4_gphy_intr_MASK 0x00004000
-#define BCHP_SWITCH_INTRL2_1_PCI_CLEAR_p4_gphy_intr_SHIFT 14
-#define BCHP_SWITCH_INTRL2_1_PCI_CLEAR_p4_gphy_intr_DEFAULT 0x00000000
-
-/* SWITCH_INTRL2_1 :: PCI_CLEAR :: p4_energy_off_intr [13:13] */
-#define BCHP_SWITCH_INTRL2_1_PCI_CLEAR_p4_energy_off_intr_MASK 0x00002000
-#define BCHP_SWITCH_INTRL2_1_PCI_CLEAR_p4_energy_off_intr_SHIFT 13
-#define BCHP_SWITCH_INTRL2_1_PCI_CLEAR_p4_energy_off_intr_DEFAULT 0x00000000
-
-/* SWITCH_INTRL2_1 :: PCI_CLEAR :: p4_energy_on_intr [12:12] */
-#define BCHP_SWITCH_INTRL2_1_PCI_CLEAR_p4_energy_on_intr_MASK 0x00001000
-#define BCHP_SWITCH_INTRL2_1_PCI_CLEAR_p4_energy_on_intr_SHIFT 12
-#define BCHP_SWITCH_INTRL2_1_PCI_CLEAR_p4_energy_on_intr_DEFAULT 0x00000000
-
-/* SWITCH_INTRL2_1 :: PCI_CLEAR :: p4_link_down_intr [11:11] */
-#define BCHP_SWITCH_INTRL2_1_PCI_CLEAR_p4_link_down_intr_MASK 0x00000800
-#define BCHP_SWITCH_INTRL2_1_PCI_CLEAR_p4_link_down_intr_SHIFT 11
-#define BCHP_SWITCH_INTRL2_1_PCI_CLEAR_p4_link_down_intr_DEFAULT 0x00000000
-
-/* SWITCH_INTRL2_1 :: PCI_CLEAR :: p4_link_up_intr [10:10] */
-#define BCHP_SWITCH_INTRL2_1_PCI_CLEAR_p4_link_up_intr_MASK 0x00000400
-#define BCHP_SWITCH_INTRL2_1_PCI_CLEAR_p4_link_up_intr_SHIFT 10
-#define BCHP_SWITCH_INTRL2_1_PCI_CLEAR_p4_link_up_intr_DEFAULT 0x00000000
-
-/* SWITCH_INTRL2_1 :: PCI_CLEAR :: p5_gphy_intr [09:09] */
-#define BCHP_SWITCH_INTRL2_1_PCI_CLEAR_p5_gphy_intr_MASK 0x00000200
-#define BCHP_SWITCH_INTRL2_1_PCI_CLEAR_p5_gphy_intr_SHIFT 9
-#define BCHP_SWITCH_INTRL2_1_PCI_CLEAR_p5_gphy_intr_DEFAULT 0x00000000
-
-/* SWITCH_INTRL2_1 :: PCI_CLEAR :: p5_energy_off_intr [08:08] */
-#define BCHP_SWITCH_INTRL2_1_PCI_CLEAR_p5_energy_off_intr_MASK 0x00000100
-#define BCHP_SWITCH_INTRL2_1_PCI_CLEAR_p5_energy_off_intr_SHIFT 8
-#define BCHP_SWITCH_INTRL2_1_PCI_CLEAR_p5_energy_off_intr_DEFAULT 0x00000000
-
-/* SWITCH_INTRL2_1 :: PCI_CLEAR :: p5_energy_on_intr [07:07] */
-#define BCHP_SWITCH_INTRL2_1_PCI_CLEAR_p5_energy_on_intr_MASK 0x00000080
-#define BCHP_SWITCH_INTRL2_1_PCI_CLEAR_p5_energy_on_intr_SHIFT 7
-#define BCHP_SWITCH_INTRL2_1_PCI_CLEAR_p5_energy_on_intr_DEFAULT 0x00000000
-
-/* SWITCH_INTRL2_1 :: PCI_CLEAR :: p5_link_down_intr [06:06] */
-#define BCHP_SWITCH_INTRL2_1_PCI_CLEAR_p5_link_down_intr_MASK 0x00000040
-#define BCHP_SWITCH_INTRL2_1_PCI_CLEAR_p5_link_down_intr_SHIFT 6
-#define BCHP_SWITCH_INTRL2_1_PCI_CLEAR_p5_link_down_intr_DEFAULT 0x00000000
-
-/* SWITCH_INTRL2_1 :: PCI_CLEAR :: p5_link_up_intr [05:05] */
-#define BCHP_SWITCH_INTRL2_1_PCI_CLEAR_p5_link_up_intr_MASK 0x00000020
-#define BCHP_SWITCH_INTRL2_1_PCI_CLEAR_p5_link_up_intr_SHIFT 5
-#define BCHP_SWITCH_INTRL2_1_PCI_CLEAR_p5_link_up_intr_DEFAULT 0x00000000
-
-/* SWITCH_INTRL2_1 :: PCI_CLEAR :: p7_gphy_intr [04:04] */
-#define BCHP_SWITCH_INTRL2_1_PCI_CLEAR_p7_gphy_intr_MASK 0x00000010
-#define BCHP_SWITCH_INTRL2_1_PCI_CLEAR_p7_gphy_intr_SHIFT 4
-#define BCHP_SWITCH_INTRL2_1_PCI_CLEAR_p7_gphy_intr_DEFAULT 0x00000000
-
-/* SWITCH_INTRL2_1 :: PCI_CLEAR :: p7_energy_off_intr [03:03] */
-#define BCHP_SWITCH_INTRL2_1_PCI_CLEAR_p7_energy_off_intr_MASK 0x00000008
-#define BCHP_SWITCH_INTRL2_1_PCI_CLEAR_p7_energy_off_intr_SHIFT 3
-#define BCHP_SWITCH_INTRL2_1_PCI_CLEAR_p7_energy_off_intr_DEFAULT 0x00000000
-
-/* SWITCH_INTRL2_1 :: PCI_CLEAR :: p7_energy_on_intr [02:02] */
-#define BCHP_SWITCH_INTRL2_1_PCI_CLEAR_p7_energy_on_intr_MASK 0x00000004
-#define BCHP_SWITCH_INTRL2_1_PCI_CLEAR_p7_energy_on_intr_SHIFT 2
-#define BCHP_SWITCH_INTRL2_1_PCI_CLEAR_p7_energy_on_intr_DEFAULT 0x00000000
-
-/* SWITCH_INTRL2_1 :: PCI_CLEAR :: p7_link_down_intr [01:01] */
-#define BCHP_SWITCH_INTRL2_1_PCI_CLEAR_p7_link_down_intr_MASK 0x00000002
-#define BCHP_SWITCH_INTRL2_1_PCI_CLEAR_p7_link_down_intr_SHIFT 1
-#define BCHP_SWITCH_INTRL2_1_PCI_CLEAR_p7_link_down_intr_DEFAULT 0x00000000
-
-/* SWITCH_INTRL2_1 :: PCI_CLEAR :: p7_link_up_intr [00:00] */
-#define BCHP_SWITCH_INTRL2_1_PCI_CLEAR_p7_link_up_intr_MASK 0x00000001
-#define BCHP_SWITCH_INTRL2_1_PCI_CLEAR_p7_link_up_intr_SHIFT 0
-#define BCHP_SWITCH_INTRL2_1_PCI_CLEAR_p7_link_up_intr_DEFAULT 0x00000000
-
-/***************************************************************************
- *PCI_MASK_STATUS - PCI interrupt Mask Status Register
- ***************************************************************************/
-/* SWITCH_INTRL2_1 :: PCI_MASK_STATUS :: reserved0 [31:30] */
-#define BCHP_SWITCH_INTRL2_1_PCI_MASK_STATUS_reserved0_MASK 0xc0000000
-#define BCHP_SWITCH_INTRL2_1_PCI_MASK_STATUS_reserved0_SHIFT 30
-
-/* SWITCH_INTRL2_1 :: PCI_MASK_STATUS :: p1_gphy_intr_mask [29:29] */
-#define BCHP_SWITCH_INTRL2_1_PCI_MASK_STATUS_p1_gphy_intr_mask_MASK 0x20000000
-#define BCHP_SWITCH_INTRL2_1_PCI_MASK_STATUS_p1_gphy_intr_mask_SHIFT 29
-#define BCHP_SWITCH_INTRL2_1_PCI_MASK_STATUS_p1_gphy_intr_mask_DEFAULT 0x00000001
-
-/* SWITCH_INTRL2_1 :: PCI_MASK_STATUS :: p1_energy_off_intr_mask [28:28] */
-#define BCHP_SWITCH_INTRL2_1_PCI_MASK_STATUS_p1_energy_off_intr_mask_MASK 0x10000000
-#define BCHP_SWITCH_INTRL2_1_PCI_MASK_STATUS_p1_energy_off_intr_mask_SHIFT 28
-#define BCHP_SWITCH_INTRL2_1_PCI_MASK_STATUS_p1_energy_off_intr_mask_DEFAULT 0x00000001
-
-/* SWITCH_INTRL2_1 :: PCI_MASK_STATUS :: p1_energy_on_intr_mask [27:27] */
-#define BCHP_SWITCH_INTRL2_1_PCI_MASK_STATUS_p1_energy_on_intr_mask_MASK 0x08000000
-#define BCHP_SWITCH_INTRL2_1_PCI_MASK_STATUS_p1_energy_on_intr_mask_SHIFT 27
-#define BCHP_SWITCH_INTRL2_1_PCI_MASK_STATUS_p1_energy_on_intr_mask_DEFAULT 0x00000001
-
-/* SWITCH_INTRL2_1 :: PCI_MASK_STATUS :: p1_link_down_intr_mask [26:26] */
-#define BCHP_SWITCH_INTRL2_1_PCI_MASK_STATUS_p1_link_down_intr_mask_MASK 0x04000000
-#define BCHP_SWITCH_INTRL2_1_PCI_MASK_STATUS_p1_link_down_intr_mask_SHIFT 26
-#define BCHP_SWITCH_INTRL2_1_PCI_MASK_STATUS_p1_link_down_intr_mask_DEFAULT 0x00000001
-
-/* SWITCH_INTRL2_1 :: PCI_MASK_STATUS :: p1_link_up_intr_mask [25:25] */
-#define BCHP_SWITCH_INTRL2_1_PCI_MASK_STATUS_p1_link_up_intr_mask_MASK 0x02000000
-#define BCHP_SWITCH_INTRL2_1_PCI_MASK_STATUS_p1_link_up_intr_mask_SHIFT 25
-#define BCHP_SWITCH_INTRL2_1_PCI_MASK_STATUS_p1_link_up_intr_mask_DEFAULT 0x00000001
-
-/* SWITCH_INTRL2_1 :: PCI_MASK_STATUS :: p2_gphy_intr_mask [24:24] */
-#define BCHP_SWITCH_INTRL2_1_PCI_MASK_STATUS_p2_gphy_intr_mask_MASK 0x01000000
-#define BCHP_SWITCH_INTRL2_1_PCI_MASK_STATUS_p2_gphy_intr_mask_SHIFT 24
-#define BCHP_SWITCH_INTRL2_1_PCI_MASK_STATUS_p2_gphy_intr_mask_DEFAULT 0x00000001
-
-/* SWITCH_INTRL2_1 :: PCI_MASK_STATUS :: p2_energy_off_intr_mask [23:23] */
-#define BCHP_SWITCH_INTRL2_1_PCI_MASK_STATUS_p2_energy_off_intr_mask_MASK 0x00800000
-#define BCHP_SWITCH_INTRL2_1_PCI_MASK_STATUS_p2_energy_off_intr_mask_SHIFT 23
-#define BCHP_SWITCH_INTRL2_1_PCI_MASK_STATUS_p2_energy_off_intr_mask_DEFAULT 0x00000001
-
-/* SWITCH_INTRL2_1 :: PCI_MASK_STATUS :: p2_energy_on_intr_mask [22:22] */
-#define BCHP_SWITCH_INTRL2_1_PCI_MASK_STATUS_p2_energy_on_intr_mask_MASK 0x00400000
-#define BCHP_SWITCH_INTRL2_1_PCI_MASK_STATUS_p2_energy_on_intr_mask_SHIFT 22
-#define BCHP_SWITCH_INTRL2_1_PCI_MASK_STATUS_p2_energy_on_intr_mask_DEFAULT 0x00000001
-
-/* SWITCH_INTRL2_1 :: PCI_MASK_STATUS :: p2_link_down_intr_mask [21:21] */
-#define BCHP_SWITCH_INTRL2_1_PCI_MASK_STATUS_p2_link_down_intr_mask_MASK 0x00200000
-#define BCHP_SWITCH_INTRL2_1_PCI_MASK_STATUS_p2_link_down_intr_mask_SHIFT 21
-#define BCHP_SWITCH_INTRL2_1_PCI_MASK_STATUS_p2_link_down_intr_mask_DEFAULT 0x00000001
-
-/* SWITCH_INTRL2_1 :: PCI_MASK_STATUS :: p2_link_up_intr_mask [20:20] */
-#define BCHP_SWITCH_INTRL2_1_PCI_MASK_STATUS_p2_link_up_intr_mask_MASK 0x00100000
-#define BCHP_SWITCH_INTRL2_1_PCI_MASK_STATUS_p2_link_up_intr_mask_SHIFT 20
-#define BCHP_SWITCH_INTRL2_1_PCI_MASK_STATUS_p2_link_up_intr_mask_DEFAULT 0x00000001
-
-/* SWITCH_INTRL2_1 :: PCI_MASK_STATUS :: p3_gphy_intr_mask [19:19] */
-#define BCHP_SWITCH_INTRL2_1_PCI_MASK_STATUS_p3_gphy_intr_mask_MASK 0x00080000
-#define BCHP_SWITCH_INTRL2_1_PCI_MASK_STATUS_p3_gphy_intr_mask_SHIFT 19
-#define BCHP_SWITCH_INTRL2_1_PCI_MASK_STATUS_p3_gphy_intr_mask_DEFAULT 0x00000001
-
-/* SWITCH_INTRL2_1 :: PCI_MASK_STATUS :: p3_energy_off_intr_mask [18:18] */
-#define BCHP_SWITCH_INTRL2_1_PCI_MASK_STATUS_p3_energy_off_intr_mask_MASK 0x00040000
-#define BCHP_SWITCH_INTRL2_1_PCI_MASK_STATUS_p3_energy_off_intr_mask_SHIFT 18
-#define BCHP_SWITCH_INTRL2_1_PCI_MASK_STATUS_p3_energy_off_intr_mask_DEFAULT 0x00000001
-
-/* SWITCH_INTRL2_1 :: PCI_MASK_STATUS :: p3_energy_on_intr_mask [17:17] */
-#define BCHP_SWITCH_INTRL2_1_PCI_MASK_STATUS_p3_energy_on_intr_mask_MASK 0x00020000
-#define BCHP_SWITCH_INTRL2_1_PCI_MASK_STATUS_p3_energy_on_intr_mask_SHIFT 17
-#define BCHP_SWITCH_INTRL2_1_PCI_MASK_STATUS_p3_energy_on_intr_mask_DEFAULT 0x00000001
-
-/* SWITCH_INTRL2_1 :: PCI_MASK_STATUS :: p3_link_down_intr_mask [16:16] */
-#define BCHP_SWITCH_INTRL2_1_PCI_MASK_STATUS_p3_link_down_intr_mask_MASK 0x00010000
-#define BCHP_SWITCH_INTRL2_1_PCI_MASK_STATUS_p3_link_down_intr_mask_SHIFT 16
-#define BCHP_SWITCH_INTRL2_1_PCI_MASK_STATUS_p3_link_down_intr_mask_DEFAULT 0x00000001
-
-/* SWITCH_INTRL2_1 :: PCI_MASK_STATUS :: p3_link_up_intr_mask [15:15] */
-#define BCHP_SWITCH_INTRL2_1_PCI_MASK_STATUS_p3_link_up_intr_mask_MASK 0x00008000
-#define BCHP_SWITCH_INTRL2_1_PCI_MASK_STATUS_p3_link_up_intr_mask_SHIFT 15
-#define BCHP_SWITCH_INTRL2_1_PCI_MASK_STATUS_p3_link_up_intr_mask_DEFAULT 0x00000001
-
-/* SWITCH_INTRL2_1 :: PCI_MASK_STATUS :: p4_gphy_intr_mask [14:14] */
-#define BCHP_SWITCH_INTRL2_1_PCI_MASK_STATUS_p4_gphy_intr_mask_MASK 0x00004000
-#define BCHP_SWITCH_INTRL2_1_PCI_MASK_STATUS_p4_gphy_intr_mask_SHIFT 14
-#define BCHP_SWITCH_INTRL2_1_PCI_MASK_STATUS_p4_gphy_intr_mask_DEFAULT 0x00000001
-
-/* SWITCH_INTRL2_1 :: PCI_MASK_STATUS :: p4_energy_off_intr_mask [13:13] */
-#define BCHP_SWITCH_INTRL2_1_PCI_MASK_STATUS_p4_energy_off_intr_mask_MASK 0x00002000
-#define BCHP_SWITCH_INTRL2_1_PCI_MASK_STATUS_p4_energy_off_intr_mask_SHIFT 13
-#define BCHP_SWITCH_INTRL2_1_PCI_MASK_STATUS_p4_energy_off_intr_mask_DEFAULT 0x00000001
-
-/* SWITCH_INTRL2_1 :: PCI_MASK_STATUS :: p4_energy_on_intr_mask [12:12] */
-#define BCHP_SWITCH_INTRL2_1_PCI_MASK_STATUS_p4_energy_on_intr_mask_MASK 0x00001000
-#define BCHP_SWITCH_INTRL2_1_PCI_MASK_STATUS_p4_energy_on_intr_mask_SHIFT 12
-#define BCHP_SWITCH_INTRL2_1_PCI_MASK_STATUS_p4_energy_on_intr_mask_DEFAULT 0x00000001
-
-/* SWITCH_INTRL2_1 :: PCI_MASK_STATUS :: p4_link_down_intr_mask [11:11] */
-#define BCHP_SWITCH_INTRL2_1_PCI_MASK_STATUS_p4_link_down_intr_mask_MASK 0x00000800
-#define BCHP_SWITCH_INTRL2_1_PCI_MASK_STATUS_p4_link_down_intr_mask_SHIFT 11
-#define BCHP_SWITCH_INTRL2_1_PCI_MASK_STATUS_p4_link_down_intr_mask_DEFAULT 0x00000001
-
-/* SWITCH_INTRL2_1 :: PCI_MASK_STATUS :: p4_link_up_intr_mask [10:10] */
-#define BCHP_SWITCH_INTRL2_1_PCI_MASK_STATUS_p4_link_up_intr_mask_MASK 0x00000400
-#define BCHP_SWITCH_INTRL2_1_PCI_MASK_STATUS_p4_link_up_intr_mask_SHIFT 10
-#define BCHP_SWITCH_INTRL2_1_PCI_MASK_STATUS_p4_link_up_intr_mask_DEFAULT 0x00000001
-
-/* SWITCH_INTRL2_1 :: PCI_MASK_STATUS :: p5_gphy_intr_mask [09:09] */
-#define BCHP_SWITCH_INTRL2_1_PCI_MASK_STATUS_p5_gphy_intr_mask_MASK 0x00000200
-#define BCHP_SWITCH_INTRL2_1_PCI_MASK_STATUS_p5_gphy_intr_mask_SHIFT 9
-#define BCHP_SWITCH_INTRL2_1_PCI_MASK_STATUS_p5_gphy_intr_mask_DEFAULT 0x00000001
-
-/* SWITCH_INTRL2_1 :: PCI_MASK_STATUS :: p5_energy_off_intr_mask [08:08] */
-#define BCHP_SWITCH_INTRL2_1_PCI_MASK_STATUS_p5_energy_off_intr_mask_MASK 0x00000100
-#define BCHP_SWITCH_INTRL2_1_PCI_MASK_STATUS_p5_energy_off_intr_mask_SHIFT 8
-#define BCHP_SWITCH_INTRL2_1_PCI_MASK_STATUS_p5_energy_off_intr_mask_DEFAULT 0x00000001
-
-/* SWITCH_INTRL2_1 :: PCI_MASK_STATUS :: p5_energy_on_intr_mask [07:07] */
-#define BCHP_SWITCH_INTRL2_1_PCI_MASK_STATUS_p5_energy_on_intr_mask_MASK 0x00000080
-#define BCHP_SWITCH_INTRL2_1_PCI_MASK_STATUS_p5_energy_on_intr_mask_SHIFT 7
-#define BCHP_SWITCH_INTRL2_1_PCI_MASK_STATUS_p5_energy_on_intr_mask_DEFAULT 0x00000001
-
-/* SWITCH_INTRL2_1 :: PCI_MASK_STATUS :: p5_link_down_intr_mask [06:06] */
-#define BCHP_SWITCH_INTRL2_1_PCI_MASK_STATUS_p5_link_down_intr_mask_MASK 0x00000040
-#define BCHP_SWITCH_INTRL2_1_PCI_MASK_STATUS_p5_link_down_intr_mask_SHIFT 6
-#define BCHP_SWITCH_INTRL2_1_PCI_MASK_STATUS_p5_link_down_intr_mask_DEFAULT 0x00000001
-
-/* SWITCH_INTRL2_1 :: PCI_MASK_STATUS :: p5_link_up_intr_mask [05:05] */
-#define BCHP_SWITCH_INTRL2_1_PCI_MASK_STATUS_p5_link_up_intr_mask_MASK 0x00000020
-#define BCHP_SWITCH_INTRL2_1_PCI_MASK_STATUS_p5_link_up_intr_mask_SHIFT 5
-#define BCHP_SWITCH_INTRL2_1_PCI_MASK_STATUS_p5_link_up_intr_mask_DEFAULT 0x00000001
-
-/* SWITCH_INTRL2_1 :: PCI_MASK_STATUS :: p7_gphy_intr_mask [04:04] */
-#define BCHP_SWITCH_INTRL2_1_PCI_MASK_STATUS_p7_gphy_intr_mask_MASK 0x00000010
-#define BCHP_SWITCH_INTRL2_1_PCI_MASK_STATUS_p7_gphy_intr_mask_SHIFT 4
-#define BCHP_SWITCH_INTRL2_1_PCI_MASK_STATUS_p7_gphy_intr_mask_DEFAULT 0x00000001
-
-/* SWITCH_INTRL2_1 :: PCI_MASK_STATUS :: p7_energy_off_intr_mask [03:03] */
-#define BCHP_SWITCH_INTRL2_1_PCI_MASK_STATUS_p7_energy_off_intr_mask_MASK 0x00000008
-#define BCHP_SWITCH_INTRL2_1_PCI_MASK_STATUS_p7_energy_off_intr_mask_SHIFT 3
-#define BCHP_SWITCH_INTRL2_1_PCI_MASK_STATUS_p7_energy_off_intr_mask_DEFAULT 0x00000001
-
-/* SWITCH_INTRL2_1 :: PCI_MASK_STATUS :: p7_energy_on_intr_mask [02:02] */
-#define BCHP_SWITCH_INTRL2_1_PCI_MASK_STATUS_p7_energy_on_intr_mask_MASK 0x00000004
-#define BCHP_SWITCH_INTRL2_1_PCI_MASK_STATUS_p7_energy_on_intr_mask_SHIFT 2
-#define BCHP_SWITCH_INTRL2_1_PCI_MASK_STATUS_p7_energy_on_intr_mask_DEFAULT 0x00000001
-
-/* SWITCH_INTRL2_1 :: PCI_MASK_STATUS :: p7_link_down_intr_mask [01:01] */
-#define BCHP_SWITCH_INTRL2_1_PCI_MASK_STATUS_p7_link_down_intr_mask_MASK 0x00000002
-#define BCHP_SWITCH_INTRL2_1_PCI_MASK_STATUS_p7_link_down_intr_mask_SHIFT 1
-#define BCHP_SWITCH_INTRL2_1_PCI_MASK_STATUS_p7_link_down_intr_mask_DEFAULT 0x00000001
-
-/* SWITCH_INTRL2_1 :: PCI_MASK_STATUS :: p7_link_up_intr_mask [00:00] */
-#define BCHP_SWITCH_INTRL2_1_PCI_MASK_STATUS_p7_link_up_intr_mask_MASK 0x00000001
-#define BCHP_SWITCH_INTRL2_1_PCI_MASK_STATUS_p7_link_up_intr_mask_SHIFT 0
-#define BCHP_SWITCH_INTRL2_1_PCI_MASK_STATUS_p7_link_up_intr_mask_DEFAULT 0x00000001
-
-/***************************************************************************
- *PCI_MASK_SET - PCI interrupt Mask Set Register
- ***************************************************************************/
-/* SWITCH_INTRL2_1 :: PCI_MASK_SET :: reserved0 [31:30] */
-#define BCHP_SWITCH_INTRL2_1_PCI_MASK_SET_reserved0_MASK 0xc0000000
-#define BCHP_SWITCH_INTRL2_1_PCI_MASK_SET_reserved0_SHIFT 30
-
-/* SWITCH_INTRL2_1 :: PCI_MASK_SET :: p1_gphy_intr_mask [29:29] */
-#define BCHP_SWITCH_INTRL2_1_PCI_MASK_SET_p1_gphy_intr_mask_MASK 0x20000000
-#define BCHP_SWITCH_INTRL2_1_PCI_MASK_SET_p1_gphy_intr_mask_SHIFT 29
-#define BCHP_SWITCH_INTRL2_1_PCI_MASK_SET_p1_gphy_intr_mask_DEFAULT 0x00000001
-
-/* SWITCH_INTRL2_1 :: PCI_MASK_SET :: p1_energy_off_intr_mask [28:28] */
-#define BCHP_SWITCH_INTRL2_1_PCI_MASK_SET_p1_energy_off_intr_mask_MASK 0x10000000
-#define BCHP_SWITCH_INTRL2_1_PCI_MASK_SET_p1_energy_off_intr_mask_SHIFT 28
-#define BCHP_SWITCH_INTRL2_1_PCI_MASK_SET_p1_energy_off_intr_mask_DEFAULT 0x00000001
-
-/* SWITCH_INTRL2_1 :: PCI_MASK_SET :: p1_energy_on_intr_mask [27:27] */
-#define BCHP_SWITCH_INTRL2_1_PCI_MASK_SET_p1_energy_on_intr_mask_MASK 0x08000000
-#define BCHP_SWITCH_INTRL2_1_PCI_MASK_SET_p1_energy_on_intr_mask_SHIFT 27
-#define BCHP_SWITCH_INTRL2_1_PCI_MASK_SET_p1_energy_on_intr_mask_DEFAULT 0x00000001
-
-/* SWITCH_INTRL2_1 :: PCI_MASK_SET :: p1_link_down_intr_mask [26:26] */
-#define BCHP_SWITCH_INTRL2_1_PCI_MASK_SET_p1_link_down_intr_mask_MASK 0x04000000
-#define BCHP_SWITCH_INTRL2_1_PCI_MASK_SET_p1_link_down_intr_mask_SHIFT 26
-#define BCHP_SWITCH_INTRL2_1_PCI_MASK_SET_p1_link_down_intr_mask_DEFAULT 0x00000001
-
-/* SWITCH_INTRL2_1 :: PCI_MASK_SET :: p1_link_up_intr_mask [25:25] */
-#define BCHP_SWITCH_INTRL2_1_PCI_MASK_SET_p1_link_up_intr_mask_MASK 0x02000000
-#define BCHP_SWITCH_INTRL2_1_PCI_MASK_SET_p1_link_up_intr_mask_SHIFT 25
-#define BCHP_SWITCH_INTRL2_1_PCI_MASK_SET_p1_link_up_intr_mask_DEFAULT 0x00000001
-
-/* SWITCH_INTRL2_1 :: PCI_MASK_SET :: p2_gphy_intr_mask [24:24] */
-#define BCHP_SWITCH_INTRL2_1_PCI_MASK_SET_p2_gphy_intr_mask_MASK 0x01000000
-#define BCHP_SWITCH_INTRL2_1_PCI_MASK_SET_p2_gphy_intr_mask_SHIFT 24
-#define BCHP_SWITCH_INTRL2_1_PCI_MASK_SET_p2_gphy_intr_mask_DEFAULT 0x00000001
-
-/* SWITCH_INTRL2_1 :: PCI_MASK_SET :: p2_energy_off_intr_mask [23:23] */
-#define BCHP_SWITCH_INTRL2_1_PCI_MASK_SET_p2_energy_off_intr_mask_MASK 0x00800000
-#define BCHP_SWITCH_INTRL2_1_PCI_MASK_SET_p2_energy_off_intr_mask_SHIFT 23
-#define BCHP_SWITCH_INTRL2_1_PCI_MASK_SET_p2_energy_off_intr_mask_DEFAULT 0x00000001
-
-/* SWITCH_INTRL2_1 :: PCI_MASK_SET :: p2_energy_on_intr_mask [22:22] */
-#define BCHP_SWITCH_INTRL2_1_PCI_MASK_SET_p2_energy_on_intr_mask_MASK 0x00400000
-#define BCHP_SWITCH_INTRL2_1_PCI_MASK_SET_p2_energy_on_intr_mask_SHIFT 22
-#define BCHP_SWITCH_INTRL2_1_PCI_MASK_SET_p2_energy_on_intr_mask_DEFAULT 0x00000001
-
-/* SWITCH_INTRL2_1 :: PCI_MASK_SET :: p2_link_down_intr_mask [21:21] */
-#define BCHP_SWITCH_INTRL2_1_PCI_MASK_SET_p2_link_down_intr_mask_MASK 0x00200000
-#define BCHP_SWITCH_INTRL2_1_PCI_MASK_SET_p2_link_down_intr_mask_SHIFT 21
-#define BCHP_SWITCH_INTRL2_1_PCI_MASK_SET_p2_link_down_intr_mask_DEFAULT 0x00000001
-
-/* SWITCH_INTRL2_1 :: PCI_MASK_SET :: p2_link_up_intr_mask [20:20] */
-#define BCHP_SWITCH_INTRL2_1_PCI_MASK_SET_p2_link_up_intr_mask_MASK 0x00100000
-#define BCHP_SWITCH_INTRL2_1_PCI_MASK_SET_p2_link_up_intr_mask_SHIFT 20
-#define BCHP_SWITCH_INTRL2_1_PCI_MASK_SET_p2_link_up_intr_mask_DEFAULT 0x00000001
-
-/* SWITCH_INTRL2_1 :: PCI_MASK_SET :: p3_gphy_intr_mask [19:19] */
-#define BCHP_SWITCH_INTRL2_1_PCI_MASK_SET_p3_gphy_intr_mask_MASK 0x00080000
-#define BCHP_SWITCH_INTRL2_1_PCI_MASK_SET_p3_gphy_intr_mask_SHIFT 19
-#define BCHP_SWITCH_INTRL2_1_PCI_MASK_SET_p3_gphy_intr_mask_DEFAULT 0x00000001
-
-/* SWITCH_INTRL2_1 :: PCI_MASK_SET :: p3_energy_off_intr_mask [18:18] */
-#define BCHP_SWITCH_INTRL2_1_PCI_MASK_SET_p3_energy_off_intr_mask_MASK 0x00040000
-#define BCHP_SWITCH_INTRL2_1_PCI_MASK_SET_p3_energy_off_intr_mask_SHIFT 18
-#define BCHP_SWITCH_INTRL2_1_PCI_MASK_SET_p3_energy_off_intr_mask_DEFAULT 0x00000001
-
-/* SWITCH_INTRL2_1 :: PCI_MASK_SET :: p3_energy_on_intr_mask [17:17] */
-#define BCHP_SWITCH_INTRL2_1_PCI_MASK_SET_p3_energy_on_intr_mask_MASK 0x00020000
-#define BCHP_SWITCH_INTRL2_1_PCI_MASK_SET_p3_energy_on_intr_mask_SHIFT 17
-#define BCHP_SWITCH_INTRL2_1_PCI_MASK_SET_p3_energy_on_intr_mask_DEFAULT 0x00000001
-
-/* SWITCH_INTRL2_1 :: PCI_MASK_SET :: p3_link_down_intr_mask [16:16] */
-#define BCHP_SWITCH_INTRL2_1_PCI_MASK_SET_p3_link_down_intr_mask_MASK 0x00010000
-#define BCHP_SWITCH_INTRL2_1_PCI_MASK_SET_p3_link_down_intr_mask_SHIFT 16
-#define BCHP_SWITCH_INTRL2_1_PCI_MASK_SET_p3_link_down_intr_mask_DEFAULT 0x00000001
-
-/* SWITCH_INTRL2_1 :: PCI_MASK_SET :: p3_link_up_intr_mask [15:15] */
-#define BCHP_SWITCH_INTRL2_1_PCI_MASK_SET_p3_link_up_intr_mask_MASK 0x00008000
-#define BCHP_SWITCH_INTRL2_1_PCI_MASK_SET_p3_link_up_intr_mask_SHIFT 15
-#define BCHP_SWITCH_INTRL2_1_PCI_MASK_SET_p3_link_up_intr_mask_DEFAULT 0x00000001
-
-/* SWITCH_INTRL2_1 :: PCI_MASK_SET :: p4_gphy_intr_mask [14:14] */
-#define BCHP_SWITCH_INTRL2_1_PCI_MASK_SET_p4_gphy_intr_mask_MASK 0x00004000
-#define BCHP_SWITCH_INTRL2_1_PCI_MASK_SET_p4_gphy_intr_mask_SHIFT 14
-#define BCHP_SWITCH_INTRL2_1_PCI_MASK_SET_p4_gphy_intr_mask_DEFAULT 0x00000001
-
-/* SWITCH_INTRL2_1 :: PCI_MASK_SET :: p4_energy_off_intr_mask [13:13] */
-#define BCHP_SWITCH_INTRL2_1_PCI_MASK_SET_p4_energy_off_intr_mask_MASK 0x00002000
-#define BCHP_SWITCH_INTRL2_1_PCI_MASK_SET_p4_energy_off_intr_mask_SHIFT 13
-#define BCHP_SWITCH_INTRL2_1_PCI_MASK_SET_p4_energy_off_intr_mask_DEFAULT 0x00000001
-
-/* SWITCH_INTRL2_1 :: PCI_MASK_SET :: p4_energy_on_intr_mask [12:12] */
-#define BCHP_SWITCH_INTRL2_1_PCI_MASK_SET_p4_energy_on_intr_mask_MASK 0x00001000
-#define BCHP_SWITCH_INTRL2_1_PCI_MASK_SET_p4_energy_on_intr_mask_SHIFT 12
-#define BCHP_SWITCH_INTRL2_1_PCI_MASK_SET_p4_energy_on_intr_mask_DEFAULT 0x00000001
-
-/* SWITCH_INTRL2_1 :: PCI_MASK_SET :: p4_link_down_intr_mask [11:11] */
-#define BCHP_SWITCH_INTRL2_1_PCI_MASK_SET_p4_link_down_intr_mask_MASK 0x00000800
-#define BCHP_SWITCH_INTRL2_1_PCI_MASK_SET_p4_link_down_intr_mask_SHIFT 11
-#define BCHP_SWITCH_INTRL2_1_PCI_MASK_SET_p4_link_down_intr_mask_DEFAULT 0x00000001
-
-/* SWITCH_INTRL2_1 :: PCI_MASK_SET :: p4_link_up_intr_mask [10:10] */
-#define BCHP_SWITCH_INTRL2_1_PCI_MASK_SET_p4_link_up_intr_mask_MASK 0x00000400
-#define BCHP_SWITCH_INTRL2_1_PCI_MASK_SET_p4_link_up_intr_mask_SHIFT 10
-#define BCHP_SWITCH_INTRL2_1_PCI_MASK_SET_p4_link_up_intr_mask_DEFAULT 0x00000001
-
-/* SWITCH_INTRL2_1 :: PCI_MASK_SET :: p5_gphy_intr_mask [09:09] */
-#define BCHP_SWITCH_INTRL2_1_PCI_MASK_SET_p5_gphy_intr_mask_MASK 0x00000200
-#define BCHP_SWITCH_INTRL2_1_PCI_MASK_SET_p5_gphy_intr_mask_SHIFT 9
-#define BCHP_SWITCH_INTRL2_1_PCI_MASK_SET_p5_gphy_intr_mask_DEFAULT 0x00000001
-
-/* SWITCH_INTRL2_1 :: PCI_MASK_SET :: p5_energy_off_intr_mask [08:08] */
-#define BCHP_SWITCH_INTRL2_1_PCI_MASK_SET_p5_energy_off_intr_mask_MASK 0x00000100
-#define BCHP_SWITCH_INTRL2_1_PCI_MASK_SET_p5_energy_off_intr_mask_SHIFT 8
-#define BCHP_SWITCH_INTRL2_1_PCI_MASK_SET_p5_energy_off_intr_mask_DEFAULT 0x00000001
-
-/* SWITCH_INTRL2_1 :: PCI_MASK_SET :: p5_energy_on_intr_mask [07:07] */
-#define BCHP_SWITCH_INTRL2_1_PCI_MASK_SET_p5_energy_on_intr_mask_MASK 0x00000080
-#define BCHP_SWITCH_INTRL2_1_PCI_MASK_SET_p5_energy_on_intr_mask_SHIFT 7
-#define BCHP_SWITCH_INTRL2_1_PCI_MASK_SET_p5_energy_on_intr_mask_DEFAULT 0x00000001
-
-/* SWITCH_INTRL2_1 :: PCI_MASK_SET :: p5_link_down_intr_mask [06:06] */
-#define BCHP_SWITCH_INTRL2_1_PCI_MASK_SET_p5_link_down_intr_mask_MASK 0x00000040
-#define BCHP_SWITCH_INTRL2_1_PCI_MASK_SET_p5_link_down_intr_mask_SHIFT 6
-#define BCHP_SWITCH_INTRL2_1_PCI_MASK_SET_p5_link_down_intr_mask_DEFAULT 0x00000001
-
-/* SWITCH_INTRL2_1 :: PCI_MASK_SET :: p5_link_up_intr_mask [05:05] */
-#define BCHP_SWITCH_INTRL2_1_PCI_MASK_SET_p5_link_up_intr_mask_MASK 0x00000020
-#define BCHP_SWITCH_INTRL2_1_PCI_MASK_SET_p5_link_up_intr_mask_SHIFT 5
-#define BCHP_SWITCH_INTRL2_1_PCI_MASK_SET_p5_link_up_intr_mask_DEFAULT 0x00000001
-
-/* SWITCH_INTRL2_1 :: PCI_MASK_SET :: p7_gphy_intr_mask [04:04] */
-#define BCHP_SWITCH_INTRL2_1_PCI_MASK_SET_p7_gphy_intr_mask_MASK 0x00000010
-#define BCHP_SWITCH_INTRL2_1_PCI_MASK_SET_p7_gphy_intr_mask_SHIFT 4
-#define BCHP_SWITCH_INTRL2_1_PCI_MASK_SET_p7_gphy_intr_mask_DEFAULT 0x00000001
-
-/* SWITCH_INTRL2_1 :: PCI_MASK_SET :: p7_energy_off_intr_mask [03:03] */
-#define BCHP_SWITCH_INTRL2_1_PCI_MASK_SET_p7_energy_off_intr_mask_MASK 0x00000008
-#define BCHP_SWITCH_INTRL2_1_PCI_MASK_SET_p7_energy_off_intr_mask_SHIFT 3
-#define BCHP_SWITCH_INTRL2_1_PCI_MASK_SET_p7_energy_off_intr_mask_DEFAULT 0x00000001
-
-/* SWITCH_INTRL2_1 :: PCI_MASK_SET :: p7_energy_on_intr_mask [02:02] */
-#define BCHP_SWITCH_INTRL2_1_PCI_MASK_SET_p7_energy_on_intr_mask_MASK 0x00000004
-#define BCHP_SWITCH_INTRL2_1_PCI_MASK_SET_p7_energy_on_intr_mask_SHIFT 2
-#define BCHP_SWITCH_INTRL2_1_PCI_MASK_SET_p7_energy_on_intr_mask_DEFAULT 0x00000001
-
-/* SWITCH_INTRL2_1 :: PCI_MASK_SET :: p7_link_down_intr_mask [01:01] */
-#define BCHP_SWITCH_INTRL2_1_PCI_MASK_SET_p7_link_down_intr_mask_MASK 0x00000002
-#define BCHP_SWITCH_INTRL2_1_PCI_MASK_SET_p7_link_down_intr_mask_SHIFT 1
-#define BCHP_SWITCH_INTRL2_1_PCI_MASK_SET_p7_link_down_intr_mask_DEFAULT 0x00000001
-
-/* SWITCH_INTRL2_1 :: PCI_MASK_SET :: p7_link_up_intr_mask [00:00] */
-#define BCHP_SWITCH_INTRL2_1_PCI_MASK_SET_p7_link_up_intr_mask_MASK 0x00000001
-#define BCHP_SWITCH_INTRL2_1_PCI_MASK_SET_p7_link_up_intr_mask_SHIFT 0
-#define BCHP_SWITCH_INTRL2_1_PCI_MASK_SET_p7_link_up_intr_mask_DEFAULT 0x00000001
-
-/***************************************************************************
- *PCI_MASK_CLEAR - PCI interrupt Mask Clear Register
- ***************************************************************************/
-/* SWITCH_INTRL2_1 :: PCI_MASK_CLEAR :: reserved0 [31:30] */
-#define BCHP_SWITCH_INTRL2_1_PCI_MASK_CLEAR_reserved0_MASK 0xc0000000
-#define BCHP_SWITCH_INTRL2_1_PCI_MASK_CLEAR_reserved0_SHIFT 30
-
-/* SWITCH_INTRL2_1 :: PCI_MASK_CLEAR :: p1_gphy_intr_mask [29:29] */
-#define BCHP_SWITCH_INTRL2_1_PCI_MASK_CLEAR_p1_gphy_intr_mask_MASK 0x20000000
-#define BCHP_SWITCH_INTRL2_1_PCI_MASK_CLEAR_p1_gphy_intr_mask_SHIFT 29
-#define BCHP_SWITCH_INTRL2_1_PCI_MASK_CLEAR_p1_gphy_intr_mask_DEFAULT 0x00000001
-
-/* SWITCH_INTRL2_1 :: PCI_MASK_CLEAR :: p1_energy_off_intr_mask [28:28] */
-#define BCHP_SWITCH_INTRL2_1_PCI_MASK_CLEAR_p1_energy_off_intr_mask_MASK 0x10000000
-#define BCHP_SWITCH_INTRL2_1_PCI_MASK_CLEAR_p1_energy_off_intr_mask_SHIFT 28
-#define BCHP_SWITCH_INTRL2_1_PCI_MASK_CLEAR_p1_energy_off_intr_mask_DEFAULT 0x00000001
-
-/* SWITCH_INTRL2_1 :: PCI_MASK_CLEAR :: p1_energy_on_intr_mask [27:27] */
-#define BCHP_SWITCH_INTRL2_1_PCI_MASK_CLEAR_p1_energy_on_intr_mask_MASK 0x08000000
-#define BCHP_SWITCH_INTRL2_1_PCI_MASK_CLEAR_p1_energy_on_intr_mask_SHIFT 27
-#define BCHP_SWITCH_INTRL2_1_PCI_MASK_CLEAR_p1_energy_on_intr_mask_DEFAULT 0x00000001
-
-/* SWITCH_INTRL2_1 :: PCI_MASK_CLEAR :: p1_link_down_intr_mask [26:26] */
-#define BCHP_SWITCH_INTRL2_1_PCI_MASK_CLEAR_p1_link_down_intr_mask_MASK 0x04000000
-#define BCHP_SWITCH_INTRL2_1_PCI_MASK_CLEAR_p1_link_down_intr_mask_SHIFT 26
-#define BCHP_SWITCH_INTRL2_1_PCI_MASK_CLEAR_p1_link_down_intr_mask_DEFAULT 0x00000001
-
-/* SWITCH_INTRL2_1 :: PCI_MASK_CLEAR :: p1_link_up_intr_mask [25:25] */
-#define BCHP_SWITCH_INTRL2_1_PCI_MASK_CLEAR_p1_link_up_intr_mask_MASK 0x02000000
-#define BCHP_SWITCH_INTRL2_1_PCI_MASK_CLEAR_p1_link_up_intr_mask_SHIFT 25
-#define BCHP_SWITCH_INTRL2_1_PCI_MASK_CLEAR_p1_link_up_intr_mask_DEFAULT 0x00000001
-
-/* SWITCH_INTRL2_1 :: PCI_MASK_CLEAR :: p2_gphy_intr_mask [24:24] */
-#define BCHP_SWITCH_INTRL2_1_PCI_MASK_CLEAR_p2_gphy_intr_mask_MASK 0x01000000
-#define BCHP_SWITCH_INTRL2_1_PCI_MASK_CLEAR_p2_gphy_intr_mask_SHIFT 24
-#define BCHP_SWITCH_INTRL2_1_PCI_MASK_CLEAR_p2_gphy_intr_mask_DEFAULT 0x00000001
-
-/* SWITCH_INTRL2_1 :: PCI_MASK_CLEAR :: p2_energy_off_intr_mask [23:23] */
-#define BCHP_SWITCH_INTRL2_1_PCI_MASK_CLEAR_p2_energy_off_intr_mask_MASK 0x00800000
-#define BCHP_SWITCH_INTRL2_1_PCI_MASK_CLEAR_p2_energy_off_intr_mask_SHIFT 23
-#define BCHP_SWITCH_INTRL2_1_PCI_MASK_CLEAR_p2_energy_off_intr_mask_DEFAULT 0x00000001
-
-/* SWITCH_INTRL2_1 :: PCI_MASK_CLEAR :: p2_energy_on_intr_mask [22:22] */
-#define BCHP_SWITCH_INTRL2_1_PCI_MASK_CLEAR_p2_energy_on_intr_mask_MASK 0x00400000
-#define BCHP_SWITCH_INTRL2_1_PCI_MASK_CLEAR_p2_energy_on_intr_mask_SHIFT 22
-#define BCHP_SWITCH_INTRL2_1_PCI_MASK_CLEAR_p2_energy_on_intr_mask_DEFAULT 0x00000001
-
-/* SWITCH_INTRL2_1 :: PCI_MASK_CLEAR :: p2_link_down_intr_mask [21:21] */
-#define BCHP_SWITCH_INTRL2_1_PCI_MASK_CLEAR_p2_link_down_intr_mask_MASK 0x00200000
-#define BCHP_SWITCH_INTRL2_1_PCI_MASK_CLEAR_p2_link_down_intr_mask_SHIFT 21
-#define BCHP_SWITCH_INTRL2_1_PCI_MASK_CLEAR_p2_link_down_intr_mask_DEFAULT 0x00000001
-
-/* SWITCH_INTRL2_1 :: PCI_MASK_CLEAR :: p2_link_up_intr_mask [20:20] */
-#define BCHP_SWITCH_INTRL2_1_PCI_MASK_CLEAR_p2_link_up_intr_mask_MASK 0x00100000
-#define BCHP_SWITCH_INTRL2_1_PCI_MASK_CLEAR_p2_link_up_intr_mask_SHIFT 20
-#define BCHP_SWITCH_INTRL2_1_PCI_MASK_CLEAR_p2_link_up_intr_mask_DEFAULT 0x00000001
-
-/* SWITCH_INTRL2_1 :: PCI_MASK_CLEAR :: p3_gphy_intr_mask [19:19] */
-#define BCHP_SWITCH_INTRL2_1_PCI_MASK_CLEAR_p3_gphy_intr_mask_MASK 0x00080000
-#define BCHP_SWITCH_INTRL2_1_PCI_MASK_CLEAR_p3_gphy_intr_mask_SHIFT 19
-#define BCHP_SWITCH_INTRL2_1_PCI_MASK_CLEAR_p3_gphy_intr_mask_DEFAULT 0x00000001
-
-/* SWITCH_INTRL2_1 :: PCI_MASK_CLEAR :: p3_energy_off_intr_mask [18:18] */
-#define BCHP_SWITCH_INTRL2_1_PCI_MASK_CLEAR_p3_energy_off_intr_mask_MASK 0x00040000
-#define BCHP_SWITCH_INTRL2_1_PCI_MASK_CLEAR_p3_energy_off_intr_mask_SHIFT 18
-#define BCHP_SWITCH_INTRL2_1_PCI_MASK_CLEAR_p3_energy_off_intr_mask_DEFAULT 0x00000001
-
-/* SWITCH_INTRL2_1 :: PCI_MASK_CLEAR :: p3_energy_on_intr_mask [17:17] */
-#define BCHP_SWITCH_INTRL2_1_PCI_MASK_CLEAR_p3_energy_on_intr_mask_MASK 0x00020000
-#define BCHP_SWITCH_INTRL2_1_PCI_MASK_CLEAR_p3_energy_on_intr_mask_SHIFT 17
-#define BCHP_SWITCH_INTRL2_1_PCI_MASK_CLEAR_p3_energy_on_intr_mask_DEFAULT 0x00000001
-
-/* SWITCH_INTRL2_1 :: PCI_MASK_CLEAR :: p3_link_down_intr_mask [16:16] */
-#define BCHP_SWITCH_INTRL2_1_PCI_MASK_CLEAR_p3_link_down_intr_mask_MASK 0x00010000
-#define BCHP_SWITCH_INTRL2_1_PCI_MASK_CLEAR_p3_link_down_intr_mask_SHIFT 16
-#define BCHP_SWITCH_INTRL2_1_PCI_MASK_CLEAR_p3_link_down_intr_mask_DEFAULT 0x00000001
-
-/* SWITCH_INTRL2_1 :: PCI_MASK_CLEAR :: p3_link_up_intr_mask [15:15] */
-#define BCHP_SWITCH_INTRL2_1_PCI_MASK_CLEAR_p3_link_up_intr_mask_MASK 0x00008000
-#define BCHP_SWITCH_INTRL2_1_PCI_MASK_CLEAR_p3_link_up_intr_mask_SHIFT 15
-#define BCHP_SWITCH_INTRL2_1_PCI_MASK_CLEAR_p3_link_up_intr_mask_DEFAULT 0x00000001
-
-/* SWITCH_INTRL2_1 :: PCI_MASK_CLEAR :: p4_gphy_intr_mask [14:14] */
-#define BCHP_SWITCH_INTRL2_1_PCI_MASK_CLEAR_p4_gphy_intr_mask_MASK 0x00004000
-#define BCHP_SWITCH_INTRL2_1_PCI_MASK_CLEAR_p4_gphy_intr_mask_SHIFT 14
-#define BCHP_SWITCH_INTRL2_1_PCI_MASK_CLEAR_p4_gphy_intr_mask_DEFAULT 0x00000001
-
-/* SWITCH_INTRL2_1 :: PCI_MASK_CLEAR :: p4_energy_off_intr_mask [13:13] */
-#define BCHP_SWITCH_INTRL2_1_PCI_MASK_CLEAR_p4_energy_off_intr_mask_MASK 0x00002000
-#define BCHP_SWITCH_INTRL2_1_PCI_MASK_CLEAR_p4_energy_off_intr_mask_SHIFT 13
-#define BCHP_SWITCH_INTRL2_1_PCI_MASK_CLEAR_p4_energy_off_intr_mask_DEFAULT 0x00000001
-
-/* SWITCH_INTRL2_1 :: PCI_MASK_CLEAR :: p4_energy_on_intr_mask [12:12] */
-#define BCHP_SWITCH_INTRL2_1_PCI_MASK_CLEAR_p4_energy_on_intr_mask_MASK 0x00001000
-#define BCHP_SWITCH_INTRL2_1_PCI_MASK_CLEAR_p4_energy_on_intr_mask_SHIFT 12
-#define BCHP_SWITCH_INTRL2_1_PCI_MASK_CLEAR_p4_energy_on_intr_mask_DEFAULT 0x00000001
-
-/* SWITCH_INTRL2_1 :: PCI_MASK_CLEAR :: p4_link_down_intr_mask [11:11] */
-#define BCHP_SWITCH_INTRL2_1_PCI_MASK_CLEAR_p4_link_down_intr_mask_MASK 0x00000800
-#define BCHP_SWITCH_INTRL2_1_PCI_MASK_CLEAR_p4_link_down_intr_mask_SHIFT 11
-#define BCHP_SWITCH_INTRL2_1_PCI_MASK_CLEAR_p4_link_down_intr_mask_DEFAULT 0x00000001
-
-/* SWITCH_INTRL2_1 :: PCI_MASK_CLEAR :: p4_link_up_intr_mask [10:10] */
-#define BCHP_SWITCH_INTRL2_1_PCI_MASK_CLEAR_p4_link_up_intr_mask_MASK 0x00000400
-#define BCHP_SWITCH_INTRL2_1_PCI_MASK_CLEAR_p4_link_up_intr_mask_SHIFT 10
-#define BCHP_SWITCH_INTRL2_1_PCI_MASK_CLEAR_p4_link_up_intr_mask_DEFAULT 0x00000001
-
-/* SWITCH_INTRL2_1 :: PCI_MASK_CLEAR :: p5_gphy_intr_mask [09:09] */
-#define BCHP_SWITCH_INTRL2_1_PCI_MASK_CLEAR_p5_gphy_intr_mask_MASK 0x00000200
-#define BCHP_SWITCH_INTRL2_1_PCI_MASK_CLEAR_p5_gphy_intr_mask_SHIFT 9
-#define BCHP_SWITCH_INTRL2_1_PCI_MASK_CLEAR_p5_gphy_intr_mask_DEFAULT 0x00000001
-
-/* SWITCH_INTRL2_1 :: PCI_MASK_CLEAR :: p5_energy_off_intr_mask [08:08] */
-#define BCHP_SWITCH_INTRL2_1_PCI_MASK_CLEAR_p5_energy_off_intr_mask_MASK 0x00000100
-#define BCHP_SWITCH_INTRL2_1_PCI_MASK_CLEAR_p5_energy_off_intr_mask_SHIFT 8
-#define BCHP_SWITCH_INTRL2_1_PCI_MASK_CLEAR_p5_energy_off_intr_mask_DEFAULT 0x00000001
-
-/* SWITCH_INTRL2_1 :: PCI_MASK_CLEAR :: p5_energy_on_intr_mask [07:07] */
-#define BCHP_SWITCH_INTRL2_1_PCI_MASK_CLEAR_p5_energy_on_intr_mask_MASK 0x00000080
-#define BCHP_SWITCH_INTRL2_1_PCI_MASK_CLEAR_p5_energy_on_intr_mask_SHIFT 7
-#define BCHP_SWITCH_INTRL2_1_PCI_MASK_CLEAR_p5_energy_on_intr_mask_DEFAULT 0x00000001
-
-/* SWITCH_INTRL2_1 :: PCI_MASK_CLEAR :: p5_link_down_intr_mask [06:06] */
-#define BCHP_SWITCH_INTRL2_1_PCI_MASK_CLEAR_p5_link_down_intr_mask_MASK 0x00000040
-#define BCHP_SWITCH_INTRL2_1_PCI_MASK_CLEAR_p5_link_down_intr_mask_SHIFT 6
-#define BCHP_SWITCH_INTRL2_1_PCI_MASK_CLEAR_p5_link_down_intr_mask_DEFAULT 0x00000001
-
-/* SWITCH_INTRL2_1 :: PCI_MASK_CLEAR :: p5_link_up_intr_mask [05:05] */
-#define BCHP_SWITCH_INTRL2_1_PCI_MASK_CLEAR_p5_link_up_intr_mask_MASK 0x00000020
-#define BCHP_SWITCH_INTRL2_1_PCI_MASK_CLEAR_p5_link_up_intr_mask_SHIFT 5
-#define BCHP_SWITCH_INTRL2_1_PCI_MASK_CLEAR_p5_link_up_intr_mask_DEFAULT 0x00000001
-
-/* SWITCH_INTRL2_1 :: PCI_MASK_CLEAR :: p7_gphy_intr_mask [04:04] */
-#define BCHP_SWITCH_INTRL2_1_PCI_MASK_CLEAR_p7_gphy_intr_mask_MASK 0x00000010
-#define BCHP_SWITCH_INTRL2_1_PCI_MASK_CLEAR_p7_gphy_intr_mask_SHIFT 4
-#define BCHP_SWITCH_INTRL2_1_PCI_MASK_CLEAR_p7_gphy_intr_mask_DEFAULT 0x00000001
-
-/* SWITCH_INTRL2_1 :: PCI_MASK_CLEAR :: p7_energy_off_intr_mask [03:03] */
-#define BCHP_SWITCH_INTRL2_1_PCI_MASK_CLEAR_p7_energy_off_intr_mask_MASK 0x00000008
-#define BCHP_SWITCH_INTRL2_1_PCI_MASK_CLEAR_p7_energy_off_intr_mask_SHIFT 3
-#define BCHP_SWITCH_INTRL2_1_PCI_MASK_CLEAR_p7_energy_off_intr_mask_DEFAULT 0x00000001
-
-/* SWITCH_INTRL2_1 :: PCI_MASK_CLEAR :: p7_energy_on_intr_mask [02:02] */
-#define BCHP_SWITCH_INTRL2_1_PCI_MASK_CLEAR_p7_energy_on_intr_mask_MASK 0x00000004
-#define BCHP_SWITCH_INTRL2_1_PCI_MASK_CLEAR_p7_energy_on_intr_mask_SHIFT 2
-#define BCHP_SWITCH_INTRL2_1_PCI_MASK_CLEAR_p7_energy_on_intr_mask_DEFAULT 0x00000001
-
-/* SWITCH_INTRL2_1 :: PCI_MASK_CLEAR :: p7_link_down_intr_mask [01:01] */
-#define BCHP_SWITCH_INTRL2_1_PCI_MASK_CLEAR_p7_link_down_intr_mask_MASK 0x00000002
-#define BCHP_SWITCH_INTRL2_1_PCI_MASK_CLEAR_p7_link_down_intr_mask_SHIFT 1
-#define BCHP_SWITCH_INTRL2_1_PCI_MASK_CLEAR_p7_link_down_intr_mask_DEFAULT 0x00000001
-
-/* SWITCH_INTRL2_1 :: PCI_MASK_CLEAR :: p7_link_up_intr_mask [00:00] */
-#define BCHP_SWITCH_INTRL2_1_PCI_MASK_CLEAR_p7_link_up_intr_mask_MASK 0x00000001
-#define BCHP_SWITCH_INTRL2_1_PCI_MASK_CLEAR_p7_link_up_intr_mask_SHIFT 0
-#define BCHP_SWITCH_INTRL2_1_PCI_MASK_CLEAR_p7_link_up_intr_mask_DEFAULT 0x00000001
-
-#endif /* #ifndef BCHP_SWITCH_INTRL2_1_H__ */
-
-/* End of File */
diff --git a/include/linux/brcmstb/7145a0/bchp_switch_mdio.h b/include/linux/brcmstb/7145a0/bchp_switch_mdio.h
deleted file mode 100644
index 52e6be2..0000000
--- a/include/linux/brcmstb/7145a0/bchp_switch_mdio.h
+++ /dev/null
@@ -1,117 +0,0 @@
-/***************************************************************************
- * Copyright (c) 1999-2013, Broadcom Corporation
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
- *
- * Module Description:
- * DO NOT EDIT THIS FILE DIRECTLY
- *
- * This module was generated magically with RDB from a source description
- * file. You must edit the source file for changes to be made to this file.
- *
- *
- * Date: Generated on Wed May 8 03:09:24 2013
- * MD5 Checksum d41d8cd98f00b204e9800998ecf8427e
- *
- * Compiled with: RDB Utility combo_header.pl
- * RDB Parser 3.0
- * unknown unknown
- * Perl Interpreter 5.008008
- * Operating System linux
- *
- * Revision History:
- *
- * $brcm_Log: $
- *
- ***************************************************************************/
-
-#ifndef BCHP_SWITCH_MDIO_H__
-#define BCHP_SWITCH_MDIO_H__
-
-/***************************************************************************
- *SWITCH_MDIO
- ***************************************************************************/
-#define BCHP_SWITCH_MDIO_MDIO_CMD 0x04e403c0 /* MDIO Command Register */
-#define BCHP_SWITCH_MDIO_MDIO_CFG 0x04e403c4 /* MDIO Configuration Register */
-
-/***************************************************************************
- *MDIO_CMD - MDIO Command Register
- ***************************************************************************/
-/* SWITCH_MDIO :: MDIO_CMD :: reserved0 [31:30] */
-#define BCHP_SWITCH_MDIO_MDIO_CMD_reserved0_MASK 0xc0000000
-#define BCHP_SWITCH_MDIO_MDIO_CMD_reserved0_SHIFT 30
-
-/* SWITCH_MDIO :: MDIO_CMD :: mdio_busy [29:29] */
-#define BCHP_SWITCH_MDIO_MDIO_CMD_mdio_busy_MASK 0x20000000
-#define BCHP_SWITCH_MDIO_MDIO_CMD_mdio_busy_SHIFT 29
-#define BCHP_SWITCH_MDIO_MDIO_CMD_mdio_busy_DEFAULT 0x00000000
-
-/* SWITCH_MDIO :: MDIO_CMD :: fail [28:28] */
-#define BCHP_SWITCH_MDIO_MDIO_CMD_fail_MASK 0x10000000
-#define BCHP_SWITCH_MDIO_MDIO_CMD_fail_SHIFT 28
-#define BCHP_SWITCH_MDIO_MDIO_CMD_fail_DEFAULT 0x00000000
-
-/* SWITCH_MDIO :: MDIO_CMD :: op_code [27:26] */
-#define BCHP_SWITCH_MDIO_MDIO_CMD_op_code_MASK 0x0c000000
-#define BCHP_SWITCH_MDIO_MDIO_CMD_op_code_SHIFT 26
-#define BCHP_SWITCH_MDIO_MDIO_CMD_op_code_DEFAULT 0x00000000
-
-/* SWITCH_MDIO :: MDIO_CMD :: phy_prt_addr [25:21] */
-#define BCHP_SWITCH_MDIO_MDIO_CMD_phy_prt_addr_MASK 0x03e00000
-#define BCHP_SWITCH_MDIO_MDIO_CMD_phy_prt_addr_SHIFT 21
-#define BCHP_SWITCH_MDIO_MDIO_CMD_phy_prt_addr_DEFAULT 0x00000000
-
-/* SWITCH_MDIO :: MDIO_CMD :: reg_dec_addr [20:16] */
-#define BCHP_SWITCH_MDIO_MDIO_CMD_reg_dec_addr_MASK 0x001f0000
-#define BCHP_SWITCH_MDIO_MDIO_CMD_reg_dec_addr_SHIFT 16
-#define BCHP_SWITCH_MDIO_MDIO_CMD_reg_dec_addr_DEFAULT 0x00000000
-
-/* SWITCH_MDIO :: MDIO_CMD :: data_addr [15:00] */
-#define BCHP_SWITCH_MDIO_MDIO_CMD_data_addr_MASK 0x0000ffff
-#define BCHP_SWITCH_MDIO_MDIO_CMD_data_addr_SHIFT 0
-#define BCHP_SWITCH_MDIO_MDIO_CMD_data_addr_DEFAULT 0x00000000
-
-/***************************************************************************
- *MDIO_CFG - MDIO Configuration Register
- ***************************************************************************/
-/* SWITCH_MDIO :: MDIO_CFG :: reserved0 [31:13] */
-#define BCHP_SWITCH_MDIO_MDIO_CFG_reserved0_MASK 0xffffe000
-#define BCHP_SWITCH_MDIO_MDIO_CFG_reserved0_SHIFT 13
-
-/* SWITCH_MDIO :: MDIO_CFG :: supress_preamble [12:12] */
-#define BCHP_SWITCH_MDIO_MDIO_CFG_supress_preamble_MASK 0x00001000
-#define BCHP_SWITCH_MDIO_MDIO_CFG_supress_preamble_SHIFT 12
-#define BCHP_SWITCH_MDIO_MDIO_CFG_supress_preamble_DEFAULT 0x00000000
-
-/* SWITCH_MDIO :: MDIO_CFG :: reserved1 [11:10] */
-#define BCHP_SWITCH_MDIO_MDIO_CFG_reserved1_MASK 0x00000c00
-#define BCHP_SWITCH_MDIO_MDIO_CFG_reserved1_SHIFT 10
-
-/* SWITCH_MDIO :: MDIO_CFG :: mdio_clk_divider [09:04] */
-#define BCHP_SWITCH_MDIO_MDIO_CFG_mdio_clk_divider_MASK 0x000003f0
-#define BCHP_SWITCH_MDIO_MDIO_CFG_mdio_clk_divider_SHIFT 4
-#define BCHP_SWITCH_MDIO_MDIO_CFG_mdio_clk_divider_DEFAULT 0x00000009
-
-/* SWITCH_MDIO :: MDIO_CFG :: reserved2 [03:01] */
-#define BCHP_SWITCH_MDIO_MDIO_CFG_reserved2_MASK 0x0000000e
-#define BCHP_SWITCH_MDIO_MDIO_CFG_reserved2_SHIFT 1
-
-/* SWITCH_MDIO :: MDIO_CFG :: mdio_clause [00:00] */
-#define BCHP_SWITCH_MDIO_MDIO_CFG_mdio_clause_MASK 0x00000001
-#define BCHP_SWITCH_MDIO_MDIO_CFG_mdio_clause_SHIFT 0
-#define BCHP_SWITCH_MDIO_MDIO_CFG_mdio_clause_DEFAULT 0x00000001
-
-#endif /* #ifndef BCHP_SWITCH_MDIO_H__ */
-
-/* End of File */
diff --git a/include/linux/brcmstb/7145a0/bchp_switch_reg.h b/include/linux/brcmstb/7145a0/bchp_switch_reg.h
deleted file mode 100644
index 69fc3f4..0000000
--- a/include/linux/brcmstb/7145a0/bchp_switch_reg.h
+++ /dev/null
@@ -1,837 +0,0 @@
-/***************************************************************************
- * Copyright (c) 1999-2013, Broadcom Corporation
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
- *
- * Module Description:
- * DO NOT EDIT THIS FILE DIRECTLY
- *
- * This module was generated magically with RDB from a source description
- * file. You must edit the source file for changes to be made to this file.
- *
- *
- * Date: Generated on Wed May 8 03:09:20 2013
- * MD5 Checksum d41d8cd98f00b204e9800998ecf8427e
- *
- * Compiled with: RDB Utility combo_header.pl
- * RDB Parser 3.0
- * unknown unknown
- * Perl Interpreter 5.008008
- * Operating System linux
- *
- * Revision History:
- *
- * $brcm_Log: $
- *
- ***************************************************************************/
-
-#ifndef BCHP_SWITCH_REG_H__
-#define BCHP_SWITCH_REG_H__
-
-/***************************************************************************
- *SWITCH_REG
- ***************************************************************************/
-#define BCHP_SWITCH_REG_SWITCH_CNTRL 0x04e40000 /* Switch Control Register */
-#define BCHP_SWITCH_REG_SWITCH_STATUS 0x04e40004 /* Switch Status Register */
-#define BCHP_SWITCH_REG_DIR_DATA_WRITE_REG 0x04e40008 /* Direct Data Write Register */
-#define BCHP_SWITCH_REG_DIR_DATA_READ_REG 0x04e4000c /* Direct Data Read Register */
-#define BCHP_SWITCH_REG_LED_SERIAL_REFRESH_TIME_UNIT 0x04e40010 /* LED Serial Refresh Time Unit Register */
-#define BCHP_SWITCH_REG_SWITCH_REVISION 0x04e40018 /* SWITCH Revision Control Register */
-#define BCHP_SWITCH_REG_PHY_REVISION 0x04e4001c /* PHY Revision Control Register */
-#define BCHP_SWITCH_REG_PHY_TEST_CNTRL 0x04e40020 /* PHY Test Control Register */
-#define BCHP_SWITCH_REG_QPHY_CNTRL 0x04e40024 /* Quad GPHY Control Register */
-#define BCHP_SWITCH_REG_QPHY_STATUS 0x04e40028 /* Quad GPHY Status Register */
-#define BCHP_SWITCH_REG_LED_BLINK_RATE_CNTRL 0x04e40088 /* LED port Blink Rate Control Register */
-#define BCHP_SWITCH_REG_LED_SERIAL_CNTRL 0x04e4008c /* LED Serial Control Register */
-#define BCHP_SWITCH_REG_LED_0_CNTRL 0x04e40090 /* LED port 0 Control Register */
-#define BCHP_SWITCH_REG_LED_1_CNTRL 0x04e40094 /* LED port 1 Control Register */
-#define BCHP_SWITCH_REG_LED_2_CNTRL 0x04e40098 /* LED port 2 Control Register */
-#define BCHP_SWITCH_REG_LED_3_CNTRL 0x04e4009c /* LED port 3 Control Register */
-#define BCHP_SWITCH_REG_LED_7_CNTRL 0x04e400a8 /* LED port 7 Control Register */
-#define BCHP_SWITCH_REG_RGMII_9_CNTRL 0x04e400b0 /* RGMII port 9 Control Register */
-#define BCHP_SWITCH_REG_RGMII_9_IB_STATUS 0x04e400b4 /* RGMII port 9 InBand Status Register */
-#define BCHP_SWITCH_REG_RGMII_9_RX_CLOCK_DELAY_CNTRL 0x04e400b8 /* RGMII port 9 RX Clock Delay Control Register */
-
-/***************************************************************************
- *SWITCH_CNTRL - Switch Control Register
- ***************************************************************************/
-/* SWITCH_REG :: SWITCH_CNTRL :: reserved0 [31:01] */
-#define BCHP_SWITCH_REG_SWITCH_CNTRL_reserved0_MASK 0xfffffffe
-#define BCHP_SWITCH_REG_SWITCH_CNTRL_reserved0_SHIFT 1
-
-/* SWITCH_REG :: SWITCH_CNTRL :: mdio_master_sel [00:00] */
-#define BCHP_SWITCH_REG_SWITCH_CNTRL_mdio_master_sel_MASK 0x00000001
-#define BCHP_SWITCH_REG_SWITCH_CNTRL_mdio_master_sel_SHIFT 0
-#define BCHP_SWITCH_REG_SWITCH_CNTRL_mdio_master_sel_DEFAULT 0x00000000
-
-/***************************************************************************
- *SWITCH_STATUS - Switch Status Register
- ***************************************************************************/
-/* SWITCH_REG :: SWITCH_STATUS :: reserved0 [31:01] */
-#define BCHP_SWITCH_REG_SWITCH_STATUS_reserved0_MASK 0xfffffffe
-#define BCHP_SWITCH_REG_SWITCH_STATUS_reserved0_SHIFT 1
-
-/* SWITCH_REG :: SWITCH_STATUS :: sw_init_done [00:00] */
-#define BCHP_SWITCH_REG_SWITCH_STATUS_sw_init_done_MASK 0x00000001
-#define BCHP_SWITCH_REG_SWITCH_STATUS_sw_init_done_SHIFT 0
-#define BCHP_SWITCH_REG_SWITCH_STATUS_sw_init_done_DEFAULT 0x00000000
-
-/***************************************************************************
- *DIR_DATA_WRITE_REG - Direct Data Write Register
- ***************************************************************************/
-/* SWITCH_REG :: DIR_DATA_WRITE_REG :: write_data [31:00] */
-#define BCHP_SWITCH_REG_DIR_DATA_WRITE_REG_write_data_MASK 0xffffffff
-#define BCHP_SWITCH_REG_DIR_DATA_WRITE_REG_write_data_SHIFT 0
-#define BCHP_SWITCH_REG_DIR_DATA_WRITE_REG_write_data_DEFAULT 0x00000000
-
-/***************************************************************************
- *DIR_DATA_READ_REG - Direct Data Read Register
- ***************************************************************************/
-/* SWITCH_REG :: DIR_DATA_READ_REG :: read_data [31:00] */
-#define BCHP_SWITCH_REG_DIR_DATA_READ_REG_read_data_MASK 0xffffffff
-#define BCHP_SWITCH_REG_DIR_DATA_READ_REG_read_data_SHIFT 0
-#define BCHP_SWITCH_REG_DIR_DATA_READ_REG_read_data_DEFAULT 0x00000000
-
-/***************************************************************************
- *LED_SERIAL_REFRESH_TIME_UNIT - LED Serial Refresh Time Unit Register
- ***************************************************************************/
-/* SWITCH_REG :: LED_SERIAL_REFRESH_TIME_UNIT :: reserved0 [31:24] */
-#define BCHP_SWITCH_REG_LED_SERIAL_REFRESH_TIME_UNIT_reserved0_MASK 0xff000000
-#define BCHP_SWITCH_REG_LED_SERIAL_REFRESH_TIME_UNIT_reserved0_SHIFT 24
-
-/* SWITCH_REG :: LED_SERIAL_REFRESH_TIME_UNIT :: refresh_time_unit [23:00] */
-#define BCHP_SWITCH_REG_LED_SERIAL_REFRESH_TIME_UNIT_refresh_time_unit_MASK 0x00ffffff
-#define BCHP_SWITCH_REG_LED_SERIAL_REFRESH_TIME_UNIT_refresh_time_unit_SHIFT 0
-#define BCHP_SWITCH_REG_LED_SERIAL_REFRESH_TIME_UNIT_refresh_time_unit_DEFAULT 0x0001e847
-
-/***************************************************************************
- *SWITCH_REVISION - SWITCH Revision Control Register
- ***************************************************************************/
-/* SWITCH_REG :: SWITCH_REVISION :: SF2_rev [31:16] */
-#define BCHP_SWITCH_REG_SWITCH_REVISION_SF2_rev_MASK 0xffff0000
-#define BCHP_SWITCH_REG_SWITCH_REVISION_SF2_rev_SHIFT 16
-#define BCHP_SWITCH_REG_SWITCH_REVISION_SF2_rev_DEFAULT 0x00000000
-
-/* SWITCH_REG :: SWITCH_REVISION :: switch_top_rev [15:00] */
-#define BCHP_SWITCH_REG_SWITCH_REVISION_switch_top_rev_MASK 0x0000ffff
-#define BCHP_SWITCH_REG_SWITCH_REVISION_switch_top_rev_SHIFT 0
-#define BCHP_SWITCH_REG_SWITCH_REVISION_switch_top_rev_DEFAULT 0x00000000
-
-/***************************************************************************
- *PHY_REVISION - PHY Revision Control Register
- ***************************************************************************/
-/* SWITCH_REG :: PHY_REVISION :: quad_phy_rev [31:16] */
-#define BCHP_SWITCH_REG_PHY_REVISION_quad_phy_rev_MASK 0xffff0000
-#define BCHP_SWITCH_REG_PHY_REVISION_quad_phy_rev_SHIFT 16
-#define BCHP_SWITCH_REG_PHY_REVISION_quad_phy_rev_DEFAULT 0x00000000
-
-/* SWITCH_REG :: PHY_REVISION :: single_phy_rev [15:00] */
-#define BCHP_SWITCH_REG_PHY_REVISION_single_phy_rev_MASK 0x0000ffff
-#define BCHP_SWITCH_REG_PHY_REVISION_single_phy_rev_SHIFT 0
-#define BCHP_SWITCH_REG_PHY_REVISION_single_phy_rev_DEFAULT 0x00000000
-
-/***************************************************************************
- *PHY_TEST_CNTRL - PHY Test Control Register
- ***************************************************************************/
-/* SWITCH_REG :: PHY_TEST_CNTRL :: reserved0 [31:06] */
-#define BCHP_SWITCH_REG_PHY_TEST_CNTRL_reserved0_MASK 0xffffffc0
-#define BCHP_SWITCH_REG_PHY_TEST_CNTRL_reserved0_SHIFT 6
-
-/* SWITCH_REG :: PHY_TEST_CNTRL :: phy_sel [05:03] */
-#define BCHP_SWITCH_REG_PHY_TEST_CNTRL_phy_sel_MASK 0x00000038
-#define BCHP_SWITCH_REG_PHY_TEST_CNTRL_phy_sel_SHIFT 3
-#define BCHP_SWITCH_REG_PHY_TEST_CNTRL_phy_sel_DEFAULT 0x00000000
-
-/* SWITCH_REG :: PHY_TEST_CNTRL :: phy_test_mode [02:01] */
-#define BCHP_SWITCH_REG_PHY_TEST_CNTRL_phy_test_mode_MASK 0x00000006
-#define BCHP_SWITCH_REG_PHY_TEST_CNTRL_phy_test_mode_SHIFT 1
-#define BCHP_SWITCH_REG_PHY_TEST_CNTRL_phy_test_mode_DEFAULT 0x00000000
-
-/* SWITCH_REG :: PHY_TEST_CNTRL :: phy_test_en [00:00] */
-#define BCHP_SWITCH_REG_PHY_TEST_CNTRL_phy_test_en_MASK 0x00000001
-#define BCHP_SWITCH_REG_PHY_TEST_CNTRL_phy_test_en_SHIFT 0
-#define BCHP_SWITCH_REG_PHY_TEST_CNTRL_phy_test_en_DEFAULT 0x00000000
-
-/***************************************************************************
- *QPHY_CNTRL - Quad GPHY Control Register
- ***************************************************************************/
-/* SWITCH_REG :: QPHY_CNTRL :: reserved0 [31:17] */
-#define BCHP_SWITCH_REG_QPHY_CNTRL_reserved0_MASK 0xfffe0000
-#define BCHP_SWITCH_REG_QPHY_CNTRL_reserved0_SHIFT 17
-
-/* SWITCH_REG :: QPHY_CNTRL :: phy_phyad [16:12] */
-#define BCHP_SWITCH_REG_QPHY_CNTRL_phy_phyad_MASK 0x0001f000
-#define BCHP_SWITCH_REG_QPHY_CNTRL_phy_phyad_SHIFT 12
-#define BCHP_SWITCH_REG_QPHY_CNTRL_phy_phyad_DEFAULT 0x00000001
-
-/* SWITCH_REG :: QPHY_CNTRL :: reserved1 [11:09] */
-#define BCHP_SWITCH_REG_QPHY_CNTRL_reserved1_MASK 0x00000e00
-#define BCHP_SWITCH_REG_QPHY_CNTRL_reserved1_SHIFT 9
-
-/* SWITCH_REG :: QPHY_CNTRL :: phy_reset [08:08] */
-#define BCHP_SWITCH_REG_QPHY_CNTRL_phy_reset_MASK 0x00000100
-#define BCHP_SWITCH_REG_QPHY_CNTRL_phy_reset_SHIFT 8
-#define BCHP_SWITCH_REG_QPHY_CNTRL_phy_reset_DEFAULT 0x00000000
-
-/* SWITCH_REG :: QPHY_CNTRL :: ck25_dis [07:07] */
-#define BCHP_SWITCH_REG_QPHY_CNTRL_ck25_dis_MASK 0x00000080
-#define BCHP_SWITCH_REG_QPHY_CNTRL_ck25_dis_SHIFT 7
-#define BCHP_SWITCH_REG_QPHY_CNTRL_ck25_dis_DEFAULT 0x00000000
-
-/* SWITCH_REG :: QPHY_CNTRL :: iddq_global_pwr [06:06] */
-#define BCHP_SWITCH_REG_QPHY_CNTRL_iddq_global_pwr_MASK 0x00000040
-#define BCHP_SWITCH_REG_QPHY_CNTRL_iddq_global_pwr_SHIFT 6
-#define BCHP_SWITCH_REG_QPHY_CNTRL_iddq_global_pwr_DEFAULT 0x00000000
-
-/* SWITCH_REG :: QPHY_CNTRL :: force_dll_en [05:05] */
-#define BCHP_SWITCH_REG_QPHY_CNTRL_force_dll_en_MASK 0x00000020
-#define BCHP_SWITCH_REG_QPHY_CNTRL_force_dll_en_SHIFT 5
-#define BCHP_SWITCH_REG_QPHY_CNTRL_force_dll_en_DEFAULT 0x00000000
-
-/* SWITCH_REG :: QPHY_CNTRL :: ext_pwr_down [04:01] */
-#define BCHP_SWITCH_REG_QPHY_CNTRL_ext_pwr_down_MASK 0x0000001e
-#define BCHP_SWITCH_REG_QPHY_CNTRL_ext_pwr_down_SHIFT 1
-#define BCHP_SWITCH_REG_QPHY_CNTRL_ext_pwr_down_DEFAULT 0x0000000f
-
-/* SWITCH_REG :: QPHY_CNTRL :: iddq_bias [00:00] */
-#define BCHP_SWITCH_REG_QPHY_CNTRL_iddq_bias_MASK 0x00000001
-#define BCHP_SWITCH_REG_QPHY_CNTRL_iddq_bias_SHIFT 0
-#define BCHP_SWITCH_REG_QPHY_CNTRL_iddq_bias_DEFAULT 0x00000001
-
-/***************************************************************************
- *QPHY_STATUS - Quad GPHY Status Register
- ***************************************************************************/
-/* SWITCH_REG :: QPHY_STATUS :: reserved0 [31:09] */
-#define BCHP_SWITCH_REG_QPHY_STATUS_reserved0_MASK 0xfffffe00
-#define BCHP_SWITCH_REG_QPHY_STATUS_reserved0_SHIFT 9
-
-/* SWITCH_REG :: QPHY_STATUS :: pll_lock [08:08] */
-#define BCHP_SWITCH_REG_QPHY_STATUS_pll_lock_MASK 0x00000100
-#define BCHP_SWITCH_REG_QPHY_STATUS_pll_lock_SHIFT 8
-#define BCHP_SWITCH_REG_QPHY_STATUS_pll_lock_DEFAULT 0x00000000
-
-/* SWITCH_REG :: QPHY_STATUS :: energy_det_apd [07:04] */
-#define BCHP_SWITCH_REG_QPHY_STATUS_energy_det_apd_MASK 0x000000f0
-#define BCHP_SWITCH_REG_QPHY_STATUS_energy_det_apd_SHIFT 4
-#define BCHP_SWITCH_REG_QPHY_STATUS_energy_det_apd_DEFAULT 0x00000000
-
-/* SWITCH_REG :: QPHY_STATUS :: energy_det_masked [03:00] */
-#define BCHP_SWITCH_REG_QPHY_STATUS_energy_det_masked_MASK 0x0000000f
-#define BCHP_SWITCH_REG_QPHY_STATUS_energy_det_masked_SHIFT 0
-#define BCHP_SWITCH_REG_QPHY_STATUS_energy_det_masked_DEFAULT 0x00000000
-
-/***************************************************************************
- *LED_BLINK_RATE_CNTRL - LED port Blink Rate Control Register
- ***************************************************************************/
-/* SWITCH_REG :: LED_BLINK_RATE_CNTRL :: led_on_time [31:16] */
-#define BCHP_SWITCH_REG_LED_BLINK_RATE_CNTRL_led_on_time_MASK 0xffff0000
-#define BCHP_SWITCH_REG_LED_BLINK_RATE_CNTRL_led_on_time_SHIFT 16
-#define BCHP_SWITCH_REG_LED_BLINK_RATE_CNTRL_led_on_time_DEFAULT 0x00000320
-
-/* SWITCH_REG :: LED_BLINK_RATE_CNTRL :: led_off_time [15:00] */
-#define BCHP_SWITCH_REG_LED_BLINK_RATE_CNTRL_led_off_time_MASK 0x0000ffff
-#define BCHP_SWITCH_REG_LED_BLINK_RATE_CNTRL_led_off_time_SHIFT 0
-#define BCHP_SWITCH_REG_LED_BLINK_RATE_CNTRL_led_off_time_DEFAULT 0x00000320
-
-/***************************************************************************
- *LED_SERIAL_CNTRL - LED Serial Control Register
- ***************************************************************************/
-/* SWITCH_REG :: LED_SERIAL_CNTRL :: reserved0 [31:16] */
-#define BCHP_SWITCH_REG_LED_SERIAL_CNTRL_reserved0_MASK 0xffff0000
-#define BCHP_SWITCH_REG_LED_SERIAL_CNTRL_reserved0_SHIFT 16
-
-/* SWITCH_REG :: LED_SERIAL_CNTRL :: port_en [15:08] */
-#define BCHP_SWITCH_REG_LED_SERIAL_CNTRL_port_en_MASK 0x0000ff00
-#define BCHP_SWITCH_REG_LED_SERIAL_CNTRL_port_en_SHIFT 8
-#define BCHP_SWITCH_REG_LED_SERIAL_CNTRL_port_en_DEFAULT 0x00000000
-
-/* SWITCH_REG :: LED_SERIAL_CNTRL :: smode [07:07] */
-#define BCHP_SWITCH_REG_LED_SERIAL_CNTRL_smode_MASK 0x00000080
-#define BCHP_SWITCH_REG_LED_SERIAL_CNTRL_smode_SHIFT 7
-#define BCHP_SWITCH_REG_LED_SERIAL_CNTRL_smode_DEFAULT 0x00000000
-
-/* SWITCH_REG :: LED_SERIAL_CNTRL :: sled_clk_frequency [06:06] */
-#define BCHP_SWITCH_REG_LED_SERIAL_CNTRL_sled_clk_frequency_MASK 0x00000040
-#define BCHP_SWITCH_REG_LED_SERIAL_CNTRL_sled_clk_frequency_SHIFT 6
-#define BCHP_SWITCH_REG_LED_SERIAL_CNTRL_sled_clk_frequency_DEFAULT 0x00000000
-
-/* SWITCH_REG :: LED_SERIAL_CNTRL :: sled_clk_pol [05:05] */
-#define BCHP_SWITCH_REG_LED_SERIAL_CNTRL_sled_clk_pol_MASK 0x00000020
-#define BCHP_SWITCH_REG_LED_SERIAL_CNTRL_sled_clk_pol_SHIFT 5
-#define BCHP_SWITCH_REG_LED_SERIAL_CNTRL_sled_clk_pol_DEFAULT 0x00000000
-
-/* SWITCH_REG :: LED_SERIAL_CNTRL :: refresh_period [04:00] */
-#define BCHP_SWITCH_REG_LED_SERIAL_CNTRL_refresh_period_MASK 0x0000001f
-#define BCHP_SWITCH_REG_LED_SERIAL_CNTRL_refresh_period_SHIFT 0
-#define BCHP_SWITCH_REG_LED_SERIAL_CNTRL_refresh_period_DEFAULT 0x00000004
-
-/***************************************************************************
- *LED_0_CNTRL - LED port 0 Control Register
- ***************************************************************************/
-/* SWITCH_REG :: LED_0_CNTRL :: reserved0 [31:28] */
-#define BCHP_SWITCH_REG_LED_0_CNTRL_reserved0_MASK 0xf0000000
-#define BCHP_SWITCH_REG_LED_0_CNTRL_reserved0_SHIFT 28
-
-/* SWITCH_REG :: LED_0_CNTRL :: act_led_pol_sel [27:27] */
-#define BCHP_SWITCH_REG_LED_0_CNTRL_act_led_pol_sel_MASK 0x08000000
-#define BCHP_SWITCH_REG_LED_0_CNTRL_act_led_pol_sel_SHIFT 27
-#define BCHP_SWITCH_REG_LED_0_CNTRL_act_led_pol_sel_DEFAULT 0x00000000
-
-/* SWITCH_REG :: LED_0_CNTRL :: spdlnk_led1_act_pol_sel [26:26] */
-#define BCHP_SWITCH_REG_LED_0_CNTRL_spdlnk_led1_act_pol_sel_MASK 0x04000000
-#define BCHP_SWITCH_REG_LED_0_CNTRL_spdlnk_led1_act_pol_sel_SHIFT 26
-#define BCHP_SWITCH_REG_LED_0_CNTRL_spdlnk_led1_act_pol_sel_DEFAULT 0x00000000
-
-/* SWITCH_REG :: LED_0_CNTRL :: spdlnk_led0_act_pol_sel [25:25] */
-#define BCHP_SWITCH_REG_LED_0_CNTRL_spdlnk_led0_act_pol_sel_MASK 0x02000000
-#define BCHP_SWITCH_REG_LED_0_CNTRL_spdlnk_led0_act_pol_sel_SHIFT 25
-#define BCHP_SWITCH_REG_LED_0_CNTRL_spdlnk_led0_act_pol_sel_DEFAULT 0x00000000
-
-/* SWITCH_REG :: LED_0_CNTRL :: spdlnk_src_sel [24:24] */
-#define BCHP_SWITCH_REG_LED_0_CNTRL_spdlnk_src_sel_MASK 0x01000000
-#define BCHP_SWITCH_REG_LED_0_CNTRL_spdlnk_src_sel_SHIFT 24
-#define BCHP_SWITCH_REG_LED_0_CNTRL_spdlnk_src_sel_DEFAULT 0x00000000
-
-/* SWITCH_REG :: LED_0_CNTRL :: act_led_act_sel [23:22] */
-#define BCHP_SWITCH_REG_LED_0_CNTRL_act_led_act_sel_MASK 0x00c00000
-#define BCHP_SWITCH_REG_LED_0_CNTRL_act_led_act_sel_SHIFT 22
-#define BCHP_SWITCH_REG_LED_0_CNTRL_act_led_act_sel_DEFAULT 0x00000000
-
-/* SWITCH_REG :: LED_0_CNTRL :: spdlnk_led1_act_sel [21:20] */
-#define BCHP_SWITCH_REG_LED_0_CNTRL_spdlnk_led1_act_sel_MASK 0x00300000
-#define BCHP_SWITCH_REG_LED_0_CNTRL_spdlnk_led1_act_sel_SHIFT 20
-#define BCHP_SWITCH_REG_LED_0_CNTRL_spdlnk_led1_act_sel_DEFAULT 0x00000000
-
-/* SWITCH_REG :: LED_0_CNTRL :: spdlnk_led0_act_sel [19:18] */
-#define BCHP_SWITCH_REG_LED_0_CNTRL_spdlnk_led0_act_sel_MASK 0x000c0000
-#define BCHP_SWITCH_REG_LED_0_CNTRL_spdlnk_led0_act_sel_SHIFT 18
-#define BCHP_SWITCH_REG_LED_0_CNTRL_spdlnk_led0_act_sel_DEFAULT 0x00000000
-
-/* SWITCH_REG :: LED_0_CNTRL :: tx_en_en [17:17] */
-#define BCHP_SWITCH_REG_LED_0_CNTRL_tx_en_en_MASK 0x00020000
-#define BCHP_SWITCH_REG_LED_0_CNTRL_tx_en_en_SHIFT 17
-#define BCHP_SWITCH_REG_LED_0_CNTRL_tx_en_en_DEFAULT 0x00000001
-
-/* SWITCH_REG :: LED_0_CNTRL :: rx_dv_en [16:16] */
-#define BCHP_SWITCH_REG_LED_0_CNTRL_rx_dv_en_MASK 0x00010000
-#define BCHP_SWITCH_REG_LED_0_CNTRL_rx_dv_en_SHIFT 16
-#define BCHP_SWITCH_REG_LED_0_CNTRL_rx_dv_en_DEFAULT 0x00000001
-
-/* SWITCH_REG :: LED_0_CNTRL :: sel_1000m_encode [15:14] */
-#define BCHP_SWITCH_REG_LED_0_CNTRL_sel_1000m_encode_MASK 0x0000c000
-#define BCHP_SWITCH_REG_LED_0_CNTRL_sel_1000m_encode_SHIFT 14
-#define BCHP_SWITCH_REG_LED_0_CNTRL_sel_1000m_encode_DEFAULT 0x00000000
-
-/* SWITCH_REG :: LED_0_CNTRL :: sel_100m_encode [13:12] */
-#define BCHP_SWITCH_REG_LED_0_CNTRL_sel_100m_encode_MASK 0x00003000
-#define BCHP_SWITCH_REG_LED_0_CNTRL_sel_100m_encode_SHIFT 12
-#define BCHP_SWITCH_REG_LED_0_CNTRL_sel_100m_encode_DEFAULT 0x00000000
-
-/* SWITCH_REG :: LED_0_CNTRL :: sel_10m_encode [11:10] */
-#define BCHP_SWITCH_REG_LED_0_CNTRL_sel_10m_encode_MASK 0x00000c00
-#define BCHP_SWITCH_REG_LED_0_CNTRL_sel_10m_encode_SHIFT 10
-#define BCHP_SWITCH_REG_LED_0_CNTRL_sel_10m_encode_DEFAULT 0x00000000
-
-/* SWITCH_REG :: LED_0_CNTRL :: sel_no_link_encode [09:08] */
-#define BCHP_SWITCH_REG_LED_0_CNTRL_sel_no_link_encode_MASK 0x00000300
-#define BCHP_SWITCH_REG_LED_0_CNTRL_sel_no_link_encode_SHIFT 8
-#define BCHP_SWITCH_REG_LED_0_CNTRL_sel_no_link_encode_DEFAULT 0x00000000
-
-/* SWITCH_REG :: LED_0_CNTRL :: 1000m_encode [07:06] */
-#define BCHP_SWITCH_REG_LED_0_CNTRL_1000m_encode_MASK 0x000000c0
-#define BCHP_SWITCH_REG_LED_0_CNTRL_1000m_encode_SHIFT 6
-#define BCHP_SWITCH_REG_LED_0_CNTRL_1000m_encode_DEFAULT 0x00000000
-
-/* SWITCH_REG :: LED_0_CNTRL :: 100m_encode [05:04] */
-#define BCHP_SWITCH_REG_LED_0_CNTRL_100m_encode_MASK 0x00000030
-#define BCHP_SWITCH_REG_LED_0_CNTRL_100m_encode_SHIFT 4
-#define BCHP_SWITCH_REG_LED_0_CNTRL_100m_encode_DEFAULT 0x00000001
-
-/* SWITCH_REG :: LED_0_CNTRL :: 10m_encode [03:02] */
-#define BCHP_SWITCH_REG_LED_0_CNTRL_10m_encode_MASK 0x0000000c
-#define BCHP_SWITCH_REG_LED_0_CNTRL_10m_encode_SHIFT 2
-#define BCHP_SWITCH_REG_LED_0_CNTRL_10m_encode_DEFAULT 0x00000002
-
-/* SWITCH_REG :: LED_0_CNTRL :: no_link_encode [01:00] */
-#define BCHP_SWITCH_REG_LED_0_CNTRL_no_link_encode_MASK 0x00000003
-#define BCHP_SWITCH_REG_LED_0_CNTRL_no_link_encode_SHIFT 0
-#define BCHP_SWITCH_REG_LED_0_CNTRL_no_link_encode_DEFAULT 0x00000003
-
-/***************************************************************************
- *LED_1_CNTRL - LED port 1 Control Register
- ***************************************************************************/
-/* SWITCH_REG :: LED_1_CNTRL :: reserved0 [31:28] */
-#define BCHP_SWITCH_REG_LED_1_CNTRL_reserved0_MASK 0xf0000000
-#define BCHP_SWITCH_REG_LED_1_CNTRL_reserved0_SHIFT 28
-
-/* SWITCH_REG :: LED_1_CNTRL :: act_led_pol_sel [27:27] */
-#define BCHP_SWITCH_REG_LED_1_CNTRL_act_led_pol_sel_MASK 0x08000000
-#define BCHP_SWITCH_REG_LED_1_CNTRL_act_led_pol_sel_SHIFT 27
-#define BCHP_SWITCH_REG_LED_1_CNTRL_act_led_pol_sel_DEFAULT 0x00000000
-
-/* SWITCH_REG :: LED_1_CNTRL :: spdlnk_led1_act_pol_sel [26:26] */
-#define BCHP_SWITCH_REG_LED_1_CNTRL_spdlnk_led1_act_pol_sel_MASK 0x04000000
-#define BCHP_SWITCH_REG_LED_1_CNTRL_spdlnk_led1_act_pol_sel_SHIFT 26
-#define BCHP_SWITCH_REG_LED_1_CNTRL_spdlnk_led1_act_pol_sel_DEFAULT 0x00000000
-
-/* SWITCH_REG :: LED_1_CNTRL :: spdlnk_led0_act_pol_sel [25:25] */
-#define BCHP_SWITCH_REG_LED_1_CNTRL_spdlnk_led0_act_pol_sel_MASK 0x02000000
-#define BCHP_SWITCH_REG_LED_1_CNTRL_spdlnk_led0_act_pol_sel_SHIFT 25
-#define BCHP_SWITCH_REG_LED_1_CNTRL_spdlnk_led0_act_pol_sel_DEFAULT 0x00000000
-
-/* SWITCH_REG :: LED_1_CNTRL :: spdlnk_src_sel [24:24] */
-#define BCHP_SWITCH_REG_LED_1_CNTRL_spdlnk_src_sel_MASK 0x01000000
-#define BCHP_SWITCH_REG_LED_1_CNTRL_spdlnk_src_sel_SHIFT 24
-#define BCHP_SWITCH_REG_LED_1_CNTRL_spdlnk_src_sel_DEFAULT 0x00000000
-
-/* SWITCH_REG :: LED_1_CNTRL :: act_led_act_sel [23:22] */
-#define BCHP_SWITCH_REG_LED_1_CNTRL_act_led_act_sel_MASK 0x00c00000
-#define BCHP_SWITCH_REG_LED_1_CNTRL_act_led_act_sel_SHIFT 22
-#define BCHP_SWITCH_REG_LED_1_CNTRL_act_led_act_sel_DEFAULT 0x00000000
-
-/* SWITCH_REG :: LED_1_CNTRL :: spdlnk_led1_act_sel [21:20] */
-#define BCHP_SWITCH_REG_LED_1_CNTRL_spdlnk_led1_act_sel_MASK 0x00300000
-#define BCHP_SWITCH_REG_LED_1_CNTRL_spdlnk_led1_act_sel_SHIFT 20
-#define BCHP_SWITCH_REG_LED_1_CNTRL_spdlnk_led1_act_sel_DEFAULT 0x00000000
-
-/* SWITCH_REG :: LED_1_CNTRL :: spdlnk_led0_act_sel [19:18] */
-#define BCHP_SWITCH_REG_LED_1_CNTRL_spdlnk_led0_act_sel_MASK 0x000c0000
-#define BCHP_SWITCH_REG_LED_1_CNTRL_spdlnk_led0_act_sel_SHIFT 18
-#define BCHP_SWITCH_REG_LED_1_CNTRL_spdlnk_led0_act_sel_DEFAULT 0x00000000
-
-/* SWITCH_REG :: LED_1_CNTRL :: tx_en_en [17:17] */
-#define BCHP_SWITCH_REG_LED_1_CNTRL_tx_en_en_MASK 0x00020000
-#define BCHP_SWITCH_REG_LED_1_CNTRL_tx_en_en_SHIFT 17
-#define BCHP_SWITCH_REG_LED_1_CNTRL_tx_en_en_DEFAULT 0x00000001
-
-/* SWITCH_REG :: LED_1_CNTRL :: rx_dv_en [16:16] */
-#define BCHP_SWITCH_REG_LED_1_CNTRL_rx_dv_en_MASK 0x00010000
-#define BCHP_SWITCH_REG_LED_1_CNTRL_rx_dv_en_SHIFT 16
-#define BCHP_SWITCH_REG_LED_1_CNTRL_rx_dv_en_DEFAULT 0x00000001
-
-/* SWITCH_REG :: LED_1_CNTRL :: sel_1000m_encode [15:14] */
-#define BCHP_SWITCH_REG_LED_1_CNTRL_sel_1000m_encode_MASK 0x0000c000
-#define BCHP_SWITCH_REG_LED_1_CNTRL_sel_1000m_encode_SHIFT 14
-#define BCHP_SWITCH_REG_LED_1_CNTRL_sel_1000m_encode_DEFAULT 0x00000000
-
-/* SWITCH_REG :: LED_1_CNTRL :: sel_100m_encode [13:12] */
-#define BCHP_SWITCH_REG_LED_1_CNTRL_sel_100m_encode_MASK 0x00003000
-#define BCHP_SWITCH_REG_LED_1_CNTRL_sel_100m_encode_SHIFT 12
-#define BCHP_SWITCH_REG_LED_1_CNTRL_sel_100m_encode_DEFAULT 0x00000000
-
-/* SWITCH_REG :: LED_1_CNTRL :: sel_10m_encode [11:10] */
-#define BCHP_SWITCH_REG_LED_1_CNTRL_sel_10m_encode_MASK 0x00000c00
-#define BCHP_SWITCH_REG_LED_1_CNTRL_sel_10m_encode_SHIFT 10
-#define BCHP_SWITCH_REG_LED_1_CNTRL_sel_10m_encode_DEFAULT 0x00000000
-
-/* SWITCH_REG :: LED_1_CNTRL :: sel_no_link_encode [09:08] */
-#define BCHP_SWITCH_REG_LED_1_CNTRL_sel_no_link_encode_MASK 0x00000300
-#define BCHP_SWITCH_REG_LED_1_CNTRL_sel_no_link_encode_SHIFT 8
-#define BCHP_SWITCH_REG_LED_1_CNTRL_sel_no_link_encode_DEFAULT 0x00000000
-
-/* SWITCH_REG :: LED_1_CNTRL :: 1000m_encode [07:06] */
-#define BCHP_SWITCH_REG_LED_1_CNTRL_1000m_encode_MASK 0x000000c0
-#define BCHP_SWITCH_REG_LED_1_CNTRL_1000m_encode_SHIFT 6
-#define BCHP_SWITCH_REG_LED_1_CNTRL_1000m_encode_DEFAULT 0x00000000
-
-/* SWITCH_REG :: LED_1_CNTRL :: 100m_encode [05:04] */
-#define BCHP_SWITCH_REG_LED_1_CNTRL_100m_encode_MASK 0x00000030
-#define BCHP_SWITCH_REG_LED_1_CNTRL_100m_encode_SHIFT 4
-#define BCHP_SWITCH_REG_LED_1_CNTRL_100m_encode_DEFAULT 0x00000001
-
-/* SWITCH_REG :: LED_1_CNTRL :: 10m_encode [03:02] */
-#define BCHP_SWITCH_REG_LED_1_CNTRL_10m_encode_MASK 0x0000000c
-#define BCHP_SWITCH_REG_LED_1_CNTRL_10m_encode_SHIFT 2
-#define BCHP_SWITCH_REG_LED_1_CNTRL_10m_encode_DEFAULT 0x00000002
-
-/* SWITCH_REG :: LED_1_CNTRL :: no_link_encode [01:00] */
-#define BCHP_SWITCH_REG_LED_1_CNTRL_no_link_encode_MASK 0x00000003
-#define BCHP_SWITCH_REG_LED_1_CNTRL_no_link_encode_SHIFT 0
-#define BCHP_SWITCH_REG_LED_1_CNTRL_no_link_encode_DEFAULT 0x00000003
-
-/***************************************************************************
- *LED_2_CNTRL - LED port 2 Control Register
- ***************************************************************************/
-/* SWITCH_REG :: LED_2_CNTRL :: reserved0 [31:28] */
-#define BCHP_SWITCH_REG_LED_2_CNTRL_reserved0_MASK 0xf0000000
-#define BCHP_SWITCH_REG_LED_2_CNTRL_reserved0_SHIFT 28
-
-/* SWITCH_REG :: LED_2_CNTRL :: act_led_pol_sel [27:27] */
-#define BCHP_SWITCH_REG_LED_2_CNTRL_act_led_pol_sel_MASK 0x08000000
-#define BCHP_SWITCH_REG_LED_2_CNTRL_act_led_pol_sel_SHIFT 27
-#define BCHP_SWITCH_REG_LED_2_CNTRL_act_led_pol_sel_DEFAULT 0x00000000
-
-/* SWITCH_REG :: LED_2_CNTRL :: spdlnk_led1_act_pol_sel [26:26] */
-#define BCHP_SWITCH_REG_LED_2_CNTRL_spdlnk_led1_act_pol_sel_MASK 0x04000000
-#define BCHP_SWITCH_REG_LED_2_CNTRL_spdlnk_led1_act_pol_sel_SHIFT 26
-#define BCHP_SWITCH_REG_LED_2_CNTRL_spdlnk_led1_act_pol_sel_DEFAULT 0x00000000
-
-/* SWITCH_REG :: LED_2_CNTRL :: spdlnk_led0_act_pol_sel [25:25] */
-#define BCHP_SWITCH_REG_LED_2_CNTRL_spdlnk_led0_act_pol_sel_MASK 0x02000000
-#define BCHP_SWITCH_REG_LED_2_CNTRL_spdlnk_led0_act_pol_sel_SHIFT 25
-#define BCHP_SWITCH_REG_LED_2_CNTRL_spdlnk_led0_act_pol_sel_DEFAULT 0x00000000
-
-/* SWITCH_REG :: LED_2_CNTRL :: spdlnk_src_sel [24:24] */
-#define BCHP_SWITCH_REG_LED_2_CNTRL_spdlnk_src_sel_MASK 0x01000000
-#define BCHP_SWITCH_REG_LED_2_CNTRL_spdlnk_src_sel_SHIFT 24
-#define BCHP_SWITCH_REG_LED_2_CNTRL_spdlnk_src_sel_DEFAULT 0x00000000
-
-/* SWITCH_REG :: LED_2_CNTRL :: act_led_act_sel [23:22] */
-#define BCHP_SWITCH_REG_LED_2_CNTRL_act_led_act_sel_MASK 0x00c00000
-#define BCHP_SWITCH_REG_LED_2_CNTRL_act_led_act_sel_SHIFT 22
-#define BCHP_SWITCH_REG_LED_2_CNTRL_act_led_act_sel_DEFAULT 0x00000000
-
-/* SWITCH_REG :: LED_2_CNTRL :: spdlnk_led1_act_sel [21:20] */
-#define BCHP_SWITCH_REG_LED_2_CNTRL_spdlnk_led1_act_sel_MASK 0x00300000
-#define BCHP_SWITCH_REG_LED_2_CNTRL_spdlnk_led1_act_sel_SHIFT 20
-#define BCHP_SWITCH_REG_LED_2_CNTRL_spdlnk_led1_act_sel_DEFAULT 0x00000000
-
-/* SWITCH_REG :: LED_2_CNTRL :: spdlnk_led0_act_sel [19:18] */
-#define BCHP_SWITCH_REG_LED_2_CNTRL_spdlnk_led0_act_sel_MASK 0x000c0000
-#define BCHP_SWITCH_REG_LED_2_CNTRL_spdlnk_led0_act_sel_SHIFT 18
-#define BCHP_SWITCH_REG_LED_2_CNTRL_spdlnk_led0_act_sel_DEFAULT 0x00000000
-
-/* SWITCH_REG :: LED_2_CNTRL :: tx_en_en [17:17] */
-#define BCHP_SWITCH_REG_LED_2_CNTRL_tx_en_en_MASK 0x00020000
-#define BCHP_SWITCH_REG_LED_2_CNTRL_tx_en_en_SHIFT 17
-#define BCHP_SWITCH_REG_LED_2_CNTRL_tx_en_en_DEFAULT 0x00000001
-
-/* SWITCH_REG :: LED_2_CNTRL :: rx_dv_en [16:16] */
-#define BCHP_SWITCH_REG_LED_2_CNTRL_rx_dv_en_MASK 0x00010000
-#define BCHP_SWITCH_REG_LED_2_CNTRL_rx_dv_en_SHIFT 16
-#define BCHP_SWITCH_REG_LED_2_CNTRL_rx_dv_en_DEFAULT 0x00000001
-
-/* SWITCH_REG :: LED_2_CNTRL :: sel_1000m_encode [15:14] */
-#define BCHP_SWITCH_REG_LED_2_CNTRL_sel_1000m_encode_MASK 0x0000c000
-#define BCHP_SWITCH_REG_LED_2_CNTRL_sel_1000m_encode_SHIFT 14
-#define BCHP_SWITCH_REG_LED_2_CNTRL_sel_1000m_encode_DEFAULT 0x00000000
-
-/* SWITCH_REG :: LED_2_CNTRL :: sel_100m_encode [13:12] */
-#define BCHP_SWITCH_REG_LED_2_CNTRL_sel_100m_encode_MASK 0x00003000
-#define BCHP_SWITCH_REG_LED_2_CNTRL_sel_100m_encode_SHIFT 12
-#define BCHP_SWITCH_REG_LED_2_CNTRL_sel_100m_encode_DEFAULT 0x00000000
-
-/* SWITCH_REG :: LED_2_CNTRL :: sel_10m_encode [11:10] */
-#define BCHP_SWITCH_REG_LED_2_CNTRL_sel_10m_encode_MASK 0x00000c00
-#define BCHP_SWITCH_REG_LED_2_CNTRL_sel_10m_encode_SHIFT 10
-#define BCHP_SWITCH_REG_LED_2_CNTRL_sel_10m_encode_DEFAULT 0x00000000
-
-/* SWITCH_REG :: LED_2_CNTRL :: sel_no_link_encode [09:08] */
-#define BCHP_SWITCH_REG_LED_2_CNTRL_sel_no_link_encode_MASK 0x00000300
-#define BCHP_SWITCH_REG_LED_2_CNTRL_sel_no_link_encode_SHIFT 8
-#define BCHP_SWITCH_REG_LED_2_CNTRL_sel_no_link_encode_DEFAULT 0x00000000
-
-/* SWITCH_REG :: LED_2_CNTRL :: 1000m_encode [07:06] */
-#define BCHP_SWITCH_REG_LED_2_CNTRL_1000m_encode_MASK 0x000000c0
-#define BCHP_SWITCH_REG_LED_2_CNTRL_1000m_encode_SHIFT 6
-#define BCHP_SWITCH_REG_LED_2_CNTRL_1000m_encode_DEFAULT 0x00000000
-
-/* SWITCH_REG :: LED_2_CNTRL :: 100m_encode [05:04] */
-#define BCHP_SWITCH_REG_LED_2_CNTRL_100m_encode_MASK 0x00000030
-#define BCHP_SWITCH_REG_LED_2_CNTRL_100m_encode_SHIFT 4
-#define BCHP_SWITCH_REG_LED_2_CNTRL_100m_encode_DEFAULT 0x00000001
-
-/* SWITCH_REG :: LED_2_CNTRL :: 10m_encode [03:02] */
-#define BCHP_SWITCH_REG_LED_2_CNTRL_10m_encode_MASK 0x0000000c
-#define BCHP_SWITCH_REG_LED_2_CNTRL_10m_encode_SHIFT 2
-#define BCHP_SWITCH_REG_LED_2_CNTRL_10m_encode_DEFAULT 0x00000002
-
-/* SWITCH_REG :: LED_2_CNTRL :: no_link_encode [01:00] */
-#define BCHP_SWITCH_REG_LED_2_CNTRL_no_link_encode_MASK 0x00000003
-#define BCHP_SWITCH_REG_LED_2_CNTRL_no_link_encode_SHIFT 0
-#define BCHP_SWITCH_REG_LED_2_CNTRL_no_link_encode_DEFAULT 0x00000003
-
-/***************************************************************************
- *LED_3_CNTRL - LED port 3 Control Register
- ***************************************************************************/
-/* SWITCH_REG :: LED_3_CNTRL :: reserved0 [31:28] */
-#define BCHP_SWITCH_REG_LED_3_CNTRL_reserved0_MASK 0xf0000000
-#define BCHP_SWITCH_REG_LED_3_CNTRL_reserved0_SHIFT 28
-
-/* SWITCH_REG :: LED_3_CNTRL :: act_led_pol_sel [27:27] */
-#define BCHP_SWITCH_REG_LED_3_CNTRL_act_led_pol_sel_MASK 0x08000000
-#define BCHP_SWITCH_REG_LED_3_CNTRL_act_led_pol_sel_SHIFT 27
-#define BCHP_SWITCH_REG_LED_3_CNTRL_act_led_pol_sel_DEFAULT 0x00000000
-
-/* SWITCH_REG :: LED_3_CNTRL :: spdlnk_led1_act_pol_sel [26:26] */
-#define BCHP_SWITCH_REG_LED_3_CNTRL_spdlnk_led1_act_pol_sel_MASK 0x04000000
-#define BCHP_SWITCH_REG_LED_3_CNTRL_spdlnk_led1_act_pol_sel_SHIFT 26
-#define BCHP_SWITCH_REG_LED_3_CNTRL_spdlnk_led1_act_pol_sel_DEFAULT 0x00000000
-
-/* SWITCH_REG :: LED_3_CNTRL :: spdlnk_led0_act_pol_sel [25:25] */
-#define BCHP_SWITCH_REG_LED_3_CNTRL_spdlnk_led0_act_pol_sel_MASK 0x02000000
-#define BCHP_SWITCH_REG_LED_3_CNTRL_spdlnk_led0_act_pol_sel_SHIFT 25
-#define BCHP_SWITCH_REG_LED_3_CNTRL_spdlnk_led0_act_pol_sel_DEFAULT 0x00000000
-
-/* SWITCH_REG :: LED_3_CNTRL :: spdlnk_src_sel [24:24] */
-#define BCHP_SWITCH_REG_LED_3_CNTRL_spdlnk_src_sel_MASK 0x01000000
-#define BCHP_SWITCH_REG_LED_3_CNTRL_spdlnk_src_sel_SHIFT 24
-#define BCHP_SWITCH_REG_LED_3_CNTRL_spdlnk_src_sel_DEFAULT 0x00000000
-
-/* SWITCH_REG :: LED_3_CNTRL :: act_led_act_sel [23:22] */
-#define BCHP_SWITCH_REG_LED_3_CNTRL_act_led_act_sel_MASK 0x00c00000
-#define BCHP_SWITCH_REG_LED_3_CNTRL_act_led_act_sel_SHIFT 22
-#define BCHP_SWITCH_REG_LED_3_CNTRL_act_led_act_sel_DEFAULT 0x00000000
-
-/* SWITCH_REG :: LED_3_CNTRL :: spdlnk_led1_act_sel [21:20] */
-#define BCHP_SWITCH_REG_LED_3_CNTRL_spdlnk_led1_act_sel_MASK 0x00300000
-#define BCHP_SWITCH_REG_LED_3_CNTRL_spdlnk_led1_act_sel_SHIFT 20
-#define BCHP_SWITCH_REG_LED_3_CNTRL_spdlnk_led1_act_sel_DEFAULT 0x00000000
-
-/* SWITCH_REG :: LED_3_CNTRL :: spdlnk_led0_act_sel [19:18] */
-#define BCHP_SWITCH_REG_LED_3_CNTRL_spdlnk_led0_act_sel_MASK 0x000c0000
-#define BCHP_SWITCH_REG_LED_3_CNTRL_spdlnk_led0_act_sel_SHIFT 18
-#define BCHP_SWITCH_REG_LED_3_CNTRL_spdlnk_led0_act_sel_DEFAULT 0x00000000
-
-/* SWITCH_REG :: LED_3_CNTRL :: tx_en_en [17:17] */
-#define BCHP_SWITCH_REG_LED_3_CNTRL_tx_en_en_MASK 0x00020000
-#define BCHP_SWITCH_REG_LED_3_CNTRL_tx_en_en_SHIFT 17
-#define BCHP_SWITCH_REG_LED_3_CNTRL_tx_en_en_DEFAULT 0x00000001
-
-/* SWITCH_REG :: LED_3_CNTRL :: rx_dv_en [16:16] */
-#define BCHP_SWITCH_REG_LED_3_CNTRL_rx_dv_en_MASK 0x00010000
-#define BCHP_SWITCH_REG_LED_3_CNTRL_rx_dv_en_SHIFT 16
-#define BCHP_SWITCH_REG_LED_3_CNTRL_rx_dv_en_DEFAULT 0x00000001
-
-/* SWITCH_REG :: LED_3_CNTRL :: sel_1000m_encode [15:14] */
-#define BCHP_SWITCH_REG_LED_3_CNTRL_sel_1000m_encode_MASK 0x0000c000
-#define BCHP_SWITCH_REG_LED_3_CNTRL_sel_1000m_encode_SHIFT 14
-#define BCHP_SWITCH_REG_LED_3_CNTRL_sel_1000m_encode_DEFAULT 0x00000000
-
-/* SWITCH_REG :: LED_3_CNTRL :: sel_100m_encode [13:12] */
-#define BCHP_SWITCH_REG_LED_3_CNTRL_sel_100m_encode_MASK 0x00003000
-#define BCHP_SWITCH_REG_LED_3_CNTRL_sel_100m_encode_SHIFT 12
-#define BCHP_SWITCH_REG_LED_3_CNTRL_sel_100m_encode_DEFAULT 0x00000000
-
-/* SWITCH_REG :: LED_3_CNTRL :: sel_10m_encode [11:10] */
-#define BCHP_SWITCH_REG_LED_3_CNTRL_sel_10m_encode_MASK 0x00000c00
-#define BCHP_SWITCH_REG_LED_3_CNTRL_sel_10m_encode_SHIFT 10
-#define BCHP_SWITCH_REG_LED_3_CNTRL_sel_10m_encode_DEFAULT 0x00000000
-
-/* SWITCH_REG :: LED_3_CNTRL :: sel_no_link_encode [09:08] */
-#define BCHP_SWITCH_REG_LED_3_CNTRL_sel_no_link_encode_MASK 0x00000300
-#define BCHP_SWITCH_REG_LED_3_CNTRL_sel_no_link_encode_SHIFT 8
-#define BCHP_SWITCH_REG_LED_3_CNTRL_sel_no_link_encode_DEFAULT 0x00000000
-
-/* SWITCH_REG :: LED_3_CNTRL :: 1000m_encode [07:06] */
-#define BCHP_SWITCH_REG_LED_3_CNTRL_1000m_encode_MASK 0x000000c0
-#define BCHP_SWITCH_REG_LED_3_CNTRL_1000m_encode_SHIFT 6
-#define BCHP_SWITCH_REG_LED_3_CNTRL_1000m_encode_DEFAULT 0x00000000
-
-/* SWITCH_REG :: LED_3_CNTRL :: 100m_encode [05:04] */
-#define BCHP_SWITCH_REG_LED_3_CNTRL_100m_encode_MASK 0x00000030
-#define BCHP_SWITCH_REG_LED_3_CNTRL_100m_encode_SHIFT 4
-#define BCHP_SWITCH_REG_LED_3_CNTRL_100m_encode_DEFAULT 0x00000001
-
-/* SWITCH_REG :: LED_3_CNTRL :: 10m_encode [03:02] */
-#define BCHP_SWITCH_REG_LED_3_CNTRL_10m_encode_MASK 0x0000000c
-#define BCHP_SWITCH_REG_LED_3_CNTRL_10m_encode_SHIFT 2
-#define BCHP_SWITCH_REG_LED_3_CNTRL_10m_encode_DEFAULT 0x00000002
-
-/* SWITCH_REG :: LED_3_CNTRL :: no_link_encode [01:00] */
-#define BCHP_SWITCH_REG_LED_3_CNTRL_no_link_encode_MASK 0x00000003
-#define BCHP_SWITCH_REG_LED_3_CNTRL_no_link_encode_SHIFT 0
-#define BCHP_SWITCH_REG_LED_3_CNTRL_no_link_encode_DEFAULT 0x00000003
-
-/***************************************************************************
- *LED_7_CNTRL - LED port 7 Control Register
- ***************************************************************************/
-/* SWITCH_REG :: LED_7_CNTRL :: reserved0 [31:28] */
-#define BCHP_SWITCH_REG_LED_7_CNTRL_reserved0_MASK 0xf0000000
-#define BCHP_SWITCH_REG_LED_7_CNTRL_reserved0_SHIFT 28
-
-/* SWITCH_REG :: LED_7_CNTRL :: act_led_pol_sel [27:27] */
-#define BCHP_SWITCH_REG_LED_7_CNTRL_act_led_pol_sel_MASK 0x08000000
-#define BCHP_SWITCH_REG_LED_7_CNTRL_act_led_pol_sel_SHIFT 27
-#define BCHP_SWITCH_REG_LED_7_CNTRL_act_led_pol_sel_DEFAULT 0x00000000
-
-/* SWITCH_REG :: LED_7_CNTRL :: spdlnk_led1_act_pol_sel [26:26] */
-#define BCHP_SWITCH_REG_LED_7_CNTRL_spdlnk_led1_act_pol_sel_MASK 0x04000000
-#define BCHP_SWITCH_REG_LED_7_CNTRL_spdlnk_led1_act_pol_sel_SHIFT 26
-#define BCHP_SWITCH_REG_LED_7_CNTRL_spdlnk_led1_act_pol_sel_DEFAULT 0x00000000
-
-/* SWITCH_REG :: LED_7_CNTRL :: spdlnk_led0_act_pol_sel [25:25] */
-#define BCHP_SWITCH_REG_LED_7_CNTRL_spdlnk_led0_act_pol_sel_MASK 0x02000000
-#define BCHP_SWITCH_REG_LED_7_CNTRL_spdlnk_led0_act_pol_sel_SHIFT 25
-#define BCHP_SWITCH_REG_LED_7_CNTRL_spdlnk_led0_act_pol_sel_DEFAULT 0x00000000
-
-/* SWITCH_REG :: LED_7_CNTRL :: spdlnk_src_sel [24:24] */
-#define BCHP_SWITCH_REG_LED_7_CNTRL_spdlnk_src_sel_MASK 0x01000000
-#define BCHP_SWITCH_REG_LED_7_CNTRL_spdlnk_src_sel_SHIFT 24
-#define BCHP_SWITCH_REG_LED_7_CNTRL_spdlnk_src_sel_DEFAULT 0x00000000
-
-/* SWITCH_REG :: LED_7_CNTRL :: act_led_act_sel [23:22] */
-#define BCHP_SWITCH_REG_LED_7_CNTRL_act_led_act_sel_MASK 0x00c00000
-#define BCHP_SWITCH_REG_LED_7_CNTRL_act_led_act_sel_SHIFT 22
-#define BCHP_SWITCH_REG_LED_7_CNTRL_act_led_act_sel_DEFAULT 0x00000000
-
-/* SWITCH_REG :: LED_7_CNTRL :: spdlnk_led1_act_sel [21:20] */
-#define BCHP_SWITCH_REG_LED_7_CNTRL_spdlnk_led1_act_sel_MASK 0x00300000
-#define BCHP_SWITCH_REG_LED_7_CNTRL_spdlnk_led1_act_sel_SHIFT 20
-#define BCHP_SWITCH_REG_LED_7_CNTRL_spdlnk_led1_act_sel_DEFAULT 0x00000000
-
-/* SWITCH_REG :: LED_7_CNTRL :: spdlnk_led0_act_sel [19:18] */
-#define BCHP_SWITCH_REG_LED_7_CNTRL_spdlnk_led0_act_sel_MASK 0x000c0000
-#define BCHP_SWITCH_REG_LED_7_CNTRL_spdlnk_led0_act_sel_SHIFT 18
-#define BCHP_SWITCH_REG_LED_7_CNTRL_spdlnk_led0_act_sel_DEFAULT 0x00000000
-
-/* SWITCH_REG :: LED_7_CNTRL :: tx_en_en [17:17] */
-#define BCHP_SWITCH_REG_LED_7_CNTRL_tx_en_en_MASK 0x00020000
-#define BCHP_SWITCH_REG_LED_7_CNTRL_tx_en_en_SHIFT 17
-#define BCHP_SWITCH_REG_LED_7_CNTRL_tx_en_en_DEFAULT 0x00000001
-
-/* SWITCH_REG :: LED_7_CNTRL :: rx_dv_en [16:16] */
-#define BCHP_SWITCH_REG_LED_7_CNTRL_rx_dv_en_MASK 0x00010000
-#define BCHP_SWITCH_REG_LED_7_CNTRL_rx_dv_en_SHIFT 16
-#define BCHP_SWITCH_REG_LED_7_CNTRL_rx_dv_en_DEFAULT 0x00000001
-
-/* SWITCH_REG :: LED_7_CNTRL :: sel_1000m_encode [15:14] */
-#define BCHP_SWITCH_REG_LED_7_CNTRL_sel_1000m_encode_MASK 0x0000c000
-#define BCHP_SWITCH_REG_LED_7_CNTRL_sel_1000m_encode_SHIFT 14
-#define BCHP_SWITCH_REG_LED_7_CNTRL_sel_1000m_encode_DEFAULT 0x00000000
-
-/* SWITCH_REG :: LED_7_CNTRL :: sel_100m_encode [13:12] */
-#define BCHP_SWITCH_REG_LED_7_CNTRL_sel_100m_encode_MASK 0x00003000
-#define BCHP_SWITCH_REG_LED_7_CNTRL_sel_100m_encode_SHIFT 12
-#define BCHP_SWITCH_REG_LED_7_CNTRL_sel_100m_encode_DEFAULT 0x00000000
-
-/* SWITCH_REG :: LED_7_CNTRL :: sel_10m_encode [11:10] */
-#define BCHP_SWITCH_REG_LED_7_CNTRL_sel_10m_encode_MASK 0x00000c00
-#define BCHP_SWITCH_REG_LED_7_CNTRL_sel_10m_encode_SHIFT 10
-#define BCHP_SWITCH_REG_LED_7_CNTRL_sel_10m_encode_DEFAULT 0x00000000
-
-/* SWITCH_REG :: LED_7_CNTRL :: sel_no_link_encode [09:08] */
-#define BCHP_SWITCH_REG_LED_7_CNTRL_sel_no_link_encode_MASK 0x00000300
-#define BCHP_SWITCH_REG_LED_7_CNTRL_sel_no_link_encode_SHIFT 8
-#define BCHP_SWITCH_REG_LED_7_CNTRL_sel_no_link_encode_DEFAULT 0x00000000
-
-/* SWITCH_REG :: LED_7_CNTRL :: 1000m_encode [07:06] */
-#define BCHP_SWITCH_REG_LED_7_CNTRL_1000m_encode_MASK 0x000000c0
-#define BCHP_SWITCH_REG_LED_7_CNTRL_1000m_encode_SHIFT 6
-#define BCHP_SWITCH_REG_LED_7_CNTRL_1000m_encode_DEFAULT 0x00000000
-
-/* SWITCH_REG :: LED_7_CNTRL :: 100m_encode [05:04] */
-#define BCHP_SWITCH_REG_LED_7_CNTRL_100m_encode_MASK 0x00000030
-#define BCHP_SWITCH_REG_LED_7_CNTRL_100m_encode_SHIFT 4
-#define BCHP_SWITCH_REG_LED_7_CNTRL_100m_encode_DEFAULT 0x00000001
-
-/* SWITCH_REG :: LED_7_CNTRL :: 10m_encode [03:02] */
-#define BCHP_SWITCH_REG_LED_7_CNTRL_10m_encode_MASK 0x0000000c
-#define BCHP_SWITCH_REG_LED_7_CNTRL_10m_encode_SHIFT 2
-#define BCHP_SWITCH_REG_LED_7_CNTRL_10m_encode_DEFAULT 0x00000002
-
-/* SWITCH_REG :: LED_7_CNTRL :: no_link_encode [01:00] */
-#define BCHP_SWITCH_REG_LED_7_CNTRL_no_link_encode_MASK 0x00000003
-#define BCHP_SWITCH_REG_LED_7_CNTRL_no_link_encode_SHIFT 0
-#define BCHP_SWITCH_REG_LED_7_CNTRL_no_link_encode_DEFAULT 0x00000003
-
-/***************************************************************************
- *RGMII_9_CNTRL - RGMII port 9 Control Register
- ***************************************************************************/
-/* SWITCH_REG :: RGMII_9_CNTRL :: reserved0 [31:08] */
-#define BCHP_SWITCH_REG_RGMII_9_CNTRL_reserved0_MASK 0xffffff00
-#define BCHP_SWITCH_REG_RGMII_9_CNTRL_reserved0_SHIFT 8
-
-/* SWITCH_REG :: RGMII_9_CNTRL :: tx_pause_en [07:07] */
-#define BCHP_SWITCH_REG_RGMII_9_CNTRL_tx_pause_en_MASK 0x00000080
-#define BCHP_SWITCH_REG_RGMII_9_CNTRL_tx_pause_en_SHIFT 7
-#define BCHP_SWITCH_REG_RGMII_9_CNTRL_tx_pause_en_DEFAULT 0x00000000
-
-/* SWITCH_REG :: RGMII_9_CNTRL :: rx_pause_en [06:06] */
-#define BCHP_SWITCH_REG_RGMII_9_CNTRL_rx_pause_en_MASK 0x00000040
-#define BCHP_SWITCH_REG_RGMII_9_CNTRL_rx_pause_en_SHIFT 6
-#define BCHP_SWITCH_REG_RGMII_9_CNTRL_rx_pause_en_DEFAULT 0x00000000
-
-/* SWITCH_REG :: RGMII_9_CNTRL :: rvmii_ref_sel [05:05] */
-#define BCHP_SWITCH_REG_RGMII_9_CNTRL_rvmii_ref_sel_MASK 0x00000020
-#define BCHP_SWITCH_REG_RGMII_9_CNTRL_rvmii_ref_sel_SHIFT 5
-#define BCHP_SWITCH_REG_RGMII_9_CNTRL_rvmii_ref_sel_DEFAULT 0x00000000
-
-/* SWITCH_REG :: RGMII_9_CNTRL :: port_mode [04:02] */
-#define BCHP_SWITCH_REG_RGMII_9_CNTRL_port_mode_MASK 0x0000001c
-#define BCHP_SWITCH_REG_RGMII_9_CNTRL_port_mode_SHIFT 2
-#define BCHP_SWITCH_REG_RGMII_9_CNTRL_port_mode_DEFAULT 0x00000003
-
-/* SWITCH_REG :: RGMII_9_CNTRL :: id_mode_dis [01:01] */
-#define BCHP_SWITCH_REG_RGMII_9_CNTRL_id_mode_dis_MASK 0x00000002
-#define BCHP_SWITCH_REG_RGMII_9_CNTRL_id_mode_dis_SHIFT 1
-#define BCHP_SWITCH_REG_RGMII_9_CNTRL_id_mode_dis_DEFAULT 0x00000000
-
-/* SWITCH_REG :: RGMII_9_CNTRL :: rgmii_mode_en [00:00] */
-#define BCHP_SWITCH_REG_RGMII_9_CNTRL_rgmii_mode_en_MASK 0x00000001
-#define BCHP_SWITCH_REG_RGMII_9_CNTRL_rgmii_mode_en_SHIFT 0
-#define BCHP_SWITCH_REG_RGMII_9_CNTRL_rgmii_mode_en_DEFAULT 0x00000000
-
-/***************************************************************************
- *RGMII_9_IB_STATUS - RGMII port 9 InBand Status Register
- ***************************************************************************/
-/* SWITCH_REG :: RGMII_9_IB_STATUS :: reserved0 [31:04] */
-#define BCHP_SWITCH_REG_RGMII_9_IB_STATUS_reserved0_MASK 0xfffffff0
-#define BCHP_SWITCH_REG_RGMII_9_IB_STATUS_reserved0_SHIFT 4
-
-/* SWITCH_REG :: RGMII_9_IB_STATUS :: link_decode [03:03] */
-#define BCHP_SWITCH_REG_RGMII_9_IB_STATUS_link_decode_MASK 0x00000008
-#define BCHP_SWITCH_REG_RGMII_9_IB_STATUS_link_decode_SHIFT 3
-#define BCHP_SWITCH_REG_RGMII_9_IB_STATUS_link_decode_DEFAULT 0x00000000
-
-/* SWITCH_REG :: RGMII_9_IB_STATUS :: duplex_decode [02:02] */
-#define BCHP_SWITCH_REG_RGMII_9_IB_STATUS_duplex_decode_MASK 0x00000004
-#define BCHP_SWITCH_REG_RGMII_9_IB_STATUS_duplex_decode_SHIFT 2
-#define BCHP_SWITCH_REG_RGMII_9_IB_STATUS_duplex_decode_DEFAULT 0x00000000
-
-/* SWITCH_REG :: RGMII_9_IB_STATUS :: speed_decode [01:00] */
-#define BCHP_SWITCH_REG_RGMII_9_IB_STATUS_speed_decode_MASK 0x00000003
-#define BCHP_SWITCH_REG_RGMII_9_IB_STATUS_speed_decode_SHIFT 0
-#define BCHP_SWITCH_REG_RGMII_9_IB_STATUS_speed_decode_DEFAULT 0x00000000
-
-/***************************************************************************
- *RGMII_9_RX_CLOCK_DELAY_CNTRL - RGMII port 9 RX Clock Delay Control Register
- ***************************************************************************/
-/* SWITCH_REG :: RGMII_9_RX_CLOCK_DELAY_CNTRL :: reserved0 [31:08] */
-#define BCHP_SWITCH_REG_RGMII_9_RX_CLOCK_DELAY_CNTRL_reserved0_MASK 0xffffff00
-#define BCHP_SWITCH_REG_RGMII_9_RX_CLOCK_DELAY_CNTRL_reserved0_SHIFT 8
-
-/* SWITCH_REG :: RGMII_9_RX_CLOCK_DELAY_CNTRL :: dly_override [07:07] */
-#define BCHP_SWITCH_REG_RGMII_9_RX_CLOCK_DELAY_CNTRL_dly_override_MASK 0x00000080
-#define BCHP_SWITCH_REG_RGMII_9_RX_CLOCK_DELAY_CNTRL_dly_override_SHIFT 7
-#define BCHP_SWITCH_REG_RGMII_9_RX_CLOCK_DELAY_CNTRL_dly_override_DEFAULT 0x00000001
-
-/* SWITCH_REG :: RGMII_9_RX_CLOCK_DELAY_CNTRL :: dly_sel [06:06] */
-#define BCHP_SWITCH_REG_RGMII_9_RX_CLOCK_DELAY_CNTRL_dly_sel_MASK 0x00000040
-#define BCHP_SWITCH_REG_RGMII_9_RX_CLOCK_DELAY_CNTRL_dly_sel_SHIFT 6
-#define BCHP_SWITCH_REG_RGMII_9_RX_CLOCK_DELAY_CNTRL_dly_sel_DEFAULT 0x00000001
-
-/* SWITCH_REG :: RGMII_9_RX_CLOCK_DELAY_CNTRL :: bypass [05:05] */
-#define BCHP_SWITCH_REG_RGMII_9_RX_CLOCK_DELAY_CNTRL_bypass_MASK 0x00000020
-#define BCHP_SWITCH_REG_RGMII_9_RX_CLOCK_DELAY_CNTRL_bypass_SHIFT 5
-#define BCHP_SWITCH_REG_RGMII_9_RX_CLOCK_DELAY_CNTRL_bypass_DEFAULT 0x00000001
-
-/* SWITCH_REG :: RGMII_9_RX_CLOCK_DELAY_CNTRL :: iddq [04:04] */
-#define BCHP_SWITCH_REG_RGMII_9_RX_CLOCK_DELAY_CNTRL_iddq_MASK 0x00000010
-#define BCHP_SWITCH_REG_RGMII_9_RX_CLOCK_DELAY_CNTRL_iddq_SHIFT 4
-#define BCHP_SWITCH_REG_RGMII_9_RX_CLOCK_DELAY_CNTRL_iddq_DEFAULT 0x00000000
-
-/* SWITCH_REG :: RGMII_9_RX_CLOCK_DELAY_CNTRL :: drng [03:02] */
-#define BCHP_SWITCH_REG_RGMII_9_RX_CLOCK_DELAY_CNTRL_drng_MASK 0x0000000c
-#define BCHP_SWITCH_REG_RGMII_9_RX_CLOCK_DELAY_CNTRL_drng_SHIFT 2
-#define BCHP_SWITCH_REG_RGMII_9_RX_CLOCK_DELAY_CNTRL_drng_DEFAULT 0x00000000
-
-/* SWITCH_REG :: RGMII_9_RX_CLOCK_DELAY_CNTRL :: ctri [01:00] */
-#define BCHP_SWITCH_REG_RGMII_9_RX_CLOCK_DELAY_CNTRL_ctri_MASK 0x00000003
-#define BCHP_SWITCH_REG_RGMII_9_RX_CLOCK_DELAY_CNTRL_ctri_SHIFT 0
-#define BCHP_SWITCH_REG_RGMII_9_RX_CLOCK_DELAY_CNTRL_ctri_DEFAULT 0x00000000
-
-#endif /* #ifndef BCHP_SWITCH_REG_H__ */
-
-/* End of File */
diff --git a/include/linux/brcmstb/7145a0/bchp_usb_ctrl.h b/include/linux/brcmstb/7145a0/bchp_usb_ctrl.h
deleted file mode 100644
index 29b046e..0000000
--- a/include/linux/brcmstb/7145a0/bchp_usb_ctrl.h
+++ /dev/null
@@ -1,1154 +0,0 @@
-/***************************************************************************
- * Copyright (c) 1999-2014, Broadcom Corporation
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
- *
- * Module Description:
- * DO NOT EDIT THIS FILE DIRECTLY
- *
- * This module was generated magically with RDB from a source description
- * file. You must edit the source file for changes to be made to this file.
- *
- *
- * Date: Generated on Wed Sep 3 13:17:37 2014
- * Full Compile MD5 Checksum a8ee62ccf9dde43435c825f266da463d
- * (minus title and desc)
- * MD5 Checksum e373b364a1742e13a0f9eb15fd8aa94f
- *
- * Compiled with: RDB Utility combo_header.pl
- * RDB Parser 3.0
- * unknown unknown
- * Perl Interpreter 5.008005
- * Operating System linux
- *
- * Revision History:
- *
- * $brcm_Log: $
- *
- ***************************************************************************/
-
-#ifndef BCHP_USB_CTRL_H__
-#define BCHP_USB_CTRL_H__
-
-/***************************************************************************
- *USB_CTRL - USB Control Registers
- ***************************************************************************/
-#define BCHP_USB_CTRL_SETUP 0x20930200 /* Setup Register */
-#define BCHP_USB_CTRL_PLL_CTL 0x20930204 /* PLL Control Register */
-#define BCHP_USB_CTRL_FLADJ_VALUE 0x20930208 /* Frame Adjust Value */
-#define BCHP_USB_CTRL_EBRIDGE 0x2093020c /* Control Register for EHCI Bridge */
-#define BCHP_USB_CTRL_OBRIDGE 0x20930210 /* Control Register for OHCI Bridge */
-#define BCHP_USB_CTRL_MDIO 0x20930214 /* MDIO Interface Programming Register */
-#define BCHP_USB_CTRL_MDIO2 0x20930218 /* MDIO Interface Read Register */
-#define BCHP_USB_CTRL_TEST_PORT_CTL 0x2093021c /* Test Port Control Register */
-#define BCHP_USB_CTRL_USB_SIMCTL 0x20930220 /* Simulation Register */
-#define BCHP_USB_CTRL_USB_TESTCTL 0x20930224 /* Throutput Test Control */
-#define BCHP_USB_CTRL_USB_TESTMON 0x20930228 /* Throughput Test Monitor */
-#define BCHP_USB_CTRL_UTMI_CTL_1 0x2093022c /* UTMI Control Register */
-#define BCHP_USB_CTRL_UTMI_CTL_2 0x20930230 /* UTMI Control 2 Register */
-#define BCHP_USB_CTRL_USB_PM 0x20930234 /* Power Management Register */
-#define BCHP_USB_CTRL_OHCI_ADDR_EXT 0x20930238 /* OHCI ADDRESS Extension */
-#define BCHP_USB_CTRL_SPARE1 0x2093023c /* Spare1 Register for future use */
-#define BCHP_USB_CTRL_PLL_LDO_CTL 0x20930240 /* 28NM USBPHY LDO Control */
-#define BCHP_USB_CTRL_PLL_LDO_PLLBIAS 0x20930244 /* 28NM USBPHY PLLBIAS Control */
-#define BCHP_USB_CTRL_PLL_AFE_BG_CNTL 0x20930248 /* 28NM USBPHY AFE Bandgap Control */
-#define BCHP_USB_CTRL_AFE_USBIO_TST 0x2093024c /* 28NM USBPHY AFE Bandgap Control */
-#define BCHP_USB_CTRL_PLL_NDIV_FRAC 0x20930250 /* PLL Feedback Divider Control Register */
-#define BCHP_USB_CTRL_SPARE2 0x20930254 /* Spare2 Register for future use */
-#define BCHP_USB_CTRL_SPARE3 0x20930258 /* Spare1 Register for future use */
-#define BCHP_USB_CTRL_SPARE4 0x2093025c /* Spare1 Register for future use */
-#define BCHP_USB_CTRL_USB30_CTL1 0x20930260 /* USB30 CONTROL Register 1 */
-#define BCHP_USB_CTRL_USB30_CTL2 0x20930264 /* USB30 CONTROL Register 2 */
-#define BCHP_USB_CTRL_USB30_CTL3 0x20930268 /* USB30 CONTROL Register 3 */
-#define BCHP_USB_CTRL_USB30_CTL4 0x2093026c /* USB30 CONTROL Register 4 */
-#define BCHP_USB_CTRL_SPARE5 0x20930270 /* Spare1 Register for future use */
-#define BCHP_USB_CTRL_SPARE6 0x20930274 /* Spare2 Register for future use */
-
-/***************************************************************************
- *SETUP - Setup Register
- ***************************************************************************/
-/* USB_CTRL :: SETUP :: OC_DISABLE [31:28] */
-#define BCHP_USB_CTRL_SETUP_OC_DISABLE_MASK 0xf0000000
-#define BCHP_USB_CTRL_SETUP_OC_DISABLE_SHIFT 28
-#define BCHP_USB_CTRL_SETUP_OC_DISABLE_DEFAULT 0x00000000
-
-/* USB_CTRL :: SETUP :: SRAM_CS_DIS [27:25] */
-#define BCHP_USB_CTRL_SETUP_SRAM_CS_DIS_MASK 0x0e000000
-#define BCHP_USB_CTRL_SETUP_SRAM_CS_DIS_SHIFT 25
-#define BCHP_USB_CTRL_SETUP_SRAM_CS_DIS_DEFAULT 0x00000000
-
-/* USB_CTRL :: SETUP :: SETUP_SPARE [24:19] */
-#define BCHP_USB_CTRL_SETUP_SETUP_SPARE_MASK 0x01f80000
-#define BCHP_USB_CTRL_SETUP_SETUP_SPARE_SHIFT 19
-#define BCHP_USB_CTRL_SETUP_SETUP_SPARE_DEFAULT 0x00000000
-
-/* USB_CTRL :: SETUP :: ohci_susp_lgcy [18:18] */
-#define BCHP_USB_CTRL_SETUP_ohci_susp_lgcy_MASK 0x00040000
-#define BCHP_USB_CTRL_SETUP_ohci_susp_lgcy_SHIFT 18
-#define BCHP_USB_CTRL_SETUP_ohci_susp_lgcy_DEFAULT 0x00000000
-
-/* USB_CTRL :: SETUP :: ss_ulpi_pp2vbus [17:17] */
-#define BCHP_USB_CTRL_SETUP_ss_ulpi_pp2vbus_MASK 0x00020000
-#define BCHP_USB_CTRL_SETUP_ss_ulpi_pp2vbus_SHIFT 17
-#define BCHP_USB_CTRL_SETUP_ss_ulpi_pp2vbus_DEFAULT 0x00000000
-
-/* USB_CTRL :: SETUP :: ss_ehci64bit_en [16:16] */
-#define BCHP_USB_CTRL_SETUP_ss_ehci64bit_en_MASK 0x00010000
-#define BCHP_USB_CTRL_SETUP_ss_ehci64bit_en_SHIFT 16
-#define BCHP_USB_CTRL_SETUP_ss_ehci64bit_en_DEFAULT 0x00000000
-
-/* USB_CTRL :: SETUP :: scb2_en [15:15] */
-#define BCHP_USB_CTRL_SETUP_scb2_en_MASK 0x00008000
-#define BCHP_USB_CTRL_SETUP_scb2_en_SHIFT 15
-#define BCHP_USB_CTRL_SETUP_scb2_en_DEFAULT 0x00000000
-
-/* USB_CTRL :: SETUP :: scb1_en [14:14] */
-#define BCHP_USB_CTRL_SETUP_scb1_en_MASK 0x00004000
-#define BCHP_USB_CTRL_SETUP_scb1_en_SHIFT 14
-#define BCHP_USB_CTRL_SETUP_scb1_en_DEFAULT 0x00000000
-
-/* USB_CTRL :: SETUP :: scb_client_swap [13:13] */
-#define BCHP_USB_CTRL_SETUP_scb_client_swap_MASK 0x00002000
-#define BCHP_USB_CTRL_SETUP_scb_client_swap_SHIFT 13
-#define BCHP_USB_CTRL_SETUP_scb_client_swap_DEFAULT 0x00000000
-
-/* USB_CTRL :: SETUP :: async_expire_dis [12:12] */
-#define BCHP_USB_CTRL_SETUP_async_expire_dis_MASK 0x00001000
-#define BCHP_USB_CTRL_SETUP_async_expire_dis_SHIFT 12
-#define BCHP_USB_CTRL_SETUP_async_expire_dis_DEFAULT 0x00000000
-
-/* USB_CTRL :: SETUP :: SETUP_SPARE1 [11:10] */
-#define BCHP_USB_CTRL_SETUP_SETUP_SPARE1_MASK 0x00000c00
-#define BCHP_USB_CTRL_SETUP_SETUP_SPARE1_SHIFT 10
-#define BCHP_USB_CTRL_SETUP_SETUP_SPARE1_DEFAULT 0x00000000
-
-/* USB_CTRL :: SETUP :: soft_shutdown [09:09] */
-#define BCHP_USB_CTRL_SETUP_soft_shutdown_MASK 0x00000200
-#define BCHP_USB_CTRL_SETUP_soft_shutdown_SHIFT 9
-#define BCHP_USB_CTRL_SETUP_soft_shutdown_DEFAULT 0x00000000
-
-/* USB_CTRL :: SETUP :: utmi_bkward_en [08:08] */
-#define BCHP_USB_CTRL_SETUP_utmi_bkward_en_MASK 0x00000100
-#define BCHP_USB_CTRL_SETUP_utmi_bkward_en_SHIFT 8
-#define BCHP_USB_CTRL_SETUP_utmi_bkward_en_DEFAULT 0x00000000
-
-/* USB_CTRL :: SETUP :: utmi_pls_en [07:07] */
-#define BCHP_USB_CTRL_SETUP_utmi_pls_en_MASK 0x00000080
-#define BCHP_USB_CTRL_SETUP_utmi_pls_en_SHIFT 7
-#define BCHP_USB_CTRL_SETUP_utmi_pls_en_DEFAULT 0x00000000
-
-/* USB_CTRL :: SETUP :: soft_reset [06:06] */
-#define BCHP_USB_CTRL_SETUP_soft_reset_MASK 0x00000040
-#define BCHP_USB_CTRL_SETUP_soft_reset_SHIFT 6
-#define BCHP_USB_CTRL_SETUP_soft_reset_DEFAULT 0x00000000
-
-/* USB_CTRL :: SETUP :: IPP [05:05] */
-#define BCHP_USB_CTRL_SETUP_IPP_MASK 0x00000020
-#define BCHP_USB_CTRL_SETUP_IPP_SHIFT 5
-#define BCHP_USB_CTRL_SETUP_IPP_DEFAULT 0x00000000
-
-/* USB_CTRL :: SETUP :: IOC [04:04] */
-#define BCHP_USB_CTRL_SETUP_IOC_MASK 0x00000010
-#define BCHP_USB_CTRL_SETUP_IOC_SHIFT 4
-#define BCHP_USB_CTRL_SETUP_IOC_DEFAULT 0x00000000
-
-/* USB_CTRL :: SETUP :: WABO [03:03] */
-#define BCHP_USB_CTRL_SETUP_WABO_MASK 0x00000008
-#define BCHP_USB_CTRL_SETUP_WABO_SHIFT 3
-#define BCHP_USB_CTRL_SETUP_WABO_DEFAULT 0x00000000
-
-/* USB_CTRL :: SETUP :: FNBO [02:02] */
-#define BCHP_USB_CTRL_SETUP_FNBO_MASK 0x00000004
-#define BCHP_USB_CTRL_SETUP_FNBO_SHIFT 2
-#define BCHP_USB_CTRL_SETUP_FNBO_DEFAULT 0x00000000
-
-/* USB_CTRL :: SETUP :: FNHW [01:01] */
-#define BCHP_USB_CTRL_SETUP_FNHW_MASK 0x00000002
-#define BCHP_USB_CTRL_SETUP_FNHW_SHIFT 1
-#define BCHP_USB_CTRL_SETUP_FNHW_DEFAULT 0x00000000
-
-/* USB_CTRL :: SETUP :: BABO [00:00] */
-#define BCHP_USB_CTRL_SETUP_BABO_MASK 0x00000001
-#define BCHP_USB_CTRL_SETUP_BABO_SHIFT 0
-#define BCHP_USB_CTRL_SETUP_BABO_DEFAULT 0x00000000
-
-/***************************************************************************
- *PLL_CTL - PLL Control Register
- ***************************************************************************/
-/* USB_CTRL :: PLL_CTL :: PLL_IDDQ_PWRDN [31:31] */
-#define BCHP_USB_CTRL_PLL_CTL_PLL_IDDQ_PWRDN_MASK 0x80000000
-#define BCHP_USB_CTRL_PLL_CTL_PLL_IDDQ_PWRDN_SHIFT 31
-#define BCHP_USB_CTRL_PLL_CTL_PLL_IDDQ_PWRDN_DEFAULT 0x00000001
-
-/* USB_CTRL :: PLL_CTL :: PLL_RESETB [30:30] */
-#define BCHP_USB_CTRL_PLL_CTL_PLL_RESETB_MASK 0x40000000
-#define BCHP_USB_CTRL_PLL_CTL_PLL_RESETB_SHIFT 30
-#define BCHP_USB_CTRL_PLL_CTL_PLL_RESETB_DEFAULT 0x00000001
-
-/* USB_CTRL :: PLL_CTL :: PHYPLL_BYP [29:29] */
-#define BCHP_USB_CTRL_PLL_CTL_PHYPLL_BYP_MASK 0x20000000
-#define BCHP_USB_CTRL_PLL_CTL_PHYPLL_BYP_SHIFT 29
-#define BCHP_USB_CTRL_PLL_CTL_PHYPLL_BYP_DEFAULT 0x00000000
-
-/* USB_CTRL :: PLL_CTL :: PLL_PWRDWNB [28:28] */
-#define BCHP_USB_CTRL_PLL_CTL_PLL_PWRDWNB_MASK 0x10000000
-#define BCHP_USB_CTRL_PLL_CTL_PLL_PWRDWNB_SHIFT 28
-#define BCHP_USB_CTRL_PLL_CTL_PLL_PWRDWNB_DEFAULT 0x00000001
-
-/* USB_CTRL :: PLL_CTL :: PLL_SUSPEND_EN [27:27] */
-#define BCHP_USB_CTRL_PLL_CTL_PLL_SUSPEND_EN_MASK 0x08000000
-#define BCHP_USB_CTRL_PLL_CTL_PLL_SUSPEND_EN_SHIFT 27
-#define BCHP_USB_CTRL_PLL_CTL_PLL_SUSPEND_EN_DEFAULT 0x00000000
-
-/* USB_CTRL :: PLL_CTL :: PLL_Ka [26:24] */
-#define BCHP_USB_CTRL_PLL_CTL_PLL_Ka_MASK 0x07000000
-#define BCHP_USB_CTRL_PLL_CTL_PLL_Ka_SHIFT 24
-#define BCHP_USB_CTRL_PLL_CTL_PLL_Ka_DEFAULT 0x00000000
-
-/* USB_CTRL :: PLL_CTL :: PLLCTL_SPARE3 [23:23] */
-#define BCHP_USB_CTRL_PLL_CTL_PLLCTL_SPARE3_MASK 0x00800000
-#define BCHP_USB_CTRL_PLL_CTL_PLLCTL_SPARE3_SHIFT 23
-#define BCHP_USB_CTRL_PLL_CTL_PLLCTL_SPARE3_DEFAULT 0x00000000
-
-/* USB_CTRL :: PLL_CTL :: PLL_Ki [22:20] */
-#define BCHP_USB_CTRL_PLL_CTL_PLL_Ki_MASK 0x00700000
-#define BCHP_USB_CTRL_PLL_CTL_PLL_Ki_SHIFT 20
-#define BCHP_USB_CTRL_PLL_CTL_PLL_Ki_DEFAULT 0x00000004
-
-/* USB_CTRL :: PLL_CTL :: PLL_Kp [19:16] */
-#define BCHP_USB_CTRL_PLL_CTL_PLL_Kp_MASK 0x000f0000
-#define BCHP_USB_CTRL_PLL_CTL_PLL_Kp_SHIFT 16
-#define BCHP_USB_CTRL_PLL_CTL_PLL_Kp_DEFAULT 0x0000000a
-
-/* USB_CTRL :: PLL_CTL :: PLLCTL_SPARE2 [15:15] */
-#define BCHP_USB_CTRL_PLL_CTL_PLLCTL_SPARE2_MASK 0x00008000
-#define BCHP_USB_CTRL_PLL_CTL_PLLCTL_SPARE2_SHIFT 15
-#define BCHP_USB_CTRL_PLL_CTL_PLLCTL_SPARE2_DEFAULT 0x00000000
-
-/* USB_CTRL :: PLL_CTL :: PLL_pdiv [14:12] */
-#define BCHP_USB_CTRL_PLL_CTL_PLL_pdiv_MASK 0x00007000
-#define BCHP_USB_CTRL_PLL_CTL_PLL_pdiv_SHIFT 12
-#define BCHP_USB_CTRL_PLL_CTL_PLL_pdiv_DEFAULT 0x00000001
-
-/* USB_CTRL :: PLL_CTL :: PLLCTL_SPARE1 [11:10] */
-#define BCHP_USB_CTRL_PLL_CTL_PLLCTL_SPARE1_MASK 0x00000c00
-#define BCHP_USB_CTRL_PLL_CTL_PLLCTL_SPARE1_SHIFT 10
-#define BCHP_USB_CTRL_PLL_CTL_PLLCTL_SPARE1_DEFAULT 0x00000000
-
-/* USB_CTRL :: PLL_CTL :: PLL_ndiv [09:00] */
-#define BCHP_USB_CTRL_PLL_CTL_PLL_ndiv_MASK 0x000003ff
-#define BCHP_USB_CTRL_PLL_CTL_PLL_ndiv_SHIFT 0
-#define BCHP_USB_CTRL_PLL_CTL_PLL_ndiv_DEFAULT 0x00000020
-
-/***************************************************************************
- *FLADJ_VALUE - Frame Adjust Value
- ***************************************************************************/
-/* USB_CTRL :: FLADJ_VALUE :: FLADJ_VAL [31:00] */
-#define BCHP_USB_CTRL_FLADJ_VALUE_FLADJ_VAL_MASK 0xffffffff
-#define BCHP_USB_CTRL_FLADJ_VALUE_FLADJ_VAL_SHIFT 0
-#define BCHP_USB_CTRL_FLADJ_VALUE_FLADJ_VAL_DEFAULT 0x000c0020
-
-/***************************************************************************
- *EBRIDGE - Control Register for EHCI Bridge
- ***************************************************************************/
-/* USB_CTRL :: EBRIDGE :: EBR_SOFT_RESET [31:31] */
-#define BCHP_USB_CTRL_EBRIDGE_EBR_SOFT_RESET_MASK 0x80000000
-#define BCHP_USB_CTRL_EBRIDGE_EBR_SOFT_RESET_SHIFT 31
-#define BCHP_USB_CTRL_EBRIDGE_EBR_SOFT_RESET_DEFAULT 0x00000000
-
-/* USB_CTRL :: EBRIDGE :: ebrff_reset [30:30] */
-#define BCHP_USB_CTRL_EBRIDGE_ebrff_reset_MASK 0x40000000
-#define BCHP_USB_CTRL_EBRIDGE_ebrff_reset_SHIFT 30
-#define BCHP_USB_CTRL_EBRIDGE_ebrff_reset_DEFAULT 0x00000000
-
-/* USB_CTRL :: EBRIDGE :: ebr_wrgwordcnt_sel [29:29] */
-#define BCHP_USB_CTRL_EBRIDGE_ebr_wrgwordcnt_sel_MASK 0x20000000
-#define BCHP_USB_CTRL_EBRIDGE_ebr_wrgwordcnt_sel_SHIFT 29
-#define BCHP_USB_CTRL_EBRIDGE_ebr_wrgwordcnt_sel_DEFAULT 0x00000000
-
-/* USB_CTRL :: EBRIDGE :: ebr_size_sel [28:28] */
-#define BCHP_USB_CTRL_EBRIDGE_ebr_size_sel_MASK 0x10000000
-#define BCHP_USB_CTRL_EBRIDGE_ebr_size_sel_SHIFT 28
-#define BCHP_USB_CTRL_EBRIDGE_ebr_size_sel_DEFAULT 0x00000000
-
-/* USB_CTRL :: EBRIDGE :: EBR_SPARE [27:17] */
-#define BCHP_USB_CTRL_EBRIDGE_EBR_SPARE_MASK 0x0ffe0000
-#define BCHP_USB_CTRL_EBRIDGE_EBR_SPARE_SHIFT 17
-#define BCHP_USB_CTRL_EBRIDGE_EBR_SPARE_DEFAULT 0x00000000
-
-/* USB_CTRL :: EBRIDGE :: EBR_RD_THRESH [16:12] */
-#define BCHP_USB_CTRL_EBRIDGE_EBR_RD_THRESH_MASK 0x0001f000
-#define BCHP_USB_CTRL_EBRIDGE_EBR_RD_THRESH_SHIFT 12
-#define BCHP_USB_CTRL_EBRIDGE_EBR_RD_THRESH_DEFAULT 0x00000002
-
-/* USB_CTRL :: EBRIDGE :: EBR_SCB_SIZE [11:07] */
-#define BCHP_USB_CTRL_EBRIDGE_EBR_SCB_SIZE_MASK 0x00000f80
-#define BCHP_USB_CTRL_EBRIDGE_EBR_SCB_SIZE_SHIFT 7
-#define BCHP_USB_CTRL_EBRIDGE_EBR_SCB_SIZE_DEFAULT 0x00000008
-
-/* USB_CTRL :: EBRIDGE :: EBR_MISC [06:01] */
-#define BCHP_USB_CTRL_EBRIDGE_EBR_MISC_MASK 0x0000007e
-#define BCHP_USB_CTRL_EBRIDGE_EBR_MISC_SHIFT 1
-#define BCHP_USB_CTRL_EBRIDGE_EBR_MISC_DEFAULT 0x00000000
-
-/* USB_CTRL :: EBRIDGE :: EBR_SEQ_EN [00:00] */
-#define BCHP_USB_CTRL_EBRIDGE_EBR_SEQ_EN_MASK 0x00000001
-#define BCHP_USB_CTRL_EBRIDGE_EBR_SEQ_EN_SHIFT 0
-#define BCHP_USB_CTRL_EBRIDGE_EBR_SEQ_EN_DEFAULT 0x00000000
-
-/***************************************************************************
- *OBRIDGE - Control Register for OHCI Bridge
- ***************************************************************************/
-/* USB_CTRL :: OBRIDGE :: OBR_SOFT_RESET [31:31] */
-#define BCHP_USB_CTRL_OBRIDGE_OBR_SOFT_RESET_MASK 0x80000000
-#define BCHP_USB_CTRL_OBRIDGE_OBR_SOFT_RESET_SHIFT 31
-#define BCHP_USB_CTRL_OBRIDGE_OBR_SOFT_RESET_DEFAULT 0x00000000
-
-/* USB_CTRL :: OBRIDGE :: obrff_reset [30:30] */
-#define BCHP_USB_CTRL_OBRIDGE_obrff_reset_MASK 0x40000000
-#define BCHP_USB_CTRL_OBRIDGE_obrff_reset_SHIFT 30
-#define BCHP_USB_CTRL_OBRIDGE_obrff_reset_DEFAULT 0x00000000
-
-/* USB_CTRL :: OBRIDGE :: obr_wrgwordcnt_sel [29:29] */
-#define BCHP_USB_CTRL_OBRIDGE_obr_wrgwordcnt_sel_MASK 0x20000000
-#define BCHP_USB_CTRL_OBRIDGE_obr_wrgwordcnt_sel_SHIFT 29
-#define BCHP_USB_CTRL_OBRIDGE_obr_wrgwordcnt_sel_DEFAULT 0x00000000
-
-/* USB_CTRL :: OBRIDGE :: obr_size_sel [28:28] */
-#define BCHP_USB_CTRL_OBRIDGE_obr_size_sel_MASK 0x10000000
-#define BCHP_USB_CTRL_OBRIDGE_obr_size_sel_SHIFT 28
-#define BCHP_USB_CTRL_OBRIDGE_obr_size_sel_DEFAULT 0x00000000
-
-/* USB_CTRL :: OBRIDGE :: OBR_SPARE [27:17] */
-#define BCHP_USB_CTRL_OBRIDGE_OBR_SPARE_MASK 0x0ffe0000
-#define BCHP_USB_CTRL_OBRIDGE_OBR_SPARE_SHIFT 17
-#define BCHP_USB_CTRL_OBRIDGE_OBR_SPARE_DEFAULT 0x00000000
-
-/* USB_CTRL :: OBRIDGE :: OBR_RD_THRESH [16:12] */
-#define BCHP_USB_CTRL_OBRIDGE_OBR_RD_THRESH_MASK 0x0001f000
-#define BCHP_USB_CTRL_OBRIDGE_OBR_RD_THRESH_SHIFT 12
-#define BCHP_USB_CTRL_OBRIDGE_OBR_RD_THRESH_DEFAULT 0x00000002
-
-/* USB_CTRL :: OBRIDGE :: OBR_SCB_SIZE [11:07] */
-#define BCHP_USB_CTRL_OBRIDGE_OBR_SCB_SIZE_MASK 0x00000f80
-#define BCHP_USB_CTRL_OBRIDGE_OBR_SCB_SIZE_SHIFT 7
-#define BCHP_USB_CTRL_OBRIDGE_OBR_SCB_SIZE_DEFAULT 0x00000004
-
-/* USB_CTRL :: OBRIDGE :: OBR_MISC [06:01] */
-#define BCHP_USB_CTRL_OBRIDGE_OBR_MISC_MASK 0x0000007e
-#define BCHP_USB_CTRL_OBRIDGE_OBR_MISC_SHIFT 1
-#define BCHP_USB_CTRL_OBRIDGE_OBR_MISC_DEFAULT 0x00000000
-
-/* USB_CTRL :: OBRIDGE :: OBR_SEQ_EN [00:00] */
-#define BCHP_USB_CTRL_OBRIDGE_OBR_SEQ_EN_MASK 0x00000001
-#define BCHP_USB_CTRL_OBRIDGE_OBR_SEQ_EN_SHIFT 0
-#define BCHP_USB_CTRL_OBRIDGE_OBR_SEQ_EN_DEFAULT 0x00000000
-
-/***************************************************************************
- *MDIO - MDIO Interface Programming Register
- ***************************************************************************/
-/* USB_CTRL :: MDIO :: MDIO_PHY_SEL [31:31] */
-#define BCHP_USB_CTRL_MDIO_MDIO_PHY_SEL_MASK 0x80000000
-#define BCHP_USB_CTRL_MDIO_MDIO_PHY_SEL_SHIFT 31
-#define BCHP_USB_CTRL_MDIO_MDIO_PHY_SEL_DEFAULT 0x00000000
-
-/* USB_CTRL :: MDIO :: MDIO_SPARE [30:27] */
-#define BCHP_USB_CTRL_MDIO_MDIO_SPARE_MASK 0x78000000
-#define BCHP_USB_CTRL_MDIO_MDIO_SPARE_SHIFT 27
-#define BCHP_USB_CTRL_MDIO_MDIO_SPARE_DEFAULT 0x00000000
-
-/* USB_CTRL :: MDIO :: MDIO_RESET [26:26] */
-#define BCHP_USB_CTRL_MDIO_MDIO_RESET_MASK 0x04000000
-#define BCHP_USB_CTRL_MDIO_MDIO_RESET_SHIFT 26
-#define BCHP_USB_CTRL_MDIO_MDIO_RESET_DEFAULT 0x00000000
-
-/* USB_CTRL :: MDIO :: WR_START [25:25] */
-#define BCHP_USB_CTRL_MDIO_WR_START_MASK 0x02000000
-#define BCHP_USB_CTRL_MDIO_WR_START_SHIFT 25
-#define BCHP_USB_CTRL_MDIO_WR_START_DEFAULT 0x00000000
-
-/* USB_CTRL :: MDIO :: RD_START [24:24] */
-#define BCHP_USB_CTRL_MDIO_RD_START_MASK 0x01000000
-#define BCHP_USB_CTRL_MDIO_RD_START_SHIFT 24
-#define BCHP_USB_CTRL_MDIO_RD_START_DEFAULT 0x00000000
-
-/* USB_CTRL :: MDIO :: MDIO_ADDR [23:16] */
-#define BCHP_USB_CTRL_MDIO_MDIO_ADDR_MASK 0x00ff0000
-#define BCHP_USB_CTRL_MDIO_MDIO_ADDR_SHIFT 16
-#define BCHP_USB_CTRL_MDIO_MDIO_ADDR_DEFAULT 0x00000000
-
-/* USB_CTRL :: MDIO :: MDIO_DATA [15:00] */
-#define BCHP_USB_CTRL_MDIO_MDIO_DATA_MASK 0x0000ffff
-#define BCHP_USB_CTRL_MDIO_MDIO_DATA_SHIFT 0
-#define BCHP_USB_CTRL_MDIO_MDIO_DATA_DEFAULT 0x00000000
-
-/***************************************************************************
- *MDIO2 - MDIO Interface Read Register
- ***************************************************************************/
-/* USB_CTRL :: MDIO2 :: SYNOPSIS_CORE_ID [31:16] */
-#define BCHP_USB_CTRL_MDIO2_SYNOPSIS_CORE_ID_MASK 0xffff0000
-#define BCHP_USB_CTRL_MDIO2_SYNOPSIS_CORE_ID_SHIFT 16
-#define BCHP_USB_CTRL_MDIO2_SYNOPSIS_CORE_ID_DEFAULT 0x0000296a
-
-/* USB_CTRL :: MDIO2 :: MDIO_RD_DATA [15:00] */
-#define BCHP_USB_CTRL_MDIO2_MDIO_RD_DATA_MASK 0x0000ffff
-#define BCHP_USB_CTRL_MDIO2_MDIO_RD_DATA_SHIFT 0
-#define BCHP_USB_CTRL_MDIO2_MDIO_RD_DATA_DEFAULT 0x00000000
-
-/***************************************************************************
- *TEST_PORT_CTL - Test Port Control Register
- ***************************************************************************/
-/* USB_CTRL :: TEST_PORT_CTL :: TP_EN [31:31] */
-#define BCHP_USB_CTRL_TEST_PORT_CTL_TP_EN_MASK 0x80000000
-#define BCHP_USB_CTRL_TEST_PORT_CTL_TP_EN_SHIFT 31
-#define BCHP_USB_CTRL_TEST_PORT_CTL_TP_EN_DEFAULT 0x00000000
-
-/* USB_CTRL :: TEST_PORT_CTL :: TPCTL_SPARE [30:28] */
-#define BCHP_USB_CTRL_TEST_PORT_CTL_TPCTL_SPARE_MASK 0x70000000
-#define BCHP_USB_CTRL_TEST_PORT_CTL_TPCTL_SPARE_SHIFT 28
-#define BCHP_USB_CTRL_TEST_PORT_CTL_TPCTL_SPARE_DEFAULT 0x00000000
-
-/* USB_CTRL :: TEST_PORT_CTL :: scb2_wr_data_sel [27:27] */
-#define BCHP_USB_CTRL_TEST_PORT_CTL_scb2_wr_data_sel_MASK 0x08000000
-#define BCHP_USB_CTRL_TEST_PORT_CTL_scb2_wr_data_sel_SHIFT 27
-#define BCHP_USB_CTRL_TEST_PORT_CTL_scb2_wr_data_sel_DEFAULT 0x00000000
-
-/* USB_CTRL :: TEST_PORT_CTL :: scb1_wr_data_sel [26:26] */
-#define BCHP_USB_CTRL_TEST_PORT_CTL_scb1_wr_data_sel_MASK 0x04000000
-#define BCHP_USB_CTRL_TEST_PORT_CTL_scb1_wr_data_sel_SHIFT 26
-#define BCHP_USB_CTRL_TEST_PORT_CTL_scb1_wr_data_sel_DEFAULT 0x00000000
-
-/* USB_CTRL :: TEST_PORT_CTL :: scb0_wr_data_sel [25:25] */
-#define BCHP_USB_CTRL_TEST_PORT_CTL_scb0_wr_data_sel_MASK 0x02000000
-#define BCHP_USB_CTRL_TEST_PORT_CTL_scb0_wr_data_sel_SHIFT 25
-#define BCHP_USB_CTRL_TEST_PORT_CTL_scb0_wr_data_sel_DEFAULT 0x00000000
-
-/* USB_CTRL :: TEST_PORT_CTL :: testclk_sel [24:23] */
-#define BCHP_USB_CTRL_TEST_PORT_CTL_testclk_sel_MASK 0x01800000
-#define BCHP_USB_CTRL_TEST_PORT_CTL_testclk_sel_SHIFT 23
-#define BCHP_USB_CTRL_TEST_PORT_CTL_testclk_sel_DEFAULT 0x00000000
-
-/* USB_CTRL :: TEST_PORT_CTL :: pwrflt_testsel [22:21] */
-#define BCHP_USB_CTRL_TEST_PORT_CTL_pwrflt_testsel_MASK 0x00600000
-#define BCHP_USB_CTRL_TEST_PORT_CTL_pwrflt_testsel_SHIFT 21
-#define BCHP_USB_CTRL_TEST_PORT_CTL_pwrflt_testsel_DEFAULT 0x00000000
-
-/* USB_CTRL :: TEST_PORT_CTL :: pwrflt1_oe [20:20] */
-#define BCHP_USB_CTRL_TEST_PORT_CTL_pwrflt1_oe_MASK 0x00100000
-#define BCHP_USB_CTRL_TEST_PORT_CTL_pwrflt1_oe_SHIFT 20
-#define BCHP_USB_CTRL_TEST_PORT_CTL_pwrflt1_oe_DEFAULT 0x00000000
-
-/* USB_CTRL :: TEST_PORT_CTL :: pwrflt0_oe [19:19] */
-#define BCHP_USB_CTRL_TEST_PORT_CTL_pwrflt0_oe_MASK 0x00080000
-#define BCHP_USB_CTRL_TEST_PORT_CTL_pwrflt0_oe_SHIFT 19
-#define BCHP_USB_CTRL_TEST_PORT_CTL_pwrflt0_oe_DEFAULT 0x00000000
-
-/* USB_CTRL :: TEST_PORT_CTL :: pwron1_testsel [18:18] */
-#define BCHP_USB_CTRL_TEST_PORT_CTL_pwron1_testsel_MASK 0x00040000
-#define BCHP_USB_CTRL_TEST_PORT_CTL_pwron1_testsel_SHIFT 18
-#define BCHP_USB_CTRL_TEST_PORT_CTL_pwron1_testsel_DEFAULT 0x00000000
-
-/* USB_CTRL :: TEST_PORT_CTL :: pwron0_testsel [17:17] */
-#define BCHP_USB_CTRL_TEST_PORT_CTL_pwron0_testsel_MASK 0x00020000
-#define BCHP_USB_CTRL_TEST_PORT_CTL_pwron0_testsel_SHIFT 17
-#define BCHP_USB_CTRL_TEST_PORT_CTL_pwron0_testsel_DEFAULT 0x00000000
-
-/* USB_CTRL :: TEST_PORT_CTL :: tpin_sel [16:16] */
-#define BCHP_USB_CTRL_TEST_PORT_CTL_tpin_sel_MASK 0x00010000
-#define BCHP_USB_CTRL_TEST_PORT_CTL_tpin_sel_SHIFT 16
-#define BCHP_USB_CTRL_TEST_PORT_CTL_tpin_sel_DEFAULT 0x00000000
-
-/* USB_CTRL :: TEST_PORT_CTL :: UTMI_TP_SEL [15:08] */
-#define BCHP_USB_CTRL_TEST_PORT_CTL_UTMI_TP_SEL_MASK 0x0000ff00
-#define BCHP_USB_CTRL_TEST_PORT_CTL_UTMI_TP_SEL_SHIFT 8
-#define BCHP_USB_CTRL_TEST_PORT_CTL_UTMI_TP_SEL_DEFAULT 0x00000000
-
-/* USB_CTRL :: TEST_PORT_CTL :: TPOUT_SEL [07:00] */
-#define BCHP_USB_CTRL_TEST_PORT_CTL_TPOUT_SEL_MASK 0x000000ff
-#define BCHP_USB_CTRL_TEST_PORT_CTL_TPOUT_SEL_SHIFT 0
-#define BCHP_USB_CTRL_TEST_PORT_CTL_TPOUT_SEL_DEFAULT 0x00000000
-
-/***************************************************************************
- *USB_SIMCTL - Simulation Register
- ***************************************************************************/
-/* USB_CTRL :: USB_SIMCTL :: sim_mode_en [31:31] */
-#define BCHP_USB_CTRL_USB_SIMCTL_sim_mode_en_MASK 0x80000000
-#define BCHP_USB_CTRL_USB_SIMCTL_sim_mode_en_SHIFT 31
-#define BCHP_USB_CTRL_USB_SIMCTL_sim_mode_en_DEFAULT 0x00000000
-
-/* USB_CTRL :: USB_SIMCTL :: scale_down_en [30:30] */
-#define BCHP_USB_CTRL_USB_SIMCTL_scale_down_en_MASK 0x40000000
-#define BCHP_USB_CTRL_USB_SIMCTL_scale_down_en_SHIFT 30
-#define BCHP_USB_CTRL_USB_SIMCTL_scale_down_en_DEFAULT 0x00000000
-
-/* USB_CTRL :: USB_SIMCTL :: otg_scale_down_en [29:28] */
-#define BCHP_USB_CTRL_USB_SIMCTL_otg_scale_down_en_MASK 0x30000000
-#define BCHP_USB_CTRL_USB_SIMCTL_otg_scale_down_en_SHIFT 28
-#define BCHP_USB_CTRL_USB_SIMCTL_otg_scale_down_en_DEFAULT 0x00000000
-
-/* USB_CTRL :: USB_SIMCTL :: intr_test [27:27] */
-#define BCHP_USB_CTRL_USB_SIMCTL_intr_test_MASK 0x08000000
-#define BCHP_USB_CTRL_USB_SIMCTL_intr_test_SHIFT 27
-#define BCHP_USB_CTRL_USB_SIMCTL_intr_test_DEFAULT 0x00000000
-
-/* USB_CTRL :: USB_SIMCTL :: AUTOPPD_ON_OVERCUR_EN [26:26] */
-#define BCHP_USB_CTRL_USB_SIMCTL_AUTOPPD_ON_OVERCUR_EN_MASK 0x04000000
-#define BCHP_USB_CTRL_USB_SIMCTL_AUTOPPD_ON_OVERCUR_EN_SHIFT 26
-#define BCHP_USB_CTRL_USB_SIMCTL_AUTOPPD_ON_OVERCUR_EN_DEFAULT 0x00000000
-
-/* USB_CTRL :: USB_SIMCTL :: SIMCTL_SPARE [25:07] */
-#define BCHP_USB_CTRL_USB_SIMCTL_SIMCTL_SPARE_MASK 0x03ffff80
-#define BCHP_USB_CTRL_USB_SIMCTL_SIMCTL_SPARE_SHIFT 7
-#define BCHP_USB_CTRL_USB_SIMCTL_SIMCTL_SPARE_DEFAULT 0x00000000
-
-/* USB_CTRL :: USB_SIMCTL :: USB_CAP_DIS [06:06] */
-#define BCHP_USB_CTRL_USB_SIMCTL_USB_CAP_DIS_MASK 0x00000040
-#define BCHP_USB_CTRL_USB_SIMCTL_USB_CAP_DIS_SHIFT 6
-#define BCHP_USB_CTRL_USB_SIMCTL_USB_CAP_DIS_DEFAULT 0x00000000
-
-/* USB_CTRL :: USB_SIMCTL :: SCB_REQ_LGCY [05:05] */
-#define BCHP_USB_CTRL_USB_SIMCTL_SCB_REQ_LGCY_MASK 0x00000020
-#define BCHP_USB_CTRL_USB_SIMCTL_SCB_REQ_LGCY_SHIFT 5
-#define BCHP_USB_CTRL_USB_SIMCTL_SCB_REQ_LGCY_DEFAULT 0x00000000
-
-/* USB_CTRL :: USB_SIMCTL :: rel_270a_comp [04:04] */
-#define BCHP_USB_CTRL_USB_SIMCTL_rel_270a_comp_MASK 0x00000010
-#define BCHP_USB_CTRL_USB_SIMCTL_rel_270a_comp_SHIFT 4
-#define BCHP_USB_CTRL_USB_SIMCTL_rel_270a_comp_DEFAULT 0x00000001
-
-/* USB_CTRL :: USB_SIMCTL :: SIMCTL_SPARE1 [03:00] */
-#define BCHP_USB_CTRL_USB_SIMCTL_SIMCTL_SPARE1_MASK 0x0000000f
-#define BCHP_USB_CTRL_USB_SIMCTL_SIMCTL_SPARE1_SHIFT 0
-#define BCHP_USB_CTRL_USB_SIMCTL_SIMCTL_SPARE1_DEFAULT 0x00000000
-
-/***************************************************************************
- *USB_TESTCTL - Throutput Test Control
- ***************************************************************************/
-/* USB_CTRL :: USB_TESTCTL :: TESTCTL_SPARE2 [31:23] */
-#define BCHP_USB_CTRL_USB_TESTCTL_TESTCTL_SPARE2_MASK 0xff800000
-#define BCHP_USB_CTRL_USB_TESTCTL_TESTCTL_SPARE2_SHIFT 23
-#define BCHP_USB_CTRL_USB_TESTCTL_TESTCTL_SPARE2_DEFAULT 0x00000000
-
-/* USB_CTRL :: USB_TESTCTL :: CONTROLLER_SEL [22:21] */
-#define BCHP_USB_CTRL_USB_TESTCTL_CONTROLLER_SEL_MASK 0x00600000
-#define BCHP_USB_CTRL_USB_TESTCTL_CONTROLLER_SEL_SHIFT 21
-#define BCHP_USB_CTRL_USB_TESTCTL_CONTROLLER_SEL_DEFAULT 0x00000000
-
-/* USB_CTRL :: USB_TESTCTL :: DCNT_EN [20:20] */
-#define BCHP_USB_CTRL_USB_TESTCTL_DCNT_EN_MASK 0x00100000
-#define BCHP_USB_CTRL_USB_TESTCTL_DCNT_EN_SHIFT 20
-#define BCHP_USB_CTRL_USB_TESTCTL_DCNT_EN_DEFAULT 0x00000000
-
-/* USB_CTRL :: USB_TESTCTL :: SPEED_SEL [19:19] */
-#define BCHP_USB_CTRL_USB_TESTCTL_SPEED_SEL_MASK 0x00080000
-#define BCHP_USB_CTRL_USB_TESTCTL_SPEED_SEL_SHIFT 19
-#define BCHP_USB_CTRL_USB_TESTCTL_SPEED_SEL_DEFAULT 0x00000000
-
-/* USB_CTRL :: USB_TESTCTL :: DCNT_SEL [18:16] */
-#define BCHP_USB_CTRL_USB_TESTCTL_DCNT_SEL_MASK 0x00070000
-#define BCHP_USB_CTRL_USB_TESTCTL_DCNT_SEL_SHIFT 16
-#define BCHP_USB_CTRL_USB_TESTCTL_DCNT_SEL_DEFAULT 0x00000000
-
-/* USB_CTRL :: USB_TESTCTL :: TESTCTL_SPARE1 [15:10] */
-#define BCHP_USB_CTRL_USB_TESTCTL_TESTCTL_SPARE1_MASK 0x0000fc00
-#define BCHP_USB_CTRL_USB_TESTCTL_TESTCTL_SPARE1_SHIFT 10
-#define BCHP_USB_CTRL_USB_TESTCTL_TESTCTL_SPARE1_DEFAULT 0x00000000
-
-/* USB_CTRL :: USB_TESTCTL :: MSEC_PRESCALER [09:00] */
-#define BCHP_USB_CTRL_USB_TESTCTL_MSEC_PRESCALER_MASK 0x000003ff
-#define BCHP_USB_CTRL_USB_TESTCTL_MSEC_PRESCALER_SHIFT 0
-#define BCHP_USB_CTRL_USB_TESTCTL_MSEC_PRESCALER_DEFAULT 0x00000000
-
-/***************************************************************************
- *USB_TESTMON - Throughput Test Monitor
- ***************************************************************************/
-/* USB_CTRL :: USB_TESTMON :: PLL_SS_LOCK [31:31] */
-#define BCHP_USB_CTRL_USB_TESTMON_PLL_SS_LOCK_MASK 0x80000000
-#define BCHP_USB_CTRL_USB_TESTMON_PLL_SS_LOCK_SHIFT 31
-#define BCHP_USB_CTRL_USB_TESTMON_PLL_SS_LOCK_DEFAULT 0x00000000
-
-/* USB_CTRL :: USB_TESTMON :: PLL_HS_LOCK [30:30] */
-#define BCHP_USB_CTRL_USB_TESTMON_PLL_HS_LOCK_MASK 0x40000000
-#define BCHP_USB_CTRL_USB_TESTMON_PLL_HS_LOCK_SHIFT 30
-#define BCHP_USB_CTRL_USB_TESTMON_PLL_HS_LOCK_DEFAULT 0x00000000
-
-/* USB_CTRL :: USB_TESTMON :: TESTMON_SPARE [29:00] */
-#define BCHP_USB_CTRL_USB_TESTMON_TESTMON_SPARE_MASK 0x3fffffff
-#define BCHP_USB_CTRL_USB_TESTMON_TESTMON_SPARE_SHIFT 0
-#define BCHP_USB_CTRL_USB_TESTMON_TESTMON_SPARE_DEFAULT 0x00000000
-
-/***************************************************************************
- *UTMI_CTL_1 - UTMI Control Register
- ***************************************************************************/
-/* USB_CTRL :: UTMI_CTL_1 :: USB11_TX_OEB_P1 [31:31] */
-#define BCHP_USB_CTRL_UTMI_CTL_1_USB11_TX_OEB_P1_MASK 0x80000000
-#define BCHP_USB_CTRL_UTMI_CTL_1_USB11_TX_OEB_P1_SHIFT 31
-#define BCHP_USB_CTRL_UTMI_CTL_1_USB11_TX_OEB_P1_DEFAULT 0x00000000
-
-/* USB_CTRL :: UTMI_CTL_1 :: SYNC_DET_LENG_P1 [30:28] */
-#define BCHP_USB_CTRL_UTMI_CTL_1_SYNC_DET_LENG_P1_MASK 0x70000000
-#define BCHP_USB_CTRL_UTMI_CTL_1_SYNC_DET_LENG_P1_SHIFT 28
-#define BCHP_USB_CTRL_UTMI_CTL_1_SYNC_DET_LENG_P1_DEFAULT 0x00000000
-
-/* USB_CTRL :: UTMI_CTL_1 :: DFE_LPBACK_P1 [27:27] */
-#define BCHP_USB_CTRL_UTMI_CTL_1_DFE_LPBACK_P1_MASK 0x08000000
-#define BCHP_USB_CTRL_UTMI_CTL_1_DFE_LPBACK_P1_SHIFT 27
-#define BCHP_USB_CTRL_UTMI_CTL_1_DFE_LPBACK_P1_DEFAULT 0x00000001
-
-/* USB_CTRL :: UTMI_CTL_1 :: UTMICTL1_SPARE3 [26:25] */
-#define BCHP_USB_CTRL_UTMI_CTL_1_UTMICTL1_SPARE3_MASK 0x06000000
-#define BCHP_USB_CTRL_UTMI_CTL_1_UTMICTL1_SPARE3_SHIFT 25
-#define BCHP_USB_CTRL_UTMI_CTL_1_UTMICTL1_SPARE3_DEFAULT 0x00000000
-
-/* USB_CTRL :: UTMI_CTL_1 :: POWER_UP_FSM_SPEED_P1 [24:24] */
-#define BCHP_USB_CTRL_UTMI_CTL_1_POWER_UP_FSM_SPEED_P1_MASK 0x01000000
-#define BCHP_USB_CTRL_UTMI_CTL_1_POWER_UP_FSM_SPEED_P1_SHIFT 24
-#define BCHP_USB_CTRL_UTMI_CTL_1_POWER_UP_FSM_SPEED_P1_DEFAULT 0x00000001
-
-/* USB_CTRL :: UTMI_CTL_1 :: BC10_DM_PU_P1 [23:23] */
-#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_DM_PU_P1_MASK 0x00800000
-#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_DM_PU_P1_SHIFT 23
-#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_DM_PU_P1_DEFAULT 0x00000000
-
-/* USB_CTRL :: UTMI_CTL_1 :: BC10_DP_PU_P1 [22:22] */
-#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_DP_PU_P1_MASK 0x00400000
-#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_DP_PU_P1_SHIFT 22
-#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_DP_PU_P1_DEFAULT 0x00000000
-
-/* USB_CTRL :: UTMI_CTL_1 :: BC10_DM_PD_P1 [21:21] */
-#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_DM_PD_P1_MASK 0x00200000
-#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_DM_PD_P1_SHIFT 21
-#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_DM_PD_P1_DEFAULT 0x00000000
-
-/* USB_CTRL :: UTMI_CTL_1 :: BC10_DP_PD_P1 [20:20] */
-#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_DP_PD_P1_MASK 0x00100000
-#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_DP_PD_P1_SHIFT 20
-#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_DP_PD_P1_DEFAULT 0x00000000
-
-/* USB_CTRL :: UTMI_CTL_1 :: PHY_MODE_P1 [19:18] */
-#define BCHP_USB_CTRL_UTMI_CTL_1_PHY_MODE_P1_MASK 0x000c0000
-#define BCHP_USB_CTRL_UTMI_CTL_1_PHY_MODE_P1_SHIFT 18
-#define BCHP_USB_CTRL_UTMI_CTL_1_PHY_MODE_P1_DEFAULT 0x00000000
-
-/* USB_CTRL :: UTMI_CTL_1 :: UTMI_SOFT_RESETB_P1 [17:17] */
-#define BCHP_USB_CTRL_UTMI_CTL_1_UTMI_SOFT_RESETB_P1_MASK 0x00020000
-#define BCHP_USB_CTRL_UTMI_CTL_1_UTMI_SOFT_RESETB_P1_SHIFT 17
-#define BCHP_USB_CTRL_UTMI_CTL_1_UTMI_SOFT_RESETB_P1_DEFAULT 0x00000001
-
-/* USB_CTRL :: UTMI_CTL_1 :: AFE_NON_DRIVING_P1 [16:16] */
-#define BCHP_USB_CTRL_UTMI_CTL_1_AFE_NON_DRIVING_P1_MASK 0x00010000
-#define BCHP_USB_CTRL_UTMI_CTL_1_AFE_NON_DRIVING_P1_SHIFT 16
-#define BCHP_USB_CTRL_UTMI_CTL_1_AFE_NON_DRIVING_P1_DEFAULT 0x00000000
-
-/* USB_CTRL :: UTMI_CTL_1 :: USB11_TX_OEB [15:15] */
-#define BCHP_USB_CTRL_UTMI_CTL_1_USB11_TX_OEB_MASK 0x00008000
-#define BCHP_USB_CTRL_UTMI_CTL_1_USB11_TX_OEB_SHIFT 15
-#define BCHP_USB_CTRL_UTMI_CTL_1_USB11_TX_OEB_DEFAULT 0x00000000
-
-/* USB_CTRL :: UTMI_CTL_1 :: SYNC_DET_LENG [14:12] */
-#define BCHP_USB_CTRL_UTMI_CTL_1_SYNC_DET_LENG_MASK 0x00007000
-#define BCHP_USB_CTRL_UTMI_CTL_1_SYNC_DET_LENG_SHIFT 12
-#define BCHP_USB_CTRL_UTMI_CTL_1_SYNC_DET_LENG_DEFAULT 0x00000000
-
-/* USB_CTRL :: UTMI_CTL_1 :: Power_Up_FSM_ENABLE [11:11] */
-#define BCHP_USB_CTRL_UTMI_CTL_1_Power_Up_FSM_ENABLE_MASK 0x00000800
-#define BCHP_USB_CTRL_UTMI_CTL_1_Power_Up_FSM_ENABLE_SHIFT 11
-#define BCHP_USB_CTRL_UTMI_CTL_1_Power_Up_FSM_ENABLE_DEFAULT 0x00000001
-
-/* USB_CTRL :: UTMI_CTL_1 :: UTMICTL1_SPARE1 [10:09] */
-#define BCHP_USB_CTRL_UTMI_CTL_1_UTMICTL1_SPARE1_MASK 0x00000600
-#define BCHP_USB_CTRL_UTMI_CTL_1_UTMICTL1_SPARE1_SHIFT 9
-#define BCHP_USB_CTRL_UTMI_CTL_1_UTMICTL1_SPARE1_DEFAULT 0x00000000
-
-/* USB_CTRL :: UTMI_CTL_1 :: POWER_UP_FSM_SPEED [08:08] */
-#define BCHP_USB_CTRL_UTMI_CTL_1_POWER_UP_FSM_SPEED_MASK 0x00000100
-#define BCHP_USB_CTRL_UTMI_CTL_1_POWER_UP_FSM_SPEED_SHIFT 8
-#define BCHP_USB_CTRL_UTMI_CTL_1_POWER_UP_FSM_SPEED_DEFAULT 0x00000001
-
-/* USB_CTRL :: UTMI_CTL_1 :: BC10_DM_PU [07:07] */
-#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_DM_PU_MASK 0x00000080
-#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_DM_PU_SHIFT 7
-#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_DM_PU_DEFAULT 0x00000000
-
-/* USB_CTRL :: UTMI_CTL_1 :: BC10_DP_PU [06:06] */
-#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_DP_PU_MASK 0x00000040
-#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_DP_PU_SHIFT 6
-#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_DP_PU_DEFAULT 0x00000000
-
-/* USB_CTRL :: UTMI_CTL_1 :: BC10_DM_PD [05:05] */
-#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_DM_PD_MASK 0x00000020
-#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_DM_PD_SHIFT 5
-#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_DM_PD_DEFAULT 0x00000000
-
-/* USB_CTRL :: UTMI_CTL_1 :: BC10_DP_PD [04:04] */
-#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_DP_PD_MASK 0x00000010
-#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_DP_PD_SHIFT 4
-#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_DP_PD_DEFAULT 0x00000000
-
-/* USB_CTRL :: UTMI_CTL_1 :: PHY_MODE [03:02] */
-#define BCHP_USB_CTRL_UTMI_CTL_1_PHY_MODE_MASK 0x0000000c
-#define BCHP_USB_CTRL_UTMI_CTL_1_PHY_MODE_SHIFT 2
-#define BCHP_USB_CTRL_UTMI_CTL_1_PHY_MODE_DEFAULT 0x00000000
-
-/* USB_CTRL :: UTMI_CTL_1 :: UTMI_SOFT_RESETB [01:01] */
-#define BCHP_USB_CTRL_UTMI_CTL_1_UTMI_SOFT_RESETB_MASK 0x00000002
-#define BCHP_USB_CTRL_UTMI_CTL_1_UTMI_SOFT_RESETB_SHIFT 1
-#define BCHP_USB_CTRL_UTMI_CTL_1_UTMI_SOFT_RESETB_DEFAULT 0x00000001
-
-/* USB_CTRL :: UTMI_CTL_1 :: AFE_NON_DRIVING [00:00] */
-#define BCHP_USB_CTRL_UTMI_CTL_1_AFE_NON_DRIVING_MASK 0x00000001
-#define BCHP_USB_CTRL_UTMI_CTL_1_AFE_NON_DRIVING_SHIFT 0
-#define BCHP_USB_CTRL_UTMI_CTL_1_AFE_NON_DRIVING_DEFAULT 0x00000000
-
-/***************************************************************************
- *UTMI_CTL_2 - UTMI Control 2 Register
- ***************************************************************************/
-/* USB_CTRL :: UTMI_CTL_2 :: UTMICTL2_SPARE [31:00] */
-#define BCHP_USB_CTRL_UTMI_CTL_2_UTMICTL2_SPARE_MASK 0xffffffff
-#define BCHP_USB_CTRL_UTMI_CTL_2_UTMICTL2_SPARE_SHIFT 0
-#define BCHP_USB_CTRL_UTMI_CTL_2_UTMICTL2_SPARE_DEFAULT 0x00000000
-
-/***************************************************************************
- *USB_PM - Power Management Register
- ***************************************************************************/
-/* USB_CTRL :: USB_PM :: USB_PM_SPARE [31:05] */
-#define BCHP_USB_CTRL_USB_PM_USB_PM_SPARE_MASK 0xffffffe0
-#define BCHP_USB_CTRL_USB_PM_USB_PM_SPARE_SHIFT 5
-#define BCHP_USB_CTRL_USB_PM_USB_PM_SPARE_DEFAULT 0x00000000
-
-/* USB_CTRL :: USB_PM :: xhc_pme_en [04:04] */
-#define BCHP_USB_CTRL_USB_PM_xhc_pme_en_MASK 0x00000010
-#define BCHP_USB_CTRL_USB_PM_xhc_pme_en_SHIFT 4
-#define BCHP_USB_CTRL_USB_PM_xhc_pme_en_DEFAULT 0x00000000
-
-/* USB_CTRL :: USB_PM :: S2_discon_intr_en [03:03] */
-#define BCHP_USB_CTRL_USB_PM_S2_discon_intr_en_MASK 0x00000008
-#define BCHP_USB_CTRL_USB_PM_S2_discon_intr_en_SHIFT 3
-#define BCHP_USB_CTRL_USB_PM_S2_discon_intr_en_DEFAULT 0x00000000
-
-/* USB_CTRL :: USB_PM :: S0_discon_intr_en [02:02] */
-#define BCHP_USB_CTRL_USB_PM_S0_discon_intr_en_MASK 0x00000004
-#define BCHP_USB_CTRL_USB_PM_S0_discon_intr_en_SHIFT 2
-#define BCHP_USB_CTRL_USB_PM_S0_discon_intr_en_DEFAULT 0x00000000
-
-/* USB_CTRL :: USB_PM :: con_intr_en [01:01] */
-#define BCHP_USB_CTRL_USB_PM_con_intr_en_MASK 0x00000002
-#define BCHP_USB_CTRL_USB_PM_con_intr_en_SHIFT 1
-#define BCHP_USB_CTRL_USB_PM_con_intr_en_DEFAULT 0x00000000
-
-/* USB_CTRL :: USB_PM :: rmtwkup_en [00:00] */
-#define BCHP_USB_CTRL_USB_PM_rmtwkup_en_MASK 0x00000001
-#define BCHP_USB_CTRL_USB_PM_rmtwkup_en_SHIFT 0
-#define BCHP_USB_CTRL_USB_PM_rmtwkup_en_DEFAULT 0x00000000
-
-/***************************************************************************
- *OHCI_ADDR_EXT - OHCI ADDRESS Extension
- ***************************************************************************/
-/* USB_CTRL :: OHCI_ADDR_EXT :: OHCI_ADDR_SPARE [31:08] */
-#define BCHP_USB_CTRL_OHCI_ADDR_EXT_OHCI_ADDR_SPARE_MASK 0xffffff00
-#define BCHP_USB_CTRL_OHCI_ADDR_EXT_OHCI_ADDR_SPARE_SHIFT 8
-#define BCHP_USB_CTRL_OHCI_ADDR_EXT_OHCI_ADDR_SPARE_DEFAULT 0x00000000
-
-/* USB_CTRL :: OHCI_ADDR_EXT :: OHCI_ADDR_EXT [07:00] */
-#define BCHP_USB_CTRL_OHCI_ADDR_EXT_OHCI_ADDR_EXT_MASK 0x000000ff
-#define BCHP_USB_CTRL_OHCI_ADDR_EXT_OHCI_ADDR_EXT_SHIFT 0
-#define BCHP_USB_CTRL_OHCI_ADDR_EXT_OHCI_ADDR_EXT_DEFAULT 0x00000000
-
-/***************************************************************************
- *SPARE1 - Spare1 Register for future use
- ***************************************************************************/
-/* USB_CTRL :: SPARE1 :: SPARE1_BITS [31:00] */
-#define BCHP_USB_CTRL_SPARE1_SPARE1_BITS_MASK 0xffffffff
-#define BCHP_USB_CTRL_SPARE1_SPARE1_BITS_SHIFT 0
-#define BCHP_USB_CTRL_SPARE1_SPARE1_BITS_DEFAULT 0x00000000
-
-/***************************************************************************
- *PLL_LDO_CTL - 28NM USBPHY LDO Control
- ***************************************************************************/
-/* USB_CTRL :: PLL_LDO_CTL :: AFE_PLL_LDO_CNTL [31:16] */
-#define BCHP_USB_CTRL_PLL_LDO_CTL_AFE_PLL_LDO_CNTL_MASK 0xffff0000
-#define BCHP_USB_CTRL_PLL_LDO_CTL_AFE_PLL_LDO_CNTL_SHIFT 16
-#define BCHP_USB_CTRL_PLL_LDO_CTL_AFE_PLL_LDO_CNTL_DEFAULT 0x00000000
-
-/* USB_CTRL :: PLL_LDO_CTL :: DFE_LDO_CNTL [15:12] */
-#define BCHP_USB_CTRL_PLL_LDO_CTL_DFE_LDO_CNTL_MASK 0x0000f000
-#define BCHP_USB_CTRL_PLL_LDO_CTL_DFE_LDO_CNTL_SHIFT 12
-#define BCHP_USB_CTRL_PLL_LDO_CTL_DFE_LDO_CNTL_DEFAULT 0x00000000
-
-/* USB_CTRL :: PLL_LDO_CTL :: AFE_LDO_CNTL [11:08] */
-#define BCHP_USB_CTRL_PLL_LDO_CTL_AFE_LDO_CNTL_MASK 0x00000f00
-#define BCHP_USB_CTRL_PLL_LDO_CTL_AFE_LDO_CNTL_SHIFT 8
-#define BCHP_USB_CTRL_PLL_LDO_CTL_AFE_LDO_CNTL_DEFAULT 0x00000000
-
-/* USB_CTRL :: PLL_LDO_CTL :: AFE_LDO_SPARE [07:03] */
-#define BCHP_USB_CTRL_PLL_LDO_CTL_AFE_LDO_SPARE_MASK 0x000000f8
-#define BCHP_USB_CTRL_PLL_LDO_CTL_AFE_LDO_SPARE_SHIFT 3
-#define BCHP_USB_CTRL_PLL_LDO_CTL_AFE_LDO_SPARE_DEFAULT 0x00000000
-
-/* USB_CTRL :: PLL_LDO_CTL :: AFE_CORERDY_VDDC [02:02] */
-#define BCHP_USB_CTRL_PLL_LDO_CTL_AFE_CORERDY_VDDC_MASK 0x00000004
-#define BCHP_USB_CTRL_PLL_LDO_CTL_AFE_CORERDY_VDDC_SHIFT 2
-#define BCHP_USB_CTRL_PLL_LDO_CTL_AFE_CORERDY_VDDC_DEFAULT 0x00000001
-
-/* USB_CTRL :: PLL_LDO_CTL :: AFE_LDO_PWRDWNB [01:01] */
-#define BCHP_USB_CTRL_PLL_LDO_CTL_AFE_LDO_PWRDWNB_MASK 0x00000002
-#define BCHP_USB_CTRL_PLL_LDO_CTL_AFE_LDO_PWRDWNB_SHIFT 1
-#define BCHP_USB_CTRL_PLL_LDO_CTL_AFE_LDO_PWRDWNB_DEFAULT 0x00000001
-
-/* USB_CTRL :: PLL_LDO_CTL :: AFE_BG_PWRDWNB [00:00] */
-#define BCHP_USB_CTRL_PLL_LDO_CTL_AFE_BG_PWRDWNB_MASK 0x00000001
-#define BCHP_USB_CTRL_PLL_LDO_CTL_AFE_BG_PWRDWNB_SHIFT 0
-#define BCHP_USB_CTRL_PLL_LDO_CTL_AFE_BG_PWRDWNB_DEFAULT 0x00000001
-
-/***************************************************************************
- *PLL_LDO_PLLBIAS - 28NM USBPHY PLLBIAS Control
- ***************************************************************************/
-/* USB_CTRL :: PLL_LDO_PLLBIAS :: PLLBIAS_SPARE [31:18] */
-#define BCHP_USB_CTRL_PLL_LDO_PLLBIAS_PLLBIAS_SPARE_MASK 0xfffc0000
-#define BCHP_USB_CTRL_PLL_LDO_PLLBIAS_PLLBIAS_SPARE_SHIFT 18
-#define BCHP_USB_CTRL_PLL_LDO_PLLBIAS_PLLBIAS_SPARE_DEFAULT 0x00000000
-
-/* USB_CTRL :: PLL_LDO_PLLBIAS :: AFE_PLLBIAS_TESTMODE [17:00] */
-#define BCHP_USB_CTRL_PLL_LDO_PLLBIAS_AFE_PLLBIAS_TESTMODE_MASK 0x0003ffff
-#define BCHP_USB_CTRL_PLL_LDO_PLLBIAS_AFE_PLLBIAS_TESTMODE_SHIFT 0
-#define BCHP_USB_CTRL_PLL_LDO_PLLBIAS_AFE_PLLBIAS_TESTMODE_DEFAULT 0x00000000
-
-/***************************************************************************
- *PLL_AFE_BG_CNTL - 28NM USBPHY AFE Bandgap Control
- ***************************************************************************/
-/* USB_CTRL :: PLL_AFE_BG_CNTL :: PLL_AFE_BG_SPARE [31:17] */
-#define BCHP_USB_CTRL_PLL_AFE_BG_CNTL_PLL_AFE_BG_SPARE_MASK 0xfffe0000
-#define BCHP_USB_CTRL_PLL_AFE_BG_CNTL_PLL_AFE_BG_SPARE_SHIFT 17
-#define BCHP_USB_CTRL_PLL_AFE_BG_CNTL_PLL_AFE_BG_SPARE_DEFAULT 0x00000000
-
-/* USB_CTRL :: PLL_AFE_BG_CNTL :: AFE_BG_PRGM [16:12] */
-#define BCHP_USB_CTRL_PLL_AFE_BG_CNTL_AFE_BG_PRGM_MASK 0x0001f000
-#define BCHP_USB_CTRL_PLL_AFE_BG_CNTL_AFE_BG_PRGM_SHIFT 12
-#define BCHP_USB_CTRL_PLL_AFE_BG_CNTL_AFE_BG_PRGM_DEFAULT 0x00000000
-
-/* USB_CTRL :: PLL_AFE_BG_CNTL :: AFE_BG_VREF0P7_AFE_PRGM [11:08] */
-#define BCHP_USB_CTRL_PLL_AFE_BG_CNTL_AFE_BG_VREF0P7_AFE_PRGM_MASK 0x00000f00
-#define BCHP_USB_CTRL_PLL_AFE_BG_CNTL_AFE_BG_VREF0P7_AFE_PRGM_SHIFT 8
-#define BCHP_USB_CTRL_PLL_AFE_BG_CNTL_AFE_BG_VREF0P7_AFE_PRGM_DEFAULT 0x00000000
-
-/* USB_CTRL :: PLL_AFE_BG_CNTL :: AFE_BG_VREF0P7_DFE_PRGM [07:04] */
-#define BCHP_USB_CTRL_PLL_AFE_BG_CNTL_AFE_BG_VREF0P7_DFE_PRGM_MASK 0x000000f0
-#define BCHP_USB_CTRL_PLL_AFE_BG_CNTL_AFE_BG_VREF0P7_DFE_PRGM_SHIFT 4
-#define BCHP_USB_CTRL_PLL_AFE_BG_CNTL_AFE_BG_VREF0P7_DFE_PRGM_DEFAULT 0x00000000
-
-/* USB_CTRL :: PLL_AFE_BG_CNTL :: AFE_BG_VREF1P0_TRIM [03:00] */
-#define BCHP_USB_CTRL_PLL_AFE_BG_CNTL_AFE_BG_VREF1P0_TRIM_MASK 0x0000000f
-#define BCHP_USB_CTRL_PLL_AFE_BG_CNTL_AFE_BG_VREF1P0_TRIM_SHIFT 0
-#define BCHP_USB_CTRL_PLL_AFE_BG_CNTL_AFE_BG_VREF1P0_TRIM_DEFAULT 0x00000000
-
-/***************************************************************************
- *AFE_USBIO_TST - 28NM USBPHY AFE Bandgap Control
- ***************************************************************************/
-/* USB_CTRL :: AFE_USBIO_TST :: AFE_USBIO_TST_SPARE [31:16] */
-#define BCHP_USB_CTRL_AFE_USBIO_TST_AFE_USBIO_TST_SPARE_MASK 0xffff0000
-#define BCHP_USB_CTRL_AFE_USBIO_TST_AFE_USBIO_TST_SPARE_SHIFT 16
-#define BCHP_USB_CTRL_AFE_USBIO_TST_AFE_USBIO_TST_SPARE_DEFAULT 0x00000000
-
-/* USB_CTRL :: AFE_USBIO_TST :: AFE_USBIO_TST_P2 [15:08] */
-#define BCHP_USB_CTRL_AFE_USBIO_TST_AFE_USBIO_TST_P2_MASK 0x0000ff00
-#define BCHP_USB_CTRL_AFE_USBIO_TST_AFE_USBIO_TST_P2_SHIFT 8
-#define BCHP_USB_CTRL_AFE_USBIO_TST_AFE_USBIO_TST_P2_DEFAULT 0x00000000
-
-/* USB_CTRL :: AFE_USBIO_TST :: AFE_USBIO_TST_P1 [07:00] */
-#define BCHP_USB_CTRL_AFE_USBIO_TST_AFE_USBIO_TST_P1_MASK 0x000000ff
-#define BCHP_USB_CTRL_AFE_USBIO_TST_AFE_USBIO_TST_P1_SHIFT 0
-#define BCHP_USB_CTRL_AFE_USBIO_TST_AFE_USBIO_TST_P1_DEFAULT 0x00000000
-
-/***************************************************************************
- *PLL_NDIV_FRAC - PLL Feedback Divider Control Register
- ***************************************************************************/
-/* USB_CTRL :: PLL_NDIV_FRAC :: PLL_NDIV_FRAC_SPARE2 [31:20] */
-#define BCHP_USB_CTRL_PLL_NDIV_FRAC_PLL_NDIV_FRAC_SPARE2_MASK 0xfff00000
-#define BCHP_USB_CTRL_PLL_NDIV_FRAC_PLL_NDIV_FRAC_SPARE2_SHIFT 20
-#define BCHP_USB_CTRL_PLL_NDIV_FRAC_PLL_NDIV_FRAC_SPARE2_DEFAULT 0x00000000
-
-/* USB_CTRL :: PLL_NDIV_FRAC :: pll_ndiv_frac [19:00] */
-#define BCHP_USB_CTRL_PLL_NDIV_FRAC_pll_ndiv_frac_MASK 0x000fffff
-#define BCHP_USB_CTRL_PLL_NDIV_FRAC_pll_ndiv_frac_SHIFT 0
-#define BCHP_USB_CTRL_PLL_NDIV_FRAC_pll_ndiv_frac_DEFAULT 0x00000000
-
-/***************************************************************************
- *SPARE2 - Spare2 Register for future use
- ***************************************************************************/
-/* USB_CTRL :: SPARE2 :: SPARE2_BITS [31:00] */
-#define BCHP_USB_CTRL_SPARE2_SPARE2_BITS_MASK 0xffffffff
-#define BCHP_USB_CTRL_SPARE2_SPARE2_BITS_SHIFT 0
-#define BCHP_USB_CTRL_SPARE2_SPARE2_BITS_DEFAULT 0x00000000
-
-/***************************************************************************
- *SPARE3 - Spare1 Register for future use
- ***************************************************************************/
-/* USB_CTRL :: SPARE3 :: SPARE3_BITS [31:00] */
-#define BCHP_USB_CTRL_SPARE3_SPARE3_BITS_MASK 0xffffffff
-#define BCHP_USB_CTRL_SPARE3_SPARE3_BITS_SHIFT 0
-#define BCHP_USB_CTRL_SPARE3_SPARE3_BITS_DEFAULT 0x00000000
-
-/***************************************************************************
- *SPARE4 - Spare1 Register for future use
- ***************************************************************************/
-/* USB_CTRL :: SPARE4 :: SPARE4_BITS [31:00] */
-#define BCHP_USB_CTRL_SPARE4_SPARE4_BITS_MASK 0xffffffff
-#define BCHP_USB_CTRL_SPARE4_SPARE4_BITS_SHIFT 0
-#define BCHP_USB_CTRL_SPARE4_SPARE4_BITS_DEFAULT 0x00000000
-
-/***************************************************************************
- *USB30_CTL1 - USB30 CONTROL Register 1
- ***************************************************************************/
-/* USB_CTRL :: USB30_CTL1 :: usb3_oc_dis [31:31] */
-#define BCHP_USB_CTRL_USB30_CTL1_usb3_oc_dis_MASK 0x80000000
-#define BCHP_USB_CTRL_USB30_CTL1_usb3_oc_dis_SHIFT 31
-#define BCHP_USB_CTRL_USB30_CTL1_usb3_oc_dis_DEFAULT 0x00000000
-
-/* USB_CTRL :: USB30_CTL1 :: usb3_ipp [30:30] */
-#define BCHP_USB_CTRL_USB30_CTL1_usb3_ipp_MASK 0x40000000
-#define BCHP_USB_CTRL_USB30_CTL1_usb3_ipp_SHIFT 30
-#define BCHP_USB_CTRL_USB30_CTL1_usb3_ipp_DEFAULT 0x00000000
-
-/* USB_CTRL :: USB30_CTL1 :: usb3_ioc [29:29] */
-#define BCHP_USB_CTRL_USB30_CTL1_usb3_ioc_MASK 0x20000000
-#define BCHP_USB_CTRL_USB30_CTL1_usb3_ioc_SHIFT 29
-#define BCHP_USB_CTRL_USB30_CTL1_usb3_ioc_DEFAULT 0x00000000
-
-/* USB_CTRL :: USB30_CTL1 :: usb3_pwron_sel [28:27] */
-#define BCHP_USB_CTRL_USB30_CTL1_usb3_pwron_sel_MASK 0x18000000
-#define BCHP_USB_CTRL_USB30_CTL1_usb3_pwron_sel_SHIFT 27
-#define BCHP_USB_CTRL_USB30_CTL1_usb3_pwron_sel_DEFAULT 0x00000000
-
-/* USB_CTRL :: USB30_CTL1 :: usb3_pwron_force [26:26] */
-#define BCHP_USB_CTRL_USB30_CTL1_usb3_pwron_force_MASK 0x04000000
-#define BCHP_USB_CTRL_USB30_CTL1_usb3_pwron_force_SHIFT 26
-#define BCHP_USB_CTRL_USB30_CTL1_usb3_pwron_force_DEFAULT 0x00000000
-
-/* USB_CTRL :: USB30_CTL1 :: usb3_pwron_force_val [25:25] */
-#define BCHP_USB_CTRL_USB30_CTL1_usb3_pwron_force_val_MASK 0x02000000
-#define BCHP_USB_CTRL_USB30_CTL1_usb3_pwron_force_val_SHIFT 25
-#define BCHP_USB_CTRL_USB30_CTL1_usb3_pwron_force_val_DEFAULT 0x00000000
-
-/* USB_CTRL :: USB30_CTL1 :: usb30_ctl1_spare2 [24:19] */
-#define BCHP_USB_CTRL_USB30_CTL1_usb30_ctl1_spare2_MASK 0x01f80000
-#define BCHP_USB_CTRL_USB30_CTL1_usb30_ctl1_spare2_SHIFT 19
-#define BCHP_USB_CTRL_USB30_CTL1_usb30_ctl1_spare2_DEFAULT 0x00000000
-
-/* USB_CTRL :: USB30_CTL1 :: aux_resetb [18:18] */
-#define BCHP_USB_CTRL_USB30_CTL1_aux_resetb_MASK 0x00040000
-#define BCHP_USB_CTRL_USB30_CTL1_aux_resetb_SHIFT 18
-#define BCHP_USB_CTRL_USB30_CTL1_aux_resetb_DEFAULT 0x00000000
-
-/* USB_CTRL :: USB30_CTL1 :: xhc_soft_resetb [17:17] */
-#define BCHP_USB_CTRL_USB30_CTL1_xhc_soft_resetb_MASK 0x00020000
-#define BCHP_USB_CTRL_USB30_CTL1_xhc_soft_resetb_SHIFT 17
-#define BCHP_USB_CTRL_USB30_CTL1_xhc_soft_resetb_DEFAULT 0x00000000
-
-/* USB_CTRL :: USB30_CTL1 :: phy3_resetb [16:16] */
-#define BCHP_USB_CTRL_USB30_CTL1_phy3_resetb_MASK 0x00010000
-#define BCHP_USB_CTRL_USB30_CTL1_phy3_resetb_SHIFT 16
-#define BCHP_USB_CTRL_USB30_CTL1_phy3_resetb_DEFAULT 0x00000001
-
-/* USB_CTRL :: USB30_CTL1 :: usb30_ctl1_spare1 [15:07] */
-#define BCHP_USB_CTRL_USB30_CTL1_usb30_ctl1_spare1_MASK 0x0000ff80
-#define BCHP_USB_CTRL_USB30_CTL1_usb30_ctl1_spare1_SHIFT 7
-#define BCHP_USB_CTRL_USB30_CTL1_usb30_ctl1_spare1_DEFAULT 0x00000000
-
-/* USB_CTRL :: USB30_CTL1 :: phy3_standalonemode [06:06] */
-#define BCHP_USB_CTRL_USB30_CTL1_phy3_standalonemode_MASK 0x00000040
-#define BCHP_USB_CTRL_USB30_CTL1_phy3_standalonemode_SHIFT 6
-#define BCHP_USB_CTRL_USB30_CTL1_phy3_standalonemode_DEFAULT 0x00000000
-
-/* USB_CTRL :: USB30_CTL1 :: phy3_phy_iso [05:05] */
-#define BCHP_USB_CTRL_USB30_CTL1_phy3_phy_iso_MASK 0x00000020
-#define BCHP_USB_CTRL_USB30_CTL1_phy3_phy_iso_SHIFT 5
-#define BCHP_USB_CTRL_USB30_CTL1_phy3_phy_iso_DEFAULT 0x00000000
-
-/* USB_CTRL :: USB30_CTL1 :: phy3_pll_seq_start [04:04] */
-#define BCHP_USB_CTRL_USB30_CTL1_phy3_pll_seq_start_MASK 0x00000010
-#define BCHP_USB_CTRL_USB30_CTL1_phy3_pll_seq_start_SHIFT 4
-#define BCHP_USB_CTRL_USB30_CTL1_phy3_pll_seq_start_DEFAULT 0x00000000
-
-/* USB_CTRL :: USB30_CTL1 :: phy3_pll_refclk_sel [03:01] */
-#define BCHP_USB_CTRL_USB30_CTL1_phy3_pll_refclk_sel_MASK 0x0000000e
-#define BCHP_USB_CTRL_USB30_CTL1_phy3_pll_refclk_sel_SHIFT 1
-#define BCHP_USB_CTRL_USB30_CTL1_phy3_pll_refclk_sel_DEFAULT 0x00000004
-
-/* USB_CTRL :: USB30_CTL1 :: phy3_pll_auxclk_sel [00:00] */
-#define BCHP_USB_CTRL_USB30_CTL1_phy3_pll_auxclk_sel_MASK 0x00000001
-#define BCHP_USB_CTRL_USB30_CTL1_phy3_pll_auxclk_sel_SHIFT 0
-#define BCHP_USB_CTRL_USB30_CTL1_phy3_pll_auxclk_sel_DEFAULT 0x00000000
-
-/***************************************************************************
- *USB30_CTL2 - USB30 CONTROL Register 2
- ***************************************************************************/
-/* USB_CTRL :: USB30_CTL2 :: usb30_ctl2_spare2 [31:30] */
-#define BCHP_USB_CTRL_USB30_CTL2_usb30_ctl2_spare2_MASK 0xc0000000
-#define BCHP_USB_CTRL_USB30_CTL2_usb30_ctl2_spare2_SHIFT 30
-#define BCHP_USB_CTRL_USB30_CTL2_usb30_ctl2_spare2_DEFAULT 0x00000000
-
-/* USB_CTRL :: USB30_CTL2 :: xhci_max_scb_size [29:24] */
-#define BCHP_USB_CTRL_USB30_CTL2_xhci_max_scb_size_MASK 0x3f000000
-#define BCHP_USB_CTRL_USB30_CTL2_xhci_max_scb_size_SHIFT 24
-#define BCHP_USB_CTRL_USB30_CTL2_xhci_max_scb_size_DEFAULT 0x00000020
-
-/* USB_CTRL :: USB30_CTL2 :: xhci_wrfifo_thrshld [23:16] */
-#define BCHP_USB_CTRL_USB30_CTL2_xhci_wrfifo_thrshld_MASK 0x00ff0000
-#define BCHP_USB_CTRL_USB30_CTL2_xhci_wrfifo_thrshld_SHIFT 16
-#define BCHP_USB_CTRL_USB30_CTL2_xhci_wrfifo_thrshld_DEFAULT 0x00000000
-
-/* USB_CTRL :: USB30_CTL2 :: xhci_rdfifo_thrshld [15:08] */
-#define BCHP_USB_CTRL_USB30_CTL2_xhci_rdfifo_thrshld_MASK 0x0000ff00
-#define BCHP_USB_CTRL_USB30_CTL2_xhci_rdfifo_thrshld_SHIFT 8
-#define BCHP_USB_CTRL_USB30_CTL2_xhci_rdfifo_thrshld_DEFAULT 0x00000000
-
-/* USB_CTRL :: USB30_CTL2 :: usb30_ctl2_spare1 [07:03] */
-#define BCHP_USB_CTRL_USB30_CTL2_usb30_ctl2_spare1_MASK 0x000000f8
-#define BCHP_USB_CTRL_USB30_CTL2_usb30_ctl2_spare1_SHIFT 3
-#define BCHP_USB_CTRL_USB30_CTL2_usb30_ctl2_spare1_DEFAULT 0x00000000
-
-/* USB_CTRL :: USB30_CTL2 :: xhci_cntl_client_en [02:02] */
-#define BCHP_USB_CTRL_USB30_CTL2_xhci_cntl_client_en_MASK 0x00000004
-#define BCHP_USB_CTRL_USB30_CTL2_xhci_cntl_client_en_SHIFT 2
-#define BCHP_USB_CTRL_USB30_CTL2_xhci_cntl_client_en_DEFAULT 0x00000001
-
-/* USB_CTRL :: USB30_CTL2 :: xhci_swap_mode [01:00] */
-#define BCHP_USB_CTRL_USB30_CTL2_xhci_swap_mode_MASK 0x00000003
-#define BCHP_USB_CTRL_USB30_CTL2_xhci_swap_mode_SHIFT 0
-#define BCHP_USB_CTRL_USB30_CTL2_xhci_swap_mode_DEFAULT 0x00000000
-#define BCHP_USB_CTRL_USB30_CTL2_xhci_swap_mode_NO_SWAP 0
-#define BCHP_USB_CTRL_USB30_CTL2_xhci_swap_mode_DESC_DATA_SWAP 1
-#define BCHP_USB_CTRL_USB30_CTL2_xhci_swap_mode_DATA_SWAP 2
-#define BCHP_USB_CTRL_USB30_CTL2_xhci_swap_mode_DESC_SWAP 3
-
-/***************************************************************************
- *USB30_CTL3 - USB30 CONTROL Register 3
- ***************************************************************************/
-/* USB_CTRL :: USB30_CTL3 :: usb30_ctl3_spare2 [31:30] */
-#define BCHP_USB_CTRL_USB30_CTL3_usb30_ctl3_spare2_MASK 0xc0000000
-#define BCHP_USB_CTRL_USB30_CTL3_usb30_ctl3_spare2_SHIFT 30
-#define BCHP_USB_CTRL_USB30_CTL3_usb30_ctl3_spare2_DEFAULT 0x00000000
-
-/* USB_CTRL :: USB30_CTL3 :: phy3_pipe_txdeemph_en_p1 [29:29] */
-#define BCHP_USB_CTRL_USB30_CTL3_phy3_pipe_txdeemph_en_p1_MASK 0x20000000
-#define BCHP_USB_CTRL_USB30_CTL3_phy3_pipe_txdeemph_en_p1_SHIFT 29
-#define BCHP_USB_CTRL_USB30_CTL3_phy3_pipe_txdeemph_en_p1_DEFAULT 0x00000000
-
-/* USB_CTRL :: USB30_CTL3 :: phy3_pipe_txdeemph_p1 [28:24] */
-#define BCHP_USB_CTRL_USB30_CTL3_phy3_pipe_txdeemph_p1_MASK 0x1f000000
-#define BCHP_USB_CTRL_USB30_CTL3_phy3_pipe_txdeemph_p1_SHIFT 24
-#define BCHP_USB_CTRL_USB30_CTL3_phy3_pipe_txdeemph_p1_DEFAULT 0x0000001b
-
-/* USB_CTRL :: USB30_CTL3 :: phy3_pipe_txmargin_p1 [23:20] */
-#define BCHP_USB_CTRL_USB30_CTL3_phy3_pipe_txmargin_p1_MASK 0x00f00000
-#define BCHP_USB_CTRL_USB30_CTL3_phy3_pipe_txmargin_p1_SHIFT 20
-#define BCHP_USB_CTRL_USB30_CTL3_phy3_pipe_txmargin_p1_DEFAULT 0x00000009
-
-/* USB_CTRL :: USB30_CTL3 :: phy3_rxebufmode_p1 [19:19] */
-#define BCHP_USB_CTRL_USB30_CTL3_phy3_rxebufmode_p1_MASK 0x00080000
-#define BCHP_USB_CTRL_USB30_CTL3_phy3_rxebufmode_p1_SHIFT 19
-#define BCHP_USB_CTRL_USB30_CTL3_phy3_rxebufmode_p1_DEFAULT 0x00000000
-
-/* USB_CTRL :: USB30_CTL3 :: phy3_pipe_txmargin_en_p1 [18:18] */
-#define BCHP_USB_CTRL_USB30_CTL3_phy3_pipe_txmargin_en_p1_MASK 0x00040000
-#define BCHP_USB_CTRL_USB30_CTL3_phy3_pipe_txmargin_en_p1_SHIFT 18
-#define BCHP_USB_CTRL_USB30_CTL3_phy3_pipe_txmargin_en_p1_DEFAULT 0x00000000
-
-/* USB_CTRL :: USB30_CTL3 :: phy3_pipe_txswing_p1 [17:17] */
-#define BCHP_USB_CTRL_USB30_CTL3_phy3_pipe_txswing_p1_MASK 0x00020000
-#define BCHP_USB_CTRL_USB30_CTL3_phy3_pipe_txswing_p1_SHIFT 17
-#define BCHP_USB_CTRL_USB30_CTL3_phy3_pipe_txswing_p1_DEFAULT 0x00000000
-
-/* USB_CTRL :: USB30_CTL3 :: phy3_mode_p1 [16:16] */
-#define BCHP_USB_CTRL_USB30_CTL3_phy3_mode_p1_MASK 0x00010000
-#define BCHP_USB_CTRL_USB30_CTL3_phy3_mode_p1_SHIFT 16
-#define BCHP_USB_CTRL_USB30_CTL3_phy3_mode_p1_DEFAULT 0x00000001
-
-/* USB_CTRL :: USB30_CTL3 :: usb30_ctl3_spare1 [15:14] */
-#define BCHP_USB_CTRL_USB30_CTL3_usb30_ctl3_spare1_MASK 0x0000c000
-#define BCHP_USB_CTRL_USB30_CTL3_usb30_ctl3_spare1_SHIFT 14
-#define BCHP_USB_CTRL_USB30_CTL3_usb30_ctl3_spare1_DEFAULT 0x00000000
-
-/* USB_CTRL :: USB30_CTL3 :: phy3_pipe_txdeemph_en [13:13] */
-#define BCHP_USB_CTRL_USB30_CTL3_phy3_pipe_txdeemph_en_MASK 0x00002000
-#define BCHP_USB_CTRL_USB30_CTL3_phy3_pipe_txdeemph_en_SHIFT 13
-#define BCHP_USB_CTRL_USB30_CTL3_phy3_pipe_txdeemph_en_DEFAULT 0x00000000
-
-/* USB_CTRL :: USB30_CTL3 :: phy3_pipe_txdeemph [12:08] */
-#define BCHP_USB_CTRL_USB30_CTL3_phy3_pipe_txdeemph_MASK 0x00001f00
-#define BCHP_USB_CTRL_USB30_CTL3_phy3_pipe_txdeemph_SHIFT 8
-#define BCHP_USB_CTRL_USB30_CTL3_phy3_pipe_txdeemph_DEFAULT 0x0000001b
-
-/* USB_CTRL :: USB30_CTL3 :: phy3_pipe_txmargin [07:04] */
-#define BCHP_USB_CTRL_USB30_CTL3_phy3_pipe_txmargin_MASK 0x000000f0
-#define BCHP_USB_CTRL_USB30_CTL3_phy3_pipe_txmargin_SHIFT 4
-#define BCHP_USB_CTRL_USB30_CTL3_phy3_pipe_txmargin_DEFAULT 0x00000009
-
-/* USB_CTRL :: USB30_CTL3 :: phy3_rxebufmode [03:03] */
-#define BCHP_USB_CTRL_USB30_CTL3_phy3_rxebufmode_MASK 0x00000008
-#define BCHP_USB_CTRL_USB30_CTL3_phy3_rxebufmode_SHIFT 3
-#define BCHP_USB_CTRL_USB30_CTL3_phy3_rxebufmode_DEFAULT 0x00000000
-
-/* USB_CTRL :: USB30_CTL3 :: phy3_pipe_txmargin_en [02:02] */
-#define BCHP_USB_CTRL_USB30_CTL3_phy3_pipe_txmargin_en_MASK 0x00000004
-#define BCHP_USB_CTRL_USB30_CTL3_phy3_pipe_txmargin_en_SHIFT 2
-#define BCHP_USB_CTRL_USB30_CTL3_phy3_pipe_txmargin_en_DEFAULT 0x00000000
-
-/* USB_CTRL :: USB30_CTL3 :: phy3_pipe_txswing [01:01] */
-#define BCHP_USB_CTRL_USB30_CTL3_phy3_pipe_txswing_MASK 0x00000002
-#define BCHP_USB_CTRL_USB30_CTL3_phy3_pipe_txswing_SHIFT 1
-#define BCHP_USB_CTRL_USB30_CTL3_phy3_pipe_txswing_DEFAULT 0x00000000
-
-/* USB_CTRL :: USB30_CTL3 :: phy3_mode [00:00] */
-#define BCHP_USB_CTRL_USB30_CTL3_phy3_mode_MASK 0x00000001
-#define BCHP_USB_CTRL_USB30_CTL3_phy3_mode_SHIFT 0
-#define BCHP_USB_CTRL_USB30_CTL3_phy3_mode_DEFAULT 0x00000001
-
-/***************************************************************************
- *USB30_CTL4 - USB30 CONTROL Register 4
- ***************************************************************************/
-/* USB_CTRL :: USB30_CTL4 :: usb30_ctl4_spare1 [31:24] */
-#define BCHP_USB_CTRL_USB30_CTL4_usb30_ctl4_spare1_MASK 0xff000000
-#define BCHP_USB_CTRL_USB30_CTL4_usb30_ctl4_spare1_SHIFT 24
-#define BCHP_USB_CTRL_USB30_CTL4_usb30_ctl4_spare1_DEFAULT 0x00000000
-
-/* USB_CTRL :: USB30_CTL4 :: phy3_tpout_sel [23:16] */
-#define BCHP_USB_CTRL_USB30_CTL4_phy3_tpout_sel_MASK 0x00ff0000
-#define BCHP_USB_CTRL_USB30_CTL4_phy3_tpout_sel_SHIFT 16
-#define BCHP_USB_CTRL_USB30_CTL4_phy3_tpout_sel_DEFAULT 0x00000000
-
-/* USB_CTRL :: USB30_CTL4 :: xhci_tpout_sel [15:00] */
-#define BCHP_USB_CTRL_USB30_CTL4_xhci_tpout_sel_MASK 0x0000ffff
-#define BCHP_USB_CTRL_USB30_CTL4_xhci_tpout_sel_SHIFT 0
-#define BCHP_USB_CTRL_USB30_CTL4_xhci_tpout_sel_DEFAULT 0x00000000
-
-/***************************************************************************
- *SPARE5 - Spare1 Register for future use
- ***************************************************************************/
-/* USB_CTRL :: SPARE5 :: SPARE5_BITS [31:00] */
-#define BCHP_USB_CTRL_SPARE5_SPARE5_BITS_MASK 0xffffffff
-#define BCHP_USB_CTRL_SPARE5_SPARE5_BITS_SHIFT 0
-#define BCHP_USB_CTRL_SPARE5_SPARE5_BITS_DEFAULT 0x00000000
-
-/***************************************************************************
- *SPARE6 - Spare2 Register for future use
- ***************************************************************************/
-/* USB_CTRL :: SPARE6 :: SPARE6_BITS [31:00] */
-#define BCHP_USB_CTRL_SPARE6_SPARE6_BITS_MASK 0xffffffff
-#define BCHP_USB_CTRL_SPARE6_SPARE6_BITS_SHIFT 0
-#define BCHP_USB_CTRL_SPARE6_SPARE6_BITS_DEFAULT 0x00000000
-
-#endif /* #ifndef BCHP_USB_CTRL_H__ */
-
-/* End of File */
diff --git a/include/linux/brcmstb/7366b0/bchp_aon_ctrl.h b/include/linux/brcmstb/7366b0/bchp_aon_ctrl.h
deleted file mode 100644
index 3f70b2a..0000000
--- a/include/linux/brcmstb/7366b0/bchp_aon_ctrl.h
+++ /dev/null
@@ -1,1791 +0,0 @@
-/***************************************************************************
- * Copyright (c) 1999-2014, Broadcom Corporation
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
- *
- * Module Description:
- * DO NOT EDIT THIS FILE DIRECTLY
- *
- * This module was generated magically with RDB from a source description
- * file. You must edit the source file for changes to be made to this file.
- *
- *
- * Date: Generated on Thu Apr 24 03:08:55 2014
- * Full Compile MD5 Checksum 1af2c2cf28828ece5496e1312aac0166
- * (minus title and desc)
- * MD5 Checksum 3203ffce85e3fc9a10f84123e54057b0
- *
- * Compiled with: RDB Utility combo_header.pl
- * RDB Parser 3.0
- * unknown unknown
- * Perl Interpreter 5.008008
- * Operating System linux
- *
- * Revision History:
- *
- * $brcm_Log: $
- *
- ***************************************************************************/
-
-#ifndef BCHP_AON_CTRL_H__
-#define BCHP_AON_CTRL_H__
-
-/***************************************************************************
- *AON_CTRL - AON Control Registers
- ***************************************************************************/
-#define BCHP_AON_CTRL_RESET_CTRL 0x00410000 /* Reset Control register for AON */
-#define BCHP_AON_CTRL_PM_CTRL 0x00410004 /* Control register for Power Controller */
-#define BCHP_AON_CTRL_PM_STATUS 0x00410008 /* Status register for Power Controller */
-#define BCHP_AON_CTRL_PM_IRQ_INPUT_STATUS 0x0041000c /* Power Management IRQ input status */
-#define BCHP_AON_CTRL_PM_CPU_WAIT_COUNT 0x00410010 /* Power Management Wait counter in place of Wait for Host CPU IRQ */
-#define BCHP_AON_CTRL_PM_CPU_GUARDBAND_TIMER 0x00410014 /* Power Good Guardband Timer for Host CPU */
-#define BCHP_AON_CTRL_PM_S3_STANDBY_TIMER 0x00410018 /* Deep Standby Assertion Timer */
-#define BCHP_AON_CTRL_PM_S3_WAKEUP_TIMER 0x0041001c /* Deep Standby Wakeup Timer */
-#define BCHP_AON_CTRL_PM_FAST_PWRDN_PRECHARGE 0x00410020 /* Control register for Power Controller */
-#define BCHP_AON_CTRL_PM_LED_CTRL 0x00410024 /* LED set control register */
-#define BCHP_AON_CTRL_PM_LED_AUTO_ON_ENABLES 0x00410028 /* LED set control register */
-#define BCHP_AON_CTRL_HLCD_CTRL 0x00410030 /* HW LED Clock Driver Control */
-#define BCHP_AON_CTRL_SECOND_FRACTION_COUNTER 0x00410034 /* Second Fraction Counter Initial value */
-#define BCHP_AON_CTRL_TIME_COUNTER 0x00410038 /* Hour/Minute Counter Initial value */
-#define BCHP_AON_CTRL_LED_DIGIT_CODE_0 0x0041003c /* Digit Code for digit 0, 1, 2, 3 */
-#define BCHP_AON_CTRL_LED_DIGIT_CODE_1 0x00410040 /* Digit Code for digit 4, 5, 6, 7 */
-#define BCHP_AON_CTRL_LED_DIGIT_CODE_2 0x00410044 /* Digit Code for digit 8, 9 */
-#define BCHP_AON_CTRL_LED_DIGIT_ADDR_OFFSET 0x00410048 /* Hour MSD/LSD and minute MSD/LSD address offset */
-#define BCHP_AON_CTRL_LED_STATUS_CTRL 0x0041004c /* LED status control */
-#define BCHP_AON_CTRL_GENERAL_CTRL_0 0x00410050 /* General control register 0 */
-#define BCHP_AON_CTRL_GENERAL_STATUS_0 0x00410054 /* General status register 0 */
-#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0 0x00410058 /* General control register without scan 0 */
-#define BCHP_AON_CTRL_SPARE_CTRL_0 0x00410060 /* Spare control bits reserved for future use */
-#define BCHP_AON_CTRL_SPARE_CTRL_1 0x00410064 /* Spare control bits reserved for future use */
-#define BCHP_AON_CTRL_UNCLEARED_SCRATCH 0x00410068 /* Scratch register */
-#define BCHP_AON_CTRL_RESET_HISTORY 0x0041006c /* Reset History Register For AON */
-#define BCHP_AON_CTRL_NMI_CTRL 0x00410070 /* Control register for NMI */
-#define BCHP_AON_CTRL_ANA_XTAL_CONTROL 0x00410074 /* Ana xtal gisb control */
-#define BCHP_AON_CTRL_SUB_TEST_MODE_CTRL 0x00410078 /* Test_mode control register */
-#define BCHP_AON_CTRL_SUB_TEST_MODE 0x0041007c /* Register source for sub_test_mode */
-#define BCHP_AON_CTRL_LATCHED_TEST_MODE 0x00410080 /* Final latched testmode value */
-#define BCHP_AON_CTRL_LATCHED_SUB_TEST_MODE 0x00410084 /* Final latched sub-testmode value */
-#define BCHP_AON_CTRL_PM_INITIATE 0x00410088 /* Power down initiate */
-#define BCHP_AON_CTRL_HOST_MISC_CMDS 0x0041008c /* Power up restore */
-#define BCHP_AON_CTRL_ANA_XTAL_EXT_CML_CONTROL 0x00410090 /* Ana xtal external CML control */
-#define BCHP_AON_CTRL_PM_DRAM_READY_STATUS_MASK 0x00410094 /* DRAM Ready status mask control */
-#define BCHP_AON_CTRL_ANA_CBUF0_CONTROL 0x00410110 /* Ana crystal buffer 0 control */
-#define BCHP_AON_CTRL_ANA_CBUF1_CONTROL 0x00410114 /* Ana crystal buffer 1 control */
-
-/***************************************************************************
- *RESET_CTRL - Reset Control register for AON
- ***************************************************************************/
-/* AON_CTRL :: RESET_CTRL :: reserved0 [31:04] */
-#define BCHP_AON_CTRL_RESET_CTRL_reserved0_MASK 0xfffffff0
-#define BCHP_AON_CTRL_RESET_CTRL_reserved0_SHIFT 4
-
-/* AON_CTRL :: RESET_CTRL :: front_panel_reset_enable_lock [03:03] */
-#define BCHP_AON_CTRL_RESET_CTRL_front_panel_reset_enable_lock_MASK 0x00000008
-#define BCHP_AON_CTRL_RESET_CTRL_front_panel_reset_enable_lock_SHIFT 3
-#define BCHP_AON_CTRL_RESET_CTRL_front_panel_reset_enable_lock_DEFAULT 0x00000000
-
-/* AON_CTRL :: RESET_CTRL :: front_panel_reset_enable [02:02] */
-#define BCHP_AON_CTRL_RESET_CTRL_front_panel_reset_enable_MASK 0x00000004
-#define BCHP_AON_CTRL_RESET_CTRL_front_panel_reset_enable_SHIFT 2
-#define BCHP_AON_CTRL_RESET_CTRL_front_panel_reset_enable_DEFAULT 0x00000000
-
-/* AON_CTRL :: RESET_CTRL :: front_panel_reset_polarity [01:01] */
-#define BCHP_AON_CTRL_RESET_CTRL_front_panel_reset_polarity_MASK 0x00000002
-#define BCHP_AON_CTRL_RESET_CTRL_front_panel_reset_polarity_SHIFT 1
-#define BCHP_AON_CTRL_RESET_CTRL_front_panel_reset_polarity_DEFAULT 0x00000000
-
-/* AON_CTRL :: RESET_CTRL :: clear_reset_history [00:00] */
-#define BCHP_AON_CTRL_RESET_CTRL_clear_reset_history_MASK 0x00000001
-#define BCHP_AON_CTRL_RESET_CTRL_clear_reset_history_SHIFT 0
-#define BCHP_AON_CTRL_RESET_CTRL_clear_reset_history_DEFAULT 0x00000000
-
-/***************************************************************************
- *PM_CTRL - Control register for Power Controller
- ***************************************************************************/
-/* AON_CTRL :: PM_CTRL :: reserved0 [31:21] */
-#define BCHP_AON_CTRL_PM_CTRL_reserved0_MASK 0xffe00000
-#define BCHP_AON_CTRL_PM_CTRL_reserved0_SHIFT 21
-
-/* AON_CTRL :: PM_CTRL :: pm_dphy_standby_clear [20:20] */
-#define BCHP_AON_CTRL_PM_CTRL_pm_dphy_standby_clear_MASK 0x00100000
-#define BCHP_AON_CTRL_PM_CTRL_pm_dphy_standby_clear_SHIFT 20
-#define BCHP_AON_CTRL_PM_CTRL_pm_dphy_standby_clear_DEFAULT 0x00000000
-
-/* AON_CTRL :: PM_CTRL :: reserved1 [19:08] */
-#define BCHP_AON_CTRL_PM_CTRL_reserved1_MASK 0x000fff00
-#define BCHP_AON_CTRL_PM_CTRL_reserved1_SHIFT 8
-
-/* AON_CTRL :: PM_CTRL :: min_s3_width_timer_bypass [07:07] */
-#define BCHP_AON_CTRL_PM_CTRL_min_s3_width_timer_bypass_MASK 0x00000080
-#define BCHP_AON_CTRL_PM_CTRL_min_s3_width_timer_bypass_SHIFT 7
-#define BCHP_AON_CTRL_PM_CTRL_min_s3_width_timer_bypass_DEFAULT 0x00000000
-
-/* AON_CTRL :: PM_CTRL :: pm_fast_power_down [06:06] */
-#define BCHP_AON_CTRL_PM_CTRL_pm_fast_power_down_MASK 0x00000040
-#define BCHP_AON_CTRL_PM_CTRL_pm_fast_power_down_SHIFT 6
-#define BCHP_AON_CTRL_PM_CTRL_pm_fast_power_down_DEFAULT 0x00000000
-
-/* AON_CTRL :: PM_CTRL :: pm_warm_boot [05:05] */
-#define BCHP_AON_CTRL_PM_CTRL_pm_warm_boot_MASK 0x00000020
-#define BCHP_AON_CTRL_PM_CTRL_pm_warm_boot_SHIFT 5
-#define BCHP_AON_CTRL_PM_CTRL_pm_warm_boot_DEFAULT 0x00000000
-
-/* AON_CTRL :: PM_CTRL :: pm_deep_standby [04:04] */
-#define BCHP_AON_CTRL_PM_CTRL_pm_deep_standby_MASK 0x00000010
-#define BCHP_AON_CTRL_PM_CTRL_pm_deep_standby_SHIFT 4
-#define BCHP_AON_CTRL_PM_CTRL_pm_deep_standby_DEFAULT 0x00000000
-
-/* AON_CTRL :: PM_CTRL :: pm_enable_cpu_pwrdn [03:03] */
-#define BCHP_AON_CTRL_PM_CTRL_pm_enable_cpu_pwrdn_MASK 0x00000008
-#define BCHP_AON_CTRL_PM_CTRL_pm_enable_cpu_pwrdn_SHIFT 3
-#define BCHP_AON_CTRL_PM_CTRL_pm_enable_cpu_pwrdn_DEFAULT 0x00000000
-
-/* AON_CTRL :: PM_CTRL :: pm_use_cpu_ready_ctrl [02:02] */
-#define BCHP_AON_CTRL_PM_CTRL_pm_use_cpu_ready_ctrl_MASK 0x00000004
-#define BCHP_AON_CTRL_PM_CTRL_pm_use_cpu_ready_ctrl_SHIFT 2
-#define BCHP_AON_CTRL_PM_CTRL_pm_use_cpu_ready_ctrl_DEFAULT 0x00000000
-
-/* AON_CTRL :: PM_CTRL :: pm_enable_pll_pwrdn [01:01] */
-#define BCHP_AON_CTRL_PM_CTRL_pm_enable_pll_pwrdn_MASK 0x00000002
-#define BCHP_AON_CTRL_PM_CTRL_pm_enable_pll_pwrdn_SHIFT 1
-#define BCHP_AON_CTRL_PM_CTRL_pm_enable_pll_pwrdn_DEFAULT 0x00000000
-
-/* AON_CTRL :: PM_CTRL :: pm_start_pwrdn [00:00] */
-#define BCHP_AON_CTRL_PM_CTRL_pm_start_pwrdn_MASK 0x00000001
-#define BCHP_AON_CTRL_PM_CTRL_pm_start_pwrdn_SHIFT 0
-
-/***************************************************************************
- *PM_STATUS - Status register for Power Controller
- ***************************************************************************/
-/* AON_CTRL :: PM_STATUS :: pm_wait_count_upper_bits [31:28] */
-#define BCHP_AON_CTRL_PM_STATUS_pm_wait_count_upper_bits_MASK 0xf0000000
-#define BCHP_AON_CTRL_PM_STATUS_pm_wait_count_upper_bits_SHIFT 28
-
-/* AON_CTRL :: PM_STATUS :: pm_wait_counter_active [27:27] */
-#define BCHP_AON_CTRL_PM_STATUS_pm_wait_counter_active_MASK 0x08000000
-#define BCHP_AON_CTRL_PM_STATUS_pm_wait_counter_active_SHIFT 27
-
-/* AON_CTRL :: PM_STATUS :: pm_power_down_cpu [26:26] */
-#define BCHP_AON_CTRL_PM_STATUS_pm_power_down_cpu_MASK 0x04000000
-#define BCHP_AON_CTRL_PM_STATUS_pm_power_down_cpu_SHIFT 26
-
-/* AON_CTRL :: PM_STATUS :: pm_cpu_reset_b [25:25] */
-#define BCHP_AON_CTRL_PM_STATUS_pm_cpu_reset_b_MASK 0x02000000
-#define BCHP_AON_CTRL_PM_STATUS_pm_cpu_reset_b_SHIFT 25
-
-/* AON_CTRL :: PM_STATUS :: pm_s3_wakeup_reset_ [24:24] */
-#define BCHP_AON_CTRL_PM_STATUS_pm_s3_wakeup_reset__MASK 0x01000000
-#define BCHP_AON_CTRL_PM_STATUS_pm_s3_wakeup_reset__SHIFT 24
-
-/* AON_CTRL :: PM_STATUS :: pm_boundary_scan_request [23:23] */
-#define BCHP_AON_CTRL_PM_STATUS_pm_boundary_scan_request_MASK 0x00800000
-#define BCHP_AON_CTRL_PM_STATUS_pm_boundary_scan_request_SHIFT 23
-
-/* AON_CTRL :: PM_STATUS :: pm_fast_pd_precharge_valid [22:22] */
-#define BCHP_AON_CTRL_PM_STATUS_pm_fast_pd_precharge_valid_MASK 0x00400000
-#define BCHP_AON_CTRL_PM_STATUS_pm_fast_pd_precharge_valid_SHIFT 22
-
-/* AON_CTRL :: PM_STATUS :: pm_led_out [21:21] */
-#define BCHP_AON_CTRL_PM_STATUS_pm_led_out_MASK 0x00200000
-#define BCHP_AON_CTRL_PM_STATUS_pm_led_out_SHIFT 21
-
-/* AON_CTRL :: PM_STATUS :: pm_standby_b [20:20] */
-#define BCHP_AON_CTRL_PM_STATUS_pm_standby_b_MASK 0x00100000
-#define BCHP_AON_CTRL_PM_STATUS_pm_standby_b_SHIFT 20
-
-/* AON_CTRL :: PM_STATUS :: pm_ignore_inputs_ng [19:19] */
-#define BCHP_AON_CTRL_PM_STATUS_pm_ignore_inputs_ng_MASK 0x00080000
-#define BCHP_AON_CTRL_PM_STATUS_pm_ignore_inputs_ng_SHIFT 19
-
-/* AON_CTRL :: PM_STATUS :: pm_ignore_inputs [18:18] */
-#define BCHP_AON_CTRL_PM_STATUS_pm_ignore_inputs_MASK 0x00040000
-#define BCHP_AON_CTRL_PM_STATUS_pm_ignore_inputs_SHIFT 18
-
-/* AON_CTRL :: PM_STATUS :: pm_s2_standby [17:17] */
-#define BCHP_AON_CTRL_PM_STATUS_pm_s2_standby_MASK 0x00020000
-#define BCHP_AON_CTRL_PM_STATUS_pm_s2_standby_SHIFT 17
-
-/* AON_CTRL :: PM_STATUS :: pm_pwrdn_pll_req [16:16] */
-#define BCHP_AON_CTRL_PM_STATUS_pm_pwrdn_pll_req_MASK 0x00010000
-#define BCHP_AON_CTRL_PM_STATUS_pm_pwrdn_pll_req_SHIFT 16
-
-/* AON_CTRL :: PM_STATUS :: pm_dis_xtal_clocks [15:15] */
-#define BCHP_AON_CTRL_PM_STATUS_pm_dis_xtal_clocks_MASK 0x00008000
-#define BCHP_AON_CTRL_PM_STATUS_pm_dis_xtal_clocks_SHIFT 15
-
-/* AON_CTRL :: PM_STATUS :: pm_dis_all_clocks [14:14] */
-#define BCHP_AON_CTRL_PM_STATUS_pm_dis_all_clocks_MASK 0x00004000
-#define BCHP_AON_CTRL_PM_STATUS_pm_dis_all_clocks_SHIFT 14
-
-/* AON_CTRL :: PM_STATUS :: pm_dphy_standby [13:13] */
-#define BCHP_AON_CTRL_PM_STATUS_pm_dphy_standby_MASK 0x00002000
-#define BCHP_AON_CTRL_PM_STATUS_pm_dphy_standby_SHIFT 13
-
-/* AON_CTRL :: PM_STATUS :: pm_dis_cpu_clock [12:12] */
-#define BCHP_AON_CTRL_PM_STATUS_pm_dis_cpu_clock_MASK 0x00001000
-#define BCHP_AON_CTRL_PM_STATUS_pm_dis_cpu_clock_SHIFT 12
-
-/* AON_CTRL :: PM_STATUS :: pm_dis_avd_rptd_clock [11:11] */
-#define BCHP_AON_CTRL_PM_STATUS_pm_dis_avd_rptd_clock_MASK 0x00000800
-#define BCHP_AON_CTRL_PM_STATUS_pm_dis_avd_rptd_clock_SHIFT 11
-
-/* AON_CTRL :: PM_STATUS :: pm_power_ctrl_disable [10:10] */
-#define BCHP_AON_CTRL_PM_STATUS_pm_power_ctrl_disable_MASK 0x00000400
-#define BCHP_AON_CTRL_PM_STATUS_pm_power_ctrl_disable_SHIFT 10
-
-/* AON_CTRL :: PM_STATUS :: pm_pll_lock [09:09] */
-#define BCHP_AON_CTRL_PM_STATUS_pm_pll_lock_MASK 0x00000200
-#define BCHP_AON_CTRL_PM_STATUS_pm_pll_lock_SHIFT 9
-
-/* AON_CTRL :: PM_STATUS :: pm_dram_ready_for_pwrdn [08:08] */
-#define BCHP_AON_CTRL_PM_STATUS_pm_dram_ready_for_pwrdn_MASK 0x00000100
-#define BCHP_AON_CTRL_PM_STATUS_pm_dram_ready_for_pwrdn_SHIFT 8
-
-/* AON_CTRL :: PM_STATUS :: pm_bsp_ready_for_pwrdn [07:07] */
-#define BCHP_AON_CTRL_PM_STATUS_pm_bsp_ready_for_pwrdn_MASK 0x00000080
-#define BCHP_AON_CTRL_PM_STATUS_pm_bsp_ready_for_pwrdn_SHIFT 7
-
-/* AON_CTRL :: PM_STATUS :: pm_cpu_ready_for_pwrdn [06:06] */
-#define BCHP_AON_CTRL_PM_STATUS_pm_cpu_ready_for_pwrdn_MASK 0x00000040
-#define BCHP_AON_CTRL_PM_STATUS_pm_cpu_ready_for_pwrdn_SHIFT 6
-
-/* AON_CTRL :: PM_STATUS :: pm_sec_avd_rptd_clk_disable [05:05] */
-#define BCHP_AON_CTRL_PM_STATUS_pm_sec_avd_rptd_clk_disable_MASK 0x00000020
-#define BCHP_AON_CTRL_PM_STATUS_pm_sec_avd_rptd_clk_disable_SHIFT 5
-
-/* AON_CTRL :: PM_STATUS :: pm_state [04:00] */
-#define BCHP_AON_CTRL_PM_STATUS_pm_state_MASK 0x0000001f
-#define BCHP_AON_CTRL_PM_STATUS_pm_state_SHIFT 0
-#define BCHP_AON_CTRL_PM_STATUS_pm_state_PM_ACTIVE 0
-#define BCHP_AON_CTRL_PM_STATUS_pm_state_PM_PWRDN_RDY 1
-#define BCHP_AON_CTRL_PM_STATUS_pm_state_PM_DISABLE_AVD_RPTD 2
-#define BCHP_AON_CTRL_PM_STATUS_pm_state_PM_DISABLE_CPU 3
-#define BCHP_AON_CTRL_PM_STATUS_pm_state_PM_TRANSITION_TO_STANDBY 4
-#define BCHP_AON_CTRL_PM_STATUS_pm_state_PM_STANDBY 5
-#define BCHP_AON_CTRL_PM_STATUS_pm_state_PM_STANDBY_WITH_PLLS_ON 6
-#define BCHP_AON_CTRL_PM_STATUS_pm_state_PM_HOLD_CPU_POWERED_DOWN 7
-#define BCHP_AON_CTRL_PM_STATUS_pm_state_PM_POWER_UP_CPU 8
-#define BCHP_AON_CTRL_PM_STATUS_pm_state_PM_TRANSITION_TO_ACTIVE 9
-#define BCHP_AON_CTRL_PM_STATUS_pm_state_PM_FAST_PWRDN 10
-#define BCHP_AON_CTRL_PM_STATUS_pm_state_PM_DEEP_STANDBY_ENTRY_S1 11
-#define BCHP_AON_CTRL_PM_STATUS_pm_state_PM_DEEP_STANDBY_COLD_ENTRY_S2 12
-#define BCHP_AON_CTRL_PM_STATUS_pm_state_PM_DEEP_STANDBY_WARM_ENTRY_S2 13
-#define BCHP_AON_CTRL_PM_STATUS_pm_state_PM_DEEP_STANDBY_ENTRY_S3 14
-#define BCHP_AON_CTRL_PM_STATUS_pm_state_PM_DEEP_STANDBY 15
-#define BCHP_AON_CTRL_PM_STATUS_pm_state_PM_DEEP_STANDBY_EXIT_S1 16
-#define BCHP_AON_CTRL_PM_STATUS_pm_state_PM_DEEP_STANDBY_EXIT_S2 17
-
-/***************************************************************************
- *PM_IRQ_INPUT_STATUS - Power Management IRQ input status
- ***************************************************************************/
-/* AON_CTRL :: PM_IRQ_INPUT_STATUS :: pm_irq_input_status [31:00] */
-#define BCHP_AON_CTRL_PM_IRQ_INPUT_STATUS_pm_irq_input_status_MASK 0xffffffff
-#define BCHP_AON_CTRL_PM_IRQ_INPUT_STATUS_pm_irq_input_status_SHIFT 0
-
-/***************************************************************************
- *PM_CPU_WAIT_COUNT - Power Management Wait counter in place of Wait for Host CPU IRQ
- ***************************************************************************/
-/* AON_CTRL :: PM_CPU_WAIT_COUNT :: reserved0 [31:16] */
-#define BCHP_AON_CTRL_PM_CPU_WAIT_COUNT_reserved0_MASK 0xffff0000
-#define BCHP_AON_CTRL_PM_CPU_WAIT_COUNT_reserved0_SHIFT 16
-
-/* AON_CTRL :: PM_CPU_WAIT_COUNT :: counter_start_value [15:00] */
-#define BCHP_AON_CTRL_PM_CPU_WAIT_COUNT_counter_start_value_MASK 0x0000ffff
-#define BCHP_AON_CTRL_PM_CPU_WAIT_COUNT_counter_start_value_SHIFT 0
-#define BCHP_AON_CTRL_PM_CPU_WAIT_COUNT_counter_start_value_DEFAULT 0x00000010
-
-/***************************************************************************
- *PM_CPU_GUARDBAND_TIMER - Power Good Guardband Timer for Host CPU
- ***************************************************************************/
-/* AON_CTRL :: PM_CPU_GUARDBAND_TIMER :: reserved0 [31:10] */
-#define BCHP_AON_CTRL_PM_CPU_GUARDBAND_TIMER_reserved0_MASK 0xfffffc00
-#define BCHP_AON_CTRL_PM_CPU_GUARDBAND_TIMER_reserved0_SHIFT 10
-
-/* AON_CTRL :: PM_CPU_GUARDBAND_TIMER :: counter_start_value [09:00] */
-#define BCHP_AON_CTRL_PM_CPU_GUARDBAND_TIMER_counter_start_value_MASK 0x000003ff
-#define BCHP_AON_CTRL_PM_CPU_GUARDBAND_TIMER_counter_start_value_SHIFT 0
-#define BCHP_AON_CTRL_PM_CPU_GUARDBAND_TIMER_counter_start_value_DEFAULT 0x0000007f
-
-/***************************************************************************
- *PM_S3_STANDBY_TIMER - Deep Standby Assertion Timer
- ***************************************************************************/
-/* AON_CTRL :: PM_S3_STANDBY_TIMER :: reserved0 [31:27] */
-#define BCHP_AON_CTRL_PM_S3_STANDBY_TIMER_reserved0_MASK 0xf8000000
-#define BCHP_AON_CTRL_PM_S3_STANDBY_TIMER_reserved0_SHIFT 27
-
-/* AON_CTRL :: PM_S3_STANDBY_TIMER :: counter_start_value [26:00] */
-#define BCHP_AON_CTRL_PM_S3_STANDBY_TIMER_counter_start_value_MASK 0x07ffffff
-#define BCHP_AON_CTRL_PM_S3_STANDBY_TIMER_counter_start_value_SHIFT 0
-#define BCHP_AON_CTRL_PM_S3_STANDBY_TIMER_counter_start_value_DEFAULT 0x002932e0
-
-/***************************************************************************
- *PM_S3_WAKEUP_TIMER - Deep Standby Wakeup Timer
- ***************************************************************************/
-/* AON_CTRL :: PM_S3_WAKEUP_TIMER :: reserved0 [31:27] */
-#define BCHP_AON_CTRL_PM_S3_WAKEUP_TIMER_reserved0_MASK 0xf8000000
-#define BCHP_AON_CTRL_PM_S3_WAKEUP_TIMER_reserved0_SHIFT 27
-
-/* AON_CTRL :: PM_S3_WAKEUP_TIMER :: counter_start_value [26:00] */
-#define BCHP_AON_CTRL_PM_S3_WAKEUP_TIMER_counter_start_value_MASK 0x07ffffff
-#define BCHP_AON_CTRL_PM_S3_WAKEUP_TIMER_counter_start_value_SHIFT 0
-#define BCHP_AON_CTRL_PM_S3_WAKEUP_TIMER_counter_start_value_DEFAULT 0x00107ac0
-
-/***************************************************************************
- *PM_FAST_PWRDN_PRECHARGE - Control register for Power Controller
- ***************************************************************************/
-/* AON_CTRL :: PM_FAST_PWRDN_PRECHARGE :: reserved0 [31:24] */
-#define BCHP_AON_CTRL_PM_FAST_PWRDN_PRECHARGE_reserved0_MASK 0xff000000
-#define BCHP_AON_CTRL_PM_FAST_PWRDN_PRECHARGE_reserved0_SHIFT 24
-
-/* AON_CTRL :: PM_FAST_PWRDN_PRECHARGE :: pm_fast_power_down_precharge [23:00] */
-#define BCHP_AON_CTRL_PM_FAST_PWRDN_PRECHARGE_pm_fast_power_down_precharge_MASK 0x00ffffff
-#define BCHP_AON_CTRL_PM_FAST_PWRDN_PRECHARGE_pm_fast_power_down_precharge_SHIFT 0
-#define BCHP_AON_CTRL_PM_FAST_PWRDN_PRECHARGE_pm_fast_power_down_precharge_DEFAULT 0x00000000
-
-/***************************************************************************
- *PM_LED_CTRL - LED set control register
- ***************************************************************************/
-/* AON_CTRL :: PM_LED_CTRL :: reserved0 [31:03] */
-#define BCHP_AON_CTRL_PM_LED_CTRL_reserved0_MASK 0xfffffff8
-#define BCHP_AON_CTRL_PM_LED_CTRL_reserved0_SHIFT 3
-
-/* AON_CTRL :: PM_LED_CTRL :: led_status [02:02] */
-#define BCHP_AON_CTRL_PM_LED_CTRL_led_status_MASK 0x00000004
-#define BCHP_AON_CTRL_PM_LED_CTRL_led_status_SHIFT 2
-
-/* AON_CTRL :: PM_LED_CTRL :: led_turn_on [01:01] */
-#define BCHP_AON_CTRL_PM_LED_CTRL_led_turn_on_MASK 0x00000002
-#define BCHP_AON_CTRL_PM_LED_CTRL_led_turn_on_SHIFT 1
-
-/* AON_CTRL :: PM_LED_CTRL :: led_turn_off [00:00] */
-#define BCHP_AON_CTRL_PM_LED_CTRL_led_turn_off_MASK 0x00000001
-#define BCHP_AON_CTRL_PM_LED_CTRL_led_turn_off_SHIFT 0
-
-/***************************************************************************
- *PM_LED_AUTO_ON_ENABLES - LED set control register
- ***************************************************************************/
-/* AON_CTRL :: PM_LED_AUTO_ON_ENABLES :: led_status [31:00] */
-#define BCHP_AON_CTRL_PM_LED_AUTO_ON_ENABLES_led_status_MASK 0xffffffff
-#define BCHP_AON_CTRL_PM_LED_AUTO_ON_ENABLES_led_status_SHIFT 0
-#define BCHP_AON_CTRL_PM_LED_AUTO_ON_ENABLES_led_status_DEFAULT 0x00000000
-
-/***************************************************************************
- *HLCD_CTRL - HW LED Clock Driver Control
- ***************************************************************************/
-/* AON_CTRL :: HLCD_CTRL :: reserved0 [31:02] */
-#define BCHP_AON_CTRL_HLCD_CTRL_reserved0_MASK 0xfffffffc
-#define BCHP_AON_CTRL_HLCD_CTRL_reserved0_SHIFT 2
-
-/* AON_CTRL :: HLCD_CTRL :: hlcd_enable_status [01:01] */
-#define BCHP_AON_CTRL_HLCD_CTRL_hlcd_enable_status_MASK 0x00000002
-#define BCHP_AON_CTRL_HLCD_CTRL_hlcd_enable_status_SHIFT 1
-
-/* AON_CTRL :: HLCD_CTRL :: hlcd_enable [00:00] */
-#define BCHP_AON_CTRL_HLCD_CTRL_hlcd_enable_MASK 0x00000001
-#define BCHP_AON_CTRL_HLCD_CTRL_hlcd_enable_SHIFT 0
-#define BCHP_AON_CTRL_HLCD_CTRL_hlcd_enable_DEFAULT 0x00000000
-
-/***************************************************************************
- *SECOND_FRACTION_COUNTER - Second Fraction Counter Initial value
- ***************************************************************************/
-/* AON_CTRL :: SECOND_FRACTION_COUNTER :: reserved0 [31:25] */
-#define BCHP_AON_CTRL_SECOND_FRACTION_COUNTER_reserved0_MASK 0xfe000000
-#define BCHP_AON_CTRL_SECOND_FRACTION_COUNTER_reserved0_SHIFT 25
-
-/* AON_CTRL :: SECOND_FRACTION_COUNTER :: second_fraction_counter_init [24:00] */
-#define BCHP_AON_CTRL_SECOND_FRACTION_COUNTER_second_fraction_counter_init_MASK 0x01ffffff
-#define BCHP_AON_CTRL_SECOND_FRACTION_COUNTER_second_fraction_counter_init_SHIFT 0
-#define BCHP_AON_CTRL_SECOND_FRACTION_COUNTER_second_fraction_counter_init_DEFAULT 0x00000000
-
-/***************************************************************************
- *TIME_COUNTER - Hour/Minute Counter Initial value
- ***************************************************************************/
-/* AON_CTRL :: TIME_COUNTER :: reserved0 [31:20] */
-#define BCHP_AON_CTRL_TIME_COUNTER_reserved0_MASK 0xfff00000
-#define BCHP_AON_CTRL_TIME_COUNTER_reserved0_SHIFT 20
-
-/* AON_CTRL :: TIME_COUNTER :: hour_display_mode [19:19] */
-#define BCHP_AON_CTRL_TIME_COUNTER_hour_display_mode_MASK 0x00080000
-#define BCHP_AON_CTRL_TIME_COUNTER_hour_display_mode_SHIFT 19
-#define BCHP_AON_CTRL_TIME_COUNTER_hour_display_mode_DEFAULT 0x00000000
-
-/* AON_CTRL :: TIME_COUNTER :: mode_12h_24h_init [18:18] */
-#define BCHP_AON_CTRL_TIME_COUNTER_mode_12h_24h_init_MASK 0x00040000
-#define BCHP_AON_CTRL_TIME_COUNTER_mode_12h_24h_init_SHIFT 18
-#define BCHP_AON_CTRL_TIME_COUNTER_mode_12h_24h_init_DEFAULT 0x00000000
-
-/* AON_CTRL :: TIME_COUNTER :: am_pm_counter_init [17:17] */
-#define BCHP_AON_CTRL_TIME_COUNTER_am_pm_counter_init_MASK 0x00020000
-#define BCHP_AON_CTRL_TIME_COUNTER_am_pm_counter_init_SHIFT 17
-#define BCHP_AON_CTRL_TIME_COUNTER_am_pm_counter_init_DEFAULT 0x00000000
-
-/* AON_CTRL :: TIME_COUNTER :: hour_counter_init [16:12] */
-#define BCHP_AON_CTRL_TIME_COUNTER_hour_counter_init_MASK 0x0001f000
-#define BCHP_AON_CTRL_TIME_COUNTER_hour_counter_init_SHIFT 12
-#define BCHP_AON_CTRL_TIME_COUNTER_hour_counter_init_DEFAULT 0x00000000
-
-/* AON_CTRL :: TIME_COUNTER :: minute_counter_init [11:06] */
-#define BCHP_AON_CTRL_TIME_COUNTER_minute_counter_init_MASK 0x00000fc0
-#define BCHP_AON_CTRL_TIME_COUNTER_minute_counter_init_SHIFT 6
-#define BCHP_AON_CTRL_TIME_COUNTER_minute_counter_init_DEFAULT 0x00000000
-
-/* AON_CTRL :: TIME_COUNTER :: second_counter_init [05:00] */
-#define BCHP_AON_CTRL_TIME_COUNTER_second_counter_init_MASK 0x0000003f
-#define BCHP_AON_CTRL_TIME_COUNTER_second_counter_init_SHIFT 0
-#define BCHP_AON_CTRL_TIME_COUNTER_second_counter_init_DEFAULT 0x00000000
-
-/***************************************************************************
- *LED_DIGIT_CODE_0 - Digit Code for digit 0, 1, 2, 3
- ***************************************************************************/
-/* AON_CTRL :: LED_DIGIT_CODE_0 :: digit_code_3 [31:24] */
-#define BCHP_AON_CTRL_LED_DIGIT_CODE_0_digit_code_3_MASK 0xff000000
-#define BCHP_AON_CTRL_LED_DIGIT_CODE_0_digit_code_3_SHIFT 24
-#define BCHP_AON_CTRL_LED_DIGIT_CODE_0_digit_code_3_DEFAULT 0x00000000
-
-/* AON_CTRL :: LED_DIGIT_CODE_0 :: digit_code_2 [23:16] */
-#define BCHP_AON_CTRL_LED_DIGIT_CODE_0_digit_code_2_MASK 0x00ff0000
-#define BCHP_AON_CTRL_LED_DIGIT_CODE_0_digit_code_2_SHIFT 16
-#define BCHP_AON_CTRL_LED_DIGIT_CODE_0_digit_code_2_DEFAULT 0x00000000
-
-/* AON_CTRL :: LED_DIGIT_CODE_0 :: digit_code_1 [15:08] */
-#define BCHP_AON_CTRL_LED_DIGIT_CODE_0_digit_code_1_MASK 0x0000ff00
-#define BCHP_AON_CTRL_LED_DIGIT_CODE_0_digit_code_1_SHIFT 8
-#define BCHP_AON_CTRL_LED_DIGIT_CODE_0_digit_code_1_DEFAULT 0x00000000
-
-/* AON_CTRL :: LED_DIGIT_CODE_0 :: digit_code_0 [07:00] */
-#define BCHP_AON_CTRL_LED_DIGIT_CODE_0_digit_code_0_MASK 0x000000ff
-#define BCHP_AON_CTRL_LED_DIGIT_CODE_0_digit_code_0_SHIFT 0
-#define BCHP_AON_CTRL_LED_DIGIT_CODE_0_digit_code_0_DEFAULT 0x00000000
-
-/***************************************************************************
- *LED_DIGIT_CODE_1 - Digit Code for digit 4, 5, 6, 7
- ***************************************************************************/
-/* AON_CTRL :: LED_DIGIT_CODE_1 :: digit_code_7 [31:24] */
-#define BCHP_AON_CTRL_LED_DIGIT_CODE_1_digit_code_7_MASK 0xff000000
-#define BCHP_AON_CTRL_LED_DIGIT_CODE_1_digit_code_7_SHIFT 24
-#define BCHP_AON_CTRL_LED_DIGIT_CODE_1_digit_code_7_DEFAULT 0x00000000
-
-/* AON_CTRL :: LED_DIGIT_CODE_1 :: digit_code_6 [23:16] */
-#define BCHP_AON_CTRL_LED_DIGIT_CODE_1_digit_code_6_MASK 0x00ff0000
-#define BCHP_AON_CTRL_LED_DIGIT_CODE_1_digit_code_6_SHIFT 16
-#define BCHP_AON_CTRL_LED_DIGIT_CODE_1_digit_code_6_DEFAULT 0x00000000
-
-/* AON_CTRL :: LED_DIGIT_CODE_1 :: digit_code_5 [15:08] */
-#define BCHP_AON_CTRL_LED_DIGIT_CODE_1_digit_code_5_MASK 0x0000ff00
-#define BCHP_AON_CTRL_LED_DIGIT_CODE_1_digit_code_5_SHIFT 8
-#define BCHP_AON_CTRL_LED_DIGIT_CODE_1_digit_code_5_DEFAULT 0x00000000
-
-/* AON_CTRL :: LED_DIGIT_CODE_1 :: digit_code_4 [07:00] */
-#define BCHP_AON_CTRL_LED_DIGIT_CODE_1_digit_code_4_MASK 0x000000ff
-#define BCHP_AON_CTRL_LED_DIGIT_CODE_1_digit_code_4_SHIFT 0
-#define BCHP_AON_CTRL_LED_DIGIT_CODE_1_digit_code_4_DEFAULT 0x00000000
-
-/***************************************************************************
- *LED_DIGIT_CODE_2 - Digit Code for digit 8, 9
- ***************************************************************************/
-/* AON_CTRL :: LED_DIGIT_CODE_2 :: reserved0 [31:16] */
-#define BCHP_AON_CTRL_LED_DIGIT_CODE_2_reserved0_MASK 0xffff0000
-#define BCHP_AON_CTRL_LED_DIGIT_CODE_2_reserved0_SHIFT 16
-
-/* AON_CTRL :: LED_DIGIT_CODE_2 :: digit_code_9 [15:08] */
-#define BCHP_AON_CTRL_LED_DIGIT_CODE_2_digit_code_9_MASK 0x0000ff00
-#define BCHP_AON_CTRL_LED_DIGIT_CODE_2_digit_code_9_SHIFT 8
-#define BCHP_AON_CTRL_LED_DIGIT_CODE_2_digit_code_9_DEFAULT 0x00000000
-
-/* AON_CTRL :: LED_DIGIT_CODE_2 :: digit_code_8 [07:00] */
-#define BCHP_AON_CTRL_LED_DIGIT_CODE_2_digit_code_8_MASK 0x000000ff
-#define BCHP_AON_CTRL_LED_DIGIT_CODE_2_digit_code_8_SHIFT 0
-#define BCHP_AON_CTRL_LED_DIGIT_CODE_2_digit_code_8_DEFAULT 0x00000000
-
-/***************************************************************************
- *LED_DIGIT_ADDR_OFFSET - Hour MSD/LSD and minute MSD/LSD address offset
- ***************************************************************************/
-/* AON_CTRL :: LED_DIGIT_ADDR_OFFSET :: hour_msd_addr_offset [31:24] */
-#define BCHP_AON_CTRL_LED_DIGIT_ADDR_OFFSET_hour_msd_addr_offset_MASK 0xff000000
-#define BCHP_AON_CTRL_LED_DIGIT_ADDR_OFFSET_hour_msd_addr_offset_SHIFT 24
-#define BCHP_AON_CTRL_LED_DIGIT_ADDR_OFFSET_hour_msd_addr_offset_DEFAULT 0x00000020
-
-/* AON_CTRL :: LED_DIGIT_ADDR_OFFSET :: hour_lsd_addr_offset [23:16] */
-#define BCHP_AON_CTRL_LED_DIGIT_ADDR_OFFSET_hour_lsd_addr_offset_MASK 0x00ff0000
-#define BCHP_AON_CTRL_LED_DIGIT_ADDR_OFFSET_hour_lsd_addr_offset_SHIFT 16
-#define BCHP_AON_CTRL_LED_DIGIT_ADDR_OFFSET_hour_lsd_addr_offset_DEFAULT 0x00000024
-
-/* AON_CTRL :: LED_DIGIT_ADDR_OFFSET :: minute_msd_addr_offset [15:08] */
-#define BCHP_AON_CTRL_LED_DIGIT_ADDR_OFFSET_minute_msd_addr_offset_MASK 0x0000ff00
-#define BCHP_AON_CTRL_LED_DIGIT_ADDR_OFFSET_minute_msd_addr_offset_SHIFT 8
-#define BCHP_AON_CTRL_LED_DIGIT_ADDR_OFFSET_minute_msd_addr_offset_DEFAULT 0x00000018
-
-/* AON_CTRL :: LED_DIGIT_ADDR_OFFSET :: minute_lsd_addr_offset [07:00] */
-#define BCHP_AON_CTRL_LED_DIGIT_ADDR_OFFSET_minute_lsd_addr_offset_MASK 0x000000ff
-#define BCHP_AON_CTRL_LED_DIGIT_ADDR_OFFSET_minute_lsd_addr_offset_SHIFT 0
-#define BCHP_AON_CTRL_LED_DIGIT_ADDR_OFFSET_minute_lsd_addr_offset_DEFAULT 0x0000001c
-
-/***************************************************************************
- *LED_STATUS_CTRL - LED status control
- ***************************************************************************/
-/* AON_CTRL :: LED_STATUS_CTRL :: reserved0 [31:28] */
-#define BCHP_AON_CTRL_LED_STATUS_CTRL_reserved0_MASK 0xf0000000
-#define BCHP_AON_CTRL_LED_STATUS_CTRL_reserved0_SHIFT 28
-
-/* AON_CTRL :: LED_STATUS_CTRL :: hlcd_state [27:25] */
-#define BCHP_AON_CTRL_LED_STATUS_CTRL_hlcd_state_MASK 0x0e000000
-#define BCHP_AON_CTRL_LED_STATUS_CTRL_hlcd_state_SHIFT 25
-#define BCHP_AON_CTRL_LED_STATUS_CTRL_hlcd_state_HLCD_IDLE 0
-#define BCHP_AON_CTRL_LED_STATUS_CTRL_hlcd_state_HLCD_COUNT 1
-#define BCHP_AON_CTRL_LED_STATUS_CTRL_hlcd_state_HLCD_PROGRAM_MINUTE_LSD 2
-#define BCHP_AON_CTRL_LED_STATUS_CTRL_hlcd_state_HLCD_PROGRAM_MINUTE_MSD 3
-#define BCHP_AON_CTRL_LED_STATUS_CTRL_hlcd_state_HLCD_PROGRAM_HOUR_LSD 4
-#define BCHP_AON_CTRL_LED_STATUS_CTRL_hlcd_state_HLCD_PROGRAM_HOUR_MSD 5
-#define BCHP_AON_CTRL_LED_STATUS_CTRL_hlcd_state_HLCD_PROGRAM_STATUS 6
-
-/* AON_CTRL :: LED_STATUS_CTRL :: status_update_enable [24:24] */
-#define BCHP_AON_CTRL_LED_STATUS_CTRL_status_update_enable_MASK 0x01000000
-#define BCHP_AON_CTRL_LED_STATUS_CTRL_status_update_enable_SHIFT 24
-#define BCHP_AON_CTRL_LED_STATUS_CTRL_status_update_enable_DEFAULT 0x00000000
-
-/* AON_CTRL :: LED_STATUS_CTRL :: status_mask [23:12] */
-#define BCHP_AON_CTRL_LED_STATUS_CTRL_status_mask_MASK 0x00fff000
-#define BCHP_AON_CTRL_LED_STATUS_CTRL_status_mask_SHIFT 12
-#define BCHP_AON_CTRL_LED_STATUS_CTRL_status_mask_DEFAULT 0x00000000
-
-/* AON_CTRL :: LED_STATUS_CTRL :: status_bit_offset [11:08] */
-#define BCHP_AON_CTRL_LED_STATUS_CTRL_status_bit_offset_MASK 0x00000f00
-#define BCHP_AON_CTRL_LED_STATUS_CTRL_status_bit_offset_SHIFT 8
-#define BCHP_AON_CTRL_LED_STATUS_CTRL_status_bit_offset_DEFAULT 0x00000000
-
-/* AON_CTRL :: LED_STATUS_CTRL :: status_addr_offset [07:00] */
-#define BCHP_AON_CTRL_LED_STATUS_CTRL_status_addr_offset_MASK 0x000000ff
-#define BCHP_AON_CTRL_LED_STATUS_CTRL_status_addr_offset_SHIFT 0
-#define BCHP_AON_CTRL_LED_STATUS_CTRL_status_addr_offset_DEFAULT 0x00000000
-
-/***************************************************************************
- *GENERAL_CTRL_0 - General control register 0
- ***************************************************************************/
-/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_31 [31:31] */
-#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_31_MASK 0x80000000
-#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_31_SHIFT 31
-#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_31_DEFAULT 0x00000001
-
-/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_30 [30:30] */
-#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_30_MASK 0x40000000
-#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_30_SHIFT 30
-#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_30_DEFAULT 0x00000001
-
-/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_29 [29:29] */
-#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_29_MASK 0x20000000
-#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_29_SHIFT 29
-#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_29_DEFAULT 0x00000001
-
-/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_28 [28:28] */
-#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_28_MASK 0x10000000
-#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_28_SHIFT 28
-#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_28_DEFAULT 0x00000001
-
-/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_27 [27:27] */
-#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_27_MASK 0x08000000
-#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_27_SHIFT 27
-#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_27_DEFAULT 0x00000001
-
-/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_26 [26:26] */
-#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_26_MASK 0x04000000
-#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_26_SHIFT 26
-#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_26_DEFAULT 0x00000001
-
-/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_25 [25:25] */
-#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_25_MASK 0x02000000
-#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_25_SHIFT 25
-#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_25_DEFAULT 0x00000001
-
-/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_24 [24:24] */
-#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_24_MASK 0x01000000
-#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_24_SHIFT 24
-#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_24_DEFAULT 0x00000001
-
-/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_23 [23:23] */
-#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_23_MASK 0x00800000
-#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_23_SHIFT 23
-#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_23_DEFAULT 0x00000001
-
-/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_22 [22:22] */
-#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_22_MASK 0x00400000
-#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_22_SHIFT 22
-#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_22_DEFAULT 0x00000001
-
-/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_21 [21:21] */
-#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_21_MASK 0x00200000
-#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_21_SHIFT 21
-#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_21_DEFAULT 0x00000001
-
-/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_20 [20:20] */
-#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_20_MASK 0x00100000
-#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_20_SHIFT 20
-#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_20_DEFAULT 0x00000001
-
-/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_19 [19:19] */
-#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_19_MASK 0x00080000
-#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_19_SHIFT 19
-#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_19_DEFAULT 0x00000001
-
-/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_18 [18:18] */
-#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_18_MASK 0x00040000
-#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_18_SHIFT 18
-#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_18_DEFAULT 0x00000001
-
-/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_17 [17:17] */
-#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_17_MASK 0x00020000
-#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_17_SHIFT 17
-#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_17_DEFAULT 0x00000001
-
-/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_16 [16:16] */
-#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_16_MASK 0x00010000
-#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_16_SHIFT 16
-#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_16_DEFAULT 0x00000001
-
-/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_15 [15:15] */
-#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_15_MASK 0x00008000
-#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_15_SHIFT 15
-#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_15_DEFAULT 0x00000000
-
-/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_14 [14:14] */
-#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_14_MASK 0x00004000
-#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_14_SHIFT 14
-#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_14_DEFAULT 0x00000000
-
-/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_13 [13:13] */
-#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_13_MASK 0x00002000
-#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_13_SHIFT 13
-#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_13_DEFAULT 0x00000000
-
-/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_12 [12:12] */
-#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_12_MASK 0x00001000
-#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_12_SHIFT 12
-#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_12_DEFAULT 0x00000000
-
-/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_11 [11:11] */
-#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_11_MASK 0x00000800
-#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_11_SHIFT 11
-#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_11_DEFAULT 0x00000000
-
-/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_10 [10:10] */
-#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_10_MASK 0x00000400
-#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_10_SHIFT 10
-#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_10_DEFAULT 0x00000000
-
-/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_9 [09:09] */
-#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_9_MASK 0x00000200
-#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_9_SHIFT 9
-#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_9_DEFAULT 0x00000000
-
-/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_8 [08:08] */
-#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_8_MASK 0x00000100
-#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_8_SHIFT 8
-#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_8_DEFAULT 0x00000000
-
-/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_7 [07:07] */
-#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_7_MASK 0x00000080
-#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_7_SHIFT 7
-#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_7_DEFAULT 0x00000000
-
-/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_6 [06:06] */
-#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_6_MASK 0x00000040
-#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_6_SHIFT 6
-#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_6_DEFAULT 0x00000000
-
-/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_5 [05:05] */
-#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_5_MASK 0x00000020
-#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_5_SHIFT 5
-#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_5_DEFAULT 0x00000000
-
-/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_4 [04:04] */
-#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_4_MASK 0x00000010
-#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_4_SHIFT 4
-#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_4_DEFAULT 0x00000000
-
-/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_3 [03:03] */
-#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_3_MASK 0x00000008
-#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_3_SHIFT 3
-#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_3_DEFAULT 0x00000000
-
-/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_2 [02:02] */
-#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_2_MASK 0x00000004
-#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_2_SHIFT 2
-#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_2_DEFAULT 0x00000000
-
-/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_1 [01:01] */
-#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_1_MASK 0x00000002
-#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_1_SHIFT 1
-#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_1_DEFAULT 0x00000000
-
-/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_0 [00:00] */
-#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_0_MASK 0x00000001
-#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_0_SHIFT 0
-#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_0_DEFAULT 0x00000000
-
-/***************************************************************************
- *GENERAL_STATUS_0 - General status register 0
- ***************************************************************************/
-/* AON_CTRL :: GENERAL_STATUS_0 :: reserved0 [31:08] */
-#define BCHP_AON_CTRL_GENERAL_STATUS_0_reserved0_MASK 0xffffff00
-#define BCHP_AON_CTRL_GENERAL_STATUS_0_reserved0_SHIFT 8
-
-/* AON_CTRL :: GENERAL_STATUS_0 :: general_status0_7 [07:07] */
-#define BCHP_AON_CTRL_GENERAL_STATUS_0_general_status0_7_MASK 0x00000080
-#define BCHP_AON_CTRL_GENERAL_STATUS_0_general_status0_7_SHIFT 7
-
-/* AON_CTRL :: GENERAL_STATUS_0 :: general_status0_6 [06:06] */
-#define BCHP_AON_CTRL_GENERAL_STATUS_0_general_status0_6_MASK 0x00000040
-#define BCHP_AON_CTRL_GENERAL_STATUS_0_general_status0_6_SHIFT 6
-
-/* AON_CTRL :: GENERAL_STATUS_0 :: general_status0_5 [05:05] */
-#define BCHP_AON_CTRL_GENERAL_STATUS_0_general_status0_5_MASK 0x00000020
-#define BCHP_AON_CTRL_GENERAL_STATUS_0_general_status0_5_SHIFT 5
-
-/* AON_CTRL :: GENERAL_STATUS_0 :: general_status0_4 [04:04] */
-#define BCHP_AON_CTRL_GENERAL_STATUS_0_general_status0_4_MASK 0x00000010
-#define BCHP_AON_CTRL_GENERAL_STATUS_0_general_status0_4_SHIFT 4
-
-/* AON_CTRL :: GENERAL_STATUS_0 :: general_status0_3 [03:03] */
-#define BCHP_AON_CTRL_GENERAL_STATUS_0_general_status0_3_MASK 0x00000008
-#define BCHP_AON_CTRL_GENERAL_STATUS_0_general_status0_3_SHIFT 3
-
-/* AON_CTRL :: GENERAL_STATUS_0 :: general_status0_2 [02:02] */
-#define BCHP_AON_CTRL_GENERAL_STATUS_0_general_status0_2_MASK 0x00000004
-#define BCHP_AON_CTRL_GENERAL_STATUS_0_general_status0_2_SHIFT 2
-
-/* AON_CTRL :: GENERAL_STATUS_0 :: general_status0_1 [01:01] */
-#define BCHP_AON_CTRL_GENERAL_STATUS_0_general_status0_1_MASK 0x00000002
-#define BCHP_AON_CTRL_GENERAL_STATUS_0_general_status0_1_SHIFT 1
-
-/* AON_CTRL :: GENERAL_STATUS_0 :: ejtag_ce_wakeup_event [00:00] */
-#define BCHP_AON_CTRL_GENERAL_STATUS_0_ejtag_ce_wakeup_event_MASK 0x00000001
-#define BCHP_AON_CTRL_GENERAL_STATUS_0_ejtag_ce_wakeup_event_SHIFT 0
-
-/***************************************************************************
- *GENERAL_CTRL_NO_SCAN_0 - General control register without scan 0
- ***************************************************************************/
-/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_31 [31:31] */
-#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_31_MASK 0x80000000
-#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_31_SHIFT 31
-#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_31_DEFAULT 0x00000001
-
-/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_30 [30:30] */
-#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_30_MASK 0x40000000
-#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_30_SHIFT 30
-#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_30_DEFAULT 0x00000001
-
-/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_29 [29:29] */
-#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_29_MASK 0x20000000
-#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_29_SHIFT 29
-#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_29_DEFAULT 0x00000001
-
-/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_28 [28:28] */
-#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_28_MASK 0x10000000
-#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_28_SHIFT 28
-#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_28_DEFAULT 0x00000001
-
-/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_27 [27:27] */
-#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_27_MASK 0x08000000
-#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_27_SHIFT 27
-#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_27_DEFAULT 0x00000001
-
-/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_26 [26:26] */
-#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_26_MASK 0x04000000
-#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_26_SHIFT 26
-#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_26_DEFAULT 0x00000001
-
-/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_25 [25:25] */
-#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_25_MASK 0x02000000
-#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_25_SHIFT 25
-#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_25_DEFAULT 0x00000001
-
-/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_24 [24:24] */
-#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_24_MASK 0x01000000
-#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_24_SHIFT 24
-#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_24_DEFAULT 0x00000001
-
-/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_23 [23:23] */
-#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_23_MASK 0x00800000
-#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_23_SHIFT 23
-#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_23_DEFAULT 0x00000001
-
-/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_22 [22:22] */
-#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_22_MASK 0x00400000
-#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_22_SHIFT 22
-#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_22_DEFAULT 0x00000001
-
-/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_21 [21:21] */
-#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_21_MASK 0x00200000
-#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_21_SHIFT 21
-#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_21_DEFAULT 0x00000001
-
-/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_20 [20:20] */
-#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_20_MASK 0x00100000
-#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_20_SHIFT 20
-#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_20_DEFAULT 0x00000001
-
-/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_19 [19:19] */
-#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_19_MASK 0x00080000
-#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_19_SHIFT 19
-#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_19_DEFAULT 0x00000001
-
-/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_18 [18:18] */
-#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_18_MASK 0x00040000
-#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_18_SHIFT 18
-#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_18_DEFAULT 0x00000001
-
-/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_17 [17:17] */
-#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_17_MASK 0x00020000
-#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_17_SHIFT 17
-#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_17_DEFAULT 0x00000001
-
-/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_16 [16:16] */
-#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_16_MASK 0x00010000
-#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_16_SHIFT 16
-#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_16_DEFAULT 0x00000001
-
-/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_15 [15:15] */
-#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_15_MASK 0x00008000
-#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_15_SHIFT 15
-#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_15_DEFAULT 0x00000000
-
-/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_14 [14:14] */
-#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_14_MASK 0x00004000
-#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_14_SHIFT 14
-#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_14_DEFAULT 0x00000000
-
-/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_13 [13:13] */
-#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_13_MASK 0x00002000
-#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_13_SHIFT 13
-#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_13_DEFAULT 0x00000000
-
-/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_12 [12:12] */
-#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_12_MASK 0x00001000
-#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_12_SHIFT 12
-#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_12_DEFAULT 0x00000000
-
-/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_11 [11:11] */
-#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_11_MASK 0x00000800
-#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_11_SHIFT 11
-#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_11_DEFAULT 0x00000000
-
-/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_10 [10:10] */
-#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_10_MASK 0x00000400
-#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_10_SHIFT 10
-#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_10_DEFAULT 0x00000000
-
-/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_9 [09:09] */
-#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_9_MASK 0x00000200
-#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_9_SHIFT 9
-#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_9_DEFAULT 0x00000000
-
-/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_8 [08:08] */
-#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_8_MASK 0x00000100
-#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_8_SHIFT 8
-#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_8_DEFAULT 0x00000000
-
-/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_7 [07:07] */
-#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_7_MASK 0x00000080
-#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_7_SHIFT 7
-#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_7_DEFAULT 0x00000000
-
-/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_6 [06:06] */
-#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_6_MASK 0x00000040
-#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_6_SHIFT 6
-#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_6_DEFAULT 0x00000000
-
-/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_5 [05:05] */
-#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_5_MASK 0x00000020
-#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_5_SHIFT 5
-#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_5_DEFAULT 0x00000000
-
-/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_4 [04:04] */
-#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_4_MASK 0x00000010
-#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_4_SHIFT 4
-#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_4_DEFAULT 0x00000000
-
-/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_3 [03:03] */
-#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_3_MASK 0x00000008
-#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_3_SHIFT 3
-#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_3_DEFAULT 0x00000000
-
-/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_2 [02:02] */
-#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_2_MASK 0x00000004
-#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_2_SHIFT 2
-#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_2_DEFAULT 0x00000000
-
-/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_1 [01:01] */
-#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_1_MASK 0x00000002
-#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_1_SHIFT 1
-#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_1_DEFAULT 0x00000000
-
-/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_0 [00:00] */
-#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_0_MASK 0x00000001
-#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_0_SHIFT 0
-#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_0_DEFAULT 0x00000000
-
-/***************************************************************************
- *SPARE_CTRL_0 - Spare control bits reserved for future use
- ***************************************************************************/
-/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_31 [31:31] */
-#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_31_MASK 0x80000000
-#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_31_SHIFT 31
-#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_31_DEFAULT 0x00000001
-
-/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_30 [30:30] */
-#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_30_MASK 0x40000000
-#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_30_SHIFT 30
-#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_30_DEFAULT 0x00000001
-
-/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_29 [29:29] */
-#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_29_MASK 0x20000000
-#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_29_SHIFT 29
-#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_29_DEFAULT 0x00000001
-
-/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_28 [28:28] */
-#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_28_MASK 0x10000000
-#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_28_SHIFT 28
-#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_28_DEFAULT 0x00000001
-
-/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_27 [27:27] */
-#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_27_MASK 0x08000000
-#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_27_SHIFT 27
-#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_27_DEFAULT 0x00000001
-
-/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_26 [26:26] */
-#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_26_MASK 0x04000000
-#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_26_SHIFT 26
-#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_26_DEFAULT 0x00000001
-
-/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_25 [25:25] */
-#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_25_MASK 0x02000000
-#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_25_SHIFT 25
-#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_25_DEFAULT 0x00000001
-
-/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_24 [24:24] */
-#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_24_MASK 0x01000000
-#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_24_SHIFT 24
-#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_24_DEFAULT 0x00000001
-
-/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_23 [23:23] */
-#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_23_MASK 0x00800000
-#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_23_SHIFT 23
-#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_23_DEFAULT 0x00000000
-
-/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_22 [22:22] */
-#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_22_MASK 0x00400000
-#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_22_SHIFT 22
-#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_22_DEFAULT 0x00000000
-
-/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_21 [21:21] */
-#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_21_MASK 0x00200000
-#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_21_SHIFT 21
-#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_21_DEFAULT 0x00000000
-
-/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_20 [20:20] */
-#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_20_MASK 0x00100000
-#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_20_SHIFT 20
-#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_20_DEFAULT 0x00000000
-
-/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_19 [19:19] */
-#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_19_MASK 0x00080000
-#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_19_SHIFT 19
-#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_19_DEFAULT 0x00000000
-
-/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_18 [18:18] */
-#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_18_MASK 0x00040000
-#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_18_SHIFT 18
-#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_18_DEFAULT 0x00000000
-
-/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_17 [17:17] */
-#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_17_MASK 0x00020000
-#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_17_SHIFT 17
-#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_17_DEFAULT 0x00000000
-
-/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_16 [16:16] */
-#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_16_MASK 0x00010000
-#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_16_SHIFT 16
-#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_16_DEFAULT 0x00000000
-
-/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_15 [15:15] */
-#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_15_MASK 0x00008000
-#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_15_SHIFT 15
-#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_15_DEFAULT 0x00000000
-
-/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_14 [14:14] */
-#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_14_MASK 0x00004000
-#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_14_SHIFT 14
-#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_14_DEFAULT 0x00000000
-
-/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_13 [13:13] */
-#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_13_MASK 0x00002000
-#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_13_SHIFT 13
-#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_13_DEFAULT 0x00000000
-
-/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_12 [12:12] */
-#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_12_MASK 0x00001000
-#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_12_SHIFT 12
-#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_12_DEFAULT 0x00000000
-
-/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_11 [11:11] */
-#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_11_MASK 0x00000800
-#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_11_SHIFT 11
-#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_11_DEFAULT 0x00000000
-
-/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_10 [10:10] */
-#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_10_MASK 0x00000400
-#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_10_SHIFT 10
-#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_10_DEFAULT 0x00000000
-
-/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_09 [09:09] */
-#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_09_MASK 0x00000200
-#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_09_SHIFT 9
-#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_09_DEFAULT 0x00000000
-
-/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_08 [08:08] */
-#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_08_MASK 0x00000100
-#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_08_SHIFT 8
-#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_08_DEFAULT 0x00000000
-
-/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_07 [07:07] */
-#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_07_MASK 0x00000080
-#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_07_SHIFT 7
-#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_07_DEFAULT 0x00000000
-
-/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_06 [06:06] */
-#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_06_MASK 0x00000040
-#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_06_SHIFT 6
-#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_06_DEFAULT 0x00000000
-
-/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_05 [05:05] */
-#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_05_MASK 0x00000020
-#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_05_SHIFT 5
-#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_05_DEFAULT 0x00000000
-
-/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_04 [04:04] */
-#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_04_MASK 0x00000010
-#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_04_SHIFT 4
-#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_04_DEFAULT 0x00000000
-
-/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_03 [03:03] */
-#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_03_MASK 0x00000008
-#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_03_SHIFT 3
-#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_03_DEFAULT 0x00000000
-
-/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_02 [02:02] */
-#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_02_MASK 0x00000004
-#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_02_SHIFT 2
-#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_02_DEFAULT 0x00000000
-
-/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_01 [01:01] */
-#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_01_MASK 0x00000002
-#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_01_SHIFT 1
-#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_01_DEFAULT 0x00000000
-
-/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_00 [00:00] */
-#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_00_MASK 0x00000001
-#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_00_SHIFT 0
-#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_00_DEFAULT 0x00000000
-
-/***************************************************************************
- *SPARE_CTRL_1 - Spare control bits reserved for future use
- ***************************************************************************/
-/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_31 [31:31] */
-#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_31_MASK 0x80000000
-#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_31_SHIFT 31
-#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_31_DEFAULT 0x00000001
-
-/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_30 [30:30] */
-#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_30_MASK 0x40000000
-#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_30_SHIFT 30
-#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_30_DEFAULT 0x00000001
-
-/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_29 [29:29] */
-#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_29_MASK 0x20000000
-#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_29_SHIFT 29
-#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_29_DEFAULT 0x00000001
-
-/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_28 [28:28] */
-#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_28_MASK 0x10000000
-#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_28_SHIFT 28
-#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_28_DEFAULT 0x00000001
-
-/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_27 [27:27] */
-#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_27_MASK 0x08000000
-#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_27_SHIFT 27
-#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_27_DEFAULT 0x00000001
-
-/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_26 [26:26] */
-#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_26_MASK 0x04000000
-#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_26_SHIFT 26
-#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_26_DEFAULT 0x00000001
-
-/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_25 [25:25] */
-#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_25_MASK 0x02000000
-#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_25_SHIFT 25
-#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_25_DEFAULT 0x00000001
-
-/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_24 [24:24] */
-#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_24_MASK 0x01000000
-#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_24_SHIFT 24
-#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_24_DEFAULT 0x00000001
-
-/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_23 [23:23] */
-#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_23_MASK 0x00800000
-#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_23_SHIFT 23
-#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_23_DEFAULT 0x00000000
-
-/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_22 [22:22] */
-#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_22_MASK 0x00400000
-#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_22_SHIFT 22
-#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_22_DEFAULT 0x00000000
-
-/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_21 [21:21] */
-#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_21_MASK 0x00200000
-#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_21_SHIFT 21
-#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_21_DEFAULT 0x00000000
-
-/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_20 [20:20] */
-#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_20_MASK 0x00100000
-#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_20_SHIFT 20
-#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_20_DEFAULT 0x00000000
-
-/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_19 [19:19] */
-#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_19_MASK 0x00080000
-#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_19_SHIFT 19
-#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_19_DEFAULT 0x00000000
-
-/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_18 [18:18] */
-#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_18_MASK 0x00040000
-#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_18_SHIFT 18
-#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_18_DEFAULT 0x00000000
-
-/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_17 [17:17] */
-#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_17_MASK 0x00020000
-#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_17_SHIFT 17
-#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_17_DEFAULT 0x00000000
-
-/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_16 [16:16] */
-#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_16_MASK 0x00010000
-#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_16_SHIFT 16
-#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_16_DEFAULT 0x00000000
-
-/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_15 [15:15] */
-#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_15_MASK 0x00008000
-#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_15_SHIFT 15
-#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_15_DEFAULT 0x00000000
-
-/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_14 [14:14] */
-#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_14_MASK 0x00004000
-#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_14_SHIFT 14
-#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_14_DEFAULT 0x00000000
-
-/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_13 [13:13] */
-#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_13_MASK 0x00002000
-#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_13_SHIFT 13
-#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_13_DEFAULT 0x00000000
-
-/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_12 [12:12] */
-#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_12_MASK 0x00001000
-#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_12_SHIFT 12
-#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_12_DEFAULT 0x00000000
-
-/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_11 [11:11] */
-#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_11_MASK 0x00000800
-#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_11_SHIFT 11
-#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_11_DEFAULT 0x00000000
-
-/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_10 [10:10] */
-#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_10_MASK 0x00000400
-#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_10_SHIFT 10
-#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_10_DEFAULT 0x00000000
-
-/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_09 [09:09] */
-#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_09_MASK 0x00000200
-#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_09_SHIFT 9
-#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_09_DEFAULT 0x00000000
-
-/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_08 [08:08] */
-#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_08_MASK 0x00000100
-#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_08_SHIFT 8
-#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_08_DEFAULT 0x00000000
-
-/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_07 [07:07] */
-#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_07_MASK 0x00000080
-#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_07_SHIFT 7
-#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_07_DEFAULT 0x00000000
-
-/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_06 [06:06] */
-#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_06_MASK 0x00000040
-#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_06_SHIFT 6
-#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_06_DEFAULT 0x00000000
-
-/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_05 [05:05] */
-#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_05_MASK 0x00000020
-#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_05_SHIFT 5
-#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_05_DEFAULT 0x00000000
-
-/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_04 [04:04] */
-#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_04_MASK 0x00000010
-#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_04_SHIFT 4
-#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_04_DEFAULT 0x00000000
-
-/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_03 [03:03] */
-#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_03_MASK 0x00000008
-#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_03_SHIFT 3
-#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_03_DEFAULT 0x00000000
-
-/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_02 [02:02] */
-#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_02_MASK 0x00000004
-#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_02_SHIFT 2
-#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_02_DEFAULT 0x00000000
-
-/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_01 [01:01] */
-#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_01_MASK 0x00000002
-#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_01_SHIFT 1
-#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_01_DEFAULT 0x00000000
-
-/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_00 [00:00] */
-#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_00_MASK 0x00000001
-#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_00_SHIFT 0
-#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_00_DEFAULT 0x00000000
-
-/***************************************************************************
- *UNCLEARED_SCRATCH - Scratch register
- ***************************************************************************/
-/* AON_CTRL :: UNCLEARED_SCRATCH :: uncleared_scratch [31:00] */
-#define BCHP_AON_CTRL_UNCLEARED_SCRATCH_uncleared_scratch_MASK 0xffffffff
-#define BCHP_AON_CTRL_UNCLEARED_SCRATCH_uncleared_scratch_SHIFT 0
-#define BCHP_AON_CTRL_UNCLEARED_SCRATCH_uncleared_scratch_DEFAULT 0x00000000
-
-/***************************************************************************
- *RESET_HISTORY - Reset History Register For AON
- ***************************************************************************/
-/* AON_CTRL :: RESET_HISTORY :: reserved0 [31:22] */
-#define BCHP_AON_CTRL_RESET_HISTORY_reserved0_MASK 0xffc00000
-#define BCHP_AON_CTRL_RESET_HISTORY_reserved0_SHIFT 22
-
-/* AON_CTRL :: RESET_HISTORY :: aux_chip_level_reset_1 [21:21] */
-#define BCHP_AON_CTRL_RESET_HISTORY_aux_chip_level_reset_1_MASK 0x00200000
-#define BCHP_AON_CTRL_RESET_HISTORY_aux_chip_level_reset_1_SHIFT 21
-#define BCHP_AON_CTRL_RESET_HISTORY_aux_chip_level_reset_1_DEFAULT 0x00000000
-
-/* AON_CTRL :: RESET_HISTORY :: aux_chip_level_reset_0 [20:20] */
-#define BCHP_AON_CTRL_RESET_HISTORY_aux_chip_level_reset_0_MASK 0x00100000
-#define BCHP_AON_CTRL_RESET_HISTORY_aux_chip_level_reset_0_SHIFT 20
-#define BCHP_AON_CTRL_RESET_HISTORY_aux_chip_level_reset_0_DEFAULT 0x00000000
-
-/* AON_CTRL :: RESET_HISTORY :: aux_chip_edge_reset_1 [19:19] */
-#define BCHP_AON_CTRL_RESET_HISTORY_aux_chip_edge_reset_1_MASK 0x00080000
-#define BCHP_AON_CTRL_RESET_HISTORY_aux_chip_edge_reset_1_SHIFT 19
-#define BCHP_AON_CTRL_RESET_HISTORY_aux_chip_edge_reset_1_DEFAULT 0x00000000
-
-/* AON_CTRL :: RESET_HISTORY :: aux_chip_edge_reset_0 [18:18] */
-#define BCHP_AON_CTRL_RESET_HISTORY_aux_chip_edge_reset_0_MASK 0x00040000
-#define BCHP_AON_CTRL_RESET_HISTORY_aux_chip_edge_reset_0_SHIFT 18
-#define BCHP_AON_CTRL_RESET_HISTORY_aux_chip_edge_reset_0_DEFAULT 0x00000000
-
-/* AON_CTRL :: RESET_HISTORY :: gen_watchdog_1_reset [17:17] */
-#define BCHP_AON_CTRL_RESET_HISTORY_gen_watchdog_1_reset_MASK 0x00020000
-#define BCHP_AON_CTRL_RESET_HISTORY_gen_watchdog_1_reset_SHIFT 17
-#define BCHP_AON_CTRL_RESET_HISTORY_gen_watchdog_1_reset_DEFAULT 0x00000000
-
-/* AON_CTRL :: RESET_HISTORY :: scpu_ejtag_reset [16:16] */
-#define BCHP_AON_CTRL_RESET_HISTORY_scpu_ejtag_reset_MASK 0x00010000
-#define BCHP_AON_CTRL_RESET_HISTORY_scpu_ejtag_reset_SHIFT 16
-#define BCHP_AON_CTRL_RESET_HISTORY_scpu_ejtag_reset_DEFAULT 0x00000000
-
-/* AON_CTRL :: RESET_HISTORY :: cpu_ejtag_reset [15:15] */
-#define BCHP_AON_CTRL_RESET_HISTORY_cpu_ejtag_reset_MASK 0x00008000
-#define BCHP_AON_CTRL_RESET_HISTORY_cpu_ejtag_reset_SHIFT 15
-#define BCHP_AON_CTRL_RESET_HISTORY_cpu_ejtag_reset_DEFAULT 0x00000000
-
-/* AON_CTRL :: RESET_HISTORY :: overtemp_reset [14:14] */
-#define BCHP_AON_CTRL_RESET_HISTORY_overtemp_reset_MASK 0x00004000
-#define BCHP_AON_CTRL_RESET_HISTORY_overtemp_reset_SHIFT 14
-#define BCHP_AON_CTRL_RESET_HISTORY_overtemp_reset_DEFAULT 0x00000000
-
-/* AON_CTRL :: RESET_HISTORY :: overvoltage_1_reset [13:13] */
-#define BCHP_AON_CTRL_RESET_HISTORY_overvoltage_1_reset_MASK 0x00002000
-#define BCHP_AON_CTRL_RESET_HISTORY_overvoltage_1_reset_SHIFT 13
-#define BCHP_AON_CTRL_RESET_HISTORY_overvoltage_1_reset_DEFAULT 0x00000000
-
-/* AON_CTRL :: RESET_HISTORY :: undervoltage_1_reset [12:12] */
-#define BCHP_AON_CTRL_RESET_HISTORY_undervoltage_1_reset_MASK 0x00001000
-#define BCHP_AON_CTRL_RESET_HISTORY_undervoltage_1_reset_SHIFT 12
-#define BCHP_AON_CTRL_RESET_HISTORY_undervoltage_1_reset_DEFAULT 0x00000000
-
-/* AON_CTRL :: RESET_HISTORY :: undervoltage_0_reset [11:11] */
-#define BCHP_AON_CTRL_RESET_HISTORY_undervoltage_0_reset_MASK 0x00000800
-#define BCHP_AON_CTRL_RESET_HISTORY_undervoltage_0_reset_SHIFT 11
-#define BCHP_AON_CTRL_RESET_HISTORY_undervoltage_0_reset_DEFAULT 0x00000000
-
-/* AON_CTRL :: RESET_HISTORY :: security_master_reset [10:10] */
-#define BCHP_AON_CTRL_RESET_HISTORY_security_master_reset_MASK 0x00000400
-#define BCHP_AON_CTRL_RESET_HISTORY_security_master_reset_SHIFT 10
-#define BCHP_AON_CTRL_RESET_HISTORY_security_master_reset_DEFAULT 0x00000000
-
-/* AON_CTRL :: RESET_HISTORY :: software_master_reset [09:09] */
-#define BCHP_AON_CTRL_RESET_HISTORY_software_master_reset_MASK 0x00000200
-#define BCHP_AON_CTRL_RESET_HISTORY_software_master_reset_SHIFT 9
-#define BCHP_AON_CTRL_RESET_HISTORY_software_master_reset_DEFAULT 0x00000000
-
-/* AON_CTRL :: RESET_HISTORY :: pcie_1_hot_boot_reset [08:08] */
-#define BCHP_AON_CTRL_RESET_HISTORY_pcie_1_hot_boot_reset_MASK 0x00000100
-#define BCHP_AON_CTRL_RESET_HISTORY_pcie_1_hot_boot_reset_SHIFT 8
-#define BCHP_AON_CTRL_RESET_HISTORY_pcie_1_hot_boot_reset_DEFAULT 0x00000000
-
-/* AON_CTRL :: RESET_HISTORY :: pcie_0_hot_boot_reset [07:07] */
-#define BCHP_AON_CTRL_RESET_HISTORY_pcie_0_hot_boot_reset_MASK 0x00000080
-#define BCHP_AON_CTRL_RESET_HISTORY_pcie_0_hot_boot_reset_SHIFT 7
-#define BCHP_AON_CTRL_RESET_HISTORY_pcie_0_hot_boot_reset_DEFAULT 0x00000000
-
-/* AON_CTRL :: RESET_HISTORY :: watchdog_timer_reset [06:06] */
-#define BCHP_AON_CTRL_RESET_HISTORY_watchdog_timer_reset_MASK 0x00000040
-#define BCHP_AON_CTRL_RESET_HISTORY_watchdog_timer_reset_SHIFT 6
-#define BCHP_AON_CTRL_RESET_HISTORY_watchdog_timer_reset_DEFAULT 0x00000000
-
-/* AON_CTRL :: RESET_HISTORY :: smartcard_insert_reset [05:05] */
-#define BCHP_AON_CTRL_RESET_HISTORY_smartcard_insert_reset_MASK 0x00000020
-#define BCHP_AON_CTRL_RESET_HISTORY_smartcard_insert_reset_SHIFT 5
-#define BCHP_AON_CTRL_RESET_HISTORY_smartcard_insert_reset_DEFAULT 0x00000000
-
-/* AON_CTRL :: RESET_HISTORY :: s3_wakeup_reset [04:04] */
-#define BCHP_AON_CTRL_RESET_HISTORY_s3_wakeup_reset_MASK 0x00000010
-#define BCHP_AON_CTRL_RESET_HISTORY_s3_wakeup_reset_SHIFT 4
-#define BCHP_AON_CTRL_RESET_HISTORY_s3_wakeup_reset_DEFAULT 0x00000000
-
-/* AON_CTRL :: RESET_HISTORY :: front_panel_4sec_reset [03:03] */
-#define BCHP_AON_CTRL_RESET_HISTORY_front_panel_4sec_reset_MASK 0x00000008
-#define BCHP_AON_CTRL_RESET_HISTORY_front_panel_4sec_reset_SHIFT 3
-#define BCHP_AON_CTRL_RESET_HISTORY_front_panel_4sec_reset_DEFAULT 0x00000000
-
-/* AON_CTRL :: RESET_HISTORY :: tap_in_system_reset [02:02] */
-#define BCHP_AON_CTRL_RESET_HISTORY_tap_in_system_reset_MASK 0x00000004
-#define BCHP_AON_CTRL_RESET_HISTORY_tap_in_system_reset_SHIFT 2
-#define BCHP_AON_CTRL_RESET_HISTORY_tap_in_system_reset_DEFAULT 0x00000000
-
-/* AON_CTRL :: RESET_HISTORY :: main_chip_reset_input [01:01] */
-#define BCHP_AON_CTRL_RESET_HISTORY_main_chip_reset_input_MASK 0x00000002
-#define BCHP_AON_CTRL_RESET_HISTORY_main_chip_reset_input_SHIFT 1
-#define BCHP_AON_CTRL_RESET_HISTORY_main_chip_reset_input_DEFAULT 0x00000000
-
-/* AON_CTRL :: RESET_HISTORY :: power_on_reset [00:00] */
-#define BCHP_AON_CTRL_RESET_HISTORY_power_on_reset_MASK 0x00000001
-#define BCHP_AON_CTRL_RESET_HISTORY_power_on_reset_SHIFT 0
-#define BCHP_AON_CTRL_RESET_HISTORY_power_on_reset_DEFAULT 0x00000001
-
-/***************************************************************************
- *NMI_CTRL - Control register for NMI
- ***************************************************************************/
-/* AON_CTRL :: NMI_CTRL :: nmi_config_lock [31:31] */
-#define BCHP_AON_CTRL_NMI_CTRL_nmi_config_lock_MASK 0x80000000
-#define BCHP_AON_CTRL_NMI_CTRL_nmi_config_lock_SHIFT 31
-#define BCHP_AON_CTRL_NMI_CTRL_nmi_config_lock_DEFAULT 0x00000000
-
-/* AON_CTRL :: NMI_CTRL :: reserved0 [30:03] */
-#define BCHP_AON_CTRL_NMI_CTRL_reserved0_MASK 0x7ffffff8
-#define BCHP_AON_CTRL_NMI_CTRL_reserved0_SHIFT 3
-
-/* AON_CTRL :: NMI_CTRL :: nmi_pad_monitor [02:02] */
-#define BCHP_AON_CTRL_NMI_CTRL_nmi_pad_monitor_MASK 0x00000004
-#define BCHP_AON_CTRL_NMI_CTRL_nmi_pad_monitor_SHIFT 2
-
-/* AON_CTRL :: NMI_CTRL :: config_nmi_polarity [01:01] */
-#define BCHP_AON_CTRL_NMI_CTRL_config_nmi_polarity_MASK 0x00000002
-#define BCHP_AON_CTRL_NMI_CTRL_config_nmi_polarity_SHIFT 1
-#define BCHP_AON_CTRL_NMI_CTRL_config_nmi_polarity_DEFAULT 0x00000000
-
-/* AON_CTRL :: NMI_CTRL :: disable_pad_nmi [00:00] */
-#define BCHP_AON_CTRL_NMI_CTRL_disable_pad_nmi_MASK 0x00000001
-#define BCHP_AON_CTRL_NMI_CTRL_disable_pad_nmi_SHIFT 0
-#define BCHP_AON_CTRL_NMI_CTRL_disable_pad_nmi_DEFAULT 0x00000001
-
-/***************************************************************************
- *ANA_XTAL_CONTROL - Ana xtal gisb control
- ***************************************************************************/
-/* AON_CTRL :: ANA_XTAL_CONTROL :: reserved0 [31:22] */
-#define BCHP_AON_CTRL_ANA_XTAL_CONTROL_reserved0_MASK 0xffc00000
-#define BCHP_AON_CTRL_ANA_XTAL_CONTROL_reserved0_SHIFT 22
-
-/* AON_CTRL :: ANA_XTAL_CONTROL :: en_osc_cmos_in_s3 [21:16] */
-#define BCHP_AON_CTRL_ANA_XTAL_CONTROL_en_osc_cmos_in_s3_MASK 0x003f0000
-#define BCHP_AON_CTRL_ANA_XTAL_CONTROL_en_osc_cmos_in_s3_SHIFT 16
-#define BCHP_AON_CTRL_ANA_XTAL_CONTROL_en_osc_cmos_in_s3_DEFAULT 0x00000000
-
-/* AON_CTRL :: ANA_XTAL_CONTROL :: en_osc_cml_in_s3 [15:12] */
-#define BCHP_AON_CTRL_ANA_XTAL_CONTROL_en_osc_cml_in_s3_MASK 0x0000f000
-#define BCHP_AON_CTRL_ANA_XTAL_CONTROL_en_osc_cml_in_s3_SHIFT 12
-#define BCHP_AON_CTRL_ANA_XTAL_CONTROL_en_osc_cml_in_s3_DEFAULT 0x00000000
-
-/* AON_CTRL :: ANA_XTAL_CONTROL :: osc_ldo_ctrl [11:08] */
-#define BCHP_AON_CTRL_ANA_XTAL_CONTROL_osc_ldo_ctrl_MASK 0x00000f00
-#define BCHP_AON_CTRL_ANA_XTAL_CONTROL_osc_ldo_ctrl_SHIFT 8
-#define BCHP_AON_CTRL_ANA_XTAL_CONTROL_osc_ldo_ctrl_DEFAULT 0x00000005
-
-/* AON_CTRL :: ANA_XTAL_CONTROL :: osc_select_current_gisb_control [07:07] */
-#define BCHP_AON_CTRL_ANA_XTAL_CONTROL_osc_select_current_gisb_control_MASK 0x00000080
-#define BCHP_AON_CTRL_ANA_XTAL_CONTROL_osc_select_current_gisb_control_SHIFT 7
-#define BCHP_AON_CTRL_ANA_XTAL_CONTROL_osc_select_current_gisb_control_DEFAULT 0x00000000
-
-/* AON_CTRL :: ANA_XTAL_CONTROL :: osc_cml_sel_pd [06:03] */
-#define BCHP_AON_CTRL_ANA_XTAL_CONTROL_osc_cml_sel_pd_MASK 0x00000078
-#define BCHP_AON_CTRL_ANA_XTAL_CONTROL_osc_cml_sel_pd_SHIFT 3
-#define BCHP_AON_CTRL_ANA_XTAL_CONTROL_osc_cml_sel_pd_DEFAULT 0x00000000
-
-/* AON_CTRL :: ANA_XTAL_CONTROL :: osc_d2cbias_gisb_control [02:00] */
-#define BCHP_AON_CTRL_ANA_XTAL_CONTROL_osc_d2cbias_gisb_control_MASK 0x00000007
-#define BCHP_AON_CTRL_ANA_XTAL_CONTROL_osc_d2cbias_gisb_control_SHIFT 0
-#define BCHP_AON_CTRL_ANA_XTAL_CONTROL_osc_d2cbias_gisb_control_DEFAULT 0x00000004
-
-/***************************************************************************
- *SUB_TEST_MODE_CTRL - Test_mode control register
- ***************************************************************************/
-/* AON_CTRL :: SUB_TEST_MODE_CTRL :: reserved0 [31:01] */
-#define BCHP_AON_CTRL_SUB_TEST_MODE_CTRL_reserved0_MASK 0xfffffffe
-#define BCHP_AON_CTRL_SUB_TEST_MODE_CTRL_reserved0_SHIFT 1
-
-/* AON_CTRL :: SUB_TEST_MODE_CTRL :: use_sub_test_mode_reg_src [00:00] */
-#define BCHP_AON_CTRL_SUB_TEST_MODE_CTRL_use_sub_test_mode_reg_src_MASK 0x00000001
-#define BCHP_AON_CTRL_SUB_TEST_MODE_CTRL_use_sub_test_mode_reg_src_SHIFT 0
-#define BCHP_AON_CTRL_SUB_TEST_MODE_CTRL_use_sub_test_mode_reg_src_DEFAULT 0x00000000
-
-/***************************************************************************
- *SUB_TEST_MODE - Register source for sub_test_mode
- ***************************************************************************/
-/* AON_CTRL :: SUB_TEST_MODE :: reserved0 [31:10] */
-#define BCHP_AON_CTRL_SUB_TEST_MODE_reserved0_MASK 0xfffffc00
-#define BCHP_AON_CTRL_SUB_TEST_MODE_reserved0_SHIFT 10
-
-/* AON_CTRL :: SUB_TEST_MODE :: sub_test_mode_spare_1 [09:09] */
-#define BCHP_AON_CTRL_SUB_TEST_MODE_sub_test_mode_spare_1_MASK 0x00000200
-#define BCHP_AON_CTRL_SUB_TEST_MODE_sub_test_mode_spare_1_SHIFT 9
-#define BCHP_AON_CTRL_SUB_TEST_MODE_sub_test_mode_spare_1_DEFAULT 0x00000000
-
-/* AON_CTRL :: SUB_TEST_MODE :: sub_test_mode_spare_0 [08:08] */
-#define BCHP_AON_CTRL_SUB_TEST_MODE_sub_test_mode_spare_0_MASK 0x00000100
-#define BCHP_AON_CTRL_SUB_TEST_MODE_sub_test_mode_spare_0_SHIFT 8
-#define BCHP_AON_CTRL_SUB_TEST_MODE_sub_test_mode_spare_0_DEFAULT 0x00000000
-
-/* AON_CTRL :: SUB_TEST_MODE :: sub_test_mode_alt2_spi_slave_enable [07:07] */
-#define BCHP_AON_CTRL_SUB_TEST_MODE_sub_test_mode_alt2_spi_slave_enable_MASK 0x00000080
-#define BCHP_AON_CTRL_SUB_TEST_MODE_sub_test_mode_alt2_spi_slave_enable_SHIFT 7
-#define BCHP_AON_CTRL_SUB_TEST_MODE_sub_test_mode_alt2_spi_slave_enable_DEFAULT 0x00000000
-
-/* AON_CTRL :: SUB_TEST_MODE :: sub_test_mode_alt_spi_slave_enable [06:06] */
-#define BCHP_AON_CTRL_SUB_TEST_MODE_sub_test_mode_alt_spi_slave_enable_MASK 0x00000040
-#define BCHP_AON_CTRL_SUB_TEST_MODE_sub_test_mode_alt_spi_slave_enable_SHIFT 6
-#define BCHP_AON_CTRL_SUB_TEST_MODE_sub_test_mode_alt_spi_slave_enable_DEFAULT 0x00000000
-
-/* AON_CTRL :: SUB_TEST_MODE :: sub_test_mode_fast_tspi [05:05] */
-#define BCHP_AON_CTRL_SUB_TEST_MODE_sub_test_mode_fast_tspi_MASK 0x00000020
-#define BCHP_AON_CTRL_SUB_TEST_MODE_sub_test_mode_fast_tspi_SHIFT 5
-#define BCHP_AON_CTRL_SUB_TEST_MODE_sub_test_mode_fast_tspi_DEFAULT 0x00000000
-
-/* AON_CTRL :: SUB_TEST_MODE :: sub_test_mode_hold_cpu_in_reset [04:04] */
-#define BCHP_AON_CTRL_SUB_TEST_MODE_sub_test_mode_hold_cpu_in_reset_MASK 0x00000010
-#define BCHP_AON_CTRL_SUB_TEST_MODE_sub_test_mode_hold_cpu_in_reset_SHIFT 4
-#define BCHP_AON_CTRL_SUB_TEST_MODE_sub_test_mode_hold_cpu_in_reset_DEFAULT 0x00000000
-
-/* AON_CTRL :: SUB_TEST_MODE :: sub_test_mode_spi_slave_enable [03:03] */
-#define BCHP_AON_CTRL_SUB_TEST_MODE_sub_test_mode_spi_slave_enable_MASK 0x00000008
-#define BCHP_AON_CTRL_SUB_TEST_MODE_sub_test_mode_spi_slave_enable_SHIFT 3
-#define BCHP_AON_CTRL_SUB_TEST_MODE_sub_test_mode_spi_slave_enable_DEFAULT 0x00000000
-
-/* AON_CTRL :: SUB_TEST_MODE :: sub_test_mode_extend_reset [02:02] */
-#define BCHP_AON_CTRL_SUB_TEST_MODE_sub_test_mode_extend_reset_MASK 0x00000004
-#define BCHP_AON_CTRL_SUB_TEST_MODE_sub_test_mode_extend_reset_SHIFT 2
-#define BCHP_AON_CTRL_SUB_TEST_MODE_sub_test_mode_extend_reset_DEFAULT 0x00000000
-
-/* AON_CTRL :: SUB_TEST_MODE :: sub_test_mode_bsp_debug [01:00] */
-#define BCHP_AON_CTRL_SUB_TEST_MODE_sub_test_mode_bsp_debug_MASK 0x00000003
-#define BCHP_AON_CTRL_SUB_TEST_MODE_sub_test_mode_bsp_debug_SHIFT 0
-#define BCHP_AON_CTRL_SUB_TEST_MODE_sub_test_mode_bsp_debug_DEFAULT 0x00000000
-
-/***************************************************************************
- *LATCHED_TEST_MODE - Final latched testmode value
- ***************************************************************************/
-/* AON_CTRL :: LATCHED_TEST_MODE :: latched_test_mode [31:00] */
-#define BCHP_AON_CTRL_LATCHED_TEST_MODE_latched_test_mode_MASK 0xffffffff
-#define BCHP_AON_CTRL_LATCHED_TEST_MODE_latched_test_mode_SHIFT 0
-
-/***************************************************************************
- *LATCHED_SUB_TEST_MODE - Final latched sub-testmode value
- ***************************************************************************/
-/* AON_CTRL :: LATCHED_SUB_TEST_MODE :: latched_sub_test_mode [31:00] */
-#define BCHP_AON_CTRL_LATCHED_SUB_TEST_MODE_latched_sub_test_mode_MASK 0xffffffff
-#define BCHP_AON_CTRL_LATCHED_SUB_TEST_MODE_latched_sub_test_mode_SHIFT 0
-
-/***************************************************************************
- *PM_INITIATE - Power down initiate
- ***************************************************************************/
-/* AON_CTRL :: PM_INITIATE :: reserved0 [31:08] */
-#define BCHP_AON_CTRL_PM_INITIATE_reserved0_MASK 0xffffff00
-#define BCHP_AON_CTRL_PM_INITIATE_reserved0_SHIFT 8
-
-/* AON_CTRL :: PM_INITIATE :: pm_initiate_7 [07:07] */
-#define BCHP_AON_CTRL_PM_INITIATE_pm_initiate_7_MASK 0x00000080
-#define BCHP_AON_CTRL_PM_INITIATE_pm_initiate_7_SHIFT 7
-#define BCHP_AON_CTRL_PM_INITIATE_pm_initiate_7_DEFAULT 0x00000000
-
-/* AON_CTRL :: PM_INITIATE :: pm_initiate_6 [06:06] */
-#define BCHP_AON_CTRL_PM_INITIATE_pm_initiate_6_MASK 0x00000040
-#define BCHP_AON_CTRL_PM_INITIATE_pm_initiate_6_SHIFT 6
-#define BCHP_AON_CTRL_PM_INITIATE_pm_initiate_6_DEFAULT 0x00000000
-
-/* AON_CTRL :: PM_INITIATE :: pm_initiate_5 [05:05] */
-#define BCHP_AON_CTRL_PM_INITIATE_pm_initiate_5_MASK 0x00000020
-#define BCHP_AON_CTRL_PM_INITIATE_pm_initiate_5_SHIFT 5
-#define BCHP_AON_CTRL_PM_INITIATE_pm_initiate_5_DEFAULT 0x00000000
-
-/* AON_CTRL :: PM_INITIATE :: pm_initiate_4 [04:04] */
-#define BCHP_AON_CTRL_PM_INITIATE_pm_initiate_4_MASK 0x00000010
-#define BCHP_AON_CTRL_PM_INITIATE_pm_initiate_4_SHIFT 4
-#define BCHP_AON_CTRL_PM_INITIATE_pm_initiate_4_DEFAULT 0x00000000
-
-/* AON_CTRL :: PM_INITIATE :: pm_initiate_3 [03:03] */
-#define BCHP_AON_CTRL_PM_INITIATE_pm_initiate_3_MASK 0x00000008
-#define BCHP_AON_CTRL_PM_INITIATE_pm_initiate_3_SHIFT 3
-#define BCHP_AON_CTRL_PM_INITIATE_pm_initiate_3_DEFAULT 0x00000000
-
-/* AON_CTRL :: PM_INITIATE :: pm_initiate_2 [02:02] */
-#define BCHP_AON_CTRL_PM_INITIATE_pm_initiate_2_MASK 0x00000004
-#define BCHP_AON_CTRL_PM_INITIATE_pm_initiate_2_SHIFT 2
-#define BCHP_AON_CTRL_PM_INITIATE_pm_initiate_2_DEFAULT 0x00000000
-
-/* AON_CTRL :: PM_INITIATE :: pm_initiate_1 [01:01] */
-#define BCHP_AON_CTRL_PM_INITIATE_pm_initiate_1_MASK 0x00000002
-#define BCHP_AON_CTRL_PM_INITIATE_pm_initiate_1_SHIFT 1
-#define BCHP_AON_CTRL_PM_INITIATE_pm_initiate_1_DEFAULT 0x00000000
-
-/* AON_CTRL :: PM_INITIATE :: pm_initiate_0 [00:00] */
-#define BCHP_AON_CTRL_PM_INITIATE_pm_initiate_0_MASK 0x00000001
-#define BCHP_AON_CTRL_PM_INITIATE_pm_initiate_0_SHIFT 0
-#define BCHP_AON_CTRL_PM_INITIATE_pm_initiate_0_DEFAULT 0x00000000
-
-/***************************************************************************
- *HOST_MISC_CMDS - Power up restore
- ***************************************************************************/
-/* AON_CTRL :: HOST_MISC_CMDS :: reserved0 [31:08] */
-#define BCHP_AON_CTRL_HOST_MISC_CMDS_reserved0_MASK 0xffffff00
-#define BCHP_AON_CTRL_HOST_MISC_CMDS_reserved0_SHIFT 8
-
-/* AON_CTRL :: HOST_MISC_CMDS :: host_misc_cmds_7 [07:07] */
-#define BCHP_AON_CTRL_HOST_MISC_CMDS_host_misc_cmds_7_MASK 0x00000080
-#define BCHP_AON_CTRL_HOST_MISC_CMDS_host_misc_cmds_7_SHIFT 7
-#define BCHP_AON_CTRL_HOST_MISC_CMDS_host_misc_cmds_7_DEFAULT 0x00000000
-
-/* AON_CTRL :: HOST_MISC_CMDS :: host_misc_cmds_6 [06:06] */
-#define BCHP_AON_CTRL_HOST_MISC_CMDS_host_misc_cmds_6_MASK 0x00000040
-#define BCHP_AON_CTRL_HOST_MISC_CMDS_host_misc_cmds_6_SHIFT 6
-#define BCHP_AON_CTRL_HOST_MISC_CMDS_host_misc_cmds_6_DEFAULT 0x00000000
-
-/* AON_CTRL :: HOST_MISC_CMDS :: host_misc_cmds_5 [05:05] */
-#define BCHP_AON_CTRL_HOST_MISC_CMDS_host_misc_cmds_5_MASK 0x00000020
-#define BCHP_AON_CTRL_HOST_MISC_CMDS_host_misc_cmds_5_SHIFT 5
-#define BCHP_AON_CTRL_HOST_MISC_CMDS_host_misc_cmds_5_DEFAULT 0x00000000
-
-/* AON_CTRL :: HOST_MISC_CMDS :: host_misc_cmds_4 [04:04] */
-#define BCHP_AON_CTRL_HOST_MISC_CMDS_host_misc_cmds_4_MASK 0x00000010
-#define BCHP_AON_CTRL_HOST_MISC_CMDS_host_misc_cmds_4_SHIFT 4
-#define BCHP_AON_CTRL_HOST_MISC_CMDS_host_misc_cmds_4_DEFAULT 0x00000000
-
-/* AON_CTRL :: HOST_MISC_CMDS :: host_misc_cmds_3 [03:03] */
-#define BCHP_AON_CTRL_HOST_MISC_CMDS_host_misc_cmds_3_MASK 0x00000008
-#define BCHP_AON_CTRL_HOST_MISC_CMDS_host_misc_cmds_3_SHIFT 3
-#define BCHP_AON_CTRL_HOST_MISC_CMDS_host_misc_cmds_3_DEFAULT 0x00000000
-
-/* AON_CTRL :: HOST_MISC_CMDS :: host_misc_cmds_2 [02:02] */
-#define BCHP_AON_CTRL_HOST_MISC_CMDS_host_misc_cmds_2_MASK 0x00000004
-#define BCHP_AON_CTRL_HOST_MISC_CMDS_host_misc_cmds_2_SHIFT 2
-#define BCHP_AON_CTRL_HOST_MISC_CMDS_host_misc_cmds_2_DEFAULT 0x00000000
-
-/* AON_CTRL :: HOST_MISC_CMDS :: dram_scram_key_reuse_req [01:01] */
-#define BCHP_AON_CTRL_HOST_MISC_CMDS_dram_scram_key_reuse_req_MASK 0x00000002
-#define BCHP_AON_CTRL_HOST_MISC_CMDS_dram_scram_key_reuse_req_SHIFT 1
-#define BCHP_AON_CTRL_HOST_MISC_CMDS_dram_scram_key_reuse_req_DEFAULT 0x00000000
-
-/* AON_CTRL :: HOST_MISC_CMDS :: pm_restore [00:00] */
-#define BCHP_AON_CTRL_HOST_MISC_CMDS_pm_restore_MASK 0x00000001
-#define BCHP_AON_CTRL_HOST_MISC_CMDS_pm_restore_SHIFT 0
-#define BCHP_AON_CTRL_HOST_MISC_CMDS_pm_restore_DEFAULT 0x00000000
-
-/***************************************************************************
- *ANA_XTAL_EXT_CML_CONTROL - Ana xtal external CML control
- ***************************************************************************/
-/* AON_CTRL :: ANA_XTAL_EXT_CML_CONTROL :: reserved0 [31:06] */
-#define BCHP_AON_CTRL_ANA_XTAL_EXT_CML_CONTROL_reserved0_MASK 0xffffffc0
-#define BCHP_AON_CTRL_ANA_XTAL_EXT_CML_CONTROL_reserved0_SHIFT 6
-
-/* AON_CTRL :: ANA_XTAL_EXT_CML_CONTROL :: osc_PMSM_S3_pd_buffer [05:05] */
-#define BCHP_AON_CTRL_ANA_XTAL_EXT_CML_CONTROL_osc_PMSM_S3_pd_buffer_MASK 0x00000020
-#define BCHP_AON_CTRL_ANA_XTAL_EXT_CML_CONTROL_osc_PMSM_S3_pd_buffer_SHIFT 5
-#define BCHP_AON_CTRL_ANA_XTAL_EXT_CML_CONTROL_osc_PMSM_S3_pd_buffer_DEFAULT 0x00000000
-
-/* AON_CTRL :: ANA_XTAL_EXT_CML_CONTROL :: osc_override_strap [04:04] */
-#define BCHP_AON_CTRL_ANA_XTAL_EXT_CML_CONTROL_osc_override_strap_MASK 0x00000010
-#define BCHP_AON_CTRL_ANA_XTAL_EXT_CML_CONTROL_osc_override_strap_SHIFT 4
-#define BCHP_AON_CTRL_ANA_XTAL_EXT_CML_CONTROL_osc_override_strap_DEFAULT 0x00000000
-
-/* AON_CTRL :: ANA_XTAL_EXT_CML_CONTROL :: osc_pd_buffer [03:03] */
-#define BCHP_AON_CTRL_ANA_XTAL_EXT_CML_CONTROL_osc_pd_buffer_MASK 0x00000008
-#define BCHP_AON_CTRL_ANA_XTAL_EXT_CML_CONTROL_osc_pd_buffer_SHIFT 3
-#define BCHP_AON_CTRL_ANA_XTAL_EXT_CML_CONTROL_osc_pd_buffer_DEFAULT 0x00000000
-
-/* AON_CTRL :: ANA_XTAL_EXT_CML_CONTROL :: osc_div2_sel [02:02] */
-#define BCHP_AON_CTRL_ANA_XTAL_EXT_CML_CONTROL_osc_div2_sel_MASK 0x00000004
-#define BCHP_AON_CTRL_ANA_XTAL_EXT_CML_CONTROL_osc_div2_sel_SHIFT 2
-#define BCHP_AON_CTRL_ANA_XTAL_EXT_CML_CONTROL_osc_div2_sel_DEFAULT 0x00000001
-
-/* AON_CTRL :: ANA_XTAL_EXT_CML_CONTROL :: osc_current [01:00] */
-#define BCHP_AON_CTRL_ANA_XTAL_EXT_CML_CONTROL_osc_current_MASK 0x00000003
-#define BCHP_AON_CTRL_ANA_XTAL_EXT_CML_CONTROL_osc_current_SHIFT 0
-#define BCHP_AON_CTRL_ANA_XTAL_EXT_CML_CONTROL_osc_current_DEFAULT 0x00000001
-
-/***************************************************************************
- *PM_DRAM_READY_STATUS_MASK - DRAM Ready status mask control
- ***************************************************************************/
-/* AON_CTRL :: PM_DRAM_READY_STATUS_MASK :: reserved0 [31:02] */
-#define BCHP_AON_CTRL_PM_DRAM_READY_STATUS_MASK_reserved0_MASK 0xfffffffc
-#define BCHP_AON_CTRL_PM_DRAM_READY_STATUS_MASK_reserved0_SHIFT 2
-
-/* AON_CTRL :: PM_DRAM_READY_STATUS_MASK :: memc [01:00] */
-#define BCHP_AON_CTRL_PM_DRAM_READY_STATUS_MASK_memc_MASK 0x00000003
-#define BCHP_AON_CTRL_PM_DRAM_READY_STATUS_MASK_memc_SHIFT 0
-#define BCHP_AON_CTRL_PM_DRAM_READY_STATUS_MASK_memc_DEFAULT 0x00000000
-
-/***************************************************************************
- *ANA_CBUF0_CONTROL - Ana crystal buffer 0 control
- ***************************************************************************/
-/* AON_CTRL :: ANA_CBUF0_CONTROL :: spare_ctrl [31:24] */
-#define BCHP_AON_CTRL_ANA_CBUF0_CONTROL_spare_ctrl_MASK 0xff000000
-#define BCHP_AON_CTRL_ANA_CBUF0_CONTROL_spare_ctrl_SHIFT 24
-#define BCHP_AON_CTRL_ANA_CBUF0_CONTROL_spare_ctrl_DEFAULT 0x00000000
-
-/* AON_CTRL :: ANA_CBUF0_CONTROL :: clk2_cml_drv1 [23:21] */
-#define BCHP_AON_CTRL_ANA_CBUF0_CONTROL_clk2_cml_drv1_MASK 0x00e00000
-#define BCHP_AON_CTRL_ANA_CBUF0_CONTROL_clk2_cml_drv1_SHIFT 21
-#define BCHP_AON_CTRL_ANA_CBUF0_CONTROL_clk2_cml_drv1_DEFAULT 0x00000000
-
-/* AON_CTRL :: ANA_CBUF0_CONTROL :: clk2_cml_drv0 [20:18] */
-#define BCHP_AON_CTRL_ANA_CBUF0_CONTROL_clk2_cml_drv0_MASK 0x001c0000
-#define BCHP_AON_CTRL_ANA_CBUF0_CONTROL_clk2_cml_drv0_SHIFT 18
-#define BCHP_AON_CTRL_ANA_CBUF0_CONTROL_clk2_cml_drv0_DEFAULT 0x00000000
-
-/* AON_CTRL :: ANA_CBUF0_CONTROL :: clk2_cml_en_in_s3 [17:16] */
-#define BCHP_AON_CTRL_ANA_CBUF0_CONTROL_clk2_cml_en_in_s3_MASK 0x00030000
-#define BCHP_AON_CTRL_ANA_CBUF0_CONTROL_clk2_cml_en_in_s3_SHIFT 16
-#define BCHP_AON_CTRL_ANA_CBUF0_CONTROL_clk2_cml_en_in_s3_DEFAULT 0x00000000
-
-/* AON_CTRL :: ANA_CBUF0_CONTROL :: clk2_cml_enb [15:14] */
-#define BCHP_AON_CTRL_ANA_CBUF0_CONTROL_clk2_cml_enb_MASK 0x0000c000
-#define BCHP_AON_CTRL_ANA_CBUF0_CONTROL_clk2_cml_enb_SHIFT 14
-#define BCHP_AON_CTRL_ANA_CBUF0_CONTROL_clk2_cml_enb_DEFAULT 0x00000003
-
-/* AON_CTRL :: ANA_CBUF0_CONTROL :: clk1_cml_drv1 [13:11] */
-#define BCHP_AON_CTRL_ANA_CBUF0_CONTROL_clk1_cml_drv1_MASK 0x00003800
-#define BCHP_AON_CTRL_ANA_CBUF0_CONTROL_clk1_cml_drv1_SHIFT 11
-#define BCHP_AON_CTRL_ANA_CBUF0_CONTROL_clk1_cml_drv1_DEFAULT 0x00000000
-
-/* AON_CTRL :: ANA_CBUF0_CONTROL :: clk1_cml_drv0 [10:08] */
-#define BCHP_AON_CTRL_ANA_CBUF0_CONTROL_clk1_cml_drv0_MASK 0x00000700
-#define BCHP_AON_CTRL_ANA_CBUF0_CONTROL_clk1_cml_drv0_SHIFT 8
-#define BCHP_AON_CTRL_ANA_CBUF0_CONTROL_clk1_cml_drv0_DEFAULT 0x00000000
-
-/* AON_CTRL :: ANA_CBUF0_CONTROL :: clk1_cml_en_in_s3 [07:06] */
-#define BCHP_AON_CTRL_ANA_CBUF0_CONTROL_clk1_cml_en_in_s3_MASK 0x000000c0
-#define BCHP_AON_CTRL_ANA_CBUF0_CONTROL_clk1_cml_en_in_s3_SHIFT 6
-#define BCHP_AON_CTRL_ANA_CBUF0_CONTROL_clk1_cml_en_in_s3_DEFAULT 0x00000000
-
-/* AON_CTRL :: ANA_CBUF0_CONTROL :: clk1_cml_enb [05:04] */
-#define BCHP_AON_CTRL_ANA_CBUF0_CONTROL_clk1_cml_enb_MASK 0x00000030
-#define BCHP_AON_CTRL_ANA_CBUF0_CONTROL_clk1_cml_enb_SHIFT 4
-#define BCHP_AON_CTRL_ANA_CBUF0_CONTROL_clk1_cml_enb_DEFAULT 0x00000000
-
-/* AON_CTRL :: ANA_CBUF0_CONTROL :: ldo_ctrl [03:00] */
-#define BCHP_AON_CTRL_ANA_CBUF0_CONTROL_ldo_ctrl_MASK 0x0000000f
-#define BCHP_AON_CTRL_ANA_CBUF0_CONTROL_ldo_ctrl_SHIFT 0
-#define BCHP_AON_CTRL_ANA_CBUF0_CONTROL_ldo_ctrl_DEFAULT 0x00000005
-
-/***************************************************************************
- *ANA_CBUF1_CONTROL - Ana crystal buffer 1 control
- ***************************************************************************/
-/* AON_CTRL :: ANA_CBUF1_CONTROL :: spare_ctrl [31:24] */
-#define BCHP_AON_CTRL_ANA_CBUF1_CONTROL_spare_ctrl_MASK 0xff000000
-#define BCHP_AON_CTRL_ANA_CBUF1_CONTROL_spare_ctrl_SHIFT 24
-#define BCHP_AON_CTRL_ANA_CBUF1_CONTROL_spare_ctrl_DEFAULT 0x00000000
-
-/* AON_CTRL :: ANA_CBUF1_CONTROL :: clk2_cml_drv1 [23:21] */
-#define BCHP_AON_CTRL_ANA_CBUF1_CONTROL_clk2_cml_drv1_MASK 0x00e00000
-#define BCHP_AON_CTRL_ANA_CBUF1_CONTROL_clk2_cml_drv1_SHIFT 21
-#define BCHP_AON_CTRL_ANA_CBUF1_CONTROL_clk2_cml_drv1_DEFAULT 0x00000000
-
-/* AON_CTRL :: ANA_CBUF1_CONTROL :: clk2_cml_drv0 [20:18] */
-#define BCHP_AON_CTRL_ANA_CBUF1_CONTROL_clk2_cml_drv0_MASK 0x001c0000
-#define BCHP_AON_CTRL_ANA_CBUF1_CONTROL_clk2_cml_drv0_SHIFT 18
-#define BCHP_AON_CTRL_ANA_CBUF1_CONTROL_clk2_cml_drv0_DEFAULT 0x00000000
-
-/* AON_CTRL :: ANA_CBUF1_CONTROL :: clk2_cml_en_in_s3 [17:16] */
-#define BCHP_AON_CTRL_ANA_CBUF1_CONTROL_clk2_cml_en_in_s3_MASK 0x00030000
-#define BCHP_AON_CTRL_ANA_CBUF1_CONTROL_clk2_cml_en_in_s3_SHIFT 16
-#define BCHP_AON_CTRL_ANA_CBUF1_CONTROL_clk2_cml_en_in_s3_DEFAULT 0x00000000
-
-/* AON_CTRL :: ANA_CBUF1_CONTROL :: clk2_cml_enb [15:14] */
-#define BCHP_AON_CTRL_ANA_CBUF1_CONTROL_clk2_cml_enb_MASK 0x0000c000
-#define BCHP_AON_CTRL_ANA_CBUF1_CONTROL_clk2_cml_enb_SHIFT 14
-#define BCHP_AON_CTRL_ANA_CBUF1_CONTROL_clk2_cml_enb_DEFAULT 0x00000003
-
-/* AON_CTRL :: ANA_CBUF1_CONTROL :: clk1_cml_drv1 [13:11] */
-#define BCHP_AON_CTRL_ANA_CBUF1_CONTROL_clk1_cml_drv1_MASK 0x00003800
-#define BCHP_AON_CTRL_ANA_CBUF1_CONTROL_clk1_cml_drv1_SHIFT 11
-#define BCHP_AON_CTRL_ANA_CBUF1_CONTROL_clk1_cml_drv1_DEFAULT 0x00000000
-
-/* AON_CTRL :: ANA_CBUF1_CONTROL :: clk1_cml_drv0 [10:08] */
-#define BCHP_AON_CTRL_ANA_CBUF1_CONTROL_clk1_cml_drv0_MASK 0x00000700
-#define BCHP_AON_CTRL_ANA_CBUF1_CONTROL_clk1_cml_drv0_SHIFT 8
-#define BCHP_AON_CTRL_ANA_CBUF1_CONTROL_clk1_cml_drv0_DEFAULT 0x00000000
-
-/* AON_CTRL :: ANA_CBUF1_CONTROL :: clk1_cml_en_in_s3 [07:06] */
-#define BCHP_AON_CTRL_ANA_CBUF1_CONTROL_clk1_cml_en_in_s3_MASK 0x000000c0
-#define BCHP_AON_CTRL_ANA_CBUF1_CONTROL_clk1_cml_en_in_s3_SHIFT 6
-#define BCHP_AON_CTRL_ANA_CBUF1_CONTROL_clk1_cml_en_in_s3_DEFAULT 0x00000000
-
-/* AON_CTRL :: ANA_CBUF1_CONTROL :: clk1_cml_enb [05:04] */
-#define BCHP_AON_CTRL_ANA_CBUF1_CONTROL_clk1_cml_enb_MASK 0x00000030
-#define BCHP_AON_CTRL_ANA_CBUF1_CONTROL_clk1_cml_enb_SHIFT 4
-#define BCHP_AON_CTRL_ANA_CBUF1_CONTROL_clk1_cml_enb_DEFAULT 0x00000002
-
-/* AON_CTRL :: ANA_CBUF1_CONTROL :: ldo_ctrl [03:00] */
-#define BCHP_AON_CTRL_ANA_CBUF1_CONTROL_ldo_ctrl_MASK 0x0000000f
-#define BCHP_AON_CTRL_ANA_CBUF1_CONTROL_ldo_ctrl_SHIFT 0
-#define BCHP_AON_CTRL_ANA_CBUF1_CONTROL_ldo_ctrl_DEFAULT 0x00000005
-
-/***************************************************************************
- *SYSTEM_DATA_RAM%i - System Data RAM Address 0..255
- ***************************************************************************/
-#define BCHP_AON_CTRL_SYSTEM_DATA_RAMi_ARRAY_BASE 0x00410200
-#define BCHP_AON_CTRL_SYSTEM_DATA_RAMi_ARRAY_START 0
-#define BCHP_AON_CTRL_SYSTEM_DATA_RAMi_ARRAY_END 255
-#define BCHP_AON_CTRL_SYSTEM_DATA_RAMi_ARRAY_ELEMENT_SIZE 32
-
-/***************************************************************************
- *SYSTEM_DATA_RAM%i - System Data RAM Address 0..255
- ***************************************************************************/
-/* AON_CTRL :: SYSTEM_DATA_RAMi :: SYSTEM_DATA_RAM [31:00] */
-#define BCHP_AON_CTRL_SYSTEM_DATA_RAMi_SYSTEM_DATA_RAM_MASK 0xffffffff
-#define BCHP_AON_CTRL_SYSTEM_DATA_RAMi_SYSTEM_DATA_RAM_SHIFT 0
-
-
-#endif /* #ifndef BCHP_AON_CTRL_H__ */
-
-/* End of File */
diff --git a/include/linux/brcmstb/7366b0/bchp_aon_pin_ctrl.h b/include/linux/brcmstb/7366b0/bchp_aon_pin_ctrl.h
deleted file mode 100644
index 8bf39d4..0000000
--- a/include/linux/brcmstb/7366b0/bchp_aon_pin_ctrl.h
+++ /dev/null
@@ -1,541 +0,0 @@
-/***************************************************************************
- * Copyright (c) 1999-2014, Broadcom Corporation
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
- *
- * Module Description:
- * DO NOT EDIT THIS FILE DIRECTLY
- *
- * This module was generated magically with RDB from a source description
- * file. You must edit the source file for changes to be made to this file.
- *
- *
- * Date: Generated on Thu Apr 24 03:08:54 2014
- * Full Compile MD5 Checksum 1af2c2cf28828ece5496e1312aac0166
- * (minus title and desc)
- * MD5 Checksum 3203ffce85e3fc9a10f84123e54057b0
- *
- * Compiled with: RDB Utility combo_header.pl
- * RDB Parser 3.0
- * unknown unknown
- * Perl Interpreter 5.008008
- * Operating System linux
- *
- * Revision History:
- *
- * $brcm_Log: $
- *
- ***************************************************************************/
-
-#ifndef BCHP_AON_PIN_CTRL_H__
-#define BCHP_AON_PIN_CTRL_H__
-
-/***************************************************************************
- *AON_PIN_CTRL - AON Pinmux Control Registers
- ***************************************************************************/
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0 0x00410700 /* Pinmux control register 0 */
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1 0x00410704 /* Pinmux control register 1 */
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2 0x00410708 /* Pinmux control register 2 */
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_3 0x0041070c /* Pinmux control register 3 */
-#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0 0x00410710 /* Pad pull-up/pull-down control register 0 */
-#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1 0x00410714 /* Pad pull-up/pull-down control register 1 */
-#define BCHP_AON_PIN_CTRL_BYP_CLK_UNSELECT_0 0x00410718 /* Bypass clock unselect register 0 */
-
-/***************************************************************************
- *PIN_MUX_CTRL_0 - Pinmux control register 0
- ***************************************************************************/
-/* AON_PIN_CTRL :: PIN_MUX_CTRL_0 :: aon_gpio_07 [31:28] */
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_07_MASK 0xf0000000
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_07_SHIFT 28
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_07_DEFAULT 0x00000000
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_07_AON_GPIO_07 0
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_07_LED_LS_0 1
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_07_LED_LD_12 2
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_07_TP_OUT_07 3
-
-/* AON_PIN_CTRL :: PIN_MUX_CTRL_0 :: aon_gpio_06 [27:24] */
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_06_MASK 0x0f000000
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_06_SHIFT 24
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_06_DEFAULT 0x00000000
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_06_AON_GPIO_06 0
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_06_LED_KD_3 1
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_06_LED_LD_11 2
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_06_I2S_LR0_OUT 3
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_06_ENET0_ACTIVITY 4
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_06_ENET2_LINK 5
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_06_TP_OUT_06 6
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_06_PM_AON_GPIO_06 7
-
-/* AON_PIN_CTRL :: PIN_MUX_CTRL_0 :: aon_gpio_05 [23:20] */
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_05_MASK 0x00f00000
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_05_SHIFT 20
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_05_DEFAULT 0x00000000
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_05_AON_GPIO_05 0
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_05_LED_KD_2 1
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_05_LED_LD_10 2
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_05_I2S_DATA0_OUT 3
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_05_SATA_MDIO 4
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_05_DSEC1_SELVTOP 5
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_05_PM_AON_GPIO_05 6
-
-/* AON_PIN_CTRL :: PIN_MUX_CTRL_0 :: aon_gpio_04 [19:16] */
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_04_MASK 0x000f0000
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_04_SHIFT 16
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_04_DEFAULT 0x00000000
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_04_AON_GPIO_04 0
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_04_LED_KD_1 1
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_04_LED_LD_9 2
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_04_I2S_CLK0_OUT 3
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_04_SATA_MDCLK 4
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_04_DSEC1_VCTL 5
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_04_PM_AON_GPIO_04 6
-
-/* AON_PIN_CTRL :: PIN_MUX_CTRL_0 :: aon_gpio_03 [15:12] */
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_03_MASK 0x0000f000
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_03_SHIFT 12
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_03_DEFAULT 0x00000000
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_03_AON_GPIO_03 0
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_03_LED_KD_0 1
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_03_LED_LD_8 2
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_03_TP_OUT_03 3
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_03_PM_AON_GPIO_03 4
-
-/* AON_PIN_CTRL :: PIN_MUX_CTRL_0 :: aon_gpio_02 [11:08] */
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_02_MASK 0x00000f00
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_02_SHIFT 8
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_02_DEFAULT 0x00000000
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_02_AON_GPIO_02 0
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_02_ENET1_LINK 1
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_02_AUD_FS_CLK1 2
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_02_VEC_VSYNC 3
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_02_TSIO_VCTRL 4
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_02_ENET0_ACTIVITY 5
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_02_TP_OUT_02 6
-
-/* AON_PIN_CTRL :: PIN_MUX_CTRL_0 :: aon_gpio_01 [07:04] */
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_01_MASK 0x000000f0
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_01_SHIFT 4
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_01_DEFAULT 0x00000000
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_01_AON_GPIO_01 0
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_01_ENET0_LINK 1
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_01_PWM0 2
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_01_VEC_HSYNC 3
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_01_SPI_M_SS1B 4
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_01_ENET1_ACTIVITY 5
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_01_TP_OUT_01 6
-
-/* AON_PIN_CTRL :: PIN_MUX_CTRL_0 :: aon_gpio_00 [03:00] */
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_00_MASK 0x0000000f
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_00_SHIFT 0
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_00_DEFAULT 0x00000000
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_00_AON_GPIO_00 0
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_00_IR_INT 1
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_00_PWM1 2
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_00_SPI_M_SS2B 3
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_00_TSIO_VCTRL 4
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_00_ENET2_ACTIVITY 5
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_00_TP_OUT_00 6
-
-/***************************************************************************
- *PIN_MUX_CTRL_1 - Pinmux control register 1
- ***************************************************************************/
-/* AON_PIN_CTRL :: PIN_MUX_CTRL_1 :: aon_gpio_15 [31:28] */
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_15_MASK 0xf0000000
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_15_SHIFT 28
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_15_DEFAULT 0x00000000
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_15_AON_GPIO_15 0
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_15_LED_LD_3 1
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_15_UART_CTS_1 2
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_15_I2S_LR0_IN 3
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_15_SPI_S_MISO 4
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_15_PWM2 5
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_15_DSEC0_SELVTOP 6
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_15_TP_OUT_13 7
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_15_PM_AON_GPIO_15 8
-
-/* AON_PIN_CTRL :: PIN_MUX_CTRL_1 :: aon_gpio_14 [27:24] */
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_14_MASK 0x0f000000
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_14_SHIFT 24
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_14_DEFAULT 0x00000000
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_14_AON_GPIO_14 0
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_14_LED_LD_2 1
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_14_UART_RTS_1 2
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_14_ENET2_ACTIVITY 3
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_14_SPI_S_SS0B 4
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_14_PWM3 5
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_14_DSEC0_VCTL 6
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_14_TP_OUT_12 7
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_14_PM_AON_GPIO_14 8
-
-/* AON_PIN_CTRL :: PIN_MUX_CTRL_1 :: aon_gpio_13 [23:20] */
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_13_MASK 0x00f00000
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_13_SHIFT 20
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_13_DEFAULT 0x00000000
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_13_AON_GPIO_13 0
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_13_LED_LD_1 1
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_13_UART_TXD_1 2
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_13_ENET0_LINK 3
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_13_TSPI_S0_MISO 4
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_13_ALT_TP_OUT_00 5
-
-/* AON_PIN_CTRL :: PIN_MUX_CTRL_1 :: aon_gpio_12 [19:16] */
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_12_MASK 0x000f0000
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_12_SHIFT 16
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_12_DEFAULT 0x00000000
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_12_AON_GPIO_12 0
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_12_LED_LD_0 1
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_12_UART_RXD_1 2
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_12_I2S_CLK0_IN 3
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_12_IR_IN1 4
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_12_ENET1_ACTIVITY 5
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_12_ZIG_LNA_CTL 6
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_12_TP_IN_10 7
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_12_PM_AON_GPIO_12 8
-
-/* AON_PIN_CTRL :: PIN_MUX_CTRL_1 :: aon_gpio_11 [15:12] */
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_11_MASK 0x0000f000
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_11_SHIFT 12
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_11_DEFAULT 0x00000000
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_11_AON_GPIO_11 0
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_11_LED_LS_4 1
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_11_UART_CTS_0 2
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_11_I2S_DATA0_IN 3
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_11_ENET1_LINK 4
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_11_ZIG_ANT_SEL 5
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_11_TP_OUT_11 6
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_11_PM_AON_GPIO_11 7
-
-/* AON_PIN_CTRL :: PIN_MUX_CTRL_1 :: aon_gpio_10 [11:08] */
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_10_MASK 0x00000f00
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_10_SHIFT 8
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_10_DEFAULT 0x00000000
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_10_AON_GPIO_10 0
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_10_LED_LS_3 1
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_10_UART_RTS_0 2
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_10_LED_LD_15 3
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_10_TP_OUT_10 4
-
-/* AON_PIN_CTRL :: PIN_MUX_CTRL_1 :: aon_gpio_09 [07:04] */
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_09_MASK 0x000000f0
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_09_SHIFT 4
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_09_DEFAULT 0x00000000
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_09_AON_GPIO_09 0
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_09_LED_LS_2 1
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_09_LED_LD_14 2
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_09_SPI_M_SS2B 3
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_09_TP_OUT_09 4
-
-/* AON_PIN_CTRL :: PIN_MUX_CTRL_1 :: aon_gpio_08 [03:00] */
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_08_MASK 0x0000000f
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_08_SHIFT 0
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_08_DEFAULT 0x00000000
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_08_AON_GPIO_08 0
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_08_LED_LS_1 1
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_08_LED_LD_13 2
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_08_SPI_M_SS1B 3
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_08_TP_OUT_08 4
-
-/***************************************************************************
- *PIN_MUX_CTRL_2 - Pinmux control register 2
- ***************************************************************************/
-/* AON_PIN_CTRL :: PIN_MUX_CTRL_2 :: aon_sgpio_02 [31:28] */
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_sgpio_02_MASK 0xf0000000
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_sgpio_02_SHIFT 28
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_sgpio_02_DEFAULT 0x00000000
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_sgpio_02_AON_SGPIO_02 0
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_sgpio_02_BSC_M1_SCL 1
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_sgpio_02_HDMI_TX1_BSC_SCL 2
-
-/* AON_PIN_CTRL :: PIN_MUX_CTRL_2 :: aon_sgpio_01 [27:24] */
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_sgpio_01_MASK 0x0f000000
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_sgpio_01_SHIFT 24
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_sgpio_01_DEFAULT 0x00000000
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_sgpio_01_AON_SGPIO_01 0
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_sgpio_01_BSC_M0_SDA 1
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_sgpio_01_HDMI_TX0_BSC_SDA 2
-
-/* AON_PIN_CTRL :: PIN_MUX_CTRL_2 :: aon_sgpio_00 [23:20] */
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_sgpio_00_MASK 0x00f00000
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_sgpio_00_SHIFT 20
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_sgpio_00_DEFAULT 0x00000000
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_sgpio_00_AON_SGPIO_00 0
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_sgpio_00_BSC_M0_SCL 1
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_sgpio_00_HDMI_TX0_BSC_SCL 2
-
-/* AON_PIN_CTRL :: PIN_MUX_CTRL_2 :: aon_gpio_20 [19:16] */
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_20_MASK 0x000f0000
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_20_SHIFT 16
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_20_DEFAULT 0x00000001
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_20_AON_GPIO_20 0
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_20_LED_OUT 1
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_20_ENET1_LINK 2
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_20_CODEC_MCLK 3
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_20_RO_OBSRV 4
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_20_IR_IN1 5
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_20_TP_OUT_16 6
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_20_PM_AON_GPIO_20 7
-
-/* AON_PIN_CTRL :: PIN_MUX_CTRL_2 :: aon_gpio_19 [15:12] */
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_19_MASK 0x0000f000
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_19_SHIFT 12
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_19_DEFAULT 0x00000000
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_19_AON_GPIO_19 0
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_19_LED_LD_7 1
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_19_UART_RTS_2 2
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_19_SPI_M_SS0B 3
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_19_ENET2_LINK 4
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_19_ZIG_SECO 5
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_19_TP_OUT_15 6
-
-/* AON_PIN_CTRL :: PIN_MUX_CTRL_2 :: aon_gpio_18 [11:08] */
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_18_MASK 0x00000f00
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_18_SHIFT 8
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_18_DEFAULT 0x00000000
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_18_AON_GPIO_18 0
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_18_LED_LD_6 1
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_18_UART_CTS_2 2
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_18_SPI_M_MISO 3
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_18_ENET0_ACTIVITY 4
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_18_ENET1_ACTIVITY 5
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_18_ZIG_SECI_2 6
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_18_TP_OUT_14 7
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_18_PM_AON_GPIO_18 8
-
-/* AON_PIN_CTRL :: PIN_MUX_CTRL_2 :: aon_gpio_17 [07:04] */
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_17_MASK 0x000000f0
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_17_SHIFT 4
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_17_DEFAULT 0x00000000
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_17_AON_GPIO_17 0
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_17_LED_LD_5 1
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_17_UART_TXD_2 2
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_17_SPI_M_MOSI 3
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_17_ZIG_SECI_1 4
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_17_TSPI_S0_SS0B 5
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_17_ALT_TP_OUT_01 6
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_17_PM_AON_GPIO_17 7
-
-/* AON_PIN_CTRL :: PIN_MUX_CTRL_2 :: aon_gpio_16 [03:00] */
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_16_MASK 0x0000000f
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_16_SHIFT 0
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_16_DEFAULT 0x00000000
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_16_AON_GPIO_16 0
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_16_LED_LD_4 1
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_16_UART_RXD_2 2
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_16_SPI_M_SCK 3
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_16_ENET0_LINK 4
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_16_ENET1_LINK 5
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_16_ZIG_SECI_0 6
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_16_TP_IN_12 7
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_16_PM_AON_GPIO_16 8
-
-/***************************************************************************
- *PIN_MUX_CTRL_3 - Pinmux control register 3
- ***************************************************************************/
-/* AON_PIN_CTRL :: PIN_MUX_CTRL_3 :: reserved0 [31:20] */
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_3_reserved0_MASK 0xfff00000
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_3_reserved0_SHIFT 20
-
-/* AON_PIN_CTRL :: PIN_MUX_CTRL_3 :: aon_sgpio_07 [19:16] */
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_3_aon_sgpio_07_MASK 0x000f0000
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_3_aon_sgpio_07_SHIFT 16
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_3_aon_sgpio_07_DEFAULT 0x00000000
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_3_aon_sgpio_07_AON_SGPIO_07 0
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_3_aon_sgpio_07_BSC_M3_SDA 1
-
-/* AON_PIN_CTRL :: PIN_MUX_CTRL_3 :: aon_sgpio_06 [15:12] */
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_3_aon_sgpio_06_MASK 0x0000f000
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_3_aon_sgpio_06_SHIFT 12
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_3_aon_sgpio_06_DEFAULT 0x00000000
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_3_aon_sgpio_06_AON_SGPIO_06 0
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_3_aon_sgpio_06_BSC_M3_SCL 1
-
-/* AON_PIN_CTRL :: PIN_MUX_CTRL_3 :: aon_sgpio_05 [11:08] */
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_3_aon_sgpio_05_MASK 0x00000f00
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_3_aon_sgpio_05_SHIFT 8
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_3_aon_sgpio_05_DEFAULT 0x00000000
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_3_aon_sgpio_05_AON_SGPIO_05 0
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_3_aon_sgpio_05_BSC_M2_SDA 1
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_3_aon_sgpio_05_HDMI_RX_BSC_SDA 2
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_3_aon_sgpio_05_BSC_S1_SDA 3
-
-/* AON_PIN_CTRL :: PIN_MUX_CTRL_3 :: aon_sgpio_04 [07:04] */
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_3_aon_sgpio_04_MASK 0x000000f0
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_3_aon_sgpio_04_SHIFT 4
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_3_aon_sgpio_04_DEFAULT 0x00000000
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_3_aon_sgpio_04_AON_SGPIO_04 0
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_3_aon_sgpio_04_BSC_M2_SCL 1
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_3_aon_sgpio_04_HDMI_RX_BSC_SCL 2
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_3_aon_sgpio_04_BSC_S1_SCL 3
-
-/* AON_PIN_CTRL :: PIN_MUX_CTRL_3 :: aon_sgpio_03 [03:00] */
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_3_aon_sgpio_03_MASK 0x0000000f
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_3_aon_sgpio_03_SHIFT 0
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_3_aon_sgpio_03_DEFAULT 0x00000000
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_3_aon_sgpio_03_AON_SGPIO_03 0
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_3_aon_sgpio_03_BSC_M1_SDA 1
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_3_aon_sgpio_03_HDMI_TX1_BSC_SDA 2
-
-/***************************************************************************
- *PIN_MUX_PAD_CTRL_0 - Pad pull-up/pull-down control register 0
- ***************************************************************************/
-/* AON_PIN_CTRL :: PIN_MUX_PAD_CTRL_0 :: spare_pad_ctrl_0 [31:30] */
-#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_spare_pad_ctrl_0_MASK 0xc0000000
-#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_spare_pad_ctrl_0_SHIFT 30
-#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_spare_pad_ctrl_0_DEFAULT 0x00000000
-#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_spare_pad_ctrl_0_PULL_NONE 0
-#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_spare_pad_ctrl_0_PULL_DOWN 1
-#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_spare_pad_ctrl_0_PULL_UP 2
-
-/* AON_PIN_CTRL :: PIN_MUX_PAD_CTRL_0 :: reserved0 [29:28] */
-#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_reserved0_MASK 0x30000000
-#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_reserved0_SHIFT 28
-
-/* AON_PIN_CTRL :: PIN_MUX_PAD_CTRL_0 :: aon_gpio_12_pad_ctrl [27:26] */
-#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_12_pad_ctrl_MASK 0x0c000000
-#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_12_pad_ctrl_SHIFT 26
-#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_12_pad_ctrl_DEFAULT 0x00000001
-#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_12_pad_ctrl_PULL_NONE 0
-#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_12_pad_ctrl_PULL_DOWN 1
-#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_12_pad_ctrl_PULL_UP 2
-
-/* AON_PIN_CTRL :: PIN_MUX_PAD_CTRL_0 :: aon_gpio_11_pad_ctrl [25:24] */
-#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_11_pad_ctrl_MASK 0x03000000
-#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_11_pad_ctrl_SHIFT 24
-#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_11_pad_ctrl_DEFAULT 0x00000001
-#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_11_pad_ctrl_PULL_NONE 0
-#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_11_pad_ctrl_PULL_DOWN 1
-#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_11_pad_ctrl_PULL_UP 2
-
-/* AON_PIN_CTRL :: PIN_MUX_PAD_CTRL_0 :: reserved1 [23:16] */
-#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_reserved1_MASK 0x00ff0000
-#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_reserved1_SHIFT 16
-
-/* AON_PIN_CTRL :: PIN_MUX_PAD_CTRL_0 :: aon_gpio_06_pad_ctrl [15:14] */
-#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_06_pad_ctrl_MASK 0x0000c000
-#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_06_pad_ctrl_SHIFT 14
-#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_06_pad_ctrl_DEFAULT 0x00000001
-#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_06_pad_ctrl_PULL_NONE 0
-#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_06_pad_ctrl_PULL_DOWN 1
-#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_06_pad_ctrl_PULL_UP 2
-
-/* AON_PIN_CTRL :: PIN_MUX_PAD_CTRL_0 :: aon_gpio_05_pad_ctrl [13:12] */
-#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_05_pad_ctrl_MASK 0x00003000
-#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_05_pad_ctrl_SHIFT 12
-#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_05_pad_ctrl_DEFAULT 0x00000001
-#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_05_pad_ctrl_PULL_NONE 0
-#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_05_pad_ctrl_PULL_DOWN 1
-#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_05_pad_ctrl_PULL_UP 2
-
-/* AON_PIN_CTRL :: PIN_MUX_PAD_CTRL_0 :: aon_gpio_04_pad_ctrl [11:10] */
-#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_04_pad_ctrl_MASK 0x00000c00
-#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_04_pad_ctrl_SHIFT 10
-#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_04_pad_ctrl_DEFAULT 0x00000001
-#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_04_pad_ctrl_PULL_NONE 0
-#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_04_pad_ctrl_PULL_DOWN 1
-#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_04_pad_ctrl_PULL_UP 2
-
-/* AON_PIN_CTRL :: PIN_MUX_PAD_CTRL_0 :: aon_gpio_03_pad_ctrl [09:08] */
-#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_03_pad_ctrl_MASK 0x00000300
-#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_03_pad_ctrl_SHIFT 8
-#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_03_pad_ctrl_DEFAULT 0x00000001
-#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_03_pad_ctrl_PULL_NONE 0
-#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_03_pad_ctrl_PULL_DOWN 1
-#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_03_pad_ctrl_PULL_UP 2
-
-/* AON_PIN_CTRL :: PIN_MUX_PAD_CTRL_0 :: reserved2 [07:00] */
-#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_reserved2_MASK 0x000000ff
-#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_reserved2_SHIFT 0
-
-/***************************************************************************
- *PIN_MUX_PAD_CTRL_1 - Pad pull-up/pull-down control register 1
- ***************************************************************************/
-/* AON_PIN_CTRL :: PIN_MUX_PAD_CTRL_1 :: spare_pad_ctrl_1 [31:30] */
-#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_spare_pad_ctrl_1_MASK 0xc0000000
-#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_spare_pad_ctrl_1_SHIFT 30
-#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_spare_pad_ctrl_1_DEFAULT 0x00000000
-#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_spare_pad_ctrl_1_PULL_NONE 0
-#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_spare_pad_ctrl_1_PULL_DOWN 1
-#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_spare_pad_ctrl_1_PULL_UP 2
-
-/* AON_PIN_CTRL :: PIN_MUX_PAD_CTRL_1 :: reserved0 [29:14] */
-#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_reserved0_MASK 0x3fffc000
-#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_reserved0_SHIFT 14
-
-/* AON_PIN_CTRL :: PIN_MUX_PAD_CTRL_1 :: aon_gpio_20_pad_ctrl [13:12] */
-#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_20_pad_ctrl_MASK 0x00003000
-#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_20_pad_ctrl_SHIFT 12
-#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_20_pad_ctrl_DEFAULT 0x00000001
-#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_20_pad_ctrl_PULL_NONE 0
-#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_20_pad_ctrl_PULL_DOWN 1
-#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_20_pad_ctrl_PULL_UP 2
-
-/* AON_PIN_CTRL :: PIN_MUX_PAD_CTRL_1 :: reserved1 [11:10] */
-#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_reserved1_MASK 0x00000c00
-#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_reserved1_SHIFT 10
-
-/* AON_PIN_CTRL :: PIN_MUX_PAD_CTRL_1 :: aon_gpio_18_pad_ctrl [09:08] */
-#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_18_pad_ctrl_MASK 0x00000300
-#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_18_pad_ctrl_SHIFT 8
-#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_18_pad_ctrl_DEFAULT 0x00000001
-#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_18_pad_ctrl_PULL_NONE 0
-#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_18_pad_ctrl_PULL_DOWN 1
-#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_18_pad_ctrl_PULL_UP 2
-
-/* AON_PIN_CTRL :: PIN_MUX_PAD_CTRL_1 :: aon_gpio_17_pad_ctrl [07:06] */
-#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_17_pad_ctrl_MASK 0x000000c0
-#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_17_pad_ctrl_SHIFT 6
-#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_17_pad_ctrl_DEFAULT 0x00000001
-#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_17_pad_ctrl_PULL_NONE 0
-#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_17_pad_ctrl_PULL_DOWN 1
-#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_17_pad_ctrl_PULL_UP 2
-
-/* AON_PIN_CTRL :: PIN_MUX_PAD_CTRL_1 :: aon_gpio_16_pad_ctrl [05:04] */
-#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_16_pad_ctrl_MASK 0x00000030
-#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_16_pad_ctrl_SHIFT 4
-#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_16_pad_ctrl_DEFAULT 0x00000001
-#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_16_pad_ctrl_PULL_NONE 0
-#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_16_pad_ctrl_PULL_DOWN 1
-#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_16_pad_ctrl_PULL_UP 2
-
-/* AON_PIN_CTRL :: PIN_MUX_PAD_CTRL_1 :: aon_gpio_15_pad_ctrl [03:02] */
-#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_15_pad_ctrl_MASK 0x0000000c
-#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_15_pad_ctrl_SHIFT 2
-#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_15_pad_ctrl_DEFAULT 0x00000001
-#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_15_pad_ctrl_PULL_NONE 0
-#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_15_pad_ctrl_PULL_DOWN 1
-#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_15_pad_ctrl_PULL_UP 2
-
-/* AON_PIN_CTRL :: PIN_MUX_PAD_CTRL_1 :: aon_gpio_14_pad_ctrl [01:00] */
-#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_14_pad_ctrl_MASK 0x00000003
-#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_14_pad_ctrl_SHIFT 0
-#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_14_pad_ctrl_DEFAULT 0x00000001
-#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_14_pad_ctrl_PULL_NONE 0
-#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_14_pad_ctrl_PULL_DOWN 1
-#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_14_pad_ctrl_PULL_UP 2
-
-/***************************************************************************
- *BYP_CLK_UNSELECT_0 - Bypass clock unselect register 0
- ***************************************************************************/
-/* AON_PIN_CTRL :: BYP_CLK_UNSELECT_0 :: reserved0 [31:01] */
-#define BCHP_AON_PIN_CTRL_BYP_CLK_UNSELECT_0_reserved0_MASK 0xfffffffe
-#define BCHP_AON_PIN_CTRL_BYP_CLK_UNSELECT_0_reserved0_SHIFT 1
-
-/* AON_PIN_CTRL :: BYP_CLK_UNSELECT_0 :: unsel_byp_clk_on_aon_gpio_04 [00:00] */
-#define BCHP_AON_PIN_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_aon_gpio_04_MASK 0x00000001
-#define BCHP_AON_PIN_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_aon_gpio_04_SHIFT 0
-#define BCHP_AON_PIN_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_aon_gpio_04_DEFAULT 0x00000000
-
-#endif /* #ifndef BCHP_AON_PIN_CTRL_H__ */
-
-/* End of File */
diff --git a/include/linux/brcmstb/7366b0/bchp_aon_pm_l2.h b/include/linux/brcmstb/7366b0/bchp_aon_pm_l2.h
deleted file mode 100644
index 61377ea..0000000
--- a/include/linux/brcmstb/7366b0/bchp_aon_pm_l2.h
+++ /dev/null
@@ -1,1406 +0,0 @@
-/***************************************************************************
- * Copyright (c) 1999-2014, Broadcom Corporation
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
- *
- * Module Description:
- * DO NOT EDIT THIS FILE DIRECTLY
- *
- * This module was generated magically with RDB from a source description
- * file. You must edit the source file for changes to be made to this file.
- *
- *
- * Date: Generated on Thu Apr 24 03:08:55 2014
- * Full Compile MD5 Checksum 1af2c2cf28828ece5496e1312aac0166
- * (minus title and desc)
- * MD5 Checksum 3203ffce85e3fc9a10f84123e54057b0
- *
- * Compiled with: RDB Utility combo_header.pl
- * RDB Parser 3.0
- * unknown unknown
- * Perl Interpreter 5.008008
- * Operating System linux
- *
- * Revision History:
- *
- * $brcm_Log: $
- *
- ***************************************************************************/
-
-#ifndef BCHP_AON_PM_L2_H__
-#define BCHP_AON_PM_L2_H__
-
-/***************************************************************************
- *AON_PM_L2 - AON Power Management L2 Interrupt Controller Registers
- ***************************************************************************/
-#define BCHP_AON_PM_L2_CPU_STATUS 0x00410640 /* CPU interrupt Status Register */
-#define BCHP_AON_PM_L2_CPU_SET 0x00410644 /* CPU interrupt Set Register */
-#define BCHP_AON_PM_L2_CPU_CLEAR 0x00410648 /* CPU interrupt Clear Register */
-#define BCHP_AON_PM_L2_CPU_MASK_STATUS 0x0041064c /* CPU interrupt Mask Status Register */
-#define BCHP_AON_PM_L2_CPU_MASK_SET 0x00410650 /* CPU interrupt Mask Set Register */
-#define BCHP_AON_PM_L2_CPU_MASK_CLEAR 0x00410654 /* CPU interrupt Mask Clear Register */
-#define BCHP_AON_PM_L2_PCI_STATUS 0x00410658 /* PCI interrupt Status Register */
-#define BCHP_AON_PM_L2_PCI_SET 0x0041065c /* PCI interrupt Set Register */
-#define BCHP_AON_PM_L2_PCI_CLEAR 0x00410660 /* PCI interrupt Clear Register */
-#define BCHP_AON_PM_L2_PCI_MASK_STATUS 0x00410664 /* PCI interrupt Mask Status Register */
-#define BCHP_AON_PM_L2_PCI_MASK_SET 0x00410668 /* PCI interrupt Mask Set Register */
-#define BCHP_AON_PM_L2_PCI_MASK_CLEAR 0x0041066c /* PCI interrupt Mask Clear Register */
-
-/***************************************************************************
- *CPU_STATUS - CPU interrupt Status Register
- ***************************************************************************/
-/* AON_PM_L2 :: CPU_STATUS :: reserved0 [31:21] */
-#define BCHP_AON_PM_L2_CPU_STATUS_reserved0_MASK 0xffe00000
-#define BCHP_AON_PM_L2_CPU_STATUS_reserved0_SHIFT 21
-
-/* AON_PM_L2 :: CPU_STATUS :: SPARE_WAKEUP_EVENT_0 [20:20] */
-#define BCHP_AON_PM_L2_CPU_STATUS_SPARE_WAKEUP_EVENT_0_MASK 0x00100000
-#define BCHP_AON_PM_L2_CPU_STATUS_SPARE_WAKEUP_EVENT_0_SHIFT 20
-#define BCHP_AON_PM_L2_CPU_STATUS_SPARE_WAKEUP_EVENT_0_DEFAULT 0x00000000
-
-/* AON_PM_L2 :: CPU_STATUS :: FP_RESET [19:19] */
-#define BCHP_AON_PM_L2_CPU_STATUS_FP_RESET_MASK 0x00080000
-#define BCHP_AON_PM_L2_CPU_STATUS_FP_RESET_SHIFT 19
-#define BCHP_AON_PM_L2_CPU_STATUS_FP_RESET_DEFAULT 0x00000000
-
-/* AON_PM_L2 :: CPU_STATUS :: BOUNDARY_SCAN_REQ [18:18] */
-#define BCHP_AON_PM_L2_CPU_STATUS_BOUNDARY_SCAN_REQ_MASK 0x00040000
-#define BCHP_AON_PM_L2_CPU_STATUS_BOUNDARY_SCAN_REQ_SHIFT 18
-#define BCHP_AON_PM_L2_CPU_STATUS_BOUNDARY_SCAN_REQ_DEFAULT 0x00000000
-
-/* AON_PM_L2 :: CPU_STATUS :: LEAP [17:17] */
-#define BCHP_AON_PM_L2_CPU_STATUS_LEAP_MASK 0x00020000
-#define BCHP_AON_PM_L2_CPU_STATUS_LEAP_SHIFT 17
-#define BCHP_AON_PM_L2_CPU_STATUS_LEAP_DEFAULT 0x00000000
-
-/* AON_PM_L2 :: CPU_STATUS :: USB1 [16:16] */
-#define BCHP_AON_PM_L2_CPU_STATUS_USB1_MASK 0x00010000
-#define BCHP_AON_PM_L2_CPU_STATUS_USB1_SHIFT 16
-#define BCHP_AON_PM_L2_CPU_STATUS_USB1_DEFAULT 0x00000000
-
-/* AON_PM_L2 :: CPU_STATUS :: USB0 [15:15] */
-#define BCHP_AON_PM_L2_CPU_STATUS_USB0_MASK 0x00008000
-#define BCHP_AON_PM_L2_CPU_STATUS_USB0_SHIFT 15
-#define BCHP_AON_PM_L2_CPU_STATUS_USB0_DEFAULT 0x00000000
-
-/* AON_PM_L2 :: CPU_STATUS :: MOCA [14:14] */
-#define BCHP_AON_PM_L2_CPU_STATUS_MOCA_MASK 0x00004000
-#define BCHP_AON_PM_L2_CPU_STATUS_MOCA_SHIFT 14
-#define BCHP_AON_PM_L2_CPU_STATUS_MOCA_DEFAULT 0x00000000
-
-/* AON_PM_L2 :: CPU_STATUS :: DEMOD_XPT [13:13] */
-#define BCHP_AON_PM_L2_CPU_STATUS_DEMOD_XPT_MASK 0x00002000
-#define BCHP_AON_PM_L2_CPU_STATUS_DEMOD_XPT_SHIFT 13
-#define BCHP_AON_PM_L2_CPU_STATUS_DEMOD_XPT_DEFAULT 0x00000000
-
-/* AON_PM_L2 :: CPU_STATUS :: XPT_PMU [12:12] */
-#define BCHP_AON_PM_L2_CPU_STATUS_XPT_PMU_MASK 0x00001000
-#define BCHP_AON_PM_L2_CPU_STATUS_XPT_PMU_SHIFT 12
-#define BCHP_AON_PM_L2_CPU_STATUS_XPT_PMU_DEFAULT 0x00000000
-
-/* AON_PM_L2 :: CPU_STATUS :: CAP [11:11] */
-#define BCHP_AON_PM_L2_CPU_STATUS_CAP_MASK 0x00000800
-#define BCHP_AON_PM_L2_CPU_STATUS_CAP_SHIFT 11
-#define BCHP_AON_PM_L2_CPU_STATUS_CAP_DEFAULT 0x00000000
-
-/* AON_PM_L2 :: CPU_STATUS :: WOL_GENET2 [10:10] */
-#define BCHP_AON_PM_L2_CPU_STATUS_WOL_GENET2_MASK 0x00000400
-#define BCHP_AON_PM_L2_CPU_STATUS_WOL_GENET2_SHIFT 10
-#define BCHP_AON_PM_L2_CPU_STATUS_WOL_GENET2_DEFAULT 0x00000000
-
-/* AON_PM_L2 :: CPU_STATUS :: WOL_GENET1 [09:09] */
-#define BCHP_AON_PM_L2_CPU_STATUS_WOL_GENET1_MASK 0x00000200
-#define BCHP_AON_PM_L2_CPU_STATUS_WOL_GENET1_SHIFT 9
-#define BCHP_AON_PM_L2_CPU_STATUS_WOL_GENET1_DEFAULT 0x00000000
-
-/* AON_PM_L2 :: CPU_STATUS :: WOL_GENET0 [08:08] */
-#define BCHP_AON_PM_L2_CPU_STATUS_WOL_GENET0_MASK 0x00000100
-#define BCHP_AON_PM_L2_CPU_STATUS_WOL_GENET0_SHIFT 8
-#define BCHP_AON_PM_L2_CPU_STATUS_WOL_GENET0_DEFAULT 0x00000000
-
-/* AON_PM_L2 :: CPU_STATUS :: AVS_WATCHDOG [07:07] */
-#define BCHP_AON_PM_L2_CPU_STATUS_AVS_WATCHDOG_MASK 0x00000080
-#define BCHP_AON_PM_L2_CPU_STATUS_AVS_WATCHDOG_SHIFT 7
-#define BCHP_AON_PM_L2_CPU_STATUS_AVS_WATCHDOG_DEFAULT 0x00000000
-
-/* AON_PM_L2 :: CPU_STATUS :: RF4CE [06:06] */
-#define BCHP_AON_PM_L2_CPU_STATUS_RF4CE_MASK 0x00000040
-#define BCHP_AON_PM_L2_CPU_STATUS_RF4CE_SHIFT 6
-#define BCHP_AON_PM_L2_CPU_STATUS_RF4CE_DEFAULT 0x00000000
-
-/* AON_PM_L2 :: CPU_STATUS :: GPIO [05:05] */
-#define BCHP_AON_PM_L2_CPU_STATUS_GPIO_MASK 0x00000020
-#define BCHP_AON_PM_L2_CPU_STATUS_GPIO_SHIFT 5
-#define BCHP_AON_PM_L2_CPU_STATUS_GPIO_DEFAULT 0x00000000
-
-/* AON_PM_L2 :: CPU_STATUS :: NMI_B_INTR [04:04] */
-#define BCHP_AON_PM_L2_CPU_STATUS_NMI_B_INTR_MASK 0x00000010
-#define BCHP_AON_PM_L2_CPU_STATUS_NMI_B_INTR_SHIFT 4
-#define BCHP_AON_PM_L2_CPU_STATUS_NMI_B_INTR_DEFAULT 0x00000000
-
-/* AON_PM_L2 :: CPU_STATUS :: TIMER_INTR [03:03] */
-#define BCHP_AON_PM_L2_CPU_STATUS_TIMER_INTR_MASK 0x00000008
-#define BCHP_AON_PM_L2_CPU_STATUS_TIMER_INTR_SHIFT 3
-#define BCHP_AON_PM_L2_CPU_STATUS_TIMER_INTR_DEFAULT 0x00000000
-
-/* AON_PM_L2 :: CPU_STATUS :: KPD_INTR [02:02] */
-#define BCHP_AON_PM_L2_CPU_STATUS_KPD_INTR_MASK 0x00000004
-#define BCHP_AON_PM_L2_CPU_STATUS_KPD_INTR_SHIFT 2
-#define BCHP_AON_PM_L2_CPU_STATUS_KPD_INTR_DEFAULT 0x00000000
-
-/* AON_PM_L2 :: CPU_STATUS :: IRR_INTR [01:01] */
-#define BCHP_AON_PM_L2_CPU_STATUS_IRR_INTR_MASK 0x00000002
-#define BCHP_AON_PM_L2_CPU_STATUS_IRR_INTR_SHIFT 1
-#define BCHP_AON_PM_L2_CPU_STATUS_IRR_INTR_DEFAULT 0x00000000
-
-/* AON_PM_L2 :: CPU_STATUS :: CEC_INTR [00:00] */
-#define BCHP_AON_PM_L2_CPU_STATUS_CEC_INTR_MASK 0x00000001
-#define BCHP_AON_PM_L2_CPU_STATUS_CEC_INTR_SHIFT 0
-#define BCHP_AON_PM_L2_CPU_STATUS_CEC_INTR_DEFAULT 0x00000000
-
-/***************************************************************************
- *CPU_SET - CPU interrupt Set Register
- ***************************************************************************/
-/* AON_PM_L2 :: CPU_SET :: reserved0 [31:21] */
-#define BCHP_AON_PM_L2_CPU_SET_reserved0_MASK 0xffe00000
-#define BCHP_AON_PM_L2_CPU_SET_reserved0_SHIFT 21
-
-/* AON_PM_L2 :: CPU_SET :: SPARE_WAKEUP_EVENT_0 [20:20] */
-#define BCHP_AON_PM_L2_CPU_SET_SPARE_WAKEUP_EVENT_0_MASK 0x00100000
-#define BCHP_AON_PM_L2_CPU_SET_SPARE_WAKEUP_EVENT_0_SHIFT 20
-#define BCHP_AON_PM_L2_CPU_SET_SPARE_WAKEUP_EVENT_0_DEFAULT 0x00000000
-
-/* AON_PM_L2 :: CPU_SET :: FP_RESET [19:19] */
-#define BCHP_AON_PM_L2_CPU_SET_FP_RESET_MASK 0x00080000
-#define BCHP_AON_PM_L2_CPU_SET_FP_RESET_SHIFT 19
-#define BCHP_AON_PM_L2_CPU_SET_FP_RESET_DEFAULT 0x00000000
-
-/* AON_PM_L2 :: CPU_SET :: BOUNDARY_SCAN_REQ [18:18] */
-#define BCHP_AON_PM_L2_CPU_SET_BOUNDARY_SCAN_REQ_MASK 0x00040000
-#define BCHP_AON_PM_L2_CPU_SET_BOUNDARY_SCAN_REQ_SHIFT 18
-#define BCHP_AON_PM_L2_CPU_SET_BOUNDARY_SCAN_REQ_DEFAULT 0x00000000
-
-/* AON_PM_L2 :: CPU_SET :: LEAP [17:17] */
-#define BCHP_AON_PM_L2_CPU_SET_LEAP_MASK 0x00020000
-#define BCHP_AON_PM_L2_CPU_SET_LEAP_SHIFT 17
-#define BCHP_AON_PM_L2_CPU_SET_LEAP_DEFAULT 0x00000000
-
-/* AON_PM_L2 :: CPU_SET :: USB1 [16:16] */
-#define BCHP_AON_PM_L2_CPU_SET_USB1_MASK 0x00010000
-#define BCHP_AON_PM_L2_CPU_SET_USB1_SHIFT 16
-#define BCHP_AON_PM_L2_CPU_SET_USB1_DEFAULT 0x00000000
-
-/* AON_PM_L2 :: CPU_SET :: USB0 [15:15] */
-#define BCHP_AON_PM_L2_CPU_SET_USB0_MASK 0x00008000
-#define BCHP_AON_PM_L2_CPU_SET_USB0_SHIFT 15
-#define BCHP_AON_PM_L2_CPU_SET_USB0_DEFAULT 0x00000000
-
-/* AON_PM_L2 :: CPU_SET :: MOCA [14:14] */
-#define BCHP_AON_PM_L2_CPU_SET_MOCA_MASK 0x00004000
-#define BCHP_AON_PM_L2_CPU_SET_MOCA_SHIFT 14
-#define BCHP_AON_PM_L2_CPU_SET_MOCA_DEFAULT 0x00000000
-
-/* AON_PM_L2 :: CPU_SET :: DEMOD_XPT [13:13] */
-#define BCHP_AON_PM_L2_CPU_SET_DEMOD_XPT_MASK 0x00002000
-#define BCHP_AON_PM_L2_CPU_SET_DEMOD_XPT_SHIFT 13
-#define BCHP_AON_PM_L2_CPU_SET_DEMOD_XPT_DEFAULT 0x00000000
-
-/* AON_PM_L2 :: CPU_SET :: XPT_PMU [12:12] */
-#define BCHP_AON_PM_L2_CPU_SET_XPT_PMU_MASK 0x00001000
-#define BCHP_AON_PM_L2_CPU_SET_XPT_PMU_SHIFT 12
-#define BCHP_AON_PM_L2_CPU_SET_XPT_PMU_DEFAULT 0x00000000
-
-/* AON_PM_L2 :: CPU_SET :: CAP [11:11] */
-#define BCHP_AON_PM_L2_CPU_SET_CAP_MASK 0x00000800
-#define BCHP_AON_PM_L2_CPU_SET_CAP_SHIFT 11
-#define BCHP_AON_PM_L2_CPU_SET_CAP_DEFAULT 0x00000000
-
-/* AON_PM_L2 :: CPU_SET :: WOL_GENET2 [10:10] */
-#define BCHP_AON_PM_L2_CPU_SET_WOL_GENET2_MASK 0x00000400
-#define BCHP_AON_PM_L2_CPU_SET_WOL_GENET2_SHIFT 10
-#define BCHP_AON_PM_L2_CPU_SET_WOL_GENET2_DEFAULT 0x00000000
-
-/* AON_PM_L2 :: CPU_SET :: WOL_GENET1 [09:09] */
-#define BCHP_AON_PM_L2_CPU_SET_WOL_GENET1_MASK 0x00000200
-#define BCHP_AON_PM_L2_CPU_SET_WOL_GENET1_SHIFT 9
-#define BCHP_AON_PM_L2_CPU_SET_WOL_GENET1_DEFAULT 0x00000000
-
-/* AON_PM_L2 :: CPU_SET :: WOL_GENET0 [08:08] */
-#define BCHP_AON_PM_L2_CPU_SET_WOL_GENET0_MASK 0x00000100
-#define BCHP_AON_PM_L2_CPU_SET_WOL_GENET0_SHIFT 8
-#define BCHP_AON_PM_L2_CPU_SET_WOL_GENET0_DEFAULT 0x00000000
-
-/* AON_PM_L2 :: CPU_SET :: AVS_WATCHDOG [07:07] */
-#define BCHP_AON_PM_L2_CPU_SET_AVS_WATCHDOG_MASK 0x00000080
-#define BCHP_AON_PM_L2_CPU_SET_AVS_WATCHDOG_SHIFT 7
-#define BCHP_AON_PM_L2_CPU_SET_AVS_WATCHDOG_DEFAULT 0x00000000
-
-/* AON_PM_L2 :: CPU_SET :: RF4CE [06:06] */
-#define BCHP_AON_PM_L2_CPU_SET_RF4CE_MASK 0x00000040
-#define BCHP_AON_PM_L2_CPU_SET_RF4CE_SHIFT 6
-#define BCHP_AON_PM_L2_CPU_SET_RF4CE_DEFAULT 0x00000000
-
-/* AON_PM_L2 :: CPU_SET :: GPIO [05:05] */
-#define BCHP_AON_PM_L2_CPU_SET_GPIO_MASK 0x00000020
-#define BCHP_AON_PM_L2_CPU_SET_GPIO_SHIFT 5
-#define BCHP_AON_PM_L2_CPU_SET_GPIO_DEFAULT 0x00000000
-
-/* AON_PM_L2 :: CPU_SET :: NMI_B_INTR [04:04] */
-#define BCHP_AON_PM_L2_CPU_SET_NMI_B_INTR_MASK 0x00000010
-#define BCHP_AON_PM_L2_CPU_SET_NMI_B_INTR_SHIFT 4
-#define BCHP_AON_PM_L2_CPU_SET_NMI_B_INTR_DEFAULT 0x00000000
-
-/* AON_PM_L2 :: CPU_SET :: TIMER_INTR [03:03] */
-#define BCHP_AON_PM_L2_CPU_SET_TIMER_INTR_MASK 0x00000008
-#define BCHP_AON_PM_L2_CPU_SET_TIMER_INTR_SHIFT 3
-#define BCHP_AON_PM_L2_CPU_SET_TIMER_INTR_DEFAULT 0x00000000
-
-/* AON_PM_L2 :: CPU_SET :: KPD_INTR [02:02] */
-#define BCHP_AON_PM_L2_CPU_SET_KPD_INTR_MASK 0x00000004
-#define BCHP_AON_PM_L2_CPU_SET_KPD_INTR_SHIFT 2
-#define BCHP_AON_PM_L2_CPU_SET_KPD_INTR_DEFAULT 0x00000000
-
-/* AON_PM_L2 :: CPU_SET :: IRR_INTR [01:01] */
-#define BCHP_AON_PM_L2_CPU_SET_IRR_INTR_MASK 0x00000002
-#define BCHP_AON_PM_L2_CPU_SET_IRR_INTR_SHIFT 1
-#define BCHP_AON_PM_L2_CPU_SET_IRR_INTR_DEFAULT 0x00000000
-
-/* AON_PM_L2 :: CPU_SET :: CEC_INTR [00:00] */
-#define BCHP_AON_PM_L2_CPU_SET_CEC_INTR_MASK 0x00000001
-#define BCHP_AON_PM_L2_CPU_SET_CEC_INTR_SHIFT 0
-#define BCHP_AON_PM_L2_CPU_SET_CEC_INTR_DEFAULT 0x00000000
-
-/***************************************************************************
- *CPU_CLEAR - CPU interrupt Clear Register
- ***************************************************************************/
-/* AON_PM_L2 :: CPU_CLEAR :: reserved0 [31:21] */
-#define BCHP_AON_PM_L2_CPU_CLEAR_reserved0_MASK 0xffe00000
-#define BCHP_AON_PM_L2_CPU_CLEAR_reserved0_SHIFT 21
-
-/* AON_PM_L2 :: CPU_CLEAR :: SPARE_WAKEUP_EVENT_0 [20:20] */
-#define BCHP_AON_PM_L2_CPU_CLEAR_SPARE_WAKEUP_EVENT_0_MASK 0x00100000
-#define BCHP_AON_PM_L2_CPU_CLEAR_SPARE_WAKEUP_EVENT_0_SHIFT 20
-#define BCHP_AON_PM_L2_CPU_CLEAR_SPARE_WAKEUP_EVENT_0_DEFAULT 0x00000000
-
-/* AON_PM_L2 :: CPU_CLEAR :: FP_RESET [19:19] */
-#define BCHP_AON_PM_L2_CPU_CLEAR_FP_RESET_MASK 0x00080000
-#define BCHP_AON_PM_L2_CPU_CLEAR_FP_RESET_SHIFT 19
-#define BCHP_AON_PM_L2_CPU_CLEAR_FP_RESET_DEFAULT 0x00000000
-
-/* AON_PM_L2 :: CPU_CLEAR :: BOUNDARY_SCAN_REQ [18:18] */
-#define BCHP_AON_PM_L2_CPU_CLEAR_BOUNDARY_SCAN_REQ_MASK 0x00040000
-#define BCHP_AON_PM_L2_CPU_CLEAR_BOUNDARY_SCAN_REQ_SHIFT 18
-#define BCHP_AON_PM_L2_CPU_CLEAR_BOUNDARY_SCAN_REQ_DEFAULT 0x00000000
-
-/* AON_PM_L2 :: CPU_CLEAR :: LEAP [17:17] */
-#define BCHP_AON_PM_L2_CPU_CLEAR_LEAP_MASK 0x00020000
-#define BCHP_AON_PM_L2_CPU_CLEAR_LEAP_SHIFT 17
-#define BCHP_AON_PM_L2_CPU_CLEAR_LEAP_DEFAULT 0x00000000
-
-/* AON_PM_L2 :: CPU_CLEAR :: USB1 [16:16] */
-#define BCHP_AON_PM_L2_CPU_CLEAR_USB1_MASK 0x00010000
-#define BCHP_AON_PM_L2_CPU_CLEAR_USB1_SHIFT 16
-#define BCHP_AON_PM_L2_CPU_CLEAR_USB1_DEFAULT 0x00000000
-
-/* AON_PM_L2 :: CPU_CLEAR :: USB0 [15:15] */
-#define BCHP_AON_PM_L2_CPU_CLEAR_USB0_MASK 0x00008000
-#define BCHP_AON_PM_L2_CPU_CLEAR_USB0_SHIFT 15
-#define BCHP_AON_PM_L2_CPU_CLEAR_USB0_DEFAULT 0x00000000
-
-/* AON_PM_L2 :: CPU_CLEAR :: MOCA [14:14] */
-#define BCHP_AON_PM_L2_CPU_CLEAR_MOCA_MASK 0x00004000
-#define BCHP_AON_PM_L2_CPU_CLEAR_MOCA_SHIFT 14
-#define BCHP_AON_PM_L2_CPU_CLEAR_MOCA_DEFAULT 0x00000000
-
-/* AON_PM_L2 :: CPU_CLEAR :: DEMOD_XPT [13:13] */
-#define BCHP_AON_PM_L2_CPU_CLEAR_DEMOD_XPT_MASK 0x00002000
-#define BCHP_AON_PM_L2_CPU_CLEAR_DEMOD_XPT_SHIFT 13
-#define BCHP_AON_PM_L2_CPU_CLEAR_DEMOD_XPT_DEFAULT 0x00000000
-
-/* AON_PM_L2 :: CPU_CLEAR :: XPT_PMU [12:12] */
-#define BCHP_AON_PM_L2_CPU_CLEAR_XPT_PMU_MASK 0x00001000
-#define BCHP_AON_PM_L2_CPU_CLEAR_XPT_PMU_SHIFT 12
-#define BCHP_AON_PM_L2_CPU_CLEAR_XPT_PMU_DEFAULT 0x00000000
-
-/* AON_PM_L2 :: CPU_CLEAR :: CAP [11:11] */
-#define BCHP_AON_PM_L2_CPU_CLEAR_CAP_MASK 0x00000800
-#define BCHP_AON_PM_L2_CPU_CLEAR_CAP_SHIFT 11
-#define BCHP_AON_PM_L2_CPU_CLEAR_CAP_DEFAULT 0x00000000
-
-/* AON_PM_L2 :: CPU_CLEAR :: WOL_GENET2 [10:10] */
-#define BCHP_AON_PM_L2_CPU_CLEAR_WOL_GENET2_MASK 0x00000400
-#define BCHP_AON_PM_L2_CPU_CLEAR_WOL_GENET2_SHIFT 10
-#define BCHP_AON_PM_L2_CPU_CLEAR_WOL_GENET2_DEFAULT 0x00000000
-
-/* AON_PM_L2 :: CPU_CLEAR :: WOL_GENET1 [09:09] */
-#define BCHP_AON_PM_L2_CPU_CLEAR_WOL_GENET1_MASK 0x00000200
-#define BCHP_AON_PM_L2_CPU_CLEAR_WOL_GENET1_SHIFT 9
-#define BCHP_AON_PM_L2_CPU_CLEAR_WOL_GENET1_DEFAULT 0x00000000
-
-/* AON_PM_L2 :: CPU_CLEAR :: WOL_GENET0 [08:08] */
-#define BCHP_AON_PM_L2_CPU_CLEAR_WOL_GENET0_MASK 0x00000100
-#define BCHP_AON_PM_L2_CPU_CLEAR_WOL_GENET0_SHIFT 8
-#define BCHP_AON_PM_L2_CPU_CLEAR_WOL_GENET0_DEFAULT 0x00000000
-
-/* AON_PM_L2 :: CPU_CLEAR :: AVS_WATCHDOG [07:07] */
-#define BCHP_AON_PM_L2_CPU_CLEAR_AVS_WATCHDOG_MASK 0x00000080
-#define BCHP_AON_PM_L2_CPU_CLEAR_AVS_WATCHDOG_SHIFT 7
-#define BCHP_AON_PM_L2_CPU_CLEAR_AVS_WATCHDOG_DEFAULT 0x00000000
-
-/* AON_PM_L2 :: CPU_CLEAR :: RF4CE [06:06] */
-#define BCHP_AON_PM_L2_CPU_CLEAR_RF4CE_MASK 0x00000040
-#define BCHP_AON_PM_L2_CPU_CLEAR_RF4CE_SHIFT 6
-#define BCHP_AON_PM_L2_CPU_CLEAR_RF4CE_DEFAULT 0x00000000
-
-/* AON_PM_L2 :: CPU_CLEAR :: GPIO [05:05] */
-#define BCHP_AON_PM_L2_CPU_CLEAR_GPIO_MASK 0x00000020
-#define BCHP_AON_PM_L2_CPU_CLEAR_GPIO_SHIFT 5
-#define BCHP_AON_PM_L2_CPU_CLEAR_GPIO_DEFAULT 0x00000000
-
-/* AON_PM_L2 :: CPU_CLEAR :: NMI_B_INTR [04:04] */
-#define BCHP_AON_PM_L2_CPU_CLEAR_NMI_B_INTR_MASK 0x00000010
-#define BCHP_AON_PM_L2_CPU_CLEAR_NMI_B_INTR_SHIFT 4
-#define BCHP_AON_PM_L2_CPU_CLEAR_NMI_B_INTR_DEFAULT 0x00000000
-
-/* AON_PM_L2 :: CPU_CLEAR :: TIMER_INTR [03:03] */
-#define BCHP_AON_PM_L2_CPU_CLEAR_TIMER_INTR_MASK 0x00000008
-#define BCHP_AON_PM_L2_CPU_CLEAR_TIMER_INTR_SHIFT 3
-#define BCHP_AON_PM_L2_CPU_CLEAR_TIMER_INTR_DEFAULT 0x00000000
-
-/* AON_PM_L2 :: CPU_CLEAR :: KPD_INTR [02:02] */
-#define BCHP_AON_PM_L2_CPU_CLEAR_KPD_INTR_MASK 0x00000004
-#define BCHP_AON_PM_L2_CPU_CLEAR_KPD_INTR_SHIFT 2
-#define BCHP_AON_PM_L2_CPU_CLEAR_KPD_INTR_DEFAULT 0x00000000
-
-/* AON_PM_L2 :: CPU_CLEAR :: IRR_INTR [01:01] */
-#define BCHP_AON_PM_L2_CPU_CLEAR_IRR_INTR_MASK 0x00000002
-#define BCHP_AON_PM_L2_CPU_CLEAR_IRR_INTR_SHIFT 1
-#define BCHP_AON_PM_L2_CPU_CLEAR_IRR_INTR_DEFAULT 0x00000000
-
-/* AON_PM_L2 :: CPU_CLEAR :: CEC_INTR [00:00] */
-#define BCHP_AON_PM_L2_CPU_CLEAR_CEC_INTR_MASK 0x00000001
-#define BCHP_AON_PM_L2_CPU_CLEAR_CEC_INTR_SHIFT 0
-#define BCHP_AON_PM_L2_CPU_CLEAR_CEC_INTR_DEFAULT 0x00000000
-
-/***************************************************************************
- *CPU_MASK_STATUS - CPU interrupt Mask Status Register
- ***************************************************************************/
-/* AON_PM_L2 :: CPU_MASK_STATUS :: reserved0 [31:21] */
-#define BCHP_AON_PM_L2_CPU_MASK_STATUS_reserved0_MASK 0xffe00000
-#define BCHP_AON_PM_L2_CPU_MASK_STATUS_reserved0_SHIFT 21
-
-/* AON_PM_L2 :: CPU_MASK_STATUS :: SPARE_WAKEUP_EVENT_0 [20:20] */
-#define BCHP_AON_PM_L2_CPU_MASK_STATUS_SPARE_WAKEUP_EVENT_0_MASK 0x00100000
-#define BCHP_AON_PM_L2_CPU_MASK_STATUS_SPARE_WAKEUP_EVENT_0_SHIFT 20
-#define BCHP_AON_PM_L2_CPU_MASK_STATUS_SPARE_WAKEUP_EVENT_0_DEFAULT 0x00000001
-
-/* AON_PM_L2 :: CPU_MASK_STATUS :: FP_RESET [19:19] */
-#define BCHP_AON_PM_L2_CPU_MASK_STATUS_FP_RESET_MASK 0x00080000
-#define BCHP_AON_PM_L2_CPU_MASK_STATUS_FP_RESET_SHIFT 19
-#define BCHP_AON_PM_L2_CPU_MASK_STATUS_FP_RESET_DEFAULT 0x00000001
-
-/* AON_PM_L2 :: CPU_MASK_STATUS :: BOUNDARY_SCAN_REQ [18:18] */
-#define BCHP_AON_PM_L2_CPU_MASK_STATUS_BOUNDARY_SCAN_REQ_MASK 0x00040000
-#define BCHP_AON_PM_L2_CPU_MASK_STATUS_BOUNDARY_SCAN_REQ_SHIFT 18
-#define BCHP_AON_PM_L2_CPU_MASK_STATUS_BOUNDARY_SCAN_REQ_DEFAULT 0x00000001
-
-/* AON_PM_L2 :: CPU_MASK_STATUS :: LEAP [17:17] */
-#define BCHP_AON_PM_L2_CPU_MASK_STATUS_LEAP_MASK 0x00020000
-#define BCHP_AON_PM_L2_CPU_MASK_STATUS_LEAP_SHIFT 17
-#define BCHP_AON_PM_L2_CPU_MASK_STATUS_LEAP_DEFAULT 0x00000001
-
-/* AON_PM_L2 :: CPU_MASK_STATUS :: USB1 [16:16] */
-#define BCHP_AON_PM_L2_CPU_MASK_STATUS_USB1_MASK 0x00010000
-#define BCHP_AON_PM_L2_CPU_MASK_STATUS_USB1_SHIFT 16
-#define BCHP_AON_PM_L2_CPU_MASK_STATUS_USB1_DEFAULT 0x00000001
-
-/* AON_PM_L2 :: CPU_MASK_STATUS :: USB0 [15:15] */
-#define BCHP_AON_PM_L2_CPU_MASK_STATUS_USB0_MASK 0x00008000
-#define BCHP_AON_PM_L2_CPU_MASK_STATUS_USB0_SHIFT 15
-#define BCHP_AON_PM_L2_CPU_MASK_STATUS_USB0_DEFAULT 0x00000001
-
-/* AON_PM_L2 :: CPU_MASK_STATUS :: MOCA [14:14] */
-#define BCHP_AON_PM_L2_CPU_MASK_STATUS_MOCA_MASK 0x00004000
-#define BCHP_AON_PM_L2_CPU_MASK_STATUS_MOCA_SHIFT 14
-#define BCHP_AON_PM_L2_CPU_MASK_STATUS_MOCA_DEFAULT 0x00000001
-
-/* AON_PM_L2 :: CPU_MASK_STATUS :: DEMOD_XPT [13:13] */
-#define BCHP_AON_PM_L2_CPU_MASK_STATUS_DEMOD_XPT_MASK 0x00002000
-#define BCHP_AON_PM_L2_CPU_MASK_STATUS_DEMOD_XPT_SHIFT 13
-#define BCHP_AON_PM_L2_CPU_MASK_STATUS_DEMOD_XPT_DEFAULT 0x00000001
-
-/* AON_PM_L2 :: CPU_MASK_STATUS :: XPT_PMU [12:12] */
-#define BCHP_AON_PM_L2_CPU_MASK_STATUS_XPT_PMU_MASK 0x00001000
-#define BCHP_AON_PM_L2_CPU_MASK_STATUS_XPT_PMU_SHIFT 12
-#define BCHP_AON_PM_L2_CPU_MASK_STATUS_XPT_PMU_DEFAULT 0x00000001
-
-/* AON_PM_L2 :: CPU_MASK_STATUS :: CAP [11:11] */
-#define BCHP_AON_PM_L2_CPU_MASK_STATUS_CAP_MASK 0x00000800
-#define BCHP_AON_PM_L2_CPU_MASK_STATUS_CAP_SHIFT 11
-#define BCHP_AON_PM_L2_CPU_MASK_STATUS_CAP_DEFAULT 0x00000001
-
-/* AON_PM_L2 :: CPU_MASK_STATUS :: WOL_GENET2 [10:10] */
-#define BCHP_AON_PM_L2_CPU_MASK_STATUS_WOL_GENET2_MASK 0x00000400
-#define BCHP_AON_PM_L2_CPU_MASK_STATUS_WOL_GENET2_SHIFT 10
-#define BCHP_AON_PM_L2_CPU_MASK_STATUS_WOL_GENET2_DEFAULT 0x00000001
-
-/* AON_PM_L2 :: CPU_MASK_STATUS :: WOL_GENET1 [09:09] */
-#define BCHP_AON_PM_L2_CPU_MASK_STATUS_WOL_GENET1_MASK 0x00000200
-#define BCHP_AON_PM_L2_CPU_MASK_STATUS_WOL_GENET1_SHIFT 9
-#define BCHP_AON_PM_L2_CPU_MASK_STATUS_WOL_GENET1_DEFAULT 0x00000001
-
-/* AON_PM_L2 :: CPU_MASK_STATUS :: WOL_GENET0 [08:08] */
-#define BCHP_AON_PM_L2_CPU_MASK_STATUS_WOL_GENET0_MASK 0x00000100
-#define BCHP_AON_PM_L2_CPU_MASK_STATUS_WOL_GENET0_SHIFT 8
-#define BCHP_AON_PM_L2_CPU_MASK_STATUS_WOL_GENET0_DEFAULT 0x00000001
-
-/* AON_PM_L2 :: CPU_MASK_STATUS :: AVS_WATCHDOG [07:07] */
-#define BCHP_AON_PM_L2_CPU_MASK_STATUS_AVS_WATCHDOG_MASK 0x00000080
-#define BCHP_AON_PM_L2_CPU_MASK_STATUS_AVS_WATCHDOG_SHIFT 7
-#define BCHP_AON_PM_L2_CPU_MASK_STATUS_AVS_WATCHDOG_DEFAULT 0x00000001
-
-/* AON_PM_L2 :: CPU_MASK_STATUS :: RF4CE [06:06] */
-#define BCHP_AON_PM_L2_CPU_MASK_STATUS_RF4CE_MASK 0x00000040
-#define BCHP_AON_PM_L2_CPU_MASK_STATUS_RF4CE_SHIFT 6
-#define BCHP_AON_PM_L2_CPU_MASK_STATUS_RF4CE_DEFAULT 0x00000001
-
-/* AON_PM_L2 :: CPU_MASK_STATUS :: GPIO [05:05] */
-#define BCHP_AON_PM_L2_CPU_MASK_STATUS_GPIO_MASK 0x00000020
-#define BCHP_AON_PM_L2_CPU_MASK_STATUS_GPIO_SHIFT 5
-#define BCHP_AON_PM_L2_CPU_MASK_STATUS_GPIO_DEFAULT 0x00000001
-
-/* AON_PM_L2 :: CPU_MASK_STATUS :: NMI_B_INTR [04:04] */
-#define BCHP_AON_PM_L2_CPU_MASK_STATUS_NMI_B_INTR_MASK 0x00000010
-#define BCHP_AON_PM_L2_CPU_MASK_STATUS_NMI_B_INTR_SHIFT 4
-#define BCHP_AON_PM_L2_CPU_MASK_STATUS_NMI_B_INTR_DEFAULT 0x00000001
-
-/* AON_PM_L2 :: CPU_MASK_STATUS :: TIMER_INTR [03:03] */
-#define BCHP_AON_PM_L2_CPU_MASK_STATUS_TIMER_INTR_MASK 0x00000008
-#define BCHP_AON_PM_L2_CPU_MASK_STATUS_TIMER_INTR_SHIFT 3
-#define BCHP_AON_PM_L2_CPU_MASK_STATUS_TIMER_INTR_DEFAULT 0x00000001
-
-/* AON_PM_L2 :: CPU_MASK_STATUS :: KPD_INTR [02:02] */
-#define BCHP_AON_PM_L2_CPU_MASK_STATUS_KPD_INTR_MASK 0x00000004
-#define BCHP_AON_PM_L2_CPU_MASK_STATUS_KPD_INTR_SHIFT 2
-#define BCHP_AON_PM_L2_CPU_MASK_STATUS_KPD_INTR_DEFAULT 0x00000001
-
-/* AON_PM_L2 :: CPU_MASK_STATUS :: IRR_INTR [01:01] */
-#define BCHP_AON_PM_L2_CPU_MASK_STATUS_IRR_INTR_MASK 0x00000002
-#define BCHP_AON_PM_L2_CPU_MASK_STATUS_IRR_INTR_SHIFT 1
-#define BCHP_AON_PM_L2_CPU_MASK_STATUS_IRR_INTR_DEFAULT 0x00000001
-
-/* AON_PM_L2 :: CPU_MASK_STATUS :: CEC_INTR [00:00] */
-#define BCHP_AON_PM_L2_CPU_MASK_STATUS_CEC_INTR_MASK 0x00000001
-#define BCHP_AON_PM_L2_CPU_MASK_STATUS_CEC_INTR_SHIFT 0
-#define BCHP_AON_PM_L2_CPU_MASK_STATUS_CEC_INTR_DEFAULT 0x00000001
-
-/***************************************************************************
- *CPU_MASK_SET - CPU interrupt Mask Set Register
- ***************************************************************************/
-/* AON_PM_L2 :: CPU_MASK_SET :: reserved0 [31:21] */
-#define BCHP_AON_PM_L2_CPU_MASK_SET_reserved0_MASK 0xffe00000
-#define BCHP_AON_PM_L2_CPU_MASK_SET_reserved0_SHIFT 21
-
-/* AON_PM_L2 :: CPU_MASK_SET :: SPARE_WAKEUP_EVENT_0 [20:20] */
-#define BCHP_AON_PM_L2_CPU_MASK_SET_SPARE_WAKEUP_EVENT_0_MASK 0x00100000
-#define BCHP_AON_PM_L2_CPU_MASK_SET_SPARE_WAKEUP_EVENT_0_SHIFT 20
-#define BCHP_AON_PM_L2_CPU_MASK_SET_SPARE_WAKEUP_EVENT_0_DEFAULT 0x00000001
-
-/* AON_PM_L2 :: CPU_MASK_SET :: FP_RESET [19:19] */
-#define BCHP_AON_PM_L2_CPU_MASK_SET_FP_RESET_MASK 0x00080000
-#define BCHP_AON_PM_L2_CPU_MASK_SET_FP_RESET_SHIFT 19
-#define BCHP_AON_PM_L2_CPU_MASK_SET_FP_RESET_DEFAULT 0x00000001
-
-/* AON_PM_L2 :: CPU_MASK_SET :: BOUNDARY_SCAN_REQ [18:18] */
-#define BCHP_AON_PM_L2_CPU_MASK_SET_BOUNDARY_SCAN_REQ_MASK 0x00040000
-#define BCHP_AON_PM_L2_CPU_MASK_SET_BOUNDARY_SCAN_REQ_SHIFT 18
-#define BCHP_AON_PM_L2_CPU_MASK_SET_BOUNDARY_SCAN_REQ_DEFAULT 0x00000001
-
-/* AON_PM_L2 :: CPU_MASK_SET :: LEAP [17:17] */
-#define BCHP_AON_PM_L2_CPU_MASK_SET_LEAP_MASK 0x00020000
-#define BCHP_AON_PM_L2_CPU_MASK_SET_LEAP_SHIFT 17
-#define BCHP_AON_PM_L2_CPU_MASK_SET_LEAP_DEFAULT 0x00000001
-
-/* AON_PM_L2 :: CPU_MASK_SET :: USB1 [16:16] */
-#define BCHP_AON_PM_L2_CPU_MASK_SET_USB1_MASK 0x00010000
-#define BCHP_AON_PM_L2_CPU_MASK_SET_USB1_SHIFT 16
-#define BCHP_AON_PM_L2_CPU_MASK_SET_USB1_DEFAULT 0x00000001
-
-/* AON_PM_L2 :: CPU_MASK_SET :: USB0 [15:15] */
-#define BCHP_AON_PM_L2_CPU_MASK_SET_USB0_MASK 0x00008000
-#define BCHP_AON_PM_L2_CPU_MASK_SET_USB0_SHIFT 15
-#define BCHP_AON_PM_L2_CPU_MASK_SET_USB0_DEFAULT 0x00000001
-
-/* AON_PM_L2 :: CPU_MASK_SET :: MOCA [14:14] */
-#define BCHP_AON_PM_L2_CPU_MASK_SET_MOCA_MASK 0x00004000
-#define BCHP_AON_PM_L2_CPU_MASK_SET_MOCA_SHIFT 14
-#define BCHP_AON_PM_L2_CPU_MASK_SET_MOCA_DEFAULT 0x00000001
-
-/* AON_PM_L2 :: CPU_MASK_SET :: DEMOD_XPT [13:13] */
-#define BCHP_AON_PM_L2_CPU_MASK_SET_DEMOD_XPT_MASK 0x00002000
-#define BCHP_AON_PM_L2_CPU_MASK_SET_DEMOD_XPT_SHIFT 13
-#define BCHP_AON_PM_L2_CPU_MASK_SET_DEMOD_XPT_DEFAULT 0x00000001
-
-/* AON_PM_L2 :: CPU_MASK_SET :: XPT_PMU [12:12] */
-#define BCHP_AON_PM_L2_CPU_MASK_SET_XPT_PMU_MASK 0x00001000
-#define BCHP_AON_PM_L2_CPU_MASK_SET_XPT_PMU_SHIFT 12
-#define BCHP_AON_PM_L2_CPU_MASK_SET_XPT_PMU_DEFAULT 0x00000001
-
-/* AON_PM_L2 :: CPU_MASK_SET :: CAP [11:11] */
-#define BCHP_AON_PM_L2_CPU_MASK_SET_CAP_MASK 0x00000800
-#define BCHP_AON_PM_L2_CPU_MASK_SET_CAP_SHIFT 11
-#define BCHP_AON_PM_L2_CPU_MASK_SET_CAP_DEFAULT 0x00000001
-
-/* AON_PM_L2 :: CPU_MASK_SET :: WOL_GENET2 [10:10] */
-#define BCHP_AON_PM_L2_CPU_MASK_SET_WOL_GENET2_MASK 0x00000400
-#define BCHP_AON_PM_L2_CPU_MASK_SET_WOL_GENET2_SHIFT 10
-#define BCHP_AON_PM_L2_CPU_MASK_SET_WOL_GENET2_DEFAULT 0x00000001
-
-/* AON_PM_L2 :: CPU_MASK_SET :: WOL_GENET1 [09:09] */
-#define BCHP_AON_PM_L2_CPU_MASK_SET_WOL_GENET1_MASK 0x00000200
-#define BCHP_AON_PM_L2_CPU_MASK_SET_WOL_GENET1_SHIFT 9
-#define BCHP_AON_PM_L2_CPU_MASK_SET_WOL_GENET1_DEFAULT 0x00000001
-
-/* AON_PM_L2 :: CPU_MASK_SET :: WOL_GENET0 [08:08] */
-#define BCHP_AON_PM_L2_CPU_MASK_SET_WOL_GENET0_MASK 0x00000100
-#define BCHP_AON_PM_L2_CPU_MASK_SET_WOL_GENET0_SHIFT 8
-#define BCHP_AON_PM_L2_CPU_MASK_SET_WOL_GENET0_DEFAULT 0x00000001
-
-/* AON_PM_L2 :: CPU_MASK_SET :: AVS_WATCHDOG [07:07] */
-#define BCHP_AON_PM_L2_CPU_MASK_SET_AVS_WATCHDOG_MASK 0x00000080
-#define BCHP_AON_PM_L2_CPU_MASK_SET_AVS_WATCHDOG_SHIFT 7
-#define BCHP_AON_PM_L2_CPU_MASK_SET_AVS_WATCHDOG_DEFAULT 0x00000001
-
-/* AON_PM_L2 :: CPU_MASK_SET :: RF4CE [06:06] */
-#define BCHP_AON_PM_L2_CPU_MASK_SET_RF4CE_MASK 0x00000040
-#define BCHP_AON_PM_L2_CPU_MASK_SET_RF4CE_SHIFT 6
-#define BCHP_AON_PM_L2_CPU_MASK_SET_RF4CE_DEFAULT 0x00000001
-
-/* AON_PM_L2 :: CPU_MASK_SET :: GPIO [05:05] */
-#define BCHP_AON_PM_L2_CPU_MASK_SET_GPIO_MASK 0x00000020
-#define BCHP_AON_PM_L2_CPU_MASK_SET_GPIO_SHIFT 5
-#define BCHP_AON_PM_L2_CPU_MASK_SET_GPIO_DEFAULT 0x00000001
-
-/* AON_PM_L2 :: CPU_MASK_SET :: NMI_B_INTR [04:04] */
-#define BCHP_AON_PM_L2_CPU_MASK_SET_NMI_B_INTR_MASK 0x00000010
-#define BCHP_AON_PM_L2_CPU_MASK_SET_NMI_B_INTR_SHIFT 4
-#define BCHP_AON_PM_L2_CPU_MASK_SET_NMI_B_INTR_DEFAULT 0x00000001
-
-/* AON_PM_L2 :: CPU_MASK_SET :: TIMER_INTR [03:03] */
-#define BCHP_AON_PM_L2_CPU_MASK_SET_TIMER_INTR_MASK 0x00000008
-#define BCHP_AON_PM_L2_CPU_MASK_SET_TIMER_INTR_SHIFT 3
-#define BCHP_AON_PM_L2_CPU_MASK_SET_TIMER_INTR_DEFAULT 0x00000001
-
-/* AON_PM_L2 :: CPU_MASK_SET :: KPD_INTR [02:02] */
-#define BCHP_AON_PM_L2_CPU_MASK_SET_KPD_INTR_MASK 0x00000004
-#define BCHP_AON_PM_L2_CPU_MASK_SET_KPD_INTR_SHIFT 2
-#define BCHP_AON_PM_L2_CPU_MASK_SET_KPD_INTR_DEFAULT 0x00000001
-
-/* AON_PM_L2 :: CPU_MASK_SET :: IRR_INTR [01:01] */
-#define BCHP_AON_PM_L2_CPU_MASK_SET_IRR_INTR_MASK 0x00000002
-#define BCHP_AON_PM_L2_CPU_MASK_SET_IRR_INTR_SHIFT 1
-#define BCHP_AON_PM_L2_CPU_MASK_SET_IRR_INTR_DEFAULT 0x00000001
-
-/* AON_PM_L2 :: CPU_MASK_SET :: CEC_INTR [00:00] */
-#define BCHP_AON_PM_L2_CPU_MASK_SET_CEC_INTR_MASK 0x00000001
-#define BCHP_AON_PM_L2_CPU_MASK_SET_CEC_INTR_SHIFT 0
-#define BCHP_AON_PM_L2_CPU_MASK_SET_CEC_INTR_DEFAULT 0x00000001
-
-/***************************************************************************
- *CPU_MASK_CLEAR - CPU interrupt Mask Clear Register
- ***************************************************************************/
-/* AON_PM_L2 :: CPU_MASK_CLEAR :: reserved0 [31:21] */
-#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_reserved0_MASK 0xffe00000
-#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_reserved0_SHIFT 21
-
-/* AON_PM_L2 :: CPU_MASK_CLEAR :: SPARE_WAKEUP_EVENT_0 [20:20] */
-#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_SPARE_WAKEUP_EVENT_0_MASK 0x00100000
-#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_SPARE_WAKEUP_EVENT_0_SHIFT 20
-#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_SPARE_WAKEUP_EVENT_0_DEFAULT 0x00000001
-
-/* AON_PM_L2 :: CPU_MASK_CLEAR :: FP_RESET [19:19] */
-#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_FP_RESET_MASK 0x00080000
-#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_FP_RESET_SHIFT 19
-#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_FP_RESET_DEFAULT 0x00000001
-
-/* AON_PM_L2 :: CPU_MASK_CLEAR :: BOUNDARY_SCAN_REQ [18:18] */
-#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_BOUNDARY_SCAN_REQ_MASK 0x00040000
-#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_BOUNDARY_SCAN_REQ_SHIFT 18
-#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_BOUNDARY_SCAN_REQ_DEFAULT 0x00000001
-
-/* AON_PM_L2 :: CPU_MASK_CLEAR :: LEAP [17:17] */
-#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_LEAP_MASK 0x00020000
-#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_LEAP_SHIFT 17
-#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_LEAP_DEFAULT 0x00000001
-
-/* AON_PM_L2 :: CPU_MASK_CLEAR :: USB1 [16:16] */
-#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_USB1_MASK 0x00010000
-#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_USB1_SHIFT 16
-#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_USB1_DEFAULT 0x00000001
-
-/* AON_PM_L2 :: CPU_MASK_CLEAR :: USB0 [15:15] */
-#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_USB0_MASK 0x00008000
-#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_USB0_SHIFT 15
-#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_USB0_DEFAULT 0x00000001
-
-/* AON_PM_L2 :: CPU_MASK_CLEAR :: MOCA [14:14] */
-#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_MOCA_MASK 0x00004000
-#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_MOCA_SHIFT 14
-#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_MOCA_DEFAULT 0x00000001
-
-/* AON_PM_L2 :: CPU_MASK_CLEAR :: DEMOD_XPT [13:13] */
-#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_DEMOD_XPT_MASK 0x00002000
-#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_DEMOD_XPT_SHIFT 13
-#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_DEMOD_XPT_DEFAULT 0x00000001
-
-/* AON_PM_L2 :: CPU_MASK_CLEAR :: XPT_PMU [12:12] */
-#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_XPT_PMU_MASK 0x00001000
-#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_XPT_PMU_SHIFT 12
-#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_XPT_PMU_DEFAULT 0x00000001
-
-/* AON_PM_L2 :: CPU_MASK_CLEAR :: CAP [11:11] */
-#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_CAP_MASK 0x00000800
-#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_CAP_SHIFT 11
-#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_CAP_DEFAULT 0x00000001
-
-/* AON_PM_L2 :: CPU_MASK_CLEAR :: WOL_GENET2 [10:10] */
-#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_WOL_GENET2_MASK 0x00000400
-#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_WOL_GENET2_SHIFT 10
-#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_WOL_GENET2_DEFAULT 0x00000001
-
-/* AON_PM_L2 :: CPU_MASK_CLEAR :: WOL_GENET1 [09:09] */
-#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_WOL_GENET1_MASK 0x00000200
-#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_WOL_GENET1_SHIFT 9
-#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_WOL_GENET1_DEFAULT 0x00000001
-
-/* AON_PM_L2 :: CPU_MASK_CLEAR :: WOL_GENET0 [08:08] */
-#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_WOL_GENET0_MASK 0x00000100
-#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_WOL_GENET0_SHIFT 8
-#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_WOL_GENET0_DEFAULT 0x00000001
-
-/* AON_PM_L2 :: CPU_MASK_CLEAR :: AVS_WATCHDOG [07:07] */
-#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_AVS_WATCHDOG_MASK 0x00000080
-#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_AVS_WATCHDOG_SHIFT 7
-#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_AVS_WATCHDOG_DEFAULT 0x00000001
-
-/* AON_PM_L2 :: CPU_MASK_CLEAR :: RF4CE [06:06] */
-#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_RF4CE_MASK 0x00000040
-#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_RF4CE_SHIFT 6
-#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_RF4CE_DEFAULT 0x00000001
-
-/* AON_PM_L2 :: CPU_MASK_CLEAR :: GPIO [05:05] */
-#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_GPIO_MASK 0x00000020
-#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_GPIO_SHIFT 5
-#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_GPIO_DEFAULT 0x00000001
-
-/* AON_PM_L2 :: CPU_MASK_CLEAR :: NMI_B_INTR [04:04] */
-#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_NMI_B_INTR_MASK 0x00000010
-#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_NMI_B_INTR_SHIFT 4
-#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_NMI_B_INTR_DEFAULT 0x00000001
-
-/* AON_PM_L2 :: CPU_MASK_CLEAR :: TIMER_INTR [03:03] */
-#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_TIMER_INTR_MASK 0x00000008
-#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_TIMER_INTR_SHIFT 3
-#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_TIMER_INTR_DEFAULT 0x00000001
-
-/* AON_PM_L2 :: CPU_MASK_CLEAR :: KPD_INTR [02:02] */
-#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_KPD_INTR_MASK 0x00000004
-#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_KPD_INTR_SHIFT 2
-#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_KPD_INTR_DEFAULT 0x00000001
-
-/* AON_PM_L2 :: CPU_MASK_CLEAR :: IRR_INTR [01:01] */
-#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_IRR_INTR_MASK 0x00000002
-#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_IRR_INTR_SHIFT 1
-#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_IRR_INTR_DEFAULT 0x00000001
-
-/* AON_PM_L2 :: CPU_MASK_CLEAR :: CEC_INTR [00:00] */
-#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_CEC_INTR_MASK 0x00000001
-#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_CEC_INTR_SHIFT 0
-#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_CEC_INTR_DEFAULT 0x00000001
-
-/***************************************************************************
- *PCI_STATUS - PCI interrupt Status Register
- ***************************************************************************/
-/* AON_PM_L2 :: PCI_STATUS :: reserved0 [31:21] */
-#define BCHP_AON_PM_L2_PCI_STATUS_reserved0_MASK 0xffe00000
-#define BCHP_AON_PM_L2_PCI_STATUS_reserved0_SHIFT 21
-
-/* AON_PM_L2 :: PCI_STATUS :: SPARE_WAKEUP_EVENT_0 [20:20] */
-#define BCHP_AON_PM_L2_PCI_STATUS_SPARE_WAKEUP_EVENT_0_MASK 0x00100000
-#define BCHP_AON_PM_L2_PCI_STATUS_SPARE_WAKEUP_EVENT_0_SHIFT 20
-#define BCHP_AON_PM_L2_PCI_STATUS_SPARE_WAKEUP_EVENT_0_DEFAULT 0x00000000
-
-/* AON_PM_L2 :: PCI_STATUS :: FP_RESET [19:19] */
-#define BCHP_AON_PM_L2_PCI_STATUS_FP_RESET_MASK 0x00080000
-#define BCHP_AON_PM_L2_PCI_STATUS_FP_RESET_SHIFT 19
-#define BCHP_AON_PM_L2_PCI_STATUS_FP_RESET_DEFAULT 0x00000000
-
-/* AON_PM_L2 :: PCI_STATUS :: BOUNDARY_SCAN_REQ [18:18] */
-#define BCHP_AON_PM_L2_PCI_STATUS_BOUNDARY_SCAN_REQ_MASK 0x00040000
-#define BCHP_AON_PM_L2_PCI_STATUS_BOUNDARY_SCAN_REQ_SHIFT 18
-#define BCHP_AON_PM_L2_PCI_STATUS_BOUNDARY_SCAN_REQ_DEFAULT 0x00000000
-
-/* AON_PM_L2 :: PCI_STATUS :: LEAP [17:17] */
-#define BCHP_AON_PM_L2_PCI_STATUS_LEAP_MASK 0x00020000
-#define BCHP_AON_PM_L2_PCI_STATUS_LEAP_SHIFT 17
-#define BCHP_AON_PM_L2_PCI_STATUS_LEAP_DEFAULT 0x00000000
-
-/* AON_PM_L2 :: PCI_STATUS :: USB1 [16:16] */
-#define BCHP_AON_PM_L2_PCI_STATUS_USB1_MASK 0x00010000
-#define BCHP_AON_PM_L2_PCI_STATUS_USB1_SHIFT 16
-#define BCHP_AON_PM_L2_PCI_STATUS_USB1_DEFAULT 0x00000000
-
-/* AON_PM_L2 :: PCI_STATUS :: USB0 [15:15] */
-#define BCHP_AON_PM_L2_PCI_STATUS_USB0_MASK 0x00008000
-#define BCHP_AON_PM_L2_PCI_STATUS_USB0_SHIFT 15
-#define BCHP_AON_PM_L2_PCI_STATUS_USB0_DEFAULT 0x00000000
-
-/* AON_PM_L2 :: PCI_STATUS :: MOCA [14:14] */
-#define BCHP_AON_PM_L2_PCI_STATUS_MOCA_MASK 0x00004000
-#define BCHP_AON_PM_L2_PCI_STATUS_MOCA_SHIFT 14
-#define BCHP_AON_PM_L2_PCI_STATUS_MOCA_DEFAULT 0x00000000
-
-/* AON_PM_L2 :: PCI_STATUS :: DEMOD_XPT [13:13] */
-#define BCHP_AON_PM_L2_PCI_STATUS_DEMOD_XPT_MASK 0x00002000
-#define BCHP_AON_PM_L2_PCI_STATUS_DEMOD_XPT_SHIFT 13
-#define BCHP_AON_PM_L2_PCI_STATUS_DEMOD_XPT_DEFAULT 0x00000000
-
-/* AON_PM_L2 :: PCI_STATUS :: XPT_PMU [12:12] */
-#define BCHP_AON_PM_L2_PCI_STATUS_XPT_PMU_MASK 0x00001000
-#define BCHP_AON_PM_L2_PCI_STATUS_XPT_PMU_SHIFT 12
-#define BCHP_AON_PM_L2_PCI_STATUS_XPT_PMU_DEFAULT 0x00000000
-
-/* AON_PM_L2 :: PCI_STATUS :: CAP [11:11] */
-#define BCHP_AON_PM_L2_PCI_STATUS_CAP_MASK 0x00000800
-#define BCHP_AON_PM_L2_PCI_STATUS_CAP_SHIFT 11
-#define BCHP_AON_PM_L2_PCI_STATUS_CAP_DEFAULT 0x00000000
-
-/* AON_PM_L2 :: PCI_STATUS :: WOL_GENET2 [10:10] */
-#define BCHP_AON_PM_L2_PCI_STATUS_WOL_GENET2_MASK 0x00000400
-#define BCHP_AON_PM_L2_PCI_STATUS_WOL_GENET2_SHIFT 10
-#define BCHP_AON_PM_L2_PCI_STATUS_WOL_GENET2_DEFAULT 0x00000000
-
-/* AON_PM_L2 :: PCI_STATUS :: WOL_GENET1 [09:09] */
-#define BCHP_AON_PM_L2_PCI_STATUS_WOL_GENET1_MASK 0x00000200
-#define BCHP_AON_PM_L2_PCI_STATUS_WOL_GENET1_SHIFT 9
-#define BCHP_AON_PM_L2_PCI_STATUS_WOL_GENET1_DEFAULT 0x00000000
-
-/* AON_PM_L2 :: PCI_STATUS :: WOL_GENET0 [08:08] */
-#define BCHP_AON_PM_L2_PCI_STATUS_WOL_GENET0_MASK 0x00000100
-#define BCHP_AON_PM_L2_PCI_STATUS_WOL_GENET0_SHIFT 8
-#define BCHP_AON_PM_L2_PCI_STATUS_WOL_GENET0_DEFAULT 0x00000000
-
-/* AON_PM_L2 :: PCI_STATUS :: AVS_WATCHDOG [07:07] */
-#define BCHP_AON_PM_L2_PCI_STATUS_AVS_WATCHDOG_MASK 0x00000080
-#define BCHP_AON_PM_L2_PCI_STATUS_AVS_WATCHDOG_SHIFT 7
-#define BCHP_AON_PM_L2_PCI_STATUS_AVS_WATCHDOG_DEFAULT 0x00000000
-
-/* AON_PM_L2 :: PCI_STATUS :: RF4CE [06:06] */
-#define BCHP_AON_PM_L2_PCI_STATUS_RF4CE_MASK 0x00000040
-#define BCHP_AON_PM_L2_PCI_STATUS_RF4CE_SHIFT 6
-#define BCHP_AON_PM_L2_PCI_STATUS_RF4CE_DEFAULT 0x00000000
-
-/* AON_PM_L2 :: PCI_STATUS :: GPIO [05:05] */
-#define BCHP_AON_PM_L2_PCI_STATUS_GPIO_MASK 0x00000020
-#define BCHP_AON_PM_L2_PCI_STATUS_GPIO_SHIFT 5
-#define BCHP_AON_PM_L2_PCI_STATUS_GPIO_DEFAULT 0x00000000
-
-/* AON_PM_L2 :: PCI_STATUS :: NMI_B_INTR [04:04] */
-#define BCHP_AON_PM_L2_PCI_STATUS_NMI_B_INTR_MASK 0x00000010
-#define BCHP_AON_PM_L2_PCI_STATUS_NMI_B_INTR_SHIFT 4
-#define BCHP_AON_PM_L2_PCI_STATUS_NMI_B_INTR_DEFAULT 0x00000000
-
-/* AON_PM_L2 :: PCI_STATUS :: TIMER_INTR [03:03] */
-#define BCHP_AON_PM_L2_PCI_STATUS_TIMER_INTR_MASK 0x00000008
-#define BCHP_AON_PM_L2_PCI_STATUS_TIMER_INTR_SHIFT 3
-#define BCHP_AON_PM_L2_PCI_STATUS_TIMER_INTR_DEFAULT 0x00000000
-
-/* AON_PM_L2 :: PCI_STATUS :: KPD_INTR [02:02] */
-#define BCHP_AON_PM_L2_PCI_STATUS_KPD_INTR_MASK 0x00000004
-#define BCHP_AON_PM_L2_PCI_STATUS_KPD_INTR_SHIFT 2
-#define BCHP_AON_PM_L2_PCI_STATUS_KPD_INTR_DEFAULT 0x00000000
-
-/* AON_PM_L2 :: PCI_STATUS :: IRR_INTR [01:01] */
-#define BCHP_AON_PM_L2_PCI_STATUS_IRR_INTR_MASK 0x00000002
-#define BCHP_AON_PM_L2_PCI_STATUS_IRR_INTR_SHIFT 1
-#define BCHP_AON_PM_L2_PCI_STATUS_IRR_INTR_DEFAULT 0x00000000
-
-/* AON_PM_L2 :: PCI_STATUS :: CEC_INTR [00:00] */
-#define BCHP_AON_PM_L2_PCI_STATUS_CEC_INTR_MASK 0x00000001
-#define BCHP_AON_PM_L2_PCI_STATUS_CEC_INTR_SHIFT 0
-#define BCHP_AON_PM_L2_PCI_STATUS_CEC_INTR_DEFAULT 0x00000000
-
-/***************************************************************************
- *PCI_SET - PCI interrupt Set Register
- ***************************************************************************/
-/* AON_PM_L2 :: PCI_SET :: reserved0 [31:21] */
-#define BCHP_AON_PM_L2_PCI_SET_reserved0_MASK 0xffe00000
-#define BCHP_AON_PM_L2_PCI_SET_reserved0_SHIFT 21
-
-/* AON_PM_L2 :: PCI_SET :: SPARE_WAKEUP_EVENT_0 [20:20] */
-#define BCHP_AON_PM_L2_PCI_SET_SPARE_WAKEUP_EVENT_0_MASK 0x00100000
-#define BCHP_AON_PM_L2_PCI_SET_SPARE_WAKEUP_EVENT_0_SHIFT 20
-#define BCHP_AON_PM_L2_PCI_SET_SPARE_WAKEUP_EVENT_0_DEFAULT 0x00000000
-
-/* AON_PM_L2 :: PCI_SET :: FP_RESET [19:19] */
-#define BCHP_AON_PM_L2_PCI_SET_FP_RESET_MASK 0x00080000
-#define BCHP_AON_PM_L2_PCI_SET_FP_RESET_SHIFT 19
-#define BCHP_AON_PM_L2_PCI_SET_FP_RESET_DEFAULT 0x00000000
-
-/* AON_PM_L2 :: PCI_SET :: BOUNDARY_SCAN_REQ [18:18] */
-#define BCHP_AON_PM_L2_PCI_SET_BOUNDARY_SCAN_REQ_MASK 0x00040000
-#define BCHP_AON_PM_L2_PCI_SET_BOUNDARY_SCAN_REQ_SHIFT 18
-#define BCHP_AON_PM_L2_PCI_SET_BOUNDARY_SCAN_REQ_DEFAULT 0x00000000
-
-/* AON_PM_L2 :: PCI_SET :: LEAP [17:17] */
-#define BCHP_AON_PM_L2_PCI_SET_LEAP_MASK 0x00020000
-#define BCHP_AON_PM_L2_PCI_SET_LEAP_SHIFT 17
-#define BCHP_AON_PM_L2_PCI_SET_LEAP_DEFAULT 0x00000000
-
-/* AON_PM_L2 :: PCI_SET :: USB1 [16:16] */
-#define BCHP_AON_PM_L2_PCI_SET_USB1_MASK 0x00010000
-#define BCHP_AON_PM_L2_PCI_SET_USB1_SHIFT 16
-#define BCHP_AON_PM_L2_PCI_SET_USB1_DEFAULT 0x00000000
-
-/* AON_PM_L2 :: PCI_SET :: USB0 [15:15] */
-#define BCHP_AON_PM_L2_PCI_SET_USB0_MASK 0x00008000
-#define BCHP_AON_PM_L2_PCI_SET_USB0_SHIFT 15
-#define BCHP_AON_PM_L2_PCI_SET_USB0_DEFAULT 0x00000000
-
-/* AON_PM_L2 :: PCI_SET :: MOCA [14:14] */
-#define BCHP_AON_PM_L2_PCI_SET_MOCA_MASK 0x00004000
-#define BCHP_AON_PM_L2_PCI_SET_MOCA_SHIFT 14
-#define BCHP_AON_PM_L2_PCI_SET_MOCA_DEFAULT 0x00000000
-
-/* AON_PM_L2 :: PCI_SET :: DEMOD_XPT [13:13] */
-#define BCHP_AON_PM_L2_PCI_SET_DEMOD_XPT_MASK 0x00002000
-#define BCHP_AON_PM_L2_PCI_SET_DEMOD_XPT_SHIFT 13
-#define BCHP_AON_PM_L2_PCI_SET_DEMOD_XPT_DEFAULT 0x00000000
-
-/* AON_PM_L2 :: PCI_SET :: XPT_PMU [12:12] */
-#define BCHP_AON_PM_L2_PCI_SET_XPT_PMU_MASK 0x00001000
-#define BCHP_AON_PM_L2_PCI_SET_XPT_PMU_SHIFT 12
-#define BCHP_AON_PM_L2_PCI_SET_XPT_PMU_DEFAULT 0x00000000
-
-/* AON_PM_L2 :: PCI_SET :: CAP [11:11] */
-#define BCHP_AON_PM_L2_PCI_SET_CAP_MASK 0x00000800
-#define BCHP_AON_PM_L2_PCI_SET_CAP_SHIFT 11
-#define BCHP_AON_PM_L2_PCI_SET_CAP_DEFAULT 0x00000000
-
-/* AON_PM_L2 :: PCI_SET :: WOL_GENET2 [10:10] */
-#define BCHP_AON_PM_L2_PCI_SET_WOL_GENET2_MASK 0x00000400
-#define BCHP_AON_PM_L2_PCI_SET_WOL_GENET2_SHIFT 10
-#define BCHP_AON_PM_L2_PCI_SET_WOL_GENET2_DEFAULT 0x00000000
-
-/* AON_PM_L2 :: PCI_SET :: WOL_GENET1 [09:09] */
-#define BCHP_AON_PM_L2_PCI_SET_WOL_GENET1_MASK 0x00000200
-#define BCHP_AON_PM_L2_PCI_SET_WOL_GENET1_SHIFT 9
-#define BCHP_AON_PM_L2_PCI_SET_WOL_GENET1_DEFAULT 0x00000000
-
-/* AON_PM_L2 :: PCI_SET :: WOL_GENET0 [08:08] */
-#define BCHP_AON_PM_L2_PCI_SET_WOL_GENET0_MASK 0x00000100
-#define BCHP_AON_PM_L2_PCI_SET_WOL_GENET0_SHIFT 8
-#define BCHP_AON_PM_L2_PCI_SET_WOL_GENET0_DEFAULT 0x00000000
-
-/* AON_PM_L2 :: PCI_SET :: AVS_WATCHDOG [07:07] */
-#define BCHP_AON_PM_L2_PCI_SET_AVS_WATCHDOG_MASK 0x00000080
-#define BCHP_AON_PM_L2_PCI_SET_AVS_WATCHDOG_SHIFT 7
-#define BCHP_AON_PM_L2_PCI_SET_AVS_WATCHDOG_DEFAULT 0x00000000
-
-/* AON_PM_L2 :: PCI_SET :: RF4CE [06:06] */
-#define BCHP_AON_PM_L2_PCI_SET_RF4CE_MASK 0x00000040
-#define BCHP_AON_PM_L2_PCI_SET_RF4CE_SHIFT 6
-#define BCHP_AON_PM_L2_PCI_SET_RF4CE_DEFAULT 0x00000000
-
-/* AON_PM_L2 :: PCI_SET :: GPIO [05:05] */
-#define BCHP_AON_PM_L2_PCI_SET_GPIO_MASK 0x00000020
-#define BCHP_AON_PM_L2_PCI_SET_GPIO_SHIFT 5
-#define BCHP_AON_PM_L2_PCI_SET_GPIO_DEFAULT 0x00000000
-
-/* AON_PM_L2 :: PCI_SET :: NMI_B_INTR [04:04] */
-#define BCHP_AON_PM_L2_PCI_SET_NMI_B_INTR_MASK 0x00000010
-#define BCHP_AON_PM_L2_PCI_SET_NMI_B_INTR_SHIFT 4
-#define BCHP_AON_PM_L2_PCI_SET_NMI_B_INTR_DEFAULT 0x00000000
-
-/* AON_PM_L2 :: PCI_SET :: TIMER_INTR [03:03] */
-#define BCHP_AON_PM_L2_PCI_SET_TIMER_INTR_MASK 0x00000008
-#define BCHP_AON_PM_L2_PCI_SET_TIMER_INTR_SHIFT 3
-#define BCHP_AON_PM_L2_PCI_SET_TIMER_INTR_DEFAULT 0x00000000
-
-/* AON_PM_L2 :: PCI_SET :: KPD_INTR [02:02] */
-#define BCHP_AON_PM_L2_PCI_SET_KPD_INTR_MASK 0x00000004
-#define BCHP_AON_PM_L2_PCI_SET_KPD_INTR_SHIFT 2
-#define BCHP_AON_PM_L2_PCI_SET_KPD_INTR_DEFAULT 0x00000000
-
-/* AON_PM_L2 :: PCI_SET :: IRR_INTR [01:01] */
-#define BCHP_AON_PM_L2_PCI_SET_IRR_INTR_MASK 0x00000002
-#define BCHP_AON_PM_L2_PCI_SET_IRR_INTR_SHIFT 1
-#define BCHP_AON_PM_L2_PCI_SET_IRR_INTR_DEFAULT 0x00000000
-
-/* AON_PM_L2 :: PCI_SET :: CEC_INTR [00:00] */
-#define BCHP_AON_PM_L2_PCI_SET_CEC_INTR_MASK 0x00000001
-#define BCHP_AON_PM_L2_PCI_SET_CEC_INTR_SHIFT 0
-#define BCHP_AON_PM_L2_PCI_SET_CEC_INTR_DEFAULT 0x00000000
-
-/***************************************************************************
- *PCI_CLEAR - PCI interrupt Clear Register
- ***************************************************************************/
-/* AON_PM_L2 :: PCI_CLEAR :: reserved0 [31:21] */
-#define BCHP_AON_PM_L2_PCI_CLEAR_reserved0_MASK 0xffe00000
-#define BCHP_AON_PM_L2_PCI_CLEAR_reserved0_SHIFT 21
-
-/* AON_PM_L2 :: PCI_CLEAR :: SPARE_WAKEUP_EVENT_0 [20:20] */
-#define BCHP_AON_PM_L2_PCI_CLEAR_SPARE_WAKEUP_EVENT_0_MASK 0x00100000
-#define BCHP_AON_PM_L2_PCI_CLEAR_SPARE_WAKEUP_EVENT_0_SHIFT 20
-#define BCHP_AON_PM_L2_PCI_CLEAR_SPARE_WAKEUP_EVENT_0_DEFAULT 0x00000000
-
-/* AON_PM_L2 :: PCI_CLEAR :: FP_RESET [19:19] */
-#define BCHP_AON_PM_L2_PCI_CLEAR_FP_RESET_MASK 0x00080000
-#define BCHP_AON_PM_L2_PCI_CLEAR_FP_RESET_SHIFT 19
-#define BCHP_AON_PM_L2_PCI_CLEAR_FP_RESET_DEFAULT 0x00000000
-
-/* AON_PM_L2 :: PCI_CLEAR :: BOUNDARY_SCAN_REQ [18:18] */
-#define BCHP_AON_PM_L2_PCI_CLEAR_BOUNDARY_SCAN_REQ_MASK 0x00040000
-#define BCHP_AON_PM_L2_PCI_CLEAR_BOUNDARY_SCAN_REQ_SHIFT 18
-#define BCHP_AON_PM_L2_PCI_CLEAR_BOUNDARY_SCAN_REQ_DEFAULT 0x00000000
-
-/* AON_PM_L2 :: PCI_CLEAR :: LEAP [17:17] */
-#define BCHP_AON_PM_L2_PCI_CLEAR_LEAP_MASK 0x00020000
-#define BCHP_AON_PM_L2_PCI_CLEAR_LEAP_SHIFT 17
-#define BCHP_AON_PM_L2_PCI_CLEAR_LEAP_DEFAULT 0x00000000
-
-/* AON_PM_L2 :: PCI_CLEAR :: USB1 [16:16] */
-#define BCHP_AON_PM_L2_PCI_CLEAR_USB1_MASK 0x00010000
-#define BCHP_AON_PM_L2_PCI_CLEAR_USB1_SHIFT 16
-#define BCHP_AON_PM_L2_PCI_CLEAR_USB1_DEFAULT 0x00000000
-
-/* AON_PM_L2 :: PCI_CLEAR :: USB0 [15:15] */
-#define BCHP_AON_PM_L2_PCI_CLEAR_USB0_MASK 0x00008000
-#define BCHP_AON_PM_L2_PCI_CLEAR_USB0_SHIFT 15
-#define BCHP_AON_PM_L2_PCI_CLEAR_USB0_DEFAULT 0x00000000
-
-/* AON_PM_L2 :: PCI_CLEAR :: MOCA [14:14] */
-#define BCHP_AON_PM_L2_PCI_CLEAR_MOCA_MASK 0x00004000
-#define BCHP_AON_PM_L2_PCI_CLEAR_MOCA_SHIFT 14
-#define BCHP_AON_PM_L2_PCI_CLEAR_MOCA_DEFAULT 0x00000000
-
-/* AON_PM_L2 :: PCI_CLEAR :: DEMOD_XPT [13:13] */
-#define BCHP_AON_PM_L2_PCI_CLEAR_DEMOD_XPT_MASK 0x00002000
-#define BCHP_AON_PM_L2_PCI_CLEAR_DEMOD_XPT_SHIFT 13
-#define BCHP_AON_PM_L2_PCI_CLEAR_DEMOD_XPT_DEFAULT 0x00000000
-
-/* AON_PM_L2 :: PCI_CLEAR :: XPT_PMU [12:12] */
-#define BCHP_AON_PM_L2_PCI_CLEAR_XPT_PMU_MASK 0x00001000
-#define BCHP_AON_PM_L2_PCI_CLEAR_XPT_PMU_SHIFT 12
-#define BCHP_AON_PM_L2_PCI_CLEAR_XPT_PMU_DEFAULT 0x00000000
-
-/* AON_PM_L2 :: PCI_CLEAR :: CAP [11:11] */
-#define BCHP_AON_PM_L2_PCI_CLEAR_CAP_MASK 0x00000800
-#define BCHP_AON_PM_L2_PCI_CLEAR_CAP_SHIFT 11
-#define BCHP_AON_PM_L2_PCI_CLEAR_CAP_DEFAULT 0x00000000
-
-/* AON_PM_L2 :: PCI_CLEAR :: WOL_GENET2 [10:10] */
-#define BCHP_AON_PM_L2_PCI_CLEAR_WOL_GENET2_MASK 0x00000400
-#define BCHP_AON_PM_L2_PCI_CLEAR_WOL_GENET2_SHIFT 10
-#define BCHP_AON_PM_L2_PCI_CLEAR_WOL_GENET2_DEFAULT 0x00000000
-
-/* AON_PM_L2 :: PCI_CLEAR :: WOL_GENET1 [09:09] */
-#define BCHP_AON_PM_L2_PCI_CLEAR_WOL_GENET1_MASK 0x00000200
-#define BCHP_AON_PM_L2_PCI_CLEAR_WOL_GENET1_SHIFT 9
-#define BCHP_AON_PM_L2_PCI_CLEAR_WOL_GENET1_DEFAULT 0x00000000
-
-/* AON_PM_L2 :: PCI_CLEAR :: WOL_GENET0 [08:08] */
-#define BCHP_AON_PM_L2_PCI_CLEAR_WOL_GENET0_MASK 0x00000100
-#define BCHP_AON_PM_L2_PCI_CLEAR_WOL_GENET0_SHIFT 8
-#define BCHP_AON_PM_L2_PCI_CLEAR_WOL_GENET0_DEFAULT 0x00000000
-
-/* AON_PM_L2 :: PCI_CLEAR :: AVS_WATCHDOG [07:07] */
-#define BCHP_AON_PM_L2_PCI_CLEAR_AVS_WATCHDOG_MASK 0x00000080
-#define BCHP_AON_PM_L2_PCI_CLEAR_AVS_WATCHDOG_SHIFT 7
-#define BCHP_AON_PM_L2_PCI_CLEAR_AVS_WATCHDOG_DEFAULT 0x00000000
-
-/* AON_PM_L2 :: PCI_CLEAR :: RF4CE [06:06] */
-#define BCHP_AON_PM_L2_PCI_CLEAR_RF4CE_MASK 0x00000040
-#define BCHP_AON_PM_L2_PCI_CLEAR_RF4CE_SHIFT 6
-#define BCHP_AON_PM_L2_PCI_CLEAR_RF4CE_DEFAULT 0x00000000
-
-/* AON_PM_L2 :: PCI_CLEAR :: GPIO [05:05] */
-#define BCHP_AON_PM_L2_PCI_CLEAR_GPIO_MASK 0x00000020
-#define BCHP_AON_PM_L2_PCI_CLEAR_GPIO_SHIFT 5
-#define BCHP_AON_PM_L2_PCI_CLEAR_GPIO_DEFAULT 0x00000000
-
-/* AON_PM_L2 :: PCI_CLEAR :: NMI_B_INTR [04:04] */
-#define BCHP_AON_PM_L2_PCI_CLEAR_NMI_B_INTR_MASK 0x00000010
-#define BCHP_AON_PM_L2_PCI_CLEAR_NMI_B_INTR_SHIFT 4
-#define BCHP_AON_PM_L2_PCI_CLEAR_NMI_B_INTR_DEFAULT 0x00000000
-
-/* AON_PM_L2 :: PCI_CLEAR :: TIMER_INTR [03:03] */
-#define BCHP_AON_PM_L2_PCI_CLEAR_TIMER_INTR_MASK 0x00000008
-#define BCHP_AON_PM_L2_PCI_CLEAR_TIMER_INTR_SHIFT 3
-#define BCHP_AON_PM_L2_PCI_CLEAR_TIMER_INTR_DEFAULT 0x00000000
-
-/* AON_PM_L2 :: PCI_CLEAR :: KPD_INTR [02:02] */
-#define BCHP_AON_PM_L2_PCI_CLEAR_KPD_INTR_MASK 0x00000004
-#define BCHP_AON_PM_L2_PCI_CLEAR_KPD_INTR_SHIFT 2
-#define BCHP_AON_PM_L2_PCI_CLEAR_KPD_INTR_DEFAULT 0x00000000
-
-/* AON_PM_L2 :: PCI_CLEAR :: IRR_INTR [01:01] */
-#define BCHP_AON_PM_L2_PCI_CLEAR_IRR_INTR_MASK 0x00000002
-#define BCHP_AON_PM_L2_PCI_CLEAR_IRR_INTR_SHIFT 1
-#define BCHP_AON_PM_L2_PCI_CLEAR_IRR_INTR_DEFAULT 0x00000000
-
-/* AON_PM_L2 :: PCI_CLEAR :: CEC_INTR [00:00] */
-#define BCHP_AON_PM_L2_PCI_CLEAR_CEC_INTR_MASK 0x00000001
-#define BCHP_AON_PM_L2_PCI_CLEAR_CEC_INTR_SHIFT 0
-#define BCHP_AON_PM_L2_PCI_CLEAR_CEC_INTR_DEFAULT 0x00000000
-
-/***************************************************************************
- *PCI_MASK_STATUS - PCI interrupt Mask Status Register
- ***************************************************************************/
-/* AON_PM_L2 :: PCI_MASK_STATUS :: reserved0 [31:21] */
-#define BCHP_AON_PM_L2_PCI_MASK_STATUS_reserved0_MASK 0xffe00000
-#define BCHP_AON_PM_L2_PCI_MASK_STATUS_reserved0_SHIFT 21
-
-/* AON_PM_L2 :: PCI_MASK_STATUS :: SPARE_WAKEUP_EVENT_0 [20:20] */
-#define BCHP_AON_PM_L2_PCI_MASK_STATUS_SPARE_WAKEUP_EVENT_0_MASK 0x00100000
-#define BCHP_AON_PM_L2_PCI_MASK_STATUS_SPARE_WAKEUP_EVENT_0_SHIFT 20
-#define BCHP_AON_PM_L2_PCI_MASK_STATUS_SPARE_WAKEUP_EVENT_0_DEFAULT 0x00000001
-
-/* AON_PM_L2 :: PCI_MASK_STATUS :: FP_RESET [19:19] */
-#define BCHP_AON_PM_L2_PCI_MASK_STATUS_FP_RESET_MASK 0x00080000
-#define BCHP_AON_PM_L2_PCI_MASK_STATUS_FP_RESET_SHIFT 19
-#define BCHP_AON_PM_L2_PCI_MASK_STATUS_FP_RESET_DEFAULT 0x00000001
-
-/* AON_PM_L2 :: PCI_MASK_STATUS :: BOUNDARY_SCAN_REQ [18:18] */
-#define BCHP_AON_PM_L2_PCI_MASK_STATUS_BOUNDARY_SCAN_REQ_MASK 0x00040000
-#define BCHP_AON_PM_L2_PCI_MASK_STATUS_BOUNDARY_SCAN_REQ_SHIFT 18
-#define BCHP_AON_PM_L2_PCI_MASK_STATUS_BOUNDARY_SCAN_REQ_DEFAULT 0x00000001
-
-/* AON_PM_L2 :: PCI_MASK_STATUS :: LEAP [17:17] */
-#define BCHP_AON_PM_L2_PCI_MASK_STATUS_LEAP_MASK 0x00020000
-#define BCHP_AON_PM_L2_PCI_MASK_STATUS_LEAP_SHIFT 17
-#define BCHP_AON_PM_L2_PCI_MASK_STATUS_LEAP_DEFAULT 0x00000001
-
-/* AON_PM_L2 :: PCI_MASK_STATUS :: USB1 [16:16] */
-#define BCHP_AON_PM_L2_PCI_MASK_STATUS_USB1_MASK 0x00010000
-#define BCHP_AON_PM_L2_PCI_MASK_STATUS_USB1_SHIFT 16
-#define BCHP_AON_PM_L2_PCI_MASK_STATUS_USB1_DEFAULT 0x00000001
-
-/* AON_PM_L2 :: PCI_MASK_STATUS :: USB0 [15:15] */
-#define BCHP_AON_PM_L2_PCI_MASK_STATUS_USB0_MASK 0x00008000
-#define BCHP_AON_PM_L2_PCI_MASK_STATUS_USB0_SHIFT 15
-#define BCHP_AON_PM_L2_PCI_MASK_STATUS_USB0_DEFAULT 0x00000001
-
-/* AON_PM_L2 :: PCI_MASK_STATUS :: MOCA [14:14] */
-#define BCHP_AON_PM_L2_PCI_MASK_STATUS_MOCA_MASK 0x00004000
-#define BCHP_AON_PM_L2_PCI_MASK_STATUS_MOCA_SHIFT 14
-#define BCHP_AON_PM_L2_PCI_MASK_STATUS_MOCA_DEFAULT 0x00000001
-
-/* AON_PM_L2 :: PCI_MASK_STATUS :: DEMOD_XPT [13:13] */
-#define BCHP_AON_PM_L2_PCI_MASK_STATUS_DEMOD_XPT_MASK 0x00002000
-#define BCHP_AON_PM_L2_PCI_MASK_STATUS_DEMOD_XPT_SHIFT 13
-#define BCHP_AON_PM_L2_PCI_MASK_STATUS_DEMOD_XPT_DEFAULT 0x00000001
-
-/* AON_PM_L2 :: PCI_MASK_STATUS :: XPT_PMU [12:12] */
-#define BCHP_AON_PM_L2_PCI_MASK_STATUS_XPT_PMU_MASK 0x00001000
-#define BCHP_AON_PM_L2_PCI_MASK_STATUS_XPT_PMU_SHIFT 12
-#define BCHP_AON_PM_L2_PCI_MASK_STATUS_XPT_PMU_DEFAULT 0x00000001
-
-/* AON_PM_L2 :: PCI_MASK_STATUS :: CAP [11:11] */
-#define BCHP_AON_PM_L2_PCI_MASK_STATUS_CAP_MASK 0x00000800
-#define BCHP_AON_PM_L2_PCI_MASK_STATUS_CAP_SHIFT 11
-#define BCHP_AON_PM_L2_PCI_MASK_STATUS_CAP_DEFAULT 0x00000001
-
-/* AON_PM_L2 :: PCI_MASK_STATUS :: WOL_GENET2 [10:10] */
-#define BCHP_AON_PM_L2_PCI_MASK_STATUS_WOL_GENET2_MASK 0x00000400
-#define BCHP_AON_PM_L2_PCI_MASK_STATUS_WOL_GENET2_SHIFT 10
-#define BCHP_AON_PM_L2_PCI_MASK_STATUS_WOL_GENET2_DEFAULT 0x00000001
-
-/* AON_PM_L2 :: PCI_MASK_STATUS :: WOL_GENET1 [09:09] */
-#define BCHP_AON_PM_L2_PCI_MASK_STATUS_WOL_GENET1_MASK 0x00000200
-#define BCHP_AON_PM_L2_PCI_MASK_STATUS_WOL_GENET1_SHIFT 9
-#define BCHP_AON_PM_L2_PCI_MASK_STATUS_WOL_GENET1_DEFAULT 0x00000001
-
-/* AON_PM_L2 :: PCI_MASK_STATUS :: WOL_GENET0 [08:08] */
-#define BCHP_AON_PM_L2_PCI_MASK_STATUS_WOL_GENET0_MASK 0x00000100
-#define BCHP_AON_PM_L2_PCI_MASK_STATUS_WOL_GENET0_SHIFT 8
-#define BCHP_AON_PM_L2_PCI_MASK_STATUS_WOL_GENET0_DEFAULT 0x00000001
-
-/* AON_PM_L2 :: PCI_MASK_STATUS :: AVS_WATCHDOG [07:07] */
-#define BCHP_AON_PM_L2_PCI_MASK_STATUS_AVS_WATCHDOG_MASK 0x00000080
-#define BCHP_AON_PM_L2_PCI_MASK_STATUS_AVS_WATCHDOG_SHIFT 7
-#define BCHP_AON_PM_L2_PCI_MASK_STATUS_AVS_WATCHDOG_DEFAULT 0x00000001
-
-/* AON_PM_L2 :: PCI_MASK_STATUS :: RF4CE [06:06] */
-#define BCHP_AON_PM_L2_PCI_MASK_STATUS_RF4CE_MASK 0x00000040
-#define BCHP_AON_PM_L2_PCI_MASK_STATUS_RF4CE_SHIFT 6
-#define BCHP_AON_PM_L2_PCI_MASK_STATUS_RF4CE_DEFAULT 0x00000001
-
-/* AON_PM_L2 :: PCI_MASK_STATUS :: GPIO [05:05] */
-#define BCHP_AON_PM_L2_PCI_MASK_STATUS_GPIO_MASK 0x00000020
-#define BCHP_AON_PM_L2_PCI_MASK_STATUS_GPIO_SHIFT 5
-#define BCHP_AON_PM_L2_PCI_MASK_STATUS_GPIO_DEFAULT 0x00000001
-
-/* AON_PM_L2 :: PCI_MASK_STATUS :: NMI_B_INTR [04:04] */
-#define BCHP_AON_PM_L2_PCI_MASK_STATUS_NMI_B_INTR_MASK 0x00000010
-#define BCHP_AON_PM_L2_PCI_MASK_STATUS_NMI_B_INTR_SHIFT 4
-#define BCHP_AON_PM_L2_PCI_MASK_STATUS_NMI_B_INTR_DEFAULT 0x00000001
-
-/* AON_PM_L2 :: PCI_MASK_STATUS :: TIMER_INTR [03:03] */
-#define BCHP_AON_PM_L2_PCI_MASK_STATUS_TIMER_INTR_MASK 0x00000008
-#define BCHP_AON_PM_L2_PCI_MASK_STATUS_TIMER_INTR_SHIFT 3
-#define BCHP_AON_PM_L2_PCI_MASK_STATUS_TIMER_INTR_DEFAULT 0x00000001
-
-/* AON_PM_L2 :: PCI_MASK_STATUS :: KPD_INTR [02:02] */
-#define BCHP_AON_PM_L2_PCI_MASK_STATUS_KPD_INTR_MASK 0x00000004
-#define BCHP_AON_PM_L2_PCI_MASK_STATUS_KPD_INTR_SHIFT 2
-#define BCHP_AON_PM_L2_PCI_MASK_STATUS_KPD_INTR_DEFAULT 0x00000001
-
-/* AON_PM_L2 :: PCI_MASK_STATUS :: IRR_INTR [01:01] */
-#define BCHP_AON_PM_L2_PCI_MASK_STATUS_IRR_INTR_MASK 0x00000002
-#define BCHP_AON_PM_L2_PCI_MASK_STATUS_IRR_INTR_SHIFT 1
-#define BCHP_AON_PM_L2_PCI_MASK_STATUS_IRR_INTR_DEFAULT 0x00000001
-
-/* AON_PM_L2 :: PCI_MASK_STATUS :: CEC_INTR [00:00] */
-#define BCHP_AON_PM_L2_PCI_MASK_STATUS_CEC_INTR_MASK 0x00000001
-#define BCHP_AON_PM_L2_PCI_MASK_STATUS_CEC_INTR_SHIFT 0
-#define BCHP_AON_PM_L2_PCI_MASK_STATUS_CEC_INTR_DEFAULT 0x00000001
-
-/***************************************************************************
- *PCI_MASK_SET - PCI interrupt Mask Set Register
- ***************************************************************************/
-/* AON_PM_L2 :: PCI_MASK_SET :: reserved0 [31:21] */
-#define BCHP_AON_PM_L2_PCI_MASK_SET_reserved0_MASK 0xffe00000
-#define BCHP_AON_PM_L2_PCI_MASK_SET_reserved0_SHIFT 21
-
-/* AON_PM_L2 :: PCI_MASK_SET :: SPARE_WAKEUP_EVENT_0 [20:20] */
-#define BCHP_AON_PM_L2_PCI_MASK_SET_SPARE_WAKEUP_EVENT_0_MASK 0x00100000
-#define BCHP_AON_PM_L2_PCI_MASK_SET_SPARE_WAKEUP_EVENT_0_SHIFT 20
-#define BCHP_AON_PM_L2_PCI_MASK_SET_SPARE_WAKEUP_EVENT_0_DEFAULT 0x00000001
-
-/* AON_PM_L2 :: PCI_MASK_SET :: FP_RESET [19:19] */
-#define BCHP_AON_PM_L2_PCI_MASK_SET_FP_RESET_MASK 0x00080000
-#define BCHP_AON_PM_L2_PCI_MASK_SET_FP_RESET_SHIFT 19
-#define BCHP_AON_PM_L2_PCI_MASK_SET_FP_RESET_DEFAULT 0x00000001
-
-/* AON_PM_L2 :: PCI_MASK_SET :: BOUNDARY_SCAN_REQ [18:18] */
-#define BCHP_AON_PM_L2_PCI_MASK_SET_BOUNDARY_SCAN_REQ_MASK 0x00040000
-#define BCHP_AON_PM_L2_PCI_MASK_SET_BOUNDARY_SCAN_REQ_SHIFT 18
-#define BCHP_AON_PM_L2_PCI_MASK_SET_BOUNDARY_SCAN_REQ_DEFAULT 0x00000001
-
-/* AON_PM_L2 :: PCI_MASK_SET :: LEAP [17:17] */
-#define BCHP_AON_PM_L2_PCI_MASK_SET_LEAP_MASK 0x00020000
-#define BCHP_AON_PM_L2_PCI_MASK_SET_LEAP_SHIFT 17
-#define BCHP_AON_PM_L2_PCI_MASK_SET_LEAP_DEFAULT 0x00000001
-
-/* AON_PM_L2 :: PCI_MASK_SET :: USB1 [16:16] */
-#define BCHP_AON_PM_L2_PCI_MASK_SET_USB1_MASK 0x00010000
-#define BCHP_AON_PM_L2_PCI_MASK_SET_USB1_SHIFT 16
-#define BCHP_AON_PM_L2_PCI_MASK_SET_USB1_DEFAULT 0x00000001
-
-/* AON_PM_L2 :: PCI_MASK_SET :: USB0 [15:15] */
-#define BCHP_AON_PM_L2_PCI_MASK_SET_USB0_MASK 0x00008000
-#define BCHP_AON_PM_L2_PCI_MASK_SET_USB0_SHIFT 15
-#define BCHP_AON_PM_L2_PCI_MASK_SET_USB0_DEFAULT 0x00000001
-
-/* AON_PM_L2 :: PCI_MASK_SET :: MOCA [14:14] */
-#define BCHP_AON_PM_L2_PCI_MASK_SET_MOCA_MASK 0x00004000
-#define BCHP_AON_PM_L2_PCI_MASK_SET_MOCA_SHIFT 14
-#define BCHP_AON_PM_L2_PCI_MASK_SET_MOCA_DEFAULT 0x00000001
-
-/* AON_PM_L2 :: PCI_MASK_SET :: DEMOD_XPT [13:13] */
-#define BCHP_AON_PM_L2_PCI_MASK_SET_DEMOD_XPT_MASK 0x00002000
-#define BCHP_AON_PM_L2_PCI_MASK_SET_DEMOD_XPT_SHIFT 13
-#define BCHP_AON_PM_L2_PCI_MASK_SET_DEMOD_XPT_DEFAULT 0x00000001
-
-/* AON_PM_L2 :: PCI_MASK_SET :: XPT_PMU [12:12] */
-#define BCHP_AON_PM_L2_PCI_MASK_SET_XPT_PMU_MASK 0x00001000
-#define BCHP_AON_PM_L2_PCI_MASK_SET_XPT_PMU_SHIFT 12
-#define BCHP_AON_PM_L2_PCI_MASK_SET_XPT_PMU_DEFAULT 0x00000001
-
-/* AON_PM_L2 :: PCI_MASK_SET :: CAP [11:11] */
-#define BCHP_AON_PM_L2_PCI_MASK_SET_CAP_MASK 0x00000800
-#define BCHP_AON_PM_L2_PCI_MASK_SET_CAP_SHIFT 11
-#define BCHP_AON_PM_L2_PCI_MASK_SET_CAP_DEFAULT 0x00000001
-
-/* AON_PM_L2 :: PCI_MASK_SET :: WOL_GENET2 [10:10] */
-#define BCHP_AON_PM_L2_PCI_MASK_SET_WOL_GENET2_MASK 0x00000400
-#define BCHP_AON_PM_L2_PCI_MASK_SET_WOL_GENET2_SHIFT 10
-#define BCHP_AON_PM_L2_PCI_MASK_SET_WOL_GENET2_DEFAULT 0x00000001
-
-/* AON_PM_L2 :: PCI_MASK_SET :: WOL_GENET1 [09:09] */
-#define BCHP_AON_PM_L2_PCI_MASK_SET_WOL_GENET1_MASK 0x00000200
-#define BCHP_AON_PM_L2_PCI_MASK_SET_WOL_GENET1_SHIFT 9
-#define BCHP_AON_PM_L2_PCI_MASK_SET_WOL_GENET1_DEFAULT 0x00000001
-
-/* AON_PM_L2 :: PCI_MASK_SET :: WOL_GENET0 [08:08] */
-#define BCHP_AON_PM_L2_PCI_MASK_SET_WOL_GENET0_MASK 0x00000100
-#define BCHP_AON_PM_L2_PCI_MASK_SET_WOL_GENET0_SHIFT 8
-#define BCHP_AON_PM_L2_PCI_MASK_SET_WOL_GENET0_DEFAULT 0x00000001
-
-/* AON_PM_L2 :: PCI_MASK_SET :: AVS_WATCHDOG [07:07] */
-#define BCHP_AON_PM_L2_PCI_MASK_SET_AVS_WATCHDOG_MASK 0x00000080
-#define BCHP_AON_PM_L2_PCI_MASK_SET_AVS_WATCHDOG_SHIFT 7
-#define BCHP_AON_PM_L2_PCI_MASK_SET_AVS_WATCHDOG_DEFAULT 0x00000001
-
-/* AON_PM_L2 :: PCI_MASK_SET :: RF4CE [06:06] */
-#define BCHP_AON_PM_L2_PCI_MASK_SET_RF4CE_MASK 0x00000040
-#define BCHP_AON_PM_L2_PCI_MASK_SET_RF4CE_SHIFT 6
-#define BCHP_AON_PM_L2_PCI_MASK_SET_RF4CE_DEFAULT 0x00000001
-
-/* AON_PM_L2 :: PCI_MASK_SET :: GPIO [05:05] */
-#define BCHP_AON_PM_L2_PCI_MASK_SET_GPIO_MASK 0x00000020
-#define BCHP_AON_PM_L2_PCI_MASK_SET_GPIO_SHIFT 5
-#define BCHP_AON_PM_L2_PCI_MASK_SET_GPIO_DEFAULT 0x00000001
-
-/* AON_PM_L2 :: PCI_MASK_SET :: NMI_B_INTR [04:04] */
-#define BCHP_AON_PM_L2_PCI_MASK_SET_NMI_B_INTR_MASK 0x00000010
-#define BCHP_AON_PM_L2_PCI_MASK_SET_NMI_B_INTR_SHIFT 4
-#define BCHP_AON_PM_L2_PCI_MASK_SET_NMI_B_INTR_DEFAULT 0x00000001
-
-/* AON_PM_L2 :: PCI_MASK_SET :: TIMER_INTR [03:03] */
-#define BCHP_AON_PM_L2_PCI_MASK_SET_TIMER_INTR_MASK 0x00000008
-#define BCHP_AON_PM_L2_PCI_MASK_SET_TIMER_INTR_SHIFT 3
-#define BCHP_AON_PM_L2_PCI_MASK_SET_TIMER_INTR_DEFAULT 0x00000001
-
-/* AON_PM_L2 :: PCI_MASK_SET :: KPD_INTR [02:02] */
-#define BCHP_AON_PM_L2_PCI_MASK_SET_KPD_INTR_MASK 0x00000004
-#define BCHP_AON_PM_L2_PCI_MASK_SET_KPD_INTR_SHIFT 2
-#define BCHP_AON_PM_L2_PCI_MASK_SET_KPD_INTR_DEFAULT 0x00000001
-
-/* AON_PM_L2 :: PCI_MASK_SET :: IRR_INTR [01:01] */
-#define BCHP_AON_PM_L2_PCI_MASK_SET_IRR_INTR_MASK 0x00000002
-#define BCHP_AON_PM_L2_PCI_MASK_SET_IRR_INTR_SHIFT 1
-#define BCHP_AON_PM_L2_PCI_MASK_SET_IRR_INTR_DEFAULT 0x00000001
-
-/* AON_PM_L2 :: PCI_MASK_SET :: CEC_INTR [00:00] */
-#define BCHP_AON_PM_L2_PCI_MASK_SET_CEC_INTR_MASK 0x00000001
-#define BCHP_AON_PM_L2_PCI_MASK_SET_CEC_INTR_SHIFT 0
-#define BCHP_AON_PM_L2_PCI_MASK_SET_CEC_INTR_DEFAULT 0x00000001
-
-/***************************************************************************
- *PCI_MASK_CLEAR - PCI interrupt Mask Clear Register
- ***************************************************************************/
-/* AON_PM_L2 :: PCI_MASK_CLEAR :: reserved0 [31:21] */
-#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_reserved0_MASK 0xffe00000
-#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_reserved0_SHIFT 21
-
-/* AON_PM_L2 :: PCI_MASK_CLEAR :: SPARE_WAKEUP_EVENT_0 [20:20] */
-#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_SPARE_WAKEUP_EVENT_0_MASK 0x00100000
-#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_SPARE_WAKEUP_EVENT_0_SHIFT 20
-#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_SPARE_WAKEUP_EVENT_0_DEFAULT 0x00000001
-
-/* AON_PM_L2 :: PCI_MASK_CLEAR :: FP_RESET [19:19] */
-#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_FP_RESET_MASK 0x00080000
-#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_FP_RESET_SHIFT 19
-#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_FP_RESET_DEFAULT 0x00000001
-
-/* AON_PM_L2 :: PCI_MASK_CLEAR :: BOUNDARY_SCAN_REQ [18:18] */
-#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_BOUNDARY_SCAN_REQ_MASK 0x00040000
-#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_BOUNDARY_SCAN_REQ_SHIFT 18
-#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_BOUNDARY_SCAN_REQ_DEFAULT 0x00000001
-
-/* AON_PM_L2 :: PCI_MASK_CLEAR :: LEAP [17:17] */
-#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_LEAP_MASK 0x00020000
-#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_LEAP_SHIFT 17
-#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_LEAP_DEFAULT 0x00000001
-
-/* AON_PM_L2 :: PCI_MASK_CLEAR :: USB1 [16:16] */
-#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_USB1_MASK 0x00010000
-#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_USB1_SHIFT 16
-#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_USB1_DEFAULT 0x00000001
-
-/* AON_PM_L2 :: PCI_MASK_CLEAR :: USB0 [15:15] */
-#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_USB0_MASK 0x00008000
-#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_USB0_SHIFT 15
-#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_USB0_DEFAULT 0x00000001
-
-/* AON_PM_L2 :: PCI_MASK_CLEAR :: MOCA [14:14] */
-#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_MOCA_MASK 0x00004000
-#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_MOCA_SHIFT 14
-#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_MOCA_DEFAULT 0x00000001
-
-/* AON_PM_L2 :: PCI_MASK_CLEAR :: DEMOD_XPT [13:13] */
-#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_DEMOD_XPT_MASK 0x00002000
-#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_DEMOD_XPT_SHIFT 13
-#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_DEMOD_XPT_DEFAULT 0x00000001
-
-/* AON_PM_L2 :: PCI_MASK_CLEAR :: XPT_PMU [12:12] */
-#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_XPT_PMU_MASK 0x00001000
-#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_XPT_PMU_SHIFT 12
-#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_XPT_PMU_DEFAULT 0x00000001
-
-/* AON_PM_L2 :: PCI_MASK_CLEAR :: CAP [11:11] */
-#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_CAP_MASK 0x00000800
-#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_CAP_SHIFT 11
-#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_CAP_DEFAULT 0x00000001
-
-/* AON_PM_L2 :: PCI_MASK_CLEAR :: WOL_GENET2 [10:10] */
-#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_WOL_GENET2_MASK 0x00000400
-#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_WOL_GENET2_SHIFT 10
-#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_WOL_GENET2_DEFAULT 0x00000001
-
-/* AON_PM_L2 :: PCI_MASK_CLEAR :: WOL_GENET1 [09:09] */
-#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_WOL_GENET1_MASK 0x00000200
-#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_WOL_GENET1_SHIFT 9
-#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_WOL_GENET1_DEFAULT 0x00000001
-
-/* AON_PM_L2 :: PCI_MASK_CLEAR :: WOL_GENET0 [08:08] */
-#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_WOL_GENET0_MASK 0x00000100
-#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_WOL_GENET0_SHIFT 8
-#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_WOL_GENET0_DEFAULT 0x00000001
-
-/* AON_PM_L2 :: PCI_MASK_CLEAR :: AVS_WATCHDOG [07:07] */
-#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_AVS_WATCHDOG_MASK 0x00000080
-#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_AVS_WATCHDOG_SHIFT 7
-#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_AVS_WATCHDOG_DEFAULT 0x00000001
-
-/* AON_PM_L2 :: PCI_MASK_CLEAR :: RF4CE [06:06] */
-#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_RF4CE_MASK 0x00000040
-#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_RF4CE_SHIFT 6
-#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_RF4CE_DEFAULT 0x00000001
-
-/* AON_PM_L2 :: PCI_MASK_CLEAR :: GPIO [05:05] */
-#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_GPIO_MASK 0x00000020
-#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_GPIO_SHIFT 5
-#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_GPIO_DEFAULT 0x00000001
-
-/* AON_PM_L2 :: PCI_MASK_CLEAR :: NMI_B_INTR [04:04] */
-#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_NMI_B_INTR_MASK 0x00000010
-#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_NMI_B_INTR_SHIFT 4
-#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_NMI_B_INTR_DEFAULT 0x00000001
-
-/* AON_PM_L2 :: PCI_MASK_CLEAR :: TIMER_INTR [03:03] */
-#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_TIMER_INTR_MASK 0x00000008
-#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_TIMER_INTR_SHIFT 3
-#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_TIMER_INTR_DEFAULT 0x00000001
-
-/* AON_PM_L2 :: PCI_MASK_CLEAR :: KPD_INTR [02:02] */
-#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_KPD_INTR_MASK 0x00000004
-#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_KPD_INTR_SHIFT 2
-#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_KPD_INTR_DEFAULT 0x00000001
-
-/* AON_PM_L2 :: PCI_MASK_CLEAR :: IRR_INTR [01:01] */
-#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_IRR_INTR_MASK 0x00000002
-#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_IRR_INTR_SHIFT 1
-#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_IRR_INTR_DEFAULT 0x00000001
-
-/* AON_PM_L2 :: PCI_MASK_CLEAR :: CEC_INTR [00:00] */
-#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_CEC_INTR_MASK 0x00000001
-#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_CEC_INTR_SHIFT 0
-#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_CEC_INTR_DEFAULT 0x00000001
-
-#endif /* #ifndef BCHP_AON_PM_L2_H__ */
-
-/* End of File */
diff --git a/include/linux/brcmstb/7366b0/bchp_bspi.h b/include/linux/brcmstb/7366b0/bchp_bspi.h
deleted file mode 100644
index b6344fb..0000000
--- a/include/linux/brcmstb/7366b0/bchp_bspi.h
+++ /dev/null
@@ -1,443 +0,0 @@
-/***************************************************************************
- * Copyright (c) 1999-2013, Broadcom Corporation
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
- *
- * Module Description:
- * DO NOT EDIT THIS FILE DIRECTLY
- *
- * This module was generated magically with RDB from a source description
- * file. You must edit the source file for changes to be made to this file.
- *
- *
- * Date: Generated on Sat Apr 20 03:07:44 2013
- * MD5 Checksum d41d8cd98f00b204e9800998ecf8427e
- *
- * Compiled with: RDB Utility combo_header.pl
- * RDB Parser 3.0
- * unknown unknown
- * Perl Interpreter 5.008008
- * Operating System linux
- *
- * Revision History:
- *
- * $brcm_Log: $
- *
- ***************************************************************************/
-
-#ifndef BCHP_BSPI_H__
-#define BCHP_BSPI_H__
-
-/***************************************************************************
- *BSPI - Public BSPI Control Registers
- ***************************************************************************/
-#define BCHP_BSPI_REVISION_ID 0x00443200 /* Revision ID */
-#define BCHP_BSPI_SCRATCH 0x00443204 /* Revision ID */
-#define BCHP_BSPI_MAST_N_BOOT_CTRL 0x00443208 /* Master/Boot SPI Control Register */
-#define BCHP_BSPI_BUSY_STATUS 0x0044320c /* BSPI Busy Status Register */
-#define BCHP_BSPI_INTR_STATUS 0x00443210 /* Interrupt Status Register */
-#define BCHP_BSPI_B0_STATUS 0x00443214 /* Prefetch Buffer 0 Status Register */
-#define BCHP_BSPI_B0_CTRL 0x00443218 /* Prefetch Buffer 0 Control Register */
-#define BCHP_BSPI_B1_STATUS 0x0044321c /* Prefetch Buffer 1 Status Register */
-#define BCHP_BSPI_B1_CTRL 0x00443220 /* Prefetch Buffer 1 Control Register */
-#define BCHP_BSPI_STRAP_OVERRIDE_CTRL 0x00443224 /* Dual/Single Receive Mode Control Register */
-#define BCHP_BSPI_FLEX_MODE_ENABLE 0x00443228 /* Flexible Control Mode Enable Register */
-#define BCHP_BSPI_BITS_PER_CYCLE 0x0044322c /* Bits per cycle "b-p-c" Control Register */
-#define BCHP_BSPI_BITS_PER_PHASE 0x00443230 /* Bits per Phase "b-p-p" Control Register */
-#define BCHP_BSPI_CMD_AND_MODE_BYTE 0x00443234 /* Command and Mode Data Register */
-#define BCHP_BSPI_BSPI_FLASH_UPPER_ADDR_BYTE 0x00443238 /* Bspi FLash upper address byte register */
-#define BCHP_BSPI_BSPI_XOR_VALUE 0x0044323c /* BSPI FLASH XOR Value Register */
-#define BCHP_BSPI_BSPI_XOR_ENABLE 0x00443240 /* BSPI FLASH XOR Enable Register */
-#define BCHP_BSPI_BSPI_PIO_MODE_ENABLE 0x00443244 /* BSPI Pin Programmed IO Mode Enable Register */
-#define BCHP_BSPI_BSPI_PIO_IODIR 0x00443248 /* BSPI Pin Programmed IO Mode Direction Register */
-#define BCHP_BSPI_BSPI_PIO_DATA 0x0044324c /* BSPI Pin Programmed IO Mode Data Register */
-
-/***************************************************************************
- *REVISION_ID - Revision ID
- ***************************************************************************/
-/* BSPI :: REVISION_ID :: reserved0 [31:16] */
-#define BCHP_BSPI_REVISION_ID_reserved0_MASK 0xffff0000
-#define BCHP_BSPI_REVISION_ID_reserved0_SHIFT 16
-
-/* BSPI :: REVISION_ID :: MAJOR [15:08] */
-#define BCHP_BSPI_REVISION_ID_MAJOR_MASK 0x0000ff00
-#define BCHP_BSPI_REVISION_ID_MAJOR_SHIFT 8
-#define BCHP_BSPI_REVISION_ID_MAJOR_DEFAULT 0x00000004
-
-/* BSPI :: REVISION_ID :: MINOR [07:00] */
-#define BCHP_BSPI_REVISION_ID_MINOR_MASK 0x000000ff
-#define BCHP_BSPI_REVISION_ID_MINOR_SHIFT 0
-#define BCHP_BSPI_REVISION_ID_MINOR_DEFAULT 0x00000002
-
-/***************************************************************************
- *SCRATCH - Revision ID
- ***************************************************************************/
-/* BSPI :: SCRATCH :: SCRATCH [31:00] */
-#define BCHP_BSPI_SCRATCH_SCRATCH_MASK 0xffffffff
-#define BCHP_BSPI_SCRATCH_SCRATCH_SHIFT 0
-#define BCHP_BSPI_SCRATCH_SCRATCH_DEFAULT 0x00000000
-
-/***************************************************************************
- *MAST_N_BOOT_CTRL - Master/Boot SPI Control Register
- ***************************************************************************/
-/* BSPI :: MAST_N_BOOT_CTRL :: reserved0 [31:01] */
-#define BCHP_BSPI_MAST_N_BOOT_CTRL_reserved0_MASK 0xfffffffe
-#define BCHP_BSPI_MAST_N_BOOT_CTRL_reserved0_SHIFT 1
-
-/* BSPI :: MAST_N_BOOT_CTRL :: mast_n_boot [00:00] */
-#define BCHP_BSPI_MAST_N_BOOT_CTRL_mast_n_boot_MASK 0x00000001
-#define BCHP_BSPI_MAST_N_BOOT_CTRL_mast_n_boot_SHIFT 0
-#define BCHP_BSPI_MAST_N_BOOT_CTRL_mast_n_boot_DEFAULT 0x00000000
-
-/***************************************************************************
- *BUSY_STATUS - BSPI Busy Status Register
- ***************************************************************************/
-/* BSPI :: BUSY_STATUS :: reserved0 [31:01] */
-#define BCHP_BSPI_BUSY_STATUS_reserved0_MASK 0xfffffffe
-#define BCHP_BSPI_BUSY_STATUS_reserved0_SHIFT 1
-
-/* BSPI :: BUSY_STATUS :: busy [00:00] */
-#define BCHP_BSPI_BUSY_STATUS_busy_MASK 0x00000001
-#define BCHP_BSPI_BUSY_STATUS_busy_SHIFT 0
-#define BCHP_BSPI_BUSY_STATUS_busy_DEFAULT 0x00000000
-
-/***************************************************************************
- *INTR_STATUS - Interrupt Status Register
- ***************************************************************************/
-/* BSPI :: INTR_STATUS :: reserved0 [31:02] */
-#define BCHP_BSPI_INTR_STATUS_reserved0_MASK 0xfffffffc
-#define BCHP_BSPI_INTR_STATUS_reserved0_SHIFT 2
-
-/* BSPI :: INTR_STATUS :: intr_1 [01:01] */
-#define BCHP_BSPI_INTR_STATUS_intr_1_MASK 0x00000002
-#define BCHP_BSPI_INTR_STATUS_intr_1_SHIFT 1
-#define BCHP_BSPI_INTR_STATUS_intr_1_DEFAULT 0x00000000
-
-/* BSPI :: INTR_STATUS :: intr_0 [00:00] */
-#define BCHP_BSPI_INTR_STATUS_intr_0_MASK 0x00000001
-#define BCHP_BSPI_INTR_STATUS_intr_0_SHIFT 0
-#define BCHP_BSPI_INTR_STATUS_intr_0_DEFAULT 0x00000000
-
-/***************************************************************************
- *B0_STATUS - Prefetch Buffer 0 Status Register
- ***************************************************************************/
-/* BSPI :: B0_STATUS :: reserved0 [31:31] */
-#define BCHP_BSPI_B0_STATUS_reserved0_MASK 0x80000000
-#define BCHP_BSPI_B0_STATUS_reserved0_SHIFT 31
-
-/* BSPI :: B0_STATUS :: b0_prefetch_active [30:30] */
-#define BCHP_BSPI_B0_STATUS_b0_prefetch_active_MASK 0x40000000
-#define BCHP_BSPI_B0_STATUS_b0_prefetch_active_SHIFT 30
-#define BCHP_BSPI_B0_STATUS_b0_prefetch_active_DEFAULT 0x00000000
-
-/* BSPI :: B0_STATUS :: b0_full [29:29] */
-#define BCHP_BSPI_B0_STATUS_b0_full_MASK 0x20000000
-#define BCHP_BSPI_B0_STATUS_b0_full_SHIFT 29
-#define BCHP_BSPI_B0_STATUS_b0_full_DEFAULT 0x00000000
-
-/* BSPI :: B0_STATUS :: b0_empty [28:28] */
-#define BCHP_BSPI_B0_STATUS_b0_empty_MASK 0x10000000
-#define BCHP_BSPI_B0_STATUS_b0_empty_SHIFT 28
-#define BCHP_BSPI_B0_STATUS_b0_empty_DEFAULT 0x00000001
-
-/* BSPI :: B0_STATUS :: b0_miss [27:27] */
-#define BCHP_BSPI_B0_STATUS_b0_miss_MASK 0x08000000
-#define BCHP_BSPI_B0_STATUS_b0_miss_SHIFT 27
-#define BCHP_BSPI_B0_STATUS_b0_miss_DEFAULT 0x00000000
-
-/* BSPI :: B0_STATUS :: b0_hit [26:26] */
-#define BCHP_BSPI_B0_STATUS_b0_hit_MASK 0x04000000
-#define BCHP_BSPI_B0_STATUS_b0_hit_SHIFT 26
-#define BCHP_BSPI_B0_STATUS_b0_hit_DEFAULT 0x00000000
-
-/* BSPI :: B0_STATUS :: b0_address [25:00] */
-#define BCHP_BSPI_B0_STATUS_b0_address_MASK 0x03ffffff
-#define BCHP_BSPI_B0_STATUS_b0_address_SHIFT 0
-#define BCHP_BSPI_B0_STATUS_b0_address_DEFAULT 0x00000000
-
-/***************************************************************************
- *B0_CTRL - Prefetch Buffer 0 Control Register
- ***************************************************************************/
-/* BSPI :: B0_CTRL :: reserved0 [31:01] */
-#define BCHP_BSPI_B0_CTRL_reserved0_MASK 0xfffffffe
-#define BCHP_BSPI_B0_CTRL_reserved0_SHIFT 1
-
-/* BSPI :: B0_CTRL :: b0_flush [00:00] */
-#define BCHP_BSPI_B0_CTRL_b0_flush_MASK 0x00000001
-#define BCHP_BSPI_B0_CTRL_b0_flush_SHIFT 0
-#define BCHP_BSPI_B0_CTRL_b0_flush_DEFAULT 0x00000000
-
-/***************************************************************************
- *B1_STATUS - Prefetch Buffer 1 Status Register
- ***************************************************************************/
-/* BSPI :: B1_STATUS :: reserved0 [31:31] */
-#define BCHP_BSPI_B1_STATUS_reserved0_MASK 0x80000000
-#define BCHP_BSPI_B1_STATUS_reserved0_SHIFT 31
-
-/* BSPI :: B1_STATUS :: b1_prefetch_active [30:30] */
-#define BCHP_BSPI_B1_STATUS_b1_prefetch_active_MASK 0x40000000
-#define BCHP_BSPI_B1_STATUS_b1_prefetch_active_SHIFT 30
-#define BCHP_BSPI_B1_STATUS_b1_prefetch_active_DEFAULT 0x00000000
-
-/* BSPI :: B1_STATUS :: b1_full [29:29] */
-#define BCHP_BSPI_B1_STATUS_b1_full_MASK 0x20000000
-#define BCHP_BSPI_B1_STATUS_b1_full_SHIFT 29
-#define BCHP_BSPI_B1_STATUS_b1_full_DEFAULT 0x00000000
-
-/* BSPI :: B1_STATUS :: b1_empty [28:28] */
-#define BCHP_BSPI_B1_STATUS_b1_empty_MASK 0x10000000
-#define BCHP_BSPI_B1_STATUS_b1_empty_SHIFT 28
-#define BCHP_BSPI_B1_STATUS_b1_empty_DEFAULT 0x00000001
-
-/* BSPI :: B1_STATUS :: b1_miss [27:27] */
-#define BCHP_BSPI_B1_STATUS_b1_miss_MASK 0x08000000
-#define BCHP_BSPI_B1_STATUS_b1_miss_SHIFT 27
-#define BCHP_BSPI_B1_STATUS_b1_miss_DEFAULT 0x00000000
-
-/* BSPI :: B1_STATUS :: b1_hit [26:26] */
-#define BCHP_BSPI_B1_STATUS_b1_hit_MASK 0x04000000
-#define BCHP_BSPI_B1_STATUS_b1_hit_SHIFT 26
-#define BCHP_BSPI_B1_STATUS_b1_hit_DEFAULT 0x00000000
-
-/* BSPI :: B1_STATUS :: b1_address [25:00] */
-#define BCHP_BSPI_B1_STATUS_b1_address_MASK 0x03ffffff
-#define BCHP_BSPI_B1_STATUS_b1_address_SHIFT 0
-#define BCHP_BSPI_B1_STATUS_b1_address_DEFAULT 0x00000000
-
-/***************************************************************************
- *B1_CTRL - Prefetch Buffer 1 Control Register
- ***************************************************************************/
-/* BSPI :: B1_CTRL :: reserved0 [31:01] */
-#define BCHP_BSPI_B1_CTRL_reserved0_MASK 0xfffffffe
-#define BCHP_BSPI_B1_CTRL_reserved0_SHIFT 1
-
-/* BSPI :: B1_CTRL :: b1_flush [00:00] */
-#define BCHP_BSPI_B1_CTRL_b1_flush_MASK 0x00000001
-#define BCHP_BSPI_B1_CTRL_b1_flush_SHIFT 0
-#define BCHP_BSPI_B1_CTRL_b1_flush_DEFAULT 0x00000000
-
-/***************************************************************************
- *STRAP_OVERRIDE_CTRL - Dual/Single Receive Mode Control Register
- ***************************************************************************/
-/* BSPI :: STRAP_OVERRIDE_CTRL :: reserved0 [31:05] */
-#define BCHP_BSPI_STRAP_OVERRIDE_CTRL_reserved0_MASK 0xffffffe0
-#define BCHP_BSPI_STRAP_OVERRIDE_CTRL_reserved0_SHIFT 5
-
-/* BSPI :: STRAP_OVERRIDE_CTRL :: endian_mode [04:04] */
-#define BCHP_BSPI_STRAP_OVERRIDE_CTRL_endian_mode_MASK 0x00000010
-#define BCHP_BSPI_STRAP_OVERRIDE_CTRL_endian_mode_SHIFT 4
-#define BCHP_BSPI_STRAP_OVERRIDE_CTRL_endian_mode_DEFAULT 0x00000000
-
-/* BSPI :: STRAP_OVERRIDE_CTRL :: data_quad [03:03] */
-#define BCHP_BSPI_STRAP_OVERRIDE_CTRL_data_quad_MASK 0x00000008
-#define BCHP_BSPI_STRAP_OVERRIDE_CTRL_data_quad_SHIFT 3
-#define BCHP_BSPI_STRAP_OVERRIDE_CTRL_data_quad_DEFAULT 0x00000000
-
-/* BSPI :: STRAP_OVERRIDE_CTRL :: addr_4byte_n_3byte [02:02] */
-#define BCHP_BSPI_STRAP_OVERRIDE_CTRL_addr_4byte_n_3byte_MASK 0x00000004
-#define BCHP_BSPI_STRAP_OVERRIDE_CTRL_addr_4byte_n_3byte_SHIFT 2
-#define BCHP_BSPI_STRAP_OVERRIDE_CTRL_addr_4byte_n_3byte_DEFAULT 0x00000000
-
-/* BSPI :: STRAP_OVERRIDE_CTRL :: data_dual_n_sgl [01:01] */
-#define BCHP_BSPI_STRAP_OVERRIDE_CTRL_data_dual_n_sgl_MASK 0x00000002
-#define BCHP_BSPI_STRAP_OVERRIDE_CTRL_data_dual_n_sgl_SHIFT 1
-#define BCHP_BSPI_STRAP_OVERRIDE_CTRL_data_dual_n_sgl_DEFAULT 0x00000000
-
-/* BSPI :: STRAP_OVERRIDE_CTRL :: override [00:00] */
-#define BCHP_BSPI_STRAP_OVERRIDE_CTRL_override_MASK 0x00000001
-#define BCHP_BSPI_STRAP_OVERRIDE_CTRL_override_SHIFT 0
-#define BCHP_BSPI_STRAP_OVERRIDE_CTRL_override_DEFAULT 0x00000000
-
-/***************************************************************************
- *FLEX_MODE_ENABLE - Flexible Control Mode Enable Register
- ***************************************************************************/
-/* BSPI :: FLEX_MODE_ENABLE :: reserved0 [31:01] */
-#define BCHP_BSPI_FLEX_MODE_ENABLE_reserved0_MASK 0xfffffffe
-#define BCHP_BSPI_FLEX_MODE_ENABLE_reserved0_SHIFT 1
-
-/* BSPI :: FLEX_MODE_ENABLE :: bspi_flex_mode_enable [00:00] */
-#define BCHP_BSPI_FLEX_MODE_ENABLE_bspi_flex_mode_enable_MASK 0x00000001
-#define BCHP_BSPI_FLEX_MODE_ENABLE_bspi_flex_mode_enable_SHIFT 0
-#define BCHP_BSPI_FLEX_MODE_ENABLE_bspi_flex_mode_enable_DEFAULT 0x00000000
-
-/***************************************************************************
- *BITS_PER_CYCLE - Bits per cycle "b-p-c" Control Register
- ***************************************************************************/
-/* BSPI :: BITS_PER_CYCLE :: reserved0 [31:26] */
-#define BCHP_BSPI_BITS_PER_CYCLE_reserved0_MASK 0xfc000000
-#define BCHP_BSPI_BITS_PER_CYCLE_reserved0_SHIFT 26
-
-/* BSPI :: BITS_PER_CYCLE :: cmd_bpc_select [25:24] */
-#define BCHP_BSPI_BITS_PER_CYCLE_cmd_bpc_select_MASK 0x03000000
-#define BCHP_BSPI_BITS_PER_CYCLE_cmd_bpc_select_SHIFT 24
-#define BCHP_BSPI_BITS_PER_CYCLE_cmd_bpc_select_DEFAULT 0x00000000
-
-/* BSPI :: BITS_PER_CYCLE :: reserved1 [23:18] */
-#define BCHP_BSPI_BITS_PER_CYCLE_reserved1_MASK 0x00fc0000
-#define BCHP_BSPI_BITS_PER_CYCLE_reserved1_SHIFT 18
-
-/* BSPI :: BITS_PER_CYCLE :: addr_bpc_select [17:16] */
-#define BCHP_BSPI_BITS_PER_CYCLE_addr_bpc_select_MASK 0x00030000
-#define BCHP_BSPI_BITS_PER_CYCLE_addr_bpc_select_SHIFT 16
-#define BCHP_BSPI_BITS_PER_CYCLE_addr_bpc_select_DEFAULT 0x00000000
-
-/* BSPI :: BITS_PER_CYCLE :: reserved2 [15:10] */
-#define BCHP_BSPI_BITS_PER_CYCLE_reserved2_MASK 0x0000fc00
-#define BCHP_BSPI_BITS_PER_CYCLE_reserved2_SHIFT 10
-
-/* BSPI :: BITS_PER_CYCLE :: mode_bpc_select [09:08] */
-#define BCHP_BSPI_BITS_PER_CYCLE_mode_bpc_select_MASK 0x00000300
-#define BCHP_BSPI_BITS_PER_CYCLE_mode_bpc_select_SHIFT 8
-#define BCHP_BSPI_BITS_PER_CYCLE_mode_bpc_select_DEFAULT 0x00000000
-
-/* BSPI :: BITS_PER_CYCLE :: reserved3 [07:02] */
-#define BCHP_BSPI_BITS_PER_CYCLE_reserved3_MASK 0x000000fc
-#define BCHP_BSPI_BITS_PER_CYCLE_reserved3_SHIFT 2
-
-/* BSPI :: BITS_PER_CYCLE :: data_bpc_select [01:00] */
-#define BCHP_BSPI_BITS_PER_CYCLE_data_bpc_select_MASK 0x00000003
-#define BCHP_BSPI_BITS_PER_CYCLE_data_bpc_select_SHIFT 0
-#define BCHP_BSPI_BITS_PER_CYCLE_data_bpc_select_DEFAULT 0x00000000
-
-/***************************************************************************
- *BITS_PER_PHASE - Bits per Phase "b-p-p" Control Register
- ***************************************************************************/
-/* BSPI :: BITS_PER_PHASE :: reserved0 [31:25] */
-#define BCHP_BSPI_BITS_PER_PHASE_reserved0_MASK 0xfe000000
-#define BCHP_BSPI_BITS_PER_PHASE_reserved0_SHIFT 25
-
-/* BSPI :: BITS_PER_PHASE :: cmd_bpp_select [24:24] */
-#define BCHP_BSPI_BITS_PER_PHASE_cmd_bpp_select_MASK 0x01000000
-#define BCHP_BSPI_BITS_PER_PHASE_cmd_bpp_select_SHIFT 24
-#define BCHP_BSPI_BITS_PER_PHASE_cmd_bpp_select_DEFAULT 0x00000000
-
-/* BSPI :: BITS_PER_PHASE :: reserved1 [23:17] */
-#define BCHP_BSPI_BITS_PER_PHASE_reserved1_MASK 0x00fe0000
-#define BCHP_BSPI_BITS_PER_PHASE_reserved1_SHIFT 17
-
-/* BSPI :: BITS_PER_PHASE :: addr_bpp_select [16:16] */
-#define BCHP_BSPI_BITS_PER_PHASE_addr_bpp_select_MASK 0x00010000
-#define BCHP_BSPI_BITS_PER_PHASE_addr_bpp_select_SHIFT 16
-#define BCHP_BSPI_BITS_PER_PHASE_addr_bpp_select_DEFAULT 0x00000000
-
-/* BSPI :: BITS_PER_PHASE :: reserved2 [15:09] */
-#define BCHP_BSPI_BITS_PER_PHASE_reserved2_MASK 0x0000fe00
-#define BCHP_BSPI_BITS_PER_PHASE_reserved2_SHIFT 9
-
-/* BSPI :: BITS_PER_PHASE :: mode_bpp [08:08] */
-#define BCHP_BSPI_BITS_PER_PHASE_mode_bpp_MASK 0x00000100
-#define BCHP_BSPI_BITS_PER_PHASE_mode_bpp_SHIFT 8
-#define BCHP_BSPI_BITS_PER_PHASE_mode_bpp_DEFAULT 0x00000000
-
-/* BSPI :: BITS_PER_PHASE :: dummy_cycles [07:00] */
-#define BCHP_BSPI_BITS_PER_PHASE_dummy_cycles_MASK 0x000000ff
-#define BCHP_BSPI_BITS_PER_PHASE_dummy_cycles_SHIFT 0
-#define BCHP_BSPI_BITS_PER_PHASE_dummy_cycles_DEFAULT 0x00000008
-
-/***************************************************************************
- *CMD_AND_MODE_BYTE - Command and Mode Data Register
- ***************************************************************************/
-/* BSPI :: CMD_AND_MODE_BYTE :: reserved0 [31:24] */
-#define BCHP_BSPI_CMD_AND_MODE_BYTE_reserved0_MASK 0xff000000
-#define BCHP_BSPI_CMD_AND_MODE_BYTE_reserved0_SHIFT 24
-
-/* BSPI :: CMD_AND_MODE_BYTE :: bspi_mode_byte [23:16] */
-#define BCHP_BSPI_CMD_AND_MODE_BYTE_bspi_mode_byte_MASK 0x00ff0000
-#define BCHP_BSPI_CMD_AND_MODE_BYTE_bspi_mode_byte_SHIFT 16
-#define BCHP_BSPI_CMD_AND_MODE_BYTE_bspi_mode_byte_DEFAULT 0x00000000
-
-/* BSPI :: CMD_AND_MODE_BYTE :: reserved1 [15:08] */
-#define BCHP_BSPI_CMD_AND_MODE_BYTE_reserved1_MASK 0x0000ff00
-#define BCHP_BSPI_CMD_AND_MODE_BYTE_reserved1_SHIFT 8
-
-/* BSPI :: CMD_AND_MODE_BYTE :: bspi_cmd_byte [07:00] */
-#define BCHP_BSPI_CMD_AND_MODE_BYTE_bspi_cmd_byte_MASK 0x000000ff
-#define BCHP_BSPI_CMD_AND_MODE_BYTE_bspi_cmd_byte_SHIFT 0
-#define BCHP_BSPI_CMD_AND_MODE_BYTE_bspi_cmd_byte_DEFAULT 0x0000000b
-
-/***************************************************************************
- *BSPI_FLASH_UPPER_ADDR_BYTE - Bspi FLash upper address byte register
- ***************************************************************************/
-/* BSPI :: BSPI_FLASH_UPPER_ADDR_BYTE :: bspi_flash_upper_addr [31:24] */
-#define BCHP_BSPI_BSPI_FLASH_UPPER_ADDR_BYTE_bspi_flash_upper_addr_MASK 0xff000000
-#define BCHP_BSPI_BSPI_FLASH_UPPER_ADDR_BYTE_bspi_flash_upper_addr_SHIFT 24
-#define BCHP_BSPI_BSPI_FLASH_UPPER_ADDR_BYTE_bspi_flash_upper_addr_DEFAULT 0x00000000
-
-/* BSPI :: BSPI_FLASH_UPPER_ADDR_BYTE :: reserved0 [23:00] */
-#define BCHP_BSPI_BSPI_FLASH_UPPER_ADDR_BYTE_reserved0_MASK 0x00ffffff
-#define BCHP_BSPI_BSPI_FLASH_UPPER_ADDR_BYTE_reserved0_SHIFT 0
-
-/***************************************************************************
- *BSPI_XOR_VALUE - BSPI FLASH XOR Value Register
- ***************************************************************************/
-/* BSPI :: BSPI_XOR_VALUE :: bspi_xor_value [31:20] */
-#define BCHP_BSPI_BSPI_XOR_VALUE_bspi_xor_value_MASK 0xfff00000
-#define BCHP_BSPI_BSPI_XOR_VALUE_bspi_xor_value_SHIFT 20
-#define BCHP_BSPI_BSPI_XOR_VALUE_bspi_xor_value_DEFAULT 0x00000e00
-
-/* BSPI :: BSPI_XOR_VALUE :: reserved0 [19:00] */
-#define BCHP_BSPI_BSPI_XOR_VALUE_reserved0_MASK 0x000fffff
-#define BCHP_BSPI_BSPI_XOR_VALUE_reserved0_SHIFT 0
-
-/***************************************************************************
- *BSPI_XOR_ENABLE - BSPI FLASH XOR Enable Register
- ***************************************************************************/
-/* BSPI :: BSPI_XOR_ENABLE :: reserved0 [31:01] */
-#define BCHP_BSPI_BSPI_XOR_ENABLE_reserved0_MASK 0xfffffffe
-#define BCHP_BSPI_BSPI_XOR_ENABLE_reserved0_SHIFT 1
-
-/* BSPI :: BSPI_XOR_ENABLE :: bspi_xor_enable [00:00] */
-#define BCHP_BSPI_BSPI_XOR_ENABLE_bspi_xor_enable_MASK 0x00000001
-#define BCHP_BSPI_BSPI_XOR_ENABLE_bspi_xor_enable_SHIFT 0
-#define BCHP_BSPI_BSPI_XOR_ENABLE_bspi_xor_enable_DEFAULT 0x00000001
-
-/***************************************************************************
- *BSPI_PIO_MODE_ENABLE - BSPI Pin Programmed IO Mode Enable Register
- ***************************************************************************/
-/* BSPI :: BSPI_PIO_MODE_ENABLE :: reserved0 [31:01] */
-#define BCHP_BSPI_BSPI_PIO_MODE_ENABLE_reserved0_MASK 0xfffffffe
-#define BCHP_BSPI_BSPI_PIO_MODE_ENABLE_reserved0_SHIFT 1
-
-/* BSPI :: BSPI_PIO_MODE_ENABLE :: bspi_pio_mode [00:00] */
-#define BCHP_BSPI_BSPI_PIO_MODE_ENABLE_bspi_pio_mode_MASK 0x00000001
-#define BCHP_BSPI_BSPI_PIO_MODE_ENABLE_bspi_pio_mode_SHIFT 0
-#define BCHP_BSPI_BSPI_PIO_MODE_ENABLE_bspi_pio_mode_DEFAULT 0x00000000
-
-/***************************************************************************
- *BSPI_PIO_IODIR - BSPI Pin Programmed IO Mode Direction Register
- ***************************************************************************/
-/* BSPI :: BSPI_PIO_IODIR :: reserved0 [31:03] */
-#define BCHP_BSPI_BSPI_PIO_IODIR_reserved0_MASK 0xfffffff8
-#define BCHP_BSPI_BSPI_PIO_IODIR_reserved0_SHIFT 3
-
-/* BSPI :: BSPI_PIO_IODIR :: bspi_pio_dir [02:00] */
-#define BCHP_BSPI_BSPI_PIO_IODIR_bspi_pio_dir_MASK 0x00000007
-#define BCHP_BSPI_BSPI_PIO_IODIR_bspi_pio_dir_SHIFT 0
-#define BCHP_BSPI_BSPI_PIO_IODIR_bspi_pio_dir_DEFAULT 0x00000003
-
-/***************************************************************************
- *BSPI_PIO_DATA - BSPI Pin Programmed IO Mode Data Register
- ***************************************************************************/
-/* BSPI :: BSPI_PIO_DATA :: reserved0 [31:03] */
-#define BCHP_BSPI_BSPI_PIO_DATA_reserved0_MASK 0xfffffff8
-#define BCHP_BSPI_BSPI_PIO_DATA_reserved0_SHIFT 3
-
-/* BSPI :: BSPI_PIO_DATA :: bspi_pio_data [02:00] */
-#define BCHP_BSPI_BSPI_PIO_DATA_bspi_pio_data_MASK 0x00000007
-#define BCHP_BSPI_BSPI_PIO_DATA_bspi_pio_data_SHIFT 0
-#define BCHP_BSPI_BSPI_PIO_DATA_bspi_pio_data_DEFAULT 0x00000000
-
-#endif /* #ifndef BCHP_BSPI_H__ */
-
-/* End of File */
diff --git a/include/linux/brcmstb/7366b0/bchp_bspi_raf.h b/include/linux/brcmstb/7366b0/bchp_bspi_raf.h
deleted file mode 100644
index 21fadaa..0000000
--- a/include/linux/brcmstb/7366b0/bchp_bspi_raf.h
+++ /dev/null
@@ -1,160 +0,0 @@
-/***************************************************************************
- * Copyright (c) 1999-2012, Broadcom Corporation
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
- *
- * Module Description:
- * DO NOT EDIT THIS FILE DIRECTLY
- *
- * This module was generated magically with RDB from a source description
- * file. You must edit the source file for changes to be made to this file.
- *
- *
- * Date: Generated on Wed Oct 17 03:11:33 2012
- * MD5 Checksum d41d8cd98f00b204e9800998ecf8427e
- *
- * Compiled with: RDB Utility combo_header.pl
- * RDB Parser 3.0
- * unknown unknown
- * Perl Interpreter 5.008008
- * Operating System linux
- *
- * Revision History:
- *
- * $brcm_Log: $
- *
- ***************************************************************************/
-
-#ifndef BCHP_BSPI_RAF_H__
-#define BCHP_BSPI_RAF_H__
-
-/***************************************************************************
- *BSPI_RAF - Public Linear Read BSPI Pipe Registers
- ***************************************************************************/
-#define BCHP_BSPI_RAF_START_ADDR 0x00443300 /* Physical Starting Address Location in Flash device */
-#define BCHP_BSPI_RAF_NUM_WORDS 0x00443304 /* Number of Words to be fetched */
-#define BCHP_BSPI_RAF_CTRL 0x00443308 /* RAF Session Control Register */
-#define BCHP_BSPI_RAF_FULLNESS 0x0044330c /* Fullness indicator for the read ahead buffer */
-#define BCHP_BSPI_RAF_WATERMARK 0x00443310 /* Watermark level in the read ahead buffer that triggers an interrupt */
-#define BCHP_BSPI_RAF_STATUS 0x00443314 /* Linear Read Status Register */
-#define BCHP_BSPI_RAF_READ_DATA 0x00443318 /* Read data from Raf-buffer */
-#define BCHP_BSPI_RAF_WORD_CNT 0x0044331c /* Current number of words fetched from Flash */
-#define BCHP_BSPI_RAF_CURR_ADDR 0x00443320 /* Current read address for the linear read session */
-
-/***************************************************************************
- *START_ADDR - Physical Starting Address Location in Flash device
- ***************************************************************************/
-/* BSPI_RAF :: START_ADDR :: START_ADDR [31:00] */
-#define BCHP_BSPI_RAF_START_ADDR_START_ADDR_MASK 0xffffffff
-#define BCHP_BSPI_RAF_START_ADDR_START_ADDR_SHIFT 0
-#define BCHP_BSPI_RAF_START_ADDR_START_ADDR_DEFAULT 0x00000000
-
-/***************************************************************************
- *NUM_WORDS - Number of Words to be fetched
- ***************************************************************************/
-/* BSPI_RAF :: NUM_WORDS :: NumWords [31:00] */
-#define BCHP_BSPI_RAF_NUM_WORDS_NumWords_MASK 0xffffffff
-#define BCHP_BSPI_RAF_NUM_WORDS_NumWords_SHIFT 0
-#define BCHP_BSPI_RAF_NUM_WORDS_NumWords_DEFAULT 0x00000000
-
-/***************************************************************************
- *CTRL - RAF Session Control Register
- ***************************************************************************/
-/* BSPI_RAF :: CTRL :: reserved0 [31:02] */
-#define BCHP_BSPI_RAF_CTRL_reserved0_MASK 0xfffffffc
-#define BCHP_BSPI_RAF_CTRL_reserved0_SHIFT 2
-
-/* BSPI_RAF :: CTRL :: CLEAR [01:01] */
-#define BCHP_BSPI_RAF_CTRL_CLEAR_MASK 0x00000002
-#define BCHP_BSPI_RAF_CTRL_CLEAR_SHIFT 1
-#define BCHP_BSPI_RAF_CTRL_CLEAR_DEFAULT 0x00000000
-
-/* BSPI_RAF :: CTRL :: START [00:00] */
-#define BCHP_BSPI_RAF_CTRL_START_MASK 0x00000001
-#define BCHP_BSPI_RAF_CTRL_START_SHIFT 0
-#define BCHP_BSPI_RAF_CTRL_START_DEFAULT 0x00000000
-
-/***************************************************************************
- *FULLNESS - Fullness indicator for the read ahead buffer
- ***************************************************************************/
-/* BSPI_RAF :: FULLNESS :: reserved0 [31:07] */
-#define BCHP_BSPI_RAF_FULLNESS_reserved0_MASK 0xffffff80
-#define BCHP_BSPI_RAF_FULLNESS_reserved0_SHIFT 7
-
-/* BSPI_RAF :: FULLNESS :: FULLNESS [06:00] */
-#define BCHP_BSPI_RAF_FULLNESS_FULLNESS_MASK 0x0000007f
-#define BCHP_BSPI_RAF_FULLNESS_FULLNESS_SHIFT 0
-#define BCHP_BSPI_RAF_FULLNESS_FULLNESS_DEFAULT 0x00000000
-
-/***************************************************************************
- *WATERMARK - Watermark level in the read ahead buffer that triggers an interrupt
- ***************************************************************************/
-/* BSPI_RAF :: WATERMARK :: reserved0 [31:02] */
-#define BCHP_BSPI_RAF_WATERMARK_reserved0_MASK 0xfffffffc
-#define BCHP_BSPI_RAF_WATERMARK_reserved0_SHIFT 2
-
-/* BSPI_RAF :: WATERMARK :: FULLNESS_WATERMARK [01:00] */
-#define BCHP_BSPI_RAF_WATERMARK_FULLNESS_WATERMARK_MASK 0x00000003
-#define BCHP_BSPI_RAF_WATERMARK_FULLNESS_WATERMARK_SHIFT 0
-#define BCHP_BSPI_RAF_WATERMARK_FULLNESS_WATERMARK_DEFAULT 0x00000000
-
-/***************************************************************************
- *STATUS - Linear Read Status Register
- ***************************************************************************/
-/* BSPI_RAF :: STATUS :: reserved0 [31:03] */
-#define BCHP_BSPI_RAF_STATUS_reserved0_MASK 0xfffffff8
-#define BCHP_BSPI_RAF_STATUS_reserved0_SHIFT 3
-
-/* BSPI_RAF :: STATUS :: FIFO_FULL [02:02] */
-#define BCHP_BSPI_RAF_STATUS_FIFO_FULL_MASK 0x00000004
-#define BCHP_BSPI_RAF_STATUS_FIFO_FULL_SHIFT 2
-#define BCHP_BSPI_RAF_STATUS_FIFO_FULL_DEFAULT 0x00000000
-
-/* BSPI_RAF :: STATUS :: FIFO_EMPTY [01:01] */
-#define BCHP_BSPI_RAF_STATUS_FIFO_EMPTY_MASK 0x00000002
-#define BCHP_BSPI_RAF_STATUS_FIFO_EMPTY_SHIFT 1
-#define BCHP_BSPI_RAF_STATUS_FIFO_EMPTY_DEFAULT 0x00000001
-
-/* BSPI_RAF :: STATUS :: SESSION_BUSY [00:00] */
-#define BCHP_BSPI_RAF_STATUS_SESSION_BUSY_MASK 0x00000001
-#define BCHP_BSPI_RAF_STATUS_SESSION_BUSY_SHIFT 0
-#define BCHP_BSPI_RAF_STATUS_SESSION_BUSY_DEFAULT 0x00000000
-
-/***************************************************************************
- *READ_DATA - Read data from Raf-buffer
- ***************************************************************************/
-/* BSPI_RAF :: READ_DATA :: DATA [31:00] */
-#define BCHP_BSPI_RAF_READ_DATA_DATA_MASK 0xffffffff
-#define BCHP_BSPI_RAF_READ_DATA_DATA_SHIFT 0
-#define BCHP_BSPI_RAF_READ_DATA_DATA_DEFAULT 0x00000000
-
-/***************************************************************************
- *WORD_CNT - Current number of words fetched from Flash
- ***************************************************************************/
-/* BSPI_RAF :: WORD_CNT :: CURRENT_WORD_COUNT [31:00] */
-#define BCHP_BSPI_RAF_WORD_CNT_CURRENT_WORD_COUNT_MASK 0xffffffff
-#define BCHP_BSPI_RAF_WORD_CNT_CURRENT_WORD_COUNT_SHIFT 0
-#define BCHP_BSPI_RAF_WORD_CNT_CURRENT_WORD_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *CURR_ADDR - Current read address for the linear read session
- ***************************************************************************/
-/* BSPI_RAF :: CURR_ADDR :: CURRENT_ADDRESS [31:00] */
-#define BCHP_BSPI_RAF_CURR_ADDR_CURRENT_ADDRESS_MASK 0xffffffff
-#define BCHP_BSPI_RAF_CURR_ADDR_CURRENT_ADDRESS_SHIFT 0
-#define BCHP_BSPI_RAF_CURR_ADDR_CURRENT_ADDRESS_DEFAULT 0x00000000
-
-#endif /* #ifndef BCHP_BSPI_RAF_H__ */
-
-/* End of File */
diff --git a/include/linux/brcmstb/7366b0/bchp_clkgen.h b/include/linux/brcmstb/7366b0/bchp_clkgen.h
deleted file mode 100644
index 2e43e80..0000000
--- a/include/linux/brcmstb/7366b0/bchp_clkgen.h
+++ /dev/null
@@ -1,11392 +0,0 @@
-/***************************************************************************
- * Copyright (c) 1999-2014, Broadcom Corporation
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
- *
- * Module Description:
- * DO NOT EDIT THIS FILE DIRECTLY
- *
- * This module was generated magically with RDB from a source description
- * file. You must edit the source file for changes to be made to this file.
- *
- *
- * Date: Generated on Thu Apr 24 03:08:54 2014
- * Full Compile MD5 Checksum 1af2c2cf28828ece5496e1312aac0166
- * (minus title and desc)
- * MD5 Checksum 3203ffce85e3fc9a10f84123e54057b0
- *
- * Compiled with: RDB Utility combo_header.pl
- * RDB Parser 3.0
- * unknown unknown
- * Perl Interpreter 5.008008
- * Operating System linux
- *
- * Revision History:
- *
- * $brcm_Log: $
- *
- ***************************************************************************/
-
-#ifndef BCHP_CLKGEN_H__
-#define BCHP_CLKGEN_H__
-
-/***************************************************************************
- *CLKGEN - clkgen registers
- ***************************************************************************/
-#define BCHP_CLKGEN_PLL_CPU_PLL_CHANNEL_CTRL_CH_0 0x004e0000 /* PLL CHANNEL control CH 0 */
-#define BCHP_CLKGEN_PLL_CPU_PLL_CHANNEL_CTRL_CH_1 0x004e0004 /* PLL CHANNEL control CH 1 */
-#define BCHP_CLKGEN_PLL_CPU_PLL_DIV 0x004e0008 /* Pre multiplier */
-#define BCHP_CLKGEN_PLL_CPU_PLL_FRAC 0x004e000c /* Fractional */
-#define BCHP_CLKGEN_PLL_CPU_PLL_GAIN 0x004e0010 /* PLL GAIN */
-#define BCHP_CLKGEN_PLL_CPU_PLL_LDO_PWRON 0x004e0014 /* LDO Power on */
-#define BCHP_CLKGEN_PLL_CPU_PLL_LOCK_STATUS 0x004e0018 /* Lock Status */
-#define BCHP_CLKGEN_PLL_CPU_PLL_MISC 0x004e001c /* Mscellaneous control bus. */
-#define BCHP_CLKGEN_PLL_CPU_PLL_MISC2 0x004e0020 /* Mscellaneous control bus continued. */
-#define BCHP_CLKGEN_PLL_CPU_PLL_PWRON 0x004e0024 /* Poweron */
-#define BCHP_CLKGEN_PLL_CPU_PLL_RESET 0x004e0028 /* Resets */
-#define BCHP_CLKGEN_PLL_CPU_PLL_SSC_MODE_CONTROL_HIGH 0x004e002c /* Higher bits of Spread Spectrum mode control */
-#define BCHP_CLKGEN_PLL_CPU_PLL_SSC_MODE_CONTROL_LOW 0x004e0030 /* Lower bits of Spread Spectrum mode control */
-#define BCHP_CLKGEN_PLL_CPU_PLL_STATUS 0x004e0034 /* Status */
-#define BCHP_CLKGEN_PLL_HVD_PLL_CHANNEL_CTRL_CH_0 0x004e0038 /* PLL CHANNEL control CH 0 */
-#define BCHP_CLKGEN_PLL_HVD_PLL_CHANNEL_CTRL_CH_1 0x004e003c /* PLL CHANNEL control CH 1 */
-#define BCHP_CLKGEN_PLL_HVD_PLL_CHANNEL_CTRL_CH_3 0x004e0040 /* PLL CHANNEL control CH 3 */
-#define BCHP_CLKGEN_PLL_HVD_PLL_CHANNEL_CTRL_CH_4 0x004e0044 /* PLL CHANNEL control CH 4 */
-#define BCHP_CLKGEN_PLL_HVD_PLL_DIV 0x004e0048 /* Pre multiplier */
-#define BCHP_CLKGEN_PLL_HVD_PLL_FRAC 0x004e004c /* Fractional */
-#define BCHP_CLKGEN_PLL_HVD_PLL_GAIN 0x004e0050 /* PLL GAIN */
-#define BCHP_CLKGEN_PLL_HVD_PLL_LDO_PWRON 0x004e0054 /* LDO Power on */
-#define BCHP_CLKGEN_PLL_HVD_PLL_LOCK_STATUS 0x004e0058 /* Lock Status */
-#define BCHP_CLKGEN_PLL_HVD_PLL_MISC 0x004e005c /* Mscellaneous control bus. */
-#define BCHP_CLKGEN_PLL_HVD_PLL_MISC2 0x004e0060 /* Mscellaneous control bus continued. */
-#define BCHP_CLKGEN_PLL_HVD_PLL_PWRON 0x004e0064 /* Poweron */
-#define BCHP_CLKGEN_PLL_HVD_PLL_RESET 0x004e0068 /* Resets */
-#define BCHP_CLKGEN_PLL_HVD_PLL_SSC_MODE_CONTROL_HIGH 0x004e006c /* Higher bits of Spread Spectrum mode control */
-#define BCHP_CLKGEN_PLL_HVD_PLL_SSC_MODE_CONTROL_LOW 0x004e0070 /* Lower bits of Spread Spectrum mode control */
-#define BCHP_CLKGEN_PLL_HVD_PLL_STATUS 0x004e0074 /* Status */
-#define BCHP_CLKGEN_PLL_LC_PLL_CHANNEL_CTRL_CH_0 0x004e0078 /* PLL CHANNEL control CH 0 */
-#define BCHP_CLKGEN_PLL_LC_PLL_CHANNEL_CTRL_CH_1 0x004e007c /* PLL CHANNEL control CH 1 */
-#define BCHP_CLKGEN_PLL_LC_PLL_CHANNEL_CTRL_CH_2 0x004e0080 /* PLL CHANNEL control CH 2 */
-#define BCHP_CLKGEN_PLL_LC_PLL_CHANNEL_CTRL_CH_3 0x004e0084 /* PLL CHANNEL control CH 3 */
-#define BCHP_CLKGEN_PLL_LC_PLL_CHANNEL_CTRL_CH_4 0x004e0088 /* PLL CHANNEL control CH 4 */
-#define BCHP_CLKGEN_PLL_LC_PLL_CHANNEL_CTRL_CH_5 0x004e008c /* PLL CHANNEL control CH 5 */
-#define BCHP_CLKGEN_PLL_LC_PLL_CONTROL 0x004e0090 /* Miscellaneous Controls */
-#define BCHP_CLKGEN_PLL_LC_PLL_DIV 0x004e0094 /* Pre multiplier */
-#define BCHP_CLKGEN_PLL_LC_PLL_GAIN 0x004e0098 /* PLL GAIN */
-#define BCHP_CLKGEN_PLL_LC_PLL_HOLD_CH_ALL 0x004e009c /* Hold PLL all channels */
-#define BCHP_CLKGEN_PLL_LC_PLL_LDO_CTRL 0x004e00a0 /* Ldo voltage control */
-#define BCHP_CLKGEN_PLL_LC_PLL_LDO_PWRON 0x004e00a4 /* LDO Power on */
-#define BCHP_CLKGEN_PLL_LC_PLL_LOCK_STATUS 0x004e00a8 /* Lock Status */
-#define BCHP_CLKGEN_PLL_LC_PLL_MISC 0x004e00ac /* Mscellaneous control bus. */
-#define BCHP_CLKGEN_PLL_LC_PLL_MISC2 0x004e00b0 /* Mscellaneous control bus continued. */
-#define BCHP_CLKGEN_PLL_LC_PLL_OUTSEL_SEL 0x004e00b4 /* selection of the output clock from the PLL core */
-#define BCHP_CLKGEN_PLL_LC_PLL_PWRON 0x004e00b8 /* Poweron */
-#define BCHP_CLKGEN_PLL_LC_PLL_RESET 0x004e00bc /* Resets */
-#define BCHP_CLKGEN_PLL_LC_PLL_STATUS 0x004e00c0 /* Status */
-#define BCHP_CLKGEN_PLL_LC_PLL_TEST 0x004e00c4 /* enable and selection pf PLL test */
-#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_0 0x004e00c8 /* PLL CHANNEL control CH 0 */
-#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_1 0x004e00cc /* PLL CHANNEL control CH 1 */
-#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_2 0x004e00d0 /* PLL CHANNEL control CH 2 */
-#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_4 0x004e00d4 /* PLL CHANNEL control CH 4 */
-#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_5 0x004e00d8 /* PLL CHANNEL control CH 5 */
-#define BCHP_CLKGEN_PLL_MOCA_PLL_DIV 0x004e00dc /* Pre multiplier */
-#define BCHP_CLKGEN_PLL_MOCA_PLL_GAIN 0x004e00e0 /* PLL GAIN */
-#define BCHP_CLKGEN_PLL_MOCA_PLL_LDO_PWRON 0x004e00e4 /* LDO Power on */
-#define BCHP_CLKGEN_PLL_MOCA_PLL_LOCK_STATUS 0x004e00e8 /* Lock Status */
-#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC 0x004e00ec /* Mscellaneous control bus. */
-#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC2 0x004e00f0 /* Mscellaneous control bus continued. */
-#define BCHP_CLKGEN_PLL_MOCA_PLL_PWRON 0x004e00f4 /* Poweron */
-#define BCHP_CLKGEN_PLL_MOCA_PLL_RESET 0x004e00f8 /* Resets */
-#define BCHP_CLKGEN_PLL_MOCA_PLL_SSC_MODE_CONTROL_HIGH 0x004e00fc /* Higher bits of Spread Spectrum mode control */
-#define BCHP_CLKGEN_PLL_MOCA_PLL_SSC_MODE_CONTROL_LOW 0x004e0100 /* Lower bits of Spread Spectrum mode control */
-#define BCHP_CLKGEN_PLL_MOCA_PLL_STATUS 0x004e0104 /* Status */
-#define BCHP_CLKGEN_PLL_NETWORK_PLL_CHANNEL_CTRL_CH_0 0x004e0108 /* PLL CHANNEL control CH 0 */
-#define BCHP_CLKGEN_PLL_NETWORK_PLL_CHANNEL_CTRL_CH_1 0x004e010c /* PLL CHANNEL control CH 1 */
-#define BCHP_CLKGEN_PLL_NETWORK_PLL_CHANNEL_CTRL_CH_2 0x004e0110 /* PLL CHANNEL control CH 2 */
-#define BCHP_CLKGEN_PLL_NETWORK_PLL_DIV 0x004e0114 /* Pre multiplier */
-#define BCHP_CLKGEN_PLL_NETWORK_PLL_GAIN 0x004e0118 /* PLL GAIN */
-#define BCHP_CLKGEN_PLL_NETWORK_PLL_LDO_PWRON 0x004e011c /* LDO Power on */
-#define BCHP_CLKGEN_PLL_NETWORK_PLL_LOCK_STATUS 0x004e0120 /* Lock Status */
-#define BCHP_CLKGEN_PLL_NETWORK_PLL_MISC 0x004e0124 /* Mscellaneous control bus. */
-#define BCHP_CLKGEN_PLL_NETWORK_PLL_MISC2 0x004e0128 /* Mscellaneous control bus continued. */
-#define BCHP_CLKGEN_PLL_NETWORK_PLL_PWRON 0x004e012c /* Poweron */
-#define BCHP_CLKGEN_PLL_NETWORK_PLL_RESET 0x004e0130 /* Resets */
-#define BCHP_CLKGEN_PLL_NETWORK_PLL_SSC_MODE_CONTROL_HIGH 0x004e0134 /* Higher bits of Spread Spectrum mode control */
-#define BCHP_CLKGEN_PLL_NETWORK_PLL_SSC_MODE_CONTROL_LOW 0x004e0138 /* Lower bits of Spread Spectrum mode control */
-#define BCHP_CLKGEN_PLL_NETWORK_PLL_STATUS 0x004e013c /* Status */
-#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_0 0x004e0140 /* PLL CHANNEL control CH 0 */
-#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_3 0x004e0144 /* PLL CHANNEL control CH 3 */
-#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_4 0x004e0148 /* PLL CHANNEL control CH 4 */
-#define BCHP_CLKGEN_PLL_RAAGA_PLL_DIV 0x004e014c /* Pre multiplier */
-#define BCHP_CLKGEN_PLL_RAAGA_PLL_GAIN 0x004e0150 /* PLL GAIN */
-#define BCHP_CLKGEN_PLL_RAAGA_PLL_LDO_PWRON 0x004e0154 /* LDO Power on */
-#define BCHP_CLKGEN_PLL_RAAGA_PLL_LOCK_STATUS 0x004e0158 /* Lock Status */
-#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC 0x004e015c /* Mscellaneous control bus. */
-#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC2 0x004e0160 /* Mscellaneous control bus continued. */
-#define BCHP_CLKGEN_PLL_RAAGA_PLL_PWRON 0x004e0164 /* Poweron */
-#define BCHP_CLKGEN_PLL_RAAGA_PLL_RESET 0x004e0168 /* Resets */
-#define BCHP_CLKGEN_PLL_RAAGA_PLL_SSC_MODE_CONTROL_HIGH 0x004e016c /* Higher bits of Spread Spectrum mode control */
-#define BCHP_CLKGEN_PLL_RAAGA_PLL_SSC_MODE_CONTROL_LOW 0x004e0170 /* Lower bits of Spread Spectrum mode control */
-#define BCHP_CLKGEN_PLL_RAAGA_PLL_STATUS 0x004e0174 /* Status */
-#define BCHP_CLKGEN_PLL_SC0_PLL_CHANNEL_CTRL_CH_0 0x004e0178 /* PLL CHANNEL control CH 0 */
-#define BCHP_CLKGEN_PLL_SC0_PLL_DIV 0x004e017c /* Pre multiplier */
-#define BCHP_CLKGEN_PLL_SC0_PLL_FRAC 0x004e0180 /* Fractional */
-#define BCHP_CLKGEN_PLL_SC0_PLL_GAIN 0x004e0184 /* PLL GAIN */
-#define BCHP_CLKGEN_PLL_SC0_PLL_LOCK_STATUS 0x004e0188 /* Lock Status */
-#define BCHP_CLKGEN_PLL_SC0_PLL_MISC 0x004e018c /* Mscellaneous control bus. */
-#define BCHP_CLKGEN_PLL_SC0_PLL_MISC2 0x004e0190 /* Mscellaneous control bus continued. */
-#define BCHP_CLKGEN_PLL_SC0_PLL_PWRON 0x004e0194 /* Poweron */
-#define BCHP_CLKGEN_PLL_SC0_PLL_RESET 0x004e0198 /* Resets */
-#define BCHP_CLKGEN_PLL_SC0_PLL_SSC_MODE_CONTROL_HIGH 0x004e019c /* Higher bits of Spread Spectrum mode control */
-#define BCHP_CLKGEN_PLL_SC0_PLL_SSC_MODE_CONTROL_LOW 0x004e01a0 /* Lower bits of Spread Spectrum mode control */
-#define BCHP_CLKGEN_PLL_SC0_PLL_STATUS 0x004e01a4 /* Status */
-#define BCHP_CLKGEN_PLL_SC1_PLL_CHANNEL_CTRL_CH_0 0x004e01a8 /* PLL CHANNEL control CH 0 */
-#define BCHP_CLKGEN_PLL_SC1_PLL_DIV 0x004e01ac /* Pre multiplier */
-#define BCHP_CLKGEN_PLL_SC1_PLL_FRAC 0x004e01b0 /* Fractional */
-#define BCHP_CLKGEN_PLL_SC1_PLL_GAIN 0x004e01b4 /* PLL GAIN */
-#define BCHP_CLKGEN_PLL_SC1_PLL_LOCK_STATUS 0x004e01b8 /* Lock Status */
-#define BCHP_CLKGEN_PLL_SC1_PLL_MISC 0x004e01bc /* Mscellaneous control bus. */
-#define BCHP_CLKGEN_PLL_SC1_PLL_MISC2 0x004e01c0 /* Mscellaneous control bus continued. */
-#define BCHP_CLKGEN_PLL_SC1_PLL_PWRON 0x004e01c4 /* Poweron */
-#define BCHP_CLKGEN_PLL_SC1_PLL_RESET 0x004e01c8 /* Resets */
-#define BCHP_CLKGEN_PLL_SC1_PLL_SSC_MODE_CONTROL_HIGH 0x004e01cc /* Higher bits of Spread Spectrum mode control */
-#define BCHP_CLKGEN_PLL_SC1_PLL_SSC_MODE_CONTROL_LOW 0x004e01d0 /* Lower bits of Spread Spectrum mode control */
-#define BCHP_CLKGEN_PLL_SC1_PLL_STATUS 0x004e01d4 /* Status */
-#define BCHP_CLKGEN_PLL_SDS_PLL_CHANNEL_CTRL_CH_0 0x004e01d8 /* PLL CHANNEL control CH 0 */
-#define BCHP_CLKGEN_PLL_SDS_PLL_CHANNEL_CTRL_CH_1 0x004e01dc /* PLL CHANNEL control CH 1 */
-#define BCHP_CLKGEN_PLL_SDS_PLL_DIV 0x004e01e0 /* Pre multiplier */
-#define BCHP_CLKGEN_PLL_SDS_PLL_GAIN 0x004e01e4 /* PLL GAIN */
-#define BCHP_CLKGEN_PLL_SDS_PLL_LDO_PWRON 0x004e01e8 /* LDO Power on */
-#define BCHP_CLKGEN_PLL_SDS_PLL_LOCK_STATUS 0x004e01ec /* Lock Status */
-#define BCHP_CLKGEN_PLL_SDS_PLL_MISC 0x004e01f0 /* Mscellaneous control bus. */
-#define BCHP_CLKGEN_PLL_SDS_PLL_MISC2 0x004e01f4 /* Mscellaneous control bus continued. */
-#define BCHP_CLKGEN_PLL_SDS_PLL_PWRON 0x004e01f8 /* Poweron */
-#define BCHP_CLKGEN_PLL_SDS_PLL_RESET 0x004e01fc /* Resets */
-#define BCHP_CLKGEN_PLL_SDS_PLL_SSC_MODE_CONTROL_HIGH 0x004e0200 /* Higher bits of Spread Spectrum mode control */
-#define BCHP_CLKGEN_PLL_SDS_PLL_SSC_MODE_CONTROL_LOW 0x004e0204 /* Lower bits of Spread Spectrum mode control */
-#define BCHP_CLKGEN_PLL_SDS_PLL_STATUS 0x004e0208 /* Status */
-#define BCHP_CLKGEN_PLL_SYS0_PLL_BG_PWRON 0x004e020c /* Bandgap Power on */
-#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_0 0x004e0210 /* PLL CHANNEL control CH 0 */
-#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_1 0x004e0214 /* PLL CHANNEL control CH 1 */
-#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2 0x004e0218 /* PLL CHANNEL control CH 2 */
-#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3 0x004e021c /* PLL CHANNEL control CH 3 */
-#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_4 0x004e0220 /* PLL CHANNEL control CH 4 */
-#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_5 0x004e0224 /* PLL CHANNEL control CH 5 */
-#define BCHP_CLKGEN_PLL_SYS0_PLL_DIV 0x004e0228 /* Pre multiplier */
-#define BCHP_CLKGEN_PLL_SYS0_PLL_GAIN 0x004e022c /* PLL GAIN */
-#define BCHP_CLKGEN_PLL_SYS0_PLL_HOLD_CH_ALL 0x004e0230 /* Hold PLL all channels */
-#define BCHP_CLKGEN_PLL_SYS0_PLL_LDO_CTRL 0x004e0234 /* Ldo voltage control */
-#define BCHP_CLKGEN_PLL_SYS0_PLL_LDO_PWRON 0x004e0238 /* LDO Power on */
-#define BCHP_CLKGEN_PLL_SYS0_PLL_LOCK_STATUS 0x004e023c /* Lock Status */
-#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC 0x004e0240 /* Mscellaneous control bus. */
-#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC2 0x004e0244 /* Mscellaneous control bus continued. */
-#define BCHP_CLKGEN_PLL_SYS0_PLL_PWRON 0x004e0248 /* Poweron */
-#define BCHP_CLKGEN_PLL_SYS0_PLL_RESET 0x004e024c /* Resets */
-#define BCHP_CLKGEN_PLL_SYS0_PLL_SSC_MODE_CONTROL_HIGH 0x004e0250 /* Higher bits of Spread Spectrum mode control */
-#define BCHP_CLKGEN_PLL_SYS0_PLL_SSC_MODE_CONTROL_LOW 0x004e0254 /* Lower bits of Spread Spectrum mode control */
-#define BCHP_CLKGEN_PLL_SYS0_PLL_STATUS 0x004e0258 /* Status */
-#define BCHP_CLKGEN_PLL_V3D_PLL_CHANNEL_CTRL_CH_0 0x004e025c /* PLL CHANNEL control CH 0 */
-#define BCHP_CLKGEN_PLL_V3D_PLL_CHANNEL_CTRL_CH_1 0x004e0260 /* PLL CHANNEL control CH 1 */
-#define BCHP_CLKGEN_PLL_V3D_PLL_CHANNEL_CTRL_CH_2 0x004e0264 /* PLL CHANNEL control CH 2 */
-#define BCHP_CLKGEN_PLL_V3D_PLL_CHANNEL_CTRL_CH_5 0x004e0268 /* PLL CHANNEL control CH 5 */
-#define BCHP_CLKGEN_PLL_V3D_PLL_DIV 0x004e026c /* Pre multiplier */
-#define BCHP_CLKGEN_PLL_V3D_PLL_GAIN 0x004e0270 /* PLL GAIN */
-#define BCHP_CLKGEN_PLL_V3D_PLL_LDO_PWRON 0x004e0274 /* LDO Power on */
-#define BCHP_CLKGEN_PLL_V3D_PLL_LOCK_STATUS 0x004e0278 /* Lock Status */
-#define BCHP_CLKGEN_PLL_V3D_PLL_MISC 0x004e027c /* Mscellaneous control bus. */
-#define BCHP_CLKGEN_PLL_V3D_PLL_MISC2 0x004e0280 /* Mscellaneous control bus continued. */
-#define BCHP_CLKGEN_PLL_V3D_PLL_PWRON 0x004e0284 /* Poweron */
-#define BCHP_CLKGEN_PLL_V3D_PLL_RESET 0x004e0288 /* Resets */
-#define BCHP_CLKGEN_PLL_V3D_PLL_SSC_MODE_CONTROL_HIGH 0x004e028c /* Higher bits of Spread Spectrum mode control */
-#define BCHP_CLKGEN_PLL_V3D_PLL_SSC_MODE_CONTROL_LOW 0x004e0290 /* Lower bits of Spread Spectrum mode control */
-#define BCHP_CLKGEN_PLL_V3D_PLL_STATUS 0x004e0294 /* Status */
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_BG_PWRON 0x004e0298 /* Bandgap Power on */
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_CHANNEL_CTRL_CH_0 0x004e029c /* PLL CHANNEL control CH 0 */
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_CHANNEL_CTRL_CH_1 0x004e02a0 /* PLL CHANNEL control CH 1 */
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_CHANNEL_CTRL_CH_2 0x004e02a4 /* PLL CHANNEL control CH 2 */
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_DIV 0x004e02a8 /* Pre multiplier */
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_FRAC 0x004e02ac /* Fractional */
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_GAIN 0x004e02b0 /* PLL GAIN */
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_HOLD_CH_ALL 0x004e02b4 /* Hold PLL all channels */
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_LDO_CTRL 0x004e02b8 /* Ldo voltage control */
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_LDO_PWRON 0x004e02bc /* LDO Power on */
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_LOCK_STATUS 0x004e02c0 /* Lock Status */
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_MISC 0x004e02c4 /* Mscellaneous control bus. */
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_MISC2 0x004e02c8 /* Mscellaneous control bus continued. */
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_PWRON 0x004e02cc /* Poweron */
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_RESET 0x004e02d0 /* Resets */
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_SSC_MODE_CONTROL_HIGH 0x004e02d4 /* Higher bits of Spread Spectrum mode control */
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_SSC_MODE_CONTROL_LOW 0x004e02d8 /* Lower bits of Spread Spectrum mode control */
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_STATUS 0x004e02dc /* Status */
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_BG_PWRON 0x004e02e0 /* Bandgap Power on */
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_CHANNEL_CTRL_CH_0 0x004e02e4 /* PLL CHANNEL control CH 0 */
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_CHANNEL_CTRL_CH_1 0x004e02e8 /* PLL CHANNEL control CH 1 */
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_CHANNEL_CTRL_CH_2 0x004e02ec /* PLL CHANNEL control CH 2 */
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_DIV 0x004e02f0 /* Pre multiplier */
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_FRAC 0x004e02f4 /* Fractional */
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_GAIN 0x004e02f8 /* PLL GAIN */
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_HOLD_CH_ALL 0x004e02fc /* Hold PLL all channels */
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_LDO_CTRL 0x004e0300 /* Ldo voltage control */
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_LDO_PWRON 0x004e0304 /* LDO Power on */
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_LOCK_STATUS 0x004e0308 /* Lock Status */
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_MISC 0x004e030c /* Mscellaneous control bus. */
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_MISC2 0x004e0310 /* Mscellaneous control bus continued. */
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_PWRON 0x004e0314 /* Poweron */
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_RESET 0x004e0318 /* Resets */
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_SSC_MODE_CONTROL_HIGH 0x004e031c /* Higher bits of Spread Spectrum mode control */
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_SSC_MODE_CONTROL_LOW 0x004e0320 /* Lower bits of Spread Spectrum mode control */
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_STATUS 0x004e0324 /* Status */
-#define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_0 0x004e0328 /* PLL CHANNEL control CH 0 */
-#define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_1 0x004e032c /* PLL CHANNEL control CH 1 */
-#define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_2 0x004e0330 /* PLL CHANNEL control CH 2 */
-#define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_3 0x004e0334 /* PLL CHANNEL control CH 3 */
-#define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_4 0x004e0338 /* PLL CHANNEL control CH 4 */
-#define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_5 0x004e033c /* PLL CHANNEL control CH 5 */
-#define BCHP_CLKGEN_PLL_XPT_PLL_DIV 0x004e0340 /* Pre multiplier */
-#define BCHP_CLKGEN_PLL_XPT_PLL_GAIN 0x004e0344 /* PLL GAIN */
-#define BCHP_CLKGEN_PLL_XPT_PLL_LDO_PWRON 0x004e0348 /* LDO Power on */
-#define BCHP_CLKGEN_PLL_XPT_PLL_LOCK_STATUS 0x004e034c /* Lock Status */
-#define BCHP_CLKGEN_PLL_XPT_PLL_MISC 0x004e0350 /* Mscellaneous control bus. */
-#define BCHP_CLKGEN_PLL_XPT_PLL_MISC2 0x004e0354 /* Mscellaneous control bus continued. */
-#define BCHP_CLKGEN_PLL_XPT_PLL_PWRON 0x004e0358 /* Poweron */
-#define BCHP_CLKGEN_PLL_XPT_PLL_RESET 0x004e035c /* Resets */
-#define BCHP_CLKGEN_PLL_XPT_PLL_SSC_MODE_CONTROL_HIGH 0x004e0360 /* Higher bits of Spread Spectrum mode control */
-#define BCHP_CLKGEN_PLL_XPT_PLL_SSC_MODE_CONTROL_LOW 0x004e0364 /* Lower bits of Spread Spectrum mode control */
-#define BCHP_CLKGEN_PLL_XPT_PLL_STATUS 0x004e0368 /* Status */
-#define BCHP_CLKGEN_AIF_MDAC_CAL_TOP_INST_CLOCK_ENABLE 0x004e036c /* Aif mdac cal top inst clock enable */
-#define BCHP_CLKGEN_AIF_MDAC_CAL_TOP_INST_CLOCK_ENABLE_STATUS 0x004e0370 /* Clock Enable Status */
-#define BCHP_CLKGEN_AIF_MDAC_CAL_TOP_INST_OBSERVE_CLOCK 0x004e0374 /* Aif mdac cal top inst observe clock */
-#define BCHP_CLKGEN_AIF_MDAC_CAL_TOP_INST_SEL 0x004e0378 /* Aif mdac cal top inst sel */
-#define BCHP_CLKGEN_AIF_WB_SAT_TOP_0_INST_CLOCK_ENABLE 0x004e037c /* Aif wb sat top 0 inst clock enable */
-#define BCHP_CLKGEN_AIF_WB_SAT_TOP_0_INST_CLOCK_ENABLE_STATUS 0x004e0380 /* Clock Enable Status */
-#define BCHP_CLKGEN_AIF_WB_SAT_TOP_0_INST_OBSERVE_CLOCK 0x004e0384 /* Aif wb sat top 0 inst observe clock */
-#define BCHP_CLKGEN_AIF_WB_SAT_TOP_0_INST_SEL 0x004e0388 /* Aif wb sat top 0 inst sel */
-#define BCHP_CLKGEN_AIF_WB_SAT_TOP_1_INST_CLOCK_ENABLE 0x004e038c /* Aif wb sat top 1 inst clock enable */
-#define BCHP_CLKGEN_AIF_WB_SAT_TOP_1_INST_CLOCK_ENABLE_STATUS 0x004e0390 /* Clock Enable Status */
-#define BCHP_CLKGEN_AIF_WB_SAT_TOP_1_INST_OBSERVE_CLOCK 0x004e0394 /* Aif wb sat top 1 inst observe clock */
-#define BCHP_CLKGEN_AIF_WB_SAT_TOP_1_INST_SEL 0x004e0398 /* Aif wb sat top 1 inst sel */
-#define BCHP_CLKGEN_ANA_QDAC_TS28HPM_6MX_2MR_FC_H_E_INST_CLOCK_DISABLE 0x004e039c /* Disable ANA_QDAC_TS28HPM_6MX_2MR_FC_H_E_INST's clocks */
-#define BCHP_CLKGEN_ANA_QDAC_TS28HPM_6MX_2MR_FC_H_E_INST_CLOCK_DISABLE_STATUS 0x004e03a0 /* Clock Disable Status */
-#define BCHP_CLKGEN_ANA_SW_AVS_TS28HPM_6MX_2MR_FC_H_E_INST_CLOCK_DISABLE 0x004e03a4 /* Disable ANA_SW_AVS_TS28HPM_6MX_2MR_FC_H_E_INST's clocks */
-#define BCHP_CLKGEN_ANA_SW_AVS_TS28HPM_6MX_2MR_FC_H_E_INST_CLOCK_DISABLE_STATUS 0x004e03a8 /* Clock Disable Status */
-#define BCHP_CLKGEN_BVN_MVP_TOP_INST_CKTAPSEL 0x004e03ac /* Bvn mvp top inst cktapsel */
-#define BCHP_CLKGEN_BVN_MVP_TOP_INST_CLOCK_ENABLE 0x004e03b0 /* Bvn mvp top inst clock enable */
-#define BCHP_CLKGEN_BVN_MVP_TOP_INST_CLOCK_ENABLE_STATUS 0x004e03b4 /* Clock Enable Status */
-#define BCHP_CLKGEN_BVN_TOP_INST_CKTAPSEL 0x004e03b8 /* Bvn top inst cktapsel */
-#define BCHP_CLKGEN_BVN_TOP_INST_CLOCK_ENABLE 0x004e03bc /* Bvn top inst clock enable */
-#define BCHP_CLKGEN_BVN_TOP_INST_CLOCK_ENABLE_STATUS 0x004e03c0 /* Clock Enable Status */
-#define BCHP_CLKGEN_CLKGEN_CLOCK_DISABLE 0x004e03c4 /* Disable CLKGEN's clocks */
-#define BCHP_CLKGEN_CLKGEN_CLOCK_DISABLE_STATUS 0x004e03c8 /* Clock Disable Status */
-#define BCHP_CLKGEN_CLOCK_MONITOR_CONTROL 0x004e03cc /* Clock Monitor Control */
-#define BCHP_CLKGEN_CLOCK_MONITOR_MAX_COUNT 0x004e03d0 /* Clock Monitor Max Reference Count */
-#define BCHP_CLKGEN_CLOCK_MONITOR_REF_COUNTER 0x004e03d4 /* Clock Monitor Reference Counter */
-#define BCHP_CLKGEN_CLOCK_MONITOR_REF_DONE 0x004e03d8 /* Clock Monitor Reference Counter */
-#define BCHP_CLKGEN_CLOCK_MONITOR_VIEW_COUNTER 0x004e03dc /* Clock Monitor View Counter */
-#define BCHP_CLKGEN_CORE_XPT_INST_CKTAPSEL 0x004e03e0 /* Core xpt inst cktapsel */
-#define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_DISABLE 0x004e03e4 /* Disable CORE_XPT_INST's clocks */
-#define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_DISABLE_STATUS 0x004e03e8 /* Clock Disable Status */
-#define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_ENABLE 0x004e03ec /* Core xpt inst clock enable */
-#define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_ENABLE_STATUS 0x004e03f0 /* Clock Enable Status */
-#define BCHP_CLKGEN_CORE_XPT_INST_OBSERVE_CLOCK 0x004e03f4 /* Core xpt inst observe clock */
-#define BCHP_CLKGEN_DISABLE_AVS_TOP_DURING_S2 0x004e03f8 /* Disable AVS_TOP 54MHz clocks during S2 standby. */
-#define BCHP_CLKGEN_DISABLE_AVS_TOP_DURING_S2_SECURE 0x004e03fc /* Secure AVS_TOP clock disable. Set at start-up to guarantee AVS_TOP is clock gated in S2 standby. */
-#define BCHP_CLKGEN_DUALSDS_0_INST_CLOCK_DISABLE 0x004e0400 /* Disable DUALSDS_0_INST's clocks */
-#define BCHP_CLKGEN_DUALSDS_0_INST_CLOCK_DISABLE_STATUS 0x004e0404 /* Clock Disable Status */
-#define BCHP_CLKGEN_DUALSDS_0_INST_CLOCK_ENABLE_CH0 0x004e0408 /* Dualsds 0 inst clock enable ch0 */
-#define BCHP_CLKGEN_DUALSDS_0_INST_CLOCK_ENABLE_CH0_STATUS 0x004e040c /* Clock Enable Status */
-#define BCHP_CLKGEN_DUALSDS_0_INST_CLOCK_ENABLE_CH1 0x004e0410 /* Dualsds 0 inst clock enable ch1 */
-#define BCHP_CLKGEN_DUALSDS_0_INST_CLOCK_ENABLE_CH1_STATUS 0x004e0414 /* Clock Enable Status */
-#define BCHP_CLKGEN_DUALSDS_0_INST_EN_CH0 0x004e0418 /* Dualsds 0 inst en ch0 */
-#define BCHP_CLKGEN_DUALSDS_0_INST_EN_CH1 0x004e041c /* Dualsds 0 inst en ch1 */
-#define BCHP_CLKGEN_DUALSDS_0_INST_OBSERVE_CLOCK 0x004e0420 /* Dualsds 0 inst observe clock */
-#define BCHP_CLKGEN_DUALSDS_0_INST_PLL_CLOCK_EN 0x004e0424 /* Dualsds 0 inst pll clock en */
-#define BCHP_CLKGEN_DUALSDS_0_INST_SEL 0x004e0428 /* Dualsds 0 inst sel */
-#define BCHP_CLKGEN_DUALSDS_1_INST_CLOCK_DISABLE 0x004e042c /* Disable DUALSDS_1_INST's clocks */
-#define BCHP_CLKGEN_DUALSDS_1_INST_CLOCK_DISABLE_STATUS 0x004e0430 /* Clock Disable Status */
-#define BCHP_CLKGEN_DUALSDS_1_INST_CLOCK_ENABLE_CH0 0x004e0434 /* Dualsds 1 inst clock enable ch0 */
-#define BCHP_CLKGEN_DUALSDS_1_INST_CLOCK_ENABLE_CH0_STATUS 0x004e0438 /* Clock Enable Status */
-#define BCHP_CLKGEN_DUALSDS_1_INST_CLOCK_ENABLE_CH1 0x004e043c /* Dualsds 1 inst clock enable ch1 */
-#define BCHP_CLKGEN_DUALSDS_1_INST_CLOCK_ENABLE_CH1_STATUS 0x004e0440 /* Clock Enable Status */
-#define BCHP_CLKGEN_DUALSDS_1_INST_EN_CH0 0x004e0444 /* Dualsds 1 inst en ch0 */
-#define BCHP_CLKGEN_DUALSDS_1_INST_EN_CH1 0x004e0448 /* Dualsds 1 inst en ch1 */
-#define BCHP_CLKGEN_DUALSDS_1_INST_OBSERVE_CLOCK 0x004e044c /* Dualsds 1 inst observe clock */
-#define BCHP_CLKGEN_DUALSDS_1_INST_PLL_CLOCK_EN 0x004e0450 /* Dualsds 1 inst pll clock en */
-#define BCHP_CLKGEN_DUALSDS_1_INST_SEL 0x004e0454 /* Dualsds 1 inst sel */
-#define BCHP_CLKGEN_DUALSDS_2_INST_CLOCK_DISABLE 0x004e0458 /* Disable DUALSDS_2_INST's clocks */
-#define BCHP_CLKGEN_DUALSDS_2_INST_CLOCK_DISABLE_STATUS 0x004e045c /* Clock Disable Status */
-#define BCHP_CLKGEN_DUALSDS_2_INST_CLOCK_ENABLE_CH0 0x004e0460 /* Dualsds 2 inst clock enable ch0 */
-#define BCHP_CLKGEN_DUALSDS_2_INST_CLOCK_ENABLE_CH0_STATUS 0x004e0464 /* Clock Enable Status */
-#define BCHP_CLKGEN_DUALSDS_2_INST_CLOCK_ENABLE_CH1 0x004e0468 /* Dualsds 2 inst clock enable ch1 */
-#define BCHP_CLKGEN_DUALSDS_2_INST_CLOCK_ENABLE_CH1_STATUS 0x004e046c /* Clock Enable Status */
-#define BCHP_CLKGEN_DUALSDS_2_INST_EN_CH0 0x004e0470 /* Dualsds 2 inst en ch0 */
-#define BCHP_CLKGEN_DUALSDS_2_INST_EN_CH1 0x004e0474 /* Dualsds 2 inst en ch1 */
-#define BCHP_CLKGEN_DUALSDS_2_INST_OBSERVE_CLOCK 0x004e0478 /* Dualsds 2 inst observe clock */
-#define BCHP_CLKGEN_DUALSDS_2_INST_PLL_CLOCK_EN 0x004e047c /* Dualsds 2 inst pll clock en */
-#define BCHP_CLKGEN_DUALSDS_2_INST_SEL 0x004e0480 /* Dualsds 2 inst sel */
-#define BCHP_CLKGEN_DUALSDS_3_INST_CLOCK_DISABLE 0x004e0484 /* Disable DUALSDS_3_INST's clocks */
-#define BCHP_CLKGEN_DUALSDS_3_INST_CLOCK_DISABLE_STATUS 0x004e0488 /* Clock Disable Status */
-#define BCHP_CLKGEN_DUALSDS_3_INST_CLOCK_ENABLE_CH0 0x004e048c /* Dualsds 3 inst clock enable ch0 */
-#define BCHP_CLKGEN_DUALSDS_3_INST_CLOCK_ENABLE_CH0_STATUS 0x004e0490 /* Clock Enable Status */
-#define BCHP_CLKGEN_DUALSDS_3_INST_CLOCK_ENABLE_CH1 0x004e0494 /* Dualsds 3 inst clock enable ch1 */
-#define BCHP_CLKGEN_DUALSDS_3_INST_CLOCK_ENABLE_CH1_STATUS 0x004e0498 /* Clock Enable Status */
-#define BCHP_CLKGEN_DUALSDS_3_INST_EN_CH0 0x004e049c /* Dualsds 3 inst en ch0 */
-#define BCHP_CLKGEN_DUALSDS_3_INST_EN_CH1 0x004e04a0 /* Dualsds 3 inst en ch1 */
-#define BCHP_CLKGEN_DUALSDS_3_INST_OBSERVE_CLOCK 0x004e04a4 /* Dualsds 3 inst observe clock */
-#define BCHP_CLKGEN_DUALSDS_3_INST_PLL_CLOCK_EN 0x004e04a8 /* Dualsds 3 inst pll clock en */
-#define BCHP_CLKGEN_DUALSDS_3_INST_SEL 0x004e04ac /* Dualsds 3 inst sel */
-#define BCHP_CLKGEN_DVP_HR_INST_CLOCK_DISABLE 0x004e04b0 /* Disable DVP_HR_INST's clocks */
-#define BCHP_CLKGEN_DVP_HR_INST_CLOCK_DISABLE_STATUS 0x004e04b4 /* Clock Disable Status */
-#define BCHP_CLKGEN_DVP_HR_INST_CLOCK_ENABLE 0x004e04b8 /* Dvp hr inst clock enable */
-#define BCHP_CLKGEN_DVP_HR_INST_CLOCK_ENABLE0 0x004e04bc /* Dvp hr inst clock enable0 */
-#define BCHP_CLKGEN_DVP_HR_INST_CLOCK_ENABLE0_STATUS 0x004e04c0 /* Clock Enable Status */
-#define BCHP_CLKGEN_DVP_HR_INST_CLOCK_ENABLE_STATUS 0x004e04c4 /* Clock Enable Status */
-#define BCHP_CLKGEN_DVP_HR_INST_OBSERVE_CLOCK 0x004e04c8 /* Dvp hr inst observe clock */
-#define BCHP_CLKGEN_DVP_HT_DUAL_WRAPPER_INST_CLOCK_DISABLE 0x004e04cc /* Disable DVP_HT_DUAL_WRAPPER_INST's clocks */
-#define BCHP_CLKGEN_DVP_HT_DUAL_WRAPPER_INST_CLOCK_DISABLE_STATUS 0x004e04d0 /* Clock Disable Status */
-#define BCHP_CLKGEN_DVP_HT_DUAL_WRAPPER_INST_CLOCK_ENABLE 0x004e04d4 /* Dvp ht dual wrapper inst clock enable */
-#define BCHP_CLKGEN_DVP_HT_DUAL_WRAPPER_INST_CLOCK_ENABLE_STATUS 0x004e04d8 /* Clock Enable Status */
-#define BCHP_CLKGEN_DVP_HT_DUAL_WRAPPER_INST_ENABLE 0x004e04dc /* Dvp ht dual wrapper inst enable */
-#define BCHP_CLKGEN_DVP_HT_DUAL_WRAPPER_INST_OBSERVE_CLOCK 0x004e04e0 /* Dvp ht dual wrapper inst observe clock */
-#define BCHP_CLKGEN_EAGLET_TOP_INST_CKTAPSEL 0x004e04e4 /* Eaglet top inst cktapsel */
-#define BCHP_CLKGEN_EAGLET_TOP_INST_CLOCK_DISABLE 0x004e04e8 /* Disable EAGLET_TOP_INST's clocks */
-#define BCHP_CLKGEN_EAGLET_TOP_INST_CLOCK_DISABLE_STATUS 0x004e04ec /* Clock Disable Status */
-#define BCHP_CLKGEN_EAGLET_TOP_INST_CLOCK_ENABLE 0x004e04f0 /* Eaglet top inst clock enable */
-#define BCHP_CLKGEN_EAGLET_TOP_INST_CLOCK_ENABLE_STATUS 0x004e04f4 /* Clock Enable Status */
-#define BCHP_CLKGEN_EGPHY28_1PORT_33V_90O_FC_INST_DIV5 0x004e04f8 /* Egphy28 1port 33v 90o fc inst div5 */
-#define BCHP_CLKGEN_EGPHY28_1PORT_33V_90O_FC_INST_SEL 0x004e04fc /* Egphy28 1port 33v 90o fc inst sel */
-#define BCHP_CLKGEN_FSK_TOP_INST_CLOCK_ENABLE 0x004e0500 /* Fsk top inst clock enable */
-#define BCHP_CLKGEN_FSK_TOP_INST_CLOCK_ENABLE_STATUS 0x004e0504 /* Clock Enable Status */
-#define BCHP_CLKGEN_FSK_TOP_INST_OBSERVE_CLOCK 0x004e0508 /* Fsk top inst observe clock */
-#define BCHP_CLKGEN_GRAPHICS_INST_ALT_CLOCK_ENABLE_M2MC 0x004e050c /* Graphics inst alt clock enable m2mc */
-#define BCHP_CLKGEN_GRAPHICS_INST_CKTAPSEL 0x004e0510 /* Graphics inst cktapsel */
-#define BCHP_CLKGEN_GRAPHICS_INST_CLOCK_ENABLE_M2MC 0x004e0514 /* Graphics inst clock enable m2mc */
-#define BCHP_CLKGEN_GRAPHICS_INST_CLOCK_ENABLE_M2MC1 0x004e0518 /* Graphics inst clock enable m2mc1 */
-#define BCHP_CLKGEN_GRAPHICS_INST_CLOCK_ENABLE_M2MC1_STATUS 0x004e051c /* Clock Enable Status */
-#define BCHP_CLKGEN_GRAPHICS_INST_CLOCK_ENABLE_M2MC_STATUS 0x004e0520 /* Clock Enable Status */
-#define BCHP_CLKGEN_GRAPHICS_INST_OBSERVE_CLOCK 0x004e0524 /* Graphics inst observe clock */
-#define BCHP_CLKGEN_HIF_INST_CKTAPSEL 0x004e0528 /* Hif inst cktapsel */
-#define BCHP_CLKGEN_HIF_INST_CLOCK_DISABLE 0x004e052c /* Disable HIF_INST's clocks */
-#define BCHP_CLKGEN_HIF_INST_CLOCK_DISABLE_STATUS 0x004e0530 /* Clock Disable Status */
-#define BCHP_CLKGEN_HIF_INST_CLOCK_ENABLE 0x004e0534 /* Hif inst clock enable */
-#define BCHP_CLKGEN_HIF_INST_CLOCK_ENABLE_STATUS 0x004e0538 /* Clock Enable Status */
-#define BCHP_CLKGEN_HIF_INST_OBSERVE_CLOCK 0x004e053c /* Hif inst observe clock */
-#define BCHP_CLKGEN_HVD_SID0_TOP_INST_CKTAPSEL 0x004e0540 /* Hvd sid0 top inst cktapsel */
-#define BCHP_CLKGEN_HVD_SID0_TOP_INST_CLOCK_ENABLE 0x004e0544 /* Hvd sid0 top inst clock enable */
-#define BCHP_CLKGEN_HVD_SID0_TOP_INST_CLOCK_ENABLE_SID 0x004e0548 /* Hvd sid0 top inst clock enable sid */
-#define BCHP_CLKGEN_HVD_SID0_TOP_INST_CLOCK_ENABLE_SID_STATUS 0x004e054c /* Clock Enable Status */
-#define BCHP_CLKGEN_HVD_SID0_TOP_INST_CLOCK_ENABLE_STATUS 0x004e0550 /* Clock Enable Status */
-#define BCHP_CLKGEN_HVD_SID0_TOP_INST_OBSERVE_CLOCK 0x004e0554 /* Hvd sid0 top inst observe clock */
-#define BCHP_CLKGEN_INTERNAL_MUX_SELECT 0x004e0558 /* Mux selects for Internal clocks */
-#define BCHP_CLKGEN_ITU656_0_MUX_SELECT 0x004e055c /* Mux selects for itu656_0 clocks */
-#define BCHP_CLKGEN_LEAP_TOP_INST_CKTAPSEL 0x004e0560 /* Leap top inst cktapsel */
-#define BCHP_CLKGEN_LEAP_TOP_INST_CLOCK_DISABLE 0x004e0564 /* Disable LEAP_TOP_INST's clocks */
-#define BCHP_CLKGEN_LEAP_TOP_INST_CLOCK_DISABLE_STATUS 0x004e0568 /* Clock Disable Status */
-#define BCHP_CLKGEN_LEAP_TOP_INST_CLOCK_ENABLE 0x004e056c /* Leap top inst clock enable */
-#define BCHP_CLKGEN_LEAP_TOP_INST_CLOCK_ENABLE_STATUS 0x004e0570 /* Clock Enable Status */
-#define BCHP_CLKGEN_MEMSYS_32_0_INST_CKTAPSEL 0x004e0574 /* Memsys 32 0 inst cktapsel */
-#define BCHP_CLKGEN_MEMSYS_32_0_INST_CLOCK_ENABLE 0x004e0578 /* Memsys 32 0 inst clock enable */
-#define BCHP_CLKGEN_MEMSYS_32_0_INST_CLOCK_ENABLE_STATUS 0x004e057c /* Clock Enable Status */
-#define BCHP_CLKGEN_MEMSYS_32_0_INST_OBSERVE_CLOCK 0x004e0580 /* Memsys 32 0 inst observe clock */
-#define BCHP_CLKGEN_MEMSYS_32_0_INST_STATUS 0x004e0584 /* Memsys 32 0 inst status */
-#define BCHP_CLKGEN_MEMSYS_32_1_INST_CKTAPSEL 0x004e0588 /* Memsys 32 1 inst cktapsel */
-#define BCHP_CLKGEN_MEMSYS_32_1_INST_CLOCK_ENABLE 0x004e058c /* Memsys 32 1 inst clock enable */
-#define BCHP_CLKGEN_MEMSYS_32_1_INST_CLOCK_ENABLE_STATUS 0x004e0590 /* Clock Enable Status */
-#define BCHP_CLKGEN_MEMSYS_32_1_INST_OBSERVE_CLOCK 0x004e0594 /* Memsys 32 1 inst observe clock */
-#define BCHP_CLKGEN_MEMSYS_32_1_INST_STATUS 0x004e0598 /* Memsys 32 1 inst status */
-#define BCHP_CLKGEN_MOCAMAC_TOP_INST_CKTAPSEL 0x004e059c /* Mocamac top inst cktapsel */
-#define BCHP_CLKGEN_MOCAMAC_TOP_INST_CLOCK_ENABLE 0x004e05a0 /* Mocamac top inst clock enable */
-#define BCHP_CLKGEN_MOCAMAC_TOP_INST_CLOCK_ENABLE_STATUS 0x004e05a4 /* Clock Enable Status */
-#define BCHP_CLKGEN_MOCAMAC_TOP_INST_OBSERVE_CLOCK 0x004e05a8 /* Mocamac top inst observe clock */
-#define BCHP_CLKGEN_MOCAPHY_TOP_INST_CLOCK_ENABLE 0x004e05ac /* Mocaphy top inst clock enable */
-#define BCHP_CLKGEN_MOCAPHY_TOP_INST_CLOCK_ENABLE_STATUS 0x004e05b0 /* Clock Enable Status */
-#define BCHP_CLKGEN_MOCAPHY_TOP_INST_OBSERVE_CLOCK 0x004e05b4 /* Mocaphy top inst observe clock */
-#define BCHP_CLKGEN_PAD_BYP_CLK_0_OBSERVATION 0x004e05b8 /* Select observation clk */
-#define BCHP_CLKGEN_PAD_BYP_CLK_1_OBSERVATION 0x004e05bc /* Select observation clk */
-#define BCHP_CLKGEN_PAD_CLOCK_DISABLE 0x004e05c0 /* Disable PAD's clocks */
-#define BCHP_CLKGEN_PAD_CLOCK_DISABLE_STATUS 0x004e05c4 /* Clock Disable Status */
-#define BCHP_CLKGEN_PAD_CODEC_MCLK_OBSERVATION 0x004e05c8 /* Select observation clk */
-#define BCHP_CLKGEN_PAD_MUX_SELECT 0x004e05cc /* Mux selects for Pad clocks */
-#define BCHP_CLKGEN_PCIE_X1_TOP_INST_CKTAPSEL 0x004e05d0 /* Pcie x1 top inst cktapsel */
-#define BCHP_CLKGEN_PCIE_X1_TOP_INST_CLOCK_DISABLE 0x004e05d4 /* Disable PCIE_X1_TOP_INST's clocks */
-#define BCHP_CLKGEN_PCIE_X1_TOP_INST_CLOCK_DISABLE_STATUS 0x004e05d8 /* Clock Disable Status */
-#define BCHP_CLKGEN_PCIE_X1_TOP_INST_CLOCK_ENABLE 0x004e05dc /* Pcie x1 top inst clock enable */
-#define BCHP_CLKGEN_PCIE_X1_TOP_INST_CLOCK_ENABLE_STATUS 0x004e05e0 /* Clock Enable Status */
-#define BCHP_CLKGEN_PCIE_X1_TOP_INST_OBSERVE_CLOCK 0x004e05e4 /* Pcie x1 top inst observe clock */
-#define BCHP_CLKGEN_PLL_AUDIO0_AUDIO0 0x004e05e8 /* Pll audio0 audio0 */
-#define BCHP_CLKGEN_PLL_AUDIO1_AUDIO1 0x004e05ec /* Pll audio1 audio1 */
-#define BCHP_CLKGEN_PLL_CPU_GLITCHLESS_SWITCH_REQUEST 0x004e05f0 /* PLL_CPU Glitchless Clock Switching */
-#define BCHP_CLKGEN_PLL_CPU_GLITCHLESS_SWITCH_STATUS 0x004e05f4 /* PLL_CPU Glitchless Switching */
-#define BCHP_CLKGEN_PLL_CPU_PLL_RESET_STATUS 0x004e05f8 /* PLL_CPU Reset Status */
-#define BCHP_CLKGEN_PLL_CPU_RDB_MACRO_CTRL 0x004e05fc /* PLL RDB Macro Disable */
-#define BCHP_CLKGEN_PLL_HVD_PLL_RESET_STATUS 0x004e0600 /* PLL_HVD Reset Status */
-#define BCHP_CLKGEN_PLL_HVD_RDB_MACRO_CTRL 0x004e0604 /* PLL RDB Macro Disable */
-#define BCHP_CLKGEN_PLL_LC_PLL_RESET_STATUS 0x004e0608 /* PLL_LC Reset Status */
-#define BCHP_CLKGEN_PLL_MOCA_PLL_RESET_STATUS 0x004e060c /* PLL_MOCA Reset Status */
-#define BCHP_CLKGEN_PLL_MOCA_RDB_MACRO_CTRL 0x004e0610 /* PLL RDB Macro Disable */
-#define BCHP_CLKGEN_PLL_NETWORK_PLL_RESET_STATUS 0x004e0614 /* PLL_NETWORK Reset Status */
-#define BCHP_CLKGEN_PLL_NETWORK_RDB_MACRO_CTRL 0x004e0618 /* PLL RDB Macro Disable */
-#define BCHP_CLKGEN_PLL_RAAGA_PLL_RESET_STATUS 0x004e061c /* PLL_RAAGA Reset Status */
-#define BCHP_CLKGEN_PLL_RAAGA_RDB_MACRO_CTRL 0x004e0620 /* PLL RDB Macro Disable */
-#define BCHP_CLKGEN_PLL_SC0_PLL_RESET_STATUS 0x004e0624 /* PLL_SC0 Reset Status */
-#define BCHP_CLKGEN_PLL_SC0_RDB_MACRO_CTRL 0x004e0628 /* PLL RDB Macro Disable */
-#define BCHP_CLKGEN_PLL_SC1_PLL_RESET_STATUS 0x004e062c /* PLL_SC1 Reset Status */
-#define BCHP_CLKGEN_PLL_SC1_RDB_MACRO_CTRL 0x004e0630 /* PLL RDB Macro Disable */
-#define BCHP_CLKGEN_PLL_SDS_PLL_RESET_STATUS 0x004e0634 /* PLL_SDS Reset Status */
-#define BCHP_CLKGEN_PLL_V3D_PLL_RESET_STATUS 0x004e063c /* PLL_V3D Reset Status */
-#define BCHP_CLKGEN_PLL_V3D_RDB_MACRO_CTRL 0x004e0640 /* PLL RDB Macro Disable */
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_RESET_STATUS 0x004e0644 /* PLL_VCXO0 Reset Status */
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_RESET_STATUS 0x004e0648 /* PLL_VCXO1 Reset Status */
-#define BCHP_CLKGEN_PLL_XPT_RDB_MACRO_CTRL 0x004e064c /* PLL RDB Macro Disable */
-#define BCHP_CLKGEN_PM_CLOCK_108_ALIVE_SEL 0x004e0650 /* Select clocks that can stay alive during power management standby mode. */
-#define BCHP_CLKGEN_PM_CLOCK_Async_ALIVE_SEL 0x004e0654 /* Select clocks that can stay alive during power management standby mode. */
-#define BCHP_CLKGEN_PM_CLOCK_Gisb_ALIVE_SEL 0x004e0658 /* Select clocks that can stay alive during power management standby mode. */
-#define BCHP_CLKGEN_PM_PLL_ALIVE_SEL 0x004e065c /* PLL Alive in Standby Mode */
-#define BCHP_CLKGEN_PM_PLL_LDO_POWERUP 0x004e0660 /* Power management LDO PLL */
-#define BCHP_CLKGEN_PROD_OTP_INST_CLOCK_DISABLE 0x004e0664 /* Disable PROD_OTP_INST's clocks */
-#define BCHP_CLKGEN_PROD_OTP_INST_CLOCK_DISABLE_STATUS 0x004e0668 /* Clock Disable Status */
-#define BCHP_CLKGEN_PROD_OTP_INST_CLOCK_ENABLE 0x004e066c /* Prod otp inst clock enable */
-#define BCHP_CLKGEN_PROD_OTP_INST_CLOCK_ENABLE_STATUS 0x004e0670 /* Clock Enable Status */
-#define BCHP_CLKGEN_RAAGA_DSP_TOP_0_INST_CKTAPSEL 0x004e0674 /* Raaga dsp top 0 inst cktapsel */
-#define BCHP_CLKGEN_RAAGA_DSP_TOP_0_INST_CLOCK_ENABLE 0x004e0678 /* Raaga dsp top 0 inst clock enable */
-#define BCHP_CLKGEN_RAAGA_DSP_TOP_0_INST_CLOCK_ENABLE_STATUS 0x004e067c /* Clock Enable Status */
-#define BCHP_CLKGEN_RAAGA_DSP_TOP_0_INST_OBSERVE_CLOCK 0x004e0680 /* Raaga dsp top 0 inst observe clock */
-#define BCHP_CLKGEN_RFM_TOP_INST_CLOCK_ENABLE 0x004e0684 /* Rfm top inst clock enable */
-#define BCHP_CLKGEN_RFM_TOP_INST_CLOCK_ENABLE_STATUS 0x004e0688 /* Clock Enable Status */
-#define BCHP_CLKGEN_RFM_TOP_INST_OBSERVE_CLOCK 0x004e068c /* Rfm top inst observe clock */
-#define BCHP_CLKGEN_SATA3_PCIE_TOP_INST_CKTAPSEL 0x004e0690 /* Sata3 pcie top inst cktapsel */
-#define BCHP_CLKGEN_SATA3_PCIE_TOP_INST_CLOCK_DISABLE 0x004e0694 /* Disable SATA3_PCIE_TOP_INST's clocks */
-#define BCHP_CLKGEN_SATA3_PCIE_TOP_INST_CLOCK_DISABLE_STATUS 0x004e0698 /* Clock Disable Status */
-#define BCHP_CLKGEN_SATA3_PCIE_TOP_INST_CLOCK_ENABLE_PCIE 0x004e069c /* Sata3 pcie top inst clock enable pcie */
-#define BCHP_CLKGEN_SATA3_PCIE_TOP_INST_CLOCK_ENABLE_PCIE_STATUS 0x004e06a0 /* Clock Enable Status */
-#define BCHP_CLKGEN_SATA3_PCIE_TOP_INST_CLOCK_ENABLE_SATA3 0x004e06a4 /* Sata3 pcie top inst clock enable sata3 */
-#define BCHP_CLKGEN_SATA3_PCIE_TOP_INST_CLOCK_ENABLE_SATA3_STATUS 0x004e06a8 /* Clock Enable Status */
-#define BCHP_CLKGEN_SATA3_PCIE_TOP_INST_CLOCK_SELECT 0x004e06ac /* Sata3 pcie top inst clock select */
-#define BCHP_CLKGEN_SATA3_PCIE_TOP_INST_OBSERVE_CLOCK 0x004e06b0 /* Sata3 pcie top inst observe clock */
-#define BCHP_CLKGEN_SCB_CHANNEL_2_INST_CKTAPSEL 0x004e06b4 /* Scb channel 2 inst cktapsel */
-#define BCHP_CLKGEN_SCB_CHANNEL_3_INST_CKTAPSEL 0x004e06b8 /* Scb channel 3 inst cktapsel */
-#define BCHP_CLKGEN_SCB_CHANNEL_4_INST_CKTAPSEL 0x004e06bc /* Scb channel 4 inst cktapsel */
-#define BCHP_CLKGEN_SCB_CHANNEL_INST_CKTAPSEL 0x004e06c0 /* Scb channel inst cktapsel */
-#define BCHP_CLKGEN_SDS_AFEC2X_TOP_0_INST_CLOCK_ENABLE 0x004e06c4 /* Sds afec2x top 0 inst clock enable */
-#define BCHP_CLKGEN_SDS_AFEC2X_TOP_0_INST_CLOCK_ENABLE_STATUS 0x004e06c8 /* Clock Enable Status */
-#define BCHP_CLKGEN_SDS_AFEC2X_TOP_0_INST_OBSERVE_CLOCK 0x004e06cc /* Sds afec2x top 0 inst observe clock */
-#define BCHP_CLKGEN_SDS_AFEC2X_TOP_0_INST_SEL 0x004e06d0 /* Sds afec2x top 0 inst sel */
-#define BCHP_CLKGEN_SDS_AFEC2X_TOP_1_INST_CLOCK_ENABLE 0x004e06d4 /* Sds afec2x top 1 inst clock enable */
-#define BCHP_CLKGEN_SDS_AFEC2X_TOP_1_INST_CLOCK_ENABLE_STATUS 0x004e06d8 /* Clock Enable Status */
-#define BCHP_CLKGEN_SDS_AFEC2X_TOP_1_INST_OBSERVE_CLOCK 0x004e06dc /* Sds afec2x top 1 inst observe clock */
-#define BCHP_CLKGEN_SDS_AFEC2X_TOP_1_INST_SEL 0x004e06e0 /* Sds afec2x top 1 inst sel */
-#define BCHP_CLKGEN_SDS_AFEC2X_TOP_2_INST_CLOCK_ENABLE 0x004e06e4 /* Sds afec2x top 2 inst clock enable */
-#define BCHP_CLKGEN_SDS_AFEC2X_TOP_2_INST_CLOCK_ENABLE_STATUS 0x004e06e8 /* Clock Enable Status */
-#define BCHP_CLKGEN_SDS_AFEC2X_TOP_2_INST_OBSERVE_CLOCK 0x004e06ec /* Sds afec2x top 2 inst observe clock */
-#define BCHP_CLKGEN_SDS_AFEC2X_TOP_2_INST_SEL 0x004e06f0 /* Sds afec2x top 2 inst sel */
-#define BCHP_CLKGEN_SDS_AFEC2X_TOP_3_INST_CLOCK_ENABLE 0x004e06f4 /* Sds afec2x top 3 inst clock enable */
-#define BCHP_CLKGEN_SDS_AFEC2X_TOP_3_INST_CLOCK_ENABLE_STATUS 0x004e06f8 /* Clock Enable Status */
-#define BCHP_CLKGEN_SDS_AFEC2X_TOP_3_INST_OBSERVE_CLOCK 0x004e06fc /* Sds afec2x top 3 inst observe clock */
-#define BCHP_CLKGEN_SDS_AFEC2X_TOP_3_INST_SEL 0x004e0700 /* Sds afec2x top 3 inst sel */
-#define BCHP_CLKGEN_SECTOP_INST_CKTAPSEL 0x004e0704 /* Sectop inst cktapsel */
-#define BCHP_CLKGEN_SECTOP_INST_OBSERVE_CLOCK 0x004e0708 /* Sectop inst observe clock */
-#define BCHP_CLKGEN_SMARTCARD_MUX_SELECT 0x004e070c /* Mux selects for Smartcard clocks */
-#define BCHP_CLKGEN_SPARE 0x004e0710 /* Spares */
-#define BCHP_CLKGEN_CKTAP_CTRL 0x004e0714 /* cktap control */
-#define BCHP_CLKGEN_STB_CHAN_TOP_INST_CLOCK_ENABLE 0x004e0718 /* Stb chan top inst clock enable */
-#define BCHP_CLKGEN_STB_CHAN_TOP_INST_CLOCK_ENABLE_STATUS 0x004e071c /* Clock Enable Status */
-#define BCHP_CLKGEN_STB_CHAN_TOP_INST_OBSERVE_CLOCK 0x004e0720 /* Stb chan top inst observe clock */
-#define BCHP_CLKGEN_SYS_CTRL_INST_CKTAPSEL 0x004e0724 /* Sys ctrl inst cktapsel */
-#define BCHP_CLKGEN_SYS_CTRL_INST_CLOCK_DISABLE 0x004e0728 /* Disable SYS_CTRL_INST's clocks */
-#define BCHP_CLKGEN_SYS_CTRL_INST_CLOCK_DISABLE_STATUS 0x004e072c /* Clock Disable Status */
-#define BCHP_CLKGEN_SYS_CTRL_INST_OBSERVE_CLOCK 0x004e0730 /* Sys ctrl inst observe clock */
-#define BCHP_CLKGEN_TESTPORT 0x004e0734 /* Special Testport Controls */
-#define BCHP_CLKGEN_TRIPLE_GENET_TOP_RGMII_INST_CKTAPSEL 0x004e0738 /* Triple genet top rgmii inst cktapsel */
-#define BCHP_CLKGEN_TRIPLE_GENET_TOP_RGMII_INST_CLOCK_DISABLE 0x004e073c /* Disable TRIPLE_GENET_TOP_RGMII_INST's clocks */
-#define BCHP_CLKGEN_TRIPLE_GENET_TOP_RGMII_INST_CLOCK_DISABLE_STATUS 0x004e0740 /* Clock Disable Status */
-#define BCHP_CLKGEN_TRIPLE_GENET_TOP_RGMII_INST_CLOCK_ENABLE 0x004e0744 /* Triple genet top rgmii inst clock enable */
-#define BCHP_CLKGEN_TRIPLE_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET0 0x004e0748 /* Triple genet top rgmii inst clock enable genet0 */
-#define BCHP_CLKGEN_TRIPLE_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET0_STATUS 0x004e074c /* Clock Enable Status */
-#define BCHP_CLKGEN_TRIPLE_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET1 0x004e0750 /* Triple genet top rgmii inst clock enable genet1 */
-#define BCHP_CLKGEN_TRIPLE_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET1_STATUS 0x004e0754 /* Clock Enable Status */
-#define BCHP_CLKGEN_TRIPLE_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET2 0x004e0758 /* Triple genet top rgmii inst clock enable genet2 */
-#define BCHP_CLKGEN_TRIPLE_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET2_STATUS 0x004e075c /* Clock Enable Status */
-#define BCHP_CLKGEN_TRIPLE_GENET_TOP_RGMII_INST_CLOCK_ENABLE_STATUS 0x004e0760 /* Clock Enable Status */
-#define BCHP_CLKGEN_TRIPLE_GENET_TOP_RGMII_INST_CLOCK_SELECT_GENET0 0x004e0764 /* Triple genet top rgmii inst clock select genet0 */
-#define BCHP_CLKGEN_TRIPLE_GENET_TOP_RGMII_INST_CLOCK_SELECT_GENET1 0x004e0768 /* Triple genet top rgmii inst clock select genet1 */
-#define BCHP_CLKGEN_TRIPLE_GENET_TOP_RGMII_INST_CLOCK_SELECT_GENET2 0x004e076c /* Triple genet top rgmii inst clock select genet2 */
-#define BCHP_CLKGEN_TRIPLE_GENET_TOP_RGMII_INST_OBSERVE_CLOCK 0x004e0770 /* Triple genet top rgmii inst observe clock */
-#define BCHP_CLKGEN_USB0_TOP_INST_CKTAPSEL 0x004e0774 /* Usb0 top inst cktapsel */
-#define BCHP_CLKGEN_USB0_TOP_INST_CLOCK_ENABLE 0x004e0778 /* Usb0 top inst clock enable */
-#define BCHP_CLKGEN_USB0_TOP_INST_CLOCK_ENABLE_AHB 0x004e077c /* Usb0 top inst clock enable ahb */
-#define BCHP_CLKGEN_USB0_TOP_INST_CLOCK_ENABLE_AHB_STATUS 0x004e0780 /* Clock Enable Status */
-#define BCHP_CLKGEN_USB0_TOP_INST_CLOCK_ENABLE_AXI 0x004e0784 /* Usb0 top inst clock enable axi */
-#define BCHP_CLKGEN_USB0_TOP_INST_CLOCK_ENABLE_AXI_STATUS 0x004e0788 /* Clock Enable Status */
-#define BCHP_CLKGEN_USB0_TOP_INST_CLOCK_ENABLE_STATUS 0x004e078c /* Clock Enable Status */
-#define BCHP_CLKGEN_USB0_TOP_INST_OBSERVE_CLOCK 0x004e0790 /* Usb0 top inst observe clock */
-#define BCHP_CLKGEN_USB1_TOP_INST_CKTAPSEL 0x004e0794 /* Usb1 top inst cktapsel */
-#define BCHP_CLKGEN_USB1_TOP_INST_CLOCK_ENABLE 0x004e0798 /* Usb1 top inst clock enable */
-#define BCHP_CLKGEN_USB1_TOP_INST_CLOCK_ENABLE_AHB 0x004e079c /* Usb1 top inst clock enable ahb */
-#define BCHP_CLKGEN_USB1_TOP_INST_CLOCK_ENABLE_AHB_STATUS 0x004e07a0 /* Clock Enable Status */
-#define BCHP_CLKGEN_USB1_TOP_INST_CLOCK_ENABLE_AXI 0x004e07a4 /* Usb1 top inst clock enable axi */
-#define BCHP_CLKGEN_USB1_TOP_INST_CLOCK_ENABLE_AXI_STATUS 0x004e07a8 /* Clock Enable Status */
-#define BCHP_CLKGEN_USB1_TOP_INST_CLOCK_ENABLE_STATUS 0x004e07ac /* Clock Enable Status */
-#define BCHP_CLKGEN_USB1_TOP_INST_OBSERVE_CLOCK 0x004e07b0 /* Usb1 top inst observe clock */
-#define BCHP_CLKGEN_V3D_TOP_INST_CKTAPSEL 0x004e07b4 /* V3d top inst cktapsel */
-#define BCHP_CLKGEN_V3D_TOP_INST_CLOCK_ENABLE 0x004e07b8 /* V3d top inst clock enable */
-#define BCHP_CLKGEN_V3D_TOP_INST_CLOCK_ENABLE_STATUS 0x004e07bc /* Clock Enable Status */
-#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CKTAPSEL 0x004e07c0 /* Vec aio top inst cktapsel */
-#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_DISABLE 0x004e07c4 /* Disable VEC_AIO_TOP_INST's clocks */
-#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_DISABLE_STATUS 0x004e07c8 /* Clock Disable Status */
-#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE 0x004e07cc /* Vec aio top inst clock enable */
-#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_AIO 0x004e07d0 /* Vec aio top inst clock enable aio */
-#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_AIO_STATUS 0x004e07d4 /* Clock Enable Status */
-#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_STATUS 0x004e07d8 /* Clock Enable Status */
-#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC 0x004e07dc /* Vec aio top inst clock enable vec */
-#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC_QDAC_INTF 0x004e07e0 /* Vec aio top inst clock enable vec qdac intf */
-#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC_QDAC_INTF_STATUS 0x004e07e4 /* Clock Enable Status */
-#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC_STATUS 0x004e07e8 /* Clock Enable Status */
-#define BCHP_CLKGEN_VEC_AIO_TOP_INST_OBSERVE_CLOCK 0x004e07ec /* Vec aio top inst observe clock */
-#define BCHP_CLKGEN_VICE2_0_INST_CKTAPSEL 0x004e07f0 /* Vice2 0 inst cktapsel */
-#define BCHP_CLKGEN_VICE2_0_INST_CLOCK_ENABLE 0x004e07f4 /* Vice2 0 inst clock enable */
-#define BCHP_CLKGEN_VICE2_0_INST_CLOCK_ENABLE_STATUS 0x004e07f8 /* Clock Enable Status */
-#define BCHP_CLKGEN_BSPI_CLOCK_SELECT 0x004e0820 /* spi clock control */
-#define BCHP_CLKGEN_USBPHY_REF_CLOCK_BYPASS 0x004e0824 /* bypass USBPHY reference clocks */
-#define BCHP_CLKGEN_EPHY_REF_CLOCK_BYPASS 0x004e0828 /* bypass EPHY reference clocks */
-#define BCHP_CLKGEN_HVD_PLL_CTRL_WRAPPER_CONTROL 0x004e082c /* HVD_PLL_CTRL_WRAPPER control */
-#define BCHP_CLKGEN_MOCA_PLL_CTRL_WRAPPER_CONTROL 0x004e0830 /* MOCA_PLL_CTRL_WRAPPER control */
-#define BCHP_CLKGEN_NETWORK_PLL_CTRL_WRAPPER_CONTROL 0x004e0834 /* NETWORK_PLL_CTRL_WRAPPER control */
-#define BCHP_CLKGEN_RAAGA_PLL_CTRL_WRAPPER_CONTROL 0x004e0838 /* RAAGA_PLL_CTRL_WRAPPER control */
-#define BCHP_CLKGEN_VCXO0_PLL_CTRL_WRAPPER_CONTROL 0x004e083c /* VCXO0_PLL_CTRL_WRAPPER control */
-#define BCHP_CLKGEN_VCXO1_PLL_CTRL_WRAPPER_CONTROL 0x004e0840 /* VCXO1_PLL_CTRL_WRAPPER control */
-#define BCHP_CLKGEN_V3D_PLL_CTRL_WRAPPER_CONTROL 0x004e0844 /* V3D_PLL_CTRL_WRAPPER control */
-#define BCHP_CLKGEN_LC_PLL_CTRL_WRAPPER_CONTROL 0x004e0848 /* LC_PLL_CTRL_WRAPPER control */
-#define BCHP_CLKGEN_SYS0_PLL_CTRL_WRAPPER_CONTROL 0x004e0850 /* SYS0_PLL_CTRL_WRAPPER control */
-#define BCHP_CLKGEN_XPT_PLL_CTRL_WRAPPER_CONTROL 0x004e0854 /* XPT_PLL_CTRL_WRAPPER control */
-#define BCHP_CLKGEN_CPU_PLL_CTRL_WRAPPER_CONTROL 0x004e0858 /* CPU_PLL_CTRL_WRAPPER control */
-#define BCHP_CLKGEN_SDS_PLL_CTRL_WRAPPER_CONTROL 0x004e085c /* SDS_PLL_CTRL_WRAPPER control */
-#define BCHP_CLKGEN_SC0_PLL_CTRL_WRAPPER_CONTROL 0x004e0860 /* SC0_PLL_CTRL_WRAPPER control */
-#define BCHP_CLKGEN_SC1_PLL_CTRL_WRAPPER_CONTROL 0x004e0864 /* SC1_PLL_CTRL_WRAPPER control */
-#define BCHP_CLKGEN_PLL_SC0_PLL_LDO_PWRON 0x004e0868 /* LDO Power on */
-#define BCHP_CLKGEN_PLL_SC1_PLL_LDO_PWRON 0x004e086c /* LDO Power on */
-
-/***************************************************************************
- *PLL_CPU_PLL_CHANNEL_CTRL_CH_0 - PLL CHANNEL control CH 0
- ***************************************************************************/
-/* CLKGEN :: PLL_CPU_PLL_CHANNEL_CTRL_CH_0 :: reserved0 [31:11] */
-#define BCHP_CLKGEN_PLL_CPU_PLL_CHANNEL_CTRL_CH_0_reserved0_MASK 0xfffff800
-#define BCHP_CLKGEN_PLL_CPU_PLL_CHANNEL_CTRL_CH_0_reserved0_SHIFT 11
-
-/* CLKGEN :: PLL_CPU_PLL_CHANNEL_CTRL_CH_0 :: POST_DIVIDER_HOLD_CH0 [10:10] */
-#define BCHP_CLKGEN_PLL_CPU_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_MASK 0x00000400
-#define BCHP_CLKGEN_PLL_CPU_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_SHIFT 10
-#define BCHP_CLKGEN_PLL_CPU_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_CPU_PLL_CHANNEL_CTRL_CH_0 :: PHASE_OFFSET_CH0 [09:09] */
-#define BCHP_CLKGEN_PLL_CPU_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_MASK 0x00000200
-#define BCHP_CLKGEN_PLL_CPU_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_SHIFT 9
-#define BCHP_CLKGEN_PLL_CPU_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_CPU_PLL_CHANNEL_CTRL_CH_0 :: MDIV_CH0 [08:01] */
-#define BCHP_CLKGEN_PLL_CPU_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_MASK 0x000001fe
-#define BCHP_CLKGEN_PLL_CPU_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_SHIFT 1
-#define BCHP_CLKGEN_PLL_CPU_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_DEFAULT 0x00000002
-
-/* CLKGEN :: PLL_CPU_PLL_CHANNEL_CTRL_CH_0 :: CLOCK_DIS_CH0 [00:00] */
-#define BCHP_CLKGEN_PLL_CPU_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_MASK 0x00000001
-#define BCHP_CLKGEN_PLL_CPU_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_SHIFT 0
-#define BCHP_CLKGEN_PLL_CPU_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_DEFAULT 0x00000000
-
-/***************************************************************************
- *PLL_CPU_PLL_CHANNEL_CTRL_CH_1 - PLL CHANNEL control CH 1
- ***************************************************************************/
-/* CLKGEN :: PLL_CPU_PLL_CHANNEL_CTRL_CH_1 :: reserved0 [31:11] */
-#define BCHP_CLKGEN_PLL_CPU_PLL_CHANNEL_CTRL_CH_1_reserved0_MASK 0xfffff800
-#define BCHP_CLKGEN_PLL_CPU_PLL_CHANNEL_CTRL_CH_1_reserved0_SHIFT 11
-
-/* CLKGEN :: PLL_CPU_PLL_CHANNEL_CTRL_CH_1 :: POST_DIVIDER_HOLD_CH1 [10:10] */
-#define BCHP_CLKGEN_PLL_CPU_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_MASK 0x00000400
-#define BCHP_CLKGEN_PLL_CPU_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_SHIFT 10
-#define BCHP_CLKGEN_PLL_CPU_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_CPU_PLL_CHANNEL_CTRL_CH_1 :: PHASE_OFFSET_CH1 [09:09] */
-#define BCHP_CLKGEN_PLL_CPU_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_MASK 0x00000200
-#define BCHP_CLKGEN_PLL_CPU_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_SHIFT 9
-#define BCHP_CLKGEN_PLL_CPU_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_CPU_PLL_CHANNEL_CTRL_CH_1 :: MDIV_CH1 [08:01] */
-#define BCHP_CLKGEN_PLL_CPU_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_MASK 0x000001fe
-#define BCHP_CLKGEN_PLL_CPU_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_SHIFT 1
-#define BCHP_CLKGEN_PLL_CPU_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_DEFAULT 0x00000064
-
-/* CLKGEN :: PLL_CPU_PLL_CHANNEL_CTRL_CH_1 :: CLOCK_DIS_CH1 [00:00] */
-#define BCHP_CLKGEN_PLL_CPU_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_MASK 0x00000001
-#define BCHP_CLKGEN_PLL_CPU_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_SHIFT 0
-#define BCHP_CLKGEN_PLL_CPU_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_DEFAULT 0x00000001
-
-/***************************************************************************
- *PLL_CPU_PLL_DIV - Pre multiplier
- ***************************************************************************/
-/* CLKGEN :: PLL_CPU_PLL_DIV :: reserved0 [31:14] */
-#define BCHP_CLKGEN_PLL_CPU_PLL_DIV_reserved0_MASK 0xffffc000
-#define BCHP_CLKGEN_PLL_CPU_PLL_DIV_reserved0_SHIFT 14
-
-/* CLKGEN :: PLL_CPU_PLL_DIV :: PDIV [13:10] */
-#define BCHP_CLKGEN_PLL_CPU_PLL_DIV_PDIV_MASK 0x00003c00
-#define BCHP_CLKGEN_PLL_CPU_PLL_DIV_PDIV_SHIFT 10
-#define BCHP_CLKGEN_PLL_CPU_PLL_DIV_PDIV_DEFAULT 0x00000003
-
-/* CLKGEN :: PLL_CPU_PLL_DIV :: NDIV_INT [09:00] */
-#define BCHP_CLKGEN_PLL_CPU_PLL_DIV_NDIV_INT_MASK 0x000003ff
-#define BCHP_CLKGEN_PLL_CPU_PLL_DIV_NDIV_INT_SHIFT 0
-#define BCHP_CLKGEN_PLL_CPU_PLL_DIV_NDIV_INT_DEFAULT 0x000000a7
-
-/***************************************************************************
- *PLL_CPU_PLL_FRAC - Fractional
- ***************************************************************************/
-/* CLKGEN :: PLL_CPU_PLL_FRAC :: reserved0 [31:20] */
-#define BCHP_CLKGEN_PLL_CPU_PLL_FRAC_reserved0_MASK 0xfff00000
-#define BCHP_CLKGEN_PLL_CPU_PLL_FRAC_reserved0_SHIFT 20
-
-/* CLKGEN :: PLL_CPU_PLL_FRAC :: FRAC_CONTROL [19:00] */
-#define BCHP_CLKGEN_PLL_CPU_PLL_FRAC_FRAC_CONTROL_MASK 0x000fffff
-#define BCHP_CLKGEN_PLL_CPU_PLL_FRAC_FRAC_CONTROL_SHIFT 0
-#define BCHP_CLKGEN_PLL_CPU_PLL_FRAC_FRAC_CONTROL_DEFAULT 0x00000000
-
-/***************************************************************************
- *PLL_CPU_PLL_GAIN - PLL GAIN
- ***************************************************************************/
-/* CLKGEN :: PLL_CPU_PLL_GAIN :: reserved0 [31:10] */
-#define BCHP_CLKGEN_PLL_CPU_PLL_GAIN_reserved0_MASK 0xfffffc00
-#define BCHP_CLKGEN_PLL_CPU_PLL_GAIN_reserved0_SHIFT 10
-
-/* CLKGEN :: PLL_CPU_PLL_GAIN :: LOOP_GAIN_PROPORTIONAL_IN_PHASE [09:06] */
-#define BCHP_CLKGEN_PLL_CPU_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_MASK 0x000003c0
-#define BCHP_CLKGEN_PLL_CPU_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_SHIFT 6
-#define BCHP_CLKGEN_PLL_CPU_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_DEFAULT 0x00000003
-
-/* CLKGEN :: PLL_CPU_PLL_GAIN :: LOOP_GAIN_IN_FREQ [05:03] */
-#define BCHP_CLKGEN_PLL_CPU_PLL_GAIN_LOOP_GAIN_IN_FREQ_MASK 0x00000038
-#define BCHP_CLKGEN_PLL_CPU_PLL_GAIN_LOOP_GAIN_IN_FREQ_SHIFT 3
-#define BCHP_CLKGEN_PLL_CPU_PLL_GAIN_LOOP_GAIN_IN_FREQ_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_CPU_PLL_GAIN :: LOOP_GAIN_INTEGRATOR_IN_PHASE [02:00] */
-#define BCHP_CLKGEN_PLL_CPU_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_MASK 0x00000007
-#define BCHP_CLKGEN_PLL_CPU_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_SHIFT 0
-#define BCHP_CLKGEN_PLL_CPU_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_DEFAULT 0x00000002
-
-/***************************************************************************
- *PLL_CPU_PLL_LDO_PWRON - LDO Power on
- ***************************************************************************/
-/* CLKGEN :: PLL_CPU_PLL_LDO_PWRON :: reserved0 [31:01] */
-#define BCHP_CLKGEN_PLL_CPU_PLL_LDO_PWRON_reserved0_MASK 0xfffffffe
-#define BCHP_CLKGEN_PLL_CPU_PLL_LDO_PWRON_reserved0_SHIFT 1
-
-/* CLKGEN :: PLL_CPU_PLL_LDO_PWRON :: LDO_PWRON_PLL [00:00] */
-#define BCHP_CLKGEN_PLL_CPU_PLL_LDO_PWRON_LDO_PWRON_PLL_MASK 0x00000001
-#define BCHP_CLKGEN_PLL_CPU_PLL_LDO_PWRON_LDO_PWRON_PLL_SHIFT 0
-#define BCHP_CLKGEN_PLL_CPU_PLL_LDO_PWRON_LDO_PWRON_PLL_DEFAULT 0x00000001
-
-/***************************************************************************
- *PLL_CPU_PLL_LOCK_STATUS - Lock Status
- ***************************************************************************/
-/* CLKGEN :: PLL_CPU_PLL_LOCK_STATUS :: reserved0 [31:02] */
-#define BCHP_CLKGEN_PLL_CPU_PLL_LOCK_STATUS_reserved0_MASK 0xfffffffc
-#define BCHP_CLKGEN_PLL_CPU_PLL_LOCK_STATUS_reserved0_SHIFT 2
-
-/* CLKGEN :: PLL_CPU_PLL_LOCK_STATUS :: LOCK_LOST [01:01] */
-#define BCHP_CLKGEN_PLL_CPU_PLL_LOCK_STATUS_LOCK_LOST_MASK 0x00000002
-#define BCHP_CLKGEN_PLL_CPU_PLL_LOCK_STATUS_LOCK_LOST_SHIFT 1
-
-/* CLKGEN :: PLL_CPU_PLL_LOCK_STATUS :: LOCK [00:00] */
-#define BCHP_CLKGEN_PLL_CPU_PLL_LOCK_STATUS_LOCK_MASK 0x00000001
-#define BCHP_CLKGEN_PLL_CPU_PLL_LOCK_STATUS_LOCK_SHIFT 0
-
-/***************************************************************************
- *PLL_CPU_PLL_MISC - Mscellaneous control bus.
- ***************************************************************************/
-/* CLKGEN :: PLL_CPU_PLL_MISC :: VCO_RANGE [31:30] */
-#define BCHP_CLKGEN_PLL_CPU_PLL_MISC_VCO_RANGE_MASK 0xc0000000
-#define BCHP_CLKGEN_PLL_CPU_PLL_MISC_VCO_RANGE_SHIFT 30
-#define BCHP_CLKGEN_PLL_CPU_PLL_MISC_VCO_RANGE_DEFAULT 0x00000002
-
-/* CLKGEN :: PLL_CPU_PLL_MISC :: VCO_FB_DIV2 [29:29] */
-#define BCHP_CLKGEN_PLL_CPU_PLL_MISC_VCO_FB_DIV2_MASK 0x20000000
-#define BCHP_CLKGEN_PLL_CPU_PLL_MISC_VCO_FB_DIV2_SHIFT 29
-#define BCHP_CLKGEN_PLL_CPU_PLL_MISC_VCO_FB_DIV2_DEFAULT 0x00000001
-
-/* CLKGEN :: PLL_CPU_PLL_MISC :: STAT_UPDATE [28:28] */
-#define BCHP_CLKGEN_PLL_CPU_PLL_MISC_STAT_UPDATE_MASK 0x10000000
-#define BCHP_CLKGEN_PLL_CPU_PLL_MISC_STAT_UPDATE_SHIFT 28
-#define BCHP_CLKGEN_PLL_CPU_PLL_MISC_STAT_UPDATE_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_CPU_PLL_MISC :: STAT_SELECT [27:25] */
-#define BCHP_CLKGEN_PLL_CPU_PLL_MISC_STAT_SELECT_MASK 0x0e000000
-#define BCHP_CLKGEN_PLL_CPU_PLL_MISC_STAT_SELECT_SHIFT 25
-#define BCHP_CLKGEN_PLL_CPU_PLL_MISC_STAT_SELECT_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_CPU_PLL_MISC :: STAT_RESET [24:24] */
-#define BCHP_CLKGEN_PLL_CPU_PLL_MISC_STAT_RESET_MASK 0x01000000
-#define BCHP_CLKGEN_PLL_CPU_PLL_MISC_STAT_RESET_SHIFT 24
-#define BCHP_CLKGEN_PLL_CPU_PLL_MISC_STAT_RESET_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_CPU_PLL_MISC :: STAT_MODE [23:22] */
-#define BCHP_CLKGEN_PLL_CPU_PLL_MISC_STAT_MODE_MASK 0x00c00000
-#define BCHP_CLKGEN_PLL_CPU_PLL_MISC_STAT_MODE_SHIFT 22
-#define BCHP_CLKGEN_PLL_CPU_PLL_MISC_STAT_MODE_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_CPU_PLL_MISC :: PWM_RATE [21:20] */
-#define BCHP_CLKGEN_PLL_CPU_PLL_MISC_PWM_RATE_MASK 0x00300000
-#define BCHP_CLKGEN_PLL_CPU_PLL_MISC_PWM_RATE_SHIFT 20
-#define BCHP_CLKGEN_PLL_CPU_PLL_MISC_PWM_RATE_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_CPU_PLL_MISC :: POST_CTRL_RESETB [19:18] */
-#define BCHP_CLKGEN_PLL_CPU_PLL_MISC_POST_CTRL_RESETB_MASK 0x000c0000
-#define BCHP_CLKGEN_PLL_CPU_PLL_MISC_POST_CTRL_RESETB_SHIFT 18
-#define BCHP_CLKGEN_PLL_CPU_PLL_MISC_POST_CTRL_RESETB_DEFAULT 0x00000003
-
-/* CLKGEN :: PLL_CPU_PLL_MISC :: PLLRESERVED2 [17:16] */
-#define BCHP_CLKGEN_PLL_CPU_PLL_MISC_PLLRESERVED2_MASK 0x00030000
-#define BCHP_CLKGEN_PLL_CPU_PLL_MISC_PLLRESERVED2_SHIFT 16
-#define BCHP_CLKGEN_PLL_CPU_PLL_MISC_PLLRESERVED2_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_CPU_PLL_MISC :: PLLRESERVED1 [15:15] */
-#define BCHP_CLKGEN_PLL_CPU_PLL_MISC_PLLRESERVED1_MASK 0x00008000
-#define BCHP_CLKGEN_PLL_CPU_PLL_MISC_PLLRESERVED1_SHIFT 15
-#define BCHP_CLKGEN_PLL_CPU_PLL_MISC_PLLRESERVED1_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_CPU_PLL_MISC :: NDIV_RELOCK [14:14] */
-#define BCHP_CLKGEN_PLL_CPU_PLL_MISC_NDIV_RELOCK_MASK 0x00004000
-#define BCHP_CLKGEN_PLL_CPU_PLL_MISC_NDIV_RELOCK_SHIFT 14
-#define BCHP_CLKGEN_PLL_CPU_PLL_MISC_NDIV_RELOCK_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_CPU_PLL_MISC :: FAST_LOCK [13:13] */
-#define BCHP_CLKGEN_PLL_CPU_PLL_MISC_FAST_LOCK_MASK 0x00002000
-#define BCHP_CLKGEN_PLL_CPU_PLL_MISC_FAST_LOCK_SHIFT 13
-#define BCHP_CLKGEN_PLL_CPU_PLL_MISC_FAST_LOCK_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_CPU_PLL_MISC :: DCO_CTRL_BYPASS_ENABLE [12:12] */
-#define BCHP_CLKGEN_PLL_CPU_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_MASK 0x00001000
-#define BCHP_CLKGEN_PLL_CPU_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_SHIFT 12
-#define BCHP_CLKGEN_PLL_CPU_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_CPU_PLL_MISC :: DCO_CTRL_BYPASS [11:00] */
-#define BCHP_CLKGEN_PLL_CPU_PLL_MISC_DCO_CTRL_BYPASS_MASK 0x00000fff
-#define BCHP_CLKGEN_PLL_CPU_PLL_MISC_DCO_CTRL_BYPASS_SHIFT 0
-#define BCHP_CLKGEN_PLL_CPU_PLL_MISC_DCO_CTRL_BYPASS_DEFAULT 0x00000000
-
-/***************************************************************************
- *PLL_CPU_PLL_MISC2 - Mscellaneous control bus continued.
- ***************************************************************************/
-/* CLKGEN :: PLL_CPU_PLL_MISC2 :: PLLRESERVED0 [31:02] */
-#define BCHP_CLKGEN_PLL_CPU_PLL_MISC2_PLLRESERVED0_MASK 0xfffffffc
-#define BCHP_CLKGEN_PLL_CPU_PLL_MISC2_PLLRESERVED0_SHIFT 2
-#define BCHP_CLKGEN_PLL_CPU_PLL_MISC2_PLLRESERVED0_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_CPU_PLL_MISC2 :: LDO [01:00] */
-#define BCHP_CLKGEN_PLL_CPU_PLL_MISC2_LDO_MASK 0x00000003
-#define BCHP_CLKGEN_PLL_CPU_PLL_MISC2_LDO_SHIFT 0
-#define BCHP_CLKGEN_PLL_CPU_PLL_MISC2_LDO_DEFAULT 0x00000001
-
-/***************************************************************************
- *PLL_CPU_PLL_PWRON - Poweron
- ***************************************************************************/
-/* CLKGEN :: PLL_CPU_PLL_PWRON :: reserved0 [31:01] */
-#define BCHP_CLKGEN_PLL_CPU_PLL_PWRON_reserved0_MASK 0xfffffffe
-#define BCHP_CLKGEN_PLL_CPU_PLL_PWRON_reserved0_SHIFT 1
-
-/* CLKGEN :: PLL_CPU_PLL_PWRON :: PWRON_PLL [00:00] */
-#define BCHP_CLKGEN_PLL_CPU_PLL_PWRON_PWRON_PLL_MASK 0x00000001
-#define BCHP_CLKGEN_PLL_CPU_PLL_PWRON_PWRON_PLL_SHIFT 0
-#define BCHP_CLKGEN_PLL_CPU_PLL_PWRON_PWRON_PLL_DEFAULT 0x00000001
-
-/***************************************************************************
- *PLL_CPU_PLL_RESET - Resets
- ***************************************************************************/
-/* CLKGEN :: PLL_CPU_PLL_RESET :: reserved0 [31:02] */
-#define BCHP_CLKGEN_PLL_CPU_PLL_RESET_reserved0_MASK 0xfffffffc
-#define BCHP_CLKGEN_PLL_CPU_PLL_RESET_reserved0_SHIFT 2
-
-/* CLKGEN :: PLL_CPU_PLL_RESET :: RESETD [01:01] */
-#define BCHP_CLKGEN_PLL_CPU_PLL_RESET_RESETD_MASK 0x00000002
-#define BCHP_CLKGEN_PLL_CPU_PLL_RESET_RESETD_SHIFT 1
-#define BCHP_CLKGEN_PLL_CPU_PLL_RESET_RESETD_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_CPU_PLL_RESET :: RESETA [00:00] */
-#define BCHP_CLKGEN_PLL_CPU_PLL_RESET_RESETA_MASK 0x00000001
-#define BCHP_CLKGEN_PLL_CPU_PLL_RESET_RESETA_SHIFT 0
-#define BCHP_CLKGEN_PLL_CPU_PLL_RESET_RESETA_DEFAULT 0x00000000
-
-/***************************************************************************
- *PLL_CPU_PLL_SSC_MODE_CONTROL_HIGH - Higher bits of Spread Spectrum mode control
- ***************************************************************************/
-/* CLKGEN :: PLL_CPU_PLL_SSC_MODE_CONTROL_HIGH :: reserved0 [31:16] */
-#define BCHP_CLKGEN_PLL_CPU_PLL_SSC_MODE_CONTROL_HIGH_reserved0_MASK 0xffff0000
-#define BCHP_CLKGEN_PLL_CPU_PLL_SSC_MODE_CONTROL_HIGH_reserved0_SHIFT 16
-
-/* CLKGEN :: PLL_CPU_PLL_SSC_MODE_CONTROL_HIGH :: SSC_STEP [15:00] */
-#define BCHP_CLKGEN_PLL_CPU_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_MASK 0x0000ffff
-#define BCHP_CLKGEN_PLL_CPU_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_SHIFT 0
-#define BCHP_CLKGEN_PLL_CPU_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *PLL_CPU_PLL_SSC_MODE_CONTROL_LOW - Lower bits of Spread Spectrum mode control
- ***************************************************************************/
-/* CLKGEN :: PLL_CPU_PLL_SSC_MODE_CONTROL_LOW :: reserved0 [31:23] */
-#define BCHP_CLKGEN_PLL_CPU_PLL_SSC_MODE_CONTROL_LOW_reserved0_MASK 0xff800000
-#define BCHP_CLKGEN_PLL_CPU_PLL_SSC_MODE_CONTROL_LOW_reserved0_SHIFT 23
-
-/* CLKGEN :: PLL_CPU_PLL_SSC_MODE_CONTROL_LOW :: SSC_MODE [22:22] */
-#define BCHP_CLKGEN_PLL_CPU_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_MASK 0x00400000
-#define BCHP_CLKGEN_PLL_CPU_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_SHIFT 22
-#define BCHP_CLKGEN_PLL_CPU_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_CPU_PLL_SSC_MODE_CONTROL_LOW :: SSC_LIMIT [21:00] */
-#define BCHP_CLKGEN_PLL_CPU_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_MASK 0x003fffff
-#define BCHP_CLKGEN_PLL_CPU_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_SHIFT 0
-#define BCHP_CLKGEN_PLL_CPU_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_DEFAULT 0x00000000
-
-/***************************************************************************
- *PLL_CPU_PLL_STATUS - Status
- ***************************************************************************/
-/* CLKGEN :: PLL_CPU_PLL_STATUS :: reserved0 [31:12] */
-#define BCHP_CLKGEN_PLL_CPU_PLL_STATUS_reserved0_MASK 0xfffff000
-#define BCHP_CLKGEN_PLL_CPU_PLL_STATUS_reserved0_SHIFT 12
-
-/* CLKGEN :: PLL_CPU_PLL_STATUS :: TEST_STATUS [11:00] */
-#define BCHP_CLKGEN_PLL_CPU_PLL_STATUS_TEST_STATUS_MASK 0x00000fff
-#define BCHP_CLKGEN_PLL_CPU_PLL_STATUS_TEST_STATUS_SHIFT 0
-
-/***************************************************************************
- *PLL_HVD_PLL_CHANNEL_CTRL_CH_0 - PLL CHANNEL control CH 0
- ***************************************************************************/
-/* CLKGEN :: PLL_HVD_PLL_CHANNEL_CTRL_CH_0 :: reserved0 [31:11] */
-#define BCHP_CLKGEN_PLL_HVD_PLL_CHANNEL_CTRL_CH_0_reserved0_MASK 0xfffff800
-#define BCHP_CLKGEN_PLL_HVD_PLL_CHANNEL_CTRL_CH_0_reserved0_SHIFT 11
-
-/* CLKGEN :: PLL_HVD_PLL_CHANNEL_CTRL_CH_0 :: POST_DIVIDER_HOLD_CH0 [10:10] */
-#define BCHP_CLKGEN_PLL_HVD_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_MASK 0x00000400
-#define BCHP_CLKGEN_PLL_HVD_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_SHIFT 10
-#define BCHP_CLKGEN_PLL_HVD_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_HVD_PLL_CHANNEL_CTRL_CH_0 :: PHASE_OFFSET_CH0 [09:09] */
-#define BCHP_CLKGEN_PLL_HVD_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_MASK 0x00000200
-#define BCHP_CLKGEN_PLL_HVD_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_SHIFT 9
-#define BCHP_CLKGEN_PLL_HVD_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_HVD_PLL_CHANNEL_CTRL_CH_0 :: MDIV_CH0 [08:01] */
-#define BCHP_CLKGEN_PLL_HVD_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_MASK 0x000001fe
-#define BCHP_CLKGEN_PLL_HVD_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_SHIFT 1
-#define BCHP_CLKGEN_PLL_HVD_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_DEFAULT 0x00000008
-
-/* CLKGEN :: PLL_HVD_PLL_CHANNEL_CTRL_CH_0 :: CLOCK_DIS_CH0 [00:00] */
-#define BCHP_CLKGEN_PLL_HVD_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_MASK 0x00000001
-#define BCHP_CLKGEN_PLL_HVD_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_SHIFT 0
-#define BCHP_CLKGEN_PLL_HVD_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_DEFAULT 0x00000000
-
-/***************************************************************************
- *PLL_HVD_PLL_CHANNEL_CTRL_CH_1 - PLL CHANNEL control CH 1
- ***************************************************************************/
-/* CLKGEN :: PLL_HVD_PLL_CHANNEL_CTRL_CH_1 :: reserved0 [31:11] */
-#define BCHP_CLKGEN_PLL_HVD_PLL_CHANNEL_CTRL_CH_1_reserved0_MASK 0xfffff800
-#define BCHP_CLKGEN_PLL_HVD_PLL_CHANNEL_CTRL_CH_1_reserved0_SHIFT 11
-
-/* CLKGEN :: PLL_HVD_PLL_CHANNEL_CTRL_CH_1 :: POST_DIVIDER_HOLD_CH1 [10:10] */
-#define BCHP_CLKGEN_PLL_HVD_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_MASK 0x00000400
-#define BCHP_CLKGEN_PLL_HVD_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_SHIFT 10
-#define BCHP_CLKGEN_PLL_HVD_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_HVD_PLL_CHANNEL_CTRL_CH_1 :: PHASE_OFFSET_CH1 [09:09] */
-#define BCHP_CLKGEN_PLL_HVD_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_MASK 0x00000200
-#define BCHP_CLKGEN_PLL_HVD_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_SHIFT 9
-#define BCHP_CLKGEN_PLL_HVD_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_HVD_PLL_CHANNEL_CTRL_CH_1 :: MDIV_CH1 [08:01] */
-#define BCHP_CLKGEN_PLL_HVD_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_MASK 0x000001fe
-#define BCHP_CLKGEN_PLL_HVD_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_SHIFT 1
-#define BCHP_CLKGEN_PLL_HVD_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_DEFAULT 0x00000006
-
-/* CLKGEN :: PLL_HVD_PLL_CHANNEL_CTRL_CH_1 :: CLOCK_DIS_CH1 [00:00] */
-#define BCHP_CLKGEN_PLL_HVD_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_MASK 0x00000001
-#define BCHP_CLKGEN_PLL_HVD_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_SHIFT 0
-#define BCHP_CLKGEN_PLL_HVD_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_DEFAULT 0x00000000
-
-/***************************************************************************
- *PLL_HVD_PLL_CHANNEL_CTRL_CH_3 - PLL CHANNEL control CH 3
- ***************************************************************************/
-/* CLKGEN :: PLL_HVD_PLL_CHANNEL_CTRL_CH_3 :: reserved0 [31:11] */
-#define BCHP_CLKGEN_PLL_HVD_PLL_CHANNEL_CTRL_CH_3_reserved0_MASK 0xfffff800
-#define BCHP_CLKGEN_PLL_HVD_PLL_CHANNEL_CTRL_CH_3_reserved0_SHIFT 11
-
-/* CLKGEN :: PLL_HVD_PLL_CHANNEL_CTRL_CH_3 :: POST_DIVIDER_HOLD_CH3 [10:10] */
-#define BCHP_CLKGEN_PLL_HVD_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_HOLD_CH3_MASK 0x00000400
-#define BCHP_CLKGEN_PLL_HVD_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_HOLD_CH3_SHIFT 10
-#define BCHP_CLKGEN_PLL_HVD_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_HOLD_CH3_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_HVD_PLL_CHANNEL_CTRL_CH_3 :: PHASE_OFFSET_CH3 [09:09] */
-#define BCHP_CLKGEN_PLL_HVD_PLL_CHANNEL_CTRL_CH_3_PHASE_OFFSET_CH3_MASK 0x00000200
-#define BCHP_CLKGEN_PLL_HVD_PLL_CHANNEL_CTRL_CH_3_PHASE_OFFSET_CH3_SHIFT 9
-#define BCHP_CLKGEN_PLL_HVD_PLL_CHANNEL_CTRL_CH_3_PHASE_OFFSET_CH3_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_HVD_PLL_CHANNEL_CTRL_CH_3 :: MDIV_CH3 [08:01] */
-#define BCHP_CLKGEN_PLL_HVD_PLL_CHANNEL_CTRL_CH_3_MDIV_CH3_MASK 0x000001fe
-#define BCHP_CLKGEN_PLL_HVD_PLL_CHANNEL_CTRL_CH_3_MDIV_CH3_SHIFT 1
-#define BCHP_CLKGEN_PLL_HVD_PLL_CHANNEL_CTRL_CH_3_MDIV_CH3_DEFAULT 0x0000000f
-
-/* CLKGEN :: PLL_HVD_PLL_CHANNEL_CTRL_CH_3 :: CLOCK_DIS_CH3 [00:00] */
-#define BCHP_CLKGEN_PLL_HVD_PLL_CHANNEL_CTRL_CH_3_CLOCK_DIS_CH3_MASK 0x00000001
-#define BCHP_CLKGEN_PLL_HVD_PLL_CHANNEL_CTRL_CH_3_CLOCK_DIS_CH3_SHIFT 0
-#define BCHP_CLKGEN_PLL_HVD_PLL_CHANNEL_CTRL_CH_3_CLOCK_DIS_CH3_DEFAULT 0x00000000
-
-/***************************************************************************
- *PLL_HVD_PLL_CHANNEL_CTRL_CH_4 - PLL CHANNEL control CH 4
- ***************************************************************************/
-/* CLKGEN :: PLL_HVD_PLL_CHANNEL_CTRL_CH_4 :: reserved0 [31:11] */
-#define BCHP_CLKGEN_PLL_HVD_PLL_CHANNEL_CTRL_CH_4_reserved0_MASK 0xfffff800
-#define BCHP_CLKGEN_PLL_HVD_PLL_CHANNEL_CTRL_CH_4_reserved0_SHIFT 11
-
-/* CLKGEN :: PLL_HVD_PLL_CHANNEL_CTRL_CH_4 :: POST_DIVIDER_HOLD_CH4 [10:10] */
-#define BCHP_CLKGEN_PLL_HVD_PLL_CHANNEL_CTRL_CH_4_POST_DIVIDER_HOLD_CH4_MASK 0x00000400
-#define BCHP_CLKGEN_PLL_HVD_PLL_CHANNEL_CTRL_CH_4_POST_DIVIDER_HOLD_CH4_SHIFT 10
-#define BCHP_CLKGEN_PLL_HVD_PLL_CHANNEL_CTRL_CH_4_POST_DIVIDER_HOLD_CH4_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_HVD_PLL_CHANNEL_CTRL_CH_4 :: PHASE_OFFSET_CH4 [09:09] */
-#define BCHP_CLKGEN_PLL_HVD_PLL_CHANNEL_CTRL_CH_4_PHASE_OFFSET_CH4_MASK 0x00000200
-#define BCHP_CLKGEN_PLL_HVD_PLL_CHANNEL_CTRL_CH_4_PHASE_OFFSET_CH4_SHIFT 9
-#define BCHP_CLKGEN_PLL_HVD_PLL_CHANNEL_CTRL_CH_4_PHASE_OFFSET_CH4_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_HVD_PLL_CHANNEL_CTRL_CH_4 :: MDIV_CH4 [08:01] */
-#define BCHP_CLKGEN_PLL_HVD_PLL_CHANNEL_CTRL_CH_4_MDIV_CH4_MASK 0x000001fe
-#define BCHP_CLKGEN_PLL_HVD_PLL_CHANNEL_CTRL_CH_4_MDIV_CH4_SHIFT 1
-#define BCHP_CLKGEN_PLL_HVD_PLL_CHANNEL_CTRL_CH_4_MDIV_CH4_DEFAULT 0x00000064
-
-/* CLKGEN :: PLL_HVD_PLL_CHANNEL_CTRL_CH_4 :: CLOCK_DIS_CH4 [00:00] */
-#define BCHP_CLKGEN_PLL_HVD_PLL_CHANNEL_CTRL_CH_4_CLOCK_DIS_CH4_MASK 0x00000001
-#define BCHP_CLKGEN_PLL_HVD_PLL_CHANNEL_CTRL_CH_4_CLOCK_DIS_CH4_SHIFT 0
-#define BCHP_CLKGEN_PLL_HVD_PLL_CHANNEL_CTRL_CH_4_CLOCK_DIS_CH4_DEFAULT 0x00000001
-
-/***************************************************************************
- *PLL_HVD_PLL_DIV - Pre multiplier
- ***************************************************************************/
-/* CLKGEN :: PLL_HVD_PLL_DIV :: reserved0 [31:14] */
-#define BCHP_CLKGEN_PLL_HVD_PLL_DIV_reserved0_MASK 0xffffc000
-#define BCHP_CLKGEN_PLL_HVD_PLL_DIV_reserved0_SHIFT 14
-
-/* CLKGEN :: PLL_HVD_PLL_DIV :: PDIV [13:10] */
-#define BCHP_CLKGEN_PLL_HVD_PLL_DIV_PDIV_MASK 0x00003c00
-#define BCHP_CLKGEN_PLL_HVD_PLL_DIV_PDIV_SHIFT 10
-#define BCHP_CLKGEN_PLL_HVD_PLL_DIV_PDIV_DEFAULT 0x00000003
-
-/* CLKGEN :: PLL_HVD_PLL_DIV :: NDIV_INT [09:00] */
-#define BCHP_CLKGEN_PLL_HVD_PLL_DIV_NDIV_INT_MASK 0x000003ff
-#define BCHP_CLKGEN_PLL_HVD_PLL_DIV_NDIV_INT_SHIFT 0
-#define BCHP_CLKGEN_PLL_HVD_PLL_DIV_NDIV_INT_DEFAULT 0x000000c8
-
-/***************************************************************************
- *PLL_HVD_PLL_FRAC - Fractional
- ***************************************************************************/
-/* CLKGEN :: PLL_HVD_PLL_FRAC :: reserved0 [31:20] */
-#define BCHP_CLKGEN_PLL_HVD_PLL_FRAC_reserved0_MASK 0xfff00000
-#define BCHP_CLKGEN_PLL_HVD_PLL_FRAC_reserved0_SHIFT 20
-
-/* CLKGEN :: PLL_HVD_PLL_FRAC :: FRAC_CONTROL [19:00] */
-#define BCHP_CLKGEN_PLL_HVD_PLL_FRAC_FRAC_CONTROL_MASK 0x000fffff
-#define BCHP_CLKGEN_PLL_HVD_PLL_FRAC_FRAC_CONTROL_SHIFT 0
-#define BCHP_CLKGEN_PLL_HVD_PLL_FRAC_FRAC_CONTROL_DEFAULT 0x00000000
-
-/***************************************************************************
- *PLL_HVD_PLL_GAIN - PLL GAIN
- ***************************************************************************/
-/* CLKGEN :: PLL_HVD_PLL_GAIN :: reserved0 [31:10] */
-#define BCHP_CLKGEN_PLL_HVD_PLL_GAIN_reserved0_MASK 0xfffffc00
-#define BCHP_CLKGEN_PLL_HVD_PLL_GAIN_reserved0_SHIFT 10
-
-/* CLKGEN :: PLL_HVD_PLL_GAIN :: LOOP_GAIN_PROPORTIONAL_IN_PHASE [09:06] */
-#define BCHP_CLKGEN_PLL_HVD_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_MASK 0x000003c0
-#define BCHP_CLKGEN_PLL_HVD_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_SHIFT 6
-#define BCHP_CLKGEN_PLL_HVD_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_DEFAULT 0x00000003
-
-/* CLKGEN :: PLL_HVD_PLL_GAIN :: LOOP_GAIN_IN_FREQ [05:03] */
-#define BCHP_CLKGEN_PLL_HVD_PLL_GAIN_LOOP_GAIN_IN_FREQ_MASK 0x00000038
-#define BCHP_CLKGEN_PLL_HVD_PLL_GAIN_LOOP_GAIN_IN_FREQ_SHIFT 3
-#define BCHP_CLKGEN_PLL_HVD_PLL_GAIN_LOOP_GAIN_IN_FREQ_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_HVD_PLL_GAIN :: LOOP_GAIN_INTEGRATOR_IN_PHASE [02:00] */
-#define BCHP_CLKGEN_PLL_HVD_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_MASK 0x00000007
-#define BCHP_CLKGEN_PLL_HVD_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_SHIFT 0
-#define BCHP_CLKGEN_PLL_HVD_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_DEFAULT 0x00000002
-
-/***************************************************************************
- *PLL_HVD_PLL_LDO_PWRON - LDO Power on
- ***************************************************************************/
-/* CLKGEN :: PLL_HVD_PLL_LDO_PWRON :: reserved0 [31:01] */
-#define BCHP_CLKGEN_PLL_HVD_PLL_LDO_PWRON_reserved0_MASK 0xfffffffe
-#define BCHP_CLKGEN_PLL_HVD_PLL_LDO_PWRON_reserved0_SHIFT 1
-
-/* CLKGEN :: PLL_HVD_PLL_LDO_PWRON :: LDO_PWRON_PLL [00:00] */
-#define BCHP_CLKGEN_PLL_HVD_PLL_LDO_PWRON_LDO_PWRON_PLL_MASK 0x00000001
-#define BCHP_CLKGEN_PLL_HVD_PLL_LDO_PWRON_LDO_PWRON_PLL_SHIFT 0
-#define BCHP_CLKGEN_PLL_HVD_PLL_LDO_PWRON_LDO_PWRON_PLL_DEFAULT 0x00000001
-
-/***************************************************************************
- *PLL_HVD_PLL_LOCK_STATUS - Lock Status
- ***************************************************************************/
-/* CLKGEN :: PLL_HVD_PLL_LOCK_STATUS :: reserved0 [31:02] */
-#define BCHP_CLKGEN_PLL_HVD_PLL_LOCK_STATUS_reserved0_MASK 0xfffffffc
-#define BCHP_CLKGEN_PLL_HVD_PLL_LOCK_STATUS_reserved0_SHIFT 2
-
-/* CLKGEN :: PLL_HVD_PLL_LOCK_STATUS :: LOCK_LOST [01:01] */
-#define BCHP_CLKGEN_PLL_HVD_PLL_LOCK_STATUS_LOCK_LOST_MASK 0x00000002
-#define BCHP_CLKGEN_PLL_HVD_PLL_LOCK_STATUS_LOCK_LOST_SHIFT 1
-
-/* CLKGEN :: PLL_HVD_PLL_LOCK_STATUS :: LOCK [00:00] */
-#define BCHP_CLKGEN_PLL_HVD_PLL_LOCK_STATUS_LOCK_MASK 0x00000001
-#define BCHP_CLKGEN_PLL_HVD_PLL_LOCK_STATUS_LOCK_SHIFT 0
-
-/***************************************************************************
- *PLL_HVD_PLL_MISC - Mscellaneous control bus.
- ***************************************************************************/
-/* CLKGEN :: PLL_HVD_PLL_MISC :: VCO_RANGE [31:30] */
-#define BCHP_CLKGEN_PLL_HVD_PLL_MISC_VCO_RANGE_MASK 0xc0000000
-#define BCHP_CLKGEN_PLL_HVD_PLL_MISC_VCO_RANGE_SHIFT 30
-#define BCHP_CLKGEN_PLL_HVD_PLL_MISC_VCO_RANGE_DEFAULT 0x00000002
-
-/* CLKGEN :: PLL_HVD_PLL_MISC :: VCO_FB_DIV2 [29:29] */
-#define BCHP_CLKGEN_PLL_HVD_PLL_MISC_VCO_FB_DIV2_MASK 0x20000000
-#define BCHP_CLKGEN_PLL_HVD_PLL_MISC_VCO_FB_DIV2_SHIFT 29
-#define BCHP_CLKGEN_PLL_HVD_PLL_MISC_VCO_FB_DIV2_DEFAULT 0x00000001
-
-/* CLKGEN :: PLL_HVD_PLL_MISC :: STAT_UPDATE [28:28] */
-#define BCHP_CLKGEN_PLL_HVD_PLL_MISC_STAT_UPDATE_MASK 0x10000000
-#define BCHP_CLKGEN_PLL_HVD_PLL_MISC_STAT_UPDATE_SHIFT 28
-#define BCHP_CLKGEN_PLL_HVD_PLL_MISC_STAT_UPDATE_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_HVD_PLL_MISC :: STAT_SELECT [27:25] */
-#define BCHP_CLKGEN_PLL_HVD_PLL_MISC_STAT_SELECT_MASK 0x0e000000
-#define BCHP_CLKGEN_PLL_HVD_PLL_MISC_STAT_SELECT_SHIFT 25
-#define BCHP_CLKGEN_PLL_HVD_PLL_MISC_STAT_SELECT_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_HVD_PLL_MISC :: STAT_RESET [24:24] */
-#define BCHP_CLKGEN_PLL_HVD_PLL_MISC_STAT_RESET_MASK 0x01000000
-#define BCHP_CLKGEN_PLL_HVD_PLL_MISC_STAT_RESET_SHIFT 24
-#define BCHP_CLKGEN_PLL_HVD_PLL_MISC_STAT_RESET_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_HVD_PLL_MISC :: STAT_MODE [23:22] */
-#define BCHP_CLKGEN_PLL_HVD_PLL_MISC_STAT_MODE_MASK 0x00c00000
-#define BCHP_CLKGEN_PLL_HVD_PLL_MISC_STAT_MODE_SHIFT 22
-#define BCHP_CLKGEN_PLL_HVD_PLL_MISC_STAT_MODE_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_HVD_PLL_MISC :: PWM_RATE [21:20] */
-#define BCHP_CLKGEN_PLL_HVD_PLL_MISC_PWM_RATE_MASK 0x00300000
-#define BCHP_CLKGEN_PLL_HVD_PLL_MISC_PWM_RATE_SHIFT 20
-#define BCHP_CLKGEN_PLL_HVD_PLL_MISC_PWM_RATE_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_HVD_PLL_MISC :: POST_CTRL_RESETB [19:18] */
-#define BCHP_CLKGEN_PLL_HVD_PLL_MISC_POST_CTRL_RESETB_MASK 0x000c0000
-#define BCHP_CLKGEN_PLL_HVD_PLL_MISC_POST_CTRL_RESETB_SHIFT 18
-#define BCHP_CLKGEN_PLL_HVD_PLL_MISC_POST_CTRL_RESETB_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_HVD_PLL_MISC :: PLLRESERVED2 [17:16] */
-#define BCHP_CLKGEN_PLL_HVD_PLL_MISC_PLLRESERVED2_MASK 0x00030000
-#define BCHP_CLKGEN_PLL_HVD_PLL_MISC_PLLRESERVED2_SHIFT 16
-#define BCHP_CLKGEN_PLL_HVD_PLL_MISC_PLLRESERVED2_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_HVD_PLL_MISC :: PLLRESERVED1 [15:15] */
-#define BCHP_CLKGEN_PLL_HVD_PLL_MISC_PLLRESERVED1_MASK 0x00008000
-#define BCHP_CLKGEN_PLL_HVD_PLL_MISC_PLLRESERVED1_SHIFT 15
-#define BCHP_CLKGEN_PLL_HVD_PLL_MISC_PLLRESERVED1_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_HVD_PLL_MISC :: NDIV_RELOCK [14:14] */
-#define BCHP_CLKGEN_PLL_HVD_PLL_MISC_NDIV_RELOCK_MASK 0x00004000
-#define BCHP_CLKGEN_PLL_HVD_PLL_MISC_NDIV_RELOCK_SHIFT 14
-#define BCHP_CLKGEN_PLL_HVD_PLL_MISC_NDIV_RELOCK_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_HVD_PLL_MISC :: FAST_LOCK [13:13] */
-#define BCHP_CLKGEN_PLL_HVD_PLL_MISC_FAST_LOCK_MASK 0x00002000
-#define BCHP_CLKGEN_PLL_HVD_PLL_MISC_FAST_LOCK_SHIFT 13
-#define BCHP_CLKGEN_PLL_HVD_PLL_MISC_FAST_LOCK_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_HVD_PLL_MISC :: DCO_CTRL_BYPASS_ENABLE [12:12] */
-#define BCHP_CLKGEN_PLL_HVD_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_MASK 0x00001000
-#define BCHP_CLKGEN_PLL_HVD_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_SHIFT 12
-#define BCHP_CLKGEN_PLL_HVD_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_HVD_PLL_MISC :: DCO_CTRL_BYPASS [11:00] */
-#define BCHP_CLKGEN_PLL_HVD_PLL_MISC_DCO_CTRL_BYPASS_MASK 0x00000fff
-#define BCHP_CLKGEN_PLL_HVD_PLL_MISC_DCO_CTRL_BYPASS_SHIFT 0
-#define BCHP_CLKGEN_PLL_HVD_PLL_MISC_DCO_CTRL_BYPASS_DEFAULT 0x00000000
-
-/***************************************************************************
- *PLL_HVD_PLL_MISC2 - Mscellaneous control bus continued.
- ***************************************************************************/
-/* CLKGEN :: PLL_HVD_PLL_MISC2 :: PLLRESERVED0 [31:02] */
-#define BCHP_CLKGEN_PLL_HVD_PLL_MISC2_PLLRESERVED0_MASK 0xfffffffc
-#define BCHP_CLKGEN_PLL_HVD_PLL_MISC2_PLLRESERVED0_SHIFT 2
-#define BCHP_CLKGEN_PLL_HVD_PLL_MISC2_PLLRESERVED0_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_HVD_PLL_MISC2 :: LDO [01:00] */
-#define BCHP_CLKGEN_PLL_HVD_PLL_MISC2_LDO_MASK 0x00000003
-#define BCHP_CLKGEN_PLL_HVD_PLL_MISC2_LDO_SHIFT 0
-#define BCHP_CLKGEN_PLL_HVD_PLL_MISC2_LDO_DEFAULT 0x00000001
-
-/***************************************************************************
- *PLL_HVD_PLL_PWRON - Poweron
- ***************************************************************************/
-/* CLKGEN :: PLL_HVD_PLL_PWRON :: reserved0 [31:01] */
-#define BCHP_CLKGEN_PLL_HVD_PLL_PWRON_reserved0_MASK 0xfffffffe
-#define BCHP_CLKGEN_PLL_HVD_PLL_PWRON_reserved0_SHIFT 1
-
-/* CLKGEN :: PLL_HVD_PLL_PWRON :: PWRON_PLL [00:00] */
-#define BCHP_CLKGEN_PLL_HVD_PLL_PWRON_PWRON_PLL_MASK 0x00000001
-#define BCHP_CLKGEN_PLL_HVD_PLL_PWRON_PWRON_PLL_SHIFT 0
-#define BCHP_CLKGEN_PLL_HVD_PLL_PWRON_PWRON_PLL_DEFAULT 0x00000001
-
-/***************************************************************************
- *PLL_HVD_PLL_RESET - Resets
- ***************************************************************************/
-/* CLKGEN :: PLL_HVD_PLL_RESET :: reserved0 [31:02] */
-#define BCHP_CLKGEN_PLL_HVD_PLL_RESET_reserved0_MASK 0xfffffffc
-#define BCHP_CLKGEN_PLL_HVD_PLL_RESET_reserved0_SHIFT 2
-
-/* CLKGEN :: PLL_HVD_PLL_RESET :: RESETD [01:01] */
-#define BCHP_CLKGEN_PLL_HVD_PLL_RESET_RESETD_MASK 0x00000002
-#define BCHP_CLKGEN_PLL_HVD_PLL_RESET_RESETD_SHIFT 1
-#define BCHP_CLKGEN_PLL_HVD_PLL_RESET_RESETD_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_HVD_PLL_RESET :: RESETA [00:00] */
-#define BCHP_CLKGEN_PLL_HVD_PLL_RESET_RESETA_MASK 0x00000001
-#define BCHP_CLKGEN_PLL_HVD_PLL_RESET_RESETA_SHIFT 0
-#define BCHP_CLKGEN_PLL_HVD_PLL_RESET_RESETA_DEFAULT 0x00000000
-
-/***************************************************************************
- *PLL_HVD_PLL_SSC_MODE_CONTROL_HIGH - Higher bits of Spread Spectrum mode control
- ***************************************************************************/
-/* CLKGEN :: PLL_HVD_PLL_SSC_MODE_CONTROL_HIGH :: reserved0 [31:16] */
-#define BCHP_CLKGEN_PLL_HVD_PLL_SSC_MODE_CONTROL_HIGH_reserved0_MASK 0xffff0000
-#define BCHP_CLKGEN_PLL_HVD_PLL_SSC_MODE_CONTROL_HIGH_reserved0_SHIFT 16
-
-/* CLKGEN :: PLL_HVD_PLL_SSC_MODE_CONTROL_HIGH :: SSC_STEP [15:00] */
-#define BCHP_CLKGEN_PLL_HVD_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_MASK 0x0000ffff
-#define BCHP_CLKGEN_PLL_HVD_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_SHIFT 0
-#define BCHP_CLKGEN_PLL_HVD_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *PLL_HVD_PLL_SSC_MODE_CONTROL_LOW - Lower bits of Spread Spectrum mode control
- ***************************************************************************/
-/* CLKGEN :: PLL_HVD_PLL_SSC_MODE_CONTROL_LOW :: reserved0 [31:23] */
-#define BCHP_CLKGEN_PLL_HVD_PLL_SSC_MODE_CONTROL_LOW_reserved0_MASK 0xff800000
-#define BCHP_CLKGEN_PLL_HVD_PLL_SSC_MODE_CONTROL_LOW_reserved0_SHIFT 23
-
-/* CLKGEN :: PLL_HVD_PLL_SSC_MODE_CONTROL_LOW :: SSC_MODE [22:22] */
-#define BCHP_CLKGEN_PLL_HVD_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_MASK 0x00400000
-#define BCHP_CLKGEN_PLL_HVD_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_SHIFT 22
-#define BCHP_CLKGEN_PLL_HVD_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_HVD_PLL_SSC_MODE_CONTROL_LOW :: SSC_LIMIT [21:00] */
-#define BCHP_CLKGEN_PLL_HVD_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_MASK 0x003fffff
-#define BCHP_CLKGEN_PLL_HVD_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_SHIFT 0
-#define BCHP_CLKGEN_PLL_HVD_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_DEFAULT 0x00000000
-
-/***************************************************************************
- *PLL_HVD_PLL_STATUS - Status
- ***************************************************************************/
-/* CLKGEN :: PLL_HVD_PLL_STATUS :: reserved0 [31:12] */
-#define BCHP_CLKGEN_PLL_HVD_PLL_STATUS_reserved0_MASK 0xfffff000
-#define BCHP_CLKGEN_PLL_HVD_PLL_STATUS_reserved0_SHIFT 12
-
-/* CLKGEN :: PLL_HVD_PLL_STATUS :: TEST_STATUS [11:00] */
-#define BCHP_CLKGEN_PLL_HVD_PLL_STATUS_TEST_STATUS_MASK 0x00000fff
-#define BCHP_CLKGEN_PLL_HVD_PLL_STATUS_TEST_STATUS_SHIFT 0
-
-/***************************************************************************
- *PLL_LC_PLL_CHANNEL_CTRL_CH_0 - PLL CHANNEL control CH 0
- ***************************************************************************/
-/* CLKGEN :: PLL_LC_PLL_CHANNEL_CTRL_CH_0 :: reserved0 [31:11] */
-#define BCHP_CLKGEN_PLL_LC_PLL_CHANNEL_CTRL_CH_0_reserved0_MASK 0xfffff800
-#define BCHP_CLKGEN_PLL_LC_PLL_CHANNEL_CTRL_CH_0_reserved0_SHIFT 11
-
-/* CLKGEN :: PLL_LC_PLL_CHANNEL_CTRL_CH_0 :: POST_DIVIDER_HOLD_CH0 [10:10] */
-#define BCHP_CLKGEN_PLL_LC_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_MASK 0x00000400
-#define BCHP_CLKGEN_PLL_LC_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_SHIFT 10
-#define BCHP_CLKGEN_PLL_LC_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_LC_PLL_CHANNEL_CTRL_CH_0 :: PHASE_OFFSET_CH0 [09:09] */
-#define BCHP_CLKGEN_PLL_LC_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_MASK 0x00000200
-#define BCHP_CLKGEN_PLL_LC_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_SHIFT 9
-#define BCHP_CLKGEN_PLL_LC_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_LC_PLL_CHANNEL_CTRL_CH_0 :: MDIV_CH0 [08:01] */
-#define BCHP_CLKGEN_PLL_LC_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_MASK 0x000001fe
-#define BCHP_CLKGEN_PLL_LC_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_SHIFT 1
-#define BCHP_CLKGEN_PLL_LC_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_DEFAULT 0x0000006c
-
-/* CLKGEN :: PLL_LC_PLL_CHANNEL_CTRL_CH_0 :: CLOCK_DIS_CH0 [00:00] */
-#define BCHP_CLKGEN_PLL_LC_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_MASK 0x00000001
-#define BCHP_CLKGEN_PLL_LC_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_SHIFT 0
-#define BCHP_CLKGEN_PLL_LC_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_DEFAULT 0x00000000
-
-/***************************************************************************
- *PLL_LC_PLL_CHANNEL_CTRL_CH_1 - PLL CHANNEL control CH 1
- ***************************************************************************/
-/* CLKGEN :: PLL_LC_PLL_CHANNEL_CTRL_CH_1 :: reserved0 [31:11] */
-#define BCHP_CLKGEN_PLL_LC_PLL_CHANNEL_CTRL_CH_1_reserved0_MASK 0xfffff800
-#define BCHP_CLKGEN_PLL_LC_PLL_CHANNEL_CTRL_CH_1_reserved0_SHIFT 11
-
-/* CLKGEN :: PLL_LC_PLL_CHANNEL_CTRL_CH_1 :: POST_DIVIDER_HOLD_CH1 [10:10] */
-#define BCHP_CLKGEN_PLL_LC_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_MASK 0x00000400
-#define BCHP_CLKGEN_PLL_LC_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_SHIFT 10
-#define BCHP_CLKGEN_PLL_LC_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_LC_PLL_CHANNEL_CTRL_CH_1 :: PHASE_OFFSET_CH1 [09:09] */
-#define BCHP_CLKGEN_PLL_LC_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_MASK 0x00000200
-#define BCHP_CLKGEN_PLL_LC_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_SHIFT 9
-#define BCHP_CLKGEN_PLL_LC_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_LC_PLL_CHANNEL_CTRL_CH_1 :: MDIV_CH1 [08:01] */
-#define BCHP_CLKGEN_PLL_LC_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_MASK 0x000001fe
-#define BCHP_CLKGEN_PLL_LC_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_SHIFT 1
-#define BCHP_CLKGEN_PLL_LC_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_DEFAULT 0x0000002d
-
-/* CLKGEN :: PLL_LC_PLL_CHANNEL_CTRL_CH_1 :: CLOCK_DIS_CH1 [00:00] */
-#define BCHP_CLKGEN_PLL_LC_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_MASK 0x00000001
-#define BCHP_CLKGEN_PLL_LC_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_SHIFT 0
-#define BCHP_CLKGEN_PLL_LC_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_DEFAULT 0x00000000
-
-/***************************************************************************
- *PLL_LC_PLL_CHANNEL_CTRL_CH_2 - PLL CHANNEL control CH 2
- ***************************************************************************/
-/* CLKGEN :: PLL_LC_PLL_CHANNEL_CTRL_CH_2 :: reserved0 [31:11] */
-#define BCHP_CLKGEN_PLL_LC_PLL_CHANNEL_CTRL_CH_2_reserved0_MASK 0xfffff800
-#define BCHP_CLKGEN_PLL_LC_PLL_CHANNEL_CTRL_CH_2_reserved0_SHIFT 11
-
-/* CLKGEN :: PLL_LC_PLL_CHANNEL_CTRL_CH_2 :: POST_DIVIDER_HOLD_CH2 [10:10] */
-#define BCHP_CLKGEN_PLL_LC_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_HOLD_CH2_MASK 0x00000400
-#define BCHP_CLKGEN_PLL_LC_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_HOLD_CH2_SHIFT 10
-#define BCHP_CLKGEN_PLL_LC_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_HOLD_CH2_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_LC_PLL_CHANNEL_CTRL_CH_2 :: PHASE_OFFSET_CH2 [09:09] */
-#define BCHP_CLKGEN_PLL_LC_PLL_CHANNEL_CTRL_CH_2_PHASE_OFFSET_CH2_MASK 0x00000200
-#define BCHP_CLKGEN_PLL_LC_PLL_CHANNEL_CTRL_CH_2_PHASE_OFFSET_CH2_SHIFT 9
-#define BCHP_CLKGEN_PLL_LC_PLL_CHANNEL_CTRL_CH_2_PHASE_OFFSET_CH2_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_LC_PLL_CHANNEL_CTRL_CH_2 :: MDIV_CH2 [08:01] */
-#define BCHP_CLKGEN_PLL_LC_PLL_CHANNEL_CTRL_CH_2_MDIV_CH2_MASK 0x000001fe
-#define BCHP_CLKGEN_PLL_LC_PLL_CHANNEL_CTRL_CH_2_MDIV_CH2_SHIFT 1
-#define BCHP_CLKGEN_PLL_LC_PLL_CHANNEL_CTRL_CH_2_MDIV_CH2_DEFAULT 0x0000002d
-
-/* CLKGEN :: PLL_LC_PLL_CHANNEL_CTRL_CH_2 :: CLOCK_DIS_CH2 [00:00] */
-#define BCHP_CLKGEN_PLL_LC_PLL_CHANNEL_CTRL_CH_2_CLOCK_DIS_CH2_MASK 0x00000001
-#define BCHP_CLKGEN_PLL_LC_PLL_CHANNEL_CTRL_CH_2_CLOCK_DIS_CH2_SHIFT 0
-#define BCHP_CLKGEN_PLL_LC_PLL_CHANNEL_CTRL_CH_2_CLOCK_DIS_CH2_DEFAULT 0x00000000
-
-/***************************************************************************
- *PLL_LC_PLL_CHANNEL_CTRL_CH_3 - PLL CHANNEL control CH 3
- ***************************************************************************/
-/* CLKGEN :: PLL_LC_PLL_CHANNEL_CTRL_CH_3 :: reserved0 [31:11] */
-#define BCHP_CLKGEN_PLL_LC_PLL_CHANNEL_CTRL_CH_3_reserved0_MASK 0xfffff800
-#define BCHP_CLKGEN_PLL_LC_PLL_CHANNEL_CTRL_CH_3_reserved0_SHIFT 11
-
-/* CLKGEN :: PLL_LC_PLL_CHANNEL_CTRL_CH_3 :: POST_DIVIDER_HOLD_CH3 [10:10] */
-#define BCHP_CLKGEN_PLL_LC_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_HOLD_CH3_MASK 0x00000400
-#define BCHP_CLKGEN_PLL_LC_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_HOLD_CH3_SHIFT 10
-#define BCHP_CLKGEN_PLL_LC_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_HOLD_CH3_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_LC_PLL_CHANNEL_CTRL_CH_3 :: PHASE_OFFSET_CH3 [09:09] */
-#define BCHP_CLKGEN_PLL_LC_PLL_CHANNEL_CTRL_CH_3_PHASE_OFFSET_CH3_MASK 0x00000200
-#define BCHP_CLKGEN_PLL_LC_PLL_CHANNEL_CTRL_CH_3_PHASE_OFFSET_CH3_SHIFT 9
-#define BCHP_CLKGEN_PLL_LC_PLL_CHANNEL_CTRL_CH_3_PHASE_OFFSET_CH3_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_LC_PLL_CHANNEL_CTRL_CH_3 :: MDIV_CH3 [08:01] */
-#define BCHP_CLKGEN_PLL_LC_PLL_CHANNEL_CTRL_CH_3_MDIV_CH3_MASK 0x000001fe
-#define BCHP_CLKGEN_PLL_LC_PLL_CHANNEL_CTRL_CH_3_MDIV_CH3_SHIFT 1
-#define BCHP_CLKGEN_PLL_LC_PLL_CHANNEL_CTRL_CH_3_MDIV_CH3_DEFAULT 0x00000019
-
-/* CLKGEN :: PLL_LC_PLL_CHANNEL_CTRL_CH_3 :: CLOCK_DIS_CH3 [00:00] */
-#define BCHP_CLKGEN_PLL_LC_PLL_CHANNEL_CTRL_CH_3_CLOCK_DIS_CH3_MASK 0x00000001
-#define BCHP_CLKGEN_PLL_LC_PLL_CHANNEL_CTRL_CH_3_CLOCK_DIS_CH3_SHIFT 0
-#define BCHP_CLKGEN_PLL_LC_PLL_CHANNEL_CTRL_CH_3_CLOCK_DIS_CH3_DEFAULT 0x00000000
-
-/***************************************************************************
- *PLL_LC_PLL_CHANNEL_CTRL_CH_4 - PLL CHANNEL control CH 4
- ***************************************************************************/
-/* CLKGEN :: PLL_LC_PLL_CHANNEL_CTRL_CH_4 :: reserved0 [31:11] */
-#define BCHP_CLKGEN_PLL_LC_PLL_CHANNEL_CTRL_CH_4_reserved0_MASK 0xfffff800
-#define BCHP_CLKGEN_PLL_LC_PLL_CHANNEL_CTRL_CH_4_reserved0_SHIFT 11
-
-/* CLKGEN :: PLL_LC_PLL_CHANNEL_CTRL_CH_4 :: POST_DIVIDER_HOLD_CH4 [10:10] */
-#define BCHP_CLKGEN_PLL_LC_PLL_CHANNEL_CTRL_CH_4_POST_DIVIDER_HOLD_CH4_MASK 0x00000400
-#define BCHP_CLKGEN_PLL_LC_PLL_CHANNEL_CTRL_CH_4_POST_DIVIDER_HOLD_CH4_SHIFT 10
-#define BCHP_CLKGEN_PLL_LC_PLL_CHANNEL_CTRL_CH_4_POST_DIVIDER_HOLD_CH4_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_LC_PLL_CHANNEL_CTRL_CH_4 :: PHASE_OFFSET_CH4 [09:09] */
-#define BCHP_CLKGEN_PLL_LC_PLL_CHANNEL_CTRL_CH_4_PHASE_OFFSET_CH4_MASK 0x00000200
-#define BCHP_CLKGEN_PLL_LC_PLL_CHANNEL_CTRL_CH_4_PHASE_OFFSET_CH4_SHIFT 9
-#define BCHP_CLKGEN_PLL_LC_PLL_CHANNEL_CTRL_CH_4_PHASE_OFFSET_CH4_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_LC_PLL_CHANNEL_CTRL_CH_4 :: MDIV_CH4 [08:01] */
-#define BCHP_CLKGEN_PLL_LC_PLL_CHANNEL_CTRL_CH_4_MDIV_CH4_MASK 0x000001fe
-#define BCHP_CLKGEN_PLL_LC_PLL_CHANNEL_CTRL_CH_4_MDIV_CH4_SHIFT 1
-#define BCHP_CLKGEN_PLL_LC_PLL_CHANNEL_CTRL_CH_4_MDIV_CH4_DEFAULT 0x00000036
-
-/* CLKGEN :: PLL_LC_PLL_CHANNEL_CTRL_CH_4 :: CLOCK_DIS_CH4 [00:00] */
-#define BCHP_CLKGEN_PLL_LC_PLL_CHANNEL_CTRL_CH_4_CLOCK_DIS_CH4_MASK 0x00000001
-#define BCHP_CLKGEN_PLL_LC_PLL_CHANNEL_CTRL_CH_4_CLOCK_DIS_CH4_SHIFT 0
-#define BCHP_CLKGEN_PLL_LC_PLL_CHANNEL_CTRL_CH_4_CLOCK_DIS_CH4_DEFAULT 0x00000000
-
-/***************************************************************************
- *PLL_LC_PLL_CHANNEL_CTRL_CH_5 - PLL CHANNEL control CH 5
- ***************************************************************************/
-/* CLKGEN :: PLL_LC_PLL_CHANNEL_CTRL_CH_5 :: reserved0 [31:11] */
-#define BCHP_CLKGEN_PLL_LC_PLL_CHANNEL_CTRL_CH_5_reserved0_MASK 0xfffff800
-#define BCHP_CLKGEN_PLL_LC_PLL_CHANNEL_CTRL_CH_5_reserved0_SHIFT 11
-
-/* CLKGEN :: PLL_LC_PLL_CHANNEL_CTRL_CH_5 :: POST_DIVIDER_HOLD_CH5 [10:10] */
-#define BCHP_CLKGEN_PLL_LC_PLL_CHANNEL_CTRL_CH_5_POST_DIVIDER_HOLD_CH5_MASK 0x00000400
-#define BCHP_CLKGEN_PLL_LC_PLL_CHANNEL_CTRL_CH_5_POST_DIVIDER_HOLD_CH5_SHIFT 10
-#define BCHP_CLKGEN_PLL_LC_PLL_CHANNEL_CTRL_CH_5_POST_DIVIDER_HOLD_CH5_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_LC_PLL_CHANNEL_CTRL_CH_5 :: PHASE_OFFSET_CH5 [09:09] */
-#define BCHP_CLKGEN_PLL_LC_PLL_CHANNEL_CTRL_CH_5_PHASE_OFFSET_CH5_MASK 0x00000200
-#define BCHP_CLKGEN_PLL_LC_PLL_CHANNEL_CTRL_CH_5_PHASE_OFFSET_CH5_SHIFT 9
-#define BCHP_CLKGEN_PLL_LC_PLL_CHANNEL_CTRL_CH_5_PHASE_OFFSET_CH5_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_LC_PLL_CHANNEL_CTRL_CH_5 :: MDIV_CH5 [08:01] */
-#define BCHP_CLKGEN_PLL_LC_PLL_CHANNEL_CTRL_CH_5_MDIV_CH5_MASK 0x000001fe
-#define BCHP_CLKGEN_PLL_LC_PLL_CHANNEL_CTRL_CH_5_MDIV_CH5_SHIFT 1
-#define BCHP_CLKGEN_PLL_LC_PLL_CHANNEL_CTRL_CH_5_MDIV_CH5_DEFAULT 0x00000019
-
-/* CLKGEN :: PLL_LC_PLL_CHANNEL_CTRL_CH_5 :: CLOCK_DIS_CH5 [00:00] */
-#define BCHP_CLKGEN_PLL_LC_PLL_CHANNEL_CTRL_CH_5_CLOCK_DIS_CH5_MASK 0x00000001
-#define BCHP_CLKGEN_PLL_LC_PLL_CHANNEL_CTRL_CH_5_CLOCK_DIS_CH5_SHIFT 0
-#define BCHP_CLKGEN_PLL_LC_PLL_CHANNEL_CTRL_CH_5_CLOCK_DIS_CH5_DEFAULT 0x00000000
-
-/***************************************************************************
- *PLL_LC_PLL_CONTROL - Miscellaneous Controls
- ***************************************************************************/
-/* CLKGEN :: PLL_LC_PLL_CONTROL :: reserved0 [31:01] */
-#define BCHP_CLKGEN_PLL_LC_PLL_CONTROL_reserved0_MASK 0xfffffffe
-#define BCHP_CLKGEN_PLL_LC_PLL_CONTROL_reserved0_SHIFT 1
-
-/* CLKGEN :: PLL_LC_PLL_CONTROL :: REF_SEL [00:00] */
-#define BCHP_CLKGEN_PLL_LC_PLL_CONTROL_REF_SEL_MASK 0x00000001
-#define BCHP_CLKGEN_PLL_LC_PLL_CONTROL_REF_SEL_SHIFT 0
-#define BCHP_CLKGEN_PLL_LC_PLL_CONTROL_REF_SEL_DEFAULT 0x00000000
-
-/***************************************************************************
- *PLL_LC_PLL_DIV - Pre multiplier
- ***************************************************************************/
-/* CLKGEN :: PLL_LC_PLL_DIV :: reserved0 [31:14] */
-#define BCHP_CLKGEN_PLL_LC_PLL_DIV_reserved0_MASK 0xffffc000
-#define BCHP_CLKGEN_PLL_LC_PLL_DIV_reserved0_SHIFT 14
-
-/* CLKGEN :: PLL_LC_PLL_DIV :: PDIV [13:10] */
-#define BCHP_CLKGEN_PLL_LC_PLL_DIV_PDIV_MASK 0x00003c00
-#define BCHP_CLKGEN_PLL_LC_PLL_DIV_PDIV_SHIFT 10
-#define BCHP_CLKGEN_PLL_LC_PLL_DIV_PDIV_DEFAULT 0x00000002
-
-/* CLKGEN :: PLL_LC_PLL_DIV :: NDIV_INT [09:00] */
-#define BCHP_CLKGEN_PLL_LC_PLL_DIV_NDIV_INT_MASK 0x000003ff
-#define BCHP_CLKGEN_PLL_LC_PLL_DIV_NDIV_INT_SHIFT 0
-#define BCHP_CLKGEN_PLL_LC_PLL_DIV_NDIV_INT_DEFAULT 0x00000064
-
-/***************************************************************************
- *PLL_LC_PLL_GAIN - PLL GAIN
- ***************************************************************************/
-/* CLKGEN :: PLL_LC_PLL_GAIN :: reserved0 [31:07] */
-#define BCHP_CLKGEN_PLL_LC_PLL_GAIN_reserved0_MASK 0xffffff80
-#define BCHP_CLKGEN_PLL_LC_PLL_GAIN_reserved0_SHIFT 7
-
-/* CLKGEN :: PLL_LC_PLL_GAIN :: LOOP_GAIN_PROPORTIONAL_IN_PHASE [06:03] */
-#define BCHP_CLKGEN_PLL_LC_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_MASK 0x00000078
-#define BCHP_CLKGEN_PLL_LC_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_SHIFT 3
-#define BCHP_CLKGEN_PLL_LC_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_DEFAULT 0x00000005
-
-/* CLKGEN :: PLL_LC_PLL_GAIN :: LOOP_GAIN_INTEGRATOR_IN_PHASE [02:00] */
-#define BCHP_CLKGEN_PLL_LC_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_MASK 0x00000007
-#define BCHP_CLKGEN_PLL_LC_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_SHIFT 0
-#define BCHP_CLKGEN_PLL_LC_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_DEFAULT 0x00000003
-
-/***************************************************************************
- *PLL_LC_PLL_HOLD_CH_ALL - Hold PLL all channels
- ***************************************************************************/
-/* CLKGEN :: PLL_LC_PLL_HOLD_CH_ALL :: reserved0 [31:01] */
-#define BCHP_CLKGEN_PLL_LC_PLL_HOLD_CH_ALL_reserved0_MASK 0xfffffffe
-#define BCHP_CLKGEN_PLL_LC_PLL_HOLD_CH_ALL_reserved0_SHIFT 1
-
-/* CLKGEN :: PLL_LC_PLL_HOLD_CH_ALL :: HOLD_CH_ALL [00:00] */
-#define BCHP_CLKGEN_PLL_LC_PLL_HOLD_CH_ALL_HOLD_CH_ALL_MASK 0x00000001
-#define BCHP_CLKGEN_PLL_LC_PLL_HOLD_CH_ALL_HOLD_CH_ALL_SHIFT 0
-#define BCHP_CLKGEN_PLL_LC_PLL_HOLD_CH_ALL_HOLD_CH_ALL_DEFAULT 0x00000000
-
-/***************************************************************************
- *PLL_LC_PLL_LDO_CTRL - Ldo voltage control
- ***************************************************************************/
-/* CLKGEN :: PLL_LC_PLL_LDO_CTRL :: reserved0 [31:06] */
-#define BCHP_CLKGEN_PLL_LC_PLL_LDO_CTRL_reserved0_MASK 0xffffffc0
-#define BCHP_CLKGEN_PLL_LC_PLL_LDO_CTRL_reserved0_SHIFT 6
-
-/* CLKGEN :: PLL_LC_PLL_LDO_CTRL :: LDO_CTRL [05:00] */
-#define BCHP_CLKGEN_PLL_LC_PLL_LDO_CTRL_LDO_CTRL_MASK 0x0000003f
-#define BCHP_CLKGEN_PLL_LC_PLL_LDO_CTRL_LDO_CTRL_SHIFT 0
-#define BCHP_CLKGEN_PLL_LC_PLL_LDO_CTRL_LDO_CTRL_DEFAULT 0x00000000
-
-/***************************************************************************
- *PLL_LC_PLL_LDO_PWRON - LDO Power on
- ***************************************************************************/
-/* CLKGEN :: PLL_LC_PLL_LDO_PWRON :: reserved0 [31:01] */
-#define BCHP_CLKGEN_PLL_LC_PLL_LDO_PWRON_reserved0_MASK 0xfffffffe
-#define BCHP_CLKGEN_PLL_LC_PLL_LDO_PWRON_reserved0_SHIFT 1
-
-/* CLKGEN :: PLL_LC_PLL_LDO_PWRON :: LDO_PWRON_PLL [00:00] */
-#define BCHP_CLKGEN_PLL_LC_PLL_LDO_PWRON_LDO_PWRON_PLL_MASK 0x00000001
-#define BCHP_CLKGEN_PLL_LC_PLL_LDO_PWRON_LDO_PWRON_PLL_SHIFT 0
-#define BCHP_CLKGEN_PLL_LC_PLL_LDO_PWRON_LDO_PWRON_PLL_DEFAULT 0x00000001
-
-/***************************************************************************
- *PLL_LC_PLL_LOCK_STATUS - Lock Status
- ***************************************************************************/
-/* CLKGEN :: PLL_LC_PLL_LOCK_STATUS :: reserved0 [31:01] */
-#define BCHP_CLKGEN_PLL_LC_PLL_LOCK_STATUS_reserved0_MASK 0xfffffffe
-#define BCHP_CLKGEN_PLL_LC_PLL_LOCK_STATUS_reserved0_SHIFT 1
-
-/* CLKGEN :: PLL_LC_PLL_LOCK_STATUS :: LOCK [00:00] */
-#define BCHP_CLKGEN_PLL_LC_PLL_LOCK_STATUS_LOCK_MASK 0x00000001
-#define BCHP_CLKGEN_PLL_LC_PLL_LOCK_STATUS_LOCK_SHIFT 0
-
-/***************************************************************************
- *PLL_LC_PLL_MISC - Mscellaneous control bus.
- ***************************************************************************/
-/* CLKGEN :: PLL_LC_PLL_MISC :: VCO_PREDIV_RATIO [31:31] */
-#define BCHP_CLKGEN_PLL_LC_PLL_MISC_VCO_PREDIV_RATIO_MASK 0x80000000
-#define BCHP_CLKGEN_PLL_LC_PLL_MISC_VCO_PREDIV_RATIO_SHIFT 31
-#define BCHP_CLKGEN_PLL_LC_PLL_MISC_VCO_PREDIV_RATIO_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_LC_PLL_MISC :: T2D_DELAY_SEL_LOW [30:28] */
-#define BCHP_CLKGEN_PLL_LC_PLL_MISC_T2D_DELAY_SEL_LOW_MASK 0x70000000
-#define BCHP_CLKGEN_PLL_LC_PLL_MISC_T2D_DELAY_SEL_LOW_SHIFT 28
-#define BCHP_CLKGEN_PLL_LC_PLL_MISC_T2D_DELAY_SEL_LOW_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_LC_PLL_MISC :: SEL_MEASURE_UNIT [27:25] */
-#define BCHP_CLKGEN_PLL_LC_PLL_MISC_SEL_MEASURE_UNIT_MASK 0x0e000000
-#define BCHP_CLKGEN_PLL_LC_PLL_MISC_SEL_MEASURE_UNIT_SHIFT 25
-#define BCHP_CLKGEN_PLL_LC_PLL_MISC_SEL_MEASURE_UNIT_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_LC_PLL_MISC :: RESET_MEASURE_MODE [24:24] */
-#define BCHP_CLKGEN_PLL_LC_PLL_MISC_RESET_MEASURE_MODE_MASK 0x01000000
-#define BCHP_CLKGEN_PLL_LC_PLL_MISC_RESET_MEASURE_MODE_SHIFT 24
-#define BCHP_CLKGEN_PLL_LC_PLL_MISC_RESET_MEASURE_MODE_DEFAULT 0x00000001
-
-/* CLKGEN :: PLL_LC_PLL_MISC :: LOAD_DCO_BYP_WORD [23:23] */
-#define BCHP_CLKGEN_PLL_LC_PLL_MISC_LOAD_DCO_BYP_WORD_MASK 0x00800000
-#define BCHP_CLKGEN_PLL_LC_PLL_MISC_LOAD_DCO_BYP_WORD_SHIFT 23
-#define BCHP_CLKGEN_PLL_LC_PLL_MISC_LOAD_DCO_BYP_WORD_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_LC_PLL_MISC :: FREQ_BYP_WORD [22:07] */
-#define BCHP_CLKGEN_PLL_LC_PLL_MISC_FREQ_BYP_WORD_MASK 0x007fff80
-#define BCHP_CLKGEN_PLL_LC_PLL_MISC_FREQ_BYP_WORD_SHIFT 7
-#define BCHP_CLKGEN_PLL_LC_PLL_MISC_FREQ_BYP_WORD_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_LC_PLL_MISC :: EN_VCO_OUTPUT [06:06] */
-#define BCHP_CLKGEN_PLL_LC_PLL_MISC_EN_VCO_OUTPUT_MASK 0x00000040
-#define BCHP_CLKGEN_PLL_LC_PLL_MISC_EN_VCO_OUTPUT_SHIFT 6
-#define BCHP_CLKGEN_PLL_LC_PLL_MISC_EN_VCO_OUTPUT_DEFAULT 0x00000001
-
-/* CLKGEN :: PLL_LC_PLL_MISC :: EN_DCO_BYP_WORD [05:05] */
-#define BCHP_CLKGEN_PLL_LC_PLL_MISC_EN_DCO_BYP_WORD_MASK 0x00000020
-#define BCHP_CLKGEN_PLL_LC_PLL_MISC_EN_DCO_BYP_WORD_SHIFT 5
-#define BCHP_CLKGEN_PLL_LC_PLL_MISC_EN_DCO_BYP_WORD_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_LC_PLL_MISC :: EN_BANGBANG_MODE [04:04] */
-#define BCHP_CLKGEN_PLL_LC_PLL_MISC_EN_BANGBANG_MODE_MASK 0x00000010
-#define BCHP_CLKGEN_PLL_LC_PLL_MISC_EN_BANGBANG_MODE_SHIFT 4
-#define BCHP_CLKGEN_PLL_LC_PLL_MISC_EN_BANGBANG_MODE_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_LC_PLL_MISC :: CTRL_MEASURE_MODE [03:02] */
-#define BCHP_CLKGEN_PLL_LC_PLL_MISC_CTRL_MEASURE_MODE_MASK 0x0000000c
-#define BCHP_CLKGEN_PLL_LC_PLL_MISC_CTRL_MEASURE_MODE_SHIFT 2
-#define BCHP_CLKGEN_PLL_LC_PLL_MISC_CTRL_MEASURE_MODE_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_LC_PLL_MISC :: CHANGE_MEASURE_UNIT [01:01] */
-#define BCHP_CLKGEN_PLL_LC_PLL_MISC_CHANGE_MEASURE_UNIT_MASK 0x00000002
-#define BCHP_CLKGEN_PLL_LC_PLL_MISC_CHANGE_MEASURE_UNIT_SHIFT 1
-#define BCHP_CLKGEN_PLL_LC_PLL_MISC_CHANGE_MEASURE_UNIT_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_LC_PLL_MISC :: BOOST_BIAS_CIRCUIT [00:00] */
-#define BCHP_CLKGEN_PLL_LC_PLL_MISC_BOOST_BIAS_CIRCUIT_MASK 0x00000001
-#define BCHP_CLKGEN_PLL_LC_PLL_MISC_BOOST_BIAS_CIRCUIT_SHIFT 0
-#define BCHP_CLKGEN_PLL_LC_PLL_MISC_BOOST_BIAS_CIRCUIT_DEFAULT 0x00000001
-
-/***************************************************************************
- *PLL_LC_PLL_MISC2 - Mscellaneous control bus continued.
- ***************************************************************************/
-/* CLKGEN :: PLL_LC_PLL_MISC2 :: T2D_DELAY_SEL_HIGH [31:31] */
-#define BCHP_CLKGEN_PLL_LC_PLL_MISC2_T2D_DELAY_SEL_HIGH_MASK 0x80000000
-#define BCHP_CLKGEN_PLL_LC_PLL_MISC2_T2D_DELAY_SEL_HIGH_SHIFT 31
-#define BCHP_CLKGEN_PLL_LC_PLL_MISC2_T2D_DELAY_SEL_HIGH_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_LC_PLL_MISC2 :: SEL_TEST_CLK [30:30] */
-#define BCHP_CLKGEN_PLL_LC_PLL_MISC2_SEL_TEST_CLK_MASK 0x40000000
-#define BCHP_CLKGEN_PLL_LC_PLL_MISC2_SEL_TEST_CLK_SHIFT 30
-#define BCHP_CLKGEN_PLL_LC_PLL_MISC2_SEL_TEST_CLK_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_LC_PLL_MISC2 :: SEL_DIFF_REFCLK_SRC [29:29] */
-#define BCHP_CLKGEN_PLL_LC_PLL_MISC2_SEL_DIFF_REFCLK_SRC_MASK 0x20000000
-#define BCHP_CLKGEN_PLL_LC_PLL_MISC2_SEL_DIFF_REFCLK_SRC_SHIFT 29
-#define BCHP_CLKGEN_PLL_LC_PLL_MISC2_SEL_DIFF_REFCLK_SRC_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_LC_PLL_MISC2 :: PLLRESERVED0 [28:11] */
-#define BCHP_CLKGEN_PLL_LC_PLL_MISC2_PLLRESERVED0_MASK 0x1ffff800
-#define BCHP_CLKGEN_PLL_LC_PLL_MISC2_PLLRESERVED0_SHIFT 11
-#define BCHP_CLKGEN_PLL_LC_PLL_MISC2_PLLRESERVED0_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_LC_PLL_MISC2 :: INTERNAL_RESET_MODE [10:09] */
-#define BCHP_CLKGEN_PLL_LC_PLL_MISC2_INTERNAL_RESET_MODE_MASK 0x00000600
-#define BCHP_CLKGEN_PLL_LC_PLL_MISC2_INTERNAL_RESET_MODE_SHIFT 9
-#define BCHP_CLKGEN_PLL_LC_PLL_MISC2_INTERNAL_RESET_MODE_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_LC_PLL_MISC2 :: EN_TEST_CLK [08:08] */
-#define BCHP_CLKGEN_PLL_LC_PLL_MISC2_EN_TEST_CLK_MASK 0x00000100
-#define BCHP_CLKGEN_PLL_LC_PLL_MISC2_EN_TEST_CLK_SHIFT 8
-#define BCHP_CLKGEN_PLL_LC_PLL_MISC2_EN_TEST_CLK_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_LC_PLL_MISC2 :: EN_BYPCLK_1 [07:07] */
-#define BCHP_CLKGEN_PLL_LC_PLL_MISC2_EN_BYPCLK_1_MASK 0x00000080
-#define BCHP_CLKGEN_PLL_LC_PLL_MISC2_EN_BYPCLK_1_SHIFT 7
-#define BCHP_CLKGEN_PLL_LC_PLL_MISC2_EN_BYPCLK_1_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_LC_PLL_MISC2 :: EN_BYPCLK_0 [06:06] */
-#define BCHP_CLKGEN_PLL_LC_PLL_MISC2_EN_BYPCLK_0_MASK 0x00000040
-#define BCHP_CLKGEN_PLL_LC_PLL_MISC2_EN_BYPCLK_0_SHIFT 6
-#define BCHP_CLKGEN_PLL_LC_PLL_MISC2_EN_BYPCLK_0_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_LC_PLL_MISC2 :: DCO_PWM_RATE_CTRL [05:04] */
-#define BCHP_CLKGEN_PLL_LC_PLL_MISC2_DCO_PWM_RATE_CTRL_MASK 0x00000030
-#define BCHP_CLKGEN_PLL_LC_PLL_MISC2_DCO_PWM_RATE_CTRL_SHIFT 4
-#define BCHP_CLKGEN_PLL_LC_PLL_MISC2_DCO_PWM_RATE_CTRL_DEFAULT 0x00000002
-
-/* CLKGEN :: PLL_LC_PLL_MISC2 :: CTRL_2ND_POLE [03:00] */
-#define BCHP_CLKGEN_PLL_LC_PLL_MISC2_CTRL_2ND_POLE_MASK 0x0000000f
-#define BCHP_CLKGEN_PLL_LC_PLL_MISC2_CTRL_2ND_POLE_SHIFT 0
-#define BCHP_CLKGEN_PLL_LC_PLL_MISC2_CTRL_2ND_POLE_DEFAULT 0x00000000
-
-/***************************************************************************
- *PLL_LC_PLL_OUTSEL_SEL - selection of the output clock from the PLL core
- ***************************************************************************/
-/* CLKGEN :: PLL_LC_PLL_OUTSEL_SEL :: reserved0 [31:03] */
-#define BCHP_CLKGEN_PLL_LC_PLL_OUTSEL_SEL_reserved0_MASK 0xfffffff8
-#define BCHP_CLKGEN_PLL_LC_PLL_OUTSEL_SEL_reserved0_SHIFT 3
-
-/* CLKGEN :: PLL_LC_PLL_OUTSEL_SEL :: OUTPUT_SEL [02:00] */
-#define BCHP_CLKGEN_PLL_LC_PLL_OUTSEL_SEL_OUTPUT_SEL_MASK 0x00000007
-#define BCHP_CLKGEN_PLL_LC_PLL_OUTSEL_SEL_OUTPUT_SEL_SHIFT 0
-#define BCHP_CLKGEN_PLL_LC_PLL_OUTSEL_SEL_OUTPUT_SEL_DEFAULT 0x00000000
-
-/***************************************************************************
- *PLL_LC_PLL_PWRON - Poweron
- ***************************************************************************/
-/* CLKGEN :: PLL_LC_PLL_PWRON :: reserved0 [31:01] */
-#define BCHP_CLKGEN_PLL_LC_PLL_PWRON_reserved0_MASK 0xfffffffe
-#define BCHP_CLKGEN_PLL_LC_PLL_PWRON_reserved0_SHIFT 1
-
-/* CLKGEN :: PLL_LC_PLL_PWRON :: PWRON_PLL [00:00] */
-#define BCHP_CLKGEN_PLL_LC_PLL_PWRON_PWRON_PLL_MASK 0x00000001
-#define BCHP_CLKGEN_PLL_LC_PLL_PWRON_PWRON_PLL_SHIFT 0
-#define BCHP_CLKGEN_PLL_LC_PLL_PWRON_PWRON_PLL_DEFAULT 0x00000001
-
-/***************************************************************************
- *PLL_LC_PLL_RESET - Resets
- ***************************************************************************/
-/* CLKGEN :: PLL_LC_PLL_RESET :: reserved0 [31:02] */
-#define BCHP_CLKGEN_PLL_LC_PLL_RESET_reserved0_MASK 0xfffffffc
-#define BCHP_CLKGEN_PLL_LC_PLL_RESET_reserved0_SHIFT 2
-
-/* CLKGEN :: PLL_LC_PLL_RESET :: RESETD [01:01] */
-#define BCHP_CLKGEN_PLL_LC_PLL_RESET_RESETD_MASK 0x00000002
-#define BCHP_CLKGEN_PLL_LC_PLL_RESET_RESETD_SHIFT 1
-#define BCHP_CLKGEN_PLL_LC_PLL_RESET_RESETD_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_LC_PLL_RESET :: RESETA [00:00] */
-#define BCHP_CLKGEN_PLL_LC_PLL_RESET_RESETA_MASK 0x00000001
-#define BCHP_CLKGEN_PLL_LC_PLL_RESET_RESETA_SHIFT 0
-#define BCHP_CLKGEN_PLL_LC_PLL_RESET_RESETA_DEFAULT 0x00000000
-
-/***************************************************************************
- *PLL_LC_PLL_STATUS - Status
- ***************************************************************************/
-/* CLKGEN :: PLL_LC_PLL_STATUS :: TEST_STATUS [31:00] */
-#define BCHP_CLKGEN_PLL_LC_PLL_STATUS_TEST_STATUS_MASK 0xffffffff
-#define BCHP_CLKGEN_PLL_LC_PLL_STATUS_TEST_STATUS_SHIFT 0
-
-/***************************************************************************
- *PLL_LC_PLL_TEST - enable and selection pf PLL test
- ***************************************************************************/
-/* CLKGEN :: PLL_LC_PLL_TEST :: reserved0 [31:04] */
-#define BCHP_CLKGEN_PLL_LC_PLL_TEST_reserved0_MASK 0xfffffff0
-#define BCHP_CLKGEN_PLL_LC_PLL_TEST_reserved0_SHIFT 4
-
-/* CLKGEN :: PLL_LC_PLL_TEST :: TEST_SEL [03:01] */
-#define BCHP_CLKGEN_PLL_LC_PLL_TEST_TEST_SEL_MASK 0x0000000e
-#define BCHP_CLKGEN_PLL_LC_PLL_TEST_TEST_SEL_SHIFT 1
-#define BCHP_CLKGEN_PLL_LC_PLL_TEST_TEST_SEL_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_LC_PLL_TEST :: TEST_ENABLE [00:00] */
-#define BCHP_CLKGEN_PLL_LC_PLL_TEST_TEST_ENABLE_MASK 0x00000001
-#define BCHP_CLKGEN_PLL_LC_PLL_TEST_TEST_ENABLE_SHIFT 0
-#define BCHP_CLKGEN_PLL_LC_PLL_TEST_TEST_ENABLE_DEFAULT 0x00000000
-
-/***************************************************************************
- *PLL_MOCA_PLL_CHANNEL_CTRL_CH_0 - PLL CHANNEL control CH 0
- ***************************************************************************/
-/* CLKGEN :: PLL_MOCA_PLL_CHANNEL_CTRL_CH_0 :: reserved0 [31:11] */
-#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_0_reserved0_MASK 0xfffff800
-#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_0_reserved0_SHIFT 11
-
-/* CLKGEN :: PLL_MOCA_PLL_CHANNEL_CTRL_CH_0 :: POST_DIVIDER_HOLD_CH0 [10:10] */
-#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_MASK 0x00000400
-#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_SHIFT 10
-#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_MOCA_PLL_CHANNEL_CTRL_CH_0 :: PHASE_OFFSET_CH0 [09:09] */
-#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_MASK 0x00000200
-#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_SHIFT 9
-#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_MOCA_PLL_CHANNEL_CTRL_CH_0 :: MDIV_CH0 [08:01] */
-#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_MASK 0x000001fe
-#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_SHIFT 1
-#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_DEFAULT 0x00000009
-
-/* CLKGEN :: PLL_MOCA_PLL_CHANNEL_CTRL_CH_0 :: CLOCK_DIS_CH0 [00:00] */
-#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_MASK 0x00000001
-#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_SHIFT 0
-#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_DEFAULT 0x00000000
-
-/***************************************************************************
- *PLL_MOCA_PLL_CHANNEL_CTRL_CH_1 - PLL CHANNEL control CH 1
- ***************************************************************************/
-/* CLKGEN :: PLL_MOCA_PLL_CHANNEL_CTRL_CH_1 :: reserved0 [31:11] */
-#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_1_reserved0_MASK 0xfffff800
-#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_1_reserved0_SHIFT 11
-
-/* CLKGEN :: PLL_MOCA_PLL_CHANNEL_CTRL_CH_1 :: POST_DIVIDER_HOLD_CH1 [10:10] */
-#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_MASK 0x00000400
-#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_SHIFT 10
-#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_MOCA_PLL_CHANNEL_CTRL_CH_1 :: PHASE_OFFSET_CH1 [09:09] */
-#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_MASK 0x00000200
-#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_SHIFT 9
-#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_MOCA_PLL_CHANNEL_CTRL_CH_1 :: MDIV_CH1 [08:01] */
-#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_MASK 0x000001fe
-#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_SHIFT 1
-#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_DEFAULT 0x00000009
-
-/* CLKGEN :: PLL_MOCA_PLL_CHANNEL_CTRL_CH_1 :: CLOCK_DIS_CH1 [00:00] */
-#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_MASK 0x00000001
-#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_SHIFT 0
-#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_DEFAULT 0x00000000
-
-/***************************************************************************
- *PLL_MOCA_PLL_CHANNEL_CTRL_CH_2 - PLL CHANNEL control CH 2
- ***************************************************************************/
-/* CLKGEN :: PLL_MOCA_PLL_CHANNEL_CTRL_CH_2 :: reserved0 [31:11] */
-#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_2_reserved0_MASK 0xfffff800
-#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_2_reserved0_SHIFT 11
-
-/* CLKGEN :: PLL_MOCA_PLL_CHANNEL_CTRL_CH_2 :: POST_DIVIDER_HOLD_CH2 [10:10] */
-#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_HOLD_CH2_MASK 0x00000400
-#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_HOLD_CH2_SHIFT 10
-#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_HOLD_CH2_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_MOCA_PLL_CHANNEL_CTRL_CH_2 :: PHASE_OFFSET_CH2 [09:09] */
-#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_2_PHASE_OFFSET_CH2_MASK 0x00000200
-#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_2_PHASE_OFFSET_CH2_SHIFT 9
-#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_2_PHASE_OFFSET_CH2_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_MOCA_PLL_CHANNEL_CTRL_CH_2 :: MDIV_CH2 [08:01] */
-#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_2_MDIV_CH2_MASK 0x000001fe
-#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_2_MDIV_CH2_SHIFT 1
-#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_2_MDIV_CH2_DEFAULT 0x00000024
-
-/* CLKGEN :: PLL_MOCA_PLL_CHANNEL_CTRL_CH_2 :: CLOCK_DIS_CH2 [00:00] */
-#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_2_CLOCK_DIS_CH2_MASK 0x00000001
-#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_2_CLOCK_DIS_CH2_SHIFT 0
-#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_2_CLOCK_DIS_CH2_DEFAULT 0x00000000
-
-/***************************************************************************
- *PLL_MOCA_PLL_CHANNEL_CTRL_CH_4 - PLL CHANNEL control CH 4
- ***************************************************************************/
-/* CLKGEN :: PLL_MOCA_PLL_CHANNEL_CTRL_CH_4 :: reserved0 [31:11] */
-#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_4_reserved0_MASK 0xfffff800
-#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_4_reserved0_SHIFT 11
-
-/* CLKGEN :: PLL_MOCA_PLL_CHANNEL_CTRL_CH_4 :: POST_DIVIDER_HOLD_CH4 [10:10] */
-#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_4_POST_DIVIDER_HOLD_CH4_MASK 0x00000400
-#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_4_POST_DIVIDER_HOLD_CH4_SHIFT 10
-#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_4_POST_DIVIDER_HOLD_CH4_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_MOCA_PLL_CHANNEL_CTRL_CH_4 :: PHASE_OFFSET_CH4 [09:09] */
-#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_4_PHASE_OFFSET_CH4_MASK 0x00000200
-#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_4_PHASE_OFFSET_CH4_SHIFT 9
-#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_4_PHASE_OFFSET_CH4_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_MOCA_PLL_CHANNEL_CTRL_CH_4 :: MDIV_CH4 [08:01] */
-#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_4_MDIV_CH4_MASK 0x000001fe
-#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_4_MDIV_CH4_SHIFT 1
-#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_4_MDIV_CH4_DEFAULT 0x00000007
-
-/* CLKGEN :: PLL_MOCA_PLL_CHANNEL_CTRL_CH_4 :: CLOCK_DIS_CH4 [00:00] */
-#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_4_CLOCK_DIS_CH4_MASK 0x00000001
-#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_4_CLOCK_DIS_CH4_SHIFT 0
-#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_4_CLOCK_DIS_CH4_DEFAULT 0x00000000
-
-/***************************************************************************
- *PLL_MOCA_PLL_CHANNEL_CTRL_CH_5 - PLL CHANNEL control CH 5
- ***************************************************************************/
-/* CLKGEN :: PLL_MOCA_PLL_CHANNEL_CTRL_CH_5 :: reserved0 [31:11] */
-#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_5_reserved0_MASK 0xfffff800
-#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_5_reserved0_SHIFT 11
-
-/* CLKGEN :: PLL_MOCA_PLL_CHANNEL_CTRL_CH_5 :: POST_DIVIDER_HOLD_CH5 [10:10] */
-#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_5_POST_DIVIDER_HOLD_CH5_MASK 0x00000400
-#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_5_POST_DIVIDER_HOLD_CH5_SHIFT 10
-#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_5_POST_DIVIDER_HOLD_CH5_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_MOCA_PLL_CHANNEL_CTRL_CH_5 :: PHASE_OFFSET_CH5 [09:09] */
-#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_5_PHASE_OFFSET_CH5_MASK 0x00000200
-#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_5_PHASE_OFFSET_CH5_SHIFT 9
-#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_5_PHASE_OFFSET_CH5_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_MOCA_PLL_CHANNEL_CTRL_CH_5 :: MDIV_CH5 [08:01] */
-#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_5_MDIV_CH5_MASK 0x000001fe
-#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_5_MDIV_CH5_SHIFT 1
-#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_5_MDIV_CH5_DEFAULT 0x00000024
-
-/* CLKGEN :: PLL_MOCA_PLL_CHANNEL_CTRL_CH_5 :: CLOCK_DIS_CH5 [00:00] */
-#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_5_CLOCK_DIS_CH5_MASK 0x00000001
-#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_5_CLOCK_DIS_CH5_SHIFT 0
-#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_5_CLOCK_DIS_CH5_DEFAULT 0x00000000
-
-/***************************************************************************
- *PLL_MOCA_PLL_DIV - Pre multiplier
- ***************************************************************************/
-/* CLKGEN :: PLL_MOCA_PLL_DIV :: reserved0 [31:14] */
-#define BCHP_CLKGEN_PLL_MOCA_PLL_DIV_reserved0_MASK 0xffffc000
-#define BCHP_CLKGEN_PLL_MOCA_PLL_DIV_reserved0_SHIFT 14
-
-/* CLKGEN :: PLL_MOCA_PLL_DIV :: PDIV [13:10] */
-#define BCHP_CLKGEN_PLL_MOCA_PLL_DIV_PDIV_MASK 0x00003c00
-#define BCHP_CLKGEN_PLL_MOCA_PLL_DIV_PDIV_SHIFT 10
-#define BCHP_CLKGEN_PLL_MOCA_PLL_DIV_PDIV_DEFAULT 0x00000003
-
-/* CLKGEN :: PLL_MOCA_PLL_DIV :: NDIV_INT [09:00] */
-#define BCHP_CLKGEN_PLL_MOCA_PLL_DIV_NDIV_INT_MASK 0x000003ff
-#define BCHP_CLKGEN_PLL_MOCA_PLL_DIV_NDIV_INT_SHIFT 0
-#define BCHP_CLKGEN_PLL_MOCA_PLL_DIV_NDIV_INT_DEFAULT 0x000000c8
-
-/***************************************************************************
- *PLL_MOCA_PLL_GAIN - PLL GAIN
- ***************************************************************************/
-/* CLKGEN :: PLL_MOCA_PLL_GAIN :: reserved0 [31:10] */
-#define BCHP_CLKGEN_PLL_MOCA_PLL_GAIN_reserved0_MASK 0xfffffc00
-#define BCHP_CLKGEN_PLL_MOCA_PLL_GAIN_reserved0_SHIFT 10
-
-/* CLKGEN :: PLL_MOCA_PLL_GAIN :: LOOP_GAIN_PROPORTIONAL_IN_PHASE [09:06] */
-#define BCHP_CLKGEN_PLL_MOCA_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_MASK 0x000003c0
-#define BCHP_CLKGEN_PLL_MOCA_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_SHIFT 6
-#define BCHP_CLKGEN_PLL_MOCA_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_DEFAULT 0x00000003
-
-/* CLKGEN :: PLL_MOCA_PLL_GAIN :: LOOP_GAIN_IN_FREQ [05:03] */
-#define BCHP_CLKGEN_PLL_MOCA_PLL_GAIN_LOOP_GAIN_IN_FREQ_MASK 0x00000038
-#define BCHP_CLKGEN_PLL_MOCA_PLL_GAIN_LOOP_GAIN_IN_FREQ_SHIFT 3
-#define BCHP_CLKGEN_PLL_MOCA_PLL_GAIN_LOOP_GAIN_IN_FREQ_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_MOCA_PLL_GAIN :: LOOP_GAIN_INTEGRATOR_IN_PHASE [02:00] */
-#define BCHP_CLKGEN_PLL_MOCA_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_MASK 0x00000007
-#define BCHP_CLKGEN_PLL_MOCA_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_SHIFT 0
-#define BCHP_CLKGEN_PLL_MOCA_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_DEFAULT 0x00000002
-
-/***************************************************************************
- *PLL_MOCA_PLL_LDO_PWRON - LDO Power on
- ***************************************************************************/
-/* CLKGEN :: PLL_MOCA_PLL_LDO_PWRON :: reserved0 [31:01] */
-#define BCHP_CLKGEN_PLL_MOCA_PLL_LDO_PWRON_reserved0_MASK 0xfffffffe
-#define BCHP_CLKGEN_PLL_MOCA_PLL_LDO_PWRON_reserved0_SHIFT 1
-
-/* CLKGEN :: PLL_MOCA_PLL_LDO_PWRON :: LDO_PWRON_PLL [00:00] */
-#define BCHP_CLKGEN_PLL_MOCA_PLL_LDO_PWRON_LDO_PWRON_PLL_MASK 0x00000001
-#define BCHP_CLKGEN_PLL_MOCA_PLL_LDO_PWRON_LDO_PWRON_PLL_SHIFT 0
-#define BCHP_CLKGEN_PLL_MOCA_PLL_LDO_PWRON_LDO_PWRON_PLL_DEFAULT 0x00000001
-
-/***************************************************************************
- *PLL_MOCA_PLL_LOCK_STATUS - Lock Status
- ***************************************************************************/
-/* CLKGEN :: PLL_MOCA_PLL_LOCK_STATUS :: reserved0 [31:02] */
-#define BCHP_CLKGEN_PLL_MOCA_PLL_LOCK_STATUS_reserved0_MASK 0xfffffffc
-#define BCHP_CLKGEN_PLL_MOCA_PLL_LOCK_STATUS_reserved0_SHIFT 2
-
-/* CLKGEN :: PLL_MOCA_PLL_LOCK_STATUS :: LOCK_LOST [01:01] */
-#define BCHP_CLKGEN_PLL_MOCA_PLL_LOCK_STATUS_LOCK_LOST_MASK 0x00000002
-#define BCHP_CLKGEN_PLL_MOCA_PLL_LOCK_STATUS_LOCK_LOST_SHIFT 1
-
-/* CLKGEN :: PLL_MOCA_PLL_LOCK_STATUS :: LOCK [00:00] */
-#define BCHP_CLKGEN_PLL_MOCA_PLL_LOCK_STATUS_LOCK_MASK 0x00000001
-#define BCHP_CLKGEN_PLL_MOCA_PLL_LOCK_STATUS_LOCK_SHIFT 0
-
-/***************************************************************************
- *PLL_MOCA_PLL_MISC - Mscellaneous control bus.
- ***************************************************************************/
-/* CLKGEN :: PLL_MOCA_PLL_MISC :: VCO_RANGE [31:30] */
-#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_VCO_RANGE_MASK 0xc0000000
-#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_VCO_RANGE_SHIFT 30
-#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_VCO_RANGE_DEFAULT 0x00000002
-
-/* CLKGEN :: PLL_MOCA_PLL_MISC :: VCO_FB_DIV2 [29:29] */
-#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_VCO_FB_DIV2_MASK 0x20000000
-#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_VCO_FB_DIV2_SHIFT 29
-#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_VCO_FB_DIV2_DEFAULT 0x00000001
-
-/* CLKGEN :: PLL_MOCA_PLL_MISC :: STAT_UPDATE [28:28] */
-#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_STAT_UPDATE_MASK 0x10000000
-#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_STAT_UPDATE_SHIFT 28
-#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_STAT_UPDATE_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_MOCA_PLL_MISC :: STAT_SELECT [27:25] */
-#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_STAT_SELECT_MASK 0x0e000000
-#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_STAT_SELECT_SHIFT 25
-#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_STAT_SELECT_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_MOCA_PLL_MISC :: STAT_RESET [24:24] */
-#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_STAT_RESET_MASK 0x01000000
-#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_STAT_RESET_SHIFT 24
-#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_STAT_RESET_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_MOCA_PLL_MISC :: STAT_MODE [23:22] */
-#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_STAT_MODE_MASK 0x00c00000
-#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_STAT_MODE_SHIFT 22
-#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_STAT_MODE_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_MOCA_PLL_MISC :: PWM_RATE [21:20] */
-#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_PWM_RATE_MASK 0x00300000
-#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_PWM_RATE_SHIFT 20
-#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_PWM_RATE_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_MOCA_PLL_MISC :: POST_CTRL_RESETB [19:18] */
-#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_POST_CTRL_RESETB_MASK 0x000c0000
-#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_POST_CTRL_RESETB_SHIFT 18
-#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_POST_CTRL_RESETB_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_MOCA_PLL_MISC :: PLLRESERVED2 [17:16] */
-#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_PLLRESERVED2_MASK 0x00030000
-#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_PLLRESERVED2_SHIFT 16
-#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_PLLRESERVED2_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_MOCA_PLL_MISC :: PLLRESERVED1 [15:15] */
-#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_PLLRESERVED1_MASK 0x00008000
-#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_PLLRESERVED1_SHIFT 15
-#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_PLLRESERVED1_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_MOCA_PLL_MISC :: NDIV_RELOCK [14:14] */
-#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_NDIV_RELOCK_MASK 0x00004000
-#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_NDIV_RELOCK_SHIFT 14
-#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_NDIV_RELOCK_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_MOCA_PLL_MISC :: FAST_LOCK [13:13] */
-#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_FAST_LOCK_MASK 0x00002000
-#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_FAST_LOCK_SHIFT 13
-#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_FAST_LOCK_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_MOCA_PLL_MISC :: DCO_CTRL_BYPASS_ENABLE [12:12] */
-#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_MASK 0x00001000
-#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_SHIFT 12
-#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_MOCA_PLL_MISC :: DCO_CTRL_BYPASS [11:00] */
-#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_DCO_CTRL_BYPASS_MASK 0x00000fff
-#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_DCO_CTRL_BYPASS_SHIFT 0
-#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_DCO_CTRL_BYPASS_DEFAULT 0x00000000
-
-/***************************************************************************
- *PLL_MOCA_PLL_MISC2 - Mscellaneous control bus continued.
- ***************************************************************************/
-/* CLKGEN :: PLL_MOCA_PLL_MISC2 :: PLLRESERVED0 [31:02] */
-#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC2_PLLRESERVED0_MASK 0xfffffffc
-#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC2_PLLRESERVED0_SHIFT 2
-#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC2_PLLRESERVED0_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_MOCA_PLL_MISC2 :: LDO [01:00] */
-#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC2_LDO_MASK 0x00000003
-#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC2_LDO_SHIFT 0
-#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC2_LDO_DEFAULT 0x00000001
-
-/***************************************************************************
- *PLL_MOCA_PLL_PWRON - Poweron
- ***************************************************************************/
-/* CLKGEN :: PLL_MOCA_PLL_PWRON :: reserved0 [31:01] */
-#define BCHP_CLKGEN_PLL_MOCA_PLL_PWRON_reserved0_MASK 0xfffffffe
-#define BCHP_CLKGEN_PLL_MOCA_PLL_PWRON_reserved0_SHIFT 1
-
-/* CLKGEN :: PLL_MOCA_PLL_PWRON :: PWRON_PLL [00:00] */
-#define BCHP_CLKGEN_PLL_MOCA_PLL_PWRON_PWRON_PLL_MASK 0x00000001
-#define BCHP_CLKGEN_PLL_MOCA_PLL_PWRON_PWRON_PLL_SHIFT 0
-#define BCHP_CLKGEN_PLL_MOCA_PLL_PWRON_PWRON_PLL_DEFAULT 0x00000001
-
-/***************************************************************************
- *PLL_MOCA_PLL_RESET - Resets
- ***************************************************************************/
-/* CLKGEN :: PLL_MOCA_PLL_RESET :: reserved0 [31:02] */
-#define BCHP_CLKGEN_PLL_MOCA_PLL_RESET_reserved0_MASK 0xfffffffc
-#define BCHP_CLKGEN_PLL_MOCA_PLL_RESET_reserved0_SHIFT 2
-
-/* CLKGEN :: PLL_MOCA_PLL_RESET :: RESETD [01:01] */
-#define BCHP_CLKGEN_PLL_MOCA_PLL_RESET_RESETD_MASK 0x00000002
-#define BCHP_CLKGEN_PLL_MOCA_PLL_RESET_RESETD_SHIFT 1
-#define BCHP_CLKGEN_PLL_MOCA_PLL_RESET_RESETD_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_MOCA_PLL_RESET :: RESETA [00:00] */
-#define BCHP_CLKGEN_PLL_MOCA_PLL_RESET_RESETA_MASK 0x00000001
-#define BCHP_CLKGEN_PLL_MOCA_PLL_RESET_RESETA_SHIFT 0
-#define BCHP_CLKGEN_PLL_MOCA_PLL_RESET_RESETA_DEFAULT 0x00000000
-
-/***************************************************************************
- *PLL_MOCA_PLL_SSC_MODE_CONTROL_HIGH - Higher bits of Spread Spectrum mode control
- ***************************************************************************/
-/* CLKGEN :: PLL_MOCA_PLL_SSC_MODE_CONTROL_HIGH :: reserved0 [31:16] */
-#define BCHP_CLKGEN_PLL_MOCA_PLL_SSC_MODE_CONTROL_HIGH_reserved0_MASK 0xffff0000
-#define BCHP_CLKGEN_PLL_MOCA_PLL_SSC_MODE_CONTROL_HIGH_reserved0_SHIFT 16
-
-/* CLKGEN :: PLL_MOCA_PLL_SSC_MODE_CONTROL_HIGH :: SSC_STEP [15:00] */
-#define BCHP_CLKGEN_PLL_MOCA_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_MASK 0x0000ffff
-#define BCHP_CLKGEN_PLL_MOCA_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_SHIFT 0
-#define BCHP_CLKGEN_PLL_MOCA_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *PLL_MOCA_PLL_SSC_MODE_CONTROL_LOW - Lower bits of Spread Spectrum mode control
- ***************************************************************************/
-/* CLKGEN :: PLL_MOCA_PLL_SSC_MODE_CONTROL_LOW :: reserved0 [31:23] */
-#define BCHP_CLKGEN_PLL_MOCA_PLL_SSC_MODE_CONTROL_LOW_reserved0_MASK 0xff800000
-#define BCHP_CLKGEN_PLL_MOCA_PLL_SSC_MODE_CONTROL_LOW_reserved0_SHIFT 23
-
-/* CLKGEN :: PLL_MOCA_PLL_SSC_MODE_CONTROL_LOW :: SSC_MODE [22:22] */
-#define BCHP_CLKGEN_PLL_MOCA_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_MASK 0x00400000
-#define BCHP_CLKGEN_PLL_MOCA_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_SHIFT 22
-#define BCHP_CLKGEN_PLL_MOCA_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_MOCA_PLL_SSC_MODE_CONTROL_LOW :: SSC_LIMIT [21:00] */
-#define BCHP_CLKGEN_PLL_MOCA_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_MASK 0x003fffff
-#define BCHP_CLKGEN_PLL_MOCA_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_SHIFT 0
-#define BCHP_CLKGEN_PLL_MOCA_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_DEFAULT 0x00000000
-
-/***************************************************************************
- *PLL_MOCA_PLL_STATUS - Status
- ***************************************************************************/
-/* CLKGEN :: PLL_MOCA_PLL_STATUS :: reserved0 [31:12] */
-#define BCHP_CLKGEN_PLL_MOCA_PLL_STATUS_reserved0_MASK 0xfffff000
-#define BCHP_CLKGEN_PLL_MOCA_PLL_STATUS_reserved0_SHIFT 12
-
-/* CLKGEN :: PLL_MOCA_PLL_STATUS :: TEST_STATUS [11:00] */
-#define BCHP_CLKGEN_PLL_MOCA_PLL_STATUS_TEST_STATUS_MASK 0x00000fff
-#define BCHP_CLKGEN_PLL_MOCA_PLL_STATUS_TEST_STATUS_SHIFT 0
-
-/***************************************************************************
- *PLL_NETWORK_PLL_CHANNEL_CTRL_CH_0 - PLL CHANNEL control CH 0
- ***************************************************************************/
-/* CLKGEN :: PLL_NETWORK_PLL_CHANNEL_CTRL_CH_0 :: reserved0 [31:11] */
-#define BCHP_CLKGEN_PLL_NETWORK_PLL_CHANNEL_CTRL_CH_0_reserved0_MASK 0xfffff800
-#define BCHP_CLKGEN_PLL_NETWORK_PLL_CHANNEL_CTRL_CH_0_reserved0_SHIFT 11
-
-/* CLKGEN :: PLL_NETWORK_PLL_CHANNEL_CTRL_CH_0 :: POST_DIVIDER_HOLD_CH0 [10:10] */
-#define BCHP_CLKGEN_PLL_NETWORK_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_MASK 0x00000400
-#define BCHP_CLKGEN_PLL_NETWORK_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_SHIFT 10
-#define BCHP_CLKGEN_PLL_NETWORK_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_NETWORK_PLL_CHANNEL_CTRL_CH_0 :: PHASE_OFFSET_CH0 [09:09] */
-#define BCHP_CLKGEN_PLL_NETWORK_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_MASK 0x00000200
-#define BCHP_CLKGEN_PLL_NETWORK_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_SHIFT 9
-#define BCHP_CLKGEN_PLL_NETWORK_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_NETWORK_PLL_CHANNEL_CTRL_CH_0 :: MDIV_CH0 [08:01] */
-#define BCHP_CLKGEN_PLL_NETWORK_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_MASK 0x000001fe
-#define BCHP_CLKGEN_PLL_NETWORK_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_SHIFT 1
-#define BCHP_CLKGEN_PLL_NETWORK_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_DEFAULT 0x00000009
-
-/* CLKGEN :: PLL_NETWORK_PLL_CHANNEL_CTRL_CH_0 :: CLOCK_DIS_CH0 [00:00] */
-#define BCHP_CLKGEN_PLL_NETWORK_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_MASK 0x00000001
-#define BCHP_CLKGEN_PLL_NETWORK_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_SHIFT 0
-#define BCHP_CLKGEN_PLL_NETWORK_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_DEFAULT 0x00000000
-
-/***************************************************************************
- *PLL_NETWORK_PLL_CHANNEL_CTRL_CH_1 - PLL CHANNEL control CH 1
- ***************************************************************************/
-/* CLKGEN :: PLL_NETWORK_PLL_CHANNEL_CTRL_CH_1 :: reserved0 [31:11] */
-#define BCHP_CLKGEN_PLL_NETWORK_PLL_CHANNEL_CTRL_CH_1_reserved0_MASK 0xfffff800
-#define BCHP_CLKGEN_PLL_NETWORK_PLL_CHANNEL_CTRL_CH_1_reserved0_SHIFT 11
-
-/* CLKGEN :: PLL_NETWORK_PLL_CHANNEL_CTRL_CH_1 :: POST_DIVIDER_HOLD_CH1 [10:10] */
-#define BCHP_CLKGEN_PLL_NETWORK_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_MASK 0x00000400
-#define BCHP_CLKGEN_PLL_NETWORK_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_SHIFT 10
-#define BCHP_CLKGEN_PLL_NETWORK_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_NETWORK_PLL_CHANNEL_CTRL_CH_1 :: PHASE_OFFSET_CH1 [09:09] */
-#define BCHP_CLKGEN_PLL_NETWORK_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_MASK 0x00000200
-#define BCHP_CLKGEN_PLL_NETWORK_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_SHIFT 9
-#define BCHP_CLKGEN_PLL_NETWORK_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_NETWORK_PLL_CHANNEL_CTRL_CH_1 :: MDIV_CH1 [08:01] */
-#define BCHP_CLKGEN_PLL_NETWORK_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_MASK 0x000001fe
-#define BCHP_CLKGEN_PLL_NETWORK_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_SHIFT 1
-#define BCHP_CLKGEN_PLL_NETWORK_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_DEFAULT 0x00000012
-
-/* CLKGEN :: PLL_NETWORK_PLL_CHANNEL_CTRL_CH_1 :: CLOCK_DIS_CH1 [00:00] */
-#define BCHP_CLKGEN_PLL_NETWORK_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_MASK 0x00000001
-#define BCHP_CLKGEN_PLL_NETWORK_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_SHIFT 0
-#define BCHP_CLKGEN_PLL_NETWORK_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_DEFAULT 0x00000000
-
-/***************************************************************************
- *PLL_NETWORK_PLL_CHANNEL_CTRL_CH_2 - PLL CHANNEL control CH 2
- ***************************************************************************/
-/* CLKGEN :: PLL_NETWORK_PLL_CHANNEL_CTRL_CH_2 :: reserved0 [31:11] */
-#define BCHP_CLKGEN_PLL_NETWORK_PLL_CHANNEL_CTRL_CH_2_reserved0_MASK 0xfffff800
-#define BCHP_CLKGEN_PLL_NETWORK_PLL_CHANNEL_CTRL_CH_2_reserved0_SHIFT 11
-
-/* CLKGEN :: PLL_NETWORK_PLL_CHANNEL_CTRL_CH_2 :: POST_DIVIDER_HOLD_CH2 [10:10] */
-#define BCHP_CLKGEN_PLL_NETWORK_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_HOLD_CH2_MASK 0x00000400
-#define BCHP_CLKGEN_PLL_NETWORK_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_HOLD_CH2_SHIFT 10
-#define BCHP_CLKGEN_PLL_NETWORK_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_HOLD_CH2_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_NETWORK_PLL_CHANNEL_CTRL_CH_2 :: PHASE_OFFSET_CH2 [09:09] */
-#define BCHP_CLKGEN_PLL_NETWORK_PLL_CHANNEL_CTRL_CH_2_PHASE_OFFSET_CH2_MASK 0x00000200
-#define BCHP_CLKGEN_PLL_NETWORK_PLL_CHANNEL_CTRL_CH_2_PHASE_OFFSET_CH2_SHIFT 9
-#define BCHP_CLKGEN_PLL_NETWORK_PLL_CHANNEL_CTRL_CH_2_PHASE_OFFSET_CH2_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_NETWORK_PLL_CHANNEL_CTRL_CH_2 :: MDIV_CH2 [08:01] */
-#define BCHP_CLKGEN_PLL_NETWORK_PLL_CHANNEL_CTRL_CH_2_MDIV_CH2_MASK 0x000001fe
-#define BCHP_CLKGEN_PLL_NETWORK_PLL_CHANNEL_CTRL_CH_2_MDIV_CH2_SHIFT 1
-#define BCHP_CLKGEN_PLL_NETWORK_PLL_CHANNEL_CTRL_CH_2_MDIV_CH2_DEFAULT 0x00000053
-
-/* CLKGEN :: PLL_NETWORK_PLL_CHANNEL_CTRL_CH_2 :: CLOCK_DIS_CH2 [00:00] */
-#define BCHP_CLKGEN_PLL_NETWORK_PLL_CHANNEL_CTRL_CH_2_CLOCK_DIS_CH2_MASK 0x00000001
-#define BCHP_CLKGEN_PLL_NETWORK_PLL_CHANNEL_CTRL_CH_2_CLOCK_DIS_CH2_SHIFT 0
-#define BCHP_CLKGEN_PLL_NETWORK_PLL_CHANNEL_CTRL_CH_2_CLOCK_DIS_CH2_DEFAULT 0x00000000
-
-/***************************************************************************
- *PLL_NETWORK_PLL_DIV - Pre multiplier
- ***************************************************************************/
-/* CLKGEN :: PLL_NETWORK_PLL_DIV :: reserved0 [31:14] */
-#define BCHP_CLKGEN_PLL_NETWORK_PLL_DIV_reserved0_MASK 0xffffc000
-#define BCHP_CLKGEN_PLL_NETWORK_PLL_DIV_reserved0_SHIFT 14
-
-/* CLKGEN :: PLL_NETWORK_PLL_DIV :: PDIV [13:10] */
-#define BCHP_CLKGEN_PLL_NETWORK_PLL_DIV_PDIV_MASK 0x00003c00
-#define BCHP_CLKGEN_PLL_NETWORK_PLL_DIV_PDIV_SHIFT 10
-#define BCHP_CLKGEN_PLL_NETWORK_PLL_DIV_PDIV_DEFAULT 0x00000003
-
-/* CLKGEN :: PLL_NETWORK_PLL_DIV :: NDIV_INT [09:00] */
-#define BCHP_CLKGEN_PLL_NETWORK_PLL_DIV_NDIV_INT_MASK 0x000003ff
-#define BCHP_CLKGEN_PLL_NETWORK_PLL_DIV_NDIV_INT_SHIFT 0
-#define BCHP_CLKGEN_PLL_NETWORK_PLL_DIV_NDIV_INT_DEFAULT 0x0000007d
-
-/***************************************************************************
- *PLL_NETWORK_PLL_GAIN - PLL GAIN
- ***************************************************************************/
-/* CLKGEN :: PLL_NETWORK_PLL_GAIN :: reserved0 [31:10] */
-#define BCHP_CLKGEN_PLL_NETWORK_PLL_GAIN_reserved0_MASK 0xfffffc00
-#define BCHP_CLKGEN_PLL_NETWORK_PLL_GAIN_reserved0_SHIFT 10
-
-/* CLKGEN :: PLL_NETWORK_PLL_GAIN :: LOOP_GAIN_PROPORTIONAL_IN_PHASE [09:06] */
-#define BCHP_CLKGEN_PLL_NETWORK_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_MASK 0x000003c0
-#define BCHP_CLKGEN_PLL_NETWORK_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_SHIFT 6
-#define BCHP_CLKGEN_PLL_NETWORK_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_DEFAULT 0x00000003
-
-/* CLKGEN :: PLL_NETWORK_PLL_GAIN :: LOOP_GAIN_IN_FREQ [05:03] */
-#define BCHP_CLKGEN_PLL_NETWORK_PLL_GAIN_LOOP_GAIN_IN_FREQ_MASK 0x00000038
-#define BCHP_CLKGEN_PLL_NETWORK_PLL_GAIN_LOOP_GAIN_IN_FREQ_SHIFT 3
-#define BCHP_CLKGEN_PLL_NETWORK_PLL_GAIN_LOOP_GAIN_IN_FREQ_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_NETWORK_PLL_GAIN :: LOOP_GAIN_INTEGRATOR_IN_PHASE [02:00] */
-#define BCHP_CLKGEN_PLL_NETWORK_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_MASK 0x00000007
-#define BCHP_CLKGEN_PLL_NETWORK_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_SHIFT 0
-#define BCHP_CLKGEN_PLL_NETWORK_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_DEFAULT 0x00000002
-
-/***************************************************************************
- *PLL_NETWORK_PLL_LDO_PWRON - LDO Power on
- ***************************************************************************/
-/* CLKGEN :: PLL_NETWORK_PLL_LDO_PWRON :: reserved0 [31:01] */
-#define BCHP_CLKGEN_PLL_NETWORK_PLL_LDO_PWRON_reserved0_MASK 0xfffffffe
-#define BCHP_CLKGEN_PLL_NETWORK_PLL_LDO_PWRON_reserved0_SHIFT 1
-
-/* CLKGEN :: PLL_NETWORK_PLL_LDO_PWRON :: LDO_PWRON_PLL [00:00] */
-#define BCHP_CLKGEN_PLL_NETWORK_PLL_LDO_PWRON_LDO_PWRON_PLL_MASK 0x00000001
-#define BCHP_CLKGEN_PLL_NETWORK_PLL_LDO_PWRON_LDO_PWRON_PLL_SHIFT 0
-#define BCHP_CLKGEN_PLL_NETWORK_PLL_LDO_PWRON_LDO_PWRON_PLL_DEFAULT 0x00000001
-
-/***************************************************************************
- *PLL_NETWORK_PLL_LOCK_STATUS - Lock Status
- ***************************************************************************/
-/* CLKGEN :: PLL_NETWORK_PLL_LOCK_STATUS :: reserved0 [31:02] */
-#define BCHP_CLKGEN_PLL_NETWORK_PLL_LOCK_STATUS_reserved0_MASK 0xfffffffc
-#define BCHP_CLKGEN_PLL_NETWORK_PLL_LOCK_STATUS_reserved0_SHIFT 2
-
-/* CLKGEN :: PLL_NETWORK_PLL_LOCK_STATUS :: LOCK_LOST [01:01] */
-#define BCHP_CLKGEN_PLL_NETWORK_PLL_LOCK_STATUS_LOCK_LOST_MASK 0x00000002
-#define BCHP_CLKGEN_PLL_NETWORK_PLL_LOCK_STATUS_LOCK_LOST_SHIFT 1
-
-/* CLKGEN :: PLL_NETWORK_PLL_LOCK_STATUS :: LOCK [00:00] */
-#define BCHP_CLKGEN_PLL_NETWORK_PLL_LOCK_STATUS_LOCK_MASK 0x00000001
-#define BCHP_CLKGEN_PLL_NETWORK_PLL_LOCK_STATUS_LOCK_SHIFT 0
-
-/***************************************************************************
- *PLL_NETWORK_PLL_MISC - Mscellaneous control bus.
- ***************************************************************************/
-/* CLKGEN :: PLL_NETWORK_PLL_MISC :: VCO_RANGE [31:30] */
-#define BCHP_CLKGEN_PLL_NETWORK_PLL_MISC_VCO_RANGE_MASK 0xc0000000
-#define BCHP_CLKGEN_PLL_NETWORK_PLL_MISC_VCO_RANGE_SHIFT 30
-#define BCHP_CLKGEN_PLL_NETWORK_PLL_MISC_VCO_RANGE_DEFAULT 0x00000002
-
-/* CLKGEN :: PLL_NETWORK_PLL_MISC :: VCO_FB_DIV2 [29:29] */
-#define BCHP_CLKGEN_PLL_NETWORK_PLL_MISC_VCO_FB_DIV2_MASK 0x20000000
-#define BCHP_CLKGEN_PLL_NETWORK_PLL_MISC_VCO_FB_DIV2_SHIFT 29
-#define BCHP_CLKGEN_PLL_NETWORK_PLL_MISC_VCO_FB_DIV2_DEFAULT 0x00000001
-
-/* CLKGEN :: PLL_NETWORK_PLL_MISC :: STAT_UPDATE [28:28] */
-#define BCHP_CLKGEN_PLL_NETWORK_PLL_MISC_STAT_UPDATE_MASK 0x10000000
-#define BCHP_CLKGEN_PLL_NETWORK_PLL_MISC_STAT_UPDATE_SHIFT 28
-#define BCHP_CLKGEN_PLL_NETWORK_PLL_MISC_STAT_UPDATE_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_NETWORK_PLL_MISC :: STAT_SELECT [27:25] */
-#define BCHP_CLKGEN_PLL_NETWORK_PLL_MISC_STAT_SELECT_MASK 0x0e000000
-#define BCHP_CLKGEN_PLL_NETWORK_PLL_MISC_STAT_SELECT_SHIFT 25
-#define BCHP_CLKGEN_PLL_NETWORK_PLL_MISC_STAT_SELECT_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_NETWORK_PLL_MISC :: STAT_RESET [24:24] */
-#define BCHP_CLKGEN_PLL_NETWORK_PLL_MISC_STAT_RESET_MASK 0x01000000
-#define BCHP_CLKGEN_PLL_NETWORK_PLL_MISC_STAT_RESET_SHIFT 24
-#define BCHP_CLKGEN_PLL_NETWORK_PLL_MISC_STAT_RESET_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_NETWORK_PLL_MISC :: STAT_MODE [23:22] */
-#define BCHP_CLKGEN_PLL_NETWORK_PLL_MISC_STAT_MODE_MASK 0x00c00000
-#define BCHP_CLKGEN_PLL_NETWORK_PLL_MISC_STAT_MODE_SHIFT 22
-#define BCHP_CLKGEN_PLL_NETWORK_PLL_MISC_STAT_MODE_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_NETWORK_PLL_MISC :: PWM_RATE [21:20] */
-#define BCHP_CLKGEN_PLL_NETWORK_PLL_MISC_PWM_RATE_MASK 0x00300000
-#define BCHP_CLKGEN_PLL_NETWORK_PLL_MISC_PWM_RATE_SHIFT 20
-#define BCHP_CLKGEN_PLL_NETWORK_PLL_MISC_PWM_RATE_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_NETWORK_PLL_MISC :: POST_CTRL_RESETB [19:18] */
-#define BCHP_CLKGEN_PLL_NETWORK_PLL_MISC_POST_CTRL_RESETB_MASK 0x000c0000
-#define BCHP_CLKGEN_PLL_NETWORK_PLL_MISC_POST_CTRL_RESETB_SHIFT 18
-#define BCHP_CLKGEN_PLL_NETWORK_PLL_MISC_POST_CTRL_RESETB_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_NETWORK_PLL_MISC :: PLLRESERVED2 [17:16] */
-#define BCHP_CLKGEN_PLL_NETWORK_PLL_MISC_PLLRESERVED2_MASK 0x00030000
-#define BCHP_CLKGEN_PLL_NETWORK_PLL_MISC_PLLRESERVED2_SHIFT 16
-#define BCHP_CLKGEN_PLL_NETWORK_PLL_MISC_PLLRESERVED2_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_NETWORK_PLL_MISC :: PLLRESERVED1 [15:15] */
-#define BCHP_CLKGEN_PLL_NETWORK_PLL_MISC_PLLRESERVED1_MASK 0x00008000
-#define BCHP_CLKGEN_PLL_NETWORK_PLL_MISC_PLLRESERVED1_SHIFT 15
-#define BCHP_CLKGEN_PLL_NETWORK_PLL_MISC_PLLRESERVED1_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_NETWORK_PLL_MISC :: NDIV_RELOCK [14:14] */
-#define BCHP_CLKGEN_PLL_NETWORK_PLL_MISC_NDIV_RELOCK_MASK 0x00004000
-#define BCHP_CLKGEN_PLL_NETWORK_PLL_MISC_NDIV_RELOCK_SHIFT 14
-#define BCHP_CLKGEN_PLL_NETWORK_PLL_MISC_NDIV_RELOCK_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_NETWORK_PLL_MISC :: FAST_LOCK [13:13] */
-#define BCHP_CLKGEN_PLL_NETWORK_PLL_MISC_FAST_LOCK_MASK 0x00002000
-#define BCHP_CLKGEN_PLL_NETWORK_PLL_MISC_FAST_LOCK_SHIFT 13
-#define BCHP_CLKGEN_PLL_NETWORK_PLL_MISC_FAST_LOCK_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_NETWORK_PLL_MISC :: DCO_CTRL_BYPASS_ENABLE [12:12] */
-#define BCHP_CLKGEN_PLL_NETWORK_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_MASK 0x00001000
-#define BCHP_CLKGEN_PLL_NETWORK_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_SHIFT 12
-#define BCHP_CLKGEN_PLL_NETWORK_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_NETWORK_PLL_MISC :: DCO_CTRL_BYPASS [11:00] */
-#define BCHP_CLKGEN_PLL_NETWORK_PLL_MISC_DCO_CTRL_BYPASS_MASK 0x00000fff
-#define BCHP_CLKGEN_PLL_NETWORK_PLL_MISC_DCO_CTRL_BYPASS_SHIFT 0
-#define BCHP_CLKGEN_PLL_NETWORK_PLL_MISC_DCO_CTRL_BYPASS_DEFAULT 0x00000000
-
-/***************************************************************************
- *PLL_NETWORK_PLL_MISC2 - Mscellaneous control bus continued.
- ***************************************************************************/
-/* CLKGEN :: PLL_NETWORK_PLL_MISC2 :: PLLRESERVED0 [31:02] */
-#define BCHP_CLKGEN_PLL_NETWORK_PLL_MISC2_PLLRESERVED0_MASK 0xfffffffc
-#define BCHP_CLKGEN_PLL_NETWORK_PLL_MISC2_PLLRESERVED0_SHIFT 2
-#define BCHP_CLKGEN_PLL_NETWORK_PLL_MISC2_PLLRESERVED0_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_NETWORK_PLL_MISC2 :: LDO [01:00] */
-#define BCHP_CLKGEN_PLL_NETWORK_PLL_MISC2_LDO_MASK 0x00000003
-#define BCHP_CLKGEN_PLL_NETWORK_PLL_MISC2_LDO_SHIFT 0
-#define BCHP_CLKGEN_PLL_NETWORK_PLL_MISC2_LDO_DEFAULT 0x00000001
-
-/***************************************************************************
- *PLL_NETWORK_PLL_PWRON - Poweron
- ***************************************************************************/
-/* CLKGEN :: PLL_NETWORK_PLL_PWRON :: reserved0 [31:01] */
-#define BCHP_CLKGEN_PLL_NETWORK_PLL_PWRON_reserved0_MASK 0xfffffffe
-#define BCHP_CLKGEN_PLL_NETWORK_PLL_PWRON_reserved0_SHIFT 1
-
-/* CLKGEN :: PLL_NETWORK_PLL_PWRON :: PWRON_PLL [00:00] */
-#define BCHP_CLKGEN_PLL_NETWORK_PLL_PWRON_PWRON_PLL_MASK 0x00000001
-#define BCHP_CLKGEN_PLL_NETWORK_PLL_PWRON_PWRON_PLL_SHIFT 0
-#define BCHP_CLKGEN_PLL_NETWORK_PLL_PWRON_PWRON_PLL_DEFAULT 0x00000001
-
-/***************************************************************************
- *PLL_NETWORK_PLL_RESET - Resets
- ***************************************************************************/
-/* CLKGEN :: PLL_NETWORK_PLL_RESET :: reserved0 [31:02] */
-#define BCHP_CLKGEN_PLL_NETWORK_PLL_RESET_reserved0_MASK 0xfffffffc
-#define BCHP_CLKGEN_PLL_NETWORK_PLL_RESET_reserved0_SHIFT 2
-
-/* CLKGEN :: PLL_NETWORK_PLL_RESET :: RESETD [01:01] */
-#define BCHP_CLKGEN_PLL_NETWORK_PLL_RESET_RESETD_MASK 0x00000002
-#define BCHP_CLKGEN_PLL_NETWORK_PLL_RESET_RESETD_SHIFT 1
-#define BCHP_CLKGEN_PLL_NETWORK_PLL_RESET_RESETD_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_NETWORK_PLL_RESET :: RESETA [00:00] */
-#define BCHP_CLKGEN_PLL_NETWORK_PLL_RESET_RESETA_MASK 0x00000001
-#define BCHP_CLKGEN_PLL_NETWORK_PLL_RESET_RESETA_SHIFT 0
-#define BCHP_CLKGEN_PLL_NETWORK_PLL_RESET_RESETA_DEFAULT 0x00000000
-
-/***************************************************************************
- *PLL_NETWORK_PLL_SSC_MODE_CONTROL_HIGH - Higher bits of Spread Spectrum mode control
- ***************************************************************************/
-/* CLKGEN :: PLL_NETWORK_PLL_SSC_MODE_CONTROL_HIGH :: reserved0 [31:16] */
-#define BCHP_CLKGEN_PLL_NETWORK_PLL_SSC_MODE_CONTROL_HIGH_reserved0_MASK 0xffff0000
-#define BCHP_CLKGEN_PLL_NETWORK_PLL_SSC_MODE_CONTROL_HIGH_reserved0_SHIFT 16
-
-/* CLKGEN :: PLL_NETWORK_PLL_SSC_MODE_CONTROL_HIGH :: SSC_STEP [15:00] */
-#define BCHP_CLKGEN_PLL_NETWORK_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_MASK 0x0000ffff
-#define BCHP_CLKGEN_PLL_NETWORK_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_SHIFT 0
-#define BCHP_CLKGEN_PLL_NETWORK_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *PLL_NETWORK_PLL_SSC_MODE_CONTROL_LOW - Lower bits of Spread Spectrum mode control
- ***************************************************************************/
-/* CLKGEN :: PLL_NETWORK_PLL_SSC_MODE_CONTROL_LOW :: reserved0 [31:23] */
-#define BCHP_CLKGEN_PLL_NETWORK_PLL_SSC_MODE_CONTROL_LOW_reserved0_MASK 0xff800000
-#define BCHP_CLKGEN_PLL_NETWORK_PLL_SSC_MODE_CONTROL_LOW_reserved0_SHIFT 23
-
-/* CLKGEN :: PLL_NETWORK_PLL_SSC_MODE_CONTROL_LOW :: SSC_MODE [22:22] */
-#define BCHP_CLKGEN_PLL_NETWORK_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_MASK 0x00400000
-#define BCHP_CLKGEN_PLL_NETWORK_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_SHIFT 22
-#define BCHP_CLKGEN_PLL_NETWORK_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_NETWORK_PLL_SSC_MODE_CONTROL_LOW :: SSC_LIMIT [21:00] */
-#define BCHP_CLKGEN_PLL_NETWORK_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_MASK 0x003fffff
-#define BCHP_CLKGEN_PLL_NETWORK_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_SHIFT 0
-#define BCHP_CLKGEN_PLL_NETWORK_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_DEFAULT 0x00000000
-
-/***************************************************************************
- *PLL_NETWORK_PLL_STATUS - Status
- ***************************************************************************/
-/* CLKGEN :: PLL_NETWORK_PLL_STATUS :: reserved0 [31:12] */
-#define BCHP_CLKGEN_PLL_NETWORK_PLL_STATUS_reserved0_MASK 0xfffff000
-#define BCHP_CLKGEN_PLL_NETWORK_PLL_STATUS_reserved0_SHIFT 12
-
-/* CLKGEN :: PLL_NETWORK_PLL_STATUS :: TEST_STATUS [11:00] */
-#define BCHP_CLKGEN_PLL_NETWORK_PLL_STATUS_TEST_STATUS_MASK 0x00000fff
-#define BCHP_CLKGEN_PLL_NETWORK_PLL_STATUS_TEST_STATUS_SHIFT 0
-
-/***************************************************************************
- *PLL_RAAGA_PLL_CHANNEL_CTRL_CH_0 - PLL CHANNEL control CH 0
- ***************************************************************************/
-/* CLKGEN :: PLL_RAAGA_PLL_CHANNEL_CTRL_CH_0 :: reserved0 [31:11] */
-#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_0_reserved0_MASK 0xfffff800
-#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_0_reserved0_SHIFT 11
-
-/* CLKGEN :: PLL_RAAGA_PLL_CHANNEL_CTRL_CH_0 :: POST_DIVIDER_HOLD_CH0 [10:10] */
-#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_MASK 0x00000400
-#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_SHIFT 10
-#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_RAAGA_PLL_CHANNEL_CTRL_CH_0 :: PHASE_OFFSET_CH0 [09:09] */
-#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_MASK 0x00000200
-#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_SHIFT 9
-#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_RAAGA_PLL_CHANNEL_CTRL_CH_0 :: MDIV_CH0 [08:01] */
-#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_MASK 0x000001fe
-#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_SHIFT 1
-#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_DEFAULT 0x00000007
-
-/* CLKGEN :: PLL_RAAGA_PLL_CHANNEL_CTRL_CH_0 :: CLOCK_DIS_CH0 [00:00] */
-#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_MASK 0x00000001
-#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_SHIFT 0
-#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_DEFAULT 0x00000000
-
-/***************************************************************************
- *PLL_RAAGA_PLL_CHANNEL_CTRL_CH_3 - PLL CHANNEL control CH 3
- ***************************************************************************/
-/* CLKGEN :: PLL_RAAGA_PLL_CHANNEL_CTRL_CH_3 :: reserved0 [31:11] */
-#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_3_reserved0_MASK 0xfffff800
-#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_3_reserved0_SHIFT 11
-
-/* CLKGEN :: PLL_RAAGA_PLL_CHANNEL_CTRL_CH_3 :: POST_DIVIDER_HOLD_CH3 [10:10] */
-#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_HOLD_CH3_MASK 0x00000400
-#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_HOLD_CH3_SHIFT 10
-#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_HOLD_CH3_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_RAAGA_PLL_CHANNEL_CTRL_CH_3 :: PHASE_OFFSET_CH3 [09:09] */
-#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_3_PHASE_OFFSET_CH3_MASK 0x00000200
-#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_3_PHASE_OFFSET_CH3_SHIFT 9
-#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_3_PHASE_OFFSET_CH3_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_RAAGA_PLL_CHANNEL_CTRL_CH_3 :: MDIV_CH3 [08:01] */
-#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_3_MDIV_CH3_MASK 0x000001fe
-#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_3_MDIV_CH3_SHIFT 1
-#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_3_MDIV_CH3_DEFAULT 0x0000000b
-
-/* CLKGEN :: PLL_RAAGA_PLL_CHANNEL_CTRL_CH_3 :: CLOCK_DIS_CH3 [00:00] */
-#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_3_CLOCK_DIS_CH3_MASK 0x00000001
-#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_3_CLOCK_DIS_CH3_SHIFT 0
-#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_3_CLOCK_DIS_CH3_DEFAULT 0x00000000
-
-/***************************************************************************
- *PLL_RAAGA_PLL_CHANNEL_CTRL_CH_4 - PLL CHANNEL control CH 4
- ***************************************************************************/
-/* CLKGEN :: PLL_RAAGA_PLL_CHANNEL_CTRL_CH_4 :: reserved0 [31:11] */
-#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_4_reserved0_MASK 0xfffff800
-#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_4_reserved0_SHIFT 11
-
-/* CLKGEN :: PLL_RAAGA_PLL_CHANNEL_CTRL_CH_4 :: POST_DIVIDER_HOLD_CH4 [10:10] */
-#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_4_POST_DIVIDER_HOLD_CH4_MASK 0x00000400
-#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_4_POST_DIVIDER_HOLD_CH4_SHIFT 10
-#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_4_POST_DIVIDER_HOLD_CH4_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_RAAGA_PLL_CHANNEL_CTRL_CH_4 :: PHASE_OFFSET_CH4 [09:09] */
-#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_4_PHASE_OFFSET_CH4_MASK 0x00000200
-#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_4_PHASE_OFFSET_CH4_SHIFT 9
-#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_4_PHASE_OFFSET_CH4_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_RAAGA_PLL_CHANNEL_CTRL_CH_4 :: MDIV_CH4 [08:01] */
-#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_4_MDIV_CH4_MASK 0x000001fe
-#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_4_MDIV_CH4_SHIFT 1
-#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_4_MDIV_CH4_DEFAULT 0x00000064
-
-/* CLKGEN :: PLL_RAAGA_PLL_CHANNEL_CTRL_CH_4 :: CLOCK_DIS_CH4 [00:00] */
-#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_4_CLOCK_DIS_CH4_MASK 0x00000001
-#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_4_CLOCK_DIS_CH4_SHIFT 0
-#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_4_CLOCK_DIS_CH4_DEFAULT 0x00000001
-
-/***************************************************************************
- *PLL_RAAGA_PLL_DIV - Pre multiplier
- ***************************************************************************/
-/* CLKGEN :: PLL_RAAGA_PLL_DIV :: reserved0 [31:14] */
-#define BCHP_CLKGEN_PLL_RAAGA_PLL_DIV_reserved0_MASK 0xffffc000
-#define BCHP_CLKGEN_PLL_RAAGA_PLL_DIV_reserved0_SHIFT 14
-
-/* CLKGEN :: PLL_RAAGA_PLL_DIV :: PDIV [13:10] */
-#define BCHP_CLKGEN_PLL_RAAGA_PLL_DIV_PDIV_MASK 0x00003c00
-#define BCHP_CLKGEN_PLL_RAAGA_PLL_DIV_PDIV_SHIFT 10
-#define BCHP_CLKGEN_PLL_RAAGA_PLL_DIV_PDIV_DEFAULT 0x00000002
-
-/* CLKGEN :: PLL_RAAGA_PLL_DIV :: NDIV_INT [09:00] */
-#define BCHP_CLKGEN_PLL_RAAGA_PLL_DIV_NDIV_INT_MASK 0x000003ff
-#define BCHP_CLKGEN_PLL_RAAGA_PLL_DIV_NDIV_INT_SHIFT 0
-#define BCHP_CLKGEN_PLL_RAAGA_PLL_DIV_NDIV_INT_DEFAULT 0x0000008f
-
-/***************************************************************************
- *PLL_RAAGA_PLL_GAIN - PLL GAIN
- ***************************************************************************/
-/* CLKGEN :: PLL_RAAGA_PLL_GAIN :: reserved0 [31:10] */
-#define BCHP_CLKGEN_PLL_RAAGA_PLL_GAIN_reserved0_MASK 0xfffffc00
-#define BCHP_CLKGEN_PLL_RAAGA_PLL_GAIN_reserved0_SHIFT 10
-
-/* CLKGEN :: PLL_RAAGA_PLL_GAIN :: LOOP_GAIN_PROPORTIONAL_IN_PHASE [09:06] */
-#define BCHP_CLKGEN_PLL_RAAGA_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_MASK 0x000003c0
-#define BCHP_CLKGEN_PLL_RAAGA_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_SHIFT 6
-#define BCHP_CLKGEN_PLL_RAAGA_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_DEFAULT 0x00000003
-
-/* CLKGEN :: PLL_RAAGA_PLL_GAIN :: LOOP_GAIN_IN_FREQ [05:03] */
-#define BCHP_CLKGEN_PLL_RAAGA_PLL_GAIN_LOOP_GAIN_IN_FREQ_MASK 0x00000038
-#define BCHP_CLKGEN_PLL_RAAGA_PLL_GAIN_LOOP_GAIN_IN_FREQ_SHIFT 3
-#define BCHP_CLKGEN_PLL_RAAGA_PLL_GAIN_LOOP_GAIN_IN_FREQ_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_RAAGA_PLL_GAIN :: LOOP_GAIN_INTEGRATOR_IN_PHASE [02:00] */
-#define BCHP_CLKGEN_PLL_RAAGA_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_MASK 0x00000007
-#define BCHP_CLKGEN_PLL_RAAGA_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_SHIFT 0
-#define BCHP_CLKGEN_PLL_RAAGA_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_DEFAULT 0x00000002
-
-/***************************************************************************
- *PLL_RAAGA_PLL_LDO_PWRON - LDO Power on
- ***************************************************************************/
-/* CLKGEN :: PLL_RAAGA_PLL_LDO_PWRON :: reserved0 [31:01] */
-#define BCHP_CLKGEN_PLL_RAAGA_PLL_LDO_PWRON_reserved0_MASK 0xfffffffe
-#define BCHP_CLKGEN_PLL_RAAGA_PLL_LDO_PWRON_reserved0_SHIFT 1
-
-/* CLKGEN :: PLL_RAAGA_PLL_LDO_PWRON :: LDO_PWRON_PLL [00:00] */
-#define BCHP_CLKGEN_PLL_RAAGA_PLL_LDO_PWRON_LDO_PWRON_PLL_MASK 0x00000001
-#define BCHP_CLKGEN_PLL_RAAGA_PLL_LDO_PWRON_LDO_PWRON_PLL_SHIFT 0
-#define BCHP_CLKGEN_PLL_RAAGA_PLL_LDO_PWRON_LDO_PWRON_PLL_DEFAULT 0x00000001
-
-/***************************************************************************
- *PLL_RAAGA_PLL_LOCK_STATUS - Lock Status
- ***************************************************************************/
-/* CLKGEN :: PLL_RAAGA_PLL_LOCK_STATUS :: reserved0 [31:02] */
-#define BCHP_CLKGEN_PLL_RAAGA_PLL_LOCK_STATUS_reserved0_MASK 0xfffffffc
-#define BCHP_CLKGEN_PLL_RAAGA_PLL_LOCK_STATUS_reserved0_SHIFT 2
-
-/* CLKGEN :: PLL_RAAGA_PLL_LOCK_STATUS :: LOCK_LOST [01:01] */
-#define BCHP_CLKGEN_PLL_RAAGA_PLL_LOCK_STATUS_LOCK_LOST_MASK 0x00000002
-#define BCHP_CLKGEN_PLL_RAAGA_PLL_LOCK_STATUS_LOCK_LOST_SHIFT 1
-
-/* CLKGEN :: PLL_RAAGA_PLL_LOCK_STATUS :: LOCK [00:00] */
-#define BCHP_CLKGEN_PLL_RAAGA_PLL_LOCK_STATUS_LOCK_MASK 0x00000001
-#define BCHP_CLKGEN_PLL_RAAGA_PLL_LOCK_STATUS_LOCK_SHIFT 0
-
-/***************************************************************************
- *PLL_RAAGA_PLL_MISC - Mscellaneous control bus.
- ***************************************************************************/
-/* CLKGEN :: PLL_RAAGA_PLL_MISC :: VCO_RANGE [31:30] */
-#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_VCO_RANGE_MASK 0xc0000000
-#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_VCO_RANGE_SHIFT 30
-#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_VCO_RANGE_DEFAULT 0x00000002
-
-/* CLKGEN :: PLL_RAAGA_PLL_MISC :: VCO_FB_DIV2 [29:29] */
-#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_VCO_FB_DIV2_MASK 0x20000000
-#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_VCO_FB_DIV2_SHIFT 29
-#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_VCO_FB_DIV2_DEFAULT 0x00000001
-
-/* CLKGEN :: PLL_RAAGA_PLL_MISC :: STAT_UPDATE [28:28] */
-#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_STAT_UPDATE_MASK 0x10000000
-#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_STAT_UPDATE_SHIFT 28
-#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_STAT_UPDATE_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_RAAGA_PLL_MISC :: STAT_SELECT [27:25] */
-#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_STAT_SELECT_MASK 0x0e000000
-#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_STAT_SELECT_SHIFT 25
-#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_STAT_SELECT_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_RAAGA_PLL_MISC :: STAT_RESET [24:24] */
-#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_STAT_RESET_MASK 0x01000000
-#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_STAT_RESET_SHIFT 24
-#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_STAT_RESET_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_RAAGA_PLL_MISC :: STAT_MODE [23:22] */
-#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_STAT_MODE_MASK 0x00c00000
-#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_STAT_MODE_SHIFT 22
-#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_STAT_MODE_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_RAAGA_PLL_MISC :: PWM_RATE [21:20] */
-#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_PWM_RATE_MASK 0x00300000
-#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_PWM_RATE_SHIFT 20
-#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_PWM_RATE_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_RAAGA_PLL_MISC :: POST_CTRL_RESETB [19:18] */
-#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_POST_CTRL_RESETB_MASK 0x000c0000
-#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_POST_CTRL_RESETB_SHIFT 18
-#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_POST_CTRL_RESETB_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_RAAGA_PLL_MISC :: PLLRESERVED2 [17:16] */
-#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_PLLRESERVED2_MASK 0x00030000
-#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_PLLRESERVED2_SHIFT 16
-#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_PLLRESERVED2_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_RAAGA_PLL_MISC :: PLLRESERVED1 [15:15] */
-#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_PLLRESERVED1_MASK 0x00008000
-#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_PLLRESERVED1_SHIFT 15
-#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_PLLRESERVED1_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_RAAGA_PLL_MISC :: NDIV_RELOCK [14:14] */
-#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_NDIV_RELOCK_MASK 0x00004000
-#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_NDIV_RELOCK_SHIFT 14
-#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_NDIV_RELOCK_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_RAAGA_PLL_MISC :: FAST_LOCK [13:13] */
-#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_FAST_LOCK_MASK 0x00002000
-#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_FAST_LOCK_SHIFT 13
-#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_FAST_LOCK_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_RAAGA_PLL_MISC :: DCO_CTRL_BYPASS_ENABLE [12:12] */
-#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_MASK 0x00001000
-#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_SHIFT 12
-#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_RAAGA_PLL_MISC :: DCO_CTRL_BYPASS [11:00] */
-#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_DCO_CTRL_BYPASS_MASK 0x00000fff
-#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_DCO_CTRL_BYPASS_SHIFT 0
-#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_DCO_CTRL_BYPASS_DEFAULT 0x00000000
-
-/***************************************************************************
- *PLL_RAAGA_PLL_MISC2 - Mscellaneous control bus continued.
- ***************************************************************************/
-/* CLKGEN :: PLL_RAAGA_PLL_MISC2 :: PLLRESERVED0 [31:02] */
-#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC2_PLLRESERVED0_MASK 0xfffffffc
-#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC2_PLLRESERVED0_SHIFT 2
-#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC2_PLLRESERVED0_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_RAAGA_PLL_MISC2 :: LDO [01:00] */
-#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC2_LDO_MASK 0x00000003
-#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC2_LDO_SHIFT 0
-#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC2_LDO_DEFAULT 0x00000001
-
-/***************************************************************************
- *PLL_RAAGA_PLL_PWRON - Poweron
- ***************************************************************************/
-/* CLKGEN :: PLL_RAAGA_PLL_PWRON :: reserved0 [31:01] */
-#define BCHP_CLKGEN_PLL_RAAGA_PLL_PWRON_reserved0_MASK 0xfffffffe
-#define BCHP_CLKGEN_PLL_RAAGA_PLL_PWRON_reserved0_SHIFT 1
-
-/* CLKGEN :: PLL_RAAGA_PLL_PWRON :: PWRON_PLL [00:00] */
-#define BCHP_CLKGEN_PLL_RAAGA_PLL_PWRON_PWRON_PLL_MASK 0x00000001
-#define BCHP_CLKGEN_PLL_RAAGA_PLL_PWRON_PWRON_PLL_SHIFT 0
-#define BCHP_CLKGEN_PLL_RAAGA_PLL_PWRON_PWRON_PLL_DEFAULT 0x00000001
-
-/***************************************************************************
- *PLL_RAAGA_PLL_RESET - Resets
- ***************************************************************************/
-/* CLKGEN :: PLL_RAAGA_PLL_RESET :: reserved0 [31:02] */
-#define BCHP_CLKGEN_PLL_RAAGA_PLL_RESET_reserved0_MASK 0xfffffffc
-#define BCHP_CLKGEN_PLL_RAAGA_PLL_RESET_reserved0_SHIFT 2
-
-/* CLKGEN :: PLL_RAAGA_PLL_RESET :: RESETD [01:01] */
-#define BCHP_CLKGEN_PLL_RAAGA_PLL_RESET_RESETD_MASK 0x00000002
-#define BCHP_CLKGEN_PLL_RAAGA_PLL_RESET_RESETD_SHIFT 1
-#define BCHP_CLKGEN_PLL_RAAGA_PLL_RESET_RESETD_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_RAAGA_PLL_RESET :: RESETA [00:00] */
-#define BCHP_CLKGEN_PLL_RAAGA_PLL_RESET_RESETA_MASK 0x00000001
-#define BCHP_CLKGEN_PLL_RAAGA_PLL_RESET_RESETA_SHIFT 0
-#define BCHP_CLKGEN_PLL_RAAGA_PLL_RESET_RESETA_DEFAULT 0x00000000
-
-/***************************************************************************
- *PLL_RAAGA_PLL_SSC_MODE_CONTROL_HIGH - Higher bits of Spread Spectrum mode control
- ***************************************************************************/
-/* CLKGEN :: PLL_RAAGA_PLL_SSC_MODE_CONTROL_HIGH :: reserved0 [31:16] */
-#define BCHP_CLKGEN_PLL_RAAGA_PLL_SSC_MODE_CONTROL_HIGH_reserved0_MASK 0xffff0000
-#define BCHP_CLKGEN_PLL_RAAGA_PLL_SSC_MODE_CONTROL_HIGH_reserved0_SHIFT 16
-
-/* CLKGEN :: PLL_RAAGA_PLL_SSC_MODE_CONTROL_HIGH :: SSC_STEP [15:00] */
-#define BCHP_CLKGEN_PLL_RAAGA_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_MASK 0x0000ffff
-#define BCHP_CLKGEN_PLL_RAAGA_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_SHIFT 0
-#define BCHP_CLKGEN_PLL_RAAGA_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *PLL_RAAGA_PLL_SSC_MODE_CONTROL_LOW - Lower bits of Spread Spectrum mode control
- ***************************************************************************/
-/* CLKGEN :: PLL_RAAGA_PLL_SSC_MODE_CONTROL_LOW :: reserved0 [31:23] */
-#define BCHP_CLKGEN_PLL_RAAGA_PLL_SSC_MODE_CONTROL_LOW_reserved0_MASK 0xff800000
-#define BCHP_CLKGEN_PLL_RAAGA_PLL_SSC_MODE_CONTROL_LOW_reserved0_SHIFT 23
-
-/* CLKGEN :: PLL_RAAGA_PLL_SSC_MODE_CONTROL_LOW :: SSC_MODE [22:22] */
-#define BCHP_CLKGEN_PLL_RAAGA_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_MASK 0x00400000
-#define BCHP_CLKGEN_PLL_RAAGA_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_SHIFT 22
-#define BCHP_CLKGEN_PLL_RAAGA_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_RAAGA_PLL_SSC_MODE_CONTROL_LOW :: SSC_LIMIT [21:00] */
-#define BCHP_CLKGEN_PLL_RAAGA_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_MASK 0x003fffff
-#define BCHP_CLKGEN_PLL_RAAGA_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_SHIFT 0
-#define BCHP_CLKGEN_PLL_RAAGA_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_DEFAULT 0x00000000
-
-/***************************************************************************
- *PLL_RAAGA_PLL_STATUS - Status
- ***************************************************************************/
-/* CLKGEN :: PLL_RAAGA_PLL_STATUS :: reserved0 [31:12] */
-#define BCHP_CLKGEN_PLL_RAAGA_PLL_STATUS_reserved0_MASK 0xfffff000
-#define BCHP_CLKGEN_PLL_RAAGA_PLL_STATUS_reserved0_SHIFT 12
-
-/* CLKGEN :: PLL_RAAGA_PLL_STATUS :: TEST_STATUS [11:00] */
-#define BCHP_CLKGEN_PLL_RAAGA_PLL_STATUS_TEST_STATUS_MASK 0x00000fff
-#define BCHP_CLKGEN_PLL_RAAGA_PLL_STATUS_TEST_STATUS_SHIFT 0
-
-/***************************************************************************
- *PLL_SC0_PLL_CHANNEL_CTRL_CH_0 - PLL CHANNEL control CH 0
- ***************************************************************************/
-/* CLKGEN :: PLL_SC0_PLL_CHANNEL_CTRL_CH_0 :: reserved0 [31:11] */
-#define BCHP_CLKGEN_PLL_SC0_PLL_CHANNEL_CTRL_CH_0_reserved0_MASK 0xfffff800
-#define BCHP_CLKGEN_PLL_SC0_PLL_CHANNEL_CTRL_CH_0_reserved0_SHIFT 11
-
-/* CLKGEN :: PLL_SC0_PLL_CHANNEL_CTRL_CH_0 :: POST_DIVIDER_HOLD_CH0 [10:10] */
-#define BCHP_CLKGEN_PLL_SC0_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_MASK 0x00000400
-#define BCHP_CLKGEN_PLL_SC0_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_SHIFT 10
-#define BCHP_CLKGEN_PLL_SC0_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_SC0_PLL_CHANNEL_CTRL_CH_0 :: PHASE_OFFSET_CH0 [09:09] */
-#define BCHP_CLKGEN_PLL_SC0_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_MASK 0x00000200
-#define BCHP_CLKGEN_PLL_SC0_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_SHIFT 9
-#define BCHP_CLKGEN_PLL_SC0_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_SC0_PLL_CHANNEL_CTRL_CH_0 :: MDIV_CH0 [08:01] */
-#define BCHP_CLKGEN_PLL_SC0_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_MASK 0x000001fe
-#define BCHP_CLKGEN_PLL_SC0_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_SHIFT 1
-#define BCHP_CLKGEN_PLL_SC0_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_DEFAULT 0x00000030
-
-/* CLKGEN :: PLL_SC0_PLL_CHANNEL_CTRL_CH_0 :: CLOCK_DIS_CH0 [00:00] */
-#define BCHP_CLKGEN_PLL_SC0_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_MASK 0x00000001
-#define BCHP_CLKGEN_PLL_SC0_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_SHIFT 0
-#define BCHP_CLKGEN_PLL_SC0_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_DEFAULT 0x00000000
-
-/***************************************************************************
- *PLL_SC0_PLL_DIV - Pre multiplier
- ***************************************************************************/
-/* CLKGEN :: PLL_SC0_PLL_DIV :: reserved0 [31:14] */
-#define BCHP_CLKGEN_PLL_SC0_PLL_DIV_reserved0_MASK 0xffffc000
-#define BCHP_CLKGEN_PLL_SC0_PLL_DIV_reserved0_SHIFT 14
-
-/* CLKGEN :: PLL_SC0_PLL_DIV :: PDIV [13:10] */
-#define BCHP_CLKGEN_PLL_SC0_PLL_DIV_PDIV_MASK 0x00003c00
-#define BCHP_CLKGEN_PLL_SC0_PLL_DIV_PDIV_SHIFT 10
-#define BCHP_CLKGEN_PLL_SC0_PLL_DIV_PDIV_DEFAULT 0x00000002
-
-/* CLKGEN :: PLL_SC0_PLL_DIV :: NDIV_INT [09:00] */
-#define BCHP_CLKGEN_PLL_SC0_PLL_DIV_NDIV_INT_MASK 0x000003ff
-#define BCHP_CLKGEN_PLL_SC0_PLL_DIV_NDIV_INT_SHIFT 0
-#define BCHP_CLKGEN_PLL_SC0_PLL_DIV_NDIV_INT_DEFAULT 0x00000030
-
-/***************************************************************************
- *PLL_SC0_PLL_FRAC - Fractional
- ***************************************************************************/
-/* CLKGEN :: PLL_SC0_PLL_FRAC :: reserved0 [31:20] */
-#define BCHP_CLKGEN_PLL_SC0_PLL_FRAC_reserved0_MASK 0xfff00000
-#define BCHP_CLKGEN_PLL_SC0_PLL_FRAC_reserved0_SHIFT 20
-
-/* CLKGEN :: PLL_SC0_PLL_FRAC :: FRAC_CONTROL [19:00] */
-#define BCHP_CLKGEN_PLL_SC0_PLL_FRAC_FRAC_CONTROL_MASK 0x000fffff
-#define BCHP_CLKGEN_PLL_SC0_PLL_FRAC_FRAC_CONTROL_SHIFT 0
-#define BCHP_CLKGEN_PLL_SC0_PLL_FRAC_FRAC_CONTROL_DEFAULT 0x00000000
-
-/***************************************************************************
- *PLL_SC0_PLL_GAIN - PLL GAIN
- ***************************************************************************/
-/* CLKGEN :: PLL_SC0_PLL_GAIN :: reserved0 [31:10] */
-#define BCHP_CLKGEN_PLL_SC0_PLL_GAIN_reserved0_MASK 0xfffffc00
-#define BCHP_CLKGEN_PLL_SC0_PLL_GAIN_reserved0_SHIFT 10
-
-/* CLKGEN :: PLL_SC0_PLL_GAIN :: LOOP_GAIN_PROPORTIONAL_IN_PHASE [09:06] */
-#define BCHP_CLKGEN_PLL_SC0_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_MASK 0x000003c0
-#define BCHP_CLKGEN_PLL_SC0_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_SHIFT 6
-#define BCHP_CLKGEN_PLL_SC0_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_DEFAULT 0x00000005
-
-/* CLKGEN :: PLL_SC0_PLL_GAIN :: LOOP_GAIN_IN_FREQ [05:03] */
-#define BCHP_CLKGEN_PLL_SC0_PLL_GAIN_LOOP_GAIN_IN_FREQ_MASK 0x00000038
-#define BCHP_CLKGEN_PLL_SC0_PLL_GAIN_LOOP_GAIN_IN_FREQ_SHIFT 3
-#define BCHP_CLKGEN_PLL_SC0_PLL_GAIN_LOOP_GAIN_IN_FREQ_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_SC0_PLL_GAIN :: LOOP_GAIN_INTEGRATOR_IN_PHASE [02:00] */
-#define BCHP_CLKGEN_PLL_SC0_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_MASK 0x00000007
-#define BCHP_CLKGEN_PLL_SC0_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_SHIFT 0
-#define BCHP_CLKGEN_PLL_SC0_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_DEFAULT 0x00000002
-
-/***************************************************************************
- *PLL_SC0_PLL_LOCK_STATUS - Lock Status
- ***************************************************************************/
-/* CLKGEN :: PLL_SC0_PLL_LOCK_STATUS :: reserved0 [31:02] */
-#define BCHP_CLKGEN_PLL_SC0_PLL_LOCK_STATUS_reserved0_MASK 0xfffffffc
-#define BCHP_CLKGEN_PLL_SC0_PLL_LOCK_STATUS_reserved0_SHIFT 2
-
-/* CLKGEN :: PLL_SC0_PLL_LOCK_STATUS :: LOCK_LOST [01:01] */
-#define BCHP_CLKGEN_PLL_SC0_PLL_LOCK_STATUS_LOCK_LOST_MASK 0x00000002
-#define BCHP_CLKGEN_PLL_SC0_PLL_LOCK_STATUS_LOCK_LOST_SHIFT 1
-
-/* CLKGEN :: PLL_SC0_PLL_LOCK_STATUS :: LOCK [00:00] */
-#define BCHP_CLKGEN_PLL_SC0_PLL_LOCK_STATUS_LOCK_MASK 0x00000001
-#define BCHP_CLKGEN_PLL_SC0_PLL_LOCK_STATUS_LOCK_SHIFT 0
-
-/***************************************************************************
- *PLL_SC0_PLL_MISC - Mscellaneous control bus.
- ***************************************************************************/
-/* CLKGEN :: PLL_SC0_PLL_MISC :: VCO_RANGE [31:30] */
-#define BCHP_CLKGEN_PLL_SC0_PLL_MISC_VCO_RANGE_MASK 0xc0000000
-#define BCHP_CLKGEN_PLL_SC0_PLL_MISC_VCO_RANGE_SHIFT 30
-#define BCHP_CLKGEN_PLL_SC0_PLL_MISC_VCO_RANGE_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_SC0_PLL_MISC :: VCO_FB_DIV2 [29:29] */
-#define BCHP_CLKGEN_PLL_SC0_PLL_MISC_VCO_FB_DIV2_MASK 0x20000000
-#define BCHP_CLKGEN_PLL_SC0_PLL_MISC_VCO_FB_DIV2_SHIFT 29
-#define BCHP_CLKGEN_PLL_SC0_PLL_MISC_VCO_FB_DIV2_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_SC0_PLL_MISC :: STAT_UPDATE [28:28] */
-#define BCHP_CLKGEN_PLL_SC0_PLL_MISC_STAT_UPDATE_MASK 0x10000000
-#define BCHP_CLKGEN_PLL_SC0_PLL_MISC_STAT_UPDATE_SHIFT 28
-#define BCHP_CLKGEN_PLL_SC0_PLL_MISC_STAT_UPDATE_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_SC0_PLL_MISC :: STAT_SELECT [27:25] */
-#define BCHP_CLKGEN_PLL_SC0_PLL_MISC_STAT_SELECT_MASK 0x0e000000
-#define BCHP_CLKGEN_PLL_SC0_PLL_MISC_STAT_SELECT_SHIFT 25
-#define BCHP_CLKGEN_PLL_SC0_PLL_MISC_STAT_SELECT_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_SC0_PLL_MISC :: STAT_RESET [24:24] */
-#define BCHP_CLKGEN_PLL_SC0_PLL_MISC_STAT_RESET_MASK 0x01000000
-#define BCHP_CLKGEN_PLL_SC0_PLL_MISC_STAT_RESET_SHIFT 24
-#define BCHP_CLKGEN_PLL_SC0_PLL_MISC_STAT_RESET_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_SC0_PLL_MISC :: STAT_MODE [23:22] */
-#define BCHP_CLKGEN_PLL_SC0_PLL_MISC_STAT_MODE_MASK 0x00c00000
-#define BCHP_CLKGEN_PLL_SC0_PLL_MISC_STAT_MODE_SHIFT 22
-#define BCHP_CLKGEN_PLL_SC0_PLL_MISC_STAT_MODE_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_SC0_PLL_MISC :: PWM_RATE [21:20] */
-#define BCHP_CLKGEN_PLL_SC0_PLL_MISC_PWM_RATE_MASK 0x00300000
-#define BCHP_CLKGEN_PLL_SC0_PLL_MISC_PWM_RATE_SHIFT 20
-#define BCHP_CLKGEN_PLL_SC0_PLL_MISC_PWM_RATE_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_SC0_PLL_MISC :: POST_CTRL_RESETB [19:18] */
-#define BCHP_CLKGEN_PLL_SC0_PLL_MISC_POST_CTRL_RESETB_MASK 0x000c0000
-#define BCHP_CLKGEN_PLL_SC0_PLL_MISC_POST_CTRL_RESETB_SHIFT 18
-#define BCHP_CLKGEN_PLL_SC0_PLL_MISC_POST_CTRL_RESETB_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_SC0_PLL_MISC :: PLLRESERVED2 [17:16] */
-#define BCHP_CLKGEN_PLL_SC0_PLL_MISC_PLLRESERVED2_MASK 0x00030000
-#define BCHP_CLKGEN_PLL_SC0_PLL_MISC_PLLRESERVED2_SHIFT 16
-#define BCHP_CLKGEN_PLL_SC0_PLL_MISC_PLLRESERVED2_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_SC0_PLL_MISC :: PLLRESERVED1 [15:15] */
-#define BCHP_CLKGEN_PLL_SC0_PLL_MISC_PLLRESERVED1_MASK 0x00008000
-#define BCHP_CLKGEN_PLL_SC0_PLL_MISC_PLLRESERVED1_SHIFT 15
-#define BCHP_CLKGEN_PLL_SC0_PLL_MISC_PLLRESERVED1_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_SC0_PLL_MISC :: NDIV_RELOCK [14:14] */
-#define BCHP_CLKGEN_PLL_SC0_PLL_MISC_NDIV_RELOCK_MASK 0x00004000
-#define BCHP_CLKGEN_PLL_SC0_PLL_MISC_NDIV_RELOCK_SHIFT 14
-#define BCHP_CLKGEN_PLL_SC0_PLL_MISC_NDIV_RELOCK_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_SC0_PLL_MISC :: FAST_LOCK [13:13] */
-#define BCHP_CLKGEN_PLL_SC0_PLL_MISC_FAST_LOCK_MASK 0x00002000
-#define BCHP_CLKGEN_PLL_SC0_PLL_MISC_FAST_LOCK_SHIFT 13
-#define BCHP_CLKGEN_PLL_SC0_PLL_MISC_FAST_LOCK_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_SC0_PLL_MISC :: DCO_CTRL_BYPASS_ENABLE [12:12] */
-#define BCHP_CLKGEN_PLL_SC0_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_MASK 0x00001000
-#define BCHP_CLKGEN_PLL_SC0_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_SHIFT 12
-#define BCHP_CLKGEN_PLL_SC0_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_SC0_PLL_MISC :: DCO_CTRL_BYPASS [11:00] */
-#define BCHP_CLKGEN_PLL_SC0_PLL_MISC_DCO_CTRL_BYPASS_MASK 0x00000fff
-#define BCHP_CLKGEN_PLL_SC0_PLL_MISC_DCO_CTRL_BYPASS_SHIFT 0
-#define BCHP_CLKGEN_PLL_SC0_PLL_MISC_DCO_CTRL_BYPASS_DEFAULT 0x00000000
-
-/***************************************************************************
- *PLL_SC0_PLL_MISC2 - Mscellaneous control bus continued.
- ***************************************************************************/
-/* CLKGEN :: PLL_SC0_PLL_MISC2 :: PLLRESERVED0 [31:02] */
-#define BCHP_CLKGEN_PLL_SC0_PLL_MISC2_PLLRESERVED0_MASK 0xfffffffc
-#define BCHP_CLKGEN_PLL_SC0_PLL_MISC2_PLLRESERVED0_SHIFT 2
-#define BCHP_CLKGEN_PLL_SC0_PLL_MISC2_PLLRESERVED0_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_SC0_PLL_MISC2 :: LDO [01:00] */
-#define BCHP_CLKGEN_PLL_SC0_PLL_MISC2_LDO_MASK 0x00000003
-#define BCHP_CLKGEN_PLL_SC0_PLL_MISC2_LDO_SHIFT 0
-#define BCHP_CLKGEN_PLL_SC0_PLL_MISC2_LDO_DEFAULT 0x00000001
-
-/***************************************************************************
- *PLL_SC0_PLL_PWRON - Poweron
- ***************************************************************************/
-/* CLKGEN :: PLL_SC0_PLL_PWRON :: reserved0 [31:01] */
-#define BCHP_CLKGEN_PLL_SC0_PLL_PWRON_reserved0_MASK 0xfffffffe
-#define BCHP_CLKGEN_PLL_SC0_PLL_PWRON_reserved0_SHIFT 1
-
-/* CLKGEN :: PLL_SC0_PLL_PWRON :: PWRON_PLL [00:00] */
-#define BCHP_CLKGEN_PLL_SC0_PLL_PWRON_PWRON_PLL_MASK 0x00000001
-#define BCHP_CLKGEN_PLL_SC0_PLL_PWRON_PWRON_PLL_SHIFT 0
-#define BCHP_CLKGEN_PLL_SC0_PLL_PWRON_PWRON_PLL_DEFAULT 0x00000001
-
-/***************************************************************************
- *PLL_SC0_PLL_RESET - Resets
- ***************************************************************************/
-/* CLKGEN :: PLL_SC0_PLL_RESET :: reserved0 [31:02] */
-#define BCHP_CLKGEN_PLL_SC0_PLL_RESET_reserved0_MASK 0xfffffffc
-#define BCHP_CLKGEN_PLL_SC0_PLL_RESET_reserved0_SHIFT 2
-
-/* CLKGEN :: PLL_SC0_PLL_RESET :: RESETD [01:01] */
-#define BCHP_CLKGEN_PLL_SC0_PLL_RESET_RESETD_MASK 0x00000002
-#define BCHP_CLKGEN_PLL_SC0_PLL_RESET_RESETD_SHIFT 1
-#define BCHP_CLKGEN_PLL_SC0_PLL_RESET_RESETD_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_SC0_PLL_RESET :: RESETA [00:00] */
-#define BCHP_CLKGEN_PLL_SC0_PLL_RESET_RESETA_MASK 0x00000001
-#define BCHP_CLKGEN_PLL_SC0_PLL_RESET_RESETA_SHIFT 0
-#define BCHP_CLKGEN_PLL_SC0_PLL_RESET_RESETA_DEFAULT 0x00000000
-
-/***************************************************************************
- *PLL_SC0_PLL_SSC_MODE_CONTROL_HIGH - Higher bits of Spread Spectrum mode control
- ***************************************************************************/
-/* CLKGEN :: PLL_SC0_PLL_SSC_MODE_CONTROL_HIGH :: reserved0 [31:16] */
-#define BCHP_CLKGEN_PLL_SC0_PLL_SSC_MODE_CONTROL_HIGH_reserved0_MASK 0xffff0000
-#define BCHP_CLKGEN_PLL_SC0_PLL_SSC_MODE_CONTROL_HIGH_reserved0_SHIFT 16
-
-/* CLKGEN :: PLL_SC0_PLL_SSC_MODE_CONTROL_HIGH :: SSC_STEP [15:00] */
-#define BCHP_CLKGEN_PLL_SC0_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_MASK 0x0000ffff
-#define BCHP_CLKGEN_PLL_SC0_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_SHIFT 0
-#define BCHP_CLKGEN_PLL_SC0_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *PLL_SC0_PLL_SSC_MODE_CONTROL_LOW - Lower bits of Spread Spectrum mode control
- ***************************************************************************/
-/* CLKGEN :: PLL_SC0_PLL_SSC_MODE_CONTROL_LOW :: reserved0 [31:23] */
-#define BCHP_CLKGEN_PLL_SC0_PLL_SSC_MODE_CONTROL_LOW_reserved0_MASK 0xff800000
-#define BCHP_CLKGEN_PLL_SC0_PLL_SSC_MODE_CONTROL_LOW_reserved0_SHIFT 23
-
-/* CLKGEN :: PLL_SC0_PLL_SSC_MODE_CONTROL_LOW :: SSC_MODE [22:22] */
-#define BCHP_CLKGEN_PLL_SC0_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_MASK 0x00400000
-#define BCHP_CLKGEN_PLL_SC0_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_SHIFT 22
-#define BCHP_CLKGEN_PLL_SC0_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_SC0_PLL_SSC_MODE_CONTROL_LOW :: SSC_LIMIT [21:00] */
-#define BCHP_CLKGEN_PLL_SC0_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_MASK 0x003fffff
-#define BCHP_CLKGEN_PLL_SC0_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_SHIFT 0
-#define BCHP_CLKGEN_PLL_SC0_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_DEFAULT 0x00000000
-
-/***************************************************************************
- *PLL_SC0_PLL_STATUS - Status
- ***************************************************************************/
-/* CLKGEN :: PLL_SC0_PLL_STATUS :: reserved0 [31:12] */
-#define BCHP_CLKGEN_PLL_SC0_PLL_STATUS_reserved0_MASK 0xfffff000
-#define BCHP_CLKGEN_PLL_SC0_PLL_STATUS_reserved0_SHIFT 12
-
-/* CLKGEN :: PLL_SC0_PLL_STATUS :: TEST_STATUS [11:00] */
-#define BCHP_CLKGEN_PLL_SC0_PLL_STATUS_TEST_STATUS_MASK 0x00000fff
-#define BCHP_CLKGEN_PLL_SC0_PLL_STATUS_TEST_STATUS_SHIFT 0
-
-/***************************************************************************
- *PLL_SC1_PLL_CHANNEL_CTRL_CH_0 - PLL CHANNEL control CH 0
- ***************************************************************************/
-/* CLKGEN :: PLL_SC1_PLL_CHANNEL_CTRL_CH_0 :: reserved0 [31:11] */
-#define BCHP_CLKGEN_PLL_SC1_PLL_CHANNEL_CTRL_CH_0_reserved0_MASK 0xfffff800
-#define BCHP_CLKGEN_PLL_SC1_PLL_CHANNEL_CTRL_CH_0_reserved0_SHIFT 11
-
-/* CLKGEN :: PLL_SC1_PLL_CHANNEL_CTRL_CH_0 :: POST_DIVIDER_HOLD_CH0 [10:10] */
-#define BCHP_CLKGEN_PLL_SC1_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_MASK 0x00000400
-#define BCHP_CLKGEN_PLL_SC1_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_SHIFT 10
-#define BCHP_CLKGEN_PLL_SC1_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_SC1_PLL_CHANNEL_CTRL_CH_0 :: PHASE_OFFSET_CH0 [09:09] */
-#define BCHP_CLKGEN_PLL_SC1_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_MASK 0x00000200
-#define BCHP_CLKGEN_PLL_SC1_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_SHIFT 9
-#define BCHP_CLKGEN_PLL_SC1_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_SC1_PLL_CHANNEL_CTRL_CH_0 :: MDIV_CH0 [08:01] */
-#define BCHP_CLKGEN_PLL_SC1_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_MASK 0x000001fe
-#define BCHP_CLKGEN_PLL_SC1_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_SHIFT 1
-#define BCHP_CLKGEN_PLL_SC1_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_DEFAULT 0x00000030
-
-/* CLKGEN :: PLL_SC1_PLL_CHANNEL_CTRL_CH_0 :: CLOCK_DIS_CH0 [00:00] */
-#define BCHP_CLKGEN_PLL_SC1_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_MASK 0x00000001
-#define BCHP_CLKGEN_PLL_SC1_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_SHIFT 0
-#define BCHP_CLKGEN_PLL_SC1_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_DEFAULT 0x00000000
-
-/***************************************************************************
- *PLL_SC1_PLL_DIV - Pre multiplier
- ***************************************************************************/
-/* CLKGEN :: PLL_SC1_PLL_DIV :: reserved0 [31:14] */
-#define BCHP_CLKGEN_PLL_SC1_PLL_DIV_reserved0_MASK 0xffffc000
-#define BCHP_CLKGEN_PLL_SC1_PLL_DIV_reserved0_SHIFT 14
-
-/* CLKGEN :: PLL_SC1_PLL_DIV :: PDIV [13:10] */
-#define BCHP_CLKGEN_PLL_SC1_PLL_DIV_PDIV_MASK 0x00003c00
-#define BCHP_CLKGEN_PLL_SC1_PLL_DIV_PDIV_SHIFT 10
-#define BCHP_CLKGEN_PLL_SC1_PLL_DIV_PDIV_DEFAULT 0x00000002
-
-/* CLKGEN :: PLL_SC1_PLL_DIV :: NDIV_INT [09:00] */
-#define BCHP_CLKGEN_PLL_SC1_PLL_DIV_NDIV_INT_MASK 0x000003ff
-#define BCHP_CLKGEN_PLL_SC1_PLL_DIV_NDIV_INT_SHIFT 0
-#define BCHP_CLKGEN_PLL_SC1_PLL_DIV_NDIV_INT_DEFAULT 0x00000030
-
-/***************************************************************************
- *PLL_SC1_PLL_FRAC - Fractional
- ***************************************************************************/
-/* CLKGEN :: PLL_SC1_PLL_FRAC :: reserved0 [31:20] */
-#define BCHP_CLKGEN_PLL_SC1_PLL_FRAC_reserved0_MASK 0xfff00000
-#define BCHP_CLKGEN_PLL_SC1_PLL_FRAC_reserved0_SHIFT 20
-
-/* CLKGEN :: PLL_SC1_PLL_FRAC :: FRAC_CONTROL [19:00] */
-#define BCHP_CLKGEN_PLL_SC1_PLL_FRAC_FRAC_CONTROL_MASK 0x000fffff
-#define BCHP_CLKGEN_PLL_SC1_PLL_FRAC_FRAC_CONTROL_SHIFT 0
-#define BCHP_CLKGEN_PLL_SC1_PLL_FRAC_FRAC_CONTROL_DEFAULT 0x00000000
-
-/***************************************************************************
- *PLL_SC1_PLL_GAIN - PLL GAIN
- ***************************************************************************/
-/* CLKGEN :: PLL_SC1_PLL_GAIN :: reserved0 [31:10] */
-#define BCHP_CLKGEN_PLL_SC1_PLL_GAIN_reserved0_MASK 0xfffffc00
-#define BCHP_CLKGEN_PLL_SC1_PLL_GAIN_reserved0_SHIFT 10
-
-/* CLKGEN :: PLL_SC1_PLL_GAIN :: LOOP_GAIN_PROPORTIONAL_IN_PHASE [09:06] */
-#define BCHP_CLKGEN_PLL_SC1_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_MASK 0x000003c0
-#define BCHP_CLKGEN_PLL_SC1_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_SHIFT 6
-#define BCHP_CLKGEN_PLL_SC1_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_DEFAULT 0x00000005
-
-/* CLKGEN :: PLL_SC1_PLL_GAIN :: LOOP_GAIN_IN_FREQ [05:03] */
-#define BCHP_CLKGEN_PLL_SC1_PLL_GAIN_LOOP_GAIN_IN_FREQ_MASK 0x00000038
-#define BCHP_CLKGEN_PLL_SC1_PLL_GAIN_LOOP_GAIN_IN_FREQ_SHIFT 3
-#define BCHP_CLKGEN_PLL_SC1_PLL_GAIN_LOOP_GAIN_IN_FREQ_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_SC1_PLL_GAIN :: LOOP_GAIN_INTEGRATOR_IN_PHASE [02:00] */
-#define BCHP_CLKGEN_PLL_SC1_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_MASK 0x00000007
-#define BCHP_CLKGEN_PLL_SC1_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_SHIFT 0
-#define BCHP_CLKGEN_PLL_SC1_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_DEFAULT 0x00000002
-
-/***************************************************************************
- *PLL_SC1_PLL_LOCK_STATUS - Lock Status
- ***************************************************************************/
-/* CLKGEN :: PLL_SC1_PLL_LOCK_STATUS :: reserved0 [31:02] */
-#define BCHP_CLKGEN_PLL_SC1_PLL_LOCK_STATUS_reserved0_MASK 0xfffffffc
-#define BCHP_CLKGEN_PLL_SC1_PLL_LOCK_STATUS_reserved0_SHIFT 2
-
-/* CLKGEN :: PLL_SC1_PLL_LOCK_STATUS :: LOCK_LOST [01:01] */
-#define BCHP_CLKGEN_PLL_SC1_PLL_LOCK_STATUS_LOCK_LOST_MASK 0x00000002
-#define BCHP_CLKGEN_PLL_SC1_PLL_LOCK_STATUS_LOCK_LOST_SHIFT 1
-
-/* CLKGEN :: PLL_SC1_PLL_LOCK_STATUS :: LOCK [00:00] */
-#define BCHP_CLKGEN_PLL_SC1_PLL_LOCK_STATUS_LOCK_MASK 0x00000001
-#define BCHP_CLKGEN_PLL_SC1_PLL_LOCK_STATUS_LOCK_SHIFT 0
-
-/***************************************************************************
- *PLL_SC1_PLL_MISC - Mscellaneous control bus.
- ***************************************************************************/
-/* CLKGEN :: PLL_SC1_PLL_MISC :: VCO_RANGE [31:30] */
-#define BCHP_CLKGEN_PLL_SC1_PLL_MISC_VCO_RANGE_MASK 0xc0000000
-#define BCHP_CLKGEN_PLL_SC1_PLL_MISC_VCO_RANGE_SHIFT 30
-#define BCHP_CLKGEN_PLL_SC1_PLL_MISC_VCO_RANGE_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_SC1_PLL_MISC :: VCO_FB_DIV2 [29:29] */
-#define BCHP_CLKGEN_PLL_SC1_PLL_MISC_VCO_FB_DIV2_MASK 0x20000000
-#define BCHP_CLKGEN_PLL_SC1_PLL_MISC_VCO_FB_DIV2_SHIFT 29
-#define BCHP_CLKGEN_PLL_SC1_PLL_MISC_VCO_FB_DIV2_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_SC1_PLL_MISC :: STAT_UPDATE [28:28] */
-#define BCHP_CLKGEN_PLL_SC1_PLL_MISC_STAT_UPDATE_MASK 0x10000000
-#define BCHP_CLKGEN_PLL_SC1_PLL_MISC_STAT_UPDATE_SHIFT 28
-#define BCHP_CLKGEN_PLL_SC1_PLL_MISC_STAT_UPDATE_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_SC1_PLL_MISC :: STAT_SELECT [27:25] */
-#define BCHP_CLKGEN_PLL_SC1_PLL_MISC_STAT_SELECT_MASK 0x0e000000
-#define BCHP_CLKGEN_PLL_SC1_PLL_MISC_STAT_SELECT_SHIFT 25
-#define BCHP_CLKGEN_PLL_SC1_PLL_MISC_STAT_SELECT_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_SC1_PLL_MISC :: STAT_RESET [24:24] */
-#define BCHP_CLKGEN_PLL_SC1_PLL_MISC_STAT_RESET_MASK 0x01000000
-#define BCHP_CLKGEN_PLL_SC1_PLL_MISC_STAT_RESET_SHIFT 24
-#define BCHP_CLKGEN_PLL_SC1_PLL_MISC_STAT_RESET_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_SC1_PLL_MISC :: STAT_MODE [23:22] */
-#define BCHP_CLKGEN_PLL_SC1_PLL_MISC_STAT_MODE_MASK 0x00c00000
-#define BCHP_CLKGEN_PLL_SC1_PLL_MISC_STAT_MODE_SHIFT 22
-#define BCHP_CLKGEN_PLL_SC1_PLL_MISC_STAT_MODE_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_SC1_PLL_MISC :: PWM_RATE [21:20] */
-#define BCHP_CLKGEN_PLL_SC1_PLL_MISC_PWM_RATE_MASK 0x00300000
-#define BCHP_CLKGEN_PLL_SC1_PLL_MISC_PWM_RATE_SHIFT 20
-#define BCHP_CLKGEN_PLL_SC1_PLL_MISC_PWM_RATE_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_SC1_PLL_MISC :: POST_CTRL_RESETB [19:18] */
-#define BCHP_CLKGEN_PLL_SC1_PLL_MISC_POST_CTRL_RESETB_MASK 0x000c0000
-#define BCHP_CLKGEN_PLL_SC1_PLL_MISC_POST_CTRL_RESETB_SHIFT 18
-#define BCHP_CLKGEN_PLL_SC1_PLL_MISC_POST_CTRL_RESETB_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_SC1_PLL_MISC :: PLLRESERVED2 [17:16] */
-#define BCHP_CLKGEN_PLL_SC1_PLL_MISC_PLLRESERVED2_MASK 0x00030000
-#define BCHP_CLKGEN_PLL_SC1_PLL_MISC_PLLRESERVED2_SHIFT 16
-#define BCHP_CLKGEN_PLL_SC1_PLL_MISC_PLLRESERVED2_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_SC1_PLL_MISC :: PLLRESERVED1 [15:15] */
-#define BCHP_CLKGEN_PLL_SC1_PLL_MISC_PLLRESERVED1_MASK 0x00008000
-#define BCHP_CLKGEN_PLL_SC1_PLL_MISC_PLLRESERVED1_SHIFT 15
-#define BCHP_CLKGEN_PLL_SC1_PLL_MISC_PLLRESERVED1_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_SC1_PLL_MISC :: NDIV_RELOCK [14:14] */
-#define BCHP_CLKGEN_PLL_SC1_PLL_MISC_NDIV_RELOCK_MASK 0x00004000
-#define BCHP_CLKGEN_PLL_SC1_PLL_MISC_NDIV_RELOCK_SHIFT 14
-#define BCHP_CLKGEN_PLL_SC1_PLL_MISC_NDIV_RELOCK_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_SC1_PLL_MISC :: FAST_LOCK [13:13] */
-#define BCHP_CLKGEN_PLL_SC1_PLL_MISC_FAST_LOCK_MASK 0x00002000
-#define BCHP_CLKGEN_PLL_SC1_PLL_MISC_FAST_LOCK_SHIFT 13
-#define BCHP_CLKGEN_PLL_SC1_PLL_MISC_FAST_LOCK_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_SC1_PLL_MISC :: DCO_CTRL_BYPASS_ENABLE [12:12] */
-#define BCHP_CLKGEN_PLL_SC1_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_MASK 0x00001000
-#define BCHP_CLKGEN_PLL_SC1_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_SHIFT 12
-#define BCHP_CLKGEN_PLL_SC1_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_SC1_PLL_MISC :: DCO_CTRL_BYPASS [11:00] */
-#define BCHP_CLKGEN_PLL_SC1_PLL_MISC_DCO_CTRL_BYPASS_MASK 0x00000fff
-#define BCHP_CLKGEN_PLL_SC1_PLL_MISC_DCO_CTRL_BYPASS_SHIFT 0
-#define BCHP_CLKGEN_PLL_SC1_PLL_MISC_DCO_CTRL_BYPASS_DEFAULT 0x00000000
-
-/***************************************************************************
- *PLL_SC1_PLL_MISC2 - Mscellaneous control bus continued.
- ***************************************************************************/
-/* CLKGEN :: PLL_SC1_PLL_MISC2 :: PLLRESERVED0 [31:02] */
-#define BCHP_CLKGEN_PLL_SC1_PLL_MISC2_PLLRESERVED0_MASK 0xfffffffc
-#define BCHP_CLKGEN_PLL_SC1_PLL_MISC2_PLLRESERVED0_SHIFT 2
-#define BCHP_CLKGEN_PLL_SC1_PLL_MISC2_PLLRESERVED0_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_SC1_PLL_MISC2 :: LDO [01:00] */
-#define BCHP_CLKGEN_PLL_SC1_PLL_MISC2_LDO_MASK 0x00000003
-#define BCHP_CLKGEN_PLL_SC1_PLL_MISC2_LDO_SHIFT 0
-#define BCHP_CLKGEN_PLL_SC1_PLL_MISC2_LDO_DEFAULT 0x00000001
-
-/***************************************************************************
- *PLL_SC1_PLL_PWRON - Poweron
- ***************************************************************************/
-/* CLKGEN :: PLL_SC1_PLL_PWRON :: reserved0 [31:01] */
-#define BCHP_CLKGEN_PLL_SC1_PLL_PWRON_reserved0_MASK 0xfffffffe
-#define BCHP_CLKGEN_PLL_SC1_PLL_PWRON_reserved0_SHIFT 1
-
-/* CLKGEN :: PLL_SC1_PLL_PWRON :: PWRON_PLL [00:00] */
-#define BCHP_CLKGEN_PLL_SC1_PLL_PWRON_PWRON_PLL_MASK 0x00000001
-#define BCHP_CLKGEN_PLL_SC1_PLL_PWRON_PWRON_PLL_SHIFT 0
-#define BCHP_CLKGEN_PLL_SC1_PLL_PWRON_PWRON_PLL_DEFAULT 0x00000001
-
-/***************************************************************************
- *PLL_SC1_PLL_RESET - Resets
- ***************************************************************************/
-/* CLKGEN :: PLL_SC1_PLL_RESET :: reserved0 [31:02] */
-#define BCHP_CLKGEN_PLL_SC1_PLL_RESET_reserved0_MASK 0xfffffffc
-#define BCHP_CLKGEN_PLL_SC1_PLL_RESET_reserved0_SHIFT 2
-
-/* CLKGEN :: PLL_SC1_PLL_RESET :: RESETD [01:01] */
-#define BCHP_CLKGEN_PLL_SC1_PLL_RESET_RESETD_MASK 0x00000002
-#define BCHP_CLKGEN_PLL_SC1_PLL_RESET_RESETD_SHIFT 1
-#define BCHP_CLKGEN_PLL_SC1_PLL_RESET_RESETD_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_SC1_PLL_RESET :: RESETA [00:00] */
-#define BCHP_CLKGEN_PLL_SC1_PLL_RESET_RESETA_MASK 0x00000001
-#define BCHP_CLKGEN_PLL_SC1_PLL_RESET_RESETA_SHIFT 0
-#define BCHP_CLKGEN_PLL_SC1_PLL_RESET_RESETA_DEFAULT 0x00000000
-
-/***************************************************************************
- *PLL_SC1_PLL_SSC_MODE_CONTROL_HIGH - Higher bits of Spread Spectrum mode control
- ***************************************************************************/
-/* CLKGEN :: PLL_SC1_PLL_SSC_MODE_CONTROL_HIGH :: reserved0 [31:16] */
-#define BCHP_CLKGEN_PLL_SC1_PLL_SSC_MODE_CONTROL_HIGH_reserved0_MASK 0xffff0000
-#define BCHP_CLKGEN_PLL_SC1_PLL_SSC_MODE_CONTROL_HIGH_reserved0_SHIFT 16
-
-/* CLKGEN :: PLL_SC1_PLL_SSC_MODE_CONTROL_HIGH :: SSC_STEP [15:00] */
-#define BCHP_CLKGEN_PLL_SC1_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_MASK 0x0000ffff
-#define BCHP_CLKGEN_PLL_SC1_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_SHIFT 0
-#define BCHP_CLKGEN_PLL_SC1_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *PLL_SC1_PLL_SSC_MODE_CONTROL_LOW - Lower bits of Spread Spectrum mode control
- ***************************************************************************/
-/* CLKGEN :: PLL_SC1_PLL_SSC_MODE_CONTROL_LOW :: reserved0 [31:23] */
-#define BCHP_CLKGEN_PLL_SC1_PLL_SSC_MODE_CONTROL_LOW_reserved0_MASK 0xff800000
-#define BCHP_CLKGEN_PLL_SC1_PLL_SSC_MODE_CONTROL_LOW_reserved0_SHIFT 23
-
-/* CLKGEN :: PLL_SC1_PLL_SSC_MODE_CONTROL_LOW :: SSC_MODE [22:22] */
-#define BCHP_CLKGEN_PLL_SC1_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_MASK 0x00400000
-#define BCHP_CLKGEN_PLL_SC1_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_SHIFT 22
-#define BCHP_CLKGEN_PLL_SC1_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_SC1_PLL_SSC_MODE_CONTROL_LOW :: SSC_LIMIT [21:00] */
-#define BCHP_CLKGEN_PLL_SC1_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_MASK 0x003fffff
-#define BCHP_CLKGEN_PLL_SC1_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_SHIFT 0
-#define BCHP_CLKGEN_PLL_SC1_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_DEFAULT 0x00000000
-
-/***************************************************************************
- *PLL_SC1_PLL_STATUS - Status
- ***************************************************************************/
-/* CLKGEN :: PLL_SC1_PLL_STATUS :: reserved0 [31:12] */
-#define BCHP_CLKGEN_PLL_SC1_PLL_STATUS_reserved0_MASK 0xfffff000
-#define BCHP_CLKGEN_PLL_SC1_PLL_STATUS_reserved0_SHIFT 12
-
-/* CLKGEN :: PLL_SC1_PLL_STATUS :: TEST_STATUS [11:00] */
-#define BCHP_CLKGEN_PLL_SC1_PLL_STATUS_TEST_STATUS_MASK 0x00000fff
-#define BCHP_CLKGEN_PLL_SC1_PLL_STATUS_TEST_STATUS_SHIFT 0
-
-/***************************************************************************
- *PLL_SDS_PLL_CHANNEL_CTRL_CH_0 - PLL CHANNEL control CH 0
- ***************************************************************************/
-/* CLKGEN :: PLL_SDS_PLL_CHANNEL_CTRL_CH_0 :: reserved0 [31:11] */
-#define BCHP_CLKGEN_PLL_SDS_PLL_CHANNEL_CTRL_CH_0_reserved0_MASK 0xfffff800
-#define BCHP_CLKGEN_PLL_SDS_PLL_CHANNEL_CTRL_CH_0_reserved0_SHIFT 11
-
-/* CLKGEN :: PLL_SDS_PLL_CHANNEL_CTRL_CH_0 :: POST_DIVIDER_HOLD_CH0 [10:10] */
-#define BCHP_CLKGEN_PLL_SDS_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_MASK 0x00000400
-#define BCHP_CLKGEN_PLL_SDS_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_SHIFT 10
-#define BCHP_CLKGEN_PLL_SDS_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_SDS_PLL_CHANNEL_CTRL_CH_0 :: PHASE_OFFSET_CH0 [09:09] */
-#define BCHP_CLKGEN_PLL_SDS_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_MASK 0x00000200
-#define BCHP_CLKGEN_PLL_SDS_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_SHIFT 9
-#define BCHP_CLKGEN_PLL_SDS_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_SDS_PLL_CHANNEL_CTRL_CH_0 :: MDIV_CH0 [08:01] */
-#define BCHP_CLKGEN_PLL_SDS_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_MASK 0x000001fe
-#define BCHP_CLKGEN_PLL_SDS_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_SHIFT 1
-#define BCHP_CLKGEN_PLL_SDS_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_DEFAULT 0x00000009
-
-/* CLKGEN :: PLL_SDS_PLL_CHANNEL_CTRL_CH_0 :: CLOCK_DIS_CH0 [00:00] */
-#define BCHP_CLKGEN_PLL_SDS_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_MASK 0x00000001
-#define BCHP_CLKGEN_PLL_SDS_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_SHIFT 0
-#define BCHP_CLKGEN_PLL_SDS_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_DEFAULT 0x00000000
-
-/***************************************************************************
- *PLL_SDS_PLL_CHANNEL_CTRL_CH_1 - PLL CHANNEL control CH 1
- ***************************************************************************/
-/* CLKGEN :: PLL_SDS_PLL_CHANNEL_CTRL_CH_1 :: reserved0 [31:11] */
-#define BCHP_CLKGEN_PLL_SDS_PLL_CHANNEL_CTRL_CH_1_reserved0_MASK 0xfffff800
-#define BCHP_CLKGEN_PLL_SDS_PLL_CHANNEL_CTRL_CH_1_reserved0_SHIFT 11
-
-/* CLKGEN :: PLL_SDS_PLL_CHANNEL_CTRL_CH_1 :: POST_DIVIDER_HOLD_CH1 [10:10] */
-#define BCHP_CLKGEN_PLL_SDS_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_MASK 0x00000400
-#define BCHP_CLKGEN_PLL_SDS_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_SHIFT 10
-#define BCHP_CLKGEN_PLL_SDS_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_SDS_PLL_CHANNEL_CTRL_CH_1 :: PHASE_OFFSET_CH1 [09:09] */
-#define BCHP_CLKGEN_PLL_SDS_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_MASK 0x00000200
-#define BCHP_CLKGEN_PLL_SDS_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_SHIFT 9
-#define BCHP_CLKGEN_PLL_SDS_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_SDS_PLL_CHANNEL_CTRL_CH_1 :: MDIV_CH1 [08:01] */
-#define BCHP_CLKGEN_PLL_SDS_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_MASK 0x000001fe
-#define BCHP_CLKGEN_PLL_SDS_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_SHIFT 1
-#define BCHP_CLKGEN_PLL_SDS_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_DEFAULT 0x0000005a
-
-/* CLKGEN :: PLL_SDS_PLL_CHANNEL_CTRL_CH_1 :: CLOCK_DIS_CH1 [00:00] */
-#define BCHP_CLKGEN_PLL_SDS_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_MASK 0x00000001
-#define BCHP_CLKGEN_PLL_SDS_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_SHIFT 0
-#define BCHP_CLKGEN_PLL_SDS_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_DEFAULT 0x00000000
-
-/***************************************************************************
- *PLL_SDS_PLL_DIV - Pre multiplier
- ***************************************************************************/
-/* CLKGEN :: PLL_SDS_PLL_DIV :: reserved0 [31:14] */
-#define BCHP_CLKGEN_PLL_SDS_PLL_DIV_reserved0_MASK 0xffffc000
-#define BCHP_CLKGEN_PLL_SDS_PLL_DIV_reserved0_SHIFT 14
-
-/* CLKGEN :: PLL_SDS_PLL_DIV :: PDIV [13:10] */
-#define BCHP_CLKGEN_PLL_SDS_PLL_DIV_PDIV_MASK 0x00003c00
-#define BCHP_CLKGEN_PLL_SDS_PLL_DIV_PDIV_SHIFT 10
-#define BCHP_CLKGEN_PLL_SDS_PLL_DIV_PDIV_DEFAULT 0x00000001
-
-/* CLKGEN :: PLL_SDS_PLL_DIV :: NDIV_INT [09:00] */
-#define BCHP_CLKGEN_PLL_SDS_PLL_DIV_NDIV_INT_MASK 0x000003ff
-#define BCHP_CLKGEN_PLL_SDS_PLL_DIV_NDIV_INT_SHIFT 0
-#define BCHP_CLKGEN_PLL_SDS_PLL_DIV_NDIV_INT_DEFAULT 0x00000048
-
-/***************************************************************************
- *PLL_SDS_PLL_GAIN - PLL GAIN
- ***************************************************************************/
-/* CLKGEN :: PLL_SDS_PLL_GAIN :: reserved0 [31:10] */
-#define BCHP_CLKGEN_PLL_SDS_PLL_GAIN_reserved0_MASK 0xfffffc00
-#define BCHP_CLKGEN_PLL_SDS_PLL_GAIN_reserved0_SHIFT 10
-
-/* CLKGEN :: PLL_SDS_PLL_GAIN :: LOOP_GAIN_PROPORTIONAL_IN_PHASE [09:06] */
-#define BCHP_CLKGEN_PLL_SDS_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_MASK 0x000003c0
-#define BCHP_CLKGEN_PLL_SDS_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_SHIFT 6
-#define BCHP_CLKGEN_PLL_SDS_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_DEFAULT 0x00000003
-
-/* CLKGEN :: PLL_SDS_PLL_GAIN :: LOOP_GAIN_IN_FREQ [05:03] */
-#define BCHP_CLKGEN_PLL_SDS_PLL_GAIN_LOOP_GAIN_IN_FREQ_MASK 0x00000038
-#define BCHP_CLKGEN_PLL_SDS_PLL_GAIN_LOOP_GAIN_IN_FREQ_SHIFT 3
-#define BCHP_CLKGEN_PLL_SDS_PLL_GAIN_LOOP_GAIN_IN_FREQ_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_SDS_PLL_GAIN :: LOOP_GAIN_INTEGRATOR_IN_PHASE [02:00] */
-#define BCHP_CLKGEN_PLL_SDS_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_MASK 0x00000007
-#define BCHP_CLKGEN_PLL_SDS_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_SHIFT 0
-#define BCHP_CLKGEN_PLL_SDS_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_DEFAULT 0x00000002
-
-/***************************************************************************
- *PLL_SDS_PLL_LDO_PWRON - LDO Power on
- ***************************************************************************/
-/* CLKGEN :: PLL_SDS_PLL_LDO_PWRON :: reserved0 [31:01] */
-#define BCHP_CLKGEN_PLL_SDS_PLL_LDO_PWRON_reserved0_MASK 0xfffffffe
-#define BCHP_CLKGEN_PLL_SDS_PLL_LDO_PWRON_reserved0_SHIFT 1
-
-/* CLKGEN :: PLL_SDS_PLL_LDO_PWRON :: LDO_PWRON_PLL [00:00] */
-#define BCHP_CLKGEN_PLL_SDS_PLL_LDO_PWRON_LDO_PWRON_PLL_MASK 0x00000001
-#define BCHP_CLKGEN_PLL_SDS_PLL_LDO_PWRON_LDO_PWRON_PLL_SHIFT 0
-#define BCHP_CLKGEN_PLL_SDS_PLL_LDO_PWRON_LDO_PWRON_PLL_DEFAULT 0x00000001
-
-/***************************************************************************
- *PLL_SDS_PLL_LOCK_STATUS - Lock Status
- ***************************************************************************/
-/* CLKGEN :: PLL_SDS_PLL_LOCK_STATUS :: reserved0 [31:02] */
-#define BCHP_CLKGEN_PLL_SDS_PLL_LOCK_STATUS_reserved0_MASK 0xfffffffc
-#define BCHP_CLKGEN_PLL_SDS_PLL_LOCK_STATUS_reserved0_SHIFT 2
-
-/* CLKGEN :: PLL_SDS_PLL_LOCK_STATUS :: LOCK_LOST [01:01] */
-#define BCHP_CLKGEN_PLL_SDS_PLL_LOCK_STATUS_LOCK_LOST_MASK 0x00000002
-#define BCHP_CLKGEN_PLL_SDS_PLL_LOCK_STATUS_LOCK_LOST_SHIFT 1
-
-/* CLKGEN :: PLL_SDS_PLL_LOCK_STATUS :: LOCK [00:00] */
-#define BCHP_CLKGEN_PLL_SDS_PLL_LOCK_STATUS_LOCK_MASK 0x00000001
-#define BCHP_CLKGEN_PLL_SDS_PLL_LOCK_STATUS_LOCK_SHIFT 0
-
-/***************************************************************************
- *PLL_SDS_PLL_MISC - Mscellaneous control bus.
- ***************************************************************************/
-/* CLKGEN :: PLL_SDS_PLL_MISC :: VCO_RANGE [31:30] */
-#define BCHP_CLKGEN_PLL_SDS_PLL_MISC_VCO_RANGE_MASK 0xc0000000
-#define BCHP_CLKGEN_PLL_SDS_PLL_MISC_VCO_RANGE_SHIFT 30
-#define BCHP_CLKGEN_PLL_SDS_PLL_MISC_VCO_RANGE_DEFAULT 0x00000002
-
-/* CLKGEN :: PLL_SDS_PLL_MISC :: VCO_FB_DIV2 [29:29] */
-#define BCHP_CLKGEN_PLL_SDS_PLL_MISC_VCO_FB_DIV2_MASK 0x20000000
-#define BCHP_CLKGEN_PLL_SDS_PLL_MISC_VCO_FB_DIV2_SHIFT 29
-#define BCHP_CLKGEN_PLL_SDS_PLL_MISC_VCO_FB_DIV2_DEFAULT 0x00000001
-
-/* CLKGEN :: PLL_SDS_PLL_MISC :: STAT_UPDATE [28:28] */
-#define BCHP_CLKGEN_PLL_SDS_PLL_MISC_STAT_UPDATE_MASK 0x10000000
-#define BCHP_CLKGEN_PLL_SDS_PLL_MISC_STAT_UPDATE_SHIFT 28
-#define BCHP_CLKGEN_PLL_SDS_PLL_MISC_STAT_UPDATE_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_SDS_PLL_MISC :: STAT_SELECT [27:25] */
-#define BCHP_CLKGEN_PLL_SDS_PLL_MISC_STAT_SELECT_MASK 0x0e000000
-#define BCHP_CLKGEN_PLL_SDS_PLL_MISC_STAT_SELECT_SHIFT 25
-#define BCHP_CLKGEN_PLL_SDS_PLL_MISC_STAT_SELECT_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_SDS_PLL_MISC :: STAT_RESET [24:24] */
-#define BCHP_CLKGEN_PLL_SDS_PLL_MISC_STAT_RESET_MASK 0x01000000
-#define BCHP_CLKGEN_PLL_SDS_PLL_MISC_STAT_RESET_SHIFT 24
-#define BCHP_CLKGEN_PLL_SDS_PLL_MISC_STAT_RESET_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_SDS_PLL_MISC :: STAT_MODE [23:22] */
-#define BCHP_CLKGEN_PLL_SDS_PLL_MISC_STAT_MODE_MASK 0x00c00000
-#define BCHP_CLKGEN_PLL_SDS_PLL_MISC_STAT_MODE_SHIFT 22
-#define BCHP_CLKGEN_PLL_SDS_PLL_MISC_STAT_MODE_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_SDS_PLL_MISC :: PWM_RATE [21:20] */
-#define BCHP_CLKGEN_PLL_SDS_PLL_MISC_PWM_RATE_MASK 0x00300000
-#define BCHP_CLKGEN_PLL_SDS_PLL_MISC_PWM_RATE_SHIFT 20
-#define BCHP_CLKGEN_PLL_SDS_PLL_MISC_PWM_RATE_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_SDS_PLL_MISC :: POST_CTRL_RESETB [19:18] */
-#define BCHP_CLKGEN_PLL_SDS_PLL_MISC_POST_CTRL_RESETB_MASK 0x000c0000
-#define BCHP_CLKGEN_PLL_SDS_PLL_MISC_POST_CTRL_RESETB_SHIFT 18
-#define BCHP_CLKGEN_PLL_SDS_PLL_MISC_POST_CTRL_RESETB_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_SDS_PLL_MISC :: PLLRESERVED2 [17:16] */
-#define BCHP_CLKGEN_PLL_SDS_PLL_MISC_PLLRESERVED2_MASK 0x00030000
-#define BCHP_CLKGEN_PLL_SDS_PLL_MISC_PLLRESERVED2_SHIFT 16
-#define BCHP_CLKGEN_PLL_SDS_PLL_MISC_PLLRESERVED2_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_SDS_PLL_MISC :: PLLRESERVED1 [15:15] */
-#define BCHP_CLKGEN_PLL_SDS_PLL_MISC_PLLRESERVED1_MASK 0x00008000
-#define BCHP_CLKGEN_PLL_SDS_PLL_MISC_PLLRESERVED1_SHIFT 15
-#define BCHP_CLKGEN_PLL_SDS_PLL_MISC_PLLRESERVED1_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_SDS_PLL_MISC :: NDIV_RELOCK [14:14] */
-#define BCHP_CLKGEN_PLL_SDS_PLL_MISC_NDIV_RELOCK_MASK 0x00004000
-#define BCHP_CLKGEN_PLL_SDS_PLL_MISC_NDIV_RELOCK_SHIFT 14
-#define BCHP_CLKGEN_PLL_SDS_PLL_MISC_NDIV_RELOCK_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_SDS_PLL_MISC :: FAST_LOCK [13:13] */
-#define BCHP_CLKGEN_PLL_SDS_PLL_MISC_FAST_LOCK_MASK 0x00002000
-#define BCHP_CLKGEN_PLL_SDS_PLL_MISC_FAST_LOCK_SHIFT 13
-#define BCHP_CLKGEN_PLL_SDS_PLL_MISC_FAST_LOCK_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_SDS_PLL_MISC :: DCO_CTRL_BYPASS_ENABLE [12:12] */
-#define BCHP_CLKGEN_PLL_SDS_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_MASK 0x00001000
-#define BCHP_CLKGEN_PLL_SDS_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_SHIFT 12
-#define BCHP_CLKGEN_PLL_SDS_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_SDS_PLL_MISC :: DCO_CTRL_BYPASS [11:00] */
-#define BCHP_CLKGEN_PLL_SDS_PLL_MISC_DCO_CTRL_BYPASS_MASK 0x00000fff
-#define BCHP_CLKGEN_PLL_SDS_PLL_MISC_DCO_CTRL_BYPASS_SHIFT 0
-#define BCHP_CLKGEN_PLL_SDS_PLL_MISC_DCO_CTRL_BYPASS_DEFAULT 0x00000000
-
-/***************************************************************************
- *PLL_SDS_PLL_MISC2 - Mscellaneous control bus continued.
- ***************************************************************************/
-/* CLKGEN :: PLL_SDS_PLL_MISC2 :: PLLRESERVED0 [31:02] */
-#define BCHP_CLKGEN_PLL_SDS_PLL_MISC2_PLLRESERVED0_MASK 0xfffffffc
-#define BCHP_CLKGEN_PLL_SDS_PLL_MISC2_PLLRESERVED0_SHIFT 2
-#define BCHP_CLKGEN_PLL_SDS_PLL_MISC2_PLLRESERVED0_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_SDS_PLL_MISC2 :: LDO [01:00] */
-#define BCHP_CLKGEN_PLL_SDS_PLL_MISC2_LDO_MASK 0x00000003
-#define BCHP_CLKGEN_PLL_SDS_PLL_MISC2_LDO_SHIFT 0
-#define BCHP_CLKGEN_PLL_SDS_PLL_MISC2_LDO_DEFAULT 0x00000001
-
-/***************************************************************************
- *PLL_SDS_PLL_PWRON - Poweron
- ***************************************************************************/
-/* CLKGEN :: PLL_SDS_PLL_PWRON :: reserved0 [31:01] */
-#define BCHP_CLKGEN_PLL_SDS_PLL_PWRON_reserved0_MASK 0xfffffffe
-#define BCHP_CLKGEN_PLL_SDS_PLL_PWRON_reserved0_SHIFT 1
-
-/* CLKGEN :: PLL_SDS_PLL_PWRON :: PWRON_PLL [00:00] */
-#define BCHP_CLKGEN_PLL_SDS_PLL_PWRON_PWRON_PLL_MASK 0x00000001
-#define BCHP_CLKGEN_PLL_SDS_PLL_PWRON_PWRON_PLL_SHIFT 0
-#define BCHP_CLKGEN_PLL_SDS_PLL_PWRON_PWRON_PLL_DEFAULT 0x00000001
-
-/***************************************************************************
- *PLL_SDS_PLL_RESET - Resets
- ***************************************************************************/
-/* CLKGEN :: PLL_SDS_PLL_RESET :: reserved0 [31:02] */
-#define BCHP_CLKGEN_PLL_SDS_PLL_RESET_reserved0_MASK 0xfffffffc
-#define BCHP_CLKGEN_PLL_SDS_PLL_RESET_reserved0_SHIFT 2
-
-/* CLKGEN :: PLL_SDS_PLL_RESET :: RESETD [01:01] */
-#define BCHP_CLKGEN_PLL_SDS_PLL_RESET_RESETD_MASK 0x00000002
-#define BCHP_CLKGEN_PLL_SDS_PLL_RESET_RESETD_SHIFT 1
-#define BCHP_CLKGEN_PLL_SDS_PLL_RESET_RESETD_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_SDS_PLL_RESET :: RESETA [00:00] */
-#define BCHP_CLKGEN_PLL_SDS_PLL_RESET_RESETA_MASK 0x00000001
-#define BCHP_CLKGEN_PLL_SDS_PLL_RESET_RESETA_SHIFT 0
-#define BCHP_CLKGEN_PLL_SDS_PLL_RESET_RESETA_DEFAULT 0x00000000
-
-/***************************************************************************
- *PLL_SDS_PLL_SSC_MODE_CONTROL_HIGH - Higher bits of Spread Spectrum mode control
- ***************************************************************************/
-/* CLKGEN :: PLL_SDS_PLL_SSC_MODE_CONTROL_HIGH :: reserved0 [31:16] */
-#define BCHP_CLKGEN_PLL_SDS_PLL_SSC_MODE_CONTROL_HIGH_reserved0_MASK 0xffff0000
-#define BCHP_CLKGEN_PLL_SDS_PLL_SSC_MODE_CONTROL_HIGH_reserved0_SHIFT 16
-
-/* CLKGEN :: PLL_SDS_PLL_SSC_MODE_CONTROL_HIGH :: SSC_STEP [15:00] */
-#define BCHP_CLKGEN_PLL_SDS_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_MASK 0x0000ffff
-#define BCHP_CLKGEN_PLL_SDS_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_SHIFT 0
-#define BCHP_CLKGEN_PLL_SDS_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *PLL_SDS_PLL_SSC_MODE_CONTROL_LOW - Lower bits of Spread Spectrum mode control
- ***************************************************************************/
-/* CLKGEN :: PLL_SDS_PLL_SSC_MODE_CONTROL_LOW :: reserved0 [31:23] */
-#define BCHP_CLKGEN_PLL_SDS_PLL_SSC_MODE_CONTROL_LOW_reserved0_MASK 0xff800000
-#define BCHP_CLKGEN_PLL_SDS_PLL_SSC_MODE_CONTROL_LOW_reserved0_SHIFT 23
-
-/* CLKGEN :: PLL_SDS_PLL_SSC_MODE_CONTROL_LOW :: SSC_MODE [22:22] */
-#define BCHP_CLKGEN_PLL_SDS_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_MASK 0x00400000
-#define BCHP_CLKGEN_PLL_SDS_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_SHIFT 22
-#define BCHP_CLKGEN_PLL_SDS_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_SDS_PLL_SSC_MODE_CONTROL_LOW :: SSC_LIMIT [21:00] */
-#define BCHP_CLKGEN_PLL_SDS_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_MASK 0x003fffff
-#define BCHP_CLKGEN_PLL_SDS_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_SHIFT 0
-#define BCHP_CLKGEN_PLL_SDS_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_DEFAULT 0x00000000
-
-/***************************************************************************
- *PLL_SDS_PLL_STATUS - Status
- ***************************************************************************/
-/* CLKGEN :: PLL_SDS_PLL_STATUS :: reserved0 [31:12] */
-#define BCHP_CLKGEN_PLL_SDS_PLL_STATUS_reserved0_MASK 0xfffff000
-#define BCHP_CLKGEN_PLL_SDS_PLL_STATUS_reserved0_SHIFT 12
-
-/* CLKGEN :: PLL_SDS_PLL_STATUS :: TEST_STATUS [11:00] */
-#define BCHP_CLKGEN_PLL_SDS_PLL_STATUS_TEST_STATUS_MASK 0x00000fff
-#define BCHP_CLKGEN_PLL_SDS_PLL_STATUS_TEST_STATUS_SHIFT 0
-
-/***************************************************************************
- *PLL_SYS0_PLL_BG_PWRON - Bandgap Power on
- ***************************************************************************/
-/* CLKGEN :: PLL_SYS0_PLL_BG_PWRON :: reserved0 [31:01] */
-#define BCHP_CLKGEN_PLL_SYS0_PLL_BG_PWRON_reserved0_MASK 0xfffffffe
-#define BCHP_CLKGEN_PLL_SYS0_PLL_BG_PWRON_reserved0_SHIFT 1
-
-/* CLKGEN :: PLL_SYS0_PLL_BG_PWRON :: BG_PWRON_PLL [00:00] */
-#define BCHP_CLKGEN_PLL_SYS0_PLL_BG_PWRON_BG_PWRON_PLL_MASK 0x00000001
-#define BCHP_CLKGEN_PLL_SYS0_PLL_BG_PWRON_BG_PWRON_PLL_SHIFT 0
-#define BCHP_CLKGEN_PLL_SYS0_PLL_BG_PWRON_BG_PWRON_PLL_DEFAULT 0x00000001
-
-/***************************************************************************
- *PLL_SYS0_PLL_CHANNEL_CTRL_CH_0 - PLL CHANNEL control CH 0
- ***************************************************************************/
-/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_0 :: reserved0 [31:11] */
-#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_0_reserved0_MASK 0xfffff800
-#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_0_reserved0_SHIFT 11
-
-/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_0 :: POST_DIVIDER_HOLD_CH0 [10:10] */
-#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_MASK 0x00000400
-#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_SHIFT 10
-#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_0 :: PHASE_OFFSET_CH0 [09:09] */
-#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_MASK 0x00000200
-#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_SHIFT 9
-#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_0 :: MDIV_CH0 [08:01] */
-#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_MASK 0x000001fe
-#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_SHIFT 1
-#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_DEFAULT 0x0000000f
-
-/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_0 :: CLOCK_DIS_CH0 [00:00] */
-#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_MASK 0x00000001
-#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_SHIFT 0
-#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_DEFAULT 0x00000000
-
-/***************************************************************************
- *PLL_SYS0_PLL_CHANNEL_CTRL_CH_1 - PLL CHANNEL control CH 1
- ***************************************************************************/
-/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_1 :: reserved0 [31:11] */
-#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_1_reserved0_MASK 0xfffff800
-#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_1_reserved0_SHIFT 11
-
-/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_1 :: POST_DIVIDER_HOLD_CH1 [10:10] */
-#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_MASK 0x00000400
-#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_SHIFT 10
-#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_1 :: PHASE_OFFSET_CH1 [09:09] */
-#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_MASK 0x00000200
-#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_SHIFT 9
-#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_1 :: MDIV_CH1 [08:01] */
-#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_MASK 0x000001fe
-#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_SHIFT 1
-#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_DEFAULT 0x0000000a
-
-/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_1 :: CLOCK_DIS_CH1 [00:00] */
-#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_MASK 0x00000001
-#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_SHIFT 0
-#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_DEFAULT 0x00000000
-
-/***************************************************************************
- *PLL_SYS0_PLL_CHANNEL_CTRL_CH_2 - PLL CHANNEL control CH 2
- ***************************************************************************/
-/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_2 :: reserved0 [31:11] */
-#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2_reserved0_MASK 0xfffff800
-#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2_reserved0_SHIFT 11
-
-/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_2 :: POST_DIVIDER_HOLD_CH2 [10:10] */
-#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_HOLD_CH2_MASK 0x00000400
-#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_HOLD_CH2_SHIFT 10
-#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_HOLD_CH2_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_2 :: PHASE_OFFSET_CH2 [09:09] */
-#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2_PHASE_OFFSET_CH2_MASK 0x00000200
-#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2_PHASE_OFFSET_CH2_SHIFT 9
-#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2_PHASE_OFFSET_CH2_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_2 :: MDIV_CH2 [08:01] */
-#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2_MDIV_CH2_MASK 0x000001fe
-#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2_MDIV_CH2_SHIFT 1
-#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2_MDIV_CH2_DEFAULT 0x0000000a
-
-/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_2 :: CLOCK_DIS_CH2 [00:00] */
-#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2_CLOCK_DIS_CH2_MASK 0x00000001
-#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2_CLOCK_DIS_CH2_SHIFT 0
-#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2_CLOCK_DIS_CH2_DEFAULT 0x00000000
-
-/***************************************************************************
- *PLL_SYS0_PLL_CHANNEL_CTRL_CH_3 - PLL CHANNEL control CH 3
- ***************************************************************************/
-/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_3 :: reserved0 [31:11] */
-#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3_reserved0_MASK 0xfffff800
-#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3_reserved0_SHIFT 11
-
-/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_3 :: POST_DIVIDER_HOLD_CH3 [10:10] */
-#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_HOLD_CH3_MASK 0x00000400
-#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_HOLD_CH3_SHIFT 10
-#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_HOLD_CH3_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_3 :: PHASE_OFFSET_CH3 [09:09] */
-#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3_PHASE_OFFSET_CH3_MASK 0x00000200
-#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3_PHASE_OFFSET_CH3_SHIFT 9
-#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3_PHASE_OFFSET_CH3_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_3 :: MDIV_CH3 [08:01] */
-#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3_MDIV_CH3_MASK 0x000001fe
-#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3_MDIV_CH3_SHIFT 1
-#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3_MDIV_CH3_DEFAULT 0x0000000a
-
-/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_3 :: CLOCK_DIS_CH3 [00:00] */
-#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3_CLOCK_DIS_CH3_MASK 0x00000001
-#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3_CLOCK_DIS_CH3_SHIFT 0
-#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3_CLOCK_DIS_CH3_DEFAULT 0x00000000
-
-/***************************************************************************
- *PLL_SYS0_PLL_CHANNEL_CTRL_CH_4 - PLL CHANNEL control CH 4
- ***************************************************************************/
-/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_4 :: reserved0 [31:11] */
-#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_4_reserved0_MASK 0xfffff800
-#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_4_reserved0_SHIFT 11
-
-/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_4 :: POST_DIVIDER_HOLD_CH4 [10:10] */
-#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_4_POST_DIVIDER_HOLD_CH4_MASK 0x00000400
-#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_4_POST_DIVIDER_HOLD_CH4_SHIFT 10
-#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_4_POST_DIVIDER_HOLD_CH4_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_4 :: PHASE_OFFSET_CH4 [09:09] */
-#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_4_PHASE_OFFSET_CH4_MASK 0x00000200
-#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_4_PHASE_OFFSET_CH4_SHIFT 9
-#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_4_PHASE_OFFSET_CH4_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_4 :: MDIV_CH4 [08:01] */
-#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_4_MDIV_CH4_MASK 0x000001fe
-#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_4_MDIV_CH4_SHIFT 1
-#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_4_MDIV_CH4_DEFAULT 0x0000000f
-
-/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_4 :: CLOCK_DIS_CH4 [00:00] */
-#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_4_CLOCK_DIS_CH4_MASK 0x00000001
-#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_4_CLOCK_DIS_CH4_SHIFT 0
-#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_4_CLOCK_DIS_CH4_DEFAULT 0x00000000
-
-/***************************************************************************
- *PLL_SYS0_PLL_CHANNEL_CTRL_CH_5 - PLL CHANNEL control CH 5
- ***************************************************************************/
-/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_5 :: reserved0 [31:11] */
-#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_5_reserved0_MASK 0xfffff800
-#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_5_reserved0_SHIFT 11
-
-/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_5 :: POST_DIVIDER_HOLD_CH5 [10:10] */
-#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_5_POST_DIVIDER_HOLD_CH5_MASK 0x00000400
-#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_5_POST_DIVIDER_HOLD_CH5_SHIFT 10
-#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_5_POST_DIVIDER_HOLD_CH5_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_5 :: PHASE_OFFSET_CH5 [09:09] */
-#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_5_PHASE_OFFSET_CH5_MASK 0x00000200
-#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_5_PHASE_OFFSET_CH5_SHIFT 9
-#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_5_PHASE_OFFSET_CH5_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_5 :: MDIV_CH5 [08:01] */
-#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_5_MDIV_CH5_MASK 0x000001fe
-#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_5_MDIV_CH5_SHIFT 1
-#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_5_MDIV_CH5_DEFAULT 0x00000005
-
-/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_5 :: CLOCK_DIS_CH5 [00:00] */
-#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_5_CLOCK_DIS_CH5_MASK 0x00000001
-#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_5_CLOCK_DIS_CH5_SHIFT 0
-#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_5_CLOCK_DIS_CH5_DEFAULT 0x00000000
-
-/***************************************************************************
- *PLL_SYS0_PLL_DIV - Pre multiplier
- ***************************************************************************/
-/* CLKGEN :: PLL_SYS0_PLL_DIV :: reserved0 [31:14] */
-#define BCHP_CLKGEN_PLL_SYS0_PLL_DIV_reserved0_MASK 0xffffc000
-#define BCHP_CLKGEN_PLL_SYS0_PLL_DIV_reserved0_SHIFT 14
-
-/* CLKGEN :: PLL_SYS0_PLL_DIV :: PDIV [13:10] */
-#define BCHP_CLKGEN_PLL_SYS0_PLL_DIV_PDIV_MASK 0x00003c00
-#define BCHP_CLKGEN_PLL_SYS0_PLL_DIV_PDIV_SHIFT 10
-#define BCHP_CLKGEN_PLL_SYS0_PLL_DIV_PDIV_DEFAULT 0x00000001
-
-/* CLKGEN :: PLL_SYS0_PLL_DIV :: NDIV_INT [09:00] */
-#define BCHP_CLKGEN_PLL_SYS0_PLL_DIV_NDIV_INT_MASK 0x000003ff
-#define BCHP_CLKGEN_PLL_SYS0_PLL_DIV_NDIV_INT_SHIFT 0
-#define BCHP_CLKGEN_PLL_SYS0_PLL_DIV_NDIV_INT_DEFAULT 0x0000003c
-
-/***************************************************************************
- *PLL_SYS0_PLL_GAIN - PLL GAIN
- ***************************************************************************/
-/* CLKGEN :: PLL_SYS0_PLL_GAIN :: reserved0 [31:10] */
-#define BCHP_CLKGEN_PLL_SYS0_PLL_GAIN_reserved0_MASK 0xfffffc00
-#define BCHP_CLKGEN_PLL_SYS0_PLL_GAIN_reserved0_SHIFT 10
-
-/* CLKGEN :: PLL_SYS0_PLL_GAIN :: LOOP_GAIN_PROPORTIONAL_IN_PHASE [09:06] */
-#define BCHP_CLKGEN_PLL_SYS0_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_MASK 0x000003c0
-#define BCHP_CLKGEN_PLL_SYS0_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_SHIFT 6
-#define BCHP_CLKGEN_PLL_SYS0_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_DEFAULT 0x00000008
-
-/* CLKGEN :: PLL_SYS0_PLL_GAIN :: LOOP_GAIN_IN_FREQ [05:03] */
-#define BCHP_CLKGEN_PLL_SYS0_PLL_GAIN_LOOP_GAIN_IN_FREQ_MASK 0x00000038
-#define BCHP_CLKGEN_PLL_SYS0_PLL_GAIN_LOOP_GAIN_IN_FREQ_SHIFT 3
-#define BCHP_CLKGEN_PLL_SYS0_PLL_GAIN_LOOP_GAIN_IN_FREQ_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_SYS0_PLL_GAIN :: LOOP_GAIN_INTEGRATOR_IN_PHASE [02:00] */
-#define BCHP_CLKGEN_PLL_SYS0_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_MASK 0x00000007
-#define BCHP_CLKGEN_PLL_SYS0_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_SHIFT 0
-#define BCHP_CLKGEN_PLL_SYS0_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_DEFAULT 0x00000003
-
-/***************************************************************************
- *PLL_SYS0_PLL_HOLD_CH_ALL - Hold PLL all channels
- ***************************************************************************/
-/* CLKGEN :: PLL_SYS0_PLL_HOLD_CH_ALL :: reserved0 [31:01] */
-#define BCHP_CLKGEN_PLL_SYS0_PLL_HOLD_CH_ALL_reserved0_MASK 0xfffffffe
-#define BCHP_CLKGEN_PLL_SYS0_PLL_HOLD_CH_ALL_reserved0_SHIFT 1
-
-/* CLKGEN :: PLL_SYS0_PLL_HOLD_CH_ALL :: HOLD_CH_ALL [00:00] */
-#define BCHP_CLKGEN_PLL_SYS0_PLL_HOLD_CH_ALL_HOLD_CH_ALL_MASK 0x00000001
-#define BCHP_CLKGEN_PLL_SYS0_PLL_HOLD_CH_ALL_HOLD_CH_ALL_SHIFT 0
-#define BCHP_CLKGEN_PLL_SYS0_PLL_HOLD_CH_ALL_HOLD_CH_ALL_DEFAULT 0x00000000
-
-/***************************************************************************
- *PLL_SYS0_PLL_LDO_CTRL - Ldo voltage control
- ***************************************************************************/
-/* CLKGEN :: PLL_SYS0_PLL_LDO_CTRL :: reserved0 [31:16] */
-#define BCHP_CLKGEN_PLL_SYS0_PLL_LDO_CTRL_reserved0_MASK 0xffff0000
-#define BCHP_CLKGEN_PLL_SYS0_PLL_LDO_CTRL_reserved0_SHIFT 16
-
-/* CLKGEN :: PLL_SYS0_PLL_LDO_CTRL :: LDO_CTRL [15:00] */
-#define BCHP_CLKGEN_PLL_SYS0_PLL_LDO_CTRL_LDO_CTRL_MASK 0x0000ffff
-#define BCHP_CLKGEN_PLL_SYS0_PLL_LDO_CTRL_LDO_CTRL_SHIFT 0
-#define BCHP_CLKGEN_PLL_SYS0_PLL_LDO_CTRL_LDO_CTRL_DEFAULT 0x00005005
-
-/***************************************************************************
- *PLL_SYS0_PLL_LDO_PWRON - LDO Power on
- ***************************************************************************/
-/* CLKGEN :: PLL_SYS0_PLL_LDO_PWRON :: reserved0 [31:01] */
-#define BCHP_CLKGEN_PLL_SYS0_PLL_LDO_PWRON_reserved0_MASK 0xfffffffe
-#define BCHP_CLKGEN_PLL_SYS0_PLL_LDO_PWRON_reserved0_SHIFT 1
-
-/* CLKGEN :: PLL_SYS0_PLL_LDO_PWRON :: LDO_PWRON_PLL [00:00] */
-#define BCHP_CLKGEN_PLL_SYS0_PLL_LDO_PWRON_LDO_PWRON_PLL_MASK 0x00000001
-#define BCHP_CLKGEN_PLL_SYS0_PLL_LDO_PWRON_LDO_PWRON_PLL_SHIFT 0
-#define BCHP_CLKGEN_PLL_SYS0_PLL_LDO_PWRON_LDO_PWRON_PLL_DEFAULT 0x00000001
-
-/***************************************************************************
- *PLL_SYS0_PLL_LOCK_STATUS - Lock Status
- ***************************************************************************/
-/* CLKGEN :: PLL_SYS0_PLL_LOCK_STATUS :: reserved0 [31:02] */
-#define BCHP_CLKGEN_PLL_SYS0_PLL_LOCK_STATUS_reserved0_MASK 0xfffffffc
-#define BCHP_CLKGEN_PLL_SYS0_PLL_LOCK_STATUS_reserved0_SHIFT 2
-
-/* CLKGEN :: PLL_SYS0_PLL_LOCK_STATUS :: LOCK_LOST [01:01] */
-#define BCHP_CLKGEN_PLL_SYS0_PLL_LOCK_STATUS_LOCK_LOST_MASK 0x00000002
-#define BCHP_CLKGEN_PLL_SYS0_PLL_LOCK_STATUS_LOCK_LOST_SHIFT 1
-
-/* CLKGEN :: PLL_SYS0_PLL_LOCK_STATUS :: LOCK [00:00] */
-#define BCHP_CLKGEN_PLL_SYS0_PLL_LOCK_STATUS_LOCK_MASK 0x00000001
-#define BCHP_CLKGEN_PLL_SYS0_PLL_LOCK_STATUS_LOCK_SHIFT 0
-
-/***************************************************************************
- *PLL_SYS0_PLL_MISC - Mscellaneous control bus.
- ***************************************************************************/
-/* CLKGEN :: PLL_SYS0_PLL_MISC :: VCO_RANGE_LOW [31:31] */
-#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_VCO_RANGE_LOW_MASK 0x80000000
-#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_VCO_RANGE_LOW_SHIFT 31
-#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_VCO_RANGE_LOW_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_SYS0_PLL_MISC :: VCO_RANGE_HIGH [30:30] */
-#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_VCO_RANGE_HIGH_MASK 0x40000000
-#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_VCO_RANGE_HIGH_SHIFT 30
-#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_VCO_RANGE_HIGH_DEFAULT 0x00000001
-
-/* CLKGEN :: PLL_SYS0_PLL_MISC :: VCO_DIV2 [29:29] */
-#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_VCO_DIV2_MASK 0x20000000
-#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_VCO_DIV2_SHIFT 29
-#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_VCO_DIV2_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_SYS0_PLL_MISC :: STAT_UPDATE [28:28] */
-#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_STAT_UPDATE_MASK 0x10000000
-#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_STAT_UPDATE_SHIFT 28
-#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_STAT_UPDATE_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_SYS0_PLL_MISC :: STAT_SELECT [27:25] */
-#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_STAT_SELECT_MASK 0x0e000000
-#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_STAT_SELECT_SHIFT 25
-#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_STAT_SELECT_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_SYS0_PLL_MISC :: STAT_RESET [24:24] */
-#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_STAT_RESET_MASK 0x01000000
-#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_STAT_RESET_SHIFT 24
-#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_STAT_RESET_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_SYS0_PLL_MISC :: STAT_MODE [23:22] */
-#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_STAT_MODE_MASK 0x00c00000
-#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_STAT_MODE_SHIFT 22
-#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_STAT_MODE_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_SYS0_PLL_MISC :: REF_ALT_OFFS [21:21] */
-#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_REF_ALT_OFFS_MASK 0x00200000
-#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_REF_ALT_OFFS_SHIFT 21
-#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_REF_ALT_OFFS_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_SYS0_PLL_MISC :: PWM_RATE [20:19] */
-#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_PWM_RATE_MASK 0x00180000
-#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_PWM_RATE_SHIFT 19
-#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_PWM_RATE_DEFAULT 0x00000001
-
-/* CLKGEN :: PLL_SYS0_PLL_MISC :: POST_CTRL_RESETB [18:17] */
-#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_POST_CTRL_RESETB_MASK 0x00060000
-#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_POST_CTRL_RESETB_SHIFT 17
-#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_POST_CTRL_RESETB_DEFAULT 0x00000003
-
-/* CLKGEN :: PLL_SYS0_PLL_MISC :: NDIV_RELOCK [16:16] */
-#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_NDIV_RELOCK_MASK 0x00010000
-#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_NDIV_RELOCK_SHIFT 16
-#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_NDIV_RELOCK_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_SYS0_PLL_MISC :: FAST_LOCK [15:15] */
-#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_FAST_LOCK_MASK 0x00008000
-#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_FAST_LOCK_SHIFT 15
-#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_FAST_LOCK_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_SYS0_PLL_MISC :: DITHER_DISABLE [14:14] */
-#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_DITHER_DISABLE_MASK 0x00004000
-#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_DITHER_DISABLE_SHIFT 14
-#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_DITHER_DISABLE_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_SYS0_PLL_MISC :: DCO_CTRL_BYPASS_ENABLE [13:13] */
-#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_MASK 0x00002000
-#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_SHIFT 13
-#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_SYS0_PLL_MISC :: DCO_CTRL_BYPASS [12:01] */
-#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_DCO_CTRL_BYPASS_MASK 0x00001ffe
-#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_DCO_CTRL_BYPASS_SHIFT 1
-#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_DCO_CTRL_BYPASS_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_SYS0_PLL_MISC :: AUX_CTRL [00:00] */
-#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_AUX_CTRL_MASK 0x00000001
-#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_AUX_CTRL_SHIFT 0
-#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_AUX_CTRL_DEFAULT 0x00000000
-
-/***************************************************************************
- *PLL_SYS0_PLL_MISC2 - Mscellaneous control bus continued.
- ***************************************************************************/
-/* CLKGEN :: PLL_SYS0_PLL_MISC2 :: PLLRESERVED0 [31:01] */
-#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC2_PLLRESERVED0_MASK 0xfffffffe
-#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC2_PLLRESERVED0_SHIFT 1
-#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC2_PLLRESERVED0_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_SYS0_PLL_MISC2 :: DIG_INPUT_SEL [00:00] */
-#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC2_DIG_INPUT_SEL_MASK 0x00000001
-#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC2_DIG_INPUT_SEL_SHIFT 0
-#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC2_DIG_INPUT_SEL_DEFAULT 0x00000000
-
-/***************************************************************************
- *PLL_SYS0_PLL_PWRON - Poweron
- ***************************************************************************/
-/* CLKGEN :: PLL_SYS0_PLL_PWRON :: reserved0 [31:01] */
-#define BCHP_CLKGEN_PLL_SYS0_PLL_PWRON_reserved0_MASK 0xfffffffe
-#define BCHP_CLKGEN_PLL_SYS0_PLL_PWRON_reserved0_SHIFT 1
-
-/* CLKGEN :: PLL_SYS0_PLL_PWRON :: PWRON_PLL [00:00] */
-#define BCHP_CLKGEN_PLL_SYS0_PLL_PWRON_PWRON_PLL_MASK 0x00000001
-#define BCHP_CLKGEN_PLL_SYS0_PLL_PWRON_PWRON_PLL_SHIFT 0
-#define BCHP_CLKGEN_PLL_SYS0_PLL_PWRON_PWRON_PLL_DEFAULT 0x00000001
-
-/***************************************************************************
- *PLL_SYS0_PLL_RESET - Resets
- ***************************************************************************/
-/* CLKGEN :: PLL_SYS0_PLL_RESET :: reserved0 [31:01] */
-#define BCHP_CLKGEN_PLL_SYS0_PLL_RESET_reserved0_MASK 0xfffffffe
-#define BCHP_CLKGEN_PLL_SYS0_PLL_RESET_reserved0_SHIFT 1
-
-/* CLKGEN :: PLL_SYS0_PLL_RESET :: RESETD [00:00] */
-#define BCHP_CLKGEN_PLL_SYS0_PLL_RESET_RESETD_MASK 0x00000001
-#define BCHP_CLKGEN_PLL_SYS0_PLL_RESET_RESETD_SHIFT 0
-#define BCHP_CLKGEN_PLL_SYS0_PLL_RESET_RESETD_DEFAULT 0x00000000
-
-/***************************************************************************
- *PLL_SYS0_PLL_SSC_MODE_CONTROL_HIGH - Higher bits of Spread Spectrum mode control
- ***************************************************************************/
-/* CLKGEN :: PLL_SYS0_PLL_SSC_MODE_CONTROL_HIGH :: reserved0 [31:16] */
-#define BCHP_CLKGEN_PLL_SYS0_PLL_SSC_MODE_CONTROL_HIGH_reserved0_MASK 0xffff0000
-#define BCHP_CLKGEN_PLL_SYS0_PLL_SSC_MODE_CONTROL_HIGH_reserved0_SHIFT 16
-
-/* CLKGEN :: PLL_SYS0_PLL_SSC_MODE_CONTROL_HIGH :: SSC_STEP [15:00] */
-#define BCHP_CLKGEN_PLL_SYS0_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_MASK 0x0000ffff
-#define BCHP_CLKGEN_PLL_SYS0_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_SHIFT 0
-#define BCHP_CLKGEN_PLL_SYS0_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *PLL_SYS0_PLL_SSC_MODE_CONTROL_LOW - Lower bits of Spread Spectrum mode control
- ***************************************************************************/
-/* CLKGEN :: PLL_SYS0_PLL_SSC_MODE_CONTROL_LOW :: reserved0 [31:23] */
-#define BCHP_CLKGEN_PLL_SYS0_PLL_SSC_MODE_CONTROL_LOW_reserved0_MASK 0xff800000
-#define BCHP_CLKGEN_PLL_SYS0_PLL_SSC_MODE_CONTROL_LOW_reserved0_SHIFT 23
-
-/* CLKGEN :: PLL_SYS0_PLL_SSC_MODE_CONTROL_LOW :: SSC_MODE [22:22] */
-#define BCHP_CLKGEN_PLL_SYS0_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_MASK 0x00400000
-#define BCHP_CLKGEN_PLL_SYS0_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_SHIFT 22
-#define BCHP_CLKGEN_PLL_SYS0_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_SYS0_PLL_SSC_MODE_CONTROL_LOW :: SSC_LIMIT [21:00] */
-#define BCHP_CLKGEN_PLL_SYS0_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_MASK 0x003fffff
-#define BCHP_CLKGEN_PLL_SYS0_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_SHIFT 0
-#define BCHP_CLKGEN_PLL_SYS0_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_DEFAULT 0x00000000
-
-/***************************************************************************
- *PLL_SYS0_PLL_STATUS - Status
- ***************************************************************************/
-/* CLKGEN :: PLL_SYS0_PLL_STATUS :: reserved0 [31:12] */
-#define BCHP_CLKGEN_PLL_SYS0_PLL_STATUS_reserved0_MASK 0xfffff000
-#define BCHP_CLKGEN_PLL_SYS0_PLL_STATUS_reserved0_SHIFT 12
-
-/* CLKGEN :: PLL_SYS0_PLL_STATUS :: TEST_STATUS [11:00] */
-#define BCHP_CLKGEN_PLL_SYS0_PLL_STATUS_TEST_STATUS_MASK 0x00000fff
-#define BCHP_CLKGEN_PLL_SYS0_PLL_STATUS_TEST_STATUS_SHIFT 0
-
-/***************************************************************************
- *PLL_V3D_PLL_CHANNEL_CTRL_CH_0 - PLL CHANNEL control CH 0
- ***************************************************************************/
-/* CLKGEN :: PLL_V3D_PLL_CHANNEL_CTRL_CH_0 :: reserved0 [31:11] */
-#define BCHP_CLKGEN_PLL_V3D_PLL_CHANNEL_CTRL_CH_0_reserved0_MASK 0xfffff800
-#define BCHP_CLKGEN_PLL_V3D_PLL_CHANNEL_CTRL_CH_0_reserved0_SHIFT 11
-
-/* CLKGEN :: PLL_V3D_PLL_CHANNEL_CTRL_CH_0 :: POST_DIVIDER_HOLD_CH0 [10:10] */
-#define BCHP_CLKGEN_PLL_V3D_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_MASK 0x00000400
-#define BCHP_CLKGEN_PLL_V3D_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_SHIFT 10
-#define BCHP_CLKGEN_PLL_V3D_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_V3D_PLL_CHANNEL_CTRL_CH_0 :: PHASE_OFFSET_CH0 [09:09] */
-#define BCHP_CLKGEN_PLL_V3D_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_MASK 0x00000200
-#define BCHP_CLKGEN_PLL_V3D_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_SHIFT 9
-#define BCHP_CLKGEN_PLL_V3D_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_V3D_PLL_CHANNEL_CTRL_CH_0 :: MDIV_CH0 [08:01] */
-#define BCHP_CLKGEN_PLL_V3D_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_MASK 0x000001fe
-#define BCHP_CLKGEN_PLL_V3D_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_SHIFT 1
-#define BCHP_CLKGEN_PLL_V3D_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_DEFAULT 0x00000008
-
-/* CLKGEN :: PLL_V3D_PLL_CHANNEL_CTRL_CH_0 :: CLOCK_DIS_CH0 [00:00] */
-#define BCHP_CLKGEN_PLL_V3D_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_MASK 0x00000001
-#define BCHP_CLKGEN_PLL_V3D_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_SHIFT 0
-#define BCHP_CLKGEN_PLL_V3D_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_DEFAULT 0x00000000
-
-/***************************************************************************
- *PLL_V3D_PLL_CHANNEL_CTRL_CH_1 - PLL CHANNEL control CH 1
- ***************************************************************************/
-/* CLKGEN :: PLL_V3D_PLL_CHANNEL_CTRL_CH_1 :: reserved0 [31:11] */
-#define BCHP_CLKGEN_PLL_V3D_PLL_CHANNEL_CTRL_CH_1_reserved0_MASK 0xfffff800
-#define BCHP_CLKGEN_PLL_V3D_PLL_CHANNEL_CTRL_CH_1_reserved0_SHIFT 11
-
-/* CLKGEN :: PLL_V3D_PLL_CHANNEL_CTRL_CH_1 :: POST_DIVIDER_HOLD_CH1 [10:10] */
-#define BCHP_CLKGEN_PLL_V3D_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_MASK 0x00000400
-#define BCHP_CLKGEN_PLL_V3D_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_SHIFT 10
-#define BCHP_CLKGEN_PLL_V3D_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_V3D_PLL_CHANNEL_CTRL_CH_1 :: PHASE_OFFSET_CH1 [09:09] */
-#define BCHP_CLKGEN_PLL_V3D_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_MASK 0x00000200
-#define BCHP_CLKGEN_PLL_V3D_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_SHIFT 9
-#define BCHP_CLKGEN_PLL_V3D_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_V3D_PLL_CHANNEL_CTRL_CH_1 :: MDIV_CH1 [08:01] */
-#define BCHP_CLKGEN_PLL_V3D_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_MASK 0x000001fe
-#define BCHP_CLKGEN_PLL_V3D_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_SHIFT 1
-#define BCHP_CLKGEN_PLL_V3D_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_DEFAULT 0x0000001e
-
-/* CLKGEN :: PLL_V3D_PLL_CHANNEL_CTRL_CH_1 :: CLOCK_DIS_CH1 [00:00] */
-#define BCHP_CLKGEN_PLL_V3D_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_MASK 0x00000001
-#define BCHP_CLKGEN_PLL_V3D_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_SHIFT 0
-#define BCHP_CLKGEN_PLL_V3D_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_DEFAULT 0x00000000
-
-/***************************************************************************
- *PLL_V3D_PLL_CHANNEL_CTRL_CH_2 - PLL CHANNEL control CH 2
- ***************************************************************************/
-/* CLKGEN :: PLL_V3D_PLL_CHANNEL_CTRL_CH_2 :: reserved0 [31:11] */
-#define BCHP_CLKGEN_PLL_V3D_PLL_CHANNEL_CTRL_CH_2_reserved0_MASK 0xfffff800
-#define BCHP_CLKGEN_PLL_V3D_PLL_CHANNEL_CTRL_CH_2_reserved0_SHIFT 11
-
-/* CLKGEN :: PLL_V3D_PLL_CHANNEL_CTRL_CH_2 :: POST_DIVIDER_HOLD_CH2 [10:10] */
-#define BCHP_CLKGEN_PLL_V3D_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_HOLD_CH2_MASK 0x00000400
-#define BCHP_CLKGEN_PLL_V3D_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_HOLD_CH2_SHIFT 10
-#define BCHP_CLKGEN_PLL_V3D_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_HOLD_CH2_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_V3D_PLL_CHANNEL_CTRL_CH_2 :: PHASE_OFFSET_CH2 [09:09] */
-#define BCHP_CLKGEN_PLL_V3D_PLL_CHANNEL_CTRL_CH_2_PHASE_OFFSET_CH2_MASK 0x00000200
-#define BCHP_CLKGEN_PLL_V3D_PLL_CHANNEL_CTRL_CH_2_PHASE_OFFSET_CH2_SHIFT 9
-#define BCHP_CLKGEN_PLL_V3D_PLL_CHANNEL_CTRL_CH_2_PHASE_OFFSET_CH2_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_V3D_PLL_CHANNEL_CTRL_CH_2 :: MDIV_CH2 [08:01] */
-#define BCHP_CLKGEN_PLL_V3D_PLL_CHANNEL_CTRL_CH_2_MDIV_CH2_MASK 0x000001fe
-#define BCHP_CLKGEN_PLL_V3D_PLL_CHANNEL_CTRL_CH_2_MDIV_CH2_SHIFT 1
-#define BCHP_CLKGEN_PLL_V3D_PLL_CHANNEL_CTRL_CH_2_MDIV_CH2_DEFAULT 0x0000000a
-
-/* CLKGEN :: PLL_V3D_PLL_CHANNEL_CTRL_CH_2 :: CLOCK_DIS_CH2 [00:00] */
-#define BCHP_CLKGEN_PLL_V3D_PLL_CHANNEL_CTRL_CH_2_CLOCK_DIS_CH2_MASK 0x00000001
-#define BCHP_CLKGEN_PLL_V3D_PLL_CHANNEL_CTRL_CH_2_CLOCK_DIS_CH2_SHIFT 0
-#define BCHP_CLKGEN_PLL_V3D_PLL_CHANNEL_CTRL_CH_2_CLOCK_DIS_CH2_DEFAULT 0x00000000
-
-/***************************************************************************
- *PLL_V3D_PLL_CHANNEL_CTRL_CH_5 - PLL CHANNEL control CH 5
- ***************************************************************************/
-/* CLKGEN :: PLL_V3D_PLL_CHANNEL_CTRL_CH_5 :: reserved0 [31:11] */
-#define BCHP_CLKGEN_PLL_V3D_PLL_CHANNEL_CTRL_CH_5_reserved0_MASK 0xfffff800
-#define BCHP_CLKGEN_PLL_V3D_PLL_CHANNEL_CTRL_CH_5_reserved0_SHIFT 11
-
-/* CLKGEN :: PLL_V3D_PLL_CHANNEL_CTRL_CH_5 :: POST_DIVIDER_HOLD_CH5 [10:10] */
-#define BCHP_CLKGEN_PLL_V3D_PLL_CHANNEL_CTRL_CH_5_POST_DIVIDER_HOLD_CH5_MASK 0x00000400
-#define BCHP_CLKGEN_PLL_V3D_PLL_CHANNEL_CTRL_CH_5_POST_DIVIDER_HOLD_CH5_SHIFT 10
-#define BCHP_CLKGEN_PLL_V3D_PLL_CHANNEL_CTRL_CH_5_POST_DIVIDER_HOLD_CH5_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_V3D_PLL_CHANNEL_CTRL_CH_5 :: PHASE_OFFSET_CH5 [09:09] */
-#define BCHP_CLKGEN_PLL_V3D_PLL_CHANNEL_CTRL_CH_5_PHASE_OFFSET_CH5_MASK 0x00000200
-#define BCHP_CLKGEN_PLL_V3D_PLL_CHANNEL_CTRL_CH_5_PHASE_OFFSET_CH5_SHIFT 9
-#define BCHP_CLKGEN_PLL_V3D_PLL_CHANNEL_CTRL_CH_5_PHASE_OFFSET_CH5_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_V3D_PLL_CHANNEL_CTRL_CH_5 :: MDIV_CH5 [08:01] */
-#define BCHP_CLKGEN_PLL_V3D_PLL_CHANNEL_CTRL_CH_5_MDIV_CH5_MASK 0x000001fe
-#define BCHP_CLKGEN_PLL_V3D_PLL_CHANNEL_CTRL_CH_5_MDIV_CH5_SHIFT 1
-#define BCHP_CLKGEN_PLL_V3D_PLL_CHANNEL_CTRL_CH_5_MDIV_CH5_DEFAULT 0x00000064
-
-/* CLKGEN :: PLL_V3D_PLL_CHANNEL_CTRL_CH_5 :: CLOCK_DIS_CH5 [00:00] */
-#define BCHP_CLKGEN_PLL_V3D_PLL_CHANNEL_CTRL_CH_5_CLOCK_DIS_CH5_MASK 0x00000001
-#define BCHP_CLKGEN_PLL_V3D_PLL_CHANNEL_CTRL_CH_5_CLOCK_DIS_CH5_SHIFT 0
-#define BCHP_CLKGEN_PLL_V3D_PLL_CHANNEL_CTRL_CH_5_CLOCK_DIS_CH5_DEFAULT 0x00000001
-
-/***************************************************************************
- *PLL_V3D_PLL_DIV - Pre multiplier
- ***************************************************************************/
-/* CLKGEN :: PLL_V3D_PLL_DIV :: reserved0 [31:14] */
-#define BCHP_CLKGEN_PLL_V3D_PLL_DIV_reserved0_MASK 0xffffc000
-#define BCHP_CLKGEN_PLL_V3D_PLL_DIV_reserved0_SHIFT 14
-
-/* CLKGEN :: PLL_V3D_PLL_DIV :: PDIV [13:10] */
-#define BCHP_CLKGEN_PLL_V3D_PLL_DIV_PDIV_MASK 0x00003c00
-#define BCHP_CLKGEN_PLL_V3D_PLL_DIV_PDIV_SHIFT 10
-#define BCHP_CLKGEN_PLL_V3D_PLL_DIV_PDIV_DEFAULT 0x00000001
-
-/* CLKGEN :: PLL_V3D_PLL_DIV :: NDIV_INT [09:00] */
-#define BCHP_CLKGEN_PLL_V3D_PLL_DIV_NDIV_INT_MASK 0x000003ff
-#define BCHP_CLKGEN_PLL_V3D_PLL_DIV_NDIV_INT_SHIFT 0
-#define BCHP_CLKGEN_PLL_V3D_PLL_DIV_NDIV_INT_DEFAULT 0x0000003c
-
-/***************************************************************************
- *PLL_V3D_PLL_GAIN - PLL GAIN
- ***************************************************************************/
-/* CLKGEN :: PLL_V3D_PLL_GAIN :: reserved0 [31:10] */
-#define BCHP_CLKGEN_PLL_V3D_PLL_GAIN_reserved0_MASK 0xfffffc00
-#define BCHP_CLKGEN_PLL_V3D_PLL_GAIN_reserved0_SHIFT 10
-
-/* CLKGEN :: PLL_V3D_PLL_GAIN :: LOOP_GAIN_PROPORTIONAL_IN_PHASE [09:06] */
-#define BCHP_CLKGEN_PLL_V3D_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_MASK 0x000003c0
-#define BCHP_CLKGEN_PLL_V3D_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_SHIFT 6
-#define BCHP_CLKGEN_PLL_V3D_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_DEFAULT 0x00000003
-
-/* CLKGEN :: PLL_V3D_PLL_GAIN :: LOOP_GAIN_IN_FREQ [05:03] */
-#define BCHP_CLKGEN_PLL_V3D_PLL_GAIN_LOOP_GAIN_IN_FREQ_MASK 0x00000038
-#define BCHP_CLKGEN_PLL_V3D_PLL_GAIN_LOOP_GAIN_IN_FREQ_SHIFT 3
-#define BCHP_CLKGEN_PLL_V3D_PLL_GAIN_LOOP_GAIN_IN_FREQ_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_V3D_PLL_GAIN :: LOOP_GAIN_INTEGRATOR_IN_PHASE [02:00] */
-#define BCHP_CLKGEN_PLL_V3D_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_MASK 0x00000007
-#define BCHP_CLKGEN_PLL_V3D_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_SHIFT 0
-#define BCHP_CLKGEN_PLL_V3D_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_DEFAULT 0x00000002
-
-/***************************************************************************
- *PLL_V3D_PLL_LDO_PWRON - LDO Power on
- ***************************************************************************/
-/* CLKGEN :: PLL_V3D_PLL_LDO_PWRON :: reserved0 [31:01] */
-#define BCHP_CLKGEN_PLL_V3D_PLL_LDO_PWRON_reserved0_MASK 0xfffffffe
-#define BCHP_CLKGEN_PLL_V3D_PLL_LDO_PWRON_reserved0_SHIFT 1
-
-/* CLKGEN :: PLL_V3D_PLL_LDO_PWRON :: LDO_PWRON_PLL [00:00] */
-#define BCHP_CLKGEN_PLL_V3D_PLL_LDO_PWRON_LDO_PWRON_PLL_MASK 0x00000001
-#define BCHP_CLKGEN_PLL_V3D_PLL_LDO_PWRON_LDO_PWRON_PLL_SHIFT 0
-#define BCHP_CLKGEN_PLL_V3D_PLL_LDO_PWRON_LDO_PWRON_PLL_DEFAULT 0x00000001
-
-/***************************************************************************
- *PLL_V3D_PLL_LOCK_STATUS - Lock Status
- ***************************************************************************/
-/* CLKGEN :: PLL_V3D_PLL_LOCK_STATUS :: reserved0 [31:02] */
-#define BCHP_CLKGEN_PLL_V3D_PLL_LOCK_STATUS_reserved0_MASK 0xfffffffc
-#define BCHP_CLKGEN_PLL_V3D_PLL_LOCK_STATUS_reserved0_SHIFT 2
-
-/* CLKGEN :: PLL_V3D_PLL_LOCK_STATUS :: LOCK_LOST [01:01] */
-#define BCHP_CLKGEN_PLL_V3D_PLL_LOCK_STATUS_LOCK_LOST_MASK 0x00000002
-#define BCHP_CLKGEN_PLL_V3D_PLL_LOCK_STATUS_LOCK_LOST_SHIFT 1
-
-/* CLKGEN :: PLL_V3D_PLL_LOCK_STATUS :: LOCK [00:00] */
-#define BCHP_CLKGEN_PLL_V3D_PLL_LOCK_STATUS_LOCK_MASK 0x00000001
-#define BCHP_CLKGEN_PLL_V3D_PLL_LOCK_STATUS_LOCK_SHIFT 0
-
-/***************************************************************************
- *PLL_V3D_PLL_MISC - Mscellaneous control bus.
- ***************************************************************************/
-/* CLKGEN :: PLL_V3D_PLL_MISC :: VCO_RANGE [31:30] */
-#define BCHP_CLKGEN_PLL_V3D_PLL_MISC_VCO_RANGE_MASK 0xc0000000
-#define BCHP_CLKGEN_PLL_V3D_PLL_MISC_VCO_RANGE_SHIFT 30
-#define BCHP_CLKGEN_PLL_V3D_PLL_MISC_VCO_RANGE_DEFAULT 0x00000002
-
-/* CLKGEN :: PLL_V3D_PLL_MISC :: VCO_FB_DIV2 [29:29] */
-#define BCHP_CLKGEN_PLL_V3D_PLL_MISC_VCO_FB_DIV2_MASK 0x20000000
-#define BCHP_CLKGEN_PLL_V3D_PLL_MISC_VCO_FB_DIV2_SHIFT 29
-#define BCHP_CLKGEN_PLL_V3D_PLL_MISC_VCO_FB_DIV2_DEFAULT 0x00000001
-
-/* CLKGEN :: PLL_V3D_PLL_MISC :: STAT_UPDATE [28:28] */
-#define BCHP_CLKGEN_PLL_V3D_PLL_MISC_STAT_UPDATE_MASK 0x10000000
-#define BCHP_CLKGEN_PLL_V3D_PLL_MISC_STAT_UPDATE_SHIFT 28
-#define BCHP_CLKGEN_PLL_V3D_PLL_MISC_STAT_UPDATE_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_V3D_PLL_MISC :: STAT_SELECT [27:25] */
-#define BCHP_CLKGEN_PLL_V3D_PLL_MISC_STAT_SELECT_MASK 0x0e000000
-#define BCHP_CLKGEN_PLL_V3D_PLL_MISC_STAT_SELECT_SHIFT 25
-#define BCHP_CLKGEN_PLL_V3D_PLL_MISC_STAT_SELECT_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_V3D_PLL_MISC :: STAT_RESET [24:24] */
-#define BCHP_CLKGEN_PLL_V3D_PLL_MISC_STAT_RESET_MASK 0x01000000
-#define BCHP_CLKGEN_PLL_V3D_PLL_MISC_STAT_RESET_SHIFT 24
-#define BCHP_CLKGEN_PLL_V3D_PLL_MISC_STAT_RESET_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_V3D_PLL_MISC :: STAT_MODE [23:22] */
-#define BCHP_CLKGEN_PLL_V3D_PLL_MISC_STAT_MODE_MASK 0x00c00000
-#define BCHP_CLKGEN_PLL_V3D_PLL_MISC_STAT_MODE_SHIFT 22
-#define BCHP_CLKGEN_PLL_V3D_PLL_MISC_STAT_MODE_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_V3D_PLL_MISC :: PWM_RATE [21:20] */
-#define BCHP_CLKGEN_PLL_V3D_PLL_MISC_PWM_RATE_MASK 0x00300000
-#define BCHP_CLKGEN_PLL_V3D_PLL_MISC_PWM_RATE_SHIFT 20
-#define BCHP_CLKGEN_PLL_V3D_PLL_MISC_PWM_RATE_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_V3D_PLL_MISC :: POST_CTRL_RESETB [19:18] */
-#define BCHP_CLKGEN_PLL_V3D_PLL_MISC_POST_CTRL_RESETB_MASK 0x000c0000
-#define BCHP_CLKGEN_PLL_V3D_PLL_MISC_POST_CTRL_RESETB_SHIFT 18
-#define BCHP_CLKGEN_PLL_V3D_PLL_MISC_POST_CTRL_RESETB_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_V3D_PLL_MISC :: PLLRESERVED2 [17:16] */
-#define BCHP_CLKGEN_PLL_V3D_PLL_MISC_PLLRESERVED2_MASK 0x00030000
-#define BCHP_CLKGEN_PLL_V3D_PLL_MISC_PLLRESERVED2_SHIFT 16
-#define BCHP_CLKGEN_PLL_V3D_PLL_MISC_PLLRESERVED2_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_V3D_PLL_MISC :: PLLRESERVED1 [15:15] */
-#define BCHP_CLKGEN_PLL_V3D_PLL_MISC_PLLRESERVED1_MASK 0x00008000
-#define BCHP_CLKGEN_PLL_V3D_PLL_MISC_PLLRESERVED1_SHIFT 15
-#define BCHP_CLKGEN_PLL_V3D_PLL_MISC_PLLRESERVED1_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_V3D_PLL_MISC :: NDIV_RELOCK [14:14] */
-#define BCHP_CLKGEN_PLL_V3D_PLL_MISC_NDIV_RELOCK_MASK 0x00004000
-#define BCHP_CLKGEN_PLL_V3D_PLL_MISC_NDIV_RELOCK_SHIFT 14
-#define BCHP_CLKGEN_PLL_V3D_PLL_MISC_NDIV_RELOCK_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_V3D_PLL_MISC :: FAST_LOCK [13:13] */
-#define BCHP_CLKGEN_PLL_V3D_PLL_MISC_FAST_LOCK_MASK 0x00002000
-#define BCHP_CLKGEN_PLL_V3D_PLL_MISC_FAST_LOCK_SHIFT 13
-#define BCHP_CLKGEN_PLL_V3D_PLL_MISC_FAST_LOCK_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_V3D_PLL_MISC :: DCO_CTRL_BYPASS_ENABLE [12:12] */
-#define BCHP_CLKGEN_PLL_V3D_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_MASK 0x00001000
-#define BCHP_CLKGEN_PLL_V3D_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_SHIFT 12
-#define BCHP_CLKGEN_PLL_V3D_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_V3D_PLL_MISC :: DCO_CTRL_BYPASS [11:00] */
-#define BCHP_CLKGEN_PLL_V3D_PLL_MISC_DCO_CTRL_BYPASS_MASK 0x00000fff
-#define BCHP_CLKGEN_PLL_V3D_PLL_MISC_DCO_CTRL_BYPASS_SHIFT 0
-#define BCHP_CLKGEN_PLL_V3D_PLL_MISC_DCO_CTRL_BYPASS_DEFAULT 0x00000000
-
-/***************************************************************************
- *PLL_V3D_PLL_MISC2 - Mscellaneous control bus continued.
- ***************************************************************************/
-/* CLKGEN :: PLL_V3D_PLL_MISC2 :: PLLRESERVED0 [31:02] */
-#define BCHP_CLKGEN_PLL_V3D_PLL_MISC2_PLLRESERVED0_MASK 0xfffffffc
-#define BCHP_CLKGEN_PLL_V3D_PLL_MISC2_PLLRESERVED0_SHIFT 2
-#define BCHP_CLKGEN_PLL_V3D_PLL_MISC2_PLLRESERVED0_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_V3D_PLL_MISC2 :: LDO [01:00] */
-#define BCHP_CLKGEN_PLL_V3D_PLL_MISC2_LDO_MASK 0x00000003
-#define BCHP_CLKGEN_PLL_V3D_PLL_MISC2_LDO_SHIFT 0
-#define BCHP_CLKGEN_PLL_V3D_PLL_MISC2_LDO_DEFAULT 0x00000001
-
-/***************************************************************************
- *PLL_V3D_PLL_PWRON - Poweron
- ***************************************************************************/
-/* CLKGEN :: PLL_V3D_PLL_PWRON :: reserved0 [31:01] */
-#define BCHP_CLKGEN_PLL_V3D_PLL_PWRON_reserved0_MASK 0xfffffffe
-#define BCHP_CLKGEN_PLL_V3D_PLL_PWRON_reserved0_SHIFT 1
-
-/* CLKGEN :: PLL_V3D_PLL_PWRON :: PWRON_PLL [00:00] */
-#define BCHP_CLKGEN_PLL_V3D_PLL_PWRON_PWRON_PLL_MASK 0x00000001
-#define BCHP_CLKGEN_PLL_V3D_PLL_PWRON_PWRON_PLL_SHIFT 0
-#define BCHP_CLKGEN_PLL_V3D_PLL_PWRON_PWRON_PLL_DEFAULT 0x00000001
-
-/***************************************************************************
- *PLL_V3D_PLL_RESET - Resets
- ***************************************************************************/
-/* CLKGEN :: PLL_V3D_PLL_RESET :: reserved0 [31:02] */
-#define BCHP_CLKGEN_PLL_V3D_PLL_RESET_reserved0_MASK 0xfffffffc
-#define BCHP_CLKGEN_PLL_V3D_PLL_RESET_reserved0_SHIFT 2
-
-/* CLKGEN :: PLL_V3D_PLL_RESET :: RESETD [01:01] */
-#define BCHP_CLKGEN_PLL_V3D_PLL_RESET_RESETD_MASK 0x00000002
-#define BCHP_CLKGEN_PLL_V3D_PLL_RESET_RESETD_SHIFT 1
-#define BCHP_CLKGEN_PLL_V3D_PLL_RESET_RESETD_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_V3D_PLL_RESET :: RESETA [00:00] */
-#define BCHP_CLKGEN_PLL_V3D_PLL_RESET_RESETA_MASK 0x00000001
-#define BCHP_CLKGEN_PLL_V3D_PLL_RESET_RESETA_SHIFT 0
-#define BCHP_CLKGEN_PLL_V3D_PLL_RESET_RESETA_DEFAULT 0x00000000
-
-/***************************************************************************
- *PLL_V3D_PLL_SSC_MODE_CONTROL_HIGH - Higher bits of Spread Spectrum mode control
- ***************************************************************************/
-/* CLKGEN :: PLL_V3D_PLL_SSC_MODE_CONTROL_HIGH :: reserved0 [31:16] */
-#define BCHP_CLKGEN_PLL_V3D_PLL_SSC_MODE_CONTROL_HIGH_reserved0_MASK 0xffff0000
-#define BCHP_CLKGEN_PLL_V3D_PLL_SSC_MODE_CONTROL_HIGH_reserved0_SHIFT 16
-
-/* CLKGEN :: PLL_V3D_PLL_SSC_MODE_CONTROL_HIGH :: SSC_STEP [15:00] */
-#define BCHP_CLKGEN_PLL_V3D_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_MASK 0x0000ffff
-#define BCHP_CLKGEN_PLL_V3D_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_SHIFT 0
-#define BCHP_CLKGEN_PLL_V3D_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *PLL_V3D_PLL_SSC_MODE_CONTROL_LOW - Lower bits of Spread Spectrum mode control
- ***************************************************************************/
-/* CLKGEN :: PLL_V3D_PLL_SSC_MODE_CONTROL_LOW :: reserved0 [31:23] */
-#define BCHP_CLKGEN_PLL_V3D_PLL_SSC_MODE_CONTROL_LOW_reserved0_MASK 0xff800000
-#define BCHP_CLKGEN_PLL_V3D_PLL_SSC_MODE_CONTROL_LOW_reserved0_SHIFT 23
-
-/* CLKGEN :: PLL_V3D_PLL_SSC_MODE_CONTROL_LOW :: SSC_MODE [22:22] */
-#define BCHP_CLKGEN_PLL_V3D_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_MASK 0x00400000
-#define BCHP_CLKGEN_PLL_V3D_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_SHIFT 22
-#define BCHP_CLKGEN_PLL_V3D_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_V3D_PLL_SSC_MODE_CONTROL_LOW :: SSC_LIMIT [21:00] */
-#define BCHP_CLKGEN_PLL_V3D_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_MASK 0x003fffff
-#define BCHP_CLKGEN_PLL_V3D_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_SHIFT 0
-#define BCHP_CLKGEN_PLL_V3D_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_DEFAULT 0x00000000
-
-/***************************************************************************
- *PLL_V3D_PLL_STATUS - Status
- ***************************************************************************/
-/* CLKGEN :: PLL_V3D_PLL_STATUS :: reserved0 [31:12] */
-#define BCHP_CLKGEN_PLL_V3D_PLL_STATUS_reserved0_MASK 0xfffff000
-#define BCHP_CLKGEN_PLL_V3D_PLL_STATUS_reserved0_SHIFT 12
-
-/* CLKGEN :: PLL_V3D_PLL_STATUS :: TEST_STATUS [11:00] */
-#define BCHP_CLKGEN_PLL_V3D_PLL_STATUS_TEST_STATUS_MASK 0x00000fff
-#define BCHP_CLKGEN_PLL_V3D_PLL_STATUS_TEST_STATUS_SHIFT 0
-
-/***************************************************************************
- *PLL_VCXO0_PLL_BG_PWRON - Bandgap Power on
- ***************************************************************************/
-/* CLKGEN :: PLL_VCXO0_PLL_BG_PWRON :: reserved0 [31:01] */
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_BG_PWRON_reserved0_MASK 0xfffffffe
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_BG_PWRON_reserved0_SHIFT 1
-
-/* CLKGEN :: PLL_VCXO0_PLL_BG_PWRON :: BG_PWRON_PLL [00:00] */
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_BG_PWRON_BG_PWRON_PLL_MASK 0x00000001
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_BG_PWRON_BG_PWRON_PLL_SHIFT 0
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_BG_PWRON_BG_PWRON_PLL_DEFAULT 0x00000001
-
-/***************************************************************************
- *PLL_VCXO0_PLL_CHANNEL_CTRL_CH_0 - PLL CHANNEL control CH 0
- ***************************************************************************/
-/* CLKGEN :: PLL_VCXO0_PLL_CHANNEL_CTRL_CH_0 :: reserved0 [31:11] */
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_CHANNEL_CTRL_CH_0_reserved0_MASK 0xfffff800
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_CHANNEL_CTRL_CH_0_reserved0_SHIFT 11
-
-/* CLKGEN :: PLL_VCXO0_PLL_CHANNEL_CTRL_CH_0 :: POST_DIVIDER_HOLD_CH0 [10:10] */
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_MASK 0x00000400
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_SHIFT 10
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_VCXO0_PLL_CHANNEL_CTRL_CH_0 :: PHASE_OFFSET_CH0 [09:09] */
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_MASK 0x00000200
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_SHIFT 9
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_VCXO0_PLL_CHANNEL_CTRL_CH_0 :: MDIV_CH0 [08:01] */
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_MASK 0x000001fe
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_SHIFT 1
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_DEFAULT 0x00000040
-
-/* CLKGEN :: PLL_VCXO0_PLL_CHANNEL_CTRL_CH_0 :: CLOCK_DIS_CH0 [00:00] */
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_MASK 0x00000001
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_SHIFT 0
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_DEFAULT 0x00000000
-
-/***************************************************************************
- *PLL_VCXO0_PLL_CHANNEL_CTRL_CH_1 - PLL CHANNEL control CH 1
- ***************************************************************************/
-/* CLKGEN :: PLL_VCXO0_PLL_CHANNEL_CTRL_CH_1 :: reserved0 [31:11] */
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_CHANNEL_CTRL_CH_1_reserved0_MASK 0xfffff800
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_CHANNEL_CTRL_CH_1_reserved0_SHIFT 11
-
-/* CLKGEN :: PLL_VCXO0_PLL_CHANNEL_CTRL_CH_1 :: POST_DIVIDER_HOLD_CH1 [10:10] */
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_MASK 0x00000400
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_SHIFT 10
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_VCXO0_PLL_CHANNEL_CTRL_CH_1 :: PHASE_OFFSET_CH1 [09:09] */
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_MASK 0x00000200
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_SHIFT 9
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_VCXO0_PLL_CHANNEL_CTRL_CH_1 :: MDIV_CH1 [08:01] */
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_MASK 0x000001fe
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_SHIFT 1
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_DEFAULT 0x000000fa
-
-/* CLKGEN :: PLL_VCXO0_PLL_CHANNEL_CTRL_CH_1 :: CLOCK_DIS_CH1 [00:00] */
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_MASK 0x00000001
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_SHIFT 0
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_DEFAULT 0x00000000
-
-/***************************************************************************
- *PLL_VCXO0_PLL_CHANNEL_CTRL_CH_2 - PLL CHANNEL control CH 2
- ***************************************************************************/
-/* CLKGEN :: PLL_VCXO0_PLL_CHANNEL_CTRL_CH_2 :: reserved0 [31:11] */
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_CHANNEL_CTRL_CH_2_reserved0_MASK 0xfffff800
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_CHANNEL_CTRL_CH_2_reserved0_SHIFT 11
-
-/* CLKGEN :: PLL_VCXO0_PLL_CHANNEL_CTRL_CH_2 :: POST_DIVIDER_HOLD_CH2 [10:10] */
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_HOLD_CH2_MASK 0x00000400
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_HOLD_CH2_SHIFT 10
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_HOLD_CH2_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_VCXO0_PLL_CHANNEL_CTRL_CH_2 :: PHASE_OFFSET_CH2 [09:09] */
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_CHANNEL_CTRL_CH_2_PHASE_OFFSET_CH2_MASK 0x00000200
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_CHANNEL_CTRL_CH_2_PHASE_OFFSET_CH2_SHIFT 9
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_CHANNEL_CTRL_CH_2_PHASE_OFFSET_CH2_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_VCXO0_PLL_CHANNEL_CTRL_CH_2 :: MDIV_CH2 [08:01] */
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_CHANNEL_CTRL_CH_2_MDIV_CH2_MASK 0x000001fe
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_CHANNEL_CTRL_CH_2_MDIV_CH2_SHIFT 1
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_CHANNEL_CTRL_CH_2_MDIV_CH2_DEFAULT 0x0000007d
-
-/* CLKGEN :: PLL_VCXO0_PLL_CHANNEL_CTRL_CH_2 :: CLOCK_DIS_CH2 [00:00] */
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_CHANNEL_CTRL_CH_2_CLOCK_DIS_CH2_MASK 0x00000001
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_CHANNEL_CTRL_CH_2_CLOCK_DIS_CH2_SHIFT 0
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_CHANNEL_CTRL_CH_2_CLOCK_DIS_CH2_DEFAULT 0x00000000
-
-/***************************************************************************
- *PLL_VCXO0_PLL_DIV - Pre multiplier
- ***************************************************************************/
-/* CLKGEN :: PLL_VCXO0_PLL_DIV :: reserved0 [31:14] */
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_DIV_reserved0_MASK 0xffffc000
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_DIV_reserved0_SHIFT 14
-
-/* CLKGEN :: PLL_VCXO0_PLL_DIV :: PDIV [13:10] */
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_DIV_PDIV_MASK 0x00003c00
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_DIV_PDIV_SHIFT 10
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_DIV_PDIV_DEFAULT 0x00000002
-
-/* CLKGEN :: PLL_VCXO0_PLL_DIV :: NDIV_INT [09:00] */
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_DIV_NDIV_INT_MASK 0x000003ff
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_DIV_NDIV_INT_SHIFT 0
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_DIV_NDIV_INT_DEFAULT 0x00000040
-
-/***************************************************************************
- *PLL_VCXO0_PLL_FRAC - Fractional
- ***************************************************************************/
-/* CLKGEN :: PLL_VCXO0_PLL_FRAC :: reserved0 [31:20] */
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_FRAC_reserved0_MASK 0xfff00000
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_FRAC_reserved0_SHIFT 20
-
-/* CLKGEN :: PLL_VCXO0_PLL_FRAC :: FRAC_CONTROL [19:00] */
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_FRAC_FRAC_CONTROL_MASK 0x000fffff
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_FRAC_FRAC_CONTROL_SHIFT 0
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_FRAC_FRAC_CONTROL_DEFAULT 0x00000000
-
-/***************************************************************************
- *PLL_VCXO0_PLL_GAIN - PLL GAIN
- ***************************************************************************/
-/* CLKGEN :: PLL_VCXO0_PLL_GAIN :: reserved0 [31:10] */
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_GAIN_reserved0_MASK 0xfffffc00
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_GAIN_reserved0_SHIFT 10
-
-/* CLKGEN :: PLL_VCXO0_PLL_GAIN :: LOOP_GAIN_PROPORTIONAL_IN_PHASE [09:06] */
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_MASK 0x000003c0
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_SHIFT 6
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_DEFAULT 0x00000007
-
-/* CLKGEN :: PLL_VCXO0_PLL_GAIN :: LOOP_GAIN_IN_FREQ [05:03] */
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_GAIN_LOOP_GAIN_IN_FREQ_MASK 0x00000038
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_GAIN_LOOP_GAIN_IN_FREQ_SHIFT 3
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_GAIN_LOOP_GAIN_IN_FREQ_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_VCXO0_PLL_GAIN :: LOOP_GAIN_INTEGRATOR_IN_PHASE [02:00] */
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_MASK 0x00000007
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_SHIFT 0
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_DEFAULT 0x00000004
-
-/***************************************************************************
- *PLL_VCXO0_PLL_HOLD_CH_ALL - Hold PLL all channels
- ***************************************************************************/
-/* CLKGEN :: PLL_VCXO0_PLL_HOLD_CH_ALL :: reserved0 [31:01] */
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_HOLD_CH_ALL_reserved0_MASK 0xfffffffe
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_HOLD_CH_ALL_reserved0_SHIFT 1
-
-/* CLKGEN :: PLL_VCXO0_PLL_HOLD_CH_ALL :: HOLD_CH_ALL [00:00] */
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_HOLD_CH_ALL_HOLD_CH_ALL_MASK 0x00000001
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_HOLD_CH_ALL_HOLD_CH_ALL_SHIFT 0
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_HOLD_CH_ALL_HOLD_CH_ALL_DEFAULT 0x00000000
-
-/***************************************************************************
- *PLL_VCXO0_PLL_LDO_CTRL - Ldo voltage control
- ***************************************************************************/
-/* CLKGEN :: PLL_VCXO0_PLL_LDO_CTRL :: reserved0 [31:16] */
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_LDO_CTRL_reserved0_MASK 0xffff0000
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_LDO_CTRL_reserved0_SHIFT 16
-
-/* CLKGEN :: PLL_VCXO0_PLL_LDO_CTRL :: LDO_CTRL [15:00] */
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_LDO_CTRL_LDO_CTRL_MASK 0x0000ffff
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_LDO_CTRL_LDO_CTRL_SHIFT 0
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_LDO_CTRL_LDO_CTRL_DEFAULT 0x00005005
-
-/***************************************************************************
- *PLL_VCXO0_PLL_LDO_PWRON - LDO Power on
- ***************************************************************************/
-/* CLKGEN :: PLL_VCXO0_PLL_LDO_PWRON :: reserved0 [31:01] */
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_LDO_PWRON_reserved0_MASK 0xfffffffe
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_LDO_PWRON_reserved0_SHIFT 1
-
-/* CLKGEN :: PLL_VCXO0_PLL_LDO_PWRON :: LDO_PWRON_PLL [00:00] */
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_LDO_PWRON_LDO_PWRON_PLL_MASK 0x00000001
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_LDO_PWRON_LDO_PWRON_PLL_SHIFT 0
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_LDO_PWRON_LDO_PWRON_PLL_DEFAULT 0x00000001
-
-/***************************************************************************
- *PLL_VCXO0_PLL_LOCK_STATUS - Lock Status
- ***************************************************************************/
-/* CLKGEN :: PLL_VCXO0_PLL_LOCK_STATUS :: reserved0 [31:02] */
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_LOCK_STATUS_reserved0_MASK 0xfffffffc
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_LOCK_STATUS_reserved0_SHIFT 2
-
-/* CLKGEN :: PLL_VCXO0_PLL_LOCK_STATUS :: LOCK_LOST [01:01] */
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_LOCK_STATUS_LOCK_LOST_MASK 0x00000002
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_LOCK_STATUS_LOCK_LOST_SHIFT 1
-
-/* CLKGEN :: PLL_VCXO0_PLL_LOCK_STATUS :: LOCK [00:00] */
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_LOCK_STATUS_LOCK_MASK 0x00000001
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_LOCK_STATUS_LOCK_SHIFT 0
-
-/***************************************************************************
- *PLL_VCXO0_PLL_MISC - Mscellaneous control bus.
- ***************************************************************************/
-/* CLKGEN :: PLL_VCXO0_PLL_MISC :: VCO_RANGE_LOW [31:31] */
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_MISC_VCO_RANGE_LOW_MASK 0x80000000
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_MISC_VCO_RANGE_LOW_SHIFT 31
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_MISC_VCO_RANGE_LOW_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_VCXO0_PLL_MISC :: VCO_RANGE_HIGH [30:30] */
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_MISC_VCO_RANGE_HIGH_MASK 0x40000000
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_MISC_VCO_RANGE_HIGH_SHIFT 30
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_MISC_VCO_RANGE_HIGH_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_VCXO0_PLL_MISC :: VCO_DIV2 [29:29] */
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_MISC_VCO_DIV2_MASK 0x20000000
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_MISC_VCO_DIV2_SHIFT 29
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_MISC_VCO_DIV2_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_VCXO0_PLL_MISC :: STAT_UPDATE [28:28] */
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_MISC_STAT_UPDATE_MASK 0x10000000
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_MISC_STAT_UPDATE_SHIFT 28
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_MISC_STAT_UPDATE_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_VCXO0_PLL_MISC :: STAT_SELECT [27:25] */
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_MISC_STAT_SELECT_MASK 0x0e000000
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_MISC_STAT_SELECT_SHIFT 25
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_MISC_STAT_SELECT_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_VCXO0_PLL_MISC :: STAT_RESET [24:24] */
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_MISC_STAT_RESET_MASK 0x01000000
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_MISC_STAT_RESET_SHIFT 24
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_MISC_STAT_RESET_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_VCXO0_PLL_MISC :: STAT_MODE [23:22] */
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_MISC_STAT_MODE_MASK 0x00c00000
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_MISC_STAT_MODE_SHIFT 22
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_MISC_STAT_MODE_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_VCXO0_PLL_MISC :: REF_ALT_OFFS [21:21] */
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_MISC_REF_ALT_OFFS_MASK 0x00200000
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_MISC_REF_ALT_OFFS_SHIFT 21
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_MISC_REF_ALT_OFFS_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_VCXO0_PLL_MISC :: PWM_RATE [20:19] */
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_MISC_PWM_RATE_MASK 0x00180000
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_MISC_PWM_RATE_SHIFT 19
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_MISC_PWM_RATE_DEFAULT 0x00000003
-
-/* CLKGEN :: PLL_VCXO0_PLL_MISC :: POST_CTRL_RESETB [18:17] */
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_MISC_POST_CTRL_RESETB_MASK 0x00060000
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_MISC_POST_CTRL_RESETB_SHIFT 17
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_MISC_POST_CTRL_RESETB_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_VCXO0_PLL_MISC :: NDIV_RELOCK [16:16] */
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_MISC_NDIV_RELOCK_MASK 0x00010000
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_MISC_NDIV_RELOCK_SHIFT 16
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_MISC_NDIV_RELOCK_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_VCXO0_PLL_MISC :: FAST_LOCK [15:15] */
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_MISC_FAST_LOCK_MASK 0x00008000
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_MISC_FAST_LOCK_SHIFT 15
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_MISC_FAST_LOCK_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_VCXO0_PLL_MISC :: DITHER_DISABLE [14:14] */
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_MISC_DITHER_DISABLE_MASK 0x00004000
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_MISC_DITHER_DISABLE_SHIFT 14
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_MISC_DITHER_DISABLE_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_VCXO0_PLL_MISC :: DCO_CTRL_BYPASS_ENABLE [13:13] */
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_MASK 0x00002000
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_SHIFT 13
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_VCXO0_PLL_MISC :: DCO_CTRL_BYPASS [12:01] */
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_MISC_DCO_CTRL_BYPASS_MASK 0x00001ffe
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_MISC_DCO_CTRL_BYPASS_SHIFT 1
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_MISC_DCO_CTRL_BYPASS_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_VCXO0_PLL_MISC :: AUX_CTRL [00:00] */
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_MISC_AUX_CTRL_MASK 0x00000001
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_MISC_AUX_CTRL_SHIFT 0
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_MISC_AUX_CTRL_DEFAULT 0x00000000
-
-/***************************************************************************
- *PLL_VCXO0_PLL_MISC2 - Mscellaneous control bus continued.
- ***************************************************************************/
-/* CLKGEN :: PLL_VCXO0_PLL_MISC2 :: PLLRESERVED0 [31:01] */
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_MISC2_PLLRESERVED0_MASK 0xfffffffe
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_MISC2_PLLRESERVED0_SHIFT 1
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_MISC2_PLLRESERVED0_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_VCXO0_PLL_MISC2 :: DIG_INPUT_SEL [00:00] */
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_MISC2_DIG_INPUT_SEL_MASK 0x00000001
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_MISC2_DIG_INPUT_SEL_SHIFT 0
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_MISC2_DIG_INPUT_SEL_DEFAULT 0x00000000
-
-/***************************************************************************
- *PLL_VCXO0_PLL_PWRON - Poweron
- ***************************************************************************/
-/* CLKGEN :: PLL_VCXO0_PLL_PWRON :: reserved0 [31:01] */
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_PWRON_reserved0_MASK 0xfffffffe
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_PWRON_reserved0_SHIFT 1
-
-/* CLKGEN :: PLL_VCXO0_PLL_PWRON :: PWRON_PLL [00:00] */
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_PWRON_PWRON_PLL_MASK 0x00000001
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_PWRON_PWRON_PLL_SHIFT 0
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_PWRON_PWRON_PLL_DEFAULT 0x00000001
-
-/***************************************************************************
- *PLL_VCXO0_PLL_RESET - Resets
- ***************************************************************************/
-/* CLKGEN :: PLL_VCXO0_PLL_RESET :: reserved0 [31:02] */
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_RESET_reserved0_MASK 0xfffffffc
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_RESET_reserved0_SHIFT 2
-
-/* CLKGEN :: PLL_VCXO0_PLL_RESET :: RESETD [01:01] */
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_RESET_RESETD_MASK 0x00000002
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_RESET_RESETD_SHIFT 1
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_RESET_RESETD_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_VCXO0_PLL_RESET :: RESETA [00:00] */
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_RESET_RESETA_MASK 0x00000001
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_RESET_RESETA_SHIFT 0
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_RESET_RESETA_DEFAULT 0x00000000
-
-/***************************************************************************
- *PLL_VCXO0_PLL_SSC_MODE_CONTROL_HIGH - Higher bits of Spread Spectrum mode control
- ***************************************************************************/
-/* CLKGEN :: PLL_VCXO0_PLL_SSC_MODE_CONTROL_HIGH :: reserved0 [31:16] */
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_SSC_MODE_CONTROL_HIGH_reserved0_MASK 0xffff0000
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_SSC_MODE_CONTROL_HIGH_reserved0_SHIFT 16
-
-/* CLKGEN :: PLL_VCXO0_PLL_SSC_MODE_CONTROL_HIGH :: SSC_STEP [15:00] */
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_MASK 0x0000ffff
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_SHIFT 0
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *PLL_VCXO0_PLL_SSC_MODE_CONTROL_LOW - Lower bits of Spread Spectrum mode control
- ***************************************************************************/
-/* CLKGEN :: PLL_VCXO0_PLL_SSC_MODE_CONTROL_LOW :: reserved0 [31:23] */
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_SSC_MODE_CONTROL_LOW_reserved0_MASK 0xff800000
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_SSC_MODE_CONTROL_LOW_reserved0_SHIFT 23
-
-/* CLKGEN :: PLL_VCXO0_PLL_SSC_MODE_CONTROL_LOW :: SSC_MODE [22:22] */
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_MASK 0x00400000
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_SHIFT 22
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_VCXO0_PLL_SSC_MODE_CONTROL_LOW :: SSC_LIMIT [21:00] */
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_MASK 0x003fffff
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_SHIFT 0
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_DEFAULT 0x00000000
-
-/***************************************************************************
- *PLL_VCXO0_PLL_STATUS - Status
- ***************************************************************************/
-/* CLKGEN :: PLL_VCXO0_PLL_STATUS :: reserved0 [31:12] */
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_STATUS_reserved0_MASK 0xfffff000
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_STATUS_reserved0_SHIFT 12
-
-/* CLKGEN :: PLL_VCXO0_PLL_STATUS :: TEST_STATUS [11:00] */
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_STATUS_TEST_STATUS_MASK 0x00000fff
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_STATUS_TEST_STATUS_SHIFT 0
-
-/***************************************************************************
- *PLL_VCXO1_PLL_BG_PWRON - Bandgap Power on
- ***************************************************************************/
-/* CLKGEN :: PLL_VCXO1_PLL_BG_PWRON :: reserved0 [31:01] */
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_BG_PWRON_reserved0_MASK 0xfffffffe
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_BG_PWRON_reserved0_SHIFT 1
-
-/* CLKGEN :: PLL_VCXO1_PLL_BG_PWRON :: BG_PWRON_PLL [00:00] */
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_BG_PWRON_BG_PWRON_PLL_MASK 0x00000001
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_BG_PWRON_BG_PWRON_PLL_SHIFT 0
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_BG_PWRON_BG_PWRON_PLL_DEFAULT 0x00000001
-
-/***************************************************************************
- *PLL_VCXO1_PLL_CHANNEL_CTRL_CH_0 - PLL CHANNEL control CH 0
- ***************************************************************************/
-/* CLKGEN :: PLL_VCXO1_PLL_CHANNEL_CTRL_CH_0 :: reserved0 [31:11] */
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_CHANNEL_CTRL_CH_0_reserved0_MASK 0xfffff800
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_CHANNEL_CTRL_CH_0_reserved0_SHIFT 11
-
-/* CLKGEN :: PLL_VCXO1_PLL_CHANNEL_CTRL_CH_0 :: POST_DIVIDER_HOLD_CH0 [10:10] */
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_MASK 0x00000400
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_SHIFT 10
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_VCXO1_PLL_CHANNEL_CTRL_CH_0 :: PHASE_OFFSET_CH0 [09:09] */
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_MASK 0x00000200
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_SHIFT 9
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_VCXO1_PLL_CHANNEL_CTRL_CH_0 :: MDIV_CH0 [08:01] */
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_MASK 0x000001fe
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_SHIFT 1
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_DEFAULT 0x00000040
-
-/* CLKGEN :: PLL_VCXO1_PLL_CHANNEL_CTRL_CH_0 :: CLOCK_DIS_CH0 [00:00] */
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_MASK 0x00000001
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_SHIFT 0
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_DEFAULT 0x00000000
-
-/***************************************************************************
- *PLL_VCXO1_PLL_CHANNEL_CTRL_CH_1 - PLL CHANNEL control CH 1
- ***************************************************************************/
-/* CLKGEN :: PLL_VCXO1_PLL_CHANNEL_CTRL_CH_1 :: reserved0 [31:11] */
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_CHANNEL_CTRL_CH_1_reserved0_MASK 0xfffff800
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_CHANNEL_CTRL_CH_1_reserved0_SHIFT 11
-
-/* CLKGEN :: PLL_VCXO1_PLL_CHANNEL_CTRL_CH_1 :: POST_DIVIDER_HOLD_CH1 [10:10] */
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_MASK 0x00000400
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_SHIFT 10
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_VCXO1_PLL_CHANNEL_CTRL_CH_1 :: PHASE_OFFSET_CH1 [09:09] */
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_MASK 0x00000200
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_SHIFT 9
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_VCXO1_PLL_CHANNEL_CTRL_CH_1 :: MDIV_CH1 [08:01] */
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_MASK 0x000001fe
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_SHIFT 1
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_DEFAULT 0x000000fa
-
-/* CLKGEN :: PLL_VCXO1_PLL_CHANNEL_CTRL_CH_1 :: CLOCK_DIS_CH1 [00:00] */
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_MASK 0x00000001
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_SHIFT 0
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_DEFAULT 0x00000000
-
-/***************************************************************************
- *PLL_VCXO1_PLL_CHANNEL_CTRL_CH_2 - PLL CHANNEL control CH 2
- ***************************************************************************/
-/* CLKGEN :: PLL_VCXO1_PLL_CHANNEL_CTRL_CH_2 :: reserved0 [31:11] */
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_CHANNEL_CTRL_CH_2_reserved0_MASK 0xfffff800
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_CHANNEL_CTRL_CH_2_reserved0_SHIFT 11
-
-/* CLKGEN :: PLL_VCXO1_PLL_CHANNEL_CTRL_CH_2 :: POST_DIVIDER_HOLD_CH2 [10:10] */
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_HOLD_CH2_MASK 0x00000400
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_HOLD_CH2_SHIFT 10
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_HOLD_CH2_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_VCXO1_PLL_CHANNEL_CTRL_CH_2 :: PHASE_OFFSET_CH2 [09:09] */
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_CHANNEL_CTRL_CH_2_PHASE_OFFSET_CH2_MASK 0x00000200
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_CHANNEL_CTRL_CH_2_PHASE_OFFSET_CH2_SHIFT 9
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_CHANNEL_CTRL_CH_2_PHASE_OFFSET_CH2_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_VCXO1_PLL_CHANNEL_CTRL_CH_2 :: MDIV_CH2 [08:01] */
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_CHANNEL_CTRL_CH_2_MDIV_CH2_MASK 0x000001fe
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_CHANNEL_CTRL_CH_2_MDIV_CH2_SHIFT 1
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_CHANNEL_CTRL_CH_2_MDIV_CH2_DEFAULT 0x0000007d
-
-/* CLKGEN :: PLL_VCXO1_PLL_CHANNEL_CTRL_CH_2 :: CLOCK_DIS_CH2 [00:00] */
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_CHANNEL_CTRL_CH_2_CLOCK_DIS_CH2_MASK 0x00000001
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_CHANNEL_CTRL_CH_2_CLOCK_DIS_CH2_SHIFT 0
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_CHANNEL_CTRL_CH_2_CLOCK_DIS_CH2_DEFAULT 0x00000000
-
-/***************************************************************************
- *PLL_VCXO1_PLL_DIV - Pre multiplier
- ***************************************************************************/
-/* CLKGEN :: PLL_VCXO1_PLL_DIV :: reserved0 [31:14] */
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_DIV_reserved0_MASK 0xffffc000
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_DIV_reserved0_SHIFT 14
-
-/* CLKGEN :: PLL_VCXO1_PLL_DIV :: PDIV [13:10] */
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_DIV_PDIV_MASK 0x00003c00
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_DIV_PDIV_SHIFT 10
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_DIV_PDIV_DEFAULT 0x00000002
-
-/* CLKGEN :: PLL_VCXO1_PLL_DIV :: NDIV_INT [09:00] */
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_DIV_NDIV_INT_MASK 0x000003ff
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_DIV_NDIV_INT_SHIFT 0
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_DIV_NDIV_INT_DEFAULT 0x00000040
-
-/***************************************************************************
- *PLL_VCXO1_PLL_FRAC - Fractional
- ***************************************************************************/
-/* CLKGEN :: PLL_VCXO1_PLL_FRAC :: reserved0 [31:20] */
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_FRAC_reserved0_MASK 0xfff00000
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_FRAC_reserved0_SHIFT 20
-
-/* CLKGEN :: PLL_VCXO1_PLL_FRAC :: FRAC_CONTROL [19:00] */
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_FRAC_FRAC_CONTROL_MASK 0x000fffff
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_FRAC_FRAC_CONTROL_SHIFT 0
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_FRAC_FRAC_CONTROL_DEFAULT 0x00000000
-
-/***************************************************************************
- *PLL_VCXO1_PLL_GAIN - PLL GAIN
- ***************************************************************************/
-/* CLKGEN :: PLL_VCXO1_PLL_GAIN :: reserved0 [31:10] */
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_GAIN_reserved0_MASK 0xfffffc00
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_GAIN_reserved0_SHIFT 10
-
-/* CLKGEN :: PLL_VCXO1_PLL_GAIN :: LOOP_GAIN_PROPORTIONAL_IN_PHASE [09:06] */
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_MASK 0x000003c0
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_SHIFT 6
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_DEFAULT 0x00000007
-
-/* CLKGEN :: PLL_VCXO1_PLL_GAIN :: LOOP_GAIN_IN_FREQ [05:03] */
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_GAIN_LOOP_GAIN_IN_FREQ_MASK 0x00000038
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_GAIN_LOOP_GAIN_IN_FREQ_SHIFT 3
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_GAIN_LOOP_GAIN_IN_FREQ_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_VCXO1_PLL_GAIN :: LOOP_GAIN_INTEGRATOR_IN_PHASE [02:00] */
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_MASK 0x00000007
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_SHIFT 0
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_DEFAULT 0x00000004
-
-/***************************************************************************
- *PLL_VCXO1_PLL_HOLD_CH_ALL - Hold PLL all channels
- ***************************************************************************/
-/* CLKGEN :: PLL_VCXO1_PLL_HOLD_CH_ALL :: reserved0 [31:01] */
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_HOLD_CH_ALL_reserved0_MASK 0xfffffffe
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_HOLD_CH_ALL_reserved0_SHIFT 1
-
-/* CLKGEN :: PLL_VCXO1_PLL_HOLD_CH_ALL :: HOLD_CH_ALL [00:00] */
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_HOLD_CH_ALL_HOLD_CH_ALL_MASK 0x00000001
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_HOLD_CH_ALL_HOLD_CH_ALL_SHIFT 0
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_HOLD_CH_ALL_HOLD_CH_ALL_DEFAULT 0x00000000
-
-/***************************************************************************
- *PLL_VCXO1_PLL_LDO_CTRL - Ldo voltage control
- ***************************************************************************/
-/* CLKGEN :: PLL_VCXO1_PLL_LDO_CTRL :: reserved0 [31:16] */
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_LDO_CTRL_reserved0_MASK 0xffff0000
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_LDO_CTRL_reserved0_SHIFT 16
-
-/* CLKGEN :: PLL_VCXO1_PLL_LDO_CTRL :: LDO_CTRL [15:00] */
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_LDO_CTRL_LDO_CTRL_MASK 0x0000ffff
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_LDO_CTRL_LDO_CTRL_SHIFT 0
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_LDO_CTRL_LDO_CTRL_DEFAULT 0x00005005
-
-/***************************************************************************
- *PLL_VCXO1_PLL_LDO_PWRON - LDO Power on
- ***************************************************************************/
-/* CLKGEN :: PLL_VCXO1_PLL_LDO_PWRON :: reserved0 [31:01] */
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_LDO_PWRON_reserved0_MASK 0xfffffffe
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_LDO_PWRON_reserved0_SHIFT 1
-
-/* CLKGEN :: PLL_VCXO1_PLL_LDO_PWRON :: LDO_PWRON_PLL [00:00] */
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_LDO_PWRON_LDO_PWRON_PLL_MASK 0x00000001
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_LDO_PWRON_LDO_PWRON_PLL_SHIFT 0
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_LDO_PWRON_LDO_PWRON_PLL_DEFAULT 0x00000001
-
-/***************************************************************************
- *PLL_VCXO1_PLL_LOCK_STATUS - Lock Status
- ***************************************************************************/
-/* CLKGEN :: PLL_VCXO1_PLL_LOCK_STATUS :: reserved0 [31:02] */
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_LOCK_STATUS_reserved0_MASK 0xfffffffc
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_LOCK_STATUS_reserved0_SHIFT 2
-
-/* CLKGEN :: PLL_VCXO1_PLL_LOCK_STATUS :: LOCK_LOST [01:01] */
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_LOCK_STATUS_LOCK_LOST_MASK 0x00000002
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_LOCK_STATUS_LOCK_LOST_SHIFT 1
-
-/* CLKGEN :: PLL_VCXO1_PLL_LOCK_STATUS :: LOCK [00:00] */
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_LOCK_STATUS_LOCK_MASK 0x00000001
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_LOCK_STATUS_LOCK_SHIFT 0
-
-/***************************************************************************
- *PLL_VCXO1_PLL_MISC - Mscellaneous control bus.
- ***************************************************************************/
-/* CLKGEN :: PLL_VCXO1_PLL_MISC :: VCO_RANGE_LOW [31:31] */
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_MISC_VCO_RANGE_LOW_MASK 0x80000000
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_MISC_VCO_RANGE_LOW_SHIFT 31
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_MISC_VCO_RANGE_LOW_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_VCXO1_PLL_MISC :: VCO_RANGE_HIGH [30:30] */
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_MISC_VCO_RANGE_HIGH_MASK 0x40000000
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_MISC_VCO_RANGE_HIGH_SHIFT 30
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_MISC_VCO_RANGE_HIGH_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_VCXO1_PLL_MISC :: VCO_DIV2 [29:29] */
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_MISC_VCO_DIV2_MASK 0x20000000
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_MISC_VCO_DIV2_SHIFT 29
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_MISC_VCO_DIV2_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_VCXO1_PLL_MISC :: STAT_UPDATE [28:28] */
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_MISC_STAT_UPDATE_MASK 0x10000000
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_MISC_STAT_UPDATE_SHIFT 28
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_MISC_STAT_UPDATE_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_VCXO1_PLL_MISC :: STAT_SELECT [27:25] */
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_MISC_STAT_SELECT_MASK 0x0e000000
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_MISC_STAT_SELECT_SHIFT 25
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_MISC_STAT_SELECT_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_VCXO1_PLL_MISC :: STAT_RESET [24:24] */
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_MISC_STAT_RESET_MASK 0x01000000
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_MISC_STAT_RESET_SHIFT 24
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_MISC_STAT_RESET_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_VCXO1_PLL_MISC :: STAT_MODE [23:22] */
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_MISC_STAT_MODE_MASK 0x00c00000
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_MISC_STAT_MODE_SHIFT 22
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_MISC_STAT_MODE_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_VCXO1_PLL_MISC :: REF_ALT_OFFS [21:21] */
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_MISC_REF_ALT_OFFS_MASK 0x00200000
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_MISC_REF_ALT_OFFS_SHIFT 21
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_MISC_REF_ALT_OFFS_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_VCXO1_PLL_MISC :: PWM_RATE [20:19] */
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_MISC_PWM_RATE_MASK 0x00180000
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_MISC_PWM_RATE_SHIFT 19
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_MISC_PWM_RATE_DEFAULT 0x00000003
-
-/* CLKGEN :: PLL_VCXO1_PLL_MISC :: POST_CTRL_RESETB [18:17] */
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_MISC_POST_CTRL_RESETB_MASK 0x00060000
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_MISC_POST_CTRL_RESETB_SHIFT 17
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_MISC_POST_CTRL_RESETB_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_VCXO1_PLL_MISC :: NDIV_RELOCK [16:16] */
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_MISC_NDIV_RELOCK_MASK 0x00010000
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_MISC_NDIV_RELOCK_SHIFT 16
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_MISC_NDIV_RELOCK_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_VCXO1_PLL_MISC :: FAST_LOCK [15:15] */
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_MISC_FAST_LOCK_MASK 0x00008000
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_MISC_FAST_LOCK_SHIFT 15
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_MISC_FAST_LOCK_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_VCXO1_PLL_MISC :: DITHER_DISABLE [14:14] */
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_MISC_DITHER_DISABLE_MASK 0x00004000
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_MISC_DITHER_DISABLE_SHIFT 14
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_MISC_DITHER_DISABLE_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_VCXO1_PLL_MISC :: DCO_CTRL_BYPASS_ENABLE [13:13] */
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_MASK 0x00002000
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_SHIFT 13
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_VCXO1_PLL_MISC :: DCO_CTRL_BYPASS [12:01] */
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_MISC_DCO_CTRL_BYPASS_MASK 0x00001ffe
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_MISC_DCO_CTRL_BYPASS_SHIFT 1
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_MISC_DCO_CTRL_BYPASS_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_VCXO1_PLL_MISC :: AUX_CTRL [00:00] */
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_MISC_AUX_CTRL_MASK 0x00000001
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_MISC_AUX_CTRL_SHIFT 0
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_MISC_AUX_CTRL_DEFAULT 0x00000000
-
-/***************************************************************************
- *PLL_VCXO1_PLL_MISC2 - Mscellaneous control bus continued.
- ***************************************************************************/
-/* CLKGEN :: PLL_VCXO1_PLL_MISC2 :: PLLRESERVED0 [31:01] */
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_MISC2_PLLRESERVED0_MASK 0xfffffffe
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_MISC2_PLLRESERVED0_SHIFT 1
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_MISC2_PLLRESERVED0_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_VCXO1_PLL_MISC2 :: DIG_INPUT_SEL [00:00] */
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_MISC2_DIG_INPUT_SEL_MASK 0x00000001
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_MISC2_DIG_INPUT_SEL_SHIFT 0
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_MISC2_DIG_INPUT_SEL_DEFAULT 0x00000000
-
-/***************************************************************************
- *PLL_VCXO1_PLL_PWRON - Poweron
- ***************************************************************************/
-/* CLKGEN :: PLL_VCXO1_PLL_PWRON :: reserved0 [31:01] */
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_PWRON_reserved0_MASK 0xfffffffe
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_PWRON_reserved0_SHIFT 1
-
-/* CLKGEN :: PLL_VCXO1_PLL_PWRON :: PWRON_PLL [00:00] */
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_PWRON_PWRON_PLL_MASK 0x00000001
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_PWRON_PWRON_PLL_SHIFT 0
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_PWRON_PWRON_PLL_DEFAULT 0x00000001
-
-/***************************************************************************
- *PLL_VCXO1_PLL_RESET - Resets
- ***************************************************************************/
-/* CLKGEN :: PLL_VCXO1_PLL_RESET :: reserved0 [31:02] */
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_RESET_reserved0_MASK 0xfffffffc
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_RESET_reserved0_SHIFT 2
-
-/* CLKGEN :: PLL_VCXO1_PLL_RESET :: RESETD [01:01] */
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_RESET_RESETD_MASK 0x00000002
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_RESET_RESETD_SHIFT 1
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_RESET_RESETD_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_VCXO1_PLL_RESET :: RESETA [00:00] */
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_RESET_RESETA_MASK 0x00000001
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_RESET_RESETA_SHIFT 0
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_RESET_RESETA_DEFAULT 0x00000000
-
-/***************************************************************************
- *PLL_VCXO1_PLL_SSC_MODE_CONTROL_HIGH - Higher bits of Spread Spectrum mode control
- ***************************************************************************/
-/* CLKGEN :: PLL_VCXO1_PLL_SSC_MODE_CONTROL_HIGH :: reserved0 [31:16] */
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_SSC_MODE_CONTROL_HIGH_reserved0_MASK 0xffff0000
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_SSC_MODE_CONTROL_HIGH_reserved0_SHIFT 16
-
-/* CLKGEN :: PLL_VCXO1_PLL_SSC_MODE_CONTROL_HIGH :: SSC_STEP [15:00] */
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_MASK 0x0000ffff
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_SHIFT 0
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *PLL_VCXO1_PLL_SSC_MODE_CONTROL_LOW - Lower bits of Spread Spectrum mode control
- ***************************************************************************/
-/* CLKGEN :: PLL_VCXO1_PLL_SSC_MODE_CONTROL_LOW :: reserved0 [31:23] */
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_SSC_MODE_CONTROL_LOW_reserved0_MASK 0xff800000
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_SSC_MODE_CONTROL_LOW_reserved0_SHIFT 23
-
-/* CLKGEN :: PLL_VCXO1_PLL_SSC_MODE_CONTROL_LOW :: SSC_MODE [22:22] */
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_MASK 0x00400000
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_SHIFT 22
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_VCXO1_PLL_SSC_MODE_CONTROL_LOW :: SSC_LIMIT [21:00] */
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_MASK 0x003fffff
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_SHIFT 0
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_DEFAULT 0x00000000
-
-/***************************************************************************
- *PLL_VCXO1_PLL_STATUS - Status
- ***************************************************************************/
-/* CLKGEN :: PLL_VCXO1_PLL_STATUS :: reserved0 [31:12] */
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_STATUS_reserved0_MASK 0xfffff000
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_STATUS_reserved0_SHIFT 12
-
-/* CLKGEN :: PLL_VCXO1_PLL_STATUS :: TEST_STATUS [11:00] */
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_STATUS_TEST_STATUS_MASK 0x00000fff
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_STATUS_TEST_STATUS_SHIFT 0
-
-/***************************************************************************
- *PLL_XPT_PLL_CHANNEL_CTRL_CH_0 - PLL CHANNEL control CH 0
- ***************************************************************************/
-/* CLKGEN :: PLL_XPT_PLL_CHANNEL_CTRL_CH_0 :: reserved0 [31:11] */
-#define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_0_reserved0_MASK 0xfffff800
-#define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_0_reserved0_SHIFT 11
-
-/* CLKGEN :: PLL_XPT_PLL_CHANNEL_CTRL_CH_0 :: POST_DIVIDER_HOLD_CH0 [10:10] */
-#define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_MASK 0x00000400
-#define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_SHIFT 10
-#define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_XPT_PLL_CHANNEL_CTRL_CH_0 :: PHASE_OFFSET_CH0 [09:09] */
-#define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_MASK 0x00000200
-#define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_SHIFT 9
-#define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_XPT_PLL_CHANNEL_CTRL_CH_0 :: MDIV_CH0 [08:01] */
-#define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_MASK 0x000001fe
-#define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_SHIFT 1
-#define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_DEFAULT 0x00000008
-
-/* CLKGEN :: PLL_XPT_PLL_CHANNEL_CTRL_CH_0 :: CLOCK_DIS_CH0 [00:00] */
-#define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_MASK 0x00000001
-#define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_SHIFT 0
-#define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_DEFAULT 0x00000000
-
-/***************************************************************************
- *PLL_XPT_PLL_CHANNEL_CTRL_CH_1 - PLL CHANNEL control CH 1
- ***************************************************************************/
-/* CLKGEN :: PLL_XPT_PLL_CHANNEL_CTRL_CH_1 :: reserved0 [31:11] */
-#define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_1_reserved0_MASK 0xfffff800
-#define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_1_reserved0_SHIFT 11
-
-/* CLKGEN :: PLL_XPT_PLL_CHANNEL_CTRL_CH_1 :: POST_DIVIDER_HOLD_CH1 [10:10] */
-#define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_MASK 0x00000400
-#define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_SHIFT 10
-#define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_XPT_PLL_CHANNEL_CTRL_CH_1 :: PHASE_OFFSET_CH1 [09:09] */
-#define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_MASK 0x00000200
-#define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_SHIFT 9
-#define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_XPT_PLL_CHANNEL_CTRL_CH_1 :: MDIV_CH1 [08:01] */
-#define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_MASK 0x000001fe
-#define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_SHIFT 1
-#define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_DEFAULT 0x00000008
-
-/* CLKGEN :: PLL_XPT_PLL_CHANNEL_CTRL_CH_1 :: CLOCK_DIS_CH1 [00:00] */
-#define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_MASK 0x00000001
-#define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_SHIFT 0
-#define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_DEFAULT 0x00000000
-
-/***************************************************************************
- *PLL_XPT_PLL_CHANNEL_CTRL_CH_2 - PLL CHANNEL control CH 2
- ***************************************************************************/
-/* CLKGEN :: PLL_XPT_PLL_CHANNEL_CTRL_CH_2 :: reserved0 [31:11] */
-#define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_2_reserved0_MASK 0xfffff800
-#define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_2_reserved0_SHIFT 11
-
-/* CLKGEN :: PLL_XPT_PLL_CHANNEL_CTRL_CH_2 :: POST_DIVIDER_HOLD_CH2 [10:10] */
-#define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_HOLD_CH2_MASK 0x00000400
-#define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_HOLD_CH2_SHIFT 10
-#define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_HOLD_CH2_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_XPT_PLL_CHANNEL_CTRL_CH_2 :: PHASE_OFFSET_CH2 [09:09] */
-#define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_2_PHASE_OFFSET_CH2_MASK 0x00000200
-#define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_2_PHASE_OFFSET_CH2_SHIFT 9
-#define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_2_PHASE_OFFSET_CH2_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_XPT_PLL_CHANNEL_CTRL_CH_2 :: MDIV_CH2 [08:01] */
-#define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_2_MDIV_CH2_MASK 0x000001fe
-#define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_2_MDIV_CH2_SHIFT 1
-#define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_2_MDIV_CH2_DEFAULT 0x0000000f
-
-/* CLKGEN :: PLL_XPT_PLL_CHANNEL_CTRL_CH_2 :: CLOCK_DIS_CH2 [00:00] */
-#define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_2_CLOCK_DIS_CH2_MASK 0x00000001
-#define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_2_CLOCK_DIS_CH2_SHIFT 0
-#define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_2_CLOCK_DIS_CH2_DEFAULT 0x00000000
-
-/***************************************************************************
- *PLL_XPT_PLL_CHANNEL_CTRL_CH_3 - PLL CHANNEL control CH 3
- ***************************************************************************/
-/* CLKGEN :: PLL_XPT_PLL_CHANNEL_CTRL_CH_3 :: reserved0 [31:11] */
-#define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_3_reserved0_MASK 0xfffff800
-#define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_3_reserved0_SHIFT 11
-
-/* CLKGEN :: PLL_XPT_PLL_CHANNEL_CTRL_CH_3 :: POST_DIVIDER_HOLD_CH3 [10:10] */
-#define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_HOLD_CH3_MASK 0x00000400
-#define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_HOLD_CH3_SHIFT 10
-#define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_HOLD_CH3_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_XPT_PLL_CHANNEL_CTRL_CH_3 :: PHASE_OFFSET_CH3 [09:09] */
-#define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_3_PHASE_OFFSET_CH3_MASK 0x00000200
-#define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_3_PHASE_OFFSET_CH3_SHIFT 9
-#define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_3_PHASE_OFFSET_CH3_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_XPT_PLL_CHANNEL_CTRL_CH_3 :: MDIV_CH3 [08:01] */
-#define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_3_MDIV_CH3_MASK 0x000001fe
-#define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_3_MDIV_CH3_SHIFT 1
-#define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_3_MDIV_CH3_DEFAULT 0x0000000c
-
-/* CLKGEN :: PLL_XPT_PLL_CHANNEL_CTRL_CH_3 :: CLOCK_DIS_CH3 [00:00] */
-#define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_3_CLOCK_DIS_CH3_MASK 0x00000001
-#define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_3_CLOCK_DIS_CH3_SHIFT 0
-#define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_3_CLOCK_DIS_CH3_DEFAULT 0x00000000
-
-/***************************************************************************
- *PLL_XPT_PLL_CHANNEL_CTRL_CH_4 - PLL CHANNEL control CH 4
- ***************************************************************************/
-/* CLKGEN :: PLL_XPT_PLL_CHANNEL_CTRL_CH_4 :: reserved0 [31:11] */
-#define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_4_reserved0_MASK 0xfffff800
-#define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_4_reserved0_SHIFT 11
-
-/* CLKGEN :: PLL_XPT_PLL_CHANNEL_CTRL_CH_4 :: POST_DIVIDER_HOLD_CH4 [10:10] */
-#define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_4_POST_DIVIDER_HOLD_CH4_MASK 0x00000400
-#define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_4_POST_DIVIDER_HOLD_CH4_SHIFT 10
-#define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_4_POST_DIVIDER_HOLD_CH4_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_XPT_PLL_CHANNEL_CTRL_CH_4 :: PHASE_OFFSET_CH4 [09:09] */
-#define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_4_PHASE_OFFSET_CH4_MASK 0x00000200
-#define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_4_PHASE_OFFSET_CH4_SHIFT 9
-#define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_4_PHASE_OFFSET_CH4_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_XPT_PLL_CHANNEL_CTRL_CH_4 :: MDIV_CH4 [08:01] */
-#define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_4_MDIV_CH4_MASK 0x000001fe
-#define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_4_MDIV_CH4_SHIFT 1
-#define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_4_MDIV_CH4_DEFAULT 0x00000028
-
-/* CLKGEN :: PLL_XPT_PLL_CHANNEL_CTRL_CH_4 :: CLOCK_DIS_CH4 [00:00] */
-#define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_4_CLOCK_DIS_CH4_MASK 0x00000001
-#define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_4_CLOCK_DIS_CH4_SHIFT 0
-#define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_4_CLOCK_DIS_CH4_DEFAULT 0x00000000
-
-/***************************************************************************
- *PLL_XPT_PLL_CHANNEL_CTRL_CH_5 - PLL CHANNEL control CH 5
- ***************************************************************************/
-/* CLKGEN :: PLL_XPT_PLL_CHANNEL_CTRL_CH_5 :: reserved0 [31:11] */
-#define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_5_reserved0_MASK 0xfffff800
-#define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_5_reserved0_SHIFT 11
-
-/* CLKGEN :: PLL_XPT_PLL_CHANNEL_CTRL_CH_5 :: POST_DIVIDER_HOLD_CH5 [10:10] */
-#define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_5_POST_DIVIDER_HOLD_CH5_MASK 0x00000400
-#define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_5_POST_DIVIDER_HOLD_CH5_SHIFT 10
-#define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_5_POST_DIVIDER_HOLD_CH5_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_XPT_PLL_CHANNEL_CTRL_CH_5 :: PHASE_OFFSET_CH5 [09:09] */
-#define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_5_PHASE_OFFSET_CH5_MASK 0x00000200
-#define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_5_PHASE_OFFSET_CH5_SHIFT 9
-#define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_5_PHASE_OFFSET_CH5_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_XPT_PLL_CHANNEL_CTRL_CH_5 :: MDIV_CH5 [08:01] */
-#define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_5_MDIV_CH5_MASK 0x000001fe
-#define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_5_MDIV_CH5_SHIFT 1
-#define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_5_MDIV_CH5_DEFAULT 0x00000028
-
-/* CLKGEN :: PLL_XPT_PLL_CHANNEL_CTRL_CH_5 :: CLOCK_DIS_CH5 [00:00] */
-#define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_5_CLOCK_DIS_CH5_MASK 0x00000001
-#define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_5_CLOCK_DIS_CH5_SHIFT 0
-#define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_5_CLOCK_DIS_CH5_DEFAULT 0x00000000
-
-/***************************************************************************
- *PLL_XPT_PLL_DIV - Pre multiplier
- ***************************************************************************/
-/* CLKGEN :: PLL_XPT_PLL_DIV :: reserved0 [31:14] */
-#define BCHP_CLKGEN_PLL_XPT_PLL_DIV_reserved0_MASK 0xffffc000
-#define BCHP_CLKGEN_PLL_XPT_PLL_DIV_reserved0_SHIFT 14
-
-/* CLKGEN :: PLL_XPT_PLL_DIV :: PDIV [13:10] */
-#define BCHP_CLKGEN_PLL_XPT_PLL_DIV_PDIV_MASK 0x00003c00
-#define BCHP_CLKGEN_PLL_XPT_PLL_DIV_PDIV_SHIFT 10
-#define BCHP_CLKGEN_PLL_XPT_PLL_DIV_PDIV_DEFAULT 0x00000002
-
-/* CLKGEN :: PLL_XPT_PLL_DIV :: NDIV_INT [09:00] */
-#define BCHP_CLKGEN_PLL_XPT_PLL_DIV_NDIV_INT_MASK 0x000003ff
-#define BCHP_CLKGEN_PLL_XPT_PLL_DIV_NDIV_INT_SHIFT 0
-#define BCHP_CLKGEN_PLL_XPT_PLL_DIV_NDIV_INT_DEFAULT 0x00000078
-
-/***************************************************************************
- *PLL_XPT_PLL_GAIN - PLL GAIN
- ***************************************************************************/
-/* CLKGEN :: PLL_XPT_PLL_GAIN :: reserved0 [31:10] */
-#define BCHP_CLKGEN_PLL_XPT_PLL_GAIN_reserved0_MASK 0xfffffc00
-#define BCHP_CLKGEN_PLL_XPT_PLL_GAIN_reserved0_SHIFT 10
-
-/* CLKGEN :: PLL_XPT_PLL_GAIN :: LOOP_GAIN_PROPORTIONAL_IN_PHASE [09:06] */
-#define BCHP_CLKGEN_PLL_XPT_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_MASK 0x000003c0
-#define BCHP_CLKGEN_PLL_XPT_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_SHIFT 6
-#define BCHP_CLKGEN_PLL_XPT_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_DEFAULT 0x00000003
-
-/* CLKGEN :: PLL_XPT_PLL_GAIN :: LOOP_GAIN_IN_FREQ [05:03] */
-#define BCHP_CLKGEN_PLL_XPT_PLL_GAIN_LOOP_GAIN_IN_FREQ_MASK 0x00000038
-#define BCHP_CLKGEN_PLL_XPT_PLL_GAIN_LOOP_GAIN_IN_FREQ_SHIFT 3
-#define BCHP_CLKGEN_PLL_XPT_PLL_GAIN_LOOP_GAIN_IN_FREQ_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_XPT_PLL_GAIN :: LOOP_GAIN_INTEGRATOR_IN_PHASE [02:00] */
-#define BCHP_CLKGEN_PLL_XPT_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_MASK 0x00000007
-#define BCHP_CLKGEN_PLL_XPT_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_SHIFT 0
-#define BCHP_CLKGEN_PLL_XPT_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_DEFAULT 0x00000002
-
-/***************************************************************************
- *PLL_XPT_PLL_LDO_PWRON - LDO Power on
- ***************************************************************************/
-/* CLKGEN :: PLL_XPT_PLL_LDO_PWRON :: reserved0 [31:01] */
-#define BCHP_CLKGEN_PLL_XPT_PLL_LDO_PWRON_reserved0_MASK 0xfffffffe
-#define BCHP_CLKGEN_PLL_XPT_PLL_LDO_PWRON_reserved0_SHIFT 1
-
-/* CLKGEN :: PLL_XPT_PLL_LDO_PWRON :: LDO_PWRON_PLL [00:00] */
-#define BCHP_CLKGEN_PLL_XPT_PLL_LDO_PWRON_LDO_PWRON_PLL_MASK 0x00000001
-#define BCHP_CLKGEN_PLL_XPT_PLL_LDO_PWRON_LDO_PWRON_PLL_SHIFT 0
-#define BCHP_CLKGEN_PLL_XPT_PLL_LDO_PWRON_LDO_PWRON_PLL_DEFAULT 0x00000001
-
-/***************************************************************************
- *PLL_XPT_PLL_LOCK_STATUS - Lock Status
- ***************************************************************************/
-/* CLKGEN :: PLL_XPT_PLL_LOCK_STATUS :: reserved0 [31:02] */
-#define BCHP_CLKGEN_PLL_XPT_PLL_LOCK_STATUS_reserved0_MASK 0xfffffffc
-#define BCHP_CLKGEN_PLL_XPT_PLL_LOCK_STATUS_reserved0_SHIFT 2
-
-/* CLKGEN :: PLL_XPT_PLL_LOCK_STATUS :: LOCK_LOST [01:01] */
-#define BCHP_CLKGEN_PLL_XPT_PLL_LOCK_STATUS_LOCK_LOST_MASK 0x00000002
-#define BCHP_CLKGEN_PLL_XPT_PLL_LOCK_STATUS_LOCK_LOST_SHIFT 1
-
-/* CLKGEN :: PLL_XPT_PLL_LOCK_STATUS :: LOCK [00:00] */
-#define BCHP_CLKGEN_PLL_XPT_PLL_LOCK_STATUS_LOCK_MASK 0x00000001
-#define BCHP_CLKGEN_PLL_XPT_PLL_LOCK_STATUS_LOCK_SHIFT 0
-
-/***************************************************************************
- *PLL_XPT_PLL_MISC - Mscellaneous control bus.
- ***************************************************************************/
-/* CLKGEN :: PLL_XPT_PLL_MISC :: VCO_RANGE [31:30] */
-#define BCHP_CLKGEN_PLL_XPT_PLL_MISC_VCO_RANGE_MASK 0xc0000000
-#define BCHP_CLKGEN_PLL_XPT_PLL_MISC_VCO_RANGE_SHIFT 30
-#define BCHP_CLKGEN_PLL_XPT_PLL_MISC_VCO_RANGE_DEFAULT 0x00000002
-
-/* CLKGEN :: PLL_XPT_PLL_MISC :: VCO_FB_DIV2 [29:29] */
-#define BCHP_CLKGEN_PLL_XPT_PLL_MISC_VCO_FB_DIV2_MASK 0x20000000
-#define BCHP_CLKGEN_PLL_XPT_PLL_MISC_VCO_FB_DIV2_SHIFT 29
-#define BCHP_CLKGEN_PLL_XPT_PLL_MISC_VCO_FB_DIV2_DEFAULT 0x00000001
-
-/* CLKGEN :: PLL_XPT_PLL_MISC :: STAT_UPDATE [28:28] */
-#define BCHP_CLKGEN_PLL_XPT_PLL_MISC_STAT_UPDATE_MASK 0x10000000
-#define BCHP_CLKGEN_PLL_XPT_PLL_MISC_STAT_UPDATE_SHIFT 28
-#define BCHP_CLKGEN_PLL_XPT_PLL_MISC_STAT_UPDATE_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_XPT_PLL_MISC :: STAT_SELECT [27:25] */
-#define BCHP_CLKGEN_PLL_XPT_PLL_MISC_STAT_SELECT_MASK 0x0e000000
-#define BCHP_CLKGEN_PLL_XPT_PLL_MISC_STAT_SELECT_SHIFT 25
-#define BCHP_CLKGEN_PLL_XPT_PLL_MISC_STAT_SELECT_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_XPT_PLL_MISC :: STAT_RESET [24:24] */
-#define BCHP_CLKGEN_PLL_XPT_PLL_MISC_STAT_RESET_MASK 0x01000000
-#define BCHP_CLKGEN_PLL_XPT_PLL_MISC_STAT_RESET_SHIFT 24
-#define BCHP_CLKGEN_PLL_XPT_PLL_MISC_STAT_RESET_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_XPT_PLL_MISC :: STAT_MODE [23:22] */
-#define BCHP_CLKGEN_PLL_XPT_PLL_MISC_STAT_MODE_MASK 0x00c00000
-#define BCHP_CLKGEN_PLL_XPT_PLL_MISC_STAT_MODE_SHIFT 22
-#define BCHP_CLKGEN_PLL_XPT_PLL_MISC_STAT_MODE_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_XPT_PLL_MISC :: PWM_RATE [21:20] */
-#define BCHP_CLKGEN_PLL_XPT_PLL_MISC_PWM_RATE_MASK 0x00300000
-#define BCHP_CLKGEN_PLL_XPT_PLL_MISC_PWM_RATE_SHIFT 20
-#define BCHP_CLKGEN_PLL_XPT_PLL_MISC_PWM_RATE_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_XPT_PLL_MISC :: POST_CTRL_RESETB [19:18] */
-#define BCHP_CLKGEN_PLL_XPT_PLL_MISC_POST_CTRL_RESETB_MASK 0x000c0000
-#define BCHP_CLKGEN_PLL_XPT_PLL_MISC_POST_CTRL_RESETB_SHIFT 18
-#define BCHP_CLKGEN_PLL_XPT_PLL_MISC_POST_CTRL_RESETB_DEFAULT 0x00000003
-
-/* CLKGEN :: PLL_XPT_PLL_MISC :: PLLRESERVED2 [17:16] */
-#define BCHP_CLKGEN_PLL_XPT_PLL_MISC_PLLRESERVED2_MASK 0x00030000
-#define BCHP_CLKGEN_PLL_XPT_PLL_MISC_PLLRESERVED2_SHIFT 16
-#define BCHP_CLKGEN_PLL_XPT_PLL_MISC_PLLRESERVED2_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_XPT_PLL_MISC :: PLLRESERVED1 [15:15] */
-#define BCHP_CLKGEN_PLL_XPT_PLL_MISC_PLLRESERVED1_MASK 0x00008000
-#define BCHP_CLKGEN_PLL_XPT_PLL_MISC_PLLRESERVED1_SHIFT 15
-#define BCHP_CLKGEN_PLL_XPT_PLL_MISC_PLLRESERVED1_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_XPT_PLL_MISC :: NDIV_RELOCK [14:14] */
-#define BCHP_CLKGEN_PLL_XPT_PLL_MISC_NDIV_RELOCK_MASK 0x00004000
-#define BCHP_CLKGEN_PLL_XPT_PLL_MISC_NDIV_RELOCK_SHIFT 14
-#define BCHP_CLKGEN_PLL_XPT_PLL_MISC_NDIV_RELOCK_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_XPT_PLL_MISC :: FAST_LOCK [13:13] */
-#define BCHP_CLKGEN_PLL_XPT_PLL_MISC_FAST_LOCK_MASK 0x00002000
-#define BCHP_CLKGEN_PLL_XPT_PLL_MISC_FAST_LOCK_SHIFT 13
-#define BCHP_CLKGEN_PLL_XPT_PLL_MISC_FAST_LOCK_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_XPT_PLL_MISC :: DCO_CTRL_BYPASS_ENABLE [12:12] */
-#define BCHP_CLKGEN_PLL_XPT_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_MASK 0x00001000
-#define BCHP_CLKGEN_PLL_XPT_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_SHIFT 12
-#define BCHP_CLKGEN_PLL_XPT_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_XPT_PLL_MISC :: DCO_CTRL_BYPASS [11:00] */
-#define BCHP_CLKGEN_PLL_XPT_PLL_MISC_DCO_CTRL_BYPASS_MASK 0x00000fff
-#define BCHP_CLKGEN_PLL_XPT_PLL_MISC_DCO_CTRL_BYPASS_SHIFT 0
-#define BCHP_CLKGEN_PLL_XPT_PLL_MISC_DCO_CTRL_BYPASS_DEFAULT 0x00000000
-
-/***************************************************************************
- *PLL_XPT_PLL_MISC2 - Mscellaneous control bus continued.
- ***************************************************************************/
-/* CLKGEN :: PLL_XPT_PLL_MISC2 :: PLLRESERVED0 [31:02] */
-#define BCHP_CLKGEN_PLL_XPT_PLL_MISC2_PLLRESERVED0_MASK 0xfffffffc
-#define BCHP_CLKGEN_PLL_XPT_PLL_MISC2_PLLRESERVED0_SHIFT 2
-#define BCHP_CLKGEN_PLL_XPT_PLL_MISC2_PLLRESERVED0_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_XPT_PLL_MISC2 :: LDO [01:00] */
-#define BCHP_CLKGEN_PLL_XPT_PLL_MISC2_LDO_MASK 0x00000003
-#define BCHP_CLKGEN_PLL_XPT_PLL_MISC2_LDO_SHIFT 0
-#define BCHP_CLKGEN_PLL_XPT_PLL_MISC2_LDO_DEFAULT 0x00000001
-
-/***************************************************************************
- *PLL_XPT_PLL_PWRON - Poweron
- ***************************************************************************/
-/* CLKGEN :: PLL_XPT_PLL_PWRON :: reserved0 [31:01] */
-#define BCHP_CLKGEN_PLL_XPT_PLL_PWRON_reserved0_MASK 0xfffffffe
-#define BCHP_CLKGEN_PLL_XPT_PLL_PWRON_reserved0_SHIFT 1
-
-/* CLKGEN :: PLL_XPT_PLL_PWRON :: PWRON_PLL [00:00] */
-#define BCHP_CLKGEN_PLL_XPT_PLL_PWRON_PWRON_PLL_MASK 0x00000001
-#define BCHP_CLKGEN_PLL_XPT_PLL_PWRON_PWRON_PLL_SHIFT 0
-#define BCHP_CLKGEN_PLL_XPT_PLL_PWRON_PWRON_PLL_DEFAULT 0x00000001
-
-/***************************************************************************
- *PLL_XPT_PLL_RESET - Resets
- ***************************************************************************/
-/* CLKGEN :: PLL_XPT_PLL_RESET :: reserved0 [31:01] */
-#define BCHP_CLKGEN_PLL_XPT_PLL_RESET_reserved0_MASK 0xfffffffe
-#define BCHP_CLKGEN_PLL_XPT_PLL_RESET_reserved0_SHIFT 1
-
-/* CLKGEN :: PLL_XPT_PLL_RESET :: RESETD [00:00] */
-#define BCHP_CLKGEN_PLL_XPT_PLL_RESET_RESETD_MASK 0x00000001
-#define BCHP_CLKGEN_PLL_XPT_PLL_RESET_RESETD_SHIFT 0
-#define BCHP_CLKGEN_PLL_XPT_PLL_RESET_RESETD_DEFAULT 0x00000000
-
-/***************************************************************************
- *PLL_XPT_PLL_SSC_MODE_CONTROL_HIGH - Higher bits of Spread Spectrum mode control
- ***************************************************************************/
-/* CLKGEN :: PLL_XPT_PLL_SSC_MODE_CONTROL_HIGH :: reserved0 [31:16] */
-#define BCHP_CLKGEN_PLL_XPT_PLL_SSC_MODE_CONTROL_HIGH_reserved0_MASK 0xffff0000
-#define BCHP_CLKGEN_PLL_XPT_PLL_SSC_MODE_CONTROL_HIGH_reserved0_SHIFT 16
-
-/* CLKGEN :: PLL_XPT_PLL_SSC_MODE_CONTROL_HIGH :: SSC_STEP [15:00] */
-#define BCHP_CLKGEN_PLL_XPT_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_MASK 0x0000ffff
-#define BCHP_CLKGEN_PLL_XPT_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_SHIFT 0
-#define BCHP_CLKGEN_PLL_XPT_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *PLL_XPT_PLL_SSC_MODE_CONTROL_LOW - Lower bits of Spread Spectrum mode control
- ***************************************************************************/
-/* CLKGEN :: PLL_XPT_PLL_SSC_MODE_CONTROL_LOW :: reserved0 [31:23] */
-#define BCHP_CLKGEN_PLL_XPT_PLL_SSC_MODE_CONTROL_LOW_reserved0_MASK 0xff800000
-#define BCHP_CLKGEN_PLL_XPT_PLL_SSC_MODE_CONTROL_LOW_reserved0_SHIFT 23
-
-/* CLKGEN :: PLL_XPT_PLL_SSC_MODE_CONTROL_LOW :: SSC_MODE [22:22] */
-#define BCHP_CLKGEN_PLL_XPT_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_MASK 0x00400000
-#define BCHP_CLKGEN_PLL_XPT_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_SHIFT 22
-#define BCHP_CLKGEN_PLL_XPT_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_XPT_PLL_SSC_MODE_CONTROL_LOW :: SSC_LIMIT [21:00] */
-#define BCHP_CLKGEN_PLL_XPT_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_MASK 0x003fffff
-#define BCHP_CLKGEN_PLL_XPT_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_SHIFT 0
-#define BCHP_CLKGEN_PLL_XPT_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_DEFAULT 0x00000000
-
-/***************************************************************************
- *PLL_XPT_PLL_STATUS - Status
- ***************************************************************************/
-/* CLKGEN :: PLL_XPT_PLL_STATUS :: reserved0 [31:12] */
-#define BCHP_CLKGEN_PLL_XPT_PLL_STATUS_reserved0_MASK 0xfffff000
-#define BCHP_CLKGEN_PLL_XPT_PLL_STATUS_reserved0_SHIFT 12
-
-/* CLKGEN :: PLL_XPT_PLL_STATUS :: TEST_STATUS [11:00] */
-#define BCHP_CLKGEN_PLL_XPT_PLL_STATUS_TEST_STATUS_MASK 0x00000fff
-#define BCHP_CLKGEN_PLL_XPT_PLL_STATUS_TEST_STATUS_SHIFT 0
-
-/***************************************************************************
- *AIF_MDAC_CAL_TOP_INST_CLOCK_ENABLE - Aif mdac cal top inst clock enable
- ***************************************************************************/
-/* CLKGEN :: AIF_MDAC_CAL_TOP_INST_CLOCK_ENABLE :: reserved0 [31:02] */
-#define BCHP_CLKGEN_AIF_MDAC_CAL_TOP_INST_CLOCK_ENABLE_reserved0_MASK 0xfffffffc
-#define BCHP_CLKGEN_AIF_MDAC_CAL_TOP_INST_CLOCK_ENABLE_reserved0_SHIFT 2
-
-/* CLKGEN :: AIF_MDAC_CAL_TOP_INST_CLOCK_ENABLE :: MDAC_54_CLOCK_ENABLE [01:01] */
-#define BCHP_CLKGEN_AIF_MDAC_CAL_TOP_INST_CLOCK_ENABLE_MDAC_54_CLOCK_ENABLE_MASK 0x00000002
-#define BCHP_CLKGEN_AIF_MDAC_CAL_TOP_INST_CLOCK_ENABLE_MDAC_54_CLOCK_ENABLE_SHIFT 1
-#define BCHP_CLKGEN_AIF_MDAC_CAL_TOP_INST_CLOCK_ENABLE_MDAC_54_CLOCK_ENABLE_DEFAULT 0x00000001
-
-/* CLKGEN :: AIF_MDAC_CAL_TOP_INST_CLOCK_ENABLE :: MDAC_108_CLOCK_ENABLE [00:00] */
-#define BCHP_CLKGEN_AIF_MDAC_CAL_TOP_INST_CLOCK_ENABLE_MDAC_108_CLOCK_ENABLE_MASK 0x00000001
-#define BCHP_CLKGEN_AIF_MDAC_CAL_TOP_INST_CLOCK_ENABLE_MDAC_108_CLOCK_ENABLE_SHIFT 0
-#define BCHP_CLKGEN_AIF_MDAC_CAL_TOP_INST_CLOCK_ENABLE_MDAC_108_CLOCK_ENABLE_DEFAULT 0x00000001
-
-/***************************************************************************
- *AIF_MDAC_CAL_TOP_INST_CLOCK_ENABLE_STATUS - Clock Enable Status
- ***************************************************************************/
-/* CLKGEN :: AIF_MDAC_CAL_TOP_INST_CLOCK_ENABLE_STATUS :: reserved0 [31:02] */
-#define BCHP_CLKGEN_AIF_MDAC_CAL_TOP_INST_CLOCK_ENABLE_STATUS_reserved0_MASK 0xfffffffc
-#define BCHP_CLKGEN_AIF_MDAC_CAL_TOP_INST_CLOCK_ENABLE_STATUS_reserved0_SHIFT 2
-
-/* CLKGEN :: AIF_MDAC_CAL_TOP_INST_CLOCK_ENABLE_STATUS :: MDAC_54_CLOCK_ENABLE_STATUS [01:01] */
-#define BCHP_CLKGEN_AIF_MDAC_CAL_TOP_INST_CLOCK_ENABLE_STATUS_MDAC_54_CLOCK_ENABLE_STATUS_MASK 0x00000002
-#define BCHP_CLKGEN_AIF_MDAC_CAL_TOP_INST_CLOCK_ENABLE_STATUS_MDAC_54_CLOCK_ENABLE_STATUS_SHIFT 1
-
-/* CLKGEN :: AIF_MDAC_CAL_TOP_INST_CLOCK_ENABLE_STATUS :: MDAC_108_CLOCK_ENABLE_STATUS [00:00] */
-#define BCHP_CLKGEN_AIF_MDAC_CAL_TOP_INST_CLOCK_ENABLE_STATUS_MDAC_108_CLOCK_ENABLE_STATUS_MASK 0x00000001
-#define BCHP_CLKGEN_AIF_MDAC_CAL_TOP_INST_CLOCK_ENABLE_STATUS_MDAC_108_CLOCK_ENABLE_STATUS_SHIFT 0
-
-/***************************************************************************
- *AIF_MDAC_CAL_TOP_INST_OBSERVE_CLOCK - Aif mdac cal top inst observe clock
- ***************************************************************************/
-/* CLKGEN :: AIF_MDAC_CAL_TOP_INST_OBSERVE_CLOCK :: reserved0 [31:06] */
-#define BCHP_CLKGEN_AIF_MDAC_CAL_TOP_INST_OBSERVE_CLOCK_reserved0_MASK 0xffffffc0
-#define BCHP_CLKGEN_AIF_MDAC_CAL_TOP_INST_OBSERVE_CLOCK_reserved0_SHIFT 6
-
-/* CLKGEN :: AIF_MDAC_CAL_TOP_INST_OBSERVE_CLOCK :: MDAC_ENABLE_OBSERVE_CLOCK [05:05] */
-#define BCHP_CLKGEN_AIF_MDAC_CAL_TOP_INST_OBSERVE_CLOCK_MDAC_ENABLE_OBSERVE_CLOCK_MASK 0x00000020
-#define BCHP_CLKGEN_AIF_MDAC_CAL_TOP_INST_OBSERVE_CLOCK_MDAC_ENABLE_OBSERVE_CLOCK_SHIFT 5
-#define BCHP_CLKGEN_AIF_MDAC_CAL_TOP_INST_OBSERVE_CLOCK_MDAC_ENABLE_OBSERVE_CLOCK_DEFAULT 0x00000000
-
-/* CLKGEN :: AIF_MDAC_CAL_TOP_INST_OBSERVE_CLOCK :: MDAC_ENABLE_DIVIDER_OBSERVE_CLOCK [04:04] */
-#define BCHP_CLKGEN_AIF_MDAC_CAL_TOP_INST_OBSERVE_CLOCK_MDAC_ENABLE_DIVIDER_OBSERVE_CLOCK_MASK 0x00000010
-#define BCHP_CLKGEN_AIF_MDAC_CAL_TOP_INST_OBSERVE_CLOCK_MDAC_ENABLE_DIVIDER_OBSERVE_CLOCK_SHIFT 4
-#define BCHP_CLKGEN_AIF_MDAC_CAL_TOP_INST_OBSERVE_CLOCK_MDAC_ENABLE_DIVIDER_OBSERVE_CLOCK_DEFAULT 0x00000000
-
-/* CLKGEN :: AIF_MDAC_CAL_TOP_INST_OBSERVE_CLOCK :: MDAC_CONTROL_OBSERVE_CLOCK [03:00] */
-#define BCHP_CLKGEN_AIF_MDAC_CAL_TOP_INST_OBSERVE_CLOCK_MDAC_CONTROL_OBSERVE_CLOCK_MASK 0x0000000f
-#define BCHP_CLKGEN_AIF_MDAC_CAL_TOP_INST_OBSERVE_CLOCK_MDAC_CONTROL_OBSERVE_CLOCK_SHIFT 0
-#define BCHP_CLKGEN_AIF_MDAC_CAL_TOP_INST_OBSERVE_CLOCK_MDAC_CONTROL_OBSERVE_CLOCK_DEFAULT 0x00000000
-
-/***************************************************************************
- *AIF_MDAC_CAL_TOP_INST_SEL - Aif mdac cal top inst sel
- ***************************************************************************/
-/* CLKGEN :: AIF_MDAC_CAL_TOP_INST_SEL :: reserved0 [31:01] */
-#define BCHP_CLKGEN_AIF_MDAC_CAL_TOP_INST_SEL_reserved0_MASK 0xfffffffe
-#define BCHP_CLKGEN_AIF_MDAC_CAL_TOP_INST_SEL_reserved0_SHIFT 1
-
-/* CLKGEN :: AIF_MDAC_CAL_TOP_INST_SEL :: MDAC_BYPASS_CLK_ADC_SEL [00:00] */
-#define BCHP_CLKGEN_AIF_MDAC_CAL_TOP_INST_SEL_MDAC_BYPASS_CLK_ADC_SEL_MASK 0x00000001
-#define BCHP_CLKGEN_AIF_MDAC_CAL_TOP_INST_SEL_MDAC_BYPASS_CLK_ADC_SEL_SHIFT 0
-#define BCHP_CLKGEN_AIF_MDAC_CAL_TOP_INST_SEL_MDAC_BYPASS_CLK_ADC_SEL_DEFAULT 0x00000000
-
-/***************************************************************************
- *AIF_WB_SAT_TOP_0_INST_CLOCK_ENABLE - Aif wb sat top 0 inst clock enable
- ***************************************************************************/
-/* CLKGEN :: AIF_WB_SAT_TOP_0_INST_CLOCK_ENABLE :: reserved0 [31:02] */
-#define BCHP_CLKGEN_AIF_WB_SAT_TOP_0_INST_CLOCK_ENABLE_reserved0_MASK 0xfffffffc
-#define BCHP_CLKGEN_AIF_WB_SAT_TOP_0_INST_CLOCK_ENABLE_reserved0_SHIFT 2
-
-/* CLKGEN :: AIF_WB_SAT_TOP_0_INST_CLOCK_ENABLE :: AIF0_54_CLOCK_ENABLE [01:01] */
-#define BCHP_CLKGEN_AIF_WB_SAT_TOP_0_INST_CLOCK_ENABLE_AIF0_54_CLOCK_ENABLE_MASK 0x00000002
-#define BCHP_CLKGEN_AIF_WB_SAT_TOP_0_INST_CLOCK_ENABLE_AIF0_54_CLOCK_ENABLE_SHIFT 1
-#define BCHP_CLKGEN_AIF_WB_SAT_TOP_0_INST_CLOCK_ENABLE_AIF0_54_CLOCK_ENABLE_DEFAULT 0x00000001
-
-/* CLKGEN :: AIF_WB_SAT_TOP_0_INST_CLOCK_ENABLE :: AIF0_108_CLOCK_ENABLE [00:00] */
-#define BCHP_CLKGEN_AIF_WB_SAT_TOP_0_INST_CLOCK_ENABLE_AIF0_108_CLOCK_ENABLE_MASK 0x00000001
-#define BCHP_CLKGEN_AIF_WB_SAT_TOP_0_INST_CLOCK_ENABLE_AIF0_108_CLOCK_ENABLE_SHIFT 0
-#define BCHP_CLKGEN_AIF_WB_SAT_TOP_0_INST_CLOCK_ENABLE_AIF0_108_CLOCK_ENABLE_DEFAULT 0x00000001
-
-/***************************************************************************
- *AIF_WB_SAT_TOP_0_INST_CLOCK_ENABLE_STATUS - Clock Enable Status
- ***************************************************************************/
-/* CLKGEN :: AIF_WB_SAT_TOP_0_INST_CLOCK_ENABLE_STATUS :: reserved0 [31:02] */
-#define BCHP_CLKGEN_AIF_WB_SAT_TOP_0_INST_CLOCK_ENABLE_STATUS_reserved0_MASK 0xfffffffc
-#define BCHP_CLKGEN_AIF_WB_SAT_TOP_0_INST_CLOCK_ENABLE_STATUS_reserved0_SHIFT 2
-
-/* CLKGEN :: AIF_WB_SAT_TOP_0_INST_CLOCK_ENABLE_STATUS :: AIF0_54_CLOCK_ENABLE_STATUS [01:01] */
-#define BCHP_CLKGEN_AIF_WB_SAT_TOP_0_INST_CLOCK_ENABLE_STATUS_AIF0_54_CLOCK_ENABLE_STATUS_MASK 0x00000002
-#define BCHP_CLKGEN_AIF_WB_SAT_TOP_0_INST_CLOCK_ENABLE_STATUS_AIF0_54_CLOCK_ENABLE_STATUS_SHIFT 1
-
-/* CLKGEN :: AIF_WB_SAT_TOP_0_INST_CLOCK_ENABLE_STATUS :: AIF0_108_CLOCK_ENABLE_STATUS [00:00] */
-#define BCHP_CLKGEN_AIF_WB_SAT_TOP_0_INST_CLOCK_ENABLE_STATUS_AIF0_108_CLOCK_ENABLE_STATUS_MASK 0x00000001
-#define BCHP_CLKGEN_AIF_WB_SAT_TOP_0_INST_CLOCK_ENABLE_STATUS_AIF0_108_CLOCK_ENABLE_STATUS_SHIFT 0
-
-/***************************************************************************
- *AIF_WB_SAT_TOP_0_INST_OBSERVE_CLOCK - Aif wb sat top 0 inst observe clock
- ***************************************************************************/
-/* CLKGEN :: AIF_WB_SAT_TOP_0_INST_OBSERVE_CLOCK :: reserved0 [31:06] */
-#define BCHP_CLKGEN_AIF_WB_SAT_TOP_0_INST_OBSERVE_CLOCK_reserved0_MASK 0xffffffc0
-#define BCHP_CLKGEN_AIF_WB_SAT_TOP_0_INST_OBSERVE_CLOCK_reserved0_SHIFT 6
-
-/* CLKGEN :: AIF_WB_SAT_TOP_0_INST_OBSERVE_CLOCK :: AIF0_ENABLE_OBSERVE_CLOCK [05:05] */
-#define BCHP_CLKGEN_AIF_WB_SAT_TOP_0_INST_OBSERVE_CLOCK_AIF0_ENABLE_OBSERVE_CLOCK_MASK 0x00000020
-#define BCHP_CLKGEN_AIF_WB_SAT_TOP_0_INST_OBSERVE_CLOCK_AIF0_ENABLE_OBSERVE_CLOCK_SHIFT 5
-#define BCHP_CLKGEN_AIF_WB_SAT_TOP_0_INST_OBSERVE_CLOCK_AIF0_ENABLE_OBSERVE_CLOCK_DEFAULT 0x00000000
-
-/* CLKGEN :: AIF_WB_SAT_TOP_0_INST_OBSERVE_CLOCK :: AIF0_ENABLE_DIVIDER_OBSERVE_CLOCK [04:04] */
-#define BCHP_CLKGEN_AIF_WB_SAT_TOP_0_INST_OBSERVE_CLOCK_AIF0_ENABLE_DIVIDER_OBSERVE_CLOCK_MASK 0x00000010
-#define BCHP_CLKGEN_AIF_WB_SAT_TOP_0_INST_OBSERVE_CLOCK_AIF0_ENABLE_DIVIDER_OBSERVE_CLOCK_SHIFT 4
-#define BCHP_CLKGEN_AIF_WB_SAT_TOP_0_INST_OBSERVE_CLOCK_AIF0_ENABLE_DIVIDER_OBSERVE_CLOCK_DEFAULT 0x00000000
-
-/* CLKGEN :: AIF_WB_SAT_TOP_0_INST_OBSERVE_CLOCK :: AIF0_CONTROL_OBSERVE_CLOCK [03:00] */
-#define BCHP_CLKGEN_AIF_WB_SAT_TOP_0_INST_OBSERVE_CLOCK_AIF0_CONTROL_OBSERVE_CLOCK_MASK 0x0000000f
-#define BCHP_CLKGEN_AIF_WB_SAT_TOP_0_INST_OBSERVE_CLOCK_AIF0_CONTROL_OBSERVE_CLOCK_SHIFT 0
-#define BCHP_CLKGEN_AIF_WB_SAT_TOP_0_INST_OBSERVE_CLOCK_AIF0_CONTROL_OBSERVE_CLOCK_DEFAULT 0x00000000
-
-/***************************************************************************
- *AIF_WB_SAT_TOP_0_INST_SEL - Aif wb sat top 0 inst sel
- ***************************************************************************/
-/* CLKGEN :: AIF_WB_SAT_TOP_0_INST_SEL :: reserved0 [31:01] */
-#define BCHP_CLKGEN_AIF_WB_SAT_TOP_0_INST_SEL_reserved0_MASK 0xfffffffe
-#define BCHP_CLKGEN_AIF_WB_SAT_TOP_0_INST_SEL_reserved0_SHIFT 1
-
-/* CLKGEN :: AIF_WB_SAT_TOP_0_INST_SEL :: AIF0_BYPASS_CLK_ADC_SEL [00:00] */
-#define BCHP_CLKGEN_AIF_WB_SAT_TOP_0_INST_SEL_AIF0_BYPASS_CLK_ADC_SEL_MASK 0x00000001
-#define BCHP_CLKGEN_AIF_WB_SAT_TOP_0_INST_SEL_AIF0_BYPASS_CLK_ADC_SEL_SHIFT 0
-#define BCHP_CLKGEN_AIF_WB_SAT_TOP_0_INST_SEL_AIF0_BYPASS_CLK_ADC_SEL_DEFAULT 0x00000000
-
-/***************************************************************************
- *AIF_WB_SAT_TOP_1_INST_CLOCK_ENABLE - Aif wb sat top 1 inst clock enable
- ***************************************************************************/
-/* CLKGEN :: AIF_WB_SAT_TOP_1_INST_CLOCK_ENABLE :: reserved0 [31:02] */
-#define BCHP_CLKGEN_AIF_WB_SAT_TOP_1_INST_CLOCK_ENABLE_reserved0_MASK 0xfffffffc
-#define BCHP_CLKGEN_AIF_WB_SAT_TOP_1_INST_CLOCK_ENABLE_reserved0_SHIFT 2
-
-/* CLKGEN :: AIF_WB_SAT_TOP_1_INST_CLOCK_ENABLE :: AIF1_54_CLOCK_ENABLE [01:01] */
-#define BCHP_CLKGEN_AIF_WB_SAT_TOP_1_INST_CLOCK_ENABLE_AIF1_54_CLOCK_ENABLE_MASK 0x00000002
-#define BCHP_CLKGEN_AIF_WB_SAT_TOP_1_INST_CLOCK_ENABLE_AIF1_54_CLOCK_ENABLE_SHIFT 1
-#define BCHP_CLKGEN_AIF_WB_SAT_TOP_1_INST_CLOCK_ENABLE_AIF1_54_CLOCK_ENABLE_DEFAULT 0x00000001
-
-/* CLKGEN :: AIF_WB_SAT_TOP_1_INST_CLOCK_ENABLE :: AIF1_108_CLOCK_ENABLE [00:00] */
-#define BCHP_CLKGEN_AIF_WB_SAT_TOP_1_INST_CLOCK_ENABLE_AIF1_108_CLOCK_ENABLE_MASK 0x00000001
-#define BCHP_CLKGEN_AIF_WB_SAT_TOP_1_INST_CLOCK_ENABLE_AIF1_108_CLOCK_ENABLE_SHIFT 0
-#define BCHP_CLKGEN_AIF_WB_SAT_TOP_1_INST_CLOCK_ENABLE_AIF1_108_CLOCK_ENABLE_DEFAULT 0x00000001
-
-/***************************************************************************
- *AIF_WB_SAT_TOP_1_INST_CLOCK_ENABLE_STATUS - Clock Enable Status
- ***************************************************************************/
-/* CLKGEN :: AIF_WB_SAT_TOP_1_INST_CLOCK_ENABLE_STATUS :: reserved0 [31:02] */
-#define BCHP_CLKGEN_AIF_WB_SAT_TOP_1_INST_CLOCK_ENABLE_STATUS_reserved0_MASK 0xfffffffc
-#define BCHP_CLKGEN_AIF_WB_SAT_TOP_1_INST_CLOCK_ENABLE_STATUS_reserved0_SHIFT 2
-
-/* CLKGEN :: AIF_WB_SAT_TOP_1_INST_CLOCK_ENABLE_STATUS :: AIF1_54_CLOCK_ENABLE_STATUS [01:01] */
-#define BCHP_CLKGEN_AIF_WB_SAT_TOP_1_INST_CLOCK_ENABLE_STATUS_AIF1_54_CLOCK_ENABLE_STATUS_MASK 0x00000002
-#define BCHP_CLKGEN_AIF_WB_SAT_TOP_1_INST_CLOCK_ENABLE_STATUS_AIF1_54_CLOCK_ENABLE_STATUS_SHIFT 1
-
-/* CLKGEN :: AIF_WB_SAT_TOP_1_INST_CLOCK_ENABLE_STATUS :: AIF1_108_CLOCK_ENABLE_STATUS [00:00] */
-#define BCHP_CLKGEN_AIF_WB_SAT_TOP_1_INST_CLOCK_ENABLE_STATUS_AIF1_108_CLOCK_ENABLE_STATUS_MASK 0x00000001
-#define BCHP_CLKGEN_AIF_WB_SAT_TOP_1_INST_CLOCK_ENABLE_STATUS_AIF1_108_CLOCK_ENABLE_STATUS_SHIFT 0
-
-/***************************************************************************
- *AIF_WB_SAT_TOP_1_INST_OBSERVE_CLOCK - Aif wb sat top 1 inst observe clock
- ***************************************************************************/
-/* CLKGEN :: AIF_WB_SAT_TOP_1_INST_OBSERVE_CLOCK :: reserved0 [31:06] */
-#define BCHP_CLKGEN_AIF_WB_SAT_TOP_1_INST_OBSERVE_CLOCK_reserved0_MASK 0xffffffc0
-#define BCHP_CLKGEN_AIF_WB_SAT_TOP_1_INST_OBSERVE_CLOCK_reserved0_SHIFT 6
-
-/* CLKGEN :: AIF_WB_SAT_TOP_1_INST_OBSERVE_CLOCK :: AIF1_ENABLE_OBSERVE_CLOCK [05:05] */
-#define BCHP_CLKGEN_AIF_WB_SAT_TOP_1_INST_OBSERVE_CLOCK_AIF1_ENABLE_OBSERVE_CLOCK_MASK 0x00000020
-#define BCHP_CLKGEN_AIF_WB_SAT_TOP_1_INST_OBSERVE_CLOCK_AIF1_ENABLE_OBSERVE_CLOCK_SHIFT 5
-#define BCHP_CLKGEN_AIF_WB_SAT_TOP_1_INST_OBSERVE_CLOCK_AIF1_ENABLE_OBSERVE_CLOCK_DEFAULT 0x00000000
-
-/* CLKGEN :: AIF_WB_SAT_TOP_1_INST_OBSERVE_CLOCK :: AIF1_ENABLE_DIVIDER_OBSERVE_CLOCK [04:04] */
-#define BCHP_CLKGEN_AIF_WB_SAT_TOP_1_INST_OBSERVE_CLOCK_AIF1_ENABLE_DIVIDER_OBSERVE_CLOCK_MASK 0x00000010
-#define BCHP_CLKGEN_AIF_WB_SAT_TOP_1_INST_OBSERVE_CLOCK_AIF1_ENABLE_DIVIDER_OBSERVE_CLOCK_SHIFT 4
-#define BCHP_CLKGEN_AIF_WB_SAT_TOP_1_INST_OBSERVE_CLOCK_AIF1_ENABLE_DIVIDER_OBSERVE_CLOCK_DEFAULT 0x00000000
-
-/* CLKGEN :: AIF_WB_SAT_TOP_1_INST_OBSERVE_CLOCK :: AIF1_CONTROL_OBSERVE_CLOCK [03:00] */
-#define BCHP_CLKGEN_AIF_WB_SAT_TOP_1_INST_OBSERVE_CLOCK_AIF1_CONTROL_OBSERVE_CLOCK_MASK 0x0000000f
-#define BCHP_CLKGEN_AIF_WB_SAT_TOP_1_INST_OBSERVE_CLOCK_AIF1_CONTROL_OBSERVE_CLOCK_SHIFT 0
-#define BCHP_CLKGEN_AIF_WB_SAT_TOP_1_INST_OBSERVE_CLOCK_AIF1_CONTROL_OBSERVE_CLOCK_DEFAULT 0x00000000
-
-/***************************************************************************
- *AIF_WB_SAT_TOP_1_INST_SEL - Aif wb sat top 1 inst sel
- ***************************************************************************/
-/* CLKGEN :: AIF_WB_SAT_TOP_1_INST_SEL :: reserved0 [31:01] */
-#define BCHP_CLKGEN_AIF_WB_SAT_TOP_1_INST_SEL_reserved0_MASK 0xfffffffe
-#define BCHP_CLKGEN_AIF_WB_SAT_TOP_1_INST_SEL_reserved0_SHIFT 1
-
-/* CLKGEN :: AIF_WB_SAT_TOP_1_INST_SEL :: AIF1_BYPASS_CLK_ADC_SEL [00:00] */
-#define BCHP_CLKGEN_AIF_WB_SAT_TOP_1_INST_SEL_AIF1_BYPASS_CLK_ADC_SEL_MASK 0x00000001
-#define BCHP_CLKGEN_AIF_WB_SAT_TOP_1_INST_SEL_AIF1_BYPASS_CLK_ADC_SEL_SHIFT 0
-#define BCHP_CLKGEN_AIF_WB_SAT_TOP_1_INST_SEL_AIF1_BYPASS_CLK_ADC_SEL_DEFAULT 0x00000000
-
-/***************************************************************************
- *ANA_QDAC_TS28HPM_6MX_2MR_FC_H_E_INST_CLOCK_DISABLE - Disable ANA_QDAC_TS28HPM_6MX_2MR_FC_H_E_INST's clocks
- ***************************************************************************/
-/* CLKGEN :: ANA_QDAC_TS28HPM_6MX_2MR_FC_H_E_INST_CLOCK_DISABLE :: reserved0 [31:01] */
-#define BCHP_CLKGEN_ANA_QDAC_TS28HPM_6MX_2MR_FC_H_E_INST_CLOCK_DISABLE_reserved0_MASK 0xfffffffe
-#define BCHP_CLKGEN_ANA_QDAC_TS28HPM_6MX_2MR_FC_H_E_INST_CLOCK_DISABLE_reserved0_SHIFT 1
-
-/* CLKGEN :: ANA_QDAC_TS28HPM_6MX_2MR_FC_H_E_INST_CLOCK_DISABLE :: DISABLE_QDAC_DACADC_CLOCK [00:00] */
-#define BCHP_CLKGEN_ANA_QDAC_TS28HPM_6MX_2MR_FC_H_E_INST_CLOCK_DISABLE_DISABLE_QDAC_DACADC_CLOCK_MASK 0x00000001
-#define BCHP_CLKGEN_ANA_QDAC_TS28HPM_6MX_2MR_FC_H_E_INST_CLOCK_DISABLE_DISABLE_QDAC_DACADC_CLOCK_SHIFT 0
-#define BCHP_CLKGEN_ANA_QDAC_TS28HPM_6MX_2MR_FC_H_E_INST_CLOCK_DISABLE_DISABLE_QDAC_DACADC_CLOCK_DEFAULT 0x00000000
-
-/***************************************************************************
- *ANA_QDAC_TS28HPM_6MX_2MR_FC_H_E_INST_CLOCK_DISABLE_STATUS - Clock Disable Status
- ***************************************************************************/
-/* CLKGEN :: ANA_QDAC_TS28HPM_6MX_2MR_FC_H_E_INST_CLOCK_DISABLE_STATUS :: reserved0 [31:01] */
-#define BCHP_CLKGEN_ANA_QDAC_TS28HPM_6MX_2MR_FC_H_E_INST_CLOCK_DISABLE_STATUS_reserved0_MASK 0xfffffffe
-#define BCHP_CLKGEN_ANA_QDAC_TS28HPM_6MX_2MR_FC_H_E_INST_CLOCK_DISABLE_STATUS_reserved0_SHIFT 1
-
-/* CLKGEN :: ANA_QDAC_TS28HPM_6MX_2MR_FC_H_E_INST_CLOCK_DISABLE_STATUS :: DISABLE_QDAC_DACADC_CLOCK_STATUS [00:00] */
-#define BCHP_CLKGEN_ANA_QDAC_TS28HPM_6MX_2MR_FC_H_E_INST_CLOCK_DISABLE_STATUS_DISABLE_QDAC_DACADC_CLOCK_STATUS_MASK 0x00000001
-#define BCHP_CLKGEN_ANA_QDAC_TS28HPM_6MX_2MR_FC_H_E_INST_CLOCK_DISABLE_STATUS_DISABLE_QDAC_DACADC_CLOCK_STATUS_SHIFT 0
-
-/***************************************************************************
- *ANA_SW_AVS_TS28HPM_6MX_2MR_FC_H_E_INST_CLOCK_DISABLE - Disable ANA_SW_AVS_TS28HPM_6MX_2MR_FC_H_E_INST's clocks
- ***************************************************************************/
-/* CLKGEN :: ANA_SW_AVS_TS28HPM_6MX_2MR_FC_H_E_INST_CLOCK_DISABLE :: reserved0 [31:01] */
-#define BCHP_CLKGEN_ANA_SW_AVS_TS28HPM_6MX_2MR_FC_H_E_INST_CLOCK_DISABLE_reserved0_MASK 0xfffffffe
-#define BCHP_CLKGEN_ANA_SW_AVS_TS28HPM_6MX_2MR_FC_H_E_INST_CLOCK_DISABLE_reserved0_SHIFT 1
-
-/* CLKGEN :: ANA_SW_AVS_TS28HPM_6MX_2MR_FC_H_E_INST_CLOCK_DISABLE :: DISABLE_SYSTEM_54_VR_CLOCK [00:00] */
-#define BCHP_CLKGEN_ANA_SW_AVS_TS28HPM_6MX_2MR_FC_H_E_INST_CLOCK_DISABLE_DISABLE_SYSTEM_54_VR_CLOCK_MASK 0x00000001
-#define BCHP_CLKGEN_ANA_SW_AVS_TS28HPM_6MX_2MR_FC_H_E_INST_CLOCK_DISABLE_DISABLE_SYSTEM_54_VR_CLOCK_SHIFT 0
-#define BCHP_CLKGEN_ANA_SW_AVS_TS28HPM_6MX_2MR_FC_H_E_INST_CLOCK_DISABLE_DISABLE_SYSTEM_54_VR_CLOCK_DEFAULT 0x00000000
-
-/***************************************************************************
- *ANA_SW_AVS_TS28HPM_6MX_2MR_FC_H_E_INST_CLOCK_DISABLE_STATUS - Clock Disable Status
- ***************************************************************************/
-/* CLKGEN :: ANA_SW_AVS_TS28HPM_6MX_2MR_FC_H_E_INST_CLOCK_DISABLE_STATUS :: reserved0 [31:01] */
-#define BCHP_CLKGEN_ANA_SW_AVS_TS28HPM_6MX_2MR_FC_H_E_INST_CLOCK_DISABLE_STATUS_reserved0_MASK 0xfffffffe
-#define BCHP_CLKGEN_ANA_SW_AVS_TS28HPM_6MX_2MR_FC_H_E_INST_CLOCK_DISABLE_STATUS_reserved0_SHIFT 1
-
-/* CLKGEN :: ANA_SW_AVS_TS28HPM_6MX_2MR_FC_H_E_INST_CLOCK_DISABLE_STATUS :: DISABLE_SYSTEM_54_VR_CLOCK_STATUS [00:00] */
-#define BCHP_CLKGEN_ANA_SW_AVS_TS28HPM_6MX_2MR_FC_H_E_INST_CLOCK_DISABLE_STATUS_DISABLE_SYSTEM_54_VR_CLOCK_STATUS_MASK 0x00000001
-#define BCHP_CLKGEN_ANA_SW_AVS_TS28HPM_6MX_2MR_FC_H_E_INST_CLOCK_DISABLE_STATUS_DISABLE_SYSTEM_54_VR_CLOCK_STATUS_SHIFT 0
-
-/***************************************************************************
- *BVN_MVP_TOP_INST_CKTAPSEL - Bvn mvp top inst cktapsel
- ***************************************************************************/
-/* CLKGEN :: BVN_MVP_TOP_INST_CKTAPSEL :: reserved0 [31:12] */
-#define BCHP_CLKGEN_BVN_MVP_TOP_INST_CKTAPSEL_reserved0_MASK 0xfffff000
-#define BCHP_CLKGEN_BVN_MVP_TOP_INST_CKTAPSEL_reserved0_SHIFT 12
-
-/* CLKGEN :: BVN_MVP_TOP_INST_CKTAPSEL :: SCB_CKTAP1_CKTAPSEL [11:06] */
-#define BCHP_CLKGEN_BVN_MVP_TOP_INST_CKTAPSEL_SCB_CKTAP1_CKTAPSEL_MASK 0x00000fc0
-#define BCHP_CLKGEN_BVN_MVP_TOP_INST_CKTAPSEL_SCB_CKTAP1_CKTAPSEL_SHIFT 6
-#define BCHP_CLKGEN_BVN_MVP_TOP_INST_CKTAPSEL_SCB_CKTAP1_CKTAPSEL_DEFAULT 0x00000000
-
-/* CLKGEN :: BVN_MVP_TOP_INST_CKTAPSEL :: SCB_CKTAP0_CKTAPSEL [05:00] */
-#define BCHP_CLKGEN_BVN_MVP_TOP_INST_CKTAPSEL_SCB_CKTAP0_CKTAPSEL_MASK 0x0000003f
-#define BCHP_CLKGEN_BVN_MVP_TOP_INST_CKTAPSEL_SCB_CKTAP0_CKTAPSEL_SHIFT 0
-#define BCHP_CLKGEN_BVN_MVP_TOP_INST_CKTAPSEL_SCB_CKTAP0_CKTAPSEL_DEFAULT 0x00000000
-
-/***************************************************************************
- *BVN_MVP_TOP_INST_CLOCK_ENABLE - Bvn mvp top inst clock enable
- ***************************************************************************/
-/* CLKGEN :: BVN_MVP_TOP_INST_CLOCK_ENABLE :: reserved0 [31:04] */
-#define BCHP_CLKGEN_BVN_MVP_TOP_INST_CLOCK_ENABLE_reserved0_MASK 0xfffffff0
-#define BCHP_CLKGEN_BVN_MVP_TOP_INST_CLOCK_ENABLE_reserved0_SHIFT 4
-
-/* CLKGEN :: BVN_MVP_TOP_INST_CLOCK_ENABLE :: BVND_SCB_CLOCK_ENABLE [03:03] */
-#define BCHP_CLKGEN_BVN_MVP_TOP_INST_CLOCK_ENABLE_BVND_SCB_CLOCK_ENABLE_MASK 0x00000008
-#define BCHP_CLKGEN_BVN_MVP_TOP_INST_CLOCK_ENABLE_BVND_SCB_CLOCK_ENABLE_SHIFT 3
-#define BCHP_CLKGEN_BVN_MVP_TOP_INST_CLOCK_ENABLE_BVND_SCB_CLOCK_ENABLE_DEFAULT 0x00000001
-
-/* CLKGEN :: BVN_MVP_TOP_INST_CLOCK_ENABLE :: BVND_BVB_324_CLOCK_ENABLE [02:02] */
-#define BCHP_CLKGEN_BVN_MVP_TOP_INST_CLOCK_ENABLE_BVND_BVB_324_CLOCK_ENABLE_MASK 0x00000004
-#define BCHP_CLKGEN_BVN_MVP_TOP_INST_CLOCK_ENABLE_BVND_BVB_324_CLOCK_ENABLE_SHIFT 2
-#define BCHP_CLKGEN_BVN_MVP_TOP_INST_CLOCK_ENABLE_BVND_BVB_324_CLOCK_ENABLE_DEFAULT 0x00000001
-
-/* CLKGEN :: BVN_MVP_TOP_INST_CLOCK_ENABLE :: BVND_54_CLOCK_ENABLE [01:01] */
-#define BCHP_CLKGEN_BVN_MVP_TOP_INST_CLOCK_ENABLE_BVND_54_CLOCK_ENABLE_MASK 0x00000002
-#define BCHP_CLKGEN_BVN_MVP_TOP_INST_CLOCK_ENABLE_BVND_54_CLOCK_ENABLE_SHIFT 1
-#define BCHP_CLKGEN_BVN_MVP_TOP_INST_CLOCK_ENABLE_BVND_54_CLOCK_ENABLE_DEFAULT 0x00000001
-
-/* CLKGEN :: BVN_MVP_TOP_INST_CLOCK_ENABLE :: BVND_108_CLOCK_ENABLE [00:00] */
-#define BCHP_CLKGEN_BVN_MVP_TOP_INST_CLOCK_ENABLE_BVND_108_CLOCK_ENABLE_MASK 0x00000001
-#define BCHP_CLKGEN_BVN_MVP_TOP_INST_CLOCK_ENABLE_BVND_108_CLOCK_ENABLE_SHIFT 0
-#define BCHP_CLKGEN_BVN_MVP_TOP_INST_CLOCK_ENABLE_BVND_108_CLOCK_ENABLE_DEFAULT 0x00000001
-
-/***************************************************************************
- *BVN_MVP_TOP_INST_CLOCK_ENABLE_STATUS - Clock Enable Status
- ***************************************************************************/
-/* CLKGEN :: BVN_MVP_TOP_INST_CLOCK_ENABLE_STATUS :: reserved0 [31:04] */
-#define BCHP_CLKGEN_BVN_MVP_TOP_INST_CLOCK_ENABLE_STATUS_reserved0_MASK 0xfffffff0
-#define BCHP_CLKGEN_BVN_MVP_TOP_INST_CLOCK_ENABLE_STATUS_reserved0_SHIFT 4
-
-/* CLKGEN :: BVN_MVP_TOP_INST_CLOCK_ENABLE_STATUS :: BVND_SCB_CLOCK_ENABLE_STATUS [03:03] */
-#define BCHP_CLKGEN_BVN_MVP_TOP_INST_CLOCK_ENABLE_STATUS_BVND_SCB_CLOCK_ENABLE_STATUS_MASK 0x00000008
-#define BCHP_CLKGEN_BVN_MVP_TOP_INST_CLOCK_ENABLE_STATUS_BVND_SCB_CLOCK_ENABLE_STATUS_SHIFT 3
-
-/* CLKGEN :: BVN_MVP_TOP_INST_CLOCK_ENABLE_STATUS :: BVND_BVB_324_CLOCK_ENABLE_STATUS [02:02] */
-#define BCHP_CLKGEN_BVN_MVP_TOP_INST_CLOCK_ENABLE_STATUS_BVND_BVB_324_CLOCK_ENABLE_STATUS_MASK 0x00000004
-#define BCHP_CLKGEN_BVN_MVP_TOP_INST_CLOCK_ENABLE_STATUS_BVND_BVB_324_CLOCK_ENABLE_STATUS_SHIFT 2
-
-/* CLKGEN :: BVN_MVP_TOP_INST_CLOCK_ENABLE_STATUS :: BVND_54_CLOCK_ENABLE_STATUS [01:01] */
-#define BCHP_CLKGEN_BVN_MVP_TOP_INST_CLOCK_ENABLE_STATUS_BVND_54_CLOCK_ENABLE_STATUS_MASK 0x00000002
-#define BCHP_CLKGEN_BVN_MVP_TOP_INST_CLOCK_ENABLE_STATUS_BVND_54_CLOCK_ENABLE_STATUS_SHIFT 1
-
-/* CLKGEN :: BVN_MVP_TOP_INST_CLOCK_ENABLE_STATUS :: BVND_108_CLOCK_ENABLE_STATUS [00:00] */
-#define BCHP_CLKGEN_BVN_MVP_TOP_INST_CLOCK_ENABLE_STATUS_BVND_108_CLOCK_ENABLE_STATUS_MASK 0x00000001
-#define BCHP_CLKGEN_BVN_MVP_TOP_INST_CLOCK_ENABLE_STATUS_BVND_108_CLOCK_ENABLE_STATUS_SHIFT 0
-
-/***************************************************************************
- *BVN_TOP_INST_CKTAPSEL - Bvn top inst cktapsel
- ***************************************************************************/
-/* CLKGEN :: BVN_TOP_INST_CKTAPSEL :: reserved0 [31:12] */
-#define BCHP_CLKGEN_BVN_TOP_INST_CKTAPSEL_reserved0_MASK 0xfffff000
-#define BCHP_CLKGEN_BVN_TOP_INST_CKTAPSEL_reserved0_SHIFT 12
-
-/* CLKGEN :: BVN_TOP_INST_CKTAPSEL :: SCB_CKTAP1_CKTAPSEL [11:06] */
-#define BCHP_CLKGEN_BVN_TOP_INST_CKTAPSEL_SCB_CKTAP1_CKTAPSEL_MASK 0x00000fc0
-#define BCHP_CLKGEN_BVN_TOP_INST_CKTAPSEL_SCB_CKTAP1_CKTAPSEL_SHIFT 6
-#define BCHP_CLKGEN_BVN_TOP_INST_CKTAPSEL_SCB_CKTAP1_CKTAPSEL_DEFAULT 0x00000000
-
-/* CLKGEN :: BVN_TOP_INST_CKTAPSEL :: SCB_CKTAP0_CKTAPSEL [05:00] */
-#define BCHP_CLKGEN_BVN_TOP_INST_CKTAPSEL_SCB_CKTAP0_CKTAPSEL_MASK 0x0000003f
-#define BCHP_CLKGEN_BVN_TOP_INST_CKTAPSEL_SCB_CKTAP0_CKTAPSEL_SHIFT 0
-#define BCHP_CLKGEN_BVN_TOP_INST_CKTAPSEL_SCB_CKTAP0_CKTAPSEL_DEFAULT 0x00000000
-
-/***************************************************************************
- *BVN_TOP_INST_CLOCK_ENABLE - Bvn top inst clock enable
- ***************************************************************************/
-/* CLKGEN :: BVN_TOP_INST_CLOCK_ENABLE :: reserved0 [31:05] */
-#define BCHP_CLKGEN_BVN_TOP_INST_CLOCK_ENABLE_reserved0_MASK 0xffffffe0
-#define BCHP_CLKGEN_BVN_TOP_INST_CLOCK_ENABLE_reserved0_SHIFT 5
-
-/* CLKGEN :: BVN_TOP_INST_CLOCK_ENABLE :: BVN_SCB_CLOCK_ENABLE [04:04] */
-#define BCHP_CLKGEN_BVN_TOP_INST_CLOCK_ENABLE_BVN_SCB_CLOCK_ENABLE_MASK 0x00000010
-#define BCHP_CLKGEN_BVN_TOP_INST_CLOCK_ENABLE_BVN_SCB_CLOCK_ENABLE_SHIFT 4
-#define BCHP_CLKGEN_BVN_TOP_INST_CLOCK_ENABLE_BVN_SCB_CLOCK_ENABLE_DEFAULT 0x00000001
-
-/* CLKGEN :: BVN_TOP_INST_CLOCK_ENABLE :: BVN_GISB_CLOCK_ENABLE [03:03] */
-#define BCHP_CLKGEN_BVN_TOP_INST_CLOCK_ENABLE_BVN_GISB_CLOCK_ENABLE_MASK 0x00000008
-#define BCHP_CLKGEN_BVN_TOP_INST_CLOCK_ENABLE_BVN_GISB_CLOCK_ENABLE_SHIFT 3
-#define BCHP_CLKGEN_BVN_TOP_INST_CLOCK_ENABLE_BVN_GISB_CLOCK_ENABLE_DEFAULT 0x00000001
-
-/* CLKGEN :: BVN_TOP_INST_CLOCK_ENABLE :: BVN_BVB_648_CLOCK_ENABLE [02:02] */
-#define BCHP_CLKGEN_BVN_TOP_INST_CLOCK_ENABLE_BVN_BVB_648_CLOCK_ENABLE_MASK 0x00000004
-#define BCHP_CLKGEN_BVN_TOP_INST_CLOCK_ENABLE_BVN_BVB_648_CLOCK_ENABLE_SHIFT 2
-#define BCHP_CLKGEN_BVN_TOP_INST_CLOCK_ENABLE_BVN_BVB_648_CLOCK_ENABLE_DEFAULT 0x00000001
-
-/* CLKGEN :: BVN_TOP_INST_CLOCK_ENABLE :: BVN_BVB_324_CLOCK_ENABLE [01:01] */
-#define BCHP_CLKGEN_BVN_TOP_INST_CLOCK_ENABLE_BVN_BVB_324_CLOCK_ENABLE_MASK 0x00000002
-#define BCHP_CLKGEN_BVN_TOP_INST_CLOCK_ENABLE_BVN_BVB_324_CLOCK_ENABLE_SHIFT 1
-#define BCHP_CLKGEN_BVN_TOP_INST_CLOCK_ENABLE_BVN_BVB_324_CLOCK_ENABLE_DEFAULT 0x00000001
-
-/* CLKGEN :: BVN_TOP_INST_CLOCK_ENABLE :: BVN_54_CLOCK_ENABLE [00:00] */
-#define BCHP_CLKGEN_BVN_TOP_INST_CLOCK_ENABLE_BVN_54_CLOCK_ENABLE_MASK 0x00000001
-#define BCHP_CLKGEN_BVN_TOP_INST_CLOCK_ENABLE_BVN_54_CLOCK_ENABLE_SHIFT 0
-#define BCHP_CLKGEN_BVN_TOP_INST_CLOCK_ENABLE_BVN_54_CLOCK_ENABLE_DEFAULT 0x00000001
-
-/***************************************************************************
- *BVN_TOP_INST_CLOCK_ENABLE_STATUS - Clock Enable Status
- ***************************************************************************/
-/* CLKGEN :: BVN_TOP_INST_CLOCK_ENABLE_STATUS :: reserved0 [31:05] */
-#define BCHP_CLKGEN_BVN_TOP_INST_CLOCK_ENABLE_STATUS_reserved0_MASK 0xffffffe0
-#define BCHP_CLKGEN_BVN_TOP_INST_CLOCK_ENABLE_STATUS_reserved0_SHIFT 5
-
-/* CLKGEN :: BVN_TOP_INST_CLOCK_ENABLE_STATUS :: BVN_SCB_CLOCK_ENABLE_STATUS [04:04] */
-#define BCHP_CLKGEN_BVN_TOP_INST_CLOCK_ENABLE_STATUS_BVN_SCB_CLOCK_ENABLE_STATUS_MASK 0x00000010
-#define BCHP_CLKGEN_BVN_TOP_INST_CLOCK_ENABLE_STATUS_BVN_SCB_CLOCK_ENABLE_STATUS_SHIFT 4
-
-/* CLKGEN :: BVN_TOP_INST_CLOCK_ENABLE_STATUS :: BVN_GISB_CLOCK_ENABLE_STATUS [03:03] */
-#define BCHP_CLKGEN_BVN_TOP_INST_CLOCK_ENABLE_STATUS_BVN_GISB_CLOCK_ENABLE_STATUS_MASK 0x00000008
-#define BCHP_CLKGEN_BVN_TOP_INST_CLOCK_ENABLE_STATUS_BVN_GISB_CLOCK_ENABLE_STATUS_SHIFT 3
-
-/* CLKGEN :: BVN_TOP_INST_CLOCK_ENABLE_STATUS :: BVN_BVB_648_CLOCK_ENABLE_STATUS [02:02] */
-#define BCHP_CLKGEN_BVN_TOP_INST_CLOCK_ENABLE_STATUS_BVN_BVB_648_CLOCK_ENABLE_STATUS_MASK 0x00000004
-#define BCHP_CLKGEN_BVN_TOP_INST_CLOCK_ENABLE_STATUS_BVN_BVB_648_CLOCK_ENABLE_STATUS_SHIFT 2
-
-/* CLKGEN :: BVN_TOP_INST_CLOCK_ENABLE_STATUS :: BVN_BVB_324_CLOCK_ENABLE_STATUS [01:01] */
-#define BCHP_CLKGEN_BVN_TOP_INST_CLOCK_ENABLE_STATUS_BVN_BVB_324_CLOCK_ENABLE_STATUS_MASK 0x00000002
-#define BCHP_CLKGEN_BVN_TOP_INST_CLOCK_ENABLE_STATUS_BVN_BVB_324_CLOCK_ENABLE_STATUS_SHIFT 1
-
-/* CLKGEN :: BVN_TOP_INST_CLOCK_ENABLE_STATUS :: BVN_54_CLOCK_ENABLE_STATUS [00:00] */
-#define BCHP_CLKGEN_BVN_TOP_INST_CLOCK_ENABLE_STATUS_BVN_54_CLOCK_ENABLE_STATUS_MASK 0x00000001
-#define BCHP_CLKGEN_BVN_TOP_INST_CLOCK_ENABLE_STATUS_BVN_54_CLOCK_ENABLE_STATUS_SHIFT 0
-
-/***************************************************************************
- *CLKGEN_CLOCK_DISABLE - Disable CLKGEN's clocks
- ***************************************************************************/
-/* CLKGEN :: CLKGEN_CLOCK_DISABLE :: reserved0 [31:01] */
-#define BCHP_CLKGEN_CLKGEN_CLOCK_DISABLE_reserved0_MASK 0xfffffffe
-#define BCHP_CLKGEN_CLKGEN_CLOCK_DISABLE_reserved0_SHIFT 1
-
-/* CLKGEN :: CLKGEN_CLOCK_DISABLE :: DISABLE_OSC_DIGITAL_CLOCK [00:00] */
-#define BCHP_CLKGEN_CLKGEN_CLOCK_DISABLE_DISABLE_OSC_DIGITAL_CLOCK_MASK 0x00000001
-#define BCHP_CLKGEN_CLKGEN_CLOCK_DISABLE_DISABLE_OSC_DIGITAL_CLOCK_SHIFT 0
-#define BCHP_CLKGEN_CLKGEN_CLOCK_DISABLE_DISABLE_OSC_DIGITAL_CLOCK_DEFAULT 0x00000000
-
-/***************************************************************************
- *CLKGEN_CLOCK_DISABLE_STATUS - Clock Disable Status
- ***************************************************************************/
-/* CLKGEN :: CLKGEN_CLOCK_DISABLE_STATUS :: reserved0 [31:01] */
-#define BCHP_CLKGEN_CLKGEN_CLOCK_DISABLE_STATUS_reserved0_MASK 0xfffffffe
-#define BCHP_CLKGEN_CLKGEN_CLOCK_DISABLE_STATUS_reserved0_SHIFT 1
-
-/* CLKGEN :: CLKGEN_CLOCK_DISABLE_STATUS :: DISABLE_OSC_DIGITAL_CLOCK_STATUS [00:00] */
-#define BCHP_CLKGEN_CLKGEN_CLOCK_DISABLE_STATUS_DISABLE_OSC_DIGITAL_CLOCK_STATUS_MASK 0x00000001
-#define BCHP_CLKGEN_CLKGEN_CLOCK_DISABLE_STATUS_DISABLE_OSC_DIGITAL_CLOCK_STATUS_SHIFT 0
-
-/***************************************************************************
- *CLOCK_MONITOR_CONTROL - Clock Monitor Control
- ***************************************************************************/
-/* CLKGEN :: CLOCK_MONITOR_CONTROL :: reserved0 [31:04] */
-#define BCHP_CLKGEN_CLOCK_MONITOR_CONTROL_reserved0_MASK 0xfffffff0
-#define BCHP_CLKGEN_CLOCK_MONITOR_CONTROL_reserved0_SHIFT 4
-
-/* CLKGEN :: CLOCK_MONITOR_CONTROL :: STOP_VIEW_COUNTER [03:03] */
-#define BCHP_CLKGEN_CLOCK_MONITOR_CONTROL_STOP_VIEW_COUNTER_MASK 0x00000008
-#define BCHP_CLKGEN_CLOCK_MONITOR_CONTROL_STOP_VIEW_COUNTER_SHIFT 3
-#define BCHP_CLKGEN_CLOCK_MONITOR_CONTROL_STOP_VIEW_COUNTER_DEFAULT 0x00000001
-
-/* CLKGEN :: CLOCK_MONITOR_CONTROL :: STOP_REF_COUNTER [02:02] */
-#define BCHP_CLKGEN_CLOCK_MONITOR_CONTROL_STOP_REF_COUNTER_MASK 0x00000004
-#define BCHP_CLKGEN_CLOCK_MONITOR_CONTROL_STOP_REF_COUNTER_SHIFT 2
-#define BCHP_CLKGEN_CLOCK_MONITOR_CONTROL_STOP_REF_COUNTER_DEFAULT 0x00000001
-
-/* CLKGEN :: CLOCK_MONITOR_CONTROL :: RESET_COUNTERS [01:01] */
-#define BCHP_CLKGEN_CLOCK_MONITOR_CONTROL_RESET_COUNTERS_MASK 0x00000002
-#define BCHP_CLKGEN_CLOCK_MONITOR_CONTROL_RESET_COUNTERS_SHIFT 1
-#define BCHP_CLKGEN_CLOCK_MONITOR_CONTROL_RESET_COUNTERS_DEFAULT 0x00000001
-
-/* CLKGEN :: CLOCK_MONITOR_CONTROL :: LAUNCH_AUTO_REF_COUNT [00:00] */
-#define BCHP_CLKGEN_CLOCK_MONITOR_CONTROL_LAUNCH_AUTO_REF_COUNT_MASK 0x00000001
-#define BCHP_CLKGEN_CLOCK_MONITOR_CONTROL_LAUNCH_AUTO_REF_COUNT_SHIFT 0
-#define BCHP_CLKGEN_CLOCK_MONITOR_CONTROL_LAUNCH_AUTO_REF_COUNT_DEFAULT 0x00000001
-
-/***************************************************************************
- *CLOCK_MONITOR_MAX_COUNT - Clock Monitor Max Reference Count
- ***************************************************************************/
-/* CLKGEN :: CLOCK_MONITOR_MAX_COUNT :: SET_MAX_REF_COUNT [31:00] */
-#define BCHP_CLKGEN_CLOCK_MONITOR_MAX_COUNT_SET_MAX_REF_COUNT_MASK 0xffffffff
-#define BCHP_CLKGEN_CLOCK_MONITOR_MAX_COUNT_SET_MAX_REF_COUNT_SHIFT 0
-#define BCHP_CLKGEN_CLOCK_MONITOR_MAX_COUNT_SET_MAX_REF_COUNT_DEFAULT 0xffffffff
-
-/***************************************************************************
- *CLOCK_MONITOR_REF_COUNTER - Clock Monitor Reference Counter
- ***************************************************************************/
-/* CLKGEN :: CLOCK_MONITOR_REF_COUNTER :: READ_MAX_COUNT [31:00] */
-#define BCHP_CLKGEN_CLOCK_MONITOR_REF_COUNTER_READ_MAX_COUNT_MASK 0xffffffff
-#define BCHP_CLKGEN_CLOCK_MONITOR_REF_COUNTER_READ_MAX_COUNT_SHIFT 0
-
-/***************************************************************************
- *CLOCK_MONITOR_REF_DONE - Clock Monitor Reference Counter
- ***************************************************************************/
-/* CLKGEN :: CLOCK_MONITOR_REF_DONE :: reserved0 [31:01] */
-#define BCHP_CLKGEN_CLOCK_MONITOR_REF_DONE_reserved0_MASK 0xfffffffe
-#define BCHP_CLKGEN_CLOCK_MONITOR_REF_DONE_reserved0_SHIFT 1
-
-/* CLKGEN :: CLOCK_MONITOR_REF_DONE :: REF_COUNT_DONE [00:00] */
-#define BCHP_CLKGEN_CLOCK_MONITOR_REF_DONE_REF_COUNT_DONE_MASK 0x00000001
-#define BCHP_CLKGEN_CLOCK_MONITOR_REF_DONE_REF_COUNT_DONE_SHIFT 0
-
-/***************************************************************************
- *CLOCK_MONITOR_VIEW_COUNTER - Clock Monitor View Counter
- ***************************************************************************/
-/* CLKGEN :: CLOCK_MONITOR_VIEW_COUNTER :: READ_MAX_COUNT [31:00] */
-#define BCHP_CLKGEN_CLOCK_MONITOR_VIEW_COUNTER_READ_MAX_COUNT_MASK 0xffffffff
-#define BCHP_CLKGEN_CLOCK_MONITOR_VIEW_COUNTER_READ_MAX_COUNT_SHIFT 0
-
-/***************************************************************************
- *CORE_XPT_INST_CKTAPSEL - Core xpt inst cktapsel
- ***************************************************************************/
-/* CLKGEN :: CORE_XPT_INST_CKTAPSEL :: reserved0 [31:12] */
-#define BCHP_CLKGEN_CORE_XPT_INST_CKTAPSEL_reserved0_MASK 0xfffff000
-#define BCHP_CLKGEN_CORE_XPT_INST_CKTAPSEL_reserved0_SHIFT 12
-
-/* CLKGEN :: CORE_XPT_INST_CKTAPSEL :: SCB_CKTAP1_CKTAPSEL [11:06] */
-#define BCHP_CLKGEN_CORE_XPT_INST_CKTAPSEL_SCB_CKTAP1_CKTAPSEL_MASK 0x00000fc0
-#define BCHP_CLKGEN_CORE_XPT_INST_CKTAPSEL_SCB_CKTAP1_CKTAPSEL_SHIFT 6
-#define BCHP_CLKGEN_CORE_XPT_INST_CKTAPSEL_SCB_CKTAP1_CKTAPSEL_DEFAULT 0x00000000
-
-/* CLKGEN :: CORE_XPT_INST_CKTAPSEL :: SCB_CKTAP0_CKTAPSEL [05:00] */
-#define BCHP_CLKGEN_CORE_XPT_INST_CKTAPSEL_SCB_CKTAP0_CKTAPSEL_MASK 0x0000003f
-#define BCHP_CLKGEN_CORE_XPT_INST_CKTAPSEL_SCB_CKTAP0_CKTAPSEL_SHIFT 0
-#define BCHP_CLKGEN_CORE_XPT_INST_CKTAPSEL_SCB_CKTAP0_CKTAPSEL_DEFAULT 0x00000000
-
-/***************************************************************************
- *CORE_XPT_INST_CLOCK_DISABLE - Disable CORE_XPT_INST's clocks
- ***************************************************************************/
-/* CLKGEN :: CORE_XPT_INST_CLOCK_DISABLE :: reserved0 [31:05] */
-#define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_DISABLE_reserved0_MASK 0xffffffe0
-#define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_DISABLE_reserved0_SHIFT 5
-
-/* CLKGEN :: CORE_XPT_INST_CLOCK_DISABLE :: DISABLE_XPT_81_CLOCK [04:04] */
-#define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_DISABLE_DISABLE_XPT_81_CLOCK_MASK 0x00000010
-#define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_DISABLE_DISABLE_XPT_81_CLOCK_SHIFT 4
-#define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_DISABLE_DISABLE_XPT_81_CLOCK_DEFAULT 0x00000000
-
-/* CLKGEN :: CORE_XPT_INST_CLOCK_DISABLE :: DISABLE_XPT_54_CLOCK [03:03] */
-#define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_DISABLE_DISABLE_XPT_54_CLOCK_MASK 0x00000008
-#define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_DISABLE_DISABLE_XPT_54_CLOCK_SHIFT 3
-#define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_DISABLE_DISABLE_XPT_54_CLOCK_DEFAULT 0x00000000
-
-/* CLKGEN :: CORE_XPT_INST_CLOCK_DISABLE :: DISABLE_XPT_40P5_CLOCK [02:02] */
-#define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_DISABLE_DISABLE_XPT_40P5_CLOCK_MASK 0x00000004
-#define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_DISABLE_DISABLE_XPT_40P5_CLOCK_SHIFT 2
-#define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_DISABLE_DISABLE_XPT_40P5_CLOCK_DEFAULT 0x00000000
-
-/* CLKGEN :: CORE_XPT_INST_CLOCK_DISABLE :: DISABLE_XPT_27_CLOCK [01:01] */
-#define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_DISABLE_DISABLE_XPT_27_CLOCK_MASK 0x00000002
-#define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_DISABLE_DISABLE_XPT_27_CLOCK_SHIFT 1
-#define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_DISABLE_DISABLE_XPT_27_CLOCK_DEFAULT 0x00000000
-
-/* CLKGEN :: CORE_XPT_INST_CLOCK_DISABLE :: DISABLE_XPT_20P25_CLOCK [00:00] */
-#define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_DISABLE_DISABLE_XPT_20P25_CLOCK_MASK 0x00000001
-#define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_DISABLE_DISABLE_XPT_20P25_CLOCK_SHIFT 0
-#define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_DISABLE_DISABLE_XPT_20P25_CLOCK_DEFAULT 0x00000000
-
-/***************************************************************************
- *CORE_XPT_INST_CLOCK_DISABLE_STATUS - Clock Disable Status
- ***************************************************************************/
-/* CLKGEN :: CORE_XPT_INST_CLOCK_DISABLE_STATUS :: reserved0 [31:05] */
-#define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_DISABLE_STATUS_reserved0_MASK 0xffffffe0
-#define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_DISABLE_STATUS_reserved0_SHIFT 5
-
-/* CLKGEN :: CORE_XPT_INST_CLOCK_DISABLE_STATUS :: DISABLE_XPT_81_CLOCK_STATUS [04:04] */
-#define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_DISABLE_STATUS_DISABLE_XPT_81_CLOCK_STATUS_MASK 0x00000010
-#define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_DISABLE_STATUS_DISABLE_XPT_81_CLOCK_STATUS_SHIFT 4
-
-/* CLKGEN :: CORE_XPT_INST_CLOCK_DISABLE_STATUS :: DISABLE_XPT_54_CLOCK_STATUS [03:03] */
-#define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_DISABLE_STATUS_DISABLE_XPT_54_CLOCK_STATUS_MASK 0x00000008
-#define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_DISABLE_STATUS_DISABLE_XPT_54_CLOCK_STATUS_SHIFT 3
-
-/* CLKGEN :: CORE_XPT_INST_CLOCK_DISABLE_STATUS :: DISABLE_XPT_40P5_CLOCK_STATUS [02:02] */
-#define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_DISABLE_STATUS_DISABLE_XPT_40P5_CLOCK_STATUS_MASK 0x00000004
-#define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_DISABLE_STATUS_DISABLE_XPT_40P5_CLOCK_STATUS_SHIFT 2
-
-/* CLKGEN :: CORE_XPT_INST_CLOCK_DISABLE_STATUS :: DISABLE_XPT_27_CLOCK_STATUS [01:01] */
-#define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_DISABLE_STATUS_DISABLE_XPT_27_CLOCK_STATUS_MASK 0x00000002
-#define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_DISABLE_STATUS_DISABLE_XPT_27_CLOCK_STATUS_SHIFT 1
-
-/* CLKGEN :: CORE_XPT_INST_CLOCK_DISABLE_STATUS :: DISABLE_XPT_20P25_CLOCK_STATUS [00:00] */
-#define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_DISABLE_STATUS_DISABLE_XPT_20P25_CLOCK_STATUS_MASK 0x00000001
-#define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_DISABLE_STATUS_DISABLE_XPT_20P25_CLOCK_STATUS_SHIFT 0
-
-/***************************************************************************
- *CORE_XPT_INST_CLOCK_ENABLE - Core xpt inst clock enable
- ***************************************************************************/
-/* CLKGEN :: CORE_XPT_INST_CLOCK_ENABLE :: reserved0 [31:05] */
-#define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_ENABLE_reserved0_MASK 0xffffffe0
-#define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_ENABLE_reserved0_SHIFT 5
-
-/* CLKGEN :: CORE_XPT_INST_CLOCK_ENABLE :: XPT_SCB_CLOCK_ENABLE [04:04] */
-#define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_ENABLE_XPT_SCB_CLOCK_ENABLE_MASK 0x00000010
-#define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_ENABLE_XPT_SCB_CLOCK_ENABLE_SHIFT 4
-#define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_ENABLE_XPT_SCB_CLOCK_ENABLE_DEFAULT 0x00000001
-
-/* CLKGEN :: CORE_XPT_INST_CLOCK_ENABLE :: XPT_GISB_CLOCK_ENABLE [03:03] */
-#define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_ENABLE_XPT_GISB_CLOCK_ENABLE_MASK 0x00000008
-#define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_ENABLE_XPT_GISB_CLOCK_ENABLE_SHIFT 3
-#define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_ENABLE_XPT_GISB_CLOCK_ENABLE_DEFAULT 0x00000001
-
-/* CLKGEN :: CORE_XPT_INST_CLOCK_ENABLE :: XPT_CORE_CLOCK_ENABLE [02:02] */
-#define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_ENABLE_XPT_CORE_CLOCK_ENABLE_MASK 0x00000004
-#define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_ENABLE_XPT_CORE_CLOCK_ENABLE_SHIFT 2
-#define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_ENABLE_XPT_CORE_CLOCK_ENABLE_DEFAULT 0x00000001
-
-/* CLKGEN :: CORE_XPT_INST_CLOCK_ENABLE :: XPT_54_CLOCK_ENABLE [01:01] */
-#define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_ENABLE_XPT_54_CLOCK_ENABLE_MASK 0x00000002
-#define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_ENABLE_XPT_54_CLOCK_ENABLE_SHIFT 1
-#define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_ENABLE_XPT_54_CLOCK_ENABLE_DEFAULT 0x00000001
-
-/* CLKGEN :: CORE_XPT_INST_CLOCK_ENABLE :: XPT_108_CLOCK_ENABLE [00:00] */
-#define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_ENABLE_XPT_108_CLOCK_ENABLE_MASK 0x00000001
-#define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_ENABLE_XPT_108_CLOCK_ENABLE_SHIFT 0
-#define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_ENABLE_XPT_108_CLOCK_ENABLE_DEFAULT 0x00000001
-
-/***************************************************************************
- *CORE_XPT_INST_CLOCK_ENABLE_STATUS - Clock Enable Status
- ***************************************************************************/
-/* CLKGEN :: CORE_XPT_INST_CLOCK_ENABLE_STATUS :: reserved0 [31:05] */
-#define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_ENABLE_STATUS_reserved0_MASK 0xffffffe0
-#define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_ENABLE_STATUS_reserved0_SHIFT 5
-
-/* CLKGEN :: CORE_XPT_INST_CLOCK_ENABLE_STATUS :: XPT_SCB_CLOCK_ENABLE_STATUS [04:04] */
-#define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_ENABLE_STATUS_XPT_SCB_CLOCK_ENABLE_STATUS_MASK 0x00000010
-#define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_ENABLE_STATUS_XPT_SCB_CLOCK_ENABLE_STATUS_SHIFT 4
-
-/* CLKGEN :: CORE_XPT_INST_CLOCK_ENABLE_STATUS :: XPT_GISB_CLOCK_ENABLE_STATUS [03:03] */
-#define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_ENABLE_STATUS_XPT_GISB_CLOCK_ENABLE_STATUS_MASK 0x00000008
-#define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_ENABLE_STATUS_XPT_GISB_CLOCK_ENABLE_STATUS_SHIFT 3
-
-/* CLKGEN :: CORE_XPT_INST_CLOCK_ENABLE_STATUS :: XPT_CORE_CLOCK_ENABLE_STATUS [02:02] */
-#define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_ENABLE_STATUS_XPT_CORE_CLOCK_ENABLE_STATUS_MASK 0x00000004
-#define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_ENABLE_STATUS_XPT_CORE_CLOCK_ENABLE_STATUS_SHIFT 2
-
-/* CLKGEN :: CORE_XPT_INST_CLOCK_ENABLE_STATUS :: XPT_54_CLOCK_ENABLE_STATUS [01:01] */
-#define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_ENABLE_STATUS_XPT_54_CLOCK_ENABLE_STATUS_MASK 0x00000002
-#define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_ENABLE_STATUS_XPT_54_CLOCK_ENABLE_STATUS_SHIFT 1
-
-/* CLKGEN :: CORE_XPT_INST_CLOCK_ENABLE_STATUS :: XPT_108_CLOCK_ENABLE_STATUS [00:00] */
-#define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_ENABLE_STATUS_XPT_108_CLOCK_ENABLE_STATUS_MASK 0x00000001
-#define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_ENABLE_STATUS_XPT_108_CLOCK_ENABLE_STATUS_SHIFT 0
-
-/***************************************************************************
- *CORE_XPT_INST_OBSERVE_CLOCK - Core xpt inst observe clock
- ***************************************************************************/
-/* CLKGEN :: CORE_XPT_INST_OBSERVE_CLOCK :: reserved0 [31:06] */
-#define BCHP_CLKGEN_CORE_XPT_INST_OBSERVE_CLOCK_reserved0_MASK 0xffffffc0
-#define BCHP_CLKGEN_CORE_XPT_INST_OBSERVE_CLOCK_reserved0_SHIFT 6
-
-/* CLKGEN :: CORE_XPT_INST_OBSERVE_CLOCK :: XPT_ENABLE_OBSERVE_CLOCK [05:05] */
-#define BCHP_CLKGEN_CORE_XPT_INST_OBSERVE_CLOCK_XPT_ENABLE_OBSERVE_CLOCK_MASK 0x00000020
-#define BCHP_CLKGEN_CORE_XPT_INST_OBSERVE_CLOCK_XPT_ENABLE_OBSERVE_CLOCK_SHIFT 5
-#define BCHP_CLKGEN_CORE_XPT_INST_OBSERVE_CLOCK_XPT_ENABLE_OBSERVE_CLOCK_DEFAULT 0x00000000
-
-/* CLKGEN :: CORE_XPT_INST_OBSERVE_CLOCK :: XPT_ENABLE_DIVIDER_OBSERVE_CLOCK [04:04] */
-#define BCHP_CLKGEN_CORE_XPT_INST_OBSERVE_CLOCK_XPT_ENABLE_DIVIDER_OBSERVE_CLOCK_MASK 0x00000010
-#define BCHP_CLKGEN_CORE_XPT_INST_OBSERVE_CLOCK_XPT_ENABLE_DIVIDER_OBSERVE_CLOCK_SHIFT 4
-#define BCHP_CLKGEN_CORE_XPT_INST_OBSERVE_CLOCK_XPT_ENABLE_DIVIDER_OBSERVE_CLOCK_DEFAULT 0x00000000
-
-/* CLKGEN :: CORE_XPT_INST_OBSERVE_CLOCK :: XPT_CONTROL_OBSERVE_CLOCK [03:00] */
-#define BCHP_CLKGEN_CORE_XPT_INST_OBSERVE_CLOCK_XPT_CONTROL_OBSERVE_CLOCK_MASK 0x0000000f
-#define BCHP_CLKGEN_CORE_XPT_INST_OBSERVE_CLOCK_XPT_CONTROL_OBSERVE_CLOCK_SHIFT 0
-#define BCHP_CLKGEN_CORE_XPT_INST_OBSERVE_CLOCK_XPT_CONTROL_OBSERVE_CLOCK_DEFAULT 0x00000000
-
-/***************************************************************************
- *DISABLE_AVS_TOP_DURING_S2 - Disable AVS_TOP 54MHz clocks during S2 standby.
- ***************************************************************************/
-/* CLKGEN :: DISABLE_AVS_TOP_DURING_S2 :: reserved0 [31:01] */
-#define BCHP_CLKGEN_DISABLE_AVS_TOP_DURING_S2_reserved0_MASK 0xfffffffe
-#define BCHP_CLKGEN_DISABLE_AVS_TOP_DURING_S2_reserved0_SHIFT 1
-
-/* CLKGEN :: DISABLE_AVS_TOP_DURING_S2 :: DISABLE_AVS_TOP [00:00] */
-#define BCHP_CLKGEN_DISABLE_AVS_TOP_DURING_S2_DISABLE_AVS_TOP_MASK 0x00000001
-#define BCHP_CLKGEN_DISABLE_AVS_TOP_DURING_S2_DISABLE_AVS_TOP_SHIFT 0
-#define BCHP_CLKGEN_DISABLE_AVS_TOP_DURING_S2_DISABLE_AVS_TOP_DEFAULT 0x00000000
-
-/***************************************************************************
- *DISABLE_AVS_TOP_DURING_S2_SECURE - Secure AVS_TOP clock disable. Set at start-up to guarantee AVS_TOP is clock gated in S2 standby.
- ***************************************************************************/
-/* CLKGEN :: DISABLE_AVS_TOP_DURING_S2_SECURE :: reserved0 [31:01] */
-#define BCHP_CLKGEN_DISABLE_AVS_TOP_DURING_S2_SECURE_reserved0_MASK 0xfffffffe
-#define BCHP_CLKGEN_DISABLE_AVS_TOP_DURING_S2_SECURE_reserved0_SHIFT 1
-
-/* CLKGEN :: DISABLE_AVS_TOP_DURING_S2_SECURE :: DISABLE_AVS_TOP_SECURE [00:00] */
-#define BCHP_CLKGEN_DISABLE_AVS_TOP_DURING_S2_SECURE_DISABLE_AVS_TOP_SECURE_MASK 0x00000001
-#define BCHP_CLKGEN_DISABLE_AVS_TOP_DURING_S2_SECURE_DISABLE_AVS_TOP_SECURE_SHIFT 0
-#define BCHP_CLKGEN_DISABLE_AVS_TOP_DURING_S2_SECURE_DISABLE_AVS_TOP_SECURE_DEFAULT 0x00000000
-
-/***************************************************************************
- *DUALSDS_0_INST_CLOCK_DISABLE - Disable DUALSDS_0_INST's clocks
- ***************************************************************************/
-/* CLKGEN :: DUALSDS_0_INST_CLOCK_DISABLE :: reserved0 [31:02] */
-#define BCHP_CLKGEN_DUALSDS_0_INST_CLOCK_DISABLE_reserved0_MASK 0xfffffffc
-#define BCHP_CLKGEN_DUALSDS_0_INST_CLOCK_DISABLE_reserved0_SHIFT 2
-
-/* CLKGEN :: DUALSDS_0_INST_CLOCK_DISABLE :: DISABLE_SDS0RCVR1_108_PRESPMBALANCE_CLOCK [01:01] */
-#define BCHP_CLKGEN_DUALSDS_0_INST_CLOCK_DISABLE_DISABLE_SDS0RCVR1_108_PRESPMBALANCE_CLOCK_MASK 0x00000002
-#define BCHP_CLKGEN_DUALSDS_0_INST_CLOCK_DISABLE_DISABLE_SDS0RCVR1_108_PRESPMBALANCE_CLOCK_SHIFT 1
-#define BCHP_CLKGEN_DUALSDS_0_INST_CLOCK_DISABLE_DISABLE_SDS0RCVR1_108_PRESPMBALANCE_CLOCK_DEFAULT 0x00000000
-
-/* CLKGEN :: DUALSDS_0_INST_CLOCK_DISABLE :: DISABLE_SDS0RCVR0_108_PRESPMBALANCE_CLOCK [00:00] */
-#define BCHP_CLKGEN_DUALSDS_0_INST_CLOCK_DISABLE_DISABLE_SDS0RCVR0_108_PRESPMBALANCE_CLOCK_MASK 0x00000001
-#define BCHP_CLKGEN_DUALSDS_0_INST_CLOCK_DISABLE_DISABLE_SDS0RCVR0_108_PRESPMBALANCE_CLOCK_SHIFT 0
-#define BCHP_CLKGEN_DUALSDS_0_INST_CLOCK_DISABLE_DISABLE_SDS0RCVR0_108_PRESPMBALANCE_CLOCK_DEFAULT 0x00000000
-
-/***************************************************************************
- *DUALSDS_0_INST_CLOCK_DISABLE_STATUS - Clock Disable Status
- ***************************************************************************/
-/* CLKGEN :: DUALSDS_0_INST_CLOCK_DISABLE_STATUS :: reserved0 [31:02] */
-#define BCHP_CLKGEN_DUALSDS_0_INST_CLOCK_DISABLE_STATUS_reserved0_MASK 0xfffffffc
-#define BCHP_CLKGEN_DUALSDS_0_INST_CLOCK_DISABLE_STATUS_reserved0_SHIFT 2
-
-/* CLKGEN :: DUALSDS_0_INST_CLOCK_DISABLE_STATUS :: DISABLE_SDS0RCVR1_108_PRESPMBALANCE_CLOCK_STATUS [01:01] */
-#define BCHP_CLKGEN_DUALSDS_0_INST_CLOCK_DISABLE_STATUS_DISABLE_SDS0RCVR1_108_PRESPMBALANCE_CLOCK_STATUS_MASK 0x00000002
-#define BCHP_CLKGEN_DUALSDS_0_INST_CLOCK_DISABLE_STATUS_DISABLE_SDS0RCVR1_108_PRESPMBALANCE_CLOCK_STATUS_SHIFT 1
-
-/* CLKGEN :: DUALSDS_0_INST_CLOCK_DISABLE_STATUS :: DISABLE_SDS0RCVR0_108_PRESPMBALANCE_CLOCK_STATUS [00:00] */
-#define BCHP_CLKGEN_DUALSDS_0_INST_CLOCK_DISABLE_STATUS_DISABLE_SDS0RCVR0_108_PRESPMBALANCE_CLOCK_STATUS_MASK 0x00000001
-#define BCHP_CLKGEN_DUALSDS_0_INST_CLOCK_DISABLE_STATUS_DISABLE_SDS0RCVR0_108_PRESPMBALANCE_CLOCK_STATUS_SHIFT 0
-
-/***************************************************************************
- *DUALSDS_0_INST_CLOCK_ENABLE_CH0 - Dualsds 0 inst clock enable ch0
- ***************************************************************************/
-/* CLKGEN :: DUALSDS_0_INST_CLOCK_ENABLE_CH0 :: reserved0 [31:02] */
-#define BCHP_CLKGEN_DUALSDS_0_INST_CLOCK_ENABLE_CH0_reserved0_MASK 0xfffffffc
-#define BCHP_CLKGEN_DUALSDS_0_INST_CLOCK_ENABLE_CH0_reserved0_SHIFT 2
-
-/* CLKGEN :: DUALSDS_0_INST_CLOCK_ENABLE_CH0 :: SDS0_54_CLOCK_ENABLE_CH0 [01:01] */
-#define BCHP_CLKGEN_DUALSDS_0_INST_CLOCK_ENABLE_CH0_SDS0_54_CLOCK_ENABLE_CH0_MASK 0x00000002
-#define BCHP_CLKGEN_DUALSDS_0_INST_CLOCK_ENABLE_CH0_SDS0_54_CLOCK_ENABLE_CH0_SHIFT 1
-#define BCHP_CLKGEN_DUALSDS_0_INST_CLOCK_ENABLE_CH0_SDS0_54_CLOCK_ENABLE_CH0_DEFAULT 0x00000001
-
-/* CLKGEN :: DUALSDS_0_INST_CLOCK_ENABLE_CH0 :: SDS0_108_CLOCK_ENABLE_CH0 [00:00] */
-#define BCHP_CLKGEN_DUALSDS_0_INST_CLOCK_ENABLE_CH0_SDS0_108_CLOCK_ENABLE_CH0_MASK 0x00000001
-#define BCHP_CLKGEN_DUALSDS_0_INST_CLOCK_ENABLE_CH0_SDS0_108_CLOCK_ENABLE_CH0_SHIFT 0
-#define BCHP_CLKGEN_DUALSDS_0_INST_CLOCK_ENABLE_CH0_SDS0_108_CLOCK_ENABLE_CH0_DEFAULT 0x00000001
-
-/***************************************************************************
- *DUALSDS_0_INST_CLOCK_ENABLE_CH0_STATUS - Clock Enable Status
- ***************************************************************************/
-/* CLKGEN :: DUALSDS_0_INST_CLOCK_ENABLE_CH0_STATUS :: reserved0 [31:02] */
-#define BCHP_CLKGEN_DUALSDS_0_INST_CLOCK_ENABLE_CH0_STATUS_reserved0_MASK 0xfffffffc
-#define BCHP_CLKGEN_DUALSDS_0_INST_CLOCK_ENABLE_CH0_STATUS_reserved0_SHIFT 2
-
-/* CLKGEN :: DUALSDS_0_INST_CLOCK_ENABLE_CH0_STATUS :: SDS0_54_CLOCK_ENABLE_CH0_STATUS [01:01] */
-#define BCHP_CLKGEN_DUALSDS_0_INST_CLOCK_ENABLE_CH0_STATUS_SDS0_54_CLOCK_ENABLE_CH0_STATUS_MASK 0x00000002
-#define BCHP_CLKGEN_DUALSDS_0_INST_CLOCK_ENABLE_CH0_STATUS_SDS0_54_CLOCK_ENABLE_CH0_STATUS_SHIFT 1
-
-/* CLKGEN :: DUALSDS_0_INST_CLOCK_ENABLE_CH0_STATUS :: SDS0_108_CLOCK_ENABLE_CH0_STATUS [00:00] */
-#define BCHP_CLKGEN_DUALSDS_0_INST_CLOCK_ENABLE_CH0_STATUS_SDS0_108_CLOCK_ENABLE_CH0_STATUS_MASK 0x00000001
-#define BCHP_CLKGEN_DUALSDS_0_INST_CLOCK_ENABLE_CH0_STATUS_SDS0_108_CLOCK_ENABLE_CH0_STATUS_SHIFT 0
-
-/***************************************************************************
- *DUALSDS_0_INST_CLOCK_ENABLE_CH1 - Dualsds 0 inst clock enable ch1
- ***************************************************************************/
-/* CLKGEN :: DUALSDS_0_INST_CLOCK_ENABLE_CH1 :: reserved0 [31:02] */
-#define BCHP_CLKGEN_DUALSDS_0_INST_CLOCK_ENABLE_CH1_reserved0_MASK 0xfffffffc
-#define BCHP_CLKGEN_DUALSDS_0_INST_CLOCK_ENABLE_CH1_reserved0_SHIFT 2
-
-/* CLKGEN :: DUALSDS_0_INST_CLOCK_ENABLE_CH1 :: SDS0_54_CLOCK_ENABLE_CH1 [01:01] */
-#define BCHP_CLKGEN_DUALSDS_0_INST_CLOCK_ENABLE_CH1_SDS0_54_CLOCK_ENABLE_CH1_MASK 0x00000002
-#define BCHP_CLKGEN_DUALSDS_0_INST_CLOCK_ENABLE_CH1_SDS0_54_CLOCK_ENABLE_CH1_SHIFT 1
-#define BCHP_CLKGEN_DUALSDS_0_INST_CLOCK_ENABLE_CH1_SDS0_54_CLOCK_ENABLE_CH1_DEFAULT 0x00000001
-
-/* CLKGEN :: DUALSDS_0_INST_CLOCK_ENABLE_CH1 :: SDS0_108_CLOCK_ENABLE_CH1 [00:00] */
-#define BCHP_CLKGEN_DUALSDS_0_INST_CLOCK_ENABLE_CH1_SDS0_108_CLOCK_ENABLE_CH1_MASK 0x00000001
-#define BCHP_CLKGEN_DUALSDS_0_INST_CLOCK_ENABLE_CH1_SDS0_108_CLOCK_ENABLE_CH1_SHIFT 0
-#define BCHP_CLKGEN_DUALSDS_0_INST_CLOCK_ENABLE_CH1_SDS0_108_CLOCK_ENABLE_CH1_DEFAULT 0x00000001
-
-/***************************************************************************
- *DUALSDS_0_INST_CLOCK_ENABLE_CH1_STATUS - Clock Enable Status
- ***************************************************************************/
-/* CLKGEN :: DUALSDS_0_INST_CLOCK_ENABLE_CH1_STATUS :: reserved0 [31:02] */
-#define BCHP_CLKGEN_DUALSDS_0_INST_CLOCK_ENABLE_CH1_STATUS_reserved0_MASK 0xfffffffc
-#define BCHP_CLKGEN_DUALSDS_0_INST_CLOCK_ENABLE_CH1_STATUS_reserved0_SHIFT 2
-
-/* CLKGEN :: DUALSDS_0_INST_CLOCK_ENABLE_CH1_STATUS :: SDS0_54_CLOCK_ENABLE_CH1_STATUS [01:01] */
-#define BCHP_CLKGEN_DUALSDS_0_INST_CLOCK_ENABLE_CH1_STATUS_SDS0_54_CLOCK_ENABLE_CH1_STATUS_MASK 0x00000002
-#define BCHP_CLKGEN_DUALSDS_0_INST_CLOCK_ENABLE_CH1_STATUS_SDS0_54_CLOCK_ENABLE_CH1_STATUS_SHIFT 1
-
-/* CLKGEN :: DUALSDS_0_INST_CLOCK_ENABLE_CH1_STATUS :: SDS0_108_CLOCK_ENABLE_CH1_STATUS [00:00] */
-#define BCHP_CLKGEN_DUALSDS_0_INST_CLOCK_ENABLE_CH1_STATUS_SDS0_108_CLOCK_ENABLE_CH1_STATUS_MASK 0x00000001
-#define BCHP_CLKGEN_DUALSDS_0_INST_CLOCK_ENABLE_CH1_STATUS_SDS0_108_CLOCK_ENABLE_CH1_STATUS_SHIFT 0
-
-/***************************************************************************
- *DUALSDS_0_INST_EN_CH0 - Dualsds 0 inst en ch0
- ***************************************************************************/
-/* CLKGEN :: DUALSDS_0_INST_EN_CH0 :: reserved0 [31:01] */
-#define BCHP_CLKGEN_DUALSDS_0_INST_EN_CH0_reserved0_MASK 0xfffffffe
-#define BCHP_CLKGEN_DUALSDS_0_INST_EN_CH0_reserved0_SHIFT 1
-
-/* CLKGEN :: DUALSDS_0_INST_EN_CH0 :: SDS0_PLL_CLOCK_EN_CH0 [00:00] */
-#define BCHP_CLKGEN_DUALSDS_0_INST_EN_CH0_SDS0_PLL_CLOCK_EN_CH0_MASK 0x00000001
-#define BCHP_CLKGEN_DUALSDS_0_INST_EN_CH0_SDS0_PLL_CLOCK_EN_CH0_SHIFT 0
-#define BCHP_CLKGEN_DUALSDS_0_INST_EN_CH0_SDS0_PLL_CLOCK_EN_CH0_DEFAULT 0x00000001
-
-/***************************************************************************
- *DUALSDS_0_INST_EN_CH1 - Dualsds 0 inst en ch1
- ***************************************************************************/
-/* CLKGEN :: DUALSDS_0_INST_EN_CH1 :: reserved0 [31:01] */
-#define BCHP_CLKGEN_DUALSDS_0_INST_EN_CH1_reserved0_MASK 0xfffffffe
-#define BCHP_CLKGEN_DUALSDS_0_INST_EN_CH1_reserved0_SHIFT 1
-
-/* CLKGEN :: DUALSDS_0_INST_EN_CH1 :: SDS0_PLL_CLOCK_EN_CH1 [00:00] */
-#define BCHP_CLKGEN_DUALSDS_0_INST_EN_CH1_SDS0_PLL_CLOCK_EN_CH1_MASK 0x00000001
-#define BCHP_CLKGEN_DUALSDS_0_INST_EN_CH1_SDS0_PLL_CLOCK_EN_CH1_SHIFT 0
-#define BCHP_CLKGEN_DUALSDS_0_INST_EN_CH1_SDS0_PLL_CLOCK_EN_CH1_DEFAULT 0x00000001
-
-/***************************************************************************
- *DUALSDS_0_INST_OBSERVE_CLOCK - Dualsds 0 inst observe clock
- ***************************************************************************/
-/* CLKGEN :: DUALSDS_0_INST_OBSERVE_CLOCK :: reserved0 [31:24] */
-#define BCHP_CLKGEN_DUALSDS_0_INST_OBSERVE_CLOCK_reserved0_MASK 0xff000000
-#define BCHP_CLKGEN_DUALSDS_0_INST_OBSERVE_CLOCK_reserved0_SHIFT 24
-
-/* CLKGEN :: DUALSDS_0_INST_OBSERVE_CLOCK :: SDS0TFEC1_ENABLE_OBSERVE_CLOCK [23:23] */
-#define BCHP_CLKGEN_DUALSDS_0_INST_OBSERVE_CLOCK_SDS0TFEC1_ENABLE_OBSERVE_CLOCK_MASK 0x00800000
-#define BCHP_CLKGEN_DUALSDS_0_INST_OBSERVE_CLOCK_SDS0TFEC1_ENABLE_OBSERVE_CLOCK_SHIFT 23
-#define BCHP_CLKGEN_DUALSDS_0_INST_OBSERVE_CLOCK_SDS0TFEC1_ENABLE_OBSERVE_CLOCK_DEFAULT 0x00000000
-
-/* CLKGEN :: DUALSDS_0_INST_OBSERVE_CLOCK :: SDS0TFEC1_ENABLE_DIVIDER_OBSERVE_CLOCK [22:22] */
-#define BCHP_CLKGEN_DUALSDS_0_INST_OBSERVE_CLOCK_SDS0TFEC1_ENABLE_DIVIDER_OBSERVE_CLOCK_MASK 0x00400000
-#define BCHP_CLKGEN_DUALSDS_0_INST_OBSERVE_CLOCK_SDS0TFEC1_ENABLE_DIVIDER_OBSERVE_CLOCK_SHIFT 22
-#define BCHP_CLKGEN_DUALSDS_0_INST_OBSERVE_CLOCK_SDS0TFEC1_ENABLE_DIVIDER_OBSERVE_CLOCK_DEFAULT 0x00000000
-
-/* CLKGEN :: DUALSDS_0_INST_OBSERVE_CLOCK :: SDS0TFEC1_CONTROL_OBSERVE_CLOCK [21:18] */
-#define BCHP_CLKGEN_DUALSDS_0_INST_OBSERVE_CLOCK_SDS0TFEC1_CONTROL_OBSERVE_CLOCK_MASK 0x003c0000
-#define BCHP_CLKGEN_DUALSDS_0_INST_OBSERVE_CLOCK_SDS0TFEC1_CONTROL_OBSERVE_CLOCK_SHIFT 18
-#define BCHP_CLKGEN_DUALSDS_0_INST_OBSERVE_CLOCK_SDS0TFEC1_CONTROL_OBSERVE_CLOCK_DEFAULT 0x00000000
-
-/* CLKGEN :: DUALSDS_0_INST_OBSERVE_CLOCK :: SDS0TFEC0_ENABLE_OBSERVE_CLOCK [17:17] */
-#define BCHP_CLKGEN_DUALSDS_0_INST_OBSERVE_CLOCK_SDS0TFEC0_ENABLE_OBSERVE_CLOCK_MASK 0x00020000
-#define BCHP_CLKGEN_DUALSDS_0_INST_OBSERVE_CLOCK_SDS0TFEC0_ENABLE_OBSERVE_CLOCK_SHIFT 17
-#define BCHP_CLKGEN_DUALSDS_0_INST_OBSERVE_CLOCK_SDS0TFEC0_ENABLE_OBSERVE_CLOCK_DEFAULT 0x00000000
-
-/* CLKGEN :: DUALSDS_0_INST_OBSERVE_CLOCK :: SDS0TFEC0_ENABLE_DIVIDER_OBSERVE_CLOCK [16:16] */
-#define BCHP_CLKGEN_DUALSDS_0_INST_OBSERVE_CLOCK_SDS0TFEC0_ENABLE_DIVIDER_OBSERVE_CLOCK_MASK 0x00010000
-#define BCHP_CLKGEN_DUALSDS_0_INST_OBSERVE_CLOCK_SDS0TFEC0_ENABLE_DIVIDER_OBSERVE_CLOCK_SHIFT 16
-#define BCHP_CLKGEN_DUALSDS_0_INST_OBSERVE_CLOCK_SDS0TFEC0_ENABLE_DIVIDER_OBSERVE_CLOCK_DEFAULT 0x00000000
-
-/* CLKGEN :: DUALSDS_0_INST_OBSERVE_CLOCK :: SDS0TFEC0_CONTROL_OBSERVE_CLOCK [15:12] */
-#define BCHP_CLKGEN_DUALSDS_0_INST_OBSERVE_CLOCK_SDS0TFEC0_CONTROL_OBSERVE_CLOCK_MASK 0x0000f000
-#define BCHP_CLKGEN_DUALSDS_0_INST_OBSERVE_CLOCK_SDS0TFEC0_CONTROL_OBSERVE_CLOCK_SHIFT 12
-#define BCHP_CLKGEN_DUALSDS_0_INST_OBSERVE_CLOCK_SDS0TFEC0_CONTROL_OBSERVE_CLOCK_DEFAULT 0x00000000
-
-/* CLKGEN :: DUALSDS_0_INST_OBSERVE_CLOCK :: SDS0RCVR1_ENABLE_OBSERVE_CLOCK [11:11] */
-#define BCHP_CLKGEN_DUALSDS_0_INST_OBSERVE_CLOCK_SDS0RCVR1_ENABLE_OBSERVE_CLOCK_MASK 0x00000800
-#define BCHP_CLKGEN_DUALSDS_0_INST_OBSERVE_CLOCK_SDS0RCVR1_ENABLE_OBSERVE_CLOCK_SHIFT 11
-#define BCHP_CLKGEN_DUALSDS_0_INST_OBSERVE_CLOCK_SDS0RCVR1_ENABLE_OBSERVE_CLOCK_DEFAULT 0x00000000
-
-/* CLKGEN :: DUALSDS_0_INST_OBSERVE_CLOCK :: SDS0RCVR1_ENABLE_DIVIDER_OBSERVE_CLOCK [10:10] */
-#define BCHP_CLKGEN_DUALSDS_0_INST_OBSERVE_CLOCK_SDS0RCVR1_ENABLE_DIVIDER_OBSERVE_CLOCK_MASK 0x00000400
-#define BCHP_CLKGEN_DUALSDS_0_INST_OBSERVE_CLOCK_SDS0RCVR1_ENABLE_DIVIDER_OBSERVE_CLOCK_SHIFT 10
-#define BCHP_CLKGEN_DUALSDS_0_INST_OBSERVE_CLOCK_SDS0RCVR1_ENABLE_DIVIDER_OBSERVE_CLOCK_DEFAULT 0x00000000
-
-/* CLKGEN :: DUALSDS_0_INST_OBSERVE_CLOCK :: SDS0RCVR1_CONTROL_OBSERVE_CLOCK [09:06] */
-#define BCHP_CLKGEN_DUALSDS_0_INST_OBSERVE_CLOCK_SDS0RCVR1_CONTROL_OBSERVE_CLOCK_MASK 0x000003c0
-#define BCHP_CLKGEN_DUALSDS_0_INST_OBSERVE_CLOCK_SDS0RCVR1_CONTROL_OBSERVE_CLOCK_SHIFT 6
-#define BCHP_CLKGEN_DUALSDS_0_INST_OBSERVE_CLOCK_SDS0RCVR1_CONTROL_OBSERVE_CLOCK_DEFAULT 0x00000000
-
-/* CLKGEN :: DUALSDS_0_INST_OBSERVE_CLOCK :: SDS0RCVR0_ENABLE_OBSERVE_CLOCK [05:05] */
-#define BCHP_CLKGEN_DUALSDS_0_INST_OBSERVE_CLOCK_SDS0RCVR0_ENABLE_OBSERVE_CLOCK_MASK 0x00000020
-#define BCHP_CLKGEN_DUALSDS_0_INST_OBSERVE_CLOCK_SDS0RCVR0_ENABLE_OBSERVE_CLOCK_SHIFT 5
-#define BCHP_CLKGEN_DUALSDS_0_INST_OBSERVE_CLOCK_SDS0RCVR0_ENABLE_OBSERVE_CLOCK_DEFAULT 0x00000000
-
-/* CLKGEN :: DUALSDS_0_INST_OBSERVE_CLOCK :: SDS0RCVR0_ENABLE_DIVIDER_OBSERVE_CLOCK [04:04] */
-#define BCHP_CLKGEN_DUALSDS_0_INST_OBSERVE_CLOCK_SDS0RCVR0_ENABLE_DIVIDER_OBSERVE_CLOCK_MASK 0x00000010
-#define BCHP_CLKGEN_DUALSDS_0_INST_OBSERVE_CLOCK_SDS0RCVR0_ENABLE_DIVIDER_OBSERVE_CLOCK_SHIFT 4
-#define BCHP_CLKGEN_DUALSDS_0_INST_OBSERVE_CLOCK_SDS0RCVR0_ENABLE_DIVIDER_OBSERVE_CLOCK_DEFAULT 0x00000000
-
-/* CLKGEN :: DUALSDS_0_INST_OBSERVE_CLOCK :: SDS0RCVR0_CONTROL_OBSERVE_CLOCK [03:00] */
-#define BCHP_CLKGEN_DUALSDS_0_INST_OBSERVE_CLOCK_SDS0RCVR0_CONTROL_OBSERVE_CLOCK_MASK 0x0000000f
-#define BCHP_CLKGEN_DUALSDS_0_INST_OBSERVE_CLOCK_SDS0RCVR0_CONTROL_OBSERVE_CLOCK_SHIFT 0
-#define BCHP_CLKGEN_DUALSDS_0_INST_OBSERVE_CLOCK_SDS0RCVR0_CONTROL_OBSERVE_CLOCK_DEFAULT 0x00000000
-
-/***************************************************************************
- *DUALSDS_0_INST_PLL_CLOCK_EN - Dualsds 0 inst pll clock en
- ***************************************************************************/
-/* CLKGEN :: DUALSDS_0_INST_PLL_CLOCK_EN :: reserved0 [31:02] */
-#define BCHP_CLKGEN_DUALSDS_0_INST_PLL_CLOCK_EN_reserved0_MASK 0xfffffffc
-#define BCHP_CLKGEN_DUALSDS_0_INST_PLL_CLOCK_EN_reserved0_SHIFT 2
-
-/* CLKGEN :: DUALSDS_0_INST_PLL_CLOCK_EN :: SDS0TFEC1_PLL_CLOCK_EN [01:01] */
-#define BCHP_CLKGEN_DUALSDS_0_INST_PLL_CLOCK_EN_SDS0TFEC1_PLL_CLOCK_EN_MASK 0x00000002
-#define BCHP_CLKGEN_DUALSDS_0_INST_PLL_CLOCK_EN_SDS0TFEC1_PLL_CLOCK_EN_SHIFT 1
-#define BCHP_CLKGEN_DUALSDS_0_INST_PLL_CLOCK_EN_SDS0TFEC1_PLL_CLOCK_EN_DEFAULT 0x00000001
-
-/* CLKGEN :: DUALSDS_0_INST_PLL_CLOCK_EN :: SDS0TFEC0_PLL_CLOCK_EN [00:00] */
-#define BCHP_CLKGEN_DUALSDS_0_INST_PLL_CLOCK_EN_SDS0TFEC0_PLL_CLOCK_EN_MASK 0x00000001
-#define BCHP_CLKGEN_DUALSDS_0_INST_PLL_CLOCK_EN_SDS0TFEC0_PLL_CLOCK_EN_SHIFT 0
-#define BCHP_CLKGEN_DUALSDS_0_INST_PLL_CLOCK_EN_SDS0TFEC0_PLL_CLOCK_EN_DEFAULT 0x00000001
-
-/***************************************************************************
- *DUALSDS_0_INST_SEL - Dualsds 0 inst sel
- ***************************************************************************/
-/* CLKGEN :: DUALSDS_0_INST_SEL :: reserved0 [31:02] */
-#define BCHP_CLKGEN_DUALSDS_0_INST_SEL_reserved0_MASK 0xfffffffc
-#define BCHP_CLKGEN_DUALSDS_0_INST_SEL_reserved0_SHIFT 2
-
-/* CLKGEN :: DUALSDS_0_INST_SEL :: SDS0_LV_CLK_PLL_SRC_SEL [01:01] */
-#define BCHP_CLKGEN_DUALSDS_0_INST_SEL_SDS0_LV_CLK_PLL_SRC_SEL_MASK 0x00000002
-#define BCHP_CLKGEN_DUALSDS_0_INST_SEL_SDS0_LV_CLK_PLL_SRC_SEL_SHIFT 1
-#define BCHP_CLKGEN_DUALSDS_0_INST_SEL_SDS0_LV_CLK_PLL_SRC_SEL_DEFAULT 0x00000000
-
-/* CLKGEN :: DUALSDS_0_INST_SEL :: SDS0_CHAN_I_CLK_240_LV_CLK_PLL_SRC_SEL [00:00] */
-#define BCHP_CLKGEN_DUALSDS_0_INST_SEL_SDS0_CHAN_I_CLK_240_LV_CLK_PLL_SRC_SEL_MASK 0x00000001
-#define BCHP_CLKGEN_DUALSDS_0_INST_SEL_SDS0_CHAN_I_CLK_240_LV_CLK_PLL_SRC_SEL_SHIFT 0
-#define BCHP_CLKGEN_DUALSDS_0_INST_SEL_SDS0_CHAN_I_CLK_240_LV_CLK_PLL_SRC_SEL_DEFAULT 0x00000000
-
-/***************************************************************************
- *DUALSDS_1_INST_CLOCK_DISABLE - Disable DUALSDS_1_INST's clocks
- ***************************************************************************/
-/* CLKGEN :: DUALSDS_1_INST_CLOCK_DISABLE :: reserved0 [31:02] */
-#define BCHP_CLKGEN_DUALSDS_1_INST_CLOCK_DISABLE_reserved0_MASK 0xfffffffc
-#define BCHP_CLKGEN_DUALSDS_1_INST_CLOCK_DISABLE_reserved0_SHIFT 2
-
-/* CLKGEN :: DUALSDS_1_INST_CLOCK_DISABLE :: DISABLE_SDS1RCVR1_108_PRESPMBALANCE_CLOCK [01:01] */
-#define BCHP_CLKGEN_DUALSDS_1_INST_CLOCK_DISABLE_DISABLE_SDS1RCVR1_108_PRESPMBALANCE_CLOCK_MASK 0x00000002
-#define BCHP_CLKGEN_DUALSDS_1_INST_CLOCK_DISABLE_DISABLE_SDS1RCVR1_108_PRESPMBALANCE_CLOCK_SHIFT 1
-#define BCHP_CLKGEN_DUALSDS_1_INST_CLOCK_DISABLE_DISABLE_SDS1RCVR1_108_PRESPMBALANCE_CLOCK_DEFAULT 0x00000000
-
-/* CLKGEN :: DUALSDS_1_INST_CLOCK_DISABLE :: DISABLE_SDS1RCVR0_108_PRESPMBALANCE_CLOCK [00:00] */
-#define BCHP_CLKGEN_DUALSDS_1_INST_CLOCK_DISABLE_DISABLE_SDS1RCVR0_108_PRESPMBALANCE_CLOCK_MASK 0x00000001
-#define BCHP_CLKGEN_DUALSDS_1_INST_CLOCK_DISABLE_DISABLE_SDS1RCVR0_108_PRESPMBALANCE_CLOCK_SHIFT 0
-#define BCHP_CLKGEN_DUALSDS_1_INST_CLOCK_DISABLE_DISABLE_SDS1RCVR0_108_PRESPMBALANCE_CLOCK_DEFAULT 0x00000000
-
-/***************************************************************************
- *DUALSDS_1_INST_CLOCK_DISABLE_STATUS - Clock Disable Status
- ***************************************************************************/
-/* CLKGEN :: DUALSDS_1_INST_CLOCK_DISABLE_STATUS :: reserved0 [31:02] */
-#define BCHP_CLKGEN_DUALSDS_1_INST_CLOCK_DISABLE_STATUS_reserved0_MASK 0xfffffffc
-#define BCHP_CLKGEN_DUALSDS_1_INST_CLOCK_DISABLE_STATUS_reserved0_SHIFT 2
-
-/* CLKGEN :: DUALSDS_1_INST_CLOCK_DISABLE_STATUS :: DISABLE_SDS1RCVR1_108_PRESPMBALANCE_CLOCK_STATUS [01:01] */
-#define BCHP_CLKGEN_DUALSDS_1_INST_CLOCK_DISABLE_STATUS_DISABLE_SDS1RCVR1_108_PRESPMBALANCE_CLOCK_STATUS_MASK 0x00000002
-#define BCHP_CLKGEN_DUALSDS_1_INST_CLOCK_DISABLE_STATUS_DISABLE_SDS1RCVR1_108_PRESPMBALANCE_CLOCK_STATUS_SHIFT 1
-
-/* CLKGEN :: DUALSDS_1_INST_CLOCK_DISABLE_STATUS :: DISABLE_SDS1RCVR0_108_PRESPMBALANCE_CLOCK_STATUS [00:00] */
-#define BCHP_CLKGEN_DUALSDS_1_INST_CLOCK_DISABLE_STATUS_DISABLE_SDS1RCVR0_108_PRESPMBALANCE_CLOCK_STATUS_MASK 0x00000001
-#define BCHP_CLKGEN_DUALSDS_1_INST_CLOCK_DISABLE_STATUS_DISABLE_SDS1RCVR0_108_PRESPMBALANCE_CLOCK_STATUS_SHIFT 0
-
-/***************************************************************************
- *DUALSDS_1_INST_CLOCK_ENABLE_CH0 - Dualsds 1 inst clock enable ch0
- ***************************************************************************/
-/* CLKGEN :: DUALSDS_1_INST_CLOCK_ENABLE_CH0 :: reserved0 [31:02] */
-#define BCHP_CLKGEN_DUALSDS_1_INST_CLOCK_ENABLE_CH0_reserved0_MASK 0xfffffffc
-#define BCHP_CLKGEN_DUALSDS_1_INST_CLOCK_ENABLE_CH0_reserved0_SHIFT 2
-
-/* CLKGEN :: DUALSDS_1_INST_CLOCK_ENABLE_CH0 :: SDS1_54_CLOCK_ENABLE_CH0 [01:01] */
-#define BCHP_CLKGEN_DUALSDS_1_INST_CLOCK_ENABLE_CH0_SDS1_54_CLOCK_ENABLE_CH0_MASK 0x00000002
-#define BCHP_CLKGEN_DUALSDS_1_INST_CLOCK_ENABLE_CH0_SDS1_54_CLOCK_ENABLE_CH0_SHIFT 1
-#define BCHP_CLKGEN_DUALSDS_1_INST_CLOCK_ENABLE_CH0_SDS1_54_CLOCK_ENABLE_CH0_DEFAULT 0x00000001
-
-/* CLKGEN :: DUALSDS_1_INST_CLOCK_ENABLE_CH0 :: SDS1_108_CLOCK_ENABLE_CH0 [00:00] */
-#define BCHP_CLKGEN_DUALSDS_1_INST_CLOCK_ENABLE_CH0_SDS1_108_CLOCK_ENABLE_CH0_MASK 0x00000001
-#define BCHP_CLKGEN_DUALSDS_1_INST_CLOCK_ENABLE_CH0_SDS1_108_CLOCK_ENABLE_CH0_SHIFT 0
-#define BCHP_CLKGEN_DUALSDS_1_INST_CLOCK_ENABLE_CH0_SDS1_108_CLOCK_ENABLE_CH0_DEFAULT 0x00000001
-
-/***************************************************************************
- *DUALSDS_1_INST_CLOCK_ENABLE_CH0_STATUS - Clock Enable Status
- ***************************************************************************/
-/* CLKGEN :: DUALSDS_1_INST_CLOCK_ENABLE_CH0_STATUS :: reserved0 [31:02] */
-#define BCHP_CLKGEN_DUALSDS_1_INST_CLOCK_ENABLE_CH0_STATUS_reserved0_MASK 0xfffffffc
-#define BCHP_CLKGEN_DUALSDS_1_INST_CLOCK_ENABLE_CH0_STATUS_reserved0_SHIFT 2
-
-/* CLKGEN :: DUALSDS_1_INST_CLOCK_ENABLE_CH0_STATUS :: SDS1_54_CLOCK_ENABLE_CH0_STATUS [01:01] */
-#define BCHP_CLKGEN_DUALSDS_1_INST_CLOCK_ENABLE_CH0_STATUS_SDS1_54_CLOCK_ENABLE_CH0_STATUS_MASK 0x00000002
-#define BCHP_CLKGEN_DUALSDS_1_INST_CLOCK_ENABLE_CH0_STATUS_SDS1_54_CLOCK_ENABLE_CH0_STATUS_SHIFT 1
-
-/* CLKGEN :: DUALSDS_1_INST_CLOCK_ENABLE_CH0_STATUS :: SDS1_108_CLOCK_ENABLE_CH0_STATUS [00:00] */
-#define BCHP_CLKGEN_DUALSDS_1_INST_CLOCK_ENABLE_CH0_STATUS_SDS1_108_CLOCK_ENABLE_CH0_STATUS_MASK 0x00000001
-#define BCHP_CLKGEN_DUALSDS_1_INST_CLOCK_ENABLE_CH0_STATUS_SDS1_108_CLOCK_ENABLE_CH0_STATUS_SHIFT 0
-
-/***************************************************************************
- *DUALSDS_1_INST_CLOCK_ENABLE_CH1 - Dualsds 1 inst clock enable ch1
- ***************************************************************************/
-/* CLKGEN :: DUALSDS_1_INST_CLOCK_ENABLE_CH1 :: reserved0 [31:02] */
-#define BCHP_CLKGEN_DUALSDS_1_INST_CLOCK_ENABLE_CH1_reserved0_MASK 0xfffffffc
-#define BCHP_CLKGEN_DUALSDS_1_INST_CLOCK_ENABLE_CH1_reserved0_SHIFT 2
-
-/* CLKGEN :: DUALSDS_1_INST_CLOCK_ENABLE_CH1 :: SDS1_54_CLOCK_ENABLE_CH1 [01:01] */
-#define BCHP_CLKGEN_DUALSDS_1_INST_CLOCK_ENABLE_CH1_SDS1_54_CLOCK_ENABLE_CH1_MASK 0x00000002
-#define BCHP_CLKGEN_DUALSDS_1_INST_CLOCK_ENABLE_CH1_SDS1_54_CLOCK_ENABLE_CH1_SHIFT 1
-#define BCHP_CLKGEN_DUALSDS_1_INST_CLOCK_ENABLE_CH1_SDS1_54_CLOCK_ENABLE_CH1_DEFAULT 0x00000001
-
-/* CLKGEN :: DUALSDS_1_INST_CLOCK_ENABLE_CH1 :: SDS1_108_CLOCK_ENABLE_CH1 [00:00] */
-#define BCHP_CLKGEN_DUALSDS_1_INST_CLOCK_ENABLE_CH1_SDS1_108_CLOCK_ENABLE_CH1_MASK 0x00000001
-#define BCHP_CLKGEN_DUALSDS_1_INST_CLOCK_ENABLE_CH1_SDS1_108_CLOCK_ENABLE_CH1_SHIFT 0
-#define BCHP_CLKGEN_DUALSDS_1_INST_CLOCK_ENABLE_CH1_SDS1_108_CLOCK_ENABLE_CH1_DEFAULT 0x00000001
-
-/***************************************************************************
- *DUALSDS_1_INST_CLOCK_ENABLE_CH1_STATUS - Clock Enable Status
- ***************************************************************************/
-/* CLKGEN :: DUALSDS_1_INST_CLOCK_ENABLE_CH1_STATUS :: reserved0 [31:02] */
-#define BCHP_CLKGEN_DUALSDS_1_INST_CLOCK_ENABLE_CH1_STATUS_reserved0_MASK 0xfffffffc
-#define BCHP_CLKGEN_DUALSDS_1_INST_CLOCK_ENABLE_CH1_STATUS_reserved0_SHIFT 2
-
-/* CLKGEN :: DUALSDS_1_INST_CLOCK_ENABLE_CH1_STATUS :: SDS1_54_CLOCK_ENABLE_CH1_STATUS [01:01] */
-#define BCHP_CLKGEN_DUALSDS_1_INST_CLOCK_ENABLE_CH1_STATUS_SDS1_54_CLOCK_ENABLE_CH1_STATUS_MASK 0x00000002
-#define BCHP_CLKGEN_DUALSDS_1_INST_CLOCK_ENABLE_CH1_STATUS_SDS1_54_CLOCK_ENABLE_CH1_STATUS_SHIFT 1
-
-/* CLKGEN :: DUALSDS_1_INST_CLOCK_ENABLE_CH1_STATUS :: SDS1_108_CLOCK_ENABLE_CH1_STATUS [00:00] */
-#define BCHP_CLKGEN_DUALSDS_1_INST_CLOCK_ENABLE_CH1_STATUS_SDS1_108_CLOCK_ENABLE_CH1_STATUS_MASK 0x00000001
-#define BCHP_CLKGEN_DUALSDS_1_INST_CLOCK_ENABLE_CH1_STATUS_SDS1_108_CLOCK_ENABLE_CH1_STATUS_SHIFT 0
-
-/***************************************************************************
- *DUALSDS_1_INST_EN_CH0 - Dualsds 1 inst en ch0
- ***************************************************************************/
-/* CLKGEN :: DUALSDS_1_INST_EN_CH0 :: reserved0 [31:01] */
-#define BCHP_CLKGEN_DUALSDS_1_INST_EN_CH0_reserved0_MASK 0xfffffffe
-#define BCHP_CLKGEN_DUALSDS_1_INST_EN_CH0_reserved0_SHIFT 1
-
-/* CLKGEN :: DUALSDS_1_INST_EN_CH0 :: SDS1_PLL_CLOCK_EN_CH0 [00:00] */
-#define BCHP_CLKGEN_DUALSDS_1_INST_EN_CH0_SDS1_PLL_CLOCK_EN_CH0_MASK 0x00000001
-#define BCHP_CLKGEN_DUALSDS_1_INST_EN_CH0_SDS1_PLL_CLOCK_EN_CH0_SHIFT 0
-#define BCHP_CLKGEN_DUALSDS_1_INST_EN_CH0_SDS1_PLL_CLOCK_EN_CH0_DEFAULT 0x00000001
-
-/***************************************************************************
- *DUALSDS_1_INST_EN_CH1 - Dualsds 1 inst en ch1
- ***************************************************************************/
-/* CLKGEN :: DUALSDS_1_INST_EN_CH1 :: reserved0 [31:01] */
-#define BCHP_CLKGEN_DUALSDS_1_INST_EN_CH1_reserved0_MASK 0xfffffffe
-#define BCHP_CLKGEN_DUALSDS_1_INST_EN_CH1_reserved0_SHIFT 1
-
-/* CLKGEN :: DUALSDS_1_INST_EN_CH1 :: SDS1_PLL_CLOCK_EN_CH1 [00:00] */
-#define BCHP_CLKGEN_DUALSDS_1_INST_EN_CH1_SDS1_PLL_CLOCK_EN_CH1_MASK 0x00000001
-#define BCHP_CLKGEN_DUALSDS_1_INST_EN_CH1_SDS1_PLL_CLOCK_EN_CH1_SHIFT 0
-#define BCHP_CLKGEN_DUALSDS_1_INST_EN_CH1_SDS1_PLL_CLOCK_EN_CH1_DEFAULT 0x00000001
-
-/***************************************************************************
- *DUALSDS_1_INST_OBSERVE_CLOCK - Dualsds 1 inst observe clock
- ***************************************************************************/
-/* CLKGEN :: DUALSDS_1_INST_OBSERVE_CLOCK :: reserved0 [31:24] */
-#define BCHP_CLKGEN_DUALSDS_1_INST_OBSERVE_CLOCK_reserved0_MASK 0xff000000
-#define BCHP_CLKGEN_DUALSDS_1_INST_OBSERVE_CLOCK_reserved0_SHIFT 24
-
-/* CLKGEN :: DUALSDS_1_INST_OBSERVE_CLOCK :: SDS1TFEC1_ENABLE_OBSERVE_CLOCK [23:23] */
-#define BCHP_CLKGEN_DUALSDS_1_INST_OBSERVE_CLOCK_SDS1TFEC1_ENABLE_OBSERVE_CLOCK_MASK 0x00800000
-#define BCHP_CLKGEN_DUALSDS_1_INST_OBSERVE_CLOCK_SDS1TFEC1_ENABLE_OBSERVE_CLOCK_SHIFT 23
-#define BCHP_CLKGEN_DUALSDS_1_INST_OBSERVE_CLOCK_SDS1TFEC1_ENABLE_OBSERVE_CLOCK_DEFAULT 0x00000000
-
-/* CLKGEN :: DUALSDS_1_INST_OBSERVE_CLOCK :: SDS1TFEC1_ENABLE_DIVIDER_OBSERVE_CLOCK [22:22] */
-#define BCHP_CLKGEN_DUALSDS_1_INST_OBSERVE_CLOCK_SDS1TFEC1_ENABLE_DIVIDER_OBSERVE_CLOCK_MASK 0x00400000
-#define BCHP_CLKGEN_DUALSDS_1_INST_OBSERVE_CLOCK_SDS1TFEC1_ENABLE_DIVIDER_OBSERVE_CLOCK_SHIFT 22
-#define BCHP_CLKGEN_DUALSDS_1_INST_OBSERVE_CLOCK_SDS1TFEC1_ENABLE_DIVIDER_OBSERVE_CLOCK_DEFAULT 0x00000000
-
-/* CLKGEN :: DUALSDS_1_INST_OBSERVE_CLOCK :: SDS1TFEC1_CONTROL_OBSERVE_CLOCK [21:18] */
-#define BCHP_CLKGEN_DUALSDS_1_INST_OBSERVE_CLOCK_SDS1TFEC1_CONTROL_OBSERVE_CLOCK_MASK 0x003c0000
-#define BCHP_CLKGEN_DUALSDS_1_INST_OBSERVE_CLOCK_SDS1TFEC1_CONTROL_OBSERVE_CLOCK_SHIFT 18
-#define BCHP_CLKGEN_DUALSDS_1_INST_OBSERVE_CLOCK_SDS1TFEC1_CONTROL_OBSERVE_CLOCK_DEFAULT 0x00000000
-
-/* CLKGEN :: DUALSDS_1_INST_OBSERVE_CLOCK :: SDS1TFEC0_ENABLE_OBSERVE_CLOCK [17:17] */
-#define BCHP_CLKGEN_DUALSDS_1_INST_OBSERVE_CLOCK_SDS1TFEC0_ENABLE_OBSERVE_CLOCK_MASK 0x00020000
-#define BCHP_CLKGEN_DUALSDS_1_INST_OBSERVE_CLOCK_SDS1TFEC0_ENABLE_OBSERVE_CLOCK_SHIFT 17
-#define BCHP_CLKGEN_DUALSDS_1_INST_OBSERVE_CLOCK_SDS1TFEC0_ENABLE_OBSERVE_CLOCK_DEFAULT 0x00000000
-
-/* CLKGEN :: DUALSDS_1_INST_OBSERVE_CLOCK :: SDS1TFEC0_ENABLE_DIVIDER_OBSERVE_CLOCK [16:16] */
-#define BCHP_CLKGEN_DUALSDS_1_INST_OBSERVE_CLOCK_SDS1TFEC0_ENABLE_DIVIDER_OBSERVE_CLOCK_MASK 0x00010000
-#define BCHP_CLKGEN_DUALSDS_1_INST_OBSERVE_CLOCK_SDS1TFEC0_ENABLE_DIVIDER_OBSERVE_CLOCK_SHIFT 16
-#define BCHP_CLKGEN_DUALSDS_1_INST_OBSERVE_CLOCK_SDS1TFEC0_ENABLE_DIVIDER_OBSERVE_CLOCK_DEFAULT 0x00000000
-
-/* CLKGEN :: DUALSDS_1_INST_OBSERVE_CLOCK :: SDS1TFEC0_CONTROL_OBSERVE_CLOCK [15:12] */
-#define BCHP_CLKGEN_DUALSDS_1_INST_OBSERVE_CLOCK_SDS1TFEC0_CONTROL_OBSERVE_CLOCK_MASK 0x0000f000
-#define BCHP_CLKGEN_DUALSDS_1_INST_OBSERVE_CLOCK_SDS1TFEC0_CONTROL_OBSERVE_CLOCK_SHIFT 12
-#define BCHP_CLKGEN_DUALSDS_1_INST_OBSERVE_CLOCK_SDS1TFEC0_CONTROL_OBSERVE_CLOCK_DEFAULT 0x00000000
-
-/* CLKGEN :: DUALSDS_1_INST_OBSERVE_CLOCK :: SDS1RCVR1_ENABLE_OBSERVE_CLOCK [11:11] */
-#define BCHP_CLKGEN_DUALSDS_1_INST_OBSERVE_CLOCK_SDS1RCVR1_ENABLE_OBSERVE_CLOCK_MASK 0x00000800
-#define BCHP_CLKGEN_DUALSDS_1_INST_OBSERVE_CLOCK_SDS1RCVR1_ENABLE_OBSERVE_CLOCK_SHIFT 11
-#define BCHP_CLKGEN_DUALSDS_1_INST_OBSERVE_CLOCK_SDS1RCVR1_ENABLE_OBSERVE_CLOCK_DEFAULT 0x00000000
-
-/* CLKGEN :: DUALSDS_1_INST_OBSERVE_CLOCK :: SDS1RCVR1_ENABLE_DIVIDER_OBSERVE_CLOCK [10:10] */
-#define BCHP_CLKGEN_DUALSDS_1_INST_OBSERVE_CLOCK_SDS1RCVR1_ENABLE_DIVIDER_OBSERVE_CLOCK_MASK 0x00000400
-#define BCHP_CLKGEN_DUALSDS_1_INST_OBSERVE_CLOCK_SDS1RCVR1_ENABLE_DIVIDER_OBSERVE_CLOCK_SHIFT 10
-#define BCHP_CLKGEN_DUALSDS_1_INST_OBSERVE_CLOCK_SDS1RCVR1_ENABLE_DIVIDER_OBSERVE_CLOCK_DEFAULT 0x00000000
-
-/* CLKGEN :: DUALSDS_1_INST_OBSERVE_CLOCK :: SDS1RCVR1_CONTROL_OBSERVE_CLOCK [09:06] */
-#define BCHP_CLKGEN_DUALSDS_1_INST_OBSERVE_CLOCK_SDS1RCVR1_CONTROL_OBSERVE_CLOCK_MASK 0x000003c0
-#define BCHP_CLKGEN_DUALSDS_1_INST_OBSERVE_CLOCK_SDS1RCVR1_CONTROL_OBSERVE_CLOCK_SHIFT 6
-#define BCHP_CLKGEN_DUALSDS_1_INST_OBSERVE_CLOCK_SDS1RCVR1_CONTROL_OBSERVE_CLOCK_DEFAULT 0x00000000
-
-/* CLKGEN :: DUALSDS_1_INST_OBSERVE_CLOCK :: SDS1RCVR0_ENABLE_OBSERVE_CLOCK [05:05] */
-#define BCHP_CLKGEN_DUALSDS_1_INST_OBSERVE_CLOCK_SDS1RCVR0_ENABLE_OBSERVE_CLOCK_MASK 0x00000020
-#define BCHP_CLKGEN_DUALSDS_1_INST_OBSERVE_CLOCK_SDS1RCVR0_ENABLE_OBSERVE_CLOCK_SHIFT 5
-#define BCHP_CLKGEN_DUALSDS_1_INST_OBSERVE_CLOCK_SDS1RCVR0_ENABLE_OBSERVE_CLOCK_DEFAULT 0x00000000
-
-/* CLKGEN :: DUALSDS_1_INST_OBSERVE_CLOCK :: SDS1RCVR0_ENABLE_DIVIDER_OBSERVE_CLOCK [04:04] */
-#define BCHP_CLKGEN_DUALSDS_1_INST_OBSERVE_CLOCK_SDS1RCVR0_ENABLE_DIVIDER_OBSERVE_CLOCK_MASK 0x00000010
-#define BCHP_CLKGEN_DUALSDS_1_INST_OBSERVE_CLOCK_SDS1RCVR0_ENABLE_DIVIDER_OBSERVE_CLOCK_SHIFT 4
-#define BCHP_CLKGEN_DUALSDS_1_INST_OBSERVE_CLOCK_SDS1RCVR0_ENABLE_DIVIDER_OBSERVE_CLOCK_DEFAULT 0x00000000
-
-/* CLKGEN :: DUALSDS_1_INST_OBSERVE_CLOCK :: SDS1RCVR0_CONTROL_OBSERVE_CLOCK [03:00] */
-#define BCHP_CLKGEN_DUALSDS_1_INST_OBSERVE_CLOCK_SDS1RCVR0_CONTROL_OBSERVE_CLOCK_MASK 0x0000000f
-#define BCHP_CLKGEN_DUALSDS_1_INST_OBSERVE_CLOCK_SDS1RCVR0_CONTROL_OBSERVE_CLOCK_SHIFT 0
-#define BCHP_CLKGEN_DUALSDS_1_INST_OBSERVE_CLOCK_SDS1RCVR0_CONTROL_OBSERVE_CLOCK_DEFAULT 0x00000000
-
-/***************************************************************************
- *DUALSDS_1_INST_PLL_CLOCK_EN - Dualsds 1 inst pll clock en
- ***************************************************************************/
-/* CLKGEN :: DUALSDS_1_INST_PLL_CLOCK_EN :: reserved0 [31:02] */
-#define BCHP_CLKGEN_DUALSDS_1_INST_PLL_CLOCK_EN_reserved0_MASK 0xfffffffc
-#define BCHP_CLKGEN_DUALSDS_1_INST_PLL_CLOCK_EN_reserved0_SHIFT 2
-
-/* CLKGEN :: DUALSDS_1_INST_PLL_CLOCK_EN :: SDS1TFEC1_PLL_CLOCK_EN [01:01] */
-#define BCHP_CLKGEN_DUALSDS_1_INST_PLL_CLOCK_EN_SDS1TFEC1_PLL_CLOCK_EN_MASK 0x00000002
-#define BCHP_CLKGEN_DUALSDS_1_INST_PLL_CLOCK_EN_SDS1TFEC1_PLL_CLOCK_EN_SHIFT 1
-#define BCHP_CLKGEN_DUALSDS_1_INST_PLL_CLOCK_EN_SDS1TFEC1_PLL_CLOCK_EN_DEFAULT 0x00000001
-
-/* CLKGEN :: DUALSDS_1_INST_PLL_CLOCK_EN :: SDS1TFEC0_PLL_CLOCK_EN [00:00] */
-#define BCHP_CLKGEN_DUALSDS_1_INST_PLL_CLOCK_EN_SDS1TFEC0_PLL_CLOCK_EN_MASK 0x00000001
-#define BCHP_CLKGEN_DUALSDS_1_INST_PLL_CLOCK_EN_SDS1TFEC0_PLL_CLOCK_EN_SHIFT 0
-#define BCHP_CLKGEN_DUALSDS_1_INST_PLL_CLOCK_EN_SDS1TFEC0_PLL_CLOCK_EN_DEFAULT 0x00000001
-
-/***************************************************************************
- *DUALSDS_1_INST_SEL - Dualsds 1 inst sel
- ***************************************************************************/
-/* CLKGEN :: DUALSDS_1_INST_SEL :: reserved0 [31:02] */
-#define BCHP_CLKGEN_DUALSDS_1_INST_SEL_reserved0_MASK 0xfffffffc
-#define BCHP_CLKGEN_DUALSDS_1_INST_SEL_reserved0_SHIFT 2
-
-/* CLKGEN :: DUALSDS_1_INST_SEL :: SDS1_LV_CLK_PLL_SRC_SEL [01:01] */
-#define BCHP_CLKGEN_DUALSDS_1_INST_SEL_SDS1_LV_CLK_PLL_SRC_SEL_MASK 0x00000002
-#define BCHP_CLKGEN_DUALSDS_1_INST_SEL_SDS1_LV_CLK_PLL_SRC_SEL_SHIFT 1
-#define BCHP_CLKGEN_DUALSDS_1_INST_SEL_SDS1_LV_CLK_PLL_SRC_SEL_DEFAULT 0x00000000
-
-/* CLKGEN :: DUALSDS_1_INST_SEL :: SDS1_CHAN_I_CLK_240_LV_CLK_PLL_SRC_SEL [00:00] */
-#define BCHP_CLKGEN_DUALSDS_1_INST_SEL_SDS1_CHAN_I_CLK_240_LV_CLK_PLL_SRC_SEL_MASK 0x00000001
-#define BCHP_CLKGEN_DUALSDS_1_INST_SEL_SDS1_CHAN_I_CLK_240_LV_CLK_PLL_SRC_SEL_SHIFT 0
-#define BCHP_CLKGEN_DUALSDS_1_INST_SEL_SDS1_CHAN_I_CLK_240_LV_CLK_PLL_SRC_SEL_DEFAULT 0x00000000
-
-/***************************************************************************
- *DUALSDS_2_INST_CLOCK_DISABLE - Disable DUALSDS_2_INST's clocks
- ***************************************************************************/
-/* CLKGEN :: DUALSDS_2_INST_CLOCK_DISABLE :: reserved0 [31:02] */
-#define BCHP_CLKGEN_DUALSDS_2_INST_CLOCK_DISABLE_reserved0_MASK 0xfffffffc
-#define BCHP_CLKGEN_DUALSDS_2_INST_CLOCK_DISABLE_reserved0_SHIFT 2
-
-/* CLKGEN :: DUALSDS_2_INST_CLOCK_DISABLE :: DISABLE_SDS2RCVR1_108_PRESPMBALANCE_CLOCK [01:01] */
-#define BCHP_CLKGEN_DUALSDS_2_INST_CLOCK_DISABLE_DISABLE_SDS2RCVR1_108_PRESPMBALANCE_CLOCK_MASK 0x00000002
-#define BCHP_CLKGEN_DUALSDS_2_INST_CLOCK_DISABLE_DISABLE_SDS2RCVR1_108_PRESPMBALANCE_CLOCK_SHIFT 1
-#define BCHP_CLKGEN_DUALSDS_2_INST_CLOCK_DISABLE_DISABLE_SDS2RCVR1_108_PRESPMBALANCE_CLOCK_DEFAULT 0x00000000
-
-/* CLKGEN :: DUALSDS_2_INST_CLOCK_DISABLE :: DISABLE_SDS2RCVR0_108_PRESPMBALANCE_CLOCK [00:00] */
-#define BCHP_CLKGEN_DUALSDS_2_INST_CLOCK_DISABLE_DISABLE_SDS2RCVR0_108_PRESPMBALANCE_CLOCK_MASK 0x00000001
-#define BCHP_CLKGEN_DUALSDS_2_INST_CLOCK_DISABLE_DISABLE_SDS2RCVR0_108_PRESPMBALANCE_CLOCK_SHIFT 0
-#define BCHP_CLKGEN_DUALSDS_2_INST_CLOCK_DISABLE_DISABLE_SDS2RCVR0_108_PRESPMBALANCE_CLOCK_DEFAULT 0x00000000
-
-/***************************************************************************
- *DUALSDS_2_INST_CLOCK_DISABLE_STATUS - Clock Disable Status
- ***************************************************************************/
-/* CLKGEN :: DUALSDS_2_INST_CLOCK_DISABLE_STATUS :: reserved0 [31:02] */
-#define BCHP_CLKGEN_DUALSDS_2_INST_CLOCK_DISABLE_STATUS_reserved0_MASK 0xfffffffc
-#define BCHP_CLKGEN_DUALSDS_2_INST_CLOCK_DISABLE_STATUS_reserved0_SHIFT 2
-
-/* CLKGEN :: DUALSDS_2_INST_CLOCK_DISABLE_STATUS :: DISABLE_SDS2RCVR1_108_PRESPMBALANCE_CLOCK_STATUS [01:01] */
-#define BCHP_CLKGEN_DUALSDS_2_INST_CLOCK_DISABLE_STATUS_DISABLE_SDS2RCVR1_108_PRESPMBALANCE_CLOCK_STATUS_MASK 0x00000002
-#define BCHP_CLKGEN_DUALSDS_2_INST_CLOCK_DISABLE_STATUS_DISABLE_SDS2RCVR1_108_PRESPMBALANCE_CLOCK_STATUS_SHIFT 1
-
-/* CLKGEN :: DUALSDS_2_INST_CLOCK_DISABLE_STATUS :: DISABLE_SDS2RCVR0_108_PRESPMBALANCE_CLOCK_STATUS [00:00] */
-#define BCHP_CLKGEN_DUALSDS_2_INST_CLOCK_DISABLE_STATUS_DISABLE_SDS2RCVR0_108_PRESPMBALANCE_CLOCK_STATUS_MASK 0x00000001
-#define BCHP_CLKGEN_DUALSDS_2_INST_CLOCK_DISABLE_STATUS_DISABLE_SDS2RCVR0_108_PRESPMBALANCE_CLOCK_STATUS_SHIFT 0
-
-/***************************************************************************
- *DUALSDS_2_INST_CLOCK_ENABLE_CH0 - Dualsds 2 inst clock enable ch0
- ***************************************************************************/
-/* CLKGEN :: DUALSDS_2_INST_CLOCK_ENABLE_CH0 :: reserved0 [31:02] */
-#define BCHP_CLKGEN_DUALSDS_2_INST_CLOCK_ENABLE_CH0_reserved0_MASK 0xfffffffc
-#define BCHP_CLKGEN_DUALSDS_2_INST_CLOCK_ENABLE_CH0_reserved0_SHIFT 2
-
-/* CLKGEN :: DUALSDS_2_INST_CLOCK_ENABLE_CH0 :: SDS2_54_CLOCK_ENABLE_CH0 [01:01] */
-#define BCHP_CLKGEN_DUALSDS_2_INST_CLOCK_ENABLE_CH0_SDS2_54_CLOCK_ENABLE_CH0_MASK 0x00000002
-#define BCHP_CLKGEN_DUALSDS_2_INST_CLOCK_ENABLE_CH0_SDS2_54_CLOCK_ENABLE_CH0_SHIFT 1
-#define BCHP_CLKGEN_DUALSDS_2_INST_CLOCK_ENABLE_CH0_SDS2_54_CLOCK_ENABLE_CH0_DEFAULT 0x00000001
-
-/* CLKGEN :: DUALSDS_2_INST_CLOCK_ENABLE_CH0 :: SDS2_108_CLOCK_ENABLE_CH0 [00:00] */
-#define BCHP_CLKGEN_DUALSDS_2_INST_CLOCK_ENABLE_CH0_SDS2_108_CLOCK_ENABLE_CH0_MASK 0x00000001
-#define BCHP_CLKGEN_DUALSDS_2_INST_CLOCK_ENABLE_CH0_SDS2_108_CLOCK_ENABLE_CH0_SHIFT 0
-#define BCHP_CLKGEN_DUALSDS_2_INST_CLOCK_ENABLE_CH0_SDS2_108_CLOCK_ENABLE_CH0_DEFAULT 0x00000001
-
-/***************************************************************************
- *DUALSDS_2_INST_CLOCK_ENABLE_CH0_STATUS - Clock Enable Status
- ***************************************************************************/
-/* CLKGEN :: DUALSDS_2_INST_CLOCK_ENABLE_CH0_STATUS :: reserved0 [31:02] */
-#define BCHP_CLKGEN_DUALSDS_2_INST_CLOCK_ENABLE_CH0_STATUS_reserved0_MASK 0xfffffffc
-#define BCHP_CLKGEN_DUALSDS_2_INST_CLOCK_ENABLE_CH0_STATUS_reserved0_SHIFT 2
-
-/* CLKGEN :: DUALSDS_2_INST_CLOCK_ENABLE_CH0_STATUS :: SDS2_54_CLOCK_ENABLE_CH0_STATUS [01:01] */
-#define BCHP_CLKGEN_DUALSDS_2_INST_CLOCK_ENABLE_CH0_STATUS_SDS2_54_CLOCK_ENABLE_CH0_STATUS_MASK 0x00000002
-#define BCHP_CLKGEN_DUALSDS_2_INST_CLOCK_ENABLE_CH0_STATUS_SDS2_54_CLOCK_ENABLE_CH0_STATUS_SHIFT 1
-
-/* CLKGEN :: DUALSDS_2_INST_CLOCK_ENABLE_CH0_STATUS :: SDS2_108_CLOCK_ENABLE_CH0_STATUS [00:00] */
-#define BCHP_CLKGEN_DUALSDS_2_INST_CLOCK_ENABLE_CH0_STATUS_SDS2_108_CLOCK_ENABLE_CH0_STATUS_MASK 0x00000001
-#define BCHP_CLKGEN_DUALSDS_2_INST_CLOCK_ENABLE_CH0_STATUS_SDS2_108_CLOCK_ENABLE_CH0_STATUS_SHIFT 0
-
-/***************************************************************************
- *DUALSDS_2_INST_CLOCK_ENABLE_CH1 - Dualsds 2 inst clock enable ch1
- ***************************************************************************/
-/* CLKGEN :: DUALSDS_2_INST_CLOCK_ENABLE_CH1 :: reserved0 [31:02] */
-#define BCHP_CLKGEN_DUALSDS_2_INST_CLOCK_ENABLE_CH1_reserved0_MASK 0xfffffffc
-#define BCHP_CLKGEN_DUALSDS_2_INST_CLOCK_ENABLE_CH1_reserved0_SHIFT 2
-
-/* CLKGEN :: DUALSDS_2_INST_CLOCK_ENABLE_CH1 :: SDS2_54_CLOCK_ENABLE_CH1 [01:01] */
-#define BCHP_CLKGEN_DUALSDS_2_INST_CLOCK_ENABLE_CH1_SDS2_54_CLOCK_ENABLE_CH1_MASK 0x00000002
-#define BCHP_CLKGEN_DUALSDS_2_INST_CLOCK_ENABLE_CH1_SDS2_54_CLOCK_ENABLE_CH1_SHIFT 1
-#define BCHP_CLKGEN_DUALSDS_2_INST_CLOCK_ENABLE_CH1_SDS2_54_CLOCK_ENABLE_CH1_DEFAULT 0x00000001
-
-/* CLKGEN :: DUALSDS_2_INST_CLOCK_ENABLE_CH1 :: SDS2_108_CLOCK_ENABLE_CH1 [00:00] */
-#define BCHP_CLKGEN_DUALSDS_2_INST_CLOCK_ENABLE_CH1_SDS2_108_CLOCK_ENABLE_CH1_MASK 0x00000001
-#define BCHP_CLKGEN_DUALSDS_2_INST_CLOCK_ENABLE_CH1_SDS2_108_CLOCK_ENABLE_CH1_SHIFT 0
-#define BCHP_CLKGEN_DUALSDS_2_INST_CLOCK_ENABLE_CH1_SDS2_108_CLOCK_ENABLE_CH1_DEFAULT 0x00000001
-
-/***************************************************************************
- *DUALSDS_2_INST_CLOCK_ENABLE_CH1_STATUS - Clock Enable Status
- ***************************************************************************/
-/* CLKGEN :: DUALSDS_2_INST_CLOCK_ENABLE_CH1_STATUS :: reserved0 [31:02] */
-#define BCHP_CLKGEN_DUALSDS_2_INST_CLOCK_ENABLE_CH1_STATUS_reserved0_MASK 0xfffffffc
-#define BCHP_CLKGEN_DUALSDS_2_INST_CLOCK_ENABLE_CH1_STATUS_reserved0_SHIFT 2
-
-/* CLKGEN :: DUALSDS_2_INST_CLOCK_ENABLE_CH1_STATUS :: SDS2_54_CLOCK_ENABLE_CH1_STATUS [01:01] */
-#define BCHP_CLKGEN_DUALSDS_2_INST_CLOCK_ENABLE_CH1_STATUS_SDS2_54_CLOCK_ENABLE_CH1_STATUS_MASK 0x00000002
-#define BCHP_CLKGEN_DUALSDS_2_INST_CLOCK_ENABLE_CH1_STATUS_SDS2_54_CLOCK_ENABLE_CH1_STATUS_SHIFT 1
-
-/* CLKGEN :: DUALSDS_2_INST_CLOCK_ENABLE_CH1_STATUS :: SDS2_108_CLOCK_ENABLE_CH1_STATUS [00:00] */
-#define BCHP_CLKGEN_DUALSDS_2_INST_CLOCK_ENABLE_CH1_STATUS_SDS2_108_CLOCK_ENABLE_CH1_STATUS_MASK 0x00000001
-#define BCHP_CLKGEN_DUALSDS_2_INST_CLOCK_ENABLE_CH1_STATUS_SDS2_108_CLOCK_ENABLE_CH1_STATUS_SHIFT 0
-
-/***************************************************************************
- *DUALSDS_2_INST_EN_CH0 - Dualsds 2 inst en ch0
- ***************************************************************************/
-/* CLKGEN :: DUALSDS_2_INST_EN_CH0 :: reserved0 [31:01] */
-#define BCHP_CLKGEN_DUALSDS_2_INST_EN_CH0_reserved0_MASK 0xfffffffe
-#define BCHP_CLKGEN_DUALSDS_2_INST_EN_CH0_reserved0_SHIFT 1
-
-/* CLKGEN :: DUALSDS_2_INST_EN_CH0 :: SDS2_PLL_CLOCK_EN_CH0 [00:00] */
-#define BCHP_CLKGEN_DUALSDS_2_INST_EN_CH0_SDS2_PLL_CLOCK_EN_CH0_MASK 0x00000001
-#define BCHP_CLKGEN_DUALSDS_2_INST_EN_CH0_SDS2_PLL_CLOCK_EN_CH0_SHIFT 0
-#define BCHP_CLKGEN_DUALSDS_2_INST_EN_CH0_SDS2_PLL_CLOCK_EN_CH0_DEFAULT 0x00000001
-
-/***************************************************************************
- *DUALSDS_2_INST_EN_CH1 - Dualsds 2 inst en ch1
- ***************************************************************************/
-/* CLKGEN :: DUALSDS_2_INST_EN_CH1 :: reserved0 [31:01] */
-#define BCHP_CLKGEN_DUALSDS_2_INST_EN_CH1_reserved0_MASK 0xfffffffe
-#define BCHP_CLKGEN_DUALSDS_2_INST_EN_CH1_reserved0_SHIFT 1
-
-/* CLKGEN :: DUALSDS_2_INST_EN_CH1 :: SDS2_PLL_CLOCK_EN_CH1 [00:00] */
-#define BCHP_CLKGEN_DUALSDS_2_INST_EN_CH1_SDS2_PLL_CLOCK_EN_CH1_MASK 0x00000001
-#define BCHP_CLKGEN_DUALSDS_2_INST_EN_CH1_SDS2_PLL_CLOCK_EN_CH1_SHIFT 0
-#define BCHP_CLKGEN_DUALSDS_2_INST_EN_CH1_SDS2_PLL_CLOCK_EN_CH1_DEFAULT 0x00000001
-
-/***************************************************************************
- *DUALSDS_2_INST_OBSERVE_CLOCK - Dualsds 2 inst observe clock
- ***************************************************************************/
-/* CLKGEN :: DUALSDS_2_INST_OBSERVE_CLOCK :: reserved0 [31:24] */
-#define BCHP_CLKGEN_DUALSDS_2_INST_OBSERVE_CLOCK_reserved0_MASK 0xff000000
-#define BCHP_CLKGEN_DUALSDS_2_INST_OBSERVE_CLOCK_reserved0_SHIFT 24
-
-/* CLKGEN :: DUALSDS_2_INST_OBSERVE_CLOCK :: SDS2TFEC1_ENABLE_OBSERVE_CLOCK [23:23] */
-#define BCHP_CLKGEN_DUALSDS_2_INST_OBSERVE_CLOCK_SDS2TFEC1_ENABLE_OBSERVE_CLOCK_MASK 0x00800000
-#define BCHP_CLKGEN_DUALSDS_2_INST_OBSERVE_CLOCK_SDS2TFEC1_ENABLE_OBSERVE_CLOCK_SHIFT 23
-#define BCHP_CLKGEN_DUALSDS_2_INST_OBSERVE_CLOCK_SDS2TFEC1_ENABLE_OBSERVE_CLOCK_DEFAULT 0x00000000
-
-/* CLKGEN :: DUALSDS_2_INST_OBSERVE_CLOCK :: SDS2TFEC1_ENABLE_DIVIDER_OBSERVE_CLOCK [22:22] */
-#define BCHP_CLKGEN_DUALSDS_2_INST_OBSERVE_CLOCK_SDS2TFEC1_ENABLE_DIVIDER_OBSERVE_CLOCK_MASK 0x00400000
-#define BCHP_CLKGEN_DUALSDS_2_INST_OBSERVE_CLOCK_SDS2TFEC1_ENABLE_DIVIDER_OBSERVE_CLOCK_SHIFT 22
-#define BCHP_CLKGEN_DUALSDS_2_INST_OBSERVE_CLOCK_SDS2TFEC1_ENABLE_DIVIDER_OBSERVE_CLOCK_DEFAULT 0x00000000
-
-/* CLKGEN :: DUALSDS_2_INST_OBSERVE_CLOCK :: SDS2TFEC1_CONTROL_OBSERVE_CLOCK [21:18] */
-#define BCHP_CLKGEN_DUALSDS_2_INST_OBSERVE_CLOCK_SDS2TFEC1_CONTROL_OBSERVE_CLOCK_MASK 0x003c0000
-#define BCHP_CLKGEN_DUALSDS_2_INST_OBSERVE_CLOCK_SDS2TFEC1_CONTROL_OBSERVE_CLOCK_SHIFT 18
-#define BCHP_CLKGEN_DUALSDS_2_INST_OBSERVE_CLOCK_SDS2TFEC1_CONTROL_OBSERVE_CLOCK_DEFAULT 0x00000000
-
-/* CLKGEN :: DUALSDS_2_INST_OBSERVE_CLOCK :: SDS2TFEC0_ENABLE_OBSERVE_CLOCK [17:17] */
-#define BCHP_CLKGEN_DUALSDS_2_INST_OBSERVE_CLOCK_SDS2TFEC0_ENABLE_OBSERVE_CLOCK_MASK 0x00020000
-#define BCHP_CLKGEN_DUALSDS_2_INST_OBSERVE_CLOCK_SDS2TFEC0_ENABLE_OBSERVE_CLOCK_SHIFT 17
-#define BCHP_CLKGEN_DUALSDS_2_INST_OBSERVE_CLOCK_SDS2TFEC0_ENABLE_OBSERVE_CLOCK_DEFAULT 0x00000000
-
-/* CLKGEN :: DUALSDS_2_INST_OBSERVE_CLOCK :: SDS2TFEC0_ENABLE_DIVIDER_OBSERVE_CLOCK [16:16] */
-#define BCHP_CLKGEN_DUALSDS_2_INST_OBSERVE_CLOCK_SDS2TFEC0_ENABLE_DIVIDER_OBSERVE_CLOCK_MASK 0x00010000
-#define BCHP_CLKGEN_DUALSDS_2_INST_OBSERVE_CLOCK_SDS2TFEC0_ENABLE_DIVIDER_OBSERVE_CLOCK_SHIFT 16
-#define BCHP_CLKGEN_DUALSDS_2_INST_OBSERVE_CLOCK_SDS2TFEC0_ENABLE_DIVIDER_OBSERVE_CLOCK_DEFAULT 0x00000000
-
-/* CLKGEN :: DUALSDS_2_INST_OBSERVE_CLOCK :: SDS2TFEC0_CONTROL_OBSERVE_CLOCK [15:12] */
-#define BCHP_CLKGEN_DUALSDS_2_INST_OBSERVE_CLOCK_SDS2TFEC0_CONTROL_OBSERVE_CLOCK_MASK 0x0000f000
-#define BCHP_CLKGEN_DUALSDS_2_INST_OBSERVE_CLOCK_SDS2TFEC0_CONTROL_OBSERVE_CLOCK_SHIFT 12
-#define BCHP_CLKGEN_DUALSDS_2_INST_OBSERVE_CLOCK_SDS2TFEC0_CONTROL_OBSERVE_CLOCK_DEFAULT 0x00000000
-
-/* CLKGEN :: DUALSDS_2_INST_OBSERVE_CLOCK :: SDS2RCVR1_ENABLE_OBSERVE_CLOCK [11:11] */
-#define BCHP_CLKGEN_DUALSDS_2_INST_OBSERVE_CLOCK_SDS2RCVR1_ENABLE_OBSERVE_CLOCK_MASK 0x00000800
-#define BCHP_CLKGEN_DUALSDS_2_INST_OBSERVE_CLOCK_SDS2RCVR1_ENABLE_OBSERVE_CLOCK_SHIFT 11
-#define BCHP_CLKGEN_DUALSDS_2_INST_OBSERVE_CLOCK_SDS2RCVR1_ENABLE_OBSERVE_CLOCK_DEFAULT 0x00000000
-
-/* CLKGEN :: DUALSDS_2_INST_OBSERVE_CLOCK :: SDS2RCVR1_ENABLE_DIVIDER_OBSERVE_CLOCK [10:10] */
-#define BCHP_CLKGEN_DUALSDS_2_INST_OBSERVE_CLOCK_SDS2RCVR1_ENABLE_DIVIDER_OBSERVE_CLOCK_MASK 0x00000400
-#define BCHP_CLKGEN_DUALSDS_2_INST_OBSERVE_CLOCK_SDS2RCVR1_ENABLE_DIVIDER_OBSERVE_CLOCK_SHIFT 10
-#define BCHP_CLKGEN_DUALSDS_2_INST_OBSERVE_CLOCK_SDS2RCVR1_ENABLE_DIVIDER_OBSERVE_CLOCK_DEFAULT 0x00000000
-
-/* CLKGEN :: DUALSDS_2_INST_OBSERVE_CLOCK :: SDS2RCVR1_CONTROL_OBSERVE_CLOCK [09:06] */
-#define BCHP_CLKGEN_DUALSDS_2_INST_OBSERVE_CLOCK_SDS2RCVR1_CONTROL_OBSERVE_CLOCK_MASK 0x000003c0
-#define BCHP_CLKGEN_DUALSDS_2_INST_OBSERVE_CLOCK_SDS2RCVR1_CONTROL_OBSERVE_CLOCK_SHIFT 6
-#define BCHP_CLKGEN_DUALSDS_2_INST_OBSERVE_CLOCK_SDS2RCVR1_CONTROL_OBSERVE_CLOCK_DEFAULT 0x00000000
-
-/* CLKGEN :: DUALSDS_2_INST_OBSERVE_CLOCK :: SDS2RCVR0_ENABLE_OBSERVE_CLOCK [05:05] */
-#define BCHP_CLKGEN_DUALSDS_2_INST_OBSERVE_CLOCK_SDS2RCVR0_ENABLE_OBSERVE_CLOCK_MASK 0x00000020
-#define BCHP_CLKGEN_DUALSDS_2_INST_OBSERVE_CLOCK_SDS2RCVR0_ENABLE_OBSERVE_CLOCK_SHIFT 5
-#define BCHP_CLKGEN_DUALSDS_2_INST_OBSERVE_CLOCK_SDS2RCVR0_ENABLE_OBSERVE_CLOCK_DEFAULT 0x00000000
-
-/* CLKGEN :: DUALSDS_2_INST_OBSERVE_CLOCK :: SDS2RCVR0_ENABLE_DIVIDER_OBSERVE_CLOCK [04:04] */
-#define BCHP_CLKGEN_DUALSDS_2_INST_OBSERVE_CLOCK_SDS2RCVR0_ENABLE_DIVIDER_OBSERVE_CLOCK_MASK 0x00000010
-#define BCHP_CLKGEN_DUALSDS_2_INST_OBSERVE_CLOCK_SDS2RCVR0_ENABLE_DIVIDER_OBSERVE_CLOCK_SHIFT 4
-#define BCHP_CLKGEN_DUALSDS_2_INST_OBSERVE_CLOCK_SDS2RCVR0_ENABLE_DIVIDER_OBSERVE_CLOCK_DEFAULT 0x00000000
-
-/* CLKGEN :: DUALSDS_2_INST_OBSERVE_CLOCK :: SDS2RCVR0_CONTROL_OBSERVE_CLOCK [03:00] */
-#define BCHP_CLKGEN_DUALSDS_2_INST_OBSERVE_CLOCK_SDS2RCVR0_CONTROL_OBSERVE_CLOCK_MASK 0x0000000f
-#define BCHP_CLKGEN_DUALSDS_2_INST_OBSERVE_CLOCK_SDS2RCVR0_CONTROL_OBSERVE_CLOCK_SHIFT 0
-#define BCHP_CLKGEN_DUALSDS_2_INST_OBSERVE_CLOCK_SDS2RCVR0_CONTROL_OBSERVE_CLOCK_DEFAULT 0x00000000
-
-/***************************************************************************
- *DUALSDS_2_INST_PLL_CLOCK_EN - Dualsds 2 inst pll clock en
- ***************************************************************************/
-/* CLKGEN :: DUALSDS_2_INST_PLL_CLOCK_EN :: reserved0 [31:02] */
-#define BCHP_CLKGEN_DUALSDS_2_INST_PLL_CLOCK_EN_reserved0_MASK 0xfffffffc
-#define BCHP_CLKGEN_DUALSDS_2_INST_PLL_CLOCK_EN_reserved0_SHIFT 2
-
-/* CLKGEN :: DUALSDS_2_INST_PLL_CLOCK_EN :: SDS2TFEC1_PLL_CLOCK_EN [01:01] */
-#define BCHP_CLKGEN_DUALSDS_2_INST_PLL_CLOCK_EN_SDS2TFEC1_PLL_CLOCK_EN_MASK 0x00000002
-#define BCHP_CLKGEN_DUALSDS_2_INST_PLL_CLOCK_EN_SDS2TFEC1_PLL_CLOCK_EN_SHIFT 1
-#define BCHP_CLKGEN_DUALSDS_2_INST_PLL_CLOCK_EN_SDS2TFEC1_PLL_CLOCK_EN_DEFAULT 0x00000001
-
-/* CLKGEN :: DUALSDS_2_INST_PLL_CLOCK_EN :: SDS2TFEC0_PLL_CLOCK_EN [00:00] */
-#define BCHP_CLKGEN_DUALSDS_2_INST_PLL_CLOCK_EN_SDS2TFEC0_PLL_CLOCK_EN_MASK 0x00000001
-#define BCHP_CLKGEN_DUALSDS_2_INST_PLL_CLOCK_EN_SDS2TFEC0_PLL_CLOCK_EN_SHIFT 0
-#define BCHP_CLKGEN_DUALSDS_2_INST_PLL_CLOCK_EN_SDS2TFEC0_PLL_CLOCK_EN_DEFAULT 0x00000001
-
-/***************************************************************************
- *DUALSDS_2_INST_SEL - Dualsds 2 inst sel
- ***************************************************************************/
-/* CLKGEN :: DUALSDS_2_INST_SEL :: reserved0 [31:02] */
-#define BCHP_CLKGEN_DUALSDS_2_INST_SEL_reserved0_MASK 0xfffffffc
-#define BCHP_CLKGEN_DUALSDS_2_INST_SEL_reserved0_SHIFT 2
-
-/* CLKGEN :: DUALSDS_2_INST_SEL :: SDS2_LV_CLK_PLL_SRC_SEL [01:01] */
-#define BCHP_CLKGEN_DUALSDS_2_INST_SEL_SDS2_LV_CLK_PLL_SRC_SEL_MASK 0x00000002
-#define BCHP_CLKGEN_DUALSDS_2_INST_SEL_SDS2_LV_CLK_PLL_SRC_SEL_SHIFT 1
-#define BCHP_CLKGEN_DUALSDS_2_INST_SEL_SDS2_LV_CLK_PLL_SRC_SEL_DEFAULT 0x00000000
-
-/* CLKGEN :: DUALSDS_2_INST_SEL :: SDS2_CHAN_I_CLK_240_LV_CLK_PLL_SRC_SEL [00:00] */
-#define BCHP_CLKGEN_DUALSDS_2_INST_SEL_SDS2_CHAN_I_CLK_240_LV_CLK_PLL_SRC_SEL_MASK 0x00000001
-#define BCHP_CLKGEN_DUALSDS_2_INST_SEL_SDS2_CHAN_I_CLK_240_LV_CLK_PLL_SRC_SEL_SHIFT 0
-#define BCHP_CLKGEN_DUALSDS_2_INST_SEL_SDS2_CHAN_I_CLK_240_LV_CLK_PLL_SRC_SEL_DEFAULT 0x00000000
-
-/***************************************************************************
- *DUALSDS_3_INST_CLOCK_DISABLE - Disable DUALSDS_3_INST's clocks
- ***************************************************************************/
-/* CLKGEN :: DUALSDS_3_INST_CLOCK_DISABLE :: reserved0 [31:02] */
-#define BCHP_CLKGEN_DUALSDS_3_INST_CLOCK_DISABLE_reserved0_MASK 0xfffffffc
-#define BCHP_CLKGEN_DUALSDS_3_INST_CLOCK_DISABLE_reserved0_SHIFT 2
-
-/* CLKGEN :: DUALSDS_3_INST_CLOCK_DISABLE :: DISABLE_SDS3RCVR1_108_PRESPMBALANCE_CLOCK [01:01] */
-#define BCHP_CLKGEN_DUALSDS_3_INST_CLOCK_DISABLE_DISABLE_SDS3RCVR1_108_PRESPMBALANCE_CLOCK_MASK 0x00000002
-#define BCHP_CLKGEN_DUALSDS_3_INST_CLOCK_DISABLE_DISABLE_SDS3RCVR1_108_PRESPMBALANCE_CLOCK_SHIFT 1
-#define BCHP_CLKGEN_DUALSDS_3_INST_CLOCK_DISABLE_DISABLE_SDS3RCVR1_108_PRESPMBALANCE_CLOCK_DEFAULT 0x00000000
-
-/* CLKGEN :: DUALSDS_3_INST_CLOCK_DISABLE :: DISABLE_SDS3RCVR0_108_PRESPMBALANCE_CLOCK [00:00] */
-#define BCHP_CLKGEN_DUALSDS_3_INST_CLOCK_DISABLE_DISABLE_SDS3RCVR0_108_PRESPMBALANCE_CLOCK_MASK 0x00000001
-#define BCHP_CLKGEN_DUALSDS_3_INST_CLOCK_DISABLE_DISABLE_SDS3RCVR0_108_PRESPMBALANCE_CLOCK_SHIFT 0
-#define BCHP_CLKGEN_DUALSDS_3_INST_CLOCK_DISABLE_DISABLE_SDS3RCVR0_108_PRESPMBALANCE_CLOCK_DEFAULT 0x00000000
-
-/***************************************************************************
- *DUALSDS_3_INST_CLOCK_DISABLE_STATUS - Clock Disable Status
- ***************************************************************************/
-/* CLKGEN :: DUALSDS_3_INST_CLOCK_DISABLE_STATUS :: reserved0 [31:02] */
-#define BCHP_CLKGEN_DUALSDS_3_INST_CLOCK_DISABLE_STATUS_reserved0_MASK 0xfffffffc
-#define BCHP_CLKGEN_DUALSDS_3_INST_CLOCK_DISABLE_STATUS_reserved0_SHIFT 2
-
-/* CLKGEN :: DUALSDS_3_INST_CLOCK_DISABLE_STATUS :: DISABLE_SDS3RCVR1_108_PRESPMBALANCE_CLOCK_STATUS [01:01] */
-#define BCHP_CLKGEN_DUALSDS_3_INST_CLOCK_DISABLE_STATUS_DISABLE_SDS3RCVR1_108_PRESPMBALANCE_CLOCK_STATUS_MASK 0x00000002
-#define BCHP_CLKGEN_DUALSDS_3_INST_CLOCK_DISABLE_STATUS_DISABLE_SDS3RCVR1_108_PRESPMBALANCE_CLOCK_STATUS_SHIFT 1
-
-/* CLKGEN :: DUALSDS_3_INST_CLOCK_DISABLE_STATUS :: DISABLE_SDS3RCVR0_108_PRESPMBALANCE_CLOCK_STATUS [00:00] */
-#define BCHP_CLKGEN_DUALSDS_3_INST_CLOCK_DISABLE_STATUS_DISABLE_SDS3RCVR0_108_PRESPMBALANCE_CLOCK_STATUS_MASK 0x00000001
-#define BCHP_CLKGEN_DUALSDS_3_INST_CLOCK_DISABLE_STATUS_DISABLE_SDS3RCVR0_108_PRESPMBALANCE_CLOCK_STATUS_SHIFT 0
-
-/***************************************************************************
- *DUALSDS_3_INST_CLOCK_ENABLE_CH0 - Dualsds 3 inst clock enable ch0
- ***************************************************************************/
-/* CLKGEN :: DUALSDS_3_INST_CLOCK_ENABLE_CH0 :: reserved0 [31:02] */
-#define BCHP_CLKGEN_DUALSDS_3_INST_CLOCK_ENABLE_CH0_reserved0_MASK 0xfffffffc
-#define BCHP_CLKGEN_DUALSDS_3_INST_CLOCK_ENABLE_CH0_reserved0_SHIFT 2
-
-/* CLKGEN :: DUALSDS_3_INST_CLOCK_ENABLE_CH0 :: SDS3_54_CLOCK_ENABLE_CH0 [01:01] */
-#define BCHP_CLKGEN_DUALSDS_3_INST_CLOCK_ENABLE_CH0_SDS3_54_CLOCK_ENABLE_CH0_MASK 0x00000002
-#define BCHP_CLKGEN_DUALSDS_3_INST_CLOCK_ENABLE_CH0_SDS3_54_CLOCK_ENABLE_CH0_SHIFT 1
-#define BCHP_CLKGEN_DUALSDS_3_INST_CLOCK_ENABLE_CH0_SDS3_54_CLOCK_ENABLE_CH0_DEFAULT 0x00000001
-
-/* CLKGEN :: DUALSDS_3_INST_CLOCK_ENABLE_CH0 :: SDS3_108_CLOCK_ENABLE_CH0 [00:00] */
-#define BCHP_CLKGEN_DUALSDS_3_INST_CLOCK_ENABLE_CH0_SDS3_108_CLOCK_ENABLE_CH0_MASK 0x00000001
-#define BCHP_CLKGEN_DUALSDS_3_INST_CLOCK_ENABLE_CH0_SDS3_108_CLOCK_ENABLE_CH0_SHIFT 0
-#define BCHP_CLKGEN_DUALSDS_3_INST_CLOCK_ENABLE_CH0_SDS3_108_CLOCK_ENABLE_CH0_DEFAULT 0x00000001
-
-/***************************************************************************
- *DUALSDS_3_INST_CLOCK_ENABLE_CH0_STATUS - Clock Enable Status
- ***************************************************************************/
-/* CLKGEN :: DUALSDS_3_INST_CLOCK_ENABLE_CH0_STATUS :: reserved0 [31:02] */
-#define BCHP_CLKGEN_DUALSDS_3_INST_CLOCK_ENABLE_CH0_STATUS_reserved0_MASK 0xfffffffc
-#define BCHP_CLKGEN_DUALSDS_3_INST_CLOCK_ENABLE_CH0_STATUS_reserved0_SHIFT 2
-
-/* CLKGEN :: DUALSDS_3_INST_CLOCK_ENABLE_CH0_STATUS :: SDS3_54_CLOCK_ENABLE_CH0_STATUS [01:01] */
-#define BCHP_CLKGEN_DUALSDS_3_INST_CLOCK_ENABLE_CH0_STATUS_SDS3_54_CLOCK_ENABLE_CH0_STATUS_MASK 0x00000002
-#define BCHP_CLKGEN_DUALSDS_3_INST_CLOCK_ENABLE_CH0_STATUS_SDS3_54_CLOCK_ENABLE_CH0_STATUS_SHIFT 1
-
-/* CLKGEN :: DUALSDS_3_INST_CLOCK_ENABLE_CH0_STATUS :: SDS3_108_CLOCK_ENABLE_CH0_STATUS [00:00] */
-#define BCHP_CLKGEN_DUALSDS_3_INST_CLOCK_ENABLE_CH0_STATUS_SDS3_108_CLOCK_ENABLE_CH0_STATUS_MASK 0x00000001
-#define BCHP_CLKGEN_DUALSDS_3_INST_CLOCK_ENABLE_CH0_STATUS_SDS3_108_CLOCK_ENABLE_CH0_STATUS_SHIFT 0
-
-/***************************************************************************
- *DUALSDS_3_INST_CLOCK_ENABLE_CH1 - Dualsds 3 inst clock enable ch1
- ***************************************************************************/
-/* CLKGEN :: DUALSDS_3_INST_CLOCK_ENABLE_CH1 :: reserved0 [31:02] */
-#define BCHP_CLKGEN_DUALSDS_3_INST_CLOCK_ENABLE_CH1_reserved0_MASK 0xfffffffc
-#define BCHP_CLKGEN_DUALSDS_3_INST_CLOCK_ENABLE_CH1_reserved0_SHIFT 2
-
-/* CLKGEN :: DUALSDS_3_INST_CLOCK_ENABLE_CH1 :: SDS3_54_CLOCK_ENABLE_CH1 [01:01] */
-#define BCHP_CLKGEN_DUALSDS_3_INST_CLOCK_ENABLE_CH1_SDS3_54_CLOCK_ENABLE_CH1_MASK 0x00000002
-#define BCHP_CLKGEN_DUALSDS_3_INST_CLOCK_ENABLE_CH1_SDS3_54_CLOCK_ENABLE_CH1_SHIFT 1
-#define BCHP_CLKGEN_DUALSDS_3_INST_CLOCK_ENABLE_CH1_SDS3_54_CLOCK_ENABLE_CH1_DEFAULT 0x00000001
-
-/* CLKGEN :: DUALSDS_3_INST_CLOCK_ENABLE_CH1 :: SDS3_108_CLOCK_ENABLE_CH1 [00:00] */
-#define BCHP_CLKGEN_DUALSDS_3_INST_CLOCK_ENABLE_CH1_SDS3_108_CLOCK_ENABLE_CH1_MASK 0x00000001
-#define BCHP_CLKGEN_DUALSDS_3_INST_CLOCK_ENABLE_CH1_SDS3_108_CLOCK_ENABLE_CH1_SHIFT 0
-#define BCHP_CLKGEN_DUALSDS_3_INST_CLOCK_ENABLE_CH1_SDS3_108_CLOCK_ENABLE_CH1_DEFAULT 0x00000001
-
-/***************************************************************************
- *DUALSDS_3_INST_CLOCK_ENABLE_CH1_STATUS - Clock Enable Status
- ***************************************************************************/
-/* CLKGEN :: DUALSDS_3_INST_CLOCK_ENABLE_CH1_STATUS :: reserved0 [31:02] */
-#define BCHP_CLKGEN_DUALSDS_3_INST_CLOCK_ENABLE_CH1_STATUS_reserved0_MASK 0xfffffffc
-#define BCHP_CLKGEN_DUALSDS_3_INST_CLOCK_ENABLE_CH1_STATUS_reserved0_SHIFT 2
-
-/* CLKGEN :: DUALSDS_3_INST_CLOCK_ENABLE_CH1_STATUS :: SDS3_54_CLOCK_ENABLE_CH1_STATUS [01:01] */
-#define BCHP_CLKGEN_DUALSDS_3_INST_CLOCK_ENABLE_CH1_STATUS_SDS3_54_CLOCK_ENABLE_CH1_STATUS_MASK 0x00000002
-#define BCHP_CLKGEN_DUALSDS_3_INST_CLOCK_ENABLE_CH1_STATUS_SDS3_54_CLOCK_ENABLE_CH1_STATUS_SHIFT 1
-
-/* CLKGEN :: DUALSDS_3_INST_CLOCK_ENABLE_CH1_STATUS :: SDS3_108_CLOCK_ENABLE_CH1_STATUS [00:00] */
-#define BCHP_CLKGEN_DUALSDS_3_INST_CLOCK_ENABLE_CH1_STATUS_SDS3_108_CLOCK_ENABLE_CH1_STATUS_MASK 0x00000001
-#define BCHP_CLKGEN_DUALSDS_3_INST_CLOCK_ENABLE_CH1_STATUS_SDS3_108_CLOCK_ENABLE_CH1_STATUS_SHIFT 0
-
-/***************************************************************************
- *DUALSDS_3_INST_EN_CH0 - Dualsds 3 inst en ch0
- ***************************************************************************/
-/* CLKGEN :: DUALSDS_3_INST_EN_CH0 :: reserved0 [31:01] */
-#define BCHP_CLKGEN_DUALSDS_3_INST_EN_CH0_reserved0_MASK 0xfffffffe
-#define BCHP_CLKGEN_DUALSDS_3_INST_EN_CH0_reserved0_SHIFT 1
-
-/* CLKGEN :: DUALSDS_3_INST_EN_CH0 :: SDS3_PLL_CLOCK_EN_CH0 [00:00] */
-#define BCHP_CLKGEN_DUALSDS_3_INST_EN_CH0_SDS3_PLL_CLOCK_EN_CH0_MASK 0x00000001
-#define BCHP_CLKGEN_DUALSDS_3_INST_EN_CH0_SDS3_PLL_CLOCK_EN_CH0_SHIFT 0
-#define BCHP_CLKGEN_DUALSDS_3_INST_EN_CH0_SDS3_PLL_CLOCK_EN_CH0_DEFAULT 0x00000001
-
-/***************************************************************************
- *DUALSDS_3_INST_EN_CH1 - Dualsds 3 inst en ch1
- ***************************************************************************/
-/* CLKGEN :: DUALSDS_3_INST_EN_CH1 :: reserved0 [31:01] */
-#define BCHP_CLKGEN_DUALSDS_3_INST_EN_CH1_reserved0_MASK 0xfffffffe
-#define BCHP_CLKGEN_DUALSDS_3_INST_EN_CH1_reserved0_SHIFT 1
-
-/* CLKGEN :: DUALSDS_3_INST_EN_CH1 :: SDS3_PLL_CLOCK_EN_CH1 [00:00] */
-#define BCHP_CLKGEN_DUALSDS_3_INST_EN_CH1_SDS3_PLL_CLOCK_EN_CH1_MASK 0x00000001
-#define BCHP_CLKGEN_DUALSDS_3_INST_EN_CH1_SDS3_PLL_CLOCK_EN_CH1_SHIFT 0
-#define BCHP_CLKGEN_DUALSDS_3_INST_EN_CH1_SDS3_PLL_CLOCK_EN_CH1_DEFAULT 0x00000001
-
-/***************************************************************************
- *DUALSDS_3_INST_OBSERVE_CLOCK - Dualsds 3 inst observe clock
- ***************************************************************************/
-/* CLKGEN :: DUALSDS_3_INST_OBSERVE_CLOCK :: reserved0 [31:24] */
-#define BCHP_CLKGEN_DUALSDS_3_INST_OBSERVE_CLOCK_reserved0_MASK 0xff000000
-#define BCHP_CLKGEN_DUALSDS_3_INST_OBSERVE_CLOCK_reserved0_SHIFT 24
-
-/* CLKGEN :: DUALSDS_3_INST_OBSERVE_CLOCK :: SDS3TFEC1_ENABLE_OBSERVE_CLOCK [23:23] */
-#define BCHP_CLKGEN_DUALSDS_3_INST_OBSERVE_CLOCK_SDS3TFEC1_ENABLE_OBSERVE_CLOCK_MASK 0x00800000
-#define BCHP_CLKGEN_DUALSDS_3_INST_OBSERVE_CLOCK_SDS3TFEC1_ENABLE_OBSERVE_CLOCK_SHIFT 23
-#define BCHP_CLKGEN_DUALSDS_3_INST_OBSERVE_CLOCK_SDS3TFEC1_ENABLE_OBSERVE_CLOCK_DEFAULT 0x00000000
-
-/* CLKGEN :: DUALSDS_3_INST_OBSERVE_CLOCK :: SDS3TFEC1_ENABLE_DIVIDER_OBSERVE_CLOCK [22:22] */
-#define BCHP_CLKGEN_DUALSDS_3_INST_OBSERVE_CLOCK_SDS3TFEC1_ENABLE_DIVIDER_OBSERVE_CLOCK_MASK 0x00400000
-#define BCHP_CLKGEN_DUALSDS_3_INST_OBSERVE_CLOCK_SDS3TFEC1_ENABLE_DIVIDER_OBSERVE_CLOCK_SHIFT 22
-#define BCHP_CLKGEN_DUALSDS_3_INST_OBSERVE_CLOCK_SDS3TFEC1_ENABLE_DIVIDER_OBSERVE_CLOCK_DEFAULT 0x00000000
-
-/* CLKGEN :: DUALSDS_3_INST_OBSERVE_CLOCK :: SDS3TFEC1_CONTROL_OBSERVE_CLOCK [21:18] */
-#define BCHP_CLKGEN_DUALSDS_3_INST_OBSERVE_CLOCK_SDS3TFEC1_CONTROL_OBSERVE_CLOCK_MASK 0x003c0000
-#define BCHP_CLKGEN_DUALSDS_3_INST_OBSERVE_CLOCK_SDS3TFEC1_CONTROL_OBSERVE_CLOCK_SHIFT 18
-#define BCHP_CLKGEN_DUALSDS_3_INST_OBSERVE_CLOCK_SDS3TFEC1_CONTROL_OBSERVE_CLOCK_DEFAULT 0x00000000
-
-/* CLKGEN :: DUALSDS_3_INST_OBSERVE_CLOCK :: SDS3TFEC0_ENABLE_OBSERVE_CLOCK [17:17] */
-#define BCHP_CLKGEN_DUALSDS_3_INST_OBSERVE_CLOCK_SDS3TFEC0_ENABLE_OBSERVE_CLOCK_MASK 0x00020000
-#define BCHP_CLKGEN_DUALSDS_3_INST_OBSERVE_CLOCK_SDS3TFEC0_ENABLE_OBSERVE_CLOCK_SHIFT 17
-#define BCHP_CLKGEN_DUALSDS_3_INST_OBSERVE_CLOCK_SDS3TFEC0_ENABLE_OBSERVE_CLOCK_DEFAULT 0x00000000
-
-/* CLKGEN :: DUALSDS_3_INST_OBSERVE_CLOCK :: SDS3TFEC0_ENABLE_DIVIDER_OBSERVE_CLOCK [16:16] */
-#define BCHP_CLKGEN_DUALSDS_3_INST_OBSERVE_CLOCK_SDS3TFEC0_ENABLE_DIVIDER_OBSERVE_CLOCK_MASK 0x00010000
-#define BCHP_CLKGEN_DUALSDS_3_INST_OBSERVE_CLOCK_SDS3TFEC0_ENABLE_DIVIDER_OBSERVE_CLOCK_SHIFT 16
-#define BCHP_CLKGEN_DUALSDS_3_INST_OBSERVE_CLOCK_SDS3TFEC0_ENABLE_DIVIDER_OBSERVE_CLOCK_DEFAULT 0x00000000
-
-/* CLKGEN :: DUALSDS_3_INST_OBSERVE_CLOCK :: SDS3TFEC0_CONTROL_OBSERVE_CLOCK [15:12] */
-#define BCHP_CLKGEN_DUALSDS_3_INST_OBSERVE_CLOCK_SDS3TFEC0_CONTROL_OBSERVE_CLOCK_MASK 0x0000f000
-#define BCHP_CLKGEN_DUALSDS_3_INST_OBSERVE_CLOCK_SDS3TFEC0_CONTROL_OBSERVE_CLOCK_SHIFT 12
-#define BCHP_CLKGEN_DUALSDS_3_INST_OBSERVE_CLOCK_SDS3TFEC0_CONTROL_OBSERVE_CLOCK_DEFAULT 0x00000000
-
-/* CLKGEN :: DUALSDS_3_INST_OBSERVE_CLOCK :: SDS3RCVR1_ENABLE_OBSERVE_CLOCK [11:11] */
-#define BCHP_CLKGEN_DUALSDS_3_INST_OBSERVE_CLOCK_SDS3RCVR1_ENABLE_OBSERVE_CLOCK_MASK 0x00000800
-#define BCHP_CLKGEN_DUALSDS_3_INST_OBSERVE_CLOCK_SDS3RCVR1_ENABLE_OBSERVE_CLOCK_SHIFT 11
-#define BCHP_CLKGEN_DUALSDS_3_INST_OBSERVE_CLOCK_SDS3RCVR1_ENABLE_OBSERVE_CLOCK_DEFAULT 0x00000000
-
-/* CLKGEN :: DUALSDS_3_INST_OBSERVE_CLOCK :: SDS3RCVR1_ENABLE_DIVIDER_OBSERVE_CLOCK [10:10] */
-#define BCHP_CLKGEN_DUALSDS_3_INST_OBSERVE_CLOCK_SDS3RCVR1_ENABLE_DIVIDER_OBSERVE_CLOCK_MASK 0x00000400
-#define BCHP_CLKGEN_DUALSDS_3_INST_OBSERVE_CLOCK_SDS3RCVR1_ENABLE_DIVIDER_OBSERVE_CLOCK_SHIFT 10
-#define BCHP_CLKGEN_DUALSDS_3_INST_OBSERVE_CLOCK_SDS3RCVR1_ENABLE_DIVIDER_OBSERVE_CLOCK_DEFAULT 0x00000000
-
-/* CLKGEN :: DUALSDS_3_INST_OBSERVE_CLOCK :: SDS3RCVR1_CONTROL_OBSERVE_CLOCK [09:06] */
-#define BCHP_CLKGEN_DUALSDS_3_INST_OBSERVE_CLOCK_SDS3RCVR1_CONTROL_OBSERVE_CLOCK_MASK 0x000003c0
-#define BCHP_CLKGEN_DUALSDS_3_INST_OBSERVE_CLOCK_SDS3RCVR1_CONTROL_OBSERVE_CLOCK_SHIFT 6
-#define BCHP_CLKGEN_DUALSDS_3_INST_OBSERVE_CLOCK_SDS3RCVR1_CONTROL_OBSERVE_CLOCK_DEFAULT 0x00000000
-
-/* CLKGEN :: DUALSDS_3_INST_OBSERVE_CLOCK :: SDS3RCVR0_ENABLE_OBSERVE_CLOCK [05:05] */
-#define BCHP_CLKGEN_DUALSDS_3_INST_OBSERVE_CLOCK_SDS3RCVR0_ENABLE_OBSERVE_CLOCK_MASK 0x00000020
-#define BCHP_CLKGEN_DUALSDS_3_INST_OBSERVE_CLOCK_SDS3RCVR0_ENABLE_OBSERVE_CLOCK_SHIFT 5
-#define BCHP_CLKGEN_DUALSDS_3_INST_OBSERVE_CLOCK_SDS3RCVR0_ENABLE_OBSERVE_CLOCK_DEFAULT 0x00000000
-
-/* CLKGEN :: DUALSDS_3_INST_OBSERVE_CLOCK :: SDS3RCVR0_ENABLE_DIVIDER_OBSERVE_CLOCK [04:04] */
-#define BCHP_CLKGEN_DUALSDS_3_INST_OBSERVE_CLOCK_SDS3RCVR0_ENABLE_DIVIDER_OBSERVE_CLOCK_MASK 0x00000010
-#define BCHP_CLKGEN_DUALSDS_3_INST_OBSERVE_CLOCK_SDS3RCVR0_ENABLE_DIVIDER_OBSERVE_CLOCK_SHIFT 4
-#define BCHP_CLKGEN_DUALSDS_3_INST_OBSERVE_CLOCK_SDS3RCVR0_ENABLE_DIVIDER_OBSERVE_CLOCK_DEFAULT 0x00000000
-
-/* CLKGEN :: DUALSDS_3_INST_OBSERVE_CLOCK :: SDS3RCVR0_CONTROL_OBSERVE_CLOCK [03:00] */
-#define BCHP_CLKGEN_DUALSDS_3_INST_OBSERVE_CLOCK_SDS3RCVR0_CONTROL_OBSERVE_CLOCK_MASK 0x0000000f
-#define BCHP_CLKGEN_DUALSDS_3_INST_OBSERVE_CLOCK_SDS3RCVR0_CONTROL_OBSERVE_CLOCK_SHIFT 0
-#define BCHP_CLKGEN_DUALSDS_3_INST_OBSERVE_CLOCK_SDS3RCVR0_CONTROL_OBSERVE_CLOCK_DEFAULT 0x00000000
-
-/***************************************************************************
- *DUALSDS_3_INST_PLL_CLOCK_EN - Dualsds 3 inst pll clock en
- ***************************************************************************/
-/* CLKGEN :: DUALSDS_3_INST_PLL_CLOCK_EN :: reserved0 [31:02] */
-#define BCHP_CLKGEN_DUALSDS_3_INST_PLL_CLOCK_EN_reserved0_MASK 0xfffffffc
-#define BCHP_CLKGEN_DUALSDS_3_INST_PLL_CLOCK_EN_reserved0_SHIFT 2
-
-/* CLKGEN :: DUALSDS_3_INST_PLL_CLOCK_EN :: SDS3TFEC1_PLL_CLOCK_EN [01:01] */
-#define BCHP_CLKGEN_DUALSDS_3_INST_PLL_CLOCK_EN_SDS3TFEC1_PLL_CLOCK_EN_MASK 0x00000002
-#define BCHP_CLKGEN_DUALSDS_3_INST_PLL_CLOCK_EN_SDS3TFEC1_PLL_CLOCK_EN_SHIFT 1
-#define BCHP_CLKGEN_DUALSDS_3_INST_PLL_CLOCK_EN_SDS3TFEC1_PLL_CLOCK_EN_DEFAULT 0x00000001
-
-/* CLKGEN :: DUALSDS_3_INST_PLL_CLOCK_EN :: SDS3TFEC0_PLL_CLOCK_EN [00:00] */
-#define BCHP_CLKGEN_DUALSDS_3_INST_PLL_CLOCK_EN_SDS3TFEC0_PLL_CLOCK_EN_MASK 0x00000001
-#define BCHP_CLKGEN_DUALSDS_3_INST_PLL_CLOCK_EN_SDS3TFEC0_PLL_CLOCK_EN_SHIFT 0
-#define BCHP_CLKGEN_DUALSDS_3_INST_PLL_CLOCK_EN_SDS3TFEC0_PLL_CLOCK_EN_DEFAULT 0x00000001
-
-/***************************************************************************
- *DUALSDS_3_INST_SEL - Dualsds 3 inst sel
- ***************************************************************************/
-/* CLKGEN :: DUALSDS_3_INST_SEL :: reserved0 [31:02] */
-#define BCHP_CLKGEN_DUALSDS_3_INST_SEL_reserved0_MASK 0xfffffffc
-#define BCHP_CLKGEN_DUALSDS_3_INST_SEL_reserved0_SHIFT 2
-
-/* CLKGEN :: DUALSDS_3_INST_SEL :: SDS3_LV_CLK_PLL_SRC_SEL [01:01] */
-#define BCHP_CLKGEN_DUALSDS_3_INST_SEL_SDS3_LV_CLK_PLL_SRC_SEL_MASK 0x00000002
-#define BCHP_CLKGEN_DUALSDS_3_INST_SEL_SDS3_LV_CLK_PLL_SRC_SEL_SHIFT 1
-#define BCHP_CLKGEN_DUALSDS_3_INST_SEL_SDS3_LV_CLK_PLL_SRC_SEL_DEFAULT 0x00000000
-
-/* CLKGEN :: DUALSDS_3_INST_SEL :: SDS3_CHAN_I_CLK_240_LV_CLK_PLL_SRC_SEL [00:00] */
-#define BCHP_CLKGEN_DUALSDS_3_INST_SEL_SDS3_CHAN_I_CLK_240_LV_CLK_PLL_SRC_SEL_MASK 0x00000001
-#define BCHP_CLKGEN_DUALSDS_3_INST_SEL_SDS3_CHAN_I_CLK_240_LV_CLK_PLL_SRC_SEL_SHIFT 0
-#define BCHP_CLKGEN_DUALSDS_3_INST_SEL_SDS3_CHAN_I_CLK_240_LV_CLK_PLL_SRC_SEL_DEFAULT 0x00000000
-
-/***************************************************************************
- *DVP_HR_INST_CLOCK_DISABLE - Disable DVP_HR_INST's clocks
- ***************************************************************************/
-/* CLKGEN :: DVP_HR_INST_CLOCK_DISABLE :: reserved0 [31:01] */
-#define BCHP_CLKGEN_DVP_HR_INST_CLOCK_DISABLE_reserved0_MASK 0xfffffffe
-#define BCHP_CLKGEN_DVP_HR_INST_CLOCK_DISABLE_reserved0_SHIFT 1
-
-/* CLKGEN :: DVP_HR_INST_CLOCK_DISABLE :: DISABLE_DVPHR_ALWAYSON_CLOCK [00:00] */
-#define BCHP_CLKGEN_DVP_HR_INST_CLOCK_DISABLE_DISABLE_DVPHR_ALWAYSON_CLOCK_MASK 0x00000001
-#define BCHP_CLKGEN_DVP_HR_INST_CLOCK_DISABLE_DISABLE_DVPHR_ALWAYSON_CLOCK_SHIFT 0
-#define BCHP_CLKGEN_DVP_HR_INST_CLOCK_DISABLE_DISABLE_DVPHR_ALWAYSON_CLOCK_DEFAULT 0x00000000
-
-/***************************************************************************
- *DVP_HR_INST_CLOCK_DISABLE_STATUS - Clock Disable Status
- ***************************************************************************/
-/* CLKGEN :: DVP_HR_INST_CLOCK_DISABLE_STATUS :: reserved0 [31:01] */
-#define BCHP_CLKGEN_DVP_HR_INST_CLOCK_DISABLE_STATUS_reserved0_MASK 0xfffffffe
-#define BCHP_CLKGEN_DVP_HR_INST_CLOCK_DISABLE_STATUS_reserved0_SHIFT 1
-
-/* CLKGEN :: DVP_HR_INST_CLOCK_DISABLE_STATUS :: DISABLE_DVPHR_ALWAYSON_CLOCK_STATUS [00:00] */
-#define BCHP_CLKGEN_DVP_HR_INST_CLOCK_DISABLE_STATUS_DISABLE_DVPHR_ALWAYSON_CLOCK_STATUS_MASK 0x00000001
-#define BCHP_CLKGEN_DVP_HR_INST_CLOCK_DISABLE_STATUS_DISABLE_DVPHR_ALWAYSON_CLOCK_STATUS_SHIFT 0
-
-/***************************************************************************
- *DVP_HR_INST_CLOCK_ENABLE - Dvp hr inst clock enable
- ***************************************************************************/
-/* CLKGEN :: DVP_HR_INST_CLOCK_ENABLE :: reserved0 [31:03] */
-#define BCHP_CLKGEN_DVP_HR_INST_CLOCK_ENABLE_reserved0_MASK 0xfffffff8
-#define BCHP_CLKGEN_DVP_HR_INST_CLOCK_ENABLE_reserved0_SHIFT 3
-
-/* CLKGEN :: DVP_HR_INST_CLOCK_ENABLE :: DVPHR_HD_DVI_CLOCK_ENABLE [02:02] */
-#define BCHP_CLKGEN_DVP_HR_INST_CLOCK_ENABLE_DVPHR_HD_DVI_CLOCK_ENABLE_MASK 0x00000004
-#define BCHP_CLKGEN_DVP_HR_INST_CLOCK_ENABLE_DVPHR_HD_DVI_CLOCK_ENABLE_SHIFT 2
-#define BCHP_CLKGEN_DVP_HR_INST_CLOCK_ENABLE_DVPHR_HD_DVI_CLOCK_ENABLE_DEFAULT 0x00000001
-
-/* CLKGEN :: DVP_HR_INST_CLOCK_ENABLE :: DVPHR_BVB_324_CLOCK_ENABLE [01:01] */
-#define BCHP_CLKGEN_DVP_HR_INST_CLOCK_ENABLE_DVPHR_BVB_324_CLOCK_ENABLE_MASK 0x00000002
-#define BCHP_CLKGEN_DVP_HR_INST_CLOCK_ENABLE_DVPHR_BVB_324_CLOCK_ENABLE_SHIFT 1
-#define BCHP_CLKGEN_DVP_HR_INST_CLOCK_ENABLE_DVPHR_BVB_324_CLOCK_ENABLE_DEFAULT 0x00000001
-
-/* CLKGEN :: DVP_HR_INST_CLOCK_ENABLE :: DVPHR_54_CLOCK_ENABLE [00:00] */
-#define BCHP_CLKGEN_DVP_HR_INST_CLOCK_ENABLE_DVPHR_54_CLOCK_ENABLE_MASK 0x00000001
-#define BCHP_CLKGEN_DVP_HR_INST_CLOCK_ENABLE_DVPHR_54_CLOCK_ENABLE_SHIFT 0
-#define BCHP_CLKGEN_DVP_HR_INST_CLOCK_ENABLE_DVPHR_54_CLOCK_ENABLE_DEFAULT 0x00000001
-
-/***************************************************************************
- *DVP_HR_INST_CLOCK_ENABLE0 - Dvp hr inst clock enable0
- ***************************************************************************/
-/* CLKGEN :: DVP_HR_INST_CLOCK_ENABLE0 :: reserved0 [31:01] */
-#define BCHP_CLKGEN_DVP_HR_INST_CLOCK_ENABLE0_reserved0_MASK 0xfffffffe
-#define BCHP_CLKGEN_DVP_HR_INST_CLOCK_ENABLE0_reserved0_SHIFT 1
-
-/* CLKGEN :: DVP_HR_INST_CLOCK_ENABLE0 :: DVPHR_108_CLOCK_ENABLE0 [00:00] */
-#define BCHP_CLKGEN_DVP_HR_INST_CLOCK_ENABLE0_DVPHR_108_CLOCK_ENABLE0_MASK 0x00000001
-#define BCHP_CLKGEN_DVP_HR_INST_CLOCK_ENABLE0_DVPHR_108_CLOCK_ENABLE0_SHIFT 0
-#define BCHP_CLKGEN_DVP_HR_INST_CLOCK_ENABLE0_DVPHR_108_CLOCK_ENABLE0_DEFAULT 0x00000001
-
-/***************************************************************************
- *DVP_HR_INST_CLOCK_ENABLE0_STATUS - Clock Enable Status
- ***************************************************************************/
-/* CLKGEN :: DVP_HR_INST_CLOCK_ENABLE0_STATUS :: reserved0 [31:01] */
-#define BCHP_CLKGEN_DVP_HR_INST_CLOCK_ENABLE0_STATUS_reserved0_MASK 0xfffffffe
-#define BCHP_CLKGEN_DVP_HR_INST_CLOCK_ENABLE0_STATUS_reserved0_SHIFT 1
-
-/* CLKGEN :: DVP_HR_INST_CLOCK_ENABLE0_STATUS :: DVPHR_108_CLOCK_ENABLE0_STATUS [00:00] */
-#define BCHP_CLKGEN_DVP_HR_INST_CLOCK_ENABLE0_STATUS_DVPHR_108_CLOCK_ENABLE0_STATUS_MASK 0x00000001
-#define BCHP_CLKGEN_DVP_HR_INST_CLOCK_ENABLE0_STATUS_DVPHR_108_CLOCK_ENABLE0_STATUS_SHIFT 0
-
-/***************************************************************************
- *DVP_HR_INST_CLOCK_ENABLE_STATUS - Clock Enable Status
- ***************************************************************************/
-/* CLKGEN :: DVP_HR_INST_CLOCK_ENABLE_STATUS :: reserved0 [31:03] */
-#define BCHP_CLKGEN_DVP_HR_INST_CLOCK_ENABLE_STATUS_reserved0_MASK 0xfffffff8
-#define BCHP_CLKGEN_DVP_HR_INST_CLOCK_ENABLE_STATUS_reserved0_SHIFT 3
-
-/* CLKGEN :: DVP_HR_INST_CLOCK_ENABLE_STATUS :: DVPHR_HD_DVI_CLOCK_ENABLE_STATUS [02:02] */
-#define BCHP_CLKGEN_DVP_HR_INST_CLOCK_ENABLE_STATUS_DVPHR_HD_DVI_CLOCK_ENABLE_STATUS_MASK 0x00000004
-#define BCHP_CLKGEN_DVP_HR_INST_CLOCK_ENABLE_STATUS_DVPHR_HD_DVI_CLOCK_ENABLE_STATUS_SHIFT 2
-
-/* CLKGEN :: DVP_HR_INST_CLOCK_ENABLE_STATUS :: DVPHR_BVB_324_CLOCK_ENABLE_STATUS [01:01] */
-#define BCHP_CLKGEN_DVP_HR_INST_CLOCK_ENABLE_STATUS_DVPHR_BVB_324_CLOCK_ENABLE_STATUS_MASK 0x00000002
-#define BCHP_CLKGEN_DVP_HR_INST_CLOCK_ENABLE_STATUS_DVPHR_BVB_324_CLOCK_ENABLE_STATUS_SHIFT 1
-
-/* CLKGEN :: DVP_HR_INST_CLOCK_ENABLE_STATUS :: DVPHR_54_CLOCK_ENABLE_STATUS [00:00] */
-#define BCHP_CLKGEN_DVP_HR_INST_CLOCK_ENABLE_STATUS_DVPHR_54_CLOCK_ENABLE_STATUS_MASK 0x00000001
-#define BCHP_CLKGEN_DVP_HR_INST_CLOCK_ENABLE_STATUS_DVPHR_54_CLOCK_ENABLE_STATUS_SHIFT 0
-
-/***************************************************************************
- *DVP_HR_INST_OBSERVE_CLOCK - Dvp hr inst observe clock
- ***************************************************************************/
-/* CLKGEN :: DVP_HR_INST_OBSERVE_CLOCK :: reserved0 [31:06] */
-#define BCHP_CLKGEN_DVP_HR_INST_OBSERVE_CLOCK_reserved0_MASK 0xffffffc0
-#define BCHP_CLKGEN_DVP_HR_INST_OBSERVE_CLOCK_reserved0_SHIFT 6
-
-/* CLKGEN :: DVP_HR_INST_OBSERVE_CLOCK :: DVPHR_ENABLE_OBSERVE_CLOCK [05:05] */
-#define BCHP_CLKGEN_DVP_HR_INST_OBSERVE_CLOCK_DVPHR_ENABLE_OBSERVE_CLOCK_MASK 0x00000020
-#define BCHP_CLKGEN_DVP_HR_INST_OBSERVE_CLOCK_DVPHR_ENABLE_OBSERVE_CLOCK_SHIFT 5
-#define BCHP_CLKGEN_DVP_HR_INST_OBSERVE_CLOCK_DVPHR_ENABLE_OBSERVE_CLOCK_DEFAULT 0x00000000
-
-/* CLKGEN :: DVP_HR_INST_OBSERVE_CLOCK :: DVPHR_ENABLE_DIVIDER_OBSERVE_CLOCK [04:04] */
-#define BCHP_CLKGEN_DVP_HR_INST_OBSERVE_CLOCK_DVPHR_ENABLE_DIVIDER_OBSERVE_CLOCK_MASK 0x00000010
-#define BCHP_CLKGEN_DVP_HR_INST_OBSERVE_CLOCK_DVPHR_ENABLE_DIVIDER_OBSERVE_CLOCK_SHIFT 4
-#define BCHP_CLKGEN_DVP_HR_INST_OBSERVE_CLOCK_DVPHR_ENABLE_DIVIDER_OBSERVE_CLOCK_DEFAULT 0x00000000
-
-/* CLKGEN :: DVP_HR_INST_OBSERVE_CLOCK :: DVPHR_CONTROL_OBSERVE_CLOCK [03:00] */
-#define BCHP_CLKGEN_DVP_HR_INST_OBSERVE_CLOCK_DVPHR_CONTROL_OBSERVE_CLOCK_MASK 0x0000000f
-#define BCHP_CLKGEN_DVP_HR_INST_OBSERVE_CLOCK_DVPHR_CONTROL_OBSERVE_CLOCK_SHIFT 0
-#define BCHP_CLKGEN_DVP_HR_INST_OBSERVE_CLOCK_DVPHR_CONTROL_OBSERVE_CLOCK_DEFAULT 0x00000000
-
-/***************************************************************************
- *DVP_HT_DUAL_WRAPPER_INST_CLOCK_DISABLE - Disable DVP_HT_DUAL_WRAPPER_INST's clocks
- ***************************************************************************/
-/* CLKGEN :: DVP_HT_DUAL_WRAPPER_INST_CLOCK_DISABLE :: reserved0 [31:01] */
-#define BCHP_CLKGEN_DVP_HT_DUAL_WRAPPER_INST_CLOCK_DISABLE_reserved0_MASK 0xfffffffe
-#define BCHP_CLKGEN_DVP_HT_DUAL_WRAPPER_INST_CLOCK_DISABLE_reserved0_SHIFT 1
-
-/* CLKGEN :: DVP_HT_DUAL_WRAPPER_INST_CLOCK_DISABLE :: DISABLE_DVPHT_IIC_MASTER_CLOCK [00:00] */
-#define BCHP_CLKGEN_DVP_HT_DUAL_WRAPPER_INST_CLOCK_DISABLE_DISABLE_DVPHT_IIC_MASTER_CLOCK_MASK 0x00000001
-#define BCHP_CLKGEN_DVP_HT_DUAL_WRAPPER_INST_CLOCK_DISABLE_DISABLE_DVPHT_IIC_MASTER_CLOCK_SHIFT 0
-#define BCHP_CLKGEN_DVP_HT_DUAL_WRAPPER_INST_CLOCK_DISABLE_DISABLE_DVPHT_IIC_MASTER_CLOCK_DEFAULT 0x00000000
-
-/***************************************************************************
- *DVP_HT_DUAL_WRAPPER_INST_CLOCK_DISABLE_STATUS - Clock Disable Status
- ***************************************************************************/
-/* CLKGEN :: DVP_HT_DUAL_WRAPPER_INST_CLOCK_DISABLE_STATUS :: reserved0 [31:01] */
-#define BCHP_CLKGEN_DVP_HT_DUAL_WRAPPER_INST_CLOCK_DISABLE_STATUS_reserved0_MASK 0xfffffffe
-#define BCHP_CLKGEN_DVP_HT_DUAL_WRAPPER_INST_CLOCK_DISABLE_STATUS_reserved0_SHIFT 1
-
-/* CLKGEN :: DVP_HT_DUAL_WRAPPER_INST_CLOCK_DISABLE_STATUS :: DISABLE_DVPHT_IIC_MASTER_CLOCK_STATUS [00:00] */
-#define BCHP_CLKGEN_DVP_HT_DUAL_WRAPPER_INST_CLOCK_DISABLE_STATUS_DISABLE_DVPHT_IIC_MASTER_CLOCK_STATUS_MASK 0x00000001
-#define BCHP_CLKGEN_DVP_HT_DUAL_WRAPPER_INST_CLOCK_DISABLE_STATUS_DISABLE_DVPHT_IIC_MASTER_CLOCK_STATUS_SHIFT 0
-
-/***************************************************************************
- *DVP_HT_DUAL_WRAPPER_INST_CLOCK_ENABLE - Dvp ht dual wrapper inst clock enable
- ***************************************************************************/
-/* CLKGEN :: DVP_HT_DUAL_WRAPPER_INST_CLOCK_ENABLE :: reserved0 [31:07] */
-#define BCHP_CLKGEN_DVP_HT_DUAL_WRAPPER_INST_CLOCK_ENABLE_reserved0_MASK 0xffffff80
-#define BCHP_CLKGEN_DVP_HT_DUAL_WRAPPER_INST_CLOCK_ENABLE_reserved0_SHIFT 7
-
-/* CLKGEN :: DVP_HT_DUAL_WRAPPER_INST_CLOCK_ENABLE :: DVPHT_BVB_324_CLOCK_ENABLE [06:06] */
-#define BCHP_CLKGEN_DVP_HT_DUAL_WRAPPER_INST_CLOCK_ENABLE_DVPHT_BVB_324_CLOCK_ENABLE_MASK 0x00000040
-#define BCHP_CLKGEN_DVP_HT_DUAL_WRAPPER_INST_CLOCK_ENABLE_DVPHT_BVB_324_CLOCK_ENABLE_SHIFT 6
-#define BCHP_CLKGEN_DVP_HT_DUAL_WRAPPER_INST_CLOCK_ENABLE_DVPHT_BVB_324_CLOCK_ENABLE_DEFAULT 0x00000001
-
-/* CLKGEN :: DVP_HT_DUAL_WRAPPER_INST_CLOCK_ENABLE :: DVPHT_648_CLOCK_ENABLE [05:05] */
-#define BCHP_CLKGEN_DVP_HT_DUAL_WRAPPER_INST_CLOCK_ENABLE_DVPHT_648_CLOCK_ENABLE_MASK 0x00000020
-#define BCHP_CLKGEN_DVP_HT_DUAL_WRAPPER_INST_CLOCK_ENABLE_DVPHT_648_CLOCK_ENABLE_SHIFT 5
-#define BCHP_CLKGEN_DVP_HT_DUAL_WRAPPER_INST_CLOCK_ENABLE_DVPHT_648_CLOCK_ENABLE_DEFAULT 0x00000001
-
-/* CLKGEN :: DVP_HT_DUAL_WRAPPER_INST_CLOCK_ENABLE :: DVPHT_54_CLOCK_ENABLE [04:04] */
-#define BCHP_CLKGEN_DVP_HT_DUAL_WRAPPER_INST_CLOCK_ENABLE_DVPHT_54_CLOCK_ENABLE_MASK 0x00000010
-#define BCHP_CLKGEN_DVP_HT_DUAL_WRAPPER_INST_CLOCK_ENABLE_DVPHT_54_CLOCK_ENABLE_SHIFT 4
-#define BCHP_CLKGEN_DVP_HT_DUAL_WRAPPER_INST_CLOCK_ENABLE_DVPHT_54_CLOCK_ENABLE_DEFAULT 0x00000001
-
-/* CLKGEN :: DVP_HT_DUAL_WRAPPER_INST_CLOCK_ENABLE :: DVPHT_1_648_CLOCK_ENABLE [03:03] */
-#define BCHP_CLKGEN_DVP_HT_DUAL_WRAPPER_INST_CLOCK_ENABLE_DVPHT_1_648_CLOCK_ENABLE_MASK 0x00000008
-#define BCHP_CLKGEN_DVP_HT_DUAL_WRAPPER_INST_CLOCK_ENABLE_DVPHT_1_648_CLOCK_ENABLE_SHIFT 3
-#define BCHP_CLKGEN_DVP_HT_DUAL_WRAPPER_INST_CLOCK_ENABLE_DVPHT_1_648_CLOCK_ENABLE_DEFAULT 0x00000001
-
-/* CLKGEN :: DVP_HT_DUAL_WRAPPER_INST_CLOCK_ENABLE :: DVPHT_1_54_CLOCK_ENABLE [02:02] */
-#define BCHP_CLKGEN_DVP_HT_DUAL_WRAPPER_INST_CLOCK_ENABLE_DVPHT_1_54_CLOCK_ENABLE_MASK 0x00000004
-#define BCHP_CLKGEN_DVP_HT_DUAL_WRAPPER_INST_CLOCK_ENABLE_DVPHT_1_54_CLOCK_ENABLE_SHIFT 2
-#define BCHP_CLKGEN_DVP_HT_DUAL_WRAPPER_INST_CLOCK_ENABLE_DVPHT_1_54_CLOCK_ENABLE_DEFAULT 0x00000001
-
-/* CLKGEN :: DVP_HT_DUAL_WRAPPER_INST_CLOCK_ENABLE :: DVPHT_1_108_CLOCK_ENABLE [01:01] */
-#define BCHP_CLKGEN_DVP_HT_DUAL_WRAPPER_INST_CLOCK_ENABLE_DVPHT_1_108_CLOCK_ENABLE_MASK 0x00000002
-#define BCHP_CLKGEN_DVP_HT_DUAL_WRAPPER_INST_CLOCK_ENABLE_DVPHT_1_108_CLOCK_ENABLE_SHIFT 1
-#define BCHP_CLKGEN_DVP_HT_DUAL_WRAPPER_INST_CLOCK_ENABLE_DVPHT_1_108_CLOCK_ENABLE_DEFAULT 0x00000001
-
-/* CLKGEN :: DVP_HT_DUAL_WRAPPER_INST_CLOCK_ENABLE :: DVPHT_108_CLOCK_ENABLE [00:00] */
-#define BCHP_CLKGEN_DVP_HT_DUAL_WRAPPER_INST_CLOCK_ENABLE_DVPHT_108_CLOCK_ENABLE_MASK 0x00000001
-#define BCHP_CLKGEN_DVP_HT_DUAL_WRAPPER_INST_CLOCK_ENABLE_DVPHT_108_CLOCK_ENABLE_SHIFT 0
-#define BCHP_CLKGEN_DVP_HT_DUAL_WRAPPER_INST_CLOCK_ENABLE_DVPHT_108_CLOCK_ENABLE_DEFAULT 0x00000001
-
-/***************************************************************************
- *DVP_HT_DUAL_WRAPPER_INST_CLOCK_ENABLE_STATUS - Clock Enable Status
- ***************************************************************************/
-/* CLKGEN :: DVP_HT_DUAL_WRAPPER_INST_CLOCK_ENABLE_STATUS :: reserved0 [31:07] */
-#define BCHP_CLKGEN_DVP_HT_DUAL_WRAPPER_INST_CLOCK_ENABLE_STATUS_reserved0_MASK 0xffffff80
-#define BCHP_CLKGEN_DVP_HT_DUAL_WRAPPER_INST_CLOCK_ENABLE_STATUS_reserved0_SHIFT 7
-
-/* CLKGEN :: DVP_HT_DUAL_WRAPPER_INST_CLOCK_ENABLE_STATUS :: DVPHT_BVB_324_CLOCK_ENABLE_STATUS [06:06] */
-#define BCHP_CLKGEN_DVP_HT_DUAL_WRAPPER_INST_CLOCK_ENABLE_STATUS_DVPHT_BVB_324_CLOCK_ENABLE_STATUS_MASK 0x00000040
-#define BCHP_CLKGEN_DVP_HT_DUAL_WRAPPER_INST_CLOCK_ENABLE_STATUS_DVPHT_BVB_324_CLOCK_ENABLE_STATUS_SHIFT 6
-
-/* CLKGEN :: DVP_HT_DUAL_WRAPPER_INST_CLOCK_ENABLE_STATUS :: DVPHT_648_CLOCK_ENABLE_STATUS [05:05] */
-#define BCHP_CLKGEN_DVP_HT_DUAL_WRAPPER_INST_CLOCK_ENABLE_STATUS_DVPHT_648_CLOCK_ENABLE_STATUS_MASK 0x00000020
-#define BCHP_CLKGEN_DVP_HT_DUAL_WRAPPER_INST_CLOCK_ENABLE_STATUS_DVPHT_648_CLOCK_ENABLE_STATUS_SHIFT 5
-
-/* CLKGEN :: DVP_HT_DUAL_WRAPPER_INST_CLOCK_ENABLE_STATUS :: DVPHT_54_CLOCK_ENABLE_STATUS [04:04] */
-#define BCHP_CLKGEN_DVP_HT_DUAL_WRAPPER_INST_CLOCK_ENABLE_STATUS_DVPHT_54_CLOCK_ENABLE_STATUS_MASK 0x00000010
-#define BCHP_CLKGEN_DVP_HT_DUAL_WRAPPER_INST_CLOCK_ENABLE_STATUS_DVPHT_54_CLOCK_ENABLE_STATUS_SHIFT 4
-
-/* CLKGEN :: DVP_HT_DUAL_WRAPPER_INST_CLOCK_ENABLE_STATUS :: DVPHT_1_648_CLOCK_ENABLE_STATUS [03:03] */
-#define BCHP_CLKGEN_DVP_HT_DUAL_WRAPPER_INST_CLOCK_ENABLE_STATUS_DVPHT_1_648_CLOCK_ENABLE_STATUS_MASK 0x00000008
-#define BCHP_CLKGEN_DVP_HT_DUAL_WRAPPER_INST_CLOCK_ENABLE_STATUS_DVPHT_1_648_CLOCK_ENABLE_STATUS_SHIFT 3
-
-/* CLKGEN :: DVP_HT_DUAL_WRAPPER_INST_CLOCK_ENABLE_STATUS :: DVPHT_1_54_CLOCK_ENABLE_STATUS [02:02] */
-#define BCHP_CLKGEN_DVP_HT_DUAL_WRAPPER_INST_CLOCK_ENABLE_STATUS_DVPHT_1_54_CLOCK_ENABLE_STATUS_MASK 0x00000004
-#define BCHP_CLKGEN_DVP_HT_DUAL_WRAPPER_INST_CLOCK_ENABLE_STATUS_DVPHT_1_54_CLOCK_ENABLE_STATUS_SHIFT 2
-
-/* CLKGEN :: DVP_HT_DUAL_WRAPPER_INST_CLOCK_ENABLE_STATUS :: DVPHT_1_108_CLOCK_ENABLE_STATUS [01:01] */
-#define BCHP_CLKGEN_DVP_HT_DUAL_WRAPPER_INST_CLOCK_ENABLE_STATUS_DVPHT_1_108_CLOCK_ENABLE_STATUS_MASK 0x00000002
-#define BCHP_CLKGEN_DVP_HT_DUAL_WRAPPER_INST_CLOCK_ENABLE_STATUS_DVPHT_1_108_CLOCK_ENABLE_STATUS_SHIFT 1
-
-/* CLKGEN :: DVP_HT_DUAL_WRAPPER_INST_CLOCK_ENABLE_STATUS :: DVPHT_108_CLOCK_ENABLE_STATUS [00:00] */
-#define BCHP_CLKGEN_DVP_HT_DUAL_WRAPPER_INST_CLOCK_ENABLE_STATUS_DVPHT_108_CLOCK_ENABLE_STATUS_MASK 0x00000001
-#define BCHP_CLKGEN_DVP_HT_DUAL_WRAPPER_INST_CLOCK_ENABLE_STATUS_DVPHT_108_CLOCK_ENABLE_STATUS_SHIFT 0
-
-/***************************************************************************
- *DVP_HT_DUAL_WRAPPER_INST_ENABLE - Dvp ht dual wrapper inst enable
- ***************************************************************************/
-/* CLKGEN :: DVP_HT_DUAL_WRAPPER_INST_ENABLE :: reserved0 [31:01] */
-#define BCHP_CLKGEN_DVP_HT_DUAL_WRAPPER_INST_ENABLE_reserved0_MASK 0xfffffffe
-#define BCHP_CLKGEN_DVP_HT_DUAL_WRAPPER_INST_ENABLE_reserved0_SHIFT 1
-
-/* CLKGEN :: DVP_HT_DUAL_WRAPPER_INST_ENABLE :: DVPHT_1_CLK_VEC_ENABLE [00:00] */
-#define BCHP_CLKGEN_DVP_HT_DUAL_WRAPPER_INST_ENABLE_DVPHT_1_CLK_VEC_ENABLE_MASK 0x00000001
-#define BCHP_CLKGEN_DVP_HT_DUAL_WRAPPER_INST_ENABLE_DVPHT_1_CLK_VEC_ENABLE_SHIFT 0
-#define BCHP_CLKGEN_DVP_HT_DUAL_WRAPPER_INST_ENABLE_DVPHT_1_CLK_VEC_ENABLE_DEFAULT 0x00000001
-
-/***************************************************************************
- *DVP_HT_DUAL_WRAPPER_INST_OBSERVE_CLOCK - Dvp ht dual wrapper inst observe clock
- ***************************************************************************/
-/* CLKGEN :: DVP_HT_DUAL_WRAPPER_INST_OBSERVE_CLOCK :: reserved0 [31:12] */
-#define BCHP_CLKGEN_DVP_HT_DUAL_WRAPPER_INST_OBSERVE_CLOCK_reserved0_MASK 0xfffff000
-#define BCHP_CLKGEN_DVP_HT_DUAL_WRAPPER_INST_OBSERVE_CLOCK_reserved0_SHIFT 12
-
-/* CLKGEN :: DVP_HT_DUAL_WRAPPER_INST_OBSERVE_CLOCK :: DVPHT_ENABLE_OBSERVE_CLOCK [11:11] */
-#define BCHP_CLKGEN_DVP_HT_DUAL_WRAPPER_INST_OBSERVE_CLOCK_DVPHT_ENABLE_OBSERVE_CLOCK_MASK 0x00000800
-#define BCHP_CLKGEN_DVP_HT_DUAL_WRAPPER_INST_OBSERVE_CLOCK_DVPHT_ENABLE_OBSERVE_CLOCK_SHIFT 11
-#define BCHP_CLKGEN_DVP_HT_DUAL_WRAPPER_INST_OBSERVE_CLOCK_DVPHT_ENABLE_OBSERVE_CLOCK_DEFAULT 0x00000000
-
-/* CLKGEN :: DVP_HT_DUAL_WRAPPER_INST_OBSERVE_CLOCK :: DVPHT_ENABLE_DIVIDER_OBSERVE_CLOCK [10:10] */
-#define BCHP_CLKGEN_DVP_HT_DUAL_WRAPPER_INST_OBSERVE_CLOCK_DVPHT_ENABLE_DIVIDER_OBSERVE_CLOCK_MASK 0x00000400
-#define BCHP_CLKGEN_DVP_HT_DUAL_WRAPPER_INST_OBSERVE_CLOCK_DVPHT_ENABLE_DIVIDER_OBSERVE_CLOCK_SHIFT 10
-#define BCHP_CLKGEN_DVP_HT_DUAL_WRAPPER_INST_OBSERVE_CLOCK_DVPHT_ENABLE_DIVIDER_OBSERVE_CLOCK_DEFAULT 0x00000000
-
-/* CLKGEN :: DVP_HT_DUAL_WRAPPER_INST_OBSERVE_CLOCK :: DVPHT_CONTROL_OBSERVE_CLOCK [09:06] */
-#define BCHP_CLKGEN_DVP_HT_DUAL_WRAPPER_INST_OBSERVE_CLOCK_DVPHT_CONTROL_OBSERVE_CLOCK_MASK 0x000003c0
-#define BCHP_CLKGEN_DVP_HT_DUAL_WRAPPER_INST_OBSERVE_CLOCK_DVPHT_CONTROL_OBSERVE_CLOCK_SHIFT 6
-#define BCHP_CLKGEN_DVP_HT_DUAL_WRAPPER_INST_OBSERVE_CLOCK_DVPHT_CONTROL_OBSERVE_CLOCK_DEFAULT 0x00000000
-
-/* CLKGEN :: DVP_HT_DUAL_WRAPPER_INST_OBSERVE_CLOCK :: DVPHT_1_ENABLE_OBSERVE_CLOCK [05:05] */
-#define BCHP_CLKGEN_DVP_HT_DUAL_WRAPPER_INST_OBSERVE_CLOCK_DVPHT_1_ENABLE_OBSERVE_CLOCK_MASK 0x00000020
-#define BCHP_CLKGEN_DVP_HT_DUAL_WRAPPER_INST_OBSERVE_CLOCK_DVPHT_1_ENABLE_OBSERVE_CLOCK_SHIFT 5
-#define BCHP_CLKGEN_DVP_HT_DUAL_WRAPPER_INST_OBSERVE_CLOCK_DVPHT_1_ENABLE_OBSERVE_CLOCK_DEFAULT 0x00000000
-
-/* CLKGEN :: DVP_HT_DUAL_WRAPPER_INST_OBSERVE_CLOCK :: DVPHT_1_ENABLE_DIVIDER_OBSERVE_CLOCK [04:04] */
-#define BCHP_CLKGEN_DVP_HT_DUAL_WRAPPER_INST_OBSERVE_CLOCK_DVPHT_1_ENABLE_DIVIDER_OBSERVE_CLOCK_MASK 0x00000010
-#define BCHP_CLKGEN_DVP_HT_DUAL_WRAPPER_INST_OBSERVE_CLOCK_DVPHT_1_ENABLE_DIVIDER_OBSERVE_CLOCK_SHIFT 4
-#define BCHP_CLKGEN_DVP_HT_DUAL_WRAPPER_INST_OBSERVE_CLOCK_DVPHT_1_ENABLE_DIVIDER_OBSERVE_CLOCK_DEFAULT 0x00000000
-
-/* CLKGEN :: DVP_HT_DUAL_WRAPPER_INST_OBSERVE_CLOCK :: DVPHT_1_CONTROL_OBSERVE_CLOCK [03:00] */
-#define BCHP_CLKGEN_DVP_HT_DUAL_WRAPPER_INST_OBSERVE_CLOCK_DVPHT_1_CONTROL_OBSERVE_CLOCK_MASK 0x0000000f
-#define BCHP_CLKGEN_DVP_HT_DUAL_WRAPPER_INST_OBSERVE_CLOCK_DVPHT_1_CONTROL_OBSERVE_CLOCK_SHIFT 0
-#define BCHP_CLKGEN_DVP_HT_DUAL_WRAPPER_INST_OBSERVE_CLOCK_DVPHT_1_CONTROL_OBSERVE_CLOCK_DEFAULT 0x00000000
-
-/***************************************************************************
- *EAGLET_TOP_INST_CKTAPSEL - Eaglet top inst cktapsel
- ***************************************************************************/
-/* CLKGEN :: EAGLET_TOP_INST_CKTAPSEL :: reserved0 [31:12] */
-#define BCHP_CLKGEN_EAGLET_TOP_INST_CKTAPSEL_reserved0_MASK 0xfffff000
-#define BCHP_CLKGEN_EAGLET_TOP_INST_CKTAPSEL_reserved0_SHIFT 12
-
-/* CLKGEN :: EAGLET_TOP_INST_CKTAPSEL :: SCB_CKTAP1_CKTAPSEL [11:06] */
-#define BCHP_CLKGEN_EAGLET_TOP_INST_CKTAPSEL_SCB_CKTAP1_CKTAPSEL_MASK 0x00000fc0
-#define BCHP_CLKGEN_EAGLET_TOP_INST_CKTAPSEL_SCB_CKTAP1_CKTAPSEL_SHIFT 6
-#define BCHP_CLKGEN_EAGLET_TOP_INST_CKTAPSEL_SCB_CKTAP1_CKTAPSEL_DEFAULT 0x00000000
-
-/* CLKGEN :: EAGLET_TOP_INST_CKTAPSEL :: SCB_CKTAP0_CKTAPSEL [05:00] */
-#define BCHP_CLKGEN_EAGLET_TOP_INST_CKTAPSEL_SCB_CKTAP0_CKTAPSEL_MASK 0x0000003f
-#define BCHP_CLKGEN_EAGLET_TOP_INST_CKTAPSEL_SCB_CKTAP0_CKTAPSEL_SHIFT 0
-#define BCHP_CLKGEN_EAGLET_TOP_INST_CKTAPSEL_SCB_CKTAP0_CKTAPSEL_DEFAULT 0x00000000
-
-/***************************************************************************
- *EAGLET_TOP_INST_CLOCK_DISABLE - Disable EAGLET_TOP_INST's clocks
- ***************************************************************************/
-/* CLKGEN :: EAGLET_TOP_INST_CLOCK_DISABLE :: reserved0 [31:01] */
-#define BCHP_CLKGEN_EAGLET_TOP_INST_CLOCK_DISABLE_reserved0_MASK 0xfffffffe
-#define BCHP_CLKGEN_EAGLET_TOP_INST_CLOCK_DISABLE_reserved0_SHIFT 1
-
-/* CLKGEN :: EAGLET_TOP_INST_CLOCK_DISABLE :: DISABLE_CPU_SLOWCPU_CLOCK [00:00] */
-#define BCHP_CLKGEN_EAGLET_TOP_INST_CLOCK_DISABLE_DISABLE_CPU_SLOWCPU_CLOCK_MASK 0x00000001
-#define BCHP_CLKGEN_EAGLET_TOP_INST_CLOCK_DISABLE_DISABLE_CPU_SLOWCPU_CLOCK_SHIFT 0
-#define BCHP_CLKGEN_EAGLET_TOP_INST_CLOCK_DISABLE_DISABLE_CPU_SLOWCPU_CLOCK_DEFAULT 0x00000001
-
-/***************************************************************************
- *EAGLET_TOP_INST_CLOCK_DISABLE_STATUS - Clock Disable Status
- ***************************************************************************/
-/* CLKGEN :: EAGLET_TOP_INST_CLOCK_DISABLE_STATUS :: reserved0 [31:01] */
-#define BCHP_CLKGEN_EAGLET_TOP_INST_CLOCK_DISABLE_STATUS_reserved0_MASK 0xfffffffe
-#define BCHP_CLKGEN_EAGLET_TOP_INST_CLOCK_DISABLE_STATUS_reserved0_SHIFT 1
-
-/* CLKGEN :: EAGLET_TOP_INST_CLOCK_DISABLE_STATUS :: DISABLE_CPU_SLOWCPU_CLOCK_STATUS [00:00] */
-#define BCHP_CLKGEN_EAGLET_TOP_INST_CLOCK_DISABLE_STATUS_DISABLE_CPU_SLOWCPU_CLOCK_STATUS_MASK 0x00000001
-#define BCHP_CLKGEN_EAGLET_TOP_INST_CLOCK_DISABLE_STATUS_DISABLE_CPU_SLOWCPU_CLOCK_STATUS_SHIFT 0
-
-/***************************************************************************
- *EAGLET_TOP_INST_CLOCK_ENABLE - Eaglet top inst clock enable
- ***************************************************************************/
-/* CLKGEN :: EAGLET_TOP_INST_CLOCK_ENABLE :: reserved0 [31:04] */
-#define BCHP_CLKGEN_EAGLET_TOP_INST_CLOCK_ENABLE_reserved0_MASK 0xfffffff0
-#define BCHP_CLKGEN_EAGLET_TOP_INST_CLOCK_ENABLE_reserved0_SHIFT 4
-
-/* CLKGEN :: EAGLET_TOP_INST_CLOCK_ENABLE :: CPU_SECURE_CLOCK_ENABLE [03:03] */
-#define BCHP_CLKGEN_EAGLET_TOP_INST_CLOCK_ENABLE_CPU_SECURE_CLOCK_ENABLE_MASK 0x00000008
-#define BCHP_CLKGEN_EAGLET_TOP_INST_CLOCK_ENABLE_CPU_SECURE_CLOCK_ENABLE_SHIFT 3
-#define BCHP_CLKGEN_EAGLET_TOP_INST_CLOCK_ENABLE_CPU_SECURE_CLOCK_ENABLE_DEFAULT 0x00000001
-
-/* CLKGEN :: EAGLET_TOP_INST_CLOCK_ENABLE :: CPU_SCB_CLOCK_ENABLE [02:02] */
-#define BCHP_CLKGEN_EAGLET_TOP_INST_CLOCK_ENABLE_CPU_SCB_CLOCK_ENABLE_MASK 0x00000004
-#define BCHP_CLKGEN_EAGLET_TOP_INST_CLOCK_ENABLE_CPU_SCB_CLOCK_ENABLE_SHIFT 2
-#define BCHP_CLKGEN_EAGLET_TOP_INST_CLOCK_ENABLE_CPU_SCB_CLOCK_ENABLE_DEFAULT 0x00000001
-
-/* CLKGEN :: EAGLET_TOP_INST_CLOCK_ENABLE :: CPU_GISB_CLOCK_ENABLE [01:01] */
-#define BCHP_CLKGEN_EAGLET_TOP_INST_CLOCK_ENABLE_CPU_GISB_CLOCK_ENABLE_MASK 0x00000002
-#define BCHP_CLKGEN_EAGLET_TOP_INST_CLOCK_ENABLE_CPU_GISB_CLOCK_ENABLE_SHIFT 1
-#define BCHP_CLKGEN_EAGLET_TOP_INST_CLOCK_ENABLE_CPU_GISB_CLOCK_ENABLE_DEFAULT 0x00000001
-
-/* CLKGEN :: EAGLET_TOP_INST_CLOCK_ENABLE :: CPU_54_CLOCK_ENABLE [00:00] */
-#define BCHP_CLKGEN_EAGLET_TOP_INST_CLOCK_ENABLE_CPU_54_CLOCK_ENABLE_MASK 0x00000001
-#define BCHP_CLKGEN_EAGLET_TOP_INST_CLOCK_ENABLE_CPU_54_CLOCK_ENABLE_SHIFT 0
-#define BCHP_CLKGEN_EAGLET_TOP_INST_CLOCK_ENABLE_CPU_54_CLOCK_ENABLE_DEFAULT 0x00000001
-
-/***************************************************************************
- *EAGLET_TOP_INST_CLOCK_ENABLE_STATUS - Clock Enable Status
- ***************************************************************************/
-/* CLKGEN :: EAGLET_TOP_INST_CLOCK_ENABLE_STATUS :: reserved0 [31:04] */
-#define BCHP_CLKGEN_EAGLET_TOP_INST_CLOCK_ENABLE_STATUS_reserved0_MASK 0xfffffff0
-#define BCHP_CLKGEN_EAGLET_TOP_INST_CLOCK_ENABLE_STATUS_reserved0_SHIFT 4
-
-/* CLKGEN :: EAGLET_TOP_INST_CLOCK_ENABLE_STATUS :: CPU_SECURE_CLOCK_ENABLE_STATUS [03:03] */
-#define BCHP_CLKGEN_EAGLET_TOP_INST_CLOCK_ENABLE_STATUS_CPU_SECURE_CLOCK_ENABLE_STATUS_MASK 0x00000008
-#define BCHP_CLKGEN_EAGLET_TOP_INST_CLOCK_ENABLE_STATUS_CPU_SECURE_CLOCK_ENABLE_STATUS_SHIFT 3
-
-/* CLKGEN :: EAGLET_TOP_INST_CLOCK_ENABLE_STATUS :: CPU_SCB_CLOCK_ENABLE_STATUS [02:02] */
-#define BCHP_CLKGEN_EAGLET_TOP_INST_CLOCK_ENABLE_STATUS_CPU_SCB_CLOCK_ENABLE_STATUS_MASK 0x00000004
-#define BCHP_CLKGEN_EAGLET_TOP_INST_CLOCK_ENABLE_STATUS_CPU_SCB_CLOCK_ENABLE_STATUS_SHIFT 2
-
-/* CLKGEN :: EAGLET_TOP_INST_CLOCK_ENABLE_STATUS :: CPU_GISB_CLOCK_ENABLE_STATUS [01:01] */
-#define BCHP_CLKGEN_EAGLET_TOP_INST_CLOCK_ENABLE_STATUS_CPU_GISB_CLOCK_ENABLE_STATUS_MASK 0x00000002
-#define BCHP_CLKGEN_EAGLET_TOP_INST_CLOCK_ENABLE_STATUS_CPU_GISB_CLOCK_ENABLE_STATUS_SHIFT 1
-
-/* CLKGEN :: EAGLET_TOP_INST_CLOCK_ENABLE_STATUS :: CPU_54_CLOCK_ENABLE_STATUS [00:00] */
-#define BCHP_CLKGEN_EAGLET_TOP_INST_CLOCK_ENABLE_STATUS_CPU_54_CLOCK_ENABLE_STATUS_MASK 0x00000001
-#define BCHP_CLKGEN_EAGLET_TOP_INST_CLOCK_ENABLE_STATUS_CPU_54_CLOCK_ENABLE_STATUS_SHIFT 0
-
-/***************************************************************************
- *EGPHY28_1PORT_33V_90O_FC_INST_DIV5 - Egphy28 1port 33v 90o fc inst div5
- ***************************************************************************/
-/* CLKGEN :: EGPHY28_1PORT_33V_90O_FC_INST_DIV5 :: reserved0 [31:01] */
-#define BCHP_CLKGEN_EGPHY28_1PORT_33V_90O_FC_INST_DIV5_reserved0_MASK 0xfffffffe
-#define BCHP_CLKGEN_EGPHY28_1PORT_33V_90O_FC_INST_DIV5_reserved0_SHIFT 1
-
-/* CLKGEN :: EGPHY28_1PORT_33V_90O_FC_INST_DIV5 :: EGPHY_PLL_SEL_DIV5 [00:00] */
-#define BCHP_CLKGEN_EGPHY28_1PORT_33V_90O_FC_INST_DIV5_EGPHY_PLL_SEL_DIV5_MASK 0x00000001
-#define BCHP_CLKGEN_EGPHY28_1PORT_33V_90O_FC_INST_DIV5_EGPHY_PLL_SEL_DIV5_SHIFT 0
-#define BCHP_CLKGEN_EGPHY28_1PORT_33V_90O_FC_INST_DIV5_EGPHY_PLL_SEL_DIV5_DEFAULT 0x00000000
-
-/***************************************************************************
- *EGPHY28_1PORT_33V_90O_FC_INST_SEL - Egphy28 1port 33v 90o fc inst sel
- ***************************************************************************/
-/* CLKGEN :: EGPHY28_1PORT_33V_90O_FC_INST_SEL :: reserved0 [31:03] */
-#define BCHP_CLKGEN_EGPHY28_1PORT_33V_90O_FC_INST_SEL_reserved0_MASK 0xfffffff8
-#define BCHP_CLKGEN_EGPHY28_1PORT_33V_90O_FC_INST_SEL_reserved0_SHIFT 3
-
-/* CLKGEN :: EGPHY28_1PORT_33V_90O_FC_INST_SEL :: EGPHY_PLL_REFCLK_SEL [02:01] */
-#define BCHP_CLKGEN_EGPHY28_1PORT_33V_90O_FC_INST_SEL_EGPHY_PLL_REFCLK_SEL_MASK 0x00000006
-#define BCHP_CLKGEN_EGPHY28_1PORT_33V_90O_FC_INST_SEL_EGPHY_PLL_REFCLK_SEL_SHIFT 1
-#define BCHP_CLKGEN_EGPHY28_1PORT_33V_90O_FC_INST_SEL_EGPHY_PLL_REFCLK_SEL_DEFAULT 0x00000000
-
-/* CLKGEN :: EGPHY28_1PORT_33V_90O_FC_INST_SEL :: EGPHY_PLL_CLK_SEL [00:00] */
-#define BCHP_CLKGEN_EGPHY28_1PORT_33V_90O_FC_INST_SEL_EGPHY_PLL_CLK_SEL_MASK 0x00000001
-#define BCHP_CLKGEN_EGPHY28_1PORT_33V_90O_FC_INST_SEL_EGPHY_PLL_CLK_SEL_SHIFT 0
-#define BCHP_CLKGEN_EGPHY28_1PORT_33V_90O_FC_INST_SEL_EGPHY_PLL_CLK_SEL_DEFAULT 0x00000000
-
-/***************************************************************************
- *FSK_TOP_INST_CLOCK_ENABLE - Fsk top inst clock enable
- ***************************************************************************/
-/* CLKGEN :: FSK_TOP_INST_CLOCK_ENABLE :: reserved0 [31:03] */
-#define BCHP_CLKGEN_FSK_TOP_INST_CLOCK_ENABLE_reserved0_MASK 0xfffffff8
-#define BCHP_CLKGEN_FSK_TOP_INST_CLOCK_ENABLE_reserved0_SHIFT 3
-
-/* CLKGEN :: FSK_TOP_INST_CLOCK_ENABLE :: SDS0_54_CLOCK_ENABLE [02:02] */
-#define BCHP_CLKGEN_FSK_TOP_INST_CLOCK_ENABLE_SDS0_54_CLOCK_ENABLE_MASK 0x00000004
-#define BCHP_CLKGEN_FSK_TOP_INST_CLOCK_ENABLE_SDS0_54_CLOCK_ENABLE_SHIFT 2
-#define BCHP_CLKGEN_FSK_TOP_INST_CLOCK_ENABLE_SDS0_54_CLOCK_ENABLE_DEFAULT 0x00000001
-
-/* CLKGEN :: FSK_TOP_INST_CLOCK_ENABLE :: SDS0_108_CLOCK_ENABLE [01:01] */
-#define BCHP_CLKGEN_FSK_TOP_INST_CLOCK_ENABLE_SDS0_108_CLOCK_ENABLE_MASK 0x00000002
-#define BCHP_CLKGEN_FSK_TOP_INST_CLOCK_ENABLE_SDS0_108_CLOCK_ENABLE_SHIFT 1
-#define BCHP_CLKGEN_FSK_TOP_INST_CLOCK_ENABLE_SDS0_108_CLOCK_ENABLE_DEFAULT 0x00000001
-
-/* CLKGEN :: FSK_TOP_INST_CLOCK_ENABLE :: FSK_CH0_DIG_CLOCK_ENABLE [00:00] */
-#define BCHP_CLKGEN_FSK_TOP_INST_CLOCK_ENABLE_FSK_CH0_DIG_CLOCK_ENABLE_MASK 0x00000001
-#define BCHP_CLKGEN_FSK_TOP_INST_CLOCK_ENABLE_FSK_CH0_DIG_CLOCK_ENABLE_SHIFT 0
-#define BCHP_CLKGEN_FSK_TOP_INST_CLOCK_ENABLE_FSK_CH0_DIG_CLOCK_ENABLE_DEFAULT 0x00000001
-
-/***************************************************************************
- *FSK_TOP_INST_CLOCK_ENABLE_STATUS - Clock Enable Status
- ***************************************************************************/
-/* CLKGEN :: FSK_TOP_INST_CLOCK_ENABLE_STATUS :: reserved0 [31:03] */
-#define BCHP_CLKGEN_FSK_TOP_INST_CLOCK_ENABLE_STATUS_reserved0_MASK 0xfffffff8
-#define BCHP_CLKGEN_FSK_TOP_INST_CLOCK_ENABLE_STATUS_reserved0_SHIFT 3
-
-/* CLKGEN :: FSK_TOP_INST_CLOCK_ENABLE_STATUS :: SDS0_54_CLOCK_ENABLE_STATUS [02:02] */
-#define BCHP_CLKGEN_FSK_TOP_INST_CLOCK_ENABLE_STATUS_SDS0_54_CLOCK_ENABLE_STATUS_MASK 0x00000004
-#define BCHP_CLKGEN_FSK_TOP_INST_CLOCK_ENABLE_STATUS_SDS0_54_CLOCK_ENABLE_STATUS_SHIFT 2
-
-/* CLKGEN :: FSK_TOP_INST_CLOCK_ENABLE_STATUS :: SDS0_108_CLOCK_ENABLE_STATUS [01:01] */
-#define BCHP_CLKGEN_FSK_TOP_INST_CLOCK_ENABLE_STATUS_SDS0_108_CLOCK_ENABLE_STATUS_MASK 0x00000002
-#define BCHP_CLKGEN_FSK_TOP_INST_CLOCK_ENABLE_STATUS_SDS0_108_CLOCK_ENABLE_STATUS_SHIFT 1
-
-/* CLKGEN :: FSK_TOP_INST_CLOCK_ENABLE_STATUS :: FSK_CH0_DIG_CLOCK_ENABLE_STATUS [00:00] */
-#define BCHP_CLKGEN_FSK_TOP_INST_CLOCK_ENABLE_STATUS_FSK_CH0_DIG_CLOCK_ENABLE_STATUS_MASK 0x00000001
-#define BCHP_CLKGEN_FSK_TOP_INST_CLOCK_ENABLE_STATUS_FSK_CH0_DIG_CLOCK_ENABLE_STATUS_SHIFT 0
-
-/***************************************************************************
- *FSK_TOP_INST_OBSERVE_CLOCK - Fsk top inst observe clock
- ***************************************************************************/
-/* CLKGEN :: FSK_TOP_INST_OBSERVE_CLOCK :: reserved0 [31:06] */
-#define BCHP_CLKGEN_FSK_TOP_INST_OBSERVE_CLOCK_reserved0_MASK 0xffffffc0
-#define BCHP_CLKGEN_FSK_TOP_INST_OBSERVE_CLOCK_reserved0_SHIFT 6
-
-/* CLKGEN :: FSK_TOP_INST_OBSERVE_CLOCK :: SDSTFEC0_CONTROL_OBSERVE_CLOCK [05:02] */
-#define BCHP_CLKGEN_FSK_TOP_INST_OBSERVE_CLOCK_SDSTFEC0_CONTROL_OBSERVE_CLOCK_MASK 0x0000003c
-#define BCHP_CLKGEN_FSK_TOP_INST_OBSERVE_CLOCK_SDSTFEC0_CONTROL_OBSERVE_CLOCK_SHIFT 2
-#define BCHP_CLKGEN_FSK_TOP_INST_OBSERVE_CLOCK_SDSTFEC0_CONTROL_OBSERVE_CLOCK_DEFAULT 0x00000000
-
-/* CLKGEN :: FSK_TOP_INST_OBSERVE_CLOCK :: SDSAFEC0_ENABLE_OBSERVE_CLOCK [01:01] */
-#define BCHP_CLKGEN_FSK_TOP_INST_OBSERVE_CLOCK_SDSAFEC0_ENABLE_OBSERVE_CLOCK_MASK 0x00000002
-#define BCHP_CLKGEN_FSK_TOP_INST_OBSERVE_CLOCK_SDSAFEC0_ENABLE_OBSERVE_CLOCK_SHIFT 1
-#define BCHP_CLKGEN_FSK_TOP_INST_OBSERVE_CLOCK_SDSAFEC0_ENABLE_OBSERVE_CLOCK_DEFAULT 0x00000000
-
-/* CLKGEN :: FSK_TOP_INST_OBSERVE_CLOCK :: SDSAFEC0_ENABLE_DIVIDER_OBSERVE_CLOCK [00:00] */
-#define BCHP_CLKGEN_FSK_TOP_INST_OBSERVE_CLOCK_SDSAFEC0_ENABLE_DIVIDER_OBSERVE_CLOCK_MASK 0x00000001
-#define BCHP_CLKGEN_FSK_TOP_INST_OBSERVE_CLOCK_SDSAFEC0_ENABLE_DIVIDER_OBSERVE_CLOCK_SHIFT 0
-#define BCHP_CLKGEN_FSK_TOP_INST_OBSERVE_CLOCK_SDSAFEC0_ENABLE_DIVIDER_OBSERVE_CLOCK_DEFAULT 0x00000000
-
-/***************************************************************************
- *GRAPHICS_INST_ALT_CLOCK_ENABLE_M2MC - Graphics inst alt clock enable m2mc
- ***************************************************************************/
-/* CLKGEN :: GRAPHICS_INST_ALT_CLOCK_ENABLE_M2MC :: reserved0 [31:01] */
-#define BCHP_CLKGEN_GRAPHICS_INST_ALT_CLOCK_ENABLE_M2MC_reserved0_MASK 0xfffffffe
-#define BCHP_CLKGEN_GRAPHICS_INST_ALT_CLOCK_ENABLE_M2MC_reserved0_SHIFT 1
-
-/* CLKGEN :: GRAPHICS_INST_ALT_CLOCK_ENABLE_M2MC :: GFX_GISB_ALT_CLOCK_ENABLE_M2MC [00:00] */
-#define BCHP_CLKGEN_GRAPHICS_INST_ALT_CLOCK_ENABLE_M2MC_GFX_GISB_ALT_CLOCK_ENABLE_M2MC_MASK 0x00000001
-#define BCHP_CLKGEN_GRAPHICS_INST_ALT_CLOCK_ENABLE_M2MC_GFX_GISB_ALT_CLOCK_ENABLE_M2MC_SHIFT 0
-#define BCHP_CLKGEN_GRAPHICS_INST_ALT_CLOCK_ENABLE_M2MC_GFX_GISB_ALT_CLOCK_ENABLE_M2MC_DEFAULT 0x00000001
-
-/***************************************************************************
- *GRAPHICS_INST_CKTAPSEL - Graphics inst cktapsel
- ***************************************************************************/
-/* CLKGEN :: GRAPHICS_INST_CKTAPSEL :: reserved0 [31:12] */
-#define BCHP_CLKGEN_GRAPHICS_INST_CKTAPSEL_reserved0_MASK 0xfffff000
-#define BCHP_CLKGEN_GRAPHICS_INST_CKTAPSEL_reserved0_SHIFT 12
-
-/* CLKGEN :: GRAPHICS_INST_CKTAPSEL :: SCB_CKTAP1_CKTAPSEL [11:06] */
-#define BCHP_CLKGEN_GRAPHICS_INST_CKTAPSEL_SCB_CKTAP1_CKTAPSEL_MASK 0x00000fc0
-#define BCHP_CLKGEN_GRAPHICS_INST_CKTAPSEL_SCB_CKTAP1_CKTAPSEL_SHIFT 6
-#define BCHP_CLKGEN_GRAPHICS_INST_CKTAPSEL_SCB_CKTAP1_CKTAPSEL_DEFAULT 0x00000000
-
-/* CLKGEN :: GRAPHICS_INST_CKTAPSEL :: SCB_CKTAP0_CKTAPSEL [05:00] */
-#define BCHP_CLKGEN_GRAPHICS_INST_CKTAPSEL_SCB_CKTAP0_CKTAPSEL_MASK 0x0000003f
-#define BCHP_CLKGEN_GRAPHICS_INST_CKTAPSEL_SCB_CKTAP0_CKTAPSEL_SHIFT 0
-#define BCHP_CLKGEN_GRAPHICS_INST_CKTAPSEL_SCB_CKTAP0_CKTAPSEL_DEFAULT 0x00000000
-
-/***************************************************************************
- *GRAPHICS_INST_CLOCK_ENABLE_M2MC - Graphics inst clock enable m2mc
- ***************************************************************************/
-/* CLKGEN :: GRAPHICS_INST_CLOCK_ENABLE_M2MC :: reserved0 [31:04] */
-#define BCHP_CLKGEN_GRAPHICS_INST_CLOCK_ENABLE_M2MC_reserved0_MASK 0xfffffff0
-#define BCHP_CLKGEN_GRAPHICS_INST_CLOCK_ENABLE_M2MC_reserved0_SHIFT 4
-
-/* CLKGEN :: GRAPHICS_INST_CLOCK_ENABLE_M2MC :: GFX_SCB_CLOCK_ENABLE_M2MC [03:03] */
-#define BCHP_CLKGEN_GRAPHICS_INST_CLOCK_ENABLE_M2MC_GFX_SCB_CLOCK_ENABLE_M2MC_MASK 0x00000008
-#define BCHP_CLKGEN_GRAPHICS_INST_CLOCK_ENABLE_M2MC_GFX_SCB_CLOCK_ENABLE_M2MC_SHIFT 3
-#define BCHP_CLKGEN_GRAPHICS_INST_CLOCK_ENABLE_M2MC_GFX_SCB_CLOCK_ENABLE_M2MC_DEFAULT 0x00000001
-
-/* CLKGEN :: GRAPHICS_INST_CLOCK_ENABLE_M2MC :: GFX_GISB_CLOCK_ENABLE_M2MC [02:02] */
-#define BCHP_CLKGEN_GRAPHICS_INST_CLOCK_ENABLE_M2MC_GFX_GISB_CLOCK_ENABLE_M2MC_MASK 0x00000004
-#define BCHP_CLKGEN_GRAPHICS_INST_CLOCK_ENABLE_M2MC_GFX_GISB_CLOCK_ENABLE_M2MC_SHIFT 2
-#define BCHP_CLKGEN_GRAPHICS_INST_CLOCK_ENABLE_M2MC_GFX_GISB_CLOCK_ENABLE_M2MC_DEFAULT 0x00000001
-
-/* CLKGEN :: GRAPHICS_INST_CLOCK_ENABLE_M2MC :: GFX_CLOCK_ENABLE_M2MC [01:01] */
-#define BCHP_CLKGEN_GRAPHICS_INST_CLOCK_ENABLE_M2MC_GFX_CLOCK_ENABLE_M2MC_MASK 0x00000002
-#define BCHP_CLKGEN_GRAPHICS_INST_CLOCK_ENABLE_M2MC_GFX_CLOCK_ENABLE_M2MC_SHIFT 1
-#define BCHP_CLKGEN_GRAPHICS_INST_CLOCK_ENABLE_M2MC_GFX_CLOCK_ENABLE_M2MC_DEFAULT 0x00000001
-
-/* CLKGEN :: GRAPHICS_INST_CLOCK_ENABLE_M2MC :: GFX_54_CLOCK_ENABLE_M2MC [00:00] */
-#define BCHP_CLKGEN_GRAPHICS_INST_CLOCK_ENABLE_M2MC_GFX_54_CLOCK_ENABLE_M2MC_MASK 0x00000001
-#define BCHP_CLKGEN_GRAPHICS_INST_CLOCK_ENABLE_M2MC_GFX_54_CLOCK_ENABLE_M2MC_SHIFT 0
-#define BCHP_CLKGEN_GRAPHICS_INST_CLOCK_ENABLE_M2MC_GFX_54_CLOCK_ENABLE_M2MC_DEFAULT 0x00000001
-
-/***************************************************************************
- *GRAPHICS_INST_CLOCK_ENABLE_M2MC1 - Graphics inst clock enable m2mc1
- ***************************************************************************/
-/* CLKGEN :: GRAPHICS_INST_CLOCK_ENABLE_M2MC1 :: reserved0 [31:03] */
-#define BCHP_CLKGEN_GRAPHICS_INST_CLOCK_ENABLE_M2MC1_reserved0_MASK 0xfffffff8
-#define BCHP_CLKGEN_GRAPHICS_INST_CLOCK_ENABLE_M2MC1_reserved0_SHIFT 3
-
-/* CLKGEN :: GRAPHICS_INST_CLOCK_ENABLE_M2MC1 :: GFX_SCB_CLOCK_ENABLE_M2MC1 [02:02] */
-#define BCHP_CLKGEN_GRAPHICS_INST_CLOCK_ENABLE_M2MC1_GFX_SCB_CLOCK_ENABLE_M2MC1_MASK 0x00000004
-#define BCHP_CLKGEN_GRAPHICS_INST_CLOCK_ENABLE_M2MC1_GFX_SCB_CLOCK_ENABLE_M2MC1_SHIFT 2
-#define BCHP_CLKGEN_GRAPHICS_INST_CLOCK_ENABLE_M2MC1_GFX_SCB_CLOCK_ENABLE_M2MC1_DEFAULT 0x00000001
-
-/* CLKGEN :: GRAPHICS_INST_CLOCK_ENABLE_M2MC1 :: GFX_GISB_CLOCK_ENABLE_M2MC1 [01:01] */
-#define BCHP_CLKGEN_GRAPHICS_INST_CLOCK_ENABLE_M2MC1_GFX_GISB_CLOCK_ENABLE_M2MC1_MASK 0x00000002
-#define BCHP_CLKGEN_GRAPHICS_INST_CLOCK_ENABLE_M2MC1_GFX_GISB_CLOCK_ENABLE_M2MC1_SHIFT 1
-#define BCHP_CLKGEN_GRAPHICS_INST_CLOCK_ENABLE_M2MC1_GFX_GISB_CLOCK_ENABLE_M2MC1_DEFAULT 0x00000001
-
-/* CLKGEN :: GRAPHICS_INST_CLOCK_ENABLE_M2MC1 :: GFX_CLOCK_ENABLE_M2MC1 [00:00] */
-#define BCHP_CLKGEN_GRAPHICS_INST_CLOCK_ENABLE_M2MC1_GFX_CLOCK_ENABLE_M2MC1_MASK 0x00000001
-#define BCHP_CLKGEN_GRAPHICS_INST_CLOCK_ENABLE_M2MC1_GFX_CLOCK_ENABLE_M2MC1_SHIFT 0
-#define BCHP_CLKGEN_GRAPHICS_INST_CLOCK_ENABLE_M2MC1_GFX_CLOCK_ENABLE_M2MC1_DEFAULT 0x00000001
-
-/***************************************************************************
- *GRAPHICS_INST_CLOCK_ENABLE_M2MC1_STATUS - Clock Enable Status
- ***************************************************************************/
-/* CLKGEN :: GRAPHICS_INST_CLOCK_ENABLE_M2MC1_STATUS :: reserved0 [31:03] */
-#define BCHP_CLKGEN_GRAPHICS_INST_CLOCK_ENABLE_M2MC1_STATUS_reserved0_MASK 0xfffffff8
-#define BCHP_CLKGEN_GRAPHICS_INST_CLOCK_ENABLE_M2MC1_STATUS_reserved0_SHIFT 3
-
-/* CLKGEN :: GRAPHICS_INST_CLOCK_ENABLE_M2MC1_STATUS :: GFX_SCB_CLOCK_ENABLE_M2MC1_STATUS [02:02] */
-#define BCHP_CLKGEN_GRAPHICS_INST_CLOCK_ENABLE_M2MC1_STATUS_GFX_SCB_CLOCK_ENABLE_M2MC1_STATUS_MASK 0x00000004
-#define BCHP_CLKGEN_GRAPHICS_INST_CLOCK_ENABLE_M2MC1_STATUS_GFX_SCB_CLOCK_ENABLE_M2MC1_STATUS_SHIFT 2
-
-/* CLKGEN :: GRAPHICS_INST_CLOCK_ENABLE_M2MC1_STATUS :: GFX_GISB_CLOCK_ENABLE_M2MC1_STATUS [01:01] */
-#define BCHP_CLKGEN_GRAPHICS_INST_CLOCK_ENABLE_M2MC1_STATUS_GFX_GISB_CLOCK_ENABLE_M2MC1_STATUS_MASK 0x00000002
-#define BCHP_CLKGEN_GRAPHICS_INST_CLOCK_ENABLE_M2MC1_STATUS_GFX_GISB_CLOCK_ENABLE_M2MC1_STATUS_SHIFT 1
-
-/* CLKGEN :: GRAPHICS_INST_CLOCK_ENABLE_M2MC1_STATUS :: GFX_CLOCK_ENABLE_M2MC1_STATUS [00:00] */
-#define BCHP_CLKGEN_GRAPHICS_INST_CLOCK_ENABLE_M2MC1_STATUS_GFX_CLOCK_ENABLE_M2MC1_STATUS_MASK 0x00000001
-#define BCHP_CLKGEN_GRAPHICS_INST_CLOCK_ENABLE_M2MC1_STATUS_GFX_CLOCK_ENABLE_M2MC1_STATUS_SHIFT 0
-
-/***************************************************************************
- *GRAPHICS_INST_CLOCK_ENABLE_M2MC_STATUS - Clock Enable Status
- ***************************************************************************/
-/* CLKGEN :: GRAPHICS_INST_CLOCK_ENABLE_M2MC_STATUS :: reserved0 [31:04] */
-#define BCHP_CLKGEN_GRAPHICS_INST_CLOCK_ENABLE_M2MC_STATUS_reserved0_MASK 0xfffffff0
-#define BCHP_CLKGEN_GRAPHICS_INST_CLOCK_ENABLE_M2MC_STATUS_reserved0_SHIFT 4
-
-/* CLKGEN :: GRAPHICS_INST_CLOCK_ENABLE_M2MC_STATUS :: GFX_SCB_CLOCK_ENABLE_M2MC_STATUS [03:03] */
-#define BCHP_CLKGEN_GRAPHICS_INST_CLOCK_ENABLE_M2MC_STATUS_GFX_SCB_CLOCK_ENABLE_M2MC_STATUS_MASK 0x00000008
-#define BCHP_CLKGEN_GRAPHICS_INST_CLOCK_ENABLE_M2MC_STATUS_GFX_SCB_CLOCK_ENABLE_M2MC_STATUS_SHIFT 3
-
-/* CLKGEN :: GRAPHICS_INST_CLOCK_ENABLE_M2MC_STATUS :: GFX_GISB_CLOCK_ENABLE_M2MC_STATUS [02:02] */
-#define BCHP_CLKGEN_GRAPHICS_INST_CLOCK_ENABLE_M2MC_STATUS_GFX_GISB_CLOCK_ENABLE_M2MC_STATUS_MASK 0x00000004
-#define BCHP_CLKGEN_GRAPHICS_INST_CLOCK_ENABLE_M2MC_STATUS_GFX_GISB_CLOCK_ENABLE_M2MC_STATUS_SHIFT 2
-
-/* CLKGEN :: GRAPHICS_INST_CLOCK_ENABLE_M2MC_STATUS :: GFX_CLOCK_ENABLE_M2MC_STATUS [01:01] */
-#define BCHP_CLKGEN_GRAPHICS_INST_CLOCK_ENABLE_M2MC_STATUS_GFX_CLOCK_ENABLE_M2MC_STATUS_MASK 0x00000002
-#define BCHP_CLKGEN_GRAPHICS_INST_CLOCK_ENABLE_M2MC_STATUS_GFX_CLOCK_ENABLE_M2MC_STATUS_SHIFT 1
-
-/* CLKGEN :: GRAPHICS_INST_CLOCK_ENABLE_M2MC_STATUS :: GFX_54_CLOCK_ENABLE_M2MC_STATUS [00:00] */
-#define BCHP_CLKGEN_GRAPHICS_INST_CLOCK_ENABLE_M2MC_STATUS_GFX_54_CLOCK_ENABLE_M2MC_STATUS_MASK 0x00000001
-#define BCHP_CLKGEN_GRAPHICS_INST_CLOCK_ENABLE_M2MC_STATUS_GFX_54_CLOCK_ENABLE_M2MC_STATUS_SHIFT 0
-
-/***************************************************************************
- *GRAPHICS_INST_OBSERVE_CLOCK - Graphics inst observe clock
- ***************************************************************************/
-/* CLKGEN :: GRAPHICS_INST_OBSERVE_CLOCK :: reserved0 [31:06] */
-#define BCHP_CLKGEN_GRAPHICS_INST_OBSERVE_CLOCK_reserved0_MASK 0xffffffc0
-#define BCHP_CLKGEN_GRAPHICS_INST_OBSERVE_CLOCK_reserved0_SHIFT 6
-
-/* CLKGEN :: GRAPHICS_INST_OBSERVE_CLOCK :: GFX_ENABLE_OBSERVE_CLOCK [05:05] */
-#define BCHP_CLKGEN_GRAPHICS_INST_OBSERVE_CLOCK_GFX_ENABLE_OBSERVE_CLOCK_MASK 0x00000020
-#define BCHP_CLKGEN_GRAPHICS_INST_OBSERVE_CLOCK_GFX_ENABLE_OBSERVE_CLOCK_SHIFT 5
-#define BCHP_CLKGEN_GRAPHICS_INST_OBSERVE_CLOCK_GFX_ENABLE_OBSERVE_CLOCK_DEFAULT 0x00000000
-
-/* CLKGEN :: GRAPHICS_INST_OBSERVE_CLOCK :: GFX_ENABLE_DIVIDER_OBSERVE_CLOCK [04:04] */
-#define BCHP_CLKGEN_GRAPHICS_INST_OBSERVE_CLOCK_GFX_ENABLE_DIVIDER_OBSERVE_CLOCK_MASK 0x00000010
-#define BCHP_CLKGEN_GRAPHICS_INST_OBSERVE_CLOCK_GFX_ENABLE_DIVIDER_OBSERVE_CLOCK_SHIFT 4
-#define BCHP_CLKGEN_GRAPHICS_INST_OBSERVE_CLOCK_GFX_ENABLE_DIVIDER_OBSERVE_CLOCK_DEFAULT 0x00000000
-
-/* CLKGEN :: GRAPHICS_INST_OBSERVE_CLOCK :: GFX_CONTROL_OBSERVE_CLOCK [03:00] */
-#define BCHP_CLKGEN_GRAPHICS_INST_OBSERVE_CLOCK_GFX_CONTROL_OBSERVE_CLOCK_MASK 0x0000000f
-#define BCHP_CLKGEN_GRAPHICS_INST_OBSERVE_CLOCK_GFX_CONTROL_OBSERVE_CLOCK_SHIFT 0
-#define BCHP_CLKGEN_GRAPHICS_INST_OBSERVE_CLOCK_GFX_CONTROL_OBSERVE_CLOCK_DEFAULT 0x00000000
-
-/***************************************************************************
- *HIF_INST_CKTAPSEL - Hif inst cktapsel
- ***************************************************************************/
-/* CLKGEN :: HIF_INST_CKTAPSEL :: reserved0 [31:12] */
-#define BCHP_CLKGEN_HIF_INST_CKTAPSEL_reserved0_MASK 0xfffff000
-#define BCHP_CLKGEN_HIF_INST_CKTAPSEL_reserved0_SHIFT 12
-
-/* CLKGEN :: HIF_INST_CKTAPSEL :: SCB_CKTAP1_CKTAPSEL [11:06] */
-#define BCHP_CLKGEN_HIF_INST_CKTAPSEL_SCB_CKTAP1_CKTAPSEL_MASK 0x00000fc0
-#define BCHP_CLKGEN_HIF_INST_CKTAPSEL_SCB_CKTAP1_CKTAPSEL_SHIFT 6
-#define BCHP_CLKGEN_HIF_INST_CKTAPSEL_SCB_CKTAP1_CKTAPSEL_DEFAULT 0x00000000
-
-/* CLKGEN :: HIF_INST_CKTAPSEL :: SCB_CKTAP0_CKTAPSEL [05:00] */
-#define BCHP_CLKGEN_HIF_INST_CKTAPSEL_SCB_CKTAP0_CKTAPSEL_MASK 0x0000003f
-#define BCHP_CLKGEN_HIF_INST_CKTAPSEL_SCB_CKTAP0_CKTAPSEL_SHIFT 0
-#define BCHP_CLKGEN_HIF_INST_CKTAPSEL_SCB_CKTAP0_CKTAPSEL_DEFAULT 0x00000000
-
-/***************************************************************************
- *HIF_INST_CLOCK_DISABLE - Disable HIF_INST's clocks
- ***************************************************************************/
-/* CLKGEN :: HIF_INST_CLOCK_DISABLE :: reserved0 [31:06] */
-#define BCHP_CLKGEN_HIF_INST_CLOCK_DISABLE_reserved0_MASK 0xffffffc0
-#define BCHP_CLKGEN_HIF_INST_CLOCK_DISABLE_reserved0_SHIFT 6
-
-/* CLKGEN :: HIF_INST_CLOCK_DISABLE :: DISABLE_PAD_OUTPUT_EBI_CLOCK [05:05] */
-#define BCHP_CLKGEN_HIF_INST_CLOCK_DISABLE_DISABLE_PAD_OUTPUT_EBI_CLOCK_MASK 0x00000020
-#define BCHP_CLKGEN_HIF_INST_CLOCK_DISABLE_DISABLE_PAD_OUTPUT_EBI_CLOCK_SHIFT 5
-#define BCHP_CLKGEN_HIF_INST_CLOCK_DISABLE_DISABLE_PAD_OUTPUT_EBI_CLOCK_DEFAULT 0x00000000
-
-/* CLKGEN :: HIF_INST_CLOCK_DISABLE :: DISABLE_NAND_DDR_CLOCK [04:04] */
-#define BCHP_CLKGEN_HIF_INST_CLOCK_DISABLE_DISABLE_NAND_DDR_CLOCK_MASK 0x00000010
-#define BCHP_CLKGEN_HIF_INST_CLOCK_DISABLE_DISABLE_NAND_DDR_CLOCK_SHIFT 4
-#define BCHP_CLKGEN_HIF_INST_CLOCK_DISABLE_DISABLE_NAND_DDR_CLOCK_DEFAULT 0x00000000
-
-/* CLKGEN :: HIF_INST_CLOCK_DISABLE :: DISABLE_HIF_SPI_CLOCK [03:03] */
-#define BCHP_CLKGEN_HIF_INST_CLOCK_DISABLE_DISABLE_HIF_SPI_CLOCK_MASK 0x00000008
-#define BCHP_CLKGEN_HIF_INST_CLOCK_DISABLE_DISABLE_HIF_SPI_CLOCK_SHIFT 3
-#define BCHP_CLKGEN_HIF_INST_CLOCK_DISABLE_DISABLE_HIF_SPI_CLOCK_DEFAULT 0x00000000
-
-/* CLKGEN :: HIF_INST_CLOCK_DISABLE :: DISABLE_HIF_SDIO_EMMC_CLOCK [02:02] */
-#define BCHP_CLKGEN_HIF_INST_CLOCK_DISABLE_DISABLE_HIF_SDIO_EMMC_CLOCK_MASK 0x00000004
-#define BCHP_CLKGEN_HIF_INST_CLOCK_DISABLE_DISABLE_HIF_SDIO_EMMC_CLOCK_SHIFT 2
-#define BCHP_CLKGEN_HIF_INST_CLOCK_DISABLE_DISABLE_HIF_SDIO_EMMC_CLOCK_DEFAULT 0x00000000
-
-/* CLKGEN :: HIF_INST_CLOCK_DISABLE :: DISABLE_HIF_SDIO_CARD_CLOCK [01:01] */
-#define BCHP_CLKGEN_HIF_INST_CLOCK_DISABLE_DISABLE_HIF_SDIO_CARD_CLOCK_MASK 0x00000002
-#define BCHP_CLKGEN_HIF_INST_CLOCK_DISABLE_DISABLE_HIF_SDIO_CARD_CLOCK_SHIFT 1
-#define BCHP_CLKGEN_HIF_INST_CLOCK_DISABLE_DISABLE_HIF_SDIO_CARD_CLOCK_DEFAULT 0x00000000
-
-/* CLKGEN :: HIF_INST_CLOCK_DISABLE :: DISABLE_HIF_ALWAYSON_CLOCK [00:00] */
-#define BCHP_CLKGEN_HIF_INST_CLOCK_DISABLE_DISABLE_HIF_ALWAYSON_CLOCK_MASK 0x00000001
-#define BCHP_CLKGEN_HIF_INST_CLOCK_DISABLE_DISABLE_HIF_ALWAYSON_CLOCK_SHIFT 0
-#define BCHP_CLKGEN_HIF_INST_CLOCK_DISABLE_DISABLE_HIF_ALWAYSON_CLOCK_DEFAULT 0x00000000
-
-/***************************************************************************
- *HIF_INST_CLOCK_DISABLE_STATUS - Clock Disable Status
- ***************************************************************************/
-/* CLKGEN :: HIF_INST_CLOCK_DISABLE_STATUS :: reserved0 [31:06] */
-#define BCHP_CLKGEN_HIF_INST_CLOCK_DISABLE_STATUS_reserved0_MASK 0xffffffc0
-#define BCHP_CLKGEN_HIF_INST_CLOCK_DISABLE_STATUS_reserved0_SHIFT 6
-
-/* CLKGEN :: HIF_INST_CLOCK_DISABLE_STATUS :: DISABLE_PAD_OUTPUT_EBI_CLOCK_STATUS [05:05] */
-#define BCHP_CLKGEN_HIF_INST_CLOCK_DISABLE_STATUS_DISABLE_PAD_OUTPUT_EBI_CLOCK_STATUS_MASK 0x00000020
-#define BCHP_CLKGEN_HIF_INST_CLOCK_DISABLE_STATUS_DISABLE_PAD_OUTPUT_EBI_CLOCK_STATUS_SHIFT 5
-
-/* CLKGEN :: HIF_INST_CLOCK_DISABLE_STATUS :: DISABLE_NAND_DDR_CLOCK_STATUS [04:04] */
-#define BCHP_CLKGEN_HIF_INST_CLOCK_DISABLE_STATUS_DISABLE_NAND_DDR_CLOCK_STATUS_MASK 0x00000010
-#define BCHP_CLKGEN_HIF_INST_CLOCK_DISABLE_STATUS_DISABLE_NAND_DDR_CLOCK_STATUS_SHIFT 4
-
-/* CLKGEN :: HIF_INST_CLOCK_DISABLE_STATUS :: DISABLE_HIF_SPI_CLOCK_STATUS [03:03] */
-#define BCHP_CLKGEN_HIF_INST_CLOCK_DISABLE_STATUS_DISABLE_HIF_SPI_CLOCK_STATUS_MASK 0x00000008
-#define BCHP_CLKGEN_HIF_INST_CLOCK_DISABLE_STATUS_DISABLE_HIF_SPI_CLOCK_STATUS_SHIFT 3
-
-/* CLKGEN :: HIF_INST_CLOCK_DISABLE_STATUS :: DISABLE_HIF_SDIO_EMMC_CLOCK_STATUS [02:02] */
-#define BCHP_CLKGEN_HIF_INST_CLOCK_DISABLE_STATUS_DISABLE_HIF_SDIO_EMMC_CLOCK_STATUS_MASK 0x00000004
-#define BCHP_CLKGEN_HIF_INST_CLOCK_DISABLE_STATUS_DISABLE_HIF_SDIO_EMMC_CLOCK_STATUS_SHIFT 2
-
-/* CLKGEN :: HIF_INST_CLOCK_DISABLE_STATUS :: DISABLE_HIF_SDIO_CARD_CLOCK_STATUS [01:01] */
-#define BCHP_CLKGEN_HIF_INST_CLOCK_DISABLE_STATUS_DISABLE_HIF_SDIO_CARD_CLOCK_STATUS_MASK 0x00000002
-#define BCHP_CLKGEN_HIF_INST_CLOCK_DISABLE_STATUS_DISABLE_HIF_SDIO_CARD_CLOCK_STATUS_SHIFT 1
-
-/* CLKGEN :: HIF_INST_CLOCK_DISABLE_STATUS :: DISABLE_HIF_ALWAYSON_CLOCK_STATUS [00:00] */
-#define BCHP_CLKGEN_HIF_INST_CLOCK_DISABLE_STATUS_DISABLE_HIF_ALWAYSON_CLOCK_STATUS_MASK 0x00000001
-#define BCHP_CLKGEN_HIF_INST_CLOCK_DISABLE_STATUS_DISABLE_HIF_ALWAYSON_CLOCK_STATUS_SHIFT 0
-
-/***************************************************************************
- *HIF_INST_CLOCK_ENABLE - Hif inst clock enable
- ***************************************************************************/
-/* CLKGEN :: HIF_INST_CLOCK_ENABLE :: reserved0 [31:01] */
-#define BCHP_CLKGEN_HIF_INST_CLOCK_ENABLE_reserved0_MASK 0xfffffffe
-#define BCHP_CLKGEN_HIF_INST_CLOCK_ENABLE_reserved0_SHIFT 1
-
-/* CLKGEN :: HIF_INST_CLOCK_ENABLE :: HIF_54_CLOCK_ENABLE [00:00] */
-#define BCHP_CLKGEN_HIF_INST_CLOCK_ENABLE_HIF_54_CLOCK_ENABLE_MASK 0x00000001
-#define BCHP_CLKGEN_HIF_INST_CLOCK_ENABLE_HIF_54_CLOCK_ENABLE_SHIFT 0
-#define BCHP_CLKGEN_HIF_INST_CLOCK_ENABLE_HIF_54_CLOCK_ENABLE_DEFAULT 0x00000001
-
-/***************************************************************************
- *HIF_INST_CLOCK_ENABLE_STATUS - Clock Enable Status
- ***************************************************************************/
-/* CLKGEN :: HIF_INST_CLOCK_ENABLE_STATUS :: reserved0 [31:01] */
-#define BCHP_CLKGEN_HIF_INST_CLOCK_ENABLE_STATUS_reserved0_MASK 0xfffffffe
-#define BCHP_CLKGEN_HIF_INST_CLOCK_ENABLE_STATUS_reserved0_SHIFT 1
-
-/* CLKGEN :: HIF_INST_CLOCK_ENABLE_STATUS :: HIF_54_CLOCK_ENABLE_STATUS [00:00] */
-#define BCHP_CLKGEN_HIF_INST_CLOCK_ENABLE_STATUS_HIF_54_CLOCK_ENABLE_STATUS_MASK 0x00000001
-#define BCHP_CLKGEN_HIF_INST_CLOCK_ENABLE_STATUS_HIF_54_CLOCK_ENABLE_STATUS_SHIFT 0
-
-/***************************************************************************
- *HIF_INST_OBSERVE_CLOCK - Hif inst observe clock
- ***************************************************************************/
-/* CLKGEN :: HIF_INST_OBSERVE_CLOCK :: reserved0 [31:06] */
-#define BCHP_CLKGEN_HIF_INST_OBSERVE_CLOCK_reserved0_MASK 0xffffffc0
-#define BCHP_CLKGEN_HIF_INST_OBSERVE_CLOCK_reserved0_SHIFT 6
-
-/* CLKGEN :: HIF_INST_OBSERVE_CLOCK :: HIF_ENABLE_OBSERVE_CLOCK [05:05] */
-#define BCHP_CLKGEN_HIF_INST_OBSERVE_CLOCK_HIF_ENABLE_OBSERVE_CLOCK_MASK 0x00000020
-#define BCHP_CLKGEN_HIF_INST_OBSERVE_CLOCK_HIF_ENABLE_OBSERVE_CLOCK_SHIFT 5
-#define BCHP_CLKGEN_HIF_INST_OBSERVE_CLOCK_HIF_ENABLE_OBSERVE_CLOCK_DEFAULT 0x00000000
-
-/* CLKGEN :: HIF_INST_OBSERVE_CLOCK :: HIF_ENABLE_DIVIDER_OBSERVE_CLOCK [04:04] */
-#define BCHP_CLKGEN_HIF_INST_OBSERVE_CLOCK_HIF_ENABLE_DIVIDER_OBSERVE_CLOCK_MASK 0x00000010
-#define BCHP_CLKGEN_HIF_INST_OBSERVE_CLOCK_HIF_ENABLE_DIVIDER_OBSERVE_CLOCK_SHIFT 4
-#define BCHP_CLKGEN_HIF_INST_OBSERVE_CLOCK_HIF_ENABLE_DIVIDER_OBSERVE_CLOCK_DEFAULT 0x00000000
-
-/* CLKGEN :: HIF_INST_OBSERVE_CLOCK :: HIF_CONTROL_OBSERVE_CLOCK [03:00] */
-#define BCHP_CLKGEN_HIF_INST_OBSERVE_CLOCK_HIF_CONTROL_OBSERVE_CLOCK_MASK 0x0000000f
-#define BCHP_CLKGEN_HIF_INST_OBSERVE_CLOCK_HIF_CONTROL_OBSERVE_CLOCK_SHIFT 0
-#define BCHP_CLKGEN_HIF_INST_OBSERVE_CLOCK_HIF_CONTROL_OBSERVE_CLOCK_DEFAULT 0x00000000
-
-/***************************************************************************
- *HVD_SID0_TOP_INST_CKTAPSEL - Hvd sid0 top inst cktapsel
- ***************************************************************************/
-/* CLKGEN :: HVD_SID0_TOP_INST_CKTAPSEL :: reserved0 [31:12] */
-#define BCHP_CLKGEN_HVD_SID0_TOP_INST_CKTAPSEL_reserved0_MASK 0xfffff000
-#define BCHP_CLKGEN_HVD_SID0_TOP_INST_CKTAPSEL_reserved0_SHIFT 12
-
-/* CLKGEN :: HVD_SID0_TOP_INST_CKTAPSEL :: SCB_CKTAP1_CKTAPSEL [11:06] */
-#define BCHP_CLKGEN_HVD_SID0_TOP_INST_CKTAPSEL_SCB_CKTAP1_CKTAPSEL_MASK 0x00000fc0
-#define BCHP_CLKGEN_HVD_SID0_TOP_INST_CKTAPSEL_SCB_CKTAP1_CKTAPSEL_SHIFT 6
-#define BCHP_CLKGEN_HVD_SID0_TOP_INST_CKTAPSEL_SCB_CKTAP1_CKTAPSEL_DEFAULT 0x00000000
-
-/* CLKGEN :: HVD_SID0_TOP_INST_CKTAPSEL :: SCB_CKTAP0_CKTAPSEL [05:00] */
-#define BCHP_CLKGEN_HVD_SID0_TOP_INST_CKTAPSEL_SCB_CKTAP0_CKTAPSEL_MASK 0x0000003f
-#define BCHP_CLKGEN_HVD_SID0_TOP_INST_CKTAPSEL_SCB_CKTAP0_CKTAPSEL_SHIFT 0
-#define BCHP_CLKGEN_HVD_SID0_TOP_INST_CKTAPSEL_SCB_CKTAP0_CKTAPSEL_DEFAULT 0x00000000
-
-/***************************************************************************
- *HVD_SID0_TOP_INST_CLOCK_ENABLE - Hvd sid0 top inst clock enable
- ***************************************************************************/
-/* CLKGEN :: HVD_SID0_TOP_INST_CLOCK_ENABLE :: reserved0 [31:06] */
-#define BCHP_CLKGEN_HVD_SID0_TOP_INST_CLOCK_ENABLE_reserved0_MASK 0xffffffc0
-#define BCHP_CLKGEN_HVD_SID0_TOP_INST_CLOCK_ENABLE_reserved0_SHIFT 6
-
-/* CLKGEN :: HVD_SID0_TOP_INST_CLOCK_ENABLE :: HVD_SCB_CLOCK_ENABLE [05:05] */
-#define BCHP_CLKGEN_HVD_SID0_TOP_INST_CLOCK_ENABLE_HVD_SCB_CLOCK_ENABLE_MASK 0x00000020
-#define BCHP_CLKGEN_HVD_SID0_TOP_INST_CLOCK_ENABLE_HVD_SCB_CLOCK_ENABLE_SHIFT 5
-#define BCHP_CLKGEN_HVD_SID0_TOP_INST_CLOCK_ENABLE_HVD_SCB_CLOCK_ENABLE_DEFAULT 0x00000001
-
-/* CLKGEN :: HVD_SID0_TOP_INST_CLOCK_ENABLE :: HVD_GISB_CLOCK_ENABLE [04:04] */
-#define BCHP_CLKGEN_HVD_SID0_TOP_INST_CLOCK_ENABLE_HVD_GISB_CLOCK_ENABLE_MASK 0x00000010
-#define BCHP_CLKGEN_HVD_SID0_TOP_INST_CLOCK_ENABLE_HVD_GISB_CLOCK_ENABLE_SHIFT 4
-#define BCHP_CLKGEN_HVD_SID0_TOP_INST_CLOCK_ENABLE_HVD_GISB_CLOCK_ENABLE_DEFAULT 0x00000001
-
-/* CLKGEN :: HVD_SID0_TOP_INST_CLOCK_ENABLE :: HVD_CPU_CLOCK_ENABLE [03:03] */
-#define BCHP_CLKGEN_HVD_SID0_TOP_INST_CLOCK_ENABLE_HVD_CPU_CLOCK_ENABLE_MASK 0x00000008
-#define BCHP_CLKGEN_HVD_SID0_TOP_INST_CLOCK_ENABLE_HVD_CPU_CLOCK_ENABLE_SHIFT 3
-#define BCHP_CLKGEN_HVD_SID0_TOP_INST_CLOCK_ENABLE_HVD_CPU_CLOCK_ENABLE_DEFAULT 0x00000001
-
-/* CLKGEN :: HVD_SID0_TOP_INST_CLOCK_ENABLE :: HVD_CORE_CLOCK_ENABLE [02:02] */
-#define BCHP_CLKGEN_HVD_SID0_TOP_INST_CLOCK_ENABLE_HVD_CORE_CLOCK_ENABLE_MASK 0x00000004
-#define BCHP_CLKGEN_HVD_SID0_TOP_INST_CLOCK_ENABLE_HVD_CORE_CLOCK_ENABLE_SHIFT 2
-#define BCHP_CLKGEN_HVD_SID0_TOP_INST_CLOCK_ENABLE_HVD_CORE_CLOCK_ENABLE_DEFAULT 0x00000001
-
-/* CLKGEN :: HVD_SID0_TOP_INST_CLOCK_ENABLE :: HVD_54_CLOCK_ENABLE [01:01] */
-#define BCHP_CLKGEN_HVD_SID0_TOP_INST_CLOCK_ENABLE_HVD_54_CLOCK_ENABLE_MASK 0x00000002
-#define BCHP_CLKGEN_HVD_SID0_TOP_INST_CLOCK_ENABLE_HVD_54_CLOCK_ENABLE_SHIFT 1
-#define BCHP_CLKGEN_HVD_SID0_TOP_INST_CLOCK_ENABLE_HVD_54_CLOCK_ENABLE_DEFAULT 0x00000001
-
-/* CLKGEN :: HVD_SID0_TOP_INST_CLOCK_ENABLE :: HVD_108_CLOCK_ENABLE [00:00] */
-#define BCHP_CLKGEN_HVD_SID0_TOP_INST_CLOCK_ENABLE_HVD_108_CLOCK_ENABLE_MASK 0x00000001
-#define BCHP_CLKGEN_HVD_SID0_TOP_INST_CLOCK_ENABLE_HVD_108_CLOCK_ENABLE_SHIFT 0
-#define BCHP_CLKGEN_HVD_SID0_TOP_INST_CLOCK_ENABLE_HVD_108_CLOCK_ENABLE_DEFAULT 0x00000001
-
-/***************************************************************************
- *HVD_SID0_TOP_INST_CLOCK_ENABLE_SID - Hvd sid0 top inst clock enable sid
- ***************************************************************************/
-/* CLKGEN :: HVD_SID0_TOP_INST_CLOCK_ENABLE_SID :: reserved0 [31:01] */
-#define BCHP_CLKGEN_HVD_SID0_TOP_INST_CLOCK_ENABLE_SID_reserved0_MASK 0xfffffffe
-#define BCHP_CLKGEN_HVD_SID0_TOP_INST_CLOCK_ENABLE_SID_reserved0_SHIFT 1
-
-/* CLKGEN :: HVD_SID0_TOP_INST_CLOCK_ENABLE_SID :: HVD_CLOCK_ENABLE_SID [00:00] */
-#define BCHP_CLKGEN_HVD_SID0_TOP_INST_CLOCK_ENABLE_SID_HVD_CLOCK_ENABLE_SID_MASK 0x00000001
-#define BCHP_CLKGEN_HVD_SID0_TOP_INST_CLOCK_ENABLE_SID_HVD_CLOCK_ENABLE_SID_SHIFT 0
-#define BCHP_CLKGEN_HVD_SID0_TOP_INST_CLOCK_ENABLE_SID_HVD_CLOCK_ENABLE_SID_DEFAULT 0x00000001
-
-/***************************************************************************
- *HVD_SID0_TOP_INST_CLOCK_ENABLE_SID_STATUS - Clock Enable Status
- ***************************************************************************/
-/* CLKGEN :: HVD_SID0_TOP_INST_CLOCK_ENABLE_SID_STATUS :: reserved0 [31:01] */
-#define BCHP_CLKGEN_HVD_SID0_TOP_INST_CLOCK_ENABLE_SID_STATUS_reserved0_MASK 0xfffffffe
-#define BCHP_CLKGEN_HVD_SID0_TOP_INST_CLOCK_ENABLE_SID_STATUS_reserved0_SHIFT 1
-
-/* CLKGEN :: HVD_SID0_TOP_INST_CLOCK_ENABLE_SID_STATUS :: HVD_CLOCK_ENABLE_SID_STATUS [00:00] */
-#define BCHP_CLKGEN_HVD_SID0_TOP_INST_CLOCK_ENABLE_SID_STATUS_HVD_CLOCK_ENABLE_SID_STATUS_MASK 0x00000001
-#define BCHP_CLKGEN_HVD_SID0_TOP_INST_CLOCK_ENABLE_SID_STATUS_HVD_CLOCK_ENABLE_SID_STATUS_SHIFT 0
-
-/***************************************************************************
- *HVD_SID0_TOP_INST_CLOCK_ENABLE_STATUS - Clock Enable Status
- ***************************************************************************/
-/* CLKGEN :: HVD_SID0_TOP_INST_CLOCK_ENABLE_STATUS :: reserved0 [31:06] */
-#define BCHP_CLKGEN_HVD_SID0_TOP_INST_CLOCK_ENABLE_STATUS_reserved0_MASK 0xffffffc0
-#define BCHP_CLKGEN_HVD_SID0_TOP_INST_CLOCK_ENABLE_STATUS_reserved0_SHIFT 6
-
-/* CLKGEN :: HVD_SID0_TOP_INST_CLOCK_ENABLE_STATUS :: HVD_SCB_CLOCK_ENABLE_STATUS [05:05] */
-#define BCHP_CLKGEN_HVD_SID0_TOP_INST_CLOCK_ENABLE_STATUS_HVD_SCB_CLOCK_ENABLE_STATUS_MASK 0x00000020
-#define BCHP_CLKGEN_HVD_SID0_TOP_INST_CLOCK_ENABLE_STATUS_HVD_SCB_CLOCK_ENABLE_STATUS_SHIFT 5
-
-/* CLKGEN :: HVD_SID0_TOP_INST_CLOCK_ENABLE_STATUS :: HVD_GISB_CLOCK_ENABLE_STATUS [04:04] */
-#define BCHP_CLKGEN_HVD_SID0_TOP_INST_CLOCK_ENABLE_STATUS_HVD_GISB_CLOCK_ENABLE_STATUS_MASK 0x00000010
-#define BCHP_CLKGEN_HVD_SID0_TOP_INST_CLOCK_ENABLE_STATUS_HVD_GISB_CLOCK_ENABLE_STATUS_SHIFT 4
-
-/* CLKGEN :: HVD_SID0_TOP_INST_CLOCK_ENABLE_STATUS :: HVD_CPU_CLOCK_ENABLE_STATUS [03:03] */
-#define BCHP_CLKGEN_HVD_SID0_TOP_INST_CLOCK_ENABLE_STATUS_HVD_CPU_CLOCK_ENABLE_STATUS_MASK 0x00000008
-#define BCHP_CLKGEN_HVD_SID0_TOP_INST_CLOCK_ENABLE_STATUS_HVD_CPU_CLOCK_ENABLE_STATUS_SHIFT 3
-
-/* CLKGEN :: HVD_SID0_TOP_INST_CLOCK_ENABLE_STATUS :: HVD_CORE_CLOCK_ENABLE_STATUS [02:02] */
-#define BCHP_CLKGEN_HVD_SID0_TOP_INST_CLOCK_ENABLE_STATUS_HVD_CORE_CLOCK_ENABLE_STATUS_MASK 0x00000004
-#define BCHP_CLKGEN_HVD_SID0_TOP_INST_CLOCK_ENABLE_STATUS_HVD_CORE_CLOCK_ENABLE_STATUS_SHIFT 2
-
-/* CLKGEN :: HVD_SID0_TOP_INST_CLOCK_ENABLE_STATUS :: HVD_54_CLOCK_ENABLE_STATUS [01:01] */
-#define BCHP_CLKGEN_HVD_SID0_TOP_INST_CLOCK_ENABLE_STATUS_HVD_54_CLOCK_ENABLE_STATUS_MASK 0x00000002
-#define BCHP_CLKGEN_HVD_SID0_TOP_INST_CLOCK_ENABLE_STATUS_HVD_54_CLOCK_ENABLE_STATUS_SHIFT 1
-
-/* CLKGEN :: HVD_SID0_TOP_INST_CLOCK_ENABLE_STATUS :: HVD_108_CLOCK_ENABLE_STATUS [00:00] */
-#define BCHP_CLKGEN_HVD_SID0_TOP_INST_CLOCK_ENABLE_STATUS_HVD_108_CLOCK_ENABLE_STATUS_MASK 0x00000001
-#define BCHP_CLKGEN_HVD_SID0_TOP_INST_CLOCK_ENABLE_STATUS_HVD_108_CLOCK_ENABLE_STATUS_SHIFT 0
-
-/***************************************************************************
- *HVD_SID0_TOP_INST_OBSERVE_CLOCK - Hvd sid0 top inst observe clock
- ***************************************************************************/
-/* CLKGEN :: HVD_SID0_TOP_INST_OBSERVE_CLOCK :: reserved0 [31:06] */
-#define BCHP_CLKGEN_HVD_SID0_TOP_INST_OBSERVE_CLOCK_reserved0_MASK 0xffffffc0
-#define BCHP_CLKGEN_HVD_SID0_TOP_INST_OBSERVE_CLOCK_reserved0_SHIFT 6
-
-/* CLKGEN :: HVD_SID0_TOP_INST_OBSERVE_CLOCK :: HVD_ENABLE_OBSERVE_CLOCK [05:05] */
-#define BCHP_CLKGEN_HVD_SID0_TOP_INST_OBSERVE_CLOCK_HVD_ENABLE_OBSERVE_CLOCK_MASK 0x00000020
-#define BCHP_CLKGEN_HVD_SID0_TOP_INST_OBSERVE_CLOCK_HVD_ENABLE_OBSERVE_CLOCK_SHIFT 5
-#define BCHP_CLKGEN_HVD_SID0_TOP_INST_OBSERVE_CLOCK_HVD_ENABLE_OBSERVE_CLOCK_DEFAULT 0x00000000
-
-/* CLKGEN :: HVD_SID0_TOP_INST_OBSERVE_CLOCK :: HVD_ENABLE_DIVIDER_OBSERVE_CLOCK [04:04] */
-#define BCHP_CLKGEN_HVD_SID0_TOP_INST_OBSERVE_CLOCK_HVD_ENABLE_DIVIDER_OBSERVE_CLOCK_MASK 0x00000010
-#define BCHP_CLKGEN_HVD_SID0_TOP_INST_OBSERVE_CLOCK_HVD_ENABLE_DIVIDER_OBSERVE_CLOCK_SHIFT 4
-#define BCHP_CLKGEN_HVD_SID0_TOP_INST_OBSERVE_CLOCK_HVD_ENABLE_DIVIDER_OBSERVE_CLOCK_DEFAULT 0x00000000
-
-/* CLKGEN :: HVD_SID0_TOP_INST_OBSERVE_CLOCK :: HVD_CONTROL_OBSERVE_CLOCK [03:00] */
-#define BCHP_CLKGEN_HVD_SID0_TOP_INST_OBSERVE_CLOCK_HVD_CONTROL_OBSERVE_CLOCK_MASK 0x0000000f
-#define BCHP_CLKGEN_HVD_SID0_TOP_INST_OBSERVE_CLOCK_HVD_CONTROL_OBSERVE_CLOCK_SHIFT 0
-#define BCHP_CLKGEN_HVD_SID0_TOP_INST_OBSERVE_CLOCK_HVD_CONTROL_OBSERVE_CLOCK_DEFAULT 0x00000000
-
-/***************************************************************************
- *INTERNAL_MUX_SELECT - Mux selects for Internal clocks
- ***************************************************************************/
-/* CLKGEN :: INTERNAL_MUX_SELECT :: reserved0 [31:02] */
-#define BCHP_CLKGEN_INTERNAL_MUX_SELECT_reserved0_MASK 0xfffffffc
-#define BCHP_CLKGEN_INTERNAL_MUX_SELECT_reserved0_SHIFT 2
-
-/* CLKGEN :: INTERNAL_MUX_SELECT :: PLLAUDIO1_REFERENCE_CLOCK [01:01] */
-#define BCHP_CLKGEN_INTERNAL_MUX_SELECT_PLLAUDIO1_REFERENCE_CLOCK_MASK 0x00000002
-#define BCHP_CLKGEN_INTERNAL_MUX_SELECT_PLLAUDIO1_REFERENCE_CLOCK_SHIFT 1
-#define BCHP_CLKGEN_INTERNAL_MUX_SELECT_PLLAUDIO1_REFERENCE_CLOCK_DEFAULT 0x00000000
-
-/* CLKGEN :: INTERNAL_MUX_SELECT :: PLLAUDIO0_REFERENCE_CLOCK [00:00] */
-#define BCHP_CLKGEN_INTERNAL_MUX_SELECT_PLLAUDIO0_REFERENCE_CLOCK_MASK 0x00000001
-#define BCHP_CLKGEN_INTERNAL_MUX_SELECT_PLLAUDIO0_REFERENCE_CLOCK_SHIFT 0
-#define BCHP_CLKGEN_INTERNAL_MUX_SELECT_PLLAUDIO0_REFERENCE_CLOCK_DEFAULT 0x00000000
-
-/***************************************************************************
- *ITU656_0_MUX_SELECT - Mux selects for itu656_0 clocks
- ***************************************************************************/
-/* CLKGEN :: ITU656_0_MUX_SELECT :: reserved0 [31:02] */
-#define BCHP_CLKGEN_ITU656_0_MUX_SELECT_reserved0_MASK 0xfffffffc
-#define BCHP_CLKGEN_ITU656_0_MUX_SELECT_reserved0_SHIFT 2
-
-/* CLKGEN :: ITU656_0_MUX_SELECT :: VEC_ITU656_0_CLOCK [01:01] */
-#define BCHP_CLKGEN_ITU656_0_MUX_SELECT_VEC_ITU656_0_CLOCK_MASK 0x00000002
-#define BCHP_CLKGEN_ITU656_0_MUX_SELECT_VEC_ITU656_0_CLOCK_SHIFT 1
-#define BCHP_CLKGEN_ITU656_0_MUX_SELECT_VEC_ITU656_0_CLOCK_DEFAULT 0x00000000
-
-/* CLKGEN :: ITU656_0_MUX_SELECT :: ENABLE_INVERT_VEC_ITU656_0_CLOCK [00:00] */
-#define BCHP_CLKGEN_ITU656_0_MUX_SELECT_ENABLE_INVERT_VEC_ITU656_0_CLOCK_MASK 0x00000001
-#define BCHP_CLKGEN_ITU656_0_MUX_SELECT_ENABLE_INVERT_VEC_ITU656_0_CLOCK_SHIFT 0
-#define BCHP_CLKGEN_ITU656_0_MUX_SELECT_ENABLE_INVERT_VEC_ITU656_0_CLOCK_DEFAULT 0x00000000
-
-/***************************************************************************
- *LEAP_TOP_INST_CKTAPSEL - Leap top inst cktapsel
- ***************************************************************************/
-/* CLKGEN :: LEAP_TOP_INST_CKTAPSEL :: reserved0 [31:12] */
-#define BCHP_CLKGEN_LEAP_TOP_INST_CKTAPSEL_reserved0_MASK 0xfffff000
-#define BCHP_CLKGEN_LEAP_TOP_INST_CKTAPSEL_reserved0_SHIFT 12
-
-/* CLKGEN :: LEAP_TOP_INST_CKTAPSEL :: SCB_CKTAP1_CKTAPSEL [11:06] */
-#define BCHP_CLKGEN_LEAP_TOP_INST_CKTAPSEL_SCB_CKTAP1_CKTAPSEL_MASK 0x00000fc0
-#define BCHP_CLKGEN_LEAP_TOP_INST_CKTAPSEL_SCB_CKTAP1_CKTAPSEL_SHIFT 6
-#define BCHP_CLKGEN_LEAP_TOP_INST_CKTAPSEL_SCB_CKTAP1_CKTAPSEL_DEFAULT 0x00000000
-
-/* CLKGEN :: LEAP_TOP_INST_CKTAPSEL :: SCB_CKTAP0_CKTAPSEL [05:00] */
-#define BCHP_CLKGEN_LEAP_TOP_INST_CKTAPSEL_SCB_CKTAP0_CKTAPSEL_MASK 0x0000003f
-#define BCHP_CLKGEN_LEAP_TOP_INST_CKTAPSEL_SCB_CKTAP0_CKTAPSEL_SHIFT 0
-#define BCHP_CLKGEN_LEAP_TOP_INST_CKTAPSEL_SCB_CKTAP0_CKTAPSEL_DEFAULT 0x00000000
-
-/***************************************************************************
- *LEAP_TOP_INST_CLOCK_DISABLE - Disable LEAP_TOP_INST's clocks
- ***************************************************************************/
-/* CLKGEN :: LEAP_TOP_INST_CLOCK_DISABLE :: reserved0 [31:05] */
-#define BCHP_CLKGEN_LEAP_TOP_INST_CLOCK_DISABLE_reserved0_MASK 0xffffffe0
-#define BCHP_CLKGEN_LEAP_TOP_INST_CLOCK_DISABLE_reserved0_SHIFT 5
-
-/* CLKGEN :: LEAP_TOP_INST_CLOCK_DISABLE :: DISABLE_LEAP_27_CLOCK [04:04] */
-#define BCHP_CLKGEN_LEAP_TOP_INST_CLOCK_DISABLE_DISABLE_LEAP_27_CLOCK_MASK 0x00000010
-#define BCHP_CLKGEN_LEAP_TOP_INST_CLOCK_DISABLE_DISABLE_LEAP_27_CLOCK_SHIFT 4
-#define BCHP_CLKGEN_LEAP_TOP_INST_CLOCK_DISABLE_DISABLE_LEAP_27_CLOCK_DEFAULT 0x00000000
-
-/* CLKGEN :: LEAP_TOP_INST_CLOCK_DISABLE :: DISABLE_LEAP_216_CLOCK [03:03] */
-#define BCHP_CLKGEN_LEAP_TOP_INST_CLOCK_DISABLE_DISABLE_LEAP_216_CLOCK_MASK 0x00000008
-#define BCHP_CLKGEN_LEAP_TOP_INST_CLOCK_DISABLE_DISABLE_LEAP_216_CLOCK_SHIFT 3
-#define BCHP_CLKGEN_LEAP_TOP_INST_CLOCK_DISABLE_DISABLE_LEAP_216_CLOCK_DEFAULT 0x00000000
-
-/* CLKGEN :: LEAP_TOP_INST_CLOCK_DISABLE :: DISABLE_DEMOD_XPT_0_MTSIF_TX1 [02:02] */
-#define BCHP_CLKGEN_LEAP_TOP_INST_CLOCK_DISABLE_DISABLE_DEMOD_XPT_0_MTSIF_TX1_MASK 0x00000004
-#define BCHP_CLKGEN_LEAP_TOP_INST_CLOCK_DISABLE_DISABLE_DEMOD_XPT_0_MTSIF_TX1_SHIFT 2
-#define BCHP_CLKGEN_LEAP_TOP_INST_CLOCK_DISABLE_DISABLE_DEMOD_XPT_0_MTSIF_TX1_DEFAULT 0x00000000
-
-/* CLKGEN :: LEAP_TOP_INST_CLOCK_DISABLE :: DISABLE_DEMOD_XPT_0_MTSIF_TX0 [01:01] */
-#define BCHP_CLKGEN_LEAP_TOP_INST_CLOCK_DISABLE_DISABLE_DEMOD_XPT_0_MTSIF_TX0_MASK 0x00000002
-#define BCHP_CLKGEN_LEAP_TOP_INST_CLOCK_DISABLE_DISABLE_DEMOD_XPT_0_MTSIF_TX0_SHIFT 1
-#define BCHP_CLKGEN_LEAP_TOP_INST_CLOCK_DISABLE_DISABLE_DEMOD_XPT_0_MTSIF_TX0_DEFAULT 0x00000000
-
-/* CLKGEN :: LEAP_TOP_INST_CLOCK_DISABLE :: DISABLE_DEMOD_XPT_0_324_CLOCK [00:00] */
-#define BCHP_CLKGEN_LEAP_TOP_INST_CLOCK_DISABLE_DISABLE_DEMOD_XPT_0_324_CLOCK_MASK 0x00000001
-#define BCHP_CLKGEN_LEAP_TOP_INST_CLOCK_DISABLE_DISABLE_DEMOD_XPT_0_324_CLOCK_SHIFT 0
-#define BCHP_CLKGEN_LEAP_TOP_INST_CLOCK_DISABLE_DISABLE_DEMOD_XPT_0_324_CLOCK_DEFAULT 0x00000000
-
-/***************************************************************************
- *LEAP_TOP_INST_CLOCK_DISABLE_STATUS - Clock Disable Status
- ***************************************************************************/
-/* CLKGEN :: LEAP_TOP_INST_CLOCK_DISABLE_STATUS :: reserved0 [31:05] */
-#define BCHP_CLKGEN_LEAP_TOP_INST_CLOCK_DISABLE_STATUS_reserved0_MASK 0xffffffe0
-#define BCHP_CLKGEN_LEAP_TOP_INST_CLOCK_DISABLE_STATUS_reserved0_SHIFT 5
-
-/* CLKGEN :: LEAP_TOP_INST_CLOCK_DISABLE_STATUS :: DISABLE_LEAP_27_CLOCK_STATUS [04:04] */
-#define BCHP_CLKGEN_LEAP_TOP_INST_CLOCK_DISABLE_STATUS_DISABLE_LEAP_27_CLOCK_STATUS_MASK 0x00000010
-#define BCHP_CLKGEN_LEAP_TOP_INST_CLOCK_DISABLE_STATUS_DISABLE_LEAP_27_CLOCK_STATUS_SHIFT 4
-
-/* CLKGEN :: LEAP_TOP_INST_CLOCK_DISABLE_STATUS :: DISABLE_LEAP_216_CLOCK_STATUS [03:03] */
-#define BCHP_CLKGEN_LEAP_TOP_INST_CLOCK_DISABLE_STATUS_DISABLE_LEAP_216_CLOCK_STATUS_MASK 0x00000008
-#define BCHP_CLKGEN_LEAP_TOP_INST_CLOCK_DISABLE_STATUS_DISABLE_LEAP_216_CLOCK_STATUS_SHIFT 3
-
-/* CLKGEN :: LEAP_TOP_INST_CLOCK_DISABLE_STATUS :: DISABLE_DEMOD_XPT_0_MTSIF_TX1_STATUS [02:02] */
-#define BCHP_CLKGEN_LEAP_TOP_INST_CLOCK_DISABLE_STATUS_DISABLE_DEMOD_XPT_0_MTSIF_TX1_STATUS_MASK 0x00000004
-#define BCHP_CLKGEN_LEAP_TOP_INST_CLOCK_DISABLE_STATUS_DISABLE_DEMOD_XPT_0_MTSIF_TX1_STATUS_SHIFT 2
-
-/* CLKGEN :: LEAP_TOP_INST_CLOCK_DISABLE_STATUS :: DISABLE_DEMOD_XPT_0_MTSIF_TX0_STATUS [01:01] */
-#define BCHP_CLKGEN_LEAP_TOP_INST_CLOCK_DISABLE_STATUS_DISABLE_DEMOD_XPT_0_MTSIF_TX0_STATUS_MASK 0x00000002
-#define BCHP_CLKGEN_LEAP_TOP_INST_CLOCK_DISABLE_STATUS_DISABLE_DEMOD_XPT_0_MTSIF_TX0_STATUS_SHIFT 1
-
-/* CLKGEN :: LEAP_TOP_INST_CLOCK_DISABLE_STATUS :: DISABLE_DEMOD_XPT_0_324_CLOCK_STATUS [00:00] */
-#define BCHP_CLKGEN_LEAP_TOP_INST_CLOCK_DISABLE_STATUS_DISABLE_DEMOD_XPT_0_324_CLOCK_STATUS_MASK 0x00000001
-#define BCHP_CLKGEN_LEAP_TOP_INST_CLOCK_DISABLE_STATUS_DISABLE_DEMOD_XPT_0_324_CLOCK_STATUS_SHIFT 0
-
-/***************************************************************************
- *LEAP_TOP_INST_CLOCK_ENABLE - Leap top inst clock enable
- ***************************************************************************/
-/* CLKGEN :: LEAP_TOP_INST_CLOCK_ENABLE :: reserved0 [31:05] */
-#define BCHP_CLKGEN_LEAP_TOP_INST_CLOCK_ENABLE_reserved0_MASK 0xffffffe0
-#define BCHP_CLKGEN_LEAP_TOP_INST_CLOCK_ENABLE_reserved0_SHIFT 5
-
-/* CLKGEN :: LEAP_TOP_INST_CLOCK_ENABLE :: LEAP_SCB_CLOCK_ENABLE [04:04] */
-#define BCHP_CLKGEN_LEAP_TOP_INST_CLOCK_ENABLE_LEAP_SCB_CLOCK_ENABLE_MASK 0x00000010
-#define BCHP_CLKGEN_LEAP_TOP_INST_CLOCK_ENABLE_LEAP_SCB_CLOCK_ENABLE_SHIFT 4
-#define BCHP_CLKGEN_LEAP_TOP_INST_CLOCK_ENABLE_LEAP_SCB_CLOCK_ENABLE_DEFAULT 0x00000001
-
-/* CLKGEN :: LEAP_TOP_INST_CLOCK_ENABLE :: LEAP_GISB_CLOCK_ENABLE [03:03] */
-#define BCHP_CLKGEN_LEAP_TOP_INST_CLOCK_ENABLE_LEAP_GISB_CLOCK_ENABLE_MASK 0x00000008
-#define BCHP_CLKGEN_LEAP_TOP_INST_CLOCK_ENABLE_LEAP_GISB_CLOCK_ENABLE_SHIFT 3
-#define BCHP_CLKGEN_LEAP_TOP_INST_CLOCK_ENABLE_LEAP_GISB_CLOCK_ENABLE_DEFAULT 0x00000001
-
-/* CLKGEN :: LEAP_TOP_INST_CLOCK_ENABLE :: LEAP_54_CLOCK_ENABLE [02:02] */
-#define BCHP_CLKGEN_LEAP_TOP_INST_CLOCK_ENABLE_LEAP_54_CLOCK_ENABLE_MASK 0x00000004
-#define BCHP_CLKGEN_LEAP_TOP_INST_CLOCK_ENABLE_LEAP_54_CLOCK_ENABLE_SHIFT 2
-#define BCHP_CLKGEN_LEAP_TOP_INST_CLOCK_ENABLE_LEAP_54_CLOCK_ENABLE_DEFAULT 0x00000001
-
-/* CLKGEN :: LEAP_TOP_INST_CLOCK_ENABLE :: LEAP_216_CLOCK_ENABLE [01:01] */
-#define BCHP_CLKGEN_LEAP_TOP_INST_CLOCK_ENABLE_LEAP_216_CLOCK_ENABLE_MASK 0x00000002
-#define BCHP_CLKGEN_LEAP_TOP_INST_CLOCK_ENABLE_LEAP_216_CLOCK_ENABLE_SHIFT 1
-#define BCHP_CLKGEN_LEAP_TOP_INST_CLOCK_ENABLE_LEAP_216_CLOCK_ENABLE_DEFAULT 0x00000001
-
-/* CLKGEN :: LEAP_TOP_INST_CLOCK_ENABLE :: LEAP_108_CLOCK_ENABLE [00:00] */
-#define BCHP_CLKGEN_LEAP_TOP_INST_CLOCK_ENABLE_LEAP_108_CLOCK_ENABLE_MASK 0x00000001
-#define BCHP_CLKGEN_LEAP_TOP_INST_CLOCK_ENABLE_LEAP_108_CLOCK_ENABLE_SHIFT 0
-#define BCHP_CLKGEN_LEAP_TOP_INST_CLOCK_ENABLE_LEAP_108_CLOCK_ENABLE_DEFAULT 0x00000001
-
-/***************************************************************************
- *LEAP_TOP_INST_CLOCK_ENABLE_STATUS - Clock Enable Status
- ***************************************************************************/
-/* CLKGEN :: LEAP_TOP_INST_CLOCK_ENABLE_STATUS :: reserved0 [31:05] */
-#define BCHP_CLKGEN_LEAP_TOP_INST_CLOCK_ENABLE_STATUS_reserved0_MASK 0xffffffe0
-#define BCHP_CLKGEN_LEAP_TOP_INST_CLOCK_ENABLE_STATUS_reserved0_SHIFT 5
-
-/* CLKGEN :: LEAP_TOP_INST_CLOCK_ENABLE_STATUS :: LEAP_SCB_CLOCK_ENABLE_STATUS [04:04] */
-#define BCHP_CLKGEN_LEAP_TOP_INST_CLOCK_ENABLE_STATUS_LEAP_SCB_CLOCK_ENABLE_STATUS_MASK 0x00000010
-#define BCHP_CLKGEN_LEAP_TOP_INST_CLOCK_ENABLE_STATUS_LEAP_SCB_CLOCK_ENABLE_STATUS_SHIFT 4
-
-/* CLKGEN :: LEAP_TOP_INST_CLOCK_ENABLE_STATUS :: LEAP_GISB_CLOCK_ENABLE_STATUS [03:03] */
-#define BCHP_CLKGEN_LEAP_TOP_INST_CLOCK_ENABLE_STATUS_LEAP_GISB_CLOCK_ENABLE_STATUS_MASK 0x00000008
-#define BCHP_CLKGEN_LEAP_TOP_INST_CLOCK_ENABLE_STATUS_LEAP_GISB_CLOCK_ENABLE_STATUS_SHIFT 3
-
-/* CLKGEN :: LEAP_TOP_INST_CLOCK_ENABLE_STATUS :: LEAP_54_CLOCK_ENABLE_STATUS [02:02] */
-#define BCHP_CLKGEN_LEAP_TOP_INST_CLOCK_ENABLE_STATUS_LEAP_54_CLOCK_ENABLE_STATUS_MASK 0x00000004
-#define BCHP_CLKGEN_LEAP_TOP_INST_CLOCK_ENABLE_STATUS_LEAP_54_CLOCK_ENABLE_STATUS_SHIFT 2
-
-/* CLKGEN :: LEAP_TOP_INST_CLOCK_ENABLE_STATUS :: LEAP_216_CLOCK_ENABLE_STATUS [01:01] */
-#define BCHP_CLKGEN_LEAP_TOP_INST_CLOCK_ENABLE_STATUS_LEAP_216_CLOCK_ENABLE_STATUS_MASK 0x00000002
-#define BCHP_CLKGEN_LEAP_TOP_INST_CLOCK_ENABLE_STATUS_LEAP_216_CLOCK_ENABLE_STATUS_SHIFT 1
-
-/* CLKGEN :: LEAP_TOP_INST_CLOCK_ENABLE_STATUS :: LEAP_108_CLOCK_ENABLE_STATUS [00:00] */
-#define BCHP_CLKGEN_LEAP_TOP_INST_CLOCK_ENABLE_STATUS_LEAP_108_CLOCK_ENABLE_STATUS_MASK 0x00000001
-#define BCHP_CLKGEN_LEAP_TOP_INST_CLOCK_ENABLE_STATUS_LEAP_108_CLOCK_ENABLE_STATUS_SHIFT 0
-
-/***************************************************************************
- *MEMSYS_32_0_INST_CKTAPSEL - Memsys 32 0 inst cktapsel
- ***************************************************************************/
-/* CLKGEN :: MEMSYS_32_0_INST_CKTAPSEL :: reserved0 [31:12] */
-#define BCHP_CLKGEN_MEMSYS_32_0_INST_CKTAPSEL_reserved0_MASK 0xfffff000
-#define BCHP_CLKGEN_MEMSYS_32_0_INST_CKTAPSEL_reserved0_SHIFT 12
-
-/* CLKGEN :: MEMSYS_32_0_INST_CKTAPSEL :: SCB_CKTAP1_CKTAPSEL [11:06] */
-#define BCHP_CLKGEN_MEMSYS_32_0_INST_CKTAPSEL_SCB_CKTAP1_CKTAPSEL_MASK 0x00000fc0
-#define BCHP_CLKGEN_MEMSYS_32_0_INST_CKTAPSEL_SCB_CKTAP1_CKTAPSEL_SHIFT 6
-#define BCHP_CLKGEN_MEMSYS_32_0_INST_CKTAPSEL_SCB_CKTAP1_CKTAPSEL_DEFAULT 0x00000000
-
-/* CLKGEN :: MEMSYS_32_0_INST_CKTAPSEL :: SCB_CKTAP0_CKTAPSEL [05:00] */
-#define BCHP_CLKGEN_MEMSYS_32_0_INST_CKTAPSEL_SCB_CKTAP0_CKTAPSEL_MASK 0x0000003f
-#define BCHP_CLKGEN_MEMSYS_32_0_INST_CKTAPSEL_SCB_CKTAP0_CKTAPSEL_SHIFT 0
-#define BCHP_CLKGEN_MEMSYS_32_0_INST_CKTAPSEL_SCB_CKTAP0_CKTAPSEL_DEFAULT 0x00000000
-
-/***************************************************************************
- *MEMSYS_32_0_INST_CLOCK_ENABLE - Memsys 32 0 inst clock enable
- ***************************************************************************/
-/* CLKGEN :: MEMSYS_32_0_INST_CLOCK_ENABLE :: reserved0 [31:03] */
-#define BCHP_CLKGEN_MEMSYS_32_0_INST_CLOCK_ENABLE_reserved0_MASK 0xfffffff8
-#define BCHP_CLKGEN_MEMSYS_32_0_INST_CLOCK_ENABLE_reserved0_SHIFT 3
-
-/* CLKGEN :: MEMSYS_32_0_INST_CLOCK_ENABLE :: MEMSYS0_SCB_CLOCK_ENABLE [02:02] */
-#define BCHP_CLKGEN_MEMSYS_32_0_INST_CLOCK_ENABLE_MEMSYS0_SCB_CLOCK_ENABLE_MASK 0x00000004
-#define BCHP_CLKGEN_MEMSYS_32_0_INST_CLOCK_ENABLE_MEMSYS0_SCB_CLOCK_ENABLE_SHIFT 2
-#define BCHP_CLKGEN_MEMSYS_32_0_INST_CLOCK_ENABLE_MEMSYS0_SCB_CLOCK_ENABLE_DEFAULT 0x00000001
-
-/* CLKGEN :: MEMSYS_32_0_INST_CLOCK_ENABLE :: MEMSYS0_GISB_CLOCK_ENABLE [01:01] */
-#define BCHP_CLKGEN_MEMSYS_32_0_INST_CLOCK_ENABLE_MEMSYS0_GISB_CLOCK_ENABLE_MASK 0x00000002
-#define BCHP_CLKGEN_MEMSYS_32_0_INST_CLOCK_ENABLE_MEMSYS0_GISB_CLOCK_ENABLE_SHIFT 1
-#define BCHP_CLKGEN_MEMSYS_32_0_INST_CLOCK_ENABLE_MEMSYS0_GISB_CLOCK_ENABLE_DEFAULT 0x00000001
-
-/* CLKGEN :: MEMSYS_32_0_INST_CLOCK_ENABLE :: MEMSYS0_54_CLOCK_ENABLE [00:00] */
-#define BCHP_CLKGEN_MEMSYS_32_0_INST_CLOCK_ENABLE_MEMSYS0_54_CLOCK_ENABLE_MASK 0x00000001
-#define BCHP_CLKGEN_MEMSYS_32_0_INST_CLOCK_ENABLE_MEMSYS0_54_CLOCK_ENABLE_SHIFT 0
-#define BCHP_CLKGEN_MEMSYS_32_0_INST_CLOCK_ENABLE_MEMSYS0_54_CLOCK_ENABLE_DEFAULT 0x00000001
-
-/***************************************************************************
- *MEMSYS_32_0_INST_CLOCK_ENABLE_STATUS - Clock Enable Status
- ***************************************************************************/
-/* CLKGEN :: MEMSYS_32_0_INST_CLOCK_ENABLE_STATUS :: reserved0 [31:03] */
-#define BCHP_CLKGEN_MEMSYS_32_0_INST_CLOCK_ENABLE_STATUS_reserved0_MASK 0xfffffff8
-#define BCHP_CLKGEN_MEMSYS_32_0_INST_CLOCK_ENABLE_STATUS_reserved0_SHIFT 3
-
-/* CLKGEN :: MEMSYS_32_0_INST_CLOCK_ENABLE_STATUS :: MEMSYS0_SCB_CLOCK_ENABLE_STATUS [02:02] */
-#define BCHP_CLKGEN_MEMSYS_32_0_INST_CLOCK_ENABLE_STATUS_MEMSYS0_SCB_CLOCK_ENABLE_STATUS_MASK 0x00000004
-#define BCHP_CLKGEN_MEMSYS_32_0_INST_CLOCK_ENABLE_STATUS_MEMSYS0_SCB_CLOCK_ENABLE_STATUS_SHIFT 2
-
-/* CLKGEN :: MEMSYS_32_0_INST_CLOCK_ENABLE_STATUS :: MEMSYS0_GISB_CLOCK_ENABLE_STATUS [01:01] */
-#define BCHP_CLKGEN_MEMSYS_32_0_INST_CLOCK_ENABLE_STATUS_MEMSYS0_GISB_CLOCK_ENABLE_STATUS_MASK 0x00000002
-#define BCHP_CLKGEN_MEMSYS_32_0_INST_CLOCK_ENABLE_STATUS_MEMSYS0_GISB_CLOCK_ENABLE_STATUS_SHIFT 1
-
-/* CLKGEN :: MEMSYS_32_0_INST_CLOCK_ENABLE_STATUS :: MEMSYS0_54_CLOCK_ENABLE_STATUS [00:00] */
-#define BCHP_CLKGEN_MEMSYS_32_0_INST_CLOCK_ENABLE_STATUS_MEMSYS0_54_CLOCK_ENABLE_STATUS_MASK 0x00000001
-#define BCHP_CLKGEN_MEMSYS_32_0_INST_CLOCK_ENABLE_STATUS_MEMSYS0_54_CLOCK_ENABLE_STATUS_SHIFT 0
-
-/***************************************************************************
- *MEMSYS_32_0_INST_OBSERVE_CLOCK - Memsys 32 0 inst observe clock
- ***************************************************************************/
-/* CLKGEN :: MEMSYS_32_0_INST_OBSERVE_CLOCK :: reserved0 [31:06] */
-#define BCHP_CLKGEN_MEMSYS_32_0_INST_OBSERVE_CLOCK_reserved0_MASK 0xffffffc0
-#define BCHP_CLKGEN_MEMSYS_32_0_INST_OBSERVE_CLOCK_reserved0_SHIFT 6
-
-/* CLKGEN :: MEMSYS_32_0_INST_OBSERVE_CLOCK :: MEMSYS0_ENABLE_OBSERVE_CLOCK [05:05] */
-#define BCHP_CLKGEN_MEMSYS_32_0_INST_OBSERVE_CLOCK_MEMSYS0_ENABLE_OBSERVE_CLOCK_MASK 0x00000020
-#define BCHP_CLKGEN_MEMSYS_32_0_INST_OBSERVE_CLOCK_MEMSYS0_ENABLE_OBSERVE_CLOCK_SHIFT 5
-#define BCHP_CLKGEN_MEMSYS_32_0_INST_OBSERVE_CLOCK_MEMSYS0_ENABLE_OBSERVE_CLOCK_DEFAULT 0x00000000
-
-/* CLKGEN :: MEMSYS_32_0_INST_OBSERVE_CLOCK :: MEMSYS0_ENABLE_DIVIDER_OBSERVE_CLOCK [04:04] */
-#define BCHP_CLKGEN_MEMSYS_32_0_INST_OBSERVE_CLOCK_MEMSYS0_ENABLE_DIVIDER_OBSERVE_CLOCK_MASK 0x00000010
-#define BCHP_CLKGEN_MEMSYS_32_0_INST_OBSERVE_CLOCK_MEMSYS0_ENABLE_DIVIDER_OBSERVE_CLOCK_SHIFT 4
-#define BCHP_CLKGEN_MEMSYS_32_0_INST_OBSERVE_CLOCK_MEMSYS0_ENABLE_DIVIDER_OBSERVE_CLOCK_DEFAULT 0x00000000
-
-/* CLKGEN :: MEMSYS_32_0_INST_OBSERVE_CLOCK :: MEMSYS0_CONTROL_OBSERVE_CLOCK [03:00] */
-#define BCHP_CLKGEN_MEMSYS_32_0_INST_OBSERVE_CLOCK_MEMSYS0_CONTROL_OBSERVE_CLOCK_MASK 0x0000000f
-#define BCHP_CLKGEN_MEMSYS_32_0_INST_OBSERVE_CLOCK_MEMSYS0_CONTROL_OBSERVE_CLOCK_SHIFT 0
-#define BCHP_CLKGEN_MEMSYS_32_0_INST_OBSERVE_CLOCK_MEMSYS0_CONTROL_OBSERVE_CLOCK_DEFAULT 0x00000000
-
-/***************************************************************************
- *MEMSYS_32_0_INST_STATUS - Memsys 32 0 inst status
- ***************************************************************************/
-/* CLKGEN :: MEMSYS_32_0_INST_STATUS :: reserved0 [31:01] */
-#define BCHP_CLKGEN_MEMSYS_32_0_INST_STATUS_reserved0_MASK 0xfffffffe
-#define BCHP_CLKGEN_MEMSYS_32_0_INST_STATUS_reserved0_SHIFT 1
-
-/* CLKGEN :: MEMSYS_32_0_INST_STATUS :: MEMSYS0_PLL_LOCKED_STATUS [00:00] */
-#define BCHP_CLKGEN_MEMSYS_32_0_INST_STATUS_MEMSYS0_PLL_LOCKED_STATUS_MASK 0x00000001
-#define BCHP_CLKGEN_MEMSYS_32_0_INST_STATUS_MEMSYS0_PLL_LOCKED_STATUS_SHIFT 0
-
-/***************************************************************************
- *MEMSYS_32_1_INST_CKTAPSEL - Memsys 32 1 inst cktapsel
- ***************************************************************************/
-/* CLKGEN :: MEMSYS_32_1_INST_CKTAPSEL :: reserved0 [31:12] */
-#define BCHP_CLKGEN_MEMSYS_32_1_INST_CKTAPSEL_reserved0_MASK 0xfffff000
-#define BCHP_CLKGEN_MEMSYS_32_1_INST_CKTAPSEL_reserved0_SHIFT 12
-
-/* CLKGEN :: MEMSYS_32_1_INST_CKTAPSEL :: SCB_CKTAP1_CKTAPSEL [11:06] */
-#define BCHP_CLKGEN_MEMSYS_32_1_INST_CKTAPSEL_SCB_CKTAP1_CKTAPSEL_MASK 0x00000fc0
-#define BCHP_CLKGEN_MEMSYS_32_1_INST_CKTAPSEL_SCB_CKTAP1_CKTAPSEL_SHIFT 6
-#define BCHP_CLKGEN_MEMSYS_32_1_INST_CKTAPSEL_SCB_CKTAP1_CKTAPSEL_DEFAULT 0x00000000
-
-/* CLKGEN :: MEMSYS_32_1_INST_CKTAPSEL :: SCB_CKTAP0_CKTAPSEL [05:00] */
-#define BCHP_CLKGEN_MEMSYS_32_1_INST_CKTAPSEL_SCB_CKTAP0_CKTAPSEL_MASK 0x0000003f
-#define BCHP_CLKGEN_MEMSYS_32_1_INST_CKTAPSEL_SCB_CKTAP0_CKTAPSEL_SHIFT 0
-#define BCHP_CLKGEN_MEMSYS_32_1_INST_CKTAPSEL_SCB_CKTAP0_CKTAPSEL_DEFAULT 0x00000000
-
-/***************************************************************************
- *MEMSYS_32_1_INST_CLOCK_ENABLE - Memsys 32 1 inst clock enable
- ***************************************************************************/
-/* CLKGEN :: MEMSYS_32_1_INST_CLOCK_ENABLE :: reserved0 [31:03] */
-#define BCHP_CLKGEN_MEMSYS_32_1_INST_CLOCK_ENABLE_reserved0_MASK 0xfffffff8
-#define BCHP_CLKGEN_MEMSYS_32_1_INST_CLOCK_ENABLE_reserved0_SHIFT 3
-
-/* CLKGEN :: MEMSYS_32_1_INST_CLOCK_ENABLE :: MEMSYS1_SCB_CLOCK_ENABLE [02:02] */
-#define BCHP_CLKGEN_MEMSYS_32_1_INST_CLOCK_ENABLE_MEMSYS1_SCB_CLOCK_ENABLE_MASK 0x00000004
-#define BCHP_CLKGEN_MEMSYS_32_1_INST_CLOCK_ENABLE_MEMSYS1_SCB_CLOCK_ENABLE_SHIFT 2
-#define BCHP_CLKGEN_MEMSYS_32_1_INST_CLOCK_ENABLE_MEMSYS1_SCB_CLOCK_ENABLE_DEFAULT 0x00000001
-
-/* CLKGEN :: MEMSYS_32_1_INST_CLOCK_ENABLE :: MEMSYS1_GISB_CLOCK_ENABLE [01:01] */
-#define BCHP_CLKGEN_MEMSYS_32_1_INST_CLOCK_ENABLE_MEMSYS1_GISB_CLOCK_ENABLE_MASK 0x00000002
-#define BCHP_CLKGEN_MEMSYS_32_1_INST_CLOCK_ENABLE_MEMSYS1_GISB_CLOCK_ENABLE_SHIFT 1
-#define BCHP_CLKGEN_MEMSYS_32_1_INST_CLOCK_ENABLE_MEMSYS1_GISB_CLOCK_ENABLE_DEFAULT 0x00000001
-
-/* CLKGEN :: MEMSYS_32_1_INST_CLOCK_ENABLE :: MEMSYS1_54_CLOCK_ENABLE [00:00] */
-#define BCHP_CLKGEN_MEMSYS_32_1_INST_CLOCK_ENABLE_MEMSYS1_54_CLOCK_ENABLE_MASK 0x00000001
-#define BCHP_CLKGEN_MEMSYS_32_1_INST_CLOCK_ENABLE_MEMSYS1_54_CLOCK_ENABLE_SHIFT 0
-#define BCHP_CLKGEN_MEMSYS_32_1_INST_CLOCK_ENABLE_MEMSYS1_54_CLOCK_ENABLE_DEFAULT 0x00000001
-
-/***************************************************************************
- *MEMSYS_32_1_INST_CLOCK_ENABLE_STATUS - Clock Enable Status
- ***************************************************************************/
-/* CLKGEN :: MEMSYS_32_1_INST_CLOCK_ENABLE_STATUS :: reserved0 [31:03] */
-#define BCHP_CLKGEN_MEMSYS_32_1_INST_CLOCK_ENABLE_STATUS_reserved0_MASK 0xfffffff8
-#define BCHP_CLKGEN_MEMSYS_32_1_INST_CLOCK_ENABLE_STATUS_reserved0_SHIFT 3
-
-/* CLKGEN :: MEMSYS_32_1_INST_CLOCK_ENABLE_STATUS :: MEMSYS1_SCB_CLOCK_ENABLE_STATUS [02:02] */
-#define BCHP_CLKGEN_MEMSYS_32_1_INST_CLOCK_ENABLE_STATUS_MEMSYS1_SCB_CLOCK_ENABLE_STATUS_MASK 0x00000004
-#define BCHP_CLKGEN_MEMSYS_32_1_INST_CLOCK_ENABLE_STATUS_MEMSYS1_SCB_CLOCK_ENABLE_STATUS_SHIFT 2
-
-/* CLKGEN :: MEMSYS_32_1_INST_CLOCK_ENABLE_STATUS :: MEMSYS1_GISB_CLOCK_ENABLE_STATUS [01:01] */
-#define BCHP_CLKGEN_MEMSYS_32_1_INST_CLOCK_ENABLE_STATUS_MEMSYS1_GISB_CLOCK_ENABLE_STATUS_MASK 0x00000002
-#define BCHP_CLKGEN_MEMSYS_32_1_INST_CLOCK_ENABLE_STATUS_MEMSYS1_GISB_CLOCK_ENABLE_STATUS_SHIFT 1
-
-/* CLKGEN :: MEMSYS_32_1_INST_CLOCK_ENABLE_STATUS :: MEMSYS1_54_CLOCK_ENABLE_STATUS [00:00] */
-#define BCHP_CLKGEN_MEMSYS_32_1_INST_CLOCK_ENABLE_STATUS_MEMSYS1_54_CLOCK_ENABLE_STATUS_MASK 0x00000001
-#define BCHP_CLKGEN_MEMSYS_32_1_INST_CLOCK_ENABLE_STATUS_MEMSYS1_54_CLOCK_ENABLE_STATUS_SHIFT 0
-
-/***************************************************************************
- *MEMSYS_32_1_INST_OBSERVE_CLOCK - Memsys 32 1 inst observe clock
- ***************************************************************************/
-/* CLKGEN :: MEMSYS_32_1_INST_OBSERVE_CLOCK :: reserved0 [31:06] */
-#define BCHP_CLKGEN_MEMSYS_32_1_INST_OBSERVE_CLOCK_reserved0_MASK 0xffffffc0
-#define BCHP_CLKGEN_MEMSYS_32_1_INST_OBSERVE_CLOCK_reserved0_SHIFT 6
-
-/* CLKGEN :: MEMSYS_32_1_INST_OBSERVE_CLOCK :: MEMSYS1_ENABLE_OBSERVE_CLOCK [05:05] */
-#define BCHP_CLKGEN_MEMSYS_32_1_INST_OBSERVE_CLOCK_MEMSYS1_ENABLE_OBSERVE_CLOCK_MASK 0x00000020
-#define BCHP_CLKGEN_MEMSYS_32_1_INST_OBSERVE_CLOCK_MEMSYS1_ENABLE_OBSERVE_CLOCK_SHIFT 5
-#define BCHP_CLKGEN_MEMSYS_32_1_INST_OBSERVE_CLOCK_MEMSYS1_ENABLE_OBSERVE_CLOCK_DEFAULT 0x00000000
-
-/* CLKGEN :: MEMSYS_32_1_INST_OBSERVE_CLOCK :: MEMSYS1_ENABLE_DIVIDER_OBSERVE_CLOCK [04:04] */
-#define BCHP_CLKGEN_MEMSYS_32_1_INST_OBSERVE_CLOCK_MEMSYS1_ENABLE_DIVIDER_OBSERVE_CLOCK_MASK 0x00000010
-#define BCHP_CLKGEN_MEMSYS_32_1_INST_OBSERVE_CLOCK_MEMSYS1_ENABLE_DIVIDER_OBSERVE_CLOCK_SHIFT 4
-#define BCHP_CLKGEN_MEMSYS_32_1_INST_OBSERVE_CLOCK_MEMSYS1_ENABLE_DIVIDER_OBSERVE_CLOCK_DEFAULT 0x00000000
-
-/* CLKGEN :: MEMSYS_32_1_INST_OBSERVE_CLOCK :: MEMSYS1_CONTROL_OBSERVE_CLOCK [03:00] */
-#define BCHP_CLKGEN_MEMSYS_32_1_INST_OBSERVE_CLOCK_MEMSYS1_CONTROL_OBSERVE_CLOCK_MASK 0x0000000f
-#define BCHP_CLKGEN_MEMSYS_32_1_INST_OBSERVE_CLOCK_MEMSYS1_CONTROL_OBSERVE_CLOCK_SHIFT 0
-#define BCHP_CLKGEN_MEMSYS_32_1_INST_OBSERVE_CLOCK_MEMSYS1_CONTROL_OBSERVE_CLOCK_DEFAULT 0x00000000
-
-/***************************************************************************
- *MEMSYS_32_1_INST_STATUS - Memsys 32 1 inst status
- ***************************************************************************/
-/* CLKGEN :: MEMSYS_32_1_INST_STATUS :: reserved0 [31:01] */
-#define BCHP_CLKGEN_MEMSYS_32_1_INST_STATUS_reserved0_MASK 0xfffffffe
-#define BCHP_CLKGEN_MEMSYS_32_1_INST_STATUS_reserved0_SHIFT 1
-
-/* CLKGEN :: MEMSYS_32_1_INST_STATUS :: MEMSYS1_PLL_LOCKED_STATUS [00:00] */
-#define BCHP_CLKGEN_MEMSYS_32_1_INST_STATUS_MEMSYS1_PLL_LOCKED_STATUS_MASK 0x00000001
-#define BCHP_CLKGEN_MEMSYS_32_1_INST_STATUS_MEMSYS1_PLL_LOCKED_STATUS_SHIFT 0
-
-/***************************************************************************
- *MOCAMAC_TOP_INST_CKTAPSEL - Mocamac top inst cktapsel
- ***************************************************************************/
-/* CLKGEN :: MOCAMAC_TOP_INST_CKTAPSEL :: reserved0 [31:12] */
-#define BCHP_CLKGEN_MOCAMAC_TOP_INST_CKTAPSEL_reserved0_MASK 0xfffff000
-#define BCHP_CLKGEN_MOCAMAC_TOP_INST_CKTAPSEL_reserved0_SHIFT 12
-
-/* CLKGEN :: MOCAMAC_TOP_INST_CKTAPSEL :: SCB_CKTAP1_CKTAPSEL [11:06] */
-#define BCHP_CLKGEN_MOCAMAC_TOP_INST_CKTAPSEL_SCB_CKTAP1_CKTAPSEL_MASK 0x00000fc0
-#define BCHP_CLKGEN_MOCAMAC_TOP_INST_CKTAPSEL_SCB_CKTAP1_CKTAPSEL_SHIFT 6
-#define BCHP_CLKGEN_MOCAMAC_TOP_INST_CKTAPSEL_SCB_CKTAP1_CKTAPSEL_DEFAULT 0x00000000
-
-/* CLKGEN :: MOCAMAC_TOP_INST_CKTAPSEL :: SCB_CKTAP0_CKTAPSEL [05:00] */
-#define BCHP_CLKGEN_MOCAMAC_TOP_INST_CKTAPSEL_SCB_CKTAP0_CKTAPSEL_MASK 0x0000003f
-#define BCHP_CLKGEN_MOCAMAC_TOP_INST_CKTAPSEL_SCB_CKTAP0_CKTAPSEL_SHIFT 0
-#define BCHP_CLKGEN_MOCAMAC_TOP_INST_CKTAPSEL_SCB_CKTAP0_CKTAPSEL_DEFAULT 0x00000000
-
-/***************************************************************************
- *MOCAMAC_TOP_INST_CLOCK_ENABLE - Mocamac top inst clock enable
- ***************************************************************************/
-/* CLKGEN :: MOCAMAC_TOP_INST_CLOCK_ENABLE :: reserved0 [31:03] */
-#define BCHP_CLKGEN_MOCAMAC_TOP_INST_CLOCK_ENABLE_reserved0_MASK 0xfffffff8
-#define BCHP_CLKGEN_MOCAMAC_TOP_INST_CLOCK_ENABLE_reserved0_SHIFT 3
-
-/* CLKGEN :: MOCAMAC_TOP_INST_CLOCK_ENABLE :: MOCAMAC_SCB_CLOCK_ENABLE [02:02] */
-#define BCHP_CLKGEN_MOCAMAC_TOP_INST_CLOCK_ENABLE_MOCAMAC_SCB_CLOCK_ENABLE_MASK 0x00000004
-#define BCHP_CLKGEN_MOCAMAC_TOP_INST_CLOCK_ENABLE_MOCAMAC_SCB_CLOCK_ENABLE_SHIFT 2
-#define BCHP_CLKGEN_MOCAMAC_TOP_INST_CLOCK_ENABLE_MOCAMAC_SCB_CLOCK_ENABLE_DEFAULT 0x00000001
-
-/* CLKGEN :: MOCAMAC_TOP_INST_CLOCK_ENABLE :: MOCAMAC_GISB_CLOCK_ENABLE [01:01] */
-#define BCHP_CLKGEN_MOCAMAC_TOP_INST_CLOCK_ENABLE_MOCAMAC_GISB_CLOCK_ENABLE_MASK 0x00000002
-#define BCHP_CLKGEN_MOCAMAC_TOP_INST_CLOCK_ENABLE_MOCAMAC_GISB_CLOCK_ENABLE_SHIFT 1
-#define BCHP_CLKGEN_MOCAMAC_TOP_INST_CLOCK_ENABLE_MOCAMAC_GISB_CLOCK_ENABLE_DEFAULT 0x00000001
-
-/* CLKGEN :: MOCAMAC_TOP_INST_CLOCK_ENABLE :: MOCAMAC_54_CLOCK_ENABLE [00:00] */
-#define BCHP_CLKGEN_MOCAMAC_TOP_INST_CLOCK_ENABLE_MOCAMAC_54_CLOCK_ENABLE_MASK 0x00000001
-#define BCHP_CLKGEN_MOCAMAC_TOP_INST_CLOCK_ENABLE_MOCAMAC_54_CLOCK_ENABLE_SHIFT 0
-#define BCHP_CLKGEN_MOCAMAC_TOP_INST_CLOCK_ENABLE_MOCAMAC_54_CLOCK_ENABLE_DEFAULT 0x00000001
-
-/***************************************************************************
- *MOCAMAC_TOP_INST_CLOCK_ENABLE_STATUS - Clock Enable Status
- ***************************************************************************/
-/* CLKGEN :: MOCAMAC_TOP_INST_CLOCK_ENABLE_STATUS :: reserved0 [31:03] */
-#define BCHP_CLKGEN_MOCAMAC_TOP_INST_CLOCK_ENABLE_STATUS_reserved0_MASK 0xfffffff8
-#define BCHP_CLKGEN_MOCAMAC_TOP_INST_CLOCK_ENABLE_STATUS_reserved0_SHIFT 3
-
-/* CLKGEN :: MOCAMAC_TOP_INST_CLOCK_ENABLE_STATUS :: MOCAMAC_SCB_CLOCK_ENABLE_STATUS [02:02] */
-#define BCHP_CLKGEN_MOCAMAC_TOP_INST_CLOCK_ENABLE_STATUS_MOCAMAC_SCB_CLOCK_ENABLE_STATUS_MASK 0x00000004
-#define BCHP_CLKGEN_MOCAMAC_TOP_INST_CLOCK_ENABLE_STATUS_MOCAMAC_SCB_CLOCK_ENABLE_STATUS_SHIFT 2
-
-/* CLKGEN :: MOCAMAC_TOP_INST_CLOCK_ENABLE_STATUS :: MOCAMAC_GISB_CLOCK_ENABLE_STATUS [01:01] */
-#define BCHP_CLKGEN_MOCAMAC_TOP_INST_CLOCK_ENABLE_STATUS_MOCAMAC_GISB_CLOCK_ENABLE_STATUS_MASK 0x00000002
-#define BCHP_CLKGEN_MOCAMAC_TOP_INST_CLOCK_ENABLE_STATUS_MOCAMAC_GISB_CLOCK_ENABLE_STATUS_SHIFT 1
-
-/* CLKGEN :: MOCAMAC_TOP_INST_CLOCK_ENABLE_STATUS :: MOCAMAC_54_CLOCK_ENABLE_STATUS [00:00] */
-#define BCHP_CLKGEN_MOCAMAC_TOP_INST_CLOCK_ENABLE_STATUS_MOCAMAC_54_CLOCK_ENABLE_STATUS_MASK 0x00000001
-#define BCHP_CLKGEN_MOCAMAC_TOP_INST_CLOCK_ENABLE_STATUS_MOCAMAC_54_CLOCK_ENABLE_STATUS_SHIFT 0
-
-/***************************************************************************
- *MOCAMAC_TOP_INST_OBSERVE_CLOCK - Mocamac top inst observe clock
- ***************************************************************************/
-/* CLKGEN :: MOCAMAC_TOP_INST_OBSERVE_CLOCK :: reserved0 [31:06] */
-#define BCHP_CLKGEN_MOCAMAC_TOP_INST_OBSERVE_CLOCK_reserved0_MASK 0xffffffc0
-#define BCHP_CLKGEN_MOCAMAC_TOP_INST_OBSERVE_CLOCK_reserved0_SHIFT 6
-
-/* CLKGEN :: MOCAMAC_TOP_INST_OBSERVE_CLOCK :: MOCAMAC_ENABLE_OBSERVE_CLOCK [05:05] */
-#define BCHP_CLKGEN_MOCAMAC_TOP_INST_OBSERVE_CLOCK_MOCAMAC_ENABLE_OBSERVE_CLOCK_MASK 0x00000020
-#define BCHP_CLKGEN_MOCAMAC_TOP_INST_OBSERVE_CLOCK_MOCAMAC_ENABLE_OBSERVE_CLOCK_SHIFT 5
-#define BCHP_CLKGEN_MOCAMAC_TOP_INST_OBSERVE_CLOCK_MOCAMAC_ENABLE_OBSERVE_CLOCK_DEFAULT 0x00000000
-
-/* CLKGEN :: MOCAMAC_TOP_INST_OBSERVE_CLOCK :: MOCAMAC_ENABLE_DIVIDER_OBSERVE_CLOCK [04:04] */
-#define BCHP_CLKGEN_MOCAMAC_TOP_INST_OBSERVE_CLOCK_MOCAMAC_ENABLE_DIVIDER_OBSERVE_CLOCK_MASK 0x00000010
-#define BCHP_CLKGEN_MOCAMAC_TOP_INST_OBSERVE_CLOCK_MOCAMAC_ENABLE_DIVIDER_OBSERVE_CLOCK_SHIFT 4
-#define BCHP_CLKGEN_MOCAMAC_TOP_INST_OBSERVE_CLOCK_MOCAMAC_ENABLE_DIVIDER_OBSERVE_CLOCK_DEFAULT 0x00000000
-
-/* CLKGEN :: MOCAMAC_TOP_INST_OBSERVE_CLOCK :: MOCAMAC_CONTROL_OBSERVE_CLOCK [03:00] */
-#define BCHP_CLKGEN_MOCAMAC_TOP_INST_OBSERVE_CLOCK_MOCAMAC_CONTROL_OBSERVE_CLOCK_MASK 0x0000000f
-#define BCHP_CLKGEN_MOCAMAC_TOP_INST_OBSERVE_CLOCK_MOCAMAC_CONTROL_OBSERVE_CLOCK_SHIFT 0
-#define BCHP_CLKGEN_MOCAMAC_TOP_INST_OBSERVE_CLOCK_MOCAMAC_CONTROL_OBSERVE_CLOCK_DEFAULT 0x00000000
-
-/***************************************************************************
- *MOCAPHY_TOP_INST_CLOCK_ENABLE - Mocaphy top inst clock enable
- ***************************************************************************/
-/* CLKGEN :: MOCAPHY_TOP_INST_CLOCK_ENABLE :: reserved0 [31:02] */
-#define BCHP_CLKGEN_MOCAPHY_TOP_INST_CLOCK_ENABLE_reserved0_MASK 0xfffffffc
-#define BCHP_CLKGEN_MOCAPHY_TOP_INST_CLOCK_ENABLE_reserved0_SHIFT 2
-
-/* CLKGEN :: MOCAPHY_TOP_INST_CLOCK_ENABLE :: MOCAPHY_GISB_CLOCK_ENABLE [01:01] */
-#define BCHP_CLKGEN_MOCAPHY_TOP_INST_CLOCK_ENABLE_MOCAPHY_GISB_CLOCK_ENABLE_MASK 0x00000002
-#define BCHP_CLKGEN_MOCAPHY_TOP_INST_CLOCK_ENABLE_MOCAPHY_GISB_CLOCK_ENABLE_SHIFT 1
-#define BCHP_CLKGEN_MOCAPHY_TOP_INST_CLOCK_ENABLE_MOCAPHY_GISB_CLOCK_ENABLE_DEFAULT 0x00000001
-
-/* CLKGEN :: MOCAPHY_TOP_INST_CLOCK_ENABLE :: MOCAPHY_54_CLOCK_ENABLE [00:00] */
-#define BCHP_CLKGEN_MOCAPHY_TOP_INST_CLOCK_ENABLE_MOCAPHY_54_CLOCK_ENABLE_MASK 0x00000001
-#define BCHP_CLKGEN_MOCAPHY_TOP_INST_CLOCK_ENABLE_MOCAPHY_54_CLOCK_ENABLE_SHIFT 0
-#define BCHP_CLKGEN_MOCAPHY_TOP_INST_CLOCK_ENABLE_MOCAPHY_54_CLOCK_ENABLE_DEFAULT 0x00000001
-
-/***************************************************************************
- *MOCAPHY_TOP_INST_CLOCK_ENABLE_STATUS - Clock Enable Status
- ***************************************************************************/
-/* CLKGEN :: MOCAPHY_TOP_INST_CLOCK_ENABLE_STATUS :: reserved0 [31:02] */
-#define BCHP_CLKGEN_MOCAPHY_TOP_INST_CLOCK_ENABLE_STATUS_reserved0_MASK 0xfffffffc
-#define BCHP_CLKGEN_MOCAPHY_TOP_INST_CLOCK_ENABLE_STATUS_reserved0_SHIFT 2
-
-/* CLKGEN :: MOCAPHY_TOP_INST_CLOCK_ENABLE_STATUS :: MOCAPHY_GISB_CLOCK_ENABLE_STATUS [01:01] */
-#define BCHP_CLKGEN_MOCAPHY_TOP_INST_CLOCK_ENABLE_STATUS_MOCAPHY_GISB_CLOCK_ENABLE_STATUS_MASK 0x00000002
-#define BCHP_CLKGEN_MOCAPHY_TOP_INST_CLOCK_ENABLE_STATUS_MOCAPHY_GISB_CLOCK_ENABLE_STATUS_SHIFT 1
-
-/* CLKGEN :: MOCAPHY_TOP_INST_CLOCK_ENABLE_STATUS :: MOCAPHY_54_CLOCK_ENABLE_STATUS [00:00] */
-#define BCHP_CLKGEN_MOCAPHY_TOP_INST_CLOCK_ENABLE_STATUS_MOCAPHY_54_CLOCK_ENABLE_STATUS_MASK 0x00000001
-#define BCHP_CLKGEN_MOCAPHY_TOP_INST_CLOCK_ENABLE_STATUS_MOCAPHY_54_CLOCK_ENABLE_STATUS_SHIFT 0
-
-/***************************************************************************
- *MOCAPHY_TOP_INST_OBSERVE_CLOCK - Mocaphy top inst observe clock
- ***************************************************************************/
-/* CLKGEN :: MOCAPHY_TOP_INST_OBSERVE_CLOCK :: reserved0 [31:06] */
-#define BCHP_CLKGEN_MOCAPHY_TOP_INST_OBSERVE_CLOCK_reserved0_MASK 0xffffffc0
-#define BCHP_CLKGEN_MOCAPHY_TOP_INST_OBSERVE_CLOCK_reserved0_SHIFT 6
-
-/* CLKGEN :: MOCAPHY_TOP_INST_OBSERVE_CLOCK :: MOCAPHY_ENABLE_OBSERVE_CLOCK [05:05] */
-#define BCHP_CLKGEN_MOCAPHY_TOP_INST_OBSERVE_CLOCK_MOCAPHY_ENABLE_OBSERVE_CLOCK_MASK 0x00000020
-#define BCHP_CLKGEN_MOCAPHY_TOP_INST_OBSERVE_CLOCK_MOCAPHY_ENABLE_OBSERVE_CLOCK_SHIFT 5
-#define BCHP_CLKGEN_MOCAPHY_TOP_INST_OBSERVE_CLOCK_MOCAPHY_ENABLE_OBSERVE_CLOCK_DEFAULT 0x00000000
-
-/* CLKGEN :: MOCAPHY_TOP_INST_OBSERVE_CLOCK :: MOCAPHY_ENABLE_DIVIDER_OBSERVE_CLOCK [04:04] */
-#define BCHP_CLKGEN_MOCAPHY_TOP_INST_OBSERVE_CLOCK_MOCAPHY_ENABLE_DIVIDER_OBSERVE_CLOCK_MASK 0x00000010
-#define BCHP_CLKGEN_MOCAPHY_TOP_INST_OBSERVE_CLOCK_MOCAPHY_ENABLE_DIVIDER_OBSERVE_CLOCK_SHIFT 4
-#define BCHP_CLKGEN_MOCAPHY_TOP_INST_OBSERVE_CLOCK_MOCAPHY_ENABLE_DIVIDER_OBSERVE_CLOCK_DEFAULT 0x00000000
-
-/* CLKGEN :: MOCAPHY_TOP_INST_OBSERVE_CLOCK :: MOCAPHY_CONTROL_OBSERVE_CLOCK [03:00] */
-#define BCHP_CLKGEN_MOCAPHY_TOP_INST_OBSERVE_CLOCK_MOCAPHY_CONTROL_OBSERVE_CLOCK_MASK 0x0000000f
-#define BCHP_CLKGEN_MOCAPHY_TOP_INST_OBSERVE_CLOCK_MOCAPHY_CONTROL_OBSERVE_CLOCK_SHIFT 0
-#define BCHP_CLKGEN_MOCAPHY_TOP_INST_OBSERVE_CLOCK_MOCAPHY_CONTROL_OBSERVE_CLOCK_DEFAULT 0x00000000
-
-/***************************************************************************
- *PAD_BYP_CLK_0_OBSERVATION - Select observation clk
- ***************************************************************************/
-/* CLKGEN :: PAD_BYP_CLK_0_OBSERVATION :: reserved0 [31:09] */
-#define BCHP_CLKGEN_PAD_BYP_CLK_0_OBSERVATION_reserved0_MASK 0xfffffe00
-#define BCHP_CLKGEN_PAD_BYP_CLK_0_OBSERVATION_reserved0_SHIFT 9
-
-/* CLKGEN :: PAD_BYP_CLK_0_OBSERVATION :: SELECT_OBSERVE_CLK [08:08] */
-#define BCHP_CLKGEN_PAD_BYP_CLK_0_OBSERVATION_SELECT_OBSERVE_CLK_MASK 0x00000100
-#define BCHP_CLKGEN_PAD_BYP_CLK_0_OBSERVATION_SELECT_OBSERVE_CLK_SHIFT 8
-#define BCHP_CLKGEN_PAD_BYP_CLK_0_OBSERVATION_SELECT_OBSERVE_CLK_DEFAULT 0x00000000
-
-/* CLKGEN :: PAD_BYP_CLK_0_OBSERVATION :: OBSERVE_MUX_SELECT [07:01] */
-#define BCHP_CLKGEN_PAD_BYP_CLK_0_OBSERVATION_OBSERVE_MUX_SELECT_MASK 0x000000fe
-#define BCHP_CLKGEN_PAD_BYP_CLK_0_OBSERVATION_OBSERVE_MUX_SELECT_SHIFT 1
-#define BCHP_CLKGEN_PAD_BYP_CLK_0_OBSERVATION_OBSERVE_MUX_SELECT_DEFAULT 0x00000000
-
-/* CLKGEN :: PAD_BYP_CLK_0_OBSERVATION :: OBSERVE_DIV_ENABLE [00:00] */
-#define BCHP_CLKGEN_PAD_BYP_CLK_0_OBSERVATION_OBSERVE_DIV_ENABLE_MASK 0x00000001
-#define BCHP_CLKGEN_PAD_BYP_CLK_0_OBSERVATION_OBSERVE_DIV_ENABLE_SHIFT 0
-#define BCHP_CLKGEN_PAD_BYP_CLK_0_OBSERVATION_OBSERVE_DIV_ENABLE_DEFAULT 0x00000000
-
-/***************************************************************************
- *PAD_BYP_CLK_1_OBSERVATION - Select observation clk
- ***************************************************************************/
-/* CLKGEN :: PAD_BYP_CLK_1_OBSERVATION :: reserved0 [31:09] */
-#define BCHP_CLKGEN_PAD_BYP_CLK_1_OBSERVATION_reserved0_MASK 0xfffffe00
-#define BCHP_CLKGEN_PAD_BYP_CLK_1_OBSERVATION_reserved0_SHIFT 9
-
-/* CLKGEN :: PAD_BYP_CLK_1_OBSERVATION :: SELECT_OBSERVE_CLK [08:08] */
-#define BCHP_CLKGEN_PAD_BYP_CLK_1_OBSERVATION_SELECT_OBSERVE_CLK_MASK 0x00000100
-#define BCHP_CLKGEN_PAD_BYP_CLK_1_OBSERVATION_SELECT_OBSERVE_CLK_SHIFT 8
-#define BCHP_CLKGEN_PAD_BYP_CLK_1_OBSERVATION_SELECT_OBSERVE_CLK_DEFAULT 0x00000000
-
-/* CLKGEN :: PAD_BYP_CLK_1_OBSERVATION :: OBSERVE_MUX_SELECT [07:01] */
-#define BCHP_CLKGEN_PAD_BYP_CLK_1_OBSERVATION_OBSERVE_MUX_SELECT_MASK 0x000000fe
-#define BCHP_CLKGEN_PAD_BYP_CLK_1_OBSERVATION_OBSERVE_MUX_SELECT_SHIFT 1
-#define BCHP_CLKGEN_PAD_BYP_CLK_1_OBSERVATION_OBSERVE_MUX_SELECT_DEFAULT 0x00000000
-
-/* CLKGEN :: PAD_BYP_CLK_1_OBSERVATION :: OBSERVE_DIV_ENABLE [00:00] */
-#define BCHP_CLKGEN_PAD_BYP_CLK_1_OBSERVATION_OBSERVE_DIV_ENABLE_MASK 0x00000001
-#define BCHP_CLKGEN_PAD_BYP_CLK_1_OBSERVATION_OBSERVE_DIV_ENABLE_SHIFT 0
-#define BCHP_CLKGEN_PAD_BYP_CLK_1_OBSERVATION_OBSERVE_DIV_ENABLE_DEFAULT 0x00000000
-
-/***************************************************************************
- *PAD_CLOCK_DISABLE - Disable PAD's clocks
- ***************************************************************************/
-/* CLKGEN :: PAD_CLOCK_DISABLE :: reserved0 [31:04] */
-#define BCHP_CLKGEN_PAD_CLOCK_DISABLE_reserved0_MASK 0xfffffff0
-#define BCHP_CLKGEN_PAD_CLOCK_DISABLE_reserved0_SHIFT 4
-
-/* CLKGEN :: PAD_CLOCK_DISABLE :: DISABLE_PAD_OUTPUT_SC_CLOCK [03:03] */
-#define BCHP_CLKGEN_PAD_CLOCK_DISABLE_DISABLE_PAD_OUTPUT_SC_CLOCK_MASK 0x00000008
-#define BCHP_CLKGEN_PAD_CLOCK_DISABLE_DISABLE_PAD_OUTPUT_SC_CLOCK_SHIFT 3
-#define BCHP_CLKGEN_PAD_CLOCK_DISABLE_DISABLE_PAD_OUTPUT_SC_CLOCK_DEFAULT 0x00000000
-
-/* CLKGEN :: PAD_CLOCK_DISABLE :: DISABLE_PAD_OUTPUT_CODECMCLK_CLOCK [02:02] */
-#define BCHP_CLKGEN_PAD_CLOCK_DISABLE_DISABLE_PAD_OUTPUT_CODECMCLK_CLOCK_MASK 0x00000004
-#define BCHP_CLKGEN_PAD_CLOCK_DISABLE_DISABLE_PAD_OUTPUT_CODECMCLK_CLOCK_SHIFT 2
-#define BCHP_CLKGEN_PAD_CLOCK_DISABLE_DISABLE_PAD_OUTPUT_CODECMCLK_CLOCK_DEFAULT 0x00000000
-
-/* CLKGEN :: PAD_CLOCK_DISABLE :: DISABLE_PAD_OUTPUT_BYPCLK1_CLOCK [01:01] */
-#define BCHP_CLKGEN_PAD_CLOCK_DISABLE_DISABLE_PAD_OUTPUT_BYPCLK1_CLOCK_MASK 0x00000002
-#define BCHP_CLKGEN_PAD_CLOCK_DISABLE_DISABLE_PAD_OUTPUT_BYPCLK1_CLOCK_SHIFT 1
-#define BCHP_CLKGEN_PAD_CLOCK_DISABLE_DISABLE_PAD_OUTPUT_BYPCLK1_CLOCK_DEFAULT 0x00000000
-
-/* CLKGEN :: PAD_CLOCK_DISABLE :: DISABLE_PAD_OUTPUT_BYPCLK0_CLOCK [00:00] */
-#define BCHP_CLKGEN_PAD_CLOCK_DISABLE_DISABLE_PAD_OUTPUT_BYPCLK0_CLOCK_MASK 0x00000001
-#define BCHP_CLKGEN_PAD_CLOCK_DISABLE_DISABLE_PAD_OUTPUT_BYPCLK0_CLOCK_SHIFT 0
-#define BCHP_CLKGEN_PAD_CLOCK_DISABLE_DISABLE_PAD_OUTPUT_BYPCLK0_CLOCK_DEFAULT 0x00000000
-
-/***************************************************************************
- *PAD_CLOCK_DISABLE_STATUS - Clock Disable Status
- ***************************************************************************/
-/* CLKGEN :: PAD_CLOCK_DISABLE_STATUS :: reserved0 [31:04] */
-#define BCHP_CLKGEN_PAD_CLOCK_DISABLE_STATUS_reserved0_MASK 0xfffffff0
-#define BCHP_CLKGEN_PAD_CLOCK_DISABLE_STATUS_reserved0_SHIFT 4
-
-/* CLKGEN :: PAD_CLOCK_DISABLE_STATUS :: DISABLE_PAD_OUTPUT_SC_CLOCK_STATUS [03:03] */
-#define BCHP_CLKGEN_PAD_CLOCK_DISABLE_STATUS_DISABLE_PAD_OUTPUT_SC_CLOCK_STATUS_MASK 0x00000008
-#define BCHP_CLKGEN_PAD_CLOCK_DISABLE_STATUS_DISABLE_PAD_OUTPUT_SC_CLOCK_STATUS_SHIFT 3
-
-/* CLKGEN :: PAD_CLOCK_DISABLE_STATUS :: DISABLE_PAD_OUTPUT_CODECMCLK_CLOCK_STATUS [02:02] */
-#define BCHP_CLKGEN_PAD_CLOCK_DISABLE_STATUS_DISABLE_PAD_OUTPUT_CODECMCLK_CLOCK_STATUS_MASK 0x00000004
-#define BCHP_CLKGEN_PAD_CLOCK_DISABLE_STATUS_DISABLE_PAD_OUTPUT_CODECMCLK_CLOCK_STATUS_SHIFT 2
-
-/* CLKGEN :: PAD_CLOCK_DISABLE_STATUS :: DISABLE_PAD_OUTPUT_BYPCLK1_CLOCK_STATUS [01:01] */
-#define BCHP_CLKGEN_PAD_CLOCK_DISABLE_STATUS_DISABLE_PAD_OUTPUT_BYPCLK1_CLOCK_STATUS_MASK 0x00000002
-#define BCHP_CLKGEN_PAD_CLOCK_DISABLE_STATUS_DISABLE_PAD_OUTPUT_BYPCLK1_CLOCK_STATUS_SHIFT 1
-
-/* CLKGEN :: PAD_CLOCK_DISABLE_STATUS :: DISABLE_PAD_OUTPUT_BYPCLK0_CLOCK_STATUS [00:00] */
-#define BCHP_CLKGEN_PAD_CLOCK_DISABLE_STATUS_DISABLE_PAD_OUTPUT_BYPCLK0_CLOCK_STATUS_MASK 0x00000001
-#define BCHP_CLKGEN_PAD_CLOCK_DISABLE_STATUS_DISABLE_PAD_OUTPUT_BYPCLK0_CLOCK_STATUS_SHIFT 0
-
-/***************************************************************************
- *PAD_CODEC_MCLK_OBSERVATION - Select observation clk
- ***************************************************************************/
-/* CLKGEN :: PAD_CODEC_MCLK_OBSERVATION :: reserved0 [31:09] */
-#define BCHP_CLKGEN_PAD_CODEC_MCLK_OBSERVATION_reserved0_MASK 0xfffffe00
-#define BCHP_CLKGEN_PAD_CODEC_MCLK_OBSERVATION_reserved0_SHIFT 9
-
-/* CLKGEN :: PAD_CODEC_MCLK_OBSERVATION :: SELECT_OBSERVE_CLK [08:08] */
-#define BCHP_CLKGEN_PAD_CODEC_MCLK_OBSERVATION_SELECT_OBSERVE_CLK_MASK 0x00000100
-#define BCHP_CLKGEN_PAD_CODEC_MCLK_OBSERVATION_SELECT_OBSERVE_CLK_SHIFT 8
-#define BCHP_CLKGEN_PAD_CODEC_MCLK_OBSERVATION_SELECT_OBSERVE_CLK_DEFAULT 0x00000000
-
-/* CLKGEN :: PAD_CODEC_MCLK_OBSERVATION :: OBSERVE_MUX_SELECT [07:01] */
-#define BCHP_CLKGEN_PAD_CODEC_MCLK_OBSERVATION_OBSERVE_MUX_SELECT_MASK 0x000000fe
-#define BCHP_CLKGEN_PAD_CODEC_MCLK_OBSERVATION_OBSERVE_MUX_SELECT_SHIFT 1
-#define BCHP_CLKGEN_PAD_CODEC_MCLK_OBSERVATION_OBSERVE_MUX_SELECT_DEFAULT 0x00000000
-
-/* CLKGEN :: PAD_CODEC_MCLK_OBSERVATION :: OBSERVE_DIV_ENABLE [00:00] */
-#define BCHP_CLKGEN_PAD_CODEC_MCLK_OBSERVATION_OBSERVE_DIV_ENABLE_MASK 0x00000001
-#define BCHP_CLKGEN_PAD_CODEC_MCLK_OBSERVATION_OBSERVE_DIV_ENABLE_SHIFT 0
-#define BCHP_CLKGEN_PAD_CODEC_MCLK_OBSERVATION_OBSERVE_DIV_ENABLE_DEFAULT 0x00000000
-
-/***************************************************************************
- *PAD_MUX_SELECT - Mux selects for Pad clocks
- ***************************************************************************/
-/* CLKGEN :: PAD_MUX_SELECT :: reserved0 [31:01] */
-#define BCHP_CLKGEN_PAD_MUX_SELECT_reserved0_MASK 0xfffffffe
-#define BCHP_CLKGEN_PAD_MUX_SELECT_reserved0_SHIFT 1
-
-/* CLKGEN :: PAD_MUX_SELECT :: PAD_OUTPUT_SC_CLOCK [00:00] */
-#define BCHP_CLKGEN_PAD_MUX_SELECT_PAD_OUTPUT_SC_CLOCK_MASK 0x00000001
-#define BCHP_CLKGEN_PAD_MUX_SELECT_PAD_OUTPUT_SC_CLOCK_SHIFT 0
-#define BCHP_CLKGEN_PAD_MUX_SELECT_PAD_OUTPUT_SC_CLOCK_DEFAULT 0x00000000
-
-/***************************************************************************
- *PCIE_X1_TOP_INST_CKTAPSEL - Pcie x1 top inst cktapsel
- ***************************************************************************/
-/* CLKGEN :: PCIE_X1_TOP_INST_CKTAPSEL :: reserved0 [31:12] */
-#define BCHP_CLKGEN_PCIE_X1_TOP_INST_CKTAPSEL_reserved0_MASK 0xfffff000
-#define BCHP_CLKGEN_PCIE_X1_TOP_INST_CKTAPSEL_reserved0_SHIFT 12
-
-/* CLKGEN :: PCIE_X1_TOP_INST_CKTAPSEL :: SCB_CKTAP1_CKTAPSEL [11:06] */
-#define BCHP_CLKGEN_PCIE_X1_TOP_INST_CKTAPSEL_SCB_CKTAP1_CKTAPSEL_MASK 0x00000fc0
-#define BCHP_CLKGEN_PCIE_X1_TOP_INST_CKTAPSEL_SCB_CKTAP1_CKTAPSEL_SHIFT 6
-#define BCHP_CLKGEN_PCIE_X1_TOP_INST_CKTAPSEL_SCB_CKTAP1_CKTAPSEL_DEFAULT 0x00000000
-
-/* CLKGEN :: PCIE_X1_TOP_INST_CKTAPSEL :: SCB_CKTAP0_CKTAPSEL [05:00] */
-#define BCHP_CLKGEN_PCIE_X1_TOP_INST_CKTAPSEL_SCB_CKTAP0_CKTAPSEL_MASK 0x0000003f
-#define BCHP_CLKGEN_PCIE_X1_TOP_INST_CKTAPSEL_SCB_CKTAP0_CKTAPSEL_SHIFT 0
-#define BCHP_CLKGEN_PCIE_X1_TOP_INST_CKTAPSEL_SCB_CKTAP0_CKTAPSEL_DEFAULT 0x00000000
-
-/***************************************************************************
- *PCIE_X1_TOP_INST_CLOCK_DISABLE - Disable PCIE_X1_TOP_INST's clocks
- ***************************************************************************/
-/* CLKGEN :: PCIE_X1_TOP_INST_CLOCK_DISABLE :: reserved0 [31:01] */
-#define BCHP_CLKGEN_PCIE_X1_TOP_INST_CLOCK_DISABLE_reserved0_MASK 0xfffffffe
-#define BCHP_CLKGEN_PCIE_X1_TOP_INST_CLOCK_DISABLE_reserved0_SHIFT 1
-
-/* CLKGEN :: PCIE_X1_TOP_INST_CLOCK_DISABLE :: DISABLE_PCIE_ALWAYSON_CLOCK [00:00] */
-#define BCHP_CLKGEN_PCIE_X1_TOP_INST_CLOCK_DISABLE_DISABLE_PCIE_ALWAYSON_CLOCK_MASK 0x00000001
-#define BCHP_CLKGEN_PCIE_X1_TOP_INST_CLOCK_DISABLE_DISABLE_PCIE_ALWAYSON_CLOCK_SHIFT 0
-#define BCHP_CLKGEN_PCIE_X1_TOP_INST_CLOCK_DISABLE_DISABLE_PCIE_ALWAYSON_CLOCK_DEFAULT 0x00000000
-
-/***************************************************************************
- *PCIE_X1_TOP_INST_CLOCK_DISABLE_STATUS - Clock Disable Status
- ***************************************************************************/
-/* CLKGEN :: PCIE_X1_TOP_INST_CLOCK_DISABLE_STATUS :: reserved0 [31:01] */
-#define BCHP_CLKGEN_PCIE_X1_TOP_INST_CLOCK_DISABLE_STATUS_reserved0_MASK 0xfffffffe
-#define BCHP_CLKGEN_PCIE_X1_TOP_INST_CLOCK_DISABLE_STATUS_reserved0_SHIFT 1
-
-/* CLKGEN :: PCIE_X1_TOP_INST_CLOCK_DISABLE_STATUS :: DISABLE_PCIE_ALWAYSON_CLOCK_STATUS [00:00] */
-#define BCHP_CLKGEN_PCIE_X1_TOP_INST_CLOCK_DISABLE_STATUS_DISABLE_PCIE_ALWAYSON_CLOCK_STATUS_MASK 0x00000001
-#define BCHP_CLKGEN_PCIE_X1_TOP_INST_CLOCK_DISABLE_STATUS_DISABLE_PCIE_ALWAYSON_CLOCK_STATUS_SHIFT 0
-
-/***************************************************************************
- *PCIE_X1_TOP_INST_CLOCK_ENABLE - Pcie x1 top inst clock enable
- ***************************************************************************/
-/* CLKGEN :: PCIE_X1_TOP_INST_CLOCK_ENABLE :: reserved0 [31:04] */
-#define BCHP_CLKGEN_PCIE_X1_TOP_INST_CLOCK_ENABLE_reserved0_MASK 0xfffffff0
-#define BCHP_CLKGEN_PCIE_X1_TOP_INST_CLOCK_ENABLE_reserved0_SHIFT 4
-
-/* CLKGEN :: PCIE_X1_TOP_INST_CLOCK_ENABLE :: PCIE_SCB_CLOCK_ENABLE [03:03] */
-#define BCHP_CLKGEN_PCIE_X1_TOP_INST_CLOCK_ENABLE_PCIE_SCB_CLOCK_ENABLE_MASK 0x00000008
-#define BCHP_CLKGEN_PCIE_X1_TOP_INST_CLOCK_ENABLE_PCIE_SCB_CLOCK_ENABLE_SHIFT 3
-#define BCHP_CLKGEN_PCIE_X1_TOP_INST_CLOCK_ENABLE_PCIE_SCB_CLOCK_ENABLE_DEFAULT 0x00000001
-
-/* CLKGEN :: PCIE_X1_TOP_INST_CLOCK_ENABLE :: PCIE_GISB_CLOCK_ENABLE [02:02] */
-#define BCHP_CLKGEN_PCIE_X1_TOP_INST_CLOCK_ENABLE_PCIE_GISB_CLOCK_ENABLE_MASK 0x00000004
-#define BCHP_CLKGEN_PCIE_X1_TOP_INST_CLOCK_ENABLE_PCIE_GISB_CLOCK_ENABLE_SHIFT 2
-#define BCHP_CLKGEN_PCIE_X1_TOP_INST_CLOCK_ENABLE_PCIE_GISB_CLOCK_ENABLE_DEFAULT 0x00000001
-
-/* CLKGEN :: PCIE_X1_TOP_INST_CLOCK_ENABLE :: PCIE_54_CLOCK_ENABLE [01:01] */
-#define BCHP_CLKGEN_PCIE_X1_TOP_INST_CLOCK_ENABLE_PCIE_54_CLOCK_ENABLE_MASK 0x00000002
-#define BCHP_CLKGEN_PCIE_X1_TOP_INST_CLOCK_ENABLE_PCIE_54_CLOCK_ENABLE_SHIFT 1
-#define BCHP_CLKGEN_PCIE_X1_TOP_INST_CLOCK_ENABLE_PCIE_54_CLOCK_ENABLE_DEFAULT 0x00000001
-
-/* CLKGEN :: PCIE_X1_TOP_INST_CLOCK_ENABLE :: PCIE_108_CLOCK_ENABLE [00:00] */
-#define BCHP_CLKGEN_PCIE_X1_TOP_INST_CLOCK_ENABLE_PCIE_108_CLOCK_ENABLE_MASK 0x00000001
-#define BCHP_CLKGEN_PCIE_X1_TOP_INST_CLOCK_ENABLE_PCIE_108_CLOCK_ENABLE_SHIFT 0
-#define BCHP_CLKGEN_PCIE_X1_TOP_INST_CLOCK_ENABLE_PCIE_108_CLOCK_ENABLE_DEFAULT 0x00000001
-
-/***************************************************************************
- *PCIE_X1_TOP_INST_CLOCK_ENABLE_STATUS - Clock Enable Status
- ***************************************************************************/
-/* CLKGEN :: PCIE_X1_TOP_INST_CLOCK_ENABLE_STATUS :: reserved0 [31:04] */
-#define BCHP_CLKGEN_PCIE_X1_TOP_INST_CLOCK_ENABLE_STATUS_reserved0_MASK 0xfffffff0
-#define BCHP_CLKGEN_PCIE_X1_TOP_INST_CLOCK_ENABLE_STATUS_reserved0_SHIFT 4
-
-/* CLKGEN :: PCIE_X1_TOP_INST_CLOCK_ENABLE_STATUS :: PCIE_SCB_CLOCK_ENABLE_STATUS [03:03] */
-#define BCHP_CLKGEN_PCIE_X1_TOP_INST_CLOCK_ENABLE_STATUS_PCIE_SCB_CLOCK_ENABLE_STATUS_MASK 0x00000008
-#define BCHP_CLKGEN_PCIE_X1_TOP_INST_CLOCK_ENABLE_STATUS_PCIE_SCB_CLOCK_ENABLE_STATUS_SHIFT 3
-
-/* CLKGEN :: PCIE_X1_TOP_INST_CLOCK_ENABLE_STATUS :: PCIE_GISB_CLOCK_ENABLE_STATUS [02:02] */
-#define BCHP_CLKGEN_PCIE_X1_TOP_INST_CLOCK_ENABLE_STATUS_PCIE_GISB_CLOCK_ENABLE_STATUS_MASK 0x00000004
-#define BCHP_CLKGEN_PCIE_X1_TOP_INST_CLOCK_ENABLE_STATUS_PCIE_GISB_CLOCK_ENABLE_STATUS_SHIFT 2
-
-/* CLKGEN :: PCIE_X1_TOP_INST_CLOCK_ENABLE_STATUS :: PCIE_54_CLOCK_ENABLE_STATUS [01:01] */
-#define BCHP_CLKGEN_PCIE_X1_TOP_INST_CLOCK_ENABLE_STATUS_PCIE_54_CLOCK_ENABLE_STATUS_MASK 0x00000002
-#define BCHP_CLKGEN_PCIE_X1_TOP_INST_CLOCK_ENABLE_STATUS_PCIE_54_CLOCK_ENABLE_STATUS_SHIFT 1
-
-/* CLKGEN :: PCIE_X1_TOP_INST_CLOCK_ENABLE_STATUS :: PCIE_108_CLOCK_ENABLE_STATUS [00:00] */
-#define BCHP_CLKGEN_PCIE_X1_TOP_INST_CLOCK_ENABLE_STATUS_PCIE_108_CLOCK_ENABLE_STATUS_MASK 0x00000001
-#define BCHP_CLKGEN_PCIE_X1_TOP_INST_CLOCK_ENABLE_STATUS_PCIE_108_CLOCK_ENABLE_STATUS_SHIFT 0
-
-/***************************************************************************
- *PCIE_X1_TOP_INST_OBSERVE_CLOCK - Pcie x1 top inst observe clock
- ***************************************************************************/
-/* CLKGEN :: PCIE_X1_TOP_INST_OBSERVE_CLOCK :: reserved0 [31:06] */
-#define BCHP_CLKGEN_PCIE_X1_TOP_INST_OBSERVE_CLOCK_reserved0_MASK 0xffffffc0
-#define BCHP_CLKGEN_PCIE_X1_TOP_INST_OBSERVE_CLOCK_reserved0_SHIFT 6
-
-/* CLKGEN :: PCIE_X1_TOP_INST_OBSERVE_CLOCK :: PCIE_ENABLE_OBSERVE_CLOCK [05:05] */
-#define BCHP_CLKGEN_PCIE_X1_TOP_INST_OBSERVE_CLOCK_PCIE_ENABLE_OBSERVE_CLOCK_MASK 0x00000020
-#define BCHP_CLKGEN_PCIE_X1_TOP_INST_OBSERVE_CLOCK_PCIE_ENABLE_OBSERVE_CLOCK_SHIFT 5
-#define BCHP_CLKGEN_PCIE_X1_TOP_INST_OBSERVE_CLOCK_PCIE_ENABLE_OBSERVE_CLOCK_DEFAULT 0x00000000
-
-/* CLKGEN :: PCIE_X1_TOP_INST_OBSERVE_CLOCK :: PCIE_ENABLE_DIVIDER_OBSERVE_CLOCK [04:04] */
-#define BCHP_CLKGEN_PCIE_X1_TOP_INST_OBSERVE_CLOCK_PCIE_ENABLE_DIVIDER_OBSERVE_CLOCK_MASK 0x00000010
-#define BCHP_CLKGEN_PCIE_X1_TOP_INST_OBSERVE_CLOCK_PCIE_ENABLE_DIVIDER_OBSERVE_CLOCK_SHIFT 4
-#define BCHP_CLKGEN_PCIE_X1_TOP_INST_OBSERVE_CLOCK_PCIE_ENABLE_DIVIDER_OBSERVE_CLOCK_DEFAULT 0x00000000
-
-/* CLKGEN :: PCIE_X1_TOP_INST_OBSERVE_CLOCK :: PCIE_CONTROL_OBSERVE_CLOCK [03:00] */
-#define BCHP_CLKGEN_PCIE_X1_TOP_INST_OBSERVE_CLOCK_PCIE_CONTROL_OBSERVE_CLOCK_MASK 0x0000000f
-#define BCHP_CLKGEN_PCIE_X1_TOP_INST_OBSERVE_CLOCK_PCIE_CONTROL_OBSERVE_CLOCK_SHIFT 0
-#define BCHP_CLKGEN_PCIE_X1_TOP_INST_OBSERVE_CLOCK_PCIE_CONTROL_OBSERVE_CLOCK_DEFAULT 0x00000000
-
-/***************************************************************************
- *PLL_AUDIO0_AUDIO0 - Pll audio0 audio0
- ***************************************************************************/
-/* CLKGEN :: PLL_AUDIO0_AUDIO0 :: reserved0 [31:01] */
-#define BCHP_CLKGEN_PLL_AUDIO0_AUDIO0_reserved0_MASK 0xfffffffe
-#define BCHP_CLKGEN_PLL_AUDIO0_AUDIO0_reserved0_SHIFT 1
-
-/* CLKGEN :: PLL_AUDIO0_AUDIO0 :: PM_PLLL_LDO_POWERDOWN_PLL_AUDIO0 [00:00] */
-#define BCHP_CLKGEN_PLL_AUDIO0_AUDIO0_PM_PLLL_LDO_POWERDOWN_PLL_AUDIO0_MASK 0x00000001
-#define BCHP_CLKGEN_PLL_AUDIO0_AUDIO0_PM_PLLL_LDO_POWERDOWN_PLL_AUDIO0_SHIFT 0
-#define BCHP_CLKGEN_PLL_AUDIO0_AUDIO0_PM_PLLL_LDO_POWERDOWN_PLL_AUDIO0_DEFAULT 0x00000000
-
-/***************************************************************************
- *PLL_AUDIO1_AUDIO1 - Pll audio1 audio1
- ***************************************************************************/
-/* CLKGEN :: PLL_AUDIO1_AUDIO1 :: reserved0 [31:01] */
-#define BCHP_CLKGEN_PLL_AUDIO1_AUDIO1_reserved0_MASK 0xfffffffe
-#define BCHP_CLKGEN_PLL_AUDIO1_AUDIO1_reserved0_SHIFT 1
-
-/* CLKGEN :: PLL_AUDIO1_AUDIO1 :: PM_PLLL_LDO_POWERDOWN_PLL_AUDIO1 [00:00] */
-#define BCHP_CLKGEN_PLL_AUDIO1_AUDIO1_PM_PLLL_LDO_POWERDOWN_PLL_AUDIO1_MASK 0x00000001
-#define BCHP_CLKGEN_PLL_AUDIO1_AUDIO1_PM_PLLL_LDO_POWERDOWN_PLL_AUDIO1_SHIFT 0
-#define BCHP_CLKGEN_PLL_AUDIO1_AUDIO1_PM_PLLL_LDO_POWERDOWN_PLL_AUDIO1_DEFAULT 0x00000000
-
-/***************************************************************************
- *PLL_CPU_GLITCHLESS_SWITCH_REQUEST - PLL_CPU Glitchless Clock Switching
- ***************************************************************************/
-/* CLKGEN :: PLL_CPU_GLITCHLESS_SWITCH_REQUEST :: reserved0 [31:09] */
-#define BCHP_CLKGEN_PLL_CPU_GLITCHLESS_SWITCH_REQUEST_reserved0_MASK 0xfffffe00
-#define BCHP_CLKGEN_PLL_CPU_GLITCHLESS_SWITCH_REQUEST_reserved0_SHIFT 9
-
-/* CLKGEN :: PLL_CPU_GLITCHLESS_SWITCH_REQUEST :: TRANSACTION_WAIT [08:01] */
-#define BCHP_CLKGEN_PLL_CPU_GLITCHLESS_SWITCH_REQUEST_TRANSACTION_WAIT_MASK 0x000001fe
-#define BCHP_CLKGEN_PLL_CPU_GLITCHLESS_SWITCH_REQUEST_TRANSACTION_WAIT_SHIFT 1
-#define BCHP_CLKGEN_PLL_CPU_GLITCHLESS_SWITCH_REQUEST_TRANSACTION_WAIT_DEFAULT 0x0000001f
-
-/* CLKGEN :: PLL_CPU_GLITCHLESS_SWITCH_REQUEST :: PLL_BYPASS_REQUEST [00:00] */
-#define BCHP_CLKGEN_PLL_CPU_GLITCHLESS_SWITCH_REQUEST_PLL_BYPASS_REQUEST_MASK 0x00000001
-#define BCHP_CLKGEN_PLL_CPU_GLITCHLESS_SWITCH_REQUEST_PLL_BYPASS_REQUEST_SHIFT 0
-#define BCHP_CLKGEN_PLL_CPU_GLITCHLESS_SWITCH_REQUEST_PLL_BYPASS_REQUEST_DEFAULT 0x00000000
-
-/***************************************************************************
- *PLL_CPU_GLITCHLESS_SWITCH_STATUS - PLL_CPU Glitchless Switching
- ***************************************************************************/
-/* CLKGEN :: PLL_CPU_GLITCHLESS_SWITCH_STATUS :: reserved0 [31:04] */
-#define BCHP_CLKGEN_PLL_CPU_GLITCHLESS_SWITCH_STATUS_reserved0_MASK 0xfffffff0
-#define BCHP_CLKGEN_PLL_CPU_GLITCHLESS_SWITCH_STATUS_reserved0_SHIFT 4
-
-/* CLKGEN :: PLL_CPU_GLITCHLESS_SWITCH_STATUS :: PLL_BYPASS_STATUS [03:00] */
-#define BCHP_CLKGEN_PLL_CPU_GLITCHLESS_SWITCH_STATUS_PLL_BYPASS_STATUS_MASK 0x0000000f
-#define BCHP_CLKGEN_PLL_CPU_GLITCHLESS_SWITCH_STATUS_PLL_BYPASS_STATUS_SHIFT 0
-
-/***************************************************************************
- *PLL_CPU_PLL_RESET_STATUS - PLL_CPU Reset Status
- ***************************************************************************/
-/* CLKGEN :: PLL_CPU_PLL_RESET_STATUS :: reserved0 [31:02] */
-#define BCHP_CLKGEN_PLL_CPU_PLL_RESET_STATUS_reserved0_MASK 0xfffffffc
-#define BCHP_CLKGEN_PLL_CPU_PLL_RESET_STATUS_reserved0_SHIFT 2
-
-/* CLKGEN :: PLL_CPU_PLL_RESET_STATUS :: PLL_DRESET_STATUS [01:01] */
-#define BCHP_CLKGEN_PLL_CPU_PLL_RESET_STATUS_PLL_DRESET_STATUS_MASK 0x00000002
-#define BCHP_CLKGEN_PLL_CPU_PLL_RESET_STATUS_PLL_DRESET_STATUS_SHIFT 1
-
-/* CLKGEN :: PLL_CPU_PLL_RESET_STATUS :: PLL_ARESET_STATUS [00:00] */
-#define BCHP_CLKGEN_PLL_CPU_PLL_RESET_STATUS_PLL_ARESET_STATUS_MASK 0x00000001
-#define BCHP_CLKGEN_PLL_CPU_PLL_RESET_STATUS_PLL_ARESET_STATUS_SHIFT 0
-
-/***************************************************************************
- *PLL_CPU_RDB_MACRO_CTRL - PLL RDB Macro Disable
- ***************************************************************************/
-/* CLKGEN :: PLL_CPU_RDB_MACRO_CTRL :: reserved0 [31:04] */
-#define BCHP_CLKGEN_PLL_CPU_RDB_MACRO_CTRL_reserved0_MASK 0xfffffff0
-#define BCHP_CLKGEN_PLL_CPU_RDB_MACRO_CTRL_reserved0_SHIFT 4
-
-/* CLKGEN :: PLL_CPU_RDB_MACRO_CTRL :: PLL_CPU_OPTIONS_DISABLE_RDB_MACRO [03:03] */
-#define BCHP_CLKGEN_PLL_CPU_RDB_MACRO_CTRL_PLL_CPU_OPTIONS_DISABLE_RDB_MACRO_MASK 0x00000008
-#define BCHP_CLKGEN_PLL_CPU_RDB_MACRO_CTRL_PLL_CPU_OPTIONS_DISABLE_RDB_MACRO_SHIFT 3
-#define BCHP_CLKGEN_PLL_CPU_RDB_MACRO_CTRL_PLL_CPU_OPTIONS_DISABLE_RDB_MACRO_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_CPU_RDB_MACRO_CTRL :: OPTIONS [02:00] */
-#define BCHP_CLKGEN_PLL_CPU_RDB_MACRO_CTRL_OPTIONS_MASK 0x00000007
-#define BCHP_CLKGEN_PLL_CPU_RDB_MACRO_CTRL_OPTIONS_SHIFT 0
-#define BCHP_CLKGEN_PLL_CPU_RDB_MACRO_CTRL_OPTIONS_DEFAULT 0x00000000
-
-/***************************************************************************
- *PLL_HVD_PLL_RESET_STATUS - PLL_HVD Reset Status
- ***************************************************************************/
-/* CLKGEN :: PLL_HVD_PLL_RESET_STATUS :: reserved0 [31:02] */
-#define BCHP_CLKGEN_PLL_HVD_PLL_RESET_STATUS_reserved0_MASK 0xfffffffc
-#define BCHP_CLKGEN_PLL_HVD_PLL_RESET_STATUS_reserved0_SHIFT 2
-
-/* CLKGEN :: PLL_HVD_PLL_RESET_STATUS :: PLL_DRESET_STATUS [01:01] */
-#define BCHP_CLKGEN_PLL_HVD_PLL_RESET_STATUS_PLL_DRESET_STATUS_MASK 0x00000002
-#define BCHP_CLKGEN_PLL_HVD_PLL_RESET_STATUS_PLL_DRESET_STATUS_SHIFT 1
-
-/* CLKGEN :: PLL_HVD_PLL_RESET_STATUS :: PLL_ARESET_STATUS [00:00] */
-#define BCHP_CLKGEN_PLL_HVD_PLL_RESET_STATUS_PLL_ARESET_STATUS_MASK 0x00000001
-#define BCHP_CLKGEN_PLL_HVD_PLL_RESET_STATUS_PLL_ARESET_STATUS_SHIFT 0
-
-/***************************************************************************
- *PLL_HVD_RDB_MACRO_CTRL - PLL RDB Macro Disable
- ***************************************************************************/
-/* CLKGEN :: PLL_HVD_RDB_MACRO_CTRL :: reserved0 [31:04] */
-#define BCHP_CLKGEN_PLL_HVD_RDB_MACRO_CTRL_reserved0_MASK 0xfffffff0
-#define BCHP_CLKGEN_PLL_HVD_RDB_MACRO_CTRL_reserved0_SHIFT 4
-
-/* CLKGEN :: PLL_HVD_RDB_MACRO_CTRL :: PLL_HVD_OPTIONS_DISABLE_RDB_MACRO [03:03] */
-#define BCHP_CLKGEN_PLL_HVD_RDB_MACRO_CTRL_PLL_HVD_OPTIONS_DISABLE_RDB_MACRO_MASK 0x00000008
-#define BCHP_CLKGEN_PLL_HVD_RDB_MACRO_CTRL_PLL_HVD_OPTIONS_DISABLE_RDB_MACRO_SHIFT 3
-#define BCHP_CLKGEN_PLL_HVD_RDB_MACRO_CTRL_PLL_HVD_OPTIONS_DISABLE_RDB_MACRO_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_HVD_RDB_MACRO_CTRL :: OPTIONS [02:00] */
-#define BCHP_CLKGEN_PLL_HVD_RDB_MACRO_CTRL_OPTIONS_MASK 0x00000007
-#define BCHP_CLKGEN_PLL_HVD_RDB_MACRO_CTRL_OPTIONS_SHIFT 0
-#define BCHP_CLKGEN_PLL_HVD_RDB_MACRO_CTRL_OPTIONS_DEFAULT 0x00000000
-
-/***************************************************************************
- *PLL_LC_PLL_RESET_STATUS - PLL_LC Reset Status
- ***************************************************************************/
-/* CLKGEN :: PLL_LC_PLL_RESET_STATUS :: reserved0 [31:02] */
-#define BCHP_CLKGEN_PLL_LC_PLL_RESET_STATUS_reserved0_MASK 0xfffffffc
-#define BCHP_CLKGEN_PLL_LC_PLL_RESET_STATUS_reserved0_SHIFT 2
-
-/* CLKGEN :: PLL_LC_PLL_RESET_STATUS :: PLL_DRESET_STATUS [01:01] */
-#define BCHP_CLKGEN_PLL_LC_PLL_RESET_STATUS_PLL_DRESET_STATUS_MASK 0x00000002
-#define BCHP_CLKGEN_PLL_LC_PLL_RESET_STATUS_PLL_DRESET_STATUS_SHIFT 1
-
-/* CLKGEN :: PLL_LC_PLL_RESET_STATUS :: PLL_ARESET_STATUS [00:00] */
-#define BCHP_CLKGEN_PLL_LC_PLL_RESET_STATUS_PLL_ARESET_STATUS_MASK 0x00000001
-#define BCHP_CLKGEN_PLL_LC_PLL_RESET_STATUS_PLL_ARESET_STATUS_SHIFT 0
-
-/***************************************************************************
- *PLL_MOCA_PLL_RESET_STATUS - PLL_MOCA Reset Status
- ***************************************************************************/
-/* CLKGEN :: PLL_MOCA_PLL_RESET_STATUS :: reserved0 [31:02] */
-#define BCHP_CLKGEN_PLL_MOCA_PLL_RESET_STATUS_reserved0_MASK 0xfffffffc
-#define BCHP_CLKGEN_PLL_MOCA_PLL_RESET_STATUS_reserved0_SHIFT 2
-
-/* CLKGEN :: PLL_MOCA_PLL_RESET_STATUS :: PLL_DRESET_STATUS [01:01] */
-#define BCHP_CLKGEN_PLL_MOCA_PLL_RESET_STATUS_PLL_DRESET_STATUS_MASK 0x00000002
-#define BCHP_CLKGEN_PLL_MOCA_PLL_RESET_STATUS_PLL_DRESET_STATUS_SHIFT 1
-
-/* CLKGEN :: PLL_MOCA_PLL_RESET_STATUS :: PLL_ARESET_STATUS [00:00] */
-#define BCHP_CLKGEN_PLL_MOCA_PLL_RESET_STATUS_PLL_ARESET_STATUS_MASK 0x00000001
-#define BCHP_CLKGEN_PLL_MOCA_PLL_RESET_STATUS_PLL_ARESET_STATUS_SHIFT 0
-
-/***************************************************************************
- *PLL_MOCA_RDB_MACRO_CTRL - PLL RDB Macro Disable
- ***************************************************************************/
-/* CLKGEN :: PLL_MOCA_RDB_MACRO_CTRL :: reserved0 [31:03] */
-#define BCHP_CLKGEN_PLL_MOCA_RDB_MACRO_CTRL_reserved0_MASK 0xfffffff8
-#define BCHP_CLKGEN_PLL_MOCA_RDB_MACRO_CTRL_reserved0_SHIFT 3
-
-/* CLKGEN :: PLL_MOCA_RDB_MACRO_CTRL :: PLL_MOCA_OPTIONS_DISABLE_RDB_MACRO [02:02] */
-#define BCHP_CLKGEN_PLL_MOCA_RDB_MACRO_CTRL_PLL_MOCA_OPTIONS_DISABLE_RDB_MACRO_MASK 0x00000004
-#define BCHP_CLKGEN_PLL_MOCA_RDB_MACRO_CTRL_PLL_MOCA_OPTIONS_DISABLE_RDB_MACRO_SHIFT 2
-#define BCHP_CLKGEN_PLL_MOCA_RDB_MACRO_CTRL_PLL_MOCA_OPTIONS_DISABLE_RDB_MACRO_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_MOCA_RDB_MACRO_CTRL :: OPTIONS [01:00] */
-#define BCHP_CLKGEN_PLL_MOCA_RDB_MACRO_CTRL_OPTIONS_MASK 0x00000003
-#define BCHP_CLKGEN_PLL_MOCA_RDB_MACRO_CTRL_OPTIONS_SHIFT 0
-#define BCHP_CLKGEN_PLL_MOCA_RDB_MACRO_CTRL_OPTIONS_DEFAULT 0x00000000
-
-/***************************************************************************
- *PLL_NETWORK_PLL_RESET_STATUS - PLL_NETWORK Reset Status
- ***************************************************************************/
-/* CLKGEN :: PLL_NETWORK_PLL_RESET_STATUS :: reserved0 [31:02] */
-#define BCHP_CLKGEN_PLL_NETWORK_PLL_RESET_STATUS_reserved0_MASK 0xfffffffc
-#define BCHP_CLKGEN_PLL_NETWORK_PLL_RESET_STATUS_reserved0_SHIFT 2
-
-/* CLKGEN :: PLL_NETWORK_PLL_RESET_STATUS :: PLL_DRESET_STATUS [01:01] */
-#define BCHP_CLKGEN_PLL_NETWORK_PLL_RESET_STATUS_PLL_DRESET_STATUS_MASK 0x00000002
-#define BCHP_CLKGEN_PLL_NETWORK_PLL_RESET_STATUS_PLL_DRESET_STATUS_SHIFT 1
-
-/* CLKGEN :: PLL_NETWORK_PLL_RESET_STATUS :: PLL_ARESET_STATUS [00:00] */
-#define BCHP_CLKGEN_PLL_NETWORK_PLL_RESET_STATUS_PLL_ARESET_STATUS_MASK 0x00000001
-#define BCHP_CLKGEN_PLL_NETWORK_PLL_RESET_STATUS_PLL_ARESET_STATUS_SHIFT 0
-
-/***************************************************************************
- *PLL_NETWORK_RDB_MACRO_CTRL - PLL RDB Macro Disable
- ***************************************************************************/
-/* CLKGEN :: PLL_NETWORK_RDB_MACRO_CTRL :: reserved0 [31:03] */
-#define BCHP_CLKGEN_PLL_NETWORK_RDB_MACRO_CTRL_reserved0_MASK 0xfffffff8
-#define BCHP_CLKGEN_PLL_NETWORK_RDB_MACRO_CTRL_reserved0_SHIFT 3
-
-/* CLKGEN :: PLL_NETWORK_RDB_MACRO_CTRL :: PLL_NETWORK_OPTIONS_DISABLE_RDB_MACRO [02:02] */
-#define BCHP_CLKGEN_PLL_NETWORK_RDB_MACRO_CTRL_PLL_NETWORK_OPTIONS_DISABLE_RDB_MACRO_MASK 0x00000004
-#define BCHP_CLKGEN_PLL_NETWORK_RDB_MACRO_CTRL_PLL_NETWORK_OPTIONS_DISABLE_RDB_MACRO_SHIFT 2
-#define BCHP_CLKGEN_PLL_NETWORK_RDB_MACRO_CTRL_PLL_NETWORK_OPTIONS_DISABLE_RDB_MACRO_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_NETWORK_RDB_MACRO_CTRL :: OPTIONS [01:00] */
-#define BCHP_CLKGEN_PLL_NETWORK_RDB_MACRO_CTRL_OPTIONS_MASK 0x00000003
-#define BCHP_CLKGEN_PLL_NETWORK_RDB_MACRO_CTRL_OPTIONS_SHIFT 0
-#define BCHP_CLKGEN_PLL_NETWORK_RDB_MACRO_CTRL_OPTIONS_DEFAULT 0x00000000
-
-/***************************************************************************
- *PLL_RAAGA_PLL_RESET_STATUS - PLL_RAAGA Reset Status
- ***************************************************************************/
-/* CLKGEN :: PLL_RAAGA_PLL_RESET_STATUS :: reserved0 [31:02] */
-#define BCHP_CLKGEN_PLL_RAAGA_PLL_RESET_STATUS_reserved0_MASK 0xfffffffc
-#define BCHP_CLKGEN_PLL_RAAGA_PLL_RESET_STATUS_reserved0_SHIFT 2
-
-/* CLKGEN :: PLL_RAAGA_PLL_RESET_STATUS :: PLL_DRESET_STATUS [01:01] */
-#define BCHP_CLKGEN_PLL_RAAGA_PLL_RESET_STATUS_PLL_DRESET_STATUS_MASK 0x00000002
-#define BCHP_CLKGEN_PLL_RAAGA_PLL_RESET_STATUS_PLL_DRESET_STATUS_SHIFT 1
-
-/* CLKGEN :: PLL_RAAGA_PLL_RESET_STATUS :: PLL_ARESET_STATUS [00:00] */
-#define BCHP_CLKGEN_PLL_RAAGA_PLL_RESET_STATUS_PLL_ARESET_STATUS_MASK 0x00000001
-#define BCHP_CLKGEN_PLL_RAAGA_PLL_RESET_STATUS_PLL_ARESET_STATUS_SHIFT 0
-
-/***************************************************************************
- *PLL_RAAGA_RDB_MACRO_CTRL - PLL RDB Macro Disable
- ***************************************************************************/
-/* CLKGEN :: PLL_RAAGA_RDB_MACRO_CTRL :: reserved0 [31:04] */
-#define BCHP_CLKGEN_PLL_RAAGA_RDB_MACRO_CTRL_reserved0_MASK 0xfffffff0
-#define BCHP_CLKGEN_PLL_RAAGA_RDB_MACRO_CTRL_reserved0_SHIFT 4
-
-/* CLKGEN :: PLL_RAAGA_RDB_MACRO_CTRL :: PLL_RAAGA_OPTIONS_DISABLE_RDB_MACRO [03:03] */
-#define BCHP_CLKGEN_PLL_RAAGA_RDB_MACRO_CTRL_PLL_RAAGA_OPTIONS_DISABLE_RDB_MACRO_MASK 0x00000008
-#define BCHP_CLKGEN_PLL_RAAGA_RDB_MACRO_CTRL_PLL_RAAGA_OPTIONS_DISABLE_RDB_MACRO_SHIFT 3
-#define BCHP_CLKGEN_PLL_RAAGA_RDB_MACRO_CTRL_PLL_RAAGA_OPTIONS_DISABLE_RDB_MACRO_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_RAAGA_RDB_MACRO_CTRL :: OPTIONS [02:00] */
-#define BCHP_CLKGEN_PLL_RAAGA_RDB_MACRO_CTRL_OPTIONS_MASK 0x00000007
-#define BCHP_CLKGEN_PLL_RAAGA_RDB_MACRO_CTRL_OPTIONS_SHIFT 0
-#define BCHP_CLKGEN_PLL_RAAGA_RDB_MACRO_CTRL_OPTIONS_DEFAULT 0x00000000
-
-/***************************************************************************
- *PLL_SC0_PLL_RESET_STATUS - PLL_SC0 Reset Status
- ***************************************************************************/
-/* CLKGEN :: PLL_SC0_PLL_RESET_STATUS :: reserved0 [31:02] */
-#define BCHP_CLKGEN_PLL_SC0_PLL_RESET_STATUS_reserved0_MASK 0xfffffffc
-#define BCHP_CLKGEN_PLL_SC0_PLL_RESET_STATUS_reserved0_SHIFT 2
-
-/* CLKGEN :: PLL_SC0_PLL_RESET_STATUS :: PLL_DRESET_STATUS [01:01] */
-#define BCHP_CLKGEN_PLL_SC0_PLL_RESET_STATUS_PLL_DRESET_STATUS_MASK 0x00000002
-#define BCHP_CLKGEN_PLL_SC0_PLL_RESET_STATUS_PLL_DRESET_STATUS_SHIFT 1
-
-/* CLKGEN :: PLL_SC0_PLL_RESET_STATUS :: PLL_ARESET_STATUS [00:00] */
-#define BCHP_CLKGEN_PLL_SC0_PLL_RESET_STATUS_PLL_ARESET_STATUS_MASK 0x00000001
-#define BCHP_CLKGEN_PLL_SC0_PLL_RESET_STATUS_PLL_ARESET_STATUS_SHIFT 0
-
-/***************************************************************************
- *PLL_SC0_RDB_MACRO_CTRL - PLL RDB Macro Disable
- ***************************************************************************/
-/* CLKGEN :: PLL_SC0_RDB_MACRO_CTRL :: reserved0 [31:05] */
-#define BCHP_CLKGEN_PLL_SC0_RDB_MACRO_CTRL_reserved0_MASK 0xffffffe0
-#define BCHP_CLKGEN_PLL_SC0_RDB_MACRO_CTRL_reserved0_SHIFT 5
-
-/* CLKGEN :: PLL_SC0_RDB_MACRO_CTRL :: PLL_SC0_OPTIONS_DISABLE_RDB_MACRO [04:04] */
-#define BCHP_CLKGEN_PLL_SC0_RDB_MACRO_CTRL_PLL_SC0_OPTIONS_DISABLE_RDB_MACRO_MASK 0x00000010
-#define BCHP_CLKGEN_PLL_SC0_RDB_MACRO_CTRL_PLL_SC0_OPTIONS_DISABLE_RDB_MACRO_SHIFT 4
-#define BCHP_CLKGEN_PLL_SC0_RDB_MACRO_CTRL_PLL_SC0_OPTIONS_DISABLE_RDB_MACRO_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_SC0_RDB_MACRO_CTRL :: OPTIONS [03:00] */
-#define BCHP_CLKGEN_PLL_SC0_RDB_MACRO_CTRL_OPTIONS_MASK 0x0000000f
-#define BCHP_CLKGEN_PLL_SC0_RDB_MACRO_CTRL_OPTIONS_SHIFT 0
-#define BCHP_CLKGEN_PLL_SC0_RDB_MACRO_CTRL_OPTIONS_DEFAULT 0x00000000
-
-/***************************************************************************
- *PLL_SC1_PLL_RESET_STATUS - PLL_SC1 Reset Status
- ***************************************************************************/
-/* CLKGEN :: PLL_SC1_PLL_RESET_STATUS :: reserved0 [31:02] */
-#define BCHP_CLKGEN_PLL_SC1_PLL_RESET_STATUS_reserved0_MASK 0xfffffffc
-#define BCHP_CLKGEN_PLL_SC1_PLL_RESET_STATUS_reserved0_SHIFT 2
-
-/* CLKGEN :: PLL_SC1_PLL_RESET_STATUS :: PLL_DRESET_STATUS [01:01] */
-#define BCHP_CLKGEN_PLL_SC1_PLL_RESET_STATUS_PLL_DRESET_STATUS_MASK 0x00000002
-#define BCHP_CLKGEN_PLL_SC1_PLL_RESET_STATUS_PLL_DRESET_STATUS_SHIFT 1
-
-/* CLKGEN :: PLL_SC1_PLL_RESET_STATUS :: PLL_ARESET_STATUS [00:00] */
-#define BCHP_CLKGEN_PLL_SC1_PLL_RESET_STATUS_PLL_ARESET_STATUS_MASK 0x00000001
-#define BCHP_CLKGEN_PLL_SC1_PLL_RESET_STATUS_PLL_ARESET_STATUS_SHIFT 0
-
-/***************************************************************************
- *PLL_SC1_RDB_MACRO_CTRL - PLL RDB Macro Disable
- ***************************************************************************/
-/* CLKGEN :: PLL_SC1_RDB_MACRO_CTRL :: reserved0 [31:05] */
-#define BCHP_CLKGEN_PLL_SC1_RDB_MACRO_CTRL_reserved0_MASK 0xffffffe0
-#define BCHP_CLKGEN_PLL_SC1_RDB_MACRO_CTRL_reserved0_SHIFT 5
-
-/* CLKGEN :: PLL_SC1_RDB_MACRO_CTRL :: PLL_SC1_OPTIONS_DISABLE_RDB_MACRO [04:04] */
-#define BCHP_CLKGEN_PLL_SC1_RDB_MACRO_CTRL_PLL_SC1_OPTIONS_DISABLE_RDB_MACRO_MASK 0x00000010
-#define BCHP_CLKGEN_PLL_SC1_RDB_MACRO_CTRL_PLL_SC1_OPTIONS_DISABLE_RDB_MACRO_SHIFT 4
-#define BCHP_CLKGEN_PLL_SC1_RDB_MACRO_CTRL_PLL_SC1_OPTIONS_DISABLE_RDB_MACRO_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_SC1_RDB_MACRO_CTRL :: OPTIONS [03:00] */
-#define BCHP_CLKGEN_PLL_SC1_RDB_MACRO_CTRL_OPTIONS_MASK 0x0000000f
-#define BCHP_CLKGEN_PLL_SC1_RDB_MACRO_CTRL_OPTIONS_SHIFT 0
-#define BCHP_CLKGEN_PLL_SC1_RDB_MACRO_CTRL_OPTIONS_DEFAULT 0x00000000
-
-/***************************************************************************
- *PLL_SDS_PLL_RESET_STATUS - PLL_SDS Reset Status
- ***************************************************************************/
-/* CLKGEN :: PLL_SDS_PLL_RESET_STATUS :: reserved0 [31:02] */
-#define BCHP_CLKGEN_PLL_SDS_PLL_RESET_STATUS_reserved0_MASK 0xfffffffc
-#define BCHP_CLKGEN_PLL_SDS_PLL_RESET_STATUS_reserved0_SHIFT 2
-
-/* CLKGEN :: PLL_SDS_PLL_RESET_STATUS :: PLL_DRESET_STATUS [01:01] */
-#define BCHP_CLKGEN_PLL_SDS_PLL_RESET_STATUS_PLL_DRESET_STATUS_MASK 0x00000002
-#define BCHP_CLKGEN_PLL_SDS_PLL_RESET_STATUS_PLL_DRESET_STATUS_SHIFT 1
-
-/* CLKGEN :: PLL_SDS_PLL_RESET_STATUS :: PLL_ARESET_STATUS [00:00] */
-#define BCHP_CLKGEN_PLL_SDS_PLL_RESET_STATUS_PLL_ARESET_STATUS_MASK 0x00000001
-#define BCHP_CLKGEN_PLL_SDS_PLL_RESET_STATUS_PLL_ARESET_STATUS_SHIFT 0
-
-/***************************************************************************
- *PLL_V3D_PLL_RESET_STATUS - PLL_V3D Reset Status
- ***************************************************************************/
-/* CLKGEN :: PLL_V3D_PLL_RESET_STATUS :: reserved0 [31:02] */
-#define BCHP_CLKGEN_PLL_V3D_PLL_RESET_STATUS_reserved0_MASK 0xfffffffc
-#define BCHP_CLKGEN_PLL_V3D_PLL_RESET_STATUS_reserved0_SHIFT 2
-
-/* CLKGEN :: PLL_V3D_PLL_RESET_STATUS :: PLL_DRESET_STATUS [01:01] */
-#define BCHP_CLKGEN_PLL_V3D_PLL_RESET_STATUS_PLL_DRESET_STATUS_MASK 0x00000002
-#define BCHP_CLKGEN_PLL_V3D_PLL_RESET_STATUS_PLL_DRESET_STATUS_SHIFT 1
-
-/* CLKGEN :: PLL_V3D_PLL_RESET_STATUS :: PLL_ARESET_STATUS [00:00] */
-#define BCHP_CLKGEN_PLL_V3D_PLL_RESET_STATUS_PLL_ARESET_STATUS_MASK 0x00000001
-#define BCHP_CLKGEN_PLL_V3D_PLL_RESET_STATUS_PLL_ARESET_STATUS_SHIFT 0
-
-/***************************************************************************
- *PLL_V3D_RDB_MACRO_CTRL - PLL RDB Macro Disable
- ***************************************************************************/
-/* CLKGEN :: PLL_V3D_RDB_MACRO_CTRL :: reserved0 [31:03] */
-#define BCHP_CLKGEN_PLL_V3D_RDB_MACRO_CTRL_reserved0_MASK 0xfffffff8
-#define BCHP_CLKGEN_PLL_V3D_RDB_MACRO_CTRL_reserved0_SHIFT 3
-
-/* CLKGEN :: PLL_V3D_RDB_MACRO_CTRL :: PLL_V3D_OPTIONS_DISABLE_RDB_MACRO [02:02] */
-#define BCHP_CLKGEN_PLL_V3D_RDB_MACRO_CTRL_PLL_V3D_OPTIONS_DISABLE_RDB_MACRO_MASK 0x00000004
-#define BCHP_CLKGEN_PLL_V3D_RDB_MACRO_CTRL_PLL_V3D_OPTIONS_DISABLE_RDB_MACRO_SHIFT 2
-#define BCHP_CLKGEN_PLL_V3D_RDB_MACRO_CTRL_PLL_V3D_OPTIONS_DISABLE_RDB_MACRO_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_V3D_RDB_MACRO_CTRL :: OPTIONS [01:00] */
-#define BCHP_CLKGEN_PLL_V3D_RDB_MACRO_CTRL_OPTIONS_MASK 0x00000003
-#define BCHP_CLKGEN_PLL_V3D_RDB_MACRO_CTRL_OPTIONS_SHIFT 0
-#define BCHP_CLKGEN_PLL_V3D_RDB_MACRO_CTRL_OPTIONS_DEFAULT 0x00000000
-
-/***************************************************************************
- *PLL_VCXO0_PLL_RESET_STATUS - PLL_VCXO0 Reset Status
- ***************************************************************************/
-/* CLKGEN :: PLL_VCXO0_PLL_RESET_STATUS :: reserved0 [31:02] */
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_RESET_STATUS_reserved0_MASK 0xfffffffc
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_RESET_STATUS_reserved0_SHIFT 2
-
-/* CLKGEN :: PLL_VCXO0_PLL_RESET_STATUS :: PLL_DRESET_STATUS [01:01] */
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_RESET_STATUS_PLL_DRESET_STATUS_MASK 0x00000002
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_RESET_STATUS_PLL_DRESET_STATUS_SHIFT 1
-
-/* CLKGEN :: PLL_VCXO0_PLL_RESET_STATUS :: PLL_ARESET_STATUS [00:00] */
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_RESET_STATUS_PLL_ARESET_STATUS_MASK 0x00000001
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_RESET_STATUS_PLL_ARESET_STATUS_SHIFT 0
-
-/***************************************************************************
- *PLL_VCXO1_PLL_RESET_STATUS - PLL_VCXO1 Reset Status
- ***************************************************************************/
-/* CLKGEN :: PLL_VCXO1_PLL_RESET_STATUS :: reserved0 [31:02] */
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_RESET_STATUS_reserved0_MASK 0xfffffffc
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_RESET_STATUS_reserved0_SHIFT 2
-
-/* CLKGEN :: PLL_VCXO1_PLL_RESET_STATUS :: PLL_DRESET_STATUS [01:01] */
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_RESET_STATUS_PLL_DRESET_STATUS_MASK 0x00000002
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_RESET_STATUS_PLL_DRESET_STATUS_SHIFT 1
-
-/* CLKGEN :: PLL_VCXO1_PLL_RESET_STATUS :: PLL_ARESET_STATUS [00:00] */
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_RESET_STATUS_PLL_ARESET_STATUS_MASK 0x00000001
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_RESET_STATUS_PLL_ARESET_STATUS_SHIFT 0
-
-/***************************************************************************
- *PLL_XPT_RDB_MACRO_CTRL - PLL RDB Macro Disable
- ***************************************************************************/
-/* CLKGEN :: PLL_XPT_RDB_MACRO_CTRL :: reserved0 [31:02] */
-#define BCHP_CLKGEN_PLL_XPT_RDB_MACRO_CTRL_reserved0_MASK 0xfffffffc
-#define BCHP_CLKGEN_PLL_XPT_RDB_MACRO_CTRL_reserved0_SHIFT 2
-
-/* CLKGEN :: PLL_XPT_RDB_MACRO_CTRL :: PLL_XPT_OPTIONS_DISABLE_RDB_MACRO [01:01] */
-#define BCHP_CLKGEN_PLL_XPT_RDB_MACRO_CTRL_PLL_XPT_OPTIONS_DISABLE_RDB_MACRO_MASK 0x00000002
-#define BCHP_CLKGEN_PLL_XPT_RDB_MACRO_CTRL_PLL_XPT_OPTIONS_DISABLE_RDB_MACRO_SHIFT 1
-#define BCHP_CLKGEN_PLL_XPT_RDB_MACRO_CTRL_PLL_XPT_OPTIONS_DISABLE_RDB_MACRO_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_XPT_RDB_MACRO_CTRL :: OPTIONS [00:00] */
-#define BCHP_CLKGEN_PLL_XPT_RDB_MACRO_CTRL_OPTIONS_MASK 0x00000001
-#define BCHP_CLKGEN_PLL_XPT_RDB_MACRO_CTRL_OPTIONS_SHIFT 0
-#define BCHP_CLKGEN_PLL_XPT_RDB_MACRO_CTRL_OPTIONS_DEFAULT 0x00000000
-
-/***************************************************************************
- *PM_CLOCK_108_ALIVE_SEL - Select clocks that can stay alive during power management standby mode.
- ***************************************************************************/
-/* CLKGEN :: PM_CLOCK_108_ALIVE_SEL :: reserved0 [31:14] */
-#define BCHP_CLKGEN_PM_CLOCK_108_ALIVE_SEL_reserved0_MASK 0xffffc000
-#define BCHP_CLKGEN_PM_CLOCK_108_ALIVE_SEL_reserved0_SHIFT 14
-
-/* CLKGEN :: PM_CLOCK_108_ALIVE_SEL :: CLOCK_108_CG_SDS3 [13:13] */
-#define BCHP_CLKGEN_PM_CLOCK_108_ALIVE_SEL_CLOCK_108_CG_SDS3_MASK 0x00002000
-#define BCHP_CLKGEN_PM_CLOCK_108_ALIVE_SEL_CLOCK_108_CG_SDS3_SHIFT 13
-#define BCHP_CLKGEN_PM_CLOCK_108_ALIVE_SEL_CLOCK_108_CG_SDS3_DEFAULT 0x00000000
-
-/* CLKGEN :: PM_CLOCK_108_ALIVE_SEL :: CLOCK_108_CG_SDS2 [12:12] */
-#define BCHP_CLKGEN_PM_CLOCK_108_ALIVE_SEL_CLOCK_108_CG_SDS2_MASK 0x00001000
-#define BCHP_CLKGEN_PM_CLOCK_108_ALIVE_SEL_CLOCK_108_CG_SDS2_SHIFT 12
-#define BCHP_CLKGEN_PM_CLOCK_108_ALIVE_SEL_CLOCK_108_CG_SDS2_DEFAULT 0x00000000
-
-/* CLKGEN :: PM_CLOCK_108_ALIVE_SEL :: CLOCK_108_CG_SDS1 [11:11] */
-#define BCHP_CLKGEN_PM_CLOCK_108_ALIVE_SEL_CLOCK_108_CG_SDS1_MASK 0x00000800
-#define BCHP_CLKGEN_PM_CLOCK_108_ALIVE_SEL_CLOCK_108_CG_SDS1_SHIFT 11
-#define BCHP_CLKGEN_PM_CLOCK_108_ALIVE_SEL_CLOCK_108_CG_SDS1_DEFAULT 0x00000000
-
-/* CLKGEN :: PM_CLOCK_108_ALIVE_SEL :: CLOCK_108_CG_SDS0 [10:10] */
-#define BCHP_CLKGEN_PM_CLOCK_108_ALIVE_SEL_CLOCK_108_CG_SDS0_MASK 0x00000400
-#define BCHP_CLKGEN_PM_CLOCK_108_ALIVE_SEL_CLOCK_108_CG_SDS0_SHIFT 10
-#define BCHP_CLKGEN_PM_CLOCK_108_ALIVE_SEL_CLOCK_108_CG_SDS0_DEFAULT 0x00000000
-
-/* CLKGEN :: PM_CLOCK_108_ALIVE_SEL :: CLOCK_108_CG_MDAC [09:09] */
-#define BCHP_CLKGEN_PM_CLOCK_108_ALIVE_SEL_CLOCK_108_CG_MDAC_MASK 0x00000200
-#define BCHP_CLKGEN_PM_CLOCK_108_ALIVE_SEL_CLOCK_108_CG_MDAC_SHIFT 9
-#define BCHP_CLKGEN_PM_CLOCK_108_ALIVE_SEL_CLOCK_108_CG_MDAC_DEFAULT 0x00000000
-
-/* CLKGEN :: PM_CLOCK_108_ALIVE_SEL :: CLOCK_108_CG_LEAP [08:08] */
-#define BCHP_CLKGEN_PM_CLOCK_108_ALIVE_SEL_CLOCK_108_CG_LEAP_MASK 0x00000100
-#define BCHP_CLKGEN_PM_CLOCK_108_ALIVE_SEL_CLOCK_108_CG_LEAP_SHIFT 8
-#define BCHP_CLKGEN_PM_CLOCK_108_ALIVE_SEL_CLOCK_108_CG_LEAP_DEFAULT 0x00000000
-
-/* CLKGEN :: PM_CLOCK_108_ALIVE_SEL :: CLOCK_108_CG_FSK [07:07] */
-#define BCHP_CLKGEN_PM_CLOCK_108_ALIVE_SEL_CLOCK_108_CG_FSK_MASK 0x00000080
-#define BCHP_CLKGEN_PM_CLOCK_108_ALIVE_SEL_CLOCK_108_CG_FSK_SHIFT 7
-#define BCHP_CLKGEN_PM_CLOCK_108_ALIVE_SEL_CLOCK_108_CG_FSK_DEFAULT 0x00000000
-
-/* CLKGEN :: PM_CLOCK_108_ALIVE_SEL :: CLOCK_108_CG_CHAN [06:06] */
-#define BCHP_CLKGEN_PM_CLOCK_108_ALIVE_SEL_CLOCK_108_CG_CHAN_MASK 0x00000040
-#define BCHP_CLKGEN_PM_CLOCK_108_ALIVE_SEL_CLOCK_108_CG_CHAN_SHIFT 6
-#define BCHP_CLKGEN_PM_CLOCK_108_ALIVE_SEL_CLOCK_108_CG_CHAN_DEFAULT 0x00000000
-
-/* CLKGEN :: PM_CLOCK_108_ALIVE_SEL :: CLOCK_108_CG_AIF1 [05:05] */
-#define BCHP_CLKGEN_PM_CLOCK_108_ALIVE_SEL_CLOCK_108_CG_AIF1_MASK 0x00000020
-#define BCHP_CLKGEN_PM_CLOCK_108_ALIVE_SEL_CLOCK_108_CG_AIF1_SHIFT 5
-#define BCHP_CLKGEN_PM_CLOCK_108_ALIVE_SEL_CLOCK_108_CG_AIF1_DEFAULT 0x00000000
-
-/* CLKGEN :: PM_CLOCK_108_ALIVE_SEL :: CLOCK_108_CG_AIF0 [04:04] */
-#define BCHP_CLKGEN_PM_CLOCK_108_ALIVE_SEL_CLOCK_108_CG_AIF0_MASK 0x00000010
-#define BCHP_CLKGEN_PM_CLOCK_108_ALIVE_SEL_CLOCK_108_CG_AIF0_SHIFT 4
-#define BCHP_CLKGEN_PM_CLOCK_108_ALIVE_SEL_CLOCK_108_CG_AIF0_DEFAULT 0x00000000
-
-/* CLKGEN :: PM_CLOCK_108_ALIVE_SEL :: CLOCK_108_CG_AFEC3 [03:03] */
-#define BCHP_CLKGEN_PM_CLOCK_108_ALIVE_SEL_CLOCK_108_CG_AFEC3_MASK 0x00000008
-#define BCHP_CLKGEN_PM_CLOCK_108_ALIVE_SEL_CLOCK_108_CG_AFEC3_SHIFT 3
-#define BCHP_CLKGEN_PM_CLOCK_108_ALIVE_SEL_CLOCK_108_CG_AFEC3_DEFAULT 0x00000000
-
-/* CLKGEN :: PM_CLOCK_108_ALIVE_SEL :: CLOCK_108_CG_AFEC2 [02:02] */
-#define BCHP_CLKGEN_PM_CLOCK_108_ALIVE_SEL_CLOCK_108_CG_AFEC2_MASK 0x00000004
-#define BCHP_CLKGEN_PM_CLOCK_108_ALIVE_SEL_CLOCK_108_CG_AFEC2_SHIFT 2
-#define BCHP_CLKGEN_PM_CLOCK_108_ALIVE_SEL_CLOCK_108_CG_AFEC2_DEFAULT 0x00000000
-
-/* CLKGEN :: PM_CLOCK_108_ALIVE_SEL :: CLOCK_108_CG_AFEC1 [01:01] */
-#define BCHP_CLKGEN_PM_CLOCK_108_ALIVE_SEL_CLOCK_108_CG_AFEC1_MASK 0x00000002
-#define BCHP_CLKGEN_PM_CLOCK_108_ALIVE_SEL_CLOCK_108_CG_AFEC1_SHIFT 1
-#define BCHP_CLKGEN_PM_CLOCK_108_ALIVE_SEL_CLOCK_108_CG_AFEC1_DEFAULT 0x00000000
-
-/* CLKGEN :: PM_CLOCK_108_ALIVE_SEL :: CLOCK_108_CG_AFEC0 [00:00] */
-#define BCHP_CLKGEN_PM_CLOCK_108_ALIVE_SEL_CLOCK_108_CG_AFEC0_MASK 0x00000001
-#define BCHP_CLKGEN_PM_CLOCK_108_ALIVE_SEL_CLOCK_108_CG_AFEC0_SHIFT 0
-#define BCHP_CLKGEN_PM_CLOCK_108_ALIVE_SEL_CLOCK_108_CG_AFEC0_DEFAULT 0x00000000
-
-/***************************************************************************
- *PM_CLOCK_Async_ALIVE_SEL - Select clocks that can stay alive during power management standby mode.
- ***************************************************************************/
-/* CLKGEN :: PM_CLOCK_Async_ALIVE_SEL :: reserved0 [31:01] */
-#define BCHP_CLKGEN_PM_CLOCK_Async_ALIVE_SEL_reserved0_MASK 0xfffffffe
-#define BCHP_CLKGEN_PM_CLOCK_Async_ALIVE_SEL_reserved0_SHIFT 1
-
-/* CLKGEN :: PM_CLOCK_Async_ALIVE_SEL :: CLOCK_Async_CG_XPT [00:00] */
-#define BCHP_CLKGEN_PM_CLOCK_Async_ALIVE_SEL_CLOCK_Async_CG_XPT_MASK 0x00000001
-#define BCHP_CLKGEN_PM_CLOCK_Async_ALIVE_SEL_CLOCK_Async_CG_XPT_SHIFT 0
-#define BCHP_CLKGEN_PM_CLOCK_Async_ALIVE_SEL_CLOCK_Async_CG_XPT_DEFAULT 0x00000000
-
-/***************************************************************************
- *PM_CLOCK_Gisb_ALIVE_SEL - Select clocks that can stay alive during power management standby mode.
- ***************************************************************************/
-/* CLKGEN :: PM_CLOCK_Gisb_ALIVE_SEL :: reserved0 [31:01] */
-#define BCHP_CLKGEN_PM_CLOCK_Gisb_ALIVE_SEL_reserved0_MASK 0xfffffffe
-#define BCHP_CLKGEN_PM_CLOCK_Gisb_ALIVE_SEL_reserved0_SHIFT 1
-
-/* CLKGEN :: PM_CLOCK_Gisb_ALIVE_SEL :: CLOCK_Gisb_CG_LEAP [00:00] */
-#define BCHP_CLKGEN_PM_CLOCK_Gisb_ALIVE_SEL_CLOCK_Gisb_CG_LEAP_MASK 0x00000001
-#define BCHP_CLKGEN_PM_CLOCK_Gisb_ALIVE_SEL_CLOCK_Gisb_CG_LEAP_SHIFT 0
-#define BCHP_CLKGEN_PM_CLOCK_Gisb_ALIVE_SEL_CLOCK_Gisb_CG_LEAP_DEFAULT 0x00000000
-
-/***************************************************************************
- *PM_PLL_ALIVE_SEL - PLL Alive in Standby Mode
- ***************************************************************************/
-/* CLKGEN :: PM_PLL_ALIVE_SEL :: reserved0 [31:05] */
-#define BCHP_CLKGEN_PM_PLL_ALIVE_SEL_reserved0_MASK 0xffffffe0
-#define BCHP_CLKGEN_PM_PLL_ALIVE_SEL_reserved0_SHIFT 5
-
-/* CLKGEN :: PM_PLL_ALIVE_SEL :: memsys1_PLL [04:04] */
-#define BCHP_CLKGEN_PM_PLL_ALIVE_SEL_memsys1_PLL_MASK 0x00000010
-#define BCHP_CLKGEN_PM_PLL_ALIVE_SEL_memsys1_PLL_SHIFT 4
-#define BCHP_CLKGEN_PM_PLL_ALIVE_SEL_memsys1_PLL_DEFAULT 0x00000000
-
-/* CLKGEN :: PM_PLL_ALIVE_SEL :: memsys0_PLL [03:03] */
-#define BCHP_CLKGEN_PM_PLL_ALIVE_SEL_memsys0_PLL_MASK 0x00000008
-#define BCHP_CLKGEN_PM_PLL_ALIVE_SEL_memsys0_PLL_SHIFT 3
-#define BCHP_CLKGEN_PM_PLL_ALIVE_SEL_memsys0_PLL_DEFAULT 0x00000000
-
-/* CLKGEN :: PM_PLL_ALIVE_SEL :: PLL_XPT [02:02] */
-#define BCHP_CLKGEN_PM_PLL_ALIVE_SEL_PLL_XPT_MASK 0x00000004
-#define BCHP_CLKGEN_PM_PLL_ALIVE_SEL_PLL_XPT_SHIFT 2
-#define BCHP_CLKGEN_PM_PLL_ALIVE_SEL_PLL_XPT_DEFAULT 0x00000000
-
-/* CLKGEN :: PM_PLL_ALIVE_SEL :: PLL_SYS0 [01:01] */
-#define BCHP_CLKGEN_PM_PLL_ALIVE_SEL_PLL_SYS0_MASK 0x00000002
-#define BCHP_CLKGEN_PM_PLL_ALIVE_SEL_PLL_SYS0_SHIFT 1
-#define BCHP_CLKGEN_PM_PLL_ALIVE_SEL_PLL_SYS0_DEFAULT 0x00000000
-
-/* CLKGEN :: PM_PLL_ALIVE_SEL :: PLL_CPU [00:00] */
-#define BCHP_CLKGEN_PM_PLL_ALIVE_SEL_PLL_CPU_MASK 0x00000001
-#define BCHP_CLKGEN_PM_PLL_ALIVE_SEL_PLL_CPU_SHIFT 0
-#define BCHP_CLKGEN_PM_PLL_ALIVE_SEL_PLL_CPU_DEFAULT 0x00000000
-
-/***************************************************************************
- *PM_PLL_LDO_POWERUP - Power management LDO PLL
- ***************************************************************************/
-/* CLKGEN :: PM_PLL_LDO_POWERUP :: reserved0 [31:11] */
-#define BCHP_CLKGEN_PM_PLL_LDO_POWERUP_reserved0_MASK 0xfffff800
-#define BCHP_CLKGEN_PM_PLL_LDO_POWERUP_reserved0_SHIFT 11
-
-/* CLKGEN :: PM_PLL_LDO_POWERUP :: ISO_CLOCK_PLL_VCXO1 [10:10] */
-#define BCHP_CLKGEN_PM_PLL_LDO_POWERUP_ISO_CLOCK_PLL_VCXO1_MASK 0x00000400
-#define BCHP_CLKGEN_PM_PLL_LDO_POWERUP_ISO_CLOCK_PLL_VCXO1_SHIFT 10
-#define BCHP_CLKGEN_PM_PLL_LDO_POWERUP_ISO_CLOCK_PLL_VCXO1_DEFAULT 0x00000000
-
-/* CLKGEN :: PM_PLL_LDO_POWERUP :: ISO_CLOCK_PLL_VCXO0 [09:09] */
-#define BCHP_CLKGEN_PM_PLL_LDO_POWERUP_ISO_CLOCK_PLL_VCXO0_MASK 0x00000200
-#define BCHP_CLKGEN_PM_PLL_LDO_POWERUP_ISO_CLOCK_PLL_VCXO0_SHIFT 9
-#define BCHP_CLKGEN_PM_PLL_LDO_POWERUP_ISO_CLOCK_PLL_VCXO0_DEFAULT 0x00000000
-
-/* CLKGEN :: PM_PLL_LDO_POWERUP :: ISO_CLOCK_PLL_V3D [08:08] */
-#define BCHP_CLKGEN_PM_PLL_LDO_POWERUP_ISO_CLOCK_PLL_V3D_MASK 0x00000100
-#define BCHP_CLKGEN_PM_PLL_LDO_POWERUP_ISO_CLOCK_PLL_V3D_SHIFT 8
-#define BCHP_CLKGEN_PM_PLL_LDO_POWERUP_ISO_CLOCK_PLL_V3D_DEFAULT 0x00000000
-
-/* CLKGEN :: PM_PLL_LDO_POWERUP :: ISO_CLOCK_PLL_SDS [07:07] */
-#define BCHP_CLKGEN_PM_PLL_LDO_POWERUP_ISO_CLOCK_PLL_SDS_MASK 0x00000080
-#define BCHP_CLKGEN_PM_PLL_LDO_POWERUP_ISO_CLOCK_PLL_SDS_SHIFT 7
-#define BCHP_CLKGEN_PM_PLL_LDO_POWERUP_ISO_CLOCK_PLL_SDS_DEFAULT 0x00000000
-
-/* CLKGEN :: PM_PLL_LDO_POWERUP :: ISO_CLOCK_PLL_SC1 [06:06] */
-#define BCHP_CLKGEN_PM_PLL_LDO_POWERUP_ISO_CLOCK_PLL_SC1_MASK 0x00000040
-#define BCHP_CLKGEN_PM_PLL_LDO_POWERUP_ISO_CLOCK_PLL_SC1_SHIFT 6
-#define BCHP_CLKGEN_PM_PLL_LDO_POWERUP_ISO_CLOCK_PLL_SC1_DEFAULT 0x00000000
-
-/* CLKGEN :: PM_PLL_LDO_POWERUP :: ISO_CLOCK_PLL_SC0 [05:05] */
-#define BCHP_CLKGEN_PM_PLL_LDO_POWERUP_ISO_CLOCK_PLL_SC0_MASK 0x00000020
-#define BCHP_CLKGEN_PM_PLL_LDO_POWERUP_ISO_CLOCK_PLL_SC0_SHIFT 5
-#define BCHP_CLKGEN_PM_PLL_LDO_POWERUP_ISO_CLOCK_PLL_SC0_DEFAULT 0x00000000
-
-/* CLKGEN :: PM_PLL_LDO_POWERUP :: ISO_CLOCK_PLL_RAAGA [04:04] */
-#define BCHP_CLKGEN_PM_PLL_LDO_POWERUP_ISO_CLOCK_PLL_RAAGA_MASK 0x00000010
-#define BCHP_CLKGEN_PM_PLL_LDO_POWERUP_ISO_CLOCK_PLL_RAAGA_SHIFT 4
-#define BCHP_CLKGEN_PM_PLL_LDO_POWERUP_ISO_CLOCK_PLL_RAAGA_DEFAULT 0x00000000
-
-/* CLKGEN :: PM_PLL_LDO_POWERUP :: ISO_CLOCK_PLL_NETWORK [03:03] */
-#define BCHP_CLKGEN_PM_PLL_LDO_POWERUP_ISO_CLOCK_PLL_NETWORK_MASK 0x00000008
-#define BCHP_CLKGEN_PM_PLL_LDO_POWERUP_ISO_CLOCK_PLL_NETWORK_SHIFT 3
-#define BCHP_CLKGEN_PM_PLL_LDO_POWERUP_ISO_CLOCK_PLL_NETWORK_DEFAULT 0x00000000
-
-/* CLKGEN :: PM_PLL_LDO_POWERUP :: ISO_CLOCK_PLL_MOCA [02:02] */
-#define BCHP_CLKGEN_PM_PLL_LDO_POWERUP_ISO_CLOCK_PLL_MOCA_MASK 0x00000004
-#define BCHP_CLKGEN_PM_PLL_LDO_POWERUP_ISO_CLOCK_PLL_MOCA_SHIFT 2
-#define BCHP_CLKGEN_PM_PLL_LDO_POWERUP_ISO_CLOCK_PLL_MOCA_DEFAULT 0x00000000
-
-/* CLKGEN :: PM_PLL_LDO_POWERUP :: ISO_CLOCK_PLL_LC [01:01] */
-#define BCHP_CLKGEN_PM_PLL_LDO_POWERUP_ISO_CLOCK_PLL_LC_MASK 0x00000002
-#define BCHP_CLKGEN_PM_PLL_LDO_POWERUP_ISO_CLOCK_PLL_LC_SHIFT 1
-#define BCHP_CLKGEN_PM_PLL_LDO_POWERUP_ISO_CLOCK_PLL_LC_DEFAULT 0x00000000
-
-/* CLKGEN :: PM_PLL_LDO_POWERUP :: ISO_CLOCK_PLL_HVD [00:00] */
-#define BCHP_CLKGEN_PM_PLL_LDO_POWERUP_ISO_CLOCK_PLL_HVD_MASK 0x00000001
-#define BCHP_CLKGEN_PM_PLL_LDO_POWERUP_ISO_CLOCK_PLL_HVD_SHIFT 0
-#define BCHP_CLKGEN_PM_PLL_LDO_POWERUP_ISO_CLOCK_PLL_HVD_DEFAULT 0x00000000
-
-/***************************************************************************
- *PROD_OTP_INST_CLOCK_DISABLE - Disable PROD_OTP_INST's clocks
- ***************************************************************************/
-/* CLKGEN :: PROD_OTP_INST_CLOCK_DISABLE :: reserved0 [31:02] */
-#define BCHP_CLKGEN_PROD_OTP_INST_CLOCK_DISABLE_reserved0_MASK 0xfffffffc
-#define BCHP_CLKGEN_PROD_OTP_INST_CLOCK_DISABLE_reserved0_SHIFT 2
-
-/* CLKGEN :: PROD_OTP_INST_CLOCK_DISABLE :: DISABLE_POTP_JTAGOTP_CLOCK [01:01] */
-#define BCHP_CLKGEN_PROD_OTP_INST_CLOCK_DISABLE_DISABLE_POTP_JTAGOTP_CLOCK_MASK 0x00000002
-#define BCHP_CLKGEN_PROD_OTP_INST_CLOCK_DISABLE_DISABLE_POTP_JTAGOTP_CLOCK_SHIFT 1
-#define BCHP_CLKGEN_PROD_OTP_INST_CLOCK_DISABLE_DISABLE_POTP_JTAGOTP_CLOCK_DEFAULT 0x00000000
-
-/* CLKGEN :: PROD_OTP_INST_CLOCK_DISABLE :: DISABLE_POTP_ALWAYSON_CLOCK [00:00] */
-#define BCHP_CLKGEN_PROD_OTP_INST_CLOCK_DISABLE_DISABLE_POTP_ALWAYSON_CLOCK_MASK 0x00000001
-#define BCHP_CLKGEN_PROD_OTP_INST_CLOCK_DISABLE_DISABLE_POTP_ALWAYSON_CLOCK_SHIFT 0
-#define BCHP_CLKGEN_PROD_OTP_INST_CLOCK_DISABLE_DISABLE_POTP_ALWAYSON_CLOCK_DEFAULT 0x00000000
-
-/***************************************************************************
- *PROD_OTP_INST_CLOCK_DISABLE_STATUS - Clock Disable Status
- ***************************************************************************/
-/* CLKGEN :: PROD_OTP_INST_CLOCK_DISABLE_STATUS :: reserved0 [31:02] */
-#define BCHP_CLKGEN_PROD_OTP_INST_CLOCK_DISABLE_STATUS_reserved0_MASK 0xfffffffc
-#define BCHP_CLKGEN_PROD_OTP_INST_CLOCK_DISABLE_STATUS_reserved0_SHIFT 2
-
-/* CLKGEN :: PROD_OTP_INST_CLOCK_DISABLE_STATUS :: DISABLE_POTP_JTAGOTP_CLOCK_STATUS [01:01] */
-#define BCHP_CLKGEN_PROD_OTP_INST_CLOCK_DISABLE_STATUS_DISABLE_POTP_JTAGOTP_CLOCK_STATUS_MASK 0x00000002
-#define BCHP_CLKGEN_PROD_OTP_INST_CLOCK_DISABLE_STATUS_DISABLE_POTP_JTAGOTP_CLOCK_STATUS_SHIFT 1
-
-/* CLKGEN :: PROD_OTP_INST_CLOCK_DISABLE_STATUS :: DISABLE_POTP_ALWAYSON_CLOCK_STATUS [00:00] */
-#define BCHP_CLKGEN_PROD_OTP_INST_CLOCK_DISABLE_STATUS_DISABLE_POTP_ALWAYSON_CLOCK_STATUS_MASK 0x00000001
-#define BCHP_CLKGEN_PROD_OTP_INST_CLOCK_DISABLE_STATUS_DISABLE_POTP_ALWAYSON_CLOCK_STATUS_SHIFT 0
-
-/***************************************************************************
- *PROD_OTP_INST_CLOCK_ENABLE - Prod otp inst clock enable
- ***************************************************************************/
-/* CLKGEN :: PROD_OTP_INST_CLOCK_ENABLE :: reserved0 [31:02] */
-#define BCHP_CLKGEN_PROD_OTP_INST_CLOCK_ENABLE_reserved0_MASK 0xfffffffc
-#define BCHP_CLKGEN_PROD_OTP_INST_CLOCK_ENABLE_reserved0_SHIFT 2
-
-/* CLKGEN :: PROD_OTP_INST_CLOCK_ENABLE :: POTP_GISB_CLOCK_ENABLE [01:01] */
-#define BCHP_CLKGEN_PROD_OTP_INST_CLOCK_ENABLE_POTP_GISB_CLOCK_ENABLE_MASK 0x00000002
-#define BCHP_CLKGEN_PROD_OTP_INST_CLOCK_ENABLE_POTP_GISB_CLOCK_ENABLE_SHIFT 1
-#define BCHP_CLKGEN_PROD_OTP_INST_CLOCK_ENABLE_POTP_GISB_CLOCK_ENABLE_DEFAULT 0x00000001
-
-/* CLKGEN :: PROD_OTP_INST_CLOCK_ENABLE :: POTP_54_CLOCK_ENABLE [00:00] */
-#define BCHP_CLKGEN_PROD_OTP_INST_CLOCK_ENABLE_POTP_54_CLOCK_ENABLE_MASK 0x00000001
-#define BCHP_CLKGEN_PROD_OTP_INST_CLOCK_ENABLE_POTP_54_CLOCK_ENABLE_SHIFT 0
-#define BCHP_CLKGEN_PROD_OTP_INST_CLOCK_ENABLE_POTP_54_CLOCK_ENABLE_DEFAULT 0x00000001
-
-/***************************************************************************
- *PROD_OTP_INST_CLOCK_ENABLE_STATUS - Clock Enable Status
- ***************************************************************************/
-/* CLKGEN :: PROD_OTP_INST_CLOCK_ENABLE_STATUS :: reserved0 [31:02] */
-#define BCHP_CLKGEN_PROD_OTP_INST_CLOCK_ENABLE_STATUS_reserved0_MASK 0xfffffffc
-#define BCHP_CLKGEN_PROD_OTP_INST_CLOCK_ENABLE_STATUS_reserved0_SHIFT 2
-
-/* CLKGEN :: PROD_OTP_INST_CLOCK_ENABLE_STATUS :: POTP_GISB_CLOCK_ENABLE_STATUS [01:01] */
-#define BCHP_CLKGEN_PROD_OTP_INST_CLOCK_ENABLE_STATUS_POTP_GISB_CLOCK_ENABLE_STATUS_MASK 0x00000002
-#define BCHP_CLKGEN_PROD_OTP_INST_CLOCK_ENABLE_STATUS_POTP_GISB_CLOCK_ENABLE_STATUS_SHIFT 1
-
-/* CLKGEN :: PROD_OTP_INST_CLOCK_ENABLE_STATUS :: POTP_54_CLOCK_ENABLE_STATUS [00:00] */
-#define BCHP_CLKGEN_PROD_OTP_INST_CLOCK_ENABLE_STATUS_POTP_54_CLOCK_ENABLE_STATUS_MASK 0x00000001
-#define BCHP_CLKGEN_PROD_OTP_INST_CLOCK_ENABLE_STATUS_POTP_54_CLOCK_ENABLE_STATUS_SHIFT 0
-
-/***************************************************************************
- *RAAGA_DSP_TOP_0_INST_CKTAPSEL - Raaga dsp top 0 inst cktapsel
- ***************************************************************************/
-/* CLKGEN :: RAAGA_DSP_TOP_0_INST_CKTAPSEL :: reserved0 [31:12] */
-#define BCHP_CLKGEN_RAAGA_DSP_TOP_0_INST_CKTAPSEL_reserved0_MASK 0xfffff000
-#define BCHP_CLKGEN_RAAGA_DSP_TOP_0_INST_CKTAPSEL_reserved0_SHIFT 12
-
-/* CLKGEN :: RAAGA_DSP_TOP_0_INST_CKTAPSEL :: SCB_CKTAP1_CKTAPSEL [11:06] */
-#define BCHP_CLKGEN_RAAGA_DSP_TOP_0_INST_CKTAPSEL_SCB_CKTAP1_CKTAPSEL_MASK 0x00000fc0
-#define BCHP_CLKGEN_RAAGA_DSP_TOP_0_INST_CKTAPSEL_SCB_CKTAP1_CKTAPSEL_SHIFT 6
-#define BCHP_CLKGEN_RAAGA_DSP_TOP_0_INST_CKTAPSEL_SCB_CKTAP1_CKTAPSEL_DEFAULT 0x00000000
-
-/* CLKGEN :: RAAGA_DSP_TOP_0_INST_CKTAPSEL :: SCB_CKTAP0_CKTAPSEL [05:00] */
-#define BCHP_CLKGEN_RAAGA_DSP_TOP_0_INST_CKTAPSEL_SCB_CKTAP0_CKTAPSEL_MASK 0x0000003f
-#define BCHP_CLKGEN_RAAGA_DSP_TOP_0_INST_CKTAPSEL_SCB_CKTAP0_CKTAPSEL_SHIFT 0
-#define BCHP_CLKGEN_RAAGA_DSP_TOP_0_INST_CKTAPSEL_SCB_CKTAP0_CKTAPSEL_DEFAULT 0x00000000
-
-/***************************************************************************
- *RAAGA_DSP_TOP_0_INST_CLOCK_ENABLE - Raaga dsp top 0 inst clock enable
- ***************************************************************************/
-/* CLKGEN :: RAAGA_DSP_TOP_0_INST_CLOCK_ENABLE :: reserved0 [31:05] */
-#define BCHP_CLKGEN_RAAGA_DSP_TOP_0_INST_CLOCK_ENABLE_reserved0_MASK 0xffffffe0
-#define BCHP_CLKGEN_RAAGA_DSP_TOP_0_INST_CLOCK_ENABLE_reserved0_SHIFT 5
-
-/* CLKGEN :: RAAGA_DSP_TOP_0_INST_CLOCK_ENABLE :: RAAGA_SCB_CLOCK_ENABLE [04:04] */
-#define BCHP_CLKGEN_RAAGA_DSP_TOP_0_INST_CLOCK_ENABLE_RAAGA_SCB_CLOCK_ENABLE_MASK 0x00000010
-#define BCHP_CLKGEN_RAAGA_DSP_TOP_0_INST_CLOCK_ENABLE_RAAGA_SCB_CLOCK_ENABLE_SHIFT 4
-#define BCHP_CLKGEN_RAAGA_DSP_TOP_0_INST_CLOCK_ENABLE_RAAGA_SCB_CLOCK_ENABLE_DEFAULT 0x00000001
-
-/* CLKGEN :: RAAGA_DSP_TOP_0_INST_CLOCK_ENABLE :: RAAGA_GISB_CLOCK_ENABLE [03:03] */
-#define BCHP_CLKGEN_RAAGA_DSP_TOP_0_INST_CLOCK_ENABLE_RAAGA_GISB_CLOCK_ENABLE_MASK 0x00000008
-#define BCHP_CLKGEN_RAAGA_DSP_TOP_0_INST_CLOCK_ENABLE_RAAGA_GISB_CLOCK_ENABLE_SHIFT 3
-#define BCHP_CLKGEN_RAAGA_DSP_TOP_0_INST_CLOCK_ENABLE_RAAGA_GISB_CLOCK_ENABLE_DEFAULT 0x00000001
-
-/* CLKGEN :: RAAGA_DSP_TOP_0_INST_CLOCK_ENABLE :: RAAGA_DSP_CLOCK_ENABLE [02:02] */
-#define BCHP_CLKGEN_RAAGA_DSP_TOP_0_INST_CLOCK_ENABLE_RAAGA_DSP_CLOCK_ENABLE_MASK 0x00000004
-#define BCHP_CLKGEN_RAAGA_DSP_TOP_0_INST_CLOCK_ENABLE_RAAGA_DSP_CLOCK_ENABLE_SHIFT 2
-#define BCHP_CLKGEN_RAAGA_DSP_TOP_0_INST_CLOCK_ENABLE_RAAGA_DSP_CLOCK_ENABLE_DEFAULT 0x00000001
-
-/* CLKGEN :: RAAGA_DSP_TOP_0_INST_CLOCK_ENABLE :: RAAGA_54_CLOCK_ENABLE [01:01] */
-#define BCHP_CLKGEN_RAAGA_DSP_TOP_0_INST_CLOCK_ENABLE_RAAGA_54_CLOCK_ENABLE_MASK 0x00000002
-#define BCHP_CLKGEN_RAAGA_DSP_TOP_0_INST_CLOCK_ENABLE_RAAGA_54_CLOCK_ENABLE_SHIFT 1
-#define BCHP_CLKGEN_RAAGA_DSP_TOP_0_INST_CLOCK_ENABLE_RAAGA_54_CLOCK_ENABLE_DEFAULT 0x00000001
-
-/* CLKGEN :: RAAGA_DSP_TOP_0_INST_CLOCK_ENABLE :: RAAGA_108_CLOCK_ENABLE [00:00] */
-#define BCHP_CLKGEN_RAAGA_DSP_TOP_0_INST_CLOCK_ENABLE_RAAGA_108_CLOCK_ENABLE_MASK 0x00000001
-#define BCHP_CLKGEN_RAAGA_DSP_TOP_0_INST_CLOCK_ENABLE_RAAGA_108_CLOCK_ENABLE_SHIFT 0
-#define BCHP_CLKGEN_RAAGA_DSP_TOP_0_INST_CLOCK_ENABLE_RAAGA_108_CLOCK_ENABLE_DEFAULT 0x00000001
-
-/***************************************************************************
- *RAAGA_DSP_TOP_0_INST_CLOCK_ENABLE_STATUS - Clock Enable Status
- ***************************************************************************/
-/* CLKGEN :: RAAGA_DSP_TOP_0_INST_CLOCK_ENABLE_STATUS :: reserved0 [31:05] */
-#define BCHP_CLKGEN_RAAGA_DSP_TOP_0_INST_CLOCK_ENABLE_STATUS_reserved0_MASK 0xffffffe0
-#define BCHP_CLKGEN_RAAGA_DSP_TOP_0_INST_CLOCK_ENABLE_STATUS_reserved0_SHIFT 5
-
-/* CLKGEN :: RAAGA_DSP_TOP_0_INST_CLOCK_ENABLE_STATUS :: RAAGA_SCB_CLOCK_ENABLE_STATUS [04:04] */
-#define BCHP_CLKGEN_RAAGA_DSP_TOP_0_INST_CLOCK_ENABLE_STATUS_RAAGA_SCB_CLOCK_ENABLE_STATUS_MASK 0x00000010
-#define BCHP_CLKGEN_RAAGA_DSP_TOP_0_INST_CLOCK_ENABLE_STATUS_RAAGA_SCB_CLOCK_ENABLE_STATUS_SHIFT 4
-
-/* CLKGEN :: RAAGA_DSP_TOP_0_INST_CLOCK_ENABLE_STATUS :: RAAGA_GISB_CLOCK_ENABLE_STATUS [03:03] */
-#define BCHP_CLKGEN_RAAGA_DSP_TOP_0_INST_CLOCK_ENABLE_STATUS_RAAGA_GISB_CLOCK_ENABLE_STATUS_MASK 0x00000008
-#define BCHP_CLKGEN_RAAGA_DSP_TOP_0_INST_CLOCK_ENABLE_STATUS_RAAGA_GISB_CLOCK_ENABLE_STATUS_SHIFT 3
-
-/* CLKGEN :: RAAGA_DSP_TOP_0_INST_CLOCK_ENABLE_STATUS :: RAAGA_DSP_CLOCK_ENABLE_STATUS [02:02] */
-#define BCHP_CLKGEN_RAAGA_DSP_TOP_0_INST_CLOCK_ENABLE_STATUS_RAAGA_DSP_CLOCK_ENABLE_STATUS_MASK 0x00000004
-#define BCHP_CLKGEN_RAAGA_DSP_TOP_0_INST_CLOCK_ENABLE_STATUS_RAAGA_DSP_CLOCK_ENABLE_STATUS_SHIFT 2
-
-/* CLKGEN :: RAAGA_DSP_TOP_0_INST_CLOCK_ENABLE_STATUS :: RAAGA_54_CLOCK_ENABLE_STATUS [01:01] */
-#define BCHP_CLKGEN_RAAGA_DSP_TOP_0_INST_CLOCK_ENABLE_STATUS_RAAGA_54_CLOCK_ENABLE_STATUS_MASK 0x00000002
-#define BCHP_CLKGEN_RAAGA_DSP_TOP_0_INST_CLOCK_ENABLE_STATUS_RAAGA_54_CLOCK_ENABLE_STATUS_SHIFT 1
-
-/* CLKGEN :: RAAGA_DSP_TOP_0_INST_CLOCK_ENABLE_STATUS :: RAAGA_108_CLOCK_ENABLE_STATUS [00:00] */
-#define BCHP_CLKGEN_RAAGA_DSP_TOP_0_INST_CLOCK_ENABLE_STATUS_RAAGA_108_CLOCK_ENABLE_STATUS_MASK 0x00000001
-#define BCHP_CLKGEN_RAAGA_DSP_TOP_0_INST_CLOCK_ENABLE_STATUS_RAAGA_108_CLOCK_ENABLE_STATUS_SHIFT 0
-
-/***************************************************************************
- *RAAGA_DSP_TOP_0_INST_OBSERVE_CLOCK - Raaga dsp top 0 inst observe clock
- ***************************************************************************/
-/* CLKGEN :: RAAGA_DSP_TOP_0_INST_OBSERVE_CLOCK :: reserved0 [31:02] */
-#define BCHP_CLKGEN_RAAGA_DSP_TOP_0_INST_OBSERVE_CLOCK_reserved0_MASK 0xfffffffc
-#define BCHP_CLKGEN_RAAGA_DSP_TOP_0_INST_OBSERVE_CLOCK_reserved0_SHIFT 2
-
-/* CLKGEN :: RAAGA_DSP_TOP_0_INST_OBSERVE_CLOCK :: RAAGA_ENABLE_OBSERVE_CLOCK [01:01] */
-#define BCHP_CLKGEN_RAAGA_DSP_TOP_0_INST_OBSERVE_CLOCK_RAAGA_ENABLE_OBSERVE_CLOCK_MASK 0x00000002
-#define BCHP_CLKGEN_RAAGA_DSP_TOP_0_INST_OBSERVE_CLOCK_RAAGA_ENABLE_OBSERVE_CLOCK_SHIFT 1
-#define BCHP_CLKGEN_RAAGA_DSP_TOP_0_INST_OBSERVE_CLOCK_RAAGA_ENABLE_OBSERVE_CLOCK_DEFAULT 0x00000000
-
-/* CLKGEN :: RAAGA_DSP_TOP_0_INST_OBSERVE_CLOCK :: RAAGA_ENABLE_DIVIDER_OBSERVE_CLOCK [00:00] */
-#define BCHP_CLKGEN_RAAGA_DSP_TOP_0_INST_OBSERVE_CLOCK_RAAGA_ENABLE_DIVIDER_OBSERVE_CLOCK_MASK 0x00000001
-#define BCHP_CLKGEN_RAAGA_DSP_TOP_0_INST_OBSERVE_CLOCK_RAAGA_ENABLE_DIVIDER_OBSERVE_CLOCK_SHIFT 0
-#define BCHP_CLKGEN_RAAGA_DSP_TOP_0_INST_OBSERVE_CLOCK_RAAGA_ENABLE_DIVIDER_OBSERVE_CLOCK_DEFAULT 0x00000000
-
-/***************************************************************************
- *RFM_TOP_INST_CLOCK_ENABLE - Rfm top inst clock enable
- ***************************************************************************/
-/* CLKGEN :: RFM_TOP_INST_CLOCK_ENABLE :: reserved0 [31:03] */
-#define BCHP_CLKGEN_RFM_TOP_INST_CLOCK_ENABLE_reserved0_MASK 0xfffffff8
-#define BCHP_CLKGEN_RFM_TOP_INST_CLOCK_ENABLE_reserved0_SHIFT 3
-
-/* CLKGEN :: RFM_TOP_INST_CLOCK_ENABLE :: RFM_GISB_CLOCK_ENABLE [02:02] */
-#define BCHP_CLKGEN_RFM_TOP_INST_CLOCK_ENABLE_RFM_GISB_CLOCK_ENABLE_MASK 0x00000004
-#define BCHP_CLKGEN_RFM_TOP_INST_CLOCK_ENABLE_RFM_GISB_CLOCK_ENABLE_SHIFT 2
-#define BCHP_CLKGEN_RFM_TOP_INST_CLOCK_ENABLE_RFM_GISB_CLOCK_ENABLE_DEFAULT 0x00000001
-
-/* CLKGEN :: RFM_TOP_INST_CLOCK_ENABLE :: RFM_54_CLOCK_ENABLE [01:01] */
-#define BCHP_CLKGEN_RFM_TOP_INST_CLOCK_ENABLE_RFM_54_CLOCK_ENABLE_MASK 0x00000002
-#define BCHP_CLKGEN_RFM_TOP_INST_CLOCK_ENABLE_RFM_54_CLOCK_ENABLE_SHIFT 1
-#define BCHP_CLKGEN_RFM_TOP_INST_CLOCK_ENABLE_RFM_54_CLOCK_ENABLE_DEFAULT 0x00000001
-
-/* CLKGEN :: RFM_TOP_INST_CLOCK_ENABLE :: RFM_108_CLOCK_ENABLE [00:00] */
-#define BCHP_CLKGEN_RFM_TOP_INST_CLOCK_ENABLE_RFM_108_CLOCK_ENABLE_MASK 0x00000001
-#define BCHP_CLKGEN_RFM_TOP_INST_CLOCK_ENABLE_RFM_108_CLOCK_ENABLE_SHIFT 0
-#define BCHP_CLKGEN_RFM_TOP_INST_CLOCK_ENABLE_RFM_108_CLOCK_ENABLE_DEFAULT 0x00000001
-
-/***************************************************************************
- *RFM_TOP_INST_CLOCK_ENABLE_STATUS - Clock Enable Status
- ***************************************************************************/
-/* CLKGEN :: RFM_TOP_INST_CLOCK_ENABLE_STATUS :: reserved0 [31:03] */
-#define BCHP_CLKGEN_RFM_TOP_INST_CLOCK_ENABLE_STATUS_reserved0_MASK 0xfffffff8
-#define BCHP_CLKGEN_RFM_TOP_INST_CLOCK_ENABLE_STATUS_reserved0_SHIFT 3
-
-/* CLKGEN :: RFM_TOP_INST_CLOCK_ENABLE_STATUS :: RFM_GISB_CLOCK_ENABLE_STATUS [02:02] */
-#define BCHP_CLKGEN_RFM_TOP_INST_CLOCK_ENABLE_STATUS_RFM_GISB_CLOCK_ENABLE_STATUS_MASK 0x00000004
-#define BCHP_CLKGEN_RFM_TOP_INST_CLOCK_ENABLE_STATUS_RFM_GISB_CLOCK_ENABLE_STATUS_SHIFT 2
-
-/* CLKGEN :: RFM_TOP_INST_CLOCK_ENABLE_STATUS :: RFM_54_CLOCK_ENABLE_STATUS [01:01] */
-#define BCHP_CLKGEN_RFM_TOP_INST_CLOCK_ENABLE_STATUS_RFM_54_CLOCK_ENABLE_STATUS_MASK 0x00000002
-#define BCHP_CLKGEN_RFM_TOP_INST_CLOCK_ENABLE_STATUS_RFM_54_CLOCK_ENABLE_STATUS_SHIFT 1
-
-/* CLKGEN :: RFM_TOP_INST_CLOCK_ENABLE_STATUS :: RFM_108_CLOCK_ENABLE_STATUS [00:00] */
-#define BCHP_CLKGEN_RFM_TOP_INST_CLOCK_ENABLE_STATUS_RFM_108_CLOCK_ENABLE_STATUS_MASK 0x00000001
-#define BCHP_CLKGEN_RFM_TOP_INST_CLOCK_ENABLE_STATUS_RFM_108_CLOCK_ENABLE_STATUS_SHIFT 0
-
-/***************************************************************************
- *RFM_TOP_INST_OBSERVE_CLOCK - Rfm top inst observe clock
- ***************************************************************************/
-/* CLKGEN :: RFM_TOP_INST_OBSERVE_CLOCK :: reserved0 [31:06] */
-#define BCHP_CLKGEN_RFM_TOP_INST_OBSERVE_CLOCK_reserved0_MASK 0xffffffc0
-#define BCHP_CLKGEN_RFM_TOP_INST_OBSERVE_CLOCK_reserved0_SHIFT 6
-
-/* CLKGEN :: RFM_TOP_INST_OBSERVE_CLOCK :: RFM_ENABLE_OBSERVE_CLOCK [05:05] */
-#define BCHP_CLKGEN_RFM_TOP_INST_OBSERVE_CLOCK_RFM_ENABLE_OBSERVE_CLOCK_MASK 0x00000020
-#define BCHP_CLKGEN_RFM_TOP_INST_OBSERVE_CLOCK_RFM_ENABLE_OBSERVE_CLOCK_SHIFT 5
-#define BCHP_CLKGEN_RFM_TOP_INST_OBSERVE_CLOCK_RFM_ENABLE_OBSERVE_CLOCK_DEFAULT 0x00000000
-
-/* CLKGEN :: RFM_TOP_INST_OBSERVE_CLOCK :: RFM_ENABLE_DIVIDER_OBSERVE_CLOCK [04:04] */
-#define BCHP_CLKGEN_RFM_TOP_INST_OBSERVE_CLOCK_RFM_ENABLE_DIVIDER_OBSERVE_CLOCK_MASK 0x00000010
-#define BCHP_CLKGEN_RFM_TOP_INST_OBSERVE_CLOCK_RFM_ENABLE_DIVIDER_OBSERVE_CLOCK_SHIFT 4
-#define BCHP_CLKGEN_RFM_TOP_INST_OBSERVE_CLOCK_RFM_ENABLE_DIVIDER_OBSERVE_CLOCK_DEFAULT 0x00000000
-
-/* CLKGEN :: RFM_TOP_INST_OBSERVE_CLOCK :: RFM_CONTROL_OBSERVE_CLOCK [03:00] */
-#define BCHP_CLKGEN_RFM_TOP_INST_OBSERVE_CLOCK_RFM_CONTROL_OBSERVE_CLOCK_MASK 0x0000000f
-#define BCHP_CLKGEN_RFM_TOP_INST_OBSERVE_CLOCK_RFM_CONTROL_OBSERVE_CLOCK_SHIFT 0
-#define BCHP_CLKGEN_RFM_TOP_INST_OBSERVE_CLOCK_RFM_CONTROL_OBSERVE_CLOCK_DEFAULT 0x00000000
-
-/***************************************************************************
- *SATA3_PCIE_TOP_INST_CKTAPSEL - Sata3 pcie top inst cktapsel
- ***************************************************************************/
-/* CLKGEN :: SATA3_PCIE_TOP_INST_CKTAPSEL :: reserved0 [31:12] */
-#define BCHP_CLKGEN_SATA3_PCIE_TOP_INST_CKTAPSEL_reserved0_MASK 0xfffff000
-#define BCHP_CLKGEN_SATA3_PCIE_TOP_INST_CKTAPSEL_reserved0_SHIFT 12
-
-/* CLKGEN :: SATA3_PCIE_TOP_INST_CKTAPSEL :: SCB_CKTAP1_CKTAPSEL [11:06] */
-#define BCHP_CLKGEN_SATA3_PCIE_TOP_INST_CKTAPSEL_SCB_CKTAP1_CKTAPSEL_MASK 0x00000fc0
-#define BCHP_CLKGEN_SATA3_PCIE_TOP_INST_CKTAPSEL_SCB_CKTAP1_CKTAPSEL_SHIFT 6
-#define BCHP_CLKGEN_SATA3_PCIE_TOP_INST_CKTAPSEL_SCB_CKTAP1_CKTAPSEL_DEFAULT 0x00000000
-
-/* CLKGEN :: SATA3_PCIE_TOP_INST_CKTAPSEL :: SCB_CKTAP0_CKTAPSEL [05:00] */
-#define BCHP_CLKGEN_SATA3_PCIE_TOP_INST_CKTAPSEL_SCB_CKTAP0_CKTAPSEL_MASK 0x0000003f
-#define BCHP_CLKGEN_SATA3_PCIE_TOP_INST_CKTAPSEL_SCB_CKTAP0_CKTAPSEL_SHIFT 0
-#define BCHP_CLKGEN_SATA3_PCIE_TOP_INST_CKTAPSEL_SCB_CKTAP0_CKTAPSEL_DEFAULT 0x00000000
-
-/***************************************************************************
- *SATA3_PCIE_TOP_INST_CLOCK_DISABLE - Disable SATA3_PCIE_TOP_INST's clocks
- ***************************************************************************/
-/* CLKGEN :: SATA3_PCIE_TOP_INST_CLOCK_DISABLE :: reserved0 [31:02] */
-#define BCHP_CLKGEN_SATA3_PCIE_TOP_INST_CLOCK_DISABLE_reserved0_MASK 0xfffffffc
-#define BCHP_CLKGEN_SATA3_PCIE_TOP_INST_CLOCK_DISABLE_reserved0_SHIFT 2
-
-/* CLKGEN :: SATA3_PCIE_TOP_INST_CLOCK_DISABLE :: DISABLE_SATA3_AT_SPEED_SCAN_CLOCK [01:01] */
-#define BCHP_CLKGEN_SATA3_PCIE_TOP_INST_CLOCK_DISABLE_DISABLE_SATA3_AT_SPEED_SCAN_CLOCK_MASK 0x00000002
-#define BCHP_CLKGEN_SATA3_PCIE_TOP_INST_CLOCK_DISABLE_DISABLE_SATA3_AT_SPEED_SCAN_CLOCK_SHIFT 1
-#define BCHP_CLKGEN_SATA3_PCIE_TOP_INST_CLOCK_DISABLE_DISABLE_SATA3_AT_SPEED_SCAN_CLOCK_DEFAULT 0x00000000
-
-/* CLKGEN :: SATA3_PCIE_TOP_INST_CLOCK_DISABLE :: DISABLE_PCIE1_ALWAYSON_CLOCK [00:00] */
-#define BCHP_CLKGEN_SATA3_PCIE_TOP_INST_CLOCK_DISABLE_DISABLE_PCIE1_ALWAYSON_CLOCK_MASK 0x00000001
-#define BCHP_CLKGEN_SATA3_PCIE_TOP_INST_CLOCK_DISABLE_DISABLE_PCIE1_ALWAYSON_CLOCK_SHIFT 0
-#define BCHP_CLKGEN_SATA3_PCIE_TOP_INST_CLOCK_DISABLE_DISABLE_PCIE1_ALWAYSON_CLOCK_DEFAULT 0x00000000
-
-/***************************************************************************
- *SATA3_PCIE_TOP_INST_CLOCK_DISABLE_STATUS - Clock Disable Status
- ***************************************************************************/
-/* CLKGEN :: SATA3_PCIE_TOP_INST_CLOCK_DISABLE_STATUS :: reserved0 [31:02] */
-#define BCHP_CLKGEN_SATA3_PCIE_TOP_INST_CLOCK_DISABLE_STATUS_reserved0_MASK 0xfffffffc
-#define BCHP_CLKGEN_SATA3_PCIE_TOP_INST_CLOCK_DISABLE_STATUS_reserved0_SHIFT 2
-
-/* CLKGEN :: SATA3_PCIE_TOP_INST_CLOCK_DISABLE_STATUS :: DISABLE_SATA3_AT_SPEED_SCAN_CLOCK_STATUS [01:01] */
-#define BCHP_CLKGEN_SATA3_PCIE_TOP_INST_CLOCK_DISABLE_STATUS_DISABLE_SATA3_AT_SPEED_SCAN_CLOCK_STATUS_MASK 0x00000002
-#define BCHP_CLKGEN_SATA3_PCIE_TOP_INST_CLOCK_DISABLE_STATUS_DISABLE_SATA3_AT_SPEED_SCAN_CLOCK_STATUS_SHIFT 1
-
-/* CLKGEN :: SATA3_PCIE_TOP_INST_CLOCK_DISABLE_STATUS :: DISABLE_PCIE1_ALWAYSON_CLOCK_STATUS [00:00] */
-#define BCHP_CLKGEN_SATA3_PCIE_TOP_INST_CLOCK_DISABLE_STATUS_DISABLE_PCIE1_ALWAYSON_CLOCK_STATUS_MASK 0x00000001
-#define BCHP_CLKGEN_SATA3_PCIE_TOP_INST_CLOCK_DISABLE_STATUS_DISABLE_PCIE1_ALWAYSON_CLOCK_STATUS_SHIFT 0
-
-/***************************************************************************
- *SATA3_PCIE_TOP_INST_CLOCK_ENABLE_PCIE - Sata3 pcie top inst clock enable pcie
- ***************************************************************************/
-/* CLKGEN :: SATA3_PCIE_TOP_INST_CLOCK_ENABLE_PCIE :: reserved0 [31:04] */
-#define BCHP_CLKGEN_SATA3_PCIE_TOP_INST_CLOCK_ENABLE_PCIE_reserved0_MASK 0xfffffff0
-#define BCHP_CLKGEN_SATA3_PCIE_TOP_INST_CLOCK_ENABLE_PCIE_reserved0_SHIFT 4
-
-/* CLKGEN :: SATA3_PCIE_TOP_INST_CLOCK_ENABLE_PCIE :: SATA3_108_CLOCK_ENABLE_PCIE [03:03] */
-#define BCHP_CLKGEN_SATA3_PCIE_TOP_INST_CLOCK_ENABLE_PCIE_SATA3_108_CLOCK_ENABLE_PCIE_MASK 0x00000008
-#define BCHP_CLKGEN_SATA3_PCIE_TOP_INST_CLOCK_ENABLE_PCIE_SATA3_108_CLOCK_ENABLE_PCIE_SHIFT 3
-#define BCHP_CLKGEN_SATA3_PCIE_TOP_INST_CLOCK_ENABLE_PCIE_SATA3_108_CLOCK_ENABLE_PCIE_DEFAULT 0x00000001
-
-/* CLKGEN :: SATA3_PCIE_TOP_INST_CLOCK_ENABLE_PCIE :: PCIE1_SCB_CLOCK_ENABLE_PCIE [02:02] */
-#define BCHP_CLKGEN_SATA3_PCIE_TOP_INST_CLOCK_ENABLE_PCIE_PCIE1_SCB_CLOCK_ENABLE_PCIE_MASK 0x00000004
-#define BCHP_CLKGEN_SATA3_PCIE_TOP_INST_CLOCK_ENABLE_PCIE_PCIE1_SCB_CLOCK_ENABLE_PCIE_SHIFT 2
-#define BCHP_CLKGEN_SATA3_PCIE_TOP_INST_CLOCK_ENABLE_PCIE_PCIE1_SCB_CLOCK_ENABLE_PCIE_DEFAULT 0x00000001
-
-/* CLKGEN :: SATA3_PCIE_TOP_INST_CLOCK_ENABLE_PCIE :: PCIE1_GISB_CLOCK_ENABLE_PCIE [01:01] */
-#define BCHP_CLKGEN_SATA3_PCIE_TOP_INST_CLOCK_ENABLE_PCIE_PCIE1_GISB_CLOCK_ENABLE_PCIE_MASK 0x00000002
-#define BCHP_CLKGEN_SATA3_PCIE_TOP_INST_CLOCK_ENABLE_PCIE_PCIE1_GISB_CLOCK_ENABLE_PCIE_SHIFT 1
-#define BCHP_CLKGEN_SATA3_PCIE_TOP_INST_CLOCK_ENABLE_PCIE_PCIE1_GISB_CLOCK_ENABLE_PCIE_DEFAULT 0x00000001
-
-/* CLKGEN :: SATA3_PCIE_TOP_INST_CLOCK_ENABLE_PCIE :: PCIE1_54_CLOCK_ENABLE_PCIE [00:00] */
-#define BCHP_CLKGEN_SATA3_PCIE_TOP_INST_CLOCK_ENABLE_PCIE_PCIE1_54_CLOCK_ENABLE_PCIE_MASK 0x00000001
-#define BCHP_CLKGEN_SATA3_PCIE_TOP_INST_CLOCK_ENABLE_PCIE_PCIE1_54_CLOCK_ENABLE_PCIE_SHIFT 0
-#define BCHP_CLKGEN_SATA3_PCIE_TOP_INST_CLOCK_ENABLE_PCIE_PCIE1_54_CLOCK_ENABLE_PCIE_DEFAULT 0x00000001
-
-/***************************************************************************
- *SATA3_PCIE_TOP_INST_CLOCK_ENABLE_PCIE_STATUS - Clock Enable Status
- ***************************************************************************/
-/* CLKGEN :: SATA3_PCIE_TOP_INST_CLOCK_ENABLE_PCIE_STATUS :: reserved0 [31:04] */
-#define BCHP_CLKGEN_SATA3_PCIE_TOP_INST_CLOCK_ENABLE_PCIE_STATUS_reserved0_MASK 0xfffffff0
-#define BCHP_CLKGEN_SATA3_PCIE_TOP_INST_CLOCK_ENABLE_PCIE_STATUS_reserved0_SHIFT 4
-
-/* CLKGEN :: SATA3_PCIE_TOP_INST_CLOCK_ENABLE_PCIE_STATUS :: SATA3_108_CLOCK_ENABLE_PCIE_STATUS [03:03] */
-#define BCHP_CLKGEN_SATA3_PCIE_TOP_INST_CLOCK_ENABLE_PCIE_STATUS_SATA3_108_CLOCK_ENABLE_PCIE_STATUS_MASK 0x00000008
-#define BCHP_CLKGEN_SATA3_PCIE_TOP_INST_CLOCK_ENABLE_PCIE_STATUS_SATA3_108_CLOCK_ENABLE_PCIE_STATUS_SHIFT 3
-
-/* CLKGEN :: SATA3_PCIE_TOP_INST_CLOCK_ENABLE_PCIE_STATUS :: PCIE1_SCB_CLOCK_ENABLE_PCIE_STATUS [02:02] */
-#define BCHP_CLKGEN_SATA3_PCIE_TOP_INST_CLOCK_ENABLE_PCIE_STATUS_PCIE1_SCB_CLOCK_ENABLE_PCIE_STATUS_MASK 0x00000004
-#define BCHP_CLKGEN_SATA3_PCIE_TOP_INST_CLOCK_ENABLE_PCIE_STATUS_PCIE1_SCB_CLOCK_ENABLE_PCIE_STATUS_SHIFT 2
-
-/* CLKGEN :: SATA3_PCIE_TOP_INST_CLOCK_ENABLE_PCIE_STATUS :: PCIE1_GISB_CLOCK_ENABLE_PCIE_STATUS [01:01] */
-#define BCHP_CLKGEN_SATA3_PCIE_TOP_INST_CLOCK_ENABLE_PCIE_STATUS_PCIE1_GISB_CLOCK_ENABLE_PCIE_STATUS_MASK 0x00000002
-#define BCHP_CLKGEN_SATA3_PCIE_TOP_INST_CLOCK_ENABLE_PCIE_STATUS_PCIE1_GISB_CLOCK_ENABLE_PCIE_STATUS_SHIFT 1
-
-/* CLKGEN :: SATA3_PCIE_TOP_INST_CLOCK_ENABLE_PCIE_STATUS :: PCIE1_54_CLOCK_ENABLE_PCIE_STATUS [00:00] */
-#define BCHP_CLKGEN_SATA3_PCIE_TOP_INST_CLOCK_ENABLE_PCIE_STATUS_PCIE1_54_CLOCK_ENABLE_PCIE_STATUS_MASK 0x00000001
-#define BCHP_CLKGEN_SATA3_PCIE_TOP_INST_CLOCK_ENABLE_PCIE_STATUS_PCIE1_54_CLOCK_ENABLE_PCIE_STATUS_SHIFT 0
-
-/***************************************************************************
- *SATA3_PCIE_TOP_INST_CLOCK_ENABLE_SATA3 - Sata3 pcie top inst clock enable sata3
- ***************************************************************************/
-/* CLKGEN :: SATA3_PCIE_TOP_INST_CLOCK_ENABLE_SATA3 :: reserved0 [31:03] */
-#define BCHP_CLKGEN_SATA3_PCIE_TOP_INST_CLOCK_ENABLE_SATA3_reserved0_MASK 0xfffffff8
-#define BCHP_CLKGEN_SATA3_PCIE_TOP_INST_CLOCK_ENABLE_SATA3_reserved0_SHIFT 3
-
-/* CLKGEN :: SATA3_PCIE_TOP_INST_CLOCK_ENABLE_SATA3 :: SATA3_SCB_CLOCK_ENABLE_SATA3 [02:02] */
-#define BCHP_CLKGEN_SATA3_PCIE_TOP_INST_CLOCK_ENABLE_SATA3_SATA3_SCB_CLOCK_ENABLE_SATA3_MASK 0x00000004
-#define BCHP_CLKGEN_SATA3_PCIE_TOP_INST_CLOCK_ENABLE_SATA3_SATA3_SCB_CLOCK_ENABLE_SATA3_SHIFT 2
-#define BCHP_CLKGEN_SATA3_PCIE_TOP_INST_CLOCK_ENABLE_SATA3_SATA3_SCB_CLOCK_ENABLE_SATA3_DEFAULT 0x00000001
-
-/* CLKGEN :: SATA3_PCIE_TOP_INST_CLOCK_ENABLE_SATA3 :: SATA3_GISB_CLOCK_ENABLE_SATA3 [01:01] */
-#define BCHP_CLKGEN_SATA3_PCIE_TOP_INST_CLOCK_ENABLE_SATA3_SATA3_GISB_CLOCK_ENABLE_SATA3_MASK 0x00000002
-#define BCHP_CLKGEN_SATA3_PCIE_TOP_INST_CLOCK_ENABLE_SATA3_SATA3_GISB_CLOCK_ENABLE_SATA3_SHIFT 1
-#define BCHP_CLKGEN_SATA3_PCIE_TOP_INST_CLOCK_ENABLE_SATA3_SATA3_GISB_CLOCK_ENABLE_SATA3_DEFAULT 0x00000001
-
-/* CLKGEN :: SATA3_PCIE_TOP_INST_CLOCK_ENABLE_SATA3 :: SATA3_54_CLOCK_ENABLE_SATA3 [00:00] */
-#define BCHP_CLKGEN_SATA3_PCIE_TOP_INST_CLOCK_ENABLE_SATA3_SATA3_54_CLOCK_ENABLE_SATA3_MASK 0x00000001
-#define BCHP_CLKGEN_SATA3_PCIE_TOP_INST_CLOCK_ENABLE_SATA3_SATA3_54_CLOCK_ENABLE_SATA3_SHIFT 0
-#define BCHP_CLKGEN_SATA3_PCIE_TOP_INST_CLOCK_ENABLE_SATA3_SATA3_54_CLOCK_ENABLE_SATA3_DEFAULT 0x00000001
-
-/***************************************************************************
- *SATA3_PCIE_TOP_INST_CLOCK_ENABLE_SATA3_STATUS - Clock Enable Status
- ***************************************************************************/
-/* CLKGEN :: SATA3_PCIE_TOP_INST_CLOCK_ENABLE_SATA3_STATUS :: reserved0 [31:03] */
-#define BCHP_CLKGEN_SATA3_PCIE_TOP_INST_CLOCK_ENABLE_SATA3_STATUS_reserved0_MASK 0xfffffff8
-#define BCHP_CLKGEN_SATA3_PCIE_TOP_INST_CLOCK_ENABLE_SATA3_STATUS_reserved0_SHIFT 3
-
-/* CLKGEN :: SATA3_PCIE_TOP_INST_CLOCK_ENABLE_SATA3_STATUS :: SATA3_SCB_CLOCK_ENABLE_SATA3_STATUS [02:02] */
-#define BCHP_CLKGEN_SATA3_PCIE_TOP_INST_CLOCK_ENABLE_SATA3_STATUS_SATA3_SCB_CLOCK_ENABLE_SATA3_STATUS_MASK 0x00000004
-#define BCHP_CLKGEN_SATA3_PCIE_TOP_INST_CLOCK_ENABLE_SATA3_STATUS_SATA3_SCB_CLOCK_ENABLE_SATA3_STATUS_SHIFT 2
-
-/* CLKGEN :: SATA3_PCIE_TOP_INST_CLOCK_ENABLE_SATA3_STATUS :: SATA3_GISB_CLOCK_ENABLE_SATA3_STATUS [01:01] */
-#define BCHP_CLKGEN_SATA3_PCIE_TOP_INST_CLOCK_ENABLE_SATA3_STATUS_SATA3_GISB_CLOCK_ENABLE_SATA3_STATUS_MASK 0x00000002
-#define BCHP_CLKGEN_SATA3_PCIE_TOP_INST_CLOCK_ENABLE_SATA3_STATUS_SATA3_GISB_CLOCK_ENABLE_SATA3_STATUS_SHIFT 1
-
-/* CLKGEN :: SATA3_PCIE_TOP_INST_CLOCK_ENABLE_SATA3_STATUS :: SATA3_54_CLOCK_ENABLE_SATA3_STATUS [00:00] */
-#define BCHP_CLKGEN_SATA3_PCIE_TOP_INST_CLOCK_ENABLE_SATA3_STATUS_SATA3_54_CLOCK_ENABLE_SATA3_STATUS_MASK 0x00000001
-#define BCHP_CLKGEN_SATA3_PCIE_TOP_INST_CLOCK_ENABLE_SATA3_STATUS_SATA3_54_CLOCK_ENABLE_SATA3_STATUS_SHIFT 0
-
-/***************************************************************************
- *SATA3_PCIE_TOP_INST_CLOCK_SELECT - Sata3 pcie top inst clock select
- ***************************************************************************/
-/* CLKGEN :: SATA3_PCIE_TOP_INST_CLOCK_SELECT :: reserved0 [31:03] */
-#define BCHP_CLKGEN_SATA3_PCIE_TOP_INST_CLOCK_SELECT_reserved0_MASK 0xfffffff8
-#define BCHP_CLKGEN_SATA3_PCIE_TOP_INST_CLOCK_SELECT_reserved0_SHIFT 3
-
-/* CLKGEN :: SATA3_PCIE_TOP_INST_CLOCK_SELECT :: SATA3_REF_CLOCK_SELECT [02:00] */
-#define BCHP_CLKGEN_SATA3_PCIE_TOP_INST_CLOCK_SELECT_SATA3_REF_CLOCK_SELECT_MASK 0x00000007
-#define BCHP_CLKGEN_SATA3_PCIE_TOP_INST_CLOCK_SELECT_SATA3_REF_CLOCK_SELECT_SHIFT 0
-#define BCHP_CLKGEN_SATA3_PCIE_TOP_INST_CLOCK_SELECT_SATA3_REF_CLOCK_SELECT_DEFAULT 0x00000000
-
-/***************************************************************************
- *SATA3_PCIE_TOP_INST_OBSERVE_CLOCK - Sata3 pcie top inst observe clock
- ***************************************************************************/
-/* CLKGEN :: SATA3_PCIE_TOP_INST_OBSERVE_CLOCK :: reserved0 [31:12] */
-#define BCHP_CLKGEN_SATA3_PCIE_TOP_INST_OBSERVE_CLOCK_reserved0_MASK 0xfffff000
-#define BCHP_CLKGEN_SATA3_PCIE_TOP_INST_OBSERVE_CLOCK_reserved0_SHIFT 12
-
-/* CLKGEN :: SATA3_PCIE_TOP_INST_OBSERVE_CLOCK :: SATA3_ENABLE_OBSERVE_CLOCK [11:11] */
-#define BCHP_CLKGEN_SATA3_PCIE_TOP_INST_OBSERVE_CLOCK_SATA3_ENABLE_OBSERVE_CLOCK_MASK 0x00000800
-#define BCHP_CLKGEN_SATA3_PCIE_TOP_INST_OBSERVE_CLOCK_SATA3_ENABLE_OBSERVE_CLOCK_SHIFT 11
-#define BCHP_CLKGEN_SATA3_PCIE_TOP_INST_OBSERVE_CLOCK_SATA3_ENABLE_OBSERVE_CLOCK_DEFAULT 0x00000000
-
-/* CLKGEN :: SATA3_PCIE_TOP_INST_OBSERVE_CLOCK :: SATA3_ENABLE_DIVIDER_OBSERVE_CLOCK [10:10] */
-#define BCHP_CLKGEN_SATA3_PCIE_TOP_INST_OBSERVE_CLOCK_SATA3_ENABLE_DIVIDER_OBSERVE_CLOCK_MASK 0x00000400
-#define BCHP_CLKGEN_SATA3_PCIE_TOP_INST_OBSERVE_CLOCK_SATA3_ENABLE_DIVIDER_OBSERVE_CLOCK_SHIFT 10
-#define BCHP_CLKGEN_SATA3_PCIE_TOP_INST_OBSERVE_CLOCK_SATA3_ENABLE_DIVIDER_OBSERVE_CLOCK_DEFAULT 0x00000000
-
-/* CLKGEN :: SATA3_PCIE_TOP_INST_OBSERVE_CLOCK :: SATA3_CONTROL_OBSERVE_CLOCK [09:06] */
-#define BCHP_CLKGEN_SATA3_PCIE_TOP_INST_OBSERVE_CLOCK_SATA3_CONTROL_OBSERVE_CLOCK_MASK 0x000003c0
-#define BCHP_CLKGEN_SATA3_PCIE_TOP_INST_OBSERVE_CLOCK_SATA3_CONTROL_OBSERVE_CLOCK_SHIFT 6
-#define BCHP_CLKGEN_SATA3_PCIE_TOP_INST_OBSERVE_CLOCK_SATA3_CONTROL_OBSERVE_CLOCK_DEFAULT 0x00000000
-
-/* CLKGEN :: SATA3_PCIE_TOP_INST_OBSERVE_CLOCK :: PCIE1_ENABLE_OBSERVE_CLOCK [05:05] */
-#define BCHP_CLKGEN_SATA3_PCIE_TOP_INST_OBSERVE_CLOCK_PCIE1_ENABLE_OBSERVE_CLOCK_MASK 0x00000020
-#define BCHP_CLKGEN_SATA3_PCIE_TOP_INST_OBSERVE_CLOCK_PCIE1_ENABLE_OBSERVE_CLOCK_SHIFT 5
-#define BCHP_CLKGEN_SATA3_PCIE_TOP_INST_OBSERVE_CLOCK_PCIE1_ENABLE_OBSERVE_CLOCK_DEFAULT 0x00000000
-
-/* CLKGEN :: SATA3_PCIE_TOP_INST_OBSERVE_CLOCK :: PCIE1_ENABLE_DIVIDER_OBSERVE_CLOCK [04:04] */
-#define BCHP_CLKGEN_SATA3_PCIE_TOP_INST_OBSERVE_CLOCK_PCIE1_ENABLE_DIVIDER_OBSERVE_CLOCK_MASK 0x00000010
-#define BCHP_CLKGEN_SATA3_PCIE_TOP_INST_OBSERVE_CLOCK_PCIE1_ENABLE_DIVIDER_OBSERVE_CLOCK_SHIFT 4
-#define BCHP_CLKGEN_SATA3_PCIE_TOP_INST_OBSERVE_CLOCK_PCIE1_ENABLE_DIVIDER_OBSERVE_CLOCK_DEFAULT 0x00000000
-
-/* CLKGEN :: SATA3_PCIE_TOP_INST_OBSERVE_CLOCK :: PCIE1_CONTROL_OBSERVE_CLOCK [03:00] */
-#define BCHP_CLKGEN_SATA3_PCIE_TOP_INST_OBSERVE_CLOCK_PCIE1_CONTROL_OBSERVE_CLOCK_MASK 0x0000000f
-#define BCHP_CLKGEN_SATA3_PCIE_TOP_INST_OBSERVE_CLOCK_PCIE1_CONTROL_OBSERVE_CLOCK_SHIFT 0
-#define BCHP_CLKGEN_SATA3_PCIE_TOP_INST_OBSERVE_CLOCK_PCIE1_CONTROL_OBSERVE_CLOCK_DEFAULT 0x00000000
-
-/***************************************************************************
- *SCB_CHANNEL_2_INST_CKTAPSEL - Scb channel 2 inst cktapsel
- ***************************************************************************/
-/* CLKGEN :: SCB_CHANNEL_2_INST_CKTAPSEL :: reserved0 [31:12] */
-#define BCHP_CLKGEN_SCB_CHANNEL_2_INST_CKTAPSEL_reserved0_MASK 0xfffff000
-#define BCHP_CLKGEN_SCB_CHANNEL_2_INST_CKTAPSEL_reserved0_SHIFT 12
-
-/* CLKGEN :: SCB_CHANNEL_2_INST_CKTAPSEL :: SCB_CKTAP1_CKTAPSEL [11:06] */
-#define BCHP_CLKGEN_SCB_CHANNEL_2_INST_CKTAPSEL_SCB_CKTAP1_CKTAPSEL_MASK 0x00000fc0
-#define BCHP_CLKGEN_SCB_CHANNEL_2_INST_CKTAPSEL_SCB_CKTAP1_CKTAPSEL_SHIFT 6
-#define BCHP_CLKGEN_SCB_CHANNEL_2_INST_CKTAPSEL_SCB_CKTAP1_CKTAPSEL_DEFAULT 0x00000000
-
-/* CLKGEN :: SCB_CHANNEL_2_INST_CKTAPSEL :: SCB_CKTAP0_CKTAPSEL [05:00] */
-#define BCHP_CLKGEN_SCB_CHANNEL_2_INST_CKTAPSEL_SCB_CKTAP0_CKTAPSEL_MASK 0x0000003f
-#define BCHP_CLKGEN_SCB_CHANNEL_2_INST_CKTAPSEL_SCB_CKTAP0_CKTAPSEL_SHIFT 0
-#define BCHP_CLKGEN_SCB_CHANNEL_2_INST_CKTAPSEL_SCB_CKTAP0_CKTAPSEL_DEFAULT 0x00000000
-
-/***************************************************************************
- *SCB_CHANNEL_3_INST_CKTAPSEL - Scb channel 3 inst cktapsel
- ***************************************************************************/
-/* CLKGEN :: SCB_CHANNEL_3_INST_CKTAPSEL :: reserved0 [31:12] */
-#define BCHP_CLKGEN_SCB_CHANNEL_3_INST_CKTAPSEL_reserved0_MASK 0xfffff000
-#define BCHP_CLKGEN_SCB_CHANNEL_3_INST_CKTAPSEL_reserved0_SHIFT 12
-
-/* CLKGEN :: SCB_CHANNEL_3_INST_CKTAPSEL :: SCB_CKTAP1_CKTAPSEL [11:06] */
-#define BCHP_CLKGEN_SCB_CHANNEL_3_INST_CKTAPSEL_SCB_CKTAP1_CKTAPSEL_MASK 0x00000fc0
-#define BCHP_CLKGEN_SCB_CHANNEL_3_INST_CKTAPSEL_SCB_CKTAP1_CKTAPSEL_SHIFT 6
-#define BCHP_CLKGEN_SCB_CHANNEL_3_INST_CKTAPSEL_SCB_CKTAP1_CKTAPSEL_DEFAULT 0x00000000
-
-/* CLKGEN :: SCB_CHANNEL_3_INST_CKTAPSEL :: SCB_CKTAP0_CKTAPSEL [05:00] */
-#define BCHP_CLKGEN_SCB_CHANNEL_3_INST_CKTAPSEL_SCB_CKTAP0_CKTAPSEL_MASK 0x0000003f
-#define BCHP_CLKGEN_SCB_CHANNEL_3_INST_CKTAPSEL_SCB_CKTAP0_CKTAPSEL_SHIFT 0
-#define BCHP_CLKGEN_SCB_CHANNEL_3_INST_CKTAPSEL_SCB_CKTAP0_CKTAPSEL_DEFAULT 0x00000000
-
-/***************************************************************************
- *SCB_CHANNEL_4_INST_CKTAPSEL - Scb channel 4 inst cktapsel
- ***************************************************************************/
-/* CLKGEN :: SCB_CHANNEL_4_INST_CKTAPSEL :: reserved0 [31:12] */
-#define BCHP_CLKGEN_SCB_CHANNEL_4_INST_CKTAPSEL_reserved0_MASK 0xfffff000
-#define BCHP_CLKGEN_SCB_CHANNEL_4_INST_CKTAPSEL_reserved0_SHIFT 12
-
-/* CLKGEN :: SCB_CHANNEL_4_INST_CKTAPSEL :: SCB_CKTAP1_CKTAPSEL [11:06] */
-#define BCHP_CLKGEN_SCB_CHANNEL_4_INST_CKTAPSEL_SCB_CKTAP1_CKTAPSEL_MASK 0x00000fc0
-#define BCHP_CLKGEN_SCB_CHANNEL_4_INST_CKTAPSEL_SCB_CKTAP1_CKTAPSEL_SHIFT 6
-#define BCHP_CLKGEN_SCB_CHANNEL_4_INST_CKTAPSEL_SCB_CKTAP1_CKTAPSEL_DEFAULT 0x00000000
-
-/* CLKGEN :: SCB_CHANNEL_4_INST_CKTAPSEL :: SCB_CKTAP0_CKTAPSEL [05:00] */
-#define BCHP_CLKGEN_SCB_CHANNEL_4_INST_CKTAPSEL_SCB_CKTAP0_CKTAPSEL_MASK 0x0000003f
-#define BCHP_CLKGEN_SCB_CHANNEL_4_INST_CKTAPSEL_SCB_CKTAP0_CKTAPSEL_SHIFT 0
-#define BCHP_CLKGEN_SCB_CHANNEL_4_INST_CKTAPSEL_SCB_CKTAP0_CKTAPSEL_DEFAULT 0x00000000
-
-/***************************************************************************
- *SCB_CHANNEL_INST_CKTAPSEL - Scb channel inst cktapsel
- ***************************************************************************/
-/* CLKGEN :: SCB_CHANNEL_INST_CKTAPSEL :: reserved0 [31:12] */
-#define BCHP_CLKGEN_SCB_CHANNEL_INST_CKTAPSEL_reserved0_MASK 0xfffff000
-#define BCHP_CLKGEN_SCB_CHANNEL_INST_CKTAPSEL_reserved0_SHIFT 12
-
-/* CLKGEN :: SCB_CHANNEL_INST_CKTAPSEL :: SCB_CKTAP1_CKTAPSEL [11:06] */
-#define BCHP_CLKGEN_SCB_CHANNEL_INST_CKTAPSEL_SCB_CKTAP1_CKTAPSEL_MASK 0x00000fc0
-#define BCHP_CLKGEN_SCB_CHANNEL_INST_CKTAPSEL_SCB_CKTAP1_CKTAPSEL_SHIFT 6
-#define BCHP_CLKGEN_SCB_CHANNEL_INST_CKTAPSEL_SCB_CKTAP1_CKTAPSEL_DEFAULT 0x00000000
-
-/* CLKGEN :: SCB_CHANNEL_INST_CKTAPSEL :: SCB_CKTAP0_CKTAPSEL [05:00] */
-#define BCHP_CLKGEN_SCB_CHANNEL_INST_CKTAPSEL_SCB_CKTAP0_CKTAPSEL_MASK 0x0000003f
-#define BCHP_CLKGEN_SCB_CHANNEL_INST_CKTAPSEL_SCB_CKTAP0_CKTAPSEL_SHIFT 0
-#define BCHP_CLKGEN_SCB_CHANNEL_INST_CKTAPSEL_SCB_CKTAP0_CKTAPSEL_DEFAULT 0x00000000
-
-/***************************************************************************
- *SDS_AFEC2X_TOP_0_INST_CLOCK_ENABLE - Sds afec2x top 0 inst clock enable
- ***************************************************************************/
-/* CLKGEN :: SDS_AFEC2X_TOP_0_INST_CLOCK_ENABLE :: reserved0 [31:03] */
-#define BCHP_CLKGEN_SDS_AFEC2X_TOP_0_INST_CLOCK_ENABLE_reserved0_MASK 0xfffffff8
-#define BCHP_CLKGEN_SDS_AFEC2X_TOP_0_INST_CLOCK_ENABLE_reserved0_SHIFT 3
-
-/* CLKGEN :: SDS_AFEC2X_TOP_0_INST_CLOCK_ENABLE :: AFEC0_FUNC_CLOCK_ENABLE [02:02] */
-#define BCHP_CLKGEN_SDS_AFEC2X_TOP_0_INST_CLOCK_ENABLE_AFEC0_FUNC_CLOCK_ENABLE_MASK 0x00000004
-#define BCHP_CLKGEN_SDS_AFEC2X_TOP_0_INST_CLOCK_ENABLE_AFEC0_FUNC_CLOCK_ENABLE_SHIFT 2
-#define BCHP_CLKGEN_SDS_AFEC2X_TOP_0_INST_CLOCK_ENABLE_AFEC0_FUNC_CLOCK_ENABLE_DEFAULT 0x00000001
-
-/* CLKGEN :: SDS_AFEC2X_TOP_0_INST_CLOCK_ENABLE :: AFEC0_54_CLOCK_ENABLE [01:01] */
-#define BCHP_CLKGEN_SDS_AFEC2X_TOP_0_INST_CLOCK_ENABLE_AFEC0_54_CLOCK_ENABLE_MASK 0x00000002
-#define BCHP_CLKGEN_SDS_AFEC2X_TOP_0_INST_CLOCK_ENABLE_AFEC0_54_CLOCK_ENABLE_SHIFT 1
-#define BCHP_CLKGEN_SDS_AFEC2X_TOP_0_INST_CLOCK_ENABLE_AFEC0_54_CLOCK_ENABLE_DEFAULT 0x00000001
-
-/* CLKGEN :: SDS_AFEC2X_TOP_0_INST_CLOCK_ENABLE :: AFEC0_108_CLOCK_ENABLE [00:00] */
-#define BCHP_CLKGEN_SDS_AFEC2X_TOP_0_INST_CLOCK_ENABLE_AFEC0_108_CLOCK_ENABLE_MASK 0x00000001
-#define BCHP_CLKGEN_SDS_AFEC2X_TOP_0_INST_CLOCK_ENABLE_AFEC0_108_CLOCK_ENABLE_SHIFT 0
-#define BCHP_CLKGEN_SDS_AFEC2X_TOP_0_INST_CLOCK_ENABLE_AFEC0_108_CLOCK_ENABLE_DEFAULT 0x00000001
-
-/***************************************************************************
- *SDS_AFEC2X_TOP_0_INST_CLOCK_ENABLE_STATUS - Clock Enable Status
- ***************************************************************************/
-/* CLKGEN :: SDS_AFEC2X_TOP_0_INST_CLOCK_ENABLE_STATUS :: reserved0 [31:03] */
-#define BCHP_CLKGEN_SDS_AFEC2X_TOP_0_INST_CLOCK_ENABLE_STATUS_reserved0_MASK 0xfffffff8
-#define BCHP_CLKGEN_SDS_AFEC2X_TOP_0_INST_CLOCK_ENABLE_STATUS_reserved0_SHIFT 3
-
-/* CLKGEN :: SDS_AFEC2X_TOP_0_INST_CLOCK_ENABLE_STATUS :: AFEC0_FUNC_CLOCK_ENABLE_STATUS [02:02] */
-#define BCHP_CLKGEN_SDS_AFEC2X_TOP_0_INST_CLOCK_ENABLE_STATUS_AFEC0_FUNC_CLOCK_ENABLE_STATUS_MASK 0x00000004
-#define BCHP_CLKGEN_SDS_AFEC2X_TOP_0_INST_CLOCK_ENABLE_STATUS_AFEC0_FUNC_CLOCK_ENABLE_STATUS_SHIFT 2
-
-/* CLKGEN :: SDS_AFEC2X_TOP_0_INST_CLOCK_ENABLE_STATUS :: AFEC0_54_CLOCK_ENABLE_STATUS [01:01] */
-#define BCHP_CLKGEN_SDS_AFEC2X_TOP_0_INST_CLOCK_ENABLE_STATUS_AFEC0_54_CLOCK_ENABLE_STATUS_MASK 0x00000002
-#define BCHP_CLKGEN_SDS_AFEC2X_TOP_0_INST_CLOCK_ENABLE_STATUS_AFEC0_54_CLOCK_ENABLE_STATUS_SHIFT 1
-
-/* CLKGEN :: SDS_AFEC2X_TOP_0_INST_CLOCK_ENABLE_STATUS :: AFEC0_108_CLOCK_ENABLE_STATUS [00:00] */
-#define BCHP_CLKGEN_SDS_AFEC2X_TOP_0_INST_CLOCK_ENABLE_STATUS_AFEC0_108_CLOCK_ENABLE_STATUS_MASK 0x00000001
-#define BCHP_CLKGEN_SDS_AFEC2X_TOP_0_INST_CLOCK_ENABLE_STATUS_AFEC0_108_CLOCK_ENABLE_STATUS_SHIFT 0
-
-/***************************************************************************
- *SDS_AFEC2X_TOP_0_INST_OBSERVE_CLOCK - Sds afec2x top 0 inst observe clock
- ***************************************************************************/
-/* CLKGEN :: SDS_AFEC2X_TOP_0_INST_OBSERVE_CLOCK :: reserved0 [31:06] */
-#define BCHP_CLKGEN_SDS_AFEC2X_TOP_0_INST_OBSERVE_CLOCK_reserved0_MASK 0xffffffc0
-#define BCHP_CLKGEN_SDS_AFEC2X_TOP_0_INST_OBSERVE_CLOCK_reserved0_SHIFT 6
-
-/* CLKGEN :: SDS_AFEC2X_TOP_0_INST_OBSERVE_CLOCK :: AFEC0_ENABLE_OBSERVE_CLOCK [05:05] */
-#define BCHP_CLKGEN_SDS_AFEC2X_TOP_0_INST_OBSERVE_CLOCK_AFEC0_ENABLE_OBSERVE_CLOCK_MASK 0x00000020
-#define BCHP_CLKGEN_SDS_AFEC2X_TOP_0_INST_OBSERVE_CLOCK_AFEC0_ENABLE_OBSERVE_CLOCK_SHIFT 5
-#define BCHP_CLKGEN_SDS_AFEC2X_TOP_0_INST_OBSERVE_CLOCK_AFEC0_ENABLE_OBSERVE_CLOCK_DEFAULT 0x00000000
-
-/* CLKGEN :: SDS_AFEC2X_TOP_0_INST_OBSERVE_CLOCK :: AFEC0_ENABLE_DIVIDER_OBSERVE_CLOCK [04:04] */
-#define BCHP_CLKGEN_SDS_AFEC2X_TOP_0_INST_OBSERVE_CLOCK_AFEC0_ENABLE_DIVIDER_OBSERVE_CLOCK_MASK 0x00000010
-#define BCHP_CLKGEN_SDS_AFEC2X_TOP_0_INST_OBSERVE_CLOCK_AFEC0_ENABLE_DIVIDER_OBSERVE_CLOCK_SHIFT 4
-#define BCHP_CLKGEN_SDS_AFEC2X_TOP_0_INST_OBSERVE_CLOCK_AFEC0_ENABLE_DIVIDER_OBSERVE_CLOCK_DEFAULT 0x00000000
-
-/* CLKGEN :: SDS_AFEC2X_TOP_0_INST_OBSERVE_CLOCK :: AFEC0TFEC0_CONTROL_OBSERVE_CLOCK [03:00] */
-#define BCHP_CLKGEN_SDS_AFEC2X_TOP_0_INST_OBSERVE_CLOCK_AFEC0TFEC0_CONTROL_OBSERVE_CLOCK_MASK 0x0000000f
-#define BCHP_CLKGEN_SDS_AFEC2X_TOP_0_INST_OBSERVE_CLOCK_AFEC0TFEC0_CONTROL_OBSERVE_CLOCK_SHIFT 0
-#define BCHP_CLKGEN_SDS_AFEC2X_TOP_0_INST_OBSERVE_CLOCK_AFEC0TFEC0_CONTROL_OBSERVE_CLOCK_DEFAULT 0x00000000
-
-/***************************************************************************
- *SDS_AFEC2X_TOP_0_INST_SEL - Sds afec2x top 0 inst sel
- ***************************************************************************/
-/* CLKGEN :: SDS_AFEC2X_TOP_0_INST_SEL :: reserved0 [31:01] */
-#define BCHP_CLKGEN_SDS_AFEC2X_TOP_0_INST_SEL_reserved0_MASK 0xfffffffe
-#define BCHP_CLKGEN_SDS_AFEC2X_TOP_0_INST_SEL_reserved0_SHIFT 1
-
-/* CLKGEN :: SDS_AFEC2X_TOP_0_INST_SEL :: AFEC0_LV_CLK_PLL_SRC_SEL [00:00] */
-#define BCHP_CLKGEN_SDS_AFEC2X_TOP_0_INST_SEL_AFEC0_LV_CLK_PLL_SRC_SEL_MASK 0x00000001
-#define BCHP_CLKGEN_SDS_AFEC2X_TOP_0_INST_SEL_AFEC0_LV_CLK_PLL_SRC_SEL_SHIFT 0
-#define BCHP_CLKGEN_SDS_AFEC2X_TOP_0_INST_SEL_AFEC0_LV_CLK_PLL_SRC_SEL_DEFAULT 0x00000000
-
-/***************************************************************************
- *SDS_AFEC2X_TOP_1_INST_CLOCK_ENABLE - Sds afec2x top 1 inst clock enable
- ***************************************************************************/
-/* CLKGEN :: SDS_AFEC2X_TOP_1_INST_CLOCK_ENABLE :: reserved0 [31:03] */
-#define BCHP_CLKGEN_SDS_AFEC2X_TOP_1_INST_CLOCK_ENABLE_reserved0_MASK 0xfffffff8
-#define BCHP_CLKGEN_SDS_AFEC2X_TOP_1_INST_CLOCK_ENABLE_reserved0_SHIFT 3
-
-/* CLKGEN :: SDS_AFEC2X_TOP_1_INST_CLOCK_ENABLE :: AFEC1_FUNC_CLOCK_ENABLE [02:02] */
-#define BCHP_CLKGEN_SDS_AFEC2X_TOP_1_INST_CLOCK_ENABLE_AFEC1_FUNC_CLOCK_ENABLE_MASK 0x00000004
-#define BCHP_CLKGEN_SDS_AFEC2X_TOP_1_INST_CLOCK_ENABLE_AFEC1_FUNC_CLOCK_ENABLE_SHIFT 2
-#define BCHP_CLKGEN_SDS_AFEC2X_TOP_1_INST_CLOCK_ENABLE_AFEC1_FUNC_CLOCK_ENABLE_DEFAULT 0x00000001
-
-/* CLKGEN :: SDS_AFEC2X_TOP_1_INST_CLOCK_ENABLE :: AFEC1_54_CLOCK_ENABLE [01:01] */
-#define BCHP_CLKGEN_SDS_AFEC2X_TOP_1_INST_CLOCK_ENABLE_AFEC1_54_CLOCK_ENABLE_MASK 0x00000002
-#define BCHP_CLKGEN_SDS_AFEC2X_TOP_1_INST_CLOCK_ENABLE_AFEC1_54_CLOCK_ENABLE_SHIFT 1
-#define BCHP_CLKGEN_SDS_AFEC2X_TOP_1_INST_CLOCK_ENABLE_AFEC1_54_CLOCK_ENABLE_DEFAULT 0x00000001
-
-/* CLKGEN :: SDS_AFEC2X_TOP_1_INST_CLOCK_ENABLE :: AFEC1_108_CLOCK_ENABLE [00:00] */
-#define BCHP_CLKGEN_SDS_AFEC2X_TOP_1_INST_CLOCK_ENABLE_AFEC1_108_CLOCK_ENABLE_MASK 0x00000001
-#define BCHP_CLKGEN_SDS_AFEC2X_TOP_1_INST_CLOCK_ENABLE_AFEC1_108_CLOCK_ENABLE_SHIFT 0
-#define BCHP_CLKGEN_SDS_AFEC2X_TOP_1_INST_CLOCK_ENABLE_AFEC1_108_CLOCK_ENABLE_DEFAULT 0x00000001
-
-/***************************************************************************
- *SDS_AFEC2X_TOP_1_INST_CLOCK_ENABLE_STATUS - Clock Enable Status
- ***************************************************************************/
-/* CLKGEN :: SDS_AFEC2X_TOP_1_INST_CLOCK_ENABLE_STATUS :: reserved0 [31:03] */
-#define BCHP_CLKGEN_SDS_AFEC2X_TOP_1_INST_CLOCK_ENABLE_STATUS_reserved0_MASK 0xfffffff8
-#define BCHP_CLKGEN_SDS_AFEC2X_TOP_1_INST_CLOCK_ENABLE_STATUS_reserved0_SHIFT 3
-
-/* CLKGEN :: SDS_AFEC2X_TOP_1_INST_CLOCK_ENABLE_STATUS :: AFEC1_FUNC_CLOCK_ENABLE_STATUS [02:02] */
-#define BCHP_CLKGEN_SDS_AFEC2X_TOP_1_INST_CLOCK_ENABLE_STATUS_AFEC1_FUNC_CLOCK_ENABLE_STATUS_MASK 0x00000004
-#define BCHP_CLKGEN_SDS_AFEC2X_TOP_1_INST_CLOCK_ENABLE_STATUS_AFEC1_FUNC_CLOCK_ENABLE_STATUS_SHIFT 2
-
-/* CLKGEN :: SDS_AFEC2X_TOP_1_INST_CLOCK_ENABLE_STATUS :: AFEC1_54_CLOCK_ENABLE_STATUS [01:01] */
-#define BCHP_CLKGEN_SDS_AFEC2X_TOP_1_INST_CLOCK_ENABLE_STATUS_AFEC1_54_CLOCK_ENABLE_STATUS_MASK 0x00000002
-#define BCHP_CLKGEN_SDS_AFEC2X_TOP_1_INST_CLOCK_ENABLE_STATUS_AFEC1_54_CLOCK_ENABLE_STATUS_SHIFT 1
-
-/* CLKGEN :: SDS_AFEC2X_TOP_1_INST_CLOCK_ENABLE_STATUS :: AFEC1_108_CLOCK_ENABLE_STATUS [00:00] */
-#define BCHP_CLKGEN_SDS_AFEC2X_TOP_1_INST_CLOCK_ENABLE_STATUS_AFEC1_108_CLOCK_ENABLE_STATUS_MASK 0x00000001
-#define BCHP_CLKGEN_SDS_AFEC2X_TOP_1_INST_CLOCK_ENABLE_STATUS_AFEC1_108_CLOCK_ENABLE_STATUS_SHIFT 0
-
-/***************************************************************************
- *SDS_AFEC2X_TOP_1_INST_OBSERVE_CLOCK - Sds afec2x top 1 inst observe clock
- ***************************************************************************/
-/* CLKGEN :: SDS_AFEC2X_TOP_1_INST_OBSERVE_CLOCK :: reserved0 [31:06] */
-#define BCHP_CLKGEN_SDS_AFEC2X_TOP_1_INST_OBSERVE_CLOCK_reserved0_MASK 0xffffffc0
-#define BCHP_CLKGEN_SDS_AFEC2X_TOP_1_INST_OBSERVE_CLOCK_reserved0_SHIFT 6
-
-/* CLKGEN :: SDS_AFEC2X_TOP_1_INST_OBSERVE_CLOCK :: AFEC1_ENABLE_OBSERVE_CLOCK [05:05] */
-#define BCHP_CLKGEN_SDS_AFEC2X_TOP_1_INST_OBSERVE_CLOCK_AFEC1_ENABLE_OBSERVE_CLOCK_MASK 0x00000020
-#define BCHP_CLKGEN_SDS_AFEC2X_TOP_1_INST_OBSERVE_CLOCK_AFEC1_ENABLE_OBSERVE_CLOCK_SHIFT 5
-#define BCHP_CLKGEN_SDS_AFEC2X_TOP_1_INST_OBSERVE_CLOCK_AFEC1_ENABLE_OBSERVE_CLOCK_DEFAULT 0x00000000
-
-/* CLKGEN :: SDS_AFEC2X_TOP_1_INST_OBSERVE_CLOCK :: AFEC1_ENABLE_DIVIDER_OBSERVE_CLOCK [04:04] */
-#define BCHP_CLKGEN_SDS_AFEC2X_TOP_1_INST_OBSERVE_CLOCK_AFEC1_ENABLE_DIVIDER_OBSERVE_CLOCK_MASK 0x00000010
-#define BCHP_CLKGEN_SDS_AFEC2X_TOP_1_INST_OBSERVE_CLOCK_AFEC1_ENABLE_DIVIDER_OBSERVE_CLOCK_SHIFT 4
-#define BCHP_CLKGEN_SDS_AFEC2X_TOP_1_INST_OBSERVE_CLOCK_AFEC1_ENABLE_DIVIDER_OBSERVE_CLOCK_DEFAULT 0x00000000
-
-/* CLKGEN :: SDS_AFEC2X_TOP_1_INST_OBSERVE_CLOCK :: AFEC1TFEC0_CONTROL_OBSERVE_CLOCK [03:00] */
-#define BCHP_CLKGEN_SDS_AFEC2X_TOP_1_INST_OBSERVE_CLOCK_AFEC1TFEC0_CONTROL_OBSERVE_CLOCK_MASK 0x0000000f
-#define BCHP_CLKGEN_SDS_AFEC2X_TOP_1_INST_OBSERVE_CLOCK_AFEC1TFEC0_CONTROL_OBSERVE_CLOCK_SHIFT 0
-#define BCHP_CLKGEN_SDS_AFEC2X_TOP_1_INST_OBSERVE_CLOCK_AFEC1TFEC0_CONTROL_OBSERVE_CLOCK_DEFAULT 0x00000000
-
-/***************************************************************************
- *SDS_AFEC2X_TOP_1_INST_SEL - Sds afec2x top 1 inst sel
- ***************************************************************************/
-/* CLKGEN :: SDS_AFEC2X_TOP_1_INST_SEL :: reserved0 [31:01] */
-#define BCHP_CLKGEN_SDS_AFEC2X_TOP_1_INST_SEL_reserved0_MASK 0xfffffffe
-#define BCHP_CLKGEN_SDS_AFEC2X_TOP_1_INST_SEL_reserved0_SHIFT 1
-
-/* CLKGEN :: SDS_AFEC2X_TOP_1_INST_SEL :: AFEC1_LV_CLK_PLL_SRC_SEL [00:00] */
-#define BCHP_CLKGEN_SDS_AFEC2X_TOP_1_INST_SEL_AFEC1_LV_CLK_PLL_SRC_SEL_MASK 0x00000001
-#define BCHP_CLKGEN_SDS_AFEC2X_TOP_1_INST_SEL_AFEC1_LV_CLK_PLL_SRC_SEL_SHIFT 0
-#define BCHP_CLKGEN_SDS_AFEC2X_TOP_1_INST_SEL_AFEC1_LV_CLK_PLL_SRC_SEL_DEFAULT 0x00000000
-
-/***************************************************************************
- *SDS_AFEC2X_TOP_2_INST_CLOCK_ENABLE - Sds afec2x top 2 inst clock enable
- ***************************************************************************/
-/* CLKGEN :: SDS_AFEC2X_TOP_2_INST_CLOCK_ENABLE :: reserved0 [31:03] */
-#define BCHP_CLKGEN_SDS_AFEC2X_TOP_2_INST_CLOCK_ENABLE_reserved0_MASK 0xfffffff8
-#define BCHP_CLKGEN_SDS_AFEC2X_TOP_2_INST_CLOCK_ENABLE_reserved0_SHIFT 3
-
-/* CLKGEN :: SDS_AFEC2X_TOP_2_INST_CLOCK_ENABLE :: AFEC2_FUNC_CLOCK_ENABLE [02:02] */
-#define BCHP_CLKGEN_SDS_AFEC2X_TOP_2_INST_CLOCK_ENABLE_AFEC2_FUNC_CLOCK_ENABLE_MASK 0x00000004
-#define BCHP_CLKGEN_SDS_AFEC2X_TOP_2_INST_CLOCK_ENABLE_AFEC2_FUNC_CLOCK_ENABLE_SHIFT 2
-#define BCHP_CLKGEN_SDS_AFEC2X_TOP_2_INST_CLOCK_ENABLE_AFEC2_FUNC_CLOCK_ENABLE_DEFAULT 0x00000001
-
-/* CLKGEN :: SDS_AFEC2X_TOP_2_INST_CLOCK_ENABLE :: AFEC2_54_CLOCK_ENABLE [01:01] */
-#define BCHP_CLKGEN_SDS_AFEC2X_TOP_2_INST_CLOCK_ENABLE_AFEC2_54_CLOCK_ENABLE_MASK 0x00000002
-#define BCHP_CLKGEN_SDS_AFEC2X_TOP_2_INST_CLOCK_ENABLE_AFEC2_54_CLOCK_ENABLE_SHIFT 1
-#define BCHP_CLKGEN_SDS_AFEC2X_TOP_2_INST_CLOCK_ENABLE_AFEC2_54_CLOCK_ENABLE_DEFAULT 0x00000001
-
-/* CLKGEN :: SDS_AFEC2X_TOP_2_INST_CLOCK_ENABLE :: AFEC2_108_CLOCK_ENABLE [00:00] */
-#define BCHP_CLKGEN_SDS_AFEC2X_TOP_2_INST_CLOCK_ENABLE_AFEC2_108_CLOCK_ENABLE_MASK 0x00000001
-#define BCHP_CLKGEN_SDS_AFEC2X_TOP_2_INST_CLOCK_ENABLE_AFEC2_108_CLOCK_ENABLE_SHIFT 0
-#define BCHP_CLKGEN_SDS_AFEC2X_TOP_2_INST_CLOCK_ENABLE_AFEC2_108_CLOCK_ENABLE_DEFAULT 0x00000001
-
-/***************************************************************************
- *SDS_AFEC2X_TOP_2_INST_CLOCK_ENABLE_STATUS - Clock Enable Status
- ***************************************************************************/
-/* CLKGEN :: SDS_AFEC2X_TOP_2_INST_CLOCK_ENABLE_STATUS :: reserved0 [31:03] */
-#define BCHP_CLKGEN_SDS_AFEC2X_TOP_2_INST_CLOCK_ENABLE_STATUS_reserved0_MASK 0xfffffff8
-#define BCHP_CLKGEN_SDS_AFEC2X_TOP_2_INST_CLOCK_ENABLE_STATUS_reserved0_SHIFT 3
-
-/* CLKGEN :: SDS_AFEC2X_TOP_2_INST_CLOCK_ENABLE_STATUS :: AFEC2_FUNC_CLOCK_ENABLE_STATUS [02:02] */
-#define BCHP_CLKGEN_SDS_AFEC2X_TOP_2_INST_CLOCK_ENABLE_STATUS_AFEC2_FUNC_CLOCK_ENABLE_STATUS_MASK 0x00000004
-#define BCHP_CLKGEN_SDS_AFEC2X_TOP_2_INST_CLOCK_ENABLE_STATUS_AFEC2_FUNC_CLOCK_ENABLE_STATUS_SHIFT 2
-
-/* CLKGEN :: SDS_AFEC2X_TOP_2_INST_CLOCK_ENABLE_STATUS :: AFEC2_54_CLOCK_ENABLE_STATUS [01:01] */
-#define BCHP_CLKGEN_SDS_AFEC2X_TOP_2_INST_CLOCK_ENABLE_STATUS_AFEC2_54_CLOCK_ENABLE_STATUS_MASK 0x00000002
-#define BCHP_CLKGEN_SDS_AFEC2X_TOP_2_INST_CLOCK_ENABLE_STATUS_AFEC2_54_CLOCK_ENABLE_STATUS_SHIFT 1
-
-/* CLKGEN :: SDS_AFEC2X_TOP_2_INST_CLOCK_ENABLE_STATUS :: AFEC2_108_CLOCK_ENABLE_STATUS [00:00] */
-#define BCHP_CLKGEN_SDS_AFEC2X_TOP_2_INST_CLOCK_ENABLE_STATUS_AFEC2_108_CLOCK_ENABLE_STATUS_MASK 0x00000001
-#define BCHP_CLKGEN_SDS_AFEC2X_TOP_2_INST_CLOCK_ENABLE_STATUS_AFEC2_108_CLOCK_ENABLE_STATUS_SHIFT 0
-
-/***************************************************************************
- *SDS_AFEC2X_TOP_2_INST_OBSERVE_CLOCK - Sds afec2x top 2 inst observe clock
- ***************************************************************************/
-/* CLKGEN :: SDS_AFEC2X_TOP_2_INST_OBSERVE_CLOCK :: reserved0 [31:06] */
-#define BCHP_CLKGEN_SDS_AFEC2X_TOP_2_INST_OBSERVE_CLOCK_reserved0_MASK 0xffffffc0
-#define BCHP_CLKGEN_SDS_AFEC2X_TOP_2_INST_OBSERVE_CLOCK_reserved0_SHIFT 6
-
-/* CLKGEN :: SDS_AFEC2X_TOP_2_INST_OBSERVE_CLOCK :: AFEC2_ENABLE_OBSERVE_CLOCK [05:05] */
-#define BCHP_CLKGEN_SDS_AFEC2X_TOP_2_INST_OBSERVE_CLOCK_AFEC2_ENABLE_OBSERVE_CLOCK_MASK 0x00000020
-#define BCHP_CLKGEN_SDS_AFEC2X_TOP_2_INST_OBSERVE_CLOCK_AFEC2_ENABLE_OBSERVE_CLOCK_SHIFT 5
-#define BCHP_CLKGEN_SDS_AFEC2X_TOP_2_INST_OBSERVE_CLOCK_AFEC2_ENABLE_OBSERVE_CLOCK_DEFAULT 0x00000000
-
-/* CLKGEN :: SDS_AFEC2X_TOP_2_INST_OBSERVE_CLOCK :: AFEC2_ENABLE_DIVIDER_OBSERVE_CLOCK [04:04] */
-#define BCHP_CLKGEN_SDS_AFEC2X_TOP_2_INST_OBSERVE_CLOCK_AFEC2_ENABLE_DIVIDER_OBSERVE_CLOCK_MASK 0x00000010
-#define BCHP_CLKGEN_SDS_AFEC2X_TOP_2_INST_OBSERVE_CLOCK_AFEC2_ENABLE_DIVIDER_OBSERVE_CLOCK_SHIFT 4
-#define BCHP_CLKGEN_SDS_AFEC2X_TOP_2_INST_OBSERVE_CLOCK_AFEC2_ENABLE_DIVIDER_OBSERVE_CLOCK_DEFAULT 0x00000000
-
-/* CLKGEN :: SDS_AFEC2X_TOP_2_INST_OBSERVE_CLOCK :: AFEC2_CONTROL_OBSERVE_CLOCK [03:00] */
-#define BCHP_CLKGEN_SDS_AFEC2X_TOP_2_INST_OBSERVE_CLOCK_AFEC2_CONTROL_OBSERVE_CLOCK_MASK 0x0000000f
-#define BCHP_CLKGEN_SDS_AFEC2X_TOP_2_INST_OBSERVE_CLOCK_AFEC2_CONTROL_OBSERVE_CLOCK_SHIFT 0
-#define BCHP_CLKGEN_SDS_AFEC2X_TOP_2_INST_OBSERVE_CLOCK_AFEC2_CONTROL_OBSERVE_CLOCK_DEFAULT 0x00000000
-
-/***************************************************************************
- *SDS_AFEC2X_TOP_2_INST_SEL - Sds afec2x top 2 inst sel
- ***************************************************************************/
-/* CLKGEN :: SDS_AFEC2X_TOP_2_INST_SEL :: reserved0 [31:01] */
-#define BCHP_CLKGEN_SDS_AFEC2X_TOP_2_INST_SEL_reserved0_MASK 0xfffffffe
-#define BCHP_CLKGEN_SDS_AFEC2X_TOP_2_INST_SEL_reserved0_SHIFT 1
-
-/* CLKGEN :: SDS_AFEC2X_TOP_2_INST_SEL :: AFEC2_LV_CLK_PLL_SRC_SEL [00:00] */
-#define BCHP_CLKGEN_SDS_AFEC2X_TOP_2_INST_SEL_AFEC2_LV_CLK_PLL_SRC_SEL_MASK 0x00000001
-#define BCHP_CLKGEN_SDS_AFEC2X_TOP_2_INST_SEL_AFEC2_LV_CLK_PLL_SRC_SEL_SHIFT 0
-#define BCHP_CLKGEN_SDS_AFEC2X_TOP_2_INST_SEL_AFEC2_LV_CLK_PLL_SRC_SEL_DEFAULT 0x00000000
-
-/***************************************************************************
- *SDS_AFEC2X_TOP_3_INST_CLOCK_ENABLE - Sds afec2x top 3 inst clock enable
- ***************************************************************************/
-/* CLKGEN :: SDS_AFEC2X_TOP_3_INST_CLOCK_ENABLE :: reserved0 [31:03] */
-#define BCHP_CLKGEN_SDS_AFEC2X_TOP_3_INST_CLOCK_ENABLE_reserved0_MASK 0xfffffff8
-#define BCHP_CLKGEN_SDS_AFEC2X_TOP_3_INST_CLOCK_ENABLE_reserved0_SHIFT 3
-
-/* CLKGEN :: SDS_AFEC2X_TOP_3_INST_CLOCK_ENABLE :: AFEC3_FUNC_CLOCK_ENABLE [02:02] */
-#define BCHP_CLKGEN_SDS_AFEC2X_TOP_3_INST_CLOCK_ENABLE_AFEC3_FUNC_CLOCK_ENABLE_MASK 0x00000004
-#define BCHP_CLKGEN_SDS_AFEC2X_TOP_3_INST_CLOCK_ENABLE_AFEC3_FUNC_CLOCK_ENABLE_SHIFT 2
-#define BCHP_CLKGEN_SDS_AFEC2X_TOP_3_INST_CLOCK_ENABLE_AFEC3_FUNC_CLOCK_ENABLE_DEFAULT 0x00000001
-
-/* CLKGEN :: SDS_AFEC2X_TOP_3_INST_CLOCK_ENABLE :: AFEC3_54_CLOCK_ENABLE [01:01] */
-#define BCHP_CLKGEN_SDS_AFEC2X_TOP_3_INST_CLOCK_ENABLE_AFEC3_54_CLOCK_ENABLE_MASK 0x00000002
-#define BCHP_CLKGEN_SDS_AFEC2X_TOP_3_INST_CLOCK_ENABLE_AFEC3_54_CLOCK_ENABLE_SHIFT 1
-#define BCHP_CLKGEN_SDS_AFEC2X_TOP_3_INST_CLOCK_ENABLE_AFEC3_54_CLOCK_ENABLE_DEFAULT 0x00000001
-
-/* CLKGEN :: SDS_AFEC2X_TOP_3_INST_CLOCK_ENABLE :: AFEC3_108_CLOCK_ENABLE [00:00] */
-#define BCHP_CLKGEN_SDS_AFEC2X_TOP_3_INST_CLOCK_ENABLE_AFEC3_108_CLOCK_ENABLE_MASK 0x00000001
-#define BCHP_CLKGEN_SDS_AFEC2X_TOP_3_INST_CLOCK_ENABLE_AFEC3_108_CLOCK_ENABLE_SHIFT 0
-#define BCHP_CLKGEN_SDS_AFEC2X_TOP_3_INST_CLOCK_ENABLE_AFEC3_108_CLOCK_ENABLE_DEFAULT 0x00000001
-
-/***************************************************************************
- *SDS_AFEC2X_TOP_3_INST_CLOCK_ENABLE_STATUS - Clock Enable Status
- ***************************************************************************/
-/* CLKGEN :: SDS_AFEC2X_TOP_3_INST_CLOCK_ENABLE_STATUS :: reserved0 [31:03] */
-#define BCHP_CLKGEN_SDS_AFEC2X_TOP_3_INST_CLOCK_ENABLE_STATUS_reserved0_MASK 0xfffffff8
-#define BCHP_CLKGEN_SDS_AFEC2X_TOP_3_INST_CLOCK_ENABLE_STATUS_reserved0_SHIFT 3
-
-/* CLKGEN :: SDS_AFEC2X_TOP_3_INST_CLOCK_ENABLE_STATUS :: AFEC3_FUNC_CLOCK_ENABLE_STATUS [02:02] */
-#define BCHP_CLKGEN_SDS_AFEC2X_TOP_3_INST_CLOCK_ENABLE_STATUS_AFEC3_FUNC_CLOCK_ENABLE_STATUS_MASK 0x00000004
-#define BCHP_CLKGEN_SDS_AFEC2X_TOP_3_INST_CLOCK_ENABLE_STATUS_AFEC3_FUNC_CLOCK_ENABLE_STATUS_SHIFT 2
-
-/* CLKGEN :: SDS_AFEC2X_TOP_3_INST_CLOCK_ENABLE_STATUS :: AFEC3_54_CLOCK_ENABLE_STATUS [01:01] */
-#define BCHP_CLKGEN_SDS_AFEC2X_TOP_3_INST_CLOCK_ENABLE_STATUS_AFEC3_54_CLOCK_ENABLE_STATUS_MASK 0x00000002
-#define BCHP_CLKGEN_SDS_AFEC2X_TOP_3_INST_CLOCK_ENABLE_STATUS_AFEC3_54_CLOCK_ENABLE_STATUS_SHIFT 1
-
-/* CLKGEN :: SDS_AFEC2X_TOP_3_INST_CLOCK_ENABLE_STATUS :: AFEC3_108_CLOCK_ENABLE_STATUS [00:00] */
-#define BCHP_CLKGEN_SDS_AFEC2X_TOP_3_INST_CLOCK_ENABLE_STATUS_AFEC3_108_CLOCK_ENABLE_STATUS_MASK 0x00000001
-#define BCHP_CLKGEN_SDS_AFEC2X_TOP_3_INST_CLOCK_ENABLE_STATUS_AFEC3_108_CLOCK_ENABLE_STATUS_SHIFT 0
-
-/***************************************************************************
- *SDS_AFEC2X_TOP_3_INST_OBSERVE_CLOCK - Sds afec2x top 3 inst observe clock
- ***************************************************************************/
-/* CLKGEN :: SDS_AFEC2X_TOP_3_INST_OBSERVE_CLOCK :: reserved0 [31:06] */
-#define BCHP_CLKGEN_SDS_AFEC2X_TOP_3_INST_OBSERVE_CLOCK_reserved0_MASK 0xffffffc0
-#define BCHP_CLKGEN_SDS_AFEC2X_TOP_3_INST_OBSERVE_CLOCK_reserved0_SHIFT 6
-
-/* CLKGEN :: SDS_AFEC2X_TOP_3_INST_OBSERVE_CLOCK :: AFEC3_ENABLE_OBSERVE_CLOCK [05:05] */
-#define BCHP_CLKGEN_SDS_AFEC2X_TOP_3_INST_OBSERVE_CLOCK_AFEC3_ENABLE_OBSERVE_CLOCK_MASK 0x00000020
-#define BCHP_CLKGEN_SDS_AFEC2X_TOP_3_INST_OBSERVE_CLOCK_AFEC3_ENABLE_OBSERVE_CLOCK_SHIFT 5
-#define BCHP_CLKGEN_SDS_AFEC2X_TOP_3_INST_OBSERVE_CLOCK_AFEC3_ENABLE_OBSERVE_CLOCK_DEFAULT 0x00000000
-
-/* CLKGEN :: SDS_AFEC2X_TOP_3_INST_OBSERVE_CLOCK :: AFEC3_ENABLE_DIVIDER_OBSERVE_CLOCK [04:04] */
-#define BCHP_CLKGEN_SDS_AFEC2X_TOP_3_INST_OBSERVE_CLOCK_AFEC3_ENABLE_DIVIDER_OBSERVE_CLOCK_MASK 0x00000010
-#define BCHP_CLKGEN_SDS_AFEC2X_TOP_3_INST_OBSERVE_CLOCK_AFEC3_ENABLE_DIVIDER_OBSERVE_CLOCK_SHIFT 4
-#define BCHP_CLKGEN_SDS_AFEC2X_TOP_3_INST_OBSERVE_CLOCK_AFEC3_ENABLE_DIVIDER_OBSERVE_CLOCK_DEFAULT 0x00000000
-
-/* CLKGEN :: SDS_AFEC2X_TOP_3_INST_OBSERVE_CLOCK :: AFEC3_CONTROL_OBSERVE_CLOCK [03:00] */
-#define BCHP_CLKGEN_SDS_AFEC2X_TOP_3_INST_OBSERVE_CLOCK_AFEC3_CONTROL_OBSERVE_CLOCK_MASK 0x0000000f
-#define BCHP_CLKGEN_SDS_AFEC2X_TOP_3_INST_OBSERVE_CLOCK_AFEC3_CONTROL_OBSERVE_CLOCK_SHIFT 0
-#define BCHP_CLKGEN_SDS_AFEC2X_TOP_3_INST_OBSERVE_CLOCK_AFEC3_CONTROL_OBSERVE_CLOCK_DEFAULT 0x00000000
-
-/***************************************************************************
- *SDS_AFEC2X_TOP_3_INST_SEL - Sds afec2x top 3 inst sel
- ***************************************************************************/
-/* CLKGEN :: SDS_AFEC2X_TOP_3_INST_SEL :: reserved0 [31:01] */
-#define BCHP_CLKGEN_SDS_AFEC2X_TOP_3_INST_SEL_reserved0_MASK 0xfffffffe
-#define BCHP_CLKGEN_SDS_AFEC2X_TOP_3_INST_SEL_reserved0_SHIFT 1
-
-/* CLKGEN :: SDS_AFEC2X_TOP_3_INST_SEL :: AFEC3_LV_CLK_PLL_SRC_SEL [00:00] */
-#define BCHP_CLKGEN_SDS_AFEC2X_TOP_3_INST_SEL_AFEC3_LV_CLK_PLL_SRC_SEL_MASK 0x00000001
-#define BCHP_CLKGEN_SDS_AFEC2X_TOP_3_INST_SEL_AFEC3_LV_CLK_PLL_SRC_SEL_SHIFT 0
-#define BCHP_CLKGEN_SDS_AFEC2X_TOP_3_INST_SEL_AFEC3_LV_CLK_PLL_SRC_SEL_DEFAULT 0x00000000
-
-/***************************************************************************
- *SECTOP_INST_CKTAPSEL - Sectop inst cktapsel
- ***************************************************************************/
-/* CLKGEN :: SECTOP_INST_CKTAPSEL :: reserved0 [31:12] */
-#define BCHP_CLKGEN_SECTOP_INST_CKTAPSEL_reserved0_MASK 0xfffff000
-#define BCHP_CLKGEN_SECTOP_INST_CKTAPSEL_reserved0_SHIFT 12
-
-/* CLKGEN :: SECTOP_INST_CKTAPSEL :: SCB_CKTAP1_CKTAPSEL [11:06] */
-#define BCHP_CLKGEN_SECTOP_INST_CKTAPSEL_SCB_CKTAP1_CKTAPSEL_MASK 0x00000fc0
-#define BCHP_CLKGEN_SECTOP_INST_CKTAPSEL_SCB_CKTAP1_CKTAPSEL_SHIFT 6
-#define BCHP_CLKGEN_SECTOP_INST_CKTAPSEL_SCB_CKTAP1_CKTAPSEL_DEFAULT 0x00000000
-
-/* CLKGEN :: SECTOP_INST_CKTAPSEL :: SCB_CKTAP0_CKTAPSEL [05:00] */
-#define BCHP_CLKGEN_SECTOP_INST_CKTAPSEL_SCB_CKTAP0_CKTAPSEL_MASK 0x0000003f
-#define BCHP_CLKGEN_SECTOP_INST_CKTAPSEL_SCB_CKTAP0_CKTAPSEL_SHIFT 0
-#define BCHP_CLKGEN_SECTOP_INST_CKTAPSEL_SCB_CKTAP0_CKTAPSEL_DEFAULT 0x00000000
-
-/***************************************************************************
- *SECTOP_INST_OBSERVE_CLOCK - Sectop inst observe clock
- ***************************************************************************/
-/* CLKGEN :: SECTOP_INST_OBSERVE_CLOCK :: reserved0 [31:06] */
-#define BCHP_CLKGEN_SECTOP_INST_OBSERVE_CLOCK_reserved0_MASK 0xffffffc0
-#define BCHP_CLKGEN_SECTOP_INST_OBSERVE_CLOCK_reserved0_SHIFT 6
-
-/* CLKGEN :: SECTOP_INST_OBSERVE_CLOCK :: SECTOP_ENABLE_OBSERVE_CLOCK [05:05] */
-#define BCHP_CLKGEN_SECTOP_INST_OBSERVE_CLOCK_SECTOP_ENABLE_OBSERVE_CLOCK_MASK 0x00000020
-#define BCHP_CLKGEN_SECTOP_INST_OBSERVE_CLOCK_SECTOP_ENABLE_OBSERVE_CLOCK_SHIFT 5
-#define BCHP_CLKGEN_SECTOP_INST_OBSERVE_CLOCK_SECTOP_ENABLE_OBSERVE_CLOCK_DEFAULT 0x00000000
-
-/* CLKGEN :: SECTOP_INST_OBSERVE_CLOCK :: SECTOP_ENABLE_DIVIDER_OBSERVE_CLOCK [04:04] */
-#define BCHP_CLKGEN_SECTOP_INST_OBSERVE_CLOCK_SECTOP_ENABLE_DIVIDER_OBSERVE_CLOCK_MASK 0x00000010
-#define BCHP_CLKGEN_SECTOP_INST_OBSERVE_CLOCK_SECTOP_ENABLE_DIVIDER_OBSERVE_CLOCK_SHIFT 4
-#define BCHP_CLKGEN_SECTOP_INST_OBSERVE_CLOCK_SECTOP_ENABLE_DIVIDER_OBSERVE_CLOCK_DEFAULT 0x00000000
-
-/* CLKGEN :: SECTOP_INST_OBSERVE_CLOCK :: SECTOP_CONTROL_OBSERVE_CLOCK [03:00] */
-#define BCHP_CLKGEN_SECTOP_INST_OBSERVE_CLOCK_SECTOP_CONTROL_OBSERVE_CLOCK_MASK 0x0000000f
-#define BCHP_CLKGEN_SECTOP_INST_OBSERVE_CLOCK_SECTOP_CONTROL_OBSERVE_CLOCK_SHIFT 0
-#define BCHP_CLKGEN_SECTOP_INST_OBSERVE_CLOCK_SECTOP_CONTROL_OBSERVE_CLOCK_DEFAULT 0x00000000
-
-/***************************************************************************
- *SMARTCARD_MUX_SELECT - Mux selects for Smartcard clocks
- ***************************************************************************/
-/* CLKGEN :: SMARTCARD_MUX_SELECT :: reserved0 [31:02] */
-#define BCHP_CLKGEN_SMARTCARD_MUX_SELECT_reserved0_MASK 0xfffffffc
-#define BCHP_CLKGEN_SMARTCARD_MUX_SELECT_reserved0_SHIFT 2
-
-/* CLKGEN :: SMARTCARD_MUX_SELECT :: SC1_CLOCK [01:01] */
-#define BCHP_CLKGEN_SMARTCARD_MUX_SELECT_SC1_CLOCK_MASK 0x00000002
-#define BCHP_CLKGEN_SMARTCARD_MUX_SELECT_SC1_CLOCK_SHIFT 1
-#define BCHP_CLKGEN_SMARTCARD_MUX_SELECT_SC1_CLOCK_DEFAULT 0x00000000
-
-/* CLKGEN :: SMARTCARD_MUX_SELECT :: SC0_CLOCK [00:00] */
-#define BCHP_CLKGEN_SMARTCARD_MUX_SELECT_SC0_CLOCK_MASK 0x00000001
-#define BCHP_CLKGEN_SMARTCARD_MUX_SELECT_SC0_CLOCK_SHIFT 0
-#define BCHP_CLKGEN_SMARTCARD_MUX_SELECT_SC0_CLOCK_DEFAULT 0x00000000
-
-/***************************************************************************
- *SPARE - Spares
- ***************************************************************************/
-/* CLKGEN :: SPARE :: SPARE_RESET_LOW [31:12] */
-#define BCHP_CLKGEN_SPARE_SPARE_RESET_LOW_MASK 0xfffff000
-#define BCHP_CLKGEN_SPARE_SPARE_RESET_LOW_SHIFT 12
-#define BCHP_CLKGEN_SPARE_SPARE_RESET_LOW_DEFAULT 0x00000000
-
-/* CLKGEN :: SPARE :: SPARE_RESET_HIGH [11:00] */
-#define BCHP_CLKGEN_SPARE_SPARE_RESET_HIGH_MASK 0x00000fff
-#define BCHP_CLKGEN_SPARE_SPARE_RESET_HIGH_SHIFT 0
-#define BCHP_CLKGEN_SPARE_SPARE_RESET_HIGH_DEFAULT 0x00000000
-
-/***************************************************************************
- *CKTAP_CTRL - cktap control
- ***************************************************************************/
-/* CLKGEN :: CKTAP_CTRL :: reserved0 [31:01] */
-#define BCHP_CLKGEN_CKTAP_CTRL_reserved0_MASK 0xfffffffe
-#define BCHP_CLKGEN_CKTAP_CTRL_reserved0_SHIFT 1
-
-/* CLKGEN :: CKTAP_CTRL :: CKTAP_SW_OVERWRITE [00:00] */
-#define BCHP_CLKGEN_CKTAP_CTRL_CKTAP_SW_OVERWRITE_MASK 0x00000001
-#define BCHP_CLKGEN_CKTAP_CTRL_CKTAP_SW_OVERWRITE_SHIFT 0
-#define BCHP_CLKGEN_CKTAP_CTRL_CKTAP_SW_OVERWRITE_DEFAULT 0x00000001
-
-/***************************************************************************
- *STB_CHAN_TOP_INST_CLOCK_ENABLE - Stb chan top inst clock enable
- ***************************************************************************/
-/* CLKGEN :: STB_CHAN_TOP_INST_CLOCK_ENABLE :: reserved0 [31:02] */
-#define BCHP_CLKGEN_STB_CHAN_TOP_INST_CLOCK_ENABLE_reserved0_MASK 0xfffffffc
-#define BCHP_CLKGEN_STB_CHAN_TOP_INST_CLOCK_ENABLE_reserved0_SHIFT 2
-
-/* CLKGEN :: STB_CHAN_TOP_INST_CLOCK_ENABLE :: CHAN_54_CLOCK_ENABLE [01:01] */
-#define BCHP_CLKGEN_STB_CHAN_TOP_INST_CLOCK_ENABLE_CHAN_54_CLOCK_ENABLE_MASK 0x00000002
-#define BCHP_CLKGEN_STB_CHAN_TOP_INST_CLOCK_ENABLE_CHAN_54_CLOCK_ENABLE_SHIFT 1
-#define BCHP_CLKGEN_STB_CHAN_TOP_INST_CLOCK_ENABLE_CHAN_54_CLOCK_ENABLE_DEFAULT 0x00000001
-
-/* CLKGEN :: STB_CHAN_TOP_INST_CLOCK_ENABLE :: CHAN_108_CLOCK_ENABLE [00:00] */
-#define BCHP_CLKGEN_STB_CHAN_TOP_INST_CLOCK_ENABLE_CHAN_108_CLOCK_ENABLE_MASK 0x00000001
-#define BCHP_CLKGEN_STB_CHAN_TOP_INST_CLOCK_ENABLE_CHAN_108_CLOCK_ENABLE_SHIFT 0
-#define BCHP_CLKGEN_STB_CHAN_TOP_INST_CLOCK_ENABLE_CHAN_108_CLOCK_ENABLE_DEFAULT 0x00000001
-
-/***************************************************************************
- *STB_CHAN_TOP_INST_CLOCK_ENABLE_STATUS - Clock Enable Status
- ***************************************************************************/
-/* CLKGEN :: STB_CHAN_TOP_INST_CLOCK_ENABLE_STATUS :: reserved0 [31:02] */
-#define BCHP_CLKGEN_STB_CHAN_TOP_INST_CLOCK_ENABLE_STATUS_reserved0_MASK 0xfffffffc
-#define BCHP_CLKGEN_STB_CHAN_TOP_INST_CLOCK_ENABLE_STATUS_reserved0_SHIFT 2
-
-/* CLKGEN :: STB_CHAN_TOP_INST_CLOCK_ENABLE_STATUS :: CHAN_54_CLOCK_ENABLE_STATUS [01:01] */
-#define BCHP_CLKGEN_STB_CHAN_TOP_INST_CLOCK_ENABLE_STATUS_CHAN_54_CLOCK_ENABLE_STATUS_MASK 0x00000002
-#define BCHP_CLKGEN_STB_CHAN_TOP_INST_CLOCK_ENABLE_STATUS_CHAN_54_CLOCK_ENABLE_STATUS_SHIFT 1
-
-/* CLKGEN :: STB_CHAN_TOP_INST_CLOCK_ENABLE_STATUS :: CHAN_108_CLOCK_ENABLE_STATUS [00:00] */
-#define BCHP_CLKGEN_STB_CHAN_TOP_INST_CLOCK_ENABLE_STATUS_CHAN_108_CLOCK_ENABLE_STATUS_MASK 0x00000001
-#define BCHP_CLKGEN_STB_CHAN_TOP_INST_CLOCK_ENABLE_STATUS_CHAN_108_CLOCK_ENABLE_STATUS_SHIFT 0
-
-/***************************************************************************
- *STB_CHAN_TOP_INST_OBSERVE_CLOCK - Stb chan top inst observe clock
- ***************************************************************************/
-/* CLKGEN :: STB_CHAN_TOP_INST_OBSERVE_CLOCK :: reserved0 [31:06] */
-#define BCHP_CLKGEN_STB_CHAN_TOP_INST_OBSERVE_CLOCK_reserved0_MASK 0xffffffc0
-#define BCHP_CLKGEN_STB_CHAN_TOP_INST_OBSERVE_CLOCK_reserved0_SHIFT 6
-
-/* CLKGEN :: STB_CHAN_TOP_INST_OBSERVE_CLOCK :: CHAN_ENABLE_OBSERVE_CLOCK [05:05] */
-#define BCHP_CLKGEN_STB_CHAN_TOP_INST_OBSERVE_CLOCK_CHAN_ENABLE_OBSERVE_CLOCK_MASK 0x00000020
-#define BCHP_CLKGEN_STB_CHAN_TOP_INST_OBSERVE_CLOCK_CHAN_ENABLE_OBSERVE_CLOCK_SHIFT 5
-#define BCHP_CLKGEN_STB_CHAN_TOP_INST_OBSERVE_CLOCK_CHAN_ENABLE_OBSERVE_CLOCK_DEFAULT 0x00000000
-
-/* CLKGEN :: STB_CHAN_TOP_INST_OBSERVE_CLOCK :: CHAN_ENABLE_DIVIDER_OBSERVE_CLOCK [04:04] */
-#define BCHP_CLKGEN_STB_CHAN_TOP_INST_OBSERVE_CLOCK_CHAN_ENABLE_DIVIDER_OBSERVE_CLOCK_MASK 0x00000010
-#define BCHP_CLKGEN_STB_CHAN_TOP_INST_OBSERVE_CLOCK_CHAN_ENABLE_DIVIDER_OBSERVE_CLOCK_SHIFT 4
-#define BCHP_CLKGEN_STB_CHAN_TOP_INST_OBSERVE_CLOCK_CHAN_ENABLE_DIVIDER_OBSERVE_CLOCK_DEFAULT 0x00000000
-
-/* CLKGEN :: STB_CHAN_TOP_INST_OBSERVE_CLOCK :: CHAN_CONTROL_OBSERVE_CLOCK [03:00] */
-#define BCHP_CLKGEN_STB_CHAN_TOP_INST_OBSERVE_CLOCK_CHAN_CONTROL_OBSERVE_CLOCK_MASK 0x0000000f
-#define BCHP_CLKGEN_STB_CHAN_TOP_INST_OBSERVE_CLOCK_CHAN_CONTROL_OBSERVE_CLOCK_SHIFT 0
-#define BCHP_CLKGEN_STB_CHAN_TOP_INST_OBSERVE_CLOCK_CHAN_CONTROL_OBSERVE_CLOCK_DEFAULT 0x00000000
-
-/***************************************************************************
- *SYS_CTRL_INST_CKTAPSEL - Sys ctrl inst cktapsel
- ***************************************************************************/
-/* CLKGEN :: SYS_CTRL_INST_CKTAPSEL :: reserved0 [31:12] */
-#define BCHP_CLKGEN_SYS_CTRL_INST_CKTAPSEL_reserved0_MASK 0xfffff000
-#define BCHP_CLKGEN_SYS_CTRL_INST_CKTAPSEL_reserved0_SHIFT 12
-
-/* CLKGEN :: SYS_CTRL_INST_CKTAPSEL :: SCB_CKTAP1_CKTAPSEL [11:06] */
-#define BCHP_CLKGEN_SYS_CTRL_INST_CKTAPSEL_SCB_CKTAP1_CKTAPSEL_MASK 0x00000fc0
-#define BCHP_CLKGEN_SYS_CTRL_INST_CKTAPSEL_SCB_CKTAP1_CKTAPSEL_SHIFT 6
-#define BCHP_CLKGEN_SYS_CTRL_INST_CKTAPSEL_SCB_CKTAP1_CKTAPSEL_DEFAULT 0x00000000
-
-/* CLKGEN :: SYS_CTRL_INST_CKTAPSEL :: SCB_CKTAP0_CKTAPSEL [05:00] */
-#define BCHP_CLKGEN_SYS_CTRL_INST_CKTAPSEL_SCB_CKTAP0_CKTAPSEL_MASK 0x0000003f
-#define BCHP_CLKGEN_SYS_CTRL_INST_CKTAPSEL_SCB_CKTAP0_CKTAPSEL_SHIFT 0
-#define BCHP_CLKGEN_SYS_CTRL_INST_CKTAPSEL_SCB_CKTAP0_CKTAPSEL_DEFAULT 0x00000000
-
-/***************************************************************************
- *SYS_CTRL_INST_CLOCK_DISABLE - Disable SYS_CTRL_INST's clocks
- ***************************************************************************/
-/* CLKGEN :: SYS_CTRL_INST_CLOCK_DISABLE :: reserved0 [31:05] */
-#define BCHP_CLKGEN_SYS_CTRL_INST_CLOCK_DISABLE_reserved0_MASK 0xffffffe0
-#define BCHP_CLKGEN_SYS_CTRL_INST_CLOCK_DISABLE_reserved0_SHIFT 5
-
-/* CLKGEN :: SYS_CTRL_INST_CLOCK_DISABLE :: DISABLE_SYSCTRL_UPG_CLOCK [04:04] */
-#define BCHP_CLKGEN_SYS_CTRL_INST_CLOCK_DISABLE_DISABLE_SYSCTRL_UPG_CLOCK_MASK 0x00000010
-#define BCHP_CLKGEN_SYS_CTRL_INST_CLOCK_DISABLE_DISABLE_SYSCTRL_UPG_CLOCK_SHIFT 4
-#define BCHP_CLKGEN_SYS_CTRL_INST_CLOCK_DISABLE_DISABLE_SYSCTRL_UPG_CLOCK_DEFAULT 0x00000000
-
-/* CLKGEN :: SYS_CTRL_INST_CLOCK_DISABLE :: DISABLE_SC1_CLOCK [03:03] */
-#define BCHP_CLKGEN_SYS_CTRL_INST_CLOCK_DISABLE_DISABLE_SC1_CLOCK_MASK 0x00000008
-#define BCHP_CLKGEN_SYS_CTRL_INST_CLOCK_DISABLE_DISABLE_SC1_CLOCK_SHIFT 3
-#define BCHP_CLKGEN_SYS_CTRL_INST_CLOCK_DISABLE_DISABLE_SC1_CLOCK_DEFAULT 0x00000000
-
-/* CLKGEN :: SYS_CTRL_INST_CLOCK_DISABLE :: DISABLE_SC0_CLOCK [02:02] */
-#define BCHP_CLKGEN_SYS_CTRL_INST_CLOCK_DISABLE_DISABLE_SC0_CLOCK_MASK 0x00000004
-#define BCHP_CLKGEN_SYS_CTRL_INST_CLOCK_DISABLE_DISABLE_SC0_CLOCK_SHIFT 2
-#define BCHP_CLKGEN_SYS_CTRL_INST_CLOCK_DISABLE_DISABLE_SC0_CLOCK_DEFAULT 0x00000000
-
-/* CLKGEN :: SYS_CTRL_INST_CLOCK_DISABLE :: DISABLE_AVSTOP_PVTMON_CLOCK [01:01] */
-#define BCHP_CLKGEN_SYS_CTRL_INST_CLOCK_DISABLE_DISABLE_AVSTOP_PVTMON_CLOCK_MASK 0x00000002
-#define BCHP_CLKGEN_SYS_CTRL_INST_CLOCK_DISABLE_DISABLE_AVSTOP_PVTMON_CLOCK_SHIFT 1
-#define BCHP_CLKGEN_SYS_CTRL_INST_CLOCK_DISABLE_DISABLE_AVSTOP_PVTMON_CLOCK_DEFAULT 0x00000000
-
-/* CLKGEN :: SYS_CTRL_INST_CLOCK_DISABLE :: DISABLE_AVSTOP_27_UART_CLOCK [00:00] */
-#define BCHP_CLKGEN_SYS_CTRL_INST_CLOCK_DISABLE_DISABLE_AVSTOP_27_UART_CLOCK_MASK 0x00000001
-#define BCHP_CLKGEN_SYS_CTRL_INST_CLOCK_DISABLE_DISABLE_AVSTOP_27_UART_CLOCK_SHIFT 0
-#define BCHP_CLKGEN_SYS_CTRL_INST_CLOCK_DISABLE_DISABLE_AVSTOP_27_UART_CLOCK_DEFAULT 0x00000000
-
-/***************************************************************************
- *SYS_CTRL_INST_CLOCK_DISABLE_STATUS - Clock Disable Status
- ***************************************************************************/
-/* CLKGEN :: SYS_CTRL_INST_CLOCK_DISABLE_STATUS :: reserved0 [31:05] */
-#define BCHP_CLKGEN_SYS_CTRL_INST_CLOCK_DISABLE_STATUS_reserved0_MASK 0xffffffe0
-#define BCHP_CLKGEN_SYS_CTRL_INST_CLOCK_DISABLE_STATUS_reserved0_SHIFT 5
-
-/* CLKGEN :: SYS_CTRL_INST_CLOCK_DISABLE_STATUS :: DISABLE_SYSCTRL_UPG_CLOCK_STATUS [04:04] */
-#define BCHP_CLKGEN_SYS_CTRL_INST_CLOCK_DISABLE_STATUS_DISABLE_SYSCTRL_UPG_CLOCK_STATUS_MASK 0x00000010
-#define BCHP_CLKGEN_SYS_CTRL_INST_CLOCK_DISABLE_STATUS_DISABLE_SYSCTRL_UPG_CLOCK_STATUS_SHIFT 4
-
-/* CLKGEN :: SYS_CTRL_INST_CLOCK_DISABLE_STATUS :: DISABLE_SC1_CLOCK_STATUS [03:03] */
-#define BCHP_CLKGEN_SYS_CTRL_INST_CLOCK_DISABLE_STATUS_DISABLE_SC1_CLOCK_STATUS_MASK 0x00000008
-#define BCHP_CLKGEN_SYS_CTRL_INST_CLOCK_DISABLE_STATUS_DISABLE_SC1_CLOCK_STATUS_SHIFT 3
-
-/* CLKGEN :: SYS_CTRL_INST_CLOCK_DISABLE_STATUS :: DISABLE_SC0_CLOCK_STATUS [02:02] */
-#define BCHP_CLKGEN_SYS_CTRL_INST_CLOCK_DISABLE_STATUS_DISABLE_SC0_CLOCK_STATUS_MASK 0x00000004
-#define BCHP_CLKGEN_SYS_CTRL_INST_CLOCK_DISABLE_STATUS_DISABLE_SC0_CLOCK_STATUS_SHIFT 2
-
-/* CLKGEN :: SYS_CTRL_INST_CLOCK_DISABLE_STATUS :: DISABLE_AVSTOP_PVTMON_CLOCK_STATUS [01:01] */
-#define BCHP_CLKGEN_SYS_CTRL_INST_CLOCK_DISABLE_STATUS_DISABLE_AVSTOP_PVTMON_CLOCK_STATUS_MASK 0x00000002
-#define BCHP_CLKGEN_SYS_CTRL_INST_CLOCK_DISABLE_STATUS_DISABLE_AVSTOP_PVTMON_CLOCK_STATUS_SHIFT 1
-
-/* CLKGEN :: SYS_CTRL_INST_CLOCK_DISABLE_STATUS :: DISABLE_AVSTOP_27_UART_CLOCK_STATUS [00:00] */
-#define BCHP_CLKGEN_SYS_CTRL_INST_CLOCK_DISABLE_STATUS_DISABLE_AVSTOP_27_UART_CLOCK_STATUS_MASK 0x00000001
-#define BCHP_CLKGEN_SYS_CTRL_INST_CLOCK_DISABLE_STATUS_DISABLE_AVSTOP_27_UART_CLOCK_STATUS_SHIFT 0
-
-/***************************************************************************
- *SYS_CTRL_INST_OBSERVE_CLOCK - Sys ctrl inst observe clock
- ***************************************************************************/
-/* CLKGEN :: SYS_CTRL_INST_OBSERVE_CLOCK :: reserved0 [31:06] */
-#define BCHP_CLKGEN_SYS_CTRL_INST_OBSERVE_CLOCK_reserved0_MASK 0xffffffc0
-#define BCHP_CLKGEN_SYS_CTRL_INST_OBSERVE_CLOCK_reserved0_SHIFT 6
-
-/* CLKGEN :: SYS_CTRL_INST_OBSERVE_CLOCK :: AVS_TOP_ENABLE_OBSERVE_CLOCK [05:05] */
-#define BCHP_CLKGEN_SYS_CTRL_INST_OBSERVE_CLOCK_AVS_TOP_ENABLE_OBSERVE_CLOCK_MASK 0x00000020
-#define BCHP_CLKGEN_SYS_CTRL_INST_OBSERVE_CLOCK_AVS_TOP_ENABLE_OBSERVE_CLOCK_SHIFT 5
-#define BCHP_CLKGEN_SYS_CTRL_INST_OBSERVE_CLOCK_AVS_TOP_ENABLE_OBSERVE_CLOCK_DEFAULT 0x00000000
-
-/* CLKGEN :: SYS_CTRL_INST_OBSERVE_CLOCK :: AVS_TOP_ENABLE_DIVIDER_OBSERVE_CLOCK [04:04] */
-#define BCHP_CLKGEN_SYS_CTRL_INST_OBSERVE_CLOCK_AVS_TOP_ENABLE_DIVIDER_OBSERVE_CLOCK_MASK 0x00000010
-#define BCHP_CLKGEN_SYS_CTRL_INST_OBSERVE_CLOCK_AVS_TOP_ENABLE_DIVIDER_OBSERVE_CLOCK_SHIFT 4
-#define BCHP_CLKGEN_SYS_CTRL_INST_OBSERVE_CLOCK_AVS_TOP_ENABLE_DIVIDER_OBSERVE_CLOCK_DEFAULT 0x00000000
-
-/* CLKGEN :: SYS_CTRL_INST_OBSERVE_CLOCK :: AVS_TOP_CONTROL_OBSERVE_CLOCK [03:00] */
-#define BCHP_CLKGEN_SYS_CTRL_INST_OBSERVE_CLOCK_AVS_TOP_CONTROL_OBSERVE_CLOCK_MASK 0x0000000f
-#define BCHP_CLKGEN_SYS_CTRL_INST_OBSERVE_CLOCK_AVS_TOP_CONTROL_OBSERVE_CLOCK_SHIFT 0
-#define BCHP_CLKGEN_SYS_CTRL_INST_OBSERVE_CLOCK_AVS_TOP_CONTROL_OBSERVE_CLOCK_DEFAULT 0x00000000
-
-/***************************************************************************
- *TESTPORT - Special Testport Controls
- ***************************************************************************/
-/* CLKGEN :: TESTPORT :: reserved0 [31:04] */
-#define BCHP_CLKGEN_TESTPORT_reserved0_MASK 0xfffffff0
-#define BCHP_CLKGEN_TESTPORT_reserved0_SHIFT 4
-
-/* CLKGEN :: TESTPORT :: PLL_TEST_STATUS_SELECT [03:00] */
-#define BCHP_CLKGEN_TESTPORT_PLL_TEST_STATUS_SELECT_MASK 0x0000000f
-#define BCHP_CLKGEN_TESTPORT_PLL_TEST_STATUS_SELECT_SHIFT 0
-#define BCHP_CLKGEN_TESTPORT_PLL_TEST_STATUS_SELECT_DEFAULT 0x00000000
-
-/***************************************************************************
- *TRIPLE_GENET_TOP_RGMII_INST_CKTAPSEL - Triple genet top rgmii inst cktapsel
- ***************************************************************************/
-/* CLKGEN :: TRIPLE_GENET_TOP_RGMII_INST_CKTAPSEL :: reserved0 [31:12] */
-#define BCHP_CLKGEN_TRIPLE_GENET_TOP_RGMII_INST_CKTAPSEL_reserved0_MASK 0xfffff000
-#define BCHP_CLKGEN_TRIPLE_GENET_TOP_RGMII_INST_CKTAPSEL_reserved0_SHIFT 12
-
-/* CLKGEN :: TRIPLE_GENET_TOP_RGMII_INST_CKTAPSEL :: SCB_CKTAP1_CKTAPSEL [11:06] */
-#define BCHP_CLKGEN_TRIPLE_GENET_TOP_RGMII_INST_CKTAPSEL_SCB_CKTAP1_CKTAPSEL_MASK 0x00000fc0
-#define BCHP_CLKGEN_TRIPLE_GENET_TOP_RGMII_INST_CKTAPSEL_SCB_CKTAP1_CKTAPSEL_SHIFT 6
-#define BCHP_CLKGEN_TRIPLE_GENET_TOP_RGMII_INST_CKTAPSEL_SCB_CKTAP1_CKTAPSEL_DEFAULT 0x00000000
-
-/* CLKGEN :: TRIPLE_GENET_TOP_RGMII_INST_CKTAPSEL :: SCB_CKTAP0_CKTAPSEL [05:00] */
-#define BCHP_CLKGEN_TRIPLE_GENET_TOP_RGMII_INST_CKTAPSEL_SCB_CKTAP0_CKTAPSEL_MASK 0x0000003f
-#define BCHP_CLKGEN_TRIPLE_GENET_TOP_RGMII_INST_CKTAPSEL_SCB_CKTAP0_CKTAPSEL_SHIFT 0
-#define BCHP_CLKGEN_TRIPLE_GENET_TOP_RGMII_INST_CKTAPSEL_SCB_CKTAP0_CKTAPSEL_DEFAULT 0x00000000
-
-/***************************************************************************
- *TRIPLE_GENET_TOP_RGMII_INST_CLOCK_DISABLE - Disable TRIPLE_GENET_TOP_RGMII_INST's clocks
- ***************************************************************************/
-/* CLKGEN :: TRIPLE_GENET_TOP_RGMII_INST_CLOCK_DISABLE :: reserved0 [31:12] */
-#define BCHP_CLKGEN_TRIPLE_GENET_TOP_RGMII_INST_CLOCK_DISABLE_reserved0_MASK 0xfffff000
-#define BCHP_CLKGEN_TRIPLE_GENET_TOP_RGMII_INST_CLOCK_DISABLE_reserved0_SHIFT 12
-
-/* CLKGEN :: TRIPLE_GENET_TOP_RGMII_INST_CLOCK_DISABLE :: DISABLE_GENET2_SYSTEM_SLOW_CLOCK [11:11] */
-#define BCHP_CLKGEN_TRIPLE_GENET_TOP_RGMII_INST_CLOCK_DISABLE_DISABLE_GENET2_SYSTEM_SLOW_CLOCK_MASK 0x00000800
-#define BCHP_CLKGEN_TRIPLE_GENET_TOP_RGMII_INST_CLOCK_DISABLE_DISABLE_GENET2_SYSTEM_SLOW_CLOCK_SHIFT 11
-#define BCHP_CLKGEN_TRIPLE_GENET_TOP_RGMII_INST_CLOCK_DISABLE_DISABLE_GENET2_SYSTEM_SLOW_CLOCK_DEFAULT 0x00000000
-
-/* CLKGEN :: TRIPLE_GENET_TOP_RGMII_INST_CLOCK_DISABLE :: DISABLE_GENET2_SYSTEM_PM_CLOCK [10:10] */
-#define BCHP_CLKGEN_TRIPLE_GENET_TOP_RGMII_INST_CLOCK_DISABLE_DISABLE_GENET2_SYSTEM_PM_CLOCK_MASK 0x00000400
-#define BCHP_CLKGEN_TRIPLE_GENET_TOP_RGMII_INST_CLOCK_DISABLE_DISABLE_GENET2_SYSTEM_PM_CLOCK_SHIFT 10
-#define BCHP_CLKGEN_TRIPLE_GENET_TOP_RGMII_INST_CLOCK_DISABLE_DISABLE_GENET2_SYSTEM_PM_CLOCK_DEFAULT 0x00000000
-
-/* CLKGEN :: TRIPLE_GENET_TOP_RGMII_INST_CLOCK_DISABLE :: DISABLE_GENET2_SYSTEM_FAST_CLOCK [09:09] */
-#define BCHP_CLKGEN_TRIPLE_GENET_TOP_RGMII_INST_CLOCK_DISABLE_DISABLE_GENET2_SYSTEM_FAST_CLOCK_MASK 0x00000200
-#define BCHP_CLKGEN_TRIPLE_GENET_TOP_RGMII_INST_CLOCK_DISABLE_DISABLE_GENET2_SYSTEM_FAST_CLOCK_SHIFT 9
-#define BCHP_CLKGEN_TRIPLE_GENET_TOP_RGMII_INST_CLOCK_DISABLE_DISABLE_GENET2_SYSTEM_FAST_CLOCK_DEFAULT 0x00000000
-
-/* CLKGEN :: TRIPLE_GENET_TOP_RGMII_INST_CLOCK_DISABLE :: DISABLE_GENET2_ALWAYSON_CLOCK [08:08] */
-#define BCHP_CLKGEN_TRIPLE_GENET_TOP_RGMII_INST_CLOCK_DISABLE_DISABLE_GENET2_ALWAYSON_CLOCK_MASK 0x00000100
-#define BCHP_CLKGEN_TRIPLE_GENET_TOP_RGMII_INST_CLOCK_DISABLE_DISABLE_GENET2_ALWAYSON_CLOCK_SHIFT 8
-#define BCHP_CLKGEN_TRIPLE_GENET_TOP_RGMII_INST_CLOCK_DISABLE_DISABLE_GENET2_ALWAYSON_CLOCK_DEFAULT 0x00000000
-
-/* CLKGEN :: TRIPLE_GENET_TOP_RGMII_INST_CLOCK_DISABLE :: DISABLE_GENET1_SYSTEM_SLOW_CLOCK [07:07] */
-#define BCHP_CLKGEN_TRIPLE_GENET_TOP_RGMII_INST_CLOCK_DISABLE_DISABLE_GENET1_SYSTEM_SLOW_CLOCK_MASK 0x00000080
-#define BCHP_CLKGEN_TRIPLE_GENET_TOP_RGMII_INST_CLOCK_DISABLE_DISABLE_GENET1_SYSTEM_SLOW_CLOCK_SHIFT 7
-#define BCHP_CLKGEN_TRIPLE_GENET_TOP_RGMII_INST_CLOCK_DISABLE_DISABLE_GENET1_SYSTEM_SLOW_CLOCK_DEFAULT 0x00000000
-
-/* CLKGEN :: TRIPLE_GENET_TOP_RGMII_INST_CLOCK_DISABLE :: DISABLE_GENET1_SYSTEM_PM_CLOCK [06:06] */
-#define BCHP_CLKGEN_TRIPLE_GENET_TOP_RGMII_INST_CLOCK_DISABLE_DISABLE_GENET1_SYSTEM_PM_CLOCK_MASK 0x00000040
-#define BCHP_CLKGEN_TRIPLE_GENET_TOP_RGMII_INST_CLOCK_DISABLE_DISABLE_GENET1_SYSTEM_PM_CLOCK_SHIFT 6
-#define BCHP_CLKGEN_TRIPLE_GENET_TOP_RGMII_INST_CLOCK_DISABLE_DISABLE_GENET1_SYSTEM_PM_CLOCK_DEFAULT 0x00000000
-
-/* CLKGEN :: TRIPLE_GENET_TOP_RGMII_INST_CLOCK_DISABLE :: DISABLE_GENET1_SYSTEM_FAST_CLOCK [05:05] */
-#define BCHP_CLKGEN_TRIPLE_GENET_TOP_RGMII_INST_CLOCK_DISABLE_DISABLE_GENET1_SYSTEM_FAST_CLOCK_MASK 0x00000020
-#define BCHP_CLKGEN_TRIPLE_GENET_TOP_RGMII_INST_CLOCK_DISABLE_DISABLE_GENET1_SYSTEM_FAST_CLOCK_SHIFT 5
-#define BCHP_CLKGEN_TRIPLE_GENET_TOP_RGMII_INST_CLOCK_DISABLE_DISABLE_GENET1_SYSTEM_FAST_CLOCK_DEFAULT 0x00000000
-
-/* CLKGEN :: TRIPLE_GENET_TOP_RGMII_INST_CLOCK_DISABLE :: DISABLE_GENET1_ALWAYSON_CLOCK [04:04] */
-#define BCHP_CLKGEN_TRIPLE_GENET_TOP_RGMII_INST_CLOCK_DISABLE_DISABLE_GENET1_ALWAYSON_CLOCK_MASK 0x00000010
-#define BCHP_CLKGEN_TRIPLE_GENET_TOP_RGMII_INST_CLOCK_DISABLE_DISABLE_GENET1_ALWAYSON_CLOCK_SHIFT 4
-#define BCHP_CLKGEN_TRIPLE_GENET_TOP_RGMII_INST_CLOCK_DISABLE_DISABLE_GENET1_ALWAYSON_CLOCK_DEFAULT 0x00000000
-
-/* CLKGEN :: TRIPLE_GENET_TOP_RGMII_INST_CLOCK_DISABLE :: DISABLE_GENET0_SYSTEM_SLOW_CLOCK [03:03] */
-#define BCHP_CLKGEN_TRIPLE_GENET_TOP_RGMII_INST_CLOCK_DISABLE_DISABLE_GENET0_SYSTEM_SLOW_CLOCK_MASK 0x00000008
-#define BCHP_CLKGEN_TRIPLE_GENET_TOP_RGMII_INST_CLOCK_DISABLE_DISABLE_GENET0_SYSTEM_SLOW_CLOCK_SHIFT 3
-#define BCHP_CLKGEN_TRIPLE_GENET_TOP_RGMII_INST_CLOCK_DISABLE_DISABLE_GENET0_SYSTEM_SLOW_CLOCK_DEFAULT 0x00000000
-
-/* CLKGEN :: TRIPLE_GENET_TOP_RGMII_INST_CLOCK_DISABLE :: DISABLE_GENET0_SYSTEM_PM_CLOCK [02:02] */
-#define BCHP_CLKGEN_TRIPLE_GENET_TOP_RGMII_INST_CLOCK_DISABLE_DISABLE_GENET0_SYSTEM_PM_CLOCK_MASK 0x00000004
-#define BCHP_CLKGEN_TRIPLE_GENET_TOP_RGMII_INST_CLOCK_DISABLE_DISABLE_GENET0_SYSTEM_PM_CLOCK_SHIFT 2
-#define BCHP_CLKGEN_TRIPLE_GENET_TOP_RGMII_INST_CLOCK_DISABLE_DISABLE_GENET0_SYSTEM_PM_CLOCK_DEFAULT 0x00000000
-
-/* CLKGEN :: TRIPLE_GENET_TOP_RGMII_INST_CLOCK_DISABLE :: DISABLE_GENET0_SYSTEM_FAST_CLOCK [01:01] */
-#define BCHP_CLKGEN_TRIPLE_GENET_TOP_RGMII_INST_CLOCK_DISABLE_DISABLE_GENET0_SYSTEM_FAST_CLOCK_MASK 0x00000002
-#define BCHP_CLKGEN_TRIPLE_GENET_TOP_RGMII_INST_CLOCK_DISABLE_DISABLE_GENET0_SYSTEM_FAST_CLOCK_SHIFT 1
-#define BCHP_CLKGEN_TRIPLE_GENET_TOP_RGMII_INST_CLOCK_DISABLE_DISABLE_GENET0_SYSTEM_FAST_CLOCK_DEFAULT 0x00000000
-
-/* CLKGEN :: TRIPLE_GENET_TOP_RGMII_INST_CLOCK_DISABLE :: DISABLE_GENET0_ALWAYSON_CLOCK [00:00] */
-#define BCHP_CLKGEN_TRIPLE_GENET_TOP_RGMII_INST_CLOCK_DISABLE_DISABLE_GENET0_ALWAYSON_CLOCK_MASK 0x00000001
-#define BCHP_CLKGEN_TRIPLE_GENET_TOP_RGMII_INST_CLOCK_DISABLE_DISABLE_GENET0_ALWAYSON_CLOCK_SHIFT 0
-#define BCHP_CLKGEN_TRIPLE_GENET_TOP_RGMII_INST_CLOCK_DISABLE_DISABLE_GENET0_ALWAYSON_CLOCK_DEFAULT 0x00000000
-
-/***************************************************************************
- *TRIPLE_GENET_TOP_RGMII_INST_CLOCK_DISABLE_STATUS - Clock Disable Status
- ***************************************************************************/
-/* CLKGEN :: TRIPLE_GENET_TOP_RGMII_INST_CLOCK_DISABLE_STATUS :: reserved0 [31:12] */
-#define BCHP_CLKGEN_TRIPLE_GENET_TOP_RGMII_INST_CLOCK_DISABLE_STATUS_reserved0_MASK 0xfffff000
-#define BCHP_CLKGEN_TRIPLE_GENET_TOP_RGMII_INST_CLOCK_DISABLE_STATUS_reserved0_SHIFT 12
-
-/* CLKGEN :: TRIPLE_GENET_TOP_RGMII_INST_CLOCK_DISABLE_STATUS :: DISABLE_GENET2_SYSTEM_SLOW_CLOCK_STATUS [11:11] */
-#define BCHP_CLKGEN_TRIPLE_GENET_TOP_RGMII_INST_CLOCK_DISABLE_STATUS_DISABLE_GENET2_SYSTEM_SLOW_CLOCK_STATUS_MASK 0x00000800
-#define BCHP_CLKGEN_TRIPLE_GENET_TOP_RGMII_INST_CLOCK_DISABLE_STATUS_DISABLE_GENET2_SYSTEM_SLOW_CLOCK_STATUS_SHIFT 11
-
-/* CLKGEN :: TRIPLE_GENET_TOP_RGMII_INST_CLOCK_DISABLE_STATUS :: DISABLE_GENET2_SYSTEM_PM_CLOCK_STATUS [10:10] */
-#define BCHP_CLKGEN_TRIPLE_GENET_TOP_RGMII_INST_CLOCK_DISABLE_STATUS_DISABLE_GENET2_SYSTEM_PM_CLOCK_STATUS_MASK 0x00000400
-#define BCHP_CLKGEN_TRIPLE_GENET_TOP_RGMII_INST_CLOCK_DISABLE_STATUS_DISABLE_GENET2_SYSTEM_PM_CLOCK_STATUS_SHIFT 10
-
-/* CLKGEN :: TRIPLE_GENET_TOP_RGMII_INST_CLOCK_DISABLE_STATUS :: DISABLE_GENET2_SYSTEM_FAST_CLOCK_STATUS [09:09] */
-#define BCHP_CLKGEN_TRIPLE_GENET_TOP_RGMII_INST_CLOCK_DISABLE_STATUS_DISABLE_GENET2_SYSTEM_FAST_CLOCK_STATUS_MASK 0x00000200
-#define BCHP_CLKGEN_TRIPLE_GENET_TOP_RGMII_INST_CLOCK_DISABLE_STATUS_DISABLE_GENET2_SYSTEM_FAST_CLOCK_STATUS_SHIFT 9
-
-/* CLKGEN :: TRIPLE_GENET_TOP_RGMII_INST_CLOCK_DISABLE_STATUS :: DISABLE_GENET2_ALWAYSON_CLOCK_STATUS [08:08] */
-#define BCHP_CLKGEN_TRIPLE_GENET_TOP_RGMII_INST_CLOCK_DISABLE_STATUS_DISABLE_GENET2_ALWAYSON_CLOCK_STATUS_MASK 0x00000100
-#define BCHP_CLKGEN_TRIPLE_GENET_TOP_RGMII_INST_CLOCK_DISABLE_STATUS_DISABLE_GENET2_ALWAYSON_CLOCK_STATUS_SHIFT 8
-
-/* CLKGEN :: TRIPLE_GENET_TOP_RGMII_INST_CLOCK_DISABLE_STATUS :: DISABLE_GENET1_SYSTEM_SLOW_CLOCK_STATUS [07:07] */
-#define BCHP_CLKGEN_TRIPLE_GENET_TOP_RGMII_INST_CLOCK_DISABLE_STATUS_DISABLE_GENET1_SYSTEM_SLOW_CLOCK_STATUS_MASK 0x00000080
-#define BCHP_CLKGEN_TRIPLE_GENET_TOP_RGMII_INST_CLOCK_DISABLE_STATUS_DISABLE_GENET1_SYSTEM_SLOW_CLOCK_STATUS_SHIFT 7
-
-/* CLKGEN :: TRIPLE_GENET_TOP_RGMII_INST_CLOCK_DISABLE_STATUS :: DISABLE_GENET1_SYSTEM_PM_CLOCK_STATUS [06:06] */
-#define BCHP_CLKGEN_TRIPLE_GENET_TOP_RGMII_INST_CLOCK_DISABLE_STATUS_DISABLE_GENET1_SYSTEM_PM_CLOCK_STATUS_MASK 0x00000040
-#define BCHP_CLKGEN_TRIPLE_GENET_TOP_RGMII_INST_CLOCK_DISABLE_STATUS_DISABLE_GENET1_SYSTEM_PM_CLOCK_STATUS_SHIFT 6
-
-/* CLKGEN :: TRIPLE_GENET_TOP_RGMII_INST_CLOCK_DISABLE_STATUS :: DISABLE_GENET1_SYSTEM_FAST_CLOCK_STATUS [05:05] */
-#define BCHP_CLKGEN_TRIPLE_GENET_TOP_RGMII_INST_CLOCK_DISABLE_STATUS_DISABLE_GENET1_SYSTEM_FAST_CLOCK_STATUS_MASK 0x00000020
-#define BCHP_CLKGEN_TRIPLE_GENET_TOP_RGMII_INST_CLOCK_DISABLE_STATUS_DISABLE_GENET1_SYSTEM_FAST_CLOCK_STATUS_SHIFT 5
-
-/* CLKGEN :: TRIPLE_GENET_TOP_RGMII_INST_CLOCK_DISABLE_STATUS :: DISABLE_GENET1_ALWAYSON_CLOCK_STATUS [04:04] */
-#define BCHP_CLKGEN_TRIPLE_GENET_TOP_RGMII_INST_CLOCK_DISABLE_STATUS_DISABLE_GENET1_ALWAYSON_CLOCK_STATUS_MASK 0x00000010
-#define BCHP_CLKGEN_TRIPLE_GENET_TOP_RGMII_INST_CLOCK_DISABLE_STATUS_DISABLE_GENET1_ALWAYSON_CLOCK_STATUS_SHIFT 4
-
-/* CLKGEN :: TRIPLE_GENET_TOP_RGMII_INST_CLOCK_DISABLE_STATUS :: DISABLE_GENET0_SYSTEM_SLOW_CLOCK_STATUS [03:03] */
-#define BCHP_CLKGEN_TRIPLE_GENET_TOP_RGMII_INST_CLOCK_DISABLE_STATUS_DISABLE_GENET0_SYSTEM_SLOW_CLOCK_STATUS_MASK 0x00000008
-#define BCHP_CLKGEN_TRIPLE_GENET_TOP_RGMII_INST_CLOCK_DISABLE_STATUS_DISABLE_GENET0_SYSTEM_SLOW_CLOCK_STATUS_SHIFT 3
-
-/* CLKGEN :: TRIPLE_GENET_TOP_RGMII_INST_CLOCK_DISABLE_STATUS :: DISABLE_GENET0_SYSTEM_PM_CLOCK_STATUS [02:02] */
-#define BCHP_CLKGEN_TRIPLE_GENET_TOP_RGMII_INST_CLOCK_DISABLE_STATUS_DISABLE_GENET0_SYSTEM_PM_CLOCK_STATUS_MASK 0x00000004
-#define BCHP_CLKGEN_TRIPLE_GENET_TOP_RGMII_INST_CLOCK_DISABLE_STATUS_DISABLE_GENET0_SYSTEM_PM_CLOCK_STATUS_SHIFT 2
-
-/* CLKGEN :: TRIPLE_GENET_TOP_RGMII_INST_CLOCK_DISABLE_STATUS :: DISABLE_GENET0_SYSTEM_FAST_CLOCK_STATUS [01:01] */
-#define BCHP_CLKGEN_TRIPLE_GENET_TOP_RGMII_INST_CLOCK_DISABLE_STATUS_DISABLE_GENET0_SYSTEM_FAST_CLOCK_STATUS_MASK 0x00000002
-#define BCHP_CLKGEN_TRIPLE_GENET_TOP_RGMII_INST_CLOCK_DISABLE_STATUS_DISABLE_GENET0_SYSTEM_FAST_CLOCK_STATUS_SHIFT 1
-
-/* CLKGEN :: TRIPLE_GENET_TOP_RGMII_INST_CLOCK_DISABLE_STATUS :: DISABLE_GENET0_ALWAYSON_CLOCK_STATUS [00:00] */
-#define BCHP_CLKGEN_TRIPLE_GENET_TOP_RGMII_INST_CLOCK_DISABLE_STATUS_DISABLE_GENET0_ALWAYSON_CLOCK_STATUS_MASK 0x00000001
-#define BCHP_CLKGEN_TRIPLE_GENET_TOP_RGMII_INST_CLOCK_DISABLE_STATUS_DISABLE_GENET0_ALWAYSON_CLOCK_STATUS_SHIFT 0
-
-/***************************************************************************
- *TRIPLE_GENET_TOP_RGMII_INST_CLOCK_ENABLE - Triple genet top rgmii inst clock enable
- ***************************************************************************/
-/* CLKGEN :: TRIPLE_GENET_TOP_RGMII_INST_CLOCK_ENABLE :: reserved0 [31:02] */
-#define BCHP_CLKGEN_TRIPLE_GENET_TOP_RGMII_INST_CLOCK_ENABLE_reserved0_MASK 0xfffffffc
-#define BCHP_CLKGEN_TRIPLE_GENET_TOP_RGMII_INST_CLOCK_ENABLE_reserved0_SHIFT 2
-
-/* CLKGEN :: TRIPLE_GENET_TOP_RGMII_INST_CLOCK_ENABLE :: GENET_SCB_CLOCK_ENABLE [01:01] */
-#define BCHP_CLKGEN_TRIPLE_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET_SCB_CLOCK_ENABLE_MASK 0x00000002
-#define BCHP_CLKGEN_TRIPLE_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET_SCB_CLOCK_ENABLE_SHIFT 1
-#define BCHP_CLKGEN_TRIPLE_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET_SCB_CLOCK_ENABLE_DEFAULT 0x00000001
-
-/* CLKGEN :: TRIPLE_GENET_TOP_RGMII_INST_CLOCK_ENABLE :: GENET_54_CLOCK_ENABLE [00:00] */
-#define BCHP_CLKGEN_TRIPLE_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET_54_CLOCK_ENABLE_MASK 0x00000001
-#define BCHP_CLKGEN_TRIPLE_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET_54_CLOCK_ENABLE_SHIFT 0
-#define BCHP_CLKGEN_TRIPLE_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET_54_CLOCK_ENABLE_DEFAULT 0x00000001
-
-/***************************************************************************
- *TRIPLE_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET0 - Triple genet top rgmii inst clock enable genet0
- ***************************************************************************/
-/* CLKGEN :: TRIPLE_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET0 :: reserved0 [31:08] */
-#define BCHP_CLKGEN_TRIPLE_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET0_reserved0_MASK 0xffffff00
-#define BCHP_CLKGEN_TRIPLE_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET0_reserved0_SHIFT 8
-
-/* CLKGEN :: TRIPLE_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET0 :: GENET0_UNIMAC_SYS_TX_CLOCK_ENABLE_GENET0 [07:07] */
-#define BCHP_CLKGEN_TRIPLE_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET0_GENET0_UNIMAC_SYS_TX_CLOCK_ENABLE_GENET0_MASK 0x00000080
-#define BCHP_CLKGEN_TRIPLE_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET0_GENET0_UNIMAC_SYS_TX_CLOCK_ENABLE_GENET0_SHIFT 7
-#define BCHP_CLKGEN_TRIPLE_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET0_GENET0_UNIMAC_SYS_TX_CLOCK_ENABLE_GENET0_DEFAULT 0x00000001
-
-/* CLKGEN :: TRIPLE_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET0 :: GENET0_UNIMAC_SYS_RX_CLOCK_ENABLE_GENET0 [06:06] */
-#define BCHP_CLKGEN_TRIPLE_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET0_GENET0_UNIMAC_SYS_RX_CLOCK_ENABLE_GENET0_MASK 0x00000040
-#define BCHP_CLKGEN_TRIPLE_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET0_GENET0_UNIMAC_SYS_RX_CLOCK_ENABLE_GENET0_SHIFT 6
-#define BCHP_CLKGEN_TRIPLE_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET0_GENET0_UNIMAC_SYS_RX_CLOCK_ENABLE_GENET0_DEFAULT 0x00000001
-
-/* CLKGEN :: TRIPLE_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET0 :: GENET0_SCB_CLOCK_ENABLE_GENET0 [05:05] */
-#define BCHP_CLKGEN_TRIPLE_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET0_GENET0_SCB_CLOCK_ENABLE_GENET0_MASK 0x00000020
-#define BCHP_CLKGEN_TRIPLE_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET0_GENET0_SCB_CLOCK_ENABLE_GENET0_SHIFT 5
-#define BCHP_CLKGEN_TRIPLE_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET0_GENET0_SCB_CLOCK_ENABLE_GENET0_DEFAULT 0x00000001
-
-/* CLKGEN :: TRIPLE_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET0 :: GENET0_L2INTR_CLOCK_ENABLE_GENET0 [04:04] */
-#define BCHP_CLKGEN_TRIPLE_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET0_GENET0_L2INTR_CLOCK_ENABLE_GENET0_MASK 0x00000010
-#define BCHP_CLKGEN_TRIPLE_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET0_GENET0_L2INTR_CLOCK_ENABLE_GENET0_SHIFT 4
-#define BCHP_CLKGEN_TRIPLE_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET0_GENET0_L2INTR_CLOCK_ENABLE_GENET0_DEFAULT 0x00000001
-
-/* CLKGEN :: TRIPLE_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET0 :: GENET0_HFB_CLOCK_ENABLE_GENET0 [03:03] */
-#define BCHP_CLKGEN_TRIPLE_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET0_GENET0_HFB_CLOCK_ENABLE_GENET0_MASK 0x00000008
-#define BCHP_CLKGEN_TRIPLE_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET0_GENET0_HFB_CLOCK_ENABLE_GENET0_SHIFT 3
-#define BCHP_CLKGEN_TRIPLE_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET0_GENET0_HFB_CLOCK_ENABLE_GENET0_DEFAULT 0x00000001
-
-/* CLKGEN :: TRIPLE_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET0 :: GENET0_GMII_CLOCK_ENABLE_GENET0 [02:02] */
-#define BCHP_CLKGEN_TRIPLE_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET0_GENET0_GMII_CLOCK_ENABLE_GENET0_MASK 0x00000004
-#define BCHP_CLKGEN_TRIPLE_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET0_GENET0_GMII_CLOCK_ENABLE_GENET0_SHIFT 2
-#define BCHP_CLKGEN_TRIPLE_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET0_GENET0_GMII_CLOCK_ENABLE_GENET0_DEFAULT 0x00000001
-
-/* CLKGEN :: TRIPLE_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET0 :: GENET0_GISB_CLOCK_ENABLE_GENET0 [01:01] */
-#define BCHP_CLKGEN_TRIPLE_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET0_GENET0_GISB_CLOCK_ENABLE_GENET0_MASK 0x00000002
-#define BCHP_CLKGEN_TRIPLE_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET0_GENET0_GISB_CLOCK_ENABLE_GENET0_SHIFT 1
-#define BCHP_CLKGEN_TRIPLE_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET0_GENET0_GISB_CLOCK_ENABLE_GENET0_DEFAULT 0x00000001
-
-/* CLKGEN :: TRIPLE_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET0 :: GENET0_EEE_CLOCK_ENABLE_GENET0 [00:00] */
-#define BCHP_CLKGEN_TRIPLE_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET0_GENET0_EEE_CLOCK_ENABLE_GENET0_MASK 0x00000001
-#define BCHP_CLKGEN_TRIPLE_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET0_GENET0_EEE_CLOCK_ENABLE_GENET0_SHIFT 0
-#define BCHP_CLKGEN_TRIPLE_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET0_GENET0_EEE_CLOCK_ENABLE_GENET0_DEFAULT 0x00000001
-
-/***************************************************************************
- *TRIPLE_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET0_STATUS - Clock Enable Status
- ***************************************************************************/
-/* CLKGEN :: TRIPLE_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET0_STATUS :: reserved0 [31:08] */
-#define BCHP_CLKGEN_TRIPLE_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET0_STATUS_reserved0_MASK 0xffffff00
-#define BCHP_CLKGEN_TRIPLE_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET0_STATUS_reserved0_SHIFT 8
-
-/* CLKGEN :: TRIPLE_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET0_STATUS :: GENET0_UNIMAC_SYS_TX_CLOCK_ENABLE_GENET0_STATUS [07:07] */
-#define BCHP_CLKGEN_TRIPLE_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET0_STATUS_GENET0_UNIMAC_SYS_TX_CLOCK_ENABLE_GENET0_STATUS_MASK 0x00000080
-#define BCHP_CLKGEN_TRIPLE_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET0_STATUS_GENET0_UNIMAC_SYS_TX_CLOCK_ENABLE_GENET0_STATUS_SHIFT 7
-
-/* CLKGEN :: TRIPLE_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET0_STATUS :: GENET0_UNIMAC_SYS_RX_CLOCK_ENABLE_GENET0_STATUS [06:06] */
-#define BCHP_CLKGEN_TRIPLE_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET0_STATUS_GENET0_UNIMAC_SYS_RX_CLOCK_ENABLE_GENET0_STATUS_MASK 0x00000040
-#define BCHP_CLKGEN_TRIPLE_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET0_STATUS_GENET0_UNIMAC_SYS_RX_CLOCK_ENABLE_GENET0_STATUS_SHIFT 6
-
-/* CLKGEN :: TRIPLE_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET0_STATUS :: GENET0_SCB_CLOCK_ENABLE_GENET0_STATUS [05:05] */
-#define BCHP_CLKGEN_TRIPLE_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET0_STATUS_GENET0_SCB_CLOCK_ENABLE_GENET0_STATUS_MASK 0x00000020
-#define BCHP_CLKGEN_TRIPLE_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET0_STATUS_GENET0_SCB_CLOCK_ENABLE_GENET0_STATUS_SHIFT 5
-
-/* CLKGEN :: TRIPLE_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET0_STATUS :: GENET0_L2INTR_CLOCK_ENABLE_GENET0_STATUS [04:04] */
-#define BCHP_CLKGEN_TRIPLE_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET0_STATUS_GENET0_L2INTR_CLOCK_ENABLE_GENET0_STATUS_MASK 0x00000010
-#define BCHP_CLKGEN_TRIPLE_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET0_STATUS_GENET0_L2INTR_CLOCK_ENABLE_GENET0_STATUS_SHIFT 4
-
-/* CLKGEN :: TRIPLE_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET0_STATUS :: GENET0_HFB_CLOCK_ENABLE_GENET0_STATUS [03:03] */
-#define BCHP_CLKGEN_TRIPLE_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET0_STATUS_GENET0_HFB_CLOCK_ENABLE_GENET0_STATUS_MASK 0x00000008
-#define BCHP_CLKGEN_TRIPLE_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET0_STATUS_GENET0_HFB_CLOCK_ENABLE_GENET0_STATUS_SHIFT 3
-
-/* CLKGEN :: TRIPLE_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET0_STATUS :: GENET0_GMII_CLOCK_ENABLE_GENET0_STATUS [02:02] */
-#define BCHP_CLKGEN_TRIPLE_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET0_STATUS_GENET0_GMII_CLOCK_ENABLE_GENET0_STATUS_MASK 0x00000004
-#define BCHP_CLKGEN_TRIPLE_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET0_STATUS_GENET0_GMII_CLOCK_ENABLE_GENET0_STATUS_SHIFT 2
-
-/* CLKGEN :: TRIPLE_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET0_STATUS :: GENET0_GISB_CLOCK_ENABLE_GENET0_STATUS [01:01] */
-#define BCHP_CLKGEN_TRIPLE_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET0_STATUS_GENET0_GISB_CLOCK_ENABLE_GENET0_STATUS_MASK 0x00000002
-#define BCHP_CLKGEN_TRIPLE_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET0_STATUS_GENET0_GISB_CLOCK_ENABLE_GENET0_STATUS_SHIFT 1
-
-/* CLKGEN :: TRIPLE_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET0_STATUS :: GENET0_EEE_CLOCK_ENABLE_GENET0_STATUS [00:00] */
-#define BCHP_CLKGEN_TRIPLE_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET0_STATUS_GENET0_EEE_CLOCK_ENABLE_GENET0_STATUS_MASK 0x00000001
-#define BCHP_CLKGEN_TRIPLE_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET0_STATUS_GENET0_EEE_CLOCK_ENABLE_GENET0_STATUS_SHIFT 0
-
-/***************************************************************************
- *TRIPLE_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET1 - Triple genet top rgmii inst clock enable genet1
- ***************************************************************************/
-/* CLKGEN :: TRIPLE_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET1 :: reserved0 [31:09] */
-#define BCHP_CLKGEN_TRIPLE_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET1_reserved0_MASK 0xfffffe00
-#define BCHP_CLKGEN_TRIPLE_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET1_reserved0_SHIFT 9
-
-/* CLKGEN :: TRIPLE_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET1 :: GENET1_UNIMAC_SYS_TX_CLOCK_ENABLE_GENET1 [08:08] */
-#define BCHP_CLKGEN_TRIPLE_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET1_GENET1_UNIMAC_SYS_TX_CLOCK_ENABLE_GENET1_MASK 0x00000100
-#define BCHP_CLKGEN_TRIPLE_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET1_GENET1_UNIMAC_SYS_TX_CLOCK_ENABLE_GENET1_SHIFT 8
-#define BCHP_CLKGEN_TRIPLE_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET1_GENET1_UNIMAC_SYS_TX_CLOCK_ENABLE_GENET1_DEFAULT 0x00000001
-
-/* CLKGEN :: TRIPLE_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET1 :: GENET1_UNIMAC_SYS_RX_CLOCK_ENABLE_GENET1 [07:07] */
-#define BCHP_CLKGEN_TRIPLE_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET1_GENET1_UNIMAC_SYS_RX_CLOCK_ENABLE_GENET1_MASK 0x00000080
-#define BCHP_CLKGEN_TRIPLE_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET1_GENET1_UNIMAC_SYS_RX_CLOCK_ENABLE_GENET1_SHIFT 7
-#define BCHP_CLKGEN_TRIPLE_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET1_GENET1_UNIMAC_SYS_RX_CLOCK_ENABLE_GENET1_DEFAULT 0x00000001
-
-/* CLKGEN :: TRIPLE_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET1 :: GENET1_SCB_CLOCK_ENABLE_GENET1 [06:06] */
-#define BCHP_CLKGEN_TRIPLE_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET1_GENET1_SCB_CLOCK_ENABLE_GENET1_MASK 0x00000040
-#define BCHP_CLKGEN_TRIPLE_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET1_GENET1_SCB_CLOCK_ENABLE_GENET1_SHIFT 6
-#define BCHP_CLKGEN_TRIPLE_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET1_GENET1_SCB_CLOCK_ENABLE_GENET1_DEFAULT 0x00000001
-
-/* CLKGEN :: TRIPLE_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET1 :: GENET1_L2INTR_CLOCK_ENABLE_GENET1 [05:05] */
-#define BCHP_CLKGEN_TRIPLE_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET1_GENET1_L2INTR_CLOCK_ENABLE_GENET1_MASK 0x00000020
-#define BCHP_CLKGEN_TRIPLE_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET1_GENET1_L2INTR_CLOCK_ENABLE_GENET1_SHIFT 5
-#define BCHP_CLKGEN_TRIPLE_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET1_GENET1_L2INTR_CLOCK_ENABLE_GENET1_DEFAULT 0x00000001
-
-/* CLKGEN :: TRIPLE_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET1 :: GENET1_HFB_CLOCK_ENABLE_GENET1 [04:04] */
-#define BCHP_CLKGEN_TRIPLE_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET1_GENET1_HFB_CLOCK_ENABLE_GENET1_MASK 0x00000010
-#define BCHP_CLKGEN_TRIPLE_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET1_GENET1_HFB_CLOCK_ENABLE_GENET1_SHIFT 4
-#define BCHP_CLKGEN_TRIPLE_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET1_GENET1_HFB_CLOCK_ENABLE_GENET1_DEFAULT 0x00000001
-
-/* CLKGEN :: TRIPLE_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET1 :: GENET1_GMII_CLOCK_ENABLE_GENET1 [03:03] */
-#define BCHP_CLKGEN_TRIPLE_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET1_GENET1_GMII_CLOCK_ENABLE_GENET1_MASK 0x00000008
-#define BCHP_CLKGEN_TRIPLE_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET1_GENET1_GMII_CLOCK_ENABLE_GENET1_SHIFT 3
-#define BCHP_CLKGEN_TRIPLE_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET1_GENET1_GMII_CLOCK_ENABLE_GENET1_DEFAULT 0x00000001
-
-/* CLKGEN :: TRIPLE_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET1 :: GENET1_GISB_CLOCK_ENABLE_GENET1 [02:02] */
-#define BCHP_CLKGEN_TRIPLE_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET1_GENET1_GISB_CLOCK_ENABLE_GENET1_MASK 0x00000004
-#define BCHP_CLKGEN_TRIPLE_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET1_GENET1_GISB_CLOCK_ENABLE_GENET1_SHIFT 2
-#define BCHP_CLKGEN_TRIPLE_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET1_GENET1_GISB_CLOCK_ENABLE_GENET1_DEFAULT 0x00000001
-
-/* CLKGEN :: TRIPLE_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET1 :: GENET1_EEE_CLOCK_ENABLE_GENET1 [01:01] */
-#define BCHP_CLKGEN_TRIPLE_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET1_GENET1_EEE_CLOCK_ENABLE_GENET1_MASK 0x00000002
-#define BCHP_CLKGEN_TRIPLE_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET1_GENET1_EEE_CLOCK_ENABLE_GENET1_SHIFT 1
-#define BCHP_CLKGEN_TRIPLE_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET1_GENET1_EEE_CLOCK_ENABLE_GENET1_DEFAULT 0x00000001
-
-/* CLKGEN :: TRIPLE_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET1 :: GENET1_CLK_250_CLOCK_ENABLE_GENET1 [00:00] */
-#define BCHP_CLKGEN_TRIPLE_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET1_GENET1_CLK_250_CLOCK_ENABLE_GENET1_MASK 0x00000001
-#define BCHP_CLKGEN_TRIPLE_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET1_GENET1_CLK_250_CLOCK_ENABLE_GENET1_SHIFT 0
-#define BCHP_CLKGEN_TRIPLE_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET1_GENET1_CLK_250_CLOCK_ENABLE_GENET1_DEFAULT 0x00000001
-
-/***************************************************************************
- *TRIPLE_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET1_STATUS - Clock Enable Status
- ***************************************************************************/
-/* CLKGEN :: TRIPLE_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET1_STATUS :: reserved0 [31:09] */
-#define BCHP_CLKGEN_TRIPLE_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET1_STATUS_reserved0_MASK 0xfffffe00
-#define BCHP_CLKGEN_TRIPLE_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET1_STATUS_reserved0_SHIFT 9
-
-/* CLKGEN :: TRIPLE_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET1_STATUS :: GENET1_UNIMAC_SYS_TX_CLOCK_ENABLE_GENET1_STATUS [08:08] */
-#define BCHP_CLKGEN_TRIPLE_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET1_STATUS_GENET1_UNIMAC_SYS_TX_CLOCK_ENABLE_GENET1_STATUS_MASK 0x00000100
-#define BCHP_CLKGEN_TRIPLE_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET1_STATUS_GENET1_UNIMAC_SYS_TX_CLOCK_ENABLE_GENET1_STATUS_SHIFT 8
-
-/* CLKGEN :: TRIPLE_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET1_STATUS :: GENET1_UNIMAC_SYS_RX_CLOCK_ENABLE_GENET1_STATUS [07:07] */
-#define BCHP_CLKGEN_TRIPLE_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET1_STATUS_GENET1_UNIMAC_SYS_RX_CLOCK_ENABLE_GENET1_STATUS_MASK 0x00000080
-#define BCHP_CLKGEN_TRIPLE_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET1_STATUS_GENET1_UNIMAC_SYS_RX_CLOCK_ENABLE_GENET1_STATUS_SHIFT 7
-
-/* CLKGEN :: TRIPLE_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET1_STATUS :: GENET1_SCB_CLOCK_ENABLE_GENET1_STATUS [06:06] */
-#define BCHP_CLKGEN_TRIPLE_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET1_STATUS_GENET1_SCB_CLOCK_ENABLE_GENET1_STATUS_MASK 0x00000040
-#define BCHP_CLKGEN_TRIPLE_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET1_STATUS_GENET1_SCB_CLOCK_ENABLE_GENET1_STATUS_SHIFT 6
-
-/* CLKGEN :: TRIPLE_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET1_STATUS :: GENET1_L2INTR_CLOCK_ENABLE_GENET1_STATUS [05:05] */
-#define BCHP_CLKGEN_TRIPLE_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET1_STATUS_GENET1_L2INTR_CLOCK_ENABLE_GENET1_STATUS_MASK 0x00000020
-#define BCHP_CLKGEN_TRIPLE_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET1_STATUS_GENET1_L2INTR_CLOCK_ENABLE_GENET1_STATUS_SHIFT 5
-
-/* CLKGEN :: TRIPLE_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET1_STATUS :: GENET1_HFB_CLOCK_ENABLE_GENET1_STATUS [04:04] */
-#define BCHP_CLKGEN_TRIPLE_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET1_STATUS_GENET1_HFB_CLOCK_ENABLE_GENET1_STATUS_MASK 0x00000010
-#define BCHP_CLKGEN_TRIPLE_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET1_STATUS_GENET1_HFB_CLOCK_ENABLE_GENET1_STATUS_SHIFT 4
-
-/* CLKGEN :: TRIPLE_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET1_STATUS :: GENET1_GMII_CLOCK_ENABLE_GENET1_STATUS [03:03] */
-#define BCHP_CLKGEN_TRIPLE_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET1_STATUS_GENET1_GMII_CLOCK_ENABLE_GENET1_STATUS_MASK 0x00000008
-#define BCHP_CLKGEN_TRIPLE_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET1_STATUS_GENET1_GMII_CLOCK_ENABLE_GENET1_STATUS_SHIFT 3
-
-/* CLKGEN :: TRIPLE_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET1_STATUS :: GENET1_GISB_CLOCK_ENABLE_GENET1_STATUS [02:02] */
-#define BCHP_CLKGEN_TRIPLE_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET1_STATUS_GENET1_GISB_CLOCK_ENABLE_GENET1_STATUS_MASK 0x00000004
-#define BCHP_CLKGEN_TRIPLE_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET1_STATUS_GENET1_GISB_CLOCK_ENABLE_GENET1_STATUS_SHIFT 2
-
-/* CLKGEN :: TRIPLE_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET1_STATUS :: GENET1_EEE_CLOCK_ENABLE_GENET1_STATUS [01:01] */
-#define BCHP_CLKGEN_TRIPLE_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET1_STATUS_GENET1_EEE_CLOCK_ENABLE_GENET1_STATUS_MASK 0x00000002
-#define BCHP_CLKGEN_TRIPLE_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET1_STATUS_GENET1_EEE_CLOCK_ENABLE_GENET1_STATUS_SHIFT 1
-
-/* CLKGEN :: TRIPLE_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET1_STATUS :: GENET1_CLK_250_CLOCK_ENABLE_GENET1_STATUS [00:00] */
-#define BCHP_CLKGEN_TRIPLE_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET1_STATUS_GENET1_CLK_250_CLOCK_ENABLE_GENET1_STATUS_MASK 0x00000001
-#define BCHP_CLKGEN_TRIPLE_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET1_STATUS_GENET1_CLK_250_CLOCK_ENABLE_GENET1_STATUS_SHIFT 0
-
-/***************************************************************************
- *TRIPLE_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET2 - Triple genet top rgmii inst clock enable genet2
- ***************************************************************************/
-/* CLKGEN :: TRIPLE_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET2 :: reserved0 [31:09] */
-#define BCHP_CLKGEN_TRIPLE_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET2_reserved0_MASK 0xfffffe00
-#define BCHP_CLKGEN_TRIPLE_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET2_reserved0_SHIFT 9
-
-/* CLKGEN :: TRIPLE_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET2 :: GENET2_UNIMAC_SYS_TX_CLOCK_ENABLE_GENET2 [08:08] */
-#define BCHP_CLKGEN_TRIPLE_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET2_GENET2_UNIMAC_SYS_TX_CLOCK_ENABLE_GENET2_MASK 0x00000100
-#define BCHP_CLKGEN_TRIPLE_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET2_GENET2_UNIMAC_SYS_TX_CLOCK_ENABLE_GENET2_SHIFT 8
-#define BCHP_CLKGEN_TRIPLE_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET2_GENET2_UNIMAC_SYS_TX_CLOCK_ENABLE_GENET2_DEFAULT 0x00000001
-
-/* CLKGEN :: TRIPLE_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET2 :: GENET2_UNIMAC_SYS_RX_CLOCK_ENABLE_GENET2 [07:07] */
-#define BCHP_CLKGEN_TRIPLE_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET2_GENET2_UNIMAC_SYS_RX_CLOCK_ENABLE_GENET2_MASK 0x00000080
-#define BCHP_CLKGEN_TRIPLE_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET2_GENET2_UNIMAC_SYS_RX_CLOCK_ENABLE_GENET2_SHIFT 7
-#define BCHP_CLKGEN_TRIPLE_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET2_GENET2_UNIMAC_SYS_RX_CLOCK_ENABLE_GENET2_DEFAULT 0x00000001
-
-/* CLKGEN :: TRIPLE_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET2 :: GENET2_SCB_CLOCK_ENABLE_GENET2 [06:06] */
-#define BCHP_CLKGEN_TRIPLE_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET2_GENET2_SCB_CLOCK_ENABLE_GENET2_MASK 0x00000040
-#define BCHP_CLKGEN_TRIPLE_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET2_GENET2_SCB_CLOCK_ENABLE_GENET2_SHIFT 6
-#define BCHP_CLKGEN_TRIPLE_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET2_GENET2_SCB_CLOCK_ENABLE_GENET2_DEFAULT 0x00000001
-
-/* CLKGEN :: TRIPLE_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET2 :: GENET2_L2INTR_CLOCK_ENABLE_GENET2 [05:05] */
-#define BCHP_CLKGEN_TRIPLE_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET2_GENET2_L2INTR_CLOCK_ENABLE_GENET2_MASK 0x00000020
-#define BCHP_CLKGEN_TRIPLE_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET2_GENET2_L2INTR_CLOCK_ENABLE_GENET2_SHIFT 5
-#define BCHP_CLKGEN_TRIPLE_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET2_GENET2_L2INTR_CLOCK_ENABLE_GENET2_DEFAULT 0x00000001
-
-/* CLKGEN :: TRIPLE_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET2 :: GENET2_HFB_CLOCK_ENABLE_GENET2 [04:04] */
-#define BCHP_CLKGEN_TRIPLE_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET2_GENET2_HFB_CLOCK_ENABLE_GENET2_MASK 0x00000010
-#define BCHP_CLKGEN_TRIPLE_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET2_GENET2_HFB_CLOCK_ENABLE_GENET2_SHIFT 4
-#define BCHP_CLKGEN_TRIPLE_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET2_GENET2_HFB_CLOCK_ENABLE_GENET2_DEFAULT 0x00000001
-
-/* CLKGEN :: TRIPLE_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET2 :: GENET2_GMII_CLOCK_ENABLE_GENET2 [03:03] */
-#define BCHP_CLKGEN_TRIPLE_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET2_GENET2_GMII_CLOCK_ENABLE_GENET2_MASK 0x00000008
-#define BCHP_CLKGEN_TRIPLE_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET2_GENET2_GMII_CLOCK_ENABLE_GENET2_SHIFT 3
-#define BCHP_CLKGEN_TRIPLE_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET2_GENET2_GMII_CLOCK_ENABLE_GENET2_DEFAULT 0x00000001
-
-/* CLKGEN :: TRIPLE_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET2 :: GENET2_GISB_CLOCK_ENABLE_GENET2 [02:02] */
-#define BCHP_CLKGEN_TRIPLE_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET2_GENET2_GISB_CLOCK_ENABLE_GENET2_MASK 0x00000004
-#define BCHP_CLKGEN_TRIPLE_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET2_GENET2_GISB_CLOCK_ENABLE_GENET2_SHIFT 2
-#define BCHP_CLKGEN_TRIPLE_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET2_GENET2_GISB_CLOCK_ENABLE_GENET2_DEFAULT 0x00000001
-
-/* CLKGEN :: TRIPLE_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET2 :: GENET2_EEE_CLOCK_ENABLE_GENET2 [01:01] */
-#define BCHP_CLKGEN_TRIPLE_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET2_GENET2_EEE_CLOCK_ENABLE_GENET2_MASK 0x00000002
-#define BCHP_CLKGEN_TRIPLE_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET2_GENET2_EEE_CLOCK_ENABLE_GENET2_SHIFT 1
-#define BCHP_CLKGEN_TRIPLE_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET2_GENET2_EEE_CLOCK_ENABLE_GENET2_DEFAULT 0x00000001
-
-/* CLKGEN :: TRIPLE_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET2 :: GENET2_CLK_250_CLOCK_ENABLE_GENET2 [00:00] */
-#define BCHP_CLKGEN_TRIPLE_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET2_GENET2_CLK_250_CLOCK_ENABLE_GENET2_MASK 0x00000001
-#define BCHP_CLKGEN_TRIPLE_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET2_GENET2_CLK_250_CLOCK_ENABLE_GENET2_SHIFT 0
-#define BCHP_CLKGEN_TRIPLE_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET2_GENET2_CLK_250_CLOCK_ENABLE_GENET2_DEFAULT 0x00000001
-
-/***************************************************************************
- *TRIPLE_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET2_STATUS - Clock Enable Status
- ***************************************************************************/
-/* CLKGEN :: TRIPLE_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET2_STATUS :: reserved0 [31:09] */
-#define BCHP_CLKGEN_TRIPLE_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET2_STATUS_reserved0_MASK 0xfffffe00
-#define BCHP_CLKGEN_TRIPLE_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET2_STATUS_reserved0_SHIFT 9
-
-/* CLKGEN :: TRIPLE_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET2_STATUS :: GENET2_UNIMAC_SYS_TX_CLOCK_ENABLE_GENET2_STATUS [08:08] */
-#define BCHP_CLKGEN_TRIPLE_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET2_STATUS_GENET2_UNIMAC_SYS_TX_CLOCK_ENABLE_GENET2_STATUS_MASK 0x00000100
-#define BCHP_CLKGEN_TRIPLE_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET2_STATUS_GENET2_UNIMAC_SYS_TX_CLOCK_ENABLE_GENET2_STATUS_SHIFT 8
-
-/* CLKGEN :: TRIPLE_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET2_STATUS :: GENET2_UNIMAC_SYS_RX_CLOCK_ENABLE_GENET2_STATUS [07:07] */
-#define BCHP_CLKGEN_TRIPLE_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET2_STATUS_GENET2_UNIMAC_SYS_RX_CLOCK_ENABLE_GENET2_STATUS_MASK 0x00000080
-#define BCHP_CLKGEN_TRIPLE_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET2_STATUS_GENET2_UNIMAC_SYS_RX_CLOCK_ENABLE_GENET2_STATUS_SHIFT 7
-
-/* CLKGEN :: TRIPLE_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET2_STATUS :: GENET2_SCB_CLOCK_ENABLE_GENET2_STATUS [06:06] */
-#define BCHP_CLKGEN_TRIPLE_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET2_STATUS_GENET2_SCB_CLOCK_ENABLE_GENET2_STATUS_MASK 0x00000040
-#define BCHP_CLKGEN_TRIPLE_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET2_STATUS_GENET2_SCB_CLOCK_ENABLE_GENET2_STATUS_SHIFT 6
-
-/* CLKGEN :: TRIPLE_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET2_STATUS :: GENET2_L2INTR_CLOCK_ENABLE_GENET2_STATUS [05:05] */
-#define BCHP_CLKGEN_TRIPLE_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET2_STATUS_GENET2_L2INTR_CLOCK_ENABLE_GENET2_STATUS_MASK 0x00000020
-#define BCHP_CLKGEN_TRIPLE_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET2_STATUS_GENET2_L2INTR_CLOCK_ENABLE_GENET2_STATUS_SHIFT 5
-
-/* CLKGEN :: TRIPLE_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET2_STATUS :: GENET2_HFB_CLOCK_ENABLE_GENET2_STATUS [04:04] */
-#define BCHP_CLKGEN_TRIPLE_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET2_STATUS_GENET2_HFB_CLOCK_ENABLE_GENET2_STATUS_MASK 0x00000010
-#define BCHP_CLKGEN_TRIPLE_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET2_STATUS_GENET2_HFB_CLOCK_ENABLE_GENET2_STATUS_SHIFT 4
-
-/* CLKGEN :: TRIPLE_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET2_STATUS :: GENET2_GMII_CLOCK_ENABLE_GENET2_STATUS [03:03] */
-#define BCHP_CLKGEN_TRIPLE_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET2_STATUS_GENET2_GMII_CLOCK_ENABLE_GENET2_STATUS_MASK 0x00000008
-#define BCHP_CLKGEN_TRIPLE_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET2_STATUS_GENET2_GMII_CLOCK_ENABLE_GENET2_STATUS_SHIFT 3
-
-/* CLKGEN :: TRIPLE_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET2_STATUS :: GENET2_GISB_CLOCK_ENABLE_GENET2_STATUS [02:02] */
-#define BCHP_CLKGEN_TRIPLE_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET2_STATUS_GENET2_GISB_CLOCK_ENABLE_GENET2_STATUS_MASK 0x00000004
-#define BCHP_CLKGEN_TRIPLE_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET2_STATUS_GENET2_GISB_CLOCK_ENABLE_GENET2_STATUS_SHIFT 2
-
-/* CLKGEN :: TRIPLE_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET2_STATUS :: GENET2_EEE_CLOCK_ENABLE_GENET2_STATUS [01:01] */
-#define BCHP_CLKGEN_TRIPLE_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET2_STATUS_GENET2_EEE_CLOCK_ENABLE_GENET2_STATUS_MASK 0x00000002
-#define BCHP_CLKGEN_TRIPLE_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET2_STATUS_GENET2_EEE_CLOCK_ENABLE_GENET2_STATUS_SHIFT 1
-
-/* CLKGEN :: TRIPLE_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET2_STATUS :: GENET2_CLK_250_CLOCK_ENABLE_GENET2_STATUS [00:00] */
-#define BCHP_CLKGEN_TRIPLE_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET2_STATUS_GENET2_CLK_250_CLOCK_ENABLE_GENET2_STATUS_MASK 0x00000001
-#define BCHP_CLKGEN_TRIPLE_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET2_STATUS_GENET2_CLK_250_CLOCK_ENABLE_GENET2_STATUS_SHIFT 0
-
-/***************************************************************************
- *TRIPLE_GENET_TOP_RGMII_INST_CLOCK_ENABLE_STATUS - Clock Enable Status
- ***************************************************************************/
-/* CLKGEN :: TRIPLE_GENET_TOP_RGMII_INST_CLOCK_ENABLE_STATUS :: reserved0 [31:02] */
-#define BCHP_CLKGEN_TRIPLE_GENET_TOP_RGMII_INST_CLOCK_ENABLE_STATUS_reserved0_MASK 0xfffffffc
-#define BCHP_CLKGEN_TRIPLE_GENET_TOP_RGMII_INST_CLOCK_ENABLE_STATUS_reserved0_SHIFT 2
-
-/* CLKGEN :: TRIPLE_GENET_TOP_RGMII_INST_CLOCK_ENABLE_STATUS :: GENET_SCB_CLOCK_ENABLE_STATUS [01:01] */
-#define BCHP_CLKGEN_TRIPLE_GENET_TOP_RGMII_INST_CLOCK_ENABLE_STATUS_GENET_SCB_CLOCK_ENABLE_STATUS_MASK 0x00000002
-#define BCHP_CLKGEN_TRIPLE_GENET_TOP_RGMII_INST_CLOCK_ENABLE_STATUS_GENET_SCB_CLOCK_ENABLE_STATUS_SHIFT 1
-
-/* CLKGEN :: TRIPLE_GENET_TOP_RGMII_INST_CLOCK_ENABLE_STATUS :: GENET_54_CLOCK_ENABLE_STATUS [00:00] */
-#define BCHP_CLKGEN_TRIPLE_GENET_TOP_RGMII_INST_CLOCK_ENABLE_STATUS_GENET_54_CLOCK_ENABLE_STATUS_MASK 0x00000001
-#define BCHP_CLKGEN_TRIPLE_GENET_TOP_RGMII_INST_CLOCK_ENABLE_STATUS_GENET_54_CLOCK_ENABLE_STATUS_SHIFT 0
-
-/***************************************************************************
- *TRIPLE_GENET_TOP_RGMII_INST_CLOCK_SELECT_GENET0 - Triple genet top rgmii inst clock select genet0
- ***************************************************************************/
-/* CLKGEN :: TRIPLE_GENET_TOP_RGMII_INST_CLOCK_SELECT_GENET0 :: reserved0 [31:02] */
-#define BCHP_CLKGEN_TRIPLE_GENET_TOP_RGMII_INST_CLOCK_SELECT_GENET0_reserved0_MASK 0xfffffffc
-#define BCHP_CLKGEN_TRIPLE_GENET_TOP_RGMII_INST_CLOCK_SELECT_GENET0_reserved0_SHIFT 2
-
-/* CLKGEN :: TRIPLE_GENET_TOP_RGMII_INST_CLOCK_SELECT_GENET0 :: GENET0_GMII_CLOCK_SELECT_GENET0 [01:01] */
-#define BCHP_CLKGEN_TRIPLE_GENET_TOP_RGMII_INST_CLOCK_SELECT_GENET0_GENET0_GMII_CLOCK_SELECT_GENET0_MASK 0x00000002
-#define BCHP_CLKGEN_TRIPLE_GENET_TOP_RGMII_INST_CLOCK_SELECT_GENET0_GENET0_GMII_CLOCK_SELECT_GENET0_SHIFT 1
-#define BCHP_CLKGEN_TRIPLE_GENET_TOP_RGMII_INST_CLOCK_SELECT_GENET0_GENET0_GMII_CLOCK_SELECT_GENET0_DEFAULT 0x00000000
-
-/* CLKGEN :: TRIPLE_GENET_TOP_RGMII_INST_CLOCK_SELECT_GENET0 :: GENET0_CLOCK_SELECT_GENET0 [00:00] */
-#define BCHP_CLKGEN_TRIPLE_GENET_TOP_RGMII_INST_CLOCK_SELECT_GENET0_GENET0_CLOCK_SELECT_GENET0_MASK 0x00000001
-#define BCHP_CLKGEN_TRIPLE_GENET_TOP_RGMII_INST_CLOCK_SELECT_GENET0_GENET0_CLOCK_SELECT_GENET0_SHIFT 0
-#define BCHP_CLKGEN_TRIPLE_GENET_TOP_RGMII_INST_CLOCK_SELECT_GENET0_GENET0_CLOCK_SELECT_GENET0_DEFAULT 0x00000000
-
-/***************************************************************************
- *TRIPLE_GENET_TOP_RGMII_INST_CLOCK_SELECT_GENET1 - Triple genet top rgmii inst clock select genet1
- ***************************************************************************/
-/* CLKGEN :: TRIPLE_GENET_TOP_RGMII_INST_CLOCK_SELECT_GENET1 :: reserved0 [31:02] */
-#define BCHP_CLKGEN_TRIPLE_GENET_TOP_RGMII_INST_CLOCK_SELECT_GENET1_reserved0_MASK 0xfffffffc
-#define BCHP_CLKGEN_TRIPLE_GENET_TOP_RGMII_INST_CLOCK_SELECT_GENET1_reserved0_SHIFT 2
-
-/* CLKGEN :: TRIPLE_GENET_TOP_RGMII_INST_CLOCK_SELECT_GENET1 :: GENET1_GMII_CLOCK_SELECT_GENET1 [01:01] */
-#define BCHP_CLKGEN_TRIPLE_GENET_TOP_RGMII_INST_CLOCK_SELECT_GENET1_GENET1_GMII_CLOCK_SELECT_GENET1_MASK 0x00000002
-#define BCHP_CLKGEN_TRIPLE_GENET_TOP_RGMII_INST_CLOCK_SELECT_GENET1_GENET1_GMII_CLOCK_SELECT_GENET1_SHIFT 1
-#define BCHP_CLKGEN_TRIPLE_GENET_TOP_RGMII_INST_CLOCK_SELECT_GENET1_GENET1_GMII_CLOCK_SELECT_GENET1_DEFAULT 0x00000000
-
-/* CLKGEN :: TRIPLE_GENET_TOP_RGMII_INST_CLOCK_SELECT_GENET1 :: GENET1_CLOCK_SELECT_GENET1 [00:00] */
-#define BCHP_CLKGEN_TRIPLE_GENET_TOP_RGMII_INST_CLOCK_SELECT_GENET1_GENET1_CLOCK_SELECT_GENET1_MASK 0x00000001
-#define BCHP_CLKGEN_TRIPLE_GENET_TOP_RGMII_INST_CLOCK_SELECT_GENET1_GENET1_CLOCK_SELECT_GENET1_SHIFT 0
-#define BCHP_CLKGEN_TRIPLE_GENET_TOP_RGMII_INST_CLOCK_SELECT_GENET1_GENET1_CLOCK_SELECT_GENET1_DEFAULT 0x00000000
-
-/***************************************************************************
- *TRIPLE_GENET_TOP_RGMII_INST_CLOCK_SELECT_GENET2 - Triple genet top rgmii inst clock select genet2
- ***************************************************************************/
-/* CLKGEN :: TRIPLE_GENET_TOP_RGMII_INST_CLOCK_SELECT_GENET2 :: reserved0 [31:02] */
-#define BCHP_CLKGEN_TRIPLE_GENET_TOP_RGMII_INST_CLOCK_SELECT_GENET2_reserved0_MASK 0xfffffffc
-#define BCHP_CLKGEN_TRIPLE_GENET_TOP_RGMII_INST_CLOCK_SELECT_GENET2_reserved0_SHIFT 2
-
-/* CLKGEN :: TRIPLE_GENET_TOP_RGMII_INST_CLOCK_SELECT_GENET2 :: GENET2_GMII_CLOCK_SELECT_GENET2 [01:01] */
-#define BCHP_CLKGEN_TRIPLE_GENET_TOP_RGMII_INST_CLOCK_SELECT_GENET2_GENET2_GMII_CLOCK_SELECT_GENET2_MASK 0x00000002
-#define BCHP_CLKGEN_TRIPLE_GENET_TOP_RGMII_INST_CLOCK_SELECT_GENET2_GENET2_GMII_CLOCK_SELECT_GENET2_SHIFT 1
-#define BCHP_CLKGEN_TRIPLE_GENET_TOP_RGMII_INST_CLOCK_SELECT_GENET2_GENET2_GMII_CLOCK_SELECT_GENET2_DEFAULT 0x00000000
-
-/* CLKGEN :: TRIPLE_GENET_TOP_RGMII_INST_CLOCK_SELECT_GENET2 :: GENET2_CLOCK_SELECT_GENET2 [00:00] */
-#define BCHP_CLKGEN_TRIPLE_GENET_TOP_RGMII_INST_CLOCK_SELECT_GENET2_GENET2_CLOCK_SELECT_GENET2_MASK 0x00000001
-#define BCHP_CLKGEN_TRIPLE_GENET_TOP_RGMII_INST_CLOCK_SELECT_GENET2_GENET2_CLOCK_SELECT_GENET2_SHIFT 0
-#define BCHP_CLKGEN_TRIPLE_GENET_TOP_RGMII_INST_CLOCK_SELECT_GENET2_GENET2_CLOCK_SELECT_GENET2_DEFAULT 0x00000000
-
-/***************************************************************************
- *TRIPLE_GENET_TOP_RGMII_INST_OBSERVE_CLOCK - Triple genet top rgmii inst observe clock
- ***************************************************************************/
-/* CLKGEN :: TRIPLE_GENET_TOP_RGMII_INST_OBSERVE_CLOCK :: reserved0 [31:06] */
-#define BCHP_CLKGEN_TRIPLE_GENET_TOP_RGMII_INST_OBSERVE_CLOCK_reserved0_MASK 0xffffffc0
-#define BCHP_CLKGEN_TRIPLE_GENET_TOP_RGMII_INST_OBSERVE_CLOCK_reserved0_SHIFT 6
-
-/* CLKGEN :: TRIPLE_GENET_TOP_RGMII_INST_OBSERVE_CLOCK :: GENET_ENABLE_OBSERVE_CLOCK [05:05] */
-#define BCHP_CLKGEN_TRIPLE_GENET_TOP_RGMII_INST_OBSERVE_CLOCK_GENET_ENABLE_OBSERVE_CLOCK_MASK 0x00000020
-#define BCHP_CLKGEN_TRIPLE_GENET_TOP_RGMII_INST_OBSERVE_CLOCK_GENET_ENABLE_OBSERVE_CLOCK_SHIFT 5
-#define BCHP_CLKGEN_TRIPLE_GENET_TOP_RGMII_INST_OBSERVE_CLOCK_GENET_ENABLE_OBSERVE_CLOCK_DEFAULT 0x00000000
-
-/* CLKGEN :: TRIPLE_GENET_TOP_RGMII_INST_OBSERVE_CLOCK :: GENET_ENABLE_DIVIDER_OBSERVE_CLOCK [04:04] */
-#define BCHP_CLKGEN_TRIPLE_GENET_TOP_RGMII_INST_OBSERVE_CLOCK_GENET_ENABLE_DIVIDER_OBSERVE_CLOCK_MASK 0x00000010
-#define BCHP_CLKGEN_TRIPLE_GENET_TOP_RGMII_INST_OBSERVE_CLOCK_GENET_ENABLE_DIVIDER_OBSERVE_CLOCK_SHIFT 4
-#define BCHP_CLKGEN_TRIPLE_GENET_TOP_RGMII_INST_OBSERVE_CLOCK_GENET_ENABLE_DIVIDER_OBSERVE_CLOCK_DEFAULT 0x00000000
-
-/* CLKGEN :: TRIPLE_GENET_TOP_RGMII_INST_OBSERVE_CLOCK :: GENET_CONTROL_OBSERVE_CLOCK [03:00] */
-#define BCHP_CLKGEN_TRIPLE_GENET_TOP_RGMII_INST_OBSERVE_CLOCK_GENET_CONTROL_OBSERVE_CLOCK_MASK 0x0000000f
-#define BCHP_CLKGEN_TRIPLE_GENET_TOP_RGMII_INST_OBSERVE_CLOCK_GENET_CONTROL_OBSERVE_CLOCK_SHIFT 0
-#define BCHP_CLKGEN_TRIPLE_GENET_TOP_RGMII_INST_OBSERVE_CLOCK_GENET_CONTROL_OBSERVE_CLOCK_DEFAULT 0x00000000
-
-/***************************************************************************
- *USB0_TOP_INST_CKTAPSEL - Usb0 top inst cktapsel
- ***************************************************************************/
-/* CLKGEN :: USB0_TOP_INST_CKTAPSEL :: reserved0 [31:12] */
-#define BCHP_CLKGEN_USB0_TOP_INST_CKTAPSEL_reserved0_MASK 0xfffff000
-#define BCHP_CLKGEN_USB0_TOP_INST_CKTAPSEL_reserved0_SHIFT 12
-
-/* CLKGEN :: USB0_TOP_INST_CKTAPSEL :: SCB_CKTAP1_CKTAPSEL [11:06] */
-#define BCHP_CLKGEN_USB0_TOP_INST_CKTAPSEL_SCB_CKTAP1_CKTAPSEL_MASK 0x00000fc0
-#define BCHP_CLKGEN_USB0_TOP_INST_CKTAPSEL_SCB_CKTAP1_CKTAPSEL_SHIFT 6
-#define BCHP_CLKGEN_USB0_TOP_INST_CKTAPSEL_SCB_CKTAP1_CKTAPSEL_DEFAULT 0x00000000
-
-/* CLKGEN :: USB0_TOP_INST_CKTAPSEL :: SCB_CKTAP0_CKTAPSEL [05:00] */
-#define BCHP_CLKGEN_USB0_TOP_INST_CKTAPSEL_SCB_CKTAP0_CKTAPSEL_MASK 0x0000003f
-#define BCHP_CLKGEN_USB0_TOP_INST_CKTAPSEL_SCB_CKTAP0_CKTAPSEL_SHIFT 0
-#define BCHP_CLKGEN_USB0_TOP_INST_CKTAPSEL_SCB_CKTAP0_CKTAPSEL_DEFAULT 0x00000000
-
-/***************************************************************************
- *USB0_TOP_INST_CLOCK_ENABLE - Usb0 top inst clock enable
- ***************************************************************************/
-/* CLKGEN :: USB0_TOP_INST_CLOCK_ENABLE :: reserved0 [31:03] */
-#define BCHP_CLKGEN_USB0_TOP_INST_CLOCK_ENABLE_reserved0_MASK 0xfffffff8
-#define BCHP_CLKGEN_USB0_TOP_INST_CLOCK_ENABLE_reserved0_SHIFT 3
-
-/* CLKGEN :: USB0_TOP_INST_CLOCK_ENABLE :: USB0_SCB_CLOCK_ENABLE [02:02] */
-#define BCHP_CLKGEN_USB0_TOP_INST_CLOCK_ENABLE_USB0_SCB_CLOCK_ENABLE_MASK 0x00000004
-#define BCHP_CLKGEN_USB0_TOP_INST_CLOCK_ENABLE_USB0_SCB_CLOCK_ENABLE_SHIFT 2
-#define BCHP_CLKGEN_USB0_TOP_INST_CLOCK_ENABLE_USB0_SCB_CLOCK_ENABLE_DEFAULT 0x00000001
-
-/* CLKGEN :: USB0_TOP_INST_CLOCK_ENABLE :: USB0_GISB_CLOCK_ENABLE [01:01] */
-#define BCHP_CLKGEN_USB0_TOP_INST_CLOCK_ENABLE_USB0_GISB_CLOCK_ENABLE_MASK 0x00000002
-#define BCHP_CLKGEN_USB0_TOP_INST_CLOCK_ENABLE_USB0_GISB_CLOCK_ENABLE_SHIFT 1
-#define BCHP_CLKGEN_USB0_TOP_INST_CLOCK_ENABLE_USB0_GISB_CLOCK_ENABLE_DEFAULT 0x00000001
-
-/* CLKGEN :: USB0_TOP_INST_CLOCK_ENABLE :: USB0_54_CLOCK_ENABLE [00:00] */
-#define BCHP_CLKGEN_USB0_TOP_INST_CLOCK_ENABLE_USB0_54_CLOCK_ENABLE_MASK 0x00000001
-#define BCHP_CLKGEN_USB0_TOP_INST_CLOCK_ENABLE_USB0_54_CLOCK_ENABLE_SHIFT 0
-#define BCHP_CLKGEN_USB0_TOP_INST_CLOCK_ENABLE_USB0_54_CLOCK_ENABLE_DEFAULT 0x00000001
-
-/***************************************************************************
- *USB0_TOP_INST_CLOCK_ENABLE_AHB - Usb0 top inst clock enable ahb
- ***************************************************************************/
-/* CLKGEN :: USB0_TOP_INST_CLOCK_ENABLE_AHB :: reserved0 [31:01] */
-#define BCHP_CLKGEN_USB0_TOP_INST_CLOCK_ENABLE_AHB_reserved0_MASK 0xfffffffe
-#define BCHP_CLKGEN_USB0_TOP_INST_CLOCK_ENABLE_AHB_reserved0_SHIFT 1
-
-/* CLKGEN :: USB0_TOP_INST_CLOCK_ENABLE_AHB :: USB0_108_CLOCK_ENABLE_AHB [00:00] */
-#define BCHP_CLKGEN_USB0_TOP_INST_CLOCK_ENABLE_AHB_USB0_108_CLOCK_ENABLE_AHB_MASK 0x00000001
-#define BCHP_CLKGEN_USB0_TOP_INST_CLOCK_ENABLE_AHB_USB0_108_CLOCK_ENABLE_AHB_SHIFT 0
-#define BCHP_CLKGEN_USB0_TOP_INST_CLOCK_ENABLE_AHB_USB0_108_CLOCK_ENABLE_AHB_DEFAULT 0x00000001
-
-/***************************************************************************
- *USB0_TOP_INST_CLOCK_ENABLE_AHB_STATUS - Clock Enable Status
- ***************************************************************************/
-/* CLKGEN :: USB0_TOP_INST_CLOCK_ENABLE_AHB_STATUS :: reserved0 [31:01] */
-#define BCHP_CLKGEN_USB0_TOP_INST_CLOCK_ENABLE_AHB_STATUS_reserved0_MASK 0xfffffffe
-#define BCHP_CLKGEN_USB0_TOP_INST_CLOCK_ENABLE_AHB_STATUS_reserved0_SHIFT 1
-
-/* CLKGEN :: USB0_TOP_INST_CLOCK_ENABLE_AHB_STATUS :: USB0_108_CLOCK_ENABLE_AHB_STATUS [00:00] */
-#define BCHP_CLKGEN_USB0_TOP_INST_CLOCK_ENABLE_AHB_STATUS_USB0_108_CLOCK_ENABLE_AHB_STATUS_MASK 0x00000001
-#define BCHP_CLKGEN_USB0_TOP_INST_CLOCK_ENABLE_AHB_STATUS_USB0_108_CLOCK_ENABLE_AHB_STATUS_SHIFT 0
-
-/***************************************************************************
- *USB0_TOP_INST_CLOCK_ENABLE_AXI - Usb0 top inst clock enable axi
- ***************************************************************************/
-/* CLKGEN :: USB0_TOP_INST_CLOCK_ENABLE_AXI :: reserved0 [31:01] */
-#define BCHP_CLKGEN_USB0_TOP_INST_CLOCK_ENABLE_AXI_reserved0_MASK 0xfffffffe
-#define BCHP_CLKGEN_USB0_TOP_INST_CLOCK_ENABLE_AXI_reserved0_SHIFT 1
-
-/* CLKGEN :: USB0_TOP_INST_CLOCK_ENABLE_AXI :: USB0_108_CLOCK_ENABLE_AXI [00:00] */
-#define BCHP_CLKGEN_USB0_TOP_INST_CLOCK_ENABLE_AXI_USB0_108_CLOCK_ENABLE_AXI_MASK 0x00000001
-#define BCHP_CLKGEN_USB0_TOP_INST_CLOCK_ENABLE_AXI_USB0_108_CLOCK_ENABLE_AXI_SHIFT 0
-#define BCHP_CLKGEN_USB0_TOP_INST_CLOCK_ENABLE_AXI_USB0_108_CLOCK_ENABLE_AXI_DEFAULT 0x00000001
-
-/***************************************************************************
- *USB0_TOP_INST_CLOCK_ENABLE_AXI_STATUS - Clock Enable Status
- ***************************************************************************/
-/* CLKGEN :: USB0_TOP_INST_CLOCK_ENABLE_AXI_STATUS :: reserved0 [31:01] */
-#define BCHP_CLKGEN_USB0_TOP_INST_CLOCK_ENABLE_AXI_STATUS_reserved0_MASK 0xfffffffe
-#define BCHP_CLKGEN_USB0_TOP_INST_CLOCK_ENABLE_AXI_STATUS_reserved0_SHIFT 1
-
-/* CLKGEN :: USB0_TOP_INST_CLOCK_ENABLE_AXI_STATUS :: USB0_108_CLOCK_ENABLE_AXI_STATUS [00:00] */
-#define BCHP_CLKGEN_USB0_TOP_INST_CLOCK_ENABLE_AXI_STATUS_USB0_108_CLOCK_ENABLE_AXI_STATUS_MASK 0x00000001
-#define BCHP_CLKGEN_USB0_TOP_INST_CLOCK_ENABLE_AXI_STATUS_USB0_108_CLOCK_ENABLE_AXI_STATUS_SHIFT 0
-
-/***************************************************************************
- *USB0_TOP_INST_CLOCK_ENABLE_STATUS - Clock Enable Status
- ***************************************************************************/
-/* CLKGEN :: USB0_TOP_INST_CLOCK_ENABLE_STATUS :: reserved0 [31:03] */
-#define BCHP_CLKGEN_USB0_TOP_INST_CLOCK_ENABLE_STATUS_reserved0_MASK 0xfffffff8
-#define BCHP_CLKGEN_USB0_TOP_INST_CLOCK_ENABLE_STATUS_reserved0_SHIFT 3
-
-/* CLKGEN :: USB0_TOP_INST_CLOCK_ENABLE_STATUS :: USB0_SCB_CLOCK_ENABLE_STATUS [02:02] */
-#define BCHP_CLKGEN_USB0_TOP_INST_CLOCK_ENABLE_STATUS_USB0_SCB_CLOCK_ENABLE_STATUS_MASK 0x00000004
-#define BCHP_CLKGEN_USB0_TOP_INST_CLOCK_ENABLE_STATUS_USB0_SCB_CLOCK_ENABLE_STATUS_SHIFT 2
-
-/* CLKGEN :: USB0_TOP_INST_CLOCK_ENABLE_STATUS :: USB0_GISB_CLOCK_ENABLE_STATUS [01:01] */
-#define BCHP_CLKGEN_USB0_TOP_INST_CLOCK_ENABLE_STATUS_USB0_GISB_CLOCK_ENABLE_STATUS_MASK 0x00000002
-#define BCHP_CLKGEN_USB0_TOP_INST_CLOCK_ENABLE_STATUS_USB0_GISB_CLOCK_ENABLE_STATUS_SHIFT 1
-
-/* CLKGEN :: USB0_TOP_INST_CLOCK_ENABLE_STATUS :: USB0_54_CLOCK_ENABLE_STATUS [00:00] */
-#define BCHP_CLKGEN_USB0_TOP_INST_CLOCK_ENABLE_STATUS_USB0_54_CLOCK_ENABLE_STATUS_MASK 0x00000001
-#define BCHP_CLKGEN_USB0_TOP_INST_CLOCK_ENABLE_STATUS_USB0_54_CLOCK_ENABLE_STATUS_SHIFT 0
-
-/***************************************************************************
- *USB0_TOP_INST_OBSERVE_CLOCK - Usb0 top inst observe clock
- ***************************************************************************/
-/* CLKGEN :: USB0_TOP_INST_OBSERVE_CLOCK :: reserved0 [31:06] */
-#define BCHP_CLKGEN_USB0_TOP_INST_OBSERVE_CLOCK_reserved0_MASK 0xffffffc0
-#define BCHP_CLKGEN_USB0_TOP_INST_OBSERVE_CLOCK_reserved0_SHIFT 6
-
-/* CLKGEN :: USB0_TOP_INST_OBSERVE_CLOCK :: USB0_ENABLE_OBSERVE_CLOCK [05:05] */
-#define BCHP_CLKGEN_USB0_TOP_INST_OBSERVE_CLOCK_USB0_ENABLE_OBSERVE_CLOCK_MASK 0x00000020
-#define BCHP_CLKGEN_USB0_TOP_INST_OBSERVE_CLOCK_USB0_ENABLE_OBSERVE_CLOCK_SHIFT 5
-#define BCHP_CLKGEN_USB0_TOP_INST_OBSERVE_CLOCK_USB0_ENABLE_OBSERVE_CLOCK_DEFAULT 0x00000000
-
-/* CLKGEN :: USB0_TOP_INST_OBSERVE_CLOCK :: USB0_ENABLE_DIVIDER_OBSERVE_CLOCK [04:04] */
-#define BCHP_CLKGEN_USB0_TOP_INST_OBSERVE_CLOCK_USB0_ENABLE_DIVIDER_OBSERVE_CLOCK_MASK 0x00000010
-#define BCHP_CLKGEN_USB0_TOP_INST_OBSERVE_CLOCK_USB0_ENABLE_DIVIDER_OBSERVE_CLOCK_SHIFT 4
-#define BCHP_CLKGEN_USB0_TOP_INST_OBSERVE_CLOCK_USB0_ENABLE_DIVIDER_OBSERVE_CLOCK_DEFAULT 0x00000000
-
-/* CLKGEN :: USB0_TOP_INST_OBSERVE_CLOCK :: USB0_CONTROL_OBSERVE_CLOCK [03:00] */
-#define BCHP_CLKGEN_USB0_TOP_INST_OBSERVE_CLOCK_USB0_CONTROL_OBSERVE_CLOCK_MASK 0x0000000f
-#define BCHP_CLKGEN_USB0_TOP_INST_OBSERVE_CLOCK_USB0_CONTROL_OBSERVE_CLOCK_SHIFT 0
-#define BCHP_CLKGEN_USB0_TOP_INST_OBSERVE_CLOCK_USB0_CONTROL_OBSERVE_CLOCK_DEFAULT 0x00000000
-
-/***************************************************************************
- *USB1_TOP_INST_CKTAPSEL - Usb1 top inst cktapsel
- ***************************************************************************/
-/* CLKGEN :: USB1_TOP_INST_CKTAPSEL :: reserved0 [31:12] */
-#define BCHP_CLKGEN_USB1_TOP_INST_CKTAPSEL_reserved0_MASK 0xfffff000
-#define BCHP_CLKGEN_USB1_TOP_INST_CKTAPSEL_reserved0_SHIFT 12
-
-/* CLKGEN :: USB1_TOP_INST_CKTAPSEL :: SCB_CKTAP1_CKTAPSEL [11:06] */
-#define BCHP_CLKGEN_USB1_TOP_INST_CKTAPSEL_SCB_CKTAP1_CKTAPSEL_MASK 0x00000fc0
-#define BCHP_CLKGEN_USB1_TOP_INST_CKTAPSEL_SCB_CKTAP1_CKTAPSEL_SHIFT 6
-#define BCHP_CLKGEN_USB1_TOP_INST_CKTAPSEL_SCB_CKTAP1_CKTAPSEL_DEFAULT 0x00000000
-
-/* CLKGEN :: USB1_TOP_INST_CKTAPSEL :: SCB_CKTAP0_CKTAPSEL [05:00] */
-#define BCHP_CLKGEN_USB1_TOP_INST_CKTAPSEL_SCB_CKTAP0_CKTAPSEL_MASK 0x0000003f
-#define BCHP_CLKGEN_USB1_TOP_INST_CKTAPSEL_SCB_CKTAP0_CKTAPSEL_SHIFT 0
-#define BCHP_CLKGEN_USB1_TOP_INST_CKTAPSEL_SCB_CKTAP0_CKTAPSEL_DEFAULT 0x00000000
-
-/***************************************************************************
- *USB1_TOP_INST_CLOCK_ENABLE - Usb1 top inst clock enable
- ***************************************************************************/
-/* CLKGEN :: USB1_TOP_INST_CLOCK_ENABLE :: reserved0 [31:03] */
-#define BCHP_CLKGEN_USB1_TOP_INST_CLOCK_ENABLE_reserved0_MASK 0xfffffff8
-#define BCHP_CLKGEN_USB1_TOP_INST_CLOCK_ENABLE_reserved0_SHIFT 3
-
-/* CLKGEN :: USB1_TOP_INST_CLOCK_ENABLE :: USB1_SCB_CLOCK_ENABLE [02:02] */
-#define BCHP_CLKGEN_USB1_TOP_INST_CLOCK_ENABLE_USB1_SCB_CLOCK_ENABLE_MASK 0x00000004
-#define BCHP_CLKGEN_USB1_TOP_INST_CLOCK_ENABLE_USB1_SCB_CLOCK_ENABLE_SHIFT 2
-#define BCHP_CLKGEN_USB1_TOP_INST_CLOCK_ENABLE_USB1_SCB_CLOCK_ENABLE_DEFAULT 0x00000001
-
-/* CLKGEN :: USB1_TOP_INST_CLOCK_ENABLE :: USB1_GISB_CLOCK_ENABLE [01:01] */
-#define BCHP_CLKGEN_USB1_TOP_INST_CLOCK_ENABLE_USB1_GISB_CLOCK_ENABLE_MASK 0x00000002
-#define BCHP_CLKGEN_USB1_TOP_INST_CLOCK_ENABLE_USB1_GISB_CLOCK_ENABLE_SHIFT 1
-#define BCHP_CLKGEN_USB1_TOP_INST_CLOCK_ENABLE_USB1_GISB_CLOCK_ENABLE_DEFAULT 0x00000001
-
-/* CLKGEN :: USB1_TOP_INST_CLOCK_ENABLE :: USB1_54_CLOCK_ENABLE [00:00] */
-#define BCHP_CLKGEN_USB1_TOP_INST_CLOCK_ENABLE_USB1_54_CLOCK_ENABLE_MASK 0x00000001
-#define BCHP_CLKGEN_USB1_TOP_INST_CLOCK_ENABLE_USB1_54_CLOCK_ENABLE_SHIFT 0
-#define BCHP_CLKGEN_USB1_TOP_INST_CLOCK_ENABLE_USB1_54_CLOCK_ENABLE_DEFAULT 0x00000001
-
-/***************************************************************************
- *USB1_TOP_INST_CLOCK_ENABLE_AHB - Usb1 top inst clock enable ahb
- ***************************************************************************/
-/* CLKGEN :: USB1_TOP_INST_CLOCK_ENABLE_AHB :: reserved0 [31:01] */
-#define BCHP_CLKGEN_USB1_TOP_INST_CLOCK_ENABLE_AHB_reserved0_MASK 0xfffffffe
-#define BCHP_CLKGEN_USB1_TOP_INST_CLOCK_ENABLE_AHB_reserved0_SHIFT 1
-
-/* CLKGEN :: USB1_TOP_INST_CLOCK_ENABLE_AHB :: USB1_108_CLOCK_ENABLE_AHB [00:00] */
-#define BCHP_CLKGEN_USB1_TOP_INST_CLOCK_ENABLE_AHB_USB1_108_CLOCK_ENABLE_AHB_MASK 0x00000001
-#define BCHP_CLKGEN_USB1_TOP_INST_CLOCK_ENABLE_AHB_USB1_108_CLOCK_ENABLE_AHB_SHIFT 0
-#define BCHP_CLKGEN_USB1_TOP_INST_CLOCK_ENABLE_AHB_USB1_108_CLOCK_ENABLE_AHB_DEFAULT 0x00000001
-
-/***************************************************************************
- *USB1_TOP_INST_CLOCK_ENABLE_AHB_STATUS - Clock Enable Status
- ***************************************************************************/
-/* CLKGEN :: USB1_TOP_INST_CLOCK_ENABLE_AHB_STATUS :: reserved0 [31:01] */
-#define BCHP_CLKGEN_USB1_TOP_INST_CLOCK_ENABLE_AHB_STATUS_reserved0_MASK 0xfffffffe
-#define BCHP_CLKGEN_USB1_TOP_INST_CLOCK_ENABLE_AHB_STATUS_reserved0_SHIFT 1
-
-/* CLKGEN :: USB1_TOP_INST_CLOCK_ENABLE_AHB_STATUS :: USB1_108_CLOCK_ENABLE_AHB_STATUS [00:00] */
-#define BCHP_CLKGEN_USB1_TOP_INST_CLOCK_ENABLE_AHB_STATUS_USB1_108_CLOCK_ENABLE_AHB_STATUS_MASK 0x00000001
-#define BCHP_CLKGEN_USB1_TOP_INST_CLOCK_ENABLE_AHB_STATUS_USB1_108_CLOCK_ENABLE_AHB_STATUS_SHIFT 0
-
-/***************************************************************************
- *USB1_TOP_INST_CLOCK_ENABLE_AXI - Usb1 top inst clock enable axi
- ***************************************************************************/
-/* CLKGEN :: USB1_TOP_INST_CLOCK_ENABLE_AXI :: reserved0 [31:01] */
-#define BCHP_CLKGEN_USB1_TOP_INST_CLOCK_ENABLE_AXI_reserved0_MASK 0xfffffffe
-#define BCHP_CLKGEN_USB1_TOP_INST_CLOCK_ENABLE_AXI_reserved0_SHIFT 1
-
-/* CLKGEN :: USB1_TOP_INST_CLOCK_ENABLE_AXI :: USB1_108_CLOCK_ENABLE_AXI [00:00] */
-#define BCHP_CLKGEN_USB1_TOP_INST_CLOCK_ENABLE_AXI_USB1_108_CLOCK_ENABLE_AXI_MASK 0x00000001
-#define BCHP_CLKGEN_USB1_TOP_INST_CLOCK_ENABLE_AXI_USB1_108_CLOCK_ENABLE_AXI_SHIFT 0
-#define BCHP_CLKGEN_USB1_TOP_INST_CLOCK_ENABLE_AXI_USB1_108_CLOCK_ENABLE_AXI_DEFAULT 0x00000001
-
-/***************************************************************************
- *USB1_TOP_INST_CLOCK_ENABLE_AXI_STATUS - Clock Enable Status
- ***************************************************************************/
-/* CLKGEN :: USB1_TOP_INST_CLOCK_ENABLE_AXI_STATUS :: reserved0 [31:01] */
-#define BCHP_CLKGEN_USB1_TOP_INST_CLOCK_ENABLE_AXI_STATUS_reserved0_MASK 0xfffffffe
-#define BCHP_CLKGEN_USB1_TOP_INST_CLOCK_ENABLE_AXI_STATUS_reserved0_SHIFT 1
-
-/* CLKGEN :: USB1_TOP_INST_CLOCK_ENABLE_AXI_STATUS :: USB1_108_CLOCK_ENABLE_AXI_STATUS [00:00] */
-#define BCHP_CLKGEN_USB1_TOP_INST_CLOCK_ENABLE_AXI_STATUS_USB1_108_CLOCK_ENABLE_AXI_STATUS_MASK 0x00000001
-#define BCHP_CLKGEN_USB1_TOP_INST_CLOCK_ENABLE_AXI_STATUS_USB1_108_CLOCK_ENABLE_AXI_STATUS_SHIFT 0
-
-/***************************************************************************
- *USB1_TOP_INST_CLOCK_ENABLE_STATUS - Clock Enable Status
- ***************************************************************************/
-/* CLKGEN :: USB1_TOP_INST_CLOCK_ENABLE_STATUS :: reserved0 [31:03] */
-#define BCHP_CLKGEN_USB1_TOP_INST_CLOCK_ENABLE_STATUS_reserved0_MASK 0xfffffff8
-#define BCHP_CLKGEN_USB1_TOP_INST_CLOCK_ENABLE_STATUS_reserved0_SHIFT 3
-
-/* CLKGEN :: USB1_TOP_INST_CLOCK_ENABLE_STATUS :: USB1_SCB_CLOCK_ENABLE_STATUS [02:02] */
-#define BCHP_CLKGEN_USB1_TOP_INST_CLOCK_ENABLE_STATUS_USB1_SCB_CLOCK_ENABLE_STATUS_MASK 0x00000004
-#define BCHP_CLKGEN_USB1_TOP_INST_CLOCK_ENABLE_STATUS_USB1_SCB_CLOCK_ENABLE_STATUS_SHIFT 2
-
-/* CLKGEN :: USB1_TOP_INST_CLOCK_ENABLE_STATUS :: USB1_GISB_CLOCK_ENABLE_STATUS [01:01] */
-#define BCHP_CLKGEN_USB1_TOP_INST_CLOCK_ENABLE_STATUS_USB1_GISB_CLOCK_ENABLE_STATUS_MASK 0x00000002
-#define BCHP_CLKGEN_USB1_TOP_INST_CLOCK_ENABLE_STATUS_USB1_GISB_CLOCK_ENABLE_STATUS_SHIFT 1
-
-/* CLKGEN :: USB1_TOP_INST_CLOCK_ENABLE_STATUS :: USB1_54_CLOCK_ENABLE_STATUS [00:00] */
-#define BCHP_CLKGEN_USB1_TOP_INST_CLOCK_ENABLE_STATUS_USB1_54_CLOCK_ENABLE_STATUS_MASK 0x00000001
-#define BCHP_CLKGEN_USB1_TOP_INST_CLOCK_ENABLE_STATUS_USB1_54_CLOCK_ENABLE_STATUS_SHIFT 0
-
-/***************************************************************************
- *USB1_TOP_INST_OBSERVE_CLOCK - Usb1 top inst observe clock
- ***************************************************************************/
-/* CLKGEN :: USB1_TOP_INST_OBSERVE_CLOCK :: reserved0 [31:06] */
-#define BCHP_CLKGEN_USB1_TOP_INST_OBSERVE_CLOCK_reserved0_MASK 0xffffffc0
-#define BCHP_CLKGEN_USB1_TOP_INST_OBSERVE_CLOCK_reserved0_SHIFT 6
-
-/* CLKGEN :: USB1_TOP_INST_OBSERVE_CLOCK :: USB1_ENABLE_OBSERVE_CLOCK [05:05] */
-#define BCHP_CLKGEN_USB1_TOP_INST_OBSERVE_CLOCK_USB1_ENABLE_OBSERVE_CLOCK_MASK 0x00000020
-#define BCHP_CLKGEN_USB1_TOP_INST_OBSERVE_CLOCK_USB1_ENABLE_OBSERVE_CLOCK_SHIFT 5
-#define BCHP_CLKGEN_USB1_TOP_INST_OBSERVE_CLOCK_USB1_ENABLE_OBSERVE_CLOCK_DEFAULT 0x00000000
-
-/* CLKGEN :: USB1_TOP_INST_OBSERVE_CLOCK :: USB1_ENABLE_DIVIDER_OBSERVE_CLOCK [04:04] */
-#define BCHP_CLKGEN_USB1_TOP_INST_OBSERVE_CLOCK_USB1_ENABLE_DIVIDER_OBSERVE_CLOCK_MASK 0x00000010
-#define BCHP_CLKGEN_USB1_TOP_INST_OBSERVE_CLOCK_USB1_ENABLE_DIVIDER_OBSERVE_CLOCK_SHIFT 4
-#define BCHP_CLKGEN_USB1_TOP_INST_OBSERVE_CLOCK_USB1_ENABLE_DIVIDER_OBSERVE_CLOCK_DEFAULT 0x00000000
-
-/* CLKGEN :: USB1_TOP_INST_OBSERVE_CLOCK :: USB1_CONTROL_OBSERVE_CLOCK [03:00] */
-#define BCHP_CLKGEN_USB1_TOP_INST_OBSERVE_CLOCK_USB1_CONTROL_OBSERVE_CLOCK_MASK 0x0000000f
-#define BCHP_CLKGEN_USB1_TOP_INST_OBSERVE_CLOCK_USB1_CONTROL_OBSERVE_CLOCK_SHIFT 0
-#define BCHP_CLKGEN_USB1_TOP_INST_OBSERVE_CLOCK_USB1_CONTROL_OBSERVE_CLOCK_DEFAULT 0x00000000
-
-/***************************************************************************
- *V3D_TOP_INST_CKTAPSEL - V3d top inst cktapsel
- ***************************************************************************/
-/* CLKGEN :: V3D_TOP_INST_CKTAPSEL :: reserved0 [31:12] */
-#define BCHP_CLKGEN_V3D_TOP_INST_CKTAPSEL_reserved0_MASK 0xfffff000
-#define BCHP_CLKGEN_V3D_TOP_INST_CKTAPSEL_reserved0_SHIFT 12
-
-/* CLKGEN :: V3D_TOP_INST_CKTAPSEL :: SCB_CKTAP1_CKTAPSEL [11:06] */
-#define BCHP_CLKGEN_V3D_TOP_INST_CKTAPSEL_SCB_CKTAP1_CKTAPSEL_MASK 0x00000fc0
-#define BCHP_CLKGEN_V3D_TOP_INST_CKTAPSEL_SCB_CKTAP1_CKTAPSEL_SHIFT 6
-#define BCHP_CLKGEN_V3D_TOP_INST_CKTAPSEL_SCB_CKTAP1_CKTAPSEL_DEFAULT 0x00000000
-
-/* CLKGEN :: V3D_TOP_INST_CKTAPSEL :: SCB_CKTAP0_CKTAPSEL [05:00] */
-#define BCHP_CLKGEN_V3D_TOP_INST_CKTAPSEL_SCB_CKTAP0_CKTAPSEL_MASK 0x0000003f
-#define BCHP_CLKGEN_V3D_TOP_INST_CKTAPSEL_SCB_CKTAP0_CKTAPSEL_SHIFT 0
-#define BCHP_CLKGEN_V3D_TOP_INST_CKTAPSEL_SCB_CKTAP0_CKTAPSEL_DEFAULT 0x00000000
-
-/***************************************************************************
- *V3D_TOP_INST_CLOCK_ENABLE - V3d top inst clock enable
- ***************************************************************************/
-/* CLKGEN :: V3D_TOP_INST_CLOCK_ENABLE :: reserved0 [31:04] */
-#define BCHP_CLKGEN_V3D_TOP_INST_CLOCK_ENABLE_reserved0_MASK 0xfffffff0
-#define BCHP_CLKGEN_V3D_TOP_INST_CLOCK_ENABLE_reserved0_SHIFT 4
-
-/* CLKGEN :: V3D_TOP_INST_CLOCK_ENABLE :: V3D_SCB_CLOCK_ENABLE [03:03] */
-#define BCHP_CLKGEN_V3D_TOP_INST_CLOCK_ENABLE_V3D_SCB_CLOCK_ENABLE_MASK 0x00000008
-#define BCHP_CLKGEN_V3D_TOP_INST_CLOCK_ENABLE_V3D_SCB_CLOCK_ENABLE_SHIFT 3
-#define BCHP_CLKGEN_V3D_TOP_INST_CLOCK_ENABLE_V3D_SCB_CLOCK_ENABLE_DEFAULT 0x00000001
-
-/* CLKGEN :: V3D_TOP_INST_CLOCK_ENABLE :: V3D_GISB_CLOCK_ENABLE [02:02] */
-#define BCHP_CLKGEN_V3D_TOP_INST_CLOCK_ENABLE_V3D_GISB_CLOCK_ENABLE_MASK 0x00000004
-#define BCHP_CLKGEN_V3D_TOP_INST_CLOCK_ENABLE_V3D_GISB_CLOCK_ENABLE_SHIFT 2
-#define BCHP_CLKGEN_V3D_TOP_INST_CLOCK_ENABLE_V3D_GISB_CLOCK_ENABLE_DEFAULT 0x00000001
-
-/* CLKGEN :: V3D_TOP_INST_CLOCK_ENABLE :: V3D_CLOCK_ENABLE [01:01] */
-#define BCHP_CLKGEN_V3D_TOP_INST_CLOCK_ENABLE_V3D_CLOCK_ENABLE_MASK 0x00000002
-#define BCHP_CLKGEN_V3D_TOP_INST_CLOCK_ENABLE_V3D_CLOCK_ENABLE_SHIFT 1
-#define BCHP_CLKGEN_V3D_TOP_INST_CLOCK_ENABLE_V3D_CLOCK_ENABLE_DEFAULT 0x00000001
-
-/* CLKGEN :: V3D_TOP_INST_CLOCK_ENABLE :: V3D_54_CLOCK_ENABLE [00:00] */
-#define BCHP_CLKGEN_V3D_TOP_INST_CLOCK_ENABLE_V3D_54_CLOCK_ENABLE_MASK 0x00000001
-#define BCHP_CLKGEN_V3D_TOP_INST_CLOCK_ENABLE_V3D_54_CLOCK_ENABLE_SHIFT 0
-#define BCHP_CLKGEN_V3D_TOP_INST_CLOCK_ENABLE_V3D_54_CLOCK_ENABLE_DEFAULT 0x00000001
-
-/***************************************************************************
- *V3D_TOP_INST_CLOCK_ENABLE_STATUS - Clock Enable Status
- ***************************************************************************/
-/* CLKGEN :: V3D_TOP_INST_CLOCK_ENABLE_STATUS :: reserved0 [31:04] */
-#define BCHP_CLKGEN_V3D_TOP_INST_CLOCK_ENABLE_STATUS_reserved0_MASK 0xfffffff0
-#define BCHP_CLKGEN_V3D_TOP_INST_CLOCK_ENABLE_STATUS_reserved0_SHIFT 4
-
-/* CLKGEN :: V3D_TOP_INST_CLOCK_ENABLE_STATUS :: V3D_SCB_CLOCK_ENABLE_STATUS [03:03] */
-#define BCHP_CLKGEN_V3D_TOP_INST_CLOCK_ENABLE_STATUS_V3D_SCB_CLOCK_ENABLE_STATUS_MASK 0x00000008
-#define BCHP_CLKGEN_V3D_TOP_INST_CLOCK_ENABLE_STATUS_V3D_SCB_CLOCK_ENABLE_STATUS_SHIFT 3
-
-/* CLKGEN :: V3D_TOP_INST_CLOCK_ENABLE_STATUS :: V3D_GISB_CLOCK_ENABLE_STATUS [02:02] */
-#define BCHP_CLKGEN_V3D_TOP_INST_CLOCK_ENABLE_STATUS_V3D_GISB_CLOCK_ENABLE_STATUS_MASK 0x00000004
-#define BCHP_CLKGEN_V3D_TOP_INST_CLOCK_ENABLE_STATUS_V3D_GISB_CLOCK_ENABLE_STATUS_SHIFT 2
-
-/* CLKGEN :: V3D_TOP_INST_CLOCK_ENABLE_STATUS :: V3D_CLOCK_ENABLE_STATUS [01:01] */
-#define BCHP_CLKGEN_V3D_TOP_INST_CLOCK_ENABLE_STATUS_V3D_CLOCK_ENABLE_STATUS_MASK 0x00000002
-#define BCHP_CLKGEN_V3D_TOP_INST_CLOCK_ENABLE_STATUS_V3D_CLOCK_ENABLE_STATUS_SHIFT 1
-
-/* CLKGEN :: V3D_TOP_INST_CLOCK_ENABLE_STATUS :: V3D_54_CLOCK_ENABLE_STATUS [00:00] */
-#define BCHP_CLKGEN_V3D_TOP_INST_CLOCK_ENABLE_STATUS_V3D_54_CLOCK_ENABLE_STATUS_MASK 0x00000001
-#define BCHP_CLKGEN_V3D_TOP_INST_CLOCK_ENABLE_STATUS_V3D_54_CLOCK_ENABLE_STATUS_SHIFT 0
-
-/***************************************************************************
- *VEC_AIO_TOP_INST_CKTAPSEL - Vec aio top inst cktapsel
- ***************************************************************************/
-/* CLKGEN :: VEC_AIO_TOP_INST_CKTAPSEL :: reserved0 [31:12] */
-#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CKTAPSEL_reserved0_MASK 0xfffff000
-#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CKTAPSEL_reserved0_SHIFT 12
-
-/* CLKGEN :: VEC_AIO_TOP_INST_CKTAPSEL :: SCB_CKTAP1_CKTAPSEL [11:06] */
-#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CKTAPSEL_SCB_CKTAP1_CKTAPSEL_MASK 0x00000fc0
-#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CKTAPSEL_SCB_CKTAP1_CKTAPSEL_SHIFT 6
-#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CKTAPSEL_SCB_CKTAP1_CKTAPSEL_DEFAULT 0x00000000
-
-/* CLKGEN :: VEC_AIO_TOP_INST_CKTAPSEL :: SCB_CKTAP0_CKTAPSEL [05:00] */
-#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CKTAPSEL_SCB_CKTAP0_CKTAPSEL_MASK 0x0000003f
-#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CKTAPSEL_SCB_CKTAP0_CKTAPSEL_SHIFT 0
-#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CKTAPSEL_SCB_CKTAP0_CKTAPSEL_DEFAULT 0x00000000
-
-/***************************************************************************
- *VEC_AIO_TOP_INST_CLOCK_DISABLE - Disable VEC_AIO_TOP_INST's clocks
- ***************************************************************************/
-/* CLKGEN :: VEC_AIO_TOP_INST_CLOCK_DISABLE :: reserved0 [31:02] */
-#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_DISABLE_reserved0_MASK 0xfffffffc
-#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_DISABLE_reserved0_SHIFT 2
-
-/* CLKGEN :: VEC_AIO_TOP_INST_CLOCK_DISABLE :: DISABLE_VEC_ITU656_0_CLOCK [01:01] */
-#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_DISABLE_DISABLE_VEC_ITU656_0_CLOCK_MASK 0x00000002
-#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_DISABLE_DISABLE_VEC_ITU656_0_CLOCK_SHIFT 1
-#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_DISABLE_DISABLE_VEC_ITU656_0_CLOCK_DEFAULT 0x00000000
-
-/* CLKGEN :: VEC_AIO_TOP_INST_CLOCK_DISABLE :: DISABLE_VEC_DACADC_CLOCK [00:00] */
-#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_DISABLE_DISABLE_VEC_DACADC_CLOCK_MASK 0x00000001
-#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_DISABLE_DISABLE_VEC_DACADC_CLOCK_SHIFT 0
-#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_DISABLE_DISABLE_VEC_DACADC_CLOCK_DEFAULT 0x00000000
-
-/***************************************************************************
- *VEC_AIO_TOP_INST_CLOCK_DISABLE_STATUS - Clock Disable Status
- ***************************************************************************/
-/* CLKGEN :: VEC_AIO_TOP_INST_CLOCK_DISABLE_STATUS :: reserved0 [31:02] */
-#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_DISABLE_STATUS_reserved0_MASK 0xfffffffc
-#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_DISABLE_STATUS_reserved0_SHIFT 2
-
-/* CLKGEN :: VEC_AIO_TOP_INST_CLOCK_DISABLE_STATUS :: DISABLE_VEC_ITU656_0_CLOCK_STATUS [01:01] */
-#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_DISABLE_STATUS_DISABLE_VEC_ITU656_0_CLOCK_STATUS_MASK 0x00000002
-#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_DISABLE_STATUS_DISABLE_VEC_ITU656_0_CLOCK_STATUS_SHIFT 1
-
-/* CLKGEN :: VEC_AIO_TOP_INST_CLOCK_DISABLE_STATUS :: DISABLE_VEC_DACADC_CLOCK_STATUS [00:00] */
-#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_DISABLE_STATUS_DISABLE_VEC_DACADC_CLOCK_STATUS_MASK 0x00000001
-#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_DISABLE_STATUS_DISABLE_VEC_DACADC_CLOCK_STATUS_SHIFT 0
-
-/***************************************************************************
- *VEC_AIO_TOP_INST_CLOCK_ENABLE - Vec aio top inst clock enable
- ***************************************************************************/
-/* CLKGEN :: VEC_AIO_TOP_INST_CLOCK_ENABLE :: reserved0 [31:01] */
-#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_reserved0_MASK 0xfffffffe
-#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_reserved0_SHIFT 1
-
-/* CLKGEN :: VEC_AIO_TOP_INST_CLOCK_ENABLE :: VEC_AIO_54_CLOCK_ENABLE [00:00] */
-#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC_AIO_54_CLOCK_ENABLE_MASK 0x00000001
-#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC_AIO_54_CLOCK_ENABLE_SHIFT 0
-#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC_AIO_54_CLOCK_ENABLE_DEFAULT 0x00000001
-
-/***************************************************************************
- *VEC_AIO_TOP_INST_CLOCK_ENABLE_AIO - Vec aio top inst clock enable aio
- ***************************************************************************/
-/* CLKGEN :: VEC_AIO_TOP_INST_CLOCK_ENABLE_AIO :: reserved0 [31:02] */
-#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_AIO_reserved0_MASK 0xfffffffc
-#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_AIO_reserved0_SHIFT 2
-
-/* CLKGEN :: VEC_AIO_TOP_INST_CLOCK_ENABLE_AIO :: AIO_ALTERNATE_SCB_CLOCK_ENABLE_AIO [01:01] */
-#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_AIO_AIO_ALTERNATE_SCB_CLOCK_ENABLE_AIO_MASK 0x00000002
-#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_AIO_AIO_ALTERNATE_SCB_CLOCK_ENABLE_AIO_SHIFT 1
-#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_AIO_AIO_ALTERNATE_SCB_CLOCK_ENABLE_AIO_DEFAULT 0x00000001
-
-/* CLKGEN :: VEC_AIO_TOP_INST_CLOCK_ENABLE_AIO :: AIO_ALTERNATE_108_CLOCK_ENABLE_AIO [00:00] */
-#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_AIO_AIO_ALTERNATE_108_CLOCK_ENABLE_AIO_MASK 0x00000001
-#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_AIO_AIO_ALTERNATE_108_CLOCK_ENABLE_AIO_SHIFT 0
-#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_AIO_AIO_ALTERNATE_108_CLOCK_ENABLE_AIO_DEFAULT 0x00000001
-
-/***************************************************************************
- *VEC_AIO_TOP_INST_CLOCK_ENABLE_AIO_STATUS - Clock Enable Status
- ***************************************************************************/
-/* CLKGEN :: VEC_AIO_TOP_INST_CLOCK_ENABLE_AIO_STATUS :: reserved0 [31:02] */
-#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_AIO_STATUS_reserved0_MASK 0xfffffffc
-#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_AIO_STATUS_reserved0_SHIFT 2
-
-/* CLKGEN :: VEC_AIO_TOP_INST_CLOCK_ENABLE_AIO_STATUS :: AIO_ALTERNATE_SCB_CLOCK_ENABLE_AIO_STATUS [01:01] */
-#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_AIO_STATUS_AIO_ALTERNATE_SCB_CLOCK_ENABLE_AIO_STATUS_MASK 0x00000002
-#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_AIO_STATUS_AIO_ALTERNATE_SCB_CLOCK_ENABLE_AIO_STATUS_SHIFT 1
-
-/* CLKGEN :: VEC_AIO_TOP_INST_CLOCK_ENABLE_AIO_STATUS :: AIO_ALTERNATE_108_CLOCK_ENABLE_AIO_STATUS [00:00] */
-#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_AIO_STATUS_AIO_ALTERNATE_108_CLOCK_ENABLE_AIO_STATUS_MASK 0x00000001
-#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_AIO_STATUS_AIO_ALTERNATE_108_CLOCK_ENABLE_AIO_STATUS_SHIFT 0
-
-/***************************************************************************
- *VEC_AIO_TOP_INST_CLOCK_ENABLE_STATUS - Clock Enable Status
- ***************************************************************************/
-/* CLKGEN :: VEC_AIO_TOP_INST_CLOCK_ENABLE_STATUS :: reserved0 [31:01] */
-#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_STATUS_reserved0_MASK 0xfffffffe
-#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_STATUS_reserved0_SHIFT 1
-
-/* CLKGEN :: VEC_AIO_TOP_INST_CLOCK_ENABLE_STATUS :: VEC_AIO_54_CLOCK_ENABLE_STATUS [00:00] */
-#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_STATUS_VEC_AIO_54_CLOCK_ENABLE_STATUS_MASK 0x00000001
-#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_STATUS_VEC_AIO_54_CLOCK_ENABLE_STATUS_SHIFT 0
-
-/***************************************************************************
- *VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC - Vec aio top inst clock enable vec
- ***************************************************************************/
-/* CLKGEN :: VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC :: reserved0 [31:07] */
-#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC_reserved0_MASK 0xffffff80
-#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC_reserved0_SHIFT 7
-
-/* CLKGEN :: VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC :: VEC_SCB_CLOCK_ENABLE_VEC [06:06] */
-#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC_VEC_SCB_CLOCK_ENABLE_VEC_MASK 0x00000040
-#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC_VEC_SCB_CLOCK_ENABLE_VEC_SHIFT 6
-#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC_VEC_SCB_CLOCK_ENABLE_VEC_DEFAULT 0x00000001
-
-/* CLKGEN :: VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC :: VEC_GISB_CLOCK_ENABLE_VEC [05:05] */
-#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC_VEC_GISB_CLOCK_ENABLE_VEC_MASK 0x00000020
-#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC_VEC_GISB_CLOCK_ENABLE_VEC_SHIFT 5
-#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC_VEC_GISB_CLOCK_ENABLE_VEC_DEFAULT 0x00000001
-
-/* CLKGEN :: VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC :: VEC_BVB_648_CLOCK_ENABLE_VEC [04:04] */
-#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC_VEC_BVB_648_CLOCK_ENABLE_VEC_MASK 0x00000010
-#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC_VEC_BVB_648_CLOCK_ENABLE_VEC_SHIFT 4
-#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC_VEC_BVB_648_CLOCK_ENABLE_VEC_DEFAULT 0x00000001
-
-/* CLKGEN :: VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC :: VEC_BVB_324_CLOCK_ENABLE_VEC [03:03] */
-#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC_VEC_BVB_324_CLOCK_ENABLE_VEC_MASK 0x00000008
-#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC_VEC_BVB_324_CLOCK_ENABLE_VEC_SHIFT 3
-#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC_VEC_BVB_324_CLOCK_ENABLE_VEC_DEFAULT 0x00000001
-
-/* CLKGEN :: VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC :: VEC_BVB_216_CLOCK_ENABLE_VEC [02:02] */
-#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC_VEC_BVB_216_CLOCK_ENABLE_VEC_MASK 0x00000004
-#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC_VEC_BVB_216_CLOCK_ENABLE_VEC_SHIFT 2
-#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC_VEC_BVB_216_CLOCK_ENABLE_VEC_DEFAULT 0x00000001
-
-/* CLKGEN :: VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC :: VEC_108_CLOCK_ENABLE_VEC [01:01] */
-#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC_VEC_108_CLOCK_ENABLE_VEC_MASK 0x00000002
-#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC_VEC_108_CLOCK_ENABLE_VEC_SHIFT 1
-#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC_VEC_108_CLOCK_ENABLE_VEC_DEFAULT 0x00000001
-
-/* CLKGEN :: VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC :: QDAC_GISB_CLOCK_ENABLE_VEC [00:00] */
-#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC_QDAC_GISB_CLOCK_ENABLE_VEC_MASK 0x00000001
-#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC_QDAC_GISB_CLOCK_ENABLE_VEC_SHIFT 0
-#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC_QDAC_GISB_CLOCK_ENABLE_VEC_DEFAULT 0x00000001
-
-/***************************************************************************
- *VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC_QDAC_INTF - Vec aio top inst clock enable vec qdac intf
- ***************************************************************************/
-/* CLKGEN :: VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC_QDAC_INTF :: reserved0 [31:01] */
-#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC_QDAC_INTF_reserved0_MASK 0xfffffffe
-#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC_QDAC_INTF_reserved0_SHIFT 1
-
-/* CLKGEN :: VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC_QDAC_INTF :: VEC_GISB_CLOCK_ENABLE_VEC_QDAC_INTF [00:00] */
-#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC_QDAC_INTF_VEC_GISB_CLOCK_ENABLE_VEC_QDAC_INTF_MASK 0x00000001
-#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC_QDAC_INTF_VEC_GISB_CLOCK_ENABLE_VEC_QDAC_INTF_SHIFT 0
-#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC_QDAC_INTF_VEC_GISB_CLOCK_ENABLE_VEC_QDAC_INTF_DEFAULT 0x00000001
-
-/***************************************************************************
- *VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC_QDAC_INTF_STATUS - Clock Enable Status
- ***************************************************************************/
-/* CLKGEN :: VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC_QDAC_INTF_STATUS :: reserved0 [31:01] */
-#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC_QDAC_INTF_STATUS_reserved0_MASK 0xfffffffe
-#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC_QDAC_INTF_STATUS_reserved0_SHIFT 1
-
-/* CLKGEN :: VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC_QDAC_INTF_STATUS :: VEC_GISB_CLOCK_ENABLE_VEC_QDAC_INTF_STATUS [00:00] */
-#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC_QDAC_INTF_STATUS_VEC_GISB_CLOCK_ENABLE_VEC_QDAC_INTF_STATUS_MASK 0x00000001
-#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC_QDAC_INTF_STATUS_VEC_GISB_CLOCK_ENABLE_VEC_QDAC_INTF_STATUS_SHIFT 0
-
-/***************************************************************************
- *VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC_STATUS - Clock Enable Status
- ***************************************************************************/
-/* CLKGEN :: VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC_STATUS :: reserved0 [31:07] */
-#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC_STATUS_reserved0_MASK 0xffffff80
-#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC_STATUS_reserved0_SHIFT 7
-
-/* CLKGEN :: VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC_STATUS :: VEC_SCB_CLOCK_ENABLE_VEC_STATUS [06:06] */
-#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC_STATUS_VEC_SCB_CLOCK_ENABLE_VEC_STATUS_MASK 0x00000040
-#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC_STATUS_VEC_SCB_CLOCK_ENABLE_VEC_STATUS_SHIFT 6
-
-/* CLKGEN :: VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC_STATUS :: VEC_GISB_CLOCK_ENABLE_VEC_STATUS [05:05] */
-#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC_STATUS_VEC_GISB_CLOCK_ENABLE_VEC_STATUS_MASK 0x00000020
-#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC_STATUS_VEC_GISB_CLOCK_ENABLE_VEC_STATUS_SHIFT 5
-
-/* CLKGEN :: VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC_STATUS :: VEC_BVB_648_CLOCK_ENABLE_VEC_STATUS [04:04] */
-#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC_STATUS_VEC_BVB_648_CLOCK_ENABLE_VEC_STATUS_MASK 0x00000010
-#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC_STATUS_VEC_BVB_648_CLOCK_ENABLE_VEC_STATUS_SHIFT 4
-
-/* CLKGEN :: VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC_STATUS :: VEC_BVB_324_CLOCK_ENABLE_VEC_STATUS [03:03] */
-#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC_STATUS_VEC_BVB_324_CLOCK_ENABLE_VEC_STATUS_MASK 0x00000008
-#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC_STATUS_VEC_BVB_324_CLOCK_ENABLE_VEC_STATUS_SHIFT 3
-
-/* CLKGEN :: VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC_STATUS :: VEC_BVB_216_CLOCK_ENABLE_VEC_STATUS [02:02] */
-#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC_STATUS_VEC_BVB_216_CLOCK_ENABLE_VEC_STATUS_MASK 0x00000004
-#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC_STATUS_VEC_BVB_216_CLOCK_ENABLE_VEC_STATUS_SHIFT 2
-
-/* CLKGEN :: VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC_STATUS :: VEC_108_CLOCK_ENABLE_VEC_STATUS [01:01] */
-#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC_STATUS_VEC_108_CLOCK_ENABLE_VEC_STATUS_MASK 0x00000002
-#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC_STATUS_VEC_108_CLOCK_ENABLE_VEC_STATUS_SHIFT 1
-
-/* CLKGEN :: VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC_STATUS :: QDAC_GISB_CLOCK_ENABLE_VEC_STATUS [00:00] */
-#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC_STATUS_QDAC_GISB_CLOCK_ENABLE_VEC_STATUS_MASK 0x00000001
-#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC_STATUS_QDAC_GISB_CLOCK_ENABLE_VEC_STATUS_SHIFT 0
-
-/***************************************************************************
- *VEC_AIO_TOP_INST_OBSERVE_CLOCK - Vec aio top inst observe clock
- ***************************************************************************/
-/* CLKGEN :: VEC_AIO_TOP_INST_OBSERVE_CLOCK :: reserved0 [31:12] */
-#define BCHP_CLKGEN_VEC_AIO_TOP_INST_OBSERVE_CLOCK_reserved0_MASK 0xfffff000
-#define BCHP_CLKGEN_VEC_AIO_TOP_INST_OBSERVE_CLOCK_reserved0_SHIFT 12
-
-/* CLKGEN :: VEC_AIO_TOP_INST_OBSERVE_CLOCK :: VEC_ENABLE_OBSERVE_CLOCK [11:11] */
-#define BCHP_CLKGEN_VEC_AIO_TOP_INST_OBSERVE_CLOCK_VEC_ENABLE_OBSERVE_CLOCK_MASK 0x00000800
-#define BCHP_CLKGEN_VEC_AIO_TOP_INST_OBSERVE_CLOCK_VEC_ENABLE_OBSERVE_CLOCK_SHIFT 11
-#define BCHP_CLKGEN_VEC_AIO_TOP_INST_OBSERVE_CLOCK_VEC_ENABLE_OBSERVE_CLOCK_DEFAULT 0x00000000
-
-/* CLKGEN :: VEC_AIO_TOP_INST_OBSERVE_CLOCK :: VEC_ENABLE_DIVIDER_OBSERVE_CLOCK [10:10] */
-#define BCHP_CLKGEN_VEC_AIO_TOP_INST_OBSERVE_CLOCK_VEC_ENABLE_DIVIDER_OBSERVE_CLOCK_MASK 0x00000400
-#define BCHP_CLKGEN_VEC_AIO_TOP_INST_OBSERVE_CLOCK_VEC_ENABLE_DIVIDER_OBSERVE_CLOCK_SHIFT 10
-#define BCHP_CLKGEN_VEC_AIO_TOP_INST_OBSERVE_CLOCK_VEC_ENABLE_DIVIDER_OBSERVE_CLOCK_DEFAULT 0x00000000
-
-/* CLKGEN :: VEC_AIO_TOP_INST_OBSERVE_CLOCK :: VEC_CONTROL_OBSERVE_CLOCK [09:06] */
-#define BCHP_CLKGEN_VEC_AIO_TOP_INST_OBSERVE_CLOCK_VEC_CONTROL_OBSERVE_CLOCK_MASK 0x000003c0
-#define BCHP_CLKGEN_VEC_AIO_TOP_INST_OBSERVE_CLOCK_VEC_CONTROL_OBSERVE_CLOCK_SHIFT 6
-#define BCHP_CLKGEN_VEC_AIO_TOP_INST_OBSERVE_CLOCK_VEC_CONTROL_OBSERVE_CLOCK_DEFAULT 0x00000000
-
-/* CLKGEN :: VEC_AIO_TOP_INST_OBSERVE_CLOCK :: AIO_ENABLE_OBSERVE_CLOCK [05:05] */
-#define BCHP_CLKGEN_VEC_AIO_TOP_INST_OBSERVE_CLOCK_AIO_ENABLE_OBSERVE_CLOCK_MASK 0x00000020
-#define BCHP_CLKGEN_VEC_AIO_TOP_INST_OBSERVE_CLOCK_AIO_ENABLE_OBSERVE_CLOCK_SHIFT 5
-#define BCHP_CLKGEN_VEC_AIO_TOP_INST_OBSERVE_CLOCK_AIO_ENABLE_OBSERVE_CLOCK_DEFAULT 0x00000000
-
-/* CLKGEN :: VEC_AIO_TOP_INST_OBSERVE_CLOCK :: AIO_ENABLE_DIVIDER_OBSERVE_CLOCK [04:04] */
-#define BCHP_CLKGEN_VEC_AIO_TOP_INST_OBSERVE_CLOCK_AIO_ENABLE_DIVIDER_OBSERVE_CLOCK_MASK 0x00000010
-#define BCHP_CLKGEN_VEC_AIO_TOP_INST_OBSERVE_CLOCK_AIO_ENABLE_DIVIDER_OBSERVE_CLOCK_SHIFT 4
-#define BCHP_CLKGEN_VEC_AIO_TOP_INST_OBSERVE_CLOCK_AIO_ENABLE_DIVIDER_OBSERVE_CLOCK_DEFAULT 0x00000000
-
-/* CLKGEN :: VEC_AIO_TOP_INST_OBSERVE_CLOCK :: AIO_CONTROL_OBSERVE_CLOCK [03:00] */
-#define BCHP_CLKGEN_VEC_AIO_TOP_INST_OBSERVE_CLOCK_AIO_CONTROL_OBSERVE_CLOCK_MASK 0x0000000f
-#define BCHP_CLKGEN_VEC_AIO_TOP_INST_OBSERVE_CLOCK_AIO_CONTROL_OBSERVE_CLOCK_SHIFT 0
-#define BCHP_CLKGEN_VEC_AIO_TOP_INST_OBSERVE_CLOCK_AIO_CONTROL_OBSERVE_CLOCK_DEFAULT 0x00000000
-
-/***************************************************************************
- *VICE2_0_INST_CKTAPSEL - Vice2 0 inst cktapsel
- ***************************************************************************/
-/* CLKGEN :: VICE2_0_INST_CKTAPSEL :: reserved0 [31:12] */
-#define BCHP_CLKGEN_VICE2_0_INST_CKTAPSEL_reserved0_MASK 0xfffff000
-#define BCHP_CLKGEN_VICE2_0_INST_CKTAPSEL_reserved0_SHIFT 12
-
-/* CLKGEN :: VICE2_0_INST_CKTAPSEL :: SCB_CKTAP1_CKTAPSEL [11:06] */
-#define BCHP_CLKGEN_VICE2_0_INST_CKTAPSEL_SCB_CKTAP1_CKTAPSEL_MASK 0x00000fc0
-#define BCHP_CLKGEN_VICE2_0_INST_CKTAPSEL_SCB_CKTAP1_CKTAPSEL_SHIFT 6
-#define BCHP_CLKGEN_VICE2_0_INST_CKTAPSEL_SCB_CKTAP1_CKTAPSEL_DEFAULT 0x00000000
-
-/* CLKGEN :: VICE2_0_INST_CKTAPSEL :: SCB_CKTAP0_CKTAPSEL [05:00] */
-#define BCHP_CLKGEN_VICE2_0_INST_CKTAPSEL_SCB_CKTAP0_CKTAPSEL_MASK 0x0000003f
-#define BCHP_CLKGEN_VICE2_0_INST_CKTAPSEL_SCB_CKTAP0_CKTAPSEL_SHIFT 0
-#define BCHP_CLKGEN_VICE2_0_INST_CKTAPSEL_SCB_CKTAP0_CKTAPSEL_DEFAULT 0x00000000
-
-/***************************************************************************
- *VICE2_0_INST_CLOCK_ENABLE - Vice2 0 inst clock enable
- ***************************************************************************/
-/* CLKGEN :: VICE2_0_INST_CLOCK_ENABLE :: reserved0 [31:06] */
-#define BCHP_CLKGEN_VICE2_0_INST_CLOCK_ENABLE_reserved0_MASK 0xffffffc0
-#define BCHP_CLKGEN_VICE2_0_INST_CLOCK_ENABLE_reserved0_SHIFT 6
-
-/* CLKGEN :: VICE2_0_INST_CLOCK_ENABLE :: VICE2_0_SCB_CLOCK_ENABLE [05:05] */
-#define BCHP_CLKGEN_VICE2_0_INST_CLOCK_ENABLE_VICE2_0_SCB_CLOCK_ENABLE_MASK 0x00000020
-#define BCHP_CLKGEN_VICE2_0_INST_CLOCK_ENABLE_VICE2_0_SCB_CLOCK_ENABLE_SHIFT 5
-#define BCHP_CLKGEN_VICE2_0_INST_CLOCK_ENABLE_VICE2_0_SCB_CLOCK_ENABLE_DEFAULT 0x00000001
-
-/* CLKGEN :: VICE2_0_INST_CLOCK_ENABLE :: VICE2_0_GISB_CLOCK_ENABLE [04:04] */
-#define BCHP_CLKGEN_VICE2_0_INST_CLOCK_ENABLE_VICE2_0_GISB_CLOCK_ENABLE_MASK 0x00000010
-#define BCHP_CLKGEN_VICE2_0_INST_CLOCK_ENABLE_VICE2_0_GISB_CLOCK_ENABLE_SHIFT 4
-#define BCHP_CLKGEN_VICE2_0_INST_CLOCK_ENABLE_VICE2_0_GISB_CLOCK_ENABLE_DEFAULT 0x00000001
-
-/* CLKGEN :: VICE2_0_INST_CLOCK_ENABLE :: VICE2_0_CORE_CLOCK_ENABLE [03:03] */
-#define BCHP_CLKGEN_VICE2_0_INST_CLOCK_ENABLE_VICE2_0_CORE_CLOCK_ENABLE_MASK 0x00000008
-#define BCHP_CLKGEN_VICE2_0_INST_CLOCK_ENABLE_VICE2_0_CORE_CLOCK_ENABLE_SHIFT 3
-#define BCHP_CLKGEN_VICE2_0_INST_CLOCK_ENABLE_VICE2_0_CORE_CLOCK_ENABLE_DEFAULT 0x00000001
-
-/* CLKGEN :: VICE2_0_INST_CLOCK_ENABLE :: VICE2_0_BVB_216_CLOCK_ENABLE [02:02] */
-#define BCHP_CLKGEN_VICE2_0_INST_CLOCK_ENABLE_VICE2_0_BVB_216_CLOCK_ENABLE_MASK 0x00000004
-#define BCHP_CLKGEN_VICE2_0_INST_CLOCK_ENABLE_VICE2_0_BVB_216_CLOCK_ENABLE_SHIFT 2
-#define BCHP_CLKGEN_VICE2_0_INST_CLOCK_ENABLE_VICE2_0_BVB_216_CLOCK_ENABLE_DEFAULT 0x00000001
-
-/* CLKGEN :: VICE2_0_INST_CLOCK_ENABLE :: VICE2_0_54_CLOCK_ENABLE [01:01] */
-#define BCHP_CLKGEN_VICE2_0_INST_CLOCK_ENABLE_VICE2_0_54_CLOCK_ENABLE_MASK 0x00000002
-#define BCHP_CLKGEN_VICE2_0_INST_CLOCK_ENABLE_VICE2_0_54_CLOCK_ENABLE_SHIFT 1
-#define BCHP_CLKGEN_VICE2_0_INST_CLOCK_ENABLE_VICE2_0_54_CLOCK_ENABLE_DEFAULT 0x00000001
-
-/* CLKGEN :: VICE2_0_INST_CLOCK_ENABLE :: VICE2_0_108_CLOCK_ENABLE [00:00] */
-#define BCHP_CLKGEN_VICE2_0_INST_CLOCK_ENABLE_VICE2_0_108_CLOCK_ENABLE_MASK 0x00000001
-#define BCHP_CLKGEN_VICE2_0_INST_CLOCK_ENABLE_VICE2_0_108_CLOCK_ENABLE_SHIFT 0
-#define BCHP_CLKGEN_VICE2_0_INST_CLOCK_ENABLE_VICE2_0_108_CLOCK_ENABLE_DEFAULT 0x00000001
-
-/***************************************************************************
- *VICE2_0_INST_CLOCK_ENABLE_STATUS - Clock Enable Status
- ***************************************************************************/
-/* CLKGEN :: VICE2_0_INST_CLOCK_ENABLE_STATUS :: reserved0 [31:06] */
-#define BCHP_CLKGEN_VICE2_0_INST_CLOCK_ENABLE_STATUS_reserved0_MASK 0xffffffc0
-#define BCHP_CLKGEN_VICE2_0_INST_CLOCK_ENABLE_STATUS_reserved0_SHIFT 6
-
-/* CLKGEN :: VICE2_0_INST_CLOCK_ENABLE_STATUS :: VICE2_0_SCB_CLOCK_ENABLE_STATUS [05:05] */
-#define BCHP_CLKGEN_VICE2_0_INST_CLOCK_ENABLE_STATUS_VICE2_0_SCB_CLOCK_ENABLE_STATUS_MASK 0x00000020
-#define BCHP_CLKGEN_VICE2_0_INST_CLOCK_ENABLE_STATUS_VICE2_0_SCB_CLOCK_ENABLE_STATUS_SHIFT 5
-
-/* CLKGEN :: VICE2_0_INST_CLOCK_ENABLE_STATUS :: VICE2_0_GISB_CLOCK_ENABLE_STATUS [04:04] */
-#define BCHP_CLKGEN_VICE2_0_INST_CLOCK_ENABLE_STATUS_VICE2_0_GISB_CLOCK_ENABLE_STATUS_MASK 0x00000010
-#define BCHP_CLKGEN_VICE2_0_INST_CLOCK_ENABLE_STATUS_VICE2_0_GISB_CLOCK_ENABLE_STATUS_SHIFT 4
-
-/* CLKGEN :: VICE2_0_INST_CLOCK_ENABLE_STATUS :: VICE2_0_CORE_CLOCK_ENABLE_STATUS [03:03] */
-#define BCHP_CLKGEN_VICE2_0_INST_CLOCK_ENABLE_STATUS_VICE2_0_CORE_CLOCK_ENABLE_STATUS_MASK 0x00000008
-#define BCHP_CLKGEN_VICE2_0_INST_CLOCK_ENABLE_STATUS_VICE2_0_CORE_CLOCK_ENABLE_STATUS_SHIFT 3
-
-/* CLKGEN :: VICE2_0_INST_CLOCK_ENABLE_STATUS :: VICE2_0_BVB_216_CLOCK_ENABLE_STATUS [02:02] */
-#define BCHP_CLKGEN_VICE2_0_INST_CLOCK_ENABLE_STATUS_VICE2_0_BVB_216_CLOCK_ENABLE_STATUS_MASK 0x00000004
-#define BCHP_CLKGEN_VICE2_0_INST_CLOCK_ENABLE_STATUS_VICE2_0_BVB_216_CLOCK_ENABLE_STATUS_SHIFT 2
-
-/* CLKGEN :: VICE2_0_INST_CLOCK_ENABLE_STATUS :: VICE2_0_54_CLOCK_ENABLE_STATUS [01:01] */
-#define BCHP_CLKGEN_VICE2_0_INST_CLOCK_ENABLE_STATUS_VICE2_0_54_CLOCK_ENABLE_STATUS_MASK 0x00000002
-#define BCHP_CLKGEN_VICE2_0_INST_CLOCK_ENABLE_STATUS_VICE2_0_54_CLOCK_ENABLE_STATUS_SHIFT 1
-
-/* CLKGEN :: VICE2_0_INST_CLOCK_ENABLE_STATUS :: VICE2_0_108_CLOCK_ENABLE_STATUS [00:00] */
-#define BCHP_CLKGEN_VICE2_0_INST_CLOCK_ENABLE_STATUS_VICE2_0_108_CLOCK_ENABLE_STATUS_MASK 0x00000001
-#define BCHP_CLKGEN_VICE2_0_INST_CLOCK_ENABLE_STATUS_VICE2_0_108_CLOCK_ENABLE_STATUS_SHIFT 0
-
-/***************************************************************************
- *BSPI_CLOCK_SELECT - spi clock control
- ***************************************************************************/
-/* CLKGEN :: BSPI_CLOCK_SELECT :: reserved0 [31:03] */
-#define BCHP_CLKGEN_BSPI_CLOCK_SELECT_reserved0_MASK 0xfffffff8
-#define BCHP_CLKGEN_BSPI_CLOCK_SELECT_reserved0_SHIFT 3
-
-/* CLKGEN :: BSPI_CLOCK_SELECT :: SPI_CLOCK_FREQ_SEL [02:01] */
-#define BCHP_CLKGEN_BSPI_CLOCK_SELECT_SPI_CLOCK_FREQ_SEL_MASK 0x00000006
-#define BCHP_CLKGEN_BSPI_CLOCK_SELECT_SPI_CLOCK_FREQ_SEL_SHIFT 1
-#define BCHP_CLKGEN_BSPI_CLOCK_SELECT_SPI_CLOCK_FREQ_SEL_DEFAULT 0x00000000
-
-/* CLKGEN :: BSPI_CLOCK_SELECT :: SPI_CLOCK_OVERRIDE_STRAP [00:00] */
-#define BCHP_CLKGEN_BSPI_CLOCK_SELECT_SPI_CLOCK_OVERRIDE_STRAP_MASK 0x00000001
-#define BCHP_CLKGEN_BSPI_CLOCK_SELECT_SPI_CLOCK_OVERRIDE_STRAP_SHIFT 0
-#define BCHP_CLKGEN_BSPI_CLOCK_SELECT_SPI_CLOCK_OVERRIDE_STRAP_DEFAULT 0x00000000
-
-/***************************************************************************
- *USBPHY_REF_CLOCK_BYPASS - bypass USBPHY reference clocks
- ***************************************************************************/
-/* CLKGEN :: USBPHY_REF_CLOCK_BYPASS :: reserved0 [31:03] */
-#define BCHP_CLKGEN_USBPHY_REF_CLOCK_BYPASS_reserved0_MASK 0xfffffff8
-#define BCHP_CLKGEN_USBPHY_REF_CLOCK_BYPASS_reserved0_SHIFT 3
-
-/* CLKGEN :: USBPHY_REF_CLOCK_BYPASS :: BYP_USB1_USB20_60MHZ_REFCLK [02:02] */
-#define BCHP_CLKGEN_USBPHY_REF_CLOCK_BYPASS_BYP_USB1_USB20_60MHZ_REFCLK_MASK 0x00000004
-#define BCHP_CLKGEN_USBPHY_REF_CLOCK_BYPASS_BYP_USB1_USB20_60MHZ_REFCLK_SHIFT 2
-#define BCHP_CLKGEN_USBPHY_REF_CLOCK_BYPASS_BYP_USB1_USB20_60MHZ_REFCLK_DEFAULT 0x00000000
-
-/* CLKGEN :: USBPHY_REF_CLOCK_BYPASS :: BYP_USB0_USB20_60MHZ_REFCLK [01:01] */
-#define BCHP_CLKGEN_USBPHY_REF_CLOCK_BYPASS_BYP_USB0_USB20_60MHZ_REFCLK_MASK 0x00000002
-#define BCHP_CLKGEN_USBPHY_REF_CLOCK_BYPASS_BYP_USB0_USB20_60MHZ_REFCLK_SHIFT 1
-#define BCHP_CLKGEN_USBPHY_REF_CLOCK_BYPASS_BYP_USB0_USB20_60MHZ_REFCLK_DEFAULT 0x00000000
-
-/* CLKGEN :: USBPHY_REF_CLOCK_BYPASS :: BYP_USB0_USB30_50MHZ_REFCLK [00:00] */
-#define BCHP_CLKGEN_USBPHY_REF_CLOCK_BYPASS_BYP_USB0_USB30_50MHZ_REFCLK_MASK 0x00000001
-#define BCHP_CLKGEN_USBPHY_REF_CLOCK_BYPASS_BYP_USB0_USB30_50MHZ_REFCLK_SHIFT 0
-#define BCHP_CLKGEN_USBPHY_REF_CLOCK_BYPASS_BYP_USB0_USB30_50MHZ_REFCLK_DEFAULT 0x00000000
-
-/***************************************************************************
- *EPHY_REF_CLOCK_BYPASS - bypass EPHY reference clocks
- ***************************************************************************/
-/* CLKGEN :: EPHY_REF_CLOCK_BYPASS :: reserved0 [31:01] */
-#define BCHP_CLKGEN_EPHY_REF_CLOCK_BYPASS_reserved0_MASK 0xfffffffe
-#define BCHP_CLKGEN_EPHY_REF_CLOCK_BYPASS_reserved0_SHIFT 1
-
-/* CLKGEN :: EPHY_REF_CLOCK_BYPASS :: BYP_EN_EPHY_REFCLK [00:00] */
-#define BCHP_CLKGEN_EPHY_REF_CLOCK_BYPASS_BYP_EN_EPHY_REFCLK_MASK 0x00000001
-#define BCHP_CLKGEN_EPHY_REF_CLOCK_BYPASS_BYP_EN_EPHY_REFCLK_SHIFT 0
-#define BCHP_CLKGEN_EPHY_REF_CLOCK_BYPASS_BYP_EN_EPHY_REFCLK_DEFAULT 0x00000000
-
-/***************************************************************************
- *HVD_PLL_CTRL_WRAPPER_CONTROL - HVD_PLL_CTRL_WRAPPER control
- ***************************************************************************/
-/* CLKGEN :: HVD_PLL_CTRL_WRAPPER_CONTROL :: reserved0 [31:02] */
-#define BCHP_CLKGEN_HVD_PLL_CTRL_WRAPPER_CONTROL_reserved0_MASK 0xfffffffc
-#define BCHP_CLKGEN_HVD_PLL_CTRL_WRAPPER_CONTROL_reserved0_SHIFT 2
-
-/* CLKGEN :: HVD_PLL_CTRL_WRAPPER_CONTROL :: PWRDN_PLL_REQ [01:01] */
-#define BCHP_CLKGEN_HVD_PLL_CTRL_WRAPPER_CONTROL_PWRDN_PLL_REQ_MASK 0x00000002
-#define BCHP_CLKGEN_HVD_PLL_CTRL_WRAPPER_CONTROL_PWRDN_PLL_REQ_SHIFT 1
-#define BCHP_CLKGEN_HVD_PLL_CTRL_WRAPPER_CONTROL_PWRDN_PLL_REQ_DEFAULT 0x00000000
-
-/* CLKGEN :: HVD_PLL_CTRL_WRAPPER_CONTROL :: SW_SM_OVERRIDE [00:00] */
-#define BCHP_CLKGEN_HVD_PLL_CTRL_WRAPPER_CONTROL_SW_SM_OVERRIDE_MASK 0x00000001
-#define BCHP_CLKGEN_HVD_PLL_CTRL_WRAPPER_CONTROL_SW_SM_OVERRIDE_SHIFT 0
-#define BCHP_CLKGEN_HVD_PLL_CTRL_WRAPPER_CONTROL_SW_SM_OVERRIDE_DEFAULT 0x00000000
-
-/***************************************************************************
- *MOCA_PLL_CTRL_WRAPPER_CONTROL - MOCA_PLL_CTRL_WRAPPER control
- ***************************************************************************/
-/* CLKGEN :: MOCA_PLL_CTRL_WRAPPER_CONTROL :: reserved0 [31:02] */
-#define BCHP_CLKGEN_MOCA_PLL_CTRL_WRAPPER_CONTROL_reserved0_MASK 0xfffffffc
-#define BCHP_CLKGEN_MOCA_PLL_CTRL_WRAPPER_CONTROL_reserved0_SHIFT 2
-
-/* CLKGEN :: MOCA_PLL_CTRL_WRAPPER_CONTROL :: PWRDN_PLL_REQ [01:01] */
-#define BCHP_CLKGEN_MOCA_PLL_CTRL_WRAPPER_CONTROL_PWRDN_PLL_REQ_MASK 0x00000002
-#define BCHP_CLKGEN_MOCA_PLL_CTRL_WRAPPER_CONTROL_PWRDN_PLL_REQ_SHIFT 1
-#define BCHP_CLKGEN_MOCA_PLL_CTRL_WRAPPER_CONTROL_PWRDN_PLL_REQ_DEFAULT 0x00000000
-
-/* CLKGEN :: MOCA_PLL_CTRL_WRAPPER_CONTROL :: SW_SM_OVERRIDE [00:00] */
-#define BCHP_CLKGEN_MOCA_PLL_CTRL_WRAPPER_CONTROL_SW_SM_OVERRIDE_MASK 0x00000001
-#define BCHP_CLKGEN_MOCA_PLL_CTRL_WRAPPER_CONTROL_SW_SM_OVERRIDE_SHIFT 0
-#define BCHP_CLKGEN_MOCA_PLL_CTRL_WRAPPER_CONTROL_SW_SM_OVERRIDE_DEFAULT 0x00000000
-
-/***************************************************************************
- *NETWORK_PLL_CTRL_WRAPPER_CONTROL - NETWORK_PLL_CTRL_WRAPPER control
- ***************************************************************************/
-/* CLKGEN :: NETWORK_PLL_CTRL_WRAPPER_CONTROL :: reserved0 [31:02] */
-#define BCHP_CLKGEN_NETWORK_PLL_CTRL_WRAPPER_CONTROL_reserved0_MASK 0xfffffffc
-#define BCHP_CLKGEN_NETWORK_PLL_CTRL_WRAPPER_CONTROL_reserved0_SHIFT 2
-
-/* CLKGEN :: NETWORK_PLL_CTRL_WRAPPER_CONTROL :: PWRDN_PLL_REQ [01:01] */
-#define BCHP_CLKGEN_NETWORK_PLL_CTRL_WRAPPER_CONTROL_PWRDN_PLL_REQ_MASK 0x00000002
-#define BCHP_CLKGEN_NETWORK_PLL_CTRL_WRAPPER_CONTROL_PWRDN_PLL_REQ_SHIFT 1
-#define BCHP_CLKGEN_NETWORK_PLL_CTRL_WRAPPER_CONTROL_PWRDN_PLL_REQ_DEFAULT 0x00000000
-
-/* CLKGEN :: NETWORK_PLL_CTRL_WRAPPER_CONTROL :: SW_SM_OVERRIDE [00:00] */
-#define BCHP_CLKGEN_NETWORK_PLL_CTRL_WRAPPER_CONTROL_SW_SM_OVERRIDE_MASK 0x00000001
-#define BCHP_CLKGEN_NETWORK_PLL_CTRL_WRAPPER_CONTROL_SW_SM_OVERRIDE_SHIFT 0
-#define BCHP_CLKGEN_NETWORK_PLL_CTRL_WRAPPER_CONTROL_SW_SM_OVERRIDE_DEFAULT 0x00000000
-
-/***************************************************************************
- *RAAGA_PLL_CTRL_WRAPPER_CONTROL - RAAGA_PLL_CTRL_WRAPPER control
- ***************************************************************************/
-/* CLKGEN :: RAAGA_PLL_CTRL_WRAPPER_CONTROL :: reserved0 [31:02] */
-#define BCHP_CLKGEN_RAAGA_PLL_CTRL_WRAPPER_CONTROL_reserved0_MASK 0xfffffffc
-#define BCHP_CLKGEN_RAAGA_PLL_CTRL_WRAPPER_CONTROL_reserved0_SHIFT 2
-
-/* CLKGEN :: RAAGA_PLL_CTRL_WRAPPER_CONTROL :: PWRDN_PLL_REQ [01:01] */
-#define BCHP_CLKGEN_RAAGA_PLL_CTRL_WRAPPER_CONTROL_PWRDN_PLL_REQ_MASK 0x00000002
-#define BCHP_CLKGEN_RAAGA_PLL_CTRL_WRAPPER_CONTROL_PWRDN_PLL_REQ_SHIFT 1
-#define BCHP_CLKGEN_RAAGA_PLL_CTRL_WRAPPER_CONTROL_PWRDN_PLL_REQ_DEFAULT 0x00000000
-
-/* CLKGEN :: RAAGA_PLL_CTRL_WRAPPER_CONTROL :: SW_SM_OVERRIDE [00:00] */
-#define BCHP_CLKGEN_RAAGA_PLL_CTRL_WRAPPER_CONTROL_SW_SM_OVERRIDE_MASK 0x00000001
-#define BCHP_CLKGEN_RAAGA_PLL_CTRL_WRAPPER_CONTROL_SW_SM_OVERRIDE_SHIFT 0
-#define BCHP_CLKGEN_RAAGA_PLL_CTRL_WRAPPER_CONTROL_SW_SM_OVERRIDE_DEFAULT 0x00000000
-
-/***************************************************************************
- *VCXO0_PLL_CTRL_WRAPPER_CONTROL - VCXO0_PLL_CTRL_WRAPPER control
- ***************************************************************************/
-/* CLKGEN :: VCXO0_PLL_CTRL_WRAPPER_CONTROL :: reserved0 [31:02] */
-#define BCHP_CLKGEN_VCXO0_PLL_CTRL_WRAPPER_CONTROL_reserved0_MASK 0xfffffffc
-#define BCHP_CLKGEN_VCXO0_PLL_CTRL_WRAPPER_CONTROL_reserved0_SHIFT 2
-
-/* CLKGEN :: VCXO0_PLL_CTRL_WRAPPER_CONTROL :: PWRDN_PLL_REQ [01:01] */
-#define BCHP_CLKGEN_VCXO0_PLL_CTRL_WRAPPER_CONTROL_PWRDN_PLL_REQ_MASK 0x00000002
-#define BCHP_CLKGEN_VCXO0_PLL_CTRL_WRAPPER_CONTROL_PWRDN_PLL_REQ_SHIFT 1
-#define BCHP_CLKGEN_VCXO0_PLL_CTRL_WRAPPER_CONTROL_PWRDN_PLL_REQ_DEFAULT 0x00000000
-
-/* CLKGEN :: VCXO0_PLL_CTRL_WRAPPER_CONTROL :: SW_SM_OVERRIDE [00:00] */
-#define BCHP_CLKGEN_VCXO0_PLL_CTRL_WRAPPER_CONTROL_SW_SM_OVERRIDE_MASK 0x00000001
-#define BCHP_CLKGEN_VCXO0_PLL_CTRL_WRAPPER_CONTROL_SW_SM_OVERRIDE_SHIFT 0
-#define BCHP_CLKGEN_VCXO0_PLL_CTRL_WRAPPER_CONTROL_SW_SM_OVERRIDE_DEFAULT 0x00000000
-
-/***************************************************************************
- *VCXO1_PLL_CTRL_WRAPPER_CONTROL - VCXO1_PLL_CTRL_WRAPPER control
- ***************************************************************************/
-/* CLKGEN :: VCXO1_PLL_CTRL_WRAPPER_CONTROL :: reserved0 [31:02] */
-#define BCHP_CLKGEN_VCXO1_PLL_CTRL_WRAPPER_CONTROL_reserved0_MASK 0xfffffffc
-#define BCHP_CLKGEN_VCXO1_PLL_CTRL_WRAPPER_CONTROL_reserved0_SHIFT 2
-
-/* CLKGEN :: VCXO1_PLL_CTRL_WRAPPER_CONTROL :: PWRDN_PLL_REQ [01:01] */
-#define BCHP_CLKGEN_VCXO1_PLL_CTRL_WRAPPER_CONTROL_PWRDN_PLL_REQ_MASK 0x00000002
-#define BCHP_CLKGEN_VCXO1_PLL_CTRL_WRAPPER_CONTROL_PWRDN_PLL_REQ_SHIFT 1
-#define BCHP_CLKGEN_VCXO1_PLL_CTRL_WRAPPER_CONTROL_PWRDN_PLL_REQ_DEFAULT 0x00000000
-
-/* CLKGEN :: VCXO1_PLL_CTRL_WRAPPER_CONTROL :: SW_SM_OVERRIDE [00:00] */
-#define BCHP_CLKGEN_VCXO1_PLL_CTRL_WRAPPER_CONTROL_SW_SM_OVERRIDE_MASK 0x00000001
-#define BCHP_CLKGEN_VCXO1_PLL_CTRL_WRAPPER_CONTROL_SW_SM_OVERRIDE_SHIFT 0
-#define BCHP_CLKGEN_VCXO1_PLL_CTRL_WRAPPER_CONTROL_SW_SM_OVERRIDE_DEFAULT 0x00000000
-
-/***************************************************************************
- *V3D_PLL_CTRL_WRAPPER_CONTROL - V3D_PLL_CTRL_WRAPPER control
- ***************************************************************************/
-/* CLKGEN :: V3D_PLL_CTRL_WRAPPER_CONTROL :: reserved0 [31:02] */
-#define BCHP_CLKGEN_V3D_PLL_CTRL_WRAPPER_CONTROL_reserved0_MASK 0xfffffffc
-#define BCHP_CLKGEN_V3D_PLL_CTRL_WRAPPER_CONTROL_reserved0_SHIFT 2
-
-/* CLKGEN :: V3D_PLL_CTRL_WRAPPER_CONTROL :: PWRDN_PLL_REQ [01:01] */
-#define BCHP_CLKGEN_V3D_PLL_CTRL_WRAPPER_CONTROL_PWRDN_PLL_REQ_MASK 0x00000002
-#define BCHP_CLKGEN_V3D_PLL_CTRL_WRAPPER_CONTROL_PWRDN_PLL_REQ_SHIFT 1
-#define BCHP_CLKGEN_V3D_PLL_CTRL_WRAPPER_CONTROL_PWRDN_PLL_REQ_DEFAULT 0x00000000
-
-/* CLKGEN :: V3D_PLL_CTRL_WRAPPER_CONTROL :: SW_SM_OVERRIDE [00:00] */
-#define BCHP_CLKGEN_V3D_PLL_CTRL_WRAPPER_CONTROL_SW_SM_OVERRIDE_MASK 0x00000001
-#define BCHP_CLKGEN_V3D_PLL_CTRL_WRAPPER_CONTROL_SW_SM_OVERRIDE_SHIFT 0
-#define BCHP_CLKGEN_V3D_PLL_CTRL_WRAPPER_CONTROL_SW_SM_OVERRIDE_DEFAULT 0x00000000
-
-/***************************************************************************
- *LC_PLL_CTRL_WRAPPER_CONTROL - LC_PLL_CTRL_WRAPPER control
- ***************************************************************************/
-/* CLKGEN :: LC_PLL_CTRL_WRAPPER_CONTROL :: reserved0 [31:02] */
-#define BCHP_CLKGEN_LC_PLL_CTRL_WRAPPER_CONTROL_reserved0_MASK 0xfffffffc
-#define BCHP_CLKGEN_LC_PLL_CTRL_WRAPPER_CONTROL_reserved0_SHIFT 2
-
-/* CLKGEN :: LC_PLL_CTRL_WRAPPER_CONTROL :: PWRDN_PLL_REQ [01:01] */
-#define BCHP_CLKGEN_LC_PLL_CTRL_WRAPPER_CONTROL_PWRDN_PLL_REQ_MASK 0x00000002
-#define BCHP_CLKGEN_LC_PLL_CTRL_WRAPPER_CONTROL_PWRDN_PLL_REQ_SHIFT 1
-#define BCHP_CLKGEN_LC_PLL_CTRL_WRAPPER_CONTROL_PWRDN_PLL_REQ_DEFAULT 0x00000000
-
-/* CLKGEN :: LC_PLL_CTRL_WRAPPER_CONTROL :: SW_SM_OVERRIDE [00:00] */
-#define BCHP_CLKGEN_LC_PLL_CTRL_WRAPPER_CONTROL_SW_SM_OVERRIDE_MASK 0x00000001
-#define BCHP_CLKGEN_LC_PLL_CTRL_WRAPPER_CONTROL_SW_SM_OVERRIDE_SHIFT 0
-#define BCHP_CLKGEN_LC_PLL_CTRL_WRAPPER_CONTROL_SW_SM_OVERRIDE_DEFAULT 0x00000000
-
-/***************************************************************************
- *SYS0_PLL_CTRL_WRAPPER_CONTROL - SYS0_PLL_CTRL_WRAPPER control
- ***************************************************************************/
-/* CLKGEN :: SYS0_PLL_CTRL_WRAPPER_CONTROL :: reserved0 [31:01] */
-#define BCHP_CLKGEN_SYS0_PLL_CTRL_WRAPPER_CONTROL_reserved0_MASK 0xfffffffe
-#define BCHP_CLKGEN_SYS0_PLL_CTRL_WRAPPER_CONTROL_reserved0_SHIFT 1
-
-/* CLKGEN :: SYS0_PLL_CTRL_WRAPPER_CONTROL :: SW_SM_OVERRIDE [00:00] */
-#define BCHP_CLKGEN_SYS0_PLL_CTRL_WRAPPER_CONTROL_SW_SM_OVERRIDE_MASK 0x00000001
-#define BCHP_CLKGEN_SYS0_PLL_CTRL_WRAPPER_CONTROL_SW_SM_OVERRIDE_SHIFT 0
-#define BCHP_CLKGEN_SYS0_PLL_CTRL_WRAPPER_CONTROL_SW_SM_OVERRIDE_DEFAULT 0x00000000
-
-/***************************************************************************
- *XPT_PLL_CTRL_WRAPPER_CONTROL - XPT_PLL_CTRL_WRAPPER control
- ***************************************************************************/
-/* CLKGEN :: XPT_PLL_CTRL_WRAPPER_CONTROL :: reserved0 [31:01] */
-#define BCHP_CLKGEN_XPT_PLL_CTRL_WRAPPER_CONTROL_reserved0_MASK 0xfffffffe
-#define BCHP_CLKGEN_XPT_PLL_CTRL_WRAPPER_CONTROL_reserved0_SHIFT 1
-
-/* CLKGEN :: XPT_PLL_CTRL_WRAPPER_CONTROL :: SW_SM_OVERRIDE [00:00] */
-#define BCHP_CLKGEN_XPT_PLL_CTRL_WRAPPER_CONTROL_SW_SM_OVERRIDE_MASK 0x00000001
-#define BCHP_CLKGEN_XPT_PLL_CTRL_WRAPPER_CONTROL_SW_SM_OVERRIDE_SHIFT 0
-#define BCHP_CLKGEN_XPT_PLL_CTRL_WRAPPER_CONTROL_SW_SM_OVERRIDE_DEFAULT 0x00000000
-
-/***************************************************************************
- *CPU_PLL_CTRL_WRAPPER_CONTROL - CPU_PLL_CTRL_WRAPPER control
- ***************************************************************************/
-/* CLKGEN :: CPU_PLL_CTRL_WRAPPER_CONTROL :: reserved0 [31:01] */
-#define BCHP_CLKGEN_CPU_PLL_CTRL_WRAPPER_CONTROL_reserved0_MASK 0xfffffffe
-#define BCHP_CLKGEN_CPU_PLL_CTRL_WRAPPER_CONTROL_reserved0_SHIFT 1
-
-/* CLKGEN :: CPU_PLL_CTRL_WRAPPER_CONTROL :: SW_SM_OVERRIDE [00:00] */
-#define BCHP_CLKGEN_CPU_PLL_CTRL_WRAPPER_CONTROL_SW_SM_OVERRIDE_MASK 0x00000001
-#define BCHP_CLKGEN_CPU_PLL_CTRL_WRAPPER_CONTROL_SW_SM_OVERRIDE_SHIFT 0
-#define BCHP_CLKGEN_CPU_PLL_CTRL_WRAPPER_CONTROL_SW_SM_OVERRIDE_DEFAULT 0x00000000
-
-/***************************************************************************
- *SDS_PLL_CTRL_WRAPPER_CONTROL - SDS_PLL_CTRL_WRAPPER control
- ***************************************************************************/
-/* CLKGEN :: SDS_PLL_CTRL_WRAPPER_CONTROL :: reserved0 [31:02] */
-#define BCHP_CLKGEN_SDS_PLL_CTRL_WRAPPER_CONTROL_reserved0_MASK 0xfffffffc
-#define BCHP_CLKGEN_SDS_PLL_CTRL_WRAPPER_CONTROL_reserved0_SHIFT 2
-
-/* CLKGEN :: SDS_PLL_CTRL_WRAPPER_CONTROL :: PWRDN_PLL_REQ [01:01] */
-#define BCHP_CLKGEN_SDS_PLL_CTRL_WRAPPER_CONTROL_PWRDN_PLL_REQ_MASK 0x00000002
-#define BCHP_CLKGEN_SDS_PLL_CTRL_WRAPPER_CONTROL_PWRDN_PLL_REQ_SHIFT 1
-#define BCHP_CLKGEN_SDS_PLL_CTRL_WRAPPER_CONTROL_PWRDN_PLL_REQ_DEFAULT 0x00000000
-
-/* CLKGEN :: SDS_PLL_CTRL_WRAPPER_CONTROL :: SW_SM_OVERRIDE [00:00] */
-#define BCHP_CLKGEN_SDS_PLL_CTRL_WRAPPER_CONTROL_SW_SM_OVERRIDE_MASK 0x00000001
-#define BCHP_CLKGEN_SDS_PLL_CTRL_WRAPPER_CONTROL_SW_SM_OVERRIDE_SHIFT 0
-#define BCHP_CLKGEN_SDS_PLL_CTRL_WRAPPER_CONTROL_SW_SM_OVERRIDE_DEFAULT 0x00000000
-
-/***************************************************************************
- *SC0_PLL_CTRL_WRAPPER_CONTROL - SC0_PLL_CTRL_WRAPPER control
- ***************************************************************************/
-/* CLKGEN :: SC0_PLL_CTRL_WRAPPER_CONTROL :: reserved0 [31:02] */
-#define BCHP_CLKGEN_SC0_PLL_CTRL_WRAPPER_CONTROL_reserved0_MASK 0xfffffffc
-#define BCHP_CLKGEN_SC0_PLL_CTRL_WRAPPER_CONTROL_reserved0_SHIFT 2
-
-/* CLKGEN :: SC0_PLL_CTRL_WRAPPER_CONTROL :: PWRDN_PLL_REQ [01:01] */
-#define BCHP_CLKGEN_SC0_PLL_CTRL_WRAPPER_CONTROL_PWRDN_PLL_REQ_MASK 0x00000002
-#define BCHP_CLKGEN_SC0_PLL_CTRL_WRAPPER_CONTROL_PWRDN_PLL_REQ_SHIFT 1
-#define BCHP_CLKGEN_SC0_PLL_CTRL_WRAPPER_CONTROL_PWRDN_PLL_REQ_DEFAULT 0x00000000
-
-/* CLKGEN :: SC0_PLL_CTRL_WRAPPER_CONTROL :: SW_SM_OVERRIDE [00:00] */
-#define BCHP_CLKGEN_SC0_PLL_CTRL_WRAPPER_CONTROL_SW_SM_OVERRIDE_MASK 0x00000001
-#define BCHP_CLKGEN_SC0_PLL_CTRL_WRAPPER_CONTROL_SW_SM_OVERRIDE_SHIFT 0
-#define BCHP_CLKGEN_SC0_PLL_CTRL_WRAPPER_CONTROL_SW_SM_OVERRIDE_DEFAULT 0x00000000
-
-/***************************************************************************
- *SC1_PLL_CTRL_WRAPPER_CONTROL - SC1_PLL_CTRL_WRAPPER control
- ***************************************************************************/
-/* CLKGEN :: SC1_PLL_CTRL_WRAPPER_CONTROL :: reserved0 [31:02] */
-#define BCHP_CLKGEN_SC1_PLL_CTRL_WRAPPER_CONTROL_reserved0_MASK 0xfffffffc
-#define BCHP_CLKGEN_SC1_PLL_CTRL_WRAPPER_CONTROL_reserved0_SHIFT 2
-
-/* CLKGEN :: SC1_PLL_CTRL_WRAPPER_CONTROL :: PWRDN_PLL_REQ [01:01] */
-#define BCHP_CLKGEN_SC1_PLL_CTRL_WRAPPER_CONTROL_PWRDN_PLL_REQ_MASK 0x00000002
-#define BCHP_CLKGEN_SC1_PLL_CTRL_WRAPPER_CONTROL_PWRDN_PLL_REQ_SHIFT 1
-#define BCHP_CLKGEN_SC1_PLL_CTRL_WRAPPER_CONTROL_PWRDN_PLL_REQ_DEFAULT 0x00000000
-
-/* CLKGEN :: SC1_PLL_CTRL_WRAPPER_CONTROL :: SW_SM_OVERRIDE [00:00] */
-#define BCHP_CLKGEN_SC1_PLL_CTRL_WRAPPER_CONTROL_SW_SM_OVERRIDE_MASK 0x00000001
-#define BCHP_CLKGEN_SC1_PLL_CTRL_WRAPPER_CONTROL_SW_SM_OVERRIDE_SHIFT 0
-#define BCHP_CLKGEN_SC1_PLL_CTRL_WRAPPER_CONTROL_SW_SM_OVERRIDE_DEFAULT 0x00000000
-
-/***************************************************************************
- *PLL_SC0_PLL_LDO_PWRON - LDO Power on
- ***************************************************************************/
-/* CLKGEN :: PLL_SC0_PLL_LDO_PWRON :: reserved0 [31:01] */
-#define BCHP_CLKGEN_PLL_SC0_PLL_LDO_PWRON_reserved0_MASK 0xfffffffe
-#define BCHP_CLKGEN_PLL_SC0_PLL_LDO_PWRON_reserved0_SHIFT 1
-
-/* CLKGEN :: PLL_SC0_PLL_LDO_PWRON :: LDO_PWRON_PLL [00:00] */
-#define BCHP_CLKGEN_PLL_SC0_PLL_LDO_PWRON_LDO_PWRON_PLL_MASK 0x00000001
-#define BCHP_CLKGEN_PLL_SC0_PLL_LDO_PWRON_LDO_PWRON_PLL_SHIFT 0
-#define BCHP_CLKGEN_PLL_SC0_PLL_LDO_PWRON_LDO_PWRON_PLL_DEFAULT 0x00000001
-
-/***************************************************************************
- *PLL_SC1_PLL_LDO_PWRON - LDO Power on
- ***************************************************************************/
-/* CLKGEN :: PLL_SC1_PLL_LDO_PWRON :: reserved0 [31:01] */
-#define BCHP_CLKGEN_PLL_SC1_PLL_LDO_PWRON_reserved0_MASK 0xfffffffe
-#define BCHP_CLKGEN_PLL_SC1_PLL_LDO_PWRON_reserved0_SHIFT 1
-
-/* CLKGEN :: PLL_SC1_PLL_LDO_PWRON :: LDO_PWRON_PLL [00:00] */
-#define BCHP_CLKGEN_PLL_SC1_PLL_LDO_PWRON_LDO_PWRON_PLL_MASK 0x00000001
-#define BCHP_CLKGEN_PLL_SC1_PLL_LDO_PWRON_LDO_PWRON_PLL_SHIFT 0
-#define BCHP_CLKGEN_PLL_SC1_PLL_LDO_PWRON_LDO_PWRON_PLL_DEFAULT 0x00000001
-
-#endif /* #ifndef BCHP_CLKGEN_H__ */
-
-/* End of File */
diff --git a/include/linux/brcmstb/7366b0/bchp_common.h b/include/linux/brcmstb/7366b0/bchp_common.h
deleted file mode 100644
index d8dea15..0000000
--- a/include/linux/brcmstb/7366b0/bchp_common.h
+++ /dev/null
@@ -1,4373 +0,0 @@
-/***************************************************************************
- * Copyright (c) 1999-2014, Broadcom Corporation
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
- *
- * Module Description:
- * DO NOT EDIT THIS FILE DIRECTLY
- *
- * This module was generated magically with RDB from a source description
- * file. You must edit the source file for changes to be made to this file.
- *
- *
- * Date: Generated on Wed Sep 3 14:59:28 2014
- * Full Compile MD5 Checksum 10187d4079392bab2546025f43274d34
- * (minus title and desc)
- * MD5 Checksum c1587c5e16f21f52e852e7c7a65c7811
- *
- * Compiled with: RDB Utility combo_header.pl
- * RDB Parser 3.0
- * unknown unknown
- * Perl Interpreter 5.008005
- * Operating System linux
- *
- * Revision History:
- *
- * $brcm_Log: $
- *
- ***************************************************************************/
-
-#ifndef BCHP_COMMON_H__
-#define BCHP_COMMON_H__
-
-/**
- * m = memory, c = core, r = register, f = field, d = data.
- */
-#if !defined(GET_FIELD) && !defined(SET_FIELD)
-#define BRCM_MASK(c,r,f) c##_##r##_##f##_MASK
-#define BRCM_SHIFT(c,r,f) c##_##r##_##f##_SHIFT
-
-#define GET_FIELD(m,c,r,f) \
-((((m) & BRCM_MASK(c,r,f)) >> BRCM_SHIFT(c,r,f)))
-
-#define SET_FIELD(m,c,r,f,d) \
-((m) = (((m) & ~BRCM_MASK(c,r,f)) | ((((d)) << BRCM_SHIFT(c,r,f)) & BRCM_MASK(c,r,f))))
-
-#define SET_TYPE_FIELD(m,c,r,f,d) SET_FIELD(m,c,r,f,c##_##d)
-#define SET_NAME_FIELD(m,c,r,f,d) SET_FIELD(m,c,r,f,c##_##r##_##f##_##d)
-#define SET_VALUE_FIELD(m,c,r,f,d) SET_FIELD(m,c,r,f,d)
-
-#endif /* GET & SET */
-
-/***************************************************************************
- *BCM7366_B0
- ***************************************************************************/
-#define BCHP_PHYSICAL_OFFSET 0xf0000000
-#define BCHP_REGISTER_START 0x00100000 /* HEVD_OL_CPU_REGS_0 is first */
-#define BCHP_REGISTER_END 0x014e1a08 /* GCI_2 is last */
-#define BCHP_REGISTER_SIZE 0x004f8682 /* Number of registers */
-
-/****************************************************************************
- * Core instance register start address.
- ***************************************************************************/
-#define BCHP_HEVD_OL_CPU_REGS_0_REG_START 0x00100000
-#define BCHP_HEVD_OL_CPU_REGS_0_REG_END 0x00100108
-#define BCHP_HEVD_OL_CPU_DMA_0_REG_START 0x00100400
-#define BCHP_HEVD_OL_CPU_DMA_0_REG_END 0x00100440
-#define BCHP_HEVD_OL_CPU_DEBUG_0_REG_START 0x00100800
-#define BCHP_HEVD_OL_CPU_DEBUG_0_REG_END 0x00100ffc
-#define BCHP_HEVD_OL_SINT_0_REG_START 0x00101000
-#define BCHP_HEVD_OL_SINT_0_REG_END 0x00101028
-#define BCHP_HEVD_OL_LDST_0_REG_START 0x00108000
-#define BCHP_HEVD_OL_LDST_0_REG_END 0x0010fffc
-#define BCHP_REG_CABAC2BINS_0_REG_START 0x00110b00
-#define BCHP_REG_CABAC2BINS_0_REG_END 0x00110bfc
-#define BCHP_REG_CABAC2BINS2_0_REG_START 0x00112400
-#define BCHP_REG_CABAC2BINS2_0_REG_END 0x001127fc
-#define BCHP_HEVD_CABAC_0_REG_START 0x00113000
-#define BCHP_HEVD_CABAC_0_REG_END 0x0011307c
-#define BCHP_HEVD_OL_CTL_0_REG_START 0x00114000
-#define BCHP_HEVD_OL_CTL_0_REG_END 0x001151fc
-#define BCHP_DECODE_MAIN_0_REG_START 0x00120100
-#define BCHP_DECODE_MAIN_0_REG_END 0x001201fc
-#define BCHP_DECODE_MCOM_0_REG_START 0x00120300
-#define BCHP_DECODE_MCOM_0_REG_END 0x0012031c
-#define BCHP_DECODE_SPRE_0_REG_START 0x00120320
-#define BCHP_DECODE_SPRE_0_REG_END 0x0012033c
-#define BCHP_DECODE_WPRD_0_REG_START 0x00120340
-#define BCHP_DECODE_WPRD_0_REG_END 0x0012035c
-#define BCHP_DECODE_DQNT_0_REG_START 0x00120400
-#define BCHP_DECODE_DQNT_0_REG_END 0x0012045c
-#define BCHP_DECODE_DQNT_8X8_0_REG_START 0x00120500
-#define BCHP_DECODE_DQNT_8X8_0_REG_END 0x0012057c
-#define BCHP_DECODE_VP8_XFRM_0_REG_START 0x00120600
-#define BCHP_DECODE_VP8_XFRM_0_REG_END 0x0012060c
-#define BCHP_DECODE_VP6_DCP_0_REG_START 0x00120620
-#define BCHP_DECODE_VP6_DCP_0_REG_END 0x0012062c
-#define BCHP_DECODE_XFRM_0_REG_START 0x00120700
-#define BCHP_DECODE_XFRM_0_REG_END 0x0012071c
-#define BCHP_DECODE_DBLK_0_REG_START 0x00120720
-#define BCHP_DECODE_DBLK_0_REG_END 0x0012073c
-#define BCHP_DECODE_MB_0_REG_START 0x00120740
-#define BCHP_DECODE_MB_0_REG_END 0x0012075c
-#define BCHP_DECODE_SINT_0_REG_START 0x00120c00
-#define BCHP_DECODE_SINT_0_REG_END 0x00120dfc
-#define BCHP_DECODE_WPTBL_0_REG_START 0x00123000
-#define BCHP_DECODE_WPTBL_0_REG_END 0x001231fc
-#define BCHP_HEVD_BE_GLOBAL_0_REG_START 0x00124000
-#define BCHP_HEVD_BE_GLOBAL_0_REG_END 0x00124030
-#define BCHP_HEVD_IXFORM_0_REG_START 0x00124100
-#define BCHP_HEVD_IXFORM_0_REG_END 0x001241fc
-#define BCHP_HEVD_MCOMP_0_REG_START 0x00124200
-#define BCHP_HEVD_MCOMP_0_REG_END 0x001242fc
-#define BCHP_HEVD_SPRED_0_REG_START 0x00124300
-#define BCHP_HEVD_SPRED_0_REG_END 0x001243f0
-#define BCHP_HEVD_FILTER_0_REG_START 0x00124400
-#define BCHP_HEVD_FILTER_0_REG_END 0x001244fc
-#define BCHP_HEVD_OUTPUT_0_REG_START 0x00124500
-#define BCHP_HEVD_OUTPUT_0_REG_END 0x001245fc
-#define BCHP_HEVD_MARKER_0_REG_START 0x00124f00
-#define BCHP_HEVD_MARKER_0_REG_END 0x00124f7c
-#define BCHP_HEVD_FE_CTRL_0_REG_START 0x00125000
-#define BCHP_HEVD_FE_CTRL_0_REG_END 0x00125048
-#define BCHP_HEVD_STRM_IN_0_REG_START 0x00125100
-#define BCHP_HEVD_STRM_IN_0_REG_END 0x00125118
-#define BCHP_HEVD_CMDBUS_XMIT_0_REG_START 0x00125200
-#define BCHP_HEVD_CMDBUS_XMIT_0_REG_END 0x00125230
-#define BCHP_HEVD_VECGEN_0_REG_START 0x00125400
-#define BCHP_HEVD_VECGEN_0_REG_END 0x0012568c
-#define BCHP_DCD_PIPE_CTL_0_REG_START 0x00126000
-#define BCHP_DCD_PIPE_CTL_0_REG_END 0x00126404
-#define BCHP_HEVD_PCACHE_0_REG_START 0x00126800
-#define BCHP_HEVD_PCACHE_0_REG_END 0x00126834
-#define BCHP_HEVD_PFRI_0_REG_START 0x00126a00
-#define BCHP_HEVD_PFRI_0_REG_END 0x00126b58
-#define BCHP_RVC_0_REG_START 0x00126c00
-#define BCHP_RVC_0_REG_END 0x00126c20
-#define BCHP_ILS_REGS_0_REG_START 0x00127000
-#define BCHP_ILS_REGS_0_REG_END 0x001270fc
-#define BCHP_ILS_SCALE_ADDR_0_REG_START 0x00127100
-#define BCHP_ILS_SCALE_ADDR_0_REG_END 0x0012710c
-#define BCHP_ILS_SPSCALE_FILL_0_REG_START 0x00127180
-#define BCHP_ILS_SPSCALE_FILL_0_REG_END 0x00127184
-#define BCHP_ILS_MVSCALE_0_REG_START 0x00127200
-#define BCHP_ILS_MVSCALE_0_REG_END 0x0012738c
-#define BCHP_ILB_REGS_0_REG_START 0x00127400
-#define BCHP_ILB_REGS_0_REG_END 0x00127410
-#define BCHP_BLD_DECODE_MAIN_0_REG_START 0x00128100
-#define BCHP_BLD_DECODE_MAIN_0_REG_END 0x001281fc
-#define BCHP_BLD_DECODE_MCOM_0_REG_START 0x00128300
-#define BCHP_BLD_DECODE_MCOM_0_REG_END 0x0012831c
-#define BCHP_BLD_DECODE_SPRE_0_REG_START 0x00128320
-#define BCHP_BLD_DECODE_SPRE_0_REG_END 0x0012833c
-#define BCHP_BLD_DECODE_DQNT_0_REG_START 0x00128400
-#define BCHP_BLD_DECODE_DQNT_0_REG_END 0x0012845c
-#define BCHP_BLD_DECODE_DQNT_8X8_0_REG_START 0x00128500
-#define BCHP_BLD_DECODE_DQNT_8X8_0_REG_END 0x0012857c
-#define BCHP_BLD_DECODE_XFRM_0_REG_START 0x00128700
-#define BCHP_BLD_DECODE_XFRM_0_REG_END 0x0012871c
-#define BCHP_BLD_DECODE_DBLK_0_REG_START 0x00128720
-#define BCHP_BLD_DECODE_DBLK_0_REG_END 0x0012873c
-#define BCHP_BLD_DECODE_MB_0_REG_START 0x00128740
-#define BCHP_BLD_DECODE_MB_0_REG_END 0x0012875c
-#define BCHP_BLD_DECODE_SINT_0_REG_START 0x00128c00
-#define BCHP_BLD_DECODE_SINT_0_REG_END 0x00128dfc
-#define BCHP_BLD_DECODE_RVC_0_REG_START 0x00128e00
-#define BCHP_BLD_DECODE_RVC_0_REG_END 0x00128efc
-#define BCHP_BLD_BL_CPU_REGS_0_REG_START 0x0012c000
-#define BCHP_BLD_BL_CPU_REGS_0_REG_END 0x0012c108
-#define BCHP_BLD_BL_CPU_DMA_0_REG_START 0x0012c400
-#define BCHP_BLD_BL_CPU_DMA_0_REG_END 0x0012c440
-#define BCHP_BLD_BL_CPU_DEBUG_0_REG_START 0x0012c800
-#define BCHP_BLD_BL_CPU_DEBUG_0_REG_END 0x0012cffc
-#define BCHP_BLD_DECODE_IP_SHIM_0_REG_START 0x0012d000
-#define BCHP_BLD_DECODE_IP_SHIM_0_REG_END 0x0012d090
-#define BCHP_HEVD_IL_CPU_REGS_0_REG_START 0x00130000
-#define BCHP_HEVD_IL_CPU_REGS_0_REG_END 0x00130108
-#define BCHP_HEVD_IL_CPU_DMA_0_REG_START 0x00130400
-#define BCHP_HEVD_IL_CPU_DMA_0_REG_END 0x00130440
-#define BCHP_HEVD_IL_CPU_DEBUG_0_REG_START 0x00130800
-#define BCHP_HEVD_IL_CPU_DEBUG_0_REG_END 0x00130ffc
-#define BCHP_HEVD_IL_SLICE_DMA_0_REG_START 0x00131000
-#define BCHP_HEVD_IL_SLICE_DMA_0_REG_END 0x0013100c
-#define BCHP_HEVD_IL_LDST_0_REG_START 0x00134000
-#define BCHP_HEVD_IL_LDST_0_REG_END 0x00137ffc
-#define BCHP_DECODE_MAIN_2_0_REG_START 0x00140100
-#define BCHP_DECODE_MAIN_2_0_REG_END 0x001401fc
-#define BCHP_DECODE_MCOM_2_0_REG_START 0x00140300
-#define BCHP_DECODE_MCOM_2_0_REG_END 0x0014031c
-#define BCHP_DECODE_SPRE_2_0_REG_START 0x00140320
-#define BCHP_DECODE_SPRE_2_0_REG_END 0x0014033c
-#define BCHP_DECODE_WPRD_2_0_REG_START 0x00140340
-#define BCHP_DECODE_WPRD_2_0_REG_END 0x0014035c
-#define BCHP_DECODE_DQNT_2_0_REG_START 0x00140400
-#define BCHP_DECODE_DQNT_2_0_REG_END 0x0014045c
-#define BCHP_DECODE_DQNT_8X8_2_0_REG_START 0x00140500
-#define BCHP_DECODE_DQNT_8X8_2_0_REG_END 0x0014057c
-#define BCHP_DECODE_VP8_XFRM_2_0_REG_START 0x00140600
-#define BCHP_DECODE_VP8_XFRM_2_0_REG_END 0x0014060c
-#define BCHP_DECODE_VP6_DCP_2_0_REG_START 0x00140620
-#define BCHP_DECODE_VP6_DCP_2_0_REG_END 0x0014062c
-#define BCHP_DECODE_XFRM_2_0_REG_START 0x00140700
-#define BCHP_DECODE_XFRM_2_0_REG_END 0x0014071c
-#define BCHP_DECODE_DBLK_2_0_REG_START 0x00140720
-#define BCHP_DECODE_DBLK_2_0_REG_END 0x0014073c
-#define BCHP_DECODE_MB_2_0_REG_START 0x00140740
-#define BCHP_DECODE_MB_2_0_REG_END 0x0014075c
-#define BCHP_DECODE_SINT_2_0_REG_START 0x00140c00
-#define BCHP_DECODE_SINT_2_0_REG_END 0x00140dfc
-#define BCHP_DECODE_WPTBL_2_0_REG_START 0x00143000
-#define BCHP_DECODE_WPTBL_2_0_REG_END 0x001431fc
-#define BCHP_HEVD_BE_GLOBAL_2_0_REG_START 0x00144000
-#define BCHP_HEVD_BE_GLOBAL_2_0_REG_END 0x00144030
-#define BCHP_HEVD_IXFORM_2_0_REG_START 0x00144100
-#define BCHP_HEVD_IXFORM_2_0_REG_END 0x001441fc
-#define BCHP_HEVD_MCOMP_2_0_REG_START 0x00144200
-#define BCHP_HEVD_MCOMP_2_0_REG_END 0x001442fc
-#define BCHP_HEVD_SPRED_2_0_REG_START 0x00144300
-#define BCHP_HEVD_SPRED_2_0_REG_END 0x001443f0
-#define BCHP_HEVD_FILTER_2_0_REG_START 0x00144400
-#define BCHP_HEVD_FILTER_2_0_REG_END 0x001444fc
-#define BCHP_HEVD_OUTPUT_2_0_REG_START 0x00144500
-#define BCHP_HEVD_OUTPUT_2_0_REG_END 0x001445fc
-#define BCHP_HEVD_MARKER_2_0_REG_START 0x00144f00
-#define BCHP_HEVD_MARKER_2_0_REG_END 0x00144f7c
-#define BCHP_HEVD_FE_CTRL_2_0_REG_START 0x00145000
-#define BCHP_HEVD_FE_CTRL_2_0_REG_END 0x00145048
-#define BCHP_HEVD_STRM_IN_2_0_REG_START 0x00145100
-#define BCHP_HEVD_STRM_IN_2_0_REG_END 0x00145118
-#define BCHP_HEVD_CMDBUS_XMIT_2_0_REG_START 0x00145200
-#define BCHP_HEVD_CMDBUS_XMIT_2_0_REG_END 0x00145230
-#define BCHP_HEVD_VECGEN_2_0_REG_START 0x00145400
-#define BCHP_HEVD_VECGEN_2_0_REG_END 0x0014568c
-#define BCHP_DCD_PIPE_CTL_2_0_REG_START 0x00146000
-#define BCHP_DCD_PIPE_CTL_2_0_REG_END 0x00146404
-#define BCHP_HEVD_PCACHE_2_0_REG_START 0x00146800
-#define BCHP_HEVD_PCACHE_2_0_REG_END 0x00146834
-#define BCHP_HEVD_PFRI_2_0_REG_START 0x00146a00
-#define BCHP_HEVD_PFRI_2_0_REG_END 0x00146b58
-#define BCHP_RVC_2_0_REG_START 0x00146c00
-#define BCHP_RVC_2_0_REG_END 0x00146c20
-#define BCHP_ILS_REGS_2_0_REG_START 0x00147000
-#define BCHP_ILS_REGS_2_0_REG_END 0x001470fc
-#define BCHP_ILS_SCALE_ADDR_2_0_REG_START 0x00147100
-#define BCHP_ILS_SCALE_ADDR_2_0_REG_END 0x0014710c
-#define BCHP_ILS_SPSCALE_FILL_2_0_REG_START 0x00147180
-#define BCHP_ILS_SPSCALE_FILL_2_0_REG_END 0x00147184
-#define BCHP_ILS_MVSCALE_2_0_REG_START 0x00147200
-#define BCHP_ILS_MVSCALE_2_0_REG_END 0x0014738c
-#define BCHP_ILB_REGS_2_0_REG_START 0x00147400
-#define BCHP_ILB_REGS_2_0_REG_END 0x00147410
-#define BCHP_BLD_DECODE_MAIN_2_0_REG_START 0x00148100
-#define BCHP_BLD_DECODE_MAIN_2_0_REG_END 0x001481fc
-#define BCHP_BLD_DECODE_MCOM_2_0_REG_START 0x00148300
-#define BCHP_BLD_DECODE_MCOM_2_0_REG_END 0x0014831c
-#define BCHP_BLD_DECODE_SPRE_2_0_REG_START 0x00148320
-#define BCHP_BLD_DECODE_SPRE_2_0_REG_END 0x0014833c
-#define BCHP_BLD_DECODE_DQNT_2_0_REG_START 0x00148400
-#define BCHP_BLD_DECODE_DQNT_2_0_REG_END 0x0014845c
-#define BCHP_BLD_DECODE_DQNT_8X8_2_0_REG_START 0x00148500
-#define BCHP_BLD_DECODE_DQNT_8X8_2_0_REG_END 0x0014857c
-#define BCHP_BLD_DECODE_XFRM_2_0_REG_START 0x00148700
-#define BCHP_BLD_DECODE_XFRM_2_0_REG_END 0x0014871c
-#define BCHP_BLD_DECODE_DBLK_2_0_REG_START 0x00148720
-#define BCHP_BLD_DECODE_DBLK_2_0_REG_END 0x0014873c
-#define BCHP_BLD_DECODE_MB_2_0_REG_START 0x00148740
-#define BCHP_BLD_DECODE_MB_2_0_REG_END 0x0014875c
-#define BCHP_BLD_DECODE_SINT_2_0_REG_START 0x00148c00
-#define BCHP_BLD_DECODE_SINT_2_0_REG_END 0x00148dfc
-#define BCHP_BLD_DECODE_RVC_2_0_REG_START 0x00148e00
-#define BCHP_BLD_DECODE_RVC_2_0_REG_END 0x00148efc
-#define BCHP_BLD_BL_CPU_REGS_2_0_REG_START 0x0014c000
-#define BCHP_BLD_BL_CPU_REGS_2_0_REG_END 0x0014c108
-#define BCHP_BLD_BL_CPU_DMA_2_0_REG_START 0x0014c400
-#define BCHP_BLD_BL_CPU_DMA_2_0_REG_END 0x0014c440
-#define BCHP_BLD_BL_CPU_DEBUG_2_0_REG_START 0x0014c800
-#define BCHP_BLD_BL_CPU_DEBUG_2_0_REG_END 0x0014cffc
-#define BCHP_BLD_DECODE_IP_SHIM_2_0_REG_START 0x0014d000
-#define BCHP_BLD_DECODE_IP_SHIM_2_0_REG_END 0x0014d090
-#define BCHP_HEVD_IL_CPU_REGS_2_0_REG_START 0x00150000
-#define BCHP_HEVD_IL_CPU_REGS_2_0_REG_END 0x00150108
-#define BCHP_HEVD_IL_CPU_DMA_2_0_REG_START 0x00150400
-#define BCHP_HEVD_IL_CPU_DMA_2_0_REG_END 0x00150440
-#define BCHP_HEVD_IL_CPU_DEBUG_2_0_REG_START 0x00150800
-#define BCHP_HEVD_IL_CPU_DEBUG_2_0_REG_END 0x00150ffc
-#define BCHP_HEVD_IL_SLICE_DMA_2_0_REG_START 0x00151000
-#define BCHP_HEVD_IL_SLICE_DMA_2_0_REG_END 0x0015100c
-#define BCHP_HEVD_IL_LDST_2_0_REG_START 0x00154000
-#define BCHP_HEVD_IL_LDST_2_0_REG_END 0x00157ffc
-#define BCHP_HVD_INTR2_0_REG_START 0x00180000
-#define BCHP_HVD_INTR2_0_REG_END 0x0018002c
-#define BCHP_HVD_RGR_0_REG_START 0x00180400
-#define BCHP_HVD_RGR_0_REG_END 0x00180410
-#define BCHP_VICH_0_REG_START 0x001a0000
-#define BCHP_VICH_0_REG_END 0x001a008b
-#define BCHP_SCPU_LOCALRAM_REG_START 0x00300000
-#define BCHP_SCPU_LOCALRAM_REG_END 0x0030fffc
-#define BCHP_SCPU_GLOBALRAM_REG_START 0x00310000
-#define BCHP_SCPU_GLOBALRAM_REG_END 0x003103fc
-#define BCHP_SCPU_MISB_BRIDGE_REG_START 0x00310400
-#define BCHP_SCPU_MISB_BRIDGE_REG_END 0x00310450
-#define BCHP_SCPU_RGR_BRIDGE_REG_START 0x00310460
-#define BCHP_SCPU_RGR_BRIDGE_REG_END 0x00310470
-#define BCHP_SCPU_INTR1_REG_START 0x00310480
-#define BCHP_SCPU_INTR1_REG_END 0x00310498
-#define BCHP_INTERNAL_INTR2_REG_START 0x003104c0
-#define BCHP_INTERNAL_INTR2_REG_END 0x003104ec
-#define BCHP_BSP_IPI_INTR2_REG_START 0x00310500
-#define BCHP_BSP_IPI_INTR2_REG_END 0x0031052c
-#define BCHP_SCPU_HW_INTR2_REG_START 0x00310540
-#define BCHP_SCPU_HW_INTR2_REG_END 0x0031056c
-#define BCHP_CPU_IPI_INTR2_REG_START 0x00311000
-#define BCHP_CPU_IPI_INTR2_REG_END 0x0031102c
-#define BCHP_SCPU_HOST_INTR2_REG_START 0x00311040
-#define BCHP_SCPU_HOST_INTR2_REG_END 0x0031106c
-#define BCHP_SCPU_TOP_CTRL_REG_START 0x00312000
-#define BCHP_SCPU_TOP_CTRL_REG_END 0x00312008
-#define BCHP_SCPU_HDMI_CTRL_REG_START 0x00312080
-#define BCHP_SCPU_HDMI_CTRL_REG_END 0x00312084
-#define BCHP_SCPU_SEC_TIME_REG_START 0x00312100
-#define BCHP_SCPU_SEC_TIME_REG_END 0x00312114
-#define BCHP_SAGE_UART_REG_START 0x00312200
-#define BCHP_SAGE_UART_REG_END 0x0031221c
-#define BCHP_SCPU_PM_REG_START 0x00312980
-#define BCHP_SCPU_PM_REG_END 0x00312988
-#define BCHP_SCPU_TIMER_REG_START 0x00312e80
-#define BCHP_SCPU_TIMER_REG_END 0x00312ebc
-#define BCHP_BSP_CMDBUF_REG_START 0x0032c800
-#define BCHP_BSP_CMDBUF_REG_END 0x0032cffc
-#define BCHP_BSP_GLB_CONTROL_REG_START 0x0032d000
-#define BCHP_BSP_GLB_CONTROL_REG_END 0x0032d0b0
-#define BCHP_BSP_PKL_REG_START 0x0032d300
-#define BCHP_BSP_PKL_REG_END 0x0032d37c
-#define BCHP_BSP_CONTROL_INTR2_REG_START 0x0032d800
-#define BCHP_BSP_CONTROL_INTR2_REG_END 0x0032d82c
-#define BCHP_BSP_VISTA_GENACC_REG_START 0x0032d900
-#define BCHP_BSP_VISTA_GENACC_REG_END 0x0032d9fc
-#define BCHP_BSP_OTP_SCRATCH_REG_START 0x0032e000
-#define BCHP_BSP_OTP_SCRATCH_REG_END 0x0032fffc
-#define BCHP_XPT_SECURITY_REG_START 0x00360000
-#define BCHP_XPT_SECURITY_REG_END 0x0037fffc
-#define BCHP_SECTOP_GRB_REG_START 0x00380000
-#define BCHP_SECTOP_GRB_REG_END 0x0038000c
-#define BCHP_XPT_SECURITY_NS_INTR2_0_REG_START 0x00380080
-#define BCHP_XPT_SECURITY_NS_INTR2_0_REG_END 0x003800ac
-#define BCHP_XPT_SECURITY_NS_INTR2_1_REG_START 0x00380100
-#define BCHP_XPT_SECURITY_NS_INTR2_1_REG_END 0x0038012c
-#define BCHP_XPT_SECURITY_NS_INTR2_2_REG_START 0x00380180
-#define BCHP_XPT_SECURITY_NS_INTR2_2_REG_END 0x003801ac
-#define BCHP_XPT_SECURITY_NS_REG_START 0x00380200
-#define BCHP_XPT_SECURITY_NS_REG_END 0x003802c8
-#define BCHP_SUN_GISB_ARB_REG_START 0x00400000
-#define BCHP_SUN_GISB_ARB_REG_END 0x004007fc
-#define BCHP_SUN_GR_REG_START 0x00401000
-#define BCHP_SUN_GR_REG_END 0x0040100c
-#define BCHP_SSP_RG_REG_START 0x00401200
-#define BCHP_SSP_RG_REG_END 0x0040120c
-#define BCHP_SUN_RG_REG_START 0x00401400
-#define BCHP_SUN_RG_REG_END 0x0040140c
-#define BCHP_RF4CE_GR_REG_START 0x00401600
-#define BCHP_RF4CE_GR_REG_END 0x0040160c
-#define BCHP_TPCAP_REG_START 0x00401800
-#define BCHP_TPCAP_REG_END 0x0040189c
-#define BCHP_SUN_L2_REG_START 0x00403000
-#define BCHP_SUN_L2_REG_END 0x00403044
-#define BCHP_SUN_TOP_CTRL_REG_START 0x00404000
-#define BCHP_SUN_TOP_CTRL_REG_END 0x0040452c
-#define BCHP_BBSI_RG_REG_START 0x00405c00
-#define BCHP_BBSI_RG_REG_END 0x00405c0c
-#define BCHP_PWM_REG_START 0x00408000
-#define BCHP_PWM_REG_END 0x00408024
-#define BCHP_PWMB_REG_START 0x00409000
-#define BCHP_PWMB_REG_END 0x00409024
-#define BCHP_IRB_REG_START 0x0040a000
-#define BCHP_IRB_REG_END 0x0040a138
-#define BCHP_BSCA_REG_START 0x0040a180
-#define BCHP_BSCA_REG_END 0x0040a1d4
-#define BCHP_BSCB_REG_START 0x0040a200
-#define BCHP_BSCB_REG_END 0x0040a254
-#define BCHP_BSCE_REG_START 0x0040a280
-#define BCHP_BSCE_REG_END 0x0040a2d4
-#define BCHP_BSCF_REG_START 0x0040a300
-#define BCHP_BSCF_REG_END 0x0040a354
-#define BCHP_BSCG_REG_START 0x0040a380
-#define BCHP_BSCG_REG_END 0x0040a3d4
-#define BCHP_GIO_REG_START 0x0040a400
-#define BCHP_GIO_REG_END 0x0040a4bc
-#define BCHP_PM_REG_START 0x0040a500
-#define BCHP_PM_REG_END 0x0040a508
-#define BCHP_TIMER_REG_START 0x0040a540
-#define BCHP_TIMER_REG_END 0x0040a57c
-#define BCHP_IRQ0_REG_START 0x0040a580
-#define BCHP_IRQ0_REG_END 0x0040a584
-#define BCHP_IRQ1_REG_START 0x0040a5c0
-#define BCHP_IRQ1_REG_END 0x0040a5c4
-#define BCHP_CTK_REG_START 0x0040a800
-#define BCHP_CTK_REG_END 0x0040a978
-#define BCHP_TMON_REG_START 0x0040a980
-#define BCHP_TMON_REG_END 0x0040a9d4
-#define BCHP_UPG_AUX_INTR2_REG_START 0x0040aa00
-#define BCHP_UPG_AUX_INTR2_REG_END 0x0040aa2c
-#define BCHP_MCIF_REG_START 0x0040aa40
-#define BCHP_MCIF_REG_END 0x0040aa68
-#define BCHP_MCIF1_REG_START 0x0040aa80
-#define BCHP_MCIF1_REG_END 0x0040aaa8
-#define BCHP_MCIF_INTR2_REG_START 0x0040ab00
-#define BCHP_MCIF_INTR2_REG_END 0x0040ab44
-#define BCHP_SCA_REG_START 0x0040ac00
-#define BCHP_SCA_REG_END 0x0040acfc
-#define BCHP_SCB_REG_START 0x0040ad00
-#define BCHP_SCB_REG_END 0x0040adfc
-#define BCHP_SCIRQ0_REG_START 0x0040ae00
-#define BCHP_SCIRQ0_REG_END 0x0040ae04
-#define BCHP_SCIRQ1_REG_START 0x0040ae40
-#define BCHP_SCIRQ1_REG_END 0x0040ae44
-#define BCHP_SCIRQ_SCPU_REG_START 0x0040ae80
-#define BCHP_SCIRQ_SCPU_REG_END 0x0040ae84
-#define BCHP_UARTA_REG_START 0x0040b000
-#define BCHP_UARTA_REG_END 0x0040b01c
-#define BCHP_UARTB_REG_START 0x0040b040
-#define BCHP_UARTB_REG_END 0x0040b05c
-#define BCHP_UARTC_REG_START 0x0040b080
-#define BCHP_UARTC_REG_END 0x0040b09c
-#define BCHP_UPG_UART_DMA_REG_START 0x0040b0c0
-#define BCHP_UPG_UART_DMA_REG_END 0x0040b0f0
-#define BCHP_AON_CTRL_REG_START 0x00410000
-#define BCHP_AON_CTRL_REG_END 0x004105fc
-#define BCHP_AON_L2_REG_START 0x00410600
-#define BCHP_AON_L2_REG_END 0x0041062c
-#define BCHP_AON_PM_L2_REG_START 0x00410640
-#define BCHP_AON_PM_L2_REG_END 0x0041066c
-#define BCHP_AON_PIN_CTRL_REG_START 0x00410700
-#define BCHP_AON_PIN_CTRL_REG_END 0x00410718
-#define BCHP_AON_HDMI_TX_REG_START 0x00410800
-#define BCHP_AON_HDMI_TX_REG_END 0x004108ac
-#define BCHP_CNTControlBase_REG_START 0x00412000
-#define BCHP_CNTControlBase_REG_END 0x00412ffc
-#define BCHP_CNTReadBase_REG_START 0x00414000
-#define BCHP_CNTReadBase_REG_END 0x00414ffc
-#define BCHP_MSPI_REG_START 0x00416000
-#define BCHP_MSPI_REG_END 0x0041617c
-#define BCHP_LDK_REG_START 0x00417000
-#define BCHP_LDK_REG_END 0x0041703c
-#define BCHP_PM_AON_REG_START 0x00417040
-#define BCHP_PM_AON_REG_END 0x00417048
-#define BCHP_ICAP_REG_START 0x00417080
-#define BCHP_ICAP_REG_END 0x004170bc
-#define BCHP_KBD1_REG_START 0x004170c0
-#define BCHP_KBD1_REG_END 0x004170fc
-#define BCHP_KBD2_REG_START 0x00417100
-#define BCHP_KBD2_REG_END 0x0041713c
-#define BCHP_KBD3_REG_START 0x00417140
-#define BCHP_KBD3_REG_END 0x0041717c
-#define BCHP_BSCC_REG_START 0x00417180
-#define BCHP_BSCC_REG_END 0x004171d4
-#define BCHP_BSCD_REG_START 0x00417200
-#define BCHP_BSCD_REG_END 0x00417254
-#define BCHP_IRQ0_AON_REG_START 0x00417280
-#define BCHP_IRQ0_AON_REG_END 0x00417284
-#define BCHP_IRQ1_AON_REG_START 0x004172c0
-#define BCHP_IRQ1_AON_REG_END 0x004172c4
-#define BCHP_GIO_AON_REG_START 0x00417300
-#define BCHP_GIO_AON_REG_END 0x0041733c
-#define BCHP_UPG_AUX_AON_INTR2_REG_START 0x00417400
-#define BCHP_UPG_AUX_AON_INTR2_REG_END 0x0041742c
-#define BCHP_WKTMR_REG_START 0x00417480
-#define BCHP_WKTMR_REG_END 0x00417490
-#define BCHP_BICAP_REG_START 0x004174c0
-#define BCHP_BICAP_REG_END 0x004174f8
-#define BCHP_SYS_GISB_ARB_SEC_REG_START 0x0041e000
-#define BCHP_SYS_GISB_ARB_SEC_REG_END 0x0041e7fc
-#define BCHP_SYS_TOP_CTRL_SEC_REG_START 0x0041e800
-#define BCHP_SYS_TOP_CTRL_SEC_REG_END 0x0041e808
-#define BCHP_AON_CTRL_SECURE_REG_START 0x0041e900
-#define BCHP_AON_CTRL_SECURE_REG_END 0x0041e97c
-#define BCHP_BOOTSRAM_SECURE_REG_START 0x00420000
-#define BCHP_BOOTSRAM_SECURE_REG_END 0x0042fffc
-#define BCHP_ITCH0_REG_START 0x00430000
-#define BCHP_ITCH0_REG_END 0x00430000
-#define BCHP_HIF_SECURE_CTRL_REG_START 0x00430400
-#define BCHP_HIF_SECURE_CTRL_REG_END 0x00430400
-#define BCHP_HIF_SECURE_BSPI_REG_START 0x00430500
-#define BCHP_HIF_SECURE_BSPI_REG_END 0x00430500
-#define BCHP_HIF_SECURE_LR_SPI_REG_START 0x00430600
-#define BCHP_HIF_SECURE_LR_SPI_REG_END 0x00430600
-#define BCHP_NAND_SECURE_REG_START 0x00430800
-#define BCHP_NAND_SECURE_REG_END 0x00430800
-#define BCHP_HIF_SECURE_INDIRECT_MSPI_PIPE_REG_START 0x00430c00
-#define BCHP_HIF_SECURE_INDIRECT_MSPI_PIPE_REG_END 0x00430c00
-#define BCHP_HIF_CPUBIUARCH_SECURE_REG_START 0x00430e00
-#define BCHP_HIF_CPUBIUARCH_SECURE_REG_END 0x00430ffc
-#define BCHP_HIF_CONTINUATION_SECURE_REG_START 0x00431000
-#define BCHP_HIF_CONTINUATION_SECURE_REG_END 0x00431004
-#define BCHP_ITCH1_REG_START 0x00431200
-#define BCHP_ITCH1_REG_END 0x00431200
-#define BCHP_SDIO_0_HOST_REG_START 0x00440000
-#define BCHP_SDIO_0_HOST_REG_END 0x004400fc
-#define BCHP_SDIO_0_CFG_REG_START 0x00440100
-#define BCHP_SDIO_0_CFG_REG_END 0x004401fc
-#define BCHP_SDIO_1_HOST_REG_START 0x00440200
-#define BCHP_SDIO_1_HOST_REG_END 0x004402fc
-#define BCHP_SDIO_1_CFG_REG_START 0x00440300
-#define BCHP_SDIO_1_CFG_REG_END 0x004403fc
-#define BCHP_SDIO_1_BOOT_REG_START 0x00440400
-#define BCHP_SDIO_1_BOOT_REG_END 0x0044043c
-#define BCHP_EBI_REG_START 0x00440800
-#define BCHP_EBI_REG_END 0x00440bfc
-#define BCHP_HIF_INTR2_REG_START 0x00441000
-#define BCHP_HIF_INTR2_REG_END 0x0044102c
-#define BCHP_HIF_CPU_INTR1_REG_START 0x00441500
-#define BCHP_HIF_CPU_INTR1_REG_END 0x0044153c
-#define BCHP_PCI_PCIE_INTR1_REG_START 0x00441600
-#define BCHP_PCI_PCIE_INTR1_REG_END 0x0044163c
-#define BCHP_HIF_RGR2_REG_START 0x00441700
-#define BCHP_HIF_RGR2_REG_END 0x00441710
-#define BCHP_HIF_SPI_INTR2_REG_START 0x00441a00
-#define BCHP_HIF_SPI_INTR2_REG_END 0x00441a2c
-#define BCHP_HIF_TOP_CTRL_REG_START 0x00442000
-#define BCHP_HIF_TOP_CTRL_REG_END 0x0044203c
-#define BCHP_WEBHIF_L1_MASK_REG_START 0x00442100
-#define BCHP_WEBHIF_L1_MASK_REG_END 0x0044210c
-#define BCHP_HIF_CPUBIUARCH_REG_START 0x00442200
-#define BCHP_HIF_CPUBIUARCH_REG_END 0x004423fc
-#define BCHP_HIF_CPUBIUCTRL_REG_START 0x00442400
-#define BCHP_HIF_CPUBIUCTRL_REG_END 0x004427fc
-#define BCHP_NAND_REG_START 0x00442800
-#define BCHP_NAND_REG_END 0x00442dfc
-#define BCHP_FLASH_DMA_REG_START 0x00443000
-#define BCHP_FLASH_DMA_REG_END 0x00443028
-#define BCHP_BSPI_REG_START 0x00443200
-#define BCHP_BSPI_REG_END 0x0044324c
-#define BCHP_BSPI_RAF_REG_START 0x00443300
-#define BCHP_BSPI_RAF_REG_END 0x00443320
-#define BCHP_HIF_MSPI_REG_START 0x00443400
-#define BCHP_HIF_MSPI_REG_END 0x00443584
-#define BCHP_HIF_CONTINUATION_SECURE_TM_REG_START 0x00443600
-#define BCHP_HIF_CONTINUATION_SECURE_TM_REG_END 0x00443604
-#define BCHP_IPI0_INTR2_REG_START 0x00444000
-#define BCHP_IPI0_INTR2_REG_END 0x0044402c
-#define BCHP_IPI1_INTR2_REG_START 0x00444100
-#define BCHP_IPI1_INTR2_REG_END 0x0044412c
-#define BCHP_BOOTSRAM_TM_REG_START 0x00450000
-#define BCHP_BOOTSRAM_TM_REG_END 0x0045fffc
-#define BCHP_HIF_CONTINUATION_REG_START 0x00462000
-#define BCHP_HIF_CONTINUATION_REG_END 0x004620fc
-#define BCHP_WEBHIF_CONTINUATION_REG_START 0x00462800
-#define BCHP_WEBHIF_CONTINUATION_REG_END 0x00462804
-#define BCHP_WEBHIF_RGR1_REG_START 0x00464000
-#define BCHP_WEBHIF_RGR1_REG_END 0x00464010
-#define BCHP_WEBHIF_INTR2_REG_START 0x00464100
-#define BCHP_WEBHIF_INTR2_REG_END 0x0046412c
-#define BCHP_WEBHIF_CPU_INTR1_REG_START 0x00464600
-#define BCHP_WEBHIF_CPU_INTR1_REG_END 0x0046463c
-#define BCHP_WEBHIF_SCRATCH_REG_START 0x00464800
-#define BCHP_WEBHIF_SCRATCH_REG_END 0x0046481c
-#define BCHP_WEBHIF_TIMER_REG_START 0x00464900
-#define BCHP_WEBHIF_TIMER_REG_END 0x0046493c
-#define BCHP_WEBHIF_TOP_CTRL_REG_START 0x00464a00
-#define BCHP_WEBHIF_TOP_CTRL_REG_END 0x00464a00
-#define BCHP_WEBHIF_IPI0_INTR2_REG_START 0x00465000
-#define BCHP_WEBHIF_IPI0_INTR2_REG_END 0x0046502c
-#define BCHP_WEBHIF_STB_IPI0_INTR2_REG_START 0x00466000
-#define BCHP_WEBHIF_STB_IPI0_INTR2_REG_END 0x0046602c
-#define BCHP_SATA_GRB_REG_START 0x00468000
-#define BCHP_SATA_GRB_REG_END 0x0046800c
-#define BCHP_SATA_TOP_CTRL_REG_START 0x00468040
-#define BCHP_SATA_TOP_CTRL_REG_END 0x00468060
-#define BCHP_SATA3_INTR2_REG_START 0x00468080
-#define BCHP_SATA3_INTR2_REG_END 0x004680ac
-#define BCHP_PORT0_SATA3_PCB_REG_START 0x00468100
-#define BCHP_PORT0_SATA3_PCB_REG_END 0x00468ffc
-#define BCHP_PORT1_SATA3_PCB_REG_START 0x00469100
-#define BCHP_PORT1_SATA3_PCB_REG_END 0x00469ffc
-#define BCHP_SATA_AHCI_GHC_REG_START 0x0046a000
-#define BCHP_SATA_AHCI_GHC_REG_END 0x0046a028
-#define BCHP_SATA_GLOBAL_RESERVED_REG_START 0x0046a02c
-#define BCHP_SATA_GLOBAL_RESERVED_REG_END 0x0046a09c
-#define BCHP_SATA_PORT0_AHCI_S1_REG_START 0x0046a100
-#define BCHP_SATA_PORT0_AHCI_S1_REG_END 0x0046a11c
-#define BCHP_SATA_PORT0_AHCI_S2_REG_START 0x0046a120
-#define BCHP_SATA_PORT0_AHCI_S2_REG_END 0x0046a134
-#define BCHP_SATA_PORT0_AHCI_S3_REG_START 0x0046a138
-#define BCHP_SATA_PORT0_AHCI_S3_REG_END 0x0046a17c
-#define BCHP_SATA_PORT1_AHCI_S1_REG_START 0x0046a180
-#define BCHP_SATA_PORT1_AHCI_S1_REG_END 0x0046a19c
-#define BCHP_SATA_PORT1_AHCI_S2_REG_START 0x0046a1a0
-#define BCHP_SATA_PORT1_AHCI_S2_REG_END 0x0046a1b4
-#define BCHP_SATA_PORT1_AHCI_S3_REG_START 0x0046a1b8
-#define BCHP_SATA_PORT1_AHCI_S3_REG_END 0x0046a1fc
-#define BCHP_SATA_AHCI_PCICFG_REG_START 0x0046a600
-#define BCHP_SATA_AHCI_PCICFG_REG_END 0x0046a664
-#define BCHP_SATA_PORT0_CTRL_REG_START 0x0046a700
-#define BCHP_SATA_PORT0_CTRL_REG_END 0x0046a730
-#define BCHP_SATA_PORT0_CJPAT_REG_START 0x0046a740
-#define BCHP_SATA_PORT0_CJPAT_REG_END 0x0046a764
-#define BCHP_SATA_PORT1_CTRL_REG_START 0x0046a780
-#define BCHP_SATA_PORT1_CTRL_REG_END 0x0046a7b0
-#define BCHP_SATA_PORT1_CJPAT_REG_START 0x0046a7c0
-#define BCHP_SATA_PORT1_CJPAT_REG_END 0x0046a7e4
-#define BCHP_SATA_LEG_PCICFG_REG_START 0x0046a800
-#define BCHP_SATA_LEG_PCICFG_REG_END 0x0046a880
-#define BCHP_SATA_PORT0_LEG_S1_REG_START 0x0046a900
-#define BCHP_SATA_PORT0_LEG_S1_REG_END 0x0046a934
-#define BCHP_SATA_PORT0_LEG_S2_REG_START 0x0046a940
-#define BCHP_SATA_PORT0_LEG_S2_REG_END 0x0046a954
-#define BCHP_SATA_PORT0_LEG_S3_REG_START 0x0046a958
-#define BCHP_SATA_PORT0_LEG_S3_REG_END 0x0046a998
-#define BCHP_SATA_PORT1_LEG_S1_REG_START 0x0046aa00
-#define BCHP_SATA_PORT1_LEG_S1_REG_END 0x0046aa34
-#define BCHP_SATA_PORT1_LEG_S2_REG_START 0x0046aa40
-#define BCHP_SATA_PORT1_LEG_S2_REG_END 0x0046aa54
-#define BCHP_SATA_PORT1_LEG_S3_REG_START 0x0046aa58
-#define BCHP_SATA_PORT1_LEG_S3_REG_END 0x0046aa98
-#define BCHP_PCIE_0_RC_CFG_TYPE1_REG_START 0x00470000
-#define BCHP_PCIE_0_RC_CFG_TYPE1_REG_END 0x0047003c
-#define BCHP_PCIE_0_RC_CFG_PM_REG_START 0x00470048
-#define BCHP_PCIE_0_RC_CFG_PM_REG_END 0x0047004c
-#define BCHP_PCIE_0_RC_CFG_PCIE_REG_START 0x004700ac
-#define BCHP_PCIE_0_RC_CFG_PCIE_REG_END 0x004700e4
-#define BCHP_PCIE_0_RC_CFG_AER_REG_START 0x00470100
-#define BCHP_PCIE_0_RC_CFG_AER_REG_END 0x00470134
-#define BCHP_PCIE_0_RC_CFG_VC_REG_START 0x00470160
-#define BCHP_PCIE_0_RC_CFG_VC_REG_END 0x00470178
-#define BCHP_PCIE_0_RC_CFG_VENDOR_REG_START 0x00470180
-#define BCHP_PCIE_0_RC_CFG_VENDOR_REG_END 0x004701a4
-#define BCHP_PCIE_0_RC_CFG_PRIV0_REG_START 0x00470404
-#define BCHP_PCIE_0_RC_CFG_PRIV0_REG_END 0x00470418
-#define BCHP_PCIE_0_RC_CFG_PRIV1_REG_START 0x00470428
-#define BCHP_PCIE_0_RC_CFG_PRIV1_REG_END 0x00470630
-#define BCHP_PCIE_0_RC_TL_REG_START 0x00470800
-#define BCHP_PCIE_0_RC_TL_REG_END 0x00470998
-#define BCHP_PCIE_0_RC_DL_REG_START 0x00471000
-#define BCHP_PCIE_0_RC_DL_REG_END 0x00471424
-#define BCHP_PCIE_0_RC_PL_REG_START 0x00471800
-#define BCHP_PCIE_0_RC_PL_REG_END 0x00471e1c
-#define BCHP_PCIE_0_EP_CFG_TYPE0_REG_START 0x00472000
-#define BCHP_PCIE_0_EP_CFG_TYPE0_REG_END 0x0047203c
-#define BCHP_PCIE_0_EP_CFG_PM_REG_START 0x00472048
-#define BCHP_PCIE_0_EP_CFG_PM_REG_END 0x0047204c
-#define BCHP_PCIE_0_EP_CFG_VPD_REG_START 0x00472050
-#define BCHP_PCIE_0_EP_CFG_VPD_REG_END 0x00472054
-#define BCHP_PCIE_0_EP_CFG_MSI_REG_START 0x00472058
-#define BCHP_PCIE_0_EP_CFG_MSI_REG_END 0x00472064
-#define BCHP_PCIE_0_EP_CFG_MSIX_REG_START 0x004720a0
-#define BCHP_PCIE_0_EP_CFG_MSIX_REG_END 0x004720a8
-#define BCHP_PCIE_0_EP_CFG_PCIE_REG_START 0x004720ac
-#define BCHP_PCIE_0_EP_CFG_PCIE_REG_END 0x004720e4
-#define BCHP_PCIE_0_EP_CFG_AER_REG_START 0x00472100
-#define BCHP_PCIE_0_EP_CFG_AER_REG_END 0x00472134
-#define BCHP_PCIE_0_EP_CFG_DEV_REG_START 0x0047213c
-#define BCHP_PCIE_0_EP_CFG_DEV_REG_END 0x00472144
-#define BCHP_PCIE_0_EP_CFG_PB_REG_START 0x00472150
-#define BCHP_PCIE_0_EP_CFG_PB_REG_END 0x0047215c
-#define BCHP_PCIE_0_EP_CFG_VC_REG_START 0x00472160
-#define BCHP_PCIE_0_EP_CFG_VC_REG_END 0x00472178
-#define BCHP_PCIE_0_EP_CFG_VENDOR_REG_START 0x00472180
-#define BCHP_PCIE_0_EP_CFG_VENDOR_REG_END 0x004721a4
-#define BCHP_PCIE_0_EP_CFG_PRIV0_REG_START 0x00472404
-#define BCHP_PCIE_0_EP_CFG_PRIV0_REG_END 0x00472418
-#define BCHP_PCIE_0_EP_CFG_PRIV1_REG_START 0x00472428
-#define BCHP_PCIE_0_EP_CFG_PRIV1_REG_END 0x00472630
-#define BCHP_PCIE_0_EP_TL_REG_START 0x00472800
-#define BCHP_PCIE_0_EP_TL_REG_END 0x00472998
-#define BCHP_PCIE_0_EP_DL_REG_START 0x00473000
-#define BCHP_PCIE_0_EP_DL_REG_END 0x00473424
-#define BCHP_PCIE_0_EP_PL_REG_START 0x00473800
-#define BCHP_PCIE_0_EP_PL_REG_END 0x00473e1c
-#define BCHP_PCIE_0_MISC_REG_START 0x00474000
-#define BCHP_PCIE_0_MISC_REG_END 0x004740c8
-#define BCHP_PCIE_0_MISC_PERST_REG_START 0x00474100
-#define BCHP_PCIE_0_MISC_PERST_REG_END 0x00474104
-#define BCHP_PCIE_0_MISC_HARD_REG_START 0x00474200
-#define BCHP_PCIE_0_MISC_HARD_REG_END 0x00474204
-#define BCHP_PCIE_0_INTR2_REG_START 0x00474300
-#define BCHP_PCIE_0_INTR2_REG_END 0x0047432c
-#define BCHP_PCIE_0_DMA_REG_START 0x00474400
-#define BCHP_PCIE_0_DMA_REG_END 0x0047446c
-#define BCHP_PCIE_0_EXT_CFG_REG_START 0x00478000
-#define BCHP_PCIE_0_EXT_CFG_REG_END 0x00479008
-#define BCHP_PCIE_0_RGR1_REG_START 0x00479200
-#define BCHP_PCIE_0_RGR1_REG_END 0x00479210
-#define BCHP_PCIE_0_RG_REG_START 0x00479300
-#define BCHP_PCIE_0_RG_REG_END 0x0047930c
-#define BCHP_USB_CAPS_REG_START 0x00480000
-#define BCHP_USB_CAPS_REG_END 0x0048002c
-#define BCHP_USB_GR_BRIDGE_REG_START 0x00480100
-#define BCHP_USB_GR_BRIDGE_REG_END 0x0048010c
-#define BCHP_USB_INTR2_REG_START 0x00480180
-#define BCHP_USB_INTR2_REG_END 0x004801ac
-#define BCHP_USB_CTRL_REG_START 0x00480200
-#define BCHP_USB_CTRL_REG_END 0x004802fc
-#define BCHP_USB_EHCI_REG_START 0x00480300
-#define BCHP_USB_EHCI_REG_END 0x004803a4
-#define BCHP_USB_OHCI_REG_START 0x00480400
-#define BCHP_USB_OHCI_REG_END 0x00480454
-#define BCHP_USB_EHCI1_REG_START 0x00480500
-#define BCHP_USB_EHCI1_REG_END 0x004805a4
-#define BCHP_USB_OHCI1_REG_START 0x00480600
-#define BCHP_USB_OHCI1_REG_END 0x00480654
-#define BCHP_USB_XHCI_REG_START 0x00481000
-#define BCHP_USB_XHCI_REG_END 0x004818c8
-#define BCHP_USB_XHCI_EC_REG_START 0x00481940
-#define BCHP_USB_XHCI_EC_REG_END 0x00481ffc
-#define BCHP_USB1_CAPS_REG_START 0x00490000
-#define BCHP_USB1_CAPS_REG_END 0x0049002c
-#define BCHP_USB1_GR_BRIDGE_REG_START 0x00490100
-#define BCHP_USB1_GR_BRIDGE_REG_END 0x0049010c
-#define BCHP_USB1_INTR2_REG_START 0x00490180
-#define BCHP_USB1_INTR2_REG_END 0x004901ac
-#define BCHP_USB1_CTRL_REG_START 0x00490200
-#define BCHP_USB1_CTRL_REG_END 0x004902fc
-#define BCHP_USB1_EHCI_REG_START 0x00490300
-#define BCHP_USB1_EHCI_REG_END 0x004903a4
-#define BCHP_USB1_OHCI_REG_START 0x00490400
-#define BCHP_USB1_OHCI_REG_END 0x00490454
-#define BCHP_USB1_EHCI1_REG_START 0x00490500
-#define BCHP_USB1_EHCI1_REG_END 0x004905a4
-#define BCHP_USB1_OHCI1_REG_START 0x00490600
-#define BCHP_USB1_OHCI1_REG_END 0x00490654
-#define BCHP_PCIE_1_RC_CFG_TYPE1_REG_START 0x004a0000
-#define BCHP_PCIE_1_RC_CFG_TYPE1_REG_END 0x004a003c
-#define BCHP_PCIE_1_RC_CFG_PM_REG_START 0x004a0048
-#define BCHP_PCIE_1_RC_CFG_PM_REG_END 0x004a004c
-#define BCHP_PCIE_1_RC_CFG_PCIE_REG_START 0x004a00ac
-#define BCHP_PCIE_1_RC_CFG_PCIE_REG_END 0x004a00e4
-#define BCHP_PCIE_1_RC_CFG_AER_REG_START 0x004a0100
-#define BCHP_PCIE_1_RC_CFG_AER_REG_END 0x004a0134
-#define BCHP_PCIE_1_RC_CFG_VC_REG_START 0x004a0160
-#define BCHP_PCIE_1_RC_CFG_VC_REG_END 0x004a0178
-#define BCHP_PCIE_1_RC_CFG_VENDOR_REG_START 0x004a0180
-#define BCHP_PCIE_1_RC_CFG_VENDOR_REG_END 0x004a01a4
-#define BCHP_PCIE_1_RC_CFG_PRIV0_REG_START 0x004a0404
-#define BCHP_PCIE_1_RC_CFG_PRIV0_REG_END 0x004a0418
-#define BCHP_PCIE_1_RC_CFG_PRIV1_REG_START 0x004a0428
-#define BCHP_PCIE_1_RC_CFG_PRIV1_REG_END 0x004a0630
-#define BCHP_PCIE_1_RC_TL_REG_START 0x004a0800
-#define BCHP_PCIE_1_RC_TL_REG_END 0x004a0998
-#define BCHP_PCIE_1_RC_DL_REG_START 0x004a1000
-#define BCHP_PCIE_1_RC_DL_REG_END 0x004a1424
-#define BCHP_PCIE_1_RC_PL_REG_START 0x004a1800
-#define BCHP_PCIE_1_RC_PL_REG_END 0x004a1e1c
-#define BCHP_PCIE_1_EP_CFG_TYPE0_REG_START 0x004a2000
-#define BCHP_PCIE_1_EP_CFG_TYPE0_REG_END 0x004a203c
-#define BCHP_PCIE_1_EP_CFG_PM_REG_START 0x004a2048
-#define BCHP_PCIE_1_EP_CFG_PM_REG_END 0x004a204c
-#define BCHP_PCIE_1_EP_CFG_VPD_REG_START 0x004a2050
-#define BCHP_PCIE_1_EP_CFG_VPD_REG_END 0x004a2054
-#define BCHP_PCIE_1_EP_CFG_MSI_REG_START 0x004a2058
-#define BCHP_PCIE_1_EP_CFG_MSI_REG_END 0x004a2064
-#define BCHP_PCIE_1_EP_CFG_MSIX_REG_START 0x004a20a0
-#define BCHP_PCIE_1_EP_CFG_MSIX_REG_END 0x004a20a8
-#define BCHP_PCIE_1_EP_CFG_PCIE_REG_START 0x004a20ac
-#define BCHP_PCIE_1_EP_CFG_PCIE_REG_END 0x004a20e4
-#define BCHP_PCIE_1_EP_CFG_AER_REG_START 0x004a2100
-#define BCHP_PCIE_1_EP_CFG_AER_REG_END 0x004a2134
-#define BCHP_PCIE_1_EP_CFG_DEV_REG_START 0x004a213c
-#define BCHP_PCIE_1_EP_CFG_DEV_REG_END 0x004a2144
-#define BCHP_PCIE_1_EP_CFG_PB_REG_START 0x004a2150
-#define BCHP_PCIE_1_EP_CFG_PB_REG_END 0x004a215c
-#define BCHP_PCIE_1_EP_CFG_VC_REG_START 0x004a2160
-#define BCHP_PCIE_1_EP_CFG_VC_REG_END 0x004a2178
-#define BCHP_PCIE_1_EP_CFG_VENDOR_REG_START 0x004a2180
-#define BCHP_PCIE_1_EP_CFG_VENDOR_REG_END 0x004a21a4
-#define BCHP_PCIE_1_EP_CFG_PRIV0_REG_START 0x004a2404
-#define BCHP_PCIE_1_EP_CFG_PRIV0_REG_END 0x004a2418
-#define BCHP_PCIE_1_EP_CFG_PRIV1_REG_START 0x004a2428
-#define BCHP_PCIE_1_EP_CFG_PRIV1_REG_END 0x004a2630
-#define BCHP_PCIE_1_EP_TL_REG_START 0x004a2800
-#define BCHP_PCIE_1_EP_TL_REG_END 0x004a2998
-#define BCHP_PCIE_1_EP_DL_REG_START 0x004a3000
-#define BCHP_PCIE_1_EP_DL_REG_END 0x004a3424
-#define BCHP_PCIE_1_EP_PL_REG_START 0x004a3800
-#define BCHP_PCIE_1_EP_PL_REG_END 0x004a3e1c
-#define BCHP_PCIE_1_MISC_REG_START 0x004a4000
-#define BCHP_PCIE_1_MISC_REG_END 0x004a40c8
-#define BCHP_PCIE_1_MISC_PERST_REG_START 0x004a4100
-#define BCHP_PCIE_1_MISC_PERST_REG_END 0x004a4104
-#define BCHP_PCIE_1_MISC_HARD_REG_START 0x004a4200
-#define BCHP_PCIE_1_MISC_HARD_REG_END 0x004a4204
-#define BCHP_PCIE_1_INTR2_REG_START 0x004a4300
-#define BCHP_PCIE_1_INTR2_REG_END 0x004a432c
-#define BCHP_PCIE_1_DMA_REG_START 0x004a4400
-#define BCHP_PCIE_1_DMA_REG_END 0x004a446c
-#define BCHP_PCIE_1_EXT_CFG_REG_START 0x004a8000
-#define BCHP_PCIE_1_EXT_CFG_REG_END 0x004a9008
-#define BCHP_PCIE_1_RGR1_REG_START 0x004a9200
-#define BCHP_PCIE_1_RGR1_REG_END 0x004a9210
-#define BCHP_PCIE_1_RG_REG_START 0x004a9300
-#define BCHP_PCIE_1_RG_REG_END 0x004a930c
-#define BCHP_AVS_CPU_PROG_MEM_REG_START 0x004c0000
-#define BCHP_AVS_CPU_PROG_MEM_REG_END 0x004c2ffc
-#define BCHP_AVS_CPU_DATA_MEM_REG_START 0x004c4000
-#define BCHP_AVS_CPU_DATA_MEM_REG_END 0x004c4bfc
-#define BCHP_AVS_CPU_CORE_REGS_REG_START 0x004c8000
-#define BCHP_AVS_CPU_CORE_REGS_REG_END 0x004c80fc
-#define BCHP_AVS_CPU_AUX_REGS_REG_START 0x004ca000
-#define BCHP_AVS_CPU_AUX_REGS_REG_END 0x004cb058
-#define BCHP_AVS_UART_REG_START 0x004d0000
-#define BCHP_AVS_UART_REG_END 0x004d0ffc
-#define BCHP_AVS_CPU_L2_REG_START 0x004d1100
-#define BCHP_AVS_CPU_L2_REG_END 0x004d112c
-#define BCHP_AVS_HOST_L2_REG_START 0x004d1200
-#define BCHP_AVS_HOST_L2_REG_END 0x004d1244
-#define BCHP_AVS_CPU_CTRL_REG_START 0x004d1300
-#define BCHP_AVS_CPU_CTRL_REG_END 0x004d1330
-#define BCHP_AVS_BSTI_REG_START 0x004d1400
-#define BCHP_AVS_BSTI_REG_END 0x004d1404
-#define BCHP_AVS_TMON_REG_START 0x004d1500
-#define BCHP_AVS_TMON_REG_END 0x004d1524
-#define BCHP_AVS_TOP_CTRL_REG_START 0x004d1800
-#define BCHP_AVS_TOP_CTRL_REG_END 0x004d1928
-#define BCHP_AVS_HW_MNTR_REG_START 0x004d2000
-#define BCHP_AVS_HW_MNTR_REG_END 0x004d20c8
-#define BCHP_AVS_PVT_MNTR_CONFIG_REG_START 0x004d2100
-#define BCHP_AVS_PVT_MNTR_CONFIG_REG_END 0x004d2124
-#define BCHP_AVS_RO_REGISTERS_0_REG_START 0x004d2200
-#define BCHP_AVS_RO_REGISTERS_0_REG_END 0x004d22e0
-#define BCHP_AVS_RO_REGISTERS_1_REG_START 0x004d2800
-#define BCHP_AVS_RO_REGISTERS_1_REG_END 0x004d2808
-#define BCHP_AVS_ROSC_THRESHOLD_1_REG_START 0x004d2d00
-#define BCHP_AVS_ROSC_THRESHOLD_1_REG_END 0x004d2dfc
-#define BCHP_AVS_ROSC_THRESHOLD_2_REG_START 0x004d2e00
-#define BCHP_AVS_ROSC_THRESHOLD_2_REG_END 0x004d2efc
-#define BCHP_AVS_WDOG_REG_START 0x004d3000
-#define BCHP_AVS_WDOG_REG_END 0x004d3ffc
-#define BCHP_AVS_PMB_S_000_REG_START 0x004d4000
-#define BCHP_AVS_PMB_S_000_REG_END 0x004d4024
-#define BCHP_AVS_PMB_S_001_REG_START 0x004d4040
-#define BCHP_AVS_PMB_S_001_REG_END 0x004d4064
-#define BCHP_AVS_PMB_S_002_REG_START 0x004d4080
-#define BCHP_AVS_PMB_S_002_REG_END 0x004d40a4
-#define BCHP_AVS_PMB_S_003_REG_START 0x004d40c0
-#define BCHP_AVS_PMB_S_003_REG_END 0x004d40e4
-#define BCHP_AVS_PMB_S_004_REG_START 0x004d4100
-#define BCHP_AVS_PMB_S_004_REG_END 0x004d4124
-#define BCHP_AVS_PMB_S_005_REG_START 0x004d4140
-#define BCHP_AVS_PMB_S_005_REG_END 0x004d4164
-#define BCHP_AVS_PMB_S_006_REG_START 0x004d4180
-#define BCHP_AVS_PMB_S_006_REG_END 0x004d41a4
-#define BCHP_AVS_PMB_S_007_REG_START 0x004d41c0
-#define BCHP_AVS_PMB_S_007_REG_END 0x004d41e4
-#define BCHP_AVS_PMB_S_008_REG_START 0x004d4200
-#define BCHP_AVS_PMB_S_008_REG_END 0x004d4224
-#define BCHP_AVS_PMB_S_009_REG_START 0x004d4240
-#define BCHP_AVS_PMB_S_009_REG_END 0x004d4264
-#define BCHP_AVS_PMB_S_010_REG_START 0x004d4280
-#define BCHP_AVS_PMB_S_010_REG_END 0x004d42a4
-#define BCHP_AVS_PMB_S_011_REG_START 0x004d42c0
-#define BCHP_AVS_PMB_S_011_REG_END 0x004d42e4
-#define BCHP_AVS_PMB_S_012_REG_START 0x004d4300
-#define BCHP_AVS_PMB_S_012_REG_END 0x004d4324
-#define BCHP_AVS_PMB_S_013_REG_START 0x004d4340
-#define BCHP_AVS_PMB_S_013_REG_END 0x004d4364
-#define BCHP_AVS_PMB_S_014_REG_START 0x004d4380
-#define BCHP_AVS_PMB_S_014_REG_END 0x004d43a4
-#define BCHP_AVS_PMB_S_015_REG_START 0x004d43c0
-#define BCHP_AVS_PMB_S_015_REG_END 0x004d43e4
-#define BCHP_AVS_PMB_S_016_REG_START 0x004d4400
-#define BCHP_AVS_PMB_S_016_REG_END 0x004d4424
-#define BCHP_AVS_PMB_S_017_REG_START 0x004d4440
-#define BCHP_AVS_PMB_S_017_REG_END 0x004d4464
-#define BCHP_AVS_PMB_S_018_REG_START 0x004d4480
-#define BCHP_AVS_PMB_S_018_REG_END 0x004d44a4
-#define BCHP_AVS_PMB_S_019_REG_START 0x004d44c0
-#define BCHP_AVS_PMB_S_019_REG_END 0x004d44e4
-#define BCHP_AVS_PMB_S_020_REG_START 0x004d4500
-#define BCHP_AVS_PMB_S_020_REG_END 0x004d4524
-#define BCHP_AVS_PMB_S_021_REG_START 0x004d4540
-#define BCHP_AVS_PMB_S_021_REG_END 0x004d4564
-#define BCHP_AVS_PMB_S_022_REG_START 0x004d4580
-#define BCHP_AVS_PMB_S_022_REG_END 0x004d45a4
-#define BCHP_AVS_PMB_S_023_REG_START 0x004d45c0
-#define BCHP_AVS_PMB_S_023_REG_END 0x004d45e4
-#define BCHP_AVS_PMB_S_024_REG_START 0x004d4600
-#define BCHP_AVS_PMB_S_024_REG_END 0x004d4624
-#define BCHP_AVS_PMB_S_025_REG_START 0x004d4640
-#define BCHP_AVS_PMB_S_025_REG_END 0x004d4664
-#define BCHP_AVS_PMB_S_026_REG_START 0x004d4680
-#define BCHP_AVS_PMB_S_026_REG_END 0x004d46a4
-#define BCHP_AVS_PMB_S_027_REG_START 0x004d46c0
-#define BCHP_AVS_PMB_S_027_REG_END 0x004d46e4
-#define BCHP_AVS_PMB_S_028_REG_START 0x004d4700
-#define BCHP_AVS_PMB_S_028_REG_END 0x004d4724
-#define BCHP_AVS_PMB_S_029_REG_START 0x004d4740
-#define BCHP_AVS_PMB_S_029_REG_END 0x004d4764
-#define BCHP_AVS_PMB_S_030_REG_START 0x004d4780
-#define BCHP_AVS_PMB_S_030_REG_END 0x004d47a4
-#define BCHP_AVS_PMB_S_031_REG_START 0x004d47c0
-#define BCHP_AVS_PMB_S_031_REG_END 0x004d47e4
-#define BCHP_AVS_PMB_S_032_REG_START 0x004d4800
-#define BCHP_AVS_PMB_S_032_REG_END 0x004d4824
-#define BCHP_AVS_PMB_S_033_REG_START 0x004d4840
-#define BCHP_AVS_PMB_S_033_REG_END 0x004d4864
-#define BCHP_AVS_PMB_S_034_REG_START 0x004d4880
-#define BCHP_AVS_PMB_S_034_REG_END 0x004d48a4
-#define BCHP_AVS_PMB_S_035_REG_START 0x004d48c0
-#define BCHP_AVS_PMB_S_035_REG_END 0x004d48e4
-#define BCHP_AVS_PMB_REGISTERS_REG_START 0x004d6000
-#define BCHP_AVS_PMB_REGISTERS_REG_END 0x004d6008
-#define BCHP_CLKGEN_REG_START 0x004e0000
-#define BCHP_CLKGEN_REG_END 0x004e086c
-#define BCHP_VCXO_0_RM_REG_START 0x004e2800
-#define BCHP_VCXO_0_RM_REG_END 0x004e2838
-#define BCHP_VCXO_1_RM_REG_START 0x004e2880
-#define BCHP_VCXO_1_RM_REG_END 0x004e28b8
-#define BCHP_CLKGEN_GR_REG_START 0x004e3000
-#define BCHP_CLKGEN_GR_REG_END 0x004e300c
-#define BCHP_CLKGEN_INTR2_REG_START 0x004e4800
-#define BCHP_CLKGEN_INTR2_REG_END 0x004e4844
-#define BCHP_AVS_RANGE_BLOCKER_REG_START 0x004e5000
-#define BCHP_AVS_RANGE_BLOCKER_REG_END 0x004e5058
-#define BCHP_PROD_OTP_GRB_REG_START 0x004e6000
-#define BCHP_PROD_OTP_GRB_REG_END 0x004e600c
-#define BCHP_JTAG_OTP_REG_START 0x004e6100
-#define BCHP_JTAG_OTP_REG_END 0x004e615c
-#define BCHP_MEMC_GEN_0_REG_START 0x00500000
-#define BCHP_MEMC_GEN_0_REG_END 0x005007fc
-#define BCHP_MEMC_EDIS_0_0_REG_START 0x00500800
-#define BCHP_MEMC_EDIS_0_0_REG_END 0x005008fc
-#define BCHP_MEMC_EDIS_0_1_REG_START 0x00500a00
-#define BCHP_MEMC_EDIS_0_1_REG_END 0x00500afc
-#define BCHP_MEMC_ARC_0_REG_START 0x00500c00
-#define BCHP_MEMC_ARC_0_REG_END 0x00500f74
-#define BCHP_MEMC_ARB_0_REG_START 0x00501000
-#define BCHP_MEMC_ARB_0_REG_END 0x005014cc
-#define BCHP_MEMC_DDR_0_REG_START 0x00502000
-#define BCHP_MEMC_DDR_0_REG_END 0x005027fc
-#define BCHP_MEMC_L2_0_0_REG_START 0x00503000
-#define BCHP_MEMC_L2_0_0_REG_END 0x00503044
-#define BCHP_MEMC_L2_0_1_REG_START 0x00503200
-#define BCHP_MEMC_L2_0_1_REG_END 0x00503244
-#define BCHP_MEMC_L2_0_2_REG_START 0x00503400
-#define BCHP_MEMC_L2_0_2_REG_END 0x00503444
-#define BCHP_MEMC_TRACELOG_0_0_REG_START 0x00503800
-#define BCHP_MEMC_TRACELOG_0_0_REG_END 0x005039fc
-#define BCHP_MEMC_RGRB_0_REG_START 0x00504000
-#define BCHP_MEMC_RGRB_0_REG_END 0x00504010
-#define BCHP_MEMC_MISC_0_REG_START 0x00505000
-#define BCHP_MEMC_MISC_0_REG_END 0x00505010
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_REG_START 0x00506000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_REG_END 0x00506218
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_REG_START 0x00506400
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_REG_END 0x00506518
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_REG_START 0x00506600
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_REG_END 0x00506718
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_REG_START 0x00506800
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_REG_END 0x00506918
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_REG_START 0x00506a00
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_REG_END 0x00506b18
-#define BCHP_DDR34_PHY_ECC_LANE_0_REG_START 0x00506c00
-#define BCHP_DDR34_PHY_ECC_LANE_0_REG_END 0x00506d18
-#define BCHP_SHIMPHY_ADDR_CNTL_0_REG_START 0x00508000
-#define BCHP_SHIMPHY_ADDR_CNTL_0_REG_END 0x005080e0
-#define BCHP_MEMC_SENTINEL_0_0_REG_START 0x00540000
-#define BCHP_MEMC_SENTINEL_0_0_REG_END 0x0057fffc
-#define BCHP_S_MEMC_0_REG_START 0x00580000
-#define BCHP_S_MEMC_0_REG_END 0x00580780
-#define BCHP_MFD_0_REG_START 0x00600000
-#define BCHP_MFD_0_REG_END 0x006001fc
-#define BCHP_MFD_1_REG_START 0x00600400
-#define BCHP_MFD_1_REG_END 0x006005fc
-#define BCHP_MFD_2_REG_START 0x00600800
-#define BCHP_MFD_2_REG_END 0x006009fc
-#define BCHP_VFD_0_REG_START 0x00602000
-#define BCHP_VFD_0_REG_END 0x006021fc
-#define BCHP_VFD_1_REG_START 0x00602200
-#define BCHP_VFD_1_REG_END 0x006023fc
-#define BCHP_VFD_2_REG_START 0x00602400
-#define BCHP_VFD_2_REG_END 0x006025fc
-#define BCHP_VFD_3_REG_START 0x00602600
-#define BCHP_VFD_3_REG_END 0x006027fc
-#define BCHP_RDC_REG_START 0x00603000
-#define BCHP_RDC_REG_END 0x00603cfc
-#define BCHP_BVNF_INTR2_0_REG_START 0x00604000
-#define BCHP_BVNF_INTR2_0_REG_END 0x0060402c
-#define BCHP_BVNF_INTR2_1_REG_START 0x00604100
-#define BCHP_BVNF_INTR2_1_REG_END 0x0060412c
-#define BCHP_BVNF_INTR2_3_REG_START 0x00604300
-#define BCHP_BVNF_INTR2_3_REG_END 0x0060432c
-#define BCHP_BVNF_INTR2_5_REG_START 0x00604500
-#define BCHP_BVNF_INTR2_5_REG_END 0x0060452c
-#define BCHP_BVNF_INTR2_6_REG_START 0x00604600
-#define BCHP_BVNF_INTR2_6_REG_END 0x0060462c
-#define BCHP_BVNF_INTR2_7_REG_START 0x00604700
-#define BCHP_BVNF_INTR2_7_REG_END 0x0060472c
-#define BCHP_BVNF_INTR2_9_REG_START 0x00604900
-#define BCHP_BVNF_INTR2_9_REG_END 0x0060492c
-#define BCHP_BVNF_INTR2_15_REG_START 0x00604f00
-#define BCHP_BVNF_INTR2_15_REG_END 0x00604f2c
-#define BCHP_BVNF_INTR2_16_REG_START 0x00605000
-#define BCHP_BVNF_INTR2_16_REG_END 0x0060502c
-#define BCHP_BVNF_INTR2_18_REG_START 0x00605200
-#define BCHP_BVNF_INTR2_18_REG_END 0x0060522c
-#define BCHP_FMISC_REG_START 0x00606000
-#define BCHP_FMISC_REG_END 0x00606020
-#define BCHP_SCL_0_REG_START 0x00620000
-#define BCHP_SCL_0_REG_END 0x006203fc
-#define BCHP_SCL_1_REG_START 0x00620400
-#define BCHP_SCL_1_REG_END 0x006207fc
-#define BCHP_SCL_2_REG_START 0x00620800
-#define BCHP_SCL_2_REG_END 0x00620bfc
-#define BCHP_SCL_3_REG_START 0x00620c00
-#define BCHP_SCL_3_REG_END 0x00620ffc
-#define BCHP_VNET_F_REG_START 0x00622000
-#define BCHP_VNET_F_REG_END 0x006221fc
-#define BCHP_VNET_B_REG_START 0x00622200
-#define BCHP_VNET_B_REG_END 0x006223fc
-#define BCHP_MMISC_REG_START 0x00622800
-#define BCHP_MMISC_REG_END 0x00622828
-#define BCHP_LBOX_0_REG_START 0x00624000
-#define BCHP_LBOX_0_REG_END 0x00624070
-#define BCHP_XSRC_0_REG_START 0x00624800
-#define BCHP_XSRC_0_REG_END 0x00624bfc
-#define BCHP_XSRC_1_REG_START 0x00624c00
-#define BCHP_XSRC_1_REG_END 0x00624ffc
-#define BCHP_DNR_0_REG_START 0x00626000
-#define BCHP_DNR_0_REG_END 0x006260a4
-#define BCHP_DNR_1_REG_START 0x00626200
-#define BCHP_DNR_1_REG_END 0x006262a4
-#define BCHP_DNR_2_REG_START 0x00626400
-#define BCHP_DNR_2_REG_END 0x006264a4
-#define BCHP_BVNM_INTR2_0_REG_START 0x00627000
-#define BCHP_BVNM_INTR2_0_REG_END 0x0062702c
-#define BCHP_BVNM_INTR2_1_REG_START 0x00627100
-#define BCHP_BVNM_INTR2_1_REG_END 0x0062712c
-#define BCHP_DMISC_REG_START 0x00640000
-#define BCHP_DMISC_REG_END 0x0064001c
-#define BCHP_MVP_TOP_0_REG_START 0x00644000
-#define BCHP_MVP_TOP_0_REG_END 0x0064402c
-#define BCHP_SIOB_0_REG_START 0x00644200
-#define BCHP_SIOB_0_REG_END 0x006442fc
-#define BCHP_HSCL_0_REG_START 0x00644400
-#define BCHP_HSCL_0_REG_END 0x006447fc
-#define BCHP_HD_ANR_MCTF_0_REG_START 0x00645000
-#define BCHP_HD_ANR_MCTF_0_REG_END 0x0064527c
-#define BCHP_HD_ANR_AND_0_REG_START 0x00645800
-#define BCHP_HD_ANR_AND_0_REG_END 0x00645888
-#define BCHP_MDI_TOP_0_REG_START 0x00646000
-#define BCHP_MDI_TOP_0_REG_END 0x006460fc
-#define BCHP_MDI_FCB_0_REG_START 0x00646400
-#define BCHP_MDI_FCB_0_REG_END 0x006467fc
-#define BCHP_MDI_PPB_0_REG_START 0x00646800
-#define BCHP_MDI_PPB_0_REG_END 0x00646bfc
-#define BCHP_MDI_MEMC_0_REG_START 0x00646c00
-#define BCHP_MDI_MEMC_0_REG_END 0x00646dfc
-#define BCHP_MDI_FCN_0_REG_START 0x00646e00
-#define BCHP_MDI_FCN_0_REG_END 0x006471fc
-#define BCHP_MVP_TOP_1_REG_START 0x00650000
-#define BCHP_MVP_TOP_1_REG_END 0x0065002c
-#define BCHP_SIOB_1_REG_START 0x00650200
-#define BCHP_SIOB_1_REG_END 0x006502fc
-#define BCHP_HSCL_1_REG_START 0x00650400
-#define BCHP_HSCL_1_REG_END 0x006507fc
-#define BCHP_MDI_TOP_1_REG_START 0x00652000
-#define BCHP_MDI_TOP_1_REG_END 0x006520fc
-#define BCHP_MDI_PPB_1_REG_START 0x00652800
-#define BCHP_MDI_PPB_1_REG_END 0x00652bfc
-#define BCHP_MDI_FCN_1_REG_START 0x00652c00
-#define BCHP_MDI_FCN_1_REG_END 0x00652ffc
-#define BCHP_MVP_TOP_2_REG_START 0x00658000
-#define BCHP_MVP_TOP_2_REG_END 0x0065802c
-#define BCHP_SIOB_2_REG_START 0x00658200
-#define BCHP_SIOB_2_REG_END 0x006582fc
-#define BCHP_HSCL_2_REG_START 0x00658400
-#define BCHP_HSCL_2_REG_END 0x006587fc
-#define BCHP_MDI_TOP_2_REG_START 0x0065a000
-#define BCHP_MDI_TOP_2_REG_END 0x0065a0fc
-#define BCHP_MDI_PPB_2_REG_START 0x0065a800
-#define BCHP_MDI_PPB_2_REG_END 0x0065abfc
-#define BCHP_MDI_FCN_2_REG_START 0x0065ac00
-#define BCHP_MDI_FCN_2_REG_END 0x0065affc
-#define BCHP_CAP_0_REG_START 0x00680000
-#define BCHP_CAP_0_REG_END 0x0068010c
-#define BCHP_CAP_1_REG_START 0x00680200
-#define BCHP_CAP_1_REG_END 0x0068030c
-#define BCHP_CAP_2_REG_START 0x00680400
-#define BCHP_CAP_2_REG_END 0x0068050c
-#define BCHP_CAP_3_REG_START 0x00680600
-#define BCHP_CAP_3_REG_END 0x0068070c
-#define BCHP_GFD_0_REG_START 0x00681000
-#define BCHP_GFD_0_REG_END 0x0068122c
-#define BCHP_GFD_0_1_REG_START 0x00681400
-#define BCHP_GFD_0_1_REG_END 0x0068162c
-#define BCHP_GFD_1_REG_START 0x00681800
-#define BCHP_GFD_1_REG_END 0x00681a2c
-#define BCHP_GFD_2_REG_START 0x00681c00
-#define BCHP_GFD_2_REG_END 0x00681e2c
-#define BCHP_CMP_0_REG_START 0x00683000
-#define BCHP_CMP_0_REG_END 0x0068351c
-#define BCHP_CMP_1_REG_START 0x00683800
-#define BCHP_CMP_1_REG_END 0x00683cc0
-#define BCHP_CMP_2_REG_START 0x00684000
-#define BCHP_CMP_2_REG_END 0x00684260
-#define BCHP_TNT_CMP_0_V0_REG_START 0x00685800
-#define BCHP_TNT_CMP_0_V0_REG_END 0x006858a4
-#define BCHP_MASK_0_REG_START 0x00685c00
-#define BCHP_MASK_0_REG_END 0x00685c20
-#define BCHP_PEP_CMP_0_V0_REG_START 0x00686000
-#define BCHP_PEP_CMP_0_V0_REG_END 0x00687284
-#define BCHP_TNT_CMP_1_V0_REG_START 0x00687600
-#define BCHP_TNT_CMP_1_V0_REG_END 0x006876a4
-#define BCHP_MASK_1_REG_START 0x00687800
-#define BCHP_MASK_1_REG_END 0x00687820
-#define BCHP_BVNB_INTR2_REG_START 0x00688000
-#define BCHP_BVNB_INTR2_REG_END 0x0068802c
-#define BCHP_BMISC_REG_START 0x00688400
-#define BCHP_BMISC_REG_END 0x0068841c
-#define BCHP_MISC_REG_START 0x006a0000
-#define BCHP_MISC_REG_END 0x006a00ac
-#define BCHP_IT_0_REG_START 0x006a1000
-#define BCHP_IT_0_REG_END 0x006a17fc
-#define BCHP_IT_1_REG_START 0x006a2000
-#define BCHP_IT_1_REG_END 0x006a27fc
-#define BCHP_VF_0_REG_START 0x006a3000
-#define BCHP_VF_0_REG_END 0x006a3134
-#define BCHP_SECAM_0_REG_START 0x006a3200
-#define BCHP_SECAM_0_REG_END 0x006a3214
-#define BCHP_SM_0_REG_START 0x006a3280
-#define BCHP_SM_0_REG_END 0x006a32ac
-#define BCHP_SDSRC_0_REG_START 0x006a3300
-#define BCHP_SDSRC_0_REG_END 0x006a330c
-#define BCHP_HDSRC_0_REG_START 0x006a3320
-#define BCHP_HDSRC_0_REG_END 0x006a333c
-#define BCHP_CSC_0_REG_START 0x006a3380
-#define BCHP_CSC_0_REG_END 0x006a33b0
-#define BCHP_RM_0_REG_START 0x006a3400
-#define BCHP_RM_0_REG_END 0x006a3430
-#define BCHP_RM_1_REG_START 0x006a3440
-#define BCHP_RM_1_REG_END 0x006a3470
-#define BCHP_ANA_DEBUG_0_REG_START 0x006a3500
-#define BCHP_ANA_DEBUG_0_REG_END 0x006a3544
-#define BCHP_DVI_MISC_0_REG_START 0x006a3600
-#define BCHP_DVI_MISC_0_REG_END 0x006a3600
-#define BCHP_DVI_DTG_0_REG_START 0x006a4000
-#define BCHP_DVI_DTG_0_REG_END 0x006a4488
-#define BCHP_DVI_DTG_RM_0_REG_START 0x006a4800
-#define BCHP_DVI_DTG_RM_0_REG_END 0x006a4830
-#define BCHP_DVI_CSC_0_REG_START 0x006a4900
-#define BCHP_DVI_CSC_0_REG_END 0x006a4930
-#define BCHP_DVI_FC_0_REG_START 0x006a4a00
-#define BCHP_DVI_FC_0_REG_END 0x006a4a04
-#define BCHP_DVI_DVF_0_REG_START 0x006a4b00
-#define BCHP_DVI_DVF_0_REG_END 0x006a4b18
-#define BCHP_DVI_DEBUG_0_REG_START 0x006a4c00
-#define BCHP_DVI_DEBUG_0_REG_END 0x006a4c44
-#define BCHP_DVI_MISC_1_REG_START 0x006a4d00
-#define BCHP_DVI_MISC_1_REG_END 0x006a4d00
-#define BCHP_DVI_DTG_1_REG_START 0x006a5000
-#define BCHP_DVI_DTG_1_REG_END 0x006a5488
-#define BCHP_DVI_DTG_RM_1_REG_START 0x006a5800
-#define BCHP_DVI_DTG_RM_1_REG_END 0x006a5830
-#define BCHP_DVI_CSC_1_REG_START 0x006a5900
-#define BCHP_DVI_CSC_1_REG_END 0x006a5930
-#define BCHP_DVI_DVF_1_REG_START 0x006a5a00
-#define BCHP_DVI_DVF_1_REG_END 0x006a5a18
-#define BCHP_DVI_DEBUG_1_REG_START 0x006a5b00
-#define BCHP_DVI_DEBUG_1_REG_END 0x006a5b44
-#define BCHP_ITU656_DTG_0_REG_START 0x006a6000
-#define BCHP_ITU656_DTG_0_REG_END 0x006a6488
-#define BCHP_ITU656_CSC_0_REG_START 0x006a6600
-#define BCHP_ITU656_CSC_0_REG_END 0x006a6630
-#define BCHP_ITU656_DVF_0_REG_START 0x006a6700
-#define BCHP_ITU656_DVF_0_REG_END 0x006a6718
-#define BCHP_ITU656_0_REG_START 0x006a6800
-#define BCHP_ITU656_0_REG_END 0x006a6820
-#define BCHP_VEC_CFG_REG_START 0x006a6c00
-#define BCHP_VEC_CFG_REG_END 0x006a6d48
-#define BCHP_VIDEO_ENC_INTR2_REG_START 0x006a7000
-#define BCHP_VIDEO_ENC_INTR2_REG_END 0x006a702c
-#define BCHP_VIDEO_ENC_TPG_0_REG_START 0x006a7200
-#define BCHP_VIDEO_ENC_TPG_0_REG_END 0x006a7320
-#define BCHP_VIDEO_ENC_STG_0_REG_START 0x006a7400
-#define BCHP_VIDEO_ENC_STG_0_REG_END 0x006a745c
-#define BCHP_VIDEO_ENC_STG_1_REG_START 0x006a7500
-#define BCHP_VIDEO_ENC_STG_1_REG_END 0x006a755c
-#define BCHP_VIDEO_ENC_DECIM_0_REG_START 0x006a7600
-#define BCHP_VIDEO_ENC_DECIM_0_REG_END 0x006a7608
-#define BCHP_VIDEO_ENC_BP_FIFO_0_REG_START 0x006a7700
-#define BCHP_VIDEO_ENC_BP_FIFO_0_REG_END 0x006a772c
-#define BCHP_DVP_TVG_0_REG_START 0x006a7800
-#define BCHP_DVP_TVG_0_REG_END 0x006a7888
-#define BCHP_DVP_TVG_1_REG_START 0x006a7900
-#define BCHP_DVP_TVG_1_REG_END 0x006a7988
-#define BCHP_VBI_ENC_REG_START 0x006a8000
-#define BCHP_VBI_ENC_REG_END 0x006a8074
-#define BCHP_CCE_0_REG_START 0x006a8400
-#define BCHP_CCE_0_REG_END 0x006a8458
-#define BCHP_WSE_0_REG_START 0x006a8500
-#define BCHP_WSE_0_REG_END 0x006a8514
-#define BCHP_CGMSAE_0_REG_START 0x006a8600
-#define BCHP_CGMSAE_0_REG_END 0x006a8658
-#define BCHP_TTE_0_REG_START 0x006a8700
-#define BCHP_TTE_0_REG_END 0x006a8728
-#define BCHP_GSE_0_REG_START 0x006a8800
-#define BCHP_GSE_0_REG_END 0x006a8880
-#define BCHP_AMOLE_0_REG_START 0x006a8900
-#define BCHP_AMOLE_0_REG_END 0x006a898c
-#define BCHP_CCE_ANCIL_0_REG_START 0x006a8a00
-#define BCHP_CCE_ANCIL_0_REG_END 0x006a8a54
-#define BCHP_WSE_ANCIL_0_REG_START 0x006a8b00
-#define BCHP_WSE_ANCIL_0_REG_END 0x006a8b0c
-#define BCHP_TTE_ANCIL_0_REG_START 0x006a8c00
-#define BCHP_TTE_ANCIL_0_REG_END 0x006a8c28
-#define BCHP_GSE_ANCIL_0_REG_START 0x006a8d00
-#define BCHP_GSE_ANCIL_0_REG_END 0x006a8d80
-#define BCHP_AMOLE_ANCIL_0_REG_START 0x006a8e00
-#define BCHP_AMOLE_ANCIL_0_REG_END 0x006a8e8c
-#define BCHP_ANCI656_ANCIL_0_REG_START 0x006a8f00
-#define BCHP_ANCI656_ANCIL_0_REG_END 0x006a8f24
-#define BCHP_DVP_HT_REG_START 0x006c0000
-#define BCHP_DVP_HT_REG_END 0x006c0114
-#define BCHP_HDMI_REG_START 0x006c0800
-#define BCHP_HDMI_REG_END 0x006c0afc
-#define BCHP_HDMI_TX_AUTO_I2C_REG_START 0x006c0b00
-#define BCHP_HDMI_TX_AUTO_I2C_REG_END 0x006c0dfc
-#define BCHP_HDMI_TX_PHY_REG_START 0x006c0e00
-#define BCHP_HDMI_TX_PHY_REG_END 0x006c0e7c
-#define BCHP_HDMI_RM_REG_START 0x006c0e80
-#define BCHP_HDMI_RM_REG_END 0x006c0eb8
-#define BCHP_HDMI_TX_INTR2_REG_START 0x006c0f00
-#define BCHP_HDMI_TX_INTR2_REG_END 0x006c0f2c
-#define BCHP_HDMI_TX_SCDC_INTR2_0_REG_START 0x006c0f80
-#define BCHP_HDMI_TX_SCDC_INTR2_0_REG_END 0x006c0fac
-#define BCHP_HDCP2_TX_HAE_INTR2_0_REG_START 0x006c1000
-#define BCHP_HDCP2_TX_HAE_INTR2_0_REG_END 0x006c102c
-#define BCHP_HDMI_TX_HAE_INTR2_0_REG_START 0x006c1080
-#define BCHP_HDMI_TX_HAE_INTR2_0_REG_END 0x006c10ac
-#define BCHP_HDMI_RAM_REG_START 0x006c1100
-#define BCHP_HDMI_RAM_REG_END 0x006c12fc
-#define BCHP_BVN_RGR_REG_START 0x006e0000
-#define BCHP_BVN_RGR_REG_END 0x006e0010
-#define BCHP_VICE2_CABAC_0_0_REG_START 0x00700000
-#define BCHP_VICE2_CABAC_0_0_REG_END 0x007002ec
-#define BCHP_VICE2_CME_0_0_REG_START 0x00700400
-#define BCHP_VICE2_CME_0_0_REG_END 0x007004a0
-#define BCHP_VICE2_DBLK_0_0_REG_START 0x00700800
-#define BCHP_VICE2_DBLK_0_0_REG_END 0x0070088c
-#define BCHP_VICE2_FME_0_0_REG_START 0x00701000
-#define BCHP_VICE2_FME_0_0_REG_END 0x007010c0
-#define BCHP_VICE2_HA_0_0_REG_START 0x00701400
-#define BCHP_VICE2_HA_0_0_REG_END 0x0070148c
-#define BCHP_VICE2_IMD_0_0_REG_START 0x00701800
-#define BCHP_VICE2_IMD_0_0_REG_END 0x0070187c
-#define BCHP_VICE2_MAU_0_0_REG_START 0x00701c00
-#define BCHP_VICE2_MAU_0_0_REG_END 0x00701d28
-#define BCHP_VICE2_MC_0_0_REG_START 0x00702000
-#define BCHP_VICE2_MC_0_0_REG_END 0x0070208c
-#define BCHP_VICE2_SG_0_0_REG_START 0x00702400
-#define BCHP_VICE2_SG_0_0_REG_END 0x007025e4
-#define BCHP_VICE2_VIP_0_0_REG_START 0x00702800
-#define BCHP_VICE2_VIP_0_0_REG_END 0x00702a24
-#define BCHP_VICE2_VIP1_0_0_REG_START 0x00702c00
-#define BCHP_VICE2_VIP1_0_0_REG_END 0x00702e24
-#define BCHP_VICE2_VIP2_0_0_REG_START 0x00703000
-#define BCHP_VICE2_VIP2_0_0_REG_END 0x00703224
-#define BCHP_VICE2_VIP3_0_0_REG_START 0x00703400
-#define BCHP_VICE2_VIP3_0_0_REG_END 0x00703624
-#define BCHP_VICE2_XQ_0_0_REG_START 0x00704000
-#define BCHP_VICE2_XQ_0_0_REG_END 0x00705338
-#define BCHP_VICE2_ARCSS_ESS_ADI_0_0_REG_START 0x00718000
-#define BCHP_VICE2_ARCSS_ESS_ADI_0_0_REG_END 0x007182b4
-#define BCHP_VICE2_ARCSS_ESS_CTRL_0_0_REG_START 0x00720000
-#define BCHP_VICE2_ARCSS_ESS_CTRL_0_0_REG_END 0x007200a4
-#define BCHP_VICE2_ARCSS_ESS_FLAG_INTR2_0_0_REG_START 0x00720400
-#define BCHP_VICE2_ARCSS_ESS_FLAG_INTR2_0_0_REG_END 0x0072042c
-#define BCHP_VICE2_ARCSS_ESS_P1_INTR2_0_0_REG_START 0x00720600
-#define BCHP_VICE2_ARCSS_ESS_P1_INTR2_0_0_REG_END 0x0072062c
-#define BCHP_VICE2_ARCSS_ESS_HOSTIF_0_0_REG_START 0x00722000
-#define BCHP_VICE2_ARCSS_ESS_HOSTIF_0_0_REG_END 0x007233fc
-#define BCHP_VICE2_ARCSS_ESS_DCCM_0_0_REG_START 0x00730000
-#define BCHP_VICE2_ARCSS_ESS_DCCM_0_0_REG_END 0x0073fffc
-#define BCHP_VICE2_ARCSS_ESS_ADI_1_0_REG_START 0x00758000
-#define BCHP_VICE2_ARCSS_ESS_ADI_1_0_REG_END 0x007582a8
-#define BCHP_VICE2_ARCSS_ESS_CTRL_1_0_REG_START 0x00760000
-#define BCHP_VICE2_ARCSS_ESS_CTRL_1_0_REG_END 0x007600a4
-#define BCHP_VICE2_ARCSS_ESS_FLAG_INTR2_1_0_REG_START 0x00760400
-#define BCHP_VICE2_ARCSS_ESS_FLAG_INTR2_1_0_REG_END 0x0076042c
-#define BCHP_VICE2_ARCSS_ESS_P1_INTR2_1_0_REG_START 0x00760600
-#define BCHP_VICE2_ARCSS_ESS_P1_INTR2_1_0_REG_END 0x0076062c
-#define BCHP_VICE2_ARCSS_ESS_HOSTIF_1_0_REG_START 0x00762000
-#define BCHP_VICE2_ARCSS_ESS_HOSTIF_1_0_REG_END 0x007633fc
-#define BCHP_VICE2_ARCSS_ESS_DCCM_1_0_REG_START 0x00770000
-#define BCHP_VICE2_ARCSS_ESS_DCCM_1_0_REG_END 0x0077fffc
-#define BCHP_VICE2_RGR_0_REG_START 0x00780000
-#define BCHP_VICE2_RGR_0_REG_END 0x0078000c
-#define BCHP_VICE2_MISC_0_REG_START 0x00781000
-#define BCHP_VICE2_MISC_0_REG_END 0x00781050
-#define BCHP_VICE2_L2_0_REG_START 0x00781100
-#define BCHP_VICE2_L2_0_REG_END 0x0078112c
-#define BCHP_VICE2_ARCSS_MISC_0_REG_START 0x00782000
-#define BCHP_VICE2_ARCSS_MISC_0_REG_END 0x007820b8
-#define BCHP_VICE2_SEC_CTRL_0_REG_START 0x00800000
-#define BCHP_VICE2_SEC_CTRL_0_REG_END 0x00800080
-#define BCHP_MEMC_GEN_1_REG_START 0x00900000
-#define BCHP_MEMC_GEN_1_REG_END 0x009007fc
-#define BCHP_MEMC_EDIS_1_0_REG_START 0x00900800
-#define BCHP_MEMC_EDIS_1_0_REG_END 0x009008fc
-#define BCHP_MEMC_EDIS_1_1_REG_START 0x00900a00
-#define BCHP_MEMC_EDIS_1_1_REG_END 0x00900afc
-#define BCHP_MEMC_ARC_1_REG_START 0x00900c00
-#define BCHP_MEMC_ARC_1_REG_END 0x00900f74
-#define BCHP_MEMC_ARB_1_REG_START 0x00901000
-#define BCHP_MEMC_ARB_1_REG_END 0x009014cc
-#define BCHP_MEMC_DDR_1_REG_START 0x00902000
-#define BCHP_MEMC_DDR_1_REG_END 0x009027fc
-#define BCHP_MEMC_L2_1_0_REG_START 0x00903000
-#define BCHP_MEMC_L2_1_0_REG_END 0x00903044
-#define BCHP_MEMC_L2_1_1_REG_START 0x00903200
-#define BCHP_MEMC_L2_1_1_REG_END 0x00903244
-#define BCHP_MEMC_L2_1_2_REG_START 0x00903400
-#define BCHP_MEMC_L2_1_2_REG_END 0x00903444
-#define BCHP_MEMC_TRACELOG_0_1_REG_START 0x00903800
-#define BCHP_MEMC_TRACELOG_0_1_REG_END 0x009039fc
-#define BCHP_MEMC_RGRB_1_REG_START 0x00904000
-#define BCHP_MEMC_RGRB_1_REG_END 0x00904010
-#define BCHP_MEMC_MISC_1_REG_START 0x00905000
-#define BCHP_MEMC_MISC_1_REG_END 0x00905010
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_REG_START 0x00906000
-#define BCHP_DDR34_PHY_CONTROL_REGS_1_REG_END 0x00906218
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_REG_START 0x00906400
-#define BCHP_DDR34_PHY_BYTE_LANE_0_1_REG_END 0x00906518
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_REG_START 0x00906600
-#define BCHP_DDR34_PHY_BYTE_LANE_1_1_REG_END 0x00906718
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_REG_START 0x00906800
-#define BCHP_DDR34_PHY_BYTE_LANE_2_1_REG_END 0x00906918
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_REG_START 0x00906a00
-#define BCHP_DDR34_PHY_BYTE_LANE_3_1_REG_END 0x00906b18
-#define BCHP_DDR34_PHY_ECC_LANE_1_REG_START 0x00906c00
-#define BCHP_DDR34_PHY_ECC_LANE_1_REG_END 0x00906d18
-#define BCHP_SHIMPHY_ADDR_CNTL_1_REG_START 0x00908000
-#define BCHP_SHIMPHY_ADDR_CNTL_1_REG_END 0x009080e0
-#define BCHP_MEMC_SENTINEL_0_1_REG_START 0x00940000
-#define BCHP_MEMC_SENTINEL_0_1_REG_END 0x0097fffc
-#define BCHP_S_MEMC_1_REG_START 0x00980000
-#define BCHP_S_MEMC_1_REG_END 0x00980780
-#define BCHP_XPT_BUS_IF_SUB_MODULE_SOFT_INIT_DONE_INTR2_REG_START 0x00a00000
-#define BCHP_XPT_BUS_IF_SUB_MODULE_SOFT_INIT_DONE_INTR2_REG_END 0x00a0002c
-#define BCHP_XPT_BUS_IF_REG_START 0x00a00080
-#define BCHP_XPT_BUS_IF_REG_END 0x00a000fc
-#define BCHP_XPT_XMEMIF_REG_START 0x00a00100
-#define BCHP_XPT_XMEMIF_REG_END 0x00a001fc
-#define BCHP_XPT_PMU_REG_START 0x00a00200
-#define BCHP_XPT_PMU_REG_END 0x00a00218
-#define BCHP_XPT_GR_REG_START 0x00a00300
-#define BCHP_XPT_GR_REG_END 0x00a0030c
-#define BCHP_XPT_RMX0_IO_REG_START 0x00a00400
-#define BCHP_XPT_RMX0_IO_REG_END 0x00a00420
-#define BCHP_XPT_RMX1_IO_REG_START 0x00a00500
-#define BCHP_XPT_RMX1_IO_REG_END 0x00a00520
-#define BCHP_XPT_WAKEUP_REG_START 0x00a01000
-#define BCHP_XPT_WAKEUP_REG_END 0x00a01fbc
-#define BCHP_XPT_DPCR0_REG_START 0x00a02000
-#define BCHP_XPT_DPCR0_REG_END 0x00a02074
-#define BCHP_XPT_DPCR1_REG_START 0x00a02080
-#define BCHP_XPT_DPCR1_REG_END 0x00a020f4
-#define BCHP_XPT_DPCR2_REG_START 0x00a02100
-#define BCHP_XPT_DPCR2_REG_END 0x00a02174
-#define BCHP_XPT_DPCR3_REG_START 0x00a02180
-#define BCHP_XPT_DPCR3_REG_END 0x00a021f4
-#define BCHP_XPT_DPCR4_REG_START 0x00a02200
-#define BCHP_XPT_DPCR4_REG_END 0x00a02274
-#define BCHP_XPT_DPCR5_REG_START 0x00a02280
-#define BCHP_XPT_DPCR5_REG_END 0x00a022f4
-#define BCHP_XPT_DPCR6_REG_START 0x00a02300
-#define BCHP_XPT_DPCR6_REG_END 0x00a02374
-#define BCHP_XPT_DPCR7_REG_START 0x00a02380
-#define BCHP_XPT_DPCR7_REG_END 0x00a023f4
-#define BCHP_XPT_DPCR8_REG_START 0x00a02400
-#define BCHP_XPT_DPCR8_REG_END 0x00a02474
-#define BCHP_XPT_DPCR9_REG_START 0x00a02480
-#define BCHP_XPT_DPCR9_REG_END 0x00a024f4
-#define BCHP_XPT_DPCR10_REG_START 0x00a02500
-#define BCHP_XPT_DPCR10_REG_END 0x00a02574
-#define BCHP_XPT_DPCR11_REG_START 0x00a02580
-#define BCHP_XPT_DPCR11_REG_END 0x00a025f4
-#define BCHP_XPT_DPCR12_REG_START 0x00a02600
-#define BCHP_XPT_DPCR12_REG_END 0x00a02674
-#define BCHP_XPT_DPCR13_REG_START 0x00a02680
-#define BCHP_XPT_DPCR13_REG_END 0x00a026f4
-#define BCHP_XPT_DPCR_PP_REG_START 0x00a02800
-#define BCHP_XPT_DPCR_PP_REG_END 0x00a02804
-#define BCHP_XPT_PSUB_REG_START 0x00a02a00
-#define BCHP_XPT_PSUB_REG_END 0x00a02b88
-#define BCHP_XPT_MPOD_REG_START 0x00a02c00
-#define BCHP_XPT_MPOD_REG_END 0x00a02c20
-#define BCHP_XPT_RMX0_REG_START 0x00a02d00
-#define BCHP_XPT_RMX0_REG_END 0x00a02d10
-#define BCHP_XPT_RMX1_REG_START 0x00a02e00
-#define BCHP_XPT_RMX1_REG_END 0x00a02e10
-#define BCHP_XPT_RSBUFF_REG_START 0x00a04000
-#define BCHP_XPT_RSBUFF_REG_END 0x00a054fc
-#define BCHP_XPT_XCBUFF_REG_START 0x00a06000
-#define BCHP_XPT_XCBUFF_REG_END 0x00a07e9c
-#define BCHP_XPT_PCROFFSET_REG_START 0x00a08000
-#define BCHP_XPT_PCROFFSET_REG_END 0x00a0aafc
-#define BCHP_XPT_TSIO_CONFIG_REGISTERS_REG_START 0x00a0c000
-#define BCHP_XPT_TSIO_CONFIG_REGISTERS_REG_END 0x00a0ea04
-#define BCHP_XPT_TSIO_CALIB_REGISTERS_REG_START 0x00a0f000
-#define BCHP_XPT_TSIO_CALIB_REGISTERS_REG_END 0x00a0f9fc
-#define BCHP_XPT_TSIO_INTR_L2_REG_START 0x00a0fc00
-#define BCHP_XPT_TSIO_INTR_L2_REG_END 0x00a0fc2c
-#define BCHP_XPT_FULL_PID_PARSER_REG_START 0x00a10000
-#define BCHP_XPT_FULL_PID_PARSER_REG_END 0x00a14050
-#define BCHP_XPT_FE_REG_START 0x00a20000
-#define BCHP_XPT_FE_REG_END 0x00a25ffc
-#define BCHP_XPT_MSG_REG_START 0x00a30000
-#define BCHP_XPT_MSG_REG_END 0x00a3ca14
-#define BCHP_XPT_MSG_BUF_DAT_RDY_CPU_INTR_AGGREGATOR_REG_START 0x00a3fb00
-#define BCHP_XPT_MSG_BUF_DAT_RDY_CPU_INTR_AGGREGATOR_REG_END 0x00a3fb1c
-#define BCHP_XPT_MSG_BUF_OVFL_CPU_INTR_AGGREGATOR_REG_START 0x00a3fb20
-#define BCHP_XPT_MSG_BUF_OVFL_CPU_INTR_AGGREGATOR_REG_END 0x00a3fb3c
-#define BCHP_XPT_MSG_BUF_DAT_RDY_PCI_INTR_AGGREGATOR_REG_START 0x00a3fb40
-#define BCHP_XPT_MSG_BUF_DAT_RDY_PCI_INTR_AGGREGATOR_REG_END 0x00a3fb5c
-#define BCHP_XPT_MSG_BUF_OVFL_PCI_INTR_AGGREGATOR_REG_START 0x00a3fb60
-#define BCHP_XPT_MSG_BUF_OVFL_PCI_INTR_AGGREGATOR_REG_END 0x00a3fb7c
-#define BCHP_XPT_MSG_DAT_ERR_INTR_L2_REG_START 0x00a3fb80
-#define BCHP_XPT_MSG_DAT_ERR_INTR_L2_REG_END 0x00a3fbac
-#define BCHP_XPT_MSG_BUF_DAT_RDY_INTR_00_31_L2_REG_START 0x00a3fc00
-#define BCHP_XPT_MSG_BUF_DAT_RDY_INTR_00_31_L2_REG_END 0x00a3fc2c
-#define BCHP_XPT_MSG_BUF_DAT_RDY_INTR_32_63_L2_REG_START 0x00a3fc40
-#define BCHP_XPT_MSG_BUF_DAT_RDY_INTR_32_63_L2_REG_END 0x00a3fc6c
-#define BCHP_XPT_MSG_BUF_DAT_RDY_INTR_64_95_L2_REG_START 0x00a3fc80
-#define BCHP_XPT_MSG_BUF_DAT_RDY_INTR_64_95_L2_REG_END 0x00a3fcac
-#define BCHP_XPT_MSG_BUF_DAT_RDY_INTR_96_127_L2_REG_START 0x00a3fcc0
-#define BCHP_XPT_MSG_BUF_DAT_RDY_INTR_96_127_L2_REG_END 0x00a3fcec
-#define BCHP_XPT_MSG_BUF_DAT_RDY_INTR_128_159_L2_REG_START 0x00a3fd00
-#define BCHP_XPT_MSG_BUF_DAT_RDY_INTR_128_159_L2_REG_END 0x00a3fd2c
-#define BCHP_XPT_MSG_BUF_DAT_RDY_INTR_160_191_L2_REG_START 0x00a3fd40
-#define BCHP_XPT_MSG_BUF_DAT_RDY_INTR_160_191_L2_REG_END 0x00a3fd6c
-#define BCHP_XPT_MSG_BUF_DAT_RDY_INTR_192_223_L2_REG_START 0x00a3fd80
-#define BCHP_XPT_MSG_BUF_DAT_RDY_INTR_192_223_L2_REG_END 0x00a3fdac
-#define BCHP_XPT_MSG_BUF_DAT_RDY_INTR_224_255_L2_REG_START 0x00a3fdc0
-#define BCHP_XPT_MSG_BUF_DAT_RDY_INTR_224_255_L2_REG_END 0x00a3fdec
-#define BCHP_XPT_MSG_BUF_OVFL_INTR_00_31_L2_REG_START 0x00a3fe00
-#define BCHP_XPT_MSG_BUF_OVFL_INTR_00_31_L2_REG_END 0x00a3fe2c
-#define BCHP_XPT_MSG_BUF_OVFL_INTR_32_63_L2_REG_START 0x00a3fe40
-#define BCHP_XPT_MSG_BUF_OVFL_INTR_32_63_L2_REG_END 0x00a3fe6c
-#define BCHP_XPT_MSG_BUF_OVFL_INTR_64_95_L2_REG_START 0x00a3fe80
-#define BCHP_XPT_MSG_BUF_OVFL_INTR_64_95_L2_REG_END 0x00a3feac
-#define BCHP_XPT_MSG_BUF_OVFL_INTR_96_127_L2_REG_START 0x00a3fec0
-#define BCHP_XPT_MSG_BUF_OVFL_INTR_96_127_L2_REG_END 0x00a3feec
-#define BCHP_XPT_MSG_BUF_OVFL_INTR_128_159_L2_REG_START 0x00a3ff00
-#define BCHP_XPT_MSG_BUF_OVFL_INTR_128_159_L2_REG_END 0x00a3ff2c
-#define BCHP_XPT_MSG_BUF_OVFL_INTR_160_191_L2_REG_START 0x00a3ff40
-#define BCHP_XPT_MSG_BUF_OVFL_INTR_160_191_L2_REG_END 0x00a3ff6c
-#define BCHP_XPT_MSG_BUF_OVFL_INTR_192_223_L2_REG_START 0x00a3ff80
-#define BCHP_XPT_MSG_BUF_OVFL_INTR_192_223_L2_REG_END 0x00a3ffac
-#define BCHP_XPT_MSG_BUF_OVFL_INTR_224_255_L2_REG_START 0x00a3ffc0
-#define BCHP_XPT_MSG_BUF_OVFL_INTR_224_255_L2_REG_END 0x00a3ffec
-#define BCHP_XPT_RAVE_REG_START 0x00a40000
-#define BCHP_XPT_RAVE_REG_END 0x00a4e174
-#define BCHP_XPT_RAVE_CPU_INTR_AGGREGATOR_REG_START 0x00a4f000
-#define BCHP_XPT_RAVE_CPU_INTR_AGGREGATOR_REG_END 0x00a4f01c
-#define BCHP_XPT_RAVE_PCI_INTR_AGGREGATOR_REG_START 0x00a4f020
-#define BCHP_XPT_RAVE_PCI_INTR_AGGREGATOR_REG_END 0x00a4f03c
-#define BCHP_XPT_RAVE_MISC_L2_INTR_REG_START 0x00a4f040
-#define BCHP_XPT_RAVE_MISC_L2_INTR_REG_END 0x00a4f06c
-#define BCHP_XPT_RAVE_EMU_ERROR_CX00_31_L2_INTR_REG_START 0x00a4f080
-#define BCHP_XPT_RAVE_EMU_ERROR_CX00_31_L2_INTR_REG_END 0x00a4f0ac
-#define BCHP_XPT_RAVE_EMU_ERROR_CX32_47_L2_INTR_REG_START 0x00a4f0c0
-#define BCHP_XPT_RAVE_EMU_ERROR_CX32_47_L2_INTR_REG_END 0x00a4f0ec
-#define BCHP_XPT_RAVE_PUSI_ERROR_CX00_31_L2_INTR_REG_START 0x00a4f100
-#define BCHP_XPT_RAVE_PUSI_ERROR_CX00_31_L2_INTR_REG_END 0x00a4f12c
-#define BCHP_XPT_RAVE_PUSI_ERROR_CX32_47_L2_INTR_REG_START 0x00a4f140
-#define BCHP_XPT_RAVE_PUSI_ERROR_CX32_47_L2_INTR_REG_END 0x00a4f16c
-#define BCHP_XPT_RAVE_TEI_ERROR_CX00_31_L2_INTR_REG_START 0x00a4f180
-#define BCHP_XPT_RAVE_TEI_ERROR_CX00_31_L2_INTR_REG_END 0x00a4f1ac
-#define BCHP_XPT_RAVE_TEI_ERROR_CX32_47_L2_INTR_REG_START 0x00a4f1c0
-#define BCHP_XPT_RAVE_TEI_ERROR_CX32_47_L2_INTR_REG_END 0x00a4f1ec
-#define BCHP_XPT_RAVE_CC_ERROR_CX00_31_L2_INTR_REG_START 0x00a4f200
-#define BCHP_XPT_RAVE_CC_ERROR_CX00_31_L2_INTR_REG_END 0x00a4f22c
-#define BCHP_XPT_RAVE_CC_ERROR_CX32_47_L2_INTR_REG_START 0x00a4f240
-#define BCHP_XPT_RAVE_CC_ERROR_CX32_47_L2_INTR_REG_END 0x00a4f26c
-#define BCHP_XPT_RAVE_CDB_OVERFLOW_CX00_31_L2_INTR_REG_START 0x00a4f280
-#define BCHP_XPT_RAVE_CDB_OVERFLOW_CX00_31_L2_INTR_REG_END 0x00a4f2ac
-#define BCHP_XPT_RAVE_CDB_OVERFLOW_CX32_47_L2_INTR_REG_START 0x00a4f2c0
-#define BCHP_XPT_RAVE_CDB_OVERFLOW_CX32_47_L2_INTR_REG_END 0x00a4f2ec
-#define BCHP_XPT_RAVE_ITB_OVERFLOW_CX00_31_L2_INTR_REG_START 0x00a4f300
-#define BCHP_XPT_RAVE_ITB_OVERFLOW_CX00_31_L2_INTR_REG_END 0x00a4f32c
-#define BCHP_XPT_RAVE_ITB_OVERFLOW_CX32_47_L2_INTR_REG_START 0x00a4f340
-#define BCHP_XPT_RAVE_ITB_OVERFLOW_CX32_47_L2_INTR_REG_END 0x00a4f36c
-#define BCHP_XPT_RAVE_SPLICE_CX00_31_L2_INTR_REG_START 0x00a4f380
-#define BCHP_XPT_RAVE_SPLICE_CX00_31_L2_INTR_REG_END 0x00a4f3ac
-#define BCHP_XPT_RAVE_SPLICE_CX32_47_L2_INTR_REG_START 0x00a4f3c0
-#define BCHP_XPT_RAVE_SPLICE_CX32_47_L2_INTR_REG_END 0x00a4f3ec
-#define BCHP_XPT_RAVE_LAST_CMD_CX00_31_L2_INTR_REG_START 0x00a4f400
-#define BCHP_XPT_RAVE_LAST_CMD_CX00_31_L2_INTR_REG_END 0x00a4f42c
-#define BCHP_XPT_RAVE_LAST_CMD_CX32_47_L2_INTR_REG_START 0x00a4f440
-#define BCHP_XPT_RAVE_LAST_CMD_CX32_47_L2_INTR_REG_END 0x00a4f46c
-#define BCHP_XPT_RAVE_CDB_LOWER_THRESH_CX00_31_L2_INTR_REG_START 0x00a4f480
-#define BCHP_XPT_RAVE_CDB_LOWER_THRESH_CX00_31_L2_INTR_REG_END 0x00a4f4ac
-#define BCHP_XPT_RAVE_CDB_LOWER_THRESH_CX32_47_L2_INTR_REG_START 0x00a4f4c0
-#define BCHP_XPT_RAVE_CDB_LOWER_THRESH_CX32_47_L2_INTR_REG_END 0x00a4f4ec
-#define BCHP_XPT_RAVE_CDB_UPPER_THRESH_CX00_31_L2_INTR_REG_START 0x00a4f500
-#define BCHP_XPT_RAVE_CDB_UPPER_THRESH_CX00_31_L2_INTR_REG_END 0x00a4f52c
-#define BCHP_XPT_RAVE_CDB_UPPER_THRESH_CX32_47_L2_INTR_REG_START 0x00a4f540
-#define BCHP_XPT_RAVE_CDB_UPPER_THRESH_CX32_47_L2_INTR_REG_END 0x00a4f56c
-#define BCHP_XPT_RAVE_ITB_LOWER_THRESH_CX00_31_L2_INTR_REG_START 0x00a4f580
-#define BCHP_XPT_RAVE_ITB_LOWER_THRESH_CX00_31_L2_INTR_REG_END 0x00a4f5ac
-#define BCHP_XPT_RAVE_ITB_LOWER_THRESH_CX32_47_L2_INTR_REG_START 0x00a4f5c0
-#define BCHP_XPT_RAVE_ITB_LOWER_THRESH_CX32_47_L2_INTR_REG_END 0x00a4f5ec
-#define BCHP_XPT_RAVE_ITB_UPPER_THRESH_CX00_31_L2_INTR_REG_START 0x00a4f600
-#define BCHP_XPT_RAVE_ITB_UPPER_THRESH_CX00_31_L2_INTR_REG_END 0x00a4f62c
-#define BCHP_XPT_RAVE_ITB_UPPER_THRESH_CX32_47_L2_INTR_REG_START 0x00a4f640
-#define BCHP_XPT_RAVE_ITB_UPPER_THRESH_CX32_47_L2_INTR_REG_END 0x00a4f66c
-#define BCHP_XPT_RAVE_CDB_MIN_DEPTH_THRESH_CX00_31_L2_INTR_REG_START 0x00a4f680
-#define BCHP_XPT_RAVE_CDB_MIN_DEPTH_THRESH_CX00_31_L2_INTR_REG_END 0x00a4f6ac
-#define BCHP_XPT_RAVE_CDB_MIN_DEPTH_THRESH_CX32_47_L2_INTR_REG_START 0x00a4f6c0
-#define BCHP_XPT_RAVE_CDB_MIN_DEPTH_THRESH_CX32_47_L2_INTR_REG_END 0x00a4f6ec
-#define BCHP_XPT_RAVE_ITB_MIN_DEPTH_THRESH_CX00_31_L2_INTR_REG_START 0x00a4f700
-#define BCHP_XPT_RAVE_ITB_MIN_DEPTH_THRESH_CX00_31_L2_INTR_REG_END 0x00a4f72c
-#define BCHP_XPT_RAVE_ITB_MIN_DEPTH_THRESH_CX32_47_L2_INTR_REG_START 0x00a4f740
-#define BCHP_XPT_RAVE_ITB_MIN_DEPTH_THRESH_CX32_47_L2_INTR_REG_END 0x00a4f76c
-#define BCHP_XPT_RAVE_TSIO_DMA_END_CX00_31_L2_INTR_REG_START 0x00a4f780
-#define BCHP_XPT_RAVE_TSIO_DMA_END_CX00_31_L2_INTR_REG_END 0x00a4f7ac
-#define BCHP_XPT_RAVE_TSIO_DMA_END_CX32_47_L2_INTR_REG_START 0x00a4f7c0
-#define BCHP_XPT_RAVE_TSIO_DMA_END_CX32_47_L2_INTR_REG_END 0x00a4f7ec
-#define BCHP_XPT_RAVE_FW_GENERIC_1_CX00_31_L2_INTR_REG_START 0x00a4f800
-#define BCHP_XPT_RAVE_FW_GENERIC_1_CX00_31_L2_INTR_REG_END 0x00a4f82c
-#define BCHP_XPT_RAVE_FW_GENERIC_1_CX32_47_L2_INTR_REG_START 0x00a4f840
-#define BCHP_XPT_RAVE_FW_GENERIC_1_CX32_47_L2_INTR_REG_END 0x00a4f86c
-#define BCHP_XPT_RAVE_TO_SCPU_L2_INTR_0_31_REG_START 0x00a4ff80
-#define BCHP_XPT_RAVE_TO_SCPU_L2_INTR_0_31_REG_END 0x00a4ffac
-#define BCHP_XPT_RAVE_TO_SCPU_L2_INTR_32_47_REG_START 0x00a4ffc0
-#define BCHP_XPT_RAVE_TO_SCPU_L2_INTR_32_47_REG_END 0x00a4ffec
-#define BCHP_XPT_MEMDMA_MCPB_CPU_INTR_AGGREGATOR_REG_START 0x00a60000
-#define BCHP_XPT_MEMDMA_MCPB_CPU_INTR_AGGREGATOR_REG_END 0x00a6001c
-#define BCHP_XPT_MEMDMA_MCPB_PCI_INTR_AGGREGATOR_REG_START 0x00a60020
-#define BCHP_XPT_MEMDMA_MCPB_PCI_INTR_AGGREGATOR_REG_END 0x00a6003c
-#define BCHP_XPT_MEMDMA_MCPB_DESC_DONE_INTR_L2_REG_START 0x00a60040
-#define BCHP_XPT_MEMDMA_MCPB_DESC_DONE_INTR_L2_REG_END 0x00a6006c
-#define BCHP_XPT_MEMDMA_MCPB_MISC_FALSE_WAKE_INTR_L2_REG_START 0x00a60080
-#define BCHP_XPT_MEMDMA_MCPB_MISC_FALSE_WAKE_INTR_L2_REG_END 0x00a600ac
-#define BCHP_XPT_MEMDMA_MCPB_MISC_OOS_INTR_L2_REG_START 0x00a600c0
-#define BCHP_XPT_MEMDMA_MCPB_MISC_OOS_INTR_L2_REG_END 0x00a600ec
-#define BCHP_XPT_MEMDMA_MCPB_MISC_TS_PARITY_ERR_INTR_L2_REG_START 0x00a60100
-#define BCHP_XPT_MEMDMA_MCPB_MISC_TS_PARITY_ERR_INTR_L2_REG_END 0x00a6012c
-#define BCHP_XPT_MEMDMA_MCPB_MISC_TEI_INTR_L2_REG_START 0x00a60140
-#define BCHP_XPT_MEMDMA_MCPB_MISC_TEI_INTR_L2_REG_END 0x00a6016c
-#define BCHP_XPT_MEMDMA_MCPB_MISC_ASF_LEN_ERR_INTR_L2_REG_START 0x00a60180
-#define BCHP_XPT_MEMDMA_MCPB_MISC_ASF_LEN_ERR_INTR_L2_REG_END 0x00a601ac
-#define BCHP_XPT_MEMDMA_MCPB_MISC_WATCHDOG_TIMEOUT_OR_ASF_FATAL_ERR_INTR_L2_REG_START 0x00a601c0
-#define BCHP_XPT_MEMDMA_MCPB_MISC_WATCHDOG_TIMEOUT_OR_ASF_FATAL_ERR_INTR_L2_REG_END 0x00a601ec
-#define BCHP_XPT_MEMDMA_MCPB_MISC_ASF_COMPRESSED_DATA_RECEIVED_INTR_L2_REG_START 0x00a60200
-#define BCHP_XPT_MEMDMA_MCPB_MISC_ASF_COMPRESSED_DATA_RECEIVED_INTR_L2_REG_END 0x00a6022c
-#define BCHP_XPT_MEMDMA_MCPB_MISC_ASF_PROTOCOL_ERR_INTR_L2_REG_START 0x00a60240
-#define BCHP_XPT_MEMDMA_MCPB_MISC_ASF_PROTOCOL_ERR_INTR_L2_REG_END 0x00a6026c
-#define BCHP_XPT_MEMDMA_MCPB_MISC_ASF_PADDING_LEN_ERR_INTR_L2_REG_START 0x00a60280
-#define BCHP_XPT_MEMDMA_MCPB_MISC_ASF_PADDING_LEN_ERR_INTR_L2_REG_END 0x00a602ac
-#define BCHP_XPT_MEMDMA_MCPB_MISC_TS_RANGE_ERR_INTR_L2_REG_START 0x00a602c0
-#define BCHP_XPT_MEMDMA_MCPB_MISC_TS_RANGE_ERR_INTR_L2_REG_END 0x00a602ec
-#define BCHP_XPT_MEMDMA_MCPB_MISC_PES_NEXT_TS_RANGE_ERR_INTR_L2_REG_START 0x00a60300
-#define BCHP_XPT_MEMDMA_MCPB_MISC_PES_NEXT_TS_RANGE_ERR_INTR_L2_REG_END 0x00a6032c
-#define BCHP_XPT_MEMDMA_MCPB_MISC_PAUSE_AT_DESC_READ_INTR_L2_REG_START 0x00a60340
-#define BCHP_XPT_MEMDMA_MCPB_MISC_PAUSE_AT_DESC_READ_INTR_L2_REG_END 0x00a6036c
-#define BCHP_XPT_MEMDMA_MCPB_MISC_PAUSE_AT_DESC_END_INTR_L2_REG_START 0x00a60380
-#define BCHP_XPT_MEMDMA_MCPB_MISC_PAUSE_AT_DESC_END_INTR_L2_REG_END 0x00a603ac
-#define BCHP_XPT_MEMDMA_MCPB_MISC_PAUSE_AFTER_GROUP_PACKETS_INTR_L2_REG_START 0x00a603c0
-#define BCHP_XPT_MEMDMA_MCPB_MISC_PAUSE_AFTER_GROUP_PACKETS_INTR_L2_REG_END 0x00a603ec
-#define BCHP_XPT_MEMDMA_MCPB_MISC_DESC_TAGID_MISMATCH_INTR_L2_REG_START 0x00a60400
-#define BCHP_XPT_MEMDMA_MCPB_MISC_DESC_TAGID_MISMATCH_INTR_L2_REG_END 0x00a6042c
-#define BCHP_XPT_MEMDMA_MCPB_MISC_DATA_TAGID_MISMATCH_INTR_L2_REG_START 0x00a60440
-#define BCHP_XPT_MEMDMA_MCPB_MISC_DATA_TAGID_MISMATCH_INTR_L2_REG_END 0x00a6046c
-#define BCHP_XPT_MEMDMA_MCPB_MISC_CRC_COMPARE_ERROR_INTR_L2_REG_START 0x00a60480
-#define BCHP_XPT_MEMDMA_MCPB_MISC_CRC_COMPARE_ERROR_INTR_L2_REG_END 0x00a604ac
-#define BCHP_XPT_MEMDMA_MCPB_REG_START 0x00a60800
-#define BCHP_XPT_MEMDMA_MCPB_REG_END 0x00a60b98
-#define BCHP_XPT_MEMDMA_MCPB_CH0_REG_START 0x00a60c00
-#define BCHP_XPT_MEMDMA_MCPB_CH0_REG_END 0x00a60d5c
-#define BCHP_XPT_MEMDMA_MCPB_CH1_REG_START 0x00a60e00
-#define BCHP_XPT_MEMDMA_MCPB_CH1_REG_END 0x00a60f5c
-#define BCHP_XPT_MEMDMA_MCPB_CH2_REG_START 0x00a61000
-#define BCHP_XPT_MEMDMA_MCPB_CH2_REG_END 0x00a6115c
-#define BCHP_XPT_MEMDMA_MCPB_CH3_REG_START 0x00a61200
-#define BCHP_XPT_MEMDMA_MCPB_CH3_REG_END 0x00a6135c
-#define BCHP_XPT_MEMDMA_MCPB_CH4_REG_START 0x00a61400
-#define BCHP_XPT_MEMDMA_MCPB_CH4_REG_END 0x00a6155c
-#define BCHP_XPT_MEMDMA_MCPB_CH5_REG_START 0x00a61600
-#define BCHP_XPT_MEMDMA_MCPB_CH5_REG_END 0x00a6175c
-#define BCHP_XPT_MEMDMA_MCPB_CH6_REG_START 0x00a61800
-#define BCHP_XPT_MEMDMA_MCPB_CH6_REG_END 0x00a6195c
-#define BCHP_XPT_MEMDMA_MCPB_CH7_REG_START 0x00a61a00
-#define BCHP_XPT_MEMDMA_MCPB_CH7_REG_END 0x00a61b5c
-#define BCHP_XPT_MEMDMA_MCPB_CH8_REG_START 0x00a61c00
-#define BCHP_XPT_MEMDMA_MCPB_CH8_REG_END 0x00a61d5c
-#define BCHP_XPT_MEMDMA_MCPB_CH9_REG_START 0x00a61e00
-#define BCHP_XPT_MEMDMA_MCPB_CH9_REG_END 0x00a61f5c
-#define BCHP_XPT_MEMDMA_MCPB_CH10_REG_START 0x00a62000
-#define BCHP_XPT_MEMDMA_MCPB_CH10_REG_END 0x00a6215c
-#define BCHP_XPT_MEMDMA_MCPB_CH11_REG_START 0x00a62200
-#define BCHP_XPT_MEMDMA_MCPB_CH11_REG_END 0x00a6235c
-#define BCHP_XPT_MEMDMA_MCPB_CH12_REG_START 0x00a62400
-#define BCHP_XPT_MEMDMA_MCPB_CH12_REG_END 0x00a6255c
-#define BCHP_XPT_MEMDMA_MCPB_CH13_REG_START 0x00a62600
-#define BCHP_XPT_MEMDMA_MCPB_CH13_REG_END 0x00a6275c
-#define BCHP_XPT_MEMDMA_MCPB_CH14_REG_START 0x00a62800
-#define BCHP_XPT_MEMDMA_MCPB_CH14_REG_END 0x00a6295c
-#define BCHP_XPT_MEMDMA_MCPB_CH15_REG_START 0x00a62a00
-#define BCHP_XPT_MEMDMA_MCPB_CH15_REG_END 0x00a62b5c
-#define BCHP_XPT_MEMDMA_MCPB_CH16_REG_START 0x00a62c00
-#define BCHP_XPT_MEMDMA_MCPB_CH16_REG_END 0x00a62d5c
-#define BCHP_XPT_MEMDMA_MCPB_CH17_REG_START 0x00a62e00
-#define BCHP_XPT_MEMDMA_MCPB_CH17_REG_END 0x00a62f5c
-#define BCHP_XPT_MEMDMA_MCPB_CH18_REG_START 0x00a63000
-#define BCHP_XPT_MEMDMA_MCPB_CH18_REG_END 0x00a6315c
-#define BCHP_XPT_MEMDMA_MCPB_CH19_REG_START 0x00a63200
-#define BCHP_XPT_MEMDMA_MCPB_CH19_REG_END 0x00a6335c
-#define BCHP_XPT_MEMDMA_MCPB_CH20_REG_START 0x00a63400
-#define BCHP_XPT_MEMDMA_MCPB_CH20_REG_END 0x00a6355c
-#define BCHP_XPT_MEMDMA_MCPB_CH21_REG_START 0x00a63600
-#define BCHP_XPT_MEMDMA_MCPB_CH21_REG_END 0x00a6375c
-#define BCHP_XPT_MEMDMA_MCPB_CH22_REG_START 0x00a63800
-#define BCHP_XPT_MEMDMA_MCPB_CH22_REG_END 0x00a6395c
-#define BCHP_XPT_MEMDMA_MCPB_CH23_REG_START 0x00a63a00
-#define BCHP_XPT_MEMDMA_MCPB_CH23_REG_END 0x00a63b5c
-#define BCHP_XPT_MEMDMA_MCPB_CH24_REG_START 0x00a63c00
-#define BCHP_XPT_MEMDMA_MCPB_CH24_REG_END 0x00a63d5c
-#define BCHP_XPT_MEMDMA_MCPB_CH25_REG_START 0x00a63e00
-#define BCHP_XPT_MEMDMA_MCPB_CH25_REG_END 0x00a63f5c
-#define BCHP_XPT_MEMDMA_MCPB_CH26_REG_START 0x00a64000
-#define BCHP_XPT_MEMDMA_MCPB_CH26_REG_END 0x00a6415c
-#define BCHP_XPT_MEMDMA_MCPB_CH27_REG_START 0x00a64200
-#define BCHP_XPT_MEMDMA_MCPB_CH27_REG_END 0x00a6435c
-#define BCHP_XPT_MEMDMA_MCPB_CH28_REG_START 0x00a64400
-#define BCHP_XPT_MEMDMA_MCPB_CH28_REG_END 0x00a6455c
-#define BCHP_XPT_MEMDMA_MCPB_CH29_REG_START 0x00a64600
-#define BCHP_XPT_MEMDMA_MCPB_CH29_REG_END 0x00a6475c
-#define BCHP_XPT_MEMDMA_MCPB_CH30_REG_START 0x00a64800
-#define BCHP_XPT_MEMDMA_MCPB_CH30_REG_END 0x00a6495c
-#define BCHP_XPT_MEMDMA_MCPB_CH31_REG_START 0x00a64a00
-#define BCHP_XPT_MEMDMA_MCPB_CH31_REG_END 0x00a64b5c
-#define BCHP_XPT_WDMA_PCI_INTR_AGGREGATOR_REG_START 0x00a68000
-#define BCHP_XPT_WDMA_PCI_INTR_AGGREGATOR_REG_END 0x00a6801c
-#define BCHP_XPT_WDMA_CPU_INTR_AGGREGATOR_REG_START 0x00a68020
-#define BCHP_XPT_WDMA_CPU_INTR_AGGREGATOR_REG_END 0x00a6803c
-#define BCHP_XPT_WDMA_SCPU_INTR_AGGREGATOR_REG_START 0x00a68040
-#define BCHP_XPT_WDMA_SCPU_INTR_AGGREGATOR_REG_END 0x00a6805c
-#define BCHP_XPT_WDMA_BTP_INTR_L2_REG_START 0x00a68100
-#define BCHP_XPT_WDMA_BTP_INTR_L2_REG_END 0x00a68144
-#define BCHP_XPT_WDMA_OVERFLOW_INTR_L2_REG_START 0x00a68200
-#define BCHP_XPT_WDMA_OVERFLOW_INTR_L2_REG_END 0x00a68244
-#define BCHP_XPT_WDMA_DESC_DONE_INTR_L2_REG_START 0x00a68300
-#define BCHP_XPT_WDMA_DESC_DONE_INTR_L2_REG_END 0x00a68344
-#define BCHP_XPT_WDMA_PM_INTR_L2_REG_START 0x00a68400
-#define BCHP_XPT_WDMA_PM_INTR_L2_REG_END 0x00a68444
-#define BCHP_XPT_WDMA_PM_CONTROL_REG_START 0x00a68500
-#define BCHP_XPT_WDMA_PM_CONTROL_REG_END 0x00a68510
-#define BCHP_XPT_WDMA_PM_RESULTS_REG_START 0x00a68600
-#define BCHP_XPT_WDMA_PM_RESULTS_REG_END 0x00a68658
-#define BCHP_XPT_WDMA_REGS_REG_START 0x00a69000
-#define BCHP_XPT_WDMA_REGS_REG_END 0x00a69068
-#define BCHP_XPT_WDMA_RAMS_REG_START 0x00a6a000
-#define BCHP_XPT_WDMA_RAMS_REG_END 0x00a6bffc
-#define BCHP_XPT_MEMDMA_XMEMIF_REG_START 0x00a6ff00
-#define BCHP_XPT_MEMDMA_XMEMIF_REG_END 0x00a6fffc
-#define BCHP_XPT_MCPB_CPU_INTR_AGGREGATOR_REG_START 0x00a70000
-#define BCHP_XPT_MCPB_CPU_INTR_AGGREGATOR_REG_END 0x00a7001c
-#define BCHP_XPT_MCPB_PCI_INTR_AGGREGATOR_REG_START 0x00a70020
-#define BCHP_XPT_MCPB_PCI_INTR_AGGREGATOR_REG_END 0x00a7003c
-#define BCHP_XPT_MCPB_DESC_DONE_INTR_L2_REG_START 0x00a70040
-#define BCHP_XPT_MCPB_DESC_DONE_INTR_L2_REG_END 0x00a7006c
-#define BCHP_XPT_MCPB_MISC_FALSE_WAKE_INTR_L2_REG_START 0x00a70080
-#define BCHP_XPT_MCPB_MISC_FALSE_WAKE_INTR_L2_REG_END 0x00a700ac
-#define BCHP_XPT_MCPB_MISC_OOS_INTR_L2_REG_START 0x00a700c0
-#define BCHP_XPT_MCPB_MISC_OOS_INTR_L2_REG_END 0x00a700ec
-#define BCHP_XPT_MCPB_MISC_TS_PARITY_ERR_INTR_L2_REG_START 0x00a70100
-#define BCHP_XPT_MCPB_MISC_TS_PARITY_ERR_INTR_L2_REG_END 0x00a7012c
-#define BCHP_XPT_MCPB_MISC_TEI_INTR_L2_REG_START 0x00a70140
-#define BCHP_XPT_MCPB_MISC_TEI_INTR_L2_REG_END 0x00a7016c
-#define BCHP_XPT_MCPB_MISC_ASF_LEN_ERR_INTR_L2_REG_START 0x00a70180
-#define BCHP_XPT_MCPB_MISC_ASF_LEN_ERR_INTR_L2_REG_END 0x00a701ac
-#define BCHP_XPT_MCPB_MISC_WATCHDOG_TIMEOUT_OR_ASF_FATAL_ERR_INTR_L2_REG_START 0x00a701c0
-#define BCHP_XPT_MCPB_MISC_WATCHDOG_TIMEOUT_OR_ASF_FATAL_ERR_INTR_L2_REG_END 0x00a701ec
-#define BCHP_XPT_MCPB_MISC_ASF_COMPRESSED_DATA_RECEIVED_INTR_L2_REG_START 0x00a70200
-#define BCHP_XPT_MCPB_MISC_ASF_COMPRESSED_DATA_RECEIVED_INTR_L2_REG_END 0x00a7022c
-#define BCHP_XPT_MCPB_MISC_ASF_PROTOCOL_ERR_INTR_L2_REG_START 0x00a70240
-#define BCHP_XPT_MCPB_MISC_ASF_PROTOCOL_ERR_INTR_L2_REG_END 0x00a7026c
-#define BCHP_XPT_MCPB_MISC_ASF_PADDING_LEN_ERR_INTR_L2_REG_START 0x00a70280
-#define BCHP_XPT_MCPB_MISC_ASF_PADDING_LEN_ERR_INTR_L2_REG_END 0x00a702ac
-#define BCHP_XPT_MCPB_MISC_TS_RANGE_ERR_INTR_L2_REG_START 0x00a702c0
-#define BCHP_XPT_MCPB_MISC_TS_RANGE_ERR_INTR_L2_REG_END 0x00a702ec
-#define BCHP_XPT_MCPB_MISC_PES_NEXT_TS_RANGE_ERR_INTR_L2_REG_START 0x00a70300
-#define BCHP_XPT_MCPB_MISC_PES_NEXT_TS_RANGE_ERR_INTR_L2_REG_END 0x00a7032c
-#define BCHP_XPT_MCPB_MISC_PAUSE_AT_DESC_READ_INTR_L2_REG_START 0x00a70340
-#define BCHP_XPT_MCPB_MISC_PAUSE_AT_DESC_READ_INTR_L2_REG_END 0x00a7036c
-#define BCHP_XPT_MCPB_MISC_PAUSE_AT_DESC_END_INTR_L2_REG_START 0x00a70380
-#define BCHP_XPT_MCPB_MISC_PAUSE_AT_DESC_END_INTR_L2_REG_END 0x00a703ac
-#define BCHP_XPT_MCPB_MISC_PAUSE_AFTER_GROUP_PACKETS_INTR_L2_REG_START 0x00a703c0
-#define BCHP_XPT_MCPB_MISC_PAUSE_AFTER_GROUP_PACKETS_INTR_L2_REG_END 0x00a703ec
-#define BCHP_XPT_MCPB_MISC_DESC_TAGID_MISMATCH_INTR_L2_REG_START 0x00a70400
-#define BCHP_XPT_MCPB_MISC_DESC_TAGID_MISMATCH_INTR_L2_REG_END 0x00a7042c
-#define BCHP_XPT_MCPB_MISC_DATA_TAGID_MISMATCH_INTR_L2_REG_START 0x00a70440
-#define BCHP_XPT_MCPB_MISC_DATA_TAGID_MISMATCH_INTR_L2_REG_END 0x00a7046c
-#define BCHP_XPT_MCPB_MISC_CRC_COMPARE_ERROR_INTR_L2_REG_START 0x00a70480
-#define BCHP_XPT_MCPB_MISC_CRC_COMPARE_ERROR_INTR_L2_REG_END 0x00a704ac
-#define BCHP_XPT_MCPB_REG_START 0x00a70800
-#define BCHP_XPT_MCPB_REG_END 0x00a70b98
-#define BCHP_XPT_MCPB_CH0_REG_START 0x00a70c00
-#define BCHP_XPT_MCPB_CH0_REG_END 0x00a70d5c
-#define BCHP_XPT_MCPB_CH1_REG_START 0x00a70e00
-#define BCHP_XPT_MCPB_CH1_REG_END 0x00a70f5c
-#define BCHP_XPT_MCPB_CH2_REG_START 0x00a71000
-#define BCHP_XPT_MCPB_CH2_REG_END 0x00a7115c
-#define BCHP_XPT_MCPB_CH3_REG_START 0x00a71200
-#define BCHP_XPT_MCPB_CH3_REG_END 0x00a7135c
-#define BCHP_XPT_MCPB_CH4_REG_START 0x00a71400
-#define BCHP_XPT_MCPB_CH4_REG_END 0x00a7155c
-#define BCHP_XPT_MCPB_CH5_REG_START 0x00a71600
-#define BCHP_XPT_MCPB_CH5_REG_END 0x00a7175c
-#define BCHP_XPT_MCPB_CH6_REG_START 0x00a71800
-#define BCHP_XPT_MCPB_CH6_REG_END 0x00a7195c
-#define BCHP_XPT_MCPB_CH7_REG_START 0x00a71a00
-#define BCHP_XPT_MCPB_CH7_REG_END 0x00a71b5c
-#define BCHP_XPT_MCPB_CH8_REG_START 0x00a71c00
-#define BCHP_XPT_MCPB_CH8_REG_END 0x00a71d5c
-#define BCHP_XPT_MCPB_CH9_REG_START 0x00a71e00
-#define BCHP_XPT_MCPB_CH9_REG_END 0x00a71f5c
-#define BCHP_XPT_MCPB_CH10_REG_START 0x00a72000
-#define BCHP_XPT_MCPB_CH10_REG_END 0x00a7215c
-#define BCHP_XPT_MCPB_CH11_REG_START 0x00a72200
-#define BCHP_XPT_MCPB_CH11_REG_END 0x00a7235c
-#define BCHP_XPT_MCPB_CH12_REG_START 0x00a72400
-#define BCHP_XPT_MCPB_CH12_REG_END 0x00a7255c
-#define BCHP_XPT_MCPB_CH13_REG_START 0x00a72600
-#define BCHP_XPT_MCPB_CH13_REG_END 0x00a7275c
-#define BCHP_XPT_MCPB_CH14_REG_START 0x00a72800
-#define BCHP_XPT_MCPB_CH14_REG_END 0x00a7295c
-#define BCHP_XPT_MCPB_CH15_REG_START 0x00a72a00
-#define BCHP_XPT_MCPB_CH15_REG_END 0x00a72b5c
-#define BCHP_XPT_MCPB_CH16_REG_START 0x00a72c00
-#define BCHP_XPT_MCPB_CH16_REG_END 0x00a72d5c
-#define BCHP_XPT_MCPB_CH17_REG_START 0x00a72e00
-#define BCHP_XPT_MCPB_CH17_REG_END 0x00a72f5c
-#define BCHP_XPT_MCPB_CH18_REG_START 0x00a73000
-#define BCHP_XPT_MCPB_CH18_REG_END 0x00a7315c
-#define BCHP_XPT_MCPB_CH19_REG_START 0x00a73200
-#define BCHP_XPT_MCPB_CH19_REG_END 0x00a7335c
-#define BCHP_XPT_MCPB_CH20_REG_START 0x00a73400
-#define BCHP_XPT_MCPB_CH20_REG_END 0x00a7355c
-#define BCHP_XPT_MCPB_CH21_REG_START 0x00a73600
-#define BCHP_XPT_MCPB_CH21_REG_END 0x00a7375c
-#define BCHP_XPT_MCPB_CH22_REG_START 0x00a73800
-#define BCHP_XPT_MCPB_CH22_REG_END 0x00a7395c
-#define BCHP_XPT_MCPB_CH23_REG_START 0x00a73a00
-#define BCHP_XPT_MCPB_CH23_REG_END 0x00a73b5c
-#define BCHP_XPT_MCPB_CH24_REG_START 0x00a73c00
-#define BCHP_XPT_MCPB_CH24_REG_END 0x00a73d5c
-#define BCHP_XPT_MCPB_CH25_REG_START 0x00a73e00
-#define BCHP_XPT_MCPB_CH25_REG_END 0x00a73f5c
-#define BCHP_XPT_MCPB_CH26_REG_START 0x00a74000
-#define BCHP_XPT_MCPB_CH26_REG_END 0x00a7415c
-#define BCHP_XPT_MCPB_CH27_REG_START 0x00a74200
-#define BCHP_XPT_MCPB_CH27_REG_END 0x00a7435c
-#define BCHP_XPT_MCPB_CH28_REG_START 0x00a74400
-#define BCHP_XPT_MCPB_CH28_REG_END 0x00a7455c
-#define BCHP_XPT_MCPB_CH29_REG_START 0x00a74600
-#define BCHP_XPT_MCPB_CH29_REG_END 0x00a7475c
-#define BCHP_XPT_MCPB_CH30_REG_START 0x00a74800
-#define BCHP_XPT_MCPB_CH30_REG_END 0x00a7495c
-#define BCHP_XPT_MCPB_CH31_REG_START 0x00a74a00
-#define BCHP_XPT_MCPB_CH31_REG_END 0x00a74b5c
-#define BCHP_XPT_XPU_REG_START 0x00a78000
-#define BCHP_XPT_XPU_REG_END 0x00a7c7fc
-#define BCHP_XPT_SECURE_BUS_IF_REG_START 0x00a7f000
-#define BCHP_XPT_SECURE_BUS_IF_REG_END 0x00a7f000
-#define BCHP_GENET_0_SYS_REG_START 0x00b60000
-#define BCHP_GENET_0_SYS_REG_END 0x00b60010
-#define BCHP_GENET_0_GR_BRIDGE_REG_START 0x00b60040
-#define BCHP_GENET_0_GR_BRIDGE_REG_END 0x00b6004c
-#define BCHP_GENET_0_EXT_REG_START 0x00b60080
-#define BCHP_GENET_0_EXT_REG_END 0x00b600b4
-#define BCHP_GENET_0_INTRL2_0_REG_START 0x00b60200
-#define BCHP_GENET_0_INTRL2_0_REG_END 0x00b6022c
-#define BCHP_GENET_0_INTRL2_1_REG_START 0x00b60240
-#define BCHP_GENET_0_INTRL2_1_REG_END 0x00b6026c
-#define BCHP_GENET_0_RBUF_REG_START 0x00b60300
-#define BCHP_GENET_0_RBUF_REG_END 0x00b603b4
-#define BCHP_GENET_0_TBUF_REG_START 0x00b60600
-#define BCHP_GENET_0_TBUF_REG_END 0x00b60628
-#define BCHP_GENET_0_UMAC_REG_START 0x00b60800
-#define BCHP_GENET_0_UMAC_REG_END 0x00b60ed8
-#define BCHP_GENET_0_RDMA_REG_START 0x00b62000
-#define BCHP_GENET_0_RDMA_REG_END 0x00b630d4
-#define BCHP_GENET_0_TDMA_REG_START 0x00b64000
-#define BCHP_GENET_0_TDMA_REG_END 0x00b65084
-#define BCHP_GENET_0_HFB_REG_START 0x00b68000
-#define BCHP_GENET_0_HFB_REG_END 0x00b6fc48
-#define BCHP_GENET_1_SYS_REG_START 0x00b80000
-#define BCHP_GENET_1_SYS_REG_END 0x00b80010
-#define BCHP_GENET_1_GR_BRIDGE_REG_START 0x00b80040
-#define BCHP_GENET_1_GR_BRIDGE_REG_END 0x00b8004c
-#define BCHP_GENET_1_EXT_REG_START 0x00b80080
-#define BCHP_GENET_1_EXT_REG_END 0x00b800b4
-#define BCHP_GENET_1_INTRL2_0_REG_START 0x00b80200
-#define BCHP_GENET_1_INTRL2_0_REG_END 0x00b8022c
-#define BCHP_GENET_1_INTRL2_1_REG_START 0x00b80240
-#define BCHP_GENET_1_INTRL2_1_REG_END 0x00b8026c
-#define BCHP_GENET_1_RBUF_REG_START 0x00b80300
-#define BCHP_GENET_1_RBUF_REG_END 0x00b803b4
-#define BCHP_GENET_1_TBUF_REG_START 0x00b80600
-#define BCHP_GENET_1_TBUF_REG_END 0x00b80628
-#define BCHP_GENET_1_UMAC_REG_START 0x00b80800
-#define BCHP_GENET_1_UMAC_REG_END 0x00b80ed8
-#define BCHP_GENET_1_RDMA_REG_START 0x00b82000
-#define BCHP_GENET_1_RDMA_REG_END 0x00b830d4
-#define BCHP_GENET_1_TDMA_REG_START 0x00b84000
-#define BCHP_GENET_1_TDMA_REG_END 0x00b85084
-#define BCHP_GENET_1_HFB_REG_START 0x00b88000
-#define BCHP_GENET_1_HFB_REG_END 0x00b8fc48
-#define BCHP_GENET_2_SYS_REG_START 0x00ba0000
-#define BCHP_GENET_2_SYS_REG_END 0x00ba0010
-#define BCHP_GENET_2_GR_BRIDGE_REG_START 0x00ba0040
-#define BCHP_GENET_2_GR_BRIDGE_REG_END 0x00ba004c
-#define BCHP_GENET_2_EXT_REG_START 0x00ba0080
-#define BCHP_GENET_2_EXT_REG_END 0x00ba00b4
-#define BCHP_GENET_2_INTRL2_0_REG_START 0x00ba0200
-#define BCHP_GENET_2_INTRL2_0_REG_END 0x00ba022c
-#define BCHP_GENET_2_INTRL2_1_REG_START 0x00ba0240
-#define BCHP_GENET_2_INTRL2_1_REG_END 0x00ba026c
-#define BCHP_GENET_2_RBUF_REG_START 0x00ba0300
-#define BCHP_GENET_2_RBUF_REG_END 0x00ba03b4
-#define BCHP_GENET_2_TBUF_REG_START 0x00ba0600
-#define BCHP_GENET_2_TBUF_REG_END 0x00ba0628
-#define BCHP_GENET_2_UMAC_REG_START 0x00ba0800
-#define BCHP_GENET_2_UMAC_REG_END 0x00ba0ed8
-#define BCHP_GENET_2_RDMA_REG_START 0x00ba2000
-#define BCHP_GENET_2_RDMA_REG_END 0x00ba30d4
-#define BCHP_GENET_2_TDMA_REG_START 0x00ba4000
-#define BCHP_GENET_2_TDMA_REG_END 0x00ba5084
-#define BCHP_GENET_2_HFB_REG_START 0x00ba8000
-#define BCHP_GENET_2_HFB_REG_END 0x00bafc48
-#define BCHP_SID_REG_START 0x00bc0100
-#define BCHP_SID_REG_END 0x00bc019c
-#define BCHP_SID_RLE_REG_START 0x00bc0300
-#define BCHP_SID_RLE_REG_END 0x00bc039c
-#define BCHP_SID_DQ_REG_START 0x00bc0400
-#define BCHP_SID_DQ_REG_END 0x00bc04bc
-#define BCHP_SID_STRM_REG_START 0x00bc0800
-#define BCHP_SID_STRM_REG_END 0x00bc087c
-#define BCHP_SID_OUTPUT_REG_START 0x00bc0c00
-#define BCHP_SID_OUTPUT_REG_END 0x00bc0c40
-#define BCHP_SID_ARC_REG_START 0x00bc0f00
-#define BCHP_SID_ARC_REG_END 0x00bc0f3c
-#define BCHP_SID_ARCDMA_REG_START 0x00bc1800
-#define BCHP_SID_ARCDMA_REG_END 0x00bc1840
-#define BCHP_SID_DMARAM_REG_START 0x00bc1a00
-#define BCHP_SID_DMARAM_REG_END 0x00bc1bfc
-#define BCHP_SID_PEEK_BITS_REG_START 0x00bc2b00
-#define BCHP_SID_PEEK_BITS_REG_END 0x00bc2b3c
-#define BCHP_SID_EXTRACT_BITS_REG_START 0x00bc2b40
-#define BCHP_SID_EXTRACT_BITS_REG_END 0x00bc2b7c
-#define BCHP_SID_HUFF_SYMB_REG_START 0x00bc3000
-#define BCHP_SID_HUFF_SYMB_REG_END 0x00bc37fc
-#define BCHP_SID_HUFF_CODE_REG_START 0x00bc3900
-#define BCHP_SID_HUFF_CODE_REG_END 0x00bc39fc
-#define BCHP_SID_SYMB_REG_START 0x00bc3a00
-#define BCHP_SID_SYMB_REG_END 0x00bc3a10
-#define BCHP_SID_SYMB_JPEG_REG_START 0x00bc3a80
-#define BCHP_SID_SYMB_JPEG_REG_END 0x00bc3a8c
-#define BCHP_SID_BIGRAM_REG_START 0x00bc8000
-#define BCHP_SID_BIGRAM_REG_END 0x00bcfffc
-#define BCHP_SID_ARC_DBG_REG_START 0x00bd1000
-#define BCHP_SID_ARC_DBG_REG_END 0x00bd1010
-#define BCHP_SID_ARC_CORE_REG_START 0x00bd5000
-#define BCHP_SID_ARC_CORE_REG_END 0x00bd5014
-#define BCHP_SID_GR_REG_START 0x00be0000
-#define BCHP_SID_GR_REG_END 0x00be000c
-#define BCHP_SID_L2_REG_START 0x00be0100
-#define BCHP_SID_L2_REG_END 0x00be012c
-#define BCHP_SICH_REG_START 0x00be2000
-#define BCHP_SICH_REG_END 0x00be203c
-#define BCHP_M2MC_REG_START 0x00be4000
-#define BCHP_M2MC_REG_END 0x00be47fc
-#define BCHP_M2MC_L2_REG_START 0x00be5000
-#define BCHP_M2MC_L2_REG_END 0x00be502c
-#define BCHP_M2MC_GR_REG_START 0x00be5800
-#define BCHP_M2MC_GR_REG_END 0x00be580c
-#define BCHP_M2MC1_REG_START 0x00be6000
-#define BCHP_M2MC1_REG_END 0x00be67fc
-#define BCHP_M2MC1_L2_REG_START 0x00be7000
-#define BCHP_M2MC1_L2_REG_END 0x00be702c
-#define BCHP_M2MC1_GR_REG_START 0x00be7800
-#define BCHP_M2MC1_GR_REG_END 0x00be780c
-#define BCHP_V3D_CTL_REG_START 0x00bea000
-#define BCHP_V3D_CTL_REG_END 0x00bea040
-#define BCHP_V3D_CLE_REG_START 0x00bea100
-#define BCHP_V3D_CLE_REG_END 0x00bea138
-#define BCHP_V3D_PTB_REG_START 0x00bea300
-#define BCHP_V3D_PTB_REG_END 0x00bea310
-#define BCHP_V3D_QPS_REG_START 0x00bea400
-#define BCHP_V3D_QPS_REG_END 0x00bea43c
-#define BCHP_V3D_VPM_REG_START 0x00bea500
-#define BCHP_V3D_VPM_REG_END 0x00bea504
-#define BCHP_V3D_PCTR_REG_START 0x00bea600
-#define BCHP_V3D_PCTR_REG_END 0x00bea6fc
-#define BCHP_V3D_TOP_GR_BRIDGE_REG_START 0x00bea800
-#define BCHP_V3D_TOP_GR_BRIDGE_REG_END 0x00bea80c
-#define BCHP_V3D_GCA_REG_START 0x00beaa00
-#define BCHP_V3D_GCA_REG_END 0x00beaa64
-#define BCHP_V3D_DBG_REG_START 0x00beae00
-#define BCHP_V3D_DBG_REG_END 0x00beaf20
-#define BCHP_RAAGA_DSP_SEC0_REG_START 0x00bf0000
-#define BCHP_RAAGA_DSP_SEC0_REG_END 0x00bf0000
-#define BCHP_RAAGA_DSP_RGR_REG_START 0x00c00000
-#define BCHP_RAAGA_DSP_RGR_REG_END 0x00c00008
-#define BCHP_RAAGA_DSP_MISC_REG_START 0x00c20000
-#define BCHP_RAAGA_DSP_MISC_REG_END 0x00c2044c
-#define BCHP_RAAGA_DSP_TIMERS_REG_START 0x00c21000
-#define BCHP_RAAGA_DSP_TIMERS_REG_END 0x00c21058
-#define BCHP_RAAGA_DSP_PERI_DBG_CTRL_REG_START 0x00c21080
-#define BCHP_RAAGA_DSP_PERI_DBG_CTRL_REG_END 0x00c2109c
-#define BCHP_RAAGA_DSP_PERI_SW_REG_START 0x00c21100
-#define BCHP_RAAGA_DSP_PERI_SW_REG_END 0x00c21154
-#define BCHP_RAAGA_DSP_DMA_REG_START 0x00c21400
-#define BCHP_RAAGA_DSP_DMA_REG_END 0x00c21664
-#define BCHP_RAAGA_DSP_ESR_SI_REG_START 0x00c22000
-#define BCHP_RAAGA_DSP_ESR_SI_REG_END 0x00c22014
-#define BCHP_RAAGA_DSP_INTH_REG_START 0x00c22200
-#define BCHP_RAAGA_DSP_INTH_REG_END 0x00c2222c
-#define BCHP_RAAGA_DSP_FW_INTH_REG_START 0x00c22400
-#define BCHP_RAAGA_DSP_FW_INTH_REG_END 0x00c2242c
-#define BCHP_RAAGA_DSP_FW_CFG_REG_START 0x00c23000
-#define BCHP_RAAGA_DSP_FW_CFG_REG_END 0x00c2357c
-#define BCHP_RAAGA_DSP_MEM_SUBSYSTEM_REG_START 0x00c30000
-#define BCHP_RAAGA_DSP_MEM_SUBSYSTEM_REG_END 0x00c3bffc
-#define BCHP_AUD_MISC_REG_START 0x00c80000
-#define BCHP_AUD_MISC_REG_END 0x00c80120
-#define BCHP_AUD_INTH_REG_START 0x00c80800
-#define BCHP_AUD_INTH_REG_END 0x00c8082c
-#define BCHP_AUD_FMM_BF_CTRL_REG_START 0x00ca0000
-#define BCHP_AUD_FMM_BF_CTRL_REG_END 0x00ca0d3c
-#define BCHP_AUD_FMM_BF_ESR_REG_START 0x00ca1000
-#define BCHP_AUD_FMM_BF_ESR_REG_END 0x00ca1074
-#define BCHP_AUD_FMM_SRC_CTRL0_REG_START 0x00ca2000
-#define BCHP_AUD_FMM_SRC_CTRL0_REG_END 0x00ca2bfc
-#define BCHP_AUD_FMM_SRC_ESR0_REG_START 0x00ca3000
-#define BCHP_AUD_FMM_SRC_ESR0_REG_END 0x00ca3014
-#define BCHP_AUD_FMM_DP_CTRL0_REG_START 0x00ca4000
-#define BCHP_AUD_FMM_DP_CTRL0_REG_END 0x00ca612c
-#define BCHP_AUD_FMM_DP_ESR0_REG_START 0x00ca7c00
-#define BCHP_AUD_FMM_DP_ESR0_REG_END 0x00ca7c2c
-#define BCHP_AUD_FMM_IOP_OUT_I2S_STEREO_0_REG_START 0x00cb0000
-#define BCHP_AUD_FMM_IOP_OUT_I2S_STEREO_0_REG_END 0x00cb0084
-#define BCHP_AUD_FMM_IOP_OUT_SPDIF_0_REG_START 0x00cb0100
-#define BCHP_AUD_FMM_IOP_OUT_SPDIF_0_REG_END 0x00cb0184
-#define BCHP_AUD_FMM_IOP_OUT_MAI_0_REG_START 0x00cb0200
-#define BCHP_AUD_FMM_IOP_OUT_MAI_0_REG_END 0x00cb02b4
-#define BCHP_AUD_FMM_IOP_OUT_MAI_1_REG_START 0x00cb0300
-#define BCHP_AUD_FMM_IOP_OUT_MAI_1_REG_END 0x00cb03b4
-#define BCHP_HIFIDAC_CTRL_0_REG_START 0x00cb0800
-#define BCHP_HIFIDAC_CTRL_0_REG_END 0x00cb09fc
-#define BCHP_HIFIDAC_RM_0_REG_START 0x00cb0a00
-#define BCHP_HIFIDAC_RM_0_REG_END 0x00cb0a30
-#define BCHP_HIFIDAC_ESR_0_REG_START 0x00cb0b00
-#define BCHP_HIFIDAC_ESR_0_REG_END 0x00cb0b14
-#define BCHP_AUD_FMM_IOP_OUT_DAC_CTRL_0_REG_START 0x00cb0c00
-#define BCHP_AUD_FMM_IOP_OUT_DAC_CTRL_0_REG_END 0x00cb0c98
-#define BCHP_AUD_FMM_IOP_PLL_0_REG_START 0x00cb0d00
-#define BCHP_AUD_FMM_IOP_PLL_0_REG_END 0x00cb0d88
-#define BCHP_AUD_FMM_IOP_PLL_1_REG_START 0x00cb0e00
-#define BCHP_AUD_FMM_IOP_PLL_1_REG_END 0x00cb0e88
-#define BCHP_AUD_FMM_IOP_NCO_0_REG_START 0x00cb0f00
-#define BCHP_AUD_FMM_IOP_NCO_0_REG_END 0x00cb0f30
-#define BCHP_AUD_FMM_IOP_NCO_1_REG_START 0x00cb1000
-#define BCHP_AUD_FMM_IOP_NCO_1_REG_END 0x00cb1030
-#define BCHP_AUD_FMM_IOP_NCO_2_REG_START 0x00cb1100
-#define BCHP_AUD_FMM_IOP_NCO_2_REG_END 0x00cb1130
-#define BCHP_AUD_FMM_IOP_NCO_3_REG_START 0x00cb1200
-#define BCHP_AUD_FMM_IOP_NCO_3_REG_END 0x00cb1230
-#define BCHP_AUD_FMM_IOP_NCO_4_REG_START 0x00cb1300
-#define BCHP_AUD_FMM_IOP_NCO_4_REG_END 0x00cb1330
-#define BCHP_AUD_FMM_IOP_LOOPBACK_0_REG_START 0x00cb1400
-#define BCHP_AUD_FMM_IOP_LOOPBACK_0_REG_END 0x00cb1524
-#define BCHP_AUD_FMM_IOP_DUMMYSINK_0_REG_START 0x00cb1600
-#define BCHP_AUD_FMM_IOP_DUMMYSINK_0_REG_END 0x00cb165c
-#define BCHP_AUD_FMM_IOP_IN_SPDIF_0_REG_START 0x00cb1800
-#define BCHP_AUD_FMM_IOP_IN_SPDIF_0_REG_END 0x00cb18fc
-#define BCHP_AUD_FMM_IOP_IN_HDMI_0_REG_START 0x00cb2000
-#define BCHP_AUD_FMM_IOP_IN_HDMI_0_REG_END 0x00cb20ac
-#define BCHP_AUD_FMM_IOP_IN_I2S_STEREO_0_REG_START 0x00cb2800
-#define BCHP_AUD_FMM_IOP_IN_I2S_STEREO_0_REG_END 0x00cb2864
-#define BCHP_AUD_FMM_IOP_ATTG_0_REG_START 0x00cb2900
-#define BCHP_AUD_FMM_IOP_ATTG_0_REG_END 0x00cb2964
-#define BCHP_AUD_FMM_IOP_OUT_MS_STRM_CFG_0_REG_START 0x00cb4000
-#define BCHP_AUD_FMM_IOP_OUT_MS_STRM_CFG_0_REG_END 0x00cb41fc
-#define BCHP_AUD_FMM_IOP_OUT_MS_STRM_ESR_0_REG_START 0x00cb4400
-#define BCHP_AUD_FMM_IOP_OUT_MS_STRM_ESR_0_REG_END 0x00cb4414
-#define BCHP_AUD_FMM_IOP_OUT_MS_CTRL_0_REG_START 0x00cb6000
-#define BCHP_AUD_FMM_IOP_OUT_MS_CTRL_0_REG_END 0x00cb7bfc
-#define BCHP_AUD_FMM_IOP_OUT_MS_ESR_0_REG_START 0x00cb7d00
-#define BCHP_AUD_FMM_IOP_OUT_MS_ESR_0_REG_END 0x00cb7d14
-#define BCHP_AUD_FMM_IOP_OUT_MS_STRM_CFG_1_REG_START 0x00cb8000
-#define BCHP_AUD_FMM_IOP_OUT_MS_STRM_CFG_1_REG_END 0x00cb81fc
-#define BCHP_AUD_FMM_IOP_OUT_MS_STRM_ESR_1_REG_START 0x00cb8400
-#define BCHP_AUD_FMM_IOP_OUT_MS_STRM_ESR_1_REG_END 0x00cb8414
-#define BCHP_AUD_FMM_IOP_OUT_MS_CTRL_1_REG_START 0x00cba000
-#define BCHP_AUD_FMM_IOP_OUT_MS_CTRL_1_REG_END 0x00cbbbfc
-#define BCHP_AUD_FMM_IOP_OUT_MS_ESR_1_REG_START 0x00cbbd00
-#define BCHP_AUD_FMM_IOP_OUT_MS_ESR_1_REG_END 0x00cbbd14
-#define BCHP_AUD_FMM_IOP_MISC_REG_START 0x00cbc100
-#define BCHP_AUD_FMM_IOP_MISC_REG_END 0x00cbc154
-#define BCHP_DATA_MEM_REG_START 0x00e00000
-#define BCHP_DATA_MEM_REG_END 0x00e47ffc
-#define BCHP_CNTL_MEM_REG_START 0x00f20000
-#define BCHP_CNTL_MEM_REG_END 0x00f67ffc
-#define BCHP_DMA_AHB_ECL_CMD_SCH0_REG_START 0x00fc0000
-#define BCHP_DMA_AHB_ECL_CMD_SCH0_REG_END 0x00fc0000
-#define BCHP_DMA_AHB_ECL_CMD_SCH1_REG_START 0x00fc0010
-#define BCHP_DMA_AHB_ECL_CMD_SCH1_REG_END 0x00fc0010
-#define BCHP_DMA_AHB_ECL_CMD_SCH2_REG_START 0x00fc0020
-#define BCHP_DMA_AHB_ECL_CMD_SCH2_REG_END 0x00fc0020
-#define BCHP_DMA_AHB_ECL_CMD_SCH3_REG_START 0x00fc0030
-#define BCHP_DMA_AHB_ECL_CMD_SCH3_REG_END 0x00fc0030
-#define BCHP_DMA_AHB_ECL_CMD_SCH4_REG_START 0x00fc0040
-#define BCHP_DMA_AHB_ECL_CMD_SCH4_REG_END 0x00fc0040
-#define BCHP_DMA_AHB_ECL_CMD_SCH5_REG_START 0x00fc0050
-#define BCHP_DMA_AHB_ECL_CMD_SCH5_REG_END 0x00fc0050
-#define BCHP_DMA_AHB_ECL_CMD_SCH6_REG_START 0x00fc0060
-#define BCHP_DMA_AHB_ECL_CMD_SCH6_REG_END 0x00fc0060
-#define BCHP_DMA_AHB_ECL_CMD_SCH7_REG_START 0x00fc0070
-#define BCHP_DMA_AHB_ECL_CMD_SCH7_REG_END 0x00fc0070
-#define BCHP_DMA_AHB_ECL_CMD_SCH8_REG_START 0x00fc0080
-#define BCHP_DMA_AHB_ECL_CMD_SCH8_REG_END 0x00fc0080
-#define BCHP_DMA_AHB_ECL_CMD_SCH9_REG_START 0x00fc0090
-#define BCHP_DMA_AHB_ECL_CMD_SCH9_REG_END 0x00fc0090
-#define BCHP_DMA_AHB_ECL_CMD_SCH10_REG_START 0x00fc00a0
-#define BCHP_DMA_AHB_ECL_CMD_SCH10_REG_END 0x00fc00a0
-#define BCHP_DMA_AHB_ECL_CMD_SCH11_REG_START 0x00fc00b0
-#define BCHP_DMA_AHB_ECL_CMD_SCH11_REG_END 0x00fc00b0
-#define BCHP_DMA_AHB_ECL_CMD_SCH12_REG_START 0x00fc00c0
-#define BCHP_DMA_AHB_ECL_CMD_SCH12_REG_END 0x00fc00c0
-#define BCHP_DMA_AHB_ECL_CMD_SCH13_REG_START 0x00fc00d0
-#define BCHP_DMA_AHB_ECL_CMD_SCH13_REG_END 0x00fc00d0
-#define BCHP_DMA_AHB_ECL_CMD_SCH14_REG_START 0x00fc00e0
-#define BCHP_DMA_AHB_ECL_CMD_SCH14_REG_END 0x00fc00e0
-#define BCHP_DMA_AHB_ECL_CMD_SCH15_REG_START 0x00fc00f0
-#define BCHP_DMA_AHB_ECL_CMD_SCH15_REG_END 0x00fc00f0
-#define BCHP_DMA_AHB_ECL_CMD_SCH16_REG_START 0x00fc0100
-#define BCHP_DMA_AHB_ECL_CMD_SCH16_REG_END 0x00fc0100
-#define BCHP_DMA_AHB_ECL_CMD_SCH17_REG_START 0x00fc0110
-#define BCHP_DMA_AHB_ECL_CMD_SCH17_REG_END 0x00fc0110
-#define BCHP_DMA_AHB_ECL_CMD_SCH18_REG_START 0x00fc0120
-#define BCHP_DMA_AHB_ECL_CMD_SCH18_REG_END 0x00fc0120
-#define BCHP_DMA_AHB_ECL_CMD_SCH19_REG_START 0x00fc0130
-#define BCHP_DMA_AHB_ECL_CMD_SCH19_REG_END 0x00fc0130
-#define BCHP_DMA_AHB_ECL_CMD_RX_REG_START 0x00fc0800
-#define BCHP_DMA_AHB_ECL_CMD_RX_REG_END 0x00fc0800
-#define BCHP_DMA_AHB_CMD_RX_SCH0_REG_START 0x00fc4000
-#define BCHP_DMA_AHB_CMD_RX_SCH0_REG_END 0x00fc4000
-#define BCHP_DMA_AHB_CMD_RX_SCH1_REG_START 0x00fc4010
-#define BCHP_DMA_AHB_CMD_RX_SCH1_REG_END 0x00fc4010
-#define BCHP_DMA_AHB_CMD_RX_SCH2_REG_START 0x00fc4020
-#define BCHP_DMA_AHB_CMD_RX_SCH2_REG_END 0x00fc4020
-#define BCHP_DMA_AHB_CMD_RX_SCH3_REG_START 0x00fc4030
-#define BCHP_DMA_AHB_CMD_RX_SCH3_REG_END 0x00fc4030
-#define BCHP_DMA_AHB_CMD_RX_SCH4_REG_START 0x00fc4040
-#define BCHP_DMA_AHB_CMD_RX_SCH4_REG_END 0x00fc4040
-#define BCHP_DMA_AHB_CMD_RX_SCH5_REG_START 0x00fc4050
-#define BCHP_DMA_AHB_CMD_RX_SCH5_REG_END 0x00fc4050
-#define BCHP_DMA_AHB_CMD_RX_SCH6_REG_START 0x00fc4060
-#define BCHP_DMA_AHB_CMD_RX_SCH6_REG_END 0x00fc4060
-#define BCHP_DMA_AHB_CMD_RX_SCH7_REG_START 0x00fc4070
-#define BCHP_DMA_AHB_CMD_RX_SCH7_REG_END 0x00fc4070
-#define BCHP_DMA_AHB_CMD_RX_SCH8_REG_START 0x00fc4080
-#define BCHP_DMA_AHB_CMD_RX_SCH8_REG_END 0x00fc4080
-#define BCHP_DMA_AHB_CMD_RX_SCH9_REG_START 0x00fc4090
-#define BCHP_DMA_AHB_CMD_RX_SCH9_REG_END 0x00fc4090
-#define BCHP_DMA_AHB_CMD_RX_SCH10_REG_START 0x00fc40a0
-#define BCHP_DMA_AHB_CMD_RX_SCH10_REG_END 0x00fc40a0
-#define BCHP_DMA_AHB_CMD_RX_SCH11_REG_START 0x00fc40b0
-#define BCHP_DMA_AHB_CMD_RX_SCH11_REG_END 0x00fc40b0
-#define BCHP_DMA_AHB_CMD_RX_SCH12_REG_START 0x00fc40c0
-#define BCHP_DMA_AHB_CMD_RX_SCH12_REG_END 0x00fc40c0
-#define BCHP_DMA_AHB_CMD_RX_SCH13_REG_START 0x00fc40d0
-#define BCHP_DMA_AHB_CMD_RX_SCH13_REG_END 0x00fc40d0
-#define BCHP_DMA_AHB_CMD_RX_SCH14_REG_START 0x00fc40e0
-#define BCHP_DMA_AHB_CMD_RX_SCH14_REG_END 0x00fc40e0
-#define BCHP_DMA_AHB_CMD_RX_SCH15_REG_START 0x00fc40f0
-#define BCHP_DMA_AHB_CMD_RX_SCH15_REG_END 0x00fc40f0
-#define BCHP_DMA_AHB_CMD_RX_SCH16_REG_START 0x00fc4100
-#define BCHP_DMA_AHB_CMD_RX_SCH16_REG_END 0x00fc4100
-#define BCHP_DMA_AHB_CMD_RX_SCH17_REG_START 0x00fc4110
-#define BCHP_DMA_AHB_CMD_RX_SCH17_REG_END 0x00fc4110
-#define BCHP_DMA_AHB_CMD_RX_SCH18_REG_START 0x00fc4120
-#define BCHP_DMA_AHB_CMD_RX_SCH18_REG_END 0x00fc4120
-#define BCHP_DMA_AHB_CMD_RX_SCH19_REG_START 0x00fc4130
-#define BCHP_DMA_AHB_CMD_RX_SCH19_REG_END 0x00fc4130
-#define BCHP_DMA_AHB_CMD_RES0_SCH0_REG_START 0x00fc4200
-#define BCHP_DMA_AHB_CMD_RES0_SCH0_REG_END 0x00fc4200
-#define BCHP_DMA_AHB_CMD_RES0_SCH1_REG_START 0x00fc4210
-#define BCHP_DMA_AHB_CMD_RES0_SCH1_REG_END 0x00fc4210
-#define BCHP_DMA_AHB_CMD_RES0_SCH2_REG_START 0x00fc4220
-#define BCHP_DMA_AHB_CMD_RES0_SCH2_REG_END 0x00fc4220
-#define BCHP_DMA_AHB_CMD_RES0_SCH3_REG_START 0x00fc4230
-#define BCHP_DMA_AHB_CMD_RES0_SCH3_REG_END 0x00fc4230
-#define BCHP_DMA_AHB_CMD_RES0_SCH4_REG_START 0x00fc4240
-#define BCHP_DMA_AHB_CMD_RES0_SCH4_REG_END 0x00fc4240
-#define BCHP_DMA_AHB_CMD_RES0_SCH5_REG_START 0x00fc4250
-#define BCHP_DMA_AHB_CMD_RES0_SCH5_REG_END 0x00fc4250
-#define BCHP_DMA_AHB_CMD_RES0_SCH6_REG_START 0x00fc4260
-#define BCHP_DMA_AHB_CMD_RES0_SCH6_REG_END 0x00fc4260
-#define BCHP_DMA_AHB_CMD_RES0_SCH7_REG_START 0x00fc4270
-#define BCHP_DMA_AHB_CMD_RES0_SCH7_REG_END 0x00fc4270
-#define BCHP_DMA_AHB_CMD_TX0_REG_START 0x00fc4800
-#define BCHP_DMA_AHB_CMD_TX0_REG_END 0x00fc4800
-#define BCHP_DMA_AHB_CMD_TX1_REG_START 0x00fc4a00
-#define BCHP_DMA_AHB_CMD_TX1_REG_END 0x00fc4a00
-#define BCHP_DMA_AHB_CMD_CONF0_REG_START 0x00fc4c00
-#define BCHP_DMA_AHB_CMD_CONF0_REG_END 0x00fc4c00
-#define BCHP_MAC_AHB_REG_START 0x00fc5000
-#define BCHP_MAC_AHB_REG_END 0x00fc500c
-#define BCHP_LLM_AHB_REG_START 0x00fc8000
-#define BCHP_LLM_AHB_REG_END 0x00fc805c
-#define BCHP_PHY_REG_START 0x00fe0000
-#define BCHP_PHY_REG_END 0x00fe47fc
-#define BCHP_ECL_REG_START 0x00fe8000
-#define BCHP_ECL_REG_END 0x00fecb20
-#define BCHP_DMA_IO2MEM_CH_ECL_TX_Global_REG_START 0x00fed000
-#define BCHP_DMA_IO2MEM_CH_ECL_TX_Global_REG_END 0x00fed014
-#define BCHP_DMA_IO2MEM_SUBCH_ECL_TX_SUBCH0_REG_START 0x00fed040
-#define BCHP_DMA_IO2MEM_SUBCH_ECL_TX_SUBCH0_REG_END 0x00fed06c
-#define BCHP_DMA_IO2MEM_SUBCH_ECL_TX_SUBCH1_REG_START 0x00fed080
-#define BCHP_DMA_IO2MEM_SUBCH_ECL_TX_SUBCH1_REG_END 0x00fed0ac
-#define BCHP_DMA_IO2MEM_SUBCH_ECL_TX_SUBCH2_REG_START 0x00fed0c0
-#define BCHP_DMA_IO2MEM_SUBCH_ECL_TX_SUBCH2_REG_END 0x00fed0ec
-#define BCHP_DMA_IO2MEM_SUBCH_ECL_TX_SUBCH3_REG_START 0x00fed100
-#define BCHP_DMA_IO2MEM_SUBCH_ECL_TX_SUBCH3_REG_END 0x00fed12c
-#define BCHP_DMA_IO2MEM_SUBCH_ECL_TX_SUBCH4_REG_START 0x00fed140
-#define BCHP_DMA_IO2MEM_SUBCH_ECL_TX_SUBCH4_REG_END 0x00fed16c
-#define BCHP_DMA_IO2MEM_SUBCH_ECL_TX_SUBCH5_REG_START 0x00fed180
-#define BCHP_DMA_IO2MEM_SUBCH_ECL_TX_SUBCH5_REG_END 0x00fed1ac
-#define BCHP_DMA_IO2MEM_SUBCH_ECL_TX_SUBCH6_REG_START 0x00fed1c0
-#define BCHP_DMA_IO2MEM_SUBCH_ECL_TX_SUBCH6_REG_END 0x00fed1ec
-#define BCHP_DMA_IO2MEM_SUBCH_ECL_TX_SUBCH7_REG_START 0x00fed200
-#define BCHP_DMA_IO2MEM_SUBCH_ECL_TX_SUBCH7_REG_END 0x00fed22c
-#define BCHP_DMA_IO2MEM_SUBCH_ECL_TX_SUBCH8_REG_START 0x00fed240
-#define BCHP_DMA_IO2MEM_SUBCH_ECL_TX_SUBCH8_REG_END 0x00fed26c
-#define BCHP_DMA_IO2MEM_SUBCH_ECL_TX_SUBCH9_REG_START 0x00fed280
-#define BCHP_DMA_IO2MEM_SUBCH_ECL_TX_SUBCH9_REG_END 0x00fed2ac
-#define BCHP_DMA_IO2MEM_SUBCH_ECL_TX_SUBCH10_REG_START 0x00fed2c0
-#define BCHP_DMA_IO2MEM_SUBCH_ECL_TX_SUBCH10_REG_END 0x00fed2ec
-#define BCHP_DMA_IO2MEM_SUBCH_ECL_TX_SUBCH11_REG_START 0x00fed300
-#define BCHP_DMA_IO2MEM_SUBCH_ECL_TX_SUBCH11_REG_END 0x00fed32c
-#define BCHP_DMA_IO2MEM_SUBCH_ECL_TX_SUBCH12_REG_START 0x00fed340
-#define BCHP_DMA_IO2MEM_SUBCH_ECL_TX_SUBCH12_REG_END 0x00fed36c
-#define BCHP_DMA_IO2MEM_SUBCH_ECL_TX_SUBCH13_REG_START 0x00fed380
-#define BCHP_DMA_IO2MEM_SUBCH_ECL_TX_SUBCH13_REG_END 0x00fed3ac
-#define BCHP_DMA_IO2MEM_SUBCH_ECL_TX_SUBCH14_REG_START 0x00fed3c0
-#define BCHP_DMA_IO2MEM_SUBCH_ECL_TX_SUBCH14_REG_END 0x00fed3ec
-#define BCHP_DMA_IO2MEM_SUBCH_ECL_TX_SUBCH15_REG_START 0x00fed400
-#define BCHP_DMA_IO2MEM_SUBCH_ECL_TX_SUBCH15_REG_END 0x00fed42c
-#define BCHP_DMA_IO2MEM_SUBCH_ECL_TX_SUBCH16_REG_START 0x00fed440
-#define BCHP_DMA_IO2MEM_SUBCH_ECL_TX_SUBCH16_REG_END 0x00fed46c
-#define BCHP_DMA_IO2MEM_SUBCH_ECL_TX_SUBCH17_REG_START 0x00fed480
-#define BCHP_DMA_IO2MEM_SUBCH_ECL_TX_SUBCH17_REG_END 0x00fed4ac
-#define BCHP_DMA_IO2MEM_SUBCH_ECL_TX_SUBCH18_REG_START 0x00fed4c0
-#define BCHP_DMA_IO2MEM_SUBCH_ECL_TX_SUBCH18_REG_END 0x00fed4ec
-#define BCHP_DMA_IO2MEM_SUBCH_ECL_TX_SUBCH19_REG_START 0x00fed500
-#define BCHP_DMA_IO2MEM_SUBCH_ECL_TX_SUBCH19_REG_END 0x00fed52c
-#define BCHP_DMA_MEM2IO_CH_ECL_RX_REG_START 0x00fed800
-#define BCHP_DMA_MEM2IO_CH_ECL_RX_REG_END 0x00fed828
-#define BCHP_GMII_REG_START 0x00fedc00
-#define BCHP_GMII_REG_END 0x00fedc58
-#define BCHP_MAC_APB_REG_START 0x00ff0000
-#define BCHP_MAC_APB_REG_END 0x00ff14fc
-#define BCHP_DMA_IO2MEM_CH_MAC_RX_Global_REG_START 0x00ff4000
-#define BCHP_DMA_IO2MEM_CH_MAC_RX_Global_REG_END 0x00ff4014
-#define BCHP_DMA_IO2MEM_SUBCH_MAC_RX_SUBCH0_REG_START 0x00ff4040
-#define BCHP_DMA_IO2MEM_SUBCH_MAC_RX_SUBCH0_REG_END 0x00ff406c
-#define BCHP_DMA_IO2MEM_SUBCH_MAC_RX_SUBCH1_REG_START 0x00ff4080
-#define BCHP_DMA_IO2MEM_SUBCH_MAC_RX_SUBCH1_REG_END 0x00ff40ac
-#define BCHP_DMA_IO2MEM_SUBCH_MAC_RX_SUBCH2_REG_START 0x00ff40c0
-#define BCHP_DMA_IO2MEM_SUBCH_MAC_RX_SUBCH2_REG_END 0x00ff40ec
-#define BCHP_DMA_IO2MEM_SUBCH_MAC_RX_SUBCH3_REG_START 0x00ff4100
-#define BCHP_DMA_IO2MEM_SUBCH_MAC_RX_SUBCH3_REG_END 0x00ff412c
-#define BCHP_DMA_IO2MEM_SUBCH_MAC_RX_SUBCH4_REG_START 0x00ff4140
-#define BCHP_DMA_IO2MEM_SUBCH_MAC_RX_SUBCH4_REG_END 0x00ff416c
-#define BCHP_DMA_IO2MEM_SUBCH_MAC_RX_SUBCH5_REG_START 0x00ff4180
-#define BCHP_DMA_IO2MEM_SUBCH_MAC_RX_SUBCH5_REG_END 0x00ff41ac
-#define BCHP_DMA_IO2MEM_SUBCH_MAC_RX_SUBCH6_REG_START 0x00ff41c0
-#define BCHP_DMA_IO2MEM_SUBCH_MAC_RX_SUBCH6_REG_END 0x00ff41ec
-#define BCHP_DMA_IO2MEM_SUBCH_MAC_RX_SUBCH7_REG_START 0x00ff4200
-#define BCHP_DMA_IO2MEM_SUBCH_MAC_RX_SUBCH7_REG_END 0x00ff422c
-#define BCHP_DMA_IO2MEM_SUBCH_MAC_RX_SUBCH8_REG_START 0x00ff4240
-#define BCHP_DMA_IO2MEM_SUBCH_MAC_RX_SUBCH8_REG_END 0x00ff426c
-#define BCHP_DMA_IO2MEM_SUBCH_MAC_RX_SUBCH9_REG_START 0x00ff4280
-#define BCHP_DMA_IO2MEM_SUBCH_MAC_RX_SUBCH9_REG_END 0x00ff42ac
-#define BCHP_DMA_IO2MEM_SUBCH_MAC_RX_SUBCH10_REG_START 0x00ff42c0
-#define BCHP_DMA_IO2MEM_SUBCH_MAC_RX_SUBCH10_REG_END 0x00ff42ec
-#define BCHP_DMA_IO2MEM_SUBCH_MAC_RX_SUBCH11_REG_START 0x00ff4300
-#define BCHP_DMA_IO2MEM_SUBCH_MAC_RX_SUBCH11_REG_END 0x00ff432c
-#define BCHP_DMA_IO2MEM_SUBCH_MAC_RX_SUBCH12_REG_START 0x00ff4340
-#define BCHP_DMA_IO2MEM_SUBCH_MAC_RX_SUBCH12_REG_END 0x00ff436c
-#define BCHP_DMA_IO2MEM_SUBCH_MAC_RX_SUBCH13_REG_START 0x00ff4380
-#define BCHP_DMA_IO2MEM_SUBCH_MAC_RX_SUBCH13_REG_END 0x00ff43ac
-#define BCHP_DMA_IO2MEM_SUBCH_MAC_RX_SUBCH14_REG_START 0x00ff43c0
-#define BCHP_DMA_IO2MEM_SUBCH_MAC_RX_SUBCH14_REG_END 0x00ff43ec
-#define BCHP_DMA_IO2MEM_SUBCH_MAC_RX_SUBCH15_REG_START 0x00ff4400
-#define BCHP_DMA_IO2MEM_SUBCH_MAC_RX_SUBCH15_REG_END 0x00ff442c
-#define BCHP_DMA_IO2MEM_SUBCH_MAC_RX_SUBCH16_REG_START 0x00ff4440
-#define BCHP_DMA_IO2MEM_SUBCH_MAC_RX_SUBCH16_REG_END 0x00ff446c
-#define BCHP_DMA_IO2MEM_SUBCH_MAC_RX_SUBCH17_REG_START 0x00ff4480
-#define BCHP_DMA_IO2MEM_SUBCH_MAC_RX_SUBCH17_REG_END 0x00ff44ac
-#define BCHP_DMA_IO2MEM_SUBCH_MAC_RX_SUBCH18_REG_START 0x00ff44c0
-#define BCHP_DMA_IO2MEM_SUBCH_MAC_RX_SUBCH18_REG_END 0x00ff44ec
-#define BCHP_DMA_IO2MEM_SUBCH_MAC_RX_SUBCH19_REG_START 0x00ff4500
-#define BCHP_DMA_IO2MEM_SUBCH_MAC_RX_SUBCH19_REG_END 0x00ff452c
-#define BCHP_DMA_IO2MEM_CH_PHY0_Global_REG_START 0x00ff4800
-#define BCHP_DMA_IO2MEM_CH_PHY0_Global_REG_END 0x00ff4814
-#define BCHP_DMA_IO2MEM_SUBCH_PHY0_SUBCH0_REG_START 0x00ff4840
-#define BCHP_DMA_IO2MEM_SUBCH_PHY0_SUBCH0_REG_END 0x00ff486c
-#define BCHP_DMA_IO2MEM_SUBCH_PHY0_SUBCH1_REG_START 0x00ff4880
-#define BCHP_DMA_IO2MEM_SUBCH_PHY0_SUBCH1_REG_END 0x00ff48ac
-#define BCHP_DMA_IO2MEM_SUBCH_PHY0_SUBCH2_REG_START 0x00ff48c0
-#define BCHP_DMA_IO2MEM_SUBCH_PHY0_SUBCH2_REG_END 0x00ff48ec
-#define BCHP_DMA_IO2MEM_SUBCH_PHY0_SUBCH3_REG_START 0x00ff4900
-#define BCHP_DMA_IO2MEM_SUBCH_PHY0_SUBCH3_REG_END 0x00ff492c
-#define BCHP_DMA_IO2MEM_SUBCH_PHY0_SUBCH4_REG_START 0x00ff4940
-#define BCHP_DMA_IO2MEM_SUBCH_PHY0_SUBCH4_REG_END 0x00ff496c
-#define BCHP_DMA_IO2MEM_SUBCH_PHY0_SUBCH5_REG_START 0x00ff4980
-#define BCHP_DMA_IO2MEM_SUBCH_PHY0_SUBCH5_REG_END 0x00ff49ac
-#define BCHP_DMA_IO2MEM_SUBCH_PHY0_SUBCH6_REG_START 0x00ff49c0
-#define BCHP_DMA_IO2MEM_SUBCH_PHY0_SUBCH6_REG_END 0x00ff49ec
-#define BCHP_DMA_IO2MEM_SUBCH_PHY0_SUBCH7_REG_START 0x00ff4a00
-#define BCHP_DMA_IO2MEM_SUBCH_PHY0_SUBCH7_REG_END 0x00ff4a2c
-#define BCHP_DMA_MEM2IO_CH_MAC_TX0_REG_START 0x00ff6000
-#define BCHP_DMA_MEM2IO_CH_MAC_TX0_REG_END 0x00ff6028
-#define BCHP_DMA_MEM2IO_CH_MAC_TX1_REG_START 0x00ff6400
-#define BCHP_DMA_MEM2IO_CH_MAC_TX1_REG_END 0x00ff6428
-#define BCHP_DMA_MEM2IO_CH_PHY0_CONFIG_REG_START 0x00ff6800
-#define BCHP_DMA_MEM2IO_CH_PHY0_CONFIG_REG_END 0x00ff6828
-#define BCHP_MOCA_INTC_L2_HI_REG_START 0x00ff8000
-#define BCHP_MOCA_INTC_L2_HI_REG_END 0x00ff8584
-#define BCHP_MOCA_INTC_L2_LO_REG_START 0x00ff8800
-#define BCHP_MOCA_INTC_L2_LO_REG_END 0x00ff8d84
-#define BCHP_LLM_APB_REG_START 0x00ffc000
-#define BCHP_LLM_APB_REG_END 0x00ffd00c
-#define BCHP_TRX_REG_START 0x00ffe000
-#define BCHP_TRX_REG_END 0x00ffe1fc
-#define BCHP_MOCA_TIMER_REG_START 0x00ffe400
-#define BCHP_MOCA_TIMER_REG_END 0x00ffe4ec
-#define BCHP_MOCA_GPIO_REG_START 0x00ffe800
-#define BCHP_MOCA_GPIO_REG_END 0x00ffe818
-#define BCHP_EXTRAS_REG_START 0x00ffec00
-#define BCHP_EXTRAS_REG_END 0x00ffed18
-#define BCHP_MOCA_BSC_REG_START 0x00fff000
-#define BCHP_MOCA_BSC_REG_END 0x00fff058
-#define BCHP_MOCA_HOSTM2M_REG_START 0x00fffc00
-#define BCHP_MOCA_HOSTM2M_REG_END 0x00fffc14
-#define BCHP_AHB_M2M_DMA_REG_START 0x00fffc20
-#define BCHP_AHB_M2M_DMA_REG_END 0x00fffc2c
-#define BCHP_MOCA_L2_REG_START 0x00fffc40
-#define BCHP_MOCA_L2_REG_END 0x00fffc6c
-#define BCHP_MOCA_GR_BRIDGE_REG_START 0x00fffc80
-#define BCHP_MOCA_GR_BRIDGE_REG_END 0x00fffc8c
-#define BCHP_MOCA_HOSTMISC_REG_START 0x00fffd00
-#define BCHP_MOCA_HOSTMISC_REG_END 0x00fffd9c
-#define BCHP_LEAP_ROM_REG_START 0x01000000
-#define BCHP_LEAP_ROM_REG_END 0x01007ffc
-#define BCHP_LEAP_PROG0_MEM_REG_START 0x01040000
-#define BCHP_LEAP_PROG0_MEM_REG_END 0x01043ffc
-#define BCHP_LEAP_PROG1_MEM_REG_START 0x01060000
-#define BCHP_LEAP_PROG1_MEM_REG_END 0x0106fffc
-#define BCHP_LEAP_DATA_MEM_REG_START 0x01080000
-#define BCHP_LEAP_DATA_MEM_REG_END 0x0109fffc
-#define BCHP_LEAP_CPU_CORE_REGS_REG_START 0x010a0000
-#define BCHP_LEAP_CPU_CORE_REGS_REG_END 0x010a00fc
-#define BCHP_LEAP_CPU_AUX_REGS_REG_START 0x010c0000
-#define BCHP_LEAP_CPU_AUX_REGS_REG_END 0x010c10c4
-#define BCHP_LEAP_HAB_MEM_REG_START 0x010c8000
-#define BCHP_LEAP_HAB_MEM_REG_END 0x010c83fc
-#define BCHP_LEAP_UART_REG_START 0x010c9000
-#define BCHP_LEAP_UART_REG_END 0x010c9ffc
-#define BCHP_LEAP_WDG_REG_START 0x010ca000
-#define BCHP_LEAP_WDG_REG_END 0x010caffc
-#define BCHP_LEAP_CTRL_REG_START 0x01100000
-#define BCHP_LEAP_CTRL_REG_END 0x011002fc
-#define BCHP_LEAP_L1_REG_START 0x01100400
-#define BCHP_LEAP_L1_REG_END 0x0110041c
-#define BCHP_LEAP_L2_REG_START 0x01100500
-#define BCHP_LEAP_L2_REG_END 0x01100514
-#define BCHP_LEAP_HOST_L1_REG_START 0x01100600
-#define BCHP_LEAP_HOST_L1_REG_END 0x0110061c
-#define BCHP_LEAP_HOST_L2_REG_START 0x01100700
-#define BCHP_LEAP_HOST_L2_REG_END 0x0110072c
-#define BCHP_LEAP_ROM_PATCH_REG_START 0x01100a00
-#define BCHP_LEAP_ROM_PATCH_REG_END 0x01100a3c
-#define BCHP_LEAP_RGR_BRIDGE_REG_START 0x01100b00
-#define BCHP_LEAP_RGR_BRIDGE_REG_END 0x01100b10
-#define BCHP_FTM_UART_REG_START 0x01210000
-#define BCHP_FTM_UART_REG_END 0x012100fc
-#define BCHP_FTM_PHY_REG_START 0x01210000
-#define BCHP_FTM_PHY_REG_END 0x012101fc
-#define BCHP_FTM_PHY_ANA_REG_START 0x01210000
-#define BCHP_FTM_PHY_ANA_REG_END 0x01210208
-#define BCHP_FTM_SKIT_REG_START 0x01210000
-#define BCHP_FTM_SKIT_REG_END 0x01210248
-#define BCHP_FTM_INTR2_REG_START 0x01210000
-#define BCHP_FTM_INTR2_REG_END 0x0121032c
-#define BCHP_FTM_SW_SPARE_REG_START 0x01210000
-#define BCHP_FTM_SW_SPARE_REG_END 0x01210334
-#define BCHP_SDS_DSEC_0_REG_START 0x01218000
-#define BCHP_SDS_DSEC_0_REG_END 0x012180d4
-#define BCHP_SDS_DSEC_INTR2_0_REG_START 0x01218100
-#define BCHP_SDS_DSEC_INTR2_0_REG_END 0x0121812c
-#define BCHP_SDS_DSEC_GR_BRIDGE_0_REG_START 0x01218140
-#define BCHP_SDS_DSEC_GR_BRIDGE_0_REG_END 0x0121814c
-#define BCHP_SDS_DSEC_AP_0_REG_START 0x01218150
-#define BCHP_SDS_DSEC_AP_0_REG_END 0x01218158
-#define BCHP_SDS_DSEC_1_REG_START 0x01219000
-#define BCHP_SDS_DSEC_1_REG_END 0x012190d4
-#define BCHP_SDS_DSEC_INTR2_1_REG_START 0x01219100
-#define BCHP_SDS_DSEC_INTR2_1_REG_END 0x0121912c
-#define BCHP_SDS_DSEC_GR_BRIDGE_1_REG_START 0x01219140
-#define BCHP_SDS_DSEC_GR_BRIDGE_1_REG_END 0x0121914c
-#define BCHP_SDS_DSEC_AP_1_REG_START 0x01219150
-#define BCHP_SDS_DSEC_AP_1_REG_END 0x01219158
-#define BCHP_STB_CHAN_CTRL_REG_START 0x0121c000
-#define BCHP_STB_CHAN_CTRL_REG_END 0x0121c040
-#define BCHP_STB_CHAN_CH0_REG_START 0x0121c100
-#define BCHP_STB_CHAN_CH0_REG_END 0x0121c1ec
-#define BCHP_STB_CHAN_CH1_REG_START 0x0121c200
-#define BCHP_STB_CHAN_CH1_REG_END 0x0121c2ec
-#define BCHP_STB_CHAN_CH2_REG_START 0x0121c300
-#define BCHP_STB_CHAN_CH2_REG_END 0x0121c3ec
-#define BCHP_STB_CHAN_CH3_REG_START 0x0121c400
-#define BCHP_STB_CHAN_CH3_REG_END 0x0121c4ec
-#define BCHP_STB_CHAN_CH4_REG_START 0x0121c500
-#define BCHP_STB_CHAN_CH4_REG_END 0x0121c5ec
-#define BCHP_STB_CHAN_CH5_REG_START 0x0121c600
-#define BCHP_STB_CHAN_CH5_REG_END 0x0121c6ec
-#define BCHP_STB_CHAN_CH6_REG_START 0x0121c700
-#define BCHP_STB_CHAN_CH6_REG_END 0x0121c7ec
-#define BCHP_STB_CHAN_CH7_REG_START 0x0121c800
-#define BCHP_STB_CHAN_CH7_REG_END 0x0121c8ec
-#define BCHP_AIF_MDAC_CAL_SAT_CORE0_REG_START 0x01224000
-#define BCHP_AIF_MDAC_CAL_SAT_CORE0_REG_END 0x01224118
-#define BCHP_AIF_MDAC_CAL_SAT_CORE_INTR2_0_REG_START 0x01224800
-#define BCHP_AIF_MDAC_CAL_SAT_CORE_INTR2_0_REG_END 0x0122482c
-#define BCHP_BAC_MSPI_REG_START 0x01225000
-#define BCHP_BAC_MSPI_REG_END 0x01225018
-#define BCHP_AIF_MDAC_CAL_SAT_BAC_REG_START 0x01225800
-#define BCHP_AIF_MDAC_CAL_SAT_BAC_REG_END 0x01225810
-#define BCHP_AIF_MDAC_CAL_SAT_ANA_REG_START 0x01226000
-#define BCHP_AIF_MDAC_CAL_SAT_ANA_REG_END 0x01226094
-#define BCHP_AIF_WB_SAT_CORE0_0_REG_START 0x01230000
-#define BCHP_AIF_WB_SAT_CORE0_0_REG_END 0x01230474
-#define BCHP_AIF_WB_SAT_CORE_INTR2_0_0_REG_START 0x01230800
-#define BCHP_AIF_WB_SAT_CORE_INTR2_0_0_REG_END 0x0123082c
-#define BCHP_AIF_WB_SAT_ANA_0_REG_START 0x01231000
-#define BCHP_AIF_WB_SAT_ANA_0_REG_END 0x012310c0
-#define BCHP_AIF_WB_SAT_CORE0_1_REG_START 0x01234000
-#define BCHP_AIF_WB_SAT_CORE0_1_REG_END 0x01234474
-#define BCHP_AIF_WB_SAT_CORE_INTR2_0_1_REG_START 0x01234800
-#define BCHP_AIF_WB_SAT_CORE_INTR2_0_1_REG_END 0x0123482c
-#define BCHP_AIF_WB_SAT_ANA_1_REG_START 0x01235000
-#define BCHP_AIF_WB_SAT_ANA_1_REG_END 0x012350c0
-#define BCHP_SDS_CG_0_REG_START 0x01240000
-#define BCHP_SDS_CG_0_REG_END 0x0124003c
-#define BCHP_SDS_FE_0_REG_START 0x01240080
-#define BCHP_SDS_FE_0_REG_END 0x012400bc
-#define BCHP_SDS_BL_0_REG_START 0x01240140
-#define BCHP_SDS_BL_0_REG_END 0x01240160
-#define BCHP_SDS_CL_0_REG_START 0x01240180
-#define BCHP_SDS_CL_0_REG_END 0x012401fc
-#define BCHP_SDS_EQ_0_REG_START 0x01240200
-#define BCHP_SDS_EQ_0_REG_END 0x0124028c
-#define BCHP_SDS_HP_0_REG_START 0x01240300
-#define BCHP_SDS_HP_0_REG_END 0x012403e8
-#define BCHP_SDS_VIT_0_REG_START 0x01240400
-#define BCHP_SDS_VIT_0_REG_END 0x01240428
-#define BCHP_SDS_FEC_0_REG_START 0x01240440
-#define BCHP_SDS_FEC_0_REG_END 0x01240454
-#define BCHP_SDS_OI_0_REG_START 0x01240480
-#define BCHP_SDS_OI_0_REG_END 0x012404cc
-#define BCHP_SDS_SNR_0_REG_START 0x01240500
-#define BCHP_SDS_SNR_0_REG_END 0x01240518
-#define BCHP_SDS_BERT_0_REG_START 0x01240540
-#define BCHP_SDS_BERT_0_REG_END 0x01240568
-#define BCHP_SDS_DFT_0_REG_START 0x01240580
-#define BCHP_SDS_DFT_0_REG_END 0x012405a8
-#define BCHP_SDS_CWC_0_REG_START 0x01240600
-#define BCHP_SDS_CWC_0_REG_END 0x01240694
-#define BCHP_SDS_MISC_0_REG_START 0x01240700
-#define BCHP_SDS_MISC_0_REG_END 0x01240798
-#define BCHP_SDS_INTR2_0_0_REG_START 0x01240a00
-#define BCHP_SDS_INTR2_0_0_REG_END 0x01240a2c
-#define BCHP_SDS_GR_BRIDGE_0_REG_START 0x01240c00
-#define BCHP_SDS_GR_BRIDGE_0_REG_END 0x01240c0c
-#define BCHP_SDS_CG_1_REG_START 0x01241000
-#define BCHP_SDS_CG_1_REG_END 0x0124103c
-#define BCHP_SDS_FE_1_REG_START 0x01241080
-#define BCHP_SDS_FE_1_REG_END 0x012410bc
-#define BCHP_SDS_BL_1_REG_START 0x01241140
-#define BCHP_SDS_BL_1_REG_END 0x01241160
-#define BCHP_SDS_CL_1_REG_START 0x01241180
-#define BCHP_SDS_CL_1_REG_END 0x012411fc
-#define BCHP_SDS_EQ_1_REG_START 0x01241200
-#define BCHP_SDS_EQ_1_REG_END 0x0124128c
-#define BCHP_SDS_HP_1_REG_START 0x01241300
-#define BCHP_SDS_HP_1_REG_END 0x012413e8
-#define BCHP_SDS_VIT_1_REG_START 0x01241400
-#define BCHP_SDS_VIT_1_REG_END 0x01241428
-#define BCHP_SDS_FEC_1_REG_START 0x01241440
-#define BCHP_SDS_FEC_1_REG_END 0x01241454
-#define BCHP_SDS_OI_1_REG_START 0x01241480
-#define BCHP_SDS_OI_1_REG_END 0x012414cc
-#define BCHP_SDS_SNR_1_REG_START 0x01241500
-#define BCHP_SDS_SNR_1_REG_END 0x01241518
-#define BCHP_SDS_BERT_1_REG_START 0x01241540
-#define BCHP_SDS_BERT_1_REG_END 0x01241568
-#define BCHP_SDS_DFT_1_REG_START 0x01241580
-#define BCHP_SDS_DFT_1_REG_END 0x012415a8
-#define BCHP_SDS_CWC_1_REG_START 0x01241600
-#define BCHP_SDS_CWC_1_REG_END 0x01241694
-#define BCHP_SDS_MISC_1_REG_START 0x01241700
-#define BCHP_SDS_MISC_1_REG_END 0x01241798
-#define BCHP_SDS_INTR2_0_1_REG_START 0x01241a00
-#define BCHP_SDS_INTR2_0_1_REG_END 0x01241a2c
-#define BCHP_SDS_GR_BRIDGE_1_REG_START 0x01241c00
-#define BCHP_SDS_GR_BRIDGE_1_REG_END 0x01241c0c
-#define BCHP_SDS_CG_2_REG_START 0x01242000
-#define BCHP_SDS_CG_2_REG_END 0x0124203c
-#define BCHP_SDS_FE_2_REG_START 0x01242080
-#define BCHP_SDS_FE_2_REG_END 0x012420bc
-#define BCHP_SDS_BL_2_REG_START 0x01242140
-#define BCHP_SDS_BL_2_REG_END 0x01242160
-#define BCHP_SDS_CL_2_REG_START 0x01242180
-#define BCHP_SDS_CL_2_REG_END 0x012421fc
-#define BCHP_SDS_EQ_2_REG_START 0x01242200
-#define BCHP_SDS_EQ_2_REG_END 0x0124228c
-#define BCHP_SDS_HP_2_REG_START 0x01242300
-#define BCHP_SDS_HP_2_REG_END 0x012423e8
-#define BCHP_SDS_VIT_2_REG_START 0x01242400
-#define BCHP_SDS_VIT_2_REG_END 0x01242428
-#define BCHP_SDS_FEC_2_REG_START 0x01242440
-#define BCHP_SDS_FEC_2_REG_END 0x01242454
-#define BCHP_SDS_OI_2_REG_START 0x01242480
-#define BCHP_SDS_OI_2_REG_END 0x012424cc
-#define BCHP_SDS_SNR_2_REG_START 0x01242500
-#define BCHP_SDS_SNR_2_REG_END 0x01242518
-#define BCHP_SDS_BERT_2_REG_START 0x01242540
-#define BCHP_SDS_BERT_2_REG_END 0x01242568
-#define BCHP_SDS_DFT_2_REG_START 0x01242580
-#define BCHP_SDS_DFT_2_REG_END 0x012425a8
-#define BCHP_SDS_CWC_2_REG_START 0x01242600
-#define BCHP_SDS_CWC_2_REG_END 0x01242694
-#define BCHP_SDS_MISC_2_REG_START 0x01242700
-#define BCHP_SDS_MISC_2_REG_END 0x01242798
-#define BCHP_SDS_INTR2_0_2_REG_START 0x01242a00
-#define BCHP_SDS_INTR2_0_2_REG_END 0x01242a2c
-#define BCHP_SDS_GR_BRIDGE_2_REG_START 0x01242c00
-#define BCHP_SDS_GR_BRIDGE_2_REG_END 0x01242c0c
-#define BCHP_SDS_CG_3_REG_START 0x01243000
-#define BCHP_SDS_CG_3_REG_END 0x0124303c
-#define BCHP_SDS_FE_3_REG_START 0x01243080
-#define BCHP_SDS_FE_3_REG_END 0x012430bc
-#define BCHP_SDS_BL_3_REG_START 0x01243140
-#define BCHP_SDS_BL_3_REG_END 0x01243160
-#define BCHP_SDS_CL_3_REG_START 0x01243180
-#define BCHP_SDS_CL_3_REG_END 0x012431fc
-#define BCHP_SDS_EQ_3_REG_START 0x01243200
-#define BCHP_SDS_EQ_3_REG_END 0x0124328c
-#define BCHP_SDS_HP_3_REG_START 0x01243300
-#define BCHP_SDS_HP_3_REG_END 0x012433e8
-#define BCHP_SDS_VIT_3_REG_START 0x01243400
-#define BCHP_SDS_VIT_3_REG_END 0x01243428
-#define BCHP_SDS_FEC_3_REG_START 0x01243440
-#define BCHP_SDS_FEC_3_REG_END 0x01243454
-#define BCHP_SDS_OI_3_REG_START 0x01243480
-#define BCHP_SDS_OI_3_REG_END 0x012434cc
-#define BCHP_SDS_SNR_3_REG_START 0x01243500
-#define BCHP_SDS_SNR_3_REG_END 0x01243518
-#define BCHP_SDS_BERT_3_REG_START 0x01243540
-#define BCHP_SDS_BERT_3_REG_END 0x01243568
-#define BCHP_SDS_DFT_3_REG_START 0x01243580
-#define BCHP_SDS_DFT_3_REG_END 0x012435a8
-#define BCHP_SDS_CWC_3_REG_START 0x01243600
-#define BCHP_SDS_CWC_3_REG_END 0x01243694
-#define BCHP_SDS_MISC_3_REG_START 0x01243700
-#define BCHP_SDS_MISC_3_REG_END 0x01243798
-#define BCHP_SDS_INTR2_0_3_REG_START 0x01243a00
-#define BCHP_SDS_INTR2_0_3_REG_END 0x01243a2c
-#define BCHP_SDS_GR_BRIDGE_3_REG_START 0x01243c00
-#define BCHP_SDS_GR_BRIDGE_3_REG_END 0x01243c0c
-#define BCHP_SDS_CG_4_REG_START 0x01244000
-#define BCHP_SDS_CG_4_REG_END 0x0124403c
-#define BCHP_SDS_FE_4_REG_START 0x01244080
-#define BCHP_SDS_FE_4_REG_END 0x012440bc
-#define BCHP_SDS_BL_4_REG_START 0x01244140
-#define BCHP_SDS_BL_4_REG_END 0x01244160
-#define BCHP_SDS_CL_4_REG_START 0x01244180
-#define BCHP_SDS_CL_4_REG_END 0x012441fc
-#define BCHP_SDS_EQ_4_REG_START 0x01244200
-#define BCHP_SDS_EQ_4_REG_END 0x0124428c
-#define BCHP_SDS_HP_4_REG_START 0x01244300
-#define BCHP_SDS_HP_4_REG_END 0x012443e8
-#define BCHP_SDS_VIT_4_REG_START 0x01244400
-#define BCHP_SDS_VIT_4_REG_END 0x01244428
-#define BCHP_SDS_FEC_4_REG_START 0x01244440
-#define BCHP_SDS_FEC_4_REG_END 0x01244454
-#define BCHP_SDS_OI_4_REG_START 0x01244480
-#define BCHP_SDS_OI_4_REG_END 0x012444cc
-#define BCHP_SDS_SNR_4_REG_START 0x01244500
-#define BCHP_SDS_SNR_4_REG_END 0x01244518
-#define BCHP_SDS_BERT_4_REG_START 0x01244540
-#define BCHP_SDS_BERT_4_REG_END 0x01244568
-#define BCHP_SDS_DFT_4_REG_START 0x01244580
-#define BCHP_SDS_DFT_4_REG_END 0x012445a8
-#define BCHP_SDS_CWC_4_REG_START 0x01244600
-#define BCHP_SDS_CWC_4_REG_END 0x01244694
-#define BCHP_SDS_MISC_4_REG_START 0x01244700
-#define BCHP_SDS_MISC_4_REG_END 0x01244798
-#define BCHP_SDS_INTR2_0_4_REG_START 0x01244a00
-#define BCHP_SDS_INTR2_0_4_REG_END 0x01244a2c
-#define BCHP_SDS_GR_BRIDGE_4_REG_START 0x01244c00
-#define BCHP_SDS_GR_BRIDGE_4_REG_END 0x01244c0c
-#define BCHP_SDS_CG_5_REG_START 0x01245000
-#define BCHP_SDS_CG_5_REG_END 0x0124503c
-#define BCHP_SDS_FE_5_REG_START 0x01245080
-#define BCHP_SDS_FE_5_REG_END 0x012450bc
-#define BCHP_SDS_BL_5_REG_START 0x01245140
-#define BCHP_SDS_BL_5_REG_END 0x01245160
-#define BCHP_SDS_CL_5_REG_START 0x01245180
-#define BCHP_SDS_CL_5_REG_END 0x012451fc
-#define BCHP_SDS_EQ_5_REG_START 0x01245200
-#define BCHP_SDS_EQ_5_REG_END 0x0124528c
-#define BCHP_SDS_HP_5_REG_START 0x01245300
-#define BCHP_SDS_HP_5_REG_END 0x012453e8
-#define BCHP_SDS_VIT_5_REG_START 0x01245400
-#define BCHP_SDS_VIT_5_REG_END 0x01245428
-#define BCHP_SDS_FEC_5_REG_START 0x01245440
-#define BCHP_SDS_FEC_5_REG_END 0x01245454
-#define BCHP_SDS_OI_5_REG_START 0x01245480
-#define BCHP_SDS_OI_5_REG_END 0x012454cc
-#define BCHP_SDS_SNR_5_REG_START 0x01245500
-#define BCHP_SDS_SNR_5_REG_END 0x01245518
-#define BCHP_SDS_BERT_5_REG_START 0x01245540
-#define BCHP_SDS_BERT_5_REG_END 0x01245568
-#define BCHP_SDS_DFT_5_REG_START 0x01245580
-#define BCHP_SDS_DFT_5_REG_END 0x012455a8
-#define BCHP_SDS_CWC_5_REG_START 0x01245600
-#define BCHP_SDS_CWC_5_REG_END 0x01245694
-#define BCHP_SDS_MISC_5_REG_START 0x01245700
-#define BCHP_SDS_MISC_5_REG_END 0x01245798
-#define BCHP_SDS_INTR2_0_5_REG_START 0x01245a00
-#define BCHP_SDS_INTR2_0_5_REG_END 0x01245a2c
-#define BCHP_SDS_GR_BRIDGE_5_REG_START 0x01245c00
-#define BCHP_SDS_GR_BRIDGE_5_REG_END 0x01245c0c
-#define BCHP_SDS_CG_6_REG_START 0x01246000
-#define BCHP_SDS_CG_6_REG_END 0x0124603c
-#define BCHP_SDS_FE_6_REG_START 0x01246080
-#define BCHP_SDS_FE_6_REG_END 0x012460bc
-#define BCHP_SDS_BL_6_REG_START 0x01246140
-#define BCHP_SDS_BL_6_REG_END 0x01246160
-#define BCHP_SDS_CL_6_REG_START 0x01246180
-#define BCHP_SDS_CL_6_REG_END 0x012461fc
-#define BCHP_SDS_EQ_6_REG_START 0x01246200
-#define BCHP_SDS_EQ_6_REG_END 0x0124628c
-#define BCHP_SDS_HP_6_REG_START 0x01246300
-#define BCHP_SDS_HP_6_REG_END 0x012463e8
-#define BCHP_SDS_VIT_6_REG_START 0x01246400
-#define BCHP_SDS_VIT_6_REG_END 0x01246428
-#define BCHP_SDS_FEC_6_REG_START 0x01246440
-#define BCHP_SDS_FEC_6_REG_END 0x01246454
-#define BCHP_SDS_OI_6_REG_START 0x01246480
-#define BCHP_SDS_OI_6_REG_END 0x012464cc
-#define BCHP_SDS_SNR_6_REG_START 0x01246500
-#define BCHP_SDS_SNR_6_REG_END 0x01246518
-#define BCHP_SDS_BERT_6_REG_START 0x01246540
-#define BCHP_SDS_BERT_6_REG_END 0x01246568
-#define BCHP_SDS_DFT_6_REG_START 0x01246580
-#define BCHP_SDS_DFT_6_REG_END 0x012465a8
-#define BCHP_SDS_CWC_6_REG_START 0x01246600
-#define BCHP_SDS_CWC_6_REG_END 0x01246694
-#define BCHP_SDS_MISC_6_REG_START 0x01246700
-#define BCHP_SDS_MISC_6_REG_END 0x01246798
-#define BCHP_SDS_INTR2_0_6_REG_START 0x01246a00
-#define BCHP_SDS_INTR2_0_6_REG_END 0x01246a2c
-#define BCHP_SDS_GR_BRIDGE_6_REG_START 0x01246c00
-#define BCHP_SDS_GR_BRIDGE_6_REG_END 0x01246c0c
-#define BCHP_SDS_CG_7_REG_START 0x01247000
-#define BCHP_SDS_CG_7_REG_END 0x0124703c
-#define BCHP_SDS_FE_7_REG_START 0x01247080
-#define BCHP_SDS_FE_7_REG_END 0x012470bc
-#define BCHP_SDS_BL_7_REG_START 0x01247140
-#define BCHP_SDS_BL_7_REG_END 0x01247160
-#define BCHP_SDS_CL_7_REG_START 0x01247180
-#define BCHP_SDS_CL_7_REG_END 0x012471fc
-#define BCHP_SDS_EQ_7_REG_START 0x01247200
-#define BCHP_SDS_EQ_7_REG_END 0x0124728c
-#define BCHP_SDS_HP_7_REG_START 0x01247300
-#define BCHP_SDS_HP_7_REG_END 0x012473e8
-#define BCHP_SDS_VIT_7_REG_START 0x01247400
-#define BCHP_SDS_VIT_7_REG_END 0x01247428
-#define BCHP_SDS_FEC_7_REG_START 0x01247440
-#define BCHP_SDS_FEC_7_REG_END 0x01247454
-#define BCHP_SDS_OI_7_REG_START 0x01247480
-#define BCHP_SDS_OI_7_REG_END 0x012474cc
-#define BCHP_SDS_SNR_7_REG_START 0x01247500
-#define BCHP_SDS_SNR_7_REG_END 0x01247518
-#define BCHP_SDS_BERT_7_REG_START 0x01247540
-#define BCHP_SDS_BERT_7_REG_END 0x01247568
-#define BCHP_SDS_DFT_7_REG_START 0x01247580
-#define BCHP_SDS_DFT_7_REG_END 0x012475a8
-#define BCHP_SDS_CWC_7_REG_START 0x01247600
-#define BCHP_SDS_CWC_7_REG_END 0x01247694
-#define BCHP_SDS_MISC_7_REG_START 0x01247700
-#define BCHP_SDS_MISC_7_REG_END 0x01247798
-#define BCHP_SDS_INTR2_0_7_REG_START 0x01247a00
-#define BCHP_SDS_INTR2_0_7_REG_END 0x01247a2c
-#define BCHP_SDS_GR_BRIDGE_7_REG_START 0x01247c00
-#define BCHP_SDS_GR_BRIDGE_7_REG_END 0x01247c0c
-#define BCHP_TFEC_0_REG_START 0x01248000
-#define BCHP_TFEC_0_REG_END 0x01248060
-#define BCHP_TFEC_MISC_0_REG_START 0x01248100
-#define BCHP_TFEC_MISC_0_REG_END 0x01248108
-#define BCHP_TFEC_INTR2_0_REG_START 0x01248200
-#define BCHP_TFEC_INTR2_0_REG_END 0x0124822c
-#define BCHP_TFEC_GR_BRIDGE_0_REG_START 0x01248300
-#define BCHP_TFEC_GR_BRIDGE_0_REG_END 0x0124830c
-#define BCHP_TFEC_1_REG_START 0x01249000
-#define BCHP_TFEC_1_REG_END 0x01249060
-#define BCHP_TFEC_MISC_1_REG_START 0x01249100
-#define BCHP_TFEC_MISC_1_REG_END 0x01249108
-#define BCHP_TFEC_INTR2_1_REG_START 0x01249200
-#define BCHP_TFEC_INTR2_1_REG_END 0x0124922c
-#define BCHP_TFEC_GR_BRIDGE_1_REG_START 0x01249300
-#define BCHP_TFEC_GR_BRIDGE_1_REG_END 0x0124930c
-#define BCHP_TFEC_2_REG_START 0x0124a000
-#define BCHP_TFEC_2_REG_END 0x0124a060
-#define BCHP_TFEC_MISC_2_REG_START 0x0124a100
-#define BCHP_TFEC_MISC_2_REG_END 0x0124a108
-#define BCHP_TFEC_INTR2_2_REG_START 0x0124a200
-#define BCHP_TFEC_INTR2_2_REG_END 0x0124a22c
-#define BCHP_TFEC_GR_BRIDGE_2_REG_START 0x0124a300
-#define BCHP_TFEC_GR_BRIDGE_2_REG_END 0x0124a30c
-#define BCHP_TFEC_3_REG_START 0x0124b000
-#define BCHP_TFEC_3_REG_END 0x0124b060
-#define BCHP_TFEC_MISC_3_REG_START 0x0124b100
-#define BCHP_TFEC_MISC_3_REG_END 0x0124b108
-#define BCHP_TFEC_INTR2_3_REG_START 0x0124b200
-#define BCHP_TFEC_INTR2_3_REG_END 0x0124b22c
-#define BCHP_TFEC_GR_BRIDGE_3_REG_START 0x0124b300
-#define BCHP_TFEC_GR_BRIDGE_3_REG_END 0x0124b30c
-#define BCHP_TFEC_4_REG_START 0x0124c000
-#define BCHP_TFEC_4_REG_END 0x0124c060
-#define BCHP_TFEC_MISC_4_REG_START 0x0124c100
-#define BCHP_TFEC_MISC_4_REG_END 0x0124c108
-#define BCHP_TFEC_INTR2_4_REG_START 0x0124c200
-#define BCHP_TFEC_INTR2_4_REG_END 0x0124c22c
-#define BCHP_TFEC_GR_BRIDGE_4_REG_START 0x0124c300
-#define BCHP_TFEC_GR_BRIDGE_4_REG_END 0x0124c30c
-#define BCHP_TFEC_5_REG_START 0x0124d000
-#define BCHP_TFEC_5_REG_END 0x0124d060
-#define BCHP_TFEC_MISC_5_REG_START 0x0124d100
-#define BCHP_TFEC_MISC_5_REG_END 0x0124d108
-#define BCHP_TFEC_INTR2_5_REG_START 0x0124d200
-#define BCHP_TFEC_INTR2_5_REG_END 0x0124d22c
-#define BCHP_TFEC_GR_BRIDGE_5_REG_START 0x0124d300
-#define BCHP_TFEC_GR_BRIDGE_5_REG_END 0x0124d30c
-#define BCHP_TFEC_6_REG_START 0x0124e000
-#define BCHP_TFEC_6_REG_END 0x0124e060
-#define BCHP_TFEC_MISC_6_REG_START 0x0124e100
-#define BCHP_TFEC_MISC_6_REG_END 0x0124e108
-#define BCHP_TFEC_INTR2_6_REG_START 0x0124e200
-#define BCHP_TFEC_INTR2_6_REG_END 0x0124e22c
-#define BCHP_TFEC_GR_BRIDGE_6_REG_START 0x0124e300
-#define BCHP_TFEC_GR_BRIDGE_6_REG_END 0x0124e30c
-#define BCHP_TFEC_7_REG_START 0x0124f000
-#define BCHP_TFEC_7_REG_END 0x0124f060
-#define BCHP_TFEC_MISC_7_REG_START 0x0124f100
-#define BCHP_TFEC_MISC_7_REG_END 0x0124f108
-#define BCHP_TFEC_INTR2_7_REG_START 0x0124f200
-#define BCHP_TFEC_INTR2_7_REG_END 0x0124f22c
-#define BCHP_TFEC_GR_BRIDGE_7_REG_START 0x0124f300
-#define BCHP_TFEC_GR_BRIDGE_7_REG_END 0x0124f30c
-#define BCHP_AFECNX_GLOBAL_0_REG_START 0x01250000
-#define BCHP_AFECNX_GLOBAL_0_REG_END 0x01250010
-#define BCHP_AFECNX_0_REG_START 0x01250100
-#define BCHP_AFECNX_0_REG_END 0x01250144
-#define BCHP_AFEC0_0_REG_START 0x01251000
-#define BCHP_AFEC0_0_REG_END 0x01251a0c
-#define BCHP_AFEC1_0_REG_START 0x01252000
-#define BCHP_AFEC1_0_REG_END 0x01252a0c
-#define BCHP_AFEC0_INTR_0_REG_START 0x01253000
-#define BCHP_AFEC0_INTR_0_REG_END 0x0125302c
-#define BCHP_AFEC1_INTR_0_REG_START 0x01253400
-#define BCHP_AFEC1_INTR_0_REG_END 0x0125342c
-#define BCHP_AFEC_GLOBAL_INTR_0_REG_START 0x01253800
-#define BCHP_AFEC_GLOBAL_INTR_0_REG_END 0x0125382c
-#define BCHP_AFEC_GR_BRIDGE_0_REG_START 0x01254000
-#define BCHP_AFEC_GR_BRIDGE_0_REG_END 0x0125400c
-#define BCHP_AFECNX_GLOBAL_1_REG_START 0x01258000
-#define BCHP_AFECNX_GLOBAL_1_REG_END 0x01258010
-#define BCHP_AFECNX_1_REG_START 0x01258100
-#define BCHP_AFECNX_1_REG_END 0x01258144
-#define BCHP_AFEC0_1_REG_START 0x01259000
-#define BCHP_AFEC0_1_REG_END 0x01259a0c
-#define BCHP_AFEC1_1_REG_START 0x0125a000
-#define BCHP_AFEC1_1_REG_END 0x0125aa0c
-#define BCHP_AFEC0_INTR_1_REG_START 0x0125b000
-#define BCHP_AFEC0_INTR_1_REG_END 0x0125b02c
-#define BCHP_AFEC1_INTR_1_REG_START 0x0125b400
-#define BCHP_AFEC1_INTR_1_REG_END 0x0125b42c
-#define BCHP_AFEC_GLOBAL_INTR_1_REG_START 0x0125b800
-#define BCHP_AFEC_GLOBAL_INTR_1_REG_END 0x0125b82c
-#define BCHP_AFEC_GR_BRIDGE_1_REG_START 0x0125c000
-#define BCHP_AFEC_GR_BRIDGE_1_REG_END 0x0125c00c
-#define BCHP_AFECNX_GLOBAL_2_REG_START 0x01260000
-#define BCHP_AFECNX_GLOBAL_2_REG_END 0x01260010
-#define BCHP_AFECNX_2_REG_START 0x01260100
-#define BCHP_AFECNX_2_REG_END 0x01260144
-#define BCHP_AFEC0_2_REG_START 0x01261000
-#define BCHP_AFEC0_2_REG_END 0x01261a0c
-#define BCHP_AFEC1_2_REG_START 0x01262000
-#define BCHP_AFEC1_2_REG_END 0x01262a0c
-#define BCHP_AFEC0_INTR_2_REG_START 0x01263000
-#define BCHP_AFEC0_INTR_2_REG_END 0x0126302c
-#define BCHP_AFEC1_INTR_2_REG_START 0x01263400
-#define BCHP_AFEC1_INTR_2_REG_END 0x0126342c
-#define BCHP_AFEC_GLOBAL_INTR_2_REG_START 0x01263800
-#define BCHP_AFEC_GLOBAL_INTR_2_REG_END 0x0126382c
-#define BCHP_AFEC_GR_BRIDGE_2_REG_START 0x01264000
-#define BCHP_AFEC_GR_BRIDGE_2_REG_END 0x0126400c
-#define BCHP_AFECNX_GLOBAL_3_REG_START 0x01268000
-#define BCHP_AFECNX_GLOBAL_3_REG_END 0x01268010
-#define BCHP_AFECNX_3_REG_START 0x01268100
-#define BCHP_AFECNX_3_REG_END 0x01268144
-#define BCHP_AFEC0_3_REG_START 0x01269000
-#define BCHP_AFEC0_3_REG_END 0x01269a0c
-#define BCHP_AFEC1_3_REG_START 0x0126a000
-#define BCHP_AFEC1_3_REG_END 0x0126aa0c
-#define BCHP_AFEC0_INTR_3_REG_START 0x0126b000
-#define BCHP_AFEC0_INTR_3_REG_END 0x0126b02c
-#define BCHP_AFEC1_INTR_3_REG_START 0x0126b400
-#define BCHP_AFEC1_INTR_3_REG_END 0x0126b42c
-#define BCHP_AFEC_GLOBAL_INTR_3_REG_START 0x0126b800
-#define BCHP_AFEC_GLOBAL_INTR_3_REG_END 0x0126b82c
-#define BCHP_AFEC_GR_BRIDGE_3_REG_START 0x0126c000
-#define BCHP_AFEC_GR_BRIDGE_3_REG_END 0x0126c00c
-#define BCHP_DEMOD_XPT_MTSIF_TX0_IO_REG_START 0x01270200
-#define BCHP_DEMOD_XPT_MTSIF_TX0_IO_REG_END 0x01270204
-#define BCHP_DEMOD_XPT_MTSIF_TX1_IO_REG_START 0x01270300
-#define BCHP_DEMOD_XPT_MTSIF_TX1_IO_REG_END 0x01270304
-#define BCHP_DEMOD_XPT_WAKEUP_REG_START 0x01271000
-#define BCHP_DEMOD_XPT_WAKEUP_REG_END 0x01271fbc
-#define BCHP_DEMOD_XPT_FE_REG_START 0x01272000
-#define BCHP_DEMOD_XPT_FE_REG_END 0x012737fc
-#define BCHP_RF4CE_CPU_PROG0_MEM_REG_START 0x01400000
-#define BCHP_RF4CE_CPU_PROG0_MEM_REG_END 0x0141fffc
-#define BCHP_RF4CE_CPU_PROG1_MEM_REG_START 0x01420000
-#define BCHP_RF4CE_CPU_PROG1_MEM_REG_END 0x0143fffc
-#define BCHP_RF4CE_CPU_DATA_MEM_REG_START 0x01440000
-#define BCHP_RF4CE_CPU_DATA_MEM_REG_END 0x01447ffc
-#define BCHP_RF4CE_CPU_CORE_REGS_REG_START 0x01450000
-#define BCHP_RF4CE_CPU_CORE_REGS_REG_END 0x014500fc
-#define BCHP_RF4CE_CPU_AUX_REGS_REG_START 0x01451000
-#define BCHP_RF4CE_CPU_AUX_REGS_REG_END 0x01451a08
-#define BCHP_RF4CE_CPU_UART_REG_START 0x01452000
-#define BCHP_RF4CE_CPU_UART_REG_END 0x01452ffc
-#define BCHP_RF4CE_CPU_WDG_REG_START 0x01453000
-#define BCHP_RF4CE_CPU_WDG_REG_END 0x01453ffc
-#define BCHP_RF4CE_CPU_CTRL_REG_START 0x01480000
-#define BCHP_RF4CE_CPU_CTRL_REG_END 0x0148008c
-#define BCHP_RF4CE_CPU_L2_REG_START 0x01480300
-#define BCHP_RF4CE_CPU_L2_REG_END 0x01480314
-#define BCHP_RF4CE_CPU_HOST_STB_L2_REG_START 0x01480500
-#define BCHP_RF4CE_CPU_HOST_STB_L2_REG_END 0x0148052c
-#define BCHP_RF4CE_CPU_HOST_CM_L2_REG_START 0x01480800
-#define BCHP_RF4CE_CPU_HOST_CM_L2_REG_END 0x0148082c
-#define BCHP_RF4CE_CPU_HOST_RG_L2_REG_START 0x01480a00
-#define BCHP_RF4CE_CPU_HOST_RG_L2_REG_END 0x01480a2c
-#define BCHP_TX_REG_START 0x014c0000
-#define BCHP_TX_REG_END 0x014c0020
-#define BCHP_RX_REG_START 0x014d0000
-#define BCHP_RX_REG_END 0x014d01e0
-#define BCHP_RF_REG_START 0x014e0000
-#define BCHP_RF_REG_END 0x014e0098
-#define BCHP_VCOCAL_REG_START 0x014e0100
-#define BCHP_VCOCAL_REG_END 0x014e0174
-#define BCHP_KVCO_REG_START 0x014e0200
-#define BCHP_KVCO_REG_END 0x014e0224
-#define BCHP_PA_REG_START 0x014e0300
-#define BCHP_PA_REG_END 0x014e0314
-#define BCHP_MAC_REG_START 0x014e0400
-#define BCHP_MAC_REG_END 0x014e0564
-#define BCHP_PWR_MGT_L2_REG_START 0x014e0600
-#define BCHP_PWR_MGT_L2_REG_END 0x014e0614
-#define BCHP_MISC_L2_REG_START 0x014e0700
-#define BCHP_MISC_L2_REG_END 0x014e0714
-#define BCHP_IQCAL_CCA_CCM_L2_REG_START 0x014e0800
-#define BCHP_IQCAL_CCA_CCM_L2_REG_END 0x014e0814
-#define BCHP_SYMCNT6_L2_REG_START 0x014e0900
-#define BCHP_SYMCNT6_L2_REG_END 0x014e0914
-#define BCHP_TX_DONE_L2_REG_START 0x014e0a00
-#define BCHP_TX_DONE_L2_REG_END 0x014e0a14
-#define BCHP_RX_DONE_L2_REG_START 0x014e0b00
-#define BCHP_RX_DONE_L2_REG_END 0x014e0b14
-#define BCHP_RX_START_L2_REG_START 0x014e0c00
-#define BCHP_RX_START_L2_REG_END 0x014e0c14
-#define BCHP_SYMCNT7_L2_REG_START 0x014e0d00
-#define BCHP_SYMCNT7_L2_REG_END 0x014e0d14
-#define BCHP_GCI_0_REG_START 0x014e1000
-#define BCHP_GCI_0_REG_END 0x014e120c
-#define BCHP_GCI_1_REG_START 0x014e1400
-#define BCHP_GCI_1_REG_END 0x014e1604
-#define BCHP_GCI_2_REG_START 0x014e1800
-#define BCHP_GCI_2_REG_END 0x014e1a04
-
-
-/***************************************************************************
- *AUD_FMM_MS_CTRL
- ***************************************************************************/
-/***************************************************************************
- *ABSTRACT_01_MICRO_SEQUENCER_CONTROL - Process to initialize and enable microsequencer
- ***************************************************************************/
-/* AUD_FMM_MS_CTRL :: ABSTRACT_01_MICRO_SEQUENCER_CONTROL :: NULL [31:00] */
-#define BCHP_AUD_FMM_MS_CTRL_ABSTRACT_01_MICRO_SEQUENCER_CONTROL_NULL_MASK 0xffffffff
-#define BCHP_AUD_FMM_MS_CTRL_ABSTRACT_01_MICRO_SEQUENCER_CONTROL_NULL_SHIFT 0
-
-/***************************************************************************
- *ABSTRACT_02_CHANNEL_STATUS - How to control channel status bits
- ***************************************************************************/
-/* AUD_FMM_MS_CTRL :: ABSTRACT_02_CHANNEL_STATUS :: NULL [31:00] */
-#define BCHP_AUD_FMM_MS_CTRL_ABSTRACT_02_CHANNEL_STATUS_NULL_MASK 0xffffffff
-#define BCHP_AUD_FMM_MS_CTRL_ABSTRACT_02_CHANNEL_STATUS_NULL_SHIFT 0
-
-/***************************************************************************
- *AUD_FMM_OP_CTRL
- ***************************************************************************/
-/***************************************************************************
- *ABSTRACT_01_MULTICHANNEL_MAI - Transmitting 6- and 8-channel MAI
- ***************************************************************************/
-/* AUD_FMM_OP_CTRL :: ABSTRACT_01_MULTICHANNEL_MAI :: MORE_INFORMATION [31:00] */
-#define BCHP_AUD_FMM_OP_CTRL_ABSTRACT_01_MULTICHANNEL_MAI_MORE_INFORMATION_MASK 0xffffffff
-#define BCHP_AUD_FMM_OP_CTRL_ABSTRACT_01_MULTICHANNEL_MAI_MORE_INFORMATION_SHIFT 0
-
-/***************************************************************************
- *BVN_MVFD_MFD
- ***************************************************************************/
-/***************************************************************************
- *DRAM_DATA_STRUCTURE - DRAM Data Structure
- ***************************************************************************/
-/* BVN_MVFD_MFD :: DRAM_DATA_STRUCTURE :: DRAM_DATA_STRUCTURE [31:00] */
-#define BCHP_BVN_MVFD_MFD_DRAM_DATA_STRUCTURE_DRAM_DATA_STRUCTURE_MASK 0xffffffff
-#define BCHP_BVN_MVFD_MFD_DRAM_DATA_STRUCTURE_DRAM_DATA_STRUCTURE_SHIFT 0
-
-/***************************************************************************
- *BVN_MVFD_MFD_8B_HD
- ***************************************************************************/
-/***************************************************************************
- *DRAM_DATA_STRUCTURE - DRAM Data Structure
- ***************************************************************************/
-/* BVN_MVFD_MFD_8B_HD :: DRAM_DATA_STRUCTURE :: DRAM_DATA_STRUCTURE [31:00] */
-#define BCHP_BVN_MVFD_MFD_8B_HD_DRAM_DATA_STRUCTURE_DRAM_DATA_STRUCTURE_MASK 0xffffffff
-#define BCHP_BVN_MVFD_MFD_8B_HD_DRAM_DATA_STRUCTURE_DRAM_DATA_STRUCTURE_SHIFT 0
-
-/***************************************************************************
- *BVN_MVFD_MFD_8B_UHD
- ***************************************************************************/
-/***************************************************************************
- *DRAM_DATA_STRUCTURE - DRAM Data Structure
- ***************************************************************************/
-/* BVN_MVFD_MFD_8B_UHD :: DRAM_DATA_STRUCTURE :: DRAM_DATA_STRUCTURE [31:00] */
-#define BCHP_BVN_MVFD_MFD_8B_UHD_DRAM_DATA_STRUCTURE_DRAM_DATA_STRUCTURE_MASK 0xffffffff
-#define BCHP_BVN_MVFD_MFD_8B_UHD_DRAM_DATA_STRUCTURE_DRAM_DATA_STRUCTURE_SHIFT 0
-
-/***************************************************************************
- *BVN_MVFD_VFD
- ***************************************************************************/
-/***************************************************************************
- *DRAM_DATA_STRUCTURE - DRAM Data Structure
- ***************************************************************************/
-/* BVN_MVFD_VFD :: DRAM_DATA_STRUCTURE :: DRAM_DATA_STRUCTURE [31:00] */
-#define BCHP_BVN_MVFD_VFD_DRAM_DATA_STRUCTURE_DRAM_DATA_STRUCTURE_MASK 0xffffffff
-#define BCHP_BVN_MVFD_VFD_DRAM_DATA_STRUCTURE_DRAM_DATA_STRUCTURE_SHIFT 0
-
-/***************************************************************************
- *BVN_MVFD_VFD_8B
- ***************************************************************************/
-/***************************************************************************
- *DRAM_DATA_STRUCTURE - DRAM Data Structure
- ***************************************************************************/
-/* BVN_MVFD_VFD_8B :: DRAM_DATA_STRUCTURE :: DRAM_DATA_STRUCTURE [31:00] */
-#define BCHP_BVN_MVFD_VFD_8B_DRAM_DATA_STRUCTURE_DRAM_DATA_STRUCTURE_MASK 0xffffffff
-#define BCHP_BVN_MVFD_VFD_8B_DRAM_DATA_STRUCTURE_DRAM_DATA_STRUCTURE_SHIFT 0
-
-/***************************************************************************
- *BVN_MVFD_VFD_8B_NODCD
- ***************************************************************************/
-/***************************************************************************
- *DRAM_DATA_STRUCTURE - DRAM Data Structure
- ***************************************************************************/
-/* BVN_MVFD_VFD_8B_NODCD :: DRAM_DATA_STRUCTURE :: DRAM_DATA_STRUCTURE [31:00] */
-#define BCHP_BVN_MVFD_VFD_8B_NODCD_DRAM_DATA_STRUCTURE_DRAM_DATA_STRUCTURE_MASK 0xffffffff
-#define BCHP_BVN_MVFD_VFD_8B_NODCD_DRAM_DATA_STRUCTURE_DRAM_DATA_STRUCTURE_SHIFT 0
-
-/***************************************************************************
- *GFD
- ***************************************************************************/
-/***************************************************************************
- *DRAM_DATA_STRUCTURE - DRAM Data Structure
- ***************************************************************************/
-/* GFD :: DRAM_DATA_STRUCTURE :: DRAM_DATA_STRUCTURE [31:00] */
-#define BCHP_GFD_DRAM_DATA_STRUCTURE_DRAM_DATA_STRUCTURE_MASK 0xffffffff
-#define BCHP_GFD_DRAM_DATA_STRUCTURE_DRAM_DATA_STRUCTURE_SHIFT 0
-
-/***************************************************************************
- *GFD_HSCL_VSCL_ONLY
- ***************************************************************************/
-/***************************************************************************
- *DRAM_DATA_STRUCTURE - DRAM Data Structure
- ***************************************************************************/
-/* GFD_HSCL_VSCL_ONLY :: DRAM_DATA_STRUCTURE :: DRAM_DATA_STRUCTURE [31:00] */
-#define BCHP_GFD_HSCL_VSCL_ONLY_DRAM_DATA_STRUCTURE_DRAM_DATA_STRUCTURE_MASK 0xffffffff
-#define BCHP_GFD_HSCL_VSCL_ONLY_DRAM_DATA_STRUCTURE_DRAM_DATA_STRUCTURE_SHIFT 0
-
-/***************************************************************************
- *GFD_NO_DCXG
- ***************************************************************************/
-/***************************************************************************
- *DRAM_DATA_STRUCTURE - DRAM Data Structure
- ***************************************************************************/
-/* GFD_NO_DCXG :: DRAM_DATA_STRUCTURE :: DRAM_DATA_STRUCTURE [31:00] */
-#define BCHP_GFD_NO_DCXG_DRAM_DATA_STRUCTURE_DRAM_DATA_STRUCTURE_MASK 0xffffffff
-#define BCHP_GFD_NO_DCXG_DRAM_DATA_STRUCTURE_DRAM_DATA_STRUCTURE_SHIFT 0
-
-/***************************************************************************
- *HIFIDAC_CTRL
- ***************************************************************************/
-/***************************************************************************
- *ABSTRACT_01_COMING_OUT_OF_RESET - Process to come out of reset
- ***************************************************************************/
-/* HIFIDAC_CTRL :: ABSTRACT_01_COMING_OUT_OF_RESET :: MORE_INFORMATION [31:00] */
-#define BCHP_HIFIDAC_CTRL_ABSTRACT_01_COMING_OUT_OF_RESET_MORE_INFORMATION_MASK 0xffffffff
-#define BCHP_HIFIDAC_CTRL_ABSTRACT_01_COMING_OUT_OF_RESET_MORE_INFORMATION_SHIFT 0
-
-/***************************************************************************
- *ABSTRACT_02_MUTE_USAGE - Mute usage
- ***************************************************************************/
-/* HIFIDAC_CTRL :: ABSTRACT_02_MUTE_USAGE :: MORE_INFORMATION [31:00] */
-#define BCHP_HIFIDAC_CTRL_ABSTRACT_02_MUTE_USAGE_MORE_INFORMATION_MASK 0xffffffff
-#define BCHP_HIFIDAC_CTRL_ABSTRACT_02_MUTE_USAGE_MORE_INFORMATION_SHIFT 0
-
-/***************************************************************************
- *ABSTRACT_03_SAMPLE_RATE_CHANGE - Process to effect a sample rate change
- ***************************************************************************/
-/* HIFIDAC_CTRL :: ABSTRACT_03_SAMPLE_RATE_CHANGE :: MORE_INFORMATION [31:00] */
-#define BCHP_HIFIDAC_CTRL_ABSTRACT_03_SAMPLE_RATE_CHANGE_MORE_INFORMATION_MASK 0xffffffff
-#define BCHP_HIFIDAC_CTRL_ABSTRACT_03_SAMPLE_RATE_CHANGE_MORE_INFORMATION_SHIFT 0
-
-/***************************************************************************
- *M2MC
- ***************************************************************************/
-/***************************************************************************
- *TYPE_CLUT_COLOR_DATA - color data for color look up table
- ***************************************************************************/
-/* M2MC :: TYPE_CLUT_COLOR_DATA :: ALPHA [31:24] */
-#define BCHP_M2MC_TYPE_CLUT_COLOR_DATA_ALPHA_MASK 0xff000000
-#define BCHP_M2MC_TYPE_CLUT_COLOR_DATA_ALPHA_SHIFT 24
-
-/* M2MC :: TYPE_CLUT_COLOR_DATA :: RED [23:16] */
-#define BCHP_M2MC_TYPE_CLUT_COLOR_DATA_RED_MASK 0x00ff0000
-#define BCHP_M2MC_TYPE_CLUT_COLOR_DATA_RED_SHIFT 16
-
-/* M2MC :: TYPE_CLUT_COLOR_DATA :: GREEN [15:08] */
-#define BCHP_M2MC_TYPE_CLUT_COLOR_DATA_GREEN_MASK 0x0000ff00
-#define BCHP_M2MC_TYPE_CLUT_COLOR_DATA_GREEN_SHIFT 8
-
-/* M2MC :: TYPE_CLUT_COLOR_DATA :: BLUE [07:00] */
-#define BCHP_M2MC_TYPE_CLUT_COLOR_DATA_BLUE_MASK 0x000000ff
-#define BCHP_M2MC_TYPE_CLUT_COLOR_DATA_BLUE_SHIFT 0
-
-/***************************************************************************
- *LIST_PACKET_ABSTRACT - Linked-List Packet Abstract
- ***************************************************************************/
-/* M2MC :: LIST_PACKET_ABSTRACT :: PACKET_FORMAT [31:00] */
-#define BCHP_M2MC_LIST_PACKET_ABSTRACT_PACKET_FORMAT_MASK 0xffffffff
-#define BCHP_M2MC_LIST_PACKET_ABSTRACT_PACKET_FORMAT_SHIFT 0
-
-/***************************************************************************
- *LIST_PACKET_HEADER_0 - Linked-List Packet Header Word 0
- ***************************************************************************/
-/* M2MC :: LIST_PACKET_HEADER_0 :: reserved0 [31:28] */
-#define BCHP_M2MC_LIST_PACKET_HEADER_0_reserved0_MASK 0xf0000000
-#define BCHP_M2MC_LIST_PACKET_HEADER_0_reserved0_SHIFT 28
-
-/* M2MC :: LIST_PACKET_HEADER_0 :: NEXT_PKT_ADDR [27:05] */
-#define BCHP_M2MC_LIST_PACKET_HEADER_0_NEXT_PKT_ADDR_MASK 0x0fffffe0
-#define BCHP_M2MC_LIST_PACKET_HEADER_0_NEXT_PKT_ADDR_SHIFT 5
-
-/* M2MC :: LIST_PACKET_HEADER_0 :: reserved1 [04:01] */
-#define BCHP_M2MC_LIST_PACKET_HEADER_0_reserved1_MASK 0x0000001e
-#define BCHP_M2MC_LIST_PACKET_HEADER_0_reserved1_SHIFT 1
-
-/* M2MC :: LIST_PACKET_HEADER_0 :: LAST_PKT_IND [00:00] */
-#define BCHP_M2MC_LIST_PACKET_HEADER_0_LAST_PKT_IND_MASK 0x00000001
-#define BCHP_M2MC_LIST_PACKET_HEADER_0_LAST_PKT_IND_SHIFT 0
-#define BCHP_M2MC_LIST_PACKET_HEADER_0_LAST_PKT_IND_NextPktValid 0
-#define BCHP_M2MC_LIST_PACKET_HEADER_0_LAST_PKT_IND_NextPktInvalid 1
-
-/***************************************************************************
- *LIST_PACKET_HEADER_1 - Linked-List Packet Header Word 1
- ***************************************************************************/
-/* M2MC :: LIST_PACKET_HEADER_1 :: reserved0 [31:15] */
-#define BCHP_M2MC_LIST_PACKET_HEADER_1_reserved0_MASK 0xffff8000
-#define BCHP_M2MC_LIST_PACKET_HEADER_1_reserved0_SHIFT 15
-
-/* M2MC :: LIST_PACKET_HEADER_1 :: SRC_FEEDER_GRP_CNTRL [14:14] */
-#define BCHP_M2MC_LIST_PACKET_HEADER_1_SRC_FEEDER_GRP_CNTRL_MASK 0x00004000
-#define BCHP_M2MC_LIST_PACKET_HEADER_1_SRC_FEEDER_GRP_CNTRL_SHIFT 14
-#define BCHP_M2MC_LIST_PACKET_HEADER_1_SRC_FEEDER_GRP_CNTRL_GRP_ENABLE 1
-#define BCHP_M2MC_LIST_PACKET_HEADER_1_SRC_FEEDER_GRP_CNTRL_GRP_DISABLE 0
-
-/* M2MC :: LIST_PACKET_HEADER_1 :: DST_FEEDER_GRP_CNTRL [13:13] */
-#define BCHP_M2MC_LIST_PACKET_HEADER_1_DST_FEEDER_GRP_CNTRL_MASK 0x00002000
-#define BCHP_M2MC_LIST_PACKET_HEADER_1_DST_FEEDER_GRP_CNTRL_SHIFT 13
-#define BCHP_M2MC_LIST_PACKET_HEADER_1_DST_FEEDER_GRP_CNTRL_GRP_ENABLE 1
-#define BCHP_M2MC_LIST_PACKET_HEADER_1_DST_FEEDER_GRP_CNTRL_GRP_DISABLE 0
-
-/* M2MC :: LIST_PACKET_HEADER_1 :: OUTPUT_FEEDER_GRP_CNTRL [12:12] */
-#define BCHP_M2MC_LIST_PACKET_HEADER_1_OUTPUT_FEEDER_GRP_CNTRL_MASK 0x00001000
-#define BCHP_M2MC_LIST_PACKET_HEADER_1_OUTPUT_FEEDER_GRP_CNTRL_SHIFT 12
-#define BCHP_M2MC_LIST_PACKET_HEADER_1_OUTPUT_FEEDER_GRP_CNTRL_GRP_ENABLE 1
-#define BCHP_M2MC_LIST_PACKET_HEADER_1_OUTPUT_FEEDER_GRP_CNTRL_GRP_DISABLE 0
-
-/* M2MC :: LIST_PACKET_HEADER_1 :: BLIT_GRP_CNTRL [11:11] */
-#define BCHP_M2MC_LIST_PACKET_HEADER_1_BLIT_GRP_CNTRL_MASK 0x00000800
-#define BCHP_M2MC_LIST_PACKET_HEADER_1_BLIT_GRP_CNTRL_SHIFT 11
-#define BCHP_M2MC_LIST_PACKET_HEADER_1_BLIT_GRP_CNTRL_GRP_ENABLE 1
-#define BCHP_M2MC_LIST_PACKET_HEADER_1_BLIT_GRP_CNTRL_GRP_DISABLE 0
-
-/* M2MC :: LIST_PACKET_HEADER_1 :: SCALE_PARAM_GRP_CNTRL [10:10] */
-#define BCHP_M2MC_LIST_PACKET_HEADER_1_SCALE_PARAM_GRP_CNTRL_MASK 0x00000400
-#define BCHP_M2MC_LIST_PACKET_HEADER_1_SCALE_PARAM_GRP_CNTRL_SHIFT 10
-#define BCHP_M2MC_LIST_PACKET_HEADER_1_SCALE_PARAM_GRP_CNTRL_GRP_ENABLE 1
-#define BCHP_M2MC_LIST_PACKET_HEADER_1_SCALE_PARAM_GRP_CNTRL_GRP_DISABLE 0
-
-/* M2MC :: LIST_PACKET_HEADER_1 :: BLEND_PARAM_GRP_CNTRL [09:09] */
-#define BCHP_M2MC_LIST_PACKET_HEADER_1_BLEND_PARAM_GRP_CNTRL_MASK 0x00000200
-#define BCHP_M2MC_LIST_PACKET_HEADER_1_BLEND_PARAM_GRP_CNTRL_SHIFT 9
-#define BCHP_M2MC_LIST_PACKET_HEADER_1_BLEND_PARAM_GRP_CNTRL_GRP_ENABLE 1
-#define BCHP_M2MC_LIST_PACKET_HEADER_1_BLEND_PARAM_GRP_CNTRL_GRP_DISABLE 0
-
-/* M2MC :: LIST_PACKET_HEADER_1 :: ROP_GRP_CNTRL [08:08] */
-#define BCHP_M2MC_LIST_PACKET_HEADER_1_ROP_GRP_CNTRL_MASK 0x00000100
-#define BCHP_M2MC_LIST_PACKET_HEADER_1_ROP_GRP_CNTRL_SHIFT 8
-#define BCHP_M2MC_LIST_PACKET_HEADER_1_ROP_GRP_CNTRL_GRP_ENABLE 1
-#define BCHP_M2MC_LIST_PACKET_HEADER_1_ROP_GRP_CNTRL_GRP_DISABLE 0
-
-/* M2MC :: LIST_PACKET_HEADER_1 :: SRC_COLOR_KEY_GRP_CNTRL [07:07] */
-#define BCHP_M2MC_LIST_PACKET_HEADER_1_SRC_COLOR_KEY_GRP_CNTRL_MASK 0x00000080
-#define BCHP_M2MC_LIST_PACKET_HEADER_1_SRC_COLOR_KEY_GRP_CNTRL_SHIFT 7
-#define BCHP_M2MC_LIST_PACKET_HEADER_1_SRC_COLOR_KEY_GRP_CNTRL_GRP_ENABLE 1
-#define BCHP_M2MC_LIST_PACKET_HEADER_1_SRC_COLOR_KEY_GRP_CNTRL_GRP_DISABLE 0
-
-/* M2MC :: LIST_PACKET_HEADER_1 :: DST_COLOR_KEY_GRP_CNTRL [06:06] */
-#define BCHP_M2MC_LIST_PACKET_HEADER_1_DST_COLOR_KEY_GRP_CNTRL_MASK 0x00000040
-#define BCHP_M2MC_LIST_PACKET_HEADER_1_DST_COLOR_KEY_GRP_CNTRL_SHIFT 6
-#define BCHP_M2MC_LIST_PACKET_HEADER_1_DST_COLOR_KEY_GRP_CNTRL_GRP_ENABLE 1
-#define BCHP_M2MC_LIST_PACKET_HEADER_1_DST_COLOR_KEY_GRP_CNTRL_GRP_DISABLE 0
-
-/* M2MC :: LIST_PACKET_HEADER_1 :: SCALE_COEF_GRP_CNTRL [05:05] */
-#define BCHP_M2MC_LIST_PACKET_HEADER_1_SCALE_COEF_GRP_CNTRL_MASK 0x00000020
-#define BCHP_M2MC_LIST_PACKET_HEADER_1_SCALE_COEF_GRP_CNTRL_SHIFT 5
-#define BCHP_M2MC_LIST_PACKET_HEADER_1_SCALE_COEF_GRP_CNTRL_GRP_ENABLE 1
-#define BCHP_M2MC_LIST_PACKET_HEADER_1_SCALE_COEF_GRP_CNTRL_GRP_DISABLE 0
-
-/* M2MC :: LIST_PACKET_HEADER_1 :: SRC_COLOR_MATRIX_GRP_CNTRL [04:04] */
-#define BCHP_M2MC_LIST_PACKET_HEADER_1_SRC_COLOR_MATRIX_GRP_CNTRL_MASK 0x00000010
-#define BCHP_M2MC_LIST_PACKET_HEADER_1_SRC_COLOR_MATRIX_GRP_CNTRL_SHIFT 4
-#define BCHP_M2MC_LIST_PACKET_HEADER_1_SRC_COLOR_MATRIX_GRP_CNTRL_GRP_ENABLE 1
-#define BCHP_M2MC_LIST_PACKET_HEADER_1_SRC_COLOR_MATRIX_GRP_CNTRL_GRP_DISABLE 0
-
-/* M2MC :: LIST_PACKET_HEADER_1 :: DST_COLOR_MATRIX_GRP_CNTRL [03:03] */
-#define BCHP_M2MC_LIST_PACKET_HEADER_1_DST_COLOR_MATRIX_GRP_CNTRL_MASK 0x00000008
-#define BCHP_M2MC_LIST_PACKET_HEADER_1_DST_COLOR_MATRIX_GRP_CNTRL_SHIFT 3
-#define BCHP_M2MC_LIST_PACKET_HEADER_1_DST_COLOR_MATRIX_GRP_CNTRL_GRP_ENABLE 1
-#define BCHP_M2MC_LIST_PACKET_HEADER_1_DST_COLOR_MATRIX_GRP_CNTRL_GRP_DISABLE 0
-
-/* M2MC :: LIST_PACKET_HEADER_1 :: OUTPUT_COLOR_MATRIX_GRP_CNTRL [02:02] */
-#define BCHP_M2MC_LIST_PACKET_HEADER_1_OUTPUT_COLOR_MATRIX_GRP_CNTRL_MASK 0x00000004
-#define BCHP_M2MC_LIST_PACKET_HEADER_1_OUTPUT_COLOR_MATRIX_GRP_CNTRL_SHIFT 2
-#define BCHP_M2MC_LIST_PACKET_HEADER_1_OUTPUT_COLOR_MATRIX_GRP_CNTRL_GRP_ENABLE 1
-#define BCHP_M2MC_LIST_PACKET_HEADER_1_OUTPUT_COLOR_MATRIX_GRP_CNTRL_GRP_DISABLE 0
-
-/* M2MC :: LIST_PACKET_HEADER_1 :: SRC_CLUT_GRP_CNTRL [01:01] */
-#define BCHP_M2MC_LIST_PACKET_HEADER_1_SRC_CLUT_GRP_CNTRL_MASK 0x00000002
-#define BCHP_M2MC_LIST_PACKET_HEADER_1_SRC_CLUT_GRP_CNTRL_SHIFT 1
-#define BCHP_M2MC_LIST_PACKET_HEADER_1_SRC_CLUT_GRP_CNTRL_GRP_ENABLE 1
-#define BCHP_M2MC_LIST_PACKET_HEADER_1_SRC_CLUT_GRP_CNTRL_GRP_DISABLE 0
-
-/* M2MC :: LIST_PACKET_HEADER_1 :: DST_CLUT_GRP_CNTRL [00:00] */
-#define BCHP_M2MC_LIST_PACKET_HEADER_1_DST_CLUT_GRP_CNTRL_MASK 0x00000001
-#define BCHP_M2MC_LIST_PACKET_HEADER_1_DST_CLUT_GRP_CNTRL_SHIFT 0
-#define BCHP_M2MC_LIST_PACKET_HEADER_1_DST_CLUT_GRP_CNTRL_GRP_ENABLE 1
-#define BCHP_M2MC_LIST_PACKET_HEADER_1_DST_CLUT_GRP_CNTRL_GRP_DISABLE 0
-
-/***************************************************************************
- *LIST_PKT_00_SRC_FEEDER_N - Linked-List Packet Word N for group SRC_FEEDER
- ***************************************************************************/
-/* M2MC :: LIST_PKT_00_SRC_FEEDER_N :: REGISTER_CONTENTS [31:00] */
-#define BCHP_M2MC_LIST_PKT_00_SRC_FEEDER_N_REGISTER_CONTENTS_MASK 0xffffffff
-#define BCHP_M2MC_LIST_PKT_00_SRC_FEEDER_N_REGISTER_CONTENTS_SHIFT 0
-
-/***************************************************************************
- *LIST_PKT_01_DST_FEEDER_N - Linked-List Packet Word N for group DST_FEEDER
- ***************************************************************************/
-/* M2MC :: LIST_PKT_01_DST_FEEDER_N :: REGISTER_CONTENTS [31:00] */
-#define BCHP_M2MC_LIST_PKT_01_DST_FEEDER_N_REGISTER_CONTENTS_MASK 0xffffffff
-#define BCHP_M2MC_LIST_PKT_01_DST_FEEDER_N_REGISTER_CONTENTS_SHIFT 0
-
-/***************************************************************************
- *LIST_PKT_02_OUTPUT_FEEDER_N - Linked-List Packet Word N for group OUTPUT_FEEDER
- ***************************************************************************/
-/* M2MC :: LIST_PKT_02_OUTPUT_FEEDER_N :: REGISTER_CONTENTS [31:00] */
-#define BCHP_M2MC_LIST_PKT_02_OUTPUT_FEEDER_N_REGISTER_CONTENTS_MASK 0xffffffff
-#define BCHP_M2MC_LIST_PKT_02_OUTPUT_FEEDER_N_REGISTER_CONTENTS_SHIFT 0
-
-/***************************************************************************
- *LIST_PKT_03_BLIT_N - Linked-List Packet Word N for group BLIT
- ***************************************************************************/
-/* M2MC :: LIST_PKT_03_BLIT_N :: REGISTER_CONTENTS [31:00] */
-#define BCHP_M2MC_LIST_PKT_03_BLIT_N_REGISTER_CONTENTS_MASK 0xffffffff
-#define BCHP_M2MC_LIST_PKT_03_BLIT_N_REGISTER_CONTENTS_SHIFT 0
-
-/***************************************************************************
- *LIST_PKT_04_SCALE_PARAM_N - Linked-List Packet Word N for group SCALE_PARAM
- ***************************************************************************/
-/* M2MC :: LIST_PKT_04_SCALE_PARAM_N :: REGISTER_CONTENTS [31:00] */
-#define BCHP_M2MC_LIST_PKT_04_SCALE_PARAM_N_REGISTER_CONTENTS_MASK 0xffffffff
-#define BCHP_M2MC_LIST_PKT_04_SCALE_PARAM_N_REGISTER_CONTENTS_SHIFT 0
-
-/***************************************************************************
- *LIST_PKT_05_BLEND_PARAM_N - Linked-List Packet Word N for group BLEND_PARAM
- ***************************************************************************/
-/* M2MC :: LIST_PKT_05_BLEND_PARAM_N :: REGISTER_CONTENTS [31:00] */
-#define BCHP_M2MC_LIST_PKT_05_BLEND_PARAM_N_REGISTER_CONTENTS_MASK 0xffffffff
-#define BCHP_M2MC_LIST_PKT_05_BLEND_PARAM_N_REGISTER_CONTENTS_SHIFT 0
-
-/***************************************************************************
- *LIST_PKT_06_ROP_N - Linked-List Packet Word N for group ROP
- ***************************************************************************/
-/* M2MC :: LIST_PKT_06_ROP_N :: REGISTER_CONTENTS [31:00] */
-#define BCHP_M2MC_LIST_PKT_06_ROP_N_REGISTER_CONTENTS_MASK 0xffffffff
-#define BCHP_M2MC_LIST_PKT_06_ROP_N_REGISTER_CONTENTS_SHIFT 0
-
-/***************************************************************************
- *LIST_PKT_07_SRC_COLOR_KEY_N - Linked-List Packet Word N for group SRC_COLOR_KEY
- ***************************************************************************/
-/* M2MC :: LIST_PKT_07_SRC_COLOR_KEY_N :: REGISTER_CONTENTS [31:00] */
-#define BCHP_M2MC_LIST_PKT_07_SRC_COLOR_KEY_N_REGISTER_CONTENTS_MASK 0xffffffff
-#define BCHP_M2MC_LIST_PKT_07_SRC_COLOR_KEY_N_REGISTER_CONTENTS_SHIFT 0
-
-/***************************************************************************
- *LIST_PKT_08_DST_COLOR_KEY_N - Linked-List Packet Word N for group DST_COLOR_KEY
- ***************************************************************************/
-/* M2MC :: LIST_PKT_08_DST_COLOR_KEY_N :: REGISTER_CONTENTS [31:00] */
-#define BCHP_M2MC_LIST_PKT_08_DST_COLOR_KEY_N_REGISTER_CONTENTS_MASK 0xffffffff
-#define BCHP_M2MC_LIST_PKT_08_DST_COLOR_KEY_N_REGISTER_CONTENTS_SHIFT 0
-
-/***************************************************************************
- *LIST_PKT_09_SCALE_COEF_N - Linked-List Packet Word N for group SCALE_COEF
- ***************************************************************************/
-/* M2MC :: LIST_PKT_09_SCALE_COEF_N :: REGISTER_CONTENTS [31:00] */
-#define BCHP_M2MC_LIST_PKT_09_SCALE_COEF_N_REGISTER_CONTENTS_MASK 0xffffffff
-#define BCHP_M2MC_LIST_PKT_09_SCALE_COEF_N_REGISTER_CONTENTS_SHIFT 0
-
-/***************************************************************************
- *LIST_PKT_10_SRC_COLOR_MATRIX_N - Linked-List Packet Word N for group SRC_COLOR_MATRIX
- ***************************************************************************/
-/* M2MC :: LIST_PKT_10_SRC_COLOR_MATRIX_N :: REGISTER_CONTENTS [31:00] */
-#define BCHP_M2MC_LIST_PKT_10_SRC_COLOR_MATRIX_N_REGISTER_CONTENTS_MASK 0xffffffff
-#define BCHP_M2MC_LIST_PKT_10_SRC_COLOR_MATRIX_N_REGISTER_CONTENTS_SHIFT 0
-
-/***************************************************************************
- *LIST_PKT_11_SRC_CLUT - Linked-List Packet Word for group SRC_CLUT
- ***************************************************************************/
-/* M2MC :: LIST_PKT_11_SRC_CLUT :: reserved0 [31:29] */
-#define BCHP_M2MC_LIST_PKT_11_SRC_CLUT_reserved0_MASK 0xe0000000
-#define BCHP_M2MC_LIST_PKT_11_SRC_CLUT_reserved0_SHIFT 29
-
-/* M2MC :: LIST_PKT_11_SRC_CLUT :: REGISTER_CONTENTS [28:00] */
-#define BCHP_M2MC_LIST_PKT_11_SRC_CLUT_REGISTER_CONTENTS_MASK 0x1fffffff
-#define BCHP_M2MC_LIST_PKT_11_SRC_CLUT_REGISTER_CONTENTS_SHIFT 0
-
-/***************************************************************************
- *PCIE_DMA
- ***************************************************************************/
-/***************************************************************************
- *DESC_WORD0 - PCIE DMA Descriptor Word 0
- ***************************************************************************/
-/* PCIE_DMA :: DESC_WORD0 :: MEMORY_ADDRESS [31:00] */
-#define BCHP_PCIE_DMA_DESC_WORD0_MEMORY_ADDRESS_MASK 0xffffffff
-#define BCHP_PCIE_DMA_DESC_WORD0_MEMORY_ADDRESS_SHIFT 0
-
-/***************************************************************************
- *DESC_WORD1 - PCIE DMA Descriptor Word 1
- ***************************************************************************/
-/* PCIE_DMA :: DESC_WORD1 :: PCIE_ADDRESS_LO [31:00] */
-#define BCHP_PCIE_DMA_DESC_WORD1_PCIE_ADDRESS_LO_MASK 0xffffffff
-#define BCHP_PCIE_DMA_DESC_WORD1_PCIE_ADDRESS_LO_SHIFT 0
-
-/***************************************************************************
- *DESC_WORD2 - PCIE DMA Descriptor Word 2
- ***************************************************************************/
-/* PCIE_DMA :: DESC_WORD2 :: PCIE_ADDRESS_HI [31:00] */
-#define BCHP_PCIE_DMA_DESC_WORD2_PCIE_ADDRESS_HI_MASK 0xffffffff
-#define BCHP_PCIE_DMA_DESC_WORD2_PCIE_ADDRESS_HI_SHIFT 0
-
-/***************************************************************************
- *DESC_WORD3 - PCIE DMA Descriptor Word 3
- ***************************************************************************/
-/* PCIE_DMA :: DESC_WORD3 :: INTERRUPT_ENABLE [31:31] */
-#define BCHP_PCIE_DMA_DESC_WORD3_INTERRUPT_ENABLE_MASK 0x80000000
-#define BCHP_PCIE_DMA_DESC_WORD3_INTERRUPT_ENABLE_SHIFT 31
-
-/* PCIE_DMA :: DESC_WORD3 :: reserved0 [30:25] */
-#define BCHP_PCIE_DMA_DESC_WORD3_reserved0_MASK 0x7e000000
-#define BCHP_PCIE_DMA_DESC_WORD3_reserved0_SHIFT 25
-
-/* PCIE_DMA :: DESC_WORD3 :: DMA_TRANSFER_SIZE [24:00] */
-#define BCHP_PCIE_DMA_DESC_WORD3_DMA_TRANSFER_SIZE_MASK 0x01ffffff
-#define BCHP_PCIE_DMA_DESC_WORD3_DMA_TRANSFER_SIZE_SHIFT 0
-
-/***************************************************************************
- *DESC_WORD4 - PCIE DMA Descriptor Word 4
- ***************************************************************************/
-/* PCIE_DMA :: DESC_WORD4 :: LAST_RECORD_INDICATOR [31:31] */
-#define BCHP_PCIE_DMA_DESC_WORD4_LAST_RECORD_INDICATOR_MASK 0x80000000
-#define BCHP_PCIE_DMA_DESC_WORD4_LAST_RECORD_INDICATOR_SHIFT 31
-
-/* PCIE_DMA :: DESC_WORD4 :: DMA_DIRECTION [30:30] */
-#define BCHP_PCIE_DMA_DESC_WORD4_DMA_DIRECTION_MASK 0x40000000
-#define BCHP_PCIE_DMA_DESC_WORD4_DMA_DIRECTION_SHIFT 30
-#define BCHP_PCIE_DMA_DESC_WORD4_DMA_DIRECTION_PCIE_TO_MEMORY 1
-#define BCHP_PCIE_DMA_DESC_WORD4_DMA_DIRECTION_MEMORY_TO_PCIE 0
-
-/* PCIE_DMA :: DESC_WORD4 :: reserved0 [29:03] */
-#define BCHP_PCIE_DMA_DESC_WORD4_reserved0_MASK 0x3ffffff8
-#define BCHP_PCIE_DMA_DESC_WORD4_reserved0_SHIFT 3
-
-/* PCIE_DMA :: DESC_WORD4 :: DESC_CONTIGUOUS [02:02] */
-#define BCHP_PCIE_DMA_DESC_WORD4_DESC_CONTIGUOUS_MASK 0x00000004
-#define BCHP_PCIE_DMA_DESC_WORD4_DESC_CONTIGUOUS_SHIFT 2
-
-/* PCIE_DMA :: DESC_WORD4 :: ENDIAN_XLATE_MODE [01:00] */
-#define BCHP_PCIE_DMA_DESC_WORD4_ENDIAN_XLATE_MODE_MASK 0x00000003
-#define BCHP_PCIE_DMA_DESC_WORD4_ENDIAN_XLATE_MODE_SHIFT 0
-#define BCHP_PCIE_DMA_DESC_WORD4_ENDIAN_XLATE_MODE_NO_SWAP 0
-#define BCHP_PCIE_DMA_DESC_WORD4_ENDIAN_XLATE_MODE_SWAP_16_IN_32 1
-#define BCHP_PCIE_DMA_DESC_WORD4_ENDIAN_XLATE_MODE_SWAP_32 2
-#define BCHP_PCIE_DMA_DESC_WORD4_ENDIAN_XLATE_MODE_reserved 3
-
-/***************************************************************************
- *DESC_WORD5 - PCIE DMA Descriptor Word 5
- ***************************************************************************/
-/* PCIE_DMA :: DESC_WORD5 :: NEXT_DESC_ADDRESS_LO [31:05] */
-#define BCHP_PCIE_DMA_DESC_WORD5_NEXT_DESC_ADDRESS_LO_MASK 0xffffffe0
-#define BCHP_PCIE_DMA_DESC_WORD5_NEXT_DESC_ADDRESS_LO_SHIFT 5
-
-/* PCIE_DMA :: DESC_WORD5 :: reserved0 [04:00] */
-#define BCHP_PCIE_DMA_DESC_WORD5_reserved0_MASK 0x0000001f
-#define BCHP_PCIE_DMA_DESC_WORD5_reserved0_SHIFT 0
-
-/***************************************************************************
- *DESC_WORD6 - PCIE DMA Descriptor Word 6
- ***************************************************************************/
-/* PCIE_DMA :: DESC_WORD6 :: NEXT_DESC_ADDRESS_HI [31:00] */
-#define BCHP_PCIE_DMA_DESC_WORD6_NEXT_DESC_ADDRESS_HI_MASK 0xffffffff
-#define BCHP_PCIE_DMA_DESC_WORD6_NEXT_DESC_ADDRESS_HI_SHIFT 0
-
-/***************************************************************************
- *DESC_WORD7 - PCIE DMA Descriptor Word 7
- ***************************************************************************/
-/* PCIE_DMA :: DESC_WORD7 :: reserved0 [31:08] */
-#define BCHP_PCIE_DMA_DESC_WORD7_reserved0_MASK 0xffffff00
-#define BCHP_PCIE_DMA_DESC_WORD7_reserved0_SHIFT 8
-
-/* PCIE_DMA :: DESC_WORD7 :: MEMORY_ADDRESS_HI [07:00] */
-#define BCHP_PCIE_DMA_DESC_WORD7_MEMORY_ADDRESS_HI_MASK 0x000000ff
-#define BCHP_PCIE_DMA_DESC_WORD7_MEMORY_ADDRESS_HI_SHIFT 0
-
-/***************************************************************************
- *RAAGA_REGSET_DSP_CFG
- ***************************************************************************/
-/***************************************************************************
- *AC3_UPS_WORD_00 - AC3 User Parameters Structure Word 0 - DYNRNGSCALEHI
- ***************************************************************************/
-/* RAAGA_REGSET_DSP_CFG :: AC3_UPS_WORD_00 :: DYNRNGSCALEHI [15:00] */
-#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_00_DYNRNGSCALEHI_MASK 0xffff
-#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_00_DYNRNGSCALEHI_SHIFT 0
-#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_00_DYNRNGSCALEHI_No_compression 0
-#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_00_DYNRNGSCALEHI_Full_compression 32767
-
-/***************************************************************************
- *AC3_UPS_WORD_01 - AC3 User Parameters Structure Word 1 - DYNRNGSCALELOW
- ***************************************************************************/
-/* RAAGA_REGSET_DSP_CFG :: AC3_UPS_WORD_01 :: DYNRNGSCALELOW [15:00] */
-#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_01_DYNRNGSCALELOW_MASK 0xffff
-#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_01_DYNRNGSCALELOW_SHIFT 0
-#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_01_DYNRNGSCALELOW_No_compression 0
-#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_01_DYNRNGSCALELOW_Full_compression 32767
-
-/***************************************************************************
- *AC3_UPS_WORD_02 - AC3 User Parameters Structure Word 2 - PCMSCALEFAC
- ***************************************************************************/
-/* RAAGA_REGSET_DSP_CFG :: AC3_UPS_WORD_02 :: PCMSCALEFAC [15:00] */
-#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_02_PCMSCALEFAC_MASK 0xffff
-#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_02_PCMSCALEFAC_SHIFT 0
-#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_02_PCMSCALEFAC_Full_scale 32767
-#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_02_PCMSCALEFAC_Mute 0
-
-/***************************************************************************
- *AC3_UPS_WORD_03 - AC3 User Parameters Structure Word 3 - COMPMODE
- ***************************************************************************/
-/* RAAGA_REGSET_DSP_CFG :: AC3_UPS_WORD_03 :: COMPMODE [15:00] */
-#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_03_COMPMODE_MASK 0xffff
-#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_03_COMPMODE_SHIFT 0
-#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_03_COMPMODE_Comp_custom_a 0
-#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_03_COMPMODE_Comp_custom_d 1
-#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_03_COMPMODE_Comp_line 2
-#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_03_COMPMODE_Comp_rf 3
-
-/***************************************************************************
- *AC3_UPS_WORD_04 - AC3 User Parameters Structure Word 4 - DUALMONOMODE
- ***************************************************************************/
-/* RAAGA_REGSET_DSP_CFG :: AC3_UPS_WORD_04 :: DUALMONOMODE [15:00] */
-#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_04_DUALMONOMODE_MASK 0xffff
-#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_04_DUALMONOMODE_SHIFT 0
-#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_04_DUALMONOMODE_Pass_through 0
-#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_04_DUALMONOMODE_Left_mono 1
-#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_04_DUALMONOMODE_Right_mono 2
-#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_04_DUALMONOMODE_True_mono 3
-
-/***************************************************************************
- *AC3_UPS_WORD_05 - AC3 User Parameters Structure Word 5 - OUTPUTMODE
- ***************************************************************************/
-/* RAAGA_REGSET_DSP_CFG :: AC3_UPS_WORD_05 :: OUTPUTMODE [15:00] */
-#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_05_OUTPUTMODE_MASK 0xffff
-#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_05_OUTPUTMODE_SHIFT 0
-#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_05_OUTPUTMODE_Mode11 0
-#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_05_OUTPUTMODE_Mode10 1
-#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_05_OUTPUTMODE_Mode20 2
-#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_05_OUTPUTMODE_Mode30 3
-#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_05_OUTPUTMODE_Mode21 4
-#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_05_OUTPUTMODE_Mode31 5
-#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_05_OUTPUTMODE_Mode22 6
-#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_05_OUTPUTMODE_Mode32 7
-
-/***************************************************************************
- *AC3_UPS_WORD_06 - AC3 User Parameters Structure Word 6 - OUTLFEON
- ***************************************************************************/
-/* RAAGA_REGSET_DSP_CFG :: AC3_UPS_WORD_06 :: OUTLFEON [15:00] */
-#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_06_OUTLFEON_MASK 0xffff
-#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_06_OUTLFEON_SHIFT 0
-#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_06_OUTLFEON_Off 0
-#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_06_OUTLFEON_On 1
-
-/***************************************************************************
- *AC3_UPS_WORD_07 - AC3 User Parameters Structure Word 7 - KCAPABLEMODE
- ***************************************************************************/
-/* RAAGA_REGSET_DSP_CFG :: AC3_UPS_WORD_07 :: KCAPABLEMODE [15:00] */
-#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_07_KCAPABLEMODE_MASK 0xffff
-#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_07_KCAPABLEMODE_SHIFT 0
-#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_07_KCAPABLEMODE_No_vocal_channels 0
-#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_07_KCAPABLEMODE_Vocal_channel_V1 1
-#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_07_KCAPABLEMODE_Vocal_channel_V2 2
-#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_07_KCAPABLEMODE_Both_vocal_channels 3
-
-/***************************************************************************
- *AC3_UPS_WORD_08 - AC3 User Parameters Structure Word 8 - KARAOKE_PARAMETER_FLAG
- ***************************************************************************/
-/* RAAGA_REGSET_DSP_CFG :: AC3_UPS_WORD_08 :: KARAOKE_PARAMETER_FLAG [15:00] */
-#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_08_KARAOKE_PARAMETER_FLAG_MASK 0xffff
-#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_08_KARAOKE_PARAMETER_FLAG_SHIFT 0
-#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_08_KARAOKE_PARAMETER_FLAG_Off 0
-#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_08_KARAOKE_PARAMETER_FLAG_On 1
-
-/***************************************************************************
- *AC3_UPS_WORD_09 - AC3 User Parameters Structure Word 9 - KARAOKE_V1_LEVEL
- ***************************************************************************/
-/* RAAGA_REGSET_DSP_CFG :: AC3_UPS_WORD_09 :: KARAOKE_V1_LEVEL [15:00] */
-#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_09_KARAOKE_V1_LEVEL_MASK 0xffff
-#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_09_KARAOKE_V1_LEVEL_SHIFT 0
-#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_09_KARAOKE_V1_LEVEL_Full_scale 32767
-#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_09_KARAOKE_V1_LEVEL_Mute 0
-
-/***************************************************************************
- *AC3_UPS_WORD_10 - AC3 User Parameters Structure Word 10 - KARAOKE_V1_PAN
- ***************************************************************************/
-/* RAAGA_REGSET_DSP_CFG :: AC3_UPS_WORD_10 :: KARAOKE_V1_PAN [15:00] */
-#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_10_KARAOKE_V1_PAN_MASK 0xffff
-#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_10_KARAOKE_V1_PAN_SHIFT 0
-#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_10_KARAOKE_V1_PAN_Hard_left 32767
-#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_10_KARAOKE_V1_PAN_Middle 0
-#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_10_KARAOKE_V1_PAN_Hard_right 32768
-
-/***************************************************************************
- *AC3_UPS_WORD_11 - AC3 User Parameters Structure Word 11 - KARAOKE_V2_LEVEL
- ***************************************************************************/
-/* RAAGA_REGSET_DSP_CFG :: AC3_UPS_WORD_11 :: KARAOKE_V2_LEVEL [15:00] */
-#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_11_KARAOKE_V2_LEVEL_MASK 0xffff
-#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_11_KARAOKE_V2_LEVEL_SHIFT 0
-#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_11_KARAOKE_V2_LEVEL_Full_scale 32767
-#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_11_KARAOKE_V2_LEVEL_Mute 0
-
-/***************************************************************************
- *AC3_UPS_WORD_12 - AC3 User Parameters Structure Word 12 - KARAOKE_V2_PAN
- ***************************************************************************/
-/* RAAGA_REGSET_DSP_CFG :: AC3_UPS_WORD_12 :: KARAOKE_V2_PAN [15:00] */
-#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_12_KARAOKE_V2_PAN_MASK 0xffff
-#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_12_KARAOKE_V2_PAN_SHIFT 0
-#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_12_KARAOKE_V2_PAN_Hard_left 32767
-#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_12_KARAOKE_V2_PAN_Middle 0
-#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_12_KARAOKE_V2_PAN_Hard_right 32768
-
-/***************************************************************************
- *AC3_UPS_WORD_13 - AC3 User Parameters Structure Word 13 - KARAOKE_GM_LEVEL
- ***************************************************************************/
-/* RAAGA_REGSET_DSP_CFG :: AC3_UPS_WORD_13 :: KARAOKE_GM_LEVEL [15:00] */
-#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_13_KARAOKE_GM_LEVEL_MASK 0xffff
-#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_13_KARAOKE_GM_LEVEL_SHIFT 0
-#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_13_KARAOKE_GM_LEVEL_Full_scale 32767
-#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_13_KARAOKE_GM_LEVEL_Mute 0
-
-/***************************************************************************
- *AC3_UPS_WORD_14 - AC3 User Parameters Structure Word 14 - KARAOKE_GM_PAN
- ***************************************************************************/
-/* RAAGA_REGSET_DSP_CFG :: AC3_UPS_WORD_14 :: KARAOKE_GM_PAN [15:00] */
-#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_14_KARAOKE_GM_PAN_MASK 0xffff
-#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_14_KARAOKE_GM_PAN_SHIFT 0
-#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_14_KARAOKE_GM_PAN_Hard_left 32767
-#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_14_KARAOKE_GM_PAN_Middle 0
-#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_14_KARAOKE_GM_PAN_Hard_right 32768
-
-/***************************************************************************
- *AC3_UPS_WORD_15 - AC3 User Parameters Structure Word 15 - STEREO_MOD
- ***************************************************************************/
-/* RAAGA_REGSET_DSP_CFG :: AC3_UPS_WORD_15 :: STEREO_MOD [15:00] */
-#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_15_STEREO_MOD_MASK 0xffff
-#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_15_STEREO_MOD_SHIFT 0
-#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_15_STEREO_MOD_Auto 0
-#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_15_STEREO_MOD_LtRt 1
-#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_15_STEREO_MOD_LoRo 2
-
-/***************************************************************************
- *AC3_UPS_WORD_16 - AC3 User Parameters Structure Word 16 - USER_DOWNMIX_FLAG
- ***************************************************************************/
-/* RAAGA_REGSET_DSP_CFG :: AC3_UPS_WORD_16 :: USER_DOWNMIX_FLAG [15:00] */
-#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_16_USER_DOWNMIX_FLAG_MASK 0xffff
-#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_16_USER_DOWNMIX_FLAG_SHIFT 0
-#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_16_USER_DOWNMIX_FLAG_Off 0
-#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_16_USER_DOWNMIX_FLAG_On 1
-
-/***************************************************************************
- *AC3_UPS_WORD_17_TO_52 - AC3 User Parameters Structure Word 17 to 52 - DRAM_USER_DEFINED_DNMX_COEFFS
- ***************************************************************************/
-/* RAAGA_REGSET_DSP_CFG :: AC3_UPS_WORD_17_TO_52 :: DRAM_USER_DEFINED_DNMX_COEFFS [15:00] */
-#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_17_TO_52_DRAM_USER_DEFINED_DNMX_COEFFS_MASK 0xffff
-#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_17_TO_52_DRAM_USER_DEFINED_DNMX_COEFFS_SHIFT 0
-#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_17_TO_52_DRAM_USER_DEFINED_DNMX_COEFFS_Full_scale 32767
-#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_17_TO_52_DRAM_USER_DEFINED_DNMX_COEFFS_Mute 0
-
-/***************************************************************************
- *AC3_UPS_WORD_53 - AC3 User Parameters Structure Word 53 - DUMMY
- ***************************************************************************/
-/* RAAGA_REGSET_DSP_CFG :: AC3_UPS_WORD_53 :: DUMMY [15:00] */
-#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_53_DUMMY_MASK 0xffff
-#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_53_DUMMY_SHIFT 0
-
-/***************************************************************************
- *AC3_PLUS_UPS_WORD_00 - AC3 Plus User Parameters Structure Word 0 - COMPMODE
- ***************************************************************************/
-/* RAAGA_REGSET_DSP_CFG :: AC3_PLUS_UPS_WORD_00 :: COMPMODE [31:00] */
-#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_00_COMPMODE_MASK 0xffffffff
-#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_00_COMPMODE_SHIFT 0
-
-/***************************************************************************
- *AC3_PLUS_UPS_WORD_01 - AC3 Plus User Parameters Structure Word 1 - PCMSCALE
- ***************************************************************************/
-/* RAAGA_REGSET_DSP_CFG :: AC3_PLUS_UPS_WORD_01 :: PCMSCALE [31:00] */
-#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_01_PCMSCALE_MASK 0xffffffff
-#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_01_PCMSCALE_SHIFT 0
-#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_01_PCMSCALE_Full_scale 2147483647
-#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_01_PCMSCALE_Mute 0
-
-/***************************************************************************
- *AC3_PLUS_UPS_WORD_02 - AC3 Plus User Parameters Structure Word 2 - DYNSCALEHIGH
- ***************************************************************************/
-/* RAAGA_REGSET_DSP_CFG :: AC3_PLUS_UPS_WORD_02 :: DYNSCALEHIGH [31:00] */
-#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_02_DYNSCALEHIGH_MASK 0xffffffff
-#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_02_DYNSCALEHIGH_SHIFT 0
-
-/***************************************************************************
- *AC3_PLUS_UPS_WORD_03 - AC3 Plus User Parameters Structure Word 3 - DYNSCALELOW
- ***************************************************************************/
-/* RAAGA_REGSET_DSP_CFG :: AC3_PLUS_UPS_WORD_03 :: DYNSCALELOW [31:00] */
-#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_03_DYNSCALELOW_MASK 0xffffffff
-#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_03_DYNSCALELOW_SHIFT 0
-
-/***************************************************************************
- *AC3_PLUS_UPS_WORD_04 - AC3 Plus User Parameters Structure Word 4 - OUTLFE
- ***************************************************************************/
-/* RAAGA_REGSET_DSP_CFG :: AC3_PLUS_UPS_WORD_04 :: OUTLFE [31:00] */
-#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_04_OUTLFE_MASK 0xffffffff
-#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_04_OUTLFE_SHIFT 0
-
-/***************************************************************************
- *AC3_PLUS_UPS_WORD_05 - AC3 Plus User Parameters Structure Word 5 - OUTMODE
- ***************************************************************************/
-/* RAAGA_REGSET_DSP_CFG :: AC3_PLUS_UPS_WORD_05 :: OUTMODE [31:00] */
-#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_05_OUTMODE_MASK 0xffffffff
-#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_05_OUTMODE_SHIFT 0
-
-/***************************************************************************
- *AC3_PLUS_UPS_WORD_06 - AC3 Plus User Parameters Structure Word 6 - STEREOMODE
- ***************************************************************************/
-/* RAAGA_REGSET_DSP_CFG :: AC3_PLUS_UPS_WORD_06 :: STEREOMODE [31:00] */
-#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_06_STEREOMODE_MASK 0xffffffff
-#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_06_STEREOMODE_SHIFT 0
-
-/***************************************************************************
- *AC3_PLUS_UPS_WORD_07 - AC3 Plus User Parameters Structure Word 7 - DUALMODE
- ***************************************************************************/
-/* RAAGA_REGSET_DSP_CFG :: AC3_PLUS_UPS_WORD_07 :: DUALMODE [31:00] */
-#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_07_DUALMODE_MASK 0xffffffff
-#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_07_DUALMODE_SHIFT 0
-
-/***************************************************************************
- *AC3_PLUS_UPS_WORD_08 - AC3 Plus User Parameters Structure Word 8 - KMODE
- ***************************************************************************/
-/* RAAGA_REGSET_DSP_CFG :: AC3_PLUS_UPS_WORD_08 :: KMODE [31:00] */
-#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_08_KMODE_MASK 0xffffffff
-#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_08_KMODE_SHIFT 0
-#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_08_KMODE_NO_VOCALS 0
-#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_08_KMODE_GBL_VOCAL1 1
-#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_08_KMODE_GBL_VOCAL2 2
-#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_08_KMODE_GBL_BOTH_VOCALS 3
-
-/***************************************************************************
- *AC3_PLUS_UPS_WORD_09 - AC3 Plus User Parameters Structure Word 9 - EXTDNMIX_ENABLED
- ***************************************************************************/
-/* RAAGA_REGSET_DSP_CFG :: AC3_PLUS_UPS_WORD_09 :: EXTDNMIX_ENABLED [31:00] */
-#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_09_EXTDNMIX_ENABLED_MASK 0xffffffff
-#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_09_EXTDNMIX_ENABLED_SHIFT 0
-
-/***************************************************************************
- *AC3_PLUS_UPS_WORD_10_TO_45 - AC3 Plus User Parameters Structure Word 10 to 45 - EXTDNMIXTAB
- ***************************************************************************/
-/* RAAGA_REGSET_DSP_CFG :: AC3_PLUS_UPS_WORD_10_TO_45 :: EXTDNMIXTAB [31:00] */
-#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_10_TO_45_EXTDNMIXTAB_MASK 0xffffffff
-#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_10_TO_45_EXTDNMIXTAB_SHIFT 0
-#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_10_TO_45_EXTDNMIXTAB_Full_scale 2147483647
-#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_10_TO_45_EXTDNMIXTAB_Mute 0
-
-/***************************************************************************
- *AC3_PLUS_UPS_WORD_46 - AC3 Plus User Parameters Structure Word 46 - EXTKARAOKE_ENABLED
- ***************************************************************************/
-/* RAAGA_REGSET_DSP_CFG :: AC3_PLUS_UPS_WORD_46 :: EXTKARAOKE_ENABLED [31:00] */
-#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_46_EXTKARAOKE_ENABLED_MASK 0xffffffff
-#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_46_EXTKARAOKE_ENABLED_SHIFT 0
-
-/***************************************************************************
- *AC3_PLUS_UPS_WORD_47 - AC3 Plus User Parameters Structure Word 47 - EXT_V1_LEVEL
- ***************************************************************************/
-/* RAAGA_REGSET_DSP_CFG :: AC3_PLUS_UPS_WORD_47 :: EXT_V1_LEVEL [31:00] */
-#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_47_EXT_V1_LEVEL_MASK 0xffffffff
-#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_47_EXT_V1_LEVEL_SHIFT 0
-#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_47_EXT_V1_LEVEL_Full_scale 2147483647
-#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_47_EXT_V1_LEVEL_Mute 0
-
-/***************************************************************************
- *AC3_PLUS_UPS_WORD_48 - AC3 Plus User Parameters Structure Word 48 - EXT_V1_PAN
- ***************************************************************************/
-/* RAAGA_REGSET_DSP_CFG :: AC3_PLUS_UPS_WORD_48 :: EXT_V1_PAN [31:00] */
-#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_48_EXT_V1_PAN_MASK 0xffffffff
-#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_48_EXT_V1_PAN_SHIFT 0
-#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_48_EXT_V1_PAN_Hard_left 2147483647
-#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_48_EXT_V1_PAN_Middle 0
-#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_48_EXT_V1_PAN_Hard_right -2147483648
-
-/***************************************************************************
- *AC3_PLUS_UPS_WORD_49 - AC3 Plus User Parameters Structure Word 49 - EXT_V2_LEVEL
- ***************************************************************************/
-/* RAAGA_REGSET_DSP_CFG :: AC3_PLUS_UPS_WORD_49 :: EXT_V2_LEVEL [31:00] */
-#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_49_EXT_V2_LEVEL_MASK 0xffffffff
-#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_49_EXT_V2_LEVEL_SHIFT 0
-#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_49_EXT_V2_LEVEL_Full_scale 2147483647
-#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_49_EXT_V2_LEVEL_Mute 0
-
-/***************************************************************************
- *AC3_PLUS_UPS_WORD_50 - AC3 Plus User Parameters Structure Word 50 - EXT_V2_PAN
- ***************************************************************************/
-/* RAAGA_REGSET_DSP_CFG :: AC3_PLUS_UPS_WORD_50 :: EXT_V2_PAN [31:00] */
-#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_50_EXT_V2_PAN_MASK 0xffffffff
-#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_50_EXT_V2_PAN_SHIFT 0
-#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_50_EXT_V2_PAN_Hard_left 2147483647
-#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_50_EXT_V2_PAN_Middle 0
-#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_50_EXT_V2_PAN_Hard_right -2147483648
-
-/***************************************************************************
- *AC3_PLUS_UPS_WORD_51 - AC3 Plus User Parameters Structure Word 51 - EXT_GM_LEVEL
- ***************************************************************************/
-/* RAAGA_REGSET_DSP_CFG :: AC3_PLUS_UPS_WORD_51 :: EXT_GM_LEVEL [31:00] */
-#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_51_EXT_GM_LEVEL_MASK 0xffffffff
-#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_51_EXT_GM_LEVEL_SHIFT 0
-#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_51_EXT_GM_LEVEL_Full_scale 2147483647
-#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_51_EXT_GM_LEVEL_Mute 0
-
-/***************************************************************************
- *AC3_PLUS_UPS_WORD_52 - AC3 Plus User Parameters Structure Word 52 - EXT_GM_PAN
- ***************************************************************************/
-/* RAAGA_REGSET_DSP_CFG :: AC3_PLUS_UPS_WORD_52 :: EXT_GM_PAN [31:00] */
-#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_52_EXT_GM_PAN_MASK 0xffffffff
-#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_52_EXT_GM_PAN_SHIFT 0
-#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_52_EXT_GM_PAN_Hard_left 2147483647
-#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_52_EXT_GM_PAN_Middle 0
-#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_52_EXT_GM_PAN_Hard_right -2147483648
-
-/***************************************************************************
- *AAC_UPS_WORD_00 - AAC User Parameters Structure Word 0 - XPT_FORMAT
- ***************************************************************************/
-/* RAAGA_REGSET_DSP_CFG :: AAC_UPS_WORD_00 :: XPT_FORMAT [31:00] */
-#define BCHP_RAAGA_REGSET_DSP_CFG_AAC_UPS_WORD_00_XPT_FORMAT_MASK 0xffffffff
-#define BCHP_RAAGA_REGSET_DSP_CFG_AAC_UPS_WORD_00_XPT_FORMAT_SHIFT 0
-
-/***************************************************************************
- *AAC_UPS_WORD_01 - AAC User Parameters Structure Word 1 - DRC_GAIN_CONTROL_COMPRESS
- ***************************************************************************/
-/* RAAGA_REGSET_DSP_CFG :: AAC_UPS_WORD_01 :: DRC_GAIN_CONTROL_COMPRESS [31:00] */
-#define BCHP_RAAGA_REGSET_DSP_CFG_AAC_UPS_WORD_01_DRC_GAIN_CONTROL_COMPRESS_MASK 0xffffffff
-#define BCHP_RAAGA_REGSET_DSP_CFG_AAC_UPS_WORD_01_DRC_GAIN_CONTROL_COMPRESS_SHIFT 0
-
-/***************************************************************************
- *AAC_UPS_WORD_02 - AAC User Parameters Structure Word 2 - DRC_GAIN_CONTROL_BOOST
- ***************************************************************************/
-/* RAAGA_REGSET_DSP_CFG :: AAC_UPS_WORD_02 :: DRC_GAIN_CONTROL_BOOST [31:00] */
-#define BCHP_RAAGA_REGSET_DSP_CFG_AAC_UPS_WORD_02_DRC_GAIN_CONTROL_BOOST_MASK 0xffffffff
-#define BCHP_RAAGA_REGSET_DSP_CFG_AAC_UPS_WORD_02_DRC_GAIN_CONTROL_BOOST_SHIFT 0
-
-/***************************************************************************
- *AAC_UPS_WORD_03 - AAC User Parameters Structure Word 3 - DRC_TARGET_LEVEL
- ***************************************************************************/
-/* RAAGA_REGSET_DSP_CFG :: AAC_UPS_WORD_03 :: DRC_TARGET_LEVEL [31:00] */
-#define BCHP_RAAGA_REGSET_DSP_CFG_AAC_UPS_WORD_03_DRC_TARGET_LEVEL_MASK 0xffffffff
-#define BCHP_RAAGA_REGSET_DSP_CFG_AAC_UPS_WORD_03_DRC_TARGET_LEVEL_SHIFT 0
-
-/***************************************************************************
- *AAC_UPS_WORD_04 - AAC User Parameters Structure Word 4 - DOWNMIX_TYPE
- ***************************************************************************/
-/* RAAGA_REGSET_DSP_CFG :: AAC_UPS_WORD_04 :: DOWNMIX_TYPE [31:00] */
-#define BCHP_RAAGA_REGSET_DSP_CFG_AAC_UPS_WORD_04_DOWNMIX_TYPE_MASK 0xffffffff
-#define BCHP_RAAGA_REGSET_DSP_CFG_AAC_UPS_WORD_04_DOWNMIX_TYPE_SHIFT 0
-
-/***************************************************************************
- *AAC_UPS_WORD_05 - AAC User Parameters Structure Word 5 - OUTMODE
- ***************************************************************************/
-/* RAAGA_REGSET_DSP_CFG :: AAC_UPS_WORD_05 :: OUTMODE [31:00] */
-#define BCHP_RAAGA_REGSET_DSP_CFG_AAC_UPS_WORD_05_OUTMODE_MASK 0xffffffff
-#define BCHP_RAAGA_REGSET_DSP_CFG_AAC_UPS_WORD_05_OUTMODE_SHIFT 0
-#define BCHP_RAAGA_REGSET_DSP_CFG_AAC_UPS_WORD_05_OUTMODE_Stereo 2
-#define BCHP_RAAGA_REGSET_DSP_CFG_AAC_UPS_WORD_05_OUTMODE_Mono 1
-
-/***************************************************************************
- *AAC_UPS_WORD_06 - AAC User Parameters Structure Word 6 - DUALMODE
- ***************************************************************************/
-/* RAAGA_REGSET_DSP_CFG :: AAC_UPS_WORD_06 :: DUALMODE [31:00] */
-#define BCHP_RAAGA_REGSET_DSP_CFG_AAC_UPS_WORD_06_DUALMODE_MASK 0xffffffff
-#define BCHP_RAAGA_REGSET_DSP_CFG_AAC_UPS_WORD_06_DUALMODE_SHIFT 0
-#define BCHP_RAAGA_REGSET_DSP_CFG_AAC_UPS_WORD_06_DUALMODE_Left_mono 0
-#define BCHP_RAAGA_REGSET_DSP_CFG_AAC_UPS_WORD_06_DUALMODE_Right_mono 1
-#define BCHP_RAAGA_REGSET_DSP_CFG_AAC_UPS_WORD_06_DUALMODE_Dual_stereo 2
-#define BCHP_RAAGA_REGSET_DSP_CFG_AAC_UPS_WORD_06_DUALMODE_Dual_mixmono 3
-
-/***************************************************************************
- *DTS_CORE_UPS_WORD_00 - DTS Core User Parameters Structure Word 0 - OUTMODE
- ***************************************************************************/
-/* RAAGA_REGSET_DSP_CFG :: DTS_CORE_UPS_WORD_00 :: OUTMODE [31:00] */
-#define BCHP_RAAGA_REGSET_DSP_CFG_DTS_CORE_UPS_WORD_00_OUTMODE_MASK 0xffffffff
-#define BCHP_RAAGA_REGSET_DSP_CFG_DTS_CORE_UPS_WORD_00_OUTMODE_SHIFT 0
-#define BCHP_RAAGA_REGSET_DSP_CFG_DTS_CORE_UPS_WORD_00_OUTMODE_Stereo 0
-#define BCHP_RAAGA_REGSET_DSP_CFG_DTS_CORE_UPS_WORD_00_OUTMODE_Mono 1
-
-/***************************************************************************
- *DTS_CORE_UPS_WORD_01 - DTS Core User Parameters Structure Word 1 - OUTLFE
- ***************************************************************************/
-/* RAAGA_REGSET_DSP_CFG :: DTS_CORE_UPS_WORD_01 :: OUTLFE [31:00] */
-#define BCHP_RAAGA_REGSET_DSP_CFG_DTS_CORE_UPS_WORD_01_OUTLFE_MASK 0xffffffff
-#define BCHP_RAAGA_REGSET_DSP_CFG_DTS_CORE_UPS_WORD_01_OUTLFE_SHIFT 0
-
-/***************************************************************************
- *DTS_CORE_UPS_WORD_02 - DTS Core User Parameters Structure Word 2 - DUALMODE
- ***************************************************************************/
-/* RAAGA_REGSET_DSP_CFG :: DTS_CORE_UPS_WORD_02 :: DUALMODE [31:00] */
-#define BCHP_RAAGA_REGSET_DSP_CFG_DTS_CORE_UPS_WORD_02_DUALMODE_MASK 0xffffffff
-#define BCHP_RAAGA_REGSET_DSP_CFG_DTS_CORE_UPS_WORD_02_DUALMODE_SHIFT 0
-#define BCHP_RAAGA_REGSET_DSP_CFG_DTS_CORE_UPS_WORD_02_DUALMODE_Dual_stereo 0
-#define BCHP_RAAGA_REGSET_DSP_CFG_DTS_CORE_UPS_WORD_02_DUALMODE_Dual_leftmono 1
-#define BCHP_RAAGA_REGSET_DSP_CFG_DTS_CORE_UPS_WORD_02_DUALMODE_Dual_rghtmono 2
-#define BCHP_RAAGA_REGSET_DSP_CFG_DTS_CORE_UPS_WORD_02_DUALMODE_Dual_mixmono 3
-
-/***************************************************************************
- *DTS_CORE_UPS_WORD_03 - DTS Core User Parameters Structure Word 3 - STEREOMODE
- ***************************************************************************/
-/* RAAGA_REGSET_DSP_CFG :: DTS_CORE_UPS_WORD_03 :: STEREOMODE [31:00] */
-#define BCHP_RAAGA_REGSET_DSP_CFG_DTS_CORE_UPS_WORD_03_STEREOMODE_MASK 0xffffffff
-#define BCHP_RAAGA_REGSET_DSP_CFG_DTS_CORE_UPS_WORD_03_STEREOMODE_SHIFT 0
-#define BCHP_RAAGA_REGSET_DSP_CFG_DTS_CORE_UPS_WORD_03_STEREOMODE_Stereomode_auto 0
-#define BCHP_RAAGA_REGSET_DSP_CFG_DTS_CORE_UPS_WORD_03_STEREOMODE_Stereodmix_LTRT 1
-#define BCHP_RAAGA_REGSET_DSP_CFG_DTS_CORE_UPS_WORD_03_STEREOMODE_Stereodmix_LORO 2
-
-/***************************************************************************
- *DTS_CORE_UPS_WORD_04 - DTS Core User Parameters Structure Word 4 - EXTDNMIX_ENABLED
- ***************************************************************************/
-/* RAAGA_REGSET_DSP_CFG :: DTS_CORE_UPS_WORD_04 :: EXTDNMIX_ENABLED [31:00] */
-#define BCHP_RAAGA_REGSET_DSP_CFG_DTS_CORE_UPS_WORD_04_EXTDNMIX_ENABLED_MASK 0xffffffff
-#define BCHP_RAAGA_REGSET_DSP_CFG_DTS_CORE_UPS_WORD_04_EXTDNMIX_ENABLED_SHIFT 0
-
-/***************************************************************************
- *DTS_CORE_UPS_WORD_05_TO_40 - DTS Core User Parameters Structure Word 5 to 40 - EXTDNMIXTAB
- ***************************************************************************/
-/* RAAGA_REGSET_DSP_CFG :: DTS_CORE_UPS_WORD_05_TO_40 :: EXTDNMIXTAB [31:00] */
-#define BCHP_RAAGA_REGSET_DSP_CFG_DTS_CORE_UPS_WORD_05_TO_40_EXTDNMIXTAB_MASK 0xffffffff
-#define BCHP_RAAGA_REGSET_DSP_CFG_DTS_CORE_UPS_WORD_05_TO_40_EXTDNMIXTAB_SHIFT 0
-#define BCHP_RAAGA_REGSET_DSP_CFG_DTS_CORE_UPS_WORD_05_TO_40_EXTDNMIXTAB_Full_scale 2147483647
-#define BCHP_RAAGA_REGSET_DSP_CFG_DTS_CORE_UPS_WORD_05_TO_40_EXTDNMIXTAB_Mute 0
-
-/***************************************************************************
- *LPCM_UPS_WORD_00 - LPCM User Parameters Structure Word 0 - EXTDNMIX_ENABLED
- ***************************************************************************/
-/* RAAGA_REGSET_DSP_CFG :: LPCM_UPS_WORD_00 :: EXTDNMIX_ENABLED [31:00] */
-#define BCHP_RAAGA_REGSET_DSP_CFG_LPCM_UPS_WORD_00_EXTDNMIX_ENABLED_MASK 0xffffffff
-#define BCHP_RAAGA_REGSET_DSP_CFG_LPCM_UPS_WORD_00_EXTDNMIX_ENABLED_SHIFT 0
-
-/***************************************************************************
- *LPCM_UPS_WORD_01_TO_16 - LPCM User Parameters Structure Word 1 to 16 - EXTDNMIXTAB
- ***************************************************************************/
-/* RAAGA_REGSET_DSP_CFG :: LPCM_UPS_WORD_01_TO_16 :: EXTDNMIXTAB [31:00] */
-#define BCHP_RAAGA_REGSET_DSP_CFG_LPCM_UPS_WORD_01_TO_16_EXTDNMIXTAB_MASK 0xffffffff
-#define BCHP_RAAGA_REGSET_DSP_CFG_LPCM_UPS_WORD_01_TO_16_EXTDNMIXTAB_SHIFT 0
-#define BCHP_RAAGA_REGSET_DSP_CFG_LPCM_UPS_WORD_01_TO_16_EXTDNMIXTAB_Full_scale 2147483647
-#define BCHP_RAAGA_REGSET_DSP_CFG_LPCM_UPS_WORD_01_TO_16_EXTDNMIXTAB_Mute 0
-
-/***************************************************************************
- *MPEG_UPS_WORD_00 - MPEG User Parameters Structure Word 0 - OUTMODE
- ***************************************************************************/
-/* RAAGA_REGSET_DSP_CFG :: MPEG_UPS_WORD_00 :: OUTMODE [31:00] */
-#define BCHP_RAAGA_REGSET_DSP_CFG_MPEG_UPS_WORD_00_OUTMODE_MASK 0xffffffff
-#define BCHP_RAAGA_REGSET_DSP_CFG_MPEG_UPS_WORD_00_OUTMODE_SHIFT 0
-#define BCHP_RAAGA_REGSET_DSP_CFG_MPEG_UPS_WORD_00_OUTMODE_Stereo 0
-#define BCHP_RAAGA_REGSET_DSP_CFG_MPEG_UPS_WORD_00_OUTMODE_Mono 1
-
-/***************************************************************************
- *MPEG_UPS_WORD_01 - MPEG User Parameters Structure Word 1 - DUALMODE
- ***************************************************************************/
-/* RAAGA_REGSET_DSP_CFG :: MPEG_UPS_WORD_01 :: DUALMODE [31:00] */
-#define BCHP_RAAGA_REGSET_DSP_CFG_MPEG_UPS_WORD_01_DUALMODE_MASK 0xffffffff
-#define BCHP_RAAGA_REGSET_DSP_CFG_MPEG_UPS_WORD_01_DUALMODE_SHIFT 0
-#define BCHP_RAAGA_REGSET_DSP_CFG_MPEG_UPS_WORD_01_DUALMODE_Left_mono 0
-#define BCHP_RAAGA_REGSET_DSP_CFG_MPEG_UPS_WORD_01_DUALMODE_Right_mono 1
-#define BCHP_RAAGA_REGSET_DSP_CFG_MPEG_UPS_WORD_01_DUALMODE_Dual_stereo 2
-#define BCHP_RAAGA_REGSET_DSP_CFG_MPEG_UPS_WORD_01_DUALMODE_Dual_mixmono 3
-
-/***************************************************************************
- *RDC
- ***************************************************************************/
-/***************************************************************************
- *RUL - RUL Command.
- ***************************************************************************/
-/* RDC :: RUL :: opcode [31:24] */
-#define BCHP_RDC_RUL_opcode_MASK 0xff000000
-#define BCHP_RDC_RUL_opcode_SHIFT 24
-#define BCHP_RDC_RUL_opcode_NOP 0
-#define BCHP_RDC_RUL_opcode_REG_WRITE_IMM 1
-#define BCHP_RDC_RUL_opcode_REG_WRITE 2
-#define BCHP_RDC_RUL_opcode_REG_READ 3
-#define BCHP_RDC_RUL_opcode_LOAD_IMM 4
-#define BCHP_RDC_RUL_opcode_WINDOW_WRITE 5
-#define BCHP_RDC_RUL_opcode_BLOCK_WRITE 6
-#define BCHP_RDC_RUL_opcode_WINDOW_COPY 7
-#define BCHP_RDC_RUL_opcode_BLOCK_COPY 8
-#define BCHP_RDC_RUL_opcode_WINDOW_TO_BLOCK 9
-#define BCHP_RDC_RUL_opcode_BLOCK_TO_WINDOW 10
-#define BCHP_RDC_RUL_opcode_AND 11
-#define BCHP_RDC_RUL_opcode_AND_IMM 12
-#define BCHP_RDC_RUL_opcode_OR 13
-#define BCHP_RDC_RUL_opcode_OR_IMM 14
-#define BCHP_RDC_RUL_opcode_XOR 15
-#define BCHP_RDC_RUL_opcode_XOR_IMM 16
-#define BCHP_RDC_RUL_opcode_NOT 17
-#define BCHP_RDC_RUL_opcode_ROTATE_RIGHT 18
-#define BCHP_RDC_RUL_opcode_SUM 19
-#define BCHP_RDC_RUL_opcode_SUM_IMM 20
-#define BCHP_RDC_RUL_opcode_COND_SKIP 21
-#define BCHP_RDC_RUL_opcode_SKIP 22
-#define BCHP_RDC_RUL_opcode_EXIT 23
-#define BCHP_RDC_RUL_opcode_WAIT_EOP 24
-#define BCHP_RDC_RUL_opcode_PLACEHOLDER 255
-
-/* RDC :: RUL :: reserved0 [23:23] */
-#define BCHP_RDC_RUL_reserved0_MASK 0x00800000
-#define BCHP_RDC_RUL_reserved0_SHIFT 23
-
-/* union - case rdc_args [22:00] */
-/* RDC :: RUL :: rdc_args :: rotation [22:18] */
-#define BCHP_RDC_RUL_rdc_args_rotation_MASK 0x007c0000
-#define BCHP_RDC_RUL_rdc_args_rotation_SHIFT 18
-
-/* RDC :: RUL :: rdc_args :: src1 [17:12] */
-#define BCHP_RDC_RUL_rdc_args_src1_MASK 0x0003f000
-#define BCHP_RDC_RUL_rdc_args_src1_SHIFT 12
-
-/* RDC :: RUL :: rdc_args :: src2 [11:06] */
-#define BCHP_RDC_RUL_rdc_args_src2_MASK 0x00000fc0
-#define BCHP_RDC_RUL_rdc_args_src2_SHIFT 6
-
-/* RDC :: RUL :: rdc_args :: dest [05:00] */
-#define BCHP_RDC_RUL_rdc_args_dest_MASK 0x0000003f
-#define BCHP_RDC_RUL_rdc_args_dest_SHIFT 0
-
-/* union - case reg_args [22:00] */
-/* RDC :: RUL :: reg_args :: rotation [22:18] */
-#define BCHP_RDC_RUL_reg_args_rotation_MASK 0x007c0000
-#define BCHP_RDC_RUL_reg_args_rotation_SHIFT 18
-
-/* RDC :: RUL :: reg_args :: src1 [17:12] */
-#define BCHP_RDC_RUL_reg_args_src1_MASK 0x0003f000
-#define BCHP_RDC_RUL_reg_args_src1_SHIFT 12
-
-/* RDC :: RUL :: reg_args :: count [11:00] */
-#define BCHP_RDC_RUL_reg_args_count_MASK 0x00000fff
-#define BCHP_RDC_RUL_reg_args_count_SHIFT 0
-
-/* union - case eop_args [22:00] */
-/* RDC :: RUL :: eop_args :: reserved0 [22:08] */
-#define BCHP_RDC_RUL_eop_args_reserved0_MASK 0x007fff00
-#define BCHP_RDC_RUL_eop_args_reserved0_SHIFT 8
-
-/* RDC :: RUL :: eop_args :: eop [07:00] */
-#define BCHP_RDC_RUL_eop_args_eop_MASK 0x000000ff
-#define BCHP_RDC_RUL_eop_args_eop_SHIFT 0
-
-/***************************************************************************
- *EOP_ID_256 - EOP_ID
- ***************************************************************************/
-/* RDC :: EOP_ID_256 :: eop_id [255:00] */
-#define BCHP_RDC_EOP_ID_256_eop_id_MASK 0x00000000000000000000000000000000000000000000000000000000ffffffff
-#define BCHP_RDC_EOP_ID_256_eop_id_SHIFT 0
-#define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_scl_0 0
-#define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_scl_1 1
-#define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_scl_2 2
-#define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_scl_3 3
-#define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_scl_4 4
-#define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_scl_5 5
-#define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_scl_6 6
-#define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_scl_7 7
-#define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_mvp_0 8
-#define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_mvp_1 9
-#define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_mvp_2 10
-#define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_mvp_3 11
-#define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_mvp_4 12
-#define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_mvp_5 13
-#define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_mvp_6 14
-#define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_mvp_7 15
-#define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_dnr_0 16
-#define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_dnr_1 17
-#define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_dnr_2 18
-#define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_dnr_3 19
-#define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_dnr_4 20
-#define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_dnr_5 21
-#define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_dnr_6 22
-#define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_dnr_7 23
-#define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_lbox_0 24
-#define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_lbox_1 25
-#define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_lbox_2 26
-#define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_lbox_3 27
-#define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_lbox_4 28
-#define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_lbox_5 29
-#define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_lbox_6 30
-#define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_pfa_0 31
-#define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_null_0 32
-#define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_null_1 33
-#define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_null_2 34
-#define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_null_3 35
-#define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_null_4 36
-#define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_null_5 37
-#define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_null_6 38
-#define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_null_7 39
-#define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_nvp_0 40
-#define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_s3dh_0 41
-#define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_v0_be 42
-#define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_tntd_0 43
-#define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_xsrc_0 44
-#define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_xsrc_1 45
-#define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_reserved_0 46
-#define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_reserved_1 47
-#define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_fch_0 48
-#define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_fch_1 49
-#define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_fch_2 50
-#define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_fch_3 51
-#define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_fch_4 52
-#define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_fch_5 53
-#define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_fch_6 54
-#define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_fch_7 55
-#define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_fch_8 56
-#define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_fch_9 57
-#define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_fch_10 58
-#define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_fch_11 59
-#define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_fch_12 60
-#define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_fch_13 61
-#define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_reserved_2 62
-#define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_reserved_3 63
-#define BCHP_RDC_EOP_ID_256_eop_id_mfd_0 64
-#define BCHP_RDC_EOP_ID_256_eop_id_mfd_1 65
-#define BCHP_RDC_EOP_ID_256_eop_id_mfd_2 66
-#define BCHP_RDC_EOP_ID_256_eop_id_mfd_3 67
-#define BCHP_RDC_EOP_ID_256_eop_id_mfd_4 68
-#define BCHP_RDC_EOP_ID_256_eop_id_mfd_5 69
-#define BCHP_RDC_EOP_ID_256_eop_id_mfd_6 70
-#define BCHP_RDC_EOP_ID_256_eop_id_mfd_7 71
-#define BCHP_RDC_EOP_ID_256_eop_id_vfd_0 72
-#define BCHP_RDC_EOP_ID_256_eop_id_vfd_1 73
-#define BCHP_RDC_EOP_ID_256_eop_id_vfd_2 74
-#define BCHP_RDC_EOP_ID_256_eop_id_vfd_3 75
-#define BCHP_RDC_EOP_ID_256_eop_id_vfd_4 76
-#define BCHP_RDC_EOP_ID_256_eop_id_vfd_5 77
-#define BCHP_RDC_EOP_ID_256_eop_id_vfd_6 78
-#define BCHP_RDC_EOP_ID_256_eop_id_vfd_7 79
-#define BCHP_RDC_EOP_ID_256_eop_id_cap_0 80
-#define BCHP_RDC_EOP_ID_256_eop_id_cap_1 81
-#define BCHP_RDC_EOP_ID_256_eop_id_cap_2 82
-#define BCHP_RDC_EOP_ID_256_eop_id_cap_3 83
-#define BCHP_RDC_EOP_ID_256_eop_id_cap_4 84
-#define BCHP_RDC_EOP_ID_256_eop_id_cap_5 85
-#define BCHP_RDC_EOP_ID_256_eop_id_cap_6 86
-#define BCHP_RDC_EOP_ID_256_eop_id_cap_7 87
-#define BCHP_RDC_EOP_ID_256_eop_id_gfd_0 88
-#define BCHP_RDC_EOP_ID_256_eop_id_gfd_1 89
-#define BCHP_RDC_EOP_ID_256_eop_id_gfd_2 90
-#define BCHP_RDC_EOP_ID_256_eop_id_gfd_3 91
-#define BCHP_RDC_EOP_ID_256_eop_id_gfd_4 92
-#define BCHP_RDC_EOP_ID_256_eop_id_gfd_5 93
-#define BCHP_RDC_EOP_ID_256_eop_id_gfd_6 94
-#define BCHP_RDC_EOP_ID_256_eop_id_gfd_7 95
-#define BCHP_RDC_EOP_ID_256_eop_id_scl_0 96
-#define BCHP_RDC_EOP_ID_256_eop_id_scl_1 97
-#define BCHP_RDC_EOP_ID_256_eop_id_scl_2 98
-#define BCHP_RDC_EOP_ID_256_eop_id_scl_3 99
-#define BCHP_RDC_EOP_ID_256_eop_id_scl_4 100
-#define BCHP_RDC_EOP_ID_256_eop_id_scl_5 101
-#define BCHP_RDC_EOP_ID_256_eop_id_scl_6 102
-#define BCHP_RDC_EOP_ID_256_eop_id_scl_7 103
-#define BCHP_RDC_EOP_ID_256_eop_id_xsrc_0 104
-#define BCHP_RDC_EOP_ID_256_eop_id_xsrc_1 105
-#define BCHP_RDC_EOP_ID_256_eop_id_xsrc_2 106
-#define BCHP_RDC_EOP_ID_256_eop_id_xsrc_3 107
-#define BCHP_RDC_EOP_ID_256_eop_id_xsrc_4 108
-#define BCHP_RDC_EOP_ID_256_eop_id_xsrc_5 109
-#define BCHP_RDC_EOP_ID_256_eop_id_xsrc_6 110
-#define BCHP_RDC_EOP_ID_256_eop_id_xsrc_7 111
-#define BCHP_RDC_EOP_ID_256_eop_id_mvp_0 112
-#define BCHP_RDC_EOP_ID_256_eop_id_mvp_1 113
-#define BCHP_RDC_EOP_ID_256_eop_id_mvp_2 114
-#define BCHP_RDC_EOP_ID_256_eop_id_mvp_3 115
-#define BCHP_RDC_EOP_ID_256_eop_id_mvp_4 116
-#define BCHP_RDC_EOP_ID_256_eop_id_mvp_5 117
-#define BCHP_RDC_EOP_ID_256_eop_id_mvp_6 118
-#define BCHP_RDC_EOP_ID_256_eop_id_mvp_7 119
-#define BCHP_RDC_EOP_ID_256_eop_id_dnr_0 120
-#define BCHP_RDC_EOP_ID_256_eop_id_dnr_1 121
-#define BCHP_RDC_EOP_ID_256_eop_id_dnr_2 122
-#define BCHP_RDC_EOP_ID_256_eop_id_dnr_3 123
-#define BCHP_RDC_EOP_ID_256_eop_id_dnr_4 124
-#define BCHP_RDC_EOP_ID_256_eop_id_dnr_5 125
-#define BCHP_RDC_EOP_ID_256_eop_id_dnr_6 126
-#define BCHP_RDC_EOP_ID_256_eop_id_dnr_7 127
-#define BCHP_RDC_EOP_ID_256_eop_id_cmp_0 128
-#define BCHP_RDC_EOP_ID_256_eop_id_cmp_1 129
-#define BCHP_RDC_EOP_ID_256_eop_id_cmp_2 130
-#define BCHP_RDC_EOP_ID_256_eop_id_cmp_3 131
-#define BCHP_RDC_EOP_ID_256_eop_id_cmp_4 132
-#define BCHP_RDC_EOP_ID_256_eop_id_cmp_5 133
-#define BCHP_RDC_EOP_ID_256_eop_id_cmp_6 134
-#define BCHP_RDC_EOP_ID_256_eop_id_cmp_7 135
-#define BCHP_RDC_EOP_ID_256_eop_id_hd_dvi_0 136
-#define BCHP_RDC_EOP_ID_256_eop_id_hd_dvi_1 137
-#define BCHP_RDC_EOP_ID_256_eop_id_hd_dvi_2 138
-#define BCHP_RDC_EOP_ID_256_eop_id_hd_dvi_3 139
-#define BCHP_RDC_EOP_ID_256_eop_id_hd_dvi_4 140
-#define BCHP_RDC_EOP_ID_256_eop_id_hd_dvi_5 141
-#define BCHP_RDC_EOP_ID_256_eop_id_hd_dvi_6 142
-#define BCHP_RDC_EOP_ID_256_eop_id_tpg_0 143
-#define BCHP_RDC_EOP_ID_256_eop_id_vec_0 144
-#define BCHP_RDC_EOP_ID_256_eop_id_vec_1 145
-#define BCHP_RDC_EOP_ID_256_eop_id_vec_2 146
-#define BCHP_RDC_EOP_ID_256_eop_id_vec_3 147
-#define BCHP_RDC_EOP_ID_256_eop_id_vec_4 148
-#define BCHP_RDC_EOP_ID_256_eop_id_vec_5 149
-#define BCHP_RDC_EOP_ID_256_eop_id_vec_6 150
-#define BCHP_RDC_EOP_ID_256_eop_id_vec_7 151
-#define BCHP_RDC_EOP_ID_256_eop_id_lbox_0 152
-#define BCHP_RDC_EOP_ID_256_eop_id_lbox_1 153
-#define BCHP_RDC_EOP_ID_256_eop_id_lbox_2 154
-#define BCHP_RDC_EOP_ID_256_eop_id_lbox_3 155
-#define BCHP_RDC_EOP_ID_256_eop_id_lbox_4 156
-#define BCHP_RDC_EOP_ID_256_eop_id_lbox_5 157
-#define BCHP_RDC_EOP_ID_256_eop_id_lbox_6 158
-#define BCHP_RDC_EOP_ID_256_eop_id_pfa_0 159
-#define BCHP_RDC_EOP_ID_256_eop_id_crc_0 160
-#define BCHP_RDC_EOP_ID_256_eop_id_crc_1 161
-#define BCHP_RDC_EOP_ID_256_eop_id_crc_2 162
-#define BCHP_RDC_EOP_ID_256_eop_id_crc_3 163
-#define BCHP_RDC_EOP_ID_256_eop_id_hist_0 164
-#define BCHP_RDC_EOP_ID_256_eop_id_hist_1 165
-#define BCHP_RDC_EOP_ID_256_eop_id_psm_0 166
-#define BCHP_RDC_EOP_ID_256_eop_id_plm_0 167
-#define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_cap_0 168
-#define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_cap_1 169
-#define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_cap_2 170
-#define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_cap_3 171
-#define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_cap_4 172
-#define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_cap_5 173
-#define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_cap_6 174
-#define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_cap_7 175
-#define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_crc_0 176
-#define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_crc_1 177
-#define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_crc_2 178
-#define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_crc_3 179
-#define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_hist_0 180
-#define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_hist_1 181
-#define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_psm_0 182
-#define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_plm_0 183
-#define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_cmp_0_v0 184
-#define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_cmp_1_v0 185
-#define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_cmp_2_v0 186
-#define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_cmp_3_v0 187
-#define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_cmp_4_v0 188
-#define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_cmp_5_v0 189
-#define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_cmp_6_v0 190
-#define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_cmp_7_v0 191
-#define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_cmp_0_v1 192
-#define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_cmp_1_v1 193
-#define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_cmp_2_v1 194
-#define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_cmp_3_v1 195
-#define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_cmp_4_v1 196
-#define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_cmp_5_v1 197
-#define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_cmp_6_v1 198
-#define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_cmp_7_v1 199
-#define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_null_0 200
-#define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_null_1 201
-#define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_null_2 202
-#define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_null_3 203
-#define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_null_4 204
-#define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_null_5 205
-#define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_null_6 206
-#define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_null_7 207
-#define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_b3dc_0 208
-#define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_frc_0 209
-#define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_reserved_0 210
-#define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_reserved_1 211
-#define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_reserved_2 212
-#define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_reserved_3 213
-#define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_reserved_4 214
-#define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_reserved_5 215
-#define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_loopback_0 216
-#define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_loopback_1 217
-#define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_loopback_2 218
-#define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_loopback_3 219
-#define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_loopback_4 220
-#define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_loopback_5 221
-#define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_loopback_6 222
-#define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_loopback_7 223
-#define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_loopback_8 224
-#define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_loopback_9 225
-#define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_loopback_10 226
-#define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_loopback_11 227
-#define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_loopback_12 228
-#define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_loopback_13 229
-#define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_loopback_14 230
-#define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_reserved_9 231
-#define BCHP_RDC_EOP_ID_256_eop_id_nvp_0 232
-#define BCHP_RDC_EOP_ID_256_eop_id_s3dh_0 233
-#define BCHP_RDC_EOP_ID_256_eop_id_v0_be 234
-#define BCHP_RDC_EOP_ID_256_eop_id_reserved_0 235
-#define BCHP_RDC_EOP_ID_256_eop_id_gfd_0_1 236
-#define BCHP_RDC_EOP_ID_256_eop_id_reserved_2 237
-#define BCHP_RDC_EOP_ID_256_eop_id_reserved_3 238
-#define BCHP_RDC_EOP_ID_256_eop_id_reserved_4 239
-#define BCHP_RDC_EOP_ID_256_eop_id_b3dc_0 240
-#define BCHP_RDC_EOP_ID_256_eop_id_frc_0 241
-#define BCHP_RDC_EOP_ID_256_eop_id_pdpf_0 242
-#define BCHP_RDC_EOP_ID_256_eop_id_pdpb_0 243
-#define BCHP_RDC_EOP_ID_256_eop_id_reserved_5 244
-#define BCHP_RDC_EOP_ID_256_eop_id_reserved_6 245
-#define BCHP_RDC_EOP_ID_256_eop_id_reserved_7 246
-#define BCHP_RDC_EOP_ID_256_eop_id_reserved_8 247
-#define BCHP_RDC_EOP_ID_256_eop_id_tntd_0 248
-#define BCHP_RDC_EOP_ID_256_eop_id_vec_hddvi_0_passthr 249
-#define BCHP_RDC_EOP_ID_256_eop_id_reserved_11 250
-#define BCHP_RDC_EOP_ID_256_eop_id_reserved_12 251
-#define BCHP_RDC_EOP_ID_256_eop_id_reserved_13 252
-#define BCHP_RDC_EOP_ID_256_eop_id_reserved_14 253
-#define BCHP_RDC_EOP_ID_256_eop_id_reserved_15 254
-#define BCHP_RDC_EOP_ID_256_eop_id_reserved_16 255
-
-/***************************************************************************
- *SPDIF_RCVR_CTRL
- ***************************************************************************/
-/***************************************************************************
- *ABSTRACT_INTERRUPT_HANDLING - Interrupt Handling
- ***************************************************************************/
-/* SPDIF_RCVR_CTRL :: ABSTRACT_INTERRUPT_HANDLING :: MORE_INFORMATION [31:00] */
-#define BCHP_SPDIF_RCVR_CTRL_ABSTRACT_INTERRUPT_HANDLING_MORE_INFORMATION_MASK 0xffffffff
-#define BCHP_SPDIF_RCVR_CTRL_ABSTRACT_INTERRUPT_HANDLING_MORE_INFORMATION_SHIFT 0
-
-/***************************************************************************
- *VICE2_REGSET_MISC
- ***************************************************************************/
-/***************************************************************************
- *DCCM - registers interface address offset in DCCM.
- ***************************************************************************/
-/* VICE2_REGSET_MISC :: DCCM :: INTERFACE [31:16] */
-#define BCHP_VICE2_REGSET_MISC_DCCM_INTERFACE_MASK 0xffff0000
-#define BCHP_VICE2_REGSET_MISC_DCCM_INTERFACE_SHIFT 16
-#define BCHP_VICE2_REGSET_MISC_DCCM_INTERFACE_HOST2VICE_OFFSET 0
-#define BCHP_VICE2_REGSET_MISC_DCCM_INTERFACE_VICE2HOST_OFFSET 4
-#define BCHP_VICE2_REGSET_MISC_DCCM_INTERFACE_BVN2VICE_OFFSET 8
-#define BCHP_VICE2_REGSET_MISC_DCCM_INTERFACE_MBOX_0_START 16
-#define BCHP_VICE2_REGSET_MISC_DCCM_INTERFACE_MBOX_1_START 40
-
-/* VICE2_REGSET_MISC :: DCCM :: REVISION [15:00] */
-#define BCHP_VICE2_REGSET_MISC_DCCM_REVISION_MASK 0x0000ffff
-#define BCHP_VICE2_REGSET_MISC_DCCM_REVISION_SHIFT 0
-#define BCHP_VICE2_REGSET_MISC_DCCM_REVISION_ID 1
-
-/***************************************************************************
- *MBOX - MBOX registers interface address offset.
- ***************************************************************************/
-/* VICE2_REGSET_MISC :: MBOX :: INTERFACE [31:16] */
-#define BCHP_VICE2_REGSET_MISC_MBOX_INTERFACE_MASK 0xffff0000
-#define BCHP_VICE2_REGSET_MISC_MBOX_INTERFACE_SHIFT 16
-#define BCHP_VICE2_REGSET_MISC_MBOX_INTERFACE_DWORD_00_BVB_PIC_SIZE_OFFSET 0
-#define BCHP_VICE2_REGSET_MISC_MBOX_INTERFACE_DWORD_01_SAMPLE_ASPECT_RATIO_OFFSET 4
-#define BCHP_VICE2_REGSET_MISC_MBOX_INTERFACE_DWORD_02_PIC_INFO_OFFSET 8
-#define BCHP_VICE2_REGSET_MISC_MBOX_INTERFACE_DWORD_03_ORIGINAL_PTS_OFFSET 12
-#define BCHP_VICE2_REGSET_MISC_MBOX_INTERFACE_DWORD_04_STG_PICTURE_ID_OFFSET 16
-#define BCHP_VICE2_REGSET_MISC_MBOX_INTERFACE_DWORD_05_BARDATA_INFO_OFFSET 20
-#define BCHP_VICE2_REGSET_MISC_MBOX_INTERFACE_SIZE 6
-
-/* VICE2_REGSET_MISC :: MBOX :: MAJORREVISION [15:08] */
-#define BCHP_VICE2_REGSET_MISC_MBOX_MAJORREVISION_MASK 0x0000ff00
-#define BCHP_VICE2_REGSET_MISC_MBOX_MAJORREVISION_SHIFT 8
-#define BCHP_VICE2_REGSET_MISC_MBOX_MAJORREVISION_ID 1
-
-/* VICE2_REGSET_MISC :: MBOX :: MINORREVISION [07:00] */
-#define BCHP_VICE2_REGSET_MISC_MBOX_MINORREVISION_MASK 0x000000ff
-#define BCHP_VICE2_REGSET_MISC_MBOX_MINORREVISION_SHIFT 0
-#define BCHP_VICE2_REGSET_MISC_MBOX_MINORREVISION_ID 0
-
-/***************************************************************************
- *DWORD_00_BVB_PIC_SIZE - BVB Picture Size
- ***************************************************************************/
-/* VICE2_REGSET_MISC :: DWORD_00_BVB_PIC_SIZE :: H_SIZE [31:16] */
-#define BCHP_VICE2_REGSET_MISC_DWORD_00_BVB_PIC_SIZE_H_SIZE_MASK 0xffff0000
-#define BCHP_VICE2_REGSET_MISC_DWORD_00_BVB_PIC_SIZE_H_SIZE_SHIFT 16
-
-/* VICE2_REGSET_MISC :: DWORD_00_BVB_PIC_SIZE :: V_SIZE [15:00] */
-#define BCHP_VICE2_REGSET_MISC_DWORD_00_BVB_PIC_SIZE_V_SIZE_MASK 0x0000ffff
-#define BCHP_VICE2_REGSET_MISC_DWORD_00_BVB_PIC_SIZE_V_SIZE_SHIFT 0
-
-/***************************************************************************
- *DWORD_01_SAMPLE_ASPECT_RATIO - Sample Aspect Ratio
- ***************************************************************************/
-/* VICE2_REGSET_MISC :: DWORD_01_SAMPLE_ASPECT_RATIO :: H_SIZE [31:16] */
-#define BCHP_VICE2_REGSET_MISC_DWORD_01_SAMPLE_ASPECT_RATIO_H_SIZE_MASK 0xffff0000
-#define BCHP_VICE2_REGSET_MISC_DWORD_01_SAMPLE_ASPECT_RATIO_H_SIZE_SHIFT 16
-
-/* VICE2_REGSET_MISC :: DWORD_01_SAMPLE_ASPECT_RATIO :: V_SIZE [15:00] */
-#define BCHP_VICE2_REGSET_MISC_DWORD_01_SAMPLE_ASPECT_RATIO_V_SIZE_MASK 0x0000ffff
-#define BCHP_VICE2_REGSET_MISC_DWORD_01_SAMPLE_ASPECT_RATIO_V_SIZE_SHIFT 0
-
-/***************************************************************************
- *DWORD_02_PIC_INFO - Picture Information
- ***************************************************************************/
-/* VICE2_REGSET_MISC :: DWORD_02_PIC_INFO :: FRAME_RATE [31:16] */
-#define BCHP_VICE2_REGSET_MISC_DWORD_02_PIC_INFO_FRAME_RATE_MASK 0xffff0000
-#define BCHP_VICE2_REGSET_MISC_DWORD_02_PIC_INFO_FRAME_RATE_SHIFT 16
-
-/* VICE2_REGSET_MISC :: DWORD_02_PIC_INFO :: SRC_PIC_TYPE [15:12] */
-#define BCHP_VICE2_REGSET_MISC_DWORD_02_PIC_INFO_SRC_PIC_TYPE_MASK 0x0000f000
-#define BCHP_VICE2_REGSET_MISC_DWORD_02_PIC_INFO_SRC_PIC_TYPE_SHIFT 12
-#define BCHP_VICE2_REGSET_MISC_DWORD_02_PIC_INFO_SRC_PIC_TYPE_UNKNOWN 0
-#define BCHP_VICE2_REGSET_MISC_DWORD_02_PIC_INFO_SRC_PIC_TYPE_I 1
-#define BCHP_VICE2_REGSET_MISC_DWORD_02_PIC_INFO_SRC_PIC_TYPE_P 2
-#define BCHP_VICE2_REGSET_MISC_DWORD_02_PIC_INFO_SRC_PIC_TYPE_B 3
-
-/* VICE2_REGSET_MISC :: DWORD_02_PIC_INFO :: POLARITY [11:10] */
-#define BCHP_VICE2_REGSET_MISC_DWORD_02_PIC_INFO_POLARITY_MASK 0x00000c00
-#define BCHP_VICE2_REGSET_MISC_DWORD_02_PIC_INFO_POLARITY_SHIFT 10
-#define BCHP_VICE2_REGSET_MISC_DWORD_02_PIC_INFO_POLARITY_TOP 0
-#define BCHP_VICE2_REGSET_MISC_DWORD_02_PIC_INFO_POLARITY_BOT 1
-#define BCHP_VICE2_REGSET_MISC_DWORD_02_PIC_INFO_POLARITY_FRAME 2
-
-/* VICE2_REGSET_MISC :: DWORD_02_PIC_INFO :: REPEAT [09:09] */
-#define BCHP_VICE2_REGSET_MISC_DWORD_02_PIC_INFO_REPEAT_MASK 0x00000200
-#define BCHP_VICE2_REGSET_MISC_DWORD_02_PIC_INFO_REPEAT_SHIFT 9
-#define BCHP_VICE2_REGSET_MISC_DWORD_02_PIC_INFO_REPEAT_DISABLE 0
-#define BCHP_VICE2_REGSET_MISC_DWORD_02_PIC_INFO_REPEAT_ENABLE 1
-
-/* VICE2_REGSET_MISC :: DWORD_02_PIC_INFO :: IGNORE [08:08] */
-#define BCHP_VICE2_REGSET_MISC_DWORD_02_PIC_INFO_IGNORE_MASK 0x00000100
-#define BCHP_VICE2_REGSET_MISC_DWORD_02_PIC_INFO_IGNORE_SHIFT 8
-#define BCHP_VICE2_REGSET_MISC_DWORD_02_PIC_INFO_IGNORE_DISABLE 0
-#define BCHP_VICE2_REGSET_MISC_DWORD_02_PIC_INFO_IGNORE_ENABLE 1
-
-/* VICE2_REGSET_MISC :: DWORD_02_PIC_INFO :: LAST [07:07] */
-#define BCHP_VICE2_REGSET_MISC_DWORD_02_PIC_INFO_LAST_MASK 0x00000080
-#define BCHP_VICE2_REGSET_MISC_DWORD_02_PIC_INFO_LAST_SHIFT 7
-#define BCHP_VICE2_REGSET_MISC_DWORD_02_PIC_INFO_LAST_FALSE 0
-#define BCHP_VICE2_REGSET_MISC_DWORD_02_PIC_INFO_LAST_TRUE 1
-
-/* VICE2_REGSET_MISC :: DWORD_02_PIC_INFO :: CHANNELCHANGE [06:06] */
-#define BCHP_VICE2_REGSET_MISC_DWORD_02_PIC_INFO_CHANNELCHANGE_MASK 0x00000040
-#define BCHP_VICE2_REGSET_MISC_DWORD_02_PIC_INFO_CHANNELCHANGE_SHIFT 6
-#define BCHP_VICE2_REGSET_MISC_DWORD_02_PIC_INFO_CHANNELCHANGE_FALSE 0
-#define BCHP_VICE2_REGSET_MISC_DWORD_02_PIC_INFO_CHANNELCHANGE_TRUE 1
-
-/* VICE2_REGSET_MISC :: DWORD_02_PIC_INFO :: reserved0 [05:05] */
-#define BCHP_VICE2_REGSET_MISC_DWORD_02_PIC_INFO_reserved0_MASK 0x00000020
-#define BCHP_VICE2_REGSET_MISC_DWORD_02_PIC_INFO_reserved0_SHIFT 5
-
-/* VICE2_REGSET_MISC :: DWORD_02_PIC_INFO :: ACTIVEFORMATDATA [04:04] */
-#define BCHP_VICE2_REGSET_MISC_DWORD_02_PIC_INFO_ACTIVEFORMATDATA_MASK 0x00000010
-#define BCHP_VICE2_REGSET_MISC_DWORD_02_PIC_INFO_ACTIVEFORMATDATA_SHIFT 4
-#define BCHP_VICE2_REGSET_MISC_DWORD_02_PIC_INFO_ACTIVEFORMATDATA_FALSE 0
-#define BCHP_VICE2_REGSET_MISC_DWORD_02_PIC_INFO_ACTIVEFORMATDATA_TRUE 1
-
-/* VICE2_REGSET_MISC :: DWORD_02_PIC_INFO :: ACTIVEFORMATDATAMODE [03:00] */
-#define BCHP_VICE2_REGSET_MISC_DWORD_02_PIC_INFO_ACTIVEFORMATDATAMODE_MASK 0x0000000f
-#define BCHP_VICE2_REGSET_MISC_DWORD_02_PIC_INFO_ACTIVEFORMATDATAMODE_SHIFT 0
-
-/***************************************************************************
- *DWORD_03_ORIGINAL_PTS - Source PTS Value
- ***************************************************************************/
-/* VICE2_REGSET_MISC :: DWORD_03_ORIGINAL_PTS :: VAL [31:00] */
-#define BCHP_VICE2_REGSET_MISC_DWORD_03_ORIGINAL_PTS_VAL_MASK 0xffffffff
-#define BCHP_VICE2_REGSET_MISC_DWORD_03_ORIGINAL_PTS_VAL_SHIFT 0
-
-/***************************************************************************
- *DWORD_04_STG_PICTURE_ID - STG Picture ID
- ***************************************************************************/
-/* VICE2_REGSET_MISC :: DWORD_04_STG_PICTURE_ID :: VAL [31:00] */
-#define BCHP_VICE2_REGSET_MISC_DWORD_04_STG_PICTURE_ID_VAL_MASK 0xffffffff
-#define BCHP_VICE2_REGSET_MISC_DWORD_04_STG_PICTURE_ID_VAL_SHIFT 0
-
-/***************************************************************************
- *DWORD_05_BARDATA_INFO - bar data Information
- ***************************************************************************/
-/* VICE2_REGSET_MISC :: DWORD_05_BARDATA_INFO :: reserved0 [31:30] */
-#define BCHP_VICE2_REGSET_MISC_DWORD_05_BARDATA_INFO_reserved0_MASK 0xc0000000
-#define BCHP_VICE2_REGSET_MISC_DWORD_05_BARDATA_INFO_reserved0_SHIFT 30
-
-/* VICE2_REGSET_MISC :: DWORD_05_BARDATA_INFO :: TOPLEFTBARVALUE [29:16] */
-#define BCHP_VICE2_REGSET_MISC_DWORD_05_BARDATA_INFO_TOPLEFTBARVALUE_MASK 0x3fff0000
-#define BCHP_VICE2_REGSET_MISC_DWORD_05_BARDATA_INFO_TOPLEFTBARVALUE_SHIFT 16
-
-/* VICE2_REGSET_MISC :: DWORD_05_BARDATA_INFO :: BARDATATYPE [15:14] */
-#define BCHP_VICE2_REGSET_MISC_DWORD_05_BARDATA_INFO_BARDATATYPE_MASK 0x0000c000
-#define BCHP_VICE2_REGSET_MISC_DWORD_05_BARDATA_INFO_BARDATATYPE_SHIFT 14
-#define BCHP_VICE2_REGSET_MISC_DWORD_05_BARDATA_INFO_BARDATATYPE_invalidBarData 0
-#define BCHP_VICE2_REGSET_MISC_DWORD_05_BARDATA_INFO_BARDATATYPE_TopBottom 1
-#define BCHP_VICE2_REGSET_MISC_DWORD_05_BARDATA_INFO_BARDATATYPE_LeftRight 2
-#define BCHP_VICE2_REGSET_MISC_DWORD_05_BARDATA_INFO_BARDATATYPE_reserved 3
-
-/* VICE2_REGSET_MISC :: DWORD_05_BARDATA_INFO :: BOTRIGHTBARVALUE [13:00] */
-#define BCHP_VICE2_REGSET_MISC_DWORD_05_BARDATA_INFO_BOTRIGHTBARVALUE_MASK 0x00003fff
-#define BCHP_VICE2_REGSET_MISC_DWORD_05_BARDATA_INFO_BOTRIGHTBARVALUE_SHIFT 0
-
-/***************************************************************************
- *XPT_RAVE
- ***************************************************************************/
-/***************************************************************************
- *NOTEA_CONTEXT_SETUP_EXAMPLES - Context Setup Examples
- ***************************************************************************/
-/* XPT_RAVE :: NOTEA_CONTEXT_SETUP_EXAMPLES :: CONTEXT_EXAMPLES [31:00] */
-#define BCHP_XPT_RAVE_NOTEA_CONTEXT_SETUP_EXAMPLES_CONTEXT_EXAMPLES_MASK 0xffffffff
-#define BCHP_XPT_RAVE_NOTEA_CONTEXT_SETUP_EXAMPLES_CONTEXT_EXAMPLES_SHIFT 0
-
-/***************************************************************************
- *NOTEB_STREAM_TYPE_SETUP - Stream Type Setup
- ***************************************************************************/
-/* XPT_RAVE :: NOTEB_STREAM_TYPE_SETUP :: STREAM_TYPE_SETUP [31:00] */
-#define BCHP_XPT_RAVE_NOTEB_STREAM_TYPE_SETUP_STREAM_TYPE_SETUP_MASK 0xffffffff
-#define BCHP_XPT_RAVE_NOTEB_STREAM_TYPE_SETUP_STREAM_TYPE_SETUP_SHIFT 0
-
-/***************************************************************************
- *NOTEC_PES_LAYER_SELECTION - PES Layer Selection
- ***************************************************************************/
-/* XPT_RAVE :: NOTEC_PES_LAYER_SELECTION :: PES_LAYER_SELECTION [31:00] */
-#define BCHP_XPT_RAVE_NOTEC_PES_LAYER_SELECTION_PES_LAYER_SELECTION_MASK 0xffffffff
-#define BCHP_XPT_RAVE_NOTEC_PES_LAYER_SELECTION_PES_LAYER_SELECTION_SHIFT 0
-
-/***************************************************************************
- *NOTED_ES_FORMAT_SELECTION_GENERAL - ES Format Selection - general
- ***************************************************************************/
-/* XPT_RAVE :: NOTED_ES_FORMAT_SELECTION_GENERAL :: GENERAL_ES_FORMAT_SELECTION [31:00] */
-#define BCHP_XPT_RAVE_NOTED_ES_FORMAT_SELECTION_GENERAL_GENERAL_ES_FORMAT_SELECTION_MASK 0xffffffff
-#define BCHP_XPT_RAVE_NOTED_ES_FORMAT_SELECTION_GENERAL_GENERAL_ES_FORMAT_SELECTION_SHIFT 0
-
-/***************************************************************************
- *NOTEE_MPEG2_VIDEO_ES_SETUP - ES Setup - MPEG2 Video
- ***************************************************************************/
-/* XPT_RAVE :: NOTEE_MPEG2_VIDEO_ES_SETUP :: MPEG2_VIDEO_ES_FORMAT [31:00] */
-#define BCHP_XPT_RAVE_NOTEE_MPEG2_VIDEO_ES_SETUP_MPEG2_VIDEO_ES_FORMAT_MASK 0xffffffff
-#define BCHP_XPT_RAVE_NOTEE_MPEG2_VIDEO_ES_SETUP_MPEG2_VIDEO_ES_FORMAT_SHIFT 0
-
-/***************************************************************************
- *NOTEF_AVC_VC1_VIDEO_ES_SETUP - ES Setup - AVC and VC1 Video
- ***************************************************************************/
-/* XPT_RAVE :: NOTEF_AVC_VC1_VIDEO_ES_SETUP :: AVC_VC1_VIDEO_ES_FORMAT [31:00] */
-#define BCHP_XPT_RAVE_NOTEF_AVC_VC1_VIDEO_ES_SETUP_AVC_VC1_VIDEO_ES_FORMAT_MASK 0xffffffff
-#define BCHP_XPT_RAVE_NOTEF_AVC_VC1_VIDEO_ES_SETUP_AVC_VC1_VIDEO_ES_FORMAT_SHIFT 0
-
-/***************************************************************************
- *NOTEG_MPEG_AUDIO_ES_SETUP - ES Setup - MPEG Audio
- ***************************************************************************/
-/* XPT_RAVE :: NOTEG_MPEG_AUDIO_ES_SETUP :: AUDIO_MPEG_ES_FORMAT [31:00] */
-#define BCHP_XPT_RAVE_NOTEG_MPEG_AUDIO_ES_SETUP_AUDIO_MPEG_ES_FORMAT_MASK 0xffffffff
-#define BCHP_XPT_RAVE_NOTEG_MPEG_AUDIO_ES_SETUP_AUDIO_MPEG_ES_FORMAT_SHIFT 0
-
-/***************************************************************************
- *NOTEH_AAC_AUDIO_ES_SETUP - ES Setup - AAC Audio
- ***************************************************************************/
-/* XPT_RAVE :: NOTEH_AAC_AUDIO_ES_SETUP :: AUDIO_AAC_ES_FORMAT [31:00] */
-#define BCHP_XPT_RAVE_NOTEH_AAC_AUDIO_ES_SETUP_AUDIO_AAC_ES_FORMAT_MASK 0xffffffff
-#define BCHP_XPT_RAVE_NOTEH_AAC_AUDIO_ES_SETUP_AUDIO_AAC_ES_FORMAT_SHIFT 0
-
-/***************************************************************************
- *NOTEH_AC3_AUDIO_ES_SETUP - ES Setup - AC3 Audio
- ***************************************************************************/
-/* XPT_RAVE :: NOTEH_AC3_AUDIO_ES_SETUP :: AUDIO_AC3_ES_FORMAT [31:00] */
-#define BCHP_XPT_RAVE_NOTEH_AC3_AUDIO_ES_SETUP_AUDIO_AC3_ES_FORMAT_MASK 0xffffffff
-#define BCHP_XPT_RAVE_NOTEH_AC3_AUDIO_ES_SETUP_AUDIO_AC3_ES_FORMAT_SHIFT 0
-
-/***************************************************************************
- *NOTEJ_ENHANCED_AC3_AUDIO_ES_SETUP - ES Setup - AC3 Audio
- ***************************************************************************/
-/* XPT_RAVE :: NOTEJ_ENHANCED_AC3_AUDIO_ES_SETUP :: AUDIO_ENHANCED_AC3_ES_FORMAT [31:00] */
-#define BCHP_XPT_RAVE_NOTEJ_ENHANCED_AC3_AUDIO_ES_SETUP_AUDIO_ENHANCED_AC3_ES_FORMAT_MASK 0xffffffff
-#define BCHP_XPT_RAVE_NOTEJ_ENHANCED_AC3_AUDIO_ES_SETUP_AUDIO_ENHANCED_AC3_ES_FORMAT_SHIFT 0
-
-/***************************************************************************
- *NOTEK_AAC_HE_AUDIO_ES_SETUP - ES Setup - AAC HE Audio
- ***************************************************************************/
-/* XPT_RAVE :: NOTEK_AAC_HE_AUDIO_ES_SETUP :: AUDIO_AAC_HE_ES_FORMAT [31:00] */
-#define BCHP_XPT_RAVE_NOTEK_AAC_HE_AUDIO_ES_SETUP_AUDIO_AAC_HE_ES_FORMAT_MASK 0xffffffff
-#define BCHP_XPT_RAVE_NOTEK_AAC_HE_AUDIO_ES_SETUP_AUDIO_AAC_HE_ES_FORMAT_SHIFT 0
-
-#endif /* #ifndef BCHP_COMMON_H__ */
-
-/* End of File */
diff --git a/include/linux/brcmstb/7366b0/bchp_ddr34_phy_byte_lane_0_0.h b/include/linux/brcmstb/7366b0/bchp_ddr34_phy_byte_lane_0_0.h
deleted file mode 100644
index 731704d..0000000
--- a/include/linux/brcmstb/7366b0/bchp_ddr34_phy_byte_lane_0_0.h
+++ /dev/null
@@ -1,2482 +0,0 @@
-/***************************************************************************
- * Copyright (c) 1999-2014, Broadcom Corporation
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
- *
- * Module Description:
- * DO NOT EDIT THIS FILE DIRECTLY
- *
- * This module was generated magically with RDB from a source description
- * file. You must edit the source file for changes to be made to this file.
- *
- *
- * Date: Generated on Thu Apr 24 03:08:53 2014
- * Full Compile MD5 Checksum 1af2c2cf28828ece5496e1312aac0166
- * (minus title and desc)
- * MD5 Checksum 3203ffce85e3fc9a10f84123e54057b0
- *
- * Compiled with: RDB Utility combo_header.pl
- * RDB Parser 3.0
- * unknown unknown
- * Perl Interpreter 5.008008
- * Operating System linux
- *
- * Revision History:
- *
- * $brcm_Log: $
- *
- ***************************************************************************/
-
-#ifndef BCHP_DDR34_PHY_BYTE_LANE_0_0_H__
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_H__
-
-/***************************************************************************
- *DDR34_PHY_BYTE_LANE_0_0 - DDR34 Byte Lane #0 control registers
- ***************************************************************************/
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQS 0x00506400 /* Write channel DQS VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ0 0x00506404 /* Write channel DQ0 VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ1 0x00506408 /* Write channel DQ1 VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ2 0x0050640c /* Write channel DQ2 VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ3 0x00506410 /* Write channel DQ3 VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ4 0x00506414 /* Write channel DQ4 VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ5 0x00506418 /* Write channel DQ5 VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ6 0x0050641c /* Write channel DQ6 VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ7 0x00506420 /* Write channel DQ7 VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DM 0x00506424 /* Write channel DM VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_EDC 0x00506428 /* Write channel EDC VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQSP 0x0050642c /* Read channel DQSP VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQSN 0x00506430 /* Read channel DQSP VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ0P 0x00506434 /* Read channel DQ0-P VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ0N 0x00506438 /* Read channel DQ0-N VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ1P 0x0050643c /* Read channel DQ1-P VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ1N 0x00506440 /* Read channel DQ1-N VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ2P 0x00506444 /* Read channel DQ2-P VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ2N 0x00506448 /* Read channel DQ2-N VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ3P 0x0050644c /* Read channel DQ3-P VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ3N 0x00506450 /* Read channel DQ3-N VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ4P 0x00506454 /* Read channel DQ4-P VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ4N 0x00506458 /* Read channel DQ4-N VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ5P 0x0050645c /* Read channel DQ5-P VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ5N 0x00506460 /* Read channel DQ5-N VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ6P 0x00506464 /* Read channel DQ6-P VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ6N 0x00506468 /* Read channel DQ6-N VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ7P 0x0050646c /* Read channel DQ7-P VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ7N 0x00506470 /* Read channel DQ7-N VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DMP 0x00506474 /* Read channel DM-P VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DMN 0x00506478 /* Read channel DM-N VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_EDCP 0x0050647c /* Read channel EDC-P VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_EDCN 0x00506480 /* Read channel EDC-N VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_EN_CS0 0x00506484 /* Read channel CS_N[0] read enable VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_EN_CS1 0x00506488 /* Read channel CS_N[1] read enable VDL control register (used for reads when only cs1_n is active) */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_EN_CRC 0x0050648c /* Read channel GDDR5 CRC read enable VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CLK_CONTROL 0x00506490 /* DDR interface signal Write Leveling CLK VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_LDE_CONTROL 0x00506494 /* DDR interface signal Write Leveling Capture Enable VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_RD_EN_DLY_CYC 0x00506498 /* Read enable bit-clock cycle delay control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_WR_CHAN_DLY_CYC 0x0050649c /* Write leveling bit-clock cycle delay control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_READ_CONTROL 0x005064a0 /* Read channel datapath control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_READ_FIFO_ADDR 0x005064a4 /* Read fifo addresss pointer register */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_READ_FIFO_DATA 0x005064a8 /* Read fifo data register */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_READ_FIFO_DM_DBI 0x005064ac /* Read fifo dm/dbi register */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_READ_FIFO_STATUS 0x005064b0 /* Read fifo status register */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_READ_FIFO_CLEAR 0x005064b4 /* Read fifo status clear register */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_IDLE_PAD_CONTROL 0x005064b8 /* Idle mode SSTL pad control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_DRIVE_PAD_CTL 0x005064bc /* DQ, DM pad drive characteristics control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_DQSP_DRIVE_PAD_CTL 0x005064c0 /* DQS pad P rail drive characteristics control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_DQSN_DRIVE_PAD_CTL 0x005064c4 /* DQS pad N rail drive characteristics control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_DRIVE_PAD_CTL 0x005064c8 /* EDC pad drive characteristics control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_RD_EN_DRIVE_PAD_CTL 0x005064cc /* RD_EN, EDC_RD_EN read enable pad drive characteristics control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_STATIC_PAD_CTL 0x005064d0 /* pad rx and tx characteristics control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_DQ_RX_TRIM 0x005064d4 /* Receiver trim for DQ */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_MISC_RX_TRIM 0x005064d8 /* Receiver trim for miscellaneous pins */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_DQS_RX_TRIM 0x005064dc /* Rreceiver trim for DQS */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_WR_PREAMBLE_MODE 0x005064e0 /* Write cycle preamble control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_ODT_CONTROL 0x005064e4 /* Read channel ODT control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_LDO_CONFIG 0x005064e8 /* LDO Configuration register */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_DPD_CONTROL 0x005064ec /* GDDR5M EDC digital phase detector control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_DPD_STATUS 0x005064f0 /* GDDR5M EDC digital phase detector status register */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_DPD_OUT_CONTROL 0x005064f4 /* GDDR5M EDC digital phase detector output signal control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_DPD_OUT_STATUS 0x005064f8 /* GDDR5M EDC digital phase detector output signal status register */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_DPD_OUT_STATUS_CLEAR 0x005064fc /* GDDR5M EDC digital phase detector output signal status clear register */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_CRC_CONTROL 0x00506500 /* GDDR5M EDC signal path CRC control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_CRC_STATUS 0x00506504 /* GDDR5M EDC signal path CRC status register */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_CRC_COUNT 0x00506508 /* GDDR5M EDC signal path CRC counter register */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_CRC_STATUS_CLEAR 0x0050650c /* GDDR5M EDC signal path CRC counter register */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_CLOCK_ENABLE 0x00506510 /* Clock Enable Register */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_CLOCK_IDLE 0x00506514 /* Clock Idle Register */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_BL_SPARE_REG 0x00506518 /* Byte-Lane Spare register */
-
-/***************************************************************************
- *VDL_CONTROL_WR_DQS - Write channel DQS VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_WR_DQS :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQS_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQS_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQS_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_WR_DQS :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQS_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQS_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_WR_DQS :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQS_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQS_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQS_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_WR_DQS :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQS_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQS_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_WR_DQS :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQS_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQS_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQS_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_WR_DQS :: reserved2 [11:09] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQS_reserved2_MASK 0x00000e00
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQS_reserved2_SHIFT 9
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_WR_DQS :: VDL_STEP [08:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQS_VDL_STEP_MASK 0x000001ff
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQS_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQS_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_WR_DQ0 - Write channel DQ0 VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_WR_DQ0 :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ0_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ0_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ0_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_WR_DQ0 :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ0_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ0_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_WR_DQ0 :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ0_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ0_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ0_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_WR_DQ0 :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ0_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ0_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_WR_DQ0 :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ0_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ0_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ0_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_WR_DQ0 :: reserved2 [11:09] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ0_reserved2_MASK 0x00000e00
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ0_reserved2_SHIFT 9
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_WR_DQ0 :: VDL_STEP [08:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ0_VDL_STEP_MASK 0x000001ff
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ0_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ0_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_WR_DQ1 - Write channel DQ1 VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_WR_DQ1 :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ1_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ1_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ1_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_WR_DQ1 :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ1_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ1_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_WR_DQ1 :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ1_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ1_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ1_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_WR_DQ1 :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ1_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ1_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_WR_DQ1 :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ1_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ1_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ1_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_WR_DQ1 :: reserved2 [11:09] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ1_reserved2_MASK 0x00000e00
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ1_reserved2_SHIFT 9
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_WR_DQ1 :: VDL_STEP [08:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ1_VDL_STEP_MASK 0x000001ff
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ1_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ1_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_WR_DQ2 - Write channel DQ2 VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_WR_DQ2 :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ2_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ2_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ2_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_WR_DQ2 :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ2_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ2_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_WR_DQ2 :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ2_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ2_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ2_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_WR_DQ2 :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ2_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ2_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_WR_DQ2 :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ2_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ2_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ2_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_WR_DQ2 :: reserved2 [11:09] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ2_reserved2_MASK 0x00000e00
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ2_reserved2_SHIFT 9
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_WR_DQ2 :: VDL_STEP [08:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ2_VDL_STEP_MASK 0x000001ff
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ2_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ2_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_WR_DQ3 - Write channel DQ3 VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_WR_DQ3 :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ3_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ3_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ3_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_WR_DQ3 :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ3_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ3_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_WR_DQ3 :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ3_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ3_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ3_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_WR_DQ3 :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ3_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ3_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_WR_DQ3 :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ3_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ3_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ3_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_WR_DQ3 :: reserved2 [11:09] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ3_reserved2_MASK 0x00000e00
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ3_reserved2_SHIFT 9
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_WR_DQ3 :: VDL_STEP [08:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ3_VDL_STEP_MASK 0x000001ff
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ3_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ3_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_WR_DQ4 - Write channel DQ4 VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_WR_DQ4 :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ4_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ4_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ4_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_WR_DQ4 :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ4_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ4_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_WR_DQ4 :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ4_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ4_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ4_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_WR_DQ4 :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ4_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ4_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_WR_DQ4 :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ4_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ4_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ4_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_WR_DQ4 :: reserved2 [11:09] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ4_reserved2_MASK 0x00000e00
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ4_reserved2_SHIFT 9
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_WR_DQ4 :: VDL_STEP [08:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ4_VDL_STEP_MASK 0x000001ff
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ4_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ4_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_WR_DQ5 - Write channel DQ5 VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_WR_DQ5 :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ5_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ5_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ5_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_WR_DQ5 :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ5_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ5_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_WR_DQ5 :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ5_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ5_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ5_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_WR_DQ5 :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ5_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ5_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_WR_DQ5 :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ5_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ5_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ5_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_WR_DQ5 :: reserved2 [11:09] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ5_reserved2_MASK 0x00000e00
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ5_reserved2_SHIFT 9
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_WR_DQ5 :: VDL_STEP [08:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ5_VDL_STEP_MASK 0x000001ff
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ5_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ5_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_WR_DQ6 - Write channel DQ6 VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_WR_DQ6 :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ6_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ6_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ6_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_WR_DQ6 :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ6_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ6_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_WR_DQ6 :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ6_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ6_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ6_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_WR_DQ6 :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ6_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ6_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_WR_DQ6 :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ6_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ6_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ6_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_WR_DQ6 :: reserved2 [11:09] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ6_reserved2_MASK 0x00000e00
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ6_reserved2_SHIFT 9
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_WR_DQ6 :: VDL_STEP [08:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ6_VDL_STEP_MASK 0x000001ff
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ6_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ6_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_WR_DQ7 - Write channel DQ7 VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_WR_DQ7 :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ7_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ7_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ7_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_WR_DQ7 :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ7_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ7_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_WR_DQ7 :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ7_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ7_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ7_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_WR_DQ7 :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ7_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ7_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_WR_DQ7 :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ7_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ7_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ7_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_WR_DQ7 :: reserved2 [11:09] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ7_reserved2_MASK 0x00000e00
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ7_reserved2_SHIFT 9
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_WR_DQ7 :: VDL_STEP [08:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ7_VDL_STEP_MASK 0x000001ff
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ7_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ7_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_WR_DM - Write channel DM VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_WR_DM :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DM_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DM_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DM_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_WR_DM :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DM_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DM_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_WR_DM :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DM_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DM_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DM_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_WR_DM :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DM_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DM_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_WR_DM :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DM_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DM_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DM_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_WR_DM :: reserved2 [11:09] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DM_reserved2_MASK 0x00000e00
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DM_reserved2_SHIFT 9
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_WR_DM :: VDL_STEP [08:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DM_VDL_STEP_MASK 0x000001ff
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DM_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DM_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_WR_EDC - Write channel EDC VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_WR_EDC :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_EDC_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_EDC_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_EDC_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_WR_EDC :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_EDC_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_EDC_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_WR_EDC :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_EDC_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_EDC_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_EDC_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_WR_EDC :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_EDC_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_EDC_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_WR_EDC :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_EDC_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_EDC_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_EDC_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_WR_EDC :: reserved2 [11:09] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_EDC_reserved2_MASK 0x00000e00
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_EDC_reserved2_SHIFT 9
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_WR_EDC :: VDL_STEP [08:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_EDC_VDL_STEP_MASK 0x000001ff
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_EDC_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_EDC_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_RD_DQSP - Read channel DQSP VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQSP :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQSP_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQSP_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQSP_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQSP :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQSP_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQSP_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQSP :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQSP_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQSP_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQSP_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQSP :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQSP_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQSP_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQSP :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQSP_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQSP_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQSP_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQSP :: reserved2 [11:08] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQSP_reserved2_MASK 0x00000f00
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQSP_reserved2_SHIFT 8
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQSP :: VDL_STEP [07:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQSP_VDL_STEP_MASK 0x000000ff
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQSP_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQSP_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_RD_DQSN - Read channel DQSP VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQSN :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQSN_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQSN_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQSN_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQSN :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQSN_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQSN_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQSN :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQSN_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQSN_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQSN_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQSN :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQSN_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQSN_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQSN :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQSN_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQSN_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQSN_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQSN :: reserved2 [11:08] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQSN_reserved2_MASK 0x00000f00
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQSN_reserved2_SHIFT 8
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQSN :: VDL_STEP [07:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQSN_VDL_STEP_MASK 0x000000ff
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQSN_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQSN_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_RD_DQ0P - Read channel DQ0-P VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQ0P :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ0P_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ0P_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ0P_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQ0P :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ0P_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ0P_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQ0P :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ0P_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ0P_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ0P_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQ0P :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ0P_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ0P_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQ0P :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ0P_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ0P_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ0P_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQ0P :: reserved2 [11:08] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ0P_reserved2_MASK 0x00000f00
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ0P_reserved2_SHIFT 8
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQ0P :: VDL_STEP [07:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ0P_VDL_STEP_MASK 0x000000ff
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ0P_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ0P_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_RD_DQ0N - Read channel DQ0-N VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQ0N :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ0N_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ0N_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ0N_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQ0N :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ0N_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ0N_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQ0N :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ0N_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ0N_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ0N_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQ0N :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ0N_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ0N_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQ0N :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ0N_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ0N_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ0N_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQ0N :: reserved2 [11:08] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ0N_reserved2_MASK 0x00000f00
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ0N_reserved2_SHIFT 8
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQ0N :: VDL_STEP [07:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ0N_VDL_STEP_MASK 0x000000ff
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ0N_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ0N_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_RD_DQ1P - Read channel DQ1-P VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQ1P :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ1P_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ1P_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ1P_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQ1P :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ1P_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ1P_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQ1P :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ1P_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ1P_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ1P_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQ1P :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ1P_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ1P_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQ1P :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ1P_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ1P_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ1P_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQ1P :: reserved2 [11:08] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ1P_reserved2_MASK 0x00000f00
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ1P_reserved2_SHIFT 8
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQ1P :: VDL_STEP [07:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ1P_VDL_STEP_MASK 0x000000ff
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ1P_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ1P_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_RD_DQ1N - Read channel DQ1-N VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQ1N :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ1N_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ1N_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ1N_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQ1N :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ1N_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ1N_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQ1N :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ1N_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ1N_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ1N_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQ1N :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ1N_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ1N_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQ1N :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ1N_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ1N_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ1N_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQ1N :: reserved2 [11:08] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ1N_reserved2_MASK 0x00000f00
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ1N_reserved2_SHIFT 8
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQ1N :: VDL_STEP [07:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ1N_VDL_STEP_MASK 0x000000ff
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ1N_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ1N_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_RD_DQ2P - Read channel DQ2-P VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQ2P :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ2P_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ2P_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ2P_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQ2P :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ2P_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ2P_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQ2P :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ2P_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ2P_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ2P_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQ2P :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ2P_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ2P_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQ2P :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ2P_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ2P_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ2P_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQ2P :: reserved2 [11:08] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ2P_reserved2_MASK 0x00000f00
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ2P_reserved2_SHIFT 8
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQ2P :: VDL_STEP [07:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ2P_VDL_STEP_MASK 0x000000ff
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ2P_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ2P_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_RD_DQ2N - Read channel DQ2-N VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQ2N :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ2N_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ2N_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ2N_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQ2N :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ2N_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ2N_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQ2N :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ2N_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ2N_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ2N_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQ2N :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ2N_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ2N_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQ2N :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ2N_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ2N_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ2N_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQ2N :: reserved2 [11:08] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ2N_reserved2_MASK 0x00000f00
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ2N_reserved2_SHIFT 8
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQ2N :: VDL_STEP [07:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ2N_VDL_STEP_MASK 0x000000ff
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ2N_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ2N_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_RD_DQ3P - Read channel DQ3-P VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQ3P :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ3P_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ3P_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ3P_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQ3P :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ3P_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ3P_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQ3P :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ3P_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ3P_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ3P_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQ3P :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ3P_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ3P_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQ3P :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ3P_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ3P_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ3P_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQ3P :: reserved2 [11:08] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ3P_reserved2_MASK 0x00000f00
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ3P_reserved2_SHIFT 8
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQ3P :: VDL_STEP [07:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ3P_VDL_STEP_MASK 0x000000ff
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ3P_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ3P_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_RD_DQ3N - Read channel DQ3-N VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQ3N :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ3N_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ3N_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ3N_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQ3N :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ3N_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ3N_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQ3N :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ3N_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ3N_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ3N_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQ3N :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ3N_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ3N_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQ3N :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ3N_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ3N_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ3N_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQ3N :: reserved2 [11:08] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ3N_reserved2_MASK 0x00000f00
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ3N_reserved2_SHIFT 8
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQ3N :: VDL_STEP [07:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ3N_VDL_STEP_MASK 0x000000ff
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ3N_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ3N_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_RD_DQ4P - Read channel DQ4-P VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQ4P :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ4P_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ4P_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ4P_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQ4P :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ4P_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ4P_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQ4P :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ4P_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ4P_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ4P_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQ4P :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ4P_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ4P_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQ4P :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ4P_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ4P_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ4P_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQ4P :: reserved2 [11:08] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ4P_reserved2_MASK 0x00000f00
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ4P_reserved2_SHIFT 8
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQ4P :: VDL_STEP [07:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ4P_VDL_STEP_MASK 0x000000ff
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ4P_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ4P_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_RD_DQ4N - Read channel DQ4-N VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQ4N :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ4N_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ4N_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ4N_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQ4N :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ4N_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ4N_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQ4N :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ4N_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ4N_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ4N_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQ4N :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ4N_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ4N_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQ4N :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ4N_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ4N_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ4N_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQ4N :: reserved2 [11:08] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ4N_reserved2_MASK 0x00000f00
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ4N_reserved2_SHIFT 8
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQ4N :: VDL_STEP [07:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ4N_VDL_STEP_MASK 0x000000ff
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ4N_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ4N_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_RD_DQ5P - Read channel DQ5-P VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQ5P :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ5P_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ5P_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ5P_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQ5P :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ5P_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ5P_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQ5P :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ5P_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ5P_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ5P_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQ5P :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ5P_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ5P_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQ5P :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ5P_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ5P_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ5P_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQ5P :: reserved2 [11:08] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ5P_reserved2_MASK 0x00000f00
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ5P_reserved2_SHIFT 8
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQ5P :: VDL_STEP [07:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ5P_VDL_STEP_MASK 0x000000ff
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ5P_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ5P_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_RD_DQ5N - Read channel DQ5-N VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQ5N :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ5N_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ5N_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ5N_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQ5N :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ5N_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ5N_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQ5N :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ5N_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ5N_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ5N_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQ5N :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ5N_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ5N_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQ5N :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ5N_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ5N_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ5N_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQ5N :: reserved2 [11:08] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ5N_reserved2_MASK 0x00000f00
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ5N_reserved2_SHIFT 8
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQ5N :: VDL_STEP [07:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ5N_VDL_STEP_MASK 0x000000ff
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ5N_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ5N_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_RD_DQ6P - Read channel DQ6-P VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQ6P :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ6P_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ6P_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ6P_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQ6P :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ6P_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ6P_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQ6P :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ6P_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ6P_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ6P_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQ6P :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ6P_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ6P_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQ6P :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ6P_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ6P_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ6P_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQ6P :: reserved2 [11:08] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ6P_reserved2_MASK 0x00000f00
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ6P_reserved2_SHIFT 8
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQ6P :: VDL_STEP [07:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ6P_VDL_STEP_MASK 0x000000ff
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ6P_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ6P_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_RD_DQ6N - Read channel DQ6-N VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQ6N :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ6N_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ6N_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ6N_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQ6N :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ6N_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ6N_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQ6N :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ6N_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ6N_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ6N_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQ6N :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ6N_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ6N_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQ6N :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ6N_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ6N_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ6N_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQ6N :: reserved2 [11:08] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ6N_reserved2_MASK 0x00000f00
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ6N_reserved2_SHIFT 8
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQ6N :: VDL_STEP [07:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ6N_VDL_STEP_MASK 0x000000ff
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ6N_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ6N_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_RD_DQ7P - Read channel DQ7-P VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQ7P :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ7P_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ7P_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ7P_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQ7P :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ7P_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ7P_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQ7P :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ7P_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ7P_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ7P_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQ7P :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ7P_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ7P_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQ7P :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ7P_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ7P_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ7P_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQ7P :: reserved2 [11:08] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ7P_reserved2_MASK 0x00000f00
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ7P_reserved2_SHIFT 8
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQ7P :: VDL_STEP [07:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ7P_VDL_STEP_MASK 0x000000ff
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ7P_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ7P_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_RD_DQ7N - Read channel DQ7-N VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQ7N :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ7N_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ7N_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ7N_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQ7N :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ7N_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ7N_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQ7N :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ7N_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ7N_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ7N_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQ7N :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ7N_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ7N_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQ7N :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ7N_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ7N_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ7N_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQ7N :: reserved2 [11:08] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ7N_reserved2_MASK 0x00000f00
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ7N_reserved2_SHIFT 8
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQ7N :: VDL_STEP [07:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ7N_VDL_STEP_MASK 0x000000ff
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ7N_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ7N_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_RD_DMP - Read channel DM-P VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DMP :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DMP_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DMP_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DMP_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DMP :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DMP_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DMP_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DMP :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DMP_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DMP_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DMP_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DMP :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DMP_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DMP_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DMP :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DMP_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DMP_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DMP_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DMP :: reserved2 [11:08] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DMP_reserved2_MASK 0x00000f00
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DMP_reserved2_SHIFT 8
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DMP :: VDL_STEP [07:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DMP_VDL_STEP_MASK 0x000000ff
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DMP_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DMP_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_RD_DMN - Read channel DM-N VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DMN :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DMN_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DMN_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DMN_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DMN :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DMN_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DMN_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DMN :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DMN_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DMN_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DMN_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DMN :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DMN_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DMN_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DMN :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DMN_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DMN_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DMN_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DMN :: reserved2 [11:08] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DMN_reserved2_MASK 0x00000f00
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DMN_reserved2_SHIFT 8
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DMN :: VDL_STEP [07:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DMN_VDL_STEP_MASK 0x000000ff
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DMN_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DMN_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_RD_EDCP - Read channel EDC-P VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_EDCP :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_EDCP_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_EDCP_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_EDCP_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_EDCP :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_EDCP_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_EDCP_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_EDCP :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_EDCP_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_EDCP_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_EDCP_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_EDCP :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_EDCP_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_EDCP_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_EDCP :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_EDCP_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_EDCP_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_EDCP_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_EDCP :: reserved2 [11:08] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_EDCP_reserved2_MASK 0x00000f00
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_EDCP_reserved2_SHIFT 8
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_EDCP :: VDL_STEP [07:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_EDCP_VDL_STEP_MASK 0x000000ff
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_EDCP_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_EDCP_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_RD_EDCN - Read channel EDC-N VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_EDCN :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_EDCN_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_EDCN_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_EDCN_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_EDCN :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_EDCN_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_EDCN_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_EDCN :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_EDCN_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_EDCN_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_EDCN_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_EDCN :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_EDCN_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_EDCN_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_EDCN :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_EDCN_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_EDCN_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_EDCN_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_EDCN :: reserved2 [11:08] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_EDCN_reserved2_MASK 0x00000f00
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_EDCN_reserved2_SHIFT 8
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_EDCN :: VDL_STEP [07:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_EDCN_VDL_STEP_MASK 0x000000ff
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_EDCN_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_EDCN_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_RD_EN_CS0 - Read channel CS_N[0] read enable VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_EN_CS0 :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_EN_CS0_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_EN_CS0_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_EN_CS0_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_EN_CS0 :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_EN_CS0_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_EN_CS0_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_EN_CS0 :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_EN_CS0_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_EN_CS0_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_EN_CS0_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_EN_CS0 :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_EN_CS0_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_EN_CS0_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_EN_CS0 :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_EN_CS0_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_EN_CS0_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_EN_CS0_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_EN_CS0 :: reserved2 [11:08] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_EN_CS0_reserved2_MASK 0x00000f00
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_EN_CS0_reserved2_SHIFT 8
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_EN_CS0 :: VDL_STEP [07:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_EN_CS0_VDL_STEP_MASK 0x000000ff
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_EN_CS0_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_EN_CS0_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_RD_EN_CS1 - Read channel CS_N[1] read enable VDL control register (used for reads when only cs1_n is active)
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_EN_CS1 :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_EN_CS1_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_EN_CS1_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_EN_CS1_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_EN_CS1 :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_EN_CS1_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_EN_CS1_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_EN_CS1 :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_EN_CS1_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_EN_CS1_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_EN_CS1_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_EN_CS1 :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_EN_CS1_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_EN_CS1_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_EN_CS1 :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_EN_CS1_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_EN_CS1_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_EN_CS1_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_EN_CS1 :: reserved2 [11:08] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_EN_CS1_reserved2_MASK 0x00000f00
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_EN_CS1_reserved2_SHIFT 8
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_EN_CS1 :: VDL_STEP [07:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_EN_CS1_VDL_STEP_MASK 0x000000ff
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_EN_CS1_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_EN_CS1_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_RD_EN_CRC - Read channel GDDR5 CRC read enable VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_EN_CRC :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_EN_CRC_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_EN_CRC_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_EN_CRC_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_EN_CRC :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_EN_CRC_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_EN_CRC_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_EN_CRC :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_EN_CRC_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_EN_CRC_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_EN_CRC_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_EN_CRC :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_EN_CRC_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_EN_CRC_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_EN_CRC :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_EN_CRC_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_EN_CRC_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_EN_CRC_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_EN_CRC :: reserved2 [11:08] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_EN_CRC_reserved2_MASK 0x00000f00
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_EN_CRC_reserved2_SHIFT 8
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_EN_CRC :: VDL_STEP [07:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_EN_CRC_VDL_STEP_MASK 0x000000ff
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_EN_CRC_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_EN_CRC_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CLK_CONTROL - DDR interface signal Write Leveling CLK VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CLK_CONTROL :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CLK_CONTROL_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CLK_CONTROL_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CLK_CONTROL_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CLK_CONTROL :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CLK_CONTROL_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CLK_CONTROL_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CLK_CONTROL :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CLK_CONTROL_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CLK_CONTROL_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CLK_CONTROL_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CLK_CONTROL :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CLK_CONTROL_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CLK_CONTROL_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CLK_CONTROL :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CLK_CONTROL_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CLK_CONTROL_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CLK_CONTROL_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CLK_CONTROL :: reserved2 [11:09] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CLK_CONTROL_reserved2_MASK 0x00000e00
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CLK_CONTROL_reserved2_SHIFT 9
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CLK_CONTROL :: VDL_STEP [08:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CLK_CONTROL_VDL_STEP_MASK 0x000001ff
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CLK_CONTROL_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CLK_CONTROL_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_LDE_CONTROL - DDR interface signal Write Leveling Capture Enable VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_LDE_CONTROL :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_LDE_CONTROL_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_LDE_CONTROL_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_LDE_CONTROL_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_LDE_CONTROL :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_LDE_CONTROL_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_LDE_CONTROL_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_LDE_CONTROL :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_LDE_CONTROL_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_LDE_CONTROL_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_LDE_CONTROL_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_LDE_CONTROL :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_LDE_CONTROL_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_LDE_CONTROL_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_LDE_CONTROL :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_LDE_CONTROL_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_LDE_CONTROL_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_LDE_CONTROL_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_LDE_CONTROL :: reserved2 [11:09] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_LDE_CONTROL_reserved2_MASK 0x00000e00
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_LDE_CONTROL_reserved2_SHIFT 9
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_LDE_CONTROL :: VDL_STEP [08:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_LDE_CONTROL_VDL_STEP_MASK 0x000001ff
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_LDE_CONTROL_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_LDE_CONTROL_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *RD_EN_DLY_CYC - Read enable bit-clock cycle delay control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_0_0 :: RD_EN_DLY_CYC :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_RD_EN_DLY_CYC_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_RD_EN_DLY_CYC_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_RD_EN_DLY_CYC_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: RD_EN_DLY_CYC :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_RD_EN_DLY_CYC_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_RD_EN_DLY_CYC_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: RD_EN_DLY_CYC :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_RD_EN_DLY_CYC_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_RD_EN_DLY_CYC_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_RD_EN_DLY_CYC_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: RD_EN_DLY_CYC :: reserved1 [15:14] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_RD_EN_DLY_CYC_reserved1_MASK 0x0000c000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_RD_EN_DLY_CYC_reserved1_SHIFT 14
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: RD_EN_DLY_CYC :: CRC_CYCLES [13:10] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_RD_EN_DLY_CYC_CRC_CYCLES_MASK 0x00003c00
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_RD_EN_DLY_CYC_CRC_CYCLES_SHIFT 10
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_RD_EN_DLY_CYC_CRC_CYCLES_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: RD_EN_DLY_CYC :: reserved2 [09:09] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_RD_EN_DLY_CYC_reserved2_MASK 0x00000200
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_RD_EN_DLY_CYC_reserved2_SHIFT 9
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: RD_EN_DLY_CYC :: ENABLE_CS1 [08:08] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_RD_EN_DLY_CYC_ENABLE_CS1_MASK 0x00000100
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_RD_EN_DLY_CYC_ENABLE_CS1_SHIFT 8
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_RD_EN_DLY_CYC_ENABLE_CS1_DEFAULT 0x00000001
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: RD_EN_DLY_CYC :: CS1_CYCLES [07:04] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_RD_EN_DLY_CYC_CS1_CYCLES_MASK 0x000000f0
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_RD_EN_DLY_CYC_CS1_CYCLES_SHIFT 4
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_RD_EN_DLY_CYC_CS1_CYCLES_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: RD_EN_DLY_CYC :: CS0_CYCLES [03:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_RD_EN_DLY_CYC_CS0_CYCLES_MASK 0x0000000f
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_RD_EN_DLY_CYC_CS0_CYCLES_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_RD_EN_DLY_CYC_CS0_CYCLES_DEFAULT 0x00000000
-
-/***************************************************************************
- *WR_CHAN_DLY_CYC - Write leveling bit-clock cycle delay control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_0_0 :: WR_CHAN_DLY_CYC :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_WR_CHAN_DLY_CYC_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_WR_CHAN_DLY_CYC_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_WR_CHAN_DLY_CYC_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: WR_CHAN_DLY_CYC :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_WR_CHAN_DLY_CYC_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_WR_CHAN_DLY_CYC_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: WR_CHAN_DLY_CYC :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_WR_CHAN_DLY_CYC_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_WR_CHAN_DLY_CYC_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_WR_CHAN_DLY_CYC_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: WR_CHAN_DLY_CYC :: reserved1 [15:08] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_WR_CHAN_DLY_CYC_reserved1_MASK 0x0000ff00
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_WR_CHAN_DLY_CYC_reserved1_SHIFT 8
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: WR_CHAN_DLY_CYC :: DQ_CYCLES [07:04] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_WR_CHAN_DLY_CYC_DQ_CYCLES_MASK 0x000000f0
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_WR_CHAN_DLY_CYC_DQ_CYCLES_SHIFT 4
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_WR_CHAN_DLY_CYC_DQ_CYCLES_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: WR_CHAN_DLY_CYC :: reserved2 [03:03] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_WR_CHAN_DLY_CYC_reserved2_MASK 0x00000008
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_WR_CHAN_DLY_CYC_reserved2_SHIFT 3
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: WR_CHAN_DLY_CYC :: CYCLES [02:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_WR_CHAN_DLY_CYC_CYCLES_MASK 0x00000007
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_WR_CHAN_DLY_CYC_CYCLES_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_WR_CHAN_DLY_CYC_CYCLES_DEFAULT 0x00000000
-
-/***************************************************************************
- *READ_CONTROL - Read channel datapath control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_0_0 :: READ_CONTROL :: reserved0 [31:05] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_READ_CONTROL_reserved0_MASK 0xffffffe0
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_READ_CONTROL_reserved0_SHIFT 5
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: READ_CONTROL :: MODE [04:04] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_READ_CONTROL_MODE_MASK 0x00000010
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_READ_CONTROL_MODE_SHIFT 4
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_READ_CONTROL_MODE_DEFAULT 0x00000001
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: READ_CONTROL :: RD_EN_MODE [03:03] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_READ_CONTROL_RD_EN_MODE_MASK 0x00000008
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_READ_CONTROL_RD_EN_MODE_SHIFT 3
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_READ_CONTROL_RD_EN_MODE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: READ_CONTROL :: RD_DATA_DLY [02:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_READ_CONTROL_RD_DATA_DLY_MASK 0x00000007
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_READ_CONTROL_RD_DATA_DLY_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_READ_CONTROL_RD_DATA_DLY_DEFAULT 0x00000007
-
-/***************************************************************************
- *READ_FIFO_ADDR - Read fifo addresss pointer register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_0_0 :: READ_FIFO_ADDR :: reserved0 [31:03] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_READ_FIFO_ADDR_reserved0_MASK 0xfffffff8
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_READ_FIFO_ADDR_reserved0_SHIFT 3
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: READ_FIFO_ADDR :: ADDR [02:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_READ_FIFO_ADDR_ADDR_MASK 0x00000007
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_READ_FIFO_ADDR_ADDR_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_READ_FIFO_ADDR_ADDR_DEFAULT 0x00000000
-
-/***************************************************************************
- *READ_FIFO_DATA - Read fifo data register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_0_0 :: READ_FIFO_DATA :: DATA [31:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_READ_FIFO_DATA_DATA_MASK 0xffffffff
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_READ_FIFO_DATA_DATA_SHIFT 0
-
-/***************************************************************************
- *READ_FIFO_DM_DBI - Read fifo dm/dbi register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_0_0 :: READ_FIFO_DM_DBI :: reserved0 [31:04] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_READ_FIFO_DM_DBI_reserved0_MASK 0xfffffff0
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_READ_FIFO_DM_DBI_reserved0_SHIFT 4
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: READ_FIFO_DM_DBI :: DM_DBI [03:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_READ_FIFO_DM_DBI_DM_DBI_MASK 0x0000000f
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_READ_FIFO_DM_DBI_DM_DBI_SHIFT 0
-
-/***************************************************************************
- *READ_FIFO_STATUS - Read fifo status register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_0_0 :: READ_FIFO_STATUS :: reserved0 [31:02] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_READ_FIFO_STATUS_reserved0_MASK 0xfffffffc
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_READ_FIFO_STATUS_reserved0_SHIFT 2
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: READ_FIFO_STATUS :: OVERFLOW [01:01] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_READ_FIFO_STATUS_OVERFLOW_MASK 0x00000002
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_READ_FIFO_STATUS_OVERFLOW_SHIFT 1
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_READ_FIFO_STATUS_OVERFLOW_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: READ_FIFO_STATUS :: UNDERFLOW [00:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_READ_FIFO_STATUS_UNDERFLOW_MASK 0x00000001
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_READ_FIFO_STATUS_UNDERFLOW_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_READ_FIFO_STATUS_UNDERFLOW_DEFAULT 0x00000000
-
-/***************************************************************************
- *READ_FIFO_CLEAR - Read fifo status clear register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_0_0 :: READ_FIFO_CLEAR :: reserved0 [31:01] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_READ_FIFO_CLEAR_reserved0_MASK 0xfffffffe
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_READ_FIFO_CLEAR_reserved0_SHIFT 1
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: READ_FIFO_CLEAR :: CLEAR [00:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_READ_FIFO_CLEAR_CLEAR_MASK 0x00000001
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_READ_FIFO_CLEAR_CLEAR_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_READ_FIFO_CLEAR_CLEAR_DEFAULT 0x00000000
-
-/***************************************************************************
- *IDLE_PAD_CONTROL - Idle mode SSTL pad control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_0_0 :: IDLE_PAD_CONTROL :: IDLE [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_IDLE_PAD_CONTROL_IDLE_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_IDLE_PAD_CONTROL_IDLE_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_IDLE_PAD_CONTROL_IDLE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: IDLE_PAD_CONTROL :: reserved0 [30:20] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_IDLE_PAD_CONTROL_reserved0_MASK 0x7ff00000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_IDLE_PAD_CONTROL_reserved0_SHIFT 20
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: IDLE_PAD_CONTROL :: AUTO_DQ_RXENB_MODE [19:18] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_IDLE_PAD_CONTROL_AUTO_DQ_RXENB_MODE_MASK 0x000c0000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_IDLE_PAD_CONTROL_AUTO_DQ_RXENB_MODE_SHIFT 18
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_IDLE_PAD_CONTROL_AUTO_DQ_RXENB_MODE_DEFAULT 0x00000003
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: IDLE_PAD_CONTROL :: AUTO_DQ_IDDQ_MODE [17:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_IDLE_PAD_CONTROL_AUTO_DQ_IDDQ_MODE_MASK 0x00030000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_IDLE_PAD_CONTROL_AUTO_DQ_IDDQ_MODE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_IDLE_PAD_CONTROL_AUTO_DQ_IDDQ_MODE_DEFAULT 0x00000003
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: IDLE_PAD_CONTROL :: IO_IDLE_ENABLE [15:04] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_IDLE_PAD_CONTROL_IO_IDLE_ENABLE_MASK 0x0000fff0
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_IDLE_PAD_CONTROL_IO_IDLE_ENABLE_SHIFT 4
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_IDLE_PAD_CONTROL_IO_IDLE_ENABLE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: IDLE_PAD_CONTROL :: RXENB [03:03] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_IDLE_PAD_CONTROL_RXENB_MASK 0x00000008
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_IDLE_PAD_CONTROL_RXENB_SHIFT 3
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_IDLE_PAD_CONTROL_RXENB_DEFAULT 0x00000001
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: IDLE_PAD_CONTROL :: IDDQ [02:02] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_IDLE_PAD_CONTROL_IDDQ_MASK 0x00000004
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_IDLE_PAD_CONTROL_IDDQ_SHIFT 2
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_IDLE_PAD_CONTROL_IDDQ_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: IDLE_PAD_CONTROL :: DOUT_N [01:01] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_IDLE_PAD_CONTROL_DOUT_N_MASK 0x00000002
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_IDLE_PAD_CONTROL_DOUT_N_SHIFT 1
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_IDLE_PAD_CONTROL_DOUT_N_DEFAULT 0x00000001
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: IDLE_PAD_CONTROL :: DOUT_P [00:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_IDLE_PAD_CONTROL_DOUT_P_MASK 0x00000001
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_IDLE_PAD_CONTROL_DOUT_P_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_IDLE_PAD_CONTROL_DOUT_P_DEFAULT 0x00000000
-
-/***************************************************************************
- *DRIVE_PAD_CTL - DQ, DM pad drive characteristics control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_0_0 :: DRIVE_PAD_CTL :: reserved0 [31:30] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_DRIVE_PAD_CTL_reserved0_MASK 0xc0000000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_DRIVE_PAD_CTL_reserved0_SHIFT 30
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: DRIVE_PAD_CTL :: BL_PD_IDLE_STRENGTH [29:25] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_DRIVE_PAD_CTL_BL_PD_IDLE_STRENGTH_MASK 0x3e000000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_DRIVE_PAD_CTL_BL_PD_IDLE_STRENGTH_SHIFT 25
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_DRIVE_PAD_CTL_BL_PD_IDLE_STRENGTH_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: DRIVE_PAD_CTL :: BL_ND_IDLE_STRENGTH [24:20] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_DRIVE_PAD_CTL_BL_ND_IDLE_STRENGTH_MASK 0x01f00000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_DRIVE_PAD_CTL_BL_ND_IDLE_STRENGTH_SHIFT 20
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_DRIVE_PAD_CTL_BL_ND_IDLE_STRENGTH_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: DRIVE_PAD_CTL :: BL_PD_TERM_STRENGTH [19:15] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_DRIVE_PAD_CTL_BL_PD_TERM_STRENGTH_MASK 0x000f8000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_DRIVE_PAD_CTL_BL_PD_TERM_STRENGTH_SHIFT 15
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_DRIVE_PAD_CTL_BL_PD_TERM_STRENGTH_DEFAULT 0x00000008
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: DRIVE_PAD_CTL :: BL_ND_TERM_STRENGTH [14:10] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_DRIVE_PAD_CTL_BL_ND_TERM_STRENGTH_MASK 0x00007c00
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_DRIVE_PAD_CTL_BL_ND_TERM_STRENGTH_SHIFT 10
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_DRIVE_PAD_CTL_BL_ND_TERM_STRENGTH_DEFAULT 0x00000008
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: DRIVE_PAD_CTL :: BL_PD_STRENGTH [09:05] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_DRIVE_PAD_CTL_BL_PD_STRENGTH_MASK 0x000003e0
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_DRIVE_PAD_CTL_BL_PD_STRENGTH_SHIFT 5
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_DRIVE_PAD_CTL_BL_PD_STRENGTH_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: DRIVE_PAD_CTL :: BL_ND_STRENGTH [04:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_DRIVE_PAD_CTL_BL_ND_STRENGTH_MASK 0x0000001f
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_DRIVE_PAD_CTL_BL_ND_STRENGTH_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_DRIVE_PAD_CTL_BL_ND_STRENGTH_DEFAULT 0x00000000
-
-/***************************************************************************
- *DQSP_DRIVE_PAD_CTL - DQS pad P rail drive characteristics control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_0_0 :: DQSP_DRIVE_PAD_CTL :: reserved0 [31:30] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_DQSP_DRIVE_PAD_CTL_reserved0_MASK 0xc0000000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_DQSP_DRIVE_PAD_CTL_reserved0_SHIFT 30
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: DQSP_DRIVE_PAD_CTL :: BL_PD_IDLE_STRENGTH [29:25] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_DQSP_DRIVE_PAD_CTL_BL_PD_IDLE_STRENGTH_MASK 0x3e000000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_DQSP_DRIVE_PAD_CTL_BL_PD_IDLE_STRENGTH_SHIFT 25
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_DQSP_DRIVE_PAD_CTL_BL_PD_IDLE_STRENGTH_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: DQSP_DRIVE_PAD_CTL :: BL_ND_IDLE_STRENGTH [24:20] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_DQSP_DRIVE_PAD_CTL_BL_ND_IDLE_STRENGTH_MASK 0x01f00000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_DQSP_DRIVE_PAD_CTL_BL_ND_IDLE_STRENGTH_SHIFT 20
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_DQSP_DRIVE_PAD_CTL_BL_ND_IDLE_STRENGTH_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: DQSP_DRIVE_PAD_CTL :: BL_PD_TERM_STRENGTH [19:15] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_DQSP_DRIVE_PAD_CTL_BL_PD_TERM_STRENGTH_MASK 0x000f8000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_DQSP_DRIVE_PAD_CTL_BL_PD_TERM_STRENGTH_SHIFT 15
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_DQSP_DRIVE_PAD_CTL_BL_PD_TERM_STRENGTH_DEFAULT 0x00000008
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: DQSP_DRIVE_PAD_CTL :: BL_ND_TERM_STRENGTH [14:10] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_DQSP_DRIVE_PAD_CTL_BL_ND_TERM_STRENGTH_MASK 0x00007c00
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_DQSP_DRIVE_PAD_CTL_BL_ND_TERM_STRENGTH_SHIFT 10
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_DQSP_DRIVE_PAD_CTL_BL_ND_TERM_STRENGTH_DEFAULT 0x00000008
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: DQSP_DRIVE_PAD_CTL :: BL_PD_STRENGTH [09:05] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_DQSP_DRIVE_PAD_CTL_BL_PD_STRENGTH_MASK 0x000003e0
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_DQSP_DRIVE_PAD_CTL_BL_PD_STRENGTH_SHIFT 5
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_DQSP_DRIVE_PAD_CTL_BL_PD_STRENGTH_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: DQSP_DRIVE_PAD_CTL :: BL_ND_STRENGTH [04:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_DQSP_DRIVE_PAD_CTL_BL_ND_STRENGTH_MASK 0x0000001f
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_DQSP_DRIVE_PAD_CTL_BL_ND_STRENGTH_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_DQSP_DRIVE_PAD_CTL_BL_ND_STRENGTH_DEFAULT 0x00000000
-
-/***************************************************************************
- *DQSN_DRIVE_PAD_CTL - DQS pad N rail drive characteristics control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_0_0 :: DQSN_DRIVE_PAD_CTL :: reserved0 [31:30] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_DQSN_DRIVE_PAD_CTL_reserved0_MASK 0xc0000000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_DQSN_DRIVE_PAD_CTL_reserved0_SHIFT 30
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: DQSN_DRIVE_PAD_CTL :: BL_PD_IDLE_STRENGTH [29:25] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_DQSN_DRIVE_PAD_CTL_BL_PD_IDLE_STRENGTH_MASK 0x3e000000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_DQSN_DRIVE_PAD_CTL_BL_PD_IDLE_STRENGTH_SHIFT 25
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_DQSN_DRIVE_PAD_CTL_BL_PD_IDLE_STRENGTH_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: DQSN_DRIVE_PAD_CTL :: BL_ND_IDLE_STRENGTH [24:20] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_DQSN_DRIVE_PAD_CTL_BL_ND_IDLE_STRENGTH_MASK 0x01f00000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_DQSN_DRIVE_PAD_CTL_BL_ND_IDLE_STRENGTH_SHIFT 20
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_DQSN_DRIVE_PAD_CTL_BL_ND_IDLE_STRENGTH_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: DQSN_DRIVE_PAD_CTL :: BL_PD_TERM_STRENGTH [19:15] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_DQSN_DRIVE_PAD_CTL_BL_PD_TERM_STRENGTH_MASK 0x000f8000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_DQSN_DRIVE_PAD_CTL_BL_PD_TERM_STRENGTH_SHIFT 15
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_DQSN_DRIVE_PAD_CTL_BL_PD_TERM_STRENGTH_DEFAULT 0x00000008
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: DQSN_DRIVE_PAD_CTL :: BL_ND_TERM_STRENGTH [14:10] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_DQSN_DRIVE_PAD_CTL_BL_ND_TERM_STRENGTH_MASK 0x00007c00
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_DQSN_DRIVE_PAD_CTL_BL_ND_TERM_STRENGTH_SHIFT 10
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_DQSN_DRIVE_PAD_CTL_BL_ND_TERM_STRENGTH_DEFAULT 0x00000008
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: DQSN_DRIVE_PAD_CTL :: BL_PD_STRENGTH [09:05] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_DQSN_DRIVE_PAD_CTL_BL_PD_STRENGTH_MASK 0x000003e0
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_DQSN_DRIVE_PAD_CTL_BL_PD_STRENGTH_SHIFT 5
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_DQSN_DRIVE_PAD_CTL_BL_PD_STRENGTH_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: DQSN_DRIVE_PAD_CTL :: BL_ND_STRENGTH [04:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_DQSN_DRIVE_PAD_CTL_BL_ND_STRENGTH_MASK 0x0000001f
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_DQSN_DRIVE_PAD_CTL_BL_ND_STRENGTH_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_DQSN_DRIVE_PAD_CTL_BL_ND_STRENGTH_DEFAULT 0x00000000
-
-/***************************************************************************
- *EDC_DRIVE_PAD_CTL - EDC pad drive characteristics control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_0_0 :: EDC_DRIVE_PAD_CTL :: reserved0 [31:30] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_DRIVE_PAD_CTL_reserved0_MASK 0xc0000000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_DRIVE_PAD_CTL_reserved0_SHIFT 30
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: EDC_DRIVE_PAD_CTL :: BL_PD_IDLE_STRENGTH [29:25] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_DRIVE_PAD_CTL_BL_PD_IDLE_STRENGTH_MASK 0x3e000000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_DRIVE_PAD_CTL_BL_PD_IDLE_STRENGTH_SHIFT 25
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_DRIVE_PAD_CTL_BL_PD_IDLE_STRENGTH_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: EDC_DRIVE_PAD_CTL :: BL_ND_IDLE_STRENGTH [24:20] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_DRIVE_PAD_CTL_BL_ND_IDLE_STRENGTH_MASK 0x01f00000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_DRIVE_PAD_CTL_BL_ND_IDLE_STRENGTH_SHIFT 20
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_DRIVE_PAD_CTL_BL_ND_IDLE_STRENGTH_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: EDC_DRIVE_PAD_CTL :: BL_PD_TERM_STRENGTH [19:15] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_DRIVE_PAD_CTL_BL_PD_TERM_STRENGTH_MASK 0x000f8000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_DRIVE_PAD_CTL_BL_PD_TERM_STRENGTH_SHIFT 15
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_DRIVE_PAD_CTL_BL_PD_TERM_STRENGTH_DEFAULT 0x00000008
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: EDC_DRIVE_PAD_CTL :: BL_ND_TERM_STRENGTH [14:10] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_DRIVE_PAD_CTL_BL_ND_TERM_STRENGTH_MASK 0x00007c00
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_DRIVE_PAD_CTL_BL_ND_TERM_STRENGTH_SHIFT 10
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_DRIVE_PAD_CTL_BL_ND_TERM_STRENGTH_DEFAULT 0x00000008
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: EDC_DRIVE_PAD_CTL :: BL_PD_STRENGTH [09:05] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_DRIVE_PAD_CTL_BL_PD_STRENGTH_MASK 0x000003e0
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_DRIVE_PAD_CTL_BL_PD_STRENGTH_SHIFT 5
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_DRIVE_PAD_CTL_BL_PD_STRENGTH_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: EDC_DRIVE_PAD_CTL :: BL_ND_STRENGTH [04:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_DRIVE_PAD_CTL_BL_ND_STRENGTH_MASK 0x0000001f
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_DRIVE_PAD_CTL_BL_ND_STRENGTH_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_DRIVE_PAD_CTL_BL_ND_STRENGTH_DEFAULT 0x00000000
-
-/***************************************************************************
- *RD_EN_DRIVE_PAD_CTL - RD_EN, EDC_RD_EN read enable pad drive characteristics control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_0_0 :: RD_EN_DRIVE_PAD_CTL :: reserved0 [31:20] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_RD_EN_DRIVE_PAD_CTL_reserved0_MASK 0xfff00000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_RD_EN_DRIVE_PAD_CTL_reserved0_SHIFT 20
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: RD_EN_DRIVE_PAD_CTL :: EDC_RD_EN_PD_STRENGTH [19:15] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_RD_EN_DRIVE_PAD_CTL_EDC_RD_EN_PD_STRENGTH_MASK 0x000f8000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_RD_EN_DRIVE_PAD_CTL_EDC_RD_EN_PD_STRENGTH_SHIFT 15
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_RD_EN_DRIVE_PAD_CTL_EDC_RD_EN_PD_STRENGTH_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: RD_EN_DRIVE_PAD_CTL :: EDC_RD_EN_ND_STRENGTH [14:10] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_RD_EN_DRIVE_PAD_CTL_EDC_RD_EN_ND_STRENGTH_MASK 0x00007c00
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_RD_EN_DRIVE_PAD_CTL_EDC_RD_EN_ND_STRENGTH_SHIFT 10
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_RD_EN_DRIVE_PAD_CTL_EDC_RD_EN_ND_STRENGTH_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: RD_EN_DRIVE_PAD_CTL :: BL_RD_EN_PD_STRENGTH [09:05] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_RD_EN_DRIVE_PAD_CTL_BL_RD_EN_PD_STRENGTH_MASK 0x000003e0
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_RD_EN_DRIVE_PAD_CTL_BL_RD_EN_PD_STRENGTH_SHIFT 5
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_RD_EN_DRIVE_PAD_CTL_BL_RD_EN_PD_STRENGTH_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: RD_EN_DRIVE_PAD_CTL :: BL_RD_EN_ND_STRENGTH [04:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_RD_EN_DRIVE_PAD_CTL_BL_RD_EN_ND_STRENGTH_MASK 0x0000001f
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_RD_EN_DRIVE_PAD_CTL_BL_RD_EN_ND_STRENGTH_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_RD_EN_DRIVE_PAD_CTL_BL_RD_EN_ND_STRENGTH_DEFAULT 0x00000000
-
-/***************************************************************************
- *STATIC_PAD_CTL - pad rx and tx characteristics control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_0_0 :: STATIC_PAD_CTL :: reserved0 [31:25] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_STATIC_PAD_CTL_reserved0_MASK 0xfe000000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_STATIC_PAD_CTL_reserved0_SHIFT 25
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: STATIC_PAD_CTL :: TX_SLEW [24:23] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_STATIC_PAD_CTL_TX_SLEW_MASK 0x01800000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_STATIC_PAD_CTL_TX_SLEW_SHIFT 23
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_STATIC_PAD_CTL_TX_SLEW_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: STATIC_PAD_CTL :: DQS_MODE [22:22] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_STATIC_PAD_CTL_DQS_MODE_MASK 0x00400000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_STATIC_PAD_CTL_DQS_MODE_SHIFT 22
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_STATIC_PAD_CTL_DQS_MODE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: STATIC_PAD_CTL :: reserved1 [21:20] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_STATIC_PAD_CTL_reserved1_MASK 0x00300000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_STATIC_PAD_CTL_reserved1_SHIFT 20
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: STATIC_PAD_CTL :: EDC_MODE [19:18] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_STATIC_PAD_CTL_EDC_MODE_MASK 0x000c0000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_STATIC_PAD_CTL_EDC_MODE_SHIFT 18
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_STATIC_PAD_CTL_EDC_MODE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: STATIC_PAD_CTL :: reserved2 [17:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_STATIC_PAD_CTL_reserved2_MASK 0x00020000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_STATIC_PAD_CTL_reserved2_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: STATIC_PAD_CTL :: WDBI_ENABLE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_STATIC_PAD_CTL_WDBI_ENABLE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_STATIC_PAD_CTL_WDBI_ENABLE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_STATIC_PAD_CTL_WDBI_ENABLE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: STATIC_PAD_CTL :: RDBI_ENABLE [15:15] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_STATIC_PAD_CTL_RDBI_ENABLE_MASK 0x00008000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_STATIC_PAD_CTL_RDBI_ENABLE_SHIFT 15
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_STATIC_PAD_CTL_RDBI_ENABLE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: STATIC_PAD_CTL :: DM_MODE [14:14] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_STATIC_PAD_CTL_DM_MODE_MASK 0x00004000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_STATIC_PAD_CTL_DM_MODE_SHIFT 14
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_STATIC_PAD_CTL_DM_MODE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: STATIC_PAD_CTL :: reserved3 [13:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_STATIC_PAD_CTL_reserved3_MASK 0x00002000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_STATIC_PAD_CTL_reserved3_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: STATIC_PAD_CTL :: DQS_TX_PAUSE [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_STATIC_PAD_CTL_DQS_TX_PAUSE_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_STATIC_PAD_CTL_DQS_TX_PAUSE_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_STATIC_PAD_CTL_DQS_TX_PAUSE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: STATIC_PAD_CTL :: reserved_for_padding4 [11:11] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_STATIC_PAD_CTL_reserved_for_padding4_MASK 0x00000800
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_STATIC_PAD_CTL_reserved_for_padding4_SHIFT 11
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: STATIC_PAD_CTL :: DQS_TX_DIS [10:10] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_STATIC_PAD_CTL_DQS_TX_DIS_MASK 0x00000400
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_STATIC_PAD_CTL_DQS_TX_DIS_SHIFT 10
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_STATIC_PAD_CTL_DQS_TX_DIS_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: STATIC_PAD_CTL :: TX_MODE [09:04] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_STATIC_PAD_CTL_TX_MODE_MASK 0x000003f0
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_STATIC_PAD_CTL_TX_MODE_SHIFT 4
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_STATIC_PAD_CTL_TX_MODE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: STATIC_PAD_CTL :: reserved5 [03:03] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_STATIC_PAD_CTL_reserved5_MASK 0x00000008
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_STATIC_PAD_CTL_reserved5_SHIFT 3
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: STATIC_PAD_CTL :: RX_MODE [02:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_STATIC_PAD_CTL_RX_MODE_MASK 0x00000007
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_STATIC_PAD_CTL_RX_MODE_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_STATIC_PAD_CTL_RX_MODE_DEFAULT 0x00000000
-
-/***************************************************************************
- *DQ_RX_TRIM - Receiver trim for DQ
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_0_0 :: DQ_RX_TRIM :: reserved0 [31:21] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_DQ_RX_TRIM_reserved0_MASK 0xffe00000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_DQ_RX_TRIM_reserved0_SHIFT 21
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: DQ_RX_TRIM :: LSTRIM [20:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_DQ_RX_TRIM_LSTRIM_MASK 0x001e0000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_DQ_RX_TRIM_LSTRIM_SHIFT 17
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_DQ_RX_TRIM_LSTRIM_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: DQ_RX_TRIM :: ITRIM [16:14] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_DQ_RX_TRIM_ITRIM_MASK 0x0001c000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_DQ_RX_TRIM_ITRIM_SHIFT 14
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_DQ_RX_TRIM_ITRIM_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: DQ_RX_TRIM :: IDLE_LSTRIM [13:10] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_DQ_RX_TRIM_IDLE_LSTRIM_MASK 0x00003c00
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_DQ_RX_TRIM_IDLE_LSTRIM_SHIFT 10
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_DQ_RX_TRIM_IDLE_LSTRIM_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: DQ_RX_TRIM :: IDLE_ITRIM [09:07] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_DQ_RX_TRIM_IDLE_ITRIM_MASK 0x00000380
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_DQ_RX_TRIM_IDLE_ITRIM_SHIFT 7
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_DQ_RX_TRIM_IDLE_ITRIM_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: DQ_RX_TRIM :: TERM_LSTRIM [06:03] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_DQ_RX_TRIM_TERM_LSTRIM_MASK 0x00000078
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_DQ_RX_TRIM_TERM_LSTRIM_SHIFT 3
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_DQ_RX_TRIM_TERM_LSTRIM_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: DQ_RX_TRIM :: TERM_ITRIM [02:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_DQ_RX_TRIM_TERM_ITRIM_MASK 0x00000007
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_DQ_RX_TRIM_TERM_ITRIM_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_DQ_RX_TRIM_TERM_ITRIM_DEFAULT 0x00000000
-
-/***************************************************************************
- *MISC_RX_TRIM - Receiver trim for miscellaneous pins
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_0_0 :: MISC_RX_TRIM :: reserved0 [31:21] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_MISC_RX_TRIM_reserved0_MASK 0xffe00000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_MISC_RX_TRIM_reserved0_SHIFT 21
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: MISC_RX_TRIM :: LSTRIM [20:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_MISC_RX_TRIM_LSTRIM_MASK 0x001e0000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_MISC_RX_TRIM_LSTRIM_SHIFT 17
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_MISC_RX_TRIM_LSTRIM_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: MISC_RX_TRIM :: ITRIM [16:14] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_MISC_RX_TRIM_ITRIM_MASK 0x0001c000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_MISC_RX_TRIM_ITRIM_SHIFT 14
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_MISC_RX_TRIM_ITRIM_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: MISC_RX_TRIM :: IDLE_LSTRIM [13:10] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_MISC_RX_TRIM_IDLE_LSTRIM_MASK 0x00003c00
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_MISC_RX_TRIM_IDLE_LSTRIM_SHIFT 10
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_MISC_RX_TRIM_IDLE_LSTRIM_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: MISC_RX_TRIM :: IDLE_ITRIM [09:07] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_MISC_RX_TRIM_IDLE_ITRIM_MASK 0x00000380
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_MISC_RX_TRIM_IDLE_ITRIM_SHIFT 7
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_MISC_RX_TRIM_IDLE_ITRIM_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: MISC_RX_TRIM :: TERM_LSTRIM [06:03] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_MISC_RX_TRIM_TERM_LSTRIM_MASK 0x00000078
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_MISC_RX_TRIM_TERM_LSTRIM_SHIFT 3
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_MISC_RX_TRIM_TERM_LSTRIM_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: MISC_RX_TRIM :: TERM_ITRIM [02:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_MISC_RX_TRIM_TERM_ITRIM_MASK 0x00000007
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_MISC_RX_TRIM_TERM_ITRIM_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_MISC_RX_TRIM_TERM_ITRIM_DEFAULT 0x00000000
-
-/***************************************************************************
- *DQS_RX_TRIM - Rreceiver trim for DQS
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_0_0 :: DQS_RX_TRIM :: reserved0 [31:21] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_DQS_RX_TRIM_reserved0_MASK 0xffe00000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_DQS_RX_TRIM_reserved0_SHIFT 21
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: DQS_RX_TRIM :: LSTRIM [20:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_DQS_RX_TRIM_LSTRIM_MASK 0x001e0000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_DQS_RX_TRIM_LSTRIM_SHIFT 17
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_DQS_RX_TRIM_LSTRIM_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: DQS_RX_TRIM :: ITRIM [16:14] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_DQS_RX_TRIM_ITRIM_MASK 0x0001c000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_DQS_RX_TRIM_ITRIM_SHIFT 14
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_DQS_RX_TRIM_ITRIM_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: DQS_RX_TRIM :: IDLE_LSTRIM [13:10] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_DQS_RX_TRIM_IDLE_LSTRIM_MASK 0x00003c00
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_DQS_RX_TRIM_IDLE_LSTRIM_SHIFT 10
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_DQS_RX_TRIM_IDLE_LSTRIM_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: DQS_RX_TRIM :: IDLE_ITRIM [09:07] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_DQS_RX_TRIM_IDLE_ITRIM_MASK 0x00000380
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_DQS_RX_TRIM_IDLE_ITRIM_SHIFT 7
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_DQS_RX_TRIM_IDLE_ITRIM_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: DQS_RX_TRIM :: TERM_LSTRIM [06:03] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_DQS_RX_TRIM_TERM_LSTRIM_MASK 0x00000078
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_DQS_RX_TRIM_TERM_LSTRIM_SHIFT 3
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_DQS_RX_TRIM_TERM_LSTRIM_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: DQS_RX_TRIM :: TERM_ITRIM [02:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_DQS_RX_TRIM_TERM_ITRIM_MASK 0x00000007
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_DQS_RX_TRIM_TERM_ITRIM_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_DQS_RX_TRIM_TERM_ITRIM_DEFAULT 0x00000000
-
-/***************************************************************************
- *WR_PREAMBLE_MODE - Write cycle preamble control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_0_0 :: WR_PREAMBLE_MODE :: reserved0 [31:21] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_WR_PREAMBLE_MODE_reserved0_MASK 0xffe00000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_WR_PREAMBLE_MODE_reserved0_SHIFT 21
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: WR_PREAMBLE_MODE :: POSTAM_TERM_BITS [20:19] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_WR_PREAMBLE_MODE_POSTAM_TERM_BITS_MASK 0x00180000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_WR_PREAMBLE_MODE_POSTAM_TERM_BITS_SHIFT 19
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_WR_PREAMBLE_MODE_POSTAM_TERM_BITS_DEFAULT 0x00000003
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: WR_PREAMBLE_MODE :: DM_POSTAM_BITS [18:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_WR_PREAMBLE_MODE_DM_POSTAM_BITS_MASK 0x00060000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_WR_PREAMBLE_MODE_DM_POSTAM_BITS_SHIFT 17
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_WR_PREAMBLE_MODE_DM_POSTAM_BITS_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: WR_PREAMBLE_MODE :: DM_PREAM_BITS [16:14] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_WR_PREAMBLE_MODE_DM_PREAM_BITS_MASK 0x0001c000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_WR_PREAMBLE_MODE_DM_PREAM_BITS_SHIFT 14
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_WR_PREAMBLE_MODE_DM_PREAM_BITS_DEFAULT 0x00000001
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: WR_PREAMBLE_MODE :: DQ_POSTAM_BITS [13:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_WR_PREAMBLE_MODE_DQ_POSTAM_BITS_MASK 0x00003000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_WR_PREAMBLE_MODE_DQ_POSTAM_BITS_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_WR_PREAMBLE_MODE_DQ_POSTAM_BITS_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: WR_PREAMBLE_MODE :: DQ_PREAM_BITS [11:09] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_WR_PREAMBLE_MODE_DQ_PREAM_BITS_MASK 0x00000e00
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_WR_PREAMBLE_MODE_DQ_PREAM_BITS_SHIFT 9
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_WR_PREAMBLE_MODE_DQ_PREAM_BITS_DEFAULT 0x00000001
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: WR_PREAMBLE_MODE :: DQS [08:05] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_WR_PREAMBLE_MODE_DQS_MASK 0x000001e0
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_WR_PREAMBLE_MODE_DQS_SHIFT 5
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_WR_PREAMBLE_MODE_DQS_DEFAULT 0x0000000a
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: WR_PREAMBLE_MODE :: DQS_POSTAM_BITS [04:03] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_WR_PREAMBLE_MODE_DQS_POSTAM_BITS_MASK 0x00000018
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_WR_PREAMBLE_MODE_DQS_POSTAM_BITS_SHIFT 3
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_WR_PREAMBLE_MODE_DQS_POSTAM_BITS_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: WR_PREAMBLE_MODE :: DQS_PREAM_BITS [02:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_WR_PREAMBLE_MODE_DQS_PREAM_BITS_MASK 0x00000007
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_WR_PREAMBLE_MODE_DQS_PREAM_BITS_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_WR_PREAMBLE_MODE_DQS_PREAM_BITS_DEFAULT 0x00000002
-
-/***************************************************************************
- *ODT_CONTROL - Read channel ODT control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_0_0 :: ODT_CONTROL :: reserved_for_padding0 [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_ODT_CONTROL_reserved_for_padding0_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_ODT_CONTROL_reserved_for_padding0_SHIFT 31
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: ODT_CONTROL :: reserved1 [30:10] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_ODT_CONTROL_reserved1_MASK 0x7ffffc00
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_ODT_CONTROL_reserved1_SHIFT 10
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: ODT_CONTROL :: ODT_ENABLE [09:09] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_ODT_CONTROL_ODT_ENABLE_MASK 0x00000200
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_ODT_CONTROL_ODT_ENABLE_SHIFT 9
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_ODT_CONTROL_ODT_ENABLE_DEFAULT 0x00000001
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: ODT_CONTROL :: ODT_DELAY [08:06] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_ODT_CONTROL_ODT_DELAY_MASK 0x000001c0
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_ODT_CONTROL_ODT_DELAY_SHIFT 6
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_ODT_CONTROL_ODT_DELAY_DEFAULT 0x00000001
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: ODT_CONTROL :: ODT_POST_LENGTH [05:03] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_ODT_CONTROL_ODT_POST_LENGTH_MASK 0x00000038
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_ODT_CONTROL_ODT_POST_LENGTH_SHIFT 3
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_ODT_CONTROL_ODT_POST_LENGTH_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: ODT_CONTROL :: ODT_PRE_LENGTH [02:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_ODT_CONTROL_ODT_PRE_LENGTH_MASK 0x00000007
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_ODT_CONTROL_ODT_PRE_LENGTH_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_ODT_CONTROL_ODT_PRE_LENGTH_DEFAULT 0x00000003
-
-/***************************************************************************
- *LDO_CONFIG - LDO Configuration register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_0_0 :: LDO_CONFIG :: reserved0 [31:06] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_LDO_CONFIG_reserved0_MASK 0xffffffc0
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_LDO_CONFIG_reserved0_SHIFT 6
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: LDO_CONFIG :: CK_LDO_PWRDOWN [05:05] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_LDO_CONFIG_CK_LDO_PWRDOWN_MASK 0x00000020
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_LDO_CONFIG_CK_LDO_PWRDOWN_SHIFT 5
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_LDO_CONFIG_CK_LDO_PWRDOWN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: LDO_CONFIG :: CK_LDO_REF_SEL [04:04] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_LDO_CONFIG_CK_LDO_REF_SEL_MASK 0x00000010
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_LDO_CONFIG_CK_LDO_REF_SEL_SHIFT 4
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_LDO_CONFIG_CK_LDO_REF_SEL_DEFAULT 0x00000001
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: LDO_CONFIG :: CK_LDO_REF_CTRL [03:02] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_LDO_CONFIG_CK_LDO_REF_CTRL_MASK 0x0000000c
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_LDO_CONFIG_CK_LDO_REF_CTRL_SHIFT 2
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_LDO_CONFIG_CK_LDO_REF_CTRL_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: LDO_CONFIG :: CK_LDO_BIAS [01:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_LDO_CONFIG_CK_LDO_BIAS_MASK 0x00000003
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_LDO_CONFIG_CK_LDO_BIAS_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_LDO_CONFIG_CK_LDO_BIAS_DEFAULT 0x00000000
-
-/***************************************************************************
- *EDC_DPD_CONTROL - GDDR5M EDC digital phase detector control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_0_0 :: EDC_DPD_CONTROL :: reserved0 [31:22] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_DPD_CONTROL_reserved0_MASK 0xffc00000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_DPD_CONTROL_reserved0_SHIFT 22
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: EDC_DPD_CONTROL :: DQS_PHASE_OVERRIDE_VALUE [21:21] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_DPD_CONTROL_DQS_PHASE_OVERRIDE_VALUE_MASK 0x00200000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_DPD_CONTROL_DQS_PHASE_OVERRIDE_VALUE_SHIFT 21
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_DPD_CONTROL_DQS_PHASE_OVERRIDE_VALUE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: EDC_DPD_CONTROL :: DQS_PHASE_OVERRIDE_ENABLE [20:20] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_DPD_CONTROL_DQS_PHASE_OVERRIDE_ENABLE_MASK 0x00100000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_DPD_CONTROL_DQS_PHASE_OVERRIDE_ENABLE_SHIFT 20
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_DPD_CONTROL_DQS_PHASE_OVERRIDE_ENABLE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: EDC_DPD_CONTROL :: reserved1 [19:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_DPD_CONTROL_reserved1_MASK 0x000f0000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_DPD_CONTROL_reserved1_SHIFT 16
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: EDC_DPD_CONTROL :: TARGET_CS_N [15:15] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_DPD_CONTROL_TARGET_CS_N_MASK 0x00008000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_DPD_CONTROL_TARGET_CS_N_SHIFT 15
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_DPD_CONTROL_TARGET_CS_N_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: EDC_DPD_CONTROL :: UPDATE_MODE [14:14] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_DPD_CONTROL_UPDATE_MODE_MASK 0x00004000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_DPD_CONTROL_UPDATE_MODE_SHIFT 14
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_DPD_CONTROL_UPDATE_MODE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: EDC_DPD_CONTROL :: SAMPLE_MODE [13:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_DPD_CONTROL_SAMPLE_MODE_MASK 0x00003000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_DPD_CONTROL_SAMPLE_MODE_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_DPD_CONTROL_SAMPLE_MODE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: EDC_DPD_CONTROL :: reserved2 [11:09] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_DPD_CONTROL_reserved2_MASK 0x00000e00
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_DPD_CONTROL_reserved2_SHIFT 9
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: EDC_DPD_CONTROL :: MIN_LOW_SAMPLES [08:04] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_DPD_CONTROL_MIN_LOW_SAMPLES_MASK 0x000001f0
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_DPD_CONTROL_MIN_LOW_SAMPLES_SHIFT 4
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_DPD_CONTROL_MIN_LOW_SAMPLES_DEFAULT 0x00000008
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: EDC_DPD_CONTROL :: SET_ADJ_EN [03:03] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_DPD_CONTROL_SET_ADJ_EN_MASK 0x00000008
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_DPD_CONTROL_SET_ADJ_EN_SHIFT 3
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_DPD_CONTROL_SET_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: EDC_DPD_CONTROL :: UPDATE [02:02] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_DPD_CONTROL_UPDATE_MASK 0x00000004
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_DPD_CONTROL_UPDATE_SHIFT 2
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_DPD_CONTROL_UPDATE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: EDC_DPD_CONTROL :: MONITOR [01:01] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_DPD_CONTROL_MONITOR_MASK 0x00000002
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_DPD_CONTROL_MONITOR_SHIFT 1
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_DPD_CONTROL_MONITOR_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: EDC_DPD_CONTROL :: INIT [00:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_DPD_CONTROL_INIT_MASK 0x00000001
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_DPD_CONTROL_INIT_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_DPD_CONTROL_INIT_DEFAULT 0x00000000
-
-/***************************************************************************
- *EDC_DPD_STATUS - GDDR5M EDC digital phase detector status register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_0_0 :: EDC_DPD_STATUS :: reserved0 [31:29] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_DPD_STATUS_reserved0_MASK 0xe0000000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_DPD_STATUS_reserved0_SHIFT 29
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: EDC_DPD_STATUS :: CURRENT_DQS_PHASE [28:28] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_DPD_STATUS_CURRENT_DQS_PHASE_MASK 0x10000000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_DPD_STATUS_CURRENT_DQS_PHASE_SHIFT 28
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_DPD_STATUS_CURRENT_DQS_PHASE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: EDC_DPD_STATUS :: CURRENT_VDL_SETTING [27:20] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_DPD_STATUS_CURRENT_VDL_SETTING_MASK 0x0ff00000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_DPD_STATUS_CURRENT_VDL_SETTING_SHIFT 20
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_DPD_STATUS_CURRENT_VDL_SETTING_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: EDC_DPD_STATUS :: reserved1 [19:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_DPD_STATUS_reserved1_MASK 0x000e0000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_DPD_STATUS_reserved1_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: EDC_DPD_STATUS :: INIT_DQS_PHASE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_DPD_STATUS_INIT_DQS_PHASE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_DPD_STATUS_INIT_DQS_PHASE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_DPD_STATUS_INIT_DQS_PHASE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: EDC_DPD_STATUS :: INIT_VDL_SETTING [15:08] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_DPD_STATUS_INIT_VDL_SETTING_MASK 0x0000ff00
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_DPD_STATUS_INIT_VDL_SETTING_SHIFT 8
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_DPD_STATUS_INIT_VDL_SETTING_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: EDC_DPD_STATUS :: reserved2 [07:05] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_DPD_STATUS_reserved2_MASK 0x000000e0
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_DPD_STATUS_reserved2_SHIFT 5
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: EDC_DPD_STATUS :: MONITOR_ERROR [04:04] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_DPD_STATUS_MONITOR_ERROR_MASK 0x00000010
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_DPD_STATUS_MONITOR_ERROR_SHIFT 4
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_DPD_STATUS_MONITOR_ERROR_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: EDC_DPD_STATUS :: MONITOR_BUSY [03:03] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_DPD_STATUS_MONITOR_BUSY_MASK 0x00000008
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_DPD_STATUS_MONITOR_BUSY_SHIFT 3
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_DPD_STATUS_MONITOR_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: EDC_DPD_STATUS :: INIT_LOCK [02:02] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_DPD_STATUS_INIT_LOCK_MASK 0x00000004
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_DPD_STATUS_INIT_LOCK_SHIFT 2
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_DPD_STATUS_INIT_LOCK_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: EDC_DPD_STATUS :: INIT_BUSY [01:01] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_DPD_STATUS_INIT_BUSY_MASK 0x00000002
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_DPD_STATUS_INIT_BUSY_SHIFT 1
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_DPD_STATUS_INIT_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: EDC_DPD_STATUS :: INIT_DONE [00:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_DPD_STATUS_INIT_DONE_MASK 0x00000001
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_DPD_STATUS_INIT_DONE_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_DPD_STATUS_INIT_DONE_DEFAULT 0x00000000
-
-/***************************************************************************
- *EDC_DPD_OUT_CONTROL - GDDR5M EDC digital phase detector output signal control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_0_0 :: EDC_DPD_OUT_CONTROL :: reserved0 [31:20] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_DPD_OUT_CONTROL_reserved0_MASK 0xfff00000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_DPD_OUT_CONTROL_reserved0_SHIFT 20
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: EDC_DPD_OUT_CONTROL :: LOWER_LIMIT [19:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_DPD_OUT_CONTROL_LOWER_LIMIT_MASK 0x000ff000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_DPD_OUT_CONTROL_LOWER_LIMIT_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_DPD_OUT_CONTROL_LOWER_LIMIT_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: EDC_DPD_OUT_CONTROL :: UPPER_LIMIT [11:04] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_DPD_OUT_CONTROL_UPPER_LIMIT_MASK 0x00000ff0
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_DPD_OUT_CONTROL_UPPER_LIMIT_SHIFT 4
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_DPD_OUT_CONTROL_UPPER_LIMIT_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: EDC_DPD_OUT_CONTROL :: reserved1 [03:01] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_DPD_OUT_CONTROL_reserved1_MASK 0x0000000e
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_DPD_OUT_CONTROL_reserved1_SHIFT 1
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: EDC_DPD_OUT_CONTROL :: ENABLE [00:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_DPD_OUT_CONTROL_ENABLE_MASK 0x00000001
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_DPD_OUT_CONTROL_ENABLE_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_DPD_OUT_CONTROL_ENABLE_DEFAULT 0x00000000
-
-/***************************************************************************
- *EDC_DPD_OUT_STATUS - GDDR5M EDC digital phase detector output signal status register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_0_0 :: EDC_DPD_OUT_STATUS :: reserved0 [31:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_DPD_OUT_STATUS_reserved0_MASK 0xfffff000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_DPD_OUT_STATUS_reserved0_SHIFT 12
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: EDC_DPD_OUT_STATUS :: VDL_SETTING [11:04] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_DPD_OUT_STATUS_VDL_SETTING_MASK 0x00000ff0
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_DPD_OUT_STATUS_VDL_SETTING_SHIFT 4
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_DPD_OUT_STATUS_VDL_SETTING_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: EDC_DPD_OUT_STATUS :: reserved1 [03:01] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_DPD_OUT_STATUS_reserved1_MASK 0x0000000e
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_DPD_OUT_STATUS_reserved1_SHIFT 1
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: EDC_DPD_OUT_STATUS :: VALID [00:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_DPD_OUT_STATUS_VALID_MASK 0x00000001
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_DPD_OUT_STATUS_VALID_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_DPD_OUT_STATUS_VALID_DEFAULT 0x00000000
-
-/***************************************************************************
- *EDC_DPD_OUT_STATUS_CLEAR - GDDR5M EDC digital phase detector output signal status clear register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_0_0 :: EDC_DPD_OUT_STATUS_CLEAR :: reserved0 [31:01] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_DPD_OUT_STATUS_CLEAR_reserved0_MASK 0xfffffffe
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_DPD_OUT_STATUS_CLEAR_reserved0_SHIFT 1
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: EDC_DPD_OUT_STATUS_CLEAR :: CLEAR [00:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_DPD_OUT_STATUS_CLEAR_CLEAR_MASK 0x00000001
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_DPD_OUT_STATUS_CLEAR_CLEAR_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_DPD_OUT_STATUS_CLEAR_CLEAR_DEFAULT 0x00000000
-
-/***************************************************************************
- *EDC_CRC_CONTROL - GDDR5M EDC signal path CRC control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_0_0 :: EDC_CRC_CONTROL :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_CRC_CONTROL_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_CRC_CONTROL_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_CRC_CONTROL_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: EDC_CRC_CONTROL :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_CRC_CONTROL_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_CRC_CONTROL_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: EDC_CRC_CONTROL :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_CRC_CONTROL_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_CRC_CONTROL_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_CRC_CONTROL_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: EDC_CRC_CONTROL :: reserved1 [15:11] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_CRC_CONTROL_reserved1_MASK 0x0000f800
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_CRC_CONTROL_reserved1_SHIFT 11
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: EDC_CRC_CONTROL :: CRCWL [10:08] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_CRC_CONTROL_CRCWL_MASK 0x00000700
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_CRC_CONTROL_CRCWL_SHIFT 8
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_CRC_CONTROL_CRCWL_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: EDC_CRC_CONTROL :: reserved2 [07:06] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_CRC_CONTROL_reserved2_MASK 0x000000c0
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_CRC_CONTROL_reserved2_SHIFT 6
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: EDC_CRC_CONTROL :: CRCRL [05:04] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_CRC_CONTROL_CRCRL_MASK 0x00000030
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_CRC_CONTROL_CRCRL_SHIFT 4
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_CRC_CONTROL_CRCRL_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: EDC_CRC_CONTROL :: reserved3 [03:02] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_CRC_CONTROL_reserved3_MASK 0x0000000c
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_CRC_CONTROL_reserved3_SHIFT 2
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: EDC_CRC_CONTROL :: ENABLE_WR [01:01] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_CRC_CONTROL_ENABLE_WR_MASK 0x00000002
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_CRC_CONTROL_ENABLE_WR_SHIFT 1
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_CRC_CONTROL_ENABLE_WR_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: EDC_CRC_CONTROL :: ENABLE_RD [00:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_CRC_CONTROL_ENABLE_RD_MASK 0x00000001
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_CRC_CONTROL_ENABLE_RD_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_CRC_CONTROL_ENABLE_RD_DEFAULT 0x00000000
-
-/***************************************************************************
- *EDC_CRC_STATUS - GDDR5M EDC signal path CRC status register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_0_0 :: EDC_CRC_STATUS :: MISCOMPARE_EXP_CRC [31:24] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_CRC_STATUS_MISCOMPARE_EXP_CRC_MASK 0xff000000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_CRC_STATUS_MISCOMPARE_EXP_CRC_SHIFT 24
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: EDC_CRC_STATUS :: MISCOMPARE_CRC [23:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_CRC_STATUS_MISCOMPARE_CRC_MASK 0x00ff0000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_CRC_STATUS_MISCOMPARE_CRC_SHIFT 16
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: EDC_CRC_STATUS :: MOST_RECENT_CRC [15:08] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_CRC_STATUS_MOST_RECENT_CRC_MASK 0x0000ff00
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_CRC_STATUS_MOST_RECENT_CRC_SHIFT 8
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: EDC_CRC_STATUS :: reserved0 [07:05] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_CRC_STATUS_reserved0_MASK 0x000000e0
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_CRC_STATUS_reserved0_SHIFT 5
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: EDC_CRC_STATUS :: MISCOMPARE_TYPE [04:04] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_CRC_STATUS_MISCOMPARE_TYPE_MASK 0x00000010
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_CRC_STATUS_MISCOMPARE_TYPE_SHIFT 4
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: EDC_CRC_STATUS :: WR_FAIL [03:03] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_CRC_STATUS_WR_FAIL_MASK 0x00000008
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_CRC_STATUS_WR_FAIL_SHIFT 3
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: EDC_CRC_STATUS :: WR_PASS [02:02] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_CRC_STATUS_WR_PASS_MASK 0x00000004
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_CRC_STATUS_WR_PASS_SHIFT 2
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: EDC_CRC_STATUS :: RD_FAIL [01:01] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_CRC_STATUS_RD_FAIL_MASK 0x00000002
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_CRC_STATUS_RD_FAIL_SHIFT 1
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: EDC_CRC_STATUS :: RD_PASS [00:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_CRC_STATUS_RD_PASS_MASK 0x00000001
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_CRC_STATUS_RD_PASS_SHIFT 0
-
-/***************************************************************************
- *EDC_CRC_COUNT - GDDR5M EDC signal path CRC counter register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_0_0 :: EDC_CRC_COUNT :: WR_FAIL_COUNT [31:24] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_CRC_COUNT_WR_FAIL_COUNT_MASK 0xff000000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_CRC_COUNT_WR_FAIL_COUNT_SHIFT 24
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: EDC_CRC_COUNT :: WR_PASS_COUNT [23:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_CRC_COUNT_WR_PASS_COUNT_MASK 0x00ff0000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_CRC_COUNT_WR_PASS_COUNT_SHIFT 16
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: EDC_CRC_COUNT :: RD_FAIL_COUNT [15:08] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_CRC_COUNT_RD_FAIL_COUNT_MASK 0x0000ff00
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_CRC_COUNT_RD_FAIL_COUNT_SHIFT 8
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: EDC_CRC_COUNT :: RD_PASS_COUNT [07:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_CRC_COUNT_RD_PASS_COUNT_MASK 0x000000ff
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_CRC_COUNT_RD_PASS_COUNT_SHIFT 0
-
-/***************************************************************************
- *EDC_CRC_STATUS_CLEAR - GDDR5M EDC signal path CRC counter register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_0_0 :: EDC_CRC_STATUS_CLEAR :: reserved0 [31:01] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_CRC_STATUS_CLEAR_reserved0_MASK 0xfffffffe
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_CRC_STATUS_CLEAR_reserved0_SHIFT 1
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: EDC_CRC_STATUS_CLEAR :: CLEAR [00:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_CRC_STATUS_CLEAR_CLEAR_MASK 0x00000001
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_CRC_STATUS_CLEAR_CLEAR_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_CRC_STATUS_CLEAR_CLEAR_DEFAULT 0x00000000
-
-/***************************************************************************
- *CLOCK_ENABLE - Clock Enable Register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_0_0 :: CLOCK_ENABLE :: reserved0 [31:03] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_CLOCK_ENABLE_reserved0_MASK 0xfffffff8
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_CLOCK_ENABLE_reserved0_SHIFT 3
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: CLOCK_ENABLE :: TO_MC_CLOCK [02:02] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_CLOCK_ENABLE_TO_MC_CLOCK_MASK 0x00000004
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_CLOCK_ENABLE_TO_MC_CLOCK_SHIFT 2
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_CLOCK_ENABLE_TO_MC_CLOCK_DEFAULT 0x00000001
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: CLOCK_ENABLE :: FROM_MC_CLOCK [01:01] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_CLOCK_ENABLE_FROM_MC_CLOCK_MASK 0x00000002
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_CLOCK_ENABLE_FROM_MC_CLOCK_SHIFT 1
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_CLOCK_ENABLE_FROM_MC_CLOCK_DEFAULT 0x00000001
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: CLOCK_ENABLE :: BIT_CLOCK [00:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_CLOCK_ENABLE_BIT_CLOCK_MASK 0x00000001
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_CLOCK_ENABLE_BIT_CLOCK_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_CLOCK_ENABLE_BIT_CLOCK_DEFAULT 0x00000001
-
-/***************************************************************************
- *CLOCK_IDLE - Clock Idle Register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_0_0 :: CLOCK_IDLE :: reserved0 [31:03] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_CLOCK_IDLE_reserved0_MASK 0xfffffff8
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_CLOCK_IDLE_reserved0_SHIFT 3
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: CLOCK_IDLE :: TO_MC_CLOCK [02:02] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_CLOCK_IDLE_TO_MC_CLOCK_MASK 0x00000004
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_CLOCK_IDLE_TO_MC_CLOCK_SHIFT 2
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_CLOCK_IDLE_TO_MC_CLOCK_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: CLOCK_IDLE :: FROM_MC_CLOCK [01:01] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_CLOCK_IDLE_FROM_MC_CLOCK_MASK 0x00000002
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_CLOCK_IDLE_FROM_MC_CLOCK_SHIFT 1
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_CLOCK_IDLE_FROM_MC_CLOCK_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: CLOCK_IDLE :: BIT_CLOCK [00:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_CLOCK_IDLE_BIT_CLOCK_MASK 0x00000001
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_CLOCK_IDLE_BIT_CLOCK_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_CLOCK_IDLE_BIT_CLOCK_DEFAULT 0x00000000
-
-/***************************************************************************
- *BL_SPARE_REG - Byte-Lane Spare register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_0_0 :: BL_SPARE_REG :: reserved_for_eco0 [31:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_BL_SPARE_REG_reserved_for_eco0_MASK 0xffffffff
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_BL_SPARE_REG_reserved_for_eco0_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_BL_SPARE_REG_reserved_for_eco0_DEFAULT 0x00000000
-
-#endif /* #ifndef BCHP_DDR34_PHY_BYTE_LANE_0_0_H__ */
-
-/* End of File */
diff --git a/include/linux/brcmstb/7366b0/bchp_ddr34_phy_byte_lane_1_0.h b/include/linux/brcmstb/7366b0/bchp_ddr34_phy_byte_lane_1_0.h
deleted file mode 100644
index 09c07a8..0000000
--- a/include/linux/brcmstb/7366b0/bchp_ddr34_phy_byte_lane_1_0.h
+++ /dev/null
@@ -1,2482 +0,0 @@
-/***************************************************************************
- * Copyright (c) 1999-2014, Broadcom Corporation
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
- *
- * Module Description:
- * DO NOT EDIT THIS FILE DIRECTLY
- *
- * This module was generated magically with RDB from a source description
- * file. You must edit the source file for changes to be made to this file.
- *
- *
- * Date: Generated on Thu Apr 24 03:08:55 2014
- * Full Compile MD5 Checksum 1af2c2cf28828ece5496e1312aac0166
- * (minus title and desc)
- * MD5 Checksum 3203ffce85e3fc9a10f84123e54057b0
- *
- * Compiled with: RDB Utility combo_header.pl
- * RDB Parser 3.0
- * unknown unknown
- * Perl Interpreter 5.008008
- * Operating System linux
- *
- * Revision History:
- *
- * $brcm_Log: $
- *
- ***************************************************************************/
-
-#ifndef BCHP_DDR34_PHY_BYTE_LANE_1_0_H__
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_H__
-
-/***************************************************************************
- *DDR34_PHY_BYTE_LANE_1_0 - DDR34 Byte Lane #1 control registers
- ***************************************************************************/
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQS 0x00506600 /* Write channel DQS VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ0 0x00506604 /* Write channel DQ0 VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ1 0x00506608 /* Write channel DQ1 VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ2 0x0050660c /* Write channel DQ2 VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ3 0x00506610 /* Write channel DQ3 VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ4 0x00506614 /* Write channel DQ4 VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ5 0x00506618 /* Write channel DQ5 VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ6 0x0050661c /* Write channel DQ6 VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ7 0x00506620 /* Write channel DQ7 VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DM 0x00506624 /* Write channel DM VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_EDC 0x00506628 /* Write channel EDC VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQSP 0x0050662c /* Read channel DQSP VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQSN 0x00506630 /* Read channel DQSP VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ0P 0x00506634 /* Read channel DQ0-P VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ0N 0x00506638 /* Read channel DQ0-N VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ1P 0x0050663c /* Read channel DQ1-P VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ1N 0x00506640 /* Read channel DQ1-N VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ2P 0x00506644 /* Read channel DQ2-P VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ2N 0x00506648 /* Read channel DQ2-N VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ3P 0x0050664c /* Read channel DQ3-P VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ3N 0x00506650 /* Read channel DQ3-N VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ4P 0x00506654 /* Read channel DQ4-P VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ4N 0x00506658 /* Read channel DQ4-N VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ5P 0x0050665c /* Read channel DQ5-P VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ5N 0x00506660 /* Read channel DQ5-N VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ6P 0x00506664 /* Read channel DQ6-P VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ6N 0x00506668 /* Read channel DQ6-N VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ7P 0x0050666c /* Read channel DQ7-P VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ7N 0x00506670 /* Read channel DQ7-N VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DMP 0x00506674 /* Read channel DM-P VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DMN 0x00506678 /* Read channel DM-N VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_EDCP 0x0050667c /* Read channel EDC-P VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_EDCN 0x00506680 /* Read channel EDC-N VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_EN_CS0 0x00506684 /* Read channel CS_N[0] read enable VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_EN_CS1 0x00506688 /* Read channel CS_N[1] read enable VDL control register (used for reads when only cs1_n is active) */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_EN_CRC 0x0050668c /* Read channel GDDR5 CRC read enable VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CLK_CONTROL 0x00506690 /* DDR interface signal Write Leveling CLK VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_LDE_CONTROL 0x00506694 /* DDR interface signal Write Leveling Capture Enable VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_RD_EN_DLY_CYC 0x00506698 /* Read enable bit-clock cycle delay control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_WR_CHAN_DLY_CYC 0x0050669c /* Write leveling bit-clock cycle delay control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_READ_CONTROL 0x005066a0 /* Read channel datapath control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_READ_FIFO_ADDR 0x005066a4 /* Read fifo addresss pointer register */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_READ_FIFO_DATA 0x005066a8 /* Read fifo data register */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_READ_FIFO_DM_DBI 0x005066ac /* Read fifo dm/dbi register */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_READ_FIFO_STATUS 0x005066b0 /* Read fifo status register */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_READ_FIFO_CLEAR 0x005066b4 /* Read fifo status clear register */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_IDLE_PAD_CONTROL 0x005066b8 /* Idle mode SSTL pad control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_DRIVE_PAD_CTL 0x005066bc /* DQ, DM pad drive characteristics control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_DQSP_DRIVE_PAD_CTL 0x005066c0 /* DQS pad P rail drive characteristics control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_DQSN_DRIVE_PAD_CTL 0x005066c4 /* DQS pad N rail drive characteristics control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_DRIVE_PAD_CTL 0x005066c8 /* EDC pad drive characteristics control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_RD_EN_DRIVE_PAD_CTL 0x005066cc /* RD_EN, EDC_RD_EN read enable pad drive characteristics control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_STATIC_PAD_CTL 0x005066d0 /* pad rx and tx characteristics control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_DQ_RX_TRIM 0x005066d4 /* Receiver trim for DQ */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_MISC_RX_TRIM 0x005066d8 /* Receiver trim for miscellaneous pins */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_DQS_RX_TRIM 0x005066dc /* Rreceiver trim for DQS */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_WR_PREAMBLE_MODE 0x005066e0 /* Write cycle preamble control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_ODT_CONTROL 0x005066e4 /* Read channel ODT control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_LDO_CONFIG 0x005066e8 /* LDO Configuration register */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_DPD_CONTROL 0x005066ec /* GDDR5M EDC digital phase detector control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_DPD_STATUS 0x005066f0 /* GDDR5M EDC digital phase detector status register */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_DPD_OUT_CONTROL 0x005066f4 /* GDDR5M EDC digital phase detector output signal control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_DPD_OUT_STATUS 0x005066f8 /* GDDR5M EDC digital phase detector output signal status register */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_DPD_OUT_STATUS_CLEAR 0x005066fc /* GDDR5M EDC digital phase detector output signal status clear register */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_CRC_CONTROL 0x00506700 /* GDDR5M EDC signal path CRC control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_CRC_STATUS 0x00506704 /* GDDR5M EDC signal path CRC status register */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_CRC_COUNT 0x00506708 /* GDDR5M EDC signal path CRC counter register */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_CRC_STATUS_CLEAR 0x0050670c /* GDDR5M EDC signal path CRC counter register */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_CLOCK_ENABLE 0x00506710 /* Clock Enable Register */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_CLOCK_IDLE 0x00506714 /* Clock Idle Register */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_BL_SPARE_REG 0x00506718 /* Byte-Lane Spare register */
-
-/***************************************************************************
- *VDL_CONTROL_WR_DQS - Write channel DQS VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_WR_DQS :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQS_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQS_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQS_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_WR_DQS :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQS_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQS_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_WR_DQS :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQS_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQS_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQS_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_WR_DQS :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQS_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQS_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_WR_DQS :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQS_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQS_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQS_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_WR_DQS :: reserved2 [11:09] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQS_reserved2_MASK 0x00000e00
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQS_reserved2_SHIFT 9
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_WR_DQS :: VDL_STEP [08:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQS_VDL_STEP_MASK 0x000001ff
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQS_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQS_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_WR_DQ0 - Write channel DQ0 VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_WR_DQ0 :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ0_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ0_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ0_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_WR_DQ0 :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ0_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ0_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_WR_DQ0 :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ0_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ0_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ0_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_WR_DQ0 :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ0_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ0_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_WR_DQ0 :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ0_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ0_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ0_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_WR_DQ0 :: reserved2 [11:09] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ0_reserved2_MASK 0x00000e00
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ0_reserved2_SHIFT 9
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_WR_DQ0 :: VDL_STEP [08:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ0_VDL_STEP_MASK 0x000001ff
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ0_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ0_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_WR_DQ1 - Write channel DQ1 VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_WR_DQ1 :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ1_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ1_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ1_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_WR_DQ1 :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ1_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ1_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_WR_DQ1 :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ1_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ1_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ1_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_WR_DQ1 :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ1_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ1_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_WR_DQ1 :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ1_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ1_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ1_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_WR_DQ1 :: reserved2 [11:09] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ1_reserved2_MASK 0x00000e00
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ1_reserved2_SHIFT 9
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_WR_DQ1 :: VDL_STEP [08:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ1_VDL_STEP_MASK 0x000001ff
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ1_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ1_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_WR_DQ2 - Write channel DQ2 VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_WR_DQ2 :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ2_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ2_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ2_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_WR_DQ2 :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ2_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ2_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_WR_DQ2 :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ2_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ2_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ2_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_WR_DQ2 :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ2_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ2_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_WR_DQ2 :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ2_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ2_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ2_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_WR_DQ2 :: reserved2 [11:09] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ2_reserved2_MASK 0x00000e00
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ2_reserved2_SHIFT 9
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_WR_DQ2 :: VDL_STEP [08:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ2_VDL_STEP_MASK 0x000001ff
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ2_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ2_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_WR_DQ3 - Write channel DQ3 VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_WR_DQ3 :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ3_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ3_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ3_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_WR_DQ3 :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ3_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ3_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_WR_DQ3 :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ3_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ3_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ3_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_WR_DQ3 :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ3_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ3_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_WR_DQ3 :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ3_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ3_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ3_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_WR_DQ3 :: reserved2 [11:09] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ3_reserved2_MASK 0x00000e00
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ3_reserved2_SHIFT 9
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_WR_DQ3 :: VDL_STEP [08:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ3_VDL_STEP_MASK 0x000001ff
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ3_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ3_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_WR_DQ4 - Write channel DQ4 VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_WR_DQ4 :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ4_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ4_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ4_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_WR_DQ4 :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ4_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ4_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_WR_DQ4 :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ4_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ4_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ4_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_WR_DQ4 :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ4_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ4_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_WR_DQ4 :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ4_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ4_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ4_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_WR_DQ4 :: reserved2 [11:09] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ4_reserved2_MASK 0x00000e00
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ4_reserved2_SHIFT 9
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_WR_DQ4 :: VDL_STEP [08:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ4_VDL_STEP_MASK 0x000001ff
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ4_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ4_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_WR_DQ5 - Write channel DQ5 VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_WR_DQ5 :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ5_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ5_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ5_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_WR_DQ5 :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ5_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ5_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_WR_DQ5 :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ5_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ5_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ5_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_WR_DQ5 :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ5_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ5_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_WR_DQ5 :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ5_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ5_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ5_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_WR_DQ5 :: reserved2 [11:09] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ5_reserved2_MASK 0x00000e00
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ5_reserved2_SHIFT 9
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_WR_DQ5 :: VDL_STEP [08:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ5_VDL_STEP_MASK 0x000001ff
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ5_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ5_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_WR_DQ6 - Write channel DQ6 VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_WR_DQ6 :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ6_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ6_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ6_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_WR_DQ6 :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ6_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ6_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_WR_DQ6 :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ6_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ6_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ6_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_WR_DQ6 :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ6_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ6_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_WR_DQ6 :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ6_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ6_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ6_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_WR_DQ6 :: reserved2 [11:09] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ6_reserved2_MASK 0x00000e00
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ6_reserved2_SHIFT 9
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_WR_DQ6 :: VDL_STEP [08:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ6_VDL_STEP_MASK 0x000001ff
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ6_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ6_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_WR_DQ7 - Write channel DQ7 VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_WR_DQ7 :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ7_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ7_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ7_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_WR_DQ7 :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ7_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ7_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_WR_DQ7 :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ7_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ7_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ7_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_WR_DQ7 :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ7_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ7_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_WR_DQ7 :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ7_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ7_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ7_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_WR_DQ7 :: reserved2 [11:09] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ7_reserved2_MASK 0x00000e00
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ7_reserved2_SHIFT 9
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_WR_DQ7 :: VDL_STEP [08:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ7_VDL_STEP_MASK 0x000001ff
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ7_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ7_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_WR_DM - Write channel DM VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_WR_DM :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DM_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DM_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DM_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_WR_DM :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DM_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DM_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_WR_DM :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DM_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DM_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DM_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_WR_DM :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DM_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DM_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_WR_DM :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DM_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DM_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DM_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_WR_DM :: reserved2 [11:09] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DM_reserved2_MASK 0x00000e00
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DM_reserved2_SHIFT 9
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_WR_DM :: VDL_STEP [08:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DM_VDL_STEP_MASK 0x000001ff
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DM_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DM_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_WR_EDC - Write channel EDC VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_WR_EDC :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_EDC_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_EDC_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_EDC_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_WR_EDC :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_EDC_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_EDC_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_WR_EDC :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_EDC_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_EDC_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_EDC_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_WR_EDC :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_EDC_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_EDC_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_WR_EDC :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_EDC_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_EDC_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_EDC_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_WR_EDC :: reserved2 [11:09] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_EDC_reserved2_MASK 0x00000e00
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_EDC_reserved2_SHIFT 9
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_WR_EDC :: VDL_STEP [08:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_EDC_VDL_STEP_MASK 0x000001ff
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_EDC_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_EDC_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_RD_DQSP - Read channel DQSP VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_DQSP :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQSP_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQSP_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQSP_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_DQSP :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQSP_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQSP_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_DQSP :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQSP_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQSP_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQSP_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_DQSP :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQSP_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQSP_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_DQSP :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQSP_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQSP_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQSP_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_DQSP :: reserved2 [11:08] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQSP_reserved2_MASK 0x00000f00
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQSP_reserved2_SHIFT 8
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_DQSP :: VDL_STEP [07:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQSP_VDL_STEP_MASK 0x000000ff
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQSP_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQSP_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_RD_DQSN - Read channel DQSP VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_DQSN :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQSN_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQSN_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQSN_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_DQSN :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQSN_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQSN_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_DQSN :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQSN_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQSN_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQSN_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_DQSN :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQSN_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQSN_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_DQSN :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQSN_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQSN_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQSN_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_DQSN :: reserved2 [11:08] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQSN_reserved2_MASK 0x00000f00
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQSN_reserved2_SHIFT 8
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_DQSN :: VDL_STEP [07:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQSN_VDL_STEP_MASK 0x000000ff
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQSN_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQSN_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_RD_DQ0P - Read channel DQ0-P VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_DQ0P :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ0P_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ0P_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ0P_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_DQ0P :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ0P_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ0P_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_DQ0P :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ0P_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ0P_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ0P_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_DQ0P :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ0P_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ0P_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_DQ0P :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ0P_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ0P_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ0P_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_DQ0P :: reserved2 [11:08] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ0P_reserved2_MASK 0x00000f00
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ0P_reserved2_SHIFT 8
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_DQ0P :: VDL_STEP [07:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ0P_VDL_STEP_MASK 0x000000ff
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ0P_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ0P_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_RD_DQ0N - Read channel DQ0-N VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_DQ0N :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ0N_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ0N_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ0N_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_DQ0N :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ0N_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ0N_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_DQ0N :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ0N_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ0N_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ0N_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_DQ0N :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ0N_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ0N_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_DQ0N :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ0N_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ0N_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ0N_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_DQ0N :: reserved2 [11:08] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ0N_reserved2_MASK 0x00000f00
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ0N_reserved2_SHIFT 8
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_DQ0N :: VDL_STEP [07:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ0N_VDL_STEP_MASK 0x000000ff
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ0N_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ0N_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_RD_DQ1P - Read channel DQ1-P VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_DQ1P :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ1P_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ1P_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ1P_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_DQ1P :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ1P_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ1P_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_DQ1P :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ1P_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ1P_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ1P_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_DQ1P :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ1P_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ1P_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_DQ1P :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ1P_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ1P_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ1P_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_DQ1P :: reserved2 [11:08] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ1P_reserved2_MASK 0x00000f00
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ1P_reserved2_SHIFT 8
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_DQ1P :: VDL_STEP [07:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ1P_VDL_STEP_MASK 0x000000ff
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ1P_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ1P_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_RD_DQ1N - Read channel DQ1-N VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_DQ1N :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ1N_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ1N_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ1N_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_DQ1N :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ1N_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ1N_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_DQ1N :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ1N_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ1N_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ1N_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_DQ1N :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ1N_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ1N_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_DQ1N :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ1N_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ1N_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ1N_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_DQ1N :: reserved2 [11:08] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ1N_reserved2_MASK 0x00000f00
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ1N_reserved2_SHIFT 8
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_DQ1N :: VDL_STEP [07:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ1N_VDL_STEP_MASK 0x000000ff
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ1N_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ1N_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_RD_DQ2P - Read channel DQ2-P VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_DQ2P :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ2P_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ2P_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ2P_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_DQ2P :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ2P_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ2P_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_DQ2P :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ2P_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ2P_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ2P_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_DQ2P :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ2P_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ2P_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_DQ2P :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ2P_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ2P_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ2P_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_DQ2P :: reserved2 [11:08] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ2P_reserved2_MASK 0x00000f00
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ2P_reserved2_SHIFT 8
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_DQ2P :: VDL_STEP [07:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ2P_VDL_STEP_MASK 0x000000ff
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ2P_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ2P_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_RD_DQ2N - Read channel DQ2-N VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_DQ2N :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ2N_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ2N_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ2N_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_DQ2N :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ2N_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ2N_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_DQ2N :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ2N_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ2N_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ2N_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_DQ2N :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ2N_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ2N_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_DQ2N :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ2N_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ2N_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ2N_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_DQ2N :: reserved2 [11:08] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ2N_reserved2_MASK 0x00000f00
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ2N_reserved2_SHIFT 8
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_DQ2N :: VDL_STEP [07:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ2N_VDL_STEP_MASK 0x000000ff
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ2N_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ2N_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_RD_DQ3P - Read channel DQ3-P VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_DQ3P :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ3P_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ3P_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ3P_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_DQ3P :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ3P_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ3P_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_DQ3P :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ3P_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ3P_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ3P_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_DQ3P :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ3P_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ3P_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_DQ3P :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ3P_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ3P_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ3P_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_DQ3P :: reserved2 [11:08] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ3P_reserved2_MASK 0x00000f00
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ3P_reserved2_SHIFT 8
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_DQ3P :: VDL_STEP [07:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ3P_VDL_STEP_MASK 0x000000ff
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ3P_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ3P_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_RD_DQ3N - Read channel DQ3-N VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_DQ3N :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ3N_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ3N_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ3N_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_DQ3N :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ3N_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ3N_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_DQ3N :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ3N_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ3N_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ3N_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_DQ3N :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ3N_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ3N_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_DQ3N :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ3N_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ3N_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ3N_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_DQ3N :: reserved2 [11:08] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ3N_reserved2_MASK 0x00000f00
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ3N_reserved2_SHIFT 8
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_DQ3N :: VDL_STEP [07:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ3N_VDL_STEP_MASK 0x000000ff
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ3N_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ3N_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_RD_DQ4P - Read channel DQ4-P VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_DQ4P :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ4P_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ4P_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ4P_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_DQ4P :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ4P_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ4P_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_DQ4P :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ4P_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ4P_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ4P_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_DQ4P :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ4P_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ4P_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_DQ4P :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ4P_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ4P_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ4P_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_DQ4P :: reserved2 [11:08] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ4P_reserved2_MASK 0x00000f00
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ4P_reserved2_SHIFT 8
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_DQ4P :: VDL_STEP [07:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ4P_VDL_STEP_MASK 0x000000ff
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ4P_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ4P_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_RD_DQ4N - Read channel DQ4-N VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_DQ4N :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ4N_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ4N_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ4N_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_DQ4N :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ4N_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ4N_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_DQ4N :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ4N_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ4N_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ4N_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_DQ4N :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ4N_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ4N_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_DQ4N :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ4N_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ4N_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ4N_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_DQ4N :: reserved2 [11:08] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ4N_reserved2_MASK 0x00000f00
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ4N_reserved2_SHIFT 8
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_DQ4N :: VDL_STEP [07:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ4N_VDL_STEP_MASK 0x000000ff
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ4N_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ4N_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_RD_DQ5P - Read channel DQ5-P VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_DQ5P :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ5P_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ5P_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ5P_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_DQ5P :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ5P_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ5P_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_DQ5P :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ5P_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ5P_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ5P_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_DQ5P :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ5P_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ5P_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_DQ5P :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ5P_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ5P_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ5P_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_DQ5P :: reserved2 [11:08] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ5P_reserved2_MASK 0x00000f00
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ5P_reserved2_SHIFT 8
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_DQ5P :: VDL_STEP [07:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ5P_VDL_STEP_MASK 0x000000ff
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ5P_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ5P_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_RD_DQ5N - Read channel DQ5-N VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_DQ5N :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ5N_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ5N_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ5N_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_DQ5N :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ5N_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ5N_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_DQ5N :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ5N_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ5N_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ5N_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_DQ5N :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ5N_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ5N_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_DQ5N :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ5N_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ5N_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ5N_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_DQ5N :: reserved2 [11:08] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ5N_reserved2_MASK 0x00000f00
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ5N_reserved2_SHIFT 8
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_DQ5N :: VDL_STEP [07:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ5N_VDL_STEP_MASK 0x000000ff
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ5N_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ5N_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_RD_DQ6P - Read channel DQ6-P VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_DQ6P :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ6P_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ6P_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ6P_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_DQ6P :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ6P_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ6P_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_DQ6P :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ6P_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ6P_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ6P_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_DQ6P :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ6P_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ6P_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_DQ6P :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ6P_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ6P_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ6P_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_DQ6P :: reserved2 [11:08] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ6P_reserved2_MASK 0x00000f00
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ6P_reserved2_SHIFT 8
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_DQ6P :: VDL_STEP [07:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ6P_VDL_STEP_MASK 0x000000ff
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ6P_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ6P_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_RD_DQ6N - Read channel DQ6-N VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_DQ6N :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ6N_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ6N_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ6N_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_DQ6N :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ6N_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ6N_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_DQ6N :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ6N_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ6N_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ6N_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_DQ6N :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ6N_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ6N_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_DQ6N :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ6N_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ6N_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ6N_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_DQ6N :: reserved2 [11:08] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ6N_reserved2_MASK 0x00000f00
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ6N_reserved2_SHIFT 8
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_DQ6N :: VDL_STEP [07:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ6N_VDL_STEP_MASK 0x000000ff
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ6N_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ6N_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_RD_DQ7P - Read channel DQ7-P VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_DQ7P :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ7P_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ7P_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ7P_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_DQ7P :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ7P_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ7P_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_DQ7P :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ7P_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ7P_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ7P_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_DQ7P :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ7P_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ7P_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_DQ7P :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ7P_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ7P_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ7P_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_DQ7P :: reserved2 [11:08] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ7P_reserved2_MASK 0x00000f00
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ7P_reserved2_SHIFT 8
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_DQ7P :: VDL_STEP [07:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ7P_VDL_STEP_MASK 0x000000ff
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ7P_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ7P_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_RD_DQ7N - Read channel DQ7-N VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_DQ7N :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ7N_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ7N_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ7N_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_DQ7N :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ7N_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ7N_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_DQ7N :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ7N_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ7N_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ7N_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_DQ7N :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ7N_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ7N_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_DQ7N :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ7N_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ7N_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ7N_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_DQ7N :: reserved2 [11:08] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ7N_reserved2_MASK 0x00000f00
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ7N_reserved2_SHIFT 8
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_DQ7N :: VDL_STEP [07:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ7N_VDL_STEP_MASK 0x000000ff
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ7N_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ7N_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_RD_DMP - Read channel DM-P VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_DMP :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DMP_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DMP_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DMP_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_DMP :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DMP_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DMP_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_DMP :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DMP_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DMP_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DMP_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_DMP :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DMP_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DMP_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_DMP :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DMP_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DMP_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DMP_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_DMP :: reserved2 [11:08] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DMP_reserved2_MASK 0x00000f00
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DMP_reserved2_SHIFT 8
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_DMP :: VDL_STEP [07:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DMP_VDL_STEP_MASK 0x000000ff
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DMP_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DMP_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_RD_DMN - Read channel DM-N VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_DMN :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DMN_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DMN_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DMN_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_DMN :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DMN_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DMN_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_DMN :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DMN_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DMN_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DMN_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_DMN :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DMN_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DMN_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_DMN :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DMN_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DMN_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DMN_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_DMN :: reserved2 [11:08] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DMN_reserved2_MASK 0x00000f00
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DMN_reserved2_SHIFT 8
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_DMN :: VDL_STEP [07:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DMN_VDL_STEP_MASK 0x000000ff
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DMN_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DMN_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_RD_EDCP - Read channel EDC-P VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_EDCP :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_EDCP_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_EDCP_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_EDCP_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_EDCP :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_EDCP_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_EDCP_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_EDCP :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_EDCP_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_EDCP_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_EDCP_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_EDCP :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_EDCP_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_EDCP_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_EDCP :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_EDCP_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_EDCP_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_EDCP_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_EDCP :: reserved2 [11:08] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_EDCP_reserved2_MASK 0x00000f00
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_EDCP_reserved2_SHIFT 8
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_EDCP :: VDL_STEP [07:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_EDCP_VDL_STEP_MASK 0x000000ff
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_EDCP_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_EDCP_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_RD_EDCN - Read channel EDC-N VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_EDCN :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_EDCN_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_EDCN_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_EDCN_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_EDCN :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_EDCN_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_EDCN_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_EDCN :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_EDCN_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_EDCN_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_EDCN_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_EDCN :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_EDCN_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_EDCN_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_EDCN :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_EDCN_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_EDCN_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_EDCN_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_EDCN :: reserved2 [11:08] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_EDCN_reserved2_MASK 0x00000f00
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_EDCN_reserved2_SHIFT 8
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_EDCN :: VDL_STEP [07:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_EDCN_VDL_STEP_MASK 0x000000ff
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_EDCN_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_EDCN_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_RD_EN_CS0 - Read channel CS_N[0] read enable VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_EN_CS0 :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_EN_CS0_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_EN_CS0_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_EN_CS0_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_EN_CS0 :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_EN_CS0_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_EN_CS0_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_EN_CS0 :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_EN_CS0_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_EN_CS0_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_EN_CS0_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_EN_CS0 :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_EN_CS0_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_EN_CS0_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_EN_CS0 :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_EN_CS0_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_EN_CS0_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_EN_CS0_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_EN_CS0 :: reserved2 [11:08] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_EN_CS0_reserved2_MASK 0x00000f00
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_EN_CS0_reserved2_SHIFT 8
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_EN_CS0 :: VDL_STEP [07:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_EN_CS0_VDL_STEP_MASK 0x000000ff
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_EN_CS0_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_EN_CS0_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_RD_EN_CS1 - Read channel CS_N[1] read enable VDL control register (used for reads when only cs1_n is active)
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_EN_CS1 :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_EN_CS1_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_EN_CS1_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_EN_CS1_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_EN_CS1 :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_EN_CS1_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_EN_CS1_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_EN_CS1 :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_EN_CS1_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_EN_CS1_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_EN_CS1_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_EN_CS1 :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_EN_CS1_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_EN_CS1_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_EN_CS1 :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_EN_CS1_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_EN_CS1_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_EN_CS1_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_EN_CS1 :: reserved2 [11:08] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_EN_CS1_reserved2_MASK 0x00000f00
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_EN_CS1_reserved2_SHIFT 8
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_EN_CS1 :: VDL_STEP [07:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_EN_CS1_VDL_STEP_MASK 0x000000ff
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_EN_CS1_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_EN_CS1_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_RD_EN_CRC - Read channel GDDR5 CRC read enable VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_EN_CRC :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_EN_CRC_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_EN_CRC_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_EN_CRC_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_EN_CRC :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_EN_CRC_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_EN_CRC_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_EN_CRC :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_EN_CRC_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_EN_CRC_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_EN_CRC_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_EN_CRC :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_EN_CRC_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_EN_CRC_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_EN_CRC :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_EN_CRC_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_EN_CRC_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_EN_CRC_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_EN_CRC :: reserved2 [11:08] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_EN_CRC_reserved2_MASK 0x00000f00
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_EN_CRC_reserved2_SHIFT 8
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_EN_CRC :: VDL_STEP [07:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_EN_CRC_VDL_STEP_MASK 0x000000ff
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_EN_CRC_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_EN_CRC_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CLK_CONTROL - DDR interface signal Write Leveling CLK VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CLK_CONTROL :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CLK_CONTROL_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CLK_CONTROL_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CLK_CONTROL_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CLK_CONTROL :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CLK_CONTROL_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CLK_CONTROL_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CLK_CONTROL :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CLK_CONTROL_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CLK_CONTROL_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CLK_CONTROL_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CLK_CONTROL :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CLK_CONTROL_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CLK_CONTROL_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CLK_CONTROL :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CLK_CONTROL_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CLK_CONTROL_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CLK_CONTROL_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CLK_CONTROL :: reserved2 [11:09] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CLK_CONTROL_reserved2_MASK 0x00000e00
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CLK_CONTROL_reserved2_SHIFT 9
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CLK_CONTROL :: VDL_STEP [08:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CLK_CONTROL_VDL_STEP_MASK 0x000001ff
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CLK_CONTROL_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CLK_CONTROL_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_LDE_CONTROL - DDR interface signal Write Leveling Capture Enable VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_LDE_CONTROL :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_LDE_CONTROL_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_LDE_CONTROL_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_LDE_CONTROL_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_LDE_CONTROL :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_LDE_CONTROL_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_LDE_CONTROL_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_LDE_CONTROL :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_LDE_CONTROL_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_LDE_CONTROL_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_LDE_CONTROL_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_LDE_CONTROL :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_LDE_CONTROL_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_LDE_CONTROL_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_LDE_CONTROL :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_LDE_CONTROL_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_LDE_CONTROL_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_LDE_CONTROL_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_LDE_CONTROL :: reserved2 [11:09] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_LDE_CONTROL_reserved2_MASK 0x00000e00
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_LDE_CONTROL_reserved2_SHIFT 9
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_LDE_CONTROL :: VDL_STEP [08:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_LDE_CONTROL_VDL_STEP_MASK 0x000001ff
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_LDE_CONTROL_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_LDE_CONTROL_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *RD_EN_DLY_CYC - Read enable bit-clock cycle delay control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_1_0 :: RD_EN_DLY_CYC :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_RD_EN_DLY_CYC_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_RD_EN_DLY_CYC_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_RD_EN_DLY_CYC_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: RD_EN_DLY_CYC :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_RD_EN_DLY_CYC_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_RD_EN_DLY_CYC_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: RD_EN_DLY_CYC :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_RD_EN_DLY_CYC_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_RD_EN_DLY_CYC_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_RD_EN_DLY_CYC_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: RD_EN_DLY_CYC :: reserved1 [15:14] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_RD_EN_DLY_CYC_reserved1_MASK 0x0000c000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_RD_EN_DLY_CYC_reserved1_SHIFT 14
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: RD_EN_DLY_CYC :: CRC_CYCLES [13:10] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_RD_EN_DLY_CYC_CRC_CYCLES_MASK 0x00003c00
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_RD_EN_DLY_CYC_CRC_CYCLES_SHIFT 10
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_RD_EN_DLY_CYC_CRC_CYCLES_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: RD_EN_DLY_CYC :: reserved2 [09:09] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_RD_EN_DLY_CYC_reserved2_MASK 0x00000200
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_RD_EN_DLY_CYC_reserved2_SHIFT 9
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: RD_EN_DLY_CYC :: ENABLE_CS1 [08:08] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_RD_EN_DLY_CYC_ENABLE_CS1_MASK 0x00000100
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_RD_EN_DLY_CYC_ENABLE_CS1_SHIFT 8
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_RD_EN_DLY_CYC_ENABLE_CS1_DEFAULT 0x00000001
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: RD_EN_DLY_CYC :: CS1_CYCLES [07:04] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_RD_EN_DLY_CYC_CS1_CYCLES_MASK 0x000000f0
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_RD_EN_DLY_CYC_CS1_CYCLES_SHIFT 4
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_RD_EN_DLY_CYC_CS1_CYCLES_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: RD_EN_DLY_CYC :: CS0_CYCLES [03:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_RD_EN_DLY_CYC_CS0_CYCLES_MASK 0x0000000f
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_RD_EN_DLY_CYC_CS0_CYCLES_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_RD_EN_DLY_CYC_CS0_CYCLES_DEFAULT 0x00000000
-
-/***************************************************************************
- *WR_CHAN_DLY_CYC - Write leveling bit-clock cycle delay control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_1_0 :: WR_CHAN_DLY_CYC :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_WR_CHAN_DLY_CYC_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_WR_CHAN_DLY_CYC_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_WR_CHAN_DLY_CYC_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: WR_CHAN_DLY_CYC :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_WR_CHAN_DLY_CYC_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_WR_CHAN_DLY_CYC_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: WR_CHAN_DLY_CYC :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_WR_CHAN_DLY_CYC_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_WR_CHAN_DLY_CYC_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_WR_CHAN_DLY_CYC_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: WR_CHAN_DLY_CYC :: reserved1 [15:08] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_WR_CHAN_DLY_CYC_reserved1_MASK 0x0000ff00
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_WR_CHAN_DLY_CYC_reserved1_SHIFT 8
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: WR_CHAN_DLY_CYC :: DQ_CYCLES [07:04] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_WR_CHAN_DLY_CYC_DQ_CYCLES_MASK 0x000000f0
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_WR_CHAN_DLY_CYC_DQ_CYCLES_SHIFT 4
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_WR_CHAN_DLY_CYC_DQ_CYCLES_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: WR_CHAN_DLY_CYC :: reserved2 [03:03] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_WR_CHAN_DLY_CYC_reserved2_MASK 0x00000008
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_WR_CHAN_DLY_CYC_reserved2_SHIFT 3
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: WR_CHAN_DLY_CYC :: CYCLES [02:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_WR_CHAN_DLY_CYC_CYCLES_MASK 0x00000007
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_WR_CHAN_DLY_CYC_CYCLES_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_WR_CHAN_DLY_CYC_CYCLES_DEFAULT 0x00000000
-
-/***************************************************************************
- *READ_CONTROL - Read channel datapath control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_1_0 :: READ_CONTROL :: reserved0 [31:05] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_READ_CONTROL_reserved0_MASK 0xffffffe0
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_READ_CONTROL_reserved0_SHIFT 5
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: READ_CONTROL :: MODE [04:04] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_READ_CONTROL_MODE_MASK 0x00000010
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_READ_CONTROL_MODE_SHIFT 4
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_READ_CONTROL_MODE_DEFAULT 0x00000001
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: READ_CONTROL :: RD_EN_MODE [03:03] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_READ_CONTROL_RD_EN_MODE_MASK 0x00000008
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_READ_CONTROL_RD_EN_MODE_SHIFT 3
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_READ_CONTROL_RD_EN_MODE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: READ_CONTROL :: RD_DATA_DLY [02:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_READ_CONTROL_RD_DATA_DLY_MASK 0x00000007
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_READ_CONTROL_RD_DATA_DLY_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_READ_CONTROL_RD_DATA_DLY_DEFAULT 0x00000007
-
-/***************************************************************************
- *READ_FIFO_ADDR - Read fifo addresss pointer register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_1_0 :: READ_FIFO_ADDR :: reserved0 [31:03] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_READ_FIFO_ADDR_reserved0_MASK 0xfffffff8
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_READ_FIFO_ADDR_reserved0_SHIFT 3
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: READ_FIFO_ADDR :: ADDR [02:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_READ_FIFO_ADDR_ADDR_MASK 0x00000007
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_READ_FIFO_ADDR_ADDR_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_READ_FIFO_ADDR_ADDR_DEFAULT 0x00000000
-
-/***************************************************************************
- *READ_FIFO_DATA - Read fifo data register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_1_0 :: READ_FIFO_DATA :: DATA [31:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_READ_FIFO_DATA_DATA_MASK 0xffffffff
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_READ_FIFO_DATA_DATA_SHIFT 0
-
-/***************************************************************************
- *READ_FIFO_DM_DBI - Read fifo dm/dbi register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_1_0 :: READ_FIFO_DM_DBI :: reserved0 [31:04] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_READ_FIFO_DM_DBI_reserved0_MASK 0xfffffff0
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_READ_FIFO_DM_DBI_reserved0_SHIFT 4
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: READ_FIFO_DM_DBI :: DM_DBI [03:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_READ_FIFO_DM_DBI_DM_DBI_MASK 0x0000000f
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_READ_FIFO_DM_DBI_DM_DBI_SHIFT 0
-
-/***************************************************************************
- *READ_FIFO_STATUS - Read fifo status register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_1_0 :: READ_FIFO_STATUS :: reserved0 [31:02] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_READ_FIFO_STATUS_reserved0_MASK 0xfffffffc
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_READ_FIFO_STATUS_reserved0_SHIFT 2
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: READ_FIFO_STATUS :: OVERFLOW [01:01] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_READ_FIFO_STATUS_OVERFLOW_MASK 0x00000002
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_READ_FIFO_STATUS_OVERFLOW_SHIFT 1
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_READ_FIFO_STATUS_OVERFLOW_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: READ_FIFO_STATUS :: UNDERFLOW [00:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_READ_FIFO_STATUS_UNDERFLOW_MASK 0x00000001
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_READ_FIFO_STATUS_UNDERFLOW_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_READ_FIFO_STATUS_UNDERFLOW_DEFAULT 0x00000000
-
-/***************************************************************************
- *READ_FIFO_CLEAR - Read fifo status clear register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_1_0 :: READ_FIFO_CLEAR :: reserved0 [31:01] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_READ_FIFO_CLEAR_reserved0_MASK 0xfffffffe
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_READ_FIFO_CLEAR_reserved0_SHIFT 1
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: READ_FIFO_CLEAR :: CLEAR [00:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_READ_FIFO_CLEAR_CLEAR_MASK 0x00000001
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_READ_FIFO_CLEAR_CLEAR_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_READ_FIFO_CLEAR_CLEAR_DEFAULT 0x00000000
-
-/***************************************************************************
- *IDLE_PAD_CONTROL - Idle mode SSTL pad control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_1_0 :: IDLE_PAD_CONTROL :: IDLE [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_IDLE_PAD_CONTROL_IDLE_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_IDLE_PAD_CONTROL_IDLE_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_IDLE_PAD_CONTROL_IDLE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: IDLE_PAD_CONTROL :: reserved0 [30:20] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_IDLE_PAD_CONTROL_reserved0_MASK 0x7ff00000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_IDLE_PAD_CONTROL_reserved0_SHIFT 20
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: IDLE_PAD_CONTROL :: AUTO_DQ_RXENB_MODE [19:18] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_IDLE_PAD_CONTROL_AUTO_DQ_RXENB_MODE_MASK 0x000c0000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_IDLE_PAD_CONTROL_AUTO_DQ_RXENB_MODE_SHIFT 18
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_IDLE_PAD_CONTROL_AUTO_DQ_RXENB_MODE_DEFAULT 0x00000003
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: IDLE_PAD_CONTROL :: AUTO_DQ_IDDQ_MODE [17:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_IDLE_PAD_CONTROL_AUTO_DQ_IDDQ_MODE_MASK 0x00030000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_IDLE_PAD_CONTROL_AUTO_DQ_IDDQ_MODE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_IDLE_PAD_CONTROL_AUTO_DQ_IDDQ_MODE_DEFAULT 0x00000003
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: IDLE_PAD_CONTROL :: IO_IDLE_ENABLE [15:04] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_IDLE_PAD_CONTROL_IO_IDLE_ENABLE_MASK 0x0000fff0
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_IDLE_PAD_CONTROL_IO_IDLE_ENABLE_SHIFT 4
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_IDLE_PAD_CONTROL_IO_IDLE_ENABLE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: IDLE_PAD_CONTROL :: RXENB [03:03] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_IDLE_PAD_CONTROL_RXENB_MASK 0x00000008
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_IDLE_PAD_CONTROL_RXENB_SHIFT 3
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_IDLE_PAD_CONTROL_RXENB_DEFAULT 0x00000001
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: IDLE_PAD_CONTROL :: IDDQ [02:02] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_IDLE_PAD_CONTROL_IDDQ_MASK 0x00000004
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_IDLE_PAD_CONTROL_IDDQ_SHIFT 2
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_IDLE_PAD_CONTROL_IDDQ_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: IDLE_PAD_CONTROL :: DOUT_N [01:01] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_IDLE_PAD_CONTROL_DOUT_N_MASK 0x00000002
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_IDLE_PAD_CONTROL_DOUT_N_SHIFT 1
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_IDLE_PAD_CONTROL_DOUT_N_DEFAULT 0x00000001
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: IDLE_PAD_CONTROL :: DOUT_P [00:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_IDLE_PAD_CONTROL_DOUT_P_MASK 0x00000001
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_IDLE_PAD_CONTROL_DOUT_P_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_IDLE_PAD_CONTROL_DOUT_P_DEFAULT 0x00000000
-
-/***************************************************************************
- *DRIVE_PAD_CTL - DQ, DM pad drive characteristics control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_1_0 :: DRIVE_PAD_CTL :: reserved0 [31:30] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_DRIVE_PAD_CTL_reserved0_MASK 0xc0000000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_DRIVE_PAD_CTL_reserved0_SHIFT 30
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: DRIVE_PAD_CTL :: BL_PD_IDLE_STRENGTH [29:25] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_DRIVE_PAD_CTL_BL_PD_IDLE_STRENGTH_MASK 0x3e000000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_DRIVE_PAD_CTL_BL_PD_IDLE_STRENGTH_SHIFT 25
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_DRIVE_PAD_CTL_BL_PD_IDLE_STRENGTH_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: DRIVE_PAD_CTL :: BL_ND_IDLE_STRENGTH [24:20] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_DRIVE_PAD_CTL_BL_ND_IDLE_STRENGTH_MASK 0x01f00000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_DRIVE_PAD_CTL_BL_ND_IDLE_STRENGTH_SHIFT 20
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_DRIVE_PAD_CTL_BL_ND_IDLE_STRENGTH_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: DRIVE_PAD_CTL :: BL_PD_TERM_STRENGTH [19:15] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_DRIVE_PAD_CTL_BL_PD_TERM_STRENGTH_MASK 0x000f8000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_DRIVE_PAD_CTL_BL_PD_TERM_STRENGTH_SHIFT 15
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_DRIVE_PAD_CTL_BL_PD_TERM_STRENGTH_DEFAULT 0x00000008
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: DRIVE_PAD_CTL :: BL_ND_TERM_STRENGTH [14:10] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_DRIVE_PAD_CTL_BL_ND_TERM_STRENGTH_MASK 0x00007c00
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_DRIVE_PAD_CTL_BL_ND_TERM_STRENGTH_SHIFT 10
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_DRIVE_PAD_CTL_BL_ND_TERM_STRENGTH_DEFAULT 0x00000008
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: DRIVE_PAD_CTL :: BL_PD_STRENGTH [09:05] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_DRIVE_PAD_CTL_BL_PD_STRENGTH_MASK 0x000003e0
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_DRIVE_PAD_CTL_BL_PD_STRENGTH_SHIFT 5
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_DRIVE_PAD_CTL_BL_PD_STRENGTH_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: DRIVE_PAD_CTL :: BL_ND_STRENGTH [04:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_DRIVE_PAD_CTL_BL_ND_STRENGTH_MASK 0x0000001f
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_DRIVE_PAD_CTL_BL_ND_STRENGTH_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_DRIVE_PAD_CTL_BL_ND_STRENGTH_DEFAULT 0x00000000
-
-/***************************************************************************
- *DQSP_DRIVE_PAD_CTL - DQS pad P rail drive characteristics control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_1_0 :: DQSP_DRIVE_PAD_CTL :: reserved0 [31:30] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_DQSP_DRIVE_PAD_CTL_reserved0_MASK 0xc0000000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_DQSP_DRIVE_PAD_CTL_reserved0_SHIFT 30
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: DQSP_DRIVE_PAD_CTL :: BL_PD_IDLE_STRENGTH [29:25] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_DQSP_DRIVE_PAD_CTL_BL_PD_IDLE_STRENGTH_MASK 0x3e000000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_DQSP_DRIVE_PAD_CTL_BL_PD_IDLE_STRENGTH_SHIFT 25
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_DQSP_DRIVE_PAD_CTL_BL_PD_IDLE_STRENGTH_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: DQSP_DRIVE_PAD_CTL :: BL_ND_IDLE_STRENGTH [24:20] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_DQSP_DRIVE_PAD_CTL_BL_ND_IDLE_STRENGTH_MASK 0x01f00000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_DQSP_DRIVE_PAD_CTL_BL_ND_IDLE_STRENGTH_SHIFT 20
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_DQSP_DRIVE_PAD_CTL_BL_ND_IDLE_STRENGTH_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: DQSP_DRIVE_PAD_CTL :: BL_PD_TERM_STRENGTH [19:15] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_DQSP_DRIVE_PAD_CTL_BL_PD_TERM_STRENGTH_MASK 0x000f8000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_DQSP_DRIVE_PAD_CTL_BL_PD_TERM_STRENGTH_SHIFT 15
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_DQSP_DRIVE_PAD_CTL_BL_PD_TERM_STRENGTH_DEFAULT 0x00000008
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: DQSP_DRIVE_PAD_CTL :: BL_ND_TERM_STRENGTH [14:10] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_DQSP_DRIVE_PAD_CTL_BL_ND_TERM_STRENGTH_MASK 0x00007c00
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_DQSP_DRIVE_PAD_CTL_BL_ND_TERM_STRENGTH_SHIFT 10
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_DQSP_DRIVE_PAD_CTL_BL_ND_TERM_STRENGTH_DEFAULT 0x00000008
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: DQSP_DRIVE_PAD_CTL :: BL_PD_STRENGTH [09:05] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_DQSP_DRIVE_PAD_CTL_BL_PD_STRENGTH_MASK 0x000003e0
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_DQSP_DRIVE_PAD_CTL_BL_PD_STRENGTH_SHIFT 5
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_DQSP_DRIVE_PAD_CTL_BL_PD_STRENGTH_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: DQSP_DRIVE_PAD_CTL :: BL_ND_STRENGTH [04:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_DQSP_DRIVE_PAD_CTL_BL_ND_STRENGTH_MASK 0x0000001f
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_DQSP_DRIVE_PAD_CTL_BL_ND_STRENGTH_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_DQSP_DRIVE_PAD_CTL_BL_ND_STRENGTH_DEFAULT 0x00000000
-
-/***************************************************************************
- *DQSN_DRIVE_PAD_CTL - DQS pad N rail drive characteristics control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_1_0 :: DQSN_DRIVE_PAD_CTL :: reserved0 [31:30] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_DQSN_DRIVE_PAD_CTL_reserved0_MASK 0xc0000000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_DQSN_DRIVE_PAD_CTL_reserved0_SHIFT 30
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: DQSN_DRIVE_PAD_CTL :: BL_PD_IDLE_STRENGTH [29:25] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_DQSN_DRIVE_PAD_CTL_BL_PD_IDLE_STRENGTH_MASK 0x3e000000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_DQSN_DRIVE_PAD_CTL_BL_PD_IDLE_STRENGTH_SHIFT 25
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_DQSN_DRIVE_PAD_CTL_BL_PD_IDLE_STRENGTH_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: DQSN_DRIVE_PAD_CTL :: BL_ND_IDLE_STRENGTH [24:20] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_DQSN_DRIVE_PAD_CTL_BL_ND_IDLE_STRENGTH_MASK 0x01f00000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_DQSN_DRIVE_PAD_CTL_BL_ND_IDLE_STRENGTH_SHIFT 20
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_DQSN_DRIVE_PAD_CTL_BL_ND_IDLE_STRENGTH_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: DQSN_DRIVE_PAD_CTL :: BL_PD_TERM_STRENGTH [19:15] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_DQSN_DRIVE_PAD_CTL_BL_PD_TERM_STRENGTH_MASK 0x000f8000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_DQSN_DRIVE_PAD_CTL_BL_PD_TERM_STRENGTH_SHIFT 15
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_DQSN_DRIVE_PAD_CTL_BL_PD_TERM_STRENGTH_DEFAULT 0x00000008
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: DQSN_DRIVE_PAD_CTL :: BL_ND_TERM_STRENGTH [14:10] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_DQSN_DRIVE_PAD_CTL_BL_ND_TERM_STRENGTH_MASK 0x00007c00
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_DQSN_DRIVE_PAD_CTL_BL_ND_TERM_STRENGTH_SHIFT 10
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_DQSN_DRIVE_PAD_CTL_BL_ND_TERM_STRENGTH_DEFAULT 0x00000008
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: DQSN_DRIVE_PAD_CTL :: BL_PD_STRENGTH [09:05] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_DQSN_DRIVE_PAD_CTL_BL_PD_STRENGTH_MASK 0x000003e0
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_DQSN_DRIVE_PAD_CTL_BL_PD_STRENGTH_SHIFT 5
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_DQSN_DRIVE_PAD_CTL_BL_PD_STRENGTH_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: DQSN_DRIVE_PAD_CTL :: BL_ND_STRENGTH [04:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_DQSN_DRIVE_PAD_CTL_BL_ND_STRENGTH_MASK 0x0000001f
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_DQSN_DRIVE_PAD_CTL_BL_ND_STRENGTH_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_DQSN_DRIVE_PAD_CTL_BL_ND_STRENGTH_DEFAULT 0x00000000
-
-/***************************************************************************
- *EDC_DRIVE_PAD_CTL - EDC pad drive characteristics control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_1_0 :: EDC_DRIVE_PAD_CTL :: reserved0 [31:30] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_DRIVE_PAD_CTL_reserved0_MASK 0xc0000000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_DRIVE_PAD_CTL_reserved0_SHIFT 30
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: EDC_DRIVE_PAD_CTL :: BL_PD_IDLE_STRENGTH [29:25] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_DRIVE_PAD_CTL_BL_PD_IDLE_STRENGTH_MASK 0x3e000000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_DRIVE_PAD_CTL_BL_PD_IDLE_STRENGTH_SHIFT 25
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_DRIVE_PAD_CTL_BL_PD_IDLE_STRENGTH_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: EDC_DRIVE_PAD_CTL :: BL_ND_IDLE_STRENGTH [24:20] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_DRIVE_PAD_CTL_BL_ND_IDLE_STRENGTH_MASK 0x01f00000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_DRIVE_PAD_CTL_BL_ND_IDLE_STRENGTH_SHIFT 20
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_DRIVE_PAD_CTL_BL_ND_IDLE_STRENGTH_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: EDC_DRIVE_PAD_CTL :: BL_PD_TERM_STRENGTH [19:15] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_DRIVE_PAD_CTL_BL_PD_TERM_STRENGTH_MASK 0x000f8000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_DRIVE_PAD_CTL_BL_PD_TERM_STRENGTH_SHIFT 15
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_DRIVE_PAD_CTL_BL_PD_TERM_STRENGTH_DEFAULT 0x00000008
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: EDC_DRIVE_PAD_CTL :: BL_ND_TERM_STRENGTH [14:10] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_DRIVE_PAD_CTL_BL_ND_TERM_STRENGTH_MASK 0x00007c00
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_DRIVE_PAD_CTL_BL_ND_TERM_STRENGTH_SHIFT 10
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_DRIVE_PAD_CTL_BL_ND_TERM_STRENGTH_DEFAULT 0x00000008
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: EDC_DRIVE_PAD_CTL :: BL_PD_STRENGTH [09:05] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_DRIVE_PAD_CTL_BL_PD_STRENGTH_MASK 0x000003e0
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_DRIVE_PAD_CTL_BL_PD_STRENGTH_SHIFT 5
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_DRIVE_PAD_CTL_BL_PD_STRENGTH_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: EDC_DRIVE_PAD_CTL :: BL_ND_STRENGTH [04:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_DRIVE_PAD_CTL_BL_ND_STRENGTH_MASK 0x0000001f
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_DRIVE_PAD_CTL_BL_ND_STRENGTH_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_DRIVE_PAD_CTL_BL_ND_STRENGTH_DEFAULT 0x00000000
-
-/***************************************************************************
- *RD_EN_DRIVE_PAD_CTL - RD_EN, EDC_RD_EN read enable pad drive characteristics control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_1_0 :: RD_EN_DRIVE_PAD_CTL :: reserved0 [31:20] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_RD_EN_DRIVE_PAD_CTL_reserved0_MASK 0xfff00000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_RD_EN_DRIVE_PAD_CTL_reserved0_SHIFT 20
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: RD_EN_DRIVE_PAD_CTL :: EDC_RD_EN_PD_STRENGTH [19:15] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_RD_EN_DRIVE_PAD_CTL_EDC_RD_EN_PD_STRENGTH_MASK 0x000f8000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_RD_EN_DRIVE_PAD_CTL_EDC_RD_EN_PD_STRENGTH_SHIFT 15
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_RD_EN_DRIVE_PAD_CTL_EDC_RD_EN_PD_STRENGTH_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: RD_EN_DRIVE_PAD_CTL :: EDC_RD_EN_ND_STRENGTH [14:10] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_RD_EN_DRIVE_PAD_CTL_EDC_RD_EN_ND_STRENGTH_MASK 0x00007c00
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_RD_EN_DRIVE_PAD_CTL_EDC_RD_EN_ND_STRENGTH_SHIFT 10
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_RD_EN_DRIVE_PAD_CTL_EDC_RD_EN_ND_STRENGTH_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: RD_EN_DRIVE_PAD_CTL :: BL_RD_EN_PD_STRENGTH [09:05] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_RD_EN_DRIVE_PAD_CTL_BL_RD_EN_PD_STRENGTH_MASK 0x000003e0
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_RD_EN_DRIVE_PAD_CTL_BL_RD_EN_PD_STRENGTH_SHIFT 5
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_RD_EN_DRIVE_PAD_CTL_BL_RD_EN_PD_STRENGTH_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: RD_EN_DRIVE_PAD_CTL :: BL_RD_EN_ND_STRENGTH [04:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_RD_EN_DRIVE_PAD_CTL_BL_RD_EN_ND_STRENGTH_MASK 0x0000001f
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_RD_EN_DRIVE_PAD_CTL_BL_RD_EN_ND_STRENGTH_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_RD_EN_DRIVE_PAD_CTL_BL_RD_EN_ND_STRENGTH_DEFAULT 0x00000000
-
-/***************************************************************************
- *STATIC_PAD_CTL - pad rx and tx characteristics control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_1_0 :: STATIC_PAD_CTL :: reserved0 [31:25] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_STATIC_PAD_CTL_reserved0_MASK 0xfe000000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_STATIC_PAD_CTL_reserved0_SHIFT 25
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: STATIC_PAD_CTL :: TX_SLEW [24:23] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_STATIC_PAD_CTL_TX_SLEW_MASK 0x01800000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_STATIC_PAD_CTL_TX_SLEW_SHIFT 23
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_STATIC_PAD_CTL_TX_SLEW_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: STATIC_PAD_CTL :: DQS_MODE [22:22] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_STATIC_PAD_CTL_DQS_MODE_MASK 0x00400000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_STATIC_PAD_CTL_DQS_MODE_SHIFT 22
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_STATIC_PAD_CTL_DQS_MODE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: STATIC_PAD_CTL :: reserved1 [21:20] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_STATIC_PAD_CTL_reserved1_MASK 0x00300000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_STATIC_PAD_CTL_reserved1_SHIFT 20
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: STATIC_PAD_CTL :: EDC_MODE [19:18] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_STATIC_PAD_CTL_EDC_MODE_MASK 0x000c0000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_STATIC_PAD_CTL_EDC_MODE_SHIFT 18
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_STATIC_PAD_CTL_EDC_MODE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: STATIC_PAD_CTL :: reserved2 [17:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_STATIC_PAD_CTL_reserved2_MASK 0x00020000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_STATIC_PAD_CTL_reserved2_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: STATIC_PAD_CTL :: WDBI_ENABLE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_STATIC_PAD_CTL_WDBI_ENABLE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_STATIC_PAD_CTL_WDBI_ENABLE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_STATIC_PAD_CTL_WDBI_ENABLE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: STATIC_PAD_CTL :: RDBI_ENABLE [15:15] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_STATIC_PAD_CTL_RDBI_ENABLE_MASK 0x00008000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_STATIC_PAD_CTL_RDBI_ENABLE_SHIFT 15
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_STATIC_PAD_CTL_RDBI_ENABLE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: STATIC_PAD_CTL :: DM_MODE [14:14] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_STATIC_PAD_CTL_DM_MODE_MASK 0x00004000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_STATIC_PAD_CTL_DM_MODE_SHIFT 14
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_STATIC_PAD_CTL_DM_MODE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: STATIC_PAD_CTL :: reserved3 [13:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_STATIC_PAD_CTL_reserved3_MASK 0x00002000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_STATIC_PAD_CTL_reserved3_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: STATIC_PAD_CTL :: DQS_TX_PAUSE [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_STATIC_PAD_CTL_DQS_TX_PAUSE_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_STATIC_PAD_CTL_DQS_TX_PAUSE_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_STATIC_PAD_CTL_DQS_TX_PAUSE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: STATIC_PAD_CTL :: reserved_for_padding4 [11:11] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_STATIC_PAD_CTL_reserved_for_padding4_MASK 0x00000800
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_STATIC_PAD_CTL_reserved_for_padding4_SHIFT 11
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: STATIC_PAD_CTL :: DQS_TX_DIS [10:10] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_STATIC_PAD_CTL_DQS_TX_DIS_MASK 0x00000400
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_STATIC_PAD_CTL_DQS_TX_DIS_SHIFT 10
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_STATIC_PAD_CTL_DQS_TX_DIS_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: STATIC_PAD_CTL :: TX_MODE [09:04] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_STATIC_PAD_CTL_TX_MODE_MASK 0x000003f0
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_STATIC_PAD_CTL_TX_MODE_SHIFT 4
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_STATIC_PAD_CTL_TX_MODE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: STATIC_PAD_CTL :: reserved5 [03:03] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_STATIC_PAD_CTL_reserved5_MASK 0x00000008
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_STATIC_PAD_CTL_reserved5_SHIFT 3
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: STATIC_PAD_CTL :: RX_MODE [02:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_STATIC_PAD_CTL_RX_MODE_MASK 0x00000007
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_STATIC_PAD_CTL_RX_MODE_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_STATIC_PAD_CTL_RX_MODE_DEFAULT 0x00000000
-
-/***************************************************************************
- *DQ_RX_TRIM - Receiver trim for DQ
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_1_0 :: DQ_RX_TRIM :: reserved0 [31:21] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_DQ_RX_TRIM_reserved0_MASK 0xffe00000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_DQ_RX_TRIM_reserved0_SHIFT 21
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: DQ_RX_TRIM :: LSTRIM [20:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_DQ_RX_TRIM_LSTRIM_MASK 0x001e0000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_DQ_RX_TRIM_LSTRIM_SHIFT 17
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_DQ_RX_TRIM_LSTRIM_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: DQ_RX_TRIM :: ITRIM [16:14] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_DQ_RX_TRIM_ITRIM_MASK 0x0001c000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_DQ_RX_TRIM_ITRIM_SHIFT 14
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_DQ_RX_TRIM_ITRIM_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: DQ_RX_TRIM :: IDLE_LSTRIM [13:10] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_DQ_RX_TRIM_IDLE_LSTRIM_MASK 0x00003c00
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_DQ_RX_TRIM_IDLE_LSTRIM_SHIFT 10
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_DQ_RX_TRIM_IDLE_LSTRIM_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: DQ_RX_TRIM :: IDLE_ITRIM [09:07] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_DQ_RX_TRIM_IDLE_ITRIM_MASK 0x00000380
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_DQ_RX_TRIM_IDLE_ITRIM_SHIFT 7
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_DQ_RX_TRIM_IDLE_ITRIM_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: DQ_RX_TRIM :: TERM_LSTRIM [06:03] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_DQ_RX_TRIM_TERM_LSTRIM_MASK 0x00000078
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_DQ_RX_TRIM_TERM_LSTRIM_SHIFT 3
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_DQ_RX_TRIM_TERM_LSTRIM_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: DQ_RX_TRIM :: TERM_ITRIM [02:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_DQ_RX_TRIM_TERM_ITRIM_MASK 0x00000007
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_DQ_RX_TRIM_TERM_ITRIM_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_DQ_RX_TRIM_TERM_ITRIM_DEFAULT 0x00000000
-
-/***************************************************************************
- *MISC_RX_TRIM - Receiver trim for miscellaneous pins
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_1_0 :: MISC_RX_TRIM :: reserved0 [31:21] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_MISC_RX_TRIM_reserved0_MASK 0xffe00000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_MISC_RX_TRIM_reserved0_SHIFT 21
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: MISC_RX_TRIM :: LSTRIM [20:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_MISC_RX_TRIM_LSTRIM_MASK 0x001e0000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_MISC_RX_TRIM_LSTRIM_SHIFT 17
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_MISC_RX_TRIM_LSTRIM_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: MISC_RX_TRIM :: ITRIM [16:14] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_MISC_RX_TRIM_ITRIM_MASK 0x0001c000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_MISC_RX_TRIM_ITRIM_SHIFT 14
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_MISC_RX_TRIM_ITRIM_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: MISC_RX_TRIM :: IDLE_LSTRIM [13:10] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_MISC_RX_TRIM_IDLE_LSTRIM_MASK 0x00003c00
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_MISC_RX_TRIM_IDLE_LSTRIM_SHIFT 10
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_MISC_RX_TRIM_IDLE_LSTRIM_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: MISC_RX_TRIM :: IDLE_ITRIM [09:07] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_MISC_RX_TRIM_IDLE_ITRIM_MASK 0x00000380
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_MISC_RX_TRIM_IDLE_ITRIM_SHIFT 7
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_MISC_RX_TRIM_IDLE_ITRIM_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: MISC_RX_TRIM :: TERM_LSTRIM [06:03] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_MISC_RX_TRIM_TERM_LSTRIM_MASK 0x00000078
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_MISC_RX_TRIM_TERM_LSTRIM_SHIFT 3
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_MISC_RX_TRIM_TERM_LSTRIM_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: MISC_RX_TRIM :: TERM_ITRIM [02:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_MISC_RX_TRIM_TERM_ITRIM_MASK 0x00000007
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_MISC_RX_TRIM_TERM_ITRIM_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_MISC_RX_TRIM_TERM_ITRIM_DEFAULT 0x00000000
-
-/***************************************************************************
- *DQS_RX_TRIM - Rreceiver trim for DQS
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_1_0 :: DQS_RX_TRIM :: reserved0 [31:21] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_DQS_RX_TRIM_reserved0_MASK 0xffe00000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_DQS_RX_TRIM_reserved0_SHIFT 21
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: DQS_RX_TRIM :: LSTRIM [20:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_DQS_RX_TRIM_LSTRIM_MASK 0x001e0000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_DQS_RX_TRIM_LSTRIM_SHIFT 17
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_DQS_RX_TRIM_LSTRIM_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: DQS_RX_TRIM :: ITRIM [16:14] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_DQS_RX_TRIM_ITRIM_MASK 0x0001c000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_DQS_RX_TRIM_ITRIM_SHIFT 14
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_DQS_RX_TRIM_ITRIM_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: DQS_RX_TRIM :: IDLE_LSTRIM [13:10] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_DQS_RX_TRIM_IDLE_LSTRIM_MASK 0x00003c00
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_DQS_RX_TRIM_IDLE_LSTRIM_SHIFT 10
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_DQS_RX_TRIM_IDLE_LSTRIM_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: DQS_RX_TRIM :: IDLE_ITRIM [09:07] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_DQS_RX_TRIM_IDLE_ITRIM_MASK 0x00000380
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_DQS_RX_TRIM_IDLE_ITRIM_SHIFT 7
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_DQS_RX_TRIM_IDLE_ITRIM_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: DQS_RX_TRIM :: TERM_LSTRIM [06:03] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_DQS_RX_TRIM_TERM_LSTRIM_MASK 0x00000078
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_DQS_RX_TRIM_TERM_LSTRIM_SHIFT 3
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_DQS_RX_TRIM_TERM_LSTRIM_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: DQS_RX_TRIM :: TERM_ITRIM [02:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_DQS_RX_TRIM_TERM_ITRIM_MASK 0x00000007
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_DQS_RX_TRIM_TERM_ITRIM_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_DQS_RX_TRIM_TERM_ITRIM_DEFAULT 0x00000000
-
-/***************************************************************************
- *WR_PREAMBLE_MODE - Write cycle preamble control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_1_0 :: WR_PREAMBLE_MODE :: reserved0 [31:21] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_WR_PREAMBLE_MODE_reserved0_MASK 0xffe00000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_WR_PREAMBLE_MODE_reserved0_SHIFT 21
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: WR_PREAMBLE_MODE :: POSTAM_TERM_BITS [20:19] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_WR_PREAMBLE_MODE_POSTAM_TERM_BITS_MASK 0x00180000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_WR_PREAMBLE_MODE_POSTAM_TERM_BITS_SHIFT 19
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_WR_PREAMBLE_MODE_POSTAM_TERM_BITS_DEFAULT 0x00000003
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: WR_PREAMBLE_MODE :: DM_POSTAM_BITS [18:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_WR_PREAMBLE_MODE_DM_POSTAM_BITS_MASK 0x00060000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_WR_PREAMBLE_MODE_DM_POSTAM_BITS_SHIFT 17
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_WR_PREAMBLE_MODE_DM_POSTAM_BITS_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: WR_PREAMBLE_MODE :: DM_PREAM_BITS [16:14] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_WR_PREAMBLE_MODE_DM_PREAM_BITS_MASK 0x0001c000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_WR_PREAMBLE_MODE_DM_PREAM_BITS_SHIFT 14
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_WR_PREAMBLE_MODE_DM_PREAM_BITS_DEFAULT 0x00000001
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: WR_PREAMBLE_MODE :: DQ_POSTAM_BITS [13:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_WR_PREAMBLE_MODE_DQ_POSTAM_BITS_MASK 0x00003000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_WR_PREAMBLE_MODE_DQ_POSTAM_BITS_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_WR_PREAMBLE_MODE_DQ_POSTAM_BITS_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: WR_PREAMBLE_MODE :: DQ_PREAM_BITS [11:09] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_WR_PREAMBLE_MODE_DQ_PREAM_BITS_MASK 0x00000e00
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_WR_PREAMBLE_MODE_DQ_PREAM_BITS_SHIFT 9
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_WR_PREAMBLE_MODE_DQ_PREAM_BITS_DEFAULT 0x00000001
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: WR_PREAMBLE_MODE :: DQS [08:05] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_WR_PREAMBLE_MODE_DQS_MASK 0x000001e0
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_WR_PREAMBLE_MODE_DQS_SHIFT 5
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_WR_PREAMBLE_MODE_DQS_DEFAULT 0x0000000a
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: WR_PREAMBLE_MODE :: DQS_POSTAM_BITS [04:03] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_WR_PREAMBLE_MODE_DQS_POSTAM_BITS_MASK 0x00000018
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_WR_PREAMBLE_MODE_DQS_POSTAM_BITS_SHIFT 3
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_WR_PREAMBLE_MODE_DQS_POSTAM_BITS_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: WR_PREAMBLE_MODE :: DQS_PREAM_BITS [02:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_WR_PREAMBLE_MODE_DQS_PREAM_BITS_MASK 0x00000007
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_WR_PREAMBLE_MODE_DQS_PREAM_BITS_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_WR_PREAMBLE_MODE_DQS_PREAM_BITS_DEFAULT 0x00000002
-
-/***************************************************************************
- *ODT_CONTROL - Read channel ODT control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_1_0 :: ODT_CONTROL :: reserved_for_padding0 [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_ODT_CONTROL_reserved_for_padding0_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_ODT_CONTROL_reserved_for_padding0_SHIFT 31
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: ODT_CONTROL :: reserved1 [30:10] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_ODT_CONTROL_reserved1_MASK 0x7ffffc00
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_ODT_CONTROL_reserved1_SHIFT 10
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: ODT_CONTROL :: ODT_ENABLE [09:09] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_ODT_CONTROL_ODT_ENABLE_MASK 0x00000200
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_ODT_CONTROL_ODT_ENABLE_SHIFT 9
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_ODT_CONTROL_ODT_ENABLE_DEFAULT 0x00000001
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: ODT_CONTROL :: ODT_DELAY [08:06] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_ODT_CONTROL_ODT_DELAY_MASK 0x000001c0
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_ODT_CONTROL_ODT_DELAY_SHIFT 6
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_ODT_CONTROL_ODT_DELAY_DEFAULT 0x00000001
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: ODT_CONTROL :: ODT_POST_LENGTH [05:03] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_ODT_CONTROL_ODT_POST_LENGTH_MASK 0x00000038
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_ODT_CONTROL_ODT_POST_LENGTH_SHIFT 3
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_ODT_CONTROL_ODT_POST_LENGTH_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: ODT_CONTROL :: ODT_PRE_LENGTH [02:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_ODT_CONTROL_ODT_PRE_LENGTH_MASK 0x00000007
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_ODT_CONTROL_ODT_PRE_LENGTH_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_ODT_CONTROL_ODT_PRE_LENGTH_DEFAULT 0x00000003
-
-/***************************************************************************
- *LDO_CONFIG - LDO Configuration register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_1_0 :: LDO_CONFIG :: reserved0 [31:06] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_LDO_CONFIG_reserved0_MASK 0xffffffc0
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_LDO_CONFIG_reserved0_SHIFT 6
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: LDO_CONFIG :: CK_LDO_PWRDOWN [05:05] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_LDO_CONFIG_CK_LDO_PWRDOWN_MASK 0x00000020
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_LDO_CONFIG_CK_LDO_PWRDOWN_SHIFT 5
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_LDO_CONFIG_CK_LDO_PWRDOWN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: LDO_CONFIG :: CK_LDO_REF_SEL [04:04] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_LDO_CONFIG_CK_LDO_REF_SEL_MASK 0x00000010
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_LDO_CONFIG_CK_LDO_REF_SEL_SHIFT 4
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_LDO_CONFIG_CK_LDO_REF_SEL_DEFAULT 0x00000001
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: LDO_CONFIG :: CK_LDO_REF_CTRL [03:02] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_LDO_CONFIG_CK_LDO_REF_CTRL_MASK 0x0000000c
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_LDO_CONFIG_CK_LDO_REF_CTRL_SHIFT 2
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_LDO_CONFIG_CK_LDO_REF_CTRL_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: LDO_CONFIG :: CK_LDO_BIAS [01:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_LDO_CONFIG_CK_LDO_BIAS_MASK 0x00000003
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_LDO_CONFIG_CK_LDO_BIAS_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_LDO_CONFIG_CK_LDO_BIAS_DEFAULT 0x00000000
-
-/***************************************************************************
- *EDC_DPD_CONTROL - GDDR5M EDC digital phase detector control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_1_0 :: EDC_DPD_CONTROL :: reserved0 [31:22] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_DPD_CONTROL_reserved0_MASK 0xffc00000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_DPD_CONTROL_reserved0_SHIFT 22
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: EDC_DPD_CONTROL :: DQS_PHASE_OVERRIDE_VALUE [21:21] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_DPD_CONTROL_DQS_PHASE_OVERRIDE_VALUE_MASK 0x00200000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_DPD_CONTROL_DQS_PHASE_OVERRIDE_VALUE_SHIFT 21
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_DPD_CONTROL_DQS_PHASE_OVERRIDE_VALUE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: EDC_DPD_CONTROL :: DQS_PHASE_OVERRIDE_ENABLE [20:20] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_DPD_CONTROL_DQS_PHASE_OVERRIDE_ENABLE_MASK 0x00100000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_DPD_CONTROL_DQS_PHASE_OVERRIDE_ENABLE_SHIFT 20
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_DPD_CONTROL_DQS_PHASE_OVERRIDE_ENABLE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: EDC_DPD_CONTROL :: reserved1 [19:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_DPD_CONTROL_reserved1_MASK 0x000f0000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_DPD_CONTROL_reserved1_SHIFT 16
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: EDC_DPD_CONTROL :: TARGET_CS_N [15:15] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_DPD_CONTROL_TARGET_CS_N_MASK 0x00008000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_DPD_CONTROL_TARGET_CS_N_SHIFT 15
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_DPD_CONTROL_TARGET_CS_N_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: EDC_DPD_CONTROL :: UPDATE_MODE [14:14] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_DPD_CONTROL_UPDATE_MODE_MASK 0x00004000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_DPD_CONTROL_UPDATE_MODE_SHIFT 14
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_DPD_CONTROL_UPDATE_MODE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: EDC_DPD_CONTROL :: SAMPLE_MODE [13:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_DPD_CONTROL_SAMPLE_MODE_MASK 0x00003000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_DPD_CONTROL_SAMPLE_MODE_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_DPD_CONTROL_SAMPLE_MODE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: EDC_DPD_CONTROL :: reserved2 [11:09] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_DPD_CONTROL_reserved2_MASK 0x00000e00
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_DPD_CONTROL_reserved2_SHIFT 9
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: EDC_DPD_CONTROL :: MIN_LOW_SAMPLES [08:04] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_DPD_CONTROL_MIN_LOW_SAMPLES_MASK 0x000001f0
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_DPD_CONTROL_MIN_LOW_SAMPLES_SHIFT 4
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_DPD_CONTROL_MIN_LOW_SAMPLES_DEFAULT 0x00000008
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: EDC_DPD_CONTROL :: SET_ADJ_EN [03:03] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_DPD_CONTROL_SET_ADJ_EN_MASK 0x00000008
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_DPD_CONTROL_SET_ADJ_EN_SHIFT 3
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_DPD_CONTROL_SET_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: EDC_DPD_CONTROL :: UPDATE [02:02] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_DPD_CONTROL_UPDATE_MASK 0x00000004
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_DPD_CONTROL_UPDATE_SHIFT 2
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_DPD_CONTROL_UPDATE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: EDC_DPD_CONTROL :: MONITOR [01:01] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_DPD_CONTROL_MONITOR_MASK 0x00000002
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_DPD_CONTROL_MONITOR_SHIFT 1
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_DPD_CONTROL_MONITOR_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: EDC_DPD_CONTROL :: INIT [00:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_DPD_CONTROL_INIT_MASK 0x00000001
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_DPD_CONTROL_INIT_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_DPD_CONTROL_INIT_DEFAULT 0x00000000
-
-/***************************************************************************
- *EDC_DPD_STATUS - GDDR5M EDC digital phase detector status register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_1_0 :: EDC_DPD_STATUS :: reserved0 [31:29] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_DPD_STATUS_reserved0_MASK 0xe0000000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_DPD_STATUS_reserved0_SHIFT 29
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: EDC_DPD_STATUS :: CURRENT_DQS_PHASE [28:28] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_DPD_STATUS_CURRENT_DQS_PHASE_MASK 0x10000000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_DPD_STATUS_CURRENT_DQS_PHASE_SHIFT 28
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_DPD_STATUS_CURRENT_DQS_PHASE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: EDC_DPD_STATUS :: CURRENT_VDL_SETTING [27:20] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_DPD_STATUS_CURRENT_VDL_SETTING_MASK 0x0ff00000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_DPD_STATUS_CURRENT_VDL_SETTING_SHIFT 20
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_DPD_STATUS_CURRENT_VDL_SETTING_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: EDC_DPD_STATUS :: reserved1 [19:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_DPD_STATUS_reserved1_MASK 0x000e0000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_DPD_STATUS_reserved1_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: EDC_DPD_STATUS :: INIT_DQS_PHASE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_DPD_STATUS_INIT_DQS_PHASE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_DPD_STATUS_INIT_DQS_PHASE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_DPD_STATUS_INIT_DQS_PHASE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: EDC_DPD_STATUS :: INIT_VDL_SETTING [15:08] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_DPD_STATUS_INIT_VDL_SETTING_MASK 0x0000ff00
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_DPD_STATUS_INIT_VDL_SETTING_SHIFT 8
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_DPD_STATUS_INIT_VDL_SETTING_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: EDC_DPD_STATUS :: reserved2 [07:05] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_DPD_STATUS_reserved2_MASK 0x000000e0
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_DPD_STATUS_reserved2_SHIFT 5
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: EDC_DPD_STATUS :: MONITOR_ERROR [04:04] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_DPD_STATUS_MONITOR_ERROR_MASK 0x00000010
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_DPD_STATUS_MONITOR_ERROR_SHIFT 4
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_DPD_STATUS_MONITOR_ERROR_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: EDC_DPD_STATUS :: MONITOR_BUSY [03:03] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_DPD_STATUS_MONITOR_BUSY_MASK 0x00000008
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_DPD_STATUS_MONITOR_BUSY_SHIFT 3
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_DPD_STATUS_MONITOR_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: EDC_DPD_STATUS :: INIT_LOCK [02:02] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_DPD_STATUS_INIT_LOCK_MASK 0x00000004
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_DPD_STATUS_INIT_LOCK_SHIFT 2
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_DPD_STATUS_INIT_LOCK_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: EDC_DPD_STATUS :: INIT_BUSY [01:01] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_DPD_STATUS_INIT_BUSY_MASK 0x00000002
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_DPD_STATUS_INIT_BUSY_SHIFT 1
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_DPD_STATUS_INIT_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: EDC_DPD_STATUS :: INIT_DONE [00:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_DPD_STATUS_INIT_DONE_MASK 0x00000001
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_DPD_STATUS_INIT_DONE_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_DPD_STATUS_INIT_DONE_DEFAULT 0x00000000
-
-/***************************************************************************
- *EDC_DPD_OUT_CONTROL - GDDR5M EDC digital phase detector output signal control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_1_0 :: EDC_DPD_OUT_CONTROL :: reserved0 [31:20] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_DPD_OUT_CONTROL_reserved0_MASK 0xfff00000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_DPD_OUT_CONTROL_reserved0_SHIFT 20
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: EDC_DPD_OUT_CONTROL :: LOWER_LIMIT [19:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_DPD_OUT_CONTROL_LOWER_LIMIT_MASK 0x000ff000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_DPD_OUT_CONTROL_LOWER_LIMIT_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_DPD_OUT_CONTROL_LOWER_LIMIT_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: EDC_DPD_OUT_CONTROL :: UPPER_LIMIT [11:04] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_DPD_OUT_CONTROL_UPPER_LIMIT_MASK 0x00000ff0
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_DPD_OUT_CONTROL_UPPER_LIMIT_SHIFT 4
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_DPD_OUT_CONTROL_UPPER_LIMIT_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: EDC_DPD_OUT_CONTROL :: reserved1 [03:01] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_DPD_OUT_CONTROL_reserved1_MASK 0x0000000e
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_DPD_OUT_CONTROL_reserved1_SHIFT 1
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: EDC_DPD_OUT_CONTROL :: ENABLE [00:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_DPD_OUT_CONTROL_ENABLE_MASK 0x00000001
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_DPD_OUT_CONTROL_ENABLE_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_DPD_OUT_CONTROL_ENABLE_DEFAULT 0x00000000
-
-/***************************************************************************
- *EDC_DPD_OUT_STATUS - GDDR5M EDC digital phase detector output signal status register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_1_0 :: EDC_DPD_OUT_STATUS :: reserved0 [31:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_DPD_OUT_STATUS_reserved0_MASK 0xfffff000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_DPD_OUT_STATUS_reserved0_SHIFT 12
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: EDC_DPD_OUT_STATUS :: VDL_SETTING [11:04] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_DPD_OUT_STATUS_VDL_SETTING_MASK 0x00000ff0
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_DPD_OUT_STATUS_VDL_SETTING_SHIFT 4
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_DPD_OUT_STATUS_VDL_SETTING_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: EDC_DPD_OUT_STATUS :: reserved1 [03:01] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_DPD_OUT_STATUS_reserved1_MASK 0x0000000e
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_DPD_OUT_STATUS_reserved1_SHIFT 1
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: EDC_DPD_OUT_STATUS :: VALID [00:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_DPD_OUT_STATUS_VALID_MASK 0x00000001
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_DPD_OUT_STATUS_VALID_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_DPD_OUT_STATUS_VALID_DEFAULT 0x00000000
-
-/***************************************************************************
- *EDC_DPD_OUT_STATUS_CLEAR - GDDR5M EDC digital phase detector output signal status clear register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_1_0 :: EDC_DPD_OUT_STATUS_CLEAR :: reserved0 [31:01] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_DPD_OUT_STATUS_CLEAR_reserved0_MASK 0xfffffffe
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_DPD_OUT_STATUS_CLEAR_reserved0_SHIFT 1
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: EDC_DPD_OUT_STATUS_CLEAR :: CLEAR [00:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_DPD_OUT_STATUS_CLEAR_CLEAR_MASK 0x00000001
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_DPD_OUT_STATUS_CLEAR_CLEAR_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_DPD_OUT_STATUS_CLEAR_CLEAR_DEFAULT 0x00000000
-
-/***************************************************************************
- *EDC_CRC_CONTROL - GDDR5M EDC signal path CRC control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_1_0 :: EDC_CRC_CONTROL :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_CRC_CONTROL_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_CRC_CONTROL_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_CRC_CONTROL_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: EDC_CRC_CONTROL :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_CRC_CONTROL_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_CRC_CONTROL_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: EDC_CRC_CONTROL :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_CRC_CONTROL_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_CRC_CONTROL_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_CRC_CONTROL_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: EDC_CRC_CONTROL :: reserved1 [15:11] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_CRC_CONTROL_reserved1_MASK 0x0000f800
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_CRC_CONTROL_reserved1_SHIFT 11
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: EDC_CRC_CONTROL :: CRCWL [10:08] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_CRC_CONTROL_CRCWL_MASK 0x00000700
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_CRC_CONTROL_CRCWL_SHIFT 8
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_CRC_CONTROL_CRCWL_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: EDC_CRC_CONTROL :: reserved2 [07:06] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_CRC_CONTROL_reserved2_MASK 0x000000c0
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_CRC_CONTROL_reserved2_SHIFT 6
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: EDC_CRC_CONTROL :: CRCRL [05:04] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_CRC_CONTROL_CRCRL_MASK 0x00000030
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_CRC_CONTROL_CRCRL_SHIFT 4
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_CRC_CONTROL_CRCRL_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: EDC_CRC_CONTROL :: reserved3 [03:02] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_CRC_CONTROL_reserved3_MASK 0x0000000c
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_CRC_CONTROL_reserved3_SHIFT 2
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: EDC_CRC_CONTROL :: ENABLE_WR [01:01] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_CRC_CONTROL_ENABLE_WR_MASK 0x00000002
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_CRC_CONTROL_ENABLE_WR_SHIFT 1
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_CRC_CONTROL_ENABLE_WR_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: EDC_CRC_CONTROL :: ENABLE_RD [00:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_CRC_CONTROL_ENABLE_RD_MASK 0x00000001
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_CRC_CONTROL_ENABLE_RD_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_CRC_CONTROL_ENABLE_RD_DEFAULT 0x00000000
-
-/***************************************************************************
- *EDC_CRC_STATUS - GDDR5M EDC signal path CRC status register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_1_0 :: EDC_CRC_STATUS :: MISCOMPARE_EXP_CRC [31:24] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_CRC_STATUS_MISCOMPARE_EXP_CRC_MASK 0xff000000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_CRC_STATUS_MISCOMPARE_EXP_CRC_SHIFT 24
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: EDC_CRC_STATUS :: MISCOMPARE_CRC [23:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_CRC_STATUS_MISCOMPARE_CRC_MASK 0x00ff0000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_CRC_STATUS_MISCOMPARE_CRC_SHIFT 16
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: EDC_CRC_STATUS :: MOST_RECENT_CRC [15:08] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_CRC_STATUS_MOST_RECENT_CRC_MASK 0x0000ff00
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_CRC_STATUS_MOST_RECENT_CRC_SHIFT 8
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: EDC_CRC_STATUS :: reserved0 [07:05] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_CRC_STATUS_reserved0_MASK 0x000000e0
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_CRC_STATUS_reserved0_SHIFT 5
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: EDC_CRC_STATUS :: MISCOMPARE_TYPE [04:04] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_CRC_STATUS_MISCOMPARE_TYPE_MASK 0x00000010
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_CRC_STATUS_MISCOMPARE_TYPE_SHIFT 4
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: EDC_CRC_STATUS :: WR_FAIL [03:03] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_CRC_STATUS_WR_FAIL_MASK 0x00000008
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_CRC_STATUS_WR_FAIL_SHIFT 3
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: EDC_CRC_STATUS :: WR_PASS [02:02] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_CRC_STATUS_WR_PASS_MASK 0x00000004
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_CRC_STATUS_WR_PASS_SHIFT 2
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: EDC_CRC_STATUS :: RD_FAIL [01:01] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_CRC_STATUS_RD_FAIL_MASK 0x00000002
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_CRC_STATUS_RD_FAIL_SHIFT 1
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: EDC_CRC_STATUS :: RD_PASS [00:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_CRC_STATUS_RD_PASS_MASK 0x00000001
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_CRC_STATUS_RD_PASS_SHIFT 0
-
-/***************************************************************************
- *EDC_CRC_COUNT - GDDR5M EDC signal path CRC counter register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_1_0 :: EDC_CRC_COUNT :: WR_FAIL_COUNT [31:24] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_CRC_COUNT_WR_FAIL_COUNT_MASK 0xff000000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_CRC_COUNT_WR_FAIL_COUNT_SHIFT 24
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: EDC_CRC_COUNT :: WR_PASS_COUNT [23:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_CRC_COUNT_WR_PASS_COUNT_MASK 0x00ff0000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_CRC_COUNT_WR_PASS_COUNT_SHIFT 16
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: EDC_CRC_COUNT :: RD_FAIL_COUNT [15:08] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_CRC_COUNT_RD_FAIL_COUNT_MASK 0x0000ff00
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_CRC_COUNT_RD_FAIL_COUNT_SHIFT 8
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: EDC_CRC_COUNT :: RD_PASS_COUNT [07:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_CRC_COUNT_RD_PASS_COUNT_MASK 0x000000ff
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_CRC_COUNT_RD_PASS_COUNT_SHIFT 0
-
-/***************************************************************************
- *EDC_CRC_STATUS_CLEAR - GDDR5M EDC signal path CRC counter register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_1_0 :: EDC_CRC_STATUS_CLEAR :: reserved0 [31:01] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_CRC_STATUS_CLEAR_reserved0_MASK 0xfffffffe
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_CRC_STATUS_CLEAR_reserved0_SHIFT 1
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: EDC_CRC_STATUS_CLEAR :: CLEAR [00:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_CRC_STATUS_CLEAR_CLEAR_MASK 0x00000001
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_CRC_STATUS_CLEAR_CLEAR_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_CRC_STATUS_CLEAR_CLEAR_DEFAULT 0x00000000
-
-/***************************************************************************
- *CLOCK_ENABLE - Clock Enable Register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_1_0 :: CLOCK_ENABLE :: reserved0 [31:03] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_CLOCK_ENABLE_reserved0_MASK 0xfffffff8
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_CLOCK_ENABLE_reserved0_SHIFT 3
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: CLOCK_ENABLE :: TO_MC_CLOCK [02:02] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_CLOCK_ENABLE_TO_MC_CLOCK_MASK 0x00000004
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_CLOCK_ENABLE_TO_MC_CLOCK_SHIFT 2
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_CLOCK_ENABLE_TO_MC_CLOCK_DEFAULT 0x00000001
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: CLOCK_ENABLE :: FROM_MC_CLOCK [01:01] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_CLOCK_ENABLE_FROM_MC_CLOCK_MASK 0x00000002
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_CLOCK_ENABLE_FROM_MC_CLOCK_SHIFT 1
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_CLOCK_ENABLE_FROM_MC_CLOCK_DEFAULT 0x00000001
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: CLOCK_ENABLE :: BIT_CLOCK [00:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_CLOCK_ENABLE_BIT_CLOCK_MASK 0x00000001
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_CLOCK_ENABLE_BIT_CLOCK_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_CLOCK_ENABLE_BIT_CLOCK_DEFAULT 0x00000001
-
-/***************************************************************************
- *CLOCK_IDLE - Clock Idle Register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_1_0 :: CLOCK_IDLE :: reserved0 [31:03] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_CLOCK_IDLE_reserved0_MASK 0xfffffff8
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_CLOCK_IDLE_reserved0_SHIFT 3
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: CLOCK_IDLE :: TO_MC_CLOCK [02:02] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_CLOCK_IDLE_TO_MC_CLOCK_MASK 0x00000004
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_CLOCK_IDLE_TO_MC_CLOCK_SHIFT 2
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_CLOCK_IDLE_TO_MC_CLOCK_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: CLOCK_IDLE :: FROM_MC_CLOCK [01:01] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_CLOCK_IDLE_FROM_MC_CLOCK_MASK 0x00000002
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_CLOCK_IDLE_FROM_MC_CLOCK_SHIFT 1
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_CLOCK_IDLE_FROM_MC_CLOCK_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: CLOCK_IDLE :: BIT_CLOCK [00:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_CLOCK_IDLE_BIT_CLOCK_MASK 0x00000001
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_CLOCK_IDLE_BIT_CLOCK_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_CLOCK_IDLE_BIT_CLOCK_DEFAULT 0x00000000
-
-/***************************************************************************
- *BL_SPARE_REG - Byte-Lane Spare register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_1_0 :: BL_SPARE_REG :: reserved_for_eco0 [31:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_BL_SPARE_REG_reserved_for_eco0_MASK 0xffffffff
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_BL_SPARE_REG_reserved_for_eco0_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_BL_SPARE_REG_reserved_for_eco0_DEFAULT 0x00000000
-
-#endif /* #ifndef BCHP_DDR34_PHY_BYTE_LANE_1_0_H__ */
-
-/* End of File */
diff --git a/include/linux/brcmstb/7366b0/bchp_ddr34_phy_byte_lane_2_0.h b/include/linux/brcmstb/7366b0/bchp_ddr34_phy_byte_lane_2_0.h
deleted file mode 100644
index 9a0776c..0000000
--- a/include/linux/brcmstb/7366b0/bchp_ddr34_phy_byte_lane_2_0.h
+++ /dev/null
@@ -1,2482 +0,0 @@
-/***************************************************************************
- * Copyright (c) 1999-2014, Broadcom Corporation
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
- *
- * Module Description:
- * DO NOT EDIT THIS FILE DIRECTLY
- *
- * This module was generated magically with RDB from a source description
- * file. You must edit the source file for changes to be made to this file.
- *
- *
- * Date: Generated on Thu Apr 24 03:08:54 2014
- * Full Compile MD5 Checksum 1af2c2cf28828ece5496e1312aac0166
- * (minus title and desc)
- * MD5 Checksum 3203ffce85e3fc9a10f84123e54057b0
- *
- * Compiled with: RDB Utility combo_header.pl
- * RDB Parser 3.0
- * unknown unknown
- * Perl Interpreter 5.008008
- * Operating System linux
- *
- * Revision History:
- *
- * $brcm_Log: $
- *
- ***************************************************************************/
-
-#ifndef BCHP_DDR34_PHY_BYTE_LANE_2_0_H__
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_H__
-
-/***************************************************************************
- *DDR34_PHY_BYTE_LANE_2_0 - DDR34 Byte Lane #2 control registers
- ***************************************************************************/
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQS 0x00506800 /* Write channel DQS VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ0 0x00506804 /* Write channel DQ0 VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ1 0x00506808 /* Write channel DQ1 VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ2 0x0050680c /* Write channel DQ2 VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ3 0x00506810 /* Write channel DQ3 VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ4 0x00506814 /* Write channel DQ4 VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ5 0x00506818 /* Write channel DQ5 VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ6 0x0050681c /* Write channel DQ6 VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ7 0x00506820 /* Write channel DQ7 VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DM 0x00506824 /* Write channel DM VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_EDC 0x00506828 /* Write channel EDC VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQSP 0x0050682c /* Read channel DQSP VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQSN 0x00506830 /* Read channel DQSP VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ0P 0x00506834 /* Read channel DQ0-P VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ0N 0x00506838 /* Read channel DQ0-N VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ1P 0x0050683c /* Read channel DQ1-P VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ1N 0x00506840 /* Read channel DQ1-N VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ2P 0x00506844 /* Read channel DQ2-P VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ2N 0x00506848 /* Read channel DQ2-N VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ3P 0x0050684c /* Read channel DQ3-P VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ3N 0x00506850 /* Read channel DQ3-N VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ4P 0x00506854 /* Read channel DQ4-P VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ4N 0x00506858 /* Read channel DQ4-N VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ5P 0x0050685c /* Read channel DQ5-P VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ5N 0x00506860 /* Read channel DQ5-N VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ6P 0x00506864 /* Read channel DQ6-P VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ6N 0x00506868 /* Read channel DQ6-N VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ7P 0x0050686c /* Read channel DQ7-P VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ7N 0x00506870 /* Read channel DQ7-N VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DMP 0x00506874 /* Read channel DM-P VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DMN 0x00506878 /* Read channel DM-N VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_EDCP 0x0050687c /* Read channel EDC-P VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_EDCN 0x00506880 /* Read channel EDC-N VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_EN_CS0 0x00506884 /* Read channel CS_N[0] read enable VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_EN_CS1 0x00506888 /* Read channel CS_N[1] read enable VDL control register (used for reads when only cs1_n is active) */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_EN_CRC 0x0050688c /* Read channel GDDR5 CRC read enable VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CLK_CONTROL 0x00506890 /* DDR interface signal Write Leveling CLK VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_LDE_CONTROL 0x00506894 /* DDR interface signal Write Leveling Capture Enable VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_RD_EN_DLY_CYC 0x00506898 /* Read enable bit-clock cycle delay control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_WR_CHAN_DLY_CYC 0x0050689c /* Write leveling bit-clock cycle delay control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_READ_CONTROL 0x005068a0 /* Read channel datapath control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_READ_FIFO_ADDR 0x005068a4 /* Read fifo addresss pointer register */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_READ_FIFO_DATA 0x005068a8 /* Read fifo data register */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_READ_FIFO_DM_DBI 0x005068ac /* Read fifo dm/dbi register */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_READ_FIFO_STATUS 0x005068b0 /* Read fifo status register */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_READ_FIFO_CLEAR 0x005068b4 /* Read fifo status clear register */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_IDLE_PAD_CONTROL 0x005068b8 /* Idle mode SSTL pad control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_DRIVE_PAD_CTL 0x005068bc /* DQ, DM pad drive characteristics control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_DQSP_DRIVE_PAD_CTL 0x005068c0 /* DQS pad P rail drive characteristics control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_DQSN_DRIVE_PAD_CTL 0x005068c4 /* DQS pad N rail drive characteristics control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_DRIVE_PAD_CTL 0x005068c8 /* EDC pad drive characteristics control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_RD_EN_DRIVE_PAD_CTL 0x005068cc /* RD_EN, EDC_RD_EN read enable pad drive characteristics control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_STATIC_PAD_CTL 0x005068d0 /* pad rx and tx characteristics control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_DQ_RX_TRIM 0x005068d4 /* Receiver trim for DQ */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_MISC_RX_TRIM 0x005068d8 /* Receiver trim for miscellaneous pins */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_DQS_RX_TRIM 0x005068dc /* Rreceiver trim for DQS */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_WR_PREAMBLE_MODE 0x005068e0 /* Write cycle preamble control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_ODT_CONTROL 0x005068e4 /* Read channel ODT control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_LDO_CONFIG 0x005068e8 /* LDO Configuration register */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_DPD_CONTROL 0x005068ec /* GDDR5M EDC digital phase detector control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_DPD_STATUS 0x005068f0 /* GDDR5M EDC digital phase detector status register */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_DPD_OUT_CONTROL 0x005068f4 /* GDDR5M EDC digital phase detector output signal control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_DPD_OUT_STATUS 0x005068f8 /* GDDR5M EDC digital phase detector output signal status register */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_DPD_OUT_STATUS_CLEAR 0x005068fc /* GDDR5M EDC digital phase detector output signal status clear register */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_CRC_CONTROL 0x00506900 /* GDDR5M EDC signal path CRC control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_CRC_STATUS 0x00506904 /* GDDR5M EDC signal path CRC status register */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_CRC_COUNT 0x00506908 /* GDDR5M EDC signal path CRC counter register */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_CRC_STATUS_CLEAR 0x0050690c /* GDDR5M EDC signal path CRC counter register */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_CLOCK_ENABLE 0x00506910 /* Clock Enable Register */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_CLOCK_IDLE 0x00506914 /* Clock Idle Register */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_BL_SPARE_REG 0x00506918 /* Byte-Lane Spare register */
-
-/***************************************************************************
- *VDL_CONTROL_WR_DQS - Write channel DQS VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_WR_DQS :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQS_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQS_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQS_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_WR_DQS :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQS_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQS_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_WR_DQS :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQS_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQS_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQS_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_WR_DQS :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQS_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQS_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_WR_DQS :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQS_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQS_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQS_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_WR_DQS :: reserved2 [11:09] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQS_reserved2_MASK 0x00000e00
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQS_reserved2_SHIFT 9
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_WR_DQS :: VDL_STEP [08:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQS_VDL_STEP_MASK 0x000001ff
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQS_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQS_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_WR_DQ0 - Write channel DQ0 VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_WR_DQ0 :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ0_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ0_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ0_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_WR_DQ0 :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ0_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ0_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_WR_DQ0 :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ0_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ0_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ0_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_WR_DQ0 :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ0_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ0_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_WR_DQ0 :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ0_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ0_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ0_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_WR_DQ0 :: reserved2 [11:09] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ0_reserved2_MASK 0x00000e00
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ0_reserved2_SHIFT 9
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_WR_DQ0 :: VDL_STEP [08:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ0_VDL_STEP_MASK 0x000001ff
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ0_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ0_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_WR_DQ1 - Write channel DQ1 VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_WR_DQ1 :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ1_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ1_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ1_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_WR_DQ1 :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ1_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ1_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_WR_DQ1 :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ1_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ1_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ1_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_WR_DQ1 :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ1_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ1_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_WR_DQ1 :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ1_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ1_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ1_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_WR_DQ1 :: reserved2 [11:09] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ1_reserved2_MASK 0x00000e00
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ1_reserved2_SHIFT 9
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_WR_DQ1 :: VDL_STEP [08:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ1_VDL_STEP_MASK 0x000001ff
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ1_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ1_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_WR_DQ2 - Write channel DQ2 VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_WR_DQ2 :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ2_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ2_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ2_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_WR_DQ2 :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ2_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ2_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_WR_DQ2 :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ2_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ2_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ2_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_WR_DQ2 :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ2_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ2_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_WR_DQ2 :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ2_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ2_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ2_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_WR_DQ2 :: reserved2 [11:09] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ2_reserved2_MASK 0x00000e00
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ2_reserved2_SHIFT 9
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_WR_DQ2 :: VDL_STEP [08:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ2_VDL_STEP_MASK 0x000001ff
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ2_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ2_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_WR_DQ3 - Write channel DQ3 VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_WR_DQ3 :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ3_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ3_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ3_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_WR_DQ3 :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ3_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ3_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_WR_DQ3 :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ3_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ3_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ3_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_WR_DQ3 :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ3_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ3_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_WR_DQ3 :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ3_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ3_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ3_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_WR_DQ3 :: reserved2 [11:09] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ3_reserved2_MASK 0x00000e00
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ3_reserved2_SHIFT 9
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_WR_DQ3 :: VDL_STEP [08:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ3_VDL_STEP_MASK 0x000001ff
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ3_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ3_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_WR_DQ4 - Write channel DQ4 VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_WR_DQ4 :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ4_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ4_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ4_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_WR_DQ4 :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ4_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ4_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_WR_DQ4 :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ4_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ4_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ4_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_WR_DQ4 :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ4_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ4_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_WR_DQ4 :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ4_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ4_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ4_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_WR_DQ4 :: reserved2 [11:09] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ4_reserved2_MASK 0x00000e00
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ4_reserved2_SHIFT 9
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_WR_DQ4 :: VDL_STEP [08:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ4_VDL_STEP_MASK 0x000001ff
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ4_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ4_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_WR_DQ5 - Write channel DQ5 VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_WR_DQ5 :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ5_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ5_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ5_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_WR_DQ5 :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ5_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ5_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_WR_DQ5 :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ5_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ5_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ5_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_WR_DQ5 :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ5_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ5_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_WR_DQ5 :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ5_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ5_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ5_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_WR_DQ5 :: reserved2 [11:09] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ5_reserved2_MASK 0x00000e00
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ5_reserved2_SHIFT 9
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_WR_DQ5 :: VDL_STEP [08:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ5_VDL_STEP_MASK 0x000001ff
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ5_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ5_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_WR_DQ6 - Write channel DQ6 VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_WR_DQ6 :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ6_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ6_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ6_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_WR_DQ6 :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ6_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ6_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_WR_DQ6 :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ6_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ6_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ6_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_WR_DQ6 :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ6_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ6_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_WR_DQ6 :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ6_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ6_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ6_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_WR_DQ6 :: reserved2 [11:09] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ6_reserved2_MASK 0x00000e00
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ6_reserved2_SHIFT 9
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_WR_DQ6 :: VDL_STEP [08:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ6_VDL_STEP_MASK 0x000001ff
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ6_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ6_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_WR_DQ7 - Write channel DQ7 VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_WR_DQ7 :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ7_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ7_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ7_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_WR_DQ7 :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ7_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ7_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_WR_DQ7 :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ7_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ7_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ7_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_WR_DQ7 :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ7_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ7_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_WR_DQ7 :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ7_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ7_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ7_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_WR_DQ7 :: reserved2 [11:09] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ7_reserved2_MASK 0x00000e00
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ7_reserved2_SHIFT 9
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_WR_DQ7 :: VDL_STEP [08:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ7_VDL_STEP_MASK 0x000001ff
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ7_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ7_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_WR_DM - Write channel DM VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_WR_DM :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DM_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DM_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DM_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_WR_DM :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DM_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DM_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_WR_DM :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DM_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DM_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DM_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_WR_DM :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DM_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DM_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_WR_DM :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DM_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DM_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DM_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_WR_DM :: reserved2 [11:09] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DM_reserved2_MASK 0x00000e00
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DM_reserved2_SHIFT 9
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_WR_DM :: VDL_STEP [08:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DM_VDL_STEP_MASK 0x000001ff
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DM_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DM_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_WR_EDC - Write channel EDC VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_WR_EDC :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_EDC_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_EDC_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_EDC_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_WR_EDC :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_EDC_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_EDC_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_WR_EDC :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_EDC_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_EDC_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_EDC_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_WR_EDC :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_EDC_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_EDC_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_WR_EDC :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_EDC_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_EDC_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_EDC_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_WR_EDC :: reserved2 [11:09] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_EDC_reserved2_MASK 0x00000e00
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_EDC_reserved2_SHIFT 9
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_WR_EDC :: VDL_STEP [08:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_EDC_VDL_STEP_MASK 0x000001ff
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_EDC_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_EDC_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_RD_DQSP - Read channel DQSP VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQSP :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQSP_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQSP_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQSP_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQSP :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQSP_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQSP_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQSP :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQSP_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQSP_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQSP_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQSP :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQSP_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQSP_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQSP :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQSP_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQSP_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQSP_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQSP :: reserved2 [11:08] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQSP_reserved2_MASK 0x00000f00
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQSP_reserved2_SHIFT 8
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQSP :: VDL_STEP [07:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQSP_VDL_STEP_MASK 0x000000ff
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQSP_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQSP_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_RD_DQSN - Read channel DQSP VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQSN :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQSN_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQSN_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQSN_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQSN :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQSN_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQSN_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQSN :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQSN_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQSN_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQSN_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQSN :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQSN_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQSN_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQSN :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQSN_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQSN_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQSN_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQSN :: reserved2 [11:08] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQSN_reserved2_MASK 0x00000f00
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQSN_reserved2_SHIFT 8
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQSN :: VDL_STEP [07:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQSN_VDL_STEP_MASK 0x000000ff
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQSN_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQSN_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_RD_DQ0P - Read channel DQ0-P VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQ0P :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ0P_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ0P_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ0P_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQ0P :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ0P_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ0P_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQ0P :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ0P_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ0P_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ0P_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQ0P :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ0P_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ0P_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQ0P :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ0P_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ0P_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ0P_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQ0P :: reserved2 [11:08] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ0P_reserved2_MASK 0x00000f00
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ0P_reserved2_SHIFT 8
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQ0P :: VDL_STEP [07:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ0P_VDL_STEP_MASK 0x000000ff
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ0P_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ0P_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_RD_DQ0N - Read channel DQ0-N VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQ0N :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ0N_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ0N_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ0N_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQ0N :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ0N_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ0N_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQ0N :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ0N_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ0N_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ0N_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQ0N :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ0N_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ0N_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQ0N :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ0N_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ0N_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ0N_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQ0N :: reserved2 [11:08] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ0N_reserved2_MASK 0x00000f00
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ0N_reserved2_SHIFT 8
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQ0N :: VDL_STEP [07:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ0N_VDL_STEP_MASK 0x000000ff
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ0N_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ0N_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_RD_DQ1P - Read channel DQ1-P VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQ1P :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ1P_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ1P_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ1P_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQ1P :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ1P_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ1P_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQ1P :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ1P_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ1P_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ1P_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQ1P :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ1P_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ1P_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQ1P :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ1P_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ1P_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ1P_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQ1P :: reserved2 [11:08] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ1P_reserved2_MASK 0x00000f00
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ1P_reserved2_SHIFT 8
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQ1P :: VDL_STEP [07:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ1P_VDL_STEP_MASK 0x000000ff
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ1P_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ1P_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_RD_DQ1N - Read channel DQ1-N VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQ1N :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ1N_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ1N_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ1N_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQ1N :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ1N_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ1N_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQ1N :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ1N_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ1N_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ1N_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQ1N :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ1N_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ1N_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQ1N :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ1N_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ1N_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ1N_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQ1N :: reserved2 [11:08] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ1N_reserved2_MASK 0x00000f00
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ1N_reserved2_SHIFT 8
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQ1N :: VDL_STEP [07:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ1N_VDL_STEP_MASK 0x000000ff
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ1N_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ1N_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_RD_DQ2P - Read channel DQ2-P VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQ2P :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ2P_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ2P_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ2P_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQ2P :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ2P_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ2P_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQ2P :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ2P_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ2P_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ2P_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQ2P :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ2P_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ2P_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQ2P :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ2P_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ2P_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ2P_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQ2P :: reserved2 [11:08] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ2P_reserved2_MASK 0x00000f00
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ2P_reserved2_SHIFT 8
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQ2P :: VDL_STEP [07:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ2P_VDL_STEP_MASK 0x000000ff
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ2P_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ2P_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_RD_DQ2N - Read channel DQ2-N VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQ2N :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ2N_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ2N_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ2N_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQ2N :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ2N_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ2N_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQ2N :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ2N_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ2N_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ2N_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQ2N :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ2N_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ2N_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQ2N :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ2N_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ2N_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ2N_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQ2N :: reserved2 [11:08] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ2N_reserved2_MASK 0x00000f00
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ2N_reserved2_SHIFT 8
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQ2N :: VDL_STEP [07:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ2N_VDL_STEP_MASK 0x000000ff
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ2N_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ2N_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_RD_DQ3P - Read channel DQ3-P VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQ3P :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ3P_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ3P_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ3P_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQ3P :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ3P_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ3P_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQ3P :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ3P_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ3P_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ3P_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQ3P :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ3P_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ3P_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQ3P :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ3P_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ3P_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ3P_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQ3P :: reserved2 [11:08] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ3P_reserved2_MASK 0x00000f00
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ3P_reserved2_SHIFT 8
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQ3P :: VDL_STEP [07:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ3P_VDL_STEP_MASK 0x000000ff
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ3P_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ3P_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_RD_DQ3N - Read channel DQ3-N VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQ3N :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ3N_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ3N_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ3N_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQ3N :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ3N_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ3N_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQ3N :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ3N_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ3N_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ3N_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQ3N :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ3N_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ3N_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQ3N :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ3N_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ3N_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ3N_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQ3N :: reserved2 [11:08] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ3N_reserved2_MASK 0x00000f00
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ3N_reserved2_SHIFT 8
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQ3N :: VDL_STEP [07:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ3N_VDL_STEP_MASK 0x000000ff
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ3N_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ3N_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_RD_DQ4P - Read channel DQ4-P VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQ4P :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ4P_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ4P_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ4P_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQ4P :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ4P_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ4P_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQ4P :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ4P_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ4P_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ4P_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQ4P :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ4P_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ4P_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQ4P :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ4P_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ4P_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ4P_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQ4P :: reserved2 [11:08] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ4P_reserved2_MASK 0x00000f00
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ4P_reserved2_SHIFT 8
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQ4P :: VDL_STEP [07:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ4P_VDL_STEP_MASK 0x000000ff
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ4P_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ4P_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_RD_DQ4N - Read channel DQ4-N VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQ4N :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ4N_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ4N_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ4N_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQ4N :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ4N_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ4N_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQ4N :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ4N_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ4N_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ4N_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQ4N :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ4N_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ4N_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQ4N :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ4N_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ4N_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ4N_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQ4N :: reserved2 [11:08] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ4N_reserved2_MASK 0x00000f00
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ4N_reserved2_SHIFT 8
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQ4N :: VDL_STEP [07:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ4N_VDL_STEP_MASK 0x000000ff
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ4N_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ4N_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_RD_DQ5P - Read channel DQ5-P VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQ5P :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ5P_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ5P_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ5P_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQ5P :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ5P_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ5P_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQ5P :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ5P_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ5P_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ5P_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQ5P :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ5P_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ5P_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQ5P :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ5P_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ5P_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ5P_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQ5P :: reserved2 [11:08] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ5P_reserved2_MASK 0x00000f00
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ5P_reserved2_SHIFT 8
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQ5P :: VDL_STEP [07:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ5P_VDL_STEP_MASK 0x000000ff
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ5P_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ5P_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_RD_DQ5N - Read channel DQ5-N VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQ5N :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ5N_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ5N_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ5N_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQ5N :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ5N_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ5N_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQ5N :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ5N_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ5N_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ5N_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQ5N :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ5N_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ5N_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQ5N :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ5N_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ5N_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ5N_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQ5N :: reserved2 [11:08] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ5N_reserved2_MASK 0x00000f00
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ5N_reserved2_SHIFT 8
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQ5N :: VDL_STEP [07:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ5N_VDL_STEP_MASK 0x000000ff
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ5N_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ5N_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_RD_DQ6P - Read channel DQ6-P VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQ6P :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ6P_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ6P_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ6P_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQ6P :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ6P_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ6P_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQ6P :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ6P_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ6P_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ6P_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQ6P :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ6P_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ6P_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQ6P :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ6P_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ6P_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ6P_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQ6P :: reserved2 [11:08] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ6P_reserved2_MASK 0x00000f00
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ6P_reserved2_SHIFT 8
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQ6P :: VDL_STEP [07:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ6P_VDL_STEP_MASK 0x000000ff
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ6P_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ6P_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_RD_DQ6N - Read channel DQ6-N VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQ6N :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ6N_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ6N_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ6N_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQ6N :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ6N_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ6N_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQ6N :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ6N_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ6N_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ6N_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQ6N :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ6N_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ6N_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQ6N :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ6N_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ6N_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ6N_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQ6N :: reserved2 [11:08] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ6N_reserved2_MASK 0x00000f00
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ6N_reserved2_SHIFT 8
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQ6N :: VDL_STEP [07:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ6N_VDL_STEP_MASK 0x000000ff
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ6N_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ6N_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_RD_DQ7P - Read channel DQ7-P VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQ7P :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ7P_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ7P_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ7P_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQ7P :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ7P_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ7P_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQ7P :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ7P_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ7P_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ7P_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQ7P :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ7P_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ7P_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQ7P :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ7P_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ7P_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ7P_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQ7P :: reserved2 [11:08] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ7P_reserved2_MASK 0x00000f00
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ7P_reserved2_SHIFT 8
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQ7P :: VDL_STEP [07:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ7P_VDL_STEP_MASK 0x000000ff
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ7P_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ7P_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_RD_DQ7N - Read channel DQ7-N VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQ7N :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ7N_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ7N_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ7N_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQ7N :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ7N_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ7N_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQ7N :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ7N_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ7N_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ7N_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQ7N :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ7N_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ7N_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQ7N :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ7N_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ7N_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ7N_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQ7N :: reserved2 [11:08] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ7N_reserved2_MASK 0x00000f00
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ7N_reserved2_SHIFT 8
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQ7N :: VDL_STEP [07:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ7N_VDL_STEP_MASK 0x000000ff
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ7N_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ7N_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_RD_DMP - Read channel DM-P VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DMP :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DMP_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DMP_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DMP_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DMP :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DMP_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DMP_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DMP :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DMP_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DMP_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DMP_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DMP :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DMP_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DMP_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DMP :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DMP_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DMP_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DMP_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DMP :: reserved2 [11:08] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DMP_reserved2_MASK 0x00000f00
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DMP_reserved2_SHIFT 8
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DMP :: VDL_STEP [07:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DMP_VDL_STEP_MASK 0x000000ff
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DMP_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DMP_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_RD_DMN - Read channel DM-N VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DMN :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DMN_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DMN_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DMN_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DMN :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DMN_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DMN_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DMN :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DMN_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DMN_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DMN_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DMN :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DMN_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DMN_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DMN :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DMN_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DMN_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DMN_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DMN :: reserved2 [11:08] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DMN_reserved2_MASK 0x00000f00
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DMN_reserved2_SHIFT 8
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DMN :: VDL_STEP [07:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DMN_VDL_STEP_MASK 0x000000ff
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DMN_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DMN_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_RD_EDCP - Read channel EDC-P VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_EDCP :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_EDCP_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_EDCP_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_EDCP_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_EDCP :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_EDCP_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_EDCP_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_EDCP :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_EDCP_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_EDCP_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_EDCP_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_EDCP :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_EDCP_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_EDCP_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_EDCP :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_EDCP_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_EDCP_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_EDCP_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_EDCP :: reserved2 [11:08] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_EDCP_reserved2_MASK 0x00000f00
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_EDCP_reserved2_SHIFT 8
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_EDCP :: VDL_STEP [07:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_EDCP_VDL_STEP_MASK 0x000000ff
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_EDCP_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_EDCP_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_RD_EDCN - Read channel EDC-N VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_EDCN :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_EDCN_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_EDCN_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_EDCN_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_EDCN :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_EDCN_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_EDCN_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_EDCN :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_EDCN_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_EDCN_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_EDCN_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_EDCN :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_EDCN_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_EDCN_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_EDCN :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_EDCN_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_EDCN_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_EDCN_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_EDCN :: reserved2 [11:08] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_EDCN_reserved2_MASK 0x00000f00
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_EDCN_reserved2_SHIFT 8
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_EDCN :: VDL_STEP [07:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_EDCN_VDL_STEP_MASK 0x000000ff
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_EDCN_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_EDCN_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_RD_EN_CS0 - Read channel CS_N[0] read enable VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_EN_CS0 :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_EN_CS0_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_EN_CS0_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_EN_CS0_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_EN_CS0 :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_EN_CS0_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_EN_CS0_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_EN_CS0 :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_EN_CS0_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_EN_CS0_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_EN_CS0_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_EN_CS0 :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_EN_CS0_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_EN_CS0_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_EN_CS0 :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_EN_CS0_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_EN_CS0_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_EN_CS0_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_EN_CS0 :: reserved2 [11:08] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_EN_CS0_reserved2_MASK 0x00000f00
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_EN_CS0_reserved2_SHIFT 8
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_EN_CS0 :: VDL_STEP [07:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_EN_CS0_VDL_STEP_MASK 0x000000ff
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_EN_CS0_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_EN_CS0_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_RD_EN_CS1 - Read channel CS_N[1] read enable VDL control register (used for reads when only cs1_n is active)
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_EN_CS1 :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_EN_CS1_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_EN_CS1_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_EN_CS1_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_EN_CS1 :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_EN_CS1_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_EN_CS1_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_EN_CS1 :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_EN_CS1_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_EN_CS1_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_EN_CS1_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_EN_CS1 :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_EN_CS1_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_EN_CS1_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_EN_CS1 :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_EN_CS1_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_EN_CS1_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_EN_CS1_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_EN_CS1 :: reserved2 [11:08] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_EN_CS1_reserved2_MASK 0x00000f00
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_EN_CS1_reserved2_SHIFT 8
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_EN_CS1 :: VDL_STEP [07:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_EN_CS1_VDL_STEP_MASK 0x000000ff
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_EN_CS1_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_EN_CS1_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_RD_EN_CRC - Read channel GDDR5 CRC read enable VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_EN_CRC :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_EN_CRC_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_EN_CRC_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_EN_CRC_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_EN_CRC :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_EN_CRC_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_EN_CRC_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_EN_CRC :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_EN_CRC_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_EN_CRC_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_EN_CRC_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_EN_CRC :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_EN_CRC_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_EN_CRC_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_EN_CRC :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_EN_CRC_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_EN_CRC_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_EN_CRC_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_EN_CRC :: reserved2 [11:08] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_EN_CRC_reserved2_MASK 0x00000f00
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_EN_CRC_reserved2_SHIFT 8
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_EN_CRC :: VDL_STEP [07:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_EN_CRC_VDL_STEP_MASK 0x000000ff
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_EN_CRC_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_EN_CRC_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CLK_CONTROL - DDR interface signal Write Leveling CLK VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CLK_CONTROL :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CLK_CONTROL_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CLK_CONTROL_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CLK_CONTROL_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CLK_CONTROL :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CLK_CONTROL_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CLK_CONTROL_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CLK_CONTROL :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CLK_CONTROL_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CLK_CONTROL_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CLK_CONTROL_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CLK_CONTROL :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CLK_CONTROL_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CLK_CONTROL_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CLK_CONTROL :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CLK_CONTROL_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CLK_CONTROL_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CLK_CONTROL_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CLK_CONTROL :: reserved2 [11:09] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CLK_CONTROL_reserved2_MASK 0x00000e00
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CLK_CONTROL_reserved2_SHIFT 9
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CLK_CONTROL :: VDL_STEP [08:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CLK_CONTROL_VDL_STEP_MASK 0x000001ff
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CLK_CONTROL_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CLK_CONTROL_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_LDE_CONTROL - DDR interface signal Write Leveling Capture Enable VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_LDE_CONTROL :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_LDE_CONTROL_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_LDE_CONTROL_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_LDE_CONTROL_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_LDE_CONTROL :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_LDE_CONTROL_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_LDE_CONTROL_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_LDE_CONTROL :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_LDE_CONTROL_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_LDE_CONTROL_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_LDE_CONTROL_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_LDE_CONTROL :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_LDE_CONTROL_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_LDE_CONTROL_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_LDE_CONTROL :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_LDE_CONTROL_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_LDE_CONTROL_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_LDE_CONTROL_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_LDE_CONTROL :: reserved2 [11:09] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_LDE_CONTROL_reserved2_MASK 0x00000e00
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_LDE_CONTROL_reserved2_SHIFT 9
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_LDE_CONTROL :: VDL_STEP [08:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_LDE_CONTROL_VDL_STEP_MASK 0x000001ff
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_LDE_CONTROL_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_LDE_CONTROL_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *RD_EN_DLY_CYC - Read enable bit-clock cycle delay control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_2_0 :: RD_EN_DLY_CYC :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_RD_EN_DLY_CYC_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_RD_EN_DLY_CYC_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_RD_EN_DLY_CYC_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: RD_EN_DLY_CYC :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_RD_EN_DLY_CYC_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_RD_EN_DLY_CYC_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: RD_EN_DLY_CYC :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_RD_EN_DLY_CYC_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_RD_EN_DLY_CYC_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_RD_EN_DLY_CYC_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: RD_EN_DLY_CYC :: reserved1 [15:14] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_RD_EN_DLY_CYC_reserved1_MASK 0x0000c000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_RD_EN_DLY_CYC_reserved1_SHIFT 14
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: RD_EN_DLY_CYC :: CRC_CYCLES [13:10] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_RD_EN_DLY_CYC_CRC_CYCLES_MASK 0x00003c00
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_RD_EN_DLY_CYC_CRC_CYCLES_SHIFT 10
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_RD_EN_DLY_CYC_CRC_CYCLES_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: RD_EN_DLY_CYC :: reserved2 [09:09] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_RD_EN_DLY_CYC_reserved2_MASK 0x00000200
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_RD_EN_DLY_CYC_reserved2_SHIFT 9
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: RD_EN_DLY_CYC :: ENABLE_CS1 [08:08] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_RD_EN_DLY_CYC_ENABLE_CS1_MASK 0x00000100
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_RD_EN_DLY_CYC_ENABLE_CS1_SHIFT 8
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_RD_EN_DLY_CYC_ENABLE_CS1_DEFAULT 0x00000001
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: RD_EN_DLY_CYC :: CS1_CYCLES [07:04] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_RD_EN_DLY_CYC_CS1_CYCLES_MASK 0x000000f0
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_RD_EN_DLY_CYC_CS1_CYCLES_SHIFT 4
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_RD_EN_DLY_CYC_CS1_CYCLES_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: RD_EN_DLY_CYC :: CS0_CYCLES [03:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_RD_EN_DLY_CYC_CS0_CYCLES_MASK 0x0000000f
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_RD_EN_DLY_CYC_CS0_CYCLES_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_RD_EN_DLY_CYC_CS0_CYCLES_DEFAULT 0x00000000
-
-/***************************************************************************
- *WR_CHAN_DLY_CYC - Write leveling bit-clock cycle delay control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_2_0 :: WR_CHAN_DLY_CYC :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_WR_CHAN_DLY_CYC_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_WR_CHAN_DLY_CYC_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_WR_CHAN_DLY_CYC_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: WR_CHAN_DLY_CYC :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_WR_CHAN_DLY_CYC_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_WR_CHAN_DLY_CYC_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: WR_CHAN_DLY_CYC :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_WR_CHAN_DLY_CYC_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_WR_CHAN_DLY_CYC_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_WR_CHAN_DLY_CYC_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: WR_CHAN_DLY_CYC :: reserved1 [15:08] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_WR_CHAN_DLY_CYC_reserved1_MASK 0x0000ff00
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_WR_CHAN_DLY_CYC_reserved1_SHIFT 8
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: WR_CHAN_DLY_CYC :: DQ_CYCLES [07:04] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_WR_CHAN_DLY_CYC_DQ_CYCLES_MASK 0x000000f0
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_WR_CHAN_DLY_CYC_DQ_CYCLES_SHIFT 4
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_WR_CHAN_DLY_CYC_DQ_CYCLES_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: WR_CHAN_DLY_CYC :: reserved2 [03:03] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_WR_CHAN_DLY_CYC_reserved2_MASK 0x00000008
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_WR_CHAN_DLY_CYC_reserved2_SHIFT 3
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: WR_CHAN_DLY_CYC :: CYCLES [02:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_WR_CHAN_DLY_CYC_CYCLES_MASK 0x00000007
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_WR_CHAN_DLY_CYC_CYCLES_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_WR_CHAN_DLY_CYC_CYCLES_DEFAULT 0x00000000
-
-/***************************************************************************
- *READ_CONTROL - Read channel datapath control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_2_0 :: READ_CONTROL :: reserved0 [31:05] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_READ_CONTROL_reserved0_MASK 0xffffffe0
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_READ_CONTROL_reserved0_SHIFT 5
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: READ_CONTROL :: MODE [04:04] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_READ_CONTROL_MODE_MASK 0x00000010
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_READ_CONTROL_MODE_SHIFT 4
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_READ_CONTROL_MODE_DEFAULT 0x00000001
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: READ_CONTROL :: RD_EN_MODE [03:03] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_READ_CONTROL_RD_EN_MODE_MASK 0x00000008
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_READ_CONTROL_RD_EN_MODE_SHIFT 3
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_READ_CONTROL_RD_EN_MODE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: READ_CONTROL :: RD_DATA_DLY [02:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_READ_CONTROL_RD_DATA_DLY_MASK 0x00000007
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_READ_CONTROL_RD_DATA_DLY_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_READ_CONTROL_RD_DATA_DLY_DEFAULT 0x00000007
-
-/***************************************************************************
- *READ_FIFO_ADDR - Read fifo addresss pointer register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_2_0 :: READ_FIFO_ADDR :: reserved0 [31:03] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_READ_FIFO_ADDR_reserved0_MASK 0xfffffff8
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_READ_FIFO_ADDR_reserved0_SHIFT 3
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: READ_FIFO_ADDR :: ADDR [02:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_READ_FIFO_ADDR_ADDR_MASK 0x00000007
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_READ_FIFO_ADDR_ADDR_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_READ_FIFO_ADDR_ADDR_DEFAULT 0x00000000
-
-/***************************************************************************
- *READ_FIFO_DATA - Read fifo data register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_2_0 :: READ_FIFO_DATA :: DATA [31:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_READ_FIFO_DATA_DATA_MASK 0xffffffff
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_READ_FIFO_DATA_DATA_SHIFT 0
-
-/***************************************************************************
- *READ_FIFO_DM_DBI - Read fifo dm/dbi register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_2_0 :: READ_FIFO_DM_DBI :: reserved0 [31:04] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_READ_FIFO_DM_DBI_reserved0_MASK 0xfffffff0
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_READ_FIFO_DM_DBI_reserved0_SHIFT 4
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: READ_FIFO_DM_DBI :: DM_DBI [03:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_READ_FIFO_DM_DBI_DM_DBI_MASK 0x0000000f
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_READ_FIFO_DM_DBI_DM_DBI_SHIFT 0
-
-/***************************************************************************
- *READ_FIFO_STATUS - Read fifo status register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_2_0 :: READ_FIFO_STATUS :: reserved0 [31:02] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_READ_FIFO_STATUS_reserved0_MASK 0xfffffffc
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_READ_FIFO_STATUS_reserved0_SHIFT 2
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: READ_FIFO_STATUS :: OVERFLOW [01:01] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_READ_FIFO_STATUS_OVERFLOW_MASK 0x00000002
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_READ_FIFO_STATUS_OVERFLOW_SHIFT 1
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_READ_FIFO_STATUS_OVERFLOW_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: READ_FIFO_STATUS :: UNDERFLOW [00:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_READ_FIFO_STATUS_UNDERFLOW_MASK 0x00000001
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_READ_FIFO_STATUS_UNDERFLOW_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_READ_FIFO_STATUS_UNDERFLOW_DEFAULT 0x00000000
-
-/***************************************************************************
- *READ_FIFO_CLEAR - Read fifo status clear register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_2_0 :: READ_FIFO_CLEAR :: reserved0 [31:01] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_READ_FIFO_CLEAR_reserved0_MASK 0xfffffffe
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_READ_FIFO_CLEAR_reserved0_SHIFT 1
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: READ_FIFO_CLEAR :: CLEAR [00:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_READ_FIFO_CLEAR_CLEAR_MASK 0x00000001
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_READ_FIFO_CLEAR_CLEAR_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_READ_FIFO_CLEAR_CLEAR_DEFAULT 0x00000000
-
-/***************************************************************************
- *IDLE_PAD_CONTROL - Idle mode SSTL pad control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_2_0 :: IDLE_PAD_CONTROL :: IDLE [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_IDLE_PAD_CONTROL_IDLE_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_IDLE_PAD_CONTROL_IDLE_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_IDLE_PAD_CONTROL_IDLE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: IDLE_PAD_CONTROL :: reserved0 [30:20] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_IDLE_PAD_CONTROL_reserved0_MASK 0x7ff00000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_IDLE_PAD_CONTROL_reserved0_SHIFT 20
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: IDLE_PAD_CONTROL :: AUTO_DQ_RXENB_MODE [19:18] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_IDLE_PAD_CONTROL_AUTO_DQ_RXENB_MODE_MASK 0x000c0000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_IDLE_PAD_CONTROL_AUTO_DQ_RXENB_MODE_SHIFT 18
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_IDLE_PAD_CONTROL_AUTO_DQ_RXENB_MODE_DEFAULT 0x00000003
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: IDLE_PAD_CONTROL :: AUTO_DQ_IDDQ_MODE [17:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_IDLE_PAD_CONTROL_AUTO_DQ_IDDQ_MODE_MASK 0x00030000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_IDLE_PAD_CONTROL_AUTO_DQ_IDDQ_MODE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_IDLE_PAD_CONTROL_AUTO_DQ_IDDQ_MODE_DEFAULT 0x00000003
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: IDLE_PAD_CONTROL :: IO_IDLE_ENABLE [15:04] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_IDLE_PAD_CONTROL_IO_IDLE_ENABLE_MASK 0x0000fff0
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_IDLE_PAD_CONTROL_IO_IDLE_ENABLE_SHIFT 4
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_IDLE_PAD_CONTROL_IO_IDLE_ENABLE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: IDLE_PAD_CONTROL :: RXENB [03:03] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_IDLE_PAD_CONTROL_RXENB_MASK 0x00000008
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_IDLE_PAD_CONTROL_RXENB_SHIFT 3
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_IDLE_PAD_CONTROL_RXENB_DEFAULT 0x00000001
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: IDLE_PAD_CONTROL :: IDDQ [02:02] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_IDLE_PAD_CONTROL_IDDQ_MASK 0x00000004
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_IDLE_PAD_CONTROL_IDDQ_SHIFT 2
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_IDLE_PAD_CONTROL_IDDQ_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: IDLE_PAD_CONTROL :: DOUT_N [01:01] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_IDLE_PAD_CONTROL_DOUT_N_MASK 0x00000002
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_IDLE_PAD_CONTROL_DOUT_N_SHIFT 1
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_IDLE_PAD_CONTROL_DOUT_N_DEFAULT 0x00000001
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: IDLE_PAD_CONTROL :: DOUT_P [00:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_IDLE_PAD_CONTROL_DOUT_P_MASK 0x00000001
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_IDLE_PAD_CONTROL_DOUT_P_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_IDLE_PAD_CONTROL_DOUT_P_DEFAULT 0x00000000
-
-/***************************************************************************
- *DRIVE_PAD_CTL - DQ, DM pad drive characteristics control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_2_0 :: DRIVE_PAD_CTL :: reserved0 [31:30] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_DRIVE_PAD_CTL_reserved0_MASK 0xc0000000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_DRIVE_PAD_CTL_reserved0_SHIFT 30
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: DRIVE_PAD_CTL :: BL_PD_IDLE_STRENGTH [29:25] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_DRIVE_PAD_CTL_BL_PD_IDLE_STRENGTH_MASK 0x3e000000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_DRIVE_PAD_CTL_BL_PD_IDLE_STRENGTH_SHIFT 25
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_DRIVE_PAD_CTL_BL_PD_IDLE_STRENGTH_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: DRIVE_PAD_CTL :: BL_ND_IDLE_STRENGTH [24:20] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_DRIVE_PAD_CTL_BL_ND_IDLE_STRENGTH_MASK 0x01f00000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_DRIVE_PAD_CTL_BL_ND_IDLE_STRENGTH_SHIFT 20
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_DRIVE_PAD_CTL_BL_ND_IDLE_STRENGTH_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: DRIVE_PAD_CTL :: BL_PD_TERM_STRENGTH [19:15] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_DRIVE_PAD_CTL_BL_PD_TERM_STRENGTH_MASK 0x000f8000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_DRIVE_PAD_CTL_BL_PD_TERM_STRENGTH_SHIFT 15
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_DRIVE_PAD_CTL_BL_PD_TERM_STRENGTH_DEFAULT 0x00000008
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: DRIVE_PAD_CTL :: BL_ND_TERM_STRENGTH [14:10] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_DRIVE_PAD_CTL_BL_ND_TERM_STRENGTH_MASK 0x00007c00
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_DRIVE_PAD_CTL_BL_ND_TERM_STRENGTH_SHIFT 10
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_DRIVE_PAD_CTL_BL_ND_TERM_STRENGTH_DEFAULT 0x00000008
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: DRIVE_PAD_CTL :: BL_PD_STRENGTH [09:05] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_DRIVE_PAD_CTL_BL_PD_STRENGTH_MASK 0x000003e0
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_DRIVE_PAD_CTL_BL_PD_STRENGTH_SHIFT 5
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_DRIVE_PAD_CTL_BL_PD_STRENGTH_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: DRIVE_PAD_CTL :: BL_ND_STRENGTH [04:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_DRIVE_PAD_CTL_BL_ND_STRENGTH_MASK 0x0000001f
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_DRIVE_PAD_CTL_BL_ND_STRENGTH_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_DRIVE_PAD_CTL_BL_ND_STRENGTH_DEFAULT 0x00000000
-
-/***************************************************************************
- *DQSP_DRIVE_PAD_CTL - DQS pad P rail drive characteristics control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_2_0 :: DQSP_DRIVE_PAD_CTL :: reserved0 [31:30] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_DQSP_DRIVE_PAD_CTL_reserved0_MASK 0xc0000000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_DQSP_DRIVE_PAD_CTL_reserved0_SHIFT 30
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: DQSP_DRIVE_PAD_CTL :: BL_PD_IDLE_STRENGTH [29:25] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_DQSP_DRIVE_PAD_CTL_BL_PD_IDLE_STRENGTH_MASK 0x3e000000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_DQSP_DRIVE_PAD_CTL_BL_PD_IDLE_STRENGTH_SHIFT 25
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_DQSP_DRIVE_PAD_CTL_BL_PD_IDLE_STRENGTH_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: DQSP_DRIVE_PAD_CTL :: BL_ND_IDLE_STRENGTH [24:20] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_DQSP_DRIVE_PAD_CTL_BL_ND_IDLE_STRENGTH_MASK 0x01f00000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_DQSP_DRIVE_PAD_CTL_BL_ND_IDLE_STRENGTH_SHIFT 20
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_DQSP_DRIVE_PAD_CTL_BL_ND_IDLE_STRENGTH_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: DQSP_DRIVE_PAD_CTL :: BL_PD_TERM_STRENGTH [19:15] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_DQSP_DRIVE_PAD_CTL_BL_PD_TERM_STRENGTH_MASK 0x000f8000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_DQSP_DRIVE_PAD_CTL_BL_PD_TERM_STRENGTH_SHIFT 15
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_DQSP_DRIVE_PAD_CTL_BL_PD_TERM_STRENGTH_DEFAULT 0x00000008
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: DQSP_DRIVE_PAD_CTL :: BL_ND_TERM_STRENGTH [14:10] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_DQSP_DRIVE_PAD_CTL_BL_ND_TERM_STRENGTH_MASK 0x00007c00
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_DQSP_DRIVE_PAD_CTL_BL_ND_TERM_STRENGTH_SHIFT 10
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_DQSP_DRIVE_PAD_CTL_BL_ND_TERM_STRENGTH_DEFAULT 0x00000008
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: DQSP_DRIVE_PAD_CTL :: BL_PD_STRENGTH [09:05] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_DQSP_DRIVE_PAD_CTL_BL_PD_STRENGTH_MASK 0x000003e0
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_DQSP_DRIVE_PAD_CTL_BL_PD_STRENGTH_SHIFT 5
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_DQSP_DRIVE_PAD_CTL_BL_PD_STRENGTH_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: DQSP_DRIVE_PAD_CTL :: BL_ND_STRENGTH [04:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_DQSP_DRIVE_PAD_CTL_BL_ND_STRENGTH_MASK 0x0000001f
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_DQSP_DRIVE_PAD_CTL_BL_ND_STRENGTH_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_DQSP_DRIVE_PAD_CTL_BL_ND_STRENGTH_DEFAULT 0x00000000
-
-/***************************************************************************
- *DQSN_DRIVE_PAD_CTL - DQS pad N rail drive characteristics control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_2_0 :: DQSN_DRIVE_PAD_CTL :: reserved0 [31:30] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_DQSN_DRIVE_PAD_CTL_reserved0_MASK 0xc0000000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_DQSN_DRIVE_PAD_CTL_reserved0_SHIFT 30
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: DQSN_DRIVE_PAD_CTL :: BL_PD_IDLE_STRENGTH [29:25] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_DQSN_DRIVE_PAD_CTL_BL_PD_IDLE_STRENGTH_MASK 0x3e000000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_DQSN_DRIVE_PAD_CTL_BL_PD_IDLE_STRENGTH_SHIFT 25
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_DQSN_DRIVE_PAD_CTL_BL_PD_IDLE_STRENGTH_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: DQSN_DRIVE_PAD_CTL :: BL_ND_IDLE_STRENGTH [24:20] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_DQSN_DRIVE_PAD_CTL_BL_ND_IDLE_STRENGTH_MASK 0x01f00000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_DQSN_DRIVE_PAD_CTL_BL_ND_IDLE_STRENGTH_SHIFT 20
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_DQSN_DRIVE_PAD_CTL_BL_ND_IDLE_STRENGTH_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: DQSN_DRIVE_PAD_CTL :: BL_PD_TERM_STRENGTH [19:15] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_DQSN_DRIVE_PAD_CTL_BL_PD_TERM_STRENGTH_MASK 0x000f8000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_DQSN_DRIVE_PAD_CTL_BL_PD_TERM_STRENGTH_SHIFT 15
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_DQSN_DRIVE_PAD_CTL_BL_PD_TERM_STRENGTH_DEFAULT 0x00000008
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: DQSN_DRIVE_PAD_CTL :: BL_ND_TERM_STRENGTH [14:10] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_DQSN_DRIVE_PAD_CTL_BL_ND_TERM_STRENGTH_MASK 0x00007c00
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_DQSN_DRIVE_PAD_CTL_BL_ND_TERM_STRENGTH_SHIFT 10
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_DQSN_DRIVE_PAD_CTL_BL_ND_TERM_STRENGTH_DEFAULT 0x00000008
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: DQSN_DRIVE_PAD_CTL :: BL_PD_STRENGTH [09:05] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_DQSN_DRIVE_PAD_CTL_BL_PD_STRENGTH_MASK 0x000003e0
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_DQSN_DRIVE_PAD_CTL_BL_PD_STRENGTH_SHIFT 5
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_DQSN_DRIVE_PAD_CTL_BL_PD_STRENGTH_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: DQSN_DRIVE_PAD_CTL :: BL_ND_STRENGTH [04:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_DQSN_DRIVE_PAD_CTL_BL_ND_STRENGTH_MASK 0x0000001f
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_DQSN_DRIVE_PAD_CTL_BL_ND_STRENGTH_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_DQSN_DRIVE_PAD_CTL_BL_ND_STRENGTH_DEFAULT 0x00000000
-
-/***************************************************************************
- *EDC_DRIVE_PAD_CTL - EDC pad drive characteristics control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_2_0 :: EDC_DRIVE_PAD_CTL :: reserved0 [31:30] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_DRIVE_PAD_CTL_reserved0_MASK 0xc0000000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_DRIVE_PAD_CTL_reserved0_SHIFT 30
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: EDC_DRIVE_PAD_CTL :: BL_PD_IDLE_STRENGTH [29:25] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_DRIVE_PAD_CTL_BL_PD_IDLE_STRENGTH_MASK 0x3e000000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_DRIVE_PAD_CTL_BL_PD_IDLE_STRENGTH_SHIFT 25
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_DRIVE_PAD_CTL_BL_PD_IDLE_STRENGTH_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: EDC_DRIVE_PAD_CTL :: BL_ND_IDLE_STRENGTH [24:20] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_DRIVE_PAD_CTL_BL_ND_IDLE_STRENGTH_MASK 0x01f00000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_DRIVE_PAD_CTL_BL_ND_IDLE_STRENGTH_SHIFT 20
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_DRIVE_PAD_CTL_BL_ND_IDLE_STRENGTH_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: EDC_DRIVE_PAD_CTL :: BL_PD_TERM_STRENGTH [19:15] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_DRIVE_PAD_CTL_BL_PD_TERM_STRENGTH_MASK 0x000f8000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_DRIVE_PAD_CTL_BL_PD_TERM_STRENGTH_SHIFT 15
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_DRIVE_PAD_CTL_BL_PD_TERM_STRENGTH_DEFAULT 0x00000008
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: EDC_DRIVE_PAD_CTL :: BL_ND_TERM_STRENGTH [14:10] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_DRIVE_PAD_CTL_BL_ND_TERM_STRENGTH_MASK 0x00007c00
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_DRIVE_PAD_CTL_BL_ND_TERM_STRENGTH_SHIFT 10
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_DRIVE_PAD_CTL_BL_ND_TERM_STRENGTH_DEFAULT 0x00000008
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: EDC_DRIVE_PAD_CTL :: BL_PD_STRENGTH [09:05] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_DRIVE_PAD_CTL_BL_PD_STRENGTH_MASK 0x000003e0
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_DRIVE_PAD_CTL_BL_PD_STRENGTH_SHIFT 5
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_DRIVE_PAD_CTL_BL_PD_STRENGTH_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: EDC_DRIVE_PAD_CTL :: BL_ND_STRENGTH [04:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_DRIVE_PAD_CTL_BL_ND_STRENGTH_MASK 0x0000001f
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_DRIVE_PAD_CTL_BL_ND_STRENGTH_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_DRIVE_PAD_CTL_BL_ND_STRENGTH_DEFAULT 0x00000000
-
-/***************************************************************************
- *RD_EN_DRIVE_PAD_CTL - RD_EN, EDC_RD_EN read enable pad drive characteristics control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_2_0 :: RD_EN_DRIVE_PAD_CTL :: reserved0 [31:20] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_RD_EN_DRIVE_PAD_CTL_reserved0_MASK 0xfff00000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_RD_EN_DRIVE_PAD_CTL_reserved0_SHIFT 20
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: RD_EN_DRIVE_PAD_CTL :: EDC_RD_EN_PD_STRENGTH [19:15] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_RD_EN_DRIVE_PAD_CTL_EDC_RD_EN_PD_STRENGTH_MASK 0x000f8000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_RD_EN_DRIVE_PAD_CTL_EDC_RD_EN_PD_STRENGTH_SHIFT 15
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_RD_EN_DRIVE_PAD_CTL_EDC_RD_EN_PD_STRENGTH_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: RD_EN_DRIVE_PAD_CTL :: EDC_RD_EN_ND_STRENGTH [14:10] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_RD_EN_DRIVE_PAD_CTL_EDC_RD_EN_ND_STRENGTH_MASK 0x00007c00
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_RD_EN_DRIVE_PAD_CTL_EDC_RD_EN_ND_STRENGTH_SHIFT 10
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_RD_EN_DRIVE_PAD_CTL_EDC_RD_EN_ND_STRENGTH_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: RD_EN_DRIVE_PAD_CTL :: BL_RD_EN_PD_STRENGTH [09:05] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_RD_EN_DRIVE_PAD_CTL_BL_RD_EN_PD_STRENGTH_MASK 0x000003e0
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_RD_EN_DRIVE_PAD_CTL_BL_RD_EN_PD_STRENGTH_SHIFT 5
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_RD_EN_DRIVE_PAD_CTL_BL_RD_EN_PD_STRENGTH_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: RD_EN_DRIVE_PAD_CTL :: BL_RD_EN_ND_STRENGTH [04:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_RD_EN_DRIVE_PAD_CTL_BL_RD_EN_ND_STRENGTH_MASK 0x0000001f
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_RD_EN_DRIVE_PAD_CTL_BL_RD_EN_ND_STRENGTH_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_RD_EN_DRIVE_PAD_CTL_BL_RD_EN_ND_STRENGTH_DEFAULT 0x00000000
-
-/***************************************************************************
- *STATIC_PAD_CTL - pad rx and tx characteristics control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_2_0 :: STATIC_PAD_CTL :: reserved0 [31:25] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_STATIC_PAD_CTL_reserved0_MASK 0xfe000000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_STATIC_PAD_CTL_reserved0_SHIFT 25
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: STATIC_PAD_CTL :: TX_SLEW [24:23] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_STATIC_PAD_CTL_TX_SLEW_MASK 0x01800000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_STATIC_PAD_CTL_TX_SLEW_SHIFT 23
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_STATIC_PAD_CTL_TX_SLEW_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: STATIC_PAD_CTL :: DQS_MODE [22:22] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_STATIC_PAD_CTL_DQS_MODE_MASK 0x00400000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_STATIC_PAD_CTL_DQS_MODE_SHIFT 22
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_STATIC_PAD_CTL_DQS_MODE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: STATIC_PAD_CTL :: reserved1 [21:20] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_STATIC_PAD_CTL_reserved1_MASK 0x00300000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_STATIC_PAD_CTL_reserved1_SHIFT 20
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: STATIC_PAD_CTL :: EDC_MODE [19:18] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_STATIC_PAD_CTL_EDC_MODE_MASK 0x000c0000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_STATIC_PAD_CTL_EDC_MODE_SHIFT 18
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_STATIC_PAD_CTL_EDC_MODE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: STATIC_PAD_CTL :: reserved2 [17:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_STATIC_PAD_CTL_reserved2_MASK 0x00020000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_STATIC_PAD_CTL_reserved2_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: STATIC_PAD_CTL :: WDBI_ENABLE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_STATIC_PAD_CTL_WDBI_ENABLE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_STATIC_PAD_CTL_WDBI_ENABLE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_STATIC_PAD_CTL_WDBI_ENABLE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: STATIC_PAD_CTL :: RDBI_ENABLE [15:15] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_STATIC_PAD_CTL_RDBI_ENABLE_MASK 0x00008000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_STATIC_PAD_CTL_RDBI_ENABLE_SHIFT 15
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_STATIC_PAD_CTL_RDBI_ENABLE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: STATIC_PAD_CTL :: DM_MODE [14:14] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_STATIC_PAD_CTL_DM_MODE_MASK 0x00004000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_STATIC_PAD_CTL_DM_MODE_SHIFT 14
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_STATIC_PAD_CTL_DM_MODE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: STATIC_PAD_CTL :: reserved3 [13:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_STATIC_PAD_CTL_reserved3_MASK 0x00002000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_STATIC_PAD_CTL_reserved3_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: STATIC_PAD_CTL :: DQS_TX_PAUSE [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_STATIC_PAD_CTL_DQS_TX_PAUSE_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_STATIC_PAD_CTL_DQS_TX_PAUSE_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_STATIC_PAD_CTL_DQS_TX_PAUSE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: STATIC_PAD_CTL :: reserved_for_padding4 [11:11] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_STATIC_PAD_CTL_reserved_for_padding4_MASK 0x00000800
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_STATIC_PAD_CTL_reserved_for_padding4_SHIFT 11
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: STATIC_PAD_CTL :: DQS_TX_DIS [10:10] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_STATIC_PAD_CTL_DQS_TX_DIS_MASK 0x00000400
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_STATIC_PAD_CTL_DQS_TX_DIS_SHIFT 10
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_STATIC_PAD_CTL_DQS_TX_DIS_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: STATIC_PAD_CTL :: TX_MODE [09:04] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_STATIC_PAD_CTL_TX_MODE_MASK 0x000003f0
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_STATIC_PAD_CTL_TX_MODE_SHIFT 4
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_STATIC_PAD_CTL_TX_MODE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: STATIC_PAD_CTL :: reserved5 [03:03] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_STATIC_PAD_CTL_reserved5_MASK 0x00000008
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_STATIC_PAD_CTL_reserved5_SHIFT 3
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: STATIC_PAD_CTL :: RX_MODE [02:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_STATIC_PAD_CTL_RX_MODE_MASK 0x00000007
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_STATIC_PAD_CTL_RX_MODE_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_STATIC_PAD_CTL_RX_MODE_DEFAULT 0x00000000
-
-/***************************************************************************
- *DQ_RX_TRIM - Receiver trim for DQ
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_2_0 :: DQ_RX_TRIM :: reserved0 [31:21] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_DQ_RX_TRIM_reserved0_MASK 0xffe00000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_DQ_RX_TRIM_reserved0_SHIFT 21
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: DQ_RX_TRIM :: LSTRIM [20:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_DQ_RX_TRIM_LSTRIM_MASK 0x001e0000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_DQ_RX_TRIM_LSTRIM_SHIFT 17
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_DQ_RX_TRIM_LSTRIM_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: DQ_RX_TRIM :: ITRIM [16:14] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_DQ_RX_TRIM_ITRIM_MASK 0x0001c000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_DQ_RX_TRIM_ITRIM_SHIFT 14
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_DQ_RX_TRIM_ITRIM_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: DQ_RX_TRIM :: IDLE_LSTRIM [13:10] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_DQ_RX_TRIM_IDLE_LSTRIM_MASK 0x00003c00
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_DQ_RX_TRIM_IDLE_LSTRIM_SHIFT 10
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_DQ_RX_TRIM_IDLE_LSTRIM_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: DQ_RX_TRIM :: IDLE_ITRIM [09:07] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_DQ_RX_TRIM_IDLE_ITRIM_MASK 0x00000380
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_DQ_RX_TRIM_IDLE_ITRIM_SHIFT 7
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_DQ_RX_TRIM_IDLE_ITRIM_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: DQ_RX_TRIM :: TERM_LSTRIM [06:03] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_DQ_RX_TRIM_TERM_LSTRIM_MASK 0x00000078
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_DQ_RX_TRIM_TERM_LSTRIM_SHIFT 3
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_DQ_RX_TRIM_TERM_LSTRIM_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: DQ_RX_TRIM :: TERM_ITRIM [02:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_DQ_RX_TRIM_TERM_ITRIM_MASK 0x00000007
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_DQ_RX_TRIM_TERM_ITRIM_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_DQ_RX_TRIM_TERM_ITRIM_DEFAULT 0x00000000
-
-/***************************************************************************
- *MISC_RX_TRIM - Receiver trim for miscellaneous pins
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_2_0 :: MISC_RX_TRIM :: reserved0 [31:21] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_MISC_RX_TRIM_reserved0_MASK 0xffe00000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_MISC_RX_TRIM_reserved0_SHIFT 21
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: MISC_RX_TRIM :: LSTRIM [20:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_MISC_RX_TRIM_LSTRIM_MASK 0x001e0000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_MISC_RX_TRIM_LSTRIM_SHIFT 17
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_MISC_RX_TRIM_LSTRIM_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: MISC_RX_TRIM :: ITRIM [16:14] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_MISC_RX_TRIM_ITRIM_MASK 0x0001c000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_MISC_RX_TRIM_ITRIM_SHIFT 14
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_MISC_RX_TRIM_ITRIM_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: MISC_RX_TRIM :: IDLE_LSTRIM [13:10] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_MISC_RX_TRIM_IDLE_LSTRIM_MASK 0x00003c00
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_MISC_RX_TRIM_IDLE_LSTRIM_SHIFT 10
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_MISC_RX_TRIM_IDLE_LSTRIM_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: MISC_RX_TRIM :: IDLE_ITRIM [09:07] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_MISC_RX_TRIM_IDLE_ITRIM_MASK 0x00000380
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_MISC_RX_TRIM_IDLE_ITRIM_SHIFT 7
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_MISC_RX_TRIM_IDLE_ITRIM_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: MISC_RX_TRIM :: TERM_LSTRIM [06:03] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_MISC_RX_TRIM_TERM_LSTRIM_MASK 0x00000078
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_MISC_RX_TRIM_TERM_LSTRIM_SHIFT 3
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_MISC_RX_TRIM_TERM_LSTRIM_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: MISC_RX_TRIM :: TERM_ITRIM [02:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_MISC_RX_TRIM_TERM_ITRIM_MASK 0x00000007
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_MISC_RX_TRIM_TERM_ITRIM_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_MISC_RX_TRIM_TERM_ITRIM_DEFAULT 0x00000000
-
-/***************************************************************************
- *DQS_RX_TRIM - Rreceiver trim for DQS
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_2_0 :: DQS_RX_TRIM :: reserved0 [31:21] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_DQS_RX_TRIM_reserved0_MASK 0xffe00000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_DQS_RX_TRIM_reserved0_SHIFT 21
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: DQS_RX_TRIM :: LSTRIM [20:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_DQS_RX_TRIM_LSTRIM_MASK 0x001e0000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_DQS_RX_TRIM_LSTRIM_SHIFT 17
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_DQS_RX_TRIM_LSTRIM_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: DQS_RX_TRIM :: ITRIM [16:14] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_DQS_RX_TRIM_ITRIM_MASK 0x0001c000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_DQS_RX_TRIM_ITRIM_SHIFT 14
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_DQS_RX_TRIM_ITRIM_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: DQS_RX_TRIM :: IDLE_LSTRIM [13:10] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_DQS_RX_TRIM_IDLE_LSTRIM_MASK 0x00003c00
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_DQS_RX_TRIM_IDLE_LSTRIM_SHIFT 10
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_DQS_RX_TRIM_IDLE_LSTRIM_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: DQS_RX_TRIM :: IDLE_ITRIM [09:07] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_DQS_RX_TRIM_IDLE_ITRIM_MASK 0x00000380
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_DQS_RX_TRIM_IDLE_ITRIM_SHIFT 7
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_DQS_RX_TRIM_IDLE_ITRIM_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: DQS_RX_TRIM :: TERM_LSTRIM [06:03] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_DQS_RX_TRIM_TERM_LSTRIM_MASK 0x00000078
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_DQS_RX_TRIM_TERM_LSTRIM_SHIFT 3
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_DQS_RX_TRIM_TERM_LSTRIM_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: DQS_RX_TRIM :: TERM_ITRIM [02:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_DQS_RX_TRIM_TERM_ITRIM_MASK 0x00000007
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_DQS_RX_TRIM_TERM_ITRIM_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_DQS_RX_TRIM_TERM_ITRIM_DEFAULT 0x00000000
-
-/***************************************************************************
- *WR_PREAMBLE_MODE - Write cycle preamble control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_2_0 :: WR_PREAMBLE_MODE :: reserved0 [31:21] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_WR_PREAMBLE_MODE_reserved0_MASK 0xffe00000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_WR_PREAMBLE_MODE_reserved0_SHIFT 21
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: WR_PREAMBLE_MODE :: POSTAM_TERM_BITS [20:19] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_WR_PREAMBLE_MODE_POSTAM_TERM_BITS_MASK 0x00180000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_WR_PREAMBLE_MODE_POSTAM_TERM_BITS_SHIFT 19
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_WR_PREAMBLE_MODE_POSTAM_TERM_BITS_DEFAULT 0x00000003
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: WR_PREAMBLE_MODE :: DM_POSTAM_BITS [18:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_WR_PREAMBLE_MODE_DM_POSTAM_BITS_MASK 0x00060000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_WR_PREAMBLE_MODE_DM_POSTAM_BITS_SHIFT 17
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_WR_PREAMBLE_MODE_DM_POSTAM_BITS_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: WR_PREAMBLE_MODE :: DM_PREAM_BITS [16:14] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_WR_PREAMBLE_MODE_DM_PREAM_BITS_MASK 0x0001c000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_WR_PREAMBLE_MODE_DM_PREAM_BITS_SHIFT 14
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_WR_PREAMBLE_MODE_DM_PREAM_BITS_DEFAULT 0x00000001
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: WR_PREAMBLE_MODE :: DQ_POSTAM_BITS [13:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_WR_PREAMBLE_MODE_DQ_POSTAM_BITS_MASK 0x00003000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_WR_PREAMBLE_MODE_DQ_POSTAM_BITS_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_WR_PREAMBLE_MODE_DQ_POSTAM_BITS_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: WR_PREAMBLE_MODE :: DQ_PREAM_BITS [11:09] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_WR_PREAMBLE_MODE_DQ_PREAM_BITS_MASK 0x00000e00
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_WR_PREAMBLE_MODE_DQ_PREAM_BITS_SHIFT 9
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_WR_PREAMBLE_MODE_DQ_PREAM_BITS_DEFAULT 0x00000001
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: WR_PREAMBLE_MODE :: DQS [08:05] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_WR_PREAMBLE_MODE_DQS_MASK 0x000001e0
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_WR_PREAMBLE_MODE_DQS_SHIFT 5
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_WR_PREAMBLE_MODE_DQS_DEFAULT 0x0000000a
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: WR_PREAMBLE_MODE :: DQS_POSTAM_BITS [04:03] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_WR_PREAMBLE_MODE_DQS_POSTAM_BITS_MASK 0x00000018
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_WR_PREAMBLE_MODE_DQS_POSTAM_BITS_SHIFT 3
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_WR_PREAMBLE_MODE_DQS_POSTAM_BITS_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: WR_PREAMBLE_MODE :: DQS_PREAM_BITS [02:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_WR_PREAMBLE_MODE_DQS_PREAM_BITS_MASK 0x00000007
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_WR_PREAMBLE_MODE_DQS_PREAM_BITS_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_WR_PREAMBLE_MODE_DQS_PREAM_BITS_DEFAULT 0x00000002
-
-/***************************************************************************
- *ODT_CONTROL - Read channel ODT control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_2_0 :: ODT_CONTROL :: reserved_for_padding0 [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_ODT_CONTROL_reserved_for_padding0_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_ODT_CONTROL_reserved_for_padding0_SHIFT 31
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: ODT_CONTROL :: reserved1 [30:10] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_ODT_CONTROL_reserved1_MASK 0x7ffffc00
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_ODT_CONTROL_reserved1_SHIFT 10
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: ODT_CONTROL :: ODT_ENABLE [09:09] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_ODT_CONTROL_ODT_ENABLE_MASK 0x00000200
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_ODT_CONTROL_ODT_ENABLE_SHIFT 9
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_ODT_CONTROL_ODT_ENABLE_DEFAULT 0x00000001
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: ODT_CONTROL :: ODT_DELAY [08:06] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_ODT_CONTROL_ODT_DELAY_MASK 0x000001c0
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_ODT_CONTROL_ODT_DELAY_SHIFT 6
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_ODT_CONTROL_ODT_DELAY_DEFAULT 0x00000001
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: ODT_CONTROL :: ODT_POST_LENGTH [05:03] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_ODT_CONTROL_ODT_POST_LENGTH_MASK 0x00000038
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_ODT_CONTROL_ODT_POST_LENGTH_SHIFT 3
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_ODT_CONTROL_ODT_POST_LENGTH_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: ODT_CONTROL :: ODT_PRE_LENGTH [02:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_ODT_CONTROL_ODT_PRE_LENGTH_MASK 0x00000007
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_ODT_CONTROL_ODT_PRE_LENGTH_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_ODT_CONTROL_ODT_PRE_LENGTH_DEFAULT 0x00000003
-
-/***************************************************************************
- *LDO_CONFIG - LDO Configuration register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_2_0 :: LDO_CONFIG :: reserved0 [31:06] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_LDO_CONFIG_reserved0_MASK 0xffffffc0
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_LDO_CONFIG_reserved0_SHIFT 6
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: LDO_CONFIG :: CK_LDO_PWRDOWN [05:05] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_LDO_CONFIG_CK_LDO_PWRDOWN_MASK 0x00000020
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_LDO_CONFIG_CK_LDO_PWRDOWN_SHIFT 5
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_LDO_CONFIG_CK_LDO_PWRDOWN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: LDO_CONFIG :: CK_LDO_REF_SEL [04:04] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_LDO_CONFIG_CK_LDO_REF_SEL_MASK 0x00000010
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_LDO_CONFIG_CK_LDO_REF_SEL_SHIFT 4
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_LDO_CONFIG_CK_LDO_REF_SEL_DEFAULT 0x00000001
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: LDO_CONFIG :: CK_LDO_REF_CTRL [03:02] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_LDO_CONFIG_CK_LDO_REF_CTRL_MASK 0x0000000c
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_LDO_CONFIG_CK_LDO_REF_CTRL_SHIFT 2
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_LDO_CONFIG_CK_LDO_REF_CTRL_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: LDO_CONFIG :: CK_LDO_BIAS [01:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_LDO_CONFIG_CK_LDO_BIAS_MASK 0x00000003
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_LDO_CONFIG_CK_LDO_BIAS_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_LDO_CONFIG_CK_LDO_BIAS_DEFAULT 0x00000000
-
-/***************************************************************************
- *EDC_DPD_CONTROL - GDDR5M EDC digital phase detector control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_2_0 :: EDC_DPD_CONTROL :: reserved0 [31:22] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_DPD_CONTROL_reserved0_MASK 0xffc00000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_DPD_CONTROL_reserved0_SHIFT 22
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: EDC_DPD_CONTROL :: DQS_PHASE_OVERRIDE_VALUE [21:21] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_DPD_CONTROL_DQS_PHASE_OVERRIDE_VALUE_MASK 0x00200000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_DPD_CONTROL_DQS_PHASE_OVERRIDE_VALUE_SHIFT 21
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_DPD_CONTROL_DQS_PHASE_OVERRIDE_VALUE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: EDC_DPD_CONTROL :: DQS_PHASE_OVERRIDE_ENABLE [20:20] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_DPD_CONTROL_DQS_PHASE_OVERRIDE_ENABLE_MASK 0x00100000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_DPD_CONTROL_DQS_PHASE_OVERRIDE_ENABLE_SHIFT 20
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_DPD_CONTROL_DQS_PHASE_OVERRIDE_ENABLE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: EDC_DPD_CONTROL :: reserved1 [19:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_DPD_CONTROL_reserved1_MASK 0x000f0000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_DPD_CONTROL_reserved1_SHIFT 16
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: EDC_DPD_CONTROL :: TARGET_CS_N [15:15] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_DPD_CONTROL_TARGET_CS_N_MASK 0x00008000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_DPD_CONTROL_TARGET_CS_N_SHIFT 15
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_DPD_CONTROL_TARGET_CS_N_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: EDC_DPD_CONTROL :: UPDATE_MODE [14:14] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_DPD_CONTROL_UPDATE_MODE_MASK 0x00004000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_DPD_CONTROL_UPDATE_MODE_SHIFT 14
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_DPD_CONTROL_UPDATE_MODE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: EDC_DPD_CONTROL :: SAMPLE_MODE [13:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_DPD_CONTROL_SAMPLE_MODE_MASK 0x00003000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_DPD_CONTROL_SAMPLE_MODE_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_DPD_CONTROL_SAMPLE_MODE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: EDC_DPD_CONTROL :: reserved2 [11:09] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_DPD_CONTROL_reserved2_MASK 0x00000e00
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_DPD_CONTROL_reserved2_SHIFT 9
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: EDC_DPD_CONTROL :: MIN_LOW_SAMPLES [08:04] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_DPD_CONTROL_MIN_LOW_SAMPLES_MASK 0x000001f0
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_DPD_CONTROL_MIN_LOW_SAMPLES_SHIFT 4
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_DPD_CONTROL_MIN_LOW_SAMPLES_DEFAULT 0x00000008
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: EDC_DPD_CONTROL :: SET_ADJ_EN [03:03] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_DPD_CONTROL_SET_ADJ_EN_MASK 0x00000008
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_DPD_CONTROL_SET_ADJ_EN_SHIFT 3
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_DPD_CONTROL_SET_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: EDC_DPD_CONTROL :: UPDATE [02:02] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_DPD_CONTROL_UPDATE_MASK 0x00000004
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_DPD_CONTROL_UPDATE_SHIFT 2
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_DPD_CONTROL_UPDATE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: EDC_DPD_CONTROL :: MONITOR [01:01] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_DPD_CONTROL_MONITOR_MASK 0x00000002
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_DPD_CONTROL_MONITOR_SHIFT 1
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_DPD_CONTROL_MONITOR_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: EDC_DPD_CONTROL :: INIT [00:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_DPD_CONTROL_INIT_MASK 0x00000001
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_DPD_CONTROL_INIT_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_DPD_CONTROL_INIT_DEFAULT 0x00000000
-
-/***************************************************************************
- *EDC_DPD_STATUS - GDDR5M EDC digital phase detector status register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_2_0 :: EDC_DPD_STATUS :: reserved0 [31:29] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_DPD_STATUS_reserved0_MASK 0xe0000000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_DPD_STATUS_reserved0_SHIFT 29
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: EDC_DPD_STATUS :: CURRENT_DQS_PHASE [28:28] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_DPD_STATUS_CURRENT_DQS_PHASE_MASK 0x10000000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_DPD_STATUS_CURRENT_DQS_PHASE_SHIFT 28
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_DPD_STATUS_CURRENT_DQS_PHASE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: EDC_DPD_STATUS :: CURRENT_VDL_SETTING [27:20] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_DPD_STATUS_CURRENT_VDL_SETTING_MASK 0x0ff00000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_DPD_STATUS_CURRENT_VDL_SETTING_SHIFT 20
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_DPD_STATUS_CURRENT_VDL_SETTING_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: EDC_DPD_STATUS :: reserved1 [19:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_DPD_STATUS_reserved1_MASK 0x000e0000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_DPD_STATUS_reserved1_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: EDC_DPD_STATUS :: INIT_DQS_PHASE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_DPD_STATUS_INIT_DQS_PHASE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_DPD_STATUS_INIT_DQS_PHASE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_DPD_STATUS_INIT_DQS_PHASE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: EDC_DPD_STATUS :: INIT_VDL_SETTING [15:08] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_DPD_STATUS_INIT_VDL_SETTING_MASK 0x0000ff00
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_DPD_STATUS_INIT_VDL_SETTING_SHIFT 8
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_DPD_STATUS_INIT_VDL_SETTING_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: EDC_DPD_STATUS :: reserved2 [07:05] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_DPD_STATUS_reserved2_MASK 0x000000e0
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_DPD_STATUS_reserved2_SHIFT 5
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: EDC_DPD_STATUS :: MONITOR_ERROR [04:04] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_DPD_STATUS_MONITOR_ERROR_MASK 0x00000010
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_DPD_STATUS_MONITOR_ERROR_SHIFT 4
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_DPD_STATUS_MONITOR_ERROR_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: EDC_DPD_STATUS :: MONITOR_BUSY [03:03] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_DPD_STATUS_MONITOR_BUSY_MASK 0x00000008
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_DPD_STATUS_MONITOR_BUSY_SHIFT 3
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_DPD_STATUS_MONITOR_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: EDC_DPD_STATUS :: INIT_LOCK [02:02] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_DPD_STATUS_INIT_LOCK_MASK 0x00000004
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_DPD_STATUS_INIT_LOCK_SHIFT 2
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_DPD_STATUS_INIT_LOCK_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: EDC_DPD_STATUS :: INIT_BUSY [01:01] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_DPD_STATUS_INIT_BUSY_MASK 0x00000002
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_DPD_STATUS_INIT_BUSY_SHIFT 1
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_DPD_STATUS_INIT_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: EDC_DPD_STATUS :: INIT_DONE [00:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_DPD_STATUS_INIT_DONE_MASK 0x00000001
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_DPD_STATUS_INIT_DONE_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_DPD_STATUS_INIT_DONE_DEFAULT 0x00000000
-
-/***************************************************************************
- *EDC_DPD_OUT_CONTROL - GDDR5M EDC digital phase detector output signal control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_2_0 :: EDC_DPD_OUT_CONTROL :: reserved0 [31:20] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_DPD_OUT_CONTROL_reserved0_MASK 0xfff00000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_DPD_OUT_CONTROL_reserved0_SHIFT 20
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: EDC_DPD_OUT_CONTROL :: LOWER_LIMIT [19:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_DPD_OUT_CONTROL_LOWER_LIMIT_MASK 0x000ff000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_DPD_OUT_CONTROL_LOWER_LIMIT_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_DPD_OUT_CONTROL_LOWER_LIMIT_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: EDC_DPD_OUT_CONTROL :: UPPER_LIMIT [11:04] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_DPD_OUT_CONTROL_UPPER_LIMIT_MASK 0x00000ff0
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_DPD_OUT_CONTROL_UPPER_LIMIT_SHIFT 4
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_DPD_OUT_CONTROL_UPPER_LIMIT_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: EDC_DPD_OUT_CONTROL :: reserved1 [03:01] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_DPD_OUT_CONTROL_reserved1_MASK 0x0000000e
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_DPD_OUT_CONTROL_reserved1_SHIFT 1
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: EDC_DPD_OUT_CONTROL :: ENABLE [00:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_DPD_OUT_CONTROL_ENABLE_MASK 0x00000001
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_DPD_OUT_CONTROL_ENABLE_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_DPD_OUT_CONTROL_ENABLE_DEFAULT 0x00000000
-
-/***************************************************************************
- *EDC_DPD_OUT_STATUS - GDDR5M EDC digital phase detector output signal status register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_2_0 :: EDC_DPD_OUT_STATUS :: reserved0 [31:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_DPD_OUT_STATUS_reserved0_MASK 0xfffff000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_DPD_OUT_STATUS_reserved0_SHIFT 12
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: EDC_DPD_OUT_STATUS :: VDL_SETTING [11:04] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_DPD_OUT_STATUS_VDL_SETTING_MASK 0x00000ff0
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_DPD_OUT_STATUS_VDL_SETTING_SHIFT 4
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_DPD_OUT_STATUS_VDL_SETTING_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: EDC_DPD_OUT_STATUS :: reserved1 [03:01] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_DPD_OUT_STATUS_reserved1_MASK 0x0000000e
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_DPD_OUT_STATUS_reserved1_SHIFT 1
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: EDC_DPD_OUT_STATUS :: VALID [00:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_DPD_OUT_STATUS_VALID_MASK 0x00000001
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_DPD_OUT_STATUS_VALID_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_DPD_OUT_STATUS_VALID_DEFAULT 0x00000000
-
-/***************************************************************************
- *EDC_DPD_OUT_STATUS_CLEAR - GDDR5M EDC digital phase detector output signal status clear register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_2_0 :: EDC_DPD_OUT_STATUS_CLEAR :: reserved0 [31:01] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_DPD_OUT_STATUS_CLEAR_reserved0_MASK 0xfffffffe
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_DPD_OUT_STATUS_CLEAR_reserved0_SHIFT 1
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: EDC_DPD_OUT_STATUS_CLEAR :: CLEAR [00:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_DPD_OUT_STATUS_CLEAR_CLEAR_MASK 0x00000001
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_DPD_OUT_STATUS_CLEAR_CLEAR_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_DPD_OUT_STATUS_CLEAR_CLEAR_DEFAULT 0x00000000
-
-/***************************************************************************
- *EDC_CRC_CONTROL - GDDR5M EDC signal path CRC control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_2_0 :: EDC_CRC_CONTROL :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_CRC_CONTROL_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_CRC_CONTROL_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_CRC_CONTROL_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: EDC_CRC_CONTROL :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_CRC_CONTROL_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_CRC_CONTROL_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: EDC_CRC_CONTROL :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_CRC_CONTROL_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_CRC_CONTROL_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_CRC_CONTROL_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: EDC_CRC_CONTROL :: reserved1 [15:11] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_CRC_CONTROL_reserved1_MASK 0x0000f800
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_CRC_CONTROL_reserved1_SHIFT 11
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: EDC_CRC_CONTROL :: CRCWL [10:08] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_CRC_CONTROL_CRCWL_MASK 0x00000700
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_CRC_CONTROL_CRCWL_SHIFT 8
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_CRC_CONTROL_CRCWL_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: EDC_CRC_CONTROL :: reserved2 [07:06] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_CRC_CONTROL_reserved2_MASK 0x000000c0
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_CRC_CONTROL_reserved2_SHIFT 6
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: EDC_CRC_CONTROL :: CRCRL [05:04] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_CRC_CONTROL_CRCRL_MASK 0x00000030
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_CRC_CONTROL_CRCRL_SHIFT 4
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_CRC_CONTROL_CRCRL_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: EDC_CRC_CONTROL :: reserved3 [03:02] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_CRC_CONTROL_reserved3_MASK 0x0000000c
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_CRC_CONTROL_reserved3_SHIFT 2
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: EDC_CRC_CONTROL :: ENABLE_WR [01:01] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_CRC_CONTROL_ENABLE_WR_MASK 0x00000002
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_CRC_CONTROL_ENABLE_WR_SHIFT 1
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_CRC_CONTROL_ENABLE_WR_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: EDC_CRC_CONTROL :: ENABLE_RD [00:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_CRC_CONTROL_ENABLE_RD_MASK 0x00000001
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_CRC_CONTROL_ENABLE_RD_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_CRC_CONTROL_ENABLE_RD_DEFAULT 0x00000000
-
-/***************************************************************************
- *EDC_CRC_STATUS - GDDR5M EDC signal path CRC status register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_2_0 :: EDC_CRC_STATUS :: MISCOMPARE_EXP_CRC [31:24] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_CRC_STATUS_MISCOMPARE_EXP_CRC_MASK 0xff000000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_CRC_STATUS_MISCOMPARE_EXP_CRC_SHIFT 24
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: EDC_CRC_STATUS :: MISCOMPARE_CRC [23:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_CRC_STATUS_MISCOMPARE_CRC_MASK 0x00ff0000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_CRC_STATUS_MISCOMPARE_CRC_SHIFT 16
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: EDC_CRC_STATUS :: MOST_RECENT_CRC [15:08] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_CRC_STATUS_MOST_RECENT_CRC_MASK 0x0000ff00
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_CRC_STATUS_MOST_RECENT_CRC_SHIFT 8
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: EDC_CRC_STATUS :: reserved0 [07:05] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_CRC_STATUS_reserved0_MASK 0x000000e0
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_CRC_STATUS_reserved0_SHIFT 5
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: EDC_CRC_STATUS :: MISCOMPARE_TYPE [04:04] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_CRC_STATUS_MISCOMPARE_TYPE_MASK 0x00000010
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_CRC_STATUS_MISCOMPARE_TYPE_SHIFT 4
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: EDC_CRC_STATUS :: WR_FAIL [03:03] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_CRC_STATUS_WR_FAIL_MASK 0x00000008
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_CRC_STATUS_WR_FAIL_SHIFT 3
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: EDC_CRC_STATUS :: WR_PASS [02:02] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_CRC_STATUS_WR_PASS_MASK 0x00000004
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_CRC_STATUS_WR_PASS_SHIFT 2
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: EDC_CRC_STATUS :: RD_FAIL [01:01] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_CRC_STATUS_RD_FAIL_MASK 0x00000002
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_CRC_STATUS_RD_FAIL_SHIFT 1
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: EDC_CRC_STATUS :: RD_PASS [00:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_CRC_STATUS_RD_PASS_MASK 0x00000001
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_CRC_STATUS_RD_PASS_SHIFT 0
-
-/***************************************************************************
- *EDC_CRC_COUNT - GDDR5M EDC signal path CRC counter register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_2_0 :: EDC_CRC_COUNT :: WR_FAIL_COUNT [31:24] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_CRC_COUNT_WR_FAIL_COUNT_MASK 0xff000000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_CRC_COUNT_WR_FAIL_COUNT_SHIFT 24
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: EDC_CRC_COUNT :: WR_PASS_COUNT [23:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_CRC_COUNT_WR_PASS_COUNT_MASK 0x00ff0000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_CRC_COUNT_WR_PASS_COUNT_SHIFT 16
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: EDC_CRC_COUNT :: RD_FAIL_COUNT [15:08] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_CRC_COUNT_RD_FAIL_COUNT_MASK 0x0000ff00
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_CRC_COUNT_RD_FAIL_COUNT_SHIFT 8
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: EDC_CRC_COUNT :: RD_PASS_COUNT [07:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_CRC_COUNT_RD_PASS_COUNT_MASK 0x000000ff
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_CRC_COUNT_RD_PASS_COUNT_SHIFT 0
-
-/***************************************************************************
- *EDC_CRC_STATUS_CLEAR - GDDR5M EDC signal path CRC counter register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_2_0 :: EDC_CRC_STATUS_CLEAR :: reserved0 [31:01] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_CRC_STATUS_CLEAR_reserved0_MASK 0xfffffffe
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_CRC_STATUS_CLEAR_reserved0_SHIFT 1
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: EDC_CRC_STATUS_CLEAR :: CLEAR [00:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_CRC_STATUS_CLEAR_CLEAR_MASK 0x00000001
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_CRC_STATUS_CLEAR_CLEAR_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_CRC_STATUS_CLEAR_CLEAR_DEFAULT 0x00000000
-
-/***************************************************************************
- *CLOCK_ENABLE - Clock Enable Register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_2_0 :: CLOCK_ENABLE :: reserved0 [31:03] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_CLOCK_ENABLE_reserved0_MASK 0xfffffff8
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_CLOCK_ENABLE_reserved0_SHIFT 3
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: CLOCK_ENABLE :: TO_MC_CLOCK [02:02] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_CLOCK_ENABLE_TO_MC_CLOCK_MASK 0x00000004
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_CLOCK_ENABLE_TO_MC_CLOCK_SHIFT 2
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_CLOCK_ENABLE_TO_MC_CLOCK_DEFAULT 0x00000001
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: CLOCK_ENABLE :: FROM_MC_CLOCK [01:01] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_CLOCK_ENABLE_FROM_MC_CLOCK_MASK 0x00000002
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_CLOCK_ENABLE_FROM_MC_CLOCK_SHIFT 1
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_CLOCK_ENABLE_FROM_MC_CLOCK_DEFAULT 0x00000001
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: CLOCK_ENABLE :: BIT_CLOCK [00:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_CLOCK_ENABLE_BIT_CLOCK_MASK 0x00000001
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_CLOCK_ENABLE_BIT_CLOCK_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_CLOCK_ENABLE_BIT_CLOCK_DEFAULT 0x00000001
-
-/***************************************************************************
- *CLOCK_IDLE - Clock Idle Register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_2_0 :: CLOCK_IDLE :: reserved0 [31:03] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_CLOCK_IDLE_reserved0_MASK 0xfffffff8
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_CLOCK_IDLE_reserved0_SHIFT 3
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: CLOCK_IDLE :: TO_MC_CLOCK [02:02] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_CLOCK_IDLE_TO_MC_CLOCK_MASK 0x00000004
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_CLOCK_IDLE_TO_MC_CLOCK_SHIFT 2
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_CLOCK_IDLE_TO_MC_CLOCK_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: CLOCK_IDLE :: FROM_MC_CLOCK [01:01] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_CLOCK_IDLE_FROM_MC_CLOCK_MASK 0x00000002
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_CLOCK_IDLE_FROM_MC_CLOCK_SHIFT 1
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_CLOCK_IDLE_FROM_MC_CLOCK_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: CLOCK_IDLE :: BIT_CLOCK [00:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_CLOCK_IDLE_BIT_CLOCK_MASK 0x00000001
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_CLOCK_IDLE_BIT_CLOCK_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_CLOCK_IDLE_BIT_CLOCK_DEFAULT 0x00000000
-
-/***************************************************************************
- *BL_SPARE_REG - Byte-Lane Spare register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_2_0 :: BL_SPARE_REG :: reserved_for_eco0 [31:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_BL_SPARE_REG_reserved_for_eco0_MASK 0xffffffff
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_BL_SPARE_REG_reserved_for_eco0_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_BL_SPARE_REG_reserved_for_eco0_DEFAULT 0x00000000
-
-#endif /* #ifndef BCHP_DDR34_PHY_BYTE_LANE_2_0_H__ */
-
-/* End of File */
diff --git a/include/linux/brcmstb/7366b0/bchp_ddr34_phy_byte_lane_3_0.h b/include/linux/brcmstb/7366b0/bchp_ddr34_phy_byte_lane_3_0.h
deleted file mode 100644
index 99d7bab..0000000
--- a/include/linux/brcmstb/7366b0/bchp_ddr34_phy_byte_lane_3_0.h
+++ /dev/null
@@ -1,2482 +0,0 @@
-/***************************************************************************
- * Copyright (c) 1999-2014, Broadcom Corporation
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
- *
- * Module Description:
- * DO NOT EDIT THIS FILE DIRECTLY
- *
- * This module was generated magically with RDB from a source description
- * file. You must edit the source file for changes to be made to this file.
- *
- *
- * Date: Generated on Thu Apr 24 03:08:54 2014
- * Full Compile MD5 Checksum 1af2c2cf28828ece5496e1312aac0166
- * (minus title and desc)
- * MD5 Checksum 3203ffce85e3fc9a10f84123e54057b0
- *
- * Compiled with: RDB Utility combo_header.pl
- * RDB Parser 3.0
- * unknown unknown
- * Perl Interpreter 5.008008
- * Operating System linux
- *
- * Revision History:
- *
- * $brcm_Log: $
- *
- ***************************************************************************/
-
-#ifndef BCHP_DDR34_PHY_BYTE_LANE_3_0_H__
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_H__
-
-/***************************************************************************
- *DDR34_PHY_BYTE_LANE_3_0 - DDR34 Byte Lane #3 control registers
- ***************************************************************************/
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQS 0x00506a00 /* Write channel DQS VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ0 0x00506a04 /* Write channel DQ0 VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ1 0x00506a08 /* Write channel DQ1 VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ2 0x00506a0c /* Write channel DQ2 VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ3 0x00506a10 /* Write channel DQ3 VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ4 0x00506a14 /* Write channel DQ4 VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ5 0x00506a18 /* Write channel DQ5 VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ6 0x00506a1c /* Write channel DQ6 VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ7 0x00506a20 /* Write channel DQ7 VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DM 0x00506a24 /* Write channel DM VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_EDC 0x00506a28 /* Write channel EDC VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQSP 0x00506a2c /* Read channel DQSP VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQSN 0x00506a30 /* Read channel DQSP VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ0P 0x00506a34 /* Read channel DQ0-P VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ0N 0x00506a38 /* Read channel DQ0-N VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ1P 0x00506a3c /* Read channel DQ1-P VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ1N 0x00506a40 /* Read channel DQ1-N VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ2P 0x00506a44 /* Read channel DQ2-P VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ2N 0x00506a48 /* Read channel DQ2-N VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ3P 0x00506a4c /* Read channel DQ3-P VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ3N 0x00506a50 /* Read channel DQ3-N VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ4P 0x00506a54 /* Read channel DQ4-P VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ4N 0x00506a58 /* Read channel DQ4-N VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ5P 0x00506a5c /* Read channel DQ5-P VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ5N 0x00506a60 /* Read channel DQ5-N VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ6P 0x00506a64 /* Read channel DQ6-P VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ6N 0x00506a68 /* Read channel DQ6-N VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ7P 0x00506a6c /* Read channel DQ7-P VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ7N 0x00506a70 /* Read channel DQ7-N VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DMP 0x00506a74 /* Read channel DM-P VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DMN 0x00506a78 /* Read channel DM-N VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_EDCP 0x00506a7c /* Read channel EDC-P VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_EDCN 0x00506a80 /* Read channel EDC-N VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_EN_CS0 0x00506a84 /* Read channel CS_N[0] read enable VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_EN_CS1 0x00506a88 /* Read channel CS_N[1] read enable VDL control register (used for reads when only cs1_n is active) */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_EN_CRC 0x00506a8c /* Read channel GDDR5 CRC read enable VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CLK_CONTROL 0x00506a90 /* DDR interface signal Write Leveling CLK VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_LDE_CONTROL 0x00506a94 /* DDR interface signal Write Leveling Capture Enable VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_RD_EN_DLY_CYC 0x00506a98 /* Read enable bit-clock cycle delay control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_WR_CHAN_DLY_CYC 0x00506a9c /* Write leveling bit-clock cycle delay control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_READ_CONTROL 0x00506aa0 /* Read channel datapath control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_READ_FIFO_ADDR 0x00506aa4 /* Read fifo addresss pointer register */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_READ_FIFO_DATA 0x00506aa8 /* Read fifo data register */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_READ_FIFO_DM_DBI 0x00506aac /* Read fifo dm/dbi register */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_READ_FIFO_STATUS 0x00506ab0 /* Read fifo status register */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_READ_FIFO_CLEAR 0x00506ab4 /* Read fifo status clear register */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_IDLE_PAD_CONTROL 0x00506ab8 /* Idle mode SSTL pad control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_DRIVE_PAD_CTL 0x00506abc /* DQ, DM pad drive characteristics control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_DQSP_DRIVE_PAD_CTL 0x00506ac0 /* DQS pad P rail drive characteristics control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_DQSN_DRIVE_PAD_CTL 0x00506ac4 /* DQS pad N rail drive characteristics control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_DRIVE_PAD_CTL 0x00506ac8 /* EDC pad drive characteristics control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_RD_EN_DRIVE_PAD_CTL 0x00506acc /* RD_EN, EDC_RD_EN read enable pad drive characteristics control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_STATIC_PAD_CTL 0x00506ad0 /* pad rx and tx characteristics control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_DQ_RX_TRIM 0x00506ad4 /* Receiver trim for DQ */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_MISC_RX_TRIM 0x00506ad8 /* Receiver trim for miscellaneous pins */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_DQS_RX_TRIM 0x00506adc /* Rreceiver trim for DQS */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_WR_PREAMBLE_MODE 0x00506ae0 /* Write cycle preamble control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_ODT_CONTROL 0x00506ae4 /* Read channel ODT control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_LDO_CONFIG 0x00506ae8 /* LDO Configuration register */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_DPD_CONTROL 0x00506aec /* GDDR5M EDC digital phase detector control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_DPD_STATUS 0x00506af0 /* GDDR5M EDC digital phase detector status register */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_DPD_OUT_CONTROL 0x00506af4 /* GDDR5M EDC digital phase detector output signal control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_DPD_OUT_STATUS 0x00506af8 /* GDDR5M EDC digital phase detector output signal status register */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_DPD_OUT_STATUS_CLEAR 0x00506afc /* GDDR5M EDC digital phase detector output signal status clear register */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_CRC_CONTROL 0x00506b00 /* GDDR5M EDC signal path CRC control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_CRC_STATUS 0x00506b04 /* GDDR5M EDC signal path CRC status register */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_CRC_COUNT 0x00506b08 /* GDDR5M EDC signal path CRC counter register */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_CRC_STATUS_CLEAR 0x00506b0c /* GDDR5M EDC signal path CRC counter register */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_CLOCK_ENABLE 0x00506b10 /* Clock Enable Register */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_CLOCK_IDLE 0x00506b14 /* Clock Idle Register */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_BL_SPARE_REG 0x00506b18 /* Byte-Lane Spare register */
-
-/***************************************************************************
- *VDL_CONTROL_WR_DQS - Write channel DQS VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_WR_DQS :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQS_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQS_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQS_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_WR_DQS :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQS_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQS_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_WR_DQS :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQS_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQS_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQS_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_WR_DQS :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQS_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQS_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_WR_DQS :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQS_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQS_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQS_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_WR_DQS :: reserved2 [11:09] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQS_reserved2_MASK 0x00000e00
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQS_reserved2_SHIFT 9
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_WR_DQS :: VDL_STEP [08:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQS_VDL_STEP_MASK 0x000001ff
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQS_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQS_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_WR_DQ0 - Write channel DQ0 VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_WR_DQ0 :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ0_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ0_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ0_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_WR_DQ0 :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ0_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ0_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_WR_DQ0 :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ0_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ0_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ0_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_WR_DQ0 :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ0_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ0_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_WR_DQ0 :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ0_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ0_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ0_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_WR_DQ0 :: reserved2 [11:09] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ0_reserved2_MASK 0x00000e00
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ0_reserved2_SHIFT 9
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_WR_DQ0 :: VDL_STEP [08:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ0_VDL_STEP_MASK 0x000001ff
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ0_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ0_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_WR_DQ1 - Write channel DQ1 VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_WR_DQ1 :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ1_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ1_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ1_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_WR_DQ1 :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ1_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ1_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_WR_DQ1 :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ1_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ1_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ1_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_WR_DQ1 :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ1_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ1_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_WR_DQ1 :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ1_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ1_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ1_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_WR_DQ1 :: reserved2 [11:09] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ1_reserved2_MASK 0x00000e00
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ1_reserved2_SHIFT 9
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_WR_DQ1 :: VDL_STEP [08:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ1_VDL_STEP_MASK 0x000001ff
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ1_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ1_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_WR_DQ2 - Write channel DQ2 VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_WR_DQ2 :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ2_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ2_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ2_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_WR_DQ2 :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ2_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ2_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_WR_DQ2 :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ2_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ2_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ2_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_WR_DQ2 :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ2_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ2_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_WR_DQ2 :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ2_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ2_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ2_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_WR_DQ2 :: reserved2 [11:09] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ2_reserved2_MASK 0x00000e00
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ2_reserved2_SHIFT 9
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_WR_DQ2 :: VDL_STEP [08:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ2_VDL_STEP_MASK 0x000001ff
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ2_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ2_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_WR_DQ3 - Write channel DQ3 VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_WR_DQ3 :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ3_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ3_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ3_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_WR_DQ3 :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ3_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ3_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_WR_DQ3 :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ3_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ3_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ3_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_WR_DQ3 :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ3_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ3_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_WR_DQ3 :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ3_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ3_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ3_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_WR_DQ3 :: reserved2 [11:09] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ3_reserved2_MASK 0x00000e00
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ3_reserved2_SHIFT 9
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_WR_DQ3 :: VDL_STEP [08:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ3_VDL_STEP_MASK 0x000001ff
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ3_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ3_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_WR_DQ4 - Write channel DQ4 VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_WR_DQ4 :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ4_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ4_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ4_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_WR_DQ4 :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ4_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ4_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_WR_DQ4 :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ4_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ4_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ4_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_WR_DQ4 :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ4_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ4_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_WR_DQ4 :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ4_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ4_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ4_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_WR_DQ4 :: reserved2 [11:09] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ4_reserved2_MASK 0x00000e00
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ4_reserved2_SHIFT 9
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_WR_DQ4 :: VDL_STEP [08:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ4_VDL_STEP_MASK 0x000001ff
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ4_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ4_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_WR_DQ5 - Write channel DQ5 VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_WR_DQ5 :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ5_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ5_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ5_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_WR_DQ5 :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ5_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ5_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_WR_DQ5 :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ5_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ5_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ5_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_WR_DQ5 :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ5_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ5_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_WR_DQ5 :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ5_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ5_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ5_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_WR_DQ5 :: reserved2 [11:09] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ5_reserved2_MASK 0x00000e00
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ5_reserved2_SHIFT 9
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_WR_DQ5 :: VDL_STEP [08:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ5_VDL_STEP_MASK 0x000001ff
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ5_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ5_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_WR_DQ6 - Write channel DQ6 VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_WR_DQ6 :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ6_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ6_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ6_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_WR_DQ6 :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ6_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ6_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_WR_DQ6 :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ6_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ6_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ6_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_WR_DQ6 :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ6_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ6_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_WR_DQ6 :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ6_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ6_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ6_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_WR_DQ6 :: reserved2 [11:09] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ6_reserved2_MASK 0x00000e00
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ6_reserved2_SHIFT 9
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_WR_DQ6 :: VDL_STEP [08:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ6_VDL_STEP_MASK 0x000001ff
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ6_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ6_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_WR_DQ7 - Write channel DQ7 VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_WR_DQ7 :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ7_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ7_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ7_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_WR_DQ7 :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ7_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ7_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_WR_DQ7 :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ7_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ7_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ7_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_WR_DQ7 :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ7_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ7_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_WR_DQ7 :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ7_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ7_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ7_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_WR_DQ7 :: reserved2 [11:09] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ7_reserved2_MASK 0x00000e00
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ7_reserved2_SHIFT 9
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_WR_DQ7 :: VDL_STEP [08:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ7_VDL_STEP_MASK 0x000001ff
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ7_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ7_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_WR_DM - Write channel DM VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_WR_DM :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DM_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DM_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DM_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_WR_DM :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DM_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DM_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_WR_DM :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DM_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DM_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DM_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_WR_DM :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DM_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DM_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_WR_DM :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DM_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DM_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DM_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_WR_DM :: reserved2 [11:09] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DM_reserved2_MASK 0x00000e00
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DM_reserved2_SHIFT 9
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_WR_DM :: VDL_STEP [08:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DM_VDL_STEP_MASK 0x000001ff
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DM_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DM_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_WR_EDC - Write channel EDC VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_WR_EDC :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_EDC_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_EDC_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_EDC_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_WR_EDC :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_EDC_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_EDC_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_WR_EDC :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_EDC_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_EDC_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_EDC_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_WR_EDC :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_EDC_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_EDC_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_WR_EDC :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_EDC_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_EDC_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_EDC_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_WR_EDC :: reserved2 [11:09] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_EDC_reserved2_MASK 0x00000e00
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_EDC_reserved2_SHIFT 9
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_WR_EDC :: VDL_STEP [08:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_EDC_VDL_STEP_MASK 0x000001ff
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_EDC_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_EDC_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_RD_DQSP - Read channel DQSP VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_DQSP :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQSP_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQSP_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQSP_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_DQSP :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQSP_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQSP_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_DQSP :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQSP_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQSP_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQSP_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_DQSP :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQSP_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQSP_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_DQSP :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQSP_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQSP_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQSP_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_DQSP :: reserved2 [11:08] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQSP_reserved2_MASK 0x00000f00
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQSP_reserved2_SHIFT 8
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_DQSP :: VDL_STEP [07:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQSP_VDL_STEP_MASK 0x000000ff
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQSP_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQSP_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_RD_DQSN - Read channel DQSP VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_DQSN :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQSN_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQSN_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQSN_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_DQSN :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQSN_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQSN_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_DQSN :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQSN_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQSN_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQSN_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_DQSN :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQSN_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQSN_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_DQSN :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQSN_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQSN_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQSN_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_DQSN :: reserved2 [11:08] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQSN_reserved2_MASK 0x00000f00
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQSN_reserved2_SHIFT 8
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_DQSN :: VDL_STEP [07:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQSN_VDL_STEP_MASK 0x000000ff
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQSN_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQSN_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_RD_DQ0P - Read channel DQ0-P VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_DQ0P :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ0P_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ0P_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ0P_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_DQ0P :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ0P_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ0P_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_DQ0P :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ0P_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ0P_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ0P_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_DQ0P :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ0P_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ0P_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_DQ0P :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ0P_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ0P_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ0P_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_DQ0P :: reserved2 [11:08] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ0P_reserved2_MASK 0x00000f00
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ0P_reserved2_SHIFT 8
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_DQ0P :: VDL_STEP [07:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ0P_VDL_STEP_MASK 0x000000ff
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ0P_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ0P_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_RD_DQ0N - Read channel DQ0-N VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_DQ0N :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ0N_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ0N_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ0N_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_DQ0N :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ0N_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ0N_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_DQ0N :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ0N_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ0N_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ0N_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_DQ0N :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ0N_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ0N_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_DQ0N :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ0N_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ0N_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ0N_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_DQ0N :: reserved2 [11:08] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ0N_reserved2_MASK 0x00000f00
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ0N_reserved2_SHIFT 8
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_DQ0N :: VDL_STEP [07:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ0N_VDL_STEP_MASK 0x000000ff
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ0N_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ0N_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_RD_DQ1P - Read channel DQ1-P VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_DQ1P :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ1P_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ1P_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ1P_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_DQ1P :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ1P_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ1P_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_DQ1P :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ1P_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ1P_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ1P_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_DQ1P :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ1P_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ1P_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_DQ1P :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ1P_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ1P_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ1P_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_DQ1P :: reserved2 [11:08] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ1P_reserved2_MASK 0x00000f00
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ1P_reserved2_SHIFT 8
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_DQ1P :: VDL_STEP [07:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ1P_VDL_STEP_MASK 0x000000ff
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ1P_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ1P_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_RD_DQ1N - Read channel DQ1-N VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_DQ1N :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ1N_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ1N_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ1N_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_DQ1N :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ1N_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ1N_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_DQ1N :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ1N_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ1N_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ1N_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_DQ1N :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ1N_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ1N_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_DQ1N :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ1N_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ1N_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ1N_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_DQ1N :: reserved2 [11:08] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ1N_reserved2_MASK 0x00000f00
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ1N_reserved2_SHIFT 8
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_DQ1N :: VDL_STEP [07:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ1N_VDL_STEP_MASK 0x000000ff
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ1N_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ1N_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_RD_DQ2P - Read channel DQ2-P VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_DQ2P :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ2P_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ2P_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ2P_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_DQ2P :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ2P_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ2P_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_DQ2P :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ2P_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ2P_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ2P_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_DQ2P :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ2P_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ2P_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_DQ2P :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ2P_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ2P_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ2P_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_DQ2P :: reserved2 [11:08] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ2P_reserved2_MASK 0x00000f00
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ2P_reserved2_SHIFT 8
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_DQ2P :: VDL_STEP [07:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ2P_VDL_STEP_MASK 0x000000ff
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ2P_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ2P_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_RD_DQ2N - Read channel DQ2-N VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_DQ2N :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ2N_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ2N_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ2N_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_DQ2N :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ2N_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ2N_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_DQ2N :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ2N_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ2N_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ2N_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_DQ2N :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ2N_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ2N_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_DQ2N :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ2N_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ2N_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ2N_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_DQ2N :: reserved2 [11:08] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ2N_reserved2_MASK 0x00000f00
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ2N_reserved2_SHIFT 8
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_DQ2N :: VDL_STEP [07:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ2N_VDL_STEP_MASK 0x000000ff
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ2N_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ2N_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_RD_DQ3P - Read channel DQ3-P VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_DQ3P :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ3P_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ3P_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ3P_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_DQ3P :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ3P_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ3P_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_DQ3P :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ3P_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ3P_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ3P_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_DQ3P :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ3P_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ3P_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_DQ3P :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ3P_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ3P_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ3P_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_DQ3P :: reserved2 [11:08] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ3P_reserved2_MASK 0x00000f00
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ3P_reserved2_SHIFT 8
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_DQ3P :: VDL_STEP [07:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ3P_VDL_STEP_MASK 0x000000ff
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ3P_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ3P_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_RD_DQ3N - Read channel DQ3-N VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_DQ3N :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ3N_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ3N_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ3N_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_DQ3N :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ3N_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ3N_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_DQ3N :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ3N_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ3N_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ3N_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_DQ3N :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ3N_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ3N_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_DQ3N :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ3N_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ3N_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ3N_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_DQ3N :: reserved2 [11:08] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ3N_reserved2_MASK 0x00000f00
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ3N_reserved2_SHIFT 8
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_DQ3N :: VDL_STEP [07:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ3N_VDL_STEP_MASK 0x000000ff
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ3N_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ3N_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_RD_DQ4P - Read channel DQ4-P VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_DQ4P :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ4P_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ4P_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ4P_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_DQ4P :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ4P_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ4P_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_DQ4P :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ4P_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ4P_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ4P_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_DQ4P :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ4P_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ4P_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_DQ4P :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ4P_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ4P_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ4P_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_DQ4P :: reserved2 [11:08] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ4P_reserved2_MASK 0x00000f00
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ4P_reserved2_SHIFT 8
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_DQ4P :: VDL_STEP [07:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ4P_VDL_STEP_MASK 0x000000ff
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ4P_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ4P_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_RD_DQ4N - Read channel DQ4-N VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_DQ4N :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ4N_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ4N_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ4N_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_DQ4N :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ4N_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ4N_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_DQ4N :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ4N_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ4N_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ4N_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_DQ4N :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ4N_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ4N_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_DQ4N :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ4N_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ4N_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ4N_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_DQ4N :: reserved2 [11:08] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ4N_reserved2_MASK 0x00000f00
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ4N_reserved2_SHIFT 8
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_DQ4N :: VDL_STEP [07:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ4N_VDL_STEP_MASK 0x000000ff
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ4N_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ4N_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_RD_DQ5P - Read channel DQ5-P VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_DQ5P :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ5P_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ5P_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ5P_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_DQ5P :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ5P_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ5P_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_DQ5P :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ5P_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ5P_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ5P_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_DQ5P :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ5P_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ5P_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_DQ5P :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ5P_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ5P_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ5P_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_DQ5P :: reserved2 [11:08] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ5P_reserved2_MASK 0x00000f00
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ5P_reserved2_SHIFT 8
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_DQ5P :: VDL_STEP [07:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ5P_VDL_STEP_MASK 0x000000ff
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ5P_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ5P_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_RD_DQ5N - Read channel DQ5-N VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_DQ5N :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ5N_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ5N_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ5N_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_DQ5N :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ5N_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ5N_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_DQ5N :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ5N_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ5N_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ5N_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_DQ5N :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ5N_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ5N_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_DQ5N :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ5N_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ5N_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ5N_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_DQ5N :: reserved2 [11:08] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ5N_reserved2_MASK 0x00000f00
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ5N_reserved2_SHIFT 8
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_DQ5N :: VDL_STEP [07:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ5N_VDL_STEP_MASK 0x000000ff
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ5N_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ5N_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_RD_DQ6P - Read channel DQ6-P VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_DQ6P :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ6P_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ6P_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ6P_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_DQ6P :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ6P_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ6P_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_DQ6P :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ6P_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ6P_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ6P_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_DQ6P :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ6P_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ6P_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_DQ6P :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ6P_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ6P_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ6P_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_DQ6P :: reserved2 [11:08] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ6P_reserved2_MASK 0x00000f00
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ6P_reserved2_SHIFT 8
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_DQ6P :: VDL_STEP [07:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ6P_VDL_STEP_MASK 0x000000ff
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ6P_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ6P_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_RD_DQ6N - Read channel DQ6-N VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_DQ6N :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ6N_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ6N_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ6N_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_DQ6N :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ6N_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ6N_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_DQ6N :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ6N_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ6N_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ6N_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_DQ6N :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ6N_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ6N_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_DQ6N :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ6N_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ6N_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ6N_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_DQ6N :: reserved2 [11:08] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ6N_reserved2_MASK 0x00000f00
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ6N_reserved2_SHIFT 8
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_DQ6N :: VDL_STEP [07:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ6N_VDL_STEP_MASK 0x000000ff
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ6N_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ6N_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_RD_DQ7P - Read channel DQ7-P VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_DQ7P :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ7P_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ7P_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ7P_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_DQ7P :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ7P_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ7P_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_DQ7P :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ7P_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ7P_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ7P_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_DQ7P :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ7P_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ7P_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_DQ7P :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ7P_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ7P_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ7P_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_DQ7P :: reserved2 [11:08] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ7P_reserved2_MASK 0x00000f00
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ7P_reserved2_SHIFT 8
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_DQ7P :: VDL_STEP [07:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ7P_VDL_STEP_MASK 0x000000ff
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ7P_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ7P_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_RD_DQ7N - Read channel DQ7-N VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_DQ7N :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ7N_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ7N_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ7N_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_DQ7N :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ7N_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ7N_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_DQ7N :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ7N_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ7N_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ7N_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_DQ7N :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ7N_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ7N_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_DQ7N :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ7N_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ7N_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ7N_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_DQ7N :: reserved2 [11:08] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ7N_reserved2_MASK 0x00000f00
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ7N_reserved2_SHIFT 8
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_DQ7N :: VDL_STEP [07:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ7N_VDL_STEP_MASK 0x000000ff
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ7N_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ7N_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_RD_DMP - Read channel DM-P VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_DMP :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DMP_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DMP_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DMP_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_DMP :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DMP_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DMP_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_DMP :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DMP_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DMP_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DMP_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_DMP :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DMP_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DMP_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_DMP :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DMP_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DMP_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DMP_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_DMP :: reserved2 [11:08] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DMP_reserved2_MASK 0x00000f00
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DMP_reserved2_SHIFT 8
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_DMP :: VDL_STEP [07:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DMP_VDL_STEP_MASK 0x000000ff
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DMP_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DMP_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_RD_DMN - Read channel DM-N VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_DMN :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DMN_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DMN_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DMN_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_DMN :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DMN_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DMN_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_DMN :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DMN_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DMN_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DMN_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_DMN :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DMN_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DMN_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_DMN :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DMN_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DMN_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DMN_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_DMN :: reserved2 [11:08] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DMN_reserved2_MASK 0x00000f00
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DMN_reserved2_SHIFT 8
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_DMN :: VDL_STEP [07:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DMN_VDL_STEP_MASK 0x000000ff
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DMN_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DMN_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_RD_EDCP - Read channel EDC-P VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_EDCP :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_EDCP_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_EDCP_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_EDCP_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_EDCP :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_EDCP_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_EDCP_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_EDCP :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_EDCP_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_EDCP_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_EDCP_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_EDCP :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_EDCP_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_EDCP_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_EDCP :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_EDCP_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_EDCP_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_EDCP_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_EDCP :: reserved2 [11:08] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_EDCP_reserved2_MASK 0x00000f00
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_EDCP_reserved2_SHIFT 8
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_EDCP :: VDL_STEP [07:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_EDCP_VDL_STEP_MASK 0x000000ff
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_EDCP_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_EDCP_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_RD_EDCN - Read channel EDC-N VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_EDCN :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_EDCN_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_EDCN_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_EDCN_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_EDCN :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_EDCN_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_EDCN_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_EDCN :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_EDCN_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_EDCN_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_EDCN_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_EDCN :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_EDCN_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_EDCN_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_EDCN :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_EDCN_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_EDCN_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_EDCN_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_EDCN :: reserved2 [11:08] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_EDCN_reserved2_MASK 0x00000f00
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_EDCN_reserved2_SHIFT 8
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_EDCN :: VDL_STEP [07:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_EDCN_VDL_STEP_MASK 0x000000ff
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_EDCN_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_EDCN_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_RD_EN_CS0 - Read channel CS_N[0] read enable VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_EN_CS0 :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_EN_CS0_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_EN_CS0_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_EN_CS0_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_EN_CS0 :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_EN_CS0_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_EN_CS0_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_EN_CS0 :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_EN_CS0_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_EN_CS0_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_EN_CS0_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_EN_CS0 :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_EN_CS0_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_EN_CS0_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_EN_CS0 :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_EN_CS0_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_EN_CS0_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_EN_CS0_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_EN_CS0 :: reserved2 [11:08] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_EN_CS0_reserved2_MASK 0x00000f00
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_EN_CS0_reserved2_SHIFT 8
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_EN_CS0 :: VDL_STEP [07:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_EN_CS0_VDL_STEP_MASK 0x000000ff
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_EN_CS0_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_EN_CS0_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_RD_EN_CS1 - Read channel CS_N[1] read enable VDL control register (used for reads when only cs1_n is active)
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_EN_CS1 :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_EN_CS1_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_EN_CS1_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_EN_CS1_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_EN_CS1 :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_EN_CS1_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_EN_CS1_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_EN_CS1 :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_EN_CS1_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_EN_CS1_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_EN_CS1_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_EN_CS1 :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_EN_CS1_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_EN_CS1_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_EN_CS1 :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_EN_CS1_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_EN_CS1_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_EN_CS1_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_EN_CS1 :: reserved2 [11:08] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_EN_CS1_reserved2_MASK 0x00000f00
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_EN_CS1_reserved2_SHIFT 8
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_EN_CS1 :: VDL_STEP [07:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_EN_CS1_VDL_STEP_MASK 0x000000ff
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_EN_CS1_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_EN_CS1_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_RD_EN_CRC - Read channel GDDR5 CRC read enable VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_EN_CRC :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_EN_CRC_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_EN_CRC_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_EN_CRC_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_EN_CRC :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_EN_CRC_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_EN_CRC_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_EN_CRC :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_EN_CRC_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_EN_CRC_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_EN_CRC_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_EN_CRC :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_EN_CRC_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_EN_CRC_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_EN_CRC :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_EN_CRC_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_EN_CRC_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_EN_CRC_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_EN_CRC :: reserved2 [11:08] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_EN_CRC_reserved2_MASK 0x00000f00
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_EN_CRC_reserved2_SHIFT 8
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_EN_CRC :: VDL_STEP [07:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_EN_CRC_VDL_STEP_MASK 0x000000ff
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_EN_CRC_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_EN_CRC_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CLK_CONTROL - DDR interface signal Write Leveling CLK VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CLK_CONTROL :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CLK_CONTROL_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CLK_CONTROL_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CLK_CONTROL_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CLK_CONTROL :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CLK_CONTROL_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CLK_CONTROL_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CLK_CONTROL :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CLK_CONTROL_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CLK_CONTROL_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CLK_CONTROL_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CLK_CONTROL :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CLK_CONTROL_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CLK_CONTROL_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CLK_CONTROL :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CLK_CONTROL_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CLK_CONTROL_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CLK_CONTROL_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CLK_CONTROL :: reserved2 [11:09] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CLK_CONTROL_reserved2_MASK 0x00000e00
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CLK_CONTROL_reserved2_SHIFT 9
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CLK_CONTROL :: VDL_STEP [08:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CLK_CONTROL_VDL_STEP_MASK 0x000001ff
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CLK_CONTROL_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CLK_CONTROL_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_LDE_CONTROL - DDR interface signal Write Leveling Capture Enable VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_LDE_CONTROL :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_LDE_CONTROL_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_LDE_CONTROL_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_LDE_CONTROL_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_LDE_CONTROL :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_LDE_CONTROL_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_LDE_CONTROL_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_LDE_CONTROL :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_LDE_CONTROL_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_LDE_CONTROL_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_LDE_CONTROL_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_LDE_CONTROL :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_LDE_CONTROL_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_LDE_CONTROL_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_LDE_CONTROL :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_LDE_CONTROL_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_LDE_CONTROL_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_LDE_CONTROL_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_LDE_CONTROL :: reserved2 [11:09] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_LDE_CONTROL_reserved2_MASK 0x00000e00
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_LDE_CONTROL_reserved2_SHIFT 9
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_LDE_CONTROL :: VDL_STEP [08:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_LDE_CONTROL_VDL_STEP_MASK 0x000001ff
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_LDE_CONTROL_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_LDE_CONTROL_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *RD_EN_DLY_CYC - Read enable bit-clock cycle delay control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_3_0 :: RD_EN_DLY_CYC :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_RD_EN_DLY_CYC_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_RD_EN_DLY_CYC_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_RD_EN_DLY_CYC_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: RD_EN_DLY_CYC :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_RD_EN_DLY_CYC_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_RD_EN_DLY_CYC_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: RD_EN_DLY_CYC :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_RD_EN_DLY_CYC_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_RD_EN_DLY_CYC_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_RD_EN_DLY_CYC_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: RD_EN_DLY_CYC :: reserved1 [15:14] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_RD_EN_DLY_CYC_reserved1_MASK 0x0000c000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_RD_EN_DLY_CYC_reserved1_SHIFT 14
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: RD_EN_DLY_CYC :: CRC_CYCLES [13:10] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_RD_EN_DLY_CYC_CRC_CYCLES_MASK 0x00003c00
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_RD_EN_DLY_CYC_CRC_CYCLES_SHIFT 10
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_RD_EN_DLY_CYC_CRC_CYCLES_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: RD_EN_DLY_CYC :: reserved2 [09:09] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_RD_EN_DLY_CYC_reserved2_MASK 0x00000200
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_RD_EN_DLY_CYC_reserved2_SHIFT 9
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: RD_EN_DLY_CYC :: ENABLE_CS1 [08:08] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_RD_EN_DLY_CYC_ENABLE_CS1_MASK 0x00000100
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_RD_EN_DLY_CYC_ENABLE_CS1_SHIFT 8
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_RD_EN_DLY_CYC_ENABLE_CS1_DEFAULT 0x00000001
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: RD_EN_DLY_CYC :: CS1_CYCLES [07:04] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_RD_EN_DLY_CYC_CS1_CYCLES_MASK 0x000000f0
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_RD_EN_DLY_CYC_CS1_CYCLES_SHIFT 4
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_RD_EN_DLY_CYC_CS1_CYCLES_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: RD_EN_DLY_CYC :: CS0_CYCLES [03:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_RD_EN_DLY_CYC_CS0_CYCLES_MASK 0x0000000f
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_RD_EN_DLY_CYC_CS0_CYCLES_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_RD_EN_DLY_CYC_CS0_CYCLES_DEFAULT 0x00000000
-
-/***************************************************************************
- *WR_CHAN_DLY_CYC - Write leveling bit-clock cycle delay control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_3_0 :: WR_CHAN_DLY_CYC :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_WR_CHAN_DLY_CYC_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_WR_CHAN_DLY_CYC_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_WR_CHAN_DLY_CYC_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: WR_CHAN_DLY_CYC :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_WR_CHAN_DLY_CYC_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_WR_CHAN_DLY_CYC_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: WR_CHAN_DLY_CYC :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_WR_CHAN_DLY_CYC_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_WR_CHAN_DLY_CYC_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_WR_CHAN_DLY_CYC_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: WR_CHAN_DLY_CYC :: reserved1 [15:08] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_WR_CHAN_DLY_CYC_reserved1_MASK 0x0000ff00
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_WR_CHAN_DLY_CYC_reserved1_SHIFT 8
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: WR_CHAN_DLY_CYC :: DQ_CYCLES [07:04] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_WR_CHAN_DLY_CYC_DQ_CYCLES_MASK 0x000000f0
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_WR_CHAN_DLY_CYC_DQ_CYCLES_SHIFT 4
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_WR_CHAN_DLY_CYC_DQ_CYCLES_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: WR_CHAN_DLY_CYC :: reserved2 [03:03] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_WR_CHAN_DLY_CYC_reserved2_MASK 0x00000008
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_WR_CHAN_DLY_CYC_reserved2_SHIFT 3
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: WR_CHAN_DLY_CYC :: CYCLES [02:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_WR_CHAN_DLY_CYC_CYCLES_MASK 0x00000007
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_WR_CHAN_DLY_CYC_CYCLES_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_WR_CHAN_DLY_CYC_CYCLES_DEFAULT 0x00000000
-
-/***************************************************************************
- *READ_CONTROL - Read channel datapath control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_3_0 :: READ_CONTROL :: reserved0 [31:05] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_READ_CONTROL_reserved0_MASK 0xffffffe0
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_READ_CONTROL_reserved0_SHIFT 5
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: READ_CONTROL :: MODE [04:04] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_READ_CONTROL_MODE_MASK 0x00000010
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_READ_CONTROL_MODE_SHIFT 4
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_READ_CONTROL_MODE_DEFAULT 0x00000001
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: READ_CONTROL :: RD_EN_MODE [03:03] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_READ_CONTROL_RD_EN_MODE_MASK 0x00000008
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_READ_CONTROL_RD_EN_MODE_SHIFT 3
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_READ_CONTROL_RD_EN_MODE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: READ_CONTROL :: RD_DATA_DLY [02:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_READ_CONTROL_RD_DATA_DLY_MASK 0x00000007
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_READ_CONTROL_RD_DATA_DLY_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_READ_CONTROL_RD_DATA_DLY_DEFAULT 0x00000007
-
-/***************************************************************************
- *READ_FIFO_ADDR - Read fifo addresss pointer register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_3_0 :: READ_FIFO_ADDR :: reserved0 [31:03] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_READ_FIFO_ADDR_reserved0_MASK 0xfffffff8
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_READ_FIFO_ADDR_reserved0_SHIFT 3
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: READ_FIFO_ADDR :: ADDR [02:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_READ_FIFO_ADDR_ADDR_MASK 0x00000007
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_READ_FIFO_ADDR_ADDR_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_READ_FIFO_ADDR_ADDR_DEFAULT 0x00000000
-
-/***************************************************************************
- *READ_FIFO_DATA - Read fifo data register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_3_0 :: READ_FIFO_DATA :: DATA [31:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_READ_FIFO_DATA_DATA_MASK 0xffffffff
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_READ_FIFO_DATA_DATA_SHIFT 0
-
-/***************************************************************************
- *READ_FIFO_DM_DBI - Read fifo dm/dbi register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_3_0 :: READ_FIFO_DM_DBI :: reserved0 [31:04] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_READ_FIFO_DM_DBI_reserved0_MASK 0xfffffff0
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_READ_FIFO_DM_DBI_reserved0_SHIFT 4
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: READ_FIFO_DM_DBI :: DM_DBI [03:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_READ_FIFO_DM_DBI_DM_DBI_MASK 0x0000000f
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_READ_FIFO_DM_DBI_DM_DBI_SHIFT 0
-
-/***************************************************************************
- *READ_FIFO_STATUS - Read fifo status register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_3_0 :: READ_FIFO_STATUS :: reserved0 [31:02] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_READ_FIFO_STATUS_reserved0_MASK 0xfffffffc
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_READ_FIFO_STATUS_reserved0_SHIFT 2
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: READ_FIFO_STATUS :: OVERFLOW [01:01] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_READ_FIFO_STATUS_OVERFLOW_MASK 0x00000002
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_READ_FIFO_STATUS_OVERFLOW_SHIFT 1
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_READ_FIFO_STATUS_OVERFLOW_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: READ_FIFO_STATUS :: UNDERFLOW [00:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_READ_FIFO_STATUS_UNDERFLOW_MASK 0x00000001
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_READ_FIFO_STATUS_UNDERFLOW_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_READ_FIFO_STATUS_UNDERFLOW_DEFAULT 0x00000000
-
-/***************************************************************************
- *READ_FIFO_CLEAR - Read fifo status clear register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_3_0 :: READ_FIFO_CLEAR :: reserved0 [31:01] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_READ_FIFO_CLEAR_reserved0_MASK 0xfffffffe
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_READ_FIFO_CLEAR_reserved0_SHIFT 1
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: READ_FIFO_CLEAR :: CLEAR [00:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_READ_FIFO_CLEAR_CLEAR_MASK 0x00000001
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_READ_FIFO_CLEAR_CLEAR_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_READ_FIFO_CLEAR_CLEAR_DEFAULT 0x00000000
-
-/***************************************************************************
- *IDLE_PAD_CONTROL - Idle mode SSTL pad control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_3_0 :: IDLE_PAD_CONTROL :: IDLE [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_IDLE_PAD_CONTROL_IDLE_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_IDLE_PAD_CONTROL_IDLE_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_IDLE_PAD_CONTROL_IDLE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: IDLE_PAD_CONTROL :: reserved0 [30:20] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_IDLE_PAD_CONTROL_reserved0_MASK 0x7ff00000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_IDLE_PAD_CONTROL_reserved0_SHIFT 20
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: IDLE_PAD_CONTROL :: AUTO_DQ_RXENB_MODE [19:18] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_IDLE_PAD_CONTROL_AUTO_DQ_RXENB_MODE_MASK 0x000c0000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_IDLE_PAD_CONTROL_AUTO_DQ_RXENB_MODE_SHIFT 18
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_IDLE_PAD_CONTROL_AUTO_DQ_RXENB_MODE_DEFAULT 0x00000003
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: IDLE_PAD_CONTROL :: AUTO_DQ_IDDQ_MODE [17:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_IDLE_PAD_CONTROL_AUTO_DQ_IDDQ_MODE_MASK 0x00030000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_IDLE_PAD_CONTROL_AUTO_DQ_IDDQ_MODE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_IDLE_PAD_CONTROL_AUTO_DQ_IDDQ_MODE_DEFAULT 0x00000003
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: IDLE_PAD_CONTROL :: IO_IDLE_ENABLE [15:04] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_IDLE_PAD_CONTROL_IO_IDLE_ENABLE_MASK 0x0000fff0
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_IDLE_PAD_CONTROL_IO_IDLE_ENABLE_SHIFT 4
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_IDLE_PAD_CONTROL_IO_IDLE_ENABLE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: IDLE_PAD_CONTROL :: RXENB [03:03] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_IDLE_PAD_CONTROL_RXENB_MASK 0x00000008
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_IDLE_PAD_CONTROL_RXENB_SHIFT 3
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_IDLE_PAD_CONTROL_RXENB_DEFAULT 0x00000001
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: IDLE_PAD_CONTROL :: IDDQ [02:02] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_IDLE_PAD_CONTROL_IDDQ_MASK 0x00000004
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_IDLE_PAD_CONTROL_IDDQ_SHIFT 2
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_IDLE_PAD_CONTROL_IDDQ_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: IDLE_PAD_CONTROL :: DOUT_N [01:01] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_IDLE_PAD_CONTROL_DOUT_N_MASK 0x00000002
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_IDLE_PAD_CONTROL_DOUT_N_SHIFT 1
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_IDLE_PAD_CONTROL_DOUT_N_DEFAULT 0x00000001
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: IDLE_PAD_CONTROL :: DOUT_P [00:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_IDLE_PAD_CONTROL_DOUT_P_MASK 0x00000001
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_IDLE_PAD_CONTROL_DOUT_P_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_IDLE_PAD_CONTROL_DOUT_P_DEFAULT 0x00000000
-
-/***************************************************************************
- *DRIVE_PAD_CTL - DQ, DM pad drive characteristics control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_3_0 :: DRIVE_PAD_CTL :: reserved0 [31:30] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_DRIVE_PAD_CTL_reserved0_MASK 0xc0000000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_DRIVE_PAD_CTL_reserved0_SHIFT 30
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: DRIVE_PAD_CTL :: BL_PD_IDLE_STRENGTH [29:25] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_DRIVE_PAD_CTL_BL_PD_IDLE_STRENGTH_MASK 0x3e000000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_DRIVE_PAD_CTL_BL_PD_IDLE_STRENGTH_SHIFT 25
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_DRIVE_PAD_CTL_BL_PD_IDLE_STRENGTH_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: DRIVE_PAD_CTL :: BL_ND_IDLE_STRENGTH [24:20] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_DRIVE_PAD_CTL_BL_ND_IDLE_STRENGTH_MASK 0x01f00000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_DRIVE_PAD_CTL_BL_ND_IDLE_STRENGTH_SHIFT 20
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_DRIVE_PAD_CTL_BL_ND_IDLE_STRENGTH_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: DRIVE_PAD_CTL :: BL_PD_TERM_STRENGTH [19:15] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_DRIVE_PAD_CTL_BL_PD_TERM_STRENGTH_MASK 0x000f8000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_DRIVE_PAD_CTL_BL_PD_TERM_STRENGTH_SHIFT 15
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_DRIVE_PAD_CTL_BL_PD_TERM_STRENGTH_DEFAULT 0x00000008
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: DRIVE_PAD_CTL :: BL_ND_TERM_STRENGTH [14:10] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_DRIVE_PAD_CTL_BL_ND_TERM_STRENGTH_MASK 0x00007c00
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_DRIVE_PAD_CTL_BL_ND_TERM_STRENGTH_SHIFT 10
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_DRIVE_PAD_CTL_BL_ND_TERM_STRENGTH_DEFAULT 0x00000008
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: DRIVE_PAD_CTL :: BL_PD_STRENGTH [09:05] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_DRIVE_PAD_CTL_BL_PD_STRENGTH_MASK 0x000003e0
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_DRIVE_PAD_CTL_BL_PD_STRENGTH_SHIFT 5
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_DRIVE_PAD_CTL_BL_PD_STRENGTH_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: DRIVE_PAD_CTL :: BL_ND_STRENGTH [04:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_DRIVE_PAD_CTL_BL_ND_STRENGTH_MASK 0x0000001f
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_DRIVE_PAD_CTL_BL_ND_STRENGTH_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_DRIVE_PAD_CTL_BL_ND_STRENGTH_DEFAULT 0x00000000
-
-/***************************************************************************
- *DQSP_DRIVE_PAD_CTL - DQS pad P rail drive characteristics control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_3_0 :: DQSP_DRIVE_PAD_CTL :: reserved0 [31:30] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_DQSP_DRIVE_PAD_CTL_reserved0_MASK 0xc0000000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_DQSP_DRIVE_PAD_CTL_reserved0_SHIFT 30
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: DQSP_DRIVE_PAD_CTL :: BL_PD_IDLE_STRENGTH [29:25] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_DQSP_DRIVE_PAD_CTL_BL_PD_IDLE_STRENGTH_MASK 0x3e000000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_DQSP_DRIVE_PAD_CTL_BL_PD_IDLE_STRENGTH_SHIFT 25
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_DQSP_DRIVE_PAD_CTL_BL_PD_IDLE_STRENGTH_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: DQSP_DRIVE_PAD_CTL :: BL_ND_IDLE_STRENGTH [24:20] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_DQSP_DRIVE_PAD_CTL_BL_ND_IDLE_STRENGTH_MASK 0x01f00000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_DQSP_DRIVE_PAD_CTL_BL_ND_IDLE_STRENGTH_SHIFT 20
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_DQSP_DRIVE_PAD_CTL_BL_ND_IDLE_STRENGTH_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: DQSP_DRIVE_PAD_CTL :: BL_PD_TERM_STRENGTH [19:15] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_DQSP_DRIVE_PAD_CTL_BL_PD_TERM_STRENGTH_MASK 0x000f8000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_DQSP_DRIVE_PAD_CTL_BL_PD_TERM_STRENGTH_SHIFT 15
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_DQSP_DRIVE_PAD_CTL_BL_PD_TERM_STRENGTH_DEFAULT 0x00000008
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: DQSP_DRIVE_PAD_CTL :: BL_ND_TERM_STRENGTH [14:10] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_DQSP_DRIVE_PAD_CTL_BL_ND_TERM_STRENGTH_MASK 0x00007c00
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_DQSP_DRIVE_PAD_CTL_BL_ND_TERM_STRENGTH_SHIFT 10
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_DQSP_DRIVE_PAD_CTL_BL_ND_TERM_STRENGTH_DEFAULT 0x00000008
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: DQSP_DRIVE_PAD_CTL :: BL_PD_STRENGTH [09:05] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_DQSP_DRIVE_PAD_CTL_BL_PD_STRENGTH_MASK 0x000003e0
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_DQSP_DRIVE_PAD_CTL_BL_PD_STRENGTH_SHIFT 5
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_DQSP_DRIVE_PAD_CTL_BL_PD_STRENGTH_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: DQSP_DRIVE_PAD_CTL :: BL_ND_STRENGTH [04:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_DQSP_DRIVE_PAD_CTL_BL_ND_STRENGTH_MASK 0x0000001f
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_DQSP_DRIVE_PAD_CTL_BL_ND_STRENGTH_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_DQSP_DRIVE_PAD_CTL_BL_ND_STRENGTH_DEFAULT 0x00000000
-
-/***************************************************************************
- *DQSN_DRIVE_PAD_CTL - DQS pad N rail drive characteristics control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_3_0 :: DQSN_DRIVE_PAD_CTL :: reserved0 [31:30] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_DQSN_DRIVE_PAD_CTL_reserved0_MASK 0xc0000000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_DQSN_DRIVE_PAD_CTL_reserved0_SHIFT 30
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: DQSN_DRIVE_PAD_CTL :: BL_PD_IDLE_STRENGTH [29:25] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_DQSN_DRIVE_PAD_CTL_BL_PD_IDLE_STRENGTH_MASK 0x3e000000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_DQSN_DRIVE_PAD_CTL_BL_PD_IDLE_STRENGTH_SHIFT 25
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_DQSN_DRIVE_PAD_CTL_BL_PD_IDLE_STRENGTH_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: DQSN_DRIVE_PAD_CTL :: BL_ND_IDLE_STRENGTH [24:20] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_DQSN_DRIVE_PAD_CTL_BL_ND_IDLE_STRENGTH_MASK 0x01f00000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_DQSN_DRIVE_PAD_CTL_BL_ND_IDLE_STRENGTH_SHIFT 20
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_DQSN_DRIVE_PAD_CTL_BL_ND_IDLE_STRENGTH_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: DQSN_DRIVE_PAD_CTL :: BL_PD_TERM_STRENGTH [19:15] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_DQSN_DRIVE_PAD_CTL_BL_PD_TERM_STRENGTH_MASK 0x000f8000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_DQSN_DRIVE_PAD_CTL_BL_PD_TERM_STRENGTH_SHIFT 15
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_DQSN_DRIVE_PAD_CTL_BL_PD_TERM_STRENGTH_DEFAULT 0x00000008
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: DQSN_DRIVE_PAD_CTL :: BL_ND_TERM_STRENGTH [14:10] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_DQSN_DRIVE_PAD_CTL_BL_ND_TERM_STRENGTH_MASK 0x00007c00
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_DQSN_DRIVE_PAD_CTL_BL_ND_TERM_STRENGTH_SHIFT 10
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_DQSN_DRIVE_PAD_CTL_BL_ND_TERM_STRENGTH_DEFAULT 0x00000008
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: DQSN_DRIVE_PAD_CTL :: BL_PD_STRENGTH [09:05] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_DQSN_DRIVE_PAD_CTL_BL_PD_STRENGTH_MASK 0x000003e0
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_DQSN_DRIVE_PAD_CTL_BL_PD_STRENGTH_SHIFT 5
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_DQSN_DRIVE_PAD_CTL_BL_PD_STRENGTH_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: DQSN_DRIVE_PAD_CTL :: BL_ND_STRENGTH [04:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_DQSN_DRIVE_PAD_CTL_BL_ND_STRENGTH_MASK 0x0000001f
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_DQSN_DRIVE_PAD_CTL_BL_ND_STRENGTH_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_DQSN_DRIVE_PAD_CTL_BL_ND_STRENGTH_DEFAULT 0x00000000
-
-/***************************************************************************
- *EDC_DRIVE_PAD_CTL - EDC pad drive characteristics control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_3_0 :: EDC_DRIVE_PAD_CTL :: reserved0 [31:30] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_DRIVE_PAD_CTL_reserved0_MASK 0xc0000000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_DRIVE_PAD_CTL_reserved0_SHIFT 30
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: EDC_DRIVE_PAD_CTL :: BL_PD_IDLE_STRENGTH [29:25] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_DRIVE_PAD_CTL_BL_PD_IDLE_STRENGTH_MASK 0x3e000000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_DRIVE_PAD_CTL_BL_PD_IDLE_STRENGTH_SHIFT 25
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_DRIVE_PAD_CTL_BL_PD_IDLE_STRENGTH_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: EDC_DRIVE_PAD_CTL :: BL_ND_IDLE_STRENGTH [24:20] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_DRIVE_PAD_CTL_BL_ND_IDLE_STRENGTH_MASK 0x01f00000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_DRIVE_PAD_CTL_BL_ND_IDLE_STRENGTH_SHIFT 20
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_DRIVE_PAD_CTL_BL_ND_IDLE_STRENGTH_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: EDC_DRIVE_PAD_CTL :: BL_PD_TERM_STRENGTH [19:15] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_DRIVE_PAD_CTL_BL_PD_TERM_STRENGTH_MASK 0x000f8000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_DRIVE_PAD_CTL_BL_PD_TERM_STRENGTH_SHIFT 15
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_DRIVE_PAD_CTL_BL_PD_TERM_STRENGTH_DEFAULT 0x00000008
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: EDC_DRIVE_PAD_CTL :: BL_ND_TERM_STRENGTH [14:10] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_DRIVE_PAD_CTL_BL_ND_TERM_STRENGTH_MASK 0x00007c00
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_DRIVE_PAD_CTL_BL_ND_TERM_STRENGTH_SHIFT 10
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_DRIVE_PAD_CTL_BL_ND_TERM_STRENGTH_DEFAULT 0x00000008
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: EDC_DRIVE_PAD_CTL :: BL_PD_STRENGTH [09:05] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_DRIVE_PAD_CTL_BL_PD_STRENGTH_MASK 0x000003e0
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_DRIVE_PAD_CTL_BL_PD_STRENGTH_SHIFT 5
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_DRIVE_PAD_CTL_BL_PD_STRENGTH_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: EDC_DRIVE_PAD_CTL :: BL_ND_STRENGTH [04:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_DRIVE_PAD_CTL_BL_ND_STRENGTH_MASK 0x0000001f
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_DRIVE_PAD_CTL_BL_ND_STRENGTH_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_DRIVE_PAD_CTL_BL_ND_STRENGTH_DEFAULT 0x00000000
-
-/***************************************************************************
- *RD_EN_DRIVE_PAD_CTL - RD_EN, EDC_RD_EN read enable pad drive characteristics control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_3_0 :: RD_EN_DRIVE_PAD_CTL :: reserved0 [31:20] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_RD_EN_DRIVE_PAD_CTL_reserved0_MASK 0xfff00000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_RD_EN_DRIVE_PAD_CTL_reserved0_SHIFT 20
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: RD_EN_DRIVE_PAD_CTL :: EDC_RD_EN_PD_STRENGTH [19:15] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_RD_EN_DRIVE_PAD_CTL_EDC_RD_EN_PD_STRENGTH_MASK 0x000f8000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_RD_EN_DRIVE_PAD_CTL_EDC_RD_EN_PD_STRENGTH_SHIFT 15
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_RD_EN_DRIVE_PAD_CTL_EDC_RD_EN_PD_STRENGTH_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: RD_EN_DRIVE_PAD_CTL :: EDC_RD_EN_ND_STRENGTH [14:10] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_RD_EN_DRIVE_PAD_CTL_EDC_RD_EN_ND_STRENGTH_MASK 0x00007c00
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_RD_EN_DRIVE_PAD_CTL_EDC_RD_EN_ND_STRENGTH_SHIFT 10
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_RD_EN_DRIVE_PAD_CTL_EDC_RD_EN_ND_STRENGTH_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: RD_EN_DRIVE_PAD_CTL :: BL_RD_EN_PD_STRENGTH [09:05] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_RD_EN_DRIVE_PAD_CTL_BL_RD_EN_PD_STRENGTH_MASK 0x000003e0
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_RD_EN_DRIVE_PAD_CTL_BL_RD_EN_PD_STRENGTH_SHIFT 5
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_RD_EN_DRIVE_PAD_CTL_BL_RD_EN_PD_STRENGTH_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: RD_EN_DRIVE_PAD_CTL :: BL_RD_EN_ND_STRENGTH [04:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_RD_EN_DRIVE_PAD_CTL_BL_RD_EN_ND_STRENGTH_MASK 0x0000001f
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_RD_EN_DRIVE_PAD_CTL_BL_RD_EN_ND_STRENGTH_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_RD_EN_DRIVE_PAD_CTL_BL_RD_EN_ND_STRENGTH_DEFAULT 0x00000000
-
-/***************************************************************************
- *STATIC_PAD_CTL - pad rx and tx characteristics control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_3_0 :: STATIC_PAD_CTL :: reserved0 [31:25] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_STATIC_PAD_CTL_reserved0_MASK 0xfe000000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_STATIC_PAD_CTL_reserved0_SHIFT 25
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: STATIC_PAD_CTL :: TX_SLEW [24:23] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_STATIC_PAD_CTL_TX_SLEW_MASK 0x01800000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_STATIC_PAD_CTL_TX_SLEW_SHIFT 23
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_STATIC_PAD_CTL_TX_SLEW_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: STATIC_PAD_CTL :: DQS_MODE [22:22] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_STATIC_PAD_CTL_DQS_MODE_MASK 0x00400000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_STATIC_PAD_CTL_DQS_MODE_SHIFT 22
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_STATIC_PAD_CTL_DQS_MODE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: STATIC_PAD_CTL :: reserved1 [21:20] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_STATIC_PAD_CTL_reserved1_MASK 0x00300000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_STATIC_PAD_CTL_reserved1_SHIFT 20
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: STATIC_PAD_CTL :: EDC_MODE [19:18] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_STATIC_PAD_CTL_EDC_MODE_MASK 0x000c0000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_STATIC_PAD_CTL_EDC_MODE_SHIFT 18
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_STATIC_PAD_CTL_EDC_MODE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: STATIC_PAD_CTL :: reserved2 [17:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_STATIC_PAD_CTL_reserved2_MASK 0x00020000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_STATIC_PAD_CTL_reserved2_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: STATIC_PAD_CTL :: WDBI_ENABLE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_STATIC_PAD_CTL_WDBI_ENABLE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_STATIC_PAD_CTL_WDBI_ENABLE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_STATIC_PAD_CTL_WDBI_ENABLE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: STATIC_PAD_CTL :: RDBI_ENABLE [15:15] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_STATIC_PAD_CTL_RDBI_ENABLE_MASK 0x00008000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_STATIC_PAD_CTL_RDBI_ENABLE_SHIFT 15
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_STATIC_PAD_CTL_RDBI_ENABLE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: STATIC_PAD_CTL :: DM_MODE [14:14] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_STATIC_PAD_CTL_DM_MODE_MASK 0x00004000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_STATIC_PAD_CTL_DM_MODE_SHIFT 14
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_STATIC_PAD_CTL_DM_MODE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: STATIC_PAD_CTL :: reserved3 [13:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_STATIC_PAD_CTL_reserved3_MASK 0x00002000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_STATIC_PAD_CTL_reserved3_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: STATIC_PAD_CTL :: DQS_TX_PAUSE [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_STATIC_PAD_CTL_DQS_TX_PAUSE_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_STATIC_PAD_CTL_DQS_TX_PAUSE_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_STATIC_PAD_CTL_DQS_TX_PAUSE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: STATIC_PAD_CTL :: reserved_for_padding4 [11:11] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_STATIC_PAD_CTL_reserved_for_padding4_MASK 0x00000800
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_STATIC_PAD_CTL_reserved_for_padding4_SHIFT 11
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: STATIC_PAD_CTL :: DQS_TX_DIS [10:10] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_STATIC_PAD_CTL_DQS_TX_DIS_MASK 0x00000400
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_STATIC_PAD_CTL_DQS_TX_DIS_SHIFT 10
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_STATIC_PAD_CTL_DQS_TX_DIS_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: STATIC_PAD_CTL :: TX_MODE [09:04] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_STATIC_PAD_CTL_TX_MODE_MASK 0x000003f0
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_STATIC_PAD_CTL_TX_MODE_SHIFT 4
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_STATIC_PAD_CTL_TX_MODE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: STATIC_PAD_CTL :: reserved5 [03:03] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_STATIC_PAD_CTL_reserved5_MASK 0x00000008
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_STATIC_PAD_CTL_reserved5_SHIFT 3
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: STATIC_PAD_CTL :: RX_MODE [02:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_STATIC_PAD_CTL_RX_MODE_MASK 0x00000007
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_STATIC_PAD_CTL_RX_MODE_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_STATIC_PAD_CTL_RX_MODE_DEFAULT 0x00000000
-
-/***************************************************************************
- *DQ_RX_TRIM - Receiver trim for DQ
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_3_0 :: DQ_RX_TRIM :: reserved0 [31:21] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_DQ_RX_TRIM_reserved0_MASK 0xffe00000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_DQ_RX_TRIM_reserved0_SHIFT 21
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: DQ_RX_TRIM :: LSTRIM [20:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_DQ_RX_TRIM_LSTRIM_MASK 0x001e0000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_DQ_RX_TRIM_LSTRIM_SHIFT 17
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_DQ_RX_TRIM_LSTRIM_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: DQ_RX_TRIM :: ITRIM [16:14] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_DQ_RX_TRIM_ITRIM_MASK 0x0001c000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_DQ_RX_TRIM_ITRIM_SHIFT 14
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_DQ_RX_TRIM_ITRIM_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: DQ_RX_TRIM :: IDLE_LSTRIM [13:10] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_DQ_RX_TRIM_IDLE_LSTRIM_MASK 0x00003c00
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_DQ_RX_TRIM_IDLE_LSTRIM_SHIFT 10
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_DQ_RX_TRIM_IDLE_LSTRIM_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: DQ_RX_TRIM :: IDLE_ITRIM [09:07] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_DQ_RX_TRIM_IDLE_ITRIM_MASK 0x00000380
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_DQ_RX_TRIM_IDLE_ITRIM_SHIFT 7
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_DQ_RX_TRIM_IDLE_ITRIM_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: DQ_RX_TRIM :: TERM_LSTRIM [06:03] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_DQ_RX_TRIM_TERM_LSTRIM_MASK 0x00000078
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_DQ_RX_TRIM_TERM_LSTRIM_SHIFT 3
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_DQ_RX_TRIM_TERM_LSTRIM_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: DQ_RX_TRIM :: TERM_ITRIM [02:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_DQ_RX_TRIM_TERM_ITRIM_MASK 0x00000007
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_DQ_RX_TRIM_TERM_ITRIM_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_DQ_RX_TRIM_TERM_ITRIM_DEFAULT 0x00000000
-
-/***************************************************************************
- *MISC_RX_TRIM - Receiver trim for miscellaneous pins
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_3_0 :: MISC_RX_TRIM :: reserved0 [31:21] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_MISC_RX_TRIM_reserved0_MASK 0xffe00000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_MISC_RX_TRIM_reserved0_SHIFT 21
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: MISC_RX_TRIM :: LSTRIM [20:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_MISC_RX_TRIM_LSTRIM_MASK 0x001e0000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_MISC_RX_TRIM_LSTRIM_SHIFT 17
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_MISC_RX_TRIM_LSTRIM_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: MISC_RX_TRIM :: ITRIM [16:14] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_MISC_RX_TRIM_ITRIM_MASK 0x0001c000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_MISC_RX_TRIM_ITRIM_SHIFT 14
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_MISC_RX_TRIM_ITRIM_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: MISC_RX_TRIM :: IDLE_LSTRIM [13:10] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_MISC_RX_TRIM_IDLE_LSTRIM_MASK 0x00003c00
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_MISC_RX_TRIM_IDLE_LSTRIM_SHIFT 10
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_MISC_RX_TRIM_IDLE_LSTRIM_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: MISC_RX_TRIM :: IDLE_ITRIM [09:07] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_MISC_RX_TRIM_IDLE_ITRIM_MASK 0x00000380
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_MISC_RX_TRIM_IDLE_ITRIM_SHIFT 7
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_MISC_RX_TRIM_IDLE_ITRIM_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: MISC_RX_TRIM :: TERM_LSTRIM [06:03] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_MISC_RX_TRIM_TERM_LSTRIM_MASK 0x00000078
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_MISC_RX_TRIM_TERM_LSTRIM_SHIFT 3
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_MISC_RX_TRIM_TERM_LSTRIM_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: MISC_RX_TRIM :: TERM_ITRIM [02:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_MISC_RX_TRIM_TERM_ITRIM_MASK 0x00000007
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_MISC_RX_TRIM_TERM_ITRIM_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_MISC_RX_TRIM_TERM_ITRIM_DEFAULT 0x00000000
-
-/***************************************************************************
- *DQS_RX_TRIM - Rreceiver trim for DQS
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_3_0 :: DQS_RX_TRIM :: reserved0 [31:21] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_DQS_RX_TRIM_reserved0_MASK 0xffe00000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_DQS_RX_TRIM_reserved0_SHIFT 21
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: DQS_RX_TRIM :: LSTRIM [20:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_DQS_RX_TRIM_LSTRIM_MASK 0x001e0000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_DQS_RX_TRIM_LSTRIM_SHIFT 17
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_DQS_RX_TRIM_LSTRIM_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: DQS_RX_TRIM :: ITRIM [16:14] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_DQS_RX_TRIM_ITRIM_MASK 0x0001c000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_DQS_RX_TRIM_ITRIM_SHIFT 14
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_DQS_RX_TRIM_ITRIM_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: DQS_RX_TRIM :: IDLE_LSTRIM [13:10] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_DQS_RX_TRIM_IDLE_LSTRIM_MASK 0x00003c00
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_DQS_RX_TRIM_IDLE_LSTRIM_SHIFT 10
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_DQS_RX_TRIM_IDLE_LSTRIM_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: DQS_RX_TRIM :: IDLE_ITRIM [09:07] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_DQS_RX_TRIM_IDLE_ITRIM_MASK 0x00000380
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_DQS_RX_TRIM_IDLE_ITRIM_SHIFT 7
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_DQS_RX_TRIM_IDLE_ITRIM_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: DQS_RX_TRIM :: TERM_LSTRIM [06:03] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_DQS_RX_TRIM_TERM_LSTRIM_MASK 0x00000078
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_DQS_RX_TRIM_TERM_LSTRIM_SHIFT 3
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_DQS_RX_TRIM_TERM_LSTRIM_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: DQS_RX_TRIM :: TERM_ITRIM [02:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_DQS_RX_TRIM_TERM_ITRIM_MASK 0x00000007
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_DQS_RX_TRIM_TERM_ITRIM_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_DQS_RX_TRIM_TERM_ITRIM_DEFAULT 0x00000000
-
-/***************************************************************************
- *WR_PREAMBLE_MODE - Write cycle preamble control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_3_0 :: WR_PREAMBLE_MODE :: reserved0 [31:21] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_WR_PREAMBLE_MODE_reserved0_MASK 0xffe00000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_WR_PREAMBLE_MODE_reserved0_SHIFT 21
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: WR_PREAMBLE_MODE :: POSTAM_TERM_BITS [20:19] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_WR_PREAMBLE_MODE_POSTAM_TERM_BITS_MASK 0x00180000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_WR_PREAMBLE_MODE_POSTAM_TERM_BITS_SHIFT 19
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_WR_PREAMBLE_MODE_POSTAM_TERM_BITS_DEFAULT 0x00000003
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: WR_PREAMBLE_MODE :: DM_POSTAM_BITS [18:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_WR_PREAMBLE_MODE_DM_POSTAM_BITS_MASK 0x00060000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_WR_PREAMBLE_MODE_DM_POSTAM_BITS_SHIFT 17
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_WR_PREAMBLE_MODE_DM_POSTAM_BITS_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: WR_PREAMBLE_MODE :: DM_PREAM_BITS [16:14] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_WR_PREAMBLE_MODE_DM_PREAM_BITS_MASK 0x0001c000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_WR_PREAMBLE_MODE_DM_PREAM_BITS_SHIFT 14
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_WR_PREAMBLE_MODE_DM_PREAM_BITS_DEFAULT 0x00000001
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: WR_PREAMBLE_MODE :: DQ_POSTAM_BITS [13:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_WR_PREAMBLE_MODE_DQ_POSTAM_BITS_MASK 0x00003000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_WR_PREAMBLE_MODE_DQ_POSTAM_BITS_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_WR_PREAMBLE_MODE_DQ_POSTAM_BITS_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: WR_PREAMBLE_MODE :: DQ_PREAM_BITS [11:09] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_WR_PREAMBLE_MODE_DQ_PREAM_BITS_MASK 0x00000e00
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_WR_PREAMBLE_MODE_DQ_PREAM_BITS_SHIFT 9
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_WR_PREAMBLE_MODE_DQ_PREAM_BITS_DEFAULT 0x00000001
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: WR_PREAMBLE_MODE :: DQS [08:05] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_WR_PREAMBLE_MODE_DQS_MASK 0x000001e0
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_WR_PREAMBLE_MODE_DQS_SHIFT 5
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_WR_PREAMBLE_MODE_DQS_DEFAULT 0x0000000a
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: WR_PREAMBLE_MODE :: DQS_POSTAM_BITS [04:03] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_WR_PREAMBLE_MODE_DQS_POSTAM_BITS_MASK 0x00000018
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_WR_PREAMBLE_MODE_DQS_POSTAM_BITS_SHIFT 3
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_WR_PREAMBLE_MODE_DQS_POSTAM_BITS_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: WR_PREAMBLE_MODE :: DQS_PREAM_BITS [02:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_WR_PREAMBLE_MODE_DQS_PREAM_BITS_MASK 0x00000007
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_WR_PREAMBLE_MODE_DQS_PREAM_BITS_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_WR_PREAMBLE_MODE_DQS_PREAM_BITS_DEFAULT 0x00000002
-
-/***************************************************************************
- *ODT_CONTROL - Read channel ODT control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_3_0 :: ODT_CONTROL :: reserved_for_padding0 [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_ODT_CONTROL_reserved_for_padding0_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_ODT_CONTROL_reserved_for_padding0_SHIFT 31
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: ODT_CONTROL :: reserved1 [30:10] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_ODT_CONTROL_reserved1_MASK 0x7ffffc00
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_ODT_CONTROL_reserved1_SHIFT 10
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: ODT_CONTROL :: ODT_ENABLE [09:09] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_ODT_CONTROL_ODT_ENABLE_MASK 0x00000200
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_ODT_CONTROL_ODT_ENABLE_SHIFT 9
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_ODT_CONTROL_ODT_ENABLE_DEFAULT 0x00000001
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: ODT_CONTROL :: ODT_DELAY [08:06] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_ODT_CONTROL_ODT_DELAY_MASK 0x000001c0
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_ODT_CONTROL_ODT_DELAY_SHIFT 6
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_ODT_CONTROL_ODT_DELAY_DEFAULT 0x00000001
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: ODT_CONTROL :: ODT_POST_LENGTH [05:03] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_ODT_CONTROL_ODT_POST_LENGTH_MASK 0x00000038
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_ODT_CONTROL_ODT_POST_LENGTH_SHIFT 3
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_ODT_CONTROL_ODT_POST_LENGTH_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: ODT_CONTROL :: ODT_PRE_LENGTH [02:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_ODT_CONTROL_ODT_PRE_LENGTH_MASK 0x00000007
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_ODT_CONTROL_ODT_PRE_LENGTH_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_ODT_CONTROL_ODT_PRE_LENGTH_DEFAULT 0x00000003
-
-/***************************************************************************
- *LDO_CONFIG - LDO Configuration register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_3_0 :: LDO_CONFIG :: reserved0 [31:06] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_LDO_CONFIG_reserved0_MASK 0xffffffc0
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_LDO_CONFIG_reserved0_SHIFT 6
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: LDO_CONFIG :: CK_LDO_PWRDOWN [05:05] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_LDO_CONFIG_CK_LDO_PWRDOWN_MASK 0x00000020
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_LDO_CONFIG_CK_LDO_PWRDOWN_SHIFT 5
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_LDO_CONFIG_CK_LDO_PWRDOWN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: LDO_CONFIG :: CK_LDO_REF_SEL [04:04] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_LDO_CONFIG_CK_LDO_REF_SEL_MASK 0x00000010
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_LDO_CONFIG_CK_LDO_REF_SEL_SHIFT 4
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_LDO_CONFIG_CK_LDO_REF_SEL_DEFAULT 0x00000001
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: LDO_CONFIG :: CK_LDO_REF_CTRL [03:02] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_LDO_CONFIG_CK_LDO_REF_CTRL_MASK 0x0000000c
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_LDO_CONFIG_CK_LDO_REF_CTRL_SHIFT 2
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_LDO_CONFIG_CK_LDO_REF_CTRL_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: LDO_CONFIG :: CK_LDO_BIAS [01:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_LDO_CONFIG_CK_LDO_BIAS_MASK 0x00000003
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_LDO_CONFIG_CK_LDO_BIAS_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_LDO_CONFIG_CK_LDO_BIAS_DEFAULT 0x00000000
-
-/***************************************************************************
- *EDC_DPD_CONTROL - GDDR5M EDC digital phase detector control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_3_0 :: EDC_DPD_CONTROL :: reserved0 [31:22] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_DPD_CONTROL_reserved0_MASK 0xffc00000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_DPD_CONTROL_reserved0_SHIFT 22
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: EDC_DPD_CONTROL :: DQS_PHASE_OVERRIDE_VALUE [21:21] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_DPD_CONTROL_DQS_PHASE_OVERRIDE_VALUE_MASK 0x00200000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_DPD_CONTROL_DQS_PHASE_OVERRIDE_VALUE_SHIFT 21
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_DPD_CONTROL_DQS_PHASE_OVERRIDE_VALUE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: EDC_DPD_CONTROL :: DQS_PHASE_OVERRIDE_ENABLE [20:20] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_DPD_CONTROL_DQS_PHASE_OVERRIDE_ENABLE_MASK 0x00100000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_DPD_CONTROL_DQS_PHASE_OVERRIDE_ENABLE_SHIFT 20
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_DPD_CONTROL_DQS_PHASE_OVERRIDE_ENABLE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: EDC_DPD_CONTROL :: reserved1 [19:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_DPD_CONTROL_reserved1_MASK 0x000f0000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_DPD_CONTROL_reserved1_SHIFT 16
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: EDC_DPD_CONTROL :: TARGET_CS_N [15:15] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_DPD_CONTROL_TARGET_CS_N_MASK 0x00008000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_DPD_CONTROL_TARGET_CS_N_SHIFT 15
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_DPD_CONTROL_TARGET_CS_N_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: EDC_DPD_CONTROL :: UPDATE_MODE [14:14] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_DPD_CONTROL_UPDATE_MODE_MASK 0x00004000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_DPD_CONTROL_UPDATE_MODE_SHIFT 14
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_DPD_CONTROL_UPDATE_MODE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: EDC_DPD_CONTROL :: SAMPLE_MODE [13:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_DPD_CONTROL_SAMPLE_MODE_MASK 0x00003000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_DPD_CONTROL_SAMPLE_MODE_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_DPD_CONTROL_SAMPLE_MODE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: EDC_DPD_CONTROL :: reserved2 [11:09] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_DPD_CONTROL_reserved2_MASK 0x00000e00
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_DPD_CONTROL_reserved2_SHIFT 9
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: EDC_DPD_CONTROL :: MIN_LOW_SAMPLES [08:04] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_DPD_CONTROL_MIN_LOW_SAMPLES_MASK 0x000001f0
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_DPD_CONTROL_MIN_LOW_SAMPLES_SHIFT 4
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_DPD_CONTROL_MIN_LOW_SAMPLES_DEFAULT 0x00000008
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: EDC_DPD_CONTROL :: SET_ADJ_EN [03:03] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_DPD_CONTROL_SET_ADJ_EN_MASK 0x00000008
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_DPD_CONTROL_SET_ADJ_EN_SHIFT 3
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_DPD_CONTROL_SET_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: EDC_DPD_CONTROL :: UPDATE [02:02] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_DPD_CONTROL_UPDATE_MASK 0x00000004
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_DPD_CONTROL_UPDATE_SHIFT 2
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_DPD_CONTROL_UPDATE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: EDC_DPD_CONTROL :: MONITOR [01:01] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_DPD_CONTROL_MONITOR_MASK 0x00000002
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_DPD_CONTROL_MONITOR_SHIFT 1
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_DPD_CONTROL_MONITOR_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: EDC_DPD_CONTROL :: INIT [00:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_DPD_CONTROL_INIT_MASK 0x00000001
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_DPD_CONTROL_INIT_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_DPD_CONTROL_INIT_DEFAULT 0x00000000
-
-/***************************************************************************
- *EDC_DPD_STATUS - GDDR5M EDC digital phase detector status register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_3_0 :: EDC_DPD_STATUS :: reserved0 [31:29] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_DPD_STATUS_reserved0_MASK 0xe0000000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_DPD_STATUS_reserved0_SHIFT 29
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: EDC_DPD_STATUS :: CURRENT_DQS_PHASE [28:28] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_DPD_STATUS_CURRENT_DQS_PHASE_MASK 0x10000000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_DPD_STATUS_CURRENT_DQS_PHASE_SHIFT 28
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_DPD_STATUS_CURRENT_DQS_PHASE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: EDC_DPD_STATUS :: CURRENT_VDL_SETTING [27:20] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_DPD_STATUS_CURRENT_VDL_SETTING_MASK 0x0ff00000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_DPD_STATUS_CURRENT_VDL_SETTING_SHIFT 20
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_DPD_STATUS_CURRENT_VDL_SETTING_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: EDC_DPD_STATUS :: reserved1 [19:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_DPD_STATUS_reserved1_MASK 0x000e0000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_DPD_STATUS_reserved1_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: EDC_DPD_STATUS :: INIT_DQS_PHASE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_DPD_STATUS_INIT_DQS_PHASE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_DPD_STATUS_INIT_DQS_PHASE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_DPD_STATUS_INIT_DQS_PHASE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: EDC_DPD_STATUS :: INIT_VDL_SETTING [15:08] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_DPD_STATUS_INIT_VDL_SETTING_MASK 0x0000ff00
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_DPD_STATUS_INIT_VDL_SETTING_SHIFT 8
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_DPD_STATUS_INIT_VDL_SETTING_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: EDC_DPD_STATUS :: reserved2 [07:05] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_DPD_STATUS_reserved2_MASK 0x000000e0
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_DPD_STATUS_reserved2_SHIFT 5
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: EDC_DPD_STATUS :: MONITOR_ERROR [04:04] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_DPD_STATUS_MONITOR_ERROR_MASK 0x00000010
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_DPD_STATUS_MONITOR_ERROR_SHIFT 4
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_DPD_STATUS_MONITOR_ERROR_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: EDC_DPD_STATUS :: MONITOR_BUSY [03:03] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_DPD_STATUS_MONITOR_BUSY_MASK 0x00000008
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_DPD_STATUS_MONITOR_BUSY_SHIFT 3
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_DPD_STATUS_MONITOR_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: EDC_DPD_STATUS :: INIT_LOCK [02:02] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_DPD_STATUS_INIT_LOCK_MASK 0x00000004
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_DPD_STATUS_INIT_LOCK_SHIFT 2
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_DPD_STATUS_INIT_LOCK_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: EDC_DPD_STATUS :: INIT_BUSY [01:01] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_DPD_STATUS_INIT_BUSY_MASK 0x00000002
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_DPD_STATUS_INIT_BUSY_SHIFT 1
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_DPD_STATUS_INIT_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: EDC_DPD_STATUS :: INIT_DONE [00:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_DPD_STATUS_INIT_DONE_MASK 0x00000001
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_DPD_STATUS_INIT_DONE_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_DPD_STATUS_INIT_DONE_DEFAULT 0x00000000
-
-/***************************************************************************
- *EDC_DPD_OUT_CONTROL - GDDR5M EDC digital phase detector output signal control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_3_0 :: EDC_DPD_OUT_CONTROL :: reserved0 [31:20] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_DPD_OUT_CONTROL_reserved0_MASK 0xfff00000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_DPD_OUT_CONTROL_reserved0_SHIFT 20
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: EDC_DPD_OUT_CONTROL :: LOWER_LIMIT [19:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_DPD_OUT_CONTROL_LOWER_LIMIT_MASK 0x000ff000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_DPD_OUT_CONTROL_LOWER_LIMIT_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_DPD_OUT_CONTROL_LOWER_LIMIT_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: EDC_DPD_OUT_CONTROL :: UPPER_LIMIT [11:04] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_DPD_OUT_CONTROL_UPPER_LIMIT_MASK 0x00000ff0
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_DPD_OUT_CONTROL_UPPER_LIMIT_SHIFT 4
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_DPD_OUT_CONTROL_UPPER_LIMIT_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: EDC_DPD_OUT_CONTROL :: reserved1 [03:01] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_DPD_OUT_CONTROL_reserved1_MASK 0x0000000e
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_DPD_OUT_CONTROL_reserved1_SHIFT 1
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: EDC_DPD_OUT_CONTROL :: ENABLE [00:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_DPD_OUT_CONTROL_ENABLE_MASK 0x00000001
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_DPD_OUT_CONTROL_ENABLE_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_DPD_OUT_CONTROL_ENABLE_DEFAULT 0x00000000
-
-/***************************************************************************
- *EDC_DPD_OUT_STATUS - GDDR5M EDC digital phase detector output signal status register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_3_0 :: EDC_DPD_OUT_STATUS :: reserved0 [31:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_DPD_OUT_STATUS_reserved0_MASK 0xfffff000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_DPD_OUT_STATUS_reserved0_SHIFT 12
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: EDC_DPD_OUT_STATUS :: VDL_SETTING [11:04] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_DPD_OUT_STATUS_VDL_SETTING_MASK 0x00000ff0
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_DPD_OUT_STATUS_VDL_SETTING_SHIFT 4
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_DPD_OUT_STATUS_VDL_SETTING_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: EDC_DPD_OUT_STATUS :: reserved1 [03:01] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_DPD_OUT_STATUS_reserved1_MASK 0x0000000e
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_DPD_OUT_STATUS_reserved1_SHIFT 1
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: EDC_DPD_OUT_STATUS :: VALID [00:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_DPD_OUT_STATUS_VALID_MASK 0x00000001
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_DPD_OUT_STATUS_VALID_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_DPD_OUT_STATUS_VALID_DEFAULT 0x00000000
-
-/***************************************************************************
- *EDC_DPD_OUT_STATUS_CLEAR - GDDR5M EDC digital phase detector output signal status clear register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_3_0 :: EDC_DPD_OUT_STATUS_CLEAR :: reserved0 [31:01] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_DPD_OUT_STATUS_CLEAR_reserved0_MASK 0xfffffffe
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_DPD_OUT_STATUS_CLEAR_reserved0_SHIFT 1
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: EDC_DPD_OUT_STATUS_CLEAR :: CLEAR [00:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_DPD_OUT_STATUS_CLEAR_CLEAR_MASK 0x00000001
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_DPD_OUT_STATUS_CLEAR_CLEAR_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_DPD_OUT_STATUS_CLEAR_CLEAR_DEFAULT 0x00000000
-
-/***************************************************************************
- *EDC_CRC_CONTROL - GDDR5M EDC signal path CRC control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_3_0 :: EDC_CRC_CONTROL :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_CRC_CONTROL_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_CRC_CONTROL_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_CRC_CONTROL_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: EDC_CRC_CONTROL :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_CRC_CONTROL_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_CRC_CONTROL_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: EDC_CRC_CONTROL :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_CRC_CONTROL_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_CRC_CONTROL_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_CRC_CONTROL_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: EDC_CRC_CONTROL :: reserved1 [15:11] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_CRC_CONTROL_reserved1_MASK 0x0000f800
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_CRC_CONTROL_reserved1_SHIFT 11
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: EDC_CRC_CONTROL :: CRCWL [10:08] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_CRC_CONTROL_CRCWL_MASK 0x00000700
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_CRC_CONTROL_CRCWL_SHIFT 8
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_CRC_CONTROL_CRCWL_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: EDC_CRC_CONTROL :: reserved2 [07:06] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_CRC_CONTROL_reserved2_MASK 0x000000c0
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_CRC_CONTROL_reserved2_SHIFT 6
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: EDC_CRC_CONTROL :: CRCRL [05:04] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_CRC_CONTROL_CRCRL_MASK 0x00000030
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_CRC_CONTROL_CRCRL_SHIFT 4
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_CRC_CONTROL_CRCRL_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: EDC_CRC_CONTROL :: reserved3 [03:02] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_CRC_CONTROL_reserved3_MASK 0x0000000c
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_CRC_CONTROL_reserved3_SHIFT 2
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: EDC_CRC_CONTROL :: ENABLE_WR [01:01] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_CRC_CONTROL_ENABLE_WR_MASK 0x00000002
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_CRC_CONTROL_ENABLE_WR_SHIFT 1
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_CRC_CONTROL_ENABLE_WR_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: EDC_CRC_CONTROL :: ENABLE_RD [00:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_CRC_CONTROL_ENABLE_RD_MASK 0x00000001
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_CRC_CONTROL_ENABLE_RD_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_CRC_CONTROL_ENABLE_RD_DEFAULT 0x00000000
-
-/***************************************************************************
- *EDC_CRC_STATUS - GDDR5M EDC signal path CRC status register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_3_0 :: EDC_CRC_STATUS :: MISCOMPARE_EXP_CRC [31:24] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_CRC_STATUS_MISCOMPARE_EXP_CRC_MASK 0xff000000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_CRC_STATUS_MISCOMPARE_EXP_CRC_SHIFT 24
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: EDC_CRC_STATUS :: MISCOMPARE_CRC [23:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_CRC_STATUS_MISCOMPARE_CRC_MASK 0x00ff0000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_CRC_STATUS_MISCOMPARE_CRC_SHIFT 16
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: EDC_CRC_STATUS :: MOST_RECENT_CRC [15:08] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_CRC_STATUS_MOST_RECENT_CRC_MASK 0x0000ff00
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_CRC_STATUS_MOST_RECENT_CRC_SHIFT 8
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: EDC_CRC_STATUS :: reserved0 [07:05] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_CRC_STATUS_reserved0_MASK 0x000000e0
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_CRC_STATUS_reserved0_SHIFT 5
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: EDC_CRC_STATUS :: MISCOMPARE_TYPE [04:04] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_CRC_STATUS_MISCOMPARE_TYPE_MASK 0x00000010
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_CRC_STATUS_MISCOMPARE_TYPE_SHIFT 4
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: EDC_CRC_STATUS :: WR_FAIL [03:03] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_CRC_STATUS_WR_FAIL_MASK 0x00000008
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_CRC_STATUS_WR_FAIL_SHIFT 3
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: EDC_CRC_STATUS :: WR_PASS [02:02] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_CRC_STATUS_WR_PASS_MASK 0x00000004
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_CRC_STATUS_WR_PASS_SHIFT 2
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: EDC_CRC_STATUS :: RD_FAIL [01:01] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_CRC_STATUS_RD_FAIL_MASK 0x00000002
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_CRC_STATUS_RD_FAIL_SHIFT 1
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: EDC_CRC_STATUS :: RD_PASS [00:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_CRC_STATUS_RD_PASS_MASK 0x00000001
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_CRC_STATUS_RD_PASS_SHIFT 0
-
-/***************************************************************************
- *EDC_CRC_COUNT - GDDR5M EDC signal path CRC counter register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_3_0 :: EDC_CRC_COUNT :: WR_FAIL_COUNT [31:24] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_CRC_COUNT_WR_FAIL_COUNT_MASK 0xff000000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_CRC_COUNT_WR_FAIL_COUNT_SHIFT 24
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: EDC_CRC_COUNT :: WR_PASS_COUNT [23:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_CRC_COUNT_WR_PASS_COUNT_MASK 0x00ff0000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_CRC_COUNT_WR_PASS_COUNT_SHIFT 16
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: EDC_CRC_COUNT :: RD_FAIL_COUNT [15:08] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_CRC_COUNT_RD_FAIL_COUNT_MASK 0x0000ff00
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_CRC_COUNT_RD_FAIL_COUNT_SHIFT 8
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: EDC_CRC_COUNT :: RD_PASS_COUNT [07:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_CRC_COUNT_RD_PASS_COUNT_MASK 0x000000ff
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_CRC_COUNT_RD_PASS_COUNT_SHIFT 0
-
-/***************************************************************************
- *EDC_CRC_STATUS_CLEAR - GDDR5M EDC signal path CRC counter register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_3_0 :: EDC_CRC_STATUS_CLEAR :: reserved0 [31:01] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_CRC_STATUS_CLEAR_reserved0_MASK 0xfffffffe
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_CRC_STATUS_CLEAR_reserved0_SHIFT 1
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: EDC_CRC_STATUS_CLEAR :: CLEAR [00:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_CRC_STATUS_CLEAR_CLEAR_MASK 0x00000001
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_CRC_STATUS_CLEAR_CLEAR_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_CRC_STATUS_CLEAR_CLEAR_DEFAULT 0x00000000
-
-/***************************************************************************
- *CLOCK_ENABLE - Clock Enable Register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_3_0 :: CLOCK_ENABLE :: reserved0 [31:03] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_CLOCK_ENABLE_reserved0_MASK 0xfffffff8
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_CLOCK_ENABLE_reserved0_SHIFT 3
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: CLOCK_ENABLE :: TO_MC_CLOCK [02:02] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_CLOCK_ENABLE_TO_MC_CLOCK_MASK 0x00000004
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_CLOCK_ENABLE_TO_MC_CLOCK_SHIFT 2
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_CLOCK_ENABLE_TO_MC_CLOCK_DEFAULT 0x00000001
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: CLOCK_ENABLE :: FROM_MC_CLOCK [01:01] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_CLOCK_ENABLE_FROM_MC_CLOCK_MASK 0x00000002
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_CLOCK_ENABLE_FROM_MC_CLOCK_SHIFT 1
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_CLOCK_ENABLE_FROM_MC_CLOCK_DEFAULT 0x00000001
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: CLOCK_ENABLE :: BIT_CLOCK [00:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_CLOCK_ENABLE_BIT_CLOCK_MASK 0x00000001
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_CLOCK_ENABLE_BIT_CLOCK_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_CLOCK_ENABLE_BIT_CLOCK_DEFAULT 0x00000001
-
-/***************************************************************************
- *CLOCK_IDLE - Clock Idle Register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_3_0 :: CLOCK_IDLE :: reserved0 [31:03] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_CLOCK_IDLE_reserved0_MASK 0xfffffff8
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_CLOCK_IDLE_reserved0_SHIFT 3
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: CLOCK_IDLE :: TO_MC_CLOCK [02:02] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_CLOCK_IDLE_TO_MC_CLOCK_MASK 0x00000004
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_CLOCK_IDLE_TO_MC_CLOCK_SHIFT 2
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_CLOCK_IDLE_TO_MC_CLOCK_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: CLOCK_IDLE :: FROM_MC_CLOCK [01:01] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_CLOCK_IDLE_FROM_MC_CLOCK_MASK 0x00000002
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_CLOCK_IDLE_FROM_MC_CLOCK_SHIFT 1
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_CLOCK_IDLE_FROM_MC_CLOCK_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: CLOCK_IDLE :: BIT_CLOCK [00:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_CLOCK_IDLE_BIT_CLOCK_MASK 0x00000001
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_CLOCK_IDLE_BIT_CLOCK_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_CLOCK_IDLE_BIT_CLOCK_DEFAULT 0x00000000
-
-/***************************************************************************
- *BL_SPARE_REG - Byte-Lane Spare register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_3_0 :: BL_SPARE_REG :: reserved_for_eco0 [31:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_BL_SPARE_REG_reserved_for_eco0_MASK 0xffffffff
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_BL_SPARE_REG_reserved_for_eco0_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_BL_SPARE_REG_reserved_for_eco0_DEFAULT 0x00000000
-
-#endif /* #ifndef BCHP_DDR34_PHY_BYTE_LANE_3_0_H__ */
-
-/* End of File */
diff --git a/include/linux/brcmstb/7366b0/bchp_ddr34_phy_control_regs_0.h b/include/linux/brcmstb/7366b0/bchp_ddr34_phy_control_regs_0.h
deleted file mode 100644
index 16463bb..0000000
--- a/include/linux/brcmstb/7366b0/bchp_ddr34_phy_control_regs_0.h
+++ /dev/null
@@ -1,4441 +0,0 @@
-/***************************************************************************
- * Copyright (c) 1999-2014, Broadcom Corporation
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
- *
- * Module Description:
- * DO NOT EDIT THIS FILE DIRECTLY
- *
- * This module was generated magically with RDB from a source description
- * file. You must edit the source file for changes to be made to this file.
- *
- *
- * Date: Generated on Thu Apr 24 03:08:55 2014
- * Full Compile MD5 Checksum 1af2c2cf28828ece5496e1312aac0166
- * (minus title and desc)
- * MD5 Checksum 3203ffce85e3fc9a10f84123e54057b0
- *
- * Compiled with: RDB Utility combo_header.pl
- * RDB Parser 3.0
- * unknown unknown
- * Perl Interpreter 5.008008
- * Operating System linux
- *
- * Revision History:
- *
- * $brcm_Log: $
- *
- ***************************************************************************/
-
-#ifndef BCHP_DDR34_PHY_CONTROL_REGS_0_H__
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_H__
-
-/***************************************************************************
- *DDR34_PHY_CONTROL_REGS_0 - DDR34 Address/Comand control registers
- ***************************************************************************/
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_REVISION 0x00506000 /* Address & Control revision register */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_STATUS 0x00506004 /* PHY PLL status register */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_CONFIG 0x00506008 /* PHY PLL configuration register */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_CONTROL1 0x0050600c /* PHY PLL control register */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_CONTROL2 0x00506010 /* PHY PLL control register */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_CONTROL3 0x00506014 /* PHY PLL control register */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_DIVIDERS 0x00506018 /* PHY PLL integer divider register */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_FRAC_DIVIDER 0x0050601c /* PHY PLL fractional divider register */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_SS_CONTROL 0x00506020 /* PHY PLL spread spectrum control register */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_SS_LIMIT 0x00506024 /* PHY PLL spread spectrum limit register */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_AUX_CONTROL 0x00506028 /* Aux Control register */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL 0x0050602c /* Idle mode pad control register */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_IDLE_PAD_ENABLE0 0x00506030 /* Idle mode pad enable register */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_IDLE_PAD_ENABLE1 0x00506034 /* Idle mode pad enable register */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL 0x00506038 /* Drive strength control for all pads except CK_P, CK_N, CS, ODT and PAR */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_2T 0x0050603c /* Drive strength control for signals that are 1T when in 2T mode -- CS, ODT and PAR */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_STATIC_PAD_CTL 0x00506040 /* pad rx and tx characteristics control register */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_STATIC_PAD_CTL_2T 0x00506044 /* pad rx and tx characteristics control register for signals that are 1T when in 2T mode -- CS, ODT and PAR */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_RX_TRIM 0x00506048 /* Receiver trim */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_DRAM_CONFIG 0x0050604c /* DRAM configuration register */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_DRAM_TIMING1 0x00506050 /* DRAM timing register #1 */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_DRAM_TIMING2 0x00506054 /* DRAM timing register #2 */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_DRAM_TIMING3 0x00506058 /* DRAM timing register #3 */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_DRAM_TIMING4 0x0050605c /* DRAM timing register #4 */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CALIBRATE 0x00506060 /* PHY VDL calibration control register */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS1 0x00506064 /* PHY VDL calibration status register #1 */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS2 0x00506068 /* PHY VDL calibration status register #2 */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_MONITOR_CONTROL 0x0050606c /* PHY VDL delay monitoring control register */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_MONITOR_REF 0x00506070 /* PHY VDL delay monitoring reference register */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_MONITOR_STATUS 0x00506074 /* PHY VDL delay monitoring status register */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_MONITOR_OVERRIDE 0x00506078 /* PHY VDL delay monitoring override register */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_MONITOR_OUT_CONTROL 0x0050607c /* PHY VDL delay monitoring output control register */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_MONITOR_OUT_STATUS 0x00506080 /* PHY VDL delay monitoring output status register */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_MONITOR_OUT_STATUS_CLEAR 0x00506084 /* PHY VDL delay monitoring output status clear register */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD00 0x00506088 /* DDR interface signal AD[00] VDL control register */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD01 0x0050608c /* DDR interface signal AD[01] VDL control register */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD02 0x00506090 /* DDR interface signal AD[02] VDL control register */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD03 0x00506094 /* DDR interface signal AD[03] VDL control register */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD04 0x00506098 /* DDR interface signal AD[04] VDL control register */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD05 0x0050609c /* DDR interface signal AD[05] VDL control register */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD06 0x005060a0 /* DDR interface signal AD[06] VDL control register */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD07 0x005060a4 /* DDR interface signal AD[07] VDL control register */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD08 0x005060a8 /* DDR interface signal AD[08] VDL control register */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD09 0x005060ac /* DDR interface signal AD[09] VDL control register */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD10 0x005060b0 /* DDR interface signal AD[10] VDL control register */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD11 0x005060b4 /* DDR interface signal AD[11] VDL control register */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD12 0x005060b8 /* DDR interface signal AD[12] VDL control register */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD13 0x005060bc /* DDR interface signal AD[13] VDL control register */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD14 0x005060c0 /* DDR interface signal AD[14] VDL control register */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD15 0x005060c4 /* DDR interface signal AD[15] VDL control register */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_BA0 0x005060c8 /* DDR interface signal BA[0] VDL control register */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_BA1 0x005060cc /* DDR interface signal BA[1] VDL control register */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_BA2 0x005060d0 /* DDR interface signal BA[2] VDL control register */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AUX0 0x005060d4 /* DDR interface signal AUX[0] VDL control register */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AUX1 0x005060d8 /* DDR interface signal AUX[1] VDL control register */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AUX2 0x005060dc /* DDR interface signal AUX[2] VDL control register */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_CS0 0x005060e0 /* DDR interface signal CS0 VDL control register */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_CS1 0x005060e4 /* DDR interface signal CS1 VDL control register */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_PAR 0x005060e8 /* DDR interface signal PAR VDL control register */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_RAS_N 0x005060ec /* DDR interface signal RAS_N VDL control register */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_CAS_N 0x005060f0 /* DDR interface signal CAS_N VDL control register */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_CKE 0x005060f4 /* DDR interface signal CKE0 VDL control register */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_RST_N 0x005060f8 /* DDR interface signal RST_N VDL control register */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_ODT 0x005060fc /* DDR interface signal ODT0 VDL control register */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_WE_N 0x00506100 /* DDR interface signal WE_N VDL control register */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_DDR_CK 0x00506104 /* DDR interface signal DDR_CK VDL control register */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CLK_CONTROL 0x00506108 /* DDR interface signal Write Leveling CLK VDL control register */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_LDE_CONTROL 0x0050610c /* DDR interface signal Write Leveling Capture Enable VDL control register */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_CMD_CYC_DLY 0x00506110 /* GDDR5 command interface delay stage control */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_UPDATE_VDL 0x00506114 /* Update VDL control register */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_UPDATE_VDL_SNOOP1 0x00506118 /* Update VDL snoop control register #1 */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_UPDATE_VDL_SNOOP2 0x0050611c /* Update VDL snoop control register #2 */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_REG1 0x00506120 /* DRAM Command Register #1 */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_AUX_REG1 0x00506124 /* DRAM AUX_N Command Register #1 */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_REG2 0x00506128 /* DRAM Command Register #2 */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_AUX_REG2 0x0050612c /* DRAM AUX_N Command Register #2 */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_REG3 0x00506130 /* DRAM Command Register #3 */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_AUX_REG3 0x00506134 /* DRAM AUX_N Command Register #3 */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_REG4 0x00506138 /* DRAM Command Register #4 */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_AUX_REG4 0x0050613c /* DRAM AUX_N Command Register #4 */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_REG_TIMER 0x00506140 /* DRAM Command Timer Register */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_MODE_REG0 0x00506144 /* DDR3/DDR4/GDDR5 Mode Register 0 and LPDDR Mode Register 1 */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_MODE_REG1 0x00506148 /* DDR3/DDR4/GDDR5 Mode Register 1 and LPDDR Mode Register 2 */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_MODE_REG2 0x0050614c /* DDR3/DDR4/GDDR5 Mode Register 2 and LPDDR Mode Register 3 */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_MODE_REG3 0x00506150 /* DDR3/DDR4/GDDR5 Mode Register 3 and LPDDR Mode Register 9 */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_MODE_REG4 0x00506154 /* DDR4/GDDR5 Mode Register 4 and LPDDR Mode Register 10 */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_MODE_REG5 0x00506158 /* DDR4/GDDR5 Mode Register 5 and LPDDR Mode Register 16 */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_MODE_REG6 0x0050615c /* DDR4/GDDR5 Mode Register 6 and LPDDR Mode Register 17 */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_MODE_REG7 0x00506160 /* DDR4/GDDR5 Mode Register 7 and LPDDR Mode Register 41 */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_MODE_REG8 0x00506164 /* GDDR5 Mode Register 8 and LPDDR Mode Register 42 */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_MODE_REG15 0x00506168 /* GDDR5 Mode Register 15 and LPDDR Mode Register 48 */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_MODE_REG63 0x0050616c /* LPDDR Mode Register 63 */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_ALERT_CLEAR 0x00506170 /* DDR4 Alert status clear register */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_ALERT_STATUS 0x00506174 /* DDR4 Alert status register */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_ALERT_DFI 0x00506178 /* DDR4 Alert DFI BL mask */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_CA_PLAYBACK_CONTROL 0x0050617c /* GDDR5 CA playback control register */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_CA_PLAYBACK_STATUS0 0x00506180 /* LPDDR3 and GDDR5 CA playback status register0 (for BL0 and BL1) */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_CA_PLAYBACK_STATUS1 0x00506184 /* LPDDR3 and GDDR5 CA playback status register1 (for BL2 and BL3) */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_WRITE_LEVELING_CONTROL 0x00506188 /* Write leveling control register */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_WRITE_LEVELING_STATUS 0x0050618c /* Write leveling status register */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_READ_ENABLE_CONTROL 0x00506190 /* Read enable test cycle control register */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_READ_ENABLE_STATUS 0x00506194 /* Read enable test cycle status register */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONTROL 0x00506198 /* Virtual VTT Control and Status register */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VIRTUAL_VTT_STATUS 0x0050619c /* Virtual VTT Control and Status register */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONNECTIONS 0x005061a0 /* Virtual VTT Connections register */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VIRTUAL_VTT_OVERRIDE 0x005061a4 /* Virtual VTT Override register */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL 0x005061a8 /* VREF DAC Control register */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PHYBIST_CNTRL 0x005061ac /* PhyBist Control Register */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PHYBIST_SEED 0x005061b0 /* PhyBist Seed Register */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PHYBIST_CA_MASK 0x005061b4 /* PhyBist Command/Address Bus Mask */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PHYBIST_DQ_MASK1 0x005061b8 /* PhyBist Data Bus Mask #1 */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PHYBIST_DQ_MASK2 0x005061bc /* PhyBist Data Bus Mask #2 */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PHYBIST_STATUS 0x005061c0 /* PhyBist General Status Register */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PHYBIST_CTL_STATUS 0x005061c4 /* PhyBist Per-Bit Control Pad Status Register */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PHYBIST_BL0_STATUS 0x005061c8 /* PhyBist Byte Lane #0 Status Register */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PHYBIST_BL1_STATUS 0x005061cc /* PhyBist Byte Lane #1 Status Register */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PHYBIST_BL2_STATUS 0x005061d0 /* PhyBist Byte Lane #2 Status Register */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PHYBIST_BL3_STATUS 0x005061d4 /* PhyBist Byte Lane #3 Status Register */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PHYBIST_BL4_STATUS 0x005061d8 /* PhyBist Byte Lane #4 (ECC) Status Register */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_STANDBY_CONTROL 0x005061dc /* Standby Control register */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_DEBUG_FREEZE_ENABLE 0x005061e0 /* Freeze-on-error enable register */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_DEBUG_MUX_CONTROL 0x005061e4 /* Debug Mux Control register */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_DFI_CNTRL 0x005061e8 /* DFI Interface Ownership Control register */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_WRITE_ODT_CNTRL 0x005061ec /* Write ODT Control register */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_ABI_PAR_CNTRL 0x005061f0 /* ABI and PAR Control register */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_ZQ_CAL 0x005061f4 /* ZQ Calibration Control register */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_ZQ_CAL2 0x005061f8 /* ZQ Calibration Control register */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMR_CAL 0x005061fc /* COMR Calibration Control register */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_RO_PROC_MON_CTL 0x00506200 /* Ring-Osc control register */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_RO_PROC_MON_STATUS 0x00506204 /* Ring-Osc count register */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_CK_DRIVE_PAD_CTL 0x00506208 /* Drive strength control register for CK_P and CK_N */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_LDO_COMP_CONTROL 0x0050620c /* LDO Comparator Control register */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_BYTE_LANE_ALIGN_MASKS 0x00506210 /* Byte-lane alignment mask register */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_CLOCK_IDLE 0x00506214 /* Clock Idle Register */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_AC_SPARE_REG 0x00506218 /* Address and Control Spare register */
-
-/***************************************************************************
- *REVISION - Address & Control revision register
- ***************************************************************************/
-/* DDR34_PHY_CONTROL_REGS_0 :: REVISION :: reserved0 [31:25] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_REVISION_reserved0_MASK 0xfe000000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_REVISION_reserved0_SHIFT 25
-
-/* DDR34_PHY_CONTROL_REGS_0 :: REVISION :: PERFORMANCE [24:23] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_REVISION_PERFORMANCE_MASK 0x01800000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_REVISION_PERFORMANCE_SHIFT 23
-
-/* DDR34_PHY_CONTROL_REGS_0 :: REVISION :: TECHNOLOGY [22:20] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_REVISION_TECHNOLOGY_MASK 0x00700000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_REVISION_TECHNOLOGY_SHIFT 20
-
-/* DDR34_PHY_CONTROL_REGS_0 :: REVISION :: WB [19:19] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_REVISION_WB_MASK 0x00080000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_REVISION_WB_SHIFT 19
-
-/* DDR34_PHY_CONTROL_REGS_0 :: REVISION :: BITS [18:16] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_REVISION_BITS_MASK 0x00070000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_REVISION_BITS_SHIFT 16
-
-/* DDR34_PHY_CONTROL_REGS_0 :: REVISION :: MAJOR [15:08] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_REVISION_MAJOR_MASK 0x0000ff00
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_REVISION_MAJOR_SHIFT 8
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_REVISION_MAJOR_DEFAULT 0x000000f0
-
-/* DDR34_PHY_CONTROL_REGS_0 :: REVISION :: MINOR [07:00] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_REVISION_MINOR_MASK 0x000000ff
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_REVISION_MINOR_SHIFT 0
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_REVISION_MINOR_DEFAULT 0x00000002
-
-/***************************************************************************
- *PLL_STATUS - PHY PLL status register
- ***************************************************************************/
-/* DDR34_PHY_CONTROL_REGS_0 :: PLL_STATUS :: reserved0 [31:17] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_STATUS_reserved0_MASK 0xfffe0000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_STATUS_reserved0_SHIFT 17
-
-/* DDR34_PHY_CONTROL_REGS_0 :: PLL_STATUS :: LOCK_LOST [16:16] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_STATUS_LOCK_LOST_MASK 0x00010000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_STATUS_LOCK_LOST_SHIFT 16
-
-/* DDR34_PHY_CONTROL_REGS_0 :: PLL_STATUS :: CLOCKING_8X [15:15] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_STATUS_CLOCKING_8X_MASK 0x00008000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_STATUS_CLOCKING_8X_SHIFT 15
-
-/* DDR34_PHY_CONTROL_REGS_0 :: PLL_STATUS :: CLOCKING_4X [14:14] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_STATUS_CLOCKING_4X_MASK 0x00004000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_STATUS_CLOCKING_4X_SHIFT 14
-
-/* DDR34_PHY_CONTROL_REGS_0 :: PLL_STATUS :: CLOCKING_2X [13:13] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_STATUS_CLOCKING_2X_MASK 0x00002000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_STATUS_CLOCKING_2X_SHIFT 13
-
-/* DDR34_PHY_CONTROL_REGS_0 :: PLL_STATUS :: STATUS [12:01] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_STATUS_STATUS_MASK 0x00001ffe
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_STATUS_STATUS_SHIFT 1
-
-/* DDR34_PHY_CONTROL_REGS_0 :: PLL_STATUS :: LOCK [00:00] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_STATUS_LOCK_MASK 0x00000001
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_STATUS_LOCK_SHIFT 0
-
-/***************************************************************************
- *PLL_CONFIG - PHY PLL configuration register
- ***************************************************************************/
-/* DDR34_PHY_CONTROL_REGS_0 :: PLL_CONFIG :: PLL_LDO_DVDD1P0V_OUTPUT_V [31:30] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_CONFIG_PLL_LDO_DVDD1P0V_OUTPUT_V_MASK 0xc0000000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_CONFIG_PLL_LDO_DVDD1P0V_OUTPUT_V_SHIFT 30
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_CONFIG_PLL_LDO_DVDD1P0V_OUTPUT_V_DEFAULT 0x00000001
-
-/* DDR34_PHY_CONTROL_REGS_0 :: PLL_CONFIG :: PLL_LDO_AVDD1P0V_OUTPUT_V [29:28] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_CONFIG_PLL_LDO_AVDD1P0V_OUTPUT_V_MASK 0x30000000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_CONFIG_PLL_LDO_AVDD1P0V_OUTPUT_V_SHIFT 28
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_CONFIG_PLL_LDO_AVDD1P0V_OUTPUT_V_DEFAULT 0x00000001
-
-/* DDR34_PHY_CONTROL_REGS_0 :: PLL_CONFIG :: PLL_LDO_DVDD1P0V_BLEEDING_I [27:26] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_CONFIG_PLL_LDO_DVDD1P0V_BLEEDING_I_MASK 0x0c000000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_CONFIG_PLL_LDO_DVDD1P0V_BLEEDING_I_SHIFT 26
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_CONFIG_PLL_LDO_DVDD1P0V_BLEEDING_I_DEFAULT 0x00000001
-
-/* DDR34_PHY_CONTROL_REGS_0 :: PLL_CONFIG :: PLL_LDO_AVDD1P0V_BLEEDING_I [25:24] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_CONFIG_PLL_LDO_AVDD1P0V_BLEEDING_I_MASK 0x03000000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_CONFIG_PLL_LDO_AVDD1P0V_BLEEDING_I_SHIFT 24
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_CONFIG_PLL_LDO_AVDD1P0V_BLEEDING_I_DEFAULT 0x00000001
-
-/* DDR34_PHY_CONTROL_REGS_0 :: PLL_CONFIG :: CK_LDO_PWRDOWN [23:23] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_CONFIG_CK_LDO_PWRDOWN_MASK 0x00800000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_CONFIG_CK_LDO_PWRDOWN_SHIFT 23
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_CONFIG_CK_LDO_PWRDOWN_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: PLL_CONFIG :: CK_LDO_BIAS20 [22:21] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_CONFIG_CK_LDO_BIAS20_MASK 0x00600000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_CONFIG_CK_LDO_BIAS20_SHIFT 21
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_CONFIG_CK_LDO_BIAS20_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: PLL_CONFIG :: CK_LDO_BIAS [20:19] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_CONFIG_CK_LDO_BIAS_MASK 0x00180000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_CONFIG_CK_LDO_BIAS_SHIFT 19
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_CONFIG_CK_LDO_BIAS_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: PLL_CONFIG :: PLL_LDO_PWRDOWN [18:18] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_CONFIG_PLL_LDO_PWRDOWN_MASK 0x00040000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_CONFIG_PLL_LDO_PWRDOWN_SHIFT 18
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_CONFIG_PLL_LDO_PWRDOWN_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: PLL_CONFIG :: HOLD [17:17] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_CONFIG_HOLD_MASK 0x00020000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_CONFIG_HOLD_SHIFT 17
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_CONFIG_HOLD_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: PLL_CONFIG :: ENABLE [16:16] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_CONFIG_ENABLE_MASK 0x00010000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_CONFIG_ENABLE_SHIFT 16
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_CONFIG_ENABLE_DEFAULT 0x00000001
-
-/* DDR34_PHY_CONTROL_REGS_0 :: PLL_CONFIG :: reserved0 [15:14] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_CONFIG_reserved0_MASK 0x0000c000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_CONFIG_reserved0_SHIFT 14
-
-/* DDR34_PHY_CONTROL_REGS_0 :: PLL_CONFIG :: FB_OFFSET [13:08] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_CONFIG_FB_OFFSET_MASK 0x00003f00
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_CONFIG_FB_OFFSET_SHIFT 8
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_CONFIG_FB_OFFSET_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: PLL_CONFIG :: reserved1 [07:06] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_CONFIG_reserved1_MASK 0x000000c0
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_CONFIG_reserved1_SHIFT 6
-
-/* DDR34_PHY_CONTROL_REGS_0 :: PLL_CONFIG :: ENABLE_EXT_CTRL [05:05] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_CONFIG_ENABLE_EXT_CTRL_MASK 0x00000020
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_CONFIG_ENABLE_EXT_CTRL_SHIFT 5
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_CONFIG_ENABLE_EXT_CTRL_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: PLL_CONFIG :: RESET_POST_DIV [04:04] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_CONFIG_RESET_POST_DIV_MASK 0x00000010
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_CONFIG_RESET_POST_DIV_SHIFT 4
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_CONFIG_RESET_POST_DIV_DEFAULT 0x00000001
-
-/* DDR34_PHY_CONTROL_REGS_0 :: PLL_CONFIG :: ISO_OUT [03:03] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_CONFIG_ISO_OUT_MASK 0x00000008
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_CONFIG_ISO_OUT_SHIFT 3
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_CONFIG_ISO_OUT_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: PLL_CONFIG :: ISO_IN [02:02] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_CONFIG_ISO_IN_MASK 0x00000004
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_CONFIG_ISO_IN_SHIFT 2
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_CONFIG_ISO_IN_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: PLL_CONFIG :: RESET [01:01] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_CONFIG_RESET_MASK 0x00000002
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_CONFIG_RESET_SHIFT 1
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_CONFIG_RESET_DEFAULT 0x00000001
-
-/* DDR34_PHY_CONTROL_REGS_0 :: PLL_CONFIG :: PWRDN [00:00] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_CONFIG_PWRDN_MASK 0x00000001
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_CONFIG_PWRDN_SHIFT 0
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_CONFIG_PWRDN_DEFAULT 0x00000001
-
-/***************************************************************************
- *PLL_CONTROL1 - PHY PLL control register
- ***************************************************************************/
-/* DDR34_PHY_CONTROL_REGS_0 :: PLL_CONTROL1 :: reserved0 [31:10] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_CONTROL1_reserved0_MASK 0xfffffc00
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_CONTROL1_reserved0_SHIFT 10
-
-/* DDR34_PHY_CONTROL_REGS_0 :: PLL_CONTROL1 :: I_KP [09:06] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_CONTROL1_I_KP_MASK 0x000003c0
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_CONTROL1_I_KP_SHIFT 6
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_CONTROL1_I_KP_DEFAULT 0x00000008
-
-/* DDR34_PHY_CONTROL_REGS_0 :: PLL_CONTROL1 :: I_KI [05:03] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_CONTROL1_I_KI_MASK 0x00000038
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_CONTROL1_I_KI_SHIFT 3
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_CONTROL1_I_KI_DEFAULT 0x00000004
-
-/* DDR34_PHY_CONTROL_REGS_0 :: PLL_CONTROL1 :: I_KA [02:00] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_CONTROL1_I_KA_MASK 0x00000007
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_CONTROL1_I_KA_SHIFT 0
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_CONTROL1_I_KA_DEFAULT 0x00000000
-
-/***************************************************************************
- *PLL_CONTROL2 - PHY PLL control register
- ***************************************************************************/
-/* DDR34_PHY_CONTROL_REGS_0 :: PLL_CONTROL2 :: REF_ALT_OFFS [31:31] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_CONTROL2_REF_ALT_OFFS_MASK 0x80000000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_CONTROL2_REF_ALT_OFFS_SHIFT 31
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_CONTROL2_REF_ALT_OFFS_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: PLL_CONTROL2 :: VCO_RANGE_CONTROL_FOR_LOW [30:30] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_CONTROL2_VCO_RANGE_CONTROL_FOR_LOW_MASK 0x40000000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_CONTROL2_VCO_RANGE_CONTROL_FOR_LOW_SHIFT 30
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_CONTROL2_VCO_RANGE_CONTROL_FOR_LOW_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: PLL_CONTROL2 :: AUX_CTRL [29:29] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_CONTROL2_AUX_CTRL_MASK 0x20000000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_CONTROL2_AUX_CTRL_SHIFT 29
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_CONTROL2_AUX_CTRL_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: PLL_CONTROL2 :: NDIV_RELOCK [28:28] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_CONTROL2_NDIV_RELOCK_MASK 0x10000000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_CONTROL2_NDIV_RELOCK_SHIFT 28
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_CONTROL2_NDIV_RELOCK_DEFAULT 0x00000001
-
-/* DDR34_PHY_CONTROL_REGS_0 :: PLL_CONTROL2 :: FAST_LOCK [27:27] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_CONTROL2_FAST_LOCK_MASK 0x08000000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_CONTROL2_FAST_LOCK_SHIFT 27
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_CONTROL2_FAST_LOCK_DEFAULT 0x00000001
-
-/* DDR34_PHY_CONTROL_REGS_0 :: PLL_CONTROL2 :: VCO_FB_DIV2 [26:26] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_CONTROL2_VCO_FB_DIV2_MASK 0x04000000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_CONTROL2_VCO_FB_DIV2_SHIFT 26
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_CONTROL2_VCO_FB_DIV2_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: PLL_CONTROL2 :: POST_CTRL_RESETB [25:24] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_CONTROL2_POST_CTRL_RESETB_MASK 0x03000000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_CONTROL2_POST_CTRL_RESETB_SHIFT 24
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_CONTROL2_POST_CTRL_RESETB_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: PLL_CONTROL2 :: PWM_RATE [23:22] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_CONTROL2_PWM_RATE_MASK 0x00c00000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_CONTROL2_PWM_RATE_SHIFT 22
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_CONTROL2_PWM_RATE_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: PLL_CONTROL2 :: STAT_MODE [21:20] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_CONTROL2_STAT_MODE_MASK 0x00300000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_CONTROL2_STAT_MODE_SHIFT 20
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_CONTROL2_STAT_MODE_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: PLL_CONTROL2 :: VCO_RANGE_CONTROL_FOR_HIGH [19:19] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_CONTROL2_VCO_RANGE_CONTROL_FOR_HIGH_MASK 0x00080000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_CONTROL2_VCO_RANGE_CONTROL_FOR_HIGH_SHIFT 19
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_CONTROL2_VCO_RANGE_CONTROL_FOR_HIGH_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: PLL_CONTROL2 :: DITHER_DISABLE [18:18] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_CONTROL2_DITHER_DISABLE_MASK 0x00040000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_CONTROL2_DITHER_DISABLE_SHIFT 18
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_CONTROL2_DITHER_DISABLE_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: PLL_CONTROL2 :: STAT_UPDATE [17:17] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_CONTROL2_STAT_UPDATE_MASK 0x00020000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_CONTROL2_STAT_UPDATE_SHIFT 17
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_CONTROL2_STAT_UPDATE_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: PLL_CONTROL2 :: STAT_SELECT [16:14] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_CONTROL2_STAT_SELECT_MASK 0x0001c000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_CONTROL2_STAT_SELECT_SHIFT 14
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_CONTROL2_STAT_SELECT_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: PLL_CONTROL2 :: STAT_RESET [13:13] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_CONTROL2_STAT_RESET_MASK 0x00002000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_CONTROL2_STAT_RESET_SHIFT 13
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_CONTROL2_STAT_RESET_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: PLL_CONTROL2 :: DCO_CTRL_BYPASS_ENABLE [12:12] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_CONTROL2_DCO_CTRL_BYPASS_ENABLE_MASK 0x00001000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_CONTROL2_DCO_CTRL_BYPASS_ENABLE_SHIFT 12
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_CONTROL2_DCO_CTRL_BYPASS_ENABLE_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: PLL_CONTROL2 :: DCO_CTRL_BYP [11:00] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_CONTROL2_DCO_CTRL_BYP_MASK 0x00000fff
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_CONTROL2_DCO_CTRL_BYP_SHIFT 0
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_CONTROL2_DCO_CTRL_BYP_DEFAULT 0x00000000
-
-/***************************************************************************
- *PLL_CONTROL3 - PHY PLL control register
- ***************************************************************************/
-/* DDR34_PHY_CONTROL_REGS_0 :: PLL_CONTROL3 :: PLL_CONTROL [31:00] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_CONTROL3_PLL_CONTROL_MASK 0xffffffff
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_CONTROL3_PLL_CONTROL_SHIFT 0
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_CONTROL3_PLL_CONTROL_DEFAULT 0x00000000
-
-/***************************************************************************
- *PLL_DIVIDERS - PHY PLL integer divider register
- ***************************************************************************/
-/* DDR34_PHY_CONTROL_REGS_0 :: PLL_DIVIDERS :: reserved0 [31:28] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_DIVIDERS_reserved0_MASK 0xf0000000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_DIVIDERS_reserved0_SHIFT 28
-
-/* DDR34_PHY_CONTROL_REGS_0 :: PLL_DIVIDERS :: MDIV [27:20] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_DIVIDERS_MDIV_MASK 0x0ff00000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_DIVIDERS_MDIV_SHIFT 20
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_DIVIDERS_MDIV_DEFAULT 0x00000004
-
-/* DDR34_PHY_CONTROL_REGS_0 :: PLL_DIVIDERS :: reserved1 [19:16] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_DIVIDERS_reserved1_MASK 0x000f0000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_DIVIDERS_reserved1_SHIFT 16
-
-/* DDR34_PHY_CONTROL_REGS_0 :: PLL_DIVIDERS :: PDIV [15:12] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_DIVIDERS_PDIV_MASK 0x0000f000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_DIVIDERS_PDIV_SHIFT 12
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_DIVIDERS_PDIV_DEFAULT 0x00000001
-
-/* DDR34_PHY_CONTROL_REGS_0 :: PLL_DIVIDERS :: reserved2 [11:10] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_DIVIDERS_reserved2_MASK 0x00000c00
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_DIVIDERS_reserved2_SHIFT 10
-
-/* DDR34_PHY_CONTROL_REGS_0 :: PLL_DIVIDERS :: NDIV_INT [09:00] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_DIVIDERS_NDIV_INT_MASK 0x000003ff
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_DIVIDERS_NDIV_INT_SHIFT 0
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_DIVIDERS_NDIV_INT_DEFAULT 0x00000020
-
-/***************************************************************************
- *PLL_FRAC_DIVIDER - PHY PLL fractional divider register
- ***************************************************************************/
-/* DDR34_PHY_CONTROL_REGS_0 :: PLL_FRAC_DIVIDER :: reserved0 [31:20] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_FRAC_DIVIDER_reserved0_MASK 0xfff00000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_FRAC_DIVIDER_reserved0_SHIFT 20
-
-/* DDR34_PHY_CONTROL_REGS_0 :: PLL_FRAC_DIVIDER :: NDIV_FRAC [19:00] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_FRAC_DIVIDER_NDIV_FRAC_MASK 0x000fffff
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_FRAC_DIVIDER_NDIV_FRAC_SHIFT 0
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_FRAC_DIVIDER_NDIV_FRAC_DEFAULT 0x00000000
-
-/***************************************************************************
- *PLL_SS_CONTROL - PHY PLL spread spectrum control register
- ***************************************************************************/
-/* DDR34_PHY_CONTROL_REGS_0 :: PLL_SS_CONTROL :: reserved0 [31:20] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_SS_CONTROL_reserved0_MASK 0xfff00000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_SS_CONTROL_reserved0_SHIFT 20
-
-/* DDR34_PHY_CONTROL_REGS_0 :: PLL_SS_CONTROL :: SSC_STEP [19:04] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_SS_CONTROL_SSC_STEP_MASK 0x000ffff0
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_SS_CONTROL_SSC_STEP_SHIFT 4
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_SS_CONTROL_SSC_STEP_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: PLL_SS_CONTROL :: reserved1 [03:01] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_SS_CONTROL_reserved1_MASK 0x0000000e
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_SS_CONTROL_reserved1_SHIFT 1
-
-/* DDR34_PHY_CONTROL_REGS_0 :: PLL_SS_CONTROL :: SSC_MODE [00:00] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_SS_CONTROL_SSC_MODE_MASK 0x00000001
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_SS_CONTROL_SSC_MODE_SHIFT 0
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_SS_CONTROL_SSC_MODE_DEFAULT 0x00000000
-
-/***************************************************************************
- *PLL_SS_LIMIT - PHY PLL spread spectrum limit register
- ***************************************************************************/
-/* DDR34_PHY_CONTROL_REGS_0 :: PLL_SS_LIMIT :: reserved0 [31:26] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_SS_LIMIT_reserved0_MASK 0xfc000000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_SS_LIMIT_reserved0_SHIFT 26
-
-/* DDR34_PHY_CONTROL_REGS_0 :: PLL_SS_LIMIT :: SSC_LIMIT [25:04] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_SS_LIMIT_SSC_LIMIT_MASK 0x03fffff0
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_SS_LIMIT_SSC_LIMIT_SHIFT 4
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_SS_LIMIT_SSC_LIMIT_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: PLL_SS_LIMIT :: reserved1 [03:00] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_SS_LIMIT_reserved1_MASK 0x0000000f
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_SS_LIMIT_reserved1_SHIFT 0
-
-/***************************************************************************
- *AUX_CONTROL - Aux Control register
- ***************************************************************************/
-/* DDR34_PHY_CONTROL_REGS_0 :: AUX_CONTROL :: reserved0 [31:05] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_AUX_CONTROL_reserved0_MASK 0xffffffe0
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_AUX_CONTROL_reserved0_SHIFT 5
-
-/* DDR34_PHY_CONTROL_REGS_0 :: AUX_CONTROL :: AUX0_IS_ODT [04:04] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_AUX_CONTROL_AUX0_IS_ODT_MASK 0x00000010
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_AUX_CONTROL_AUX0_IS_ODT_SHIFT 4
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_AUX_CONTROL_AUX0_IS_ODT_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: AUX_CONTROL :: PAR_IS_ODT [03:03] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_AUX_CONTROL_PAR_IS_ODT_MASK 0x00000008
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_AUX_CONTROL_PAR_IS_ODT_SHIFT 3
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_AUX_CONTROL_PAR_IS_ODT_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: AUX_CONTROL :: IS_CS [02:00] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_AUX_CONTROL_IS_CS_MASK 0x00000007
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_AUX_CONTROL_IS_CS_SHIFT 0
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_AUX_CONTROL_IS_CS_DEFAULT 0x00000000
-
-/***************************************************************************
- *IDLE_PAD_CONTROL - Idle mode pad control register
- ***************************************************************************/
-/* DDR34_PHY_CONTROL_REGS_0 :: IDLE_PAD_CONTROL :: IDLE [31:31] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_IDLE_MASK 0x80000000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_IDLE_SHIFT 31
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_IDLE_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: IDLE_PAD_CONTROL :: DIB_MODE [30:30] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_DIB_MODE_MASK 0x40000000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_DIB_MODE_SHIFT 30
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_DIB_MODE_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: IDLE_PAD_CONTROL :: reserved0 [29:08] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_reserved0_MASK 0x3fffff00
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_reserved0_SHIFT 8
-
-/* DDR34_PHY_CONTROL_REGS_0 :: IDLE_PAD_CONTROL :: reserved_for_eco1 [07:04] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_reserved_for_eco1_MASK 0x000000f0
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_reserved_for_eco1_SHIFT 4
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_reserved_for_eco1_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: IDLE_PAD_CONTROL :: RXENB [03:03] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_RXENB_MASK 0x00000008
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_RXENB_SHIFT 3
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_RXENB_DEFAULT 0x00000001
-
-/* DDR34_PHY_CONTROL_REGS_0 :: IDLE_PAD_CONTROL :: IDDQ [02:02] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_IDDQ_MASK 0x00000004
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_IDDQ_SHIFT 2
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_IDDQ_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: IDLE_PAD_CONTROL :: DOUT_N [01:01] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_DOUT_N_MASK 0x00000002
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_DOUT_N_SHIFT 1
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_DOUT_N_DEFAULT 0x00000001
-
-/* DDR34_PHY_CONTROL_REGS_0 :: IDLE_PAD_CONTROL :: DOUT_P [00:00] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_DOUT_P_MASK 0x00000001
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_DOUT_P_SHIFT 0
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_DOUT_P_DEFAULT 0x00000000
-
-/***************************************************************************
- *IDLE_PAD_ENABLE0 - Idle mode pad enable register
- ***************************************************************************/
-/* DDR34_PHY_CONTROL_REGS_0 :: IDLE_PAD_ENABLE0 :: reserved0 [31:11] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_IDLE_PAD_ENABLE0_reserved0_MASK 0xfffff800
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_IDLE_PAD_ENABLE0_reserved0_SHIFT 11
-
-/* DDR34_PHY_CONTROL_REGS_0 :: IDLE_PAD_ENABLE0 :: IO_IDLE_ENABLE [10:00] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_IDLE_PAD_ENABLE0_IO_IDLE_ENABLE_MASK 0x000007ff
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_IDLE_PAD_ENABLE0_IO_IDLE_ENABLE_SHIFT 0
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_IDLE_PAD_ENABLE0_IO_IDLE_ENABLE_DEFAULT 0x00000000
-
-/***************************************************************************
- *IDLE_PAD_ENABLE1 - Idle mode pad enable register
- ***************************************************************************/
-/* DDR34_PHY_CONTROL_REGS_0 :: IDLE_PAD_ENABLE1 :: reserved0 [31:22] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_IDLE_PAD_ENABLE1_reserved0_MASK 0xffc00000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_IDLE_PAD_ENABLE1_reserved0_SHIFT 22
-
-/* DDR34_PHY_CONTROL_REGS_0 :: IDLE_PAD_ENABLE1 :: IO_IDLE_ENABLE [21:00] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_IDLE_PAD_ENABLE1_IO_IDLE_ENABLE_MASK 0x003fffff
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_IDLE_PAD_ENABLE1_IO_IDLE_ENABLE_SHIFT 0
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_IDLE_PAD_ENABLE1_IO_IDLE_ENABLE_DEFAULT 0x00000000
-
-/***************************************************************************
- *DRIVE_PAD_CTL - Drive strength control for all pads except CK_P, CK_N, CS, ODT and PAR
- ***************************************************************************/
-/* DDR34_PHY_CONTROL_REGS_0 :: DRIVE_PAD_CTL :: reserved0 [31:30] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_reserved0_MASK 0xc0000000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_reserved0_SHIFT 30
-
-/* DDR34_PHY_CONTROL_REGS_0 :: DRIVE_PAD_CTL :: ADDR_CTL_PD_IDLE_STRENGTH [29:25] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_ADDR_CTL_PD_IDLE_STRENGTH_MASK 0x3e000000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_ADDR_CTL_PD_IDLE_STRENGTH_SHIFT 25
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_ADDR_CTL_PD_IDLE_STRENGTH_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: DRIVE_PAD_CTL :: ADDR_CTL_ND_IDLE_STRENGTH [24:20] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_ADDR_CTL_ND_IDLE_STRENGTH_MASK 0x01f00000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_ADDR_CTL_ND_IDLE_STRENGTH_SHIFT 20
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_ADDR_CTL_ND_IDLE_STRENGTH_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: DRIVE_PAD_CTL :: ADDR_CTL_PD_TERM_STRENGTH [19:15] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_ADDR_CTL_PD_TERM_STRENGTH_MASK 0x000f8000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_ADDR_CTL_PD_TERM_STRENGTH_SHIFT 15
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_ADDR_CTL_PD_TERM_STRENGTH_DEFAULT 0x00000008
-
-/* DDR34_PHY_CONTROL_REGS_0 :: DRIVE_PAD_CTL :: ADDR_CTL_ND_TERM_STRENGTH [14:10] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_ADDR_CTL_ND_TERM_STRENGTH_MASK 0x00007c00
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_ADDR_CTL_ND_TERM_STRENGTH_SHIFT 10
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_ADDR_CTL_ND_TERM_STRENGTH_DEFAULT 0x00000008
-
-/* DDR34_PHY_CONTROL_REGS_0 :: DRIVE_PAD_CTL :: ADDR_CTL_PD_STRENGTH [09:05] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_ADDR_CTL_PD_STRENGTH_MASK 0x000003e0
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_ADDR_CTL_PD_STRENGTH_SHIFT 5
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_ADDR_CTL_PD_STRENGTH_DEFAULT 0x00000010
-
-/* DDR34_PHY_CONTROL_REGS_0 :: DRIVE_PAD_CTL :: ADDR_CTL_ND_STRENGTH [04:00] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_ADDR_CTL_ND_STRENGTH_MASK 0x0000001f
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_ADDR_CTL_ND_STRENGTH_SHIFT 0
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_ADDR_CTL_ND_STRENGTH_DEFAULT 0x00000010
-
-/***************************************************************************
- *DRIVE_PAD_CTL_2T - Drive strength control for signals that are 1T when in 2T mode -- CS, ODT and PAR
- ***************************************************************************/
-/* DDR34_PHY_CONTROL_REGS_0 :: DRIVE_PAD_CTL_2T :: reserved0 [31:30] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_2T_reserved0_MASK 0xc0000000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_2T_reserved0_SHIFT 30
-
-/* DDR34_PHY_CONTROL_REGS_0 :: DRIVE_PAD_CTL_2T :: PD_IDLE_STRENGTH [29:25] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_2T_PD_IDLE_STRENGTH_MASK 0x3e000000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_2T_PD_IDLE_STRENGTH_SHIFT 25
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_2T_PD_IDLE_STRENGTH_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: DRIVE_PAD_CTL_2T :: ND_IDLE_STRENGTH [24:20] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_2T_ND_IDLE_STRENGTH_MASK 0x01f00000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_2T_ND_IDLE_STRENGTH_SHIFT 20
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_2T_ND_IDLE_STRENGTH_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: DRIVE_PAD_CTL_2T :: PD_TERM_STRENGTH [19:15] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_2T_PD_TERM_STRENGTH_MASK 0x000f8000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_2T_PD_TERM_STRENGTH_SHIFT 15
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_2T_PD_TERM_STRENGTH_DEFAULT 0x00000008
-
-/* DDR34_PHY_CONTROL_REGS_0 :: DRIVE_PAD_CTL_2T :: ND_TERM_STRENGTH [14:10] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_2T_ND_TERM_STRENGTH_MASK 0x00007c00
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_2T_ND_TERM_STRENGTH_SHIFT 10
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_2T_ND_TERM_STRENGTH_DEFAULT 0x00000008
-
-/* DDR34_PHY_CONTROL_REGS_0 :: DRIVE_PAD_CTL_2T :: PD_STRENGTH [09:05] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_2T_PD_STRENGTH_MASK 0x000003e0
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_2T_PD_STRENGTH_SHIFT 5
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_2T_PD_STRENGTH_DEFAULT 0x00000010
-
-/* DDR34_PHY_CONTROL_REGS_0 :: DRIVE_PAD_CTL_2T :: ND_STRENGTH [04:00] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_2T_ND_STRENGTH_MASK 0x0000001f
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_2T_ND_STRENGTH_SHIFT 0
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_2T_ND_STRENGTH_DEFAULT 0x00000010
-
-/***************************************************************************
- *STATIC_PAD_CTL - pad rx and tx characteristics control register
- ***************************************************************************/
-/* DDR34_PHY_CONTROL_REGS_0 :: STATIC_PAD_CTL :: reserved0 [31:31] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_STATIC_PAD_CTL_reserved0_MASK 0x80000000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_STATIC_PAD_CTL_reserved0_SHIFT 31
-
-/* DDR34_PHY_CONTROL_REGS_0 :: STATIC_PAD_CTL :: TX_SLEW [30:29] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_STATIC_PAD_CTL_TX_SLEW_MASK 0x60000000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_STATIC_PAD_CTL_TX_SLEW_SHIFT 29
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_STATIC_PAD_CTL_TX_SLEW_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: STATIC_PAD_CTL :: AUTO_OEB [28:28] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_STATIC_PAD_CTL_AUTO_OEB_MASK 0x10000000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_STATIC_PAD_CTL_AUTO_OEB_SHIFT 28
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_STATIC_PAD_CTL_AUTO_OEB_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: STATIC_PAD_CTL :: IDDQ_GDDR5 [27:27] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_STATIC_PAD_CTL_IDDQ_GDDR5_MASK 0x08000000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_STATIC_PAD_CTL_IDDQ_GDDR5_SHIFT 27
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_STATIC_PAD_CTL_IDDQ_GDDR5_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: STATIC_PAD_CTL :: IDDQ_LPDDR [26:26] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_STATIC_PAD_CTL_IDDQ_LPDDR_MASK 0x04000000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_STATIC_PAD_CTL_IDDQ_LPDDR_SHIFT 26
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_STATIC_PAD_CTL_IDDQ_LPDDR_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: STATIC_PAD_CTL :: IDDQ_CLK0 [25:25] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_STATIC_PAD_CTL_IDDQ_CLK0_MASK 0x02000000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_STATIC_PAD_CTL_IDDQ_CLK0_SHIFT 25
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_STATIC_PAD_CTL_IDDQ_CLK0_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: STATIC_PAD_CTL :: IDDQ_ODT [24:24] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_STATIC_PAD_CTL_IDDQ_ODT_MASK 0x01000000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_STATIC_PAD_CTL_IDDQ_ODT_SHIFT 24
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_STATIC_PAD_CTL_IDDQ_ODT_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: STATIC_PAD_CTL :: IDDQ_PAR [23:23] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_STATIC_PAD_CTL_IDDQ_PAR_MASK 0x00800000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_STATIC_PAD_CTL_IDDQ_PAR_SHIFT 23
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_STATIC_PAD_CTL_IDDQ_PAR_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: STATIC_PAD_CTL :: IDDQ_BA [22:22] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_STATIC_PAD_CTL_IDDQ_BA_MASK 0x00400000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_STATIC_PAD_CTL_IDDQ_BA_SHIFT 22
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_STATIC_PAD_CTL_IDDQ_BA_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: STATIC_PAD_CTL :: IDDQ_AUX2 [21:21] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_STATIC_PAD_CTL_IDDQ_AUX2_MASK 0x00200000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_STATIC_PAD_CTL_IDDQ_AUX2_SHIFT 21
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_STATIC_PAD_CTL_IDDQ_AUX2_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: STATIC_PAD_CTL :: IDDQ_AUX1 [20:20] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_STATIC_PAD_CTL_IDDQ_AUX1_MASK 0x00100000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_STATIC_PAD_CTL_IDDQ_AUX1_SHIFT 20
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_STATIC_PAD_CTL_IDDQ_AUX1_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: STATIC_PAD_CTL :: IDDQ_AUX0 [19:19] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_STATIC_PAD_CTL_IDDQ_AUX0_MASK 0x00080000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_STATIC_PAD_CTL_IDDQ_AUX0_SHIFT 19
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_STATIC_PAD_CTL_IDDQ_AUX0_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: STATIC_PAD_CTL :: IDDQ_CS1 [18:18] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_STATIC_PAD_CTL_IDDQ_CS1_MASK 0x00040000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_STATIC_PAD_CTL_IDDQ_CS1_SHIFT 18
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_STATIC_PAD_CTL_IDDQ_CS1_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: STATIC_PAD_CTL :: IDDQ_A15 [17:17] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_STATIC_PAD_CTL_IDDQ_A15_MASK 0x00020000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_STATIC_PAD_CTL_IDDQ_A15_SHIFT 17
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_STATIC_PAD_CTL_IDDQ_A15_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: STATIC_PAD_CTL :: IDDQ_A14 [16:16] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_STATIC_PAD_CTL_IDDQ_A14_MASK 0x00010000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_STATIC_PAD_CTL_IDDQ_A14_SHIFT 16
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_STATIC_PAD_CTL_IDDQ_A14_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: STATIC_PAD_CTL :: IDDQ_A13 [15:15] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_STATIC_PAD_CTL_IDDQ_A13_MASK 0x00008000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_STATIC_PAD_CTL_IDDQ_A13_SHIFT 15
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_STATIC_PAD_CTL_IDDQ_A13_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: STATIC_PAD_CTL :: IDDQ_A12 [14:14] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_STATIC_PAD_CTL_IDDQ_A12_MASK 0x00004000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_STATIC_PAD_CTL_IDDQ_A12_SHIFT 14
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_STATIC_PAD_CTL_IDDQ_A12_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: STATIC_PAD_CTL :: IDDQ_A11 [13:13] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_STATIC_PAD_CTL_IDDQ_A11_MASK 0x00002000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_STATIC_PAD_CTL_IDDQ_A11_SHIFT 13
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_STATIC_PAD_CTL_IDDQ_A11_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: STATIC_PAD_CTL :: IDDQ_A10 [12:12] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_STATIC_PAD_CTL_IDDQ_A10_MASK 0x00001000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_STATIC_PAD_CTL_IDDQ_A10_SHIFT 12
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_STATIC_PAD_CTL_IDDQ_A10_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: STATIC_PAD_CTL :: IDDQ_A09 [11:11] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_STATIC_PAD_CTL_IDDQ_A09_MASK 0x00000800
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_STATIC_PAD_CTL_IDDQ_A09_SHIFT 11
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_STATIC_PAD_CTL_IDDQ_A09_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: STATIC_PAD_CTL :: reserved1 [10:10] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_STATIC_PAD_CTL_reserved1_MASK 0x00000400
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_STATIC_PAD_CTL_reserved1_SHIFT 10
-
-/* DDR34_PHY_CONTROL_REGS_0 :: STATIC_PAD_CTL :: TX_MODE [09:04] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_STATIC_PAD_CTL_TX_MODE_MASK 0x000003f0
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_STATIC_PAD_CTL_TX_MODE_SHIFT 4
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_STATIC_PAD_CTL_TX_MODE_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: STATIC_PAD_CTL :: reserved2 [03:03] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_STATIC_PAD_CTL_reserved2_MASK 0x00000008
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_STATIC_PAD_CTL_reserved2_SHIFT 3
-
-/* DDR34_PHY_CONTROL_REGS_0 :: STATIC_PAD_CTL :: RX_MODE [02:00] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_STATIC_PAD_CTL_RX_MODE_MASK 0x00000007
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_STATIC_PAD_CTL_RX_MODE_SHIFT 0
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_STATIC_PAD_CTL_RX_MODE_DEFAULT 0x00000000
-
-/***************************************************************************
- *STATIC_PAD_CTL_2T - pad rx and tx characteristics control register for signals that are 1T when in 2T mode -- CS, ODT and PAR
- ***************************************************************************/
-/* DDR34_PHY_CONTROL_REGS_0 :: STATIC_PAD_CTL_2T :: reserved0 [31:31] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_STATIC_PAD_CTL_2T_reserved0_MASK 0x80000000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_STATIC_PAD_CTL_2T_reserved0_SHIFT 31
-
-/* DDR34_PHY_CONTROL_REGS_0 :: STATIC_PAD_CTL_2T :: TX_SLEW [30:29] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_STATIC_PAD_CTL_2T_TX_SLEW_MASK 0x60000000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_STATIC_PAD_CTL_2T_TX_SLEW_SHIFT 29
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_STATIC_PAD_CTL_2T_TX_SLEW_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: STATIC_PAD_CTL_2T :: reserved1 [28:10] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_STATIC_PAD_CTL_2T_reserved1_MASK 0x1ffffc00
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_STATIC_PAD_CTL_2T_reserved1_SHIFT 10
-
-/* DDR34_PHY_CONTROL_REGS_0 :: STATIC_PAD_CTL_2T :: TX_MODE [09:04] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_STATIC_PAD_CTL_2T_TX_MODE_MASK 0x000003f0
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_STATIC_PAD_CTL_2T_TX_MODE_SHIFT 4
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_STATIC_PAD_CTL_2T_TX_MODE_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: STATIC_PAD_CTL_2T :: reserved2 [03:00] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_STATIC_PAD_CTL_2T_reserved2_MASK 0x0000000f
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_STATIC_PAD_CTL_2T_reserved2_SHIFT 0
-
-/***************************************************************************
- *RX_TRIM - Receiver trim
- ***************************************************************************/
-/* DDR34_PHY_CONTROL_REGS_0 :: RX_TRIM :: reserved0 [31:14] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_RX_TRIM_reserved0_MASK 0xffffc000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_RX_TRIM_reserved0_SHIFT 14
-
-/* DDR34_PHY_CONTROL_REGS_0 :: RX_TRIM :: DF_LSTRIM [13:10] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_RX_TRIM_DF_LSTRIM_MASK 0x00003c00
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_RX_TRIM_DF_LSTRIM_SHIFT 10
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_RX_TRIM_DF_LSTRIM_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: RX_TRIM :: DF_ITRIM [09:07] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_RX_TRIM_DF_ITRIM_MASK 0x00000380
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_RX_TRIM_DF_ITRIM_SHIFT 7
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_RX_TRIM_DF_ITRIM_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: RX_TRIM :: SE_LSTRIM [06:03] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_RX_TRIM_SE_LSTRIM_MASK 0x00000078
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_RX_TRIM_SE_LSTRIM_SHIFT 3
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_RX_TRIM_SE_LSTRIM_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: RX_TRIM :: SE_ITRIM [02:00] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_RX_TRIM_SE_ITRIM_MASK 0x00000007
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_RX_TRIM_SE_ITRIM_SHIFT 0
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_RX_TRIM_SE_ITRIM_DEFAULT 0x00000000
-
-/***************************************************************************
- *DRAM_CONFIG - DRAM configuration register
- ***************************************************************************/
-/* DDR34_PHY_CONTROL_REGS_0 :: DRAM_CONFIG :: INIT_MODE [31:31] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_DRAM_CONFIG_INIT_MODE_MASK 0x80000000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_DRAM_CONFIG_INIT_MODE_SHIFT 31
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_DRAM_CONFIG_INIT_MODE_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: DRAM_CONFIG :: reserved0 [30:28] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_DRAM_CONFIG_reserved0_MASK 0x70000000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_DRAM_CONFIG_reserved0_SHIFT 28
-
-/* DDR34_PHY_CONTROL_REGS_0 :: DRAM_CONFIG :: ECC_ENABLED [27:27] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_DRAM_CONFIG_ECC_ENABLED_MASK 0x08000000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_DRAM_CONFIG_ECC_ENABLED_SHIFT 27
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_DRAM_CONFIG_ECC_ENABLED_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: DRAM_CONFIG :: SPLIT_DQ_BUS [26:26] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_DRAM_CONFIG_SPLIT_DQ_BUS_MASK 0x04000000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_DRAM_CONFIG_SPLIT_DQ_BUS_SHIFT 26
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_DRAM_CONFIG_SPLIT_DQ_BUS_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: DRAM_CONFIG :: BUS16 [25:25] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_DRAM_CONFIG_BUS16_MASK 0x02000000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_DRAM_CONFIG_BUS16_SHIFT 25
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_DRAM_CONFIG_BUS16_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: DRAM_CONFIG :: BUS8 [24:24] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_DRAM_CONFIG_BUS8_MASK 0x01000000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_DRAM_CONFIG_BUS8_SHIFT 24
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_DRAM_CONFIG_BUS8_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: DRAM_CONFIG :: reserved1 [23:18] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_DRAM_CONFIG_reserved1_MASK 0x00fc0000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_DRAM_CONFIG_reserved1_SHIFT 18
-
-/* DDR34_PHY_CONTROL_REGS_0 :: DRAM_CONFIG :: CRC_ENABLED [17:17] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_DRAM_CONFIG_CRC_ENABLED_MASK 0x00020000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_DRAM_CONFIG_CRC_ENABLED_SHIFT 17
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_DRAM_CONFIG_CRC_ENABLED_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: DRAM_CONFIG :: DDR4_GEARDOWN_ENABLE [16:16] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_DRAM_CONFIG_DDR4_GEARDOWN_ENABLE_MASK 0x00010000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_DRAM_CONFIG_DDR4_GEARDOWN_ENABLE_SHIFT 16
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_DRAM_CONFIG_DDR4_GEARDOWN_ENABLE_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: DRAM_CONFIG :: EDC_MODE [15:15] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_DRAM_CONFIG_EDC_MODE_MASK 0x00008000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_DRAM_CONFIG_EDC_MODE_SHIFT 15
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_DRAM_CONFIG_EDC_MODE_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: DRAM_CONFIG :: RDQS_MODE [14:14] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_DRAM_CONFIG_RDQS_MODE_MASK 0x00004000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_DRAM_CONFIG_RDQS_MODE_SHIFT 14
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_DRAM_CONFIG_RDQS_MODE_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: DRAM_CONFIG :: GROUP_BITS [13:12] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_DRAM_CONFIG_GROUP_BITS_MASK 0x00003000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_DRAM_CONFIG_GROUP_BITS_SHIFT 12
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_DRAM_CONFIG_GROUP_BITS_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: DRAM_CONFIG :: BANK_BITS [11:10] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_DRAM_CONFIG_BANK_BITS_MASK 0x00000c00
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_DRAM_CONFIG_BANK_BITS_SHIFT 10
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_DRAM_CONFIG_BANK_BITS_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: DRAM_CONFIG :: COL_BITS [09:08] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_DRAM_CONFIG_COL_BITS_MASK 0x00000300
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_DRAM_CONFIG_COL_BITS_SHIFT 8
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_DRAM_CONFIG_COL_BITS_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: DRAM_CONFIG :: ROW_BITS [07:04] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_DRAM_CONFIG_ROW_BITS_MASK 0x000000f0
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_DRAM_CONFIG_ROW_BITS_SHIFT 4
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_DRAM_CONFIG_ROW_BITS_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: DRAM_CONFIG :: DRAM_TYPE [03:00] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_DRAM_CONFIG_DRAM_TYPE_MASK 0x0000000f
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_DRAM_CONFIG_DRAM_TYPE_SHIFT 0
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_DRAM_CONFIG_DRAM_TYPE_DEFAULT 0x00000000
-
-/***************************************************************************
- *DRAM_TIMING1 - DRAM timing register #1
- ***************************************************************************/
-/* DDR34_PHY_CONTROL_REGS_0 :: DRAM_TIMING1 :: TRAS [31:24] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_DRAM_TIMING1_TRAS_MASK 0xff000000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_DRAM_TIMING1_TRAS_SHIFT 24
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_DRAM_TIMING1_TRAS_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: DRAM_TIMING1 :: TRRD [23:16] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_DRAM_TIMING1_TRRD_MASK 0x00ff0000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_DRAM_TIMING1_TRRD_SHIFT 16
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_DRAM_TIMING1_TRRD_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: DRAM_TIMING1 :: TRP [15:08] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_DRAM_TIMING1_TRP_MASK 0x0000ff00
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_DRAM_TIMING1_TRP_SHIFT 8
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_DRAM_TIMING1_TRP_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: DRAM_TIMING1 :: TRCD [07:00] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_DRAM_TIMING1_TRCD_MASK 0x000000ff
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_DRAM_TIMING1_TRCD_SHIFT 0
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_DRAM_TIMING1_TRCD_DEFAULT 0x00000000
-
-/***************************************************************************
- *DRAM_TIMING2 - DRAM timing register #2
- ***************************************************************************/
-/* DDR34_PHY_CONTROL_REGS_0 :: DRAM_TIMING2 :: TRTP [31:24] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_DRAM_TIMING2_TRTP_MASK 0xff000000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_DRAM_TIMING2_TRTP_SHIFT 24
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_DRAM_TIMING2_TRTP_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: DRAM_TIMING2 :: TWR [23:16] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_DRAM_TIMING2_TWR_MASK 0x00ff0000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_DRAM_TIMING2_TWR_SHIFT 16
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_DRAM_TIMING2_TWR_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: DRAM_TIMING2 :: TCWL [15:08] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_DRAM_TIMING2_TCWL_MASK 0x0000ff00
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_DRAM_TIMING2_TCWL_SHIFT 8
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_DRAM_TIMING2_TCWL_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: DRAM_TIMING2 :: TCAS [07:00] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_DRAM_TIMING2_TCAS_MASK 0x000000ff
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_DRAM_TIMING2_TCAS_SHIFT 0
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_DRAM_TIMING2_TCAS_DEFAULT 0x00000000
-
-/***************************************************************************
- *DRAM_TIMING3 - DRAM timing register #3
- ***************************************************************************/
-/* DDR34_PHY_CONTROL_REGS_0 :: DRAM_TIMING3 :: reserved0 [31:28] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_DRAM_TIMING3_reserved0_MASK 0xf0000000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_DRAM_TIMING3_reserved0_SHIFT 28
-
-/* DDR34_PHY_CONTROL_REGS_0 :: DRAM_TIMING3 :: TCAL [27:20] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_DRAM_TIMING3_TCAL_MASK 0x0ff00000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_DRAM_TIMING3_TCAL_SHIFT 20
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_DRAM_TIMING3_TCAL_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: DRAM_TIMING3 :: TRTW [19:16] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_DRAM_TIMING3_TRTW_MASK 0x000f0000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_DRAM_TIMING3_TRTW_SHIFT 16
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_DRAM_TIMING3_TRTW_DEFAULT 0x00000004
-
-/* DDR34_PHY_CONTROL_REGS_0 :: DRAM_TIMING3 :: TWTR [15:12] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_DRAM_TIMING3_TWTR_MASK 0x0000f000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_DRAM_TIMING3_TWTR_SHIFT 12
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_DRAM_TIMING3_TWTR_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: DRAM_TIMING3 :: TRFC [11:00] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_DRAM_TIMING3_TRFC_MASK 0x00000fff
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_DRAM_TIMING3_TRFC_SHIFT 0
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_DRAM_TIMING3_TRFC_DEFAULT 0x00000000
-
-/***************************************************************************
- *DRAM_TIMING4 - DRAM timing register #4
- ***************************************************************************/
-/* DDR34_PHY_CONTROL_REGS_0 :: DRAM_TIMING4 :: temp [31:00] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_DRAM_TIMING4_temp_MASK 0xffffffff
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_DRAM_TIMING4_temp_SHIFT 0
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_DRAM_TIMING4_temp_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CALIBRATE - PHY VDL calibration control register
- ***************************************************************************/
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CALIBRATE :: reserved0 [31:10] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CALIBRATE_reserved0_MASK 0xfffffc00
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CALIBRATE_reserved0_SHIFT 10
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CALIBRATE :: reserved_for_eco1 [09:07] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CALIBRATE_reserved_for_eco1_MASK 0x00000380
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CALIBRATE_reserved_for_eco1_SHIFT 7
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CALIBRATE_reserved_for_eco1_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CALIBRATE :: CALIB_FAST [06:06] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CALIBRATE_CALIB_FAST_MASK 0x00000040
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CALIBRATE_CALIB_FAST_SHIFT 6
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CALIBRATE_CALIB_FAST_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CALIBRATE :: HALF_STEPS [05:05] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CALIBRATE_HALF_STEPS_MASK 0x00000020
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CALIBRATE_HALF_STEPS_SHIFT 5
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CALIBRATE_HALF_STEPS_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CALIBRATE :: UPDATE_FAST [04:04] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CALIBRATE_UPDATE_FAST_MASK 0x00000010
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CALIBRATE_UPDATE_FAST_SHIFT 4
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CALIBRATE_UPDATE_FAST_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CALIBRATE :: UPDATE_REGS [03:03] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CALIBRATE_UPDATE_REGS_MASK 0x00000008
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CALIBRATE_UPDATE_REGS_SHIFT 3
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CALIBRATE_UPDATE_REGS_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CALIBRATE :: CALIB_FTM2 [02:02] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CALIBRATE_CALIB_FTM2_MASK 0x00000004
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CALIBRATE_CALIB_FTM2_SHIFT 2
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CALIBRATE_CALIB_FTM2_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CALIBRATE :: CALIB_PHYBIST [01:01] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CALIBRATE_CALIB_PHYBIST_MASK 0x00000002
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CALIBRATE_CALIB_PHYBIST_SHIFT 1
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CALIBRATE_CALIB_PHYBIST_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CALIBRATE :: CALIB_ONCE [00:00] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CALIBRATE_CALIB_ONCE_MASK 0x00000001
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CALIBRATE_CALIB_ONCE_SHIFT 0
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CALIBRATE_CALIB_ONCE_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CALIB_STATUS1 - PHY VDL calibration status register #1
- ***************************************************************************/
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CALIB_STATUS1 :: reserved0 [31:18] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS1_reserved0_MASK 0xfffc0000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS1_reserved0_SHIFT 18
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CALIB_STATUS1 :: CALIB_TOTAL_STEPS [17:08] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS1_CALIB_TOTAL_STEPS_MASK 0x0003ff00
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS1_CALIB_TOTAL_STEPS_SHIFT 8
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS1_CALIB_TOTAL_STEPS_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CALIB_STATUS1 :: reserved1 [07:06] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS1_reserved1_MASK 0x000000c0
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS1_reserved1_SHIFT 6
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CALIB_STATUS1 :: CALIB_BUS_ERROR [05:05] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS1_CALIB_BUS_ERROR_MASK 0x00000020
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS1_CALIB_BUS_ERROR_SHIFT 5
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS1_CALIB_BUS_ERROR_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CALIB_STATUS1 :: CALIB_REGS_DONE [04:04] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS1_CALIB_REGS_DONE_MASK 0x00000010
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS1_CALIB_REGS_DONE_SHIFT 4
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS1_CALIB_REGS_DONE_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CALIB_STATUS1 :: CALIB_LOCK_6B [03:03] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS1_CALIB_LOCK_6B_MASK 0x00000008
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS1_CALIB_LOCK_6B_SHIFT 3
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS1_CALIB_LOCK_6B_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CALIB_STATUS1 :: CALIB_LOCK_4B [02:02] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS1_CALIB_LOCK_4B_MASK 0x00000004
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS1_CALIB_LOCK_4B_SHIFT 2
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS1_CALIB_LOCK_4B_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CALIB_STATUS1 :: CALIB_LOCK_2B [01:01] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS1_CALIB_LOCK_2B_MASK 0x00000002
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS1_CALIB_LOCK_2B_SHIFT 1
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS1_CALIB_LOCK_2B_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CALIB_STATUS1 :: CALIB_IDLE [00:00] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS1_CALIB_IDLE_MASK 0x00000001
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS1_CALIB_IDLE_SHIFT 0
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS1_CALIB_IDLE_DEFAULT 0x00000001
-
-/***************************************************************************
- *VDL_CALIB_STATUS2 - PHY VDL calibration status register #2
- ***************************************************************************/
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CALIB_STATUS2 :: reserved0 [31:22] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS2_reserved0_MASK 0xffc00000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS2_reserved0_SHIFT 22
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CALIB_STATUS2 :: CALIB_4B_STEPS [21:12] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS2_CALIB_4B_STEPS_MASK 0x003ff000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS2_CALIB_4B_STEPS_SHIFT 12
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS2_CALIB_4B_STEPS_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CALIB_STATUS2 :: reserved1 [11:10] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS2_reserved1_MASK 0x00000c00
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS2_reserved1_SHIFT 10
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CALIB_STATUS2 :: CALIB_2B_STEPS [09:00] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS2_CALIB_2B_STEPS_MASK 0x000003ff
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS2_CALIB_2B_STEPS_SHIFT 0
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS2_CALIB_2B_STEPS_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_MONITOR_CONTROL - PHY VDL delay monitoring control register
- ***************************************************************************/
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_MONITOR_CONTROL :: reserved0 [31:24] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_MONITOR_CONTROL_reserved0_MASK 0xff000000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_MONITOR_CONTROL_reserved0_SHIFT 24
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_MONITOR_CONTROL :: INTERVAL [23:08] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_MONITOR_CONTROL_INTERVAL_MASK 0x00ffff00
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_MONITOR_CONTROL_INTERVAL_SHIFT 8
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_MONITOR_CONTROL_INTERVAL_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_MONITOR_CONTROL :: reserved1 [07:04] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_MONITOR_CONTROL_reserved1_MASK 0x000000f0
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_MONITOR_CONTROL_reserved1_SHIFT 4
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_MONITOR_CONTROL :: UPDATE [03:03] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_MONITOR_CONTROL_UPDATE_MASK 0x00000008
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_MONITOR_CONTROL_UPDATE_SHIFT 3
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_MONITOR_CONTROL_UPDATE_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_MONITOR_CONTROL :: FORCE [02:02] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_MONITOR_CONTROL_FORCE_MASK 0x00000004
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_MONITOR_CONTROL_FORCE_SHIFT 2
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_MONITOR_CONTROL_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_MONITOR_CONTROL :: DATA_RATE [01:01] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_MONITOR_CONTROL_DATA_RATE_MASK 0x00000002
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_MONITOR_CONTROL_DATA_RATE_SHIFT 1
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_MONITOR_CONTROL_DATA_RATE_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_MONITOR_CONTROL :: ENABLE [00:00] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_MONITOR_CONTROL_ENABLE_MASK 0x00000001
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_MONITOR_CONTROL_ENABLE_SHIFT 0
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_MONITOR_CONTROL_ENABLE_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_MONITOR_REF - PHY VDL delay monitoring reference register
- ***************************************************************************/
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_MONITOR_REF :: reserved0 [31:22] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_MONITOR_REF_reserved0_MASK 0xffc00000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_MONITOR_REF_reserved0_SHIFT 22
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_MONITOR_REF :: MONITOR_4B_STEPS [21:12] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_MONITOR_REF_MONITOR_4B_STEPS_MASK 0x003ff000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_MONITOR_REF_MONITOR_4B_STEPS_SHIFT 12
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_MONITOR_REF_MONITOR_4B_STEPS_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_MONITOR_REF :: reserved1 [11:10] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_MONITOR_REF_reserved1_MASK 0x00000c00
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_MONITOR_REF_reserved1_SHIFT 10
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_MONITOR_REF :: MONITOR_2B_STEPS [09:00] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_MONITOR_REF_MONITOR_2B_STEPS_MASK 0x000003ff
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_MONITOR_REF_MONITOR_2B_STEPS_SHIFT 0
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_MONITOR_REF_MONITOR_2B_STEPS_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_MONITOR_STATUS - PHY VDL delay monitoring status register
- ***************************************************************************/
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_MONITOR_STATUS :: reserved0 [31:24] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_MONITOR_STATUS_reserved0_MASK 0xff000000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_MONITOR_STATUS_reserved0_SHIFT 24
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_MONITOR_STATUS :: MONITOR_CHANGE [23:16] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_MONITOR_STATUS_MONITOR_CHANGE_MASK 0x00ff0000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_MONITOR_STATUS_MONITOR_CHANGE_SHIFT 16
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_MONITOR_STATUS_MONITOR_CHANGE_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_MONITOR_STATUS :: reserved1 [15:14] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_MONITOR_STATUS_reserved1_MASK 0x0000c000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_MONITOR_STATUS_reserved1_SHIFT 14
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_MONITOR_STATUS :: MONITOR_TOTAL [13:04] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_MONITOR_STATUS_MONITOR_TOTAL_MASK 0x00003ff0
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_MONITOR_STATUS_MONITOR_TOTAL_SHIFT 4
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_MONITOR_STATUS_MONITOR_TOTAL_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_MONITOR_STATUS :: ERROR [03:03] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_MONITOR_STATUS_ERROR_MASK 0x00000008
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_MONITOR_STATUS_ERROR_SHIFT 3
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_MONITOR_STATUS_ERROR_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_MONITOR_STATUS :: PAUSED [02:01] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_MONITOR_STATUS_PAUSED_MASK 0x00000006
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_MONITOR_STATUS_PAUSED_SHIFT 1
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_MONITOR_STATUS_PAUSED_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_MONITOR_STATUS :: BUSY [00:00] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_MONITOR_STATUS_BUSY_MASK 0x00000001
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_MONITOR_STATUS_BUSY_SHIFT 0
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_MONITOR_STATUS_BUSY_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_MONITOR_OVERRIDE - PHY VDL delay monitoring override register
- ***************************************************************************/
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_MONITOR_OVERRIDE :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_MONITOR_OVERRIDE_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_MONITOR_OVERRIDE_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_MONITOR_OVERRIDE_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_MONITOR_OVERRIDE :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_MONITOR_OVERRIDE_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_MONITOR_OVERRIDE_reserved0_SHIFT 17
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_MONITOR_OVERRIDE :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_MONITOR_OVERRIDE_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_MONITOR_OVERRIDE_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_MONITOR_OVERRIDE_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_MONITOR_OVERRIDE :: reserved1 [15:05] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_MONITOR_OVERRIDE_reserved1_MASK 0x0000ffe0
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_MONITOR_OVERRIDE_reserved1_SHIFT 5
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_MONITOR_OVERRIDE :: ADJ [04:00] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_MONITOR_OVERRIDE_ADJ_MASK 0x0000001f
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_MONITOR_OVERRIDE_ADJ_SHIFT 0
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_MONITOR_OVERRIDE_ADJ_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_MONITOR_OUT_CONTROL - PHY VDL delay monitoring output control register
- ***************************************************************************/
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_MONITOR_OUT_CONTROL :: reserved0 [31:20] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_MONITOR_OUT_CONTROL_reserved0_MASK 0xfff00000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_MONITOR_OUT_CONTROL_reserved0_SHIFT 20
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_MONITOR_OUT_CONTROL :: LOWER_LIMIT [19:12] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_MONITOR_OUT_CONTROL_LOWER_LIMIT_MASK 0x000ff000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_MONITOR_OUT_CONTROL_LOWER_LIMIT_SHIFT 12
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_MONITOR_OUT_CONTROL_LOWER_LIMIT_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_MONITOR_OUT_CONTROL :: UPPER_LIMIT [11:04] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_MONITOR_OUT_CONTROL_UPPER_LIMIT_MASK 0x00000ff0
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_MONITOR_OUT_CONTROL_UPPER_LIMIT_SHIFT 4
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_MONITOR_OUT_CONTROL_UPPER_LIMIT_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_MONITOR_OUT_CONTROL :: reserved1 [03:01] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_MONITOR_OUT_CONTROL_reserved1_MASK 0x0000000e
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_MONITOR_OUT_CONTROL_reserved1_SHIFT 1
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_MONITOR_OUT_CONTROL :: ENABLE [00:00] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_MONITOR_OUT_CONTROL_ENABLE_MASK 0x00000001
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_MONITOR_OUT_CONTROL_ENABLE_SHIFT 0
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_MONITOR_OUT_CONTROL_ENABLE_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_MONITOR_OUT_STATUS - PHY VDL delay monitoring output status register
- ***************************************************************************/
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_MONITOR_OUT_STATUS :: reserved0 [31:24] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_MONITOR_OUT_STATUS_reserved0_MASK 0xff000000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_MONITOR_OUT_STATUS_reserved0_SHIFT 24
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_MONITOR_OUT_STATUS :: MONITOR_CHANGE [23:16] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_MONITOR_OUT_STATUS_MONITOR_CHANGE_MASK 0x00ff0000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_MONITOR_OUT_STATUS_MONITOR_CHANGE_SHIFT 16
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_MONITOR_OUT_STATUS_MONITOR_CHANGE_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_MONITOR_OUT_STATUS :: reserved1 [15:14] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_MONITOR_OUT_STATUS_reserved1_MASK 0x0000c000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_MONITOR_OUT_STATUS_reserved1_SHIFT 14
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_MONITOR_OUT_STATUS :: MONITOR_TOTAL [13:04] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_MONITOR_OUT_STATUS_MONITOR_TOTAL_MASK 0x00003ff0
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_MONITOR_OUT_STATUS_MONITOR_TOTAL_SHIFT 4
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_MONITOR_OUT_STATUS_MONITOR_TOTAL_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_MONITOR_OUT_STATUS :: reserved2 [03:01] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_MONITOR_OUT_STATUS_reserved2_MASK 0x0000000e
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_MONITOR_OUT_STATUS_reserved2_SHIFT 1
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_MONITOR_OUT_STATUS :: VALID [00:00] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_MONITOR_OUT_STATUS_VALID_MASK 0x00000001
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_MONITOR_OUT_STATUS_VALID_SHIFT 0
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_MONITOR_OUT_STATUS_VALID_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_MONITOR_OUT_STATUS_CLEAR - PHY VDL delay monitoring output status clear register
- ***************************************************************************/
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_MONITOR_OUT_STATUS_CLEAR :: reserved0 [31:01] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_MONITOR_OUT_STATUS_CLEAR_reserved0_MASK 0xfffffffe
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_MONITOR_OUT_STATUS_CLEAR_reserved0_SHIFT 1
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_MONITOR_OUT_STATUS_CLEAR :: CLEAR [00:00] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_MONITOR_OUT_STATUS_CLEAR_CLEAR_MASK 0x00000001
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_MONITOR_OUT_STATUS_CLEAR_CLEAR_SHIFT 0
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_MONITOR_OUT_STATUS_CLEAR_CLEAR_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_AD00 - DDR interface signal AD[00] VDL control register
- ***************************************************************************/
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_AD00 :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD00_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD00_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD00_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_AD00 :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD00_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD00_reserved0_SHIFT 17
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_AD00 :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD00_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD00_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD00_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_AD00 :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD00_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD00_reserved1_SHIFT 13
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_AD00 :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD00_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD00_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD00_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_AD00 :: reserved2 [11:09] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD00_reserved2_MASK 0x00000e00
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD00_reserved2_SHIFT 9
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_AD00 :: VDL_STEP [08:00] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD00_VDL_STEP_MASK 0x000001ff
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD00_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD00_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_AD01 - DDR interface signal AD[01] VDL control register
- ***************************************************************************/
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_AD01 :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD01_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD01_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD01_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_AD01 :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD01_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD01_reserved0_SHIFT 17
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_AD01 :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD01_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD01_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD01_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_AD01 :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD01_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD01_reserved1_SHIFT 13
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_AD01 :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD01_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD01_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD01_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_AD01 :: reserved2 [11:09] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD01_reserved2_MASK 0x00000e00
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD01_reserved2_SHIFT 9
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_AD01 :: VDL_STEP [08:00] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD01_VDL_STEP_MASK 0x000001ff
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD01_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD01_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_AD02 - DDR interface signal AD[02] VDL control register
- ***************************************************************************/
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_AD02 :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD02_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD02_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD02_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_AD02 :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD02_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD02_reserved0_SHIFT 17
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_AD02 :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD02_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD02_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD02_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_AD02 :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD02_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD02_reserved1_SHIFT 13
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_AD02 :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD02_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD02_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD02_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_AD02 :: reserved2 [11:09] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD02_reserved2_MASK 0x00000e00
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD02_reserved2_SHIFT 9
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_AD02 :: VDL_STEP [08:00] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD02_VDL_STEP_MASK 0x000001ff
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD02_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD02_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_AD03 - DDR interface signal AD[03] VDL control register
- ***************************************************************************/
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_AD03 :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD03_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD03_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD03_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_AD03 :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD03_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD03_reserved0_SHIFT 17
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_AD03 :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD03_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD03_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD03_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_AD03 :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD03_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD03_reserved1_SHIFT 13
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_AD03 :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD03_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD03_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD03_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_AD03 :: reserved2 [11:09] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD03_reserved2_MASK 0x00000e00
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD03_reserved2_SHIFT 9
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_AD03 :: VDL_STEP [08:00] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD03_VDL_STEP_MASK 0x000001ff
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD03_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD03_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_AD04 - DDR interface signal AD[04] VDL control register
- ***************************************************************************/
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_AD04 :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD04_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD04_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD04_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_AD04 :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD04_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD04_reserved0_SHIFT 17
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_AD04 :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD04_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD04_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD04_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_AD04 :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD04_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD04_reserved1_SHIFT 13
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_AD04 :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD04_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD04_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD04_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_AD04 :: reserved2 [11:09] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD04_reserved2_MASK 0x00000e00
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD04_reserved2_SHIFT 9
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_AD04 :: VDL_STEP [08:00] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD04_VDL_STEP_MASK 0x000001ff
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD04_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD04_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_AD05 - DDR interface signal AD[05] VDL control register
- ***************************************************************************/
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_AD05 :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD05_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD05_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD05_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_AD05 :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD05_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD05_reserved0_SHIFT 17
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_AD05 :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD05_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD05_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD05_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_AD05 :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD05_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD05_reserved1_SHIFT 13
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_AD05 :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD05_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD05_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD05_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_AD05 :: reserved2 [11:09] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD05_reserved2_MASK 0x00000e00
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD05_reserved2_SHIFT 9
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_AD05 :: VDL_STEP [08:00] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD05_VDL_STEP_MASK 0x000001ff
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD05_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD05_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_AD06 - DDR interface signal AD[06] VDL control register
- ***************************************************************************/
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_AD06 :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD06_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD06_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD06_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_AD06 :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD06_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD06_reserved0_SHIFT 17
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_AD06 :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD06_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD06_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD06_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_AD06 :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD06_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD06_reserved1_SHIFT 13
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_AD06 :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD06_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD06_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD06_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_AD06 :: reserved2 [11:09] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD06_reserved2_MASK 0x00000e00
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD06_reserved2_SHIFT 9
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_AD06 :: VDL_STEP [08:00] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD06_VDL_STEP_MASK 0x000001ff
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD06_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD06_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_AD07 - DDR interface signal AD[07] VDL control register
- ***************************************************************************/
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_AD07 :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD07_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD07_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD07_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_AD07 :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD07_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD07_reserved0_SHIFT 17
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_AD07 :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD07_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD07_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD07_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_AD07 :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD07_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD07_reserved1_SHIFT 13
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_AD07 :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD07_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD07_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD07_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_AD07 :: reserved2 [11:09] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD07_reserved2_MASK 0x00000e00
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD07_reserved2_SHIFT 9
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_AD07 :: VDL_STEP [08:00] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD07_VDL_STEP_MASK 0x000001ff
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD07_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD07_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_AD08 - DDR interface signal AD[08] VDL control register
- ***************************************************************************/
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_AD08 :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD08_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD08_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD08_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_AD08 :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD08_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD08_reserved0_SHIFT 17
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_AD08 :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD08_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD08_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD08_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_AD08 :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD08_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD08_reserved1_SHIFT 13
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_AD08 :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD08_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD08_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD08_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_AD08 :: reserved2 [11:09] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD08_reserved2_MASK 0x00000e00
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD08_reserved2_SHIFT 9
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_AD08 :: VDL_STEP [08:00] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD08_VDL_STEP_MASK 0x000001ff
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD08_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD08_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_AD09 - DDR interface signal AD[09] VDL control register
- ***************************************************************************/
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_AD09 :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD09_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD09_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD09_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_AD09 :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD09_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD09_reserved0_SHIFT 17
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_AD09 :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD09_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD09_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD09_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_AD09 :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD09_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD09_reserved1_SHIFT 13
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_AD09 :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD09_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD09_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD09_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_AD09 :: reserved2 [11:09] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD09_reserved2_MASK 0x00000e00
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD09_reserved2_SHIFT 9
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_AD09 :: VDL_STEP [08:00] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD09_VDL_STEP_MASK 0x000001ff
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD09_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD09_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_AD10 - DDR interface signal AD[10] VDL control register
- ***************************************************************************/
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_AD10 :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD10_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD10_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD10_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_AD10 :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD10_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD10_reserved0_SHIFT 17
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_AD10 :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD10_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD10_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD10_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_AD10 :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD10_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD10_reserved1_SHIFT 13
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_AD10 :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD10_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD10_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD10_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_AD10 :: reserved2 [11:09] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD10_reserved2_MASK 0x00000e00
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD10_reserved2_SHIFT 9
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_AD10 :: VDL_STEP [08:00] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD10_VDL_STEP_MASK 0x000001ff
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD10_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD10_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_AD11 - DDR interface signal AD[11] VDL control register
- ***************************************************************************/
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_AD11 :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD11_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD11_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD11_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_AD11 :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD11_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD11_reserved0_SHIFT 17
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_AD11 :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD11_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD11_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD11_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_AD11 :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD11_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD11_reserved1_SHIFT 13
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_AD11 :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD11_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD11_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD11_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_AD11 :: reserved2 [11:09] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD11_reserved2_MASK 0x00000e00
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD11_reserved2_SHIFT 9
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_AD11 :: VDL_STEP [08:00] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD11_VDL_STEP_MASK 0x000001ff
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD11_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD11_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_AD12 - DDR interface signal AD[12] VDL control register
- ***************************************************************************/
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_AD12 :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD12_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD12_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD12_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_AD12 :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD12_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD12_reserved0_SHIFT 17
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_AD12 :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD12_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD12_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD12_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_AD12 :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD12_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD12_reserved1_SHIFT 13
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_AD12 :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD12_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD12_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD12_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_AD12 :: reserved2 [11:09] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD12_reserved2_MASK 0x00000e00
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD12_reserved2_SHIFT 9
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_AD12 :: VDL_STEP [08:00] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD12_VDL_STEP_MASK 0x000001ff
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD12_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD12_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_AD13 - DDR interface signal AD[13] VDL control register
- ***************************************************************************/
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_AD13 :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD13_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD13_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD13_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_AD13 :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD13_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD13_reserved0_SHIFT 17
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_AD13 :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD13_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD13_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD13_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_AD13 :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD13_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD13_reserved1_SHIFT 13
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_AD13 :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD13_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD13_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD13_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_AD13 :: reserved2 [11:09] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD13_reserved2_MASK 0x00000e00
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD13_reserved2_SHIFT 9
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_AD13 :: VDL_STEP [08:00] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD13_VDL_STEP_MASK 0x000001ff
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD13_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD13_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_AD14 - DDR interface signal AD[14] VDL control register
- ***************************************************************************/
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_AD14 :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD14_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD14_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD14_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_AD14 :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD14_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD14_reserved0_SHIFT 17
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_AD14 :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD14_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD14_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD14_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_AD14 :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD14_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD14_reserved1_SHIFT 13
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_AD14 :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD14_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD14_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD14_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_AD14 :: reserved2 [11:09] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD14_reserved2_MASK 0x00000e00
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD14_reserved2_SHIFT 9
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_AD14 :: VDL_STEP [08:00] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD14_VDL_STEP_MASK 0x000001ff
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD14_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD14_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_AD15 - DDR interface signal AD[15] VDL control register
- ***************************************************************************/
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_AD15 :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD15_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD15_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD15_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_AD15 :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD15_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD15_reserved0_SHIFT 17
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_AD15 :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD15_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD15_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD15_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_AD15 :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD15_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD15_reserved1_SHIFT 13
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_AD15 :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD15_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD15_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD15_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_AD15 :: reserved2 [11:09] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD15_reserved2_MASK 0x00000e00
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD15_reserved2_SHIFT 9
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_AD15 :: VDL_STEP [08:00] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD15_VDL_STEP_MASK 0x000001ff
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD15_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD15_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_BA0 - DDR interface signal BA[0] VDL control register
- ***************************************************************************/
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_BA0 :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_BA0_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_BA0_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_BA0_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_BA0 :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_BA0_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_BA0_reserved0_SHIFT 17
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_BA0 :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_BA0_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_BA0_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_BA0_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_BA0 :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_BA0_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_BA0_reserved1_SHIFT 13
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_BA0 :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_BA0_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_BA0_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_BA0_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_BA0 :: reserved2 [11:09] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_BA0_reserved2_MASK 0x00000e00
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_BA0_reserved2_SHIFT 9
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_BA0 :: VDL_STEP [08:00] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_BA0_VDL_STEP_MASK 0x000001ff
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_BA0_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_BA0_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_BA1 - DDR interface signal BA[1] VDL control register
- ***************************************************************************/
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_BA1 :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_BA1_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_BA1_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_BA1_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_BA1 :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_BA1_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_BA1_reserved0_SHIFT 17
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_BA1 :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_BA1_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_BA1_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_BA1_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_BA1 :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_BA1_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_BA1_reserved1_SHIFT 13
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_BA1 :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_BA1_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_BA1_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_BA1_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_BA1 :: reserved2 [11:09] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_BA1_reserved2_MASK 0x00000e00
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_BA1_reserved2_SHIFT 9
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_BA1 :: VDL_STEP [08:00] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_BA1_VDL_STEP_MASK 0x000001ff
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_BA1_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_BA1_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_BA2 - DDR interface signal BA[2] VDL control register
- ***************************************************************************/
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_BA2 :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_BA2_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_BA2_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_BA2_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_BA2 :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_BA2_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_BA2_reserved0_SHIFT 17
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_BA2 :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_BA2_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_BA2_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_BA2_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_BA2 :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_BA2_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_BA2_reserved1_SHIFT 13
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_BA2 :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_BA2_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_BA2_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_BA2_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_BA2 :: reserved2 [11:09] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_BA2_reserved2_MASK 0x00000e00
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_BA2_reserved2_SHIFT 9
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_BA2 :: VDL_STEP [08:00] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_BA2_VDL_STEP_MASK 0x000001ff
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_BA2_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_BA2_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_AUX0 - DDR interface signal AUX[0] VDL control register
- ***************************************************************************/
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_AUX0 :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AUX0_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AUX0_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AUX0_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_AUX0 :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AUX0_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AUX0_reserved0_SHIFT 17
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_AUX0 :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AUX0_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AUX0_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AUX0_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_AUX0 :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AUX0_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AUX0_reserved1_SHIFT 13
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_AUX0 :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AUX0_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AUX0_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AUX0_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_AUX0 :: reserved2 [11:09] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AUX0_reserved2_MASK 0x00000e00
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AUX0_reserved2_SHIFT 9
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_AUX0 :: VDL_STEP [08:00] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AUX0_VDL_STEP_MASK 0x000001ff
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AUX0_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AUX0_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_AUX1 - DDR interface signal AUX[1] VDL control register
- ***************************************************************************/
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_AUX1 :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AUX1_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AUX1_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AUX1_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_AUX1 :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AUX1_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AUX1_reserved0_SHIFT 17
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_AUX1 :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AUX1_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AUX1_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AUX1_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_AUX1 :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AUX1_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AUX1_reserved1_SHIFT 13
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_AUX1 :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AUX1_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AUX1_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AUX1_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_AUX1 :: reserved2 [11:09] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AUX1_reserved2_MASK 0x00000e00
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AUX1_reserved2_SHIFT 9
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_AUX1 :: VDL_STEP [08:00] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AUX1_VDL_STEP_MASK 0x000001ff
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AUX1_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AUX1_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_AUX2 - DDR interface signal AUX[2] VDL control register
- ***************************************************************************/
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_AUX2 :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AUX2_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AUX2_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AUX2_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_AUX2 :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AUX2_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AUX2_reserved0_SHIFT 17
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_AUX2 :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AUX2_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AUX2_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AUX2_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_AUX2 :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AUX2_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AUX2_reserved1_SHIFT 13
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_AUX2 :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AUX2_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AUX2_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AUX2_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_AUX2 :: reserved2 [11:09] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AUX2_reserved2_MASK 0x00000e00
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AUX2_reserved2_SHIFT 9
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_AUX2 :: VDL_STEP [08:00] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AUX2_VDL_STEP_MASK 0x000001ff
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AUX2_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AUX2_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_CS0 - DDR interface signal CS0 VDL control register
- ***************************************************************************/
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_CS0 :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_CS0_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_CS0_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_CS0_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_CS0 :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_CS0_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_CS0_reserved0_SHIFT 17
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_CS0 :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_CS0_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_CS0_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_CS0_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_CS0 :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_CS0_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_CS0_reserved1_SHIFT 13
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_CS0 :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_CS0_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_CS0_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_CS0_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_CS0 :: reserved2 [11:09] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_CS0_reserved2_MASK 0x00000e00
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_CS0_reserved2_SHIFT 9
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_CS0 :: VDL_STEP [08:00] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_CS0_VDL_STEP_MASK 0x000001ff
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_CS0_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_CS0_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_CS1 - DDR interface signal CS1 VDL control register
- ***************************************************************************/
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_CS1 :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_CS1_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_CS1_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_CS1_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_CS1 :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_CS1_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_CS1_reserved0_SHIFT 17
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_CS1 :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_CS1_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_CS1_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_CS1_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_CS1 :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_CS1_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_CS1_reserved1_SHIFT 13
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_CS1 :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_CS1_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_CS1_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_CS1_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_CS1 :: reserved2 [11:09] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_CS1_reserved2_MASK 0x00000e00
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_CS1_reserved2_SHIFT 9
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_CS1 :: VDL_STEP [08:00] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_CS1_VDL_STEP_MASK 0x000001ff
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_CS1_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_CS1_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_PAR - DDR interface signal PAR VDL control register
- ***************************************************************************/
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_PAR :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_PAR_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_PAR_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_PAR_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_PAR :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_PAR_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_PAR_reserved0_SHIFT 17
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_PAR :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_PAR_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_PAR_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_PAR_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_PAR :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_PAR_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_PAR_reserved1_SHIFT 13
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_PAR :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_PAR_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_PAR_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_PAR_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_PAR :: reserved2 [11:09] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_PAR_reserved2_MASK 0x00000e00
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_PAR_reserved2_SHIFT 9
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_PAR :: VDL_STEP [08:00] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_PAR_VDL_STEP_MASK 0x000001ff
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_PAR_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_PAR_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_RAS_N - DDR interface signal RAS_N VDL control register
- ***************************************************************************/
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_RAS_N :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_RAS_N_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_RAS_N_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_RAS_N_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_RAS_N :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_RAS_N_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_RAS_N_reserved0_SHIFT 17
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_RAS_N :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_RAS_N_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_RAS_N_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_RAS_N_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_RAS_N :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_RAS_N_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_RAS_N_reserved1_SHIFT 13
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_RAS_N :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_RAS_N_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_RAS_N_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_RAS_N_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_RAS_N :: reserved2 [11:09] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_RAS_N_reserved2_MASK 0x00000e00
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_RAS_N_reserved2_SHIFT 9
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_RAS_N :: VDL_STEP [08:00] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_RAS_N_VDL_STEP_MASK 0x000001ff
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_RAS_N_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_RAS_N_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_CAS_N - DDR interface signal CAS_N VDL control register
- ***************************************************************************/
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_CAS_N :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_CAS_N_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_CAS_N_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_CAS_N_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_CAS_N :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_CAS_N_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_CAS_N_reserved0_SHIFT 17
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_CAS_N :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_CAS_N_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_CAS_N_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_CAS_N_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_CAS_N :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_CAS_N_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_CAS_N_reserved1_SHIFT 13
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_CAS_N :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_CAS_N_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_CAS_N_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_CAS_N_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_CAS_N :: reserved2 [11:09] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_CAS_N_reserved2_MASK 0x00000e00
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_CAS_N_reserved2_SHIFT 9
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_CAS_N :: VDL_STEP [08:00] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_CAS_N_VDL_STEP_MASK 0x000001ff
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_CAS_N_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_CAS_N_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_CKE - DDR interface signal CKE0 VDL control register
- ***************************************************************************/
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_CKE :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_CKE_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_CKE_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_CKE_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_CKE :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_CKE_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_CKE_reserved0_SHIFT 17
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_CKE :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_CKE_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_CKE_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_CKE_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_CKE :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_CKE_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_CKE_reserved1_SHIFT 13
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_CKE :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_CKE_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_CKE_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_CKE_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_CKE :: reserved2 [11:09] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_CKE_reserved2_MASK 0x00000e00
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_CKE_reserved2_SHIFT 9
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_CKE :: VDL_STEP [08:00] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_CKE_VDL_STEP_MASK 0x000001ff
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_CKE_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_CKE_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_RST_N - DDR interface signal RST_N VDL control register
- ***************************************************************************/
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_RST_N :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_RST_N_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_RST_N_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_RST_N_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_RST_N :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_RST_N_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_RST_N_reserved0_SHIFT 17
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_RST_N :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_RST_N_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_RST_N_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_RST_N_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_RST_N :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_RST_N_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_RST_N_reserved1_SHIFT 13
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_RST_N :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_RST_N_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_RST_N_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_RST_N_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_RST_N :: reserved2 [11:09] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_RST_N_reserved2_MASK 0x00000e00
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_RST_N_reserved2_SHIFT 9
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_RST_N :: VDL_STEP [08:00] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_RST_N_VDL_STEP_MASK 0x000001ff
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_RST_N_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_RST_N_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_ODT - DDR interface signal ODT0 VDL control register
- ***************************************************************************/
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_ODT :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_ODT_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_ODT_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_ODT_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_ODT :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_ODT_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_ODT_reserved0_SHIFT 17
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_ODT :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_ODT_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_ODT_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_ODT_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_ODT :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_ODT_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_ODT_reserved1_SHIFT 13
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_ODT :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_ODT_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_ODT_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_ODT_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_ODT :: reserved2 [11:09] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_ODT_reserved2_MASK 0x00000e00
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_ODT_reserved2_SHIFT 9
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_ODT :: VDL_STEP [08:00] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_ODT_VDL_STEP_MASK 0x000001ff
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_ODT_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_ODT_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_WE_N - DDR interface signal WE_N VDL control register
- ***************************************************************************/
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_WE_N :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_WE_N_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_WE_N_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_WE_N_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_WE_N :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_WE_N_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_WE_N_reserved0_SHIFT 17
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_WE_N :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_WE_N_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_WE_N_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_WE_N_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_WE_N :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_WE_N_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_WE_N_reserved1_SHIFT 13
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_WE_N :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_WE_N_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_WE_N_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_WE_N_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_WE_N :: reserved2 [11:09] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_WE_N_reserved2_MASK 0x00000e00
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_WE_N_reserved2_SHIFT 9
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_WE_N :: VDL_STEP [08:00] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_WE_N_VDL_STEP_MASK 0x000001ff
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_WE_N_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_WE_N_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_DDR_CK - DDR interface signal DDR_CK VDL control register
- ***************************************************************************/
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_DDR_CK :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_DDR_CK_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_DDR_CK_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_DDR_CK_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_DDR_CK :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_DDR_CK_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_DDR_CK_reserved0_SHIFT 17
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_DDR_CK :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_DDR_CK_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_DDR_CK_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_DDR_CK_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_DDR_CK :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_DDR_CK_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_DDR_CK_reserved1_SHIFT 13
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_DDR_CK :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_DDR_CK_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_DDR_CK_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_DDR_CK_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_DDR_CK :: reserved2 [11:09] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_DDR_CK_reserved2_MASK 0x00000e00
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_DDR_CK_reserved2_SHIFT 9
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_DDR_CK :: VDL_STEP [08:00] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_DDR_CK_VDL_STEP_MASK 0x000001ff
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_DDR_CK_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_DDR_CK_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CLK_CONTROL - DDR interface signal Write Leveling CLK VDL control register
- ***************************************************************************/
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CLK_CONTROL :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CLK_CONTROL_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CLK_CONTROL_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CLK_CONTROL_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CLK_CONTROL :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CLK_CONTROL_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CLK_CONTROL_reserved0_SHIFT 17
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CLK_CONTROL :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CLK_CONTROL_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CLK_CONTROL_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CLK_CONTROL_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CLK_CONTROL :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CLK_CONTROL_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CLK_CONTROL_reserved1_SHIFT 13
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CLK_CONTROL :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CLK_CONTROL_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CLK_CONTROL_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CLK_CONTROL_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CLK_CONTROL :: reserved2 [11:09] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CLK_CONTROL_reserved2_MASK 0x00000e00
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CLK_CONTROL_reserved2_SHIFT 9
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CLK_CONTROL :: VDL_STEP [08:00] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CLK_CONTROL_VDL_STEP_MASK 0x000001ff
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CLK_CONTROL_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CLK_CONTROL_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_LDE_CONTROL - DDR interface signal Write Leveling Capture Enable VDL control register
- ***************************************************************************/
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_LDE_CONTROL :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_LDE_CONTROL_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_LDE_CONTROL_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_LDE_CONTROL_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_LDE_CONTROL :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_LDE_CONTROL_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_LDE_CONTROL_reserved0_SHIFT 17
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_LDE_CONTROL :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_LDE_CONTROL_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_LDE_CONTROL_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_LDE_CONTROL_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_LDE_CONTROL :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_LDE_CONTROL_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_LDE_CONTROL_reserved1_SHIFT 13
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_LDE_CONTROL :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_LDE_CONTROL_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_LDE_CONTROL_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_LDE_CONTROL_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_LDE_CONTROL :: reserved2 [11:09] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_LDE_CONTROL_reserved2_MASK 0x00000e00
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_LDE_CONTROL_reserved2_SHIFT 9
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_LDE_CONTROL :: VDL_STEP [08:00] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_LDE_CONTROL_VDL_STEP_MASK 0x000001ff
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_LDE_CONTROL_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_LDE_CONTROL_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *CMD_CYC_DLY - GDDR5 command interface delay stage control
- ***************************************************************************/
-/* DDR34_PHY_CONTROL_REGS_0 :: CMD_CYC_DLY :: reserved0 [31:06] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_CMD_CYC_DLY_reserved0_MASK 0xffffffc0
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_CMD_CYC_DLY_reserved0_SHIFT 6
-
-/* DDR34_PHY_CONTROL_REGS_0 :: CMD_CYC_DLY :: CKE [05:05] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_CMD_CYC_DLY_CKE_MASK 0x00000020
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_CMD_CYC_DLY_CKE_SHIFT 5
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_CMD_CYC_DLY_CKE_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: CMD_CYC_DLY :: WE_N [04:04] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_CMD_CYC_DLY_WE_N_MASK 0x00000010
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_CMD_CYC_DLY_WE_N_SHIFT 4
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_CMD_CYC_DLY_WE_N_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: CMD_CYC_DLY :: CAS_N [03:03] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_CMD_CYC_DLY_CAS_N_MASK 0x00000008
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_CMD_CYC_DLY_CAS_N_SHIFT 3
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_CMD_CYC_DLY_CAS_N_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: CMD_CYC_DLY :: RAS_N [02:02] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_CMD_CYC_DLY_RAS_N_MASK 0x00000004
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_CMD_CYC_DLY_RAS_N_SHIFT 2
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_CMD_CYC_DLY_RAS_N_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: CMD_CYC_DLY :: CS_N [01:00] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_CMD_CYC_DLY_CS_N_MASK 0x00000003
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_CMD_CYC_DLY_CS_N_SHIFT 0
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_CMD_CYC_DLY_CS_N_DEFAULT 0x00000000
-
-/***************************************************************************
- *UPDATE_VDL - Update VDL control register
- ***************************************************************************/
-/* DDR34_PHY_CONTROL_REGS_0 :: UPDATE_VDL :: reserved0 [31:10] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_UPDATE_VDL_reserved0_MASK 0xfffffc00
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_UPDATE_VDL_reserved0_SHIFT 10
-
-/* DDR34_PHY_CONTROL_REGS_0 :: UPDATE_VDL :: MODE [09:04] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_UPDATE_VDL_MODE_MASK 0x000003f0
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_UPDATE_VDL_MODE_SHIFT 4
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_UPDATE_VDL_MODE_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: UPDATE_VDL :: reserved1 [03:02] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_UPDATE_VDL_reserved1_MASK 0x0000000c
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_UPDATE_VDL_reserved1_SHIFT 2
-
-/* DDR34_PHY_CONTROL_REGS_0 :: UPDATE_VDL :: DISABLE_INPUT [01:01] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_UPDATE_VDL_DISABLE_INPUT_MASK 0x00000002
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_UPDATE_VDL_DISABLE_INPUT_SHIFT 1
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_UPDATE_VDL_DISABLE_INPUT_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: UPDATE_VDL :: ENABLE [00:00] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_UPDATE_VDL_ENABLE_MASK 0x00000001
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_UPDATE_VDL_ENABLE_SHIFT 0
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_UPDATE_VDL_ENABLE_DEFAULT 0x00000000
-
-/***************************************************************************
- *UPDATE_VDL_SNOOP1 - Update VDL snoop control register #1
- ***************************************************************************/
-/* DDR34_PHY_CONTROL_REGS_0 :: UPDATE_VDL_SNOOP1 :: reserved0 [31:29] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_UPDATE_VDL_SNOOP1_reserved0_MASK 0xe0000000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_UPDATE_VDL_SNOOP1_reserved0_SHIFT 29
-
-/* DDR34_PHY_CONTROL_REGS_0 :: UPDATE_VDL_SNOOP1 :: MASK [28:20] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_UPDATE_VDL_SNOOP1_MASK_MASK 0x1ff00000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_UPDATE_VDL_SNOOP1_MASK_SHIFT 20
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_UPDATE_VDL_SNOOP1_MASK_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: UPDATE_VDL_SNOOP1 :: reserved1 [19:17] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_UPDATE_VDL_SNOOP1_reserved1_MASK 0x000e0000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_UPDATE_VDL_SNOOP1_reserved1_SHIFT 17
-
-/* DDR34_PHY_CONTROL_REGS_0 :: UPDATE_VDL_SNOOP1 :: CMD [16:08] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_UPDATE_VDL_SNOOP1_CMD_MASK 0x0001ff00
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_UPDATE_VDL_SNOOP1_CMD_SHIFT 8
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_UPDATE_VDL_SNOOP1_CMD_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: UPDATE_VDL_SNOOP1 :: reserved2 [07:06] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_UPDATE_VDL_SNOOP1_reserved2_MASK 0x000000c0
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_UPDATE_VDL_SNOOP1_reserved2_SHIFT 6
-
-/* DDR34_PHY_CONTROL_REGS_0 :: UPDATE_VDL_SNOOP1 :: ENABLE [05:00] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_UPDATE_VDL_SNOOP1_ENABLE_MASK 0x0000003f
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_UPDATE_VDL_SNOOP1_ENABLE_SHIFT 0
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_UPDATE_VDL_SNOOP1_ENABLE_DEFAULT 0x00000000
-
-/***************************************************************************
- *UPDATE_VDL_SNOOP2 - Update VDL snoop control register #2
- ***************************************************************************/
-/* DDR34_PHY_CONTROL_REGS_0 :: UPDATE_VDL_SNOOP2 :: reserved0 [31:29] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_UPDATE_VDL_SNOOP2_reserved0_MASK 0xe0000000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_UPDATE_VDL_SNOOP2_reserved0_SHIFT 29
-
-/* DDR34_PHY_CONTROL_REGS_0 :: UPDATE_VDL_SNOOP2 :: MASK [28:20] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_UPDATE_VDL_SNOOP2_MASK_MASK 0x1ff00000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_UPDATE_VDL_SNOOP2_MASK_SHIFT 20
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_UPDATE_VDL_SNOOP2_MASK_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: UPDATE_VDL_SNOOP2 :: reserved1 [19:17] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_UPDATE_VDL_SNOOP2_reserved1_MASK 0x000e0000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_UPDATE_VDL_SNOOP2_reserved1_SHIFT 17
-
-/* DDR34_PHY_CONTROL_REGS_0 :: UPDATE_VDL_SNOOP2 :: CMD [16:08] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_UPDATE_VDL_SNOOP2_CMD_MASK 0x0001ff00
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_UPDATE_VDL_SNOOP2_CMD_SHIFT 8
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_UPDATE_VDL_SNOOP2_CMD_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: UPDATE_VDL_SNOOP2 :: reserved2 [07:06] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_UPDATE_VDL_SNOOP2_reserved2_MASK 0x000000c0
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_UPDATE_VDL_SNOOP2_reserved2_SHIFT 6
-
-/* DDR34_PHY_CONTROL_REGS_0 :: UPDATE_VDL_SNOOP2 :: ENABLE [05:00] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_UPDATE_VDL_SNOOP2_ENABLE_MASK 0x0000003f
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_UPDATE_VDL_SNOOP2_ENABLE_SHIFT 0
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_UPDATE_VDL_SNOOP2_ENABLE_DEFAULT 0x00000000
-
-/***************************************************************************
- *COMMAND_REG1 - DRAM Command Register #1
- ***************************************************************************/
-/* DDR34_PHY_CONTROL_REGS_0 :: COMMAND_REG1 :: MCP [31:31] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_REG1_MCP_MASK 0x80000000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_REG1_MCP_SHIFT 31
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_REG1_MCP_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: COMMAND_REG1 :: CS [30:29] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_REG1_CS_MASK 0x60000000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_REG1_CS_SHIFT 29
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_REG1_CS_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: COMMAND_REG1 :: AUX [28:24] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_REG1_AUX_MASK 0x1f000000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_REG1_AUX_SHIFT 24
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_REG1_AUX_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: COMMAND_REG1 :: ACT [23:23] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_REG1_ACT_MASK 0x00800000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_REG1_ACT_SHIFT 23
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_REG1_ACT_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: COMMAND_REG1 :: WE [22:22] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_REG1_WE_MASK 0x00400000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_REG1_WE_SHIFT 22
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_REG1_WE_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: COMMAND_REG1 :: CAS [21:21] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_REG1_CAS_MASK 0x00200000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_REG1_CAS_SHIFT 21
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_REG1_CAS_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: COMMAND_REG1 :: RAS [20:20] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_REG1_RAS_MASK 0x00100000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_REG1_RAS_SHIFT 20
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_REG1_RAS_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: COMMAND_REG1 :: BA [19:16] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_REG1_BA_MASK 0x000f0000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_REG1_BA_SHIFT 16
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_REG1_BA_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: COMMAND_REG1 :: AD [15:00] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_REG1_AD_MASK 0x0000ffff
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_REG1_AD_SHIFT 0
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_REG1_AD_DEFAULT 0x00000000
-
-/***************************************************************************
- *COMMAND_AUX_REG1 - DRAM AUX_N Command Register #1
- ***************************************************************************/
-/* DDR34_PHY_CONTROL_REGS_0 :: COMMAND_AUX_REG1 :: reserved0 [31:06] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_AUX_REG1_reserved0_MASK 0xffffffc0
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_AUX_REG1_reserved0_SHIFT 6
-
-/* DDR34_PHY_CONTROL_REGS_0 :: COMMAND_AUX_REG1 :: AD16 [05:05] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_AUX_REG1_AD16_MASK 0x00000020
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_AUX_REG1_AD16_SHIFT 5
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_AUX_REG1_AD16_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: COMMAND_AUX_REG1 :: AUX [04:00] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_AUX_REG1_AUX_MASK 0x0000001f
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_AUX_REG1_AUX_SHIFT 0
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_AUX_REG1_AUX_DEFAULT 0x00000000
-
-/***************************************************************************
- *COMMAND_REG2 - DRAM Command Register #2
- ***************************************************************************/
-/* DDR34_PHY_CONTROL_REGS_0 :: COMMAND_REG2 :: MCP [31:31] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_REG2_MCP_MASK 0x80000000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_REG2_MCP_SHIFT 31
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_REG2_MCP_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: COMMAND_REG2 :: CS [30:29] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_REG2_CS_MASK 0x60000000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_REG2_CS_SHIFT 29
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_REG2_CS_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: COMMAND_REG2 :: AUX [28:24] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_REG2_AUX_MASK 0x1f000000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_REG2_AUX_SHIFT 24
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_REG2_AUX_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: COMMAND_REG2 :: ACT [23:23] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_REG2_ACT_MASK 0x00800000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_REG2_ACT_SHIFT 23
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_REG2_ACT_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: COMMAND_REG2 :: WE [22:22] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_REG2_WE_MASK 0x00400000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_REG2_WE_SHIFT 22
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_REG2_WE_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: COMMAND_REG2 :: CAS [21:21] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_REG2_CAS_MASK 0x00200000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_REG2_CAS_SHIFT 21
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_REG2_CAS_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: COMMAND_REG2 :: RAS [20:20] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_REG2_RAS_MASK 0x00100000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_REG2_RAS_SHIFT 20
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_REG2_RAS_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: COMMAND_REG2 :: BA [19:16] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_REG2_BA_MASK 0x000f0000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_REG2_BA_SHIFT 16
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_REG2_BA_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: COMMAND_REG2 :: AD [15:00] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_REG2_AD_MASK 0x0000ffff
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_REG2_AD_SHIFT 0
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_REG2_AD_DEFAULT 0x00000000
-
-/***************************************************************************
- *COMMAND_AUX_REG2 - DRAM AUX_N Command Register #2
- ***************************************************************************/
-/* DDR34_PHY_CONTROL_REGS_0 :: COMMAND_AUX_REG2 :: reserved0 [31:06] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_AUX_REG2_reserved0_MASK 0xffffffc0
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_AUX_REG2_reserved0_SHIFT 6
-
-/* DDR34_PHY_CONTROL_REGS_0 :: COMMAND_AUX_REG2 :: AD16 [05:05] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_AUX_REG2_AD16_MASK 0x00000020
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_AUX_REG2_AD16_SHIFT 5
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_AUX_REG2_AD16_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: COMMAND_AUX_REG2 :: AUX [04:00] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_AUX_REG2_AUX_MASK 0x0000001f
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_AUX_REG2_AUX_SHIFT 0
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_AUX_REG2_AUX_DEFAULT 0x00000000
-
-/***************************************************************************
- *COMMAND_REG3 - DRAM Command Register #3
- ***************************************************************************/
-/* DDR34_PHY_CONTROL_REGS_0 :: COMMAND_REG3 :: MCP [31:31] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_REG3_MCP_MASK 0x80000000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_REG3_MCP_SHIFT 31
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_REG3_MCP_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: COMMAND_REG3 :: CS [30:29] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_REG3_CS_MASK 0x60000000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_REG3_CS_SHIFT 29
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_REG3_CS_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: COMMAND_REG3 :: AUX [28:24] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_REG3_AUX_MASK 0x1f000000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_REG3_AUX_SHIFT 24
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_REG3_AUX_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: COMMAND_REG3 :: ACT [23:23] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_REG3_ACT_MASK 0x00800000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_REG3_ACT_SHIFT 23
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_REG3_ACT_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: COMMAND_REG3 :: WE [22:22] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_REG3_WE_MASK 0x00400000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_REG3_WE_SHIFT 22
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_REG3_WE_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: COMMAND_REG3 :: CAS [21:21] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_REG3_CAS_MASK 0x00200000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_REG3_CAS_SHIFT 21
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_REG3_CAS_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: COMMAND_REG3 :: RAS [20:20] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_REG3_RAS_MASK 0x00100000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_REG3_RAS_SHIFT 20
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_REG3_RAS_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: COMMAND_REG3 :: BA [19:16] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_REG3_BA_MASK 0x000f0000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_REG3_BA_SHIFT 16
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_REG3_BA_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: COMMAND_REG3 :: AD [15:00] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_REG3_AD_MASK 0x0000ffff
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_REG3_AD_SHIFT 0
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_REG3_AD_DEFAULT 0x00000000
-
-/***************************************************************************
- *COMMAND_AUX_REG3 - DRAM AUX_N Command Register #3
- ***************************************************************************/
-/* DDR34_PHY_CONTROL_REGS_0 :: COMMAND_AUX_REG3 :: reserved0 [31:06] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_AUX_REG3_reserved0_MASK 0xffffffc0
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_AUX_REG3_reserved0_SHIFT 6
-
-/* DDR34_PHY_CONTROL_REGS_0 :: COMMAND_AUX_REG3 :: AD16 [05:05] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_AUX_REG3_AD16_MASK 0x00000020
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_AUX_REG3_AD16_SHIFT 5
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_AUX_REG3_AD16_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: COMMAND_AUX_REG3 :: AUX [04:00] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_AUX_REG3_AUX_MASK 0x0000001f
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_AUX_REG3_AUX_SHIFT 0
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_AUX_REG3_AUX_DEFAULT 0x00000000
-
-/***************************************************************************
- *COMMAND_REG4 - DRAM Command Register #4
- ***************************************************************************/
-/* DDR34_PHY_CONTROL_REGS_0 :: COMMAND_REG4 :: MCP [31:31] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_REG4_MCP_MASK 0x80000000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_REG4_MCP_SHIFT 31
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_REG4_MCP_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: COMMAND_REG4 :: CS [30:29] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_REG4_CS_MASK 0x60000000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_REG4_CS_SHIFT 29
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_REG4_CS_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: COMMAND_REG4 :: AUX [28:24] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_REG4_AUX_MASK 0x1f000000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_REG4_AUX_SHIFT 24
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_REG4_AUX_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: COMMAND_REG4 :: ACT [23:23] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_REG4_ACT_MASK 0x00800000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_REG4_ACT_SHIFT 23
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_REG4_ACT_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: COMMAND_REG4 :: WE [22:22] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_REG4_WE_MASK 0x00400000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_REG4_WE_SHIFT 22
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_REG4_WE_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: COMMAND_REG4 :: CAS [21:21] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_REG4_CAS_MASK 0x00200000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_REG4_CAS_SHIFT 21
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_REG4_CAS_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: COMMAND_REG4 :: RAS [20:20] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_REG4_RAS_MASK 0x00100000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_REG4_RAS_SHIFT 20
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_REG4_RAS_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: COMMAND_REG4 :: BA [19:16] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_REG4_BA_MASK 0x000f0000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_REG4_BA_SHIFT 16
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_REG4_BA_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: COMMAND_REG4 :: AD [15:00] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_REG4_AD_MASK 0x0000ffff
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_REG4_AD_SHIFT 0
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_REG4_AD_DEFAULT 0x00000000
-
-/***************************************************************************
- *COMMAND_AUX_REG4 - DRAM AUX_N Command Register #4
- ***************************************************************************/
-/* DDR34_PHY_CONTROL_REGS_0 :: COMMAND_AUX_REG4 :: reserved0 [31:06] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_AUX_REG4_reserved0_MASK 0xffffffc0
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_AUX_REG4_reserved0_SHIFT 6
-
-/* DDR34_PHY_CONTROL_REGS_0 :: COMMAND_AUX_REG4 :: AD16 [05:05] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_AUX_REG4_AD16_MASK 0x00000020
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_AUX_REG4_AD16_SHIFT 5
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_AUX_REG4_AD16_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: COMMAND_AUX_REG4 :: AUX [04:00] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_AUX_REG4_AUX_MASK 0x0000001f
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_AUX_REG4_AUX_SHIFT 0
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_AUX_REG4_AUX_DEFAULT 0x00000000
-
-/***************************************************************************
- *COMMAND_REG_TIMER - DRAM Command Timer Register
- ***************************************************************************/
-/* DDR34_PHY_CONTROL_REGS_0 :: COMMAND_REG_TIMER :: reserved0 [31:16] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_REG_TIMER_reserved0_MASK 0xffff0000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_REG_TIMER_reserved0_SHIFT 16
-
-/* DDR34_PHY_CONTROL_REGS_0 :: COMMAND_REG_TIMER :: INIT_VAL [15:08] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_REG_TIMER_INIT_VAL_MASK 0x0000ff00
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_REG_TIMER_INIT_VAL_SHIFT 8
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_REG_TIMER_INIT_VAL_DEFAULT 0x0000000f
-
-/* DDR34_PHY_CONTROL_REGS_0 :: COMMAND_REG_TIMER :: COUNT [07:00] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_REG_TIMER_COUNT_MASK 0x000000ff
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_REG_TIMER_COUNT_SHIFT 0
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_REG_TIMER_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *MODE_REG0 - DDR3/DDR4/GDDR5 Mode Register 0 and LPDDR Mode Register 1
- ***************************************************************************/
-/* DDR34_PHY_CONTROL_REGS_0 :: MODE_REG0 :: reserved0 [31:21] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_MODE_REG0_reserved0_MASK 0xffe00000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_MODE_REG0_reserved0_SHIFT 21
-
-/* DDR34_PHY_CONTROL_REGS_0 :: MODE_REG0 :: reserved_for_eco1 [20:17] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_MODE_REG0_reserved_for_eco1_MASK 0x001e0000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_MODE_REG0_reserved_for_eco1_SHIFT 17
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_MODE_REG0_reserved_for_eco1_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: MODE_REG0 :: VALID [16:16] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_MODE_REG0_VALID_MASK 0x00010000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_MODE_REG0_VALID_SHIFT 16
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_MODE_REG0_VALID_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: MODE_REG0 :: AD [15:00] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_MODE_REG0_AD_MASK 0x0000ffff
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_MODE_REG0_AD_SHIFT 0
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_MODE_REG0_AD_DEFAULT 0x00000000
-
-/***************************************************************************
- *MODE_REG1 - DDR3/DDR4/GDDR5 Mode Register 1 and LPDDR Mode Register 2
- ***************************************************************************/
-/* DDR34_PHY_CONTROL_REGS_0 :: MODE_REG1 :: reserved0 [31:21] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_MODE_REG1_reserved0_MASK 0xffe00000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_MODE_REG1_reserved0_SHIFT 21
-
-/* DDR34_PHY_CONTROL_REGS_0 :: MODE_REG1 :: reserved_for_eco1 [20:17] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_MODE_REG1_reserved_for_eco1_MASK 0x001e0000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_MODE_REG1_reserved_for_eco1_SHIFT 17
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_MODE_REG1_reserved_for_eco1_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: MODE_REG1 :: VALID [16:16] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_MODE_REG1_VALID_MASK 0x00010000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_MODE_REG1_VALID_SHIFT 16
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_MODE_REG1_VALID_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: MODE_REG1 :: AD [15:00] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_MODE_REG1_AD_MASK 0x0000ffff
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_MODE_REG1_AD_SHIFT 0
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_MODE_REG1_AD_DEFAULT 0x00000000
-
-/***************************************************************************
- *MODE_REG2 - DDR3/DDR4/GDDR5 Mode Register 2 and LPDDR Mode Register 3
- ***************************************************************************/
-/* DDR34_PHY_CONTROL_REGS_0 :: MODE_REG2 :: reserved0 [31:21] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_MODE_REG2_reserved0_MASK 0xffe00000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_MODE_REG2_reserved0_SHIFT 21
-
-/* DDR34_PHY_CONTROL_REGS_0 :: MODE_REG2 :: reserved_for_eco1 [20:17] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_MODE_REG2_reserved_for_eco1_MASK 0x001e0000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_MODE_REG2_reserved_for_eco1_SHIFT 17
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_MODE_REG2_reserved_for_eco1_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: MODE_REG2 :: VALID [16:16] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_MODE_REG2_VALID_MASK 0x00010000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_MODE_REG2_VALID_SHIFT 16
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_MODE_REG2_VALID_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: MODE_REG2 :: AD [15:00] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_MODE_REG2_AD_MASK 0x0000ffff
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_MODE_REG2_AD_SHIFT 0
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_MODE_REG2_AD_DEFAULT 0x00000000
-
-/***************************************************************************
- *MODE_REG3 - DDR3/DDR4/GDDR5 Mode Register 3 and LPDDR Mode Register 9
- ***************************************************************************/
-/* DDR34_PHY_CONTROL_REGS_0 :: MODE_REG3 :: reserved0 [31:21] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_MODE_REG3_reserved0_MASK 0xffe00000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_MODE_REG3_reserved0_SHIFT 21
-
-/* DDR34_PHY_CONTROL_REGS_0 :: MODE_REG3 :: reserved_for_eco1 [20:17] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_MODE_REG3_reserved_for_eco1_MASK 0x001e0000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_MODE_REG3_reserved_for_eco1_SHIFT 17
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_MODE_REG3_reserved_for_eco1_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: MODE_REG3 :: VALID [16:16] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_MODE_REG3_VALID_MASK 0x00010000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_MODE_REG3_VALID_SHIFT 16
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_MODE_REG3_VALID_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: MODE_REG3 :: AD [15:00] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_MODE_REG3_AD_MASK 0x0000ffff
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_MODE_REG3_AD_SHIFT 0
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_MODE_REG3_AD_DEFAULT 0x00000000
-
-/***************************************************************************
- *MODE_REG4 - DDR4/GDDR5 Mode Register 4 and LPDDR Mode Register 10
- ***************************************************************************/
-/* DDR34_PHY_CONTROL_REGS_0 :: MODE_REG4 :: reserved0 [31:21] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_MODE_REG4_reserved0_MASK 0xffe00000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_MODE_REG4_reserved0_SHIFT 21
-
-/* DDR34_PHY_CONTROL_REGS_0 :: MODE_REG4 :: reserved_for_eco1 [20:17] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_MODE_REG4_reserved_for_eco1_MASK 0x001e0000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_MODE_REG4_reserved_for_eco1_SHIFT 17
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_MODE_REG4_reserved_for_eco1_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: MODE_REG4 :: VALID [16:16] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_MODE_REG4_VALID_MASK 0x00010000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_MODE_REG4_VALID_SHIFT 16
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_MODE_REG4_VALID_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: MODE_REG4 :: AD [15:00] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_MODE_REG4_AD_MASK 0x0000ffff
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_MODE_REG4_AD_SHIFT 0
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_MODE_REG4_AD_DEFAULT 0x00000000
-
-/***************************************************************************
- *MODE_REG5 - DDR4/GDDR5 Mode Register 5 and LPDDR Mode Register 16
- ***************************************************************************/
-/* DDR34_PHY_CONTROL_REGS_0 :: MODE_REG5 :: reserved0 [31:21] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_MODE_REG5_reserved0_MASK 0xffe00000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_MODE_REG5_reserved0_SHIFT 21
-
-/* DDR34_PHY_CONTROL_REGS_0 :: MODE_REG5 :: reserved_for_eco1 [20:17] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_MODE_REG5_reserved_for_eco1_MASK 0x001e0000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_MODE_REG5_reserved_for_eco1_SHIFT 17
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_MODE_REG5_reserved_for_eco1_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: MODE_REG5 :: VALID [16:16] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_MODE_REG5_VALID_MASK 0x00010000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_MODE_REG5_VALID_SHIFT 16
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_MODE_REG5_VALID_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: MODE_REG5 :: AD [15:00] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_MODE_REG5_AD_MASK 0x0000ffff
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_MODE_REG5_AD_SHIFT 0
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_MODE_REG5_AD_DEFAULT 0x00000000
-
-/***************************************************************************
- *MODE_REG6 - DDR4/GDDR5 Mode Register 6 and LPDDR Mode Register 17
- ***************************************************************************/
-/* DDR34_PHY_CONTROL_REGS_0 :: MODE_REG6 :: reserved0 [31:21] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_MODE_REG6_reserved0_MASK 0xffe00000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_MODE_REG6_reserved0_SHIFT 21
-
-/* DDR34_PHY_CONTROL_REGS_0 :: MODE_REG6 :: reserved_for_eco1 [20:17] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_MODE_REG6_reserved_for_eco1_MASK 0x001e0000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_MODE_REG6_reserved_for_eco1_SHIFT 17
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_MODE_REG6_reserved_for_eco1_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: MODE_REG6 :: VALID [16:16] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_MODE_REG6_VALID_MASK 0x00010000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_MODE_REG6_VALID_SHIFT 16
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_MODE_REG6_VALID_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: MODE_REG6 :: AD [15:00] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_MODE_REG6_AD_MASK 0x0000ffff
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_MODE_REG6_AD_SHIFT 0
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_MODE_REG6_AD_DEFAULT 0x00000000
-
-/***************************************************************************
- *MODE_REG7 - DDR4/GDDR5 Mode Register 7 and LPDDR Mode Register 41
- ***************************************************************************/
-/* DDR34_PHY_CONTROL_REGS_0 :: MODE_REG7 :: reserved0 [31:21] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_MODE_REG7_reserved0_MASK 0xffe00000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_MODE_REG7_reserved0_SHIFT 21
-
-/* DDR34_PHY_CONTROL_REGS_0 :: MODE_REG7 :: reserved_for_eco1 [20:17] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_MODE_REG7_reserved_for_eco1_MASK 0x001e0000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_MODE_REG7_reserved_for_eco1_SHIFT 17
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_MODE_REG7_reserved_for_eco1_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: MODE_REG7 :: VALID [16:16] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_MODE_REG7_VALID_MASK 0x00010000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_MODE_REG7_VALID_SHIFT 16
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_MODE_REG7_VALID_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: MODE_REG7 :: AD [15:00] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_MODE_REG7_AD_MASK 0x0000ffff
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_MODE_REG7_AD_SHIFT 0
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_MODE_REG7_AD_DEFAULT 0x00000000
-
-/***************************************************************************
- *MODE_REG8 - GDDR5 Mode Register 8 and LPDDR Mode Register 42
- ***************************************************************************/
-/* DDR34_PHY_CONTROL_REGS_0 :: MODE_REG8 :: reserved0 [31:21] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_MODE_REG8_reserved0_MASK 0xffe00000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_MODE_REG8_reserved0_SHIFT 21
-
-/* DDR34_PHY_CONTROL_REGS_0 :: MODE_REG8 :: reserved_for_eco1 [20:17] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_MODE_REG8_reserved_for_eco1_MASK 0x001e0000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_MODE_REG8_reserved_for_eco1_SHIFT 17
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_MODE_REG8_reserved_for_eco1_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: MODE_REG8 :: VALID [16:16] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_MODE_REG8_VALID_MASK 0x00010000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_MODE_REG8_VALID_SHIFT 16
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_MODE_REG8_VALID_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: MODE_REG8 :: AD [15:00] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_MODE_REG8_AD_MASK 0x0000ffff
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_MODE_REG8_AD_SHIFT 0
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_MODE_REG8_AD_DEFAULT 0x00000000
-
-/***************************************************************************
- *MODE_REG15 - GDDR5 Mode Register 15 and LPDDR Mode Register 48
- ***************************************************************************/
-/* DDR34_PHY_CONTROL_REGS_0 :: MODE_REG15 :: reserved0 [31:21] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_MODE_REG15_reserved0_MASK 0xffe00000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_MODE_REG15_reserved0_SHIFT 21
-
-/* DDR34_PHY_CONTROL_REGS_0 :: MODE_REG15 :: reserved_for_eco1 [20:17] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_MODE_REG15_reserved_for_eco1_MASK 0x001e0000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_MODE_REG15_reserved_for_eco1_SHIFT 17
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_MODE_REG15_reserved_for_eco1_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: MODE_REG15 :: VALID [16:16] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_MODE_REG15_VALID_MASK 0x00010000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_MODE_REG15_VALID_SHIFT 16
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_MODE_REG15_VALID_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: MODE_REG15 :: AD [15:00] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_MODE_REG15_AD_MASK 0x0000ffff
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_MODE_REG15_AD_SHIFT 0
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_MODE_REG15_AD_DEFAULT 0x00000000
-
-/***************************************************************************
- *MODE_REG63 - LPDDR Mode Register 63
- ***************************************************************************/
-/* DDR34_PHY_CONTROL_REGS_0 :: MODE_REG63 :: reserved0 [31:21] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_MODE_REG63_reserved0_MASK 0xffe00000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_MODE_REG63_reserved0_SHIFT 21
-
-/* DDR34_PHY_CONTROL_REGS_0 :: MODE_REG63 :: reserved_for_eco1 [20:17] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_MODE_REG63_reserved_for_eco1_MASK 0x001e0000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_MODE_REG63_reserved_for_eco1_SHIFT 17
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_MODE_REG63_reserved_for_eco1_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: MODE_REG63 :: VALID [16:16] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_MODE_REG63_VALID_MASK 0x00010000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_MODE_REG63_VALID_SHIFT 16
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_MODE_REG63_VALID_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: MODE_REG63 :: AD [15:00] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_MODE_REG63_AD_MASK 0x0000ffff
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_MODE_REG63_AD_SHIFT 0
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_MODE_REG63_AD_DEFAULT 0x00000000
-
-/***************************************************************************
- *ALERT_CLEAR - DDR4 Alert status clear register
- ***************************************************************************/
-/* DDR34_PHY_CONTROL_REGS_0 :: ALERT_CLEAR :: reserved0 [31:01] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_ALERT_CLEAR_reserved0_MASK 0xfffffffe
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_ALERT_CLEAR_reserved0_SHIFT 1
-
-/* DDR34_PHY_CONTROL_REGS_0 :: ALERT_CLEAR :: CLEAR [00:00] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_ALERT_CLEAR_CLEAR_MASK 0x00000001
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_ALERT_CLEAR_CLEAR_SHIFT 0
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_ALERT_CLEAR_CLEAR_DEFAULT 0x00000000
-
-/***************************************************************************
- *ALERT_STATUS - DDR4 Alert status register
- ***************************************************************************/
-/* DDR34_PHY_CONTROL_REGS_0 :: ALERT_STATUS :: reserved0 [31:13] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_ALERT_STATUS_reserved0_MASK 0xffffe000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_ALERT_STATUS_reserved0_SHIFT 13
-
-/* DDR34_PHY_CONTROL_REGS_0 :: ALERT_STATUS :: BL4_STATE [12:12] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_ALERT_STATUS_BL4_STATE_MASK 0x00001000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_ALERT_STATUS_BL4_STATE_SHIFT 12
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_ALERT_STATUS_BL4_STATE_DEFAULT 0x00000001
-
-/* DDR34_PHY_CONTROL_REGS_0 :: ALERT_STATUS :: BL3_STATE [11:11] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_ALERT_STATUS_BL3_STATE_MASK 0x00000800
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_ALERT_STATUS_BL3_STATE_SHIFT 11
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_ALERT_STATUS_BL3_STATE_DEFAULT 0x00000001
-
-/* DDR34_PHY_CONTROL_REGS_0 :: ALERT_STATUS :: BL2_STATE [10:10] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_ALERT_STATUS_BL2_STATE_MASK 0x00000400
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_ALERT_STATUS_BL2_STATE_SHIFT 10
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_ALERT_STATUS_BL2_STATE_DEFAULT 0x00000001
-
-/* DDR34_PHY_CONTROL_REGS_0 :: ALERT_STATUS :: BL1_STATE [09:09] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_ALERT_STATUS_BL1_STATE_MASK 0x00000200
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_ALERT_STATUS_BL1_STATE_SHIFT 9
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_ALERT_STATUS_BL1_STATE_DEFAULT 0x00000001
-
-/* DDR34_PHY_CONTROL_REGS_0 :: ALERT_STATUS :: BL0_STATE [08:08] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_ALERT_STATUS_BL0_STATE_MASK 0x00000100
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_ALERT_STATUS_BL0_STATE_SHIFT 8
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_ALERT_STATUS_BL0_STATE_DEFAULT 0x00000001
-
-/* DDR34_PHY_CONTROL_REGS_0 :: ALERT_STATUS :: reserved1 [07:05] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_ALERT_STATUS_reserved1_MASK 0x000000e0
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_ALERT_STATUS_reserved1_SHIFT 5
-
-/* DDR34_PHY_CONTROL_REGS_0 :: ALERT_STATUS :: BL4_ALERT [04:04] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_ALERT_STATUS_BL4_ALERT_MASK 0x00000010
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_ALERT_STATUS_BL4_ALERT_SHIFT 4
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_ALERT_STATUS_BL4_ALERT_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: ALERT_STATUS :: BL3_ALERT [03:03] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_ALERT_STATUS_BL3_ALERT_MASK 0x00000008
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_ALERT_STATUS_BL3_ALERT_SHIFT 3
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_ALERT_STATUS_BL3_ALERT_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: ALERT_STATUS :: BL2_ALERT [02:02] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_ALERT_STATUS_BL2_ALERT_MASK 0x00000004
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_ALERT_STATUS_BL2_ALERT_SHIFT 2
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_ALERT_STATUS_BL2_ALERT_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: ALERT_STATUS :: BL1_ALERT [01:01] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_ALERT_STATUS_BL1_ALERT_MASK 0x00000002
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_ALERT_STATUS_BL1_ALERT_SHIFT 1
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_ALERT_STATUS_BL1_ALERT_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: ALERT_STATUS :: BL0_ALERT [00:00] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_ALERT_STATUS_BL0_ALERT_MASK 0x00000001
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_ALERT_STATUS_BL0_ALERT_SHIFT 0
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_ALERT_STATUS_BL0_ALERT_DEFAULT 0x00000000
-
-/***************************************************************************
- *ALERT_DFI - DDR4 Alert DFI BL mask
- ***************************************************************************/
-/* DDR34_PHY_CONTROL_REGS_0 :: ALERT_DFI :: reserved0 [31:05] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_ALERT_DFI_reserved0_MASK 0xffffffe0
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_ALERT_DFI_reserved0_SHIFT 5
-
-/* DDR34_PHY_CONTROL_REGS_0 :: ALERT_DFI :: MASK [04:00] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_ALERT_DFI_MASK_MASK 0x0000001f
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_ALERT_DFI_MASK_SHIFT 0
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_ALERT_DFI_MASK_DEFAULT 0x00000000
-
-/***************************************************************************
- *CA_PLAYBACK_CONTROL - GDDR5 CA playback control register
- ***************************************************************************/
-/* DDR34_PHY_CONTROL_REGS_0 :: CA_PLAYBACK_CONTROL :: reserved0 [31:12] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_CA_PLAYBACK_CONTROL_reserved0_MASK 0xfffff000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_CA_PLAYBACK_CONTROL_reserved0_SHIFT 12
-
-/* DDR34_PHY_CONTROL_REGS_0 :: CA_PLAYBACK_CONTROL :: COUNT [11:04] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_CA_PLAYBACK_CONTROL_COUNT_MASK 0x00000ff0
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_CA_PLAYBACK_CONTROL_COUNT_SHIFT 4
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_CA_PLAYBACK_CONTROL_COUNT_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: CA_PLAYBACK_CONTROL :: reserved1 [03:01] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_CA_PLAYBACK_CONTROL_reserved1_MASK 0x0000000e
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_CA_PLAYBACK_CONTROL_reserved1_SHIFT 1
-
-/* DDR34_PHY_CONTROL_REGS_0 :: CA_PLAYBACK_CONTROL :: SAMPLE [00:00] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_CA_PLAYBACK_CONTROL_SAMPLE_MASK 0x00000001
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_CA_PLAYBACK_CONTROL_SAMPLE_SHIFT 0
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_CA_PLAYBACK_CONTROL_SAMPLE_DEFAULT 0x00000000
-
-/***************************************************************************
- *CA_PLAYBACK_STATUS0 - LPDDR3 and GDDR5 CA playback status register0 (for BL0 and BL1)
- ***************************************************************************/
-/* DDR34_PHY_CONTROL_REGS_0 :: CA_PLAYBACK_STATUS0 :: VALID [31:31] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_CA_PLAYBACK_STATUS0_VALID_MASK 0x80000000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_CA_PLAYBACK_STATUS0_VALID_SHIFT 31
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_CA_PLAYBACK_STATUS0_VALID_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: CA_PLAYBACK_STATUS0 :: reserved0 [30:26] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_CA_PLAYBACK_STATUS0_reserved0_MASK 0x7c000000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_CA_PLAYBACK_STATUS0_reserved0_SHIFT 26
-
-/* DDR34_PHY_CONTROL_REGS_0 :: CA_PLAYBACK_STATUS0 :: DATA1 [25:16] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_CA_PLAYBACK_STATUS0_DATA1_MASK 0x03ff0000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_CA_PLAYBACK_STATUS0_DATA1_SHIFT 16
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_CA_PLAYBACK_STATUS0_DATA1_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: CA_PLAYBACK_STATUS0 :: reserved1 [15:10] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_CA_PLAYBACK_STATUS0_reserved1_MASK 0x0000fc00
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_CA_PLAYBACK_STATUS0_reserved1_SHIFT 10
-
-/* DDR34_PHY_CONTROL_REGS_0 :: CA_PLAYBACK_STATUS0 :: DATA0 [09:00] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_CA_PLAYBACK_STATUS0_DATA0_MASK 0x000003ff
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_CA_PLAYBACK_STATUS0_DATA0_SHIFT 0
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_CA_PLAYBACK_STATUS0_DATA0_DEFAULT 0x00000000
-
-/***************************************************************************
- *CA_PLAYBACK_STATUS1 - LPDDR3 and GDDR5 CA playback status register1 (for BL2 and BL3)
- ***************************************************************************/
-/* DDR34_PHY_CONTROL_REGS_0 :: CA_PLAYBACK_STATUS1 :: VALID [31:31] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_CA_PLAYBACK_STATUS1_VALID_MASK 0x80000000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_CA_PLAYBACK_STATUS1_VALID_SHIFT 31
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_CA_PLAYBACK_STATUS1_VALID_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: CA_PLAYBACK_STATUS1 :: reserved0 [30:26] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_CA_PLAYBACK_STATUS1_reserved0_MASK 0x7c000000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_CA_PLAYBACK_STATUS1_reserved0_SHIFT 26
-
-/* DDR34_PHY_CONTROL_REGS_0 :: CA_PLAYBACK_STATUS1 :: DATA1 [25:16] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_CA_PLAYBACK_STATUS1_DATA1_MASK 0x03ff0000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_CA_PLAYBACK_STATUS1_DATA1_SHIFT 16
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_CA_PLAYBACK_STATUS1_DATA1_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: CA_PLAYBACK_STATUS1 :: reserved1 [15:10] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_CA_PLAYBACK_STATUS1_reserved1_MASK 0x0000fc00
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_CA_PLAYBACK_STATUS1_reserved1_SHIFT 10
-
-/* DDR34_PHY_CONTROL_REGS_0 :: CA_PLAYBACK_STATUS1 :: DATA0 [09:00] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_CA_PLAYBACK_STATUS1_DATA0_MASK 0x000003ff
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_CA_PLAYBACK_STATUS1_DATA0_SHIFT 0
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_CA_PLAYBACK_STATUS1_DATA0_DEFAULT 0x00000000
-
-/***************************************************************************
- *WRITE_LEVELING_CONTROL - Write leveling control register
- ***************************************************************************/
-/* DDR34_PHY_CONTROL_REGS_0 :: WRITE_LEVELING_CONTROL :: reserved0 [31:20] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_WRITE_LEVELING_CONTROL_reserved0_MASK 0xfff00000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_WRITE_LEVELING_CONTROL_reserved0_SHIFT 20
-
-/* DDR34_PHY_CONTROL_REGS_0 :: WRITE_LEVELING_CONTROL :: reserved_for_eco1 [19:16] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_WRITE_LEVELING_CONTROL_reserved_for_eco1_MASK 0x000f0000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_WRITE_LEVELING_CONTROL_reserved_for_eco1_SHIFT 16
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_WRITE_LEVELING_CONTROL_reserved_for_eco1_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: WRITE_LEVELING_CONTROL :: COUNT [15:08] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_WRITE_LEVELING_CONTROL_COUNT_MASK 0x0000ff00
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_WRITE_LEVELING_CONTROL_COUNT_SHIFT 8
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_WRITE_LEVELING_CONTROL_COUNT_DEFAULT 0x0000000f
-
-/* DDR34_PHY_CONTROL_REGS_0 :: WRITE_LEVELING_CONTROL :: reserved2 [07:03] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_WRITE_LEVELING_CONTROL_reserved2_MASK 0x000000f8
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_WRITE_LEVELING_CONTROL_reserved2_SHIFT 3
-
-/* DDR34_PHY_CONTROL_REGS_0 :: WRITE_LEVELING_CONTROL :: SAMPLE [02:02] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_WRITE_LEVELING_CONTROL_SAMPLE_MASK 0x00000004
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_WRITE_LEVELING_CONTROL_SAMPLE_SHIFT 2
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_WRITE_LEVELING_CONTROL_SAMPLE_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: WRITE_LEVELING_CONTROL :: CONTINUOUS [01:01] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_WRITE_LEVELING_CONTROL_CONTINUOUS_MASK 0x00000002
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_WRITE_LEVELING_CONTROL_CONTINUOUS_SHIFT 1
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_WRITE_LEVELING_CONTROL_CONTINUOUS_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: WRITE_LEVELING_CONTROL :: ENABLE [00:00] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_WRITE_LEVELING_CONTROL_ENABLE_MASK 0x00000001
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_WRITE_LEVELING_CONTROL_ENABLE_SHIFT 0
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_WRITE_LEVELING_CONTROL_ENABLE_DEFAULT 0x00000000
-
-/***************************************************************************
- *WRITE_LEVELING_STATUS - Write leveling status register
- ***************************************************************************/
-/* DDR34_PHY_CONTROL_REGS_0 :: WRITE_LEVELING_STATUS :: reserved0 [31:14] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_WRITE_LEVELING_STATUS_reserved0_MASK 0xffffc000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_WRITE_LEVELING_STATUS_reserved0_SHIFT 14
-
-/* DDR34_PHY_CONTROL_REGS_0 :: WRITE_LEVELING_STATUS :: EDC [13:09] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_WRITE_LEVELING_STATUS_EDC_MASK 0x00003e00
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_WRITE_LEVELING_STATUS_EDC_SHIFT 9
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_WRITE_LEVELING_STATUS_EDC_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: WRITE_LEVELING_STATUS :: STATUS [08:04] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_WRITE_LEVELING_STATUS_STATUS_MASK 0x000001f0
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_WRITE_LEVELING_STATUS_STATUS_SHIFT 4
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_WRITE_LEVELING_STATUS_STATUS_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: WRITE_LEVELING_STATUS :: reserved1 [03:01] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_WRITE_LEVELING_STATUS_reserved1_MASK 0x0000000e
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_WRITE_LEVELING_STATUS_reserved1_SHIFT 1
-
-/* DDR34_PHY_CONTROL_REGS_0 :: WRITE_LEVELING_STATUS :: VALID [00:00] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_WRITE_LEVELING_STATUS_VALID_MASK 0x00000001
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_WRITE_LEVELING_STATUS_VALID_SHIFT 0
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_WRITE_LEVELING_STATUS_VALID_DEFAULT 0x00000000
-
-/***************************************************************************
- *READ_ENABLE_CONTROL - Read enable test cycle control register
- ***************************************************************************/
-/* DDR34_PHY_CONTROL_REGS_0 :: READ_ENABLE_CONTROL :: reserved0 [31:13] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_READ_ENABLE_CONTROL_reserved0_MASK 0xffffe000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_READ_ENABLE_CONTROL_reserved0_SHIFT 13
-
-/* DDR34_PHY_CONTROL_REGS_0 :: READ_ENABLE_CONTROL :: TEST_CYCLE [12:12] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_READ_ENABLE_CONTROL_TEST_CYCLE_MASK 0x00001000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_READ_ENABLE_CONTROL_TEST_CYCLE_SHIFT 12
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_READ_ENABLE_CONTROL_TEST_CYCLE_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: READ_ENABLE_CONTROL :: SELECT [11:08] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_READ_ENABLE_CONTROL_SELECT_MASK 0x00000f00
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_READ_ENABLE_CONTROL_SELECT_SHIFT 8
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_READ_ENABLE_CONTROL_SELECT_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: READ_ENABLE_CONTROL :: reserved_for_eco1 [07:06] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_READ_ENABLE_CONTROL_reserved_for_eco1_MASK 0x000000c0
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_READ_ENABLE_CONTROL_reserved_for_eco1_SHIFT 6
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_READ_ENABLE_CONTROL_reserved_for_eco1_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: READ_ENABLE_CONTROL :: CS_N [05:04] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_READ_ENABLE_CONTROL_CS_N_MASK 0x00000030
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_READ_ENABLE_CONTROL_CS_N_SHIFT 4
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_READ_ENABLE_CONTROL_CS_N_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: READ_ENABLE_CONTROL :: EDC_DATA [03:03] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_READ_ENABLE_CONTROL_EDC_DATA_MASK 0x00000008
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_READ_ENABLE_CONTROL_EDC_DATA_SHIFT 3
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_READ_ENABLE_CONTROL_EDC_DATA_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: READ_ENABLE_CONTROL :: EDC_PHASE [02:02] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_READ_ENABLE_CONTROL_EDC_PHASE_MASK 0x00000004
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_READ_ENABLE_CONTROL_EDC_PHASE_SHIFT 2
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_READ_ENABLE_CONTROL_EDC_PHASE_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: READ_ENABLE_CONTROL :: DQS [01:01] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_READ_ENABLE_CONTROL_DQS_MASK 0x00000002
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_READ_ENABLE_CONTROL_DQS_SHIFT 1
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_READ_ENABLE_CONTROL_DQS_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: READ_ENABLE_CONTROL :: ENABLE [00:00] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_READ_ENABLE_CONTROL_ENABLE_MASK 0x00000001
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_READ_ENABLE_CONTROL_ENABLE_SHIFT 0
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_READ_ENABLE_CONTROL_ENABLE_DEFAULT 0x00000000
-
-/***************************************************************************
- *READ_ENABLE_STATUS - Read enable test cycle status register
- ***************************************************************************/
-/* DDR34_PHY_CONTROL_REGS_0 :: READ_ENABLE_STATUS :: reserved0 [31:20] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_READ_ENABLE_STATUS_reserved0_MASK 0xfff00000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_READ_ENABLE_STATUS_reserved0_SHIFT 20
-
-/* DDR34_PHY_CONTROL_REGS_0 :: READ_ENABLE_STATUS :: DATA [19:12] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_READ_ENABLE_STATUS_DATA_MASK 0x000ff000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_READ_ENABLE_STATUS_DATA_SHIFT 12
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_READ_ENABLE_STATUS_DATA_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: READ_ENABLE_STATUS :: reserved1 [11:09] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_READ_ENABLE_STATUS_reserved1_MASK 0x00000e00
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_READ_ENABLE_STATUS_reserved1_SHIFT 9
-
-/* DDR34_PHY_CONTROL_REGS_0 :: READ_ENABLE_STATUS :: BL4_STATUS [08:08] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_READ_ENABLE_STATUS_BL4_STATUS_MASK 0x00000100
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_READ_ENABLE_STATUS_BL4_STATUS_SHIFT 8
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_READ_ENABLE_STATUS_BL4_STATUS_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: READ_ENABLE_STATUS :: BL3_STATUS [07:07] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_READ_ENABLE_STATUS_BL3_STATUS_MASK 0x00000080
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_READ_ENABLE_STATUS_BL3_STATUS_SHIFT 7
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_READ_ENABLE_STATUS_BL3_STATUS_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: READ_ENABLE_STATUS :: BL2_STATUS [06:06] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_READ_ENABLE_STATUS_BL2_STATUS_MASK 0x00000040
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_READ_ENABLE_STATUS_BL2_STATUS_SHIFT 6
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_READ_ENABLE_STATUS_BL2_STATUS_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: READ_ENABLE_STATUS :: BL1_STATUS [05:05] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_READ_ENABLE_STATUS_BL1_STATUS_MASK 0x00000020
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_READ_ENABLE_STATUS_BL1_STATUS_SHIFT 5
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_READ_ENABLE_STATUS_BL1_STATUS_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: READ_ENABLE_STATUS :: BL0_STATUS [04:04] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_READ_ENABLE_STATUS_BL0_STATUS_MASK 0x00000010
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_READ_ENABLE_STATUS_BL0_STATUS_SHIFT 4
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_READ_ENABLE_STATUS_BL0_STATUS_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: READ_ENABLE_STATUS :: reserved2 [03:01] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_READ_ENABLE_STATUS_reserved2_MASK 0x0000000e
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_READ_ENABLE_STATUS_reserved2_SHIFT 1
-
-/* DDR34_PHY_CONTROL_REGS_0 :: READ_ENABLE_STATUS :: VALID [00:00] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_READ_ENABLE_STATUS_VALID_MASK 0x00000001
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_READ_ENABLE_STATUS_VALID_SHIFT 0
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_READ_ENABLE_STATUS_VALID_DEFAULT 0x00000000
-
-/***************************************************************************
- *VIRTUAL_VTT_CONTROL - Virtual VTT Control and Status register
- ***************************************************************************/
-/* DDR34_PHY_CONTROL_REGS_0 :: VIRTUAL_VTT_CONTROL :: reserved0 [31:12] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONTROL_reserved0_MASK 0xfffff000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONTROL_reserved0_SHIFT 12
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VIRTUAL_VTT_CONTROL :: reserved_for_eco1 [11:08] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONTROL_reserved_for_eco1_MASK 0x00000f00
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONTROL_reserved_for_eco1_SHIFT 8
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONTROL_reserved_for_eco1_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VIRTUAL_VTT_CONTROL :: MAX_NOISE [07:07] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONTROL_MAX_NOISE_MASK 0x00000080
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONTROL_MAX_NOISE_SHIFT 7
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONTROL_MAX_NOISE_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VIRTUAL_VTT_CONTROL :: LOW_NOISE [06:06] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONTROL_LOW_NOISE_MASK 0x00000040
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONTROL_LOW_NOISE_SHIFT 6
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONTROL_LOW_NOISE_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VIRTUAL_VTT_CONTROL :: LOW_VTT [05:05] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONTROL_LOW_VTT_MASK 0x00000020
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONTROL_LOW_VTT_SHIFT 5
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONTROL_LOW_VTT_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VIRTUAL_VTT_CONTROL :: HIGH_VTT [04:04] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONTROL_HIGH_VTT_MASK 0x00000010
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONTROL_HIGH_VTT_SHIFT 4
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONTROL_HIGH_VTT_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VIRTUAL_VTT_CONTROL :: ERROR_RESET [03:03] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONTROL_ERROR_RESET_MASK 0x00000008
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONTROL_ERROR_RESET_SHIFT 3
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONTROL_ERROR_RESET_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VIRTUAL_VTT_CONTROL :: ENABLE_CTL_IDLE [02:02] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONTROL_ENABLE_CTL_IDLE_MASK 0x00000004
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONTROL_ENABLE_CTL_IDLE_SHIFT 2
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONTROL_ENABLE_CTL_IDLE_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VIRTUAL_VTT_CONTROL :: ENABLE_CS_IDLE [01:01] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONTROL_ENABLE_CS_IDLE_MASK 0x00000002
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONTROL_ENABLE_CS_IDLE_SHIFT 1
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONTROL_ENABLE_CS_IDLE_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VIRTUAL_VTT_CONTROL :: ENABLE_CKE_IDLE [00:00] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONTROL_ENABLE_CKE_IDLE_MASK 0x00000001
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONTROL_ENABLE_CKE_IDLE_SHIFT 0
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONTROL_ENABLE_CKE_IDLE_DEFAULT 0x00000000
-
-/***************************************************************************
- *VIRTUAL_VTT_STATUS - Virtual VTT Control and Status register
- ***************************************************************************/
-/* DDR34_PHY_CONTROL_REGS_0 :: VIRTUAL_VTT_STATUS :: reserved0 [31:19] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VIRTUAL_VTT_STATUS_reserved0_MASK 0xfff80000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VIRTUAL_VTT_STATUS_reserved0_SHIFT 19
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VIRTUAL_VTT_STATUS :: ERROR [18:03] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VIRTUAL_VTT_STATUS_ERROR_MASK 0x0007fff8
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VIRTUAL_VTT_STATUS_ERROR_SHIFT 3
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VIRTUAL_VTT_STATUS_ERROR_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VIRTUAL_VTT_STATUS :: ERROR_LOW [02:02] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VIRTUAL_VTT_STATUS_ERROR_LOW_MASK 0x00000004
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VIRTUAL_VTT_STATUS_ERROR_LOW_SHIFT 2
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VIRTUAL_VTT_STATUS_ERROR_LOW_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VIRTUAL_VTT_STATUS :: ERROR_HIGH [01:01] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VIRTUAL_VTT_STATUS_ERROR_HIGH_MASK 0x00000002
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VIRTUAL_VTT_STATUS_ERROR_HIGH_SHIFT 1
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VIRTUAL_VTT_STATUS_ERROR_HIGH_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VIRTUAL_VTT_STATUS :: READY [00:00] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VIRTUAL_VTT_STATUS_READY_MASK 0x00000001
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VIRTUAL_VTT_STATUS_READY_SHIFT 0
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VIRTUAL_VTT_STATUS_READY_DEFAULT 0x00000000
-
-/***************************************************************************
- *VIRTUAL_VTT_CONNECTIONS - Virtual VTT Connections register
- ***************************************************************************/
-/* DDR34_PHY_CONTROL_REGS_0 :: VIRTUAL_VTT_CONNECTIONS :: reserved0 [31:31] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONNECTIONS_reserved0_MASK 0x80000000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONNECTIONS_reserved0_SHIFT 31
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VIRTUAL_VTT_CONNECTIONS :: MASK [30:00] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONNECTIONS_MASK_MASK 0x7fffffff
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONNECTIONS_MASK_SHIFT 0
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONNECTIONS_MASK_DEFAULT 0x1fffffff
-
-/***************************************************************************
- *VIRTUAL_VTT_OVERRIDE - Virtual VTT Override register
- ***************************************************************************/
-/* DDR34_PHY_CONTROL_REGS_0 :: VIRTUAL_VTT_OVERRIDE :: reserved0 [31:31] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VIRTUAL_VTT_OVERRIDE_reserved0_MASK 0x80000000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VIRTUAL_VTT_OVERRIDE_reserved0_SHIFT 31
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VIRTUAL_VTT_OVERRIDE :: MASK [30:00] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VIRTUAL_VTT_OVERRIDE_MASK_MASK 0x7fffffff
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VIRTUAL_VTT_OVERRIDE_MASK_SHIFT 0
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VIRTUAL_VTT_OVERRIDE_MASK_DEFAULT 0x0000ffff
-
-/***************************************************************************
- *VREF_DAC_CONTROL - VREF DAC Control register
- ***************************************************************************/
-/* DDR34_PHY_CONTROL_REGS_0 :: VREF_DAC_CONTROL :: reserved0 [31:21] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_reserved0_MASK 0xffe00000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_reserved0_SHIFT 21
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VREF_DAC_CONTROL :: AUX_GT_INT [20:20] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_AUX_GT_INT_MASK 0x00100000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_AUX_GT_INT_SHIFT 20
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_AUX_GT_INT_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VREF_DAC_CONTROL :: TESTOUT_MUX_CTL [19:17] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_TESTOUT_MUX_CTL_MASK 0x000e0000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_TESTOUT_MUX_CTL_SHIFT 17
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_TESTOUT_MUX_CTL_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VREF_DAC_CONTROL :: TEST [16:16] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_TEST_MASK 0x00010000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_TEST_SHIFT 16
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_TEST_DEFAULT 0x00000001
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VREF_DAC_CONTROL :: PDN3 [15:15] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_PDN3_MASK 0x00008000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_PDN3_SHIFT 15
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_PDN3_DEFAULT 0x00000001
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VREF_DAC_CONTROL :: PDN2 [14:14] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_PDN2_MASK 0x00004000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_PDN2_SHIFT 14
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_PDN2_DEFAULT 0x00000001
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VREF_DAC_CONTROL :: PDN1 [13:13] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_PDN1_MASK 0x00002000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_PDN1_SHIFT 13
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_PDN1_DEFAULT 0x00000001
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VREF_DAC_CONTROL :: PDN0 [12:12] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_PDN0_MASK 0x00001000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_PDN0_SHIFT 12
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_PDN0_DEFAULT 0x00000001
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VREF_DAC_CONTROL :: DAC1 [11:06] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_DAC1_MASK 0x00000fc0
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_DAC1_SHIFT 6
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_DAC1_DEFAULT 0x00000020
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VREF_DAC_CONTROL :: DAC0 [05:00] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_DAC0_MASK 0x0000003f
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_DAC0_SHIFT 0
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_DAC0_DEFAULT 0x00000020
-
-/***************************************************************************
- *PHYBIST_CNTRL - PhyBist Control Register
- ***************************************************************************/
-/* DDR34_PHY_CONTROL_REGS_0 :: PHYBIST_CNTRL :: reserved0 [31:30] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PHYBIST_CNTRL_reserved0_MASK 0xc0000000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PHYBIST_CNTRL_reserved0_SHIFT 30
-
-/* DDR34_PHY_CONTROL_REGS_0 :: PHYBIST_CNTRL :: PATTERN_SEL [29:28] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PHYBIST_CNTRL_PATTERN_SEL_MASK 0x30000000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PHYBIST_CNTRL_PATTERN_SEL_SHIFT 28
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PHYBIST_CNTRL_PATTERN_SEL_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: PHYBIST_CNTRL :: FORCE_DQ_ERROR_SEL [27:24] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PHYBIST_CNTRL_FORCE_DQ_ERROR_SEL_MASK 0x0f000000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PHYBIST_CNTRL_FORCE_DQ_ERROR_SEL_SHIFT 24
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PHYBIST_CNTRL_FORCE_DQ_ERROR_SEL_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: PHYBIST_CNTRL :: reserved_for_eco1 [23:23] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PHYBIST_CNTRL_reserved_for_eco1_MASK 0x00800000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PHYBIST_CNTRL_reserved_for_eco1_SHIFT 23
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PHYBIST_CNTRL_reserved_for_eco1_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: PHYBIST_CNTRL :: FORCE_BL_ERROR_SEL [22:20] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PHYBIST_CNTRL_FORCE_BL_ERROR_SEL_MASK 0x00700000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PHYBIST_CNTRL_FORCE_BL_ERROR_SEL_SHIFT 20
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PHYBIST_CNTRL_FORCE_BL_ERROR_SEL_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: PHYBIST_CNTRL :: reserved_for_eco2 [19:17] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PHYBIST_CNTRL_reserved_for_eco2_MASK 0x000e0000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PHYBIST_CNTRL_reserved_for_eco2_SHIFT 17
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PHYBIST_CNTRL_reserved_for_eco2_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: PHYBIST_CNTRL :: FORCE_CTL_ERROR_SEL [16:12] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PHYBIST_CNTRL_FORCE_CTL_ERROR_SEL_MASK 0x0001f000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PHYBIST_CNTRL_FORCE_CTL_ERROR_SEL_SHIFT 12
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PHYBIST_CNTRL_FORCE_CTL_ERROR_SEL_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: PHYBIST_CNTRL :: reserved3 [11:10] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PHYBIST_CNTRL_reserved3_MASK 0x00000c00
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PHYBIST_CNTRL_reserved3_SHIFT 10
-
-/* DDR34_PHY_CONTROL_REGS_0 :: PHYBIST_CNTRL :: FORCE_DAT_ERROR [09:09] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PHYBIST_CNTRL_FORCE_DAT_ERROR_MASK 0x00000200
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PHYBIST_CNTRL_FORCE_DAT_ERROR_SHIFT 9
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PHYBIST_CNTRL_FORCE_DAT_ERROR_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: PHYBIST_CNTRL :: FORCE_CTL_ERROR [08:08] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PHYBIST_CNTRL_FORCE_CTL_ERROR_MASK 0x00000100
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PHYBIST_CNTRL_FORCE_CTL_ERROR_SHIFT 8
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PHYBIST_CNTRL_FORCE_CTL_ERROR_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: PHYBIST_CNTRL :: SSO [07:06] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PHYBIST_CNTRL_SSO_MASK 0x000000c0
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PHYBIST_CNTRL_SSO_SHIFT 6
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PHYBIST_CNTRL_SSO_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: PHYBIST_CNTRL :: LENGTH [05:04] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PHYBIST_CNTRL_LENGTH_MASK 0x00000030
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PHYBIST_CNTRL_LENGTH_SHIFT 4
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PHYBIST_CNTRL_LENGTH_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: PHYBIST_CNTRL :: MODE [03:01] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PHYBIST_CNTRL_MODE_MASK 0x0000000e
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PHYBIST_CNTRL_MODE_SHIFT 1
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PHYBIST_CNTRL_MODE_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: PHYBIST_CNTRL :: ENABLE [00:00] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PHYBIST_CNTRL_ENABLE_MASK 0x00000001
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PHYBIST_CNTRL_ENABLE_SHIFT 0
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PHYBIST_CNTRL_ENABLE_DEFAULT 0x00000000
-
-/***************************************************************************
- *PHYBIST_SEED - PhyBist Seed Register
- ***************************************************************************/
-/* DDR34_PHY_CONTROL_REGS_0 :: PHYBIST_SEED :: SEED [31:00] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PHYBIST_SEED_SEED_MASK 0xffffffff
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PHYBIST_SEED_SEED_SHIFT 0
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PHYBIST_SEED_SEED_DEFAULT 0xba5eba11
-
-/***************************************************************************
- *PHYBIST_CA_MASK - PhyBist Command/Address Bus Mask
- ***************************************************************************/
-/* DDR34_PHY_CONTROL_REGS_0 :: PHYBIST_CA_MASK :: MASK [31:00] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PHYBIST_CA_MASK_MASK_MASK 0xffffffff
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PHYBIST_CA_MASK_MASK_SHIFT 0
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PHYBIST_CA_MASK_MASK_DEFAULT 0x00000000
-
-/***************************************************************************
- *PHYBIST_DQ_MASK1 - PhyBist Data Bus Mask #1
- ***************************************************************************/
-/* DDR34_PHY_CONTROL_REGS_0 :: PHYBIST_DQ_MASK1 :: MASK [31:00] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PHYBIST_DQ_MASK1_MASK_MASK 0xffffffff
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PHYBIST_DQ_MASK1_MASK_SHIFT 0
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PHYBIST_DQ_MASK1_MASK_DEFAULT 0x00000000
-
-/***************************************************************************
- *PHYBIST_DQ_MASK2 - PhyBist Data Bus Mask #2
- ***************************************************************************/
-/* DDR34_PHY_CONTROL_REGS_0 :: PHYBIST_DQ_MASK2 :: reserved0 [31:17] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PHYBIST_DQ_MASK2_reserved0_MASK 0xfffe0000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PHYBIST_DQ_MASK2_reserved0_SHIFT 17
-
-/* DDR34_PHY_CONTROL_REGS_0 :: PHYBIST_DQ_MASK2 :: EDC_MASK [16:12] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PHYBIST_DQ_MASK2_EDC_MASK_MASK 0x0001f000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PHYBIST_DQ_MASK2_EDC_MASK_SHIFT 12
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PHYBIST_DQ_MASK2_EDC_MASK_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: PHYBIST_DQ_MASK2 :: reserved1 [11:09] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PHYBIST_DQ_MASK2_reserved1_MASK 0x00000e00
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PHYBIST_DQ_MASK2_reserved1_SHIFT 9
-
-/* DDR34_PHY_CONTROL_REGS_0 :: PHYBIST_DQ_MASK2 :: DM_MASK [08:04] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PHYBIST_DQ_MASK2_DM_MASK_MASK 0x000001f0
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PHYBIST_DQ_MASK2_DM_MASK_SHIFT 4
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PHYBIST_DQ_MASK2_DM_MASK_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: PHYBIST_DQ_MASK2 :: DQ_MASK [03:00] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PHYBIST_DQ_MASK2_DQ_MASK_MASK 0x0000000f
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PHYBIST_DQ_MASK2_DQ_MASK_SHIFT 0
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PHYBIST_DQ_MASK2_DQ_MASK_DEFAULT 0x00000000
-
-/***************************************************************************
- *PHYBIST_STATUS - PhyBist General Status Register
- ***************************************************************************/
-/* DDR34_PHY_CONTROL_REGS_0 :: PHYBIST_STATUS :: reserved0 [31:04] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PHYBIST_STATUS_reserved0_MASK 0xfffffff0
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PHYBIST_STATUS_reserved0_SHIFT 4
-
-/* DDR34_PHY_CONTROL_REGS_0 :: PHYBIST_STATUS :: DAT_PASS [03:03] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PHYBIST_STATUS_DAT_PASS_MASK 0x00000008
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PHYBIST_STATUS_DAT_PASS_SHIFT 3
-
-/* DDR34_PHY_CONTROL_REGS_0 :: PHYBIST_STATUS :: CTL_PASS [02:02] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PHYBIST_STATUS_CTL_PASS_MASK 0x00000004
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PHYBIST_STATUS_CTL_PASS_SHIFT 2
-
-/* DDR34_PHY_CONTROL_REGS_0 :: PHYBIST_STATUS :: DAT_DONE [01:01] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PHYBIST_STATUS_DAT_DONE_MASK 0x00000002
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PHYBIST_STATUS_DAT_DONE_SHIFT 1
-
-/* DDR34_PHY_CONTROL_REGS_0 :: PHYBIST_STATUS :: CTL_DONE [00:00] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PHYBIST_STATUS_CTL_DONE_MASK 0x00000001
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PHYBIST_STATUS_CTL_DONE_SHIFT 0
-
-/***************************************************************************
- *PHYBIST_CTL_STATUS - PhyBist Per-Bit Control Pad Status Register
- ***************************************************************************/
-/* DDR34_PHY_CONTROL_REGS_0 :: PHYBIST_CTL_STATUS :: reserved0 [31:31] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PHYBIST_CTL_STATUS_reserved0_MASK 0x80000000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PHYBIST_CTL_STATUS_reserved0_SHIFT 31
-
-/* DDR34_PHY_CONTROL_REGS_0 :: PHYBIST_CTL_STATUS :: CTL_ERRORS [30:00] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PHYBIST_CTL_STATUS_CTL_ERRORS_MASK 0x7fffffff
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PHYBIST_CTL_STATUS_CTL_ERRORS_SHIFT 0
-
-/***************************************************************************
- *PHYBIST_BL0_STATUS - PhyBist Byte Lane #0 Status Register
- ***************************************************************************/
-/* DDR34_PHY_CONTROL_REGS_0 :: PHYBIST_BL0_STATUS :: reserved0 [31:10] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PHYBIST_BL0_STATUS_reserved0_MASK 0xfffffc00
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PHYBIST_BL0_STATUS_reserved0_SHIFT 10
-
-/* DDR34_PHY_CONTROL_REGS_0 :: PHYBIST_BL0_STATUS :: EDC [09:09] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PHYBIST_BL0_STATUS_EDC_MASK 0x00000200
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PHYBIST_BL0_STATUS_EDC_SHIFT 9
-
-/* DDR34_PHY_CONTROL_REGS_0 :: PHYBIST_BL0_STATUS :: DM [08:08] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PHYBIST_BL0_STATUS_DM_MASK 0x00000100
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PHYBIST_BL0_STATUS_DM_SHIFT 8
-
-/* DDR34_PHY_CONTROL_REGS_0 :: PHYBIST_BL0_STATUS :: DQ [07:00] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PHYBIST_BL0_STATUS_DQ_MASK 0x000000ff
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PHYBIST_BL0_STATUS_DQ_SHIFT 0
-
-/***************************************************************************
- *PHYBIST_BL1_STATUS - PhyBist Byte Lane #1 Status Register
- ***************************************************************************/
-/* DDR34_PHY_CONTROL_REGS_0 :: PHYBIST_BL1_STATUS :: reserved0 [31:10] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PHYBIST_BL1_STATUS_reserved0_MASK 0xfffffc00
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PHYBIST_BL1_STATUS_reserved0_SHIFT 10
-
-/* DDR34_PHY_CONTROL_REGS_0 :: PHYBIST_BL1_STATUS :: EDC [09:09] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PHYBIST_BL1_STATUS_EDC_MASK 0x00000200
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PHYBIST_BL1_STATUS_EDC_SHIFT 9
-
-/* DDR34_PHY_CONTROL_REGS_0 :: PHYBIST_BL1_STATUS :: DM [08:08] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PHYBIST_BL1_STATUS_DM_MASK 0x00000100
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PHYBIST_BL1_STATUS_DM_SHIFT 8
-
-/* DDR34_PHY_CONTROL_REGS_0 :: PHYBIST_BL1_STATUS :: DQ [07:00] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PHYBIST_BL1_STATUS_DQ_MASK 0x000000ff
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PHYBIST_BL1_STATUS_DQ_SHIFT 0
-
-/***************************************************************************
- *PHYBIST_BL2_STATUS - PhyBist Byte Lane #2 Status Register
- ***************************************************************************/
-/* DDR34_PHY_CONTROL_REGS_0 :: PHYBIST_BL2_STATUS :: reserved0 [31:10] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PHYBIST_BL2_STATUS_reserved0_MASK 0xfffffc00
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PHYBIST_BL2_STATUS_reserved0_SHIFT 10
-
-/* DDR34_PHY_CONTROL_REGS_0 :: PHYBIST_BL2_STATUS :: EDC [09:09] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PHYBIST_BL2_STATUS_EDC_MASK 0x00000200
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PHYBIST_BL2_STATUS_EDC_SHIFT 9
-
-/* DDR34_PHY_CONTROL_REGS_0 :: PHYBIST_BL2_STATUS :: DM [08:08] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PHYBIST_BL2_STATUS_DM_MASK 0x00000100
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PHYBIST_BL2_STATUS_DM_SHIFT 8
-
-/* DDR34_PHY_CONTROL_REGS_0 :: PHYBIST_BL2_STATUS :: DQ [07:00] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PHYBIST_BL2_STATUS_DQ_MASK 0x000000ff
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PHYBIST_BL2_STATUS_DQ_SHIFT 0
-
-/***************************************************************************
- *PHYBIST_BL3_STATUS - PhyBist Byte Lane #3 Status Register
- ***************************************************************************/
-/* DDR34_PHY_CONTROL_REGS_0 :: PHYBIST_BL3_STATUS :: reserved0 [31:10] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PHYBIST_BL3_STATUS_reserved0_MASK 0xfffffc00
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PHYBIST_BL3_STATUS_reserved0_SHIFT 10
-
-/* DDR34_PHY_CONTROL_REGS_0 :: PHYBIST_BL3_STATUS :: EDC [09:09] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PHYBIST_BL3_STATUS_EDC_MASK 0x00000200
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PHYBIST_BL3_STATUS_EDC_SHIFT 9
-
-/* DDR34_PHY_CONTROL_REGS_0 :: PHYBIST_BL3_STATUS :: DM [08:08] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PHYBIST_BL3_STATUS_DM_MASK 0x00000100
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PHYBIST_BL3_STATUS_DM_SHIFT 8
-
-/* DDR34_PHY_CONTROL_REGS_0 :: PHYBIST_BL3_STATUS :: DQ [07:00] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PHYBIST_BL3_STATUS_DQ_MASK 0x000000ff
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PHYBIST_BL3_STATUS_DQ_SHIFT 0
-
-/***************************************************************************
- *PHYBIST_BL4_STATUS - PhyBist Byte Lane #4 (ECC) Status Register
- ***************************************************************************/
-/* DDR34_PHY_CONTROL_REGS_0 :: PHYBIST_BL4_STATUS :: reserved0 [31:10] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PHYBIST_BL4_STATUS_reserved0_MASK 0xfffffc00
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PHYBIST_BL4_STATUS_reserved0_SHIFT 10
-
-/* DDR34_PHY_CONTROL_REGS_0 :: PHYBIST_BL4_STATUS :: EDC [09:09] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PHYBIST_BL4_STATUS_EDC_MASK 0x00000200
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PHYBIST_BL4_STATUS_EDC_SHIFT 9
-
-/* DDR34_PHY_CONTROL_REGS_0 :: PHYBIST_BL4_STATUS :: DM [08:08] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PHYBIST_BL4_STATUS_DM_MASK 0x00000100
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PHYBIST_BL4_STATUS_DM_SHIFT 8
-
-/* DDR34_PHY_CONTROL_REGS_0 :: PHYBIST_BL4_STATUS :: DQ [07:00] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PHYBIST_BL4_STATUS_DQ_MASK 0x000000ff
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PHYBIST_BL4_STATUS_DQ_SHIFT 0
-
-/***************************************************************************
- *STANDBY_CONTROL - Standby Control register
- ***************************************************************************/
-/* DDR34_PHY_CONTROL_REGS_0 :: STANDBY_CONTROL :: reserved0 [31:05] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_STANDBY_CONTROL_reserved0_MASK 0xffffffe0
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_STANDBY_CONTROL_reserved0_SHIFT 5
-
-/* DDR34_PHY_CONTROL_REGS_0 :: STANDBY_CONTROL :: PHY_STANDBY [04:04] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_STANDBY_CONTROL_PHY_STANDBY_MASK 0x00000010
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_STANDBY_CONTROL_PHY_STANDBY_SHIFT 4
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_STANDBY_CONTROL_PHY_STANDBY_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: STANDBY_CONTROL :: FORCE_CKE_RST_N [03:03] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_STANDBY_CONTROL_FORCE_CKE_RST_N_MASK 0x00000008
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_STANDBY_CONTROL_FORCE_CKE_RST_N_SHIFT 3
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_STANDBY_CONTROL_FORCE_CKE_RST_N_DEFAULT 0x00000001
-
-/* DDR34_PHY_CONTROL_REGS_0 :: STANDBY_CONTROL :: RST_N [02:02] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_STANDBY_CONTROL_RST_N_MASK 0x00000004
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_STANDBY_CONTROL_RST_N_SHIFT 2
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_STANDBY_CONTROL_RST_N_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: STANDBY_CONTROL :: CKE [01:01] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_STANDBY_CONTROL_CKE_MASK 0x00000002
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_STANDBY_CONTROL_CKE_SHIFT 1
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_STANDBY_CONTROL_CKE_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: STANDBY_CONTROL :: BIT_PIPE_RESET [00:00] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_STANDBY_CONTROL_BIT_PIPE_RESET_MASK 0x00000001
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_STANDBY_CONTROL_BIT_PIPE_RESET_SHIFT 0
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_STANDBY_CONTROL_BIT_PIPE_RESET_DEFAULT 0x00000001
-
-/***************************************************************************
- *DEBUG_FREEZE_ENABLE - Freeze-on-error enable register
- ***************************************************************************/
-/* DDR34_PHY_CONTROL_REGS_0 :: DEBUG_FREEZE_ENABLE :: reserved0 [31:05] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_DEBUG_FREEZE_ENABLE_reserved0_MASK 0xffffffe0
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_DEBUG_FREEZE_ENABLE_reserved0_SHIFT 5
-
-/* DDR34_PHY_CONTROL_REGS_0 :: DEBUG_FREEZE_ENABLE :: WLECC [04:04] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_DEBUG_FREEZE_ENABLE_WLECC_MASK 0x00000010
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_DEBUG_FREEZE_ENABLE_WLECC_SHIFT 4
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_DEBUG_FREEZE_ENABLE_WLECC_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: DEBUG_FREEZE_ENABLE :: WL1_BL1 [03:03] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_DEBUG_FREEZE_ENABLE_WL1_BL1_MASK 0x00000008
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_DEBUG_FREEZE_ENABLE_WL1_BL1_SHIFT 3
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_DEBUG_FREEZE_ENABLE_WL1_BL1_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: DEBUG_FREEZE_ENABLE :: WL1_BL0 [02:02] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_DEBUG_FREEZE_ENABLE_WL1_BL0_MASK 0x00000004
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_DEBUG_FREEZE_ENABLE_WL1_BL0_SHIFT 2
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_DEBUG_FREEZE_ENABLE_WL1_BL0_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: DEBUG_FREEZE_ENABLE :: WL0_BL1 [01:01] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_DEBUG_FREEZE_ENABLE_WL0_BL1_MASK 0x00000002
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_DEBUG_FREEZE_ENABLE_WL0_BL1_SHIFT 1
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_DEBUG_FREEZE_ENABLE_WL0_BL1_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: DEBUG_FREEZE_ENABLE :: WL0_BL0 [00:00] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_DEBUG_FREEZE_ENABLE_WL0_BL0_MASK 0x00000001
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_DEBUG_FREEZE_ENABLE_WL0_BL0_SHIFT 0
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_DEBUG_FREEZE_ENABLE_WL0_BL0_DEFAULT 0x00000000
-
-/***************************************************************************
- *DEBUG_MUX_CONTROL - Debug Mux Control register
- ***************************************************************************/
-/* DDR34_PHY_CONTROL_REGS_0 :: DEBUG_MUX_CONTROL :: reserved0 [31:11] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_DEBUG_MUX_CONTROL_reserved0_MASK 0xfffff800
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_DEBUG_MUX_CONTROL_reserved0_SHIFT 11
-
-/* DDR34_PHY_CONTROL_REGS_0 :: DEBUG_MUX_CONTROL :: BYTE_SEL [10:08] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_DEBUG_MUX_CONTROL_BYTE_SEL_MASK 0x00000700
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_DEBUG_MUX_CONTROL_BYTE_SEL_SHIFT 8
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_DEBUG_MUX_CONTROL_BYTE_SEL_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: DEBUG_MUX_CONTROL :: reserved1 [07:06] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_DEBUG_MUX_CONTROL_reserved1_MASK 0x000000c0
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_DEBUG_MUX_CONTROL_reserved1_SHIFT 6
-
-/* DDR34_PHY_CONTROL_REGS_0 :: DEBUG_MUX_CONTROL :: PHASE_SEL [05:04] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_DEBUG_MUX_CONTROL_PHASE_SEL_MASK 0x00000030
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_DEBUG_MUX_CONTROL_PHASE_SEL_SHIFT 4
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_DEBUG_MUX_CONTROL_PHASE_SEL_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: DEBUG_MUX_CONTROL :: SOURCE_SEL [03:00] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_DEBUG_MUX_CONTROL_SOURCE_SEL_MASK 0x0000000f
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_DEBUG_MUX_CONTROL_SOURCE_SEL_SHIFT 0
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_DEBUG_MUX_CONTROL_SOURCE_SEL_DEFAULT 0x00000000
-
-/***************************************************************************
- *DFI_CNTRL - DFI Interface Ownership Control register
- ***************************************************************************/
-/* DDR34_PHY_CONTROL_REGS_0 :: DFI_CNTRL :: reserved0 [31:10] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_DFI_CNTRL_reserved0_MASK 0xfffffc00
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_DFI_CNTRL_reserved0_SHIFT 10
-
-/* DDR34_PHY_CONTROL_REGS_0 :: DFI_CNTRL :: SELF_REFRESH_CS1 [09:09] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_DFI_CNTRL_SELF_REFRESH_CS1_MASK 0x00000200
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_DFI_CNTRL_SELF_REFRESH_CS1_SHIFT 9
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_DFI_CNTRL_SELF_REFRESH_CS1_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: DFI_CNTRL :: SELF_REFRESH_CS0 [08:08] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_DFI_CNTRL_SELF_REFRESH_CS0_MASK 0x00000100
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_DFI_CNTRL_SELF_REFRESH_CS0_SHIFT 8
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_DFI_CNTRL_SELF_REFRESH_CS0_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: DFI_CNTRL :: DFI_CS1 [07:07] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_DFI_CNTRL_DFI_CS1_MASK 0x00000080
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_DFI_CNTRL_DFI_CS1_SHIFT 7
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_DFI_CNTRL_DFI_CS1_DEFAULT 0x00000001
-
-/* DDR34_PHY_CONTROL_REGS_0 :: DFI_CNTRL :: DFI_CS0 [06:06] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_DFI_CNTRL_DFI_CS0_MASK 0x00000040
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_DFI_CNTRL_DFI_CS0_SHIFT 6
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_DFI_CNTRL_DFI_CS0_DEFAULT 0x00000001
-
-/* DDR34_PHY_CONTROL_REGS_0 :: DFI_CNTRL :: DFI_RST_N [05:05] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_DFI_CNTRL_DFI_RST_N_MASK 0x00000020
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_DFI_CNTRL_DFI_RST_N_SHIFT 5
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_DFI_CNTRL_DFI_RST_N_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: DFI_CNTRL :: DFI_CKE1 [04:04] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_DFI_CNTRL_DFI_CKE1_MASK 0x00000010
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_DFI_CNTRL_DFI_CKE1_SHIFT 4
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_DFI_CNTRL_DFI_CKE1_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: DFI_CNTRL :: DFI_CKE0 [03:03] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_DFI_CNTRL_DFI_CKE0_MASK 0x00000008
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_DFI_CNTRL_DFI_CKE0_SHIFT 3
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_DFI_CNTRL_DFI_CKE0_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: DFI_CNTRL :: ACK_ENABLE [02:02] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_DFI_CNTRL_ACK_ENABLE_MASK 0x00000004
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_DFI_CNTRL_ACK_ENABLE_SHIFT 2
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_DFI_CNTRL_ACK_ENABLE_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: DFI_CNTRL :: ACK_STATUS [01:01] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_DFI_CNTRL_ACK_STATUS_MASK 0x00000002
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_DFI_CNTRL_ACK_STATUS_SHIFT 1
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_DFI_CNTRL_ACK_STATUS_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: DFI_CNTRL :: ASSERT_REQ [00:00] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_DFI_CNTRL_ASSERT_REQ_MASK 0x00000001
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_DFI_CNTRL_ASSERT_REQ_SHIFT 0
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_DFI_CNTRL_ASSERT_REQ_DEFAULT 0x00000001
-
-/***************************************************************************
- *WRITE_ODT_CNTRL - Write ODT Control register
- ***************************************************************************/
-/* DDR34_PHY_CONTROL_REGS_0 :: WRITE_ODT_CNTRL :: reserved0 [31:29] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_WRITE_ODT_CNTRL_reserved0_MASK 0xe0000000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_WRITE_ODT_CNTRL_reserved0_SHIFT 29
-
-/* DDR34_PHY_CONTROL_REGS_0 :: WRITE_ODT_CNTRL :: ODT1_FORCE_VALUE [28:28] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_WRITE_ODT_CNTRL_ODT1_FORCE_VALUE_MASK 0x10000000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_WRITE_ODT_CNTRL_ODT1_FORCE_VALUE_SHIFT 28
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_WRITE_ODT_CNTRL_ODT1_FORCE_VALUE_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: WRITE_ODT_CNTRL :: ODT1_FORCE [27:27] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_WRITE_ODT_CNTRL_ODT1_FORCE_MASK 0x08000000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_WRITE_ODT_CNTRL_ODT1_FORCE_SHIFT 27
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_WRITE_ODT_CNTRL_ODT1_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: WRITE_ODT_CNTRL :: ODT1_ENABLE [26:26] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_WRITE_ODT_CNTRL_ODT1_ENABLE_MASK 0x04000000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_WRITE_ODT_CNTRL_ODT1_ENABLE_SHIFT 26
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_WRITE_ODT_CNTRL_ODT1_ENABLE_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: WRITE_ODT_CNTRL :: ODT1_LENGTH [25:22] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_WRITE_ODT_CNTRL_ODT1_LENGTH_MASK 0x03c00000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_WRITE_ODT_CNTRL_ODT1_LENGTH_SHIFT 22
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_WRITE_ODT_CNTRL_ODT1_LENGTH_DEFAULT 0x0000000c
-
-/* DDR34_PHY_CONTROL_REGS_0 :: WRITE_ODT_CNTRL :: ODT1_DELAY [21:16] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_WRITE_ODT_CNTRL_ODT1_DELAY_MASK 0x003f0000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_WRITE_ODT_CNTRL_ODT1_DELAY_SHIFT 16
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_WRITE_ODT_CNTRL_ODT1_DELAY_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: WRITE_ODT_CNTRL :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_WRITE_ODT_CNTRL_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_WRITE_ODT_CNTRL_reserved1_SHIFT 13
-
-/* DDR34_PHY_CONTROL_REGS_0 :: WRITE_ODT_CNTRL :: ODT0_FORCE_VALUE [12:12] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_WRITE_ODT_CNTRL_ODT0_FORCE_VALUE_MASK 0x00001000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_WRITE_ODT_CNTRL_ODT0_FORCE_VALUE_SHIFT 12
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_WRITE_ODT_CNTRL_ODT0_FORCE_VALUE_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: WRITE_ODT_CNTRL :: ODT0_FORCE [11:11] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_WRITE_ODT_CNTRL_ODT0_FORCE_MASK 0x00000800
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_WRITE_ODT_CNTRL_ODT0_FORCE_SHIFT 11
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_WRITE_ODT_CNTRL_ODT0_FORCE_DEFAULT 0x00000001
-
-/* DDR34_PHY_CONTROL_REGS_0 :: WRITE_ODT_CNTRL :: ODT0_ENABLE [10:10] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_WRITE_ODT_CNTRL_ODT0_ENABLE_MASK 0x00000400
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_WRITE_ODT_CNTRL_ODT0_ENABLE_SHIFT 10
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_WRITE_ODT_CNTRL_ODT0_ENABLE_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: WRITE_ODT_CNTRL :: ODT0_LENGTH [09:06] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_WRITE_ODT_CNTRL_ODT0_LENGTH_MASK 0x000003c0
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_WRITE_ODT_CNTRL_ODT0_LENGTH_SHIFT 6
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_WRITE_ODT_CNTRL_ODT0_LENGTH_DEFAULT 0x0000000c
-
-/* DDR34_PHY_CONTROL_REGS_0 :: WRITE_ODT_CNTRL :: ODT0_DELAY [05:00] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_WRITE_ODT_CNTRL_ODT0_DELAY_MASK 0x0000003f
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_WRITE_ODT_CNTRL_ODT0_DELAY_SHIFT 0
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_WRITE_ODT_CNTRL_ODT0_DELAY_DEFAULT 0x00000000
-
-/***************************************************************************
- *ABI_PAR_CNTRL - ABI and PAR Control register
- ***************************************************************************/
-/* DDR34_PHY_CONTROL_REGS_0 :: ABI_PAR_CNTRL :: reserved0 [31:08] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_ABI_PAR_CNTRL_reserved0_MASK 0xffffff00
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_ABI_PAR_CNTRL_reserved0_SHIFT 8
-
-/* DDR34_PHY_CONTROL_REGS_0 :: ABI_PAR_CNTRL :: PAR_ERROR [07:04] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_ABI_PAR_CNTRL_PAR_ERROR_MASK 0x000000f0
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_ABI_PAR_CNTRL_PAR_ERROR_SHIFT 4
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_ABI_PAR_CNTRL_PAR_ERROR_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: ABI_PAR_CNTRL :: PAR_INCLUDE_AUX [03:03] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_ABI_PAR_CNTRL_PAR_INCLUDE_AUX_MASK 0x00000008
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_ABI_PAR_CNTRL_PAR_INCLUDE_AUX_SHIFT 3
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_ABI_PAR_CNTRL_PAR_INCLUDE_AUX_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: ABI_PAR_CNTRL :: PAR_ENABLE [02:02] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_ABI_PAR_CNTRL_PAR_ENABLE_MASK 0x00000004
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_ABI_PAR_CNTRL_PAR_ENABLE_SHIFT 2
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_ABI_PAR_CNTRL_PAR_ENABLE_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: ABI_PAR_CNTRL :: ABI_INCLUDE_AUX [01:01] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_ABI_PAR_CNTRL_ABI_INCLUDE_AUX_MASK 0x00000002
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_ABI_PAR_CNTRL_ABI_INCLUDE_AUX_SHIFT 1
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_ABI_PAR_CNTRL_ABI_INCLUDE_AUX_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: ABI_PAR_CNTRL :: ABI_ENABLE [00:00] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_ABI_PAR_CNTRL_ABI_ENABLE_MASK 0x00000001
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_ABI_PAR_CNTRL_ABI_ENABLE_SHIFT 0
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_ABI_PAR_CNTRL_ABI_ENABLE_DEFAULT 0x00000000
-
-/***************************************************************************
- *ZQ_CAL - ZQ Calibration Control register
- ***************************************************************************/
-/* DDR34_PHY_CONTROL_REGS_0 :: ZQ_CAL :: reserved0 [31:31] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_ZQ_CAL_reserved0_MASK 0x80000000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_ZQ_CAL_reserved0_SHIFT 31
-
-/* DDR34_PHY_CONTROL_REGS_0 :: ZQ_CAL :: ZQ_RX_LSTRIM [30:27] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_ZQ_CAL_ZQ_RX_LSTRIM_MASK 0x78000000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_ZQ_CAL_ZQ_RX_LSTRIM_SHIFT 27
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_ZQ_CAL_ZQ_RX_LSTRIM_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: ZQ_CAL :: ZQ_RX_ITRIM [26:24] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_ZQ_CAL_ZQ_RX_ITRIM_MASK 0x07000000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_ZQ_CAL_ZQ_RX_ITRIM_SHIFT 24
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_ZQ_CAL_ZQ_RX_ITRIM_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: ZQ_CAL :: ZQ_TX_SLEW [23:22] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_ZQ_CAL_ZQ_TX_SLEW_MASK 0x00c00000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_ZQ_CAL_ZQ_TX_SLEW_SHIFT 22
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_ZQ_CAL_ZQ_TX_SLEW_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: ZQ_CAL :: ZQ_STATUS [21:21] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_ZQ_CAL_ZQ_STATUS_MASK 0x00200000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_ZQ_CAL_ZQ_STATUS_SHIFT 21
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_ZQ_CAL_ZQ_STATUS_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: ZQ_CAL :: ZQ_RXENB [20:20] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_ZQ_CAL_ZQ_RXENB_MASK 0x00100000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_ZQ_CAL_ZQ_RXENB_SHIFT 20
-
-/* DDR34_PHY_CONTROL_REGS_0 :: ZQ_CAL :: ZQ_IDDQ [19:19] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_ZQ_CAL_ZQ_IDDQ_MASK 0x00080000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_ZQ_CAL_ZQ_IDDQ_SHIFT 19
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_ZQ_CAL_ZQ_IDDQ_DEFAULT 0x00000001
-
-/* DDR34_PHY_CONTROL_REGS_0 :: ZQ_CAL :: ZQ_DRIVE_N [18:14] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_ZQ_CAL_ZQ_DRIVE_N_MASK 0x0007c000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_ZQ_CAL_ZQ_DRIVE_N_SHIFT 14
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_ZQ_CAL_ZQ_DRIVE_N_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: ZQ_CAL :: ZQ_DRIVE_P [13:09] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_ZQ_CAL_ZQ_DRIVE_P_MASK 0x00003e00
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_ZQ_CAL_ZQ_DRIVE_P_SHIFT 9
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_ZQ_CAL_ZQ_DRIVE_P_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: ZQ_CAL :: ZQ_TX_MODE [08:03] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_ZQ_CAL_ZQ_TX_MODE_MASK 0x000001f8
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_ZQ_CAL_ZQ_TX_MODE_SHIFT 3
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_ZQ_CAL_ZQ_TX_MODE_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: ZQ_CAL :: ZQ_RX_MODE [02:00] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_ZQ_CAL_ZQ_RX_MODE_MASK 0x00000007
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_ZQ_CAL_ZQ_RX_MODE_SHIFT 0
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_ZQ_CAL_ZQ_RX_MODE_DEFAULT 0x00000000
-
-/***************************************************************************
- *ZQ_CAL2 - ZQ Calibration Control register
- ***************************************************************************/
-/* DDR34_PHY_CONTROL_REGS_0 :: ZQ_CAL2 :: reserved0 [31:14] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_ZQ_CAL2_reserved0_MASK 0xffffc000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_ZQ_CAL2_reserved0_SHIFT 14
-
-/* DDR34_PHY_CONTROL_REGS_0 :: ZQ_CAL2 :: ZQ_NSETTING [13:09] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_ZQ_CAL2_ZQ_NSETTING_MASK 0x00003e00
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_ZQ_CAL2_ZQ_NSETTING_SHIFT 9
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_ZQ_CAL2_ZQ_NSETTING_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: ZQ_CAL2 :: ZQ_PSETTING [08:04] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_ZQ_CAL2_ZQ_PSETTING_MASK 0x000001f0
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_ZQ_CAL2_ZQ_PSETTING_SHIFT 4
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_ZQ_CAL2_ZQ_PSETTING_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: ZQ_CAL2 :: ZQ_CAL_OP_COMPLETE_N [03:03] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_ZQ_CAL2_ZQ_CAL_OP_COMPLETE_N_MASK 0x00000008
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_ZQ_CAL2_ZQ_CAL_OP_COMPLETE_N_SHIFT 3
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_ZQ_CAL2_ZQ_CAL_OP_COMPLETE_N_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: ZQ_CAL2 :: ZQ_CAL_OP_COMPLETE_P [02:02] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_ZQ_CAL2_ZQ_CAL_OP_COMPLETE_P_MASK 0x00000004
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_ZQ_CAL2_ZQ_CAL_OP_COMPLETE_P_SHIFT 2
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_ZQ_CAL2_ZQ_CAL_OP_COMPLETE_P_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: ZQ_CAL2 :: ZQ_CAL_START_N [01:01] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_ZQ_CAL2_ZQ_CAL_START_N_MASK 0x00000002
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_ZQ_CAL2_ZQ_CAL_START_N_SHIFT 1
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_ZQ_CAL2_ZQ_CAL_START_N_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: ZQ_CAL2 :: ZQ_CAL_START_P [00:00] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_ZQ_CAL2_ZQ_CAL_START_P_MASK 0x00000001
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_ZQ_CAL2_ZQ_CAL_START_P_SHIFT 0
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_ZQ_CAL2_ZQ_CAL_START_P_DEFAULT 0x00000000
-
-/***************************************************************************
- *COMR_CAL - COMR Calibration Control register
- ***************************************************************************/
-/* DDR34_PHY_CONTROL_REGS_0 :: COMR_CAL :: reserved0 [31:14] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMR_CAL_reserved0_MASK 0xffffc000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMR_CAL_reserved0_SHIFT 14
-
-/* DDR34_PHY_CONTROL_REGS_0 :: COMR_CAL :: COMR_RX_DIN [13:13] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMR_CAL_COMR_RX_DIN_MASK 0x00002000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMR_CAL_COMR_RX_DIN_SHIFT 13
-
-/* DDR34_PHY_CONTROL_REGS_0 :: COMR_CAL :: COMR_RX_READY [12:12] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMR_CAL_COMR_RX_READY_MASK 0x00001000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMR_CAL_COMR_RX_READY_SHIFT 12
-
-/* DDR34_PHY_CONTROL_REGS_0 :: COMR_CAL :: COMR_RXENB [11:11] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMR_CAL_COMR_RXENB_MASK 0x00000800
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMR_CAL_COMR_RXENB_SHIFT 11
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMR_CAL_COMR_RXENB_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: COMR_CAL :: reserved1 [10:09] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMR_CAL_reserved1_MASK 0x00000600
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMR_CAL_reserved1_SHIFT 9
-
-/* DDR34_PHY_CONTROL_REGS_0 :: COMR_CAL :: COMR_RX_MODE [08:08] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMR_CAL_COMR_RX_MODE_MASK 0x00000100
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMR_CAL_COMR_RX_MODE_SHIFT 8
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMR_CAL_COMR_RX_MODE_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: COMR_CAL :: COMR_RX_LSTRIM [07:04] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMR_CAL_COMR_RX_LSTRIM_MASK 0x000000f0
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMR_CAL_COMR_RX_LSTRIM_SHIFT 4
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMR_CAL_COMR_RX_LSTRIM_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: COMR_CAL :: COMR_RX_ITRIM [03:01] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMR_CAL_COMR_RX_ITRIM_MASK 0x0000000e
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMR_CAL_COMR_RX_ITRIM_SHIFT 1
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMR_CAL_COMR_RX_ITRIM_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: COMR_CAL :: COMR_IDDQ [00:00] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMR_CAL_COMR_IDDQ_MASK 0x00000001
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMR_CAL_COMR_IDDQ_SHIFT 0
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMR_CAL_COMR_IDDQ_DEFAULT 0x00000000
-
-/***************************************************************************
- *RO_PROC_MON_CTL - Ring-Osc control register
- ***************************************************************************/
-/* DDR34_PHY_CONTROL_REGS_0 :: RO_PROC_MON_CTL :: reserved0 [31:27] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_RO_PROC_MON_CTL_reserved0_MASK 0xf8000000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_RO_PROC_MON_CTL_reserved0_SHIFT 27
-
-/* DDR34_PHY_CONTROL_REGS_0 :: RO_PROC_MON_CTL :: BUSY [26:26] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_RO_PROC_MON_CTL_BUSY_MASK 0x04000000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_RO_PROC_MON_CTL_BUSY_SHIFT 26
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_RO_PROC_MON_CTL_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: RO_PROC_MON_CTL :: TRIGGER [25:25] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_RO_PROC_MON_CTL_TRIGGER_MASK 0x02000000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_RO_PROC_MON_CTL_TRIGGER_SHIFT 25
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_RO_PROC_MON_CTL_TRIGGER_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: RO_PROC_MON_CTL :: RESET [24:24] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_RO_PROC_MON_CTL_RESET_MASK 0x01000000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_RO_PROC_MON_CTL_RESET_SHIFT 24
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_RO_PROC_MON_CTL_RESET_DEFAULT 0x00000001
-
-/* DDR34_PHY_CONTROL_REGS_0 :: RO_PROC_MON_CTL :: SEL [23:12] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_RO_PROC_MON_CTL_SEL_MASK 0x00fff000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_RO_PROC_MON_CTL_SEL_SHIFT 12
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_RO_PROC_MON_CTL_SEL_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: RO_PROC_MON_CTL :: EN [11:00] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_RO_PROC_MON_CTL_EN_MASK 0x00000fff
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_RO_PROC_MON_CTL_EN_SHIFT 0
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_RO_PROC_MON_CTL_EN_DEFAULT 0x00000000
-
-/***************************************************************************
- *RO_PROC_MON_STATUS - Ring-Osc count register
- ***************************************************************************/
-/* DDR34_PHY_CONTROL_REGS_0 :: RO_PROC_MON_STATUS :: CLK_COUNT [31:08] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_RO_PROC_MON_STATUS_CLK_COUNT_MASK 0xffffff00
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_RO_PROC_MON_STATUS_CLK_COUNT_SHIFT 8
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_RO_PROC_MON_STATUS_CLK_COUNT_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: RO_PROC_MON_STATUS :: RO_COUNT [07:00] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_RO_PROC_MON_STATUS_RO_COUNT_MASK 0x000000ff
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_RO_PROC_MON_STATUS_RO_COUNT_SHIFT 0
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_RO_PROC_MON_STATUS_RO_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *CK_DRIVE_PAD_CTL - Drive strength control register for CK_P and CK_N
- ***************************************************************************/
-/* DDR34_PHY_CONTROL_REGS_0 :: CK_DRIVE_PAD_CTL :: reserved0 [31:30] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_CK_DRIVE_PAD_CTL_reserved0_MASK 0xc0000000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_CK_DRIVE_PAD_CTL_reserved0_SHIFT 30
-
-/* DDR34_PHY_CONTROL_REGS_0 :: CK_DRIVE_PAD_CTL :: ADDR_CTL_PD_IDLE_STRENGTH [29:25] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_CK_DRIVE_PAD_CTL_ADDR_CTL_PD_IDLE_STRENGTH_MASK 0x3e000000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_CK_DRIVE_PAD_CTL_ADDR_CTL_PD_IDLE_STRENGTH_SHIFT 25
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_CK_DRIVE_PAD_CTL_ADDR_CTL_PD_IDLE_STRENGTH_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: CK_DRIVE_PAD_CTL :: ADDR_CTL_ND_IDLE_STRENGTH [24:20] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_CK_DRIVE_PAD_CTL_ADDR_CTL_ND_IDLE_STRENGTH_MASK 0x01f00000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_CK_DRIVE_PAD_CTL_ADDR_CTL_ND_IDLE_STRENGTH_SHIFT 20
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_CK_DRIVE_PAD_CTL_ADDR_CTL_ND_IDLE_STRENGTH_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: CK_DRIVE_PAD_CTL :: ADDR_CTL_PD_TERM_STRENGTH [19:15] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_CK_DRIVE_PAD_CTL_ADDR_CTL_PD_TERM_STRENGTH_MASK 0x000f8000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_CK_DRIVE_PAD_CTL_ADDR_CTL_PD_TERM_STRENGTH_SHIFT 15
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_CK_DRIVE_PAD_CTL_ADDR_CTL_PD_TERM_STRENGTH_DEFAULT 0x00000008
-
-/* DDR34_PHY_CONTROL_REGS_0 :: CK_DRIVE_PAD_CTL :: ADDR_CTL_ND_TERM_STRENGTH [14:10] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_CK_DRIVE_PAD_CTL_ADDR_CTL_ND_TERM_STRENGTH_MASK 0x00007c00
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_CK_DRIVE_PAD_CTL_ADDR_CTL_ND_TERM_STRENGTH_SHIFT 10
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_CK_DRIVE_PAD_CTL_ADDR_CTL_ND_TERM_STRENGTH_DEFAULT 0x00000008
-
-/* DDR34_PHY_CONTROL_REGS_0 :: CK_DRIVE_PAD_CTL :: ADDR_CTL_PD_STRENGTH [09:05] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_CK_DRIVE_PAD_CTL_ADDR_CTL_PD_STRENGTH_MASK 0x000003e0
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_CK_DRIVE_PAD_CTL_ADDR_CTL_PD_STRENGTH_SHIFT 5
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_CK_DRIVE_PAD_CTL_ADDR_CTL_PD_STRENGTH_DEFAULT 0x00000010
-
-/* DDR34_PHY_CONTROL_REGS_0 :: CK_DRIVE_PAD_CTL :: ADDR_CTL_ND_STRENGTH [04:00] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_CK_DRIVE_PAD_CTL_ADDR_CTL_ND_STRENGTH_MASK 0x0000001f
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_CK_DRIVE_PAD_CTL_ADDR_CTL_ND_STRENGTH_SHIFT 0
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_CK_DRIVE_PAD_CTL_ADDR_CTL_ND_STRENGTH_DEFAULT 0x00000010
-
-/***************************************************************************
- *LDO_COMP_CONTROL - LDO Comparator Control register
- ***************************************************************************/
-/* DDR34_PHY_CONTROL_REGS_0 :: LDO_COMP_CONTROL :: reserved0 [31:05] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_LDO_COMP_CONTROL_reserved0_MASK 0xffffffe0
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_LDO_COMP_CONTROL_reserved0_SHIFT 5
-
-/* DDR34_PHY_CONTROL_REGS_0 :: LDO_COMP_CONTROL :: AUX_GT_INT [04:04] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_LDO_COMP_CONTROL_AUX_GT_INT_MASK 0x00000010
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_LDO_COMP_CONTROL_AUX_GT_INT_SHIFT 4
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_LDO_COMP_CONTROL_AUX_GT_INT_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: LDO_COMP_CONTROL :: TESTOUT_MUX_CTL [03:01] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_LDO_COMP_CONTROL_TESTOUT_MUX_CTL_MASK 0x0000000e
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_LDO_COMP_CONTROL_TESTOUT_MUX_CTL_SHIFT 1
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_LDO_COMP_CONTROL_TESTOUT_MUX_CTL_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: LDO_COMP_CONTROL :: TEST [00:00] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_LDO_COMP_CONTROL_TEST_MASK 0x00000001
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_LDO_COMP_CONTROL_TEST_SHIFT 0
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_LDO_COMP_CONTROL_TEST_DEFAULT 0x00000000
-
-/***************************************************************************
- *BYTE_LANE_ALIGN_MASKS - Byte-lane alignment mask register
- ***************************************************************************/
-/* DDR34_PHY_CONTROL_REGS_0 :: BYTE_LANE_ALIGN_MASKS :: reserved0 [31:26] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_BYTE_LANE_ALIGN_MASKS_reserved0_MASK 0xfc000000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_BYTE_LANE_ALIGN_MASKS_reserved0_SHIFT 26
-
-/* DDR34_PHY_CONTROL_REGS_0 :: BYTE_LANE_ALIGN_MASKS :: MASK_ENABLE [25:25] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_BYTE_LANE_ALIGN_MASKS_MASK_ENABLE_MASK 0x02000000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_BYTE_LANE_ALIGN_MASKS_MASK_ENABLE_SHIFT 25
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_BYTE_LANE_ALIGN_MASKS_MASK_ENABLE_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: BYTE_LANE_ALIGN_MASKS :: BL4_MASK [24:20] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_BYTE_LANE_ALIGN_MASKS_BL4_MASK_MASK 0x01f00000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_BYTE_LANE_ALIGN_MASKS_BL4_MASK_SHIFT 20
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_BYTE_LANE_ALIGN_MASKS_BL4_MASK_DEFAULT 0x00000010
-
-/* DDR34_PHY_CONTROL_REGS_0 :: BYTE_LANE_ALIGN_MASKS :: BL3_MASK [19:15] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_BYTE_LANE_ALIGN_MASKS_BL3_MASK_MASK 0x000f8000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_BYTE_LANE_ALIGN_MASKS_BL3_MASK_SHIFT 15
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_BYTE_LANE_ALIGN_MASKS_BL3_MASK_DEFAULT 0x0000000f
-
-/* DDR34_PHY_CONTROL_REGS_0 :: BYTE_LANE_ALIGN_MASKS :: BL2_MASK [14:10] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_BYTE_LANE_ALIGN_MASKS_BL2_MASK_MASK 0x00007c00
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_BYTE_LANE_ALIGN_MASKS_BL2_MASK_SHIFT 10
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_BYTE_LANE_ALIGN_MASKS_BL2_MASK_DEFAULT 0x0000000f
-
-/* DDR34_PHY_CONTROL_REGS_0 :: BYTE_LANE_ALIGN_MASKS :: BL1_MASK [09:05] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_BYTE_LANE_ALIGN_MASKS_BL1_MASK_MASK 0x000003e0
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_BYTE_LANE_ALIGN_MASKS_BL1_MASK_SHIFT 5
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_BYTE_LANE_ALIGN_MASKS_BL1_MASK_DEFAULT 0x0000000f
-
-/* DDR34_PHY_CONTROL_REGS_0 :: BYTE_LANE_ALIGN_MASKS :: BL0_MASK [04:00] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_BYTE_LANE_ALIGN_MASKS_BL0_MASK_MASK 0x0000001f
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_BYTE_LANE_ALIGN_MASKS_BL0_MASK_SHIFT 0
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_BYTE_LANE_ALIGN_MASKS_BL0_MASK_DEFAULT 0x0000000f
-
-/***************************************************************************
- *CLOCK_IDLE - Clock Idle Register
- ***************************************************************************/
-/* DDR34_PHY_CONTROL_REGS_0 :: CLOCK_IDLE :: reserved0 [31:05] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_CLOCK_IDLE_reserved0_MASK 0xffffffe0
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_CLOCK_IDLE_reserved0_SHIFT 5
-
-/* DDR34_PHY_CONTROL_REGS_0 :: CLOCK_IDLE :: BIT_CLOCK_CS [04:04] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_CLOCK_IDLE_BIT_CLOCK_CS_MASK 0x00000010
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_CLOCK_IDLE_BIT_CLOCK_CS_SHIFT 4
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_CLOCK_IDLE_BIT_CLOCK_CS_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: CLOCK_IDLE :: BIT_CLOCK_LS [03:03] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_CLOCK_IDLE_BIT_CLOCK_LS_MASK 0x00000008
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_CLOCK_IDLE_BIT_CLOCK_LS_SHIFT 3
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_CLOCK_IDLE_BIT_CLOCK_LS_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: CLOCK_IDLE :: TO_MC_CLOCK [02:02] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_CLOCK_IDLE_TO_MC_CLOCK_MASK 0x00000004
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_CLOCK_IDLE_TO_MC_CLOCK_SHIFT 2
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_CLOCK_IDLE_TO_MC_CLOCK_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: CLOCK_IDLE :: FROM_MC_CLOCK [01:01] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_CLOCK_IDLE_FROM_MC_CLOCK_MASK 0x00000002
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_CLOCK_IDLE_FROM_MC_CLOCK_SHIFT 1
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_CLOCK_IDLE_FROM_MC_CLOCK_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: CLOCK_IDLE :: BIT_CLOCK [00:00] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_CLOCK_IDLE_BIT_CLOCK_MASK 0x00000001
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_CLOCK_IDLE_BIT_CLOCK_SHIFT 0
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_CLOCK_IDLE_BIT_CLOCK_DEFAULT 0x00000000
-
-/***************************************************************************
- *AC_SPARE_REG - Address and Control Spare register
- ***************************************************************************/
-/* DDR34_PHY_CONTROL_REGS_0 :: AC_SPARE_REG :: reserved_for_eco0 [31:00] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_AC_SPARE_REG_reserved_for_eco0_MASK 0xffffffff
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_AC_SPARE_REG_reserved_for_eco0_SHIFT 0
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_AC_SPARE_REG_reserved_for_eco0_DEFAULT 0x00000000
-
-#endif /* #ifndef BCHP_DDR34_PHY_CONTROL_REGS_0_H__ */
-
-/* End of File */
diff --git a/include/linux/brcmstb/7366b0/bchp_ebi.h b/include/linux/brcmstb/7366b0/bchp_ebi.h
deleted file mode 100644
index 8d28b01..0000000
--- a/include/linux/brcmstb/7366b0/bchp_ebi.h
+++ /dev/null
@@ -1,2005 +0,0 @@
-/***************************************************************************
- * Copyright (c) 1999-2012, Broadcom Corporation
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
- *
- * Module Description:
- * DO NOT EDIT THIS FILE DIRECTLY
- *
- * This module was generated magically with RDB from a source description
- * file. You must edit the source file for changes to be made to this file.
- *
- *
- * Date: Generated on Wed Oct 17 03:11:30 2012
- * MD5 Checksum d41d8cd98f00b204e9800998ecf8427e
- *
- * Compiled with: RDB Utility combo_header.pl
- * RDB Parser 3.0
- * unknown unknown
- * Perl Interpreter 5.008008
- * Operating System linux
- *
- * Revision History:
- *
- * $brcm_Log: $
- *
- ***************************************************************************/
-
-#ifndef BCHP_EBI_H__
-#define BCHP_EBI_H__
-
-/***************************************************************************
- *EBI - EBI Registers
- ***************************************************************************/
-#define BCHP_EBI_CS_BASE_HI_0 0x00440800 /* Upper 8-bit of EBI CS Base 0 Register */
-#define BCHP_EBI_CS_BASE_0 0x00440804 /* Lower 32-bit of EBI CS Base 0 Register */
-#define BCHP_EBI_CS_CONFIG_0 0x00440808 /* EBI CS Config 0 Register */
-#define BCHP_EBI_CS_BASE_HI_1 0x0044080c /* Upper 8-bit of EBI CS Base 1 Register */
-#define BCHP_EBI_CS_BASE_1 0x00440810 /* Lower 32-bit of EBI CS Base 1 Register */
-#define BCHP_EBI_CS_CONFIG_1 0x00440814 /* EBI CS Config 1 Register */
-#define BCHP_EBI_CS_BASE_HI_2 0x00440818 /* Upper 8-bit of EBI CS Base 2 Register */
-#define BCHP_EBI_CS_BASE_2 0x0044081c /* Lower 32-bit of EBI CS Base 2 Register */
-#define BCHP_EBI_CS_CONFIG_2 0x00440820 /* EBI CS Config 2 Register */
-#define BCHP_EBI_CS_BASE_HI_3 0x00440824 /* Upper 8-bit of EBI CS Base 3 Register */
-#define BCHP_EBI_CS_BASE_3 0x00440828 /* Lower 32-bit of EBI CS Base 3 Register */
-#define BCHP_EBI_CS_CONFIG_3 0x0044082c /* EBI CS Config 3 Register */
-#define BCHP_EBI_CS_BASE_HI_4 0x00440830 /* Upper 8-bit of EBI CS Base 4 Register */
-#define BCHP_EBI_CS_BASE_4 0x00440834 /* Lower 32-bit of EBI CS Base 4 Register */
-#define BCHP_EBI_CS_CONFIG_4 0x00440838 /* EBI CS Config 4 Register */
-#define BCHP_EBI_CS_BASE_HI_5 0x0044083c /* Upper 8-bit of EBI CS Base 5 Register */
-#define BCHP_EBI_CS_BASE_5 0x00440840 /* Lower 32-bit of EBI CS Base 5 Register */
-#define BCHP_EBI_CS_CONFIG_5 0x00440844 /* EBI CS Config 5 Register */
-#define BCHP_EBI_CS_BASE_HI_6 0x00440848 /* Upper 8-bit of EBI CS Base 6 Register */
-#define BCHP_EBI_CS_BASE_6 0x0044084c /* Lower 32-bit of EBI CS Base 6 Register */
-#define BCHP_EBI_CS_CONFIG_6 0x00440850 /* EBI CS Config 6 Register */
-#define BCHP_EBI_BURST_CFG_0 0x00440860 /* EBI Synchronous Intel StrataFlash Burst Configure Register */
-#define BCHP_EBI_BURST_CFG_1 0x00440864 /* EBI Synchronous Intel StrataFlash Burst Configure Register */
-#define BCHP_EBI_BURST_CFG_2 0x00440868 /* EBI Synchronous Intel StrataFlash Burst Configure Register */
-#define BCHP_EBI_BURST_CFG_3 0x0044086c /* EBI Synchronous Intel StrataFlash Burst Configure Register */
-#define BCHP_EBI_BURST_CFG_4 0x00440870 /* EBI Synchronous Intel StrataFlash Burst Configure Register */
-#define BCHP_EBI_BURST_CFG_5 0x00440874 /* EBI Synchronous Intel StrataFlash Burst Configure Register */
-#define BCHP_EBI_BURST_CFG_6 0x00440878 /* EBI Synchronous Intel StrataFlash Burst Configure Register */
-#define BCHP_EBI_ECR 0x00440900 /* EBI Configuration Register */
-#define BCHP_EBI_CS_TRISTATE_CFG 0x00440918 /* EBI CS Tristate Configuration Register */
-#define BCHP_EBI_CS_SPI_SELECT 0x00440920 /* SPI CS Select */
-#define BCHP_EBI_ARRAY_ADDRESS 0x004409f0 /* EBI Data Array Address */
-
-/***************************************************************************
- *CS_BASE_HI_0 - Upper 8-bit of EBI CS Base 0 Register
- ***************************************************************************/
-/* EBI :: CS_BASE_HI_0 :: reserved0 [31:08] */
-#define BCHP_EBI_CS_BASE_HI_0_reserved0_MASK 0xffffff00
-#define BCHP_EBI_CS_BASE_HI_0_reserved0_SHIFT 8
-
-/* EBI :: CS_BASE_HI_0 :: base_addr_hi [07:00] */
-#define BCHP_EBI_CS_BASE_HI_0_base_addr_hi_MASK 0x000000ff
-#define BCHP_EBI_CS_BASE_HI_0_base_addr_hi_SHIFT 0
-#define BCHP_EBI_CS_BASE_HI_0_base_addr_hi_DEFAULT 0x00000000
-
-/***************************************************************************
- *CS_BASE_0 - Lower 32-bit of EBI CS Base 0 Register
- ***************************************************************************/
-/* EBI :: CS_BASE_0 :: base_addr [31:13] */
-#define BCHP_EBI_CS_BASE_0_base_addr_MASK 0xffffe000
-#define BCHP_EBI_CS_BASE_0_base_addr_SHIFT 13
-
-/* EBI :: CS_BASE_0 :: reserved0 [12:04] */
-#define BCHP_EBI_CS_BASE_0_reserved0_MASK 0x00001ff0
-#define BCHP_EBI_CS_BASE_0_reserved0_SHIFT 4
-
-/* EBI :: CS_BASE_0 :: size [03:00] */
-#define BCHP_EBI_CS_BASE_0_size_MASK 0x0000000f
-#define BCHP_EBI_CS_BASE_0_size_SHIFT 0
-#define BCHP_EBI_CS_BASE_0_size_SIZE_8KB 0
-#define BCHP_EBI_CS_BASE_0_size_SIZE_16KB 1
-#define BCHP_EBI_CS_BASE_0_size_SIZE_32KB 2
-#define BCHP_EBI_CS_BASE_0_size_SIZE_64KB 3
-#define BCHP_EBI_CS_BASE_0_size_SIZE_128KB 4
-#define BCHP_EBI_CS_BASE_0_size_SIZE_256KB 5
-#define BCHP_EBI_CS_BASE_0_size_SIZE_512KB 6
-#define BCHP_EBI_CS_BASE_0_size_SIZE_1MB 7
-#define BCHP_EBI_CS_BASE_0_size_SIZE_2MB 8
-#define BCHP_EBI_CS_BASE_0_size_SIZE_4MB 9
-#define BCHP_EBI_CS_BASE_0_size_SIZE_8MB 10
-#define BCHP_EBI_CS_BASE_0_size_SIZE_16MB 11
-#define BCHP_EBI_CS_BASE_0_size_SIZE_32MB 12
-#define BCHP_EBI_CS_BASE_0_size_SIZE_64MB 13
-#define BCHP_EBI_CS_BASE_0_size_SIZE_128MB 14
-#define BCHP_EBI_CS_BASE_0_size_SIZE_256MB 15
-
-/***************************************************************************
- *CS_CONFIG_0 - EBI CS Config 0 Register
- ***************************************************************************/
-/* EBI :: CS_CONFIG_0 :: mem_io [31:31] */
-#define BCHP_EBI_CS_CONFIG_0_mem_io_MASK 0x80000000
-#define BCHP_EBI_CS_CONFIG_0_mem_io_SHIFT 31
-#define BCHP_EBI_CS_CONFIG_0_mem_io_DEFAULT 0x00000000
-
-/* EBI :: CS_CONFIG_0 :: ta_wait [30:30] */
-#define BCHP_EBI_CS_CONFIG_0_ta_wait_MASK 0x40000000
-#define BCHP_EBI_CS_CONFIG_0_ta_wait_SHIFT 30
-#define BCHP_EBI_CS_CONFIG_0_ta_wait_DEFAULT 0x00000000
-
-/* EBI :: CS_CONFIG_0 :: wp [29:29] */
-#define BCHP_EBI_CS_CONFIG_0_wp_MASK 0x20000000
-#define BCHP_EBI_CS_CONFIG_0_wp_SHIFT 29
-#define BCHP_EBI_CS_CONFIG_0_wp_DEFAULT 0x00000000
-
-/* EBI :: CS_CONFIG_0 :: wait_count [28:24] */
-#define BCHP_EBI_CS_CONFIG_0_wait_count_MASK 0x1f000000
-#define BCHP_EBI_CS_CONFIG_0_wait_count_SHIFT 24
-#define BCHP_EBI_CS_CONFIG_0_wait_count_DEFAULT 0x00000007
-
-/* EBI :: CS_CONFIG_0 :: t_hold [23:20] */
-#define BCHP_EBI_CS_CONFIG_0_t_hold_MASK 0x00f00000
-#define BCHP_EBI_CS_CONFIG_0_t_hold_SHIFT 20
-#define BCHP_EBI_CS_CONFIG_0_t_hold_DEFAULT 0x00000000
-
-/* EBI :: CS_CONFIG_0 :: t_setup [19:16] */
-#define BCHP_EBI_CS_CONFIG_0_t_setup_MASK 0x000f0000
-#define BCHP_EBI_CS_CONFIG_0_t_setup_SHIFT 16
-#define BCHP_EBI_CS_CONFIG_0_t_setup_DEFAULT 0x00000000
-
-/* EBI :: CS_CONFIG_0 :: cs_hold [15:15] */
-#define BCHP_EBI_CS_CONFIG_0_cs_hold_MASK 0x00008000
-#define BCHP_EBI_CS_CONFIG_0_cs_hold_SHIFT 15
-#define BCHP_EBI_CS_CONFIG_0_cs_hold_DEFAULT 0x00000000
-
-/* EBI :: CS_CONFIG_0 :: split_cs [14:14] */
-#define BCHP_EBI_CS_CONFIG_0_split_cs_MASK 0x00004000
-#define BCHP_EBI_CS_CONFIG_0_split_cs_SHIFT 14
-#define BCHP_EBI_CS_CONFIG_0_split_cs_DEFAULT 0x00000000
-
-/* EBI :: CS_CONFIG_0 :: mask_en [13:13] */
-#define BCHP_EBI_CS_CONFIG_0_mask_en_MASK 0x00002000
-#define BCHP_EBI_CS_CONFIG_0_mask_en_SHIFT 13
-#define BCHP_EBI_CS_CONFIG_0_mask_en_DEFAULT 0x00000000
-
-/* EBI :: CS_CONFIG_0 :: ne_sample [12:12] */
-#define BCHP_EBI_CS_CONFIG_0_ne_sample_MASK 0x00001000
-#define BCHP_EBI_CS_CONFIG_0_ne_sample_SHIFT 12
-#define BCHP_EBI_CS_CONFIG_0_ne_sample_DEFAULT 0x00000000
-
-/* EBI :: CS_CONFIG_0 :: m68k [11:11] */
-#define BCHP_EBI_CS_CONFIG_0_m68k_MASK 0x00000800
-#define BCHP_EBI_CS_CONFIG_0_m68k_SHIFT 11
-#define BCHP_EBI_CS_CONFIG_0_m68k_DEFAULT 0x00000000
-
-/* EBI :: CS_CONFIG_0 :: le [10:10] */
-#define BCHP_EBI_CS_CONFIG_0_le_MASK 0x00000400
-#define BCHP_EBI_CS_CONFIG_0_le_SHIFT 10
-
-/* EBI :: CS_CONFIG_0 :: fast_read [09:09] */
-#define BCHP_EBI_CS_CONFIG_0_fast_read_MASK 0x00000200
-#define BCHP_EBI_CS_CONFIG_0_fast_read_SHIFT 9
-#define BCHP_EBI_CS_CONFIG_0_fast_read_DEFAULT 0x00000000
-#define BCHP_EBI_CS_CONFIG_0_fast_read_Normal 0
-#define BCHP_EBI_CS_CONFIG_0_fast_read_Fast_Read_Enable 1
-
-/* EBI :: CS_CONFIG_0 :: size_sel [08:08] */
-#define BCHP_EBI_CS_CONFIG_0_size_sel_MASK 0x00000100
-#define BCHP_EBI_CS_CONFIG_0_size_sel_SHIFT 8
-#define BCHP_EBI_CS_CONFIG_0_size_sel_DEFAULT 0x00000000
-
-/* EBI :: CS_CONFIG_0 :: sync [07:07] */
-#define BCHP_EBI_CS_CONFIG_0_sync_MASK 0x00000080
-#define BCHP_EBI_CS_CONFIG_0_sync_SHIFT 7
-#define BCHP_EBI_CS_CONFIG_0_sync_DEFAULT 0x00000000
-
-/* EBI :: CS_CONFIG_0 :: polarity [06:06] */
-#define BCHP_EBI_CS_CONFIG_0_polarity_MASK 0x00000040
-#define BCHP_EBI_CS_CONFIG_0_polarity_SHIFT 6
-#define BCHP_EBI_CS_CONFIG_0_polarity_DEFAULT 0x00000000
-
-/* EBI :: CS_CONFIG_0 :: we_ctl [05:05] */
-#define BCHP_EBI_CS_CONFIG_0_we_ctl_MASK 0x00000020
-#define BCHP_EBI_CS_CONFIG_0_we_ctl_SHIFT 5
-#define BCHP_EBI_CS_CONFIG_0_we_ctl_DEFAULT 0x00000000
-
-/* EBI :: CS_CONFIG_0 :: dest_size [04:04] */
-#define BCHP_EBI_CS_CONFIG_0_dest_size_MASK 0x00000010
-#define BCHP_EBI_CS_CONFIG_0_dest_size_SHIFT 4
-
-/* EBI :: CS_CONFIG_0 :: ms_inh [03:03] */
-#define BCHP_EBI_CS_CONFIG_0_ms_inh_MASK 0x00000008
-#define BCHP_EBI_CS_CONFIG_0_ms_inh_SHIFT 3
-#define BCHP_EBI_CS_CONFIG_0_ms_inh_DEFAULT 0x00000000
-
-/* EBI :: CS_CONFIG_0 :: ls_inh [02:02] */
-#define BCHP_EBI_CS_CONFIG_0_ls_inh_MASK 0x00000004
-#define BCHP_EBI_CS_CONFIG_0_ls_inh_SHIFT 2
-#define BCHP_EBI_CS_CONFIG_0_ls_inh_DEFAULT 0x00000000
-
-/* EBI :: CS_CONFIG_0 :: bcachen [01:01] */
-#define BCHP_EBI_CS_CONFIG_0_bcachen_MASK 0x00000002
-#define BCHP_EBI_CS_CONFIG_0_bcachen_SHIFT 1
-#define BCHP_EBI_CS_CONFIG_0_bcachen_DEFAULT 0x00000000
-
-/* EBI :: CS_CONFIG_0 :: enable [00:00] */
-#define BCHP_EBI_CS_CONFIG_0_enable_MASK 0x00000001
-#define BCHP_EBI_CS_CONFIG_0_enable_SHIFT 0
-#define BCHP_EBI_CS_CONFIG_0_enable_DEFAULT 0x00000001
-
-/***************************************************************************
- *CS_BASE_HI_1 - Upper 8-bit of EBI CS Base 1 Register
- ***************************************************************************/
-/* EBI :: CS_BASE_HI_1 :: reserved0 [31:08] */
-#define BCHP_EBI_CS_BASE_HI_1_reserved0_MASK 0xffffff00
-#define BCHP_EBI_CS_BASE_HI_1_reserved0_SHIFT 8
-
-/* EBI :: CS_BASE_HI_1 :: base_addr_hi [07:00] */
-#define BCHP_EBI_CS_BASE_HI_1_base_addr_hi_MASK 0x000000ff
-#define BCHP_EBI_CS_BASE_HI_1_base_addr_hi_SHIFT 0
-#define BCHP_EBI_CS_BASE_HI_1_base_addr_hi_DEFAULT 0x00000000
-
-/***************************************************************************
- *CS_BASE_1 - Lower 32-bit of EBI CS Base 1 Register
- ***************************************************************************/
-/* EBI :: CS_BASE_1 :: base_addr [31:13] */
-#define BCHP_EBI_CS_BASE_1_base_addr_MASK 0xffffe000
-#define BCHP_EBI_CS_BASE_1_base_addr_SHIFT 13
-#define BCHP_EBI_CS_BASE_1_base_addr_DEFAULT 0x00000000
-
-/* EBI :: CS_BASE_1 :: reserved0 [12:04] */
-#define BCHP_EBI_CS_BASE_1_reserved0_MASK 0x00001ff0
-#define BCHP_EBI_CS_BASE_1_reserved0_SHIFT 4
-
-/* EBI :: CS_BASE_1 :: size [03:00] */
-#define BCHP_EBI_CS_BASE_1_size_MASK 0x0000000f
-#define BCHP_EBI_CS_BASE_1_size_SHIFT 0
-#define BCHP_EBI_CS_BASE_1_size_DEFAULT 0x00000000
-#define BCHP_EBI_CS_BASE_1_size_SIZE_8KB 0
-#define BCHP_EBI_CS_BASE_1_size_SIZE_16KB 1
-#define BCHP_EBI_CS_BASE_1_size_SIZE_32KB 2
-#define BCHP_EBI_CS_BASE_1_size_SIZE_64KB 3
-#define BCHP_EBI_CS_BASE_1_size_SIZE_128KB 4
-#define BCHP_EBI_CS_BASE_1_size_SIZE_256KB 5
-#define BCHP_EBI_CS_BASE_1_size_SIZE_512KB 6
-#define BCHP_EBI_CS_BASE_1_size_SIZE_1MB 7
-#define BCHP_EBI_CS_BASE_1_size_SIZE_2MB 8
-#define BCHP_EBI_CS_BASE_1_size_SIZE_4MB 9
-#define BCHP_EBI_CS_BASE_1_size_SIZE_8MB 10
-#define BCHP_EBI_CS_BASE_1_size_SIZE_16MB 11
-#define BCHP_EBI_CS_BASE_1_size_SIZE_32MB 12
-#define BCHP_EBI_CS_BASE_1_size_SIZE_64MB 13
-#define BCHP_EBI_CS_BASE_1_size_SIZE_128MB 14
-#define BCHP_EBI_CS_BASE_1_size_SIZE_256MB 15
-
-/***************************************************************************
- *CS_CONFIG_1 - EBI CS Config 1 Register
- ***************************************************************************/
-/* EBI :: CS_CONFIG_1 :: mem_io [31:31] */
-#define BCHP_EBI_CS_CONFIG_1_mem_io_MASK 0x80000000
-#define BCHP_EBI_CS_CONFIG_1_mem_io_SHIFT 31
-#define BCHP_EBI_CS_CONFIG_1_mem_io_DEFAULT 0x00000000
-
-/* EBI :: CS_CONFIG_1 :: ta_wait [30:30] */
-#define BCHP_EBI_CS_CONFIG_1_ta_wait_MASK 0x40000000
-#define BCHP_EBI_CS_CONFIG_1_ta_wait_SHIFT 30
-#define BCHP_EBI_CS_CONFIG_1_ta_wait_DEFAULT 0x00000000
-
-/* EBI :: CS_CONFIG_1 :: wp [29:29] */
-#define BCHP_EBI_CS_CONFIG_1_wp_MASK 0x20000000
-#define BCHP_EBI_CS_CONFIG_1_wp_SHIFT 29
-#define BCHP_EBI_CS_CONFIG_1_wp_DEFAULT 0x00000000
-
-/* EBI :: CS_CONFIG_1 :: wait_count [28:24] */
-#define BCHP_EBI_CS_CONFIG_1_wait_count_MASK 0x1f000000
-#define BCHP_EBI_CS_CONFIG_1_wait_count_SHIFT 24
-#define BCHP_EBI_CS_CONFIG_1_wait_count_DEFAULT 0x00000007
-
-/* EBI :: CS_CONFIG_1 :: t_hold [23:20] */
-#define BCHP_EBI_CS_CONFIG_1_t_hold_MASK 0x00f00000
-#define BCHP_EBI_CS_CONFIG_1_t_hold_SHIFT 20
-#define BCHP_EBI_CS_CONFIG_1_t_hold_DEFAULT 0x00000000
-
-/* EBI :: CS_CONFIG_1 :: t_setup [19:16] */
-#define BCHP_EBI_CS_CONFIG_1_t_setup_MASK 0x000f0000
-#define BCHP_EBI_CS_CONFIG_1_t_setup_SHIFT 16
-#define BCHP_EBI_CS_CONFIG_1_t_setup_DEFAULT 0x00000000
-
-/* EBI :: CS_CONFIG_1 :: cs_hold [15:15] */
-#define BCHP_EBI_CS_CONFIG_1_cs_hold_MASK 0x00008000
-#define BCHP_EBI_CS_CONFIG_1_cs_hold_SHIFT 15
-#define BCHP_EBI_CS_CONFIG_1_cs_hold_DEFAULT 0x00000000
-
-/* EBI :: CS_CONFIG_1 :: split_cs [14:14] */
-#define BCHP_EBI_CS_CONFIG_1_split_cs_MASK 0x00004000
-#define BCHP_EBI_CS_CONFIG_1_split_cs_SHIFT 14
-#define BCHP_EBI_CS_CONFIG_1_split_cs_DEFAULT 0x00000000
-
-/* EBI :: CS_CONFIG_1 :: mask_en [13:13] */
-#define BCHP_EBI_CS_CONFIG_1_mask_en_MASK 0x00002000
-#define BCHP_EBI_CS_CONFIG_1_mask_en_SHIFT 13
-#define BCHP_EBI_CS_CONFIG_1_mask_en_DEFAULT 0x00000000
-
-/* EBI :: CS_CONFIG_1 :: ne_sample [12:12] */
-#define BCHP_EBI_CS_CONFIG_1_ne_sample_MASK 0x00001000
-#define BCHP_EBI_CS_CONFIG_1_ne_sample_SHIFT 12
-#define BCHP_EBI_CS_CONFIG_1_ne_sample_DEFAULT 0x00000000
-
-/* EBI :: CS_CONFIG_1 :: m68k [11:11] */
-#define BCHP_EBI_CS_CONFIG_1_m68k_MASK 0x00000800
-#define BCHP_EBI_CS_CONFIG_1_m68k_SHIFT 11
-#define BCHP_EBI_CS_CONFIG_1_m68k_DEFAULT 0x00000000
-
-/* EBI :: CS_CONFIG_1 :: le [10:10] */
-#define BCHP_EBI_CS_CONFIG_1_le_MASK 0x00000400
-#define BCHP_EBI_CS_CONFIG_1_le_SHIFT 10
-#define BCHP_EBI_CS_CONFIG_1_le_DEFAULT 0x00000000
-
-/* EBI :: CS_CONFIG_1 :: fast_read [09:09] */
-#define BCHP_EBI_CS_CONFIG_1_fast_read_MASK 0x00000200
-#define BCHP_EBI_CS_CONFIG_1_fast_read_SHIFT 9
-#define BCHP_EBI_CS_CONFIG_1_fast_read_DEFAULT 0x00000000
-#define BCHP_EBI_CS_CONFIG_1_fast_read_Normal 0
-#define BCHP_EBI_CS_CONFIG_1_fast_read_Fast_Read_Enable 1
-
-/* EBI :: CS_CONFIG_1 :: size_sel [08:08] */
-#define BCHP_EBI_CS_CONFIG_1_size_sel_MASK 0x00000100
-#define BCHP_EBI_CS_CONFIG_1_size_sel_SHIFT 8
-#define BCHP_EBI_CS_CONFIG_1_size_sel_DEFAULT 0x00000000
-
-/* EBI :: CS_CONFIG_1 :: sync [07:07] */
-#define BCHP_EBI_CS_CONFIG_1_sync_MASK 0x00000080
-#define BCHP_EBI_CS_CONFIG_1_sync_SHIFT 7
-#define BCHP_EBI_CS_CONFIG_1_sync_DEFAULT 0x00000000
-
-/* EBI :: CS_CONFIG_1 :: polarity [06:06] */
-#define BCHP_EBI_CS_CONFIG_1_polarity_MASK 0x00000040
-#define BCHP_EBI_CS_CONFIG_1_polarity_SHIFT 6
-#define BCHP_EBI_CS_CONFIG_1_polarity_DEFAULT 0x00000000
-
-/* EBI :: CS_CONFIG_1 :: we_ctl [05:05] */
-#define BCHP_EBI_CS_CONFIG_1_we_ctl_MASK 0x00000020
-#define BCHP_EBI_CS_CONFIG_1_we_ctl_SHIFT 5
-#define BCHP_EBI_CS_CONFIG_1_we_ctl_DEFAULT 0x00000000
-
-/* EBI :: CS_CONFIG_1 :: dest_size [04:04] */
-#define BCHP_EBI_CS_CONFIG_1_dest_size_MASK 0x00000010
-#define BCHP_EBI_CS_CONFIG_1_dest_size_SHIFT 4
-#define BCHP_EBI_CS_CONFIG_1_dest_size_DEFAULT 0x00000000
-
-/* EBI :: CS_CONFIG_1 :: ms_inh [03:03] */
-#define BCHP_EBI_CS_CONFIG_1_ms_inh_MASK 0x00000008
-#define BCHP_EBI_CS_CONFIG_1_ms_inh_SHIFT 3
-#define BCHP_EBI_CS_CONFIG_1_ms_inh_DEFAULT 0x00000000
-
-/* EBI :: CS_CONFIG_1 :: ls_inh [02:02] */
-#define BCHP_EBI_CS_CONFIG_1_ls_inh_MASK 0x00000004
-#define BCHP_EBI_CS_CONFIG_1_ls_inh_SHIFT 2
-#define BCHP_EBI_CS_CONFIG_1_ls_inh_DEFAULT 0x00000000
-
-/* EBI :: CS_CONFIG_1 :: bcachen [01:01] */
-#define BCHP_EBI_CS_CONFIG_1_bcachen_MASK 0x00000002
-#define BCHP_EBI_CS_CONFIG_1_bcachen_SHIFT 1
-#define BCHP_EBI_CS_CONFIG_1_bcachen_DEFAULT 0x00000000
-
-/* EBI :: CS_CONFIG_1 :: enable [00:00] */
-#define BCHP_EBI_CS_CONFIG_1_enable_MASK 0x00000001
-#define BCHP_EBI_CS_CONFIG_1_enable_SHIFT 0
-#define BCHP_EBI_CS_CONFIG_1_enable_DEFAULT 0x00000000
-
-/***************************************************************************
- *CS_BASE_HI_2 - Upper 8-bit of EBI CS Base 2 Register
- ***************************************************************************/
-/* EBI :: CS_BASE_HI_2 :: reserved0 [31:08] */
-#define BCHP_EBI_CS_BASE_HI_2_reserved0_MASK 0xffffff00
-#define BCHP_EBI_CS_BASE_HI_2_reserved0_SHIFT 8
-
-/* EBI :: CS_BASE_HI_2 :: base_addr_hi [07:00] */
-#define BCHP_EBI_CS_BASE_HI_2_base_addr_hi_MASK 0x000000ff
-#define BCHP_EBI_CS_BASE_HI_2_base_addr_hi_SHIFT 0
-#define BCHP_EBI_CS_BASE_HI_2_base_addr_hi_DEFAULT 0x00000000
-
-/***************************************************************************
- *CS_BASE_2 - Lower 32-bit of EBI CS Base 2 Register
- ***************************************************************************/
-/* EBI :: CS_BASE_2 :: base_addr [31:13] */
-#define BCHP_EBI_CS_BASE_2_base_addr_MASK 0xffffe000
-#define BCHP_EBI_CS_BASE_2_base_addr_SHIFT 13
-#define BCHP_EBI_CS_BASE_2_base_addr_DEFAULT 0x00000000
-
-/* EBI :: CS_BASE_2 :: reserved0 [12:04] */
-#define BCHP_EBI_CS_BASE_2_reserved0_MASK 0x00001ff0
-#define BCHP_EBI_CS_BASE_2_reserved0_SHIFT 4
-
-/* EBI :: CS_BASE_2 :: size [03:00] */
-#define BCHP_EBI_CS_BASE_2_size_MASK 0x0000000f
-#define BCHP_EBI_CS_BASE_2_size_SHIFT 0
-#define BCHP_EBI_CS_BASE_2_size_DEFAULT 0x00000000
-#define BCHP_EBI_CS_BASE_2_size_SIZE_8KB 0
-#define BCHP_EBI_CS_BASE_2_size_SIZE_16KB 1
-#define BCHP_EBI_CS_BASE_2_size_SIZE_32KB 2
-#define BCHP_EBI_CS_BASE_2_size_SIZE_64KB 3
-#define BCHP_EBI_CS_BASE_2_size_SIZE_128KB 4
-#define BCHP_EBI_CS_BASE_2_size_SIZE_256KB 5
-#define BCHP_EBI_CS_BASE_2_size_SIZE_512KB 6
-#define BCHP_EBI_CS_BASE_2_size_SIZE_1MB 7
-#define BCHP_EBI_CS_BASE_2_size_SIZE_2MB 8
-#define BCHP_EBI_CS_BASE_2_size_SIZE_4MB 9
-#define BCHP_EBI_CS_BASE_2_size_SIZE_8MB 10
-#define BCHP_EBI_CS_BASE_2_size_SIZE_16MB 11
-#define BCHP_EBI_CS_BASE_2_size_SIZE_32MB 12
-#define BCHP_EBI_CS_BASE_2_size_SIZE_64MB 13
-#define BCHP_EBI_CS_BASE_2_size_SIZE_128MB 14
-#define BCHP_EBI_CS_BASE_2_size_SIZE_256MB 15
-
-/***************************************************************************
- *CS_CONFIG_2 - EBI CS Config 2 Register
- ***************************************************************************/
-/* EBI :: CS_CONFIG_2 :: mem_io [31:31] */
-#define BCHP_EBI_CS_CONFIG_2_mem_io_MASK 0x80000000
-#define BCHP_EBI_CS_CONFIG_2_mem_io_SHIFT 31
-#define BCHP_EBI_CS_CONFIG_2_mem_io_DEFAULT 0x00000000
-
-/* EBI :: CS_CONFIG_2 :: ta_wait [30:30] */
-#define BCHP_EBI_CS_CONFIG_2_ta_wait_MASK 0x40000000
-#define BCHP_EBI_CS_CONFIG_2_ta_wait_SHIFT 30
-#define BCHP_EBI_CS_CONFIG_2_ta_wait_DEFAULT 0x00000000
-
-/* EBI :: CS_CONFIG_2 :: wp [29:29] */
-#define BCHP_EBI_CS_CONFIG_2_wp_MASK 0x20000000
-#define BCHP_EBI_CS_CONFIG_2_wp_SHIFT 29
-#define BCHP_EBI_CS_CONFIG_2_wp_DEFAULT 0x00000000
-
-/* EBI :: CS_CONFIG_2 :: wait_count [28:24] */
-#define BCHP_EBI_CS_CONFIG_2_wait_count_MASK 0x1f000000
-#define BCHP_EBI_CS_CONFIG_2_wait_count_SHIFT 24
-#define BCHP_EBI_CS_CONFIG_2_wait_count_DEFAULT 0x00000007
-
-/* EBI :: CS_CONFIG_2 :: t_hold [23:20] */
-#define BCHP_EBI_CS_CONFIG_2_t_hold_MASK 0x00f00000
-#define BCHP_EBI_CS_CONFIG_2_t_hold_SHIFT 20
-#define BCHP_EBI_CS_CONFIG_2_t_hold_DEFAULT 0x00000000
-
-/* EBI :: CS_CONFIG_2 :: t_setup [19:16] */
-#define BCHP_EBI_CS_CONFIG_2_t_setup_MASK 0x000f0000
-#define BCHP_EBI_CS_CONFIG_2_t_setup_SHIFT 16
-#define BCHP_EBI_CS_CONFIG_2_t_setup_DEFAULT 0x00000000
-
-/* EBI :: CS_CONFIG_2 :: cs_hold [15:15] */
-#define BCHP_EBI_CS_CONFIG_2_cs_hold_MASK 0x00008000
-#define BCHP_EBI_CS_CONFIG_2_cs_hold_SHIFT 15
-#define BCHP_EBI_CS_CONFIG_2_cs_hold_DEFAULT 0x00000000
-
-/* EBI :: CS_CONFIG_2 :: split_cs [14:14] */
-#define BCHP_EBI_CS_CONFIG_2_split_cs_MASK 0x00004000
-#define BCHP_EBI_CS_CONFIG_2_split_cs_SHIFT 14
-#define BCHP_EBI_CS_CONFIG_2_split_cs_DEFAULT 0x00000000
-
-/* EBI :: CS_CONFIG_2 :: mask_en [13:13] */
-#define BCHP_EBI_CS_CONFIG_2_mask_en_MASK 0x00002000
-#define BCHP_EBI_CS_CONFIG_2_mask_en_SHIFT 13
-#define BCHP_EBI_CS_CONFIG_2_mask_en_DEFAULT 0x00000000
-
-/* EBI :: CS_CONFIG_2 :: ne_sample [12:12] */
-#define BCHP_EBI_CS_CONFIG_2_ne_sample_MASK 0x00001000
-#define BCHP_EBI_CS_CONFIG_2_ne_sample_SHIFT 12
-#define BCHP_EBI_CS_CONFIG_2_ne_sample_DEFAULT 0x00000000
-
-/* EBI :: CS_CONFIG_2 :: m68k [11:11] */
-#define BCHP_EBI_CS_CONFIG_2_m68k_MASK 0x00000800
-#define BCHP_EBI_CS_CONFIG_2_m68k_SHIFT 11
-#define BCHP_EBI_CS_CONFIG_2_m68k_DEFAULT 0x00000000
-
-/* EBI :: CS_CONFIG_2 :: le [10:10] */
-#define BCHP_EBI_CS_CONFIG_2_le_MASK 0x00000400
-#define BCHP_EBI_CS_CONFIG_2_le_SHIFT 10
-#define BCHP_EBI_CS_CONFIG_2_le_DEFAULT 0x00000000
-
-/* EBI :: CS_CONFIG_2 :: fast_read [09:09] */
-#define BCHP_EBI_CS_CONFIG_2_fast_read_MASK 0x00000200
-#define BCHP_EBI_CS_CONFIG_2_fast_read_SHIFT 9
-#define BCHP_EBI_CS_CONFIG_2_fast_read_DEFAULT 0x00000000
-#define BCHP_EBI_CS_CONFIG_2_fast_read_Normal 0
-#define BCHP_EBI_CS_CONFIG_2_fast_read_Fast_Read_Enable 1
-
-/* EBI :: CS_CONFIG_2 :: size_sel [08:08] */
-#define BCHP_EBI_CS_CONFIG_2_size_sel_MASK 0x00000100
-#define BCHP_EBI_CS_CONFIG_2_size_sel_SHIFT 8
-#define BCHP_EBI_CS_CONFIG_2_size_sel_DEFAULT 0x00000000
-
-/* EBI :: CS_CONFIG_2 :: sync [07:07] */
-#define BCHP_EBI_CS_CONFIG_2_sync_MASK 0x00000080
-#define BCHP_EBI_CS_CONFIG_2_sync_SHIFT 7
-#define BCHP_EBI_CS_CONFIG_2_sync_DEFAULT 0x00000000
-
-/* EBI :: CS_CONFIG_2 :: polarity [06:06] */
-#define BCHP_EBI_CS_CONFIG_2_polarity_MASK 0x00000040
-#define BCHP_EBI_CS_CONFIG_2_polarity_SHIFT 6
-#define BCHP_EBI_CS_CONFIG_2_polarity_DEFAULT 0x00000000
-
-/* EBI :: CS_CONFIG_2 :: we_ctl [05:05] */
-#define BCHP_EBI_CS_CONFIG_2_we_ctl_MASK 0x00000020
-#define BCHP_EBI_CS_CONFIG_2_we_ctl_SHIFT 5
-#define BCHP_EBI_CS_CONFIG_2_we_ctl_DEFAULT 0x00000000
-
-/* EBI :: CS_CONFIG_2 :: dest_size [04:04] */
-#define BCHP_EBI_CS_CONFIG_2_dest_size_MASK 0x00000010
-#define BCHP_EBI_CS_CONFIG_2_dest_size_SHIFT 4
-#define BCHP_EBI_CS_CONFIG_2_dest_size_DEFAULT 0x00000000
-
-/* EBI :: CS_CONFIG_2 :: ms_inh [03:03] */
-#define BCHP_EBI_CS_CONFIG_2_ms_inh_MASK 0x00000008
-#define BCHP_EBI_CS_CONFIG_2_ms_inh_SHIFT 3
-#define BCHP_EBI_CS_CONFIG_2_ms_inh_DEFAULT 0x00000000
-
-/* EBI :: CS_CONFIG_2 :: ls_inh [02:02] */
-#define BCHP_EBI_CS_CONFIG_2_ls_inh_MASK 0x00000004
-#define BCHP_EBI_CS_CONFIG_2_ls_inh_SHIFT 2
-#define BCHP_EBI_CS_CONFIG_2_ls_inh_DEFAULT 0x00000000
-
-/* EBI :: CS_CONFIG_2 :: bcachen [01:01] */
-#define BCHP_EBI_CS_CONFIG_2_bcachen_MASK 0x00000002
-#define BCHP_EBI_CS_CONFIG_2_bcachen_SHIFT 1
-#define BCHP_EBI_CS_CONFIG_2_bcachen_DEFAULT 0x00000000
-
-/* EBI :: CS_CONFIG_2 :: enable [00:00] */
-#define BCHP_EBI_CS_CONFIG_2_enable_MASK 0x00000001
-#define BCHP_EBI_CS_CONFIG_2_enable_SHIFT 0
-#define BCHP_EBI_CS_CONFIG_2_enable_DEFAULT 0x00000000
-
-/***************************************************************************
- *CS_BASE_HI_3 - Upper 8-bit of EBI CS Base 3 Register
- ***************************************************************************/
-/* EBI :: CS_BASE_HI_3 :: reserved0 [31:08] */
-#define BCHP_EBI_CS_BASE_HI_3_reserved0_MASK 0xffffff00
-#define BCHP_EBI_CS_BASE_HI_3_reserved0_SHIFT 8
-
-/* EBI :: CS_BASE_HI_3 :: base_addr_hi [07:00] */
-#define BCHP_EBI_CS_BASE_HI_3_base_addr_hi_MASK 0x000000ff
-#define BCHP_EBI_CS_BASE_HI_3_base_addr_hi_SHIFT 0
-#define BCHP_EBI_CS_BASE_HI_3_base_addr_hi_DEFAULT 0x00000000
-
-/***************************************************************************
- *CS_BASE_3 - Lower 32-bit of EBI CS Base 3 Register
- ***************************************************************************/
-/* EBI :: CS_BASE_3 :: base_addr [31:13] */
-#define BCHP_EBI_CS_BASE_3_base_addr_MASK 0xffffe000
-#define BCHP_EBI_CS_BASE_3_base_addr_SHIFT 13
-#define BCHP_EBI_CS_BASE_3_base_addr_DEFAULT 0x00000000
-
-/* EBI :: CS_BASE_3 :: reserved0 [12:04] */
-#define BCHP_EBI_CS_BASE_3_reserved0_MASK 0x00001ff0
-#define BCHP_EBI_CS_BASE_3_reserved0_SHIFT 4
-
-/* EBI :: CS_BASE_3 :: size [03:00] */
-#define BCHP_EBI_CS_BASE_3_size_MASK 0x0000000f
-#define BCHP_EBI_CS_BASE_3_size_SHIFT 0
-#define BCHP_EBI_CS_BASE_3_size_DEFAULT 0x00000000
-#define BCHP_EBI_CS_BASE_3_size_SIZE_8KB 0
-#define BCHP_EBI_CS_BASE_3_size_SIZE_16KB 1
-#define BCHP_EBI_CS_BASE_3_size_SIZE_32KB 2
-#define BCHP_EBI_CS_BASE_3_size_SIZE_64KB 3
-#define BCHP_EBI_CS_BASE_3_size_SIZE_128KB 4
-#define BCHP_EBI_CS_BASE_3_size_SIZE_256KB 5
-#define BCHP_EBI_CS_BASE_3_size_SIZE_512KB 6
-#define BCHP_EBI_CS_BASE_3_size_SIZE_1MB 7
-#define BCHP_EBI_CS_BASE_3_size_SIZE_2MB 8
-#define BCHP_EBI_CS_BASE_3_size_SIZE_4MB 9
-#define BCHP_EBI_CS_BASE_3_size_SIZE_8MB 10
-#define BCHP_EBI_CS_BASE_3_size_SIZE_16MB 11
-#define BCHP_EBI_CS_BASE_3_size_SIZE_32MB 12
-#define BCHP_EBI_CS_BASE_3_size_SIZE_64MB 13
-#define BCHP_EBI_CS_BASE_3_size_SIZE_128MB 14
-#define BCHP_EBI_CS_BASE_3_size_SIZE_256MB 15
-
-/***************************************************************************
- *CS_CONFIG_3 - EBI CS Config 3 Register
- ***************************************************************************/
-/* EBI :: CS_CONFIG_3 :: mem_io [31:31] */
-#define BCHP_EBI_CS_CONFIG_3_mem_io_MASK 0x80000000
-#define BCHP_EBI_CS_CONFIG_3_mem_io_SHIFT 31
-#define BCHP_EBI_CS_CONFIG_3_mem_io_DEFAULT 0x00000000
-
-/* EBI :: CS_CONFIG_3 :: ta_wait [30:30] */
-#define BCHP_EBI_CS_CONFIG_3_ta_wait_MASK 0x40000000
-#define BCHP_EBI_CS_CONFIG_3_ta_wait_SHIFT 30
-#define BCHP_EBI_CS_CONFIG_3_ta_wait_DEFAULT 0x00000000
-
-/* EBI :: CS_CONFIG_3 :: wp [29:29] */
-#define BCHP_EBI_CS_CONFIG_3_wp_MASK 0x20000000
-#define BCHP_EBI_CS_CONFIG_3_wp_SHIFT 29
-#define BCHP_EBI_CS_CONFIG_3_wp_DEFAULT 0x00000000
-
-/* EBI :: CS_CONFIG_3 :: wait_count [28:24] */
-#define BCHP_EBI_CS_CONFIG_3_wait_count_MASK 0x1f000000
-#define BCHP_EBI_CS_CONFIG_3_wait_count_SHIFT 24
-#define BCHP_EBI_CS_CONFIG_3_wait_count_DEFAULT 0x00000007
-
-/* EBI :: CS_CONFIG_3 :: t_hold [23:20] */
-#define BCHP_EBI_CS_CONFIG_3_t_hold_MASK 0x00f00000
-#define BCHP_EBI_CS_CONFIG_3_t_hold_SHIFT 20
-#define BCHP_EBI_CS_CONFIG_3_t_hold_DEFAULT 0x00000000
-
-/* EBI :: CS_CONFIG_3 :: t_setup [19:16] */
-#define BCHP_EBI_CS_CONFIG_3_t_setup_MASK 0x000f0000
-#define BCHP_EBI_CS_CONFIG_3_t_setup_SHIFT 16
-#define BCHP_EBI_CS_CONFIG_3_t_setup_DEFAULT 0x00000000
-
-/* EBI :: CS_CONFIG_3 :: cs_hold [15:15] */
-#define BCHP_EBI_CS_CONFIG_3_cs_hold_MASK 0x00008000
-#define BCHP_EBI_CS_CONFIG_3_cs_hold_SHIFT 15
-#define BCHP_EBI_CS_CONFIG_3_cs_hold_DEFAULT 0x00000000
-
-/* EBI :: CS_CONFIG_3 :: split_cs [14:14] */
-#define BCHP_EBI_CS_CONFIG_3_split_cs_MASK 0x00004000
-#define BCHP_EBI_CS_CONFIG_3_split_cs_SHIFT 14
-#define BCHP_EBI_CS_CONFIG_3_split_cs_DEFAULT 0x00000000
-
-/* EBI :: CS_CONFIG_3 :: mask_en [13:13] */
-#define BCHP_EBI_CS_CONFIG_3_mask_en_MASK 0x00002000
-#define BCHP_EBI_CS_CONFIG_3_mask_en_SHIFT 13
-#define BCHP_EBI_CS_CONFIG_3_mask_en_DEFAULT 0x00000000
-
-/* EBI :: CS_CONFIG_3 :: ne_sample [12:12] */
-#define BCHP_EBI_CS_CONFIG_3_ne_sample_MASK 0x00001000
-#define BCHP_EBI_CS_CONFIG_3_ne_sample_SHIFT 12
-#define BCHP_EBI_CS_CONFIG_3_ne_sample_DEFAULT 0x00000000
-
-/* EBI :: CS_CONFIG_3 :: m68k [11:11] */
-#define BCHP_EBI_CS_CONFIG_3_m68k_MASK 0x00000800
-#define BCHP_EBI_CS_CONFIG_3_m68k_SHIFT 11
-#define BCHP_EBI_CS_CONFIG_3_m68k_DEFAULT 0x00000000
-
-/* EBI :: CS_CONFIG_3 :: le [10:10] */
-#define BCHP_EBI_CS_CONFIG_3_le_MASK 0x00000400
-#define BCHP_EBI_CS_CONFIG_3_le_SHIFT 10
-#define BCHP_EBI_CS_CONFIG_3_le_DEFAULT 0x00000000
-
-/* EBI :: CS_CONFIG_3 :: fast_read [09:09] */
-#define BCHP_EBI_CS_CONFIG_3_fast_read_MASK 0x00000200
-#define BCHP_EBI_CS_CONFIG_3_fast_read_SHIFT 9
-#define BCHP_EBI_CS_CONFIG_3_fast_read_DEFAULT 0x00000000
-#define BCHP_EBI_CS_CONFIG_3_fast_read_Normal 0
-#define BCHP_EBI_CS_CONFIG_3_fast_read_Fast_Read_Enable 1
-
-/* EBI :: CS_CONFIG_3 :: size_sel [08:08] */
-#define BCHP_EBI_CS_CONFIG_3_size_sel_MASK 0x00000100
-#define BCHP_EBI_CS_CONFIG_3_size_sel_SHIFT 8
-#define BCHP_EBI_CS_CONFIG_3_size_sel_DEFAULT 0x00000000
-
-/* EBI :: CS_CONFIG_3 :: sync [07:07] */
-#define BCHP_EBI_CS_CONFIG_3_sync_MASK 0x00000080
-#define BCHP_EBI_CS_CONFIG_3_sync_SHIFT 7
-#define BCHP_EBI_CS_CONFIG_3_sync_DEFAULT 0x00000000
-
-/* EBI :: CS_CONFIG_3 :: polarity [06:06] */
-#define BCHP_EBI_CS_CONFIG_3_polarity_MASK 0x00000040
-#define BCHP_EBI_CS_CONFIG_3_polarity_SHIFT 6
-#define BCHP_EBI_CS_CONFIG_3_polarity_DEFAULT 0x00000000
-
-/* EBI :: CS_CONFIG_3 :: we_ctl [05:05] */
-#define BCHP_EBI_CS_CONFIG_3_we_ctl_MASK 0x00000020
-#define BCHP_EBI_CS_CONFIG_3_we_ctl_SHIFT 5
-#define BCHP_EBI_CS_CONFIG_3_we_ctl_DEFAULT 0x00000000
-
-/* EBI :: CS_CONFIG_3 :: dest_size [04:04] */
-#define BCHP_EBI_CS_CONFIG_3_dest_size_MASK 0x00000010
-#define BCHP_EBI_CS_CONFIG_3_dest_size_SHIFT 4
-#define BCHP_EBI_CS_CONFIG_3_dest_size_DEFAULT 0x00000000
-
-/* EBI :: CS_CONFIG_3 :: ms_inh [03:03] */
-#define BCHP_EBI_CS_CONFIG_3_ms_inh_MASK 0x00000008
-#define BCHP_EBI_CS_CONFIG_3_ms_inh_SHIFT 3
-#define BCHP_EBI_CS_CONFIG_3_ms_inh_DEFAULT 0x00000000
-
-/* EBI :: CS_CONFIG_3 :: ls_inh [02:02] */
-#define BCHP_EBI_CS_CONFIG_3_ls_inh_MASK 0x00000004
-#define BCHP_EBI_CS_CONFIG_3_ls_inh_SHIFT 2
-#define BCHP_EBI_CS_CONFIG_3_ls_inh_DEFAULT 0x00000000
-
-/* EBI :: CS_CONFIG_3 :: bcachen [01:01] */
-#define BCHP_EBI_CS_CONFIG_3_bcachen_MASK 0x00000002
-#define BCHP_EBI_CS_CONFIG_3_bcachen_SHIFT 1
-#define BCHP_EBI_CS_CONFIG_3_bcachen_DEFAULT 0x00000000
-
-/* EBI :: CS_CONFIG_3 :: enable [00:00] */
-#define BCHP_EBI_CS_CONFIG_3_enable_MASK 0x00000001
-#define BCHP_EBI_CS_CONFIG_3_enable_SHIFT 0
-#define BCHP_EBI_CS_CONFIG_3_enable_DEFAULT 0x00000000
-
-/***************************************************************************
- *CS_BASE_HI_4 - Upper 8-bit of EBI CS Base 4 Register
- ***************************************************************************/
-/* EBI :: CS_BASE_HI_4 :: reserved0 [31:08] */
-#define BCHP_EBI_CS_BASE_HI_4_reserved0_MASK 0xffffff00
-#define BCHP_EBI_CS_BASE_HI_4_reserved0_SHIFT 8
-
-/* EBI :: CS_BASE_HI_4 :: base_addr_hi [07:00] */
-#define BCHP_EBI_CS_BASE_HI_4_base_addr_hi_MASK 0x000000ff
-#define BCHP_EBI_CS_BASE_HI_4_base_addr_hi_SHIFT 0
-#define BCHP_EBI_CS_BASE_HI_4_base_addr_hi_DEFAULT 0x00000000
-
-/***************************************************************************
- *CS_BASE_4 - Lower 32-bit of EBI CS Base 4 Register
- ***************************************************************************/
-/* EBI :: CS_BASE_4 :: base_addr [31:13] */
-#define BCHP_EBI_CS_BASE_4_base_addr_MASK 0xffffe000
-#define BCHP_EBI_CS_BASE_4_base_addr_SHIFT 13
-#define BCHP_EBI_CS_BASE_4_base_addr_DEFAULT 0x00000000
-
-/* EBI :: CS_BASE_4 :: reserved0 [12:04] */
-#define BCHP_EBI_CS_BASE_4_reserved0_MASK 0x00001ff0
-#define BCHP_EBI_CS_BASE_4_reserved0_SHIFT 4
-
-/* EBI :: CS_BASE_4 :: size [03:00] */
-#define BCHP_EBI_CS_BASE_4_size_MASK 0x0000000f
-#define BCHP_EBI_CS_BASE_4_size_SHIFT 0
-#define BCHP_EBI_CS_BASE_4_size_DEFAULT 0x00000000
-#define BCHP_EBI_CS_BASE_4_size_SIZE_8KB 0
-#define BCHP_EBI_CS_BASE_4_size_SIZE_16KB 1
-#define BCHP_EBI_CS_BASE_4_size_SIZE_32KB 2
-#define BCHP_EBI_CS_BASE_4_size_SIZE_64KB 3
-#define BCHP_EBI_CS_BASE_4_size_SIZE_128KB 4
-#define BCHP_EBI_CS_BASE_4_size_SIZE_256KB 5
-#define BCHP_EBI_CS_BASE_4_size_SIZE_512KB 6
-#define BCHP_EBI_CS_BASE_4_size_SIZE_1MB 7
-#define BCHP_EBI_CS_BASE_4_size_SIZE_2MB 8
-#define BCHP_EBI_CS_BASE_4_size_SIZE_4MB 9
-#define BCHP_EBI_CS_BASE_4_size_SIZE_8MB 10
-#define BCHP_EBI_CS_BASE_4_size_SIZE_16MB 11
-#define BCHP_EBI_CS_BASE_4_size_SIZE_32MB 12
-#define BCHP_EBI_CS_BASE_4_size_SIZE_64MB 13
-#define BCHP_EBI_CS_BASE_4_size_SIZE_128MB 14
-#define BCHP_EBI_CS_BASE_4_size_SIZE_256MB 15
-
-/***************************************************************************
- *CS_CONFIG_4 - EBI CS Config 4 Register
- ***************************************************************************/
-/* EBI :: CS_CONFIG_4 :: mem_io [31:31] */
-#define BCHP_EBI_CS_CONFIG_4_mem_io_MASK 0x80000000
-#define BCHP_EBI_CS_CONFIG_4_mem_io_SHIFT 31
-#define BCHP_EBI_CS_CONFIG_4_mem_io_DEFAULT 0x00000000
-
-/* EBI :: CS_CONFIG_4 :: ta_wait [30:30] */
-#define BCHP_EBI_CS_CONFIG_4_ta_wait_MASK 0x40000000
-#define BCHP_EBI_CS_CONFIG_4_ta_wait_SHIFT 30
-#define BCHP_EBI_CS_CONFIG_4_ta_wait_DEFAULT 0x00000000
-
-/* EBI :: CS_CONFIG_4 :: wp [29:29] */
-#define BCHP_EBI_CS_CONFIG_4_wp_MASK 0x20000000
-#define BCHP_EBI_CS_CONFIG_4_wp_SHIFT 29
-#define BCHP_EBI_CS_CONFIG_4_wp_DEFAULT 0x00000000
-
-/* EBI :: CS_CONFIG_4 :: wait_count [28:24] */
-#define BCHP_EBI_CS_CONFIG_4_wait_count_MASK 0x1f000000
-#define BCHP_EBI_CS_CONFIG_4_wait_count_SHIFT 24
-#define BCHP_EBI_CS_CONFIG_4_wait_count_DEFAULT 0x00000007
-
-/* EBI :: CS_CONFIG_4 :: t_hold [23:20] */
-#define BCHP_EBI_CS_CONFIG_4_t_hold_MASK 0x00f00000
-#define BCHP_EBI_CS_CONFIG_4_t_hold_SHIFT 20
-#define BCHP_EBI_CS_CONFIG_4_t_hold_DEFAULT 0x00000000
-
-/* EBI :: CS_CONFIG_4 :: t_setup [19:16] */
-#define BCHP_EBI_CS_CONFIG_4_t_setup_MASK 0x000f0000
-#define BCHP_EBI_CS_CONFIG_4_t_setup_SHIFT 16
-#define BCHP_EBI_CS_CONFIG_4_t_setup_DEFAULT 0x00000000
-
-/* EBI :: CS_CONFIG_4 :: cs_hold [15:15] */
-#define BCHP_EBI_CS_CONFIG_4_cs_hold_MASK 0x00008000
-#define BCHP_EBI_CS_CONFIG_4_cs_hold_SHIFT 15
-#define BCHP_EBI_CS_CONFIG_4_cs_hold_DEFAULT 0x00000000
-
-/* EBI :: CS_CONFIG_4 :: split_cs [14:14] */
-#define BCHP_EBI_CS_CONFIG_4_split_cs_MASK 0x00004000
-#define BCHP_EBI_CS_CONFIG_4_split_cs_SHIFT 14
-#define BCHP_EBI_CS_CONFIG_4_split_cs_DEFAULT 0x00000000
-
-/* EBI :: CS_CONFIG_4 :: mask_en [13:13] */
-#define BCHP_EBI_CS_CONFIG_4_mask_en_MASK 0x00002000
-#define BCHP_EBI_CS_CONFIG_4_mask_en_SHIFT 13
-#define BCHP_EBI_CS_CONFIG_4_mask_en_DEFAULT 0x00000000
-
-/* EBI :: CS_CONFIG_4 :: ne_sample [12:12] */
-#define BCHP_EBI_CS_CONFIG_4_ne_sample_MASK 0x00001000
-#define BCHP_EBI_CS_CONFIG_4_ne_sample_SHIFT 12
-#define BCHP_EBI_CS_CONFIG_4_ne_sample_DEFAULT 0x00000000
-
-/* EBI :: CS_CONFIG_4 :: m68k [11:11] */
-#define BCHP_EBI_CS_CONFIG_4_m68k_MASK 0x00000800
-#define BCHP_EBI_CS_CONFIG_4_m68k_SHIFT 11
-#define BCHP_EBI_CS_CONFIG_4_m68k_DEFAULT 0x00000000
-
-/* EBI :: CS_CONFIG_4 :: le [10:10] */
-#define BCHP_EBI_CS_CONFIG_4_le_MASK 0x00000400
-#define BCHP_EBI_CS_CONFIG_4_le_SHIFT 10
-#define BCHP_EBI_CS_CONFIG_4_le_DEFAULT 0x00000000
-
-/* EBI :: CS_CONFIG_4 :: fast_read [09:09] */
-#define BCHP_EBI_CS_CONFIG_4_fast_read_MASK 0x00000200
-#define BCHP_EBI_CS_CONFIG_4_fast_read_SHIFT 9
-#define BCHP_EBI_CS_CONFIG_4_fast_read_DEFAULT 0x00000000
-#define BCHP_EBI_CS_CONFIG_4_fast_read_Normal 0
-#define BCHP_EBI_CS_CONFIG_4_fast_read_Fast_Read_Enable 1
-
-/* EBI :: CS_CONFIG_4 :: size_sel [08:08] */
-#define BCHP_EBI_CS_CONFIG_4_size_sel_MASK 0x00000100
-#define BCHP_EBI_CS_CONFIG_4_size_sel_SHIFT 8
-#define BCHP_EBI_CS_CONFIG_4_size_sel_DEFAULT 0x00000000
-
-/* EBI :: CS_CONFIG_4 :: sync [07:07] */
-#define BCHP_EBI_CS_CONFIG_4_sync_MASK 0x00000080
-#define BCHP_EBI_CS_CONFIG_4_sync_SHIFT 7
-#define BCHP_EBI_CS_CONFIG_4_sync_DEFAULT 0x00000000
-
-/* EBI :: CS_CONFIG_4 :: polarity [06:06] */
-#define BCHP_EBI_CS_CONFIG_4_polarity_MASK 0x00000040
-#define BCHP_EBI_CS_CONFIG_4_polarity_SHIFT 6
-#define BCHP_EBI_CS_CONFIG_4_polarity_DEFAULT 0x00000000
-
-/* EBI :: CS_CONFIG_4 :: we_ctl [05:05] */
-#define BCHP_EBI_CS_CONFIG_4_we_ctl_MASK 0x00000020
-#define BCHP_EBI_CS_CONFIG_4_we_ctl_SHIFT 5
-#define BCHP_EBI_CS_CONFIG_4_we_ctl_DEFAULT 0x00000000
-
-/* EBI :: CS_CONFIG_4 :: dest_size [04:04] */
-#define BCHP_EBI_CS_CONFIG_4_dest_size_MASK 0x00000010
-#define BCHP_EBI_CS_CONFIG_4_dest_size_SHIFT 4
-#define BCHP_EBI_CS_CONFIG_4_dest_size_DEFAULT 0x00000000
-
-/* EBI :: CS_CONFIG_4 :: ms_inh [03:03] */
-#define BCHP_EBI_CS_CONFIG_4_ms_inh_MASK 0x00000008
-#define BCHP_EBI_CS_CONFIG_4_ms_inh_SHIFT 3
-#define BCHP_EBI_CS_CONFIG_4_ms_inh_DEFAULT 0x00000000
-
-/* EBI :: CS_CONFIG_4 :: ls_inh [02:02] */
-#define BCHP_EBI_CS_CONFIG_4_ls_inh_MASK 0x00000004
-#define BCHP_EBI_CS_CONFIG_4_ls_inh_SHIFT 2
-#define BCHP_EBI_CS_CONFIG_4_ls_inh_DEFAULT 0x00000000
-
-/* EBI :: CS_CONFIG_4 :: bcachen [01:01] */
-#define BCHP_EBI_CS_CONFIG_4_bcachen_MASK 0x00000002
-#define BCHP_EBI_CS_CONFIG_4_bcachen_SHIFT 1
-#define BCHP_EBI_CS_CONFIG_4_bcachen_DEFAULT 0x00000000
-
-/* EBI :: CS_CONFIG_4 :: enable [00:00] */
-#define BCHP_EBI_CS_CONFIG_4_enable_MASK 0x00000001
-#define BCHP_EBI_CS_CONFIG_4_enable_SHIFT 0
-#define BCHP_EBI_CS_CONFIG_4_enable_DEFAULT 0x00000000
-
-/***************************************************************************
- *CS_BASE_HI_5 - Upper 8-bit of EBI CS Base 5 Register
- ***************************************************************************/
-/* EBI :: CS_BASE_HI_5 :: reserved0 [31:08] */
-#define BCHP_EBI_CS_BASE_HI_5_reserved0_MASK 0xffffff00
-#define BCHP_EBI_CS_BASE_HI_5_reserved0_SHIFT 8
-
-/* EBI :: CS_BASE_HI_5 :: base_addr_hi [07:00] */
-#define BCHP_EBI_CS_BASE_HI_5_base_addr_hi_MASK 0x000000ff
-#define BCHP_EBI_CS_BASE_HI_5_base_addr_hi_SHIFT 0
-#define BCHP_EBI_CS_BASE_HI_5_base_addr_hi_DEFAULT 0x00000000
-
-/***************************************************************************
- *CS_BASE_5 - Lower 32-bit of EBI CS Base 5 Register
- ***************************************************************************/
-/* EBI :: CS_BASE_5 :: base_addr [31:13] */
-#define BCHP_EBI_CS_BASE_5_base_addr_MASK 0xffffe000
-#define BCHP_EBI_CS_BASE_5_base_addr_SHIFT 13
-#define BCHP_EBI_CS_BASE_5_base_addr_DEFAULT 0x00000000
-
-/* EBI :: CS_BASE_5 :: reserved0 [12:04] */
-#define BCHP_EBI_CS_BASE_5_reserved0_MASK 0x00001ff0
-#define BCHP_EBI_CS_BASE_5_reserved0_SHIFT 4
-
-/* EBI :: CS_BASE_5 :: size [03:00] */
-#define BCHP_EBI_CS_BASE_5_size_MASK 0x0000000f
-#define BCHP_EBI_CS_BASE_5_size_SHIFT 0
-#define BCHP_EBI_CS_BASE_5_size_DEFAULT 0x00000000
-#define BCHP_EBI_CS_BASE_5_size_SIZE_8KB 0
-#define BCHP_EBI_CS_BASE_5_size_SIZE_16KB 1
-#define BCHP_EBI_CS_BASE_5_size_SIZE_32KB 2
-#define BCHP_EBI_CS_BASE_5_size_SIZE_64KB 3
-#define BCHP_EBI_CS_BASE_5_size_SIZE_128KB 4
-#define BCHP_EBI_CS_BASE_5_size_SIZE_256KB 5
-#define BCHP_EBI_CS_BASE_5_size_SIZE_512KB 6
-#define BCHP_EBI_CS_BASE_5_size_SIZE_1MB 7
-#define BCHP_EBI_CS_BASE_5_size_SIZE_2MB 8
-#define BCHP_EBI_CS_BASE_5_size_SIZE_4MB 9
-#define BCHP_EBI_CS_BASE_5_size_SIZE_8MB 10
-#define BCHP_EBI_CS_BASE_5_size_SIZE_16MB 11
-#define BCHP_EBI_CS_BASE_5_size_SIZE_32MB 12
-#define BCHP_EBI_CS_BASE_5_size_SIZE_64MB 13
-#define BCHP_EBI_CS_BASE_5_size_SIZE_128MB 14
-#define BCHP_EBI_CS_BASE_5_size_SIZE_256MB 15
-
-/***************************************************************************
- *CS_CONFIG_5 - EBI CS Config 5 Register
- ***************************************************************************/
-/* EBI :: CS_CONFIG_5 :: mem_io [31:31] */
-#define BCHP_EBI_CS_CONFIG_5_mem_io_MASK 0x80000000
-#define BCHP_EBI_CS_CONFIG_5_mem_io_SHIFT 31
-#define BCHP_EBI_CS_CONFIG_5_mem_io_DEFAULT 0x00000000
-
-/* EBI :: CS_CONFIG_5 :: ta_wait [30:30] */
-#define BCHP_EBI_CS_CONFIG_5_ta_wait_MASK 0x40000000
-#define BCHP_EBI_CS_CONFIG_5_ta_wait_SHIFT 30
-#define BCHP_EBI_CS_CONFIG_5_ta_wait_DEFAULT 0x00000000
-
-/* EBI :: CS_CONFIG_5 :: wp [29:29] */
-#define BCHP_EBI_CS_CONFIG_5_wp_MASK 0x20000000
-#define BCHP_EBI_CS_CONFIG_5_wp_SHIFT 29
-#define BCHP_EBI_CS_CONFIG_5_wp_DEFAULT 0x00000000
-
-/* EBI :: CS_CONFIG_5 :: wait_count [28:24] */
-#define BCHP_EBI_CS_CONFIG_5_wait_count_MASK 0x1f000000
-#define BCHP_EBI_CS_CONFIG_5_wait_count_SHIFT 24
-#define BCHP_EBI_CS_CONFIG_5_wait_count_DEFAULT 0x00000007
-
-/* EBI :: CS_CONFIG_5 :: t_hold [23:20] */
-#define BCHP_EBI_CS_CONFIG_5_t_hold_MASK 0x00f00000
-#define BCHP_EBI_CS_CONFIG_5_t_hold_SHIFT 20
-#define BCHP_EBI_CS_CONFIG_5_t_hold_DEFAULT 0x00000000
-
-/* EBI :: CS_CONFIG_5 :: t_setup [19:16] */
-#define BCHP_EBI_CS_CONFIG_5_t_setup_MASK 0x000f0000
-#define BCHP_EBI_CS_CONFIG_5_t_setup_SHIFT 16
-#define BCHP_EBI_CS_CONFIG_5_t_setup_DEFAULT 0x00000000
-
-/* EBI :: CS_CONFIG_5 :: cs_hold [15:15] */
-#define BCHP_EBI_CS_CONFIG_5_cs_hold_MASK 0x00008000
-#define BCHP_EBI_CS_CONFIG_5_cs_hold_SHIFT 15
-#define BCHP_EBI_CS_CONFIG_5_cs_hold_DEFAULT 0x00000000
-
-/* EBI :: CS_CONFIG_5 :: split_cs [14:14] */
-#define BCHP_EBI_CS_CONFIG_5_split_cs_MASK 0x00004000
-#define BCHP_EBI_CS_CONFIG_5_split_cs_SHIFT 14
-#define BCHP_EBI_CS_CONFIG_5_split_cs_DEFAULT 0x00000000
-
-/* EBI :: CS_CONFIG_5 :: mask_en [13:13] */
-#define BCHP_EBI_CS_CONFIG_5_mask_en_MASK 0x00002000
-#define BCHP_EBI_CS_CONFIG_5_mask_en_SHIFT 13
-#define BCHP_EBI_CS_CONFIG_5_mask_en_DEFAULT 0x00000000
-
-/* EBI :: CS_CONFIG_5 :: ne_sample [12:12] */
-#define BCHP_EBI_CS_CONFIG_5_ne_sample_MASK 0x00001000
-#define BCHP_EBI_CS_CONFIG_5_ne_sample_SHIFT 12
-#define BCHP_EBI_CS_CONFIG_5_ne_sample_DEFAULT 0x00000000
-
-/* EBI :: CS_CONFIG_5 :: m68k [11:11] */
-#define BCHP_EBI_CS_CONFIG_5_m68k_MASK 0x00000800
-#define BCHP_EBI_CS_CONFIG_5_m68k_SHIFT 11
-#define BCHP_EBI_CS_CONFIG_5_m68k_DEFAULT 0x00000000
-
-/* EBI :: CS_CONFIG_5 :: le [10:10] */
-#define BCHP_EBI_CS_CONFIG_5_le_MASK 0x00000400
-#define BCHP_EBI_CS_CONFIG_5_le_SHIFT 10
-#define BCHP_EBI_CS_CONFIG_5_le_DEFAULT 0x00000000
-
-/* EBI :: CS_CONFIG_5 :: fast_read [09:09] */
-#define BCHP_EBI_CS_CONFIG_5_fast_read_MASK 0x00000200
-#define BCHP_EBI_CS_CONFIG_5_fast_read_SHIFT 9
-#define BCHP_EBI_CS_CONFIG_5_fast_read_DEFAULT 0x00000000
-#define BCHP_EBI_CS_CONFIG_5_fast_read_Normal 0
-#define BCHP_EBI_CS_CONFIG_5_fast_read_Fast_Read_Enable 1
-
-/* EBI :: CS_CONFIG_5 :: size_sel [08:08] */
-#define BCHP_EBI_CS_CONFIG_5_size_sel_MASK 0x00000100
-#define BCHP_EBI_CS_CONFIG_5_size_sel_SHIFT 8
-#define BCHP_EBI_CS_CONFIG_5_size_sel_DEFAULT 0x00000000
-
-/* EBI :: CS_CONFIG_5 :: sync [07:07] */
-#define BCHP_EBI_CS_CONFIG_5_sync_MASK 0x00000080
-#define BCHP_EBI_CS_CONFIG_5_sync_SHIFT 7
-#define BCHP_EBI_CS_CONFIG_5_sync_DEFAULT 0x00000000
-
-/* EBI :: CS_CONFIG_5 :: polarity [06:06] */
-#define BCHP_EBI_CS_CONFIG_5_polarity_MASK 0x00000040
-#define BCHP_EBI_CS_CONFIG_5_polarity_SHIFT 6
-#define BCHP_EBI_CS_CONFIG_5_polarity_DEFAULT 0x00000000
-
-/* EBI :: CS_CONFIG_5 :: we_ctl [05:05] */
-#define BCHP_EBI_CS_CONFIG_5_we_ctl_MASK 0x00000020
-#define BCHP_EBI_CS_CONFIG_5_we_ctl_SHIFT 5
-#define BCHP_EBI_CS_CONFIG_5_we_ctl_DEFAULT 0x00000000
-
-/* EBI :: CS_CONFIG_5 :: dest_size [04:04] */
-#define BCHP_EBI_CS_CONFIG_5_dest_size_MASK 0x00000010
-#define BCHP_EBI_CS_CONFIG_5_dest_size_SHIFT 4
-#define BCHP_EBI_CS_CONFIG_5_dest_size_DEFAULT 0x00000000
-
-/* EBI :: CS_CONFIG_5 :: ms_inh [03:03] */
-#define BCHP_EBI_CS_CONFIG_5_ms_inh_MASK 0x00000008
-#define BCHP_EBI_CS_CONFIG_5_ms_inh_SHIFT 3
-#define BCHP_EBI_CS_CONFIG_5_ms_inh_DEFAULT 0x00000000
-
-/* EBI :: CS_CONFIG_5 :: ls_inh [02:02] */
-#define BCHP_EBI_CS_CONFIG_5_ls_inh_MASK 0x00000004
-#define BCHP_EBI_CS_CONFIG_5_ls_inh_SHIFT 2
-#define BCHP_EBI_CS_CONFIG_5_ls_inh_DEFAULT 0x00000000
-
-/* EBI :: CS_CONFIG_5 :: bcachen [01:01] */
-#define BCHP_EBI_CS_CONFIG_5_bcachen_MASK 0x00000002
-#define BCHP_EBI_CS_CONFIG_5_bcachen_SHIFT 1
-#define BCHP_EBI_CS_CONFIG_5_bcachen_DEFAULT 0x00000000
-
-/* EBI :: CS_CONFIG_5 :: enable [00:00] */
-#define BCHP_EBI_CS_CONFIG_5_enable_MASK 0x00000001
-#define BCHP_EBI_CS_CONFIG_5_enable_SHIFT 0
-#define BCHP_EBI_CS_CONFIG_5_enable_DEFAULT 0x00000000
-
-/***************************************************************************
- *CS_BASE_HI_6 - Upper 8-bit of EBI CS Base 6 Register
- ***************************************************************************/
-/* EBI :: CS_BASE_HI_6 :: reserved0 [31:08] */
-#define BCHP_EBI_CS_BASE_HI_6_reserved0_MASK 0xffffff00
-#define BCHP_EBI_CS_BASE_HI_6_reserved0_SHIFT 8
-
-/* EBI :: CS_BASE_HI_6 :: base_addr_hi [07:00] */
-#define BCHP_EBI_CS_BASE_HI_6_base_addr_hi_MASK 0x000000ff
-#define BCHP_EBI_CS_BASE_HI_6_base_addr_hi_SHIFT 0
-#define BCHP_EBI_CS_BASE_HI_6_base_addr_hi_DEFAULT 0x00000000
-
-/***************************************************************************
- *CS_BASE_6 - Lower 32-bit of EBI CS Base 6 Register
- ***************************************************************************/
-/* EBI :: CS_BASE_6 :: base_addr [31:13] */
-#define BCHP_EBI_CS_BASE_6_base_addr_MASK 0xffffe000
-#define BCHP_EBI_CS_BASE_6_base_addr_SHIFT 13
-#define BCHP_EBI_CS_BASE_6_base_addr_DEFAULT 0x00000000
-
-/* EBI :: CS_BASE_6 :: reserved0 [12:04] */
-#define BCHP_EBI_CS_BASE_6_reserved0_MASK 0x00001ff0
-#define BCHP_EBI_CS_BASE_6_reserved0_SHIFT 4
-
-/* EBI :: CS_BASE_6 :: size [03:00] */
-#define BCHP_EBI_CS_BASE_6_size_MASK 0x0000000f
-#define BCHP_EBI_CS_BASE_6_size_SHIFT 0
-#define BCHP_EBI_CS_BASE_6_size_DEFAULT 0x00000000
-#define BCHP_EBI_CS_BASE_6_size_SIZE_8KB 0
-#define BCHP_EBI_CS_BASE_6_size_SIZE_16KB 1
-#define BCHP_EBI_CS_BASE_6_size_SIZE_32KB 2
-#define BCHP_EBI_CS_BASE_6_size_SIZE_64KB 3
-#define BCHP_EBI_CS_BASE_6_size_SIZE_128KB 4
-#define BCHP_EBI_CS_BASE_6_size_SIZE_256KB 5
-#define BCHP_EBI_CS_BASE_6_size_SIZE_512KB 6
-#define BCHP_EBI_CS_BASE_6_size_SIZE_1MB 7
-#define BCHP_EBI_CS_BASE_6_size_SIZE_2MB 8
-#define BCHP_EBI_CS_BASE_6_size_SIZE_4MB 9
-#define BCHP_EBI_CS_BASE_6_size_SIZE_8MB 10
-#define BCHP_EBI_CS_BASE_6_size_SIZE_16MB 11
-#define BCHP_EBI_CS_BASE_6_size_SIZE_32MB 12
-#define BCHP_EBI_CS_BASE_6_size_SIZE_64MB 13
-#define BCHP_EBI_CS_BASE_6_size_SIZE_128MB 14
-#define BCHP_EBI_CS_BASE_6_size_SIZE_256MB 15
-
-/***************************************************************************
- *CS_CONFIG_6 - EBI CS Config 6 Register
- ***************************************************************************/
-/* EBI :: CS_CONFIG_6 :: mem_io [31:31] */
-#define BCHP_EBI_CS_CONFIG_6_mem_io_MASK 0x80000000
-#define BCHP_EBI_CS_CONFIG_6_mem_io_SHIFT 31
-#define BCHP_EBI_CS_CONFIG_6_mem_io_DEFAULT 0x00000000
-
-/* EBI :: CS_CONFIG_6 :: ta_wait [30:30] */
-#define BCHP_EBI_CS_CONFIG_6_ta_wait_MASK 0x40000000
-#define BCHP_EBI_CS_CONFIG_6_ta_wait_SHIFT 30
-#define BCHP_EBI_CS_CONFIG_6_ta_wait_DEFAULT 0x00000000
-
-/* EBI :: CS_CONFIG_6 :: wp [29:29] */
-#define BCHP_EBI_CS_CONFIG_6_wp_MASK 0x20000000
-#define BCHP_EBI_CS_CONFIG_6_wp_SHIFT 29
-#define BCHP_EBI_CS_CONFIG_6_wp_DEFAULT 0x00000000
-
-/* EBI :: CS_CONFIG_6 :: wait_count [28:24] */
-#define BCHP_EBI_CS_CONFIG_6_wait_count_MASK 0x1f000000
-#define BCHP_EBI_CS_CONFIG_6_wait_count_SHIFT 24
-#define BCHP_EBI_CS_CONFIG_6_wait_count_DEFAULT 0x00000007
-
-/* EBI :: CS_CONFIG_6 :: t_hold [23:20] */
-#define BCHP_EBI_CS_CONFIG_6_t_hold_MASK 0x00f00000
-#define BCHP_EBI_CS_CONFIG_6_t_hold_SHIFT 20
-#define BCHP_EBI_CS_CONFIG_6_t_hold_DEFAULT 0x00000000
-
-/* EBI :: CS_CONFIG_6 :: t_setup [19:16] */
-#define BCHP_EBI_CS_CONFIG_6_t_setup_MASK 0x000f0000
-#define BCHP_EBI_CS_CONFIG_6_t_setup_SHIFT 16
-#define BCHP_EBI_CS_CONFIG_6_t_setup_DEFAULT 0x00000000
-
-/* EBI :: CS_CONFIG_6 :: cs_hold [15:15] */
-#define BCHP_EBI_CS_CONFIG_6_cs_hold_MASK 0x00008000
-#define BCHP_EBI_CS_CONFIG_6_cs_hold_SHIFT 15
-#define BCHP_EBI_CS_CONFIG_6_cs_hold_DEFAULT 0x00000000
-
-/* EBI :: CS_CONFIG_6 :: split_cs [14:14] */
-#define BCHP_EBI_CS_CONFIG_6_split_cs_MASK 0x00004000
-#define BCHP_EBI_CS_CONFIG_6_split_cs_SHIFT 14
-#define BCHP_EBI_CS_CONFIG_6_split_cs_DEFAULT 0x00000000
-
-/* EBI :: CS_CONFIG_6 :: mask_en [13:13] */
-#define BCHP_EBI_CS_CONFIG_6_mask_en_MASK 0x00002000
-#define BCHP_EBI_CS_CONFIG_6_mask_en_SHIFT 13
-#define BCHP_EBI_CS_CONFIG_6_mask_en_DEFAULT 0x00000000
-
-/* EBI :: CS_CONFIG_6 :: ne_sample [12:12] */
-#define BCHP_EBI_CS_CONFIG_6_ne_sample_MASK 0x00001000
-#define BCHP_EBI_CS_CONFIG_6_ne_sample_SHIFT 12
-#define BCHP_EBI_CS_CONFIG_6_ne_sample_DEFAULT 0x00000000
-
-/* EBI :: CS_CONFIG_6 :: m68k [11:11] */
-#define BCHP_EBI_CS_CONFIG_6_m68k_MASK 0x00000800
-#define BCHP_EBI_CS_CONFIG_6_m68k_SHIFT 11
-#define BCHP_EBI_CS_CONFIG_6_m68k_DEFAULT 0x00000000
-
-/* EBI :: CS_CONFIG_6 :: le [10:10] */
-#define BCHP_EBI_CS_CONFIG_6_le_MASK 0x00000400
-#define BCHP_EBI_CS_CONFIG_6_le_SHIFT 10
-#define BCHP_EBI_CS_CONFIG_6_le_DEFAULT 0x00000000
-
-/* EBI :: CS_CONFIG_6 :: fast_read [09:09] */
-#define BCHP_EBI_CS_CONFIG_6_fast_read_MASK 0x00000200
-#define BCHP_EBI_CS_CONFIG_6_fast_read_SHIFT 9
-#define BCHP_EBI_CS_CONFIG_6_fast_read_DEFAULT 0x00000000
-#define BCHP_EBI_CS_CONFIG_6_fast_read_Normal 0
-#define BCHP_EBI_CS_CONFIG_6_fast_read_Fast_Read_Enable 1
-
-/* EBI :: CS_CONFIG_6 :: size_sel [08:08] */
-#define BCHP_EBI_CS_CONFIG_6_size_sel_MASK 0x00000100
-#define BCHP_EBI_CS_CONFIG_6_size_sel_SHIFT 8
-#define BCHP_EBI_CS_CONFIG_6_size_sel_DEFAULT 0x00000000
-
-/* EBI :: CS_CONFIG_6 :: sync [07:07] */
-#define BCHP_EBI_CS_CONFIG_6_sync_MASK 0x00000080
-#define BCHP_EBI_CS_CONFIG_6_sync_SHIFT 7
-#define BCHP_EBI_CS_CONFIG_6_sync_DEFAULT 0x00000000
-
-/* EBI :: CS_CONFIG_6 :: polarity [06:06] */
-#define BCHP_EBI_CS_CONFIG_6_polarity_MASK 0x00000040
-#define BCHP_EBI_CS_CONFIG_6_polarity_SHIFT 6
-#define BCHP_EBI_CS_CONFIG_6_polarity_DEFAULT 0x00000000
-
-/* EBI :: CS_CONFIG_6 :: we_ctl [05:05] */
-#define BCHP_EBI_CS_CONFIG_6_we_ctl_MASK 0x00000020
-#define BCHP_EBI_CS_CONFIG_6_we_ctl_SHIFT 5
-#define BCHP_EBI_CS_CONFIG_6_we_ctl_DEFAULT 0x00000000
-
-/* EBI :: CS_CONFIG_6 :: dest_size [04:04] */
-#define BCHP_EBI_CS_CONFIG_6_dest_size_MASK 0x00000010
-#define BCHP_EBI_CS_CONFIG_6_dest_size_SHIFT 4
-#define BCHP_EBI_CS_CONFIG_6_dest_size_DEFAULT 0x00000000
-
-/* EBI :: CS_CONFIG_6 :: ms_inh [03:03] */
-#define BCHP_EBI_CS_CONFIG_6_ms_inh_MASK 0x00000008
-#define BCHP_EBI_CS_CONFIG_6_ms_inh_SHIFT 3
-#define BCHP_EBI_CS_CONFIG_6_ms_inh_DEFAULT 0x00000000
-
-/* EBI :: CS_CONFIG_6 :: ls_inh [02:02] */
-#define BCHP_EBI_CS_CONFIG_6_ls_inh_MASK 0x00000004
-#define BCHP_EBI_CS_CONFIG_6_ls_inh_SHIFT 2
-#define BCHP_EBI_CS_CONFIG_6_ls_inh_DEFAULT 0x00000000
-
-/* EBI :: CS_CONFIG_6 :: bcachen [01:01] */
-#define BCHP_EBI_CS_CONFIG_6_bcachen_MASK 0x00000002
-#define BCHP_EBI_CS_CONFIG_6_bcachen_SHIFT 1
-#define BCHP_EBI_CS_CONFIG_6_bcachen_DEFAULT 0x00000000
-
-/* EBI :: CS_CONFIG_6 :: enable [00:00] */
-#define BCHP_EBI_CS_CONFIG_6_enable_MASK 0x00000001
-#define BCHP_EBI_CS_CONFIG_6_enable_SHIFT 0
-#define BCHP_EBI_CS_CONFIG_6_enable_DEFAULT 0x00000000
-
-/***************************************************************************
- *BURST_CFG_0 - EBI Synchronous Intel StrataFlash Burst Configure Register
- ***************************************************************************/
-/* EBI :: BURST_CFG_0 :: prefetch_enable [31:31] */
-#define BCHP_EBI_BURST_CFG_0_prefetch_enable_MASK 0x80000000
-#define BCHP_EBI_BURST_CFG_0_prefetch_enable_SHIFT 31
-#define BCHP_EBI_BURST_CFG_0_prefetch_enable_DEFAULT 0x00000000
-
-/* EBI :: BURST_CFG_0 :: page_enable [30:30] */
-#define BCHP_EBI_BURST_CFG_0_page_enable_MASK 0x40000000
-#define BCHP_EBI_BURST_CFG_0_page_enable_SHIFT 30
-#define BCHP_EBI_BURST_CFG_0_page_enable_DEFAULT 0x00000000
-
-/* EBI :: BURST_CFG_0 :: pfetch_abort_enable [29:29] */
-#define BCHP_EBI_BURST_CFG_0_pfetch_abort_enable_MASK 0x20000000
-#define BCHP_EBI_BURST_CFG_0_pfetch_abort_enable_SHIFT 29
-#define BCHP_EBI_BURST_CFG_0_pfetch_abort_enable_DEFAULT 0x00000000
-
-/* EBI :: BURST_CFG_0 :: page_latch_enable [28:28] */
-#define BCHP_EBI_BURST_CFG_0_page_latch_enable_MASK 0x10000000
-#define BCHP_EBI_BURST_CFG_0_page_latch_enable_SHIFT 28
-#define BCHP_EBI_BURST_CFG_0_page_latch_enable_DEFAULT 0x00000000
-
-/* EBI :: BURST_CFG_0 :: pfetch_wrap_enable [27:27] */
-#define BCHP_EBI_BURST_CFG_0_pfetch_wrap_enable_MASK 0x08000000
-#define BCHP_EBI_BURST_CFG_0_pfetch_wrap_enable_SHIFT 27
-#define BCHP_EBI_BURST_CFG_0_pfetch_wrap_enable_DEFAULT 0x00000000
-
-/* EBI :: BURST_CFG_0 :: reserved0 [26:24] */
-#define BCHP_EBI_BURST_CFG_0_reserved0_MASK 0x07000000
-#define BCHP_EBI_BURST_CFG_0_reserved0_SHIFT 24
-
-/* EBI :: BURST_CFG_0 :: prefetch_size [23:22] */
-#define BCHP_EBI_BURST_CFG_0_prefetch_size_MASK 0x00c00000
-#define BCHP_EBI_BURST_CFG_0_prefetch_size_SHIFT 22
-#define BCHP_EBI_BURST_CFG_0_prefetch_size_DEFAULT 0x00000000
-#define BCHP_EBI_BURST_CFG_0_prefetch_size_SIZE_4_BYTES 0
-#define BCHP_EBI_BURST_CFG_0_prefetch_size_SIZE_8_BYTES 1
-#define BCHP_EBI_BURST_CFG_0_prefetch_size_SIZE_16_BYTES 2
-#define BCHP_EBI_BURST_CFG_0_prefetch_size_SIZE_32_BYTES 3
-
-/* EBI :: BURST_CFG_0 :: page_size [21:20] */
-#define BCHP_EBI_BURST_CFG_0_page_size_MASK 0x00300000
-#define BCHP_EBI_BURST_CFG_0_page_size_SHIFT 20
-#define BCHP_EBI_BURST_CFG_0_page_size_DEFAULT 0x00000000
-#define BCHP_EBI_BURST_CFG_0_page_size_SIZE_4_BYTES 0
-#define BCHP_EBI_BURST_CFG_0_page_size_SIZE_8_BYTES 1
-#define BCHP_EBI_BURST_CFG_0_page_size_SIZE_16_BYTES 2
-#define BCHP_EBI_BURST_CFG_0_page_size_SIZE_32_BYTES 3
-
-/* EBI :: BURST_CFG_0 :: page_wait_count [19:16] */
-#define BCHP_EBI_BURST_CFG_0_page_wait_count_MASK 0x000f0000
-#define BCHP_EBI_BURST_CFG_0_page_wait_count_SHIFT 16
-#define BCHP_EBI_BURST_CFG_0_page_wait_count_DEFAULT 0x00000001
-
-/* EBI :: BURST_CFG_0 :: burst_cyc_disable [15:15] */
-#define BCHP_EBI_BURST_CFG_0_burst_cyc_disable_MASK 0x00008000
-#define BCHP_EBI_BURST_CFG_0_burst_cyc_disable_SHIFT 15
-#define BCHP_EBI_BURST_CFG_0_burst_cyc_disable_DEFAULT 0x00000001
-
-/* EBI :: BURST_CFG_0 :: reserved1 [14:08] */
-#define BCHP_EBI_BURST_CFG_0_reserved1_MASK 0x00007f00
-#define BCHP_EBI_BURST_CFG_0_reserved1_SHIFT 8
-
-/* EBI :: BURST_CFG_0 :: burst_latency [07:04] */
-#define BCHP_EBI_BURST_CFG_0_burst_latency_MASK 0x000000f0
-#define BCHP_EBI_BURST_CFG_0_burst_latency_SHIFT 4
-#define BCHP_EBI_BURST_CFG_0_burst_latency_DEFAULT 0x00000000
-
-/* EBI :: BURST_CFG_0 :: reserved2 [03:02] */
-#define BCHP_EBI_BURST_CFG_0_reserved2_MASK 0x0000000c
-#define BCHP_EBI_BURST_CFG_0_reserved2_SHIFT 2
-
-/* EBI :: BURST_CFG_0 :: data_hold [01:01] */
-#define BCHP_EBI_BURST_CFG_0_data_hold_MASK 0x00000002
-#define BCHP_EBI_BURST_CFG_0_data_hold_SHIFT 1
-#define BCHP_EBI_BURST_CFG_0_data_hold_DEFAULT 0x00000000
-
-/* EBI :: BURST_CFG_0 :: burst_16 [00:00] */
-#define BCHP_EBI_BURST_CFG_0_burst_16_MASK 0x00000001
-#define BCHP_EBI_BURST_CFG_0_burst_16_SHIFT 0
-#define BCHP_EBI_BURST_CFG_0_burst_16_DEFAULT 0x00000000
-
-/***************************************************************************
- *BURST_CFG_1 - EBI Synchronous Intel StrataFlash Burst Configure Register
- ***************************************************************************/
-/* EBI :: BURST_CFG_1 :: prefetch_enable [31:31] */
-#define BCHP_EBI_BURST_CFG_1_prefetch_enable_MASK 0x80000000
-#define BCHP_EBI_BURST_CFG_1_prefetch_enable_SHIFT 31
-#define BCHP_EBI_BURST_CFG_1_prefetch_enable_DEFAULT 0x00000000
-
-/* EBI :: BURST_CFG_1 :: page_enable [30:30] */
-#define BCHP_EBI_BURST_CFG_1_page_enable_MASK 0x40000000
-#define BCHP_EBI_BURST_CFG_1_page_enable_SHIFT 30
-#define BCHP_EBI_BURST_CFG_1_page_enable_DEFAULT 0x00000000
-
-/* EBI :: BURST_CFG_1 :: pfetch_abort_enable [29:29] */
-#define BCHP_EBI_BURST_CFG_1_pfetch_abort_enable_MASK 0x20000000
-#define BCHP_EBI_BURST_CFG_1_pfetch_abort_enable_SHIFT 29
-#define BCHP_EBI_BURST_CFG_1_pfetch_abort_enable_DEFAULT 0x00000000
-
-/* EBI :: BURST_CFG_1 :: page_latch_enable [28:28] */
-#define BCHP_EBI_BURST_CFG_1_page_latch_enable_MASK 0x10000000
-#define BCHP_EBI_BURST_CFG_1_page_latch_enable_SHIFT 28
-#define BCHP_EBI_BURST_CFG_1_page_latch_enable_DEFAULT 0x00000000
-
-/* EBI :: BURST_CFG_1 :: pfetch_wrap_enable [27:27] */
-#define BCHP_EBI_BURST_CFG_1_pfetch_wrap_enable_MASK 0x08000000
-#define BCHP_EBI_BURST_CFG_1_pfetch_wrap_enable_SHIFT 27
-#define BCHP_EBI_BURST_CFG_1_pfetch_wrap_enable_DEFAULT 0x00000000
-
-/* EBI :: BURST_CFG_1 :: reserved0 [26:24] */
-#define BCHP_EBI_BURST_CFG_1_reserved0_MASK 0x07000000
-#define BCHP_EBI_BURST_CFG_1_reserved0_SHIFT 24
-
-/* EBI :: BURST_CFG_1 :: prefetch_size [23:22] */
-#define BCHP_EBI_BURST_CFG_1_prefetch_size_MASK 0x00c00000
-#define BCHP_EBI_BURST_CFG_1_prefetch_size_SHIFT 22
-#define BCHP_EBI_BURST_CFG_1_prefetch_size_DEFAULT 0x00000000
-#define BCHP_EBI_BURST_CFG_1_prefetch_size_SIZE_4_BYTES 0
-#define BCHP_EBI_BURST_CFG_1_prefetch_size_SIZE_8_BYTES 1
-#define BCHP_EBI_BURST_CFG_1_prefetch_size_SIZE_16_BYTES 2
-#define BCHP_EBI_BURST_CFG_1_prefetch_size_SIZE_32_BYTES 3
-
-/* EBI :: BURST_CFG_1 :: page_size [21:20] */
-#define BCHP_EBI_BURST_CFG_1_page_size_MASK 0x00300000
-#define BCHP_EBI_BURST_CFG_1_page_size_SHIFT 20
-#define BCHP_EBI_BURST_CFG_1_page_size_DEFAULT 0x00000000
-#define BCHP_EBI_BURST_CFG_1_page_size_SIZE_4_BYTES 0
-#define BCHP_EBI_BURST_CFG_1_page_size_SIZE_8_BYTES 1
-#define BCHP_EBI_BURST_CFG_1_page_size_SIZE_16_BYTES 2
-#define BCHP_EBI_BURST_CFG_1_page_size_SIZE_32_BYTES 3
-
-/* EBI :: BURST_CFG_1 :: page_wait_count [19:16] */
-#define BCHP_EBI_BURST_CFG_1_page_wait_count_MASK 0x000f0000
-#define BCHP_EBI_BURST_CFG_1_page_wait_count_SHIFT 16
-#define BCHP_EBI_BURST_CFG_1_page_wait_count_DEFAULT 0x00000001
-
-/* EBI :: BURST_CFG_1 :: burst_cyc_disable [15:15] */
-#define BCHP_EBI_BURST_CFG_1_burst_cyc_disable_MASK 0x00008000
-#define BCHP_EBI_BURST_CFG_1_burst_cyc_disable_SHIFT 15
-#define BCHP_EBI_BURST_CFG_1_burst_cyc_disable_DEFAULT 0x00000001
-
-/* EBI :: BURST_CFG_1 :: reserved1 [14:08] */
-#define BCHP_EBI_BURST_CFG_1_reserved1_MASK 0x00007f00
-#define BCHP_EBI_BURST_CFG_1_reserved1_SHIFT 8
-
-/* EBI :: BURST_CFG_1 :: burst_latency [07:04] */
-#define BCHP_EBI_BURST_CFG_1_burst_latency_MASK 0x000000f0
-#define BCHP_EBI_BURST_CFG_1_burst_latency_SHIFT 4
-#define BCHP_EBI_BURST_CFG_1_burst_latency_DEFAULT 0x00000000
-
-/* EBI :: BURST_CFG_1 :: reserved2 [03:02] */
-#define BCHP_EBI_BURST_CFG_1_reserved2_MASK 0x0000000c
-#define BCHP_EBI_BURST_CFG_1_reserved2_SHIFT 2
-
-/* EBI :: BURST_CFG_1 :: data_hold [01:01] */
-#define BCHP_EBI_BURST_CFG_1_data_hold_MASK 0x00000002
-#define BCHP_EBI_BURST_CFG_1_data_hold_SHIFT 1
-#define BCHP_EBI_BURST_CFG_1_data_hold_DEFAULT 0x00000000
-
-/* EBI :: BURST_CFG_1 :: burst_16 [00:00] */
-#define BCHP_EBI_BURST_CFG_1_burst_16_MASK 0x00000001
-#define BCHP_EBI_BURST_CFG_1_burst_16_SHIFT 0
-#define BCHP_EBI_BURST_CFG_1_burst_16_DEFAULT 0x00000000
-
-/***************************************************************************
- *BURST_CFG_2 - EBI Synchronous Intel StrataFlash Burst Configure Register
- ***************************************************************************/
-/* EBI :: BURST_CFG_2 :: prefetch_enable [31:31] */
-#define BCHP_EBI_BURST_CFG_2_prefetch_enable_MASK 0x80000000
-#define BCHP_EBI_BURST_CFG_2_prefetch_enable_SHIFT 31
-#define BCHP_EBI_BURST_CFG_2_prefetch_enable_DEFAULT 0x00000000
-
-/* EBI :: BURST_CFG_2 :: page_enable [30:30] */
-#define BCHP_EBI_BURST_CFG_2_page_enable_MASK 0x40000000
-#define BCHP_EBI_BURST_CFG_2_page_enable_SHIFT 30
-#define BCHP_EBI_BURST_CFG_2_page_enable_DEFAULT 0x00000000
-
-/* EBI :: BURST_CFG_2 :: pfetch_abort_enable [29:29] */
-#define BCHP_EBI_BURST_CFG_2_pfetch_abort_enable_MASK 0x20000000
-#define BCHP_EBI_BURST_CFG_2_pfetch_abort_enable_SHIFT 29
-#define BCHP_EBI_BURST_CFG_2_pfetch_abort_enable_DEFAULT 0x00000000
-
-/* EBI :: BURST_CFG_2 :: page_latch_enable [28:28] */
-#define BCHP_EBI_BURST_CFG_2_page_latch_enable_MASK 0x10000000
-#define BCHP_EBI_BURST_CFG_2_page_latch_enable_SHIFT 28
-#define BCHP_EBI_BURST_CFG_2_page_latch_enable_DEFAULT 0x00000000
-
-/* EBI :: BURST_CFG_2 :: pfetch_wrap_enable [27:27] */
-#define BCHP_EBI_BURST_CFG_2_pfetch_wrap_enable_MASK 0x08000000
-#define BCHP_EBI_BURST_CFG_2_pfetch_wrap_enable_SHIFT 27
-#define BCHP_EBI_BURST_CFG_2_pfetch_wrap_enable_DEFAULT 0x00000000
-
-/* EBI :: BURST_CFG_2 :: reserved0 [26:24] */
-#define BCHP_EBI_BURST_CFG_2_reserved0_MASK 0x07000000
-#define BCHP_EBI_BURST_CFG_2_reserved0_SHIFT 24
-
-/* EBI :: BURST_CFG_2 :: prefetch_size [23:22] */
-#define BCHP_EBI_BURST_CFG_2_prefetch_size_MASK 0x00c00000
-#define BCHP_EBI_BURST_CFG_2_prefetch_size_SHIFT 22
-#define BCHP_EBI_BURST_CFG_2_prefetch_size_DEFAULT 0x00000000
-#define BCHP_EBI_BURST_CFG_2_prefetch_size_SIZE_4_BYTES 0
-#define BCHP_EBI_BURST_CFG_2_prefetch_size_SIZE_8_BYTES 1
-#define BCHP_EBI_BURST_CFG_2_prefetch_size_SIZE_16_BYTES 2
-#define BCHP_EBI_BURST_CFG_2_prefetch_size_SIZE_32_BYTES 3
-
-/* EBI :: BURST_CFG_2 :: page_size [21:20] */
-#define BCHP_EBI_BURST_CFG_2_page_size_MASK 0x00300000
-#define BCHP_EBI_BURST_CFG_2_page_size_SHIFT 20
-#define BCHP_EBI_BURST_CFG_2_page_size_DEFAULT 0x00000000
-#define BCHP_EBI_BURST_CFG_2_page_size_SIZE_4_BYTES 0
-#define BCHP_EBI_BURST_CFG_2_page_size_SIZE_8_BYTES 1
-#define BCHP_EBI_BURST_CFG_2_page_size_SIZE_16_BYTES 2
-#define BCHP_EBI_BURST_CFG_2_page_size_SIZE_32_BYTES 3
-
-/* EBI :: BURST_CFG_2 :: page_wait_count [19:16] */
-#define BCHP_EBI_BURST_CFG_2_page_wait_count_MASK 0x000f0000
-#define BCHP_EBI_BURST_CFG_2_page_wait_count_SHIFT 16
-#define BCHP_EBI_BURST_CFG_2_page_wait_count_DEFAULT 0x00000001
-
-/* EBI :: BURST_CFG_2 :: burst_cyc_disable [15:15] */
-#define BCHP_EBI_BURST_CFG_2_burst_cyc_disable_MASK 0x00008000
-#define BCHP_EBI_BURST_CFG_2_burst_cyc_disable_SHIFT 15
-#define BCHP_EBI_BURST_CFG_2_burst_cyc_disable_DEFAULT 0x00000001
-
-/* EBI :: BURST_CFG_2 :: reserved1 [14:08] */
-#define BCHP_EBI_BURST_CFG_2_reserved1_MASK 0x00007f00
-#define BCHP_EBI_BURST_CFG_2_reserved1_SHIFT 8
-
-/* EBI :: BURST_CFG_2 :: burst_latency [07:04] */
-#define BCHP_EBI_BURST_CFG_2_burst_latency_MASK 0x000000f0
-#define BCHP_EBI_BURST_CFG_2_burst_latency_SHIFT 4
-#define BCHP_EBI_BURST_CFG_2_burst_latency_DEFAULT 0x00000000
-
-/* EBI :: BURST_CFG_2 :: reserved2 [03:02] */
-#define BCHP_EBI_BURST_CFG_2_reserved2_MASK 0x0000000c
-#define BCHP_EBI_BURST_CFG_2_reserved2_SHIFT 2
-
-/* EBI :: BURST_CFG_2 :: data_hold [01:01] */
-#define BCHP_EBI_BURST_CFG_2_data_hold_MASK 0x00000002
-#define BCHP_EBI_BURST_CFG_2_data_hold_SHIFT 1
-#define BCHP_EBI_BURST_CFG_2_data_hold_DEFAULT 0x00000000
-
-/* EBI :: BURST_CFG_2 :: burst_16 [00:00] */
-#define BCHP_EBI_BURST_CFG_2_burst_16_MASK 0x00000001
-#define BCHP_EBI_BURST_CFG_2_burst_16_SHIFT 0
-#define BCHP_EBI_BURST_CFG_2_burst_16_DEFAULT 0x00000000
-
-/***************************************************************************
- *BURST_CFG_3 - EBI Synchronous Intel StrataFlash Burst Configure Register
- ***************************************************************************/
-/* EBI :: BURST_CFG_3 :: prefetch_enable [31:31] */
-#define BCHP_EBI_BURST_CFG_3_prefetch_enable_MASK 0x80000000
-#define BCHP_EBI_BURST_CFG_3_prefetch_enable_SHIFT 31
-#define BCHP_EBI_BURST_CFG_3_prefetch_enable_DEFAULT 0x00000000
-
-/* EBI :: BURST_CFG_3 :: page_enable [30:30] */
-#define BCHP_EBI_BURST_CFG_3_page_enable_MASK 0x40000000
-#define BCHP_EBI_BURST_CFG_3_page_enable_SHIFT 30
-#define BCHP_EBI_BURST_CFG_3_page_enable_DEFAULT 0x00000000
-
-/* EBI :: BURST_CFG_3 :: pfetch_abort_enable [29:29] */
-#define BCHP_EBI_BURST_CFG_3_pfetch_abort_enable_MASK 0x20000000
-#define BCHP_EBI_BURST_CFG_3_pfetch_abort_enable_SHIFT 29
-#define BCHP_EBI_BURST_CFG_3_pfetch_abort_enable_DEFAULT 0x00000000
-
-/* EBI :: BURST_CFG_3 :: page_latch_enable [28:28] */
-#define BCHP_EBI_BURST_CFG_3_page_latch_enable_MASK 0x10000000
-#define BCHP_EBI_BURST_CFG_3_page_latch_enable_SHIFT 28
-#define BCHP_EBI_BURST_CFG_3_page_latch_enable_DEFAULT 0x00000000
-
-/* EBI :: BURST_CFG_3 :: pfetch_wrap_enable [27:27] */
-#define BCHP_EBI_BURST_CFG_3_pfetch_wrap_enable_MASK 0x08000000
-#define BCHP_EBI_BURST_CFG_3_pfetch_wrap_enable_SHIFT 27
-#define BCHP_EBI_BURST_CFG_3_pfetch_wrap_enable_DEFAULT 0x00000000
-
-/* EBI :: BURST_CFG_3 :: reserved0 [26:24] */
-#define BCHP_EBI_BURST_CFG_3_reserved0_MASK 0x07000000
-#define BCHP_EBI_BURST_CFG_3_reserved0_SHIFT 24
-
-/* EBI :: BURST_CFG_3 :: prefetch_size [23:22] */
-#define BCHP_EBI_BURST_CFG_3_prefetch_size_MASK 0x00c00000
-#define BCHP_EBI_BURST_CFG_3_prefetch_size_SHIFT 22
-#define BCHP_EBI_BURST_CFG_3_prefetch_size_DEFAULT 0x00000000
-#define BCHP_EBI_BURST_CFG_3_prefetch_size_SIZE_4_BYTES 0
-#define BCHP_EBI_BURST_CFG_3_prefetch_size_SIZE_8_BYTES 1
-#define BCHP_EBI_BURST_CFG_3_prefetch_size_SIZE_16_BYTES 2
-#define BCHP_EBI_BURST_CFG_3_prefetch_size_SIZE_32_BYTES 3
-
-/* EBI :: BURST_CFG_3 :: page_size [21:20] */
-#define BCHP_EBI_BURST_CFG_3_page_size_MASK 0x00300000
-#define BCHP_EBI_BURST_CFG_3_page_size_SHIFT 20
-#define BCHP_EBI_BURST_CFG_3_page_size_DEFAULT 0x00000000
-#define BCHP_EBI_BURST_CFG_3_page_size_SIZE_4_BYTES 0
-#define BCHP_EBI_BURST_CFG_3_page_size_SIZE_8_BYTES 1
-#define BCHP_EBI_BURST_CFG_3_page_size_SIZE_16_BYTES 2
-#define BCHP_EBI_BURST_CFG_3_page_size_SIZE_32_BYTES 3
-
-/* EBI :: BURST_CFG_3 :: page_wait_count [19:16] */
-#define BCHP_EBI_BURST_CFG_3_page_wait_count_MASK 0x000f0000
-#define BCHP_EBI_BURST_CFG_3_page_wait_count_SHIFT 16
-#define BCHP_EBI_BURST_CFG_3_page_wait_count_DEFAULT 0x00000001
-
-/* EBI :: BURST_CFG_3 :: burst_cyc_disable [15:15] */
-#define BCHP_EBI_BURST_CFG_3_burst_cyc_disable_MASK 0x00008000
-#define BCHP_EBI_BURST_CFG_3_burst_cyc_disable_SHIFT 15
-#define BCHP_EBI_BURST_CFG_3_burst_cyc_disable_DEFAULT 0x00000001
-
-/* EBI :: BURST_CFG_3 :: reserved1 [14:08] */
-#define BCHP_EBI_BURST_CFG_3_reserved1_MASK 0x00007f00
-#define BCHP_EBI_BURST_CFG_3_reserved1_SHIFT 8
-
-/* EBI :: BURST_CFG_3 :: burst_latency [07:04] */
-#define BCHP_EBI_BURST_CFG_3_burst_latency_MASK 0x000000f0
-#define BCHP_EBI_BURST_CFG_3_burst_latency_SHIFT 4
-#define BCHP_EBI_BURST_CFG_3_burst_latency_DEFAULT 0x00000000
-
-/* EBI :: BURST_CFG_3 :: reserved2 [03:02] */
-#define BCHP_EBI_BURST_CFG_3_reserved2_MASK 0x0000000c
-#define BCHP_EBI_BURST_CFG_3_reserved2_SHIFT 2
-
-/* EBI :: BURST_CFG_3 :: data_hold [01:01] */
-#define BCHP_EBI_BURST_CFG_3_data_hold_MASK 0x00000002
-#define BCHP_EBI_BURST_CFG_3_data_hold_SHIFT 1
-#define BCHP_EBI_BURST_CFG_3_data_hold_DEFAULT 0x00000000
-
-/* EBI :: BURST_CFG_3 :: burst_16 [00:00] */
-#define BCHP_EBI_BURST_CFG_3_burst_16_MASK 0x00000001
-#define BCHP_EBI_BURST_CFG_3_burst_16_SHIFT 0
-#define BCHP_EBI_BURST_CFG_3_burst_16_DEFAULT 0x00000000
-
-/***************************************************************************
- *BURST_CFG_4 - EBI Synchronous Intel StrataFlash Burst Configure Register
- ***************************************************************************/
-/* EBI :: BURST_CFG_4 :: prefetch_enable [31:31] */
-#define BCHP_EBI_BURST_CFG_4_prefetch_enable_MASK 0x80000000
-#define BCHP_EBI_BURST_CFG_4_prefetch_enable_SHIFT 31
-#define BCHP_EBI_BURST_CFG_4_prefetch_enable_DEFAULT 0x00000000
-
-/* EBI :: BURST_CFG_4 :: page_enable [30:30] */
-#define BCHP_EBI_BURST_CFG_4_page_enable_MASK 0x40000000
-#define BCHP_EBI_BURST_CFG_4_page_enable_SHIFT 30
-#define BCHP_EBI_BURST_CFG_4_page_enable_DEFAULT 0x00000000
-
-/* EBI :: BURST_CFG_4 :: pfetch_abort_enable [29:29] */
-#define BCHP_EBI_BURST_CFG_4_pfetch_abort_enable_MASK 0x20000000
-#define BCHP_EBI_BURST_CFG_4_pfetch_abort_enable_SHIFT 29
-#define BCHP_EBI_BURST_CFG_4_pfetch_abort_enable_DEFAULT 0x00000000
-
-/* EBI :: BURST_CFG_4 :: page_latch_enable [28:28] */
-#define BCHP_EBI_BURST_CFG_4_page_latch_enable_MASK 0x10000000
-#define BCHP_EBI_BURST_CFG_4_page_latch_enable_SHIFT 28
-#define BCHP_EBI_BURST_CFG_4_page_latch_enable_DEFAULT 0x00000000
-
-/* EBI :: BURST_CFG_4 :: pfetch_wrap_enable [27:27] */
-#define BCHP_EBI_BURST_CFG_4_pfetch_wrap_enable_MASK 0x08000000
-#define BCHP_EBI_BURST_CFG_4_pfetch_wrap_enable_SHIFT 27
-#define BCHP_EBI_BURST_CFG_4_pfetch_wrap_enable_DEFAULT 0x00000000
-
-/* EBI :: BURST_CFG_4 :: reserved0 [26:24] */
-#define BCHP_EBI_BURST_CFG_4_reserved0_MASK 0x07000000
-#define BCHP_EBI_BURST_CFG_4_reserved0_SHIFT 24
-
-/* EBI :: BURST_CFG_4 :: prefetch_size [23:22] */
-#define BCHP_EBI_BURST_CFG_4_prefetch_size_MASK 0x00c00000
-#define BCHP_EBI_BURST_CFG_4_prefetch_size_SHIFT 22
-#define BCHP_EBI_BURST_CFG_4_prefetch_size_DEFAULT 0x00000000
-#define BCHP_EBI_BURST_CFG_4_prefetch_size_SIZE_4_BYTES 0
-#define BCHP_EBI_BURST_CFG_4_prefetch_size_SIZE_8_BYTES 1
-#define BCHP_EBI_BURST_CFG_4_prefetch_size_SIZE_16_BYTES 2
-#define BCHP_EBI_BURST_CFG_4_prefetch_size_SIZE_32_BYTES 3
-
-/* EBI :: BURST_CFG_4 :: page_size [21:20] */
-#define BCHP_EBI_BURST_CFG_4_page_size_MASK 0x00300000
-#define BCHP_EBI_BURST_CFG_4_page_size_SHIFT 20
-#define BCHP_EBI_BURST_CFG_4_page_size_DEFAULT 0x00000000
-#define BCHP_EBI_BURST_CFG_4_page_size_SIZE_4_BYTES 0
-#define BCHP_EBI_BURST_CFG_4_page_size_SIZE_8_BYTES 1
-#define BCHP_EBI_BURST_CFG_4_page_size_SIZE_16_BYTES 2
-#define BCHP_EBI_BURST_CFG_4_page_size_SIZE_32_BYTES 3
-
-/* EBI :: BURST_CFG_4 :: page_wait_count [19:16] */
-#define BCHP_EBI_BURST_CFG_4_page_wait_count_MASK 0x000f0000
-#define BCHP_EBI_BURST_CFG_4_page_wait_count_SHIFT 16
-#define BCHP_EBI_BURST_CFG_4_page_wait_count_DEFAULT 0x00000001
-
-/* EBI :: BURST_CFG_4 :: burst_cyc_disable [15:15] */
-#define BCHP_EBI_BURST_CFG_4_burst_cyc_disable_MASK 0x00008000
-#define BCHP_EBI_BURST_CFG_4_burst_cyc_disable_SHIFT 15
-#define BCHP_EBI_BURST_CFG_4_burst_cyc_disable_DEFAULT 0x00000001
-
-/* EBI :: BURST_CFG_4 :: reserved1 [14:08] */
-#define BCHP_EBI_BURST_CFG_4_reserved1_MASK 0x00007f00
-#define BCHP_EBI_BURST_CFG_4_reserved1_SHIFT 8
-
-/* EBI :: BURST_CFG_4 :: burst_latency [07:04] */
-#define BCHP_EBI_BURST_CFG_4_burst_latency_MASK 0x000000f0
-#define BCHP_EBI_BURST_CFG_4_burst_latency_SHIFT 4
-#define BCHP_EBI_BURST_CFG_4_burst_latency_DEFAULT 0x00000000
-
-/* EBI :: BURST_CFG_4 :: reserved2 [03:02] */
-#define BCHP_EBI_BURST_CFG_4_reserved2_MASK 0x0000000c
-#define BCHP_EBI_BURST_CFG_4_reserved2_SHIFT 2
-
-/* EBI :: BURST_CFG_4 :: data_hold [01:01] */
-#define BCHP_EBI_BURST_CFG_4_data_hold_MASK 0x00000002
-#define BCHP_EBI_BURST_CFG_4_data_hold_SHIFT 1
-#define BCHP_EBI_BURST_CFG_4_data_hold_DEFAULT 0x00000000
-
-/* EBI :: BURST_CFG_4 :: burst_16 [00:00] */
-#define BCHP_EBI_BURST_CFG_4_burst_16_MASK 0x00000001
-#define BCHP_EBI_BURST_CFG_4_burst_16_SHIFT 0
-#define BCHP_EBI_BURST_CFG_4_burst_16_DEFAULT 0x00000000
-
-/***************************************************************************
- *BURST_CFG_5 - EBI Synchronous Intel StrataFlash Burst Configure Register
- ***************************************************************************/
-/* EBI :: BURST_CFG_5 :: prefetch_enable [31:31] */
-#define BCHP_EBI_BURST_CFG_5_prefetch_enable_MASK 0x80000000
-#define BCHP_EBI_BURST_CFG_5_prefetch_enable_SHIFT 31
-#define BCHP_EBI_BURST_CFG_5_prefetch_enable_DEFAULT 0x00000000
-
-/* EBI :: BURST_CFG_5 :: page_enable [30:30] */
-#define BCHP_EBI_BURST_CFG_5_page_enable_MASK 0x40000000
-#define BCHP_EBI_BURST_CFG_5_page_enable_SHIFT 30
-#define BCHP_EBI_BURST_CFG_5_page_enable_DEFAULT 0x00000000
-
-/* EBI :: BURST_CFG_5 :: pfetch_abort_enable [29:29] */
-#define BCHP_EBI_BURST_CFG_5_pfetch_abort_enable_MASK 0x20000000
-#define BCHP_EBI_BURST_CFG_5_pfetch_abort_enable_SHIFT 29
-#define BCHP_EBI_BURST_CFG_5_pfetch_abort_enable_DEFAULT 0x00000000
-
-/* EBI :: BURST_CFG_5 :: page_latch_enable [28:28] */
-#define BCHP_EBI_BURST_CFG_5_page_latch_enable_MASK 0x10000000
-#define BCHP_EBI_BURST_CFG_5_page_latch_enable_SHIFT 28
-#define BCHP_EBI_BURST_CFG_5_page_latch_enable_DEFAULT 0x00000000
-
-/* EBI :: BURST_CFG_5 :: pfetch_wrap_enable [27:27] */
-#define BCHP_EBI_BURST_CFG_5_pfetch_wrap_enable_MASK 0x08000000
-#define BCHP_EBI_BURST_CFG_5_pfetch_wrap_enable_SHIFT 27
-#define BCHP_EBI_BURST_CFG_5_pfetch_wrap_enable_DEFAULT 0x00000000
-
-/* EBI :: BURST_CFG_5 :: reserved0 [26:24] */
-#define BCHP_EBI_BURST_CFG_5_reserved0_MASK 0x07000000
-#define BCHP_EBI_BURST_CFG_5_reserved0_SHIFT 24
-
-/* EBI :: BURST_CFG_5 :: prefetch_size [23:22] */
-#define BCHP_EBI_BURST_CFG_5_prefetch_size_MASK 0x00c00000
-#define BCHP_EBI_BURST_CFG_5_prefetch_size_SHIFT 22
-#define BCHP_EBI_BURST_CFG_5_prefetch_size_DEFAULT 0x00000000
-#define BCHP_EBI_BURST_CFG_5_prefetch_size_SIZE_4_BYTES 0
-#define BCHP_EBI_BURST_CFG_5_prefetch_size_SIZE_8_BYTES 1
-#define BCHP_EBI_BURST_CFG_5_prefetch_size_SIZE_16_BYTES 2
-#define BCHP_EBI_BURST_CFG_5_prefetch_size_SIZE_32_BYTES 3
-
-/* EBI :: BURST_CFG_5 :: page_size [21:20] */
-#define BCHP_EBI_BURST_CFG_5_page_size_MASK 0x00300000
-#define BCHP_EBI_BURST_CFG_5_page_size_SHIFT 20
-#define BCHP_EBI_BURST_CFG_5_page_size_DEFAULT 0x00000000
-#define BCHP_EBI_BURST_CFG_5_page_size_SIZE_4_BYTES 0
-#define BCHP_EBI_BURST_CFG_5_page_size_SIZE_8_BYTES 1
-#define BCHP_EBI_BURST_CFG_5_page_size_SIZE_16_BYTES 2
-#define BCHP_EBI_BURST_CFG_5_page_size_SIZE_32_BYTES 3
-
-/* EBI :: BURST_CFG_5 :: page_wait_count [19:16] */
-#define BCHP_EBI_BURST_CFG_5_page_wait_count_MASK 0x000f0000
-#define BCHP_EBI_BURST_CFG_5_page_wait_count_SHIFT 16
-#define BCHP_EBI_BURST_CFG_5_page_wait_count_DEFAULT 0x00000001
-
-/* EBI :: BURST_CFG_5 :: burst_cyc_disable [15:15] */
-#define BCHP_EBI_BURST_CFG_5_burst_cyc_disable_MASK 0x00008000
-#define BCHP_EBI_BURST_CFG_5_burst_cyc_disable_SHIFT 15
-#define BCHP_EBI_BURST_CFG_5_burst_cyc_disable_DEFAULT 0x00000001
-
-/* EBI :: BURST_CFG_5 :: reserved1 [14:08] */
-#define BCHP_EBI_BURST_CFG_5_reserved1_MASK 0x00007f00
-#define BCHP_EBI_BURST_CFG_5_reserved1_SHIFT 8
-
-/* EBI :: BURST_CFG_5 :: burst_latency [07:04] */
-#define BCHP_EBI_BURST_CFG_5_burst_latency_MASK 0x000000f0
-#define BCHP_EBI_BURST_CFG_5_burst_latency_SHIFT 4
-#define BCHP_EBI_BURST_CFG_5_burst_latency_DEFAULT 0x00000000
-
-/* EBI :: BURST_CFG_5 :: reserved2 [03:02] */
-#define BCHP_EBI_BURST_CFG_5_reserved2_MASK 0x0000000c
-#define BCHP_EBI_BURST_CFG_5_reserved2_SHIFT 2
-
-/* EBI :: BURST_CFG_5 :: data_hold [01:01] */
-#define BCHP_EBI_BURST_CFG_5_data_hold_MASK 0x00000002
-#define BCHP_EBI_BURST_CFG_5_data_hold_SHIFT 1
-#define BCHP_EBI_BURST_CFG_5_data_hold_DEFAULT 0x00000000
-
-/* EBI :: BURST_CFG_5 :: burst_16 [00:00] */
-#define BCHP_EBI_BURST_CFG_5_burst_16_MASK 0x00000001
-#define BCHP_EBI_BURST_CFG_5_burst_16_SHIFT 0
-#define BCHP_EBI_BURST_CFG_5_burst_16_DEFAULT 0x00000000
-
-/***************************************************************************
- *BURST_CFG_6 - EBI Synchronous Intel StrataFlash Burst Configure Register
- ***************************************************************************/
-/* EBI :: BURST_CFG_6 :: prefetch_enable [31:31] */
-#define BCHP_EBI_BURST_CFG_6_prefetch_enable_MASK 0x80000000
-#define BCHP_EBI_BURST_CFG_6_prefetch_enable_SHIFT 31
-#define BCHP_EBI_BURST_CFG_6_prefetch_enable_DEFAULT 0x00000000
-
-/* EBI :: BURST_CFG_6 :: page_enable [30:30] */
-#define BCHP_EBI_BURST_CFG_6_page_enable_MASK 0x40000000
-#define BCHP_EBI_BURST_CFG_6_page_enable_SHIFT 30
-#define BCHP_EBI_BURST_CFG_6_page_enable_DEFAULT 0x00000000
-
-/* EBI :: BURST_CFG_6 :: pfetch_abort_enable [29:29] */
-#define BCHP_EBI_BURST_CFG_6_pfetch_abort_enable_MASK 0x20000000
-#define BCHP_EBI_BURST_CFG_6_pfetch_abort_enable_SHIFT 29
-#define BCHP_EBI_BURST_CFG_6_pfetch_abort_enable_DEFAULT 0x00000000
-
-/* EBI :: BURST_CFG_6 :: page_latch_enable [28:28] */
-#define BCHP_EBI_BURST_CFG_6_page_latch_enable_MASK 0x10000000
-#define BCHP_EBI_BURST_CFG_6_page_latch_enable_SHIFT 28
-#define BCHP_EBI_BURST_CFG_6_page_latch_enable_DEFAULT 0x00000000
-
-/* EBI :: BURST_CFG_6 :: pfetch_wrap_enable [27:27] */
-#define BCHP_EBI_BURST_CFG_6_pfetch_wrap_enable_MASK 0x08000000
-#define BCHP_EBI_BURST_CFG_6_pfetch_wrap_enable_SHIFT 27
-#define BCHP_EBI_BURST_CFG_6_pfetch_wrap_enable_DEFAULT 0x00000000
-
-/* EBI :: BURST_CFG_6 :: reserved0 [26:24] */
-#define BCHP_EBI_BURST_CFG_6_reserved0_MASK 0x07000000
-#define BCHP_EBI_BURST_CFG_6_reserved0_SHIFT 24
-
-/* EBI :: BURST_CFG_6 :: prefetch_size [23:22] */
-#define BCHP_EBI_BURST_CFG_6_prefetch_size_MASK 0x00c00000
-#define BCHP_EBI_BURST_CFG_6_prefetch_size_SHIFT 22
-#define BCHP_EBI_BURST_CFG_6_prefetch_size_DEFAULT 0x00000000
-#define BCHP_EBI_BURST_CFG_6_prefetch_size_SIZE_4_BYTES 0
-#define BCHP_EBI_BURST_CFG_6_prefetch_size_SIZE_8_BYTES 1
-#define BCHP_EBI_BURST_CFG_6_prefetch_size_SIZE_16_BYTES 2
-#define BCHP_EBI_BURST_CFG_6_prefetch_size_SIZE_32_BYTES 3
-
-/* EBI :: BURST_CFG_6 :: page_size [21:20] */
-#define BCHP_EBI_BURST_CFG_6_page_size_MASK 0x00300000
-#define BCHP_EBI_BURST_CFG_6_page_size_SHIFT 20
-#define BCHP_EBI_BURST_CFG_6_page_size_DEFAULT 0x00000000
-#define BCHP_EBI_BURST_CFG_6_page_size_SIZE_4_BYTES 0
-#define BCHP_EBI_BURST_CFG_6_page_size_SIZE_8_BYTES 1
-#define BCHP_EBI_BURST_CFG_6_page_size_SIZE_16_BYTES 2
-#define BCHP_EBI_BURST_CFG_6_page_size_SIZE_32_BYTES 3
-
-/* EBI :: BURST_CFG_6 :: page_wait_count [19:16] */
-#define BCHP_EBI_BURST_CFG_6_page_wait_count_MASK 0x000f0000
-#define BCHP_EBI_BURST_CFG_6_page_wait_count_SHIFT 16
-#define BCHP_EBI_BURST_CFG_6_page_wait_count_DEFAULT 0x00000001
-
-/* EBI :: BURST_CFG_6 :: burst_cyc_disable [15:15] */
-#define BCHP_EBI_BURST_CFG_6_burst_cyc_disable_MASK 0x00008000
-#define BCHP_EBI_BURST_CFG_6_burst_cyc_disable_SHIFT 15
-#define BCHP_EBI_BURST_CFG_6_burst_cyc_disable_DEFAULT 0x00000001
-
-/* EBI :: BURST_CFG_6 :: reserved1 [14:08] */
-#define BCHP_EBI_BURST_CFG_6_reserved1_MASK 0x00007f00
-#define BCHP_EBI_BURST_CFG_6_reserved1_SHIFT 8
-
-/* EBI :: BURST_CFG_6 :: burst_latency [07:04] */
-#define BCHP_EBI_BURST_CFG_6_burst_latency_MASK 0x000000f0
-#define BCHP_EBI_BURST_CFG_6_burst_latency_SHIFT 4
-#define BCHP_EBI_BURST_CFG_6_burst_latency_DEFAULT 0x00000000
-
-/* EBI :: BURST_CFG_6 :: reserved2 [03:02] */
-#define BCHP_EBI_BURST_CFG_6_reserved2_MASK 0x0000000c
-#define BCHP_EBI_BURST_CFG_6_reserved2_SHIFT 2
-
-/* EBI :: BURST_CFG_6 :: data_hold [01:01] */
-#define BCHP_EBI_BURST_CFG_6_data_hold_MASK 0x00000002
-#define BCHP_EBI_BURST_CFG_6_data_hold_SHIFT 1
-#define BCHP_EBI_BURST_CFG_6_data_hold_DEFAULT 0x00000000
-
-/* EBI :: BURST_CFG_6 :: burst_16 [00:00] */
-#define BCHP_EBI_BURST_CFG_6_burst_16_MASK 0x00000001
-#define BCHP_EBI_BURST_CFG_6_burst_16_SHIFT 0
-#define BCHP_EBI_BURST_CFG_6_burst_16_DEFAULT 0x00000000
-
-/***************************************************************************
- *ECR - EBI Configuration Register
- ***************************************************************************/
-/* EBI :: ECR :: reserved0 [31:28] */
-#define BCHP_EBI_ECR_reserved0_MASK 0xf0000000
-#define BCHP_EBI_ECR_reserved0_SHIFT 28
-
-/* EBI :: ECR :: Ebi_Byte_Swap [27:27] */
-#define BCHP_EBI_ECR_Ebi_Byte_Swap_MASK 0x08000000
-#define BCHP_EBI_ECR_Ebi_Byte_Swap_SHIFT 27
-#define BCHP_EBI_ECR_Ebi_Byte_Swap_DEFAULT 0x00000000
-#define BCHP_EBI_ECR_Ebi_Byte_Swap_Byte_Swap_For_32_16_and_8_bit_Xfers 0
-#define BCHP_EBI_ECR_Ebi_Byte_Swap_Byte_Swap_For_8_bit_Xfers_Only 1
-
-/* EBI :: ECR :: reserved1 [26:26] */
-#define BCHP_EBI_ECR_reserved1_MASK 0x04000000
-#define BCHP_EBI_ECR_reserved1_SHIFT 26
-
-/* EBI :: ECR :: Flag_32bit_Xfer [25:25] */
-#define BCHP_EBI_ECR_Flag_32bit_Xfer_MASK 0x02000000
-#define BCHP_EBI_ECR_Flag_32bit_Xfer_SHIFT 25
-#define BCHP_EBI_ECR_Flag_32bit_Xfer_DEFAULT 0x00000000
-#define BCHP_EBI_ECR_Flag_32bit_Xfer_Code_32bit_Xfer_as_10 0
-#define BCHP_EBI_ECR_Flag_32bit_Xfer_Code_32bit_Xfer_as_00 1
-
-/* EBI :: ECR :: reserved2 [24:11] */
-#define BCHP_EBI_ECR_reserved2_MASK 0x01fff800
-#define BCHP_EBI_ECR_reserved2_SHIFT 11
-
-/* EBI :: ECR :: timeout_count [10:00] */
-#define BCHP_EBI_ECR_timeout_count_MASK 0x000007ff
-#define BCHP_EBI_ECR_timeout_count_SHIFT 0
-#define BCHP_EBI_ECR_timeout_count_DEFAULT 0x00000400
-
-/***************************************************************************
- *CS_TRISTATE_CFG - EBI CS Tristate Configuration Register
- ***************************************************************************/
-/* EBI :: CS_TRISTATE_CFG :: tristate_ebi_rdb [31:31] */
-#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_rdb_MASK 0x80000000
-#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_rdb_SHIFT 31
-#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_rdb_DEFAULT 0x00000000
-
-/* EBI :: CS_TRISTATE_CFG :: tristate_ebi_dsb [30:30] */
-#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_dsb_MASK 0x40000000
-#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_dsb_SHIFT 30
-#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_dsb_DEFAULT 0x00000000
-
-/* EBI :: CS_TRISTATE_CFG :: tristate_ebi_tsb [29:29] */
-#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_tsb_MASK 0x20000000
-#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_tsb_SHIFT 29
-#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_tsb_DEFAULT 0x00000000
-
-/* EBI :: CS_TRISTATE_CFG :: tristate_ebi_rwb [28:28] */
-#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_rwb_MASK 0x10000000
-#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_rwb_SHIFT 28
-#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_rwb_DEFAULT 0x00000000
-
-/* EBI :: CS_TRISTATE_CFG :: tristate_ebi_we1b [27:27] */
-#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_we1b_MASK 0x08000000
-#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_we1b_SHIFT 27
-#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_we1b_DEFAULT 0x00000000
-
-/* EBI :: CS_TRISTATE_CFG :: tristate_ebi_we0b [26:26] */
-#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_we0b_MASK 0x04000000
-#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_we0b_SHIFT 26
-#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_we0b_DEFAULT 0x00000000
-
-/* EBI :: CS_TRISTATE_CFG :: tristate_ebi_tsize1b [25:25] */
-#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_tsize1b_MASK 0x02000000
-#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_tsize1b_SHIFT 25
-#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_tsize1b_DEFAULT 0x00000000
-
-/* EBI :: CS_TRISTATE_CFG :: tristate_ebi_tsize0b [24:24] */
-#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_tsize0b_MASK 0x01000000
-#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_tsize0b_SHIFT 24
-#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_tsize0b_DEFAULT 0x00000000
-
-/* EBI :: CS_TRISTATE_CFG :: reserved0 [23:07] */
-#define BCHP_EBI_CS_TRISTATE_CFG_reserved0_MASK 0x00ffff80
-#define BCHP_EBI_CS_TRISTATE_CFG_reserved0_SHIFT 7
-
-/* EBI :: CS_TRISTATE_CFG :: tristate_ebi_cs6 [06:06] */
-#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_cs6_MASK 0x00000040
-#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_cs6_SHIFT 6
-#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_cs6_DEFAULT 0x00000000
-
-/* EBI :: CS_TRISTATE_CFG :: tristate_ebi_cs5 [05:05] */
-#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_cs5_MASK 0x00000020
-#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_cs5_SHIFT 5
-#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_cs5_DEFAULT 0x00000000
-
-/* EBI :: CS_TRISTATE_CFG :: tristate_ebi_cs4 [04:04] */
-#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_cs4_MASK 0x00000010
-#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_cs4_SHIFT 4
-#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_cs4_DEFAULT 0x00000000
-
-/* EBI :: CS_TRISTATE_CFG :: tristate_ebi_cs3 [03:03] */
-#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_cs3_MASK 0x00000008
-#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_cs3_SHIFT 3
-#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_cs3_DEFAULT 0x00000000
-
-/* EBI :: CS_TRISTATE_CFG :: tristate_ebi_cs2 [02:02] */
-#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_cs2_MASK 0x00000004
-#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_cs2_SHIFT 2
-#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_cs2_DEFAULT 0x00000000
-
-/* EBI :: CS_TRISTATE_CFG :: tristate_ebi_cs1 [01:01] */
-#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_cs1_MASK 0x00000002
-#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_cs1_SHIFT 1
-#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_cs1_DEFAULT 0x00000000
-
-/* EBI :: CS_TRISTATE_CFG :: tristate_ebi_cs0 [00:00] */
-#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_cs0_MASK 0x00000001
-#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_cs0_SHIFT 0
-#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_cs0_DEFAULT 0x00000000
-
-/***************************************************************************
- *CS_SPI_SELECT - SPI CS Select
- ***************************************************************************/
-/* EBI :: CS_SPI_SELECT :: reserved0 [31:15] */
-#define BCHP_EBI_CS_SPI_SELECT_reserved0_MASK 0xffff8000
-#define BCHP_EBI_CS_SPI_SELECT_reserved0_SHIFT 15
-
-/* EBI :: CS_SPI_SELECT :: EBI_CS_6_USES_SPI [14:14] */
-#define BCHP_EBI_CS_SPI_SELECT_EBI_CS_6_USES_SPI_MASK 0x00004000
-#define BCHP_EBI_CS_SPI_SELECT_EBI_CS_6_USES_SPI_SHIFT 14
-#define BCHP_EBI_CS_SPI_SELECT_EBI_CS_6_USES_SPI_DEFAULT 0x00000000
-
-/* EBI :: CS_SPI_SELECT :: EBI_CS_5_USES_SPI [13:13] */
-#define BCHP_EBI_CS_SPI_SELECT_EBI_CS_5_USES_SPI_MASK 0x00002000
-#define BCHP_EBI_CS_SPI_SELECT_EBI_CS_5_USES_SPI_SHIFT 13
-#define BCHP_EBI_CS_SPI_SELECT_EBI_CS_5_USES_SPI_DEFAULT 0x00000000
-
-/* EBI :: CS_SPI_SELECT :: EBI_CS_4_USES_SPI [12:12] */
-#define BCHP_EBI_CS_SPI_SELECT_EBI_CS_4_USES_SPI_MASK 0x00001000
-#define BCHP_EBI_CS_SPI_SELECT_EBI_CS_4_USES_SPI_SHIFT 12
-#define BCHP_EBI_CS_SPI_SELECT_EBI_CS_4_USES_SPI_DEFAULT 0x00000000
-
-/* EBI :: CS_SPI_SELECT :: EBI_CS_3_USES_SPI [11:11] */
-#define BCHP_EBI_CS_SPI_SELECT_EBI_CS_3_USES_SPI_MASK 0x00000800
-#define BCHP_EBI_CS_SPI_SELECT_EBI_CS_3_USES_SPI_SHIFT 11
-#define BCHP_EBI_CS_SPI_SELECT_EBI_CS_3_USES_SPI_DEFAULT 0x00000000
-
-/* EBI :: CS_SPI_SELECT :: EBI_CS_2_USES_SPI [10:10] */
-#define BCHP_EBI_CS_SPI_SELECT_EBI_CS_2_USES_SPI_MASK 0x00000400
-#define BCHP_EBI_CS_SPI_SELECT_EBI_CS_2_USES_SPI_SHIFT 10
-#define BCHP_EBI_CS_SPI_SELECT_EBI_CS_2_USES_SPI_DEFAULT 0x00000000
-
-/* EBI :: CS_SPI_SELECT :: EBI_CS_1_USES_SPI [09:09] */
-#define BCHP_EBI_CS_SPI_SELECT_EBI_CS_1_USES_SPI_MASK 0x00000200
-#define BCHP_EBI_CS_SPI_SELECT_EBI_CS_1_USES_SPI_SHIFT 9
-#define BCHP_EBI_CS_SPI_SELECT_EBI_CS_1_USES_SPI_DEFAULT 0x00000000
-
-/* EBI :: CS_SPI_SELECT :: EBI_CS_0_USES_SPI [08:08] */
-#define BCHP_EBI_CS_SPI_SELECT_EBI_CS_0_USES_SPI_MASK 0x00000100
-#define BCHP_EBI_CS_SPI_SELECT_EBI_CS_0_USES_SPI_SHIFT 8
-
-/* EBI :: CS_SPI_SELECT :: reserved1 [07:07] */
-#define BCHP_EBI_CS_SPI_SELECT_reserved1_MASK 0x00000080
-#define BCHP_EBI_CS_SPI_SELECT_reserved1_SHIFT 7
-
-/* EBI :: CS_SPI_SELECT :: SPI_EBI_CS_6_SEL [06:06] */
-#define BCHP_EBI_CS_SPI_SELECT_SPI_EBI_CS_6_SEL_MASK 0x00000040
-#define BCHP_EBI_CS_SPI_SELECT_SPI_EBI_CS_6_SEL_SHIFT 6
-#define BCHP_EBI_CS_SPI_SELECT_SPI_EBI_CS_6_SEL_DEFAULT 0x00000000
-
-/* EBI :: CS_SPI_SELECT :: SPI_EBI_CS_5_SEL [05:05] */
-#define BCHP_EBI_CS_SPI_SELECT_SPI_EBI_CS_5_SEL_MASK 0x00000020
-#define BCHP_EBI_CS_SPI_SELECT_SPI_EBI_CS_5_SEL_SHIFT 5
-#define BCHP_EBI_CS_SPI_SELECT_SPI_EBI_CS_5_SEL_DEFAULT 0x00000000
-
-/* EBI :: CS_SPI_SELECT :: SPI_EBI_CS_4_SEL [04:04] */
-#define BCHP_EBI_CS_SPI_SELECT_SPI_EBI_CS_4_SEL_MASK 0x00000010
-#define BCHP_EBI_CS_SPI_SELECT_SPI_EBI_CS_4_SEL_SHIFT 4
-#define BCHP_EBI_CS_SPI_SELECT_SPI_EBI_CS_4_SEL_DEFAULT 0x00000000
-
-/* EBI :: CS_SPI_SELECT :: SPI_EBI_CS_3_SEL [03:03] */
-#define BCHP_EBI_CS_SPI_SELECT_SPI_EBI_CS_3_SEL_MASK 0x00000008
-#define BCHP_EBI_CS_SPI_SELECT_SPI_EBI_CS_3_SEL_SHIFT 3
-#define BCHP_EBI_CS_SPI_SELECT_SPI_EBI_CS_3_SEL_DEFAULT 0x00000000
-
-/* EBI :: CS_SPI_SELECT :: SPI_EBI_CS_2_SEL [02:02] */
-#define BCHP_EBI_CS_SPI_SELECT_SPI_EBI_CS_2_SEL_MASK 0x00000004
-#define BCHP_EBI_CS_SPI_SELECT_SPI_EBI_CS_2_SEL_SHIFT 2
-#define BCHP_EBI_CS_SPI_SELECT_SPI_EBI_CS_2_SEL_DEFAULT 0x00000000
-
-/* EBI :: CS_SPI_SELECT :: SPI_EBI_CS_1_SEL [01:01] */
-#define BCHP_EBI_CS_SPI_SELECT_SPI_EBI_CS_1_SEL_MASK 0x00000002
-#define BCHP_EBI_CS_SPI_SELECT_SPI_EBI_CS_1_SEL_SHIFT 1
-#define BCHP_EBI_CS_SPI_SELECT_SPI_EBI_CS_1_SEL_DEFAULT 0x00000000
-
-/* EBI :: CS_SPI_SELECT :: SPI_EBI_CS_0_SEL [00:00] */
-#define BCHP_EBI_CS_SPI_SELECT_SPI_EBI_CS_0_SEL_MASK 0x00000001
-#define BCHP_EBI_CS_SPI_SELECT_SPI_EBI_CS_0_SEL_SHIFT 0
-
-/***************************************************************************
- *ARRAY_ADDRESS - EBI Data Array Address
- ***************************************************************************/
-/* EBI :: ARRAY_ADDRESS :: ADDRESS [31:09] */
-#define BCHP_EBI_ARRAY_ADDRESS_ADDRESS_MASK 0xfffffe00
-#define BCHP_EBI_ARRAY_ADDRESS_ADDRESS_SHIFT 9
-#define BCHP_EBI_ARRAY_ADDRESS_ADDRESS_DEFAULT 0x00000000
-
-/* EBI :: ARRAY_ADDRESS :: reserved0 [08:03] */
-#define BCHP_EBI_ARRAY_ADDRESS_reserved0_MASK 0x000001f8
-#define BCHP_EBI_ARRAY_ADDRESS_reserved0_SHIFT 3
-
-/* EBI :: ARRAY_ADDRESS :: CS_SEL [02:00] */
-#define BCHP_EBI_ARRAY_ADDRESS_CS_SEL_MASK 0x00000007
-#define BCHP_EBI_ARRAY_ADDRESS_CS_SEL_SHIFT 0
-#define BCHP_EBI_ARRAY_ADDRESS_CS_SEL_DEFAULT 0x00000000
-
-/***************************************************************************
- *DATA_ARRAY%i - EBI Data Array Read/Write Access
- ***************************************************************************/
-#define BCHP_EBI_DATA_ARRAYi_ARRAY_BASE 0x00440a00
-#define BCHP_EBI_DATA_ARRAYi_ARRAY_START 0
-#define BCHP_EBI_DATA_ARRAYi_ARRAY_END 127
-#define BCHP_EBI_DATA_ARRAYi_ARRAY_ELEMENT_SIZE 32
-
-/***************************************************************************
- *DATA_ARRAY%i - EBI Data Array Read/Write Access
- ***************************************************************************/
-/* EBI :: DATA_ARRAYi :: WORD [31:00] */
-#define BCHP_EBI_DATA_ARRAYi_WORD_MASK 0xffffffff
-#define BCHP_EBI_DATA_ARRAYi_WORD_SHIFT 0
-
-
-#endif /* #ifndef BCHP_EBI_H__ */
-
-/* End of File */
diff --git a/include/linux/brcmstb/7366b0/bchp_gio.h b/include/linux/brcmstb/7366b0/bchp_gio.h
deleted file mode 100644
index 21c4b25..0000000
--- a/include/linux/brcmstb/7366b0/bchp_gio.h
+++ /dev/null
@@ -1,546 +0,0 @@
-/***************************************************************************
- * Copyright (c) 1999-2014, Broadcom Corporation
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
- *
- * Module Description:
- * DO NOT EDIT THIS FILE DIRECTLY
- *
- * This module was generated magically with RDB from a source description
- * file. You must edit the source file for changes to be made to this file.
- *
- *
- * Date: Generated on Thu Apr 24 03:08:52 2014
- * Full Compile MD5 Checksum 1af2c2cf28828ece5496e1312aac0166
- * (minus title and desc)
- * MD5 Checksum 3203ffce85e3fc9a10f84123e54057b0
- *
- * Compiled with: RDB Utility combo_header.pl
- * RDB Parser 3.0
- * unknown unknown
- * Perl Interpreter 5.008008
- * Operating System linux
- *
- * Revision History:
- *
- * $brcm_Log: $
- *
- ***************************************************************************/
-
-#ifndef BCHP_GIO_H__
-#define BCHP_GIO_H__
-
-/***************************************************************************
- *GIO - GPIO
- ***************************************************************************/
-#define BCHP_GIO_ODEN_LO 0x0040a400 /* GENERAL PURPOSE I/O OPEN DRAIN ENABLE FOR GPIO[31:0] */
-#define BCHP_GIO_DATA_LO 0x0040a404 /* GENERAL PURPOSE I/O DATA FOR GPIO[31:0] */
-#define BCHP_GIO_IODIR_LO 0x0040a408 /* GENERAL PURPOSE I/O DIRECTION FOR GPIO[31:0] */
-#define BCHP_GIO_EC_LO 0x0040a40c /* GENERAL PURPOSE I/O EDGE CONFIGURATION FOR GPIO[31:0] */
-#define BCHP_GIO_EI_LO 0x0040a410 /* GENERAL PURPOSE I/O EDGE INSENSITIVE FOR GPIO[31:0] */
-#define BCHP_GIO_MASK_LO 0x0040a414 /* GENERAL PURPOSE I/O INTERRUPT MASK FOR GPIO[31:0] */
-#define BCHP_GIO_LEVEL_LO 0x0040a418 /* GENERAL PURPOSE I/O INTERRUPT TYPE FOR GPIO[31:0] */
-#define BCHP_GIO_STAT_LO 0x0040a41c /* GENERAL PURPOSE I/O INTERRUPT STATUS FOR GPIO[31:0] */
-#define BCHP_GIO_ODEN_HI 0x0040a420 /* GENERAL PURPOSE I/O OPEN DRAIN ENABLE FOR GPIO[63:32] */
-#define BCHP_GIO_DATA_HI 0x0040a424 /* GENERAL PURPOSE I/O DATA FOR GPIO[63:32] */
-#define BCHP_GIO_IODIR_HI 0x0040a428 /* GENERAL PURPOSE I/O DIRECTION FOR GPIO[63:32] */
-#define BCHP_GIO_EC_HI 0x0040a42c /* GENERAL PURPOSE I/O EDGE CONFIGURATION FOR GPIO[63:32] */
-#define BCHP_GIO_EI_HI 0x0040a430 /* GENERAL PURPOSE I/O EDGE INSENSITIVE FOR GPIO[63:32] */
-#define BCHP_GIO_MASK_HI 0x0040a434 /* GENERAL PURPOSE I/O INTERRUPT MASK FOR GPIO[63:32] */
-#define BCHP_GIO_LEVEL_HI 0x0040a438 /* GENERAL PURPOSE I/O INTERRUPT TYPE FOR GPIO[63:32] */
-#define BCHP_GIO_STAT_HI 0x0040a43c /* GENERAL PURPOSE I/O INTERRUPT STATUS FOR GPIO[63:32] */
-#define BCHP_GIO_ODEN_EXT_HI 0x0040a440 /* GENERAL PURPOSE I/O OPEN DRAIN ENABLE FOR GPIO[95:64] */
-#define BCHP_GIO_DATA_EXT_HI 0x0040a444 /* GENERAL PURPOSE I/O DATA FOR GPIO[95:64] */
-#define BCHP_GIO_IODIR_EXT_HI 0x0040a448 /* GENERAL PURPOSE I/O DIRECTION FOR GPIO[95:64] */
-#define BCHP_GIO_EC_EXT_HI 0x0040a44c /* GENERAL PURPOSE I/O EDGE CONFIGURATION FOR GPIO[95:64] */
-#define BCHP_GIO_EI_EXT_HI 0x0040a450 /* GENERAL PURPOSE I/O EDGE INSENSITIVE FOR GPIO[95:64] */
-#define BCHP_GIO_MASK_EXT_HI 0x0040a454 /* GENERAL PURPOSE I/O INTERRUPT MASK FOR GPIO[95:64] */
-#define BCHP_GIO_LEVEL_EXT_HI 0x0040a458 /* GENERAL PURPOSE I/O INTERRUPT TYPE FOR GPIO[95:64] */
-#define BCHP_GIO_STAT_EXT_HI 0x0040a45c /* GENERAL PURPOSE I/O INTERRUPT STATUS FOR GPIO[95:64] */
-#define BCHP_GIO_ODEN_EXT2 0x0040a460 /* GENERAL PURPOSE I/O OPEN DRAIN ENABLE FOR GPIO[127:96] */
-#define BCHP_GIO_DATA_EXT2 0x0040a464 /* GENERAL PURPOSE I/O DATA FOR GPIO[127:96] */
-#define BCHP_GIO_IODIR_EXT2 0x0040a468 /* GENERAL PURPOSE I/O DIRECTION FOR GPIO[127:96] */
-#define BCHP_GIO_EC_EXT2 0x0040a46c /* GENERAL PURPOSE I/O EDGE CONFIGURATION FOR GPIO[127:96] */
-#define BCHP_GIO_EI_EXT2 0x0040a470 /* GENERAL PURPOSE I/O EDGE INSENSITIVE FOR GPIO[127:96] */
-#define BCHP_GIO_MASK_EXT2 0x0040a474 /* GENERAL PURPOSE I/O INTERRUPT MASK FOR GPIO[127:96] */
-#define BCHP_GIO_LEVEL_EXT2 0x0040a478 /* GENERAL PURPOSE I/O INTERRUPT TYPE FOR GPIO[127:96] */
-#define BCHP_GIO_STAT_EXT2 0x0040a47c /* GENERAL PURPOSE I/O INTERRUPT STATUS FOR GPIO[127:96] */
-#define BCHP_GIO_ODEN_EXT3 0x0040a480 /* GENERAL PURPOSE I/O OPEN DRAIN ENABLE FOR GPIO[137:128] */
-#define BCHP_GIO_DATA_EXT3 0x0040a484 /* GENERAL PURPOSE I/O DATA FOR GPIO[137:128] */
-#define BCHP_GIO_IODIR_EXT3 0x0040a488 /* GENERAL PURPOSE I/O DIRECTION FOR GPIO[137:128] */
-#define BCHP_GIO_EC_EXT3 0x0040a48c /* GENERAL PURPOSE I/O EDGE CONFIGURATION FOR GPIO[137:128] */
-#define BCHP_GIO_EI_EXT3 0x0040a490 /* GENERAL PURPOSE I/O EDGE INSENSITIVE FOR GPIO[137:128] */
-#define BCHP_GIO_MASK_EXT3 0x0040a494 /* GENERAL PURPOSE I/O INTERRUPT MASK FOR GPIO[137:128] */
-#define BCHP_GIO_LEVEL_EXT3 0x0040a498 /* GENERAL PURPOSE I/O INTERRUPT TYPE FOR GPIO[137:128] */
-#define BCHP_GIO_STAT_EXT3 0x0040a49c /* GENERAL PURPOSE I/O INTERRUPT STATUS FOR GPIO[137:128] */
-#define BCHP_GIO_ODEN_EXT 0x0040a4a0 /* GENERAL PURPOSE I/O OPEN DRAIN ENABLE FOR AON_SGPIO[3:0] and SGPIO[5:0] */
-#define BCHP_GIO_DATA_EXT 0x0040a4a4 /* GENERAL PURPOSE I/O DATA FOR AON_SGPIO[3:0] and SGPIO[5:0] */
-#define BCHP_GIO_IODIR_EXT 0x0040a4a8 /* GENERAL PURPOSE I/O DIRECTION FOR AON_SGPIO[3:0] and SGPIO[5:0] */
-#define BCHP_GIO_EC_EXT 0x0040a4ac /* GENERAL PURPOSE I/O EDGE CONFIGURATION FOR AON_SGPIO[3:0] and SGPIO[5:0] */
-#define BCHP_GIO_EI_EXT 0x0040a4b0 /* GENERAL PURPOSE I/O EDGE INSENSITIVE FOR AON_SGPIO[3:0] and SGPIO[5:0] */
-#define BCHP_GIO_MASK_EXT 0x0040a4b4 /* GENERAL PURPOSE I/O INTERRUPT MASK FOR AON_SGPIO[3:0] and SGPIO[5:0] */
-#define BCHP_GIO_LEVEL_EXT 0x0040a4b8 /* GENERAL PURPOSE I/O INTERRUPT TYPE FOR AON_SGPIO[3:0] and SGPIO[5:0] */
-#define BCHP_GIO_STAT_EXT 0x0040a4bc /* GENERAL PURPOSE I/O INTERRUPT STATUS FOR AON_SGPIO[3:0] and SGPIO[5:0] */
-
-/***************************************************************************
- *ODEN_LO - GENERAL PURPOSE I/O OPEN DRAIN ENABLE FOR GPIO[31:0]
- ***************************************************************************/
-/* GIO :: ODEN_LO :: oden [31:00] */
-#define BCHP_GIO_ODEN_LO_oden_MASK 0xffffffff
-#define BCHP_GIO_ODEN_LO_oden_SHIFT 0
-#define BCHP_GIO_ODEN_LO_oden_DEFAULT 0x00000000
-
-/***************************************************************************
- *DATA_LO - GENERAL PURPOSE I/O DATA FOR GPIO[31:0]
- ***************************************************************************/
-/* GIO :: DATA_LO :: data [31:00] */
-#define BCHP_GIO_DATA_LO_data_MASK 0xffffffff
-#define BCHP_GIO_DATA_LO_data_SHIFT 0
-#define BCHP_GIO_DATA_LO_data_DEFAULT 0x00000000
-
-/***************************************************************************
- *IODIR_LO - GENERAL PURPOSE I/O DIRECTION FOR GPIO[31:0]
- ***************************************************************************/
-/* GIO :: IODIR_LO :: iodir [31:00] */
-#define BCHP_GIO_IODIR_LO_iodir_MASK 0xffffffff
-#define BCHP_GIO_IODIR_LO_iodir_SHIFT 0
-#define BCHP_GIO_IODIR_LO_iodir_DEFAULT 0xffffffff
-
-/***************************************************************************
- *EC_LO - GENERAL PURPOSE I/O EDGE CONFIGURATION FOR GPIO[31:0]
- ***************************************************************************/
-/* GIO :: EC_LO :: edge_config [31:00] */
-#define BCHP_GIO_EC_LO_edge_config_MASK 0xffffffff
-#define BCHP_GIO_EC_LO_edge_config_SHIFT 0
-#define BCHP_GIO_EC_LO_edge_config_DEFAULT 0x00000000
-
-/***************************************************************************
- *EI_LO - GENERAL PURPOSE I/O EDGE INSENSITIVE FOR GPIO[31:0]
- ***************************************************************************/
-/* GIO :: EI_LO :: edge_insensitive [31:00] */
-#define BCHP_GIO_EI_LO_edge_insensitive_MASK 0xffffffff
-#define BCHP_GIO_EI_LO_edge_insensitive_SHIFT 0
-#define BCHP_GIO_EI_LO_edge_insensitive_DEFAULT 0x00000000
-
-/***************************************************************************
- *MASK_LO - GENERAL PURPOSE I/O INTERRUPT MASK FOR GPIO[31:0]
- ***************************************************************************/
-/* GIO :: MASK_LO :: irq_mask [31:00] */
-#define BCHP_GIO_MASK_LO_irq_mask_MASK 0xffffffff
-#define BCHP_GIO_MASK_LO_irq_mask_SHIFT 0
-#define BCHP_GIO_MASK_LO_irq_mask_DEFAULT 0x00000000
-
-/***************************************************************************
- *LEVEL_LO - GENERAL PURPOSE I/O INTERRUPT TYPE FOR GPIO[31:0]
- ***************************************************************************/
-/* GIO :: LEVEL_LO :: level [31:00] */
-#define BCHP_GIO_LEVEL_LO_level_MASK 0xffffffff
-#define BCHP_GIO_LEVEL_LO_level_SHIFT 0
-#define BCHP_GIO_LEVEL_LO_level_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_LO - GENERAL PURPOSE I/O INTERRUPT STATUS FOR GPIO[31:0]
- ***************************************************************************/
-/* GIO :: STAT_LO :: irq_status [31:00] */
-#define BCHP_GIO_STAT_LO_irq_status_MASK 0xffffffff
-#define BCHP_GIO_STAT_LO_irq_status_SHIFT 0
-#define BCHP_GIO_STAT_LO_irq_status_DEFAULT 0x00000000
-
-/***************************************************************************
- *ODEN_HI - GENERAL PURPOSE I/O OPEN DRAIN ENABLE FOR GPIO[63:32]
- ***************************************************************************/
-/* GIO :: ODEN_HI :: oden [31:00] */
-#define BCHP_GIO_ODEN_HI_oden_MASK 0xffffffff
-#define BCHP_GIO_ODEN_HI_oden_SHIFT 0
-#define BCHP_GIO_ODEN_HI_oden_DEFAULT 0x00000000
-
-/***************************************************************************
- *DATA_HI - GENERAL PURPOSE I/O DATA FOR GPIO[63:32]
- ***************************************************************************/
-/* GIO :: DATA_HI :: data [31:00] */
-#define BCHP_GIO_DATA_HI_data_MASK 0xffffffff
-#define BCHP_GIO_DATA_HI_data_SHIFT 0
-#define BCHP_GIO_DATA_HI_data_DEFAULT 0x00000000
-
-/***************************************************************************
- *IODIR_HI - GENERAL PURPOSE I/O DIRECTION FOR GPIO[63:32]
- ***************************************************************************/
-/* GIO :: IODIR_HI :: iodir [31:00] */
-#define BCHP_GIO_IODIR_HI_iodir_MASK 0xffffffff
-#define BCHP_GIO_IODIR_HI_iodir_SHIFT 0
-#define BCHP_GIO_IODIR_HI_iodir_DEFAULT 0xffffffff
-
-/***************************************************************************
- *EC_HI - GENERAL PURPOSE I/O EDGE CONFIGURATION FOR GPIO[63:32]
- ***************************************************************************/
-/* GIO :: EC_HI :: edge_config [31:00] */
-#define BCHP_GIO_EC_HI_edge_config_MASK 0xffffffff
-#define BCHP_GIO_EC_HI_edge_config_SHIFT 0
-#define BCHP_GIO_EC_HI_edge_config_DEFAULT 0x00000000
-
-/***************************************************************************
- *EI_HI - GENERAL PURPOSE I/O EDGE INSENSITIVE FOR GPIO[63:32]
- ***************************************************************************/
-/* GIO :: EI_HI :: edge_insensitive [31:00] */
-#define BCHP_GIO_EI_HI_edge_insensitive_MASK 0xffffffff
-#define BCHP_GIO_EI_HI_edge_insensitive_SHIFT 0
-#define BCHP_GIO_EI_HI_edge_insensitive_DEFAULT 0x00000000
-
-/***************************************************************************
- *MASK_HI - GENERAL PURPOSE I/O INTERRUPT MASK FOR GPIO[63:32]
- ***************************************************************************/
-/* GIO :: MASK_HI :: irq_mask [31:00] */
-#define BCHP_GIO_MASK_HI_irq_mask_MASK 0xffffffff
-#define BCHP_GIO_MASK_HI_irq_mask_SHIFT 0
-#define BCHP_GIO_MASK_HI_irq_mask_DEFAULT 0x00000000
-
-/***************************************************************************
- *LEVEL_HI - GENERAL PURPOSE I/O INTERRUPT TYPE FOR GPIO[63:32]
- ***************************************************************************/
-/* GIO :: LEVEL_HI :: level [31:00] */
-#define BCHP_GIO_LEVEL_HI_level_MASK 0xffffffff
-#define BCHP_GIO_LEVEL_HI_level_SHIFT 0
-#define BCHP_GIO_LEVEL_HI_level_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_HI - GENERAL PURPOSE I/O INTERRUPT STATUS FOR GPIO[63:32]
- ***************************************************************************/
-/* GIO :: STAT_HI :: irq_status [31:00] */
-#define BCHP_GIO_STAT_HI_irq_status_MASK 0xffffffff
-#define BCHP_GIO_STAT_HI_irq_status_SHIFT 0
-#define BCHP_GIO_STAT_HI_irq_status_DEFAULT 0x00000000
-
-/***************************************************************************
- *ODEN_EXT_HI - GENERAL PURPOSE I/O OPEN DRAIN ENABLE FOR GPIO[95:64]
- ***************************************************************************/
-/* GIO :: ODEN_EXT_HI :: oden [31:00] */
-#define BCHP_GIO_ODEN_EXT_HI_oden_MASK 0xffffffff
-#define BCHP_GIO_ODEN_EXT_HI_oden_SHIFT 0
-#define BCHP_GIO_ODEN_EXT_HI_oden_DEFAULT 0x00000000
-
-/***************************************************************************
- *DATA_EXT_HI - GENERAL PURPOSE I/O DATA FOR GPIO[95:64]
- ***************************************************************************/
-/* GIO :: DATA_EXT_HI :: data [31:00] */
-#define BCHP_GIO_DATA_EXT_HI_data_MASK 0xffffffff
-#define BCHP_GIO_DATA_EXT_HI_data_SHIFT 0
-#define BCHP_GIO_DATA_EXT_HI_data_DEFAULT 0x00000000
-
-/***************************************************************************
- *IODIR_EXT_HI - GENERAL PURPOSE I/O DIRECTION FOR GPIO[95:64]
- ***************************************************************************/
-/* GIO :: IODIR_EXT_HI :: iodir [31:00] */
-#define BCHP_GIO_IODIR_EXT_HI_iodir_MASK 0xffffffff
-#define BCHP_GIO_IODIR_EXT_HI_iodir_SHIFT 0
-#define BCHP_GIO_IODIR_EXT_HI_iodir_DEFAULT 0xffffffff
-
-/***************************************************************************
- *EC_EXT_HI - GENERAL PURPOSE I/O EDGE CONFIGURATION FOR GPIO[95:64]
- ***************************************************************************/
-/* GIO :: EC_EXT_HI :: edge_config [31:00] */
-#define BCHP_GIO_EC_EXT_HI_edge_config_MASK 0xffffffff
-#define BCHP_GIO_EC_EXT_HI_edge_config_SHIFT 0
-#define BCHP_GIO_EC_EXT_HI_edge_config_DEFAULT 0x00000000
-
-/***************************************************************************
- *EI_EXT_HI - GENERAL PURPOSE I/O EDGE INSENSITIVE FOR GPIO[95:64]
- ***************************************************************************/
-/* GIO :: EI_EXT_HI :: edge_insensitive [31:00] */
-#define BCHP_GIO_EI_EXT_HI_edge_insensitive_MASK 0xffffffff
-#define BCHP_GIO_EI_EXT_HI_edge_insensitive_SHIFT 0
-#define BCHP_GIO_EI_EXT_HI_edge_insensitive_DEFAULT 0x00000000
-
-/***************************************************************************
- *MASK_EXT_HI - GENERAL PURPOSE I/O INTERRUPT MASK FOR GPIO[95:64]
- ***************************************************************************/
-/* GIO :: MASK_EXT_HI :: irq_mask [31:00] */
-#define BCHP_GIO_MASK_EXT_HI_irq_mask_MASK 0xffffffff
-#define BCHP_GIO_MASK_EXT_HI_irq_mask_SHIFT 0
-#define BCHP_GIO_MASK_EXT_HI_irq_mask_DEFAULT 0x00000000
-
-/***************************************************************************
- *LEVEL_EXT_HI - GENERAL PURPOSE I/O INTERRUPT TYPE FOR GPIO[95:64]
- ***************************************************************************/
-/* GIO :: LEVEL_EXT_HI :: level [31:00] */
-#define BCHP_GIO_LEVEL_EXT_HI_level_MASK 0xffffffff
-#define BCHP_GIO_LEVEL_EXT_HI_level_SHIFT 0
-#define BCHP_GIO_LEVEL_EXT_HI_level_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_EXT_HI - GENERAL PURPOSE I/O INTERRUPT STATUS FOR GPIO[95:64]
- ***************************************************************************/
-/* GIO :: STAT_EXT_HI :: irq_status [31:00] */
-#define BCHP_GIO_STAT_EXT_HI_irq_status_MASK 0xffffffff
-#define BCHP_GIO_STAT_EXT_HI_irq_status_SHIFT 0
-#define BCHP_GIO_STAT_EXT_HI_irq_status_DEFAULT 0x00000000
-
-/***************************************************************************
- *ODEN_EXT2 - GENERAL PURPOSE I/O OPEN DRAIN ENABLE FOR GPIO[127:96]
- ***************************************************************************/
-/* GIO :: ODEN_EXT2 :: oden [31:00] */
-#define BCHP_GIO_ODEN_EXT2_oden_MASK 0xffffffff
-#define BCHP_GIO_ODEN_EXT2_oden_SHIFT 0
-#define BCHP_GIO_ODEN_EXT2_oden_DEFAULT 0x00000000
-
-/***************************************************************************
- *DATA_EXT2 - GENERAL PURPOSE I/O DATA FOR GPIO[127:96]
- ***************************************************************************/
-/* GIO :: DATA_EXT2 :: data [31:00] */
-#define BCHP_GIO_DATA_EXT2_data_MASK 0xffffffff
-#define BCHP_GIO_DATA_EXT2_data_SHIFT 0
-#define BCHP_GIO_DATA_EXT2_data_DEFAULT 0x00000000
-
-/***************************************************************************
- *IODIR_EXT2 - GENERAL PURPOSE I/O DIRECTION FOR GPIO[127:96]
- ***************************************************************************/
-/* GIO :: IODIR_EXT2 :: iodir [31:00] */
-#define BCHP_GIO_IODIR_EXT2_iodir_MASK 0xffffffff
-#define BCHP_GIO_IODIR_EXT2_iodir_SHIFT 0
-#define BCHP_GIO_IODIR_EXT2_iodir_DEFAULT 0x00000001
-
-/***************************************************************************
- *EC_EXT2 - GENERAL PURPOSE I/O EDGE CONFIGURATION FOR GPIO[127:96]
- ***************************************************************************/
-/* GIO :: EC_EXT2 :: edge_config [31:00] */
-#define BCHP_GIO_EC_EXT2_edge_config_MASK 0xffffffff
-#define BCHP_GIO_EC_EXT2_edge_config_SHIFT 0
-#define BCHP_GIO_EC_EXT2_edge_config_DEFAULT 0x00000000
-
-/***************************************************************************
- *EI_EXT2 - GENERAL PURPOSE I/O EDGE INSENSITIVE FOR GPIO[127:96]
- ***************************************************************************/
-/* GIO :: EI_EXT2 :: edge_insensitive [31:00] */
-#define BCHP_GIO_EI_EXT2_edge_insensitive_MASK 0xffffffff
-#define BCHP_GIO_EI_EXT2_edge_insensitive_SHIFT 0
-#define BCHP_GIO_EI_EXT2_edge_insensitive_DEFAULT 0x00000000
-
-/***************************************************************************
- *MASK_EXT2 - GENERAL PURPOSE I/O INTERRUPT MASK FOR GPIO[127:96]
- ***************************************************************************/
-/* GIO :: MASK_EXT2 :: irq_mask [31:00] */
-#define BCHP_GIO_MASK_EXT2_irq_mask_MASK 0xffffffff
-#define BCHP_GIO_MASK_EXT2_irq_mask_SHIFT 0
-#define BCHP_GIO_MASK_EXT2_irq_mask_DEFAULT 0x00000000
-
-/***************************************************************************
- *LEVEL_EXT2 - GENERAL PURPOSE I/O INTERRUPT TYPE FOR GPIO[127:96]
- ***************************************************************************/
-/* GIO :: LEVEL_EXT2 :: level [31:00] */
-#define BCHP_GIO_LEVEL_EXT2_level_MASK 0xffffffff
-#define BCHP_GIO_LEVEL_EXT2_level_SHIFT 0
-#define BCHP_GIO_LEVEL_EXT2_level_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_EXT2 - GENERAL PURPOSE I/O INTERRUPT STATUS FOR GPIO[127:96]
- ***************************************************************************/
-/* GIO :: STAT_EXT2 :: irq_status [31:00] */
-#define BCHP_GIO_STAT_EXT2_irq_status_MASK 0xffffffff
-#define BCHP_GIO_STAT_EXT2_irq_status_SHIFT 0
-#define BCHP_GIO_STAT_EXT2_irq_status_DEFAULT 0x00000000
-
-/***************************************************************************
- *ODEN_EXT3 - GENERAL PURPOSE I/O OPEN DRAIN ENABLE FOR GPIO[137:128]
- ***************************************************************************/
-/* GIO :: ODEN_EXT3 :: reserved0 [31:10] */
-#define BCHP_GIO_ODEN_EXT3_reserved0_MASK 0xfffffc00
-#define BCHP_GIO_ODEN_EXT3_reserved0_SHIFT 10
-
-/* GIO :: ODEN_EXT3 :: oden [09:00] */
-#define BCHP_GIO_ODEN_EXT3_oden_MASK 0x000003ff
-#define BCHP_GIO_ODEN_EXT3_oden_SHIFT 0
-#define BCHP_GIO_ODEN_EXT3_oden_DEFAULT 0x00000000
-
-/***************************************************************************
- *DATA_EXT3 - GENERAL PURPOSE I/O DATA FOR GPIO[137:128]
- ***************************************************************************/
-/* GIO :: DATA_EXT3 :: reserved0 [31:10] */
-#define BCHP_GIO_DATA_EXT3_reserved0_MASK 0xfffffc00
-#define BCHP_GIO_DATA_EXT3_reserved0_SHIFT 10
-
-/* GIO :: DATA_EXT3 :: data [09:00] */
-#define BCHP_GIO_DATA_EXT3_data_MASK 0x000003ff
-#define BCHP_GIO_DATA_EXT3_data_SHIFT 0
-#define BCHP_GIO_DATA_EXT3_data_DEFAULT 0x00000000
-
-/***************************************************************************
- *IODIR_EXT3 - GENERAL PURPOSE I/O DIRECTION FOR GPIO[137:128]
- ***************************************************************************/
-/* GIO :: IODIR_EXT3 :: reserved0 [31:10] */
-#define BCHP_GIO_IODIR_EXT3_reserved0_MASK 0xfffffc00
-#define BCHP_GIO_IODIR_EXT3_reserved0_SHIFT 10
-
-/* GIO :: IODIR_EXT3 :: iodir [09:00] */
-#define BCHP_GIO_IODIR_EXT3_iodir_MASK 0x000003ff
-#define BCHP_GIO_IODIR_EXT3_iodir_SHIFT 0
-#define BCHP_GIO_IODIR_EXT3_iodir_DEFAULT 0x00000001
-
-/***************************************************************************
- *EC_EXT3 - GENERAL PURPOSE I/O EDGE CONFIGURATION FOR GPIO[137:128]
- ***************************************************************************/
-/* GIO :: EC_EXT3 :: reserved0 [31:10] */
-#define BCHP_GIO_EC_EXT3_reserved0_MASK 0xfffffc00
-#define BCHP_GIO_EC_EXT3_reserved0_SHIFT 10
-
-/* GIO :: EC_EXT3 :: edge_config [09:00] */
-#define BCHP_GIO_EC_EXT3_edge_config_MASK 0x000003ff
-#define BCHP_GIO_EC_EXT3_edge_config_SHIFT 0
-#define BCHP_GIO_EC_EXT3_edge_config_DEFAULT 0x00000000
-
-/***************************************************************************
- *EI_EXT3 - GENERAL PURPOSE I/O EDGE INSENSITIVE FOR GPIO[137:128]
- ***************************************************************************/
-/* GIO :: EI_EXT3 :: reserved0 [31:10] */
-#define BCHP_GIO_EI_EXT3_reserved0_MASK 0xfffffc00
-#define BCHP_GIO_EI_EXT3_reserved0_SHIFT 10
-
-/* GIO :: EI_EXT3 :: edge_insensitive [09:00] */
-#define BCHP_GIO_EI_EXT3_edge_insensitive_MASK 0x000003ff
-#define BCHP_GIO_EI_EXT3_edge_insensitive_SHIFT 0
-#define BCHP_GIO_EI_EXT3_edge_insensitive_DEFAULT 0x00000000
-
-/***************************************************************************
- *MASK_EXT3 - GENERAL PURPOSE I/O INTERRUPT MASK FOR GPIO[137:128]
- ***************************************************************************/
-/* GIO :: MASK_EXT3 :: reserved0 [31:10] */
-#define BCHP_GIO_MASK_EXT3_reserved0_MASK 0xfffffc00
-#define BCHP_GIO_MASK_EXT3_reserved0_SHIFT 10
-
-/* GIO :: MASK_EXT3 :: irq_mask [09:00] */
-#define BCHP_GIO_MASK_EXT3_irq_mask_MASK 0x000003ff
-#define BCHP_GIO_MASK_EXT3_irq_mask_SHIFT 0
-#define BCHP_GIO_MASK_EXT3_irq_mask_DEFAULT 0x00000000
-
-/***************************************************************************
- *LEVEL_EXT3 - GENERAL PURPOSE I/O INTERRUPT TYPE FOR GPIO[137:128]
- ***************************************************************************/
-/* GIO :: LEVEL_EXT3 :: reserved0 [31:10] */
-#define BCHP_GIO_LEVEL_EXT3_reserved0_MASK 0xfffffc00
-#define BCHP_GIO_LEVEL_EXT3_reserved0_SHIFT 10
-
-/* GIO :: LEVEL_EXT3 :: level [09:00] */
-#define BCHP_GIO_LEVEL_EXT3_level_MASK 0x000003ff
-#define BCHP_GIO_LEVEL_EXT3_level_SHIFT 0
-#define BCHP_GIO_LEVEL_EXT3_level_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_EXT3 - GENERAL PURPOSE I/O INTERRUPT STATUS FOR GPIO[137:128]
- ***************************************************************************/
-/* GIO :: STAT_EXT3 :: reserved0 [31:10] */
-#define BCHP_GIO_STAT_EXT3_reserved0_MASK 0xfffffc00
-#define BCHP_GIO_STAT_EXT3_reserved0_SHIFT 10
-
-/* GIO :: STAT_EXT3 :: irq_status [09:00] */
-#define BCHP_GIO_STAT_EXT3_irq_status_MASK 0x000003ff
-#define BCHP_GIO_STAT_EXT3_irq_status_SHIFT 0
-#define BCHP_GIO_STAT_EXT3_irq_status_DEFAULT 0x00000000
-
-/***************************************************************************
- *ODEN_EXT - GENERAL PURPOSE I/O OPEN DRAIN ENABLE FOR AON_SGPIO[3:0] and SGPIO[5:0]
- ***************************************************************************/
-/* GIO :: ODEN_EXT :: reserved0 [31:10] */
-#define BCHP_GIO_ODEN_EXT_reserved0_MASK 0xfffffc00
-#define BCHP_GIO_ODEN_EXT_reserved0_SHIFT 10
-
-/* GIO :: ODEN_EXT :: oden [09:00] */
-#define BCHP_GIO_ODEN_EXT_oden_MASK 0x000003ff
-#define BCHP_GIO_ODEN_EXT_oden_SHIFT 0
-#define BCHP_GIO_ODEN_EXT_oden_DEFAULT 0x00000000
-
-/***************************************************************************
- *DATA_EXT - GENERAL PURPOSE I/O DATA FOR AON_SGPIO[3:0] and SGPIO[5:0]
- ***************************************************************************/
-/* GIO :: DATA_EXT :: reserved0 [31:10] */
-#define BCHP_GIO_DATA_EXT_reserved0_MASK 0xfffffc00
-#define BCHP_GIO_DATA_EXT_reserved0_SHIFT 10
-
-/* GIO :: DATA_EXT :: data [09:00] */
-#define BCHP_GIO_DATA_EXT_data_MASK 0x000003ff
-#define BCHP_GIO_DATA_EXT_data_SHIFT 0
-#define BCHP_GIO_DATA_EXT_data_DEFAULT 0x00000000
-
-/***************************************************************************
- *IODIR_EXT - GENERAL PURPOSE I/O DIRECTION FOR AON_SGPIO[3:0] and SGPIO[5:0]
- ***************************************************************************/
-/* GIO :: IODIR_EXT :: reserved0 [31:10] */
-#define BCHP_GIO_IODIR_EXT_reserved0_MASK 0xfffffc00
-#define BCHP_GIO_IODIR_EXT_reserved0_SHIFT 10
-
-/* GIO :: IODIR_EXT :: iodir [09:00] */
-#define BCHP_GIO_IODIR_EXT_iodir_MASK 0x000003ff
-#define BCHP_GIO_IODIR_EXT_iodir_SHIFT 0
-#define BCHP_GIO_IODIR_EXT_iodir_DEFAULT 0x000003ff
-
-/***************************************************************************
- *EC_EXT - GENERAL PURPOSE I/O EDGE CONFIGURATION FOR AON_SGPIO[3:0] and SGPIO[5:0]
- ***************************************************************************/
-/* GIO :: EC_EXT :: reserved0 [31:10] */
-#define BCHP_GIO_EC_EXT_reserved0_MASK 0xfffffc00
-#define BCHP_GIO_EC_EXT_reserved0_SHIFT 10
-
-/* GIO :: EC_EXT :: edge_config [09:00] */
-#define BCHP_GIO_EC_EXT_edge_config_MASK 0x000003ff
-#define BCHP_GIO_EC_EXT_edge_config_SHIFT 0
-#define BCHP_GIO_EC_EXT_edge_config_DEFAULT 0x00000000
-
-/***************************************************************************
- *EI_EXT - GENERAL PURPOSE I/O EDGE INSENSITIVE FOR AON_SGPIO[3:0] and SGPIO[5:0]
- ***************************************************************************/
-/* GIO :: EI_EXT :: reserved0 [31:10] */
-#define BCHP_GIO_EI_EXT_reserved0_MASK 0xfffffc00
-#define BCHP_GIO_EI_EXT_reserved0_SHIFT 10
-
-/* GIO :: EI_EXT :: edge_insensitive [09:00] */
-#define BCHP_GIO_EI_EXT_edge_insensitive_MASK 0x000003ff
-#define BCHP_GIO_EI_EXT_edge_insensitive_SHIFT 0
-#define BCHP_GIO_EI_EXT_edge_insensitive_DEFAULT 0x00000000
-
-/***************************************************************************
- *MASK_EXT - GENERAL PURPOSE I/O INTERRUPT MASK FOR AON_SGPIO[3:0] and SGPIO[5:0]
- ***************************************************************************/
-/* GIO :: MASK_EXT :: reserved0 [31:10] */
-#define BCHP_GIO_MASK_EXT_reserved0_MASK 0xfffffc00
-#define BCHP_GIO_MASK_EXT_reserved0_SHIFT 10
-
-/* GIO :: MASK_EXT :: irq_mask [09:00] */
-#define BCHP_GIO_MASK_EXT_irq_mask_MASK 0x000003ff
-#define BCHP_GIO_MASK_EXT_irq_mask_SHIFT 0
-#define BCHP_GIO_MASK_EXT_irq_mask_DEFAULT 0x00000000
-
-/***************************************************************************
- *LEVEL_EXT - GENERAL PURPOSE I/O INTERRUPT TYPE FOR AON_SGPIO[3:0] and SGPIO[5:0]
- ***************************************************************************/
-/* GIO :: LEVEL_EXT :: reserved0 [31:10] */
-#define BCHP_GIO_LEVEL_EXT_reserved0_MASK 0xfffffc00
-#define BCHP_GIO_LEVEL_EXT_reserved0_SHIFT 10
-
-/* GIO :: LEVEL_EXT :: level [09:00] */
-#define BCHP_GIO_LEVEL_EXT_level_MASK 0x000003ff
-#define BCHP_GIO_LEVEL_EXT_level_SHIFT 0
-#define BCHP_GIO_LEVEL_EXT_level_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_EXT - GENERAL PURPOSE I/O INTERRUPT STATUS FOR AON_SGPIO[3:0] and SGPIO[5:0]
- ***************************************************************************/
-/* GIO :: STAT_EXT :: reserved0 [31:10] */
-#define BCHP_GIO_STAT_EXT_reserved0_MASK 0xfffffc00
-#define BCHP_GIO_STAT_EXT_reserved0_SHIFT 10
-
-/* GIO :: STAT_EXT :: irq_status [09:00] */
-#define BCHP_GIO_STAT_EXT_irq_status_MASK 0x000003ff
-#define BCHP_GIO_STAT_EXT_irq_status_SHIFT 0
-#define BCHP_GIO_STAT_EXT_irq_status_DEFAULT 0x00000000
-
-#endif /* #ifndef BCHP_GIO_H__ */
-
-/* End of File */
diff --git a/include/linux/brcmstb/7366b0/bchp_gio_aon.h b/include/linux/brcmstb/7366b0/bchp_gio_aon.h
deleted file mode 100644
index 19e7c80..0000000
--- a/include/linux/brcmstb/7366b0/bchp_gio_aon.h
+++ /dev/null
@@ -1,258 +0,0 @@
-/***************************************************************************
- * Copyright (c) 1999-2014, Broadcom Corporation
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
- *
- * Module Description:
- * DO NOT EDIT THIS FILE DIRECTLY
- *
- * This module was generated magically with RDB from a source description
- * file. You must edit the source file for changes to be made to this file.
- *
- *
- * Date: Generated on Thu Apr 24 03:08:56 2014
- * Full Compile MD5 Checksum 1af2c2cf28828ece5496e1312aac0166
- * (minus title and desc)
- * MD5 Checksum 3203ffce85e3fc9a10f84123e54057b0
- *
- * Compiled with: RDB Utility combo_header.pl
- * RDB Parser 3.0
- * unknown unknown
- * Perl Interpreter 5.008008
- * Operating System linux
- *
- * Revision History:
- *
- * $brcm_Log: $
- *
- ***************************************************************************/
-
-#ifndef BCHP_GIO_AON_H__
-#define BCHP_GIO_AON_H__
-
-/***************************************************************************
- *GIO_AON - GPIO
- ***************************************************************************/
-#define BCHP_GIO_AON_ODEN_LO 0x00417300 /* GENERAL PURPOSE I/O OPEN DRAIN ENABLE FOR AON_GPIO[20:0] */
-#define BCHP_GIO_AON_DATA_LO 0x00417304 /* GENERAL PURPOSE I/O DATA FOR AON_GPIO[20:0] */
-#define BCHP_GIO_AON_IODIR_LO 0x00417308 /* GENERAL PURPOSE I/O DIRECTION FOR AON_GPIO[20:0] */
-#define BCHP_GIO_AON_EC_LO 0x0041730c /* GENERAL PURPOSE I/O EDGE CONFIGURATION FOR AON_GPIO[20:0] */
-#define BCHP_GIO_AON_EI_LO 0x00417310 /* GENERAL PURPOSE I/O EDGE INSENSITIVE FOR AON_GPIO[20:0] */
-#define BCHP_GIO_AON_MASK_LO 0x00417314 /* GENERAL PURPOSE I/O INTERRUPT MASK FOR AON_GPIO[20:0] */
-#define BCHP_GIO_AON_LEVEL_LO 0x00417318 /* GENERAL PURPOSE I/O INTERRUPT TYPE FOR AON_GPIO[20:0] */
-#define BCHP_GIO_AON_STAT_LO 0x0041731c /* GENERAL PURPOSE I/O INTERRUPT STATUS FOR AON_GPIO[20:0] */
-#define BCHP_GIO_AON_ODEN_EXT 0x00417320 /* GENERAL PURPOSE I/O OPEN DRAIN ENABLE FOR AON_SGPIO[7:4] */
-#define BCHP_GIO_AON_DATA_EXT 0x00417324 /* GENERAL PURPOSE I/O DATA FOR AON_SGPIO[7:4] */
-#define BCHP_GIO_AON_IODIR_EXT 0x00417328 /* GENERAL PURPOSE I/O DIRECTION FOR AON_SGPIO[7:4] */
-#define BCHP_GIO_AON_EC_EXT 0x0041732c /* GENERAL PURPOSE I/O EDGE CONFIGURATION FOR AON_SGPIO[7:4] */
-#define BCHP_GIO_AON_EI_EXT 0x00417330 /* GENERAL PURPOSE I/O EDGE INSENSITIVE FOR AON_SGPIO[7:4] */
-#define BCHP_GIO_AON_MASK_EXT 0x00417334 /* GENERAL PURPOSE I/O INTERRUPT MASK FOR AON_SGPIO[7:4] */
-#define BCHP_GIO_AON_LEVEL_EXT 0x00417338 /* GENERAL PURPOSE I/O INTERRUPT TYPE FOR AON_SGPIO[7:4] */
-#define BCHP_GIO_AON_STAT_EXT 0x0041733c /* GENERAL PURPOSE I/O INTERRUPT STATUS FOR AON_SGPIO[7:4] */
-
-/***************************************************************************
- *ODEN_LO - GENERAL PURPOSE I/O OPEN DRAIN ENABLE FOR AON_GPIO[20:0]
- ***************************************************************************/
-/* GIO_AON :: ODEN_LO :: reserved0 [31:21] */
-#define BCHP_GIO_AON_ODEN_LO_reserved0_MASK 0xffe00000
-#define BCHP_GIO_AON_ODEN_LO_reserved0_SHIFT 21
-
-/* GIO_AON :: ODEN_LO :: oden [20:00] */
-#define BCHP_GIO_AON_ODEN_LO_oden_MASK 0x001fffff
-#define BCHP_GIO_AON_ODEN_LO_oden_SHIFT 0
-#define BCHP_GIO_AON_ODEN_LO_oden_DEFAULT 0x00000000
-
-/***************************************************************************
- *DATA_LO - GENERAL PURPOSE I/O DATA FOR AON_GPIO[20:0]
- ***************************************************************************/
-/* GIO_AON :: DATA_LO :: reserved0 [31:21] */
-#define BCHP_GIO_AON_DATA_LO_reserved0_MASK 0xffe00000
-#define BCHP_GIO_AON_DATA_LO_reserved0_SHIFT 21
-
-/* GIO_AON :: DATA_LO :: data [20:00] */
-#define BCHP_GIO_AON_DATA_LO_data_MASK 0x001fffff
-#define BCHP_GIO_AON_DATA_LO_data_SHIFT 0
-#define BCHP_GIO_AON_DATA_LO_data_DEFAULT 0x00000000
-
-/***************************************************************************
- *IODIR_LO - GENERAL PURPOSE I/O DIRECTION FOR AON_GPIO[20:0]
- ***************************************************************************/
-/* GIO_AON :: IODIR_LO :: reserved0 [31:21] */
-#define BCHP_GIO_AON_IODIR_LO_reserved0_MASK 0xffe00000
-#define BCHP_GIO_AON_IODIR_LO_reserved0_SHIFT 21
-
-/* GIO_AON :: IODIR_LO :: iodir [20:00] */
-#define BCHP_GIO_AON_IODIR_LO_iodir_MASK 0x001fffff
-#define BCHP_GIO_AON_IODIR_LO_iodir_SHIFT 0
-#define BCHP_GIO_AON_IODIR_LO_iodir_DEFAULT 0x00000001
-
-/***************************************************************************
- *EC_LO - GENERAL PURPOSE I/O EDGE CONFIGURATION FOR AON_GPIO[20:0]
- ***************************************************************************/
-/* GIO_AON :: EC_LO :: reserved0 [31:21] */
-#define BCHP_GIO_AON_EC_LO_reserved0_MASK 0xffe00000
-#define BCHP_GIO_AON_EC_LO_reserved0_SHIFT 21
-
-/* GIO_AON :: EC_LO :: edge_config [20:00] */
-#define BCHP_GIO_AON_EC_LO_edge_config_MASK 0x001fffff
-#define BCHP_GIO_AON_EC_LO_edge_config_SHIFT 0
-#define BCHP_GIO_AON_EC_LO_edge_config_DEFAULT 0x00000000
-
-/***************************************************************************
- *EI_LO - GENERAL PURPOSE I/O EDGE INSENSITIVE FOR AON_GPIO[20:0]
- ***************************************************************************/
-/* GIO_AON :: EI_LO :: reserved0 [31:21] */
-#define BCHP_GIO_AON_EI_LO_reserved0_MASK 0xffe00000
-#define BCHP_GIO_AON_EI_LO_reserved0_SHIFT 21
-
-/* GIO_AON :: EI_LO :: edge_insensitive [20:00] */
-#define BCHP_GIO_AON_EI_LO_edge_insensitive_MASK 0x001fffff
-#define BCHP_GIO_AON_EI_LO_edge_insensitive_SHIFT 0
-#define BCHP_GIO_AON_EI_LO_edge_insensitive_DEFAULT 0x00000000
-
-/***************************************************************************
- *MASK_LO - GENERAL PURPOSE I/O INTERRUPT MASK FOR AON_GPIO[20:0]
- ***************************************************************************/
-/* GIO_AON :: MASK_LO :: reserved0 [31:21] */
-#define BCHP_GIO_AON_MASK_LO_reserved0_MASK 0xffe00000
-#define BCHP_GIO_AON_MASK_LO_reserved0_SHIFT 21
-
-/* GIO_AON :: MASK_LO :: irq_mask [20:00] */
-#define BCHP_GIO_AON_MASK_LO_irq_mask_MASK 0x001fffff
-#define BCHP_GIO_AON_MASK_LO_irq_mask_SHIFT 0
-#define BCHP_GIO_AON_MASK_LO_irq_mask_DEFAULT 0x00000000
-
-/***************************************************************************
- *LEVEL_LO - GENERAL PURPOSE I/O INTERRUPT TYPE FOR AON_GPIO[20:0]
- ***************************************************************************/
-/* GIO_AON :: LEVEL_LO :: reserved0 [31:21] */
-#define BCHP_GIO_AON_LEVEL_LO_reserved0_MASK 0xffe00000
-#define BCHP_GIO_AON_LEVEL_LO_reserved0_SHIFT 21
-
-/* GIO_AON :: LEVEL_LO :: level [20:00] */
-#define BCHP_GIO_AON_LEVEL_LO_level_MASK 0x001fffff
-#define BCHP_GIO_AON_LEVEL_LO_level_SHIFT 0
-#define BCHP_GIO_AON_LEVEL_LO_level_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_LO - GENERAL PURPOSE I/O INTERRUPT STATUS FOR AON_GPIO[20:0]
- ***************************************************************************/
-/* GIO_AON :: STAT_LO :: reserved0 [31:21] */
-#define BCHP_GIO_AON_STAT_LO_reserved0_MASK 0xffe00000
-#define BCHP_GIO_AON_STAT_LO_reserved0_SHIFT 21
-
-/* GIO_AON :: STAT_LO :: irq_status [20:00] */
-#define BCHP_GIO_AON_STAT_LO_irq_status_MASK 0x001fffff
-#define BCHP_GIO_AON_STAT_LO_irq_status_SHIFT 0
-#define BCHP_GIO_AON_STAT_LO_irq_status_DEFAULT 0x00000000
-
-/***************************************************************************
- *ODEN_EXT - GENERAL PURPOSE I/O OPEN DRAIN ENABLE FOR AON_SGPIO[7:4]
- ***************************************************************************/
-/* GIO_AON :: ODEN_EXT :: reserved0 [31:04] */
-#define BCHP_GIO_AON_ODEN_EXT_reserved0_MASK 0xfffffff0
-#define BCHP_GIO_AON_ODEN_EXT_reserved0_SHIFT 4
-
-/* GIO_AON :: ODEN_EXT :: oden [03:00] */
-#define BCHP_GIO_AON_ODEN_EXT_oden_MASK 0x0000000f
-#define BCHP_GIO_AON_ODEN_EXT_oden_SHIFT 0
-#define BCHP_GIO_AON_ODEN_EXT_oden_DEFAULT 0x00000000
-
-/***************************************************************************
- *DATA_EXT - GENERAL PURPOSE I/O DATA FOR AON_SGPIO[7:4]
- ***************************************************************************/
-/* GIO_AON :: DATA_EXT :: reserved0 [31:04] */
-#define BCHP_GIO_AON_DATA_EXT_reserved0_MASK 0xfffffff0
-#define BCHP_GIO_AON_DATA_EXT_reserved0_SHIFT 4
-
-/* GIO_AON :: DATA_EXT :: data [03:00] */
-#define BCHP_GIO_AON_DATA_EXT_data_MASK 0x0000000f
-#define BCHP_GIO_AON_DATA_EXT_data_SHIFT 0
-#define BCHP_GIO_AON_DATA_EXT_data_DEFAULT 0x00000000
-
-/***************************************************************************
- *IODIR_EXT - GENERAL PURPOSE I/O DIRECTION FOR AON_SGPIO[7:4]
- ***************************************************************************/
-/* GIO_AON :: IODIR_EXT :: reserved0 [31:04] */
-#define BCHP_GIO_AON_IODIR_EXT_reserved0_MASK 0xfffffff0
-#define BCHP_GIO_AON_IODIR_EXT_reserved0_SHIFT 4
-
-/* GIO_AON :: IODIR_EXT :: iodir [03:00] */
-#define BCHP_GIO_AON_IODIR_EXT_iodir_MASK 0x0000000f
-#define BCHP_GIO_AON_IODIR_EXT_iodir_SHIFT 0
-#define BCHP_GIO_AON_IODIR_EXT_iodir_DEFAULT 0x00000001
-
-/***************************************************************************
- *EC_EXT - GENERAL PURPOSE I/O EDGE CONFIGURATION FOR AON_SGPIO[7:4]
- ***************************************************************************/
-/* GIO_AON :: EC_EXT :: reserved0 [31:04] */
-#define BCHP_GIO_AON_EC_EXT_reserved0_MASK 0xfffffff0
-#define BCHP_GIO_AON_EC_EXT_reserved0_SHIFT 4
-
-/* GIO_AON :: EC_EXT :: edge_config [03:00] */
-#define BCHP_GIO_AON_EC_EXT_edge_config_MASK 0x0000000f
-#define BCHP_GIO_AON_EC_EXT_edge_config_SHIFT 0
-#define BCHP_GIO_AON_EC_EXT_edge_config_DEFAULT 0x00000000
-
-/***************************************************************************
- *EI_EXT - GENERAL PURPOSE I/O EDGE INSENSITIVE FOR AON_SGPIO[7:4]
- ***************************************************************************/
-/* GIO_AON :: EI_EXT :: reserved0 [31:04] */
-#define BCHP_GIO_AON_EI_EXT_reserved0_MASK 0xfffffff0
-#define BCHP_GIO_AON_EI_EXT_reserved0_SHIFT 4
-
-/* GIO_AON :: EI_EXT :: edge_insensitive [03:00] */
-#define BCHP_GIO_AON_EI_EXT_edge_insensitive_MASK 0x0000000f
-#define BCHP_GIO_AON_EI_EXT_edge_insensitive_SHIFT 0
-#define BCHP_GIO_AON_EI_EXT_edge_insensitive_DEFAULT 0x00000000
-
-/***************************************************************************
- *MASK_EXT - GENERAL PURPOSE I/O INTERRUPT MASK FOR AON_SGPIO[7:4]
- ***************************************************************************/
-/* GIO_AON :: MASK_EXT :: reserved0 [31:04] */
-#define BCHP_GIO_AON_MASK_EXT_reserved0_MASK 0xfffffff0
-#define BCHP_GIO_AON_MASK_EXT_reserved0_SHIFT 4
-
-/* GIO_AON :: MASK_EXT :: irq_mask [03:00] */
-#define BCHP_GIO_AON_MASK_EXT_irq_mask_MASK 0x0000000f
-#define BCHP_GIO_AON_MASK_EXT_irq_mask_SHIFT 0
-#define BCHP_GIO_AON_MASK_EXT_irq_mask_DEFAULT 0x00000000
-
-/***************************************************************************
- *LEVEL_EXT - GENERAL PURPOSE I/O INTERRUPT TYPE FOR AON_SGPIO[7:4]
- ***************************************************************************/
-/* GIO_AON :: LEVEL_EXT :: reserved0 [31:04] */
-#define BCHP_GIO_AON_LEVEL_EXT_reserved0_MASK 0xfffffff0
-#define BCHP_GIO_AON_LEVEL_EXT_reserved0_SHIFT 4
-
-/* GIO_AON :: LEVEL_EXT :: level [03:00] */
-#define BCHP_GIO_AON_LEVEL_EXT_level_MASK 0x0000000f
-#define BCHP_GIO_AON_LEVEL_EXT_level_SHIFT 0
-#define BCHP_GIO_AON_LEVEL_EXT_level_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_EXT - GENERAL PURPOSE I/O INTERRUPT STATUS FOR AON_SGPIO[7:4]
- ***************************************************************************/
-/* GIO_AON :: STAT_EXT :: reserved0 [31:04] */
-#define BCHP_GIO_AON_STAT_EXT_reserved0_MASK 0xfffffff0
-#define BCHP_GIO_AON_STAT_EXT_reserved0_SHIFT 4
-
-/* GIO_AON :: STAT_EXT :: irq_status [03:00] */
-#define BCHP_GIO_AON_STAT_EXT_irq_status_MASK 0x0000000f
-#define BCHP_GIO_AON_STAT_EXT_irq_status_SHIFT 0
-#define BCHP_GIO_AON_STAT_EXT_irq_status_DEFAULT 0x00000000
-
-#endif /* #ifndef BCHP_GIO_AON_H__ */
-
-/* End of File */
diff --git a/include/linux/brcmstb/7366b0/bchp_hif_continuation.h b/include/linux/brcmstb/7366b0/bchp_hif_continuation.h
deleted file mode 100644
index 296446d..0000000
--- a/include/linux/brcmstb/7366b0/bchp_hif_continuation.h
+++ /dev/null
@@ -1,114 +0,0 @@
-/***************************************************************************
- * Copyright (c) 1999-2013, Broadcom Corporation
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
- *
- * Module Description:
- * DO NOT EDIT THIS FILE DIRECTLY
- *
- * This module was generated magically with RDB from a source description
- * file. You must edit the source file for changes to be made to this file.
- *
- *
- * Date: Generated on Sat Apr 20 03:07:45 2013
- * MD5 Checksum d41d8cd98f00b204e9800998ecf8427e
- *
- * Compiled with: RDB Utility combo_header.pl
- * RDB Parser 3.0
- * unknown unknown
- * Perl Interpreter 5.008008
- * Operating System linux
- *
- * Revision History:
- *
- * $brcm_Log: $
- *
- ***************************************************************************/
-
-#ifndef BCHP_HIF_CONTINUATION_H__
-#define BCHP_HIF_CONTINUATION_H__
-
-/***************************************************************************
- *HIF_CONTINUATION - HIF Boot Continuation Registers
- ***************************************************************************/
-#define BCHP_HIF_CONTINUATION_STB_BOOT_HI_ADDR0 0x00462000 /* Higher 8-bit of HIF's Read-only STB Boot Continuation Address 0 Register */
-#define BCHP_HIF_CONTINUATION_STB_BOOT_ADDR0 0x00462004 /* Lower 32-bit of HIF's Read-only STB Boot Continuation Address 0 Register */
-#define BCHP_HIF_CONTINUATION_STB_BOOT_HI_ADDR1 0x00462008 /* Higher 8-bit of HIF's STB Boot Continuation Address 1 Register */
-#define BCHP_HIF_CONTINUATION_STB_BOOT_ADDR1 0x0046200c /* Lower 32-bit of HIF's STB Boot Continuation Address 1 Register */
-#define BCHP_HIF_CONTINUATION_WEB_BOOT_HI_ADDR0 0x004620f8 /* Higher 8-bit of HIF's WEB Boot Continuation Address 0 Register */
-#define BCHP_HIF_CONTINUATION_WEB_BOOT_ADDR0 0x004620fc /* Lower 32-bit of HIF's WEB Boot Continuation Address 0 Register */
-
-/***************************************************************************
- *STB_BOOT_HI_ADDR0 - Higher 8-bit of HIF's Read-only STB Boot Continuation Address 0 Register
- ***************************************************************************/
-/* HIF_CONTINUATION :: STB_BOOT_HI_ADDR0 :: reserved0 [31:08] */
-#define BCHP_HIF_CONTINUATION_STB_BOOT_HI_ADDR0_reserved0_MASK 0xffffff00
-#define BCHP_HIF_CONTINUATION_STB_BOOT_HI_ADDR0_reserved0_SHIFT 8
-
-/* HIF_CONTINUATION :: STB_BOOT_HI_ADDR0 :: ADDRESS [07:00] */
-#define BCHP_HIF_CONTINUATION_STB_BOOT_HI_ADDR0_ADDRESS_MASK 0x000000ff
-#define BCHP_HIF_CONTINUATION_STB_BOOT_HI_ADDR0_ADDRESS_SHIFT 0
-#define BCHP_HIF_CONTINUATION_STB_BOOT_HI_ADDR0_ADDRESS_DEFAULT 0x00000000
-
-/***************************************************************************
- *STB_BOOT_ADDR0 - Lower 32-bit of HIF's Read-only STB Boot Continuation Address 0 Register
- ***************************************************************************/
-/* HIF_CONTINUATION :: STB_BOOT_ADDR0 :: ADDRESS [31:00] */
-#define BCHP_HIF_CONTINUATION_STB_BOOT_ADDR0_ADDRESS_MASK 0xffffffff
-#define BCHP_HIF_CONTINUATION_STB_BOOT_ADDR0_ADDRESS_SHIFT 0
-#define BCHP_HIF_CONTINUATION_STB_BOOT_ADDR0_ADDRESS_DEFAULT 0xe0000000
-
-/***************************************************************************
- *STB_BOOT_HI_ADDR1 - Higher 8-bit of HIF's STB Boot Continuation Address 1 Register
- ***************************************************************************/
-/* HIF_CONTINUATION :: STB_BOOT_HI_ADDR1 :: reserved0 [31:08] */
-#define BCHP_HIF_CONTINUATION_STB_BOOT_HI_ADDR1_reserved0_MASK 0xffffff00
-#define BCHP_HIF_CONTINUATION_STB_BOOT_HI_ADDR1_reserved0_SHIFT 8
-
-/* HIF_CONTINUATION :: STB_BOOT_HI_ADDR1 :: ADDRESS [07:00] */
-#define BCHP_HIF_CONTINUATION_STB_BOOT_HI_ADDR1_ADDRESS_MASK 0x000000ff
-#define BCHP_HIF_CONTINUATION_STB_BOOT_HI_ADDR1_ADDRESS_SHIFT 0
-#define BCHP_HIF_CONTINUATION_STB_BOOT_HI_ADDR1_ADDRESS_DEFAULT 0x00000000
-
-/***************************************************************************
- *STB_BOOT_ADDR1 - Lower 32-bit of HIF's STB Boot Continuation Address 1 Register
- ***************************************************************************/
-/* HIF_CONTINUATION :: STB_BOOT_ADDR1 :: ADDRESS [31:00] */
-#define BCHP_HIF_CONTINUATION_STB_BOOT_ADDR1_ADDRESS_MASK 0xffffffff
-#define BCHP_HIF_CONTINUATION_STB_BOOT_ADDR1_ADDRESS_SHIFT 0
-#define BCHP_HIF_CONTINUATION_STB_BOOT_ADDR1_ADDRESS_DEFAULT 0xffff0000
-
-/***************************************************************************
- *WEB_BOOT_HI_ADDR0 - Higher 8-bit of HIF's WEB Boot Continuation Address 0 Register
- ***************************************************************************/
-/* HIF_CONTINUATION :: WEB_BOOT_HI_ADDR0 :: reserved0 [31:08] */
-#define BCHP_HIF_CONTINUATION_WEB_BOOT_HI_ADDR0_reserved0_MASK 0xffffff00
-#define BCHP_HIF_CONTINUATION_WEB_BOOT_HI_ADDR0_reserved0_SHIFT 8
-
-/* HIF_CONTINUATION :: WEB_BOOT_HI_ADDR0 :: ADDRESS [07:00] */
-#define BCHP_HIF_CONTINUATION_WEB_BOOT_HI_ADDR0_ADDRESS_MASK 0x000000ff
-#define BCHP_HIF_CONTINUATION_WEB_BOOT_HI_ADDR0_ADDRESS_SHIFT 0
-#define BCHP_HIF_CONTINUATION_WEB_BOOT_HI_ADDR0_ADDRESS_DEFAULT 0x00000000
-
-/***************************************************************************
- *WEB_BOOT_ADDR0 - Lower 32-bit of HIF's WEB Boot Continuation Address 0 Register
- ***************************************************************************/
-/* HIF_CONTINUATION :: WEB_BOOT_ADDR0 :: ADDRESS [31:00] */
-#define BCHP_HIF_CONTINUATION_WEB_BOOT_ADDR0_ADDRESS_MASK 0xffffffff
-#define BCHP_HIF_CONTINUATION_WEB_BOOT_ADDR0_ADDRESS_SHIFT 0
-#define BCHP_HIF_CONTINUATION_WEB_BOOT_ADDR0_ADDRESS_DEFAULT 0xffff0000
-
-#endif /* #ifndef BCHP_HIF_CONTINUATION_H__ */
-
-/* End of File */
diff --git a/include/linux/brcmstb/7366b0/bchp_hif_cpubiuctrl.h b/include/linux/brcmstb/7366b0/bchp_hif_cpubiuctrl.h
deleted file mode 100644
index e808316..0000000
--- a/include/linux/brcmstb/7366b0/bchp_hif_cpubiuctrl.h
+++ /dev/null
@@ -1,3437 +0,0 @@
-/***************************************************************************
- * Copyright (c) 1999-2014, Broadcom Corporation
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
- *
- * Module Description:
- * DO NOT EDIT THIS FILE DIRECTLY
- *
- * This module was generated magically with RDB from a source description
- * file. You must edit the source file for changes to be made to this file.
- *
- *
- * Date: Generated on Wed Jul 2 03:12:36 2014
- * Full Compile MD5 Checksum 7dc2787604a7d66ecd88cf44bdf8b9f2
- * (minus title and desc)
- * MD5 Checksum fac21eb3a5c0bbaa870b50b1cab81ef9
- *
- * Compiled with: RDB Utility combo_header.pl
- * RDB Parser 3.0
- * unknown unknown
- * Perl Interpreter 5.008008
- * Operating System linux
- *
- * Revision History:
- *
- * $brcm_Log: $
- *
- ***************************************************************************/
-
-#ifndef BCHP_HIF_CPUBIUCTRL_H__
-#define BCHP_HIF_CPUBIUCTRL_H__
-
-/***************************************************************************
- *HIF_CPUBIUCTRL - CPU BIU Control registers
- ***************************************************************************/
-#define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_ULIMT0 0x00442400 /* CPU Address Range0 Upper Limit Mapping Register */
-#define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_LLIMT0 0x00442404 /* CPU Address Range0 Lower Limit Mapping Register */
-#define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_ULIMT1 0x00442408 /* CPU Address Range1 Upper Limit Mapping Register */
-#define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_LLIMT1 0x0044240c /* CPU Address Range1 Lower Limit Mapping Register */
-#define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_ULIMT2 0x00442410 /* CPU Address Range2 Upper Limit Mapping Register */
-#define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_LLIMT2 0x00442414 /* CPU Address Range2 Lower Limit Mapping Register */
-#define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_ULIMT3 0x00442418 /* CPU Address Range3 Upper Limit Mapping Register */
-#define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_LLIMT3 0x0044241c /* CPU Address Range3 Lower Limit Mapping Register */
-#define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_ULIMT4 0x00442420 /* CPU Address Range4 Upper Limit Mapping Register */
-#define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_LLIMT4 0x00442424 /* CPU Address Range4 Lower Limit Mapping Register */
-#define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_ULIMT5 0x00442428 /* CPU Address Range5 Upper Limit Mapping Register */
-#define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_LLIMT5 0x0044242c /* CPU Address Range5 Lower Limit Mapping Register */
-#define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_ULIMT6 0x00442430 /* CPU Address Range6 Upper Limit Mapping Register */
-#define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_LLIMT6 0x00442434 /* CPU Address Range6 Lower Limit Mapping Register */
-#define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_ULIMT7 0x00442438 /* CPU Address Range7 Upper Limit Mapping Register */
-#define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_LLIMT7 0x0044243c /* CPU Address Range7 Lower Limit Mapping Register */
-#define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_ULIMT8 0x00442440 /* CPU Address Range8 Upper Limit Mapping Register */
-#define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_LLIMT8 0x00442444 /* CPU Address Range8 Lower Limit Mapping Register */
-#define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_ULIMT9 0x00442448 /* CPU Address Range9 Upper Limit Mapping Register */
-#define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_LLIMT9 0x0044244c /* CPU Address Range9 Lower Limit Mapping Register */
-#define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_ULIMT10 0x00442450 /* CPU Address Range10 Upper Limit Mapping Register */
-#define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_LLIMT10 0x00442454 /* CPU Address Range10 Lower Limit Mapping Register */
-#define BCHP_HIF_CPUBIUCTRL_SECURE_RESET_HNDSHAKE_REG 0x00442458 /* CPU Secure Soft Reset Handshake Register */
-#define BCHP_HIF_CPUBIUCTRL_SECURE_SOFT_RESET_REG 0x0044245c /* CPU Secure Soft Reset Register */
-#define BCHP_HIF_CPUBIUCTRL_CPU_ACCESS_RIGHT_VIOL_ADDR0 0x00442460 /* STB CPU Access Rights Violation Address0 Register */
-#define BCHP_HIF_CPUBIUCTRL_CPU_ACCESS_RIGHT_VIOL_UPPER_ADDR0 0x00442464 /* STB CPU Access Rights Violation Upper Address0 Register */
-#define BCHP_HIF_CPUBIUCTRL_CPU_ACCESS_RIGHT_VIOL_DETAIL_ADDR0 0x00442468 /* STB CPU Access Rights Violation Transaction Detail0 Register */
-#define BCHP_HIF_CPUBIUCTRL_CPU_ACCESS_RIGHT_VIOL_ADDR1 0x0044246c /* WEB CPU Access Rights Violation Address1 Register */
-#define BCHP_HIF_CPUBIUCTRL_CPU_ACCESS_RIGHT_VIOL_UPPER_ADDR1 0x00442470 /* WEB CPU Access Rights Violation Upper Address1 Register */
-#define BCHP_HIF_CPUBIUCTRL_CPU_ACCESS_RIGHT_VIOL_DETAIL_ADDR1 0x00442474 /* WEB CPU Access Rights Violation Transaction Detail1 Register */
-#define BCHP_HIF_CPUBIUCTRL_RAC_CONFIG0_REG 0x00442478 /* Read Ahead Cache Configuration0 Register */
-#define BCHP_HIF_CPUBIUCTRL_RAC_CONFIG1_REG 0x0044247c /* Read Ahead Cache Configuration1 Register */
-#define BCHP_HIF_CPUBIUCTRL_RAC_FLUSH_REG 0x00442480 /* Read Ahead Cache Flush Register */
-#define BCHP_HIF_CPUBIUCTRL_CPU_POWER_CONFIG_REG 0x00442484 /* CPU Power Configuration Register */
-#define BCHP_HIF_CPUBIUCTRL_CPU0_PWR_ZONE_CNTRL_REG 0x00442488 /* CPU0 Power Zone Control Register */
-#define BCHP_HIF_CPUBIUCTRL_CPU1_PWR_ZONE_CNTRL_REG 0x0044248c /* CPU1 Power Zone Control Register */
-#define BCHP_HIF_CPUBIUCTRL_CPU2_PWR_ZONE_CNTRL_REG 0x00442490 /* CPU2 Power Zone Control Register */
-#define BCHP_HIF_CPUBIUCTRL_CPU3_PWR_ZONE_CNTRL_REG 0x00442494 /* CPU3 Power Zone Control Register */
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_PWR_ZONE_CNTRL_REG 0x00442498 /* L2 and BIU Power Zone Control Register */
-#define BCHP_HIF_CPUBIUCTRL_CPU0_PWR_ZONE_CONFIG1_REG 0x0044249c /* CPU0 Power Zone Config1 Registers */
-#define BCHP_HIF_CPUBIUCTRL_CPU0_PWR_ZONE_CONFIG2_REG 0x004424a0 /* CPU0 Power Zone Config2 Registers */
-#define BCHP_HIF_CPUBIUCTRL_CPU1_PWR_ZONE_CONFIG1_REG 0x004424a4 /* CPU1 Power Zone Config1 Registers */
-#define BCHP_HIF_CPUBIUCTRL_CPU1_PWR_ZONE_CONFIG2_REG 0x004424a8 /* CPU1 Power Zone Config2 Registers */
-#define BCHP_HIF_CPUBIUCTRL_CPU2_PWR_ZONE_CONFIG1_REG 0x004424ac /* CPU2 Power Zone Config1 Registers */
-#define BCHP_HIF_CPUBIUCTRL_CPU2_PWR_ZONE_CONFIG2_REG 0x004424b0 /* CPU2 Power Zone Config2 Registers */
-#define BCHP_HIF_CPUBIUCTRL_CPU3_PWR_ZONE_CONFIG1_REG 0x004424b4 /* CPU3 Power Zone Config1 Registers */
-#define BCHP_HIF_CPUBIUCTRL_CPU3_PWR_ZONE_CONFIG2_REG 0x004424b8 /* CPU3 Power Zone Config2 Registers */
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_PWR_ZONE_CONFIG1_REG 0x004424bc /* L2/BIU Power Zone Config1 Registers */
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_PWR_ZONE_CONFIG2_REG 0x004424c0 /* L2/BIU Power Zone Config2 Registers */
-#define BCHP_HIF_CPUBIUCTRL_CPU0_PWR_FREQ_SCALAR_CTRL_REG 0x004424c4 /* CPU0 BPCM Frequency Scalar Control Register */
-#define BCHP_HIF_CPUBIUCTRL_CPU1_PWR_FREQ_SCALAR_CTRL_REG 0x004424c8 /* CPU1 BPCM Frequency Scalar Control Register */
-#define BCHP_HIF_CPUBIUCTRL_CPU2_PWR_FREQ_SCALAR_CTRL_REG 0x004424cc /* CPU2 BPCM Frequency Scalar Control Register */
-#define BCHP_HIF_CPUBIUCTRL_CPU3_PWR_FREQ_SCALAR_CTRL_REG 0x004424d0 /* CPU3 BPCM Frequency Scalar Control Register */
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_PWR_FREQ_SCALAR_CTRL_REG 0x004424d4 /* L2/BIU BPCM Frequency Scalar Control Register */
-#define BCHP_HIF_CPUBIUCTRL_CPU0_BPCM_ID 0x004424d8 /* CPU0 BPCM ID Register */
-#define BCHP_HIF_CPUBIUCTRL_CPU0_BPCM_CAPABILITY 0x004424dc /* CPU0 BPCM Capability Register */
-#define BCHP_HIF_CPUBIUCTRL_CPU0_BPCM_CONTROL 0x004424e0 /* CPU0 BPCM Control Register */
-#define BCHP_HIF_CPUBIUCTRL_CPU0_BPCM_STATUS 0x004424e4 /* CPU0 BPCM Status Register */
-#define BCHP_HIF_CPUBIUCTRL_CPU0_AVS_ROSC_CONTROL 0x004424e8 /* CPU0 Ring Oscillator Control Register */
-#define BCHP_HIF_CPUBIUCTRL_CPU0_AVS_ROSC_THRESHOLD 0x004424ec /* CPU0 Event Counter Threshold Register */
-#define BCHP_HIF_CPUBIUCTRL_CPU0_AVS_ROSC_COUNT 0x004424f0 /* CPU0 Event Counter Count Register */
-#define BCHP_HIF_CPUBIUCTRL_CPU0_AVS_PWD_CONTROL 0x004424f4 /* CPU0 PWD control Register */
-#define BCHP_HIF_CPUBIUCTRL_CPU1_BPCM_ID 0x004424f8 /* CPU1 BPCM ID Register */
-#define BCHP_HIF_CPUBIUCTRL_CPU1_BPCM_CAPABILITY 0x004424fc /* CPU1 BPCM Capability Register */
-#define BCHP_HIF_CPUBIUCTRL_CPU1_BPCM_CONTROL 0x00442500 /* CPU1 BPCM Control Register */
-#define BCHP_HIF_CPUBIUCTRL_CPU1_BPCM_STATUS 0x00442504 /* CPU1 BPCM Status Register */
-#define BCHP_HIF_CPUBIUCTRL_CPU1_AVS_ROSC_CONTROL 0x00442508 /* CPU1 Ring Oscillator Control Register */
-#define BCHP_HIF_CPUBIUCTRL_CPU1_AVS_ROSC_THRESHOLD 0x0044250c /* CPU1 Event Counter Threshold Register */
-#define BCHP_HIF_CPUBIUCTRL_CPU1_AVS_ROSC_COUNT 0x00442510 /* CPU1 Event Counter Count Register */
-#define BCHP_HIF_CPUBIUCTRL_CPU1_AVS_PWD_CONTROL 0x00442514 /* CPU1 PWD control Register */
-#define BCHP_HIF_CPUBIUCTRL_CPU2_BPCM_ID 0x00442518 /* CPU2 BPCM ID Register */
-#define BCHP_HIF_CPUBIUCTRL_CPU2_BPCM_CAPABILITY 0x0044251c /* CPU2 BPCM Capability Register */
-#define BCHP_HIF_CPUBIUCTRL_CPU2_BPCM_CONTROL 0x00442520 /* CPU2 BPCM Control Register */
-#define BCHP_HIF_CPUBIUCTRL_CPU2_BPCM_STATUS 0x00442524 /* CPU2 BPCM Status Register */
-#define BCHP_HIF_CPUBIUCTRL_CPU2_AVS_ROSC_CONTROL 0x00442528 /* CPU2 Ring Oscillator Control Register */
-#define BCHP_HIF_CPUBIUCTRL_CPU2_AVS_ROSC_THRESHOLD 0x0044252c /* CPU2 Event Counter Threshold Register */
-#define BCHP_HIF_CPUBIUCTRL_CPU2_AVS_ROSC_COUNT 0x00442530 /* CPU2 Event Counter Count Register */
-#define BCHP_HIF_CPUBIUCTRL_CPU2_AVS_PWD_CONTROL 0x00442534 /* CPU2 PWD control Register */
-#define BCHP_HIF_CPUBIUCTRL_CPU3_BPCM_ID 0x00442538 /* CPU3 BPCM ID Register */
-#define BCHP_HIF_CPUBIUCTRL_CPU3_BPCM_CAPABILITY 0x0044253c /* CPU3 BPCM Capability Register */
-#define BCHP_HIF_CPUBIUCTRL_CPU3_BPCM_CONTROL 0x00442540 /* CPU3 BPCM Control Register */
-#define BCHP_HIF_CPUBIUCTRL_CPU3_BPCM_STATUS 0x00442544 /* CPU3 BPCM Status Register */
-#define BCHP_HIF_CPUBIUCTRL_CPU3_AVS_ROSC_CONTROL 0x00442548 /* CPU3 Ring Oscillator Control Register */
-#define BCHP_HIF_CPUBIUCTRL_CPU3_AVS_ROSC_THRESHOLD 0x0044254c /* CPU3 Event Counter Threshold Register */
-#define BCHP_HIF_CPUBIUCTRL_CPU3_AVS_ROSC_COUNT 0x00442550 /* CPU3 Event Counter Count Register */
-#define BCHP_HIF_CPUBIUCTRL_CPU3_AVS_PWD_CONTROL 0x00442554 /* CPU3 PWD control Register */
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_BPCM_ID 0x00442558 /* L2BIU BPCM ID Register */
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_BPCM_CAPABILITY 0x0044255c /* L2BIU BPCM Capability Register */
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_BPCM_CONTROL 0x00442560 /* L2BIU BPCM Control Register */
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_BPCM_STATUS 0x00442564 /* L2BIU BPCM Status Register */
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_AVS_ROSC_CONTROL 0x00442568 /* L2BIU Ring Oscillator Control Register */
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_AVS_ROSC_THRESHOLD 0x0044256c /* L2BIU Event Counter Threshold Register */
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_AVS_ROSC_COUNT 0x00442570 /* L2BIU Event Counter Count Register */
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_AVS_PWD_CONTROL 0x00442574 /* L2BIU PWD control Register */
-#define BCHP_HIF_CPUBIUCTRL_CPU_RESET_CONFIG_REG 0x00442578 /* CPU Reset Configuration Register */
-#define BCHP_HIF_CPUBIUCTRL_CPU_CLOCK_CONFIG_REG 0x0044257c /* CPU Clock Configuration Register */
-#define BCHP_HIF_CPUBIUCTRL_CPU_MISC_CONFIG_REG 0x00442580 /* CPU Miscellaneous Configuration Register */
-#define BCHP_HIF_CPUBIUCTRL_CPU_CREDIT_REG 0x00442584 /* CPU Request Credit Register */
-#define BCHP_HIF_CPUBIUCTRL_CPU_THERM_THROTTLE_TEMP_REG 0x00442588 /* CPU Thermal Throttling IRQ Config Register */
-#define BCHP_HIF_CPUBIUCTRL_CPU_THERM_THROTTLE_IRQ_CONFIG_REG 0x0044258c /* CPU Thermal Throttling IRQ Config Register */
-#define BCHP_HIF_CPUBIUCTRL_CPU_THERM_IRQ_HIGH_REG 0x00442590 /* CPU Thermal Throttling IRQ High Register */
-#define BCHP_HIF_CPUBIUCTRL_CPU_THERM_IRQ_LOW_REG 0x00442594 /* CPU Thermal Throttling IRQ Low Register */
-#define BCHP_HIF_CPUBIUCTRL_CPU_THERM_MISC_THRESHOLD_REG 0x00442598 /* CPU Thermal Throttling Misc Threshold Register */
-#define BCHP_HIF_CPUBIUCTRL_CPU_THERM_IRQ_MISC_REG 0x0044259c /* CPU Thermal Throttling Misc IRQ Register */
-#define BCHP_HIF_CPUBIUCTRL_CPU_DEFEATURE_REG 0x004425a0 /* CPU Defeature Register */
-#define BCHP_HIF_CPUBIUCTRL_CPU_DEFEATURE_KEY_REG 0x004425a4 /* CPU Defeature Key Register */
-#define BCHP_HIF_CPUBIUCTRL_CPU_DEBUGROMADDR_REG 0x004425a8 /* CPU Debug ROM Address Register */
-#define BCHP_HIF_CPUBIUCTRL_CPU_DEBUGSELFADDR_REG 0x004425ac /* CPU Debug SELF Address Register */
-#define BCHP_HIF_CPUBIUCTRL_CPU_DEBUG_TRACECTRL_REG 0x004425b0 /* CPU Debug Trace Control Register */
-#define BCHP_HIF_CPUBIUCTRL_CPU_AXICONFIG_REG 0x004425b4 /* CPU AXI Config Register */
-#define BCHP_HIF_CPUBIUCTRL_CPU_REVISION_REG 0x004425b8 /* CPU Revision Register */
-#define BCHP_HIF_CPUBIUCTRL_CPU_UBUS_CFGWINDOW0 0x004425bc /* UBUS CFG Window0 Register */
-#define BCHP_HIF_CPUBIUCTRL_CPU_UBUS_CFGWINDOW1 0x004425c0 /* UBUS CFG Window1 Register */
-#define BCHP_HIF_CPUBIUCTRL_CPU_UBUS_CFGWINDOW2 0x004425c4 /* UBUS CFG Window2 Register */
-#define BCHP_HIF_CPUBIUCTRL_CPU_UBUS_CFGWINDOW3 0x004425c8 /* UBUS CFG Window3 Register */
-#define BCHP_HIF_CPUBIUCTRL_CPU_UBUS_CFGWINDOW4 0x004425cc /* UBUS CFG Window4 Register */
-#define BCHP_HIF_CPUBIUCTRL_CPU_UBUS_CFGWINDOW5 0x004425d0 /* UBUS CFG Window5 Register */
-#define BCHP_HIF_CPUBIUCTRL_CPU_UBUS_CFGWINDOW6 0x004425d4 /* UBUS CFG Window6 Register */
-#define BCHP_HIF_CPUBIUCTRL_CPU_UBUS_CFGWINDOW7 0x004425d8 /* UBUS CFG Window7 Register */
-#define BCHP_HIF_CPUBIUCTRL_CPU_UBUS_CONFIG 0x004425dc /* UBUS Configuration Register */
-#define BCHP_HIF_CPUBIUCTRL_CPU_SCRATCH_REG 0x004427fc /* Scratch Register */
-
-/***************************************************************************
- *CPU_BUS_RANGE_ULIMT0 - CPU Address Range0 Upper Limit Mapping Register
- ***************************************************************************/
-/* HIF_CPUBIUCTRL :: CPU_BUS_RANGE_ULIMT0 :: ULIMIT [31:04] */
-#define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_ULIMT0_ULIMIT_MASK 0xfffffff0
-#define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_ULIMT0_ULIMIT_SHIFT 4
-#define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_ULIMT0_ULIMIT_DEFAULT 0x000fffff
-
-/* HIF_CPUBIUCTRL :: CPU_BUS_RANGE_ULIMT0 :: BUSNUM [03:00] */
-#define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_ULIMT0_BUSNUM_MASK 0x0000000f
-#define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_ULIMT0_BUSNUM_SHIFT 0
-#define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_ULIMT0_BUSNUM_DEFAULT 0x00000002
-
-/***************************************************************************
- *CPU_BUS_RANGE_LLIMT0 - CPU Address Range0 Lower Limit Mapping Register
- ***************************************************************************/
-/* HIF_CPUBIUCTRL :: CPU_BUS_RANGE_LLIMT0 :: LLIMIT [31:04] */
-#define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_LLIMT0_LLIMIT_MASK 0xfffffff0
-#define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_LLIMT0_LLIMIT_SHIFT 4
-#define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_LLIMT0_LLIMIT_DEFAULT 0x000ffe00
-
-/* HIF_CPUBIUCTRL :: CPU_BUS_RANGE_LLIMT0 :: reserved0 [03:01] */
-#define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_LLIMT0_reserved0_MASK 0x0000000e
-#define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_LLIMT0_reserved0_SHIFT 1
-
-/* HIF_CPUBIUCTRL :: CPU_BUS_RANGE_LLIMT0 :: UBUSCDBIT [00:00] */
-#define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_LLIMT0_UBUSCDBIT_MASK 0x00000001
-#define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_LLIMT0_UBUSCDBIT_SHIFT 0
-#define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_LLIMT0_UBUSCDBIT_DEFAULT 0x00000000
-
-/***************************************************************************
- *CPU_BUS_RANGE_ULIMT1 - CPU Address Range1 Upper Limit Mapping Register
- ***************************************************************************/
-/* HIF_CPUBIUCTRL :: CPU_BUS_RANGE_ULIMT1 :: ULIMIT [31:04] */
-#define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_ULIMT1_ULIMIT_MASK 0xfffffff0
-#define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_ULIMT1_ULIMIT_SHIFT 4
-#define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_ULIMT1_ULIMIT_DEFAULT 0x000f1fff
-
-/* HIF_CPUBIUCTRL :: CPU_BUS_RANGE_ULIMT1 :: BUSNUM [03:00] */
-#define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_ULIMT1_BUSNUM_MASK 0x0000000f
-#define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_ULIMT1_BUSNUM_SHIFT 0
-#define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_ULIMT1_BUSNUM_DEFAULT 0x00000002
-
-/***************************************************************************
- *CPU_BUS_RANGE_LLIMT1 - CPU Address Range1 Lower Limit Mapping Register
- ***************************************************************************/
-/* HIF_CPUBIUCTRL :: CPU_BUS_RANGE_LLIMT1 :: LLIMIT [31:04] */
-#define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_LLIMT1_LLIMIT_MASK 0xfffffff0
-#define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_LLIMT1_LLIMIT_SHIFT 4
-#define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_LLIMT1_LLIMIT_DEFAULT 0x000c0000
-
-/* HIF_CPUBIUCTRL :: CPU_BUS_RANGE_LLIMT1 :: reserved0 [03:01] */
-#define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_LLIMT1_reserved0_MASK 0x0000000e
-#define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_LLIMT1_reserved0_SHIFT 1
-
-/* HIF_CPUBIUCTRL :: CPU_BUS_RANGE_LLIMT1 :: UBUSCDBIT [00:00] */
-#define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_LLIMT1_UBUSCDBIT_MASK 0x00000001
-#define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_LLIMT1_UBUSCDBIT_SHIFT 0
-#define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_LLIMT1_UBUSCDBIT_DEFAULT 0x00000000
-
-/***************************************************************************
- *CPU_BUS_RANGE_ULIMT2 - CPU Address Range2 Upper Limit Mapping Register
- ***************************************************************************/
-/* HIF_CPUBIUCTRL :: CPU_BUS_RANGE_ULIMT2 :: ULIMIT [31:04] */
-#define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_ULIMT2_ULIMIT_MASK 0xfffffff0
-#define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_ULIMT2_ULIMIT_SHIFT 4
-#define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_ULIMT2_ULIMIT_DEFAULT 0x00bfffff
-
-/* HIF_CPUBIUCTRL :: CPU_BUS_RANGE_ULIMT2 :: BUSNUM [03:00] */
-#define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_ULIMT2_BUSNUM_MASK 0x0000000f
-#define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_ULIMT2_BUSNUM_SHIFT 0
-#define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_ULIMT2_BUSNUM_DEFAULT 0x00000002
-
-/***************************************************************************
- *CPU_BUS_RANGE_LLIMT2 - CPU Address Range2 Lower Limit Mapping Register
- ***************************************************************************/
-/* HIF_CPUBIUCTRL :: CPU_BUS_RANGE_LLIMT2 :: LLIMIT [31:04] */
-#define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_LLIMT2_LLIMIT_MASK 0xfffffff0
-#define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_LLIMT2_LLIMIT_SHIFT 4
-#define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_LLIMT2_LLIMIT_DEFAULT 0x00600000
-
-/* HIF_CPUBIUCTRL :: CPU_BUS_RANGE_LLIMT2 :: reserved0 [03:01] */
-#define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_LLIMT2_reserved0_MASK 0x0000000e
-#define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_LLIMT2_reserved0_SHIFT 1
-
-/* HIF_CPUBIUCTRL :: CPU_BUS_RANGE_LLIMT2 :: UBUSCDBIT [00:00] */
-#define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_LLIMT2_UBUSCDBIT_MASK 0x00000001
-#define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_LLIMT2_UBUSCDBIT_SHIFT 0
-#define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_LLIMT2_UBUSCDBIT_DEFAULT 0x00000000
-
-/***************************************************************************
- *CPU_BUS_RANGE_ULIMT3 - CPU Address Range3 Upper Limit Mapping Register
- ***************************************************************************/
-/* HIF_CPUBIUCTRL :: CPU_BUS_RANGE_ULIMT3 :: ULIMIT [31:04] */
-#define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_ULIMT3_ULIMIT_MASK 0xfffffff0
-#define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_ULIMT3_ULIMIT_SHIFT 4
-#define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_ULIMT3_ULIMIT_DEFAULT 0x0003ffff
-
-/* HIF_CPUBIUCTRL :: CPU_BUS_RANGE_ULIMT3 :: BUSNUM [03:00] */
-#define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_ULIMT3_BUSNUM_MASK 0x0000000f
-#define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_ULIMT3_BUSNUM_SHIFT 0
-#define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_ULIMT3_BUSNUM_DEFAULT 0x00000004
-
-/***************************************************************************
- *CPU_BUS_RANGE_LLIMT3 - CPU Address Range3 Lower Limit Mapping Register
- ***************************************************************************/
-/* HIF_CPUBIUCTRL :: CPU_BUS_RANGE_LLIMT3 :: LLIMIT [31:04] */
-#define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_LLIMT3_LLIMIT_MASK 0xfffffff0
-#define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_LLIMT3_LLIMIT_SHIFT 4
-#define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_LLIMT3_LLIMIT_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: CPU_BUS_RANGE_LLIMT3 :: reserved0 [03:01] */
-#define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_LLIMT3_reserved0_MASK 0x0000000e
-#define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_LLIMT3_reserved0_SHIFT 1
-
-/* HIF_CPUBIUCTRL :: CPU_BUS_RANGE_LLIMT3 :: UBUSCDBIT [00:00] */
-#define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_LLIMT3_UBUSCDBIT_MASK 0x00000001
-#define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_LLIMT3_UBUSCDBIT_SHIFT 0
-#define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_LLIMT3_UBUSCDBIT_DEFAULT 0x00000000
-
-/***************************************************************************
- *CPU_BUS_RANGE_ULIMT4 - CPU Address Range4 Upper Limit Mapping Register
- ***************************************************************************/
-/* HIF_CPUBIUCTRL :: CPU_BUS_RANGE_ULIMT4 :: ULIMIT [31:04] */
-#define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_ULIMT4_ULIMIT_MASK 0xfffffff0
-#define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_ULIMT4_ULIMIT_SHIFT 4
-#define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_ULIMT4_ULIMIT_DEFAULT 0x001bffff
-
-/* HIF_CPUBIUCTRL :: CPU_BUS_RANGE_ULIMT4 :: BUSNUM [03:00] */
-#define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_ULIMT4_BUSNUM_MASK 0x0000000f
-#define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_ULIMT4_BUSNUM_SHIFT 0
-#define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_ULIMT4_BUSNUM_DEFAULT 0x00000004
-
-/***************************************************************************
- *CPU_BUS_RANGE_LLIMT4 - CPU Address Range4 Lower Limit Mapping Register
- ***************************************************************************/
-/* HIF_CPUBIUCTRL :: CPU_BUS_RANGE_LLIMT4 :: LLIMIT [31:04] */
-#define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_LLIMT4_LLIMIT_MASK 0xfffffff0
-#define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_LLIMT4_LLIMIT_SHIFT 4
-#define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_LLIMT4_LLIMIT_DEFAULT 0x00100000
-
-/* HIF_CPUBIUCTRL :: CPU_BUS_RANGE_LLIMT4 :: reserved0 [03:01] */
-#define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_LLIMT4_reserved0_MASK 0x0000000e
-#define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_LLIMT4_reserved0_SHIFT 1
-
-/* HIF_CPUBIUCTRL :: CPU_BUS_RANGE_LLIMT4 :: UBUSCDBIT [00:00] */
-#define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_LLIMT4_UBUSCDBIT_MASK 0x00000001
-#define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_LLIMT4_UBUSCDBIT_SHIFT 0
-#define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_LLIMT4_UBUSCDBIT_DEFAULT 0x00000000
-
-/***************************************************************************
- *CPU_BUS_RANGE_ULIMT5 - CPU Address Range5 Upper Limit Mapping Register
- ***************************************************************************/
-/* HIF_CPUBIUCTRL :: CPU_BUS_RANGE_ULIMT5 :: ULIMIT [31:04] */
-#define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_ULIMT5_ULIMIT_MASK 0xfffffff0
-#define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_ULIMT5_ULIMIT_SHIFT 4
-#define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_ULIMT5_ULIMIT_DEFAULT 0x0007ffff
-
-/* HIF_CPUBIUCTRL :: CPU_BUS_RANGE_ULIMT5 :: BUSNUM [03:00] */
-#define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_ULIMT5_BUSNUM_MASK 0x0000000f
-#define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_ULIMT5_BUSNUM_SHIFT 0
-#define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_ULIMT5_BUSNUM_DEFAULT 0x00000005
-
-/***************************************************************************
- *CPU_BUS_RANGE_LLIMT5 - CPU Address Range5 Lower Limit Mapping Register
- ***************************************************************************/
-/* HIF_CPUBIUCTRL :: CPU_BUS_RANGE_LLIMT5 :: LLIMIT [31:04] */
-#define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_LLIMT5_LLIMIT_MASK 0xfffffff0
-#define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_LLIMT5_LLIMIT_SHIFT 4
-#define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_LLIMT5_LLIMIT_DEFAULT 0x00040000
-
-/* HIF_CPUBIUCTRL :: CPU_BUS_RANGE_LLIMT5 :: reserved0 [03:01] */
-#define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_LLIMT5_reserved0_MASK 0x0000000e
-#define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_LLIMT5_reserved0_SHIFT 1
-
-/* HIF_CPUBIUCTRL :: CPU_BUS_RANGE_LLIMT5 :: UBUSCDBIT [00:00] */
-#define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_LLIMT5_UBUSCDBIT_MASK 0x00000001
-#define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_LLIMT5_UBUSCDBIT_SHIFT 0
-#define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_LLIMT5_UBUSCDBIT_DEFAULT 0x00000000
-
-/***************************************************************************
- *CPU_BUS_RANGE_ULIMT6 - CPU Address Range6 Upper Limit Mapping Register
- ***************************************************************************/
-/* HIF_CPUBIUCTRL :: CPU_BUS_RANGE_ULIMT6 :: ULIMIT [31:04] */
-#define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_ULIMT6_ULIMIT_MASK 0xfffffff0
-#define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_ULIMT6_ULIMIT_SHIFT 4
-#define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_ULIMT6_ULIMIT_DEFAULT 0x003bffff
-
-/* HIF_CPUBIUCTRL :: CPU_BUS_RANGE_ULIMT6 :: BUSNUM [03:00] */
-#define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_ULIMT6_BUSNUM_MASK 0x0000000f
-#define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_ULIMT6_BUSNUM_SHIFT 0
-#define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_ULIMT6_BUSNUM_DEFAULT 0x00000005
-
-/***************************************************************************
- *CPU_BUS_RANGE_LLIMT6 - CPU Address Range6 Lower Limit Mapping Register
- ***************************************************************************/
-/* HIF_CPUBIUCTRL :: CPU_BUS_RANGE_LLIMT6 :: LLIMIT [31:04] */
-#define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_LLIMT6_LLIMIT_MASK 0xfffffff0
-#define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_LLIMT6_LLIMIT_SHIFT 4
-#define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_LLIMT6_LLIMIT_DEFAULT 0x00300000
-
-/* HIF_CPUBIUCTRL :: CPU_BUS_RANGE_LLIMT6 :: reserved0 [03:01] */
-#define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_LLIMT6_reserved0_MASK 0x0000000e
-#define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_LLIMT6_reserved0_SHIFT 1
-
-/* HIF_CPUBIUCTRL :: CPU_BUS_RANGE_LLIMT6 :: UBUSCDBIT [00:00] */
-#define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_LLIMT6_UBUSCDBIT_MASK 0x00000001
-#define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_LLIMT6_UBUSCDBIT_SHIFT 0
-#define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_LLIMT6_UBUSCDBIT_DEFAULT 0x00000000
-
-/***************************************************************************
- *CPU_BUS_RANGE_ULIMT7 - CPU Address Range7 Upper Limit Mapping Register
- ***************************************************************************/
-/* HIF_CPUBIUCTRL :: CPU_BUS_RANGE_ULIMT7 :: ULIMIT [31:04] */
-#define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_ULIMT7_ULIMIT_MASK 0xfffffff0
-#define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_ULIMT7_ULIMIT_SHIFT 4
-#define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_ULIMT7_ULIMIT_DEFAULT 0x000bffff
-
-/* HIF_CPUBIUCTRL :: CPU_BUS_RANGE_ULIMT7 :: BUSNUM [03:00] */
-#define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_ULIMT7_BUSNUM_MASK 0x0000000f
-#define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_ULIMT7_BUSNUM_SHIFT 0
-#define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_ULIMT7_BUSNUM_DEFAULT 0x00000006
-
-/***************************************************************************
- *CPU_BUS_RANGE_LLIMT7 - CPU Address Range7 Lower Limit Mapping Register
- ***************************************************************************/
-/* HIF_CPUBIUCTRL :: CPU_BUS_RANGE_LLIMT7 :: LLIMIT [31:04] */
-#define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_LLIMT7_LLIMIT_MASK 0xfffffff0
-#define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_LLIMT7_LLIMIT_SHIFT 4
-#define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_LLIMT7_LLIMIT_DEFAULT 0x00080000
-
-/* HIF_CPUBIUCTRL :: CPU_BUS_RANGE_LLIMT7 :: reserved0 [03:01] */
-#define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_LLIMT7_reserved0_MASK 0x0000000e
-#define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_LLIMT7_reserved0_SHIFT 1
-
-/* HIF_CPUBIUCTRL :: CPU_BUS_RANGE_LLIMT7 :: UBUSCDBIT [00:00] */
-#define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_LLIMT7_UBUSCDBIT_MASK 0x00000001
-#define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_LLIMT7_UBUSCDBIT_SHIFT 0
-#define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_LLIMT7_UBUSCDBIT_DEFAULT 0x00000000
-
-/***************************************************************************
- *CPU_BUS_RANGE_ULIMT8 - CPU Address Range8 Upper Limit Mapping Register
- ***************************************************************************/
-/* HIF_CPUBIUCTRL :: CPU_BUS_RANGE_ULIMT8 :: ULIMIT [31:04] */
-#define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_ULIMT8_ULIMIT_MASK 0xfffffff0
-#define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_ULIMT8_ULIMIT_SHIFT 4
-#define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_ULIMT8_ULIMIT_DEFAULT 0x00cbffff
-
-/* HIF_CPUBIUCTRL :: CPU_BUS_RANGE_ULIMT8 :: BUSNUM [03:00] */
-#define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_ULIMT8_BUSNUM_MASK 0x0000000f
-#define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_ULIMT8_BUSNUM_SHIFT 0
-#define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_ULIMT8_BUSNUM_DEFAULT 0x00000006
-
-/***************************************************************************
- *CPU_BUS_RANGE_LLIMT8 - CPU Address Range8 Lower Limit Mapping Register
- ***************************************************************************/
-/* HIF_CPUBIUCTRL :: CPU_BUS_RANGE_LLIMT8 :: LLIMIT [31:04] */
-#define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_LLIMT8_LLIMIT_MASK 0xfffffff0
-#define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_LLIMT8_LLIMIT_SHIFT 4
-#define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_LLIMT8_LLIMIT_DEFAULT 0x00c00000
-
-/* HIF_CPUBIUCTRL :: CPU_BUS_RANGE_LLIMT8 :: reserved0 [03:01] */
-#define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_LLIMT8_reserved0_MASK 0x0000000e
-#define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_LLIMT8_reserved0_SHIFT 1
-
-/* HIF_CPUBIUCTRL :: CPU_BUS_RANGE_LLIMT8 :: UBUSCDBIT [00:00] */
-#define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_LLIMT8_UBUSCDBIT_MASK 0x00000001
-#define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_LLIMT8_UBUSCDBIT_SHIFT 0
-#define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_LLIMT8_UBUSCDBIT_DEFAULT 0x00000000
-
-/***************************************************************************
- *CPU_BUS_RANGE_ULIMT9 - CPU Address Range9 Upper Limit Mapping Register
- ***************************************************************************/
-/* HIF_CPUBIUCTRL :: CPU_BUS_RANGE_ULIMT9 :: ULIMIT [31:04] */
-#define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_ULIMT9_ULIMIT_MASK 0xfffffff0
-#define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_ULIMT9_ULIMIT_SHIFT 4
-#define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_ULIMT9_ULIMIT_DEFAULT 0x00dfffff
-
-/* HIF_CPUBIUCTRL :: CPU_BUS_RANGE_ULIMT9 :: BUSNUM [03:00] */
-#define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_ULIMT9_BUSNUM_MASK 0x0000000f
-#define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_ULIMT9_BUSNUM_SHIFT 0
-#define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_ULIMT9_BUSNUM_DEFAULT 0x00000000
-
-/***************************************************************************
- *CPU_BUS_RANGE_LLIMT9 - CPU Address Range9 Lower Limit Mapping Register
- ***************************************************************************/
-/* HIF_CPUBIUCTRL :: CPU_BUS_RANGE_LLIMT9 :: LLIMIT [31:04] */
-#define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_LLIMT9_LLIMIT_MASK 0xfffffff0
-#define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_LLIMT9_LLIMIT_SHIFT 4
-#define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_LLIMT9_LLIMIT_DEFAULT 0x00d00000
-
-/* HIF_CPUBIUCTRL :: CPU_BUS_RANGE_LLIMT9 :: reserved0 [03:01] */
-#define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_LLIMT9_reserved0_MASK 0x0000000e
-#define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_LLIMT9_reserved0_SHIFT 1
-
-/* HIF_CPUBIUCTRL :: CPU_BUS_RANGE_LLIMT9 :: UBUSCDBIT [00:00] */
-#define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_LLIMT9_UBUSCDBIT_MASK 0x00000001
-#define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_LLIMT9_UBUSCDBIT_SHIFT 0
-#define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_LLIMT9_UBUSCDBIT_DEFAULT 0x00000000
-
-/***************************************************************************
- *CPU_BUS_RANGE_ULIMT10 - CPU Address Range10 Upper Limit Mapping Register
- ***************************************************************************/
-/* HIF_CPUBIUCTRL :: CPU_BUS_RANGE_ULIMT10 :: ULIMIT [31:04] */
-#define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_ULIMT10_ULIMIT_MASK 0xfffffff0
-#define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_ULIMT10_ULIMIT_SHIFT 4
-#define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_ULIMT10_ULIMIT_DEFAULT 0x00efffff
-
-/* HIF_CPUBIUCTRL :: CPU_BUS_RANGE_ULIMT10 :: BUSNUM [03:00] */
-#define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_ULIMT10_BUSNUM_MASK 0x0000000f
-#define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_ULIMT10_BUSNUM_SHIFT 0
-#define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_ULIMT10_BUSNUM_DEFAULT 0x00000000
-
-/***************************************************************************
- *CPU_BUS_RANGE_LLIMT10 - CPU Address Range10 Lower Limit Mapping Register
- ***************************************************************************/
-/* HIF_CPUBIUCTRL :: CPU_BUS_RANGE_LLIMT10 :: LLIMIT [31:04] */
-#define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_LLIMT10_LLIMIT_MASK 0xfffffff0
-#define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_LLIMT10_LLIMIT_SHIFT 4
-#define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_LLIMT10_LLIMIT_DEFAULT 0x00e00000
-
-/* HIF_CPUBIUCTRL :: CPU_BUS_RANGE_LLIMT10 :: reserved0 [03:01] */
-#define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_LLIMT10_reserved0_MASK 0x0000000e
-#define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_LLIMT10_reserved0_SHIFT 1
-
-/* HIF_CPUBIUCTRL :: CPU_BUS_RANGE_LLIMT10 :: UBUSCDBIT [00:00] */
-#define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_LLIMT10_UBUSCDBIT_MASK 0x00000001
-#define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_LLIMT10_UBUSCDBIT_SHIFT 0
-#define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_LLIMT10_UBUSCDBIT_DEFAULT 0x00000000
-
-/***************************************************************************
- *SECURE_RESET_HNDSHAKE_REG - CPU Secure Soft Reset Handshake Register
- ***************************************************************************/
-/* HIF_CPUBIUCTRL :: SECURE_RESET_HNDSHAKE_REG :: START [31:31] */
-#define BCHP_HIF_CPUBIUCTRL_SECURE_RESET_HNDSHAKE_REG_START_MASK 0x80000000
-#define BCHP_HIF_CPUBIUCTRL_SECURE_RESET_HNDSHAKE_REG_START_SHIFT 31
-#define BCHP_HIF_CPUBIUCTRL_SECURE_RESET_HNDSHAKE_REG_START_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: SECURE_RESET_HNDSHAKE_REG :: SW_DONE [30:30] */
-#define BCHP_HIF_CPUBIUCTRL_SECURE_RESET_HNDSHAKE_REG_SW_DONE_MASK 0x40000000
-#define BCHP_HIF_CPUBIUCTRL_SECURE_RESET_HNDSHAKE_REG_SW_DONE_SHIFT 30
-#define BCHP_HIF_CPUBIUCTRL_SECURE_RESET_HNDSHAKE_REG_SW_DONE_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: SECURE_RESET_HNDSHAKE_REG :: HW_DONE [29:29] */
-#define BCHP_HIF_CPUBIUCTRL_SECURE_RESET_HNDSHAKE_REG_HW_DONE_MASK 0x20000000
-#define BCHP_HIF_CPUBIUCTRL_SECURE_RESET_HNDSHAKE_REG_HW_DONE_SHIFT 29
-
-/* HIF_CPUBIUCTRL :: SECURE_RESET_HNDSHAKE_REG :: reserved0 [28:00] */
-#define BCHP_HIF_CPUBIUCTRL_SECURE_RESET_HNDSHAKE_REG_reserved0_MASK 0x1fffffff
-#define BCHP_HIF_CPUBIUCTRL_SECURE_RESET_HNDSHAKE_REG_reserved0_SHIFT 0
-
-/***************************************************************************
- *SECURE_SOFT_RESET_REG - CPU Secure Soft Reset Register
- ***************************************************************************/
-/* HIF_CPUBIUCTRL :: SECURE_SOFT_RESET_REG :: WEBCORES_SOFT_RESET [31:31] */
-#define BCHP_HIF_CPUBIUCTRL_SECURE_SOFT_RESET_REG_WEBCORES_SOFT_RESET_MASK 0x80000000
-#define BCHP_HIF_CPUBIUCTRL_SECURE_SOFT_RESET_REG_WEBCORES_SOFT_RESET_SHIFT 31
-#define BCHP_HIF_CPUBIUCTRL_SECURE_SOFT_RESET_REG_WEBCORES_SOFT_RESET_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: SECURE_SOFT_RESET_REG :: reserved0 [30:00] */
-#define BCHP_HIF_CPUBIUCTRL_SECURE_SOFT_RESET_REG_reserved0_MASK 0x7fffffff
-#define BCHP_HIF_CPUBIUCTRL_SECURE_SOFT_RESET_REG_reserved0_SHIFT 0
-
-/***************************************************************************
- *CPU_ACCESS_RIGHT_VIOL_ADDR0 - STB CPU Access Rights Violation Address0 Register
- ***************************************************************************/
-/* HIF_CPUBIUCTRL :: CPU_ACCESS_RIGHT_VIOL_ADDR0 :: VIOL_ADDR [31:00] */
-#define BCHP_HIF_CPUBIUCTRL_CPU_ACCESS_RIGHT_VIOL_ADDR0_VIOL_ADDR_MASK 0xffffffff
-#define BCHP_HIF_CPUBIUCTRL_CPU_ACCESS_RIGHT_VIOL_ADDR0_VIOL_ADDR_SHIFT 0
-#define BCHP_HIF_CPUBIUCTRL_CPU_ACCESS_RIGHT_VIOL_ADDR0_VIOL_ADDR_DEFAULT 0x00000000
-
-/***************************************************************************
- *CPU_ACCESS_RIGHT_VIOL_UPPER_ADDR0 - STB CPU Access Rights Violation Upper Address0 Register
- ***************************************************************************/
-/* HIF_CPUBIUCTRL :: CPU_ACCESS_RIGHT_VIOL_UPPER_ADDR0 :: reserved0 [31:08] */
-#define BCHP_HIF_CPUBIUCTRL_CPU_ACCESS_RIGHT_VIOL_UPPER_ADDR0_reserved0_MASK 0xffffff00
-#define BCHP_HIF_CPUBIUCTRL_CPU_ACCESS_RIGHT_VIOL_UPPER_ADDR0_reserved0_SHIFT 8
-
-/* HIF_CPUBIUCTRL :: CPU_ACCESS_RIGHT_VIOL_UPPER_ADDR0 :: VIOL_UPPER_ADDR [07:00] */
-#define BCHP_HIF_CPUBIUCTRL_CPU_ACCESS_RIGHT_VIOL_UPPER_ADDR0_VIOL_UPPER_ADDR_MASK 0x000000ff
-#define BCHP_HIF_CPUBIUCTRL_CPU_ACCESS_RIGHT_VIOL_UPPER_ADDR0_VIOL_UPPER_ADDR_SHIFT 0
-#define BCHP_HIF_CPUBIUCTRL_CPU_ACCESS_RIGHT_VIOL_UPPER_ADDR0_VIOL_UPPER_ADDR_DEFAULT 0x00000000
-
-/***************************************************************************
- *CPU_ACCESS_RIGHT_VIOL_DETAIL_ADDR0 - STB CPU Access Rights Violation Transaction Detail0 Register
- ***************************************************************************/
-/* HIF_CPUBIUCTRL :: CPU_ACCESS_RIGHT_VIOL_DETAIL_ADDR0 :: ERROR_VLD [31:31] */
-#define BCHP_HIF_CPUBIUCTRL_CPU_ACCESS_RIGHT_VIOL_DETAIL_ADDR0_ERROR_VLD_MASK 0x80000000
-#define BCHP_HIF_CPUBIUCTRL_CPU_ACCESS_RIGHT_VIOL_DETAIL_ADDR0_ERROR_VLD_SHIFT 31
-
-/* HIF_CPUBIUCTRL :: CPU_ACCESS_RIGHT_VIOL_DETAIL_ADDR0 :: reserved0 [30:30] */
-#define BCHP_HIF_CPUBIUCTRL_CPU_ACCESS_RIGHT_VIOL_DETAIL_ADDR0_reserved0_MASK 0x40000000
-#define BCHP_HIF_CPUBIUCTRL_CPU_ACCESS_RIGHT_VIOL_DETAIL_ADDR0_reserved0_SHIFT 30
-
-/* HIF_CPUBIUCTRL :: CPU_ACCESS_RIGHT_VIOL_DETAIL_ADDR0 :: CLUSTER_ID [29:26] */
-#define BCHP_HIF_CPUBIUCTRL_CPU_ACCESS_RIGHT_VIOL_DETAIL_ADDR0_CLUSTER_ID_MASK 0x3c000000
-#define BCHP_HIF_CPUBIUCTRL_CPU_ACCESS_RIGHT_VIOL_DETAIL_ADDR0_CLUSTER_ID_SHIFT 26
-
-/* HIF_CPUBIUCTRL :: CPU_ACCESS_RIGHT_VIOL_DETAIL_ADDR0 :: PROCESSOR_ID [25:24] */
-#define BCHP_HIF_CPUBIUCTRL_CPU_ACCESS_RIGHT_VIOL_DETAIL_ADDR0_PROCESSOR_ID_MASK 0x03000000
-#define BCHP_HIF_CPUBIUCTRL_CPU_ACCESS_RIGHT_VIOL_DETAIL_ADDR0_PROCESSOR_ID_SHIFT 24
-
-/* HIF_CPUBIUCTRL :: CPU_ACCESS_RIGHT_VIOL_DETAIL_ADDR0 :: reserved1 [23:23] */
-#define BCHP_HIF_CPUBIUCTRL_CPU_ACCESS_RIGHT_VIOL_DETAIL_ADDR0_reserved1_MASK 0x00800000
-#define BCHP_HIF_CPUBIUCTRL_CPU_ACCESS_RIGHT_VIOL_DETAIL_ADDR0_reserved1_SHIFT 23
-
-/* HIF_CPUBIUCTRL :: CPU_ACCESS_RIGHT_VIOL_DETAIL_ADDR0 :: INSTRUCTION_ACCESS [22:22] */
-#define BCHP_HIF_CPUBIUCTRL_CPU_ACCESS_RIGHT_VIOL_DETAIL_ADDR0_INSTRUCTION_ACCESS_MASK 0x00400000
-#define BCHP_HIF_CPUBIUCTRL_CPU_ACCESS_RIGHT_VIOL_DETAIL_ADDR0_INSTRUCTION_ACCESS_SHIFT 22
-
-/* HIF_CPUBIUCTRL :: CPU_ACCESS_RIGHT_VIOL_DETAIL_ADDR0 :: reserved2 [21:16] */
-#define BCHP_HIF_CPUBIUCTRL_CPU_ACCESS_RIGHT_VIOL_DETAIL_ADDR0_reserved2_MASK 0x003f0000
-#define BCHP_HIF_CPUBIUCTRL_CPU_ACCESS_RIGHT_VIOL_DETAIL_ADDR0_reserved2_SHIFT 16
-
-/* HIF_CPUBIUCTRL :: CPU_ACCESS_RIGHT_VIOL_DETAIL_ADDR0 :: REQUEST_SIZE [15:12] */
-#define BCHP_HIF_CPUBIUCTRL_CPU_ACCESS_RIGHT_VIOL_DETAIL_ADDR0_REQUEST_SIZE_MASK 0x0000f000
-#define BCHP_HIF_CPUBIUCTRL_CPU_ACCESS_RIGHT_VIOL_DETAIL_ADDR0_REQUEST_SIZE_SHIFT 12
-
-/* HIF_CPUBIUCTRL :: CPU_ACCESS_RIGHT_VIOL_DETAIL_ADDR0 :: UPPER_VIOL_ADDR [11:04] */
-#define BCHP_HIF_CPUBIUCTRL_CPU_ACCESS_RIGHT_VIOL_DETAIL_ADDR0_UPPER_VIOL_ADDR_MASK 0x00000ff0
-#define BCHP_HIF_CPUBIUCTRL_CPU_ACCESS_RIGHT_VIOL_DETAIL_ADDR0_UPPER_VIOL_ADDR_SHIFT 4
-#define BCHP_HIF_CPUBIUCTRL_CPU_ACCESS_RIGHT_VIOL_DETAIL_ADDR0_UPPER_VIOL_ADDR_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: CPU_ACCESS_RIGHT_VIOL_DETAIL_ADDR0 :: REQUEST_TYPE [03:00] */
-#define BCHP_HIF_CPUBIUCTRL_CPU_ACCESS_RIGHT_VIOL_DETAIL_ADDR0_REQUEST_TYPE_MASK 0x0000000f
-#define BCHP_HIF_CPUBIUCTRL_CPU_ACCESS_RIGHT_VIOL_DETAIL_ADDR0_REQUEST_TYPE_SHIFT 0
-
-/***************************************************************************
- *CPU_ACCESS_RIGHT_VIOL_ADDR1 - WEB CPU Access Rights Violation Address1 Register
- ***************************************************************************/
-/* HIF_CPUBIUCTRL :: CPU_ACCESS_RIGHT_VIOL_ADDR1 :: VIOL_ADDR [31:00] */
-#define BCHP_HIF_CPUBIUCTRL_CPU_ACCESS_RIGHT_VIOL_ADDR1_VIOL_ADDR_MASK 0xffffffff
-#define BCHP_HIF_CPUBIUCTRL_CPU_ACCESS_RIGHT_VIOL_ADDR1_VIOL_ADDR_SHIFT 0
-#define BCHP_HIF_CPUBIUCTRL_CPU_ACCESS_RIGHT_VIOL_ADDR1_VIOL_ADDR_DEFAULT 0x00000000
-
-/***************************************************************************
- *CPU_ACCESS_RIGHT_VIOL_UPPER_ADDR1 - WEB CPU Access Rights Violation Upper Address1 Register
- ***************************************************************************/
-/* HIF_CPUBIUCTRL :: CPU_ACCESS_RIGHT_VIOL_UPPER_ADDR1 :: reserved0 [31:08] */
-#define BCHP_HIF_CPUBIUCTRL_CPU_ACCESS_RIGHT_VIOL_UPPER_ADDR1_reserved0_MASK 0xffffff00
-#define BCHP_HIF_CPUBIUCTRL_CPU_ACCESS_RIGHT_VIOL_UPPER_ADDR1_reserved0_SHIFT 8
-
-/* HIF_CPUBIUCTRL :: CPU_ACCESS_RIGHT_VIOL_UPPER_ADDR1 :: VIOL_UPPER_ADDR [07:00] */
-#define BCHP_HIF_CPUBIUCTRL_CPU_ACCESS_RIGHT_VIOL_UPPER_ADDR1_VIOL_UPPER_ADDR_MASK 0x000000ff
-#define BCHP_HIF_CPUBIUCTRL_CPU_ACCESS_RIGHT_VIOL_UPPER_ADDR1_VIOL_UPPER_ADDR_SHIFT 0
-#define BCHP_HIF_CPUBIUCTRL_CPU_ACCESS_RIGHT_VIOL_UPPER_ADDR1_VIOL_UPPER_ADDR_DEFAULT 0x00000000
-
-/***************************************************************************
- *CPU_ACCESS_RIGHT_VIOL_DETAIL_ADDR1 - WEB CPU Access Rights Violation Transaction Detail1 Register
- ***************************************************************************/
-/* HIF_CPUBIUCTRL :: CPU_ACCESS_RIGHT_VIOL_DETAIL_ADDR1 :: ERROR_VLD [31:31] */
-#define BCHP_HIF_CPUBIUCTRL_CPU_ACCESS_RIGHT_VIOL_DETAIL_ADDR1_ERROR_VLD_MASK 0x80000000
-#define BCHP_HIF_CPUBIUCTRL_CPU_ACCESS_RIGHT_VIOL_DETAIL_ADDR1_ERROR_VLD_SHIFT 31
-
-/* HIF_CPUBIUCTRL :: CPU_ACCESS_RIGHT_VIOL_DETAIL_ADDR1 :: reserved0 [30:30] */
-#define BCHP_HIF_CPUBIUCTRL_CPU_ACCESS_RIGHT_VIOL_DETAIL_ADDR1_reserved0_MASK 0x40000000
-#define BCHP_HIF_CPUBIUCTRL_CPU_ACCESS_RIGHT_VIOL_DETAIL_ADDR1_reserved0_SHIFT 30
-
-/* HIF_CPUBIUCTRL :: CPU_ACCESS_RIGHT_VIOL_DETAIL_ADDR1 :: CLUSTER_ID [29:26] */
-#define BCHP_HIF_CPUBIUCTRL_CPU_ACCESS_RIGHT_VIOL_DETAIL_ADDR1_CLUSTER_ID_MASK 0x3c000000
-#define BCHP_HIF_CPUBIUCTRL_CPU_ACCESS_RIGHT_VIOL_DETAIL_ADDR1_CLUSTER_ID_SHIFT 26
-
-/* HIF_CPUBIUCTRL :: CPU_ACCESS_RIGHT_VIOL_DETAIL_ADDR1 :: PROCESSOR_ID [25:24] */
-#define BCHP_HIF_CPUBIUCTRL_CPU_ACCESS_RIGHT_VIOL_DETAIL_ADDR1_PROCESSOR_ID_MASK 0x03000000
-#define BCHP_HIF_CPUBIUCTRL_CPU_ACCESS_RIGHT_VIOL_DETAIL_ADDR1_PROCESSOR_ID_SHIFT 24
-
-/* HIF_CPUBIUCTRL :: CPU_ACCESS_RIGHT_VIOL_DETAIL_ADDR1 :: reserved1 [23:23] */
-#define BCHP_HIF_CPUBIUCTRL_CPU_ACCESS_RIGHT_VIOL_DETAIL_ADDR1_reserved1_MASK 0x00800000
-#define BCHP_HIF_CPUBIUCTRL_CPU_ACCESS_RIGHT_VIOL_DETAIL_ADDR1_reserved1_SHIFT 23
-
-/* HIF_CPUBIUCTRL :: CPU_ACCESS_RIGHT_VIOL_DETAIL_ADDR1 :: INSTRUCTION_ACCESS [22:22] */
-#define BCHP_HIF_CPUBIUCTRL_CPU_ACCESS_RIGHT_VIOL_DETAIL_ADDR1_INSTRUCTION_ACCESS_MASK 0x00400000
-#define BCHP_HIF_CPUBIUCTRL_CPU_ACCESS_RIGHT_VIOL_DETAIL_ADDR1_INSTRUCTION_ACCESS_SHIFT 22
-
-/* HIF_CPUBIUCTRL :: CPU_ACCESS_RIGHT_VIOL_DETAIL_ADDR1 :: reserved2 [21:16] */
-#define BCHP_HIF_CPUBIUCTRL_CPU_ACCESS_RIGHT_VIOL_DETAIL_ADDR1_reserved2_MASK 0x003f0000
-#define BCHP_HIF_CPUBIUCTRL_CPU_ACCESS_RIGHT_VIOL_DETAIL_ADDR1_reserved2_SHIFT 16
-
-/* HIF_CPUBIUCTRL :: CPU_ACCESS_RIGHT_VIOL_DETAIL_ADDR1 :: REQUEST_SIZE [15:12] */
-#define BCHP_HIF_CPUBIUCTRL_CPU_ACCESS_RIGHT_VIOL_DETAIL_ADDR1_REQUEST_SIZE_MASK 0x0000f000
-#define BCHP_HIF_CPUBIUCTRL_CPU_ACCESS_RIGHT_VIOL_DETAIL_ADDR1_REQUEST_SIZE_SHIFT 12
-
-/* HIF_CPUBIUCTRL :: CPU_ACCESS_RIGHT_VIOL_DETAIL_ADDR1 :: UPPER_VIOL_ADDR [11:04] */
-#define BCHP_HIF_CPUBIUCTRL_CPU_ACCESS_RIGHT_VIOL_DETAIL_ADDR1_UPPER_VIOL_ADDR_MASK 0x00000ff0
-#define BCHP_HIF_CPUBIUCTRL_CPU_ACCESS_RIGHT_VIOL_DETAIL_ADDR1_UPPER_VIOL_ADDR_SHIFT 4
-#define BCHP_HIF_CPUBIUCTRL_CPU_ACCESS_RIGHT_VIOL_DETAIL_ADDR1_UPPER_VIOL_ADDR_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: CPU_ACCESS_RIGHT_VIOL_DETAIL_ADDR1 :: REQUEST_TYPE [03:00] */
-#define BCHP_HIF_CPUBIUCTRL_CPU_ACCESS_RIGHT_VIOL_DETAIL_ADDR1_REQUEST_TYPE_MASK 0x0000000f
-#define BCHP_HIF_CPUBIUCTRL_CPU_ACCESS_RIGHT_VIOL_DETAIL_ADDR1_REQUEST_TYPE_SHIFT 0
-
-/***************************************************************************
- *RAC_CONFIG0_REG - Read Ahead Cache Configuration0 Register
- ***************************************************************************/
-/* HIF_CPUBIUCTRL :: RAC_CONFIG0_REG :: RACENDATA3 [31:30] */
-#define BCHP_HIF_CPUBIUCTRL_RAC_CONFIG0_REG_RACENDATA3_MASK 0xc0000000
-#define BCHP_HIF_CPUBIUCTRL_RAC_CONFIG0_REG_RACENDATA3_SHIFT 30
-#define BCHP_HIF_CPUBIUCTRL_RAC_CONFIG0_REG_RACENDATA3_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: RAC_CONFIG0_REG :: RACPREFDATA3 [29:28] */
-#define BCHP_HIF_CPUBIUCTRL_RAC_CONFIG0_REG_RACPREFDATA3_MASK 0x30000000
-#define BCHP_HIF_CPUBIUCTRL_RAC_CONFIG0_REG_RACPREFDATA3_SHIFT 28
-#define BCHP_HIF_CPUBIUCTRL_RAC_CONFIG0_REG_RACPREFDATA3_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: RAC_CONFIG0_REG :: RACENINST3 [27:26] */
-#define BCHP_HIF_CPUBIUCTRL_RAC_CONFIG0_REG_RACENINST3_MASK 0x0c000000
-#define BCHP_HIF_CPUBIUCTRL_RAC_CONFIG0_REG_RACENINST3_SHIFT 26
-#define BCHP_HIF_CPUBIUCTRL_RAC_CONFIG0_REG_RACENINST3_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: RAC_CONFIG0_REG :: RACPREFINST3 [25:24] */
-#define BCHP_HIF_CPUBIUCTRL_RAC_CONFIG0_REG_RACPREFINST3_MASK 0x03000000
-#define BCHP_HIF_CPUBIUCTRL_RAC_CONFIG0_REG_RACPREFINST3_SHIFT 24
-#define BCHP_HIF_CPUBIUCTRL_RAC_CONFIG0_REG_RACPREFINST3_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: RAC_CONFIG0_REG :: RACENDATA2 [23:22] */
-#define BCHP_HIF_CPUBIUCTRL_RAC_CONFIG0_REG_RACENDATA2_MASK 0x00c00000
-#define BCHP_HIF_CPUBIUCTRL_RAC_CONFIG0_REG_RACENDATA2_SHIFT 22
-#define BCHP_HIF_CPUBIUCTRL_RAC_CONFIG0_REG_RACENDATA2_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: RAC_CONFIG0_REG :: RACPREFDATA2 [21:20] */
-#define BCHP_HIF_CPUBIUCTRL_RAC_CONFIG0_REG_RACPREFDATA2_MASK 0x00300000
-#define BCHP_HIF_CPUBIUCTRL_RAC_CONFIG0_REG_RACPREFDATA2_SHIFT 20
-#define BCHP_HIF_CPUBIUCTRL_RAC_CONFIG0_REG_RACPREFDATA2_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: RAC_CONFIG0_REG :: RACENINST2 [19:18] */
-#define BCHP_HIF_CPUBIUCTRL_RAC_CONFIG0_REG_RACENINST2_MASK 0x000c0000
-#define BCHP_HIF_CPUBIUCTRL_RAC_CONFIG0_REG_RACENINST2_SHIFT 18
-#define BCHP_HIF_CPUBIUCTRL_RAC_CONFIG0_REG_RACENINST2_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: RAC_CONFIG0_REG :: RACPREFINST2 [17:16] */
-#define BCHP_HIF_CPUBIUCTRL_RAC_CONFIG0_REG_RACPREFINST2_MASK 0x00030000
-#define BCHP_HIF_CPUBIUCTRL_RAC_CONFIG0_REG_RACPREFINST2_SHIFT 16
-#define BCHP_HIF_CPUBIUCTRL_RAC_CONFIG0_REG_RACPREFINST2_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: RAC_CONFIG0_REG :: RACENDATA1 [15:14] */
-#define BCHP_HIF_CPUBIUCTRL_RAC_CONFIG0_REG_RACENDATA1_MASK 0x0000c000
-#define BCHP_HIF_CPUBIUCTRL_RAC_CONFIG0_REG_RACENDATA1_SHIFT 14
-#define BCHP_HIF_CPUBIUCTRL_RAC_CONFIG0_REG_RACENDATA1_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: RAC_CONFIG0_REG :: RACPREFDATA1 [13:12] */
-#define BCHP_HIF_CPUBIUCTRL_RAC_CONFIG0_REG_RACPREFDATA1_MASK 0x00003000
-#define BCHP_HIF_CPUBIUCTRL_RAC_CONFIG0_REG_RACPREFDATA1_SHIFT 12
-#define BCHP_HIF_CPUBIUCTRL_RAC_CONFIG0_REG_RACPREFDATA1_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: RAC_CONFIG0_REG :: RACENINST1 [11:10] */
-#define BCHP_HIF_CPUBIUCTRL_RAC_CONFIG0_REG_RACENINST1_MASK 0x00000c00
-#define BCHP_HIF_CPUBIUCTRL_RAC_CONFIG0_REG_RACENINST1_SHIFT 10
-#define BCHP_HIF_CPUBIUCTRL_RAC_CONFIG0_REG_RACENINST1_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: RAC_CONFIG0_REG :: RACPREFINST1 [09:08] */
-#define BCHP_HIF_CPUBIUCTRL_RAC_CONFIG0_REG_RACPREFINST1_MASK 0x00000300
-#define BCHP_HIF_CPUBIUCTRL_RAC_CONFIG0_REG_RACPREFINST1_SHIFT 8
-#define BCHP_HIF_CPUBIUCTRL_RAC_CONFIG0_REG_RACPREFINST1_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: RAC_CONFIG0_REG :: RACENDATA0 [07:06] */
-#define BCHP_HIF_CPUBIUCTRL_RAC_CONFIG0_REG_RACENDATA0_MASK 0x000000c0
-#define BCHP_HIF_CPUBIUCTRL_RAC_CONFIG0_REG_RACENDATA0_SHIFT 6
-#define BCHP_HIF_CPUBIUCTRL_RAC_CONFIG0_REG_RACENDATA0_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: RAC_CONFIG0_REG :: RACPREFDATA0 [05:04] */
-#define BCHP_HIF_CPUBIUCTRL_RAC_CONFIG0_REG_RACPREFDATA0_MASK 0x00000030
-#define BCHP_HIF_CPUBIUCTRL_RAC_CONFIG0_REG_RACPREFDATA0_SHIFT 4
-#define BCHP_HIF_CPUBIUCTRL_RAC_CONFIG0_REG_RACPREFDATA0_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: RAC_CONFIG0_REG :: RACENINST0 [03:02] */
-#define BCHP_HIF_CPUBIUCTRL_RAC_CONFIG0_REG_RACENINST0_MASK 0x0000000c
-#define BCHP_HIF_CPUBIUCTRL_RAC_CONFIG0_REG_RACENINST0_SHIFT 2
-#define BCHP_HIF_CPUBIUCTRL_RAC_CONFIG0_REG_RACENINST0_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: RAC_CONFIG0_REG :: RACPREFINST0 [01:00] */
-#define BCHP_HIF_CPUBIUCTRL_RAC_CONFIG0_REG_RACPREFINST0_MASK 0x00000003
-#define BCHP_HIF_CPUBIUCTRL_RAC_CONFIG0_REG_RACPREFINST0_SHIFT 0
-#define BCHP_HIF_CPUBIUCTRL_RAC_CONFIG0_REG_RACPREFINST0_DEFAULT 0x00000000
-
-/***************************************************************************
- *RAC_CONFIG1_REG - Read Ahead Cache Configuration1 Register
- ***************************************************************************/
-/* HIF_CPUBIUCTRL :: RAC_CONFIG1_REG :: reserved0 [31:09] */
-#define BCHP_HIF_CPUBIUCTRL_RAC_CONFIG1_REG_reserved0_MASK 0xfffffe00
-#define BCHP_HIF_CPUBIUCTRL_RAC_CONFIG1_REG_reserved0_SHIFT 9
-
-/* HIF_CPUBIUCTRL :: RAC_CONFIG1_REG :: RAC_TBD_CTRL8 [08:08] */
-#define BCHP_HIF_CPUBIUCTRL_RAC_CONFIG1_REG_RAC_TBD_CTRL8_MASK 0x00000100
-#define BCHP_HIF_CPUBIUCTRL_RAC_CONFIG1_REG_RAC_TBD_CTRL8_SHIFT 8
-#define BCHP_HIF_CPUBIUCTRL_RAC_CONFIG1_REG_RAC_TBD_CTRL8_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: RAC_CONFIG1_REG :: RAC_TBD_CTRL7to6 [07:06] */
-#define BCHP_HIF_CPUBIUCTRL_RAC_CONFIG1_REG_RAC_TBD_CTRL7to6_MASK 0x000000c0
-#define BCHP_HIF_CPUBIUCTRL_RAC_CONFIG1_REG_RAC_TBD_CTRL7to6_SHIFT 6
-#define BCHP_HIF_CPUBIUCTRL_RAC_CONFIG1_REG_RAC_TBD_CTRL7to6_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: RAC_CONFIG1_REG :: RAC_FIFO_CTRL [05:04] */
-#define BCHP_HIF_CPUBIUCTRL_RAC_CONFIG1_REG_RAC_FIFO_CTRL_MASK 0x00000030
-#define BCHP_HIF_CPUBIUCTRL_RAC_CONFIG1_REG_RAC_FIFO_CTRL_SHIFT 4
-#define BCHP_HIF_CPUBIUCTRL_RAC_CONFIG1_REG_RAC_FIFO_CTRL_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: RAC_CONFIG1_REG :: RAC_TBD_CTRL3to1 [03:01] */
-#define BCHP_HIF_CPUBIUCTRL_RAC_CONFIG1_REG_RAC_TBD_CTRL3to1_MASK 0x0000000e
-#define BCHP_HIF_CPUBIUCTRL_RAC_CONFIG1_REG_RAC_TBD_CTRL3to1_SHIFT 1
-#define BCHP_HIF_CPUBIUCTRL_RAC_CONFIG1_REG_RAC_TBD_CTRL3to1_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: RAC_CONFIG1_REG :: UBUS_RAC_EN [00:00] */
-#define BCHP_HIF_CPUBIUCTRL_RAC_CONFIG1_REG_UBUS_RAC_EN_MASK 0x00000001
-#define BCHP_HIF_CPUBIUCTRL_RAC_CONFIG1_REG_UBUS_RAC_EN_SHIFT 0
-#define BCHP_HIF_CPUBIUCTRL_RAC_CONFIG1_REG_UBUS_RAC_EN_DEFAULT 0x00000000
-
-/***************************************************************************
- *RAC_FLUSH_REG - Read Ahead Cache Flush Register
- ***************************************************************************/
-/* HIF_CPUBIUCTRL :: RAC_FLUSH_REG :: reserved0 [31:01] */
-#define BCHP_HIF_CPUBIUCTRL_RAC_FLUSH_REG_reserved0_MASK 0xfffffffe
-#define BCHP_HIF_CPUBIUCTRL_RAC_FLUSH_REG_reserved0_SHIFT 1
-
-/* HIF_CPUBIUCTRL :: RAC_FLUSH_REG :: FLUSH_RAC [00:00] */
-#define BCHP_HIF_CPUBIUCTRL_RAC_FLUSH_REG_FLUSH_RAC_MASK 0x00000001
-#define BCHP_HIF_CPUBIUCTRL_RAC_FLUSH_REG_FLUSH_RAC_SHIFT 0
-#define BCHP_HIF_CPUBIUCTRL_RAC_FLUSH_REG_FLUSH_RAC_DEFAULT 0x00000000
-
-/***************************************************************************
- *CPU_POWER_CONFIG_REG - CPU Power Configuration Register
- ***************************************************************************/
-/* HIF_CPUBIUCTRL :: CPU_POWER_CONFIG_REG :: reserved0 [31:08] */
-#define BCHP_HIF_CPUBIUCTRL_CPU_POWER_CONFIG_REG_reserved0_MASK 0xffffff00
-#define BCHP_HIF_CPUBIUCTRL_CPU_POWER_CONFIG_REG_reserved0_SHIFT 8
-
-/* HIF_CPUBIUCTRL :: CPU_POWER_CONFIG_REG :: CPU3_BPCM_INIT_ON [07:07] */
-#define BCHP_HIF_CPUBIUCTRL_CPU_POWER_CONFIG_REG_CPU3_BPCM_INIT_ON_MASK 0x00000080
-#define BCHP_HIF_CPUBIUCTRL_CPU_POWER_CONFIG_REG_CPU3_BPCM_INIT_ON_SHIFT 7
-#define BCHP_HIF_CPUBIUCTRL_CPU_POWER_CONFIG_REG_CPU3_BPCM_INIT_ON_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: CPU_POWER_CONFIG_REG :: CPU2_BPCM_INIT_ON [06:06] */
-#define BCHP_HIF_CPUBIUCTRL_CPU_POWER_CONFIG_REG_CPU2_BPCM_INIT_ON_MASK 0x00000040
-#define BCHP_HIF_CPUBIUCTRL_CPU_POWER_CONFIG_REG_CPU2_BPCM_INIT_ON_SHIFT 6
-#define BCHP_HIF_CPUBIUCTRL_CPU_POWER_CONFIG_REG_CPU2_BPCM_INIT_ON_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: CPU_POWER_CONFIG_REG :: CPU1_BPCM_INIT_ON [05:05] */
-#define BCHP_HIF_CPUBIUCTRL_CPU_POWER_CONFIG_REG_CPU1_BPCM_INIT_ON_MASK 0x00000020
-#define BCHP_HIF_CPUBIUCTRL_CPU_POWER_CONFIG_REG_CPU1_BPCM_INIT_ON_SHIFT 5
-#define BCHP_HIF_CPUBIUCTRL_CPU_POWER_CONFIG_REG_CPU1_BPCM_INIT_ON_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: CPU_POWER_CONFIG_REG :: CPU0_BPCM_INIT_ON [04:04] */
-#define BCHP_HIF_CPUBIUCTRL_CPU_POWER_CONFIG_REG_CPU0_BPCM_INIT_ON_MASK 0x00000010
-#define BCHP_HIF_CPUBIUCTRL_CPU_POWER_CONFIG_REG_CPU0_BPCM_INIT_ON_SHIFT 4
-#define BCHP_HIF_CPUBIUCTRL_CPU_POWER_CONFIG_REG_CPU0_BPCM_INIT_ON_DEFAULT 0x00000001
-
-/* HIF_CPUBIUCTRL :: CPU_POWER_CONFIG_REG :: CPU3_BPCM_DIS [03:03] */
-#define BCHP_HIF_CPUBIUCTRL_CPU_POWER_CONFIG_REG_CPU3_BPCM_DIS_MASK 0x00000008
-#define BCHP_HIF_CPUBIUCTRL_CPU_POWER_CONFIG_REG_CPU3_BPCM_DIS_SHIFT 3
-#define BCHP_HIF_CPUBIUCTRL_CPU_POWER_CONFIG_REG_CPU3_BPCM_DIS_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: CPU_POWER_CONFIG_REG :: CPU2_BPCM_DIS [02:02] */
-#define BCHP_HIF_CPUBIUCTRL_CPU_POWER_CONFIG_REG_CPU2_BPCM_DIS_MASK 0x00000004
-#define BCHP_HIF_CPUBIUCTRL_CPU_POWER_CONFIG_REG_CPU2_BPCM_DIS_SHIFT 2
-#define BCHP_HIF_CPUBIUCTRL_CPU_POWER_CONFIG_REG_CPU2_BPCM_DIS_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: CPU_POWER_CONFIG_REG :: CPU1_BPCM_DIS [01:01] */
-#define BCHP_HIF_CPUBIUCTRL_CPU_POWER_CONFIG_REG_CPU1_BPCM_DIS_MASK 0x00000002
-#define BCHP_HIF_CPUBIUCTRL_CPU_POWER_CONFIG_REG_CPU1_BPCM_DIS_SHIFT 1
-#define BCHP_HIF_CPUBIUCTRL_CPU_POWER_CONFIG_REG_CPU1_BPCM_DIS_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: CPU_POWER_CONFIG_REG :: CPU0_BPCM_DIS [00:00] */
-#define BCHP_HIF_CPUBIUCTRL_CPU_POWER_CONFIG_REG_CPU0_BPCM_DIS_MASK 0x00000001
-#define BCHP_HIF_CPUBIUCTRL_CPU_POWER_CONFIG_REG_CPU0_BPCM_DIS_SHIFT 0
-#define BCHP_HIF_CPUBIUCTRL_CPU_POWER_CONFIG_REG_CPU0_BPCM_DIS_DEFAULT 0x00000000
-
-/***************************************************************************
- *CPU0_PWR_ZONE_CNTRL_REG - CPU0 Power Zone Control Register
- ***************************************************************************/
-/* HIF_CPUBIUCTRL :: CPU0_PWR_ZONE_CNTRL_REG :: ZONE_RESET_STATE [31:31] */
-#define BCHP_HIF_CPUBIUCTRL_CPU0_PWR_ZONE_CNTRL_REG_ZONE_RESET_STATE_MASK 0x80000000
-#define BCHP_HIF_CPUBIUCTRL_CPU0_PWR_ZONE_CNTRL_REG_ZONE_RESET_STATE_SHIFT 31
-
-/* HIF_CPUBIUCTRL :: CPU0_PWR_ZONE_CNTRL_REG :: ZONE_ISO_STATE [30:30] */
-#define BCHP_HIF_CPUBIUCTRL_CPU0_PWR_ZONE_CNTRL_REG_ZONE_ISO_STATE_MASK 0x40000000
-#define BCHP_HIF_CPUBIUCTRL_CPU0_PWR_ZONE_CNTRL_REG_ZONE_ISO_STATE_SHIFT 30
-
-/* HIF_CPUBIUCTRL :: CPU0_PWR_ZONE_CNTRL_REG :: ZONE_MEM_PWR_STATE [29:29] */
-#define BCHP_HIF_CPUBIUCTRL_CPU0_PWR_ZONE_CNTRL_REG_ZONE_MEM_PWR_STATE_MASK 0x20000000
-#define BCHP_HIF_CPUBIUCTRL_CPU0_PWR_ZONE_CNTRL_REG_ZONE_MEM_PWR_STATE_SHIFT 29
-
-/* HIF_CPUBIUCTRL :: CPU0_PWR_ZONE_CNTRL_REG :: ZONE_DPG_PWR_STATE [28:28] */
-#define BCHP_HIF_CPUBIUCTRL_CPU0_PWR_ZONE_CNTRL_REG_ZONE_DPG_PWR_STATE_MASK 0x10000000
-#define BCHP_HIF_CPUBIUCTRL_CPU0_PWR_ZONE_CNTRL_REG_ZONE_DPG_PWR_STATE_SHIFT 28
-
-/* HIF_CPUBIUCTRL :: CPU0_PWR_ZONE_CNTRL_REG :: ZONE_POWER_GOOD [27:27] */
-#define BCHP_HIF_CPUBIUCTRL_CPU0_PWR_ZONE_CNTRL_REG_ZONE_POWER_GOOD_MASK 0x08000000
-#define BCHP_HIF_CPUBIUCTRL_CPU0_PWR_ZONE_CNTRL_REG_ZONE_POWER_GOOD_SHIFT 27
-
-/* HIF_CPUBIUCTRL :: CPU0_PWR_ZONE_CNTRL_REG :: ZONE_PWR_ON_STATE [26:26] */
-#define BCHP_HIF_CPUBIUCTRL_CPU0_PWR_ZONE_CNTRL_REG_ZONE_PWR_ON_STATE_MASK 0x04000000
-#define BCHP_HIF_CPUBIUCTRL_CPU0_PWR_ZONE_CNTRL_REG_ZONE_PWR_ON_STATE_SHIFT 26
-
-/* HIF_CPUBIUCTRL :: CPU0_PWR_ZONE_CNTRL_REG :: ZONE_PWR_OFF_STATE [25:25] */
-#define BCHP_HIF_CPUBIUCTRL_CPU0_PWR_ZONE_CNTRL_REG_ZONE_PWR_OFF_STATE_MASK 0x02000000
-#define BCHP_HIF_CPUBIUCTRL_CPU0_PWR_ZONE_CNTRL_REG_ZONE_PWR_OFF_STATE_SHIFT 25
-
-/* HIF_CPUBIUCTRL :: CPU0_PWR_ZONE_CNTRL_REG :: FREQ_SCALAR_DYNAMIC_SEL [24:24] */
-#define BCHP_HIF_CPUBIUCTRL_CPU0_PWR_ZONE_CNTRL_REG_FREQ_SCALAR_DYNAMIC_SEL_MASK 0x01000000
-#define BCHP_HIF_CPUBIUCTRL_CPU0_PWR_ZONE_CNTRL_REG_FREQ_SCALAR_DYNAMIC_SEL_SHIFT 24
-
-/* HIF_CPUBIUCTRL :: CPU0_PWR_ZONE_CNTRL_REG :: ZONE_PWR_CNTL_STATE [23:19] */
-#define BCHP_HIF_CPUBIUCTRL_CPU0_PWR_ZONE_CNTRL_REG_ZONE_PWR_CNTL_STATE_MASK 0x00f80000
-#define BCHP_HIF_CPUBIUCTRL_CPU0_PWR_ZONE_CNTRL_REG_ZONE_PWR_CNTL_STATE_SHIFT 19
-
-/* HIF_CPUBIUCTRL :: CPU0_PWR_ZONE_CNTRL_REG :: reserved0 [18:14] */
-#define BCHP_HIF_CPUBIUCTRL_CPU0_PWR_ZONE_CNTRL_REG_reserved0_MASK 0x0007c000
-#define BCHP_HIF_CPUBIUCTRL_CPU0_PWR_ZONE_CNTRL_REG_reserved0_SHIFT 14
-
-/* HIF_CPUBIUCTRL :: CPU0_PWR_ZONE_CNTRL_REG :: ZONE_MEM_STBY [13:13] */
-#define BCHP_HIF_CPUBIUCTRL_CPU0_PWR_ZONE_CNTRL_REG_ZONE_MEM_STBY_MASK 0x00002000
-#define BCHP_HIF_CPUBIUCTRL_CPU0_PWR_ZONE_CNTRL_REG_ZONE_MEM_STBY_SHIFT 13
-
-/* HIF_CPUBIUCTRL :: CPU0_PWR_ZONE_CNTRL_REG :: ZONE_BLK_RST_ASSERT [12:12] */
-#define BCHP_HIF_CPUBIUCTRL_CPU0_PWR_ZONE_CNTRL_REG_ZONE_BLK_RST_ASSERT_MASK 0x00001000
-#define BCHP_HIF_CPUBIUCTRL_CPU0_PWR_ZONE_CNTRL_REG_ZONE_BLK_RST_ASSERT_SHIFT 12
-#define BCHP_HIF_CPUBIUCTRL_CPU0_PWR_ZONE_CNTRL_REG_ZONE_BLK_RST_ASSERT_DEFAULT 0x00000001
-
-/* HIF_CPUBIUCTRL :: CPU0_PWR_ZONE_CNTRL_REG :: ZONE_MEM_PWR_CNTL_EN [11:11] */
-#define BCHP_HIF_CPUBIUCTRL_CPU0_PWR_ZONE_CNTRL_REG_ZONE_MEM_PWR_CNTL_EN_MASK 0x00000800
-#define BCHP_HIF_CPUBIUCTRL_CPU0_PWR_ZONE_CNTRL_REG_ZONE_MEM_PWR_CNTL_EN_SHIFT 11
-#define BCHP_HIF_CPUBIUCTRL_CPU0_PWR_ZONE_CNTRL_REG_ZONE_MEM_PWR_CNTL_EN_DEFAULT 0x00000001
-
-/* HIF_CPUBIUCTRL :: CPU0_PWR_ZONE_CNTRL_REG :: ZONE_PWR_UP_REQ [10:10] */
-#define BCHP_HIF_CPUBIUCTRL_CPU0_PWR_ZONE_CNTRL_REG_ZONE_PWR_UP_REQ_MASK 0x00000400
-#define BCHP_HIF_CPUBIUCTRL_CPU0_PWR_ZONE_CNTRL_REG_ZONE_PWR_UP_REQ_SHIFT 10
-#define BCHP_HIF_CPUBIUCTRL_CPU0_PWR_ZONE_CNTRL_REG_ZONE_PWR_UP_REQ_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: CPU0_PWR_ZONE_CNTRL_REG :: ZONE_PWR_DN_REQ [09:09] */
-#define BCHP_HIF_CPUBIUCTRL_CPU0_PWR_ZONE_CNTRL_REG_ZONE_PWR_DN_REQ_MASK 0x00000200
-#define BCHP_HIF_CPUBIUCTRL_CPU0_PWR_ZONE_CNTRL_REG_ZONE_PWR_DN_REQ_SHIFT 9
-#define BCHP_HIF_CPUBIUCTRL_CPU0_PWR_ZONE_CNTRL_REG_ZONE_PWR_DN_REQ_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: CPU0_PWR_ZONE_CNTRL_REG :: ZONE_DPG_CNTL_EN [08:08] */
-#define BCHP_HIF_CPUBIUCTRL_CPU0_PWR_ZONE_CNTRL_REG_ZONE_DPG_CNTL_EN_MASK 0x00000100
-#define BCHP_HIF_CPUBIUCTRL_CPU0_PWR_ZONE_CNTRL_REG_ZONE_DPG_CNTL_EN_SHIFT 8
-#define BCHP_HIF_CPUBIUCTRL_CPU0_PWR_ZONE_CNTRL_REG_ZONE_DPG_CNTL_EN_DEFAULT 0x00000001
-
-/* HIF_CPUBIUCTRL :: CPU0_PWR_ZONE_CNTRL_REG :: ZONE_MANUAL_CONTROL [07:07] */
-#define BCHP_HIF_CPUBIUCTRL_CPU0_PWR_ZONE_CNTRL_REG_ZONE_MANUAL_CONTROL_MASK 0x00000080
-#define BCHP_HIF_CPUBIUCTRL_CPU0_PWR_ZONE_CNTRL_REG_ZONE_MANUAL_CONTROL_SHIFT 7
-#define BCHP_HIF_CPUBIUCTRL_CPU0_PWR_ZONE_CNTRL_REG_ZONE_MANUAL_CONTROL_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: CPU0_PWR_ZONE_CNTRL_REG :: ZONE_MAN_ISO_CNTL [06:06] */
-#define BCHP_HIF_CPUBIUCTRL_CPU0_PWR_ZONE_CNTRL_REG_ZONE_MAN_ISO_CNTL_MASK 0x00000040
-#define BCHP_HIF_CPUBIUCTRL_CPU0_PWR_ZONE_CNTRL_REG_ZONE_MAN_ISO_CNTL_SHIFT 6
-#define BCHP_HIF_CPUBIUCTRL_CPU0_PWR_ZONE_CNTRL_REG_ZONE_MAN_ISO_CNTL_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: CPU0_PWR_ZONE_CNTRL_REG :: reserved1 [05:05] */
-#define BCHP_HIF_CPUBIUCTRL_CPU0_PWR_ZONE_CNTRL_REG_reserved1_MASK 0x00000020
-#define BCHP_HIF_CPUBIUCTRL_CPU0_PWR_ZONE_CNTRL_REG_reserved1_SHIFT 5
-
-/* HIF_CPUBIUCTRL :: CPU0_PWR_ZONE_CNTRL_REG :: ZONE_MAN_MEM_PWR [04:04] */
-#define BCHP_HIF_CPUBIUCTRL_CPU0_PWR_ZONE_CNTRL_REG_ZONE_MAN_MEM_PWR_MASK 0x00000010
-#define BCHP_HIF_CPUBIUCTRL_CPU0_PWR_ZONE_CNTRL_REG_ZONE_MAN_MEM_PWR_SHIFT 4
-#define BCHP_HIF_CPUBIUCTRL_CPU0_PWR_ZONE_CNTRL_REG_ZONE_MAN_MEM_PWR_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: CPU0_PWR_ZONE_CNTRL_REG :: ZONE_DPG_CAPABLE [03:03] */
-#define BCHP_HIF_CPUBIUCTRL_CPU0_PWR_ZONE_CNTRL_REG_ZONE_DPG_CAPABLE_MASK 0x00000008
-#define BCHP_HIF_CPUBIUCTRL_CPU0_PWR_ZONE_CNTRL_REG_ZONE_DPG_CAPABLE_SHIFT 3
-
-/* HIF_CPUBIUCTRL :: CPU0_PWR_ZONE_CNTRL_REG :: ZONE_FREQ_SCALE_USED [02:02] */
-#define BCHP_HIF_CPUBIUCTRL_CPU0_PWR_ZONE_CNTRL_REG_ZONE_FREQ_SCALE_USED_MASK 0x00000004
-#define BCHP_HIF_CPUBIUCTRL_CPU0_PWR_ZONE_CNTRL_REG_ZONE_FREQ_SCALE_USED_SHIFT 2
-
-/* HIF_CPUBIUCTRL :: CPU0_PWR_ZONE_CNTRL_REG :: ZONE_MAN_RESET_CNTL [01:01] */
-#define BCHP_HIF_CPUBIUCTRL_CPU0_PWR_ZONE_CNTRL_REG_ZONE_MAN_RESET_CNTL_MASK 0x00000002
-#define BCHP_HIF_CPUBIUCTRL_CPU0_PWR_ZONE_CNTRL_REG_ZONE_MAN_RESET_CNTL_SHIFT 1
-#define BCHP_HIF_CPUBIUCTRL_CPU0_PWR_ZONE_CNTRL_REG_ZONE_MAN_RESET_CNTL_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: CPU0_PWR_ZONE_CNTRL_REG :: ZONE_MAN_CLKEN [00:00] */
-#define BCHP_HIF_CPUBIUCTRL_CPU0_PWR_ZONE_CNTRL_REG_ZONE_MAN_CLKEN_MASK 0x00000001
-#define BCHP_HIF_CPUBIUCTRL_CPU0_PWR_ZONE_CNTRL_REG_ZONE_MAN_CLKEN_SHIFT 0
-#define BCHP_HIF_CPUBIUCTRL_CPU0_PWR_ZONE_CNTRL_REG_ZONE_MAN_CLKEN_DEFAULT 0x00000000
-
-/***************************************************************************
- *CPU1_PWR_ZONE_CNTRL_REG - CPU1 Power Zone Control Register
- ***************************************************************************/
-/* HIF_CPUBIUCTRL :: CPU1_PWR_ZONE_CNTRL_REG :: ZONE_RESET_STATE [31:31] */
-#define BCHP_HIF_CPUBIUCTRL_CPU1_PWR_ZONE_CNTRL_REG_ZONE_RESET_STATE_MASK 0x80000000
-#define BCHP_HIF_CPUBIUCTRL_CPU1_PWR_ZONE_CNTRL_REG_ZONE_RESET_STATE_SHIFT 31
-
-/* HIF_CPUBIUCTRL :: CPU1_PWR_ZONE_CNTRL_REG :: ZONE_ISO_STATE [30:30] */
-#define BCHP_HIF_CPUBIUCTRL_CPU1_PWR_ZONE_CNTRL_REG_ZONE_ISO_STATE_MASK 0x40000000
-#define BCHP_HIF_CPUBIUCTRL_CPU1_PWR_ZONE_CNTRL_REG_ZONE_ISO_STATE_SHIFT 30
-
-/* HIF_CPUBIUCTRL :: CPU1_PWR_ZONE_CNTRL_REG :: ZONE_MEM_PWR_STATE [29:29] */
-#define BCHP_HIF_CPUBIUCTRL_CPU1_PWR_ZONE_CNTRL_REG_ZONE_MEM_PWR_STATE_MASK 0x20000000
-#define BCHP_HIF_CPUBIUCTRL_CPU1_PWR_ZONE_CNTRL_REG_ZONE_MEM_PWR_STATE_SHIFT 29
-
-/* HIF_CPUBIUCTRL :: CPU1_PWR_ZONE_CNTRL_REG :: ZONE_DPG_PWR_STATE [28:28] */
-#define BCHP_HIF_CPUBIUCTRL_CPU1_PWR_ZONE_CNTRL_REG_ZONE_DPG_PWR_STATE_MASK 0x10000000
-#define BCHP_HIF_CPUBIUCTRL_CPU1_PWR_ZONE_CNTRL_REG_ZONE_DPG_PWR_STATE_SHIFT 28
-
-/* HIF_CPUBIUCTRL :: CPU1_PWR_ZONE_CNTRL_REG :: ZONE_POWER_GOOD [27:27] */
-#define BCHP_HIF_CPUBIUCTRL_CPU1_PWR_ZONE_CNTRL_REG_ZONE_POWER_GOOD_MASK 0x08000000
-#define BCHP_HIF_CPUBIUCTRL_CPU1_PWR_ZONE_CNTRL_REG_ZONE_POWER_GOOD_SHIFT 27
-
-/* HIF_CPUBIUCTRL :: CPU1_PWR_ZONE_CNTRL_REG :: ZONE_PWR_ON_STATE [26:26] */
-#define BCHP_HIF_CPUBIUCTRL_CPU1_PWR_ZONE_CNTRL_REG_ZONE_PWR_ON_STATE_MASK 0x04000000
-#define BCHP_HIF_CPUBIUCTRL_CPU1_PWR_ZONE_CNTRL_REG_ZONE_PWR_ON_STATE_SHIFT 26
-
-/* HIF_CPUBIUCTRL :: CPU1_PWR_ZONE_CNTRL_REG :: ZONE_PWR_OFF_STATE [25:25] */
-#define BCHP_HIF_CPUBIUCTRL_CPU1_PWR_ZONE_CNTRL_REG_ZONE_PWR_OFF_STATE_MASK 0x02000000
-#define BCHP_HIF_CPUBIUCTRL_CPU1_PWR_ZONE_CNTRL_REG_ZONE_PWR_OFF_STATE_SHIFT 25
-
-/* HIF_CPUBIUCTRL :: CPU1_PWR_ZONE_CNTRL_REG :: FREQ_SCALAR_DYNAMIC_SEL [24:24] */
-#define BCHP_HIF_CPUBIUCTRL_CPU1_PWR_ZONE_CNTRL_REG_FREQ_SCALAR_DYNAMIC_SEL_MASK 0x01000000
-#define BCHP_HIF_CPUBIUCTRL_CPU1_PWR_ZONE_CNTRL_REG_FREQ_SCALAR_DYNAMIC_SEL_SHIFT 24
-
-/* HIF_CPUBIUCTRL :: CPU1_PWR_ZONE_CNTRL_REG :: ZONE_PWR_CNTL_STATE [23:19] */
-#define BCHP_HIF_CPUBIUCTRL_CPU1_PWR_ZONE_CNTRL_REG_ZONE_PWR_CNTL_STATE_MASK 0x00f80000
-#define BCHP_HIF_CPUBIUCTRL_CPU1_PWR_ZONE_CNTRL_REG_ZONE_PWR_CNTL_STATE_SHIFT 19
-
-/* HIF_CPUBIUCTRL :: CPU1_PWR_ZONE_CNTRL_REG :: reserved0 [18:14] */
-#define BCHP_HIF_CPUBIUCTRL_CPU1_PWR_ZONE_CNTRL_REG_reserved0_MASK 0x0007c000
-#define BCHP_HIF_CPUBIUCTRL_CPU1_PWR_ZONE_CNTRL_REG_reserved0_SHIFT 14
-
-/* HIF_CPUBIUCTRL :: CPU1_PWR_ZONE_CNTRL_REG :: ZONE_MEM_STBY [13:13] */
-#define BCHP_HIF_CPUBIUCTRL_CPU1_PWR_ZONE_CNTRL_REG_ZONE_MEM_STBY_MASK 0x00002000
-#define BCHP_HIF_CPUBIUCTRL_CPU1_PWR_ZONE_CNTRL_REG_ZONE_MEM_STBY_SHIFT 13
-
-/* HIF_CPUBIUCTRL :: CPU1_PWR_ZONE_CNTRL_REG :: ZONE_BLK_RST_ASSERT [12:12] */
-#define BCHP_HIF_CPUBIUCTRL_CPU1_PWR_ZONE_CNTRL_REG_ZONE_BLK_RST_ASSERT_MASK 0x00001000
-#define BCHP_HIF_CPUBIUCTRL_CPU1_PWR_ZONE_CNTRL_REG_ZONE_BLK_RST_ASSERT_SHIFT 12
-#define BCHP_HIF_CPUBIUCTRL_CPU1_PWR_ZONE_CNTRL_REG_ZONE_BLK_RST_ASSERT_DEFAULT 0x00000001
-
-/* HIF_CPUBIUCTRL :: CPU1_PWR_ZONE_CNTRL_REG :: ZONE_MEM_PWR_CNTL_EN [11:11] */
-#define BCHP_HIF_CPUBIUCTRL_CPU1_PWR_ZONE_CNTRL_REG_ZONE_MEM_PWR_CNTL_EN_MASK 0x00000800
-#define BCHP_HIF_CPUBIUCTRL_CPU1_PWR_ZONE_CNTRL_REG_ZONE_MEM_PWR_CNTL_EN_SHIFT 11
-#define BCHP_HIF_CPUBIUCTRL_CPU1_PWR_ZONE_CNTRL_REG_ZONE_MEM_PWR_CNTL_EN_DEFAULT 0x00000001
-
-/* HIF_CPUBIUCTRL :: CPU1_PWR_ZONE_CNTRL_REG :: ZONE_PWR_UP_REQ [10:10] */
-#define BCHP_HIF_CPUBIUCTRL_CPU1_PWR_ZONE_CNTRL_REG_ZONE_PWR_UP_REQ_MASK 0x00000400
-#define BCHP_HIF_CPUBIUCTRL_CPU1_PWR_ZONE_CNTRL_REG_ZONE_PWR_UP_REQ_SHIFT 10
-#define BCHP_HIF_CPUBIUCTRL_CPU1_PWR_ZONE_CNTRL_REG_ZONE_PWR_UP_REQ_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: CPU1_PWR_ZONE_CNTRL_REG :: ZONE_PWR_DN_REQ [09:09] */
-#define BCHP_HIF_CPUBIUCTRL_CPU1_PWR_ZONE_CNTRL_REG_ZONE_PWR_DN_REQ_MASK 0x00000200
-#define BCHP_HIF_CPUBIUCTRL_CPU1_PWR_ZONE_CNTRL_REG_ZONE_PWR_DN_REQ_SHIFT 9
-#define BCHP_HIF_CPUBIUCTRL_CPU1_PWR_ZONE_CNTRL_REG_ZONE_PWR_DN_REQ_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: CPU1_PWR_ZONE_CNTRL_REG :: ZONE_DPG_CNTL_EN [08:08] */
-#define BCHP_HIF_CPUBIUCTRL_CPU1_PWR_ZONE_CNTRL_REG_ZONE_DPG_CNTL_EN_MASK 0x00000100
-#define BCHP_HIF_CPUBIUCTRL_CPU1_PWR_ZONE_CNTRL_REG_ZONE_DPG_CNTL_EN_SHIFT 8
-#define BCHP_HIF_CPUBIUCTRL_CPU1_PWR_ZONE_CNTRL_REG_ZONE_DPG_CNTL_EN_DEFAULT 0x00000001
-
-/* HIF_CPUBIUCTRL :: CPU1_PWR_ZONE_CNTRL_REG :: ZONE_MANUAL_CONTROL [07:07] */
-#define BCHP_HIF_CPUBIUCTRL_CPU1_PWR_ZONE_CNTRL_REG_ZONE_MANUAL_CONTROL_MASK 0x00000080
-#define BCHP_HIF_CPUBIUCTRL_CPU1_PWR_ZONE_CNTRL_REG_ZONE_MANUAL_CONTROL_SHIFT 7
-#define BCHP_HIF_CPUBIUCTRL_CPU1_PWR_ZONE_CNTRL_REG_ZONE_MANUAL_CONTROL_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: CPU1_PWR_ZONE_CNTRL_REG :: ZONE_MAN_ISO_CNTL [06:06] */
-#define BCHP_HIF_CPUBIUCTRL_CPU1_PWR_ZONE_CNTRL_REG_ZONE_MAN_ISO_CNTL_MASK 0x00000040
-#define BCHP_HIF_CPUBIUCTRL_CPU1_PWR_ZONE_CNTRL_REG_ZONE_MAN_ISO_CNTL_SHIFT 6
-#define BCHP_HIF_CPUBIUCTRL_CPU1_PWR_ZONE_CNTRL_REG_ZONE_MAN_ISO_CNTL_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: CPU1_PWR_ZONE_CNTRL_REG :: reserved1 [05:05] */
-#define BCHP_HIF_CPUBIUCTRL_CPU1_PWR_ZONE_CNTRL_REG_reserved1_MASK 0x00000020
-#define BCHP_HIF_CPUBIUCTRL_CPU1_PWR_ZONE_CNTRL_REG_reserved1_SHIFT 5
-
-/* HIF_CPUBIUCTRL :: CPU1_PWR_ZONE_CNTRL_REG :: ZONE_MAN_MEM_PWR [04:04] */
-#define BCHP_HIF_CPUBIUCTRL_CPU1_PWR_ZONE_CNTRL_REG_ZONE_MAN_MEM_PWR_MASK 0x00000010
-#define BCHP_HIF_CPUBIUCTRL_CPU1_PWR_ZONE_CNTRL_REG_ZONE_MAN_MEM_PWR_SHIFT 4
-#define BCHP_HIF_CPUBIUCTRL_CPU1_PWR_ZONE_CNTRL_REG_ZONE_MAN_MEM_PWR_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: CPU1_PWR_ZONE_CNTRL_REG :: ZONE_DPG_CAPABLE [03:03] */
-#define BCHP_HIF_CPUBIUCTRL_CPU1_PWR_ZONE_CNTRL_REG_ZONE_DPG_CAPABLE_MASK 0x00000008
-#define BCHP_HIF_CPUBIUCTRL_CPU1_PWR_ZONE_CNTRL_REG_ZONE_DPG_CAPABLE_SHIFT 3
-
-/* HIF_CPUBIUCTRL :: CPU1_PWR_ZONE_CNTRL_REG :: ZONE_FREQ_SCALE_USED [02:02] */
-#define BCHP_HIF_CPUBIUCTRL_CPU1_PWR_ZONE_CNTRL_REG_ZONE_FREQ_SCALE_USED_MASK 0x00000004
-#define BCHP_HIF_CPUBIUCTRL_CPU1_PWR_ZONE_CNTRL_REG_ZONE_FREQ_SCALE_USED_SHIFT 2
-
-/* HIF_CPUBIUCTRL :: CPU1_PWR_ZONE_CNTRL_REG :: ZONE_MAN_RESET_CNTL [01:01] */
-#define BCHP_HIF_CPUBIUCTRL_CPU1_PWR_ZONE_CNTRL_REG_ZONE_MAN_RESET_CNTL_MASK 0x00000002
-#define BCHP_HIF_CPUBIUCTRL_CPU1_PWR_ZONE_CNTRL_REG_ZONE_MAN_RESET_CNTL_SHIFT 1
-#define BCHP_HIF_CPUBIUCTRL_CPU1_PWR_ZONE_CNTRL_REG_ZONE_MAN_RESET_CNTL_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: CPU1_PWR_ZONE_CNTRL_REG :: ZONE_MAN_CLKEN [00:00] */
-#define BCHP_HIF_CPUBIUCTRL_CPU1_PWR_ZONE_CNTRL_REG_ZONE_MAN_CLKEN_MASK 0x00000001
-#define BCHP_HIF_CPUBIUCTRL_CPU1_PWR_ZONE_CNTRL_REG_ZONE_MAN_CLKEN_SHIFT 0
-#define BCHP_HIF_CPUBIUCTRL_CPU1_PWR_ZONE_CNTRL_REG_ZONE_MAN_CLKEN_DEFAULT 0x00000000
-
-/***************************************************************************
- *CPU2_PWR_ZONE_CNTRL_REG - CPU2 Power Zone Control Register
- ***************************************************************************/
-/* HIF_CPUBIUCTRL :: CPU2_PWR_ZONE_CNTRL_REG :: ZONE_RESET_STATE [31:31] */
-#define BCHP_HIF_CPUBIUCTRL_CPU2_PWR_ZONE_CNTRL_REG_ZONE_RESET_STATE_MASK 0x80000000
-#define BCHP_HIF_CPUBIUCTRL_CPU2_PWR_ZONE_CNTRL_REG_ZONE_RESET_STATE_SHIFT 31
-
-/* HIF_CPUBIUCTRL :: CPU2_PWR_ZONE_CNTRL_REG :: ZONE_ISO_STATE [30:30] */
-#define BCHP_HIF_CPUBIUCTRL_CPU2_PWR_ZONE_CNTRL_REG_ZONE_ISO_STATE_MASK 0x40000000
-#define BCHP_HIF_CPUBIUCTRL_CPU2_PWR_ZONE_CNTRL_REG_ZONE_ISO_STATE_SHIFT 30
-
-/* HIF_CPUBIUCTRL :: CPU2_PWR_ZONE_CNTRL_REG :: ZONE_MEM_PWR_STATE [29:29] */
-#define BCHP_HIF_CPUBIUCTRL_CPU2_PWR_ZONE_CNTRL_REG_ZONE_MEM_PWR_STATE_MASK 0x20000000
-#define BCHP_HIF_CPUBIUCTRL_CPU2_PWR_ZONE_CNTRL_REG_ZONE_MEM_PWR_STATE_SHIFT 29
-
-/* HIF_CPUBIUCTRL :: CPU2_PWR_ZONE_CNTRL_REG :: ZONE_DPG_PWR_STATE [28:28] */
-#define BCHP_HIF_CPUBIUCTRL_CPU2_PWR_ZONE_CNTRL_REG_ZONE_DPG_PWR_STATE_MASK 0x10000000
-#define BCHP_HIF_CPUBIUCTRL_CPU2_PWR_ZONE_CNTRL_REG_ZONE_DPG_PWR_STATE_SHIFT 28
-
-/* HIF_CPUBIUCTRL :: CPU2_PWR_ZONE_CNTRL_REG :: ZONE_POWER_GOOD [27:27] */
-#define BCHP_HIF_CPUBIUCTRL_CPU2_PWR_ZONE_CNTRL_REG_ZONE_POWER_GOOD_MASK 0x08000000
-#define BCHP_HIF_CPUBIUCTRL_CPU2_PWR_ZONE_CNTRL_REG_ZONE_POWER_GOOD_SHIFT 27
-
-/* HIF_CPUBIUCTRL :: CPU2_PWR_ZONE_CNTRL_REG :: ZONE_PWR_ON_STATE [26:26] */
-#define BCHP_HIF_CPUBIUCTRL_CPU2_PWR_ZONE_CNTRL_REG_ZONE_PWR_ON_STATE_MASK 0x04000000
-#define BCHP_HIF_CPUBIUCTRL_CPU2_PWR_ZONE_CNTRL_REG_ZONE_PWR_ON_STATE_SHIFT 26
-
-/* HIF_CPUBIUCTRL :: CPU2_PWR_ZONE_CNTRL_REG :: ZONE_PWR_OFF_STATE [25:25] */
-#define BCHP_HIF_CPUBIUCTRL_CPU2_PWR_ZONE_CNTRL_REG_ZONE_PWR_OFF_STATE_MASK 0x02000000
-#define BCHP_HIF_CPUBIUCTRL_CPU2_PWR_ZONE_CNTRL_REG_ZONE_PWR_OFF_STATE_SHIFT 25
-
-/* HIF_CPUBIUCTRL :: CPU2_PWR_ZONE_CNTRL_REG :: FREQ_SCALAR_DYNAMIC_SEL [24:24] */
-#define BCHP_HIF_CPUBIUCTRL_CPU2_PWR_ZONE_CNTRL_REG_FREQ_SCALAR_DYNAMIC_SEL_MASK 0x01000000
-#define BCHP_HIF_CPUBIUCTRL_CPU2_PWR_ZONE_CNTRL_REG_FREQ_SCALAR_DYNAMIC_SEL_SHIFT 24
-
-/* HIF_CPUBIUCTRL :: CPU2_PWR_ZONE_CNTRL_REG :: ZONE_PWR_CNTL_STATE [23:19] */
-#define BCHP_HIF_CPUBIUCTRL_CPU2_PWR_ZONE_CNTRL_REG_ZONE_PWR_CNTL_STATE_MASK 0x00f80000
-#define BCHP_HIF_CPUBIUCTRL_CPU2_PWR_ZONE_CNTRL_REG_ZONE_PWR_CNTL_STATE_SHIFT 19
-
-/* HIF_CPUBIUCTRL :: CPU2_PWR_ZONE_CNTRL_REG :: reserved0 [18:14] */
-#define BCHP_HIF_CPUBIUCTRL_CPU2_PWR_ZONE_CNTRL_REG_reserved0_MASK 0x0007c000
-#define BCHP_HIF_CPUBIUCTRL_CPU2_PWR_ZONE_CNTRL_REG_reserved0_SHIFT 14
-
-/* HIF_CPUBIUCTRL :: CPU2_PWR_ZONE_CNTRL_REG :: ZONE_MEM_STBY [13:13] */
-#define BCHP_HIF_CPUBIUCTRL_CPU2_PWR_ZONE_CNTRL_REG_ZONE_MEM_STBY_MASK 0x00002000
-#define BCHP_HIF_CPUBIUCTRL_CPU2_PWR_ZONE_CNTRL_REG_ZONE_MEM_STBY_SHIFT 13
-
-/* HIF_CPUBIUCTRL :: CPU2_PWR_ZONE_CNTRL_REG :: ZONE_BLK_RST_ASSERT [12:12] */
-#define BCHP_HIF_CPUBIUCTRL_CPU2_PWR_ZONE_CNTRL_REG_ZONE_BLK_RST_ASSERT_MASK 0x00001000
-#define BCHP_HIF_CPUBIUCTRL_CPU2_PWR_ZONE_CNTRL_REG_ZONE_BLK_RST_ASSERT_SHIFT 12
-#define BCHP_HIF_CPUBIUCTRL_CPU2_PWR_ZONE_CNTRL_REG_ZONE_BLK_RST_ASSERT_DEFAULT 0x00000001
-
-/* HIF_CPUBIUCTRL :: CPU2_PWR_ZONE_CNTRL_REG :: ZONE_MEM_PWR_CNTL_EN [11:11] */
-#define BCHP_HIF_CPUBIUCTRL_CPU2_PWR_ZONE_CNTRL_REG_ZONE_MEM_PWR_CNTL_EN_MASK 0x00000800
-#define BCHP_HIF_CPUBIUCTRL_CPU2_PWR_ZONE_CNTRL_REG_ZONE_MEM_PWR_CNTL_EN_SHIFT 11
-#define BCHP_HIF_CPUBIUCTRL_CPU2_PWR_ZONE_CNTRL_REG_ZONE_MEM_PWR_CNTL_EN_DEFAULT 0x00000001
-
-/* HIF_CPUBIUCTRL :: CPU2_PWR_ZONE_CNTRL_REG :: ZONE_PWR_UP_REQ [10:10] */
-#define BCHP_HIF_CPUBIUCTRL_CPU2_PWR_ZONE_CNTRL_REG_ZONE_PWR_UP_REQ_MASK 0x00000400
-#define BCHP_HIF_CPUBIUCTRL_CPU2_PWR_ZONE_CNTRL_REG_ZONE_PWR_UP_REQ_SHIFT 10
-#define BCHP_HIF_CPUBIUCTRL_CPU2_PWR_ZONE_CNTRL_REG_ZONE_PWR_UP_REQ_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: CPU2_PWR_ZONE_CNTRL_REG :: ZONE_PWR_DN_REQ [09:09] */
-#define BCHP_HIF_CPUBIUCTRL_CPU2_PWR_ZONE_CNTRL_REG_ZONE_PWR_DN_REQ_MASK 0x00000200
-#define BCHP_HIF_CPUBIUCTRL_CPU2_PWR_ZONE_CNTRL_REG_ZONE_PWR_DN_REQ_SHIFT 9
-#define BCHP_HIF_CPUBIUCTRL_CPU2_PWR_ZONE_CNTRL_REG_ZONE_PWR_DN_REQ_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: CPU2_PWR_ZONE_CNTRL_REG :: ZONE_DPG_CNTL_EN [08:08] */
-#define BCHP_HIF_CPUBIUCTRL_CPU2_PWR_ZONE_CNTRL_REG_ZONE_DPG_CNTL_EN_MASK 0x00000100
-#define BCHP_HIF_CPUBIUCTRL_CPU2_PWR_ZONE_CNTRL_REG_ZONE_DPG_CNTL_EN_SHIFT 8
-#define BCHP_HIF_CPUBIUCTRL_CPU2_PWR_ZONE_CNTRL_REG_ZONE_DPG_CNTL_EN_DEFAULT 0x00000001
-
-/* HIF_CPUBIUCTRL :: CPU2_PWR_ZONE_CNTRL_REG :: ZONE_MANUAL_CONTROL [07:07] */
-#define BCHP_HIF_CPUBIUCTRL_CPU2_PWR_ZONE_CNTRL_REG_ZONE_MANUAL_CONTROL_MASK 0x00000080
-#define BCHP_HIF_CPUBIUCTRL_CPU2_PWR_ZONE_CNTRL_REG_ZONE_MANUAL_CONTROL_SHIFT 7
-#define BCHP_HIF_CPUBIUCTRL_CPU2_PWR_ZONE_CNTRL_REG_ZONE_MANUAL_CONTROL_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: CPU2_PWR_ZONE_CNTRL_REG :: ZONE_MAN_ISO_CNTL [06:06] */
-#define BCHP_HIF_CPUBIUCTRL_CPU2_PWR_ZONE_CNTRL_REG_ZONE_MAN_ISO_CNTL_MASK 0x00000040
-#define BCHP_HIF_CPUBIUCTRL_CPU2_PWR_ZONE_CNTRL_REG_ZONE_MAN_ISO_CNTL_SHIFT 6
-#define BCHP_HIF_CPUBIUCTRL_CPU2_PWR_ZONE_CNTRL_REG_ZONE_MAN_ISO_CNTL_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: CPU2_PWR_ZONE_CNTRL_REG :: reserved1 [05:05] */
-#define BCHP_HIF_CPUBIUCTRL_CPU2_PWR_ZONE_CNTRL_REG_reserved1_MASK 0x00000020
-#define BCHP_HIF_CPUBIUCTRL_CPU2_PWR_ZONE_CNTRL_REG_reserved1_SHIFT 5
-
-/* HIF_CPUBIUCTRL :: CPU2_PWR_ZONE_CNTRL_REG :: ZONE_MAN_MEM_PWR [04:04] */
-#define BCHP_HIF_CPUBIUCTRL_CPU2_PWR_ZONE_CNTRL_REG_ZONE_MAN_MEM_PWR_MASK 0x00000010
-#define BCHP_HIF_CPUBIUCTRL_CPU2_PWR_ZONE_CNTRL_REG_ZONE_MAN_MEM_PWR_SHIFT 4
-#define BCHP_HIF_CPUBIUCTRL_CPU2_PWR_ZONE_CNTRL_REG_ZONE_MAN_MEM_PWR_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: CPU2_PWR_ZONE_CNTRL_REG :: ZONE_DPG_CAPABLE [03:03] */
-#define BCHP_HIF_CPUBIUCTRL_CPU2_PWR_ZONE_CNTRL_REG_ZONE_DPG_CAPABLE_MASK 0x00000008
-#define BCHP_HIF_CPUBIUCTRL_CPU2_PWR_ZONE_CNTRL_REG_ZONE_DPG_CAPABLE_SHIFT 3
-
-/* HIF_CPUBIUCTRL :: CPU2_PWR_ZONE_CNTRL_REG :: ZONE_FREQ_SCALE_USED [02:02] */
-#define BCHP_HIF_CPUBIUCTRL_CPU2_PWR_ZONE_CNTRL_REG_ZONE_FREQ_SCALE_USED_MASK 0x00000004
-#define BCHP_HIF_CPUBIUCTRL_CPU2_PWR_ZONE_CNTRL_REG_ZONE_FREQ_SCALE_USED_SHIFT 2
-
-/* HIF_CPUBIUCTRL :: CPU2_PWR_ZONE_CNTRL_REG :: ZONE_MAN_RESET_CNTL [01:01] */
-#define BCHP_HIF_CPUBIUCTRL_CPU2_PWR_ZONE_CNTRL_REG_ZONE_MAN_RESET_CNTL_MASK 0x00000002
-#define BCHP_HIF_CPUBIUCTRL_CPU2_PWR_ZONE_CNTRL_REG_ZONE_MAN_RESET_CNTL_SHIFT 1
-#define BCHP_HIF_CPUBIUCTRL_CPU2_PWR_ZONE_CNTRL_REG_ZONE_MAN_RESET_CNTL_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: CPU2_PWR_ZONE_CNTRL_REG :: ZONE_MAN_CLKEN [00:00] */
-#define BCHP_HIF_CPUBIUCTRL_CPU2_PWR_ZONE_CNTRL_REG_ZONE_MAN_CLKEN_MASK 0x00000001
-#define BCHP_HIF_CPUBIUCTRL_CPU2_PWR_ZONE_CNTRL_REG_ZONE_MAN_CLKEN_SHIFT 0
-#define BCHP_HIF_CPUBIUCTRL_CPU2_PWR_ZONE_CNTRL_REG_ZONE_MAN_CLKEN_DEFAULT 0x00000000
-
-/***************************************************************************
- *CPU3_PWR_ZONE_CNTRL_REG - CPU3 Power Zone Control Register
- ***************************************************************************/
-/* HIF_CPUBIUCTRL :: CPU3_PWR_ZONE_CNTRL_REG :: ZONE_RESET_STATE [31:31] */
-#define BCHP_HIF_CPUBIUCTRL_CPU3_PWR_ZONE_CNTRL_REG_ZONE_RESET_STATE_MASK 0x80000000
-#define BCHP_HIF_CPUBIUCTRL_CPU3_PWR_ZONE_CNTRL_REG_ZONE_RESET_STATE_SHIFT 31
-
-/* HIF_CPUBIUCTRL :: CPU3_PWR_ZONE_CNTRL_REG :: ZONE_ISO_STATE [30:30] */
-#define BCHP_HIF_CPUBIUCTRL_CPU3_PWR_ZONE_CNTRL_REG_ZONE_ISO_STATE_MASK 0x40000000
-#define BCHP_HIF_CPUBIUCTRL_CPU3_PWR_ZONE_CNTRL_REG_ZONE_ISO_STATE_SHIFT 30
-
-/* HIF_CPUBIUCTRL :: CPU3_PWR_ZONE_CNTRL_REG :: ZONE_MEM_PWR_STATE [29:29] */
-#define BCHP_HIF_CPUBIUCTRL_CPU3_PWR_ZONE_CNTRL_REG_ZONE_MEM_PWR_STATE_MASK 0x20000000
-#define BCHP_HIF_CPUBIUCTRL_CPU3_PWR_ZONE_CNTRL_REG_ZONE_MEM_PWR_STATE_SHIFT 29
-
-/* HIF_CPUBIUCTRL :: CPU3_PWR_ZONE_CNTRL_REG :: ZONE_DPG_PWR_STATE [28:28] */
-#define BCHP_HIF_CPUBIUCTRL_CPU3_PWR_ZONE_CNTRL_REG_ZONE_DPG_PWR_STATE_MASK 0x10000000
-#define BCHP_HIF_CPUBIUCTRL_CPU3_PWR_ZONE_CNTRL_REG_ZONE_DPG_PWR_STATE_SHIFT 28
-
-/* HIF_CPUBIUCTRL :: CPU3_PWR_ZONE_CNTRL_REG :: ZONE_POWER_GOOD [27:27] */
-#define BCHP_HIF_CPUBIUCTRL_CPU3_PWR_ZONE_CNTRL_REG_ZONE_POWER_GOOD_MASK 0x08000000
-#define BCHP_HIF_CPUBIUCTRL_CPU3_PWR_ZONE_CNTRL_REG_ZONE_POWER_GOOD_SHIFT 27
-
-/* HIF_CPUBIUCTRL :: CPU3_PWR_ZONE_CNTRL_REG :: ZONE_PWR_ON_STATE [26:26] */
-#define BCHP_HIF_CPUBIUCTRL_CPU3_PWR_ZONE_CNTRL_REG_ZONE_PWR_ON_STATE_MASK 0x04000000
-#define BCHP_HIF_CPUBIUCTRL_CPU3_PWR_ZONE_CNTRL_REG_ZONE_PWR_ON_STATE_SHIFT 26
-
-/* HIF_CPUBIUCTRL :: CPU3_PWR_ZONE_CNTRL_REG :: ZONE_PWR_OFF_STATE [25:25] */
-#define BCHP_HIF_CPUBIUCTRL_CPU3_PWR_ZONE_CNTRL_REG_ZONE_PWR_OFF_STATE_MASK 0x02000000
-#define BCHP_HIF_CPUBIUCTRL_CPU3_PWR_ZONE_CNTRL_REG_ZONE_PWR_OFF_STATE_SHIFT 25
-
-/* HIF_CPUBIUCTRL :: CPU3_PWR_ZONE_CNTRL_REG :: FREQ_SCALAR_DYNAMIC_SEL [24:24] */
-#define BCHP_HIF_CPUBIUCTRL_CPU3_PWR_ZONE_CNTRL_REG_FREQ_SCALAR_DYNAMIC_SEL_MASK 0x01000000
-#define BCHP_HIF_CPUBIUCTRL_CPU3_PWR_ZONE_CNTRL_REG_FREQ_SCALAR_DYNAMIC_SEL_SHIFT 24
-
-/* HIF_CPUBIUCTRL :: CPU3_PWR_ZONE_CNTRL_REG :: ZONE_PWR_CNTL_STATE [23:19] */
-#define BCHP_HIF_CPUBIUCTRL_CPU3_PWR_ZONE_CNTRL_REG_ZONE_PWR_CNTL_STATE_MASK 0x00f80000
-#define BCHP_HIF_CPUBIUCTRL_CPU3_PWR_ZONE_CNTRL_REG_ZONE_PWR_CNTL_STATE_SHIFT 19
-
-/* HIF_CPUBIUCTRL :: CPU3_PWR_ZONE_CNTRL_REG :: reserved0 [18:14] */
-#define BCHP_HIF_CPUBIUCTRL_CPU3_PWR_ZONE_CNTRL_REG_reserved0_MASK 0x0007c000
-#define BCHP_HIF_CPUBIUCTRL_CPU3_PWR_ZONE_CNTRL_REG_reserved0_SHIFT 14
-
-/* HIF_CPUBIUCTRL :: CPU3_PWR_ZONE_CNTRL_REG :: ZONE_MEM_STBY [13:13] */
-#define BCHP_HIF_CPUBIUCTRL_CPU3_PWR_ZONE_CNTRL_REG_ZONE_MEM_STBY_MASK 0x00002000
-#define BCHP_HIF_CPUBIUCTRL_CPU3_PWR_ZONE_CNTRL_REG_ZONE_MEM_STBY_SHIFT 13
-
-/* HIF_CPUBIUCTRL :: CPU3_PWR_ZONE_CNTRL_REG :: ZONE_BLK_RST_ASSERT [12:12] */
-#define BCHP_HIF_CPUBIUCTRL_CPU3_PWR_ZONE_CNTRL_REG_ZONE_BLK_RST_ASSERT_MASK 0x00001000
-#define BCHP_HIF_CPUBIUCTRL_CPU3_PWR_ZONE_CNTRL_REG_ZONE_BLK_RST_ASSERT_SHIFT 12
-#define BCHP_HIF_CPUBIUCTRL_CPU3_PWR_ZONE_CNTRL_REG_ZONE_BLK_RST_ASSERT_DEFAULT 0x00000001
-
-/* HIF_CPUBIUCTRL :: CPU3_PWR_ZONE_CNTRL_REG :: ZONE_MEM_PWR_CNTL_EN [11:11] */
-#define BCHP_HIF_CPUBIUCTRL_CPU3_PWR_ZONE_CNTRL_REG_ZONE_MEM_PWR_CNTL_EN_MASK 0x00000800
-#define BCHP_HIF_CPUBIUCTRL_CPU3_PWR_ZONE_CNTRL_REG_ZONE_MEM_PWR_CNTL_EN_SHIFT 11
-#define BCHP_HIF_CPUBIUCTRL_CPU3_PWR_ZONE_CNTRL_REG_ZONE_MEM_PWR_CNTL_EN_DEFAULT 0x00000001
-
-/* HIF_CPUBIUCTRL :: CPU3_PWR_ZONE_CNTRL_REG :: ZONE_PWR_UP_REQ [10:10] */
-#define BCHP_HIF_CPUBIUCTRL_CPU3_PWR_ZONE_CNTRL_REG_ZONE_PWR_UP_REQ_MASK 0x00000400
-#define BCHP_HIF_CPUBIUCTRL_CPU3_PWR_ZONE_CNTRL_REG_ZONE_PWR_UP_REQ_SHIFT 10
-#define BCHP_HIF_CPUBIUCTRL_CPU3_PWR_ZONE_CNTRL_REG_ZONE_PWR_UP_REQ_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: CPU3_PWR_ZONE_CNTRL_REG :: ZONE_PWR_DN_REQ [09:09] */
-#define BCHP_HIF_CPUBIUCTRL_CPU3_PWR_ZONE_CNTRL_REG_ZONE_PWR_DN_REQ_MASK 0x00000200
-#define BCHP_HIF_CPUBIUCTRL_CPU3_PWR_ZONE_CNTRL_REG_ZONE_PWR_DN_REQ_SHIFT 9
-#define BCHP_HIF_CPUBIUCTRL_CPU3_PWR_ZONE_CNTRL_REG_ZONE_PWR_DN_REQ_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: CPU3_PWR_ZONE_CNTRL_REG :: ZONE_DPG_CNTL_EN [08:08] */
-#define BCHP_HIF_CPUBIUCTRL_CPU3_PWR_ZONE_CNTRL_REG_ZONE_DPG_CNTL_EN_MASK 0x00000100
-#define BCHP_HIF_CPUBIUCTRL_CPU3_PWR_ZONE_CNTRL_REG_ZONE_DPG_CNTL_EN_SHIFT 8
-#define BCHP_HIF_CPUBIUCTRL_CPU3_PWR_ZONE_CNTRL_REG_ZONE_DPG_CNTL_EN_DEFAULT 0x00000001
-
-/* HIF_CPUBIUCTRL :: CPU3_PWR_ZONE_CNTRL_REG :: ZONE_MANUAL_CONTROL [07:07] */
-#define BCHP_HIF_CPUBIUCTRL_CPU3_PWR_ZONE_CNTRL_REG_ZONE_MANUAL_CONTROL_MASK 0x00000080
-#define BCHP_HIF_CPUBIUCTRL_CPU3_PWR_ZONE_CNTRL_REG_ZONE_MANUAL_CONTROL_SHIFT 7
-#define BCHP_HIF_CPUBIUCTRL_CPU3_PWR_ZONE_CNTRL_REG_ZONE_MANUAL_CONTROL_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: CPU3_PWR_ZONE_CNTRL_REG :: ZONE_MAN_ISO_CNTL [06:06] */
-#define BCHP_HIF_CPUBIUCTRL_CPU3_PWR_ZONE_CNTRL_REG_ZONE_MAN_ISO_CNTL_MASK 0x00000040
-#define BCHP_HIF_CPUBIUCTRL_CPU3_PWR_ZONE_CNTRL_REG_ZONE_MAN_ISO_CNTL_SHIFT 6
-#define BCHP_HIF_CPUBIUCTRL_CPU3_PWR_ZONE_CNTRL_REG_ZONE_MAN_ISO_CNTL_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: CPU3_PWR_ZONE_CNTRL_REG :: reserved1 [05:05] */
-#define BCHP_HIF_CPUBIUCTRL_CPU3_PWR_ZONE_CNTRL_REG_reserved1_MASK 0x00000020
-#define BCHP_HIF_CPUBIUCTRL_CPU3_PWR_ZONE_CNTRL_REG_reserved1_SHIFT 5
-
-/* HIF_CPUBIUCTRL :: CPU3_PWR_ZONE_CNTRL_REG :: ZONE_MAN_MEM_PWR [04:04] */
-#define BCHP_HIF_CPUBIUCTRL_CPU3_PWR_ZONE_CNTRL_REG_ZONE_MAN_MEM_PWR_MASK 0x00000010
-#define BCHP_HIF_CPUBIUCTRL_CPU3_PWR_ZONE_CNTRL_REG_ZONE_MAN_MEM_PWR_SHIFT 4
-#define BCHP_HIF_CPUBIUCTRL_CPU3_PWR_ZONE_CNTRL_REG_ZONE_MAN_MEM_PWR_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: CPU3_PWR_ZONE_CNTRL_REG :: ZONE_DPG_CAPABLE [03:03] */
-#define BCHP_HIF_CPUBIUCTRL_CPU3_PWR_ZONE_CNTRL_REG_ZONE_DPG_CAPABLE_MASK 0x00000008
-#define BCHP_HIF_CPUBIUCTRL_CPU3_PWR_ZONE_CNTRL_REG_ZONE_DPG_CAPABLE_SHIFT 3
-
-/* HIF_CPUBIUCTRL :: CPU3_PWR_ZONE_CNTRL_REG :: ZONE_FREQ_SCALE_USED [02:02] */
-#define BCHP_HIF_CPUBIUCTRL_CPU3_PWR_ZONE_CNTRL_REG_ZONE_FREQ_SCALE_USED_MASK 0x00000004
-#define BCHP_HIF_CPUBIUCTRL_CPU3_PWR_ZONE_CNTRL_REG_ZONE_FREQ_SCALE_USED_SHIFT 2
-
-/* HIF_CPUBIUCTRL :: CPU3_PWR_ZONE_CNTRL_REG :: ZONE_MAN_RESET_CNTL [01:01] */
-#define BCHP_HIF_CPUBIUCTRL_CPU3_PWR_ZONE_CNTRL_REG_ZONE_MAN_RESET_CNTL_MASK 0x00000002
-#define BCHP_HIF_CPUBIUCTRL_CPU3_PWR_ZONE_CNTRL_REG_ZONE_MAN_RESET_CNTL_SHIFT 1
-#define BCHP_HIF_CPUBIUCTRL_CPU3_PWR_ZONE_CNTRL_REG_ZONE_MAN_RESET_CNTL_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: CPU3_PWR_ZONE_CNTRL_REG :: ZONE_MAN_CLKEN [00:00] */
-#define BCHP_HIF_CPUBIUCTRL_CPU3_PWR_ZONE_CNTRL_REG_ZONE_MAN_CLKEN_MASK 0x00000001
-#define BCHP_HIF_CPUBIUCTRL_CPU3_PWR_ZONE_CNTRL_REG_ZONE_MAN_CLKEN_SHIFT 0
-#define BCHP_HIF_CPUBIUCTRL_CPU3_PWR_ZONE_CNTRL_REG_ZONE_MAN_CLKEN_DEFAULT 0x00000000
-
-/***************************************************************************
- *L2BIU_PWR_ZONE_CNTRL_REG - L2 and BIU Power Zone Control Register
- ***************************************************************************/
-/* HIF_CPUBIUCTRL :: L2BIU_PWR_ZONE_CNTRL_REG :: ZONE_RESET_STATE [31:31] */
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_PWR_ZONE_CNTRL_REG_ZONE_RESET_STATE_MASK 0x80000000
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_PWR_ZONE_CNTRL_REG_ZONE_RESET_STATE_SHIFT 31
-
-/* HIF_CPUBIUCTRL :: L2BIU_PWR_ZONE_CNTRL_REG :: ZONE_ISO_STATE [30:30] */
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_PWR_ZONE_CNTRL_REG_ZONE_ISO_STATE_MASK 0x40000000
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_PWR_ZONE_CNTRL_REG_ZONE_ISO_STATE_SHIFT 30
-
-/* HIF_CPUBIUCTRL :: L2BIU_PWR_ZONE_CNTRL_REG :: ZONE_MEM_PWR_STATE [29:29] */
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_PWR_ZONE_CNTRL_REG_ZONE_MEM_PWR_STATE_MASK 0x20000000
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_PWR_ZONE_CNTRL_REG_ZONE_MEM_PWR_STATE_SHIFT 29
-
-/* HIF_CPUBIUCTRL :: L2BIU_PWR_ZONE_CNTRL_REG :: ZONE_DPG_PWR_STATE [28:28] */
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_PWR_ZONE_CNTRL_REG_ZONE_DPG_PWR_STATE_MASK 0x10000000
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_PWR_ZONE_CNTRL_REG_ZONE_DPG_PWR_STATE_SHIFT 28
-
-/* HIF_CPUBIUCTRL :: L2BIU_PWR_ZONE_CNTRL_REG :: ZONE_POWER_GOOD [27:27] */
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_PWR_ZONE_CNTRL_REG_ZONE_POWER_GOOD_MASK 0x08000000
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_PWR_ZONE_CNTRL_REG_ZONE_POWER_GOOD_SHIFT 27
-
-/* HIF_CPUBIUCTRL :: L2BIU_PWR_ZONE_CNTRL_REG :: ZONE_PWR_ON_STATE [26:26] */
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_PWR_ZONE_CNTRL_REG_ZONE_PWR_ON_STATE_MASK 0x04000000
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_PWR_ZONE_CNTRL_REG_ZONE_PWR_ON_STATE_SHIFT 26
-
-/* HIF_CPUBIUCTRL :: L2BIU_PWR_ZONE_CNTRL_REG :: ZONE_PWR_OFF_STATE [25:25] */
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_PWR_ZONE_CNTRL_REG_ZONE_PWR_OFF_STATE_MASK 0x02000000
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_PWR_ZONE_CNTRL_REG_ZONE_PWR_OFF_STATE_SHIFT 25
-
-/* HIF_CPUBIUCTRL :: L2BIU_PWR_ZONE_CNTRL_REG :: FREQ_SCALAR_DYNAMIC_SEL [24:24] */
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_PWR_ZONE_CNTRL_REG_FREQ_SCALAR_DYNAMIC_SEL_MASK 0x01000000
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_PWR_ZONE_CNTRL_REG_FREQ_SCALAR_DYNAMIC_SEL_SHIFT 24
-
-/* HIF_CPUBIUCTRL :: L2BIU_PWR_ZONE_CNTRL_REG :: ZONE_PWR_CNTL_STATE [23:19] */
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_PWR_ZONE_CNTRL_REG_ZONE_PWR_CNTL_STATE_MASK 0x00f80000
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_PWR_ZONE_CNTRL_REG_ZONE_PWR_CNTL_STATE_SHIFT 19
-
-/* HIF_CPUBIUCTRL :: L2BIU_PWR_ZONE_CNTRL_REG :: reserved0 [18:14] */
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_PWR_ZONE_CNTRL_REG_reserved0_MASK 0x0007c000
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_PWR_ZONE_CNTRL_REG_reserved0_SHIFT 14
-
-/* HIF_CPUBIUCTRL :: L2BIU_PWR_ZONE_CNTRL_REG :: ZONE_MEM_STBY [13:13] */
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_PWR_ZONE_CNTRL_REG_ZONE_MEM_STBY_MASK 0x00002000
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_PWR_ZONE_CNTRL_REG_ZONE_MEM_STBY_SHIFT 13
-
-/* HIF_CPUBIUCTRL :: L2BIU_PWR_ZONE_CNTRL_REG :: ZONE_BLK_RST_ASSERT [12:12] */
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_PWR_ZONE_CNTRL_REG_ZONE_BLK_RST_ASSERT_MASK 0x00001000
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_PWR_ZONE_CNTRL_REG_ZONE_BLK_RST_ASSERT_SHIFT 12
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_PWR_ZONE_CNTRL_REG_ZONE_BLK_RST_ASSERT_DEFAULT 0x00000001
-
-/* HIF_CPUBIUCTRL :: L2BIU_PWR_ZONE_CNTRL_REG :: ZONE_MEM_PWR_CNTL_EN [11:11] */
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_PWR_ZONE_CNTRL_REG_ZONE_MEM_PWR_CNTL_EN_MASK 0x00000800
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_PWR_ZONE_CNTRL_REG_ZONE_MEM_PWR_CNTL_EN_SHIFT 11
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_PWR_ZONE_CNTRL_REG_ZONE_MEM_PWR_CNTL_EN_DEFAULT 0x00000001
-
-/* HIF_CPUBIUCTRL :: L2BIU_PWR_ZONE_CNTRL_REG :: ZONE_PWR_UP_REQ [10:10] */
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_PWR_ZONE_CNTRL_REG_ZONE_PWR_UP_REQ_MASK 0x00000400
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_PWR_ZONE_CNTRL_REG_ZONE_PWR_UP_REQ_SHIFT 10
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_PWR_ZONE_CNTRL_REG_ZONE_PWR_UP_REQ_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: L2BIU_PWR_ZONE_CNTRL_REG :: ZONE_PWR_DN_REQ [09:09] */
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_PWR_ZONE_CNTRL_REG_ZONE_PWR_DN_REQ_MASK 0x00000200
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_PWR_ZONE_CNTRL_REG_ZONE_PWR_DN_REQ_SHIFT 9
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_PWR_ZONE_CNTRL_REG_ZONE_PWR_DN_REQ_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: L2BIU_PWR_ZONE_CNTRL_REG :: ZONE_DPG_CNTL_EN [08:08] */
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_PWR_ZONE_CNTRL_REG_ZONE_DPG_CNTL_EN_MASK 0x00000100
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_PWR_ZONE_CNTRL_REG_ZONE_DPG_CNTL_EN_SHIFT 8
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_PWR_ZONE_CNTRL_REG_ZONE_DPG_CNTL_EN_DEFAULT 0x00000001
-
-/* HIF_CPUBIUCTRL :: L2BIU_PWR_ZONE_CNTRL_REG :: ZONE_MANUAL_CONTROL [07:07] */
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_PWR_ZONE_CNTRL_REG_ZONE_MANUAL_CONTROL_MASK 0x00000080
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_PWR_ZONE_CNTRL_REG_ZONE_MANUAL_CONTROL_SHIFT 7
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_PWR_ZONE_CNTRL_REG_ZONE_MANUAL_CONTROL_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: L2BIU_PWR_ZONE_CNTRL_REG :: ZONE_MAN_ISO_CNTL [06:06] */
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_PWR_ZONE_CNTRL_REG_ZONE_MAN_ISO_CNTL_MASK 0x00000040
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_PWR_ZONE_CNTRL_REG_ZONE_MAN_ISO_CNTL_SHIFT 6
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_PWR_ZONE_CNTRL_REG_ZONE_MAN_ISO_CNTL_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: L2BIU_PWR_ZONE_CNTRL_REG :: reserved1 [05:05] */
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_PWR_ZONE_CNTRL_REG_reserved1_MASK 0x00000020
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_PWR_ZONE_CNTRL_REG_reserved1_SHIFT 5
-
-/* HIF_CPUBIUCTRL :: L2BIU_PWR_ZONE_CNTRL_REG :: ZONE_MAN_MEM_PWR [04:04] */
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_PWR_ZONE_CNTRL_REG_ZONE_MAN_MEM_PWR_MASK 0x00000010
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_PWR_ZONE_CNTRL_REG_ZONE_MAN_MEM_PWR_SHIFT 4
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_PWR_ZONE_CNTRL_REG_ZONE_MAN_MEM_PWR_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: L2BIU_PWR_ZONE_CNTRL_REG :: ZONE_DPG_CAPABLE [03:03] */
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_PWR_ZONE_CNTRL_REG_ZONE_DPG_CAPABLE_MASK 0x00000008
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_PWR_ZONE_CNTRL_REG_ZONE_DPG_CAPABLE_SHIFT 3
-
-/* HIF_CPUBIUCTRL :: L2BIU_PWR_ZONE_CNTRL_REG :: ZONE_FREQ_SCALE_USED [02:02] */
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_PWR_ZONE_CNTRL_REG_ZONE_FREQ_SCALE_USED_MASK 0x00000004
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_PWR_ZONE_CNTRL_REG_ZONE_FREQ_SCALE_USED_SHIFT 2
-
-/* HIF_CPUBIUCTRL :: L2BIU_PWR_ZONE_CNTRL_REG :: ZONE_MAN_RESET_CNTL [01:01] */
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_PWR_ZONE_CNTRL_REG_ZONE_MAN_RESET_CNTL_MASK 0x00000002
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_PWR_ZONE_CNTRL_REG_ZONE_MAN_RESET_CNTL_SHIFT 1
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_PWR_ZONE_CNTRL_REG_ZONE_MAN_RESET_CNTL_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: L2BIU_PWR_ZONE_CNTRL_REG :: ZONE_MAN_CLKEN [00:00] */
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_PWR_ZONE_CNTRL_REG_ZONE_MAN_CLKEN_MASK 0x00000001
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_PWR_ZONE_CNTRL_REG_ZONE_MAN_CLKEN_SHIFT 0
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_PWR_ZONE_CNTRL_REG_ZONE_MAN_CLKEN_DEFAULT 0x00000000
-
-/***************************************************************************
- *CPU0_PWR_ZONE_CONFIG1_REG - CPU0 Power Zone Config1 Registers
- ***************************************************************************/
-/* HIF_CPUBIUCTRL :: CPU0_PWR_ZONE_CONFIG1_REG :: RST_OFF_DLY [31:28] */
-#define BCHP_HIF_CPUBIUCTRL_CPU0_PWR_ZONE_CONFIG1_REG_RST_OFF_DLY_MASK 0xf0000000
-#define BCHP_HIF_CPUBIUCTRL_CPU0_PWR_ZONE_CONFIG1_REG_RST_OFF_DLY_SHIFT 28
-#define BCHP_HIF_CPUBIUCTRL_CPU0_PWR_ZONE_CONFIG1_REG_RST_OFF_DLY_DEFAULT 0x00000004
-
-/* HIF_CPUBIUCTRL :: CPU0_PWR_ZONE_CONFIG1_REG :: RST_ON_DLY [27:24] */
-#define BCHP_HIF_CPUBIUCTRL_CPU0_PWR_ZONE_CONFIG1_REG_RST_ON_DLY_MASK 0x0f000000
-#define BCHP_HIF_CPUBIUCTRL_CPU0_PWR_ZONE_CONFIG1_REG_RST_ON_DLY_SHIFT 24
-#define BCHP_HIF_CPUBIUCTRL_CPU0_PWR_ZONE_CONFIG1_REG_RST_ON_DLY_DEFAULT 0x00000004
-
-/* HIF_CPUBIUCTRL :: CPU0_PWR_ZONE_CONFIG1_REG :: CLK_OFF_DLY [23:20] */
-#define BCHP_HIF_CPUBIUCTRL_CPU0_PWR_ZONE_CONFIG1_REG_CLK_OFF_DLY_MASK 0x00f00000
-#define BCHP_HIF_CPUBIUCTRL_CPU0_PWR_ZONE_CONFIG1_REG_CLK_OFF_DLY_SHIFT 20
-#define BCHP_HIF_CPUBIUCTRL_CPU0_PWR_ZONE_CONFIG1_REG_CLK_OFF_DLY_DEFAULT 0x00000004
-
-/* HIF_CPUBIUCTRL :: CPU0_PWR_ZONE_CONFIG1_REG :: CLK_ON_DLY [19:16] */
-#define BCHP_HIF_CPUBIUCTRL_CPU0_PWR_ZONE_CONFIG1_REG_CLK_ON_DLY_MASK 0x000f0000
-#define BCHP_HIF_CPUBIUCTRL_CPU0_PWR_ZONE_CONFIG1_REG_CLK_ON_DLY_SHIFT 16
-#define BCHP_HIF_CPUBIUCTRL_CPU0_PWR_ZONE_CONFIG1_REG_CLK_ON_DLY_DEFAULT 0x00000004
-
-/* HIF_CPUBIUCTRL :: CPU0_PWR_ZONE_CONFIG1_REG :: ISO_OFF_DLY [15:12] */
-#define BCHP_HIF_CPUBIUCTRL_CPU0_PWR_ZONE_CONFIG1_REG_ISO_OFF_DLY_MASK 0x0000f000
-#define BCHP_HIF_CPUBIUCTRL_CPU0_PWR_ZONE_CONFIG1_REG_ISO_OFF_DLY_SHIFT 12
-#define BCHP_HIF_CPUBIUCTRL_CPU0_PWR_ZONE_CONFIG1_REG_ISO_OFF_DLY_DEFAULT 0x00000004
-
-/* HIF_CPUBIUCTRL :: CPU0_PWR_ZONE_CONFIG1_REG :: ISO_ON_DLY [11:08] */
-#define BCHP_HIF_CPUBIUCTRL_CPU0_PWR_ZONE_CONFIG1_REG_ISO_ON_DLY_MASK 0x00000f00
-#define BCHP_HIF_CPUBIUCTRL_CPU0_PWR_ZONE_CONFIG1_REG_ISO_ON_DLY_SHIFT 8
-#define BCHP_HIF_CPUBIUCTRL_CPU0_PWR_ZONE_CONFIG1_REG_ISO_ON_DLY_DEFAULT 0x00000004
-
-/* HIF_CPUBIUCTRL :: CPU0_PWR_ZONE_CONFIG1_REG :: reserved0 [07:05] */
-#define BCHP_HIF_CPUBIUCTRL_CPU0_PWR_ZONE_CONFIG1_REG_reserved0_MASK 0x000000e0
-#define BCHP_HIF_CPUBIUCTRL_CPU0_PWR_ZONE_CONFIG1_REG_reserved0_SHIFT 5
-
-/* HIF_CPUBIUCTRL :: CPU0_PWR_ZONE_CONFIG1_REG :: PWROK_TRESH [04:03] */
-#define BCHP_HIF_CPUBIUCTRL_CPU0_PWR_ZONE_CONFIG1_REG_PWROK_TRESH_MASK 0x00000018
-#define BCHP_HIF_CPUBIUCTRL_CPU0_PWR_ZONE_CONFIG1_REG_PWROK_TRESH_SHIFT 3
-#define BCHP_HIF_CPUBIUCTRL_CPU0_PWR_ZONE_CONFIG1_REG_PWROK_TRESH_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: CPU0_PWR_ZONE_CONFIG1_REG :: PWROK_DELAY_SEL [02:00] */
-#define BCHP_HIF_CPUBIUCTRL_CPU0_PWR_ZONE_CONFIG1_REG_PWROK_DELAY_SEL_MASK 0x00000007
-#define BCHP_HIF_CPUBIUCTRL_CPU0_PWR_ZONE_CONFIG1_REG_PWROK_DELAY_SEL_SHIFT 0
-#define BCHP_HIF_CPUBIUCTRL_CPU0_PWR_ZONE_CONFIG1_REG_PWROK_DELAY_SEL_DEFAULT 0x00000000
-
-/***************************************************************************
- *CPU0_PWR_ZONE_CONFIG2_REG - CPU0 Power Zone Config2 Registers
- ***************************************************************************/
-/* HIF_CPUBIUCTRL :: CPU0_PWR_ZONE_CONFIG2_REG :: MEM_OFF_DLY [31:28] */
-#define BCHP_HIF_CPUBIUCTRL_CPU0_PWR_ZONE_CONFIG2_REG_MEM_OFF_DLY_MASK 0xf0000000
-#define BCHP_HIF_CPUBIUCTRL_CPU0_PWR_ZONE_CONFIG2_REG_MEM_OFF_DLY_SHIFT 28
-#define BCHP_HIF_CPUBIUCTRL_CPU0_PWR_ZONE_CONFIG2_REG_MEM_OFF_DLY_DEFAULT 0x00000004
-
-/* HIF_CPUBIUCTRL :: CPU0_PWR_ZONE_CONFIG2_REG :: MEM_ON_DLY [27:24] */
-#define BCHP_HIF_CPUBIUCTRL_CPU0_PWR_ZONE_CONFIG2_REG_MEM_ON_DLY_MASK 0x0f000000
-#define BCHP_HIF_CPUBIUCTRL_CPU0_PWR_ZONE_CONFIG2_REG_MEM_ON_DLY_SHIFT 24
-#define BCHP_HIF_CPUBIUCTRL_CPU0_PWR_ZONE_CONFIG2_REG_MEM_ON_DLY_DEFAULT 0x00000004
-
-/* HIF_CPUBIUCTRL :: CPU0_PWR_ZONE_CONFIG2_REG :: DPG_OFF_DLY [23:20] */
-#define BCHP_HIF_CPUBIUCTRL_CPU0_PWR_ZONE_CONFIG2_REG_DPG_OFF_DLY_MASK 0x00f00000
-#define BCHP_HIF_CPUBIUCTRL_CPU0_PWR_ZONE_CONFIG2_REG_DPG_OFF_DLY_SHIFT 20
-#define BCHP_HIF_CPUBIUCTRL_CPU0_PWR_ZONE_CONFIG2_REG_DPG_OFF_DLY_DEFAULT 0x00000004
-
-/* HIF_CPUBIUCTRL :: CPU0_PWR_ZONE_CONFIG2_REG :: DPG1_ON_DLY [19:16] */
-#define BCHP_HIF_CPUBIUCTRL_CPU0_PWR_ZONE_CONFIG2_REG_DPG1_ON_DLY_MASK 0x000f0000
-#define BCHP_HIF_CPUBIUCTRL_CPU0_PWR_ZONE_CONFIG2_REG_DPG1_ON_DLY_SHIFT 16
-#define BCHP_HIF_CPUBIUCTRL_CPU0_PWR_ZONE_CONFIG2_REG_DPG1_ON_DLY_DEFAULT 0x00000003
-
-/* HIF_CPUBIUCTRL :: CPU0_PWR_ZONE_CONFIG2_REG :: DPGN_ON_DLY [15:12] */
-#define BCHP_HIF_CPUBIUCTRL_CPU0_PWR_ZONE_CONFIG2_REG_DPGN_ON_DLY_MASK 0x0000f000
-#define BCHP_HIF_CPUBIUCTRL_CPU0_PWR_ZONE_CONFIG2_REG_DPGN_ON_DLY_SHIFT 12
-#define BCHP_HIF_CPUBIUCTRL_CPU0_PWR_ZONE_CONFIG2_REG_DPGN_ON_DLY_DEFAULT 0x00000001
-
-/* HIF_CPUBIUCTRL :: CPU0_PWR_ZONE_CONFIG2_REG :: reserved0 [11:06] */
-#define BCHP_HIF_CPUBIUCTRL_CPU0_PWR_ZONE_CONFIG2_REG_reserved0_MASK 0x00000fc0
-#define BCHP_HIF_CPUBIUCTRL_CPU0_PWR_ZONE_CONFIG2_REG_reserved0_SHIFT 6
-
-/* HIF_CPUBIUCTRL :: CPU0_PWR_ZONE_CONFIG2_REG :: SLEW_PRESCALE_SEL [05:03] */
-#define BCHP_HIF_CPUBIUCTRL_CPU0_PWR_ZONE_CONFIG2_REG_SLEW_PRESCALE_SEL_MASK 0x00000038
-#define BCHP_HIF_CPUBIUCTRL_CPU0_PWR_ZONE_CONFIG2_REG_SLEW_PRESCALE_SEL_SHIFT 3
-#define BCHP_HIF_CPUBIUCTRL_CPU0_PWR_ZONE_CONFIG2_REG_SLEW_PRESCALE_SEL_DEFAULT 0x00000002
-
-/* HIF_CPUBIUCTRL :: CPU0_PWR_ZONE_CONFIG2_REG :: DELAY_PRESCALE_SEL [02:00] */
-#define BCHP_HIF_CPUBIUCTRL_CPU0_PWR_ZONE_CONFIG2_REG_DELAY_PRESCALE_SEL_MASK 0x00000007
-#define BCHP_HIF_CPUBIUCTRL_CPU0_PWR_ZONE_CONFIG2_REG_DELAY_PRESCALE_SEL_SHIFT 0
-#define BCHP_HIF_CPUBIUCTRL_CPU0_PWR_ZONE_CONFIG2_REG_DELAY_PRESCALE_SEL_DEFAULT 0x00000002
-
-/***************************************************************************
- *CPU1_PWR_ZONE_CONFIG1_REG - CPU1 Power Zone Config1 Registers
- ***************************************************************************/
-/* HIF_CPUBIUCTRL :: CPU1_PWR_ZONE_CONFIG1_REG :: RST_OFF_DLY [31:28] */
-#define BCHP_HIF_CPUBIUCTRL_CPU1_PWR_ZONE_CONFIG1_REG_RST_OFF_DLY_MASK 0xf0000000
-#define BCHP_HIF_CPUBIUCTRL_CPU1_PWR_ZONE_CONFIG1_REG_RST_OFF_DLY_SHIFT 28
-#define BCHP_HIF_CPUBIUCTRL_CPU1_PWR_ZONE_CONFIG1_REG_RST_OFF_DLY_DEFAULT 0x00000004
-
-/* HIF_CPUBIUCTRL :: CPU1_PWR_ZONE_CONFIG1_REG :: RST_ON_DLY [27:24] */
-#define BCHP_HIF_CPUBIUCTRL_CPU1_PWR_ZONE_CONFIG1_REG_RST_ON_DLY_MASK 0x0f000000
-#define BCHP_HIF_CPUBIUCTRL_CPU1_PWR_ZONE_CONFIG1_REG_RST_ON_DLY_SHIFT 24
-#define BCHP_HIF_CPUBIUCTRL_CPU1_PWR_ZONE_CONFIG1_REG_RST_ON_DLY_DEFAULT 0x00000004
-
-/* HIF_CPUBIUCTRL :: CPU1_PWR_ZONE_CONFIG1_REG :: CLK_OFF_DLY [23:20] */
-#define BCHP_HIF_CPUBIUCTRL_CPU1_PWR_ZONE_CONFIG1_REG_CLK_OFF_DLY_MASK 0x00f00000
-#define BCHP_HIF_CPUBIUCTRL_CPU1_PWR_ZONE_CONFIG1_REG_CLK_OFF_DLY_SHIFT 20
-#define BCHP_HIF_CPUBIUCTRL_CPU1_PWR_ZONE_CONFIG1_REG_CLK_OFF_DLY_DEFAULT 0x00000004
-
-/* HIF_CPUBIUCTRL :: CPU1_PWR_ZONE_CONFIG1_REG :: CLK_ON_DLY [19:16] */
-#define BCHP_HIF_CPUBIUCTRL_CPU1_PWR_ZONE_CONFIG1_REG_CLK_ON_DLY_MASK 0x000f0000
-#define BCHP_HIF_CPUBIUCTRL_CPU1_PWR_ZONE_CONFIG1_REG_CLK_ON_DLY_SHIFT 16
-#define BCHP_HIF_CPUBIUCTRL_CPU1_PWR_ZONE_CONFIG1_REG_CLK_ON_DLY_DEFAULT 0x00000004
-
-/* HIF_CPUBIUCTRL :: CPU1_PWR_ZONE_CONFIG1_REG :: ISO_OFF_DLY [15:12] */
-#define BCHP_HIF_CPUBIUCTRL_CPU1_PWR_ZONE_CONFIG1_REG_ISO_OFF_DLY_MASK 0x0000f000
-#define BCHP_HIF_CPUBIUCTRL_CPU1_PWR_ZONE_CONFIG1_REG_ISO_OFF_DLY_SHIFT 12
-#define BCHP_HIF_CPUBIUCTRL_CPU1_PWR_ZONE_CONFIG1_REG_ISO_OFF_DLY_DEFAULT 0x00000004
-
-/* HIF_CPUBIUCTRL :: CPU1_PWR_ZONE_CONFIG1_REG :: ISO_ON_DLY [11:08] */
-#define BCHP_HIF_CPUBIUCTRL_CPU1_PWR_ZONE_CONFIG1_REG_ISO_ON_DLY_MASK 0x00000f00
-#define BCHP_HIF_CPUBIUCTRL_CPU1_PWR_ZONE_CONFIG1_REG_ISO_ON_DLY_SHIFT 8
-#define BCHP_HIF_CPUBIUCTRL_CPU1_PWR_ZONE_CONFIG1_REG_ISO_ON_DLY_DEFAULT 0x00000004
-
-/* HIF_CPUBIUCTRL :: CPU1_PWR_ZONE_CONFIG1_REG :: reserved0 [07:05] */
-#define BCHP_HIF_CPUBIUCTRL_CPU1_PWR_ZONE_CONFIG1_REG_reserved0_MASK 0x000000e0
-#define BCHP_HIF_CPUBIUCTRL_CPU1_PWR_ZONE_CONFIG1_REG_reserved0_SHIFT 5
-
-/* HIF_CPUBIUCTRL :: CPU1_PWR_ZONE_CONFIG1_REG :: PWROK_TRESH [04:03] */
-#define BCHP_HIF_CPUBIUCTRL_CPU1_PWR_ZONE_CONFIG1_REG_PWROK_TRESH_MASK 0x00000018
-#define BCHP_HIF_CPUBIUCTRL_CPU1_PWR_ZONE_CONFIG1_REG_PWROK_TRESH_SHIFT 3
-#define BCHP_HIF_CPUBIUCTRL_CPU1_PWR_ZONE_CONFIG1_REG_PWROK_TRESH_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: CPU1_PWR_ZONE_CONFIG1_REG :: PWROK_DELAY_SEL [02:00] */
-#define BCHP_HIF_CPUBIUCTRL_CPU1_PWR_ZONE_CONFIG1_REG_PWROK_DELAY_SEL_MASK 0x00000007
-#define BCHP_HIF_CPUBIUCTRL_CPU1_PWR_ZONE_CONFIG1_REG_PWROK_DELAY_SEL_SHIFT 0
-#define BCHP_HIF_CPUBIUCTRL_CPU1_PWR_ZONE_CONFIG1_REG_PWROK_DELAY_SEL_DEFAULT 0x00000000
-
-/***************************************************************************
- *CPU1_PWR_ZONE_CONFIG2_REG - CPU1 Power Zone Config2 Registers
- ***************************************************************************/
-/* HIF_CPUBIUCTRL :: CPU1_PWR_ZONE_CONFIG2_REG :: MEM_OFF_DLY [31:28] */
-#define BCHP_HIF_CPUBIUCTRL_CPU1_PWR_ZONE_CONFIG2_REG_MEM_OFF_DLY_MASK 0xf0000000
-#define BCHP_HIF_CPUBIUCTRL_CPU1_PWR_ZONE_CONFIG2_REG_MEM_OFF_DLY_SHIFT 28
-#define BCHP_HIF_CPUBIUCTRL_CPU1_PWR_ZONE_CONFIG2_REG_MEM_OFF_DLY_DEFAULT 0x00000004
-
-/* HIF_CPUBIUCTRL :: CPU1_PWR_ZONE_CONFIG2_REG :: MEM_ON_DLY [27:24] */
-#define BCHP_HIF_CPUBIUCTRL_CPU1_PWR_ZONE_CONFIG2_REG_MEM_ON_DLY_MASK 0x0f000000
-#define BCHP_HIF_CPUBIUCTRL_CPU1_PWR_ZONE_CONFIG2_REG_MEM_ON_DLY_SHIFT 24
-#define BCHP_HIF_CPUBIUCTRL_CPU1_PWR_ZONE_CONFIG2_REG_MEM_ON_DLY_DEFAULT 0x00000004
-
-/* HIF_CPUBIUCTRL :: CPU1_PWR_ZONE_CONFIG2_REG :: DPG_OFF_DLY [23:20] */
-#define BCHP_HIF_CPUBIUCTRL_CPU1_PWR_ZONE_CONFIG2_REG_DPG_OFF_DLY_MASK 0x00f00000
-#define BCHP_HIF_CPUBIUCTRL_CPU1_PWR_ZONE_CONFIG2_REG_DPG_OFF_DLY_SHIFT 20
-#define BCHP_HIF_CPUBIUCTRL_CPU1_PWR_ZONE_CONFIG2_REG_DPG_OFF_DLY_DEFAULT 0x00000004
-
-/* HIF_CPUBIUCTRL :: CPU1_PWR_ZONE_CONFIG2_REG :: DPG1_ON_DLY [19:16] */
-#define BCHP_HIF_CPUBIUCTRL_CPU1_PWR_ZONE_CONFIG2_REG_DPG1_ON_DLY_MASK 0x000f0000
-#define BCHP_HIF_CPUBIUCTRL_CPU1_PWR_ZONE_CONFIG2_REG_DPG1_ON_DLY_SHIFT 16
-#define BCHP_HIF_CPUBIUCTRL_CPU1_PWR_ZONE_CONFIG2_REG_DPG1_ON_DLY_DEFAULT 0x00000003
-
-/* HIF_CPUBIUCTRL :: CPU1_PWR_ZONE_CONFIG2_REG :: DPGN_ON_DLY [15:12] */
-#define BCHP_HIF_CPUBIUCTRL_CPU1_PWR_ZONE_CONFIG2_REG_DPGN_ON_DLY_MASK 0x0000f000
-#define BCHP_HIF_CPUBIUCTRL_CPU1_PWR_ZONE_CONFIG2_REG_DPGN_ON_DLY_SHIFT 12
-#define BCHP_HIF_CPUBIUCTRL_CPU1_PWR_ZONE_CONFIG2_REG_DPGN_ON_DLY_DEFAULT 0x00000001
-
-/* HIF_CPUBIUCTRL :: CPU1_PWR_ZONE_CONFIG2_REG :: reserved0 [11:06] */
-#define BCHP_HIF_CPUBIUCTRL_CPU1_PWR_ZONE_CONFIG2_REG_reserved0_MASK 0x00000fc0
-#define BCHP_HIF_CPUBIUCTRL_CPU1_PWR_ZONE_CONFIG2_REG_reserved0_SHIFT 6
-
-/* HIF_CPUBIUCTRL :: CPU1_PWR_ZONE_CONFIG2_REG :: SLEW_PRESCALE_SEL [05:03] */
-#define BCHP_HIF_CPUBIUCTRL_CPU1_PWR_ZONE_CONFIG2_REG_SLEW_PRESCALE_SEL_MASK 0x00000038
-#define BCHP_HIF_CPUBIUCTRL_CPU1_PWR_ZONE_CONFIG2_REG_SLEW_PRESCALE_SEL_SHIFT 3
-#define BCHP_HIF_CPUBIUCTRL_CPU1_PWR_ZONE_CONFIG2_REG_SLEW_PRESCALE_SEL_DEFAULT 0x00000002
-
-/* HIF_CPUBIUCTRL :: CPU1_PWR_ZONE_CONFIG2_REG :: DELAY_PRESCALE_SEL [02:00] */
-#define BCHP_HIF_CPUBIUCTRL_CPU1_PWR_ZONE_CONFIG2_REG_DELAY_PRESCALE_SEL_MASK 0x00000007
-#define BCHP_HIF_CPUBIUCTRL_CPU1_PWR_ZONE_CONFIG2_REG_DELAY_PRESCALE_SEL_SHIFT 0
-#define BCHP_HIF_CPUBIUCTRL_CPU1_PWR_ZONE_CONFIG2_REG_DELAY_PRESCALE_SEL_DEFAULT 0x00000002
-
-/***************************************************************************
- *CPU2_PWR_ZONE_CONFIG1_REG - CPU2 Power Zone Config1 Registers
- ***************************************************************************/
-/* HIF_CPUBIUCTRL :: CPU2_PWR_ZONE_CONFIG1_REG :: RST_OFF_DLY [31:28] */
-#define BCHP_HIF_CPUBIUCTRL_CPU2_PWR_ZONE_CONFIG1_REG_RST_OFF_DLY_MASK 0xf0000000
-#define BCHP_HIF_CPUBIUCTRL_CPU2_PWR_ZONE_CONFIG1_REG_RST_OFF_DLY_SHIFT 28
-#define BCHP_HIF_CPUBIUCTRL_CPU2_PWR_ZONE_CONFIG1_REG_RST_OFF_DLY_DEFAULT 0x00000004
-
-/* HIF_CPUBIUCTRL :: CPU2_PWR_ZONE_CONFIG1_REG :: RST_ON_DLY [27:24] */
-#define BCHP_HIF_CPUBIUCTRL_CPU2_PWR_ZONE_CONFIG1_REG_RST_ON_DLY_MASK 0x0f000000
-#define BCHP_HIF_CPUBIUCTRL_CPU2_PWR_ZONE_CONFIG1_REG_RST_ON_DLY_SHIFT 24
-#define BCHP_HIF_CPUBIUCTRL_CPU2_PWR_ZONE_CONFIG1_REG_RST_ON_DLY_DEFAULT 0x00000004
-
-/* HIF_CPUBIUCTRL :: CPU2_PWR_ZONE_CONFIG1_REG :: CLK_OFF_DLY [23:20] */
-#define BCHP_HIF_CPUBIUCTRL_CPU2_PWR_ZONE_CONFIG1_REG_CLK_OFF_DLY_MASK 0x00f00000
-#define BCHP_HIF_CPUBIUCTRL_CPU2_PWR_ZONE_CONFIG1_REG_CLK_OFF_DLY_SHIFT 20
-#define BCHP_HIF_CPUBIUCTRL_CPU2_PWR_ZONE_CONFIG1_REG_CLK_OFF_DLY_DEFAULT 0x00000004
-
-/* HIF_CPUBIUCTRL :: CPU2_PWR_ZONE_CONFIG1_REG :: CLK_ON_DLY [19:16] */
-#define BCHP_HIF_CPUBIUCTRL_CPU2_PWR_ZONE_CONFIG1_REG_CLK_ON_DLY_MASK 0x000f0000
-#define BCHP_HIF_CPUBIUCTRL_CPU2_PWR_ZONE_CONFIG1_REG_CLK_ON_DLY_SHIFT 16
-#define BCHP_HIF_CPUBIUCTRL_CPU2_PWR_ZONE_CONFIG1_REG_CLK_ON_DLY_DEFAULT 0x00000004
-
-/* HIF_CPUBIUCTRL :: CPU2_PWR_ZONE_CONFIG1_REG :: ISO_OFF_DLY [15:12] */
-#define BCHP_HIF_CPUBIUCTRL_CPU2_PWR_ZONE_CONFIG1_REG_ISO_OFF_DLY_MASK 0x0000f000
-#define BCHP_HIF_CPUBIUCTRL_CPU2_PWR_ZONE_CONFIG1_REG_ISO_OFF_DLY_SHIFT 12
-#define BCHP_HIF_CPUBIUCTRL_CPU2_PWR_ZONE_CONFIG1_REG_ISO_OFF_DLY_DEFAULT 0x00000004
-
-/* HIF_CPUBIUCTRL :: CPU2_PWR_ZONE_CONFIG1_REG :: ISO_ON_DLY [11:08] */
-#define BCHP_HIF_CPUBIUCTRL_CPU2_PWR_ZONE_CONFIG1_REG_ISO_ON_DLY_MASK 0x00000f00
-#define BCHP_HIF_CPUBIUCTRL_CPU2_PWR_ZONE_CONFIG1_REG_ISO_ON_DLY_SHIFT 8
-#define BCHP_HIF_CPUBIUCTRL_CPU2_PWR_ZONE_CONFIG1_REG_ISO_ON_DLY_DEFAULT 0x00000004
-
-/* HIF_CPUBIUCTRL :: CPU2_PWR_ZONE_CONFIG1_REG :: reserved0 [07:05] */
-#define BCHP_HIF_CPUBIUCTRL_CPU2_PWR_ZONE_CONFIG1_REG_reserved0_MASK 0x000000e0
-#define BCHP_HIF_CPUBIUCTRL_CPU2_PWR_ZONE_CONFIG1_REG_reserved0_SHIFT 5
-
-/* HIF_CPUBIUCTRL :: CPU2_PWR_ZONE_CONFIG1_REG :: PWROK_TRESH [04:03] */
-#define BCHP_HIF_CPUBIUCTRL_CPU2_PWR_ZONE_CONFIG1_REG_PWROK_TRESH_MASK 0x00000018
-#define BCHP_HIF_CPUBIUCTRL_CPU2_PWR_ZONE_CONFIG1_REG_PWROK_TRESH_SHIFT 3
-#define BCHP_HIF_CPUBIUCTRL_CPU2_PWR_ZONE_CONFIG1_REG_PWROK_TRESH_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: CPU2_PWR_ZONE_CONFIG1_REG :: PWROK_DELAY_SEL [02:00] */
-#define BCHP_HIF_CPUBIUCTRL_CPU2_PWR_ZONE_CONFIG1_REG_PWROK_DELAY_SEL_MASK 0x00000007
-#define BCHP_HIF_CPUBIUCTRL_CPU2_PWR_ZONE_CONFIG1_REG_PWROK_DELAY_SEL_SHIFT 0
-#define BCHP_HIF_CPUBIUCTRL_CPU2_PWR_ZONE_CONFIG1_REG_PWROK_DELAY_SEL_DEFAULT 0x00000000
-
-/***************************************************************************
- *CPU2_PWR_ZONE_CONFIG2_REG - CPU2 Power Zone Config2 Registers
- ***************************************************************************/
-/* HIF_CPUBIUCTRL :: CPU2_PWR_ZONE_CONFIG2_REG :: MEM_OFF_DLY [31:28] */
-#define BCHP_HIF_CPUBIUCTRL_CPU2_PWR_ZONE_CONFIG2_REG_MEM_OFF_DLY_MASK 0xf0000000
-#define BCHP_HIF_CPUBIUCTRL_CPU2_PWR_ZONE_CONFIG2_REG_MEM_OFF_DLY_SHIFT 28
-#define BCHP_HIF_CPUBIUCTRL_CPU2_PWR_ZONE_CONFIG2_REG_MEM_OFF_DLY_DEFAULT 0x00000004
-
-/* HIF_CPUBIUCTRL :: CPU2_PWR_ZONE_CONFIG2_REG :: MEM_ON_DLY [27:24] */
-#define BCHP_HIF_CPUBIUCTRL_CPU2_PWR_ZONE_CONFIG2_REG_MEM_ON_DLY_MASK 0x0f000000
-#define BCHP_HIF_CPUBIUCTRL_CPU2_PWR_ZONE_CONFIG2_REG_MEM_ON_DLY_SHIFT 24
-#define BCHP_HIF_CPUBIUCTRL_CPU2_PWR_ZONE_CONFIG2_REG_MEM_ON_DLY_DEFAULT 0x00000004
-
-/* HIF_CPUBIUCTRL :: CPU2_PWR_ZONE_CONFIG2_REG :: DPG_OFF_DLY [23:20] */
-#define BCHP_HIF_CPUBIUCTRL_CPU2_PWR_ZONE_CONFIG2_REG_DPG_OFF_DLY_MASK 0x00f00000
-#define BCHP_HIF_CPUBIUCTRL_CPU2_PWR_ZONE_CONFIG2_REG_DPG_OFF_DLY_SHIFT 20
-#define BCHP_HIF_CPUBIUCTRL_CPU2_PWR_ZONE_CONFIG2_REG_DPG_OFF_DLY_DEFAULT 0x00000004
-
-/* HIF_CPUBIUCTRL :: CPU2_PWR_ZONE_CONFIG2_REG :: DPG1_ON_DLY [19:16] */
-#define BCHP_HIF_CPUBIUCTRL_CPU2_PWR_ZONE_CONFIG2_REG_DPG1_ON_DLY_MASK 0x000f0000
-#define BCHP_HIF_CPUBIUCTRL_CPU2_PWR_ZONE_CONFIG2_REG_DPG1_ON_DLY_SHIFT 16
-#define BCHP_HIF_CPUBIUCTRL_CPU2_PWR_ZONE_CONFIG2_REG_DPG1_ON_DLY_DEFAULT 0x00000003
-
-/* HIF_CPUBIUCTRL :: CPU2_PWR_ZONE_CONFIG2_REG :: DPGN_ON_DLY [15:12] */
-#define BCHP_HIF_CPUBIUCTRL_CPU2_PWR_ZONE_CONFIG2_REG_DPGN_ON_DLY_MASK 0x0000f000
-#define BCHP_HIF_CPUBIUCTRL_CPU2_PWR_ZONE_CONFIG2_REG_DPGN_ON_DLY_SHIFT 12
-#define BCHP_HIF_CPUBIUCTRL_CPU2_PWR_ZONE_CONFIG2_REG_DPGN_ON_DLY_DEFAULT 0x00000001
-
-/* HIF_CPUBIUCTRL :: CPU2_PWR_ZONE_CONFIG2_REG :: reserved0 [11:06] */
-#define BCHP_HIF_CPUBIUCTRL_CPU2_PWR_ZONE_CONFIG2_REG_reserved0_MASK 0x00000fc0
-#define BCHP_HIF_CPUBIUCTRL_CPU2_PWR_ZONE_CONFIG2_REG_reserved0_SHIFT 6
-
-/* HIF_CPUBIUCTRL :: CPU2_PWR_ZONE_CONFIG2_REG :: SLEW_PRESCALE_SEL [05:03] */
-#define BCHP_HIF_CPUBIUCTRL_CPU2_PWR_ZONE_CONFIG2_REG_SLEW_PRESCALE_SEL_MASK 0x00000038
-#define BCHP_HIF_CPUBIUCTRL_CPU2_PWR_ZONE_CONFIG2_REG_SLEW_PRESCALE_SEL_SHIFT 3
-#define BCHP_HIF_CPUBIUCTRL_CPU2_PWR_ZONE_CONFIG2_REG_SLEW_PRESCALE_SEL_DEFAULT 0x00000002
-
-/* HIF_CPUBIUCTRL :: CPU2_PWR_ZONE_CONFIG2_REG :: DELAY_PRESCALE_SEL [02:00] */
-#define BCHP_HIF_CPUBIUCTRL_CPU2_PWR_ZONE_CONFIG2_REG_DELAY_PRESCALE_SEL_MASK 0x00000007
-#define BCHP_HIF_CPUBIUCTRL_CPU2_PWR_ZONE_CONFIG2_REG_DELAY_PRESCALE_SEL_SHIFT 0
-#define BCHP_HIF_CPUBIUCTRL_CPU2_PWR_ZONE_CONFIG2_REG_DELAY_PRESCALE_SEL_DEFAULT 0x00000002
-
-/***************************************************************************
- *CPU3_PWR_ZONE_CONFIG1_REG - CPU3 Power Zone Config1 Registers
- ***************************************************************************/
-/* HIF_CPUBIUCTRL :: CPU3_PWR_ZONE_CONFIG1_REG :: RST_OFF_DLY [31:28] */
-#define BCHP_HIF_CPUBIUCTRL_CPU3_PWR_ZONE_CONFIG1_REG_RST_OFF_DLY_MASK 0xf0000000
-#define BCHP_HIF_CPUBIUCTRL_CPU3_PWR_ZONE_CONFIG1_REG_RST_OFF_DLY_SHIFT 28
-#define BCHP_HIF_CPUBIUCTRL_CPU3_PWR_ZONE_CONFIG1_REG_RST_OFF_DLY_DEFAULT 0x00000004
-
-/* HIF_CPUBIUCTRL :: CPU3_PWR_ZONE_CONFIG1_REG :: RST_ON_DLY [27:24] */
-#define BCHP_HIF_CPUBIUCTRL_CPU3_PWR_ZONE_CONFIG1_REG_RST_ON_DLY_MASK 0x0f000000
-#define BCHP_HIF_CPUBIUCTRL_CPU3_PWR_ZONE_CONFIG1_REG_RST_ON_DLY_SHIFT 24
-#define BCHP_HIF_CPUBIUCTRL_CPU3_PWR_ZONE_CONFIG1_REG_RST_ON_DLY_DEFAULT 0x00000004
-
-/* HIF_CPUBIUCTRL :: CPU3_PWR_ZONE_CONFIG1_REG :: CLK_OFF_DLY [23:20] */
-#define BCHP_HIF_CPUBIUCTRL_CPU3_PWR_ZONE_CONFIG1_REG_CLK_OFF_DLY_MASK 0x00f00000
-#define BCHP_HIF_CPUBIUCTRL_CPU3_PWR_ZONE_CONFIG1_REG_CLK_OFF_DLY_SHIFT 20
-#define BCHP_HIF_CPUBIUCTRL_CPU3_PWR_ZONE_CONFIG1_REG_CLK_OFF_DLY_DEFAULT 0x00000004
-
-/* HIF_CPUBIUCTRL :: CPU3_PWR_ZONE_CONFIG1_REG :: CLK_ON_DLY [19:16] */
-#define BCHP_HIF_CPUBIUCTRL_CPU3_PWR_ZONE_CONFIG1_REG_CLK_ON_DLY_MASK 0x000f0000
-#define BCHP_HIF_CPUBIUCTRL_CPU3_PWR_ZONE_CONFIG1_REG_CLK_ON_DLY_SHIFT 16
-#define BCHP_HIF_CPUBIUCTRL_CPU3_PWR_ZONE_CONFIG1_REG_CLK_ON_DLY_DEFAULT 0x00000004
-
-/* HIF_CPUBIUCTRL :: CPU3_PWR_ZONE_CONFIG1_REG :: ISO_OFF_DLY [15:12] */
-#define BCHP_HIF_CPUBIUCTRL_CPU3_PWR_ZONE_CONFIG1_REG_ISO_OFF_DLY_MASK 0x0000f000
-#define BCHP_HIF_CPUBIUCTRL_CPU3_PWR_ZONE_CONFIG1_REG_ISO_OFF_DLY_SHIFT 12
-#define BCHP_HIF_CPUBIUCTRL_CPU3_PWR_ZONE_CONFIG1_REG_ISO_OFF_DLY_DEFAULT 0x00000004
-
-/* HIF_CPUBIUCTRL :: CPU3_PWR_ZONE_CONFIG1_REG :: ISO_ON_DLY [11:08] */
-#define BCHP_HIF_CPUBIUCTRL_CPU3_PWR_ZONE_CONFIG1_REG_ISO_ON_DLY_MASK 0x00000f00
-#define BCHP_HIF_CPUBIUCTRL_CPU3_PWR_ZONE_CONFIG1_REG_ISO_ON_DLY_SHIFT 8
-#define BCHP_HIF_CPUBIUCTRL_CPU3_PWR_ZONE_CONFIG1_REG_ISO_ON_DLY_DEFAULT 0x00000004
-
-/* HIF_CPUBIUCTRL :: CPU3_PWR_ZONE_CONFIG1_REG :: reserved0 [07:05] */
-#define BCHP_HIF_CPUBIUCTRL_CPU3_PWR_ZONE_CONFIG1_REG_reserved0_MASK 0x000000e0
-#define BCHP_HIF_CPUBIUCTRL_CPU3_PWR_ZONE_CONFIG1_REG_reserved0_SHIFT 5
-
-/* HIF_CPUBIUCTRL :: CPU3_PWR_ZONE_CONFIG1_REG :: PWROK_TRESH [04:03] */
-#define BCHP_HIF_CPUBIUCTRL_CPU3_PWR_ZONE_CONFIG1_REG_PWROK_TRESH_MASK 0x00000018
-#define BCHP_HIF_CPUBIUCTRL_CPU3_PWR_ZONE_CONFIG1_REG_PWROK_TRESH_SHIFT 3
-#define BCHP_HIF_CPUBIUCTRL_CPU3_PWR_ZONE_CONFIG1_REG_PWROK_TRESH_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: CPU3_PWR_ZONE_CONFIG1_REG :: PWROK_DELAY_SEL [02:00] */
-#define BCHP_HIF_CPUBIUCTRL_CPU3_PWR_ZONE_CONFIG1_REG_PWROK_DELAY_SEL_MASK 0x00000007
-#define BCHP_HIF_CPUBIUCTRL_CPU3_PWR_ZONE_CONFIG1_REG_PWROK_DELAY_SEL_SHIFT 0
-#define BCHP_HIF_CPUBIUCTRL_CPU3_PWR_ZONE_CONFIG1_REG_PWROK_DELAY_SEL_DEFAULT 0x00000000
-
-/***************************************************************************
- *CPU3_PWR_ZONE_CONFIG2_REG - CPU3 Power Zone Config2 Registers
- ***************************************************************************/
-/* HIF_CPUBIUCTRL :: CPU3_PWR_ZONE_CONFIG2_REG :: MEM_OFF_DLY [31:28] */
-#define BCHP_HIF_CPUBIUCTRL_CPU3_PWR_ZONE_CONFIG2_REG_MEM_OFF_DLY_MASK 0xf0000000
-#define BCHP_HIF_CPUBIUCTRL_CPU3_PWR_ZONE_CONFIG2_REG_MEM_OFF_DLY_SHIFT 28
-#define BCHP_HIF_CPUBIUCTRL_CPU3_PWR_ZONE_CONFIG2_REG_MEM_OFF_DLY_DEFAULT 0x00000004
-
-/* HIF_CPUBIUCTRL :: CPU3_PWR_ZONE_CONFIG2_REG :: MEM_ON_DLY [27:24] */
-#define BCHP_HIF_CPUBIUCTRL_CPU3_PWR_ZONE_CONFIG2_REG_MEM_ON_DLY_MASK 0x0f000000
-#define BCHP_HIF_CPUBIUCTRL_CPU3_PWR_ZONE_CONFIG2_REG_MEM_ON_DLY_SHIFT 24
-#define BCHP_HIF_CPUBIUCTRL_CPU3_PWR_ZONE_CONFIG2_REG_MEM_ON_DLY_DEFAULT 0x00000004
-
-/* HIF_CPUBIUCTRL :: CPU3_PWR_ZONE_CONFIG2_REG :: DPG_OFF_DLY [23:20] */
-#define BCHP_HIF_CPUBIUCTRL_CPU3_PWR_ZONE_CONFIG2_REG_DPG_OFF_DLY_MASK 0x00f00000
-#define BCHP_HIF_CPUBIUCTRL_CPU3_PWR_ZONE_CONFIG2_REG_DPG_OFF_DLY_SHIFT 20
-#define BCHP_HIF_CPUBIUCTRL_CPU3_PWR_ZONE_CONFIG2_REG_DPG_OFF_DLY_DEFAULT 0x00000004
-
-/* HIF_CPUBIUCTRL :: CPU3_PWR_ZONE_CONFIG2_REG :: DPG1_ON_DLY [19:16] */
-#define BCHP_HIF_CPUBIUCTRL_CPU3_PWR_ZONE_CONFIG2_REG_DPG1_ON_DLY_MASK 0x000f0000
-#define BCHP_HIF_CPUBIUCTRL_CPU3_PWR_ZONE_CONFIG2_REG_DPG1_ON_DLY_SHIFT 16
-#define BCHP_HIF_CPUBIUCTRL_CPU3_PWR_ZONE_CONFIG2_REG_DPG1_ON_DLY_DEFAULT 0x00000003
-
-/* HIF_CPUBIUCTRL :: CPU3_PWR_ZONE_CONFIG2_REG :: DPGN_ON_DLY [15:12] */
-#define BCHP_HIF_CPUBIUCTRL_CPU3_PWR_ZONE_CONFIG2_REG_DPGN_ON_DLY_MASK 0x0000f000
-#define BCHP_HIF_CPUBIUCTRL_CPU3_PWR_ZONE_CONFIG2_REG_DPGN_ON_DLY_SHIFT 12
-#define BCHP_HIF_CPUBIUCTRL_CPU3_PWR_ZONE_CONFIG2_REG_DPGN_ON_DLY_DEFAULT 0x00000001
-
-/* HIF_CPUBIUCTRL :: CPU3_PWR_ZONE_CONFIG2_REG :: reserved0 [11:06] */
-#define BCHP_HIF_CPUBIUCTRL_CPU3_PWR_ZONE_CONFIG2_REG_reserved0_MASK 0x00000fc0
-#define BCHP_HIF_CPUBIUCTRL_CPU3_PWR_ZONE_CONFIG2_REG_reserved0_SHIFT 6
-
-/* HIF_CPUBIUCTRL :: CPU3_PWR_ZONE_CONFIG2_REG :: SLEW_PRESCALE_SEL [05:03] */
-#define BCHP_HIF_CPUBIUCTRL_CPU3_PWR_ZONE_CONFIG2_REG_SLEW_PRESCALE_SEL_MASK 0x00000038
-#define BCHP_HIF_CPUBIUCTRL_CPU3_PWR_ZONE_CONFIG2_REG_SLEW_PRESCALE_SEL_SHIFT 3
-#define BCHP_HIF_CPUBIUCTRL_CPU3_PWR_ZONE_CONFIG2_REG_SLEW_PRESCALE_SEL_DEFAULT 0x00000002
-
-/* HIF_CPUBIUCTRL :: CPU3_PWR_ZONE_CONFIG2_REG :: DELAY_PRESCALE_SEL [02:00] */
-#define BCHP_HIF_CPUBIUCTRL_CPU3_PWR_ZONE_CONFIG2_REG_DELAY_PRESCALE_SEL_MASK 0x00000007
-#define BCHP_HIF_CPUBIUCTRL_CPU3_PWR_ZONE_CONFIG2_REG_DELAY_PRESCALE_SEL_SHIFT 0
-#define BCHP_HIF_CPUBIUCTRL_CPU3_PWR_ZONE_CONFIG2_REG_DELAY_PRESCALE_SEL_DEFAULT 0x00000002
-
-/***************************************************************************
- *L2BIU_PWR_ZONE_CONFIG1_REG - L2/BIU Power Zone Config1 Registers
- ***************************************************************************/
-/* HIF_CPUBIUCTRL :: L2BIU_PWR_ZONE_CONFIG1_REG :: RST_OFF_DLY [31:28] */
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_PWR_ZONE_CONFIG1_REG_RST_OFF_DLY_MASK 0xf0000000
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_PWR_ZONE_CONFIG1_REG_RST_OFF_DLY_SHIFT 28
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_PWR_ZONE_CONFIG1_REG_RST_OFF_DLY_DEFAULT 0x00000004
-
-/* HIF_CPUBIUCTRL :: L2BIU_PWR_ZONE_CONFIG1_REG :: RST_ON_DLY [27:24] */
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_PWR_ZONE_CONFIG1_REG_RST_ON_DLY_MASK 0x0f000000
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_PWR_ZONE_CONFIG1_REG_RST_ON_DLY_SHIFT 24
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_PWR_ZONE_CONFIG1_REG_RST_ON_DLY_DEFAULT 0x00000004
-
-/* HIF_CPUBIUCTRL :: L2BIU_PWR_ZONE_CONFIG1_REG :: CLK_OFF_DLY [23:20] */
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_PWR_ZONE_CONFIG1_REG_CLK_OFF_DLY_MASK 0x00f00000
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_PWR_ZONE_CONFIG1_REG_CLK_OFF_DLY_SHIFT 20
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_PWR_ZONE_CONFIG1_REG_CLK_OFF_DLY_DEFAULT 0x00000004
-
-/* HIF_CPUBIUCTRL :: L2BIU_PWR_ZONE_CONFIG1_REG :: CLK_ON_DLY [19:16] */
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_PWR_ZONE_CONFIG1_REG_CLK_ON_DLY_MASK 0x000f0000
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_PWR_ZONE_CONFIG1_REG_CLK_ON_DLY_SHIFT 16
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_PWR_ZONE_CONFIG1_REG_CLK_ON_DLY_DEFAULT 0x00000004
-
-/* HIF_CPUBIUCTRL :: L2BIU_PWR_ZONE_CONFIG1_REG :: ISO_OFF_DLY [15:12] */
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_PWR_ZONE_CONFIG1_REG_ISO_OFF_DLY_MASK 0x0000f000
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_PWR_ZONE_CONFIG1_REG_ISO_OFF_DLY_SHIFT 12
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_PWR_ZONE_CONFIG1_REG_ISO_OFF_DLY_DEFAULT 0x00000004
-
-/* HIF_CPUBIUCTRL :: L2BIU_PWR_ZONE_CONFIG1_REG :: ISO_ON_DLY [11:08] */
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_PWR_ZONE_CONFIG1_REG_ISO_ON_DLY_MASK 0x00000f00
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_PWR_ZONE_CONFIG1_REG_ISO_ON_DLY_SHIFT 8
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_PWR_ZONE_CONFIG1_REG_ISO_ON_DLY_DEFAULT 0x00000004
-
-/* HIF_CPUBIUCTRL :: L2BIU_PWR_ZONE_CONFIG1_REG :: reserved0 [07:05] */
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_PWR_ZONE_CONFIG1_REG_reserved0_MASK 0x000000e0
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_PWR_ZONE_CONFIG1_REG_reserved0_SHIFT 5
-
-/* HIF_CPUBIUCTRL :: L2BIU_PWR_ZONE_CONFIG1_REG :: PWROK_TRESH [04:03] */
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_PWR_ZONE_CONFIG1_REG_PWROK_TRESH_MASK 0x00000018
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_PWR_ZONE_CONFIG1_REG_PWROK_TRESH_SHIFT 3
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_PWR_ZONE_CONFIG1_REG_PWROK_TRESH_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: L2BIU_PWR_ZONE_CONFIG1_REG :: PWROK_DELAY_SEL [02:00] */
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_PWR_ZONE_CONFIG1_REG_PWROK_DELAY_SEL_MASK 0x00000007
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_PWR_ZONE_CONFIG1_REG_PWROK_DELAY_SEL_SHIFT 0
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_PWR_ZONE_CONFIG1_REG_PWROK_DELAY_SEL_DEFAULT 0x00000000
-
-/***************************************************************************
- *L2BIU_PWR_ZONE_CONFIG2_REG - L2/BIU Power Zone Config2 Registers
- ***************************************************************************/
-/* HIF_CPUBIUCTRL :: L2BIU_PWR_ZONE_CONFIG2_REG :: MEM_OFF_DLY [31:28] */
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_PWR_ZONE_CONFIG2_REG_MEM_OFF_DLY_MASK 0xf0000000
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_PWR_ZONE_CONFIG2_REG_MEM_OFF_DLY_SHIFT 28
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_PWR_ZONE_CONFIG2_REG_MEM_OFF_DLY_DEFAULT 0x00000004
-
-/* HIF_CPUBIUCTRL :: L2BIU_PWR_ZONE_CONFIG2_REG :: MEM_ON_DLY [27:24] */
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_PWR_ZONE_CONFIG2_REG_MEM_ON_DLY_MASK 0x0f000000
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_PWR_ZONE_CONFIG2_REG_MEM_ON_DLY_SHIFT 24
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_PWR_ZONE_CONFIG2_REG_MEM_ON_DLY_DEFAULT 0x00000004
-
-/* HIF_CPUBIUCTRL :: L2BIU_PWR_ZONE_CONFIG2_REG :: DPG_OFF_DLY [23:20] */
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_PWR_ZONE_CONFIG2_REG_DPG_OFF_DLY_MASK 0x00f00000
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_PWR_ZONE_CONFIG2_REG_DPG_OFF_DLY_SHIFT 20
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_PWR_ZONE_CONFIG2_REG_DPG_OFF_DLY_DEFAULT 0x00000004
-
-/* HIF_CPUBIUCTRL :: L2BIU_PWR_ZONE_CONFIG2_REG :: DPG1_ON_DLY [19:16] */
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_PWR_ZONE_CONFIG2_REG_DPG1_ON_DLY_MASK 0x000f0000
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_PWR_ZONE_CONFIG2_REG_DPG1_ON_DLY_SHIFT 16
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_PWR_ZONE_CONFIG2_REG_DPG1_ON_DLY_DEFAULT 0x00000003
-
-/* HIF_CPUBIUCTRL :: L2BIU_PWR_ZONE_CONFIG2_REG :: DPGN_ON_DLY [15:12] */
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_PWR_ZONE_CONFIG2_REG_DPGN_ON_DLY_MASK 0x0000f000
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_PWR_ZONE_CONFIG2_REG_DPGN_ON_DLY_SHIFT 12
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_PWR_ZONE_CONFIG2_REG_DPGN_ON_DLY_DEFAULT 0x00000001
-
-/* HIF_CPUBIUCTRL :: L2BIU_PWR_ZONE_CONFIG2_REG :: reserved0 [11:06] */
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_PWR_ZONE_CONFIG2_REG_reserved0_MASK 0x00000fc0
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_PWR_ZONE_CONFIG2_REG_reserved0_SHIFT 6
-
-/* HIF_CPUBIUCTRL :: L2BIU_PWR_ZONE_CONFIG2_REG :: SLEW_PRESCALE_SEL [05:03] */
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_PWR_ZONE_CONFIG2_REG_SLEW_PRESCALE_SEL_MASK 0x00000038
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_PWR_ZONE_CONFIG2_REG_SLEW_PRESCALE_SEL_SHIFT 3
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_PWR_ZONE_CONFIG2_REG_SLEW_PRESCALE_SEL_DEFAULT 0x00000002
-
-/* HIF_CPUBIUCTRL :: L2BIU_PWR_ZONE_CONFIG2_REG :: DELAY_PRESCALE_SEL [02:00] */
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_PWR_ZONE_CONFIG2_REG_DELAY_PRESCALE_SEL_MASK 0x00000007
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_PWR_ZONE_CONFIG2_REG_DELAY_PRESCALE_SEL_SHIFT 0
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_PWR_ZONE_CONFIG2_REG_DELAY_PRESCALE_SEL_DEFAULT 0x00000002
-
-/***************************************************************************
- *CPU0_PWR_FREQ_SCALAR_CTRL_REG - CPU0 BPCM Frequency Scalar Control Register
- ***************************************************************************/
-/* HIF_CPUBIUCTRL :: CPU0_PWR_FREQ_SCALAR_CTRL_REG :: reserved0 [31:10] */
-#define BCHP_HIF_CPUBIUCTRL_CPU0_PWR_FREQ_SCALAR_CTRL_REG_reserved0_MASK 0xfffffc00
-#define BCHP_HIF_CPUBIUCTRL_CPU0_PWR_FREQ_SCALAR_CTRL_REG_reserved0_SHIFT 10
-
-/* HIF_CPUBIUCTRL :: CPU0_PWR_FREQ_SCALAR_CTRL_REG :: HIGH_GEAR_DIV [09:07] */
-#define BCHP_HIF_CPUBIUCTRL_CPU0_PWR_FREQ_SCALAR_CTRL_REG_HIGH_GEAR_DIV_MASK 0x00000380
-#define BCHP_HIF_CPUBIUCTRL_CPU0_PWR_FREQ_SCALAR_CTRL_REG_HIGH_GEAR_DIV_SHIFT 7
-#define BCHP_HIF_CPUBIUCTRL_CPU0_PWR_FREQ_SCALAR_CTRL_REG_HIGH_GEAR_DIV_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: CPU0_PWR_FREQ_SCALAR_CTRL_REG :: LOW_GEAR_DIV [06:04] */
-#define BCHP_HIF_CPUBIUCTRL_CPU0_PWR_FREQ_SCALAR_CTRL_REG_LOW_GEAR_DIV_MASK 0x00000070
-#define BCHP_HIF_CPUBIUCTRL_CPU0_PWR_FREQ_SCALAR_CTRL_REG_LOW_GEAR_DIV_SHIFT 4
-#define BCHP_HIF_CPUBIUCTRL_CPU0_PWR_FREQ_SCALAR_CTRL_REG_LOW_GEAR_DIV_DEFAULT 0x00000001
-
-/* HIF_CPUBIUCTRL :: CPU0_PWR_FREQ_SCALAR_CTRL_REG :: reserved1 [03:03] */
-#define BCHP_HIF_CPUBIUCTRL_CPU0_PWR_FREQ_SCALAR_CTRL_REG_reserved1_MASK 0x00000008
-#define BCHP_HIF_CPUBIUCTRL_CPU0_PWR_FREQ_SCALAR_CTRL_REG_reserved1_SHIFT 3
-
-/* HIF_CPUBIUCTRL :: CPU0_PWR_FREQ_SCALAR_CTRL_REG :: USE_DYN_GEAR_SEL [02:02] */
-#define BCHP_HIF_CPUBIUCTRL_CPU0_PWR_FREQ_SCALAR_CTRL_REG_USE_DYN_GEAR_SEL_MASK 0x00000004
-#define BCHP_HIF_CPUBIUCTRL_CPU0_PWR_FREQ_SCALAR_CTRL_REG_USE_DYN_GEAR_SEL_SHIFT 2
-#define BCHP_HIF_CPUBIUCTRL_CPU0_PWR_FREQ_SCALAR_CTRL_REG_USE_DYN_GEAR_SEL_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: CPU0_PWR_FREQ_SCALAR_CTRL_REG :: GEAR_SELECT [01:01] */
-#define BCHP_HIF_CPUBIUCTRL_CPU0_PWR_FREQ_SCALAR_CTRL_REG_GEAR_SELECT_MASK 0x00000002
-#define BCHP_HIF_CPUBIUCTRL_CPU0_PWR_FREQ_SCALAR_CTRL_REG_GEAR_SELECT_SHIFT 1
-#define BCHP_HIF_CPUBIUCTRL_CPU0_PWR_FREQ_SCALAR_CTRL_REG_GEAR_SELECT_DEFAULT 0x00000001
-
-/* HIF_CPUBIUCTRL :: CPU0_PWR_FREQ_SCALAR_CTRL_REG :: FS_BYPASS_EN [00:00] */
-#define BCHP_HIF_CPUBIUCTRL_CPU0_PWR_FREQ_SCALAR_CTRL_REG_FS_BYPASS_EN_MASK 0x00000001
-#define BCHP_HIF_CPUBIUCTRL_CPU0_PWR_FREQ_SCALAR_CTRL_REG_FS_BYPASS_EN_SHIFT 0
-#define BCHP_HIF_CPUBIUCTRL_CPU0_PWR_FREQ_SCALAR_CTRL_REG_FS_BYPASS_EN_DEFAULT 0x00000000
-
-/***************************************************************************
- *CPU1_PWR_FREQ_SCALAR_CTRL_REG - CPU1 BPCM Frequency Scalar Control Register
- ***************************************************************************/
-/* HIF_CPUBIUCTRL :: CPU1_PWR_FREQ_SCALAR_CTRL_REG :: reserved0 [31:10] */
-#define BCHP_HIF_CPUBIUCTRL_CPU1_PWR_FREQ_SCALAR_CTRL_REG_reserved0_MASK 0xfffffc00
-#define BCHP_HIF_CPUBIUCTRL_CPU1_PWR_FREQ_SCALAR_CTRL_REG_reserved0_SHIFT 10
-
-/* HIF_CPUBIUCTRL :: CPU1_PWR_FREQ_SCALAR_CTRL_REG :: HIGH_GEAR_DIV [09:07] */
-#define BCHP_HIF_CPUBIUCTRL_CPU1_PWR_FREQ_SCALAR_CTRL_REG_HIGH_GEAR_DIV_MASK 0x00000380
-#define BCHP_HIF_CPUBIUCTRL_CPU1_PWR_FREQ_SCALAR_CTRL_REG_HIGH_GEAR_DIV_SHIFT 7
-#define BCHP_HIF_CPUBIUCTRL_CPU1_PWR_FREQ_SCALAR_CTRL_REG_HIGH_GEAR_DIV_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: CPU1_PWR_FREQ_SCALAR_CTRL_REG :: LOW_GEAR_DIV [06:04] */
-#define BCHP_HIF_CPUBIUCTRL_CPU1_PWR_FREQ_SCALAR_CTRL_REG_LOW_GEAR_DIV_MASK 0x00000070
-#define BCHP_HIF_CPUBIUCTRL_CPU1_PWR_FREQ_SCALAR_CTRL_REG_LOW_GEAR_DIV_SHIFT 4
-#define BCHP_HIF_CPUBIUCTRL_CPU1_PWR_FREQ_SCALAR_CTRL_REG_LOW_GEAR_DIV_DEFAULT 0x00000001
-
-/* HIF_CPUBIUCTRL :: CPU1_PWR_FREQ_SCALAR_CTRL_REG :: reserved1 [03:03] */
-#define BCHP_HIF_CPUBIUCTRL_CPU1_PWR_FREQ_SCALAR_CTRL_REG_reserved1_MASK 0x00000008
-#define BCHP_HIF_CPUBIUCTRL_CPU1_PWR_FREQ_SCALAR_CTRL_REG_reserved1_SHIFT 3
-
-/* HIF_CPUBIUCTRL :: CPU1_PWR_FREQ_SCALAR_CTRL_REG :: USE_DYN_GEAR_SEL [02:02] */
-#define BCHP_HIF_CPUBIUCTRL_CPU1_PWR_FREQ_SCALAR_CTRL_REG_USE_DYN_GEAR_SEL_MASK 0x00000004
-#define BCHP_HIF_CPUBIUCTRL_CPU1_PWR_FREQ_SCALAR_CTRL_REG_USE_DYN_GEAR_SEL_SHIFT 2
-#define BCHP_HIF_CPUBIUCTRL_CPU1_PWR_FREQ_SCALAR_CTRL_REG_USE_DYN_GEAR_SEL_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: CPU1_PWR_FREQ_SCALAR_CTRL_REG :: GEAR_SELECT [01:01] */
-#define BCHP_HIF_CPUBIUCTRL_CPU1_PWR_FREQ_SCALAR_CTRL_REG_GEAR_SELECT_MASK 0x00000002
-#define BCHP_HIF_CPUBIUCTRL_CPU1_PWR_FREQ_SCALAR_CTRL_REG_GEAR_SELECT_SHIFT 1
-#define BCHP_HIF_CPUBIUCTRL_CPU1_PWR_FREQ_SCALAR_CTRL_REG_GEAR_SELECT_DEFAULT 0x00000001
-
-/* HIF_CPUBIUCTRL :: CPU1_PWR_FREQ_SCALAR_CTRL_REG :: FS_BYPASS_EN [00:00] */
-#define BCHP_HIF_CPUBIUCTRL_CPU1_PWR_FREQ_SCALAR_CTRL_REG_FS_BYPASS_EN_MASK 0x00000001
-#define BCHP_HIF_CPUBIUCTRL_CPU1_PWR_FREQ_SCALAR_CTRL_REG_FS_BYPASS_EN_SHIFT 0
-#define BCHP_HIF_CPUBIUCTRL_CPU1_PWR_FREQ_SCALAR_CTRL_REG_FS_BYPASS_EN_DEFAULT 0x00000000
-
-/***************************************************************************
- *CPU2_PWR_FREQ_SCALAR_CTRL_REG - CPU2 BPCM Frequency Scalar Control Register
- ***************************************************************************/
-/* HIF_CPUBIUCTRL :: CPU2_PWR_FREQ_SCALAR_CTRL_REG :: reserved0 [31:10] */
-#define BCHP_HIF_CPUBIUCTRL_CPU2_PWR_FREQ_SCALAR_CTRL_REG_reserved0_MASK 0xfffffc00
-#define BCHP_HIF_CPUBIUCTRL_CPU2_PWR_FREQ_SCALAR_CTRL_REG_reserved0_SHIFT 10
-
-/* HIF_CPUBIUCTRL :: CPU2_PWR_FREQ_SCALAR_CTRL_REG :: HIGH_GEAR_DIV [09:07] */
-#define BCHP_HIF_CPUBIUCTRL_CPU2_PWR_FREQ_SCALAR_CTRL_REG_HIGH_GEAR_DIV_MASK 0x00000380
-#define BCHP_HIF_CPUBIUCTRL_CPU2_PWR_FREQ_SCALAR_CTRL_REG_HIGH_GEAR_DIV_SHIFT 7
-#define BCHP_HIF_CPUBIUCTRL_CPU2_PWR_FREQ_SCALAR_CTRL_REG_HIGH_GEAR_DIV_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: CPU2_PWR_FREQ_SCALAR_CTRL_REG :: LOW_GEAR_DIV [06:04] */
-#define BCHP_HIF_CPUBIUCTRL_CPU2_PWR_FREQ_SCALAR_CTRL_REG_LOW_GEAR_DIV_MASK 0x00000070
-#define BCHP_HIF_CPUBIUCTRL_CPU2_PWR_FREQ_SCALAR_CTRL_REG_LOW_GEAR_DIV_SHIFT 4
-#define BCHP_HIF_CPUBIUCTRL_CPU2_PWR_FREQ_SCALAR_CTRL_REG_LOW_GEAR_DIV_DEFAULT 0x00000001
-
-/* HIF_CPUBIUCTRL :: CPU2_PWR_FREQ_SCALAR_CTRL_REG :: reserved1 [03:03] */
-#define BCHP_HIF_CPUBIUCTRL_CPU2_PWR_FREQ_SCALAR_CTRL_REG_reserved1_MASK 0x00000008
-#define BCHP_HIF_CPUBIUCTRL_CPU2_PWR_FREQ_SCALAR_CTRL_REG_reserved1_SHIFT 3
-
-/* HIF_CPUBIUCTRL :: CPU2_PWR_FREQ_SCALAR_CTRL_REG :: USE_DYN_GEAR_SEL [02:02] */
-#define BCHP_HIF_CPUBIUCTRL_CPU2_PWR_FREQ_SCALAR_CTRL_REG_USE_DYN_GEAR_SEL_MASK 0x00000004
-#define BCHP_HIF_CPUBIUCTRL_CPU2_PWR_FREQ_SCALAR_CTRL_REG_USE_DYN_GEAR_SEL_SHIFT 2
-#define BCHP_HIF_CPUBIUCTRL_CPU2_PWR_FREQ_SCALAR_CTRL_REG_USE_DYN_GEAR_SEL_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: CPU2_PWR_FREQ_SCALAR_CTRL_REG :: GEAR_SELECT [01:01] */
-#define BCHP_HIF_CPUBIUCTRL_CPU2_PWR_FREQ_SCALAR_CTRL_REG_GEAR_SELECT_MASK 0x00000002
-#define BCHP_HIF_CPUBIUCTRL_CPU2_PWR_FREQ_SCALAR_CTRL_REG_GEAR_SELECT_SHIFT 1
-#define BCHP_HIF_CPUBIUCTRL_CPU2_PWR_FREQ_SCALAR_CTRL_REG_GEAR_SELECT_DEFAULT 0x00000001
-
-/* HIF_CPUBIUCTRL :: CPU2_PWR_FREQ_SCALAR_CTRL_REG :: FS_BYPASS_EN [00:00] */
-#define BCHP_HIF_CPUBIUCTRL_CPU2_PWR_FREQ_SCALAR_CTRL_REG_FS_BYPASS_EN_MASK 0x00000001
-#define BCHP_HIF_CPUBIUCTRL_CPU2_PWR_FREQ_SCALAR_CTRL_REG_FS_BYPASS_EN_SHIFT 0
-#define BCHP_HIF_CPUBIUCTRL_CPU2_PWR_FREQ_SCALAR_CTRL_REG_FS_BYPASS_EN_DEFAULT 0x00000000
-
-/***************************************************************************
- *CPU3_PWR_FREQ_SCALAR_CTRL_REG - CPU3 BPCM Frequency Scalar Control Register
- ***************************************************************************/
-/* HIF_CPUBIUCTRL :: CPU3_PWR_FREQ_SCALAR_CTRL_REG :: reserved0 [31:10] */
-#define BCHP_HIF_CPUBIUCTRL_CPU3_PWR_FREQ_SCALAR_CTRL_REG_reserved0_MASK 0xfffffc00
-#define BCHP_HIF_CPUBIUCTRL_CPU3_PWR_FREQ_SCALAR_CTRL_REG_reserved0_SHIFT 10
-
-/* HIF_CPUBIUCTRL :: CPU3_PWR_FREQ_SCALAR_CTRL_REG :: HIGH_GEAR_DIV [09:07] */
-#define BCHP_HIF_CPUBIUCTRL_CPU3_PWR_FREQ_SCALAR_CTRL_REG_HIGH_GEAR_DIV_MASK 0x00000380
-#define BCHP_HIF_CPUBIUCTRL_CPU3_PWR_FREQ_SCALAR_CTRL_REG_HIGH_GEAR_DIV_SHIFT 7
-#define BCHP_HIF_CPUBIUCTRL_CPU3_PWR_FREQ_SCALAR_CTRL_REG_HIGH_GEAR_DIV_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: CPU3_PWR_FREQ_SCALAR_CTRL_REG :: LOW_GEAR_DIV [06:04] */
-#define BCHP_HIF_CPUBIUCTRL_CPU3_PWR_FREQ_SCALAR_CTRL_REG_LOW_GEAR_DIV_MASK 0x00000070
-#define BCHP_HIF_CPUBIUCTRL_CPU3_PWR_FREQ_SCALAR_CTRL_REG_LOW_GEAR_DIV_SHIFT 4
-#define BCHP_HIF_CPUBIUCTRL_CPU3_PWR_FREQ_SCALAR_CTRL_REG_LOW_GEAR_DIV_DEFAULT 0x00000001
-
-/* HIF_CPUBIUCTRL :: CPU3_PWR_FREQ_SCALAR_CTRL_REG :: reserved1 [03:03] */
-#define BCHP_HIF_CPUBIUCTRL_CPU3_PWR_FREQ_SCALAR_CTRL_REG_reserved1_MASK 0x00000008
-#define BCHP_HIF_CPUBIUCTRL_CPU3_PWR_FREQ_SCALAR_CTRL_REG_reserved1_SHIFT 3
-
-/* HIF_CPUBIUCTRL :: CPU3_PWR_FREQ_SCALAR_CTRL_REG :: USE_DYN_GEAR_SEL [02:02] */
-#define BCHP_HIF_CPUBIUCTRL_CPU3_PWR_FREQ_SCALAR_CTRL_REG_USE_DYN_GEAR_SEL_MASK 0x00000004
-#define BCHP_HIF_CPUBIUCTRL_CPU3_PWR_FREQ_SCALAR_CTRL_REG_USE_DYN_GEAR_SEL_SHIFT 2
-#define BCHP_HIF_CPUBIUCTRL_CPU3_PWR_FREQ_SCALAR_CTRL_REG_USE_DYN_GEAR_SEL_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: CPU3_PWR_FREQ_SCALAR_CTRL_REG :: GEAR_SELECT [01:01] */
-#define BCHP_HIF_CPUBIUCTRL_CPU3_PWR_FREQ_SCALAR_CTRL_REG_GEAR_SELECT_MASK 0x00000002
-#define BCHP_HIF_CPUBIUCTRL_CPU3_PWR_FREQ_SCALAR_CTRL_REG_GEAR_SELECT_SHIFT 1
-#define BCHP_HIF_CPUBIUCTRL_CPU3_PWR_FREQ_SCALAR_CTRL_REG_GEAR_SELECT_DEFAULT 0x00000001
-
-/* HIF_CPUBIUCTRL :: CPU3_PWR_FREQ_SCALAR_CTRL_REG :: FS_BYPASS_EN [00:00] */
-#define BCHP_HIF_CPUBIUCTRL_CPU3_PWR_FREQ_SCALAR_CTRL_REG_FS_BYPASS_EN_MASK 0x00000001
-#define BCHP_HIF_CPUBIUCTRL_CPU3_PWR_FREQ_SCALAR_CTRL_REG_FS_BYPASS_EN_SHIFT 0
-#define BCHP_HIF_CPUBIUCTRL_CPU3_PWR_FREQ_SCALAR_CTRL_REG_FS_BYPASS_EN_DEFAULT 0x00000000
-
-/***************************************************************************
- *L2BIU_PWR_FREQ_SCALAR_CTRL_REG - L2/BIU BPCM Frequency Scalar Control Register
- ***************************************************************************/
-/* HIF_CPUBIUCTRL :: L2BIU_PWR_FREQ_SCALAR_CTRL_REG :: reserved0 [31:10] */
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_PWR_FREQ_SCALAR_CTRL_REG_reserved0_MASK 0xfffffc00
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_PWR_FREQ_SCALAR_CTRL_REG_reserved0_SHIFT 10
-
-/* HIF_CPUBIUCTRL :: L2BIU_PWR_FREQ_SCALAR_CTRL_REG :: HIGH_GEAR_DIV [09:07] */
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_PWR_FREQ_SCALAR_CTRL_REG_HIGH_GEAR_DIV_MASK 0x00000380
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_PWR_FREQ_SCALAR_CTRL_REG_HIGH_GEAR_DIV_SHIFT 7
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_PWR_FREQ_SCALAR_CTRL_REG_HIGH_GEAR_DIV_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: L2BIU_PWR_FREQ_SCALAR_CTRL_REG :: LOW_GEAR_DIV [06:04] */
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_PWR_FREQ_SCALAR_CTRL_REG_LOW_GEAR_DIV_MASK 0x00000070
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_PWR_FREQ_SCALAR_CTRL_REG_LOW_GEAR_DIV_SHIFT 4
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_PWR_FREQ_SCALAR_CTRL_REG_LOW_GEAR_DIV_DEFAULT 0x00000001
-
-/* HIF_CPUBIUCTRL :: L2BIU_PWR_FREQ_SCALAR_CTRL_REG :: reserved1 [03:03] */
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_PWR_FREQ_SCALAR_CTRL_REG_reserved1_MASK 0x00000008
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_PWR_FREQ_SCALAR_CTRL_REG_reserved1_SHIFT 3
-
-/* HIF_CPUBIUCTRL :: L2BIU_PWR_FREQ_SCALAR_CTRL_REG :: USE_DYN_GEAR_SEL [02:02] */
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_PWR_FREQ_SCALAR_CTRL_REG_USE_DYN_GEAR_SEL_MASK 0x00000004
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_PWR_FREQ_SCALAR_CTRL_REG_USE_DYN_GEAR_SEL_SHIFT 2
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_PWR_FREQ_SCALAR_CTRL_REG_USE_DYN_GEAR_SEL_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: L2BIU_PWR_FREQ_SCALAR_CTRL_REG :: GEAR_SELECT [01:01] */
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_PWR_FREQ_SCALAR_CTRL_REG_GEAR_SELECT_MASK 0x00000002
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_PWR_FREQ_SCALAR_CTRL_REG_GEAR_SELECT_SHIFT 1
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_PWR_FREQ_SCALAR_CTRL_REG_GEAR_SELECT_DEFAULT 0x00000001
-
-/* HIF_CPUBIUCTRL :: L2BIU_PWR_FREQ_SCALAR_CTRL_REG :: FS_BYPASS_EN [00:00] */
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_PWR_FREQ_SCALAR_CTRL_REG_FS_BYPASS_EN_MASK 0x00000001
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_PWR_FREQ_SCALAR_CTRL_REG_FS_BYPASS_EN_SHIFT 0
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_PWR_FREQ_SCALAR_CTRL_REG_FS_BYPASS_EN_DEFAULT 0x00000000
-
-/***************************************************************************
- *CPU0_BPCM_ID - CPU0 BPCM ID Register
- ***************************************************************************/
-/* HIF_CPUBIUCTRL :: CPU0_BPCM_ID :: SW_strap [31:16] */
-#define BCHP_HIF_CPUBIUCTRL_CPU0_BPCM_ID_SW_strap_MASK 0xffff0000
-#define BCHP_HIF_CPUBIUCTRL_CPU0_BPCM_ID_SW_strap_SHIFT 16
-
-/* HIF_CPUBIUCTRL :: CPU0_BPCM_ID :: HW_revision [15:08] */
-#define BCHP_HIF_CPUBIUCTRL_CPU0_BPCM_ID_HW_revision_MASK 0x0000ff00
-#define BCHP_HIF_CPUBIUCTRL_CPU0_BPCM_ID_HW_revision_SHIFT 8
-
-/* HIF_CPUBIUCTRL :: CPU0_BPCM_ID :: PMB_ADDR [07:00] */
-#define BCHP_HIF_CPUBIUCTRL_CPU0_BPCM_ID_PMB_ADDR_MASK 0x000000ff
-#define BCHP_HIF_CPUBIUCTRL_CPU0_BPCM_ID_PMB_ADDR_SHIFT 0
-
-/***************************************************************************
- *CPU0_BPCM_CAPABILITY - CPU0 BPCM Capability Register
- ***************************************************************************/
-/* HIF_CPUBIUCTRL :: CPU0_BPCM_CAPABILITY :: reserved0 [31:08] */
-#define BCHP_HIF_CPUBIUCTRL_CPU0_BPCM_CAPABILITY_reserved0_MASK 0xffffff00
-#define BCHP_HIF_CPUBIUCTRL_CPU0_BPCM_CAPABILITY_reserved0_SHIFT 8
-
-/* HIF_CPUBIUCTRL :: CPU0_BPCM_CAPABILITY :: Number_of_zones [07:00] */
-#define BCHP_HIF_CPUBIUCTRL_CPU0_BPCM_CAPABILITY_Number_of_zones_MASK 0x000000ff
-#define BCHP_HIF_CPUBIUCTRL_CPU0_BPCM_CAPABILITY_Number_of_zones_SHIFT 0
-
-/***************************************************************************
- *CPU0_BPCM_CONTROL - CPU0 BPCM Control Register
- ***************************************************************************/
-/* HIF_CPUBIUCTRL :: CPU0_BPCM_CONTROL :: TbdField [31:00] */
-#define BCHP_HIF_CPUBIUCTRL_CPU0_BPCM_CONTROL_TbdField_MASK 0xffffffff
-#define BCHP_HIF_CPUBIUCTRL_CPU0_BPCM_CONTROL_TbdField_SHIFT 0
-
-/***************************************************************************
- *CPU0_BPCM_STATUS - CPU0 BPCM Status Register
- ***************************************************************************/
-/* HIF_CPUBIUCTRL :: CPU0_BPCM_STATUS :: reserved0 [31:01] */
-#define BCHP_HIF_CPUBIUCTRL_CPU0_BPCM_STATUS_reserved0_MASK 0xfffffffe
-#define BCHP_HIF_CPUBIUCTRL_CPU0_BPCM_STATUS_reserved0_SHIFT 1
-
-/* HIF_CPUBIUCTRL :: CPU0_BPCM_STATUS :: PWD_Alert [00:00] */
-#define BCHP_HIF_CPUBIUCTRL_CPU0_BPCM_STATUS_PWD_Alert_MASK 0x00000001
-#define BCHP_HIF_CPUBIUCTRL_CPU0_BPCM_STATUS_PWD_Alert_SHIFT 0
-
-/***************************************************************************
- *CPU0_AVS_ROSC_CONTROL - CPU0 Ring Oscillator Control Register
- ***************************************************************************/
-/* HIF_CPUBIUCTRL :: CPU0_AVS_ROSC_CONTROL :: Test_interval [31:16] */
-#define BCHP_HIF_CPUBIUCTRL_CPU0_AVS_ROSC_CONTROL_Test_interval_MASK 0xffff0000
-#define BCHP_HIF_CPUBIUCTRL_CPU0_AVS_ROSC_CONTROL_Test_interval_SHIFT 16
-#define BCHP_HIF_CPUBIUCTRL_CPU0_AVS_ROSC_CONTROL_Test_interval_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: CPU0_AVS_ROSC_CONTROL :: ALERT_H [15:15] */
-#define BCHP_HIF_CPUBIUCTRL_CPU0_AVS_ROSC_CONTROL_ALERT_H_MASK 0x00008000
-#define BCHP_HIF_CPUBIUCTRL_CPU0_AVS_ROSC_CONTROL_ALERT_H_SHIFT 15
-#define BCHP_HIF_CPUBIUCTRL_CPU0_AVS_ROSC_CONTROL_ALERT_H_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: CPU0_AVS_ROSC_CONTROL :: VALID_H [14:14] */
-#define BCHP_HIF_CPUBIUCTRL_CPU0_AVS_ROSC_CONTROL_VALID_H_MASK 0x00004000
-#define BCHP_HIF_CPUBIUCTRL_CPU0_AVS_ROSC_CONTROL_VALID_H_SHIFT 14
-#define BCHP_HIF_CPUBIUCTRL_CPU0_AVS_ROSC_CONTROL_VALID_H_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: CPU0_AVS_ROSC_CONTROL :: ALERT_S [13:13] */
-#define BCHP_HIF_CPUBIUCTRL_CPU0_AVS_ROSC_CONTROL_ALERT_S_MASK 0x00002000
-#define BCHP_HIF_CPUBIUCTRL_CPU0_AVS_ROSC_CONTROL_ALERT_S_SHIFT 13
-#define BCHP_HIF_CPUBIUCTRL_CPU0_AVS_ROSC_CONTROL_ALERT_S_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: CPU0_AVS_ROSC_CONTROL :: VALID_S [12:12] */
-#define BCHP_HIF_CPUBIUCTRL_CPU0_AVS_ROSC_CONTROL_VALID_S_MASK 0x00001000
-#define BCHP_HIF_CPUBIUCTRL_CPU0_AVS_ROSC_CONTROL_VALID_S_SHIFT 12
-#define BCHP_HIF_CPUBIUCTRL_CPU0_AVS_ROSC_CONTROL_VALID_S_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: CPU0_AVS_ROSC_CONTROL :: reserved0 [11:08] */
-#define BCHP_HIF_CPUBIUCTRL_CPU0_AVS_ROSC_CONTROL_reserved0_MASK 0x00000f00
-#define BCHP_HIF_CPUBIUCTRL_CPU0_AVS_ROSC_CONTROL_reserved0_SHIFT 8
-
-/* HIF_CPUBIUCTRL :: CPU0_AVS_ROSC_CONTROL :: CONTINUOUS_H [07:07] */
-#define BCHP_HIF_CPUBIUCTRL_CPU0_AVS_ROSC_CONTROL_CONTINUOUS_H_MASK 0x00000080
-#define BCHP_HIF_CPUBIUCTRL_CPU0_AVS_ROSC_CONTROL_CONTINUOUS_H_SHIFT 7
-#define BCHP_HIF_CPUBIUCTRL_CPU0_AVS_ROSC_CONTROL_CONTINUOUS_H_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: CPU0_AVS_ROSC_CONTROL :: CONTINUOUS_S [06:06] */
-#define BCHP_HIF_CPUBIUCTRL_CPU0_AVS_ROSC_CONTROL_CONTINUOUS_S_MASK 0x00000040
-#define BCHP_HIF_CPUBIUCTRL_CPU0_AVS_ROSC_CONTROL_CONTINUOUS_S_SHIFT 6
-#define BCHP_HIF_CPUBIUCTRL_CPU0_AVS_ROSC_CONTROL_CONTINUOUS_S_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: CPU0_AVS_ROSC_CONTROL :: THRSH_EN_H [05:05] */
-#define BCHP_HIF_CPUBIUCTRL_CPU0_AVS_ROSC_CONTROL_THRSH_EN_H_MASK 0x00000020
-#define BCHP_HIF_CPUBIUCTRL_CPU0_AVS_ROSC_CONTROL_THRSH_EN_H_SHIFT 5
-#define BCHP_HIF_CPUBIUCTRL_CPU0_AVS_ROSC_CONTROL_THRSH_EN_H_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: CPU0_AVS_ROSC_CONTROL :: THRSH_EN_S [04:04] */
-#define BCHP_HIF_CPUBIUCTRL_CPU0_AVS_ROSC_CONTROL_THRSH_EN_S_MASK 0x00000010
-#define BCHP_HIF_CPUBIUCTRL_CPU0_AVS_ROSC_CONTROL_THRSH_EN_S_SHIFT 4
-#define BCHP_HIF_CPUBIUCTRL_CPU0_AVS_ROSC_CONTROL_THRSH_EN_S_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: CPU0_AVS_ROSC_CONTROL :: ECTR_EN_H [03:03] */
-#define BCHP_HIF_CPUBIUCTRL_CPU0_AVS_ROSC_CONTROL_ECTR_EN_H_MASK 0x00000008
-#define BCHP_HIF_CPUBIUCTRL_CPU0_AVS_ROSC_CONTROL_ECTR_EN_H_SHIFT 3
-#define BCHP_HIF_CPUBIUCTRL_CPU0_AVS_ROSC_CONTROL_ECTR_EN_H_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: CPU0_AVS_ROSC_CONTROL :: ECTR_EN_S [02:02] */
-#define BCHP_HIF_CPUBIUCTRL_CPU0_AVS_ROSC_CONTROL_ECTR_EN_S_MASK 0x00000004
-#define BCHP_HIF_CPUBIUCTRL_CPU0_AVS_ROSC_CONTROL_ECTR_EN_S_SHIFT 2
-#define BCHP_HIF_CPUBIUCTRL_CPU0_AVS_ROSC_CONTROL_ECTR_EN_S_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: CPU0_AVS_ROSC_CONTROL :: RO_EN_H [01:01] */
-#define BCHP_HIF_CPUBIUCTRL_CPU0_AVS_ROSC_CONTROL_RO_EN_H_MASK 0x00000002
-#define BCHP_HIF_CPUBIUCTRL_CPU0_AVS_ROSC_CONTROL_RO_EN_H_SHIFT 1
-#define BCHP_HIF_CPUBIUCTRL_CPU0_AVS_ROSC_CONTROL_RO_EN_H_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: CPU0_AVS_ROSC_CONTROL :: RO_EN_S [00:00] */
-#define BCHP_HIF_CPUBIUCTRL_CPU0_AVS_ROSC_CONTROL_RO_EN_S_MASK 0x00000001
-#define BCHP_HIF_CPUBIUCTRL_CPU0_AVS_ROSC_CONTROL_RO_EN_S_SHIFT 0
-#define BCHP_HIF_CPUBIUCTRL_CPU0_AVS_ROSC_CONTROL_RO_EN_S_DEFAULT 0x00000000
-
-/***************************************************************************
- *CPU0_AVS_ROSC_THRESHOLD - CPU0 Event Counter Threshold Register
- ***************************************************************************/
-/* HIF_CPUBIUCTRL :: CPU0_AVS_ROSC_THRESHOLD :: THRESH_HI [31:16] */
-#define BCHP_HIF_CPUBIUCTRL_CPU0_AVS_ROSC_THRESHOLD_THRESH_HI_MASK 0xffff0000
-#define BCHP_HIF_CPUBIUCTRL_CPU0_AVS_ROSC_THRESHOLD_THRESH_HI_SHIFT 16
-#define BCHP_HIF_CPUBIUCTRL_CPU0_AVS_ROSC_THRESHOLD_THRESH_HI_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: CPU0_AVS_ROSC_THRESHOLD :: THRESH_LO [15:00] */
-#define BCHP_HIF_CPUBIUCTRL_CPU0_AVS_ROSC_THRESHOLD_THRESH_LO_MASK 0x0000ffff
-#define BCHP_HIF_CPUBIUCTRL_CPU0_AVS_ROSC_THRESHOLD_THRESH_LO_SHIFT 0
-#define BCHP_HIF_CPUBIUCTRL_CPU0_AVS_ROSC_THRESHOLD_THRESH_LO_DEFAULT 0x00000000
-
-/***************************************************************************
- *CPU0_AVS_ROSC_COUNT - CPU0 Event Counter Count Register
- ***************************************************************************/
-/* HIF_CPUBIUCTRL :: CPU0_AVS_ROSC_COUNT :: COUNT_H [31:16] */
-#define BCHP_HIF_CPUBIUCTRL_CPU0_AVS_ROSC_COUNT_COUNT_H_MASK 0xffff0000
-#define BCHP_HIF_CPUBIUCTRL_CPU0_AVS_ROSC_COUNT_COUNT_H_SHIFT 16
-#define BCHP_HIF_CPUBIUCTRL_CPU0_AVS_ROSC_COUNT_COUNT_H_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: CPU0_AVS_ROSC_COUNT :: COUNT_S [15:00] */
-#define BCHP_HIF_CPUBIUCTRL_CPU0_AVS_ROSC_COUNT_COUNT_S_MASK 0x0000ffff
-#define BCHP_HIF_CPUBIUCTRL_CPU0_AVS_ROSC_COUNT_COUNT_S_SHIFT 0
-#define BCHP_HIF_CPUBIUCTRL_CPU0_AVS_ROSC_COUNT_COUNT_S_DEFAULT 0x00000000
-
-/***************************************************************************
- *CPU0_AVS_PWD_CONTROL - CPU0 PWD control Register
- ***************************************************************************/
-/* HIF_CPUBIUCTRL :: CPU0_AVS_PWD_CONTROL :: reserved0 [31:30] */
-#define BCHP_HIF_CPUBIUCTRL_CPU0_AVS_PWD_CONTROL_reserved0_MASK 0xc0000000
-#define BCHP_HIF_CPUBIUCTRL_CPU0_AVS_PWD_CONTROL_reserved0_SHIFT 30
-
-/* HIF_CPUBIUCTRL :: CPU0_AVS_PWD_CONTROL :: CLRCFG [29:27] */
-#define BCHP_HIF_CPUBIUCTRL_CPU0_AVS_PWD_CONTROL_CLRCFG_MASK 0x38000000
-#define BCHP_HIF_CPUBIUCTRL_CPU0_AVS_PWD_CONTROL_CLRCFG_SHIFT 27
-#define BCHP_HIF_CPUBIUCTRL_CPU0_AVS_PWD_CONTROL_CLRCFG_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: CPU0_AVS_PWD_CONTROL :: RSEL [26:24] */
-#define BCHP_HIF_CPUBIUCTRL_CPU0_AVS_PWD_CONTROL_RSEL_MASK 0x07000000
-#define BCHP_HIF_CPUBIUCTRL_CPU0_AVS_PWD_CONTROL_RSEL_SHIFT 24
-#define BCHP_HIF_CPUBIUCTRL_CPU0_AVS_PWD_CONTROL_RSEL_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: CPU0_AVS_PWD_CONTROL :: CGFG [23:16] */
-#define BCHP_HIF_CPUBIUCTRL_CPU0_AVS_PWD_CONTROL_CGFG_MASK 0x00ff0000
-#define BCHP_HIF_CPUBIUCTRL_CPU0_AVS_PWD_CONTROL_CGFG_SHIFT 16
-#define BCHP_HIF_CPUBIUCTRL_CPU0_AVS_PWD_CONTROL_CGFG_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: CPU0_AVS_PWD_CONTROL :: ALERT [15:15] */
-#define BCHP_HIF_CPUBIUCTRL_CPU0_AVS_PWD_CONTROL_ALERT_MASK 0x00008000
-#define BCHP_HIF_CPUBIUCTRL_CPU0_AVS_PWD_CONTROL_ALERT_SHIFT 15
-#define BCHP_HIF_CPUBIUCTRL_CPU0_AVS_PWD_CONTROL_ALERT_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: CPU0_AVS_PWD_CONTROL :: reserved1 [14:09] */
-#define BCHP_HIF_CPUBIUCTRL_CPU0_AVS_PWD_CONTROL_reserved1_MASK 0x00007e00
-#define BCHP_HIF_CPUBIUCTRL_CPU0_AVS_PWD_CONTROL_reserved1_SHIFT 9
-
-/* HIF_CPUBIUCTRL :: CPU0_AVS_PWD_CONTROL :: PWD_TM_EN [08:08] */
-#define BCHP_HIF_CPUBIUCTRL_CPU0_AVS_PWD_CONTROL_PWD_TM_EN_MASK 0x00000100
-#define BCHP_HIF_CPUBIUCTRL_CPU0_AVS_PWD_CONTROL_PWD_TM_EN_SHIFT 8
-#define BCHP_HIF_CPUBIUCTRL_CPU0_AVS_PWD_CONTROL_PWD_TM_EN_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: CPU0_AVS_PWD_CONTROL :: START [07:02] */
-#define BCHP_HIF_CPUBIUCTRL_CPU0_AVS_PWD_CONTROL_START_MASK 0x000000fc
-#define BCHP_HIF_CPUBIUCTRL_CPU0_AVS_PWD_CONTROL_START_SHIFT 2
-#define BCHP_HIF_CPUBIUCTRL_CPU0_AVS_PWD_CONTROL_START_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: CPU0_AVS_PWD_CONTROL :: PWD_ALERT_SEL [01:01] */
-#define BCHP_HIF_CPUBIUCTRL_CPU0_AVS_PWD_CONTROL_PWD_ALERT_SEL_MASK 0x00000002
-#define BCHP_HIF_CPUBIUCTRL_CPU0_AVS_PWD_CONTROL_PWD_ALERT_SEL_SHIFT 1
-#define BCHP_HIF_CPUBIUCTRL_CPU0_AVS_PWD_CONTROL_PWD_ALERT_SEL_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: CPU0_AVS_PWD_CONTROL :: PWD_EN [00:00] */
-#define BCHP_HIF_CPUBIUCTRL_CPU0_AVS_PWD_CONTROL_PWD_EN_MASK 0x00000001
-#define BCHP_HIF_CPUBIUCTRL_CPU0_AVS_PWD_CONTROL_PWD_EN_SHIFT 0
-#define BCHP_HIF_CPUBIUCTRL_CPU0_AVS_PWD_CONTROL_PWD_EN_DEFAULT 0x00000000
-
-/***************************************************************************
- *CPU1_BPCM_ID - CPU1 BPCM ID Register
- ***************************************************************************/
-/* HIF_CPUBIUCTRL :: CPU1_BPCM_ID :: SW_strap [31:16] */
-#define BCHP_HIF_CPUBIUCTRL_CPU1_BPCM_ID_SW_strap_MASK 0xffff0000
-#define BCHP_HIF_CPUBIUCTRL_CPU1_BPCM_ID_SW_strap_SHIFT 16
-
-/* HIF_CPUBIUCTRL :: CPU1_BPCM_ID :: HW_revision [15:08] */
-#define BCHP_HIF_CPUBIUCTRL_CPU1_BPCM_ID_HW_revision_MASK 0x0000ff00
-#define BCHP_HIF_CPUBIUCTRL_CPU1_BPCM_ID_HW_revision_SHIFT 8
-
-/* HIF_CPUBIUCTRL :: CPU1_BPCM_ID :: PMB_ADDR [07:00] */
-#define BCHP_HIF_CPUBIUCTRL_CPU1_BPCM_ID_PMB_ADDR_MASK 0x000000ff
-#define BCHP_HIF_CPUBIUCTRL_CPU1_BPCM_ID_PMB_ADDR_SHIFT 0
-
-/***************************************************************************
- *CPU1_BPCM_CAPABILITY - CPU1 BPCM Capability Register
- ***************************************************************************/
-/* HIF_CPUBIUCTRL :: CPU1_BPCM_CAPABILITY :: reserved0 [31:08] */
-#define BCHP_HIF_CPUBIUCTRL_CPU1_BPCM_CAPABILITY_reserved0_MASK 0xffffff00
-#define BCHP_HIF_CPUBIUCTRL_CPU1_BPCM_CAPABILITY_reserved0_SHIFT 8
-
-/* HIF_CPUBIUCTRL :: CPU1_BPCM_CAPABILITY :: Number_of_zones [07:00] */
-#define BCHP_HIF_CPUBIUCTRL_CPU1_BPCM_CAPABILITY_Number_of_zones_MASK 0x000000ff
-#define BCHP_HIF_CPUBIUCTRL_CPU1_BPCM_CAPABILITY_Number_of_zones_SHIFT 0
-
-/***************************************************************************
- *CPU1_BPCM_CONTROL - CPU1 BPCM Control Register
- ***************************************************************************/
-/* HIF_CPUBIUCTRL :: CPU1_BPCM_CONTROL :: TbdField [31:00] */
-#define BCHP_HIF_CPUBIUCTRL_CPU1_BPCM_CONTROL_TbdField_MASK 0xffffffff
-#define BCHP_HIF_CPUBIUCTRL_CPU1_BPCM_CONTROL_TbdField_SHIFT 0
-
-/***************************************************************************
- *CPU1_BPCM_STATUS - CPU1 BPCM Status Register
- ***************************************************************************/
-/* HIF_CPUBIUCTRL :: CPU1_BPCM_STATUS :: reserved0 [31:01] */
-#define BCHP_HIF_CPUBIUCTRL_CPU1_BPCM_STATUS_reserved0_MASK 0xfffffffe
-#define BCHP_HIF_CPUBIUCTRL_CPU1_BPCM_STATUS_reserved0_SHIFT 1
-
-/* HIF_CPUBIUCTRL :: CPU1_BPCM_STATUS :: PWD_Alert [00:00] */
-#define BCHP_HIF_CPUBIUCTRL_CPU1_BPCM_STATUS_PWD_Alert_MASK 0x00000001
-#define BCHP_HIF_CPUBIUCTRL_CPU1_BPCM_STATUS_PWD_Alert_SHIFT 0
-
-/***************************************************************************
- *CPU1_AVS_ROSC_CONTROL - CPU1 Ring Oscillator Control Register
- ***************************************************************************/
-/* HIF_CPUBIUCTRL :: CPU1_AVS_ROSC_CONTROL :: Test_interval [31:16] */
-#define BCHP_HIF_CPUBIUCTRL_CPU1_AVS_ROSC_CONTROL_Test_interval_MASK 0xffff0000
-#define BCHP_HIF_CPUBIUCTRL_CPU1_AVS_ROSC_CONTROL_Test_interval_SHIFT 16
-#define BCHP_HIF_CPUBIUCTRL_CPU1_AVS_ROSC_CONTROL_Test_interval_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: CPU1_AVS_ROSC_CONTROL :: ALERT_H [15:15] */
-#define BCHP_HIF_CPUBIUCTRL_CPU1_AVS_ROSC_CONTROL_ALERT_H_MASK 0x00008000
-#define BCHP_HIF_CPUBIUCTRL_CPU1_AVS_ROSC_CONTROL_ALERT_H_SHIFT 15
-#define BCHP_HIF_CPUBIUCTRL_CPU1_AVS_ROSC_CONTROL_ALERT_H_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: CPU1_AVS_ROSC_CONTROL :: VALID_H [14:14] */
-#define BCHP_HIF_CPUBIUCTRL_CPU1_AVS_ROSC_CONTROL_VALID_H_MASK 0x00004000
-#define BCHP_HIF_CPUBIUCTRL_CPU1_AVS_ROSC_CONTROL_VALID_H_SHIFT 14
-#define BCHP_HIF_CPUBIUCTRL_CPU1_AVS_ROSC_CONTROL_VALID_H_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: CPU1_AVS_ROSC_CONTROL :: ALERT_S [13:13] */
-#define BCHP_HIF_CPUBIUCTRL_CPU1_AVS_ROSC_CONTROL_ALERT_S_MASK 0x00002000
-#define BCHP_HIF_CPUBIUCTRL_CPU1_AVS_ROSC_CONTROL_ALERT_S_SHIFT 13
-#define BCHP_HIF_CPUBIUCTRL_CPU1_AVS_ROSC_CONTROL_ALERT_S_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: CPU1_AVS_ROSC_CONTROL :: VALID_S [12:12] */
-#define BCHP_HIF_CPUBIUCTRL_CPU1_AVS_ROSC_CONTROL_VALID_S_MASK 0x00001000
-#define BCHP_HIF_CPUBIUCTRL_CPU1_AVS_ROSC_CONTROL_VALID_S_SHIFT 12
-#define BCHP_HIF_CPUBIUCTRL_CPU1_AVS_ROSC_CONTROL_VALID_S_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: CPU1_AVS_ROSC_CONTROL :: reserved0 [11:08] */
-#define BCHP_HIF_CPUBIUCTRL_CPU1_AVS_ROSC_CONTROL_reserved0_MASK 0x00000f00
-#define BCHP_HIF_CPUBIUCTRL_CPU1_AVS_ROSC_CONTROL_reserved0_SHIFT 8
-
-/* HIF_CPUBIUCTRL :: CPU1_AVS_ROSC_CONTROL :: CONTINUOUS_H [07:07] */
-#define BCHP_HIF_CPUBIUCTRL_CPU1_AVS_ROSC_CONTROL_CONTINUOUS_H_MASK 0x00000080
-#define BCHP_HIF_CPUBIUCTRL_CPU1_AVS_ROSC_CONTROL_CONTINUOUS_H_SHIFT 7
-#define BCHP_HIF_CPUBIUCTRL_CPU1_AVS_ROSC_CONTROL_CONTINUOUS_H_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: CPU1_AVS_ROSC_CONTROL :: CONTINUOUS_S [06:06] */
-#define BCHP_HIF_CPUBIUCTRL_CPU1_AVS_ROSC_CONTROL_CONTINUOUS_S_MASK 0x00000040
-#define BCHP_HIF_CPUBIUCTRL_CPU1_AVS_ROSC_CONTROL_CONTINUOUS_S_SHIFT 6
-#define BCHP_HIF_CPUBIUCTRL_CPU1_AVS_ROSC_CONTROL_CONTINUOUS_S_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: CPU1_AVS_ROSC_CONTROL :: THRSH_EN_H [05:05] */
-#define BCHP_HIF_CPUBIUCTRL_CPU1_AVS_ROSC_CONTROL_THRSH_EN_H_MASK 0x00000020
-#define BCHP_HIF_CPUBIUCTRL_CPU1_AVS_ROSC_CONTROL_THRSH_EN_H_SHIFT 5
-#define BCHP_HIF_CPUBIUCTRL_CPU1_AVS_ROSC_CONTROL_THRSH_EN_H_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: CPU1_AVS_ROSC_CONTROL :: THRSH_EN_S [04:04] */
-#define BCHP_HIF_CPUBIUCTRL_CPU1_AVS_ROSC_CONTROL_THRSH_EN_S_MASK 0x00000010
-#define BCHP_HIF_CPUBIUCTRL_CPU1_AVS_ROSC_CONTROL_THRSH_EN_S_SHIFT 4
-#define BCHP_HIF_CPUBIUCTRL_CPU1_AVS_ROSC_CONTROL_THRSH_EN_S_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: CPU1_AVS_ROSC_CONTROL :: ECTR_EN_H [03:03] */
-#define BCHP_HIF_CPUBIUCTRL_CPU1_AVS_ROSC_CONTROL_ECTR_EN_H_MASK 0x00000008
-#define BCHP_HIF_CPUBIUCTRL_CPU1_AVS_ROSC_CONTROL_ECTR_EN_H_SHIFT 3
-#define BCHP_HIF_CPUBIUCTRL_CPU1_AVS_ROSC_CONTROL_ECTR_EN_H_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: CPU1_AVS_ROSC_CONTROL :: ECTR_EN_S [02:02] */
-#define BCHP_HIF_CPUBIUCTRL_CPU1_AVS_ROSC_CONTROL_ECTR_EN_S_MASK 0x00000004
-#define BCHP_HIF_CPUBIUCTRL_CPU1_AVS_ROSC_CONTROL_ECTR_EN_S_SHIFT 2
-#define BCHP_HIF_CPUBIUCTRL_CPU1_AVS_ROSC_CONTROL_ECTR_EN_S_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: CPU1_AVS_ROSC_CONTROL :: RO_EN_H [01:01] */
-#define BCHP_HIF_CPUBIUCTRL_CPU1_AVS_ROSC_CONTROL_RO_EN_H_MASK 0x00000002
-#define BCHP_HIF_CPUBIUCTRL_CPU1_AVS_ROSC_CONTROL_RO_EN_H_SHIFT 1
-#define BCHP_HIF_CPUBIUCTRL_CPU1_AVS_ROSC_CONTROL_RO_EN_H_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: CPU1_AVS_ROSC_CONTROL :: RO_EN_S [00:00] */
-#define BCHP_HIF_CPUBIUCTRL_CPU1_AVS_ROSC_CONTROL_RO_EN_S_MASK 0x00000001
-#define BCHP_HIF_CPUBIUCTRL_CPU1_AVS_ROSC_CONTROL_RO_EN_S_SHIFT 0
-#define BCHP_HIF_CPUBIUCTRL_CPU1_AVS_ROSC_CONTROL_RO_EN_S_DEFAULT 0x00000000
-
-/***************************************************************************
- *CPU1_AVS_ROSC_THRESHOLD - CPU1 Event Counter Threshold Register
- ***************************************************************************/
-/* HIF_CPUBIUCTRL :: CPU1_AVS_ROSC_THRESHOLD :: THRESH_HI [31:16] */
-#define BCHP_HIF_CPUBIUCTRL_CPU1_AVS_ROSC_THRESHOLD_THRESH_HI_MASK 0xffff0000
-#define BCHP_HIF_CPUBIUCTRL_CPU1_AVS_ROSC_THRESHOLD_THRESH_HI_SHIFT 16
-#define BCHP_HIF_CPUBIUCTRL_CPU1_AVS_ROSC_THRESHOLD_THRESH_HI_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: CPU1_AVS_ROSC_THRESHOLD :: THRESH_LO [15:00] */
-#define BCHP_HIF_CPUBIUCTRL_CPU1_AVS_ROSC_THRESHOLD_THRESH_LO_MASK 0x0000ffff
-#define BCHP_HIF_CPUBIUCTRL_CPU1_AVS_ROSC_THRESHOLD_THRESH_LO_SHIFT 0
-#define BCHP_HIF_CPUBIUCTRL_CPU1_AVS_ROSC_THRESHOLD_THRESH_LO_DEFAULT 0x00000000
-
-/***************************************************************************
- *CPU1_AVS_ROSC_COUNT - CPU1 Event Counter Count Register
- ***************************************************************************/
-/* HIF_CPUBIUCTRL :: CPU1_AVS_ROSC_COUNT :: COUNT_H [31:16] */
-#define BCHP_HIF_CPUBIUCTRL_CPU1_AVS_ROSC_COUNT_COUNT_H_MASK 0xffff0000
-#define BCHP_HIF_CPUBIUCTRL_CPU1_AVS_ROSC_COUNT_COUNT_H_SHIFT 16
-#define BCHP_HIF_CPUBIUCTRL_CPU1_AVS_ROSC_COUNT_COUNT_H_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: CPU1_AVS_ROSC_COUNT :: COUNT_S [15:00] */
-#define BCHP_HIF_CPUBIUCTRL_CPU1_AVS_ROSC_COUNT_COUNT_S_MASK 0x0000ffff
-#define BCHP_HIF_CPUBIUCTRL_CPU1_AVS_ROSC_COUNT_COUNT_S_SHIFT 0
-#define BCHP_HIF_CPUBIUCTRL_CPU1_AVS_ROSC_COUNT_COUNT_S_DEFAULT 0x00000000
-
-/***************************************************************************
- *CPU1_AVS_PWD_CONTROL - CPU1 PWD control Register
- ***************************************************************************/
-/* HIF_CPUBIUCTRL :: CPU1_AVS_PWD_CONTROL :: reserved0 [31:30] */
-#define BCHP_HIF_CPUBIUCTRL_CPU1_AVS_PWD_CONTROL_reserved0_MASK 0xc0000000
-#define BCHP_HIF_CPUBIUCTRL_CPU1_AVS_PWD_CONTROL_reserved0_SHIFT 30
-
-/* HIF_CPUBIUCTRL :: CPU1_AVS_PWD_CONTROL :: CLRCFG [29:27] */
-#define BCHP_HIF_CPUBIUCTRL_CPU1_AVS_PWD_CONTROL_CLRCFG_MASK 0x38000000
-#define BCHP_HIF_CPUBIUCTRL_CPU1_AVS_PWD_CONTROL_CLRCFG_SHIFT 27
-#define BCHP_HIF_CPUBIUCTRL_CPU1_AVS_PWD_CONTROL_CLRCFG_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: CPU1_AVS_PWD_CONTROL :: RSEL [26:24] */
-#define BCHP_HIF_CPUBIUCTRL_CPU1_AVS_PWD_CONTROL_RSEL_MASK 0x07000000
-#define BCHP_HIF_CPUBIUCTRL_CPU1_AVS_PWD_CONTROL_RSEL_SHIFT 24
-#define BCHP_HIF_CPUBIUCTRL_CPU1_AVS_PWD_CONTROL_RSEL_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: CPU1_AVS_PWD_CONTROL :: CGFG [23:16] */
-#define BCHP_HIF_CPUBIUCTRL_CPU1_AVS_PWD_CONTROL_CGFG_MASK 0x00ff0000
-#define BCHP_HIF_CPUBIUCTRL_CPU1_AVS_PWD_CONTROL_CGFG_SHIFT 16
-#define BCHP_HIF_CPUBIUCTRL_CPU1_AVS_PWD_CONTROL_CGFG_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: CPU1_AVS_PWD_CONTROL :: ALERT [15:15] */
-#define BCHP_HIF_CPUBIUCTRL_CPU1_AVS_PWD_CONTROL_ALERT_MASK 0x00008000
-#define BCHP_HIF_CPUBIUCTRL_CPU1_AVS_PWD_CONTROL_ALERT_SHIFT 15
-#define BCHP_HIF_CPUBIUCTRL_CPU1_AVS_PWD_CONTROL_ALERT_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: CPU1_AVS_PWD_CONTROL :: reserved1 [14:09] */
-#define BCHP_HIF_CPUBIUCTRL_CPU1_AVS_PWD_CONTROL_reserved1_MASK 0x00007e00
-#define BCHP_HIF_CPUBIUCTRL_CPU1_AVS_PWD_CONTROL_reserved1_SHIFT 9
-
-/* HIF_CPUBIUCTRL :: CPU1_AVS_PWD_CONTROL :: PWD_TM_EN [08:08] */
-#define BCHP_HIF_CPUBIUCTRL_CPU1_AVS_PWD_CONTROL_PWD_TM_EN_MASK 0x00000100
-#define BCHP_HIF_CPUBIUCTRL_CPU1_AVS_PWD_CONTROL_PWD_TM_EN_SHIFT 8
-#define BCHP_HIF_CPUBIUCTRL_CPU1_AVS_PWD_CONTROL_PWD_TM_EN_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: CPU1_AVS_PWD_CONTROL :: START [07:02] */
-#define BCHP_HIF_CPUBIUCTRL_CPU1_AVS_PWD_CONTROL_START_MASK 0x000000fc
-#define BCHP_HIF_CPUBIUCTRL_CPU1_AVS_PWD_CONTROL_START_SHIFT 2
-#define BCHP_HIF_CPUBIUCTRL_CPU1_AVS_PWD_CONTROL_START_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: CPU1_AVS_PWD_CONTROL :: PWD_ALERT_SEL [01:01] */
-#define BCHP_HIF_CPUBIUCTRL_CPU1_AVS_PWD_CONTROL_PWD_ALERT_SEL_MASK 0x00000002
-#define BCHP_HIF_CPUBIUCTRL_CPU1_AVS_PWD_CONTROL_PWD_ALERT_SEL_SHIFT 1
-#define BCHP_HIF_CPUBIUCTRL_CPU1_AVS_PWD_CONTROL_PWD_ALERT_SEL_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: CPU1_AVS_PWD_CONTROL :: PWD_EN [00:00] */
-#define BCHP_HIF_CPUBIUCTRL_CPU1_AVS_PWD_CONTROL_PWD_EN_MASK 0x00000001
-#define BCHP_HIF_CPUBIUCTRL_CPU1_AVS_PWD_CONTROL_PWD_EN_SHIFT 0
-#define BCHP_HIF_CPUBIUCTRL_CPU1_AVS_PWD_CONTROL_PWD_EN_DEFAULT 0x00000000
-
-/***************************************************************************
- *CPU2_BPCM_ID - CPU2 BPCM ID Register
- ***************************************************************************/
-/* HIF_CPUBIUCTRL :: CPU2_BPCM_ID :: SW_strap [31:16] */
-#define BCHP_HIF_CPUBIUCTRL_CPU2_BPCM_ID_SW_strap_MASK 0xffff0000
-#define BCHP_HIF_CPUBIUCTRL_CPU2_BPCM_ID_SW_strap_SHIFT 16
-
-/* HIF_CPUBIUCTRL :: CPU2_BPCM_ID :: HW_revision [15:08] */
-#define BCHP_HIF_CPUBIUCTRL_CPU2_BPCM_ID_HW_revision_MASK 0x0000ff00
-#define BCHP_HIF_CPUBIUCTRL_CPU2_BPCM_ID_HW_revision_SHIFT 8
-
-/* HIF_CPUBIUCTRL :: CPU2_BPCM_ID :: PMB_ADDR [07:00] */
-#define BCHP_HIF_CPUBIUCTRL_CPU2_BPCM_ID_PMB_ADDR_MASK 0x000000ff
-#define BCHP_HIF_CPUBIUCTRL_CPU2_BPCM_ID_PMB_ADDR_SHIFT 0
-
-/***************************************************************************
- *CPU2_BPCM_CAPABILITY - CPU2 BPCM Capability Register
- ***************************************************************************/
-/* HIF_CPUBIUCTRL :: CPU2_BPCM_CAPABILITY :: reserved0 [31:08] */
-#define BCHP_HIF_CPUBIUCTRL_CPU2_BPCM_CAPABILITY_reserved0_MASK 0xffffff00
-#define BCHP_HIF_CPUBIUCTRL_CPU2_BPCM_CAPABILITY_reserved0_SHIFT 8
-
-/* HIF_CPUBIUCTRL :: CPU2_BPCM_CAPABILITY :: Number_of_zones [07:00] */
-#define BCHP_HIF_CPUBIUCTRL_CPU2_BPCM_CAPABILITY_Number_of_zones_MASK 0x000000ff
-#define BCHP_HIF_CPUBIUCTRL_CPU2_BPCM_CAPABILITY_Number_of_zones_SHIFT 0
-
-/***************************************************************************
- *CPU2_BPCM_CONTROL - CPU2 BPCM Control Register
- ***************************************************************************/
-/* HIF_CPUBIUCTRL :: CPU2_BPCM_CONTROL :: TbdField [31:00] */
-#define BCHP_HIF_CPUBIUCTRL_CPU2_BPCM_CONTROL_TbdField_MASK 0xffffffff
-#define BCHP_HIF_CPUBIUCTRL_CPU2_BPCM_CONTROL_TbdField_SHIFT 0
-
-/***************************************************************************
- *CPU2_BPCM_STATUS - CPU2 BPCM Status Register
- ***************************************************************************/
-/* HIF_CPUBIUCTRL :: CPU2_BPCM_STATUS :: reserved0 [31:01] */
-#define BCHP_HIF_CPUBIUCTRL_CPU2_BPCM_STATUS_reserved0_MASK 0xfffffffe
-#define BCHP_HIF_CPUBIUCTRL_CPU2_BPCM_STATUS_reserved0_SHIFT 1
-
-/* HIF_CPUBIUCTRL :: CPU2_BPCM_STATUS :: PWD_Alert [00:00] */
-#define BCHP_HIF_CPUBIUCTRL_CPU2_BPCM_STATUS_PWD_Alert_MASK 0x00000001
-#define BCHP_HIF_CPUBIUCTRL_CPU2_BPCM_STATUS_PWD_Alert_SHIFT 0
-
-/***************************************************************************
- *CPU2_AVS_ROSC_CONTROL - CPU2 Ring Oscillator Control Register
- ***************************************************************************/
-/* HIF_CPUBIUCTRL :: CPU2_AVS_ROSC_CONTROL :: Test_interval [31:16] */
-#define BCHP_HIF_CPUBIUCTRL_CPU2_AVS_ROSC_CONTROL_Test_interval_MASK 0xffff0000
-#define BCHP_HIF_CPUBIUCTRL_CPU2_AVS_ROSC_CONTROL_Test_interval_SHIFT 16
-#define BCHP_HIF_CPUBIUCTRL_CPU2_AVS_ROSC_CONTROL_Test_interval_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: CPU2_AVS_ROSC_CONTROL :: ALERT_H [15:15] */
-#define BCHP_HIF_CPUBIUCTRL_CPU2_AVS_ROSC_CONTROL_ALERT_H_MASK 0x00008000
-#define BCHP_HIF_CPUBIUCTRL_CPU2_AVS_ROSC_CONTROL_ALERT_H_SHIFT 15
-#define BCHP_HIF_CPUBIUCTRL_CPU2_AVS_ROSC_CONTROL_ALERT_H_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: CPU2_AVS_ROSC_CONTROL :: VALID_H [14:14] */
-#define BCHP_HIF_CPUBIUCTRL_CPU2_AVS_ROSC_CONTROL_VALID_H_MASK 0x00004000
-#define BCHP_HIF_CPUBIUCTRL_CPU2_AVS_ROSC_CONTROL_VALID_H_SHIFT 14
-#define BCHP_HIF_CPUBIUCTRL_CPU2_AVS_ROSC_CONTROL_VALID_H_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: CPU2_AVS_ROSC_CONTROL :: ALERT_S [13:13] */
-#define BCHP_HIF_CPUBIUCTRL_CPU2_AVS_ROSC_CONTROL_ALERT_S_MASK 0x00002000
-#define BCHP_HIF_CPUBIUCTRL_CPU2_AVS_ROSC_CONTROL_ALERT_S_SHIFT 13
-#define BCHP_HIF_CPUBIUCTRL_CPU2_AVS_ROSC_CONTROL_ALERT_S_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: CPU2_AVS_ROSC_CONTROL :: VALID_S [12:12] */
-#define BCHP_HIF_CPUBIUCTRL_CPU2_AVS_ROSC_CONTROL_VALID_S_MASK 0x00001000
-#define BCHP_HIF_CPUBIUCTRL_CPU2_AVS_ROSC_CONTROL_VALID_S_SHIFT 12
-#define BCHP_HIF_CPUBIUCTRL_CPU2_AVS_ROSC_CONTROL_VALID_S_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: CPU2_AVS_ROSC_CONTROL :: reserved0 [11:08] */
-#define BCHP_HIF_CPUBIUCTRL_CPU2_AVS_ROSC_CONTROL_reserved0_MASK 0x00000f00
-#define BCHP_HIF_CPUBIUCTRL_CPU2_AVS_ROSC_CONTROL_reserved0_SHIFT 8
-
-/* HIF_CPUBIUCTRL :: CPU2_AVS_ROSC_CONTROL :: CONTINUOUS_H [07:07] */
-#define BCHP_HIF_CPUBIUCTRL_CPU2_AVS_ROSC_CONTROL_CONTINUOUS_H_MASK 0x00000080
-#define BCHP_HIF_CPUBIUCTRL_CPU2_AVS_ROSC_CONTROL_CONTINUOUS_H_SHIFT 7
-#define BCHP_HIF_CPUBIUCTRL_CPU2_AVS_ROSC_CONTROL_CONTINUOUS_H_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: CPU2_AVS_ROSC_CONTROL :: CONTINUOUS_S [06:06] */
-#define BCHP_HIF_CPUBIUCTRL_CPU2_AVS_ROSC_CONTROL_CONTINUOUS_S_MASK 0x00000040
-#define BCHP_HIF_CPUBIUCTRL_CPU2_AVS_ROSC_CONTROL_CONTINUOUS_S_SHIFT 6
-#define BCHP_HIF_CPUBIUCTRL_CPU2_AVS_ROSC_CONTROL_CONTINUOUS_S_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: CPU2_AVS_ROSC_CONTROL :: THRSH_EN_H [05:05] */
-#define BCHP_HIF_CPUBIUCTRL_CPU2_AVS_ROSC_CONTROL_THRSH_EN_H_MASK 0x00000020
-#define BCHP_HIF_CPUBIUCTRL_CPU2_AVS_ROSC_CONTROL_THRSH_EN_H_SHIFT 5
-#define BCHP_HIF_CPUBIUCTRL_CPU2_AVS_ROSC_CONTROL_THRSH_EN_H_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: CPU2_AVS_ROSC_CONTROL :: THRSH_EN_S [04:04] */
-#define BCHP_HIF_CPUBIUCTRL_CPU2_AVS_ROSC_CONTROL_THRSH_EN_S_MASK 0x00000010
-#define BCHP_HIF_CPUBIUCTRL_CPU2_AVS_ROSC_CONTROL_THRSH_EN_S_SHIFT 4
-#define BCHP_HIF_CPUBIUCTRL_CPU2_AVS_ROSC_CONTROL_THRSH_EN_S_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: CPU2_AVS_ROSC_CONTROL :: ECTR_EN_H [03:03] */
-#define BCHP_HIF_CPUBIUCTRL_CPU2_AVS_ROSC_CONTROL_ECTR_EN_H_MASK 0x00000008
-#define BCHP_HIF_CPUBIUCTRL_CPU2_AVS_ROSC_CONTROL_ECTR_EN_H_SHIFT 3
-#define BCHP_HIF_CPUBIUCTRL_CPU2_AVS_ROSC_CONTROL_ECTR_EN_H_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: CPU2_AVS_ROSC_CONTROL :: ECTR_EN_S [02:02] */
-#define BCHP_HIF_CPUBIUCTRL_CPU2_AVS_ROSC_CONTROL_ECTR_EN_S_MASK 0x00000004
-#define BCHP_HIF_CPUBIUCTRL_CPU2_AVS_ROSC_CONTROL_ECTR_EN_S_SHIFT 2
-#define BCHP_HIF_CPUBIUCTRL_CPU2_AVS_ROSC_CONTROL_ECTR_EN_S_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: CPU2_AVS_ROSC_CONTROL :: RO_EN_H [01:01] */
-#define BCHP_HIF_CPUBIUCTRL_CPU2_AVS_ROSC_CONTROL_RO_EN_H_MASK 0x00000002
-#define BCHP_HIF_CPUBIUCTRL_CPU2_AVS_ROSC_CONTROL_RO_EN_H_SHIFT 1
-#define BCHP_HIF_CPUBIUCTRL_CPU2_AVS_ROSC_CONTROL_RO_EN_H_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: CPU2_AVS_ROSC_CONTROL :: RO_EN_S [00:00] */
-#define BCHP_HIF_CPUBIUCTRL_CPU2_AVS_ROSC_CONTROL_RO_EN_S_MASK 0x00000001
-#define BCHP_HIF_CPUBIUCTRL_CPU2_AVS_ROSC_CONTROL_RO_EN_S_SHIFT 0
-#define BCHP_HIF_CPUBIUCTRL_CPU2_AVS_ROSC_CONTROL_RO_EN_S_DEFAULT 0x00000000
-
-/***************************************************************************
- *CPU2_AVS_ROSC_THRESHOLD - CPU2 Event Counter Threshold Register
- ***************************************************************************/
-/* HIF_CPUBIUCTRL :: CPU2_AVS_ROSC_THRESHOLD :: THRESH_HI [31:16] */
-#define BCHP_HIF_CPUBIUCTRL_CPU2_AVS_ROSC_THRESHOLD_THRESH_HI_MASK 0xffff0000
-#define BCHP_HIF_CPUBIUCTRL_CPU2_AVS_ROSC_THRESHOLD_THRESH_HI_SHIFT 16
-#define BCHP_HIF_CPUBIUCTRL_CPU2_AVS_ROSC_THRESHOLD_THRESH_HI_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: CPU2_AVS_ROSC_THRESHOLD :: THRESH_LO [15:00] */
-#define BCHP_HIF_CPUBIUCTRL_CPU2_AVS_ROSC_THRESHOLD_THRESH_LO_MASK 0x0000ffff
-#define BCHP_HIF_CPUBIUCTRL_CPU2_AVS_ROSC_THRESHOLD_THRESH_LO_SHIFT 0
-#define BCHP_HIF_CPUBIUCTRL_CPU2_AVS_ROSC_THRESHOLD_THRESH_LO_DEFAULT 0x00000000
-
-/***************************************************************************
- *CPU2_AVS_ROSC_COUNT - CPU2 Event Counter Count Register
- ***************************************************************************/
-/* HIF_CPUBIUCTRL :: CPU2_AVS_ROSC_COUNT :: COUNT_H [31:16] */
-#define BCHP_HIF_CPUBIUCTRL_CPU2_AVS_ROSC_COUNT_COUNT_H_MASK 0xffff0000
-#define BCHP_HIF_CPUBIUCTRL_CPU2_AVS_ROSC_COUNT_COUNT_H_SHIFT 16
-#define BCHP_HIF_CPUBIUCTRL_CPU2_AVS_ROSC_COUNT_COUNT_H_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: CPU2_AVS_ROSC_COUNT :: COUNT_S [15:00] */
-#define BCHP_HIF_CPUBIUCTRL_CPU2_AVS_ROSC_COUNT_COUNT_S_MASK 0x0000ffff
-#define BCHP_HIF_CPUBIUCTRL_CPU2_AVS_ROSC_COUNT_COUNT_S_SHIFT 0
-#define BCHP_HIF_CPUBIUCTRL_CPU2_AVS_ROSC_COUNT_COUNT_S_DEFAULT 0x00000000
-
-/***************************************************************************
- *CPU2_AVS_PWD_CONTROL - CPU2 PWD control Register
- ***************************************************************************/
-/* HIF_CPUBIUCTRL :: CPU2_AVS_PWD_CONTROL :: reserved0 [31:30] */
-#define BCHP_HIF_CPUBIUCTRL_CPU2_AVS_PWD_CONTROL_reserved0_MASK 0xc0000000
-#define BCHP_HIF_CPUBIUCTRL_CPU2_AVS_PWD_CONTROL_reserved0_SHIFT 30
-
-/* HIF_CPUBIUCTRL :: CPU2_AVS_PWD_CONTROL :: CLRCFG [29:27] */
-#define BCHP_HIF_CPUBIUCTRL_CPU2_AVS_PWD_CONTROL_CLRCFG_MASK 0x38000000
-#define BCHP_HIF_CPUBIUCTRL_CPU2_AVS_PWD_CONTROL_CLRCFG_SHIFT 27
-#define BCHP_HIF_CPUBIUCTRL_CPU2_AVS_PWD_CONTROL_CLRCFG_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: CPU2_AVS_PWD_CONTROL :: RSEL [26:24] */
-#define BCHP_HIF_CPUBIUCTRL_CPU2_AVS_PWD_CONTROL_RSEL_MASK 0x07000000
-#define BCHP_HIF_CPUBIUCTRL_CPU2_AVS_PWD_CONTROL_RSEL_SHIFT 24
-#define BCHP_HIF_CPUBIUCTRL_CPU2_AVS_PWD_CONTROL_RSEL_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: CPU2_AVS_PWD_CONTROL :: CGFG [23:16] */
-#define BCHP_HIF_CPUBIUCTRL_CPU2_AVS_PWD_CONTROL_CGFG_MASK 0x00ff0000
-#define BCHP_HIF_CPUBIUCTRL_CPU2_AVS_PWD_CONTROL_CGFG_SHIFT 16
-#define BCHP_HIF_CPUBIUCTRL_CPU2_AVS_PWD_CONTROL_CGFG_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: CPU2_AVS_PWD_CONTROL :: ALERT [15:15] */
-#define BCHP_HIF_CPUBIUCTRL_CPU2_AVS_PWD_CONTROL_ALERT_MASK 0x00008000
-#define BCHP_HIF_CPUBIUCTRL_CPU2_AVS_PWD_CONTROL_ALERT_SHIFT 15
-#define BCHP_HIF_CPUBIUCTRL_CPU2_AVS_PWD_CONTROL_ALERT_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: CPU2_AVS_PWD_CONTROL :: reserved1 [14:09] */
-#define BCHP_HIF_CPUBIUCTRL_CPU2_AVS_PWD_CONTROL_reserved1_MASK 0x00007e00
-#define BCHP_HIF_CPUBIUCTRL_CPU2_AVS_PWD_CONTROL_reserved1_SHIFT 9
-
-/* HIF_CPUBIUCTRL :: CPU2_AVS_PWD_CONTROL :: PWD_TM_EN [08:08] */
-#define BCHP_HIF_CPUBIUCTRL_CPU2_AVS_PWD_CONTROL_PWD_TM_EN_MASK 0x00000100
-#define BCHP_HIF_CPUBIUCTRL_CPU2_AVS_PWD_CONTROL_PWD_TM_EN_SHIFT 8
-#define BCHP_HIF_CPUBIUCTRL_CPU2_AVS_PWD_CONTROL_PWD_TM_EN_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: CPU2_AVS_PWD_CONTROL :: START [07:02] */
-#define BCHP_HIF_CPUBIUCTRL_CPU2_AVS_PWD_CONTROL_START_MASK 0x000000fc
-#define BCHP_HIF_CPUBIUCTRL_CPU2_AVS_PWD_CONTROL_START_SHIFT 2
-#define BCHP_HIF_CPUBIUCTRL_CPU2_AVS_PWD_CONTROL_START_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: CPU2_AVS_PWD_CONTROL :: PWD_ALERT_SEL [01:01] */
-#define BCHP_HIF_CPUBIUCTRL_CPU2_AVS_PWD_CONTROL_PWD_ALERT_SEL_MASK 0x00000002
-#define BCHP_HIF_CPUBIUCTRL_CPU2_AVS_PWD_CONTROL_PWD_ALERT_SEL_SHIFT 1
-#define BCHP_HIF_CPUBIUCTRL_CPU2_AVS_PWD_CONTROL_PWD_ALERT_SEL_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: CPU2_AVS_PWD_CONTROL :: PWD_EN [00:00] */
-#define BCHP_HIF_CPUBIUCTRL_CPU2_AVS_PWD_CONTROL_PWD_EN_MASK 0x00000001
-#define BCHP_HIF_CPUBIUCTRL_CPU2_AVS_PWD_CONTROL_PWD_EN_SHIFT 0
-#define BCHP_HIF_CPUBIUCTRL_CPU2_AVS_PWD_CONTROL_PWD_EN_DEFAULT 0x00000000
-
-/***************************************************************************
- *CPU3_BPCM_ID - CPU3 BPCM ID Register
- ***************************************************************************/
-/* HIF_CPUBIUCTRL :: CPU3_BPCM_ID :: SW_strap [31:16] */
-#define BCHP_HIF_CPUBIUCTRL_CPU3_BPCM_ID_SW_strap_MASK 0xffff0000
-#define BCHP_HIF_CPUBIUCTRL_CPU3_BPCM_ID_SW_strap_SHIFT 16
-
-/* HIF_CPUBIUCTRL :: CPU3_BPCM_ID :: HW_revision [15:08] */
-#define BCHP_HIF_CPUBIUCTRL_CPU3_BPCM_ID_HW_revision_MASK 0x0000ff00
-#define BCHP_HIF_CPUBIUCTRL_CPU3_BPCM_ID_HW_revision_SHIFT 8
-
-/* HIF_CPUBIUCTRL :: CPU3_BPCM_ID :: PMB_ADDR [07:00] */
-#define BCHP_HIF_CPUBIUCTRL_CPU3_BPCM_ID_PMB_ADDR_MASK 0x000000ff
-#define BCHP_HIF_CPUBIUCTRL_CPU3_BPCM_ID_PMB_ADDR_SHIFT 0
-
-/***************************************************************************
- *CPU3_BPCM_CAPABILITY - CPU3 BPCM Capability Register
- ***************************************************************************/
-/* HIF_CPUBIUCTRL :: CPU3_BPCM_CAPABILITY :: reserved0 [31:08] */
-#define BCHP_HIF_CPUBIUCTRL_CPU3_BPCM_CAPABILITY_reserved0_MASK 0xffffff00
-#define BCHP_HIF_CPUBIUCTRL_CPU3_BPCM_CAPABILITY_reserved0_SHIFT 8
-
-/* HIF_CPUBIUCTRL :: CPU3_BPCM_CAPABILITY :: Number_of_zones [07:00] */
-#define BCHP_HIF_CPUBIUCTRL_CPU3_BPCM_CAPABILITY_Number_of_zones_MASK 0x000000ff
-#define BCHP_HIF_CPUBIUCTRL_CPU3_BPCM_CAPABILITY_Number_of_zones_SHIFT 0
-
-/***************************************************************************
- *CPU3_BPCM_CONTROL - CPU3 BPCM Control Register
- ***************************************************************************/
-/* HIF_CPUBIUCTRL :: CPU3_BPCM_CONTROL :: TbdField [31:00] */
-#define BCHP_HIF_CPUBIUCTRL_CPU3_BPCM_CONTROL_TbdField_MASK 0xffffffff
-#define BCHP_HIF_CPUBIUCTRL_CPU3_BPCM_CONTROL_TbdField_SHIFT 0
-
-/***************************************************************************
- *CPU3_BPCM_STATUS - CPU3 BPCM Status Register
- ***************************************************************************/
-/* HIF_CPUBIUCTRL :: CPU3_BPCM_STATUS :: reserved0 [31:01] */
-#define BCHP_HIF_CPUBIUCTRL_CPU3_BPCM_STATUS_reserved0_MASK 0xfffffffe
-#define BCHP_HIF_CPUBIUCTRL_CPU3_BPCM_STATUS_reserved0_SHIFT 1
-
-/* HIF_CPUBIUCTRL :: CPU3_BPCM_STATUS :: PWD_Alert [00:00] */
-#define BCHP_HIF_CPUBIUCTRL_CPU3_BPCM_STATUS_PWD_Alert_MASK 0x00000001
-#define BCHP_HIF_CPUBIUCTRL_CPU3_BPCM_STATUS_PWD_Alert_SHIFT 0
-
-/***************************************************************************
- *CPU3_AVS_ROSC_CONTROL - CPU3 Ring Oscillator Control Register
- ***************************************************************************/
-/* HIF_CPUBIUCTRL :: CPU3_AVS_ROSC_CONTROL :: Test_interval [31:16] */
-#define BCHP_HIF_CPUBIUCTRL_CPU3_AVS_ROSC_CONTROL_Test_interval_MASK 0xffff0000
-#define BCHP_HIF_CPUBIUCTRL_CPU3_AVS_ROSC_CONTROL_Test_interval_SHIFT 16
-#define BCHP_HIF_CPUBIUCTRL_CPU3_AVS_ROSC_CONTROL_Test_interval_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: CPU3_AVS_ROSC_CONTROL :: ALERT_H [15:15] */
-#define BCHP_HIF_CPUBIUCTRL_CPU3_AVS_ROSC_CONTROL_ALERT_H_MASK 0x00008000
-#define BCHP_HIF_CPUBIUCTRL_CPU3_AVS_ROSC_CONTROL_ALERT_H_SHIFT 15
-#define BCHP_HIF_CPUBIUCTRL_CPU3_AVS_ROSC_CONTROL_ALERT_H_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: CPU3_AVS_ROSC_CONTROL :: VALID_H [14:14] */
-#define BCHP_HIF_CPUBIUCTRL_CPU3_AVS_ROSC_CONTROL_VALID_H_MASK 0x00004000
-#define BCHP_HIF_CPUBIUCTRL_CPU3_AVS_ROSC_CONTROL_VALID_H_SHIFT 14
-#define BCHP_HIF_CPUBIUCTRL_CPU3_AVS_ROSC_CONTROL_VALID_H_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: CPU3_AVS_ROSC_CONTROL :: ALERT_S [13:13] */
-#define BCHP_HIF_CPUBIUCTRL_CPU3_AVS_ROSC_CONTROL_ALERT_S_MASK 0x00002000
-#define BCHP_HIF_CPUBIUCTRL_CPU3_AVS_ROSC_CONTROL_ALERT_S_SHIFT 13
-#define BCHP_HIF_CPUBIUCTRL_CPU3_AVS_ROSC_CONTROL_ALERT_S_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: CPU3_AVS_ROSC_CONTROL :: VALID_S [12:12] */
-#define BCHP_HIF_CPUBIUCTRL_CPU3_AVS_ROSC_CONTROL_VALID_S_MASK 0x00001000
-#define BCHP_HIF_CPUBIUCTRL_CPU3_AVS_ROSC_CONTROL_VALID_S_SHIFT 12
-#define BCHP_HIF_CPUBIUCTRL_CPU3_AVS_ROSC_CONTROL_VALID_S_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: CPU3_AVS_ROSC_CONTROL :: reserved0 [11:08] */
-#define BCHP_HIF_CPUBIUCTRL_CPU3_AVS_ROSC_CONTROL_reserved0_MASK 0x00000f00
-#define BCHP_HIF_CPUBIUCTRL_CPU3_AVS_ROSC_CONTROL_reserved0_SHIFT 8
-
-/* HIF_CPUBIUCTRL :: CPU3_AVS_ROSC_CONTROL :: CONTINUOUS_H [07:07] */
-#define BCHP_HIF_CPUBIUCTRL_CPU3_AVS_ROSC_CONTROL_CONTINUOUS_H_MASK 0x00000080
-#define BCHP_HIF_CPUBIUCTRL_CPU3_AVS_ROSC_CONTROL_CONTINUOUS_H_SHIFT 7
-#define BCHP_HIF_CPUBIUCTRL_CPU3_AVS_ROSC_CONTROL_CONTINUOUS_H_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: CPU3_AVS_ROSC_CONTROL :: CONTINUOUS_S [06:06] */
-#define BCHP_HIF_CPUBIUCTRL_CPU3_AVS_ROSC_CONTROL_CONTINUOUS_S_MASK 0x00000040
-#define BCHP_HIF_CPUBIUCTRL_CPU3_AVS_ROSC_CONTROL_CONTINUOUS_S_SHIFT 6
-#define BCHP_HIF_CPUBIUCTRL_CPU3_AVS_ROSC_CONTROL_CONTINUOUS_S_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: CPU3_AVS_ROSC_CONTROL :: THRSH_EN_H [05:05] */
-#define BCHP_HIF_CPUBIUCTRL_CPU3_AVS_ROSC_CONTROL_THRSH_EN_H_MASK 0x00000020
-#define BCHP_HIF_CPUBIUCTRL_CPU3_AVS_ROSC_CONTROL_THRSH_EN_H_SHIFT 5
-#define BCHP_HIF_CPUBIUCTRL_CPU3_AVS_ROSC_CONTROL_THRSH_EN_H_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: CPU3_AVS_ROSC_CONTROL :: THRSH_EN_S [04:04] */
-#define BCHP_HIF_CPUBIUCTRL_CPU3_AVS_ROSC_CONTROL_THRSH_EN_S_MASK 0x00000010
-#define BCHP_HIF_CPUBIUCTRL_CPU3_AVS_ROSC_CONTROL_THRSH_EN_S_SHIFT 4
-#define BCHP_HIF_CPUBIUCTRL_CPU3_AVS_ROSC_CONTROL_THRSH_EN_S_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: CPU3_AVS_ROSC_CONTROL :: ECTR_EN_H [03:03] */
-#define BCHP_HIF_CPUBIUCTRL_CPU3_AVS_ROSC_CONTROL_ECTR_EN_H_MASK 0x00000008
-#define BCHP_HIF_CPUBIUCTRL_CPU3_AVS_ROSC_CONTROL_ECTR_EN_H_SHIFT 3
-#define BCHP_HIF_CPUBIUCTRL_CPU3_AVS_ROSC_CONTROL_ECTR_EN_H_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: CPU3_AVS_ROSC_CONTROL :: ECTR_EN_S [02:02] */
-#define BCHP_HIF_CPUBIUCTRL_CPU3_AVS_ROSC_CONTROL_ECTR_EN_S_MASK 0x00000004
-#define BCHP_HIF_CPUBIUCTRL_CPU3_AVS_ROSC_CONTROL_ECTR_EN_S_SHIFT 2
-#define BCHP_HIF_CPUBIUCTRL_CPU3_AVS_ROSC_CONTROL_ECTR_EN_S_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: CPU3_AVS_ROSC_CONTROL :: RO_EN_H [01:01] */
-#define BCHP_HIF_CPUBIUCTRL_CPU3_AVS_ROSC_CONTROL_RO_EN_H_MASK 0x00000002
-#define BCHP_HIF_CPUBIUCTRL_CPU3_AVS_ROSC_CONTROL_RO_EN_H_SHIFT 1
-#define BCHP_HIF_CPUBIUCTRL_CPU3_AVS_ROSC_CONTROL_RO_EN_H_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: CPU3_AVS_ROSC_CONTROL :: RO_EN_S [00:00] */
-#define BCHP_HIF_CPUBIUCTRL_CPU3_AVS_ROSC_CONTROL_RO_EN_S_MASK 0x00000001
-#define BCHP_HIF_CPUBIUCTRL_CPU3_AVS_ROSC_CONTROL_RO_EN_S_SHIFT 0
-#define BCHP_HIF_CPUBIUCTRL_CPU3_AVS_ROSC_CONTROL_RO_EN_S_DEFAULT 0x00000000
-
-/***************************************************************************
- *CPU3_AVS_ROSC_THRESHOLD - CPU3 Event Counter Threshold Register
- ***************************************************************************/
-/* HIF_CPUBIUCTRL :: CPU3_AVS_ROSC_THRESHOLD :: THRESH_HI [31:16] */
-#define BCHP_HIF_CPUBIUCTRL_CPU3_AVS_ROSC_THRESHOLD_THRESH_HI_MASK 0xffff0000
-#define BCHP_HIF_CPUBIUCTRL_CPU3_AVS_ROSC_THRESHOLD_THRESH_HI_SHIFT 16
-#define BCHP_HIF_CPUBIUCTRL_CPU3_AVS_ROSC_THRESHOLD_THRESH_HI_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: CPU3_AVS_ROSC_THRESHOLD :: THRESH_LO [15:00] */
-#define BCHP_HIF_CPUBIUCTRL_CPU3_AVS_ROSC_THRESHOLD_THRESH_LO_MASK 0x0000ffff
-#define BCHP_HIF_CPUBIUCTRL_CPU3_AVS_ROSC_THRESHOLD_THRESH_LO_SHIFT 0
-#define BCHP_HIF_CPUBIUCTRL_CPU3_AVS_ROSC_THRESHOLD_THRESH_LO_DEFAULT 0x00000000
-
-/***************************************************************************
- *CPU3_AVS_ROSC_COUNT - CPU3 Event Counter Count Register
- ***************************************************************************/
-/* HIF_CPUBIUCTRL :: CPU3_AVS_ROSC_COUNT :: COUNT_H [31:16] */
-#define BCHP_HIF_CPUBIUCTRL_CPU3_AVS_ROSC_COUNT_COUNT_H_MASK 0xffff0000
-#define BCHP_HIF_CPUBIUCTRL_CPU3_AVS_ROSC_COUNT_COUNT_H_SHIFT 16
-#define BCHP_HIF_CPUBIUCTRL_CPU3_AVS_ROSC_COUNT_COUNT_H_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: CPU3_AVS_ROSC_COUNT :: COUNT_S [15:00] */
-#define BCHP_HIF_CPUBIUCTRL_CPU3_AVS_ROSC_COUNT_COUNT_S_MASK 0x0000ffff
-#define BCHP_HIF_CPUBIUCTRL_CPU3_AVS_ROSC_COUNT_COUNT_S_SHIFT 0
-#define BCHP_HIF_CPUBIUCTRL_CPU3_AVS_ROSC_COUNT_COUNT_S_DEFAULT 0x00000000
-
-/***************************************************************************
- *CPU3_AVS_PWD_CONTROL - CPU3 PWD control Register
- ***************************************************************************/
-/* HIF_CPUBIUCTRL :: CPU3_AVS_PWD_CONTROL :: reserved0 [31:30] */
-#define BCHP_HIF_CPUBIUCTRL_CPU3_AVS_PWD_CONTROL_reserved0_MASK 0xc0000000
-#define BCHP_HIF_CPUBIUCTRL_CPU3_AVS_PWD_CONTROL_reserved0_SHIFT 30
-
-/* HIF_CPUBIUCTRL :: CPU3_AVS_PWD_CONTROL :: CLRCFG [29:27] */
-#define BCHP_HIF_CPUBIUCTRL_CPU3_AVS_PWD_CONTROL_CLRCFG_MASK 0x38000000
-#define BCHP_HIF_CPUBIUCTRL_CPU3_AVS_PWD_CONTROL_CLRCFG_SHIFT 27
-#define BCHP_HIF_CPUBIUCTRL_CPU3_AVS_PWD_CONTROL_CLRCFG_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: CPU3_AVS_PWD_CONTROL :: RSEL [26:24] */
-#define BCHP_HIF_CPUBIUCTRL_CPU3_AVS_PWD_CONTROL_RSEL_MASK 0x07000000
-#define BCHP_HIF_CPUBIUCTRL_CPU3_AVS_PWD_CONTROL_RSEL_SHIFT 24
-#define BCHP_HIF_CPUBIUCTRL_CPU3_AVS_PWD_CONTROL_RSEL_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: CPU3_AVS_PWD_CONTROL :: CGFG [23:16] */
-#define BCHP_HIF_CPUBIUCTRL_CPU3_AVS_PWD_CONTROL_CGFG_MASK 0x00ff0000
-#define BCHP_HIF_CPUBIUCTRL_CPU3_AVS_PWD_CONTROL_CGFG_SHIFT 16
-#define BCHP_HIF_CPUBIUCTRL_CPU3_AVS_PWD_CONTROL_CGFG_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: CPU3_AVS_PWD_CONTROL :: ALERT [15:15] */
-#define BCHP_HIF_CPUBIUCTRL_CPU3_AVS_PWD_CONTROL_ALERT_MASK 0x00008000
-#define BCHP_HIF_CPUBIUCTRL_CPU3_AVS_PWD_CONTROL_ALERT_SHIFT 15
-#define BCHP_HIF_CPUBIUCTRL_CPU3_AVS_PWD_CONTROL_ALERT_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: CPU3_AVS_PWD_CONTROL :: reserved1 [14:09] */
-#define BCHP_HIF_CPUBIUCTRL_CPU3_AVS_PWD_CONTROL_reserved1_MASK 0x00007e00
-#define BCHP_HIF_CPUBIUCTRL_CPU3_AVS_PWD_CONTROL_reserved1_SHIFT 9
-
-/* HIF_CPUBIUCTRL :: CPU3_AVS_PWD_CONTROL :: PWD_TM_EN [08:08] */
-#define BCHP_HIF_CPUBIUCTRL_CPU3_AVS_PWD_CONTROL_PWD_TM_EN_MASK 0x00000100
-#define BCHP_HIF_CPUBIUCTRL_CPU3_AVS_PWD_CONTROL_PWD_TM_EN_SHIFT 8
-#define BCHP_HIF_CPUBIUCTRL_CPU3_AVS_PWD_CONTROL_PWD_TM_EN_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: CPU3_AVS_PWD_CONTROL :: START [07:02] */
-#define BCHP_HIF_CPUBIUCTRL_CPU3_AVS_PWD_CONTROL_START_MASK 0x000000fc
-#define BCHP_HIF_CPUBIUCTRL_CPU3_AVS_PWD_CONTROL_START_SHIFT 2
-#define BCHP_HIF_CPUBIUCTRL_CPU3_AVS_PWD_CONTROL_START_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: CPU3_AVS_PWD_CONTROL :: PWD_ALERT_SEL [01:01] */
-#define BCHP_HIF_CPUBIUCTRL_CPU3_AVS_PWD_CONTROL_PWD_ALERT_SEL_MASK 0x00000002
-#define BCHP_HIF_CPUBIUCTRL_CPU3_AVS_PWD_CONTROL_PWD_ALERT_SEL_SHIFT 1
-#define BCHP_HIF_CPUBIUCTRL_CPU3_AVS_PWD_CONTROL_PWD_ALERT_SEL_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: CPU3_AVS_PWD_CONTROL :: PWD_EN [00:00] */
-#define BCHP_HIF_CPUBIUCTRL_CPU3_AVS_PWD_CONTROL_PWD_EN_MASK 0x00000001
-#define BCHP_HIF_CPUBIUCTRL_CPU3_AVS_PWD_CONTROL_PWD_EN_SHIFT 0
-#define BCHP_HIF_CPUBIUCTRL_CPU3_AVS_PWD_CONTROL_PWD_EN_DEFAULT 0x00000000
-
-/***************************************************************************
- *L2BIU_BPCM_ID - L2BIU BPCM ID Register
- ***************************************************************************/
-/* HIF_CPUBIUCTRL :: L2BIU_BPCM_ID :: SW_strap [31:16] */
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_BPCM_ID_SW_strap_MASK 0xffff0000
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_BPCM_ID_SW_strap_SHIFT 16
-
-/* HIF_CPUBIUCTRL :: L2BIU_BPCM_ID :: HW_revision [15:08] */
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_BPCM_ID_HW_revision_MASK 0x0000ff00
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_BPCM_ID_HW_revision_SHIFT 8
-
-/* HIF_CPUBIUCTRL :: L2BIU_BPCM_ID :: PMB_ADDR [07:00] */
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_BPCM_ID_PMB_ADDR_MASK 0x000000ff
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_BPCM_ID_PMB_ADDR_SHIFT 0
-
-/***************************************************************************
- *L2BIU_BPCM_CAPABILITY - L2BIU BPCM Capability Register
- ***************************************************************************/
-/* HIF_CPUBIUCTRL :: L2BIU_BPCM_CAPABILITY :: reserved0 [31:08] */
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_BPCM_CAPABILITY_reserved0_MASK 0xffffff00
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_BPCM_CAPABILITY_reserved0_SHIFT 8
-
-/* HIF_CPUBIUCTRL :: L2BIU_BPCM_CAPABILITY :: Number_of_zones [07:00] */
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_BPCM_CAPABILITY_Number_of_zones_MASK 0x000000ff
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_BPCM_CAPABILITY_Number_of_zones_SHIFT 0
-
-/***************************************************************************
- *L2BIU_BPCM_CONTROL - L2BIU BPCM Control Register
- ***************************************************************************/
-/* HIF_CPUBIUCTRL :: L2BIU_BPCM_CONTROL :: TbdField [31:00] */
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_BPCM_CONTROL_TbdField_MASK 0xffffffff
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_BPCM_CONTROL_TbdField_SHIFT 0
-
-/***************************************************************************
- *L2BIU_BPCM_STATUS - L2BIU BPCM Status Register
- ***************************************************************************/
-/* HIF_CPUBIUCTRL :: L2BIU_BPCM_STATUS :: reserved0 [31:01] */
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_BPCM_STATUS_reserved0_MASK 0xfffffffe
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_BPCM_STATUS_reserved0_SHIFT 1
-
-/* HIF_CPUBIUCTRL :: L2BIU_BPCM_STATUS :: PWD_Alert [00:00] */
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_BPCM_STATUS_PWD_Alert_MASK 0x00000001
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_BPCM_STATUS_PWD_Alert_SHIFT 0
-
-/***************************************************************************
- *L2BIU_AVS_ROSC_CONTROL - L2BIU Ring Oscillator Control Register
- ***************************************************************************/
-/* HIF_CPUBIUCTRL :: L2BIU_AVS_ROSC_CONTROL :: Test_interval [31:16] */
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_AVS_ROSC_CONTROL_Test_interval_MASK 0xffff0000
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_AVS_ROSC_CONTROL_Test_interval_SHIFT 16
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_AVS_ROSC_CONTROL_Test_interval_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: L2BIU_AVS_ROSC_CONTROL :: ALERT_H [15:15] */
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_AVS_ROSC_CONTROL_ALERT_H_MASK 0x00008000
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_AVS_ROSC_CONTROL_ALERT_H_SHIFT 15
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_AVS_ROSC_CONTROL_ALERT_H_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: L2BIU_AVS_ROSC_CONTROL :: VALID_H [14:14] */
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_AVS_ROSC_CONTROL_VALID_H_MASK 0x00004000
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_AVS_ROSC_CONTROL_VALID_H_SHIFT 14
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_AVS_ROSC_CONTROL_VALID_H_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: L2BIU_AVS_ROSC_CONTROL :: ALERT_S [13:13] */
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_AVS_ROSC_CONTROL_ALERT_S_MASK 0x00002000
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_AVS_ROSC_CONTROL_ALERT_S_SHIFT 13
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_AVS_ROSC_CONTROL_ALERT_S_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: L2BIU_AVS_ROSC_CONTROL :: VALID_S [12:12] */
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_AVS_ROSC_CONTROL_VALID_S_MASK 0x00001000
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_AVS_ROSC_CONTROL_VALID_S_SHIFT 12
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_AVS_ROSC_CONTROL_VALID_S_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: L2BIU_AVS_ROSC_CONTROL :: reserved0 [11:08] */
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_AVS_ROSC_CONTROL_reserved0_MASK 0x00000f00
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_AVS_ROSC_CONTROL_reserved0_SHIFT 8
-
-/* HIF_CPUBIUCTRL :: L2BIU_AVS_ROSC_CONTROL :: CONTINUOUS_H [07:07] */
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_AVS_ROSC_CONTROL_CONTINUOUS_H_MASK 0x00000080
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_AVS_ROSC_CONTROL_CONTINUOUS_H_SHIFT 7
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_AVS_ROSC_CONTROL_CONTINUOUS_H_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: L2BIU_AVS_ROSC_CONTROL :: CONTINUOUS_S [06:06] */
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_AVS_ROSC_CONTROL_CONTINUOUS_S_MASK 0x00000040
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_AVS_ROSC_CONTROL_CONTINUOUS_S_SHIFT 6
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_AVS_ROSC_CONTROL_CONTINUOUS_S_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: L2BIU_AVS_ROSC_CONTROL :: THRSH_EN_H [05:05] */
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_AVS_ROSC_CONTROL_THRSH_EN_H_MASK 0x00000020
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_AVS_ROSC_CONTROL_THRSH_EN_H_SHIFT 5
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_AVS_ROSC_CONTROL_THRSH_EN_H_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: L2BIU_AVS_ROSC_CONTROL :: THRSH_EN_S [04:04] */
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_AVS_ROSC_CONTROL_THRSH_EN_S_MASK 0x00000010
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_AVS_ROSC_CONTROL_THRSH_EN_S_SHIFT 4
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_AVS_ROSC_CONTROL_THRSH_EN_S_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: L2BIU_AVS_ROSC_CONTROL :: ECTR_EN_H [03:03] */
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_AVS_ROSC_CONTROL_ECTR_EN_H_MASK 0x00000008
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_AVS_ROSC_CONTROL_ECTR_EN_H_SHIFT 3
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_AVS_ROSC_CONTROL_ECTR_EN_H_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: L2BIU_AVS_ROSC_CONTROL :: ECTR_EN_S [02:02] */
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_AVS_ROSC_CONTROL_ECTR_EN_S_MASK 0x00000004
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_AVS_ROSC_CONTROL_ECTR_EN_S_SHIFT 2
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_AVS_ROSC_CONTROL_ECTR_EN_S_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: L2BIU_AVS_ROSC_CONTROL :: RO_EN_H [01:01] */
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_AVS_ROSC_CONTROL_RO_EN_H_MASK 0x00000002
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_AVS_ROSC_CONTROL_RO_EN_H_SHIFT 1
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_AVS_ROSC_CONTROL_RO_EN_H_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: L2BIU_AVS_ROSC_CONTROL :: RO_EN_S [00:00] */
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_AVS_ROSC_CONTROL_RO_EN_S_MASK 0x00000001
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_AVS_ROSC_CONTROL_RO_EN_S_SHIFT 0
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_AVS_ROSC_CONTROL_RO_EN_S_DEFAULT 0x00000000
-
-/***************************************************************************
- *L2BIU_AVS_ROSC_THRESHOLD - L2BIU Event Counter Threshold Register
- ***************************************************************************/
-/* HIF_CPUBIUCTRL :: L2BIU_AVS_ROSC_THRESHOLD :: THRESH_HI [31:16] */
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_AVS_ROSC_THRESHOLD_THRESH_HI_MASK 0xffff0000
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_AVS_ROSC_THRESHOLD_THRESH_HI_SHIFT 16
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_AVS_ROSC_THRESHOLD_THRESH_HI_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: L2BIU_AVS_ROSC_THRESHOLD :: THRESH_LO [15:00] */
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_AVS_ROSC_THRESHOLD_THRESH_LO_MASK 0x0000ffff
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_AVS_ROSC_THRESHOLD_THRESH_LO_SHIFT 0
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_AVS_ROSC_THRESHOLD_THRESH_LO_DEFAULT 0x00000000
-
-/***************************************************************************
- *L2BIU_AVS_ROSC_COUNT - L2BIU Event Counter Count Register
- ***************************************************************************/
-/* HIF_CPUBIUCTRL :: L2BIU_AVS_ROSC_COUNT :: COUNT_H [31:16] */
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_AVS_ROSC_COUNT_COUNT_H_MASK 0xffff0000
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_AVS_ROSC_COUNT_COUNT_H_SHIFT 16
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_AVS_ROSC_COUNT_COUNT_H_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: L2BIU_AVS_ROSC_COUNT :: COUNT_S [15:00] */
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_AVS_ROSC_COUNT_COUNT_S_MASK 0x0000ffff
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_AVS_ROSC_COUNT_COUNT_S_SHIFT 0
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_AVS_ROSC_COUNT_COUNT_S_DEFAULT 0x00000000
-
-/***************************************************************************
- *L2BIU_AVS_PWD_CONTROL - L2BIU PWD control Register
- ***************************************************************************/
-/* HIF_CPUBIUCTRL :: L2BIU_AVS_PWD_CONTROL :: reserved0 [31:30] */
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_AVS_PWD_CONTROL_reserved0_MASK 0xc0000000
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_AVS_PWD_CONTROL_reserved0_SHIFT 30
-
-/* HIF_CPUBIUCTRL :: L2BIU_AVS_PWD_CONTROL :: CLRCFG [29:27] */
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_AVS_PWD_CONTROL_CLRCFG_MASK 0x38000000
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_AVS_PWD_CONTROL_CLRCFG_SHIFT 27
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_AVS_PWD_CONTROL_CLRCFG_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: L2BIU_AVS_PWD_CONTROL :: RSEL [26:24] */
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_AVS_PWD_CONTROL_RSEL_MASK 0x07000000
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_AVS_PWD_CONTROL_RSEL_SHIFT 24
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_AVS_PWD_CONTROL_RSEL_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: L2BIU_AVS_PWD_CONTROL :: CGFG [23:16] */
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_AVS_PWD_CONTROL_CGFG_MASK 0x00ff0000
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_AVS_PWD_CONTROL_CGFG_SHIFT 16
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_AVS_PWD_CONTROL_CGFG_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: L2BIU_AVS_PWD_CONTROL :: ALERT [15:15] */
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_AVS_PWD_CONTROL_ALERT_MASK 0x00008000
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_AVS_PWD_CONTROL_ALERT_SHIFT 15
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_AVS_PWD_CONTROL_ALERT_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: L2BIU_AVS_PWD_CONTROL :: reserved1 [14:09] */
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_AVS_PWD_CONTROL_reserved1_MASK 0x00007e00
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_AVS_PWD_CONTROL_reserved1_SHIFT 9
-
-/* HIF_CPUBIUCTRL :: L2BIU_AVS_PWD_CONTROL :: PWD_TM_EN [08:08] */
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_AVS_PWD_CONTROL_PWD_TM_EN_MASK 0x00000100
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_AVS_PWD_CONTROL_PWD_TM_EN_SHIFT 8
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_AVS_PWD_CONTROL_PWD_TM_EN_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: L2BIU_AVS_PWD_CONTROL :: START [07:02] */
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_AVS_PWD_CONTROL_START_MASK 0x000000fc
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_AVS_PWD_CONTROL_START_SHIFT 2
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_AVS_PWD_CONTROL_START_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: L2BIU_AVS_PWD_CONTROL :: PWD_ALERT_SEL [01:01] */
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_AVS_PWD_CONTROL_PWD_ALERT_SEL_MASK 0x00000002
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_AVS_PWD_CONTROL_PWD_ALERT_SEL_SHIFT 1
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_AVS_PWD_CONTROL_PWD_ALERT_SEL_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: L2BIU_AVS_PWD_CONTROL :: PWD_EN [00:00] */
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_AVS_PWD_CONTROL_PWD_EN_MASK 0x00000001
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_AVS_PWD_CONTROL_PWD_EN_SHIFT 0
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_AVS_PWD_CONTROL_PWD_EN_DEFAULT 0x00000000
-
-/***************************************************************************
- *CPU_RESET_CONFIG_REG - CPU Reset Configuration Register
- ***************************************************************************/
-/* HIF_CPUBIUCTRL :: CPU_RESET_CONFIG_REG :: reserved0 [31:04] */
-#define BCHP_HIF_CPUBIUCTRL_CPU_RESET_CONFIG_REG_reserved0_MASK 0xfffffff0
-#define BCHP_HIF_CPUBIUCTRL_CPU_RESET_CONFIG_REG_reserved0_SHIFT 4
-
-/* HIF_CPUBIUCTRL :: CPU_RESET_CONFIG_REG :: CPU3_RESET [03:03] */
-#define BCHP_HIF_CPUBIUCTRL_CPU_RESET_CONFIG_REG_CPU3_RESET_MASK 0x00000008
-#define BCHP_HIF_CPUBIUCTRL_CPU_RESET_CONFIG_REG_CPU3_RESET_SHIFT 3
-#define BCHP_HIF_CPUBIUCTRL_CPU_RESET_CONFIG_REG_CPU3_RESET_DEFAULT 0x00000001
-
-/* HIF_CPUBIUCTRL :: CPU_RESET_CONFIG_REG :: CPU2_RESET [02:02] */
-#define BCHP_HIF_CPUBIUCTRL_CPU_RESET_CONFIG_REG_CPU2_RESET_MASK 0x00000004
-#define BCHP_HIF_CPUBIUCTRL_CPU_RESET_CONFIG_REG_CPU2_RESET_SHIFT 2
-#define BCHP_HIF_CPUBIUCTRL_CPU_RESET_CONFIG_REG_CPU2_RESET_DEFAULT 0x00000001
-
-/* HIF_CPUBIUCTRL :: CPU_RESET_CONFIG_REG :: CPU1_RESET [01:01] */
-#define BCHP_HIF_CPUBIUCTRL_CPU_RESET_CONFIG_REG_CPU1_RESET_MASK 0x00000002
-#define BCHP_HIF_CPUBIUCTRL_CPU_RESET_CONFIG_REG_CPU1_RESET_SHIFT 1
-#define BCHP_HIF_CPUBIUCTRL_CPU_RESET_CONFIG_REG_CPU1_RESET_DEFAULT 0x00000001
-
-/* HIF_CPUBIUCTRL :: CPU_RESET_CONFIG_REG :: CPU0_RESET [00:00] */
-#define BCHP_HIF_CPUBIUCTRL_CPU_RESET_CONFIG_REG_CPU0_RESET_MASK 0x00000001
-#define BCHP_HIF_CPUBIUCTRL_CPU_RESET_CONFIG_REG_CPU0_RESET_SHIFT 0
-#define BCHP_HIF_CPUBIUCTRL_CPU_RESET_CONFIG_REG_CPU0_RESET_DEFAULT 0x00000000
-
-/***************************************************************************
- *CPU_CLOCK_CONFIG_REG - CPU Clock Configuration Register
- ***************************************************************************/
-/* HIF_CPUBIUCTRL :: CPU_CLOCK_CONFIG_REG :: reserved0 [31:12] */
-#define BCHP_HIF_CPUBIUCTRL_CPU_CLOCK_CONFIG_REG_reserved0_MASK 0xfffff000
-#define BCHP_HIF_CPUBIUCTRL_CPU_CLOCK_CONFIG_REG_reserved0_SHIFT 12
-
-/* HIF_CPUBIUCTRL :: CPU_CLOCK_CONFIG_REG :: GIC_CLK_RATIO [11:08] */
-#define BCHP_HIF_CPUBIUCTRL_CPU_CLOCK_CONFIG_REG_GIC_CLK_RATIO_MASK 0x00000f00
-#define BCHP_HIF_CPUBIUCTRL_CPU_CLOCK_CONFIG_REG_GIC_CLK_RATIO_SHIFT 8
-#define BCHP_HIF_CPUBIUCTRL_CPU_CLOCK_CONFIG_REG_GIC_CLK_RATIO_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: CPU_CLOCK_CONFIG_REG :: reserved1 [07:06] */
-#define BCHP_HIF_CPUBIUCTRL_CPU_CLOCK_CONFIG_REG_reserved1_MASK 0x000000c0
-#define BCHP_HIF_CPUBIUCTRL_CPU_CLOCK_CONFIG_REG_reserved1_SHIFT 6
-
-/* HIF_CPUBIUCTRL :: CPU_CLOCK_CONFIG_REG :: UBUS_CLK_EN [05:05] */
-#define BCHP_HIF_CPUBIUCTRL_CPU_CLOCK_CONFIG_REG_UBUS_CLK_EN_MASK 0x00000020
-#define BCHP_HIF_CPUBIUCTRL_CPU_CLOCK_CONFIG_REG_UBUS_CLK_EN_SHIFT 5
-#define BCHP_HIF_CPUBIUCTRL_CPU_CLOCK_CONFIG_REG_UBUS_CLK_EN_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: CPU_CLOCK_CONFIG_REG :: SAFE_CLK_MODE [04:04] */
-#define BCHP_HIF_CPUBIUCTRL_CPU_CLOCK_CONFIG_REG_SAFE_CLK_MODE_MASK 0x00000010
-#define BCHP_HIF_CPUBIUCTRL_CPU_CLOCK_CONFIG_REG_SAFE_CLK_MODE_SHIFT 4
-#define BCHP_HIF_CPUBIUCTRL_CPU_CLOCK_CONFIG_REG_SAFE_CLK_MODE_DEFAULT 0x00000001
-
-/* HIF_CPUBIUCTRL :: CPU_CLOCK_CONFIG_REG :: CLK_RATIO [03:00] */
-#define BCHP_HIF_CPUBIUCTRL_CPU_CLOCK_CONFIG_REG_CLK_RATIO_MASK 0x0000000f
-#define BCHP_HIF_CPUBIUCTRL_CPU_CLOCK_CONFIG_REG_CLK_RATIO_SHIFT 0
-#define BCHP_HIF_CPUBIUCTRL_CPU_CLOCK_CONFIG_REG_CLK_RATIO_DEFAULT 0x00000001
-
-/***************************************************************************
- *CPU_MISC_CONFIG_REG - CPU Miscellaneous Configuration Register
- ***************************************************************************/
-/* HIF_CPUBIUCTRL :: CPU_MISC_CONFIG_REG :: MiscCommands [31:08] */
-#define BCHP_HIF_CPUBIUCTRL_CPU_MISC_CONFIG_REG_MiscCommands_MASK 0xffffff00
-#define BCHP_HIF_CPUBIUCTRL_CPU_MISC_CONFIG_REG_MiscCommands_SHIFT 8
-#define BCHP_HIF_CPUBIUCTRL_CPU_MISC_CONFIG_REG_MiscCommands_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: CPU_MISC_CONFIG_REG :: ENABLE_PMUIRQ [07:04] */
-#define BCHP_HIF_CPUBIUCTRL_CPU_MISC_CONFIG_REG_ENABLE_PMUIRQ_MASK 0x000000f0
-#define BCHP_HIF_CPUBIUCTRL_CPU_MISC_CONFIG_REG_ENABLE_PMUIRQ_SHIFT 4
-#define BCHP_HIF_CPUBIUCTRL_CPU_MISC_CONFIG_REG_ENABLE_PMUIRQ_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: CPU_MISC_CONFIG_REG :: VINITHI [03:00] */
-#define BCHP_HIF_CPUBIUCTRL_CPU_MISC_CONFIG_REG_VINITHI_MASK 0x0000000f
-#define BCHP_HIF_CPUBIUCTRL_CPU_MISC_CONFIG_REG_VINITHI_SHIFT 0
-#define BCHP_HIF_CPUBIUCTRL_CPU_MISC_CONFIG_REG_VINITHI_DEFAULT 0x0000000f
-
-/***************************************************************************
- *CPU_CREDIT_REG - CPU Request Credit Register
- ***************************************************************************/
-/* HIF_CPUBIUCTRL :: CPU_CREDIT_REG :: reserved0 [31:31] */
-#define BCHP_HIF_CPUBIUCTRL_CPU_CREDIT_REG_reserved0_MASK 0x80000000
-#define BCHP_HIF_CPUBIUCTRL_CPU_CREDIT_REG_reserved0_SHIFT 31
-
-/* HIF_CPUBIUCTRL :: CPU_CREDIT_REG :: MCP2_WR_PAIRING_EN [30:30] */
-#define BCHP_HIF_CPUBIUCTRL_CPU_CREDIT_REG_MCP2_WR_PAIRING_EN_MASK 0x40000000
-#define BCHP_HIF_CPUBIUCTRL_CPU_CREDIT_REG_MCP2_WR_PAIRING_EN_SHIFT 30
-#define BCHP_HIF_CPUBIUCTRL_CPU_CREDIT_REG_MCP2_WR_PAIRING_EN_DEFAULT 0x00000001
-
-/* HIF_CPUBIUCTRL :: CPU_CREDIT_REG :: MCP1_WR_PAIRING_EN [29:29] */
-#define BCHP_HIF_CPUBIUCTRL_CPU_CREDIT_REG_MCP1_WR_PAIRING_EN_MASK 0x20000000
-#define BCHP_HIF_CPUBIUCTRL_CPU_CREDIT_REG_MCP1_WR_PAIRING_EN_SHIFT 29
-#define BCHP_HIF_CPUBIUCTRL_CPU_CREDIT_REG_MCP1_WR_PAIRING_EN_DEFAULT 0x00000001
-
-/* HIF_CPUBIUCTRL :: CPU_CREDIT_REG :: MCP0_WR_PAIRING_EN [28:28] */
-#define BCHP_HIF_CPUBIUCTRL_CPU_CREDIT_REG_MCP0_WR_PAIRING_EN_MASK 0x10000000
-#define BCHP_HIF_CPUBIUCTRL_CPU_CREDIT_REG_MCP0_WR_PAIRING_EN_SHIFT 28
-#define BCHP_HIF_CPUBIUCTRL_CPU_CREDIT_REG_MCP0_WR_PAIRING_EN_DEFAULT 0x00000001
-
-/* HIF_CPUBIUCTRL :: CPU_CREDIT_REG :: reserved1 [27:24] */
-#define BCHP_HIF_CPUBIUCTRL_CPU_CREDIT_REG_reserved1_MASK 0x0f000000
-#define BCHP_HIF_CPUBIUCTRL_CPU_CREDIT_REG_reserved1_SHIFT 24
-
-/* HIF_CPUBIUCTRL :: CPU_CREDIT_REG :: MCP2_WRITE_CRED [23:20] */
-#define BCHP_HIF_CPUBIUCTRL_CPU_CREDIT_REG_MCP2_WRITE_CRED_MASK 0x00f00000
-#define BCHP_HIF_CPUBIUCTRL_CPU_CREDIT_REG_MCP2_WRITE_CRED_SHIFT 20
-#define BCHP_HIF_CPUBIUCTRL_CPU_CREDIT_REG_MCP2_WRITE_CRED_DEFAULT 0x00000004
-
-/* HIF_CPUBIUCTRL :: CPU_CREDIT_REG :: MCP2_READ_CRED [19:16] */
-#define BCHP_HIF_CPUBIUCTRL_CPU_CREDIT_REG_MCP2_READ_CRED_MASK 0x000f0000
-#define BCHP_HIF_CPUBIUCTRL_CPU_CREDIT_REG_MCP2_READ_CRED_SHIFT 16
-#define BCHP_HIF_CPUBIUCTRL_CPU_CREDIT_REG_MCP2_READ_CRED_DEFAULT 0x00000004
-
-/* HIF_CPUBIUCTRL :: CPU_CREDIT_REG :: MCP1_WRITE_CRED [15:12] */
-#define BCHP_HIF_CPUBIUCTRL_CPU_CREDIT_REG_MCP1_WRITE_CRED_MASK 0x0000f000
-#define BCHP_HIF_CPUBIUCTRL_CPU_CREDIT_REG_MCP1_WRITE_CRED_SHIFT 12
-#define BCHP_HIF_CPUBIUCTRL_CPU_CREDIT_REG_MCP1_WRITE_CRED_DEFAULT 0x00000004
-
-/* HIF_CPUBIUCTRL :: CPU_CREDIT_REG :: MCP1_READ_CRED [11:08] */
-#define BCHP_HIF_CPUBIUCTRL_CPU_CREDIT_REG_MCP1_READ_CRED_MASK 0x00000f00
-#define BCHP_HIF_CPUBIUCTRL_CPU_CREDIT_REG_MCP1_READ_CRED_SHIFT 8
-#define BCHP_HIF_CPUBIUCTRL_CPU_CREDIT_REG_MCP1_READ_CRED_DEFAULT 0x00000004
-
-/* HIF_CPUBIUCTRL :: CPU_CREDIT_REG :: MCP0_WRITE_CRED [07:04] */
-#define BCHP_HIF_CPUBIUCTRL_CPU_CREDIT_REG_MCP0_WRITE_CRED_MASK 0x000000f0
-#define BCHP_HIF_CPUBIUCTRL_CPU_CREDIT_REG_MCP0_WRITE_CRED_SHIFT 4
-#define BCHP_HIF_CPUBIUCTRL_CPU_CREDIT_REG_MCP0_WRITE_CRED_DEFAULT 0x00000004
-
-/* HIF_CPUBIUCTRL :: CPU_CREDIT_REG :: MCP0_READ_CRED [03:00] */
-#define BCHP_HIF_CPUBIUCTRL_CPU_CREDIT_REG_MCP0_READ_CRED_MASK 0x0000000f
-#define BCHP_HIF_CPUBIUCTRL_CPU_CREDIT_REG_MCP0_READ_CRED_SHIFT 0
-#define BCHP_HIF_CPUBIUCTRL_CPU_CREDIT_REG_MCP0_READ_CRED_DEFAULT 0x00000004
-
-/***************************************************************************
- *CPU_THERM_THROTTLE_TEMP_REG - CPU Thermal Throttling IRQ Config Register
- ***************************************************************************/
-/* HIF_CPUBIUCTRL :: CPU_THERM_THROTTLE_TEMP_REG :: Valid [31:31] */
-#define BCHP_HIF_CPUBIUCTRL_CPU_THERM_THROTTLE_TEMP_REG_Valid_MASK 0x80000000
-#define BCHP_HIF_CPUBIUCTRL_CPU_THERM_THROTTLE_TEMP_REG_Valid_SHIFT 31
-#define BCHP_HIF_CPUBIUCTRL_CPU_THERM_THROTTLE_TEMP_REG_Valid_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: CPU_THERM_THROTTLE_TEMP_REG :: reserved0 [30:10] */
-#define BCHP_HIF_CPUBIUCTRL_CPU_THERM_THROTTLE_TEMP_REG_reserved0_MASK 0x7ffffc00
-#define BCHP_HIF_CPUBIUCTRL_CPU_THERM_THROTTLE_TEMP_REG_reserved0_SHIFT 10
-
-/* HIF_CPUBIUCTRL :: CPU_THERM_THROTTLE_TEMP_REG :: Temp [09:00] */
-#define BCHP_HIF_CPUBIUCTRL_CPU_THERM_THROTTLE_TEMP_REG_Temp_MASK 0x000003ff
-#define BCHP_HIF_CPUBIUCTRL_CPU_THERM_THROTTLE_TEMP_REG_Temp_SHIFT 0
-#define BCHP_HIF_CPUBIUCTRL_CPU_THERM_THROTTLE_TEMP_REG_Temp_DEFAULT 0x00000000
-
-/***************************************************************************
- *CPU_THERM_THROTTLE_IRQ_CONFIG_REG - CPU Thermal Throttling IRQ Config Register
- ***************************************************************************/
-/* HIF_CPUBIUCTRL :: CPU_THERM_THROTTLE_IRQ_CONFIG_REG :: reserved0 [31:27] */
-#define BCHP_HIF_CPUBIUCTRL_CPU_THERM_THROTTLE_IRQ_CONFIG_REG_reserved0_MASK 0xf8000000
-#define BCHP_HIF_CPUBIUCTRL_CPU_THERM_THROTTLE_IRQ_CONFIG_REG_reserved0_SHIFT 27
-
-/* HIF_CPUBIUCTRL :: CPU_THERM_THROTTLE_IRQ_CONFIG_REG :: ThermCtl [26:24] */
-#define BCHP_HIF_CPUBIUCTRL_CPU_THERM_THROTTLE_IRQ_CONFIG_REG_ThermCtl_MASK 0x07000000
-#define BCHP_HIF_CPUBIUCTRL_CPU_THERM_THROTTLE_IRQ_CONFIG_REG_ThermCtl_SHIFT 24
-#define BCHP_HIF_CPUBIUCTRL_CPU_THERM_THROTTLE_IRQ_CONFIG_REG_ThermCtl_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: CPU_THERM_THROTTLE_IRQ_CONFIG_REG :: Irq_Enable_Low [23:23] */
-#define BCHP_HIF_CPUBIUCTRL_CPU_THERM_THROTTLE_IRQ_CONFIG_REG_Irq_Enable_Low_MASK 0x00800000
-#define BCHP_HIF_CPUBIUCTRL_CPU_THERM_THROTTLE_IRQ_CONFIG_REG_Irq_Enable_Low_SHIFT 23
-#define BCHP_HIF_CPUBIUCTRL_CPU_THERM_THROTTLE_IRQ_CONFIG_REG_Irq_Enable_Low_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: CPU_THERM_THROTTLE_IRQ_CONFIG_REG :: Irq_Enable_High [22:22] */
-#define BCHP_HIF_CPUBIUCTRL_CPU_THERM_THROTTLE_IRQ_CONFIG_REG_Irq_Enable_High_MASK 0x00400000
-#define BCHP_HIF_CPUBIUCTRL_CPU_THERM_THROTTLE_IRQ_CONFIG_REG_Irq_Enable_High_SHIFT 22
-#define BCHP_HIF_CPUBIUCTRL_CPU_THERM_THROTTLE_IRQ_CONFIG_REG_Irq_Enable_High_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: CPU_THERM_THROTTLE_IRQ_CONFIG_REG :: Temp_Threshold_Low [21:12] */
-#define BCHP_HIF_CPUBIUCTRL_CPU_THERM_THROTTLE_IRQ_CONFIG_REG_Temp_Threshold_Low_MASK 0x003ff000
-#define BCHP_HIF_CPUBIUCTRL_CPU_THERM_THROTTLE_IRQ_CONFIG_REG_Temp_Threshold_Low_SHIFT 12
-#define BCHP_HIF_CPUBIUCTRL_CPU_THERM_THROTTLE_IRQ_CONFIG_REG_Temp_Threshold_Low_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: CPU_THERM_THROTTLE_IRQ_CONFIG_REG :: reserved1 [11:10] */
-#define BCHP_HIF_CPUBIUCTRL_CPU_THERM_THROTTLE_IRQ_CONFIG_REG_reserved1_MASK 0x00000c00
-#define BCHP_HIF_CPUBIUCTRL_CPU_THERM_THROTTLE_IRQ_CONFIG_REG_reserved1_SHIFT 10
-
-/* HIF_CPUBIUCTRL :: CPU_THERM_THROTTLE_IRQ_CONFIG_REG :: Temp_Threshold_High [09:00] */
-#define BCHP_HIF_CPUBIUCTRL_CPU_THERM_THROTTLE_IRQ_CONFIG_REG_Temp_Threshold_High_MASK 0x000003ff
-#define BCHP_HIF_CPUBIUCTRL_CPU_THERM_THROTTLE_IRQ_CONFIG_REG_Temp_Threshold_High_SHIFT 0
-#define BCHP_HIF_CPUBIUCTRL_CPU_THERM_THROTTLE_IRQ_CONFIG_REG_Temp_Threshold_High_DEFAULT 0x00000000
-
-/***************************************************************************
- *CPU_THERM_IRQ_HIGH_REG - CPU Thermal Throttling IRQ High Register
- ***************************************************************************/
-/* HIF_CPUBIUCTRL :: CPU_THERM_IRQ_HIGH_REG :: reserved0 [31:01] */
-#define BCHP_HIF_CPUBIUCTRL_CPU_THERM_IRQ_HIGH_REG_reserved0_MASK 0xfffffffe
-#define BCHP_HIF_CPUBIUCTRL_CPU_THERM_IRQ_HIGH_REG_reserved0_SHIFT 1
-
-/* HIF_CPUBIUCTRL :: CPU_THERM_IRQ_HIGH_REG :: Therm_Irq_High [00:00] */
-#define BCHP_HIF_CPUBIUCTRL_CPU_THERM_IRQ_HIGH_REG_Therm_Irq_High_MASK 0x00000001
-#define BCHP_HIF_CPUBIUCTRL_CPU_THERM_IRQ_HIGH_REG_Therm_Irq_High_SHIFT 0
-#define BCHP_HIF_CPUBIUCTRL_CPU_THERM_IRQ_HIGH_REG_Therm_Irq_High_DEFAULT 0x00000000
-
-/***************************************************************************
- *CPU_THERM_IRQ_LOW_REG - CPU Thermal Throttling IRQ Low Register
- ***************************************************************************/
-/* HIF_CPUBIUCTRL :: CPU_THERM_IRQ_LOW_REG :: reserved0 [31:01] */
-#define BCHP_HIF_CPUBIUCTRL_CPU_THERM_IRQ_LOW_REG_reserved0_MASK 0xfffffffe
-#define BCHP_HIF_CPUBIUCTRL_CPU_THERM_IRQ_LOW_REG_reserved0_SHIFT 1
-
-/* HIF_CPUBIUCTRL :: CPU_THERM_IRQ_LOW_REG :: Therm_Irq_Low [00:00] */
-#define BCHP_HIF_CPUBIUCTRL_CPU_THERM_IRQ_LOW_REG_Therm_Irq_Low_MASK 0x00000001
-#define BCHP_HIF_CPUBIUCTRL_CPU_THERM_IRQ_LOW_REG_Therm_Irq_Low_SHIFT 0
-#define BCHP_HIF_CPUBIUCTRL_CPU_THERM_IRQ_LOW_REG_Therm_Irq_Low_DEFAULT 0x00000000
-
-/***************************************************************************
- *CPU_THERM_MISC_THRESHOLD_REG - CPU Thermal Throttling Misc Threshold Register
- ***************************************************************************/
-/* HIF_CPUBIUCTRL :: CPU_THERM_MISC_THRESHOLD_REG :: reserved0 [31:23] */
-#define BCHP_HIF_CPUBIUCTRL_CPU_THERM_MISC_THRESHOLD_REG_reserved0_MASK 0xff800000
-#define BCHP_HIF_CPUBIUCTRL_CPU_THERM_MISC_THRESHOLD_REG_reserved0_SHIFT 23
-
-/* HIF_CPUBIUCTRL :: CPU_THERM_MISC_THRESHOLD_REG :: Misc_Irq_Enable [22:22] */
-#define BCHP_HIF_CPUBIUCTRL_CPU_THERM_MISC_THRESHOLD_REG_Misc_Irq_Enable_MASK 0x00400000
-#define BCHP_HIF_CPUBIUCTRL_CPU_THERM_MISC_THRESHOLD_REG_Misc_Irq_Enable_SHIFT 22
-#define BCHP_HIF_CPUBIUCTRL_CPU_THERM_MISC_THRESHOLD_REG_Misc_Irq_Enable_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: CPU_THERM_MISC_THRESHOLD_REG :: Temp_Threshold_Low [21:12] */
-#define BCHP_HIF_CPUBIUCTRL_CPU_THERM_MISC_THRESHOLD_REG_Temp_Threshold_Low_MASK 0x003ff000
-#define BCHP_HIF_CPUBIUCTRL_CPU_THERM_MISC_THRESHOLD_REG_Temp_Threshold_Low_SHIFT 12
-#define BCHP_HIF_CPUBIUCTRL_CPU_THERM_MISC_THRESHOLD_REG_Temp_Threshold_Low_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: CPU_THERM_MISC_THRESHOLD_REG :: reserved1 [11:10] */
-#define BCHP_HIF_CPUBIUCTRL_CPU_THERM_MISC_THRESHOLD_REG_reserved1_MASK 0x00000c00
-#define BCHP_HIF_CPUBIUCTRL_CPU_THERM_MISC_THRESHOLD_REG_reserved1_SHIFT 10
-
-/* HIF_CPUBIUCTRL :: CPU_THERM_MISC_THRESHOLD_REG :: Temp_Threshold_High [09:00] */
-#define BCHP_HIF_CPUBIUCTRL_CPU_THERM_MISC_THRESHOLD_REG_Temp_Threshold_High_MASK 0x000003ff
-#define BCHP_HIF_CPUBIUCTRL_CPU_THERM_MISC_THRESHOLD_REG_Temp_Threshold_High_SHIFT 0
-#define BCHP_HIF_CPUBIUCTRL_CPU_THERM_MISC_THRESHOLD_REG_Temp_Threshold_High_DEFAULT 0x00000000
-
-/***************************************************************************
- *CPU_THERM_IRQ_MISC_REG - CPU Thermal Throttling Misc IRQ Register
- ***************************************************************************/
-/* HIF_CPUBIUCTRL :: CPU_THERM_IRQ_MISC_REG :: reserved0 [31:01] */
-#define BCHP_HIF_CPUBIUCTRL_CPU_THERM_IRQ_MISC_REG_reserved0_MASK 0xfffffffe
-#define BCHP_HIF_CPUBIUCTRL_CPU_THERM_IRQ_MISC_REG_reserved0_SHIFT 1
-
-/* HIF_CPUBIUCTRL :: CPU_THERM_IRQ_MISC_REG :: Therm_Irq_Misc [00:00] */
-#define BCHP_HIF_CPUBIUCTRL_CPU_THERM_IRQ_MISC_REG_Therm_Irq_Misc_MASK 0x00000001
-#define BCHP_HIF_CPUBIUCTRL_CPU_THERM_IRQ_MISC_REG_Therm_Irq_Misc_SHIFT 0
-
-/***************************************************************************
- *CPU_DEFEATURE_REG - CPU Defeature Register
- ***************************************************************************/
-/* HIF_CPUBIUCTRL :: CPU_DEFEATURE_REG :: TBD_field [31:08] */
-#define BCHP_HIF_CPUBIUCTRL_CPU_DEFEATURE_REG_TBD_field_MASK 0xffffff00
-#define BCHP_HIF_CPUBIUCTRL_CPU_DEFEATURE_REG_TBD_field_SHIFT 8
-#define BCHP_HIF_CPUBIUCTRL_CPU_DEFEATURE_REG_TBD_field_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: CPU_DEFEATURE_REG :: RAC_DEBUG [07:04] */
-#define BCHP_HIF_CPUBIUCTRL_CPU_DEFEATURE_REG_RAC_DEBUG_MASK 0x000000f0
-#define BCHP_HIF_CPUBIUCTRL_CPU_DEFEATURE_REG_RAC_DEBUG_SHIFT 4
-#define BCHP_HIF_CPUBIUCTRL_CPU_DEFEATURE_REG_RAC_DEBUG_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: CPU_DEFEATURE_REG :: RAC_DEFEATURE [03:00] */
-#define BCHP_HIF_CPUBIUCTRL_CPU_DEFEATURE_REG_RAC_DEFEATURE_MASK 0x0000000f
-#define BCHP_HIF_CPUBIUCTRL_CPU_DEFEATURE_REG_RAC_DEFEATURE_SHIFT 0
-#define BCHP_HIF_CPUBIUCTRL_CPU_DEFEATURE_REG_RAC_DEFEATURE_DEFAULT 0x00000000
-
-/***************************************************************************
- *CPU_DEFEATURE_KEY_REG - CPU Defeature Key Register
- ***************************************************************************/
-/* HIF_CPUBIUCTRL :: CPU_DEFEATURE_KEY_REG :: KEY [31:00] */
-#define BCHP_HIF_CPUBIUCTRL_CPU_DEFEATURE_KEY_REG_KEY_MASK 0xffffffff
-#define BCHP_HIF_CPUBIUCTRL_CPU_DEFEATURE_KEY_REG_KEY_SHIFT 0
-#define BCHP_HIF_CPUBIUCTRL_CPU_DEFEATURE_KEY_REG_KEY_DEFAULT 0x00000000
-
-/***************************************************************************
- *CPU_DEBUGROMADDR_REG - CPU Debug ROM Address Register
- ***************************************************************************/
-/* HIF_CPUBIUCTRL :: CPU_DEBUGROMADDR_REG :: DBGROMADDR [31:04] */
-#define BCHP_HIF_CPUBIUCTRL_CPU_DEBUGROMADDR_REG_DBGROMADDR_MASK 0xfffffff0
-#define BCHP_HIF_CPUBIUCTRL_CPU_DEBUGROMADDR_REG_DBGROMADDR_SHIFT 4
-#define BCHP_HIF_CPUBIUCTRL_CPU_DEBUGROMADDR_REG_DBGROMADDR_DEFAULT 0x01200000
-
-/* HIF_CPUBIUCTRL :: CPU_DEBUGROMADDR_REG :: reserved0 [03:01] */
-#define BCHP_HIF_CPUBIUCTRL_CPU_DEBUGROMADDR_REG_reserved0_MASK 0x0000000e
-#define BCHP_HIF_CPUBIUCTRL_CPU_DEBUGROMADDR_REG_reserved0_SHIFT 1
-
-/* HIF_CPUBIUCTRL :: CPU_DEBUGROMADDR_REG :: DBGROMADDRV [00:00] */
-#define BCHP_HIF_CPUBIUCTRL_CPU_DEBUGROMADDR_REG_DBGROMADDRV_MASK 0x00000001
-#define BCHP_HIF_CPUBIUCTRL_CPU_DEBUGROMADDR_REG_DBGROMADDRV_SHIFT 0
-#define BCHP_HIF_CPUBIUCTRL_CPU_DEBUGROMADDR_REG_DBGROMADDRV_DEFAULT 0x00000000
-
-/***************************************************************************
- *CPU_DEBUGSELFADDR_REG - CPU Debug SELF Address Register
- ***************************************************************************/
-/* HIF_CPUBIUCTRL :: CPU_DEBUGSELFADDR_REG :: DBGSELFADDR [31:11] */
-#define BCHP_HIF_CPUBIUCTRL_CPU_DEBUGSELFADDR_REG_DBGSELFADDR_MASK 0xfffff800
-#define BCHP_HIF_CPUBIUCTRL_CPU_DEBUGSELFADDR_REG_DBGSELFADDR_SHIFT 11
-#define BCHP_HIF_CPUBIUCTRL_CPU_DEBUGSELFADDR_REG_DBGSELFADDR_DEFAULT 0x00000001
-
-/* HIF_CPUBIUCTRL :: CPU_DEBUGSELFADDR_REG :: reserved0 [10:01] */
-#define BCHP_HIF_CPUBIUCTRL_CPU_DEBUGSELFADDR_REG_reserved0_MASK 0x000007fe
-#define BCHP_HIF_CPUBIUCTRL_CPU_DEBUGSELFADDR_REG_reserved0_SHIFT 1
-
-/* HIF_CPUBIUCTRL :: CPU_DEBUGSELFADDR_REG :: DBGSELFADDRV [00:00] */
-#define BCHP_HIF_CPUBIUCTRL_CPU_DEBUGSELFADDR_REG_DBGSELFADDRV_MASK 0x00000001
-#define BCHP_HIF_CPUBIUCTRL_CPU_DEBUGSELFADDR_REG_DBGSELFADDRV_SHIFT 0
-#define BCHP_HIF_CPUBIUCTRL_CPU_DEBUGSELFADDR_REG_DBGSELFADDRV_DEFAULT 0x00000000
-
-/***************************************************************************
- *CPU_DEBUG_TRACECTRL_REG - CPU Debug Trace Control Register
- ***************************************************************************/
-/* HIF_CPUBIUCTRL :: CPU_DEBUG_TRACECTRL_REG :: reserved0 [31:05] */
-#define BCHP_HIF_CPUBIUCTRL_CPU_DEBUG_TRACECTRL_REG_reserved0_MASK 0xffffffe0
-#define BCHP_HIF_CPUBIUCTRL_CPU_DEBUG_TRACECTRL_REG_reserved0_SHIFT 5
-
-/* HIF_CPUBIUCTRL :: CPU_DEBUG_TRACECTRL_REG :: TPMAXDATASIZE [04:00] */
-#define BCHP_HIF_CPUBIUCTRL_CPU_DEBUG_TRACECTRL_REG_TPMAXDATASIZE_MASK 0x0000001f
-#define BCHP_HIF_CPUBIUCTRL_CPU_DEBUG_TRACECTRL_REG_TPMAXDATASIZE_SHIFT 0
-#define BCHP_HIF_CPUBIUCTRL_CPU_DEBUG_TRACECTRL_REG_TPMAXDATASIZE_DEFAULT 0x00000003
-
-/***************************************************************************
- *CPU_AXICONFIG_REG - CPU AXI Config Register
- ***************************************************************************/
-/* HIF_CPUBIUCTRL :: CPU_AXICONFIG_REG :: reserved0 [31:04] */
-#define BCHP_HIF_CPUBIUCTRL_CPU_AXICONFIG_REG_reserved0_MASK 0xfffffff0
-#define BCHP_HIF_CPUBIUCTRL_CPU_AXICONFIG_REG_reserved0_SHIFT 4
-
-/* HIF_CPUBIUCTRL :: CPU_AXICONFIG_REG :: BROADCASTINNER [03:03] */
-#define BCHP_HIF_CPUBIUCTRL_CPU_AXICONFIG_REG_BROADCASTINNER_MASK 0x00000008
-#define BCHP_HIF_CPUBIUCTRL_CPU_AXICONFIG_REG_BROADCASTINNER_SHIFT 3
-#define BCHP_HIF_CPUBIUCTRL_CPU_AXICONFIG_REG_BROADCASTINNER_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: CPU_AXICONFIG_REG :: BROADCASTOUTER [02:02] */
-#define BCHP_HIF_CPUBIUCTRL_CPU_AXICONFIG_REG_BROADCASTOUTER_MASK 0x00000004
-#define BCHP_HIF_CPUBIUCTRL_CPU_AXICONFIG_REG_BROADCASTOUTER_SHIFT 2
-#define BCHP_HIF_CPUBIUCTRL_CPU_AXICONFIG_REG_BROADCASTOUTER_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: CPU_AXICONFIG_REG :: BROADCASTCACHEMAINT [01:01] */
-#define BCHP_HIF_CPUBIUCTRL_CPU_AXICONFIG_REG_BROADCASTCACHEMAINT_MASK 0x00000002
-#define BCHP_HIF_CPUBIUCTRL_CPU_AXICONFIG_REG_BROADCASTCACHEMAINT_SHIFT 1
-#define BCHP_HIF_CPUBIUCTRL_CPU_AXICONFIG_REG_BROADCASTCACHEMAINT_DEFAULT 0x00000001
-
-/* HIF_CPUBIUCTRL :: CPU_AXICONFIG_REG :: SYSBARDISABLE [00:00] */
-#define BCHP_HIF_CPUBIUCTRL_CPU_AXICONFIG_REG_SYSBARDISABLE_MASK 0x00000001
-#define BCHP_HIF_CPUBIUCTRL_CPU_AXICONFIG_REG_SYSBARDISABLE_SHIFT 0
-#define BCHP_HIF_CPUBIUCTRL_CPU_AXICONFIG_REG_SYSBARDISABLE_DEFAULT 0x00000000
-
-/***************************************************************************
- *CPU_REVISION_REG - CPU Revision Register
- ***************************************************************************/
-/* HIF_CPUBIUCTRL :: CPU_REVISION_REG :: reserved0 [31:08] */
-#define BCHP_HIF_CPUBIUCTRL_CPU_REVISION_REG_reserved0_MASK 0xffffff00
-#define BCHP_HIF_CPUBIUCTRL_CPU_REVISION_REG_reserved0_SHIFT 8
-
-/* HIF_CPUBIUCTRL :: CPU_REVISION_REG :: MAJOR_REV [07:04] */
-#define BCHP_HIF_CPUBIUCTRL_CPU_REVISION_REG_MAJOR_REV_MASK 0x000000f0
-#define BCHP_HIF_CPUBIUCTRL_CPU_REVISION_REG_MAJOR_REV_SHIFT 4
-#define BCHP_HIF_CPUBIUCTRL_CPU_REVISION_REG_MAJOR_REV_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: CPU_REVISION_REG :: MINOR_REV [03:00] */
-#define BCHP_HIF_CPUBIUCTRL_CPU_REVISION_REG_MINOR_REV_MASK 0x0000000f
-#define BCHP_HIF_CPUBIUCTRL_CPU_REVISION_REG_MINOR_REV_SHIFT 0
-#define BCHP_HIF_CPUBIUCTRL_CPU_REVISION_REG_MINOR_REV_DEFAULT 0x00000001
-
-/***************************************************************************
- *CPU_UBUS_CFGWINDOW0 - UBUS CFG Window0 Register
- ***************************************************************************/
-/* HIF_CPUBIUCTRL :: CPU_UBUS_CFGWINDOW0 :: cfg_window [31:00] */
-#define BCHP_HIF_CPUBIUCTRL_CPU_UBUS_CFGWINDOW0_cfg_window_MASK 0xffffffff
-#define BCHP_HIF_CPUBIUCTRL_CPU_UBUS_CFGWINDOW0_cfg_window_SHIFT 0
-#define BCHP_HIF_CPUBIUCTRL_CPU_UBUS_CFGWINDOW0_cfg_window_DEFAULT 0x00000000
-
-/***************************************************************************
- *CPU_UBUS_CFGWINDOW1 - UBUS CFG Window1 Register
- ***************************************************************************/
-/* HIF_CPUBIUCTRL :: CPU_UBUS_CFGWINDOW1 :: cfg_window [31:00] */
-#define BCHP_HIF_CPUBIUCTRL_CPU_UBUS_CFGWINDOW1_cfg_window_MASK 0xffffffff
-#define BCHP_HIF_CPUBIUCTRL_CPU_UBUS_CFGWINDOW1_cfg_window_SHIFT 0
-#define BCHP_HIF_CPUBIUCTRL_CPU_UBUS_CFGWINDOW1_cfg_window_DEFAULT 0x00000000
-
-/***************************************************************************
- *CPU_UBUS_CFGWINDOW2 - UBUS CFG Window2 Register
- ***************************************************************************/
-/* HIF_CPUBIUCTRL :: CPU_UBUS_CFGWINDOW2 :: cfg_window [31:00] */
-#define BCHP_HIF_CPUBIUCTRL_CPU_UBUS_CFGWINDOW2_cfg_window_MASK 0xffffffff
-#define BCHP_HIF_CPUBIUCTRL_CPU_UBUS_CFGWINDOW2_cfg_window_SHIFT 0
-#define BCHP_HIF_CPUBIUCTRL_CPU_UBUS_CFGWINDOW2_cfg_window_DEFAULT 0x00000000
-
-/***************************************************************************
- *CPU_UBUS_CFGWINDOW3 - UBUS CFG Window3 Register
- ***************************************************************************/
-/* HIF_CPUBIUCTRL :: CPU_UBUS_CFGWINDOW3 :: cfg_window [31:00] */
-#define BCHP_HIF_CPUBIUCTRL_CPU_UBUS_CFGWINDOW3_cfg_window_MASK 0xffffffff
-#define BCHP_HIF_CPUBIUCTRL_CPU_UBUS_CFGWINDOW3_cfg_window_SHIFT 0
-#define BCHP_HIF_CPUBIUCTRL_CPU_UBUS_CFGWINDOW3_cfg_window_DEFAULT 0x00000000
-
-/***************************************************************************
- *CPU_UBUS_CFGWINDOW4 - UBUS CFG Window4 Register
- ***************************************************************************/
-/* HIF_CPUBIUCTRL :: CPU_UBUS_CFGWINDOW4 :: cfg_window [31:00] */
-#define BCHP_HIF_CPUBIUCTRL_CPU_UBUS_CFGWINDOW4_cfg_window_MASK 0xffffffff
-#define BCHP_HIF_CPUBIUCTRL_CPU_UBUS_CFGWINDOW4_cfg_window_SHIFT 0
-#define BCHP_HIF_CPUBIUCTRL_CPU_UBUS_CFGWINDOW4_cfg_window_DEFAULT 0x00000000
-
-/***************************************************************************
- *CPU_UBUS_CFGWINDOW5 - UBUS CFG Window5 Register
- ***************************************************************************/
-/* HIF_CPUBIUCTRL :: CPU_UBUS_CFGWINDOW5 :: cfg_window [31:00] */
-#define BCHP_HIF_CPUBIUCTRL_CPU_UBUS_CFGWINDOW5_cfg_window_MASK 0xffffffff
-#define BCHP_HIF_CPUBIUCTRL_CPU_UBUS_CFGWINDOW5_cfg_window_SHIFT 0
-#define BCHP_HIF_CPUBIUCTRL_CPU_UBUS_CFGWINDOW5_cfg_window_DEFAULT 0x00000000
-
-/***************************************************************************
- *CPU_UBUS_CFGWINDOW6 - UBUS CFG Window6 Register
- ***************************************************************************/
-/* HIF_CPUBIUCTRL :: CPU_UBUS_CFGWINDOW6 :: cfg_window [31:00] */
-#define BCHP_HIF_CPUBIUCTRL_CPU_UBUS_CFGWINDOW6_cfg_window_MASK 0xffffffff
-#define BCHP_HIF_CPUBIUCTRL_CPU_UBUS_CFGWINDOW6_cfg_window_SHIFT 0
-#define BCHP_HIF_CPUBIUCTRL_CPU_UBUS_CFGWINDOW6_cfg_window_DEFAULT 0x00000000
-
-/***************************************************************************
- *CPU_UBUS_CFGWINDOW7 - UBUS CFG Window7 Register
- ***************************************************************************/
-/* HIF_CPUBIUCTRL :: CPU_UBUS_CFGWINDOW7 :: cfg_window [31:00] */
-#define BCHP_HIF_CPUBIUCTRL_CPU_UBUS_CFGWINDOW7_cfg_window_MASK 0xffffffff
-#define BCHP_HIF_CPUBIUCTRL_CPU_UBUS_CFGWINDOW7_cfg_window_SHIFT 0
-#define BCHP_HIF_CPUBIUCTRL_CPU_UBUS_CFGWINDOW7_cfg_window_DEFAULT 0x00000000
-
-/***************************************************************************
- *CPU_UBUS_CONFIG - UBUS Configuration Register
- ***************************************************************************/
-/* HIF_CPUBIUCTRL :: CPU_UBUS_CONFIG :: reserved0 [31:08] */
-#define BCHP_HIF_CPUBIUCTRL_CPU_UBUS_CONFIG_reserved0_MASK 0xffffff00
-#define BCHP_HIF_CPUBIUCTRL_CPU_UBUS_CONFIG_reserved0_SHIFT 8
-
-/* HIF_CPUBIUCTRL :: CPU_UBUS_CONFIG :: Uniq_pid_enable [07:07] */
-#define BCHP_HIF_CPUBIUCTRL_CPU_UBUS_CONFIG_Uniq_pid_enable_MASK 0x00000080
-#define BCHP_HIF_CPUBIUCTRL_CPU_UBUS_CONFIG_Uniq_pid_enable_SHIFT 7
-#define BCHP_HIF_CPUBIUCTRL_CPU_UBUS_CONFIG_Uniq_pid_enable_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: CPU_UBUS_CONFIG :: Ubus_Dev_fast_wr [06:06] */
-#define BCHP_HIF_CPUBIUCTRL_CPU_UBUS_CONFIG_Ubus_Dev_fast_wr_MASK 0x00000040
-#define BCHP_HIF_CPUBIUCTRL_CPU_UBUS_CONFIG_Ubus_Dev_fast_wr_SHIFT 6
-#define BCHP_HIF_CPUBIUCTRL_CPU_UBUS_CONFIG_Ubus_Dev_fast_wr_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: CPU_UBUS_CONFIG :: Ubus_Dev_fast_rd [05:05] */
-#define BCHP_HIF_CPUBIUCTRL_CPU_UBUS_CONFIG_Ubus_Dev_fast_rd_MASK 0x00000020
-#define BCHP_HIF_CPUBIUCTRL_CPU_UBUS_CONFIG_Ubus_Dev_fast_rd_SHIFT 5
-#define BCHP_HIF_CPUBIUCTRL_CPU_UBUS_CONFIG_Ubus_Dev_fast_rd_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: CPU_UBUS_CONFIG :: wr_with_ack_enable [04:04] */
-#define BCHP_HIF_CPUBIUCTRL_CPU_UBUS_CONFIG_wr_with_ack_enable_MASK 0x00000010
-#define BCHP_HIF_CPUBIUCTRL_CPU_UBUS_CONFIG_wr_with_ack_enable_SHIFT 4
-#define BCHP_HIF_CPUBIUCTRL_CPU_UBUS_CONFIG_wr_with_ack_enable_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: CPU_UBUS_CONFIG :: cd_ctrl [03:00] */
-#define BCHP_HIF_CPUBIUCTRL_CPU_UBUS_CONFIG_cd_ctrl_MASK 0x0000000f
-#define BCHP_HIF_CPUBIUCTRL_CPU_UBUS_CONFIG_cd_ctrl_SHIFT 0
-#define BCHP_HIF_CPUBIUCTRL_CPU_UBUS_CONFIG_cd_ctrl_DEFAULT 0x00000004
-
-/***************************************************************************
- *CPU_SCRATCH_REG - Scratch Register
- ***************************************************************************/
-/* HIF_CPUBIUCTRL :: CPU_SCRATCH_REG :: scratch [31:00] */
-#define BCHP_HIF_CPUBIUCTRL_CPU_SCRATCH_REG_scratch_MASK 0xffffffff
-#define BCHP_HIF_CPUBIUCTRL_CPU_SCRATCH_REG_scratch_SHIFT 0
-#define BCHP_HIF_CPUBIUCTRL_CPU_SCRATCH_REG_scratch_DEFAULT 0x00000000
-
-#endif /* #ifndef BCHP_HIF_CPUBIUCTRL_H__ */
-
-/* End of File */
diff --git a/include/linux/brcmstb/7366b0/bchp_hif_intr2.h b/include/linux/brcmstb/7366b0/bchp_hif_intr2.h
deleted file mode 100644
index 1f2e40f..0000000
--- a/include/linux/brcmstb/7366b0/bchp_hif_intr2.h
+++ /dev/null
@@ -1,1610 +0,0 @@
-/***************************************************************************
- * Copyright (c) 1999-2014, Broadcom Corporation
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
- *
- * Module Description:
- * DO NOT EDIT THIS FILE DIRECTLY
- *
- * This module was generated magically with RDB from a source description
- * file. You must edit the source file for changes to be made to this file.
- *
- *
- * Date: Generated on Thu Apr 24 03:08:55 2014
- * Full Compile MD5 Checksum 1af2c2cf28828ece5496e1312aac0166
- * (minus title and desc)
- * MD5 Checksum 3203ffce85e3fc9a10f84123e54057b0
- *
- * Compiled with: RDB Utility combo_header.pl
- * RDB Parser 3.0
- * unknown unknown
- * Perl Interpreter 5.008008
- * Operating System linux
- *
- * Revision History:
- *
- * $brcm_Log: $
- *
- ***************************************************************************/
-
-#ifndef BCHP_HIF_INTR2_H__
-#define BCHP_HIF_INTR2_H__
-
-/***************************************************************************
- *HIF_INTR2 - HIF Level 2 Interrupt Controller Registers
- ***************************************************************************/
-#define BCHP_HIF_INTR2_CPU_STATUS 0x00441000 /* CPU interrupt Status Register */
-#define BCHP_HIF_INTR2_CPU_SET 0x00441004 /* CPU interrupt Set Register */
-#define BCHP_HIF_INTR2_CPU_CLEAR 0x00441008 /* CPU interrupt Clear Register */
-#define BCHP_HIF_INTR2_CPU_MASK_STATUS 0x0044100c /* CPU interrupt Mask Status Register */
-#define BCHP_HIF_INTR2_CPU_MASK_SET 0x00441010 /* CPU interrupt Mask Set Register */
-#define BCHP_HIF_INTR2_CPU_MASK_CLEAR 0x00441014 /* CPU interrupt Mask Clear Register */
-#define BCHP_HIF_INTR2_PCI_STATUS 0x00441018 /* PCI interrupt Status Register */
-#define BCHP_HIF_INTR2_PCI_SET 0x0044101c /* PCI interrupt Set Register */
-#define BCHP_HIF_INTR2_PCI_CLEAR 0x00441020 /* PCI interrupt Clear Register */
-#define BCHP_HIF_INTR2_PCI_MASK_STATUS 0x00441024 /* PCI interrupt Mask Status Register */
-#define BCHP_HIF_INTR2_PCI_MASK_SET 0x00441028 /* PCI interrupt Mask Set Register */
-#define BCHP_HIF_INTR2_PCI_MASK_CLEAR 0x0044102c /* PCI interrupt Mask Clear Register */
-
-/***************************************************************************
- *CPU_STATUS - CPU interrupt Status Register
- ***************************************************************************/
-/* HIF_INTR2 :: CPU_STATUS :: PCIE_0_LINKDOWN_INTR [31:31] */
-#define BCHP_HIF_INTR2_CPU_STATUS_PCIE_0_LINKDOWN_INTR_MASK 0x80000000
-#define BCHP_HIF_INTR2_CPU_STATUS_PCIE_0_LINKDOWN_INTR_SHIFT 31
-#define BCHP_HIF_INTR2_CPU_STATUS_PCIE_0_LINKDOWN_INTR_DEFAULT 0x00000000
-
-/* HIF_INTR2 :: CPU_STATUS :: PCIE_0_LINKUP_INTR [30:30] */
-#define BCHP_HIF_INTR2_CPU_STATUS_PCIE_0_LINKUP_INTR_MASK 0x40000000
-#define BCHP_HIF_INTR2_CPU_STATUS_PCIE_0_LINKUP_INTR_SHIFT 30
-#define BCHP_HIF_INTR2_CPU_STATUS_PCIE_0_LINKUP_INTR_DEFAULT 0x00000000
-
-/* HIF_INTR2 :: CPU_STATUS :: PCIE_1_LINKDOWN_INTR [29:29] */
-#define BCHP_HIF_INTR2_CPU_STATUS_PCIE_1_LINKDOWN_INTR_MASK 0x20000000
-#define BCHP_HIF_INTR2_CPU_STATUS_PCIE_1_LINKDOWN_INTR_SHIFT 29
-#define BCHP_HIF_INTR2_CPU_STATUS_PCIE_1_LINKDOWN_INTR_DEFAULT 0x00000000
-
-/* HIF_INTR2 :: CPU_STATUS :: PCIE_1_LINKUP_INTR [28:28] */
-#define BCHP_HIF_INTR2_CPU_STATUS_PCIE_1_LINKUP_INTR_MASK 0x10000000
-#define BCHP_HIF_INTR2_CPU_STATUS_PCIE_1_LINKUP_INTR_SHIFT 28
-#define BCHP_HIF_INTR2_CPU_STATUS_PCIE_1_LINKUP_INTR_DEFAULT 0x00000000
-
-/* HIF_INTR2 :: CPU_STATUS :: NAND_CORR_INTR [27:27] */
-#define BCHP_HIF_INTR2_CPU_STATUS_NAND_CORR_INTR_MASK 0x08000000
-#define BCHP_HIF_INTR2_CPU_STATUS_NAND_CORR_INTR_SHIFT 27
-#define BCHP_HIF_INTR2_CPU_STATUS_NAND_CORR_INTR_DEFAULT 0x00000000
-
-/* HIF_INTR2 :: CPU_STATUS :: NAND_UNC_INTR [26:26] */
-#define BCHP_HIF_INTR2_CPU_STATUS_NAND_UNC_INTR_MASK 0x04000000
-#define BCHP_HIF_INTR2_CPU_STATUS_NAND_UNC_INTR_SHIFT 26
-#define BCHP_HIF_INTR2_CPU_STATUS_NAND_UNC_INTR_DEFAULT 0x00000000
-
-/* HIF_INTR2 :: CPU_STATUS :: NAND_RBPIN_INTR [25:25] */
-#define BCHP_HIF_INTR2_CPU_STATUS_NAND_RBPIN_INTR_MASK 0x02000000
-#define BCHP_HIF_INTR2_CPU_STATUS_NAND_RBPIN_INTR_SHIFT 25
-#define BCHP_HIF_INTR2_CPU_STATUS_NAND_RBPIN_INTR_DEFAULT 0x00000000
-
-/* HIF_INTR2 :: CPU_STATUS :: NAND_CTLRDY_INTR [24:24] */
-#define BCHP_HIF_INTR2_CPU_STATUS_NAND_CTLRDY_INTR_MASK 0x01000000
-#define BCHP_HIF_INTR2_CPU_STATUS_NAND_CTLRDY_INTR_SHIFT 24
-#define BCHP_HIF_INTR2_CPU_STATUS_NAND_CTLRDY_INTR_DEFAULT 0x00000000
-
-/* HIF_INTR2 :: CPU_STATUS :: NAND_PGMPG_INTR [23:23] */
-#define BCHP_HIF_INTR2_CPU_STATUS_NAND_PGMPG_INTR_MASK 0x00800000
-#define BCHP_HIF_INTR2_CPU_STATUS_NAND_PGMPG_INTR_SHIFT 23
-#define BCHP_HIF_INTR2_CPU_STATUS_NAND_PGMPG_INTR_DEFAULT 0x00000000
-
-/* HIF_INTR2 :: CPU_STATUS :: NAND_CPYBK_INTR [22:22] */
-#define BCHP_HIF_INTR2_CPU_STATUS_NAND_CPYBK_INTR_MASK 0x00400000
-#define BCHP_HIF_INTR2_CPU_STATUS_NAND_CPYBK_INTR_SHIFT 22
-#define BCHP_HIF_INTR2_CPU_STATUS_NAND_CPYBK_INTR_DEFAULT 0x00000000
-
-/* HIF_INTR2 :: CPU_STATUS :: NAND_BLKERA_INTR [21:21] */
-#define BCHP_HIF_INTR2_CPU_STATUS_NAND_BLKERA_INTR_MASK 0x00200000
-#define BCHP_HIF_INTR2_CPU_STATUS_NAND_BLKERA_INTR_SHIFT 21
-#define BCHP_HIF_INTR2_CPU_STATUS_NAND_BLKERA_INTR_DEFAULT 0x00000000
-
-/* HIF_INTR2 :: CPU_STATUS :: NAND_NP_READ_INTR [20:20] */
-#define BCHP_HIF_INTR2_CPU_STATUS_NAND_NP_READ_INTR_MASK 0x00100000
-#define BCHP_HIF_INTR2_CPU_STATUS_NAND_NP_READ_INTR_SHIFT 20
-#define BCHP_HIF_INTR2_CPU_STATUS_NAND_NP_READ_INTR_DEFAULT 0x00000000
-
-/* HIF_INTR2 :: CPU_STATUS :: reserved0 [19:16] */
-#define BCHP_HIF_INTR2_CPU_STATUS_reserved0_MASK 0x000f0000
-#define BCHP_HIF_INTR2_CPU_STATUS_reserved0_SHIFT 16
-
-/* HIF_INTR2 :: CPU_STATUS :: ITCH0_RD_INTR [15:15] */
-#define BCHP_HIF_INTR2_CPU_STATUS_ITCH0_RD_INTR_MASK 0x00008000
-#define BCHP_HIF_INTR2_CPU_STATUS_ITCH0_RD_INTR_SHIFT 15
-#define BCHP_HIF_INTR2_CPU_STATUS_ITCH0_RD_INTR_DEFAULT 0x00000000
-
-/* HIF_INTR2 :: CPU_STATUS :: reserved1 [14:14] */
-#define BCHP_HIF_INTR2_CPU_STATUS_reserved1_MASK 0x00004000
-#define BCHP_HIF_INTR2_CPU_STATUS_reserved1_SHIFT 14
-
-/* HIF_INTR2 :: CPU_STATUS :: PCIE_0_RG_BRIDGE_INTR [13:13] */
-#define BCHP_HIF_INTR2_CPU_STATUS_PCIE_0_RG_BRIDGE_INTR_MASK 0x00002000
-#define BCHP_HIF_INTR2_CPU_STATUS_PCIE_0_RG_BRIDGE_INTR_SHIFT 13
-#define BCHP_HIF_INTR2_CPU_STATUS_PCIE_0_RG_BRIDGE_INTR_DEFAULT 0x00000000
-
-/* HIF_INTR2 :: CPU_STATUS :: PCIE_0_RGR_BRIDGE_INTR [12:12] */
-#define BCHP_HIF_INTR2_CPU_STATUS_PCIE_0_RGR_BRIDGE_INTR_MASK 0x00001000
-#define BCHP_HIF_INTR2_CPU_STATUS_PCIE_0_RGR_BRIDGE_INTR_SHIFT 12
-#define BCHP_HIF_INTR2_CPU_STATUS_PCIE_0_RGR_BRIDGE_INTR_DEFAULT 0x00000000
-
-/* HIF_INTR2 :: CPU_STATUS :: PCIE_1_RG_BRIDGE_INTR [11:11] */
-#define BCHP_HIF_INTR2_CPU_STATUS_PCIE_1_RG_BRIDGE_INTR_MASK 0x00000800
-#define BCHP_HIF_INTR2_CPU_STATUS_PCIE_1_RG_BRIDGE_INTR_SHIFT 11
-#define BCHP_HIF_INTR2_CPU_STATUS_PCIE_1_RG_BRIDGE_INTR_DEFAULT 0x00000000
-
-/* HIF_INTR2 :: CPU_STATUS :: PCIE_1_RGR_BRIDGE_INTR [10:10] */
-#define BCHP_HIF_INTR2_CPU_STATUS_PCIE_1_RGR_BRIDGE_INTR_MASK 0x00000400
-#define BCHP_HIF_INTR2_CPU_STATUS_PCIE_1_RGR_BRIDGE_INTR_SHIFT 10
-#define BCHP_HIF_INTR2_CPU_STATUS_PCIE_1_RGR_BRIDGE_INTR_DEFAULT 0x00000000
-
-/* HIF_INTR2 :: CPU_STATUS :: reserved2 [09:06] */
-#define BCHP_HIF_INTR2_CPU_STATUS_reserved2_MASK 0x000003c0
-#define BCHP_HIF_INTR2_CPU_STATUS_reserved2_SHIFT 6
-
-/* HIF_INTR2 :: CPU_STATUS :: FLASH_DMA_ERR_INTR [05:05] */
-#define BCHP_HIF_INTR2_CPU_STATUS_FLASH_DMA_ERR_INTR_MASK 0x00000020
-#define BCHP_HIF_INTR2_CPU_STATUS_FLASH_DMA_ERR_INTR_SHIFT 5
-#define BCHP_HIF_INTR2_CPU_STATUS_FLASH_DMA_ERR_INTR_DEFAULT 0x00000000
-
-/* HIF_INTR2 :: CPU_STATUS :: FLASH_DMA_DONE_INTR [04:04] */
-#define BCHP_HIF_INTR2_CPU_STATUS_FLASH_DMA_DONE_INTR_MASK 0x00000010
-#define BCHP_HIF_INTR2_CPU_STATUS_FLASH_DMA_DONE_INTR_SHIFT 4
-#define BCHP_HIF_INTR2_CPU_STATUS_FLASH_DMA_DONE_INTR_DEFAULT 0x00000000
-
-/* HIF_INTR2 :: CPU_STATUS :: WEBHIF_WD_TIMEOUT_INTR [03:03] */
-#define BCHP_HIF_INTR2_CPU_STATUS_WEBHIF_WD_TIMEOUT_INTR_MASK 0x00000008
-#define BCHP_HIF_INTR2_CPU_STATUS_WEBHIF_WD_TIMEOUT_INTR_SHIFT 3
-#define BCHP_HIF_INTR2_CPU_STATUS_WEBHIF_WD_TIMEOUT_INTR_DEFAULT 0x00000000
-
-/* HIF_INTR2 :: CPU_STATUS :: reserved3 [02:02] */
-#define BCHP_HIF_INTR2_CPU_STATUS_reserved3_MASK 0x00000004
-#define BCHP_HIF_INTR2_CPU_STATUS_reserved3_SHIFT 2
-
-/* HIF_INTR2 :: CPU_STATUS :: ITCH1_RD_INTR [01:01] */
-#define BCHP_HIF_INTR2_CPU_STATUS_ITCH1_RD_INTR_MASK 0x00000002
-#define BCHP_HIF_INTR2_CPU_STATUS_ITCH1_RD_INTR_SHIFT 1
-#define BCHP_HIF_INTR2_CPU_STATUS_ITCH1_RD_INTR_DEFAULT 0x00000000
-
-/* HIF_INTR2 :: CPU_STATUS :: HIF_RGR2_BRIDGE_INTR [00:00] */
-#define BCHP_HIF_INTR2_CPU_STATUS_HIF_RGR2_BRIDGE_INTR_MASK 0x00000001
-#define BCHP_HIF_INTR2_CPU_STATUS_HIF_RGR2_BRIDGE_INTR_SHIFT 0
-#define BCHP_HIF_INTR2_CPU_STATUS_HIF_RGR2_BRIDGE_INTR_DEFAULT 0x00000000
-
-/***************************************************************************
- *CPU_SET - CPU interrupt Set Register
- ***************************************************************************/
-/* HIF_INTR2 :: CPU_SET :: PCIE_0_LINKDOWN_INTR [31:31] */
-#define BCHP_HIF_INTR2_CPU_SET_PCIE_0_LINKDOWN_INTR_MASK 0x80000000
-#define BCHP_HIF_INTR2_CPU_SET_PCIE_0_LINKDOWN_INTR_SHIFT 31
-#define BCHP_HIF_INTR2_CPU_SET_PCIE_0_LINKDOWN_INTR_DEFAULT 0x00000000
-
-/* HIF_INTR2 :: CPU_SET :: PCIE_0_LINKUP_INTR [30:30] */
-#define BCHP_HIF_INTR2_CPU_SET_PCIE_0_LINKUP_INTR_MASK 0x40000000
-#define BCHP_HIF_INTR2_CPU_SET_PCIE_0_LINKUP_INTR_SHIFT 30
-#define BCHP_HIF_INTR2_CPU_SET_PCIE_0_LINKUP_INTR_DEFAULT 0x00000000
-
-/* HIF_INTR2 :: CPU_SET :: PCIE_1_LINKDOWN_INTR [29:29] */
-#define BCHP_HIF_INTR2_CPU_SET_PCIE_1_LINKDOWN_INTR_MASK 0x20000000
-#define BCHP_HIF_INTR2_CPU_SET_PCIE_1_LINKDOWN_INTR_SHIFT 29
-#define BCHP_HIF_INTR2_CPU_SET_PCIE_1_LINKDOWN_INTR_DEFAULT 0x00000000
-
-/* HIF_INTR2 :: CPU_SET :: PCIE_1_LINKUP_INTR [28:28] */
-#define BCHP_HIF_INTR2_CPU_SET_PCIE_1_LINKUP_INTR_MASK 0x10000000
-#define BCHP_HIF_INTR2_CPU_SET_PCIE_1_LINKUP_INTR_SHIFT 28
-#define BCHP_HIF_INTR2_CPU_SET_PCIE_1_LINKUP_INTR_DEFAULT 0x00000000
-
-/* HIF_INTR2 :: CPU_SET :: NAND_CORR_INTR [27:27] */
-#define BCHP_HIF_INTR2_CPU_SET_NAND_CORR_INTR_MASK 0x08000000
-#define BCHP_HIF_INTR2_CPU_SET_NAND_CORR_INTR_SHIFT 27
-#define BCHP_HIF_INTR2_CPU_SET_NAND_CORR_INTR_DEFAULT 0x00000000
-
-/* HIF_INTR2 :: CPU_SET :: NAND_UNC_INTR [26:26] */
-#define BCHP_HIF_INTR2_CPU_SET_NAND_UNC_INTR_MASK 0x04000000
-#define BCHP_HIF_INTR2_CPU_SET_NAND_UNC_INTR_SHIFT 26
-#define BCHP_HIF_INTR2_CPU_SET_NAND_UNC_INTR_DEFAULT 0x00000000
-
-/* HIF_INTR2 :: CPU_SET :: NAND_RBPIN_INTR [25:25] */
-#define BCHP_HIF_INTR2_CPU_SET_NAND_RBPIN_INTR_MASK 0x02000000
-#define BCHP_HIF_INTR2_CPU_SET_NAND_RBPIN_INTR_SHIFT 25
-#define BCHP_HIF_INTR2_CPU_SET_NAND_RBPIN_INTR_DEFAULT 0x00000000
-
-/* HIF_INTR2 :: CPU_SET :: NAND_CTLRDY_INTR [24:24] */
-#define BCHP_HIF_INTR2_CPU_SET_NAND_CTLRDY_INTR_MASK 0x01000000
-#define BCHP_HIF_INTR2_CPU_SET_NAND_CTLRDY_INTR_SHIFT 24
-#define BCHP_HIF_INTR2_CPU_SET_NAND_CTLRDY_INTR_DEFAULT 0x00000000
-
-/* HIF_INTR2 :: CPU_SET :: NAND_PGMPG_INTR [23:23] */
-#define BCHP_HIF_INTR2_CPU_SET_NAND_PGMPG_INTR_MASK 0x00800000
-#define BCHP_HIF_INTR2_CPU_SET_NAND_PGMPG_INTR_SHIFT 23
-#define BCHP_HIF_INTR2_CPU_SET_NAND_PGMPG_INTR_DEFAULT 0x00000000
-
-/* HIF_INTR2 :: CPU_SET :: NAND_CPYBK_INTR [22:22] */
-#define BCHP_HIF_INTR2_CPU_SET_NAND_CPYBK_INTR_MASK 0x00400000
-#define BCHP_HIF_INTR2_CPU_SET_NAND_CPYBK_INTR_SHIFT 22
-#define BCHP_HIF_INTR2_CPU_SET_NAND_CPYBK_INTR_DEFAULT 0x00000000
-
-/* HIF_INTR2 :: CPU_SET :: NAND_BLKERA_INTR [21:21] */
-#define BCHP_HIF_INTR2_CPU_SET_NAND_BLKERA_INTR_MASK 0x00200000
-#define BCHP_HIF_INTR2_CPU_SET_NAND_BLKERA_INTR_SHIFT 21
-#define BCHP_HIF_INTR2_CPU_SET_NAND_BLKERA_INTR_DEFAULT 0x00000000
-
-/* HIF_INTR2 :: CPU_SET :: NAND_NP_READ_INTR [20:20] */
-#define BCHP_HIF_INTR2_CPU_SET_NAND_NP_READ_INTR_MASK 0x00100000
-#define BCHP_HIF_INTR2_CPU_SET_NAND_NP_READ_INTR_SHIFT 20
-#define BCHP_HIF_INTR2_CPU_SET_NAND_NP_READ_INTR_DEFAULT 0x00000000
-
-/* HIF_INTR2 :: CPU_SET :: reserved0 [19:16] */
-#define BCHP_HIF_INTR2_CPU_SET_reserved0_MASK 0x000f0000
-#define BCHP_HIF_INTR2_CPU_SET_reserved0_SHIFT 16
-
-/* HIF_INTR2 :: CPU_SET :: ITCH0_RD_INTR [15:15] */
-#define BCHP_HIF_INTR2_CPU_SET_ITCH0_RD_INTR_MASK 0x00008000
-#define BCHP_HIF_INTR2_CPU_SET_ITCH0_RD_INTR_SHIFT 15
-#define BCHP_HIF_INTR2_CPU_SET_ITCH0_RD_INTR_DEFAULT 0x00000000
-
-/* HIF_INTR2 :: CPU_SET :: reserved1 [14:14] */
-#define BCHP_HIF_INTR2_CPU_SET_reserved1_MASK 0x00004000
-#define BCHP_HIF_INTR2_CPU_SET_reserved1_SHIFT 14
-
-/* HIF_INTR2 :: CPU_SET :: PCIE_0_RG_BRIDGE_INTR [13:13] */
-#define BCHP_HIF_INTR2_CPU_SET_PCIE_0_RG_BRIDGE_INTR_MASK 0x00002000
-#define BCHP_HIF_INTR2_CPU_SET_PCIE_0_RG_BRIDGE_INTR_SHIFT 13
-#define BCHP_HIF_INTR2_CPU_SET_PCIE_0_RG_BRIDGE_INTR_DEFAULT 0x00000000
-
-/* HIF_INTR2 :: CPU_SET :: PCIE_0_RGR_BRIDGE_INTR [12:12] */
-#define BCHP_HIF_INTR2_CPU_SET_PCIE_0_RGR_BRIDGE_INTR_MASK 0x00001000
-#define BCHP_HIF_INTR2_CPU_SET_PCIE_0_RGR_BRIDGE_INTR_SHIFT 12
-#define BCHP_HIF_INTR2_CPU_SET_PCIE_0_RGR_BRIDGE_INTR_DEFAULT 0x00000000
-
-/* HIF_INTR2 :: CPU_SET :: PCIE_1_RG_BRIDGE_INTR [11:11] */
-#define BCHP_HIF_INTR2_CPU_SET_PCIE_1_RG_BRIDGE_INTR_MASK 0x00000800
-#define BCHP_HIF_INTR2_CPU_SET_PCIE_1_RG_BRIDGE_INTR_SHIFT 11
-#define BCHP_HIF_INTR2_CPU_SET_PCIE_1_RG_BRIDGE_INTR_DEFAULT 0x00000000
-
-/* HIF_INTR2 :: CPU_SET :: PCIE_1_RGR_BRIDGE_INTR [10:10] */
-#define BCHP_HIF_INTR2_CPU_SET_PCIE_1_RGR_BRIDGE_INTR_MASK 0x00000400
-#define BCHP_HIF_INTR2_CPU_SET_PCIE_1_RGR_BRIDGE_INTR_SHIFT 10
-#define BCHP_HIF_INTR2_CPU_SET_PCIE_1_RGR_BRIDGE_INTR_DEFAULT 0x00000000
-
-/* HIF_INTR2 :: CPU_SET :: reserved2 [09:06] */
-#define BCHP_HIF_INTR2_CPU_SET_reserved2_MASK 0x000003c0
-#define BCHP_HIF_INTR2_CPU_SET_reserved2_SHIFT 6
-
-/* HIF_INTR2 :: CPU_SET :: FLASH_DMA_ERR_INTR [05:05] */
-#define BCHP_HIF_INTR2_CPU_SET_FLASH_DMA_ERR_INTR_MASK 0x00000020
-#define BCHP_HIF_INTR2_CPU_SET_FLASH_DMA_ERR_INTR_SHIFT 5
-#define BCHP_HIF_INTR2_CPU_SET_FLASH_DMA_ERR_INTR_DEFAULT 0x00000000
-
-/* HIF_INTR2 :: CPU_SET :: FLASH_DMA_DONE_INTR [04:04] */
-#define BCHP_HIF_INTR2_CPU_SET_FLASH_DMA_DONE_INTR_MASK 0x00000010
-#define BCHP_HIF_INTR2_CPU_SET_FLASH_DMA_DONE_INTR_SHIFT 4
-#define BCHP_HIF_INTR2_CPU_SET_FLASH_DMA_DONE_INTR_DEFAULT 0x00000000
-
-/* HIF_INTR2 :: CPU_SET :: WEBHIF_WD_TIMEOUT_INTR [03:03] */
-#define BCHP_HIF_INTR2_CPU_SET_WEBHIF_WD_TIMEOUT_INTR_MASK 0x00000008
-#define BCHP_HIF_INTR2_CPU_SET_WEBHIF_WD_TIMEOUT_INTR_SHIFT 3
-#define BCHP_HIF_INTR2_CPU_SET_WEBHIF_WD_TIMEOUT_INTR_DEFAULT 0x00000000
-
-/* HIF_INTR2 :: CPU_SET :: reserved3 [02:02] */
-#define BCHP_HIF_INTR2_CPU_SET_reserved3_MASK 0x00000004
-#define BCHP_HIF_INTR2_CPU_SET_reserved3_SHIFT 2
-
-/* HIF_INTR2 :: CPU_SET :: ITCH1_RD_INTR [01:01] */
-#define BCHP_HIF_INTR2_CPU_SET_ITCH1_RD_INTR_MASK 0x00000002
-#define BCHP_HIF_INTR2_CPU_SET_ITCH1_RD_INTR_SHIFT 1
-#define BCHP_HIF_INTR2_CPU_SET_ITCH1_RD_INTR_DEFAULT 0x00000000
-
-/* HIF_INTR2 :: CPU_SET :: HIF_RGR2_BRIDGE_INTR [00:00] */
-#define BCHP_HIF_INTR2_CPU_SET_HIF_RGR2_BRIDGE_INTR_MASK 0x00000001
-#define BCHP_HIF_INTR2_CPU_SET_HIF_RGR2_BRIDGE_INTR_SHIFT 0
-#define BCHP_HIF_INTR2_CPU_SET_HIF_RGR2_BRIDGE_INTR_DEFAULT 0x00000000
-
-/***************************************************************************
- *CPU_CLEAR - CPU interrupt Clear Register
- ***************************************************************************/
-/* HIF_INTR2 :: CPU_CLEAR :: PCIE_0_LINKDOWN_INTR [31:31] */
-#define BCHP_HIF_INTR2_CPU_CLEAR_PCIE_0_LINKDOWN_INTR_MASK 0x80000000
-#define BCHP_HIF_INTR2_CPU_CLEAR_PCIE_0_LINKDOWN_INTR_SHIFT 31
-#define BCHP_HIF_INTR2_CPU_CLEAR_PCIE_0_LINKDOWN_INTR_DEFAULT 0x00000000
-
-/* HIF_INTR2 :: CPU_CLEAR :: PCIE_0_LINKUP_INTR [30:30] */
-#define BCHP_HIF_INTR2_CPU_CLEAR_PCIE_0_LINKUP_INTR_MASK 0x40000000
-#define BCHP_HIF_INTR2_CPU_CLEAR_PCIE_0_LINKUP_INTR_SHIFT 30
-#define BCHP_HIF_INTR2_CPU_CLEAR_PCIE_0_LINKUP_INTR_DEFAULT 0x00000000
-
-/* HIF_INTR2 :: CPU_CLEAR :: PCIE_1_LINKDOWN_INTR [29:29] */
-#define BCHP_HIF_INTR2_CPU_CLEAR_PCIE_1_LINKDOWN_INTR_MASK 0x20000000
-#define BCHP_HIF_INTR2_CPU_CLEAR_PCIE_1_LINKDOWN_INTR_SHIFT 29
-#define BCHP_HIF_INTR2_CPU_CLEAR_PCIE_1_LINKDOWN_INTR_DEFAULT 0x00000000
-
-/* HIF_INTR2 :: CPU_CLEAR :: PCIE_1_LINKUP_INTR [28:28] */
-#define BCHP_HIF_INTR2_CPU_CLEAR_PCIE_1_LINKUP_INTR_MASK 0x10000000
-#define BCHP_HIF_INTR2_CPU_CLEAR_PCIE_1_LINKUP_INTR_SHIFT 28
-#define BCHP_HIF_INTR2_CPU_CLEAR_PCIE_1_LINKUP_INTR_DEFAULT 0x00000000
-
-/* HIF_INTR2 :: CPU_CLEAR :: NAND_CORR_INTR [27:27] */
-#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_CORR_INTR_MASK 0x08000000
-#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_CORR_INTR_SHIFT 27
-#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_CORR_INTR_DEFAULT 0x00000000
-
-/* HIF_INTR2 :: CPU_CLEAR :: NAND_UNC_INTR [26:26] */
-#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_UNC_INTR_MASK 0x04000000
-#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_UNC_INTR_SHIFT 26
-#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_UNC_INTR_DEFAULT 0x00000000
-
-/* HIF_INTR2 :: CPU_CLEAR :: NAND_RBPIN_INTR [25:25] */
-#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_RBPIN_INTR_MASK 0x02000000
-#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_RBPIN_INTR_SHIFT 25
-#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_RBPIN_INTR_DEFAULT 0x00000000
-
-/* HIF_INTR2 :: CPU_CLEAR :: NAND_CTLRDY_INTR [24:24] */
-#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_CTLRDY_INTR_MASK 0x01000000
-#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_CTLRDY_INTR_SHIFT 24
-#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_CTLRDY_INTR_DEFAULT 0x00000000
-
-/* HIF_INTR2 :: CPU_CLEAR :: NAND_PGMPG_INTR [23:23] */
-#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_PGMPG_INTR_MASK 0x00800000
-#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_PGMPG_INTR_SHIFT 23
-#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_PGMPG_INTR_DEFAULT 0x00000000
-
-/* HIF_INTR2 :: CPU_CLEAR :: NAND_CPYBK_INTR [22:22] */
-#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_CPYBK_INTR_MASK 0x00400000
-#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_CPYBK_INTR_SHIFT 22
-#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_CPYBK_INTR_DEFAULT 0x00000000
-
-/* HIF_INTR2 :: CPU_CLEAR :: NAND_BLKERA_INTR [21:21] */
-#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_BLKERA_INTR_MASK 0x00200000
-#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_BLKERA_INTR_SHIFT 21
-#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_BLKERA_INTR_DEFAULT 0x00000000
-
-/* HIF_INTR2 :: CPU_CLEAR :: NAND_NP_READ_INTR [20:20] */
-#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_NP_READ_INTR_MASK 0x00100000
-#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_NP_READ_INTR_SHIFT 20
-#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_NP_READ_INTR_DEFAULT 0x00000000
-
-/* HIF_INTR2 :: CPU_CLEAR :: reserved0 [19:16] */
-#define BCHP_HIF_INTR2_CPU_CLEAR_reserved0_MASK 0x000f0000
-#define BCHP_HIF_INTR2_CPU_CLEAR_reserved0_SHIFT 16
-
-/* HIF_INTR2 :: CPU_CLEAR :: ITCH0_RD_INTR [15:15] */
-#define BCHP_HIF_INTR2_CPU_CLEAR_ITCH0_RD_INTR_MASK 0x00008000
-#define BCHP_HIF_INTR2_CPU_CLEAR_ITCH0_RD_INTR_SHIFT 15
-#define BCHP_HIF_INTR2_CPU_CLEAR_ITCH0_RD_INTR_DEFAULT 0x00000000
-
-/* HIF_INTR2 :: CPU_CLEAR :: reserved1 [14:14] */
-#define BCHP_HIF_INTR2_CPU_CLEAR_reserved1_MASK 0x00004000
-#define BCHP_HIF_INTR2_CPU_CLEAR_reserved1_SHIFT 14
-
-/* HIF_INTR2 :: CPU_CLEAR :: PCIE_0_RG_BRIDGE_INTR [13:13] */
-#define BCHP_HIF_INTR2_CPU_CLEAR_PCIE_0_RG_BRIDGE_INTR_MASK 0x00002000
-#define BCHP_HIF_INTR2_CPU_CLEAR_PCIE_0_RG_BRIDGE_INTR_SHIFT 13
-#define BCHP_HIF_INTR2_CPU_CLEAR_PCIE_0_RG_BRIDGE_INTR_DEFAULT 0x00000000
-
-/* HIF_INTR2 :: CPU_CLEAR :: PCIE_0_RGR_BRIDGE_INTR [12:12] */
-#define BCHP_HIF_INTR2_CPU_CLEAR_PCIE_0_RGR_BRIDGE_INTR_MASK 0x00001000
-#define BCHP_HIF_INTR2_CPU_CLEAR_PCIE_0_RGR_BRIDGE_INTR_SHIFT 12
-#define BCHP_HIF_INTR2_CPU_CLEAR_PCIE_0_RGR_BRIDGE_INTR_DEFAULT 0x00000000
-
-/* HIF_INTR2 :: CPU_CLEAR :: PCIE_1_RG_BRIDGE_INTR [11:11] */
-#define BCHP_HIF_INTR2_CPU_CLEAR_PCIE_1_RG_BRIDGE_INTR_MASK 0x00000800
-#define BCHP_HIF_INTR2_CPU_CLEAR_PCIE_1_RG_BRIDGE_INTR_SHIFT 11
-#define BCHP_HIF_INTR2_CPU_CLEAR_PCIE_1_RG_BRIDGE_INTR_DEFAULT 0x00000000
-
-/* HIF_INTR2 :: CPU_CLEAR :: PCIE_1_RGR_BRIDGE_INTR [10:10] */
-#define BCHP_HIF_INTR2_CPU_CLEAR_PCIE_1_RGR_BRIDGE_INTR_MASK 0x00000400
-#define BCHP_HIF_INTR2_CPU_CLEAR_PCIE_1_RGR_BRIDGE_INTR_SHIFT 10
-#define BCHP_HIF_INTR2_CPU_CLEAR_PCIE_1_RGR_BRIDGE_INTR_DEFAULT 0x00000000
-
-/* HIF_INTR2 :: CPU_CLEAR :: reserved2 [09:06] */
-#define BCHP_HIF_INTR2_CPU_CLEAR_reserved2_MASK 0x000003c0
-#define BCHP_HIF_INTR2_CPU_CLEAR_reserved2_SHIFT 6
-
-/* HIF_INTR2 :: CPU_CLEAR :: FLASH_DMA_ERR_INTR [05:05] */
-#define BCHP_HIF_INTR2_CPU_CLEAR_FLASH_DMA_ERR_INTR_MASK 0x00000020
-#define BCHP_HIF_INTR2_CPU_CLEAR_FLASH_DMA_ERR_INTR_SHIFT 5
-#define BCHP_HIF_INTR2_CPU_CLEAR_FLASH_DMA_ERR_INTR_DEFAULT 0x00000000
-
-/* HIF_INTR2 :: CPU_CLEAR :: FLASH_DMA_DONE_INTR [04:04] */
-#define BCHP_HIF_INTR2_CPU_CLEAR_FLASH_DMA_DONE_INTR_MASK 0x00000010
-#define BCHP_HIF_INTR2_CPU_CLEAR_FLASH_DMA_DONE_INTR_SHIFT 4
-#define BCHP_HIF_INTR2_CPU_CLEAR_FLASH_DMA_DONE_INTR_DEFAULT 0x00000000
-
-/* HIF_INTR2 :: CPU_CLEAR :: WEBHIF_WD_TIMEOUT_INTR [03:03] */
-#define BCHP_HIF_INTR2_CPU_CLEAR_WEBHIF_WD_TIMEOUT_INTR_MASK 0x00000008
-#define BCHP_HIF_INTR2_CPU_CLEAR_WEBHIF_WD_TIMEOUT_INTR_SHIFT 3
-#define BCHP_HIF_INTR2_CPU_CLEAR_WEBHIF_WD_TIMEOUT_INTR_DEFAULT 0x00000000
-
-/* HIF_INTR2 :: CPU_CLEAR :: reserved3 [02:02] */
-#define BCHP_HIF_INTR2_CPU_CLEAR_reserved3_MASK 0x00000004
-#define BCHP_HIF_INTR2_CPU_CLEAR_reserved3_SHIFT 2
-
-/* HIF_INTR2 :: CPU_CLEAR :: ITCH1_RD_INTR [01:01] */
-#define BCHP_HIF_INTR2_CPU_CLEAR_ITCH1_RD_INTR_MASK 0x00000002
-#define BCHP_HIF_INTR2_CPU_CLEAR_ITCH1_RD_INTR_SHIFT 1
-#define BCHP_HIF_INTR2_CPU_CLEAR_ITCH1_RD_INTR_DEFAULT 0x00000000
-
-/* HIF_INTR2 :: CPU_CLEAR :: HIF_RGR2_BRIDGE_INTR [00:00] */
-#define BCHP_HIF_INTR2_CPU_CLEAR_HIF_RGR2_BRIDGE_INTR_MASK 0x00000001
-#define BCHP_HIF_INTR2_CPU_CLEAR_HIF_RGR2_BRIDGE_INTR_SHIFT 0
-#define BCHP_HIF_INTR2_CPU_CLEAR_HIF_RGR2_BRIDGE_INTR_DEFAULT 0x00000000
-
-/***************************************************************************
- *CPU_MASK_STATUS - CPU interrupt Mask Status Register
- ***************************************************************************/
-/* HIF_INTR2 :: CPU_MASK_STATUS :: PCIE_0_LINKDOWN_INTR [31:31] */
-#define BCHP_HIF_INTR2_CPU_MASK_STATUS_PCIE_0_LINKDOWN_INTR_MASK 0x80000000
-#define BCHP_HIF_INTR2_CPU_MASK_STATUS_PCIE_0_LINKDOWN_INTR_SHIFT 31
-#define BCHP_HIF_INTR2_CPU_MASK_STATUS_PCIE_0_LINKDOWN_INTR_DEFAULT 0x00000000
-
-/* HIF_INTR2 :: CPU_MASK_STATUS :: PCIE_0_LINKUP_INTR [30:30] */
-#define BCHP_HIF_INTR2_CPU_MASK_STATUS_PCIE_0_LINKUP_INTR_MASK 0x40000000
-#define BCHP_HIF_INTR2_CPU_MASK_STATUS_PCIE_0_LINKUP_INTR_SHIFT 30
-#define BCHP_HIF_INTR2_CPU_MASK_STATUS_PCIE_0_LINKUP_INTR_DEFAULT 0x00000000
-
-/* HIF_INTR2 :: CPU_MASK_STATUS :: PCIE_1_LINKDOWN_INTR [29:29] */
-#define BCHP_HIF_INTR2_CPU_MASK_STATUS_PCIE_1_LINKDOWN_INTR_MASK 0x20000000
-#define BCHP_HIF_INTR2_CPU_MASK_STATUS_PCIE_1_LINKDOWN_INTR_SHIFT 29
-#define BCHP_HIF_INTR2_CPU_MASK_STATUS_PCIE_1_LINKDOWN_INTR_DEFAULT 0x00000000
-
-/* HIF_INTR2 :: CPU_MASK_STATUS :: PCIE_1_LINKUP_INTR [28:28] */
-#define BCHP_HIF_INTR2_CPU_MASK_STATUS_PCIE_1_LINKUP_INTR_MASK 0x10000000
-#define BCHP_HIF_INTR2_CPU_MASK_STATUS_PCIE_1_LINKUP_INTR_SHIFT 28
-#define BCHP_HIF_INTR2_CPU_MASK_STATUS_PCIE_1_LINKUP_INTR_DEFAULT 0x00000000
-
-/* HIF_INTR2 :: CPU_MASK_STATUS :: NAND_CORR_INTR [27:27] */
-#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_CORR_INTR_MASK 0x08000000
-#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_CORR_INTR_SHIFT 27
-#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_CORR_INTR_DEFAULT 0x00000001
-
-/* HIF_INTR2 :: CPU_MASK_STATUS :: NAND_UNC_INTR [26:26] */
-#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_UNC_INTR_MASK 0x04000000
-#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_UNC_INTR_SHIFT 26
-#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_UNC_INTR_DEFAULT 0x00000001
-
-/* HIF_INTR2 :: CPU_MASK_STATUS :: NAND_RBPIN_INTR [25:25] */
-#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_RBPIN_INTR_MASK 0x02000000
-#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_RBPIN_INTR_SHIFT 25
-#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_RBPIN_INTR_DEFAULT 0x00000001
-
-/* HIF_INTR2 :: CPU_MASK_STATUS :: NAND_CTLRDY_INTR [24:24] */
-#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_CTLRDY_INTR_MASK 0x01000000
-#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_CTLRDY_INTR_SHIFT 24
-#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_CTLRDY_INTR_DEFAULT 0x00000001
-
-/* HIF_INTR2 :: CPU_MASK_STATUS :: NAND_PGMPG_INTR [23:23] */
-#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_PGMPG_INTR_MASK 0x00800000
-#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_PGMPG_INTR_SHIFT 23
-#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_PGMPG_INTR_DEFAULT 0x00000001
-
-/* HIF_INTR2 :: CPU_MASK_STATUS :: NAND_CPYBK_INTR [22:22] */
-#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_CPYBK_INTR_MASK 0x00400000
-#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_CPYBK_INTR_SHIFT 22
-#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_CPYBK_INTR_DEFAULT 0x00000001
-
-/* HIF_INTR2 :: CPU_MASK_STATUS :: NAND_BLKERA_INTR [21:21] */
-#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_BLKERA_INTR_MASK 0x00200000
-#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_BLKERA_INTR_SHIFT 21
-#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_BLKERA_INTR_DEFAULT 0x00000001
-
-/* HIF_INTR2 :: CPU_MASK_STATUS :: NAND_NP_READ_INTR [20:20] */
-#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_NP_READ_INTR_MASK 0x00100000
-#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_NP_READ_INTR_SHIFT 20
-#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_NP_READ_INTR_DEFAULT 0x00000001
-
-/* HIF_INTR2 :: CPU_MASK_STATUS :: reserved0 [19:16] */
-#define BCHP_HIF_INTR2_CPU_MASK_STATUS_reserved0_MASK 0x000f0000
-#define BCHP_HIF_INTR2_CPU_MASK_STATUS_reserved0_SHIFT 16
-
-/* HIF_INTR2 :: CPU_MASK_STATUS :: ITCH0_RD_INTR [15:15] */
-#define BCHP_HIF_INTR2_CPU_MASK_STATUS_ITCH0_RD_INTR_MASK 0x00008000
-#define BCHP_HIF_INTR2_CPU_MASK_STATUS_ITCH0_RD_INTR_SHIFT 15
-#define BCHP_HIF_INTR2_CPU_MASK_STATUS_ITCH0_RD_INTR_DEFAULT 0x00000001
-
-/* HIF_INTR2 :: CPU_MASK_STATUS :: reserved1 [14:14] */
-#define BCHP_HIF_INTR2_CPU_MASK_STATUS_reserved1_MASK 0x00004000
-#define BCHP_HIF_INTR2_CPU_MASK_STATUS_reserved1_SHIFT 14
-
-/* HIF_INTR2 :: CPU_MASK_STATUS :: PCIE_0_RG_BRIDGE_INTR [13:13] */
-#define BCHP_HIF_INTR2_CPU_MASK_STATUS_PCIE_0_RG_BRIDGE_INTR_MASK 0x00002000
-#define BCHP_HIF_INTR2_CPU_MASK_STATUS_PCIE_0_RG_BRIDGE_INTR_SHIFT 13
-#define BCHP_HIF_INTR2_CPU_MASK_STATUS_PCIE_0_RG_BRIDGE_INTR_DEFAULT 0x00000001
-
-/* HIF_INTR2 :: CPU_MASK_STATUS :: PCIE_0_RGR_BRIDGE_INTR [12:12] */
-#define BCHP_HIF_INTR2_CPU_MASK_STATUS_PCIE_0_RGR_BRIDGE_INTR_MASK 0x00001000
-#define BCHP_HIF_INTR2_CPU_MASK_STATUS_PCIE_0_RGR_BRIDGE_INTR_SHIFT 12
-#define BCHP_HIF_INTR2_CPU_MASK_STATUS_PCIE_0_RGR_BRIDGE_INTR_DEFAULT 0x00000001
-
-/* HIF_INTR2 :: CPU_MASK_STATUS :: PCIE_1_RG_BRIDGE_INTR [11:11] */
-#define BCHP_HIF_INTR2_CPU_MASK_STATUS_PCIE_1_RG_BRIDGE_INTR_MASK 0x00000800
-#define BCHP_HIF_INTR2_CPU_MASK_STATUS_PCIE_1_RG_BRIDGE_INTR_SHIFT 11
-#define BCHP_HIF_INTR2_CPU_MASK_STATUS_PCIE_1_RG_BRIDGE_INTR_DEFAULT 0x00000001
-
-/* HIF_INTR2 :: CPU_MASK_STATUS :: PCIE_1_RGR_BRIDGE_INTR [10:10] */
-#define BCHP_HIF_INTR2_CPU_MASK_STATUS_PCIE_1_RGR_BRIDGE_INTR_MASK 0x00000400
-#define BCHP_HIF_INTR2_CPU_MASK_STATUS_PCIE_1_RGR_BRIDGE_INTR_SHIFT 10
-#define BCHP_HIF_INTR2_CPU_MASK_STATUS_PCIE_1_RGR_BRIDGE_INTR_DEFAULT 0x00000001
-
-/* HIF_INTR2 :: CPU_MASK_STATUS :: reserved2 [09:06] */
-#define BCHP_HIF_INTR2_CPU_MASK_STATUS_reserved2_MASK 0x000003c0
-#define BCHP_HIF_INTR2_CPU_MASK_STATUS_reserved2_SHIFT 6
-
-/* HIF_INTR2 :: CPU_MASK_STATUS :: FLASH_DMA_ERR_INTR [05:05] */
-#define BCHP_HIF_INTR2_CPU_MASK_STATUS_FLASH_DMA_ERR_INTR_MASK 0x00000020
-#define BCHP_HIF_INTR2_CPU_MASK_STATUS_FLASH_DMA_ERR_INTR_SHIFT 5
-#define BCHP_HIF_INTR2_CPU_MASK_STATUS_FLASH_DMA_ERR_INTR_DEFAULT 0x00000000
-
-/* HIF_INTR2 :: CPU_MASK_STATUS :: FLASH_DMA_DONE_INTR [04:04] */
-#define BCHP_HIF_INTR2_CPU_MASK_STATUS_FLASH_DMA_DONE_INTR_MASK 0x00000010
-#define BCHP_HIF_INTR2_CPU_MASK_STATUS_FLASH_DMA_DONE_INTR_SHIFT 4
-#define BCHP_HIF_INTR2_CPU_MASK_STATUS_FLASH_DMA_DONE_INTR_DEFAULT 0x00000000
-
-/* HIF_INTR2 :: CPU_MASK_STATUS :: WEBHIF_WD_TIMEOUT_INTR [03:03] */
-#define BCHP_HIF_INTR2_CPU_MASK_STATUS_WEBHIF_WD_TIMEOUT_INTR_MASK 0x00000008
-#define BCHP_HIF_INTR2_CPU_MASK_STATUS_WEBHIF_WD_TIMEOUT_INTR_SHIFT 3
-#define BCHP_HIF_INTR2_CPU_MASK_STATUS_WEBHIF_WD_TIMEOUT_INTR_DEFAULT 0x00000000
-
-/* HIF_INTR2 :: CPU_MASK_STATUS :: reserved3 [02:02] */
-#define BCHP_HIF_INTR2_CPU_MASK_STATUS_reserved3_MASK 0x00000004
-#define BCHP_HIF_INTR2_CPU_MASK_STATUS_reserved3_SHIFT 2
-
-/* HIF_INTR2 :: CPU_MASK_STATUS :: ITCH1_RD_INTR [01:01] */
-#define BCHP_HIF_INTR2_CPU_MASK_STATUS_ITCH1_RD_INTR_MASK 0x00000002
-#define BCHP_HIF_INTR2_CPU_MASK_STATUS_ITCH1_RD_INTR_SHIFT 1
-#define BCHP_HIF_INTR2_CPU_MASK_STATUS_ITCH1_RD_INTR_DEFAULT 0x00000001
-
-/* HIF_INTR2 :: CPU_MASK_STATUS :: HIF_RGR2_BRIDGE_INTR [00:00] */
-#define BCHP_HIF_INTR2_CPU_MASK_STATUS_HIF_RGR2_BRIDGE_INTR_MASK 0x00000001
-#define BCHP_HIF_INTR2_CPU_MASK_STATUS_HIF_RGR2_BRIDGE_INTR_SHIFT 0
-#define BCHP_HIF_INTR2_CPU_MASK_STATUS_HIF_RGR2_BRIDGE_INTR_DEFAULT 0x00000001
-
-/***************************************************************************
- *CPU_MASK_SET - CPU interrupt Mask Set Register
- ***************************************************************************/
-/* HIF_INTR2 :: CPU_MASK_SET :: PCIE_0_LINKDOWN_INTR [31:31] */
-#define BCHP_HIF_INTR2_CPU_MASK_SET_PCIE_0_LINKDOWN_INTR_MASK 0x80000000
-#define BCHP_HIF_INTR2_CPU_MASK_SET_PCIE_0_LINKDOWN_INTR_SHIFT 31
-#define BCHP_HIF_INTR2_CPU_MASK_SET_PCIE_0_LINKDOWN_INTR_DEFAULT 0x00000000
-
-/* HIF_INTR2 :: CPU_MASK_SET :: PCIE_0_LINKUP_INTR [30:30] */
-#define BCHP_HIF_INTR2_CPU_MASK_SET_PCIE_0_LINKUP_INTR_MASK 0x40000000
-#define BCHP_HIF_INTR2_CPU_MASK_SET_PCIE_0_LINKUP_INTR_SHIFT 30
-#define BCHP_HIF_INTR2_CPU_MASK_SET_PCIE_0_LINKUP_INTR_DEFAULT 0x00000000
-
-/* HIF_INTR2 :: CPU_MASK_SET :: PCIE_1_LINKDOWN_INTR [29:29] */
-#define BCHP_HIF_INTR2_CPU_MASK_SET_PCIE_1_LINKDOWN_INTR_MASK 0x20000000
-#define BCHP_HIF_INTR2_CPU_MASK_SET_PCIE_1_LINKDOWN_INTR_SHIFT 29
-#define BCHP_HIF_INTR2_CPU_MASK_SET_PCIE_1_LINKDOWN_INTR_DEFAULT 0x00000000
-
-/* HIF_INTR2 :: CPU_MASK_SET :: PCIE_1_LINKUP_INTR [28:28] */
-#define BCHP_HIF_INTR2_CPU_MASK_SET_PCIE_1_LINKUP_INTR_MASK 0x10000000
-#define BCHP_HIF_INTR2_CPU_MASK_SET_PCIE_1_LINKUP_INTR_SHIFT 28
-#define BCHP_HIF_INTR2_CPU_MASK_SET_PCIE_1_LINKUP_INTR_DEFAULT 0x00000000
-
-/* HIF_INTR2 :: CPU_MASK_SET :: NAND_CORR_INTR [27:27] */
-#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_CORR_INTR_MASK 0x08000000
-#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_CORR_INTR_SHIFT 27
-#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_CORR_INTR_DEFAULT 0x00000001
-
-/* HIF_INTR2 :: CPU_MASK_SET :: NAND_UNC_INTR [26:26] */
-#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_UNC_INTR_MASK 0x04000000
-#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_UNC_INTR_SHIFT 26
-#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_UNC_INTR_DEFAULT 0x00000001
-
-/* HIF_INTR2 :: CPU_MASK_SET :: NAND_RBPIN_INTR [25:25] */
-#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_RBPIN_INTR_MASK 0x02000000
-#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_RBPIN_INTR_SHIFT 25
-#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_RBPIN_INTR_DEFAULT 0x00000001
-
-/* HIF_INTR2 :: CPU_MASK_SET :: NAND_CTLRDY_INTR [24:24] */
-#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_CTLRDY_INTR_MASK 0x01000000
-#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_CTLRDY_INTR_SHIFT 24
-#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_CTLRDY_INTR_DEFAULT 0x00000001
-
-/* HIF_INTR2 :: CPU_MASK_SET :: NAND_PGMPG_INTR [23:23] */
-#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_PGMPG_INTR_MASK 0x00800000
-#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_PGMPG_INTR_SHIFT 23
-#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_PGMPG_INTR_DEFAULT 0x00000001
-
-/* HIF_INTR2 :: CPU_MASK_SET :: NAND_CPYBK_INTR [22:22] */
-#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_CPYBK_INTR_MASK 0x00400000
-#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_CPYBK_INTR_SHIFT 22
-#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_CPYBK_INTR_DEFAULT 0x00000001
-
-/* HIF_INTR2 :: CPU_MASK_SET :: NAND_BLKERA_INTR [21:21] */
-#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_BLKERA_INTR_MASK 0x00200000
-#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_BLKERA_INTR_SHIFT 21
-#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_BLKERA_INTR_DEFAULT 0x00000001
-
-/* HIF_INTR2 :: CPU_MASK_SET :: NAND_NP_READ_INTR [20:20] */
-#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_NP_READ_INTR_MASK 0x00100000
-#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_NP_READ_INTR_SHIFT 20
-#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_NP_READ_INTR_DEFAULT 0x00000001
-
-/* HIF_INTR2 :: CPU_MASK_SET :: reserved0 [19:16] */
-#define BCHP_HIF_INTR2_CPU_MASK_SET_reserved0_MASK 0x000f0000
-#define BCHP_HIF_INTR2_CPU_MASK_SET_reserved0_SHIFT 16
-
-/* HIF_INTR2 :: CPU_MASK_SET :: ITCH0_RD_INTR [15:15] */
-#define BCHP_HIF_INTR2_CPU_MASK_SET_ITCH0_RD_INTR_MASK 0x00008000
-#define BCHP_HIF_INTR2_CPU_MASK_SET_ITCH0_RD_INTR_SHIFT 15
-#define BCHP_HIF_INTR2_CPU_MASK_SET_ITCH0_RD_INTR_DEFAULT 0x00000001
-
-/* HIF_INTR2 :: CPU_MASK_SET :: reserved1 [14:14] */
-#define BCHP_HIF_INTR2_CPU_MASK_SET_reserved1_MASK 0x00004000
-#define BCHP_HIF_INTR2_CPU_MASK_SET_reserved1_SHIFT 14
-
-/* HIF_INTR2 :: CPU_MASK_SET :: PCIE_0_RG_BRIDGE_INTR [13:13] */
-#define BCHP_HIF_INTR2_CPU_MASK_SET_PCIE_0_RG_BRIDGE_INTR_MASK 0x00002000
-#define BCHP_HIF_INTR2_CPU_MASK_SET_PCIE_0_RG_BRIDGE_INTR_SHIFT 13
-#define BCHP_HIF_INTR2_CPU_MASK_SET_PCIE_0_RG_BRIDGE_INTR_DEFAULT 0x00000001
-
-/* HIF_INTR2 :: CPU_MASK_SET :: PCIE_0_RGR_BRIDGE_INTR [12:12] */
-#define BCHP_HIF_INTR2_CPU_MASK_SET_PCIE_0_RGR_BRIDGE_INTR_MASK 0x00001000
-#define BCHP_HIF_INTR2_CPU_MASK_SET_PCIE_0_RGR_BRIDGE_INTR_SHIFT 12
-#define BCHP_HIF_INTR2_CPU_MASK_SET_PCIE_0_RGR_BRIDGE_INTR_DEFAULT 0x00000001
-
-/* HIF_INTR2 :: CPU_MASK_SET :: PCIE_1_RG_BRIDGE_INTR [11:11] */
-#define BCHP_HIF_INTR2_CPU_MASK_SET_PCIE_1_RG_BRIDGE_INTR_MASK 0x00000800
-#define BCHP_HIF_INTR2_CPU_MASK_SET_PCIE_1_RG_BRIDGE_INTR_SHIFT 11
-#define BCHP_HIF_INTR2_CPU_MASK_SET_PCIE_1_RG_BRIDGE_INTR_DEFAULT 0x00000001
-
-/* HIF_INTR2 :: CPU_MASK_SET :: PCIE_1_RGR_BRIDGE_INTR [10:10] */
-#define BCHP_HIF_INTR2_CPU_MASK_SET_PCIE_1_RGR_BRIDGE_INTR_MASK 0x00000400
-#define BCHP_HIF_INTR2_CPU_MASK_SET_PCIE_1_RGR_BRIDGE_INTR_SHIFT 10
-#define BCHP_HIF_INTR2_CPU_MASK_SET_PCIE_1_RGR_BRIDGE_INTR_DEFAULT 0x00000001
-
-/* HIF_INTR2 :: CPU_MASK_SET :: reserved2 [09:06] */
-#define BCHP_HIF_INTR2_CPU_MASK_SET_reserved2_MASK 0x000003c0
-#define BCHP_HIF_INTR2_CPU_MASK_SET_reserved2_SHIFT 6
-
-/* HIF_INTR2 :: CPU_MASK_SET :: FLASH_DMA_ERR_INTR [05:05] */
-#define BCHP_HIF_INTR2_CPU_MASK_SET_FLASH_DMA_ERR_INTR_MASK 0x00000020
-#define BCHP_HIF_INTR2_CPU_MASK_SET_FLASH_DMA_ERR_INTR_SHIFT 5
-#define BCHP_HIF_INTR2_CPU_MASK_SET_FLASH_DMA_ERR_INTR_DEFAULT 0x00000000
-
-/* HIF_INTR2 :: CPU_MASK_SET :: FLASH_DMA_DONE_INTR [04:04] */
-#define BCHP_HIF_INTR2_CPU_MASK_SET_FLASH_DMA_DONE_INTR_MASK 0x00000010
-#define BCHP_HIF_INTR2_CPU_MASK_SET_FLASH_DMA_DONE_INTR_SHIFT 4
-#define BCHP_HIF_INTR2_CPU_MASK_SET_FLASH_DMA_DONE_INTR_DEFAULT 0x00000000
-
-/* HIF_INTR2 :: CPU_MASK_SET :: WEBHIF_WD_TIMEOUT_INTR [03:03] */
-#define BCHP_HIF_INTR2_CPU_MASK_SET_WEBHIF_WD_TIMEOUT_INTR_MASK 0x00000008
-#define BCHP_HIF_INTR2_CPU_MASK_SET_WEBHIF_WD_TIMEOUT_INTR_SHIFT 3
-#define BCHP_HIF_INTR2_CPU_MASK_SET_WEBHIF_WD_TIMEOUT_INTR_DEFAULT 0x00000000
-
-/* HIF_INTR2 :: CPU_MASK_SET :: reserved3 [02:02] */
-#define BCHP_HIF_INTR2_CPU_MASK_SET_reserved3_MASK 0x00000004
-#define BCHP_HIF_INTR2_CPU_MASK_SET_reserved3_SHIFT 2
-
-/* HIF_INTR2 :: CPU_MASK_SET :: ITCH1_RD_INTR [01:01] */
-#define BCHP_HIF_INTR2_CPU_MASK_SET_ITCH1_RD_INTR_MASK 0x00000002
-#define BCHP_HIF_INTR2_CPU_MASK_SET_ITCH1_RD_INTR_SHIFT 1
-#define BCHP_HIF_INTR2_CPU_MASK_SET_ITCH1_RD_INTR_DEFAULT 0x00000001
-
-/* HIF_INTR2 :: CPU_MASK_SET :: HIF_RGR2_BRIDGE_INTR [00:00] */
-#define BCHP_HIF_INTR2_CPU_MASK_SET_HIF_RGR2_BRIDGE_INTR_MASK 0x00000001
-#define BCHP_HIF_INTR2_CPU_MASK_SET_HIF_RGR2_BRIDGE_INTR_SHIFT 0
-#define BCHP_HIF_INTR2_CPU_MASK_SET_HIF_RGR2_BRIDGE_INTR_DEFAULT 0x00000001
-
-/***************************************************************************
- *CPU_MASK_CLEAR - CPU interrupt Mask Clear Register
- ***************************************************************************/
-/* HIF_INTR2 :: CPU_MASK_CLEAR :: PCIE_0_LINKDOWN_INTR [31:31] */
-#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_PCIE_0_LINKDOWN_INTR_MASK 0x80000000
-#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_PCIE_0_LINKDOWN_INTR_SHIFT 31
-#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_PCIE_0_LINKDOWN_INTR_DEFAULT 0x00000000
-
-/* HIF_INTR2 :: CPU_MASK_CLEAR :: PCIE_0_LINKUP_INTR [30:30] */
-#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_PCIE_0_LINKUP_INTR_MASK 0x40000000
-#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_PCIE_0_LINKUP_INTR_SHIFT 30
-#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_PCIE_0_LINKUP_INTR_DEFAULT 0x00000000
-
-/* HIF_INTR2 :: CPU_MASK_CLEAR :: PCIE_1_LINKDOWN_INTR [29:29] */
-#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_PCIE_1_LINKDOWN_INTR_MASK 0x20000000
-#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_PCIE_1_LINKDOWN_INTR_SHIFT 29
-#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_PCIE_1_LINKDOWN_INTR_DEFAULT 0x00000000
-
-/* HIF_INTR2 :: CPU_MASK_CLEAR :: PCIE_1_LINKUP_INTR [28:28] */
-#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_PCIE_1_LINKUP_INTR_MASK 0x10000000
-#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_PCIE_1_LINKUP_INTR_SHIFT 28
-#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_PCIE_1_LINKUP_INTR_DEFAULT 0x00000000
-
-/* HIF_INTR2 :: CPU_MASK_CLEAR :: NAND_CORR_INTR [27:27] */
-#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_CORR_INTR_MASK 0x08000000
-#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_CORR_INTR_SHIFT 27
-#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_CORR_INTR_DEFAULT 0x00000001
-
-/* HIF_INTR2 :: CPU_MASK_CLEAR :: NAND_UNC_INTR [26:26] */
-#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_UNC_INTR_MASK 0x04000000
-#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_UNC_INTR_SHIFT 26
-#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_UNC_INTR_DEFAULT 0x00000001
-
-/* HIF_INTR2 :: CPU_MASK_CLEAR :: NAND_RBPIN_INTR [25:25] */
-#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_RBPIN_INTR_MASK 0x02000000
-#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_RBPIN_INTR_SHIFT 25
-#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_RBPIN_INTR_DEFAULT 0x00000001
-
-/* HIF_INTR2 :: CPU_MASK_CLEAR :: NAND_CTLRDY_INTR [24:24] */
-#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_CTLRDY_INTR_MASK 0x01000000
-#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_CTLRDY_INTR_SHIFT 24
-#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_CTLRDY_INTR_DEFAULT 0x00000001
-
-/* HIF_INTR2 :: CPU_MASK_CLEAR :: NAND_PGMPG_INTR [23:23] */
-#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_PGMPG_INTR_MASK 0x00800000
-#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_PGMPG_INTR_SHIFT 23
-#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_PGMPG_INTR_DEFAULT 0x00000001
-
-/* HIF_INTR2 :: CPU_MASK_CLEAR :: NAND_CPYBK_INTR [22:22] */
-#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_CPYBK_INTR_MASK 0x00400000
-#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_CPYBK_INTR_SHIFT 22
-#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_CPYBK_INTR_DEFAULT 0x00000001
-
-/* HIF_INTR2 :: CPU_MASK_CLEAR :: NAND_BLKERA_INTR [21:21] */
-#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_BLKERA_INTR_MASK 0x00200000
-#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_BLKERA_INTR_SHIFT 21
-#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_BLKERA_INTR_DEFAULT 0x00000001
-
-/* HIF_INTR2 :: CPU_MASK_CLEAR :: NAND_NP_READ_INTR [20:20] */
-#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_NP_READ_INTR_MASK 0x00100000
-#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_NP_READ_INTR_SHIFT 20
-#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_NP_READ_INTR_DEFAULT 0x00000001
-
-/* HIF_INTR2 :: CPU_MASK_CLEAR :: reserved0 [19:16] */
-#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_reserved0_MASK 0x000f0000
-#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_reserved0_SHIFT 16
-
-/* HIF_INTR2 :: CPU_MASK_CLEAR :: ITCH0_RD_INTR [15:15] */
-#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_ITCH0_RD_INTR_MASK 0x00008000
-#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_ITCH0_RD_INTR_SHIFT 15
-#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_ITCH0_RD_INTR_DEFAULT 0x00000001
-
-/* HIF_INTR2 :: CPU_MASK_CLEAR :: reserved1 [14:14] */
-#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_reserved1_MASK 0x00004000
-#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_reserved1_SHIFT 14
-
-/* HIF_INTR2 :: CPU_MASK_CLEAR :: PCIE_0_RG_BRIDGE_INTR [13:13] */
-#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_PCIE_0_RG_BRIDGE_INTR_MASK 0x00002000
-#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_PCIE_0_RG_BRIDGE_INTR_SHIFT 13
-#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_PCIE_0_RG_BRIDGE_INTR_DEFAULT 0x00000001
-
-/* HIF_INTR2 :: CPU_MASK_CLEAR :: PCIE_0_RGR_BRIDGE_INTR [12:12] */
-#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_PCIE_0_RGR_BRIDGE_INTR_MASK 0x00001000
-#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_PCIE_0_RGR_BRIDGE_INTR_SHIFT 12
-#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_PCIE_0_RGR_BRIDGE_INTR_DEFAULT 0x00000001
-
-/* HIF_INTR2 :: CPU_MASK_CLEAR :: PCIE_1_RG_BRIDGE_INTR [11:11] */
-#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_PCIE_1_RG_BRIDGE_INTR_MASK 0x00000800
-#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_PCIE_1_RG_BRIDGE_INTR_SHIFT 11
-#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_PCIE_1_RG_BRIDGE_INTR_DEFAULT 0x00000001
-
-/* HIF_INTR2 :: CPU_MASK_CLEAR :: PCIE_1_RGR_BRIDGE_INTR [10:10] */
-#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_PCIE_1_RGR_BRIDGE_INTR_MASK 0x00000400
-#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_PCIE_1_RGR_BRIDGE_INTR_SHIFT 10
-#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_PCIE_1_RGR_BRIDGE_INTR_DEFAULT 0x00000001
-
-/* HIF_INTR2 :: CPU_MASK_CLEAR :: reserved2 [09:06] */
-#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_reserved2_MASK 0x000003c0
-#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_reserved2_SHIFT 6
-
-/* HIF_INTR2 :: CPU_MASK_CLEAR :: FLASH_DMA_ERR_INTR [05:05] */
-#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_FLASH_DMA_ERR_INTR_MASK 0x00000020
-#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_FLASH_DMA_ERR_INTR_SHIFT 5
-#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_FLASH_DMA_ERR_INTR_DEFAULT 0x00000000
-
-/* HIF_INTR2 :: CPU_MASK_CLEAR :: FLASH_DMA_DONE_INTR [04:04] */
-#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_FLASH_DMA_DONE_INTR_MASK 0x00000010
-#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_FLASH_DMA_DONE_INTR_SHIFT 4
-#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_FLASH_DMA_DONE_INTR_DEFAULT 0x00000000
-
-/* HIF_INTR2 :: CPU_MASK_CLEAR :: WEBHIF_WD_TIMEOUT_INTR [03:03] */
-#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_WEBHIF_WD_TIMEOUT_INTR_MASK 0x00000008
-#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_WEBHIF_WD_TIMEOUT_INTR_SHIFT 3
-#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_WEBHIF_WD_TIMEOUT_INTR_DEFAULT 0x00000000
-
-/* HIF_INTR2 :: CPU_MASK_CLEAR :: reserved3 [02:02] */
-#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_reserved3_MASK 0x00000004
-#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_reserved3_SHIFT 2
-
-/* HIF_INTR2 :: CPU_MASK_CLEAR :: ITCH1_RD_INTR [01:01] */
-#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_ITCH1_RD_INTR_MASK 0x00000002
-#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_ITCH1_RD_INTR_SHIFT 1
-#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_ITCH1_RD_INTR_DEFAULT 0x00000001
-
-/* HIF_INTR2 :: CPU_MASK_CLEAR :: HIF_RGR2_BRIDGE_INTR [00:00] */
-#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_HIF_RGR2_BRIDGE_INTR_MASK 0x00000001
-#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_HIF_RGR2_BRIDGE_INTR_SHIFT 0
-#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_HIF_RGR2_BRIDGE_INTR_DEFAULT 0x00000001
-
-/***************************************************************************
- *PCI_STATUS - PCI interrupt Status Register
- ***************************************************************************/
-/* HIF_INTR2 :: PCI_STATUS :: PCIE_0_LINKDOWN_INTR [31:31] */
-#define BCHP_HIF_INTR2_PCI_STATUS_PCIE_0_LINKDOWN_INTR_MASK 0x80000000
-#define BCHP_HIF_INTR2_PCI_STATUS_PCIE_0_LINKDOWN_INTR_SHIFT 31
-#define BCHP_HIF_INTR2_PCI_STATUS_PCIE_0_LINKDOWN_INTR_DEFAULT 0x00000000
-
-/* HIF_INTR2 :: PCI_STATUS :: PCIE_0_LINKUP_INTR [30:30] */
-#define BCHP_HIF_INTR2_PCI_STATUS_PCIE_0_LINKUP_INTR_MASK 0x40000000
-#define BCHP_HIF_INTR2_PCI_STATUS_PCIE_0_LINKUP_INTR_SHIFT 30
-#define BCHP_HIF_INTR2_PCI_STATUS_PCIE_0_LINKUP_INTR_DEFAULT 0x00000000
-
-/* HIF_INTR2 :: PCI_STATUS :: PCIE_1_LINKDOWN_INTR [29:29] */
-#define BCHP_HIF_INTR2_PCI_STATUS_PCIE_1_LINKDOWN_INTR_MASK 0x20000000
-#define BCHP_HIF_INTR2_PCI_STATUS_PCIE_1_LINKDOWN_INTR_SHIFT 29
-#define BCHP_HIF_INTR2_PCI_STATUS_PCIE_1_LINKDOWN_INTR_DEFAULT 0x00000000
-
-/* HIF_INTR2 :: PCI_STATUS :: PCIE_1_LINKUP_INTR [28:28] */
-#define BCHP_HIF_INTR2_PCI_STATUS_PCIE_1_LINKUP_INTR_MASK 0x10000000
-#define BCHP_HIF_INTR2_PCI_STATUS_PCIE_1_LINKUP_INTR_SHIFT 28
-#define BCHP_HIF_INTR2_PCI_STATUS_PCIE_1_LINKUP_INTR_DEFAULT 0x00000000
-
-/* HIF_INTR2 :: PCI_STATUS :: NAND_CORR_INTR [27:27] */
-#define BCHP_HIF_INTR2_PCI_STATUS_NAND_CORR_INTR_MASK 0x08000000
-#define BCHP_HIF_INTR2_PCI_STATUS_NAND_CORR_INTR_SHIFT 27
-#define BCHP_HIF_INTR2_PCI_STATUS_NAND_CORR_INTR_DEFAULT 0x00000000
-
-/* HIF_INTR2 :: PCI_STATUS :: NAND_UNC_INTR [26:26] */
-#define BCHP_HIF_INTR2_PCI_STATUS_NAND_UNC_INTR_MASK 0x04000000
-#define BCHP_HIF_INTR2_PCI_STATUS_NAND_UNC_INTR_SHIFT 26
-#define BCHP_HIF_INTR2_PCI_STATUS_NAND_UNC_INTR_DEFAULT 0x00000000
-
-/* HIF_INTR2 :: PCI_STATUS :: NAND_RBPIN_INTR [25:25] */
-#define BCHP_HIF_INTR2_PCI_STATUS_NAND_RBPIN_INTR_MASK 0x02000000
-#define BCHP_HIF_INTR2_PCI_STATUS_NAND_RBPIN_INTR_SHIFT 25
-#define BCHP_HIF_INTR2_PCI_STATUS_NAND_RBPIN_INTR_DEFAULT 0x00000000
-
-/* HIF_INTR2 :: PCI_STATUS :: NAND_CTLRDY_INTR [24:24] */
-#define BCHP_HIF_INTR2_PCI_STATUS_NAND_CTLRDY_INTR_MASK 0x01000000
-#define BCHP_HIF_INTR2_PCI_STATUS_NAND_CTLRDY_INTR_SHIFT 24
-#define BCHP_HIF_INTR2_PCI_STATUS_NAND_CTLRDY_INTR_DEFAULT 0x00000000
-
-/* HIF_INTR2 :: PCI_STATUS :: NAND_PGMPG_INTR [23:23] */
-#define BCHP_HIF_INTR2_PCI_STATUS_NAND_PGMPG_INTR_MASK 0x00800000
-#define BCHP_HIF_INTR2_PCI_STATUS_NAND_PGMPG_INTR_SHIFT 23
-#define BCHP_HIF_INTR2_PCI_STATUS_NAND_PGMPG_INTR_DEFAULT 0x00000000
-
-/* HIF_INTR2 :: PCI_STATUS :: NAND_CPYBK_INTR [22:22] */
-#define BCHP_HIF_INTR2_PCI_STATUS_NAND_CPYBK_INTR_MASK 0x00400000
-#define BCHP_HIF_INTR2_PCI_STATUS_NAND_CPYBK_INTR_SHIFT 22
-#define BCHP_HIF_INTR2_PCI_STATUS_NAND_CPYBK_INTR_DEFAULT 0x00000000
-
-/* HIF_INTR2 :: PCI_STATUS :: NAND_BLKERA_INTR [21:21] */
-#define BCHP_HIF_INTR2_PCI_STATUS_NAND_BLKERA_INTR_MASK 0x00200000
-#define BCHP_HIF_INTR2_PCI_STATUS_NAND_BLKERA_INTR_SHIFT 21
-#define BCHP_HIF_INTR2_PCI_STATUS_NAND_BLKERA_INTR_DEFAULT 0x00000000
-
-/* HIF_INTR2 :: PCI_STATUS :: NAND_NP_READ_INTR [20:20] */
-#define BCHP_HIF_INTR2_PCI_STATUS_NAND_NP_READ_INTR_MASK 0x00100000
-#define BCHP_HIF_INTR2_PCI_STATUS_NAND_NP_READ_INTR_SHIFT 20
-#define BCHP_HIF_INTR2_PCI_STATUS_NAND_NP_READ_INTR_DEFAULT 0x00000000
-
-/* HIF_INTR2 :: PCI_STATUS :: reserved0 [19:16] */
-#define BCHP_HIF_INTR2_PCI_STATUS_reserved0_MASK 0x000f0000
-#define BCHP_HIF_INTR2_PCI_STATUS_reserved0_SHIFT 16
-
-/* HIF_INTR2 :: PCI_STATUS :: ITCH0_RD_INTR [15:15] */
-#define BCHP_HIF_INTR2_PCI_STATUS_ITCH0_RD_INTR_MASK 0x00008000
-#define BCHP_HIF_INTR2_PCI_STATUS_ITCH0_RD_INTR_SHIFT 15
-#define BCHP_HIF_INTR2_PCI_STATUS_ITCH0_RD_INTR_DEFAULT 0x00000000
-
-/* HIF_INTR2 :: PCI_STATUS :: reserved1 [14:14] */
-#define BCHP_HIF_INTR2_PCI_STATUS_reserved1_MASK 0x00004000
-#define BCHP_HIF_INTR2_PCI_STATUS_reserved1_SHIFT 14
-
-/* HIF_INTR2 :: PCI_STATUS :: PCIE_0_RG_BRIDGE_INTR [13:13] */
-#define BCHP_HIF_INTR2_PCI_STATUS_PCIE_0_RG_BRIDGE_INTR_MASK 0x00002000
-#define BCHP_HIF_INTR2_PCI_STATUS_PCIE_0_RG_BRIDGE_INTR_SHIFT 13
-#define BCHP_HIF_INTR2_PCI_STATUS_PCIE_0_RG_BRIDGE_INTR_DEFAULT 0x00000000
-
-/* HIF_INTR2 :: PCI_STATUS :: PCIE_0_RGR_BRIDGE_INTR [12:12] */
-#define BCHP_HIF_INTR2_PCI_STATUS_PCIE_0_RGR_BRIDGE_INTR_MASK 0x00001000
-#define BCHP_HIF_INTR2_PCI_STATUS_PCIE_0_RGR_BRIDGE_INTR_SHIFT 12
-#define BCHP_HIF_INTR2_PCI_STATUS_PCIE_0_RGR_BRIDGE_INTR_DEFAULT 0x00000000
-
-/* HIF_INTR2 :: PCI_STATUS :: PCIE_1_RG_BRIDGE_INTR [11:11] */
-#define BCHP_HIF_INTR2_PCI_STATUS_PCIE_1_RG_BRIDGE_INTR_MASK 0x00000800
-#define BCHP_HIF_INTR2_PCI_STATUS_PCIE_1_RG_BRIDGE_INTR_SHIFT 11
-#define BCHP_HIF_INTR2_PCI_STATUS_PCIE_1_RG_BRIDGE_INTR_DEFAULT 0x00000000
-
-/* HIF_INTR2 :: PCI_STATUS :: PCIE_1_RGR_BRIDGE_INTR [10:10] */
-#define BCHP_HIF_INTR2_PCI_STATUS_PCIE_1_RGR_BRIDGE_INTR_MASK 0x00000400
-#define BCHP_HIF_INTR2_PCI_STATUS_PCIE_1_RGR_BRIDGE_INTR_SHIFT 10
-#define BCHP_HIF_INTR2_PCI_STATUS_PCIE_1_RGR_BRIDGE_INTR_DEFAULT 0x00000000
-
-/* HIF_INTR2 :: PCI_STATUS :: reserved2 [09:06] */
-#define BCHP_HIF_INTR2_PCI_STATUS_reserved2_MASK 0x000003c0
-#define BCHP_HIF_INTR2_PCI_STATUS_reserved2_SHIFT 6
-
-/* HIF_INTR2 :: PCI_STATUS :: FLASH_DMA_ERR_INTR [05:05] */
-#define BCHP_HIF_INTR2_PCI_STATUS_FLASH_DMA_ERR_INTR_MASK 0x00000020
-#define BCHP_HIF_INTR2_PCI_STATUS_FLASH_DMA_ERR_INTR_SHIFT 5
-#define BCHP_HIF_INTR2_PCI_STATUS_FLASH_DMA_ERR_INTR_DEFAULT 0x00000000
-
-/* HIF_INTR2 :: PCI_STATUS :: FLASH_DMA_DONE_INTR [04:04] */
-#define BCHP_HIF_INTR2_PCI_STATUS_FLASH_DMA_DONE_INTR_MASK 0x00000010
-#define BCHP_HIF_INTR2_PCI_STATUS_FLASH_DMA_DONE_INTR_SHIFT 4
-#define BCHP_HIF_INTR2_PCI_STATUS_FLASH_DMA_DONE_INTR_DEFAULT 0x00000000
-
-/* HIF_INTR2 :: PCI_STATUS :: WEBHIF_WD_TIMEOUT_INTR [03:03] */
-#define BCHP_HIF_INTR2_PCI_STATUS_WEBHIF_WD_TIMEOUT_INTR_MASK 0x00000008
-#define BCHP_HIF_INTR2_PCI_STATUS_WEBHIF_WD_TIMEOUT_INTR_SHIFT 3
-#define BCHP_HIF_INTR2_PCI_STATUS_WEBHIF_WD_TIMEOUT_INTR_DEFAULT 0x00000000
-
-/* HIF_INTR2 :: PCI_STATUS :: reserved3 [02:02] */
-#define BCHP_HIF_INTR2_PCI_STATUS_reserved3_MASK 0x00000004
-#define BCHP_HIF_INTR2_PCI_STATUS_reserved3_SHIFT 2
-
-/* HIF_INTR2 :: PCI_STATUS :: ITCH1_RD_INTR [01:01] */
-#define BCHP_HIF_INTR2_PCI_STATUS_ITCH1_RD_INTR_MASK 0x00000002
-#define BCHP_HIF_INTR2_PCI_STATUS_ITCH1_RD_INTR_SHIFT 1
-#define BCHP_HIF_INTR2_PCI_STATUS_ITCH1_RD_INTR_DEFAULT 0x00000000
-
-/* HIF_INTR2 :: PCI_STATUS :: HIF_RGR2_BRIDGE_INTR [00:00] */
-#define BCHP_HIF_INTR2_PCI_STATUS_HIF_RGR2_BRIDGE_INTR_MASK 0x00000001
-#define BCHP_HIF_INTR2_PCI_STATUS_HIF_RGR2_BRIDGE_INTR_SHIFT 0
-#define BCHP_HIF_INTR2_PCI_STATUS_HIF_RGR2_BRIDGE_INTR_DEFAULT 0x00000000
-
-/***************************************************************************
- *PCI_SET - PCI interrupt Set Register
- ***************************************************************************/
-/* HIF_INTR2 :: PCI_SET :: PCIE_0_LINKDOWN_INTR [31:31] */
-#define BCHP_HIF_INTR2_PCI_SET_PCIE_0_LINKDOWN_INTR_MASK 0x80000000
-#define BCHP_HIF_INTR2_PCI_SET_PCIE_0_LINKDOWN_INTR_SHIFT 31
-#define BCHP_HIF_INTR2_PCI_SET_PCIE_0_LINKDOWN_INTR_DEFAULT 0x00000000
-
-/* HIF_INTR2 :: PCI_SET :: PCIE_0_LINKUP_INTR [30:30] */
-#define BCHP_HIF_INTR2_PCI_SET_PCIE_0_LINKUP_INTR_MASK 0x40000000
-#define BCHP_HIF_INTR2_PCI_SET_PCIE_0_LINKUP_INTR_SHIFT 30
-#define BCHP_HIF_INTR2_PCI_SET_PCIE_0_LINKUP_INTR_DEFAULT 0x00000000
-
-/* HIF_INTR2 :: PCI_SET :: PCIE_1_LINKDOWN_INTR [29:29] */
-#define BCHP_HIF_INTR2_PCI_SET_PCIE_1_LINKDOWN_INTR_MASK 0x20000000
-#define BCHP_HIF_INTR2_PCI_SET_PCIE_1_LINKDOWN_INTR_SHIFT 29
-#define BCHP_HIF_INTR2_PCI_SET_PCIE_1_LINKDOWN_INTR_DEFAULT 0x00000000
-
-/* HIF_INTR2 :: PCI_SET :: PCIE_1_LINKUP_INTR [28:28] */
-#define BCHP_HIF_INTR2_PCI_SET_PCIE_1_LINKUP_INTR_MASK 0x10000000
-#define BCHP_HIF_INTR2_PCI_SET_PCIE_1_LINKUP_INTR_SHIFT 28
-#define BCHP_HIF_INTR2_PCI_SET_PCIE_1_LINKUP_INTR_DEFAULT 0x00000000
-
-/* HIF_INTR2 :: PCI_SET :: NAND_CORR_INTR [27:27] */
-#define BCHP_HIF_INTR2_PCI_SET_NAND_CORR_INTR_MASK 0x08000000
-#define BCHP_HIF_INTR2_PCI_SET_NAND_CORR_INTR_SHIFT 27
-#define BCHP_HIF_INTR2_PCI_SET_NAND_CORR_INTR_DEFAULT 0x00000000
-
-/* HIF_INTR2 :: PCI_SET :: NAND_UNC_INTR [26:26] */
-#define BCHP_HIF_INTR2_PCI_SET_NAND_UNC_INTR_MASK 0x04000000
-#define BCHP_HIF_INTR2_PCI_SET_NAND_UNC_INTR_SHIFT 26
-#define BCHP_HIF_INTR2_PCI_SET_NAND_UNC_INTR_DEFAULT 0x00000000
-
-/* HIF_INTR2 :: PCI_SET :: NAND_RBPIN_INTR [25:25] */
-#define BCHP_HIF_INTR2_PCI_SET_NAND_RBPIN_INTR_MASK 0x02000000
-#define BCHP_HIF_INTR2_PCI_SET_NAND_RBPIN_INTR_SHIFT 25
-#define BCHP_HIF_INTR2_PCI_SET_NAND_RBPIN_INTR_DEFAULT 0x00000000
-
-/* HIF_INTR2 :: PCI_SET :: NAND_CTLRDY_INTR [24:24] */
-#define BCHP_HIF_INTR2_PCI_SET_NAND_CTLRDY_INTR_MASK 0x01000000
-#define BCHP_HIF_INTR2_PCI_SET_NAND_CTLRDY_INTR_SHIFT 24
-#define BCHP_HIF_INTR2_PCI_SET_NAND_CTLRDY_INTR_DEFAULT 0x00000000
-
-/* HIF_INTR2 :: PCI_SET :: NAND_PGMPG_INTR [23:23] */
-#define BCHP_HIF_INTR2_PCI_SET_NAND_PGMPG_INTR_MASK 0x00800000
-#define BCHP_HIF_INTR2_PCI_SET_NAND_PGMPG_INTR_SHIFT 23
-#define BCHP_HIF_INTR2_PCI_SET_NAND_PGMPG_INTR_DEFAULT 0x00000000
-
-/* HIF_INTR2 :: PCI_SET :: NAND_CPYBK_INTR [22:22] */
-#define BCHP_HIF_INTR2_PCI_SET_NAND_CPYBK_INTR_MASK 0x00400000
-#define BCHP_HIF_INTR2_PCI_SET_NAND_CPYBK_INTR_SHIFT 22
-#define BCHP_HIF_INTR2_PCI_SET_NAND_CPYBK_INTR_DEFAULT 0x00000000
-
-/* HIF_INTR2 :: PCI_SET :: NAND_BLKERA_INTR [21:21] */
-#define BCHP_HIF_INTR2_PCI_SET_NAND_BLKERA_INTR_MASK 0x00200000
-#define BCHP_HIF_INTR2_PCI_SET_NAND_BLKERA_INTR_SHIFT 21
-#define BCHP_HIF_INTR2_PCI_SET_NAND_BLKERA_INTR_DEFAULT 0x00000000
-
-/* HIF_INTR2 :: PCI_SET :: NAND_NP_READ_INTR [20:20] */
-#define BCHP_HIF_INTR2_PCI_SET_NAND_NP_READ_INTR_MASK 0x00100000
-#define BCHP_HIF_INTR2_PCI_SET_NAND_NP_READ_INTR_SHIFT 20
-#define BCHP_HIF_INTR2_PCI_SET_NAND_NP_READ_INTR_DEFAULT 0x00000000
-
-/* HIF_INTR2 :: PCI_SET :: reserved0 [19:16] */
-#define BCHP_HIF_INTR2_PCI_SET_reserved0_MASK 0x000f0000
-#define BCHP_HIF_INTR2_PCI_SET_reserved0_SHIFT 16
-
-/* HIF_INTR2 :: PCI_SET :: ITCH0_RD_INTR [15:15] */
-#define BCHP_HIF_INTR2_PCI_SET_ITCH0_RD_INTR_MASK 0x00008000
-#define BCHP_HIF_INTR2_PCI_SET_ITCH0_RD_INTR_SHIFT 15
-#define BCHP_HIF_INTR2_PCI_SET_ITCH0_RD_INTR_DEFAULT 0x00000000
-
-/* HIF_INTR2 :: PCI_SET :: reserved1 [14:14] */
-#define BCHP_HIF_INTR2_PCI_SET_reserved1_MASK 0x00004000
-#define BCHP_HIF_INTR2_PCI_SET_reserved1_SHIFT 14
-
-/* HIF_INTR2 :: PCI_SET :: PCIE_0_RG_BRIDGE_INTR [13:13] */
-#define BCHP_HIF_INTR2_PCI_SET_PCIE_0_RG_BRIDGE_INTR_MASK 0x00002000
-#define BCHP_HIF_INTR2_PCI_SET_PCIE_0_RG_BRIDGE_INTR_SHIFT 13
-#define BCHP_HIF_INTR2_PCI_SET_PCIE_0_RG_BRIDGE_INTR_DEFAULT 0x00000000
-
-/* HIF_INTR2 :: PCI_SET :: PCIE_0_RGR_BRIDGE_INTR [12:12] */
-#define BCHP_HIF_INTR2_PCI_SET_PCIE_0_RGR_BRIDGE_INTR_MASK 0x00001000
-#define BCHP_HIF_INTR2_PCI_SET_PCIE_0_RGR_BRIDGE_INTR_SHIFT 12
-#define BCHP_HIF_INTR2_PCI_SET_PCIE_0_RGR_BRIDGE_INTR_DEFAULT 0x00000000
-
-/* HIF_INTR2 :: PCI_SET :: PCIE_1_RG_BRIDGE_INTR [11:11] */
-#define BCHP_HIF_INTR2_PCI_SET_PCIE_1_RG_BRIDGE_INTR_MASK 0x00000800
-#define BCHP_HIF_INTR2_PCI_SET_PCIE_1_RG_BRIDGE_INTR_SHIFT 11
-#define BCHP_HIF_INTR2_PCI_SET_PCIE_1_RG_BRIDGE_INTR_DEFAULT 0x00000000
-
-/* HIF_INTR2 :: PCI_SET :: PCIE_1_RGR_BRIDGE_INTR [10:10] */
-#define BCHP_HIF_INTR2_PCI_SET_PCIE_1_RGR_BRIDGE_INTR_MASK 0x00000400
-#define BCHP_HIF_INTR2_PCI_SET_PCIE_1_RGR_BRIDGE_INTR_SHIFT 10
-#define BCHP_HIF_INTR2_PCI_SET_PCIE_1_RGR_BRIDGE_INTR_DEFAULT 0x00000000
-
-/* HIF_INTR2 :: PCI_SET :: reserved2 [09:06] */
-#define BCHP_HIF_INTR2_PCI_SET_reserved2_MASK 0x000003c0
-#define BCHP_HIF_INTR2_PCI_SET_reserved2_SHIFT 6
-
-/* HIF_INTR2 :: PCI_SET :: FLASH_DMA_ERR_INTR [05:05] */
-#define BCHP_HIF_INTR2_PCI_SET_FLASH_DMA_ERR_INTR_MASK 0x00000020
-#define BCHP_HIF_INTR2_PCI_SET_FLASH_DMA_ERR_INTR_SHIFT 5
-#define BCHP_HIF_INTR2_PCI_SET_FLASH_DMA_ERR_INTR_DEFAULT 0x00000000
-
-/* HIF_INTR2 :: PCI_SET :: FLASH_DMA_DONE_INTR [04:04] */
-#define BCHP_HIF_INTR2_PCI_SET_FLASH_DMA_DONE_INTR_MASK 0x00000010
-#define BCHP_HIF_INTR2_PCI_SET_FLASH_DMA_DONE_INTR_SHIFT 4
-#define BCHP_HIF_INTR2_PCI_SET_FLASH_DMA_DONE_INTR_DEFAULT 0x00000000
-
-/* HIF_INTR2 :: PCI_SET :: WEBHIF_WD_TIMEOUT_INTR [03:03] */
-#define BCHP_HIF_INTR2_PCI_SET_WEBHIF_WD_TIMEOUT_INTR_MASK 0x00000008
-#define BCHP_HIF_INTR2_PCI_SET_WEBHIF_WD_TIMEOUT_INTR_SHIFT 3
-#define BCHP_HIF_INTR2_PCI_SET_WEBHIF_WD_TIMEOUT_INTR_DEFAULT 0x00000000
-
-/* HIF_INTR2 :: PCI_SET :: reserved3 [02:02] */
-#define BCHP_HIF_INTR2_PCI_SET_reserved3_MASK 0x00000004
-#define BCHP_HIF_INTR2_PCI_SET_reserved3_SHIFT 2
-
-/* HIF_INTR2 :: PCI_SET :: ITCH1_RD_INTR [01:01] */
-#define BCHP_HIF_INTR2_PCI_SET_ITCH1_RD_INTR_MASK 0x00000002
-#define BCHP_HIF_INTR2_PCI_SET_ITCH1_RD_INTR_SHIFT 1
-#define BCHP_HIF_INTR2_PCI_SET_ITCH1_RD_INTR_DEFAULT 0x00000000
-
-/* HIF_INTR2 :: PCI_SET :: HIF_RGR2_BRIDGE_INTR [00:00] */
-#define BCHP_HIF_INTR2_PCI_SET_HIF_RGR2_BRIDGE_INTR_MASK 0x00000001
-#define BCHP_HIF_INTR2_PCI_SET_HIF_RGR2_BRIDGE_INTR_SHIFT 0
-#define BCHP_HIF_INTR2_PCI_SET_HIF_RGR2_BRIDGE_INTR_DEFAULT 0x00000000
-
-/***************************************************************************
- *PCI_CLEAR - PCI interrupt Clear Register
- ***************************************************************************/
-/* HIF_INTR2 :: PCI_CLEAR :: PCIE_0_LINKDOWN_INTR [31:31] */
-#define BCHP_HIF_INTR2_PCI_CLEAR_PCIE_0_LINKDOWN_INTR_MASK 0x80000000
-#define BCHP_HIF_INTR2_PCI_CLEAR_PCIE_0_LINKDOWN_INTR_SHIFT 31
-#define BCHP_HIF_INTR2_PCI_CLEAR_PCIE_0_LINKDOWN_INTR_DEFAULT 0x00000000
-
-/* HIF_INTR2 :: PCI_CLEAR :: PCIE_0_LINKUP_INTR [30:30] */
-#define BCHP_HIF_INTR2_PCI_CLEAR_PCIE_0_LINKUP_INTR_MASK 0x40000000
-#define BCHP_HIF_INTR2_PCI_CLEAR_PCIE_0_LINKUP_INTR_SHIFT 30
-#define BCHP_HIF_INTR2_PCI_CLEAR_PCIE_0_LINKUP_INTR_DEFAULT 0x00000000
-
-/* HIF_INTR2 :: PCI_CLEAR :: PCIE_1_LINKDOWN_INTR [29:29] */
-#define BCHP_HIF_INTR2_PCI_CLEAR_PCIE_1_LINKDOWN_INTR_MASK 0x20000000
-#define BCHP_HIF_INTR2_PCI_CLEAR_PCIE_1_LINKDOWN_INTR_SHIFT 29
-#define BCHP_HIF_INTR2_PCI_CLEAR_PCIE_1_LINKDOWN_INTR_DEFAULT 0x00000000
-
-/* HIF_INTR2 :: PCI_CLEAR :: PCIE_1_LINKUP_INTR [28:28] */
-#define BCHP_HIF_INTR2_PCI_CLEAR_PCIE_1_LINKUP_INTR_MASK 0x10000000
-#define BCHP_HIF_INTR2_PCI_CLEAR_PCIE_1_LINKUP_INTR_SHIFT 28
-#define BCHP_HIF_INTR2_PCI_CLEAR_PCIE_1_LINKUP_INTR_DEFAULT 0x00000000
-
-/* HIF_INTR2 :: PCI_CLEAR :: NAND_CORR_INTR [27:27] */
-#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_CORR_INTR_MASK 0x08000000
-#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_CORR_INTR_SHIFT 27
-#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_CORR_INTR_DEFAULT 0x00000000
-
-/* HIF_INTR2 :: PCI_CLEAR :: NAND_UNC_INTR [26:26] */
-#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_UNC_INTR_MASK 0x04000000
-#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_UNC_INTR_SHIFT 26
-#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_UNC_INTR_DEFAULT 0x00000000
-
-/* HIF_INTR2 :: PCI_CLEAR :: NAND_RBPIN_INTR [25:25] */
-#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_RBPIN_INTR_MASK 0x02000000
-#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_RBPIN_INTR_SHIFT 25
-#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_RBPIN_INTR_DEFAULT 0x00000000
-
-/* HIF_INTR2 :: PCI_CLEAR :: NAND_CTLRDY_INTR [24:24] */
-#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_CTLRDY_INTR_MASK 0x01000000
-#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_CTLRDY_INTR_SHIFT 24
-#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_CTLRDY_INTR_DEFAULT 0x00000000
-
-/* HIF_INTR2 :: PCI_CLEAR :: NAND_PGMPG_INTR [23:23] */
-#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_PGMPG_INTR_MASK 0x00800000
-#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_PGMPG_INTR_SHIFT 23
-#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_PGMPG_INTR_DEFAULT 0x00000000
-
-/* HIF_INTR2 :: PCI_CLEAR :: NAND_CPYBK_INTR [22:22] */
-#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_CPYBK_INTR_MASK 0x00400000
-#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_CPYBK_INTR_SHIFT 22
-#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_CPYBK_INTR_DEFAULT 0x00000000
-
-/* HIF_INTR2 :: PCI_CLEAR :: NAND_BLKERA_INTR [21:21] */
-#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_BLKERA_INTR_MASK 0x00200000
-#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_BLKERA_INTR_SHIFT 21
-#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_BLKERA_INTR_DEFAULT 0x00000000
-
-/* HIF_INTR2 :: PCI_CLEAR :: NAND_NP_READ_INTR [20:20] */
-#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_NP_READ_INTR_MASK 0x00100000
-#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_NP_READ_INTR_SHIFT 20
-#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_NP_READ_INTR_DEFAULT 0x00000000
-
-/* HIF_INTR2 :: PCI_CLEAR :: reserved0 [19:16] */
-#define BCHP_HIF_INTR2_PCI_CLEAR_reserved0_MASK 0x000f0000
-#define BCHP_HIF_INTR2_PCI_CLEAR_reserved0_SHIFT 16
-
-/* HIF_INTR2 :: PCI_CLEAR :: ITCH0_RD_INTR [15:15] */
-#define BCHP_HIF_INTR2_PCI_CLEAR_ITCH0_RD_INTR_MASK 0x00008000
-#define BCHP_HIF_INTR2_PCI_CLEAR_ITCH0_RD_INTR_SHIFT 15
-#define BCHP_HIF_INTR2_PCI_CLEAR_ITCH0_RD_INTR_DEFAULT 0x00000000
-
-/* HIF_INTR2 :: PCI_CLEAR :: reserved1 [14:14] */
-#define BCHP_HIF_INTR2_PCI_CLEAR_reserved1_MASK 0x00004000
-#define BCHP_HIF_INTR2_PCI_CLEAR_reserved1_SHIFT 14
-
-/* HIF_INTR2 :: PCI_CLEAR :: PCIE_0_RG_BRIDGE_INTR [13:13] */
-#define BCHP_HIF_INTR2_PCI_CLEAR_PCIE_0_RG_BRIDGE_INTR_MASK 0x00002000
-#define BCHP_HIF_INTR2_PCI_CLEAR_PCIE_0_RG_BRIDGE_INTR_SHIFT 13
-#define BCHP_HIF_INTR2_PCI_CLEAR_PCIE_0_RG_BRIDGE_INTR_DEFAULT 0x00000000
-
-/* HIF_INTR2 :: PCI_CLEAR :: PCIE_0_RGR_BRIDGE_INTR [12:12] */
-#define BCHP_HIF_INTR2_PCI_CLEAR_PCIE_0_RGR_BRIDGE_INTR_MASK 0x00001000
-#define BCHP_HIF_INTR2_PCI_CLEAR_PCIE_0_RGR_BRIDGE_INTR_SHIFT 12
-#define BCHP_HIF_INTR2_PCI_CLEAR_PCIE_0_RGR_BRIDGE_INTR_DEFAULT 0x00000000
-
-/* HIF_INTR2 :: PCI_CLEAR :: PCIE_1_RG_BRIDGE_INTR [11:11] */
-#define BCHP_HIF_INTR2_PCI_CLEAR_PCIE_1_RG_BRIDGE_INTR_MASK 0x00000800
-#define BCHP_HIF_INTR2_PCI_CLEAR_PCIE_1_RG_BRIDGE_INTR_SHIFT 11
-#define BCHP_HIF_INTR2_PCI_CLEAR_PCIE_1_RG_BRIDGE_INTR_DEFAULT 0x00000000
-
-/* HIF_INTR2 :: PCI_CLEAR :: PCIE_1_RGR_BRIDGE_INTR [10:10] */
-#define BCHP_HIF_INTR2_PCI_CLEAR_PCIE_1_RGR_BRIDGE_INTR_MASK 0x00000400
-#define BCHP_HIF_INTR2_PCI_CLEAR_PCIE_1_RGR_BRIDGE_INTR_SHIFT 10
-#define BCHP_HIF_INTR2_PCI_CLEAR_PCIE_1_RGR_BRIDGE_INTR_DEFAULT 0x00000000
-
-/* HIF_INTR2 :: PCI_CLEAR :: reserved2 [09:06] */
-#define BCHP_HIF_INTR2_PCI_CLEAR_reserved2_MASK 0x000003c0
-#define BCHP_HIF_INTR2_PCI_CLEAR_reserved2_SHIFT 6
-
-/* HIF_INTR2 :: PCI_CLEAR :: FLASH_DMA_ERR_INTR [05:05] */
-#define BCHP_HIF_INTR2_PCI_CLEAR_FLASH_DMA_ERR_INTR_MASK 0x00000020
-#define BCHP_HIF_INTR2_PCI_CLEAR_FLASH_DMA_ERR_INTR_SHIFT 5
-#define BCHP_HIF_INTR2_PCI_CLEAR_FLASH_DMA_ERR_INTR_DEFAULT 0x00000000
-
-/* HIF_INTR2 :: PCI_CLEAR :: FLASH_DMA_DONE_INTR [04:04] */
-#define BCHP_HIF_INTR2_PCI_CLEAR_FLASH_DMA_DONE_INTR_MASK 0x00000010
-#define BCHP_HIF_INTR2_PCI_CLEAR_FLASH_DMA_DONE_INTR_SHIFT 4
-#define BCHP_HIF_INTR2_PCI_CLEAR_FLASH_DMA_DONE_INTR_DEFAULT 0x00000000
-
-/* HIF_INTR2 :: PCI_CLEAR :: WEBHIF_WD_TIMEOUT_INTR [03:03] */
-#define BCHP_HIF_INTR2_PCI_CLEAR_WEBHIF_WD_TIMEOUT_INTR_MASK 0x00000008
-#define BCHP_HIF_INTR2_PCI_CLEAR_WEBHIF_WD_TIMEOUT_INTR_SHIFT 3
-#define BCHP_HIF_INTR2_PCI_CLEAR_WEBHIF_WD_TIMEOUT_INTR_DEFAULT 0x00000000
-
-/* HIF_INTR2 :: PCI_CLEAR :: reserved3 [02:02] */
-#define BCHP_HIF_INTR2_PCI_CLEAR_reserved3_MASK 0x00000004
-#define BCHP_HIF_INTR2_PCI_CLEAR_reserved3_SHIFT 2
-
-/* HIF_INTR2 :: PCI_CLEAR :: ITCH1_RD_INTR [01:01] */
-#define BCHP_HIF_INTR2_PCI_CLEAR_ITCH1_RD_INTR_MASK 0x00000002
-#define BCHP_HIF_INTR2_PCI_CLEAR_ITCH1_RD_INTR_SHIFT 1
-#define BCHP_HIF_INTR2_PCI_CLEAR_ITCH1_RD_INTR_DEFAULT 0x00000000
-
-/* HIF_INTR2 :: PCI_CLEAR :: HIF_RGR2_BRIDGE_INTR [00:00] */
-#define BCHP_HIF_INTR2_PCI_CLEAR_HIF_RGR2_BRIDGE_INTR_MASK 0x00000001
-#define BCHP_HIF_INTR2_PCI_CLEAR_HIF_RGR2_BRIDGE_INTR_SHIFT 0
-#define BCHP_HIF_INTR2_PCI_CLEAR_HIF_RGR2_BRIDGE_INTR_DEFAULT 0x00000000
-
-/***************************************************************************
- *PCI_MASK_STATUS - PCI interrupt Mask Status Register
- ***************************************************************************/
-/* HIF_INTR2 :: PCI_MASK_STATUS :: PCIE_0_LINKDOWN_INTR [31:31] */
-#define BCHP_HIF_INTR2_PCI_MASK_STATUS_PCIE_0_LINKDOWN_INTR_MASK 0x80000000
-#define BCHP_HIF_INTR2_PCI_MASK_STATUS_PCIE_0_LINKDOWN_INTR_SHIFT 31
-#define BCHP_HIF_INTR2_PCI_MASK_STATUS_PCIE_0_LINKDOWN_INTR_DEFAULT 0x00000000
-
-/* HIF_INTR2 :: PCI_MASK_STATUS :: PCIE_0_LINKUP_INTR [30:30] */
-#define BCHP_HIF_INTR2_PCI_MASK_STATUS_PCIE_0_LINKUP_INTR_MASK 0x40000000
-#define BCHP_HIF_INTR2_PCI_MASK_STATUS_PCIE_0_LINKUP_INTR_SHIFT 30
-#define BCHP_HIF_INTR2_PCI_MASK_STATUS_PCIE_0_LINKUP_INTR_DEFAULT 0x00000000
-
-/* HIF_INTR2 :: PCI_MASK_STATUS :: PCIE_1_LINKDOWN_INTR [29:29] */
-#define BCHP_HIF_INTR2_PCI_MASK_STATUS_PCIE_1_LINKDOWN_INTR_MASK 0x20000000
-#define BCHP_HIF_INTR2_PCI_MASK_STATUS_PCIE_1_LINKDOWN_INTR_SHIFT 29
-#define BCHP_HIF_INTR2_PCI_MASK_STATUS_PCIE_1_LINKDOWN_INTR_DEFAULT 0x00000000
-
-/* HIF_INTR2 :: PCI_MASK_STATUS :: PCIE_1_LINKUP_INTR [28:28] */
-#define BCHP_HIF_INTR2_PCI_MASK_STATUS_PCIE_1_LINKUP_INTR_MASK 0x10000000
-#define BCHP_HIF_INTR2_PCI_MASK_STATUS_PCIE_1_LINKUP_INTR_SHIFT 28
-#define BCHP_HIF_INTR2_PCI_MASK_STATUS_PCIE_1_LINKUP_INTR_DEFAULT 0x00000000
-
-/* HIF_INTR2 :: PCI_MASK_STATUS :: NAND_CORR_INTR [27:27] */
-#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_CORR_INTR_MASK 0x08000000
-#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_CORR_INTR_SHIFT 27
-#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_CORR_INTR_DEFAULT 0x00000001
-
-/* HIF_INTR2 :: PCI_MASK_STATUS :: NAND_UNC_INTR [26:26] */
-#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_UNC_INTR_MASK 0x04000000
-#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_UNC_INTR_SHIFT 26
-#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_UNC_INTR_DEFAULT 0x00000001
-
-/* HIF_INTR2 :: PCI_MASK_STATUS :: NAND_RBPIN_INTR [25:25] */
-#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_RBPIN_INTR_MASK 0x02000000
-#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_RBPIN_INTR_SHIFT 25
-#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_RBPIN_INTR_DEFAULT 0x00000001
-
-/* HIF_INTR2 :: PCI_MASK_STATUS :: NAND_CTLRDY_INTR [24:24] */
-#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_CTLRDY_INTR_MASK 0x01000000
-#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_CTLRDY_INTR_SHIFT 24
-#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_CTLRDY_INTR_DEFAULT 0x00000001
-
-/* HIF_INTR2 :: PCI_MASK_STATUS :: NAND_PGMPG_INTR [23:23] */
-#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_PGMPG_INTR_MASK 0x00800000
-#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_PGMPG_INTR_SHIFT 23
-#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_PGMPG_INTR_DEFAULT 0x00000001
-
-/* HIF_INTR2 :: PCI_MASK_STATUS :: NAND_CPYBK_INTR [22:22] */
-#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_CPYBK_INTR_MASK 0x00400000
-#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_CPYBK_INTR_SHIFT 22
-#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_CPYBK_INTR_DEFAULT 0x00000001
-
-/* HIF_INTR2 :: PCI_MASK_STATUS :: NAND_BLKERA_INTR [21:21] */
-#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_BLKERA_INTR_MASK 0x00200000
-#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_BLKERA_INTR_SHIFT 21
-#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_BLKERA_INTR_DEFAULT 0x00000001
-
-/* HIF_INTR2 :: PCI_MASK_STATUS :: NAND_NP_READ_INTR [20:20] */
-#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_NP_READ_INTR_MASK 0x00100000
-#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_NP_READ_INTR_SHIFT 20
-#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_NP_READ_INTR_DEFAULT 0x00000001
-
-/* HIF_INTR2 :: PCI_MASK_STATUS :: reserved0 [19:16] */
-#define BCHP_HIF_INTR2_PCI_MASK_STATUS_reserved0_MASK 0x000f0000
-#define BCHP_HIF_INTR2_PCI_MASK_STATUS_reserved0_SHIFT 16
-
-/* HIF_INTR2 :: PCI_MASK_STATUS :: ITCH0_RD_INTR [15:15] */
-#define BCHP_HIF_INTR2_PCI_MASK_STATUS_ITCH0_RD_INTR_MASK 0x00008000
-#define BCHP_HIF_INTR2_PCI_MASK_STATUS_ITCH0_RD_INTR_SHIFT 15
-#define BCHP_HIF_INTR2_PCI_MASK_STATUS_ITCH0_RD_INTR_DEFAULT 0x00000001
-
-/* HIF_INTR2 :: PCI_MASK_STATUS :: reserved1 [14:14] */
-#define BCHP_HIF_INTR2_PCI_MASK_STATUS_reserved1_MASK 0x00004000
-#define BCHP_HIF_INTR2_PCI_MASK_STATUS_reserved1_SHIFT 14
-
-/* HIF_INTR2 :: PCI_MASK_STATUS :: PCIE_0_RG_BRIDGE_INTR [13:13] */
-#define BCHP_HIF_INTR2_PCI_MASK_STATUS_PCIE_0_RG_BRIDGE_INTR_MASK 0x00002000
-#define BCHP_HIF_INTR2_PCI_MASK_STATUS_PCIE_0_RG_BRIDGE_INTR_SHIFT 13
-#define BCHP_HIF_INTR2_PCI_MASK_STATUS_PCIE_0_RG_BRIDGE_INTR_DEFAULT 0x00000001
-
-/* HIF_INTR2 :: PCI_MASK_STATUS :: PCIE_0_RGR_BRIDGE_INTR [12:12] */
-#define BCHP_HIF_INTR2_PCI_MASK_STATUS_PCIE_0_RGR_BRIDGE_INTR_MASK 0x00001000
-#define BCHP_HIF_INTR2_PCI_MASK_STATUS_PCIE_0_RGR_BRIDGE_INTR_SHIFT 12
-#define BCHP_HIF_INTR2_PCI_MASK_STATUS_PCIE_0_RGR_BRIDGE_INTR_DEFAULT 0x00000001
-
-/* HIF_INTR2 :: PCI_MASK_STATUS :: PCIE_1_RG_BRIDGE_INTR [11:11] */
-#define BCHP_HIF_INTR2_PCI_MASK_STATUS_PCIE_1_RG_BRIDGE_INTR_MASK 0x00000800
-#define BCHP_HIF_INTR2_PCI_MASK_STATUS_PCIE_1_RG_BRIDGE_INTR_SHIFT 11
-#define BCHP_HIF_INTR2_PCI_MASK_STATUS_PCIE_1_RG_BRIDGE_INTR_DEFAULT 0x00000001
-
-/* HIF_INTR2 :: PCI_MASK_STATUS :: PCIE_1_RGR_BRIDGE_INTR [10:10] */
-#define BCHP_HIF_INTR2_PCI_MASK_STATUS_PCIE_1_RGR_BRIDGE_INTR_MASK 0x00000400
-#define BCHP_HIF_INTR2_PCI_MASK_STATUS_PCIE_1_RGR_BRIDGE_INTR_SHIFT 10
-#define BCHP_HIF_INTR2_PCI_MASK_STATUS_PCIE_1_RGR_BRIDGE_INTR_DEFAULT 0x00000001
-
-/* HIF_INTR2 :: PCI_MASK_STATUS :: reserved2 [09:06] */
-#define BCHP_HIF_INTR2_PCI_MASK_STATUS_reserved2_MASK 0x000003c0
-#define BCHP_HIF_INTR2_PCI_MASK_STATUS_reserved2_SHIFT 6
-
-/* HIF_INTR2 :: PCI_MASK_STATUS :: FLASH_DMA_ERR_INTR [05:05] */
-#define BCHP_HIF_INTR2_PCI_MASK_STATUS_FLASH_DMA_ERR_INTR_MASK 0x00000020
-#define BCHP_HIF_INTR2_PCI_MASK_STATUS_FLASH_DMA_ERR_INTR_SHIFT 5
-#define BCHP_HIF_INTR2_PCI_MASK_STATUS_FLASH_DMA_ERR_INTR_DEFAULT 0x00000000
-
-/* HIF_INTR2 :: PCI_MASK_STATUS :: FLASH_DMA_DONE_INTR [04:04] */
-#define BCHP_HIF_INTR2_PCI_MASK_STATUS_FLASH_DMA_DONE_INTR_MASK 0x00000010
-#define BCHP_HIF_INTR2_PCI_MASK_STATUS_FLASH_DMA_DONE_INTR_SHIFT 4
-#define BCHP_HIF_INTR2_PCI_MASK_STATUS_FLASH_DMA_DONE_INTR_DEFAULT 0x00000000
-
-/* HIF_INTR2 :: PCI_MASK_STATUS :: WEBHIF_WD_TIMEOUT_INTR [03:03] */
-#define BCHP_HIF_INTR2_PCI_MASK_STATUS_WEBHIF_WD_TIMEOUT_INTR_MASK 0x00000008
-#define BCHP_HIF_INTR2_PCI_MASK_STATUS_WEBHIF_WD_TIMEOUT_INTR_SHIFT 3
-#define BCHP_HIF_INTR2_PCI_MASK_STATUS_WEBHIF_WD_TIMEOUT_INTR_DEFAULT 0x00000000
-
-/* HIF_INTR2 :: PCI_MASK_STATUS :: reserved3 [02:02] */
-#define BCHP_HIF_INTR2_PCI_MASK_STATUS_reserved3_MASK 0x00000004
-#define BCHP_HIF_INTR2_PCI_MASK_STATUS_reserved3_SHIFT 2
-
-/* HIF_INTR2 :: PCI_MASK_STATUS :: ITCH1_RD_INTR [01:01] */
-#define BCHP_HIF_INTR2_PCI_MASK_STATUS_ITCH1_RD_INTR_MASK 0x00000002
-#define BCHP_HIF_INTR2_PCI_MASK_STATUS_ITCH1_RD_INTR_SHIFT 1
-#define BCHP_HIF_INTR2_PCI_MASK_STATUS_ITCH1_RD_INTR_DEFAULT 0x00000001
-
-/* HIF_INTR2 :: PCI_MASK_STATUS :: HIF_RGR2_BRIDGE_INTR [00:00] */
-#define BCHP_HIF_INTR2_PCI_MASK_STATUS_HIF_RGR2_BRIDGE_INTR_MASK 0x00000001
-#define BCHP_HIF_INTR2_PCI_MASK_STATUS_HIF_RGR2_BRIDGE_INTR_SHIFT 0
-#define BCHP_HIF_INTR2_PCI_MASK_STATUS_HIF_RGR2_BRIDGE_INTR_DEFAULT 0x00000001
-
-/***************************************************************************
- *PCI_MASK_SET - PCI interrupt Mask Set Register
- ***************************************************************************/
-/* HIF_INTR2 :: PCI_MASK_SET :: PCIE_0_LINKDOWN_INTR [31:31] */
-#define BCHP_HIF_INTR2_PCI_MASK_SET_PCIE_0_LINKDOWN_INTR_MASK 0x80000000
-#define BCHP_HIF_INTR2_PCI_MASK_SET_PCIE_0_LINKDOWN_INTR_SHIFT 31
-#define BCHP_HIF_INTR2_PCI_MASK_SET_PCIE_0_LINKDOWN_INTR_DEFAULT 0x00000000
-
-/* HIF_INTR2 :: PCI_MASK_SET :: PCIE_0_LINKUP_INTR [30:30] */
-#define BCHP_HIF_INTR2_PCI_MASK_SET_PCIE_0_LINKUP_INTR_MASK 0x40000000
-#define BCHP_HIF_INTR2_PCI_MASK_SET_PCIE_0_LINKUP_INTR_SHIFT 30
-#define BCHP_HIF_INTR2_PCI_MASK_SET_PCIE_0_LINKUP_INTR_DEFAULT 0x00000000
-
-/* HIF_INTR2 :: PCI_MASK_SET :: PCIE_1_LINKDOWN_INTR [29:29] */
-#define BCHP_HIF_INTR2_PCI_MASK_SET_PCIE_1_LINKDOWN_INTR_MASK 0x20000000
-#define BCHP_HIF_INTR2_PCI_MASK_SET_PCIE_1_LINKDOWN_INTR_SHIFT 29
-#define BCHP_HIF_INTR2_PCI_MASK_SET_PCIE_1_LINKDOWN_INTR_DEFAULT 0x00000000
-
-/* HIF_INTR2 :: PCI_MASK_SET :: PCIE_1_LINKUP_INTR [28:28] */
-#define BCHP_HIF_INTR2_PCI_MASK_SET_PCIE_1_LINKUP_INTR_MASK 0x10000000
-#define BCHP_HIF_INTR2_PCI_MASK_SET_PCIE_1_LINKUP_INTR_SHIFT 28
-#define BCHP_HIF_INTR2_PCI_MASK_SET_PCIE_1_LINKUP_INTR_DEFAULT 0x00000000
-
-/* HIF_INTR2 :: PCI_MASK_SET :: NAND_CORR_INTR [27:27] */
-#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_CORR_INTR_MASK 0x08000000
-#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_CORR_INTR_SHIFT 27
-#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_CORR_INTR_DEFAULT 0x00000001
-
-/* HIF_INTR2 :: PCI_MASK_SET :: NAND_UNC_INTR [26:26] */
-#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_UNC_INTR_MASK 0x04000000
-#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_UNC_INTR_SHIFT 26
-#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_UNC_INTR_DEFAULT 0x00000001
-
-/* HIF_INTR2 :: PCI_MASK_SET :: NAND_RBPIN_INTR [25:25] */
-#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_RBPIN_INTR_MASK 0x02000000
-#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_RBPIN_INTR_SHIFT 25
-#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_RBPIN_INTR_DEFAULT 0x00000001
-
-/* HIF_INTR2 :: PCI_MASK_SET :: NAND_CTLRDY_INTR [24:24] */
-#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_CTLRDY_INTR_MASK 0x01000000
-#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_CTLRDY_INTR_SHIFT 24
-#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_CTLRDY_INTR_DEFAULT 0x00000001
-
-/* HIF_INTR2 :: PCI_MASK_SET :: NAND_PGMPG_INTR [23:23] */
-#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_PGMPG_INTR_MASK 0x00800000
-#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_PGMPG_INTR_SHIFT 23
-#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_PGMPG_INTR_DEFAULT 0x00000001
-
-/* HIF_INTR2 :: PCI_MASK_SET :: NAND_CPYBK_INTR [22:22] */
-#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_CPYBK_INTR_MASK 0x00400000
-#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_CPYBK_INTR_SHIFT 22
-#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_CPYBK_INTR_DEFAULT 0x00000001
-
-/* HIF_INTR2 :: PCI_MASK_SET :: NAND_BLKERA_INTR [21:21] */
-#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_BLKERA_INTR_MASK 0x00200000
-#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_BLKERA_INTR_SHIFT 21
-#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_BLKERA_INTR_DEFAULT 0x00000001
-
-/* HIF_INTR2 :: PCI_MASK_SET :: NAND_NP_READ_INTR [20:20] */
-#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_NP_READ_INTR_MASK 0x00100000
-#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_NP_READ_INTR_SHIFT 20
-#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_NP_READ_INTR_DEFAULT 0x00000001
-
-/* HIF_INTR2 :: PCI_MASK_SET :: reserved0 [19:16] */
-#define BCHP_HIF_INTR2_PCI_MASK_SET_reserved0_MASK 0x000f0000
-#define BCHP_HIF_INTR2_PCI_MASK_SET_reserved0_SHIFT 16
-
-/* HIF_INTR2 :: PCI_MASK_SET :: ITCH0_RD_INTR [15:15] */
-#define BCHP_HIF_INTR2_PCI_MASK_SET_ITCH0_RD_INTR_MASK 0x00008000
-#define BCHP_HIF_INTR2_PCI_MASK_SET_ITCH0_RD_INTR_SHIFT 15
-#define BCHP_HIF_INTR2_PCI_MASK_SET_ITCH0_RD_INTR_DEFAULT 0x00000001
-
-/* HIF_INTR2 :: PCI_MASK_SET :: reserved1 [14:14] */
-#define BCHP_HIF_INTR2_PCI_MASK_SET_reserved1_MASK 0x00004000
-#define BCHP_HIF_INTR2_PCI_MASK_SET_reserved1_SHIFT 14
-
-/* HIF_INTR2 :: PCI_MASK_SET :: PCIE_0_RG_BRIDGE_INTR [13:13] */
-#define BCHP_HIF_INTR2_PCI_MASK_SET_PCIE_0_RG_BRIDGE_INTR_MASK 0x00002000
-#define BCHP_HIF_INTR2_PCI_MASK_SET_PCIE_0_RG_BRIDGE_INTR_SHIFT 13
-#define BCHP_HIF_INTR2_PCI_MASK_SET_PCIE_0_RG_BRIDGE_INTR_DEFAULT 0x00000001
-
-/* HIF_INTR2 :: PCI_MASK_SET :: PCIE_0_RGR_BRIDGE_INTR [12:12] */
-#define BCHP_HIF_INTR2_PCI_MASK_SET_PCIE_0_RGR_BRIDGE_INTR_MASK 0x00001000
-#define BCHP_HIF_INTR2_PCI_MASK_SET_PCIE_0_RGR_BRIDGE_INTR_SHIFT 12
-#define BCHP_HIF_INTR2_PCI_MASK_SET_PCIE_0_RGR_BRIDGE_INTR_DEFAULT 0x00000001
-
-/* HIF_INTR2 :: PCI_MASK_SET :: PCIE_1_RG_BRIDGE_INTR [11:11] */
-#define BCHP_HIF_INTR2_PCI_MASK_SET_PCIE_1_RG_BRIDGE_INTR_MASK 0x00000800
-#define BCHP_HIF_INTR2_PCI_MASK_SET_PCIE_1_RG_BRIDGE_INTR_SHIFT 11
-#define BCHP_HIF_INTR2_PCI_MASK_SET_PCIE_1_RG_BRIDGE_INTR_DEFAULT 0x00000001
-
-/* HIF_INTR2 :: PCI_MASK_SET :: PCIE_1_RGR_BRIDGE_INTR [10:10] */
-#define BCHP_HIF_INTR2_PCI_MASK_SET_PCIE_1_RGR_BRIDGE_INTR_MASK 0x00000400
-#define BCHP_HIF_INTR2_PCI_MASK_SET_PCIE_1_RGR_BRIDGE_INTR_SHIFT 10
-#define BCHP_HIF_INTR2_PCI_MASK_SET_PCIE_1_RGR_BRIDGE_INTR_DEFAULT 0x00000001
-
-/* HIF_INTR2 :: PCI_MASK_SET :: reserved2 [09:06] */
-#define BCHP_HIF_INTR2_PCI_MASK_SET_reserved2_MASK 0x000003c0
-#define BCHP_HIF_INTR2_PCI_MASK_SET_reserved2_SHIFT 6
-
-/* HIF_INTR2 :: PCI_MASK_SET :: FLASH_DMA_ERR_INTR [05:05] */
-#define BCHP_HIF_INTR2_PCI_MASK_SET_FLASH_DMA_ERR_INTR_MASK 0x00000020
-#define BCHP_HIF_INTR2_PCI_MASK_SET_FLASH_DMA_ERR_INTR_SHIFT 5
-#define BCHP_HIF_INTR2_PCI_MASK_SET_FLASH_DMA_ERR_INTR_DEFAULT 0x00000000
-
-/* HIF_INTR2 :: PCI_MASK_SET :: FLASH_DMA_DONE_INTR [04:04] */
-#define BCHP_HIF_INTR2_PCI_MASK_SET_FLASH_DMA_DONE_INTR_MASK 0x00000010
-#define BCHP_HIF_INTR2_PCI_MASK_SET_FLASH_DMA_DONE_INTR_SHIFT 4
-#define BCHP_HIF_INTR2_PCI_MASK_SET_FLASH_DMA_DONE_INTR_DEFAULT 0x00000000
-
-/* HIF_INTR2 :: PCI_MASK_SET :: WEBHIF_WD_TIMEOUT_INTR [03:03] */
-#define BCHP_HIF_INTR2_PCI_MASK_SET_WEBHIF_WD_TIMEOUT_INTR_MASK 0x00000008
-#define BCHP_HIF_INTR2_PCI_MASK_SET_WEBHIF_WD_TIMEOUT_INTR_SHIFT 3
-#define BCHP_HIF_INTR2_PCI_MASK_SET_WEBHIF_WD_TIMEOUT_INTR_DEFAULT 0x00000000
-
-/* HIF_INTR2 :: PCI_MASK_SET :: reserved3 [02:02] */
-#define BCHP_HIF_INTR2_PCI_MASK_SET_reserved3_MASK 0x00000004
-#define BCHP_HIF_INTR2_PCI_MASK_SET_reserved3_SHIFT 2
-
-/* HIF_INTR2 :: PCI_MASK_SET :: ITCH1_RD_INTR [01:01] */
-#define BCHP_HIF_INTR2_PCI_MASK_SET_ITCH1_RD_INTR_MASK 0x00000002
-#define BCHP_HIF_INTR2_PCI_MASK_SET_ITCH1_RD_INTR_SHIFT 1
-#define BCHP_HIF_INTR2_PCI_MASK_SET_ITCH1_RD_INTR_DEFAULT 0x00000001
-
-/* HIF_INTR2 :: PCI_MASK_SET :: HIF_RGR2_BRIDGE_INTR [00:00] */
-#define BCHP_HIF_INTR2_PCI_MASK_SET_HIF_RGR2_BRIDGE_INTR_MASK 0x00000001
-#define BCHP_HIF_INTR2_PCI_MASK_SET_HIF_RGR2_BRIDGE_INTR_SHIFT 0
-#define BCHP_HIF_INTR2_PCI_MASK_SET_HIF_RGR2_BRIDGE_INTR_DEFAULT 0x00000001
-
-/***************************************************************************
- *PCI_MASK_CLEAR - PCI interrupt Mask Clear Register
- ***************************************************************************/
-/* HIF_INTR2 :: PCI_MASK_CLEAR :: PCIE_0_LINKDOWN_INTR [31:31] */
-#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_PCIE_0_LINKDOWN_INTR_MASK 0x80000000
-#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_PCIE_0_LINKDOWN_INTR_SHIFT 31
-#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_PCIE_0_LINKDOWN_INTR_DEFAULT 0x00000000
-
-/* HIF_INTR2 :: PCI_MASK_CLEAR :: PCIE_0_LINKUP_INTR [30:30] */
-#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_PCIE_0_LINKUP_INTR_MASK 0x40000000
-#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_PCIE_0_LINKUP_INTR_SHIFT 30
-#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_PCIE_0_LINKUP_INTR_DEFAULT 0x00000000
-
-/* HIF_INTR2 :: PCI_MASK_CLEAR :: PCIE_1_LINKDOWN_INTR [29:29] */
-#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_PCIE_1_LINKDOWN_INTR_MASK 0x20000000
-#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_PCIE_1_LINKDOWN_INTR_SHIFT 29
-#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_PCIE_1_LINKDOWN_INTR_DEFAULT 0x00000000
-
-/* HIF_INTR2 :: PCI_MASK_CLEAR :: PCIE_1_LINKUP_INTR [28:28] */
-#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_PCIE_1_LINKUP_INTR_MASK 0x10000000
-#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_PCIE_1_LINKUP_INTR_SHIFT 28
-#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_PCIE_1_LINKUP_INTR_DEFAULT 0x00000000
-
-/* HIF_INTR2 :: PCI_MASK_CLEAR :: NAND_CORR_INTR [27:27] */
-#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_CORR_INTR_MASK 0x08000000
-#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_CORR_INTR_SHIFT 27
-#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_CORR_INTR_DEFAULT 0x00000001
-
-/* HIF_INTR2 :: PCI_MASK_CLEAR :: NAND_UNC_INTR [26:26] */
-#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_UNC_INTR_MASK 0x04000000
-#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_UNC_INTR_SHIFT 26
-#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_UNC_INTR_DEFAULT 0x00000001
-
-/* HIF_INTR2 :: PCI_MASK_CLEAR :: NAND_RBPIN_INTR [25:25] */
-#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_RBPIN_INTR_MASK 0x02000000
-#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_RBPIN_INTR_SHIFT 25
-#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_RBPIN_INTR_DEFAULT 0x00000001
-
-/* HIF_INTR2 :: PCI_MASK_CLEAR :: NAND_CTLRDY_INTR [24:24] */
-#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_CTLRDY_INTR_MASK 0x01000000
-#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_CTLRDY_INTR_SHIFT 24
-#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_CTLRDY_INTR_DEFAULT 0x00000001
-
-/* HIF_INTR2 :: PCI_MASK_CLEAR :: NAND_PGMPG_INTR [23:23] */
-#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_PGMPG_INTR_MASK 0x00800000
-#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_PGMPG_INTR_SHIFT 23
-#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_PGMPG_INTR_DEFAULT 0x00000001
-
-/* HIF_INTR2 :: PCI_MASK_CLEAR :: NAND_CPYBK_INTR [22:22] */
-#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_CPYBK_INTR_MASK 0x00400000
-#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_CPYBK_INTR_SHIFT 22
-#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_CPYBK_INTR_DEFAULT 0x00000001
-
-/* HIF_INTR2 :: PCI_MASK_CLEAR :: NAND_BLKERA_INTR [21:21] */
-#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_BLKERA_INTR_MASK 0x00200000
-#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_BLKERA_INTR_SHIFT 21
-#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_BLKERA_INTR_DEFAULT 0x00000001
-
-/* HIF_INTR2 :: PCI_MASK_CLEAR :: NAND_NP_READ_INTR [20:20] */
-#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_NP_READ_INTR_MASK 0x00100000
-#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_NP_READ_INTR_SHIFT 20
-#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_NP_READ_INTR_DEFAULT 0x00000001
-
-/* HIF_INTR2 :: PCI_MASK_CLEAR :: reserved0 [19:16] */
-#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_reserved0_MASK 0x000f0000
-#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_reserved0_SHIFT 16
-
-/* HIF_INTR2 :: PCI_MASK_CLEAR :: ITCH0_RD_INTR [15:15] */
-#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_ITCH0_RD_INTR_MASK 0x00008000
-#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_ITCH0_RD_INTR_SHIFT 15
-#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_ITCH0_RD_INTR_DEFAULT 0x00000001
-
-/* HIF_INTR2 :: PCI_MASK_CLEAR :: reserved1 [14:14] */
-#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_reserved1_MASK 0x00004000
-#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_reserved1_SHIFT 14
-
-/* HIF_INTR2 :: PCI_MASK_CLEAR :: PCIE_0_RG_BRIDGE_INTR [13:13] */
-#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_PCIE_0_RG_BRIDGE_INTR_MASK 0x00002000
-#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_PCIE_0_RG_BRIDGE_INTR_SHIFT 13
-#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_PCIE_0_RG_BRIDGE_INTR_DEFAULT 0x00000001
-
-/* HIF_INTR2 :: PCI_MASK_CLEAR :: PCIE_0_RGR_BRIDGE_INTR [12:12] */
-#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_PCIE_0_RGR_BRIDGE_INTR_MASK 0x00001000
-#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_PCIE_0_RGR_BRIDGE_INTR_SHIFT 12
-#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_PCIE_0_RGR_BRIDGE_INTR_DEFAULT 0x00000001
-
-/* HIF_INTR2 :: PCI_MASK_CLEAR :: PCIE_1_RG_BRIDGE_INTR [11:11] */
-#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_PCIE_1_RG_BRIDGE_INTR_MASK 0x00000800
-#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_PCIE_1_RG_BRIDGE_INTR_SHIFT 11
-#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_PCIE_1_RG_BRIDGE_INTR_DEFAULT 0x00000001
-
-/* HIF_INTR2 :: PCI_MASK_CLEAR :: PCIE_1_RGR_BRIDGE_INTR [10:10] */
-#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_PCIE_1_RGR_BRIDGE_INTR_MASK 0x00000400
-#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_PCIE_1_RGR_BRIDGE_INTR_SHIFT 10
-#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_PCIE_1_RGR_BRIDGE_INTR_DEFAULT 0x00000001
-
-/* HIF_INTR2 :: PCI_MASK_CLEAR :: reserved2 [09:06] */
-#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_reserved2_MASK 0x000003c0
-#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_reserved2_SHIFT 6
-
-/* HIF_INTR2 :: PCI_MASK_CLEAR :: FLASH_DMA_ERR_INTR [05:05] */
-#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_FLASH_DMA_ERR_INTR_MASK 0x00000020
-#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_FLASH_DMA_ERR_INTR_SHIFT 5
-#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_FLASH_DMA_ERR_INTR_DEFAULT 0x00000000
-
-/* HIF_INTR2 :: PCI_MASK_CLEAR :: FLASH_DMA_DONE_INTR [04:04] */
-#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_FLASH_DMA_DONE_INTR_MASK 0x00000010
-#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_FLASH_DMA_DONE_INTR_SHIFT 4
-#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_FLASH_DMA_DONE_INTR_DEFAULT 0x00000000
-
-/* HIF_INTR2 :: PCI_MASK_CLEAR :: WEBHIF_WD_TIMEOUT_INTR [03:03] */
-#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_WEBHIF_WD_TIMEOUT_INTR_MASK 0x00000008
-#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_WEBHIF_WD_TIMEOUT_INTR_SHIFT 3
-#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_WEBHIF_WD_TIMEOUT_INTR_DEFAULT 0x00000000
-
-/* HIF_INTR2 :: PCI_MASK_CLEAR :: reserved3 [02:02] */
-#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_reserved3_MASK 0x00000004
-#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_reserved3_SHIFT 2
-
-/* HIF_INTR2 :: PCI_MASK_CLEAR :: ITCH1_RD_INTR [01:01] */
-#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_ITCH1_RD_INTR_MASK 0x00000002
-#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_ITCH1_RD_INTR_SHIFT 1
-#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_ITCH1_RD_INTR_DEFAULT 0x00000001
-
-/* HIF_INTR2 :: PCI_MASK_CLEAR :: HIF_RGR2_BRIDGE_INTR [00:00] */
-#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_HIF_RGR2_BRIDGE_INTR_MASK 0x00000001
-#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_HIF_RGR2_BRIDGE_INTR_SHIFT 0
-#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_HIF_RGR2_BRIDGE_INTR_DEFAULT 0x00000001
-
-#endif /* #ifndef BCHP_HIF_INTR2_H__ */
-
-/* End of File */
diff --git a/include/linux/brcmstb/7366b0/bchp_hif_mspi.h b/include/linux/brcmstb/7366b0/bchp_hif_mspi.h
deleted file mode 100644
index e537c46..0000000
--- a/include/linux/brcmstb/7366b0/bchp_hif_mspi.h
+++ /dev/null
@@ -1,1289 +0,0 @@
-/***************************************************************************
- * Copyright (c) 1999-2012, Broadcom Corporation
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
- *
- * Module Description:
- * DO NOT EDIT THIS FILE DIRECTLY
- *
- * This module was generated magically with RDB from a source description
- * file. You must edit the source file for changes to be made to this file.
- *
- *
- * Date: Generated on Wed Oct 17 03:11:31 2012
- * MD5 Checksum d41d8cd98f00b204e9800998ecf8427e
- *
- * Compiled with: RDB Utility combo_header.pl
- * RDB Parser 3.0
- * unknown unknown
- * Perl Interpreter 5.008008
- * Operating System linux
- *
- * Revision History:
- *
- * $brcm_Log: $
- *
- ***************************************************************************/
-
-#ifndef BCHP_HIF_MSPI_H__
-#define BCHP_HIF_MSPI_H__
-
-/***************************************************************************
- *HIF_MSPI - Public MSPI Registers
- ***************************************************************************/
-#define BCHP_HIF_MSPI_SPCR0_LSB 0x00443400 /* SPCR0_LSB REGISTER */
-#define BCHP_HIF_MSPI_SPCR0_MSB 0x00443404 /* SPCR0_MSB Register */
-#define BCHP_HIF_MSPI_SPCR1_LSB 0x00443408 /* SPCR1_LSB REGISTER */
-#define BCHP_HIF_MSPI_SPCR1_MSB 0x0044340c /* SPCR1_MSB REGISTER */
-#define BCHP_HIF_MSPI_NEWQP 0x00443410 /* NEWQP REGISTER */
-#define BCHP_HIF_MSPI_ENDQP 0x00443414 /* ENDQP REGISTER */
-#define BCHP_HIF_MSPI_SPCR2 0x00443418 /* SPCR2 REGISTER */
-#define BCHP_HIF_MSPI_MSPI_STATUS 0x00443420 /* MSPI STATUS REGISTER */
-#define BCHP_HIF_MSPI_CPTQP 0x00443424 /* CPTQP REGISTER */
-#define BCHP_HIF_MSPI_SPCR3 0x00443428 /* SPCR3 REGISTER */
-#define BCHP_HIF_MSPI_REVISION 0x0044342c /* REVISION ID REGISTER */
-#define BCHP_HIF_MSPI_TXRAM00 0x00443440 /* Most significant byte of TXRAM[0] (queue pointer = 0) */
-#define BCHP_HIF_MSPI_TXRAM01 0x00443444 /* Least significant byte of TXRAM[0] (queue pointer = 0) */
-#define BCHP_HIF_MSPI_TXRAM02 0x00443448 /* Most significant byte of TXRAM[1] (queue pointer = 1) */
-#define BCHP_HIF_MSPI_TXRAM03 0x0044344c /* Least significant byte of TXRAM[1] (queue pointer = 1) */
-#define BCHP_HIF_MSPI_TXRAM04 0x00443450 /* Most significant byte of TXRAM[2] (queue pointer = 2) */
-#define BCHP_HIF_MSPI_TXRAM05 0x00443454 /* Least significant byte of TXRAM[2] (queue pointer = 2) */
-#define BCHP_HIF_MSPI_TXRAM06 0x00443458 /* Most significant byte of TXRAM[3] (queue pointer = 3) */
-#define BCHP_HIF_MSPI_TXRAM07 0x0044345c /* Least significant byte of TXRAM[3] (queue pointer = 3) */
-#define BCHP_HIF_MSPI_TXRAM08 0x00443460 /* Most significant byte of TXRAM[4] (queue pointer = 4) */
-#define BCHP_HIF_MSPI_TXRAM09 0x00443464 /* Least significant byte of TXRAM[4] (queue pointer = 4) */
-#define BCHP_HIF_MSPI_TXRAM10 0x00443468 /* Most significant byte of TXRAM[5] (queue pointer = 5) */
-#define BCHP_HIF_MSPI_TXRAM11 0x0044346c /* Least significant byte of TXRAM[5] (queue pointer = 5) */
-#define BCHP_HIF_MSPI_TXRAM12 0x00443470 /* Most significant byte of TXRAM[6] (queue pointer = 6) */
-#define BCHP_HIF_MSPI_TXRAM13 0x00443474 /* Least significant byte of TXRAM[6] (queue pointer = 6) */
-#define BCHP_HIF_MSPI_TXRAM14 0x00443478 /* Most significant byte of TXRAM[7] (queue pointer = 7) */
-#define BCHP_HIF_MSPI_TXRAM15 0x0044347c /* Least significant byte of TXRAM[7] (queue pointer = 7) */
-#define BCHP_HIF_MSPI_TXRAM16 0x00443480 /* Most significant byte of TXRAM[8] (queue pointer = 8) */
-#define BCHP_HIF_MSPI_TXRAM17 0x00443484 /* Least significant byte of TXRAM[8] (queue pointer = 8) */
-#define BCHP_HIF_MSPI_TXRAM18 0x00443488 /* Most significant byte of TXRAM[9] (queue pointer = 9) */
-#define BCHP_HIF_MSPI_TXRAM19 0x0044348c /* Least significant byte of TXRAM[9] (queue pointer = 9) */
-#define BCHP_HIF_MSPI_TXRAM20 0x00443490 /* Most significant byte of TXRAM[10] (queue pointer = 10) */
-#define BCHP_HIF_MSPI_TXRAM21 0x00443494 /* Least significant byte of TXRAM[10] (queue pointer = 10) */
-#define BCHP_HIF_MSPI_TXRAM22 0x00443498 /* Most significant byte of TXRAM[11] (queue pointer = 11) */
-#define BCHP_HIF_MSPI_TXRAM23 0x0044349c /* Least significant byte of TXRAM[11] (queue pointer = 11) */
-#define BCHP_HIF_MSPI_TXRAM24 0x004434a0 /* Most significant byte of TXRAM[12] (queue pointer = 12) */
-#define BCHP_HIF_MSPI_TXRAM25 0x004434a4 /* Least significant byte of TXRAM[12] (queue pointer = 12) */
-#define BCHP_HIF_MSPI_TXRAM26 0x004434a8 /* Most significant byte of TXRAM[13] (queue pointer = 13) */
-#define BCHP_HIF_MSPI_TXRAM27 0x004434ac /* Least significant byte of TXRAM[13] (queue pointer = 13) */
-#define BCHP_HIF_MSPI_TXRAM28 0x004434b0 /* Most significant byte of TXRAM[14] (queue pointer = 14) */
-#define BCHP_HIF_MSPI_TXRAM29 0x004434b4 /* Least significant byte of TXRAM[14] (queue pointer = 14) */
-#define BCHP_HIF_MSPI_TXRAM30 0x004434b8 /* Most significant byte of TXRAM[15] (queue pointer = 15) */
-#define BCHP_HIF_MSPI_TXRAM31 0x004434bc /* Least significant byte of TXRAM[15] (queue pointer = 15) */
-#define BCHP_HIF_MSPI_RXRAM00 0x004434c0 /* Most significant byte of RXRAM[0] (queue pointer = 0) */
-#define BCHP_HIF_MSPI_RXRAM01 0x004434c4 /* Least significant byte of RXRAM[0] (queue pointer = 0) */
-#define BCHP_HIF_MSPI_RXRAM02 0x004434c8 /* Most significant byte of RXRAM[1] (queue pointer = 1) */
-#define BCHP_HIF_MSPI_RXRAM03 0x004434cc /* Least significant byte of RXRAM[1] (queue pointer = 1) */
-#define BCHP_HIF_MSPI_RXRAM04 0x004434d0 /* Most significant byte of RXRAM[2] (queue pointer = 2) */
-#define BCHP_HIF_MSPI_RXRAM05 0x004434d4 /* Least significant byte of RXRAM[2] (queue pointer = 2) */
-#define BCHP_HIF_MSPI_RXRAM06 0x004434d8 /* Most significant byte of RXRAM[3] (queue pointer = 3) */
-#define BCHP_HIF_MSPI_RXRAM07 0x004434dc /* Least significant byte of RXRAM[3] (queue pointer = 3) */
-#define BCHP_HIF_MSPI_RXRAM08 0x004434e0 /* Most significant byte of RXRAM[4] (queue pointer = 4) */
-#define BCHP_HIF_MSPI_RXRAM09 0x004434e4 /* Least significant byte of RXRAM[4] (queue pointer = 4) */
-#define BCHP_HIF_MSPI_RXRAM10 0x004434e8 /* Most significant byte of RXRAM[5] (queue pointer = 5) */
-#define BCHP_HIF_MSPI_RXRAM11 0x004434ec /* Least significant byte of RXRAM[5] (queue pointer = 5) */
-#define BCHP_HIF_MSPI_RXRAM12 0x004434f0 /* Most significant byte of RXRAM[6] (queue pointer = 6) */
-#define BCHP_HIF_MSPI_RXRAM13 0x004434f4 /* Least significant byte of RXRAM[6] (queue pointer = 6) */
-#define BCHP_HIF_MSPI_RXRAM14 0x004434f8 /* Most significant byte of RXRAM[7] (queue pointer = 7) */
-#define BCHP_HIF_MSPI_RXRAM15 0x004434fc /* Least significant byte of RXRAM[7] (queue pointer = 7) */
-#define BCHP_HIF_MSPI_RXRAM16 0x00443500 /* Most significant byte of RXRAM[8] (queue pointer = 8) */
-#define BCHP_HIF_MSPI_RXRAM17 0x00443504 /* Least significant byte of RXRAM[8] (queue pointer = 8) */
-#define BCHP_HIF_MSPI_RXRAM18 0x00443508 /* Most significant byte of RXRAM[9] (queue pointer = 9) */
-#define BCHP_HIF_MSPI_RXRAM19 0x0044350c /* Least significant byte of RXRAM[9] (queue pointer = 9) */
-#define BCHP_HIF_MSPI_RXRAM20 0x00443510 /* Most significant byte of RXRAM[10] (queue pointer = 10) */
-#define BCHP_HIF_MSPI_RXRAM21 0x00443514 /* Least significant byte of RXRAM[10] (queue pointer = 10) */
-#define BCHP_HIF_MSPI_RXRAM22 0x00443518 /* Most significant byte of RXRAM[11] (queue pointer = 11) */
-#define BCHP_HIF_MSPI_RXRAM23 0x0044351c /* Least significant byte of RXRAM[11] (queue pointer = 11) */
-#define BCHP_HIF_MSPI_RXRAM24 0x00443520 /* Most significant byte of RXRAM[12] (queue pointer = 12) */
-#define BCHP_HIF_MSPI_RXRAM25 0x00443524 /* Least significant byte of RXRAM[12] (queue pointer = 12) */
-#define BCHP_HIF_MSPI_RXRAM26 0x00443528 /* Most significant byte of RXRAM[13] (queue pointer = 13) */
-#define BCHP_HIF_MSPI_RXRAM27 0x0044352c /* Least significant byte of RXRAM[13] (queue pointer = 13) */
-#define BCHP_HIF_MSPI_RXRAM28 0x00443530 /* Most significant byte of RXRAM[14] (queue pointer = 14) */
-#define BCHP_HIF_MSPI_RXRAM29 0x00443534 /* Least significant byte of RXRAM[14] (queue pointer = 14) */
-#define BCHP_HIF_MSPI_RXRAM30 0x00443538 /* Most significant byte of RXRAM[15] (queue pointer = 15) */
-#define BCHP_HIF_MSPI_RXRAM31 0x0044353c /* Least significant byte of RXRAM[15] (queue pointer = 15) */
-#define BCHP_HIF_MSPI_CDRAM00 0x00443540 /* 8-bit command (queue pointer = 0) */
-#define BCHP_HIF_MSPI_CDRAM01 0x00443544 /* 8-bit command (queue pointer = 1) */
-#define BCHP_HIF_MSPI_CDRAM02 0x00443548 /* 8-bit command (queue pointer = 2) */
-#define BCHP_HIF_MSPI_CDRAM03 0x0044354c /* 8-bit command (queue pointer = 3) */
-#define BCHP_HIF_MSPI_CDRAM04 0x00443550 /* 8-bit command (queue pointer = 4) */
-#define BCHP_HIF_MSPI_CDRAM05 0x00443554 /* 8-bit command (queue pointer = 5) */
-#define BCHP_HIF_MSPI_CDRAM06 0x00443558 /* 8-bit command (queue pointer = 6) */
-#define BCHP_HIF_MSPI_CDRAM07 0x0044355c /* 8-bit command (queue pointer = 7) */
-#define BCHP_HIF_MSPI_CDRAM08 0x00443560 /* 8-bit command (queue pointer = 8) */
-#define BCHP_HIF_MSPI_CDRAM09 0x00443564 /* 8-bit command (queue pointer = 9) */
-#define BCHP_HIF_MSPI_CDRAM10 0x00443568 /* 8-bit command (queue pointer = a) */
-#define BCHP_HIF_MSPI_CDRAM11 0x0044356c /* 8-bit command (queue pointer = b) */
-#define BCHP_HIF_MSPI_CDRAM12 0x00443570 /* 8-bit command (queue pointer = c) */
-#define BCHP_HIF_MSPI_CDRAM13 0x00443574 /* 8-bit command (queue pointer = d) */
-#define BCHP_HIF_MSPI_CDRAM14 0x00443578 /* 8-bit command (queue pointer = e) */
-#define BCHP_HIF_MSPI_CDRAM15 0x0044357c /* 8-bit command (queue pointer = f) */
-#define BCHP_HIF_MSPI_WRITE_LOCK 0x00443580 /* Control bit to lock group of write commands */
-#define BCHP_HIF_MSPI_DISABLE_FLUSH_GEN 0x00443584 /* Debug bit to mask the generation of flush signals from Mspi */
-
-/***************************************************************************
- *SPCR0_LSB - SPCR0_LSB REGISTER
- ***************************************************************************/
-/* HIF_MSPI :: SPCR0_LSB :: reserved0 [31:08] */
-#define BCHP_HIF_MSPI_SPCR0_LSB_reserved0_MASK 0xffffff00
-#define BCHP_HIF_MSPI_SPCR0_LSB_reserved0_SHIFT 8
-
-/* HIF_MSPI :: SPCR0_LSB :: SPBR [07:00] */
-#define BCHP_HIF_MSPI_SPCR0_LSB_SPBR_MASK 0x000000ff
-#define BCHP_HIF_MSPI_SPCR0_LSB_SPBR_SHIFT 0
-#define BCHP_HIF_MSPI_SPCR0_LSB_SPBR_DEFAULT 0x00000000
-
-/***************************************************************************
- *SPCR0_MSB - SPCR0_MSB Register
- ***************************************************************************/
-/* HIF_MSPI :: SPCR0_MSB :: reserved0 [31:09] */
-#define BCHP_HIF_MSPI_SPCR0_MSB_reserved0_MASK 0xfffffe00
-#define BCHP_HIF_MSPI_SPCR0_MSB_reserved0_SHIFT 9
-
-/* HIF_MSPI :: SPCR0_MSB :: StartTransDelay [08:08] */
-#define BCHP_HIF_MSPI_SPCR0_MSB_StartTransDelay_MASK 0x00000100
-#define BCHP_HIF_MSPI_SPCR0_MSB_StartTransDelay_SHIFT 8
-#define BCHP_HIF_MSPI_SPCR0_MSB_StartTransDelay_DEFAULT 0x00000000
-
-/* union - case data_reg_8 [07:02] */
-/* HIF_MSPI :: SPCR0_MSB :: data_reg_8 :: reserved0 [07:06] */
-#define BCHP_HIF_MSPI_SPCR0_MSB_data_reg_8_reserved0_MASK 0x000000c0
-#define BCHP_HIF_MSPI_SPCR0_MSB_data_reg_8_reserved0_SHIFT 6
-
-/* HIF_MSPI :: SPCR0_MSB :: data_reg_8 :: BITS [05:02] */
-#define BCHP_HIF_MSPI_SPCR0_MSB_data_reg_8_BITS_MASK 0x0000003c
-#define BCHP_HIF_MSPI_SPCR0_MSB_data_reg_8_BITS_SHIFT 2
-#define BCHP_HIF_MSPI_SPCR0_MSB_data_reg_8_BITS_DEFAULT 0x00000000
-
-/* union - case data_reg_32 [07:02] */
-/* HIF_MSPI :: SPCR0_MSB :: data_reg_32 :: BITS [07:02] */
-#define BCHP_HIF_MSPI_SPCR0_MSB_data_reg_32_BITS_MASK 0x000000fc
-#define BCHP_HIF_MSPI_SPCR0_MSB_data_reg_32_BITS_SHIFT 2
-#define BCHP_HIF_MSPI_SPCR0_MSB_data_reg_32_BITS_DEFAULT 0x00000000
-
-/* HIF_MSPI :: SPCR0_MSB :: CPOL [01:01] */
-#define BCHP_HIF_MSPI_SPCR0_MSB_CPOL_MASK 0x00000002
-#define BCHP_HIF_MSPI_SPCR0_MSB_CPOL_SHIFT 1
-#define BCHP_HIF_MSPI_SPCR0_MSB_CPOL_DEFAULT 0x00000000
-
-/* HIF_MSPI :: SPCR0_MSB :: CPHA [00:00] */
-#define BCHP_HIF_MSPI_SPCR0_MSB_CPHA_MASK 0x00000001
-#define BCHP_HIF_MSPI_SPCR0_MSB_CPHA_SHIFT 0
-#define BCHP_HIF_MSPI_SPCR0_MSB_CPHA_DEFAULT 0x00000000
-
-/***************************************************************************
- *SPCR1_LSB - SPCR1_LSB REGISTER
- ***************************************************************************/
-/* HIF_MSPI :: SPCR1_LSB :: reserved0 [31:08] */
-#define BCHP_HIF_MSPI_SPCR1_LSB_reserved0_MASK 0xffffff00
-#define BCHP_HIF_MSPI_SPCR1_LSB_reserved0_SHIFT 8
-
-/* HIF_MSPI :: SPCR1_LSB :: DTL [07:00] */
-#define BCHP_HIF_MSPI_SPCR1_LSB_DTL_MASK 0x000000ff
-#define BCHP_HIF_MSPI_SPCR1_LSB_DTL_SHIFT 0
-#define BCHP_HIF_MSPI_SPCR1_LSB_DTL_DEFAULT 0x00000000
-
-/***************************************************************************
- *SPCR1_MSB - SPCR1_MSB REGISTER
- ***************************************************************************/
-/* HIF_MSPI :: SPCR1_MSB :: reserved0 [31:08] */
-#define BCHP_HIF_MSPI_SPCR1_MSB_reserved0_MASK 0xffffff00
-#define BCHP_HIF_MSPI_SPCR1_MSB_reserved0_SHIFT 8
-
-/* HIF_MSPI :: SPCR1_MSB :: RDSCLK [07:00] */
-#define BCHP_HIF_MSPI_SPCR1_MSB_RDSCLK_MASK 0x000000ff
-#define BCHP_HIF_MSPI_SPCR1_MSB_RDSCLK_SHIFT 0
-#define BCHP_HIF_MSPI_SPCR1_MSB_RDSCLK_DEFAULT 0x00000000
-
-/***************************************************************************
- *NEWQP - NEWQP REGISTER
- ***************************************************************************/
-/* HIF_MSPI :: NEWQP :: reserved0 [31:04] */
-#define BCHP_HIF_MSPI_NEWQP_reserved0_MASK 0xfffffff0
-#define BCHP_HIF_MSPI_NEWQP_reserved0_SHIFT 4
-
-/* HIF_MSPI :: NEWQP :: newqp [03:00] */
-#define BCHP_HIF_MSPI_NEWQP_newqp_MASK 0x0000000f
-#define BCHP_HIF_MSPI_NEWQP_newqp_SHIFT 0
-#define BCHP_HIF_MSPI_NEWQP_newqp_DEFAULT 0x00000000
-
-/***************************************************************************
- *ENDQP - ENDQP REGISTER
- ***************************************************************************/
-/* HIF_MSPI :: ENDQP :: reserved0 [31:04] */
-#define BCHP_HIF_MSPI_ENDQP_reserved0_MASK 0xfffffff0
-#define BCHP_HIF_MSPI_ENDQP_reserved0_SHIFT 4
-
-/* HIF_MSPI :: ENDQP :: endqp [03:00] */
-#define BCHP_HIF_MSPI_ENDQP_endqp_MASK 0x0000000f
-#define BCHP_HIF_MSPI_ENDQP_endqp_SHIFT 0
-#define BCHP_HIF_MSPI_ENDQP_endqp_DEFAULT 0x00000000
-
-/***************************************************************************
- *SPCR2 - SPCR2 REGISTER
- ***************************************************************************/
-/* HIF_MSPI :: SPCR2 :: reserved0 [31:08] */
-#define BCHP_HIF_MSPI_SPCR2_reserved0_MASK 0xffffff00
-#define BCHP_HIF_MSPI_SPCR2_reserved0_SHIFT 8
-
-/* HIF_MSPI :: SPCR2 :: cont_after_cmd [07:07] */
-#define BCHP_HIF_MSPI_SPCR2_cont_after_cmd_MASK 0x00000080
-#define BCHP_HIF_MSPI_SPCR2_cont_after_cmd_SHIFT 7
-#define BCHP_HIF_MSPI_SPCR2_cont_after_cmd_DEFAULT 0x00000000
-
-/* HIF_MSPI :: SPCR2 :: spe [06:06] */
-#define BCHP_HIF_MSPI_SPCR2_spe_MASK 0x00000040
-#define BCHP_HIF_MSPI_SPCR2_spe_SHIFT 6
-#define BCHP_HIF_MSPI_SPCR2_spe_DEFAULT 0x00000000
-
-/* HIF_MSPI :: SPCR2 :: spifie [05:05] */
-#define BCHP_HIF_MSPI_SPCR2_spifie_MASK 0x00000020
-#define BCHP_HIF_MSPI_SPCR2_spifie_SHIFT 5
-#define BCHP_HIF_MSPI_SPCR2_spifie_DEFAULT 0x00000000
-
-/* HIF_MSPI :: SPCR2 :: wren [04:04] */
-#define BCHP_HIF_MSPI_SPCR2_wren_MASK 0x00000010
-#define BCHP_HIF_MSPI_SPCR2_wren_SHIFT 4
-#define BCHP_HIF_MSPI_SPCR2_wren_DEFAULT 0x00000000
-
-/* HIF_MSPI :: SPCR2 :: wrt0 [03:03] */
-#define BCHP_HIF_MSPI_SPCR2_wrt0_MASK 0x00000008
-#define BCHP_HIF_MSPI_SPCR2_wrt0_SHIFT 3
-#define BCHP_HIF_MSPI_SPCR2_wrt0_DEFAULT 0x00000000
-
-/* HIF_MSPI :: SPCR2 :: loopq [02:02] */
-#define BCHP_HIF_MSPI_SPCR2_loopq_MASK 0x00000004
-#define BCHP_HIF_MSPI_SPCR2_loopq_SHIFT 2
-#define BCHP_HIF_MSPI_SPCR2_loopq_DEFAULT 0x00000000
-
-/* HIF_MSPI :: SPCR2 :: hie [01:01] */
-#define BCHP_HIF_MSPI_SPCR2_hie_MASK 0x00000002
-#define BCHP_HIF_MSPI_SPCR2_hie_SHIFT 1
-#define BCHP_HIF_MSPI_SPCR2_hie_DEFAULT 0x00000000
-
-/* HIF_MSPI :: SPCR2 :: halt [00:00] */
-#define BCHP_HIF_MSPI_SPCR2_halt_MASK 0x00000001
-#define BCHP_HIF_MSPI_SPCR2_halt_SHIFT 0
-#define BCHP_HIF_MSPI_SPCR2_halt_DEFAULT 0x00000000
-
-/***************************************************************************
- *MSPI_STATUS - MSPI STATUS REGISTER
- ***************************************************************************/
-/* HIF_MSPI :: MSPI_STATUS :: reserved0 [31:02] */
-#define BCHP_HIF_MSPI_MSPI_STATUS_reserved0_MASK 0xfffffffc
-#define BCHP_HIF_MSPI_MSPI_STATUS_reserved0_SHIFT 2
-
-/* HIF_MSPI :: MSPI_STATUS :: HALTA [01:01] */
-#define BCHP_HIF_MSPI_MSPI_STATUS_HALTA_MASK 0x00000002
-#define BCHP_HIF_MSPI_MSPI_STATUS_HALTA_SHIFT 1
-#define BCHP_HIF_MSPI_MSPI_STATUS_HALTA_DEFAULT 0x00000000
-
-/* HIF_MSPI :: MSPI_STATUS :: SPIF [00:00] */
-#define BCHP_HIF_MSPI_MSPI_STATUS_SPIF_MASK 0x00000001
-#define BCHP_HIF_MSPI_MSPI_STATUS_SPIF_SHIFT 0
-#define BCHP_HIF_MSPI_MSPI_STATUS_SPIF_DEFAULT 0x00000000
-
-/***************************************************************************
- *CPTQP - CPTQP REGISTER
- ***************************************************************************/
-/* HIF_MSPI :: CPTQP :: reserved0 [31:04] */
-#define BCHP_HIF_MSPI_CPTQP_reserved0_MASK 0xfffffff0
-#define BCHP_HIF_MSPI_CPTQP_reserved0_SHIFT 4
-
-/* HIF_MSPI :: CPTQP :: cptqp [03:00] */
-#define BCHP_HIF_MSPI_CPTQP_cptqp_MASK 0x0000000f
-#define BCHP_HIF_MSPI_CPTQP_cptqp_SHIFT 0
-#define BCHP_HIF_MSPI_CPTQP_cptqp_DEFAULT 0x00000000
-
-/***************************************************************************
- *SPCR3 - SPCR3 REGISTER
- ***************************************************************************/
-/* HIF_MSPI :: SPCR3 :: reserved0 [31:10] */
-#define BCHP_HIF_MSPI_SPCR3_reserved0_MASK 0xfffffc00
-#define BCHP_HIF_MSPI_SPCR3_reserved0_SHIFT 10
-
-/* HIF_MSPI :: SPCR3 :: cpharx [09:09] */
-#define BCHP_HIF_MSPI_SPCR3_cpharx_MASK 0x00000200
-#define BCHP_HIF_MSPI_SPCR3_cpharx_SHIFT 9
-#define BCHP_HIF_MSPI_SPCR3_cpharx_DEFAULT 0x00000000
-
-/* HIF_MSPI :: SPCR3 :: data_reg_size [08:08] */
-#define BCHP_HIF_MSPI_SPCR3_data_reg_size_MASK 0x00000100
-#define BCHP_HIF_MSPI_SPCR3_data_reg_size_SHIFT 8
-#define BCHP_HIF_MSPI_SPCR3_data_reg_size_DEFAULT 0x00000000
-
-/* HIF_MSPI :: SPCR3 :: hdouttype [07:07] */
-#define BCHP_HIF_MSPI_SPCR3_hdouttype_MASK 0x00000080
-#define BCHP_HIF_MSPI_SPCR3_hdouttype_SHIFT 7
-#define BCHP_HIF_MSPI_SPCR3_hdouttype_DEFAULT 0x00000000
-
-/* HIF_MSPI :: SPCR3 :: halfduplex [06:06] */
-#define BCHP_HIF_MSPI_SPCR3_halfduplex_MASK 0x00000040
-#define BCHP_HIF_MSPI_SPCR3_halfduplex_SHIFT 6
-#define BCHP_HIF_MSPI_SPCR3_halfduplex_DEFAULT 0x00000000
-
-/* HIF_MSPI :: SPCR3 :: txramdam [05:04] */
-#define BCHP_HIF_MSPI_SPCR3_txramdam_MASK 0x00000030
-#define BCHP_HIF_MSPI_SPCR3_txramdam_SHIFT 4
-#define BCHP_HIF_MSPI_SPCR3_txramdam_DEFAULT 0x00000000
-#define BCHP_HIF_MSPI_SPCR3_txramdam_DAM_8B 0
-#define BCHP_HIF_MSPI_SPCR3_txramdam_DAM_16B 1
-#define BCHP_HIF_MSPI_SPCR3_txramdam_DAM_32B 2
-
-/* HIF_MSPI :: SPCR3 :: rxramdam [03:02] */
-#define BCHP_HIF_MSPI_SPCR3_rxramdam_MASK 0x0000000c
-#define BCHP_HIF_MSPI_SPCR3_rxramdam_SHIFT 2
-#define BCHP_HIF_MSPI_SPCR3_rxramdam_DEFAULT 0x00000000
-#define BCHP_HIF_MSPI_SPCR3_rxramdam_DAM_8B 0
-#define BCHP_HIF_MSPI_SPCR3_rxramdam_DAM_16B 1
-#define BCHP_HIF_MSPI_SPCR3_rxramdam_DAM_32B 2
-
-/* HIF_MSPI :: SPCR3 :: fastdt [01:01] */
-#define BCHP_HIF_MSPI_SPCR3_fastdt_MASK 0x00000002
-#define BCHP_HIF_MSPI_SPCR3_fastdt_SHIFT 1
-#define BCHP_HIF_MSPI_SPCR3_fastdt_DEFAULT 0x00000000
-
-/* HIF_MSPI :: SPCR3 :: fastbr [00:00] */
-#define BCHP_HIF_MSPI_SPCR3_fastbr_MASK 0x00000001
-#define BCHP_HIF_MSPI_SPCR3_fastbr_SHIFT 0
-#define BCHP_HIF_MSPI_SPCR3_fastbr_DEFAULT 0x00000000
-
-/***************************************************************************
- *REVISION - REVISION ID REGISTER
- ***************************************************************************/
-/* HIF_MSPI :: REVISION :: reserved0 [31:08] */
-#define BCHP_HIF_MSPI_REVISION_reserved0_MASK 0xffffff00
-#define BCHP_HIF_MSPI_REVISION_reserved0_SHIFT 8
-
-/* HIF_MSPI :: REVISION :: major [07:04] */
-#define BCHP_HIF_MSPI_REVISION_major_MASK 0x000000f0
-#define BCHP_HIF_MSPI_REVISION_major_SHIFT 4
-#define BCHP_HIF_MSPI_REVISION_major_DEFAULT 0x00000001
-
-/* HIF_MSPI :: REVISION :: minor [03:00] */
-#define BCHP_HIF_MSPI_REVISION_minor_MASK 0x0000000f
-#define BCHP_HIF_MSPI_REVISION_minor_SHIFT 0
-#define BCHP_HIF_MSPI_REVISION_minor_DEFAULT 0x00000005
-
-/***************************************************************************
- *TXRAM00 - Most significant byte of TXRAM[0] (queue pointer = 0)
- ***************************************************************************/
-/* HIF_MSPI :: TXRAM00 :: reserved0 [31:08] */
-#define BCHP_HIF_MSPI_TXRAM00_reserved0_MASK 0xffffff00
-#define BCHP_HIF_MSPI_TXRAM00_reserved0_SHIFT 8
-
-/* HIF_MSPI :: TXRAM00 :: txram [07:00] */
-#define BCHP_HIF_MSPI_TXRAM00_txram_MASK 0x000000ff
-#define BCHP_HIF_MSPI_TXRAM00_txram_SHIFT 0
-
-/***************************************************************************
- *TXRAM01 - Least significant byte of TXRAM[0] (queue pointer = 0)
- ***************************************************************************/
-/* HIF_MSPI :: TXRAM01 :: reserved0 [31:08] */
-#define BCHP_HIF_MSPI_TXRAM01_reserved0_MASK 0xffffff00
-#define BCHP_HIF_MSPI_TXRAM01_reserved0_SHIFT 8
-
-/* HIF_MSPI :: TXRAM01 :: txram [07:00] */
-#define BCHP_HIF_MSPI_TXRAM01_txram_MASK 0x000000ff
-#define BCHP_HIF_MSPI_TXRAM01_txram_SHIFT 0
-
-/***************************************************************************
- *TXRAM02 - Most significant byte of TXRAM[1] (queue pointer = 1)
- ***************************************************************************/
-/* HIF_MSPI :: TXRAM02 :: reserved0 [31:08] */
-#define BCHP_HIF_MSPI_TXRAM02_reserved0_MASK 0xffffff00
-#define BCHP_HIF_MSPI_TXRAM02_reserved0_SHIFT 8
-
-/* HIF_MSPI :: TXRAM02 :: txram [07:00] */
-#define BCHP_HIF_MSPI_TXRAM02_txram_MASK 0x000000ff
-#define BCHP_HIF_MSPI_TXRAM02_txram_SHIFT 0
-
-/***************************************************************************
- *TXRAM03 - Least significant byte of TXRAM[1] (queue pointer = 1)
- ***************************************************************************/
-/* HIF_MSPI :: TXRAM03 :: reserved0 [31:08] */
-#define BCHP_HIF_MSPI_TXRAM03_reserved0_MASK 0xffffff00
-#define BCHP_HIF_MSPI_TXRAM03_reserved0_SHIFT 8
-
-/* HIF_MSPI :: TXRAM03 :: txram [07:00] */
-#define BCHP_HIF_MSPI_TXRAM03_txram_MASK 0x000000ff
-#define BCHP_HIF_MSPI_TXRAM03_txram_SHIFT 0
-
-/***************************************************************************
- *TXRAM04 - Most significant byte of TXRAM[2] (queue pointer = 2)
- ***************************************************************************/
-/* HIF_MSPI :: TXRAM04 :: reserved0 [31:08] */
-#define BCHP_HIF_MSPI_TXRAM04_reserved0_MASK 0xffffff00
-#define BCHP_HIF_MSPI_TXRAM04_reserved0_SHIFT 8
-
-/* HIF_MSPI :: TXRAM04 :: txram [07:00] */
-#define BCHP_HIF_MSPI_TXRAM04_txram_MASK 0x000000ff
-#define BCHP_HIF_MSPI_TXRAM04_txram_SHIFT 0
-
-/***************************************************************************
- *TXRAM05 - Least significant byte of TXRAM[2] (queue pointer = 2)
- ***************************************************************************/
-/* HIF_MSPI :: TXRAM05 :: reserved0 [31:08] */
-#define BCHP_HIF_MSPI_TXRAM05_reserved0_MASK 0xffffff00
-#define BCHP_HIF_MSPI_TXRAM05_reserved0_SHIFT 8
-
-/* HIF_MSPI :: TXRAM05 :: txram [07:00] */
-#define BCHP_HIF_MSPI_TXRAM05_txram_MASK 0x000000ff
-#define BCHP_HIF_MSPI_TXRAM05_txram_SHIFT 0
-
-/***************************************************************************
- *TXRAM06 - Most significant byte of TXRAM[3] (queue pointer = 3)
- ***************************************************************************/
-/* HIF_MSPI :: TXRAM06 :: reserved0 [31:08] */
-#define BCHP_HIF_MSPI_TXRAM06_reserved0_MASK 0xffffff00
-#define BCHP_HIF_MSPI_TXRAM06_reserved0_SHIFT 8
-
-/* HIF_MSPI :: TXRAM06 :: txram [07:00] */
-#define BCHP_HIF_MSPI_TXRAM06_txram_MASK 0x000000ff
-#define BCHP_HIF_MSPI_TXRAM06_txram_SHIFT 0
-
-/***************************************************************************
- *TXRAM07 - Least significant byte of TXRAM[3] (queue pointer = 3)
- ***************************************************************************/
-/* HIF_MSPI :: TXRAM07 :: reserved0 [31:08] */
-#define BCHP_HIF_MSPI_TXRAM07_reserved0_MASK 0xffffff00
-#define BCHP_HIF_MSPI_TXRAM07_reserved0_SHIFT 8
-
-/* HIF_MSPI :: TXRAM07 :: txram [07:00] */
-#define BCHP_HIF_MSPI_TXRAM07_txram_MASK 0x000000ff
-#define BCHP_HIF_MSPI_TXRAM07_txram_SHIFT 0
-
-/***************************************************************************
- *TXRAM08 - Most significant byte of TXRAM[4] (queue pointer = 4)
- ***************************************************************************/
-/* HIF_MSPI :: TXRAM08 :: reserved0 [31:08] */
-#define BCHP_HIF_MSPI_TXRAM08_reserved0_MASK 0xffffff00
-#define BCHP_HIF_MSPI_TXRAM08_reserved0_SHIFT 8
-
-/* HIF_MSPI :: TXRAM08 :: txram [07:00] */
-#define BCHP_HIF_MSPI_TXRAM08_txram_MASK 0x000000ff
-#define BCHP_HIF_MSPI_TXRAM08_txram_SHIFT 0
-
-/***************************************************************************
- *TXRAM09 - Least significant byte of TXRAM[4] (queue pointer = 4)
- ***************************************************************************/
-/* HIF_MSPI :: TXRAM09 :: reserved0 [31:08] */
-#define BCHP_HIF_MSPI_TXRAM09_reserved0_MASK 0xffffff00
-#define BCHP_HIF_MSPI_TXRAM09_reserved0_SHIFT 8
-
-/* HIF_MSPI :: TXRAM09 :: txram [07:00] */
-#define BCHP_HIF_MSPI_TXRAM09_txram_MASK 0x000000ff
-#define BCHP_HIF_MSPI_TXRAM09_txram_SHIFT 0
-
-/***************************************************************************
- *TXRAM10 - Most significant byte of TXRAM[5] (queue pointer = 5)
- ***************************************************************************/
-/* HIF_MSPI :: TXRAM10 :: reserved0 [31:08] */
-#define BCHP_HIF_MSPI_TXRAM10_reserved0_MASK 0xffffff00
-#define BCHP_HIF_MSPI_TXRAM10_reserved0_SHIFT 8
-
-/* HIF_MSPI :: TXRAM10 :: txram [07:00] */
-#define BCHP_HIF_MSPI_TXRAM10_txram_MASK 0x000000ff
-#define BCHP_HIF_MSPI_TXRAM10_txram_SHIFT 0
-
-/***************************************************************************
- *TXRAM11 - Least significant byte of TXRAM[5] (queue pointer = 5)
- ***************************************************************************/
-/* HIF_MSPI :: TXRAM11 :: reserved0 [31:08] */
-#define BCHP_HIF_MSPI_TXRAM11_reserved0_MASK 0xffffff00
-#define BCHP_HIF_MSPI_TXRAM11_reserved0_SHIFT 8
-
-/* HIF_MSPI :: TXRAM11 :: txram [07:00] */
-#define BCHP_HIF_MSPI_TXRAM11_txram_MASK 0x000000ff
-#define BCHP_HIF_MSPI_TXRAM11_txram_SHIFT 0
-
-/***************************************************************************
- *TXRAM12 - Most significant byte of TXRAM[6] (queue pointer = 6)
- ***************************************************************************/
-/* HIF_MSPI :: TXRAM12 :: reserved0 [31:08] */
-#define BCHP_HIF_MSPI_TXRAM12_reserved0_MASK 0xffffff00
-#define BCHP_HIF_MSPI_TXRAM12_reserved0_SHIFT 8
-
-/* HIF_MSPI :: TXRAM12 :: txram [07:00] */
-#define BCHP_HIF_MSPI_TXRAM12_txram_MASK 0x000000ff
-#define BCHP_HIF_MSPI_TXRAM12_txram_SHIFT 0
-
-/***************************************************************************
- *TXRAM13 - Least significant byte of TXRAM[6] (queue pointer = 6)
- ***************************************************************************/
-/* HIF_MSPI :: TXRAM13 :: reserved0 [31:08] */
-#define BCHP_HIF_MSPI_TXRAM13_reserved0_MASK 0xffffff00
-#define BCHP_HIF_MSPI_TXRAM13_reserved0_SHIFT 8
-
-/* HIF_MSPI :: TXRAM13 :: txram [07:00] */
-#define BCHP_HIF_MSPI_TXRAM13_txram_MASK 0x000000ff
-#define BCHP_HIF_MSPI_TXRAM13_txram_SHIFT 0
-
-/***************************************************************************
- *TXRAM14 - Most significant byte of TXRAM[7] (queue pointer = 7)
- ***************************************************************************/
-/* HIF_MSPI :: TXRAM14 :: reserved0 [31:08] */
-#define BCHP_HIF_MSPI_TXRAM14_reserved0_MASK 0xffffff00
-#define BCHP_HIF_MSPI_TXRAM14_reserved0_SHIFT 8
-
-/* HIF_MSPI :: TXRAM14 :: txram [07:00] */
-#define BCHP_HIF_MSPI_TXRAM14_txram_MASK 0x000000ff
-#define BCHP_HIF_MSPI_TXRAM14_txram_SHIFT 0
-
-/***************************************************************************
- *TXRAM15 - Least significant byte of TXRAM[7] (queue pointer = 7)
- ***************************************************************************/
-/* HIF_MSPI :: TXRAM15 :: reserved0 [31:08] */
-#define BCHP_HIF_MSPI_TXRAM15_reserved0_MASK 0xffffff00
-#define BCHP_HIF_MSPI_TXRAM15_reserved0_SHIFT 8
-
-/* HIF_MSPI :: TXRAM15 :: txram [07:00] */
-#define BCHP_HIF_MSPI_TXRAM15_txram_MASK 0x000000ff
-#define BCHP_HIF_MSPI_TXRAM15_txram_SHIFT 0
-
-/***************************************************************************
- *TXRAM16 - Most significant byte of TXRAM[8] (queue pointer = 8)
- ***************************************************************************/
-/* HIF_MSPI :: TXRAM16 :: reserved0 [31:08] */
-#define BCHP_HIF_MSPI_TXRAM16_reserved0_MASK 0xffffff00
-#define BCHP_HIF_MSPI_TXRAM16_reserved0_SHIFT 8
-
-/* HIF_MSPI :: TXRAM16 :: txram [07:00] */
-#define BCHP_HIF_MSPI_TXRAM16_txram_MASK 0x000000ff
-#define BCHP_HIF_MSPI_TXRAM16_txram_SHIFT 0
-
-/***************************************************************************
- *TXRAM17 - Least significant byte of TXRAM[8] (queue pointer = 8)
- ***************************************************************************/
-/* HIF_MSPI :: TXRAM17 :: reserved0 [31:08] */
-#define BCHP_HIF_MSPI_TXRAM17_reserved0_MASK 0xffffff00
-#define BCHP_HIF_MSPI_TXRAM17_reserved0_SHIFT 8
-
-/* HIF_MSPI :: TXRAM17 :: txram [07:00] */
-#define BCHP_HIF_MSPI_TXRAM17_txram_MASK 0x000000ff
-#define BCHP_HIF_MSPI_TXRAM17_txram_SHIFT 0
-
-/***************************************************************************
- *TXRAM18 - Most significant byte of TXRAM[9] (queue pointer = 9)
- ***************************************************************************/
-/* HIF_MSPI :: TXRAM18 :: reserved0 [31:08] */
-#define BCHP_HIF_MSPI_TXRAM18_reserved0_MASK 0xffffff00
-#define BCHP_HIF_MSPI_TXRAM18_reserved0_SHIFT 8
-
-/* HIF_MSPI :: TXRAM18 :: txram [07:00] */
-#define BCHP_HIF_MSPI_TXRAM18_txram_MASK 0x000000ff
-#define BCHP_HIF_MSPI_TXRAM18_txram_SHIFT 0
-
-/***************************************************************************
- *TXRAM19 - Least significant byte of TXRAM[9] (queue pointer = 9)
- ***************************************************************************/
-/* HIF_MSPI :: TXRAM19 :: reserved0 [31:08] */
-#define BCHP_HIF_MSPI_TXRAM19_reserved0_MASK 0xffffff00
-#define BCHP_HIF_MSPI_TXRAM19_reserved0_SHIFT 8
-
-/* HIF_MSPI :: TXRAM19 :: txram [07:00] */
-#define BCHP_HIF_MSPI_TXRAM19_txram_MASK 0x000000ff
-#define BCHP_HIF_MSPI_TXRAM19_txram_SHIFT 0
-
-/***************************************************************************
- *TXRAM20 - Most significant byte of TXRAM[10] (queue pointer = 10)
- ***************************************************************************/
-/* HIF_MSPI :: TXRAM20 :: reserved0 [31:08] */
-#define BCHP_HIF_MSPI_TXRAM20_reserved0_MASK 0xffffff00
-#define BCHP_HIF_MSPI_TXRAM20_reserved0_SHIFT 8
-
-/* HIF_MSPI :: TXRAM20 :: txram [07:00] */
-#define BCHP_HIF_MSPI_TXRAM20_txram_MASK 0x000000ff
-#define BCHP_HIF_MSPI_TXRAM20_txram_SHIFT 0
-
-/***************************************************************************
- *TXRAM21 - Least significant byte of TXRAM[10] (queue pointer = 10)
- ***************************************************************************/
-/* HIF_MSPI :: TXRAM21 :: reserved0 [31:08] */
-#define BCHP_HIF_MSPI_TXRAM21_reserved0_MASK 0xffffff00
-#define BCHP_HIF_MSPI_TXRAM21_reserved0_SHIFT 8
-
-/* HIF_MSPI :: TXRAM21 :: txram [07:00] */
-#define BCHP_HIF_MSPI_TXRAM21_txram_MASK 0x000000ff
-#define BCHP_HIF_MSPI_TXRAM21_txram_SHIFT 0
-
-/***************************************************************************
- *TXRAM22 - Most significant byte of TXRAM[11] (queue pointer = 11)
- ***************************************************************************/
-/* HIF_MSPI :: TXRAM22 :: reserved0 [31:08] */
-#define BCHP_HIF_MSPI_TXRAM22_reserved0_MASK 0xffffff00
-#define BCHP_HIF_MSPI_TXRAM22_reserved0_SHIFT 8
-
-/* HIF_MSPI :: TXRAM22 :: txram [07:00] */
-#define BCHP_HIF_MSPI_TXRAM22_txram_MASK 0x000000ff
-#define BCHP_HIF_MSPI_TXRAM22_txram_SHIFT 0
-
-/***************************************************************************
- *TXRAM23 - Least significant byte of TXRAM[11] (queue pointer = 11)
- ***************************************************************************/
-/* HIF_MSPI :: TXRAM23 :: reserved0 [31:08] */
-#define BCHP_HIF_MSPI_TXRAM23_reserved0_MASK 0xffffff00
-#define BCHP_HIF_MSPI_TXRAM23_reserved0_SHIFT 8
-
-/* HIF_MSPI :: TXRAM23 :: txram [07:00] */
-#define BCHP_HIF_MSPI_TXRAM23_txram_MASK 0x000000ff
-#define BCHP_HIF_MSPI_TXRAM23_txram_SHIFT 0
-
-/***************************************************************************
- *TXRAM24 - Most significant byte of TXRAM[12] (queue pointer = 12)
- ***************************************************************************/
-/* HIF_MSPI :: TXRAM24 :: reserved0 [31:08] */
-#define BCHP_HIF_MSPI_TXRAM24_reserved0_MASK 0xffffff00
-#define BCHP_HIF_MSPI_TXRAM24_reserved0_SHIFT 8
-
-/* HIF_MSPI :: TXRAM24 :: txram [07:00] */
-#define BCHP_HIF_MSPI_TXRAM24_txram_MASK 0x000000ff
-#define BCHP_HIF_MSPI_TXRAM24_txram_SHIFT 0
-
-/***************************************************************************
- *TXRAM25 - Least significant byte of TXRAM[12] (queue pointer = 12)
- ***************************************************************************/
-/* HIF_MSPI :: TXRAM25 :: reserved0 [31:08] */
-#define BCHP_HIF_MSPI_TXRAM25_reserved0_MASK 0xffffff00
-#define BCHP_HIF_MSPI_TXRAM25_reserved0_SHIFT 8
-
-/* HIF_MSPI :: TXRAM25 :: txram [07:00] */
-#define BCHP_HIF_MSPI_TXRAM25_txram_MASK 0x000000ff
-#define BCHP_HIF_MSPI_TXRAM25_txram_SHIFT 0
-
-/***************************************************************************
- *TXRAM26 - Most significant byte of TXRAM[13] (queue pointer = 13)
- ***************************************************************************/
-/* HIF_MSPI :: TXRAM26 :: reserved0 [31:08] */
-#define BCHP_HIF_MSPI_TXRAM26_reserved0_MASK 0xffffff00
-#define BCHP_HIF_MSPI_TXRAM26_reserved0_SHIFT 8
-
-/* HIF_MSPI :: TXRAM26 :: txram [07:00] */
-#define BCHP_HIF_MSPI_TXRAM26_txram_MASK 0x000000ff
-#define BCHP_HIF_MSPI_TXRAM26_txram_SHIFT 0
-
-/***************************************************************************
- *TXRAM27 - Least significant byte of TXRAM[13] (queue pointer = 13)
- ***************************************************************************/
-/* HIF_MSPI :: TXRAM27 :: reserved0 [31:08] */
-#define BCHP_HIF_MSPI_TXRAM27_reserved0_MASK 0xffffff00
-#define BCHP_HIF_MSPI_TXRAM27_reserved0_SHIFT 8
-
-/* HIF_MSPI :: TXRAM27 :: txram [07:00] */
-#define BCHP_HIF_MSPI_TXRAM27_txram_MASK 0x000000ff
-#define BCHP_HIF_MSPI_TXRAM27_txram_SHIFT 0
-
-/***************************************************************************
- *TXRAM28 - Most significant byte of TXRAM[14] (queue pointer = 14)
- ***************************************************************************/
-/* HIF_MSPI :: TXRAM28 :: reserved0 [31:08] */
-#define BCHP_HIF_MSPI_TXRAM28_reserved0_MASK 0xffffff00
-#define BCHP_HIF_MSPI_TXRAM28_reserved0_SHIFT 8
-
-/* HIF_MSPI :: TXRAM28 :: txram [07:00] */
-#define BCHP_HIF_MSPI_TXRAM28_txram_MASK 0x000000ff
-#define BCHP_HIF_MSPI_TXRAM28_txram_SHIFT 0
-
-/***************************************************************************
- *TXRAM29 - Least significant byte of TXRAM[14] (queue pointer = 14)
- ***************************************************************************/
-/* HIF_MSPI :: TXRAM29 :: reserved0 [31:08] */
-#define BCHP_HIF_MSPI_TXRAM29_reserved0_MASK 0xffffff00
-#define BCHP_HIF_MSPI_TXRAM29_reserved0_SHIFT 8
-
-/* HIF_MSPI :: TXRAM29 :: txram [07:00] */
-#define BCHP_HIF_MSPI_TXRAM29_txram_MASK 0x000000ff
-#define BCHP_HIF_MSPI_TXRAM29_txram_SHIFT 0
-
-/***************************************************************************
- *TXRAM30 - Most significant byte of TXRAM[15] (queue pointer = 15)
- ***************************************************************************/
-/* HIF_MSPI :: TXRAM30 :: reserved0 [31:08] */
-#define BCHP_HIF_MSPI_TXRAM30_reserved0_MASK 0xffffff00
-#define BCHP_HIF_MSPI_TXRAM30_reserved0_SHIFT 8
-
-/* HIF_MSPI :: TXRAM30 :: txram [07:00] */
-#define BCHP_HIF_MSPI_TXRAM30_txram_MASK 0x000000ff
-#define BCHP_HIF_MSPI_TXRAM30_txram_SHIFT 0
-
-/***************************************************************************
- *TXRAM31 - Least significant byte of TXRAM[15] (queue pointer = 15)
- ***************************************************************************/
-/* HIF_MSPI :: TXRAM31 :: reserved0 [31:08] */
-#define BCHP_HIF_MSPI_TXRAM31_reserved0_MASK 0xffffff00
-#define BCHP_HIF_MSPI_TXRAM31_reserved0_SHIFT 8
-
-/* HIF_MSPI :: TXRAM31 :: txram [07:00] */
-#define BCHP_HIF_MSPI_TXRAM31_txram_MASK 0x000000ff
-#define BCHP_HIF_MSPI_TXRAM31_txram_SHIFT 0
-
-/***************************************************************************
- *RXRAM00 - Most significant byte of RXRAM[0] (queue pointer = 0)
- ***************************************************************************/
-/* HIF_MSPI :: RXRAM00 :: reserved0 [31:08] */
-#define BCHP_HIF_MSPI_RXRAM00_reserved0_MASK 0xffffff00
-#define BCHP_HIF_MSPI_RXRAM00_reserved0_SHIFT 8
-
-/* HIF_MSPI :: RXRAM00 :: rxram [07:00] */
-#define BCHP_HIF_MSPI_RXRAM00_rxram_MASK 0x000000ff
-#define BCHP_HIF_MSPI_RXRAM00_rxram_SHIFT 0
-
-/***************************************************************************
- *RXRAM01 - Least significant byte of RXRAM[0] (queue pointer = 0)
- ***************************************************************************/
-/* HIF_MSPI :: RXRAM01 :: reserved0 [31:08] */
-#define BCHP_HIF_MSPI_RXRAM01_reserved0_MASK 0xffffff00
-#define BCHP_HIF_MSPI_RXRAM01_reserved0_SHIFT 8
-
-/* HIF_MSPI :: RXRAM01 :: rxram [07:00] */
-#define BCHP_HIF_MSPI_RXRAM01_rxram_MASK 0x000000ff
-#define BCHP_HIF_MSPI_RXRAM01_rxram_SHIFT 0
-
-/***************************************************************************
- *RXRAM02 - Most significant byte of RXRAM[1] (queue pointer = 1)
- ***************************************************************************/
-/* HIF_MSPI :: RXRAM02 :: reserved0 [31:08] */
-#define BCHP_HIF_MSPI_RXRAM02_reserved0_MASK 0xffffff00
-#define BCHP_HIF_MSPI_RXRAM02_reserved0_SHIFT 8
-
-/* HIF_MSPI :: RXRAM02 :: rxram [07:00] */
-#define BCHP_HIF_MSPI_RXRAM02_rxram_MASK 0x000000ff
-#define BCHP_HIF_MSPI_RXRAM02_rxram_SHIFT 0
-
-/***************************************************************************
- *RXRAM03 - Least significant byte of RXRAM[1] (queue pointer = 1)
- ***************************************************************************/
-/* HIF_MSPI :: RXRAM03 :: reserved0 [31:08] */
-#define BCHP_HIF_MSPI_RXRAM03_reserved0_MASK 0xffffff00
-#define BCHP_HIF_MSPI_RXRAM03_reserved0_SHIFT 8
-
-/* HIF_MSPI :: RXRAM03 :: rxram [07:00] */
-#define BCHP_HIF_MSPI_RXRAM03_rxram_MASK 0x000000ff
-#define BCHP_HIF_MSPI_RXRAM03_rxram_SHIFT 0
-
-/***************************************************************************
- *RXRAM04 - Most significant byte of RXRAM[2] (queue pointer = 2)
- ***************************************************************************/
-/* HIF_MSPI :: RXRAM04 :: reserved0 [31:08] */
-#define BCHP_HIF_MSPI_RXRAM04_reserved0_MASK 0xffffff00
-#define BCHP_HIF_MSPI_RXRAM04_reserved0_SHIFT 8
-
-/* HIF_MSPI :: RXRAM04 :: rxram [07:00] */
-#define BCHP_HIF_MSPI_RXRAM04_rxram_MASK 0x000000ff
-#define BCHP_HIF_MSPI_RXRAM04_rxram_SHIFT 0
-
-/***************************************************************************
- *RXRAM05 - Least significant byte of RXRAM[2] (queue pointer = 2)
- ***************************************************************************/
-/* HIF_MSPI :: RXRAM05 :: reserved0 [31:08] */
-#define BCHP_HIF_MSPI_RXRAM05_reserved0_MASK 0xffffff00
-#define BCHP_HIF_MSPI_RXRAM05_reserved0_SHIFT 8
-
-/* HIF_MSPI :: RXRAM05 :: rxram [07:00] */
-#define BCHP_HIF_MSPI_RXRAM05_rxram_MASK 0x000000ff
-#define BCHP_HIF_MSPI_RXRAM05_rxram_SHIFT 0
-
-/***************************************************************************
- *RXRAM06 - Most significant byte of RXRAM[3] (queue pointer = 3)
- ***************************************************************************/
-/* HIF_MSPI :: RXRAM06 :: reserved0 [31:08] */
-#define BCHP_HIF_MSPI_RXRAM06_reserved0_MASK 0xffffff00
-#define BCHP_HIF_MSPI_RXRAM06_reserved0_SHIFT 8
-
-/* HIF_MSPI :: RXRAM06 :: rxram [07:00] */
-#define BCHP_HIF_MSPI_RXRAM06_rxram_MASK 0x000000ff
-#define BCHP_HIF_MSPI_RXRAM06_rxram_SHIFT 0
-
-/***************************************************************************
- *RXRAM07 - Least significant byte of RXRAM[3] (queue pointer = 3)
- ***************************************************************************/
-/* HIF_MSPI :: RXRAM07 :: reserved0 [31:08] */
-#define BCHP_HIF_MSPI_RXRAM07_reserved0_MASK 0xffffff00
-#define BCHP_HIF_MSPI_RXRAM07_reserved0_SHIFT 8
-
-/* HIF_MSPI :: RXRAM07 :: rxram [07:00] */
-#define BCHP_HIF_MSPI_RXRAM07_rxram_MASK 0x000000ff
-#define BCHP_HIF_MSPI_RXRAM07_rxram_SHIFT 0
-
-/***************************************************************************
- *RXRAM08 - Most significant byte of RXRAM[4] (queue pointer = 4)
- ***************************************************************************/
-/* HIF_MSPI :: RXRAM08 :: reserved0 [31:08] */
-#define BCHP_HIF_MSPI_RXRAM08_reserved0_MASK 0xffffff00
-#define BCHP_HIF_MSPI_RXRAM08_reserved0_SHIFT 8
-
-/* HIF_MSPI :: RXRAM08 :: rxram [07:00] */
-#define BCHP_HIF_MSPI_RXRAM08_rxram_MASK 0x000000ff
-#define BCHP_HIF_MSPI_RXRAM08_rxram_SHIFT 0
-
-/***************************************************************************
- *RXRAM09 - Least significant byte of RXRAM[4] (queue pointer = 4)
- ***************************************************************************/
-/* HIF_MSPI :: RXRAM09 :: reserved0 [31:08] */
-#define BCHP_HIF_MSPI_RXRAM09_reserved0_MASK 0xffffff00
-#define BCHP_HIF_MSPI_RXRAM09_reserved0_SHIFT 8
-
-/* HIF_MSPI :: RXRAM09 :: rxram [07:00] */
-#define BCHP_HIF_MSPI_RXRAM09_rxram_MASK 0x000000ff
-#define BCHP_HIF_MSPI_RXRAM09_rxram_SHIFT 0
-
-/***************************************************************************
- *RXRAM10 - Most significant byte of RXRAM[5] (queue pointer = 5)
- ***************************************************************************/
-/* HIF_MSPI :: RXRAM10 :: reserved0 [31:08] */
-#define BCHP_HIF_MSPI_RXRAM10_reserved0_MASK 0xffffff00
-#define BCHP_HIF_MSPI_RXRAM10_reserved0_SHIFT 8
-
-/* HIF_MSPI :: RXRAM10 :: rxram [07:00] */
-#define BCHP_HIF_MSPI_RXRAM10_rxram_MASK 0x000000ff
-#define BCHP_HIF_MSPI_RXRAM10_rxram_SHIFT 0
-
-/***************************************************************************
- *RXRAM11 - Least significant byte of RXRAM[5] (queue pointer = 5)
- ***************************************************************************/
-/* HIF_MSPI :: RXRAM11 :: reserved0 [31:08] */
-#define BCHP_HIF_MSPI_RXRAM11_reserved0_MASK 0xffffff00
-#define BCHP_HIF_MSPI_RXRAM11_reserved0_SHIFT 8
-
-/* HIF_MSPI :: RXRAM11 :: rxram [07:00] */
-#define BCHP_HIF_MSPI_RXRAM11_rxram_MASK 0x000000ff
-#define BCHP_HIF_MSPI_RXRAM11_rxram_SHIFT 0
-
-/***************************************************************************
- *RXRAM12 - Most significant byte of RXRAM[6] (queue pointer = 6)
- ***************************************************************************/
-/* HIF_MSPI :: RXRAM12 :: reserved0 [31:08] */
-#define BCHP_HIF_MSPI_RXRAM12_reserved0_MASK 0xffffff00
-#define BCHP_HIF_MSPI_RXRAM12_reserved0_SHIFT 8
-
-/* HIF_MSPI :: RXRAM12 :: rxram [07:00] */
-#define BCHP_HIF_MSPI_RXRAM12_rxram_MASK 0x000000ff
-#define BCHP_HIF_MSPI_RXRAM12_rxram_SHIFT 0
-
-/***************************************************************************
- *RXRAM13 - Least significant byte of RXRAM[6] (queue pointer = 6)
- ***************************************************************************/
-/* HIF_MSPI :: RXRAM13 :: reserved0 [31:08] */
-#define BCHP_HIF_MSPI_RXRAM13_reserved0_MASK 0xffffff00
-#define BCHP_HIF_MSPI_RXRAM13_reserved0_SHIFT 8
-
-/* HIF_MSPI :: RXRAM13 :: rxram [07:00] */
-#define BCHP_HIF_MSPI_RXRAM13_rxram_MASK 0x000000ff
-#define BCHP_HIF_MSPI_RXRAM13_rxram_SHIFT 0
-
-/***************************************************************************
- *RXRAM14 - Most significant byte of RXRAM[7] (queue pointer = 7)
- ***************************************************************************/
-/* HIF_MSPI :: RXRAM14 :: reserved0 [31:08] */
-#define BCHP_HIF_MSPI_RXRAM14_reserved0_MASK 0xffffff00
-#define BCHP_HIF_MSPI_RXRAM14_reserved0_SHIFT 8
-
-/* HIF_MSPI :: RXRAM14 :: rxram [07:00] */
-#define BCHP_HIF_MSPI_RXRAM14_rxram_MASK 0x000000ff
-#define BCHP_HIF_MSPI_RXRAM14_rxram_SHIFT 0
-
-/***************************************************************************
- *RXRAM15 - Least significant byte of RXRAM[7] (queue pointer = 7)
- ***************************************************************************/
-/* HIF_MSPI :: RXRAM15 :: reserved0 [31:08] */
-#define BCHP_HIF_MSPI_RXRAM15_reserved0_MASK 0xffffff00
-#define BCHP_HIF_MSPI_RXRAM15_reserved0_SHIFT 8
-
-/* HIF_MSPI :: RXRAM15 :: rxram [07:00] */
-#define BCHP_HIF_MSPI_RXRAM15_rxram_MASK 0x000000ff
-#define BCHP_HIF_MSPI_RXRAM15_rxram_SHIFT 0
-
-/***************************************************************************
- *RXRAM16 - Most significant byte of RXRAM[8] (queue pointer = 8)
- ***************************************************************************/
-/* HIF_MSPI :: RXRAM16 :: reserved0 [31:08] */
-#define BCHP_HIF_MSPI_RXRAM16_reserved0_MASK 0xffffff00
-#define BCHP_HIF_MSPI_RXRAM16_reserved0_SHIFT 8
-
-/* HIF_MSPI :: RXRAM16 :: rxram [07:00] */
-#define BCHP_HIF_MSPI_RXRAM16_rxram_MASK 0x000000ff
-#define BCHP_HIF_MSPI_RXRAM16_rxram_SHIFT 0
-
-/***************************************************************************
- *RXRAM17 - Least significant byte of RXRAM[8] (queue pointer = 8)
- ***************************************************************************/
-/* HIF_MSPI :: RXRAM17 :: reserved0 [31:08] */
-#define BCHP_HIF_MSPI_RXRAM17_reserved0_MASK 0xffffff00
-#define BCHP_HIF_MSPI_RXRAM17_reserved0_SHIFT 8
-
-/* HIF_MSPI :: RXRAM17 :: rxram [07:00] */
-#define BCHP_HIF_MSPI_RXRAM17_rxram_MASK 0x000000ff
-#define BCHP_HIF_MSPI_RXRAM17_rxram_SHIFT 0
-
-/***************************************************************************
- *RXRAM18 - Most significant byte of RXRAM[9] (queue pointer = 9)
- ***************************************************************************/
-/* HIF_MSPI :: RXRAM18 :: reserved0 [31:08] */
-#define BCHP_HIF_MSPI_RXRAM18_reserved0_MASK 0xffffff00
-#define BCHP_HIF_MSPI_RXRAM18_reserved0_SHIFT 8
-
-/* HIF_MSPI :: RXRAM18 :: rxram [07:00] */
-#define BCHP_HIF_MSPI_RXRAM18_rxram_MASK 0x000000ff
-#define BCHP_HIF_MSPI_RXRAM18_rxram_SHIFT 0
-
-/***************************************************************************
- *RXRAM19 - Least significant byte of RXRAM[9] (queue pointer = 9)
- ***************************************************************************/
-/* HIF_MSPI :: RXRAM19 :: reserved0 [31:08] */
-#define BCHP_HIF_MSPI_RXRAM19_reserved0_MASK 0xffffff00
-#define BCHP_HIF_MSPI_RXRAM19_reserved0_SHIFT 8
-
-/* HIF_MSPI :: RXRAM19 :: rxram [07:00] */
-#define BCHP_HIF_MSPI_RXRAM19_rxram_MASK 0x000000ff
-#define BCHP_HIF_MSPI_RXRAM19_rxram_SHIFT 0
-
-/***************************************************************************
- *RXRAM20 - Most significant byte of RXRAM[10] (queue pointer = 10)
- ***************************************************************************/
-/* HIF_MSPI :: RXRAM20 :: reserved0 [31:08] */
-#define BCHP_HIF_MSPI_RXRAM20_reserved0_MASK 0xffffff00
-#define BCHP_HIF_MSPI_RXRAM20_reserved0_SHIFT 8
-
-/* HIF_MSPI :: RXRAM20 :: rxram [07:00] */
-#define BCHP_HIF_MSPI_RXRAM20_rxram_MASK 0x000000ff
-#define BCHP_HIF_MSPI_RXRAM20_rxram_SHIFT 0
-
-/***************************************************************************
- *RXRAM21 - Least significant byte of RXRAM[10] (queue pointer = 10)
- ***************************************************************************/
-/* HIF_MSPI :: RXRAM21 :: reserved0 [31:08] */
-#define BCHP_HIF_MSPI_RXRAM21_reserved0_MASK 0xffffff00
-#define BCHP_HIF_MSPI_RXRAM21_reserved0_SHIFT 8
-
-/* HIF_MSPI :: RXRAM21 :: rxram [07:00] */
-#define BCHP_HIF_MSPI_RXRAM21_rxram_MASK 0x000000ff
-#define BCHP_HIF_MSPI_RXRAM21_rxram_SHIFT 0
-
-/***************************************************************************
- *RXRAM22 - Most significant byte of RXRAM[11] (queue pointer = 11)
- ***************************************************************************/
-/* HIF_MSPI :: RXRAM22 :: reserved0 [31:08] */
-#define BCHP_HIF_MSPI_RXRAM22_reserved0_MASK 0xffffff00
-#define BCHP_HIF_MSPI_RXRAM22_reserved0_SHIFT 8
-
-/* HIF_MSPI :: RXRAM22 :: rxram [07:00] */
-#define BCHP_HIF_MSPI_RXRAM22_rxram_MASK 0x000000ff
-#define BCHP_HIF_MSPI_RXRAM22_rxram_SHIFT 0
-
-/***************************************************************************
- *RXRAM23 - Least significant byte of RXRAM[11] (queue pointer = 11)
- ***************************************************************************/
-/* HIF_MSPI :: RXRAM23 :: reserved0 [31:08] */
-#define BCHP_HIF_MSPI_RXRAM23_reserved0_MASK 0xffffff00
-#define BCHP_HIF_MSPI_RXRAM23_reserved0_SHIFT 8
-
-/* HIF_MSPI :: RXRAM23 :: rxram [07:00] */
-#define BCHP_HIF_MSPI_RXRAM23_rxram_MASK 0x000000ff
-#define BCHP_HIF_MSPI_RXRAM23_rxram_SHIFT 0
-
-/***************************************************************************
- *RXRAM24 - Most significant byte of RXRAM[12] (queue pointer = 12)
- ***************************************************************************/
-/* HIF_MSPI :: RXRAM24 :: reserved0 [31:08] */
-#define BCHP_HIF_MSPI_RXRAM24_reserved0_MASK 0xffffff00
-#define BCHP_HIF_MSPI_RXRAM24_reserved0_SHIFT 8
-
-/* HIF_MSPI :: RXRAM24 :: rxram [07:00] */
-#define BCHP_HIF_MSPI_RXRAM24_rxram_MASK 0x000000ff
-#define BCHP_HIF_MSPI_RXRAM24_rxram_SHIFT 0
-
-/***************************************************************************
- *RXRAM25 - Least significant byte of RXRAM[12] (queue pointer = 12)
- ***************************************************************************/
-/* HIF_MSPI :: RXRAM25 :: reserved0 [31:08] */
-#define BCHP_HIF_MSPI_RXRAM25_reserved0_MASK 0xffffff00
-#define BCHP_HIF_MSPI_RXRAM25_reserved0_SHIFT 8
-
-/* HIF_MSPI :: RXRAM25 :: rxram [07:00] */
-#define BCHP_HIF_MSPI_RXRAM25_rxram_MASK 0x000000ff
-#define BCHP_HIF_MSPI_RXRAM25_rxram_SHIFT 0
-
-/***************************************************************************
- *RXRAM26 - Most significant byte of RXRAM[13] (queue pointer = 13)
- ***************************************************************************/
-/* HIF_MSPI :: RXRAM26 :: reserved0 [31:08] */
-#define BCHP_HIF_MSPI_RXRAM26_reserved0_MASK 0xffffff00
-#define BCHP_HIF_MSPI_RXRAM26_reserved0_SHIFT 8
-
-/* HIF_MSPI :: RXRAM26 :: rxram [07:00] */
-#define BCHP_HIF_MSPI_RXRAM26_rxram_MASK 0x000000ff
-#define BCHP_HIF_MSPI_RXRAM26_rxram_SHIFT 0
-
-/***************************************************************************
- *RXRAM27 - Least significant byte of RXRAM[13] (queue pointer = 13)
- ***************************************************************************/
-/* HIF_MSPI :: RXRAM27 :: reserved0 [31:08] */
-#define BCHP_HIF_MSPI_RXRAM27_reserved0_MASK 0xffffff00
-#define BCHP_HIF_MSPI_RXRAM27_reserved0_SHIFT 8
-
-/* HIF_MSPI :: RXRAM27 :: rxram [07:00] */
-#define BCHP_HIF_MSPI_RXRAM27_rxram_MASK 0x000000ff
-#define BCHP_HIF_MSPI_RXRAM27_rxram_SHIFT 0
-
-/***************************************************************************
- *RXRAM28 - Most significant byte of RXRAM[14] (queue pointer = 14)
- ***************************************************************************/
-/* HIF_MSPI :: RXRAM28 :: reserved0 [31:08] */
-#define BCHP_HIF_MSPI_RXRAM28_reserved0_MASK 0xffffff00
-#define BCHP_HIF_MSPI_RXRAM28_reserved0_SHIFT 8
-
-/* HIF_MSPI :: RXRAM28 :: rxram [07:00] */
-#define BCHP_HIF_MSPI_RXRAM28_rxram_MASK 0x000000ff
-#define BCHP_HIF_MSPI_RXRAM28_rxram_SHIFT 0
-
-/***************************************************************************
- *RXRAM29 - Least significant byte of RXRAM[14] (queue pointer = 14)
- ***************************************************************************/
-/* HIF_MSPI :: RXRAM29 :: reserved0 [31:08] */
-#define BCHP_HIF_MSPI_RXRAM29_reserved0_MASK 0xffffff00
-#define BCHP_HIF_MSPI_RXRAM29_reserved0_SHIFT 8
-
-/* HIF_MSPI :: RXRAM29 :: rxram [07:00] */
-#define BCHP_HIF_MSPI_RXRAM29_rxram_MASK 0x000000ff
-#define BCHP_HIF_MSPI_RXRAM29_rxram_SHIFT 0
-
-/***************************************************************************
- *RXRAM30 - Most significant byte of RXRAM[15] (queue pointer = 15)
- ***************************************************************************/
-/* HIF_MSPI :: RXRAM30 :: reserved0 [31:08] */
-#define BCHP_HIF_MSPI_RXRAM30_reserved0_MASK 0xffffff00
-#define BCHP_HIF_MSPI_RXRAM30_reserved0_SHIFT 8
-
-/* HIF_MSPI :: RXRAM30 :: rxram [07:00] */
-#define BCHP_HIF_MSPI_RXRAM30_rxram_MASK 0x000000ff
-#define BCHP_HIF_MSPI_RXRAM30_rxram_SHIFT 0
-
-/***************************************************************************
- *RXRAM31 - Least significant byte of RXRAM[15] (queue pointer = 15)
- ***************************************************************************/
-/* HIF_MSPI :: RXRAM31 :: reserved0 [31:08] */
-#define BCHP_HIF_MSPI_RXRAM31_reserved0_MASK 0xffffff00
-#define BCHP_HIF_MSPI_RXRAM31_reserved0_SHIFT 8
-
-/* HIF_MSPI :: RXRAM31 :: rxram [07:00] */
-#define BCHP_HIF_MSPI_RXRAM31_rxram_MASK 0x000000ff
-#define BCHP_HIF_MSPI_RXRAM31_rxram_SHIFT 0
-
-/***************************************************************************
- *CDRAM00 - 8-bit command (queue pointer = 0)
- ***************************************************************************/
-/* HIF_MSPI :: CDRAM00 :: reserved0 [31:09] */
-#define BCHP_HIF_MSPI_CDRAM00_reserved0_MASK 0xfffffe00
-#define BCHP_HIF_MSPI_CDRAM00_reserved0_SHIFT 9
-
-/* HIF_MSPI :: CDRAM00 :: cdram [08:00] */
-#define BCHP_HIF_MSPI_CDRAM00_cdram_MASK 0x000001ff
-#define BCHP_HIF_MSPI_CDRAM00_cdram_SHIFT 0
-
-/***************************************************************************
- *CDRAM01 - 8-bit command (queue pointer = 1)
- ***************************************************************************/
-/* HIF_MSPI :: CDRAM01 :: reserved0 [31:09] */
-#define BCHP_HIF_MSPI_CDRAM01_reserved0_MASK 0xfffffe00
-#define BCHP_HIF_MSPI_CDRAM01_reserved0_SHIFT 9
-
-/* HIF_MSPI :: CDRAM01 :: cdram [08:00] */
-#define BCHP_HIF_MSPI_CDRAM01_cdram_MASK 0x000001ff
-#define BCHP_HIF_MSPI_CDRAM01_cdram_SHIFT 0
-
-/***************************************************************************
- *CDRAM02 - 8-bit command (queue pointer = 2)
- ***************************************************************************/
-/* HIF_MSPI :: CDRAM02 :: reserved0 [31:09] */
-#define BCHP_HIF_MSPI_CDRAM02_reserved0_MASK 0xfffffe00
-#define BCHP_HIF_MSPI_CDRAM02_reserved0_SHIFT 9
-
-/* HIF_MSPI :: CDRAM02 :: cdram [08:00] */
-#define BCHP_HIF_MSPI_CDRAM02_cdram_MASK 0x000001ff
-#define BCHP_HIF_MSPI_CDRAM02_cdram_SHIFT 0
-
-/***************************************************************************
- *CDRAM03 - 8-bit command (queue pointer = 3)
- ***************************************************************************/
-/* HIF_MSPI :: CDRAM03 :: reserved0 [31:09] */
-#define BCHP_HIF_MSPI_CDRAM03_reserved0_MASK 0xfffffe00
-#define BCHP_HIF_MSPI_CDRAM03_reserved0_SHIFT 9
-
-/* HIF_MSPI :: CDRAM03 :: cdram [08:00] */
-#define BCHP_HIF_MSPI_CDRAM03_cdram_MASK 0x000001ff
-#define BCHP_HIF_MSPI_CDRAM03_cdram_SHIFT 0
-
-/***************************************************************************
- *CDRAM04 - 8-bit command (queue pointer = 4)
- ***************************************************************************/
-/* HIF_MSPI :: CDRAM04 :: reserved0 [31:09] */
-#define BCHP_HIF_MSPI_CDRAM04_reserved0_MASK 0xfffffe00
-#define BCHP_HIF_MSPI_CDRAM04_reserved0_SHIFT 9
-
-/* HIF_MSPI :: CDRAM04 :: cdram [08:00] */
-#define BCHP_HIF_MSPI_CDRAM04_cdram_MASK 0x000001ff
-#define BCHP_HIF_MSPI_CDRAM04_cdram_SHIFT 0
-
-/***************************************************************************
- *CDRAM05 - 8-bit command (queue pointer = 5)
- ***************************************************************************/
-/* HIF_MSPI :: CDRAM05 :: reserved0 [31:09] */
-#define BCHP_HIF_MSPI_CDRAM05_reserved0_MASK 0xfffffe00
-#define BCHP_HIF_MSPI_CDRAM05_reserved0_SHIFT 9
-
-/* HIF_MSPI :: CDRAM05 :: cdram [08:00] */
-#define BCHP_HIF_MSPI_CDRAM05_cdram_MASK 0x000001ff
-#define BCHP_HIF_MSPI_CDRAM05_cdram_SHIFT 0
-
-/***************************************************************************
- *CDRAM06 - 8-bit command (queue pointer = 6)
- ***************************************************************************/
-/* HIF_MSPI :: CDRAM06 :: reserved0 [31:09] */
-#define BCHP_HIF_MSPI_CDRAM06_reserved0_MASK 0xfffffe00
-#define BCHP_HIF_MSPI_CDRAM06_reserved0_SHIFT 9
-
-/* HIF_MSPI :: CDRAM06 :: cdram [08:00] */
-#define BCHP_HIF_MSPI_CDRAM06_cdram_MASK 0x000001ff
-#define BCHP_HIF_MSPI_CDRAM06_cdram_SHIFT 0
-
-/***************************************************************************
- *CDRAM07 - 8-bit command (queue pointer = 7)
- ***************************************************************************/
-/* HIF_MSPI :: CDRAM07 :: reserved0 [31:09] */
-#define BCHP_HIF_MSPI_CDRAM07_reserved0_MASK 0xfffffe00
-#define BCHP_HIF_MSPI_CDRAM07_reserved0_SHIFT 9
-
-/* HIF_MSPI :: CDRAM07 :: cdram [08:00] */
-#define BCHP_HIF_MSPI_CDRAM07_cdram_MASK 0x000001ff
-#define BCHP_HIF_MSPI_CDRAM07_cdram_SHIFT 0
-
-/***************************************************************************
- *CDRAM08 - 8-bit command (queue pointer = 8)
- ***************************************************************************/
-/* HIF_MSPI :: CDRAM08 :: reserved0 [31:09] */
-#define BCHP_HIF_MSPI_CDRAM08_reserved0_MASK 0xfffffe00
-#define BCHP_HIF_MSPI_CDRAM08_reserved0_SHIFT 9
-
-/* HIF_MSPI :: CDRAM08 :: cdram [08:00] */
-#define BCHP_HIF_MSPI_CDRAM08_cdram_MASK 0x000001ff
-#define BCHP_HIF_MSPI_CDRAM08_cdram_SHIFT 0
-
-/***************************************************************************
- *CDRAM09 - 8-bit command (queue pointer = 9)
- ***************************************************************************/
-/* HIF_MSPI :: CDRAM09 :: reserved0 [31:09] */
-#define BCHP_HIF_MSPI_CDRAM09_reserved0_MASK 0xfffffe00
-#define BCHP_HIF_MSPI_CDRAM09_reserved0_SHIFT 9
-
-/* HIF_MSPI :: CDRAM09 :: cdram [08:00] */
-#define BCHP_HIF_MSPI_CDRAM09_cdram_MASK 0x000001ff
-#define BCHP_HIF_MSPI_CDRAM09_cdram_SHIFT 0
-
-/***************************************************************************
- *CDRAM10 - 8-bit command (queue pointer = a)
- ***************************************************************************/
-/* HIF_MSPI :: CDRAM10 :: reserved0 [31:09] */
-#define BCHP_HIF_MSPI_CDRAM10_reserved0_MASK 0xfffffe00
-#define BCHP_HIF_MSPI_CDRAM10_reserved0_SHIFT 9
-
-/* HIF_MSPI :: CDRAM10 :: cdram [08:00] */
-#define BCHP_HIF_MSPI_CDRAM10_cdram_MASK 0x000001ff
-#define BCHP_HIF_MSPI_CDRAM10_cdram_SHIFT 0
-
-/***************************************************************************
- *CDRAM11 - 8-bit command (queue pointer = b)
- ***************************************************************************/
-/* HIF_MSPI :: CDRAM11 :: reserved0 [31:09] */
-#define BCHP_HIF_MSPI_CDRAM11_reserved0_MASK 0xfffffe00
-#define BCHP_HIF_MSPI_CDRAM11_reserved0_SHIFT 9
-
-/* HIF_MSPI :: CDRAM11 :: cdram [08:00] */
-#define BCHP_HIF_MSPI_CDRAM11_cdram_MASK 0x000001ff
-#define BCHP_HIF_MSPI_CDRAM11_cdram_SHIFT 0
-
-/***************************************************************************
- *CDRAM12 - 8-bit command (queue pointer = c)
- ***************************************************************************/
-/* HIF_MSPI :: CDRAM12 :: reserved0 [31:09] */
-#define BCHP_HIF_MSPI_CDRAM12_reserved0_MASK 0xfffffe00
-#define BCHP_HIF_MSPI_CDRAM12_reserved0_SHIFT 9
-
-/* HIF_MSPI :: CDRAM12 :: cdram [08:00] */
-#define BCHP_HIF_MSPI_CDRAM12_cdram_MASK 0x000001ff
-#define BCHP_HIF_MSPI_CDRAM12_cdram_SHIFT 0
-
-/***************************************************************************
- *CDRAM13 - 8-bit command (queue pointer = d)
- ***************************************************************************/
-/* HIF_MSPI :: CDRAM13 :: reserved0 [31:09] */
-#define BCHP_HIF_MSPI_CDRAM13_reserved0_MASK 0xfffffe00
-#define BCHP_HIF_MSPI_CDRAM13_reserved0_SHIFT 9
-
-/* HIF_MSPI :: CDRAM13 :: cdram [08:00] */
-#define BCHP_HIF_MSPI_CDRAM13_cdram_MASK 0x000001ff
-#define BCHP_HIF_MSPI_CDRAM13_cdram_SHIFT 0
-
-/***************************************************************************
- *CDRAM14 - 8-bit command (queue pointer = e)
- ***************************************************************************/
-/* HIF_MSPI :: CDRAM14 :: reserved0 [31:09] */
-#define BCHP_HIF_MSPI_CDRAM14_reserved0_MASK 0xfffffe00
-#define BCHP_HIF_MSPI_CDRAM14_reserved0_SHIFT 9
-
-/* HIF_MSPI :: CDRAM14 :: cdram [08:00] */
-#define BCHP_HIF_MSPI_CDRAM14_cdram_MASK 0x000001ff
-#define BCHP_HIF_MSPI_CDRAM14_cdram_SHIFT 0
-
-/***************************************************************************
- *CDRAM15 - 8-bit command (queue pointer = f)
- ***************************************************************************/
-/* HIF_MSPI :: CDRAM15 :: reserved0 [31:09] */
-#define BCHP_HIF_MSPI_CDRAM15_reserved0_MASK 0xfffffe00
-#define BCHP_HIF_MSPI_CDRAM15_reserved0_SHIFT 9
-
-/* HIF_MSPI :: CDRAM15 :: cdram [08:00] */
-#define BCHP_HIF_MSPI_CDRAM15_cdram_MASK 0x000001ff
-#define BCHP_HIF_MSPI_CDRAM15_cdram_SHIFT 0
-
-/***************************************************************************
- *WRITE_LOCK - Control bit to lock group of write commands
- ***************************************************************************/
-/* HIF_MSPI :: WRITE_LOCK :: reserved0 [31:01] */
-#define BCHP_HIF_MSPI_WRITE_LOCK_reserved0_MASK 0xfffffffe
-#define BCHP_HIF_MSPI_WRITE_LOCK_reserved0_SHIFT 1
-
-/* HIF_MSPI :: WRITE_LOCK :: WriteLock [00:00] */
-#define BCHP_HIF_MSPI_WRITE_LOCK_WriteLock_MASK 0x00000001
-#define BCHP_HIF_MSPI_WRITE_LOCK_WriteLock_SHIFT 0
-#define BCHP_HIF_MSPI_WRITE_LOCK_WriteLock_DEFAULT 0x00000000
-
-/***************************************************************************
- *DISABLE_FLUSH_GEN - Debug bit to mask the generation of flush signals from Mspi
- ***************************************************************************/
-/* HIF_MSPI :: DISABLE_FLUSH_GEN :: reserved0 [31:01] */
-#define BCHP_HIF_MSPI_DISABLE_FLUSH_GEN_reserved0_MASK 0xfffffffe
-#define BCHP_HIF_MSPI_DISABLE_FLUSH_GEN_reserved0_SHIFT 1
-
-/* HIF_MSPI :: DISABLE_FLUSH_GEN :: DisableFlushGen [00:00] */
-#define BCHP_HIF_MSPI_DISABLE_FLUSH_GEN_DisableFlushGen_MASK 0x00000001
-#define BCHP_HIF_MSPI_DISABLE_FLUSH_GEN_DisableFlushGen_SHIFT 0
-#define BCHP_HIF_MSPI_DISABLE_FLUSH_GEN_DisableFlushGen_DEFAULT 0x00000000
-
-#endif /* #ifndef BCHP_HIF_MSPI_H__ */
-
-/* End of File */
diff --git a/include/linux/brcmstb/7366b0/bchp_hif_spi_intr2.h b/include/linux/brcmstb/7366b0/bchp_hif_spi_intr2.h
deleted file mode 100644
index d027ca6..0000000
--- a/include/linux/brcmstb/7366b0/bchp_hif_spi_intr2.h
+++ /dev/null
@@ -1,564 +0,0 @@
-/***************************************************************************
- * Copyright (c) 1999-2012, Broadcom Corporation
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
- *
- * Module Description:
- * DO NOT EDIT THIS FILE DIRECTLY
- *
- * This module was generated magically with RDB from a source description
- * file. You must edit the source file for changes to be made to this file.
- *
- *
- * Date: Generated on Wed Oct 17 03:11:30 2012
- * MD5 Checksum d41d8cd98f00b204e9800998ecf8427e
- *
- * Compiled with: RDB Utility combo_header.pl
- * RDB Parser 3.0
- * unknown unknown
- * Perl Interpreter 5.008008
- * Operating System linux
- *
- * Revision History:
- *
- * $brcm_Log: $
- *
- ***************************************************************************/
-
-#ifndef BCHP_HIF_SPI_INTR2_H__
-#define BCHP_HIF_SPI_INTR2_H__
-
-/***************************************************************************
- *HIF_SPI_INTR2 - HIF Level 2 Interrupt Controller Registers for SPI
- ***************************************************************************/
-#define BCHP_HIF_SPI_INTR2_CPU_STATUS 0x00441a00 /* CPU interrupt Status Register */
-#define BCHP_HIF_SPI_INTR2_CPU_SET 0x00441a04 /* CPU interrupt Set Register */
-#define BCHP_HIF_SPI_INTR2_CPU_CLEAR 0x00441a08 /* CPU interrupt Clear Register */
-#define BCHP_HIF_SPI_INTR2_CPU_MASK_STATUS 0x00441a0c /* CPU interrupt Mask Status Register */
-#define BCHP_HIF_SPI_INTR2_CPU_MASK_SET 0x00441a10 /* CPU interrupt Mask Set Register */
-#define BCHP_HIF_SPI_INTR2_CPU_MASK_CLEAR 0x00441a14 /* CPU interrupt Mask Clear Register */
-#define BCHP_HIF_SPI_INTR2_PCI_STATUS 0x00441a18 /* PCI interrupt Status Register */
-#define BCHP_HIF_SPI_INTR2_PCI_SET 0x00441a1c /* PCI interrupt Set Register */
-#define BCHP_HIF_SPI_INTR2_PCI_CLEAR 0x00441a20 /* PCI interrupt Clear Register */
-#define BCHP_HIF_SPI_INTR2_PCI_MASK_STATUS 0x00441a24 /* PCI interrupt Mask Status Register */
-#define BCHP_HIF_SPI_INTR2_PCI_MASK_SET 0x00441a28 /* PCI interrupt Mask Set Register */
-#define BCHP_HIF_SPI_INTR2_PCI_MASK_CLEAR 0x00441a2c /* PCI interrupt Mask Clear Register */
-
-/***************************************************************************
- *CPU_STATUS - CPU interrupt Status Register
- ***************************************************************************/
-/* HIF_SPI_INTR2 :: CPU_STATUS :: reserved0 [31:07] */
-#define BCHP_HIF_SPI_INTR2_CPU_STATUS_reserved0_MASK 0xffffff80
-#define BCHP_HIF_SPI_INTR2_CPU_STATUS_reserved0_SHIFT 7
-
-/* HIF_SPI_INTR2 :: CPU_STATUS :: MSPI_HALTED [06:06] */
-#define BCHP_HIF_SPI_INTR2_CPU_STATUS_MSPI_HALTED_MASK 0x00000040
-#define BCHP_HIF_SPI_INTR2_CPU_STATUS_MSPI_HALTED_SHIFT 6
-#define BCHP_HIF_SPI_INTR2_CPU_STATUS_MSPI_HALTED_DEFAULT 0x00000000
-
-/* HIF_SPI_INTR2 :: CPU_STATUS :: MSPI_DONE [05:05] */
-#define BCHP_HIF_SPI_INTR2_CPU_STATUS_MSPI_DONE_MASK 0x00000020
-#define BCHP_HIF_SPI_INTR2_CPU_STATUS_MSPI_DONE_SHIFT 5
-#define BCHP_HIF_SPI_INTR2_CPU_STATUS_MSPI_DONE_DEFAULT 0x00000000
-
-/* HIF_SPI_INTR2 :: CPU_STATUS :: SPI_LR_OVERREAD [04:04] */
-#define BCHP_HIF_SPI_INTR2_CPU_STATUS_SPI_LR_OVERREAD_MASK 0x00000010
-#define BCHP_HIF_SPI_INTR2_CPU_STATUS_SPI_LR_OVERREAD_SHIFT 4
-#define BCHP_HIF_SPI_INTR2_CPU_STATUS_SPI_LR_OVERREAD_DEFAULT 0x00000000
-
-/* HIF_SPI_INTR2 :: CPU_STATUS :: SPI_LR_SESSION_DONE [03:03] */
-#define BCHP_HIF_SPI_INTR2_CPU_STATUS_SPI_LR_SESSION_DONE_MASK 0x00000008
-#define BCHP_HIF_SPI_INTR2_CPU_STATUS_SPI_LR_SESSION_DONE_SHIFT 3
-#define BCHP_HIF_SPI_INTR2_CPU_STATUS_SPI_LR_SESSION_DONE_DEFAULT 0x00000000
-
-/* HIF_SPI_INTR2 :: CPU_STATUS :: SPI_LR_IMPATIENT [02:02] */
-#define BCHP_HIF_SPI_INTR2_CPU_STATUS_SPI_LR_IMPATIENT_MASK 0x00000004
-#define BCHP_HIF_SPI_INTR2_CPU_STATUS_SPI_LR_IMPATIENT_SHIFT 2
-#define BCHP_HIF_SPI_INTR2_CPU_STATUS_SPI_LR_IMPATIENT_DEFAULT 0x00000000
-
-/* HIF_SPI_INTR2 :: CPU_STATUS :: SPI_LR_SESSION_ABORTED [01:01] */
-#define BCHP_HIF_SPI_INTR2_CPU_STATUS_SPI_LR_SESSION_ABORTED_MASK 0x00000002
-#define BCHP_HIF_SPI_INTR2_CPU_STATUS_SPI_LR_SESSION_ABORTED_SHIFT 1
-#define BCHP_HIF_SPI_INTR2_CPU_STATUS_SPI_LR_SESSION_ABORTED_DEFAULT 0x00000000
-
-/* HIF_SPI_INTR2 :: CPU_STATUS :: SPI_LR_FULLNESS_REACHED [00:00] */
-#define BCHP_HIF_SPI_INTR2_CPU_STATUS_SPI_LR_FULLNESS_REACHED_MASK 0x00000001
-#define BCHP_HIF_SPI_INTR2_CPU_STATUS_SPI_LR_FULLNESS_REACHED_SHIFT 0
-#define BCHP_HIF_SPI_INTR2_CPU_STATUS_SPI_LR_FULLNESS_REACHED_DEFAULT 0x00000000
-
-/***************************************************************************
- *CPU_SET - CPU interrupt Set Register
- ***************************************************************************/
-/* HIF_SPI_INTR2 :: CPU_SET :: reserved0 [31:07] */
-#define BCHP_HIF_SPI_INTR2_CPU_SET_reserved0_MASK 0xffffff80
-#define BCHP_HIF_SPI_INTR2_CPU_SET_reserved0_SHIFT 7
-
-/* HIF_SPI_INTR2 :: CPU_SET :: MSPI_HALTED [06:06] */
-#define BCHP_HIF_SPI_INTR2_CPU_SET_MSPI_HALTED_MASK 0x00000040
-#define BCHP_HIF_SPI_INTR2_CPU_SET_MSPI_HALTED_SHIFT 6
-#define BCHP_HIF_SPI_INTR2_CPU_SET_MSPI_HALTED_DEFAULT 0x00000000
-
-/* HIF_SPI_INTR2 :: CPU_SET :: MSPI_DONE [05:05] */
-#define BCHP_HIF_SPI_INTR2_CPU_SET_MSPI_DONE_MASK 0x00000020
-#define BCHP_HIF_SPI_INTR2_CPU_SET_MSPI_DONE_SHIFT 5
-#define BCHP_HIF_SPI_INTR2_CPU_SET_MSPI_DONE_DEFAULT 0x00000000
-
-/* HIF_SPI_INTR2 :: CPU_SET :: SPI_LR_OVERREAD [04:04] */
-#define BCHP_HIF_SPI_INTR2_CPU_SET_SPI_LR_OVERREAD_MASK 0x00000010
-#define BCHP_HIF_SPI_INTR2_CPU_SET_SPI_LR_OVERREAD_SHIFT 4
-#define BCHP_HIF_SPI_INTR2_CPU_SET_SPI_LR_OVERREAD_DEFAULT 0x00000000
-
-/* HIF_SPI_INTR2 :: CPU_SET :: SPI_LR_SESSION_DONE [03:03] */
-#define BCHP_HIF_SPI_INTR2_CPU_SET_SPI_LR_SESSION_DONE_MASK 0x00000008
-#define BCHP_HIF_SPI_INTR2_CPU_SET_SPI_LR_SESSION_DONE_SHIFT 3
-#define BCHP_HIF_SPI_INTR2_CPU_SET_SPI_LR_SESSION_DONE_DEFAULT 0x00000000
-
-/* HIF_SPI_INTR2 :: CPU_SET :: SPI_LR_IMPATIENT [02:02] */
-#define BCHP_HIF_SPI_INTR2_CPU_SET_SPI_LR_IMPATIENT_MASK 0x00000004
-#define BCHP_HIF_SPI_INTR2_CPU_SET_SPI_LR_IMPATIENT_SHIFT 2
-#define BCHP_HIF_SPI_INTR2_CPU_SET_SPI_LR_IMPATIENT_DEFAULT 0x00000000
-
-/* HIF_SPI_INTR2 :: CPU_SET :: SPI_LR_SESSION_ABORTED [01:01] */
-#define BCHP_HIF_SPI_INTR2_CPU_SET_SPI_LR_SESSION_ABORTED_MASK 0x00000002
-#define BCHP_HIF_SPI_INTR2_CPU_SET_SPI_LR_SESSION_ABORTED_SHIFT 1
-#define BCHP_HIF_SPI_INTR2_CPU_SET_SPI_LR_SESSION_ABORTED_DEFAULT 0x00000000
-
-/* HIF_SPI_INTR2 :: CPU_SET :: SPI_LR_FULLNESS_REACHED [00:00] */
-#define BCHP_HIF_SPI_INTR2_CPU_SET_SPI_LR_FULLNESS_REACHED_MASK 0x00000001
-#define BCHP_HIF_SPI_INTR2_CPU_SET_SPI_LR_FULLNESS_REACHED_SHIFT 0
-#define BCHP_HIF_SPI_INTR2_CPU_SET_SPI_LR_FULLNESS_REACHED_DEFAULT 0x00000000
-
-/***************************************************************************
- *CPU_CLEAR - CPU interrupt Clear Register
- ***************************************************************************/
-/* HIF_SPI_INTR2 :: CPU_CLEAR :: reserved0 [31:07] */
-#define BCHP_HIF_SPI_INTR2_CPU_CLEAR_reserved0_MASK 0xffffff80
-#define BCHP_HIF_SPI_INTR2_CPU_CLEAR_reserved0_SHIFT 7
-
-/* HIF_SPI_INTR2 :: CPU_CLEAR :: MSPI_HALTED [06:06] */
-#define BCHP_HIF_SPI_INTR2_CPU_CLEAR_MSPI_HALTED_MASK 0x00000040
-#define BCHP_HIF_SPI_INTR2_CPU_CLEAR_MSPI_HALTED_SHIFT 6
-#define BCHP_HIF_SPI_INTR2_CPU_CLEAR_MSPI_HALTED_DEFAULT 0x00000000
-
-/* HIF_SPI_INTR2 :: CPU_CLEAR :: MSPI_DONE [05:05] */
-#define BCHP_HIF_SPI_INTR2_CPU_CLEAR_MSPI_DONE_MASK 0x00000020
-#define BCHP_HIF_SPI_INTR2_CPU_CLEAR_MSPI_DONE_SHIFT 5
-#define BCHP_HIF_SPI_INTR2_CPU_CLEAR_MSPI_DONE_DEFAULT 0x00000000
-
-/* HIF_SPI_INTR2 :: CPU_CLEAR :: SPI_LR_OVERREAD [04:04] */
-#define BCHP_HIF_SPI_INTR2_CPU_CLEAR_SPI_LR_OVERREAD_MASK 0x00000010
-#define BCHP_HIF_SPI_INTR2_CPU_CLEAR_SPI_LR_OVERREAD_SHIFT 4
-#define BCHP_HIF_SPI_INTR2_CPU_CLEAR_SPI_LR_OVERREAD_DEFAULT 0x00000000
-
-/* HIF_SPI_INTR2 :: CPU_CLEAR :: SPI_LR_SESSION_DONE [03:03] */
-#define BCHP_HIF_SPI_INTR2_CPU_CLEAR_SPI_LR_SESSION_DONE_MASK 0x00000008
-#define BCHP_HIF_SPI_INTR2_CPU_CLEAR_SPI_LR_SESSION_DONE_SHIFT 3
-#define BCHP_HIF_SPI_INTR2_CPU_CLEAR_SPI_LR_SESSION_DONE_DEFAULT 0x00000000
-
-/* HIF_SPI_INTR2 :: CPU_CLEAR :: SPI_LR_IMPATIENT [02:02] */
-#define BCHP_HIF_SPI_INTR2_CPU_CLEAR_SPI_LR_IMPATIENT_MASK 0x00000004
-#define BCHP_HIF_SPI_INTR2_CPU_CLEAR_SPI_LR_IMPATIENT_SHIFT 2
-#define BCHP_HIF_SPI_INTR2_CPU_CLEAR_SPI_LR_IMPATIENT_DEFAULT 0x00000000
-
-/* HIF_SPI_INTR2 :: CPU_CLEAR :: SPI_LR_SESSION_ABORTED [01:01] */
-#define BCHP_HIF_SPI_INTR2_CPU_CLEAR_SPI_LR_SESSION_ABORTED_MASK 0x00000002
-#define BCHP_HIF_SPI_INTR2_CPU_CLEAR_SPI_LR_SESSION_ABORTED_SHIFT 1
-#define BCHP_HIF_SPI_INTR2_CPU_CLEAR_SPI_LR_SESSION_ABORTED_DEFAULT 0x00000000
-
-/* HIF_SPI_INTR2 :: CPU_CLEAR :: SPI_LR_FULLNESS_REACHED [00:00] */
-#define BCHP_HIF_SPI_INTR2_CPU_CLEAR_SPI_LR_FULLNESS_REACHED_MASK 0x00000001
-#define BCHP_HIF_SPI_INTR2_CPU_CLEAR_SPI_LR_FULLNESS_REACHED_SHIFT 0
-#define BCHP_HIF_SPI_INTR2_CPU_CLEAR_SPI_LR_FULLNESS_REACHED_DEFAULT 0x00000000
-
-/***************************************************************************
- *CPU_MASK_STATUS - CPU interrupt Mask Status Register
- ***************************************************************************/
-/* HIF_SPI_INTR2 :: CPU_MASK_STATUS :: reserved0 [31:07] */
-#define BCHP_HIF_SPI_INTR2_CPU_MASK_STATUS_reserved0_MASK 0xffffff80
-#define BCHP_HIF_SPI_INTR2_CPU_MASK_STATUS_reserved0_SHIFT 7
-
-/* HIF_SPI_INTR2 :: CPU_MASK_STATUS :: MSPI_HALTED [06:06] */
-#define BCHP_HIF_SPI_INTR2_CPU_MASK_STATUS_MSPI_HALTED_MASK 0x00000040
-#define BCHP_HIF_SPI_INTR2_CPU_MASK_STATUS_MSPI_HALTED_SHIFT 6
-#define BCHP_HIF_SPI_INTR2_CPU_MASK_STATUS_MSPI_HALTED_DEFAULT 0x00000000
-
-/* HIF_SPI_INTR2 :: CPU_MASK_STATUS :: MSPI_DONE [05:05] */
-#define BCHP_HIF_SPI_INTR2_CPU_MASK_STATUS_MSPI_DONE_MASK 0x00000020
-#define BCHP_HIF_SPI_INTR2_CPU_MASK_STATUS_MSPI_DONE_SHIFT 5
-#define BCHP_HIF_SPI_INTR2_CPU_MASK_STATUS_MSPI_DONE_DEFAULT 0x00000000
-
-/* HIF_SPI_INTR2 :: CPU_MASK_STATUS :: SPI_LR_OVERREAD [04:04] */
-#define BCHP_HIF_SPI_INTR2_CPU_MASK_STATUS_SPI_LR_OVERREAD_MASK 0x00000010
-#define BCHP_HIF_SPI_INTR2_CPU_MASK_STATUS_SPI_LR_OVERREAD_SHIFT 4
-#define BCHP_HIF_SPI_INTR2_CPU_MASK_STATUS_SPI_LR_OVERREAD_DEFAULT 0x00000000
-
-/* HIF_SPI_INTR2 :: CPU_MASK_STATUS :: SPI_LR_SESSION_DONE [03:03] */
-#define BCHP_HIF_SPI_INTR2_CPU_MASK_STATUS_SPI_LR_SESSION_DONE_MASK 0x00000008
-#define BCHP_HIF_SPI_INTR2_CPU_MASK_STATUS_SPI_LR_SESSION_DONE_SHIFT 3
-#define BCHP_HIF_SPI_INTR2_CPU_MASK_STATUS_SPI_LR_SESSION_DONE_DEFAULT 0x00000000
-
-/* HIF_SPI_INTR2 :: CPU_MASK_STATUS :: SPI_LR_IMPATIENT [02:02] */
-#define BCHP_HIF_SPI_INTR2_CPU_MASK_STATUS_SPI_LR_IMPATIENT_MASK 0x00000004
-#define BCHP_HIF_SPI_INTR2_CPU_MASK_STATUS_SPI_LR_IMPATIENT_SHIFT 2
-#define BCHP_HIF_SPI_INTR2_CPU_MASK_STATUS_SPI_LR_IMPATIENT_DEFAULT 0x00000000
-
-/* HIF_SPI_INTR2 :: CPU_MASK_STATUS :: SPI_LR_SESSION_ABORTED [01:01] */
-#define BCHP_HIF_SPI_INTR2_CPU_MASK_STATUS_SPI_LR_SESSION_ABORTED_MASK 0x00000002
-#define BCHP_HIF_SPI_INTR2_CPU_MASK_STATUS_SPI_LR_SESSION_ABORTED_SHIFT 1
-#define BCHP_HIF_SPI_INTR2_CPU_MASK_STATUS_SPI_LR_SESSION_ABORTED_DEFAULT 0x00000000
-
-/* HIF_SPI_INTR2 :: CPU_MASK_STATUS :: SPI_LR_FULLNESS_REACHED [00:00] */
-#define BCHP_HIF_SPI_INTR2_CPU_MASK_STATUS_SPI_LR_FULLNESS_REACHED_MASK 0x00000001
-#define BCHP_HIF_SPI_INTR2_CPU_MASK_STATUS_SPI_LR_FULLNESS_REACHED_SHIFT 0
-#define BCHP_HIF_SPI_INTR2_CPU_MASK_STATUS_SPI_LR_FULLNESS_REACHED_DEFAULT 0x00000000
-
-/***************************************************************************
- *CPU_MASK_SET - CPU interrupt Mask Set Register
- ***************************************************************************/
-/* HIF_SPI_INTR2 :: CPU_MASK_SET :: reserved0 [31:07] */
-#define BCHP_HIF_SPI_INTR2_CPU_MASK_SET_reserved0_MASK 0xffffff80
-#define BCHP_HIF_SPI_INTR2_CPU_MASK_SET_reserved0_SHIFT 7
-
-/* HIF_SPI_INTR2 :: CPU_MASK_SET :: MSPI_HALTED [06:06] */
-#define BCHP_HIF_SPI_INTR2_CPU_MASK_SET_MSPI_HALTED_MASK 0x00000040
-#define BCHP_HIF_SPI_INTR2_CPU_MASK_SET_MSPI_HALTED_SHIFT 6
-#define BCHP_HIF_SPI_INTR2_CPU_MASK_SET_MSPI_HALTED_DEFAULT 0x00000000
-
-/* HIF_SPI_INTR2 :: CPU_MASK_SET :: MSPI_DONE [05:05] */
-#define BCHP_HIF_SPI_INTR2_CPU_MASK_SET_MSPI_DONE_MASK 0x00000020
-#define BCHP_HIF_SPI_INTR2_CPU_MASK_SET_MSPI_DONE_SHIFT 5
-#define BCHP_HIF_SPI_INTR2_CPU_MASK_SET_MSPI_DONE_DEFAULT 0x00000000
-
-/* HIF_SPI_INTR2 :: CPU_MASK_SET :: SPI_LR_OVERREAD [04:04] */
-#define BCHP_HIF_SPI_INTR2_CPU_MASK_SET_SPI_LR_OVERREAD_MASK 0x00000010
-#define BCHP_HIF_SPI_INTR2_CPU_MASK_SET_SPI_LR_OVERREAD_SHIFT 4
-#define BCHP_HIF_SPI_INTR2_CPU_MASK_SET_SPI_LR_OVERREAD_DEFAULT 0x00000000
-
-/* HIF_SPI_INTR2 :: CPU_MASK_SET :: SPI_LR_SESSION_DONE [03:03] */
-#define BCHP_HIF_SPI_INTR2_CPU_MASK_SET_SPI_LR_SESSION_DONE_MASK 0x00000008
-#define BCHP_HIF_SPI_INTR2_CPU_MASK_SET_SPI_LR_SESSION_DONE_SHIFT 3
-#define BCHP_HIF_SPI_INTR2_CPU_MASK_SET_SPI_LR_SESSION_DONE_DEFAULT 0x00000000
-
-/* HIF_SPI_INTR2 :: CPU_MASK_SET :: SPI_LR_IMPATIENT [02:02] */
-#define BCHP_HIF_SPI_INTR2_CPU_MASK_SET_SPI_LR_IMPATIENT_MASK 0x00000004
-#define BCHP_HIF_SPI_INTR2_CPU_MASK_SET_SPI_LR_IMPATIENT_SHIFT 2
-#define BCHP_HIF_SPI_INTR2_CPU_MASK_SET_SPI_LR_IMPATIENT_DEFAULT 0x00000000
-
-/* HIF_SPI_INTR2 :: CPU_MASK_SET :: SPI_LR_SESSION_ABORTED [01:01] */
-#define BCHP_HIF_SPI_INTR2_CPU_MASK_SET_SPI_LR_SESSION_ABORTED_MASK 0x00000002
-#define BCHP_HIF_SPI_INTR2_CPU_MASK_SET_SPI_LR_SESSION_ABORTED_SHIFT 1
-#define BCHP_HIF_SPI_INTR2_CPU_MASK_SET_SPI_LR_SESSION_ABORTED_DEFAULT 0x00000000
-
-/* HIF_SPI_INTR2 :: CPU_MASK_SET :: SPI_LR_FULLNESS_REACHED [00:00] */
-#define BCHP_HIF_SPI_INTR2_CPU_MASK_SET_SPI_LR_FULLNESS_REACHED_MASK 0x00000001
-#define BCHP_HIF_SPI_INTR2_CPU_MASK_SET_SPI_LR_FULLNESS_REACHED_SHIFT 0
-#define BCHP_HIF_SPI_INTR2_CPU_MASK_SET_SPI_LR_FULLNESS_REACHED_DEFAULT 0x00000000
-
-/***************************************************************************
- *CPU_MASK_CLEAR - CPU interrupt Mask Clear Register
- ***************************************************************************/
-/* HIF_SPI_INTR2 :: CPU_MASK_CLEAR :: reserved0 [31:07] */
-#define BCHP_HIF_SPI_INTR2_CPU_MASK_CLEAR_reserved0_MASK 0xffffff80
-#define BCHP_HIF_SPI_INTR2_CPU_MASK_CLEAR_reserved0_SHIFT 7
-
-/* HIF_SPI_INTR2 :: CPU_MASK_CLEAR :: MSPI_HALTED [06:06] */
-#define BCHP_HIF_SPI_INTR2_CPU_MASK_CLEAR_MSPI_HALTED_MASK 0x00000040
-#define BCHP_HIF_SPI_INTR2_CPU_MASK_CLEAR_MSPI_HALTED_SHIFT 6
-#define BCHP_HIF_SPI_INTR2_CPU_MASK_CLEAR_MSPI_HALTED_DEFAULT 0x00000000
-
-/* HIF_SPI_INTR2 :: CPU_MASK_CLEAR :: MSPI_DONE [05:05] */
-#define BCHP_HIF_SPI_INTR2_CPU_MASK_CLEAR_MSPI_DONE_MASK 0x00000020
-#define BCHP_HIF_SPI_INTR2_CPU_MASK_CLEAR_MSPI_DONE_SHIFT 5
-#define BCHP_HIF_SPI_INTR2_CPU_MASK_CLEAR_MSPI_DONE_DEFAULT 0x00000000
-
-/* HIF_SPI_INTR2 :: CPU_MASK_CLEAR :: SPI_LR_OVERREAD [04:04] */
-#define BCHP_HIF_SPI_INTR2_CPU_MASK_CLEAR_SPI_LR_OVERREAD_MASK 0x00000010
-#define BCHP_HIF_SPI_INTR2_CPU_MASK_CLEAR_SPI_LR_OVERREAD_SHIFT 4
-#define BCHP_HIF_SPI_INTR2_CPU_MASK_CLEAR_SPI_LR_OVERREAD_DEFAULT 0x00000000
-
-/* HIF_SPI_INTR2 :: CPU_MASK_CLEAR :: SPI_LR_SESSION_DONE [03:03] */
-#define BCHP_HIF_SPI_INTR2_CPU_MASK_CLEAR_SPI_LR_SESSION_DONE_MASK 0x00000008
-#define BCHP_HIF_SPI_INTR2_CPU_MASK_CLEAR_SPI_LR_SESSION_DONE_SHIFT 3
-#define BCHP_HIF_SPI_INTR2_CPU_MASK_CLEAR_SPI_LR_SESSION_DONE_DEFAULT 0x00000000
-
-/* HIF_SPI_INTR2 :: CPU_MASK_CLEAR :: SPI_LR_IMPATIENT [02:02] */
-#define BCHP_HIF_SPI_INTR2_CPU_MASK_CLEAR_SPI_LR_IMPATIENT_MASK 0x00000004
-#define BCHP_HIF_SPI_INTR2_CPU_MASK_CLEAR_SPI_LR_IMPATIENT_SHIFT 2
-#define BCHP_HIF_SPI_INTR2_CPU_MASK_CLEAR_SPI_LR_IMPATIENT_DEFAULT 0x00000000
-
-/* HIF_SPI_INTR2 :: CPU_MASK_CLEAR :: SPI_LR_SESSION_ABORTED [01:01] */
-#define BCHP_HIF_SPI_INTR2_CPU_MASK_CLEAR_SPI_LR_SESSION_ABORTED_MASK 0x00000002
-#define BCHP_HIF_SPI_INTR2_CPU_MASK_CLEAR_SPI_LR_SESSION_ABORTED_SHIFT 1
-#define BCHP_HIF_SPI_INTR2_CPU_MASK_CLEAR_SPI_LR_SESSION_ABORTED_DEFAULT 0x00000000
-
-/* HIF_SPI_INTR2 :: CPU_MASK_CLEAR :: SPI_LR_FULLNESS_REACHED [00:00] */
-#define BCHP_HIF_SPI_INTR2_CPU_MASK_CLEAR_SPI_LR_FULLNESS_REACHED_MASK 0x00000001
-#define BCHP_HIF_SPI_INTR2_CPU_MASK_CLEAR_SPI_LR_FULLNESS_REACHED_SHIFT 0
-#define BCHP_HIF_SPI_INTR2_CPU_MASK_CLEAR_SPI_LR_FULLNESS_REACHED_DEFAULT 0x00000000
-
-/***************************************************************************
- *PCI_STATUS - PCI interrupt Status Register
- ***************************************************************************/
-/* HIF_SPI_INTR2 :: PCI_STATUS :: reserved0 [31:07] */
-#define BCHP_HIF_SPI_INTR2_PCI_STATUS_reserved0_MASK 0xffffff80
-#define BCHP_HIF_SPI_INTR2_PCI_STATUS_reserved0_SHIFT 7
-
-/* HIF_SPI_INTR2 :: PCI_STATUS :: MSPI_HALTED [06:06] */
-#define BCHP_HIF_SPI_INTR2_PCI_STATUS_MSPI_HALTED_MASK 0x00000040
-#define BCHP_HIF_SPI_INTR2_PCI_STATUS_MSPI_HALTED_SHIFT 6
-#define BCHP_HIF_SPI_INTR2_PCI_STATUS_MSPI_HALTED_DEFAULT 0x00000000
-
-/* HIF_SPI_INTR2 :: PCI_STATUS :: MSPI_DONE [05:05] */
-#define BCHP_HIF_SPI_INTR2_PCI_STATUS_MSPI_DONE_MASK 0x00000020
-#define BCHP_HIF_SPI_INTR2_PCI_STATUS_MSPI_DONE_SHIFT 5
-#define BCHP_HIF_SPI_INTR2_PCI_STATUS_MSPI_DONE_DEFAULT 0x00000000
-
-/* HIF_SPI_INTR2 :: PCI_STATUS :: SPI_LR_OVERREAD [04:04] */
-#define BCHP_HIF_SPI_INTR2_PCI_STATUS_SPI_LR_OVERREAD_MASK 0x00000010
-#define BCHP_HIF_SPI_INTR2_PCI_STATUS_SPI_LR_OVERREAD_SHIFT 4
-#define BCHP_HIF_SPI_INTR2_PCI_STATUS_SPI_LR_OVERREAD_DEFAULT 0x00000000
-
-/* HIF_SPI_INTR2 :: PCI_STATUS :: SPI_LR_SESSION_DONE [03:03] */
-#define BCHP_HIF_SPI_INTR2_PCI_STATUS_SPI_LR_SESSION_DONE_MASK 0x00000008
-#define BCHP_HIF_SPI_INTR2_PCI_STATUS_SPI_LR_SESSION_DONE_SHIFT 3
-#define BCHP_HIF_SPI_INTR2_PCI_STATUS_SPI_LR_SESSION_DONE_DEFAULT 0x00000000
-
-/* HIF_SPI_INTR2 :: PCI_STATUS :: SPI_LR_IMPATIENT [02:02] */
-#define BCHP_HIF_SPI_INTR2_PCI_STATUS_SPI_LR_IMPATIENT_MASK 0x00000004
-#define BCHP_HIF_SPI_INTR2_PCI_STATUS_SPI_LR_IMPATIENT_SHIFT 2
-#define BCHP_HIF_SPI_INTR2_PCI_STATUS_SPI_LR_IMPATIENT_DEFAULT 0x00000000
-
-/* HIF_SPI_INTR2 :: PCI_STATUS :: SPI_LR_SESSION_ABORTED [01:01] */
-#define BCHP_HIF_SPI_INTR2_PCI_STATUS_SPI_LR_SESSION_ABORTED_MASK 0x00000002
-#define BCHP_HIF_SPI_INTR2_PCI_STATUS_SPI_LR_SESSION_ABORTED_SHIFT 1
-#define BCHP_HIF_SPI_INTR2_PCI_STATUS_SPI_LR_SESSION_ABORTED_DEFAULT 0x00000000
-
-/* HIF_SPI_INTR2 :: PCI_STATUS :: SPI_LR_FULLNESS_REACHED [00:00] */
-#define BCHP_HIF_SPI_INTR2_PCI_STATUS_SPI_LR_FULLNESS_REACHED_MASK 0x00000001
-#define BCHP_HIF_SPI_INTR2_PCI_STATUS_SPI_LR_FULLNESS_REACHED_SHIFT 0
-#define BCHP_HIF_SPI_INTR2_PCI_STATUS_SPI_LR_FULLNESS_REACHED_DEFAULT 0x00000000
-
-/***************************************************************************
- *PCI_SET - PCI interrupt Set Register
- ***************************************************************************/
-/* HIF_SPI_INTR2 :: PCI_SET :: reserved0 [31:07] */
-#define BCHP_HIF_SPI_INTR2_PCI_SET_reserved0_MASK 0xffffff80
-#define BCHP_HIF_SPI_INTR2_PCI_SET_reserved0_SHIFT 7
-
-/* HIF_SPI_INTR2 :: PCI_SET :: MSPI_HALTED [06:06] */
-#define BCHP_HIF_SPI_INTR2_PCI_SET_MSPI_HALTED_MASK 0x00000040
-#define BCHP_HIF_SPI_INTR2_PCI_SET_MSPI_HALTED_SHIFT 6
-#define BCHP_HIF_SPI_INTR2_PCI_SET_MSPI_HALTED_DEFAULT 0x00000000
-
-/* HIF_SPI_INTR2 :: PCI_SET :: MSPI_DONE [05:05] */
-#define BCHP_HIF_SPI_INTR2_PCI_SET_MSPI_DONE_MASK 0x00000020
-#define BCHP_HIF_SPI_INTR2_PCI_SET_MSPI_DONE_SHIFT 5
-#define BCHP_HIF_SPI_INTR2_PCI_SET_MSPI_DONE_DEFAULT 0x00000000
-
-/* HIF_SPI_INTR2 :: PCI_SET :: SPI_LR_OVERREAD [04:04] */
-#define BCHP_HIF_SPI_INTR2_PCI_SET_SPI_LR_OVERREAD_MASK 0x00000010
-#define BCHP_HIF_SPI_INTR2_PCI_SET_SPI_LR_OVERREAD_SHIFT 4
-#define BCHP_HIF_SPI_INTR2_PCI_SET_SPI_LR_OVERREAD_DEFAULT 0x00000000
-
-/* HIF_SPI_INTR2 :: PCI_SET :: SPI_LR_SESSION_DONE [03:03] */
-#define BCHP_HIF_SPI_INTR2_PCI_SET_SPI_LR_SESSION_DONE_MASK 0x00000008
-#define BCHP_HIF_SPI_INTR2_PCI_SET_SPI_LR_SESSION_DONE_SHIFT 3
-#define BCHP_HIF_SPI_INTR2_PCI_SET_SPI_LR_SESSION_DONE_DEFAULT 0x00000000
-
-/* HIF_SPI_INTR2 :: PCI_SET :: SPI_LR_IMPATIENT [02:02] */
-#define BCHP_HIF_SPI_INTR2_PCI_SET_SPI_LR_IMPATIENT_MASK 0x00000004
-#define BCHP_HIF_SPI_INTR2_PCI_SET_SPI_LR_IMPATIENT_SHIFT 2
-#define BCHP_HIF_SPI_INTR2_PCI_SET_SPI_LR_IMPATIENT_DEFAULT 0x00000000
-
-/* HIF_SPI_INTR2 :: PCI_SET :: SPI_LR_SESSION_ABORTED [01:01] */
-#define BCHP_HIF_SPI_INTR2_PCI_SET_SPI_LR_SESSION_ABORTED_MASK 0x00000002
-#define BCHP_HIF_SPI_INTR2_PCI_SET_SPI_LR_SESSION_ABORTED_SHIFT 1
-#define BCHP_HIF_SPI_INTR2_PCI_SET_SPI_LR_SESSION_ABORTED_DEFAULT 0x00000000
-
-/* HIF_SPI_INTR2 :: PCI_SET :: SPI_LR_FULLNESS_REACHED [00:00] */
-#define BCHP_HIF_SPI_INTR2_PCI_SET_SPI_LR_FULLNESS_REACHED_MASK 0x00000001
-#define BCHP_HIF_SPI_INTR2_PCI_SET_SPI_LR_FULLNESS_REACHED_SHIFT 0
-#define BCHP_HIF_SPI_INTR2_PCI_SET_SPI_LR_FULLNESS_REACHED_DEFAULT 0x00000000
-
-/***************************************************************************
- *PCI_CLEAR - PCI interrupt Clear Register
- ***************************************************************************/
-/* HIF_SPI_INTR2 :: PCI_CLEAR :: reserved0 [31:07] */
-#define BCHP_HIF_SPI_INTR2_PCI_CLEAR_reserved0_MASK 0xffffff80
-#define BCHP_HIF_SPI_INTR2_PCI_CLEAR_reserved0_SHIFT 7
-
-/* HIF_SPI_INTR2 :: PCI_CLEAR :: MSPI_HALTED [06:06] */
-#define BCHP_HIF_SPI_INTR2_PCI_CLEAR_MSPI_HALTED_MASK 0x00000040
-#define BCHP_HIF_SPI_INTR2_PCI_CLEAR_MSPI_HALTED_SHIFT 6
-#define BCHP_HIF_SPI_INTR2_PCI_CLEAR_MSPI_HALTED_DEFAULT 0x00000000
-
-/* HIF_SPI_INTR2 :: PCI_CLEAR :: MSPI_DONE [05:05] */
-#define BCHP_HIF_SPI_INTR2_PCI_CLEAR_MSPI_DONE_MASK 0x00000020
-#define BCHP_HIF_SPI_INTR2_PCI_CLEAR_MSPI_DONE_SHIFT 5
-#define BCHP_HIF_SPI_INTR2_PCI_CLEAR_MSPI_DONE_DEFAULT 0x00000000
-
-/* HIF_SPI_INTR2 :: PCI_CLEAR :: SPI_LR_OVERREAD [04:04] */
-#define BCHP_HIF_SPI_INTR2_PCI_CLEAR_SPI_LR_OVERREAD_MASK 0x00000010
-#define BCHP_HIF_SPI_INTR2_PCI_CLEAR_SPI_LR_OVERREAD_SHIFT 4
-#define BCHP_HIF_SPI_INTR2_PCI_CLEAR_SPI_LR_OVERREAD_DEFAULT 0x00000000
-
-/* HIF_SPI_INTR2 :: PCI_CLEAR :: SPI_LR_SESSION_DONE [03:03] */
-#define BCHP_HIF_SPI_INTR2_PCI_CLEAR_SPI_LR_SESSION_DONE_MASK 0x00000008
-#define BCHP_HIF_SPI_INTR2_PCI_CLEAR_SPI_LR_SESSION_DONE_SHIFT 3
-#define BCHP_HIF_SPI_INTR2_PCI_CLEAR_SPI_LR_SESSION_DONE_DEFAULT 0x00000000
-
-/* HIF_SPI_INTR2 :: PCI_CLEAR :: SPI_LR_IMPATIENT [02:02] */
-#define BCHP_HIF_SPI_INTR2_PCI_CLEAR_SPI_LR_IMPATIENT_MASK 0x00000004
-#define BCHP_HIF_SPI_INTR2_PCI_CLEAR_SPI_LR_IMPATIENT_SHIFT 2
-#define BCHP_HIF_SPI_INTR2_PCI_CLEAR_SPI_LR_IMPATIENT_DEFAULT 0x00000000
-
-/* HIF_SPI_INTR2 :: PCI_CLEAR :: SPI_LR_SESSION_ABORTED [01:01] */
-#define BCHP_HIF_SPI_INTR2_PCI_CLEAR_SPI_LR_SESSION_ABORTED_MASK 0x00000002
-#define BCHP_HIF_SPI_INTR2_PCI_CLEAR_SPI_LR_SESSION_ABORTED_SHIFT 1
-#define BCHP_HIF_SPI_INTR2_PCI_CLEAR_SPI_LR_SESSION_ABORTED_DEFAULT 0x00000000
-
-/* HIF_SPI_INTR2 :: PCI_CLEAR :: SPI_LR_FULLNESS_REACHED [00:00] */
-#define BCHP_HIF_SPI_INTR2_PCI_CLEAR_SPI_LR_FULLNESS_REACHED_MASK 0x00000001
-#define BCHP_HIF_SPI_INTR2_PCI_CLEAR_SPI_LR_FULLNESS_REACHED_SHIFT 0
-#define BCHP_HIF_SPI_INTR2_PCI_CLEAR_SPI_LR_FULLNESS_REACHED_DEFAULT 0x00000000
-
-/***************************************************************************
- *PCI_MASK_STATUS - PCI interrupt Mask Status Register
- ***************************************************************************/
-/* HIF_SPI_INTR2 :: PCI_MASK_STATUS :: reserved0 [31:07] */
-#define BCHP_HIF_SPI_INTR2_PCI_MASK_STATUS_reserved0_MASK 0xffffff80
-#define BCHP_HIF_SPI_INTR2_PCI_MASK_STATUS_reserved0_SHIFT 7
-
-/* HIF_SPI_INTR2 :: PCI_MASK_STATUS :: MSPI_HALTED [06:06] */
-#define BCHP_HIF_SPI_INTR2_PCI_MASK_STATUS_MSPI_HALTED_MASK 0x00000040
-#define BCHP_HIF_SPI_INTR2_PCI_MASK_STATUS_MSPI_HALTED_SHIFT 6
-#define BCHP_HIF_SPI_INTR2_PCI_MASK_STATUS_MSPI_HALTED_DEFAULT 0x00000000
-
-/* HIF_SPI_INTR2 :: PCI_MASK_STATUS :: MSPI_DONE [05:05] */
-#define BCHP_HIF_SPI_INTR2_PCI_MASK_STATUS_MSPI_DONE_MASK 0x00000020
-#define BCHP_HIF_SPI_INTR2_PCI_MASK_STATUS_MSPI_DONE_SHIFT 5
-#define BCHP_HIF_SPI_INTR2_PCI_MASK_STATUS_MSPI_DONE_DEFAULT 0x00000000
-
-/* HIF_SPI_INTR2 :: PCI_MASK_STATUS :: SPI_LR_OVERREAD [04:04] */
-#define BCHP_HIF_SPI_INTR2_PCI_MASK_STATUS_SPI_LR_OVERREAD_MASK 0x00000010
-#define BCHP_HIF_SPI_INTR2_PCI_MASK_STATUS_SPI_LR_OVERREAD_SHIFT 4
-#define BCHP_HIF_SPI_INTR2_PCI_MASK_STATUS_SPI_LR_OVERREAD_DEFAULT 0x00000000
-
-/* HIF_SPI_INTR2 :: PCI_MASK_STATUS :: SPI_LR_SESSION_DONE [03:03] */
-#define BCHP_HIF_SPI_INTR2_PCI_MASK_STATUS_SPI_LR_SESSION_DONE_MASK 0x00000008
-#define BCHP_HIF_SPI_INTR2_PCI_MASK_STATUS_SPI_LR_SESSION_DONE_SHIFT 3
-#define BCHP_HIF_SPI_INTR2_PCI_MASK_STATUS_SPI_LR_SESSION_DONE_DEFAULT 0x00000000
-
-/* HIF_SPI_INTR2 :: PCI_MASK_STATUS :: SPI_LR_IMPATIENT [02:02] */
-#define BCHP_HIF_SPI_INTR2_PCI_MASK_STATUS_SPI_LR_IMPATIENT_MASK 0x00000004
-#define BCHP_HIF_SPI_INTR2_PCI_MASK_STATUS_SPI_LR_IMPATIENT_SHIFT 2
-#define BCHP_HIF_SPI_INTR2_PCI_MASK_STATUS_SPI_LR_IMPATIENT_DEFAULT 0x00000000
-
-/* HIF_SPI_INTR2 :: PCI_MASK_STATUS :: SPI_LR_SESSION_ABORTED [01:01] */
-#define BCHP_HIF_SPI_INTR2_PCI_MASK_STATUS_SPI_LR_SESSION_ABORTED_MASK 0x00000002
-#define BCHP_HIF_SPI_INTR2_PCI_MASK_STATUS_SPI_LR_SESSION_ABORTED_SHIFT 1
-#define BCHP_HIF_SPI_INTR2_PCI_MASK_STATUS_SPI_LR_SESSION_ABORTED_DEFAULT 0x00000000
-
-/* HIF_SPI_INTR2 :: PCI_MASK_STATUS :: SPI_LR_FULLNESS_REACHED [00:00] */
-#define BCHP_HIF_SPI_INTR2_PCI_MASK_STATUS_SPI_LR_FULLNESS_REACHED_MASK 0x00000001
-#define BCHP_HIF_SPI_INTR2_PCI_MASK_STATUS_SPI_LR_FULLNESS_REACHED_SHIFT 0
-#define BCHP_HIF_SPI_INTR2_PCI_MASK_STATUS_SPI_LR_FULLNESS_REACHED_DEFAULT 0x00000000
-
-/***************************************************************************
- *PCI_MASK_SET - PCI interrupt Mask Set Register
- ***************************************************************************/
-/* HIF_SPI_INTR2 :: PCI_MASK_SET :: reserved0 [31:07] */
-#define BCHP_HIF_SPI_INTR2_PCI_MASK_SET_reserved0_MASK 0xffffff80
-#define BCHP_HIF_SPI_INTR2_PCI_MASK_SET_reserved0_SHIFT 7
-
-/* HIF_SPI_INTR2 :: PCI_MASK_SET :: MSPI_HALTED [06:06] */
-#define BCHP_HIF_SPI_INTR2_PCI_MASK_SET_MSPI_HALTED_MASK 0x00000040
-#define BCHP_HIF_SPI_INTR2_PCI_MASK_SET_MSPI_HALTED_SHIFT 6
-#define BCHP_HIF_SPI_INTR2_PCI_MASK_SET_MSPI_HALTED_DEFAULT 0x00000000
-
-/* HIF_SPI_INTR2 :: PCI_MASK_SET :: MSPI_DONE [05:05] */
-#define BCHP_HIF_SPI_INTR2_PCI_MASK_SET_MSPI_DONE_MASK 0x00000020
-#define BCHP_HIF_SPI_INTR2_PCI_MASK_SET_MSPI_DONE_SHIFT 5
-#define BCHP_HIF_SPI_INTR2_PCI_MASK_SET_MSPI_DONE_DEFAULT 0x00000000
-
-/* HIF_SPI_INTR2 :: PCI_MASK_SET :: SPI_LR_OVERREAD [04:04] */
-#define BCHP_HIF_SPI_INTR2_PCI_MASK_SET_SPI_LR_OVERREAD_MASK 0x00000010
-#define BCHP_HIF_SPI_INTR2_PCI_MASK_SET_SPI_LR_OVERREAD_SHIFT 4
-#define BCHP_HIF_SPI_INTR2_PCI_MASK_SET_SPI_LR_OVERREAD_DEFAULT 0x00000000
-
-/* HIF_SPI_INTR2 :: PCI_MASK_SET :: SPI_LR_SESSION_DONE [03:03] */
-#define BCHP_HIF_SPI_INTR2_PCI_MASK_SET_SPI_LR_SESSION_DONE_MASK 0x00000008
-#define BCHP_HIF_SPI_INTR2_PCI_MASK_SET_SPI_LR_SESSION_DONE_SHIFT 3
-#define BCHP_HIF_SPI_INTR2_PCI_MASK_SET_SPI_LR_SESSION_DONE_DEFAULT 0x00000000
-
-/* HIF_SPI_INTR2 :: PCI_MASK_SET :: SPI_LR_IMPATIENT [02:02] */
-#define BCHP_HIF_SPI_INTR2_PCI_MASK_SET_SPI_LR_IMPATIENT_MASK 0x00000004
-#define BCHP_HIF_SPI_INTR2_PCI_MASK_SET_SPI_LR_IMPATIENT_SHIFT 2
-#define BCHP_HIF_SPI_INTR2_PCI_MASK_SET_SPI_LR_IMPATIENT_DEFAULT 0x00000000
-
-/* HIF_SPI_INTR2 :: PCI_MASK_SET :: SPI_LR_SESSION_ABORTED [01:01] */
-#define BCHP_HIF_SPI_INTR2_PCI_MASK_SET_SPI_LR_SESSION_ABORTED_MASK 0x00000002
-#define BCHP_HIF_SPI_INTR2_PCI_MASK_SET_SPI_LR_SESSION_ABORTED_SHIFT 1
-#define BCHP_HIF_SPI_INTR2_PCI_MASK_SET_SPI_LR_SESSION_ABORTED_DEFAULT 0x00000000
-
-/* HIF_SPI_INTR2 :: PCI_MASK_SET :: SPI_LR_FULLNESS_REACHED [00:00] */
-#define BCHP_HIF_SPI_INTR2_PCI_MASK_SET_SPI_LR_FULLNESS_REACHED_MASK 0x00000001
-#define BCHP_HIF_SPI_INTR2_PCI_MASK_SET_SPI_LR_FULLNESS_REACHED_SHIFT 0
-#define BCHP_HIF_SPI_INTR2_PCI_MASK_SET_SPI_LR_FULLNESS_REACHED_DEFAULT 0x00000000
-
-/***************************************************************************
- *PCI_MASK_CLEAR - PCI interrupt Mask Clear Register
- ***************************************************************************/
-/* HIF_SPI_INTR2 :: PCI_MASK_CLEAR :: reserved0 [31:07] */
-#define BCHP_HIF_SPI_INTR2_PCI_MASK_CLEAR_reserved0_MASK 0xffffff80
-#define BCHP_HIF_SPI_INTR2_PCI_MASK_CLEAR_reserved0_SHIFT 7
-
-/* HIF_SPI_INTR2 :: PCI_MASK_CLEAR :: MSPI_HALTED [06:06] */
-#define BCHP_HIF_SPI_INTR2_PCI_MASK_CLEAR_MSPI_HALTED_MASK 0x00000040
-#define BCHP_HIF_SPI_INTR2_PCI_MASK_CLEAR_MSPI_HALTED_SHIFT 6
-#define BCHP_HIF_SPI_INTR2_PCI_MASK_CLEAR_MSPI_HALTED_DEFAULT 0x00000000
-
-/* HIF_SPI_INTR2 :: PCI_MASK_CLEAR :: MSPI_DONE [05:05] */
-#define BCHP_HIF_SPI_INTR2_PCI_MASK_CLEAR_MSPI_DONE_MASK 0x00000020
-#define BCHP_HIF_SPI_INTR2_PCI_MASK_CLEAR_MSPI_DONE_SHIFT 5
-#define BCHP_HIF_SPI_INTR2_PCI_MASK_CLEAR_MSPI_DONE_DEFAULT 0x00000000
-
-/* HIF_SPI_INTR2 :: PCI_MASK_CLEAR :: SPI_LR_OVERREAD [04:04] */
-#define BCHP_HIF_SPI_INTR2_PCI_MASK_CLEAR_SPI_LR_OVERREAD_MASK 0x00000010
-#define BCHP_HIF_SPI_INTR2_PCI_MASK_CLEAR_SPI_LR_OVERREAD_SHIFT 4
-#define BCHP_HIF_SPI_INTR2_PCI_MASK_CLEAR_SPI_LR_OVERREAD_DEFAULT 0x00000000
-
-/* HIF_SPI_INTR2 :: PCI_MASK_CLEAR :: SPI_LR_SESSION_DONE [03:03] */
-#define BCHP_HIF_SPI_INTR2_PCI_MASK_CLEAR_SPI_LR_SESSION_DONE_MASK 0x00000008
-#define BCHP_HIF_SPI_INTR2_PCI_MASK_CLEAR_SPI_LR_SESSION_DONE_SHIFT 3
-#define BCHP_HIF_SPI_INTR2_PCI_MASK_CLEAR_SPI_LR_SESSION_DONE_DEFAULT 0x00000000
-
-/* HIF_SPI_INTR2 :: PCI_MASK_CLEAR :: SPI_LR_IMPATIENT [02:02] */
-#define BCHP_HIF_SPI_INTR2_PCI_MASK_CLEAR_SPI_LR_IMPATIENT_MASK 0x00000004
-#define BCHP_HIF_SPI_INTR2_PCI_MASK_CLEAR_SPI_LR_IMPATIENT_SHIFT 2
-#define BCHP_HIF_SPI_INTR2_PCI_MASK_CLEAR_SPI_LR_IMPATIENT_DEFAULT 0x00000000
-
-/* HIF_SPI_INTR2 :: PCI_MASK_CLEAR :: SPI_LR_SESSION_ABORTED [01:01] */
-#define BCHP_HIF_SPI_INTR2_PCI_MASK_CLEAR_SPI_LR_SESSION_ABORTED_MASK 0x00000002
-#define BCHP_HIF_SPI_INTR2_PCI_MASK_CLEAR_SPI_LR_SESSION_ABORTED_SHIFT 1
-#define BCHP_HIF_SPI_INTR2_PCI_MASK_CLEAR_SPI_LR_SESSION_ABORTED_DEFAULT 0x00000000
-
-/* HIF_SPI_INTR2 :: PCI_MASK_CLEAR :: SPI_LR_FULLNESS_REACHED [00:00] */
-#define BCHP_HIF_SPI_INTR2_PCI_MASK_CLEAR_SPI_LR_FULLNESS_REACHED_MASK 0x00000001
-#define BCHP_HIF_SPI_INTR2_PCI_MASK_CLEAR_SPI_LR_FULLNESS_REACHED_SHIFT 0
-#define BCHP_HIF_SPI_INTR2_PCI_MASK_CLEAR_SPI_LR_FULLNESS_REACHED_DEFAULT 0x00000000
-
-#endif /* #ifndef BCHP_HIF_SPI_INTR2_H__ */
-
-/* End of File */
diff --git a/include/linux/brcmstb/7366b0/bchp_hif_top_ctrl.h b/include/linux/brcmstb/7366b0/bchp_hif_top_ctrl.h
deleted file mode 100644
index dc37255..0000000
--- a/include/linux/brcmstb/7366b0/bchp_hif_top_ctrl.h
+++ /dev/null
@@ -1,603 +0,0 @@
-/***************************************************************************
- * Copyright (c) 1999-2013, Broadcom Corporation
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
- *
- * Module Description:
- * DO NOT EDIT THIS FILE DIRECTLY
- *
- * This module was generated magically with RDB from a source description
- * file. You must edit the source file for changes to be made to this file.
- *
- *
- * Date: Generated on Sat Apr 20 03:07:43 2013
- * MD5 Checksum d41d8cd98f00b204e9800998ecf8427e
- *
- * Compiled with: RDB Utility combo_header.pl
- * RDB Parser 3.0
- * unknown unknown
- * Perl Interpreter 5.008008
- * Operating System linux
- *
- * Revision History:
- *
- * $brcm_Log: $
- *
- ***************************************************************************/
-
-#ifndef BCHP_HIF_TOP_CTRL_H__
-#define BCHP_HIF_TOP_CTRL_H__
-
-/***************************************************************************
- *HIF_TOP_CTRL - HIF Top Control Registers
- ***************************************************************************/
-#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL 0x00442000 /* External IRQ Active Level Control Register */
-#define BCHP_HIF_TOP_CTRL_SPI_DBG_SEL 0x00442004 /* SPI test port select register */
-#define BCHP_HIF_TOP_CTRL_PM_CTRL0 0x0044200c /* HIF Power Management Control0 Register */
-#define BCHP_HIF_TOP_CTRL_PM_CTRL1 0x00442010 /* HIF Power Management Control1 Register */
-#define BCHP_HIF_TOP_CTRL_PM_CTRL2 0x00442014 /* HIF Power Management Control Register:used to control SDIO_0 (CARD) */
-#define BCHP_HIF_TOP_CTRL_PM_CTRL3 0x00442018 /* HIF Power Management Control Register:used to control SDIO_1 (EMMC) */
-#define BCHP_HIF_TOP_CTRL_FLASH_TYPE 0x0044201c /* HIF Decoded Flash Type */
-#define BCHP_HIF_TOP_CTRL_CPU_MODE_CTRL 0x00442030 /* CPU MODE Control register (PUBLIC) */
-#define BCHP_HIF_TOP_CTRL_CPU_MODE_STATUS 0x00442034 /* CPU MODE Control status register (PUBLIC) */
-#define BCHP_HIF_TOP_CTRL_SCRATCH 0x0044203c /* HIF Scratch Register */
-
-/***************************************************************************
- *EXT_IRQ_LEVEL - External IRQ Active Level Control Register
- ***************************************************************************/
-/* HIF_TOP_CTRL :: EXT_IRQ_LEVEL :: reserved0 [31:08] */
-#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_reserved0_MASK 0xffffff00
-#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_reserved0_SHIFT 8
-
-/* HIF_TOP_CTRL :: EXT_IRQ_LEVEL :: ext_irq_7_level [07:07] */
-#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_7_level_MASK 0x00000080
-#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_7_level_SHIFT 7
-#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_7_level_DEFAULT 0x00000000
-#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_7_level_LOW 0
-#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_7_level_HIGH 1
-
-/* HIF_TOP_CTRL :: EXT_IRQ_LEVEL :: ext_irq_6_level [06:06] */
-#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_6_level_MASK 0x00000040
-#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_6_level_SHIFT 6
-#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_6_level_DEFAULT 0x00000000
-#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_6_level_LOW 0
-#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_6_level_HIGH 1
-
-/* HIF_TOP_CTRL :: EXT_IRQ_LEVEL :: ext_irq_5_level [05:05] */
-#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_5_level_MASK 0x00000020
-#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_5_level_SHIFT 5
-#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_5_level_DEFAULT 0x00000000
-#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_5_level_LOW 0
-#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_5_level_HIGH 1
-
-/* HIF_TOP_CTRL :: EXT_IRQ_LEVEL :: ext_irq_4_level [04:04] */
-#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_4_level_MASK 0x00000010
-#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_4_level_SHIFT 4
-#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_4_level_DEFAULT 0x00000000
-#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_4_level_LOW 0
-#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_4_level_HIGH 1
-
-/* HIF_TOP_CTRL :: EXT_IRQ_LEVEL :: ext_irq_3_level [03:03] */
-#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_3_level_MASK 0x00000008
-#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_3_level_SHIFT 3
-#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_3_level_DEFAULT 0x00000000
-#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_3_level_LOW 0
-#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_3_level_HIGH 1
-
-/* HIF_TOP_CTRL :: EXT_IRQ_LEVEL :: ext_irq_2_level [02:02] */
-#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_2_level_MASK 0x00000004
-#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_2_level_SHIFT 2
-#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_2_level_DEFAULT 0x00000000
-#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_2_level_LOW 0
-#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_2_level_HIGH 1
-
-/* HIF_TOP_CTRL :: EXT_IRQ_LEVEL :: ext_irq_1_level [01:01] */
-#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_1_level_MASK 0x00000002
-#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_1_level_SHIFT 1
-#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_1_level_DEFAULT 0x00000000
-#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_1_level_LOW 0
-#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_1_level_HIGH 1
-
-/* HIF_TOP_CTRL :: EXT_IRQ_LEVEL :: ext_irq_0_level [00:00] */
-#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_0_level_MASK 0x00000001
-#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_0_level_SHIFT 0
-#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_0_level_DEFAULT 0x00000000
-#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_0_level_LOW 0
-#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_0_level_HIGH 1
-
-/***************************************************************************
- *SPI_DBG_SEL - SPI test port select register
- ***************************************************************************/
-/* HIF_TOP_CTRL :: SPI_DBG_SEL :: reserved0 [31:03] */
-#define BCHP_HIF_TOP_CTRL_SPI_DBG_SEL_reserved0_MASK 0xfffffff8
-#define BCHP_HIF_TOP_CTRL_SPI_DBG_SEL_reserved0_SHIFT 3
-
-/* HIF_TOP_CTRL :: SPI_DBG_SEL :: DISABLE_MSPI_FLUSH [02:02] */
-#define BCHP_HIF_TOP_CTRL_SPI_DBG_SEL_DISABLE_MSPI_FLUSH_MASK 0x00000004
-#define BCHP_HIF_TOP_CTRL_SPI_DBG_SEL_DISABLE_MSPI_FLUSH_SHIFT 2
-#define BCHP_HIF_TOP_CTRL_SPI_DBG_SEL_DISABLE_MSPI_FLUSH_DEFAULT 0x00000000
-
-/* HIF_TOP_CTRL :: SPI_DBG_SEL :: SPI_RBUS_TIMER_EN [01:01] */
-#define BCHP_HIF_TOP_CTRL_SPI_DBG_SEL_SPI_RBUS_TIMER_EN_MASK 0x00000002
-#define BCHP_HIF_TOP_CTRL_SPI_DBG_SEL_SPI_RBUS_TIMER_EN_SHIFT 1
-#define BCHP_HIF_TOP_CTRL_SPI_DBG_SEL_SPI_RBUS_TIMER_EN_DEFAULT 0x00000000
-
-/* HIF_TOP_CTRL :: SPI_DBG_SEL :: reserved1 [00:00] */
-#define BCHP_HIF_TOP_CTRL_SPI_DBG_SEL_reserved1_MASK 0x00000001
-#define BCHP_HIF_TOP_CTRL_SPI_DBG_SEL_reserved1_SHIFT 0
-
-/***************************************************************************
- *PM_CTRL0 - HIF Power Management Control0 Register
- ***************************************************************************/
-/* HIF_TOP_CTRL :: PM_CTRL0 :: EBI_PM_IN_DRIVE_INACTIVE [31:30] */
-#define BCHP_HIF_TOP_CTRL_PM_CTRL0_EBI_PM_IN_DRIVE_INACTIVE_MASK 0xc0000000
-#define BCHP_HIF_TOP_CTRL_PM_CTRL0_EBI_PM_IN_DRIVE_INACTIVE_SHIFT 30
-#define BCHP_HIF_TOP_CTRL_PM_CTRL0_EBI_PM_IN_DRIVE_INACTIVE_DEFAULT 0x00000000
-#define BCHP_HIF_TOP_CTRL_PM_CTRL0_EBI_PM_IN_DRIVE_INACTIVE_FUNCTIONAL 0
-#define BCHP_HIF_TOP_CTRL_PM_CTRL0_EBI_PM_IN_DRIVE_INACTIVE_Low 1
-#define BCHP_HIF_TOP_CTRL_PM_CTRL0_EBI_PM_IN_DRIVE_INACTIVE_HIGH 2
-
-/* HIF_TOP_CTRL :: PM_CTRL0 :: NAND_DATA_PM_IN_DRIVE_INACTIVE [29:28] */
-#define BCHP_HIF_TOP_CTRL_PM_CTRL0_NAND_DATA_PM_IN_DRIVE_INACTIVE_MASK 0x30000000
-#define BCHP_HIF_TOP_CTRL_PM_CTRL0_NAND_DATA_PM_IN_DRIVE_INACTIVE_SHIFT 28
-#define BCHP_HIF_TOP_CTRL_PM_CTRL0_NAND_DATA_PM_IN_DRIVE_INACTIVE_DEFAULT 0x00000000
-#define BCHP_HIF_TOP_CTRL_PM_CTRL0_NAND_DATA_PM_IN_DRIVE_INACTIVE_FUNCTIONAL 0
-#define BCHP_HIF_TOP_CTRL_PM_CTRL0_NAND_DATA_PM_IN_DRIVE_INACTIVE_Low 1
-#define BCHP_HIF_TOP_CTRL_PM_CTRL0_NAND_DATA_PM_IN_DRIVE_INACTIVE_HIGH 2
-
-/* HIF_TOP_CTRL :: PM_CTRL0 :: NAND_CTRL_PM_IN_DRIVE_INACTIVE [27:26] */
-#define BCHP_HIF_TOP_CTRL_PM_CTRL0_NAND_CTRL_PM_IN_DRIVE_INACTIVE_MASK 0x0c000000
-#define BCHP_HIF_TOP_CTRL_PM_CTRL0_NAND_CTRL_PM_IN_DRIVE_INACTIVE_SHIFT 26
-#define BCHP_HIF_TOP_CTRL_PM_CTRL0_NAND_CTRL_PM_IN_DRIVE_INACTIVE_DEFAULT 0x00000000
-#define BCHP_HIF_TOP_CTRL_PM_CTRL0_NAND_CTRL_PM_IN_DRIVE_INACTIVE_FUNCTIONAL 0
-#define BCHP_HIF_TOP_CTRL_PM_CTRL0_NAND_CTRL_PM_IN_DRIVE_INACTIVE_NOT_USED 1
-#define BCHP_HIF_TOP_CTRL_PM_CTRL0_NAND_CTRL_PM_IN_DRIVE_INACTIVE_HIGH 2
-
-/* HIF_TOP_CTRL :: PM_CTRL0 :: EBI_DATA_PM_OUT_CTRL [25:24] */
-#define BCHP_HIF_TOP_CTRL_PM_CTRL0_EBI_DATA_PM_OUT_CTRL_MASK 0x03000000
-#define BCHP_HIF_TOP_CTRL_PM_CTRL0_EBI_DATA_PM_OUT_CTRL_SHIFT 24
-#define BCHP_HIF_TOP_CTRL_PM_CTRL0_EBI_DATA_PM_OUT_CTRL_DEFAULT 0x00000000
-#define BCHP_HIF_TOP_CTRL_PM_CTRL0_EBI_DATA_PM_OUT_CTRL_FUNCTIONAL 0
-#define BCHP_HIF_TOP_CTRL_PM_CTRL0_EBI_DATA_PM_OUT_CTRL_LOW 1
-#define BCHP_HIF_TOP_CTRL_PM_CTRL0_EBI_DATA_PM_OUT_CTRL_HIGH 2
-#define BCHP_HIF_TOP_CTRL_PM_CTRL0_EBI_DATA_PM_OUT_CTRL_Tristate 3
-
-/* HIF_TOP_CTRL :: PM_CTRL0 :: EBI_ADDR_PM_OUT_CTRL [23:22] */
-#define BCHP_HIF_TOP_CTRL_PM_CTRL0_EBI_ADDR_PM_OUT_CTRL_MASK 0x00c00000
-#define BCHP_HIF_TOP_CTRL_PM_CTRL0_EBI_ADDR_PM_OUT_CTRL_SHIFT 22
-#define BCHP_HIF_TOP_CTRL_PM_CTRL0_EBI_ADDR_PM_OUT_CTRL_DEFAULT 0x00000000
-#define BCHP_HIF_TOP_CTRL_PM_CTRL0_EBI_ADDR_PM_OUT_CTRL_FUNCTIONAL 0
-#define BCHP_HIF_TOP_CTRL_PM_CTRL0_EBI_ADDR_PM_OUT_CTRL_LOW 1
-#define BCHP_HIF_TOP_CTRL_PM_CTRL0_EBI_ADDR_PM_OUT_CTRL_HIGH 2
-#define BCHP_HIF_TOP_CTRL_PM_CTRL0_EBI_ADDR_PM_OUT_CTRL_Tristate 3
-
-/* HIF_TOP_CTRL :: PM_CTRL0 :: EBI_CTRL_PM_OUT_CTRL [21:20] */
-#define BCHP_HIF_TOP_CTRL_PM_CTRL0_EBI_CTRL_PM_OUT_CTRL_MASK 0x00300000
-#define BCHP_HIF_TOP_CTRL_PM_CTRL0_EBI_CTRL_PM_OUT_CTRL_SHIFT 20
-#define BCHP_HIF_TOP_CTRL_PM_CTRL0_EBI_CTRL_PM_OUT_CTRL_DEFAULT 0x00000000
-#define BCHP_HIF_TOP_CTRL_PM_CTRL0_EBI_CTRL_PM_OUT_CTRL_FUNCTIONAL 0
-#define BCHP_HIF_TOP_CTRL_PM_CTRL0_EBI_CTRL_PM_OUT_CTRL_LOW 1
-#define BCHP_HIF_TOP_CTRL_PM_CTRL0_EBI_CTRL_PM_OUT_CTRL_HIGH 2
-#define BCHP_HIF_TOP_CTRL_PM_CTRL0_EBI_CTRL_PM_OUT_CTRL_Tristate 3
-
-/* HIF_TOP_CTRL :: PM_CTRL0 :: NAND_DATA_PM_OUT_CTRL [19:18] */
-#define BCHP_HIF_TOP_CTRL_PM_CTRL0_NAND_DATA_PM_OUT_CTRL_MASK 0x000c0000
-#define BCHP_HIF_TOP_CTRL_PM_CTRL0_NAND_DATA_PM_OUT_CTRL_SHIFT 18
-#define BCHP_HIF_TOP_CTRL_PM_CTRL0_NAND_DATA_PM_OUT_CTRL_DEFAULT 0x00000000
-#define BCHP_HIF_TOP_CTRL_PM_CTRL0_NAND_DATA_PM_OUT_CTRL_FUNCTIONAL 0
-#define BCHP_HIF_TOP_CTRL_PM_CTRL0_NAND_DATA_PM_OUT_CTRL_LOW 1
-#define BCHP_HIF_TOP_CTRL_PM_CTRL0_NAND_DATA_PM_OUT_CTRL_HIGH 2
-#define BCHP_HIF_TOP_CTRL_PM_CTRL0_NAND_DATA_PM_OUT_CTRL_Tristate 3
-
-/* HIF_TOP_CTRL :: PM_CTRL0 :: NAND_CTRL_PM_OUT_CTRL [17:16] */
-#define BCHP_HIF_TOP_CTRL_PM_CTRL0_NAND_CTRL_PM_OUT_CTRL_MASK 0x00030000
-#define BCHP_HIF_TOP_CTRL_PM_CTRL0_NAND_CTRL_PM_OUT_CTRL_SHIFT 16
-#define BCHP_HIF_TOP_CTRL_PM_CTRL0_NAND_CTRL_PM_OUT_CTRL_DEFAULT 0x00000000
-#define BCHP_HIF_TOP_CTRL_PM_CTRL0_NAND_CTRL_PM_OUT_CTRL_FUNCTIONAL 0
-#define BCHP_HIF_TOP_CTRL_PM_CTRL0_NAND_CTRL_PM_OUT_CTRL_LOW 1
-#define BCHP_HIF_TOP_CTRL_PM_CTRL0_NAND_CTRL_PM_OUT_CTRL_HIGH 2
-#define BCHP_HIF_TOP_CTRL_PM_CTRL0_NAND_CTRL_PM_OUT_CTRL_Tristate 3
-
-/* HIF_TOP_CTRL :: PM_CTRL0 :: PM_OUT_CTRL_CS7 [15:14] */
-#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS7_MASK 0x0000c000
-#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS7_SHIFT 14
-#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS7_DEFAULT 0x00000000
-#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS7_FUNCTIONAL 0
-#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS7_LOW 1
-#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS7_HIGH 2
-#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS7_Tristate 3
-
-/* HIF_TOP_CTRL :: PM_CTRL0 :: PM_OUT_CTRL_CS6 [13:12] */
-#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS6_MASK 0x00003000
-#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS6_SHIFT 12
-#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS6_DEFAULT 0x00000000
-#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS6_FUNCTIONAL 0
-#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS6_LOW 1
-#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS6_HIGH 2
-#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS6_Tristate 3
-
-/* HIF_TOP_CTRL :: PM_CTRL0 :: PM_OUT_CTRL_CS5 [11:10] */
-#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS5_MASK 0x00000c00
-#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS5_SHIFT 10
-#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS5_DEFAULT 0x00000000
-#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS5_FUNCTIONAL 0
-#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS5_LOW 1
-#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS5_HIGH 2
-#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS5_Tristate 3
-
-/* HIF_TOP_CTRL :: PM_CTRL0 :: PM_OUT_CTRL_CS4 [09:08] */
-#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS4_MASK 0x00000300
-#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS4_SHIFT 8
-#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS4_DEFAULT 0x00000000
-#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS4_FUNCTIONAL 0
-#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS4_LOW 1
-#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS4_HIGH 2
-#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS4_Tristate 3
-
-/* HIF_TOP_CTRL :: PM_CTRL0 :: PM_OUT_CTRL_CS3 [07:06] */
-#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS3_MASK 0x000000c0
-#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS3_SHIFT 6
-#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS3_DEFAULT 0x00000000
-#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS3_FUNCTIONAL 0
-#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS3_LOW 1
-#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS3_HIGH 2
-#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS3_Tristate 3
-
-/* HIF_TOP_CTRL :: PM_CTRL0 :: PM_OUT_CTRL_CS2 [05:04] */
-#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS2_MASK 0x00000030
-#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS2_SHIFT 4
-#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS2_DEFAULT 0x00000000
-#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS2_FUNCTIONAL 0
-#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS2_LOW 1
-#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS2_HIGH 2
-#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS2_Tristate 3
-
-/* HIF_TOP_CTRL :: PM_CTRL0 :: PM_OUT_CTRL_CS1 [03:02] */
-#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS1_MASK 0x0000000c
-#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS1_SHIFT 2
-#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS1_DEFAULT 0x00000000
-#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS1_FUNCTIONAL 0
-#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS1_LOW 1
-#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS1_HIGH 2
-#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS1_Tristate 3
-
-/* HIF_TOP_CTRL :: PM_CTRL0 :: PM_OUT_CTRL_CS0 [01:00] */
-#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS0_MASK 0x00000003
-#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS0_SHIFT 0
-#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS0_DEFAULT 0x00000000
-#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS0_FUNCTIONAL 0
-#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS0_LOW 1
-#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS0_HIGH 2
-#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS0_Tristate 3
-
-/***************************************************************************
- *PM_CTRL1 - HIF Power Management Control1 Register
- ***************************************************************************/
-/* HIF_TOP_CTRL :: PM_CTRL1 :: reserved0 [31:12] */
-#define BCHP_HIF_TOP_CTRL_PM_CTRL1_reserved0_MASK 0xfffff000
-#define BCHP_HIF_TOP_CTRL_PM_CTRL1_reserved0_SHIFT 12
-
-/* HIF_TOP_CTRL :: PM_CTRL1 :: SPI_PM_IN_DRIVE_INACTIVE [11:10] */
-#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_PM_IN_DRIVE_INACTIVE_MASK 0x00000c00
-#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_PM_IN_DRIVE_INACTIVE_SHIFT 10
-#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_PM_IN_DRIVE_INACTIVE_DEFAULT 0x00000000
-#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_PM_IN_DRIVE_INACTIVE_FUNCTIONAL 0
-#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_PM_IN_DRIVE_INACTIVE_Low 1
-#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_PM_IN_DRIVE_INACTIVE_HIGH 2
-
-/* HIF_TOP_CTRL :: PM_CTRL1 :: SPI_WPB_PM_OUT_CTRL [09:08] */
-#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_WPB_PM_OUT_CTRL_MASK 0x00000300
-#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_WPB_PM_OUT_CTRL_SHIFT 8
-#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_WPB_PM_OUT_CTRL_DEFAULT 0x00000000
-#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_WPB_PM_OUT_CTRL_FUNCTIONAL 0
-#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_WPB_PM_OUT_CTRL_LOW 1
-#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_WPB_PM_OUT_CTRL_HIGH 2
-#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_WPB_PM_OUT_CTRL_Tristate 3
-
-/* HIF_TOP_CTRL :: PM_CTRL1 :: SPI_HOLDB_PM_OUT_CTRL [07:06] */
-#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_HOLDB_PM_OUT_CTRL_MASK 0x000000c0
-#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_HOLDB_PM_OUT_CTRL_SHIFT 6
-#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_HOLDB_PM_OUT_CTRL_DEFAULT 0x00000000
-#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_HOLDB_PM_OUT_CTRL_FUNCTIONAL 0
-#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_HOLDB_PM_OUT_CTRL_LOW 1
-#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_HOLDB_PM_OUT_CTRL_HIGH 2
-#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_HOLDB_PM_OUT_CTRL_Tristate 3
-
-/* HIF_TOP_CTRL :: PM_CTRL1 :: SPI_MISO_PM_OUT_CTRL [05:04] */
-#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_MISO_PM_OUT_CTRL_MASK 0x00000030
-#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_MISO_PM_OUT_CTRL_SHIFT 4
-#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_MISO_PM_OUT_CTRL_DEFAULT 0x00000000
-#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_MISO_PM_OUT_CTRL_FUNCTIONAL 0
-#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_MISO_PM_OUT_CTRL_LOW 1
-#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_MISO_PM_OUT_CTRL_HIGH 2
-#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_MISO_PM_OUT_CTRL_Tristate 3
-
-/* HIF_TOP_CTRL :: PM_CTRL1 :: SPI_MOSI_PM_OUT_CTRL [03:02] */
-#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_MOSI_PM_OUT_CTRL_MASK 0x0000000c
-#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_MOSI_PM_OUT_CTRL_SHIFT 2
-#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_MOSI_PM_OUT_CTRL_DEFAULT 0x00000000
-#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_MOSI_PM_OUT_CTRL_FUNCTIONAL 0
-#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_MOSI_PM_OUT_CTRL_LOW 1
-#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_MOSI_PM_OUT_CTRL_HIGH 2
-#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_MOSI_PM_OUT_CTRL_Tristate 3
-
-/* HIF_TOP_CTRL :: PM_CTRL1 :: SPI_CLK_PM_OUT_CTRL [01:00] */
-#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_CLK_PM_OUT_CTRL_MASK 0x00000003
-#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_CLK_PM_OUT_CTRL_SHIFT 0
-#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_CLK_PM_OUT_CTRL_DEFAULT 0x00000000
-#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_CLK_PM_OUT_CTRL_FUNCTIONAL 0
-#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_CLK_PM_OUT_CTRL_LOW 1
-#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_CLK_PM_OUT_CTRL_HIGH 2
-#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_CLK_PM_OUT_CTRL_Tristate 3
-
-/***************************************************************************
- *PM_CTRL2 - HIF Power Management Control Register:used to control SDIO_0 (CARD)
- ***************************************************************************/
-/* HIF_TOP_CTRL :: PM_CTRL2 :: reserved0 [31:24] */
-#define BCHP_HIF_TOP_CTRL_PM_CTRL2_reserved0_MASK 0xff000000
-#define BCHP_HIF_TOP_CTRL_PM_CTRL2_reserved0_SHIFT 24
-
-/* HIF_TOP_CTRL :: PM_CTRL2 :: SDIO_CARD_DETECT_PM_IN_DRIVE_INACTIVE [23:22] */
-#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_CARD_DETECT_PM_IN_DRIVE_INACTIVE_MASK 0x00c00000
-#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_CARD_DETECT_PM_IN_DRIVE_INACTIVE_SHIFT 22
-#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_CARD_DETECT_PM_IN_DRIVE_INACTIVE_DEFAULT 0x00000000
-#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_CARD_DETECT_PM_IN_DRIVE_INACTIVE_FUNCTIONAL 0
-#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_CARD_DETECT_PM_IN_DRIVE_INACTIVE_Low 1
-#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_CARD_DETECT_PM_IN_DRIVE_INACTIVE_HIGH 2
-
-/* HIF_TOP_CTRL :: PM_CTRL2 :: SDIO_WRITE_PROTECT_PM_IN_DRIVE_INACTIVE [21:20] */
-#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_WRITE_PROTECT_PM_IN_DRIVE_INACTIVE_MASK 0x00300000
-#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_WRITE_PROTECT_PM_IN_DRIVE_INACTIVE_SHIFT 20
-#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_WRITE_PROTECT_PM_IN_DRIVE_INACTIVE_DEFAULT 0x00000000
-#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_WRITE_PROTECT_PM_IN_DRIVE_INACTIVE_FUNCTIONAL 0
-#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_WRITE_PROTECT_PM_IN_DRIVE_INACTIVE_Low 1
-#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_WRITE_PROTECT_PM_IN_DRIVE_INACTIVE_HIGH 2
-
-/* HIF_TOP_CTRL :: PM_CTRL2 :: SDIO_DATA_PM_IN_DRIVE_INACTIVE [19:18] */
-#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_DATA_PM_IN_DRIVE_INACTIVE_MASK 0x000c0000
-#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_DATA_PM_IN_DRIVE_INACTIVE_SHIFT 18
-#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_DATA_PM_IN_DRIVE_INACTIVE_DEFAULT 0x00000000
-#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_DATA_PM_IN_DRIVE_INACTIVE_FUNCTIONAL 0
-#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_DATA_PM_IN_DRIVE_INACTIVE_Low 1
-#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_DATA_PM_IN_DRIVE_INACTIVE_HIGH 2
-
-/* HIF_TOP_CTRL :: PM_CTRL2 :: SDIO_CMD_PM_IN_DRIVE_INACTIVE [17:16] */
-#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_CMD_PM_IN_DRIVE_INACTIVE_MASK 0x00030000
-#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_CMD_PM_IN_DRIVE_INACTIVE_SHIFT 16
-#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_CMD_PM_IN_DRIVE_INACTIVE_DEFAULT 0x00000000
-#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_CMD_PM_IN_DRIVE_INACTIVE_FUNCTIONAL 0
-#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_CMD_PM_IN_DRIVE_INACTIVE_Low 1
-#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_CMD_PM_IN_DRIVE_INACTIVE_HIGH 2
-
-/* HIF_TOP_CTRL :: PM_CTRL2 :: reserved1 [15:12] */
-#define BCHP_HIF_TOP_CTRL_PM_CTRL2_reserved1_MASK 0x0000f000
-#define BCHP_HIF_TOP_CTRL_PM_CTRL2_reserved1_SHIFT 12
-
-/* HIF_TOP_CTRL :: PM_CTRL2 :: SDIO_VOLTAGE_PM_OUT_CTRL [11:10] */
-#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_VOLTAGE_PM_OUT_CTRL_MASK 0x00000c00
-#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_VOLTAGE_PM_OUT_CTRL_SHIFT 10
-#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_VOLTAGE_PM_OUT_CTRL_DEFAULT 0x00000000
-#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_VOLTAGE_PM_OUT_CTRL_FUNCTIONAL 0
-#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_VOLTAGE_PM_OUT_CTRL_LOW 1
-#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_VOLTAGE_PM_OUT_CTRL_HIGH 2
-#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_VOLTAGE_PM_OUT_CTRL_Tristate 3
-
-/* HIF_TOP_CTRL :: PM_CTRL2 :: SDIO_POWER_PM_OUT_CTRL [09:08] */
-#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_POWER_PM_OUT_CTRL_MASK 0x00000300
-#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_POWER_PM_OUT_CTRL_SHIFT 8
-#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_POWER_PM_OUT_CTRL_DEFAULT 0x00000000
-#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_POWER_PM_OUT_CTRL_FUNCTIONAL 0
-#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_POWER_PM_OUT_CTRL_LOW 1
-#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_POWER_PM_OUT_CTRL_HIGH 2
-#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_POWER_PM_OUT_CTRL_Tristate 3
-
-/* HIF_TOP_CTRL :: PM_CTRL2 :: SDIO_LED_PM_OUT_CTRL [07:06] */
-#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_LED_PM_OUT_CTRL_MASK 0x000000c0
-#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_LED_PM_OUT_CTRL_SHIFT 6
-#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_LED_PM_OUT_CTRL_DEFAULT 0x00000000
-#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_LED_PM_OUT_CTRL_FUNCTIONAL 0
-#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_LED_PM_OUT_CTRL_LOW 1
-#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_LED_PM_OUT_CTRL_HIGH 2
-#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_LED_PM_OUT_CTRL_Tristate 3
-
-/* HIF_TOP_CTRL :: PM_CTRL2 :: SDIO_DATA_PM_OUT_CTRL [05:04] */
-#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_DATA_PM_OUT_CTRL_MASK 0x00000030
-#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_DATA_PM_OUT_CTRL_SHIFT 4
-#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_DATA_PM_OUT_CTRL_DEFAULT 0x00000000
-#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_DATA_PM_OUT_CTRL_FUNCTIONAL 0
-#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_DATA_PM_OUT_CTRL_LOW 1
-#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_DATA_PM_OUT_CTRL_HIGH 2
-#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_DATA_PM_OUT_CTRL_Tristate 3
-
-/* HIF_TOP_CTRL :: PM_CTRL2 :: SDIO_CMD_PM_OUT_CTRL [03:02] */
-#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_CMD_PM_OUT_CTRL_MASK 0x0000000c
-#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_CMD_PM_OUT_CTRL_SHIFT 2
-#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_CMD_PM_OUT_CTRL_DEFAULT 0x00000000
-#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_CMD_PM_OUT_CTRL_FUNCTIONAL 0
-#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_CMD_PM_OUT_CTRL_LOW 1
-#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_CMD_PM_OUT_CTRL_HIGH 2
-#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_CMD_PM_OUT_CTRL_Tristate 3
-
-/* HIF_TOP_CTRL :: PM_CTRL2 :: SDIO_CLK_PM_OUT_CTRL [01:00] */
-#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_CLK_PM_OUT_CTRL_MASK 0x00000003
-#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_CLK_PM_OUT_CTRL_SHIFT 0
-#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_CLK_PM_OUT_CTRL_DEFAULT 0x00000000
-#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_CLK_PM_OUT_CTRL_FUNCTIONAL 0
-#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_CLK_PM_OUT_CTRL_LOW 1
-#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_CLK_PM_OUT_CTRL_HIGH 2
-#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_CLK_PM_OUT_CTRL_Tristate 3
-
-/***************************************************************************
- *PM_CTRL3 - HIF Power Management Control Register:used to control SDIO_1 (EMMC)
- ***************************************************************************/
-/* HIF_TOP_CTRL :: PM_CTRL3 :: reserved0 [31:24] */
-#define BCHP_HIF_TOP_CTRL_PM_CTRL3_reserved0_MASK 0xff000000
-#define BCHP_HIF_TOP_CTRL_PM_CTRL3_reserved0_SHIFT 24
-
-/* HIF_TOP_CTRL :: PM_CTRL3 :: SDIO_CARD_DETECT_PM_IN_DRIVE_INACTIVE [23:22] */
-#define BCHP_HIF_TOP_CTRL_PM_CTRL3_SDIO_CARD_DETECT_PM_IN_DRIVE_INACTIVE_MASK 0x00c00000
-#define BCHP_HIF_TOP_CTRL_PM_CTRL3_SDIO_CARD_DETECT_PM_IN_DRIVE_INACTIVE_SHIFT 22
-#define BCHP_HIF_TOP_CTRL_PM_CTRL3_SDIO_CARD_DETECT_PM_IN_DRIVE_INACTIVE_DEFAULT 0x00000000
-#define BCHP_HIF_TOP_CTRL_PM_CTRL3_SDIO_CARD_DETECT_PM_IN_DRIVE_INACTIVE_FUNCTIONAL 0
-#define BCHP_HIF_TOP_CTRL_PM_CTRL3_SDIO_CARD_DETECT_PM_IN_DRIVE_INACTIVE_Low 1
-#define BCHP_HIF_TOP_CTRL_PM_CTRL3_SDIO_CARD_DETECT_PM_IN_DRIVE_INACTIVE_HIGH 2
-
-/* HIF_TOP_CTRL :: PM_CTRL3 :: SDIO_WRITE_PROTECT_PM_IN_DRIVE_INACTIVE [21:20] */
-#define BCHP_HIF_TOP_CTRL_PM_CTRL3_SDIO_WRITE_PROTECT_PM_IN_DRIVE_INACTIVE_MASK 0x00300000
-#define BCHP_HIF_TOP_CTRL_PM_CTRL3_SDIO_WRITE_PROTECT_PM_IN_DRIVE_INACTIVE_SHIFT 20
-#define BCHP_HIF_TOP_CTRL_PM_CTRL3_SDIO_WRITE_PROTECT_PM_IN_DRIVE_INACTIVE_DEFAULT 0x00000000
-#define BCHP_HIF_TOP_CTRL_PM_CTRL3_SDIO_WRITE_PROTECT_PM_IN_DRIVE_INACTIVE_FUNCTIONAL 0
-#define BCHP_HIF_TOP_CTRL_PM_CTRL3_SDIO_WRITE_PROTECT_PM_IN_DRIVE_INACTIVE_Low 1
-#define BCHP_HIF_TOP_CTRL_PM_CTRL3_SDIO_WRITE_PROTECT_PM_IN_DRIVE_INACTIVE_HIGH 2
-
-/* HIF_TOP_CTRL :: PM_CTRL3 :: SDIO_DATA_PM_IN_DRIVE_INACTIVE [19:18] */
-#define BCHP_HIF_TOP_CTRL_PM_CTRL3_SDIO_DATA_PM_IN_DRIVE_INACTIVE_MASK 0x000c0000
-#define BCHP_HIF_TOP_CTRL_PM_CTRL3_SDIO_DATA_PM_IN_DRIVE_INACTIVE_SHIFT 18
-#define BCHP_HIF_TOP_CTRL_PM_CTRL3_SDIO_DATA_PM_IN_DRIVE_INACTIVE_DEFAULT 0x00000000
-#define BCHP_HIF_TOP_CTRL_PM_CTRL3_SDIO_DATA_PM_IN_DRIVE_INACTIVE_FUNCTIONAL 0
-#define BCHP_HIF_TOP_CTRL_PM_CTRL3_SDIO_DATA_PM_IN_DRIVE_INACTIVE_Low 1
-#define BCHP_HIF_TOP_CTRL_PM_CTRL3_SDIO_DATA_PM_IN_DRIVE_INACTIVE_HIGH 2
-
-/* HIF_TOP_CTRL :: PM_CTRL3 :: SDIO_CMD_PM_IN_DRIVE_INACTIVE [17:16] */
-#define BCHP_HIF_TOP_CTRL_PM_CTRL3_SDIO_CMD_PM_IN_DRIVE_INACTIVE_MASK 0x00030000
-#define BCHP_HIF_TOP_CTRL_PM_CTRL3_SDIO_CMD_PM_IN_DRIVE_INACTIVE_SHIFT 16
-#define BCHP_HIF_TOP_CTRL_PM_CTRL3_SDIO_CMD_PM_IN_DRIVE_INACTIVE_DEFAULT 0x00000000
-#define BCHP_HIF_TOP_CTRL_PM_CTRL3_SDIO_CMD_PM_IN_DRIVE_INACTIVE_FUNCTIONAL 0
-#define BCHP_HIF_TOP_CTRL_PM_CTRL3_SDIO_CMD_PM_IN_DRIVE_INACTIVE_Low 1
-#define BCHP_HIF_TOP_CTRL_PM_CTRL3_SDIO_CMD_PM_IN_DRIVE_INACTIVE_HIGH 2
-
-/* HIF_TOP_CTRL :: PM_CTRL3 :: reserved1 [15:12] */
-#define BCHP_HIF_TOP_CTRL_PM_CTRL3_reserved1_MASK 0x0000f000
-#define BCHP_HIF_TOP_CTRL_PM_CTRL3_reserved1_SHIFT 12
-
-/* HIF_TOP_CTRL :: PM_CTRL3 :: SDIO_VOLTAGE_PM_OUT_CTRL [11:10] */
-#define BCHP_HIF_TOP_CTRL_PM_CTRL3_SDIO_VOLTAGE_PM_OUT_CTRL_MASK 0x00000c00
-#define BCHP_HIF_TOP_CTRL_PM_CTRL3_SDIO_VOLTAGE_PM_OUT_CTRL_SHIFT 10
-#define BCHP_HIF_TOP_CTRL_PM_CTRL3_SDIO_VOLTAGE_PM_OUT_CTRL_DEFAULT 0x00000000
-#define BCHP_HIF_TOP_CTRL_PM_CTRL3_SDIO_VOLTAGE_PM_OUT_CTRL_FUNCTIONAL 0
-#define BCHP_HIF_TOP_CTRL_PM_CTRL3_SDIO_VOLTAGE_PM_OUT_CTRL_LOW 1
-#define BCHP_HIF_TOP_CTRL_PM_CTRL3_SDIO_VOLTAGE_PM_OUT_CTRL_HIGH 2
-#define BCHP_HIF_TOP_CTRL_PM_CTRL3_SDIO_VOLTAGE_PM_OUT_CTRL_Tristate 3
-
-/* HIF_TOP_CTRL :: PM_CTRL3 :: SDIO_POWER_PM_OUT_CTRL [09:08] */
-#define BCHP_HIF_TOP_CTRL_PM_CTRL3_SDIO_POWER_PM_OUT_CTRL_MASK 0x00000300
-#define BCHP_HIF_TOP_CTRL_PM_CTRL3_SDIO_POWER_PM_OUT_CTRL_SHIFT 8
-#define BCHP_HIF_TOP_CTRL_PM_CTRL3_SDIO_POWER_PM_OUT_CTRL_DEFAULT 0x00000000
-#define BCHP_HIF_TOP_CTRL_PM_CTRL3_SDIO_POWER_PM_OUT_CTRL_FUNCTIONAL 0
-#define BCHP_HIF_TOP_CTRL_PM_CTRL3_SDIO_POWER_PM_OUT_CTRL_LOW 1
-#define BCHP_HIF_TOP_CTRL_PM_CTRL3_SDIO_POWER_PM_OUT_CTRL_HIGH 2
-#define BCHP_HIF_TOP_CTRL_PM_CTRL3_SDIO_POWER_PM_OUT_CTRL_Tristate 3
-
-/* HIF_TOP_CTRL :: PM_CTRL3 :: SDIO_LED_PM_OUT_CTRL [07:06] */
-#define BCHP_HIF_TOP_CTRL_PM_CTRL3_SDIO_LED_PM_OUT_CTRL_MASK 0x000000c0
-#define BCHP_HIF_TOP_CTRL_PM_CTRL3_SDIO_LED_PM_OUT_CTRL_SHIFT 6
-#define BCHP_HIF_TOP_CTRL_PM_CTRL3_SDIO_LED_PM_OUT_CTRL_DEFAULT 0x00000000
-#define BCHP_HIF_TOP_CTRL_PM_CTRL3_SDIO_LED_PM_OUT_CTRL_FUNCTIONAL 0
-#define BCHP_HIF_TOP_CTRL_PM_CTRL3_SDIO_LED_PM_OUT_CTRL_LOW 1
-#define BCHP_HIF_TOP_CTRL_PM_CTRL3_SDIO_LED_PM_OUT_CTRL_HIGH 2
-#define BCHP_HIF_TOP_CTRL_PM_CTRL3_SDIO_LED_PM_OUT_CTRL_Tristate 3
-
-/* HIF_TOP_CTRL :: PM_CTRL3 :: SDIO_DATA_PM_OUT_CTRL [05:04] */
-#define BCHP_HIF_TOP_CTRL_PM_CTRL3_SDIO_DATA_PM_OUT_CTRL_MASK 0x00000030
-#define BCHP_HIF_TOP_CTRL_PM_CTRL3_SDIO_DATA_PM_OUT_CTRL_SHIFT 4
-#define BCHP_HIF_TOP_CTRL_PM_CTRL3_SDIO_DATA_PM_OUT_CTRL_DEFAULT 0x00000000
-#define BCHP_HIF_TOP_CTRL_PM_CTRL3_SDIO_DATA_PM_OUT_CTRL_FUNCTIONAL 0
-#define BCHP_HIF_TOP_CTRL_PM_CTRL3_SDIO_DATA_PM_OUT_CTRL_LOW 1
-#define BCHP_HIF_TOP_CTRL_PM_CTRL3_SDIO_DATA_PM_OUT_CTRL_HIGH 2
-#define BCHP_HIF_TOP_CTRL_PM_CTRL3_SDIO_DATA_PM_OUT_CTRL_Tristate 3
-
-/* HIF_TOP_CTRL :: PM_CTRL3 :: SDIO_CMD_PM_OUT_CTRL [03:02] */
-#define BCHP_HIF_TOP_CTRL_PM_CTRL3_SDIO_CMD_PM_OUT_CTRL_MASK 0x0000000c
-#define BCHP_HIF_TOP_CTRL_PM_CTRL3_SDIO_CMD_PM_OUT_CTRL_SHIFT 2
-#define BCHP_HIF_TOP_CTRL_PM_CTRL3_SDIO_CMD_PM_OUT_CTRL_DEFAULT 0x00000000
-#define BCHP_HIF_TOP_CTRL_PM_CTRL3_SDIO_CMD_PM_OUT_CTRL_FUNCTIONAL 0
-#define BCHP_HIF_TOP_CTRL_PM_CTRL3_SDIO_CMD_PM_OUT_CTRL_LOW 1
-#define BCHP_HIF_TOP_CTRL_PM_CTRL3_SDIO_CMD_PM_OUT_CTRL_HIGH 2
-#define BCHP_HIF_TOP_CTRL_PM_CTRL3_SDIO_CMD_PM_OUT_CTRL_Tristate 3
-
-/* HIF_TOP_CTRL :: PM_CTRL3 :: SDIO_CLK_PM_OUT_CTRL [01:00] */
-#define BCHP_HIF_TOP_CTRL_PM_CTRL3_SDIO_CLK_PM_OUT_CTRL_MASK 0x00000003
-#define BCHP_HIF_TOP_CTRL_PM_CTRL3_SDIO_CLK_PM_OUT_CTRL_SHIFT 0
-#define BCHP_HIF_TOP_CTRL_PM_CTRL3_SDIO_CLK_PM_OUT_CTRL_DEFAULT 0x00000000
-#define BCHP_HIF_TOP_CTRL_PM_CTRL3_SDIO_CLK_PM_OUT_CTRL_FUNCTIONAL 0
-#define BCHP_HIF_TOP_CTRL_PM_CTRL3_SDIO_CLK_PM_OUT_CTRL_LOW 1
-#define BCHP_HIF_TOP_CTRL_PM_CTRL3_SDIO_CLK_PM_OUT_CTRL_HIGH 2
-#define BCHP_HIF_TOP_CTRL_PM_CTRL3_SDIO_CLK_PM_OUT_CTRL_Tristate 3
-
-/***************************************************************************
- *FLASH_TYPE - HIF Decoded Flash Type
- ***************************************************************************/
-/* HIF_TOP_CTRL :: FLASH_TYPE :: reserved0 [31:03] */
-#define BCHP_HIF_TOP_CTRL_FLASH_TYPE_reserved0_MASK 0xfffffff8
-#define BCHP_HIF_TOP_CTRL_FLASH_TYPE_reserved0_SHIFT 3
-
-/* HIF_TOP_CTRL :: FLASH_TYPE :: InvalidStrap [02:02] */
-#define BCHP_HIF_TOP_CTRL_FLASH_TYPE_InvalidStrap_MASK 0x00000004
-#define BCHP_HIF_TOP_CTRL_FLASH_TYPE_InvalidStrap_SHIFT 2
-#define BCHP_HIF_TOP_CTRL_FLASH_TYPE_InvalidStrap_DEFAULT 0x00000000
-
-/* HIF_TOP_CTRL :: FLASH_TYPE :: FLASH_TYPE [01:00] */
-#define BCHP_HIF_TOP_CTRL_FLASH_TYPE_FLASH_TYPE_MASK 0x00000003
-#define BCHP_HIF_TOP_CTRL_FLASH_TYPE_FLASH_TYPE_SHIFT 0
-#define BCHP_HIF_TOP_CTRL_FLASH_TYPE_FLASH_TYPE_ParallelNOR 0
-#define BCHP_HIF_TOP_CTRL_FLASH_TYPE_FLASH_TYPE_Nand 1
-#define BCHP_HIF_TOP_CTRL_FLASH_TYPE_FLASH_TYPE_SerialNOR 2
-#define BCHP_HIF_TOP_CTRL_FLASH_TYPE_FLASH_TYPE_eMMC 3
-
-/***************************************************************************
- *CPU_MODE_CTRL - CPU MODE Control register (PUBLIC)
- ***************************************************************************/
-/* HIF_TOP_CTRL :: CPU_MODE_CTRL :: reserved0 [31:02] */
-#define BCHP_HIF_TOP_CTRL_CPU_MODE_CTRL_reserved0_MASK 0xfffffffc
-#define BCHP_HIF_TOP_CTRL_CPU_MODE_CTRL_reserved0_SHIFT 2
-
-/* HIF_TOP_CTRL :: CPU_MODE_CTRL :: CPU_MODE [01:00] */
-#define BCHP_HIF_TOP_CTRL_CPU_MODE_CTRL_CPU_MODE_MASK 0x00000003
-#define BCHP_HIF_TOP_CTRL_CPU_MODE_CTRL_CPU_MODE_SHIFT 0
-#define BCHP_HIF_TOP_CTRL_CPU_MODE_CTRL_CPU_MODE_DEFAULT 0x00000000
-#define BCHP_HIF_TOP_CTRL_CPU_MODE_CTRL_CPU_MODE_FullSMP 0
-#define BCHP_HIF_TOP_CTRL_CPU_MODE_CTRL_CPU_MODE_Sandbox_1_1 1
-#define BCHP_HIF_TOP_CTRL_CPU_MODE_CTRL_CPU_MODE_Sandbox_1_1_reserved2 2
-#define BCHP_HIF_TOP_CTRL_CPU_MODE_CTRL_CPU_MODE_Sandbox_1_1_reserved3 3
-
-/***************************************************************************
- *CPU_MODE_STATUS - CPU MODE Control status register (PUBLIC)
- ***************************************************************************/
-/* HIF_TOP_CTRL :: CPU_MODE_STATUS :: reserved0 [31:08] */
-#define BCHP_HIF_TOP_CTRL_CPU_MODE_STATUS_reserved0_MASK 0xffffff00
-#define BCHP_HIF_TOP_CTRL_CPU_MODE_STATUS_reserved0_SHIFT 8
-
-/* HIF_TOP_CTRL :: CPU_MODE_STATUS :: SPARE_STATUS [07:05] */
-#define BCHP_HIF_TOP_CTRL_CPU_MODE_STATUS_SPARE_STATUS_MASK 0x000000e0
-#define BCHP_HIF_TOP_CTRL_CPU_MODE_STATUS_SPARE_STATUS_SHIFT 5
-
-/* HIF_TOP_CTRL :: CPU_MODE_STATUS :: CPU_MODE_STATUS [04:03] */
-#define BCHP_HIF_TOP_CTRL_CPU_MODE_STATUS_CPU_MODE_STATUS_MASK 0x00000018
-#define BCHP_HIF_TOP_CTRL_CPU_MODE_STATUS_CPU_MODE_STATUS_SHIFT 3
-
-/* HIF_TOP_CTRL :: CPU_MODE_STATUS :: CPU_MODE_OTP [02:00] */
-#define BCHP_HIF_TOP_CTRL_CPU_MODE_STATUS_CPU_MODE_OTP_MASK 0x00000007
-#define BCHP_HIF_TOP_CTRL_CPU_MODE_STATUS_CPU_MODE_OTP_SHIFT 0
-
-/***************************************************************************
- *SCRATCH - HIF Scratch Register
- ***************************************************************************/
-/* HIF_TOP_CTRL :: SCRATCH :: SCRATCH_BITS [31:00] */
-#define BCHP_HIF_TOP_CTRL_SCRATCH_SCRATCH_BITS_MASK 0xffffffff
-#define BCHP_HIF_TOP_CTRL_SCRATCH_SCRATCH_BITS_SHIFT 0
-#define BCHP_HIF_TOP_CTRL_SCRATCH_SCRATCH_BITS_DEFAULT 0x00000000
-
-#endif /* #ifndef BCHP_HIF_TOP_CTRL_H__ */
-
-/* End of File */
diff --git a/include/linux/brcmstb/7366b0/bchp_irq0.h b/include/linux/brcmstb/7366b0/bchp_irq0.h
deleted file mode 100644
index cffff7a..0000000
--- a/include/linux/brcmstb/7366b0/bchp_irq0.h
+++ /dev/null
@@ -1,196 +0,0 @@
-/***************************************************************************
- * Copyright (c) 1999-2014, Broadcom Corporation
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
- *
- * Module Description:
- * DO NOT EDIT THIS FILE DIRECTLY
- *
- * This module was generated magically with RDB from a source description
- * file. You must edit the source file for changes to be made to this file.
- *
- *
- * Date: Generated on Thu Apr 24 03:08:56 2014
- * Full Compile MD5 Checksum 1af2c2cf28828ece5496e1312aac0166
- * (minus title and desc)
- * MD5 Checksum 3203ffce85e3fc9a10f84123e54057b0
- *
- * Compiled with: RDB Utility combo_header.pl
- * RDB Parser 3.0
- * unknown unknown
- * Perl Interpreter 5.008008
- * Operating System linux
- *
- * Revision History:
- *
- * $brcm_Log: $
- *
- ***************************************************************************/
-
-#ifndef BCHP_IRQ0_H__
-#define BCHP_IRQ0_H__
-
-/***************************************************************************
- *IRQ0 - Level 2 CPU Interrupt Enable/Status
- ***************************************************************************/
-#define BCHP_IRQ0_IRQEN 0x0040a580 /* Interrupt Enable */
-#define BCHP_IRQ0_IRQSTAT 0x0040a584 /* Interrupt Status */
-
-/***************************************************************************
- *IRQEN - Interrupt Enable
- ***************************************************************************/
-/* IRQ0 :: IRQEN :: reserved0 [31:13] */
-#define BCHP_IRQ0_IRQEN_reserved0_MASK 0xffffe000
-#define BCHP_IRQ0_IRQEN_reserved0_SHIFT 13
-
-/* IRQ0 :: IRQEN :: irb_irqen [12:12] */
-#define BCHP_IRQ0_IRQEN_irb_irqen_MASK 0x00001000
-#define BCHP_IRQ0_IRQEN_irb_irqen_SHIFT 12
-#define BCHP_IRQ0_IRQEN_irb_irqen_DEFAULT 0x00000000
-
-/* IRQ0 :: IRQEN :: gio_irqen [11:11] */
-#define BCHP_IRQ0_IRQEN_gio_irqen_MASK 0x00000800
-#define BCHP_IRQ0_IRQEN_gio_irqen_SHIFT 11
-#define BCHP_IRQ0_IRQEN_gio_irqen_DEFAULT 0x00000000
-
-/* IRQ0 :: IRQEN :: iicg_irqen [10:10] */
-#define BCHP_IRQ0_IRQEN_iicg_irqen_MASK 0x00000400
-#define BCHP_IRQ0_IRQEN_iicg_irqen_SHIFT 10
-#define BCHP_IRQ0_IRQEN_iicg_irqen_DEFAULT 0x00000000
-
-/* IRQ0 :: IRQEN :: iicf_irqen [09:09] */
-#define BCHP_IRQ0_IRQEN_iicf_irqen_MASK 0x00000200
-#define BCHP_IRQ0_IRQEN_iicf_irqen_SHIFT 9
-#define BCHP_IRQ0_IRQEN_iicf_irqen_DEFAULT 0x00000000
-
-/* IRQ0 :: IRQEN :: iice_irqen [08:08] */
-#define BCHP_IRQ0_IRQEN_iice_irqen_MASK 0x00000100
-#define BCHP_IRQ0_IRQEN_iice_irqen_SHIFT 8
-#define BCHP_IRQ0_IRQEN_iice_irqen_DEFAULT 0x00000000
-
-/* IRQ0 :: IRQEN :: iicb_irqen [07:07] */
-#define BCHP_IRQ0_IRQEN_iicb_irqen_MASK 0x00000080
-#define BCHP_IRQ0_IRQEN_iicb_irqen_SHIFT 7
-#define BCHP_IRQ0_IRQEN_iicb_irqen_DEFAULT 0x00000000
-
-/* IRQ0 :: IRQEN :: iica_irqen [06:06] */
-#define BCHP_IRQ0_IRQEN_iica_irqen_MASK 0x00000040
-#define BCHP_IRQ0_IRQEN_iica_irqen_SHIFT 6
-#define BCHP_IRQ0_IRQEN_iica_irqen_DEFAULT 0x00000000
-
-/* IRQ0 :: IRQEN :: uc_irqen [05:05] */
-#define BCHP_IRQ0_IRQEN_uc_irqen_MASK 0x00000020
-#define BCHP_IRQ0_IRQEN_uc_irqen_SHIFT 5
-#define BCHP_IRQ0_IRQEN_uc_irqen_DEFAULT 0x00000000
-
-/* IRQ0 :: IRQEN :: ub_irqen [04:04] */
-#define BCHP_IRQ0_IRQEN_ub_irqen_MASK 0x00000010
-#define BCHP_IRQ0_IRQEN_ub_irqen_SHIFT 4
-#define BCHP_IRQ0_IRQEN_ub_irqen_DEFAULT 0x00000000
-
-/* IRQ0 :: IRQEN :: ua_irqen [03:03] */
-#define BCHP_IRQ0_IRQEN_ua_irqen_MASK 0x00000008
-#define BCHP_IRQ0_IRQEN_ua_irqen_SHIFT 3
-#define BCHP_IRQ0_IRQEN_ua_irqen_DEFAULT 0x00000000
-
-/* IRQ0 :: IRQEN :: uartc_irqen [02:02] */
-#define BCHP_IRQ0_IRQEN_uartc_irqen_MASK 0x00000004
-#define BCHP_IRQ0_IRQEN_uartc_irqen_SHIFT 2
-#define BCHP_IRQ0_IRQEN_uartc_irqen_DEFAULT 0x00000000
-
-/* IRQ0 :: IRQEN :: uartb_irqen [01:01] */
-#define BCHP_IRQ0_IRQEN_uartb_irqen_MASK 0x00000002
-#define BCHP_IRQ0_IRQEN_uartb_irqen_SHIFT 1
-#define BCHP_IRQ0_IRQEN_uartb_irqen_DEFAULT 0x00000000
-
-/* IRQ0 :: IRQEN :: uarta_irqen [00:00] */
-#define BCHP_IRQ0_IRQEN_uarta_irqen_MASK 0x00000001
-#define BCHP_IRQ0_IRQEN_uarta_irqen_SHIFT 0
-#define BCHP_IRQ0_IRQEN_uarta_irqen_DEFAULT 0x00000000
-
-/***************************************************************************
- *IRQSTAT - Interrupt Status
- ***************************************************************************/
-/* IRQ0 :: IRQSTAT :: reserved0 [31:13] */
-#define BCHP_IRQ0_IRQSTAT_reserved0_MASK 0xffffe000
-#define BCHP_IRQ0_IRQSTAT_reserved0_SHIFT 13
-
-/* IRQ0 :: IRQSTAT :: irbirq [12:12] */
-#define BCHP_IRQ0_IRQSTAT_irbirq_MASK 0x00001000
-#define BCHP_IRQ0_IRQSTAT_irbirq_SHIFT 12
-#define BCHP_IRQ0_IRQSTAT_irbirq_DEFAULT 0x00000000
-
-/* IRQ0 :: IRQSTAT :: gioirq [11:11] */
-#define BCHP_IRQ0_IRQSTAT_gioirq_MASK 0x00000800
-#define BCHP_IRQ0_IRQSTAT_gioirq_SHIFT 11
-#define BCHP_IRQ0_IRQSTAT_gioirq_DEFAULT 0x00000000
-
-/* IRQ0 :: IRQSTAT :: iicgirq [10:10] */
-#define BCHP_IRQ0_IRQSTAT_iicgirq_MASK 0x00000400
-#define BCHP_IRQ0_IRQSTAT_iicgirq_SHIFT 10
-#define BCHP_IRQ0_IRQSTAT_iicgirq_DEFAULT 0x00000000
-
-/* IRQ0 :: IRQSTAT :: iicfirq [09:09] */
-#define BCHP_IRQ0_IRQSTAT_iicfirq_MASK 0x00000200
-#define BCHP_IRQ0_IRQSTAT_iicfirq_SHIFT 9
-#define BCHP_IRQ0_IRQSTAT_iicfirq_DEFAULT 0x00000000
-
-/* IRQ0 :: IRQSTAT :: iiceirq [08:08] */
-#define BCHP_IRQ0_IRQSTAT_iiceirq_MASK 0x00000100
-#define BCHP_IRQ0_IRQSTAT_iiceirq_SHIFT 8
-#define BCHP_IRQ0_IRQSTAT_iiceirq_DEFAULT 0x00000000
-
-/* IRQ0 :: IRQSTAT :: iicbirq [07:07] */
-#define BCHP_IRQ0_IRQSTAT_iicbirq_MASK 0x00000080
-#define BCHP_IRQ0_IRQSTAT_iicbirq_SHIFT 7
-#define BCHP_IRQ0_IRQSTAT_iicbirq_DEFAULT 0x00000000
-
-/* IRQ0 :: IRQSTAT :: iicairq [06:06] */
-#define BCHP_IRQ0_IRQSTAT_iicairq_MASK 0x00000040
-#define BCHP_IRQ0_IRQSTAT_iicairq_SHIFT 6
-#define BCHP_IRQ0_IRQSTAT_iicairq_DEFAULT 0x00000000
-
-/* IRQ0 :: IRQSTAT :: ucirq [05:05] */
-#define BCHP_IRQ0_IRQSTAT_ucirq_MASK 0x00000020
-#define BCHP_IRQ0_IRQSTAT_ucirq_SHIFT 5
-#define BCHP_IRQ0_IRQSTAT_ucirq_DEFAULT 0x00000000
-
-/* IRQ0 :: IRQSTAT :: ubirq [04:04] */
-#define BCHP_IRQ0_IRQSTAT_ubirq_MASK 0x00000010
-#define BCHP_IRQ0_IRQSTAT_ubirq_SHIFT 4
-#define BCHP_IRQ0_IRQSTAT_ubirq_DEFAULT 0x00000000
-
-/* IRQ0 :: IRQSTAT :: uairq [03:03] */
-#define BCHP_IRQ0_IRQSTAT_uairq_MASK 0x00000008
-#define BCHP_IRQ0_IRQSTAT_uairq_SHIFT 3
-#define BCHP_IRQ0_IRQSTAT_uairq_DEFAULT 0x00000000
-
-/* IRQ0 :: IRQSTAT :: uartc_irq [02:02] */
-#define BCHP_IRQ0_IRQSTAT_uartc_irq_MASK 0x00000004
-#define BCHP_IRQ0_IRQSTAT_uartc_irq_SHIFT 2
-#define BCHP_IRQ0_IRQSTAT_uartc_irq_DEFAULT 0x00000000
-
-/* IRQ0 :: IRQSTAT :: uartb_irq [01:01] */
-#define BCHP_IRQ0_IRQSTAT_uartb_irq_MASK 0x00000002
-#define BCHP_IRQ0_IRQSTAT_uartb_irq_SHIFT 1
-#define BCHP_IRQ0_IRQSTAT_uartb_irq_DEFAULT 0x00000000
-
-/* IRQ0 :: IRQSTAT :: uarta_irq [00:00] */
-#define BCHP_IRQ0_IRQSTAT_uarta_irq_MASK 0x00000001
-#define BCHP_IRQ0_IRQSTAT_uarta_irq_SHIFT 0
-#define BCHP_IRQ0_IRQSTAT_uarta_irq_DEFAULT 0x00000000
-
-#endif /* #ifndef BCHP_IRQ0_H__ */
-
-/* End of File */
diff --git a/include/linux/brcmstb/7366b0/bchp_irq1.h b/include/linux/brcmstb/7366b0/bchp_irq1.h
deleted file mode 100644
index b1fe5be..0000000
--- a/include/linux/brcmstb/7366b0/bchp_irq1.h
+++ /dev/null
@@ -1,196 +0,0 @@
-/***************************************************************************
- * Copyright (c) 1999-2014, Broadcom Corporation
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
- *
- * Module Description:
- * DO NOT EDIT THIS FILE DIRECTLY
- *
- * This module was generated magically with RDB from a source description
- * file. You must edit the source file for changes to be made to this file.
- *
- *
- * Date: Generated on Thu Apr 24 03:08:56 2014
- * Full Compile MD5 Checksum 1af2c2cf28828ece5496e1312aac0166
- * (minus title and desc)
- * MD5 Checksum 3203ffce85e3fc9a10f84123e54057b0
- *
- * Compiled with: RDB Utility combo_header.pl
- * RDB Parser 3.0
- * unknown unknown
- * Perl Interpreter 5.008008
- * Operating System linux
- *
- * Revision History:
- *
- * $brcm_Log: $
- *
- ***************************************************************************/
-
-#ifndef BCHP_IRQ1_H__
-#define BCHP_IRQ1_H__
-
-/***************************************************************************
- *IRQ1 - Level 2 PCI Interrupt Enable/Status
- ***************************************************************************/
-#define BCHP_IRQ1_IRQEN 0x0040a5c0 /* Interrupt Enable */
-#define BCHP_IRQ1_IRQSTAT 0x0040a5c4 /* Interrupt Status */
-
-/***************************************************************************
- *IRQEN - Interrupt Enable
- ***************************************************************************/
-/* IRQ1 :: IRQEN :: reserved0 [31:13] */
-#define BCHP_IRQ1_IRQEN_reserved0_MASK 0xffffe000
-#define BCHP_IRQ1_IRQEN_reserved0_SHIFT 13
-
-/* IRQ1 :: IRQEN :: irb_irqen [12:12] */
-#define BCHP_IRQ1_IRQEN_irb_irqen_MASK 0x00001000
-#define BCHP_IRQ1_IRQEN_irb_irqen_SHIFT 12
-#define BCHP_IRQ1_IRQEN_irb_irqen_DEFAULT 0x00000000
-
-/* IRQ1 :: IRQEN :: gio_irqen [11:11] */
-#define BCHP_IRQ1_IRQEN_gio_irqen_MASK 0x00000800
-#define BCHP_IRQ1_IRQEN_gio_irqen_SHIFT 11
-#define BCHP_IRQ1_IRQEN_gio_irqen_DEFAULT 0x00000000
-
-/* IRQ1 :: IRQEN :: iicg_irqen [10:10] */
-#define BCHP_IRQ1_IRQEN_iicg_irqen_MASK 0x00000400
-#define BCHP_IRQ1_IRQEN_iicg_irqen_SHIFT 10
-#define BCHP_IRQ1_IRQEN_iicg_irqen_DEFAULT 0x00000000
-
-/* IRQ1 :: IRQEN :: iicf_irqen [09:09] */
-#define BCHP_IRQ1_IRQEN_iicf_irqen_MASK 0x00000200
-#define BCHP_IRQ1_IRQEN_iicf_irqen_SHIFT 9
-#define BCHP_IRQ1_IRQEN_iicf_irqen_DEFAULT 0x00000000
-
-/* IRQ1 :: IRQEN :: iice_irqen [08:08] */
-#define BCHP_IRQ1_IRQEN_iice_irqen_MASK 0x00000100
-#define BCHP_IRQ1_IRQEN_iice_irqen_SHIFT 8
-#define BCHP_IRQ1_IRQEN_iice_irqen_DEFAULT 0x00000000
-
-/* IRQ1 :: IRQEN :: iicb_irqen [07:07] */
-#define BCHP_IRQ1_IRQEN_iicb_irqen_MASK 0x00000080
-#define BCHP_IRQ1_IRQEN_iicb_irqen_SHIFT 7
-#define BCHP_IRQ1_IRQEN_iicb_irqen_DEFAULT 0x00000000
-
-/* IRQ1 :: IRQEN :: iica_irqen [06:06] */
-#define BCHP_IRQ1_IRQEN_iica_irqen_MASK 0x00000040
-#define BCHP_IRQ1_IRQEN_iica_irqen_SHIFT 6
-#define BCHP_IRQ1_IRQEN_iica_irqen_DEFAULT 0x00000000
-
-/* IRQ1 :: IRQEN :: uc_irqen [05:05] */
-#define BCHP_IRQ1_IRQEN_uc_irqen_MASK 0x00000020
-#define BCHP_IRQ1_IRQEN_uc_irqen_SHIFT 5
-#define BCHP_IRQ1_IRQEN_uc_irqen_DEFAULT 0x00000000
-
-/* IRQ1 :: IRQEN :: ub_irqen [04:04] */
-#define BCHP_IRQ1_IRQEN_ub_irqen_MASK 0x00000010
-#define BCHP_IRQ1_IRQEN_ub_irqen_SHIFT 4
-#define BCHP_IRQ1_IRQEN_ub_irqen_DEFAULT 0x00000000
-
-/* IRQ1 :: IRQEN :: ua_irqen [03:03] */
-#define BCHP_IRQ1_IRQEN_ua_irqen_MASK 0x00000008
-#define BCHP_IRQ1_IRQEN_ua_irqen_SHIFT 3
-#define BCHP_IRQ1_IRQEN_ua_irqen_DEFAULT 0x00000000
-
-/* IRQ1 :: IRQEN :: uartc_irqen [02:02] */
-#define BCHP_IRQ1_IRQEN_uartc_irqen_MASK 0x00000004
-#define BCHP_IRQ1_IRQEN_uartc_irqen_SHIFT 2
-#define BCHP_IRQ1_IRQEN_uartc_irqen_DEFAULT 0x00000000
-
-/* IRQ1 :: IRQEN :: uartb_irqen [01:01] */
-#define BCHP_IRQ1_IRQEN_uartb_irqen_MASK 0x00000002
-#define BCHP_IRQ1_IRQEN_uartb_irqen_SHIFT 1
-#define BCHP_IRQ1_IRQEN_uartb_irqen_DEFAULT 0x00000000
-
-/* IRQ1 :: IRQEN :: uarta_irqen [00:00] */
-#define BCHP_IRQ1_IRQEN_uarta_irqen_MASK 0x00000001
-#define BCHP_IRQ1_IRQEN_uarta_irqen_SHIFT 0
-#define BCHP_IRQ1_IRQEN_uarta_irqen_DEFAULT 0x00000000
-
-/***************************************************************************
- *IRQSTAT - Interrupt Status
- ***************************************************************************/
-/* IRQ1 :: IRQSTAT :: reserved0 [31:13] */
-#define BCHP_IRQ1_IRQSTAT_reserved0_MASK 0xffffe000
-#define BCHP_IRQ1_IRQSTAT_reserved0_SHIFT 13
-
-/* IRQ1 :: IRQSTAT :: irbirq [12:12] */
-#define BCHP_IRQ1_IRQSTAT_irbirq_MASK 0x00001000
-#define BCHP_IRQ1_IRQSTAT_irbirq_SHIFT 12
-#define BCHP_IRQ1_IRQSTAT_irbirq_DEFAULT 0x00000000
-
-/* IRQ1 :: IRQSTAT :: gioirq [11:11] */
-#define BCHP_IRQ1_IRQSTAT_gioirq_MASK 0x00000800
-#define BCHP_IRQ1_IRQSTAT_gioirq_SHIFT 11
-#define BCHP_IRQ1_IRQSTAT_gioirq_DEFAULT 0x00000000
-
-/* IRQ1 :: IRQSTAT :: iicgirq [10:10] */
-#define BCHP_IRQ1_IRQSTAT_iicgirq_MASK 0x00000400
-#define BCHP_IRQ1_IRQSTAT_iicgirq_SHIFT 10
-#define BCHP_IRQ1_IRQSTAT_iicgirq_DEFAULT 0x00000000
-
-/* IRQ1 :: IRQSTAT :: iicfirq [09:09] */
-#define BCHP_IRQ1_IRQSTAT_iicfirq_MASK 0x00000200
-#define BCHP_IRQ1_IRQSTAT_iicfirq_SHIFT 9
-#define BCHP_IRQ1_IRQSTAT_iicfirq_DEFAULT 0x00000000
-
-/* IRQ1 :: IRQSTAT :: iiceirq [08:08] */
-#define BCHP_IRQ1_IRQSTAT_iiceirq_MASK 0x00000100
-#define BCHP_IRQ1_IRQSTAT_iiceirq_SHIFT 8
-#define BCHP_IRQ1_IRQSTAT_iiceirq_DEFAULT 0x00000000
-
-/* IRQ1 :: IRQSTAT :: iicbirq [07:07] */
-#define BCHP_IRQ1_IRQSTAT_iicbirq_MASK 0x00000080
-#define BCHP_IRQ1_IRQSTAT_iicbirq_SHIFT 7
-#define BCHP_IRQ1_IRQSTAT_iicbirq_DEFAULT 0x00000000
-
-/* IRQ1 :: IRQSTAT :: iicairq [06:06] */
-#define BCHP_IRQ1_IRQSTAT_iicairq_MASK 0x00000040
-#define BCHP_IRQ1_IRQSTAT_iicairq_SHIFT 6
-#define BCHP_IRQ1_IRQSTAT_iicairq_DEFAULT 0x00000000
-
-/* IRQ1 :: IRQSTAT :: ucirq [05:05] */
-#define BCHP_IRQ1_IRQSTAT_ucirq_MASK 0x00000020
-#define BCHP_IRQ1_IRQSTAT_ucirq_SHIFT 5
-#define BCHP_IRQ1_IRQSTAT_ucirq_DEFAULT 0x00000000
-
-/* IRQ1 :: IRQSTAT :: ubirq [04:04] */
-#define BCHP_IRQ1_IRQSTAT_ubirq_MASK 0x00000010
-#define BCHP_IRQ1_IRQSTAT_ubirq_SHIFT 4
-#define BCHP_IRQ1_IRQSTAT_ubirq_DEFAULT 0x00000000
-
-/* IRQ1 :: IRQSTAT :: uairq [03:03] */
-#define BCHP_IRQ1_IRQSTAT_uairq_MASK 0x00000008
-#define BCHP_IRQ1_IRQSTAT_uairq_SHIFT 3
-#define BCHP_IRQ1_IRQSTAT_uairq_DEFAULT 0x00000000
-
-/* IRQ1 :: IRQSTAT :: uartc_irq [02:02] */
-#define BCHP_IRQ1_IRQSTAT_uartc_irq_MASK 0x00000004
-#define BCHP_IRQ1_IRQSTAT_uartc_irq_SHIFT 2
-#define BCHP_IRQ1_IRQSTAT_uartc_irq_DEFAULT 0x00000000
-
-/* IRQ1 :: IRQSTAT :: uartb_irq [01:01] */
-#define BCHP_IRQ1_IRQSTAT_uartb_irq_MASK 0x00000002
-#define BCHP_IRQ1_IRQSTAT_uartb_irq_SHIFT 1
-#define BCHP_IRQ1_IRQSTAT_uartb_irq_DEFAULT 0x00000000
-
-/* IRQ1 :: IRQSTAT :: uarta_irq [00:00] */
-#define BCHP_IRQ1_IRQSTAT_uarta_irq_MASK 0x00000001
-#define BCHP_IRQ1_IRQSTAT_uarta_irq_SHIFT 0
-#define BCHP_IRQ1_IRQSTAT_uarta_irq_DEFAULT 0x00000000
-
-#endif /* #ifndef BCHP_IRQ1_H__ */
-
-/* End of File */
diff --git a/include/linux/brcmstb/7366b0/bchp_memc_ddr_0.h b/include/linux/brcmstb/7366b0/bchp_memc_ddr_0.h
deleted file mode 100644
index dd79c22..0000000
--- a/include/linux/brcmstb/7366b0/bchp_memc_ddr_0.h
+++ /dev/null
@@ -1,4799 +0,0 @@
-/***************************************************************************
- * Copyright (c) 1999-2014, Broadcom Corporation
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
- *
- * Module Description:
- * DO NOT EDIT THIS FILE DIRECTLY
- *
- * This module was generated magically with RDB from a source description
- * file. You must edit the source file for changes to be made to this file.
- *
- *
- * Date: Generated on Thu Apr 24 03:08:53 2014
- * Full Compile MD5 Checksum 1af2c2cf28828ece5496e1312aac0166
- * (minus title and desc)
- * MD5 Checksum 3203ffce85e3fc9a10f84123e54057b0
- *
- * Compiled with: RDB Utility combo_header.pl
- * RDB Parser 3.0
- * unknown unknown
- * Perl Interpreter 5.008008
- * Operating System linux
- *
- * Revision History:
- *
- * $brcm_Log: $
- *
- ***************************************************************************/
-
-#ifndef BCHP_MEMC_DDR_0_H__
-#define BCHP_MEMC_DDR_0_H__
-
-/***************************************************************************
- *MEMC_DDR_0 - Sequencer DRAM Param and Control Registers
- ***************************************************************************/
-#define BCHP_MEMC_DDR_0_CNTRLR_CONFIG 0x00502000 /* Memory Controller Configuration Register */
-#define BCHP_MEMC_DDR_0_CNTRLR_CONFIG_STATUS 0x00502004 /* Memory Controller Configuration Status Register */
-#define BCHP_MEMC_DDR_0_DRAM_INIT_CNTRL 0x00502008 /* Dram initialization control */
-#define BCHP_MEMC_DDR_0_DRAM_INIT_STATUS 0x0050200c /* Dram initialization status */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_0 0x00502010 /* Dram Mode Register 0 */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_1 0x00502014 /* Dram Mode Register 1 */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_2 0x00502018 /* Dram Mode Register 2 */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_3 0x0050201c /* Dram Mode Register 3 */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_4 0x00502020 /* Dram Mode Register 4 */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_5 0x00502024 /* Dram Mode Register 5 */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_6 0x00502028 /* Dram Mode Register 6 */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_7 0x0050202c /* Dram Mode Register 7 */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_8 0x00502030 /* Dram Mode Register 8 */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_15 0x00502034 /* Dram Mode Register 15 */
-#define BCHP_MEMC_DDR_0_PPD_CONFIG 0x00502038 /* Precharge power down mode configuration register */
-#define BCHP_MEMC_DDR_0_SRPD_CONFIG 0x0050203c /* Self-refresh power down mode configuration register */
-#define BCHP_MEMC_DDR_0_SSPD_CMD 0x00502040 /* Software standby power down mode */
-#define BCHP_MEMC_DDR_0_POWER_DOWN_STATUS 0x00502044 /* Power down status */
-#define BCHP_MEMC_DDR_0_WARM_BOOT 0x00502048 /* Warm boot control registers */
-#define BCHP_MEMC_DDR_0_DRAM_TIMING_0 0x0050204c /* DDR-SDRAM Timing Register 0 */
-#define BCHP_MEMC_DDR_0_DRAM_TIMING_1 0x00502050 /* DDR-SDRAM Timing Register 1 */
-#define BCHP_MEMC_DDR_0_DRAM_TIMING_2 0x00502054 /* Read to Write & write to read timing register */
-#define BCHP_MEMC_DDR_0_DRAM_TIMING_3 0x00502058 /* DDR-SDRAM Timing Register 3 */
-#define BCHP_MEMC_DDR_0_DRAM_TIMING_4 0x0050205c /* DDR-SDRAM Timing Register 4 */
-#define BCHP_MEMC_DDR_0_DRAM_TIMING_5 0x00502060 /* DDR-SDRAM Timing Register 5 */
-#define BCHP_MEMC_DDR_0_MIN_DQ_IDLE_CONTROL 0x00502064 /* Minimum DQ Idle Time Control */
-#define BCHP_MEMC_DDR_0_PHY_OP_ACCESS_PENALTY 0x00502068 /* PHY Operational Access Penalty Count. */
-#define BCHP_MEMC_DDR_0_CNTRLR_SM_TIMEOUT 0x0050206c /* Memory Controller , state machine timeout register. */
-#define BCHP_MEMC_DDR_0_BANK_STATUS 0x00502070 /* Memory Controller, Bank Status Register */
-#define BCHP_MEMC_DDR_0_TESTER_LATENCY 0x00502074 /* Memory Controller, Tester Latency Register. */
-#define BCHP_MEMC_DDR_0_SEQ_RING_BUF_DEPTH 0x00502078 /* Sequencer Ring Buffer programmable depth. */
-#define BCHP_MEMC_DDR_0_SEQ_WRDATA_ERR_INFO 0x0050207c /* Sequencer write data error info */
-#define BCHP_MEMC_DDR_0_SEQ_WRDATA_TRANSID_MISMATCH_INFO 0x00502080 /* Sequencer transaction ID mismatch error info */
-#define BCHP_MEMC_DDR_0_SEQ_CLEAR_VIOLATIONS 0x00502084 /* Sequencer Violation Info register clear. */
-#define BCHP_MEMC_DDR_0_CMD_LOOKAHEAD 0x00502088 /* Command Lookahead */
-#define BCHP_MEMC_DDR_0_DFI_PHASE_ENABLE 0x0050208c /* Sequencer DFI Phase Enable */
-#define BCHP_MEMC_DDR_0_STAT_CONTROL 0x00502300 /* Statistics Control register */
-#define BCHP_MEMC_DDR_0_STAT_TIMER 0x00502304 /* Statistics Timer */
-#define BCHP_MEMC_DDR_0_STAT_IDLE_NOP 0x00502308 /* DRAM Idle_NOP Cycle Count Register. */
-#define BCHP_MEMC_DDR_0_STAT_MAX_IDLE_NOP 0x0050230c /* Maximum DRAM idle_NOP cycle count register. */
-#define BCHP_MEMC_DDR_0_STAT_MIN_IDLE_NOP 0x00502310 /* Minimum DRAM idle_NOP cycle count register. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_ALL 0x00502314 /* CAS Count Register. */
-#define BCHP_MEMC_DDR_0_STAT_MAX_CAS_ALL 0x00502318 /* Maximum DRAM CAS cycle count register. */
-#define BCHP_MEMC_DDR_0_STAT_MIN_CAS_ALL 0x0050231c /* Minimum DRAM CAS cycle count register. */
-#define BCHP_MEMC_DDR_0_STAT_PENALTY_ALL 0x00502320 /* DRAM Penalty Cycle Count register. */
-#define BCHP_MEMC_DDR_0_STAT_PENALTY_GDDRWM 0x00502324 /* GDDR Write Mask Penalty Cycle Count register. */
-#define BCHP_MEMC_DDR_0_STAT_PAGE_MERGE_ALL 0x00502328 /* Page Merge Event Count register. */
-#define BCHP_MEMC_DDR_0_STAT_MAX_TRANS_CYCLES_ALL 0x0050232c /* Maximum number of transactions cycles (CAS+Penalty_ALL). */
-#define BCHP_MEMC_DDR_0_STAT_MIN_TRANS_CYCLES_ALL 0x00502330 /* Minimum number of transactions cycles (CAS+Penalty_ALL). */
-#define BCHP_MEMC_DDR_0_STAT_TRANS_READ_ALL 0x00502334 /* Number of overall system memory read transactions. */
-#define BCHP_MEMC_DDR_0_STAT_TRANS_WRITE_ALL 0x00502338 /* Number of overall system memory write transactions. */
-#define BCHP_MEMC_DDR_0_STAT_MAX_TRANS_ALL 0x0050233c /* Maximum Number of Overall System memory transactions. */
-#define BCHP_MEMC_DDR_0_STAT_MIN_TRANS_ALL 0x00502340 /* Minimum Number of Overall System memory transactions. */
-#define BCHP_MEMC_DDR_0_STAT_CLIENT_SERVICE_CAS 0x00502344 /* Service CAS Cycle Count register. */
-#define BCHP_MEMC_DDR_0_STAT_MAX_CLIENT_SERVICE_CAS 0x00502348 /* Maximum service CAS cycle count register. */
-#define BCHP_MEMC_DDR_0_STAT_MIN_CLIENT_SERVICE_CAS 0x0050234c /* Minimum service CAS cycle count register. */
-#define BCHP_MEMC_DDR_0_STAT_CLIENT_SERVICE_INTR_PENALTY 0x00502350 /* Service Intra DRAM Penalty Cycle Count register. */
-#define BCHP_MEMC_DDR_0_STAT_CLIENT_SERVICE_POST_PENALTY 0x00502354 /* Service Post DRAM Penalty Cycle Count register. */
-#define BCHP_MEMC_DDR_0_STAT_CLIENT_SERVICE_GDDRWM_PENALTY 0x00502358 /* Service GDDR Write Mask Penalty Cycle Count register. */
-#define BCHP_MEMC_DDR_0_STAT_CLIENT_SERVICE_PAGE_MERGES 0x0050235c /* Service Page Merge Event Count register. */
-#define BCHP_MEMC_DDR_0_STAT_MAX_CLIENT_SERVICE_CYCLES 0x00502360 /* Maximum service cycle count register. */
-#define BCHP_MEMC_DDR_0_STAT_MIN_CLIENT_SERVICE_CYCLES 0x00502364 /* Minimum service cycle count register. */
-#define BCHP_MEMC_DDR_0_STAT_CLIENT_SERVICE_TRANS_READ 0x00502368 /* Service Read Transaction Count register. */
-#define BCHP_MEMC_DDR_0_STAT_CLIENT_SERVICE_TRANS_WRITE 0x0050236c /* Service Write Transaction Count register. */
-#define BCHP_MEMC_DDR_0_STAT_MAX_CLIENT_SERVICE_TRANS 0x00502370 /* Maximum service Transaction count register. */
-#define BCHP_MEMC_DDR_0_STAT_MIN_CLIENT_SERVICE_TRANS 0x00502374 /* Minimum service cycle Transaction register. */
-#define BCHP_MEMC_DDR_0_STAT_CLIENT_SERVICE_LATENCY 0x00502378 /* Service Latency Count register. */
-#define BCHP_MEMC_DDR_0_STAT_MAX_CLIENT_SERVICE_LATENCY 0x0050237c /* Maximum Service Latency count register. */
-#define BCHP_MEMC_DDR_0_STAT_MIN_CLIENT_SERVICE_LATENCY 0x00502380 /* Minimum Service Latency count register. */
-#define BCHP_MEMC_DDR_0_STAT_CLIENT_ABS_MAX_SERVICE_LATENCY 0x00502384 /* Absolute Minimum Service Latency count register. */
-#define BCHP_MEMC_DDR_0_STAT_CLIENT_ABS_MIN_SERVICE_LATENCY 0x00502388 /* Absolute Maximum Service Latency count register. */
-#define BCHP_MEMC_DDR_0_STAT_REFRESH 0x0050238c /* Total number of refreshes issued. */
-#define BCHP_MEMC_DDR_0_STAT_MIN_DQ_IDLE_WRITE 0x00502390 /* Min DQ Idle Write event counter */
-#define BCHP_MEMC_DDR_0_STAT_MIN_DQ_IDLE_READ 0x00502394 /* Min DQ Idle Read event counter */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_0 0x00502400 /* CAS or consumption cycle count register for client 0. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_1 0x00502404 /* CAS or consumption cycle count register for client 1. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_2 0x00502408 /* CAS or consumption cycle count register for client 2. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_3 0x0050240c /* CAS or consumption cycle count register for client 3. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_4 0x00502410 /* CAS or consumption cycle count register for client 4. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_5 0x00502414 /* CAS or consumption cycle count register for client 5. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_6 0x00502418 /* CAS or consumption cycle count register for client 6. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_7 0x0050241c /* CAS or consumption cycle count register for client 7. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_8 0x00502420 /* CAS or consumption cycle count register for client 8. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_9 0x00502424 /* CAS or consumption cycle count register for client 9. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_10 0x00502428 /* CAS or consumption cycle count register for client 10. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_11 0x0050242c /* CAS or consumption cycle count register for client 11. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_12 0x00502430 /* CAS or consumption cycle count register for client 12. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_13 0x00502434 /* CAS or consumption cycle count register for client 13. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_14 0x00502438 /* CAS or consumption cycle count register for client 14. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_15 0x0050243c /* CAS or consumption cycle count register for client 15. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_16 0x00502440 /* CAS or consumption cycle count register for client 16. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_17 0x00502444 /* CAS or consumption cycle count register for client 17. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_18 0x00502448 /* CAS or consumption cycle count register for client 18. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_19 0x0050244c /* CAS or consumption cycle count register for client 19. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_20 0x00502450 /* CAS or consumption cycle count register for client 20. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_21 0x00502454 /* CAS or consumption cycle count register for client 21. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_22 0x00502458 /* CAS or consumption cycle count register for client 22. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_23 0x0050245c /* CAS or consumption cycle count register for client 23. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_24 0x00502460 /* CAS or consumption cycle count register for client 24. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_25 0x00502464 /* CAS or consumption cycle count register for client 25. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_26 0x00502468 /* CAS or consumption cycle count register for client 26. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_27 0x0050246c /* CAS or consumption cycle count register for client 27. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_28 0x00502470 /* CAS or consumption cycle count register for client 28. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_29 0x00502474 /* CAS or consumption cycle count register for client 29. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_30 0x00502478 /* CAS or consumption cycle count register for client 30. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_31 0x0050247c /* CAS or consumption cycle count register for client 31. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_32 0x00502480 /* CAS or consumption cycle count register for client 32. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_33 0x00502484 /* CAS or consumption cycle count register for client 33. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_34 0x00502488 /* CAS or consumption cycle count register for client 34. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_35 0x0050248c /* CAS or consumption cycle count register for client 35. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_36 0x00502490 /* CAS or consumption cycle count register for client 36. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_37 0x00502494 /* CAS or consumption cycle count register for client 37. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_38 0x00502498 /* CAS or consumption cycle count register for client 38. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_39 0x0050249c /* CAS or consumption cycle count register for client 39. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_40 0x005024a0 /* CAS or consumption cycle count register for client 40. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_41 0x005024a4 /* CAS or consumption cycle count register for client 41. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_42 0x005024a8 /* CAS or consumption cycle count register for client 42. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_43 0x005024ac /* CAS or consumption cycle count register for client 43. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_44 0x005024b0 /* CAS or consumption cycle count register for client 44. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_45 0x005024b4 /* CAS or consumption cycle count register for client 45. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_46 0x005024b8 /* CAS or consumption cycle count register for client 46. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_47 0x005024bc /* CAS or consumption cycle count register for client 47. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_48 0x005024c0 /* CAS or consumption cycle count register for client 48. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_49 0x005024c4 /* CAS or consumption cycle count register for client 49. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_50 0x005024c8 /* CAS or consumption cycle count register for client 50. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_51 0x005024cc /* CAS or consumption cycle count register for client 51. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_52 0x005024d0 /* CAS or consumption cycle count register for client 52. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_53 0x005024d4 /* CAS or consumption cycle count register for client 53. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_54 0x005024d8 /* CAS or consumption cycle count register for client 54. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_55 0x005024dc /* CAS or consumption cycle count register for client 55. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_56 0x005024e0 /* CAS or consumption cycle count register for client 56. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_57 0x005024e4 /* CAS or consumption cycle count register for client 57. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_58 0x005024e8 /* CAS or consumption cycle count register for client 58. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_59 0x005024ec /* CAS or consumption cycle count register for client 59. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_60 0x005024f0 /* CAS or consumption cycle count register for client 60. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_61 0x005024f4 /* CAS or consumption cycle count register for client 61. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_62 0x005024f8 /* CAS or consumption cycle count register for client 62. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_63 0x005024fc /* CAS or consumption cycle count register for client 63. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_64 0x00502500 /* CAS or consumption cycle count register for client 64. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_65 0x00502504 /* CAS or consumption cycle count register for client 65. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_66 0x00502508 /* CAS or consumption cycle count register for client 66. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_67 0x0050250c /* CAS or consumption cycle count register for client 67. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_68 0x00502510 /* CAS or consumption cycle count register for client 68. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_69 0x00502514 /* CAS or consumption cycle count register for client 69. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_70 0x00502518 /* CAS or consumption cycle count register for client 70. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_71 0x0050251c /* CAS or consumption cycle count register for client 71. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_72 0x00502520 /* CAS or consumption cycle count register for client 72. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_73 0x00502524 /* CAS or consumption cycle count register for client 73. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_74 0x00502528 /* CAS or consumption cycle count register for client 74. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_75 0x0050252c /* CAS or consumption cycle count register for client 75. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_76 0x00502530 /* CAS or consumption cycle count register for client 76. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_77 0x00502534 /* CAS or consumption cycle count register for client 77. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_78 0x00502538 /* CAS or consumption cycle count register for client 78. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_79 0x0050253c /* CAS or consumption cycle count register for client 79. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_80 0x00502540 /* CAS or consumption cycle count register for client 80. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_81 0x00502544 /* CAS or consumption cycle count register for client 81. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_82 0x00502548 /* CAS or consumption cycle count register for client 82. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_83 0x0050254c /* CAS or consumption cycle count register for client 83. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_84 0x00502550 /* CAS or consumption cycle count register for client 84. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_85 0x00502554 /* CAS or consumption cycle count register for client 85. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_86 0x00502558 /* CAS or consumption cycle count register for client 86. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_87 0x0050255c /* CAS or consumption cycle count register for client 87. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_88 0x00502560 /* CAS or consumption cycle count register for client 88. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_89 0x00502564 /* CAS or consumption cycle count register for client 89. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_90 0x00502568 /* CAS or consumption cycle count register for client 90. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_91 0x0050256c /* CAS or consumption cycle count register for client 91. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_92 0x00502570 /* CAS or consumption cycle count register for client 92. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_93 0x00502574 /* CAS or consumption cycle count register for client 93. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_94 0x00502578 /* CAS or consumption cycle count register for client 94. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_95 0x0050257c /* CAS or consumption cycle count register for client 95. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_96 0x00502580 /* CAS or consumption cycle count register for client 96. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_97 0x00502584 /* CAS or consumption cycle count register for client 97. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_98 0x00502588 /* CAS or consumption cycle count register for client 98. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_99 0x0050258c /* CAS or consumption cycle count register for client 99. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_100 0x00502590 /* CAS or consumption cycle count register for client 100. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_101 0x00502594 /* CAS or consumption cycle count register for client 101. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_102 0x00502598 /* CAS or consumption cycle count register for client 102. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_103 0x0050259c /* CAS or consumption cycle count register for client 103. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_104 0x005025a0 /* CAS or consumption cycle count register for client 104. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_105 0x005025a4 /* CAS or consumption cycle count register for client 105. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_106 0x005025a8 /* CAS or consumption cycle count register for client 106. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_107 0x005025ac /* CAS or consumption cycle count register for client 107. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_108 0x005025b0 /* CAS or consumption cycle count register for client 108. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_109 0x005025b4 /* CAS or consumption cycle count register for client 109. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_110 0x005025b8 /* CAS or consumption cycle count register for client 110. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_111 0x005025bc /* CAS or consumption cycle count register for client 111. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_112 0x005025c0 /* CAS or consumption cycle count register for client 112. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_113 0x005025c4 /* CAS or consumption cycle count register for client 113. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_114 0x005025c8 /* CAS or consumption cycle count register for client 114. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_115 0x005025cc /* CAS or consumption cycle count register for client 115. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_116 0x005025d0 /* CAS or consumption cycle count register for client 116. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_117 0x005025d4 /* CAS or consumption cycle count register for client 117. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_118 0x005025d8 /* CAS or consumption cycle count register for client 118. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_119 0x005025dc /* CAS or consumption cycle count register for client 119. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_120 0x005025e0 /* CAS or consumption cycle count register for client 120. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_121 0x005025e4 /* CAS or consumption cycle count register for client 121. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_122 0x005025e8 /* CAS or consumption cycle count register for client 122. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_123 0x005025ec /* CAS or consumption cycle count register for client 123. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_124 0x005025f0 /* CAS or consumption cycle count register for client 124. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_125 0x005025f4 /* CAS or consumption cycle count register for client 125. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_126 0x005025f8 /* CAS or consumption cycle count register for client 126. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_127 0x005025fc /* CAS or consumption cycle count register for client 127. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_128 0x00502600 /* CAS or consumption cycle count register for client 128. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_129 0x00502604 /* CAS or consumption cycle count register for client 129. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_130 0x00502608 /* CAS or consumption cycle count register for client 130. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_131 0x0050260c /* CAS or consumption cycle count register for client 131. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_132 0x00502610 /* CAS or consumption cycle count register for client 132. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_133 0x00502614 /* CAS or consumption cycle count register for client 133. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_134 0x00502618 /* CAS or consumption cycle count register for client 134. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_135 0x0050261c /* CAS or consumption cycle count register for client 135. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_136 0x00502620 /* CAS or consumption cycle count register for client 136. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_137 0x00502624 /* CAS or consumption cycle count register for client 137. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_138 0x00502628 /* CAS or consumption cycle count register for client 138. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_139 0x0050262c /* CAS or consumption cycle count register for client 139. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_140 0x00502630 /* CAS or consumption cycle count register for client 140. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_141 0x00502634 /* CAS or consumption cycle count register for client 141. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_142 0x00502638 /* CAS or consumption cycle count register for client 142. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_143 0x0050263c /* CAS or consumption cycle count register for client 143. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_144 0x00502640 /* CAS or consumption cycle count register for client 144. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_145 0x00502644 /* CAS or consumption cycle count register for client 145. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_146 0x00502648 /* CAS or consumption cycle count register for client 146. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_147 0x0050264c /* CAS or consumption cycle count register for client 147. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_148 0x00502650 /* CAS or consumption cycle count register for client 148. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_149 0x00502654 /* CAS or consumption cycle count register for client 149. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_150 0x00502658 /* CAS or consumption cycle count register for client 150. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_151 0x0050265c /* CAS or consumption cycle count register for client 151. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_152 0x00502660 /* CAS or consumption cycle count register for client 152. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_153 0x00502664 /* CAS or consumption cycle count register for client 153. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_154 0x00502668 /* CAS or consumption cycle count register for client 154. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_155 0x0050266c /* CAS or consumption cycle count register for client 155. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_156 0x00502670 /* CAS or consumption cycle count register for client 156. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_157 0x00502674 /* CAS or consumption cycle count register for client 157. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_158 0x00502678 /* CAS or consumption cycle count register for client 158. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_159 0x0050267c /* CAS or consumption cycle count register for client 159. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_160 0x00502680 /* CAS or consumption cycle count register for client 160. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_161 0x00502684 /* CAS or consumption cycle count register for client 161. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_162 0x00502688 /* CAS or consumption cycle count register for client 162. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_163 0x0050268c /* CAS or consumption cycle count register for client 163. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_164 0x00502690 /* CAS or consumption cycle count register for client 164. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_165 0x00502694 /* CAS or consumption cycle count register for client 165. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_166 0x00502698 /* CAS or consumption cycle count register for client 166. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_167 0x0050269c /* CAS or consumption cycle count register for client 167. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_168 0x005026a0 /* CAS or consumption cycle count register for client 168. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_169 0x005026a4 /* CAS or consumption cycle count register for client 169. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_170 0x005026a8 /* CAS or consumption cycle count register for client 170. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_171 0x005026ac /* CAS or consumption cycle count register for client 171. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_172 0x005026b0 /* CAS or consumption cycle count register for client 172. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_173 0x005026b4 /* CAS or consumption cycle count register for client 173. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_174 0x005026b8 /* CAS or consumption cycle count register for client 174. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_175 0x005026bc /* CAS or consumption cycle count register for client 175. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_176 0x005026c0 /* CAS or consumption cycle count register for client 176. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_177 0x005026c4 /* CAS or consumption cycle count register for client 177. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_178 0x005026c8 /* CAS or consumption cycle count register for client 178. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_179 0x005026cc /* CAS or consumption cycle count register for client 179. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_180 0x005026d0 /* CAS or consumption cycle count register for client 180. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_181 0x005026d4 /* CAS or consumption cycle count register for client 181. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_182 0x005026d8 /* CAS or consumption cycle count register for client 182. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_183 0x005026dc /* CAS or consumption cycle count register for client 183. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_184 0x005026e0 /* CAS or consumption cycle count register for client 184. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_185 0x005026e4 /* CAS or consumption cycle count register for client 185. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_186 0x005026e8 /* CAS or consumption cycle count register for client 186. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_187 0x005026ec /* CAS or consumption cycle count register for client 187. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_188 0x005026f0 /* CAS or consumption cycle count register for client 188. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_189 0x005026f4 /* CAS or consumption cycle count register for client 189. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_190 0x005026f8 /* CAS or consumption cycle count register for client 190. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_191 0x005026fc /* CAS or consumption cycle count register for client 191. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_192 0x00502700 /* CAS or consumption cycle count register for client 192. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_193 0x00502704 /* CAS or consumption cycle count register for client 193. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_194 0x00502708 /* CAS or consumption cycle count register for client 194. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_195 0x0050270c /* CAS or consumption cycle count register for client 195. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_196 0x00502710 /* CAS or consumption cycle count register for client 196. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_197 0x00502714 /* CAS or consumption cycle count register for client 197. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_198 0x00502718 /* CAS or consumption cycle count register for client 198. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_199 0x0050271c /* CAS or consumption cycle count register for client 199. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_200 0x00502720 /* CAS or consumption cycle count register for client 200. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_201 0x00502724 /* CAS or consumption cycle count register for client 201. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_202 0x00502728 /* CAS or consumption cycle count register for client 202. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_203 0x0050272c /* CAS or consumption cycle count register for client 203. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_204 0x00502730 /* CAS or consumption cycle count register for client 204. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_205 0x00502734 /* CAS or consumption cycle count register for client 205. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_206 0x00502738 /* CAS or consumption cycle count register for client 206. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_207 0x0050273c /* CAS or consumption cycle count register for client 207. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_208 0x00502740 /* CAS or consumption cycle count register for client 208. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_209 0x00502744 /* CAS or consumption cycle count register for client 209. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_210 0x00502748 /* CAS or consumption cycle count register for client 210. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_211 0x0050274c /* CAS or consumption cycle count register for client 211. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_212 0x00502750 /* CAS or consumption cycle count register for client 212. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_213 0x00502754 /* CAS or consumption cycle count register for client 213. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_214 0x00502758 /* CAS or consumption cycle count register for client 214. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_215 0x0050275c /* CAS or consumption cycle count register for client 215. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_216 0x00502760 /* CAS or consumption cycle count register for client 216. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_217 0x00502764 /* CAS or consumption cycle count register for client 217. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_218 0x00502768 /* CAS or consumption cycle count register for client 218. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_219 0x0050276c /* CAS or consumption cycle count register for client 219. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_220 0x00502770 /* CAS or consumption cycle count register for client 220. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_221 0x00502774 /* CAS or consumption cycle count register for client 221. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_222 0x00502778 /* CAS or consumption cycle count register for client 222. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_223 0x0050277c /* CAS or consumption cycle count register for client 223. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_224 0x00502780 /* CAS or consumption cycle count register for client 224. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_225 0x00502784 /* CAS or consumption cycle count register for client 225. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_226 0x00502788 /* CAS or consumption cycle count register for client 226. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_227 0x0050278c /* CAS or consumption cycle count register for client 227. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_228 0x00502790 /* CAS or consumption cycle count register for client 228. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_229 0x00502794 /* CAS or consumption cycle count register for client 229. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_230 0x00502798 /* CAS or consumption cycle count register for client 230. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_231 0x0050279c /* CAS or consumption cycle count register for client 231. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_232 0x005027a0 /* CAS or consumption cycle count register for client 232. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_233 0x005027a4 /* CAS or consumption cycle count register for client 233. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_234 0x005027a8 /* CAS or consumption cycle count register for client 234. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_235 0x005027ac /* CAS or consumption cycle count register for client 235. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_236 0x005027b0 /* CAS or consumption cycle count register for client 236. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_237 0x005027b4 /* CAS or consumption cycle count register for client 237. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_238 0x005027b8 /* CAS or consumption cycle count register for client 238. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_239 0x005027bc /* CAS or consumption cycle count register for client 239. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_240 0x005027c0 /* CAS or consumption cycle count register for client 240. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_241 0x005027c4 /* CAS or consumption cycle count register for client 241. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_242 0x005027c8 /* CAS or consumption cycle count register for client 242. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_243 0x005027cc /* CAS or consumption cycle count register for client 243. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_244 0x005027d0 /* CAS or consumption cycle count register for client 244. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_245 0x005027d4 /* CAS or consumption cycle count register for client 245. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_246 0x005027d8 /* CAS or consumption cycle count register for client 246. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_247 0x005027dc /* CAS or consumption cycle count register for client 247. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_248 0x005027e0 /* CAS or consumption cycle count register for client 248. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_249 0x005027e4 /* CAS or consumption cycle count register for client 249. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_250 0x005027e8 /* CAS or consumption cycle count register for client 250. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_251 0x005027ec /* CAS or consumption cycle count register for client 251. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_252 0x005027f0 /* CAS or consumption cycle count register for client 252. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_253 0x005027f4 /* CAS or consumption cycle count register for client 253. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_254 0x005027f8 /* CAS or consumption cycle count register for client 254. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_255 0x005027fc /* CAS or consumption cycle count register for client 255. */
-
-/***************************************************************************
- *CNTRLR_CONFIG - Memory Controller Configuration Register
- ***************************************************************************/
-/* MEMC_DDR_0 :: CNTRLR_CONFIG :: reserved0 [31:15] */
-#define BCHP_MEMC_DDR_0_CNTRLR_CONFIG_reserved0_MASK 0xffff8000
-#define BCHP_MEMC_DDR_0_CNTRLR_CONFIG_reserved0_SHIFT 15
-
-/* MEMC_DDR_0 :: CNTRLR_CONFIG :: GROUPAGE_ENABLE [14:14] */
-#define BCHP_MEMC_DDR_0_CNTRLR_CONFIG_GROUPAGE_ENABLE_MASK 0x00004000
-#define BCHP_MEMC_DDR_0_CNTRLR_CONFIG_GROUPAGE_ENABLE_SHIFT 14
-#define BCHP_MEMC_DDR_0_CNTRLR_CONFIG_GROUPAGE_ENABLE_DEFAULT 0x00000000
-
-/* MEMC_DDR_0 :: CNTRLR_CONFIG :: MODIFY_RASTER_ADDR [13:13] */
-#define BCHP_MEMC_DDR_0_CNTRLR_CONFIG_MODIFY_RASTER_ADDR_MASK 0x00002000
-#define BCHP_MEMC_DDR_0_CNTRLR_CONFIG_MODIFY_RASTER_ADDR_SHIFT 13
-#define BCHP_MEMC_DDR_0_CNTRLR_CONFIG_MODIFY_RASTER_ADDR_DEFAULT 0x00000001
-
-/* MEMC_DDR_0 :: CNTRLR_CONFIG :: DRAM_COMMANDS_2T [12:12] */
-#define BCHP_MEMC_DDR_0_CNTRLR_CONFIG_DRAM_COMMANDS_2T_MASK 0x00001000
-#define BCHP_MEMC_DDR_0_CNTRLR_CONFIG_DRAM_COMMANDS_2T_SHIFT 12
-#define BCHP_MEMC_DDR_0_CNTRLR_CONFIG_DRAM_COMMANDS_2T_DEFAULT 0x00000000
-
-/* MEMC_DDR_0 :: CNTRLR_CONFIG :: DRAM_TOTAL_WIDTH [11:10] */
-#define BCHP_MEMC_DDR_0_CNTRLR_CONFIG_DRAM_TOTAL_WIDTH_MASK 0x00000c00
-#define BCHP_MEMC_DDR_0_CNTRLR_CONFIG_DRAM_TOTAL_WIDTH_SHIFT 10
-#define BCHP_MEMC_DDR_0_CNTRLR_CONFIG_DRAM_TOTAL_WIDTH_DEFAULT 0x00000002
-#define BCHP_MEMC_DDR_0_CNTRLR_CONFIG_DRAM_TOTAL_WIDTH_reserved_x8 0
-#define BCHP_MEMC_DDR_0_CNTRLR_CONFIG_DRAM_TOTAL_WIDTH_x16 1
-#define BCHP_MEMC_DDR_0_CNTRLR_CONFIG_DRAM_TOTAL_WIDTH_x32 2
-#define BCHP_MEMC_DDR_0_CNTRLR_CONFIG_DRAM_TOTAL_WIDTH_reserved_x64 3
-
-/* MEMC_DDR_0 :: CNTRLR_CONFIG :: DRAM_DEVICE_WIDTH [09:08] */
-#define BCHP_MEMC_DDR_0_CNTRLR_CONFIG_DRAM_DEVICE_WIDTH_MASK 0x00000300
-#define BCHP_MEMC_DDR_0_CNTRLR_CONFIG_DRAM_DEVICE_WIDTH_SHIFT 8
-#define BCHP_MEMC_DDR_0_CNTRLR_CONFIG_DRAM_DEVICE_WIDTH_DEFAULT 0x00000001
-#define BCHP_MEMC_DDR_0_CNTRLR_CONFIG_DRAM_DEVICE_WIDTH_x8 0
-#define BCHP_MEMC_DDR_0_CNTRLR_CONFIG_DRAM_DEVICE_WIDTH_x16 1
-#define BCHP_MEMC_DDR_0_CNTRLR_CONFIG_DRAM_DEVICE_WIDTH_reserved_2 2
-#define BCHP_MEMC_DDR_0_CNTRLR_CONFIG_DRAM_DEVICE_WIDTH_reserved_3 3
-
-/* MEMC_DDR_0 :: CNTRLR_CONFIG :: DRAM_DEVICE_SIZE [07:04] */
-#define BCHP_MEMC_DDR_0_CNTRLR_CONFIG_DRAM_DEVICE_SIZE_MASK 0x000000f0
-#define BCHP_MEMC_DDR_0_CNTRLR_CONFIG_DRAM_DEVICE_SIZE_SHIFT 4
-#define BCHP_MEMC_DDR_0_CNTRLR_CONFIG_DRAM_DEVICE_SIZE_DEFAULT 0x00000003
-#define BCHP_MEMC_DDR_0_CNTRLR_CONFIG_DRAM_DEVICE_SIZE_reserved_256_Mb 0
-#define BCHP_MEMC_DDR_0_CNTRLR_CONFIG_DRAM_DEVICE_SIZE_512_Mb 1
-#define BCHP_MEMC_DDR_0_CNTRLR_CONFIG_DRAM_DEVICE_SIZE_1_Gb 2
-#define BCHP_MEMC_DDR_0_CNTRLR_CONFIG_DRAM_DEVICE_SIZE_2_Gb 3
-#define BCHP_MEMC_DDR_0_CNTRLR_CONFIG_DRAM_DEVICE_SIZE_4_Gb 4
-#define BCHP_MEMC_DDR_0_CNTRLR_CONFIG_DRAM_DEVICE_SIZE_8_Gb 5
-#define BCHP_MEMC_DDR_0_CNTRLR_CONFIG_DRAM_DEVICE_SIZE_16_Gb 6
-#define BCHP_MEMC_DDR_0_CNTRLR_CONFIG_DRAM_DEVICE_SIZE_reserved_7 7
-#define BCHP_MEMC_DDR_0_CNTRLR_CONFIG_DRAM_DEVICE_SIZE_reserved_8 8
-#define BCHP_MEMC_DDR_0_CNTRLR_CONFIG_DRAM_DEVICE_SIZE_reserved_9 9
-#define BCHP_MEMC_DDR_0_CNTRLR_CONFIG_DRAM_DEVICE_SIZE_reserved_10 10
-#define BCHP_MEMC_DDR_0_CNTRLR_CONFIG_DRAM_DEVICE_SIZE_reserved_11 11
-#define BCHP_MEMC_DDR_0_CNTRLR_CONFIG_DRAM_DEVICE_SIZE_reserved_12 12
-#define BCHP_MEMC_DDR_0_CNTRLR_CONFIG_DRAM_DEVICE_SIZE_reserved_13 13
-#define BCHP_MEMC_DDR_0_CNTRLR_CONFIG_DRAM_DEVICE_SIZE_reserved_14 14
-#define BCHP_MEMC_DDR_0_CNTRLR_CONFIG_DRAM_DEVICE_SIZE_reserved_15 15
-
-/* MEMC_DDR_0 :: CNTRLR_CONFIG :: DRAM_DEVICE_TYPE [03:00] */
-#define BCHP_MEMC_DDR_0_CNTRLR_CONFIG_DRAM_DEVICE_TYPE_MASK 0x0000000f
-#define BCHP_MEMC_DDR_0_CNTRLR_CONFIG_DRAM_DEVICE_TYPE_SHIFT 0
-#define BCHP_MEMC_DDR_0_CNTRLR_CONFIG_DRAM_DEVICE_TYPE_DEFAULT 0x00000001
-#define BCHP_MEMC_DDR_0_CNTRLR_CONFIG_DRAM_DEVICE_TYPE_reserved_DDR2 0
-#define BCHP_MEMC_DDR_0_CNTRLR_CONFIG_DRAM_DEVICE_TYPE_DDR3 1
-#define BCHP_MEMC_DDR_0_CNTRLR_CONFIG_DRAM_DEVICE_TYPE_DDR4 2
-#define BCHP_MEMC_DDR_0_CNTRLR_CONFIG_DRAM_DEVICE_TYPE_GDDR5M 3
-#define BCHP_MEMC_DDR_0_CNTRLR_CONFIG_DRAM_DEVICE_TYPE_GDDR5 4
-#define BCHP_MEMC_DDR_0_CNTRLR_CONFIG_DRAM_DEVICE_TYPE_reserved_5 5
-#define BCHP_MEMC_DDR_0_CNTRLR_CONFIG_DRAM_DEVICE_TYPE_reserved_6 6
-#define BCHP_MEMC_DDR_0_CNTRLR_CONFIG_DRAM_DEVICE_TYPE_reserved_7 7
-#define BCHP_MEMC_DDR_0_CNTRLR_CONFIG_DRAM_DEVICE_TYPE_reserved_8 8
-#define BCHP_MEMC_DDR_0_CNTRLR_CONFIG_DRAM_DEVICE_TYPE_reserved_9 9
-#define BCHP_MEMC_DDR_0_CNTRLR_CONFIG_DRAM_DEVICE_TYPE_reserved_10 10
-#define BCHP_MEMC_DDR_0_CNTRLR_CONFIG_DRAM_DEVICE_TYPE_reserved_11 11
-#define BCHP_MEMC_DDR_0_CNTRLR_CONFIG_DRAM_DEVICE_TYPE_reserved_12 12
-#define BCHP_MEMC_DDR_0_CNTRLR_CONFIG_DRAM_DEVICE_TYPE_reserved_13 13
-#define BCHP_MEMC_DDR_0_CNTRLR_CONFIG_DRAM_DEVICE_TYPE_reserved_14 14
-#define BCHP_MEMC_DDR_0_CNTRLR_CONFIG_DRAM_DEVICE_TYPE_reserved_15 15
-
-/***************************************************************************
- *CNTRLR_CONFIG_STATUS - Memory Controller Configuration Status Register
- ***************************************************************************/
-/* MEMC_DDR_0 :: CNTRLR_CONFIG_STATUS :: reserved0 [31:15] */
-#define BCHP_MEMC_DDR_0_CNTRLR_CONFIG_STATUS_reserved0_MASK 0xffff8000
-#define BCHP_MEMC_DDR_0_CNTRLR_CONFIG_STATUS_reserved0_SHIFT 15
-
-/* MEMC_DDR_0 :: CNTRLR_CONFIG_STATUS :: GROUPAGE_ENABLE [14:14] */
-#define BCHP_MEMC_DDR_0_CNTRLR_CONFIG_STATUS_GROUPAGE_ENABLE_MASK 0x00004000
-#define BCHP_MEMC_DDR_0_CNTRLR_CONFIG_STATUS_GROUPAGE_ENABLE_SHIFT 14
-#define BCHP_MEMC_DDR_0_CNTRLR_CONFIG_STATUS_GROUPAGE_ENABLE_DEFAULT 0x00000000
-
-/* MEMC_DDR_0 :: CNTRLR_CONFIG_STATUS :: MODIFY_RASTER_ADDR [13:13] */
-#define BCHP_MEMC_DDR_0_CNTRLR_CONFIG_STATUS_MODIFY_RASTER_ADDR_MASK 0x00002000
-#define BCHP_MEMC_DDR_0_CNTRLR_CONFIG_STATUS_MODIFY_RASTER_ADDR_SHIFT 13
-#define BCHP_MEMC_DDR_0_CNTRLR_CONFIG_STATUS_MODIFY_RASTER_ADDR_DEFAULT 0x00000001
-
-/* MEMC_DDR_0 :: CNTRLR_CONFIG_STATUS :: DRAM_COMMANDS_2T [12:12] */
-#define BCHP_MEMC_DDR_0_CNTRLR_CONFIG_STATUS_DRAM_COMMANDS_2T_MASK 0x00001000
-#define BCHP_MEMC_DDR_0_CNTRLR_CONFIG_STATUS_DRAM_COMMANDS_2T_SHIFT 12
-#define BCHP_MEMC_DDR_0_CNTRLR_CONFIG_STATUS_DRAM_COMMANDS_2T_DEFAULT 0x00000000
-
-/* MEMC_DDR_0 :: CNTRLR_CONFIG_STATUS :: DRAM_TOTAL_WIDTH [11:10] */
-#define BCHP_MEMC_DDR_0_CNTRLR_CONFIG_STATUS_DRAM_TOTAL_WIDTH_MASK 0x00000c00
-#define BCHP_MEMC_DDR_0_CNTRLR_CONFIG_STATUS_DRAM_TOTAL_WIDTH_SHIFT 10
-#define BCHP_MEMC_DDR_0_CNTRLR_CONFIG_STATUS_DRAM_TOTAL_WIDTH_DEFAULT 0x00000002
-#define BCHP_MEMC_DDR_0_CNTRLR_CONFIG_STATUS_DRAM_TOTAL_WIDTH_reserved_x8 0
-#define BCHP_MEMC_DDR_0_CNTRLR_CONFIG_STATUS_DRAM_TOTAL_WIDTH_x16 1
-#define BCHP_MEMC_DDR_0_CNTRLR_CONFIG_STATUS_DRAM_TOTAL_WIDTH_x32 2
-#define BCHP_MEMC_DDR_0_CNTRLR_CONFIG_STATUS_DRAM_TOTAL_WIDTH_reserved_x64 3
-
-/* MEMC_DDR_0 :: CNTRLR_CONFIG_STATUS :: DRAM_DEVICE_WIDTH [09:08] */
-#define BCHP_MEMC_DDR_0_CNTRLR_CONFIG_STATUS_DRAM_DEVICE_WIDTH_MASK 0x00000300
-#define BCHP_MEMC_DDR_0_CNTRLR_CONFIG_STATUS_DRAM_DEVICE_WIDTH_SHIFT 8
-#define BCHP_MEMC_DDR_0_CNTRLR_CONFIG_STATUS_DRAM_DEVICE_WIDTH_DEFAULT 0x00000001
-#define BCHP_MEMC_DDR_0_CNTRLR_CONFIG_STATUS_DRAM_DEVICE_WIDTH_x8 0
-#define BCHP_MEMC_DDR_0_CNTRLR_CONFIG_STATUS_DRAM_DEVICE_WIDTH_x16 1
-#define BCHP_MEMC_DDR_0_CNTRLR_CONFIG_STATUS_DRAM_DEVICE_WIDTH_reserved_2 2
-#define BCHP_MEMC_DDR_0_CNTRLR_CONFIG_STATUS_DRAM_DEVICE_WIDTH_reserved_3 3
-
-/* MEMC_DDR_0 :: CNTRLR_CONFIG_STATUS :: DRAM_DEVICE_SIZE [07:04] */
-#define BCHP_MEMC_DDR_0_CNTRLR_CONFIG_STATUS_DRAM_DEVICE_SIZE_MASK 0x000000f0
-#define BCHP_MEMC_DDR_0_CNTRLR_CONFIG_STATUS_DRAM_DEVICE_SIZE_SHIFT 4
-#define BCHP_MEMC_DDR_0_CNTRLR_CONFIG_STATUS_DRAM_DEVICE_SIZE_DEFAULT 0x00000003
-#define BCHP_MEMC_DDR_0_CNTRLR_CONFIG_STATUS_DRAM_DEVICE_SIZE_reserved_256_Mb 0
-#define BCHP_MEMC_DDR_0_CNTRLR_CONFIG_STATUS_DRAM_DEVICE_SIZE_512_Mb 1
-#define BCHP_MEMC_DDR_0_CNTRLR_CONFIG_STATUS_DRAM_DEVICE_SIZE_1_Gb 2
-#define BCHP_MEMC_DDR_0_CNTRLR_CONFIG_STATUS_DRAM_DEVICE_SIZE_2_Gb 3
-#define BCHP_MEMC_DDR_0_CNTRLR_CONFIG_STATUS_DRAM_DEVICE_SIZE_4_Gb 4
-#define BCHP_MEMC_DDR_0_CNTRLR_CONFIG_STATUS_DRAM_DEVICE_SIZE_8_Gb 5
-#define BCHP_MEMC_DDR_0_CNTRLR_CONFIG_STATUS_DRAM_DEVICE_SIZE_16_Gb 6
-#define BCHP_MEMC_DDR_0_CNTRLR_CONFIG_STATUS_DRAM_DEVICE_SIZE_reserved_7 7
-#define BCHP_MEMC_DDR_0_CNTRLR_CONFIG_STATUS_DRAM_DEVICE_SIZE_reserved_8 8
-#define BCHP_MEMC_DDR_0_CNTRLR_CONFIG_STATUS_DRAM_DEVICE_SIZE_reserved_9 9
-#define BCHP_MEMC_DDR_0_CNTRLR_CONFIG_STATUS_DRAM_DEVICE_SIZE_reserved_10 10
-#define BCHP_MEMC_DDR_0_CNTRLR_CONFIG_STATUS_DRAM_DEVICE_SIZE_reserved_11 11
-#define BCHP_MEMC_DDR_0_CNTRLR_CONFIG_STATUS_DRAM_DEVICE_SIZE_reserved_12 12
-#define BCHP_MEMC_DDR_0_CNTRLR_CONFIG_STATUS_DRAM_DEVICE_SIZE_reserved_13 13
-#define BCHP_MEMC_DDR_0_CNTRLR_CONFIG_STATUS_DRAM_DEVICE_SIZE_reserved_14 14
-#define BCHP_MEMC_DDR_0_CNTRLR_CONFIG_STATUS_DRAM_DEVICE_SIZE_reserved_15 15
-
-/* MEMC_DDR_0 :: CNTRLR_CONFIG_STATUS :: DRAM_DEVICE_TYPE [03:00] */
-#define BCHP_MEMC_DDR_0_CNTRLR_CONFIG_STATUS_DRAM_DEVICE_TYPE_MASK 0x0000000f
-#define BCHP_MEMC_DDR_0_CNTRLR_CONFIG_STATUS_DRAM_DEVICE_TYPE_SHIFT 0
-#define BCHP_MEMC_DDR_0_CNTRLR_CONFIG_STATUS_DRAM_DEVICE_TYPE_DEFAULT 0x00000001
-#define BCHP_MEMC_DDR_0_CNTRLR_CONFIG_STATUS_DRAM_DEVICE_TYPE_reserved_DDR2 0
-#define BCHP_MEMC_DDR_0_CNTRLR_CONFIG_STATUS_DRAM_DEVICE_TYPE_DDR3 1
-#define BCHP_MEMC_DDR_0_CNTRLR_CONFIG_STATUS_DRAM_DEVICE_TYPE_DDR4 2
-#define BCHP_MEMC_DDR_0_CNTRLR_CONFIG_STATUS_DRAM_DEVICE_TYPE_GDDR5M 3
-#define BCHP_MEMC_DDR_0_CNTRLR_CONFIG_STATUS_DRAM_DEVICE_TYPE_GDDR5 4
-#define BCHP_MEMC_DDR_0_CNTRLR_CONFIG_STATUS_DRAM_DEVICE_TYPE_reserved_5 5
-#define BCHP_MEMC_DDR_0_CNTRLR_CONFIG_STATUS_DRAM_DEVICE_TYPE_reserved_6 6
-#define BCHP_MEMC_DDR_0_CNTRLR_CONFIG_STATUS_DRAM_DEVICE_TYPE_reserved_7 7
-#define BCHP_MEMC_DDR_0_CNTRLR_CONFIG_STATUS_DRAM_DEVICE_TYPE_reserved_8 8
-#define BCHP_MEMC_DDR_0_CNTRLR_CONFIG_STATUS_DRAM_DEVICE_TYPE_reserved_9 9
-#define BCHP_MEMC_DDR_0_CNTRLR_CONFIG_STATUS_DRAM_DEVICE_TYPE_reserved_10 10
-#define BCHP_MEMC_DDR_0_CNTRLR_CONFIG_STATUS_DRAM_DEVICE_TYPE_reserved_11 11
-#define BCHP_MEMC_DDR_0_CNTRLR_CONFIG_STATUS_DRAM_DEVICE_TYPE_reserved_12 12
-#define BCHP_MEMC_DDR_0_CNTRLR_CONFIG_STATUS_DRAM_DEVICE_TYPE_reserved_13 13
-#define BCHP_MEMC_DDR_0_CNTRLR_CONFIG_STATUS_DRAM_DEVICE_TYPE_reserved_14 14
-#define BCHP_MEMC_DDR_0_CNTRLR_CONFIG_STATUS_DRAM_DEVICE_TYPE_reserved_15 15
-
-/***************************************************************************
- *DRAM_INIT_CNTRL - Dram initialization control
- ***************************************************************************/
-/* MEMC_DDR_0 :: DRAM_INIT_CNTRL :: reserved0 [31:06] */
-#define BCHP_MEMC_DDR_0_DRAM_INIT_CNTRL_reserved0_MASK 0xffffffc0
-#define BCHP_MEMC_DDR_0_DRAM_INIT_CNTRL_reserved0_SHIFT 6
-
-/* MEMC_DDR_0 :: DRAM_INIT_CNTRL :: IGNORE_PHY_REQUEST_AT_RESET [05:05] */
-#define BCHP_MEMC_DDR_0_DRAM_INIT_CNTRL_IGNORE_PHY_REQUEST_AT_RESET_MASK 0x00000020
-#define BCHP_MEMC_DDR_0_DRAM_INIT_CNTRL_IGNORE_PHY_REQUEST_AT_RESET_SHIFT 5
-#define BCHP_MEMC_DDR_0_DRAM_INIT_CNTRL_IGNORE_PHY_REQUEST_AT_RESET_DEFAULT 0x00000000
-
-/* MEMC_DDR_0 :: DRAM_INIT_CNTRL :: ENTER_PHY_OP_STATE [04:04] */
-#define BCHP_MEMC_DDR_0_DRAM_INIT_CNTRL_ENTER_PHY_OP_STATE_MASK 0x00000010
-#define BCHP_MEMC_DDR_0_DRAM_INIT_CNTRL_ENTER_PHY_OP_STATE_SHIFT 4
-#define BCHP_MEMC_DDR_0_DRAM_INIT_CNTRL_ENTER_PHY_OP_STATE_DEFAULT 0x00000000
-
-/* MEMC_DDR_0 :: DRAM_INIT_CNTRL :: ENABLE_AUTO_PHY_OP_ACCESS [03:03] */
-#define BCHP_MEMC_DDR_0_DRAM_INIT_CNTRL_ENABLE_AUTO_PHY_OP_ACCESS_MASK 0x00000008
-#define BCHP_MEMC_DDR_0_DRAM_INIT_CNTRL_ENABLE_AUTO_PHY_OP_ACCESS_SHIFT 3
-#define BCHP_MEMC_DDR_0_DRAM_INIT_CNTRL_ENABLE_AUTO_PHY_OP_ACCESS_DEFAULT 0x00000000
-
-/* MEMC_DDR_0 :: DRAM_INIT_CNTRL :: OVERRIDE_PHY_INIT_COMPLETE [02:02] */
-#define BCHP_MEMC_DDR_0_DRAM_INIT_CNTRL_OVERRIDE_PHY_INIT_COMPLETE_MASK 0x00000004
-#define BCHP_MEMC_DDR_0_DRAM_INIT_CNTRL_OVERRIDE_PHY_INIT_COMPLETE_SHIFT 2
-#define BCHP_MEMC_DDR_0_DRAM_INIT_CNTRL_OVERRIDE_PHY_INIT_COMPLETE_DEFAULT 0x00000000
-
-/* MEMC_DDR_0 :: DRAM_INIT_CNTRL :: OVERRIDE_PHY_DFI_GRANT [01:01] */
-#define BCHP_MEMC_DDR_0_DRAM_INIT_CNTRL_OVERRIDE_PHY_DFI_GRANT_MASK 0x00000002
-#define BCHP_MEMC_DDR_0_DRAM_INIT_CNTRL_OVERRIDE_PHY_DFI_GRANT_SHIFT 1
-#define BCHP_MEMC_DDR_0_DRAM_INIT_CNTRL_OVERRIDE_PHY_DFI_GRANT_DEFAULT 0x00000000
-
-/* MEMC_DDR_0 :: DRAM_INIT_CNTRL :: PHY_DFI_GRANT_VALUE [00:00] */
-#define BCHP_MEMC_DDR_0_DRAM_INIT_CNTRL_PHY_DFI_GRANT_VALUE_MASK 0x00000001
-#define BCHP_MEMC_DDR_0_DRAM_INIT_CNTRL_PHY_DFI_GRANT_VALUE_SHIFT 0
-#define BCHP_MEMC_DDR_0_DRAM_INIT_CNTRL_PHY_DFI_GRANT_VALUE_DEFAULT 0x00000000
-
-/***************************************************************************
- *DRAM_INIT_STATUS - Dram initialization status
- ***************************************************************************/
-/* MEMC_DDR_0 :: DRAM_INIT_STATUS :: reserved0 [31:03] */
-#define BCHP_MEMC_DDR_0_DRAM_INIT_STATUS_reserved0_MASK 0xfffffff8
-#define BCHP_MEMC_DDR_0_DRAM_INIT_STATUS_reserved0_SHIFT 3
-
-/* MEMC_DDR_0 :: DRAM_INIT_STATUS :: INIT_CLIENT_BUSY [02:02] */
-#define BCHP_MEMC_DDR_0_DRAM_INIT_STATUS_INIT_CLIENT_BUSY_MASK 0x00000004
-#define BCHP_MEMC_DDR_0_DRAM_INIT_STATUS_INIT_CLIENT_BUSY_SHIFT 2
-#define BCHP_MEMC_DDR_0_DRAM_INIT_STATUS_INIT_CLIENT_BUSY_DEFAULT 0x00000000
-
-/* MEMC_DDR_0 :: DRAM_INIT_STATUS :: PHY_DFI_REQUEST_VALUE [01:01] */
-#define BCHP_MEMC_DDR_0_DRAM_INIT_STATUS_PHY_DFI_REQUEST_VALUE_MASK 0x00000002
-#define BCHP_MEMC_DDR_0_DRAM_INIT_STATUS_PHY_DFI_REQUEST_VALUE_SHIFT 1
-#define BCHP_MEMC_DDR_0_DRAM_INIT_STATUS_PHY_DFI_REQUEST_VALUE_DEFAULT 0x00000000
-
-/* MEMC_DDR_0 :: DRAM_INIT_STATUS :: INIT_DONE [00:00] */
-#define BCHP_MEMC_DDR_0_DRAM_INIT_STATUS_INIT_DONE_MASK 0x00000001
-#define BCHP_MEMC_DDR_0_DRAM_INIT_STATUS_INIT_DONE_SHIFT 0
-#define BCHP_MEMC_DDR_0_DRAM_INIT_STATUS_INIT_DONE_DEFAULT 0x00000000
-
-/***************************************************************************
- *DRAM_MODE_0 - Dram Mode Register 0
- ***************************************************************************/
-/* MEMC_DDR_0 :: DRAM_MODE_0 :: reserved0 [31:16] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_0_reserved0_MASK 0xffff0000
-#define BCHP_MEMC_DDR_0_DRAM_MODE_0_reserved0_SHIFT 16
-
-/* MEMC_DDR_0 :: DRAM_MODE_0 :: unused_0 [15:13] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_0_unused_0_MASK 0x0000e000
-#define BCHP_MEMC_DDR_0_DRAM_MODE_0_unused_0_SHIFT 13
-#define BCHP_MEMC_DDR_0_DRAM_MODE_0_unused_0_DEFAULT 0x00000000
-
-/* union - case DDR3 [12:00] */
-/* MEMC_DDR_0 :: DRAM_MODE_0 :: DDR3 :: DLL_CNTRL_PPD [12:12] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR3_DLL_CNTRL_PPD_MASK 0x00001000
-#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR3_DLL_CNTRL_PPD_SHIFT 12
-#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR3_DLL_CNTRL_PPD_DEFAULT 0x00000000
-
-/* MEMC_DDR_0 :: DRAM_MODE_0 :: DDR3 :: WR [11:09] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR3_WR_MASK 0x00000e00
-#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR3_WR_SHIFT 9
-#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR3_WR_DEFAULT 0x00000004
-
-/* MEMC_DDR_0 :: DRAM_MODE_0 :: DDR3 :: DLL_RST [08:08] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR3_DLL_RST_MASK 0x00000100
-#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR3_DLL_RST_SHIFT 8
-#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR3_DLL_RST_DEFAULT 0x00000000
-
-/* MEMC_DDR_0 :: DRAM_MODE_0 :: DDR3 :: TEST_MODE [07:07] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR3_TEST_MODE_MASK 0x00000080
-#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR3_TEST_MODE_SHIFT 7
-#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR3_TEST_MODE_DEFAULT 0x00000000
-
-/* MEMC_DDR_0 :: DRAM_MODE_0 :: DDR3 :: CL_3_1 [06:04] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR3_CL_3_1_MASK 0x00000070
-#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR3_CL_3_1_SHIFT 4
-#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR3_CL_3_1_DEFAULT 0x00000004
-
-/* MEMC_DDR_0 :: DRAM_MODE_0 :: DDR3 :: RBT [03:03] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR3_RBT_MASK 0x00000008
-#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR3_RBT_SHIFT 3
-#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR3_RBT_DEFAULT 0x00000000
-
-/* MEMC_DDR_0 :: DRAM_MODE_0 :: DDR3 :: CL_0 [02:02] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR3_CL_0_MASK 0x00000004
-#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR3_CL_0_SHIFT 2
-#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR3_CL_0_DEFAULT 0x00000000
-
-/* MEMC_DDR_0 :: DRAM_MODE_0 :: DDR3 :: BL [01:00] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR3_BL_MASK 0x00000003
-#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR3_BL_SHIFT 0
-#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR3_BL_DEFAULT 0x00000000
-
-/* union - case DDR4 [12:00] */
-/* MEMC_DDR_0 :: DRAM_MODE_0 :: DDR4 :: unused_1 [12:12] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR4_unused_1_MASK 0x00001000
-#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR4_unused_1_SHIFT 12
-#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR4_unused_1_DEFAULT 0x00000000
-
-/* MEMC_DDR_0 :: DRAM_MODE_0 :: DDR4 :: WR [11:09] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR4_WR_MASK 0x00000e00
-#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR4_WR_SHIFT 9
-#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR4_WR_DEFAULT 0x00000004
-
-/* MEMC_DDR_0 :: DRAM_MODE_0 :: DDR4 :: DLL_RST [08:08] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR4_DLL_RST_MASK 0x00000100
-#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR4_DLL_RST_SHIFT 8
-#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR4_DLL_RST_DEFAULT 0x00000000
-
-/* MEMC_DDR_0 :: DRAM_MODE_0 :: DDR4 :: TEST_MODE [07:07] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR4_TEST_MODE_MASK 0x00000080
-#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR4_TEST_MODE_SHIFT 7
-#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR4_TEST_MODE_DEFAULT 0x00000000
-
-/* MEMC_DDR_0 :: DRAM_MODE_0 :: DDR4 :: CL_3_1 [06:04] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR4_CL_3_1_MASK 0x00000070
-#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR4_CL_3_1_SHIFT 4
-#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR4_CL_3_1_DEFAULT 0x00000004
-
-/* MEMC_DDR_0 :: DRAM_MODE_0 :: DDR4 :: BT [03:03] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR4_BT_MASK 0x00000008
-#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR4_BT_SHIFT 3
-#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR4_BT_DEFAULT 0x00000000
-
-/* MEMC_DDR_0 :: DRAM_MODE_0 :: DDR4 :: CL_0 [02:02] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR4_CL_0_MASK 0x00000004
-#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR4_CL_0_SHIFT 2
-#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR4_CL_0_DEFAULT 0x00000000
-
-/* MEMC_DDR_0 :: DRAM_MODE_0 :: DDR4 :: BL [01:00] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR4_BL_MASK 0x00000003
-#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR4_BL_SHIFT 0
-#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR4_BL_DEFAULT 0x00000000
-
-/* union - case GDDR5M [12:00] */
-/* MEMC_DDR_0 :: DRAM_MODE_0 :: GDDR5M :: unused_1 [12:12] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_0_GDDR5M_unused_1_MASK 0x00001000
-#define BCHP_MEMC_DDR_0_DRAM_MODE_0_GDDR5M_unused_1_SHIFT 12
-#define BCHP_MEMC_DDR_0_DRAM_MODE_0_GDDR5M_unused_1_DEFAULT 0x00000000
-
-/* MEMC_DDR_0 :: DRAM_MODE_0 :: GDDR5M :: WR [11:08] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_0_GDDR5M_WR_MASK 0x00000f00
-#define BCHP_MEMC_DDR_0_DRAM_MODE_0_GDDR5M_WR_SHIFT 8
-#define BCHP_MEMC_DDR_0_DRAM_MODE_0_GDDR5M_WR_DEFAULT 0x00000008
-
-/* MEMC_DDR_0 :: DRAM_MODE_0 :: GDDR5M :: TEST_MODE [07:07] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_0_GDDR5M_TEST_MODE_MASK 0x00000080
-#define BCHP_MEMC_DDR_0_DRAM_MODE_0_GDDR5M_TEST_MODE_SHIFT 7
-#define BCHP_MEMC_DDR_0_DRAM_MODE_0_GDDR5M_TEST_MODE_DEFAULT 0x00000000
-
-/* MEMC_DDR_0 :: DRAM_MODE_0 :: GDDR5M :: CL [06:03] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_0_GDDR5M_CL_MASK 0x00000078
-#define BCHP_MEMC_DDR_0_DRAM_MODE_0_GDDR5M_CL_SHIFT 3
-#define BCHP_MEMC_DDR_0_DRAM_MODE_0_GDDR5M_CL_DEFAULT 0x00000009
-
-/* MEMC_DDR_0 :: DRAM_MODE_0 :: GDDR5M :: WL [02:00] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_0_GDDR5M_WL_MASK 0x00000007
-#define BCHP_MEMC_DDR_0_DRAM_MODE_0_GDDR5M_WL_SHIFT 0
-#define BCHP_MEMC_DDR_0_DRAM_MODE_0_GDDR5M_WL_DEFAULT 0x00000004
-
-/* union - case GDDR5 [12:00] */
-/* MEMC_DDR_0 :: DRAM_MODE_0 :: GDDR5 :: unused_1 [12:12] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_0_GDDR5_unused_1_MASK 0x00001000
-#define BCHP_MEMC_DDR_0_DRAM_MODE_0_GDDR5_unused_1_SHIFT 12
-#define BCHP_MEMC_DDR_0_DRAM_MODE_0_GDDR5_unused_1_DEFAULT 0x00000000
-
-/* MEMC_DDR_0 :: DRAM_MODE_0 :: GDDR5 :: WR [11:08] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_0_GDDR5_WR_MASK 0x00000f00
-#define BCHP_MEMC_DDR_0_DRAM_MODE_0_GDDR5_WR_SHIFT 8
-#define BCHP_MEMC_DDR_0_DRAM_MODE_0_GDDR5_WR_DEFAULT 0x00000008
-
-/* MEMC_DDR_0 :: DRAM_MODE_0 :: GDDR5 :: TEST_MODE [07:07] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_0_GDDR5_TEST_MODE_MASK 0x00000080
-#define BCHP_MEMC_DDR_0_DRAM_MODE_0_GDDR5_TEST_MODE_SHIFT 7
-#define BCHP_MEMC_DDR_0_DRAM_MODE_0_GDDR5_TEST_MODE_DEFAULT 0x00000000
-
-/* MEMC_DDR_0 :: DRAM_MODE_0 :: GDDR5 :: CL [06:03] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_0_GDDR5_CL_MASK 0x00000078
-#define BCHP_MEMC_DDR_0_DRAM_MODE_0_GDDR5_CL_SHIFT 3
-#define BCHP_MEMC_DDR_0_DRAM_MODE_0_GDDR5_CL_DEFAULT 0x00000009
-
-/* MEMC_DDR_0 :: DRAM_MODE_0 :: GDDR5 :: WL [02:00] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_0_GDDR5_WL_MASK 0x00000007
-#define BCHP_MEMC_DDR_0_DRAM_MODE_0_GDDR5_WL_SHIFT 0
-#define BCHP_MEMC_DDR_0_DRAM_MODE_0_GDDR5_WL_DEFAULT 0x00000004
-
-/***************************************************************************
- *DRAM_MODE_1 - Dram Mode Register 1
- ***************************************************************************/
-/* MEMC_DDR_0 :: DRAM_MODE_1 :: reserved0 [31:16] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_1_reserved0_MASK 0xffff0000
-#define BCHP_MEMC_DDR_0_DRAM_MODE_1_reserved0_SHIFT 16
-
-/* MEMC_DDR_0 :: DRAM_MODE_1 :: unused_0 [15:13] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_1_unused_0_MASK 0x0000e000
-#define BCHP_MEMC_DDR_0_DRAM_MODE_1_unused_0_SHIFT 13
-#define BCHP_MEMC_DDR_0_DRAM_MODE_1_unused_0_DEFAULT 0x00000000
-
-/* union - case DDR3 [12:00] */
-/* MEMC_DDR_0 :: DRAM_MODE_1 :: DDR3 :: Q_OFF [12:12] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_Q_OFF_MASK 0x00001000
-#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_Q_OFF_SHIFT 12
-#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_Q_OFF_DEFAULT 0x00000000
-#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_Q_OFF_ENABLE 0
-#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_Q_OFF_DISABLE 1
-
-/* MEMC_DDR_0 :: DRAM_MODE_1 :: DDR3 :: TDQS [11:11] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_TDQS_MASK 0x00000800
-#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_TDQS_SHIFT 11
-#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_TDQS_DEFAULT 0x00000000
-#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_TDQS_ENABLE 1
-#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_TDQS_DISABLE 0
-
-/* MEMC_DDR_0 :: DRAM_MODE_1 :: DDR3 :: unused_1 [10:10] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_unused_1_MASK 0x00000400
-#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_unused_1_SHIFT 10
-#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_unused_1_DEFAULT 0x00000000
-
-/* MEMC_DDR_0 :: DRAM_MODE_1 :: DDR3 :: ODT_CNTRL_2 [09:09] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_ODT_CNTRL_2_MASK 0x00000200
-#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_ODT_CNTRL_2_SHIFT 9
-#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_ODT_CNTRL_2_DEFAULT 0x00000000
-
-/* MEMC_DDR_0 :: DRAM_MODE_1 :: DDR3 :: unused_2 [08:08] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_unused_2_MASK 0x00000100
-#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_unused_2_SHIFT 8
-#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_unused_2_DEFAULT 0x00000000
-
-/* MEMC_DDR_0 :: DRAM_MODE_1 :: DDR3 :: WR_LEVEL [07:07] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_WR_LEVEL_MASK 0x00000080
-#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_WR_LEVEL_SHIFT 7
-#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_WR_LEVEL_DEFAULT 0x00000000
-#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_WR_LEVEL_ENABLE 1
-#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_WR_LEVEL_DISABLE 0
-
-/* MEMC_DDR_0 :: DRAM_MODE_1 :: DDR3 :: ODT_CNTRL_1 [06:06] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_ODT_CNTRL_1_MASK 0x00000040
-#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_ODT_CNTRL_1_SHIFT 6
-#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_ODT_CNTRL_1_DEFAULT 0x00000000
-
-/* MEMC_DDR_0 :: DRAM_MODE_1 :: DDR3 :: DRIVER_IMP_CNTRL_1 [05:05] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_DRIVER_IMP_CNTRL_1_MASK 0x00000020
-#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_DRIVER_IMP_CNTRL_1_SHIFT 5
-#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_DRIVER_IMP_CNTRL_1_DEFAULT 0x00000000
-
-/* MEMC_DDR_0 :: DRAM_MODE_1 :: DDR3 :: AL [04:03] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_AL_MASK 0x00000018
-#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_AL_SHIFT 3
-#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_AL_DEFAULT 0x00000001
-
-/* MEMC_DDR_0 :: DRAM_MODE_1 :: DDR3 :: ODT_CNTRL_0 [02:02] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_ODT_CNTRL_0_MASK 0x00000004
-#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_ODT_CNTRL_0_SHIFT 2
-#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_ODT_CNTRL_0_DEFAULT 0x00000001
-
-/* MEMC_DDR_0 :: DRAM_MODE_1 :: DDR3 :: DRIVER_IMP_CNTRL_0 [01:01] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_DRIVER_IMP_CNTRL_0_MASK 0x00000002
-#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_DRIVER_IMP_CNTRL_0_SHIFT 1
-#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_DRIVER_IMP_CNTRL_0_DEFAULT 0x00000000
-
-/* MEMC_DDR_0 :: DRAM_MODE_1 :: DDR3 :: DLL_EN [00:00] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_DLL_EN_MASK 0x00000001
-#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_DLL_EN_SHIFT 0
-#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_DLL_EN_DEFAULT 0x00000000
-#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_DLL_EN_ENABLE 0
-#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_DLL_EN_DISABLE 1
-
-/* union - case DDR4 [12:00] */
-/* MEMC_DDR_0 :: DRAM_MODE_1 :: DDR4 :: Q_OFF [12:12] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR4_Q_OFF_MASK 0x00001000
-#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR4_Q_OFF_SHIFT 12
-#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR4_Q_OFF_DEFAULT 0x00000000
-#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR4_Q_OFF_ENABLE 0
-#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR4_Q_OFF_DISABLE 1
-
-/* MEMC_DDR_0 :: DRAM_MODE_1 :: DDR4 :: TDQS [11:11] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR4_TDQS_MASK 0x00000800
-#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR4_TDQS_SHIFT 11
-#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR4_TDQS_DEFAULT 0x00000000
-#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR4_TDQS_ENABLE 1
-#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR4_TDQS_DISABLE 0
-
-/* MEMC_DDR_0 :: DRAM_MODE_1 :: DDR4 :: RTT_NOM [10:08] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR4_RTT_NOM_MASK 0x00000700
-#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR4_RTT_NOM_SHIFT 8
-#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR4_RTT_NOM_DEFAULT 0x00000000
-
-/* MEMC_DDR_0 :: DRAM_MODE_1 :: DDR4 :: WR_LEVEL [07:07] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR4_WR_LEVEL_MASK 0x00000080
-#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR4_WR_LEVEL_SHIFT 7
-#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR4_WR_LEVEL_DEFAULT 0x00000000
-#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR4_WR_LEVEL_ENABLE 1
-#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR4_WR_LEVEL_DISABLE 0
-
-/* MEMC_DDR_0 :: DRAM_MODE_1 :: DDR4 :: unused [06:05] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR4_unused_MASK 0x00000060
-#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR4_unused_SHIFT 5
-#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR4_unused_DEFAULT 0x00000000
-
-/* MEMC_DDR_0 :: DRAM_MODE_1 :: DDR4 :: AL [04:03] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR4_AL_MASK 0x00000018
-#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR4_AL_SHIFT 3
-#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR4_AL_DEFAULT 0x00000001
-
-/* MEMC_DDR_0 :: DRAM_MODE_1 :: DDR4 :: DRIVER_IMP_CNTRL [02:01] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR4_DRIVER_IMP_CNTRL_MASK 0x00000006
-#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR4_DRIVER_IMP_CNTRL_SHIFT 1
-#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR4_DRIVER_IMP_CNTRL_DEFAULT 0x00000000
-
-/* MEMC_DDR_0 :: DRAM_MODE_1 :: DDR4 :: DLL_EN [00:00] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR4_DLL_EN_MASK 0x00000001
-#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR4_DLL_EN_SHIFT 0
-#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR4_DLL_EN_DEFAULT 0x00000000
-#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR4_DLL_EN_ENABLE 0
-#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR4_DLL_EN_DISABLE 1
-
-/* union - case GDDR5M [12:00] */
-/* MEMC_DDR_0 :: DRAM_MODE_1 :: GDDR5M :: unused_1 [12:11] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_1_GDDR5M_unused_1_MASK 0x00001800
-#define BCHP_MEMC_DDR_0_DRAM_MODE_1_GDDR5M_unused_1_SHIFT 11
-#define BCHP_MEMC_DDR_0_DRAM_MODE_1_GDDR5M_unused_1_DEFAULT 0x00000000
-
-/* MEMC_DDR_0 :: DRAM_MODE_1 :: GDDR5M :: ABI [10:10] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_1_GDDR5M_ABI_MASK 0x00000400
-#define BCHP_MEMC_DDR_0_DRAM_MODE_1_GDDR5M_ABI_SHIFT 10
-#define BCHP_MEMC_DDR_0_DRAM_MODE_1_GDDR5M_ABI_DEFAULT 0x00000000
-#define BCHP_MEMC_DDR_0_DRAM_MODE_1_GDDR5M_ABI_ENABLE 0
-#define BCHP_MEMC_DDR_0_DRAM_MODE_1_GDDR5M_ABI_DISABLE 1
-
-/* MEMC_DDR_0 :: DRAM_MODE_1 :: GDDR5M :: WDBI [09:09] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_1_GDDR5M_WDBI_MASK 0x00000200
-#define BCHP_MEMC_DDR_0_DRAM_MODE_1_GDDR5M_WDBI_SHIFT 9
-#define BCHP_MEMC_DDR_0_DRAM_MODE_1_GDDR5M_WDBI_DEFAULT 0x00000000
-#define BCHP_MEMC_DDR_0_DRAM_MODE_1_GDDR5M_WDBI_ENABLE 0
-#define BCHP_MEMC_DDR_0_DRAM_MODE_1_GDDR5M_WDBI_DISABLE 1
-
-/* MEMC_DDR_0 :: DRAM_MODE_1 :: GDDR5M :: RDBI [08:08] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_1_GDDR5M_RDBI_MASK 0x00000100
-#define BCHP_MEMC_DDR_0_DRAM_MODE_1_GDDR5M_RDBI_SHIFT 8
-#define BCHP_MEMC_DDR_0_DRAM_MODE_1_GDDR5M_RDBI_DEFAULT 0x00000000
-#define BCHP_MEMC_DDR_0_DRAM_MODE_1_GDDR5M_RDBI_ENABLE 0
-#define BCHP_MEMC_DDR_0_DRAM_MODE_1_GDDR5M_RDBI_DISABLE 1
-
-/* MEMC_DDR_0 :: DRAM_MODE_1 :: GDDR5M :: unused_2 [07:07] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_1_GDDR5M_unused_2_MASK 0x00000080
-#define BCHP_MEMC_DDR_0_DRAM_MODE_1_GDDR5M_unused_2_SHIFT 7
-#define BCHP_MEMC_DDR_0_DRAM_MODE_1_GDDR5M_unused_2_DEFAULT 0x00000000
-
-/* MEMC_DDR_0 :: DRAM_MODE_1 :: GDDR5M :: CAL_UPD [06:06] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_1_GDDR5M_CAL_UPD_MASK 0x00000040
-#define BCHP_MEMC_DDR_0_DRAM_MODE_1_GDDR5M_CAL_UPD_SHIFT 6
-#define BCHP_MEMC_DDR_0_DRAM_MODE_1_GDDR5M_CAL_UPD_DEFAULT 0x00000000
-#define BCHP_MEMC_DDR_0_DRAM_MODE_1_GDDR5M_CAL_UPD_ENABLE 0
-#define BCHP_MEMC_DDR_0_DRAM_MODE_1_GDDR5M_CAL_UPD_DISABLE 1
-
-/* MEMC_DDR_0 :: DRAM_MODE_1 :: GDDR5M :: ADDR_CMD_TERM [05:04] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_1_GDDR5M_ADDR_CMD_TERM_MASK 0x00000030
-#define BCHP_MEMC_DDR_0_DRAM_MODE_1_GDDR5M_ADDR_CMD_TERM_SHIFT 4
-#define BCHP_MEMC_DDR_0_DRAM_MODE_1_GDDR5M_ADDR_CMD_TERM_DEFAULT 0x00000000
-
-/* MEMC_DDR_0 :: DRAM_MODE_1 :: GDDR5M :: DATA_TERM [03:02] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_1_GDDR5M_DATA_TERM_MASK 0x0000000c
-#define BCHP_MEMC_DDR_0_DRAM_MODE_1_GDDR5M_DATA_TERM_SHIFT 2
-#define BCHP_MEMC_DDR_0_DRAM_MODE_1_GDDR5M_DATA_TERM_DEFAULT 0x00000000
-
-/* MEMC_DDR_0 :: DRAM_MODE_1 :: GDDR5M :: DRIVER_STRENGTH [01:00] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_1_GDDR5M_DRIVER_STRENGTH_MASK 0x00000003
-#define BCHP_MEMC_DDR_0_DRAM_MODE_1_GDDR5M_DRIVER_STRENGTH_SHIFT 0
-#define BCHP_MEMC_DDR_0_DRAM_MODE_1_GDDR5M_DRIVER_STRENGTH_DEFAULT 0x00000000
-
-/* union - case GDDR5 [12:00] */
-/* MEMC_DDR_0 :: DRAM_MODE_1 :: GDDR5 :: unused_1 [12:12] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_1_GDDR5_unused_1_MASK 0x00001000
-#define BCHP_MEMC_DDR_0_DRAM_MODE_1_GDDR5_unused_1_SHIFT 12
-#define BCHP_MEMC_DDR_0_DRAM_MODE_1_GDDR5_unused_1_DEFAULT 0x00000000
-
-/* MEMC_DDR_0 :: DRAM_MODE_1 :: GDDR5 :: PLL_DLL_RST [11:11] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_1_GDDR5_PLL_DLL_RST_MASK 0x00000800
-#define BCHP_MEMC_DDR_0_DRAM_MODE_1_GDDR5_PLL_DLL_RST_SHIFT 11
-#define BCHP_MEMC_DDR_0_DRAM_MODE_1_GDDR5_PLL_DLL_RST_DEFAULT 0x00000000
-
-/* MEMC_DDR_0 :: DRAM_MODE_1 :: GDDR5 :: ABI [10:10] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_1_GDDR5_ABI_MASK 0x00000400
-#define BCHP_MEMC_DDR_0_DRAM_MODE_1_GDDR5_ABI_SHIFT 10
-#define BCHP_MEMC_DDR_0_DRAM_MODE_1_GDDR5_ABI_DEFAULT 0x00000000
-#define BCHP_MEMC_DDR_0_DRAM_MODE_1_GDDR5_ABI_ENABLE 0
-#define BCHP_MEMC_DDR_0_DRAM_MODE_1_GDDR5_ABI_DISABLE 1
-
-/* MEMC_DDR_0 :: DRAM_MODE_1 :: GDDR5 :: WDBI [09:09] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_1_GDDR5_WDBI_MASK 0x00000200
-#define BCHP_MEMC_DDR_0_DRAM_MODE_1_GDDR5_WDBI_SHIFT 9
-#define BCHP_MEMC_DDR_0_DRAM_MODE_1_GDDR5_WDBI_DEFAULT 0x00000000
-#define BCHP_MEMC_DDR_0_DRAM_MODE_1_GDDR5_WDBI_ENABLE 0
-#define BCHP_MEMC_DDR_0_DRAM_MODE_1_GDDR5_WDBI_DISABLE 1
-
-/* MEMC_DDR_0 :: DRAM_MODE_1 :: GDDR5 :: RDBI [08:08] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_1_GDDR5_RDBI_MASK 0x00000100
-#define BCHP_MEMC_DDR_0_DRAM_MODE_1_GDDR5_RDBI_SHIFT 8
-#define BCHP_MEMC_DDR_0_DRAM_MODE_1_GDDR5_RDBI_DEFAULT 0x00000000
-#define BCHP_MEMC_DDR_0_DRAM_MODE_1_GDDR5_RDBI_ENABLE 0
-#define BCHP_MEMC_DDR_0_DRAM_MODE_1_GDDR5_RDBI_DISABLE 1
-
-/* MEMC_DDR_0 :: DRAM_MODE_1 :: GDDR5 :: PLL_DLL [07:07] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_1_GDDR5_PLL_DLL_MASK 0x00000080
-#define BCHP_MEMC_DDR_0_DRAM_MODE_1_GDDR5_PLL_DLL_SHIFT 7
-#define BCHP_MEMC_DDR_0_DRAM_MODE_1_GDDR5_PLL_DLL_DEFAULT 0x00000000
-
-/* MEMC_DDR_0 :: DRAM_MODE_1 :: GDDR5 :: CAL_UPD [06:06] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_1_GDDR5_CAL_UPD_MASK 0x00000040
-#define BCHP_MEMC_DDR_0_DRAM_MODE_1_GDDR5_CAL_UPD_SHIFT 6
-#define BCHP_MEMC_DDR_0_DRAM_MODE_1_GDDR5_CAL_UPD_DEFAULT 0x00000000
-#define BCHP_MEMC_DDR_0_DRAM_MODE_1_GDDR5_CAL_UPD_ENABLE 0
-#define BCHP_MEMC_DDR_0_DRAM_MODE_1_GDDR5_CAL_UPD_DISABLE 1
-
-/* MEMC_DDR_0 :: DRAM_MODE_1 :: GDDR5 :: ADDR_CMD_TERM [05:04] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_1_GDDR5_ADDR_CMD_TERM_MASK 0x00000030
-#define BCHP_MEMC_DDR_0_DRAM_MODE_1_GDDR5_ADDR_CMD_TERM_SHIFT 4
-#define BCHP_MEMC_DDR_0_DRAM_MODE_1_GDDR5_ADDR_CMD_TERM_DEFAULT 0x00000000
-
-/* MEMC_DDR_0 :: DRAM_MODE_1 :: GDDR5 :: DATA_TERM [03:02] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_1_GDDR5_DATA_TERM_MASK 0x0000000c
-#define BCHP_MEMC_DDR_0_DRAM_MODE_1_GDDR5_DATA_TERM_SHIFT 2
-#define BCHP_MEMC_DDR_0_DRAM_MODE_1_GDDR5_DATA_TERM_DEFAULT 0x00000000
-
-/* MEMC_DDR_0 :: DRAM_MODE_1 :: GDDR5 :: DRIVER_STRENGTH [01:00] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_1_GDDR5_DRIVER_STRENGTH_MASK 0x00000003
-#define BCHP_MEMC_DDR_0_DRAM_MODE_1_GDDR5_DRIVER_STRENGTH_SHIFT 0
-#define BCHP_MEMC_DDR_0_DRAM_MODE_1_GDDR5_DRIVER_STRENGTH_DEFAULT 0x00000000
-
-/***************************************************************************
- *DRAM_MODE_2 - Dram Mode Register 2
- ***************************************************************************/
-/* MEMC_DDR_0 :: DRAM_MODE_2 :: reserved0 [31:16] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_2_reserved0_MASK 0xffff0000
-#define BCHP_MEMC_DDR_0_DRAM_MODE_2_reserved0_SHIFT 16
-
-/* MEMC_DDR_0 :: DRAM_MODE_2 :: unused_0 [15:13] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_2_unused_0_MASK 0x0000e000
-#define BCHP_MEMC_DDR_0_DRAM_MODE_2_unused_0_SHIFT 13
-#define BCHP_MEMC_DDR_0_DRAM_MODE_2_unused_0_DEFAULT 0x00000000
-
-/* union - case DDR3 [12:00] */
-/* MEMC_DDR_0 :: DRAM_MODE_2 :: DDR3 :: unused_1 [12:11] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR3_unused_1_MASK 0x00001800
-#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR3_unused_1_SHIFT 11
-#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR3_unused_1_DEFAULT 0x00000000
-
-/* MEMC_DDR_0 :: DRAM_MODE_2 :: DDR3 :: WR_ODT [10:09] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR3_WR_ODT_MASK 0x00000600
-#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR3_WR_ODT_SHIFT 9
-#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR3_WR_ODT_DEFAULT 0x00000001
-
-/* MEMC_DDR_0 :: DRAM_MODE_2 :: DDR3 :: unused_2 [08:08] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR3_unused_2_MASK 0x00000100
-#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR3_unused_2_SHIFT 8
-#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR3_unused_2_DEFAULT 0x00000000
-
-/* MEMC_DDR_0 :: DRAM_MODE_2 :: DDR3 :: SRF_TR [07:07] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR3_SRF_TR_MASK 0x00000080
-#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR3_SRF_TR_SHIFT 7
-#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR3_SRF_TR_DEFAULT 0x00000000
-
-/* MEMC_DDR_0 :: DRAM_MODE_2 :: DDR3 :: AUTO_SR [06:06] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR3_AUTO_SR_MASK 0x00000040
-#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR3_AUTO_SR_SHIFT 6
-#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR3_AUTO_SR_DEFAULT 0x00000001
-
-/* MEMC_DDR_0 :: DRAM_MODE_2 :: DDR3 :: WCL [05:03] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR3_WCL_MASK 0x00000038
-#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR3_WCL_SHIFT 3
-#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR3_WCL_DEFAULT 0x00000001
-
-/* MEMC_DDR_0 :: DRAM_MODE_2 :: DDR3 :: PASR [02:00] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR3_PASR_MASK 0x00000007
-#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR3_PASR_SHIFT 0
-#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR3_PASR_DEFAULT 0x00000000
-
-/* union - case DDR4 [12:00] */
-/* MEMC_DDR_0 :: DRAM_MODE_2 :: DDR4 :: WR_DATA_CRC [12:12] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR4_WR_DATA_CRC_MASK 0x00001000
-#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR4_WR_DATA_CRC_SHIFT 12
-#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR4_WR_DATA_CRC_DEFAULT 0x00000000
-#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR4_WR_DATA_CRC_ENABLE 1
-#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR4_WR_DATA_CRC_DISABLE 0
-
-/* MEMC_DDR_0 :: DRAM_MODE_2 :: DDR4 :: unused_2 [11:11] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR4_unused_2_MASK 0x00000800
-#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR4_unused_2_SHIFT 11
-#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR4_unused_2_DEFAULT 0x00000000
-
-/* MEMC_DDR_0 :: DRAM_MODE_2 :: DDR4 :: RTT_WR [10:09] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR4_RTT_WR_MASK 0x00000600
-#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR4_RTT_WR_SHIFT 9
-#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR4_RTT_WR_DEFAULT 0x00000001
-
-/* MEMC_DDR_0 :: DRAM_MODE_2 :: DDR4 :: unused_1 [08:08] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR4_unused_1_MASK 0x00000100
-#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR4_unused_1_SHIFT 8
-#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR4_unused_1_DEFAULT 0x00000000
-
-/* MEMC_DDR_0 :: DRAM_MODE_2 :: DDR4 :: LPASR [07:06] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR4_LPASR_MASK 0x000000c0
-#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR4_LPASR_SHIFT 6
-#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR4_LPASR_DEFAULT 0x00000000
-
-/* MEMC_DDR_0 :: DRAM_MODE_2 :: DDR4 :: CWL [05:03] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR4_CWL_MASK 0x00000038
-#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR4_CWL_SHIFT 3
-#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR4_CWL_DEFAULT 0x00000001
-
-/* MEMC_DDR_0 :: DRAM_MODE_2 :: DDR4 :: unused_0 [02:00] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR4_unused_0_MASK 0x00000007
-#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR4_unused_0_SHIFT 0
-#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR4_unused_0_DEFAULT 0x00000000
-
-/* union - case GDDR5M [12:00] */
-/* MEMC_DDR_0 :: DRAM_MODE_2 :: GDDR5M :: unused_1 [12:12] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_2_GDDR5M_unused_1_MASK 0x00001000
-#define BCHP_MEMC_DDR_0_DRAM_MODE_2_GDDR5M_unused_1_SHIFT 12
-#define BCHP_MEMC_DDR_0_DRAM_MODE_2_GDDR5M_unused_1_DEFAULT 0x00000000
-
-/* MEMC_DDR_0 :: DRAM_MODE_2 :: GDDR5M :: ADDR_CMD_TERM_OFFSET [11:09] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_2_GDDR5M_ADDR_CMD_TERM_OFFSET_MASK 0x00000e00
-#define BCHP_MEMC_DDR_0_DRAM_MODE_2_GDDR5M_ADDR_CMD_TERM_OFFSET_SHIFT 9
-#define BCHP_MEMC_DDR_0_DRAM_MODE_2_GDDR5M_ADDR_CMD_TERM_OFFSET_DEFAULT 0x00000000
-
-/* MEMC_DDR_0 :: DRAM_MODE_2 :: GDDR5M :: DATA_WCK_TERM_OFFSET [08:06] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_2_GDDR5M_DATA_WCK_TERM_OFFSET_MASK 0x000001c0
-#define BCHP_MEMC_DDR_0_DRAM_MODE_2_GDDR5M_DATA_WCK_TERM_OFFSET_SHIFT 6
-#define BCHP_MEMC_DDR_0_DRAM_MODE_2_GDDR5M_DATA_WCK_TERM_OFFSET_DEFAULT 0x00000000
-
-/* MEMC_DDR_0 :: DRAM_MODE_2 :: GDDR5M :: OCD_PUP_DRIVER_OFFSET [05:03] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_2_GDDR5M_OCD_PUP_DRIVER_OFFSET_MASK 0x00000038
-#define BCHP_MEMC_DDR_0_DRAM_MODE_2_GDDR5M_OCD_PUP_DRIVER_OFFSET_SHIFT 3
-#define BCHP_MEMC_DDR_0_DRAM_MODE_2_GDDR5M_OCD_PUP_DRIVER_OFFSET_DEFAULT 0x00000000
-
-/* MEMC_DDR_0 :: DRAM_MODE_2 :: GDDR5M :: OCD_PDN_DRIVER_OFFSET [02:00] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_2_GDDR5M_OCD_PDN_DRIVER_OFFSET_MASK 0x00000007
-#define BCHP_MEMC_DDR_0_DRAM_MODE_2_GDDR5M_OCD_PDN_DRIVER_OFFSET_SHIFT 0
-#define BCHP_MEMC_DDR_0_DRAM_MODE_2_GDDR5M_OCD_PDN_DRIVER_OFFSET_DEFAULT 0x00000000
-
-/* union - case GDDR5 [12:00] */
-/* MEMC_DDR_0 :: DRAM_MODE_2 :: GDDR5 :: unused_1 [12:12] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_2_GDDR5_unused_1_MASK 0x00001000
-#define BCHP_MEMC_DDR_0_DRAM_MODE_2_GDDR5_unused_1_SHIFT 12
-#define BCHP_MEMC_DDR_0_DRAM_MODE_2_GDDR5_unused_1_DEFAULT 0x00000000
-
-/* MEMC_DDR_0 :: DRAM_MODE_2 :: GDDR5 :: ADDR_CMD_TERM_OFFSET [11:09] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_2_GDDR5_ADDR_CMD_TERM_OFFSET_MASK 0x00000e00
-#define BCHP_MEMC_DDR_0_DRAM_MODE_2_GDDR5_ADDR_CMD_TERM_OFFSET_SHIFT 9
-#define BCHP_MEMC_DDR_0_DRAM_MODE_2_GDDR5_ADDR_CMD_TERM_OFFSET_DEFAULT 0x00000000
-
-/* MEMC_DDR_0 :: DRAM_MODE_2 :: GDDR5 :: DATA_WCK_TERM_OFFSET [08:06] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_2_GDDR5_DATA_WCK_TERM_OFFSET_MASK 0x000001c0
-#define BCHP_MEMC_DDR_0_DRAM_MODE_2_GDDR5_DATA_WCK_TERM_OFFSET_SHIFT 6
-#define BCHP_MEMC_DDR_0_DRAM_MODE_2_GDDR5_DATA_WCK_TERM_OFFSET_DEFAULT 0x00000000
-
-/* MEMC_DDR_0 :: DRAM_MODE_2 :: GDDR5 :: OCD_PUP_DRIVER_OFFSET [05:03] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_2_GDDR5_OCD_PUP_DRIVER_OFFSET_MASK 0x00000038
-#define BCHP_MEMC_DDR_0_DRAM_MODE_2_GDDR5_OCD_PUP_DRIVER_OFFSET_SHIFT 3
-#define BCHP_MEMC_DDR_0_DRAM_MODE_2_GDDR5_OCD_PUP_DRIVER_OFFSET_DEFAULT 0x00000000
-
-/* MEMC_DDR_0 :: DRAM_MODE_2 :: GDDR5 :: OCD_PDN_DRIVER_OFFSET [02:00] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_2_GDDR5_OCD_PDN_DRIVER_OFFSET_MASK 0x00000007
-#define BCHP_MEMC_DDR_0_DRAM_MODE_2_GDDR5_OCD_PDN_DRIVER_OFFSET_SHIFT 0
-#define BCHP_MEMC_DDR_0_DRAM_MODE_2_GDDR5_OCD_PDN_DRIVER_OFFSET_DEFAULT 0x00000000
-
-/***************************************************************************
- *DRAM_MODE_3 - Dram Mode Register 3
- ***************************************************************************/
-/* MEMC_DDR_0 :: DRAM_MODE_3 :: reserved0 [31:16] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_3_reserved0_MASK 0xffff0000
-#define BCHP_MEMC_DDR_0_DRAM_MODE_3_reserved0_SHIFT 16
-
-/* MEMC_DDR_0 :: DRAM_MODE_3 :: unused_0 [15:13] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_3_unused_0_MASK 0x0000e000
-#define BCHP_MEMC_DDR_0_DRAM_MODE_3_unused_0_SHIFT 13
-#define BCHP_MEMC_DDR_0_DRAM_MODE_3_unused_0_DEFAULT 0x00000000
-
-/* union - case DDR3 [12:00] */
-/* MEMC_DDR_0 :: DRAM_MODE_3 :: DDR3 :: unused_1 [12:03] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_3_DDR3_unused_1_MASK 0x00001ff8
-#define BCHP_MEMC_DDR_0_DRAM_MODE_3_DDR3_unused_1_SHIFT 3
-#define BCHP_MEMC_DDR_0_DRAM_MODE_3_DDR3_unused_1_DEFAULT 0x00000000
-
-/* MEMC_DDR_0 :: DRAM_MODE_3 :: DDR3 :: MPR [02:02] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_3_DDR3_MPR_MASK 0x00000004
-#define BCHP_MEMC_DDR_0_DRAM_MODE_3_DDR3_MPR_SHIFT 2
-#define BCHP_MEMC_DDR_0_DRAM_MODE_3_DDR3_MPR_DEFAULT 0x00000000
-
-/* MEMC_DDR_0 :: DRAM_MODE_3 :: DDR3 :: MPR_LOC [01:00] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_3_DDR3_MPR_LOC_MASK 0x00000003
-#define BCHP_MEMC_DDR_0_DRAM_MODE_3_DDR3_MPR_LOC_SHIFT 0
-#define BCHP_MEMC_DDR_0_DRAM_MODE_3_DDR3_MPR_LOC_DEFAULT 0x00000000
-
-/* union - case DDR4 [12:00] */
-/* MEMC_DDR_0 :: DRAM_MODE_3 :: DDR4 :: MPR_READ_FORMAT [12:11] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_3_DDR4_MPR_READ_FORMAT_MASK 0x00001800
-#define BCHP_MEMC_DDR_0_DRAM_MODE_3_DDR4_MPR_READ_FORMAT_SHIFT 11
-#define BCHP_MEMC_DDR_0_DRAM_MODE_3_DDR4_MPR_READ_FORMAT_DEFAULT 0x00000000
-
-/* MEMC_DDR_0 :: DRAM_MODE_3 :: DDR4 :: WL_CRC_DM [10:09] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_3_DDR4_WL_CRC_DM_MASK 0x00000600
-#define BCHP_MEMC_DDR_0_DRAM_MODE_3_DDR4_WL_CRC_DM_SHIFT 9
-#define BCHP_MEMC_DDR_0_DRAM_MODE_3_DDR4_WL_CRC_DM_DEFAULT 0x00000000
-
-/* MEMC_DDR_0 :: DRAM_MODE_3 :: DDR4 :: FGR [08:06] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_3_DDR4_FGR_MASK 0x000001c0
-#define BCHP_MEMC_DDR_0_DRAM_MODE_3_DDR4_FGR_SHIFT 6
-#define BCHP_MEMC_DDR_0_DRAM_MODE_3_DDR4_FGR_DEFAULT 0x00000000
-
-/* MEMC_DDR_0 :: DRAM_MODE_3 :: DDR4 :: TEMP_READOUT [05:05] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_3_DDR4_TEMP_READOUT_MASK 0x00000020
-#define BCHP_MEMC_DDR_0_DRAM_MODE_3_DDR4_TEMP_READOUT_SHIFT 5
-#define BCHP_MEMC_DDR_0_DRAM_MODE_3_DDR4_TEMP_READOUT_DEFAULT 0x00000000
-#define BCHP_MEMC_DDR_0_DRAM_MODE_3_DDR4_TEMP_READOUT_ENABLE 1
-#define BCHP_MEMC_DDR_0_DRAM_MODE_3_DDR4_TEMP_READOUT_DISABLE 0
-
-/* MEMC_DDR_0 :: DRAM_MODE_3 :: DDR4 :: PER_DRAM_ADDR [04:04] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_3_DDR4_PER_DRAM_ADDR_MASK 0x00000010
-#define BCHP_MEMC_DDR_0_DRAM_MODE_3_DDR4_PER_DRAM_ADDR_SHIFT 4
-#define BCHP_MEMC_DDR_0_DRAM_MODE_3_DDR4_PER_DRAM_ADDR_DEFAULT 0x00000000
-#define BCHP_MEMC_DDR_0_DRAM_MODE_3_DDR4_PER_DRAM_ADDR_ENABLE 1
-#define BCHP_MEMC_DDR_0_DRAM_MODE_3_DDR4_PER_DRAM_ADDR_DISABLE 0
-
-/* MEMC_DDR_0 :: DRAM_MODE_3 :: DDR4 :: GEARDOWN [03:03] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_3_DDR4_GEARDOWN_MASK 0x00000008
-#define BCHP_MEMC_DDR_0_DRAM_MODE_3_DDR4_GEARDOWN_SHIFT 3
-#define BCHP_MEMC_DDR_0_DRAM_MODE_3_DDR4_GEARDOWN_DEFAULT 0x00000000
-
-/* MEMC_DDR_0 :: DRAM_MODE_3 :: DDR4 :: MPR [02:02] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_3_DDR4_MPR_MASK 0x00000004
-#define BCHP_MEMC_DDR_0_DRAM_MODE_3_DDR4_MPR_SHIFT 2
-#define BCHP_MEMC_DDR_0_DRAM_MODE_3_DDR4_MPR_DEFAULT 0x00000000
-
-/* MEMC_DDR_0 :: DRAM_MODE_3 :: DDR4 :: MPR_PAGE [01:00] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_3_DDR4_MPR_PAGE_MASK 0x00000003
-#define BCHP_MEMC_DDR_0_DRAM_MODE_3_DDR4_MPR_PAGE_SHIFT 0
-#define BCHP_MEMC_DDR_0_DRAM_MODE_3_DDR4_MPR_PAGE_DEFAULT 0x00000000
-
-/* union - case GDDR5M [12:00] */
-/* MEMC_DDR_0 :: DRAM_MODE_3 :: GDDR5M :: unused_1 [12:12] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_3_GDDR5M_unused_1_MASK 0x00001000
-#define BCHP_MEMC_DDR_0_DRAM_MODE_3_GDDR5M_unused_1_SHIFT 12
-#define BCHP_MEMC_DDR_0_DRAM_MODE_3_GDDR5M_unused_1_DEFAULT 0x00000000
-
-/* MEMC_DDR_0 :: DRAM_MODE_3 :: GDDR5M :: BANK_GROUPS [11:10] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_3_GDDR5M_BANK_GROUPS_MASK 0x00000c00
-#define BCHP_MEMC_DDR_0_DRAM_MODE_3_GDDR5M_BANK_GROUPS_SHIFT 10
-#define BCHP_MEMC_DDR_0_DRAM_MODE_3_GDDR5M_BANK_GROUPS_DEFAULT 0x00000000
-
-/* MEMC_DDR_0 :: DRAM_MODE_3 :: GDDR5M :: WCK_TERM [09:08] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_3_GDDR5M_WCK_TERM_MASK 0x00000300
-#define BCHP_MEMC_DDR_0_DRAM_MODE_3_GDDR5M_WCK_TERM_SHIFT 8
-#define BCHP_MEMC_DDR_0_DRAM_MODE_3_GDDR5M_WCK_TERM_DEFAULT 0x00000000
-
-/* MEMC_DDR_0 :: DRAM_MODE_3 :: GDDR5M :: DRAM_INFO [07:06] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_3_GDDR5M_DRAM_INFO_MASK 0x000000c0
-#define BCHP_MEMC_DDR_0_DRAM_MODE_3_GDDR5M_DRAM_INFO_SHIFT 6
-#define BCHP_MEMC_DDR_0_DRAM_MODE_3_GDDR5M_DRAM_INFO_DEFAULT 0x00000000
-
-/* MEMC_DDR_0 :: DRAM_MODE_3 :: GDDR5M :: RDQS_MODE [05:05] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_3_GDDR5M_RDQS_MODE_MASK 0x00000020
-#define BCHP_MEMC_DDR_0_DRAM_MODE_3_GDDR5M_RDQS_MODE_SHIFT 5
-#define BCHP_MEMC_DDR_0_DRAM_MODE_3_GDDR5M_RDQS_MODE_DEFAULT 0x00000000
-#define BCHP_MEMC_DDR_0_DRAM_MODE_3_GDDR5M_RDQS_MODE_ENABLE 1
-#define BCHP_MEMC_DDR_0_DRAM_MODE_3_GDDR5M_RDQS_MODE_DISABLE 0
-
-/* MEMC_DDR_0 :: DRAM_MODE_3 :: GDDR5M :: WCK2CK_TRAIN [04:04] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_3_GDDR5M_WCK2CK_TRAIN_MASK 0x00000010
-#define BCHP_MEMC_DDR_0_DRAM_MODE_3_GDDR5M_WCK2CK_TRAIN_SHIFT 4
-#define BCHP_MEMC_DDR_0_DRAM_MODE_3_GDDR5M_WCK2CK_TRAIN_DEFAULT 0x00000000
-#define BCHP_MEMC_DDR_0_DRAM_MODE_3_GDDR5M_WCK2CK_TRAIN_ENABLE 1
-#define BCHP_MEMC_DDR_0_DRAM_MODE_3_GDDR5M_WCK2CK_TRAIN_DISABLE 0
-
-/* MEMC_DDR_0 :: DRAM_MODE_3 :: GDDR5M :: WCK23_INVERT [03:03] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_3_GDDR5M_WCK23_INVERT_MASK 0x00000008
-#define BCHP_MEMC_DDR_0_DRAM_MODE_3_GDDR5M_WCK23_INVERT_SHIFT 3
-#define BCHP_MEMC_DDR_0_DRAM_MODE_3_GDDR5M_WCK23_INVERT_DEFAULT 0x00000000
-#define BCHP_MEMC_DDR_0_DRAM_MODE_3_GDDR5M_WCK23_INVERT_ENABLE 1
-#define BCHP_MEMC_DDR_0_DRAM_MODE_3_GDDR5M_WCK23_INVERT_DISABLE 0
-
-/* MEMC_DDR_0 :: DRAM_MODE_3 :: GDDR5M :: WCK01_INVERT [02:02] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_3_GDDR5M_WCK01_INVERT_MASK 0x00000004
-#define BCHP_MEMC_DDR_0_DRAM_MODE_3_GDDR5M_WCK01_INVERT_SHIFT 2
-#define BCHP_MEMC_DDR_0_DRAM_MODE_3_GDDR5M_WCK01_INVERT_DEFAULT 0x00000000
-#define BCHP_MEMC_DDR_0_DRAM_MODE_3_GDDR5M_WCK01_INVERT_ENABLE 1
-#define BCHP_MEMC_DDR_0_DRAM_MODE_3_GDDR5M_WCK01_INVERT_DISABLE 0
-
-/* MEMC_DDR_0 :: DRAM_MODE_3 :: GDDR5M :: SELF_REFRESH [01:00] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_3_GDDR5M_SELF_REFRESH_MASK 0x00000003
-#define BCHP_MEMC_DDR_0_DRAM_MODE_3_GDDR5M_SELF_REFRESH_SHIFT 0
-#define BCHP_MEMC_DDR_0_DRAM_MODE_3_GDDR5M_SELF_REFRESH_DEFAULT 0x00000000
-
-/* union - case GDDR5 [12:00] */
-/* MEMC_DDR_0 :: DRAM_MODE_3 :: GDDR5 :: unused_1 [12:12] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_3_GDDR5_unused_1_MASK 0x00001000
-#define BCHP_MEMC_DDR_0_DRAM_MODE_3_GDDR5_unused_1_SHIFT 12
-#define BCHP_MEMC_DDR_0_DRAM_MODE_3_GDDR5_unused_1_DEFAULT 0x00000000
-
-/* MEMC_DDR_0 :: DRAM_MODE_3 :: GDDR5 :: BANK_GROUPS [11:10] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_3_GDDR5_BANK_GROUPS_MASK 0x00000c00
-#define BCHP_MEMC_DDR_0_DRAM_MODE_3_GDDR5_BANK_GROUPS_SHIFT 10
-#define BCHP_MEMC_DDR_0_DRAM_MODE_3_GDDR5_BANK_GROUPS_DEFAULT 0x00000000
-
-/* MEMC_DDR_0 :: DRAM_MODE_3 :: GDDR5 :: WCK_TERM [09:08] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_3_GDDR5_WCK_TERM_MASK 0x00000300
-#define BCHP_MEMC_DDR_0_DRAM_MODE_3_GDDR5_WCK_TERM_SHIFT 8
-#define BCHP_MEMC_DDR_0_DRAM_MODE_3_GDDR5_WCK_TERM_DEFAULT 0x00000000
-
-/* MEMC_DDR_0 :: DRAM_MODE_3 :: GDDR5 :: DRAM_INFO [07:06] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_3_GDDR5_DRAM_INFO_MASK 0x000000c0
-#define BCHP_MEMC_DDR_0_DRAM_MODE_3_GDDR5_DRAM_INFO_SHIFT 6
-#define BCHP_MEMC_DDR_0_DRAM_MODE_3_GDDR5_DRAM_INFO_DEFAULT 0x00000000
-
-/* MEMC_DDR_0 :: DRAM_MODE_3 :: GDDR5 :: RDQS_MODE [05:05] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_3_GDDR5_RDQS_MODE_MASK 0x00000020
-#define BCHP_MEMC_DDR_0_DRAM_MODE_3_GDDR5_RDQS_MODE_SHIFT 5
-#define BCHP_MEMC_DDR_0_DRAM_MODE_3_GDDR5_RDQS_MODE_DEFAULT 0x00000000
-#define BCHP_MEMC_DDR_0_DRAM_MODE_3_GDDR5_RDQS_MODE_ENABLE 1
-#define BCHP_MEMC_DDR_0_DRAM_MODE_3_GDDR5_RDQS_MODE_DISABLE 0
-
-/* MEMC_DDR_0 :: DRAM_MODE_3 :: GDDR5 :: WCK2CK_TRAIN [04:04] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_3_GDDR5_WCK2CK_TRAIN_MASK 0x00000010
-#define BCHP_MEMC_DDR_0_DRAM_MODE_3_GDDR5_WCK2CK_TRAIN_SHIFT 4
-#define BCHP_MEMC_DDR_0_DRAM_MODE_3_GDDR5_WCK2CK_TRAIN_DEFAULT 0x00000000
-#define BCHP_MEMC_DDR_0_DRAM_MODE_3_GDDR5_WCK2CK_TRAIN_ENABLE 1
-#define BCHP_MEMC_DDR_0_DRAM_MODE_3_GDDR5_WCK2CK_TRAIN_DISABLE 0
-
-/* MEMC_DDR_0 :: DRAM_MODE_3 :: GDDR5 :: WCK23_INVERT [03:03] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_3_GDDR5_WCK23_INVERT_MASK 0x00000008
-#define BCHP_MEMC_DDR_0_DRAM_MODE_3_GDDR5_WCK23_INVERT_SHIFT 3
-#define BCHP_MEMC_DDR_0_DRAM_MODE_3_GDDR5_WCK23_INVERT_DEFAULT 0x00000000
-#define BCHP_MEMC_DDR_0_DRAM_MODE_3_GDDR5_WCK23_INVERT_ENABLE 1
-#define BCHP_MEMC_DDR_0_DRAM_MODE_3_GDDR5_WCK23_INVERT_DISABLE 0
-
-/* MEMC_DDR_0 :: DRAM_MODE_3 :: GDDR5 :: WCK01_INVERT [02:02] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_3_GDDR5_WCK01_INVERT_MASK 0x00000004
-#define BCHP_MEMC_DDR_0_DRAM_MODE_3_GDDR5_WCK01_INVERT_SHIFT 2
-#define BCHP_MEMC_DDR_0_DRAM_MODE_3_GDDR5_WCK01_INVERT_DEFAULT 0x00000000
-#define BCHP_MEMC_DDR_0_DRAM_MODE_3_GDDR5_WCK01_INVERT_ENABLE 1
-#define BCHP_MEMC_DDR_0_DRAM_MODE_3_GDDR5_WCK01_INVERT_DISABLE 0
-
-/* MEMC_DDR_0 :: DRAM_MODE_3 :: GDDR5 :: SELF_REFRESH [01:00] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_3_GDDR5_SELF_REFRESH_MASK 0x00000003
-#define BCHP_MEMC_DDR_0_DRAM_MODE_3_GDDR5_SELF_REFRESH_SHIFT 0
-#define BCHP_MEMC_DDR_0_DRAM_MODE_3_GDDR5_SELF_REFRESH_DEFAULT 0x00000000
-
-/* union - case Others [12:00] */
-/* MEMC_DDR_0 :: DRAM_MODE_3 :: Others :: unused_1 [12:00] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_3_Others_unused_1_MASK 0x00001fff
-#define BCHP_MEMC_DDR_0_DRAM_MODE_3_Others_unused_1_SHIFT 0
-#define BCHP_MEMC_DDR_0_DRAM_MODE_3_Others_unused_1_DEFAULT 0x00000000
-
-/***************************************************************************
- *DRAM_MODE_4 - Dram Mode Register 4
- ***************************************************************************/
-/* MEMC_DDR_0 :: DRAM_MODE_4 :: reserved0 [31:16] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_4_reserved0_MASK 0xffff0000
-#define BCHP_MEMC_DDR_0_DRAM_MODE_4_reserved0_SHIFT 16
-
-/* MEMC_DDR_0 :: DRAM_MODE_4 :: unused_0 [15:13] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_4_unused_0_MASK 0x0000e000
-#define BCHP_MEMC_DDR_0_DRAM_MODE_4_unused_0_SHIFT 13
-#define BCHP_MEMC_DDR_0_DRAM_MODE_4_unused_0_DEFAULT 0x00000000
-
-/* union - case DDR4 [12:00] */
-/* MEMC_DDR_0 :: DRAM_MODE_4 :: DDR4 :: WR_PREAMBLE [12:12] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_4_DDR4_WR_PREAMBLE_MASK 0x00001000
-#define BCHP_MEMC_DDR_0_DRAM_MODE_4_DDR4_WR_PREAMBLE_SHIFT 12
-#define BCHP_MEMC_DDR_0_DRAM_MODE_4_DDR4_WR_PREAMBLE_DEFAULT 0x00000000
-
-/* MEMC_DDR_0 :: DRAM_MODE_4 :: DDR4 :: RD_PREAMBLE [11:11] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_4_DDR4_RD_PREAMBLE_MASK 0x00000800
-#define BCHP_MEMC_DDR_0_DRAM_MODE_4_DDR4_RD_PREAMBLE_SHIFT 11
-#define BCHP_MEMC_DDR_0_DRAM_MODE_4_DDR4_RD_PREAMBLE_DEFAULT 0x00000000
-
-/* MEMC_DDR_0 :: DRAM_MODE_4 :: DDR4 :: RD_PREAMBLE_TRAINING [10:10] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_4_DDR4_RD_PREAMBLE_TRAINING_MASK 0x00000400
-#define BCHP_MEMC_DDR_0_DRAM_MODE_4_DDR4_RD_PREAMBLE_TRAINING_SHIFT 10
-#define BCHP_MEMC_DDR_0_DRAM_MODE_4_DDR4_RD_PREAMBLE_TRAINING_DEFAULT 0x00000000
-#define BCHP_MEMC_DDR_0_DRAM_MODE_4_DDR4_RD_PREAMBLE_TRAINING_ENABLE 1
-#define BCHP_MEMC_DDR_0_DRAM_MODE_4_DDR4_RD_PREAMBLE_TRAINING_DISABLE 0
-
-/* MEMC_DDR_0 :: DRAM_MODE_4 :: DDR4 :: SELF_REFRESH_ABORT [09:09] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_4_DDR4_SELF_REFRESH_ABORT_MASK 0x00000200
-#define BCHP_MEMC_DDR_0_DRAM_MODE_4_DDR4_SELF_REFRESH_ABORT_SHIFT 9
-#define BCHP_MEMC_DDR_0_DRAM_MODE_4_DDR4_SELF_REFRESH_ABORT_DEFAULT 0x00000000
-#define BCHP_MEMC_DDR_0_DRAM_MODE_4_DDR4_SELF_REFRESH_ABORT_ENABLE 1
-#define BCHP_MEMC_DDR_0_DRAM_MODE_4_DDR4_SELF_REFRESH_ABORT_DISABLE 0
-
-/* MEMC_DDR_0 :: DRAM_MODE_4 :: DDR4 :: CMD_ADDR_LATENCY [08:06] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_4_DDR4_CMD_ADDR_LATENCY_MASK 0x000001c0
-#define BCHP_MEMC_DDR_0_DRAM_MODE_4_DDR4_CMD_ADDR_LATENCY_SHIFT 6
-#define BCHP_MEMC_DDR_0_DRAM_MODE_4_DDR4_CMD_ADDR_LATENCY_DEFAULT 0x00000000
-
-/* MEMC_DDR_0 :: DRAM_MODE_4 :: DDR4 :: unused_2 [05:05] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_4_DDR4_unused_2_MASK 0x00000020
-#define BCHP_MEMC_DDR_0_DRAM_MODE_4_DDR4_unused_2_SHIFT 5
-#define BCHP_MEMC_DDR_0_DRAM_MODE_4_DDR4_unused_2_DEFAULT 0x00000000
-
-/* MEMC_DDR_0 :: DRAM_MODE_4 :: DDR4 :: VREF_MONITOR [04:04] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_4_DDR4_VREF_MONITOR_MASK 0x00000010
-#define BCHP_MEMC_DDR_0_DRAM_MODE_4_DDR4_VREF_MONITOR_SHIFT 4
-#define BCHP_MEMC_DDR_0_DRAM_MODE_4_DDR4_VREF_MONITOR_DEFAULT 0x00000000
-#define BCHP_MEMC_DDR_0_DRAM_MODE_4_DDR4_VREF_MONITOR_ENABLE 1
-#define BCHP_MEMC_DDR_0_DRAM_MODE_4_DDR4_VREF_MONITOR_DISABLE 0
-
-/* MEMC_DDR_0 :: DRAM_MODE_4 :: DDR4 :: TEMP_CONTROLLED_REFRESH [03:03] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_4_DDR4_TEMP_CONTROLLED_REFRESH_MASK 0x00000008
-#define BCHP_MEMC_DDR_0_DRAM_MODE_4_DDR4_TEMP_CONTROLLED_REFRESH_SHIFT 3
-#define BCHP_MEMC_DDR_0_DRAM_MODE_4_DDR4_TEMP_CONTROLLED_REFRESH_DEFAULT 0x00000000
-#define BCHP_MEMC_DDR_0_DRAM_MODE_4_DDR4_TEMP_CONTROLLED_REFRESH_ENABLE 1
-#define BCHP_MEMC_DDR_0_DRAM_MODE_4_DDR4_TEMP_CONTROLLED_REFRESH_DISABLE 0
-
-/* MEMC_DDR_0 :: DRAM_MODE_4 :: DDR4 :: TEMP_CONTROLLED_REFRESH_RANGE [02:02] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_4_DDR4_TEMP_CONTROLLED_REFRESH_RANGE_MASK 0x00000004
-#define BCHP_MEMC_DDR_0_DRAM_MODE_4_DDR4_TEMP_CONTROLLED_REFRESH_RANGE_SHIFT 2
-#define BCHP_MEMC_DDR_0_DRAM_MODE_4_DDR4_TEMP_CONTROLLED_REFRESH_RANGE_DEFAULT 0x00000000
-
-/* MEMC_DDR_0 :: DRAM_MODE_4 :: DDR4 :: MAXIMUM_POWER_SAVINGS [01:01] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_4_DDR4_MAXIMUM_POWER_SAVINGS_MASK 0x00000002
-#define BCHP_MEMC_DDR_0_DRAM_MODE_4_DDR4_MAXIMUM_POWER_SAVINGS_SHIFT 1
-#define BCHP_MEMC_DDR_0_DRAM_MODE_4_DDR4_MAXIMUM_POWER_SAVINGS_DEFAULT 0x00000000
-#define BCHP_MEMC_DDR_0_DRAM_MODE_4_DDR4_MAXIMUM_POWER_SAVINGS_ENABLE 1
-#define BCHP_MEMC_DDR_0_DRAM_MODE_4_DDR4_MAXIMUM_POWER_SAVINGS_DISABLE 0
-
-/* MEMC_DDR_0 :: DRAM_MODE_4 :: DDR4 :: unused_1 [00:00] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_4_DDR4_unused_1_MASK 0x00000001
-#define BCHP_MEMC_DDR_0_DRAM_MODE_4_DDR4_unused_1_SHIFT 0
-#define BCHP_MEMC_DDR_0_DRAM_MODE_4_DDR4_unused_1_DEFAULT 0x00000000
-
-/* union - case GDDR5M [12:00] */
-/* MEMC_DDR_0 :: DRAM_MODE_4 :: GDDR5M :: unused_1 [12:12] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_4_GDDR5M_unused_1_MASK 0x00001000
-#define BCHP_MEMC_DDR_0_DRAM_MODE_4_GDDR5M_unused_1_SHIFT 12
-#define BCHP_MEMC_DDR_0_DRAM_MODE_4_GDDR5M_unused_1_DEFAULT 0x00000000
-
-/* MEMC_DDR_0 :: DRAM_MODE_4 :: GDDR5M :: EDC_HOLD_INVERT [11:11] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_4_GDDR5M_EDC_HOLD_INVERT_MASK 0x00000800
-#define BCHP_MEMC_DDR_0_DRAM_MODE_4_GDDR5M_EDC_HOLD_INVERT_SHIFT 11
-#define BCHP_MEMC_DDR_0_DRAM_MODE_4_GDDR5M_EDC_HOLD_INVERT_DEFAULT 0x00000000
-
-/* MEMC_DDR_0 :: DRAM_MODE_4 :: GDDR5M :: WR_CRC [10:10] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_4_GDDR5M_WR_CRC_MASK 0x00000400
-#define BCHP_MEMC_DDR_0_DRAM_MODE_4_GDDR5M_WR_CRC_SHIFT 10
-#define BCHP_MEMC_DDR_0_DRAM_MODE_4_GDDR5M_WR_CRC_DEFAULT 0x00000001
-#define BCHP_MEMC_DDR_0_DRAM_MODE_4_GDDR5M_WR_CRC_ENABLE 0
-#define BCHP_MEMC_DDR_0_DRAM_MODE_4_GDDR5M_WR_CRC_DISABLE 1
-
-/* MEMC_DDR_0 :: DRAM_MODE_4 :: GDDR5M :: RD_CRC [09:09] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_4_GDDR5M_RD_CRC_MASK 0x00000200
-#define BCHP_MEMC_DDR_0_DRAM_MODE_4_GDDR5M_RD_CRC_SHIFT 9
-#define BCHP_MEMC_DDR_0_DRAM_MODE_4_GDDR5M_RD_CRC_DEFAULT 0x00000001
-#define BCHP_MEMC_DDR_0_DRAM_MODE_4_GDDR5M_RD_CRC_ENABLE 0
-#define BCHP_MEMC_DDR_0_DRAM_MODE_4_GDDR5M_RD_CRC_DISABLE 1
-
-/* MEMC_DDR_0 :: DRAM_MODE_4 :: GDDR5M :: CRC_RD_LATENCY [08:07] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_4_GDDR5M_CRC_RD_LATENCY_MASK 0x00000180
-#define BCHP_MEMC_DDR_0_DRAM_MODE_4_GDDR5M_CRC_RD_LATENCY_SHIFT 7
-#define BCHP_MEMC_DDR_0_DRAM_MODE_4_GDDR5M_CRC_RD_LATENCY_DEFAULT 0x00000000
-
-/* MEMC_DDR_0 :: DRAM_MODE_4 :: GDDR5M :: CRC_WR_LATENCY [06:04] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_4_GDDR5M_CRC_WR_LATENCY_MASK 0x00000070
-#define BCHP_MEMC_DDR_0_DRAM_MODE_4_GDDR5M_CRC_WR_LATENCY_SHIFT 4
-#define BCHP_MEMC_DDR_0_DRAM_MODE_4_GDDR5M_CRC_WR_LATENCY_DEFAULT 0x00000000
-
-/* MEMC_DDR_0 :: DRAM_MODE_4 :: GDDR5M :: EDC_HOLD_PATTERN [03:00] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_4_GDDR5M_EDC_HOLD_PATTERN_MASK 0x0000000f
-#define BCHP_MEMC_DDR_0_DRAM_MODE_4_GDDR5M_EDC_HOLD_PATTERN_SHIFT 0
-#define BCHP_MEMC_DDR_0_DRAM_MODE_4_GDDR5M_EDC_HOLD_PATTERN_DEFAULT 0x00000000
-
-/* union - case GDDR5 [12:00] */
-/* MEMC_DDR_0 :: DRAM_MODE_4 :: GDDR5 :: unused_1 [12:12] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_4_GDDR5_unused_1_MASK 0x00001000
-#define BCHP_MEMC_DDR_0_DRAM_MODE_4_GDDR5_unused_1_SHIFT 12
-#define BCHP_MEMC_DDR_0_DRAM_MODE_4_GDDR5_unused_1_DEFAULT 0x00000000
-
-/* MEMC_DDR_0 :: DRAM_MODE_4 :: GDDR5 :: EDC_HOLD_INVERT [11:11] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_4_GDDR5_EDC_HOLD_INVERT_MASK 0x00000800
-#define BCHP_MEMC_DDR_0_DRAM_MODE_4_GDDR5_EDC_HOLD_INVERT_SHIFT 11
-#define BCHP_MEMC_DDR_0_DRAM_MODE_4_GDDR5_EDC_HOLD_INVERT_DEFAULT 0x00000000
-
-/* MEMC_DDR_0 :: DRAM_MODE_4 :: GDDR5 :: WR_CRC [10:10] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_4_GDDR5_WR_CRC_MASK 0x00000400
-#define BCHP_MEMC_DDR_0_DRAM_MODE_4_GDDR5_WR_CRC_SHIFT 10
-#define BCHP_MEMC_DDR_0_DRAM_MODE_4_GDDR5_WR_CRC_DEFAULT 0x00000001
-#define BCHP_MEMC_DDR_0_DRAM_MODE_4_GDDR5_WR_CRC_ENABLE 0
-#define BCHP_MEMC_DDR_0_DRAM_MODE_4_GDDR5_WR_CRC_DISABLE 1
-
-/* MEMC_DDR_0 :: DRAM_MODE_4 :: GDDR5 :: RD_CRC [09:09] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_4_GDDR5_RD_CRC_MASK 0x00000200
-#define BCHP_MEMC_DDR_0_DRAM_MODE_4_GDDR5_RD_CRC_SHIFT 9
-#define BCHP_MEMC_DDR_0_DRAM_MODE_4_GDDR5_RD_CRC_DEFAULT 0x00000001
-#define BCHP_MEMC_DDR_0_DRAM_MODE_4_GDDR5_RD_CRC_ENABLE 0
-#define BCHP_MEMC_DDR_0_DRAM_MODE_4_GDDR5_RD_CRC_DISABLE 1
-
-/* MEMC_DDR_0 :: DRAM_MODE_4 :: GDDR5 :: CRC_RD_LATENCY [08:07] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_4_GDDR5_CRC_RD_LATENCY_MASK 0x00000180
-#define BCHP_MEMC_DDR_0_DRAM_MODE_4_GDDR5_CRC_RD_LATENCY_SHIFT 7
-#define BCHP_MEMC_DDR_0_DRAM_MODE_4_GDDR5_CRC_RD_LATENCY_DEFAULT 0x00000000
-
-/* MEMC_DDR_0 :: DRAM_MODE_4 :: GDDR5 :: CRC_WR_LATENCY [06:04] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_4_GDDR5_CRC_WR_LATENCY_MASK 0x00000070
-#define BCHP_MEMC_DDR_0_DRAM_MODE_4_GDDR5_CRC_WR_LATENCY_SHIFT 4
-#define BCHP_MEMC_DDR_0_DRAM_MODE_4_GDDR5_CRC_WR_LATENCY_DEFAULT 0x00000000
-
-/* MEMC_DDR_0 :: DRAM_MODE_4 :: GDDR5 :: EDC_HOLD_PATTERN [03:00] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_4_GDDR5_EDC_HOLD_PATTERN_MASK 0x0000000f
-#define BCHP_MEMC_DDR_0_DRAM_MODE_4_GDDR5_EDC_HOLD_PATTERN_SHIFT 0
-#define BCHP_MEMC_DDR_0_DRAM_MODE_4_GDDR5_EDC_HOLD_PATTERN_DEFAULT 0x00000000
-
-/* union - case Others [12:00] */
-/* MEMC_DDR_0 :: DRAM_MODE_4 :: Others :: unused_1 [12:00] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_4_Others_unused_1_MASK 0x00001fff
-#define BCHP_MEMC_DDR_0_DRAM_MODE_4_Others_unused_1_SHIFT 0
-#define BCHP_MEMC_DDR_0_DRAM_MODE_4_Others_unused_1_DEFAULT 0x00000000
-
-/***************************************************************************
- *DRAM_MODE_5 - Dram Mode Register 5
- ***************************************************************************/
-/* MEMC_DDR_0 :: DRAM_MODE_5 :: reserved0 [31:16] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_5_reserved0_MASK 0xffff0000
-#define BCHP_MEMC_DDR_0_DRAM_MODE_5_reserved0_SHIFT 16
-
-/* MEMC_DDR_0 :: DRAM_MODE_5 :: unused_0 [15:13] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_5_unused_0_MASK 0x0000e000
-#define BCHP_MEMC_DDR_0_DRAM_MODE_5_unused_0_SHIFT 13
-#define BCHP_MEMC_DDR_0_DRAM_MODE_5_unused_0_DEFAULT 0x00000000
-
-/* union - case DDR4 [12:00] */
-/* MEMC_DDR_0 :: DRAM_MODE_5 :: DDR4 :: RD_DBI [12:12] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_5_DDR4_RD_DBI_MASK 0x00001000
-#define BCHP_MEMC_DDR_0_DRAM_MODE_5_DDR4_RD_DBI_SHIFT 12
-#define BCHP_MEMC_DDR_0_DRAM_MODE_5_DDR4_RD_DBI_DEFAULT 0x00000000
-#define BCHP_MEMC_DDR_0_DRAM_MODE_5_DDR4_RD_DBI_ENABLE 1
-#define BCHP_MEMC_DDR_0_DRAM_MODE_5_DDR4_RD_DBI_DISABLE 0
-
-/* MEMC_DDR_0 :: DRAM_MODE_5 :: DDR4 :: WR_DBI [11:11] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_5_DDR4_WR_DBI_MASK 0x00000800
-#define BCHP_MEMC_DDR_0_DRAM_MODE_5_DDR4_WR_DBI_SHIFT 11
-#define BCHP_MEMC_DDR_0_DRAM_MODE_5_DDR4_WR_DBI_DEFAULT 0x00000000
-#define BCHP_MEMC_DDR_0_DRAM_MODE_5_DDR4_WR_DBI_ENABLE 1
-#define BCHP_MEMC_DDR_0_DRAM_MODE_5_DDR4_WR_DBI_DISABLE 0
-
-/* MEMC_DDR_0 :: DRAM_MODE_5 :: DDR4 :: DM [10:10] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_5_DDR4_DM_MASK 0x00000400
-#define BCHP_MEMC_DDR_0_DRAM_MODE_5_DDR4_DM_SHIFT 10
-#define BCHP_MEMC_DDR_0_DRAM_MODE_5_DDR4_DM_DEFAULT 0x00000000
-#define BCHP_MEMC_DDR_0_DRAM_MODE_5_DDR4_DM_ENABLE 1
-#define BCHP_MEMC_DDR_0_DRAM_MODE_5_DDR4_DM_DISABLE 0
-
-/* MEMC_DDR_0 :: DRAM_MODE_5 :: DDR4 :: CA_PARITY_PERSIST [09:09] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_5_DDR4_CA_PARITY_PERSIST_MASK 0x00000200
-#define BCHP_MEMC_DDR_0_DRAM_MODE_5_DDR4_CA_PARITY_PERSIST_SHIFT 9
-#define BCHP_MEMC_DDR_0_DRAM_MODE_5_DDR4_CA_PARITY_PERSIST_DEFAULT 0x00000000
-#define BCHP_MEMC_DDR_0_DRAM_MODE_5_DDR4_CA_PARITY_PERSIST_ENABLE 1
-#define BCHP_MEMC_DDR_0_DRAM_MODE_5_DDR4_CA_PARITY_PERSIST_DISABLE 0
-
-/* MEMC_DDR_0 :: DRAM_MODE_5 :: DDR4 :: RTT_PARK [08:06] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_5_DDR4_RTT_PARK_MASK 0x000001c0
-#define BCHP_MEMC_DDR_0_DRAM_MODE_5_DDR4_RTT_PARK_SHIFT 6
-#define BCHP_MEMC_DDR_0_DRAM_MODE_5_DDR4_RTT_PARK_DEFAULT 0x00000000
-
-/* MEMC_DDR_0 :: DRAM_MODE_5 :: DDR4 :: ODT_INPUT_BUFFER [05:05] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_5_DDR4_ODT_INPUT_BUFFER_MASK 0x00000020
-#define BCHP_MEMC_DDR_0_DRAM_MODE_5_DDR4_ODT_INPUT_BUFFER_SHIFT 5
-#define BCHP_MEMC_DDR_0_DRAM_MODE_5_DDR4_ODT_INPUT_BUFFER_DEFAULT 0x00000001
-#define BCHP_MEMC_DDR_0_DRAM_MODE_5_DDR4_ODT_INPUT_BUFFER_ENABLE 0
-#define BCHP_MEMC_DDR_0_DRAM_MODE_5_DDR4_ODT_INPUT_BUFFER_DISABLE 1
-
-/* MEMC_DDR_0 :: DRAM_MODE_5 :: DDR4 :: CMD_ADDR_PARITY_ERROR [04:04] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_5_DDR4_CMD_ADDR_PARITY_ERROR_MASK 0x00000010
-#define BCHP_MEMC_DDR_0_DRAM_MODE_5_DDR4_CMD_ADDR_PARITY_ERROR_SHIFT 4
-#define BCHP_MEMC_DDR_0_DRAM_MODE_5_DDR4_CMD_ADDR_PARITY_ERROR_DEFAULT 0x00000000
-
-/* MEMC_DDR_0 :: DRAM_MODE_5 :: DDR4 :: CRC_ERROR [03:03] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_5_DDR4_CRC_ERROR_MASK 0x00000008
-#define BCHP_MEMC_DDR_0_DRAM_MODE_5_DDR4_CRC_ERROR_SHIFT 3
-#define BCHP_MEMC_DDR_0_DRAM_MODE_5_DDR4_CRC_ERROR_DEFAULT 0x00000000
-
-/* MEMC_DDR_0 :: DRAM_MODE_5 :: DDR4 :: CMD_ADDR_PARITY_LATENCY [02:00] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_5_DDR4_CMD_ADDR_PARITY_LATENCY_MASK 0x00000007
-#define BCHP_MEMC_DDR_0_DRAM_MODE_5_DDR4_CMD_ADDR_PARITY_LATENCY_SHIFT 0
-#define BCHP_MEMC_DDR_0_DRAM_MODE_5_DDR4_CMD_ADDR_PARITY_LATENCY_DEFAULT 0x00000000
-
-/* union - case GDDR5M [12:00] */
-/* MEMC_DDR_0 :: DRAM_MODE_5 :: GDDR5M :: unused_1 [12:12] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_5_GDDR5M_unused_1_MASK 0x00001000
-#define BCHP_MEMC_DDR_0_DRAM_MODE_5_GDDR5M_unused_1_SHIFT 12
-#define BCHP_MEMC_DDR_0_DRAM_MODE_5_GDDR5M_unused_1_DEFAULT 0x00000000
-
-/* MEMC_DDR_0 :: DRAM_MODE_5 :: GDDR5M :: RAS [11:06] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_5_GDDR5M_RAS_MASK 0x00000fc0
-#define BCHP_MEMC_DDR_0_DRAM_MODE_5_GDDR5M_RAS_SHIFT 6
-#define BCHP_MEMC_DDR_0_DRAM_MODE_5_GDDR5M_RAS_DEFAULT 0x00000000
-
-/* MEMC_DDR_0 :: DRAM_MODE_5 :: GDDR5M :: unused_2 [05:03] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_5_GDDR5M_unused_2_MASK 0x00000038
-#define BCHP_MEMC_DDR_0_DRAM_MODE_5_GDDR5M_unused_2_SHIFT 3
-#define BCHP_MEMC_DDR_0_DRAM_MODE_5_GDDR5M_unused_2_DEFAULT 0x00000000
-
-/* MEMC_DDR_0 :: DRAM_MODE_5 :: GDDR5M :: LP3 [02:02] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_5_GDDR5M_LP3_MASK 0x00000004
-#define BCHP_MEMC_DDR_0_DRAM_MODE_5_GDDR5M_LP3_SHIFT 2
-#define BCHP_MEMC_DDR_0_DRAM_MODE_5_GDDR5M_LP3_DEFAULT 0x00000000
-#define BCHP_MEMC_DDR_0_DRAM_MODE_5_GDDR5M_LP3_ENABLE 1
-#define BCHP_MEMC_DDR_0_DRAM_MODE_5_GDDR5M_LP3_DISABLE 0
-
-/* MEMC_DDR_0 :: DRAM_MODE_5 :: GDDR5M :: LP2 [01:01] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_5_GDDR5M_LP2_MASK 0x00000002
-#define BCHP_MEMC_DDR_0_DRAM_MODE_5_GDDR5M_LP2_SHIFT 1
-#define BCHP_MEMC_DDR_0_DRAM_MODE_5_GDDR5M_LP2_DEFAULT 0x00000000
-#define BCHP_MEMC_DDR_0_DRAM_MODE_5_GDDR5M_LP2_ENABLE 1
-#define BCHP_MEMC_DDR_0_DRAM_MODE_5_GDDR5M_LP2_DISABLE 0
-
-/* MEMC_DDR_0 :: DRAM_MODE_5 :: GDDR5M :: LP1 [00:00] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_5_GDDR5M_LP1_MASK 0x00000001
-#define BCHP_MEMC_DDR_0_DRAM_MODE_5_GDDR5M_LP1_SHIFT 0
-#define BCHP_MEMC_DDR_0_DRAM_MODE_5_GDDR5M_LP1_DEFAULT 0x00000000
-#define BCHP_MEMC_DDR_0_DRAM_MODE_5_GDDR5M_LP1_ENABLE 1
-#define BCHP_MEMC_DDR_0_DRAM_MODE_5_GDDR5M_LP1_DISABLE 0
-
-/* union - case GDDR5 [12:00] */
-/* MEMC_DDR_0 :: DRAM_MODE_5 :: GDDR5 :: unused_1 [12:12] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_5_GDDR5_unused_1_MASK 0x00001000
-#define BCHP_MEMC_DDR_0_DRAM_MODE_5_GDDR5_unused_1_SHIFT 12
-#define BCHP_MEMC_DDR_0_DRAM_MODE_5_GDDR5_unused_1_DEFAULT 0x00000000
-
-/* MEMC_DDR_0 :: DRAM_MODE_5 :: GDDR5 :: RAS [11:06] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_5_GDDR5_RAS_MASK 0x00000fc0
-#define BCHP_MEMC_DDR_0_DRAM_MODE_5_GDDR5_RAS_SHIFT 6
-#define BCHP_MEMC_DDR_0_DRAM_MODE_5_GDDR5_RAS_DEFAULT 0x00000000
-
-/* MEMC_DDR_0 :: DRAM_MODE_5 :: GDDR5 :: PLL_DLL_BANDWIDTH [05:03] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_5_GDDR5_PLL_DLL_BANDWIDTH_MASK 0x00000038
-#define BCHP_MEMC_DDR_0_DRAM_MODE_5_GDDR5_PLL_DLL_BANDWIDTH_SHIFT 3
-#define BCHP_MEMC_DDR_0_DRAM_MODE_5_GDDR5_PLL_DLL_BANDWIDTH_DEFAULT 0x00000000
-
-/* MEMC_DDR_0 :: DRAM_MODE_5 :: GDDR5 :: LP3 [02:02] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_5_GDDR5_LP3_MASK 0x00000004
-#define BCHP_MEMC_DDR_0_DRAM_MODE_5_GDDR5_LP3_SHIFT 2
-#define BCHP_MEMC_DDR_0_DRAM_MODE_5_GDDR5_LP3_DEFAULT 0x00000000
-#define BCHP_MEMC_DDR_0_DRAM_MODE_5_GDDR5_LP3_ENABLE 1
-#define BCHP_MEMC_DDR_0_DRAM_MODE_5_GDDR5_LP3_DISABLE 0
-
-/* MEMC_DDR_0 :: DRAM_MODE_5 :: GDDR5 :: LP2 [01:01] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_5_GDDR5_LP2_MASK 0x00000002
-#define BCHP_MEMC_DDR_0_DRAM_MODE_5_GDDR5_LP2_SHIFT 1
-#define BCHP_MEMC_DDR_0_DRAM_MODE_5_GDDR5_LP2_DEFAULT 0x00000000
-#define BCHP_MEMC_DDR_0_DRAM_MODE_5_GDDR5_LP2_ENABLE 1
-#define BCHP_MEMC_DDR_0_DRAM_MODE_5_GDDR5_LP2_DISABLE 0
-
-/* MEMC_DDR_0 :: DRAM_MODE_5 :: GDDR5 :: LP1 [00:00] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_5_GDDR5_LP1_MASK 0x00000001
-#define BCHP_MEMC_DDR_0_DRAM_MODE_5_GDDR5_LP1_SHIFT 0
-#define BCHP_MEMC_DDR_0_DRAM_MODE_5_GDDR5_LP1_DEFAULT 0x00000000
-#define BCHP_MEMC_DDR_0_DRAM_MODE_5_GDDR5_LP1_ENABLE 1
-#define BCHP_MEMC_DDR_0_DRAM_MODE_5_GDDR5_LP1_DISABLE 0
-
-/* union - case Others [12:00] */
-/* MEMC_DDR_0 :: DRAM_MODE_5 :: Others :: unused_1 [12:00] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_5_Others_unused_1_MASK 0x00001fff
-#define BCHP_MEMC_DDR_0_DRAM_MODE_5_Others_unused_1_SHIFT 0
-#define BCHP_MEMC_DDR_0_DRAM_MODE_5_Others_unused_1_DEFAULT 0x00000000
-
-/***************************************************************************
- *DRAM_MODE_6 - Dram Mode Register 6
- ***************************************************************************/
-/* MEMC_DDR_0 :: DRAM_MODE_6 :: reserved0 [31:16] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_6_reserved0_MASK 0xffff0000
-#define BCHP_MEMC_DDR_0_DRAM_MODE_6_reserved0_SHIFT 16
-
-/* MEMC_DDR_0 :: DRAM_MODE_6 :: unused_0 [15:13] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_6_unused_0_MASK 0x0000e000
-#define BCHP_MEMC_DDR_0_DRAM_MODE_6_unused_0_SHIFT 13
-#define BCHP_MEMC_DDR_0_DRAM_MODE_6_unused_0_DEFAULT 0x00000000
-
-/* union - case DDR4 [12:00] */
-/* MEMC_DDR_0 :: DRAM_MODE_6 :: DDR4 :: CCD_L [12:10] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_6_DDR4_CCD_L_MASK 0x00001c00
-#define BCHP_MEMC_DDR_0_DRAM_MODE_6_DDR4_CCD_L_SHIFT 10
-#define BCHP_MEMC_DDR_0_DRAM_MODE_6_DDR4_CCD_L_DEFAULT 0x00000000
-
-/* MEMC_DDR_0 :: DRAM_MODE_6 :: DDR4 :: unused_1 [09:08] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_6_DDR4_unused_1_MASK 0x00000300
-#define BCHP_MEMC_DDR_0_DRAM_MODE_6_DDR4_unused_1_SHIFT 8
-#define BCHP_MEMC_DDR_0_DRAM_MODE_6_DDR4_unused_1_DEFAULT 0x00000000
-
-/* MEMC_DDR_0 :: DRAM_MODE_6 :: DDR4 :: VREF_TRAINING_ENABLE [07:07] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_6_DDR4_VREF_TRAINING_ENABLE_MASK 0x00000080
-#define BCHP_MEMC_DDR_0_DRAM_MODE_6_DDR4_VREF_TRAINING_ENABLE_SHIFT 7
-#define BCHP_MEMC_DDR_0_DRAM_MODE_6_DDR4_VREF_TRAINING_ENABLE_DEFAULT 0x00000000
-
-/* MEMC_DDR_0 :: DRAM_MODE_6 :: DDR4 :: VREF_TRAINING_RANGE [06:06] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_6_DDR4_VREF_TRAINING_RANGE_MASK 0x00000040
-#define BCHP_MEMC_DDR_0_DRAM_MODE_6_DDR4_VREF_TRAINING_RANGE_SHIFT 6
-#define BCHP_MEMC_DDR_0_DRAM_MODE_6_DDR4_VREF_TRAINING_RANGE_DEFAULT 0x00000000
-
-/* MEMC_DDR_0 :: DRAM_MODE_6 :: DDR4 :: VREF_TRAINING [05:00] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_6_DDR4_VREF_TRAINING_MASK 0x0000003f
-#define BCHP_MEMC_DDR_0_DRAM_MODE_6_DDR4_VREF_TRAINING_SHIFT 0
-#define BCHP_MEMC_DDR_0_DRAM_MODE_6_DDR4_VREF_TRAINING_DEFAULT 0x00000000
-
-/* union - case GDDR5M [12:00] */
-/* MEMC_DDR_0 :: DRAM_MODE_6 :: GDDR5M :: unused_1 [12:12] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_6_GDDR5M_unused_1_MASK 0x00001000
-#define BCHP_MEMC_DDR_0_DRAM_MODE_6_GDDR5M_unused_1_SHIFT 12
-#define BCHP_MEMC_DDR_0_DRAM_MODE_6_GDDR5M_unused_1_DEFAULT 0x00000000
-
-/* MEMC_DDR_0 :: DRAM_MODE_6 :: GDDR5M :: VREFD_OFFSET_01 [11:08] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_6_GDDR5M_VREFD_OFFSET_01_MASK 0x00000f00
-#define BCHP_MEMC_DDR_0_DRAM_MODE_6_GDDR5M_VREFD_OFFSET_01_SHIFT 8
-#define BCHP_MEMC_DDR_0_DRAM_MODE_6_GDDR5M_VREFD_OFFSET_01_DEFAULT 0x00000000
-
-/* MEMC_DDR_0 :: DRAM_MODE_6 :: GDDR5M :: VREFD_OFFSET_23 [07:04] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_6_GDDR5M_VREFD_OFFSET_23_MASK 0x000000f0
-#define BCHP_MEMC_DDR_0_DRAM_MODE_6_GDDR5M_VREFD_OFFSET_23_SHIFT 4
-#define BCHP_MEMC_DDR_0_DRAM_MODE_6_GDDR5M_VREFD_OFFSET_23_DEFAULT 0x00000000
-
-/* MEMC_DDR_0 :: DRAM_MODE_6 :: GDDR5M :: unused_2 [03:01] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_6_GDDR5M_unused_2_MASK 0x0000000e
-#define BCHP_MEMC_DDR_0_DRAM_MODE_6_GDDR5M_unused_2_SHIFT 1
-#define BCHP_MEMC_DDR_0_DRAM_MODE_6_GDDR5M_unused_2_DEFAULT 0x00000000
-
-/* MEMC_DDR_0 :: DRAM_MODE_6 :: GDDR5M :: WCK2CK_ALIGN [00:00] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_6_GDDR5M_WCK2CK_ALIGN_MASK 0x00000001
-#define BCHP_MEMC_DDR_0_DRAM_MODE_6_GDDR5M_WCK2CK_ALIGN_SHIFT 0
-#define BCHP_MEMC_DDR_0_DRAM_MODE_6_GDDR5M_WCK2CK_ALIGN_DEFAULT 0x00000000
-
-/* union - case GDDR5 [12:00] */
-/* MEMC_DDR_0 :: DRAM_MODE_6 :: GDDR5 :: unused_1 [12:12] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_6_GDDR5_unused_1_MASK 0x00001000
-#define BCHP_MEMC_DDR_0_DRAM_MODE_6_GDDR5_unused_1_SHIFT 12
-#define BCHP_MEMC_DDR_0_DRAM_MODE_6_GDDR5_unused_1_DEFAULT 0x00000000
-
-/* MEMC_DDR_0 :: DRAM_MODE_6 :: GDDR5 :: VREFD_OFFSET_01 [11:08] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_6_GDDR5_VREFD_OFFSET_01_MASK 0x00000f00
-#define BCHP_MEMC_DDR_0_DRAM_MODE_6_GDDR5_VREFD_OFFSET_01_SHIFT 8
-#define BCHP_MEMC_DDR_0_DRAM_MODE_6_GDDR5_VREFD_OFFSET_01_DEFAULT 0x00000000
-
-/* MEMC_DDR_0 :: DRAM_MODE_6 :: GDDR5 :: VREFD_OFFSET_23 [07:04] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_6_GDDR5_VREFD_OFFSET_23_MASK 0x000000f0
-#define BCHP_MEMC_DDR_0_DRAM_MODE_6_GDDR5_VREFD_OFFSET_23_SHIFT 4
-#define BCHP_MEMC_DDR_0_DRAM_MODE_6_GDDR5_VREFD_OFFSET_23_DEFAULT 0x00000000
-
-/* MEMC_DDR_0 :: DRAM_MODE_6 :: GDDR5 :: VREFD [03:03] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_6_GDDR5_VREFD_MASK 0x00000008
-#define BCHP_MEMC_DDR_0_DRAM_MODE_6_GDDR5_VREFD_SHIFT 3
-#define BCHP_MEMC_DDR_0_DRAM_MODE_6_GDDR5_VREFD_DEFAULT 0x00000000
-
-/* MEMC_DDR_0 :: DRAM_MODE_6 :: GDDR5 :: AUTO_VREFD [02:02] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_6_GDDR5_AUTO_VREFD_MASK 0x00000004
-#define BCHP_MEMC_DDR_0_DRAM_MODE_6_GDDR5_AUTO_VREFD_SHIFT 2
-#define BCHP_MEMC_DDR_0_DRAM_MODE_6_GDDR5_AUTO_VREFD_DEFAULT 0x00000000
-
-/* MEMC_DDR_0 :: DRAM_MODE_6 :: GDDR5 :: VREFD_MERGE [01:01] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_6_GDDR5_VREFD_MERGE_MASK 0x00000002
-#define BCHP_MEMC_DDR_0_DRAM_MODE_6_GDDR5_VREFD_MERGE_SHIFT 1
-#define BCHP_MEMC_DDR_0_DRAM_MODE_6_GDDR5_VREFD_MERGE_DEFAULT 0x00000000
-
-/* MEMC_DDR_0 :: DRAM_MODE_6 :: GDDR5 :: WCK2CK_ALIGN [00:00] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_6_GDDR5_WCK2CK_ALIGN_MASK 0x00000001
-#define BCHP_MEMC_DDR_0_DRAM_MODE_6_GDDR5_WCK2CK_ALIGN_SHIFT 0
-#define BCHP_MEMC_DDR_0_DRAM_MODE_6_GDDR5_WCK2CK_ALIGN_DEFAULT 0x00000000
-
-/* union - case Others [12:00] */
-/* MEMC_DDR_0 :: DRAM_MODE_6 :: Others :: unused_1 [12:00] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_6_Others_unused_1_MASK 0x00001fff
-#define BCHP_MEMC_DDR_0_DRAM_MODE_6_Others_unused_1_SHIFT 0
-#define BCHP_MEMC_DDR_0_DRAM_MODE_6_Others_unused_1_DEFAULT 0x00000000
-
-/***************************************************************************
- *DRAM_MODE_7 - Dram Mode Register 7
- ***************************************************************************/
-/* MEMC_DDR_0 :: DRAM_MODE_7 :: reserved0 [31:16] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_7_reserved0_MASK 0xffff0000
-#define BCHP_MEMC_DDR_0_DRAM_MODE_7_reserved0_SHIFT 16
-
-/* MEMC_DDR_0 :: DRAM_MODE_7 :: unused_0 [15:13] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_7_unused_0_MASK 0x0000e000
-#define BCHP_MEMC_DDR_0_DRAM_MODE_7_unused_0_SHIFT 13
-#define BCHP_MEMC_DDR_0_DRAM_MODE_7_unused_0_DEFAULT 0x00000000
-
-/* union - case GDDR5M [12:00] */
-/* MEMC_DDR_0 :: DRAM_MODE_7 :: GDDR5M :: unused_1 [12:12] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_7_GDDR5M_unused_1_MASK 0x00001000
-#define BCHP_MEMC_DDR_0_DRAM_MODE_7_GDDR5M_unused_1_SHIFT 12
-#define BCHP_MEMC_DDR_0_DRAM_MODE_7_GDDR5M_unused_1_DEFAULT 0x00000000
-
-/* MEMC_DDR_0 :: DRAM_MODE_7 :: GDDR5M :: DDC [11:10] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_7_GDDR5M_DDC_MASK 0x00000c00
-#define BCHP_MEMC_DDR_0_DRAM_MODE_7_GDDR5M_DDC_SHIFT 10
-#define BCHP_MEMC_DDR_0_DRAM_MODE_7_GDDR5M_DDC_DEFAULT 0x00000000
-
-/* MEMC_DDR_0 :: DRAM_MODE_7 :: GDDR5M :: VDD_RANGE [09:08] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_7_GDDR5M_VDD_RANGE_MASK 0x00000300
-#define BCHP_MEMC_DDR_0_DRAM_MODE_7_GDDR5M_VDD_RANGE_SHIFT 8
-#define BCHP_MEMC_DDR_0_DRAM_MODE_7_GDDR5M_VDD_RANGE_DEFAULT 0x00000000
-
-/* MEMC_DDR_0 :: DRAM_MODE_7 :: GDDR5M :: HALF_VREFD [07:07] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_7_GDDR5M_HALF_VREFD_MASK 0x00000080
-#define BCHP_MEMC_DDR_0_DRAM_MODE_7_GDDR5M_HALF_VREFD_SHIFT 7
-#define BCHP_MEMC_DDR_0_DRAM_MODE_7_GDDR5M_HALF_VREFD_DEFAULT 0x00000000
-
-/* MEMC_DDR_0 :: DRAM_MODE_7 :: GDDR5M :: TEMP_SENSE [06:06] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_7_GDDR5M_TEMP_SENSE_MASK 0x00000040
-#define BCHP_MEMC_DDR_0_DRAM_MODE_7_GDDR5M_TEMP_SENSE_SHIFT 6
-#define BCHP_MEMC_DDR_0_DRAM_MODE_7_GDDR5M_TEMP_SENSE_DEFAULT 0x00000000
-#define BCHP_MEMC_DDR_0_DRAM_MODE_7_GDDR5M_TEMP_SENSE_ENABLE 1
-#define BCHP_MEMC_DDR_0_DRAM_MODE_7_GDDR5M_TEMP_SENSE_DISABLE 0
-
-/* MEMC_DDR_0 :: DRAM_MODE_7 :: GDDR5M :: DQ_PREAMBLE [05:05] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_7_GDDR5M_DQ_PREAMBLE_MASK 0x00000020
-#define BCHP_MEMC_DDR_0_DRAM_MODE_7_GDDR5M_DQ_PREAMBLE_SHIFT 5
-#define BCHP_MEMC_DDR_0_DRAM_MODE_7_GDDR5M_DQ_PREAMBLE_DEFAULT 0x00000000
-#define BCHP_MEMC_DDR_0_DRAM_MODE_7_GDDR5M_DQ_PREAMBLE_ENABLE 1
-#define BCHP_MEMC_DDR_0_DRAM_MODE_7_GDDR5M_DQ_PREAMBLE_DISABLE 0
-
-/* MEMC_DDR_0 :: DRAM_MODE_7 :: GDDR5M :: WCK2CK_AUTO_SYNC [04:04] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_7_GDDR5M_WCK2CK_AUTO_SYNC_MASK 0x00000010
-#define BCHP_MEMC_DDR_0_DRAM_MODE_7_GDDR5M_WCK2CK_AUTO_SYNC_SHIFT 4
-#define BCHP_MEMC_DDR_0_DRAM_MODE_7_GDDR5M_WCK2CK_AUTO_SYNC_DEFAULT 0x00000000
-#define BCHP_MEMC_DDR_0_DRAM_MODE_7_GDDR5M_WCK2CK_AUTO_SYNC_ENABLE 1
-#define BCHP_MEMC_DDR_0_DRAM_MODE_7_GDDR5M_WCK2CK_AUTO_SYNC_DISABLE 0
-
-/* MEMC_DDR_0 :: DRAM_MODE_7 :: GDDR5M :: LOW_FREQ [03:03] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_7_GDDR5M_LOW_FREQ_MASK 0x00000008
-#define BCHP_MEMC_DDR_0_DRAM_MODE_7_GDDR5M_LOW_FREQ_SHIFT 3
-#define BCHP_MEMC_DDR_0_DRAM_MODE_7_GDDR5M_LOW_FREQ_DEFAULT 0x00000000
-#define BCHP_MEMC_DDR_0_DRAM_MODE_7_GDDR5M_LOW_FREQ_ENABLE 1
-#define BCHP_MEMC_DDR_0_DRAM_MODE_7_GDDR5M_LOW_FREQ_DISABLE 0
-
-/* MEMC_DDR_0 :: DRAM_MODE_7 :: GDDR5M :: unused_2 [02:00] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_7_GDDR5M_unused_2_MASK 0x00000007
-#define BCHP_MEMC_DDR_0_DRAM_MODE_7_GDDR5M_unused_2_SHIFT 0
-#define BCHP_MEMC_DDR_0_DRAM_MODE_7_GDDR5M_unused_2_DEFAULT 0x00000000
-
-/* union - case GDDR5 [12:00] */
-/* MEMC_DDR_0 :: DRAM_MODE_7 :: GDDR5 :: unused_1 [12:12] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_7_GDDR5_unused_1_MASK 0x00001000
-#define BCHP_MEMC_DDR_0_DRAM_MODE_7_GDDR5_unused_1_SHIFT 12
-#define BCHP_MEMC_DDR_0_DRAM_MODE_7_GDDR5_unused_1_DEFAULT 0x00000000
-
-/* MEMC_DDR_0 :: DRAM_MODE_7 :: GDDR5 :: DDC [11:10] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_7_GDDR5_DDC_MASK 0x00000c00
-#define BCHP_MEMC_DDR_0_DRAM_MODE_7_GDDR5_DDC_SHIFT 10
-#define BCHP_MEMC_DDR_0_DRAM_MODE_7_GDDR5_DDC_DEFAULT 0x00000000
-
-/* MEMC_DDR_0 :: DRAM_MODE_7 :: GDDR5 :: VDD_RANGE [09:08] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_7_GDDR5_VDD_RANGE_MASK 0x00000300
-#define BCHP_MEMC_DDR_0_DRAM_MODE_7_GDDR5_VDD_RANGE_SHIFT 8
-#define BCHP_MEMC_DDR_0_DRAM_MODE_7_GDDR5_VDD_RANGE_DEFAULT 0x00000000
-
-/* MEMC_DDR_0 :: DRAM_MODE_7 :: GDDR5 :: HALF_VREFD [07:07] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_7_GDDR5_HALF_VREFD_MASK 0x00000080
-#define BCHP_MEMC_DDR_0_DRAM_MODE_7_GDDR5_HALF_VREFD_SHIFT 7
-#define BCHP_MEMC_DDR_0_DRAM_MODE_7_GDDR5_HALF_VREFD_DEFAULT 0x00000000
-
-/* MEMC_DDR_0 :: DRAM_MODE_7 :: GDDR5 :: TEMP_SENSE [06:06] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_7_GDDR5_TEMP_SENSE_MASK 0x00000040
-#define BCHP_MEMC_DDR_0_DRAM_MODE_7_GDDR5_TEMP_SENSE_SHIFT 6
-#define BCHP_MEMC_DDR_0_DRAM_MODE_7_GDDR5_TEMP_SENSE_DEFAULT 0x00000000
-#define BCHP_MEMC_DDR_0_DRAM_MODE_7_GDDR5_TEMP_SENSE_ENABLE 1
-#define BCHP_MEMC_DDR_0_DRAM_MODE_7_GDDR5_TEMP_SENSE_DISABLE 0
-
-/* MEMC_DDR_0 :: DRAM_MODE_7 :: GDDR5 :: DQ_PREAMBLE [05:05] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_7_GDDR5_DQ_PREAMBLE_MASK 0x00000020
-#define BCHP_MEMC_DDR_0_DRAM_MODE_7_GDDR5_DQ_PREAMBLE_SHIFT 5
-#define BCHP_MEMC_DDR_0_DRAM_MODE_7_GDDR5_DQ_PREAMBLE_DEFAULT 0x00000000
-#define BCHP_MEMC_DDR_0_DRAM_MODE_7_GDDR5_DQ_PREAMBLE_ENABLE 1
-#define BCHP_MEMC_DDR_0_DRAM_MODE_7_GDDR5_DQ_PREAMBLE_DISABLE 0
-
-/* MEMC_DDR_0 :: DRAM_MODE_7 :: GDDR5 :: WCK2CK_AUTO_SYNC [04:04] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_7_GDDR5_WCK2CK_AUTO_SYNC_MASK 0x00000010
-#define BCHP_MEMC_DDR_0_DRAM_MODE_7_GDDR5_WCK2CK_AUTO_SYNC_SHIFT 4
-#define BCHP_MEMC_DDR_0_DRAM_MODE_7_GDDR5_WCK2CK_AUTO_SYNC_DEFAULT 0x00000000
-#define BCHP_MEMC_DDR_0_DRAM_MODE_7_GDDR5_WCK2CK_AUTO_SYNC_ENABLE 1
-#define BCHP_MEMC_DDR_0_DRAM_MODE_7_GDDR5_WCK2CK_AUTO_SYNC_DISABLE 0
-
-/* MEMC_DDR_0 :: DRAM_MODE_7 :: GDDR5 :: LOW_FREQ [03:03] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_7_GDDR5_LOW_FREQ_MASK 0x00000008
-#define BCHP_MEMC_DDR_0_DRAM_MODE_7_GDDR5_LOW_FREQ_SHIFT 3
-#define BCHP_MEMC_DDR_0_DRAM_MODE_7_GDDR5_LOW_FREQ_DEFAULT 0x00000000
-#define BCHP_MEMC_DDR_0_DRAM_MODE_7_GDDR5_LOW_FREQ_ENABLE 1
-#define BCHP_MEMC_DDR_0_DRAM_MODE_7_GDDR5_LOW_FREQ_DISABLE 0
-
-/* MEMC_DDR_0 :: DRAM_MODE_7 :: GDDR5 :: PLL_DELAY_COMP [02:02] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_7_GDDR5_PLL_DELAY_COMP_MASK 0x00000004
-#define BCHP_MEMC_DDR_0_DRAM_MODE_7_GDDR5_PLL_DELAY_COMP_SHIFT 2
-#define BCHP_MEMC_DDR_0_DRAM_MODE_7_GDDR5_PLL_DELAY_COMP_DEFAULT 0x00000000
-#define BCHP_MEMC_DDR_0_DRAM_MODE_7_GDDR5_PLL_DELAY_COMP_ENABLE 1
-#define BCHP_MEMC_DDR_0_DRAM_MODE_7_GDDR5_PLL_DELAY_COMP_DISABLE 0
-
-/* MEMC_DDR_0 :: DRAM_MODE_7 :: GDDR5 :: PLL_FAST_LOCK [01:01] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_7_GDDR5_PLL_FAST_LOCK_MASK 0x00000002
-#define BCHP_MEMC_DDR_0_DRAM_MODE_7_GDDR5_PLL_FAST_LOCK_SHIFT 1
-#define BCHP_MEMC_DDR_0_DRAM_MODE_7_GDDR5_PLL_FAST_LOCK_DEFAULT 0x00000000
-#define BCHP_MEMC_DDR_0_DRAM_MODE_7_GDDR5_PLL_FAST_LOCK_ENABLE 1
-#define BCHP_MEMC_DDR_0_DRAM_MODE_7_GDDR5_PLL_FAST_LOCK_DISABLE 0
-
-/* MEMC_DDR_0 :: DRAM_MODE_7 :: GDDR5 :: PLL_STANDBY [00:00] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_7_GDDR5_PLL_STANDBY_MASK 0x00000001
-#define BCHP_MEMC_DDR_0_DRAM_MODE_7_GDDR5_PLL_STANDBY_SHIFT 0
-#define BCHP_MEMC_DDR_0_DRAM_MODE_7_GDDR5_PLL_STANDBY_DEFAULT 0x00000000
-#define BCHP_MEMC_DDR_0_DRAM_MODE_7_GDDR5_PLL_STANDBY_ENABLE 1
-#define BCHP_MEMC_DDR_0_DRAM_MODE_7_GDDR5_PLL_STANDBY_DISABLE 0
-
-/* union - case Others [12:00] */
-/* MEMC_DDR_0 :: DRAM_MODE_7 :: Others :: unused_1 [12:00] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_7_Others_unused_1_MASK 0x00001fff
-#define BCHP_MEMC_DDR_0_DRAM_MODE_7_Others_unused_1_SHIFT 0
-#define BCHP_MEMC_DDR_0_DRAM_MODE_7_Others_unused_1_DEFAULT 0x00000000
-
-/***************************************************************************
- *DRAM_MODE_8 - Dram Mode Register 8
- ***************************************************************************/
-/* MEMC_DDR_0 :: DRAM_MODE_8 :: reserved0 [31:16] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_8_reserved0_MASK 0xffff0000
-#define BCHP_MEMC_DDR_0_DRAM_MODE_8_reserved0_SHIFT 16
-
-/* MEMC_DDR_0 :: DRAM_MODE_8 :: unused_0 [15:13] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_8_unused_0_MASK 0x0000e000
-#define BCHP_MEMC_DDR_0_DRAM_MODE_8_unused_0_SHIFT 13
-#define BCHP_MEMC_DDR_0_DRAM_MODE_8_unused_0_DEFAULT 0x00000000
-
-/* union - case GDDR5 [12:00] */
-/* MEMC_DDR_0 :: DRAM_MODE_8 :: GDDR5 :: unused_1 [12:02] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_8_GDDR5_unused_1_MASK 0x00001ffc
-#define BCHP_MEMC_DDR_0_DRAM_MODE_8_GDDR5_unused_1_SHIFT 2
-#define BCHP_MEMC_DDR_0_DRAM_MODE_8_GDDR5_unused_1_DEFAULT 0x00000000
-
-/* MEMC_DDR_0 :: DRAM_MODE_8 :: GDDR5 :: WR_EHF [01:01] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_8_GDDR5_WR_EHF_MASK 0x00000002
-#define BCHP_MEMC_DDR_0_DRAM_MODE_8_GDDR5_WR_EHF_SHIFT 1
-#define BCHP_MEMC_DDR_0_DRAM_MODE_8_GDDR5_WR_EHF_DEFAULT 0x00000000
-
-/* MEMC_DDR_0 :: DRAM_MODE_8 :: GDDR5 :: CL_EHF [00:00] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_8_GDDR5_CL_EHF_MASK 0x00000001
-#define BCHP_MEMC_DDR_0_DRAM_MODE_8_GDDR5_CL_EHF_SHIFT 0
-#define BCHP_MEMC_DDR_0_DRAM_MODE_8_GDDR5_CL_EHF_DEFAULT 0x00000000
-
-/* union - case Others [12:00] */
-/* MEMC_DDR_0 :: DRAM_MODE_8 :: Others :: unused_1 [12:00] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_8_Others_unused_1_MASK 0x00001fff
-#define BCHP_MEMC_DDR_0_DRAM_MODE_8_Others_unused_1_SHIFT 0
-#define BCHP_MEMC_DDR_0_DRAM_MODE_8_Others_unused_1_DEFAULT 0x00000000
-
-/***************************************************************************
- *DRAM_MODE_15 - Dram Mode Register 15
- ***************************************************************************/
-/* MEMC_DDR_0 :: DRAM_MODE_15 :: reserved0 [31:16] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_15_reserved0_MASK 0xffff0000
-#define BCHP_MEMC_DDR_0_DRAM_MODE_15_reserved0_SHIFT 16
-
-/* MEMC_DDR_0 :: DRAM_MODE_15 :: unused_0 [15:13] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_15_unused_0_MASK 0x0000e000
-#define BCHP_MEMC_DDR_0_DRAM_MODE_15_unused_0_SHIFT 13
-#define BCHP_MEMC_DDR_0_DRAM_MODE_15_unused_0_DEFAULT 0x00000000
-
-/* union - case GDDR5M [12:00] */
-/* MEMC_DDR_0 :: DRAM_MODE_15 :: GDDR5M :: unused_1 [12:12] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_15_GDDR5M_unused_1_MASK 0x00001000
-#define BCHP_MEMC_DDR_0_DRAM_MODE_15_GDDR5M_unused_1_SHIFT 12
-#define BCHP_MEMC_DDR_0_DRAM_MODE_15_GDDR5M_unused_1_DEFAULT 0x00000000
-
-/* MEMC_DDR_0 :: DRAM_MODE_15 :: GDDR5M :: ADDR_TRAINING [11:10] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_15_GDDR5M_ADDR_TRAINING_MASK 0x00000c00
-#define BCHP_MEMC_DDR_0_DRAM_MODE_15_GDDR5M_ADDR_TRAINING_SHIFT 10
-#define BCHP_MEMC_DDR_0_DRAM_MODE_15_GDDR5M_ADDR_TRAINING_DEFAULT 0x00000000
-
-/* MEMC_DDR_0 :: DRAM_MODE_15 :: GDDR5M :: MRE_MF1 [09:09] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_15_GDDR5M_MRE_MF1_MASK 0x00000200
-#define BCHP_MEMC_DDR_0_DRAM_MODE_15_GDDR5M_MRE_MF1_SHIFT 9
-#define BCHP_MEMC_DDR_0_DRAM_MODE_15_GDDR5M_MRE_MF1_DEFAULT 0x00000000
-#define BCHP_MEMC_DDR_0_DRAM_MODE_15_GDDR5M_MRE_MF1_ENABLE 0
-#define BCHP_MEMC_DDR_0_DRAM_MODE_15_GDDR5M_MRE_MF1_DISABLE 1
-
-/* MEMC_DDR_0 :: DRAM_MODE_15 :: GDDR5M :: MRE_MF2 [08:08] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_15_GDDR5M_MRE_MF2_MASK 0x00000100
-#define BCHP_MEMC_DDR_0_DRAM_MODE_15_GDDR5M_MRE_MF2_SHIFT 8
-#define BCHP_MEMC_DDR_0_DRAM_MODE_15_GDDR5M_MRE_MF2_DEFAULT 0x00000000
-#define BCHP_MEMC_DDR_0_DRAM_MODE_15_GDDR5M_MRE_MF2_ENABLE 0
-#define BCHP_MEMC_DDR_0_DRAM_MODE_15_GDDR5M_MRE_MF2_DISABLE 1
-
-/* MEMC_DDR_0 :: DRAM_MODE_15 :: GDDR5M :: unused_2 [07:00] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_15_GDDR5M_unused_2_MASK 0x000000ff
-#define BCHP_MEMC_DDR_0_DRAM_MODE_15_GDDR5M_unused_2_SHIFT 0
-#define BCHP_MEMC_DDR_0_DRAM_MODE_15_GDDR5M_unused_2_DEFAULT 0x00000000
-
-/* union - case GDDR5 [12:00] */
-/* MEMC_DDR_0 :: DRAM_MODE_15 :: GDDR5 :: unused_1 [12:11] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_15_GDDR5_unused_1_MASK 0x00001800
-#define BCHP_MEMC_DDR_0_DRAM_MODE_15_GDDR5_unused_1_SHIFT 11
-#define BCHP_MEMC_DDR_0_DRAM_MODE_15_GDDR5_unused_1_DEFAULT 0x00000000
-
-/* MEMC_DDR_0 :: DRAM_MODE_15 :: GDDR5 :: ADDR_TRAINING [10:10] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_15_GDDR5_ADDR_TRAINING_MASK 0x00000400
-#define BCHP_MEMC_DDR_0_DRAM_MODE_15_GDDR5_ADDR_TRAINING_SHIFT 10
-#define BCHP_MEMC_DDR_0_DRAM_MODE_15_GDDR5_ADDR_TRAINING_DEFAULT 0x00000000
-#define BCHP_MEMC_DDR_0_DRAM_MODE_15_GDDR5_ADDR_TRAINING_ENABLE 1
-#define BCHP_MEMC_DDR_0_DRAM_MODE_15_GDDR5_ADDR_TRAINING_DISABLE 0
-
-/* MEMC_DDR_0 :: DRAM_MODE_15 :: GDDR5 :: MRE_MF1 [09:09] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_15_GDDR5_MRE_MF1_MASK 0x00000200
-#define BCHP_MEMC_DDR_0_DRAM_MODE_15_GDDR5_MRE_MF1_SHIFT 9
-#define BCHP_MEMC_DDR_0_DRAM_MODE_15_GDDR5_MRE_MF1_DEFAULT 0x00000000
-#define BCHP_MEMC_DDR_0_DRAM_MODE_15_GDDR5_MRE_MF1_ENABLE 0
-#define BCHP_MEMC_DDR_0_DRAM_MODE_15_GDDR5_MRE_MF1_DISABLE 1
-
-/* MEMC_DDR_0 :: DRAM_MODE_15 :: GDDR5 :: MRE_MF2 [08:08] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_15_GDDR5_MRE_MF2_MASK 0x00000100
-#define BCHP_MEMC_DDR_0_DRAM_MODE_15_GDDR5_MRE_MF2_SHIFT 8
-#define BCHP_MEMC_DDR_0_DRAM_MODE_15_GDDR5_MRE_MF2_DEFAULT 0x00000000
-#define BCHP_MEMC_DDR_0_DRAM_MODE_15_GDDR5_MRE_MF2_ENABLE 0
-#define BCHP_MEMC_DDR_0_DRAM_MODE_15_GDDR5_MRE_MF2_DISABLE 1
-
-/* MEMC_DDR_0 :: DRAM_MODE_15 :: GDDR5 :: unused_2 [07:00] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_15_GDDR5_unused_2_MASK 0x000000ff
-#define BCHP_MEMC_DDR_0_DRAM_MODE_15_GDDR5_unused_2_SHIFT 0
-#define BCHP_MEMC_DDR_0_DRAM_MODE_15_GDDR5_unused_2_DEFAULT 0x00000000
-
-/* union - case Others [12:00] */
-/* MEMC_DDR_0 :: DRAM_MODE_15 :: Others :: unused_1 [12:00] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_15_Others_unused_1_MASK 0x00001fff
-#define BCHP_MEMC_DDR_0_DRAM_MODE_15_Others_unused_1_SHIFT 0
-#define BCHP_MEMC_DDR_0_DRAM_MODE_15_Others_unused_1_DEFAULT 0x00000000
-
-/***************************************************************************
- *PPD_CONFIG - Precharge power down mode configuration register
- ***************************************************************************/
-/* MEMC_DDR_0 :: PPD_CONFIG :: reserved0 [31:15] */
-#define BCHP_MEMC_DDR_0_PPD_CONFIG_reserved0_MASK 0xffff8000
-#define BCHP_MEMC_DDR_0_PPD_CONFIG_reserved0_SHIFT 15
-
-/* MEMC_DDR_0 :: PPD_CONFIG :: FORCE_PPD_EXIT [14:14] */
-#define BCHP_MEMC_DDR_0_PPD_CONFIG_FORCE_PPD_EXIT_MASK 0x00004000
-#define BCHP_MEMC_DDR_0_PPD_CONFIG_FORCE_PPD_EXIT_SHIFT 14
-#define BCHP_MEMC_DDR_0_PPD_CONFIG_FORCE_PPD_EXIT_DEFAULT 0x00000000
-
-/* MEMC_DDR_0 :: PPD_CONFIG :: PPD_FORCE [13:13] */
-#define BCHP_MEMC_DDR_0_PPD_CONFIG_PPD_FORCE_MASK 0x00002000
-#define BCHP_MEMC_DDR_0_PPD_CONFIG_PPD_FORCE_SHIFT 13
-#define BCHP_MEMC_DDR_0_PPD_CONFIG_PPD_FORCE_DEFAULT 0x00000000
-
-/* MEMC_DDR_0 :: PPD_CONFIG :: PPD_EN [12:12] */
-#define BCHP_MEMC_DDR_0_PPD_CONFIG_PPD_EN_MASK 0x00001000
-#define BCHP_MEMC_DDR_0_PPD_CONFIG_PPD_EN_SHIFT 12
-#define BCHP_MEMC_DDR_0_PPD_CONFIG_PPD_EN_DEFAULT 0x00000000
-
-/* MEMC_DDR_0 :: PPD_CONFIG :: INACT_COUNT [11:00] */
-#define BCHP_MEMC_DDR_0_PPD_CONFIG_INACT_COUNT_MASK 0x00000fff
-#define BCHP_MEMC_DDR_0_PPD_CONFIG_INACT_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_PPD_CONFIG_INACT_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *SRPD_CONFIG - Self-refresh power down mode configuration register
- ***************************************************************************/
-/* MEMC_DDR_0 :: SRPD_CONFIG :: reserved0 [31:18] */
-#define BCHP_MEMC_DDR_0_SRPD_CONFIG_reserved0_MASK 0xfffc0000
-#define BCHP_MEMC_DDR_0_SRPD_CONFIG_reserved0_SHIFT 18
-
-/* MEMC_DDR_0 :: SRPD_CONFIG :: FORCE_SRPD_EXIT [17:17] */
-#define BCHP_MEMC_DDR_0_SRPD_CONFIG_FORCE_SRPD_EXIT_MASK 0x00020000
-#define BCHP_MEMC_DDR_0_SRPD_CONFIG_FORCE_SRPD_EXIT_SHIFT 17
-#define BCHP_MEMC_DDR_0_SRPD_CONFIG_FORCE_SRPD_EXIT_DEFAULT 0x00000000
-
-/* MEMC_DDR_0 :: SRPD_CONFIG :: SRPD_EN [16:16] */
-#define BCHP_MEMC_DDR_0_SRPD_CONFIG_SRPD_EN_MASK 0x00010000
-#define BCHP_MEMC_DDR_0_SRPD_CONFIG_SRPD_EN_SHIFT 16
-#define BCHP_MEMC_DDR_0_SRPD_CONFIG_SRPD_EN_DEFAULT 0x00000000
-
-/* MEMC_DDR_0 :: SRPD_CONFIG :: INACT_COUNT [15:00] */
-#define BCHP_MEMC_DDR_0_SRPD_CONFIG_INACT_COUNT_MASK 0x0000ffff
-#define BCHP_MEMC_DDR_0_SRPD_CONFIG_INACT_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_SRPD_CONFIG_INACT_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *SSPD_CMD - Software standby power down mode
- ***************************************************************************/
-/* MEMC_DDR_0 :: SSPD_CMD :: reserved0 [31:01] */
-#define BCHP_MEMC_DDR_0_SSPD_CMD_reserved0_MASK 0xfffffffe
-#define BCHP_MEMC_DDR_0_SSPD_CMD_reserved0_SHIFT 1
-
-/* MEMC_DDR_0 :: SSPD_CMD :: SSPD [00:00] */
-#define BCHP_MEMC_DDR_0_SSPD_CMD_SSPD_MASK 0x00000001
-#define BCHP_MEMC_DDR_0_SSPD_CMD_SSPD_SHIFT 0
-#define BCHP_MEMC_DDR_0_SSPD_CMD_SSPD_DEFAULT 0x00000000
-
-/***************************************************************************
- *POWER_DOWN_STATUS - Power down status
- ***************************************************************************/
-/* MEMC_DDR_0 :: POWER_DOWN_STATUS :: reserved0 [31:03] */
-#define BCHP_MEMC_DDR_0_POWER_DOWN_STATUS_reserved0_MASK 0xfffffff8
-#define BCHP_MEMC_DDR_0_POWER_DOWN_STATUS_reserved0_SHIFT 3
-
-/* MEMC_DDR_0 :: POWER_DOWN_STATUS :: SSPD [02:02] */
-#define BCHP_MEMC_DDR_0_POWER_DOWN_STATUS_SSPD_MASK 0x00000004
-#define BCHP_MEMC_DDR_0_POWER_DOWN_STATUS_SSPD_SHIFT 2
-#define BCHP_MEMC_DDR_0_POWER_DOWN_STATUS_SSPD_DEFAULT 0x00000000
-
-/* MEMC_DDR_0 :: POWER_DOWN_STATUS :: SRPD [01:01] */
-#define BCHP_MEMC_DDR_0_POWER_DOWN_STATUS_SRPD_MASK 0x00000002
-#define BCHP_MEMC_DDR_0_POWER_DOWN_STATUS_SRPD_SHIFT 1
-#define BCHP_MEMC_DDR_0_POWER_DOWN_STATUS_SRPD_DEFAULT 0x00000000
-
-/* MEMC_DDR_0 :: POWER_DOWN_STATUS :: PPD [00:00] */
-#define BCHP_MEMC_DDR_0_POWER_DOWN_STATUS_PPD_MASK 0x00000001
-#define BCHP_MEMC_DDR_0_POWER_DOWN_STATUS_PPD_SHIFT 0
-#define BCHP_MEMC_DDR_0_POWER_DOWN_STATUS_PPD_DEFAULT 0x00000000
-
-/***************************************************************************
- *WARM_BOOT - Warm boot control registers
- ***************************************************************************/
-/* MEMC_DDR_0 :: WARM_BOOT :: reserved0 [31:01] */
-#define BCHP_MEMC_DDR_0_WARM_BOOT_reserved0_MASK 0xfffffffe
-#define BCHP_MEMC_DDR_0_WARM_BOOT_reserved0_SHIFT 1
-
-/* MEMC_DDR_0 :: WARM_BOOT :: WARM_BOOT [00:00] */
-#define BCHP_MEMC_DDR_0_WARM_BOOT_WARM_BOOT_MASK 0x00000001
-#define BCHP_MEMC_DDR_0_WARM_BOOT_WARM_BOOT_SHIFT 0
-#define BCHP_MEMC_DDR_0_WARM_BOOT_WARM_BOOT_DEFAULT 0x00000000
-
-/***************************************************************************
- *DRAM_TIMING_0 - DDR-SDRAM Timing Register 0
- ***************************************************************************/
-/* MEMC_DDR_0 :: DRAM_TIMING_0 :: TRRD_NOP [31:24] */
-#define BCHP_MEMC_DDR_0_DRAM_TIMING_0_TRRD_NOP_MASK 0xff000000
-#define BCHP_MEMC_DDR_0_DRAM_TIMING_0_TRRD_NOP_SHIFT 24
-#define BCHP_MEMC_DDR_0_DRAM_TIMING_0_TRRD_NOP_DEFAULT 0x00000006
-
-/* MEMC_DDR_0 :: DRAM_TIMING_0 :: TRCD_NOP [23:16] */
-#define BCHP_MEMC_DDR_0_DRAM_TIMING_0_TRCD_NOP_MASK 0x00ff0000
-#define BCHP_MEMC_DDR_0_DRAM_TIMING_0_TRCD_NOP_SHIFT 16
-#define BCHP_MEMC_DDR_0_DRAM_TIMING_0_TRCD_NOP_DEFAULT 0x00000008
-
-/* MEMC_DDR_0 :: DRAM_TIMING_0 :: TRP_NOP [15:08] */
-#define BCHP_MEMC_DDR_0_DRAM_TIMING_0_TRP_NOP_MASK 0x0000ff00
-#define BCHP_MEMC_DDR_0_DRAM_TIMING_0_TRP_NOP_SHIFT 8
-#define BCHP_MEMC_DDR_0_DRAM_TIMING_0_TRP_NOP_DEFAULT 0x00000008
-
-/* MEMC_DDR_0 :: DRAM_TIMING_0 :: TRAS_NOP [07:00] */
-#define BCHP_MEMC_DDR_0_DRAM_TIMING_0_TRAS_NOP_MASK 0x000000ff
-#define BCHP_MEMC_DDR_0_DRAM_TIMING_0_TRAS_NOP_SHIFT 0
-#define BCHP_MEMC_DDR_0_DRAM_TIMING_0_TRAS_NOP_DEFAULT 0x00000014
-
-/***************************************************************************
- *DRAM_TIMING_1 - DDR-SDRAM Timing Register 1
- ***************************************************************************/
-/* MEMC_DDR_0 :: DRAM_TIMING_1 :: reserved0 [31:28] */
-#define BCHP_MEMC_DDR_0_DRAM_TIMING_1_reserved0_MASK 0xf0000000
-#define BCHP_MEMC_DDR_0_DRAM_TIMING_1_reserved0_SHIFT 28
-
-/* MEMC_DDR_0 :: DRAM_TIMING_1 :: T32AW_NOP [27:16] */
-#define BCHP_MEMC_DDR_0_DRAM_TIMING_1_T32AW_NOP_MASK 0x0fff0000
-#define BCHP_MEMC_DDR_0_DRAM_TIMING_1_T32AW_NOP_SHIFT 16
-#define BCHP_MEMC_DDR_0_DRAM_TIMING_1_T32AW_NOP_DEFAULT 0x00000020
-
-/* MEMC_DDR_0 :: DRAM_TIMING_1 :: TFAW_NOP [15:08] */
-#define BCHP_MEMC_DDR_0_DRAM_TIMING_1_TFAW_NOP_MASK 0x0000ff00
-#define BCHP_MEMC_DDR_0_DRAM_TIMING_1_TFAW_NOP_SHIFT 8
-#define BCHP_MEMC_DDR_0_DRAM_TIMING_1_TFAW_NOP_DEFAULT 0x0000001b
-
-/* MEMC_DDR_0 :: DRAM_TIMING_1 :: TRTP_NOP [07:00] */
-#define BCHP_MEMC_DDR_0_DRAM_TIMING_1_TRTP_NOP_MASK 0x000000ff
-#define BCHP_MEMC_DDR_0_DRAM_TIMING_1_TRTP_NOP_SHIFT 0
-#define BCHP_MEMC_DDR_0_DRAM_TIMING_1_TRTP_NOP_DEFAULT 0x00000004
-
-/***************************************************************************
- *DRAM_TIMING_2 - Read to Write & write to read timing register
- ***************************************************************************/
-/* MEMC_DDR_0 :: DRAM_TIMING_2 :: TRRDL_NOP [31:24] */
-#define BCHP_MEMC_DDR_0_DRAM_TIMING_2_TRRDL_NOP_MASK 0xff000000
-#define BCHP_MEMC_DDR_0_DRAM_TIMING_2_TRRDL_NOP_SHIFT 24
-#define BCHP_MEMC_DDR_0_DRAM_TIMING_2_TRRDL_NOP_DEFAULT 0x00000006
-
-/* MEMC_DDR_0 :: DRAM_TIMING_2 :: WR2RDL_NOP [23:16] */
-#define BCHP_MEMC_DDR_0_DRAM_TIMING_2_WR2RDL_NOP_MASK 0x00ff0000
-#define BCHP_MEMC_DDR_0_DRAM_TIMING_2_WR2RDL_NOP_SHIFT 16
-#define BCHP_MEMC_DDR_0_DRAM_TIMING_2_WR2RDL_NOP_DEFAULT 0x0000000e
-
-/* MEMC_DDR_0 :: DRAM_TIMING_2 :: WR2RD_NOP [15:08] */
-#define BCHP_MEMC_DDR_0_DRAM_TIMING_2_WR2RD_NOP_MASK 0x0000ff00
-#define BCHP_MEMC_DDR_0_DRAM_TIMING_2_WR2RD_NOP_SHIFT 8
-#define BCHP_MEMC_DDR_0_DRAM_TIMING_2_WR2RD_NOP_DEFAULT 0x0000000e
-
-/* MEMC_DDR_0 :: DRAM_TIMING_2 :: RD2WR_NOP [07:00] */
-#define BCHP_MEMC_DDR_0_DRAM_TIMING_2_RD2WR_NOP_MASK 0x000000ff
-#define BCHP_MEMC_DDR_0_DRAM_TIMING_2_RD2WR_NOP_SHIFT 0
-#define BCHP_MEMC_DDR_0_DRAM_TIMING_2_RD2WR_NOP_DEFAULT 0x00000009
-
-/***************************************************************************
- *DRAM_TIMING_3 - DDR-SDRAM Timing Register 3
- ***************************************************************************/
-/* MEMC_DDR_0 :: DRAM_TIMING_3 :: TRCDWR_NOP [31:24] */
-#define BCHP_MEMC_DDR_0_DRAM_TIMING_3_TRCDWR_NOP_MASK 0xff000000
-#define BCHP_MEMC_DDR_0_DRAM_TIMING_3_TRCDWR_NOP_SHIFT 24
-#define BCHP_MEMC_DDR_0_DRAM_TIMING_3_TRCDWR_NOP_DEFAULT 0x00000008
-
-/* MEMC_DDR_0 :: DRAM_TIMING_3 :: CKENB_CKE_DELAY [23:16] */
-#define BCHP_MEMC_DDR_0_DRAM_TIMING_3_CKENB_CKE_DELAY_MASK 0x00ff0000
-#define BCHP_MEMC_DDR_0_DRAM_TIMING_3_CKENB_CKE_DELAY_SHIFT 16
-#define BCHP_MEMC_DDR_0_DRAM_TIMING_3_CKENB_CKE_DELAY_DEFAULT 0x0000000c
-
-/* MEMC_DDR_0 :: DRAM_TIMING_3 :: PRECHARGE_ALL_DELAY [15:08] */
-#define BCHP_MEMC_DDR_0_DRAM_TIMING_3_PRECHARGE_ALL_DELAY_MASK 0x0000ff00
-#define BCHP_MEMC_DDR_0_DRAM_TIMING_3_PRECHARGE_ALL_DELAY_SHIFT 8
-#define BCHP_MEMC_DDR_0_DRAM_TIMING_3_PRECHARGE_ALL_DELAY_DEFAULT 0x00000008
-
-/* MEMC_DDR_0 :: DRAM_TIMING_3 :: LOAD_MODE_DELAY [07:00] */
-#define BCHP_MEMC_DDR_0_DRAM_TIMING_3_LOAD_MODE_DELAY_MASK 0x000000ff
-#define BCHP_MEMC_DDR_0_DRAM_TIMING_3_LOAD_MODE_DELAY_SHIFT 0
-#define BCHP_MEMC_DDR_0_DRAM_TIMING_3_LOAD_MODE_DELAY_DEFAULT 0x0000000c
-
-/***************************************************************************
- *DRAM_TIMING_4 - DDR-SDRAM Timing Register 4
- ***************************************************************************/
-/* MEMC_DDR_0 :: DRAM_TIMING_4 :: reserved0 [31:24] */
-#define BCHP_MEMC_DDR_0_DRAM_TIMING_4_reserved0_MASK 0xff000000
-#define BCHP_MEMC_DDR_0_DRAM_TIMING_4_reserved0_SHIFT 24
-
-/* MEMC_DDR_0 :: DRAM_TIMING_4 :: REFRESH_DELAY [23:12] */
-#define BCHP_MEMC_DDR_0_DRAM_TIMING_4_REFRESH_DELAY_MASK 0x00fff000
-#define BCHP_MEMC_DDR_0_DRAM_TIMING_4_REFRESH_DELAY_SHIFT 12
-#define BCHP_MEMC_DDR_0_DRAM_TIMING_4_REFRESH_DELAY_DEFAULT 0x00000058
-
-/* MEMC_DDR_0 :: DRAM_TIMING_4 :: ZQCALIB_DELAY [11:00] */
-#define BCHP_MEMC_DDR_0_DRAM_TIMING_4_ZQCALIB_DELAY_MASK 0x00000fff
-#define BCHP_MEMC_DDR_0_DRAM_TIMING_4_ZQCALIB_DELAY_SHIFT 0
-#define BCHP_MEMC_DDR_0_DRAM_TIMING_4_ZQCALIB_DELAY_DEFAULT 0x00000200
-
-/***************************************************************************
- *DRAM_TIMING_5 - DDR-SDRAM Timing Register 5
- ***************************************************************************/
-/* MEMC_DDR_0 :: DRAM_TIMING_5 :: reserved0 [31:30] */
-#define BCHP_MEMC_DDR_0_DRAM_TIMING_5_reserved0_MASK 0xc0000000
-#define BCHP_MEMC_DDR_0_DRAM_TIMING_5_reserved0_SHIFT 30
-
-/* MEMC_DDR_0 :: DRAM_TIMING_5 :: CKE_MIN_WIDTH [29:22] */
-#define BCHP_MEMC_DDR_0_DRAM_TIMING_5_CKE_MIN_WIDTH_MASK 0x3fc00000
-#define BCHP_MEMC_DDR_0_DRAM_TIMING_5_CKE_MIN_WIDTH_SHIFT 22
-#define BCHP_MEMC_DDR_0_DRAM_TIMING_5_CKE_MIN_WIDTH_DEFAULT 0x00000003
-
-/* MEMC_DDR_0 :: DRAM_TIMING_5 :: PWDN_EXIT_DELAY [21:12] */
-#define BCHP_MEMC_DDR_0_DRAM_TIMING_5_PWDN_EXIT_DELAY_MASK 0x003ff000
-#define BCHP_MEMC_DDR_0_DRAM_TIMING_5_PWDN_EXIT_DELAY_SHIFT 12
-#define BCHP_MEMC_DDR_0_DRAM_TIMING_5_PWDN_EXIT_DELAY_DEFAULT 0x0000000d
-
-/* MEMC_DDR_0 :: DRAM_TIMING_5 :: SELFREF_EXIT_DELAY [11:00] */
-#define BCHP_MEMC_DDR_0_DRAM_TIMING_5_SELFREF_EXIT_DELAY_MASK 0x00000fff
-#define BCHP_MEMC_DDR_0_DRAM_TIMING_5_SELFREF_EXIT_DELAY_SHIFT 0
-#define BCHP_MEMC_DDR_0_DRAM_TIMING_5_SELFREF_EXIT_DELAY_DEFAULT 0x00000200
-
-/***************************************************************************
- *MIN_DQ_IDLE_CONTROL - Minimum DQ Idle Time Control
- ***************************************************************************/
-/* MEMC_DDR_0 :: MIN_DQ_IDLE_CONTROL :: reserved0 [31:23] */
-#define BCHP_MEMC_DDR_0_MIN_DQ_IDLE_CONTROL_reserved0_MASK 0xff800000
-#define BCHP_MEMC_DDR_0_MIN_DQ_IDLE_CONTROL_reserved0_SHIFT 23
-
-/* MEMC_DDR_0 :: MIN_DQ_IDLE_CONTROL :: WriteDelay [22:20] */
-#define BCHP_MEMC_DDR_0_MIN_DQ_IDLE_CONTROL_WriteDelay_MASK 0x00700000
-#define BCHP_MEMC_DDR_0_MIN_DQ_IDLE_CONTROL_WriteDelay_SHIFT 20
-#define BCHP_MEMC_DDR_0_MIN_DQ_IDLE_CONTROL_WriteDelay_DEFAULT 0x00000000
-
-/* MEMC_DDR_0 :: MIN_DQ_IDLE_CONTROL :: reserved1 [19:18] */
-#define BCHP_MEMC_DDR_0_MIN_DQ_IDLE_CONTROL_reserved1_MASK 0x000c0000
-#define BCHP_MEMC_DDR_0_MIN_DQ_IDLE_CONTROL_reserved1_SHIFT 18
-
-/* MEMC_DDR_0 :: MIN_DQ_IDLE_CONTROL :: WriteForceIdle [17:17] */
-#define BCHP_MEMC_DDR_0_MIN_DQ_IDLE_CONTROL_WriteForceIdle_MASK 0x00020000
-#define BCHP_MEMC_DDR_0_MIN_DQ_IDLE_CONTROL_WriteForceIdle_SHIFT 17
-#define BCHP_MEMC_DDR_0_MIN_DQ_IDLE_CONTROL_WriteForceIdle_DEFAULT 0x00000000
-
-/* MEMC_DDR_0 :: MIN_DQ_IDLE_CONTROL :: WriteEnable [16:16] */
-#define BCHP_MEMC_DDR_0_MIN_DQ_IDLE_CONTROL_WriteEnable_MASK 0x00010000
-#define BCHP_MEMC_DDR_0_MIN_DQ_IDLE_CONTROL_WriteEnable_SHIFT 16
-#define BCHP_MEMC_DDR_0_MIN_DQ_IDLE_CONTROL_WriteEnable_DEFAULT 0x00000000
-
-/* MEMC_DDR_0 :: MIN_DQ_IDLE_CONTROL :: reserved2 [15:07] */
-#define BCHP_MEMC_DDR_0_MIN_DQ_IDLE_CONTROL_reserved2_MASK 0x0000ff80
-#define BCHP_MEMC_DDR_0_MIN_DQ_IDLE_CONTROL_reserved2_SHIFT 7
-
-/* MEMC_DDR_0 :: MIN_DQ_IDLE_CONTROL :: ReadDelay [06:04] */
-#define BCHP_MEMC_DDR_0_MIN_DQ_IDLE_CONTROL_ReadDelay_MASK 0x00000070
-#define BCHP_MEMC_DDR_0_MIN_DQ_IDLE_CONTROL_ReadDelay_SHIFT 4
-#define BCHP_MEMC_DDR_0_MIN_DQ_IDLE_CONTROL_ReadDelay_DEFAULT 0x00000000
-
-/* MEMC_DDR_0 :: MIN_DQ_IDLE_CONTROL :: reserved3 [03:02] */
-#define BCHP_MEMC_DDR_0_MIN_DQ_IDLE_CONTROL_reserved3_MASK 0x0000000c
-#define BCHP_MEMC_DDR_0_MIN_DQ_IDLE_CONTROL_reserved3_SHIFT 2
-
-/* MEMC_DDR_0 :: MIN_DQ_IDLE_CONTROL :: ReadForceIdle [01:01] */
-#define BCHP_MEMC_DDR_0_MIN_DQ_IDLE_CONTROL_ReadForceIdle_MASK 0x00000002
-#define BCHP_MEMC_DDR_0_MIN_DQ_IDLE_CONTROL_ReadForceIdle_SHIFT 1
-#define BCHP_MEMC_DDR_0_MIN_DQ_IDLE_CONTROL_ReadForceIdle_DEFAULT 0x00000000
-
-/* MEMC_DDR_0 :: MIN_DQ_IDLE_CONTROL :: ReadEnable [00:00] */
-#define BCHP_MEMC_DDR_0_MIN_DQ_IDLE_CONTROL_ReadEnable_MASK 0x00000001
-#define BCHP_MEMC_DDR_0_MIN_DQ_IDLE_CONTROL_ReadEnable_SHIFT 0
-#define BCHP_MEMC_DDR_0_MIN_DQ_IDLE_CONTROL_ReadEnable_DEFAULT 0x00000000
-
-/***************************************************************************
- *PHY_OP_ACCESS_PENALTY - PHY Operational Access Penalty Count.
- ***************************************************************************/
-/* MEMC_DDR_0 :: PHY_OP_ACCESS_PENALTY :: PHY_OP_ACCESS_WAIT_PENALTY [31:00] */
-#define BCHP_MEMC_DDR_0_PHY_OP_ACCESS_PENALTY_PHY_OP_ACCESS_WAIT_PENALTY_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_PHY_OP_ACCESS_PENALTY_PHY_OP_ACCESS_WAIT_PENALTY_SHIFT 0
-#define BCHP_MEMC_DDR_0_PHY_OP_ACCESS_PENALTY_PHY_OP_ACCESS_WAIT_PENALTY_DEFAULT 0x00000004
-
-/***************************************************************************
- *CNTRLR_SM_TIMEOUT - Memory Controller , state machine timeout register.
- ***************************************************************************/
-/* MEMC_DDR_0 :: CNTRLR_SM_TIMEOUT :: reserved0 [31:17] */
-#define BCHP_MEMC_DDR_0_CNTRLR_SM_TIMEOUT_reserved0_MASK 0xfffe0000
-#define BCHP_MEMC_DDR_0_CNTRLR_SM_TIMEOUT_reserved0_SHIFT 17
-
-/* MEMC_DDR_0 :: CNTRLR_SM_TIMEOUT :: ENABLE [16:16] */
-#define BCHP_MEMC_DDR_0_CNTRLR_SM_TIMEOUT_ENABLE_MASK 0x00010000
-#define BCHP_MEMC_DDR_0_CNTRLR_SM_TIMEOUT_ENABLE_SHIFT 16
-#define BCHP_MEMC_DDR_0_CNTRLR_SM_TIMEOUT_ENABLE_DEFAULT 0x00000000
-
-/* MEMC_DDR_0 :: CNTRLR_SM_TIMEOUT :: COUNT [15:00] */
-#define BCHP_MEMC_DDR_0_CNTRLR_SM_TIMEOUT_COUNT_MASK 0x0000ffff
-#define BCHP_MEMC_DDR_0_CNTRLR_SM_TIMEOUT_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_CNTRLR_SM_TIMEOUT_COUNT_DEFAULT 0x0000ffff
-
-/***************************************************************************
- *BANK_STATUS - Memory Controller, Bank Status Register
- ***************************************************************************/
-/* MEMC_DDR_0 :: BANK_STATUS :: reserved0 [31:16] */
-#define BCHP_MEMC_DDR_0_BANK_STATUS_reserved0_MASK 0xffff0000
-#define BCHP_MEMC_DDR_0_BANK_STATUS_reserved0_SHIFT 16
-
-/* MEMC_DDR_0 :: BANK_STATUS :: BANK_STATUS [15:00] */
-#define BCHP_MEMC_DDR_0_BANK_STATUS_BANK_STATUS_MASK 0x0000ffff
-#define BCHP_MEMC_DDR_0_BANK_STATUS_BANK_STATUS_SHIFT 0
-#define BCHP_MEMC_DDR_0_BANK_STATUS_BANK_STATUS_DEFAULT 0x0000ffff
-
-/***************************************************************************
- *TESTER_LATENCY - Memory Controller, Tester Latency Register.
- ***************************************************************************/
-/* MEMC_DDR_0 :: TESTER_LATENCY :: reserved0 [31:08] */
-#define BCHP_MEMC_DDR_0_TESTER_LATENCY_reserved0_MASK 0xffffff00
-#define BCHP_MEMC_DDR_0_TESTER_LATENCY_reserved0_SHIFT 8
-
-/* MEMC_DDR_0 :: TESTER_LATENCY :: TLATENCY_SEL [07:00] */
-#define BCHP_MEMC_DDR_0_TESTER_LATENCY_TLATENCY_SEL_MASK 0x000000ff
-#define BCHP_MEMC_DDR_0_TESTER_LATENCY_TLATENCY_SEL_SHIFT 0
-#define BCHP_MEMC_DDR_0_TESTER_LATENCY_TLATENCY_SEL_DEFAULT 0x00000000
-
-/***************************************************************************
- *SEQ_RING_BUF_DEPTH - Sequencer Ring Buffer programmable depth.
- ***************************************************************************/
-/* MEMC_DDR_0 :: SEQ_RING_BUF_DEPTH :: reserved0 [31:05] */
-#define BCHP_MEMC_DDR_0_SEQ_RING_BUF_DEPTH_reserved0_MASK 0xffffffe0
-#define BCHP_MEMC_DDR_0_SEQ_RING_BUF_DEPTH_reserved0_SHIFT 5
-
-/* MEMC_DDR_0 :: SEQ_RING_BUF_DEPTH :: RING_BUF_DEPTH [04:00] */
-#define BCHP_MEMC_DDR_0_SEQ_RING_BUF_DEPTH_RING_BUF_DEPTH_MASK 0x0000001f
-#define BCHP_MEMC_DDR_0_SEQ_RING_BUF_DEPTH_RING_BUF_DEPTH_SHIFT 0
-#define BCHP_MEMC_DDR_0_SEQ_RING_BUF_DEPTH_RING_BUF_DEPTH_DEFAULT 0x00000010
-
-/***************************************************************************
- *SEQ_WRDATA_ERR_INFO - Sequencer write data error info
- ***************************************************************************/
-/* MEMC_DDR_0 :: SEQ_WRDATA_ERR_INFO :: reserved0 [31:21] */
-#define BCHP_MEMC_DDR_0_SEQ_WRDATA_ERR_INFO_reserved0_MASK 0xffe00000
-#define BCHP_MEMC_DDR_0_SEQ_WRDATA_ERR_INFO_reserved0_SHIFT 21
-
-/* MEMC_DDR_0 :: SEQ_WRDATA_ERR_INFO :: INTF_ID [20:16] */
-#define BCHP_MEMC_DDR_0_SEQ_WRDATA_ERR_INFO_INTF_ID_MASK 0x001f0000
-#define BCHP_MEMC_DDR_0_SEQ_WRDATA_ERR_INFO_INTF_ID_SHIFT 16
-#define BCHP_MEMC_DDR_0_SEQ_WRDATA_ERR_INFO_INTF_ID_DEFAULT 0x00000000
-
-/* MEMC_DDR_0 :: SEQ_WRDATA_ERR_INFO :: reserved1 [15:08] */
-#define BCHP_MEMC_DDR_0_SEQ_WRDATA_ERR_INFO_reserved1_MASK 0x0000ff00
-#define BCHP_MEMC_DDR_0_SEQ_WRDATA_ERR_INFO_reserved1_SHIFT 8
-
-/* MEMC_DDR_0 :: SEQ_WRDATA_ERR_INFO :: INTF_TRANSACTION_ID [07:00] */
-#define BCHP_MEMC_DDR_0_SEQ_WRDATA_ERR_INFO_INTF_TRANSACTION_ID_MASK 0x000000ff
-#define BCHP_MEMC_DDR_0_SEQ_WRDATA_ERR_INFO_INTF_TRANSACTION_ID_SHIFT 0
-#define BCHP_MEMC_DDR_0_SEQ_WRDATA_ERR_INFO_INTF_TRANSACTION_ID_DEFAULT 0x00000000
-
-/***************************************************************************
- *SEQ_WRDATA_TRANSID_MISMATCH_INFO - Sequencer transaction ID mismatch error info
- ***************************************************************************/
-/* MEMC_DDR_0 :: SEQ_WRDATA_TRANSID_MISMATCH_INFO :: reserved0 [31:28] */
-#define BCHP_MEMC_DDR_0_SEQ_WRDATA_TRANSID_MISMATCH_INFO_reserved0_MASK 0xf0000000
-#define BCHP_MEMC_DDR_0_SEQ_WRDATA_TRANSID_MISMATCH_INFO_reserved0_SHIFT 28
-
-/* MEMC_DDR_0 :: SEQ_WRDATA_TRANSID_MISMATCH_INFO :: INTF_TYPE [27:24] */
-#define BCHP_MEMC_DDR_0_SEQ_WRDATA_TRANSID_MISMATCH_INFO_INTF_TYPE_MASK 0x0f000000
-#define BCHP_MEMC_DDR_0_SEQ_WRDATA_TRANSID_MISMATCH_INFO_INTF_TYPE_SHIFT 24
-#define BCHP_MEMC_DDR_0_SEQ_WRDATA_TRANSID_MISMATCH_INFO_INTF_TYPE_DEFAULT 0x00000000
-
-/* MEMC_DDR_0 :: SEQ_WRDATA_TRANSID_MISMATCH_INFO :: reserved1 [23:21] */
-#define BCHP_MEMC_DDR_0_SEQ_WRDATA_TRANSID_MISMATCH_INFO_reserved1_MASK 0x00e00000
-#define BCHP_MEMC_DDR_0_SEQ_WRDATA_TRANSID_MISMATCH_INFO_reserved1_SHIFT 21
-
-/* MEMC_DDR_0 :: SEQ_WRDATA_TRANSID_MISMATCH_INFO :: INTF_ID [20:16] */
-#define BCHP_MEMC_DDR_0_SEQ_WRDATA_TRANSID_MISMATCH_INFO_INTF_ID_MASK 0x001f0000
-#define BCHP_MEMC_DDR_0_SEQ_WRDATA_TRANSID_MISMATCH_INFO_INTF_ID_SHIFT 16
-#define BCHP_MEMC_DDR_0_SEQ_WRDATA_TRANSID_MISMATCH_INFO_INTF_ID_DEFAULT 0x00000000
-
-/* MEMC_DDR_0 :: SEQ_WRDATA_TRANSID_MISMATCH_INFO :: CMD_TRANS_ID [15:08] */
-#define BCHP_MEMC_DDR_0_SEQ_WRDATA_TRANSID_MISMATCH_INFO_CMD_TRANS_ID_MASK 0x0000ff00
-#define BCHP_MEMC_DDR_0_SEQ_WRDATA_TRANSID_MISMATCH_INFO_CMD_TRANS_ID_SHIFT 8
-#define BCHP_MEMC_DDR_0_SEQ_WRDATA_TRANSID_MISMATCH_INFO_CMD_TRANS_ID_DEFAULT 0x00000000
-
-/* MEMC_DDR_0 :: SEQ_WRDATA_TRANSID_MISMATCH_INFO :: WRDATA_TRANS_ID [07:00] */
-#define BCHP_MEMC_DDR_0_SEQ_WRDATA_TRANSID_MISMATCH_INFO_WRDATA_TRANS_ID_MASK 0x000000ff
-#define BCHP_MEMC_DDR_0_SEQ_WRDATA_TRANSID_MISMATCH_INFO_WRDATA_TRANS_ID_SHIFT 0
-#define BCHP_MEMC_DDR_0_SEQ_WRDATA_TRANSID_MISMATCH_INFO_WRDATA_TRANS_ID_DEFAULT 0x00000000
-
-/***************************************************************************
- *SEQ_CLEAR_VIOLATIONS - Sequencer Violation Info register clear.
- ***************************************************************************/
-/* MEMC_DDR_0 :: SEQ_CLEAR_VIOLATIONS :: reserved0 [31:01] */
-#define BCHP_MEMC_DDR_0_SEQ_CLEAR_VIOLATIONS_reserved0_MASK 0xfffffffe
-#define BCHP_MEMC_DDR_0_SEQ_CLEAR_VIOLATIONS_reserved0_SHIFT 1
-
-/* MEMC_DDR_0 :: SEQ_CLEAR_VIOLATIONS :: SEQ_CLEAR_VIOL [00:00] */
-#define BCHP_MEMC_DDR_0_SEQ_CLEAR_VIOLATIONS_SEQ_CLEAR_VIOL_MASK 0x00000001
-#define BCHP_MEMC_DDR_0_SEQ_CLEAR_VIOLATIONS_SEQ_CLEAR_VIOL_SHIFT 0
-#define BCHP_MEMC_DDR_0_SEQ_CLEAR_VIOLATIONS_SEQ_CLEAR_VIOL_DEFAULT 0x00000000
-
-/***************************************************************************
- *CMD_LOOKAHEAD - Command Lookahead
- ***************************************************************************/
-/* MEMC_DDR_0 :: CMD_LOOKAHEAD :: KEEP_OPEN_DISABLE [31:31] */
-#define BCHP_MEMC_DDR_0_CMD_LOOKAHEAD_KEEP_OPEN_DISABLE_MASK 0x80000000
-#define BCHP_MEMC_DDR_0_CMD_LOOKAHEAD_KEEP_OPEN_DISABLE_SHIFT 31
-#define BCHP_MEMC_DDR_0_CMD_LOOKAHEAD_KEEP_OPEN_DISABLE_DEFAULT 0x00000000
-
-/* MEMC_DDR_0 :: CMD_LOOKAHEAD :: KEEP_OPEN_RW_DISABLE [30:30] */
-#define BCHP_MEMC_DDR_0_CMD_LOOKAHEAD_KEEP_OPEN_RW_DISABLE_MASK 0x40000000
-#define BCHP_MEMC_DDR_0_CMD_LOOKAHEAD_KEEP_OPEN_RW_DISABLE_SHIFT 30
-#define BCHP_MEMC_DDR_0_CMD_LOOKAHEAD_KEEP_OPEN_RW_DISABLE_DEFAULT 0x00000000
-
-/* MEMC_DDR_0 :: CMD_LOOKAHEAD :: reserved_for_padding0 [29:08] */
-#define BCHP_MEMC_DDR_0_CMD_LOOKAHEAD_reserved_for_padding0_MASK 0x3fffff00
-#define BCHP_MEMC_DDR_0_CMD_LOOKAHEAD_reserved_for_padding0_SHIFT 8
-
-/* MEMC_DDR_0 :: CMD_LOOKAHEAD :: CAS_LOOKAHEAD [07:00] */
-#define BCHP_MEMC_DDR_0_CMD_LOOKAHEAD_CAS_LOOKAHEAD_MASK 0x000000ff
-#define BCHP_MEMC_DDR_0_CMD_LOOKAHEAD_CAS_LOOKAHEAD_SHIFT 0
-#define BCHP_MEMC_DDR_0_CMD_LOOKAHEAD_CAS_LOOKAHEAD_DEFAULT 0x00000002
-
-/***************************************************************************
- *DFI_PHASE_ENABLE - Sequencer DFI Phase Enable
- ***************************************************************************/
-/* MEMC_DDR_0 :: DFI_PHASE_ENABLE :: reserved0 [31:04] */
-#define BCHP_MEMC_DDR_0_DFI_PHASE_ENABLE_reserved0_MASK 0xfffffff0
-#define BCHP_MEMC_DDR_0_DFI_PHASE_ENABLE_reserved0_SHIFT 4
-
-/* MEMC_DDR_0 :: DFI_PHASE_ENABLE :: DFI_PHASE_ENABLE [03:00] */
-#define BCHP_MEMC_DDR_0_DFI_PHASE_ENABLE_DFI_PHASE_ENABLE_MASK 0x0000000f
-#define BCHP_MEMC_DDR_0_DFI_PHASE_ENABLE_DFI_PHASE_ENABLE_SHIFT 0
-#define BCHP_MEMC_DDR_0_DFI_PHASE_ENABLE_DFI_PHASE_ENABLE_DEFAULT 0x0000000f
-
-/***************************************************************************
- *STAT_CONTROL - Statistics Control register
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CONTROL :: reserved0 [31:11] */
-#define BCHP_MEMC_DDR_0_STAT_CONTROL_reserved0_MASK 0xfffff800
-#define BCHP_MEMC_DDR_0_STAT_CONTROL_reserved0_SHIFT 11
-
-/* MEMC_DDR_0 :: STAT_CONTROL :: PER_CLIENT_MODE [10:10] */
-#define BCHP_MEMC_DDR_0_STAT_CONTROL_PER_CLIENT_MODE_MASK 0x00000400
-#define BCHP_MEMC_DDR_0_STAT_CONTROL_PER_CLIENT_MODE_SHIFT 10
-#define BCHP_MEMC_DDR_0_STAT_CONTROL_PER_CLIENT_MODE_DEFAULT 0x00000000
-
-/* MEMC_DDR_0 :: STAT_CONTROL :: COUNTER_MODE [09:09] */
-#define BCHP_MEMC_DDR_0_STAT_CONTROL_COUNTER_MODE_MASK 0x00000200
-#define BCHP_MEMC_DDR_0_STAT_CONTROL_COUNTER_MODE_SHIFT 9
-#define BCHP_MEMC_DDR_0_STAT_CONTROL_COUNTER_MODE_DEFAULT 0x00000000
-#define BCHP_MEMC_DDR_0_STAT_CONTROL_COUNTER_MODE_MAX_MIN_FUNCT 1
-#define BCHP_MEMC_DDR_0_STAT_CONTROL_COUNTER_MODE_NORMAL 0
-
-/* MEMC_DDR_0 :: STAT_CONTROL :: STAT_ENABLE [08:08] */
-#define BCHP_MEMC_DDR_0_STAT_CONTROL_STAT_ENABLE_MASK 0x00000100
-#define BCHP_MEMC_DDR_0_STAT_CONTROL_STAT_ENABLE_SHIFT 8
-#define BCHP_MEMC_DDR_0_STAT_CONTROL_STAT_ENABLE_DEFAULT 0x00000000
-#define BCHP_MEMC_DDR_0_STAT_CONTROL_STAT_ENABLE_ENABLE 1
-#define BCHP_MEMC_DDR_0_STAT_CONTROL_STAT_ENABLE_DISABLE 0
-
-/* MEMC_DDR_0 :: STAT_CONTROL :: CLIENT_ID [07:00] */
-#define BCHP_MEMC_DDR_0_STAT_CONTROL_CLIENT_ID_MASK 0x000000ff
-#define BCHP_MEMC_DDR_0_STAT_CONTROL_CLIENT_ID_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CONTROL_CLIENT_ID_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_TIMER - Statistics Timer
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_TIMER :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_TIMER_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_TIMER_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_TIMER_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_IDLE_NOP - DRAM Idle_NOP Cycle Count Register.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_IDLE_NOP :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_IDLE_NOP_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_IDLE_NOP_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_IDLE_NOP_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_MAX_IDLE_NOP - Maximum DRAM idle_NOP cycle count register.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_MAX_IDLE_NOP :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_MAX_IDLE_NOP_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_MAX_IDLE_NOP_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_MAX_IDLE_NOP_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_MIN_IDLE_NOP - Minimum DRAM idle_NOP cycle count register.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_MIN_IDLE_NOP :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_MIN_IDLE_NOP_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_MIN_IDLE_NOP_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_MIN_IDLE_NOP_COUNT_DEFAULT 0xffffffff
-
-/***************************************************************************
- *STAT_CAS_ALL - CAS Count Register.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_ALL :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_ALL_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_ALL_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_ALL_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_MAX_CAS_ALL - Maximum DRAM CAS cycle count register.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_MAX_CAS_ALL :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_MAX_CAS_ALL_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_MAX_CAS_ALL_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_MAX_CAS_ALL_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_MIN_CAS_ALL - Minimum DRAM CAS cycle count register.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_MIN_CAS_ALL :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_MIN_CAS_ALL_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_MIN_CAS_ALL_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_MIN_CAS_ALL_COUNT_DEFAULT 0xffffffff
-
-/***************************************************************************
- *STAT_PENALTY_ALL - DRAM Penalty Cycle Count register.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_PENALTY_ALL :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_PENALTY_ALL_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_PENALTY_ALL_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_PENALTY_ALL_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_PENALTY_GDDRWM - GDDR Write Mask Penalty Cycle Count register.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_PENALTY_GDDRWM :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_PENALTY_GDDRWM_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_PENALTY_GDDRWM_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_PENALTY_GDDRWM_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_PAGE_MERGE_ALL - Page Merge Event Count register.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_PAGE_MERGE_ALL :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_PAGE_MERGE_ALL_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_PAGE_MERGE_ALL_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_PAGE_MERGE_ALL_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_MAX_TRANS_CYCLES_ALL - Maximum number of transactions cycles (CAS+Penalty_ALL).
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_MAX_TRANS_CYCLES_ALL :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_MAX_TRANS_CYCLES_ALL_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_MAX_TRANS_CYCLES_ALL_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_MAX_TRANS_CYCLES_ALL_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_MIN_TRANS_CYCLES_ALL - Minimum number of transactions cycles (CAS+Penalty_ALL).
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_MIN_TRANS_CYCLES_ALL :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_MIN_TRANS_CYCLES_ALL_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_MIN_TRANS_CYCLES_ALL_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_MIN_TRANS_CYCLES_ALL_COUNT_DEFAULT 0xffffffff
-
-/***************************************************************************
- *STAT_TRANS_READ_ALL - Number of overall system memory read transactions.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_TRANS_READ_ALL :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_TRANS_READ_ALL_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_TRANS_READ_ALL_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_TRANS_READ_ALL_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_TRANS_WRITE_ALL - Number of overall system memory write transactions.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_TRANS_WRITE_ALL :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_TRANS_WRITE_ALL_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_TRANS_WRITE_ALL_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_TRANS_WRITE_ALL_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_MAX_TRANS_ALL - Maximum Number of Overall System memory transactions.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_MAX_TRANS_ALL :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_MAX_TRANS_ALL_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_MAX_TRANS_ALL_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_MAX_TRANS_ALL_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_MIN_TRANS_ALL - Minimum Number of Overall System memory transactions.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_MIN_TRANS_ALL :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_MIN_TRANS_ALL_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_MIN_TRANS_ALL_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_MIN_TRANS_ALL_COUNT_DEFAULT 0xffffffff
-
-/***************************************************************************
- *STAT_CLIENT_SERVICE_CAS - Service CAS Cycle Count register.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CLIENT_SERVICE_CAS :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CLIENT_SERVICE_CAS_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CLIENT_SERVICE_CAS_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CLIENT_SERVICE_CAS_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_MAX_CLIENT_SERVICE_CAS - Maximum service CAS cycle count register.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_MAX_CLIENT_SERVICE_CAS :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_MAX_CLIENT_SERVICE_CAS_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_MAX_CLIENT_SERVICE_CAS_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_MAX_CLIENT_SERVICE_CAS_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_MIN_CLIENT_SERVICE_CAS - Minimum service CAS cycle count register.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_MIN_CLIENT_SERVICE_CAS :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_MIN_CLIENT_SERVICE_CAS_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_MIN_CLIENT_SERVICE_CAS_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_MIN_CLIENT_SERVICE_CAS_COUNT_DEFAULT 0xffffffff
-
-/***************************************************************************
- *STAT_CLIENT_SERVICE_INTR_PENALTY - Service Intra DRAM Penalty Cycle Count register.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CLIENT_SERVICE_INTR_PENALTY :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CLIENT_SERVICE_INTR_PENALTY_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CLIENT_SERVICE_INTR_PENALTY_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CLIENT_SERVICE_INTR_PENALTY_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CLIENT_SERVICE_POST_PENALTY - Service Post DRAM Penalty Cycle Count register.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CLIENT_SERVICE_POST_PENALTY :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CLIENT_SERVICE_POST_PENALTY_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CLIENT_SERVICE_POST_PENALTY_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CLIENT_SERVICE_POST_PENALTY_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CLIENT_SERVICE_GDDRWM_PENALTY - Service GDDR Write Mask Penalty Cycle Count register.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CLIENT_SERVICE_GDDRWM_PENALTY :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CLIENT_SERVICE_GDDRWM_PENALTY_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CLIENT_SERVICE_GDDRWM_PENALTY_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CLIENT_SERVICE_GDDRWM_PENALTY_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CLIENT_SERVICE_PAGE_MERGES - Service Page Merge Event Count register.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CLIENT_SERVICE_PAGE_MERGES :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CLIENT_SERVICE_PAGE_MERGES_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CLIENT_SERVICE_PAGE_MERGES_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CLIENT_SERVICE_PAGE_MERGES_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_MAX_CLIENT_SERVICE_CYCLES - Maximum service cycle count register.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_MAX_CLIENT_SERVICE_CYCLES :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_MAX_CLIENT_SERVICE_CYCLES_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_MAX_CLIENT_SERVICE_CYCLES_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_MAX_CLIENT_SERVICE_CYCLES_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_MIN_CLIENT_SERVICE_CYCLES - Minimum service cycle count register.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_MIN_CLIENT_SERVICE_CYCLES :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_MIN_CLIENT_SERVICE_CYCLES_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_MIN_CLIENT_SERVICE_CYCLES_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_MIN_CLIENT_SERVICE_CYCLES_COUNT_DEFAULT 0xffffffff
-
-/***************************************************************************
- *STAT_CLIENT_SERVICE_TRANS_READ - Service Read Transaction Count register.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CLIENT_SERVICE_TRANS_READ :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CLIENT_SERVICE_TRANS_READ_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CLIENT_SERVICE_TRANS_READ_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CLIENT_SERVICE_TRANS_READ_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CLIENT_SERVICE_TRANS_WRITE - Service Write Transaction Count register.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CLIENT_SERVICE_TRANS_WRITE :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CLIENT_SERVICE_TRANS_WRITE_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CLIENT_SERVICE_TRANS_WRITE_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CLIENT_SERVICE_TRANS_WRITE_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_MAX_CLIENT_SERVICE_TRANS - Maximum service Transaction count register.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_MAX_CLIENT_SERVICE_TRANS :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_MAX_CLIENT_SERVICE_TRANS_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_MAX_CLIENT_SERVICE_TRANS_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_MAX_CLIENT_SERVICE_TRANS_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_MIN_CLIENT_SERVICE_TRANS - Minimum service cycle Transaction register.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_MIN_CLIENT_SERVICE_TRANS :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_MIN_CLIENT_SERVICE_TRANS_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_MIN_CLIENT_SERVICE_TRANS_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_MIN_CLIENT_SERVICE_TRANS_COUNT_DEFAULT 0xffffffff
-
-/***************************************************************************
- *STAT_CLIENT_SERVICE_LATENCY - Service Latency Count register.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CLIENT_SERVICE_LATENCY :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CLIENT_SERVICE_LATENCY_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CLIENT_SERVICE_LATENCY_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CLIENT_SERVICE_LATENCY_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_MAX_CLIENT_SERVICE_LATENCY - Maximum Service Latency count register.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_MAX_CLIENT_SERVICE_LATENCY :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_MAX_CLIENT_SERVICE_LATENCY_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_MAX_CLIENT_SERVICE_LATENCY_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_MAX_CLIENT_SERVICE_LATENCY_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_MIN_CLIENT_SERVICE_LATENCY - Minimum Service Latency count register.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_MIN_CLIENT_SERVICE_LATENCY :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_MIN_CLIENT_SERVICE_LATENCY_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_MIN_CLIENT_SERVICE_LATENCY_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_MIN_CLIENT_SERVICE_LATENCY_COUNT_DEFAULT 0xffffffff
-
-/***************************************************************************
- *STAT_CLIENT_ABS_MAX_SERVICE_LATENCY - Absolute Minimum Service Latency count register.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CLIENT_ABS_MAX_SERVICE_LATENCY :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CLIENT_ABS_MAX_SERVICE_LATENCY_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CLIENT_ABS_MAX_SERVICE_LATENCY_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CLIENT_ABS_MAX_SERVICE_LATENCY_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CLIENT_ABS_MIN_SERVICE_LATENCY - Absolute Maximum Service Latency count register.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CLIENT_ABS_MIN_SERVICE_LATENCY :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CLIENT_ABS_MIN_SERVICE_LATENCY_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CLIENT_ABS_MIN_SERVICE_LATENCY_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CLIENT_ABS_MIN_SERVICE_LATENCY_COUNT_DEFAULT 0xffffffff
-
-/***************************************************************************
- *STAT_REFRESH - Total number of refreshes issued.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_REFRESH :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_REFRESH_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_REFRESH_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_REFRESH_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_MIN_DQ_IDLE_WRITE - Min DQ Idle Write event counter
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_MIN_DQ_IDLE_WRITE :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_MIN_DQ_IDLE_WRITE_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_MIN_DQ_IDLE_WRITE_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_MIN_DQ_IDLE_WRITE_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_MIN_DQ_IDLE_READ - Min DQ Idle Read event counter
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_MIN_DQ_IDLE_READ :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_MIN_DQ_IDLE_READ_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_MIN_DQ_IDLE_READ_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_MIN_DQ_IDLE_READ_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_0 - CAS or consumption cycle count register for client 0.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_0 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_0_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_0_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_0_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_1 - CAS or consumption cycle count register for client 1.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_1 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_1_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_1_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_1_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_2 - CAS or consumption cycle count register for client 2.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_2 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_2_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_2_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_2_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_3 - CAS or consumption cycle count register for client 3.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_3 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_3_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_3_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_3_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_4 - CAS or consumption cycle count register for client 4.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_4 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_4_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_4_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_4_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_5 - CAS or consumption cycle count register for client 5.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_5 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_5_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_5_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_5_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_6 - CAS or consumption cycle count register for client 6.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_6 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_6_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_6_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_6_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_7 - CAS or consumption cycle count register for client 7.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_7 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_7_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_7_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_7_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_8 - CAS or consumption cycle count register for client 8.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_8 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_8_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_8_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_8_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_9 - CAS or consumption cycle count register for client 9.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_9 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_9_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_9_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_9_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_10 - CAS or consumption cycle count register for client 10.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_10 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_10_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_10_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_10_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_11 - CAS or consumption cycle count register for client 11.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_11 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_11_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_11_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_11_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_12 - CAS or consumption cycle count register for client 12.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_12 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_12_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_12_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_12_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_13 - CAS or consumption cycle count register for client 13.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_13 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_13_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_13_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_13_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_14 - CAS or consumption cycle count register for client 14.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_14 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_14_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_14_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_14_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_15 - CAS or consumption cycle count register for client 15.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_15 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_15_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_15_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_15_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_16 - CAS or consumption cycle count register for client 16.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_16 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_16_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_16_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_16_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_17 - CAS or consumption cycle count register for client 17.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_17 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_17_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_17_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_17_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_18 - CAS or consumption cycle count register for client 18.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_18 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_18_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_18_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_18_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_19 - CAS or consumption cycle count register for client 19.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_19 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_19_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_19_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_19_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_20 - CAS or consumption cycle count register for client 20.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_20 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_20_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_20_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_20_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_21 - CAS or consumption cycle count register for client 21.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_21 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_21_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_21_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_21_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_22 - CAS or consumption cycle count register for client 22.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_22 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_22_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_22_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_22_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_23 - CAS or consumption cycle count register for client 23.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_23 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_23_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_23_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_23_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_24 - CAS or consumption cycle count register for client 24.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_24 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_24_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_24_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_24_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_25 - CAS or consumption cycle count register for client 25.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_25 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_25_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_25_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_25_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_26 - CAS or consumption cycle count register for client 26.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_26 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_26_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_26_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_26_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_27 - CAS or consumption cycle count register for client 27.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_27 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_27_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_27_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_27_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_28 - CAS or consumption cycle count register for client 28.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_28 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_28_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_28_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_28_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_29 - CAS or consumption cycle count register for client 29.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_29 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_29_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_29_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_29_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_30 - CAS or consumption cycle count register for client 30.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_30 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_30_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_30_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_30_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_31 - CAS or consumption cycle count register for client 31.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_31 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_31_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_31_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_31_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_32 - CAS or consumption cycle count register for client 32.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_32 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_32_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_32_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_32_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_33 - CAS or consumption cycle count register for client 33.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_33 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_33_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_33_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_33_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_34 - CAS or consumption cycle count register for client 34.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_34 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_34_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_34_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_34_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_35 - CAS or consumption cycle count register for client 35.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_35 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_35_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_35_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_35_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_36 - CAS or consumption cycle count register for client 36.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_36 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_36_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_36_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_36_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_37 - CAS or consumption cycle count register for client 37.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_37 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_37_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_37_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_37_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_38 - CAS or consumption cycle count register for client 38.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_38 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_38_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_38_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_38_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_39 - CAS or consumption cycle count register for client 39.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_39 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_39_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_39_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_39_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_40 - CAS or consumption cycle count register for client 40.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_40 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_40_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_40_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_40_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_41 - CAS or consumption cycle count register for client 41.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_41 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_41_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_41_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_41_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_42 - CAS or consumption cycle count register for client 42.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_42 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_42_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_42_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_42_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_43 - CAS or consumption cycle count register for client 43.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_43 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_43_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_43_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_43_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_44 - CAS or consumption cycle count register for client 44.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_44 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_44_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_44_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_44_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_45 - CAS or consumption cycle count register for client 45.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_45 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_45_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_45_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_45_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_46 - CAS or consumption cycle count register for client 46.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_46 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_46_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_46_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_46_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_47 - CAS or consumption cycle count register for client 47.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_47 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_47_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_47_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_47_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_48 - CAS or consumption cycle count register for client 48.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_48 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_48_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_48_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_48_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_49 - CAS or consumption cycle count register for client 49.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_49 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_49_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_49_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_49_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_50 - CAS or consumption cycle count register for client 50.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_50 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_50_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_50_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_50_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_51 - CAS or consumption cycle count register for client 51.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_51 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_51_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_51_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_51_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_52 - CAS or consumption cycle count register for client 52.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_52 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_52_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_52_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_52_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_53 - CAS or consumption cycle count register for client 53.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_53 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_53_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_53_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_53_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_54 - CAS or consumption cycle count register for client 54.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_54 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_54_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_54_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_54_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_55 - CAS or consumption cycle count register for client 55.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_55 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_55_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_55_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_55_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_56 - CAS or consumption cycle count register for client 56.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_56 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_56_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_56_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_56_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_57 - CAS or consumption cycle count register for client 57.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_57 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_57_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_57_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_57_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_58 - CAS or consumption cycle count register for client 58.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_58 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_58_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_58_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_58_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_59 - CAS or consumption cycle count register for client 59.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_59 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_59_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_59_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_59_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_60 - CAS or consumption cycle count register for client 60.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_60 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_60_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_60_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_60_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_61 - CAS or consumption cycle count register for client 61.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_61 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_61_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_61_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_61_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_62 - CAS or consumption cycle count register for client 62.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_62 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_62_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_62_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_62_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_63 - CAS or consumption cycle count register for client 63.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_63 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_63_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_63_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_63_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_64 - CAS or consumption cycle count register for client 64.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_64 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_64_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_64_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_64_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_65 - CAS or consumption cycle count register for client 65.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_65 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_65_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_65_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_65_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_66 - CAS or consumption cycle count register for client 66.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_66 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_66_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_66_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_66_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_67 - CAS or consumption cycle count register for client 67.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_67 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_67_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_67_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_67_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_68 - CAS or consumption cycle count register for client 68.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_68 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_68_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_68_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_68_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_69 - CAS or consumption cycle count register for client 69.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_69 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_69_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_69_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_69_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_70 - CAS or consumption cycle count register for client 70.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_70 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_70_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_70_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_70_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_71 - CAS or consumption cycle count register for client 71.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_71 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_71_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_71_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_71_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_72 - CAS or consumption cycle count register for client 72.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_72 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_72_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_72_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_72_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_73 - CAS or consumption cycle count register for client 73.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_73 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_73_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_73_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_73_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_74 - CAS or consumption cycle count register for client 74.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_74 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_74_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_74_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_74_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_75 - CAS or consumption cycle count register for client 75.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_75 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_75_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_75_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_75_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_76 - CAS or consumption cycle count register for client 76.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_76 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_76_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_76_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_76_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_77 - CAS or consumption cycle count register for client 77.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_77 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_77_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_77_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_77_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_78 - CAS or consumption cycle count register for client 78.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_78 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_78_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_78_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_78_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_79 - CAS or consumption cycle count register for client 79.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_79 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_79_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_79_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_79_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_80 - CAS or consumption cycle count register for client 80.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_80 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_80_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_80_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_80_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_81 - CAS or consumption cycle count register for client 81.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_81 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_81_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_81_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_81_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_82 - CAS or consumption cycle count register for client 82.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_82 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_82_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_82_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_82_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_83 - CAS or consumption cycle count register for client 83.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_83 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_83_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_83_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_83_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_84 - CAS or consumption cycle count register for client 84.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_84 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_84_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_84_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_84_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_85 - CAS or consumption cycle count register for client 85.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_85 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_85_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_85_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_85_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_86 - CAS or consumption cycle count register for client 86.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_86 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_86_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_86_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_86_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_87 - CAS or consumption cycle count register for client 87.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_87 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_87_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_87_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_87_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_88 - CAS or consumption cycle count register for client 88.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_88 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_88_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_88_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_88_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_89 - CAS or consumption cycle count register for client 89.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_89 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_89_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_89_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_89_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_90 - CAS or consumption cycle count register for client 90.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_90 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_90_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_90_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_90_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_91 - CAS or consumption cycle count register for client 91.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_91 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_91_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_91_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_91_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_92 - CAS or consumption cycle count register for client 92.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_92 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_92_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_92_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_92_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_93 - CAS or consumption cycle count register for client 93.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_93 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_93_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_93_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_93_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_94 - CAS or consumption cycle count register for client 94.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_94 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_94_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_94_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_94_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_95 - CAS or consumption cycle count register for client 95.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_95 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_95_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_95_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_95_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_96 - CAS or consumption cycle count register for client 96.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_96 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_96_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_96_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_96_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_97 - CAS or consumption cycle count register for client 97.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_97 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_97_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_97_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_97_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_98 - CAS or consumption cycle count register for client 98.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_98 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_98_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_98_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_98_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_99 - CAS or consumption cycle count register for client 99.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_99 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_99_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_99_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_99_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_100 - CAS or consumption cycle count register for client 100.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_100 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_100_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_100_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_100_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_101 - CAS or consumption cycle count register for client 101.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_101 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_101_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_101_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_101_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_102 - CAS or consumption cycle count register for client 102.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_102 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_102_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_102_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_102_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_103 - CAS or consumption cycle count register for client 103.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_103 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_103_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_103_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_103_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_104 - CAS or consumption cycle count register for client 104.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_104 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_104_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_104_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_104_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_105 - CAS or consumption cycle count register for client 105.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_105 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_105_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_105_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_105_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_106 - CAS or consumption cycle count register for client 106.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_106 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_106_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_106_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_106_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_107 - CAS or consumption cycle count register for client 107.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_107 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_107_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_107_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_107_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_108 - CAS or consumption cycle count register for client 108.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_108 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_108_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_108_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_108_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_109 - CAS or consumption cycle count register for client 109.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_109 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_109_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_109_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_109_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_110 - CAS or consumption cycle count register for client 110.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_110 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_110_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_110_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_110_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_111 - CAS or consumption cycle count register for client 111.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_111 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_111_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_111_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_111_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_112 - CAS or consumption cycle count register for client 112.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_112 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_112_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_112_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_112_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_113 - CAS or consumption cycle count register for client 113.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_113 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_113_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_113_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_113_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_114 - CAS or consumption cycle count register for client 114.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_114 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_114_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_114_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_114_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_115 - CAS or consumption cycle count register for client 115.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_115 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_115_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_115_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_115_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_116 - CAS or consumption cycle count register for client 116.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_116 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_116_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_116_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_116_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_117 - CAS or consumption cycle count register for client 117.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_117 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_117_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_117_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_117_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_118 - CAS or consumption cycle count register for client 118.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_118 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_118_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_118_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_118_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_119 - CAS or consumption cycle count register for client 119.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_119 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_119_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_119_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_119_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_120 - CAS or consumption cycle count register for client 120.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_120 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_120_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_120_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_120_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_121 - CAS or consumption cycle count register for client 121.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_121 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_121_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_121_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_121_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_122 - CAS or consumption cycle count register for client 122.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_122 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_122_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_122_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_122_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_123 - CAS or consumption cycle count register for client 123.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_123 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_123_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_123_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_123_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_124 - CAS or consumption cycle count register for client 124.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_124 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_124_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_124_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_124_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_125 - CAS or consumption cycle count register for client 125.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_125 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_125_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_125_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_125_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_126 - CAS or consumption cycle count register for client 126.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_126 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_126_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_126_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_126_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_127 - CAS or consumption cycle count register for client 127.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_127 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_127_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_127_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_127_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_128 - CAS or consumption cycle count register for client 128.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_128 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_128_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_128_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_128_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_129 - CAS or consumption cycle count register for client 129.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_129 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_129_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_129_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_129_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_130 - CAS or consumption cycle count register for client 130.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_130 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_130_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_130_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_130_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_131 - CAS or consumption cycle count register for client 131.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_131 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_131_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_131_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_131_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_132 - CAS or consumption cycle count register for client 132.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_132 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_132_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_132_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_132_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_133 - CAS or consumption cycle count register for client 133.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_133 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_133_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_133_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_133_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_134 - CAS or consumption cycle count register for client 134.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_134 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_134_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_134_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_134_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_135 - CAS or consumption cycle count register for client 135.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_135 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_135_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_135_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_135_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_136 - CAS or consumption cycle count register for client 136.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_136 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_136_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_136_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_136_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_137 - CAS or consumption cycle count register for client 137.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_137 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_137_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_137_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_137_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_138 - CAS or consumption cycle count register for client 138.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_138 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_138_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_138_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_138_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_139 - CAS or consumption cycle count register for client 139.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_139 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_139_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_139_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_139_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_140 - CAS or consumption cycle count register for client 140.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_140 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_140_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_140_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_140_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_141 - CAS or consumption cycle count register for client 141.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_141 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_141_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_141_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_141_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_142 - CAS or consumption cycle count register for client 142.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_142 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_142_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_142_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_142_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_143 - CAS or consumption cycle count register for client 143.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_143 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_143_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_143_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_143_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_144 - CAS or consumption cycle count register for client 144.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_144 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_144_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_144_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_144_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_145 - CAS or consumption cycle count register for client 145.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_145 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_145_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_145_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_145_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_146 - CAS or consumption cycle count register for client 146.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_146 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_146_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_146_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_146_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_147 - CAS or consumption cycle count register for client 147.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_147 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_147_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_147_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_147_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_148 - CAS or consumption cycle count register for client 148.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_148 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_148_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_148_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_148_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_149 - CAS or consumption cycle count register for client 149.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_149 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_149_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_149_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_149_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_150 - CAS or consumption cycle count register for client 150.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_150 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_150_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_150_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_150_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_151 - CAS or consumption cycle count register for client 151.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_151 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_151_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_151_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_151_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_152 - CAS or consumption cycle count register for client 152.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_152 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_152_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_152_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_152_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_153 - CAS or consumption cycle count register for client 153.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_153 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_153_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_153_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_153_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_154 - CAS or consumption cycle count register for client 154.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_154 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_154_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_154_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_154_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_155 - CAS or consumption cycle count register for client 155.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_155 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_155_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_155_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_155_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_156 - CAS or consumption cycle count register for client 156.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_156 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_156_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_156_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_156_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_157 - CAS or consumption cycle count register for client 157.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_157 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_157_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_157_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_157_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_158 - CAS or consumption cycle count register for client 158.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_158 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_158_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_158_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_158_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_159 - CAS or consumption cycle count register for client 159.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_159 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_159_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_159_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_159_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_160 - CAS or consumption cycle count register for client 160.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_160 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_160_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_160_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_160_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_161 - CAS or consumption cycle count register for client 161.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_161 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_161_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_161_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_161_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_162 - CAS or consumption cycle count register for client 162.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_162 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_162_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_162_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_162_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_163 - CAS or consumption cycle count register for client 163.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_163 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_163_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_163_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_163_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_164 - CAS or consumption cycle count register for client 164.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_164 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_164_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_164_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_164_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_165 - CAS or consumption cycle count register for client 165.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_165 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_165_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_165_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_165_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_166 - CAS or consumption cycle count register for client 166.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_166 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_166_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_166_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_166_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_167 - CAS or consumption cycle count register for client 167.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_167 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_167_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_167_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_167_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_168 - CAS or consumption cycle count register for client 168.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_168 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_168_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_168_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_168_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_169 - CAS or consumption cycle count register for client 169.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_169 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_169_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_169_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_169_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_170 - CAS or consumption cycle count register for client 170.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_170 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_170_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_170_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_170_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_171 - CAS or consumption cycle count register for client 171.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_171 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_171_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_171_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_171_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_172 - CAS or consumption cycle count register for client 172.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_172 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_172_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_172_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_172_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_173 - CAS or consumption cycle count register for client 173.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_173 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_173_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_173_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_173_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_174 - CAS or consumption cycle count register for client 174.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_174 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_174_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_174_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_174_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_175 - CAS or consumption cycle count register for client 175.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_175 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_175_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_175_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_175_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_176 - CAS or consumption cycle count register for client 176.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_176 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_176_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_176_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_176_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_177 - CAS or consumption cycle count register for client 177.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_177 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_177_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_177_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_177_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_178 - CAS or consumption cycle count register for client 178.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_178 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_178_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_178_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_178_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_179 - CAS or consumption cycle count register for client 179.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_179 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_179_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_179_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_179_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_180 - CAS or consumption cycle count register for client 180.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_180 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_180_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_180_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_180_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_181 - CAS or consumption cycle count register for client 181.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_181 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_181_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_181_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_181_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_182 - CAS or consumption cycle count register for client 182.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_182 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_182_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_182_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_182_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_183 - CAS or consumption cycle count register for client 183.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_183 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_183_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_183_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_183_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_184 - CAS or consumption cycle count register for client 184.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_184 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_184_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_184_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_184_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_185 - CAS or consumption cycle count register for client 185.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_185 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_185_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_185_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_185_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_186 - CAS or consumption cycle count register for client 186.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_186 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_186_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_186_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_186_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_187 - CAS or consumption cycle count register for client 187.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_187 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_187_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_187_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_187_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_188 - CAS or consumption cycle count register for client 188.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_188 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_188_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_188_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_188_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_189 - CAS or consumption cycle count register for client 189.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_189 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_189_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_189_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_189_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_190 - CAS or consumption cycle count register for client 190.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_190 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_190_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_190_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_190_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_191 - CAS or consumption cycle count register for client 191.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_191 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_191_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_191_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_191_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_192 - CAS or consumption cycle count register for client 192.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_192 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_192_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_192_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_192_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_193 - CAS or consumption cycle count register for client 193.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_193 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_193_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_193_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_193_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_194 - CAS or consumption cycle count register for client 194.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_194 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_194_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_194_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_194_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_195 - CAS or consumption cycle count register for client 195.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_195 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_195_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_195_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_195_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_196 - CAS or consumption cycle count register for client 196.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_196 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_196_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_196_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_196_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_197 - CAS or consumption cycle count register for client 197.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_197 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_197_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_197_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_197_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_198 - CAS or consumption cycle count register for client 198.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_198 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_198_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_198_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_198_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_199 - CAS or consumption cycle count register for client 199.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_199 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_199_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_199_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_199_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_200 - CAS or consumption cycle count register for client 200.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_200 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_200_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_200_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_200_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_201 - CAS or consumption cycle count register for client 201.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_201 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_201_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_201_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_201_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_202 - CAS or consumption cycle count register for client 202.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_202 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_202_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_202_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_202_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_203 - CAS or consumption cycle count register for client 203.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_203 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_203_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_203_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_203_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_204 - CAS or consumption cycle count register for client 204.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_204 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_204_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_204_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_204_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_205 - CAS or consumption cycle count register for client 205.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_205 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_205_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_205_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_205_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_206 - CAS or consumption cycle count register for client 206.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_206 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_206_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_206_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_206_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_207 - CAS or consumption cycle count register for client 207.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_207 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_207_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_207_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_207_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_208 - CAS or consumption cycle count register for client 208.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_208 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_208_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_208_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_208_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_209 - CAS or consumption cycle count register for client 209.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_209 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_209_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_209_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_209_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_210 - CAS or consumption cycle count register for client 210.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_210 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_210_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_210_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_210_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_211 - CAS or consumption cycle count register for client 211.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_211 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_211_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_211_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_211_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_212 - CAS or consumption cycle count register for client 212.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_212 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_212_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_212_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_212_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_213 - CAS or consumption cycle count register for client 213.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_213 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_213_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_213_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_213_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_214 - CAS or consumption cycle count register for client 214.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_214 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_214_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_214_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_214_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_215 - CAS or consumption cycle count register for client 215.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_215 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_215_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_215_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_215_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_216 - CAS or consumption cycle count register for client 216.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_216 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_216_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_216_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_216_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_217 - CAS or consumption cycle count register for client 217.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_217 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_217_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_217_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_217_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_218 - CAS or consumption cycle count register for client 218.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_218 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_218_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_218_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_218_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_219 - CAS or consumption cycle count register for client 219.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_219 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_219_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_219_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_219_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_220 - CAS or consumption cycle count register for client 220.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_220 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_220_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_220_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_220_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_221 - CAS or consumption cycle count register for client 221.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_221 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_221_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_221_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_221_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_222 - CAS or consumption cycle count register for client 222.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_222 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_222_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_222_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_222_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_223 - CAS or consumption cycle count register for client 223.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_223 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_223_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_223_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_223_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_224 - CAS or consumption cycle count register for client 224.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_224 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_224_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_224_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_224_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_225 - CAS or consumption cycle count register for client 225.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_225 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_225_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_225_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_225_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_226 - CAS or consumption cycle count register for client 226.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_226 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_226_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_226_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_226_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_227 - CAS or consumption cycle count register for client 227.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_227 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_227_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_227_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_227_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_228 - CAS or consumption cycle count register for client 228.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_228 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_228_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_228_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_228_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_229 - CAS or consumption cycle count register for client 229.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_229 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_229_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_229_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_229_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_230 - CAS or consumption cycle count register for client 230.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_230 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_230_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_230_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_230_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_231 - CAS or consumption cycle count register for client 231.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_231 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_231_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_231_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_231_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_232 - CAS or consumption cycle count register for client 232.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_232 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_232_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_232_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_232_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_233 - CAS or consumption cycle count register for client 233.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_233 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_233_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_233_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_233_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_234 - CAS or consumption cycle count register for client 234.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_234 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_234_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_234_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_234_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_235 - CAS or consumption cycle count register for client 235.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_235 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_235_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_235_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_235_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_236 - CAS or consumption cycle count register for client 236.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_236 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_236_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_236_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_236_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_237 - CAS or consumption cycle count register for client 237.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_237 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_237_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_237_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_237_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_238 - CAS or consumption cycle count register for client 238.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_238 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_238_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_238_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_238_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_239 - CAS or consumption cycle count register for client 239.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_239 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_239_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_239_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_239_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_240 - CAS or consumption cycle count register for client 240.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_240 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_240_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_240_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_240_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_241 - CAS or consumption cycle count register for client 241.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_241 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_241_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_241_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_241_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_242 - CAS or consumption cycle count register for client 242.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_242 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_242_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_242_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_242_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_243 - CAS or consumption cycle count register for client 243.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_243 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_243_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_243_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_243_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_244 - CAS or consumption cycle count register for client 244.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_244 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_244_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_244_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_244_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_245 - CAS or consumption cycle count register for client 245.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_245 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_245_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_245_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_245_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_246 - CAS or consumption cycle count register for client 246.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_246 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_246_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_246_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_246_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_247 - CAS or consumption cycle count register for client 247.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_247 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_247_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_247_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_247_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_248 - CAS or consumption cycle count register for client 248.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_248 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_248_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_248_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_248_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_249 - CAS or consumption cycle count register for client 249.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_249 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_249_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_249_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_249_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_250 - CAS or consumption cycle count register for client 250.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_250 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_250_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_250_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_250_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_251 - CAS or consumption cycle count register for client 251.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_251 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_251_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_251_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_251_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_252 - CAS or consumption cycle count register for client 252.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_252 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_252_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_252_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_252_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_253 - CAS or consumption cycle count register for client 253.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_253 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_253_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_253_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_253_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_254 - CAS or consumption cycle count register for client 254.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_254 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_254_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_254_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_254_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_255 - CAS or consumption cycle count register for client 255.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_255 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_255_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_255_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_255_COUNT_DEFAULT 0x00000000
-
-#endif /* #ifndef BCHP_MEMC_DDR_0_H__ */
-
-/* End of File */
diff --git a/include/linux/brcmstb/7366b0/bchp_moca_hostmisc.h b/include/linux/brcmstb/7366b0/bchp_moca_hostmisc.h
deleted file mode 100644
index 3e5a892..0000000
--- a/include/linux/brcmstb/7366b0/bchp_moca_hostmisc.h
+++ /dev/null
@@ -1,511 +0,0 @@
-/***************************************************************************
- * Copyright (c) 1999-2012, Broadcom Corporation
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
- *
- * Module Description:
- * DO NOT EDIT THIS FILE DIRECTLY
- *
- * This module was generated magically with RDB from a source description
- * file. You must edit the source file for changes to be made to this file.
- *
- *
- * Date: Generated on Wed Oct 17 03:11:32 2012
- * MD5 Checksum d41d8cd98f00b204e9800998ecf8427e
- *
- * Compiled with: RDB Utility combo_header.pl
- * RDB Parser 3.0
- * unknown unknown
- * Perl Interpreter 5.008008
- * Operating System linux
- *
- * Revision History:
- *
- * $brcm_Log: $
- *
- ***************************************************************************/
-
-#ifndef BCHP_MOCA_HOSTMISC_H__
-#define BCHP_MOCA_HOSTMISC_H__
-
-/***************************************************************************
- *MOCA_HOSTMISC - MOCA_HOSTMISC registers
- ***************************************************************************/
-#define BCHP_MOCA_HOSTMISC_MISC_CTRL 0x00fffd00 /* Moca Software Reset */
-#define BCHP_MOCA_HOSTMISC_SCRATCH 0x00fffd04 /* Moca Scratch Register */
-#define BCHP_MOCA_HOSTMISC_VERSION 0x00fffd08 /* MoCA version register */
-#define BCHP_MOCA_HOSTMISC_H2M_INT_TRIG 0x00fffd0c /* Host-to-MoCA Interrupt Trigger */
-#define BCHP_MOCA_HOSTMISC_WAKEUP 0x00fffd10 /* Host-to-MoCA Wakeup Interrupt */
-#define BCHP_MOCA_HOSTMISC_SUBSYS_CFG 0x00fffd14 /* Moca Subsystem configuration */
-#define BCHP_MOCA_HOSTMISC_H2M_MMP_OUTBOX_0 0x00fffd18 /* Host to MoCA MMP outbox registes , register set index 0. */
-#define BCHP_MOCA_HOSTMISC_H2M_MMP_OUTBOX_1 0x00fffd1c /* Host to MoCA MMP outbox registes , register set index 1. */
-#define BCHP_MOCA_HOSTMISC_H2M_MMP_OUTBOX_2 0x00fffd20 /* Host to MoCA MMP outbox registes , register set index 2. */
-#define BCHP_MOCA_HOSTMISC_H2M_MMP_OUTBOX_3 0x00fffd24 /* Host to MoCA MMP outbox registes , register set index 3. */
-#define BCHP_MOCA_HOSTMISC_H2M_MMP_OUTBOX_4 0x00fffd28 /* Host to MoCA MMP outbox registes , register set index 4. */
-#define BCHP_MOCA_HOSTMISC_H2M_MMP_OUTBOX_5 0x00fffd2c /* Host to MoCA MMP outbox registes , register set index 5. */
-#define BCHP_MOCA_HOSTMISC_H2M_MMP_OUTBOX_6 0x00fffd30 /* Host to MoCA MMP outbox registes , register set index 6. */
-#define BCHP_MOCA_HOSTMISC_H2M_MMP_OUTBOX_7 0x00fffd34 /* Host to MoCA MMP outbox registes , register set index 7. */
-#define BCHP_MOCA_HOSTMISC_H2M_MMP_OUTBOX_8 0x00fffd38 /* Host to MoCA MMP outbox registes , register set index 8. */
-#define BCHP_MOCA_HOSTMISC_H2M_MMP_OUTBOX_9 0x00fffd3c /* Host to MoCA MMP outbox registes , register set index 9. */
-#define BCHP_MOCA_HOSTMISC_H2M_MMP_OUTBOX_10 0x00fffd40 /* Host to MoCA MMP outbox registes , register set index 10. */
-#define BCHP_MOCA_HOSTMISC_H2M_MMP_OUTBOX_11 0x00fffd44 /* Host to MoCA MMP outbox registes , register set index 11. */
-#define BCHP_MOCA_HOSTMISC_H2M_MMP_OUTBOX_12 0x00fffd48 /* Host to MoCA MMP outbox registes , register set index 12. */
-#define BCHP_MOCA_HOSTMISC_H2M_MMP_OUTBOX_13 0x00fffd4c /* Host to MoCA MMP outbox registes , register set index 13. */
-#define BCHP_MOCA_HOSTMISC_H2M_MMP_OUTBOX_14 0x00fffd50 /* Host to MoCA MMP outbox registes , register set index 14. */
-#define BCHP_MOCA_HOSTMISC_H2M_MMP_OUTBOX_15 0x00fffd54 /* Host to MoCA MMP outbox registes , register set index 15. */
-#define BCHP_MOCA_HOSTMISC_M2H_MMP_INBOX_0 0x00fffd58 /* MoCA to Host MMP inbox registers , register set index 0. */
-#define BCHP_MOCA_HOSTMISC_M2H_MMP_INBOX_1 0x00fffd5c /* MoCA to Host MMP inbox registers , register set index 1. */
-#define BCHP_MOCA_HOSTMISC_M2H_MMP_INBOX_2 0x00fffd60 /* MoCA to Host MMP inbox registers , register set index 2. */
-#define BCHP_MOCA_HOSTMISC_M2H_MMP_INBOX_3 0x00fffd64 /* MoCA to Host MMP inbox registers , register set index 3. */
-#define BCHP_MOCA_HOSTMISC_M2H_MMP_INBOX_4 0x00fffd68 /* MoCA to Host MMP inbox registers , register set index 4. */
-#define BCHP_MOCA_HOSTMISC_M2H_MMP_INBOX_5 0x00fffd6c /* MoCA to Host MMP inbox registers , register set index 5. */
-#define BCHP_MOCA_HOSTMISC_M2H_MMP_INBOX_6 0x00fffd70 /* MoCA to Host MMP inbox registers , register set index 6. */
-#define BCHP_MOCA_HOSTMISC_M2H_MMP_INBOX_7 0x00fffd74 /* MoCA to Host MMP inbox registers , register set index 7. */
-#define BCHP_MOCA_HOSTMISC_M2H_MMP_INBOX_8 0x00fffd78 /* MoCA to Host MMP inbox registers , register set index 8. */
-#define BCHP_MOCA_HOSTMISC_M2H_MMP_INBOX_9 0x00fffd7c /* MoCA to Host MMP inbox registers , register set index 9. */
-#define BCHP_MOCA_HOSTMISC_M2H_MMP_INBOX_10 0x00fffd80 /* MoCA to Host MMP inbox registers , register set index 10. */
-#define BCHP_MOCA_HOSTMISC_M2H_MMP_INBOX_11 0x00fffd84 /* MoCA to Host MMP inbox registers , register set index 11. */
-#define BCHP_MOCA_HOSTMISC_M2H_MMP_INBOX_12 0x00fffd88 /* MoCA to Host MMP inbox registers , register set index 12. */
-#define BCHP_MOCA_HOSTMISC_M2H_MMP_INBOX_13 0x00fffd8c /* MoCA to Host MMP inbox registers , register set index 13. */
-#define BCHP_MOCA_HOSTMISC_M2H_MMP_INBOX_14 0x00fffd90 /* MoCA to Host MMP inbox registers , register set index 14. */
-#define BCHP_MOCA_HOSTMISC_M2H_MMP_INBOX_15 0x00fffd94 /* MoCA to Host MMP inbox registers , register set index 15. */
-#define BCHP_MOCA_HOSTMISC_DMPG_CHAINS_STATUS 0x00fffd98 /* "MoCA dynamic memory power gating chain power up (bit per chain),Active when moca_dmpg_gisb_en is high,0: Chain is on,1: Chain is off" */
-#define BCHP_MOCA_HOSTMISC_DMPG_CHAINS_PWR_UP 0x00fffd9c /* "MoCA dynamic memory power gating chain status (bit per chain),0: Power down chain,1: Power up chain" */
-
-/***************************************************************************
- *MISC_CTRL - Moca Software Reset
- ***************************************************************************/
-/* MOCA_HOSTMISC :: MISC_CTRL :: spare_ctrl [31:17] */
-#define BCHP_MOCA_HOSTMISC_MISC_CTRL_spare_ctrl_MASK 0xfffe0000
-#define BCHP_MOCA_HOSTMISC_MISC_CTRL_spare_ctrl_SHIFT 17
-#define BCHP_MOCA_HOSTMISC_MISC_CTRL_spare_ctrl_DEFAULT 0x00007fff
-
-/* MOCA_HOSTMISC :: MISC_CTRL :: moca_dmpg_sel [16:16] */
-#define BCHP_MOCA_HOSTMISC_MISC_CTRL_moca_dmpg_sel_MASK 0x00010000
-#define BCHP_MOCA_HOSTMISC_MISC_CTRL_moca_dmpg_sel_SHIFT 16
-#define BCHP_MOCA_HOSTMISC_MISC_CTRL_moca_dmpg_sel_DEFAULT 0x00000000
-
-/* MOCA_HOSTMISC :: MISC_CTRL :: moca_dmpg_en [15:15] */
-#define BCHP_MOCA_HOSTMISC_MISC_CTRL_moca_dmpg_en_MASK 0x00008000
-#define BCHP_MOCA_HOSTMISC_MISC_CTRL_moca_dmpg_en_SHIFT 15
-#define BCHP_MOCA_HOSTMISC_MISC_CTRL_moca_dmpg_en_DEFAULT 0x00000001
-
-/* MOCA_HOSTMISC :: MISC_CTRL :: spare_status [14:10] */
-#define BCHP_MOCA_HOSTMISC_MISC_CTRL_spare_status_MASK 0x00007c00
-#define BCHP_MOCA_HOSTMISC_MISC_CTRL_spare_status_SHIFT 10
-#define BCHP_MOCA_HOSTMISC_MISC_CTRL_spare_status_DEFAULT 0x0000001f
-
-/* MOCA_HOSTMISC :: MISC_CTRL :: moca_phy1_disable_clk [09:09] */
-#define BCHP_MOCA_HOSTMISC_MISC_CTRL_moca_phy1_disable_clk_MASK 0x00000200
-#define BCHP_MOCA_HOSTMISC_MISC_CTRL_moca_phy1_disable_clk_SHIFT 9
-#define BCHP_MOCA_HOSTMISC_MISC_CTRL_moca_phy1_disable_clk_DEFAULT 0x00000000
-
-/* MOCA_HOSTMISC :: MISC_CTRL :: moca_phy0_disable_clk [08:08] */
-#define BCHP_MOCA_HOSTMISC_MISC_CTRL_moca_phy0_disable_clk_MASK 0x00000100
-#define BCHP_MOCA_HOSTMISC_MISC_CTRL_moca_phy0_disable_clk_SHIFT 8
-#define BCHP_MOCA_HOSTMISC_MISC_CTRL_moca_phy0_disable_clk_DEFAULT 0x00000000
-
-/* MOCA_HOSTMISC :: MISC_CTRL :: moca_disable_clocks [07:07] */
-#define BCHP_MOCA_HOSTMISC_MISC_CTRL_moca_disable_clocks_MASK 0x00000080
-#define BCHP_MOCA_HOSTMISC_MISC_CTRL_moca_disable_clocks_SHIFT 7
-#define BCHP_MOCA_HOSTMISC_MISC_CTRL_moca_disable_clocks_DEFAULT 0x00000000
-
-/* MOCA_HOSTMISC :: MISC_CTRL :: spare_reset [06:06] */
-#define BCHP_MOCA_HOSTMISC_MISC_CTRL_spare_reset_MASK 0x00000040
-#define BCHP_MOCA_HOSTMISC_MISC_CTRL_spare_reset_SHIFT 6
-#define BCHP_MOCA_HOSTMISC_MISC_CTRL_spare_reset_DEFAULT 0x00000001
-
-/* MOCA_HOSTMISC :: MISC_CTRL :: moca_phy1_reset [05:05] */
-#define BCHP_MOCA_HOSTMISC_MISC_CTRL_moca_phy1_reset_MASK 0x00000020
-#define BCHP_MOCA_HOSTMISC_MISC_CTRL_moca_phy1_reset_SHIFT 5
-#define BCHP_MOCA_HOSTMISC_MISC_CTRL_moca_phy1_reset_DEFAULT 0x00000000
-
-/* MOCA_HOSTMISC :: MISC_CTRL :: moca_phy0_reset [04:04] */
-#define BCHP_MOCA_HOSTMISC_MISC_CTRL_moca_phy0_reset_MASK 0x00000010
-#define BCHP_MOCA_HOSTMISC_MISC_CTRL_moca_phy0_reset_SHIFT 4
-#define BCHP_MOCA_HOSTMISC_MISC_CTRL_moca_phy0_reset_DEFAULT 0x00000000
-
-/* MOCA_HOSTMISC :: MISC_CTRL :: moca_gmii_sw_init [03:03] */
-#define BCHP_MOCA_HOSTMISC_MISC_CTRL_moca_gmii_sw_init_MASK 0x00000008
-#define BCHP_MOCA_HOSTMISC_MISC_CTRL_moca_gmii_sw_init_SHIFT 3
-#define BCHP_MOCA_HOSTMISC_MISC_CTRL_moca_gmii_sw_init_DEFAULT 0x00000000
-
-/* MOCA_HOSTMISC :: MISC_CTRL :: moca_cpu_l_reset [02:02] */
-#define BCHP_MOCA_HOSTMISC_MISC_CTRL_moca_cpu_l_reset_MASK 0x00000004
-#define BCHP_MOCA_HOSTMISC_MISC_CTRL_moca_cpu_l_reset_SHIFT 2
-#define BCHP_MOCA_HOSTMISC_MISC_CTRL_moca_cpu_l_reset_DEFAULT 0x00000001
-
-/* MOCA_HOSTMISC :: MISC_CTRL :: moca_sys_reset [01:01] */
-#define BCHP_MOCA_HOSTMISC_MISC_CTRL_moca_sys_reset_MASK 0x00000002
-#define BCHP_MOCA_HOSTMISC_MISC_CTRL_moca_sys_reset_SHIFT 1
-#define BCHP_MOCA_HOSTMISC_MISC_CTRL_moca_sys_reset_DEFAULT 0x00000001
-
-/* MOCA_HOSTMISC :: MISC_CTRL :: moca_cpu_h_reset [00:00] */
-#define BCHP_MOCA_HOSTMISC_MISC_CTRL_moca_cpu_h_reset_MASK 0x00000001
-#define BCHP_MOCA_HOSTMISC_MISC_CTRL_moca_cpu_h_reset_SHIFT 0
-#define BCHP_MOCA_HOSTMISC_MISC_CTRL_moca_cpu_h_reset_DEFAULT 0x00000001
-
-/***************************************************************************
- *SCRATCH - Moca Scratch Register
- ***************************************************************************/
-/* MOCA_HOSTMISC :: SCRATCH :: value [31:00] */
-#define BCHP_MOCA_HOSTMISC_SCRATCH_value_MASK 0xffffffff
-#define BCHP_MOCA_HOSTMISC_SCRATCH_value_SHIFT 0
-#define BCHP_MOCA_HOSTMISC_SCRATCH_value_DEFAULT 0x00000000
-
-/***************************************************************************
- *VERSION - MoCA version register
- ***************************************************************************/
-/* MOCA_HOSTMISC :: VERSION :: moca_id [31:16] */
-#define BCHP_MOCA_HOSTMISC_VERSION_moca_id_MASK 0xffff0000
-#define BCHP_MOCA_HOSTMISC_VERSION_moca_id_SHIFT 16
-#define BCHP_MOCA_HOSTMISC_VERSION_moca_id_DEFAULT 0x00006622
-
-/* MOCA_HOSTMISC :: VERSION :: moca_spec_ver [15:12] */
-#define BCHP_MOCA_HOSTMISC_VERSION_moca_spec_ver_MASK 0x0000f000
-#define BCHP_MOCA_HOSTMISC_VERSION_moca_spec_ver_SHIFT 12
-#define BCHP_MOCA_HOSTMISC_VERSION_moca_spec_ver_DEFAULT 0x00000003
-
-/* MOCA_HOSTMISC :: VERSION :: core_version [11:08] */
-#define BCHP_MOCA_HOSTMISC_VERSION_core_version_MASK 0x00000f00
-#define BCHP_MOCA_HOSTMISC_VERSION_core_version_SHIFT 8
-#define BCHP_MOCA_HOSTMISC_VERSION_core_version_DEFAULT 0x00000000
-
-/* MOCA_HOSTMISC :: VERSION :: core_revision [07:04] */
-#define BCHP_MOCA_HOSTMISC_VERSION_core_revision_MASK 0x000000f0
-#define BCHP_MOCA_HOSTMISC_VERSION_core_revision_SHIFT 4
-#define BCHP_MOCA_HOSTMISC_VERSION_core_revision_DEFAULT 0x00000000
-
-/* MOCA_HOSTMISC :: VERSION :: core_mask [03:00] */
-#define BCHP_MOCA_HOSTMISC_VERSION_core_mask_MASK 0x0000000f
-#define BCHP_MOCA_HOSTMISC_VERSION_core_mask_SHIFT 0
-#define BCHP_MOCA_HOSTMISC_VERSION_core_mask_DEFAULT 0x00000000
-
-/***************************************************************************
- *H2M_INT_TRIG - Host-to-MoCA Interrupt Trigger
- ***************************************************************************/
-/* MOCA_HOSTMISC :: H2M_INT_TRIG :: reserved0 [31:08] */
-#define BCHP_MOCA_HOSTMISC_H2M_INT_TRIG_reserved0_MASK 0xffffff00
-#define BCHP_MOCA_HOSTMISC_H2M_INT_TRIG_reserved0_SHIFT 8
-
-/* MOCA_HOSTMISC :: H2M_INT_TRIG :: INT_TRIG [07:00] */
-#define BCHP_MOCA_HOSTMISC_H2M_INT_TRIG_INT_TRIG_MASK 0x000000ff
-#define BCHP_MOCA_HOSTMISC_H2M_INT_TRIG_INT_TRIG_SHIFT 0
-#define BCHP_MOCA_HOSTMISC_H2M_INT_TRIG_INT_TRIG_DEFAULT 0x00000000
-
-/***************************************************************************
- *WAKEUP - Host-to-MoCA Wakeup Interrupt
- ***************************************************************************/
-/* MOCA_HOSTMISC :: WAKEUP :: reserved0 [31:02] */
-#define BCHP_MOCA_HOSTMISC_WAKEUP_reserved0_MASK 0xfffffffc
-#define BCHP_MOCA_HOSTMISC_WAKEUP_reserved0_SHIFT 2
-
-/* MOCA_HOSTMISC :: WAKEUP :: cpu_l_wakeup_int [01:01] */
-#define BCHP_MOCA_HOSTMISC_WAKEUP_cpu_l_wakeup_int_MASK 0x00000002
-#define BCHP_MOCA_HOSTMISC_WAKEUP_cpu_l_wakeup_int_SHIFT 1
-#define BCHP_MOCA_HOSTMISC_WAKEUP_cpu_l_wakeup_int_DEFAULT 0x00000000
-
-/* MOCA_HOSTMISC :: WAKEUP :: cpu_h_wakeup_int [00:00] */
-#define BCHP_MOCA_HOSTMISC_WAKEUP_cpu_h_wakeup_int_MASK 0x00000001
-#define BCHP_MOCA_HOSTMISC_WAKEUP_cpu_h_wakeup_int_SHIFT 0
-#define BCHP_MOCA_HOSTMISC_WAKEUP_cpu_h_wakeup_int_DEFAULT 0x00000000
-
-/***************************************************************************
- *SUBSYS_CFG - Moca Subsystem configuration
- ***************************************************************************/
-/* MOCA_HOSTMISC :: SUBSYS_CFG :: spare_cfg [31:01] */
-#define BCHP_MOCA_HOSTMISC_SUBSYS_CFG_spare_cfg_MASK 0xfffffffe
-#define BCHP_MOCA_HOSTMISC_SUBSYS_CFG_spare_cfg_SHIFT 1
-#define BCHP_MOCA_HOSTMISC_SUBSYS_CFG_spare_cfg_DEFAULT 0x00000000
-
-/* MOCA_HOSTMISC :: SUBSYS_CFG :: moca_arb_rr_sel [00:00] */
-#define BCHP_MOCA_HOSTMISC_SUBSYS_CFG_moca_arb_rr_sel_MASK 0x00000001
-#define BCHP_MOCA_HOSTMISC_SUBSYS_CFG_moca_arb_rr_sel_SHIFT 0
-#define BCHP_MOCA_HOSTMISC_SUBSYS_CFG_moca_arb_rr_sel_DEFAULT 0x00000001
-
-/***************************************************************************
- *H2M_MMP_OUTBOX_0 - Host to MoCA MMP outbox registes , register set index 0.
- ***************************************************************************/
-/* MOCA_HOSTMISC :: H2M_MMP_OUTBOX_0 :: m2h_mmp_outbox [31:00] */
-#define BCHP_MOCA_HOSTMISC_H2M_MMP_OUTBOX_0_m2h_mmp_outbox_MASK 0xffffffff
-#define BCHP_MOCA_HOSTMISC_H2M_MMP_OUTBOX_0_m2h_mmp_outbox_SHIFT 0
-#define BCHP_MOCA_HOSTMISC_H2M_MMP_OUTBOX_0_m2h_mmp_outbox_DEFAULT 0x00000000
-
-/***************************************************************************
- *H2M_MMP_OUTBOX_1 - Host to MoCA MMP outbox registes , register set index 1.
- ***************************************************************************/
-/* MOCA_HOSTMISC :: H2M_MMP_OUTBOX_1 :: m2h_mmp_outbox [31:00] */
-#define BCHP_MOCA_HOSTMISC_H2M_MMP_OUTBOX_1_m2h_mmp_outbox_MASK 0xffffffff
-#define BCHP_MOCA_HOSTMISC_H2M_MMP_OUTBOX_1_m2h_mmp_outbox_SHIFT 0
-#define BCHP_MOCA_HOSTMISC_H2M_MMP_OUTBOX_1_m2h_mmp_outbox_DEFAULT 0x00000000
-
-/***************************************************************************
- *H2M_MMP_OUTBOX_2 - Host to MoCA MMP outbox registes , register set index 2.
- ***************************************************************************/
-/* MOCA_HOSTMISC :: H2M_MMP_OUTBOX_2 :: m2h_mmp_outbox [31:00] */
-#define BCHP_MOCA_HOSTMISC_H2M_MMP_OUTBOX_2_m2h_mmp_outbox_MASK 0xffffffff
-#define BCHP_MOCA_HOSTMISC_H2M_MMP_OUTBOX_2_m2h_mmp_outbox_SHIFT 0
-#define BCHP_MOCA_HOSTMISC_H2M_MMP_OUTBOX_2_m2h_mmp_outbox_DEFAULT 0x00000000
-
-/***************************************************************************
- *H2M_MMP_OUTBOX_3 - Host to MoCA MMP outbox registes , register set index 3.
- ***************************************************************************/
-/* MOCA_HOSTMISC :: H2M_MMP_OUTBOX_3 :: m2h_mmp_outbox [31:00] */
-#define BCHP_MOCA_HOSTMISC_H2M_MMP_OUTBOX_3_m2h_mmp_outbox_MASK 0xffffffff
-#define BCHP_MOCA_HOSTMISC_H2M_MMP_OUTBOX_3_m2h_mmp_outbox_SHIFT 0
-#define BCHP_MOCA_HOSTMISC_H2M_MMP_OUTBOX_3_m2h_mmp_outbox_DEFAULT 0x00000000
-
-/***************************************************************************
- *H2M_MMP_OUTBOX_4 - Host to MoCA MMP outbox registes , register set index 4.
- ***************************************************************************/
-/* MOCA_HOSTMISC :: H2M_MMP_OUTBOX_4 :: m2h_mmp_outbox [31:00] */
-#define BCHP_MOCA_HOSTMISC_H2M_MMP_OUTBOX_4_m2h_mmp_outbox_MASK 0xffffffff
-#define BCHP_MOCA_HOSTMISC_H2M_MMP_OUTBOX_4_m2h_mmp_outbox_SHIFT 0
-#define BCHP_MOCA_HOSTMISC_H2M_MMP_OUTBOX_4_m2h_mmp_outbox_DEFAULT 0x00000000
-
-/***************************************************************************
- *H2M_MMP_OUTBOX_5 - Host to MoCA MMP outbox registes , register set index 5.
- ***************************************************************************/
-/* MOCA_HOSTMISC :: H2M_MMP_OUTBOX_5 :: m2h_mmp_outbox [31:00] */
-#define BCHP_MOCA_HOSTMISC_H2M_MMP_OUTBOX_5_m2h_mmp_outbox_MASK 0xffffffff
-#define BCHP_MOCA_HOSTMISC_H2M_MMP_OUTBOX_5_m2h_mmp_outbox_SHIFT 0
-#define BCHP_MOCA_HOSTMISC_H2M_MMP_OUTBOX_5_m2h_mmp_outbox_DEFAULT 0x00000000
-
-/***************************************************************************
- *H2M_MMP_OUTBOX_6 - Host to MoCA MMP outbox registes , register set index 6.
- ***************************************************************************/
-/* MOCA_HOSTMISC :: H2M_MMP_OUTBOX_6 :: m2h_mmp_outbox [31:00] */
-#define BCHP_MOCA_HOSTMISC_H2M_MMP_OUTBOX_6_m2h_mmp_outbox_MASK 0xffffffff
-#define BCHP_MOCA_HOSTMISC_H2M_MMP_OUTBOX_6_m2h_mmp_outbox_SHIFT 0
-#define BCHP_MOCA_HOSTMISC_H2M_MMP_OUTBOX_6_m2h_mmp_outbox_DEFAULT 0x00000000
-
-/***************************************************************************
- *H2M_MMP_OUTBOX_7 - Host to MoCA MMP outbox registes , register set index 7.
- ***************************************************************************/
-/* MOCA_HOSTMISC :: H2M_MMP_OUTBOX_7 :: m2h_mmp_outbox [31:00] */
-#define BCHP_MOCA_HOSTMISC_H2M_MMP_OUTBOX_7_m2h_mmp_outbox_MASK 0xffffffff
-#define BCHP_MOCA_HOSTMISC_H2M_MMP_OUTBOX_7_m2h_mmp_outbox_SHIFT 0
-#define BCHP_MOCA_HOSTMISC_H2M_MMP_OUTBOX_7_m2h_mmp_outbox_DEFAULT 0x00000000
-
-/***************************************************************************
- *H2M_MMP_OUTBOX_8 - Host to MoCA MMP outbox registes , register set index 8.
- ***************************************************************************/
-/* MOCA_HOSTMISC :: H2M_MMP_OUTBOX_8 :: m2h_mmp_outbox [31:00] */
-#define BCHP_MOCA_HOSTMISC_H2M_MMP_OUTBOX_8_m2h_mmp_outbox_MASK 0xffffffff
-#define BCHP_MOCA_HOSTMISC_H2M_MMP_OUTBOX_8_m2h_mmp_outbox_SHIFT 0
-#define BCHP_MOCA_HOSTMISC_H2M_MMP_OUTBOX_8_m2h_mmp_outbox_DEFAULT 0x00000000
-
-/***************************************************************************
- *H2M_MMP_OUTBOX_9 - Host to MoCA MMP outbox registes , register set index 9.
- ***************************************************************************/
-/* MOCA_HOSTMISC :: H2M_MMP_OUTBOX_9 :: m2h_mmp_outbox [31:00] */
-#define BCHP_MOCA_HOSTMISC_H2M_MMP_OUTBOX_9_m2h_mmp_outbox_MASK 0xffffffff
-#define BCHP_MOCA_HOSTMISC_H2M_MMP_OUTBOX_9_m2h_mmp_outbox_SHIFT 0
-#define BCHP_MOCA_HOSTMISC_H2M_MMP_OUTBOX_9_m2h_mmp_outbox_DEFAULT 0x00000000
-
-/***************************************************************************
- *H2M_MMP_OUTBOX_10 - Host to MoCA MMP outbox registes , register set index 10.
- ***************************************************************************/
-/* MOCA_HOSTMISC :: H2M_MMP_OUTBOX_10 :: m2h_mmp_outbox [31:00] */
-#define BCHP_MOCA_HOSTMISC_H2M_MMP_OUTBOX_10_m2h_mmp_outbox_MASK 0xffffffff
-#define BCHP_MOCA_HOSTMISC_H2M_MMP_OUTBOX_10_m2h_mmp_outbox_SHIFT 0
-#define BCHP_MOCA_HOSTMISC_H2M_MMP_OUTBOX_10_m2h_mmp_outbox_DEFAULT 0x00000000
-
-/***************************************************************************
- *H2M_MMP_OUTBOX_11 - Host to MoCA MMP outbox registes , register set index 11.
- ***************************************************************************/
-/* MOCA_HOSTMISC :: H2M_MMP_OUTBOX_11 :: m2h_mmp_outbox [31:00] */
-#define BCHP_MOCA_HOSTMISC_H2M_MMP_OUTBOX_11_m2h_mmp_outbox_MASK 0xffffffff
-#define BCHP_MOCA_HOSTMISC_H2M_MMP_OUTBOX_11_m2h_mmp_outbox_SHIFT 0
-#define BCHP_MOCA_HOSTMISC_H2M_MMP_OUTBOX_11_m2h_mmp_outbox_DEFAULT 0x00000000
-
-/***************************************************************************
- *H2M_MMP_OUTBOX_12 - Host to MoCA MMP outbox registes , register set index 12.
- ***************************************************************************/
-/* MOCA_HOSTMISC :: H2M_MMP_OUTBOX_12 :: m2h_mmp_outbox [31:00] */
-#define BCHP_MOCA_HOSTMISC_H2M_MMP_OUTBOX_12_m2h_mmp_outbox_MASK 0xffffffff
-#define BCHP_MOCA_HOSTMISC_H2M_MMP_OUTBOX_12_m2h_mmp_outbox_SHIFT 0
-#define BCHP_MOCA_HOSTMISC_H2M_MMP_OUTBOX_12_m2h_mmp_outbox_DEFAULT 0x00000000
-
-/***************************************************************************
- *H2M_MMP_OUTBOX_13 - Host to MoCA MMP outbox registes , register set index 13.
- ***************************************************************************/
-/* MOCA_HOSTMISC :: H2M_MMP_OUTBOX_13 :: m2h_mmp_outbox [31:00] */
-#define BCHP_MOCA_HOSTMISC_H2M_MMP_OUTBOX_13_m2h_mmp_outbox_MASK 0xffffffff
-#define BCHP_MOCA_HOSTMISC_H2M_MMP_OUTBOX_13_m2h_mmp_outbox_SHIFT 0
-#define BCHP_MOCA_HOSTMISC_H2M_MMP_OUTBOX_13_m2h_mmp_outbox_DEFAULT 0x00000000
-
-/***************************************************************************
- *H2M_MMP_OUTBOX_14 - Host to MoCA MMP outbox registes , register set index 14.
- ***************************************************************************/
-/* MOCA_HOSTMISC :: H2M_MMP_OUTBOX_14 :: m2h_mmp_outbox [31:00] */
-#define BCHP_MOCA_HOSTMISC_H2M_MMP_OUTBOX_14_m2h_mmp_outbox_MASK 0xffffffff
-#define BCHP_MOCA_HOSTMISC_H2M_MMP_OUTBOX_14_m2h_mmp_outbox_SHIFT 0
-#define BCHP_MOCA_HOSTMISC_H2M_MMP_OUTBOX_14_m2h_mmp_outbox_DEFAULT 0x00000000
-
-/***************************************************************************
- *H2M_MMP_OUTBOX_15 - Host to MoCA MMP outbox registes , register set index 15.
- ***************************************************************************/
-/* MOCA_HOSTMISC :: H2M_MMP_OUTBOX_15 :: m2h_mmp_outbox [31:00] */
-#define BCHP_MOCA_HOSTMISC_H2M_MMP_OUTBOX_15_m2h_mmp_outbox_MASK 0xffffffff
-#define BCHP_MOCA_HOSTMISC_H2M_MMP_OUTBOX_15_m2h_mmp_outbox_SHIFT 0
-#define BCHP_MOCA_HOSTMISC_H2M_MMP_OUTBOX_15_m2h_mmp_outbox_DEFAULT 0x00000000
-
-/***************************************************************************
- *M2H_MMP_INBOX_0 - MoCA to Host MMP inbox registers , register set index 0.
- ***************************************************************************/
-/* MOCA_HOSTMISC :: M2H_MMP_INBOX_0 :: h2m_mmp_inbox [31:00] */
-#define BCHP_MOCA_HOSTMISC_M2H_MMP_INBOX_0_h2m_mmp_inbox_MASK 0xffffffff
-#define BCHP_MOCA_HOSTMISC_M2H_MMP_INBOX_0_h2m_mmp_inbox_SHIFT 0
-#define BCHP_MOCA_HOSTMISC_M2H_MMP_INBOX_0_h2m_mmp_inbox_DEFAULT 0x00000000
-
-/***************************************************************************
- *M2H_MMP_INBOX_1 - MoCA to Host MMP inbox registers , register set index 1.
- ***************************************************************************/
-/* MOCA_HOSTMISC :: M2H_MMP_INBOX_1 :: h2m_mmp_inbox [31:00] */
-#define BCHP_MOCA_HOSTMISC_M2H_MMP_INBOX_1_h2m_mmp_inbox_MASK 0xffffffff
-#define BCHP_MOCA_HOSTMISC_M2H_MMP_INBOX_1_h2m_mmp_inbox_SHIFT 0
-#define BCHP_MOCA_HOSTMISC_M2H_MMP_INBOX_1_h2m_mmp_inbox_DEFAULT 0x00000000
-
-/***************************************************************************
- *M2H_MMP_INBOX_2 - MoCA to Host MMP inbox registers , register set index 2.
- ***************************************************************************/
-/* MOCA_HOSTMISC :: M2H_MMP_INBOX_2 :: h2m_mmp_inbox [31:00] */
-#define BCHP_MOCA_HOSTMISC_M2H_MMP_INBOX_2_h2m_mmp_inbox_MASK 0xffffffff
-#define BCHP_MOCA_HOSTMISC_M2H_MMP_INBOX_2_h2m_mmp_inbox_SHIFT 0
-#define BCHP_MOCA_HOSTMISC_M2H_MMP_INBOX_2_h2m_mmp_inbox_DEFAULT 0x00000000
-
-/***************************************************************************
- *M2H_MMP_INBOX_3 - MoCA to Host MMP inbox registers , register set index 3.
- ***************************************************************************/
-/* MOCA_HOSTMISC :: M2H_MMP_INBOX_3 :: h2m_mmp_inbox [31:00] */
-#define BCHP_MOCA_HOSTMISC_M2H_MMP_INBOX_3_h2m_mmp_inbox_MASK 0xffffffff
-#define BCHP_MOCA_HOSTMISC_M2H_MMP_INBOX_3_h2m_mmp_inbox_SHIFT 0
-#define BCHP_MOCA_HOSTMISC_M2H_MMP_INBOX_3_h2m_mmp_inbox_DEFAULT 0x00000000
-
-/***************************************************************************
- *M2H_MMP_INBOX_4 - MoCA to Host MMP inbox registers , register set index 4.
- ***************************************************************************/
-/* MOCA_HOSTMISC :: M2H_MMP_INBOX_4 :: h2m_mmp_inbox [31:00] */
-#define BCHP_MOCA_HOSTMISC_M2H_MMP_INBOX_4_h2m_mmp_inbox_MASK 0xffffffff
-#define BCHP_MOCA_HOSTMISC_M2H_MMP_INBOX_4_h2m_mmp_inbox_SHIFT 0
-#define BCHP_MOCA_HOSTMISC_M2H_MMP_INBOX_4_h2m_mmp_inbox_DEFAULT 0x00000000
-
-/***************************************************************************
- *M2H_MMP_INBOX_5 - MoCA to Host MMP inbox registers , register set index 5.
- ***************************************************************************/
-/* MOCA_HOSTMISC :: M2H_MMP_INBOX_5 :: h2m_mmp_inbox [31:00] */
-#define BCHP_MOCA_HOSTMISC_M2H_MMP_INBOX_5_h2m_mmp_inbox_MASK 0xffffffff
-#define BCHP_MOCA_HOSTMISC_M2H_MMP_INBOX_5_h2m_mmp_inbox_SHIFT 0
-#define BCHP_MOCA_HOSTMISC_M2H_MMP_INBOX_5_h2m_mmp_inbox_DEFAULT 0x00000000
-
-/***************************************************************************
- *M2H_MMP_INBOX_6 - MoCA to Host MMP inbox registers , register set index 6.
- ***************************************************************************/
-/* MOCA_HOSTMISC :: M2H_MMP_INBOX_6 :: h2m_mmp_inbox [31:00] */
-#define BCHP_MOCA_HOSTMISC_M2H_MMP_INBOX_6_h2m_mmp_inbox_MASK 0xffffffff
-#define BCHP_MOCA_HOSTMISC_M2H_MMP_INBOX_6_h2m_mmp_inbox_SHIFT 0
-#define BCHP_MOCA_HOSTMISC_M2H_MMP_INBOX_6_h2m_mmp_inbox_DEFAULT 0x00000000
-
-/***************************************************************************
- *M2H_MMP_INBOX_7 - MoCA to Host MMP inbox registers , register set index 7.
- ***************************************************************************/
-/* MOCA_HOSTMISC :: M2H_MMP_INBOX_7 :: h2m_mmp_inbox [31:00] */
-#define BCHP_MOCA_HOSTMISC_M2H_MMP_INBOX_7_h2m_mmp_inbox_MASK 0xffffffff
-#define BCHP_MOCA_HOSTMISC_M2H_MMP_INBOX_7_h2m_mmp_inbox_SHIFT 0
-#define BCHP_MOCA_HOSTMISC_M2H_MMP_INBOX_7_h2m_mmp_inbox_DEFAULT 0x00000000
-
-/***************************************************************************
- *M2H_MMP_INBOX_8 - MoCA to Host MMP inbox registers , register set index 8.
- ***************************************************************************/
-/* MOCA_HOSTMISC :: M2H_MMP_INBOX_8 :: h2m_mmp_inbox [31:00] */
-#define BCHP_MOCA_HOSTMISC_M2H_MMP_INBOX_8_h2m_mmp_inbox_MASK 0xffffffff
-#define BCHP_MOCA_HOSTMISC_M2H_MMP_INBOX_8_h2m_mmp_inbox_SHIFT 0
-#define BCHP_MOCA_HOSTMISC_M2H_MMP_INBOX_8_h2m_mmp_inbox_DEFAULT 0x00000000
-
-/***************************************************************************
- *M2H_MMP_INBOX_9 - MoCA to Host MMP inbox registers , register set index 9.
- ***************************************************************************/
-/* MOCA_HOSTMISC :: M2H_MMP_INBOX_9 :: h2m_mmp_inbox [31:00] */
-#define BCHP_MOCA_HOSTMISC_M2H_MMP_INBOX_9_h2m_mmp_inbox_MASK 0xffffffff
-#define BCHP_MOCA_HOSTMISC_M2H_MMP_INBOX_9_h2m_mmp_inbox_SHIFT 0
-#define BCHP_MOCA_HOSTMISC_M2H_MMP_INBOX_9_h2m_mmp_inbox_DEFAULT 0x00000000
-
-/***************************************************************************
- *M2H_MMP_INBOX_10 - MoCA to Host MMP inbox registers , register set index 10.
- ***************************************************************************/
-/* MOCA_HOSTMISC :: M2H_MMP_INBOX_10 :: h2m_mmp_inbox [31:00] */
-#define BCHP_MOCA_HOSTMISC_M2H_MMP_INBOX_10_h2m_mmp_inbox_MASK 0xffffffff
-#define BCHP_MOCA_HOSTMISC_M2H_MMP_INBOX_10_h2m_mmp_inbox_SHIFT 0
-#define BCHP_MOCA_HOSTMISC_M2H_MMP_INBOX_10_h2m_mmp_inbox_DEFAULT 0x00000000
-
-/***************************************************************************
- *M2H_MMP_INBOX_11 - MoCA to Host MMP inbox registers , register set index 11.
- ***************************************************************************/
-/* MOCA_HOSTMISC :: M2H_MMP_INBOX_11 :: h2m_mmp_inbox [31:00] */
-#define BCHP_MOCA_HOSTMISC_M2H_MMP_INBOX_11_h2m_mmp_inbox_MASK 0xffffffff
-#define BCHP_MOCA_HOSTMISC_M2H_MMP_INBOX_11_h2m_mmp_inbox_SHIFT 0
-#define BCHP_MOCA_HOSTMISC_M2H_MMP_INBOX_11_h2m_mmp_inbox_DEFAULT 0x00000000
-
-/***************************************************************************
- *M2H_MMP_INBOX_12 - MoCA to Host MMP inbox registers , register set index 12.
- ***************************************************************************/
-/* MOCA_HOSTMISC :: M2H_MMP_INBOX_12 :: h2m_mmp_inbox [31:00] */
-#define BCHP_MOCA_HOSTMISC_M2H_MMP_INBOX_12_h2m_mmp_inbox_MASK 0xffffffff
-#define BCHP_MOCA_HOSTMISC_M2H_MMP_INBOX_12_h2m_mmp_inbox_SHIFT 0
-#define BCHP_MOCA_HOSTMISC_M2H_MMP_INBOX_12_h2m_mmp_inbox_DEFAULT 0x00000000
-
-/***************************************************************************
- *M2H_MMP_INBOX_13 - MoCA to Host MMP inbox registers , register set index 13.
- ***************************************************************************/
-/* MOCA_HOSTMISC :: M2H_MMP_INBOX_13 :: h2m_mmp_inbox [31:00] */
-#define BCHP_MOCA_HOSTMISC_M2H_MMP_INBOX_13_h2m_mmp_inbox_MASK 0xffffffff
-#define BCHP_MOCA_HOSTMISC_M2H_MMP_INBOX_13_h2m_mmp_inbox_SHIFT 0
-#define BCHP_MOCA_HOSTMISC_M2H_MMP_INBOX_13_h2m_mmp_inbox_DEFAULT 0x00000000
-
-/***************************************************************************
- *M2H_MMP_INBOX_14 - MoCA to Host MMP inbox registers , register set index 14.
- ***************************************************************************/
-/* MOCA_HOSTMISC :: M2H_MMP_INBOX_14 :: h2m_mmp_inbox [31:00] */
-#define BCHP_MOCA_HOSTMISC_M2H_MMP_INBOX_14_h2m_mmp_inbox_MASK 0xffffffff
-#define BCHP_MOCA_HOSTMISC_M2H_MMP_INBOX_14_h2m_mmp_inbox_SHIFT 0
-#define BCHP_MOCA_HOSTMISC_M2H_MMP_INBOX_14_h2m_mmp_inbox_DEFAULT 0x00000000
-
-/***************************************************************************
- *M2H_MMP_INBOX_15 - MoCA to Host MMP inbox registers , register set index 15.
- ***************************************************************************/
-/* MOCA_HOSTMISC :: M2H_MMP_INBOX_15 :: h2m_mmp_inbox [31:00] */
-#define BCHP_MOCA_HOSTMISC_M2H_MMP_INBOX_15_h2m_mmp_inbox_MASK 0xffffffff
-#define BCHP_MOCA_HOSTMISC_M2H_MMP_INBOX_15_h2m_mmp_inbox_SHIFT 0
-#define BCHP_MOCA_HOSTMISC_M2H_MMP_INBOX_15_h2m_mmp_inbox_DEFAULT 0x00000000
-
-/***************************************************************************
- *DMPG_CHAINS_STATUS - "MoCA dynamic memory power gating chain power up (bit per chain),Active when moca_dmpg_gisb_en is high,0: Chain is on,1: Chain is off"
- ***************************************************************************/
-/* MOCA_HOSTMISC :: DMPG_CHAINS_STATUS :: dmpg_pda_out_status [31:00] */
-#define BCHP_MOCA_HOSTMISC_DMPG_CHAINS_STATUS_dmpg_pda_out_status_MASK 0xffffffff
-#define BCHP_MOCA_HOSTMISC_DMPG_CHAINS_STATUS_dmpg_pda_out_status_SHIFT 0
-#define BCHP_MOCA_HOSTMISC_DMPG_CHAINS_STATUS_dmpg_pda_out_status_DEFAULT 0x00000000
-
-/***************************************************************************
- *DMPG_CHAINS_PWR_UP - "MoCA dynamic memory power gating chain status (bit per chain),0: Power down chain,1: Power up chain"
- ***************************************************************************/
-/* MOCA_HOSTMISC :: DMPG_CHAINS_PWR_UP :: dmpg_pwr_up [31:00] */
-#define BCHP_MOCA_HOSTMISC_DMPG_CHAINS_PWR_UP_dmpg_pwr_up_MASK 0xffffffff
-#define BCHP_MOCA_HOSTMISC_DMPG_CHAINS_PWR_UP_dmpg_pwr_up_SHIFT 0
-#define BCHP_MOCA_HOSTMISC_DMPG_CHAINS_PWR_UP_dmpg_pwr_up_DEFAULT 0xffffffff
-
-#endif /* #ifndef BCHP_MOCA_HOSTMISC_H__ */
-
-/* End of File */
diff --git a/include/linux/brcmstb/7366b0/bchp_nand.h b/include/linux/brcmstb/7366b0/bchp_nand.h
deleted file mode 100644
index db4fc21..0000000
--- a/include/linux/brcmstb/7366b0/bchp_nand.h
+++ /dev/null
@@ -1,3757 +0,0 @@
-/***************************************************************************
- * Copyright (c) 1999-2014, Broadcom Corporation
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
- *
- * Module Description:
- * DO NOT EDIT THIS FILE DIRECTLY
- *
- * This module was generated magically with RDB from a source description
- * file. You must edit the source file for changes to be made to this file.
- *
- *
- * Date: Generated on Thu Apr 24 03:08:54 2014
- * Full Compile MD5 Checksum 1af2c2cf28828ece5496e1312aac0166
- * (minus title and desc)
- * MD5 Checksum 3203ffce85e3fc9a10f84123e54057b0
- *
- * Compiled with: RDB Utility combo_header.pl
- * RDB Parser 3.0
- * unknown unknown
- * Perl Interpreter 5.008008
- * Operating System linux
- *
- * Revision History:
- *
- * $brcm_Log: $
- *
- ***************************************************************************/
-
-#ifndef BCHP_NAND_H__
-#define BCHP_NAND_H__
-
-/***************************************************************************
- *NAND - Nand Flash Control Registers
- ***************************************************************************/
-#define BCHP_NAND_REVISION 0x00442800 /* NAND Revision */
-#define BCHP_NAND_CMD_START 0x00442804 /* Nand Flash Command Start */
-#define BCHP_NAND_CMD_EXT_ADDRESS 0x00442808 /* Nand Flash Command Extended Address */
-#define BCHP_NAND_CMD_ADDRESS 0x0044280c /* Nand Flash Command Address */
-#define BCHP_NAND_CMD_END_ADDRESS 0x00442810 /* Nand Flash Command End Address */
-#define BCHP_NAND_INTFC_STATUS 0x00442814 /* Nand Flash Interface Status */
-#define BCHP_NAND_CS_NAND_SELECT 0x00442818 /* Nand Flash EBI CS Select */
-#define BCHP_NAND_CS_NAND_XOR 0x0044281c /* Nand Flash EBI CS XOR masking on CPU address Control */
-#define BCHP_NAND_LL_OP 0x00442820 /* Nand Flash Low Level Operation */
-#define BCHP_NAND_MPLANE_BASE_EXT_ADDRESS 0x00442824 /* Nand Flash Multiplane base address */
-#define BCHP_NAND_MPLANE_BASE_ADDRESS 0x00442828 /* Nand Flash Multiplane base address */
-#define BCHP_NAND_ACC_CONTROL_CS0 0x00442850 /* Nand Flash Access Control */
-#define BCHP_NAND_CONFIG_EXT_CS0 0x00442854 /* Nand Flash Config Extension */
-#define BCHP_NAND_CONFIG_CS0 0x00442858 /* Nand Flash Config */
-#define BCHP_NAND_TIMING_1_CS0 0x0044285c /* Nand Flash Timing Parameters 1 */
-#define BCHP_NAND_TIMING_2_CS0 0x00442860 /* Nand Flash Timing Parameters 2 */
-#define BCHP_NAND_ACC_CONTROL_CS1 0x00442864 /* Nand Flash Access Control */
-#define BCHP_NAND_CONFIG_EXT_CS1 0x00442868 /* Nand Flash Config Extension */
-#define BCHP_NAND_CONFIG_CS1 0x0044286c /* Nand Flash Config */
-#define BCHP_NAND_TIMING_1_CS1 0x00442870 /* Nand Flash Timing Parameters 1 */
-#define BCHP_NAND_TIMING_2_CS1 0x00442874 /* Nand Flash Timing Parameters 2 */
-#define BCHP_NAND_ACC_CONTROL_CS2 0x00442878 /* Nand Flash Access Control */
-#define BCHP_NAND_CONFIG_EXT_CS2 0x0044287c /* Nand Flash Config Extension */
-#define BCHP_NAND_CONFIG_CS2 0x00442880 /* Nand Flash Config */
-#define BCHP_NAND_TIMING_1_CS2 0x00442884 /* Nand Flash Timing Parameters 1 */
-#define BCHP_NAND_TIMING_2_CS2 0x00442888 /* Nand Flash Timing Parameters 2 */
-#define BCHP_NAND_ACC_CONTROL_CS3 0x0044288c /* Nand Flash Access Control */
-#define BCHP_NAND_CONFIG_EXT_CS3 0x00442890 /* Nand Flash Config Extension */
-#define BCHP_NAND_CONFIG_CS3 0x00442894 /* Nand Flash Config */
-#define BCHP_NAND_TIMING_1_CS3 0x00442898 /* Nand Flash Timing Parameters 1 */
-#define BCHP_NAND_TIMING_2_CS3 0x0044289c /* Nand Flash Timing Parameters 2 */
-#define BCHP_NAND_ACC_CONTROL_CS4 0x004428a0 /* Nand Flash Access Control */
-#define BCHP_NAND_CONFIG_EXT_CS4 0x004428a4 /* Nand Flash Config Extension */
-#define BCHP_NAND_CONFIG_CS4 0x004428a8 /* Nand Flash Config */
-#define BCHP_NAND_TIMING_1_CS4 0x004428ac /* Nand Flash Timing Parameters 1 */
-#define BCHP_NAND_TIMING_2_CS4 0x004428b0 /* Nand Flash Timing Parameters 2 */
-#define BCHP_NAND_ACC_CONTROL_CS5 0x004428b4 /* Nand Flash Access Control */
-#define BCHP_NAND_CONFIG_EXT_CS5 0x004428b8 /* Nand Flash Config Extension */
-#define BCHP_NAND_CONFIG_CS5 0x004428bc /* Nand Flash Config */
-#define BCHP_NAND_TIMING_1_CS5 0x004428c0 /* Nand Flash Timing Parameters 1 */
-#define BCHP_NAND_TIMING_2_CS5 0x004428c4 /* Nand Flash Timing Parameters 2 */
-#define BCHP_NAND_ACC_CONTROL_CS6 0x004428c8 /* Nand Flash Access Control */
-#define BCHP_NAND_CONFIG_EXT_CS6 0x004428cc /* Nand Flash Config Extension */
-#define BCHP_NAND_CONFIG_CS6 0x004428d0 /* Nand Flash Config */
-#define BCHP_NAND_TIMING_1_CS6 0x004428d4 /* Nand Flash Timing Parameters 1 */
-#define BCHP_NAND_TIMING_2_CS6 0x004428d8 /* Nand Flash Timing Parameters 2 */
-#define BCHP_NAND_CORR_STAT_THRESHOLD 0x004428dc /* Correctable Error Reporting Threshold */
-#define BCHP_NAND_CORR_STAT_THRESHOLD_EXT 0x004428e0 /* Correctable Error Reporting Threshold */
-#define BCHP_NAND_BLK_WR_PROTECT 0x004428e4 /* Block Write Protect Enable and Size for EBI_CS0b */
-#define BCHP_NAND_MULTIPLANE_OPCODES_1 0x004428e8 /* Nand Flash Multiplane Customized Opcodes */
-#define BCHP_NAND_MULTIPLANE_OPCODES_2 0x004428ec /* Nand Flash Multiplane Customized Opcodes */
-#define BCHP_NAND_MULTIPLANE_CTRL 0x004428f0 /* Nand Flash Multiplane Control */
-#define BCHP_NAND_UNCORR_ERROR_COUNT 0x004428fc /* Read Uncorrectable Event Count */
-#define BCHP_NAND_CORR_ERROR_COUNT 0x00442900 /* Read Error Count */
-#define BCHP_NAND_READ_ERROR_COUNT 0x00442904 /* Read Error Count */
-#define BCHP_NAND_BLOCK_LOCK_STATUS 0x00442908 /* Nand Flash Block Lock Status */
-#define BCHP_NAND_ECC_CORR_EXT_ADDR 0x0044290c /* ECC Correctable Error Extended Address */
-#define BCHP_NAND_ECC_CORR_ADDR 0x00442910 /* ECC Correctable Error Address */
-#define BCHP_NAND_ECC_UNC_EXT_ADDR 0x00442914 /* ECC Uncorrectable Error Extended Address */
-#define BCHP_NAND_ECC_UNC_ADDR 0x00442918 /* ECC Uncorrectable Error Address */
-#define BCHP_NAND_FLASH_READ_EXT_ADDR 0x0044291c /* Flash Read Data Extended Address */
-#define BCHP_NAND_FLASH_READ_ADDR 0x00442920 /* Flash Read Data Address */
-#define BCHP_NAND_PROGRAM_PAGE_EXT_ADDR 0x00442924 /* Page Program Extended Address */
-#define BCHP_NAND_PROGRAM_PAGE_ADDR 0x00442928 /* Page Program Address */
-#define BCHP_NAND_COPY_BACK_EXT_ADDR 0x0044292c /* Copy Back Extended Address */
-#define BCHP_NAND_COPY_BACK_ADDR 0x00442930 /* Copy Back Address */
-#define BCHP_NAND_BLOCK_ERASE_EXT_ADDR 0x00442934 /* Block Erase Extended Address */
-#define BCHP_NAND_BLOCK_ERASE_ADDR 0x00442938 /* Block Erase Address */
-#define BCHP_NAND_INV_READ_EXT_ADDR 0x0044293c /* Flash Invalid Data Extended Address */
-#define BCHP_NAND_INV_READ_ADDR 0x00442940 /* Flash Invalid Data Address */
-#define BCHP_NAND_INIT_STATUS 0x00442944 /* Initialization status */
-#define BCHP_NAND_ONFI_STATUS 0x00442948 /* ONFI Status */
-#define BCHP_NAND_ONFI_DEBUG_DATA 0x0044294c /* ONFI Debug Data */
-#define BCHP_NAND_SEMAPHORE 0x00442950 /* Semaphore */
-#define BCHP_NAND_FLASH_DEVICE_ID 0x00442994 /* Nand Flash Device ID */
-#define BCHP_NAND_FLASH_DEVICE_ID_EXT 0x00442998 /* Nand Flash Extended Device ID */
-#define BCHP_NAND_LL_RDDATA 0x0044299c /* Nand Flash Low Level Read Data */
-#define BCHP_NAND_SPARE_AREA_READ_OFS_0 0x00442a00 /* Nand Flash Spare Area Read Bytes 0-3 */
-#define BCHP_NAND_SPARE_AREA_READ_OFS_4 0x00442a04 /* Nand Flash Spare Area Read Bytes 4-7 */
-#define BCHP_NAND_SPARE_AREA_READ_OFS_8 0x00442a08 /* Nand Flash Spare Area Read Bytes 8-11 */
-#define BCHP_NAND_SPARE_AREA_READ_OFS_C 0x00442a0c /* Nand Flash Spare Area Read Bytes 12-15 */
-#define BCHP_NAND_SPARE_AREA_READ_OFS_10 0x00442a10 /* Nand Flash Spare Area Read Bytes 16-19 */
-#define BCHP_NAND_SPARE_AREA_READ_OFS_14 0x00442a14 /* Nand Flash Spare Area Read Bytes 20-23 */
-#define BCHP_NAND_SPARE_AREA_READ_OFS_18 0x00442a18 /* Nand Flash Spare Area Read Bytes 24-27 */
-#define BCHP_NAND_SPARE_AREA_READ_OFS_1C 0x00442a1c /* Nand Flash Spare Area Read Bytes 28-31 */
-#define BCHP_NAND_SPARE_AREA_READ_OFS_20 0x00442a20 /* Nand Flash Spare Area Read Bytes 32-35 */
-#define BCHP_NAND_SPARE_AREA_READ_OFS_24 0x00442a24 /* Nand Flash Spare Area Read Bytes 36-39 */
-#define BCHP_NAND_SPARE_AREA_READ_OFS_28 0x00442a28 /* Nand Flash Spare Area Read Bytes 40-43 */
-#define BCHP_NAND_SPARE_AREA_READ_OFS_2C 0x00442a2c /* Nand Flash Spare Area Read Bytes 44-47 */
-#define BCHP_NAND_SPARE_AREA_READ_OFS_30 0x00442a30 /* Nand Flash Spare Area Read Bytes 48-51 */
-#define BCHP_NAND_SPARE_AREA_READ_OFS_34 0x00442a34 /* Nand Flash Spare Area Read Bytes 52-55 */
-#define BCHP_NAND_SPARE_AREA_READ_OFS_38 0x00442a38 /* Nand Flash Spare Area Read Bytes 56-59 */
-#define BCHP_NAND_SPARE_AREA_READ_OFS_3C 0x00442a3c /* Nand Flash Spare Area Read Bytes 60-63 */
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_0 0x00442a80 /* Nand Flash Spare Area Write Bytes 0-3 */
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_4 0x00442a84 /* Nand Flash Spare Area Write Bytes 4-7 */
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_8 0x00442a88 /* Nand Flash Spare Area Write Bytes 8-11 */
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_C 0x00442a8c /* Nand Flash Spare Area Write Bytes 12-15 */
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_10 0x00442a90 /* Nand Flash Spare Area Write Bytes 16-19 */
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_14 0x00442a94 /* Nand Flash Spare Area Write Bytes 20-23 */
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_18 0x00442a98 /* Nand Flash Spare Area Write Bytes 24-27 */
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_1C 0x00442a9c /* Nand Flash Spare Area Write Bytes 28-31 */
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_20 0x00442aa0 /* Nand Flash Spare Area Write Bytes 32-35 */
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_24 0x00442aa4 /* Nand Flash Spare Area Write Bytes 36-39 */
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_28 0x00442aa8 /* Nand Flash Spare Area Write Bytes 40-43 */
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_2C 0x00442aac /* Nand Flash Spare Area Write Bytes 44-47 */
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_30 0x00442ab0 /* Nand Flash Spare Area Write Bytes 48-51 */
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_34 0x00442ab4 /* Nand Flash Spare Area Write Bytes 52-55 */
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_38 0x00442ab8 /* Nand Flash Spare Area Write Bytes 56-59 */
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_3C 0x00442abc /* Nand Flash Spare Area Write Bytes 60-63 */
-#define BCHP_NAND_DDR_TIMING 0x00442ac0 /* Nand Flash DDR TIMING */
-#define BCHP_NAND_DDR_NCDL_CALIB_CTL 0x00442ac4 /* Nand Flash Calibration Control for Master DLL */
-#define BCHP_NAND_DDR_NCDL_CALIB_PERIOD 0x00442ac8 /* Nand Flash Calibration Period */
-#define BCHP_NAND_DDR_NCDL_CALIB_STAT 0x00442acc /* Nand Flash Calibration Status for Master DLL */
-#define BCHP_NAND_DDR_NCDL_MODE 0x00442ad0 /* Nand Flash NCDL mode for Slave DLLs */
-#define BCHP_NAND_DDR_NCDL_OFFSET 0x00442ad4 /* Nand Flash NCDL offset for Slave DLLs */
-#define BCHP_NAND_DDR_PHY_CTL 0x00442ad8 /* Nand Flash DDR PHY CONTROL */
-#define BCHP_NAND_DDR_PHY_BIST_CTL 0x00442adc /* Nand Flash DDR PHY BIST CONTROL */
-#define BCHP_NAND_DDR_PHY_BIST_STAT 0x00442ae0 /* Nand Flash DDR PHY BIST STATUS */
-#define BCHP_NAND_DDR_DIAG_STAT0 0x00442ae4 /* Nand Flash DDR DIAG STATUS0 */
-#define BCHP_NAND_DDR_DIAG_STAT1 0x00442ae8 /* Nand Flash DDR DIAG STATUS1 */
-
-/***************************************************************************
- *REVISION - NAND Revision
- ***************************************************************************/
-/* NAND :: REVISION :: reserved0 [31:16] */
-#define BCHP_NAND_REVISION_reserved0_MASK 0xffff0000
-#define BCHP_NAND_REVISION_reserved0_SHIFT 16
-
-/* NAND :: REVISION :: MAJOR [15:08] */
-#define BCHP_NAND_REVISION_MAJOR_MASK 0x0000ff00
-#define BCHP_NAND_REVISION_MAJOR_SHIFT 8
-#define BCHP_NAND_REVISION_MAJOR_DEFAULT 0x00000007
-
-/* NAND :: REVISION :: MINOR [07:00] */
-#define BCHP_NAND_REVISION_MINOR_MASK 0x000000ff
-#define BCHP_NAND_REVISION_MINOR_SHIFT 0
-#define BCHP_NAND_REVISION_MINOR_DEFAULT 0x00000001
-
-/***************************************************************************
- *CMD_START - Nand Flash Command Start
- ***************************************************************************/
-/* NAND :: CMD_START :: reserved0 [31:05] */
-#define BCHP_NAND_CMD_START_reserved0_MASK 0xffffffe0
-#define BCHP_NAND_CMD_START_reserved0_SHIFT 5
-
-/* NAND :: CMD_START :: OPCODE [04:00] */
-#define BCHP_NAND_CMD_START_OPCODE_MASK 0x0000001f
-#define BCHP_NAND_CMD_START_OPCODE_SHIFT 0
-#define BCHP_NAND_CMD_START_OPCODE_DEFAULT 0x00000000
-#define BCHP_NAND_CMD_START_OPCODE_NULL 0
-#define BCHP_NAND_CMD_START_OPCODE_PAGE_READ 1
-#define BCHP_NAND_CMD_START_OPCODE_SPARE_AREA_READ 2
-#define BCHP_NAND_CMD_START_OPCODE_STATUS_READ 3
-#define BCHP_NAND_CMD_START_OPCODE_PROGRAM_PAGE 4
-#define BCHP_NAND_CMD_START_OPCODE_PROGRAM_SPARE_AREA 5
-#define BCHP_NAND_CMD_START_OPCODE_COPY_BACK 6
-#define BCHP_NAND_CMD_START_OPCODE_DEVICE_ID_READ 7
-#define BCHP_NAND_CMD_START_OPCODE_BLOCK_ERASE 8
-#define BCHP_NAND_CMD_START_OPCODE_FLASH_RESET 9
-#define BCHP_NAND_CMD_START_OPCODE_BLOCKS_LOCK 10
-#define BCHP_NAND_CMD_START_OPCODE_BLOCKS_LOCK_DOWN 11
-#define BCHP_NAND_CMD_START_OPCODE_BLOCKS_UNLOCK 12
-#define BCHP_NAND_CMD_START_OPCODE_READ_BLOCKS_LOCK_STATUS 13
-#define BCHP_NAND_CMD_START_OPCODE_PARAMETER_READ 14
-#define BCHP_NAND_CMD_START_OPCODE_PARAMETER_CHANGE_COL 15
-#define BCHP_NAND_CMD_START_OPCODE_LOW_LEVEL_OP 16
-#define BCHP_NAND_CMD_START_OPCODE_PAGE_READ_MULTI 17
-#define BCHP_NAND_CMD_START_OPCODE_STATUS_READ_MULTI 18
-#define BCHP_NAND_CMD_START_OPCODE_PROGRAM_PAGE_MULTI 19
-#define BCHP_NAND_CMD_START_OPCODE_BLOCK_ERASE_MULTI 21
-
-/***************************************************************************
- *CMD_EXT_ADDRESS - Nand Flash Command Extended Address
- ***************************************************************************/
-/* NAND :: CMD_EXT_ADDRESS :: reserved0 [31:19] */
-#define BCHP_NAND_CMD_EXT_ADDRESS_reserved0_MASK 0xfff80000
-#define BCHP_NAND_CMD_EXT_ADDRESS_reserved0_SHIFT 19
-
-/* NAND :: CMD_EXT_ADDRESS :: CS_SEL [18:16] */
-#define BCHP_NAND_CMD_EXT_ADDRESS_CS_SEL_MASK 0x00070000
-#define BCHP_NAND_CMD_EXT_ADDRESS_CS_SEL_SHIFT 16
-#define BCHP_NAND_CMD_EXT_ADDRESS_CS_SEL_DEFAULT 0x00000000
-
-/* NAND :: CMD_EXT_ADDRESS :: EXT_ADDRESS [15:00] */
-#define BCHP_NAND_CMD_EXT_ADDRESS_EXT_ADDRESS_MASK 0x0000ffff
-#define BCHP_NAND_CMD_EXT_ADDRESS_EXT_ADDRESS_SHIFT 0
-#define BCHP_NAND_CMD_EXT_ADDRESS_EXT_ADDRESS_DEFAULT 0x00000000
-
-/***************************************************************************
- *CMD_ADDRESS - Nand Flash Command Address
- ***************************************************************************/
-/* NAND :: CMD_ADDRESS :: ADDRESS [31:00] */
-#define BCHP_NAND_CMD_ADDRESS_ADDRESS_MASK 0xffffffff
-#define BCHP_NAND_CMD_ADDRESS_ADDRESS_SHIFT 0
-#define BCHP_NAND_CMD_ADDRESS_ADDRESS_DEFAULT 0x00000000
-
-/***************************************************************************
- *CMD_END_ADDRESS - Nand Flash Command End Address
- ***************************************************************************/
-/* NAND :: CMD_END_ADDRESS :: ADDRESS [31:00] */
-#define BCHP_NAND_CMD_END_ADDRESS_ADDRESS_MASK 0xffffffff
-#define BCHP_NAND_CMD_END_ADDRESS_ADDRESS_SHIFT 0
-#define BCHP_NAND_CMD_END_ADDRESS_ADDRESS_DEFAULT 0x00000000
-
-/***************************************************************************
- *INTFC_STATUS - Nand Flash Interface Status
- ***************************************************************************/
-/* NAND :: INTFC_STATUS :: CTLR_READY [31:31] */
-#define BCHP_NAND_INTFC_STATUS_CTLR_READY_MASK 0x80000000
-#define BCHP_NAND_INTFC_STATUS_CTLR_READY_SHIFT 31
-
-/* NAND :: INTFC_STATUS :: FLASH_READY [30:30] */
-#define BCHP_NAND_INTFC_STATUS_FLASH_READY_MASK 0x40000000
-#define BCHP_NAND_INTFC_STATUS_FLASH_READY_SHIFT 30
-
-/* NAND :: INTFC_STATUS :: CACHE_VALID [29:29] */
-#define BCHP_NAND_INTFC_STATUS_CACHE_VALID_MASK 0x20000000
-#define BCHP_NAND_INTFC_STATUS_CACHE_VALID_SHIFT 29
-
-/* NAND :: INTFC_STATUS :: SPARE_AREA_VALID [28:28] */
-#define BCHP_NAND_INTFC_STATUS_SPARE_AREA_VALID_MASK 0x10000000
-#define BCHP_NAND_INTFC_STATUS_SPARE_AREA_VALID_SHIFT 28
-
-/* NAND :: INTFC_STATUS :: ERASED [27:27] */
-#define BCHP_NAND_INTFC_STATUS_ERASED_MASK 0x08000000
-#define BCHP_NAND_INTFC_STATUS_ERASED_SHIFT 27
-
-/* NAND :: INTFC_STATUS :: PLANE_READY [26:26] */
-#define BCHP_NAND_INTFC_STATUS_PLANE_READY_MASK 0x04000000
-#define BCHP_NAND_INTFC_STATUS_PLANE_READY_SHIFT 26
-
-/* NAND :: INTFC_STATUS :: reserved0 [25:08] */
-#define BCHP_NAND_INTFC_STATUS_reserved0_MASK 0x03ffff00
-#define BCHP_NAND_INTFC_STATUS_reserved0_SHIFT 8
-
-/* NAND :: INTFC_STATUS :: FLASH_STATUS [07:00] */
-#define BCHP_NAND_INTFC_STATUS_FLASH_STATUS_MASK 0x000000ff
-#define BCHP_NAND_INTFC_STATUS_FLASH_STATUS_SHIFT 0
-#define BCHP_NAND_INTFC_STATUS_FLASH_STATUS_DEFAULT 0x00000000
-
-/***************************************************************************
- *CS_NAND_SELECT - Nand Flash EBI CS Select
- ***************************************************************************/
-/* NAND :: CS_NAND_SELECT :: CS_LOCK [31:31] */
-#define BCHP_NAND_CS_NAND_SELECT_CS_LOCK_MASK 0x80000000
-#define BCHP_NAND_CS_NAND_SELECT_CS_LOCK_SHIFT 31
-#define BCHP_NAND_CS_NAND_SELECT_CS_LOCK_DEFAULT 0x00000000
-
-/* NAND :: CS_NAND_SELECT :: AUTO_DEVICE_ID_CONFIG [30:30] */
-#define BCHP_NAND_CS_NAND_SELECT_AUTO_DEVICE_ID_CONFIG_MASK 0x40000000
-#define BCHP_NAND_CS_NAND_SELECT_AUTO_DEVICE_ID_CONFIG_SHIFT 30
-
-/* NAND :: CS_NAND_SELECT :: NAND_WP [29:29] */
-#define BCHP_NAND_CS_NAND_SELECT_NAND_WP_MASK 0x20000000
-#define BCHP_NAND_CS_NAND_SELECT_NAND_WP_SHIFT 29
-#define BCHP_NAND_CS_NAND_SELECT_NAND_WP_DEFAULT 0x00000001
-
-/* NAND :: CS_NAND_SELECT :: WR_PROTECT_BLK0 [28:28] */
-#define BCHP_NAND_CS_NAND_SELECT_WR_PROTECT_BLK0_MASK 0x10000000
-#define BCHP_NAND_CS_NAND_SELECT_WR_PROTECT_BLK0_SHIFT 28
-#define BCHP_NAND_CS_NAND_SELECT_WR_PROTECT_BLK0_DEFAULT 0x00000000
-
-/* NAND :: CS_NAND_SELECT :: reserved0 [27:16] */
-#define BCHP_NAND_CS_NAND_SELECT_reserved0_MASK 0x0fff0000
-#define BCHP_NAND_CS_NAND_SELECT_reserved0_SHIFT 16
-
-/* NAND :: CS_NAND_SELECT :: EBI_CS_7_USES_NAND [15:15] */
-#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_7_USES_NAND_MASK 0x00008000
-#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_7_USES_NAND_SHIFT 15
-#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_7_USES_NAND_DEFAULT 0x00000000
-
-/* NAND :: CS_NAND_SELECT :: EBI_CS_6_USES_NAND [14:14] */
-#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_6_USES_NAND_MASK 0x00004000
-#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_6_USES_NAND_SHIFT 14
-#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_6_USES_NAND_DEFAULT 0x00000000
-
-/* NAND :: CS_NAND_SELECT :: EBI_CS_5_USES_NAND [13:13] */
-#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_5_USES_NAND_MASK 0x00002000
-#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_5_USES_NAND_SHIFT 13
-#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_5_USES_NAND_DEFAULT 0x00000000
-
-/* NAND :: CS_NAND_SELECT :: EBI_CS_4_USES_NAND [12:12] */
-#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_4_USES_NAND_MASK 0x00001000
-#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_4_USES_NAND_SHIFT 12
-#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_4_USES_NAND_DEFAULT 0x00000000
-
-/* NAND :: CS_NAND_SELECT :: EBI_CS_3_USES_NAND [11:11] */
-#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_3_USES_NAND_MASK 0x00000800
-#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_3_USES_NAND_SHIFT 11
-#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_3_USES_NAND_DEFAULT 0x00000000
-
-/* NAND :: CS_NAND_SELECT :: EBI_CS_2_USES_NAND [10:10] */
-#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_2_USES_NAND_MASK 0x00000400
-#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_2_USES_NAND_SHIFT 10
-#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_2_USES_NAND_DEFAULT 0x00000000
-
-/* NAND :: CS_NAND_SELECT :: EBI_CS_1_USES_NAND [09:09] */
-#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_1_USES_NAND_MASK 0x00000200
-#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_1_USES_NAND_SHIFT 9
-#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_1_USES_NAND_DEFAULT 0x00000000
-
-/* NAND :: CS_NAND_SELECT :: EBI_CS_0_USES_NAND [08:08] */
-#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_0_USES_NAND_MASK 0x00000100
-#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_0_USES_NAND_SHIFT 8
-
-/* NAND :: CS_NAND_SELECT :: EBI_CS_7_SEL [07:07] */
-#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_7_SEL_MASK 0x00000080
-#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_7_SEL_SHIFT 7
-#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_7_SEL_DEFAULT 0x00000000
-
-/* NAND :: CS_NAND_SELECT :: EBI_CS_6_SEL [06:06] */
-#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_6_SEL_MASK 0x00000040
-#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_6_SEL_SHIFT 6
-#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_6_SEL_DEFAULT 0x00000000
-
-/* NAND :: CS_NAND_SELECT :: EBI_CS_5_SEL [05:05] */
-#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_5_SEL_MASK 0x00000020
-#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_5_SEL_SHIFT 5
-#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_5_SEL_DEFAULT 0x00000000
-
-/* NAND :: CS_NAND_SELECT :: EBI_CS_4_SEL [04:04] */
-#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_4_SEL_MASK 0x00000010
-#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_4_SEL_SHIFT 4
-#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_4_SEL_DEFAULT 0x00000000
-
-/* NAND :: CS_NAND_SELECT :: EBI_CS_3_SEL [03:03] */
-#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_3_SEL_MASK 0x00000008
-#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_3_SEL_SHIFT 3
-#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_3_SEL_DEFAULT 0x00000000
-
-/* NAND :: CS_NAND_SELECT :: EBI_CS_2_SEL [02:02] */
-#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_2_SEL_MASK 0x00000004
-#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_2_SEL_SHIFT 2
-#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_2_SEL_DEFAULT 0x00000000
-
-/* NAND :: CS_NAND_SELECT :: EBI_CS_1_SEL [01:01] */
-#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_1_SEL_MASK 0x00000002
-#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_1_SEL_SHIFT 1
-#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_1_SEL_DEFAULT 0x00000000
-
-/* NAND :: CS_NAND_SELECT :: EBI_CS_0_SEL [00:00] */
-#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_0_SEL_MASK 0x00000001
-#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_0_SEL_SHIFT 0
-
-/***************************************************************************
- *CS_NAND_XOR - Nand Flash EBI CS XOR masking on CPU address Control
- ***************************************************************************/
-/* NAND :: CS_NAND_XOR :: ONLY_BLOCK_0_XOR [31:31] */
-#define BCHP_NAND_CS_NAND_XOR_ONLY_BLOCK_0_XOR_MASK 0x80000000
-#define BCHP_NAND_CS_NAND_XOR_ONLY_BLOCK_0_XOR_SHIFT 31
-#define BCHP_NAND_CS_NAND_XOR_ONLY_BLOCK_0_XOR_DEFAULT 0x00000000
-
-/* NAND :: CS_NAND_XOR :: reserved0 [30:08] */
-#define BCHP_NAND_CS_NAND_XOR_reserved0_MASK 0x7fffff00
-#define BCHP_NAND_CS_NAND_XOR_reserved0_SHIFT 8
-
-/* NAND :: CS_NAND_XOR :: EBI_CS_7_ADDR_XOR [07:07] */
-#define BCHP_NAND_CS_NAND_XOR_EBI_CS_7_ADDR_XOR_MASK 0x00000080
-#define BCHP_NAND_CS_NAND_XOR_EBI_CS_7_ADDR_XOR_SHIFT 7
-#define BCHP_NAND_CS_NAND_XOR_EBI_CS_7_ADDR_XOR_DEFAULT 0x00000000
-
-/* NAND :: CS_NAND_XOR :: EBI_CS_6_ADDR_XOR [06:06] */
-#define BCHP_NAND_CS_NAND_XOR_EBI_CS_6_ADDR_XOR_MASK 0x00000040
-#define BCHP_NAND_CS_NAND_XOR_EBI_CS_6_ADDR_XOR_SHIFT 6
-#define BCHP_NAND_CS_NAND_XOR_EBI_CS_6_ADDR_XOR_DEFAULT 0x00000000
-
-/* NAND :: CS_NAND_XOR :: EBI_CS_5_ADDR_XOR [05:05] */
-#define BCHP_NAND_CS_NAND_XOR_EBI_CS_5_ADDR_XOR_MASK 0x00000020
-#define BCHP_NAND_CS_NAND_XOR_EBI_CS_5_ADDR_XOR_SHIFT 5
-#define BCHP_NAND_CS_NAND_XOR_EBI_CS_5_ADDR_XOR_DEFAULT 0x00000000
-
-/* NAND :: CS_NAND_XOR :: EBI_CS_4_ADDR_XOR [04:04] */
-#define BCHP_NAND_CS_NAND_XOR_EBI_CS_4_ADDR_XOR_MASK 0x00000010
-#define BCHP_NAND_CS_NAND_XOR_EBI_CS_4_ADDR_XOR_SHIFT 4
-#define BCHP_NAND_CS_NAND_XOR_EBI_CS_4_ADDR_XOR_DEFAULT 0x00000000
-
-/* NAND :: CS_NAND_XOR :: EBI_CS_3_ADDR_XOR [03:03] */
-#define BCHP_NAND_CS_NAND_XOR_EBI_CS_3_ADDR_XOR_MASK 0x00000008
-#define BCHP_NAND_CS_NAND_XOR_EBI_CS_3_ADDR_XOR_SHIFT 3
-#define BCHP_NAND_CS_NAND_XOR_EBI_CS_3_ADDR_XOR_DEFAULT 0x00000000
-
-/* NAND :: CS_NAND_XOR :: EBI_CS_2_ADDR_XOR [02:02] */
-#define BCHP_NAND_CS_NAND_XOR_EBI_CS_2_ADDR_XOR_MASK 0x00000004
-#define BCHP_NAND_CS_NAND_XOR_EBI_CS_2_ADDR_XOR_SHIFT 2
-#define BCHP_NAND_CS_NAND_XOR_EBI_CS_2_ADDR_XOR_DEFAULT 0x00000000
-
-/* NAND :: CS_NAND_XOR :: EBI_CS_1_ADDR_XOR [01:01] */
-#define BCHP_NAND_CS_NAND_XOR_EBI_CS_1_ADDR_XOR_MASK 0x00000002
-#define BCHP_NAND_CS_NAND_XOR_EBI_CS_1_ADDR_XOR_SHIFT 1
-#define BCHP_NAND_CS_NAND_XOR_EBI_CS_1_ADDR_XOR_DEFAULT 0x00000000
-
-/* NAND :: CS_NAND_XOR :: EBI_CS_0_ADDR_XOR [00:00] */
-#define BCHP_NAND_CS_NAND_XOR_EBI_CS_0_ADDR_XOR_MASK 0x00000001
-#define BCHP_NAND_CS_NAND_XOR_EBI_CS_0_ADDR_XOR_SHIFT 0
-
-/***************************************************************************
- *LL_OP - Nand Flash Low Level Operation
- ***************************************************************************/
-/* NAND :: LL_OP :: RETURN_IDLE [31:31] */
-#define BCHP_NAND_LL_OP_RETURN_IDLE_MASK 0x80000000
-#define BCHP_NAND_LL_OP_RETURN_IDLE_SHIFT 31
-#define BCHP_NAND_LL_OP_RETURN_IDLE_DEFAULT 0x00000000
-
-/* NAND :: LL_OP :: reserved0 [30:20] */
-#define BCHP_NAND_LL_OP_reserved0_MASK 0x7ff00000
-#define BCHP_NAND_LL_OP_reserved0_SHIFT 20
-
-/* NAND :: LL_OP :: CLE [19:19] */
-#define BCHP_NAND_LL_OP_CLE_MASK 0x00080000
-#define BCHP_NAND_LL_OP_CLE_SHIFT 19
-#define BCHP_NAND_LL_OP_CLE_DEFAULT 0x00000000
-
-/* NAND :: LL_OP :: ALE [18:18] */
-#define BCHP_NAND_LL_OP_ALE_MASK 0x00040000
-#define BCHP_NAND_LL_OP_ALE_SHIFT 18
-#define BCHP_NAND_LL_OP_ALE_DEFAULT 0x00000000
-
-/* NAND :: LL_OP :: WE [17:17] */
-#define BCHP_NAND_LL_OP_WE_MASK 0x00020000
-#define BCHP_NAND_LL_OP_WE_SHIFT 17
-#define BCHP_NAND_LL_OP_WE_DEFAULT 0x00000000
-
-/* NAND :: LL_OP :: RE [16:16] */
-#define BCHP_NAND_LL_OP_RE_MASK 0x00010000
-#define BCHP_NAND_LL_OP_RE_SHIFT 16
-#define BCHP_NAND_LL_OP_RE_DEFAULT 0x00000000
-
-/* NAND :: LL_OP :: DATA [15:00] */
-#define BCHP_NAND_LL_OP_DATA_MASK 0x0000ffff
-#define BCHP_NAND_LL_OP_DATA_SHIFT 0
-#define BCHP_NAND_LL_OP_DATA_DEFAULT 0x00000000
-
-/***************************************************************************
- *MPLANE_BASE_EXT_ADDRESS - Nand Flash Multiplane base address
- ***************************************************************************/
-/* NAND :: MPLANE_BASE_EXT_ADDRESS :: reserved0 [31:16] */
-#define BCHP_NAND_MPLANE_BASE_EXT_ADDRESS_reserved0_MASK 0xffff0000
-#define BCHP_NAND_MPLANE_BASE_EXT_ADDRESS_reserved0_SHIFT 16
-
-/* NAND :: MPLANE_BASE_EXT_ADDRESS :: EXT_ADDRESS [15:00] */
-#define BCHP_NAND_MPLANE_BASE_EXT_ADDRESS_EXT_ADDRESS_MASK 0x0000ffff
-#define BCHP_NAND_MPLANE_BASE_EXT_ADDRESS_EXT_ADDRESS_SHIFT 0
-#define BCHP_NAND_MPLANE_BASE_EXT_ADDRESS_EXT_ADDRESS_DEFAULT 0x00000000
-
-/***************************************************************************
- *MPLANE_BASE_ADDRESS - Nand Flash Multiplane base address
- ***************************************************************************/
-/* NAND :: MPLANE_BASE_ADDRESS :: ADDRESS [31:00] */
-#define BCHP_NAND_MPLANE_BASE_ADDRESS_ADDRESS_MASK 0xffffffff
-#define BCHP_NAND_MPLANE_BASE_ADDRESS_ADDRESS_SHIFT 0
-#define BCHP_NAND_MPLANE_BASE_ADDRESS_ADDRESS_DEFAULT 0x00000000
-
-/***************************************************************************
- *ACC_CONTROL_CS0 - Nand Flash Access Control
- ***************************************************************************/
-/* NAND :: ACC_CONTROL_CS0 :: RD_ECC_EN [31:31] */
-#define BCHP_NAND_ACC_CONTROL_CS0_RD_ECC_EN_MASK 0x80000000
-#define BCHP_NAND_ACC_CONTROL_CS0_RD_ECC_EN_SHIFT 31
-#define BCHP_NAND_ACC_CONTROL_CS0_RD_ECC_EN_DEFAULT 0x00000001
-
-/* NAND :: ACC_CONTROL_CS0 :: WR_ECC_EN [30:30] */
-#define BCHP_NAND_ACC_CONTROL_CS0_WR_ECC_EN_MASK 0x40000000
-#define BCHP_NAND_ACC_CONTROL_CS0_WR_ECC_EN_SHIFT 30
-#define BCHP_NAND_ACC_CONTROL_CS0_WR_ECC_EN_DEFAULT 0x00000001
-
-/* NAND :: ACC_CONTROL_CS0 :: CE_CARE [29:29] */
-#define BCHP_NAND_ACC_CONTROL_CS0_CE_CARE_MASK 0x20000000
-#define BCHP_NAND_ACC_CONTROL_CS0_CE_CARE_SHIFT 29
-#define BCHP_NAND_ACC_CONTROL_CS0_CE_CARE_DEFAULT 0x00000000
-
-/* NAND :: ACC_CONTROL_CS0 :: reserved0 [28:28] */
-#define BCHP_NAND_ACC_CONTROL_CS0_reserved0_MASK 0x10000000
-#define BCHP_NAND_ACC_CONTROL_CS0_reserved0_SHIFT 28
-
-/* NAND :: ACC_CONTROL_CS0 :: RD_ERASED_ECC_EN [27:27] */
-#define BCHP_NAND_ACC_CONTROL_CS0_RD_ERASED_ECC_EN_MASK 0x08000000
-#define BCHP_NAND_ACC_CONTROL_CS0_RD_ERASED_ECC_EN_SHIFT 27
-#define BCHP_NAND_ACC_CONTROL_CS0_RD_ERASED_ECC_EN_DEFAULT 0x00000000
-
-/* NAND :: ACC_CONTROL_CS0 :: PARTIAL_PAGE_EN [26:26] */
-#define BCHP_NAND_ACC_CONTROL_CS0_PARTIAL_PAGE_EN_MASK 0x04000000
-#define BCHP_NAND_ACC_CONTROL_CS0_PARTIAL_PAGE_EN_SHIFT 26
-#define BCHP_NAND_ACC_CONTROL_CS0_PARTIAL_PAGE_EN_DEFAULT 0x00000000
-
-/* NAND :: ACC_CONTROL_CS0 :: WR_PREEMPT_EN [25:25] */
-#define BCHP_NAND_ACC_CONTROL_CS0_WR_PREEMPT_EN_MASK 0x02000000
-#define BCHP_NAND_ACC_CONTROL_CS0_WR_PREEMPT_EN_SHIFT 25
-#define BCHP_NAND_ACC_CONTROL_CS0_WR_PREEMPT_EN_DEFAULT 0x00000001
-
-/* NAND :: ACC_CONTROL_CS0 :: PAGE_HIT_EN [24:24] */
-#define BCHP_NAND_ACC_CONTROL_CS0_PAGE_HIT_EN_MASK 0x01000000
-#define BCHP_NAND_ACC_CONTROL_CS0_PAGE_HIT_EN_SHIFT 24
-#define BCHP_NAND_ACC_CONTROL_CS0_PAGE_HIT_EN_DEFAULT 0x00000001
-
-/* NAND :: ACC_CONTROL_CS0 :: PREFETCH_EN [23:23] */
-#define BCHP_NAND_ACC_CONTROL_CS0_PREFETCH_EN_MASK 0x00800000
-#define BCHP_NAND_ACC_CONTROL_CS0_PREFETCH_EN_SHIFT 23
-#define BCHP_NAND_ACC_CONTROL_CS0_PREFETCH_EN_DEFAULT 0x00000000
-
-/* NAND :: ACC_CONTROL_CS0 :: CACHE_MODE_EN [22:22] */
-#define BCHP_NAND_ACC_CONTROL_CS0_CACHE_MODE_EN_MASK 0x00400000
-#define BCHP_NAND_ACC_CONTROL_CS0_CACHE_MODE_EN_SHIFT 22
-#define BCHP_NAND_ACC_CONTROL_CS0_CACHE_MODE_EN_DEFAULT 0x00000000
-
-/* NAND :: ACC_CONTROL_CS0 :: reserved1 [21:21] */
-#define BCHP_NAND_ACC_CONTROL_CS0_reserved1_MASK 0x00200000
-#define BCHP_NAND_ACC_CONTROL_CS0_reserved1_SHIFT 21
-
-/* NAND :: ACC_CONTROL_CS0 :: ECC_LEVEL [20:16] */
-#define BCHP_NAND_ACC_CONTROL_CS0_ECC_LEVEL_MASK 0x001f0000
-#define BCHP_NAND_ACC_CONTROL_CS0_ECC_LEVEL_SHIFT 16
-#define BCHP_NAND_ACC_CONTROL_CS0_ECC_LEVEL_DEFAULT 0x0000000f
-
-/* NAND :: ACC_CONTROL_CS0 :: reserved2 [15:08] */
-#define BCHP_NAND_ACC_CONTROL_CS0_reserved2_MASK 0x0000ff00
-#define BCHP_NAND_ACC_CONTROL_CS0_reserved2_SHIFT 8
-
-/* NAND :: ACC_CONTROL_CS0 :: SECTOR_SIZE_1K [07:07] */
-#define BCHP_NAND_ACC_CONTROL_CS0_SECTOR_SIZE_1K_MASK 0x00000080
-#define BCHP_NAND_ACC_CONTROL_CS0_SECTOR_SIZE_1K_SHIFT 7
-#define BCHP_NAND_ACC_CONTROL_CS0_SECTOR_SIZE_1K_DEFAULT 0x00000000
-
-/* NAND :: ACC_CONTROL_CS0 :: SPARE_AREA_SIZE [06:00] */
-#define BCHP_NAND_ACC_CONTROL_CS0_SPARE_AREA_SIZE_MASK 0x0000007f
-#define BCHP_NAND_ACC_CONTROL_CS0_SPARE_AREA_SIZE_SHIFT 0
-#define BCHP_NAND_ACC_CONTROL_CS0_SPARE_AREA_SIZE_DEFAULT 0x00000010
-
-/***************************************************************************
- *CONFIG_EXT_CS0 - Nand Flash Config Extension
- ***************************************************************************/
-/* NAND :: CONFIG_EXT_CS0 :: reserved0 [31:12] */
-#define BCHP_NAND_CONFIG_EXT_CS0_reserved0_MASK 0xfffff000
-#define BCHP_NAND_CONFIG_EXT_CS0_reserved0_SHIFT 12
-
-/* NAND :: CONFIG_EXT_CS0 :: BLOCK_SIZE [11:04] */
-#define BCHP_NAND_CONFIG_EXT_CS0_BLOCK_SIZE_MASK 0x00000ff0
-#define BCHP_NAND_CONFIG_EXT_CS0_BLOCK_SIZE_SHIFT 4
-#define BCHP_NAND_CONFIG_EXT_CS0_BLOCK_SIZE_BK_SIZE_8KB 0
-#define BCHP_NAND_CONFIG_EXT_CS0_BLOCK_SIZE_BK_SIZE_16KB 1
-#define BCHP_NAND_CONFIG_EXT_CS0_BLOCK_SIZE_BK_SIZE_32KB 2
-#define BCHP_NAND_CONFIG_EXT_CS0_BLOCK_SIZE_BK_SIZE_64KB 3
-#define BCHP_NAND_CONFIG_EXT_CS0_BLOCK_SIZE_BK_SIZE_128KB 4
-#define BCHP_NAND_CONFIG_EXT_CS0_BLOCK_SIZE_BK_SIZE_256KB 5
-#define BCHP_NAND_CONFIG_EXT_CS0_BLOCK_SIZE_BK_SIZE_512KB 6
-#define BCHP_NAND_CONFIG_EXT_CS0_BLOCK_SIZE_BK_SIZE_1024KB 7
-#define BCHP_NAND_CONFIG_EXT_CS0_BLOCK_SIZE_BK_SIZE_2048KB 8
-#define BCHP_NAND_CONFIG_EXT_CS0_BLOCK_SIZE_BK_SIZE_4096KB 9
-#define BCHP_NAND_CONFIG_EXT_CS0_BLOCK_SIZE_BK_SIZE_8192KB 10
-
-/* NAND :: CONFIG_EXT_CS0 :: PAGE_SIZE [03:00] */
-#define BCHP_NAND_CONFIG_EXT_CS0_PAGE_SIZE_MASK 0x0000000f
-#define BCHP_NAND_CONFIG_EXT_CS0_PAGE_SIZE_SHIFT 0
-#define BCHP_NAND_CONFIG_EXT_CS0_PAGE_SIZE_PG_SIZE_512 0
-#define BCHP_NAND_CONFIG_EXT_CS0_PAGE_SIZE_PG_SIZE_1KB 1
-#define BCHP_NAND_CONFIG_EXT_CS0_PAGE_SIZE_PG_SIZE_2KB 2
-#define BCHP_NAND_CONFIG_EXT_CS0_PAGE_SIZE_PG_SIZE_4KB 3
-#define BCHP_NAND_CONFIG_EXT_CS0_PAGE_SIZE_PG_SIZE_8KB 4
-#define BCHP_NAND_CONFIG_EXT_CS0_PAGE_SIZE_PG_SIZE_16KB 5
-
-/***************************************************************************
- *CONFIG_CS0 - Nand Flash Config
- ***************************************************************************/
-/* NAND :: CONFIG_CS0 :: CONFIG_LOCK [31:31] */
-#define BCHP_NAND_CONFIG_CS0_CONFIG_LOCK_MASK 0x80000000
-#define BCHP_NAND_CONFIG_CS0_CONFIG_LOCK_SHIFT 31
-#define BCHP_NAND_CONFIG_CS0_CONFIG_LOCK_DEFAULT 0x00000000
-
-/* NAND :: CONFIG_CS0 :: reserved0 [30:28] */
-#define BCHP_NAND_CONFIG_CS0_reserved0_MASK 0x70000000
-#define BCHP_NAND_CONFIG_CS0_reserved0_SHIFT 28
-
-/* NAND :: CONFIG_CS0 :: DEVICE_SIZE [27:24] */
-#define BCHP_NAND_CONFIG_CS0_DEVICE_SIZE_MASK 0x0f000000
-#define BCHP_NAND_CONFIG_CS0_DEVICE_SIZE_SHIFT 24
-#define BCHP_NAND_CONFIG_CS0_DEVICE_SIZE_DVC_SIZE_4MB 0
-#define BCHP_NAND_CONFIG_CS0_DEVICE_SIZE_DVC_SIZE_8MB 1
-#define BCHP_NAND_CONFIG_CS0_DEVICE_SIZE_DVC_SIZE_16MB 2
-#define BCHP_NAND_CONFIG_CS0_DEVICE_SIZE_DVC_SIZE_32MB 3
-#define BCHP_NAND_CONFIG_CS0_DEVICE_SIZE_DVC_SIZE_64MB 4
-#define BCHP_NAND_CONFIG_CS0_DEVICE_SIZE_DVC_SIZE_128MB 5
-#define BCHP_NAND_CONFIG_CS0_DEVICE_SIZE_DVC_SIZE_256MB 6
-#define BCHP_NAND_CONFIG_CS0_DEVICE_SIZE_DVC_SIZE_512MB 7
-#define BCHP_NAND_CONFIG_CS0_DEVICE_SIZE_DVC_SIZE_1GB 8
-#define BCHP_NAND_CONFIG_CS0_DEVICE_SIZE_DVC_SIZE_2GB 9
-#define BCHP_NAND_CONFIG_CS0_DEVICE_SIZE_DVC_SIZE_4GB 10
-#define BCHP_NAND_CONFIG_CS0_DEVICE_SIZE_DVC_SIZE_8GB 11
-#define BCHP_NAND_CONFIG_CS0_DEVICE_SIZE_DVC_SIZE_16GB 12
-#define BCHP_NAND_CONFIG_CS0_DEVICE_SIZE_DVC_SIZE_32GB 13
-#define BCHP_NAND_CONFIG_CS0_DEVICE_SIZE_DVC_SIZE_64GB 14
-#define BCHP_NAND_CONFIG_CS0_DEVICE_SIZE_DVC_SIZE_128GB 15
-
-/* NAND :: CONFIG_CS0 :: DEVICE_WIDTH [23:23] */
-#define BCHP_NAND_CONFIG_CS0_DEVICE_WIDTH_MASK 0x00800000
-#define BCHP_NAND_CONFIG_CS0_DEVICE_WIDTH_SHIFT 23
-#define BCHP_NAND_CONFIG_CS0_DEVICE_WIDTH_DVC_WIDTH_8 0
-#define BCHP_NAND_CONFIG_CS0_DEVICE_WIDTH_DVC_WIDTH_16 1
-
-/* NAND :: CONFIG_CS0 :: reserved1 [22:19] */
-#define BCHP_NAND_CONFIG_CS0_reserved1_MASK 0x00780000
-#define BCHP_NAND_CONFIG_CS0_reserved1_SHIFT 19
-
-/* NAND :: CONFIG_CS0 :: FUL_ADR_BYTES [18:16] */
-#define BCHP_NAND_CONFIG_CS0_FUL_ADR_BYTES_MASK 0x00070000
-#define BCHP_NAND_CONFIG_CS0_FUL_ADR_BYTES_SHIFT 16
-
-/* NAND :: CONFIG_CS0 :: reserved2 [15:15] */
-#define BCHP_NAND_CONFIG_CS0_reserved2_MASK 0x00008000
-#define BCHP_NAND_CONFIG_CS0_reserved2_SHIFT 15
-
-/* NAND :: CONFIG_CS0 :: COL_ADR_BYTES [14:12] */
-#define BCHP_NAND_CONFIG_CS0_COL_ADR_BYTES_MASK 0x00007000
-#define BCHP_NAND_CONFIG_CS0_COL_ADR_BYTES_SHIFT 12
-
-/* NAND :: CONFIG_CS0 :: reserved3 [11:11] */
-#define BCHP_NAND_CONFIG_CS0_reserved3_MASK 0x00000800
-#define BCHP_NAND_CONFIG_CS0_reserved3_SHIFT 11
-
-/* NAND :: CONFIG_CS0 :: BLK_ADR_BYTES [10:08] */
-#define BCHP_NAND_CONFIG_CS0_BLK_ADR_BYTES_MASK 0x00000700
-#define BCHP_NAND_CONFIG_CS0_BLK_ADR_BYTES_SHIFT 8
-
-/* NAND :: CONFIG_CS0 :: reserved4 [07:00] */
-#define BCHP_NAND_CONFIG_CS0_reserved4_MASK 0x000000ff
-#define BCHP_NAND_CONFIG_CS0_reserved4_SHIFT 0
-
-/***************************************************************************
- *TIMING_1_CS0 - Nand Flash Timing Parameters 1
- ***************************************************************************/
-/* NAND :: TIMING_1_CS0 :: tWP [31:28] */
-#define BCHP_NAND_TIMING_1_CS0_tWP_MASK 0xf0000000
-#define BCHP_NAND_TIMING_1_CS0_tWP_SHIFT 28
-#define BCHP_NAND_TIMING_1_CS0_tWP_DEFAULT 0x00000006
-
-/* NAND :: TIMING_1_CS0 :: tWH [27:24] */
-#define BCHP_NAND_TIMING_1_CS0_tWH_MASK 0x0f000000
-#define BCHP_NAND_TIMING_1_CS0_tWH_SHIFT 24
-#define BCHP_NAND_TIMING_1_CS0_tWH_DEFAULT 0x00000005
-
-/* NAND :: TIMING_1_CS0 :: tRP [23:20] */
-#define BCHP_NAND_TIMING_1_CS0_tRP_MASK 0x00f00000
-#define BCHP_NAND_TIMING_1_CS0_tRP_SHIFT 20
-#define BCHP_NAND_TIMING_1_CS0_tRP_DEFAULT 0x00000007
-
-/* NAND :: TIMING_1_CS0 :: tREH [19:16] */
-#define BCHP_NAND_TIMING_1_CS0_tREH_MASK 0x000f0000
-#define BCHP_NAND_TIMING_1_CS0_tREH_SHIFT 16
-#define BCHP_NAND_TIMING_1_CS0_tREH_DEFAULT 0x00000004
-
-/* NAND :: TIMING_1_CS0 :: tCS [15:12] */
-#define BCHP_NAND_TIMING_1_CS0_tCS_MASK 0x0000f000
-#define BCHP_NAND_TIMING_1_CS0_tCS_SHIFT 12
-#define BCHP_NAND_TIMING_1_CS0_tCS_DEFAULT 0x00000008
-
-/* NAND :: TIMING_1_CS0 :: tCLH [11:08] */
-#define BCHP_NAND_TIMING_1_CS0_tCLH_MASK 0x00000f00
-#define BCHP_NAND_TIMING_1_CS0_tCLH_SHIFT 8
-#define BCHP_NAND_TIMING_1_CS0_tCLH_DEFAULT 0x00000004
-
-/* NAND :: TIMING_1_CS0 :: tALH [07:04] */
-#define BCHP_NAND_TIMING_1_CS0_tALH_MASK 0x000000f0
-#define BCHP_NAND_TIMING_1_CS0_tALH_SHIFT 4
-#define BCHP_NAND_TIMING_1_CS0_tALH_DEFAULT 0x00000005
-
-/* NAND :: TIMING_1_CS0 :: tADL [03:00] */
-#define BCHP_NAND_TIMING_1_CS0_tADL_MASK 0x0000000f
-#define BCHP_NAND_TIMING_1_CS0_tADL_SHIFT 0
-#define BCHP_NAND_TIMING_1_CS0_tADL_DEFAULT 0x0000000b
-
-/***************************************************************************
- *TIMING_2_CS0 - Nand Flash Timing Parameters 2
- ***************************************************************************/
-/* NAND :: TIMING_2_CS0 :: CLK_SELECT [31:31] */
-#define BCHP_NAND_TIMING_2_CS0_CLK_SELECT_MASK 0x80000000
-#define BCHP_NAND_TIMING_2_CS0_CLK_SELECT_SHIFT 31
-#define BCHP_NAND_TIMING_2_CS0_CLK_SELECT_DEFAULT 0x00000000
-#define BCHP_NAND_TIMING_2_CS0_CLK_SELECT_CLK_108 0
-#define BCHP_NAND_TIMING_2_CS0_CLK_SELECT_CLK_216 1
-
-/* NAND :: TIMING_2_CS0 :: reserved0 [30:20] */
-#define BCHP_NAND_TIMING_2_CS0_reserved0_MASK 0x7ff00000
-#define BCHP_NAND_TIMING_2_CS0_reserved0_SHIFT 20
-
-/* NAND :: TIMING_2_CS0 :: tCCS [19:16] */
-#define BCHP_NAND_TIMING_2_CS0_tCCS_MASK 0x000f0000
-#define BCHP_NAND_TIMING_2_CS0_tCCS_SHIFT 16
-#define BCHP_NAND_TIMING_2_CS0_tCCS_DEFAULT 0x00000009
-
-/* NAND :: TIMING_2_CS0 :: reserved1 [15:13] */
-#define BCHP_NAND_TIMING_2_CS0_reserved1_MASK 0x0000e000
-#define BCHP_NAND_TIMING_2_CS0_reserved1_SHIFT 13
-
-/* NAND :: TIMING_2_CS0 :: tWB [12:09] */
-#define BCHP_NAND_TIMING_2_CS0_tWB_MASK 0x00001e00
-#define BCHP_NAND_TIMING_2_CS0_tWB_SHIFT 9
-#define BCHP_NAND_TIMING_2_CS0_tWB_DEFAULT 0x0000000f
-
-/* NAND :: TIMING_2_CS0 :: tWHR [08:04] */
-#define BCHP_NAND_TIMING_2_CS0_tWHR_MASK 0x000001f0
-#define BCHP_NAND_TIMING_2_CS0_tWHR_SHIFT 4
-#define BCHP_NAND_TIMING_2_CS0_tWHR_DEFAULT 0x00000009
-
-/* NAND :: TIMING_2_CS0 :: tREAD [03:00] */
-#define BCHP_NAND_TIMING_2_CS0_tREAD_MASK 0x0000000f
-#define BCHP_NAND_TIMING_2_CS0_tREAD_SHIFT 0
-#define BCHP_NAND_TIMING_2_CS0_tREAD_DEFAULT 0x00000006
-
-/***************************************************************************
- *ACC_CONTROL_CS1 - Nand Flash Access Control
- ***************************************************************************/
-/* NAND :: ACC_CONTROL_CS1 :: RD_ECC_EN [31:31] */
-#define BCHP_NAND_ACC_CONTROL_CS1_RD_ECC_EN_MASK 0x80000000
-#define BCHP_NAND_ACC_CONTROL_CS1_RD_ECC_EN_SHIFT 31
-#define BCHP_NAND_ACC_CONTROL_CS1_RD_ECC_EN_DEFAULT 0x00000001
-
-/* NAND :: ACC_CONTROL_CS1 :: WR_ECC_EN [30:30] */
-#define BCHP_NAND_ACC_CONTROL_CS1_WR_ECC_EN_MASK 0x40000000
-#define BCHP_NAND_ACC_CONTROL_CS1_WR_ECC_EN_SHIFT 30
-#define BCHP_NAND_ACC_CONTROL_CS1_WR_ECC_EN_DEFAULT 0x00000001
-
-/* NAND :: ACC_CONTROL_CS1 :: CE_CARE [29:29] */
-#define BCHP_NAND_ACC_CONTROL_CS1_CE_CARE_MASK 0x20000000
-#define BCHP_NAND_ACC_CONTROL_CS1_CE_CARE_SHIFT 29
-#define BCHP_NAND_ACC_CONTROL_CS1_CE_CARE_DEFAULT 0x00000000
-
-/* NAND :: ACC_CONTROL_CS1 :: reserved0 [28:28] */
-#define BCHP_NAND_ACC_CONTROL_CS1_reserved0_MASK 0x10000000
-#define BCHP_NAND_ACC_CONTROL_CS1_reserved0_SHIFT 28
-
-/* NAND :: ACC_CONTROL_CS1 :: RD_ERASED_ECC_EN [27:27] */
-#define BCHP_NAND_ACC_CONTROL_CS1_RD_ERASED_ECC_EN_MASK 0x08000000
-#define BCHP_NAND_ACC_CONTROL_CS1_RD_ERASED_ECC_EN_SHIFT 27
-#define BCHP_NAND_ACC_CONTROL_CS1_RD_ERASED_ECC_EN_DEFAULT 0x00000000
-
-/* NAND :: ACC_CONTROL_CS1 :: PARTIAL_PAGE_EN [26:26] */
-#define BCHP_NAND_ACC_CONTROL_CS1_PARTIAL_PAGE_EN_MASK 0x04000000
-#define BCHP_NAND_ACC_CONTROL_CS1_PARTIAL_PAGE_EN_SHIFT 26
-#define BCHP_NAND_ACC_CONTROL_CS1_PARTIAL_PAGE_EN_DEFAULT 0x00000000
-
-/* NAND :: ACC_CONTROL_CS1 :: WR_PREEMPT_EN [25:25] */
-#define BCHP_NAND_ACC_CONTROL_CS1_WR_PREEMPT_EN_MASK 0x02000000
-#define BCHP_NAND_ACC_CONTROL_CS1_WR_PREEMPT_EN_SHIFT 25
-#define BCHP_NAND_ACC_CONTROL_CS1_WR_PREEMPT_EN_DEFAULT 0x00000001
-
-/* NAND :: ACC_CONTROL_CS1 :: PAGE_HIT_EN [24:24] */
-#define BCHP_NAND_ACC_CONTROL_CS1_PAGE_HIT_EN_MASK 0x01000000
-#define BCHP_NAND_ACC_CONTROL_CS1_PAGE_HIT_EN_SHIFT 24
-#define BCHP_NAND_ACC_CONTROL_CS1_PAGE_HIT_EN_DEFAULT 0x00000001
-
-/* NAND :: ACC_CONTROL_CS1 :: PREFETCH_EN [23:23] */
-#define BCHP_NAND_ACC_CONTROL_CS1_PREFETCH_EN_MASK 0x00800000
-#define BCHP_NAND_ACC_CONTROL_CS1_PREFETCH_EN_SHIFT 23
-#define BCHP_NAND_ACC_CONTROL_CS1_PREFETCH_EN_DEFAULT 0x00000000
-
-/* NAND :: ACC_CONTROL_CS1 :: CACHE_MODE_EN [22:22] */
-#define BCHP_NAND_ACC_CONTROL_CS1_CACHE_MODE_EN_MASK 0x00400000
-#define BCHP_NAND_ACC_CONTROL_CS1_CACHE_MODE_EN_SHIFT 22
-#define BCHP_NAND_ACC_CONTROL_CS1_CACHE_MODE_EN_DEFAULT 0x00000000
-
-/* NAND :: ACC_CONTROL_CS1 :: reserved1 [21:21] */
-#define BCHP_NAND_ACC_CONTROL_CS1_reserved1_MASK 0x00200000
-#define BCHP_NAND_ACC_CONTROL_CS1_reserved1_SHIFT 21
-
-/* NAND :: ACC_CONTROL_CS1 :: ECC_LEVEL [20:16] */
-#define BCHP_NAND_ACC_CONTROL_CS1_ECC_LEVEL_MASK 0x001f0000
-#define BCHP_NAND_ACC_CONTROL_CS1_ECC_LEVEL_SHIFT 16
-#define BCHP_NAND_ACC_CONTROL_CS1_ECC_LEVEL_DEFAULT 0x0000000f
-
-/* NAND :: ACC_CONTROL_CS1 :: reserved2 [15:08] */
-#define BCHP_NAND_ACC_CONTROL_CS1_reserved2_MASK 0x0000ff00
-#define BCHP_NAND_ACC_CONTROL_CS1_reserved2_SHIFT 8
-
-/* NAND :: ACC_CONTROL_CS1 :: SECTOR_SIZE_1K [07:07] */
-#define BCHP_NAND_ACC_CONTROL_CS1_SECTOR_SIZE_1K_MASK 0x00000080
-#define BCHP_NAND_ACC_CONTROL_CS1_SECTOR_SIZE_1K_SHIFT 7
-#define BCHP_NAND_ACC_CONTROL_CS1_SECTOR_SIZE_1K_DEFAULT 0x00000000
-
-/* NAND :: ACC_CONTROL_CS1 :: SPARE_AREA_SIZE [06:00] */
-#define BCHP_NAND_ACC_CONTROL_CS1_SPARE_AREA_SIZE_MASK 0x0000007f
-#define BCHP_NAND_ACC_CONTROL_CS1_SPARE_AREA_SIZE_SHIFT 0
-#define BCHP_NAND_ACC_CONTROL_CS1_SPARE_AREA_SIZE_DEFAULT 0x00000010
-
-/***************************************************************************
- *CONFIG_EXT_CS1 - Nand Flash Config Extension
- ***************************************************************************/
-/* NAND :: CONFIG_EXT_CS1 :: reserved0 [31:12] */
-#define BCHP_NAND_CONFIG_EXT_CS1_reserved0_MASK 0xfffff000
-#define BCHP_NAND_CONFIG_EXT_CS1_reserved0_SHIFT 12
-
-/* NAND :: CONFIG_EXT_CS1 :: BLOCK_SIZE [11:04] */
-#define BCHP_NAND_CONFIG_EXT_CS1_BLOCK_SIZE_MASK 0x00000ff0
-#define BCHP_NAND_CONFIG_EXT_CS1_BLOCK_SIZE_SHIFT 4
-#define BCHP_NAND_CONFIG_EXT_CS1_BLOCK_SIZE_BK_SIZE_8KB 0
-#define BCHP_NAND_CONFIG_EXT_CS1_BLOCK_SIZE_BK_SIZE_16KB 1
-#define BCHP_NAND_CONFIG_EXT_CS1_BLOCK_SIZE_BK_SIZE_32KB 2
-#define BCHP_NAND_CONFIG_EXT_CS1_BLOCK_SIZE_BK_SIZE_64KB 3
-#define BCHP_NAND_CONFIG_EXT_CS1_BLOCK_SIZE_BK_SIZE_128KB 4
-#define BCHP_NAND_CONFIG_EXT_CS1_BLOCK_SIZE_BK_SIZE_256KB 5
-#define BCHP_NAND_CONFIG_EXT_CS1_BLOCK_SIZE_BK_SIZE_512KB 6
-#define BCHP_NAND_CONFIG_EXT_CS1_BLOCK_SIZE_BK_SIZE_1024KB 7
-#define BCHP_NAND_CONFIG_EXT_CS1_BLOCK_SIZE_BK_SIZE_2048KB 8
-#define BCHP_NAND_CONFIG_EXT_CS1_BLOCK_SIZE_BK_SIZE_4096KB 9
-#define BCHP_NAND_CONFIG_EXT_CS1_BLOCK_SIZE_BK_SIZE_8192KB 10
-
-/* NAND :: CONFIG_EXT_CS1 :: PAGE_SIZE [03:00] */
-#define BCHP_NAND_CONFIG_EXT_CS1_PAGE_SIZE_MASK 0x0000000f
-#define BCHP_NAND_CONFIG_EXT_CS1_PAGE_SIZE_SHIFT 0
-#define BCHP_NAND_CONFIG_EXT_CS1_PAGE_SIZE_PG_SIZE_512 0
-#define BCHP_NAND_CONFIG_EXT_CS1_PAGE_SIZE_PG_SIZE_1KB 1
-#define BCHP_NAND_CONFIG_EXT_CS1_PAGE_SIZE_PG_SIZE_2KB 2
-#define BCHP_NAND_CONFIG_EXT_CS1_PAGE_SIZE_PG_SIZE_4KB 3
-#define BCHP_NAND_CONFIG_EXT_CS1_PAGE_SIZE_PG_SIZE_8KB 4
-#define BCHP_NAND_CONFIG_EXT_CS1_PAGE_SIZE_PG_SIZE_16KB 5
-
-/***************************************************************************
- *CONFIG_CS1 - Nand Flash Config
- ***************************************************************************/
-/* NAND :: CONFIG_CS1 :: CONFIG_LOCK [31:31] */
-#define BCHP_NAND_CONFIG_CS1_CONFIG_LOCK_MASK 0x80000000
-#define BCHP_NAND_CONFIG_CS1_CONFIG_LOCK_SHIFT 31
-#define BCHP_NAND_CONFIG_CS1_CONFIG_LOCK_DEFAULT 0x00000000
-
-/* NAND :: CONFIG_CS1 :: reserved0 [30:28] */
-#define BCHP_NAND_CONFIG_CS1_reserved0_MASK 0x70000000
-#define BCHP_NAND_CONFIG_CS1_reserved0_SHIFT 28
-
-/* NAND :: CONFIG_CS1 :: DEVICE_SIZE [27:24] */
-#define BCHP_NAND_CONFIG_CS1_DEVICE_SIZE_MASK 0x0f000000
-#define BCHP_NAND_CONFIG_CS1_DEVICE_SIZE_SHIFT 24
-#define BCHP_NAND_CONFIG_CS1_DEVICE_SIZE_DVC_SIZE_4MB 0
-#define BCHP_NAND_CONFIG_CS1_DEVICE_SIZE_DVC_SIZE_8MB 1
-#define BCHP_NAND_CONFIG_CS1_DEVICE_SIZE_DVC_SIZE_16MB 2
-#define BCHP_NAND_CONFIG_CS1_DEVICE_SIZE_DVC_SIZE_32MB 3
-#define BCHP_NAND_CONFIG_CS1_DEVICE_SIZE_DVC_SIZE_64MB 4
-#define BCHP_NAND_CONFIG_CS1_DEVICE_SIZE_DVC_SIZE_128MB 5
-#define BCHP_NAND_CONFIG_CS1_DEVICE_SIZE_DVC_SIZE_256MB 6
-#define BCHP_NAND_CONFIG_CS1_DEVICE_SIZE_DVC_SIZE_512MB 7
-#define BCHP_NAND_CONFIG_CS1_DEVICE_SIZE_DVC_SIZE_1GB 8
-#define BCHP_NAND_CONFIG_CS1_DEVICE_SIZE_DVC_SIZE_2GB 9
-#define BCHP_NAND_CONFIG_CS1_DEVICE_SIZE_DVC_SIZE_4GB 10
-#define BCHP_NAND_CONFIG_CS1_DEVICE_SIZE_DVC_SIZE_8GB 11
-#define BCHP_NAND_CONFIG_CS1_DEVICE_SIZE_DVC_SIZE_16GB 12
-#define BCHP_NAND_CONFIG_CS1_DEVICE_SIZE_DVC_SIZE_32GB 13
-#define BCHP_NAND_CONFIG_CS1_DEVICE_SIZE_DVC_SIZE_64GB 14
-#define BCHP_NAND_CONFIG_CS1_DEVICE_SIZE_DVC_SIZE_128GB 15
-
-/* NAND :: CONFIG_CS1 :: DEVICE_WIDTH [23:23] */
-#define BCHP_NAND_CONFIG_CS1_DEVICE_WIDTH_MASK 0x00800000
-#define BCHP_NAND_CONFIG_CS1_DEVICE_WIDTH_SHIFT 23
-#define BCHP_NAND_CONFIG_CS1_DEVICE_WIDTH_DVC_WIDTH_8 0
-#define BCHP_NAND_CONFIG_CS1_DEVICE_WIDTH_DVC_WIDTH_16 1
-
-/* NAND :: CONFIG_CS1 :: reserved1 [22:19] */
-#define BCHP_NAND_CONFIG_CS1_reserved1_MASK 0x00780000
-#define BCHP_NAND_CONFIG_CS1_reserved1_SHIFT 19
-
-/* NAND :: CONFIG_CS1 :: FUL_ADR_BYTES [18:16] */
-#define BCHP_NAND_CONFIG_CS1_FUL_ADR_BYTES_MASK 0x00070000
-#define BCHP_NAND_CONFIG_CS1_FUL_ADR_BYTES_SHIFT 16
-
-/* NAND :: CONFIG_CS1 :: reserved2 [15:15] */
-#define BCHP_NAND_CONFIG_CS1_reserved2_MASK 0x00008000
-#define BCHP_NAND_CONFIG_CS1_reserved2_SHIFT 15
-
-/* NAND :: CONFIG_CS1 :: COL_ADR_BYTES [14:12] */
-#define BCHP_NAND_CONFIG_CS1_COL_ADR_BYTES_MASK 0x00007000
-#define BCHP_NAND_CONFIG_CS1_COL_ADR_BYTES_SHIFT 12
-
-/* NAND :: CONFIG_CS1 :: reserved3 [11:11] */
-#define BCHP_NAND_CONFIG_CS1_reserved3_MASK 0x00000800
-#define BCHP_NAND_CONFIG_CS1_reserved3_SHIFT 11
-
-/* NAND :: CONFIG_CS1 :: BLK_ADR_BYTES [10:08] */
-#define BCHP_NAND_CONFIG_CS1_BLK_ADR_BYTES_MASK 0x00000700
-#define BCHP_NAND_CONFIG_CS1_BLK_ADR_BYTES_SHIFT 8
-
-/* NAND :: CONFIG_CS1 :: reserved4 [07:00] */
-#define BCHP_NAND_CONFIG_CS1_reserved4_MASK 0x000000ff
-#define BCHP_NAND_CONFIG_CS1_reserved4_SHIFT 0
-
-/***************************************************************************
- *TIMING_1_CS1 - Nand Flash Timing Parameters 1
- ***************************************************************************/
-/* NAND :: TIMING_1_CS1 :: tWP [31:28] */
-#define BCHP_NAND_TIMING_1_CS1_tWP_MASK 0xf0000000
-#define BCHP_NAND_TIMING_1_CS1_tWP_SHIFT 28
-#define BCHP_NAND_TIMING_1_CS1_tWP_DEFAULT 0x00000006
-
-/* NAND :: TIMING_1_CS1 :: tWH [27:24] */
-#define BCHP_NAND_TIMING_1_CS1_tWH_MASK 0x0f000000
-#define BCHP_NAND_TIMING_1_CS1_tWH_SHIFT 24
-#define BCHP_NAND_TIMING_1_CS1_tWH_DEFAULT 0x00000005
-
-/* NAND :: TIMING_1_CS1 :: tRP [23:20] */
-#define BCHP_NAND_TIMING_1_CS1_tRP_MASK 0x00f00000
-#define BCHP_NAND_TIMING_1_CS1_tRP_SHIFT 20
-#define BCHP_NAND_TIMING_1_CS1_tRP_DEFAULT 0x00000007
-
-/* NAND :: TIMING_1_CS1 :: tREH [19:16] */
-#define BCHP_NAND_TIMING_1_CS1_tREH_MASK 0x000f0000
-#define BCHP_NAND_TIMING_1_CS1_tREH_SHIFT 16
-#define BCHP_NAND_TIMING_1_CS1_tREH_DEFAULT 0x00000004
-
-/* NAND :: TIMING_1_CS1 :: tCS [15:12] */
-#define BCHP_NAND_TIMING_1_CS1_tCS_MASK 0x0000f000
-#define BCHP_NAND_TIMING_1_CS1_tCS_SHIFT 12
-#define BCHP_NAND_TIMING_1_CS1_tCS_DEFAULT 0x00000008
-
-/* NAND :: TIMING_1_CS1 :: tCLH [11:08] */
-#define BCHP_NAND_TIMING_1_CS1_tCLH_MASK 0x00000f00
-#define BCHP_NAND_TIMING_1_CS1_tCLH_SHIFT 8
-#define BCHP_NAND_TIMING_1_CS1_tCLH_DEFAULT 0x00000004
-
-/* NAND :: TIMING_1_CS1 :: tALH [07:04] */
-#define BCHP_NAND_TIMING_1_CS1_tALH_MASK 0x000000f0
-#define BCHP_NAND_TIMING_1_CS1_tALH_SHIFT 4
-#define BCHP_NAND_TIMING_1_CS1_tALH_DEFAULT 0x00000005
-
-/* NAND :: TIMING_1_CS1 :: tADL [03:00] */
-#define BCHP_NAND_TIMING_1_CS1_tADL_MASK 0x0000000f
-#define BCHP_NAND_TIMING_1_CS1_tADL_SHIFT 0
-#define BCHP_NAND_TIMING_1_CS1_tADL_DEFAULT 0x0000000b
-
-/***************************************************************************
- *TIMING_2_CS1 - Nand Flash Timing Parameters 2
- ***************************************************************************/
-/* NAND :: TIMING_2_CS1 :: CLK_SELECT [31:31] */
-#define BCHP_NAND_TIMING_2_CS1_CLK_SELECT_MASK 0x80000000
-#define BCHP_NAND_TIMING_2_CS1_CLK_SELECT_SHIFT 31
-#define BCHP_NAND_TIMING_2_CS1_CLK_SELECT_DEFAULT 0x00000000
-#define BCHP_NAND_TIMING_2_CS1_CLK_SELECT_CLK_108 0
-#define BCHP_NAND_TIMING_2_CS1_CLK_SELECT_CLK_216 1
-
-/* NAND :: TIMING_2_CS1 :: reserved0 [30:20] */
-#define BCHP_NAND_TIMING_2_CS1_reserved0_MASK 0x7ff00000
-#define BCHP_NAND_TIMING_2_CS1_reserved0_SHIFT 20
-
-/* NAND :: TIMING_2_CS1 :: tCCS [19:16] */
-#define BCHP_NAND_TIMING_2_CS1_tCCS_MASK 0x000f0000
-#define BCHP_NAND_TIMING_2_CS1_tCCS_SHIFT 16
-#define BCHP_NAND_TIMING_2_CS1_tCCS_DEFAULT 0x00000009
-
-/* NAND :: TIMING_2_CS1 :: reserved1 [15:13] */
-#define BCHP_NAND_TIMING_2_CS1_reserved1_MASK 0x0000e000
-#define BCHP_NAND_TIMING_2_CS1_reserved1_SHIFT 13
-
-/* NAND :: TIMING_2_CS1 :: tWB [12:09] */
-#define BCHP_NAND_TIMING_2_CS1_tWB_MASK 0x00001e00
-#define BCHP_NAND_TIMING_2_CS1_tWB_SHIFT 9
-#define BCHP_NAND_TIMING_2_CS1_tWB_DEFAULT 0x0000000f
-
-/* NAND :: TIMING_2_CS1 :: tWHR [08:04] */
-#define BCHP_NAND_TIMING_2_CS1_tWHR_MASK 0x000001f0
-#define BCHP_NAND_TIMING_2_CS1_tWHR_SHIFT 4
-#define BCHP_NAND_TIMING_2_CS1_tWHR_DEFAULT 0x00000009
-
-/* NAND :: TIMING_2_CS1 :: tREAD [03:00] */
-#define BCHP_NAND_TIMING_2_CS1_tREAD_MASK 0x0000000f
-#define BCHP_NAND_TIMING_2_CS1_tREAD_SHIFT 0
-#define BCHP_NAND_TIMING_2_CS1_tREAD_DEFAULT 0x00000006
-
-/***************************************************************************
- *ACC_CONTROL_CS2 - Nand Flash Access Control
- ***************************************************************************/
-/* NAND :: ACC_CONTROL_CS2 :: RD_ECC_EN [31:31] */
-#define BCHP_NAND_ACC_CONTROL_CS2_RD_ECC_EN_MASK 0x80000000
-#define BCHP_NAND_ACC_CONTROL_CS2_RD_ECC_EN_SHIFT 31
-#define BCHP_NAND_ACC_CONTROL_CS2_RD_ECC_EN_DEFAULT 0x00000001
-
-/* NAND :: ACC_CONTROL_CS2 :: WR_ECC_EN [30:30] */
-#define BCHP_NAND_ACC_CONTROL_CS2_WR_ECC_EN_MASK 0x40000000
-#define BCHP_NAND_ACC_CONTROL_CS2_WR_ECC_EN_SHIFT 30
-#define BCHP_NAND_ACC_CONTROL_CS2_WR_ECC_EN_DEFAULT 0x00000001
-
-/* NAND :: ACC_CONTROL_CS2 :: CE_CARE [29:29] */
-#define BCHP_NAND_ACC_CONTROL_CS2_CE_CARE_MASK 0x20000000
-#define BCHP_NAND_ACC_CONTROL_CS2_CE_CARE_SHIFT 29
-#define BCHP_NAND_ACC_CONTROL_CS2_CE_CARE_DEFAULT 0x00000000
-
-/* NAND :: ACC_CONTROL_CS2 :: reserved0 [28:28] */
-#define BCHP_NAND_ACC_CONTROL_CS2_reserved0_MASK 0x10000000
-#define BCHP_NAND_ACC_CONTROL_CS2_reserved0_SHIFT 28
-
-/* NAND :: ACC_CONTROL_CS2 :: RD_ERASED_ECC_EN [27:27] */
-#define BCHP_NAND_ACC_CONTROL_CS2_RD_ERASED_ECC_EN_MASK 0x08000000
-#define BCHP_NAND_ACC_CONTROL_CS2_RD_ERASED_ECC_EN_SHIFT 27
-#define BCHP_NAND_ACC_CONTROL_CS2_RD_ERASED_ECC_EN_DEFAULT 0x00000000
-
-/* NAND :: ACC_CONTROL_CS2 :: PARTIAL_PAGE_EN [26:26] */
-#define BCHP_NAND_ACC_CONTROL_CS2_PARTIAL_PAGE_EN_MASK 0x04000000
-#define BCHP_NAND_ACC_CONTROL_CS2_PARTIAL_PAGE_EN_SHIFT 26
-#define BCHP_NAND_ACC_CONTROL_CS2_PARTIAL_PAGE_EN_DEFAULT 0x00000000
-
-/* NAND :: ACC_CONTROL_CS2 :: WR_PREEMPT_EN [25:25] */
-#define BCHP_NAND_ACC_CONTROL_CS2_WR_PREEMPT_EN_MASK 0x02000000
-#define BCHP_NAND_ACC_CONTROL_CS2_WR_PREEMPT_EN_SHIFT 25
-#define BCHP_NAND_ACC_CONTROL_CS2_WR_PREEMPT_EN_DEFAULT 0x00000001
-
-/* NAND :: ACC_CONTROL_CS2 :: PAGE_HIT_EN [24:24] */
-#define BCHP_NAND_ACC_CONTROL_CS2_PAGE_HIT_EN_MASK 0x01000000
-#define BCHP_NAND_ACC_CONTROL_CS2_PAGE_HIT_EN_SHIFT 24
-#define BCHP_NAND_ACC_CONTROL_CS2_PAGE_HIT_EN_DEFAULT 0x00000001
-
-/* NAND :: ACC_CONTROL_CS2 :: PREFETCH_EN [23:23] */
-#define BCHP_NAND_ACC_CONTROL_CS2_PREFETCH_EN_MASK 0x00800000
-#define BCHP_NAND_ACC_CONTROL_CS2_PREFETCH_EN_SHIFT 23
-#define BCHP_NAND_ACC_CONTROL_CS2_PREFETCH_EN_DEFAULT 0x00000000
-
-/* NAND :: ACC_CONTROL_CS2 :: CACHE_MODE_EN [22:22] */
-#define BCHP_NAND_ACC_CONTROL_CS2_CACHE_MODE_EN_MASK 0x00400000
-#define BCHP_NAND_ACC_CONTROL_CS2_CACHE_MODE_EN_SHIFT 22
-#define BCHP_NAND_ACC_CONTROL_CS2_CACHE_MODE_EN_DEFAULT 0x00000000
-
-/* NAND :: ACC_CONTROL_CS2 :: reserved1 [21:21] */
-#define BCHP_NAND_ACC_CONTROL_CS2_reserved1_MASK 0x00200000
-#define BCHP_NAND_ACC_CONTROL_CS2_reserved1_SHIFT 21
-
-/* NAND :: ACC_CONTROL_CS2 :: ECC_LEVEL [20:16] */
-#define BCHP_NAND_ACC_CONTROL_CS2_ECC_LEVEL_MASK 0x001f0000
-#define BCHP_NAND_ACC_CONTROL_CS2_ECC_LEVEL_SHIFT 16
-#define BCHP_NAND_ACC_CONTROL_CS2_ECC_LEVEL_DEFAULT 0x0000000f
-
-/* NAND :: ACC_CONTROL_CS2 :: reserved2 [15:08] */
-#define BCHP_NAND_ACC_CONTROL_CS2_reserved2_MASK 0x0000ff00
-#define BCHP_NAND_ACC_CONTROL_CS2_reserved2_SHIFT 8
-
-/* NAND :: ACC_CONTROL_CS2 :: SECTOR_SIZE_1K [07:07] */
-#define BCHP_NAND_ACC_CONTROL_CS2_SECTOR_SIZE_1K_MASK 0x00000080
-#define BCHP_NAND_ACC_CONTROL_CS2_SECTOR_SIZE_1K_SHIFT 7
-#define BCHP_NAND_ACC_CONTROL_CS2_SECTOR_SIZE_1K_DEFAULT 0x00000000
-
-/* NAND :: ACC_CONTROL_CS2 :: SPARE_AREA_SIZE [06:00] */
-#define BCHP_NAND_ACC_CONTROL_CS2_SPARE_AREA_SIZE_MASK 0x0000007f
-#define BCHP_NAND_ACC_CONTROL_CS2_SPARE_AREA_SIZE_SHIFT 0
-#define BCHP_NAND_ACC_CONTROL_CS2_SPARE_AREA_SIZE_DEFAULT 0x00000010
-
-/***************************************************************************
- *CONFIG_EXT_CS2 - Nand Flash Config Extension
- ***************************************************************************/
-/* NAND :: CONFIG_EXT_CS2 :: reserved0 [31:12] */
-#define BCHP_NAND_CONFIG_EXT_CS2_reserved0_MASK 0xfffff000
-#define BCHP_NAND_CONFIG_EXT_CS2_reserved0_SHIFT 12
-
-/* NAND :: CONFIG_EXT_CS2 :: BLOCK_SIZE [11:04] */
-#define BCHP_NAND_CONFIG_EXT_CS2_BLOCK_SIZE_MASK 0x00000ff0
-#define BCHP_NAND_CONFIG_EXT_CS2_BLOCK_SIZE_SHIFT 4
-#define BCHP_NAND_CONFIG_EXT_CS2_BLOCK_SIZE_BK_SIZE_8KB 0
-#define BCHP_NAND_CONFIG_EXT_CS2_BLOCK_SIZE_BK_SIZE_16KB 1
-#define BCHP_NAND_CONFIG_EXT_CS2_BLOCK_SIZE_BK_SIZE_32KB 2
-#define BCHP_NAND_CONFIG_EXT_CS2_BLOCK_SIZE_BK_SIZE_64KB 3
-#define BCHP_NAND_CONFIG_EXT_CS2_BLOCK_SIZE_BK_SIZE_128KB 4
-#define BCHP_NAND_CONFIG_EXT_CS2_BLOCK_SIZE_BK_SIZE_256KB 5
-#define BCHP_NAND_CONFIG_EXT_CS2_BLOCK_SIZE_BK_SIZE_512KB 6
-#define BCHP_NAND_CONFIG_EXT_CS2_BLOCK_SIZE_BK_SIZE_1024KB 7
-#define BCHP_NAND_CONFIG_EXT_CS2_BLOCK_SIZE_BK_SIZE_2048KB 8
-#define BCHP_NAND_CONFIG_EXT_CS2_BLOCK_SIZE_BK_SIZE_4096KB 9
-#define BCHP_NAND_CONFIG_EXT_CS2_BLOCK_SIZE_BK_SIZE_8192KB 10
-
-/* NAND :: CONFIG_EXT_CS2 :: PAGE_SIZE [03:00] */
-#define BCHP_NAND_CONFIG_EXT_CS2_PAGE_SIZE_MASK 0x0000000f
-#define BCHP_NAND_CONFIG_EXT_CS2_PAGE_SIZE_SHIFT 0
-#define BCHP_NAND_CONFIG_EXT_CS2_PAGE_SIZE_PG_SIZE_512 0
-#define BCHP_NAND_CONFIG_EXT_CS2_PAGE_SIZE_PG_SIZE_1KB 1
-#define BCHP_NAND_CONFIG_EXT_CS2_PAGE_SIZE_PG_SIZE_2KB 2
-#define BCHP_NAND_CONFIG_EXT_CS2_PAGE_SIZE_PG_SIZE_4KB 3
-#define BCHP_NAND_CONFIG_EXT_CS2_PAGE_SIZE_PG_SIZE_8KB 4
-#define BCHP_NAND_CONFIG_EXT_CS2_PAGE_SIZE_PG_SIZE_16KB 5
-
-/***************************************************************************
- *CONFIG_CS2 - Nand Flash Config
- ***************************************************************************/
-/* NAND :: CONFIG_CS2 :: CONFIG_LOCK [31:31] */
-#define BCHP_NAND_CONFIG_CS2_CONFIG_LOCK_MASK 0x80000000
-#define BCHP_NAND_CONFIG_CS2_CONFIG_LOCK_SHIFT 31
-#define BCHP_NAND_CONFIG_CS2_CONFIG_LOCK_DEFAULT 0x00000000
-
-/* NAND :: CONFIG_CS2 :: reserved0 [30:28] */
-#define BCHP_NAND_CONFIG_CS2_reserved0_MASK 0x70000000
-#define BCHP_NAND_CONFIG_CS2_reserved0_SHIFT 28
-
-/* NAND :: CONFIG_CS2 :: DEVICE_SIZE [27:24] */
-#define BCHP_NAND_CONFIG_CS2_DEVICE_SIZE_MASK 0x0f000000
-#define BCHP_NAND_CONFIG_CS2_DEVICE_SIZE_SHIFT 24
-#define BCHP_NAND_CONFIG_CS2_DEVICE_SIZE_DVC_SIZE_4MB 0
-#define BCHP_NAND_CONFIG_CS2_DEVICE_SIZE_DVC_SIZE_8MB 1
-#define BCHP_NAND_CONFIG_CS2_DEVICE_SIZE_DVC_SIZE_16MB 2
-#define BCHP_NAND_CONFIG_CS2_DEVICE_SIZE_DVC_SIZE_32MB 3
-#define BCHP_NAND_CONFIG_CS2_DEVICE_SIZE_DVC_SIZE_64MB 4
-#define BCHP_NAND_CONFIG_CS2_DEVICE_SIZE_DVC_SIZE_128MB 5
-#define BCHP_NAND_CONFIG_CS2_DEVICE_SIZE_DVC_SIZE_256MB 6
-#define BCHP_NAND_CONFIG_CS2_DEVICE_SIZE_DVC_SIZE_512MB 7
-#define BCHP_NAND_CONFIG_CS2_DEVICE_SIZE_DVC_SIZE_1GB 8
-#define BCHP_NAND_CONFIG_CS2_DEVICE_SIZE_DVC_SIZE_2GB 9
-#define BCHP_NAND_CONFIG_CS2_DEVICE_SIZE_DVC_SIZE_4GB 10
-#define BCHP_NAND_CONFIG_CS2_DEVICE_SIZE_DVC_SIZE_8GB 11
-#define BCHP_NAND_CONFIG_CS2_DEVICE_SIZE_DVC_SIZE_16GB 12
-#define BCHP_NAND_CONFIG_CS2_DEVICE_SIZE_DVC_SIZE_32GB 13
-#define BCHP_NAND_CONFIG_CS2_DEVICE_SIZE_DVC_SIZE_64GB 14
-#define BCHP_NAND_CONFIG_CS2_DEVICE_SIZE_DVC_SIZE_128GB 15
-
-/* NAND :: CONFIG_CS2 :: DEVICE_WIDTH [23:23] */
-#define BCHP_NAND_CONFIG_CS2_DEVICE_WIDTH_MASK 0x00800000
-#define BCHP_NAND_CONFIG_CS2_DEVICE_WIDTH_SHIFT 23
-#define BCHP_NAND_CONFIG_CS2_DEVICE_WIDTH_DVC_WIDTH_8 0
-#define BCHP_NAND_CONFIG_CS2_DEVICE_WIDTH_DVC_WIDTH_16 1
-
-/* NAND :: CONFIG_CS2 :: reserved1 [22:19] */
-#define BCHP_NAND_CONFIG_CS2_reserved1_MASK 0x00780000
-#define BCHP_NAND_CONFIG_CS2_reserved1_SHIFT 19
-
-/* NAND :: CONFIG_CS2 :: FUL_ADR_BYTES [18:16] */
-#define BCHP_NAND_CONFIG_CS2_FUL_ADR_BYTES_MASK 0x00070000
-#define BCHP_NAND_CONFIG_CS2_FUL_ADR_BYTES_SHIFT 16
-
-/* NAND :: CONFIG_CS2 :: reserved2 [15:15] */
-#define BCHP_NAND_CONFIG_CS2_reserved2_MASK 0x00008000
-#define BCHP_NAND_CONFIG_CS2_reserved2_SHIFT 15
-
-/* NAND :: CONFIG_CS2 :: COL_ADR_BYTES [14:12] */
-#define BCHP_NAND_CONFIG_CS2_COL_ADR_BYTES_MASK 0x00007000
-#define BCHP_NAND_CONFIG_CS2_COL_ADR_BYTES_SHIFT 12
-
-/* NAND :: CONFIG_CS2 :: reserved3 [11:11] */
-#define BCHP_NAND_CONFIG_CS2_reserved3_MASK 0x00000800
-#define BCHP_NAND_CONFIG_CS2_reserved3_SHIFT 11
-
-/* NAND :: CONFIG_CS2 :: BLK_ADR_BYTES [10:08] */
-#define BCHP_NAND_CONFIG_CS2_BLK_ADR_BYTES_MASK 0x00000700
-#define BCHP_NAND_CONFIG_CS2_BLK_ADR_BYTES_SHIFT 8
-
-/* NAND :: CONFIG_CS2 :: reserved4 [07:00] */
-#define BCHP_NAND_CONFIG_CS2_reserved4_MASK 0x000000ff
-#define BCHP_NAND_CONFIG_CS2_reserved4_SHIFT 0
-
-/***************************************************************************
- *TIMING_1_CS2 - Nand Flash Timing Parameters 1
- ***************************************************************************/
-/* NAND :: TIMING_1_CS2 :: tWP [31:28] */
-#define BCHP_NAND_TIMING_1_CS2_tWP_MASK 0xf0000000
-#define BCHP_NAND_TIMING_1_CS2_tWP_SHIFT 28
-#define BCHP_NAND_TIMING_1_CS2_tWP_DEFAULT 0x00000006
-
-/* NAND :: TIMING_1_CS2 :: tWH [27:24] */
-#define BCHP_NAND_TIMING_1_CS2_tWH_MASK 0x0f000000
-#define BCHP_NAND_TIMING_1_CS2_tWH_SHIFT 24
-#define BCHP_NAND_TIMING_1_CS2_tWH_DEFAULT 0x00000005
-
-/* NAND :: TIMING_1_CS2 :: tRP [23:20] */
-#define BCHP_NAND_TIMING_1_CS2_tRP_MASK 0x00f00000
-#define BCHP_NAND_TIMING_1_CS2_tRP_SHIFT 20
-#define BCHP_NAND_TIMING_1_CS2_tRP_DEFAULT 0x00000007
-
-/* NAND :: TIMING_1_CS2 :: tREH [19:16] */
-#define BCHP_NAND_TIMING_1_CS2_tREH_MASK 0x000f0000
-#define BCHP_NAND_TIMING_1_CS2_tREH_SHIFT 16
-#define BCHP_NAND_TIMING_1_CS2_tREH_DEFAULT 0x00000004
-
-/* NAND :: TIMING_1_CS2 :: tCS [15:12] */
-#define BCHP_NAND_TIMING_1_CS2_tCS_MASK 0x0000f000
-#define BCHP_NAND_TIMING_1_CS2_tCS_SHIFT 12
-#define BCHP_NAND_TIMING_1_CS2_tCS_DEFAULT 0x00000008
-
-/* NAND :: TIMING_1_CS2 :: tCLH [11:08] */
-#define BCHP_NAND_TIMING_1_CS2_tCLH_MASK 0x00000f00
-#define BCHP_NAND_TIMING_1_CS2_tCLH_SHIFT 8
-#define BCHP_NAND_TIMING_1_CS2_tCLH_DEFAULT 0x00000004
-
-/* NAND :: TIMING_1_CS2 :: tALH [07:04] */
-#define BCHP_NAND_TIMING_1_CS2_tALH_MASK 0x000000f0
-#define BCHP_NAND_TIMING_1_CS2_tALH_SHIFT 4
-#define BCHP_NAND_TIMING_1_CS2_tALH_DEFAULT 0x00000005
-
-/* NAND :: TIMING_1_CS2 :: tADL [03:00] */
-#define BCHP_NAND_TIMING_1_CS2_tADL_MASK 0x0000000f
-#define BCHP_NAND_TIMING_1_CS2_tADL_SHIFT 0
-#define BCHP_NAND_TIMING_1_CS2_tADL_DEFAULT 0x0000000b
-
-/***************************************************************************
- *TIMING_2_CS2 - Nand Flash Timing Parameters 2
- ***************************************************************************/
-/* NAND :: TIMING_2_CS2 :: CLK_SELECT [31:31] */
-#define BCHP_NAND_TIMING_2_CS2_CLK_SELECT_MASK 0x80000000
-#define BCHP_NAND_TIMING_2_CS2_CLK_SELECT_SHIFT 31
-#define BCHP_NAND_TIMING_2_CS2_CLK_SELECT_DEFAULT 0x00000000
-#define BCHP_NAND_TIMING_2_CS2_CLK_SELECT_CLK_108 0
-#define BCHP_NAND_TIMING_2_CS2_CLK_SELECT_CLK_216 1
-
-/* NAND :: TIMING_2_CS2 :: reserved0 [30:20] */
-#define BCHP_NAND_TIMING_2_CS2_reserved0_MASK 0x7ff00000
-#define BCHP_NAND_TIMING_2_CS2_reserved0_SHIFT 20
-
-/* NAND :: TIMING_2_CS2 :: tCCS [19:16] */
-#define BCHP_NAND_TIMING_2_CS2_tCCS_MASK 0x000f0000
-#define BCHP_NAND_TIMING_2_CS2_tCCS_SHIFT 16
-#define BCHP_NAND_TIMING_2_CS2_tCCS_DEFAULT 0x00000009
-
-/* NAND :: TIMING_2_CS2 :: reserved1 [15:13] */
-#define BCHP_NAND_TIMING_2_CS2_reserved1_MASK 0x0000e000
-#define BCHP_NAND_TIMING_2_CS2_reserved1_SHIFT 13
-
-/* NAND :: TIMING_2_CS2 :: tWB [12:09] */
-#define BCHP_NAND_TIMING_2_CS2_tWB_MASK 0x00001e00
-#define BCHP_NAND_TIMING_2_CS2_tWB_SHIFT 9
-#define BCHP_NAND_TIMING_2_CS2_tWB_DEFAULT 0x0000000f
-
-/* NAND :: TIMING_2_CS2 :: tWHR [08:04] */
-#define BCHP_NAND_TIMING_2_CS2_tWHR_MASK 0x000001f0
-#define BCHP_NAND_TIMING_2_CS2_tWHR_SHIFT 4
-#define BCHP_NAND_TIMING_2_CS2_tWHR_DEFAULT 0x00000009
-
-/* NAND :: TIMING_2_CS2 :: tREAD [03:00] */
-#define BCHP_NAND_TIMING_2_CS2_tREAD_MASK 0x0000000f
-#define BCHP_NAND_TIMING_2_CS2_tREAD_SHIFT 0
-#define BCHP_NAND_TIMING_2_CS2_tREAD_DEFAULT 0x00000006
-
-/***************************************************************************
- *ACC_CONTROL_CS3 - Nand Flash Access Control
- ***************************************************************************/
-/* NAND :: ACC_CONTROL_CS3 :: RD_ECC_EN [31:31] */
-#define BCHP_NAND_ACC_CONTROL_CS3_RD_ECC_EN_MASK 0x80000000
-#define BCHP_NAND_ACC_CONTROL_CS3_RD_ECC_EN_SHIFT 31
-#define BCHP_NAND_ACC_CONTROL_CS3_RD_ECC_EN_DEFAULT 0x00000001
-
-/* NAND :: ACC_CONTROL_CS3 :: WR_ECC_EN [30:30] */
-#define BCHP_NAND_ACC_CONTROL_CS3_WR_ECC_EN_MASK 0x40000000
-#define BCHP_NAND_ACC_CONTROL_CS3_WR_ECC_EN_SHIFT 30
-#define BCHP_NAND_ACC_CONTROL_CS3_WR_ECC_EN_DEFAULT 0x00000001
-
-/* NAND :: ACC_CONTROL_CS3 :: CE_CARE [29:29] */
-#define BCHP_NAND_ACC_CONTROL_CS3_CE_CARE_MASK 0x20000000
-#define BCHP_NAND_ACC_CONTROL_CS3_CE_CARE_SHIFT 29
-#define BCHP_NAND_ACC_CONTROL_CS3_CE_CARE_DEFAULT 0x00000000
-
-/* NAND :: ACC_CONTROL_CS3 :: reserved0 [28:28] */
-#define BCHP_NAND_ACC_CONTROL_CS3_reserved0_MASK 0x10000000
-#define BCHP_NAND_ACC_CONTROL_CS3_reserved0_SHIFT 28
-
-/* NAND :: ACC_CONTROL_CS3 :: RD_ERASED_ECC_EN [27:27] */
-#define BCHP_NAND_ACC_CONTROL_CS3_RD_ERASED_ECC_EN_MASK 0x08000000
-#define BCHP_NAND_ACC_CONTROL_CS3_RD_ERASED_ECC_EN_SHIFT 27
-#define BCHP_NAND_ACC_CONTROL_CS3_RD_ERASED_ECC_EN_DEFAULT 0x00000000
-
-/* NAND :: ACC_CONTROL_CS3 :: PARTIAL_PAGE_EN [26:26] */
-#define BCHP_NAND_ACC_CONTROL_CS3_PARTIAL_PAGE_EN_MASK 0x04000000
-#define BCHP_NAND_ACC_CONTROL_CS3_PARTIAL_PAGE_EN_SHIFT 26
-#define BCHP_NAND_ACC_CONTROL_CS3_PARTIAL_PAGE_EN_DEFAULT 0x00000000
-
-/* NAND :: ACC_CONTROL_CS3 :: WR_PREEMPT_EN [25:25] */
-#define BCHP_NAND_ACC_CONTROL_CS3_WR_PREEMPT_EN_MASK 0x02000000
-#define BCHP_NAND_ACC_CONTROL_CS3_WR_PREEMPT_EN_SHIFT 25
-#define BCHP_NAND_ACC_CONTROL_CS3_WR_PREEMPT_EN_DEFAULT 0x00000001
-
-/* NAND :: ACC_CONTROL_CS3 :: PAGE_HIT_EN [24:24] */
-#define BCHP_NAND_ACC_CONTROL_CS3_PAGE_HIT_EN_MASK 0x01000000
-#define BCHP_NAND_ACC_CONTROL_CS3_PAGE_HIT_EN_SHIFT 24
-#define BCHP_NAND_ACC_CONTROL_CS3_PAGE_HIT_EN_DEFAULT 0x00000001
-
-/* NAND :: ACC_CONTROL_CS3 :: PREFETCH_EN [23:23] */
-#define BCHP_NAND_ACC_CONTROL_CS3_PREFETCH_EN_MASK 0x00800000
-#define BCHP_NAND_ACC_CONTROL_CS3_PREFETCH_EN_SHIFT 23
-#define BCHP_NAND_ACC_CONTROL_CS3_PREFETCH_EN_DEFAULT 0x00000000
-
-/* NAND :: ACC_CONTROL_CS3 :: CACHE_MODE_EN [22:22] */
-#define BCHP_NAND_ACC_CONTROL_CS3_CACHE_MODE_EN_MASK 0x00400000
-#define BCHP_NAND_ACC_CONTROL_CS3_CACHE_MODE_EN_SHIFT 22
-#define BCHP_NAND_ACC_CONTROL_CS3_CACHE_MODE_EN_DEFAULT 0x00000000
-
-/* NAND :: ACC_CONTROL_CS3 :: reserved1 [21:21] */
-#define BCHP_NAND_ACC_CONTROL_CS3_reserved1_MASK 0x00200000
-#define BCHP_NAND_ACC_CONTROL_CS3_reserved1_SHIFT 21
-
-/* NAND :: ACC_CONTROL_CS3 :: ECC_LEVEL [20:16] */
-#define BCHP_NAND_ACC_CONTROL_CS3_ECC_LEVEL_MASK 0x001f0000
-#define BCHP_NAND_ACC_CONTROL_CS3_ECC_LEVEL_SHIFT 16
-#define BCHP_NAND_ACC_CONTROL_CS3_ECC_LEVEL_DEFAULT 0x0000000f
-
-/* NAND :: ACC_CONTROL_CS3 :: reserved2 [15:08] */
-#define BCHP_NAND_ACC_CONTROL_CS3_reserved2_MASK 0x0000ff00
-#define BCHP_NAND_ACC_CONTROL_CS3_reserved2_SHIFT 8
-
-/* NAND :: ACC_CONTROL_CS3 :: SECTOR_SIZE_1K [07:07] */
-#define BCHP_NAND_ACC_CONTROL_CS3_SECTOR_SIZE_1K_MASK 0x00000080
-#define BCHP_NAND_ACC_CONTROL_CS3_SECTOR_SIZE_1K_SHIFT 7
-#define BCHP_NAND_ACC_CONTROL_CS3_SECTOR_SIZE_1K_DEFAULT 0x00000000
-
-/* NAND :: ACC_CONTROL_CS3 :: SPARE_AREA_SIZE [06:00] */
-#define BCHP_NAND_ACC_CONTROL_CS3_SPARE_AREA_SIZE_MASK 0x0000007f
-#define BCHP_NAND_ACC_CONTROL_CS3_SPARE_AREA_SIZE_SHIFT 0
-#define BCHP_NAND_ACC_CONTROL_CS3_SPARE_AREA_SIZE_DEFAULT 0x00000010
-
-/***************************************************************************
- *CONFIG_EXT_CS3 - Nand Flash Config Extension
- ***************************************************************************/
-/* NAND :: CONFIG_EXT_CS3 :: reserved0 [31:12] */
-#define BCHP_NAND_CONFIG_EXT_CS3_reserved0_MASK 0xfffff000
-#define BCHP_NAND_CONFIG_EXT_CS3_reserved0_SHIFT 12
-
-/* NAND :: CONFIG_EXT_CS3 :: BLOCK_SIZE [11:04] */
-#define BCHP_NAND_CONFIG_EXT_CS3_BLOCK_SIZE_MASK 0x00000ff0
-#define BCHP_NAND_CONFIG_EXT_CS3_BLOCK_SIZE_SHIFT 4
-#define BCHP_NAND_CONFIG_EXT_CS3_BLOCK_SIZE_BK_SIZE_8KB 0
-#define BCHP_NAND_CONFIG_EXT_CS3_BLOCK_SIZE_BK_SIZE_16KB 1
-#define BCHP_NAND_CONFIG_EXT_CS3_BLOCK_SIZE_BK_SIZE_32KB 2
-#define BCHP_NAND_CONFIG_EXT_CS3_BLOCK_SIZE_BK_SIZE_64KB 3
-#define BCHP_NAND_CONFIG_EXT_CS3_BLOCK_SIZE_BK_SIZE_128KB 4
-#define BCHP_NAND_CONFIG_EXT_CS3_BLOCK_SIZE_BK_SIZE_256KB 5
-#define BCHP_NAND_CONFIG_EXT_CS3_BLOCK_SIZE_BK_SIZE_512KB 6
-#define BCHP_NAND_CONFIG_EXT_CS3_BLOCK_SIZE_BK_SIZE_1024KB 7
-#define BCHP_NAND_CONFIG_EXT_CS3_BLOCK_SIZE_BK_SIZE_2048KB 8
-#define BCHP_NAND_CONFIG_EXT_CS3_BLOCK_SIZE_BK_SIZE_4096KB 9
-#define BCHP_NAND_CONFIG_EXT_CS3_BLOCK_SIZE_BK_SIZE_8192KB 10
-
-/* NAND :: CONFIG_EXT_CS3 :: PAGE_SIZE [03:00] */
-#define BCHP_NAND_CONFIG_EXT_CS3_PAGE_SIZE_MASK 0x0000000f
-#define BCHP_NAND_CONFIG_EXT_CS3_PAGE_SIZE_SHIFT 0
-#define BCHP_NAND_CONFIG_EXT_CS3_PAGE_SIZE_PG_SIZE_512 0
-#define BCHP_NAND_CONFIG_EXT_CS3_PAGE_SIZE_PG_SIZE_1KB 1
-#define BCHP_NAND_CONFIG_EXT_CS3_PAGE_SIZE_PG_SIZE_2KB 2
-#define BCHP_NAND_CONFIG_EXT_CS3_PAGE_SIZE_PG_SIZE_4KB 3
-#define BCHP_NAND_CONFIG_EXT_CS3_PAGE_SIZE_PG_SIZE_8KB 4
-#define BCHP_NAND_CONFIG_EXT_CS3_PAGE_SIZE_PG_SIZE_16KB 5
-
-/***************************************************************************
- *CONFIG_CS3 - Nand Flash Config
- ***************************************************************************/
-/* NAND :: CONFIG_CS3 :: CONFIG_LOCK [31:31] */
-#define BCHP_NAND_CONFIG_CS3_CONFIG_LOCK_MASK 0x80000000
-#define BCHP_NAND_CONFIG_CS3_CONFIG_LOCK_SHIFT 31
-#define BCHP_NAND_CONFIG_CS3_CONFIG_LOCK_DEFAULT 0x00000000
-
-/* NAND :: CONFIG_CS3 :: reserved0 [30:28] */
-#define BCHP_NAND_CONFIG_CS3_reserved0_MASK 0x70000000
-#define BCHP_NAND_CONFIG_CS3_reserved0_SHIFT 28
-
-/* NAND :: CONFIG_CS3 :: DEVICE_SIZE [27:24] */
-#define BCHP_NAND_CONFIG_CS3_DEVICE_SIZE_MASK 0x0f000000
-#define BCHP_NAND_CONFIG_CS3_DEVICE_SIZE_SHIFT 24
-#define BCHP_NAND_CONFIG_CS3_DEVICE_SIZE_DVC_SIZE_4MB 0
-#define BCHP_NAND_CONFIG_CS3_DEVICE_SIZE_DVC_SIZE_8MB 1
-#define BCHP_NAND_CONFIG_CS3_DEVICE_SIZE_DVC_SIZE_16MB 2
-#define BCHP_NAND_CONFIG_CS3_DEVICE_SIZE_DVC_SIZE_32MB 3
-#define BCHP_NAND_CONFIG_CS3_DEVICE_SIZE_DVC_SIZE_64MB 4
-#define BCHP_NAND_CONFIG_CS3_DEVICE_SIZE_DVC_SIZE_128MB 5
-#define BCHP_NAND_CONFIG_CS3_DEVICE_SIZE_DVC_SIZE_256MB 6
-#define BCHP_NAND_CONFIG_CS3_DEVICE_SIZE_DVC_SIZE_512MB 7
-#define BCHP_NAND_CONFIG_CS3_DEVICE_SIZE_DVC_SIZE_1GB 8
-#define BCHP_NAND_CONFIG_CS3_DEVICE_SIZE_DVC_SIZE_2GB 9
-#define BCHP_NAND_CONFIG_CS3_DEVICE_SIZE_DVC_SIZE_4GB 10
-#define BCHP_NAND_CONFIG_CS3_DEVICE_SIZE_DVC_SIZE_8GB 11
-#define BCHP_NAND_CONFIG_CS3_DEVICE_SIZE_DVC_SIZE_16GB 12
-#define BCHP_NAND_CONFIG_CS3_DEVICE_SIZE_DVC_SIZE_32GB 13
-#define BCHP_NAND_CONFIG_CS3_DEVICE_SIZE_DVC_SIZE_64GB 14
-#define BCHP_NAND_CONFIG_CS3_DEVICE_SIZE_DVC_SIZE_128GB 15
-
-/* NAND :: CONFIG_CS3 :: DEVICE_WIDTH [23:23] */
-#define BCHP_NAND_CONFIG_CS3_DEVICE_WIDTH_MASK 0x00800000
-#define BCHP_NAND_CONFIG_CS3_DEVICE_WIDTH_SHIFT 23
-#define BCHP_NAND_CONFIG_CS3_DEVICE_WIDTH_DVC_WIDTH_8 0
-#define BCHP_NAND_CONFIG_CS3_DEVICE_WIDTH_DVC_WIDTH_16 1
-
-/* NAND :: CONFIG_CS3 :: reserved1 [22:19] */
-#define BCHP_NAND_CONFIG_CS3_reserved1_MASK 0x00780000
-#define BCHP_NAND_CONFIG_CS3_reserved1_SHIFT 19
-
-/* NAND :: CONFIG_CS3 :: FUL_ADR_BYTES [18:16] */
-#define BCHP_NAND_CONFIG_CS3_FUL_ADR_BYTES_MASK 0x00070000
-#define BCHP_NAND_CONFIG_CS3_FUL_ADR_BYTES_SHIFT 16
-
-/* NAND :: CONFIG_CS3 :: reserved2 [15:15] */
-#define BCHP_NAND_CONFIG_CS3_reserved2_MASK 0x00008000
-#define BCHP_NAND_CONFIG_CS3_reserved2_SHIFT 15
-
-/* NAND :: CONFIG_CS3 :: COL_ADR_BYTES [14:12] */
-#define BCHP_NAND_CONFIG_CS3_COL_ADR_BYTES_MASK 0x00007000
-#define BCHP_NAND_CONFIG_CS3_COL_ADR_BYTES_SHIFT 12
-
-/* NAND :: CONFIG_CS3 :: reserved3 [11:11] */
-#define BCHP_NAND_CONFIG_CS3_reserved3_MASK 0x00000800
-#define BCHP_NAND_CONFIG_CS3_reserved3_SHIFT 11
-
-/* NAND :: CONFIG_CS3 :: BLK_ADR_BYTES [10:08] */
-#define BCHP_NAND_CONFIG_CS3_BLK_ADR_BYTES_MASK 0x00000700
-#define BCHP_NAND_CONFIG_CS3_BLK_ADR_BYTES_SHIFT 8
-
-/* NAND :: CONFIG_CS3 :: reserved4 [07:00] */
-#define BCHP_NAND_CONFIG_CS3_reserved4_MASK 0x000000ff
-#define BCHP_NAND_CONFIG_CS3_reserved4_SHIFT 0
-
-/***************************************************************************
- *TIMING_1_CS3 - Nand Flash Timing Parameters 1
- ***************************************************************************/
-/* NAND :: TIMING_1_CS3 :: tWP [31:28] */
-#define BCHP_NAND_TIMING_1_CS3_tWP_MASK 0xf0000000
-#define BCHP_NAND_TIMING_1_CS3_tWP_SHIFT 28
-#define BCHP_NAND_TIMING_1_CS3_tWP_DEFAULT 0x00000006
-
-/* NAND :: TIMING_1_CS3 :: tWH [27:24] */
-#define BCHP_NAND_TIMING_1_CS3_tWH_MASK 0x0f000000
-#define BCHP_NAND_TIMING_1_CS3_tWH_SHIFT 24
-#define BCHP_NAND_TIMING_1_CS3_tWH_DEFAULT 0x00000005
-
-/* NAND :: TIMING_1_CS3 :: tRP [23:20] */
-#define BCHP_NAND_TIMING_1_CS3_tRP_MASK 0x00f00000
-#define BCHP_NAND_TIMING_1_CS3_tRP_SHIFT 20
-#define BCHP_NAND_TIMING_1_CS3_tRP_DEFAULT 0x00000007
-
-/* NAND :: TIMING_1_CS3 :: tREH [19:16] */
-#define BCHP_NAND_TIMING_1_CS3_tREH_MASK 0x000f0000
-#define BCHP_NAND_TIMING_1_CS3_tREH_SHIFT 16
-#define BCHP_NAND_TIMING_1_CS3_tREH_DEFAULT 0x00000004
-
-/* NAND :: TIMING_1_CS3 :: tCS [15:12] */
-#define BCHP_NAND_TIMING_1_CS3_tCS_MASK 0x0000f000
-#define BCHP_NAND_TIMING_1_CS3_tCS_SHIFT 12
-#define BCHP_NAND_TIMING_1_CS3_tCS_DEFAULT 0x00000008
-
-/* NAND :: TIMING_1_CS3 :: tCLH [11:08] */
-#define BCHP_NAND_TIMING_1_CS3_tCLH_MASK 0x00000f00
-#define BCHP_NAND_TIMING_1_CS3_tCLH_SHIFT 8
-#define BCHP_NAND_TIMING_1_CS3_tCLH_DEFAULT 0x00000004
-
-/* NAND :: TIMING_1_CS3 :: tALH [07:04] */
-#define BCHP_NAND_TIMING_1_CS3_tALH_MASK 0x000000f0
-#define BCHP_NAND_TIMING_1_CS3_tALH_SHIFT 4
-#define BCHP_NAND_TIMING_1_CS3_tALH_DEFAULT 0x00000005
-
-/* NAND :: TIMING_1_CS3 :: tADL [03:00] */
-#define BCHP_NAND_TIMING_1_CS3_tADL_MASK 0x0000000f
-#define BCHP_NAND_TIMING_1_CS3_tADL_SHIFT 0
-#define BCHP_NAND_TIMING_1_CS3_tADL_DEFAULT 0x0000000b
-
-/***************************************************************************
- *TIMING_2_CS3 - Nand Flash Timing Parameters 2
- ***************************************************************************/
-/* NAND :: TIMING_2_CS3 :: CLK_SELECT [31:31] */
-#define BCHP_NAND_TIMING_2_CS3_CLK_SELECT_MASK 0x80000000
-#define BCHP_NAND_TIMING_2_CS3_CLK_SELECT_SHIFT 31
-#define BCHP_NAND_TIMING_2_CS3_CLK_SELECT_DEFAULT 0x00000000
-#define BCHP_NAND_TIMING_2_CS3_CLK_SELECT_CLK_108 0
-#define BCHP_NAND_TIMING_2_CS3_CLK_SELECT_CLK_216 1
-
-/* NAND :: TIMING_2_CS3 :: reserved0 [30:20] */
-#define BCHP_NAND_TIMING_2_CS3_reserved0_MASK 0x7ff00000
-#define BCHP_NAND_TIMING_2_CS3_reserved0_SHIFT 20
-
-/* NAND :: TIMING_2_CS3 :: tCCS [19:16] */
-#define BCHP_NAND_TIMING_2_CS3_tCCS_MASK 0x000f0000
-#define BCHP_NAND_TIMING_2_CS3_tCCS_SHIFT 16
-#define BCHP_NAND_TIMING_2_CS3_tCCS_DEFAULT 0x00000009
-
-/* NAND :: TIMING_2_CS3 :: reserved1 [15:13] */
-#define BCHP_NAND_TIMING_2_CS3_reserved1_MASK 0x0000e000
-#define BCHP_NAND_TIMING_2_CS3_reserved1_SHIFT 13
-
-/* NAND :: TIMING_2_CS3 :: tWB [12:09] */
-#define BCHP_NAND_TIMING_2_CS3_tWB_MASK 0x00001e00
-#define BCHP_NAND_TIMING_2_CS3_tWB_SHIFT 9
-#define BCHP_NAND_TIMING_2_CS3_tWB_DEFAULT 0x0000000f
-
-/* NAND :: TIMING_2_CS3 :: tWHR [08:04] */
-#define BCHP_NAND_TIMING_2_CS3_tWHR_MASK 0x000001f0
-#define BCHP_NAND_TIMING_2_CS3_tWHR_SHIFT 4
-#define BCHP_NAND_TIMING_2_CS3_tWHR_DEFAULT 0x00000009
-
-/* NAND :: TIMING_2_CS3 :: tREAD [03:00] */
-#define BCHP_NAND_TIMING_2_CS3_tREAD_MASK 0x0000000f
-#define BCHP_NAND_TIMING_2_CS3_tREAD_SHIFT 0
-#define BCHP_NAND_TIMING_2_CS3_tREAD_DEFAULT 0x00000006
-
-/***************************************************************************
- *ACC_CONTROL_CS4 - Nand Flash Access Control
- ***************************************************************************/
-/* NAND :: ACC_CONTROL_CS4 :: RD_ECC_EN [31:31] */
-#define BCHP_NAND_ACC_CONTROL_CS4_RD_ECC_EN_MASK 0x80000000
-#define BCHP_NAND_ACC_CONTROL_CS4_RD_ECC_EN_SHIFT 31
-#define BCHP_NAND_ACC_CONTROL_CS4_RD_ECC_EN_DEFAULT 0x00000001
-
-/* NAND :: ACC_CONTROL_CS4 :: WR_ECC_EN [30:30] */
-#define BCHP_NAND_ACC_CONTROL_CS4_WR_ECC_EN_MASK 0x40000000
-#define BCHP_NAND_ACC_CONTROL_CS4_WR_ECC_EN_SHIFT 30
-#define BCHP_NAND_ACC_CONTROL_CS4_WR_ECC_EN_DEFAULT 0x00000001
-
-/* NAND :: ACC_CONTROL_CS4 :: CE_CARE [29:29] */
-#define BCHP_NAND_ACC_CONTROL_CS4_CE_CARE_MASK 0x20000000
-#define BCHP_NAND_ACC_CONTROL_CS4_CE_CARE_SHIFT 29
-#define BCHP_NAND_ACC_CONTROL_CS4_CE_CARE_DEFAULT 0x00000000
-
-/* NAND :: ACC_CONTROL_CS4 :: reserved0 [28:28] */
-#define BCHP_NAND_ACC_CONTROL_CS4_reserved0_MASK 0x10000000
-#define BCHP_NAND_ACC_CONTROL_CS4_reserved0_SHIFT 28
-
-/* NAND :: ACC_CONTROL_CS4 :: RD_ERASED_ECC_EN [27:27] */
-#define BCHP_NAND_ACC_CONTROL_CS4_RD_ERASED_ECC_EN_MASK 0x08000000
-#define BCHP_NAND_ACC_CONTROL_CS4_RD_ERASED_ECC_EN_SHIFT 27
-#define BCHP_NAND_ACC_CONTROL_CS4_RD_ERASED_ECC_EN_DEFAULT 0x00000000
-
-/* NAND :: ACC_CONTROL_CS4 :: PARTIAL_PAGE_EN [26:26] */
-#define BCHP_NAND_ACC_CONTROL_CS4_PARTIAL_PAGE_EN_MASK 0x04000000
-#define BCHP_NAND_ACC_CONTROL_CS4_PARTIAL_PAGE_EN_SHIFT 26
-#define BCHP_NAND_ACC_CONTROL_CS4_PARTIAL_PAGE_EN_DEFAULT 0x00000000
-
-/* NAND :: ACC_CONTROL_CS4 :: WR_PREEMPT_EN [25:25] */
-#define BCHP_NAND_ACC_CONTROL_CS4_WR_PREEMPT_EN_MASK 0x02000000
-#define BCHP_NAND_ACC_CONTROL_CS4_WR_PREEMPT_EN_SHIFT 25
-#define BCHP_NAND_ACC_CONTROL_CS4_WR_PREEMPT_EN_DEFAULT 0x00000001
-
-/* NAND :: ACC_CONTROL_CS4 :: PAGE_HIT_EN [24:24] */
-#define BCHP_NAND_ACC_CONTROL_CS4_PAGE_HIT_EN_MASK 0x01000000
-#define BCHP_NAND_ACC_CONTROL_CS4_PAGE_HIT_EN_SHIFT 24
-#define BCHP_NAND_ACC_CONTROL_CS4_PAGE_HIT_EN_DEFAULT 0x00000001
-
-/* NAND :: ACC_CONTROL_CS4 :: PREFETCH_EN [23:23] */
-#define BCHP_NAND_ACC_CONTROL_CS4_PREFETCH_EN_MASK 0x00800000
-#define BCHP_NAND_ACC_CONTROL_CS4_PREFETCH_EN_SHIFT 23
-#define BCHP_NAND_ACC_CONTROL_CS4_PREFETCH_EN_DEFAULT 0x00000000
-
-/* NAND :: ACC_CONTROL_CS4 :: CACHE_MODE_EN [22:22] */
-#define BCHP_NAND_ACC_CONTROL_CS4_CACHE_MODE_EN_MASK 0x00400000
-#define BCHP_NAND_ACC_CONTROL_CS4_CACHE_MODE_EN_SHIFT 22
-#define BCHP_NAND_ACC_CONTROL_CS4_CACHE_MODE_EN_DEFAULT 0x00000000
-
-/* NAND :: ACC_CONTROL_CS4 :: reserved1 [21:21] */
-#define BCHP_NAND_ACC_CONTROL_CS4_reserved1_MASK 0x00200000
-#define BCHP_NAND_ACC_CONTROL_CS4_reserved1_SHIFT 21
-
-/* NAND :: ACC_CONTROL_CS4 :: ECC_LEVEL [20:16] */
-#define BCHP_NAND_ACC_CONTROL_CS4_ECC_LEVEL_MASK 0x001f0000
-#define BCHP_NAND_ACC_CONTROL_CS4_ECC_LEVEL_SHIFT 16
-#define BCHP_NAND_ACC_CONTROL_CS4_ECC_LEVEL_DEFAULT 0x0000000f
-
-/* NAND :: ACC_CONTROL_CS4 :: reserved2 [15:08] */
-#define BCHP_NAND_ACC_CONTROL_CS4_reserved2_MASK 0x0000ff00
-#define BCHP_NAND_ACC_CONTROL_CS4_reserved2_SHIFT 8
-
-/* NAND :: ACC_CONTROL_CS4 :: SECTOR_SIZE_1K [07:07] */
-#define BCHP_NAND_ACC_CONTROL_CS4_SECTOR_SIZE_1K_MASK 0x00000080
-#define BCHP_NAND_ACC_CONTROL_CS4_SECTOR_SIZE_1K_SHIFT 7
-#define BCHP_NAND_ACC_CONTROL_CS4_SECTOR_SIZE_1K_DEFAULT 0x00000000
-
-/* NAND :: ACC_CONTROL_CS4 :: SPARE_AREA_SIZE [06:00] */
-#define BCHP_NAND_ACC_CONTROL_CS4_SPARE_AREA_SIZE_MASK 0x0000007f
-#define BCHP_NAND_ACC_CONTROL_CS4_SPARE_AREA_SIZE_SHIFT 0
-#define BCHP_NAND_ACC_CONTROL_CS4_SPARE_AREA_SIZE_DEFAULT 0x00000010
-
-/***************************************************************************
- *CONFIG_EXT_CS4 - Nand Flash Config Extension
- ***************************************************************************/
-/* NAND :: CONFIG_EXT_CS4 :: reserved0 [31:12] */
-#define BCHP_NAND_CONFIG_EXT_CS4_reserved0_MASK 0xfffff000
-#define BCHP_NAND_CONFIG_EXT_CS4_reserved0_SHIFT 12
-
-/* NAND :: CONFIG_EXT_CS4 :: BLOCK_SIZE [11:04] */
-#define BCHP_NAND_CONFIG_EXT_CS4_BLOCK_SIZE_MASK 0x00000ff0
-#define BCHP_NAND_CONFIG_EXT_CS4_BLOCK_SIZE_SHIFT 4
-#define BCHP_NAND_CONFIG_EXT_CS4_BLOCK_SIZE_BK_SIZE_8KB 0
-#define BCHP_NAND_CONFIG_EXT_CS4_BLOCK_SIZE_BK_SIZE_16KB 1
-#define BCHP_NAND_CONFIG_EXT_CS4_BLOCK_SIZE_BK_SIZE_32KB 2
-#define BCHP_NAND_CONFIG_EXT_CS4_BLOCK_SIZE_BK_SIZE_64KB 3
-#define BCHP_NAND_CONFIG_EXT_CS4_BLOCK_SIZE_BK_SIZE_128KB 4
-#define BCHP_NAND_CONFIG_EXT_CS4_BLOCK_SIZE_BK_SIZE_256KB 5
-#define BCHP_NAND_CONFIG_EXT_CS4_BLOCK_SIZE_BK_SIZE_512KB 6
-#define BCHP_NAND_CONFIG_EXT_CS4_BLOCK_SIZE_BK_SIZE_1024KB 7
-#define BCHP_NAND_CONFIG_EXT_CS4_BLOCK_SIZE_BK_SIZE_2048KB 8
-#define BCHP_NAND_CONFIG_EXT_CS4_BLOCK_SIZE_BK_SIZE_4096KB 9
-#define BCHP_NAND_CONFIG_EXT_CS4_BLOCK_SIZE_BK_SIZE_8192KB 10
-
-/* NAND :: CONFIG_EXT_CS4 :: PAGE_SIZE [03:00] */
-#define BCHP_NAND_CONFIG_EXT_CS4_PAGE_SIZE_MASK 0x0000000f
-#define BCHP_NAND_CONFIG_EXT_CS4_PAGE_SIZE_SHIFT 0
-#define BCHP_NAND_CONFIG_EXT_CS4_PAGE_SIZE_PG_SIZE_512 0
-#define BCHP_NAND_CONFIG_EXT_CS4_PAGE_SIZE_PG_SIZE_1KB 1
-#define BCHP_NAND_CONFIG_EXT_CS4_PAGE_SIZE_PG_SIZE_2KB 2
-#define BCHP_NAND_CONFIG_EXT_CS4_PAGE_SIZE_PG_SIZE_4KB 3
-#define BCHP_NAND_CONFIG_EXT_CS4_PAGE_SIZE_PG_SIZE_8KB 4
-#define BCHP_NAND_CONFIG_EXT_CS4_PAGE_SIZE_PG_SIZE_16KB 5
-
-/***************************************************************************
- *CONFIG_CS4 - Nand Flash Config
- ***************************************************************************/
-/* NAND :: CONFIG_CS4 :: CONFIG_LOCK [31:31] */
-#define BCHP_NAND_CONFIG_CS4_CONFIG_LOCK_MASK 0x80000000
-#define BCHP_NAND_CONFIG_CS4_CONFIG_LOCK_SHIFT 31
-#define BCHP_NAND_CONFIG_CS4_CONFIG_LOCK_DEFAULT 0x00000000
-
-/* NAND :: CONFIG_CS4 :: reserved0 [30:28] */
-#define BCHP_NAND_CONFIG_CS4_reserved0_MASK 0x70000000
-#define BCHP_NAND_CONFIG_CS4_reserved0_SHIFT 28
-
-/* NAND :: CONFIG_CS4 :: DEVICE_SIZE [27:24] */
-#define BCHP_NAND_CONFIG_CS4_DEVICE_SIZE_MASK 0x0f000000
-#define BCHP_NAND_CONFIG_CS4_DEVICE_SIZE_SHIFT 24
-#define BCHP_NAND_CONFIG_CS4_DEVICE_SIZE_DVC_SIZE_4MB 0
-#define BCHP_NAND_CONFIG_CS4_DEVICE_SIZE_DVC_SIZE_8MB 1
-#define BCHP_NAND_CONFIG_CS4_DEVICE_SIZE_DVC_SIZE_16MB 2
-#define BCHP_NAND_CONFIG_CS4_DEVICE_SIZE_DVC_SIZE_32MB 3
-#define BCHP_NAND_CONFIG_CS4_DEVICE_SIZE_DVC_SIZE_64MB 4
-#define BCHP_NAND_CONFIG_CS4_DEVICE_SIZE_DVC_SIZE_128MB 5
-#define BCHP_NAND_CONFIG_CS4_DEVICE_SIZE_DVC_SIZE_256MB 6
-#define BCHP_NAND_CONFIG_CS4_DEVICE_SIZE_DVC_SIZE_512MB 7
-#define BCHP_NAND_CONFIG_CS4_DEVICE_SIZE_DVC_SIZE_1GB 8
-#define BCHP_NAND_CONFIG_CS4_DEVICE_SIZE_DVC_SIZE_2GB 9
-#define BCHP_NAND_CONFIG_CS4_DEVICE_SIZE_DVC_SIZE_4GB 10
-#define BCHP_NAND_CONFIG_CS4_DEVICE_SIZE_DVC_SIZE_8GB 11
-#define BCHP_NAND_CONFIG_CS4_DEVICE_SIZE_DVC_SIZE_16GB 12
-#define BCHP_NAND_CONFIG_CS4_DEVICE_SIZE_DVC_SIZE_32GB 13
-#define BCHP_NAND_CONFIG_CS4_DEVICE_SIZE_DVC_SIZE_64GB 14
-#define BCHP_NAND_CONFIG_CS4_DEVICE_SIZE_DVC_SIZE_128GB 15
-
-/* NAND :: CONFIG_CS4 :: DEVICE_WIDTH [23:23] */
-#define BCHP_NAND_CONFIG_CS4_DEVICE_WIDTH_MASK 0x00800000
-#define BCHP_NAND_CONFIG_CS4_DEVICE_WIDTH_SHIFT 23
-#define BCHP_NAND_CONFIG_CS4_DEVICE_WIDTH_DVC_WIDTH_8 0
-#define BCHP_NAND_CONFIG_CS4_DEVICE_WIDTH_DVC_WIDTH_16 1
-
-/* NAND :: CONFIG_CS4 :: reserved1 [22:19] */
-#define BCHP_NAND_CONFIG_CS4_reserved1_MASK 0x00780000
-#define BCHP_NAND_CONFIG_CS4_reserved1_SHIFT 19
-
-/* NAND :: CONFIG_CS4 :: FUL_ADR_BYTES [18:16] */
-#define BCHP_NAND_CONFIG_CS4_FUL_ADR_BYTES_MASK 0x00070000
-#define BCHP_NAND_CONFIG_CS4_FUL_ADR_BYTES_SHIFT 16
-
-/* NAND :: CONFIG_CS4 :: reserved2 [15:15] */
-#define BCHP_NAND_CONFIG_CS4_reserved2_MASK 0x00008000
-#define BCHP_NAND_CONFIG_CS4_reserved2_SHIFT 15
-
-/* NAND :: CONFIG_CS4 :: COL_ADR_BYTES [14:12] */
-#define BCHP_NAND_CONFIG_CS4_COL_ADR_BYTES_MASK 0x00007000
-#define BCHP_NAND_CONFIG_CS4_COL_ADR_BYTES_SHIFT 12
-
-/* NAND :: CONFIG_CS4 :: reserved3 [11:11] */
-#define BCHP_NAND_CONFIG_CS4_reserved3_MASK 0x00000800
-#define BCHP_NAND_CONFIG_CS4_reserved3_SHIFT 11
-
-/* NAND :: CONFIG_CS4 :: BLK_ADR_BYTES [10:08] */
-#define BCHP_NAND_CONFIG_CS4_BLK_ADR_BYTES_MASK 0x00000700
-#define BCHP_NAND_CONFIG_CS4_BLK_ADR_BYTES_SHIFT 8
-
-/* NAND :: CONFIG_CS4 :: reserved4 [07:00] */
-#define BCHP_NAND_CONFIG_CS4_reserved4_MASK 0x000000ff
-#define BCHP_NAND_CONFIG_CS4_reserved4_SHIFT 0
-
-/***************************************************************************
- *TIMING_1_CS4 - Nand Flash Timing Parameters 1
- ***************************************************************************/
-/* NAND :: TIMING_1_CS4 :: tWP [31:28] */
-#define BCHP_NAND_TIMING_1_CS4_tWP_MASK 0xf0000000
-#define BCHP_NAND_TIMING_1_CS4_tWP_SHIFT 28
-#define BCHP_NAND_TIMING_1_CS4_tWP_DEFAULT 0x00000006
-
-/* NAND :: TIMING_1_CS4 :: tWH [27:24] */
-#define BCHP_NAND_TIMING_1_CS4_tWH_MASK 0x0f000000
-#define BCHP_NAND_TIMING_1_CS4_tWH_SHIFT 24
-#define BCHP_NAND_TIMING_1_CS4_tWH_DEFAULT 0x00000005
-
-/* NAND :: TIMING_1_CS4 :: tRP [23:20] */
-#define BCHP_NAND_TIMING_1_CS4_tRP_MASK 0x00f00000
-#define BCHP_NAND_TIMING_1_CS4_tRP_SHIFT 20
-#define BCHP_NAND_TIMING_1_CS4_tRP_DEFAULT 0x00000007
-
-/* NAND :: TIMING_1_CS4 :: tREH [19:16] */
-#define BCHP_NAND_TIMING_1_CS4_tREH_MASK 0x000f0000
-#define BCHP_NAND_TIMING_1_CS4_tREH_SHIFT 16
-#define BCHP_NAND_TIMING_1_CS4_tREH_DEFAULT 0x00000004
-
-/* NAND :: TIMING_1_CS4 :: tCS [15:12] */
-#define BCHP_NAND_TIMING_1_CS4_tCS_MASK 0x0000f000
-#define BCHP_NAND_TIMING_1_CS4_tCS_SHIFT 12
-#define BCHP_NAND_TIMING_1_CS4_tCS_DEFAULT 0x00000008
-
-/* NAND :: TIMING_1_CS4 :: tCLH [11:08] */
-#define BCHP_NAND_TIMING_1_CS4_tCLH_MASK 0x00000f00
-#define BCHP_NAND_TIMING_1_CS4_tCLH_SHIFT 8
-#define BCHP_NAND_TIMING_1_CS4_tCLH_DEFAULT 0x00000004
-
-/* NAND :: TIMING_1_CS4 :: tALH [07:04] */
-#define BCHP_NAND_TIMING_1_CS4_tALH_MASK 0x000000f0
-#define BCHP_NAND_TIMING_1_CS4_tALH_SHIFT 4
-#define BCHP_NAND_TIMING_1_CS4_tALH_DEFAULT 0x00000005
-
-/* NAND :: TIMING_1_CS4 :: tADL [03:00] */
-#define BCHP_NAND_TIMING_1_CS4_tADL_MASK 0x0000000f
-#define BCHP_NAND_TIMING_1_CS4_tADL_SHIFT 0
-#define BCHP_NAND_TIMING_1_CS4_tADL_DEFAULT 0x0000000b
-
-/***************************************************************************
- *TIMING_2_CS4 - Nand Flash Timing Parameters 2
- ***************************************************************************/
-/* NAND :: TIMING_2_CS4 :: CLK_SELECT [31:31] */
-#define BCHP_NAND_TIMING_2_CS4_CLK_SELECT_MASK 0x80000000
-#define BCHP_NAND_TIMING_2_CS4_CLK_SELECT_SHIFT 31
-#define BCHP_NAND_TIMING_2_CS4_CLK_SELECT_DEFAULT 0x00000000
-#define BCHP_NAND_TIMING_2_CS4_CLK_SELECT_CLK_108 0
-#define BCHP_NAND_TIMING_2_CS4_CLK_SELECT_CLK_216 1
-
-/* NAND :: TIMING_2_CS4 :: reserved0 [30:20] */
-#define BCHP_NAND_TIMING_2_CS4_reserved0_MASK 0x7ff00000
-#define BCHP_NAND_TIMING_2_CS4_reserved0_SHIFT 20
-
-/* NAND :: TIMING_2_CS4 :: tCCS [19:16] */
-#define BCHP_NAND_TIMING_2_CS4_tCCS_MASK 0x000f0000
-#define BCHP_NAND_TIMING_2_CS4_tCCS_SHIFT 16
-#define BCHP_NAND_TIMING_2_CS4_tCCS_DEFAULT 0x00000009
-
-/* NAND :: TIMING_2_CS4 :: reserved1 [15:13] */
-#define BCHP_NAND_TIMING_2_CS4_reserved1_MASK 0x0000e000
-#define BCHP_NAND_TIMING_2_CS4_reserved1_SHIFT 13
-
-/* NAND :: TIMING_2_CS4 :: tWB [12:09] */
-#define BCHP_NAND_TIMING_2_CS4_tWB_MASK 0x00001e00
-#define BCHP_NAND_TIMING_2_CS4_tWB_SHIFT 9
-#define BCHP_NAND_TIMING_2_CS4_tWB_DEFAULT 0x0000000f
-
-/* NAND :: TIMING_2_CS4 :: tWHR [08:04] */
-#define BCHP_NAND_TIMING_2_CS4_tWHR_MASK 0x000001f0
-#define BCHP_NAND_TIMING_2_CS4_tWHR_SHIFT 4
-#define BCHP_NAND_TIMING_2_CS4_tWHR_DEFAULT 0x00000009
-
-/* NAND :: TIMING_2_CS4 :: tREAD [03:00] */
-#define BCHP_NAND_TIMING_2_CS4_tREAD_MASK 0x0000000f
-#define BCHP_NAND_TIMING_2_CS4_tREAD_SHIFT 0
-#define BCHP_NAND_TIMING_2_CS4_tREAD_DEFAULT 0x00000006
-
-/***************************************************************************
- *ACC_CONTROL_CS5 - Nand Flash Access Control
- ***************************************************************************/
-/* NAND :: ACC_CONTROL_CS5 :: RD_ECC_EN [31:31] */
-#define BCHP_NAND_ACC_CONTROL_CS5_RD_ECC_EN_MASK 0x80000000
-#define BCHP_NAND_ACC_CONTROL_CS5_RD_ECC_EN_SHIFT 31
-#define BCHP_NAND_ACC_CONTROL_CS5_RD_ECC_EN_DEFAULT 0x00000001
-
-/* NAND :: ACC_CONTROL_CS5 :: WR_ECC_EN [30:30] */
-#define BCHP_NAND_ACC_CONTROL_CS5_WR_ECC_EN_MASK 0x40000000
-#define BCHP_NAND_ACC_CONTROL_CS5_WR_ECC_EN_SHIFT 30
-#define BCHP_NAND_ACC_CONTROL_CS5_WR_ECC_EN_DEFAULT 0x00000001
-
-/* NAND :: ACC_CONTROL_CS5 :: CE_CARE [29:29] */
-#define BCHP_NAND_ACC_CONTROL_CS5_CE_CARE_MASK 0x20000000
-#define BCHP_NAND_ACC_CONTROL_CS5_CE_CARE_SHIFT 29
-#define BCHP_NAND_ACC_CONTROL_CS5_CE_CARE_DEFAULT 0x00000000
-
-/* NAND :: ACC_CONTROL_CS5 :: reserved0 [28:28] */
-#define BCHP_NAND_ACC_CONTROL_CS5_reserved0_MASK 0x10000000
-#define BCHP_NAND_ACC_CONTROL_CS5_reserved0_SHIFT 28
-
-/* NAND :: ACC_CONTROL_CS5 :: RD_ERASED_ECC_EN [27:27] */
-#define BCHP_NAND_ACC_CONTROL_CS5_RD_ERASED_ECC_EN_MASK 0x08000000
-#define BCHP_NAND_ACC_CONTROL_CS5_RD_ERASED_ECC_EN_SHIFT 27
-#define BCHP_NAND_ACC_CONTROL_CS5_RD_ERASED_ECC_EN_DEFAULT 0x00000000
-
-/* NAND :: ACC_CONTROL_CS5 :: PARTIAL_PAGE_EN [26:26] */
-#define BCHP_NAND_ACC_CONTROL_CS5_PARTIAL_PAGE_EN_MASK 0x04000000
-#define BCHP_NAND_ACC_CONTROL_CS5_PARTIAL_PAGE_EN_SHIFT 26
-#define BCHP_NAND_ACC_CONTROL_CS5_PARTIAL_PAGE_EN_DEFAULT 0x00000000
-
-/* NAND :: ACC_CONTROL_CS5 :: WR_PREEMPT_EN [25:25] */
-#define BCHP_NAND_ACC_CONTROL_CS5_WR_PREEMPT_EN_MASK 0x02000000
-#define BCHP_NAND_ACC_CONTROL_CS5_WR_PREEMPT_EN_SHIFT 25
-#define BCHP_NAND_ACC_CONTROL_CS5_WR_PREEMPT_EN_DEFAULT 0x00000001
-
-/* NAND :: ACC_CONTROL_CS5 :: PAGE_HIT_EN [24:24] */
-#define BCHP_NAND_ACC_CONTROL_CS5_PAGE_HIT_EN_MASK 0x01000000
-#define BCHP_NAND_ACC_CONTROL_CS5_PAGE_HIT_EN_SHIFT 24
-#define BCHP_NAND_ACC_CONTROL_CS5_PAGE_HIT_EN_DEFAULT 0x00000001
-
-/* NAND :: ACC_CONTROL_CS5 :: PREFETCH_EN [23:23] */
-#define BCHP_NAND_ACC_CONTROL_CS5_PREFETCH_EN_MASK 0x00800000
-#define BCHP_NAND_ACC_CONTROL_CS5_PREFETCH_EN_SHIFT 23
-#define BCHP_NAND_ACC_CONTROL_CS5_PREFETCH_EN_DEFAULT 0x00000000
-
-/* NAND :: ACC_CONTROL_CS5 :: CACHE_MODE_EN [22:22] */
-#define BCHP_NAND_ACC_CONTROL_CS5_CACHE_MODE_EN_MASK 0x00400000
-#define BCHP_NAND_ACC_CONTROL_CS5_CACHE_MODE_EN_SHIFT 22
-#define BCHP_NAND_ACC_CONTROL_CS5_CACHE_MODE_EN_DEFAULT 0x00000000
-
-/* NAND :: ACC_CONTROL_CS5 :: reserved1 [21:21] */
-#define BCHP_NAND_ACC_CONTROL_CS5_reserved1_MASK 0x00200000
-#define BCHP_NAND_ACC_CONTROL_CS5_reserved1_SHIFT 21
-
-/* NAND :: ACC_CONTROL_CS5 :: ECC_LEVEL [20:16] */
-#define BCHP_NAND_ACC_CONTROL_CS5_ECC_LEVEL_MASK 0x001f0000
-#define BCHP_NAND_ACC_CONTROL_CS5_ECC_LEVEL_SHIFT 16
-#define BCHP_NAND_ACC_CONTROL_CS5_ECC_LEVEL_DEFAULT 0x0000000f
-
-/* NAND :: ACC_CONTROL_CS5 :: reserved2 [15:08] */
-#define BCHP_NAND_ACC_CONTROL_CS5_reserved2_MASK 0x0000ff00
-#define BCHP_NAND_ACC_CONTROL_CS5_reserved2_SHIFT 8
-
-/* NAND :: ACC_CONTROL_CS5 :: SECTOR_SIZE_1K [07:07] */
-#define BCHP_NAND_ACC_CONTROL_CS5_SECTOR_SIZE_1K_MASK 0x00000080
-#define BCHP_NAND_ACC_CONTROL_CS5_SECTOR_SIZE_1K_SHIFT 7
-#define BCHP_NAND_ACC_CONTROL_CS5_SECTOR_SIZE_1K_DEFAULT 0x00000000
-
-/* NAND :: ACC_CONTROL_CS5 :: SPARE_AREA_SIZE [06:00] */
-#define BCHP_NAND_ACC_CONTROL_CS5_SPARE_AREA_SIZE_MASK 0x0000007f
-#define BCHP_NAND_ACC_CONTROL_CS5_SPARE_AREA_SIZE_SHIFT 0
-#define BCHP_NAND_ACC_CONTROL_CS5_SPARE_AREA_SIZE_DEFAULT 0x00000010
-
-/***************************************************************************
- *CONFIG_EXT_CS5 - Nand Flash Config Extension
- ***************************************************************************/
-/* NAND :: CONFIG_EXT_CS5 :: reserved0 [31:12] */
-#define BCHP_NAND_CONFIG_EXT_CS5_reserved0_MASK 0xfffff000
-#define BCHP_NAND_CONFIG_EXT_CS5_reserved0_SHIFT 12
-
-/* NAND :: CONFIG_EXT_CS5 :: BLOCK_SIZE [11:04] */
-#define BCHP_NAND_CONFIG_EXT_CS5_BLOCK_SIZE_MASK 0x00000ff0
-#define BCHP_NAND_CONFIG_EXT_CS5_BLOCK_SIZE_SHIFT 4
-#define BCHP_NAND_CONFIG_EXT_CS5_BLOCK_SIZE_BK_SIZE_8KB 0
-#define BCHP_NAND_CONFIG_EXT_CS5_BLOCK_SIZE_BK_SIZE_16KB 1
-#define BCHP_NAND_CONFIG_EXT_CS5_BLOCK_SIZE_BK_SIZE_32KB 2
-#define BCHP_NAND_CONFIG_EXT_CS5_BLOCK_SIZE_BK_SIZE_64KB 3
-#define BCHP_NAND_CONFIG_EXT_CS5_BLOCK_SIZE_BK_SIZE_128KB 4
-#define BCHP_NAND_CONFIG_EXT_CS5_BLOCK_SIZE_BK_SIZE_256KB 5
-#define BCHP_NAND_CONFIG_EXT_CS5_BLOCK_SIZE_BK_SIZE_512KB 6
-#define BCHP_NAND_CONFIG_EXT_CS5_BLOCK_SIZE_BK_SIZE_1024KB 7
-#define BCHP_NAND_CONFIG_EXT_CS5_BLOCK_SIZE_BK_SIZE_2048KB 8
-#define BCHP_NAND_CONFIG_EXT_CS5_BLOCK_SIZE_BK_SIZE_4096KB 9
-#define BCHP_NAND_CONFIG_EXT_CS5_BLOCK_SIZE_BK_SIZE_8192KB 10
-
-/* NAND :: CONFIG_EXT_CS5 :: PAGE_SIZE [03:00] */
-#define BCHP_NAND_CONFIG_EXT_CS5_PAGE_SIZE_MASK 0x0000000f
-#define BCHP_NAND_CONFIG_EXT_CS5_PAGE_SIZE_SHIFT 0
-#define BCHP_NAND_CONFIG_EXT_CS5_PAGE_SIZE_PG_SIZE_512 0
-#define BCHP_NAND_CONFIG_EXT_CS5_PAGE_SIZE_PG_SIZE_1KB 1
-#define BCHP_NAND_CONFIG_EXT_CS5_PAGE_SIZE_PG_SIZE_2KB 2
-#define BCHP_NAND_CONFIG_EXT_CS5_PAGE_SIZE_PG_SIZE_4KB 3
-#define BCHP_NAND_CONFIG_EXT_CS5_PAGE_SIZE_PG_SIZE_8KB 4
-#define BCHP_NAND_CONFIG_EXT_CS5_PAGE_SIZE_PG_SIZE_16KB 5
-
-/***************************************************************************
- *CONFIG_CS5 - Nand Flash Config
- ***************************************************************************/
-/* NAND :: CONFIG_CS5 :: CONFIG_LOCK [31:31] */
-#define BCHP_NAND_CONFIG_CS5_CONFIG_LOCK_MASK 0x80000000
-#define BCHP_NAND_CONFIG_CS5_CONFIG_LOCK_SHIFT 31
-#define BCHP_NAND_CONFIG_CS5_CONFIG_LOCK_DEFAULT 0x00000000
-
-/* NAND :: CONFIG_CS5 :: reserved0 [30:28] */
-#define BCHP_NAND_CONFIG_CS5_reserved0_MASK 0x70000000
-#define BCHP_NAND_CONFIG_CS5_reserved0_SHIFT 28
-
-/* NAND :: CONFIG_CS5 :: DEVICE_SIZE [27:24] */
-#define BCHP_NAND_CONFIG_CS5_DEVICE_SIZE_MASK 0x0f000000
-#define BCHP_NAND_CONFIG_CS5_DEVICE_SIZE_SHIFT 24
-#define BCHP_NAND_CONFIG_CS5_DEVICE_SIZE_DVC_SIZE_4MB 0
-#define BCHP_NAND_CONFIG_CS5_DEVICE_SIZE_DVC_SIZE_8MB 1
-#define BCHP_NAND_CONFIG_CS5_DEVICE_SIZE_DVC_SIZE_16MB 2
-#define BCHP_NAND_CONFIG_CS5_DEVICE_SIZE_DVC_SIZE_32MB 3
-#define BCHP_NAND_CONFIG_CS5_DEVICE_SIZE_DVC_SIZE_64MB 4
-#define BCHP_NAND_CONFIG_CS5_DEVICE_SIZE_DVC_SIZE_128MB 5
-#define BCHP_NAND_CONFIG_CS5_DEVICE_SIZE_DVC_SIZE_256MB 6
-#define BCHP_NAND_CONFIG_CS5_DEVICE_SIZE_DVC_SIZE_512MB 7
-#define BCHP_NAND_CONFIG_CS5_DEVICE_SIZE_DVC_SIZE_1GB 8
-#define BCHP_NAND_CONFIG_CS5_DEVICE_SIZE_DVC_SIZE_2GB 9
-#define BCHP_NAND_CONFIG_CS5_DEVICE_SIZE_DVC_SIZE_4GB 10
-#define BCHP_NAND_CONFIG_CS5_DEVICE_SIZE_DVC_SIZE_8GB 11
-#define BCHP_NAND_CONFIG_CS5_DEVICE_SIZE_DVC_SIZE_16GB 12
-#define BCHP_NAND_CONFIG_CS5_DEVICE_SIZE_DVC_SIZE_32GB 13
-#define BCHP_NAND_CONFIG_CS5_DEVICE_SIZE_DVC_SIZE_64GB 14
-#define BCHP_NAND_CONFIG_CS5_DEVICE_SIZE_DVC_SIZE_128GB 15
-
-/* NAND :: CONFIG_CS5 :: DEVICE_WIDTH [23:23] */
-#define BCHP_NAND_CONFIG_CS5_DEVICE_WIDTH_MASK 0x00800000
-#define BCHP_NAND_CONFIG_CS5_DEVICE_WIDTH_SHIFT 23
-#define BCHP_NAND_CONFIG_CS5_DEVICE_WIDTH_DVC_WIDTH_8 0
-#define BCHP_NAND_CONFIG_CS5_DEVICE_WIDTH_DVC_WIDTH_16 1
-
-/* NAND :: CONFIG_CS5 :: reserved1 [22:19] */
-#define BCHP_NAND_CONFIG_CS5_reserved1_MASK 0x00780000
-#define BCHP_NAND_CONFIG_CS5_reserved1_SHIFT 19
-
-/* NAND :: CONFIG_CS5 :: FUL_ADR_BYTES [18:16] */
-#define BCHP_NAND_CONFIG_CS5_FUL_ADR_BYTES_MASK 0x00070000
-#define BCHP_NAND_CONFIG_CS5_FUL_ADR_BYTES_SHIFT 16
-
-/* NAND :: CONFIG_CS5 :: reserved2 [15:15] */
-#define BCHP_NAND_CONFIG_CS5_reserved2_MASK 0x00008000
-#define BCHP_NAND_CONFIG_CS5_reserved2_SHIFT 15
-
-/* NAND :: CONFIG_CS5 :: COL_ADR_BYTES [14:12] */
-#define BCHP_NAND_CONFIG_CS5_COL_ADR_BYTES_MASK 0x00007000
-#define BCHP_NAND_CONFIG_CS5_COL_ADR_BYTES_SHIFT 12
-
-/* NAND :: CONFIG_CS5 :: reserved3 [11:11] */
-#define BCHP_NAND_CONFIG_CS5_reserved3_MASK 0x00000800
-#define BCHP_NAND_CONFIG_CS5_reserved3_SHIFT 11
-
-/* NAND :: CONFIG_CS5 :: BLK_ADR_BYTES [10:08] */
-#define BCHP_NAND_CONFIG_CS5_BLK_ADR_BYTES_MASK 0x00000700
-#define BCHP_NAND_CONFIG_CS5_BLK_ADR_BYTES_SHIFT 8
-
-/* NAND :: CONFIG_CS5 :: reserved4 [07:00] */
-#define BCHP_NAND_CONFIG_CS5_reserved4_MASK 0x000000ff
-#define BCHP_NAND_CONFIG_CS5_reserved4_SHIFT 0
-
-/***************************************************************************
- *TIMING_1_CS5 - Nand Flash Timing Parameters 1
- ***************************************************************************/
-/* NAND :: TIMING_1_CS5 :: tWP [31:28] */
-#define BCHP_NAND_TIMING_1_CS5_tWP_MASK 0xf0000000
-#define BCHP_NAND_TIMING_1_CS5_tWP_SHIFT 28
-#define BCHP_NAND_TIMING_1_CS5_tWP_DEFAULT 0x00000006
-
-/* NAND :: TIMING_1_CS5 :: tWH [27:24] */
-#define BCHP_NAND_TIMING_1_CS5_tWH_MASK 0x0f000000
-#define BCHP_NAND_TIMING_1_CS5_tWH_SHIFT 24
-#define BCHP_NAND_TIMING_1_CS5_tWH_DEFAULT 0x00000005
-
-/* NAND :: TIMING_1_CS5 :: tRP [23:20] */
-#define BCHP_NAND_TIMING_1_CS5_tRP_MASK 0x00f00000
-#define BCHP_NAND_TIMING_1_CS5_tRP_SHIFT 20
-#define BCHP_NAND_TIMING_1_CS5_tRP_DEFAULT 0x00000007
-
-/* NAND :: TIMING_1_CS5 :: tREH [19:16] */
-#define BCHP_NAND_TIMING_1_CS5_tREH_MASK 0x000f0000
-#define BCHP_NAND_TIMING_1_CS5_tREH_SHIFT 16
-#define BCHP_NAND_TIMING_1_CS5_tREH_DEFAULT 0x00000004
-
-/* NAND :: TIMING_1_CS5 :: tCS [15:12] */
-#define BCHP_NAND_TIMING_1_CS5_tCS_MASK 0x0000f000
-#define BCHP_NAND_TIMING_1_CS5_tCS_SHIFT 12
-#define BCHP_NAND_TIMING_1_CS5_tCS_DEFAULT 0x00000008
-
-/* NAND :: TIMING_1_CS5 :: tCLH [11:08] */
-#define BCHP_NAND_TIMING_1_CS5_tCLH_MASK 0x00000f00
-#define BCHP_NAND_TIMING_1_CS5_tCLH_SHIFT 8
-#define BCHP_NAND_TIMING_1_CS5_tCLH_DEFAULT 0x00000004
-
-/* NAND :: TIMING_1_CS5 :: tALH [07:04] */
-#define BCHP_NAND_TIMING_1_CS5_tALH_MASK 0x000000f0
-#define BCHP_NAND_TIMING_1_CS5_tALH_SHIFT 4
-#define BCHP_NAND_TIMING_1_CS5_tALH_DEFAULT 0x00000005
-
-/* NAND :: TIMING_1_CS5 :: tADL [03:00] */
-#define BCHP_NAND_TIMING_1_CS5_tADL_MASK 0x0000000f
-#define BCHP_NAND_TIMING_1_CS5_tADL_SHIFT 0
-#define BCHP_NAND_TIMING_1_CS5_tADL_DEFAULT 0x0000000b
-
-/***************************************************************************
- *TIMING_2_CS5 - Nand Flash Timing Parameters 2
- ***************************************************************************/
-/* NAND :: TIMING_2_CS5 :: CLK_SELECT [31:31] */
-#define BCHP_NAND_TIMING_2_CS5_CLK_SELECT_MASK 0x80000000
-#define BCHP_NAND_TIMING_2_CS5_CLK_SELECT_SHIFT 31
-#define BCHP_NAND_TIMING_2_CS5_CLK_SELECT_DEFAULT 0x00000000
-#define BCHP_NAND_TIMING_2_CS5_CLK_SELECT_CLK_108 0
-#define BCHP_NAND_TIMING_2_CS5_CLK_SELECT_CLK_216 1
-
-/* NAND :: TIMING_2_CS5 :: reserved0 [30:20] */
-#define BCHP_NAND_TIMING_2_CS5_reserved0_MASK 0x7ff00000
-#define BCHP_NAND_TIMING_2_CS5_reserved0_SHIFT 20
-
-/* NAND :: TIMING_2_CS5 :: tCCS [19:16] */
-#define BCHP_NAND_TIMING_2_CS5_tCCS_MASK 0x000f0000
-#define BCHP_NAND_TIMING_2_CS5_tCCS_SHIFT 16
-#define BCHP_NAND_TIMING_2_CS5_tCCS_DEFAULT 0x00000009
-
-/* NAND :: TIMING_2_CS5 :: reserved1 [15:13] */
-#define BCHP_NAND_TIMING_2_CS5_reserved1_MASK 0x0000e000
-#define BCHP_NAND_TIMING_2_CS5_reserved1_SHIFT 13
-
-/* NAND :: TIMING_2_CS5 :: tWB [12:09] */
-#define BCHP_NAND_TIMING_2_CS5_tWB_MASK 0x00001e00
-#define BCHP_NAND_TIMING_2_CS5_tWB_SHIFT 9
-#define BCHP_NAND_TIMING_2_CS5_tWB_DEFAULT 0x0000000f
-
-/* NAND :: TIMING_2_CS5 :: tWHR [08:04] */
-#define BCHP_NAND_TIMING_2_CS5_tWHR_MASK 0x000001f0
-#define BCHP_NAND_TIMING_2_CS5_tWHR_SHIFT 4
-#define BCHP_NAND_TIMING_2_CS5_tWHR_DEFAULT 0x00000009
-
-/* NAND :: TIMING_2_CS5 :: tREAD [03:00] */
-#define BCHP_NAND_TIMING_2_CS5_tREAD_MASK 0x0000000f
-#define BCHP_NAND_TIMING_2_CS5_tREAD_SHIFT 0
-#define BCHP_NAND_TIMING_2_CS5_tREAD_DEFAULT 0x00000006
-
-/***************************************************************************
- *ACC_CONTROL_CS6 - Nand Flash Access Control
- ***************************************************************************/
-/* NAND :: ACC_CONTROL_CS6 :: RD_ECC_EN [31:31] */
-#define BCHP_NAND_ACC_CONTROL_CS6_RD_ECC_EN_MASK 0x80000000
-#define BCHP_NAND_ACC_CONTROL_CS6_RD_ECC_EN_SHIFT 31
-#define BCHP_NAND_ACC_CONTROL_CS6_RD_ECC_EN_DEFAULT 0x00000001
-
-/* NAND :: ACC_CONTROL_CS6 :: WR_ECC_EN [30:30] */
-#define BCHP_NAND_ACC_CONTROL_CS6_WR_ECC_EN_MASK 0x40000000
-#define BCHP_NAND_ACC_CONTROL_CS6_WR_ECC_EN_SHIFT 30
-#define BCHP_NAND_ACC_CONTROL_CS6_WR_ECC_EN_DEFAULT 0x00000001
-
-/* NAND :: ACC_CONTROL_CS6 :: CE_CARE [29:29] */
-#define BCHP_NAND_ACC_CONTROL_CS6_CE_CARE_MASK 0x20000000
-#define BCHP_NAND_ACC_CONTROL_CS6_CE_CARE_SHIFT 29
-#define BCHP_NAND_ACC_CONTROL_CS6_CE_CARE_DEFAULT 0x00000000
-
-/* NAND :: ACC_CONTROL_CS6 :: reserved0 [28:28] */
-#define BCHP_NAND_ACC_CONTROL_CS6_reserved0_MASK 0x10000000
-#define BCHP_NAND_ACC_CONTROL_CS6_reserved0_SHIFT 28
-
-/* NAND :: ACC_CONTROL_CS6 :: RD_ERASED_ECC_EN [27:27] */
-#define BCHP_NAND_ACC_CONTROL_CS6_RD_ERASED_ECC_EN_MASK 0x08000000
-#define BCHP_NAND_ACC_CONTROL_CS6_RD_ERASED_ECC_EN_SHIFT 27
-#define BCHP_NAND_ACC_CONTROL_CS6_RD_ERASED_ECC_EN_DEFAULT 0x00000000
-
-/* NAND :: ACC_CONTROL_CS6 :: PARTIAL_PAGE_EN [26:26] */
-#define BCHP_NAND_ACC_CONTROL_CS6_PARTIAL_PAGE_EN_MASK 0x04000000
-#define BCHP_NAND_ACC_CONTROL_CS6_PARTIAL_PAGE_EN_SHIFT 26
-#define BCHP_NAND_ACC_CONTROL_CS6_PARTIAL_PAGE_EN_DEFAULT 0x00000000
-
-/* NAND :: ACC_CONTROL_CS6 :: WR_PREEMPT_EN [25:25] */
-#define BCHP_NAND_ACC_CONTROL_CS6_WR_PREEMPT_EN_MASK 0x02000000
-#define BCHP_NAND_ACC_CONTROL_CS6_WR_PREEMPT_EN_SHIFT 25
-#define BCHP_NAND_ACC_CONTROL_CS6_WR_PREEMPT_EN_DEFAULT 0x00000001
-
-/* NAND :: ACC_CONTROL_CS6 :: PAGE_HIT_EN [24:24] */
-#define BCHP_NAND_ACC_CONTROL_CS6_PAGE_HIT_EN_MASK 0x01000000
-#define BCHP_NAND_ACC_CONTROL_CS6_PAGE_HIT_EN_SHIFT 24
-#define BCHP_NAND_ACC_CONTROL_CS6_PAGE_HIT_EN_DEFAULT 0x00000001
-
-/* NAND :: ACC_CONTROL_CS6 :: PREFETCH_EN [23:23] */
-#define BCHP_NAND_ACC_CONTROL_CS6_PREFETCH_EN_MASK 0x00800000
-#define BCHP_NAND_ACC_CONTROL_CS6_PREFETCH_EN_SHIFT 23
-#define BCHP_NAND_ACC_CONTROL_CS6_PREFETCH_EN_DEFAULT 0x00000000
-
-/* NAND :: ACC_CONTROL_CS6 :: CACHE_MODE_EN [22:22] */
-#define BCHP_NAND_ACC_CONTROL_CS6_CACHE_MODE_EN_MASK 0x00400000
-#define BCHP_NAND_ACC_CONTROL_CS6_CACHE_MODE_EN_SHIFT 22
-#define BCHP_NAND_ACC_CONTROL_CS6_CACHE_MODE_EN_DEFAULT 0x00000000
-
-/* NAND :: ACC_CONTROL_CS6 :: reserved1 [21:21] */
-#define BCHP_NAND_ACC_CONTROL_CS6_reserved1_MASK 0x00200000
-#define BCHP_NAND_ACC_CONTROL_CS6_reserved1_SHIFT 21
-
-/* NAND :: ACC_CONTROL_CS6 :: ECC_LEVEL [20:16] */
-#define BCHP_NAND_ACC_CONTROL_CS6_ECC_LEVEL_MASK 0x001f0000
-#define BCHP_NAND_ACC_CONTROL_CS6_ECC_LEVEL_SHIFT 16
-#define BCHP_NAND_ACC_CONTROL_CS6_ECC_LEVEL_DEFAULT 0x0000000f
-
-/* NAND :: ACC_CONTROL_CS6 :: reserved2 [15:08] */
-#define BCHP_NAND_ACC_CONTROL_CS6_reserved2_MASK 0x0000ff00
-#define BCHP_NAND_ACC_CONTROL_CS6_reserved2_SHIFT 8
-
-/* NAND :: ACC_CONTROL_CS6 :: SECTOR_SIZE_1K [07:07] */
-#define BCHP_NAND_ACC_CONTROL_CS6_SECTOR_SIZE_1K_MASK 0x00000080
-#define BCHP_NAND_ACC_CONTROL_CS6_SECTOR_SIZE_1K_SHIFT 7
-#define BCHP_NAND_ACC_CONTROL_CS6_SECTOR_SIZE_1K_DEFAULT 0x00000000
-
-/* NAND :: ACC_CONTROL_CS6 :: SPARE_AREA_SIZE [06:00] */
-#define BCHP_NAND_ACC_CONTROL_CS6_SPARE_AREA_SIZE_MASK 0x0000007f
-#define BCHP_NAND_ACC_CONTROL_CS6_SPARE_AREA_SIZE_SHIFT 0
-#define BCHP_NAND_ACC_CONTROL_CS6_SPARE_AREA_SIZE_DEFAULT 0x00000010
-
-/***************************************************************************
- *CONFIG_EXT_CS6 - Nand Flash Config Extension
- ***************************************************************************/
-/* NAND :: CONFIG_EXT_CS6 :: reserved0 [31:12] */
-#define BCHP_NAND_CONFIG_EXT_CS6_reserved0_MASK 0xfffff000
-#define BCHP_NAND_CONFIG_EXT_CS6_reserved0_SHIFT 12
-
-/* NAND :: CONFIG_EXT_CS6 :: BLOCK_SIZE [11:04] */
-#define BCHP_NAND_CONFIG_EXT_CS6_BLOCK_SIZE_MASK 0x00000ff0
-#define BCHP_NAND_CONFIG_EXT_CS6_BLOCK_SIZE_SHIFT 4
-#define BCHP_NAND_CONFIG_EXT_CS6_BLOCK_SIZE_BK_SIZE_8KB 0
-#define BCHP_NAND_CONFIG_EXT_CS6_BLOCK_SIZE_BK_SIZE_16KB 1
-#define BCHP_NAND_CONFIG_EXT_CS6_BLOCK_SIZE_BK_SIZE_32KB 2
-#define BCHP_NAND_CONFIG_EXT_CS6_BLOCK_SIZE_BK_SIZE_64KB 3
-#define BCHP_NAND_CONFIG_EXT_CS6_BLOCK_SIZE_BK_SIZE_128KB 4
-#define BCHP_NAND_CONFIG_EXT_CS6_BLOCK_SIZE_BK_SIZE_256KB 5
-#define BCHP_NAND_CONFIG_EXT_CS6_BLOCK_SIZE_BK_SIZE_512KB 6
-#define BCHP_NAND_CONFIG_EXT_CS6_BLOCK_SIZE_BK_SIZE_1024KB 7
-#define BCHP_NAND_CONFIG_EXT_CS6_BLOCK_SIZE_BK_SIZE_2048KB 8
-#define BCHP_NAND_CONFIG_EXT_CS6_BLOCK_SIZE_BK_SIZE_4096KB 9
-#define BCHP_NAND_CONFIG_EXT_CS6_BLOCK_SIZE_BK_SIZE_8192KB 10
-
-/* NAND :: CONFIG_EXT_CS6 :: PAGE_SIZE [03:00] */
-#define BCHP_NAND_CONFIG_EXT_CS6_PAGE_SIZE_MASK 0x0000000f
-#define BCHP_NAND_CONFIG_EXT_CS6_PAGE_SIZE_SHIFT 0
-#define BCHP_NAND_CONFIG_EXT_CS6_PAGE_SIZE_PG_SIZE_512 0
-#define BCHP_NAND_CONFIG_EXT_CS6_PAGE_SIZE_PG_SIZE_1KB 1
-#define BCHP_NAND_CONFIG_EXT_CS6_PAGE_SIZE_PG_SIZE_2KB 2
-#define BCHP_NAND_CONFIG_EXT_CS6_PAGE_SIZE_PG_SIZE_4KB 3
-#define BCHP_NAND_CONFIG_EXT_CS6_PAGE_SIZE_PG_SIZE_8KB 4
-#define BCHP_NAND_CONFIG_EXT_CS6_PAGE_SIZE_PG_SIZE_16KB 5
-
-/***************************************************************************
- *CONFIG_CS6 - Nand Flash Config
- ***************************************************************************/
-/* NAND :: CONFIG_CS6 :: CONFIG_LOCK [31:31] */
-#define BCHP_NAND_CONFIG_CS6_CONFIG_LOCK_MASK 0x80000000
-#define BCHP_NAND_CONFIG_CS6_CONFIG_LOCK_SHIFT 31
-#define BCHP_NAND_CONFIG_CS6_CONFIG_LOCK_DEFAULT 0x00000000
-
-/* NAND :: CONFIG_CS6 :: reserved0 [30:28] */
-#define BCHP_NAND_CONFIG_CS6_reserved0_MASK 0x70000000
-#define BCHP_NAND_CONFIG_CS6_reserved0_SHIFT 28
-
-/* NAND :: CONFIG_CS6 :: DEVICE_SIZE [27:24] */
-#define BCHP_NAND_CONFIG_CS6_DEVICE_SIZE_MASK 0x0f000000
-#define BCHP_NAND_CONFIG_CS6_DEVICE_SIZE_SHIFT 24
-#define BCHP_NAND_CONFIG_CS6_DEVICE_SIZE_DVC_SIZE_4MB 0
-#define BCHP_NAND_CONFIG_CS6_DEVICE_SIZE_DVC_SIZE_8MB 1
-#define BCHP_NAND_CONFIG_CS6_DEVICE_SIZE_DVC_SIZE_16MB 2
-#define BCHP_NAND_CONFIG_CS6_DEVICE_SIZE_DVC_SIZE_32MB 3
-#define BCHP_NAND_CONFIG_CS6_DEVICE_SIZE_DVC_SIZE_64MB 4
-#define BCHP_NAND_CONFIG_CS6_DEVICE_SIZE_DVC_SIZE_128MB 5
-#define BCHP_NAND_CONFIG_CS6_DEVICE_SIZE_DVC_SIZE_256MB 6
-#define BCHP_NAND_CONFIG_CS6_DEVICE_SIZE_DVC_SIZE_512MB 7
-#define BCHP_NAND_CONFIG_CS6_DEVICE_SIZE_DVC_SIZE_1GB 8
-#define BCHP_NAND_CONFIG_CS6_DEVICE_SIZE_DVC_SIZE_2GB 9
-#define BCHP_NAND_CONFIG_CS6_DEVICE_SIZE_DVC_SIZE_4GB 10
-#define BCHP_NAND_CONFIG_CS6_DEVICE_SIZE_DVC_SIZE_8GB 11
-#define BCHP_NAND_CONFIG_CS6_DEVICE_SIZE_DVC_SIZE_16GB 12
-#define BCHP_NAND_CONFIG_CS6_DEVICE_SIZE_DVC_SIZE_32GB 13
-#define BCHP_NAND_CONFIG_CS6_DEVICE_SIZE_DVC_SIZE_64GB 14
-#define BCHP_NAND_CONFIG_CS6_DEVICE_SIZE_DVC_SIZE_128GB 15
-
-/* NAND :: CONFIG_CS6 :: DEVICE_WIDTH [23:23] */
-#define BCHP_NAND_CONFIG_CS6_DEVICE_WIDTH_MASK 0x00800000
-#define BCHP_NAND_CONFIG_CS6_DEVICE_WIDTH_SHIFT 23
-#define BCHP_NAND_CONFIG_CS6_DEVICE_WIDTH_DVC_WIDTH_8 0
-#define BCHP_NAND_CONFIG_CS6_DEVICE_WIDTH_DVC_WIDTH_16 1
-
-/* NAND :: CONFIG_CS6 :: reserved1 [22:19] */
-#define BCHP_NAND_CONFIG_CS6_reserved1_MASK 0x00780000
-#define BCHP_NAND_CONFIG_CS6_reserved1_SHIFT 19
-
-/* NAND :: CONFIG_CS6 :: FUL_ADR_BYTES [18:16] */
-#define BCHP_NAND_CONFIG_CS6_FUL_ADR_BYTES_MASK 0x00070000
-#define BCHP_NAND_CONFIG_CS6_FUL_ADR_BYTES_SHIFT 16
-
-/* NAND :: CONFIG_CS6 :: reserved2 [15:15] */
-#define BCHP_NAND_CONFIG_CS6_reserved2_MASK 0x00008000
-#define BCHP_NAND_CONFIG_CS6_reserved2_SHIFT 15
-
-/* NAND :: CONFIG_CS6 :: COL_ADR_BYTES [14:12] */
-#define BCHP_NAND_CONFIG_CS6_COL_ADR_BYTES_MASK 0x00007000
-#define BCHP_NAND_CONFIG_CS6_COL_ADR_BYTES_SHIFT 12
-
-/* NAND :: CONFIG_CS6 :: reserved3 [11:11] */
-#define BCHP_NAND_CONFIG_CS6_reserved3_MASK 0x00000800
-#define BCHP_NAND_CONFIG_CS6_reserved3_SHIFT 11
-
-/* NAND :: CONFIG_CS6 :: BLK_ADR_BYTES [10:08] */
-#define BCHP_NAND_CONFIG_CS6_BLK_ADR_BYTES_MASK 0x00000700
-#define BCHP_NAND_CONFIG_CS6_BLK_ADR_BYTES_SHIFT 8
-
-/* NAND :: CONFIG_CS6 :: reserved4 [07:00] */
-#define BCHP_NAND_CONFIG_CS6_reserved4_MASK 0x000000ff
-#define BCHP_NAND_CONFIG_CS6_reserved4_SHIFT 0
-
-/***************************************************************************
- *TIMING_1_CS6 - Nand Flash Timing Parameters 1
- ***************************************************************************/
-/* NAND :: TIMING_1_CS6 :: tWP [31:28] */
-#define BCHP_NAND_TIMING_1_CS6_tWP_MASK 0xf0000000
-#define BCHP_NAND_TIMING_1_CS6_tWP_SHIFT 28
-#define BCHP_NAND_TIMING_1_CS6_tWP_DEFAULT 0x00000006
-
-/* NAND :: TIMING_1_CS6 :: tWH [27:24] */
-#define BCHP_NAND_TIMING_1_CS6_tWH_MASK 0x0f000000
-#define BCHP_NAND_TIMING_1_CS6_tWH_SHIFT 24
-#define BCHP_NAND_TIMING_1_CS6_tWH_DEFAULT 0x00000005
-
-/* NAND :: TIMING_1_CS6 :: tRP [23:20] */
-#define BCHP_NAND_TIMING_1_CS6_tRP_MASK 0x00f00000
-#define BCHP_NAND_TIMING_1_CS6_tRP_SHIFT 20
-#define BCHP_NAND_TIMING_1_CS6_tRP_DEFAULT 0x00000007
-
-/* NAND :: TIMING_1_CS6 :: tREH [19:16] */
-#define BCHP_NAND_TIMING_1_CS6_tREH_MASK 0x000f0000
-#define BCHP_NAND_TIMING_1_CS6_tREH_SHIFT 16
-#define BCHP_NAND_TIMING_1_CS6_tREH_DEFAULT 0x00000004
-
-/* NAND :: TIMING_1_CS6 :: tCS [15:12] */
-#define BCHP_NAND_TIMING_1_CS6_tCS_MASK 0x0000f000
-#define BCHP_NAND_TIMING_1_CS6_tCS_SHIFT 12
-#define BCHP_NAND_TIMING_1_CS6_tCS_DEFAULT 0x00000008
-
-/* NAND :: TIMING_1_CS6 :: tCLH [11:08] */
-#define BCHP_NAND_TIMING_1_CS6_tCLH_MASK 0x00000f00
-#define BCHP_NAND_TIMING_1_CS6_tCLH_SHIFT 8
-#define BCHP_NAND_TIMING_1_CS6_tCLH_DEFAULT 0x00000004
-
-/* NAND :: TIMING_1_CS6 :: tALH [07:04] */
-#define BCHP_NAND_TIMING_1_CS6_tALH_MASK 0x000000f0
-#define BCHP_NAND_TIMING_1_CS6_tALH_SHIFT 4
-#define BCHP_NAND_TIMING_1_CS6_tALH_DEFAULT 0x00000005
-
-/* NAND :: TIMING_1_CS6 :: tADL [03:00] */
-#define BCHP_NAND_TIMING_1_CS6_tADL_MASK 0x0000000f
-#define BCHP_NAND_TIMING_1_CS6_tADL_SHIFT 0
-#define BCHP_NAND_TIMING_1_CS6_tADL_DEFAULT 0x0000000b
-
-/***************************************************************************
- *TIMING_2_CS6 - Nand Flash Timing Parameters 2
- ***************************************************************************/
-/* NAND :: TIMING_2_CS6 :: CLK_SELECT [31:31] */
-#define BCHP_NAND_TIMING_2_CS6_CLK_SELECT_MASK 0x80000000
-#define BCHP_NAND_TIMING_2_CS6_CLK_SELECT_SHIFT 31
-#define BCHP_NAND_TIMING_2_CS6_CLK_SELECT_DEFAULT 0x00000000
-#define BCHP_NAND_TIMING_2_CS6_CLK_SELECT_CLK_108 0
-#define BCHP_NAND_TIMING_2_CS6_CLK_SELECT_CLK_216 1
-
-/* NAND :: TIMING_2_CS6 :: reserved0 [30:20] */
-#define BCHP_NAND_TIMING_2_CS6_reserved0_MASK 0x7ff00000
-#define BCHP_NAND_TIMING_2_CS6_reserved0_SHIFT 20
-
-/* NAND :: TIMING_2_CS6 :: tCCS [19:16] */
-#define BCHP_NAND_TIMING_2_CS6_tCCS_MASK 0x000f0000
-#define BCHP_NAND_TIMING_2_CS6_tCCS_SHIFT 16
-#define BCHP_NAND_TIMING_2_CS6_tCCS_DEFAULT 0x00000009
-
-/* NAND :: TIMING_2_CS6 :: reserved1 [15:13] */
-#define BCHP_NAND_TIMING_2_CS6_reserved1_MASK 0x0000e000
-#define BCHP_NAND_TIMING_2_CS6_reserved1_SHIFT 13
-
-/* NAND :: TIMING_2_CS6 :: tWB [12:09] */
-#define BCHP_NAND_TIMING_2_CS6_tWB_MASK 0x00001e00
-#define BCHP_NAND_TIMING_2_CS6_tWB_SHIFT 9
-#define BCHP_NAND_TIMING_2_CS6_tWB_DEFAULT 0x0000000f
-
-/* NAND :: TIMING_2_CS6 :: tWHR [08:04] */
-#define BCHP_NAND_TIMING_2_CS6_tWHR_MASK 0x000001f0
-#define BCHP_NAND_TIMING_2_CS6_tWHR_SHIFT 4
-#define BCHP_NAND_TIMING_2_CS6_tWHR_DEFAULT 0x00000009
-
-/* NAND :: TIMING_2_CS6 :: tREAD [03:00] */
-#define BCHP_NAND_TIMING_2_CS6_tREAD_MASK 0x0000000f
-#define BCHP_NAND_TIMING_2_CS6_tREAD_SHIFT 0
-#define BCHP_NAND_TIMING_2_CS6_tREAD_DEFAULT 0x00000006
-
-/***************************************************************************
- *CORR_STAT_THRESHOLD - Correctable Error Reporting Threshold
- ***************************************************************************/
-/* NAND :: CORR_STAT_THRESHOLD :: reserved0 [31:30] */
-#define BCHP_NAND_CORR_STAT_THRESHOLD_reserved0_MASK 0xc0000000
-#define BCHP_NAND_CORR_STAT_THRESHOLD_reserved0_SHIFT 30
-
-/* NAND :: CORR_STAT_THRESHOLD :: CORR_STAT_THRESHOLD_CS4 [29:24] */
-#define BCHP_NAND_CORR_STAT_THRESHOLD_CORR_STAT_THRESHOLD_CS4_MASK 0x3f000000
-#define BCHP_NAND_CORR_STAT_THRESHOLD_CORR_STAT_THRESHOLD_CS4_SHIFT 24
-#define BCHP_NAND_CORR_STAT_THRESHOLD_CORR_STAT_THRESHOLD_CS4_DEFAULT 0x00000001
-
-/* NAND :: CORR_STAT_THRESHOLD :: CORR_STAT_THRESHOLD_CS3 [23:18] */
-#define BCHP_NAND_CORR_STAT_THRESHOLD_CORR_STAT_THRESHOLD_CS3_MASK 0x00fc0000
-#define BCHP_NAND_CORR_STAT_THRESHOLD_CORR_STAT_THRESHOLD_CS3_SHIFT 18
-#define BCHP_NAND_CORR_STAT_THRESHOLD_CORR_STAT_THRESHOLD_CS3_DEFAULT 0x00000001
-
-/* NAND :: CORR_STAT_THRESHOLD :: CORR_STAT_THRESHOLD_CS2 [17:12] */
-#define BCHP_NAND_CORR_STAT_THRESHOLD_CORR_STAT_THRESHOLD_CS2_MASK 0x0003f000
-#define BCHP_NAND_CORR_STAT_THRESHOLD_CORR_STAT_THRESHOLD_CS2_SHIFT 12
-#define BCHP_NAND_CORR_STAT_THRESHOLD_CORR_STAT_THRESHOLD_CS2_DEFAULT 0x00000001
-
-/* NAND :: CORR_STAT_THRESHOLD :: CORR_STAT_THRESHOLD_CS1 [11:06] */
-#define BCHP_NAND_CORR_STAT_THRESHOLD_CORR_STAT_THRESHOLD_CS1_MASK 0x00000fc0
-#define BCHP_NAND_CORR_STAT_THRESHOLD_CORR_STAT_THRESHOLD_CS1_SHIFT 6
-#define BCHP_NAND_CORR_STAT_THRESHOLD_CORR_STAT_THRESHOLD_CS1_DEFAULT 0x00000001
-
-/* NAND :: CORR_STAT_THRESHOLD :: CORR_STAT_THRESHOLD_CS0 [05:00] */
-#define BCHP_NAND_CORR_STAT_THRESHOLD_CORR_STAT_THRESHOLD_CS0_MASK 0x0000003f
-#define BCHP_NAND_CORR_STAT_THRESHOLD_CORR_STAT_THRESHOLD_CS0_SHIFT 0
-#define BCHP_NAND_CORR_STAT_THRESHOLD_CORR_STAT_THRESHOLD_CS0_DEFAULT 0x00000001
-
-/***************************************************************************
- *CORR_STAT_THRESHOLD_EXT - Correctable Error Reporting Threshold
- ***************************************************************************/
-/* NAND :: CORR_STAT_THRESHOLD_EXT :: reserved0 [31:12] */
-#define BCHP_NAND_CORR_STAT_THRESHOLD_EXT_reserved0_MASK 0xfffff000
-#define BCHP_NAND_CORR_STAT_THRESHOLD_EXT_reserved0_SHIFT 12
-
-/* NAND :: CORR_STAT_THRESHOLD_EXT :: CORR_STAT_THRESHOLD_CS6 [11:06] */
-#define BCHP_NAND_CORR_STAT_THRESHOLD_EXT_CORR_STAT_THRESHOLD_CS6_MASK 0x00000fc0
-#define BCHP_NAND_CORR_STAT_THRESHOLD_EXT_CORR_STAT_THRESHOLD_CS6_SHIFT 6
-#define BCHP_NAND_CORR_STAT_THRESHOLD_EXT_CORR_STAT_THRESHOLD_CS6_DEFAULT 0x00000001
-
-/* NAND :: CORR_STAT_THRESHOLD_EXT :: CORR_STAT_THRESHOLD_CS5 [05:00] */
-#define BCHP_NAND_CORR_STAT_THRESHOLD_EXT_CORR_STAT_THRESHOLD_CS5_MASK 0x0000003f
-#define BCHP_NAND_CORR_STAT_THRESHOLD_EXT_CORR_STAT_THRESHOLD_CS5_SHIFT 0
-#define BCHP_NAND_CORR_STAT_THRESHOLD_EXT_CORR_STAT_THRESHOLD_CS5_DEFAULT 0x00000001
-
-/***************************************************************************
- *BLK_WR_PROTECT - Block Write Protect Enable and Size for EBI_CS0b
- ***************************************************************************/
-/* NAND :: BLK_WR_PROTECT :: BLK_END_ADDR [31:00] */
-#define BCHP_NAND_BLK_WR_PROTECT_BLK_END_ADDR_MASK 0xffffffff
-#define BCHP_NAND_BLK_WR_PROTECT_BLK_END_ADDR_SHIFT 0
-#define BCHP_NAND_BLK_WR_PROTECT_BLK_END_ADDR_DEFAULT 0x00000000
-
-/***************************************************************************
- *MULTIPLANE_OPCODES_1 - Nand Flash Multiplane Customized Opcodes
- ***************************************************************************/
-/* NAND :: MULTIPLANE_OPCODES_1 :: ERASE_CYC2_OPCODE [31:24] */
-#define BCHP_NAND_MULTIPLANE_OPCODES_1_ERASE_CYC2_OPCODE_MASK 0xff000000
-#define BCHP_NAND_MULTIPLANE_OPCODES_1_ERASE_CYC2_OPCODE_SHIFT 24
-#define BCHP_NAND_MULTIPLANE_OPCODES_1_ERASE_CYC2_OPCODE_DEFAULT 0x000000d1
-
-/* NAND :: MULTIPLANE_OPCODES_1 :: READ_STATUS_OPCODE [23:16] */
-#define BCHP_NAND_MULTIPLANE_OPCODES_1_READ_STATUS_OPCODE_MASK 0x00ff0000
-#define BCHP_NAND_MULTIPLANE_OPCODES_1_READ_STATUS_OPCODE_SHIFT 16
-#define BCHP_NAND_MULTIPLANE_OPCODES_1_READ_STATUS_OPCODE_DEFAULT 0x00000070
-
-/* NAND :: MULTIPLANE_OPCODES_1 :: PROG_ODD_PLANE_OPCODE [15:08] */
-#define BCHP_NAND_MULTIPLANE_OPCODES_1_PROG_ODD_PLANE_OPCODE_MASK 0x0000ff00
-#define BCHP_NAND_MULTIPLANE_OPCODES_1_PROG_ODD_PLANE_OPCODE_SHIFT 8
-#define BCHP_NAND_MULTIPLANE_OPCODES_1_PROG_ODD_PLANE_OPCODE_DEFAULT 0x00000080
-
-/* NAND :: MULTIPLANE_OPCODES_1 :: PROG_TR_OPCODE [07:00] */
-#define BCHP_NAND_MULTIPLANE_OPCODES_1_PROG_TR_OPCODE_MASK 0x000000ff
-#define BCHP_NAND_MULTIPLANE_OPCODES_1_PROG_TR_OPCODE_SHIFT 0
-#define BCHP_NAND_MULTIPLANE_OPCODES_1_PROG_TR_OPCODE_DEFAULT 0x00000010
-
-/***************************************************************************
- *MULTIPLANE_OPCODES_2 - Nand Flash Multiplane Customized Opcodes
- ***************************************************************************/
-/* NAND :: MULTIPLANE_OPCODES_2 :: PROG_CACHE_TR_OPCODE [31:24] */
-#define BCHP_NAND_MULTIPLANE_OPCODES_2_PROG_CACHE_TR_OPCODE_MASK 0xff000000
-#define BCHP_NAND_MULTIPLANE_OPCODES_2_PROG_CACHE_TR_OPCODE_SHIFT 24
-#define BCHP_NAND_MULTIPLANE_OPCODES_2_PROG_CACHE_TR_OPCODE_DEFAULT 0x00000015
-
-/* NAND :: MULTIPLANE_OPCODES_2 :: TWO_PLANE_READ_STATUS_OPCODE [23:16] */
-#define BCHP_NAND_MULTIPLANE_OPCODES_2_TWO_PLANE_READ_STATUS_OPCODE_MASK 0x00ff0000
-#define BCHP_NAND_MULTIPLANE_OPCODES_2_TWO_PLANE_READ_STATUS_OPCODE_SHIFT 16
-#define BCHP_NAND_MULTIPLANE_OPCODES_2_TWO_PLANE_READ_STATUS_OPCODE_DEFAULT 0x00000078
-
-/* NAND :: MULTIPLANE_OPCODES_2 :: READ_OPCODE [15:08] */
-#define BCHP_NAND_MULTIPLANE_OPCODES_2_READ_OPCODE_MASK 0x0000ff00
-#define BCHP_NAND_MULTIPLANE_OPCODES_2_READ_OPCODE_SHIFT 8
-#define BCHP_NAND_MULTIPLANE_OPCODES_2_READ_OPCODE_DEFAULT 0x00000000
-
-/* NAND :: MULTIPLANE_OPCODES_2 :: READ_RAND_OPCODE [07:00] */
-#define BCHP_NAND_MULTIPLANE_OPCODES_2_READ_RAND_OPCODE_MASK 0x000000ff
-#define BCHP_NAND_MULTIPLANE_OPCODES_2_READ_RAND_OPCODE_SHIFT 0
-#define BCHP_NAND_MULTIPLANE_OPCODES_2_READ_RAND_OPCODE_DEFAULT 0x00000000
-
-/***************************************************************************
- *MULTIPLANE_CTRL - Nand Flash Multiplane Control
- ***************************************************************************/
-/* NAND :: MULTIPLANE_CTRL :: ERASE_CYC2_OP_ENABLE [31:31] */
-#define BCHP_NAND_MULTIPLANE_CTRL_ERASE_CYC2_OP_ENABLE_MASK 0x80000000
-#define BCHP_NAND_MULTIPLANE_CTRL_ERASE_CYC2_OP_ENABLE_SHIFT 31
-#define BCHP_NAND_MULTIPLANE_CTRL_ERASE_CYC2_OP_ENABLE_DEFAULT 0x00000000
-
-/* NAND :: MULTIPLANE_CTRL :: READ_ADR_SIZE [30:30] */
-#define BCHP_NAND_MULTIPLANE_CTRL_READ_ADR_SIZE_MASK 0x40000000
-#define BCHP_NAND_MULTIPLANE_CTRL_READ_ADR_SIZE_SHIFT 30
-#define BCHP_NAND_MULTIPLANE_CTRL_READ_ADR_SIZE_DEFAULT 0x00000000
-
-/* NAND :: MULTIPLANE_CTRL :: READ_CYC_ADR_FLAG [29:29] */
-#define BCHP_NAND_MULTIPLANE_CTRL_READ_CYC_ADR_FLAG_MASK 0x20000000
-#define BCHP_NAND_MULTIPLANE_CTRL_READ_CYC_ADR_FLAG_SHIFT 29
-#define BCHP_NAND_MULTIPLANE_CTRL_READ_CYC_ADR_FLAG_DEFAULT 0x00000000
-
-/* NAND :: MULTIPLANE_CTRL :: READ_NEXT_PAGE_FLAG [28:28] */
-#define BCHP_NAND_MULTIPLANE_CTRL_READ_NEXT_PAGE_FLAG_MASK 0x10000000
-#define BCHP_NAND_MULTIPLANE_CTRL_READ_NEXT_PAGE_FLAG_SHIFT 28
-#define BCHP_NAND_MULTIPLANE_CTRL_READ_NEXT_PAGE_FLAG_DEFAULT 0x00000000
-
-/* NAND :: MULTIPLANE_CTRL :: reserved0 [27:00] */
-#define BCHP_NAND_MULTIPLANE_CTRL_reserved0_MASK 0x0fffffff
-#define BCHP_NAND_MULTIPLANE_CTRL_reserved0_SHIFT 0
-
-/***************************************************************************
- *UNCORR_ERROR_COUNT - Read Uncorrectable Event Count
- ***************************************************************************/
-/* NAND :: UNCORR_ERROR_COUNT :: UNCORR_ERROR_COUNT [31:00] */
-#define BCHP_NAND_UNCORR_ERROR_COUNT_UNCORR_ERROR_COUNT_MASK 0xffffffff
-#define BCHP_NAND_UNCORR_ERROR_COUNT_UNCORR_ERROR_COUNT_SHIFT 0
-#define BCHP_NAND_UNCORR_ERROR_COUNT_UNCORR_ERROR_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *CORR_ERROR_COUNT - Read Error Count
- ***************************************************************************/
-/* NAND :: CORR_ERROR_COUNT :: CORR_ERROR_COUNT [31:00] */
-#define BCHP_NAND_CORR_ERROR_COUNT_CORR_ERROR_COUNT_MASK 0xffffffff
-#define BCHP_NAND_CORR_ERROR_COUNT_CORR_ERROR_COUNT_SHIFT 0
-#define BCHP_NAND_CORR_ERROR_COUNT_CORR_ERROR_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *READ_ERROR_COUNT - Read Error Count
- ***************************************************************************/
-/* NAND :: READ_ERROR_COUNT :: READ_ERROR_COUNT [31:00] */
-#define BCHP_NAND_READ_ERROR_COUNT_READ_ERROR_COUNT_MASK 0xffffffff
-#define BCHP_NAND_READ_ERROR_COUNT_READ_ERROR_COUNT_SHIFT 0
-#define BCHP_NAND_READ_ERROR_COUNT_READ_ERROR_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *BLOCK_LOCK_STATUS - Nand Flash Block Lock Status
- ***************************************************************************/
-/* NAND :: BLOCK_LOCK_STATUS :: reserved0 [31:08] */
-#define BCHP_NAND_BLOCK_LOCK_STATUS_reserved0_MASK 0xffffff00
-#define BCHP_NAND_BLOCK_LOCK_STATUS_reserved0_SHIFT 8
-
-/* NAND :: BLOCK_LOCK_STATUS :: STATUS [07:00] */
-#define BCHP_NAND_BLOCK_LOCK_STATUS_STATUS_MASK 0x000000ff
-#define BCHP_NAND_BLOCK_LOCK_STATUS_STATUS_SHIFT 0
-#define BCHP_NAND_BLOCK_LOCK_STATUS_STATUS_DEFAULT 0x00000000
-
-/***************************************************************************
- *ECC_CORR_EXT_ADDR - ECC Correctable Error Extended Address
- ***************************************************************************/
-/* NAND :: ECC_CORR_EXT_ADDR :: reserved0 [31:19] */
-#define BCHP_NAND_ECC_CORR_EXT_ADDR_reserved0_MASK 0xfff80000
-#define BCHP_NAND_ECC_CORR_EXT_ADDR_reserved0_SHIFT 19
-
-/* NAND :: ECC_CORR_EXT_ADDR :: CS_SEL [18:16] */
-#define BCHP_NAND_ECC_CORR_EXT_ADDR_CS_SEL_MASK 0x00070000
-#define BCHP_NAND_ECC_CORR_EXT_ADDR_CS_SEL_SHIFT 16
-#define BCHP_NAND_ECC_CORR_EXT_ADDR_CS_SEL_DEFAULT 0x00000000
-
-/* NAND :: ECC_CORR_EXT_ADDR :: EXT_ADDRESS [15:00] */
-#define BCHP_NAND_ECC_CORR_EXT_ADDR_EXT_ADDRESS_MASK 0x0000ffff
-#define BCHP_NAND_ECC_CORR_EXT_ADDR_EXT_ADDRESS_SHIFT 0
-#define BCHP_NAND_ECC_CORR_EXT_ADDR_EXT_ADDRESS_DEFAULT 0x00000000
-
-/***************************************************************************
- *ECC_CORR_ADDR - ECC Correctable Error Address
- ***************************************************************************/
-/* NAND :: ECC_CORR_ADDR :: ADDRESS [31:00] */
-#define BCHP_NAND_ECC_CORR_ADDR_ADDRESS_MASK 0xffffffff
-#define BCHP_NAND_ECC_CORR_ADDR_ADDRESS_SHIFT 0
-#define BCHP_NAND_ECC_CORR_ADDR_ADDRESS_DEFAULT 0x00000000
-
-/***************************************************************************
- *ECC_UNC_EXT_ADDR - ECC Uncorrectable Error Extended Address
- ***************************************************************************/
-/* NAND :: ECC_UNC_EXT_ADDR :: reserved0 [31:19] */
-#define BCHP_NAND_ECC_UNC_EXT_ADDR_reserved0_MASK 0xfff80000
-#define BCHP_NAND_ECC_UNC_EXT_ADDR_reserved0_SHIFT 19
-
-/* NAND :: ECC_UNC_EXT_ADDR :: CS_SEL [18:16] */
-#define BCHP_NAND_ECC_UNC_EXT_ADDR_CS_SEL_MASK 0x00070000
-#define BCHP_NAND_ECC_UNC_EXT_ADDR_CS_SEL_SHIFT 16
-#define BCHP_NAND_ECC_UNC_EXT_ADDR_CS_SEL_DEFAULT 0x00000000
-
-/* NAND :: ECC_UNC_EXT_ADDR :: EXT_ADDRESS [15:00] */
-#define BCHP_NAND_ECC_UNC_EXT_ADDR_EXT_ADDRESS_MASK 0x0000ffff
-#define BCHP_NAND_ECC_UNC_EXT_ADDR_EXT_ADDRESS_SHIFT 0
-#define BCHP_NAND_ECC_UNC_EXT_ADDR_EXT_ADDRESS_DEFAULT 0x00000000
-
-/***************************************************************************
- *ECC_UNC_ADDR - ECC Uncorrectable Error Address
- ***************************************************************************/
-/* NAND :: ECC_UNC_ADDR :: ADDRESS [31:00] */
-#define BCHP_NAND_ECC_UNC_ADDR_ADDRESS_MASK 0xffffffff
-#define BCHP_NAND_ECC_UNC_ADDR_ADDRESS_SHIFT 0
-#define BCHP_NAND_ECC_UNC_ADDR_ADDRESS_DEFAULT 0x00000000
-
-/***************************************************************************
- *FLASH_READ_EXT_ADDR - Flash Read Data Extended Address
- ***************************************************************************/
-/* NAND :: FLASH_READ_EXT_ADDR :: reserved0 [31:19] */
-#define BCHP_NAND_FLASH_READ_EXT_ADDR_reserved0_MASK 0xfff80000
-#define BCHP_NAND_FLASH_READ_EXT_ADDR_reserved0_SHIFT 19
-
-/* NAND :: FLASH_READ_EXT_ADDR :: CS_SEL [18:16] */
-#define BCHP_NAND_FLASH_READ_EXT_ADDR_CS_SEL_MASK 0x00070000
-#define BCHP_NAND_FLASH_READ_EXT_ADDR_CS_SEL_SHIFT 16
-#define BCHP_NAND_FLASH_READ_EXT_ADDR_CS_SEL_DEFAULT 0x00000000
-
-/* NAND :: FLASH_READ_EXT_ADDR :: EXT_ADDRESS [15:00] */
-#define BCHP_NAND_FLASH_READ_EXT_ADDR_EXT_ADDRESS_MASK 0x0000ffff
-#define BCHP_NAND_FLASH_READ_EXT_ADDR_EXT_ADDRESS_SHIFT 0
-#define BCHP_NAND_FLASH_READ_EXT_ADDR_EXT_ADDRESS_DEFAULT 0x00000000
-
-/***************************************************************************
- *FLASH_READ_ADDR - Flash Read Data Address
- ***************************************************************************/
-/* NAND :: FLASH_READ_ADDR :: ADDRESS [31:00] */
-#define BCHP_NAND_FLASH_READ_ADDR_ADDRESS_MASK 0xffffffff
-#define BCHP_NAND_FLASH_READ_ADDR_ADDRESS_SHIFT 0
-#define BCHP_NAND_FLASH_READ_ADDR_ADDRESS_DEFAULT 0x00000000
-
-/***************************************************************************
- *PROGRAM_PAGE_EXT_ADDR - Page Program Extended Address
- ***************************************************************************/
-/* NAND :: PROGRAM_PAGE_EXT_ADDR :: reserved0 [31:19] */
-#define BCHP_NAND_PROGRAM_PAGE_EXT_ADDR_reserved0_MASK 0xfff80000
-#define BCHP_NAND_PROGRAM_PAGE_EXT_ADDR_reserved0_SHIFT 19
-
-/* NAND :: PROGRAM_PAGE_EXT_ADDR :: CS_SEL [18:16] */
-#define BCHP_NAND_PROGRAM_PAGE_EXT_ADDR_CS_SEL_MASK 0x00070000
-#define BCHP_NAND_PROGRAM_PAGE_EXT_ADDR_CS_SEL_SHIFT 16
-#define BCHP_NAND_PROGRAM_PAGE_EXT_ADDR_CS_SEL_DEFAULT 0x00000000
-
-/* NAND :: PROGRAM_PAGE_EXT_ADDR :: EXT_ADDRESS [15:00] */
-#define BCHP_NAND_PROGRAM_PAGE_EXT_ADDR_EXT_ADDRESS_MASK 0x0000ffff
-#define BCHP_NAND_PROGRAM_PAGE_EXT_ADDR_EXT_ADDRESS_SHIFT 0
-#define BCHP_NAND_PROGRAM_PAGE_EXT_ADDR_EXT_ADDRESS_DEFAULT 0x00000000
-
-/***************************************************************************
- *PROGRAM_PAGE_ADDR - Page Program Address
- ***************************************************************************/
-/* NAND :: PROGRAM_PAGE_ADDR :: ADDRESS [31:00] */
-#define BCHP_NAND_PROGRAM_PAGE_ADDR_ADDRESS_MASK 0xffffffff
-#define BCHP_NAND_PROGRAM_PAGE_ADDR_ADDRESS_SHIFT 0
-#define BCHP_NAND_PROGRAM_PAGE_ADDR_ADDRESS_DEFAULT 0x00000000
-
-/***************************************************************************
- *COPY_BACK_EXT_ADDR - Copy Back Extended Address
- ***************************************************************************/
-/* NAND :: COPY_BACK_EXT_ADDR :: reserved0 [31:19] */
-#define BCHP_NAND_COPY_BACK_EXT_ADDR_reserved0_MASK 0xfff80000
-#define BCHP_NAND_COPY_BACK_EXT_ADDR_reserved0_SHIFT 19
-
-/* NAND :: COPY_BACK_EXT_ADDR :: CS_SEL [18:16] */
-#define BCHP_NAND_COPY_BACK_EXT_ADDR_CS_SEL_MASK 0x00070000
-#define BCHP_NAND_COPY_BACK_EXT_ADDR_CS_SEL_SHIFT 16
-#define BCHP_NAND_COPY_BACK_EXT_ADDR_CS_SEL_DEFAULT 0x00000000
-
-/* NAND :: COPY_BACK_EXT_ADDR :: EXT_ADDRESS [15:00] */
-#define BCHP_NAND_COPY_BACK_EXT_ADDR_EXT_ADDRESS_MASK 0x0000ffff
-#define BCHP_NAND_COPY_BACK_EXT_ADDR_EXT_ADDRESS_SHIFT 0
-#define BCHP_NAND_COPY_BACK_EXT_ADDR_EXT_ADDRESS_DEFAULT 0x00000000
-
-/***************************************************************************
- *COPY_BACK_ADDR - Copy Back Address
- ***************************************************************************/
-/* NAND :: COPY_BACK_ADDR :: ADDRESS [31:00] */
-#define BCHP_NAND_COPY_BACK_ADDR_ADDRESS_MASK 0xffffffff
-#define BCHP_NAND_COPY_BACK_ADDR_ADDRESS_SHIFT 0
-#define BCHP_NAND_COPY_BACK_ADDR_ADDRESS_DEFAULT 0x00000000
-
-/***************************************************************************
- *BLOCK_ERASE_EXT_ADDR - Block Erase Extended Address
- ***************************************************************************/
-/* NAND :: BLOCK_ERASE_EXT_ADDR :: reserved0 [31:19] */
-#define BCHP_NAND_BLOCK_ERASE_EXT_ADDR_reserved0_MASK 0xfff80000
-#define BCHP_NAND_BLOCK_ERASE_EXT_ADDR_reserved0_SHIFT 19
-
-/* NAND :: BLOCK_ERASE_EXT_ADDR :: CS_SEL [18:16] */
-#define BCHP_NAND_BLOCK_ERASE_EXT_ADDR_CS_SEL_MASK 0x00070000
-#define BCHP_NAND_BLOCK_ERASE_EXT_ADDR_CS_SEL_SHIFT 16
-#define BCHP_NAND_BLOCK_ERASE_EXT_ADDR_CS_SEL_DEFAULT 0x00000000
-
-/* NAND :: BLOCK_ERASE_EXT_ADDR :: EXT_ADDRESS [15:00] */
-#define BCHP_NAND_BLOCK_ERASE_EXT_ADDR_EXT_ADDRESS_MASK 0x0000ffff
-#define BCHP_NAND_BLOCK_ERASE_EXT_ADDR_EXT_ADDRESS_SHIFT 0
-#define BCHP_NAND_BLOCK_ERASE_EXT_ADDR_EXT_ADDRESS_DEFAULT 0x00000000
-
-/***************************************************************************
- *BLOCK_ERASE_ADDR - Block Erase Address
- ***************************************************************************/
-/* NAND :: BLOCK_ERASE_ADDR :: ADDRESS [31:00] */
-#define BCHP_NAND_BLOCK_ERASE_ADDR_ADDRESS_MASK 0xffffffff
-#define BCHP_NAND_BLOCK_ERASE_ADDR_ADDRESS_SHIFT 0
-#define BCHP_NAND_BLOCK_ERASE_ADDR_ADDRESS_DEFAULT 0x00000000
-
-/***************************************************************************
- *INV_READ_EXT_ADDR - Flash Invalid Data Extended Address
- ***************************************************************************/
-/* NAND :: INV_READ_EXT_ADDR :: reserved0 [31:19] */
-#define BCHP_NAND_INV_READ_EXT_ADDR_reserved0_MASK 0xfff80000
-#define BCHP_NAND_INV_READ_EXT_ADDR_reserved0_SHIFT 19
-
-/* NAND :: INV_READ_EXT_ADDR :: CS_SEL [18:16] */
-#define BCHP_NAND_INV_READ_EXT_ADDR_CS_SEL_MASK 0x00070000
-#define BCHP_NAND_INV_READ_EXT_ADDR_CS_SEL_SHIFT 16
-#define BCHP_NAND_INV_READ_EXT_ADDR_CS_SEL_DEFAULT 0x00000000
-
-/* NAND :: INV_READ_EXT_ADDR :: EXT_ADDRESS [15:00] */
-#define BCHP_NAND_INV_READ_EXT_ADDR_EXT_ADDRESS_MASK 0x0000ffff
-#define BCHP_NAND_INV_READ_EXT_ADDR_EXT_ADDRESS_SHIFT 0
-#define BCHP_NAND_INV_READ_EXT_ADDR_EXT_ADDRESS_DEFAULT 0x00000000
-
-/***************************************************************************
- *INV_READ_ADDR - Flash Invalid Data Address
- ***************************************************************************/
-/* NAND :: INV_READ_ADDR :: ADDRESS [31:00] */
-#define BCHP_NAND_INV_READ_ADDR_ADDRESS_MASK 0xffffffff
-#define BCHP_NAND_INV_READ_ADDR_ADDRESS_SHIFT 0
-#define BCHP_NAND_INV_READ_ADDR_ADDRESS_DEFAULT 0x00000000
-
-/***************************************************************************
- *INIT_STATUS - Initialization status
- ***************************************************************************/
-/* NAND :: INIT_STATUS :: ONFI_INIT_DONE [31:31] */
-#define BCHP_NAND_INIT_STATUS_ONFI_INIT_DONE_MASK 0x80000000
-#define BCHP_NAND_INIT_STATUS_ONFI_INIT_DONE_SHIFT 31
-
-/* NAND :: INIT_STATUS :: DEVICE_ID_INIT_DONE [30:30] */
-#define BCHP_NAND_INIT_STATUS_DEVICE_ID_INIT_DONE_MASK 0x40000000
-#define BCHP_NAND_INIT_STATUS_DEVICE_ID_INIT_DONE_SHIFT 30
-
-/* NAND :: INIT_STATUS :: INIT_SUCCESS [29:29] */
-#define BCHP_NAND_INIT_STATUS_INIT_SUCCESS_MASK 0x20000000
-#define BCHP_NAND_INIT_STATUS_INIT_SUCCESS_SHIFT 29
-
-/* NAND :: INIT_STATUS :: INIT_FAIL [28:28] */
-#define BCHP_NAND_INIT_STATUS_INIT_FAIL_MASK 0x10000000
-#define BCHP_NAND_INIT_STATUS_INIT_FAIL_SHIFT 28
-
-/* NAND :: INIT_STATUS :: INIT_BLANK [27:27] */
-#define BCHP_NAND_INIT_STATUS_INIT_BLANK_MASK 0x08000000
-#define BCHP_NAND_INIT_STATUS_INIT_BLANK_SHIFT 27
-
-/* NAND :: INIT_STATUS :: INIT_TIMEOUT [26:26] */
-#define BCHP_NAND_INIT_STATUS_INIT_TIMEOUT_MASK 0x04000000
-#define BCHP_NAND_INIT_STATUS_INIT_TIMEOUT_SHIFT 26
-
-/* NAND :: INIT_STATUS :: INIT_UNC_ERROR [25:25] */
-#define BCHP_NAND_INIT_STATUS_INIT_UNC_ERROR_MASK 0x02000000
-#define BCHP_NAND_INIT_STATUS_INIT_UNC_ERROR_SHIFT 25
-
-/* NAND :: INIT_STATUS :: INIT_CORR_ERROR [24:24] */
-#define BCHP_NAND_INIT_STATUS_INIT_CORR_ERROR_MASK 0x01000000
-#define BCHP_NAND_INIT_STATUS_INIT_CORR_ERROR_SHIFT 24
-
-/* NAND :: INIT_STATUS :: PARAMETER_READY [23:23] */
-#define BCHP_NAND_INIT_STATUS_PARAMETER_READY_MASK 0x00800000
-#define BCHP_NAND_INIT_STATUS_PARAMETER_READY_SHIFT 23
-
-/* NAND :: INIT_STATUS :: AUTHENTICATION_FAIL [22:22] */
-#define BCHP_NAND_INIT_STATUS_AUTHENTICATION_FAIL_MASK 0x00400000
-#define BCHP_NAND_INIT_STATUS_AUTHENTICATION_FAIL_SHIFT 22
-
-/* NAND :: INIT_STATUS :: reserved0 [21:00] */
-#define BCHP_NAND_INIT_STATUS_reserved0_MASK 0x003fffff
-#define BCHP_NAND_INIT_STATUS_reserved0_SHIFT 0
-
-/***************************************************************************
- *ONFI_STATUS - ONFI Status
- ***************************************************************************/
-/* NAND :: ONFI_STATUS :: ONFI_DEBUG_SEL [31:28] */
-#define BCHP_NAND_ONFI_STATUS_ONFI_DEBUG_SEL_MASK 0xf0000000
-#define BCHP_NAND_ONFI_STATUS_ONFI_DEBUG_SEL_SHIFT 28
-#define BCHP_NAND_ONFI_STATUS_ONFI_DEBUG_SEL_DEFAULT 0x00000000
-
-/* NAND :: ONFI_STATUS :: ONFI_detected [27:27] */
-#define BCHP_NAND_ONFI_STATUS_ONFI_detected_MASK 0x08000000
-#define BCHP_NAND_ONFI_STATUS_ONFI_detected_SHIFT 27
-
-/* NAND :: ONFI_STATUS :: reserved0 [26:06] */
-#define BCHP_NAND_ONFI_STATUS_reserved0_MASK 0x07ffffc0
-#define BCHP_NAND_ONFI_STATUS_reserved0_SHIFT 6
-
-/* NAND :: ONFI_STATUS :: ONFI_BAD_IDENT_PG2 [05:05] */
-#define BCHP_NAND_ONFI_STATUS_ONFI_BAD_IDENT_PG2_MASK 0x00000020
-#define BCHP_NAND_ONFI_STATUS_ONFI_BAD_IDENT_PG2_SHIFT 5
-
-/* NAND :: ONFI_STATUS :: ONFI_BAD_IDENT_PG1 [04:04] */
-#define BCHP_NAND_ONFI_STATUS_ONFI_BAD_IDENT_PG1_MASK 0x00000010
-#define BCHP_NAND_ONFI_STATUS_ONFI_BAD_IDENT_PG1_SHIFT 4
-
-/* NAND :: ONFI_STATUS :: ONFI_BAD_IDENT_PG0 [03:03] */
-#define BCHP_NAND_ONFI_STATUS_ONFI_BAD_IDENT_PG0_MASK 0x00000008
-#define BCHP_NAND_ONFI_STATUS_ONFI_BAD_IDENT_PG0_SHIFT 3
-
-/* NAND :: ONFI_STATUS :: ONFI_CRC_ERROR_PG2 [02:02] */
-#define BCHP_NAND_ONFI_STATUS_ONFI_CRC_ERROR_PG2_MASK 0x00000004
-#define BCHP_NAND_ONFI_STATUS_ONFI_CRC_ERROR_PG2_SHIFT 2
-
-/* NAND :: ONFI_STATUS :: ONFI_CRC_ERROR_PG1 [01:01] */
-#define BCHP_NAND_ONFI_STATUS_ONFI_CRC_ERROR_PG1_MASK 0x00000002
-#define BCHP_NAND_ONFI_STATUS_ONFI_CRC_ERROR_PG1_SHIFT 1
-
-/* NAND :: ONFI_STATUS :: ONFI_CRC_ERROR_PG0 [00:00] */
-#define BCHP_NAND_ONFI_STATUS_ONFI_CRC_ERROR_PG0_MASK 0x00000001
-#define BCHP_NAND_ONFI_STATUS_ONFI_CRC_ERROR_PG0_SHIFT 0
-
-/***************************************************************************
- *ONFI_DEBUG_DATA - ONFI Debug Data
- ***************************************************************************/
-/* NAND :: ONFI_DEBUG_DATA :: ONFI_DEBUG_DATA [31:00] */
-#define BCHP_NAND_ONFI_DEBUG_DATA_ONFI_DEBUG_DATA_MASK 0xffffffff
-#define BCHP_NAND_ONFI_DEBUG_DATA_ONFI_DEBUG_DATA_SHIFT 0
-
-/***************************************************************************
- *SEMAPHORE - Semaphore
- ***************************************************************************/
-/* NAND :: SEMAPHORE :: reserved0 [31:08] */
-#define BCHP_NAND_SEMAPHORE_reserved0_MASK 0xffffff00
-#define BCHP_NAND_SEMAPHORE_reserved0_SHIFT 8
-
-/* NAND :: SEMAPHORE :: semaphore_ctrl [07:00] */
-#define BCHP_NAND_SEMAPHORE_semaphore_ctrl_MASK 0x000000ff
-#define BCHP_NAND_SEMAPHORE_semaphore_ctrl_SHIFT 0
-#define BCHP_NAND_SEMAPHORE_semaphore_ctrl_DEFAULT 0x00000000
-
-/***************************************************************************
- *FLASH_DEVICE_ID - Nand Flash Device ID
- ***************************************************************************/
-/* NAND :: FLASH_DEVICE_ID :: BYTE_0 [31:24] */
-#define BCHP_NAND_FLASH_DEVICE_ID_BYTE_0_MASK 0xff000000
-#define BCHP_NAND_FLASH_DEVICE_ID_BYTE_0_SHIFT 24
-
-/* NAND :: FLASH_DEVICE_ID :: BYTE_1 [23:16] */
-#define BCHP_NAND_FLASH_DEVICE_ID_BYTE_1_MASK 0x00ff0000
-#define BCHP_NAND_FLASH_DEVICE_ID_BYTE_1_SHIFT 16
-
-/* NAND :: FLASH_DEVICE_ID :: BYTE_2 [15:08] */
-#define BCHP_NAND_FLASH_DEVICE_ID_BYTE_2_MASK 0x0000ff00
-#define BCHP_NAND_FLASH_DEVICE_ID_BYTE_2_SHIFT 8
-
-/* NAND :: FLASH_DEVICE_ID :: BYTE_3 [07:00] */
-#define BCHP_NAND_FLASH_DEVICE_ID_BYTE_3_MASK 0x000000ff
-#define BCHP_NAND_FLASH_DEVICE_ID_BYTE_3_SHIFT 0
-
-/***************************************************************************
- *FLASH_DEVICE_ID_EXT - Nand Flash Extended Device ID
- ***************************************************************************/
-/* NAND :: FLASH_DEVICE_ID_EXT :: BYTE_4 [31:24] */
-#define BCHP_NAND_FLASH_DEVICE_ID_EXT_BYTE_4_MASK 0xff000000
-#define BCHP_NAND_FLASH_DEVICE_ID_EXT_BYTE_4_SHIFT 24
-
-/* NAND :: FLASH_DEVICE_ID_EXT :: BYTE_5 [23:16] */
-#define BCHP_NAND_FLASH_DEVICE_ID_EXT_BYTE_5_MASK 0x00ff0000
-#define BCHP_NAND_FLASH_DEVICE_ID_EXT_BYTE_5_SHIFT 16
-
-/* NAND :: FLASH_DEVICE_ID_EXT :: BYTE_6 [15:08] */
-#define BCHP_NAND_FLASH_DEVICE_ID_EXT_BYTE_6_MASK 0x0000ff00
-#define BCHP_NAND_FLASH_DEVICE_ID_EXT_BYTE_6_SHIFT 8
-
-/* NAND :: FLASH_DEVICE_ID_EXT :: BYTE_7 [07:00] */
-#define BCHP_NAND_FLASH_DEVICE_ID_EXT_BYTE_7_MASK 0x000000ff
-#define BCHP_NAND_FLASH_DEVICE_ID_EXT_BYTE_7_SHIFT 0
-
-/***************************************************************************
- *LL_RDDATA - Nand Flash Low Level Read Data
- ***************************************************************************/
-/* NAND :: LL_RDDATA :: reserved0 [31:16] */
-#define BCHP_NAND_LL_RDDATA_reserved0_MASK 0xffff0000
-#define BCHP_NAND_LL_RDDATA_reserved0_SHIFT 16
-
-/* NAND :: LL_RDDATA :: DATA [15:00] */
-#define BCHP_NAND_LL_RDDATA_DATA_MASK 0x0000ffff
-#define BCHP_NAND_LL_RDDATA_DATA_SHIFT 0
-#define BCHP_NAND_LL_RDDATA_DATA_DEFAULT 0x00000000
-
-/***************************************************************************
- *SPARE_AREA_READ_OFS_0 - Nand Flash Spare Area Read Bytes 0-3
- ***************************************************************************/
-/* NAND :: SPARE_AREA_READ_OFS_0 :: BYTE_OFS_0 [31:24] */
-#define BCHP_NAND_SPARE_AREA_READ_OFS_0_BYTE_OFS_0_MASK 0xff000000
-#define BCHP_NAND_SPARE_AREA_READ_OFS_0_BYTE_OFS_0_SHIFT 24
-#define BCHP_NAND_SPARE_AREA_READ_OFS_0_BYTE_OFS_0_DEFAULT 0x000000ff
-
-/* NAND :: SPARE_AREA_READ_OFS_0 :: BYTE_OFS_1 [23:16] */
-#define BCHP_NAND_SPARE_AREA_READ_OFS_0_BYTE_OFS_1_MASK 0x00ff0000
-#define BCHP_NAND_SPARE_AREA_READ_OFS_0_BYTE_OFS_1_SHIFT 16
-#define BCHP_NAND_SPARE_AREA_READ_OFS_0_BYTE_OFS_1_DEFAULT 0x000000ff
-
-/* NAND :: SPARE_AREA_READ_OFS_0 :: BYTE_OFS_2 [15:08] */
-#define BCHP_NAND_SPARE_AREA_READ_OFS_0_BYTE_OFS_2_MASK 0x0000ff00
-#define BCHP_NAND_SPARE_AREA_READ_OFS_0_BYTE_OFS_2_SHIFT 8
-#define BCHP_NAND_SPARE_AREA_READ_OFS_0_BYTE_OFS_2_DEFAULT 0x000000ff
-
-/* NAND :: SPARE_AREA_READ_OFS_0 :: BYTE_OFS_3 [07:00] */
-#define BCHP_NAND_SPARE_AREA_READ_OFS_0_BYTE_OFS_3_MASK 0x000000ff
-#define BCHP_NAND_SPARE_AREA_READ_OFS_0_BYTE_OFS_3_SHIFT 0
-#define BCHP_NAND_SPARE_AREA_READ_OFS_0_BYTE_OFS_3_DEFAULT 0x000000ff
-
-/***************************************************************************
- *SPARE_AREA_READ_OFS_4 - Nand Flash Spare Area Read Bytes 4-7
- ***************************************************************************/
-/* NAND :: SPARE_AREA_READ_OFS_4 :: BYTE_OFS_4 [31:24] */
-#define BCHP_NAND_SPARE_AREA_READ_OFS_4_BYTE_OFS_4_MASK 0xff000000
-#define BCHP_NAND_SPARE_AREA_READ_OFS_4_BYTE_OFS_4_SHIFT 24
-#define BCHP_NAND_SPARE_AREA_READ_OFS_4_BYTE_OFS_4_DEFAULT 0x000000ff
-
-/* NAND :: SPARE_AREA_READ_OFS_4 :: BYTE_OFS_5 [23:16] */
-#define BCHP_NAND_SPARE_AREA_READ_OFS_4_BYTE_OFS_5_MASK 0x00ff0000
-#define BCHP_NAND_SPARE_AREA_READ_OFS_4_BYTE_OFS_5_SHIFT 16
-#define BCHP_NAND_SPARE_AREA_READ_OFS_4_BYTE_OFS_5_DEFAULT 0x000000ff
-
-/* NAND :: SPARE_AREA_READ_OFS_4 :: BYTE_OFS_6 [15:08] */
-#define BCHP_NAND_SPARE_AREA_READ_OFS_4_BYTE_OFS_6_MASK 0x0000ff00
-#define BCHP_NAND_SPARE_AREA_READ_OFS_4_BYTE_OFS_6_SHIFT 8
-#define BCHP_NAND_SPARE_AREA_READ_OFS_4_BYTE_OFS_6_DEFAULT 0x000000ff
-
-/* NAND :: SPARE_AREA_READ_OFS_4 :: BYTE_OFS_7 [07:00] */
-#define BCHP_NAND_SPARE_AREA_READ_OFS_4_BYTE_OFS_7_MASK 0x000000ff
-#define BCHP_NAND_SPARE_AREA_READ_OFS_4_BYTE_OFS_7_SHIFT 0
-#define BCHP_NAND_SPARE_AREA_READ_OFS_4_BYTE_OFS_7_DEFAULT 0x000000ff
-
-/***************************************************************************
- *SPARE_AREA_READ_OFS_8 - Nand Flash Spare Area Read Bytes 8-11
- ***************************************************************************/
-/* NAND :: SPARE_AREA_READ_OFS_8 :: BYTE_OFS_8 [31:24] */
-#define BCHP_NAND_SPARE_AREA_READ_OFS_8_BYTE_OFS_8_MASK 0xff000000
-#define BCHP_NAND_SPARE_AREA_READ_OFS_8_BYTE_OFS_8_SHIFT 24
-#define BCHP_NAND_SPARE_AREA_READ_OFS_8_BYTE_OFS_8_DEFAULT 0x000000ff
-
-/* NAND :: SPARE_AREA_READ_OFS_8 :: BYTE_OFS_9 [23:16] */
-#define BCHP_NAND_SPARE_AREA_READ_OFS_8_BYTE_OFS_9_MASK 0x00ff0000
-#define BCHP_NAND_SPARE_AREA_READ_OFS_8_BYTE_OFS_9_SHIFT 16
-#define BCHP_NAND_SPARE_AREA_READ_OFS_8_BYTE_OFS_9_DEFAULT 0x000000ff
-
-/* NAND :: SPARE_AREA_READ_OFS_8 :: BYTE_OFS_10 [15:08] */
-#define BCHP_NAND_SPARE_AREA_READ_OFS_8_BYTE_OFS_10_MASK 0x0000ff00
-#define BCHP_NAND_SPARE_AREA_READ_OFS_8_BYTE_OFS_10_SHIFT 8
-#define BCHP_NAND_SPARE_AREA_READ_OFS_8_BYTE_OFS_10_DEFAULT 0x000000ff
-
-/* NAND :: SPARE_AREA_READ_OFS_8 :: BYTE_OFS_11 [07:00] */
-#define BCHP_NAND_SPARE_AREA_READ_OFS_8_BYTE_OFS_11_MASK 0x000000ff
-#define BCHP_NAND_SPARE_AREA_READ_OFS_8_BYTE_OFS_11_SHIFT 0
-#define BCHP_NAND_SPARE_AREA_READ_OFS_8_BYTE_OFS_11_DEFAULT 0x000000ff
-
-/***************************************************************************
- *SPARE_AREA_READ_OFS_C - Nand Flash Spare Area Read Bytes 12-15
- ***************************************************************************/
-/* NAND :: SPARE_AREA_READ_OFS_C :: BYTE_OFS_12 [31:24] */
-#define BCHP_NAND_SPARE_AREA_READ_OFS_C_BYTE_OFS_12_MASK 0xff000000
-#define BCHP_NAND_SPARE_AREA_READ_OFS_C_BYTE_OFS_12_SHIFT 24
-#define BCHP_NAND_SPARE_AREA_READ_OFS_C_BYTE_OFS_12_DEFAULT 0x000000ff
-
-/* NAND :: SPARE_AREA_READ_OFS_C :: BYTE_OFS_13 [23:16] */
-#define BCHP_NAND_SPARE_AREA_READ_OFS_C_BYTE_OFS_13_MASK 0x00ff0000
-#define BCHP_NAND_SPARE_AREA_READ_OFS_C_BYTE_OFS_13_SHIFT 16
-#define BCHP_NAND_SPARE_AREA_READ_OFS_C_BYTE_OFS_13_DEFAULT 0x000000ff
-
-/* NAND :: SPARE_AREA_READ_OFS_C :: BYTE_OFS_14 [15:08] */
-#define BCHP_NAND_SPARE_AREA_READ_OFS_C_BYTE_OFS_14_MASK 0x0000ff00
-#define BCHP_NAND_SPARE_AREA_READ_OFS_C_BYTE_OFS_14_SHIFT 8
-#define BCHP_NAND_SPARE_AREA_READ_OFS_C_BYTE_OFS_14_DEFAULT 0x000000ff
-
-/* NAND :: SPARE_AREA_READ_OFS_C :: BYTE_OFS_15 [07:00] */
-#define BCHP_NAND_SPARE_AREA_READ_OFS_C_BYTE_OFS_15_MASK 0x000000ff
-#define BCHP_NAND_SPARE_AREA_READ_OFS_C_BYTE_OFS_15_SHIFT 0
-#define BCHP_NAND_SPARE_AREA_READ_OFS_C_BYTE_OFS_15_DEFAULT 0x000000ff
-
-/***************************************************************************
- *SPARE_AREA_READ_OFS_10 - Nand Flash Spare Area Read Bytes 16-19
- ***************************************************************************/
-/* NAND :: SPARE_AREA_READ_OFS_10 :: BYTE_OFS_16 [31:24] */
-#define BCHP_NAND_SPARE_AREA_READ_OFS_10_BYTE_OFS_16_MASK 0xff000000
-#define BCHP_NAND_SPARE_AREA_READ_OFS_10_BYTE_OFS_16_SHIFT 24
-#define BCHP_NAND_SPARE_AREA_READ_OFS_10_BYTE_OFS_16_DEFAULT 0x000000ff
-
-/* NAND :: SPARE_AREA_READ_OFS_10 :: BYTE_OFS_17 [23:16] */
-#define BCHP_NAND_SPARE_AREA_READ_OFS_10_BYTE_OFS_17_MASK 0x00ff0000
-#define BCHP_NAND_SPARE_AREA_READ_OFS_10_BYTE_OFS_17_SHIFT 16
-#define BCHP_NAND_SPARE_AREA_READ_OFS_10_BYTE_OFS_17_DEFAULT 0x000000ff
-
-/* NAND :: SPARE_AREA_READ_OFS_10 :: BYTE_OFS_18 [15:08] */
-#define BCHP_NAND_SPARE_AREA_READ_OFS_10_BYTE_OFS_18_MASK 0x0000ff00
-#define BCHP_NAND_SPARE_AREA_READ_OFS_10_BYTE_OFS_18_SHIFT 8
-#define BCHP_NAND_SPARE_AREA_READ_OFS_10_BYTE_OFS_18_DEFAULT 0x000000ff
-
-/* NAND :: SPARE_AREA_READ_OFS_10 :: BYTE_OFS_19 [07:00] */
-#define BCHP_NAND_SPARE_AREA_READ_OFS_10_BYTE_OFS_19_MASK 0x000000ff
-#define BCHP_NAND_SPARE_AREA_READ_OFS_10_BYTE_OFS_19_SHIFT 0
-#define BCHP_NAND_SPARE_AREA_READ_OFS_10_BYTE_OFS_19_DEFAULT 0x000000ff
-
-/***************************************************************************
- *SPARE_AREA_READ_OFS_14 - Nand Flash Spare Area Read Bytes 20-23
- ***************************************************************************/
-/* NAND :: SPARE_AREA_READ_OFS_14 :: BYTE_OFS_20 [31:24] */
-#define BCHP_NAND_SPARE_AREA_READ_OFS_14_BYTE_OFS_20_MASK 0xff000000
-#define BCHP_NAND_SPARE_AREA_READ_OFS_14_BYTE_OFS_20_SHIFT 24
-#define BCHP_NAND_SPARE_AREA_READ_OFS_14_BYTE_OFS_20_DEFAULT 0x000000ff
-
-/* NAND :: SPARE_AREA_READ_OFS_14 :: BYTE_OFS_21 [23:16] */
-#define BCHP_NAND_SPARE_AREA_READ_OFS_14_BYTE_OFS_21_MASK 0x00ff0000
-#define BCHP_NAND_SPARE_AREA_READ_OFS_14_BYTE_OFS_21_SHIFT 16
-#define BCHP_NAND_SPARE_AREA_READ_OFS_14_BYTE_OFS_21_DEFAULT 0x000000ff
-
-/* NAND :: SPARE_AREA_READ_OFS_14 :: BYTE_OFS_22 [15:08] */
-#define BCHP_NAND_SPARE_AREA_READ_OFS_14_BYTE_OFS_22_MASK 0x0000ff00
-#define BCHP_NAND_SPARE_AREA_READ_OFS_14_BYTE_OFS_22_SHIFT 8
-#define BCHP_NAND_SPARE_AREA_READ_OFS_14_BYTE_OFS_22_DEFAULT 0x000000ff
-
-/* NAND :: SPARE_AREA_READ_OFS_14 :: BYTE_OFS_23 [07:00] */
-#define BCHP_NAND_SPARE_AREA_READ_OFS_14_BYTE_OFS_23_MASK 0x000000ff
-#define BCHP_NAND_SPARE_AREA_READ_OFS_14_BYTE_OFS_23_SHIFT 0
-#define BCHP_NAND_SPARE_AREA_READ_OFS_14_BYTE_OFS_23_DEFAULT 0x000000ff
-
-/***************************************************************************
- *SPARE_AREA_READ_OFS_18 - Nand Flash Spare Area Read Bytes 24-27
- ***************************************************************************/
-/* NAND :: SPARE_AREA_READ_OFS_18 :: BYTE_OFS_24 [31:24] */
-#define BCHP_NAND_SPARE_AREA_READ_OFS_18_BYTE_OFS_24_MASK 0xff000000
-#define BCHP_NAND_SPARE_AREA_READ_OFS_18_BYTE_OFS_24_SHIFT 24
-#define BCHP_NAND_SPARE_AREA_READ_OFS_18_BYTE_OFS_24_DEFAULT 0x000000ff
-
-/* NAND :: SPARE_AREA_READ_OFS_18 :: BYTE_OFS_25 [23:16] */
-#define BCHP_NAND_SPARE_AREA_READ_OFS_18_BYTE_OFS_25_MASK 0x00ff0000
-#define BCHP_NAND_SPARE_AREA_READ_OFS_18_BYTE_OFS_25_SHIFT 16
-#define BCHP_NAND_SPARE_AREA_READ_OFS_18_BYTE_OFS_25_DEFAULT 0x000000ff
-
-/* NAND :: SPARE_AREA_READ_OFS_18 :: BYTE_OFS_26 [15:08] */
-#define BCHP_NAND_SPARE_AREA_READ_OFS_18_BYTE_OFS_26_MASK 0x0000ff00
-#define BCHP_NAND_SPARE_AREA_READ_OFS_18_BYTE_OFS_26_SHIFT 8
-#define BCHP_NAND_SPARE_AREA_READ_OFS_18_BYTE_OFS_26_DEFAULT 0x000000ff
-
-/* NAND :: SPARE_AREA_READ_OFS_18 :: BYTE_OFS_27 [07:00] */
-#define BCHP_NAND_SPARE_AREA_READ_OFS_18_BYTE_OFS_27_MASK 0x000000ff
-#define BCHP_NAND_SPARE_AREA_READ_OFS_18_BYTE_OFS_27_SHIFT 0
-#define BCHP_NAND_SPARE_AREA_READ_OFS_18_BYTE_OFS_27_DEFAULT 0x000000ff
-
-/***************************************************************************
- *SPARE_AREA_READ_OFS_1C - Nand Flash Spare Area Read Bytes 28-31
- ***************************************************************************/
-/* NAND :: SPARE_AREA_READ_OFS_1C :: BYTE_OFS_28 [31:24] */
-#define BCHP_NAND_SPARE_AREA_READ_OFS_1C_BYTE_OFS_28_MASK 0xff000000
-#define BCHP_NAND_SPARE_AREA_READ_OFS_1C_BYTE_OFS_28_SHIFT 24
-#define BCHP_NAND_SPARE_AREA_READ_OFS_1C_BYTE_OFS_28_DEFAULT 0x000000ff
-
-/* NAND :: SPARE_AREA_READ_OFS_1C :: BYTE_OFS_29 [23:16] */
-#define BCHP_NAND_SPARE_AREA_READ_OFS_1C_BYTE_OFS_29_MASK 0x00ff0000
-#define BCHP_NAND_SPARE_AREA_READ_OFS_1C_BYTE_OFS_29_SHIFT 16
-#define BCHP_NAND_SPARE_AREA_READ_OFS_1C_BYTE_OFS_29_DEFAULT 0x000000ff
-
-/* NAND :: SPARE_AREA_READ_OFS_1C :: BYTE_OFS_30 [15:08] */
-#define BCHP_NAND_SPARE_AREA_READ_OFS_1C_BYTE_OFS_30_MASK 0x0000ff00
-#define BCHP_NAND_SPARE_AREA_READ_OFS_1C_BYTE_OFS_30_SHIFT 8
-#define BCHP_NAND_SPARE_AREA_READ_OFS_1C_BYTE_OFS_30_DEFAULT 0x000000ff
-
-/* NAND :: SPARE_AREA_READ_OFS_1C :: BYTE_OFS_31 [07:00] */
-#define BCHP_NAND_SPARE_AREA_READ_OFS_1C_BYTE_OFS_31_MASK 0x000000ff
-#define BCHP_NAND_SPARE_AREA_READ_OFS_1C_BYTE_OFS_31_SHIFT 0
-#define BCHP_NAND_SPARE_AREA_READ_OFS_1C_BYTE_OFS_31_DEFAULT 0x000000ff
-
-/***************************************************************************
- *SPARE_AREA_READ_OFS_20 - Nand Flash Spare Area Read Bytes 32-35
- ***************************************************************************/
-/* NAND :: SPARE_AREA_READ_OFS_20 :: BYTE_OFS_32 [31:24] */
-#define BCHP_NAND_SPARE_AREA_READ_OFS_20_BYTE_OFS_32_MASK 0xff000000
-#define BCHP_NAND_SPARE_AREA_READ_OFS_20_BYTE_OFS_32_SHIFT 24
-#define BCHP_NAND_SPARE_AREA_READ_OFS_20_BYTE_OFS_32_DEFAULT 0x000000ff
-
-/* NAND :: SPARE_AREA_READ_OFS_20 :: BYTE_OFS_33 [23:16] */
-#define BCHP_NAND_SPARE_AREA_READ_OFS_20_BYTE_OFS_33_MASK 0x00ff0000
-#define BCHP_NAND_SPARE_AREA_READ_OFS_20_BYTE_OFS_33_SHIFT 16
-#define BCHP_NAND_SPARE_AREA_READ_OFS_20_BYTE_OFS_33_DEFAULT 0x000000ff
-
-/* NAND :: SPARE_AREA_READ_OFS_20 :: BYTE_OFS_34 [15:08] */
-#define BCHP_NAND_SPARE_AREA_READ_OFS_20_BYTE_OFS_34_MASK 0x0000ff00
-#define BCHP_NAND_SPARE_AREA_READ_OFS_20_BYTE_OFS_34_SHIFT 8
-#define BCHP_NAND_SPARE_AREA_READ_OFS_20_BYTE_OFS_34_DEFAULT 0x000000ff
-
-/* NAND :: SPARE_AREA_READ_OFS_20 :: BYTE_OFS_35 [07:00] */
-#define BCHP_NAND_SPARE_AREA_READ_OFS_20_BYTE_OFS_35_MASK 0x000000ff
-#define BCHP_NAND_SPARE_AREA_READ_OFS_20_BYTE_OFS_35_SHIFT 0
-#define BCHP_NAND_SPARE_AREA_READ_OFS_20_BYTE_OFS_35_DEFAULT 0x000000ff
-
-/***************************************************************************
- *SPARE_AREA_READ_OFS_24 - Nand Flash Spare Area Read Bytes 36-39
- ***************************************************************************/
-/* NAND :: SPARE_AREA_READ_OFS_24 :: BYTE_OFS_36 [31:24] */
-#define BCHP_NAND_SPARE_AREA_READ_OFS_24_BYTE_OFS_36_MASK 0xff000000
-#define BCHP_NAND_SPARE_AREA_READ_OFS_24_BYTE_OFS_36_SHIFT 24
-#define BCHP_NAND_SPARE_AREA_READ_OFS_24_BYTE_OFS_36_DEFAULT 0x000000ff
-
-/* NAND :: SPARE_AREA_READ_OFS_24 :: BYTE_OFS_37 [23:16] */
-#define BCHP_NAND_SPARE_AREA_READ_OFS_24_BYTE_OFS_37_MASK 0x00ff0000
-#define BCHP_NAND_SPARE_AREA_READ_OFS_24_BYTE_OFS_37_SHIFT 16
-#define BCHP_NAND_SPARE_AREA_READ_OFS_24_BYTE_OFS_37_DEFAULT 0x000000ff
-
-/* NAND :: SPARE_AREA_READ_OFS_24 :: BYTE_OFS_38 [15:08] */
-#define BCHP_NAND_SPARE_AREA_READ_OFS_24_BYTE_OFS_38_MASK 0x0000ff00
-#define BCHP_NAND_SPARE_AREA_READ_OFS_24_BYTE_OFS_38_SHIFT 8
-#define BCHP_NAND_SPARE_AREA_READ_OFS_24_BYTE_OFS_38_DEFAULT 0x000000ff
-
-/* NAND :: SPARE_AREA_READ_OFS_24 :: BYTE_OFS_39 [07:00] */
-#define BCHP_NAND_SPARE_AREA_READ_OFS_24_BYTE_OFS_39_MASK 0x000000ff
-#define BCHP_NAND_SPARE_AREA_READ_OFS_24_BYTE_OFS_39_SHIFT 0
-#define BCHP_NAND_SPARE_AREA_READ_OFS_24_BYTE_OFS_39_DEFAULT 0x000000ff
-
-/***************************************************************************
- *SPARE_AREA_READ_OFS_28 - Nand Flash Spare Area Read Bytes 40-43
- ***************************************************************************/
-/* NAND :: SPARE_AREA_READ_OFS_28 :: BYTE_OFS_40 [31:24] */
-#define BCHP_NAND_SPARE_AREA_READ_OFS_28_BYTE_OFS_40_MASK 0xff000000
-#define BCHP_NAND_SPARE_AREA_READ_OFS_28_BYTE_OFS_40_SHIFT 24
-#define BCHP_NAND_SPARE_AREA_READ_OFS_28_BYTE_OFS_40_DEFAULT 0x000000ff
-
-/* NAND :: SPARE_AREA_READ_OFS_28 :: BYTE_OFS_41 [23:16] */
-#define BCHP_NAND_SPARE_AREA_READ_OFS_28_BYTE_OFS_41_MASK 0x00ff0000
-#define BCHP_NAND_SPARE_AREA_READ_OFS_28_BYTE_OFS_41_SHIFT 16
-#define BCHP_NAND_SPARE_AREA_READ_OFS_28_BYTE_OFS_41_DEFAULT 0x000000ff
-
-/* NAND :: SPARE_AREA_READ_OFS_28 :: BYTE_OFS_42 [15:08] */
-#define BCHP_NAND_SPARE_AREA_READ_OFS_28_BYTE_OFS_42_MASK 0x0000ff00
-#define BCHP_NAND_SPARE_AREA_READ_OFS_28_BYTE_OFS_42_SHIFT 8
-#define BCHP_NAND_SPARE_AREA_READ_OFS_28_BYTE_OFS_42_DEFAULT 0x000000ff
-
-/* NAND :: SPARE_AREA_READ_OFS_28 :: BYTE_OFS_43 [07:00] */
-#define BCHP_NAND_SPARE_AREA_READ_OFS_28_BYTE_OFS_43_MASK 0x000000ff
-#define BCHP_NAND_SPARE_AREA_READ_OFS_28_BYTE_OFS_43_SHIFT 0
-#define BCHP_NAND_SPARE_AREA_READ_OFS_28_BYTE_OFS_43_DEFAULT 0x000000ff
-
-/***************************************************************************
- *SPARE_AREA_READ_OFS_2C - Nand Flash Spare Area Read Bytes 44-47
- ***************************************************************************/
-/* NAND :: SPARE_AREA_READ_OFS_2C :: BYTE_OFS_44 [31:24] */
-#define BCHP_NAND_SPARE_AREA_READ_OFS_2C_BYTE_OFS_44_MASK 0xff000000
-#define BCHP_NAND_SPARE_AREA_READ_OFS_2C_BYTE_OFS_44_SHIFT 24
-#define BCHP_NAND_SPARE_AREA_READ_OFS_2C_BYTE_OFS_44_DEFAULT 0x000000ff
-
-/* NAND :: SPARE_AREA_READ_OFS_2C :: BYTE_OFS_45 [23:16] */
-#define BCHP_NAND_SPARE_AREA_READ_OFS_2C_BYTE_OFS_45_MASK 0x00ff0000
-#define BCHP_NAND_SPARE_AREA_READ_OFS_2C_BYTE_OFS_45_SHIFT 16
-#define BCHP_NAND_SPARE_AREA_READ_OFS_2C_BYTE_OFS_45_DEFAULT 0x000000ff
-
-/* NAND :: SPARE_AREA_READ_OFS_2C :: BYTE_OFS_46 [15:08] */
-#define BCHP_NAND_SPARE_AREA_READ_OFS_2C_BYTE_OFS_46_MASK 0x0000ff00
-#define BCHP_NAND_SPARE_AREA_READ_OFS_2C_BYTE_OFS_46_SHIFT 8
-#define BCHP_NAND_SPARE_AREA_READ_OFS_2C_BYTE_OFS_46_DEFAULT 0x000000ff
-
-/* NAND :: SPARE_AREA_READ_OFS_2C :: BYTE_OFS_47 [07:00] */
-#define BCHP_NAND_SPARE_AREA_READ_OFS_2C_BYTE_OFS_47_MASK 0x000000ff
-#define BCHP_NAND_SPARE_AREA_READ_OFS_2C_BYTE_OFS_47_SHIFT 0
-#define BCHP_NAND_SPARE_AREA_READ_OFS_2C_BYTE_OFS_47_DEFAULT 0x000000ff
-
-/***************************************************************************
- *SPARE_AREA_READ_OFS_30 - Nand Flash Spare Area Read Bytes 48-51
- ***************************************************************************/
-/* NAND :: SPARE_AREA_READ_OFS_30 :: BYTE_OFS_48 [31:24] */
-#define BCHP_NAND_SPARE_AREA_READ_OFS_30_BYTE_OFS_48_MASK 0xff000000
-#define BCHP_NAND_SPARE_AREA_READ_OFS_30_BYTE_OFS_48_SHIFT 24
-#define BCHP_NAND_SPARE_AREA_READ_OFS_30_BYTE_OFS_48_DEFAULT 0x000000ff
-
-/* NAND :: SPARE_AREA_READ_OFS_30 :: BYTE_OFS_49 [23:16] */
-#define BCHP_NAND_SPARE_AREA_READ_OFS_30_BYTE_OFS_49_MASK 0x00ff0000
-#define BCHP_NAND_SPARE_AREA_READ_OFS_30_BYTE_OFS_49_SHIFT 16
-#define BCHP_NAND_SPARE_AREA_READ_OFS_30_BYTE_OFS_49_DEFAULT 0x000000ff
-
-/* NAND :: SPARE_AREA_READ_OFS_30 :: BYTE_OFS_50 [15:08] */
-#define BCHP_NAND_SPARE_AREA_READ_OFS_30_BYTE_OFS_50_MASK 0x0000ff00
-#define BCHP_NAND_SPARE_AREA_READ_OFS_30_BYTE_OFS_50_SHIFT 8
-#define BCHP_NAND_SPARE_AREA_READ_OFS_30_BYTE_OFS_50_DEFAULT 0x000000ff
-
-/* NAND :: SPARE_AREA_READ_OFS_30 :: BYTE_OFS_51 [07:00] */
-#define BCHP_NAND_SPARE_AREA_READ_OFS_30_BYTE_OFS_51_MASK 0x000000ff
-#define BCHP_NAND_SPARE_AREA_READ_OFS_30_BYTE_OFS_51_SHIFT 0
-#define BCHP_NAND_SPARE_AREA_READ_OFS_30_BYTE_OFS_51_DEFAULT 0x000000ff
-
-/***************************************************************************
- *SPARE_AREA_READ_OFS_34 - Nand Flash Spare Area Read Bytes 52-55
- ***************************************************************************/
-/* NAND :: SPARE_AREA_READ_OFS_34 :: BYTE_OFS_52 [31:24] */
-#define BCHP_NAND_SPARE_AREA_READ_OFS_34_BYTE_OFS_52_MASK 0xff000000
-#define BCHP_NAND_SPARE_AREA_READ_OFS_34_BYTE_OFS_52_SHIFT 24
-#define BCHP_NAND_SPARE_AREA_READ_OFS_34_BYTE_OFS_52_DEFAULT 0x000000ff
-
-/* NAND :: SPARE_AREA_READ_OFS_34 :: BYTE_OFS_53 [23:16] */
-#define BCHP_NAND_SPARE_AREA_READ_OFS_34_BYTE_OFS_53_MASK 0x00ff0000
-#define BCHP_NAND_SPARE_AREA_READ_OFS_34_BYTE_OFS_53_SHIFT 16
-#define BCHP_NAND_SPARE_AREA_READ_OFS_34_BYTE_OFS_53_DEFAULT 0x000000ff
-
-/* NAND :: SPARE_AREA_READ_OFS_34 :: BYTE_OFS_54 [15:08] */
-#define BCHP_NAND_SPARE_AREA_READ_OFS_34_BYTE_OFS_54_MASK 0x0000ff00
-#define BCHP_NAND_SPARE_AREA_READ_OFS_34_BYTE_OFS_54_SHIFT 8
-#define BCHP_NAND_SPARE_AREA_READ_OFS_34_BYTE_OFS_54_DEFAULT 0x000000ff
-
-/* NAND :: SPARE_AREA_READ_OFS_34 :: BYTE_OFS_55 [07:00] */
-#define BCHP_NAND_SPARE_AREA_READ_OFS_34_BYTE_OFS_55_MASK 0x000000ff
-#define BCHP_NAND_SPARE_AREA_READ_OFS_34_BYTE_OFS_55_SHIFT 0
-#define BCHP_NAND_SPARE_AREA_READ_OFS_34_BYTE_OFS_55_DEFAULT 0x000000ff
-
-/***************************************************************************
- *SPARE_AREA_READ_OFS_38 - Nand Flash Spare Area Read Bytes 56-59
- ***************************************************************************/
-/* NAND :: SPARE_AREA_READ_OFS_38 :: BYTE_OFS_56 [31:24] */
-#define BCHP_NAND_SPARE_AREA_READ_OFS_38_BYTE_OFS_56_MASK 0xff000000
-#define BCHP_NAND_SPARE_AREA_READ_OFS_38_BYTE_OFS_56_SHIFT 24
-#define BCHP_NAND_SPARE_AREA_READ_OFS_38_BYTE_OFS_56_DEFAULT 0x000000ff
-
-/* NAND :: SPARE_AREA_READ_OFS_38 :: BYTE_OFS_57 [23:16] */
-#define BCHP_NAND_SPARE_AREA_READ_OFS_38_BYTE_OFS_57_MASK 0x00ff0000
-#define BCHP_NAND_SPARE_AREA_READ_OFS_38_BYTE_OFS_57_SHIFT 16
-#define BCHP_NAND_SPARE_AREA_READ_OFS_38_BYTE_OFS_57_DEFAULT 0x000000ff
-
-/* NAND :: SPARE_AREA_READ_OFS_38 :: BYTE_OFS_58 [15:08] */
-#define BCHP_NAND_SPARE_AREA_READ_OFS_38_BYTE_OFS_58_MASK 0x0000ff00
-#define BCHP_NAND_SPARE_AREA_READ_OFS_38_BYTE_OFS_58_SHIFT 8
-#define BCHP_NAND_SPARE_AREA_READ_OFS_38_BYTE_OFS_58_DEFAULT 0x000000ff
-
-/* NAND :: SPARE_AREA_READ_OFS_38 :: BYTE_OFS_59 [07:00] */
-#define BCHP_NAND_SPARE_AREA_READ_OFS_38_BYTE_OFS_59_MASK 0x000000ff
-#define BCHP_NAND_SPARE_AREA_READ_OFS_38_BYTE_OFS_59_SHIFT 0
-#define BCHP_NAND_SPARE_AREA_READ_OFS_38_BYTE_OFS_59_DEFAULT 0x000000ff
-
-/***************************************************************************
- *SPARE_AREA_READ_OFS_3C - Nand Flash Spare Area Read Bytes 60-63
- ***************************************************************************/
-/* NAND :: SPARE_AREA_READ_OFS_3C :: BYTE_OFS_60 [31:24] */
-#define BCHP_NAND_SPARE_AREA_READ_OFS_3C_BYTE_OFS_60_MASK 0xff000000
-#define BCHP_NAND_SPARE_AREA_READ_OFS_3C_BYTE_OFS_60_SHIFT 24
-#define BCHP_NAND_SPARE_AREA_READ_OFS_3C_BYTE_OFS_60_DEFAULT 0x000000ff
-
-/* NAND :: SPARE_AREA_READ_OFS_3C :: BYTE_OFS_61 [23:16] */
-#define BCHP_NAND_SPARE_AREA_READ_OFS_3C_BYTE_OFS_61_MASK 0x00ff0000
-#define BCHP_NAND_SPARE_AREA_READ_OFS_3C_BYTE_OFS_61_SHIFT 16
-#define BCHP_NAND_SPARE_AREA_READ_OFS_3C_BYTE_OFS_61_DEFAULT 0x000000ff
-
-/* NAND :: SPARE_AREA_READ_OFS_3C :: BYTE_OFS_62 [15:08] */
-#define BCHP_NAND_SPARE_AREA_READ_OFS_3C_BYTE_OFS_62_MASK 0x0000ff00
-#define BCHP_NAND_SPARE_AREA_READ_OFS_3C_BYTE_OFS_62_SHIFT 8
-#define BCHP_NAND_SPARE_AREA_READ_OFS_3C_BYTE_OFS_62_DEFAULT 0x000000ff
-
-/* NAND :: SPARE_AREA_READ_OFS_3C :: BYTE_OFS_63 [07:00] */
-#define BCHP_NAND_SPARE_AREA_READ_OFS_3C_BYTE_OFS_63_MASK 0x000000ff
-#define BCHP_NAND_SPARE_AREA_READ_OFS_3C_BYTE_OFS_63_SHIFT 0
-#define BCHP_NAND_SPARE_AREA_READ_OFS_3C_BYTE_OFS_63_DEFAULT 0x000000ff
-
-/***************************************************************************
- *SPARE_AREA_WRITE_OFS_0 - Nand Flash Spare Area Write Bytes 0-3
- ***************************************************************************/
-/* NAND :: SPARE_AREA_WRITE_OFS_0 :: BYTE_OFS_0 [31:24] */
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_0_BYTE_OFS_0_MASK 0xff000000
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_0_BYTE_OFS_0_SHIFT 24
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_0_BYTE_OFS_0_DEFAULT 0x000000ff
-
-/* NAND :: SPARE_AREA_WRITE_OFS_0 :: BYTE_OFS_1 [23:16] */
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_0_BYTE_OFS_1_MASK 0x00ff0000
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_0_BYTE_OFS_1_SHIFT 16
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_0_BYTE_OFS_1_DEFAULT 0x000000ff
-
-/* NAND :: SPARE_AREA_WRITE_OFS_0 :: BYTE_OFS_2 [15:08] */
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_0_BYTE_OFS_2_MASK 0x0000ff00
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_0_BYTE_OFS_2_SHIFT 8
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_0_BYTE_OFS_2_DEFAULT 0x000000ff
-
-/* NAND :: SPARE_AREA_WRITE_OFS_0 :: BYTE_OFS_3 [07:00] */
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_0_BYTE_OFS_3_MASK 0x000000ff
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_0_BYTE_OFS_3_SHIFT 0
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_0_BYTE_OFS_3_DEFAULT 0x000000ff
-
-/***************************************************************************
- *SPARE_AREA_WRITE_OFS_4 - Nand Flash Spare Area Write Bytes 4-7
- ***************************************************************************/
-/* NAND :: SPARE_AREA_WRITE_OFS_4 :: BYTE_OFS_4 [31:24] */
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_4_BYTE_OFS_4_MASK 0xff000000
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_4_BYTE_OFS_4_SHIFT 24
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_4_BYTE_OFS_4_DEFAULT 0x000000ff
-
-/* NAND :: SPARE_AREA_WRITE_OFS_4 :: BYTE_OFS_5 [23:16] */
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_4_BYTE_OFS_5_MASK 0x00ff0000
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_4_BYTE_OFS_5_SHIFT 16
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_4_BYTE_OFS_5_DEFAULT 0x000000ff
-
-/* NAND :: SPARE_AREA_WRITE_OFS_4 :: BYTE_OFS_6 [15:08] */
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_4_BYTE_OFS_6_MASK 0x0000ff00
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_4_BYTE_OFS_6_SHIFT 8
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_4_BYTE_OFS_6_DEFAULT 0x000000ff
-
-/* NAND :: SPARE_AREA_WRITE_OFS_4 :: BYTE_OFS_7 [07:00] */
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_4_BYTE_OFS_7_MASK 0x000000ff
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_4_BYTE_OFS_7_SHIFT 0
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_4_BYTE_OFS_7_DEFAULT 0x000000ff
-
-/***************************************************************************
- *SPARE_AREA_WRITE_OFS_8 - Nand Flash Spare Area Write Bytes 8-11
- ***************************************************************************/
-/* NAND :: SPARE_AREA_WRITE_OFS_8 :: BYTE_OFS_8 [31:24] */
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_8_BYTE_OFS_8_MASK 0xff000000
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_8_BYTE_OFS_8_SHIFT 24
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_8_BYTE_OFS_8_DEFAULT 0x000000ff
-
-/* NAND :: SPARE_AREA_WRITE_OFS_8 :: BYTE_OFS_9 [23:16] */
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_8_BYTE_OFS_9_MASK 0x00ff0000
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_8_BYTE_OFS_9_SHIFT 16
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_8_BYTE_OFS_9_DEFAULT 0x000000ff
-
-/* NAND :: SPARE_AREA_WRITE_OFS_8 :: BYTE_OFS_10 [15:08] */
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_8_BYTE_OFS_10_MASK 0x0000ff00
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_8_BYTE_OFS_10_SHIFT 8
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_8_BYTE_OFS_10_DEFAULT 0x000000ff
-
-/* NAND :: SPARE_AREA_WRITE_OFS_8 :: BYTE_OFS_11 [07:00] */
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_8_BYTE_OFS_11_MASK 0x000000ff
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_8_BYTE_OFS_11_SHIFT 0
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_8_BYTE_OFS_11_DEFAULT 0x000000ff
-
-/***************************************************************************
- *SPARE_AREA_WRITE_OFS_C - Nand Flash Spare Area Write Bytes 12-15
- ***************************************************************************/
-/* NAND :: SPARE_AREA_WRITE_OFS_C :: BYTE_OFS_12 [31:24] */
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_C_BYTE_OFS_12_MASK 0xff000000
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_C_BYTE_OFS_12_SHIFT 24
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_C_BYTE_OFS_12_DEFAULT 0x000000ff
-
-/* NAND :: SPARE_AREA_WRITE_OFS_C :: BYTE_OFS_13 [23:16] */
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_C_BYTE_OFS_13_MASK 0x00ff0000
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_C_BYTE_OFS_13_SHIFT 16
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_C_BYTE_OFS_13_DEFAULT 0x000000ff
-
-/* NAND :: SPARE_AREA_WRITE_OFS_C :: BYTE_OFS_14 [15:08] */
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_C_BYTE_OFS_14_MASK 0x0000ff00
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_C_BYTE_OFS_14_SHIFT 8
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_C_BYTE_OFS_14_DEFAULT 0x000000ff
-
-/* NAND :: SPARE_AREA_WRITE_OFS_C :: BYTE_OFS_15 [07:00] */
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_C_BYTE_OFS_15_MASK 0x000000ff
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_C_BYTE_OFS_15_SHIFT 0
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_C_BYTE_OFS_15_DEFAULT 0x000000ff
-
-/***************************************************************************
- *SPARE_AREA_WRITE_OFS_10 - Nand Flash Spare Area Write Bytes 16-19
- ***************************************************************************/
-/* NAND :: SPARE_AREA_WRITE_OFS_10 :: BYTE_OFS_16 [31:24] */
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_10_BYTE_OFS_16_MASK 0xff000000
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_10_BYTE_OFS_16_SHIFT 24
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_10_BYTE_OFS_16_DEFAULT 0x000000ff
-
-/* NAND :: SPARE_AREA_WRITE_OFS_10 :: BYTE_OFS_17 [23:16] */
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_10_BYTE_OFS_17_MASK 0x00ff0000
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_10_BYTE_OFS_17_SHIFT 16
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_10_BYTE_OFS_17_DEFAULT 0x000000ff
-
-/* NAND :: SPARE_AREA_WRITE_OFS_10 :: BYTE_OFS_18 [15:08] */
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_10_BYTE_OFS_18_MASK 0x0000ff00
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_10_BYTE_OFS_18_SHIFT 8
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_10_BYTE_OFS_18_DEFAULT 0x000000ff
-
-/* NAND :: SPARE_AREA_WRITE_OFS_10 :: BYTE_OFS_19 [07:00] */
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_10_BYTE_OFS_19_MASK 0x000000ff
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_10_BYTE_OFS_19_SHIFT 0
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_10_BYTE_OFS_19_DEFAULT 0x000000ff
-
-/***************************************************************************
- *SPARE_AREA_WRITE_OFS_14 - Nand Flash Spare Area Write Bytes 20-23
- ***************************************************************************/
-/* NAND :: SPARE_AREA_WRITE_OFS_14 :: BYTE_OFS_20 [31:24] */
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_14_BYTE_OFS_20_MASK 0xff000000
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_14_BYTE_OFS_20_SHIFT 24
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_14_BYTE_OFS_20_DEFAULT 0x000000ff
-
-/* NAND :: SPARE_AREA_WRITE_OFS_14 :: BYTE_OFS_21 [23:16] */
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_14_BYTE_OFS_21_MASK 0x00ff0000
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_14_BYTE_OFS_21_SHIFT 16
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_14_BYTE_OFS_21_DEFAULT 0x000000ff
-
-/* NAND :: SPARE_AREA_WRITE_OFS_14 :: BYTE_OFS_22 [15:08] */
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_14_BYTE_OFS_22_MASK 0x0000ff00
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_14_BYTE_OFS_22_SHIFT 8
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_14_BYTE_OFS_22_DEFAULT 0x000000ff
-
-/* NAND :: SPARE_AREA_WRITE_OFS_14 :: BYTE_OFS_23 [07:00] */
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_14_BYTE_OFS_23_MASK 0x000000ff
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_14_BYTE_OFS_23_SHIFT 0
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_14_BYTE_OFS_23_DEFAULT 0x000000ff
-
-/***************************************************************************
- *SPARE_AREA_WRITE_OFS_18 - Nand Flash Spare Area Write Bytes 24-27
- ***************************************************************************/
-/* NAND :: SPARE_AREA_WRITE_OFS_18 :: BYTE_OFS_24 [31:24] */
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_18_BYTE_OFS_24_MASK 0xff000000
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_18_BYTE_OFS_24_SHIFT 24
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_18_BYTE_OFS_24_DEFAULT 0x000000ff
-
-/* NAND :: SPARE_AREA_WRITE_OFS_18 :: BYTE_OFS_25 [23:16] */
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_18_BYTE_OFS_25_MASK 0x00ff0000
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_18_BYTE_OFS_25_SHIFT 16
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_18_BYTE_OFS_25_DEFAULT 0x000000ff
-
-/* NAND :: SPARE_AREA_WRITE_OFS_18 :: BYTE_OFS_26 [15:08] */
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_18_BYTE_OFS_26_MASK 0x0000ff00
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_18_BYTE_OFS_26_SHIFT 8
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_18_BYTE_OFS_26_DEFAULT 0x000000ff
-
-/* NAND :: SPARE_AREA_WRITE_OFS_18 :: BYTE_OFS_27 [07:00] */
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_18_BYTE_OFS_27_MASK 0x000000ff
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_18_BYTE_OFS_27_SHIFT 0
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_18_BYTE_OFS_27_DEFAULT 0x000000ff
-
-/***************************************************************************
- *SPARE_AREA_WRITE_OFS_1C - Nand Flash Spare Area Write Bytes 28-31
- ***************************************************************************/
-/* NAND :: SPARE_AREA_WRITE_OFS_1C :: BYTE_OFS_28 [31:24] */
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_1C_BYTE_OFS_28_MASK 0xff000000
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_1C_BYTE_OFS_28_SHIFT 24
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_1C_BYTE_OFS_28_DEFAULT 0x000000ff
-
-/* NAND :: SPARE_AREA_WRITE_OFS_1C :: BYTE_OFS_29 [23:16] */
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_1C_BYTE_OFS_29_MASK 0x00ff0000
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_1C_BYTE_OFS_29_SHIFT 16
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_1C_BYTE_OFS_29_DEFAULT 0x000000ff
-
-/* NAND :: SPARE_AREA_WRITE_OFS_1C :: BYTE_OFS_30 [15:08] */
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_1C_BYTE_OFS_30_MASK 0x0000ff00
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_1C_BYTE_OFS_30_SHIFT 8
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_1C_BYTE_OFS_30_DEFAULT 0x000000ff
-
-/* NAND :: SPARE_AREA_WRITE_OFS_1C :: BYTE_OFS_31 [07:00] */
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_1C_BYTE_OFS_31_MASK 0x000000ff
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_1C_BYTE_OFS_31_SHIFT 0
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_1C_BYTE_OFS_31_DEFAULT 0x000000ff
-
-/***************************************************************************
- *SPARE_AREA_WRITE_OFS_20 - Nand Flash Spare Area Write Bytes 32-35
- ***************************************************************************/
-/* NAND :: SPARE_AREA_WRITE_OFS_20 :: BYTE_OFS_32 [31:24] */
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_20_BYTE_OFS_32_MASK 0xff000000
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_20_BYTE_OFS_32_SHIFT 24
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_20_BYTE_OFS_32_DEFAULT 0x000000ff
-
-/* NAND :: SPARE_AREA_WRITE_OFS_20 :: BYTE_OFS_33 [23:16] */
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_20_BYTE_OFS_33_MASK 0x00ff0000
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_20_BYTE_OFS_33_SHIFT 16
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_20_BYTE_OFS_33_DEFAULT 0x000000ff
-
-/* NAND :: SPARE_AREA_WRITE_OFS_20 :: BYTE_OFS_34 [15:08] */
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_20_BYTE_OFS_34_MASK 0x0000ff00
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_20_BYTE_OFS_34_SHIFT 8
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_20_BYTE_OFS_34_DEFAULT 0x000000ff
-
-/* NAND :: SPARE_AREA_WRITE_OFS_20 :: BYTE_OFS_35 [07:00] */
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_20_BYTE_OFS_35_MASK 0x000000ff
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_20_BYTE_OFS_35_SHIFT 0
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_20_BYTE_OFS_35_DEFAULT 0x000000ff
-
-/***************************************************************************
- *SPARE_AREA_WRITE_OFS_24 - Nand Flash Spare Area Write Bytes 36-39
- ***************************************************************************/
-/* NAND :: SPARE_AREA_WRITE_OFS_24 :: BYTE_OFS_36 [31:24] */
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_24_BYTE_OFS_36_MASK 0xff000000
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_24_BYTE_OFS_36_SHIFT 24
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_24_BYTE_OFS_36_DEFAULT 0x000000ff
-
-/* NAND :: SPARE_AREA_WRITE_OFS_24 :: BYTE_OFS_37 [23:16] */
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_24_BYTE_OFS_37_MASK 0x00ff0000
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_24_BYTE_OFS_37_SHIFT 16
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_24_BYTE_OFS_37_DEFAULT 0x000000ff
-
-/* NAND :: SPARE_AREA_WRITE_OFS_24 :: BYTE_OFS_38 [15:08] */
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_24_BYTE_OFS_38_MASK 0x0000ff00
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_24_BYTE_OFS_38_SHIFT 8
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_24_BYTE_OFS_38_DEFAULT 0x000000ff
-
-/* NAND :: SPARE_AREA_WRITE_OFS_24 :: BYTE_OFS_39 [07:00] */
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_24_BYTE_OFS_39_MASK 0x000000ff
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_24_BYTE_OFS_39_SHIFT 0
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_24_BYTE_OFS_39_DEFAULT 0x000000ff
-
-/***************************************************************************
- *SPARE_AREA_WRITE_OFS_28 - Nand Flash Spare Area Write Bytes 40-43
- ***************************************************************************/
-/* NAND :: SPARE_AREA_WRITE_OFS_28 :: BYTE_OFS_40 [31:24] */
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_28_BYTE_OFS_40_MASK 0xff000000
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_28_BYTE_OFS_40_SHIFT 24
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_28_BYTE_OFS_40_DEFAULT 0x000000ff
-
-/* NAND :: SPARE_AREA_WRITE_OFS_28 :: BYTE_OFS_41 [23:16] */
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_28_BYTE_OFS_41_MASK 0x00ff0000
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_28_BYTE_OFS_41_SHIFT 16
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_28_BYTE_OFS_41_DEFAULT 0x000000ff
-
-/* NAND :: SPARE_AREA_WRITE_OFS_28 :: BYTE_OFS_42 [15:08] */
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_28_BYTE_OFS_42_MASK 0x0000ff00
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_28_BYTE_OFS_42_SHIFT 8
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_28_BYTE_OFS_42_DEFAULT 0x000000ff
-
-/* NAND :: SPARE_AREA_WRITE_OFS_28 :: BYTE_OFS_43 [07:00] */
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_28_BYTE_OFS_43_MASK 0x000000ff
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_28_BYTE_OFS_43_SHIFT 0
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_28_BYTE_OFS_43_DEFAULT 0x000000ff
-
-/***************************************************************************
- *SPARE_AREA_WRITE_OFS_2C - Nand Flash Spare Area Write Bytes 44-47
- ***************************************************************************/
-/* NAND :: SPARE_AREA_WRITE_OFS_2C :: BYTE_OFS_44 [31:24] */
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_2C_BYTE_OFS_44_MASK 0xff000000
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_2C_BYTE_OFS_44_SHIFT 24
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_2C_BYTE_OFS_44_DEFAULT 0x000000ff
-
-/* NAND :: SPARE_AREA_WRITE_OFS_2C :: BYTE_OFS_45 [23:16] */
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_2C_BYTE_OFS_45_MASK 0x00ff0000
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_2C_BYTE_OFS_45_SHIFT 16
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_2C_BYTE_OFS_45_DEFAULT 0x000000ff
-
-/* NAND :: SPARE_AREA_WRITE_OFS_2C :: BYTE_OFS_46 [15:08] */
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_2C_BYTE_OFS_46_MASK 0x0000ff00
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_2C_BYTE_OFS_46_SHIFT 8
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_2C_BYTE_OFS_46_DEFAULT 0x000000ff
-
-/* NAND :: SPARE_AREA_WRITE_OFS_2C :: BYTE_OFS_47 [07:00] */
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_2C_BYTE_OFS_47_MASK 0x000000ff
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_2C_BYTE_OFS_47_SHIFT 0
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_2C_BYTE_OFS_47_DEFAULT 0x000000ff
-
-/***************************************************************************
- *SPARE_AREA_WRITE_OFS_30 - Nand Flash Spare Area Write Bytes 48-51
- ***************************************************************************/
-/* NAND :: SPARE_AREA_WRITE_OFS_30 :: BYTE_OFS_48 [31:24] */
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_30_BYTE_OFS_48_MASK 0xff000000
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_30_BYTE_OFS_48_SHIFT 24
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_30_BYTE_OFS_48_DEFAULT 0x000000ff
-
-/* NAND :: SPARE_AREA_WRITE_OFS_30 :: BYTE_OFS_49 [23:16] */
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_30_BYTE_OFS_49_MASK 0x00ff0000
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_30_BYTE_OFS_49_SHIFT 16
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_30_BYTE_OFS_49_DEFAULT 0x000000ff
-
-/* NAND :: SPARE_AREA_WRITE_OFS_30 :: BYTE_OFS_50 [15:08] */
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_30_BYTE_OFS_50_MASK 0x0000ff00
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_30_BYTE_OFS_50_SHIFT 8
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_30_BYTE_OFS_50_DEFAULT 0x000000ff
-
-/* NAND :: SPARE_AREA_WRITE_OFS_30 :: BYTE_OFS_51 [07:00] */
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_30_BYTE_OFS_51_MASK 0x000000ff
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_30_BYTE_OFS_51_SHIFT 0
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_30_BYTE_OFS_51_DEFAULT 0x000000ff
-
-/***************************************************************************
- *SPARE_AREA_WRITE_OFS_34 - Nand Flash Spare Area Write Bytes 52-55
- ***************************************************************************/
-/* NAND :: SPARE_AREA_WRITE_OFS_34 :: BYTE_OFS_52 [31:24] */
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_34_BYTE_OFS_52_MASK 0xff000000
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_34_BYTE_OFS_52_SHIFT 24
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_34_BYTE_OFS_52_DEFAULT 0x000000ff
-
-/* NAND :: SPARE_AREA_WRITE_OFS_34 :: BYTE_OFS_53 [23:16] */
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_34_BYTE_OFS_53_MASK 0x00ff0000
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_34_BYTE_OFS_53_SHIFT 16
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_34_BYTE_OFS_53_DEFAULT 0x000000ff
-
-/* NAND :: SPARE_AREA_WRITE_OFS_34 :: BYTE_OFS_54 [15:08] */
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_34_BYTE_OFS_54_MASK 0x0000ff00
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_34_BYTE_OFS_54_SHIFT 8
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_34_BYTE_OFS_54_DEFAULT 0x000000ff
-
-/* NAND :: SPARE_AREA_WRITE_OFS_34 :: BYTE_OFS_55 [07:00] */
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_34_BYTE_OFS_55_MASK 0x000000ff
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_34_BYTE_OFS_55_SHIFT 0
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_34_BYTE_OFS_55_DEFAULT 0x000000ff
-
-/***************************************************************************
- *SPARE_AREA_WRITE_OFS_38 - Nand Flash Spare Area Write Bytes 56-59
- ***************************************************************************/
-/* NAND :: SPARE_AREA_WRITE_OFS_38 :: BYTE_OFS_56 [31:24] */
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_38_BYTE_OFS_56_MASK 0xff000000
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_38_BYTE_OFS_56_SHIFT 24
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_38_BYTE_OFS_56_DEFAULT 0x000000ff
-
-/* NAND :: SPARE_AREA_WRITE_OFS_38 :: BYTE_OFS_57 [23:16] */
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_38_BYTE_OFS_57_MASK 0x00ff0000
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_38_BYTE_OFS_57_SHIFT 16
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_38_BYTE_OFS_57_DEFAULT 0x000000ff
-
-/* NAND :: SPARE_AREA_WRITE_OFS_38 :: BYTE_OFS_58 [15:08] */
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_38_BYTE_OFS_58_MASK 0x0000ff00
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_38_BYTE_OFS_58_SHIFT 8
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_38_BYTE_OFS_58_DEFAULT 0x000000ff
-
-/* NAND :: SPARE_AREA_WRITE_OFS_38 :: BYTE_OFS_59 [07:00] */
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_38_BYTE_OFS_59_MASK 0x000000ff
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_38_BYTE_OFS_59_SHIFT 0
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_38_BYTE_OFS_59_DEFAULT 0x000000ff
-
-/***************************************************************************
- *SPARE_AREA_WRITE_OFS_3C - Nand Flash Spare Area Write Bytes 60-63
- ***************************************************************************/
-/* NAND :: SPARE_AREA_WRITE_OFS_3C :: BYTE_OFS_60 [31:24] */
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_3C_BYTE_OFS_60_MASK 0xff000000
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_3C_BYTE_OFS_60_SHIFT 24
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_3C_BYTE_OFS_60_DEFAULT 0x000000ff
-
-/* NAND :: SPARE_AREA_WRITE_OFS_3C :: BYTE_OFS_61 [23:16] */
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_3C_BYTE_OFS_61_MASK 0x00ff0000
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_3C_BYTE_OFS_61_SHIFT 16
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_3C_BYTE_OFS_61_DEFAULT 0x000000ff
-
-/* NAND :: SPARE_AREA_WRITE_OFS_3C :: BYTE_OFS_62 [15:08] */
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_3C_BYTE_OFS_62_MASK 0x0000ff00
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_3C_BYTE_OFS_62_SHIFT 8
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_3C_BYTE_OFS_62_DEFAULT 0x000000ff
-
-/* NAND :: SPARE_AREA_WRITE_OFS_3C :: BYTE_OFS_63 [07:00] */
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_3C_BYTE_OFS_63_MASK 0x000000ff
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_3C_BYTE_OFS_63_SHIFT 0
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_3C_BYTE_OFS_63_DEFAULT 0x000000ff
-
-/***************************************************************************
- *DDR_TIMING - Nand Flash DDR TIMING
- ***************************************************************************/
-/* NAND :: DDR_TIMING :: reserved0 [31:28] */
-#define BCHP_NAND_DDR_TIMING_reserved0_MASK 0xf0000000
-#define BCHP_NAND_DDR_TIMING_reserved0_SHIFT 28
-
-/* NAND :: DDR_TIMING :: tCCS [27:24] */
-#define BCHP_NAND_DDR_TIMING_tCCS_MASK 0x0f000000
-#define BCHP_NAND_DDR_TIMING_tCCS_SHIFT 24
-#define BCHP_NAND_DDR_TIMING_tCCS_DEFAULT 0x00000008
-
-/* NAND :: DDR_TIMING :: tCAD [23:20] */
-#define BCHP_NAND_DDR_TIMING_tCAD_MASK 0x00f00000
-#define BCHP_NAND_DDR_TIMING_tCAD_SHIFT 20
-#define BCHP_NAND_DDR_TIMING_tCAD_DEFAULT 0x00000004
-
-/* NAND :: DDR_TIMING :: reserved1 [19:17] */
-#define BCHP_NAND_DDR_TIMING_reserved1_MASK 0x000e0000
-#define BCHP_NAND_DDR_TIMING_reserved1_SHIFT 17
-
-/* NAND :: DDR_TIMING :: tWHR [16:12] */
-#define BCHP_NAND_DDR_TIMING_tWHR_MASK 0x0001f000
-#define BCHP_NAND_DDR_TIMING_tWHR_SHIFT 12
-#define BCHP_NAND_DDR_TIMING_tWHR_DEFAULT 0x00000014
-
-/* NAND :: DDR_TIMING :: tCS [11:08] */
-#define BCHP_NAND_DDR_TIMING_tCS_MASK 0x00000f00
-#define BCHP_NAND_DDR_TIMING_tCS_SHIFT 8
-#define BCHP_NAND_DDR_TIMING_tCS_DEFAULT 0x00000002
-
-/* NAND :: DDR_TIMING :: tWB [07:04] */
-#define BCHP_NAND_DDR_TIMING_tWB_MASK 0x000000f0
-#define BCHP_NAND_DDR_TIMING_tWB_SHIFT 4
-#define BCHP_NAND_DDR_TIMING_tWB_DEFAULT 0x0000000f
-
-/* NAND :: DDR_TIMING :: tADL [03:00] */
-#define BCHP_NAND_DDR_TIMING_tADL_MASK 0x0000000f
-#define BCHP_NAND_DDR_TIMING_tADL_SHIFT 0
-#define BCHP_NAND_DDR_TIMING_tADL_DEFAULT 0x00000007
-
-/***************************************************************************
- *DDR_NCDL_CALIB_CTL - Nand Flash Calibration Control for Master DLL
- ***************************************************************************/
-/* NAND :: DDR_NCDL_CALIB_CTL :: reserved0 [31:04] */
-#define BCHP_NAND_DDR_NCDL_CALIB_CTL_reserved0_MASK 0xfffffff0
-#define BCHP_NAND_DDR_NCDL_CALIB_CTL_reserved0_SHIFT 4
-
-/* NAND :: DDR_NCDL_CALIB_CTL :: CALIB_PERIODIC [03:03] */
-#define BCHP_NAND_DDR_NCDL_CALIB_CTL_CALIB_PERIODIC_MASK 0x00000008
-#define BCHP_NAND_DDR_NCDL_CALIB_CTL_CALIB_PERIODIC_SHIFT 3
-#define BCHP_NAND_DDR_NCDL_CALIB_CTL_CALIB_PERIODIC_DEFAULT 0x00000000
-
-/* NAND :: DDR_NCDL_CALIB_CTL :: CALIB_ALWAYS [02:02] */
-#define BCHP_NAND_DDR_NCDL_CALIB_CTL_CALIB_ALWAYS_MASK 0x00000004
-#define BCHP_NAND_DDR_NCDL_CALIB_CTL_CALIB_ALWAYS_SHIFT 2
-#define BCHP_NAND_DDR_NCDL_CALIB_CTL_CALIB_ALWAYS_DEFAULT 0x00000000
-
-/* NAND :: DDR_NCDL_CALIB_CTL :: CALIB_ONCE [01:01] */
-#define BCHP_NAND_DDR_NCDL_CALIB_CTL_CALIB_ONCE_MASK 0x00000002
-#define BCHP_NAND_DDR_NCDL_CALIB_CTL_CALIB_ONCE_SHIFT 1
-#define BCHP_NAND_DDR_NCDL_CALIB_CTL_CALIB_ONCE_DEFAULT 0x00000000
-
-/* NAND :: DDR_NCDL_CALIB_CTL :: CALIB_EN [00:00] */
-#define BCHP_NAND_DDR_NCDL_CALIB_CTL_CALIB_EN_MASK 0x00000001
-#define BCHP_NAND_DDR_NCDL_CALIB_CTL_CALIB_EN_SHIFT 0
-#define BCHP_NAND_DDR_NCDL_CALIB_CTL_CALIB_EN_DEFAULT 0x00000000
-
-/***************************************************************************
- *DDR_NCDL_CALIB_PERIOD - Nand Flash Calibration Period
- ***************************************************************************/
-/* NAND :: DDR_NCDL_CALIB_PERIOD :: reserved0 [31:20] */
-#define BCHP_NAND_DDR_NCDL_CALIB_PERIOD_reserved0_MASK 0xfff00000
-#define BCHP_NAND_DDR_NCDL_CALIB_PERIOD_reserved0_SHIFT 20
-
-/* NAND :: DDR_NCDL_CALIB_PERIOD :: CALIB_PERIOD [19:00] */
-#define BCHP_NAND_DDR_NCDL_CALIB_PERIOD_CALIB_PERIOD_MASK 0x000fffff
-#define BCHP_NAND_DDR_NCDL_CALIB_PERIOD_CALIB_PERIOD_SHIFT 0
-#define BCHP_NAND_DDR_NCDL_CALIB_PERIOD_CALIB_PERIOD_DEFAULT 0x00000000
-
-/***************************************************************************
- *DDR_NCDL_CALIB_STAT - Nand Flash Calibration Status for Master DLL
- ***************************************************************************/
-/* NAND :: DDR_NCDL_CALIB_STAT :: reserved0 [31:16] */
-#define BCHP_NAND_DDR_NCDL_CALIB_STAT_reserved0_MASK 0xffff0000
-#define BCHP_NAND_DDR_NCDL_CALIB_STAT_reserved0_SHIFT 16
-
-/* NAND :: DDR_NCDL_CALIB_STAT :: NCDL_PHASE [15:08] */
-#define BCHP_NAND_DDR_NCDL_CALIB_STAT_NCDL_PHASE_MASK 0x0000ff00
-#define BCHP_NAND_DDR_NCDL_CALIB_STAT_NCDL_PHASE_SHIFT 8
-#define BCHP_NAND_DDR_NCDL_CALIB_STAT_NCDL_PHASE_DEFAULT 0x00000000
-
-/* NAND :: DDR_NCDL_CALIB_STAT :: reserved1 [07:01] */
-#define BCHP_NAND_DDR_NCDL_CALIB_STAT_reserved1_MASK 0x000000fe
-#define BCHP_NAND_DDR_NCDL_CALIB_STAT_reserved1_SHIFT 1
-
-/* NAND :: DDR_NCDL_CALIB_STAT :: CALIB_LOCK [00:00] */
-#define BCHP_NAND_DDR_NCDL_CALIB_STAT_CALIB_LOCK_MASK 0x00000001
-#define BCHP_NAND_DDR_NCDL_CALIB_STAT_CALIB_LOCK_SHIFT 0
-#define BCHP_NAND_DDR_NCDL_CALIB_STAT_CALIB_LOCK_DEFAULT 0x00000000
-
-/***************************************************************************
- *DDR_NCDL_MODE - Nand Flash NCDL mode for Slave DLLs
- ***************************************************************************/
-/* NAND :: DDR_NCDL_MODE :: reserved0 [31:05] */
-#define BCHP_NAND_DDR_NCDL_MODE_reserved0_MASK 0xffffffe0
-#define BCHP_NAND_DDR_NCDL_MODE_reserved0_SHIFT 5
-
-/* NAND :: DDR_NCDL_MODE :: RDNCDL [04:04] */
-#define BCHP_NAND_DDR_NCDL_MODE_RDNCDL_MASK 0x00000010
-#define BCHP_NAND_DDR_NCDL_MODE_RDNCDL_SHIFT 4
-#define BCHP_NAND_DDR_NCDL_MODE_RDNCDL_DEFAULT 0x00000000
-
-/* NAND :: DDR_NCDL_MODE :: reserved1 [03:01] */
-#define BCHP_NAND_DDR_NCDL_MODE_reserved1_MASK 0x0000000e
-#define BCHP_NAND_DDR_NCDL_MODE_reserved1_SHIFT 1
-
-/* NAND :: DDR_NCDL_MODE :: WRNCDL [00:00] */
-#define BCHP_NAND_DDR_NCDL_MODE_WRNCDL_MASK 0x00000001
-#define BCHP_NAND_DDR_NCDL_MODE_WRNCDL_SHIFT 0
-#define BCHP_NAND_DDR_NCDL_MODE_WRNCDL_DEFAULT 0x00000000
-
-/***************************************************************************
- *DDR_NCDL_OFFSET - Nand Flash NCDL offset for Slave DLLs
- ***************************************************************************/
-/* NAND :: DDR_NCDL_OFFSET :: reserved0 [31:25] */
-#define BCHP_NAND_DDR_NCDL_OFFSET_reserved0_MASK 0xfe000000
-#define BCHP_NAND_DDR_NCDL_OFFSET_reserved0_SHIFT 25
-
-/* NAND :: DDR_NCDL_OFFSET :: RDNCDL_OFF [24:16] */
-#define BCHP_NAND_DDR_NCDL_OFFSET_RDNCDL_OFF_MASK 0x01ff0000
-#define BCHP_NAND_DDR_NCDL_OFFSET_RDNCDL_OFF_SHIFT 16
-#define BCHP_NAND_DDR_NCDL_OFFSET_RDNCDL_OFF_DEFAULT 0x00000000
-
-/* NAND :: DDR_NCDL_OFFSET :: reserved1 [15:09] */
-#define BCHP_NAND_DDR_NCDL_OFFSET_reserved1_MASK 0x0000fe00
-#define BCHP_NAND_DDR_NCDL_OFFSET_reserved1_SHIFT 9
-
-/* NAND :: DDR_NCDL_OFFSET :: WRNCDL_OFF [08:00] */
-#define BCHP_NAND_DDR_NCDL_OFFSET_WRNCDL_OFF_MASK 0x000001ff
-#define BCHP_NAND_DDR_NCDL_OFFSET_WRNCDL_OFF_SHIFT 0
-#define BCHP_NAND_DDR_NCDL_OFFSET_WRNCDL_OFF_DEFAULT 0x00000000
-
-/***************************************************************************
- *DDR_PHY_CTL - Nand Flash DDR PHY CONTROL
- ***************************************************************************/
-/* NAND :: DDR_PHY_CTL :: reserved0 [31:02] */
-#define BCHP_NAND_DDR_PHY_CTL_reserved0_MASK 0xfffffffc
-#define BCHP_NAND_DDR_PHY_CTL_reserved0_SHIFT 2
-
-/* NAND :: DDR_PHY_CTL :: DDR_MODE [01:01] */
-#define BCHP_NAND_DDR_PHY_CTL_DDR_MODE_MASK 0x00000002
-#define BCHP_NAND_DDR_PHY_CTL_DDR_MODE_SHIFT 1
-#define BCHP_NAND_DDR_PHY_CTL_DDR_MODE_DEFAULT 0x00000000
-
-/* NAND :: DDR_PHY_CTL :: reserved1 [00:00] */
-#define BCHP_NAND_DDR_PHY_CTL_reserved1_MASK 0x00000001
-#define BCHP_NAND_DDR_PHY_CTL_reserved1_SHIFT 0
-
-/***************************************************************************
- *DDR_PHY_BIST_CTL - Nand Flash DDR PHY BIST CONTROL
- ***************************************************************************/
-/* NAND :: DDR_PHY_BIST_CTL :: reserved0 [31:05] */
-#define BCHP_NAND_DDR_PHY_BIST_CTL_reserved0_MASK 0xffffffe0
-#define BCHP_NAND_DDR_PHY_BIST_CTL_reserved0_SHIFT 5
-
-/* NAND :: DDR_PHY_BIST_CTL :: BIST_CLR [04:04] */
-#define BCHP_NAND_DDR_PHY_BIST_CTL_BIST_CLR_MASK 0x00000010
-#define BCHP_NAND_DDR_PHY_BIST_CTL_BIST_CLR_SHIFT 4
-#define BCHP_NAND_DDR_PHY_BIST_CTL_BIST_CLR_DEFAULT 0x00000000
-
-/* NAND :: DDR_PHY_BIST_CTL :: reserved1 [03:01] */
-#define BCHP_NAND_DDR_PHY_BIST_CTL_reserved1_MASK 0x0000000e
-#define BCHP_NAND_DDR_PHY_BIST_CTL_reserved1_SHIFT 1
-
-/* NAND :: DDR_PHY_BIST_CTL :: BIST_START [00:00] */
-#define BCHP_NAND_DDR_PHY_BIST_CTL_BIST_START_MASK 0x00000001
-#define BCHP_NAND_DDR_PHY_BIST_CTL_BIST_START_SHIFT 0
-#define BCHP_NAND_DDR_PHY_BIST_CTL_BIST_START_DEFAULT 0x00000000
-
-/***************************************************************************
- *DDR_PHY_BIST_STAT - Nand Flash DDR PHY BIST STATUS
- ***************************************************************************/
-/* NAND :: DDR_PHY_BIST_STAT :: reserved0 [31:07] */
-#define BCHP_NAND_DDR_PHY_BIST_STAT_reserved0_MASK 0xffffff80
-#define BCHP_NAND_DDR_PHY_BIST_STAT_reserved0_SHIFT 7
-
-/* NAND :: DDR_PHY_BIST_STAT :: W1_DATA_RDPH_ERR [06:06] */
-#define BCHP_NAND_DDR_PHY_BIST_STAT_W1_DATA_RDPH_ERR_MASK 0x00000040
-#define BCHP_NAND_DDR_PHY_BIST_STAT_W1_DATA_RDPH_ERR_SHIFT 6
-
-/* NAND :: DDR_PHY_BIST_STAT :: W0_DATA_RDPH_ERR [05:05] */
-#define BCHP_NAND_DDR_PHY_BIST_STAT_W0_DATA_RDPH_ERR_MASK 0x00000020
-#define BCHP_NAND_DDR_PHY_BIST_STAT_W0_DATA_RDPH_ERR_SHIFT 5
-
-/* NAND :: DDR_PHY_BIST_STAT :: W1_DATA_WRPH_ERR [04:04] */
-#define BCHP_NAND_DDR_PHY_BIST_STAT_W1_DATA_WRPH_ERR_MASK 0x00000010
-#define BCHP_NAND_DDR_PHY_BIST_STAT_W1_DATA_WRPH_ERR_SHIFT 4
-
-/* NAND :: DDR_PHY_BIST_STAT :: W0_DATA_WRPH_ERR [03:03] */
-#define BCHP_NAND_DDR_PHY_BIST_STAT_W0_DATA_WRPH_ERR_MASK 0x00000008
-#define BCHP_NAND_DDR_PHY_BIST_STAT_W0_DATA_WRPH_ERR_SHIFT 3
-
-/* NAND :: DDR_PHY_BIST_STAT :: W1_ADDR_ERR [02:02] */
-#define BCHP_NAND_DDR_PHY_BIST_STAT_W1_ADDR_ERR_MASK 0x00000004
-#define BCHP_NAND_DDR_PHY_BIST_STAT_W1_ADDR_ERR_SHIFT 2
-
-/* NAND :: DDR_PHY_BIST_STAT :: W0_ADDR_ERR [01:01] */
-#define BCHP_NAND_DDR_PHY_BIST_STAT_W0_ADDR_ERR_MASK 0x00000002
-#define BCHP_NAND_DDR_PHY_BIST_STAT_W0_ADDR_ERR_SHIFT 1
-
-/* NAND :: DDR_PHY_BIST_STAT :: BIST_DONE [00:00] */
-#define BCHP_NAND_DDR_PHY_BIST_STAT_BIST_DONE_MASK 0x00000001
-#define BCHP_NAND_DDR_PHY_BIST_STAT_BIST_DONE_SHIFT 0
-
-/***************************************************************************
- *DDR_DIAG_STAT0 - Nand Flash DDR DIAG STATUS0
- ***************************************************************************/
-/* NAND :: DDR_DIAG_STAT0 :: DIAG_STATUS [31:00] */
-#define BCHP_NAND_DDR_DIAG_STAT0_DIAG_STATUS_MASK 0xffffffff
-#define BCHP_NAND_DDR_DIAG_STAT0_DIAG_STATUS_SHIFT 0
-
-/***************************************************************************
- *DDR_DIAG_STAT1 - Nand Flash DDR DIAG STATUS1
- ***************************************************************************/
-/* NAND :: DDR_DIAG_STAT1 :: DIAG_STATUS [31:00] */
-#define BCHP_NAND_DDR_DIAG_STAT1_DIAG_STATUS_MASK 0xffffffff
-#define BCHP_NAND_DDR_DIAG_STAT1_DIAG_STATUS_SHIFT 0
-
-/***************************************************************************
- *FLASH_CACHE%i - Flash Cache Buffer Read Access
- ***************************************************************************/
-#define BCHP_NAND_FLASH_CACHEi_ARRAY_BASE 0x00442c00
-#define BCHP_NAND_FLASH_CACHEi_ARRAY_START 0
-#define BCHP_NAND_FLASH_CACHEi_ARRAY_END 127
-#define BCHP_NAND_FLASH_CACHEi_ARRAY_ELEMENT_SIZE 32
-
-/***************************************************************************
- *FLASH_CACHE%i - Flash Cache Buffer Read Access
- ***************************************************************************/
-/* NAND :: FLASH_CACHEi :: WORD [31:00] */
-#define BCHP_NAND_FLASH_CACHEi_WORD_MASK 0xffffffff
-#define BCHP_NAND_FLASH_CACHEi_WORD_SHIFT 0
-
-
-#endif /* #ifndef BCHP_NAND_H__ */
-
-/* End of File */
diff --git a/include/linux/brcmstb/7366b0/bchp_pcie_0_dma.h b/include/linux/brcmstb/7366b0/bchp_pcie_0_dma.h
deleted file mode 100644
index b5d3988..0000000
--- a/include/linux/brcmstb/7366b0/bchp_pcie_0_dma.h
+++ /dev/null
@@ -1,735 +0,0 @@
-/***************************************************************************
- * Copyright (c) 1999-2013, Broadcom Corporation
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
- *
- * Module Description:
- * DO NOT EDIT THIS FILE DIRECTLY
- *
- * This module was generated magically with RDB from a source description
- * file. You must edit the source file for changes to be made to this file.
- *
- *
- * Date: Generated on Sat Apr 20 03:07:44 2013
- * MD5 Checksum d41d8cd98f00b204e9800998ecf8427e
- *
- * Compiled with: RDB Utility combo_header.pl
- * RDB Parser 3.0
- * unknown unknown
- * Perl Interpreter 5.008008
- * Operating System linux
- *
- * Revision History:
- *
- * $brcm_Log: $
- *
- ***************************************************************************/
-
-#ifndef BCHP_PCIE_0_DMA_H__
-#define BCHP_PCIE_0_DMA_H__
-
-/***************************************************************************
- *PCIE_0_DMA - PCI-E DMA Registers
- ***************************************************************************/
-#define BCHP_PCIE_0_DMA_TX_FIRST_DESC_L_ADDR_LIST0 0x00474400 /* Tx Descriptor List0 First Descriptor lower Address */
-#define BCHP_PCIE_0_DMA_TX_FIRST_DESC_U_ADDR_LIST0 0x00474404 /* Tx Descriptor List0 First Descriptor Upper Address */
-#define BCHP_PCIE_0_DMA_TX_FIRST_DESC_L_ADDR_LIST1 0x00474408 /* Tx Descriptor List1 First Descriptor Lower Address */
-#define BCHP_PCIE_0_DMA_TX_FIRST_DESC_U_ADDR_LIST1 0x0047440c /* Tx Descriptor List1 First Descriptor Upper Address */
-#define BCHP_PCIE_0_DMA_TX_SW_DESC_LIST_CTRL_STS 0x00474410 /* Tx Software Descriptor List Control and Status */
-#define BCHP_PCIE_0_DMA_TX_WAKE_CTRL 0x00474414 /* Tx Wake Control */
-#define BCHP_PCIE_0_DMA_TX_ERROR_STATUS 0x00474418 /* Tx Engine Error Status */
-#define BCHP_PCIE_0_DMA_TX_LIST0_CUR_DESC_L_ADDR 0x0047441c /* Tx List0 Current Descriptor Lower Address */
-#define BCHP_PCIE_0_DMA_TX_LIST0_CUR_DESC_U_ADDR 0x00474420 /* Tx List0 Current Descriptor Upper Address */
-#define BCHP_PCIE_0_DMA_TX_LIST0_CUR_BYTE_CNT 0x00474424 /* Tx List0 Current Descriptor Byte Count */
-#define BCHP_PCIE_0_DMA_TX_LIST1_CUR_DESC_L_ADDR 0x00474428 /* Tx List1 Current Descriptor Lower Address */
-#define BCHP_PCIE_0_DMA_TX_LIST1_CUR_DESC_U_ADDR 0x0047442c /* Tx List1 Current Descriptor Upper Address */
-#define BCHP_PCIE_0_DMA_TX_LIST1_CUR_BYTE_CNT 0x00474430 /* Tx List1 Current Descriptor Byte Count */
-#define BCHP_PCIE_0_DMA_RX_FIRST_DESC_L_ADDR_LIST0 0x00474434 /* Rx Descriptor List0 First Descriptor Lower Address */
-#define BCHP_PCIE_0_DMA_RX_FIRST_DESC_U_ADDR_LIST0 0x00474438 /* Rx Descriptor List0 First Descriptor Upper Address */
-#define BCHP_PCIE_0_DMA_RX_FIRST_DESC_L_ADDR_LIST1 0x0047443c /* Rx Descriptor List1 First Descriptor Lower Address */
-#define BCHP_PCIE_0_DMA_RX_FIRST_DESC_U_ADDR_LIST1 0x00474440 /* Rx Descriptor List1 First Descriptor Upper Address */
-#define BCHP_PCIE_0_DMA_RX_SW_DESC_LIST_CTRL_STS 0x00474444 /* Rx Software Descriptor List Control and Status */
-#define BCHP_PCIE_0_DMA_RX_WAKE_CTRL 0x00474448 /* Rx DMA Wake Control */
-#define BCHP_PCIE_0_DMA_RX_ERROR_STATUS 0x0047444c /* Rx Engine Error Status */
-#define BCHP_PCIE_0_DMA_RX_LIST0_CUR_DESC_L_ADDR 0x00474450 /* Rx List0 Current Descriptor Lower Address */
-#define BCHP_PCIE_0_DMA_RX_LIST0_CUR_DESC_U_ADDR 0x00474454 /* Rx List0 Current Descriptor Upper Address */
-#define BCHP_PCIE_0_DMA_RX_LIST0_CUR_BYTE_CNT 0x00474458 /* Rx List0 Current Descriptor Byte Count */
-#define BCHP_PCIE_0_DMA_RX_LIST1_CUR_DESC_L_ADDR 0x0047445c /* Rx List1 Current Descriptor Lower address */
-#define BCHP_PCIE_0_DMA_RX_LIST1_CUR_DESC_U_ADDR 0x00474460 /* Rx List1 Current Descriptor Upper address */
-#define BCHP_PCIE_0_DMA_RX_LIST1_CUR_BYTE_CNT 0x00474464 /* Rx List1 Current Descriptor Byte Count */
-#define BCHP_PCIE_0_DMA_DMA_DEBUG_OPTIONS_REG 0x00474468 /* DMA Debug Options Register */
-#define BCHP_PCIE_0_DMA_READ_CHANNEL_ERROR_STATUS 0x0047446c /* Read Channel Error Status */
-
-/***************************************************************************
- *TX_FIRST_DESC_L_ADDR_LIST0 - Tx Descriptor List0 First Descriptor lower Address
- ***************************************************************************/
-/* PCIE_0_DMA :: TX_FIRST_DESC_L_ADDR_LIST0 :: DESC_ADDR [31:05] */
-#define BCHP_PCIE_0_DMA_TX_FIRST_DESC_L_ADDR_LIST0_DESC_ADDR_MASK 0xffffffe0
-#define BCHP_PCIE_0_DMA_TX_FIRST_DESC_L_ADDR_LIST0_DESC_ADDR_SHIFT 5
-#define BCHP_PCIE_0_DMA_TX_FIRST_DESC_L_ADDR_LIST0_DESC_ADDR_DEFAULT 0x00000000
-
-/* PCIE_0_DMA :: TX_FIRST_DESC_L_ADDR_LIST0 :: reserved0 [04:01] */
-#define BCHP_PCIE_0_DMA_TX_FIRST_DESC_L_ADDR_LIST0_reserved0_MASK 0x0000001e
-#define BCHP_PCIE_0_DMA_TX_FIRST_DESC_L_ADDR_LIST0_reserved0_SHIFT 1
-
-/* PCIE_0_DMA :: TX_FIRST_DESC_L_ADDR_LIST0 :: TX_DESC_LIST0_VALID [00:00] */
-#define BCHP_PCIE_0_DMA_TX_FIRST_DESC_L_ADDR_LIST0_TX_DESC_LIST0_VALID_MASK 0x00000001
-#define BCHP_PCIE_0_DMA_TX_FIRST_DESC_L_ADDR_LIST0_TX_DESC_LIST0_VALID_SHIFT 0
-#define BCHP_PCIE_0_DMA_TX_FIRST_DESC_L_ADDR_LIST0_TX_DESC_LIST0_VALID_DEFAULT 0x00000000
-
-/***************************************************************************
- *TX_FIRST_DESC_U_ADDR_LIST0 - Tx Descriptor List0 First Descriptor Upper Address
- ***************************************************************************/
-/* PCIE_0_DMA :: TX_FIRST_DESC_U_ADDR_LIST0 :: DESC_ADDR [31:00] */
-#define BCHP_PCIE_0_DMA_TX_FIRST_DESC_U_ADDR_LIST0_DESC_ADDR_MASK 0xffffffff
-#define BCHP_PCIE_0_DMA_TX_FIRST_DESC_U_ADDR_LIST0_DESC_ADDR_SHIFT 0
-#define BCHP_PCIE_0_DMA_TX_FIRST_DESC_U_ADDR_LIST0_DESC_ADDR_DEFAULT 0x00000000
-
-/***************************************************************************
- *TX_FIRST_DESC_L_ADDR_LIST1 - Tx Descriptor List1 First Descriptor Lower Address
- ***************************************************************************/
-/* PCIE_0_DMA :: TX_FIRST_DESC_L_ADDR_LIST1 :: DESC_ADDR [31:05] */
-#define BCHP_PCIE_0_DMA_TX_FIRST_DESC_L_ADDR_LIST1_DESC_ADDR_MASK 0xffffffe0
-#define BCHP_PCIE_0_DMA_TX_FIRST_DESC_L_ADDR_LIST1_DESC_ADDR_SHIFT 5
-#define BCHP_PCIE_0_DMA_TX_FIRST_DESC_L_ADDR_LIST1_DESC_ADDR_DEFAULT 0x00000000
-
-/* PCIE_0_DMA :: TX_FIRST_DESC_L_ADDR_LIST1 :: reserved0 [04:01] */
-#define BCHP_PCIE_0_DMA_TX_FIRST_DESC_L_ADDR_LIST1_reserved0_MASK 0x0000001e
-#define BCHP_PCIE_0_DMA_TX_FIRST_DESC_L_ADDR_LIST1_reserved0_SHIFT 1
-
-/* PCIE_0_DMA :: TX_FIRST_DESC_L_ADDR_LIST1 :: TX_DESC_LIST1_VALID [00:00] */
-#define BCHP_PCIE_0_DMA_TX_FIRST_DESC_L_ADDR_LIST1_TX_DESC_LIST1_VALID_MASK 0x00000001
-#define BCHP_PCIE_0_DMA_TX_FIRST_DESC_L_ADDR_LIST1_TX_DESC_LIST1_VALID_SHIFT 0
-#define BCHP_PCIE_0_DMA_TX_FIRST_DESC_L_ADDR_LIST1_TX_DESC_LIST1_VALID_DEFAULT 0x00000000
-
-/***************************************************************************
- *TX_FIRST_DESC_U_ADDR_LIST1 - Tx Descriptor List1 First Descriptor Upper Address
- ***************************************************************************/
-/* PCIE_0_DMA :: TX_FIRST_DESC_U_ADDR_LIST1 :: DESC_ADDR [31:00] */
-#define BCHP_PCIE_0_DMA_TX_FIRST_DESC_U_ADDR_LIST1_DESC_ADDR_MASK 0xffffffff
-#define BCHP_PCIE_0_DMA_TX_FIRST_DESC_U_ADDR_LIST1_DESC_ADDR_SHIFT 0
-#define BCHP_PCIE_0_DMA_TX_FIRST_DESC_U_ADDR_LIST1_DESC_ADDR_DEFAULT 0x00000000
-
-/***************************************************************************
- *TX_SW_DESC_LIST_CTRL_STS - Tx Software Descriptor List Control and Status
- ***************************************************************************/
-/* PCIE_0_DMA :: TX_SW_DESC_LIST_CTRL_STS :: reserved0 [31:20] */
-#define BCHP_PCIE_0_DMA_TX_SW_DESC_LIST_CTRL_STS_reserved0_MASK 0xfff00000
-#define BCHP_PCIE_0_DMA_TX_SW_DESC_LIST_CTRL_STS_reserved0_SHIFT 20
-
-/* PCIE_0_DMA :: TX_SW_DESC_LIST_CTRL_STS :: BURST_SIZE_OVERRIDE [19:19] */
-#define BCHP_PCIE_0_DMA_TX_SW_DESC_LIST_CTRL_STS_BURST_SIZE_OVERRIDE_MASK 0x00080000
-#define BCHP_PCIE_0_DMA_TX_SW_DESC_LIST_CTRL_STS_BURST_SIZE_OVERRIDE_SHIFT 19
-#define BCHP_PCIE_0_DMA_TX_SW_DESC_LIST_CTRL_STS_BURST_SIZE_OVERRIDE_DEFAULT 0x00000000
-
-/* PCIE_0_DMA :: TX_SW_DESC_LIST_CTRL_STS :: BURST_SIZE_OVERRIDE_VALUE [18:16] */
-#define BCHP_PCIE_0_DMA_TX_SW_DESC_LIST_CTRL_STS_BURST_SIZE_OVERRIDE_VALUE_MASK 0x00070000
-#define BCHP_PCIE_0_DMA_TX_SW_DESC_LIST_CTRL_STS_BURST_SIZE_OVERRIDE_VALUE_SHIFT 16
-#define BCHP_PCIE_0_DMA_TX_SW_DESC_LIST_CTRL_STS_BURST_SIZE_OVERRIDE_VALUE_DEFAULT 0x00000000
-
-/* PCIE_0_DMA :: TX_SW_DESC_LIST_CTRL_STS :: reserved1 [15:14] */
-#define BCHP_PCIE_0_DMA_TX_SW_DESC_LIST_CTRL_STS_reserved1_MASK 0x0000c000
-#define BCHP_PCIE_0_DMA_TX_SW_DESC_LIST_CTRL_STS_reserved1_SHIFT 14
-
-/* PCIE_0_DMA :: TX_SW_DESC_LIST_CTRL_STS :: DESC_ENDIAN_MODE [13:12] */
-#define BCHP_PCIE_0_DMA_TX_SW_DESC_LIST_CTRL_STS_DESC_ENDIAN_MODE_MASK 0x00003000
-#define BCHP_PCIE_0_DMA_TX_SW_DESC_LIST_CTRL_STS_DESC_ENDIAN_MODE_SHIFT 12
-#define BCHP_PCIE_0_DMA_TX_SW_DESC_LIST_CTRL_STS_DESC_ENDIAN_MODE_DEFAULT 0x00000000
-
-/* PCIE_0_DMA :: TX_SW_DESC_LIST_CTRL_STS :: reserved2 [11:10] */
-#define BCHP_PCIE_0_DMA_TX_SW_DESC_LIST_CTRL_STS_reserved2_MASK 0x00000c00
-#define BCHP_PCIE_0_DMA_TX_SW_DESC_LIST_CTRL_STS_reserved2_SHIFT 10
-
-/* PCIE_0_DMA :: TX_SW_DESC_LIST_CTRL_STS :: LOCAL_DESC [09:09] */
-#define BCHP_PCIE_0_DMA_TX_SW_DESC_LIST_CTRL_STS_LOCAL_DESC_MASK 0x00000200
-#define BCHP_PCIE_0_DMA_TX_SW_DESC_LIST_CTRL_STS_LOCAL_DESC_SHIFT 9
-#define BCHP_PCIE_0_DMA_TX_SW_DESC_LIST_CTRL_STS_LOCAL_DESC_DEFAULT 0x00000000
-
-/* PCIE_0_DMA :: TX_SW_DESC_LIST_CTRL_STS :: DMA_MODE [08:08] */
-#define BCHP_PCIE_0_DMA_TX_SW_DESC_LIST_CTRL_STS_DMA_MODE_MASK 0x00000100
-#define BCHP_PCIE_0_DMA_TX_SW_DESC_LIST_CTRL_STS_DMA_MODE_SHIFT 8
-#define BCHP_PCIE_0_DMA_TX_SW_DESC_LIST_CTRL_STS_DMA_MODE_DEFAULT 0x00000000
-
-/* PCIE_0_DMA :: TX_SW_DESC_LIST_CTRL_STS :: reserved3 [07:06] */
-#define BCHP_PCIE_0_DMA_TX_SW_DESC_LIST_CTRL_STS_reserved3_MASK 0x000000c0
-#define BCHP_PCIE_0_DMA_TX_SW_DESC_LIST_CTRL_STS_reserved3_SHIFT 6
-
-/* PCIE_0_DMA :: TX_SW_DESC_LIST_CTRL_STS :: DMA_STATUS [05:04] */
-#define BCHP_PCIE_0_DMA_TX_SW_DESC_LIST_CTRL_STS_DMA_STATUS_MASK 0x00000030
-#define BCHP_PCIE_0_DMA_TX_SW_DESC_LIST_CTRL_STS_DMA_STATUS_SHIFT 4
-#define BCHP_PCIE_0_DMA_TX_SW_DESC_LIST_CTRL_STS_DMA_STATUS_DEFAULT 0x00000000
-
-/* PCIE_0_DMA :: TX_SW_DESC_LIST_CTRL_STS :: DMA_DATA_SERV_PTR [03:03] */
-#define BCHP_PCIE_0_DMA_TX_SW_DESC_LIST_CTRL_STS_DMA_DATA_SERV_PTR_MASK 0x00000008
-#define BCHP_PCIE_0_DMA_TX_SW_DESC_LIST_CTRL_STS_DMA_DATA_SERV_PTR_SHIFT 3
-#define BCHP_PCIE_0_DMA_TX_SW_DESC_LIST_CTRL_STS_DMA_DATA_SERV_PTR_DEFAULT 0x00000000
-
-/* PCIE_0_DMA :: TX_SW_DESC_LIST_CTRL_STS :: DESC_SERV_PTR [02:02] */
-#define BCHP_PCIE_0_DMA_TX_SW_DESC_LIST_CTRL_STS_DESC_SERV_PTR_MASK 0x00000004
-#define BCHP_PCIE_0_DMA_TX_SW_DESC_LIST_CTRL_STS_DESC_SERV_PTR_SHIFT 2
-#define BCHP_PCIE_0_DMA_TX_SW_DESC_LIST_CTRL_STS_DESC_SERV_PTR_DEFAULT 0x00000000
-
-/* PCIE_0_DMA :: TX_SW_DESC_LIST_CTRL_STS :: reserved4 [01:01] */
-#define BCHP_PCIE_0_DMA_TX_SW_DESC_LIST_CTRL_STS_reserved4_MASK 0x00000002
-#define BCHP_PCIE_0_DMA_TX_SW_DESC_LIST_CTRL_STS_reserved4_SHIFT 1
-
-/* PCIE_0_DMA :: TX_SW_DESC_LIST_CTRL_STS :: TX_DMA_RUN_STOP [00:00] */
-#define BCHP_PCIE_0_DMA_TX_SW_DESC_LIST_CTRL_STS_TX_DMA_RUN_STOP_MASK 0x00000001
-#define BCHP_PCIE_0_DMA_TX_SW_DESC_LIST_CTRL_STS_TX_DMA_RUN_STOP_SHIFT 0
-#define BCHP_PCIE_0_DMA_TX_SW_DESC_LIST_CTRL_STS_TX_DMA_RUN_STOP_DEFAULT 0x00000000
-
-/***************************************************************************
- *TX_WAKE_CTRL - Tx Wake Control
- ***************************************************************************/
-/* PCIE_0_DMA :: TX_WAKE_CTRL :: reserved0 [31:02] */
-#define BCHP_PCIE_0_DMA_TX_WAKE_CTRL_reserved0_MASK 0xfffffffc
-#define BCHP_PCIE_0_DMA_TX_WAKE_CTRL_reserved0_SHIFT 2
-
-/* PCIE_0_DMA :: TX_WAKE_CTRL :: WAKE_MODE [01:01] */
-#define BCHP_PCIE_0_DMA_TX_WAKE_CTRL_WAKE_MODE_MASK 0x00000002
-#define BCHP_PCIE_0_DMA_TX_WAKE_CTRL_WAKE_MODE_SHIFT 1
-#define BCHP_PCIE_0_DMA_TX_WAKE_CTRL_WAKE_MODE_DEFAULT 0x00000000
-
-/* PCIE_0_DMA :: TX_WAKE_CTRL :: WAKE [00:00] */
-#define BCHP_PCIE_0_DMA_TX_WAKE_CTRL_WAKE_MASK 0x00000001
-#define BCHP_PCIE_0_DMA_TX_WAKE_CTRL_WAKE_SHIFT 0
-#define BCHP_PCIE_0_DMA_TX_WAKE_CTRL_WAKE_DEFAULT 0x00000000
-
-/***************************************************************************
- *TX_ERROR_STATUS - Tx Engine Error Status
- ***************************************************************************/
-/* PCIE_0_DMA :: TX_ERROR_STATUS :: reserved0 [31:10] */
-#define BCHP_PCIE_0_DMA_TX_ERROR_STATUS_reserved0_MASK 0xfffffc00
-#define BCHP_PCIE_0_DMA_TX_ERROR_STATUS_reserved0_SHIFT 10
-
-/* PCIE_0_DMA :: TX_ERROR_STATUS :: TX_L1_DESC_TX_ABORT_ERRORS [09:09] */
-#define BCHP_PCIE_0_DMA_TX_ERROR_STATUS_TX_L1_DESC_TX_ABORT_ERRORS_MASK 0x00000200
-#define BCHP_PCIE_0_DMA_TX_ERROR_STATUS_TX_L1_DESC_TX_ABORT_ERRORS_SHIFT 9
-#define BCHP_PCIE_0_DMA_TX_ERROR_STATUS_TX_L1_DESC_TX_ABORT_ERRORS_DEFAULT 0x00000000
-
-/* PCIE_0_DMA :: TX_ERROR_STATUS :: reserved1 [08:08] */
-#define BCHP_PCIE_0_DMA_TX_ERROR_STATUS_reserved1_MASK 0x00000100
-#define BCHP_PCIE_0_DMA_TX_ERROR_STATUS_reserved1_SHIFT 8
-
-/* PCIE_0_DMA :: TX_ERROR_STATUS :: TX_L0_DESC_TX_ABORT_ERRORS [07:07] */
-#define BCHP_PCIE_0_DMA_TX_ERROR_STATUS_TX_L0_DESC_TX_ABORT_ERRORS_MASK 0x00000080
-#define BCHP_PCIE_0_DMA_TX_ERROR_STATUS_TX_L0_DESC_TX_ABORT_ERRORS_SHIFT 7
-#define BCHP_PCIE_0_DMA_TX_ERROR_STATUS_TX_L0_DESC_TX_ABORT_ERRORS_DEFAULT 0x00000000
-
-/* PCIE_0_DMA :: TX_ERROR_STATUS :: reserved2 [06:06] */
-#define BCHP_PCIE_0_DMA_TX_ERROR_STATUS_reserved2_MASK 0x00000040
-#define BCHP_PCIE_0_DMA_TX_ERROR_STATUS_reserved2_SHIFT 6
-
-/* PCIE_0_DMA :: TX_ERROR_STATUS :: TX_L1_DATA_TX_ABORT_ERRORS [05:05] */
-#define BCHP_PCIE_0_DMA_TX_ERROR_STATUS_TX_L1_DATA_TX_ABORT_ERRORS_MASK 0x00000020
-#define BCHP_PCIE_0_DMA_TX_ERROR_STATUS_TX_L1_DATA_TX_ABORT_ERRORS_SHIFT 5
-#define BCHP_PCIE_0_DMA_TX_ERROR_STATUS_TX_L1_DATA_TX_ABORT_ERRORS_DEFAULT 0x00000000
-
-/* PCIE_0_DMA :: TX_ERROR_STATUS :: TX_L1_REPIN_ERRORS [04:04] */
-#define BCHP_PCIE_0_DMA_TX_ERROR_STATUS_TX_L1_REPIN_ERRORS_MASK 0x00000010
-#define BCHP_PCIE_0_DMA_TX_ERROR_STATUS_TX_L1_REPIN_ERRORS_SHIFT 4
-#define BCHP_PCIE_0_DMA_TX_ERROR_STATUS_TX_L1_REPIN_ERRORS_DEFAULT 0x00000000
-
-/* PCIE_0_DMA :: TX_ERROR_STATUS :: reserved3 [03:03] */
-#define BCHP_PCIE_0_DMA_TX_ERROR_STATUS_reserved3_MASK 0x00000008
-#define BCHP_PCIE_0_DMA_TX_ERROR_STATUS_reserved3_SHIFT 3
-
-/* PCIE_0_DMA :: TX_ERROR_STATUS :: TX_L0_DATA_TX_ABORT_ERRORS [02:02] */
-#define BCHP_PCIE_0_DMA_TX_ERROR_STATUS_TX_L0_DATA_TX_ABORT_ERRORS_MASK 0x00000004
-#define BCHP_PCIE_0_DMA_TX_ERROR_STATUS_TX_L0_DATA_TX_ABORT_ERRORS_SHIFT 2
-#define BCHP_PCIE_0_DMA_TX_ERROR_STATUS_TX_L0_DATA_TX_ABORT_ERRORS_DEFAULT 0x00000000
-
-/* PCIE_0_DMA :: TX_ERROR_STATUS :: TX_L0_REPIN_ERRORS [01:01] */
-#define BCHP_PCIE_0_DMA_TX_ERROR_STATUS_TX_L0_REPIN_ERRORS_MASK 0x00000002
-#define BCHP_PCIE_0_DMA_TX_ERROR_STATUS_TX_L0_REPIN_ERRORS_SHIFT 1
-#define BCHP_PCIE_0_DMA_TX_ERROR_STATUS_TX_L0_REPIN_ERRORS_DEFAULT 0x00000000
-
-/* PCIE_0_DMA :: TX_ERROR_STATUS :: reserved4 [00:00] */
-#define BCHP_PCIE_0_DMA_TX_ERROR_STATUS_reserved4_MASK 0x00000001
-#define BCHP_PCIE_0_DMA_TX_ERROR_STATUS_reserved4_SHIFT 0
-
-/***************************************************************************
- *TX_LIST0_CUR_DESC_L_ADDR - Tx List0 Current Descriptor Lower Address
- ***************************************************************************/
-/* PCIE_0_DMA :: TX_LIST0_CUR_DESC_L_ADDR :: TX_L0_CUR_DESC_L_ADDR [31:05] */
-#define BCHP_PCIE_0_DMA_TX_LIST0_CUR_DESC_L_ADDR_TX_L0_CUR_DESC_L_ADDR_MASK 0xffffffe0
-#define BCHP_PCIE_0_DMA_TX_LIST0_CUR_DESC_L_ADDR_TX_L0_CUR_DESC_L_ADDR_SHIFT 5
-#define BCHP_PCIE_0_DMA_TX_LIST0_CUR_DESC_L_ADDR_TX_L0_CUR_DESC_L_ADDR_DEFAULT 0x00000000
-
-/* PCIE_0_DMA :: TX_LIST0_CUR_DESC_L_ADDR :: reserved0 [04:04] */
-#define BCHP_PCIE_0_DMA_TX_LIST0_CUR_DESC_L_ADDR_reserved0_MASK 0x00000010
-#define BCHP_PCIE_0_DMA_TX_LIST0_CUR_DESC_L_ADDR_reserved0_SHIFT 4
-
-/* PCIE_0_DMA :: TX_LIST0_CUR_DESC_L_ADDR :: TX_L0_CUR_LIST [03:03] */
-#define BCHP_PCIE_0_DMA_TX_LIST0_CUR_DESC_L_ADDR_TX_L0_CUR_LIST_MASK 0x00000008
-#define BCHP_PCIE_0_DMA_TX_LIST0_CUR_DESC_L_ADDR_TX_L0_CUR_LIST_SHIFT 3
-#define BCHP_PCIE_0_DMA_TX_LIST0_CUR_DESC_L_ADDR_TX_L0_CUR_LIST_DEFAULT 0x00000000
-
-/* PCIE_0_DMA :: TX_LIST0_CUR_DESC_L_ADDR :: TX_L0_CUR_IN_PROGRESS [02:02] */
-#define BCHP_PCIE_0_DMA_TX_LIST0_CUR_DESC_L_ADDR_TX_L0_CUR_IN_PROGRESS_MASK 0x00000004
-#define BCHP_PCIE_0_DMA_TX_LIST0_CUR_DESC_L_ADDR_TX_L0_CUR_IN_PROGRESS_SHIFT 2
-#define BCHP_PCIE_0_DMA_TX_LIST0_CUR_DESC_L_ADDR_TX_L0_CUR_IN_PROGRESS_DEFAULT 0x00000000
-
-/* PCIE_0_DMA :: TX_LIST0_CUR_DESC_L_ADDR :: TX_L0_CUR_STATUS [01:00] */
-#define BCHP_PCIE_0_DMA_TX_LIST0_CUR_DESC_L_ADDR_TX_L0_CUR_STATUS_MASK 0x00000003
-#define BCHP_PCIE_0_DMA_TX_LIST0_CUR_DESC_L_ADDR_TX_L0_CUR_STATUS_SHIFT 0
-#define BCHP_PCIE_0_DMA_TX_LIST0_CUR_DESC_L_ADDR_TX_L0_CUR_STATUS_DEFAULT 0x00000000
-
-/***************************************************************************
- *TX_LIST0_CUR_DESC_U_ADDR - Tx List0 Current Descriptor Upper Address
- ***************************************************************************/
-/* PCIE_0_DMA :: TX_LIST0_CUR_DESC_U_ADDR :: TX_L0_CUR_DESC_U_ADDR [31:00] */
-#define BCHP_PCIE_0_DMA_TX_LIST0_CUR_DESC_U_ADDR_TX_L0_CUR_DESC_U_ADDR_MASK 0xffffffff
-#define BCHP_PCIE_0_DMA_TX_LIST0_CUR_DESC_U_ADDR_TX_L0_CUR_DESC_U_ADDR_SHIFT 0
-#define BCHP_PCIE_0_DMA_TX_LIST0_CUR_DESC_U_ADDR_TX_L0_CUR_DESC_U_ADDR_DEFAULT 0x00000000
-
-/***************************************************************************
- *TX_LIST0_CUR_BYTE_CNT - Tx List0 Current Descriptor Byte Count
- ***************************************************************************/
-/* PCIE_0_DMA :: TX_LIST0_CUR_BYTE_CNT :: TX_L0_CUR_BYTE_CNT [31:00] */
-#define BCHP_PCIE_0_DMA_TX_LIST0_CUR_BYTE_CNT_TX_L0_CUR_BYTE_CNT_MASK 0xffffffff
-#define BCHP_PCIE_0_DMA_TX_LIST0_CUR_BYTE_CNT_TX_L0_CUR_BYTE_CNT_SHIFT 0
-#define BCHP_PCIE_0_DMA_TX_LIST0_CUR_BYTE_CNT_TX_L0_CUR_BYTE_CNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *TX_LIST1_CUR_DESC_L_ADDR - Tx List1 Current Descriptor Lower Address
- ***************************************************************************/
-/* PCIE_0_DMA :: TX_LIST1_CUR_DESC_L_ADDR :: TX_L1_CUR_DESC_L_ADDR [31:05] */
-#define BCHP_PCIE_0_DMA_TX_LIST1_CUR_DESC_L_ADDR_TX_L1_CUR_DESC_L_ADDR_MASK 0xffffffe0
-#define BCHP_PCIE_0_DMA_TX_LIST1_CUR_DESC_L_ADDR_TX_L1_CUR_DESC_L_ADDR_SHIFT 5
-#define BCHP_PCIE_0_DMA_TX_LIST1_CUR_DESC_L_ADDR_TX_L1_CUR_DESC_L_ADDR_DEFAULT 0x00000000
-
-/* PCIE_0_DMA :: TX_LIST1_CUR_DESC_L_ADDR :: reserved0 [04:04] */
-#define BCHP_PCIE_0_DMA_TX_LIST1_CUR_DESC_L_ADDR_reserved0_MASK 0x00000010
-#define BCHP_PCIE_0_DMA_TX_LIST1_CUR_DESC_L_ADDR_reserved0_SHIFT 4
-
-/* PCIE_0_DMA :: TX_LIST1_CUR_DESC_L_ADDR :: TX_L1_CUR_LIST [03:03] */
-#define BCHP_PCIE_0_DMA_TX_LIST1_CUR_DESC_L_ADDR_TX_L1_CUR_LIST_MASK 0x00000008
-#define BCHP_PCIE_0_DMA_TX_LIST1_CUR_DESC_L_ADDR_TX_L1_CUR_LIST_SHIFT 3
-#define BCHP_PCIE_0_DMA_TX_LIST1_CUR_DESC_L_ADDR_TX_L1_CUR_LIST_DEFAULT 0x00000000
-
-/* PCIE_0_DMA :: TX_LIST1_CUR_DESC_L_ADDR :: TX_L1_CUR_IN_PROGRESS [02:02] */
-#define BCHP_PCIE_0_DMA_TX_LIST1_CUR_DESC_L_ADDR_TX_L1_CUR_IN_PROGRESS_MASK 0x00000004
-#define BCHP_PCIE_0_DMA_TX_LIST1_CUR_DESC_L_ADDR_TX_L1_CUR_IN_PROGRESS_SHIFT 2
-#define BCHP_PCIE_0_DMA_TX_LIST1_CUR_DESC_L_ADDR_TX_L1_CUR_IN_PROGRESS_DEFAULT 0x00000000
-
-/* PCIE_0_DMA :: TX_LIST1_CUR_DESC_L_ADDR :: TX_L1_CUR_STATUS [01:00] */
-#define BCHP_PCIE_0_DMA_TX_LIST1_CUR_DESC_L_ADDR_TX_L1_CUR_STATUS_MASK 0x00000003
-#define BCHP_PCIE_0_DMA_TX_LIST1_CUR_DESC_L_ADDR_TX_L1_CUR_STATUS_SHIFT 0
-#define BCHP_PCIE_0_DMA_TX_LIST1_CUR_DESC_L_ADDR_TX_L1_CUR_STATUS_DEFAULT 0x00000000
-
-/***************************************************************************
- *TX_LIST1_CUR_DESC_U_ADDR - Tx List1 Current Descriptor Upper Address
- ***************************************************************************/
-/* PCIE_0_DMA :: TX_LIST1_CUR_DESC_U_ADDR :: TX_L1_CUR_DESC_U_ADDR [31:00] */
-#define BCHP_PCIE_0_DMA_TX_LIST1_CUR_DESC_U_ADDR_TX_L1_CUR_DESC_U_ADDR_MASK 0xffffffff
-#define BCHP_PCIE_0_DMA_TX_LIST1_CUR_DESC_U_ADDR_TX_L1_CUR_DESC_U_ADDR_SHIFT 0
-#define BCHP_PCIE_0_DMA_TX_LIST1_CUR_DESC_U_ADDR_TX_L1_CUR_DESC_U_ADDR_DEFAULT 0x00000000
-
-/***************************************************************************
- *TX_LIST1_CUR_BYTE_CNT - Tx List1 Current Descriptor Byte Count
- ***************************************************************************/
-/* PCIE_0_DMA :: TX_LIST1_CUR_BYTE_CNT :: TX_L1_CUR_BYTE_CNT [31:00] */
-#define BCHP_PCIE_0_DMA_TX_LIST1_CUR_BYTE_CNT_TX_L1_CUR_BYTE_CNT_MASK 0xffffffff
-#define BCHP_PCIE_0_DMA_TX_LIST1_CUR_BYTE_CNT_TX_L1_CUR_BYTE_CNT_SHIFT 0
-#define BCHP_PCIE_0_DMA_TX_LIST1_CUR_BYTE_CNT_TX_L1_CUR_BYTE_CNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *RX_FIRST_DESC_L_ADDR_LIST0 - Rx Descriptor List0 First Descriptor Lower Address
- ***************************************************************************/
-/* PCIE_0_DMA :: RX_FIRST_DESC_L_ADDR_LIST0 :: DESC_ADDR [31:05] */
-#define BCHP_PCIE_0_DMA_RX_FIRST_DESC_L_ADDR_LIST0_DESC_ADDR_MASK 0xffffffe0
-#define BCHP_PCIE_0_DMA_RX_FIRST_DESC_L_ADDR_LIST0_DESC_ADDR_SHIFT 5
-#define BCHP_PCIE_0_DMA_RX_FIRST_DESC_L_ADDR_LIST0_DESC_ADDR_DEFAULT 0x00000000
-
-/* PCIE_0_DMA :: RX_FIRST_DESC_L_ADDR_LIST0 :: reserved0 [04:01] */
-#define BCHP_PCIE_0_DMA_RX_FIRST_DESC_L_ADDR_LIST0_reserved0_MASK 0x0000001e
-#define BCHP_PCIE_0_DMA_RX_FIRST_DESC_L_ADDR_LIST0_reserved0_SHIFT 1
-
-/* PCIE_0_DMA :: RX_FIRST_DESC_L_ADDR_LIST0 :: RX_DESC_LIST0_VALID [00:00] */
-#define BCHP_PCIE_0_DMA_RX_FIRST_DESC_L_ADDR_LIST0_RX_DESC_LIST0_VALID_MASK 0x00000001
-#define BCHP_PCIE_0_DMA_RX_FIRST_DESC_L_ADDR_LIST0_RX_DESC_LIST0_VALID_SHIFT 0
-#define BCHP_PCIE_0_DMA_RX_FIRST_DESC_L_ADDR_LIST0_RX_DESC_LIST0_VALID_DEFAULT 0x00000000
-
-/***************************************************************************
- *RX_FIRST_DESC_U_ADDR_LIST0 - Rx Descriptor List0 First Descriptor Upper Address
- ***************************************************************************/
-/* PCIE_0_DMA :: RX_FIRST_DESC_U_ADDR_LIST0 :: DESC_ADDR [31:00] */
-#define BCHP_PCIE_0_DMA_RX_FIRST_DESC_U_ADDR_LIST0_DESC_ADDR_MASK 0xffffffff
-#define BCHP_PCIE_0_DMA_RX_FIRST_DESC_U_ADDR_LIST0_DESC_ADDR_SHIFT 0
-#define BCHP_PCIE_0_DMA_RX_FIRST_DESC_U_ADDR_LIST0_DESC_ADDR_DEFAULT 0x00000000
-
-/***************************************************************************
- *RX_FIRST_DESC_L_ADDR_LIST1 - Rx Descriptor List1 First Descriptor Lower Address
- ***************************************************************************/
-/* PCIE_0_DMA :: RX_FIRST_DESC_L_ADDR_LIST1 :: DESC_ADDR [31:05] */
-#define BCHP_PCIE_0_DMA_RX_FIRST_DESC_L_ADDR_LIST1_DESC_ADDR_MASK 0xffffffe0
-#define BCHP_PCIE_0_DMA_RX_FIRST_DESC_L_ADDR_LIST1_DESC_ADDR_SHIFT 5
-#define BCHP_PCIE_0_DMA_RX_FIRST_DESC_L_ADDR_LIST1_DESC_ADDR_DEFAULT 0x00000000
-
-/* PCIE_0_DMA :: RX_FIRST_DESC_L_ADDR_LIST1 :: reserved0 [04:01] */
-#define BCHP_PCIE_0_DMA_RX_FIRST_DESC_L_ADDR_LIST1_reserved0_MASK 0x0000001e
-#define BCHP_PCIE_0_DMA_RX_FIRST_DESC_L_ADDR_LIST1_reserved0_SHIFT 1
-
-/* PCIE_0_DMA :: RX_FIRST_DESC_L_ADDR_LIST1 :: RX_DESC_LIST1_VALID [00:00] */
-#define BCHP_PCIE_0_DMA_RX_FIRST_DESC_L_ADDR_LIST1_RX_DESC_LIST1_VALID_MASK 0x00000001
-#define BCHP_PCIE_0_DMA_RX_FIRST_DESC_L_ADDR_LIST1_RX_DESC_LIST1_VALID_SHIFT 0
-#define BCHP_PCIE_0_DMA_RX_FIRST_DESC_L_ADDR_LIST1_RX_DESC_LIST1_VALID_DEFAULT 0x00000000
-
-/***************************************************************************
- *RX_FIRST_DESC_U_ADDR_LIST1 - Rx Descriptor List1 First Descriptor Upper Address
- ***************************************************************************/
-/* PCIE_0_DMA :: RX_FIRST_DESC_U_ADDR_LIST1 :: DESC_ADDR [31:00] */
-#define BCHP_PCIE_0_DMA_RX_FIRST_DESC_U_ADDR_LIST1_DESC_ADDR_MASK 0xffffffff
-#define BCHP_PCIE_0_DMA_RX_FIRST_DESC_U_ADDR_LIST1_DESC_ADDR_SHIFT 0
-#define BCHP_PCIE_0_DMA_RX_FIRST_DESC_U_ADDR_LIST1_DESC_ADDR_DEFAULT 0x00000000
-
-/***************************************************************************
- *RX_SW_DESC_LIST_CTRL_STS - Rx Software Descriptor List Control and Status
- ***************************************************************************/
-/* PCIE_0_DMA :: RX_SW_DESC_LIST_CTRL_STS :: reserved0 [31:20] */
-#define BCHP_PCIE_0_DMA_RX_SW_DESC_LIST_CTRL_STS_reserved0_MASK 0xfff00000
-#define BCHP_PCIE_0_DMA_RX_SW_DESC_LIST_CTRL_STS_reserved0_SHIFT 20
-
-/* PCIE_0_DMA :: RX_SW_DESC_LIST_CTRL_STS :: BURST_SIZE_OVERRIDE [19:19] */
-#define BCHP_PCIE_0_DMA_RX_SW_DESC_LIST_CTRL_STS_BURST_SIZE_OVERRIDE_MASK 0x00080000
-#define BCHP_PCIE_0_DMA_RX_SW_DESC_LIST_CTRL_STS_BURST_SIZE_OVERRIDE_SHIFT 19
-#define BCHP_PCIE_0_DMA_RX_SW_DESC_LIST_CTRL_STS_BURST_SIZE_OVERRIDE_DEFAULT 0x00000000
-
-/* PCIE_0_DMA :: RX_SW_DESC_LIST_CTRL_STS :: BURST_SIZE_OVERRIDE_VALUE [18:16] */
-#define BCHP_PCIE_0_DMA_RX_SW_DESC_LIST_CTRL_STS_BURST_SIZE_OVERRIDE_VALUE_MASK 0x00070000
-#define BCHP_PCIE_0_DMA_RX_SW_DESC_LIST_CTRL_STS_BURST_SIZE_OVERRIDE_VALUE_SHIFT 16
-#define BCHP_PCIE_0_DMA_RX_SW_DESC_LIST_CTRL_STS_BURST_SIZE_OVERRIDE_VALUE_DEFAULT 0x00000000
-
-/* PCIE_0_DMA :: RX_SW_DESC_LIST_CTRL_STS :: reserved1 [15:14] */
-#define BCHP_PCIE_0_DMA_RX_SW_DESC_LIST_CTRL_STS_reserved1_MASK 0x0000c000
-#define BCHP_PCIE_0_DMA_RX_SW_DESC_LIST_CTRL_STS_reserved1_SHIFT 14
-
-/* PCIE_0_DMA :: RX_SW_DESC_LIST_CTRL_STS :: DESC_ENDIAN_MODE [13:12] */
-#define BCHP_PCIE_0_DMA_RX_SW_DESC_LIST_CTRL_STS_DESC_ENDIAN_MODE_MASK 0x00003000
-#define BCHP_PCIE_0_DMA_RX_SW_DESC_LIST_CTRL_STS_DESC_ENDIAN_MODE_SHIFT 12
-#define BCHP_PCIE_0_DMA_RX_SW_DESC_LIST_CTRL_STS_DESC_ENDIAN_MODE_DEFAULT 0x00000000
-
-/* PCIE_0_DMA :: RX_SW_DESC_LIST_CTRL_STS :: reserved2 [11:10] */
-#define BCHP_PCIE_0_DMA_RX_SW_DESC_LIST_CTRL_STS_reserved2_MASK 0x00000c00
-#define BCHP_PCIE_0_DMA_RX_SW_DESC_LIST_CTRL_STS_reserved2_SHIFT 10
-
-/* PCIE_0_DMA :: RX_SW_DESC_LIST_CTRL_STS :: LOCAL_DESC [09:09] */
-#define BCHP_PCIE_0_DMA_RX_SW_DESC_LIST_CTRL_STS_LOCAL_DESC_MASK 0x00000200
-#define BCHP_PCIE_0_DMA_RX_SW_DESC_LIST_CTRL_STS_LOCAL_DESC_SHIFT 9
-#define BCHP_PCIE_0_DMA_RX_SW_DESC_LIST_CTRL_STS_LOCAL_DESC_DEFAULT 0x00000000
-
-/* PCIE_0_DMA :: RX_SW_DESC_LIST_CTRL_STS :: DMA_MODE [08:08] */
-#define BCHP_PCIE_0_DMA_RX_SW_DESC_LIST_CTRL_STS_DMA_MODE_MASK 0x00000100
-#define BCHP_PCIE_0_DMA_RX_SW_DESC_LIST_CTRL_STS_DMA_MODE_SHIFT 8
-#define BCHP_PCIE_0_DMA_RX_SW_DESC_LIST_CTRL_STS_DMA_MODE_DEFAULT 0x00000000
-
-/* PCIE_0_DMA :: RX_SW_DESC_LIST_CTRL_STS :: reserved3 [07:06] */
-#define BCHP_PCIE_0_DMA_RX_SW_DESC_LIST_CTRL_STS_reserved3_MASK 0x000000c0
-#define BCHP_PCIE_0_DMA_RX_SW_DESC_LIST_CTRL_STS_reserved3_SHIFT 6
-
-/* PCIE_0_DMA :: RX_SW_DESC_LIST_CTRL_STS :: DMA_STATUS [05:04] */
-#define BCHP_PCIE_0_DMA_RX_SW_DESC_LIST_CTRL_STS_DMA_STATUS_MASK 0x00000030
-#define BCHP_PCIE_0_DMA_RX_SW_DESC_LIST_CTRL_STS_DMA_STATUS_SHIFT 4
-#define BCHP_PCIE_0_DMA_RX_SW_DESC_LIST_CTRL_STS_DMA_STATUS_DEFAULT 0x00000000
-
-/* PCIE_0_DMA :: RX_SW_DESC_LIST_CTRL_STS :: DMA_DATA_SERV_PTR [03:03] */
-#define BCHP_PCIE_0_DMA_RX_SW_DESC_LIST_CTRL_STS_DMA_DATA_SERV_PTR_MASK 0x00000008
-#define BCHP_PCIE_0_DMA_RX_SW_DESC_LIST_CTRL_STS_DMA_DATA_SERV_PTR_SHIFT 3
-#define BCHP_PCIE_0_DMA_RX_SW_DESC_LIST_CTRL_STS_DMA_DATA_SERV_PTR_DEFAULT 0x00000000
-
-/* PCIE_0_DMA :: RX_SW_DESC_LIST_CTRL_STS :: DESC_SERV_PTR [02:02] */
-#define BCHP_PCIE_0_DMA_RX_SW_DESC_LIST_CTRL_STS_DESC_SERV_PTR_MASK 0x00000004
-#define BCHP_PCIE_0_DMA_RX_SW_DESC_LIST_CTRL_STS_DESC_SERV_PTR_SHIFT 2
-#define BCHP_PCIE_0_DMA_RX_SW_DESC_LIST_CTRL_STS_DESC_SERV_PTR_DEFAULT 0x00000000
-
-/* PCIE_0_DMA :: RX_SW_DESC_LIST_CTRL_STS :: reserved4 [01:01] */
-#define BCHP_PCIE_0_DMA_RX_SW_DESC_LIST_CTRL_STS_reserved4_MASK 0x00000002
-#define BCHP_PCIE_0_DMA_RX_SW_DESC_LIST_CTRL_STS_reserved4_SHIFT 1
-
-/* PCIE_0_DMA :: RX_SW_DESC_LIST_CTRL_STS :: RX_DMA_RUN_STOP [00:00] */
-#define BCHP_PCIE_0_DMA_RX_SW_DESC_LIST_CTRL_STS_RX_DMA_RUN_STOP_MASK 0x00000001
-#define BCHP_PCIE_0_DMA_RX_SW_DESC_LIST_CTRL_STS_RX_DMA_RUN_STOP_SHIFT 0
-#define BCHP_PCIE_0_DMA_RX_SW_DESC_LIST_CTRL_STS_RX_DMA_RUN_STOP_DEFAULT 0x00000000
-
-/***************************************************************************
- *RX_WAKE_CTRL - Rx DMA Wake Control
- ***************************************************************************/
-/* PCIE_0_DMA :: RX_WAKE_CTRL :: reserved0 [31:02] */
-#define BCHP_PCIE_0_DMA_RX_WAKE_CTRL_reserved0_MASK 0xfffffffc
-#define BCHP_PCIE_0_DMA_RX_WAKE_CTRL_reserved0_SHIFT 2
-
-/* PCIE_0_DMA :: RX_WAKE_CTRL :: WAKE_MODE [01:01] */
-#define BCHP_PCIE_0_DMA_RX_WAKE_CTRL_WAKE_MODE_MASK 0x00000002
-#define BCHP_PCIE_0_DMA_RX_WAKE_CTRL_WAKE_MODE_SHIFT 1
-#define BCHP_PCIE_0_DMA_RX_WAKE_CTRL_WAKE_MODE_DEFAULT 0x00000000
-
-/* PCIE_0_DMA :: RX_WAKE_CTRL :: WAKE [00:00] */
-#define BCHP_PCIE_0_DMA_RX_WAKE_CTRL_WAKE_MASK 0x00000001
-#define BCHP_PCIE_0_DMA_RX_WAKE_CTRL_WAKE_SHIFT 0
-#define BCHP_PCIE_0_DMA_RX_WAKE_CTRL_WAKE_DEFAULT 0x00000000
-
-/***************************************************************************
- *RX_ERROR_STATUS - Rx Engine Error Status
- ***************************************************************************/
-/* PCIE_0_DMA :: RX_ERROR_STATUS :: reserved0 [31:10] */
-#define BCHP_PCIE_0_DMA_RX_ERROR_STATUS_reserved0_MASK 0xfffffc00
-#define BCHP_PCIE_0_DMA_RX_ERROR_STATUS_reserved0_SHIFT 10
-
-/* PCIE_0_DMA :: RX_ERROR_STATUS :: RX_L1_DESC_TX_ABORT_ERRORS [09:09] */
-#define BCHP_PCIE_0_DMA_RX_ERROR_STATUS_RX_L1_DESC_TX_ABORT_ERRORS_MASK 0x00000200
-#define BCHP_PCIE_0_DMA_RX_ERROR_STATUS_RX_L1_DESC_TX_ABORT_ERRORS_SHIFT 9
-#define BCHP_PCIE_0_DMA_RX_ERROR_STATUS_RX_L1_DESC_TX_ABORT_ERRORS_DEFAULT 0x00000000
-
-/* PCIE_0_DMA :: RX_ERROR_STATUS :: reserved1 [08:08] */
-#define BCHP_PCIE_0_DMA_RX_ERROR_STATUS_reserved1_MASK 0x00000100
-#define BCHP_PCIE_0_DMA_RX_ERROR_STATUS_reserved1_SHIFT 8
-
-/* PCIE_0_DMA :: RX_ERROR_STATUS :: RX_L0_DESC_TX_ABORT_ERRORS [07:07] */
-#define BCHP_PCIE_0_DMA_RX_ERROR_STATUS_RX_L0_DESC_TX_ABORT_ERRORS_MASK 0x00000080
-#define BCHP_PCIE_0_DMA_RX_ERROR_STATUS_RX_L0_DESC_TX_ABORT_ERRORS_SHIFT 7
-#define BCHP_PCIE_0_DMA_RX_ERROR_STATUS_RX_L0_DESC_TX_ABORT_ERRORS_DEFAULT 0x00000000
-
-/* PCIE_0_DMA :: RX_ERROR_STATUS :: reserved2 [06:06] */
-#define BCHP_PCIE_0_DMA_RX_ERROR_STATUS_reserved2_MASK 0x00000040
-#define BCHP_PCIE_0_DMA_RX_ERROR_STATUS_reserved2_SHIFT 6
-
-/* PCIE_0_DMA :: RX_ERROR_STATUS :: RX_L1_DATA_TX_ABORT_ERRORS [05:05] */
-#define BCHP_PCIE_0_DMA_RX_ERROR_STATUS_RX_L1_DATA_TX_ABORT_ERRORS_MASK 0x00000020
-#define BCHP_PCIE_0_DMA_RX_ERROR_STATUS_RX_L1_DATA_TX_ABORT_ERRORS_SHIFT 5
-#define BCHP_PCIE_0_DMA_RX_ERROR_STATUS_RX_L1_DATA_TX_ABORT_ERRORS_DEFAULT 0x00000000
-
-/* PCIE_0_DMA :: RX_ERROR_STATUS :: reserved3 [04:03] */
-#define BCHP_PCIE_0_DMA_RX_ERROR_STATUS_reserved3_MASK 0x00000018
-#define BCHP_PCIE_0_DMA_RX_ERROR_STATUS_reserved3_SHIFT 3
-
-/* PCIE_0_DMA :: RX_ERROR_STATUS :: RX_L0_DATA_TX_ABORT_ERRORS [02:02] */
-#define BCHP_PCIE_0_DMA_RX_ERROR_STATUS_RX_L0_DATA_TX_ABORT_ERRORS_MASK 0x00000004
-#define BCHP_PCIE_0_DMA_RX_ERROR_STATUS_RX_L0_DATA_TX_ABORT_ERRORS_SHIFT 2
-#define BCHP_PCIE_0_DMA_RX_ERROR_STATUS_RX_L0_DATA_TX_ABORT_ERRORS_DEFAULT 0x00000000
-
-/* PCIE_0_DMA :: RX_ERROR_STATUS :: reserved4 [01:00] */
-#define BCHP_PCIE_0_DMA_RX_ERROR_STATUS_reserved4_MASK 0x00000003
-#define BCHP_PCIE_0_DMA_RX_ERROR_STATUS_reserved4_SHIFT 0
-
-/***************************************************************************
- *RX_LIST0_CUR_DESC_L_ADDR - Rx List0 Current Descriptor Lower Address
- ***************************************************************************/
-/* PCIE_0_DMA :: RX_LIST0_CUR_DESC_L_ADDR :: RX_L0_CUR_DESC_L_ADDR [31:05] */
-#define BCHP_PCIE_0_DMA_RX_LIST0_CUR_DESC_L_ADDR_RX_L0_CUR_DESC_L_ADDR_MASK 0xffffffe0
-#define BCHP_PCIE_0_DMA_RX_LIST0_CUR_DESC_L_ADDR_RX_L0_CUR_DESC_L_ADDR_SHIFT 5
-#define BCHP_PCIE_0_DMA_RX_LIST0_CUR_DESC_L_ADDR_RX_L0_CUR_DESC_L_ADDR_DEFAULT 0x00000000
-
-/* PCIE_0_DMA :: RX_LIST0_CUR_DESC_L_ADDR :: reserved0 [04:04] */
-#define BCHP_PCIE_0_DMA_RX_LIST0_CUR_DESC_L_ADDR_reserved0_MASK 0x00000010
-#define BCHP_PCIE_0_DMA_RX_LIST0_CUR_DESC_L_ADDR_reserved0_SHIFT 4
-
-/* PCIE_0_DMA :: RX_LIST0_CUR_DESC_L_ADDR :: RX_L0_CUR_LIST [03:03] */
-#define BCHP_PCIE_0_DMA_RX_LIST0_CUR_DESC_L_ADDR_RX_L0_CUR_LIST_MASK 0x00000008
-#define BCHP_PCIE_0_DMA_RX_LIST0_CUR_DESC_L_ADDR_RX_L0_CUR_LIST_SHIFT 3
-#define BCHP_PCIE_0_DMA_RX_LIST0_CUR_DESC_L_ADDR_RX_L0_CUR_LIST_DEFAULT 0x00000000
-
-/* PCIE_0_DMA :: RX_LIST0_CUR_DESC_L_ADDR :: RX_L0_CUR_IN_PROGRESS [02:02] */
-#define BCHP_PCIE_0_DMA_RX_LIST0_CUR_DESC_L_ADDR_RX_L0_CUR_IN_PROGRESS_MASK 0x00000004
-#define BCHP_PCIE_0_DMA_RX_LIST0_CUR_DESC_L_ADDR_RX_L0_CUR_IN_PROGRESS_SHIFT 2
-#define BCHP_PCIE_0_DMA_RX_LIST0_CUR_DESC_L_ADDR_RX_L0_CUR_IN_PROGRESS_DEFAULT 0x00000000
-
-/* PCIE_0_DMA :: RX_LIST0_CUR_DESC_L_ADDR :: RX_L0_CUR_STATUS [01:00] */
-#define BCHP_PCIE_0_DMA_RX_LIST0_CUR_DESC_L_ADDR_RX_L0_CUR_STATUS_MASK 0x00000003
-#define BCHP_PCIE_0_DMA_RX_LIST0_CUR_DESC_L_ADDR_RX_L0_CUR_STATUS_SHIFT 0
-#define BCHP_PCIE_0_DMA_RX_LIST0_CUR_DESC_L_ADDR_RX_L0_CUR_STATUS_DEFAULT 0x00000000
-
-/***************************************************************************
- *RX_LIST0_CUR_DESC_U_ADDR - Rx List0 Current Descriptor Upper Address
- ***************************************************************************/
-/* PCIE_0_DMA :: RX_LIST0_CUR_DESC_U_ADDR :: RX_L0_CUR_DESC_U_ADDR [31:00] */
-#define BCHP_PCIE_0_DMA_RX_LIST0_CUR_DESC_U_ADDR_RX_L0_CUR_DESC_U_ADDR_MASK 0xffffffff
-#define BCHP_PCIE_0_DMA_RX_LIST0_CUR_DESC_U_ADDR_RX_L0_CUR_DESC_U_ADDR_SHIFT 0
-#define BCHP_PCIE_0_DMA_RX_LIST0_CUR_DESC_U_ADDR_RX_L0_CUR_DESC_U_ADDR_DEFAULT 0x00000000
-
-/***************************************************************************
- *RX_LIST0_CUR_BYTE_CNT - Rx List0 Current Descriptor Byte Count
- ***************************************************************************/
-/* PCIE_0_DMA :: RX_LIST0_CUR_BYTE_CNT :: RX_L0_CUR_BYTE_CNT [31:00] */
-#define BCHP_PCIE_0_DMA_RX_LIST0_CUR_BYTE_CNT_RX_L0_CUR_BYTE_CNT_MASK 0xffffffff
-#define BCHP_PCIE_0_DMA_RX_LIST0_CUR_BYTE_CNT_RX_L0_CUR_BYTE_CNT_SHIFT 0
-#define BCHP_PCIE_0_DMA_RX_LIST0_CUR_BYTE_CNT_RX_L0_CUR_BYTE_CNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *RX_LIST1_CUR_DESC_L_ADDR - Rx List1 Current Descriptor Lower address
- ***************************************************************************/
-/* PCIE_0_DMA :: RX_LIST1_CUR_DESC_L_ADDR :: RX_L1_CUR_DESC_L_ADDR [31:05] */
-#define BCHP_PCIE_0_DMA_RX_LIST1_CUR_DESC_L_ADDR_RX_L1_CUR_DESC_L_ADDR_MASK 0xffffffe0
-#define BCHP_PCIE_0_DMA_RX_LIST1_CUR_DESC_L_ADDR_RX_L1_CUR_DESC_L_ADDR_SHIFT 5
-#define BCHP_PCIE_0_DMA_RX_LIST1_CUR_DESC_L_ADDR_RX_L1_CUR_DESC_L_ADDR_DEFAULT 0x00000000
-
-/* PCIE_0_DMA :: RX_LIST1_CUR_DESC_L_ADDR :: reserved0 [04:04] */
-#define BCHP_PCIE_0_DMA_RX_LIST1_CUR_DESC_L_ADDR_reserved0_MASK 0x00000010
-#define BCHP_PCIE_0_DMA_RX_LIST1_CUR_DESC_L_ADDR_reserved0_SHIFT 4
-
-/* PCIE_0_DMA :: RX_LIST1_CUR_DESC_L_ADDR :: RX_L1_CUR_LIST [03:03] */
-#define BCHP_PCIE_0_DMA_RX_LIST1_CUR_DESC_L_ADDR_RX_L1_CUR_LIST_MASK 0x00000008
-#define BCHP_PCIE_0_DMA_RX_LIST1_CUR_DESC_L_ADDR_RX_L1_CUR_LIST_SHIFT 3
-#define BCHP_PCIE_0_DMA_RX_LIST1_CUR_DESC_L_ADDR_RX_L1_CUR_LIST_DEFAULT 0x00000000
-
-/* PCIE_0_DMA :: RX_LIST1_CUR_DESC_L_ADDR :: RX_L1_CUR_IN_PROGRESS [02:02] */
-#define BCHP_PCIE_0_DMA_RX_LIST1_CUR_DESC_L_ADDR_RX_L1_CUR_IN_PROGRESS_MASK 0x00000004
-#define BCHP_PCIE_0_DMA_RX_LIST1_CUR_DESC_L_ADDR_RX_L1_CUR_IN_PROGRESS_SHIFT 2
-#define BCHP_PCIE_0_DMA_RX_LIST1_CUR_DESC_L_ADDR_RX_L1_CUR_IN_PROGRESS_DEFAULT 0x00000000
-
-/* PCIE_0_DMA :: RX_LIST1_CUR_DESC_L_ADDR :: RX_L1_CUR_STATUS [01:00] */
-#define BCHP_PCIE_0_DMA_RX_LIST1_CUR_DESC_L_ADDR_RX_L1_CUR_STATUS_MASK 0x00000003
-#define BCHP_PCIE_0_DMA_RX_LIST1_CUR_DESC_L_ADDR_RX_L1_CUR_STATUS_SHIFT 0
-#define BCHP_PCIE_0_DMA_RX_LIST1_CUR_DESC_L_ADDR_RX_L1_CUR_STATUS_DEFAULT 0x00000000
-
-/***************************************************************************
- *RX_LIST1_CUR_DESC_U_ADDR - Rx List1 Current Descriptor Upper address
- ***************************************************************************/
-/* PCIE_0_DMA :: RX_LIST1_CUR_DESC_U_ADDR :: RX_L1_CUR_DESC_U_ADDR [31:00] */
-#define BCHP_PCIE_0_DMA_RX_LIST1_CUR_DESC_U_ADDR_RX_L1_CUR_DESC_U_ADDR_MASK 0xffffffff
-#define BCHP_PCIE_0_DMA_RX_LIST1_CUR_DESC_U_ADDR_RX_L1_CUR_DESC_U_ADDR_SHIFT 0
-#define BCHP_PCIE_0_DMA_RX_LIST1_CUR_DESC_U_ADDR_RX_L1_CUR_DESC_U_ADDR_DEFAULT 0x00000000
-
-/***************************************************************************
- *RX_LIST1_CUR_BYTE_CNT - Rx List1 Current Descriptor Byte Count
- ***************************************************************************/
-/* PCIE_0_DMA :: RX_LIST1_CUR_BYTE_CNT :: RX_L1_CUR_BYTE_CNT [31:00] */
-#define BCHP_PCIE_0_DMA_RX_LIST1_CUR_BYTE_CNT_RX_L1_CUR_BYTE_CNT_MASK 0xffffffff
-#define BCHP_PCIE_0_DMA_RX_LIST1_CUR_BYTE_CNT_RX_L1_CUR_BYTE_CNT_SHIFT 0
-#define BCHP_PCIE_0_DMA_RX_LIST1_CUR_BYTE_CNT_RX_L1_CUR_BYTE_CNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *DMA_DEBUG_OPTIONS_REG - DMA Debug Options Register
- ***************************************************************************/
-/* PCIE_0_DMA :: DMA_DEBUG_OPTIONS_REG :: DMA_DEBUG_TX_DMA_SOFT_RST [31:31] */
-#define BCHP_PCIE_0_DMA_DMA_DEBUG_OPTIONS_REG_DMA_DEBUG_TX_DMA_SOFT_RST_MASK 0x80000000
-#define BCHP_PCIE_0_DMA_DMA_DEBUG_OPTIONS_REG_DMA_DEBUG_TX_DMA_SOFT_RST_SHIFT 31
-#define BCHP_PCIE_0_DMA_DMA_DEBUG_OPTIONS_REG_DMA_DEBUG_TX_DMA_SOFT_RST_DEFAULT 0x00000000
-
-/* PCIE_0_DMA :: DMA_DEBUG_OPTIONS_REG :: DMA_DEBUG_RX_DMA_SOFT_RST [30:30] */
-#define BCHP_PCIE_0_DMA_DMA_DEBUG_OPTIONS_REG_DMA_DEBUG_RX_DMA_SOFT_RST_MASK 0x40000000
-#define BCHP_PCIE_0_DMA_DMA_DEBUG_OPTIONS_REG_DMA_DEBUG_RX_DMA_SOFT_RST_SHIFT 30
-#define BCHP_PCIE_0_DMA_DMA_DEBUG_OPTIONS_REG_DMA_DEBUG_RX_DMA_SOFT_RST_DEFAULT 0x00000000
-
-/* PCIE_0_DMA :: DMA_DEBUG_OPTIONS_REG :: DMA_DEBUG_TX_DMA_RD_Q_SOFT_RST [29:29] */
-#define BCHP_PCIE_0_DMA_DMA_DEBUG_OPTIONS_REG_DMA_DEBUG_TX_DMA_RD_Q_SOFT_RST_MASK 0x20000000
-#define BCHP_PCIE_0_DMA_DMA_DEBUG_OPTIONS_REG_DMA_DEBUG_TX_DMA_RD_Q_SOFT_RST_SHIFT 29
-#define BCHP_PCIE_0_DMA_DMA_DEBUG_OPTIONS_REG_DMA_DEBUG_TX_DMA_RD_Q_SOFT_RST_DEFAULT 0x00000000
-
-/* PCIE_0_DMA :: DMA_DEBUG_OPTIONS_REG :: DMA_DEBUG_RX_DMA_WR_Q_SOFT_RST [28:28] */
-#define BCHP_PCIE_0_DMA_DMA_DEBUG_OPTIONS_REG_DMA_DEBUG_RX_DMA_WR_Q_SOFT_RST_MASK 0x10000000
-#define BCHP_PCIE_0_DMA_DMA_DEBUG_OPTIONS_REG_DMA_DEBUG_RX_DMA_WR_Q_SOFT_RST_SHIFT 28
-#define BCHP_PCIE_0_DMA_DMA_DEBUG_OPTIONS_REG_DMA_DEBUG_RX_DMA_WR_Q_SOFT_RST_DEFAULT 0x00000000
-
-/* PCIE_0_DMA :: DMA_DEBUG_OPTIONS_REG :: RSVD_DMA_DEBUG_0 [27:10] */
-#define BCHP_PCIE_0_DMA_DMA_DEBUG_OPTIONS_REG_RSVD_DMA_DEBUG_0_MASK 0x0ffffc00
-#define BCHP_PCIE_0_DMA_DMA_DEBUG_OPTIONS_REG_RSVD_DMA_DEBUG_0_SHIFT 10
-#define BCHP_PCIE_0_DMA_DMA_DEBUG_OPTIONS_REG_RSVD_DMA_DEBUG_0_DEFAULT 0x00000000
-
-/* PCIE_0_DMA :: DMA_DEBUG_OPTIONS_REG :: DMA_DEBUG_SPQ_SNAP_PW_DIS [09:09] */
-#define BCHP_PCIE_0_DMA_DMA_DEBUG_OPTIONS_REG_DMA_DEBUG_SPQ_SNAP_PW_DIS_MASK 0x00000200
-#define BCHP_PCIE_0_DMA_DMA_DEBUG_OPTIONS_REG_DMA_DEBUG_SPQ_SNAP_PW_DIS_SHIFT 9
-#define BCHP_PCIE_0_DMA_DMA_DEBUG_OPTIONS_REG_DMA_DEBUG_SPQ_SNAP_PW_DIS_DEFAULT 0x00000000
-
-/* PCIE_0_DMA :: DMA_DEBUG_OPTIONS_REG :: DMA_DEBUG_OUTCP_Q_RO [08:08] */
-#define BCHP_PCIE_0_DMA_DMA_DEBUG_OPTIONS_REG_DMA_DEBUG_OUTCP_Q_RO_MASK 0x00000100
-#define BCHP_PCIE_0_DMA_DMA_DEBUG_OPTIONS_REG_DMA_DEBUG_OUTCP_Q_RO_SHIFT 8
-#define BCHP_PCIE_0_DMA_DMA_DEBUG_OPTIONS_REG_DMA_DEBUG_OUTCP_Q_RO_DEFAULT 0x00000000
-
-/* PCIE_0_DMA :: DMA_DEBUG_OPTIONS_REG :: DMA_DEBUG_NO_TX_DESC [07:07] */
-#define BCHP_PCIE_0_DMA_DMA_DEBUG_OPTIONS_REG_DMA_DEBUG_NO_TX_DESC_MASK 0x00000080
-#define BCHP_PCIE_0_DMA_DMA_DEBUG_OPTIONS_REG_DMA_DEBUG_NO_TX_DESC_SHIFT 7
-#define BCHP_PCIE_0_DMA_DMA_DEBUG_OPTIONS_REG_DMA_DEBUG_NO_TX_DESC_DEFAULT 0x00000000
-
-/* PCIE_0_DMA :: DMA_DEBUG_OPTIONS_REG :: DMA_DEBUG_NO_RX_DESC [06:06] */
-#define BCHP_PCIE_0_DMA_DMA_DEBUG_OPTIONS_REG_DMA_DEBUG_NO_RX_DESC_MASK 0x00000040
-#define BCHP_PCIE_0_DMA_DMA_DEBUG_OPTIONS_REG_DMA_DEBUG_NO_RX_DESC_SHIFT 6
-#define BCHP_PCIE_0_DMA_DMA_DEBUG_OPTIONS_REG_DMA_DEBUG_NO_RX_DESC_DEFAULT 0x00000000
-
-/* PCIE_0_DMA :: DMA_DEBUG_OPTIONS_REG :: DMA_DEBUG_SEL_RX_CNT [05:05] */
-#define BCHP_PCIE_0_DMA_DMA_DEBUG_OPTIONS_REG_DMA_DEBUG_SEL_RX_CNT_MASK 0x00000020
-#define BCHP_PCIE_0_DMA_DMA_DEBUG_OPTIONS_REG_DMA_DEBUG_SEL_RX_CNT_SHIFT 5
-#define BCHP_PCIE_0_DMA_DMA_DEBUG_OPTIONS_REG_DMA_DEBUG_SEL_RX_CNT_DEFAULT 0x00000000
-
-/* PCIE_0_DMA :: DMA_DEBUG_OPTIONS_REG :: DMA_DEBUG_EN_RX_DMA_XFER_CNT [04:04] */
-#define BCHP_PCIE_0_DMA_DMA_DEBUG_OPTIONS_REG_DMA_DEBUG_EN_RX_DMA_XFER_CNT_MASK 0x00000010
-#define BCHP_PCIE_0_DMA_DMA_DEBUG_OPTIONS_REG_DMA_DEBUG_EN_RX_DMA_XFER_CNT_SHIFT 4
-#define BCHP_PCIE_0_DMA_DMA_DEBUG_OPTIONS_REG_DMA_DEBUG_EN_RX_DMA_XFER_CNT_DEFAULT 0x00000000
-
-/* PCIE_0_DMA :: DMA_DEBUG_OPTIONS_REG :: DMA_DEBUG_SEL_TX_CNT [03:03] */
-#define BCHP_PCIE_0_DMA_DMA_DEBUG_OPTIONS_REG_DMA_DEBUG_SEL_TX_CNT_MASK 0x00000008
-#define BCHP_PCIE_0_DMA_DMA_DEBUG_OPTIONS_REG_DMA_DEBUG_SEL_TX_CNT_SHIFT 3
-#define BCHP_PCIE_0_DMA_DMA_DEBUG_OPTIONS_REG_DMA_DEBUG_SEL_TX_CNT_DEFAULT 0x00000000
-
-/* PCIE_0_DMA :: DMA_DEBUG_OPTIONS_REG :: DMA_DEBUG_SINGLE_RD_Q [02:02] */
-#define BCHP_PCIE_0_DMA_DMA_DEBUG_OPTIONS_REG_DMA_DEBUG_SINGLE_RD_Q_MASK 0x00000004
-#define BCHP_PCIE_0_DMA_DMA_DEBUG_OPTIONS_REG_DMA_DEBUG_SINGLE_RD_Q_SHIFT 2
-#define BCHP_PCIE_0_DMA_DMA_DEBUG_OPTIONS_REG_DMA_DEBUG_SINGLE_RD_Q_DEFAULT 0x00000000
-
-/* PCIE_0_DMA :: DMA_DEBUG_OPTIONS_REG :: DMA_DEBUG_SINGLE_WR_Q [01:01] */
-#define BCHP_PCIE_0_DMA_DMA_DEBUG_OPTIONS_REG_DMA_DEBUG_SINGLE_WR_Q_MASK 0x00000002
-#define BCHP_PCIE_0_DMA_DMA_DEBUG_OPTIONS_REG_DMA_DEBUG_SINGLE_WR_Q_SHIFT 1
-#define BCHP_PCIE_0_DMA_DMA_DEBUG_OPTIONS_REG_DMA_DEBUG_SINGLE_WR_Q_DEFAULT 0x00000000
-
-/* PCIE_0_DMA :: DMA_DEBUG_OPTIONS_REG :: DMA_DEBUG_RD_Q_RO [00:00] */
-#define BCHP_PCIE_0_DMA_DMA_DEBUG_OPTIONS_REG_DMA_DEBUG_RD_Q_RO_MASK 0x00000001
-#define BCHP_PCIE_0_DMA_DMA_DEBUG_OPTIONS_REG_DMA_DEBUG_RD_Q_RO_SHIFT 0
-#define BCHP_PCIE_0_DMA_DMA_DEBUG_OPTIONS_REG_DMA_DEBUG_RD_Q_RO_DEFAULT 0x00000000
-
-/***************************************************************************
- *READ_CHANNEL_ERROR_STATUS - Read Channel Error Status
- ***************************************************************************/
-/* PCIE_0_DMA :: READ_CHANNEL_ERROR_STATUS :: TX_ERR_STS_CHAN_7 [31:28] */
-#define BCHP_PCIE_0_DMA_READ_CHANNEL_ERROR_STATUS_TX_ERR_STS_CHAN_7_MASK 0xf0000000
-#define BCHP_PCIE_0_DMA_READ_CHANNEL_ERROR_STATUS_TX_ERR_STS_CHAN_7_SHIFT 28
-#define BCHP_PCIE_0_DMA_READ_CHANNEL_ERROR_STATUS_TX_ERR_STS_CHAN_7_DEFAULT 0x00000000
-
-/* PCIE_0_DMA :: READ_CHANNEL_ERROR_STATUS :: TX_ERR_STS_CHAN_6 [27:24] */
-#define BCHP_PCIE_0_DMA_READ_CHANNEL_ERROR_STATUS_TX_ERR_STS_CHAN_6_MASK 0x0f000000
-#define BCHP_PCIE_0_DMA_READ_CHANNEL_ERROR_STATUS_TX_ERR_STS_CHAN_6_SHIFT 24
-#define BCHP_PCIE_0_DMA_READ_CHANNEL_ERROR_STATUS_TX_ERR_STS_CHAN_6_DEFAULT 0x00000000
-
-/* PCIE_0_DMA :: READ_CHANNEL_ERROR_STATUS :: TX_ERR_STS_CHAN_5 [23:20] */
-#define BCHP_PCIE_0_DMA_READ_CHANNEL_ERROR_STATUS_TX_ERR_STS_CHAN_5_MASK 0x00f00000
-#define BCHP_PCIE_0_DMA_READ_CHANNEL_ERROR_STATUS_TX_ERR_STS_CHAN_5_SHIFT 20
-#define BCHP_PCIE_0_DMA_READ_CHANNEL_ERROR_STATUS_TX_ERR_STS_CHAN_5_DEFAULT 0x00000000
-
-/* PCIE_0_DMA :: READ_CHANNEL_ERROR_STATUS :: TX_ERR_STS_CHAN_4 [19:16] */
-#define BCHP_PCIE_0_DMA_READ_CHANNEL_ERROR_STATUS_TX_ERR_STS_CHAN_4_MASK 0x000f0000
-#define BCHP_PCIE_0_DMA_READ_CHANNEL_ERROR_STATUS_TX_ERR_STS_CHAN_4_SHIFT 16
-#define BCHP_PCIE_0_DMA_READ_CHANNEL_ERROR_STATUS_TX_ERR_STS_CHAN_4_DEFAULT 0x00000000
-
-/* PCIE_0_DMA :: READ_CHANNEL_ERROR_STATUS :: TX_ERR_STS_CHAN_3 [15:12] */
-#define BCHP_PCIE_0_DMA_READ_CHANNEL_ERROR_STATUS_TX_ERR_STS_CHAN_3_MASK 0x0000f000
-#define BCHP_PCIE_0_DMA_READ_CHANNEL_ERROR_STATUS_TX_ERR_STS_CHAN_3_SHIFT 12
-#define BCHP_PCIE_0_DMA_READ_CHANNEL_ERROR_STATUS_TX_ERR_STS_CHAN_3_DEFAULT 0x00000000
-
-/* PCIE_0_DMA :: READ_CHANNEL_ERROR_STATUS :: TX_ERR_STS_CHAN_2 [11:08] */
-#define BCHP_PCIE_0_DMA_READ_CHANNEL_ERROR_STATUS_TX_ERR_STS_CHAN_2_MASK 0x00000f00
-#define BCHP_PCIE_0_DMA_READ_CHANNEL_ERROR_STATUS_TX_ERR_STS_CHAN_2_SHIFT 8
-#define BCHP_PCIE_0_DMA_READ_CHANNEL_ERROR_STATUS_TX_ERR_STS_CHAN_2_DEFAULT 0x00000000
-
-/* PCIE_0_DMA :: READ_CHANNEL_ERROR_STATUS :: TX_ERR_STS_CHAN_1 [07:04] */
-#define BCHP_PCIE_0_DMA_READ_CHANNEL_ERROR_STATUS_TX_ERR_STS_CHAN_1_MASK 0x000000f0
-#define BCHP_PCIE_0_DMA_READ_CHANNEL_ERROR_STATUS_TX_ERR_STS_CHAN_1_SHIFT 4
-#define BCHP_PCIE_0_DMA_READ_CHANNEL_ERROR_STATUS_TX_ERR_STS_CHAN_1_DEFAULT 0x00000000
-
-/* PCIE_0_DMA :: READ_CHANNEL_ERROR_STATUS :: TX_ERR_STS_CHAN_0 [03:00] */
-#define BCHP_PCIE_0_DMA_READ_CHANNEL_ERROR_STATUS_TX_ERR_STS_CHAN_0_MASK 0x0000000f
-#define BCHP_PCIE_0_DMA_READ_CHANNEL_ERROR_STATUS_TX_ERR_STS_CHAN_0_SHIFT 0
-#define BCHP_PCIE_0_DMA_READ_CHANNEL_ERROR_STATUS_TX_ERR_STS_CHAN_0_DEFAULT 0x00000000
-
-#endif /* #ifndef BCHP_PCIE_0_DMA_H__ */
-
-/* End of File */
diff --git a/include/linux/brcmstb/7366b0/bchp_pcie_0_ext_cfg.h b/include/linux/brcmstb/7366b0/bchp_pcie_0_ext_cfg.h
deleted file mode 100644
index 7b8ec73..0000000
--- a/include/linux/brcmstb/7366b0/bchp_pcie_0_ext_cfg.h
+++ /dev/null
@@ -1,116 +0,0 @@
-/***************************************************************************
- * Copyright (c) 1999-2013, Broadcom Corporation
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
- *
- * Module Description:
- * DO NOT EDIT THIS FILE DIRECTLY
- *
- * This module was generated magically with RDB from a source description
- * file. You must edit the source file for changes to be made to this file.
- *
- *
- * Date: Generated on Sat Apr 20 03:07:47 2013
- * MD5 Checksum d41d8cd98f00b204e9800998ecf8427e
- *
- * Compiled with: RDB Utility combo_header.pl
- * RDB Parser 3.0
- * unknown unknown
- * Perl Interpreter 5.008008
- * Operating System linux
- *
- * Revision History:
- *
- * $brcm_Log: $
- *
- ***************************************************************************/
-
-#ifndef BCHP_PCIE_0_EXT_CFG_H__
-#define BCHP_PCIE_0_EXT_CFG_H__
-
-/***************************************************************************
- *PCIE_0_EXT_CFG - PCIE EXTERNAL CFG Registers
- ***************************************************************************/
-#define BCHP_PCIE_0_EXT_CFG_PCIE_EXT_CFG_DATA_0 0x00478000 /* PCIe External Configuration Space Data[0] */
-#define BCHP_PCIE_0_EXT_CFG_PCIE_EXT_CFG_DATA_1023 0x00478ffc /* PCIe External Configuration Space Data[1023] */
-#define BCHP_PCIE_0_EXT_CFG_PCIE_EXT_CFG_INDEX 0x00479000 /* PCIE External Configuration Access Index */
-#define BCHP_PCIE_0_EXT_CFG_PCIE_EXT_CFG_DATA 0x00479004 /* PCIE External Configuration Access Data */
-#define BCHP_PCIE_0_EXT_CFG_SCRATCH 0x00479008 /* Scratch Register */
-
-/***************************************************************************
- *PCIE_EXT_CFG_DATA_0 - PCIe External Configuration Space Data[0]
- ***************************************************************************/
-/* PCIE_0_EXT_CFG :: PCIE_EXT_CFG_DATA_0 :: DATA [31:00] */
-#define BCHP_PCIE_0_EXT_CFG_PCIE_EXT_CFG_DATA_0_DATA_MASK 0xffffffff
-#define BCHP_PCIE_0_EXT_CFG_PCIE_EXT_CFG_DATA_0_DATA_SHIFT 0
-
-/***************************************************************************
- *PCIE_EXT_CFG_DATA_1023 - PCIe External Configuration Space Data[1023]
- ***************************************************************************/
-/* PCIE_0_EXT_CFG :: PCIE_EXT_CFG_DATA_1023 :: DATA [31:00] */
-#define BCHP_PCIE_0_EXT_CFG_PCIE_EXT_CFG_DATA_1023_DATA_MASK 0xffffffff
-#define BCHP_PCIE_0_EXT_CFG_PCIE_EXT_CFG_DATA_1023_DATA_SHIFT 0
-
-/***************************************************************************
- *PCIE_EXT_CFG_INDEX - PCIE External Configuration Access Index
- ***************************************************************************/
-/* PCIE_0_EXT_CFG :: PCIE_EXT_CFG_INDEX :: UNUSED_1 [31:28] */
-#define BCHP_PCIE_0_EXT_CFG_PCIE_EXT_CFG_INDEX_UNUSED_1_MASK 0xf0000000
-#define BCHP_PCIE_0_EXT_CFG_PCIE_EXT_CFG_INDEX_UNUSED_1_SHIFT 28
-#define BCHP_PCIE_0_EXT_CFG_PCIE_EXT_CFG_INDEX_UNUSED_1_DEFAULT 0x00000000
-
-/* PCIE_0_EXT_CFG :: PCIE_EXT_CFG_INDEX :: BUS_NUM [27:20] */
-#define BCHP_PCIE_0_EXT_CFG_PCIE_EXT_CFG_INDEX_BUS_NUM_MASK 0x0ff00000
-#define BCHP_PCIE_0_EXT_CFG_PCIE_EXT_CFG_INDEX_BUS_NUM_SHIFT 20
-#define BCHP_PCIE_0_EXT_CFG_PCIE_EXT_CFG_INDEX_BUS_NUM_DEFAULT 0x00000000
-
-/* PCIE_0_EXT_CFG :: PCIE_EXT_CFG_INDEX :: DEV_NUM [19:15] */
-#define BCHP_PCIE_0_EXT_CFG_PCIE_EXT_CFG_INDEX_DEV_NUM_MASK 0x000f8000
-#define BCHP_PCIE_0_EXT_CFG_PCIE_EXT_CFG_INDEX_DEV_NUM_SHIFT 15
-#define BCHP_PCIE_0_EXT_CFG_PCIE_EXT_CFG_INDEX_DEV_NUM_DEFAULT 0x00000000
-
-/* PCIE_0_EXT_CFG :: PCIE_EXT_CFG_INDEX :: FUNC_NUM [14:12] */
-#define BCHP_PCIE_0_EXT_CFG_PCIE_EXT_CFG_INDEX_FUNC_NUM_MASK 0x00007000
-#define BCHP_PCIE_0_EXT_CFG_PCIE_EXT_CFG_INDEX_FUNC_NUM_SHIFT 12
-#define BCHP_PCIE_0_EXT_CFG_PCIE_EXT_CFG_INDEX_FUNC_NUM_DEFAULT 0x00000000
-
-/* PCIE_0_EXT_CFG :: PCIE_EXT_CFG_INDEX :: REG_NUM [11:02] */
-#define BCHP_PCIE_0_EXT_CFG_PCIE_EXT_CFG_INDEX_REG_NUM_MASK 0x00000ffc
-#define BCHP_PCIE_0_EXT_CFG_PCIE_EXT_CFG_INDEX_REG_NUM_SHIFT 2
-#define BCHP_PCIE_0_EXT_CFG_PCIE_EXT_CFG_INDEX_REG_NUM_DEFAULT 0x00000000
-
-/* PCIE_0_EXT_CFG :: PCIE_EXT_CFG_INDEX :: UNUSED_0 [01:00] */
-#define BCHP_PCIE_0_EXT_CFG_PCIE_EXT_CFG_INDEX_UNUSED_0_MASK 0x00000003
-#define BCHP_PCIE_0_EXT_CFG_PCIE_EXT_CFG_INDEX_UNUSED_0_SHIFT 0
-#define BCHP_PCIE_0_EXT_CFG_PCIE_EXT_CFG_INDEX_UNUSED_0_DEFAULT 0x00000000
-
-/***************************************************************************
- *PCIE_EXT_CFG_DATA - PCIE External Configuration Access Data
- ***************************************************************************/
-/* PCIE_0_EXT_CFG :: PCIE_EXT_CFG_DATA :: DATA [31:00] */
-#define BCHP_PCIE_0_EXT_CFG_PCIE_EXT_CFG_DATA_DATA_MASK 0xffffffff
-#define BCHP_PCIE_0_EXT_CFG_PCIE_EXT_CFG_DATA_DATA_SHIFT 0
-#define BCHP_PCIE_0_EXT_CFG_PCIE_EXT_CFG_DATA_DATA_DEFAULT 0x00000000
-
-/***************************************************************************
- *SCRATCH - Scratch Register
- ***************************************************************************/
-/* PCIE_0_EXT_CFG :: SCRATCH :: DATA [31:00] */
-#define BCHP_PCIE_0_EXT_CFG_SCRATCH_DATA_MASK 0xffffffff
-#define BCHP_PCIE_0_EXT_CFG_SCRATCH_DATA_SHIFT 0
-#define BCHP_PCIE_0_EXT_CFG_SCRATCH_DATA_DEFAULT 0x00000000
-
-#endif /* #ifndef BCHP_PCIE_0_EXT_CFG_H__ */
-
-/* End of File */
diff --git a/include/linux/brcmstb/7366b0/bchp_pcie_0_intr2.h b/include/linux/brcmstb/7366b0/bchp_pcie_0_intr2.h
deleted file mode 100644
index f2ebcf8..0000000
--- a/include/linux/brcmstb/7366b0/bchp_pcie_0_intr2.h
+++ /dev/null
@@ -1,2016 +0,0 @@
-/***************************************************************************
- * Copyright (c) 1999-2013, Broadcom Corporation
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
- *
- * Module Description:
- * DO NOT EDIT THIS FILE DIRECTLY
- *
- * This module was generated magically with RDB from a source description
- * file. You must edit the source file for changes to be made to this file.
- *
- *
- * Date: Generated on Sat Apr 20 03:07:43 2013
- * MD5 Checksum d41d8cd98f00b204e9800998ecf8427e
- *
- * Compiled with: RDB Utility combo_header.pl
- * RDB Parser 3.0
- * unknown unknown
- * Perl Interpreter 5.008008
- * Operating System linux
- *
- * Revision History:
- *
- * $brcm_Log: $
- *
- ***************************************************************************/
-
-#ifndef BCHP_PCIE_0_INTR2_H__
-#define BCHP_PCIE_0_INTR2_H__
-
-/***************************************************************************
- *PCIE_0_INTR2 - PCI-E L2 Interrupt Controller Registers
- ***************************************************************************/
-#define BCHP_PCIE_0_INTR2_CPU_STATUS 0x00474300 /* CPU interrupt Status Register */
-#define BCHP_PCIE_0_INTR2_CPU_SET 0x00474304 /* CPU interrupt Set Register */
-#define BCHP_PCIE_0_INTR2_CPU_CLEAR 0x00474308 /* CPU interrupt Clear Register */
-#define BCHP_PCIE_0_INTR2_CPU_MASK_STATUS 0x0047430c /* CPU interrupt Mask Status Register */
-#define BCHP_PCIE_0_INTR2_CPU_MASK_SET 0x00474310 /* CPU interrupt Mask Set Register */
-#define BCHP_PCIE_0_INTR2_CPU_MASK_CLEAR 0x00474314 /* CPU interrupt Mask Clear Register */
-#define BCHP_PCIE_0_INTR2_PCI_STATUS 0x00474318 /* PCI interrupt Status Register */
-#define BCHP_PCIE_0_INTR2_PCI_SET 0x0047431c /* PCI interrupt Set Register */
-#define BCHP_PCIE_0_INTR2_PCI_CLEAR 0x00474320 /* PCI interrupt Clear Register */
-#define BCHP_PCIE_0_INTR2_PCI_MASK_STATUS 0x00474324 /* PCI interrupt Mask Status Register */
-#define BCHP_PCIE_0_INTR2_PCI_MASK_SET 0x00474328 /* PCI interrupt Mask Set Register */
-#define BCHP_PCIE_0_INTR2_PCI_MASK_CLEAR 0x0047432c /* PCI interrupt Mask Clear Register */
-
-/***************************************************************************
- *CPU_STATUS - CPU interrupt Status Register
- ***************************************************************************/
-/* PCIE_0_INTR2 :: CPU_STATUS :: MSI_INTR07 [31:31] */
-#define BCHP_PCIE_0_INTR2_CPU_STATUS_MSI_INTR07_MASK 0x80000000
-#define BCHP_PCIE_0_INTR2_CPU_STATUS_MSI_INTR07_SHIFT 31
-#define BCHP_PCIE_0_INTR2_CPU_STATUS_MSI_INTR07_DEFAULT 0x00000000
-
-/* PCIE_0_INTR2 :: CPU_STATUS :: MSI_INTR06 [30:30] */
-#define BCHP_PCIE_0_INTR2_CPU_STATUS_MSI_INTR06_MASK 0x40000000
-#define BCHP_PCIE_0_INTR2_CPU_STATUS_MSI_INTR06_SHIFT 30
-#define BCHP_PCIE_0_INTR2_CPU_STATUS_MSI_INTR06_DEFAULT 0x00000000
-
-/* PCIE_0_INTR2 :: CPU_STATUS :: MSI_INTR05 [29:29] */
-#define BCHP_PCIE_0_INTR2_CPU_STATUS_MSI_INTR05_MASK 0x20000000
-#define BCHP_PCIE_0_INTR2_CPU_STATUS_MSI_INTR05_SHIFT 29
-#define BCHP_PCIE_0_INTR2_CPU_STATUS_MSI_INTR05_DEFAULT 0x00000000
-
-/* PCIE_0_INTR2 :: CPU_STATUS :: MSI_INTR04 [28:28] */
-#define BCHP_PCIE_0_INTR2_CPU_STATUS_MSI_INTR04_MASK 0x10000000
-#define BCHP_PCIE_0_INTR2_CPU_STATUS_MSI_INTR04_SHIFT 28
-#define BCHP_PCIE_0_INTR2_CPU_STATUS_MSI_INTR04_DEFAULT 0x00000000
-
-/* PCIE_0_INTR2 :: CPU_STATUS :: MSI_INTR03 [27:27] */
-#define BCHP_PCIE_0_INTR2_CPU_STATUS_MSI_INTR03_MASK 0x08000000
-#define BCHP_PCIE_0_INTR2_CPU_STATUS_MSI_INTR03_SHIFT 27
-#define BCHP_PCIE_0_INTR2_CPU_STATUS_MSI_INTR03_DEFAULT 0x00000000
-
-/* PCIE_0_INTR2 :: CPU_STATUS :: MSI_INTR02 [26:26] */
-#define BCHP_PCIE_0_INTR2_CPU_STATUS_MSI_INTR02_MASK 0x04000000
-#define BCHP_PCIE_0_INTR2_CPU_STATUS_MSI_INTR02_SHIFT 26
-#define BCHP_PCIE_0_INTR2_CPU_STATUS_MSI_INTR02_DEFAULT 0x00000000
-
-/* PCIE_0_INTR2 :: CPU_STATUS :: MSI_INTR01 [25:25] */
-#define BCHP_PCIE_0_INTR2_CPU_STATUS_MSI_INTR01_MASK 0x02000000
-#define BCHP_PCIE_0_INTR2_CPU_STATUS_MSI_INTR01_SHIFT 25
-#define BCHP_PCIE_0_INTR2_CPU_STATUS_MSI_INTR01_DEFAULT 0x00000000
-
-/* PCIE_0_INTR2 :: CPU_STATUS :: MSI_INTR00 [24:24] */
-#define BCHP_PCIE_0_INTR2_CPU_STATUS_MSI_INTR00_MASK 0x01000000
-#define BCHP_PCIE_0_INTR2_CPU_STATUS_MSI_INTR00_SHIFT 24
-#define BCHP_PCIE_0_INTR2_CPU_STATUS_MSI_INTR00_DEFAULT 0x00000000
-
-/* PCIE_0_INTR2 :: CPU_STATUS :: UNASSIGNED_23 [23:23] */
-#define BCHP_PCIE_0_INTR2_CPU_STATUS_UNASSIGNED_23_MASK 0x00800000
-#define BCHP_PCIE_0_INTR2_CPU_STATUS_UNASSIGNED_23_SHIFT 23
-#define BCHP_PCIE_0_INTR2_CPU_STATUS_UNASSIGNED_23_DEFAULT 0x00000000
-
-/* PCIE_0_INTR2 :: CPU_STATUS :: UNASSIGNED_22 [22:22] */
-#define BCHP_PCIE_0_INTR2_CPU_STATUS_UNASSIGNED_22_MASK 0x00400000
-#define BCHP_PCIE_0_INTR2_CPU_STATUS_UNASSIGNED_22_SHIFT 22
-#define BCHP_PCIE_0_INTR2_CPU_STATUS_UNASSIGNED_22_DEFAULT 0x00000000
-
-/* PCIE_0_INTR2 :: CPU_STATUS :: UNASSIGNED_21 [21:21] */
-#define BCHP_PCIE_0_INTR2_CPU_STATUS_UNASSIGNED_21_MASK 0x00200000
-#define BCHP_PCIE_0_INTR2_CPU_STATUS_UNASSIGNED_21_SHIFT 21
-#define BCHP_PCIE_0_INTR2_CPU_STATUS_UNASSIGNED_21_DEFAULT 0x00000000
-
-/* PCIE_0_INTR2 :: CPU_STATUS :: UNASSIGNED_20 [20:20] */
-#define BCHP_PCIE_0_INTR2_CPU_STATUS_UNASSIGNED_20_MASK 0x00100000
-#define BCHP_PCIE_0_INTR2_CPU_STATUS_UNASSIGNED_20_SHIFT 20
-#define BCHP_PCIE_0_INTR2_CPU_STATUS_UNASSIGNED_20_DEFAULT 0x00000000
-
-/* PCIE_0_INTR2 :: CPU_STATUS :: MAILBOX_3 [19:19] */
-#define BCHP_PCIE_0_INTR2_CPU_STATUS_MAILBOX_3_MASK 0x00080000
-#define BCHP_PCIE_0_INTR2_CPU_STATUS_MAILBOX_3_SHIFT 19
-#define BCHP_PCIE_0_INTR2_CPU_STATUS_MAILBOX_3_DEFAULT 0x00000000
-
-/* PCIE_0_INTR2 :: CPU_STATUS :: MAILBOX_2 [18:18] */
-#define BCHP_PCIE_0_INTR2_CPU_STATUS_MAILBOX_2_MASK 0x00040000
-#define BCHP_PCIE_0_INTR2_CPU_STATUS_MAILBOX_2_SHIFT 18
-#define BCHP_PCIE_0_INTR2_CPU_STATUS_MAILBOX_2_DEFAULT 0x00000000
-
-/* PCIE_0_INTR2 :: CPU_STATUS :: MAILBOX_1 [17:17] */
-#define BCHP_PCIE_0_INTR2_CPU_STATUS_MAILBOX_1_MASK 0x00020000
-#define BCHP_PCIE_0_INTR2_CPU_STATUS_MAILBOX_1_SHIFT 17
-#define BCHP_PCIE_0_INTR2_CPU_STATUS_MAILBOX_1_DEFAULT 0x00000000
-
-/* PCIE_0_INTR2 :: CPU_STATUS :: MAILBOX_0 [16:16] */
-#define BCHP_PCIE_0_INTR2_CPU_STATUS_MAILBOX_0_MASK 0x00010000
-#define BCHP_PCIE_0_INTR2_CPU_STATUS_MAILBOX_0_SHIFT 16
-#define BCHP_PCIE_0_INTR2_CPU_STATUS_MAILBOX_0_DEFAULT 0x00000000
-
-/* PCIE_0_INTR2 :: CPU_STATUS :: PCIE_MSTR_FWD_ERR [15:15] */
-#define BCHP_PCIE_0_INTR2_CPU_STATUS_PCIE_MSTR_FWD_ERR_MASK 0x00008000
-#define BCHP_PCIE_0_INTR2_CPU_STATUS_PCIE_MSTR_FWD_ERR_SHIFT 15
-#define BCHP_PCIE_0_INTR2_CPU_STATUS_PCIE_MSTR_FWD_ERR_DEFAULT 0x00000000
-
-/* PCIE_0_INTR2 :: CPU_STATUS :: PCIE_MSTR_RETRY_TIMEOUT [14:14] */
-#define BCHP_PCIE_0_INTR2_CPU_STATUS_PCIE_MSTR_RETRY_TIMEOUT_MASK 0x00004000
-#define BCHP_PCIE_0_INTR2_CPU_STATUS_PCIE_MSTR_RETRY_TIMEOUT_SHIFT 14
-#define BCHP_PCIE_0_INTR2_CPU_STATUS_PCIE_MSTR_RETRY_TIMEOUT_DEFAULT 0x00000000
-
-/* PCIE_0_INTR2 :: CPU_STATUS :: PCIE_MSTR_CA_ATTN [13:13] */
-#define BCHP_PCIE_0_INTR2_CPU_STATUS_PCIE_MSTR_CA_ATTN_MASK 0x00002000
-#define BCHP_PCIE_0_INTR2_CPU_STATUS_PCIE_MSTR_CA_ATTN_SHIFT 13
-#define BCHP_PCIE_0_INTR2_CPU_STATUS_PCIE_MSTR_CA_ATTN_DEFAULT 0x00000000
-
-/* PCIE_0_INTR2 :: CPU_STATUS :: PCIE_MSTR_UR_ATTN [12:12] */
-#define BCHP_PCIE_0_INTR2_CPU_STATUS_PCIE_MSTR_UR_ATTN_MASK 0x00001000
-#define BCHP_PCIE_0_INTR2_CPU_STATUS_PCIE_MSTR_UR_ATTN_SHIFT 12
-#define BCHP_PCIE_0_INTR2_CPU_STATUS_PCIE_MSTR_UR_ATTN_DEFAULT 0x00000000
-
-/* PCIE_0_INTR2 :: CPU_STATUS :: UNASSIGNED_11 [11:11] */
-#define BCHP_PCIE_0_INTR2_CPU_STATUS_UNASSIGNED_11_MASK 0x00000800
-#define BCHP_PCIE_0_INTR2_CPU_STATUS_UNASSIGNED_11_SHIFT 11
-#define BCHP_PCIE_0_INTR2_CPU_STATUS_UNASSIGNED_11_DEFAULT 0x00000000
-
-/* PCIE_0_INTR2 :: CPU_STATUS :: UNASSIGNED_10 [10:10] */
-#define BCHP_PCIE_0_INTR2_CPU_STATUS_UNASSIGNED_10_MASK 0x00000400
-#define BCHP_PCIE_0_INTR2_CPU_STATUS_UNASSIGNED_10_SHIFT 10
-#define BCHP_PCIE_0_INTR2_CPU_STATUS_UNASSIGNED_10_DEFAULT 0x00000000
-
-/* PCIE_0_INTR2 :: CPU_STATUS :: PCIE_TGT_BAD_ACCESS [09:09] */
-#define BCHP_PCIE_0_INTR2_CPU_STATUS_PCIE_TGT_BAD_ACCESS_MASK 0x00000200
-#define BCHP_PCIE_0_INTR2_CPU_STATUS_PCIE_TGT_BAD_ACCESS_SHIFT 9
-#define BCHP_PCIE_0_INTR2_CPU_STATUS_PCIE_TGT_BAD_ACCESS_DEFAULT 0x00000000
-
-/* PCIE_0_INTR2 :: CPU_STATUS :: PCIE_TGT_BAD_ADDRESS [08:08] */
-#define BCHP_PCIE_0_INTR2_CPU_STATUS_PCIE_TGT_BAD_ADDRESS_MASK 0x00000100
-#define BCHP_PCIE_0_INTR2_CPU_STATUS_PCIE_TGT_BAD_ADDRESS_SHIFT 8
-#define BCHP_PCIE_0_INTR2_CPU_STATUS_PCIE_TGT_BAD_ADDRESS_DEFAULT 0x00000000
-
-/* PCIE_0_INTR2 :: CPU_STATUS :: L1_RX_DMA_ERR_INTR [07:07] */
-#define BCHP_PCIE_0_INTR2_CPU_STATUS_L1_RX_DMA_ERR_INTR_MASK 0x00000080
-#define BCHP_PCIE_0_INTR2_CPU_STATUS_L1_RX_DMA_ERR_INTR_SHIFT 7
-#define BCHP_PCIE_0_INTR2_CPU_STATUS_L1_RX_DMA_ERR_INTR_DEFAULT 0x00000000
-
-/* PCIE_0_INTR2 :: CPU_STATUS :: L1_RX_DMA_DONE_INTR [06:06] */
-#define BCHP_PCIE_0_INTR2_CPU_STATUS_L1_RX_DMA_DONE_INTR_MASK 0x00000040
-#define BCHP_PCIE_0_INTR2_CPU_STATUS_L1_RX_DMA_DONE_INTR_SHIFT 6
-#define BCHP_PCIE_0_INTR2_CPU_STATUS_L1_RX_DMA_DONE_INTR_DEFAULT 0x00000000
-
-/* PCIE_0_INTR2 :: CPU_STATUS :: L1_TX_DMA_ERR_INTR [05:05] */
-#define BCHP_PCIE_0_INTR2_CPU_STATUS_L1_TX_DMA_ERR_INTR_MASK 0x00000020
-#define BCHP_PCIE_0_INTR2_CPU_STATUS_L1_TX_DMA_ERR_INTR_SHIFT 5
-#define BCHP_PCIE_0_INTR2_CPU_STATUS_L1_TX_DMA_ERR_INTR_DEFAULT 0x00000000
-
-/* PCIE_0_INTR2 :: CPU_STATUS :: L1_TX_DMA_DONE_INTR [04:04] */
-#define BCHP_PCIE_0_INTR2_CPU_STATUS_L1_TX_DMA_DONE_INTR_MASK 0x00000010
-#define BCHP_PCIE_0_INTR2_CPU_STATUS_L1_TX_DMA_DONE_INTR_SHIFT 4
-#define BCHP_PCIE_0_INTR2_CPU_STATUS_L1_TX_DMA_DONE_INTR_DEFAULT 0x00000000
-
-/* PCIE_0_INTR2 :: CPU_STATUS :: L0_RX_DMA_ERR_INTR [03:03] */
-#define BCHP_PCIE_0_INTR2_CPU_STATUS_L0_RX_DMA_ERR_INTR_MASK 0x00000008
-#define BCHP_PCIE_0_INTR2_CPU_STATUS_L0_RX_DMA_ERR_INTR_SHIFT 3
-#define BCHP_PCIE_0_INTR2_CPU_STATUS_L0_RX_DMA_ERR_INTR_DEFAULT 0x00000000
-
-/* PCIE_0_INTR2 :: CPU_STATUS :: L0_RX_DMA_DONE_INTR [02:02] */
-#define BCHP_PCIE_0_INTR2_CPU_STATUS_L0_RX_DMA_DONE_INTR_MASK 0x00000004
-#define BCHP_PCIE_0_INTR2_CPU_STATUS_L0_RX_DMA_DONE_INTR_SHIFT 2
-#define BCHP_PCIE_0_INTR2_CPU_STATUS_L0_RX_DMA_DONE_INTR_DEFAULT 0x00000000
-
-/* PCIE_0_INTR2 :: CPU_STATUS :: L0_TX_DMA_ERR_INTR [01:01] */
-#define BCHP_PCIE_0_INTR2_CPU_STATUS_L0_TX_DMA_ERR_INTR_MASK 0x00000002
-#define BCHP_PCIE_0_INTR2_CPU_STATUS_L0_TX_DMA_ERR_INTR_SHIFT 1
-#define BCHP_PCIE_0_INTR2_CPU_STATUS_L0_TX_DMA_ERR_INTR_DEFAULT 0x00000000
-
-/* PCIE_0_INTR2 :: CPU_STATUS :: L0_TX_DMA_DONE_INTR [00:00] */
-#define BCHP_PCIE_0_INTR2_CPU_STATUS_L0_TX_DMA_DONE_INTR_MASK 0x00000001
-#define BCHP_PCIE_0_INTR2_CPU_STATUS_L0_TX_DMA_DONE_INTR_SHIFT 0
-#define BCHP_PCIE_0_INTR2_CPU_STATUS_L0_TX_DMA_DONE_INTR_DEFAULT 0x00000000
-
-/***************************************************************************
- *CPU_SET - CPU interrupt Set Register
- ***************************************************************************/
-/* PCIE_0_INTR2 :: CPU_SET :: MSI_INTR07 [31:31] */
-#define BCHP_PCIE_0_INTR2_CPU_SET_MSI_INTR07_MASK 0x80000000
-#define BCHP_PCIE_0_INTR2_CPU_SET_MSI_INTR07_SHIFT 31
-#define BCHP_PCIE_0_INTR2_CPU_SET_MSI_INTR07_DEFAULT 0x00000000
-
-/* PCIE_0_INTR2 :: CPU_SET :: MSI_INTR06 [30:30] */
-#define BCHP_PCIE_0_INTR2_CPU_SET_MSI_INTR06_MASK 0x40000000
-#define BCHP_PCIE_0_INTR2_CPU_SET_MSI_INTR06_SHIFT 30
-#define BCHP_PCIE_0_INTR2_CPU_SET_MSI_INTR06_DEFAULT 0x00000000
-
-/* PCIE_0_INTR2 :: CPU_SET :: MSI_INTR05 [29:29] */
-#define BCHP_PCIE_0_INTR2_CPU_SET_MSI_INTR05_MASK 0x20000000
-#define BCHP_PCIE_0_INTR2_CPU_SET_MSI_INTR05_SHIFT 29
-#define BCHP_PCIE_0_INTR2_CPU_SET_MSI_INTR05_DEFAULT 0x00000000
-
-/* PCIE_0_INTR2 :: CPU_SET :: MSI_INTR04 [28:28] */
-#define BCHP_PCIE_0_INTR2_CPU_SET_MSI_INTR04_MASK 0x10000000
-#define BCHP_PCIE_0_INTR2_CPU_SET_MSI_INTR04_SHIFT 28
-#define BCHP_PCIE_0_INTR2_CPU_SET_MSI_INTR04_DEFAULT 0x00000000
-
-/* PCIE_0_INTR2 :: CPU_SET :: MSI_INTR03 [27:27] */
-#define BCHP_PCIE_0_INTR2_CPU_SET_MSI_INTR03_MASK 0x08000000
-#define BCHP_PCIE_0_INTR2_CPU_SET_MSI_INTR03_SHIFT 27
-#define BCHP_PCIE_0_INTR2_CPU_SET_MSI_INTR03_DEFAULT 0x00000000
-
-/* PCIE_0_INTR2 :: CPU_SET :: MSI_INTR02 [26:26] */
-#define BCHP_PCIE_0_INTR2_CPU_SET_MSI_INTR02_MASK 0x04000000
-#define BCHP_PCIE_0_INTR2_CPU_SET_MSI_INTR02_SHIFT 26
-#define BCHP_PCIE_0_INTR2_CPU_SET_MSI_INTR02_DEFAULT 0x00000000
-
-/* PCIE_0_INTR2 :: CPU_SET :: MSI_INTR01 [25:25] */
-#define BCHP_PCIE_0_INTR2_CPU_SET_MSI_INTR01_MASK 0x02000000
-#define BCHP_PCIE_0_INTR2_CPU_SET_MSI_INTR01_SHIFT 25
-#define BCHP_PCIE_0_INTR2_CPU_SET_MSI_INTR01_DEFAULT 0x00000000
-
-/* PCIE_0_INTR2 :: CPU_SET :: MSI_INTR00 [24:24] */
-#define BCHP_PCIE_0_INTR2_CPU_SET_MSI_INTR00_MASK 0x01000000
-#define BCHP_PCIE_0_INTR2_CPU_SET_MSI_INTR00_SHIFT 24
-#define BCHP_PCIE_0_INTR2_CPU_SET_MSI_INTR00_DEFAULT 0x00000000
-
-/* PCIE_0_INTR2 :: CPU_SET :: UNASSIGNED_23 [23:23] */
-#define BCHP_PCIE_0_INTR2_CPU_SET_UNASSIGNED_23_MASK 0x00800000
-#define BCHP_PCIE_0_INTR2_CPU_SET_UNASSIGNED_23_SHIFT 23
-#define BCHP_PCIE_0_INTR2_CPU_SET_UNASSIGNED_23_DEFAULT 0x00000000
-
-/* PCIE_0_INTR2 :: CPU_SET :: UNASSIGNED_22 [22:22] */
-#define BCHP_PCIE_0_INTR2_CPU_SET_UNASSIGNED_22_MASK 0x00400000
-#define BCHP_PCIE_0_INTR2_CPU_SET_UNASSIGNED_22_SHIFT 22
-#define BCHP_PCIE_0_INTR2_CPU_SET_UNASSIGNED_22_DEFAULT 0x00000000
-
-/* PCIE_0_INTR2 :: CPU_SET :: UNASSIGNED_21 [21:21] */
-#define BCHP_PCIE_0_INTR2_CPU_SET_UNASSIGNED_21_MASK 0x00200000
-#define BCHP_PCIE_0_INTR2_CPU_SET_UNASSIGNED_21_SHIFT 21
-#define BCHP_PCIE_0_INTR2_CPU_SET_UNASSIGNED_21_DEFAULT 0x00000000
-
-/* PCIE_0_INTR2 :: CPU_SET :: UNASSIGNED_20 [20:20] */
-#define BCHP_PCIE_0_INTR2_CPU_SET_UNASSIGNED_20_MASK 0x00100000
-#define BCHP_PCIE_0_INTR2_CPU_SET_UNASSIGNED_20_SHIFT 20
-#define BCHP_PCIE_0_INTR2_CPU_SET_UNASSIGNED_20_DEFAULT 0x00000000
-
-/* PCIE_0_INTR2 :: CPU_SET :: MAILBOX_3 [19:19] */
-#define BCHP_PCIE_0_INTR2_CPU_SET_MAILBOX_3_MASK 0x00080000
-#define BCHP_PCIE_0_INTR2_CPU_SET_MAILBOX_3_SHIFT 19
-#define BCHP_PCIE_0_INTR2_CPU_SET_MAILBOX_3_DEFAULT 0x00000000
-
-/* PCIE_0_INTR2 :: CPU_SET :: MAILBOX_2 [18:18] */
-#define BCHP_PCIE_0_INTR2_CPU_SET_MAILBOX_2_MASK 0x00040000
-#define BCHP_PCIE_0_INTR2_CPU_SET_MAILBOX_2_SHIFT 18
-#define BCHP_PCIE_0_INTR2_CPU_SET_MAILBOX_2_DEFAULT 0x00000000
-
-/* PCIE_0_INTR2 :: CPU_SET :: MAILBOX_1 [17:17] */
-#define BCHP_PCIE_0_INTR2_CPU_SET_MAILBOX_1_MASK 0x00020000
-#define BCHP_PCIE_0_INTR2_CPU_SET_MAILBOX_1_SHIFT 17
-#define BCHP_PCIE_0_INTR2_CPU_SET_MAILBOX_1_DEFAULT 0x00000000
-
-/* PCIE_0_INTR2 :: CPU_SET :: MAILBOX_0 [16:16] */
-#define BCHP_PCIE_0_INTR2_CPU_SET_MAILBOX_0_MASK 0x00010000
-#define BCHP_PCIE_0_INTR2_CPU_SET_MAILBOX_0_SHIFT 16
-#define BCHP_PCIE_0_INTR2_CPU_SET_MAILBOX_0_DEFAULT 0x00000000
-
-/* PCIE_0_INTR2 :: CPU_SET :: PCIE_MSTR_FWD_ERR [15:15] */
-#define BCHP_PCIE_0_INTR2_CPU_SET_PCIE_MSTR_FWD_ERR_MASK 0x00008000
-#define BCHP_PCIE_0_INTR2_CPU_SET_PCIE_MSTR_FWD_ERR_SHIFT 15
-#define BCHP_PCIE_0_INTR2_CPU_SET_PCIE_MSTR_FWD_ERR_DEFAULT 0x00000000
-
-/* PCIE_0_INTR2 :: CPU_SET :: PCIE_MSTR_RETRY_TIMEOUT [14:14] */
-#define BCHP_PCIE_0_INTR2_CPU_SET_PCIE_MSTR_RETRY_TIMEOUT_MASK 0x00004000
-#define BCHP_PCIE_0_INTR2_CPU_SET_PCIE_MSTR_RETRY_TIMEOUT_SHIFT 14
-#define BCHP_PCIE_0_INTR2_CPU_SET_PCIE_MSTR_RETRY_TIMEOUT_DEFAULT 0x00000000
-
-/* PCIE_0_INTR2 :: CPU_SET :: PCIE_MSTR_CA_ATTN [13:13] */
-#define BCHP_PCIE_0_INTR2_CPU_SET_PCIE_MSTR_CA_ATTN_MASK 0x00002000
-#define BCHP_PCIE_0_INTR2_CPU_SET_PCIE_MSTR_CA_ATTN_SHIFT 13
-#define BCHP_PCIE_0_INTR2_CPU_SET_PCIE_MSTR_CA_ATTN_DEFAULT 0x00000000
-
-/* PCIE_0_INTR2 :: CPU_SET :: PCIE_MSTR_UR_ATTN [12:12] */
-#define BCHP_PCIE_0_INTR2_CPU_SET_PCIE_MSTR_UR_ATTN_MASK 0x00001000
-#define BCHP_PCIE_0_INTR2_CPU_SET_PCIE_MSTR_UR_ATTN_SHIFT 12
-#define BCHP_PCIE_0_INTR2_CPU_SET_PCIE_MSTR_UR_ATTN_DEFAULT 0x00000000
-
-/* PCIE_0_INTR2 :: CPU_SET :: UNASSIGNED_11 [11:11] */
-#define BCHP_PCIE_0_INTR2_CPU_SET_UNASSIGNED_11_MASK 0x00000800
-#define BCHP_PCIE_0_INTR2_CPU_SET_UNASSIGNED_11_SHIFT 11
-#define BCHP_PCIE_0_INTR2_CPU_SET_UNASSIGNED_11_DEFAULT 0x00000000
-
-/* PCIE_0_INTR2 :: CPU_SET :: UNASSIGNED_10 [10:10] */
-#define BCHP_PCIE_0_INTR2_CPU_SET_UNASSIGNED_10_MASK 0x00000400
-#define BCHP_PCIE_0_INTR2_CPU_SET_UNASSIGNED_10_SHIFT 10
-#define BCHP_PCIE_0_INTR2_CPU_SET_UNASSIGNED_10_DEFAULT 0x00000000
-
-/* PCIE_0_INTR2 :: CPU_SET :: PCIE_TGT_BAD_ACCESS [09:09] */
-#define BCHP_PCIE_0_INTR2_CPU_SET_PCIE_TGT_BAD_ACCESS_MASK 0x00000200
-#define BCHP_PCIE_0_INTR2_CPU_SET_PCIE_TGT_BAD_ACCESS_SHIFT 9
-#define BCHP_PCIE_0_INTR2_CPU_SET_PCIE_TGT_BAD_ACCESS_DEFAULT 0x00000000
-
-/* PCIE_0_INTR2 :: CPU_SET :: PCIE_TGT_BAD_ADDRESS [08:08] */
-#define BCHP_PCIE_0_INTR2_CPU_SET_PCIE_TGT_BAD_ADDRESS_MASK 0x00000100
-#define BCHP_PCIE_0_INTR2_CPU_SET_PCIE_TGT_BAD_ADDRESS_SHIFT 8
-#define BCHP_PCIE_0_INTR2_CPU_SET_PCIE_TGT_BAD_ADDRESS_DEFAULT 0x00000000
-
-/* PCIE_0_INTR2 :: CPU_SET :: L1_RX_DMA_ERR_INTR [07:07] */
-#define BCHP_PCIE_0_INTR2_CPU_SET_L1_RX_DMA_ERR_INTR_MASK 0x00000080
-#define BCHP_PCIE_0_INTR2_CPU_SET_L1_RX_DMA_ERR_INTR_SHIFT 7
-#define BCHP_PCIE_0_INTR2_CPU_SET_L1_RX_DMA_ERR_INTR_DEFAULT 0x00000000
-
-/* PCIE_0_INTR2 :: CPU_SET :: L1_RX_DMA_DONE_INTR [06:06] */
-#define BCHP_PCIE_0_INTR2_CPU_SET_L1_RX_DMA_DONE_INTR_MASK 0x00000040
-#define BCHP_PCIE_0_INTR2_CPU_SET_L1_RX_DMA_DONE_INTR_SHIFT 6
-#define BCHP_PCIE_0_INTR2_CPU_SET_L1_RX_DMA_DONE_INTR_DEFAULT 0x00000000
-
-/* PCIE_0_INTR2 :: CPU_SET :: L1_TX_DMA_ERR_INTR [05:05] */
-#define BCHP_PCIE_0_INTR2_CPU_SET_L1_TX_DMA_ERR_INTR_MASK 0x00000020
-#define BCHP_PCIE_0_INTR2_CPU_SET_L1_TX_DMA_ERR_INTR_SHIFT 5
-#define BCHP_PCIE_0_INTR2_CPU_SET_L1_TX_DMA_ERR_INTR_DEFAULT 0x00000000
-
-/* PCIE_0_INTR2 :: CPU_SET :: L1_TX_DMA_DONE_INTR [04:04] */
-#define BCHP_PCIE_0_INTR2_CPU_SET_L1_TX_DMA_DONE_INTR_MASK 0x00000010
-#define BCHP_PCIE_0_INTR2_CPU_SET_L1_TX_DMA_DONE_INTR_SHIFT 4
-#define BCHP_PCIE_0_INTR2_CPU_SET_L1_TX_DMA_DONE_INTR_DEFAULT 0x00000000
-
-/* PCIE_0_INTR2 :: CPU_SET :: L0_RX_DMA_ERR_INTR [03:03] */
-#define BCHP_PCIE_0_INTR2_CPU_SET_L0_RX_DMA_ERR_INTR_MASK 0x00000008
-#define BCHP_PCIE_0_INTR2_CPU_SET_L0_RX_DMA_ERR_INTR_SHIFT 3
-#define BCHP_PCIE_0_INTR2_CPU_SET_L0_RX_DMA_ERR_INTR_DEFAULT 0x00000000
-
-/* PCIE_0_INTR2 :: CPU_SET :: L0_RX_DMA_DONE_INTR [02:02] */
-#define BCHP_PCIE_0_INTR2_CPU_SET_L0_RX_DMA_DONE_INTR_MASK 0x00000004
-#define BCHP_PCIE_0_INTR2_CPU_SET_L0_RX_DMA_DONE_INTR_SHIFT 2
-#define BCHP_PCIE_0_INTR2_CPU_SET_L0_RX_DMA_DONE_INTR_DEFAULT 0x00000000
-
-/* PCIE_0_INTR2 :: CPU_SET :: L0_TX_DMA_ERR_INTR [01:01] */
-#define BCHP_PCIE_0_INTR2_CPU_SET_L0_TX_DMA_ERR_INTR_MASK 0x00000002
-#define BCHP_PCIE_0_INTR2_CPU_SET_L0_TX_DMA_ERR_INTR_SHIFT 1
-#define BCHP_PCIE_0_INTR2_CPU_SET_L0_TX_DMA_ERR_INTR_DEFAULT 0x00000000
-
-/* PCIE_0_INTR2 :: CPU_SET :: L0_TX_DMA_DONE_INTR [00:00] */
-#define BCHP_PCIE_0_INTR2_CPU_SET_L0_TX_DMA_DONE_INTR_MASK 0x00000001
-#define BCHP_PCIE_0_INTR2_CPU_SET_L0_TX_DMA_DONE_INTR_SHIFT 0
-#define BCHP_PCIE_0_INTR2_CPU_SET_L0_TX_DMA_DONE_INTR_DEFAULT 0x00000000
-
-/***************************************************************************
- *CPU_CLEAR - CPU interrupt Clear Register
- ***************************************************************************/
-/* PCIE_0_INTR2 :: CPU_CLEAR :: MSI_INTR07 [31:31] */
-#define BCHP_PCIE_0_INTR2_CPU_CLEAR_MSI_INTR07_MASK 0x80000000
-#define BCHP_PCIE_0_INTR2_CPU_CLEAR_MSI_INTR07_SHIFT 31
-#define BCHP_PCIE_0_INTR2_CPU_CLEAR_MSI_INTR07_DEFAULT 0x00000000
-
-/* PCIE_0_INTR2 :: CPU_CLEAR :: MSI_INTR06 [30:30] */
-#define BCHP_PCIE_0_INTR2_CPU_CLEAR_MSI_INTR06_MASK 0x40000000
-#define BCHP_PCIE_0_INTR2_CPU_CLEAR_MSI_INTR06_SHIFT 30
-#define BCHP_PCIE_0_INTR2_CPU_CLEAR_MSI_INTR06_DEFAULT 0x00000000
-
-/* PCIE_0_INTR2 :: CPU_CLEAR :: MSI_INTR05 [29:29] */
-#define BCHP_PCIE_0_INTR2_CPU_CLEAR_MSI_INTR05_MASK 0x20000000
-#define BCHP_PCIE_0_INTR2_CPU_CLEAR_MSI_INTR05_SHIFT 29
-#define BCHP_PCIE_0_INTR2_CPU_CLEAR_MSI_INTR05_DEFAULT 0x00000000
-
-/* PCIE_0_INTR2 :: CPU_CLEAR :: MSI_INTR04 [28:28] */
-#define BCHP_PCIE_0_INTR2_CPU_CLEAR_MSI_INTR04_MASK 0x10000000
-#define BCHP_PCIE_0_INTR2_CPU_CLEAR_MSI_INTR04_SHIFT 28
-#define BCHP_PCIE_0_INTR2_CPU_CLEAR_MSI_INTR04_DEFAULT 0x00000000
-
-/* PCIE_0_INTR2 :: CPU_CLEAR :: MSI_INTR03 [27:27] */
-#define BCHP_PCIE_0_INTR2_CPU_CLEAR_MSI_INTR03_MASK 0x08000000
-#define BCHP_PCIE_0_INTR2_CPU_CLEAR_MSI_INTR03_SHIFT 27
-#define BCHP_PCIE_0_INTR2_CPU_CLEAR_MSI_INTR03_DEFAULT 0x00000000
-
-/* PCIE_0_INTR2 :: CPU_CLEAR :: MSI_INTR02 [26:26] */
-#define BCHP_PCIE_0_INTR2_CPU_CLEAR_MSI_INTR02_MASK 0x04000000
-#define BCHP_PCIE_0_INTR2_CPU_CLEAR_MSI_INTR02_SHIFT 26
-#define BCHP_PCIE_0_INTR2_CPU_CLEAR_MSI_INTR02_DEFAULT 0x00000000
-
-/* PCIE_0_INTR2 :: CPU_CLEAR :: MSI_INTR01 [25:25] */
-#define BCHP_PCIE_0_INTR2_CPU_CLEAR_MSI_INTR01_MASK 0x02000000
-#define BCHP_PCIE_0_INTR2_CPU_CLEAR_MSI_INTR01_SHIFT 25
-#define BCHP_PCIE_0_INTR2_CPU_CLEAR_MSI_INTR01_DEFAULT 0x00000000
-
-/* PCIE_0_INTR2 :: CPU_CLEAR :: MSI_INTR00 [24:24] */
-#define BCHP_PCIE_0_INTR2_CPU_CLEAR_MSI_INTR00_MASK 0x01000000
-#define BCHP_PCIE_0_INTR2_CPU_CLEAR_MSI_INTR00_SHIFT 24
-#define BCHP_PCIE_0_INTR2_CPU_CLEAR_MSI_INTR00_DEFAULT 0x00000000
-
-/* PCIE_0_INTR2 :: CPU_CLEAR :: UNASSIGNED_23 [23:23] */
-#define BCHP_PCIE_0_INTR2_CPU_CLEAR_UNASSIGNED_23_MASK 0x00800000
-#define BCHP_PCIE_0_INTR2_CPU_CLEAR_UNASSIGNED_23_SHIFT 23
-#define BCHP_PCIE_0_INTR2_CPU_CLEAR_UNASSIGNED_23_DEFAULT 0x00000000
-
-/* PCIE_0_INTR2 :: CPU_CLEAR :: UNASSIGNED_22 [22:22] */
-#define BCHP_PCIE_0_INTR2_CPU_CLEAR_UNASSIGNED_22_MASK 0x00400000
-#define BCHP_PCIE_0_INTR2_CPU_CLEAR_UNASSIGNED_22_SHIFT 22
-#define BCHP_PCIE_0_INTR2_CPU_CLEAR_UNASSIGNED_22_DEFAULT 0x00000000
-
-/* PCIE_0_INTR2 :: CPU_CLEAR :: UNASSIGNED_21 [21:21] */
-#define BCHP_PCIE_0_INTR2_CPU_CLEAR_UNASSIGNED_21_MASK 0x00200000
-#define BCHP_PCIE_0_INTR2_CPU_CLEAR_UNASSIGNED_21_SHIFT 21
-#define BCHP_PCIE_0_INTR2_CPU_CLEAR_UNASSIGNED_21_DEFAULT 0x00000000
-
-/* PCIE_0_INTR2 :: CPU_CLEAR :: UNASSIGNED_20 [20:20] */
-#define BCHP_PCIE_0_INTR2_CPU_CLEAR_UNASSIGNED_20_MASK 0x00100000
-#define BCHP_PCIE_0_INTR2_CPU_CLEAR_UNASSIGNED_20_SHIFT 20
-#define BCHP_PCIE_0_INTR2_CPU_CLEAR_UNASSIGNED_20_DEFAULT 0x00000000
-
-/* PCIE_0_INTR2 :: CPU_CLEAR :: MAILBOX_3 [19:19] */
-#define BCHP_PCIE_0_INTR2_CPU_CLEAR_MAILBOX_3_MASK 0x00080000
-#define BCHP_PCIE_0_INTR2_CPU_CLEAR_MAILBOX_3_SHIFT 19
-#define BCHP_PCIE_0_INTR2_CPU_CLEAR_MAILBOX_3_DEFAULT 0x00000000
-
-/* PCIE_0_INTR2 :: CPU_CLEAR :: MAILBOX_2 [18:18] */
-#define BCHP_PCIE_0_INTR2_CPU_CLEAR_MAILBOX_2_MASK 0x00040000
-#define BCHP_PCIE_0_INTR2_CPU_CLEAR_MAILBOX_2_SHIFT 18
-#define BCHP_PCIE_0_INTR2_CPU_CLEAR_MAILBOX_2_DEFAULT 0x00000000
-
-/* PCIE_0_INTR2 :: CPU_CLEAR :: MAILBOX_1 [17:17] */
-#define BCHP_PCIE_0_INTR2_CPU_CLEAR_MAILBOX_1_MASK 0x00020000
-#define BCHP_PCIE_0_INTR2_CPU_CLEAR_MAILBOX_1_SHIFT 17
-#define BCHP_PCIE_0_INTR2_CPU_CLEAR_MAILBOX_1_DEFAULT 0x00000000
-
-/* PCIE_0_INTR2 :: CPU_CLEAR :: MAILBOX_0 [16:16] */
-#define BCHP_PCIE_0_INTR2_CPU_CLEAR_MAILBOX_0_MASK 0x00010000
-#define BCHP_PCIE_0_INTR2_CPU_CLEAR_MAILBOX_0_SHIFT 16
-#define BCHP_PCIE_0_INTR2_CPU_CLEAR_MAILBOX_0_DEFAULT 0x00000000
-
-/* PCIE_0_INTR2 :: CPU_CLEAR :: PCIE_MSTR_FWD_ERR [15:15] */
-#define BCHP_PCIE_0_INTR2_CPU_CLEAR_PCIE_MSTR_FWD_ERR_MASK 0x00008000
-#define BCHP_PCIE_0_INTR2_CPU_CLEAR_PCIE_MSTR_FWD_ERR_SHIFT 15
-#define BCHP_PCIE_0_INTR2_CPU_CLEAR_PCIE_MSTR_FWD_ERR_DEFAULT 0x00000000
-
-/* PCIE_0_INTR2 :: CPU_CLEAR :: PCIE_MSTR_RETRY_TIMEOUT [14:14] */
-#define BCHP_PCIE_0_INTR2_CPU_CLEAR_PCIE_MSTR_RETRY_TIMEOUT_MASK 0x00004000
-#define BCHP_PCIE_0_INTR2_CPU_CLEAR_PCIE_MSTR_RETRY_TIMEOUT_SHIFT 14
-#define BCHP_PCIE_0_INTR2_CPU_CLEAR_PCIE_MSTR_RETRY_TIMEOUT_DEFAULT 0x00000000
-
-/* PCIE_0_INTR2 :: CPU_CLEAR :: PCIE_MSTR_CA_ATTN [13:13] */
-#define BCHP_PCIE_0_INTR2_CPU_CLEAR_PCIE_MSTR_CA_ATTN_MASK 0x00002000
-#define BCHP_PCIE_0_INTR2_CPU_CLEAR_PCIE_MSTR_CA_ATTN_SHIFT 13
-#define BCHP_PCIE_0_INTR2_CPU_CLEAR_PCIE_MSTR_CA_ATTN_DEFAULT 0x00000000
-
-/* PCIE_0_INTR2 :: CPU_CLEAR :: PCIE_MSTR_UR_ATTN [12:12] */
-#define BCHP_PCIE_0_INTR2_CPU_CLEAR_PCIE_MSTR_UR_ATTN_MASK 0x00001000
-#define BCHP_PCIE_0_INTR2_CPU_CLEAR_PCIE_MSTR_UR_ATTN_SHIFT 12
-#define BCHP_PCIE_0_INTR2_CPU_CLEAR_PCIE_MSTR_UR_ATTN_DEFAULT 0x00000000
-
-/* PCIE_0_INTR2 :: CPU_CLEAR :: UNASSIGNED_11 [11:11] */
-#define BCHP_PCIE_0_INTR2_CPU_CLEAR_UNASSIGNED_11_MASK 0x00000800
-#define BCHP_PCIE_0_INTR2_CPU_CLEAR_UNASSIGNED_11_SHIFT 11
-#define BCHP_PCIE_0_INTR2_CPU_CLEAR_UNASSIGNED_11_DEFAULT 0x00000000
-
-/* PCIE_0_INTR2 :: CPU_CLEAR :: UNASSIGNED_10 [10:10] */
-#define BCHP_PCIE_0_INTR2_CPU_CLEAR_UNASSIGNED_10_MASK 0x00000400
-#define BCHP_PCIE_0_INTR2_CPU_CLEAR_UNASSIGNED_10_SHIFT 10
-#define BCHP_PCIE_0_INTR2_CPU_CLEAR_UNASSIGNED_10_DEFAULT 0x00000000
-
-/* PCIE_0_INTR2 :: CPU_CLEAR :: PCIE_TGT_BAD_ACCESS [09:09] */
-#define BCHP_PCIE_0_INTR2_CPU_CLEAR_PCIE_TGT_BAD_ACCESS_MASK 0x00000200
-#define BCHP_PCIE_0_INTR2_CPU_CLEAR_PCIE_TGT_BAD_ACCESS_SHIFT 9
-#define BCHP_PCIE_0_INTR2_CPU_CLEAR_PCIE_TGT_BAD_ACCESS_DEFAULT 0x00000000
-
-/* PCIE_0_INTR2 :: CPU_CLEAR :: PCIE_TGT_BAD_ADDRESS [08:08] */
-#define BCHP_PCIE_0_INTR2_CPU_CLEAR_PCIE_TGT_BAD_ADDRESS_MASK 0x00000100
-#define BCHP_PCIE_0_INTR2_CPU_CLEAR_PCIE_TGT_BAD_ADDRESS_SHIFT 8
-#define BCHP_PCIE_0_INTR2_CPU_CLEAR_PCIE_TGT_BAD_ADDRESS_DEFAULT 0x00000000
-
-/* PCIE_0_INTR2 :: CPU_CLEAR :: L1_RX_DMA_ERR_INTR [07:07] */
-#define BCHP_PCIE_0_INTR2_CPU_CLEAR_L1_RX_DMA_ERR_INTR_MASK 0x00000080
-#define BCHP_PCIE_0_INTR2_CPU_CLEAR_L1_RX_DMA_ERR_INTR_SHIFT 7
-#define BCHP_PCIE_0_INTR2_CPU_CLEAR_L1_RX_DMA_ERR_INTR_DEFAULT 0x00000000
-
-/* PCIE_0_INTR2 :: CPU_CLEAR :: L1_RX_DMA_DONE_INTR [06:06] */
-#define BCHP_PCIE_0_INTR2_CPU_CLEAR_L1_RX_DMA_DONE_INTR_MASK 0x00000040
-#define BCHP_PCIE_0_INTR2_CPU_CLEAR_L1_RX_DMA_DONE_INTR_SHIFT 6
-#define BCHP_PCIE_0_INTR2_CPU_CLEAR_L1_RX_DMA_DONE_INTR_DEFAULT 0x00000000
-
-/* PCIE_0_INTR2 :: CPU_CLEAR :: L1_TX_DMA_ERR_INTR [05:05] */
-#define BCHP_PCIE_0_INTR2_CPU_CLEAR_L1_TX_DMA_ERR_INTR_MASK 0x00000020
-#define BCHP_PCIE_0_INTR2_CPU_CLEAR_L1_TX_DMA_ERR_INTR_SHIFT 5
-#define BCHP_PCIE_0_INTR2_CPU_CLEAR_L1_TX_DMA_ERR_INTR_DEFAULT 0x00000000
-
-/* PCIE_0_INTR2 :: CPU_CLEAR :: L1_TX_DMA_DONE_INTR [04:04] */
-#define BCHP_PCIE_0_INTR2_CPU_CLEAR_L1_TX_DMA_DONE_INTR_MASK 0x00000010
-#define BCHP_PCIE_0_INTR2_CPU_CLEAR_L1_TX_DMA_DONE_INTR_SHIFT 4
-#define BCHP_PCIE_0_INTR2_CPU_CLEAR_L1_TX_DMA_DONE_INTR_DEFAULT 0x00000000
-
-/* PCIE_0_INTR2 :: CPU_CLEAR :: L0_RX_DMA_ERR_INTR [03:03] */
-#define BCHP_PCIE_0_INTR2_CPU_CLEAR_L0_RX_DMA_ERR_INTR_MASK 0x00000008
-#define BCHP_PCIE_0_INTR2_CPU_CLEAR_L0_RX_DMA_ERR_INTR_SHIFT 3
-#define BCHP_PCIE_0_INTR2_CPU_CLEAR_L0_RX_DMA_ERR_INTR_DEFAULT 0x00000000
-
-/* PCIE_0_INTR2 :: CPU_CLEAR :: L0_RX_DMA_DONE_INTR [02:02] */
-#define BCHP_PCIE_0_INTR2_CPU_CLEAR_L0_RX_DMA_DONE_INTR_MASK 0x00000004
-#define BCHP_PCIE_0_INTR2_CPU_CLEAR_L0_RX_DMA_DONE_INTR_SHIFT 2
-#define BCHP_PCIE_0_INTR2_CPU_CLEAR_L0_RX_DMA_DONE_INTR_DEFAULT 0x00000000
-
-/* PCIE_0_INTR2 :: CPU_CLEAR :: L0_TX_DMA_ERR_INTR [01:01] */
-#define BCHP_PCIE_0_INTR2_CPU_CLEAR_L0_TX_DMA_ERR_INTR_MASK 0x00000002
-#define BCHP_PCIE_0_INTR2_CPU_CLEAR_L0_TX_DMA_ERR_INTR_SHIFT 1
-#define BCHP_PCIE_0_INTR2_CPU_CLEAR_L0_TX_DMA_ERR_INTR_DEFAULT 0x00000000
-
-/* PCIE_0_INTR2 :: CPU_CLEAR :: L0_TX_DMA_DONE_INTR [00:00] */
-#define BCHP_PCIE_0_INTR2_CPU_CLEAR_L0_TX_DMA_DONE_INTR_MASK 0x00000001
-#define BCHP_PCIE_0_INTR2_CPU_CLEAR_L0_TX_DMA_DONE_INTR_SHIFT 0
-#define BCHP_PCIE_0_INTR2_CPU_CLEAR_L0_TX_DMA_DONE_INTR_DEFAULT 0x00000000
-
-/***************************************************************************
- *CPU_MASK_STATUS - CPU interrupt Mask Status Register
- ***************************************************************************/
-/* PCIE_0_INTR2 :: CPU_MASK_STATUS :: MSI_INTR07 [31:31] */
-#define BCHP_PCIE_0_INTR2_CPU_MASK_STATUS_MSI_INTR07_MASK 0x80000000
-#define BCHP_PCIE_0_INTR2_CPU_MASK_STATUS_MSI_INTR07_SHIFT 31
-#define BCHP_PCIE_0_INTR2_CPU_MASK_STATUS_MSI_INTR07_DEFAULT 0x00000001
-
-/* PCIE_0_INTR2 :: CPU_MASK_STATUS :: MSI_INTR06 [30:30] */
-#define BCHP_PCIE_0_INTR2_CPU_MASK_STATUS_MSI_INTR06_MASK 0x40000000
-#define BCHP_PCIE_0_INTR2_CPU_MASK_STATUS_MSI_INTR06_SHIFT 30
-#define BCHP_PCIE_0_INTR2_CPU_MASK_STATUS_MSI_INTR06_DEFAULT 0x00000001
-
-/* PCIE_0_INTR2 :: CPU_MASK_STATUS :: MSI_INTR05 [29:29] */
-#define BCHP_PCIE_0_INTR2_CPU_MASK_STATUS_MSI_INTR05_MASK 0x20000000
-#define BCHP_PCIE_0_INTR2_CPU_MASK_STATUS_MSI_INTR05_SHIFT 29
-#define BCHP_PCIE_0_INTR2_CPU_MASK_STATUS_MSI_INTR05_DEFAULT 0x00000001
-
-/* PCIE_0_INTR2 :: CPU_MASK_STATUS :: MSI_INTR04 [28:28] */
-#define BCHP_PCIE_0_INTR2_CPU_MASK_STATUS_MSI_INTR04_MASK 0x10000000
-#define BCHP_PCIE_0_INTR2_CPU_MASK_STATUS_MSI_INTR04_SHIFT 28
-#define BCHP_PCIE_0_INTR2_CPU_MASK_STATUS_MSI_INTR04_DEFAULT 0x00000001
-
-/* PCIE_0_INTR2 :: CPU_MASK_STATUS :: MSI_INTR03 [27:27] */
-#define BCHP_PCIE_0_INTR2_CPU_MASK_STATUS_MSI_INTR03_MASK 0x08000000
-#define BCHP_PCIE_0_INTR2_CPU_MASK_STATUS_MSI_INTR03_SHIFT 27
-#define BCHP_PCIE_0_INTR2_CPU_MASK_STATUS_MSI_INTR03_DEFAULT 0x00000001
-
-/* PCIE_0_INTR2 :: CPU_MASK_STATUS :: MSI_INTR02 [26:26] */
-#define BCHP_PCIE_0_INTR2_CPU_MASK_STATUS_MSI_INTR02_MASK 0x04000000
-#define BCHP_PCIE_0_INTR2_CPU_MASK_STATUS_MSI_INTR02_SHIFT 26
-#define BCHP_PCIE_0_INTR2_CPU_MASK_STATUS_MSI_INTR02_DEFAULT 0x00000001
-
-/* PCIE_0_INTR2 :: CPU_MASK_STATUS :: MSI_INTR01 [25:25] */
-#define BCHP_PCIE_0_INTR2_CPU_MASK_STATUS_MSI_INTR01_MASK 0x02000000
-#define BCHP_PCIE_0_INTR2_CPU_MASK_STATUS_MSI_INTR01_SHIFT 25
-#define BCHP_PCIE_0_INTR2_CPU_MASK_STATUS_MSI_INTR01_DEFAULT 0x00000001
-
-/* PCIE_0_INTR2 :: CPU_MASK_STATUS :: MSI_INTR00 [24:24] */
-#define BCHP_PCIE_0_INTR2_CPU_MASK_STATUS_MSI_INTR00_MASK 0x01000000
-#define BCHP_PCIE_0_INTR2_CPU_MASK_STATUS_MSI_INTR00_SHIFT 24
-#define BCHP_PCIE_0_INTR2_CPU_MASK_STATUS_MSI_INTR00_DEFAULT 0x00000001
-
-/* PCIE_0_INTR2 :: CPU_MASK_STATUS :: UNASSIGNED_23 [23:23] */
-#define BCHP_PCIE_0_INTR2_CPU_MASK_STATUS_UNASSIGNED_23_MASK 0x00800000
-#define BCHP_PCIE_0_INTR2_CPU_MASK_STATUS_UNASSIGNED_23_SHIFT 23
-#define BCHP_PCIE_0_INTR2_CPU_MASK_STATUS_UNASSIGNED_23_DEFAULT 0x00000001
-
-/* PCIE_0_INTR2 :: CPU_MASK_STATUS :: UNASSIGNED_22 [22:22] */
-#define BCHP_PCIE_0_INTR2_CPU_MASK_STATUS_UNASSIGNED_22_MASK 0x00400000
-#define BCHP_PCIE_0_INTR2_CPU_MASK_STATUS_UNASSIGNED_22_SHIFT 22
-#define BCHP_PCIE_0_INTR2_CPU_MASK_STATUS_UNASSIGNED_22_DEFAULT 0x00000001
-
-/* PCIE_0_INTR2 :: CPU_MASK_STATUS :: UNASSIGNED_21 [21:21] */
-#define BCHP_PCIE_0_INTR2_CPU_MASK_STATUS_UNASSIGNED_21_MASK 0x00200000
-#define BCHP_PCIE_0_INTR2_CPU_MASK_STATUS_UNASSIGNED_21_SHIFT 21
-#define BCHP_PCIE_0_INTR2_CPU_MASK_STATUS_UNASSIGNED_21_DEFAULT 0x00000001
-
-/* PCIE_0_INTR2 :: CPU_MASK_STATUS :: UNASSIGNED_20 [20:20] */
-#define BCHP_PCIE_0_INTR2_CPU_MASK_STATUS_UNASSIGNED_20_MASK 0x00100000
-#define BCHP_PCIE_0_INTR2_CPU_MASK_STATUS_UNASSIGNED_20_SHIFT 20
-#define BCHP_PCIE_0_INTR2_CPU_MASK_STATUS_UNASSIGNED_20_DEFAULT 0x00000001
-
-/* PCIE_0_INTR2 :: CPU_MASK_STATUS :: MAILBOX_3 [19:19] */
-#define BCHP_PCIE_0_INTR2_CPU_MASK_STATUS_MAILBOX_3_MASK 0x00080000
-#define BCHP_PCIE_0_INTR2_CPU_MASK_STATUS_MAILBOX_3_SHIFT 19
-#define BCHP_PCIE_0_INTR2_CPU_MASK_STATUS_MAILBOX_3_DEFAULT 0x00000001
-
-/* PCIE_0_INTR2 :: CPU_MASK_STATUS :: MAILBOX_2 [18:18] */
-#define BCHP_PCIE_0_INTR2_CPU_MASK_STATUS_MAILBOX_2_MASK 0x00040000
-#define BCHP_PCIE_0_INTR2_CPU_MASK_STATUS_MAILBOX_2_SHIFT 18
-#define BCHP_PCIE_0_INTR2_CPU_MASK_STATUS_MAILBOX_2_DEFAULT 0x00000001
-
-/* PCIE_0_INTR2 :: CPU_MASK_STATUS :: MAILBOX_1 [17:17] */
-#define BCHP_PCIE_0_INTR2_CPU_MASK_STATUS_MAILBOX_1_MASK 0x00020000
-#define BCHP_PCIE_0_INTR2_CPU_MASK_STATUS_MAILBOX_1_SHIFT 17
-#define BCHP_PCIE_0_INTR2_CPU_MASK_STATUS_MAILBOX_1_DEFAULT 0x00000001
-
-/* PCIE_0_INTR2 :: CPU_MASK_STATUS :: MAILBOX_0 [16:16] */
-#define BCHP_PCIE_0_INTR2_CPU_MASK_STATUS_MAILBOX_0_MASK 0x00010000
-#define BCHP_PCIE_0_INTR2_CPU_MASK_STATUS_MAILBOX_0_SHIFT 16
-#define BCHP_PCIE_0_INTR2_CPU_MASK_STATUS_MAILBOX_0_DEFAULT 0x00000001
-
-/* PCIE_0_INTR2 :: CPU_MASK_STATUS :: PCIE_MSTR_FWD_ERR [15:15] */
-#define BCHP_PCIE_0_INTR2_CPU_MASK_STATUS_PCIE_MSTR_FWD_ERR_MASK 0x00008000
-#define BCHP_PCIE_0_INTR2_CPU_MASK_STATUS_PCIE_MSTR_FWD_ERR_SHIFT 15
-#define BCHP_PCIE_0_INTR2_CPU_MASK_STATUS_PCIE_MSTR_FWD_ERR_DEFAULT 0x00000001
-
-/* PCIE_0_INTR2 :: CPU_MASK_STATUS :: PCIE_MSTR_RETRY_TIMEOUT [14:14] */
-#define BCHP_PCIE_0_INTR2_CPU_MASK_STATUS_PCIE_MSTR_RETRY_TIMEOUT_MASK 0x00004000
-#define BCHP_PCIE_0_INTR2_CPU_MASK_STATUS_PCIE_MSTR_RETRY_TIMEOUT_SHIFT 14
-#define BCHP_PCIE_0_INTR2_CPU_MASK_STATUS_PCIE_MSTR_RETRY_TIMEOUT_DEFAULT 0x00000001
-
-/* PCIE_0_INTR2 :: CPU_MASK_STATUS :: PCIE_MSTR_CA_ATTN [13:13] */
-#define BCHP_PCIE_0_INTR2_CPU_MASK_STATUS_PCIE_MSTR_CA_ATTN_MASK 0x00002000
-#define BCHP_PCIE_0_INTR2_CPU_MASK_STATUS_PCIE_MSTR_CA_ATTN_SHIFT 13
-#define BCHP_PCIE_0_INTR2_CPU_MASK_STATUS_PCIE_MSTR_CA_ATTN_DEFAULT 0x00000001
-
-/* PCIE_0_INTR2 :: CPU_MASK_STATUS :: PCIE_MSTR_UR_ATTN [12:12] */
-#define BCHP_PCIE_0_INTR2_CPU_MASK_STATUS_PCIE_MSTR_UR_ATTN_MASK 0x00001000
-#define BCHP_PCIE_0_INTR2_CPU_MASK_STATUS_PCIE_MSTR_UR_ATTN_SHIFT 12
-#define BCHP_PCIE_0_INTR2_CPU_MASK_STATUS_PCIE_MSTR_UR_ATTN_DEFAULT 0x00000001
-
-/* PCIE_0_INTR2 :: CPU_MASK_STATUS :: UNASSIGNED_11 [11:11] */
-#define BCHP_PCIE_0_INTR2_CPU_MASK_STATUS_UNASSIGNED_11_MASK 0x00000800
-#define BCHP_PCIE_0_INTR2_CPU_MASK_STATUS_UNASSIGNED_11_SHIFT 11
-#define BCHP_PCIE_0_INTR2_CPU_MASK_STATUS_UNASSIGNED_11_DEFAULT 0x00000001
-
-/* PCIE_0_INTR2 :: CPU_MASK_STATUS :: UNASSIGNED_10 [10:10] */
-#define BCHP_PCIE_0_INTR2_CPU_MASK_STATUS_UNASSIGNED_10_MASK 0x00000400
-#define BCHP_PCIE_0_INTR2_CPU_MASK_STATUS_UNASSIGNED_10_SHIFT 10
-#define BCHP_PCIE_0_INTR2_CPU_MASK_STATUS_UNASSIGNED_10_DEFAULT 0x00000001
-
-/* PCIE_0_INTR2 :: CPU_MASK_STATUS :: PCIE_TGT_BAD_ACCESS [09:09] */
-#define BCHP_PCIE_0_INTR2_CPU_MASK_STATUS_PCIE_TGT_BAD_ACCESS_MASK 0x00000200
-#define BCHP_PCIE_0_INTR2_CPU_MASK_STATUS_PCIE_TGT_BAD_ACCESS_SHIFT 9
-#define BCHP_PCIE_0_INTR2_CPU_MASK_STATUS_PCIE_TGT_BAD_ACCESS_DEFAULT 0x00000001
-
-/* PCIE_0_INTR2 :: CPU_MASK_STATUS :: PCIE_TGT_BAD_ADDRESS [08:08] */
-#define BCHP_PCIE_0_INTR2_CPU_MASK_STATUS_PCIE_TGT_BAD_ADDRESS_MASK 0x00000100
-#define BCHP_PCIE_0_INTR2_CPU_MASK_STATUS_PCIE_TGT_BAD_ADDRESS_SHIFT 8
-#define BCHP_PCIE_0_INTR2_CPU_MASK_STATUS_PCIE_TGT_BAD_ADDRESS_DEFAULT 0x00000001
-
-/* PCIE_0_INTR2 :: CPU_MASK_STATUS :: L1_RX_DMA_ERR_INTR [07:07] */
-#define BCHP_PCIE_0_INTR2_CPU_MASK_STATUS_L1_RX_DMA_ERR_INTR_MASK 0x00000080
-#define BCHP_PCIE_0_INTR2_CPU_MASK_STATUS_L1_RX_DMA_ERR_INTR_SHIFT 7
-#define BCHP_PCIE_0_INTR2_CPU_MASK_STATUS_L1_RX_DMA_ERR_INTR_DEFAULT 0x00000001
-
-/* PCIE_0_INTR2 :: CPU_MASK_STATUS :: L1_RX_DMA_DONE_INTR [06:06] */
-#define BCHP_PCIE_0_INTR2_CPU_MASK_STATUS_L1_RX_DMA_DONE_INTR_MASK 0x00000040
-#define BCHP_PCIE_0_INTR2_CPU_MASK_STATUS_L1_RX_DMA_DONE_INTR_SHIFT 6
-#define BCHP_PCIE_0_INTR2_CPU_MASK_STATUS_L1_RX_DMA_DONE_INTR_DEFAULT 0x00000001
-
-/* PCIE_0_INTR2 :: CPU_MASK_STATUS :: L1_TX_DMA_ERR_INTR [05:05] */
-#define BCHP_PCIE_0_INTR2_CPU_MASK_STATUS_L1_TX_DMA_ERR_INTR_MASK 0x00000020
-#define BCHP_PCIE_0_INTR2_CPU_MASK_STATUS_L1_TX_DMA_ERR_INTR_SHIFT 5
-#define BCHP_PCIE_0_INTR2_CPU_MASK_STATUS_L1_TX_DMA_ERR_INTR_DEFAULT 0x00000001
-
-/* PCIE_0_INTR2 :: CPU_MASK_STATUS :: L1_TX_DMA_DONE_INTR [04:04] */
-#define BCHP_PCIE_0_INTR2_CPU_MASK_STATUS_L1_TX_DMA_DONE_INTR_MASK 0x00000010
-#define BCHP_PCIE_0_INTR2_CPU_MASK_STATUS_L1_TX_DMA_DONE_INTR_SHIFT 4
-#define BCHP_PCIE_0_INTR2_CPU_MASK_STATUS_L1_TX_DMA_DONE_INTR_DEFAULT 0x00000001
-
-/* PCIE_0_INTR2 :: CPU_MASK_STATUS :: L0_RX_DMA_ERR_INTR [03:03] */
-#define BCHP_PCIE_0_INTR2_CPU_MASK_STATUS_L0_RX_DMA_ERR_INTR_MASK 0x00000008
-#define BCHP_PCIE_0_INTR2_CPU_MASK_STATUS_L0_RX_DMA_ERR_INTR_SHIFT 3
-#define BCHP_PCIE_0_INTR2_CPU_MASK_STATUS_L0_RX_DMA_ERR_INTR_DEFAULT 0x00000001
-
-/* PCIE_0_INTR2 :: CPU_MASK_STATUS :: L0_RX_DMA_DONE_INTR [02:02] */
-#define BCHP_PCIE_0_INTR2_CPU_MASK_STATUS_L0_RX_DMA_DONE_INTR_MASK 0x00000004
-#define BCHP_PCIE_0_INTR2_CPU_MASK_STATUS_L0_RX_DMA_DONE_INTR_SHIFT 2
-#define BCHP_PCIE_0_INTR2_CPU_MASK_STATUS_L0_RX_DMA_DONE_INTR_DEFAULT 0x00000001
-
-/* PCIE_0_INTR2 :: CPU_MASK_STATUS :: L0_TX_DMA_ERR_INTR [01:01] */
-#define BCHP_PCIE_0_INTR2_CPU_MASK_STATUS_L0_TX_DMA_ERR_INTR_MASK 0x00000002
-#define BCHP_PCIE_0_INTR2_CPU_MASK_STATUS_L0_TX_DMA_ERR_INTR_SHIFT 1
-#define BCHP_PCIE_0_INTR2_CPU_MASK_STATUS_L0_TX_DMA_ERR_INTR_DEFAULT 0x00000001
-
-/* PCIE_0_INTR2 :: CPU_MASK_STATUS :: L0_TX_DMA_DONE_INTR [00:00] */
-#define BCHP_PCIE_0_INTR2_CPU_MASK_STATUS_L0_TX_DMA_DONE_INTR_MASK 0x00000001
-#define BCHP_PCIE_0_INTR2_CPU_MASK_STATUS_L0_TX_DMA_DONE_INTR_SHIFT 0
-#define BCHP_PCIE_0_INTR2_CPU_MASK_STATUS_L0_TX_DMA_DONE_INTR_DEFAULT 0x00000001
-
-/***************************************************************************
- *CPU_MASK_SET - CPU interrupt Mask Set Register
- ***************************************************************************/
-/* PCIE_0_INTR2 :: CPU_MASK_SET :: MSI_INTR07 [31:31] */
-#define BCHP_PCIE_0_INTR2_CPU_MASK_SET_MSI_INTR07_MASK 0x80000000
-#define BCHP_PCIE_0_INTR2_CPU_MASK_SET_MSI_INTR07_SHIFT 31
-#define BCHP_PCIE_0_INTR2_CPU_MASK_SET_MSI_INTR07_DEFAULT 0x00000001
-
-/* PCIE_0_INTR2 :: CPU_MASK_SET :: MSI_INTR06 [30:30] */
-#define BCHP_PCIE_0_INTR2_CPU_MASK_SET_MSI_INTR06_MASK 0x40000000
-#define BCHP_PCIE_0_INTR2_CPU_MASK_SET_MSI_INTR06_SHIFT 30
-#define BCHP_PCIE_0_INTR2_CPU_MASK_SET_MSI_INTR06_DEFAULT 0x00000001
-
-/* PCIE_0_INTR2 :: CPU_MASK_SET :: MSI_INTR05 [29:29] */
-#define BCHP_PCIE_0_INTR2_CPU_MASK_SET_MSI_INTR05_MASK 0x20000000
-#define BCHP_PCIE_0_INTR2_CPU_MASK_SET_MSI_INTR05_SHIFT 29
-#define BCHP_PCIE_0_INTR2_CPU_MASK_SET_MSI_INTR05_DEFAULT 0x00000001
-
-/* PCIE_0_INTR2 :: CPU_MASK_SET :: MSI_INTR04 [28:28] */
-#define BCHP_PCIE_0_INTR2_CPU_MASK_SET_MSI_INTR04_MASK 0x10000000
-#define BCHP_PCIE_0_INTR2_CPU_MASK_SET_MSI_INTR04_SHIFT 28
-#define BCHP_PCIE_0_INTR2_CPU_MASK_SET_MSI_INTR04_DEFAULT 0x00000001
-
-/* PCIE_0_INTR2 :: CPU_MASK_SET :: MSI_INTR03 [27:27] */
-#define BCHP_PCIE_0_INTR2_CPU_MASK_SET_MSI_INTR03_MASK 0x08000000
-#define BCHP_PCIE_0_INTR2_CPU_MASK_SET_MSI_INTR03_SHIFT 27
-#define BCHP_PCIE_0_INTR2_CPU_MASK_SET_MSI_INTR03_DEFAULT 0x00000001
-
-/* PCIE_0_INTR2 :: CPU_MASK_SET :: MSI_INTR02 [26:26] */
-#define BCHP_PCIE_0_INTR2_CPU_MASK_SET_MSI_INTR02_MASK 0x04000000
-#define BCHP_PCIE_0_INTR2_CPU_MASK_SET_MSI_INTR02_SHIFT 26
-#define BCHP_PCIE_0_INTR2_CPU_MASK_SET_MSI_INTR02_DEFAULT 0x00000001
-
-/* PCIE_0_INTR2 :: CPU_MASK_SET :: MSI_INTR01 [25:25] */
-#define BCHP_PCIE_0_INTR2_CPU_MASK_SET_MSI_INTR01_MASK 0x02000000
-#define BCHP_PCIE_0_INTR2_CPU_MASK_SET_MSI_INTR01_SHIFT 25
-#define BCHP_PCIE_0_INTR2_CPU_MASK_SET_MSI_INTR01_DEFAULT 0x00000001
-
-/* PCIE_0_INTR2 :: CPU_MASK_SET :: MSI_INTR00 [24:24] */
-#define BCHP_PCIE_0_INTR2_CPU_MASK_SET_MSI_INTR00_MASK 0x01000000
-#define BCHP_PCIE_0_INTR2_CPU_MASK_SET_MSI_INTR00_SHIFT 24
-#define BCHP_PCIE_0_INTR2_CPU_MASK_SET_MSI_INTR00_DEFAULT 0x00000001
-
-/* PCIE_0_INTR2 :: CPU_MASK_SET :: UNASSIGNED_23 [23:23] */
-#define BCHP_PCIE_0_INTR2_CPU_MASK_SET_UNASSIGNED_23_MASK 0x00800000
-#define BCHP_PCIE_0_INTR2_CPU_MASK_SET_UNASSIGNED_23_SHIFT 23
-#define BCHP_PCIE_0_INTR2_CPU_MASK_SET_UNASSIGNED_23_DEFAULT 0x00000001
-
-/* PCIE_0_INTR2 :: CPU_MASK_SET :: UNASSIGNED_22 [22:22] */
-#define BCHP_PCIE_0_INTR2_CPU_MASK_SET_UNASSIGNED_22_MASK 0x00400000
-#define BCHP_PCIE_0_INTR2_CPU_MASK_SET_UNASSIGNED_22_SHIFT 22
-#define BCHP_PCIE_0_INTR2_CPU_MASK_SET_UNASSIGNED_22_DEFAULT 0x00000001
-
-/* PCIE_0_INTR2 :: CPU_MASK_SET :: UNASSIGNED_21 [21:21] */
-#define BCHP_PCIE_0_INTR2_CPU_MASK_SET_UNASSIGNED_21_MASK 0x00200000
-#define BCHP_PCIE_0_INTR2_CPU_MASK_SET_UNASSIGNED_21_SHIFT 21
-#define BCHP_PCIE_0_INTR2_CPU_MASK_SET_UNASSIGNED_21_DEFAULT 0x00000001
-
-/* PCIE_0_INTR2 :: CPU_MASK_SET :: UNASSIGNED_20 [20:20] */
-#define BCHP_PCIE_0_INTR2_CPU_MASK_SET_UNASSIGNED_20_MASK 0x00100000
-#define BCHP_PCIE_0_INTR2_CPU_MASK_SET_UNASSIGNED_20_SHIFT 20
-#define BCHP_PCIE_0_INTR2_CPU_MASK_SET_UNASSIGNED_20_DEFAULT 0x00000001
-
-/* PCIE_0_INTR2 :: CPU_MASK_SET :: MAILBOX_3 [19:19] */
-#define BCHP_PCIE_0_INTR2_CPU_MASK_SET_MAILBOX_3_MASK 0x00080000
-#define BCHP_PCIE_0_INTR2_CPU_MASK_SET_MAILBOX_3_SHIFT 19
-#define BCHP_PCIE_0_INTR2_CPU_MASK_SET_MAILBOX_3_DEFAULT 0x00000001
-
-/* PCIE_0_INTR2 :: CPU_MASK_SET :: MAILBOX_2 [18:18] */
-#define BCHP_PCIE_0_INTR2_CPU_MASK_SET_MAILBOX_2_MASK 0x00040000
-#define BCHP_PCIE_0_INTR2_CPU_MASK_SET_MAILBOX_2_SHIFT 18
-#define BCHP_PCIE_0_INTR2_CPU_MASK_SET_MAILBOX_2_DEFAULT 0x00000001
-
-/* PCIE_0_INTR2 :: CPU_MASK_SET :: MAILBOX_1 [17:17] */
-#define BCHP_PCIE_0_INTR2_CPU_MASK_SET_MAILBOX_1_MASK 0x00020000
-#define BCHP_PCIE_0_INTR2_CPU_MASK_SET_MAILBOX_1_SHIFT 17
-#define BCHP_PCIE_0_INTR2_CPU_MASK_SET_MAILBOX_1_DEFAULT 0x00000001
-
-/* PCIE_0_INTR2 :: CPU_MASK_SET :: MAILBOX_0 [16:16] */
-#define BCHP_PCIE_0_INTR2_CPU_MASK_SET_MAILBOX_0_MASK 0x00010000
-#define BCHP_PCIE_0_INTR2_CPU_MASK_SET_MAILBOX_0_SHIFT 16
-#define BCHP_PCIE_0_INTR2_CPU_MASK_SET_MAILBOX_0_DEFAULT 0x00000001
-
-/* PCIE_0_INTR2 :: CPU_MASK_SET :: PCIE_MSTR_FWD_ERR [15:15] */
-#define BCHP_PCIE_0_INTR2_CPU_MASK_SET_PCIE_MSTR_FWD_ERR_MASK 0x00008000
-#define BCHP_PCIE_0_INTR2_CPU_MASK_SET_PCIE_MSTR_FWD_ERR_SHIFT 15
-#define BCHP_PCIE_0_INTR2_CPU_MASK_SET_PCIE_MSTR_FWD_ERR_DEFAULT 0x00000001
-
-/* PCIE_0_INTR2 :: CPU_MASK_SET :: PCIE_MSTR_RETRY_TIMEOUT [14:14] */
-#define BCHP_PCIE_0_INTR2_CPU_MASK_SET_PCIE_MSTR_RETRY_TIMEOUT_MASK 0x00004000
-#define BCHP_PCIE_0_INTR2_CPU_MASK_SET_PCIE_MSTR_RETRY_TIMEOUT_SHIFT 14
-#define BCHP_PCIE_0_INTR2_CPU_MASK_SET_PCIE_MSTR_RETRY_TIMEOUT_DEFAULT 0x00000001
-
-/* PCIE_0_INTR2 :: CPU_MASK_SET :: PCIE_MSTR_CA_ATTN [13:13] */
-#define BCHP_PCIE_0_INTR2_CPU_MASK_SET_PCIE_MSTR_CA_ATTN_MASK 0x00002000
-#define BCHP_PCIE_0_INTR2_CPU_MASK_SET_PCIE_MSTR_CA_ATTN_SHIFT 13
-#define BCHP_PCIE_0_INTR2_CPU_MASK_SET_PCIE_MSTR_CA_ATTN_DEFAULT 0x00000001
-
-/* PCIE_0_INTR2 :: CPU_MASK_SET :: PCIE_MSTR_UR_ATTN [12:12] */
-#define BCHP_PCIE_0_INTR2_CPU_MASK_SET_PCIE_MSTR_UR_ATTN_MASK 0x00001000
-#define BCHP_PCIE_0_INTR2_CPU_MASK_SET_PCIE_MSTR_UR_ATTN_SHIFT 12
-#define BCHP_PCIE_0_INTR2_CPU_MASK_SET_PCIE_MSTR_UR_ATTN_DEFAULT 0x00000001
-
-/* PCIE_0_INTR2 :: CPU_MASK_SET :: UNASSIGNED_11 [11:11] */
-#define BCHP_PCIE_0_INTR2_CPU_MASK_SET_UNASSIGNED_11_MASK 0x00000800
-#define BCHP_PCIE_0_INTR2_CPU_MASK_SET_UNASSIGNED_11_SHIFT 11
-#define BCHP_PCIE_0_INTR2_CPU_MASK_SET_UNASSIGNED_11_DEFAULT 0x00000001
-
-/* PCIE_0_INTR2 :: CPU_MASK_SET :: UNASSIGNED_10 [10:10] */
-#define BCHP_PCIE_0_INTR2_CPU_MASK_SET_UNASSIGNED_10_MASK 0x00000400
-#define BCHP_PCIE_0_INTR2_CPU_MASK_SET_UNASSIGNED_10_SHIFT 10
-#define BCHP_PCIE_0_INTR2_CPU_MASK_SET_UNASSIGNED_10_DEFAULT 0x00000001
-
-/* PCIE_0_INTR2 :: CPU_MASK_SET :: PCIE_TGT_BAD_ACCESS [09:09] */
-#define BCHP_PCIE_0_INTR2_CPU_MASK_SET_PCIE_TGT_BAD_ACCESS_MASK 0x00000200
-#define BCHP_PCIE_0_INTR2_CPU_MASK_SET_PCIE_TGT_BAD_ACCESS_SHIFT 9
-#define BCHP_PCIE_0_INTR2_CPU_MASK_SET_PCIE_TGT_BAD_ACCESS_DEFAULT 0x00000001
-
-/* PCIE_0_INTR2 :: CPU_MASK_SET :: PCIE_TGT_BAD_ADDRESS [08:08] */
-#define BCHP_PCIE_0_INTR2_CPU_MASK_SET_PCIE_TGT_BAD_ADDRESS_MASK 0x00000100
-#define BCHP_PCIE_0_INTR2_CPU_MASK_SET_PCIE_TGT_BAD_ADDRESS_SHIFT 8
-#define BCHP_PCIE_0_INTR2_CPU_MASK_SET_PCIE_TGT_BAD_ADDRESS_DEFAULT 0x00000001
-
-/* PCIE_0_INTR2 :: CPU_MASK_SET :: L1_RX_DMA_ERR_INTR [07:07] */
-#define BCHP_PCIE_0_INTR2_CPU_MASK_SET_L1_RX_DMA_ERR_INTR_MASK 0x00000080
-#define BCHP_PCIE_0_INTR2_CPU_MASK_SET_L1_RX_DMA_ERR_INTR_SHIFT 7
-#define BCHP_PCIE_0_INTR2_CPU_MASK_SET_L1_RX_DMA_ERR_INTR_DEFAULT 0x00000001
-
-/* PCIE_0_INTR2 :: CPU_MASK_SET :: L1_RX_DMA_DONE_INTR [06:06] */
-#define BCHP_PCIE_0_INTR2_CPU_MASK_SET_L1_RX_DMA_DONE_INTR_MASK 0x00000040
-#define BCHP_PCIE_0_INTR2_CPU_MASK_SET_L1_RX_DMA_DONE_INTR_SHIFT 6
-#define BCHP_PCIE_0_INTR2_CPU_MASK_SET_L1_RX_DMA_DONE_INTR_DEFAULT 0x00000001
-
-/* PCIE_0_INTR2 :: CPU_MASK_SET :: L1_TX_DMA_ERR_INTR [05:05] */
-#define BCHP_PCIE_0_INTR2_CPU_MASK_SET_L1_TX_DMA_ERR_INTR_MASK 0x00000020
-#define BCHP_PCIE_0_INTR2_CPU_MASK_SET_L1_TX_DMA_ERR_INTR_SHIFT 5
-#define BCHP_PCIE_0_INTR2_CPU_MASK_SET_L1_TX_DMA_ERR_INTR_DEFAULT 0x00000001
-
-/* PCIE_0_INTR2 :: CPU_MASK_SET :: L1_TX_DMA_DONE_INTR [04:04] */
-#define BCHP_PCIE_0_INTR2_CPU_MASK_SET_L1_TX_DMA_DONE_INTR_MASK 0x00000010
-#define BCHP_PCIE_0_INTR2_CPU_MASK_SET_L1_TX_DMA_DONE_INTR_SHIFT 4
-#define BCHP_PCIE_0_INTR2_CPU_MASK_SET_L1_TX_DMA_DONE_INTR_DEFAULT 0x00000001
-
-/* PCIE_0_INTR2 :: CPU_MASK_SET :: L0_RX_DMA_ERR_INTR [03:03] */
-#define BCHP_PCIE_0_INTR2_CPU_MASK_SET_L0_RX_DMA_ERR_INTR_MASK 0x00000008
-#define BCHP_PCIE_0_INTR2_CPU_MASK_SET_L0_RX_DMA_ERR_INTR_SHIFT 3
-#define BCHP_PCIE_0_INTR2_CPU_MASK_SET_L0_RX_DMA_ERR_INTR_DEFAULT 0x00000001
-
-/* PCIE_0_INTR2 :: CPU_MASK_SET :: L0_RX_DMA_DONE_INTR [02:02] */
-#define BCHP_PCIE_0_INTR2_CPU_MASK_SET_L0_RX_DMA_DONE_INTR_MASK 0x00000004
-#define BCHP_PCIE_0_INTR2_CPU_MASK_SET_L0_RX_DMA_DONE_INTR_SHIFT 2
-#define BCHP_PCIE_0_INTR2_CPU_MASK_SET_L0_RX_DMA_DONE_INTR_DEFAULT 0x00000001
-
-/* PCIE_0_INTR2 :: CPU_MASK_SET :: L0_TX_DMA_ERR_INTR [01:01] */
-#define BCHP_PCIE_0_INTR2_CPU_MASK_SET_L0_TX_DMA_ERR_INTR_MASK 0x00000002
-#define BCHP_PCIE_0_INTR2_CPU_MASK_SET_L0_TX_DMA_ERR_INTR_SHIFT 1
-#define BCHP_PCIE_0_INTR2_CPU_MASK_SET_L0_TX_DMA_ERR_INTR_DEFAULT 0x00000001
-
-/* PCIE_0_INTR2 :: CPU_MASK_SET :: L0_TX_DMA_DONE_INTR [00:00] */
-#define BCHP_PCIE_0_INTR2_CPU_MASK_SET_L0_TX_DMA_DONE_INTR_MASK 0x00000001
-#define BCHP_PCIE_0_INTR2_CPU_MASK_SET_L0_TX_DMA_DONE_INTR_SHIFT 0
-#define BCHP_PCIE_0_INTR2_CPU_MASK_SET_L0_TX_DMA_DONE_INTR_DEFAULT 0x00000001
-
-/***************************************************************************
- *CPU_MASK_CLEAR - CPU interrupt Mask Clear Register
- ***************************************************************************/
-/* PCIE_0_INTR2 :: CPU_MASK_CLEAR :: MSI_INTR07 [31:31] */
-#define BCHP_PCIE_0_INTR2_CPU_MASK_CLEAR_MSI_INTR07_MASK 0x80000000
-#define BCHP_PCIE_0_INTR2_CPU_MASK_CLEAR_MSI_INTR07_SHIFT 31
-#define BCHP_PCIE_0_INTR2_CPU_MASK_CLEAR_MSI_INTR07_DEFAULT 0x00000001
-
-/* PCIE_0_INTR2 :: CPU_MASK_CLEAR :: MSI_INTR06 [30:30] */
-#define BCHP_PCIE_0_INTR2_CPU_MASK_CLEAR_MSI_INTR06_MASK 0x40000000
-#define BCHP_PCIE_0_INTR2_CPU_MASK_CLEAR_MSI_INTR06_SHIFT 30
-#define BCHP_PCIE_0_INTR2_CPU_MASK_CLEAR_MSI_INTR06_DEFAULT 0x00000001
-
-/* PCIE_0_INTR2 :: CPU_MASK_CLEAR :: MSI_INTR05 [29:29] */
-#define BCHP_PCIE_0_INTR2_CPU_MASK_CLEAR_MSI_INTR05_MASK 0x20000000
-#define BCHP_PCIE_0_INTR2_CPU_MASK_CLEAR_MSI_INTR05_SHIFT 29
-#define BCHP_PCIE_0_INTR2_CPU_MASK_CLEAR_MSI_INTR05_DEFAULT 0x00000001
-
-/* PCIE_0_INTR2 :: CPU_MASK_CLEAR :: MSI_INTR04 [28:28] */
-#define BCHP_PCIE_0_INTR2_CPU_MASK_CLEAR_MSI_INTR04_MASK 0x10000000
-#define BCHP_PCIE_0_INTR2_CPU_MASK_CLEAR_MSI_INTR04_SHIFT 28
-#define BCHP_PCIE_0_INTR2_CPU_MASK_CLEAR_MSI_INTR04_DEFAULT 0x00000001
-
-/* PCIE_0_INTR2 :: CPU_MASK_CLEAR :: MSI_INTR03 [27:27] */
-#define BCHP_PCIE_0_INTR2_CPU_MASK_CLEAR_MSI_INTR03_MASK 0x08000000
-#define BCHP_PCIE_0_INTR2_CPU_MASK_CLEAR_MSI_INTR03_SHIFT 27
-#define BCHP_PCIE_0_INTR2_CPU_MASK_CLEAR_MSI_INTR03_DEFAULT 0x00000001
-
-/* PCIE_0_INTR2 :: CPU_MASK_CLEAR :: MSI_INTR02 [26:26] */
-#define BCHP_PCIE_0_INTR2_CPU_MASK_CLEAR_MSI_INTR02_MASK 0x04000000
-#define BCHP_PCIE_0_INTR2_CPU_MASK_CLEAR_MSI_INTR02_SHIFT 26
-#define BCHP_PCIE_0_INTR2_CPU_MASK_CLEAR_MSI_INTR02_DEFAULT 0x00000001
-
-/* PCIE_0_INTR2 :: CPU_MASK_CLEAR :: MSI_INTR01 [25:25] */
-#define BCHP_PCIE_0_INTR2_CPU_MASK_CLEAR_MSI_INTR01_MASK 0x02000000
-#define BCHP_PCIE_0_INTR2_CPU_MASK_CLEAR_MSI_INTR01_SHIFT 25
-#define BCHP_PCIE_0_INTR2_CPU_MASK_CLEAR_MSI_INTR01_DEFAULT 0x00000001
-
-/* PCIE_0_INTR2 :: CPU_MASK_CLEAR :: MSI_INTR00 [24:24] */
-#define BCHP_PCIE_0_INTR2_CPU_MASK_CLEAR_MSI_INTR00_MASK 0x01000000
-#define BCHP_PCIE_0_INTR2_CPU_MASK_CLEAR_MSI_INTR00_SHIFT 24
-#define BCHP_PCIE_0_INTR2_CPU_MASK_CLEAR_MSI_INTR00_DEFAULT 0x00000001
-
-/* PCIE_0_INTR2 :: CPU_MASK_CLEAR :: UNASSIGNED_23 [23:23] */
-#define BCHP_PCIE_0_INTR2_CPU_MASK_CLEAR_UNASSIGNED_23_MASK 0x00800000
-#define BCHP_PCIE_0_INTR2_CPU_MASK_CLEAR_UNASSIGNED_23_SHIFT 23
-#define BCHP_PCIE_0_INTR2_CPU_MASK_CLEAR_UNASSIGNED_23_DEFAULT 0x00000001
-
-/* PCIE_0_INTR2 :: CPU_MASK_CLEAR :: UNASSIGNED_22 [22:22] */
-#define BCHP_PCIE_0_INTR2_CPU_MASK_CLEAR_UNASSIGNED_22_MASK 0x00400000
-#define BCHP_PCIE_0_INTR2_CPU_MASK_CLEAR_UNASSIGNED_22_SHIFT 22
-#define BCHP_PCIE_0_INTR2_CPU_MASK_CLEAR_UNASSIGNED_22_DEFAULT 0x00000001
-
-/* PCIE_0_INTR2 :: CPU_MASK_CLEAR :: UNASSIGNED_21 [21:21] */
-#define BCHP_PCIE_0_INTR2_CPU_MASK_CLEAR_UNASSIGNED_21_MASK 0x00200000
-#define BCHP_PCIE_0_INTR2_CPU_MASK_CLEAR_UNASSIGNED_21_SHIFT 21
-#define BCHP_PCIE_0_INTR2_CPU_MASK_CLEAR_UNASSIGNED_21_DEFAULT 0x00000001
-
-/* PCIE_0_INTR2 :: CPU_MASK_CLEAR :: UNASSIGNED_20 [20:20] */
-#define BCHP_PCIE_0_INTR2_CPU_MASK_CLEAR_UNASSIGNED_20_MASK 0x00100000
-#define BCHP_PCIE_0_INTR2_CPU_MASK_CLEAR_UNASSIGNED_20_SHIFT 20
-#define BCHP_PCIE_0_INTR2_CPU_MASK_CLEAR_UNASSIGNED_20_DEFAULT 0x00000001
-
-/* PCIE_0_INTR2 :: CPU_MASK_CLEAR :: MAILBOX_3 [19:19] */
-#define BCHP_PCIE_0_INTR2_CPU_MASK_CLEAR_MAILBOX_3_MASK 0x00080000
-#define BCHP_PCIE_0_INTR2_CPU_MASK_CLEAR_MAILBOX_3_SHIFT 19
-#define BCHP_PCIE_0_INTR2_CPU_MASK_CLEAR_MAILBOX_3_DEFAULT 0x00000001
-
-/* PCIE_0_INTR2 :: CPU_MASK_CLEAR :: MAILBOX_2 [18:18] */
-#define BCHP_PCIE_0_INTR2_CPU_MASK_CLEAR_MAILBOX_2_MASK 0x00040000
-#define BCHP_PCIE_0_INTR2_CPU_MASK_CLEAR_MAILBOX_2_SHIFT 18
-#define BCHP_PCIE_0_INTR2_CPU_MASK_CLEAR_MAILBOX_2_DEFAULT 0x00000001
-
-/* PCIE_0_INTR2 :: CPU_MASK_CLEAR :: MAILBOX_1 [17:17] */
-#define BCHP_PCIE_0_INTR2_CPU_MASK_CLEAR_MAILBOX_1_MASK 0x00020000
-#define BCHP_PCIE_0_INTR2_CPU_MASK_CLEAR_MAILBOX_1_SHIFT 17
-#define BCHP_PCIE_0_INTR2_CPU_MASK_CLEAR_MAILBOX_1_DEFAULT 0x00000001
-
-/* PCIE_0_INTR2 :: CPU_MASK_CLEAR :: MAILBOX_0 [16:16] */
-#define BCHP_PCIE_0_INTR2_CPU_MASK_CLEAR_MAILBOX_0_MASK 0x00010000
-#define BCHP_PCIE_0_INTR2_CPU_MASK_CLEAR_MAILBOX_0_SHIFT 16
-#define BCHP_PCIE_0_INTR2_CPU_MASK_CLEAR_MAILBOX_0_DEFAULT 0x00000001
-
-/* PCIE_0_INTR2 :: CPU_MASK_CLEAR :: PCIE_MSTR_FWD_ERR [15:15] */
-#define BCHP_PCIE_0_INTR2_CPU_MASK_CLEAR_PCIE_MSTR_FWD_ERR_MASK 0x00008000
-#define BCHP_PCIE_0_INTR2_CPU_MASK_CLEAR_PCIE_MSTR_FWD_ERR_SHIFT 15
-#define BCHP_PCIE_0_INTR2_CPU_MASK_CLEAR_PCIE_MSTR_FWD_ERR_DEFAULT 0x00000001
-
-/* PCIE_0_INTR2 :: CPU_MASK_CLEAR :: PCIE_MSTR_RETRY_TIMEOUT [14:14] */
-#define BCHP_PCIE_0_INTR2_CPU_MASK_CLEAR_PCIE_MSTR_RETRY_TIMEOUT_MASK 0x00004000
-#define BCHP_PCIE_0_INTR2_CPU_MASK_CLEAR_PCIE_MSTR_RETRY_TIMEOUT_SHIFT 14
-#define BCHP_PCIE_0_INTR2_CPU_MASK_CLEAR_PCIE_MSTR_RETRY_TIMEOUT_DEFAULT 0x00000001
-
-/* PCIE_0_INTR2 :: CPU_MASK_CLEAR :: PCIE_MSTR_CA_ATTN [13:13] */
-#define BCHP_PCIE_0_INTR2_CPU_MASK_CLEAR_PCIE_MSTR_CA_ATTN_MASK 0x00002000
-#define BCHP_PCIE_0_INTR2_CPU_MASK_CLEAR_PCIE_MSTR_CA_ATTN_SHIFT 13
-#define BCHP_PCIE_0_INTR2_CPU_MASK_CLEAR_PCIE_MSTR_CA_ATTN_DEFAULT 0x00000001
-
-/* PCIE_0_INTR2 :: CPU_MASK_CLEAR :: PCIE_MSTR_UR_ATTN [12:12] */
-#define BCHP_PCIE_0_INTR2_CPU_MASK_CLEAR_PCIE_MSTR_UR_ATTN_MASK 0x00001000
-#define BCHP_PCIE_0_INTR2_CPU_MASK_CLEAR_PCIE_MSTR_UR_ATTN_SHIFT 12
-#define BCHP_PCIE_0_INTR2_CPU_MASK_CLEAR_PCIE_MSTR_UR_ATTN_DEFAULT 0x00000001
-
-/* PCIE_0_INTR2 :: CPU_MASK_CLEAR :: UNASSIGNED_11 [11:11] */
-#define BCHP_PCIE_0_INTR2_CPU_MASK_CLEAR_UNASSIGNED_11_MASK 0x00000800
-#define BCHP_PCIE_0_INTR2_CPU_MASK_CLEAR_UNASSIGNED_11_SHIFT 11
-#define BCHP_PCIE_0_INTR2_CPU_MASK_CLEAR_UNASSIGNED_11_DEFAULT 0x00000001
-
-/* PCIE_0_INTR2 :: CPU_MASK_CLEAR :: UNASSIGNED_10 [10:10] */
-#define BCHP_PCIE_0_INTR2_CPU_MASK_CLEAR_UNASSIGNED_10_MASK 0x00000400
-#define BCHP_PCIE_0_INTR2_CPU_MASK_CLEAR_UNASSIGNED_10_SHIFT 10
-#define BCHP_PCIE_0_INTR2_CPU_MASK_CLEAR_UNASSIGNED_10_DEFAULT 0x00000001
-
-/* PCIE_0_INTR2 :: CPU_MASK_CLEAR :: PCIE_TGT_BAD_ACCESS [09:09] */
-#define BCHP_PCIE_0_INTR2_CPU_MASK_CLEAR_PCIE_TGT_BAD_ACCESS_MASK 0x00000200
-#define BCHP_PCIE_0_INTR2_CPU_MASK_CLEAR_PCIE_TGT_BAD_ACCESS_SHIFT 9
-#define BCHP_PCIE_0_INTR2_CPU_MASK_CLEAR_PCIE_TGT_BAD_ACCESS_DEFAULT 0x00000001
-
-/* PCIE_0_INTR2 :: CPU_MASK_CLEAR :: PCIE_TGT_BAD_ADDRESS [08:08] */
-#define BCHP_PCIE_0_INTR2_CPU_MASK_CLEAR_PCIE_TGT_BAD_ADDRESS_MASK 0x00000100
-#define BCHP_PCIE_0_INTR2_CPU_MASK_CLEAR_PCIE_TGT_BAD_ADDRESS_SHIFT 8
-#define BCHP_PCIE_0_INTR2_CPU_MASK_CLEAR_PCIE_TGT_BAD_ADDRESS_DEFAULT 0x00000001
-
-/* PCIE_0_INTR2 :: CPU_MASK_CLEAR :: L1_RX_DMA_ERR_INTR [07:07] */
-#define BCHP_PCIE_0_INTR2_CPU_MASK_CLEAR_L1_RX_DMA_ERR_INTR_MASK 0x00000080
-#define BCHP_PCIE_0_INTR2_CPU_MASK_CLEAR_L1_RX_DMA_ERR_INTR_SHIFT 7
-#define BCHP_PCIE_0_INTR2_CPU_MASK_CLEAR_L1_RX_DMA_ERR_INTR_DEFAULT 0x00000001
-
-/* PCIE_0_INTR2 :: CPU_MASK_CLEAR :: L1_RX_DMA_DONE_INTR [06:06] */
-#define BCHP_PCIE_0_INTR2_CPU_MASK_CLEAR_L1_RX_DMA_DONE_INTR_MASK 0x00000040
-#define BCHP_PCIE_0_INTR2_CPU_MASK_CLEAR_L1_RX_DMA_DONE_INTR_SHIFT 6
-#define BCHP_PCIE_0_INTR2_CPU_MASK_CLEAR_L1_RX_DMA_DONE_INTR_DEFAULT 0x00000001
-
-/* PCIE_0_INTR2 :: CPU_MASK_CLEAR :: L1_TX_DMA_ERR_INTR [05:05] */
-#define BCHP_PCIE_0_INTR2_CPU_MASK_CLEAR_L1_TX_DMA_ERR_INTR_MASK 0x00000020
-#define BCHP_PCIE_0_INTR2_CPU_MASK_CLEAR_L1_TX_DMA_ERR_INTR_SHIFT 5
-#define BCHP_PCIE_0_INTR2_CPU_MASK_CLEAR_L1_TX_DMA_ERR_INTR_DEFAULT 0x00000001
-
-/* PCIE_0_INTR2 :: CPU_MASK_CLEAR :: L1_TX_DMA_DONE_INTR [04:04] */
-#define BCHP_PCIE_0_INTR2_CPU_MASK_CLEAR_L1_TX_DMA_DONE_INTR_MASK 0x00000010
-#define BCHP_PCIE_0_INTR2_CPU_MASK_CLEAR_L1_TX_DMA_DONE_INTR_SHIFT 4
-#define BCHP_PCIE_0_INTR2_CPU_MASK_CLEAR_L1_TX_DMA_DONE_INTR_DEFAULT 0x00000001
-
-/* PCIE_0_INTR2 :: CPU_MASK_CLEAR :: L0_RX_DMA_ERR_INTR [03:03] */
-#define BCHP_PCIE_0_INTR2_CPU_MASK_CLEAR_L0_RX_DMA_ERR_INTR_MASK 0x00000008
-#define BCHP_PCIE_0_INTR2_CPU_MASK_CLEAR_L0_RX_DMA_ERR_INTR_SHIFT 3
-#define BCHP_PCIE_0_INTR2_CPU_MASK_CLEAR_L0_RX_DMA_ERR_INTR_DEFAULT 0x00000001
-
-/* PCIE_0_INTR2 :: CPU_MASK_CLEAR :: L0_RX_DMA_DONE_INTR [02:02] */
-#define BCHP_PCIE_0_INTR2_CPU_MASK_CLEAR_L0_RX_DMA_DONE_INTR_MASK 0x00000004
-#define BCHP_PCIE_0_INTR2_CPU_MASK_CLEAR_L0_RX_DMA_DONE_INTR_SHIFT 2
-#define BCHP_PCIE_0_INTR2_CPU_MASK_CLEAR_L0_RX_DMA_DONE_INTR_DEFAULT 0x00000001
-
-/* PCIE_0_INTR2 :: CPU_MASK_CLEAR :: L0_TX_DMA_ERR_INTR [01:01] */
-#define BCHP_PCIE_0_INTR2_CPU_MASK_CLEAR_L0_TX_DMA_ERR_INTR_MASK 0x00000002
-#define BCHP_PCIE_0_INTR2_CPU_MASK_CLEAR_L0_TX_DMA_ERR_INTR_SHIFT 1
-#define BCHP_PCIE_0_INTR2_CPU_MASK_CLEAR_L0_TX_DMA_ERR_INTR_DEFAULT 0x00000001
-
-/* PCIE_0_INTR2 :: CPU_MASK_CLEAR :: L0_TX_DMA_DONE_INTR [00:00] */
-#define BCHP_PCIE_0_INTR2_CPU_MASK_CLEAR_L0_TX_DMA_DONE_INTR_MASK 0x00000001
-#define BCHP_PCIE_0_INTR2_CPU_MASK_CLEAR_L0_TX_DMA_DONE_INTR_SHIFT 0
-#define BCHP_PCIE_0_INTR2_CPU_MASK_CLEAR_L0_TX_DMA_DONE_INTR_DEFAULT 0x00000001
-
-/***************************************************************************
- *PCI_STATUS - PCI interrupt Status Register
- ***************************************************************************/
-/* PCIE_0_INTR2 :: PCI_STATUS :: MSI_INTR07 [31:31] */
-#define BCHP_PCIE_0_INTR2_PCI_STATUS_MSI_INTR07_MASK 0x80000000
-#define BCHP_PCIE_0_INTR2_PCI_STATUS_MSI_INTR07_SHIFT 31
-#define BCHP_PCIE_0_INTR2_PCI_STATUS_MSI_INTR07_DEFAULT 0x00000000
-
-/* PCIE_0_INTR2 :: PCI_STATUS :: MSI_INTR06 [30:30] */
-#define BCHP_PCIE_0_INTR2_PCI_STATUS_MSI_INTR06_MASK 0x40000000
-#define BCHP_PCIE_0_INTR2_PCI_STATUS_MSI_INTR06_SHIFT 30
-#define BCHP_PCIE_0_INTR2_PCI_STATUS_MSI_INTR06_DEFAULT 0x00000000
-
-/* PCIE_0_INTR2 :: PCI_STATUS :: MSI_INTR05 [29:29] */
-#define BCHP_PCIE_0_INTR2_PCI_STATUS_MSI_INTR05_MASK 0x20000000
-#define BCHP_PCIE_0_INTR2_PCI_STATUS_MSI_INTR05_SHIFT 29
-#define BCHP_PCIE_0_INTR2_PCI_STATUS_MSI_INTR05_DEFAULT 0x00000000
-
-/* PCIE_0_INTR2 :: PCI_STATUS :: MSI_INTR04 [28:28] */
-#define BCHP_PCIE_0_INTR2_PCI_STATUS_MSI_INTR04_MASK 0x10000000
-#define BCHP_PCIE_0_INTR2_PCI_STATUS_MSI_INTR04_SHIFT 28
-#define BCHP_PCIE_0_INTR2_PCI_STATUS_MSI_INTR04_DEFAULT 0x00000000
-
-/* PCIE_0_INTR2 :: PCI_STATUS :: MSI_INTR03 [27:27] */
-#define BCHP_PCIE_0_INTR2_PCI_STATUS_MSI_INTR03_MASK 0x08000000
-#define BCHP_PCIE_0_INTR2_PCI_STATUS_MSI_INTR03_SHIFT 27
-#define BCHP_PCIE_0_INTR2_PCI_STATUS_MSI_INTR03_DEFAULT 0x00000000
-
-/* PCIE_0_INTR2 :: PCI_STATUS :: MSI_INTR02 [26:26] */
-#define BCHP_PCIE_0_INTR2_PCI_STATUS_MSI_INTR02_MASK 0x04000000
-#define BCHP_PCIE_0_INTR2_PCI_STATUS_MSI_INTR02_SHIFT 26
-#define BCHP_PCIE_0_INTR2_PCI_STATUS_MSI_INTR02_DEFAULT 0x00000000
-
-/* PCIE_0_INTR2 :: PCI_STATUS :: MSI_INTR01 [25:25] */
-#define BCHP_PCIE_0_INTR2_PCI_STATUS_MSI_INTR01_MASK 0x02000000
-#define BCHP_PCIE_0_INTR2_PCI_STATUS_MSI_INTR01_SHIFT 25
-#define BCHP_PCIE_0_INTR2_PCI_STATUS_MSI_INTR01_DEFAULT 0x00000000
-
-/* PCIE_0_INTR2 :: PCI_STATUS :: MSI_INTR00 [24:24] */
-#define BCHP_PCIE_0_INTR2_PCI_STATUS_MSI_INTR00_MASK 0x01000000
-#define BCHP_PCIE_0_INTR2_PCI_STATUS_MSI_INTR00_SHIFT 24
-#define BCHP_PCIE_0_INTR2_PCI_STATUS_MSI_INTR00_DEFAULT 0x00000000
-
-/* PCIE_0_INTR2 :: PCI_STATUS :: UNASSIGNED_23 [23:23] */
-#define BCHP_PCIE_0_INTR2_PCI_STATUS_UNASSIGNED_23_MASK 0x00800000
-#define BCHP_PCIE_0_INTR2_PCI_STATUS_UNASSIGNED_23_SHIFT 23
-#define BCHP_PCIE_0_INTR2_PCI_STATUS_UNASSIGNED_23_DEFAULT 0x00000000
-
-/* PCIE_0_INTR2 :: PCI_STATUS :: UNASSIGNED_22 [22:22] */
-#define BCHP_PCIE_0_INTR2_PCI_STATUS_UNASSIGNED_22_MASK 0x00400000
-#define BCHP_PCIE_0_INTR2_PCI_STATUS_UNASSIGNED_22_SHIFT 22
-#define BCHP_PCIE_0_INTR2_PCI_STATUS_UNASSIGNED_22_DEFAULT 0x00000000
-
-/* PCIE_0_INTR2 :: PCI_STATUS :: UNASSIGNED_21 [21:21] */
-#define BCHP_PCIE_0_INTR2_PCI_STATUS_UNASSIGNED_21_MASK 0x00200000
-#define BCHP_PCIE_0_INTR2_PCI_STATUS_UNASSIGNED_21_SHIFT 21
-#define BCHP_PCIE_0_INTR2_PCI_STATUS_UNASSIGNED_21_DEFAULT 0x00000000
-
-/* PCIE_0_INTR2 :: PCI_STATUS :: UNASSIGNED_20 [20:20] */
-#define BCHP_PCIE_0_INTR2_PCI_STATUS_UNASSIGNED_20_MASK 0x00100000
-#define BCHP_PCIE_0_INTR2_PCI_STATUS_UNASSIGNED_20_SHIFT 20
-#define BCHP_PCIE_0_INTR2_PCI_STATUS_UNASSIGNED_20_DEFAULT 0x00000000
-
-/* PCIE_0_INTR2 :: PCI_STATUS :: MAILBOX_3 [19:19] */
-#define BCHP_PCIE_0_INTR2_PCI_STATUS_MAILBOX_3_MASK 0x00080000
-#define BCHP_PCIE_0_INTR2_PCI_STATUS_MAILBOX_3_SHIFT 19
-#define BCHP_PCIE_0_INTR2_PCI_STATUS_MAILBOX_3_DEFAULT 0x00000000
-
-/* PCIE_0_INTR2 :: PCI_STATUS :: MAILBOX_2 [18:18] */
-#define BCHP_PCIE_0_INTR2_PCI_STATUS_MAILBOX_2_MASK 0x00040000
-#define BCHP_PCIE_0_INTR2_PCI_STATUS_MAILBOX_2_SHIFT 18
-#define BCHP_PCIE_0_INTR2_PCI_STATUS_MAILBOX_2_DEFAULT 0x00000000
-
-/* PCIE_0_INTR2 :: PCI_STATUS :: MAILBOX_1 [17:17] */
-#define BCHP_PCIE_0_INTR2_PCI_STATUS_MAILBOX_1_MASK 0x00020000
-#define BCHP_PCIE_0_INTR2_PCI_STATUS_MAILBOX_1_SHIFT 17
-#define BCHP_PCIE_0_INTR2_PCI_STATUS_MAILBOX_1_DEFAULT 0x00000000
-
-/* PCIE_0_INTR2 :: PCI_STATUS :: MAILBOX_0 [16:16] */
-#define BCHP_PCIE_0_INTR2_PCI_STATUS_MAILBOX_0_MASK 0x00010000
-#define BCHP_PCIE_0_INTR2_PCI_STATUS_MAILBOX_0_SHIFT 16
-#define BCHP_PCIE_0_INTR2_PCI_STATUS_MAILBOX_0_DEFAULT 0x00000000
-
-/* PCIE_0_INTR2 :: PCI_STATUS :: PCIE_MSTR_FWD_ERR [15:15] */
-#define BCHP_PCIE_0_INTR2_PCI_STATUS_PCIE_MSTR_FWD_ERR_MASK 0x00008000
-#define BCHP_PCIE_0_INTR2_PCI_STATUS_PCIE_MSTR_FWD_ERR_SHIFT 15
-#define BCHP_PCIE_0_INTR2_PCI_STATUS_PCIE_MSTR_FWD_ERR_DEFAULT 0x00000000
-
-/* PCIE_0_INTR2 :: PCI_STATUS :: PCIE_MSTR_RETRY_TIMEOUT [14:14] */
-#define BCHP_PCIE_0_INTR2_PCI_STATUS_PCIE_MSTR_RETRY_TIMEOUT_MASK 0x00004000
-#define BCHP_PCIE_0_INTR2_PCI_STATUS_PCIE_MSTR_RETRY_TIMEOUT_SHIFT 14
-#define BCHP_PCIE_0_INTR2_PCI_STATUS_PCIE_MSTR_RETRY_TIMEOUT_DEFAULT 0x00000000
-
-/* PCIE_0_INTR2 :: PCI_STATUS :: PCIE_MSTR_CA_ATTN [13:13] */
-#define BCHP_PCIE_0_INTR2_PCI_STATUS_PCIE_MSTR_CA_ATTN_MASK 0x00002000
-#define BCHP_PCIE_0_INTR2_PCI_STATUS_PCIE_MSTR_CA_ATTN_SHIFT 13
-#define BCHP_PCIE_0_INTR2_PCI_STATUS_PCIE_MSTR_CA_ATTN_DEFAULT 0x00000000
-
-/* PCIE_0_INTR2 :: PCI_STATUS :: PCIE_MSTR_UR_ATTN [12:12] */
-#define BCHP_PCIE_0_INTR2_PCI_STATUS_PCIE_MSTR_UR_ATTN_MASK 0x00001000
-#define BCHP_PCIE_0_INTR2_PCI_STATUS_PCIE_MSTR_UR_ATTN_SHIFT 12
-#define BCHP_PCIE_0_INTR2_PCI_STATUS_PCIE_MSTR_UR_ATTN_DEFAULT 0x00000000
-
-/* PCIE_0_INTR2 :: PCI_STATUS :: UNASSIGNED_11 [11:11] */
-#define BCHP_PCIE_0_INTR2_PCI_STATUS_UNASSIGNED_11_MASK 0x00000800
-#define BCHP_PCIE_0_INTR2_PCI_STATUS_UNASSIGNED_11_SHIFT 11
-#define BCHP_PCIE_0_INTR2_PCI_STATUS_UNASSIGNED_11_DEFAULT 0x00000000
-
-/* PCIE_0_INTR2 :: PCI_STATUS :: UNASSIGNED_10 [10:10] */
-#define BCHP_PCIE_0_INTR2_PCI_STATUS_UNASSIGNED_10_MASK 0x00000400
-#define BCHP_PCIE_0_INTR2_PCI_STATUS_UNASSIGNED_10_SHIFT 10
-#define BCHP_PCIE_0_INTR2_PCI_STATUS_UNASSIGNED_10_DEFAULT 0x00000000
-
-/* PCIE_0_INTR2 :: PCI_STATUS :: PCIE_TGT_BAD_ACCESS [09:09] */
-#define BCHP_PCIE_0_INTR2_PCI_STATUS_PCIE_TGT_BAD_ACCESS_MASK 0x00000200
-#define BCHP_PCIE_0_INTR2_PCI_STATUS_PCIE_TGT_BAD_ACCESS_SHIFT 9
-#define BCHP_PCIE_0_INTR2_PCI_STATUS_PCIE_TGT_BAD_ACCESS_DEFAULT 0x00000000
-
-/* PCIE_0_INTR2 :: PCI_STATUS :: PCIE_TGT_BAD_ADDRESS [08:08] */
-#define BCHP_PCIE_0_INTR2_PCI_STATUS_PCIE_TGT_BAD_ADDRESS_MASK 0x00000100
-#define BCHP_PCIE_0_INTR2_PCI_STATUS_PCIE_TGT_BAD_ADDRESS_SHIFT 8
-#define BCHP_PCIE_0_INTR2_PCI_STATUS_PCIE_TGT_BAD_ADDRESS_DEFAULT 0x00000000
-
-/* PCIE_0_INTR2 :: PCI_STATUS :: L1_RX_DMA_ERR_INTR [07:07] */
-#define BCHP_PCIE_0_INTR2_PCI_STATUS_L1_RX_DMA_ERR_INTR_MASK 0x00000080
-#define BCHP_PCIE_0_INTR2_PCI_STATUS_L1_RX_DMA_ERR_INTR_SHIFT 7
-#define BCHP_PCIE_0_INTR2_PCI_STATUS_L1_RX_DMA_ERR_INTR_DEFAULT 0x00000000
-
-/* PCIE_0_INTR2 :: PCI_STATUS :: L1_RX_DMA_DONE_INTR [06:06] */
-#define BCHP_PCIE_0_INTR2_PCI_STATUS_L1_RX_DMA_DONE_INTR_MASK 0x00000040
-#define BCHP_PCIE_0_INTR2_PCI_STATUS_L1_RX_DMA_DONE_INTR_SHIFT 6
-#define BCHP_PCIE_0_INTR2_PCI_STATUS_L1_RX_DMA_DONE_INTR_DEFAULT 0x00000000
-
-/* PCIE_0_INTR2 :: PCI_STATUS :: L1_TX_DMA_ERR_INTR [05:05] */
-#define BCHP_PCIE_0_INTR2_PCI_STATUS_L1_TX_DMA_ERR_INTR_MASK 0x00000020
-#define BCHP_PCIE_0_INTR2_PCI_STATUS_L1_TX_DMA_ERR_INTR_SHIFT 5
-#define BCHP_PCIE_0_INTR2_PCI_STATUS_L1_TX_DMA_ERR_INTR_DEFAULT 0x00000000
-
-/* PCIE_0_INTR2 :: PCI_STATUS :: L1_TX_DMA_DONE_INTR [04:04] */
-#define BCHP_PCIE_0_INTR2_PCI_STATUS_L1_TX_DMA_DONE_INTR_MASK 0x00000010
-#define BCHP_PCIE_0_INTR2_PCI_STATUS_L1_TX_DMA_DONE_INTR_SHIFT 4
-#define BCHP_PCIE_0_INTR2_PCI_STATUS_L1_TX_DMA_DONE_INTR_DEFAULT 0x00000000
-
-/* PCIE_0_INTR2 :: PCI_STATUS :: L0_RX_DMA_ERR_INTR [03:03] */
-#define BCHP_PCIE_0_INTR2_PCI_STATUS_L0_RX_DMA_ERR_INTR_MASK 0x00000008
-#define BCHP_PCIE_0_INTR2_PCI_STATUS_L0_RX_DMA_ERR_INTR_SHIFT 3
-#define BCHP_PCIE_0_INTR2_PCI_STATUS_L0_RX_DMA_ERR_INTR_DEFAULT 0x00000000
-
-/* PCIE_0_INTR2 :: PCI_STATUS :: L0_RX_DMA_DONE_INTR [02:02] */
-#define BCHP_PCIE_0_INTR2_PCI_STATUS_L0_RX_DMA_DONE_INTR_MASK 0x00000004
-#define BCHP_PCIE_0_INTR2_PCI_STATUS_L0_RX_DMA_DONE_INTR_SHIFT 2
-#define BCHP_PCIE_0_INTR2_PCI_STATUS_L0_RX_DMA_DONE_INTR_DEFAULT 0x00000000
-
-/* PCIE_0_INTR2 :: PCI_STATUS :: L0_TX_DMA_ERR_INTR [01:01] */
-#define BCHP_PCIE_0_INTR2_PCI_STATUS_L0_TX_DMA_ERR_INTR_MASK 0x00000002
-#define BCHP_PCIE_0_INTR2_PCI_STATUS_L0_TX_DMA_ERR_INTR_SHIFT 1
-#define BCHP_PCIE_0_INTR2_PCI_STATUS_L0_TX_DMA_ERR_INTR_DEFAULT 0x00000000
-
-/* PCIE_0_INTR2 :: PCI_STATUS :: L0_TX_DMA_DONE_INTR [00:00] */
-#define BCHP_PCIE_0_INTR2_PCI_STATUS_L0_TX_DMA_DONE_INTR_MASK 0x00000001
-#define BCHP_PCIE_0_INTR2_PCI_STATUS_L0_TX_DMA_DONE_INTR_SHIFT 0
-#define BCHP_PCIE_0_INTR2_PCI_STATUS_L0_TX_DMA_DONE_INTR_DEFAULT 0x00000000
-
-/***************************************************************************
- *PCI_SET - PCI interrupt Set Register
- ***************************************************************************/
-/* PCIE_0_INTR2 :: PCI_SET :: MSI_INTR07 [31:31] */
-#define BCHP_PCIE_0_INTR2_PCI_SET_MSI_INTR07_MASK 0x80000000
-#define BCHP_PCIE_0_INTR2_PCI_SET_MSI_INTR07_SHIFT 31
-#define BCHP_PCIE_0_INTR2_PCI_SET_MSI_INTR07_DEFAULT 0x00000000
-
-/* PCIE_0_INTR2 :: PCI_SET :: MSI_INTR06 [30:30] */
-#define BCHP_PCIE_0_INTR2_PCI_SET_MSI_INTR06_MASK 0x40000000
-#define BCHP_PCIE_0_INTR2_PCI_SET_MSI_INTR06_SHIFT 30
-#define BCHP_PCIE_0_INTR2_PCI_SET_MSI_INTR06_DEFAULT 0x00000000
-
-/* PCIE_0_INTR2 :: PCI_SET :: MSI_INTR05 [29:29] */
-#define BCHP_PCIE_0_INTR2_PCI_SET_MSI_INTR05_MASK 0x20000000
-#define BCHP_PCIE_0_INTR2_PCI_SET_MSI_INTR05_SHIFT 29
-#define BCHP_PCIE_0_INTR2_PCI_SET_MSI_INTR05_DEFAULT 0x00000000
-
-/* PCIE_0_INTR2 :: PCI_SET :: MSI_INTR04 [28:28] */
-#define BCHP_PCIE_0_INTR2_PCI_SET_MSI_INTR04_MASK 0x10000000
-#define BCHP_PCIE_0_INTR2_PCI_SET_MSI_INTR04_SHIFT 28
-#define BCHP_PCIE_0_INTR2_PCI_SET_MSI_INTR04_DEFAULT 0x00000000
-
-/* PCIE_0_INTR2 :: PCI_SET :: MSI_INTR03 [27:27] */
-#define BCHP_PCIE_0_INTR2_PCI_SET_MSI_INTR03_MASK 0x08000000
-#define BCHP_PCIE_0_INTR2_PCI_SET_MSI_INTR03_SHIFT 27
-#define BCHP_PCIE_0_INTR2_PCI_SET_MSI_INTR03_DEFAULT 0x00000000
-
-/* PCIE_0_INTR2 :: PCI_SET :: MSI_INTR02 [26:26] */
-#define BCHP_PCIE_0_INTR2_PCI_SET_MSI_INTR02_MASK 0x04000000
-#define BCHP_PCIE_0_INTR2_PCI_SET_MSI_INTR02_SHIFT 26
-#define BCHP_PCIE_0_INTR2_PCI_SET_MSI_INTR02_DEFAULT 0x00000000
-
-/* PCIE_0_INTR2 :: PCI_SET :: MSI_INTR01 [25:25] */
-#define BCHP_PCIE_0_INTR2_PCI_SET_MSI_INTR01_MASK 0x02000000
-#define BCHP_PCIE_0_INTR2_PCI_SET_MSI_INTR01_SHIFT 25
-#define BCHP_PCIE_0_INTR2_PCI_SET_MSI_INTR01_DEFAULT 0x00000000
-
-/* PCIE_0_INTR2 :: PCI_SET :: MSI_INTR00 [24:24] */
-#define BCHP_PCIE_0_INTR2_PCI_SET_MSI_INTR00_MASK 0x01000000
-#define BCHP_PCIE_0_INTR2_PCI_SET_MSI_INTR00_SHIFT 24
-#define BCHP_PCIE_0_INTR2_PCI_SET_MSI_INTR00_DEFAULT 0x00000000
-
-/* PCIE_0_INTR2 :: PCI_SET :: UNASSIGNED_23 [23:23] */
-#define BCHP_PCIE_0_INTR2_PCI_SET_UNASSIGNED_23_MASK 0x00800000
-#define BCHP_PCIE_0_INTR2_PCI_SET_UNASSIGNED_23_SHIFT 23
-#define BCHP_PCIE_0_INTR2_PCI_SET_UNASSIGNED_23_DEFAULT 0x00000000
-
-/* PCIE_0_INTR2 :: PCI_SET :: UNASSIGNED_22 [22:22] */
-#define BCHP_PCIE_0_INTR2_PCI_SET_UNASSIGNED_22_MASK 0x00400000
-#define BCHP_PCIE_0_INTR2_PCI_SET_UNASSIGNED_22_SHIFT 22
-#define BCHP_PCIE_0_INTR2_PCI_SET_UNASSIGNED_22_DEFAULT 0x00000000
-
-/* PCIE_0_INTR2 :: PCI_SET :: UNASSIGNED_21 [21:21] */
-#define BCHP_PCIE_0_INTR2_PCI_SET_UNASSIGNED_21_MASK 0x00200000
-#define BCHP_PCIE_0_INTR2_PCI_SET_UNASSIGNED_21_SHIFT 21
-#define BCHP_PCIE_0_INTR2_PCI_SET_UNASSIGNED_21_DEFAULT 0x00000000
-
-/* PCIE_0_INTR2 :: PCI_SET :: UNASSIGNED_20 [20:20] */
-#define BCHP_PCIE_0_INTR2_PCI_SET_UNASSIGNED_20_MASK 0x00100000
-#define BCHP_PCIE_0_INTR2_PCI_SET_UNASSIGNED_20_SHIFT 20
-#define BCHP_PCIE_0_INTR2_PCI_SET_UNASSIGNED_20_DEFAULT 0x00000000
-
-/* PCIE_0_INTR2 :: PCI_SET :: MAILBOX_3 [19:19] */
-#define BCHP_PCIE_0_INTR2_PCI_SET_MAILBOX_3_MASK 0x00080000
-#define BCHP_PCIE_0_INTR2_PCI_SET_MAILBOX_3_SHIFT 19
-#define BCHP_PCIE_0_INTR2_PCI_SET_MAILBOX_3_DEFAULT 0x00000000
-
-/* PCIE_0_INTR2 :: PCI_SET :: MAILBOX_2 [18:18] */
-#define BCHP_PCIE_0_INTR2_PCI_SET_MAILBOX_2_MASK 0x00040000
-#define BCHP_PCIE_0_INTR2_PCI_SET_MAILBOX_2_SHIFT 18
-#define BCHP_PCIE_0_INTR2_PCI_SET_MAILBOX_2_DEFAULT 0x00000000
-
-/* PCIE_0_INTR2 :: PCI_SET :: MAILBOX_1 [17:17] */
-#define BCHP_PCIE_0_INTR2_PCI_SET_MAILBOX_1_MASK 0x00020000
-#define BCHP_PCIE_0_INTR2_PCI_SET_MAILBOX_1_SHIFT 17
-#define BCHP_PCIE_0_INTR2_PCI_SET_MAILBOX_1_DEFAULT 0x00000000
-
-/* PCIE_0_INTR2 :: PCI_SET :: MAILBOX_0 [16:16] */
-#define BCHP_PCIE_0_INTR2_PCI_SET_MAILBOX_0_MASK 0x00010000
-#define BCHP_PCIE_0_INTR2_PCI_SET_MAILBOX_0_SHIFT 16
-#define BCHP_PCIE_0_INTR2_PCI_SET_MAILBOX_0_DEFAULT 0x00000000
-
-/* PCIE_0_INTR2 :: PCI_SET :: PCIE_MSTR_FWD_ERR [15:15] */
-#define BCHP_PCIE_0_INTR2_PCI_SET_PCIE_MSTR_FWD_ERR_MASK 0x00008000
-#define BCHP_PCIE_0_INTR2_PCI_SET_PCIE_MSTR_FWD_ERR_SHIFT 15
-#define BCHP_PCIE_0_INTR2_PCI_SET_PCIE_MSTR_FWD_ERR_DEFAULT 0x00000000
-
-/* PCIE_0_INTR2 :: PCI_SET :: PCIE_MSTR_RETRY_TIMEOUT [14:14] */
-#define BCHP_PCIE_0_INTR2_PCI_SET_PCIE_MSTR_RETRY_TIMEOUT_MASK 0x00004000
-#define BCHP_PCIE_0_INTR2_PCI_SET_PCIE_MSTR_RETRY_TIMEOUT_SHIFT 14
-#define BCHP_PCIE_0_INTR2_PCI_SET_PCIE_MSTR_RETRY_TIMEOUT_DEFAULT 0x00000000
-
-/* PCIE_0_INTR2 :: PCI_SET :: PCIE_MSTR_CA_ATTN [13:13] */
-#define BCHP_PCIE_0_INTR2_PCI_SET_PCIE_MSTR_CA_ATTN_MASK 0x00002000
-#define BCHP_PCIE_0_INTR2_PCI_SET_PCIE_MSTR_CA_ATTN_SHIFT 13
-#define BCHP_PCIE_0_INTR2_PCI_SET_PCIE_MSTR_CA_ATTN_DEFAULT 0x00000000
-
-/* PCIE_0_INTR2 :: PCI_SET :: PCIE_MSTR_UR_ATTN [12:12] */
-#define BCHP_PCIE_0_INTR2_PCI_SET_PCIE_MSTR_UR_ATTN_MASK 0x00001000
-#define BCHP_PCIE_0_INTR2_PCI_SET_PCIE_MSTR_UR_ATTN_SHIFT 12
-#define BCHP_PCIE_0_INTR2_PCI_SET_PCIE_MSTR_UR_ATTN_DEFAULT 0x00000000
-
-/* PCIE_0_INTR2 :: PCI_SET :: UNASSIGNED_11 [11:11] */
-#define BCHP_PCIE_0_INTR2_PCI_SET_UNASSIGNED_11_MASK 0x00000800
-#define BCHP_PCIE_0_INTR2_PCI_SET_UNASSIGNED_11_SHIFT 11
-#define BCHP_PCIE_0_INTR2_PCI_SET_UNASSIGNED_11_DEFAULT 0x00000000
-
-/* PCIE_0_INTR2 :: PCI_SET :: UNASSIGNED_10 [10:10] */
-#define BCHP_PCIE_0_INTR2_PCI_SET_UNASSIGNED_10_MASK 0x00000400
-#define BCHP_PCIE_0_INTR2_PCI_SET_UNASSIGNED_10_SHIFT 10
-#define BCHP_PCIE_0_INTR2_PCI_SET_UNASSIGNED_10_DEFAULT 0x00000000
-
-/* PCIE_0_INTR2 :: PCI_SET :: PCIE_TGT_BAD_ACCESS [09:09] */
-#define BCHP_PCIE_0_INTR2_PCI_SET_PCIE_TGT_BAD_ACCESS_MASK 0x00000200
-#define BCHP_PCIE_0_INTR2_PCI_SET_PCIE_TGT_BAD_ACCESS_SHIFT 9
-#define BCHP_PCIE_0_INTR2_PCI_SET_PCIE_TGT_BAD_ACCESS_DEFAULT 0x00000000
-
-/* PCIE_0_INTR2 :: PCI_SET :: PCIE_TGT_BAD_ADDRESS [08:08] */
-#define BCHP_PCIE_0_INTR2_PCI_SET_PCIE_TGT_BAD_ADDRESS_MASK 0x00000100
-#define BCHP_PCIE_0_INTR2_PCI_SET_PCIE_TGT_BAD_ADDRESS_SHIFT 8
-#define BCHP_PCIE_0_INTR2_PCI_SET_PCIE_TGT_BAD_ADDRESS_DEFAULT 0x00000000
-
-/* PCIE_0_INTR2 :: PCI_SET :: L1_RX_DMA_ERR_INTR [07:07] */
-#define BCHP_PCIE_0_INTR2_PCI_SET_L1_RX_DMA_ERR_INTR_MASK 0x00000080
-#define BCHP_PCIE_0_INTR2_PCI_SET_L1_RX_DMA_ERR_INTR_SHIFT 7
-#define BCHP_PCIE_0_INTR2_PCI_SET_L1_RX_DMA_ERR_INTR_DEFAULT 0x00000000
-
-/* PCIE_0_INTR2 :: PCI_SET :: L1_RX_DMA_DONE_INTR [06:06] */
-#define BCHP_PCIE_0_INTR2_PCI_SET_L1_RX_DMA_DONE_INTR_MASK 0x00000040
-#define BCHP_PCIE_0_INTR2_PCI_SET_L1_RX_DMA_DONE_INTR_SHIFT 6
-#define BCHP_PCIE_0_INTR2_PCI_SET_L1_RX_DMA_DONE_INTR_DEFAULT 0x00000000
-
-/* PCIE_0_INTR2 :: PCI_SET :: L1_TX_DMA_ERR_INTR [05:05] */
-#define BCHP_PCIE_0_INTR2_PCI_SET_L1_TX_DMA_ERR_INTR_MASK 0x00000020
-#define BCHP_PCIE_0_INTR2_PCI_SET_L1_TX_DMA_ERR_INTR_SHIFT 5
-#define BCHP_PCIE_0_INTR2_PCI_SET_L1_TX_DMA_ERR_INTR_DEFAULT 0x00000000
-
-/* PCIE_0_INTR2 :: PCI_SET :: L1_TX_DMA_DONE_INTR [04:04] */
-#define BCHP_PCIE_0_INTR2_PCI_SET_L1_TX_DMA_DONE_INTR_MASK 0x00000010
-#define BCHP_PCIE_0_INTR2_PCI_SET_L1_TX_DMA_DONE_INTR_SHIFT 4
-#define BCHP_PCIE_0_INTR2_PCI_SET_L1_TX_DMA_DONE_INTR_DEFAULT 0x00000000
-
-/* PCIE_0_INTR2 :: PCI_SET :: L0_RX_DMA_ERR_INTR [03:03] */
-#define BCHP_PCIE_0_INTR2_PCI_SET_L0_RX_DMA_ERR_INTR_MASK 0x00000008
-#define BCHP_PCIE_0_INTR2_PCI_SET_L0_RX_DMA_ERR_INTR_SHIFT 3
-#define BCHP_PCIE_0_INTR2_PCI_SET_L0_RX_DMA_ERR_INTR_DEFAULT 0x00000000
-
-/* PCIE_0_INTR2 :: PCI_SET :: L0_RX_DMA_DONE_INTR [02:02] */
-#define BCHP_PCIE_0_INTR2_PCI_SET_L0_RX_DMA_DONE_INTR_MASK 0x00000004
-#define BCHP_PCIE_0_INTR2_PCI_SET_L0_RX_DMA_DONE_INTR_SHIFT 2
-#define BCHP_PCIE_0_INTR2_PCI_SET_L0_RX_DMA_DONE_INTR_DEFAULT 0x00000000
-
-/* PCIE_0_INTR2 :: PCI_SET :: L0_TX_DMA_ERR_INTR [01:01] */
-#define BCHP_PCIE_0_INTR2_PCI_SET_L0_TX_DMA_ERR_INTR_MASK 0x00000002
-#define BCHP_PCIE_0_INTR2_PCI_SET_L0_TX_DMA_ERR_INTR_SHIFT 1
-#define BCHP_PCIE_0_INTR2_PCI_SET_L0_TX_DMA_ERR_INTR_DEFAULT 0x00000000
-
-/* PCIE_0_INTR2 :: PCI_SET :: L0_TX_DMA_DONE_INTR [00:00] */
-#define BCHP_PCIE_0_INTR2_PCI_SET_L0_TX_DMA_DONE_INTR_MASK 0x00000001
-#define BCHP_PCIE_0_INTR2_PCI_SET_L0_TX_DMA_DONE_INTR_SHIFT 0
-#define BCHP_PCIE_0_INTR2_PCI_SET_L0_TX_DMA_DONE_INTR_DEFAULT 0x00000000
-
-/***************************************************************************
- *PCI_CLEAR - PCI interrupt Clear Register
- ***************************************************************************/
-/* PCIE_0_INTR2 :: PCI_CLEAR :: MSI_INTR07 [31:31] */
-#define BCHP_PCIE_0_INTR2_PCI_CLEAR_MSI_INTR07_MASK 0x80000000
-#define BCHP_PCIE_0_INTR2_PCI_CLEAR_MSI_INTR07_SHIFT 31
-#define BCHP_PCIE_0_INTR2_PCI_CLEAR_MSI_INTR07_DEFAULT 0x00000000
-
-/* PCIE_0_INTR2 :: PCI_CLEAR :: MSI_INTR06 [30:30] */
-#define BCHP_PCIE_0_INTR2_PCI_CLEAR_MSI_INTR06_MASK 0x40000000
-#define BCHP_PCIE_0_INTR2_PCI_CLEAR_MSI_INTR06_SHIFT 30
-#define BCHP_PCIE_0_INTR2_PCI_CLEAR_MSI_INTR06_DEFAULT 0x00000000
-
-/* PCIE_0_INTR2 :: PCI_CLEAR :: MSI_INTR05 [29:29] */
-#define BCHP_PCIE_0_INTR2_PCI_CLEAR_MSI_INTR05_MASK 0x20000000
-#define BCHP_PCIE_0_INTR2_PCI_CLEAR_MSI_INTR05_SHIFT 29
-#define BCHP_PCIE_0_INTR2_PCI_CLEAR_MSI_INTR05_DEFAULT 0x00000000
-
-/* PCIE_0_INTR2 :: PCI_CLEAR :: MSI_INTR04 [28:28] */
-#define BCHP_PCIE_0_INTR2_PCI_CLEAR_MSI_INTR04_MASK 0x10000000
-#define BCHP_PCIE_0_INTR2_PCI_CLEAR_MSI_INTR04_SHIFT 28
-#define BCHP_PCIE_0_INTR2_PCI_CLEAR_MSI_INTR04_DEFAULT 0x00000000
-
-/* PCIE_0_INTR2 :: PCI_CLEAR :: MSI_INTR03 [27:27] */
-#define BCHP_PCIE_0_INTR2_PCI_CLEAR_MSI_INTR03_MASK 0x08000000
-#define BCHP_PCIE_0_INTR2_PCI_CLEAR_MSI_INTR03_SHIFT 27
-#define BCHP_PCIE_0_INTR2_PCI_CLEAR_MSI_INTR03_DEFAULT 0x00000000
-
-/* PCIE_0_INTR2 :: PCI_CLEAR :: MSI_INTR02 [26:26] */
-#define BCHP_PCIE_0_INTR2_PCI_CLEAR_MSI_INTR02_MASK 0x04000000
-#define BCHP_PCIE_0_INTR2_PCI_CLEAR_MSI_INTR02_SHIFT 26
-#define BCHP_PCIE_0_INTR2_PCI_CLEAR_MSI_INTR02_DEFAULT 0x00000000
-
-/* PCIE_0_INTR2 :: PCI_CLEAR :: MSI_INTR01 [25:25] */
-#define BCHP_PCIE_0_INTR2_PCI_CLEAR_MSI_INTR01_MASK 0x02000000
-#define BCHP_PCIE_0_INTR2_PCI_CLEAR_MSI_INTR01_SHIFT 25
-#define BCHP_PCIE_0_INTR2_PCI_CLEAR_MSI_INTR01_DEFAULT 0x00000000
-
-/* PCIE_0_INTR2 :: PCI_CLEAR :: MSI_INTR00 [24:24] */
-#define BCHP_PCIE_0_INTR2_PCI_CLEAR_MSI_INTR00_MASK 0x01000000
-#define BCHP_PCIE_0_INTR2_PCI_CLEAR_MSI_INTR00_SHIFT 24
-#define BCHP_PCIE_0_INTR2_PCI_CLEAR_MSI_INTR00_DEFAULT 0x00000000
-
-/* PCIE_0_INTR2 :: PCI_CLEAR :: UNASSIGNED_23 [23:23] */
-#define BCHP_PCIE_0_INTR2_PCI_CLEAR_UNASSIGNED_23_MASK 0x00800000
-#define BCHP_PCIE_0_INTR2_PCI_CLEAR_UNASSIGNED_23_SHIFT 23
-#define BCHP_PCIE_0_INTR2_PCI_CLEAR_UNASSIGNED_23_DEFAULT 0x00000000
-
-/* PCIE_0_INTR2 :: PCI_CLEAR :: UNASSIGNED_22 [22:22] */
-#define BCHP_PCIE_0_INTR2_PCI_CLEAR_UNASSIGNED_22_MASK 0x00400000
-#define BCHP_PCIE_0_INTR2_PCI_CLEAR_UNASSIGNED_22_SHIFT 22
-#define BCHP_PCIE_0_INTR2_PCI_CLEAR_UNASSIGNED_22_DEFAULT 0x00000000
-
-/* PCIE_0_INTR2 :: PCI_CLEAR :: UNASSIGNED_21 [21:21] */
-#define BCHP_PCIE_0_INTR2_PCI_CLEAR_UNASSIGNED_21_MASK 0x00200000
-#define BCHP_PCIE_0_INTR2_PCI_CLEAR_UNASSIGNED_21_SHIFT 21
-#define BCHP_PCIE_0_INTR2_PCI_CLEAR_UNASSIGNED_21_DEFAULT 0x00000000
-
-/* PCIE_0_INTR2 :: PCI_CLEAR :: UNASSIGNED_20 [20:20] */
-#define BCHP_PCIE_0_INTR2_PCI_CLEAR_UNASSIGNED_20_MASK 0x00100000
-#define BCHP_PCIE_0_INTR2_PCI_CLEAR_UNASSIGNED_20_SHIFT 20
-#define BCHP_PCIE_0_INTR2_PCI_CLEAR_UNASSIGNED_20_DEFAULT 0x00000000
-
-/* PCIE_0_INTR2 :: PCI_CLEAR :: MAILBOX_3 [19:19] */
-#define BCHP_PCIE_0_INTR2_PCI_CLEAR_MAILBOX_3_MASK 0x00080000
-#define BCHP_PCIE_0_INTR2_PCI_CLEAR_MAILBOX_3_SHIFT 19
-#define BCHP_PCIE_0_INTR2_PCI_CLEAR_MAILBOX_3_DEFAULT 0x00000000
-
-/* PCIE_0_INTR2 :: PCI_CLEAR :: MAILBOX_2 [18:18] */
-#define BCHP_PCIE_0_INTR2_PCI_CLEAR_MAILBOX_2_MASK 0x00040000
-#define BCHP_PCIE_0_INTR2_PCI_CLEAR_MAILBOX_2_SHIFT 18
-#define BCHP_PCIE_0_INTR2_PCI_CLEAR_MAILBOX_2_DEFAULT 0x00000000
-
-/* PCIE_0_INTR2 :: PCI_CLEAR :: MAILBOX_1 [17:17] */
-#define BCHP_PCIE_0_INTR2_PCI_CLEAR_MAILBOX_1_MASK 0x00020000
-#define BCHP_PCIE_0_INTR2_PCI_CLEAR_MAILBOX_1_SHIFT 17
-#define BCHP_PCIE_0_INTR2_PCI_CLEAR_MAILBOX_1_DEFAULT 0x00000000
-
-/* PCIE_0_INTR2 :: PCI_CLEAR :: MAILBOX_0 [16:16] */
-#define BCHP_PCIE_0_INTR2_PCI_CLEAR_MAILBOX_0_MASK 0x00010000
-#define BCHP_PCIE_0_INTR2_PCI_CLEAR_MAILBOX_0_SHIFT 16
-#define BCHP_PCIE_0_INTR2_PCI_CLEAR_MAILBOX_0_DEFAULT 0x00000000
-
-/* PCIE_0_INTR2 :: PCI_CLEAR :: PCIE_MSTR_FWD_ERR [15:15] */
-#define BCHP_PCIE_0_INTR2_PCI_CLEAR_PCIE_MSTR_FWD_ERR_MASK 0x00008000
-#define BCHP_PCIE_0_INTR2_PCI_CLEAR_PCIE_MSTR_FWD_ERR_SHIFT 15
-#define BCHP_PCIE_0_INTR2_PCI_CLEAR_PCIE_MSTR_FWD_ERR_DEFAULT 0x00000000
-
-/* PCIE_0_INTR2 :: PCI_CLEAR :: PCIE_MSTR_RETRY_TIMEOUT [14:14] */
-#define BCHP_PCIE_0_INTR2_PCI_CLEAR_PCIE_MSTR_RETRY_TIMEOUT_MASK 0x00004000
-#define BCHP_PCIE_0_INTR2_PCI_CLEAR_PCIE_MSTR_RETRY_TIMEOUT_SHIFT 14
-#define BCHP_PCIE_0_INTR2_PCI_CLEAR_PCIE_MSTR_RETRY_TIMEOUT_DEFAULT 0x00000000
-
-/* PCIE_0_INTR2 :: PCI_CLEAR :: PCIE_MSTR_CA_ATTN [13:13] */
-#define BCHP_PCIE_0_INTR2_PCI_CLEAR_PCIE_MSTR_CA_ATTN_MASK 0x00002000
-#define BCHP_PCIE_0_INTR2_PCI_CLEAR_PCIE_MSTR_CA_ATTN_SHIFT 13
-#define BCHP_PCIE_0_INTR2_PCI_CLEAR_PCIE_MSTR_CA_ATTN_DEFAULT 0x00000000
-
-/* PCIE_0_INTR2 :: PCI_CLEAR :: PCIE_MSTR_UR_ATTN [12:12] */
-#define BCHP_PCIE_0_INTR2_PCI_CLEAR_PCIE_MSTR_UR_ATTN_MASK 0x00001000
-#define BCHP_PCIE_0_INTR2_PCI_CLEAR_PCIE_MSTR_UR_ATTN_SHIFT 12
-#define BCHP_PCIE_0_INTR2_PCI_CLEAR_PCIE_MSTR_UR_ATTN_DEFAULT 0x00000000
-
-/* PCIE_0_INTR2 :: PCI_CLEAR :: UNASSIGNED_11 [11:11] */
-#define BCHP_PCIE_0_INTR2_PCI_CLEAR_UNASSIGNED_11_MASK 0x00000800
-#define BCHP_PCIE_0_INTR2_PCI_CLEAR_UNASSIGNED_11_SHIFT 11
-#define BCHP_PCIE_0_INTR2_PCI_CLEAR_UNASSIGNED_11_DEFAULT 0x00000000
-
-/* PCIE_0_INTR2 :: PCI_CLEAR :: UNASSIGNED_10 [10:10] */
-#define BCHP_PCIE_0_INTR2_PCI_CLEAR_UNASSIGNED_10_MASK 0x00000400
-#define BCHP_PCIE_0_INTR2_PCI_CLEAR_UNASSIGNED_10_SHIFT 10
-#define BCHP_PCIE_0_INTR2_PCI_CLEAR_UNASSIGNED_10_DEFAULT 0x00000000
-
-/* PCIE_0_INTR2 :: PCI_CLEAR :: PCIE_TGT_BAD_ACCESS [09:09] */
-#define BCHP_PCIE_0_INTR2_PCI_CLEAR_PCIE_TGT_BAD_ACCESS_MASK 0x00000200
-#define BCHP_PCIE_0_INTR2_PCI_CLEAR_PCIE_TGT_BAD_ACCESS_SHIFT 9
-#define BCHP_PCIE_0_INTR2_PCI_CLEAR_PCIE_TGT_BAD_ACCESS_DEFAULT 0x00000000
-
-/* PCIE_0_INTR2 :: PCI_CLEAR :: PCIE_TGT_BAD_ADDRESS [08:08] */
-#define BCHP_PCIE_0_INTR2_PCI_CLEAR_PCIE_TGT_BAD_ADDRESS_MASK 0x00000100
-#define BCHP_PCIE_0_INTR2_PCI_CLEAR_PCIE_TGT_BAD_ADDRESS_SHIFT 8
-#define BCHP_PCIE_0_INTR2_PCI_CLEAR_PCIE_TGT_BAD_ADDRESS_DEFAULT 0x00000000
-
-/* PCIE_0_INTR2 :: PCI_CLEAR :: L1_RX_DMA_ERR_INTR [07:07] */
-#define BCHP_PCIE_0_INTR2_PCI_CLEAR_L1_RX_DMA_ERR_INTR_MASK 0x00000080
-#define BCHP_PCIE_0_INTR2_PCI_CLEAR_L1_RX_DMA_ERR_INTR_SHIFT 7
-#define BCHP_PCIE_0_INTR2_PCI_CLEAR_L1_RX_DMA_ERR_INTR_DEFAULT 0x00000000
-
-/* PCIE_0_INTR2 :: PCI_CLEAR :: L1_RX_DMA_DONE_INTR [06:06] */
-#define BCHP_PCIE_0_INTR2_PCI_CLEAR_L1_RX_DMA_DONE_INTR_MASK 0x00000040
-#define BCHP_PCIE_0_INTR2_PCI_CLEAR_L1_RX_DMA_DONE_INTR_SHIFT 6
-#define BCHP_PCIE_0_INTR2_PCI_CLEAR_L1_RX_DMA_DONE_INTR_DEFAULT 0x00000000
-
-/* PCIE_0_INTR2 :: PCI_CLEAR :: L1_TX_DMA_ERR_INTR [05:05] */
-#define BCHP_PCIE_0_INTR2_PCI_CLEAR_L1_TX_DMA_ERR_INTR_MASK 0x00000020
-#define BCHP_PCIE_0_INTR2_PCI_CLEAR_L1_TX_DMA_ERR_INTR_SHIFT 5
-#define BCHP_PCIE_0_INTR2_PCI_CLEAR_L1_TX_DMA_ERR_INTR_DEFAULT 0x00000000
-
-/* PCIE_0_INTR2 :: PCI_CLEAR :: L1_TX_DMA_DONE_INTR [04:04] */
-#define BCHP_PCIE_0_INTR2_PCI_CLEAR_L1_TX_DMA_DONE_INTR_MASK 0x00000010
-#define BCHP_PCIE_0_INTR2_PCI_CLEAR_L1_TX_DMA_DONE_INTR_SHIFT 4
-#define BCHP_PCIE_0_INTR2_PCI_CLEAR_L1_TX_DMA_DONE_INTR_DEFAULT 0x00000000
-
-/* PCIE_0_INTR2 :: PCI_CLEAR :: L0_RX_DMA_ERR_INTR [03:03] */
-#define BCHP_PCIE_0_INTR2_PCI_CLEAR_L0_RX_DMA_ERR_INTR_MASK 0x00000008
-#define BCHP_PCIE_0_INTR2_PCI_CLEAR_L0_RX_DMA_ERR_INTR_SHIFT 3
-#define BCHP_PCIE_0_INTR2_PCI_CLEAR_L0_RX_DMA_ERR_INTR_DEFAULT 0x00000000
-
-/* PCIE_0_INTR2 :: PCI_CLEAR :: L0_RX_DMA_DONE_INTR [02:02] */
-#define BCHP_PCIE_0_INTR2_PCI_CLEAR_L0_RX_DMA_DONE_INTR_MASK 0x00000004
-#define BCHP_PCIE_0_INTR2_PCI_CLEAR_L0_RX_DMA_DONE_INTR_SHIFT 2
-#define BCHP_PCIE_0_INTR2_PCI_CLEAR_L0_RX_DMA_DONE_INTR_DEFAULT 0x00000000
-
-/* PCIE_0_INTR2 :: PCI_CLEAR :: L0_TX_DMA_ERR_INTR [01:01] */
-#define BCHP_PCIE_0_INTR2_PCI_CLEAR_L0_TX_DMA_ERR_INTR_MASK 0x00000002
-#define BCHP_PCIE_0_INTR2_PCI_CLEAR_L0_TX_DMA_ERR_INTR_SHIFT 1
-#define BCHP_PCIE_0_INTR2_PCI_CLEAR_L0_TX_DMA_ERR_INTR_DEFAULT 0x00000000
-
-/* PCIE_0_INTR2 :: PCI_CLEAR :: L0_TX_DMA_DONE_INTR [00:00] */
-#define BCHP_PCIE_0_INTR2_PCI_CLEAR_L0_TX_DMA_DONE_INTR_MASK 0x00000001
-#define BCHP_PCIE_0_INTR2_PCI_CLEAR_L0_TX_DMA_DONE_INTR_SHIFT 0
-#define BCHP_PCIE_0_INTR2_PCI_CLEAR_L0_TX_DMA_DONE_INTR_DEFAULT 0x00000000
-
-/***************************************************************************
- *PCI_MASK_STATUS - PCI interrupt Mask Status Register
- ***************************************************************************/
-/* PCIE_0_INTR2 :: PCI_MASK_STATUS :: MSI_INTR07 [31:31] */
-#define BCHP_PCIE_0_INTR2_PCI_MASK_STATUS_MSI_INTR07_MASK 0x80000000
-#define BCHP_PCIE_0_INTR2_PCI_MASK_STATUS_MSI_INTR07_SHIFT 31
-#define BCHP_PCIE_0_INTR2_PCI_MASK_STATUS_MSI_INTR07_DEFAULT 0x00000001
-
-/* PCIE_0_INTR2 :: PCI_MASK_STATUS :: MSI_INTR06 [30:30] */
-#define BCHP_PCIE_0_INTR2_PCI_MASK_STATUS_MSI_INTR06_MASK 0x40000000
-#define BCHP_PCIE_0_INTR2_PCI_MASK_STATUS_MSI_INTR06_SHIFT 30
-#define BCHP_PCIE_0_INTR2_PCI_MASK_STATUS_MSI_INTR06_DEFAULT 0x00000001
-
-/* PCIE_0_INTR2 :: PCI_MASK_STATUS :: MSI_INTR05 [29:29] */
-#define BCHP_PCIE_0_INTR2_PCI_MASK_STATUS_MSI_INTR05_MASK 0x20000000
-#define BCHP_PCIE_0_INTR2_PCI_MASK_STATUS_MSI_INTR05_SHIFT 29
-#define BCHP_PCIE_0_INTR2_PCI_MASK_STATUS_MSI_INTR05_DEFAULT 0x00000001
-
-/* PCIE_0_INTR2 :: PCI_MASK_STATUS :: MSI_INTR04 [28:28] */
-#define BCHP_PCIE_0_INTR2_PCI_MASK_STATUS_MSI_INTR04_MASK 0x10000000
-#define BCHP_PCIE_0_INTR2_PCI_MASK_STATUS_MSI_INTR04_SHIFT 28
-#define BCHP_PCIE_0_INTR2_PCI_MASK_STATUS_MSI_INTR04_DEFAULT 0x00000001
-
-/* PCIE_0_INTR2 :: PCI_MASK_STATUS :: MSI_INTR03 [27:27] */
-#define BCHP_PCIE_0_INTR2_PCI_MASK_STATUS_MSI_INTR03_MASK 0x08000000
-#define BCHP_PCIE_0_INTR2_PCI_MASK_STATUS_MSI_INTR03_SHIFT 27
-#define BCHP_PCIE_0_INTR2_PCI_MASK_STATUS_MSI_INTR03_DEFAULT 0x00000001
-
-/* PCIE_0_INTR2 :: PCI_MASK_STATUS :: MSI_INTR02 [26:26] */
-#define BCHP_PCIE_0_INTR2_PCI_MASK_STATUS_MSI_INTR02_MASK 0x04000000
-#define BCHP_PCIE_0_INTR2_PCI_MASK_STATUS_MSI_INTR02_SHIFT 26
-#define BCHP_PCIE_0_INTR2_PCI_MASK_STATUS_MSI_INTR02_DEFAULT 0x00000001
-
-/* PCIE_0_INTR2 :: PCI_MASK_STATUS :: MSI_INTR01 [25:25] */
-#define BCHP_PCIE_0_INTR2_PCI_MASK_STATUS_MSI_INTR01_MASK 0x02000000
-#define BCHP_PCIE_0_INTR2_PCI_MASK_STATUS_MSI_INTR01_SHIFT 25
-#define BCHP_PCIE_0_INTR2_PCI_MASK_STATUS_MSI_INTR01_DEFAULT 0x00000001
-
-/* PCIE_0_INTR2 :: PCI_MASK_STATUS :: MSI_INTR00 [24:24] */
-#define BCHP_PCIE_0_INTR2_PCI_MASK_STATUS_MSI_INTR00_MASK 0x01000000
-#define BCHP_PCIE_0_INTR2_PCI_MASK_STATUS_MSI_INTR00_SHIFT 24
-#define BCHP_PCIE_0_INTR2_PCI_MASK_STATUS_MSI_INTR00_DEFAULT 0x00000001
-
-/* PCIE_0_INTR2 :: PCI_MASK_STATUS :: UNASSIGNED_23 [23:23] */
-#define BCHP_PCIE_0_INTR2_PCI_MASK_STATUS_UNASSIGNED_23_MASK 0x00800000
-#define BCHP_PCIE_0_INTR2_PCI_MASK_STATUS_UNASSIGNED_23_SHIFT 23
-#define BCHP_PCIE_0_INTR2_PCI_MASK_STATUS_UNASSIGNED_23_DEFAULT 0x00000001
-
-/* PCIE_0_INTR2 :: PCI_MASK_STATUS :: UNASSIGNED_22 [22:22] */
-#define BCHP_PCIE_0_INTR2_PCI_MASK_STATUS_UNASSIGNED_22_MASK 0x00400000
-#define BCHP_PCIE_0_INTR2_PCI_MASK_STATUS_UNASSIGNED_22_SHIFT 22
-#define BCHP_PCIE_0_INTR2_PCI_MASK_STATUS_UNASSIGNED_22_DEFAULT 0x00000001
-
-/* PCIE_0_INTR2 :: PCI_MASK_STATUS :: UNASSIGNED_21 [21:21] */
-#define BCHP_PCIE_0_INTR2_PCI_MASK_STATUS_UNASSIGNED_21_MASK 0x00200000
-#define BCHP_PCIE_0_INTR2_PCI_MASK_STATUS_UNASSIGNED_21_SHIFT 21
-#define BCHP_PCIE_0_INTR2_PCI_MASK_STATUS_UNASSIGNED_21_DEFAULT 0x00000001
-
-/* PCIE_0_INTR2 :: PCI_MASK_STATUS :: UNASSIGNED_20 [20:20] */
-#define BCHP_PCIE_0_INTR2_PCI_MASK_STATUS_UNASSIGNED_20_MASK 0x00100000
-#define BCHP_PCIE_0_INTR2_PCI_MASK_STATUS_UNASSIGNED_20_SHIFT 20
-#define BCHP_PCIE_0_INTR2_PCI_MASK_STATUS_UNASSIGNED_20_DEFAULT 0x00000001
-
-/* PCIE_0_INTR2 :: PCI_MASK_STATUS :: MAILBOX_3 [19:19] */
-#define BCHP_PCIE_0_INTR2_PCI_MASK_STATUS_MAILBOX_3_MASK 0x00080000
-#define BCHP_PCIE_0_INTR2_PCI_MASK_STATUS_MAILBOX_3_SHIFT 19
-#define BCHP_PCIE_0_INTR2_PCI_MASK_STATUS_MAILBOX_3_DEFAULT 0x00000001
-
-/* PCIE_0_INTR2 :: PCI_MASK_STATUS :: MAILBOX_2 [18:18] */
-#define BCHP_PCIE_0_INTR2_PCI_MASK_STATUS_MAILBOX_2_MASK 0x00040000
-#define BCHP_PCIE_0_INTR2_PCI_MASK_STATUS_MAILBOX_2_SHIFT 18
-#define BCHP_PCIE_0_INTR2_PCI_MASK_STATUS_MAILBOX_2_DEFAULT 0x00000001
-
-/* PCIE_0_INTR2 :: PCI_MASK_STATUS :: MAILBOX_1 [17:17] */
-#define BCHP_PCIE_0_INTR2_PCI_MASK_STATUS_MAILBOX_1_MASK 0x00020000
-#define BCHP_PCIE_0_INTR2_PCI_MASK_STATUS_MAILBOX_1_SHIFT 17
-#define BCHP_PCIE_0_INTR2_PCI_MASK_STATUS_MAILBOX_1_DEFAULT 0x00000001
-
-/* PCIE_0_INTR2 :: PCI_MASK_STATUS :: MAILBOX_0 [16:16] */
-#define BCHP_PCIE_0_INTR2_PCI_MASK_STATUS_MAILBOX_0_MASK 0x00010000
-#define BCHP_PCIE_0_INTR2_PCI_MASK_STATUS_MAILBOX_0_SHIFT 16
-#define BCHP_PCIE_0_INTR2_PCI_MASK_STATUS_MAILBOX_0_DEFAULT 0x00000001
-
-/* PCIE_0_INTR2 :: PCI_MASK_STATUS :: PCIE_MSTR_FWD_ERR [15:15] */
-#define BCHP_PCIE_0_INTR2_PCI_MASK_STATUS_PCIE_MSTR_FWD_ERR_MASK 0x00008000
-#define BCHP_PCIE_0_INTR2_PCI_MASK_STATUS_PCIE_MSTR_FWD_ERR_SHIFT 15
-#define BCHP_PCIE_0_INTR2_PCI_MASK_STATUS_PCIE_MSTR_FWD_ERR_DEFAULT 0x00000001
-
-/* PCIE_0_INTR2 :: PCI_MASK_STATUS :: PCIE_MSTR_RETRY_TIMEOUT [14:14] */
-#define BCHP_PCIE_0_INTR2_PCI_MASK_STATUS_PCIE_MSTR_RETRY_TIMEOUT_MASK 0x00004000
-#define BCHP_PCIE_0_INTR2_PCI_MASK_STATUS_PCIE_MSTR_RETRY_TIMEOUT_SHIFT 14
-#define BCHP_PCIE_0_INTR2_PCI_MASK_STATUS_PCIE_MSTR_RETRY_TIMEOUT_DEFAULT 0x00000001
-
-/* PCIE_0_INTR2 :: PCI_MASK_STATUS :: PCIE_MSTR_CA_ATTN [13:13] */
-#define BCHP_PCIE_0_INTR2_PCI_MASK_STATUS_PCIE_MSTR_CA_ATTN_MASK 0x00002000
-#define BCHP_PCIE_0_INTR2_PCI_MASK_STATUS_PCIE_MSTR_CA_ATTN_SHIFT 13
-#define BCHP_PCIE_0_INTR2_PCI_MASK_STATUS_PCIE_MSTR_CA_ATTN_DEFAULT 0x00000001
-
-/* PCIE_0_INTR2 :: PCI_MASK_STATUS :: PCIE_MSTR_UR_ATTN [12:12] */
-#define BCHP_PCIE_0_INTR2_PCI_MASK_STATUS_PCIE_MSTR_UR_ATTN_MASK 0x00001000
-#define BCHP_PCIE_0_INTR2_PCI_MASK_STATUS_PCIE_MSTR_UR_ATTN_SHIFT 12
-#define BCHP_PCIE_0_INTR2_PCI_MASK_STATUS_PCIE_MSTR_UR_ATTN_DEFAULT 0x00000001
-
-/* PCIE_0_INTR2 :: PCI_MASK_STATUS :: UNASSIGNED_11 [11:11] */
-#define BCHP_PCIE_0_INTR2_PCI_MASK_STATUS_UNASSIGNED_11_MASK 0x00000800
-#define BCHP_PCIE_0_INTR2_PCI_MASK_STATUS_UNASSIGNED_11_SHIFT 11
-#define BCHP_PCIE_0_INTR2_PCI_MASK_STATUS_UNASSIGNED_11_DEFAULT 0x00000001
-
-/* PCIE_0_INTR2 :: PCI_MASK_STATUS :: UNASSIGNED_10 [10:10] */
-#define BCHP_PCIE_0_INTR2_PCI_MASK_STATUS_UNASSIGNED_10_MASK 0x00000400
-#define BCHP_PCIE_0_INTR2_PCI_MASK_STATUS_UNASSIGNED_10_SHIFT 10
-#define BCHP_PCIE_0_INTR2_PCI_MASK_STATUS_UNASSIGNED_10_DEFAULT 0x00000001
-
-/* PCIE_0_INTR2 :: PCI_MASK_STATUS :: PCIE_TGT_BAD_ACCESS [09:09] */
-#define BCHP_PCIE_0_INTR2_PCI_MASK_STATUS_PCIE_TGT_BAD_ACCESS_MASK 0x00000200
-#define BCHP_PCIE_0_INTR2_PCI_MASK_STATUS_PCIE_TGT_BAD_ACCESS_SHIFT 9
-#define BCHP_PCIE_0_INTR2_PCI_MASK_STATUS_PCIE_TGT_BAD_ACCESS_DEFAULT 0x00000001
-
-/* PCIE_0_INTR2 :: PCI_MASK_STATUS :: PCIE_TGT_BAD_ADDRESS [08:08] */
-#define BCHP_PCIE_0_INTR2_PCI_MASK_STATUS_PCIE_TGT_BAD_ADDRESS_MASK 0x00000100
-#define BCHP_PCIE_0_INTR2_PCI_MASK_STATUS_PCIE_TGT_BAD_ADDRESS_SHIFT 8
-#define BCHP_PCIE_0_INTR2_PCI_MASK_STATUS_PCIE_TGT_BAD_ADDRESS_DEFAULT 0x00000001
-
-/* PCIE_0_INTR2 :: PCI_MASK_STATUS :: L1_RX_DMA_ERR_INTR [07:07] */
-#define BCHP_PCIE_0_INTR2_PCI_MASK_STATUS_L1_RX_DMA_ERR_INTR_MASK 0x00000080
-#define BCHP_PCIE_0_INTR2_PCI_MASK_STATUS_L1_RX_DMA_ERR_INTR_SHIFT 7
-#define BCHP_PCIE_0_INTR2_PCI_MASK_STATUS_L1_RX_DMA_ERR_INTR_DEFAULT 0x00000001
-
-/* PCIE_0_INTR2 :: PCI_MASK_STATUS :: L1_RX_DMA_DONE_INTR [06:06] */
-#define BCHP_PCIE_0_INTR2_PCI_MASK_STATUS_L1_RX_DMA_DONE_INTR_MASK 0x00000040
-#define BCHP_PCIE_0_INTR2_PCI_MASK_STATUS_L1_RX_DMA_DONE_INTR_SHIFT 6
-#define BCHP_PCIE_0_INTR2_PCI_MASK_STATUS_L1_RX_DMA_DONE_INTR_DEFAULT 0x00000001
-
-/* PCIE_0_INTR2 :: PCI_MASK_STATUS :: L1_TX_DMA_ERR_INTR [05:05] */
-#define BCHP_PCIE_0_INTR2_PCI_MASK_STATUS_L1_TX_DMA_ERR_INTR_MASK 0x00000020
-#define BCHP_PCIE_0_INTR2_PCI_MASK_STATUS_L1_TX_DMA_ERR_INTR_SHIFT 5
-#define BCHP_PCIE_0_INTR2_PCI_MASK_STATUS_L1_TX_DMA_ERR_INTR_DEFAULT 0x00000001
-
-/* PCIE_0_INTR2 :: PCI_MASK_STATUS :: L1_TX_DMA_DONE_INTR [04:04] */
-#define BCHP_PCIE_0_INTR2_PCI_MASK_STATUS_L1_TX_DMA_DONE_INTR_MASK 0x00000010
-#define BCHP_PCIE_0_INTR2_PCI_MASK_STATUS_L1_TX_DMA_DONE_INTR_SHIFT 4
-#define BCHP_PCIE_0_INTR2_PCI_MASK_STATUS_L1_TX_DMA_DONE_INTR_DEFAULT 0x00000001
-
-/* PCIE_0_INTR2 :: PCI_MASK_STATUS :: L0_RX_DMA_ERR_INTR [03:03] */
-#define BCHP_PCIE_0_INTR2_PCI_MASK_STATUS_L0_RX_DMA_ERR_INTR_MASK 0x00000008
-#define BCHP_PCIE_0_INTR2_PCI_MASK_STATUS_L0_RX_DMA_ERR_INTR_SHIFT 3
-#define BCHP_PCIE_0_INTR2_PCI_MASK_STATUS_L0_RX_DMA_ERR_INTR_DEFAULT 0x00000001
-
-/* PCIE_0_INTR2 :: PCI_MASK_STATUS :: L0_RX_DMA_DONE_INTR [02:02] */
-#define BCHP_PCIE_0_INTR2_PCI_MASK_STATUS_L0_RX_DMA_DONE_INTR_MASK 0x00000004
-#define BCHP_PCIE_0_INTR2_PCI_MASK_STATUS_L0_RX_DMA_DONE_INTR_SHIFT 2
-#define BCHP_PCIE_0_INTR2_PCI_MASK_STATUS_L0_RX_DMA_DONE_INTR_DEFAULT 0x00000001
-
-/* PCIE_0_INTR2 :: PCI_MASK_STATUS :: L0_TX_DMA_ERR_INTR [01:01] */
-#define BCHP_PCIE_0_INTR2_PCI_MASK_STATUS_L0_TX_DMA_ERR_INTR_MASK 0x00000002
-#define BCHP_PCIE_0_INTR2_PCI_MASK_STATUS_L0_TX_DMA_ERR_INTR_SHIFT 1
-#define BCHP_PCIE_0_INTR2_PCI_MASK_STATUS_L0_TX_DMA_ERR_INTR_DEFAULT 0x00000001
-
-/* PCIE_0_INTR2 :: PCI_MASK_STATUS :: L0_TX_DMA_DONE_INTR [00:00] */
-#define BCHP_PCIE_0_INTR2_PCI_MASK_STATUS_L0_TX_DMA_DONE_INTR_MASK 0x00000001
-#define BCHP_PCIE_0_INTR2_PCI_MASK_STATUS_L0_TX_DMA_DONE_INTR_SHIFT 0
-#define BCHP_PCIE_0_INTR2_PCI_MASK_STATUS_L0_TX_DMA_DONE_INTR_DEFAULT 0x00000001
-
-/***************************************************************************
- *PCI_MASK_SET - PCI interrupt Mask Set Register
- ***************************************************************************/
-/* PCIE_0_INTR2 :: PCI_MASK_SET :: MSI_INTR07 [31:31] */
-#define BCHP_PCIE_0_INTR2_PCI_MASK_SET_MSI_INTR07_MASK 0x80000000
-#define BCHP_PCIE_0_INTR2_PCI_MASK_SET_MSI_INTR07_SHIFT 31
-#define BCHP_PCIE_0_INTR2_PCI_MASK_SET_MSI_INTR07_DEFAULT 0x00000001
-
-/* PCIE_0_INTR2 :: PCI_MASK_SET :: MSI_INTR06 [30:30] */
-#define BCHP_PCIE_0_INTR2_PCI_MASK_SET_MSI_INTR06_MASK 0x40000000
-#define BCHP_PCIE_0_INTR2_PCI_MASK_SET_MSI_INTR06_SHIFT 30
-#define BCHP_PCIE_0_INTR2_PCI_MASK_SET_MSI_INTR06_DEFAULT 0x00000001
-
-/* PCIE_0_INTR2 :: PCI_MASK_SET :: MSI_INTR05 [29:29] */
-#define BCHP_PCIE_0_INTR2_PCI_MASK_SET_MSI_INTR05_MASK 0x20000000
-#define BCHP_PCIE_0_INTR2_PCI_MASK_SET_MSI_INTR05_SHIFT 29
-#define BCHP_PCIE_0_INTR2_PCI_MASK_SET_MSI_INTR05_DEFAULT 0x00000001
-
-/* PCIE_0_INTR2 :: PCI_MASK_SET :: MSI_INTR04 [28:28] */
-#define BCHP_PCIE_0_INTR2_PCI_MASK_SET_MSI_INTR04_MASK 0x10000000
-#define BCHP_PCIE_0_INTR2_PCI_MASK_SET_MSI_INTR04_SHIFT 28
-#define BCHP_PCIE_0_INTR2_PCI_MASK_SET_MSI_INTR04_DEFAULT 0x00000001
-
-/* PCIE_0_INTR2 :: PCI_MASK_SET :: MSI_INTR03 [27:27] */
-#define BCHP_PCIE_0_INTR2_PCI_MASK_SET_MSI_INTR03_MASK 0x08000000
-#define BCHP_PCIE_0_INTR2_PCI_MASK_SET_MSI_INTR03_SHIFT 27
-#define BCHP_PCIE_0_INTR2_PCI_MASK_SET_MSI_INTR03_DEFAULT 0x00000001
-
-/* PCIE_0_INTR2 :: PCI_MASK_SET :: MSI_INTR02 [26:26] */
-#define BCHP_PCIE_0_INTR2_PCI_MASK_SET_MSI_INTR02_MASK 0x04000000
-#define BCHP_PCIE_0_INTR2_PCI_MASK_SET_MSI_INTR02_SHIFT 26
-#define BCHP_PCIE_0_INTR2_PCI_MASK_SET_MSI_INTR02_DEFAULT 0x00000001
-
-/* PCIE_0_INTR2 :: PCI_MASK_SET :: MSI_INTR01 [25:25] */
-#define BCHP_PCIE_0_INTR2_PCI_MASK_SET_MSI_INTR01_MASK 0x02000000
-#define BCHP_PCIE_0_INTR2_PCI_MASK_SET_MSI_INTR01_SHIFT 25
-#define BCHP_PCIE_0_INTR2_PCI_MASK_SET_MSI_INTR01_DEFAULT 0x00000001
-
-/* PCIE_0_INTR2 :: PCI_MASK_SET :: MSI_INTR00 [24:24] */
-#define BCHP_PCIE_0_INTR2_PCI_MASK_SET_MSI_INTR00_MASK 0x01000000
-#define BCHP_PCIE_0_INTR2_PCI_MASK_SET_MSI_INTR00_SHIFT 24
-#define BCHP_PCIE_0_INTR2_PCI_MASK_SET_MSI_INTR00_DEFAULT 0x00000001
-
-/* PCIE_0_INTR2 :: PCI_MASK_SET :: UNASSIGNED_23 [23:23] */
-#define BCHP_PCIE_0_INTR2_PCI_MASK_SET_UNASSIGNED_23_MASK 0x00800000
-#define BCHP_PCIE_0_INTR2_PCI_MASK_SET_UNASSIGNED_23_SHIFT 23
-#define BCHP_PCIE_0_INTR2_PCI_MASK_SET_UNASSIGNED_23_DEFAULT 0x00000001
-
-/* PCIE_0_INTR2 :: PCI_MASK_SET :: UNASSIGNED_22 [22:22] */
-#define BCHP_PCIE_0_INTR2_PCI_MASK_SET_UNASSIGNED_22_MASK 0x00400000
-#define BCHP_PCIE_0_INTR2_PCI_MASK_SET_UNASSIGNED_22_SHIFT 22
-#define BCHP_PCIE_0_INTR2_PCI_MASK_SET_UNASSIGNED_22_DEFAULT 0x00000001
-
-/* PCIE_0_INTR2 :: PCI_MASK_SET :: UNASSIGNED_21 [21:21] */
-#define BCHP_PCIE_0_INTR2_PCI_MASK_SET_UNASSIGNED_21_MASK 0x00200000
-#define BCHP_PCIE_0_INTR2_PCI_MASK_SET_UNASSIGNED_21_SHIFT 21
-#define BCHP_PCIE_0_INTR2_PCI_MASK_SET_UNASSIGNED_21_DEFAULT 0x00000001
-
-/* PCIE_0_INTR2 :: PCI_MASK_SET :: UNASSIGNED_20 [20:20] */
-#define BCHP_PCIE_0_INTR2_PCI_MASK_SET_UNASSIGNED_20_MASK 0x00100000
-#define BCHP_PCIE_0_INTR2_PCI_MASK_SET_UNASSIGNED_20_SHIFT 20
-#define BCHP_PCIE_0_INTR2_PCI_MASK_SET_UNASSIGNED_20_DEFAULT 0x00000001
-
-/* PCIE_0_INTR2 :: PCI_MASK_SET :: MAILBOX_3 [19:19] */
-#define BCHP_PCIE_0_INTR2_PCI_MASK_SET_MAILBOX_3_MASK 0x00080000
-#define BCHP_PCIE_0_INTR2_PCI_MASK_SET_MAILBOX_3_SHIFT 19
-#define BCHP_PCIE_0_INTR2_PCI_MASK_SET_MAILBOX_3_DEFAULT 0x00000001
-
-/* PCIE_0_INTR2 :: PCI_MASK_SET :: MAILBOX_2 [18:18] */
-#define BCHP_PCIE_0_INTR2_PCI_MASK_SET_MAILBOX_2_MASK 0x00040000
-#define BCHP_PCIE_0_INTR2_PCI_MASK_SET_MAILBOX_2_SHIFT 18
-#define BCHP_PCIE_0_INTR2_PCI_MASK_SET_MAILBOX_2_DEFAULT 0x00000001
-
-/* PCIE_0_INTR2 :: PCI_MASK_SET :: MAILBOX_1 [17:17] */
-#define BCHP_PCIE_0_INTR2_PCI_MASK_SET_MAILBOX_1_MASK 0x00020000
-#define BCHP_PCIE_0_INTR2_PCI_MASK_SET_MAILBOX_1_SHIFT 17
-#define BCHP_PCIE_0_INTR2_PCI_MASK_SET_MAILBOX_1_DEFAULT 0x00000001
-
-/* PCIE_0_INTR2 :: PCI_MASK_SET :: MAILBOX_0 [16:16] */
-#define BCHP_PCIE_0_INTR2_PCI_MASK_SET_MAILBOX_0_MASK 0x00010000
-#define BCHP_PCIE_0_INTR2_PCI_MASK_SET_MAILBOX_0_SHIFT 16
-#define BCHP_PCIE_0_INTR2_PCI_MASK_SET_MAILBOX_0_DEFAULT 0x00000001
-
-/* PCIE_0_INTR2 :: PCI_MASK_SET :: PCIE_MSTR_FWD_ERR [15:15] */
-#define BCHP_PCIE_0_INTR2_PCI_MASK_SET_PCIE_MSTR_FWD_ERR_MASK 0x00008000
-#define BCHP_PCIE_0_INTR2_PCI_MASK_SET_PCIE_MSTR_FWD_ERR_SHIFT 15
-#define BCHP_PCIE_0_INTR2_PCI_MASK_SET_PCIE_MSTR_FWD_ERR_DEFAULT 0x00000001
-
-/* PCIE_0_INTR2 :: PCI_MASK_SET :: PCIE_MSTR_RETRY_TIMEOUT [14:14] */
-#define BCHP_PCIE_0_INTR2_PCI_MASK_SET_PCIE_MSTR_RETRY_TIMEOUT_MASK 0x00004000
-#define BCHP_PCIE_0_INTR2_PCI_MASK_SET_PCIE_MSTR_RETRY_TIMEOUT_SHIFT 14
-#define BCHP_PCIE_0_INTR2_PCI_MASK_SET_PCIE_MSTR_RETRY_TIMEOUT_DEFAULT 0x00000001
-
-/* PCIE_0_INTR2 :: PCI_MASK_SET :: PCIE_MSTR_CA_ATTN [13:13] */
-#define BCHP_PCIE_0_INTR2_PCI_MASK_SET_PCIE_MSTR_CA_ATTN_MASK 0x00002000
-#define BCHP_PCIE_0_INTR2_PCI_MASK_SET_PCIE_MSTR_CA_ATTN_SHIFT 13
-#define BCHP_PCIE_0_INTR2_PCI_MASK_SET_PCIE_MSTR_CA_ATTN_DEFAULT 0x00000001
-
-/* PCIE_0_INTR2 :: PCI_MASK_SET :: PCIE_MSTR_UR_ATTN [12:12] */
-#define BCHP_PCIE_0_INTR2_PCI_MASK_SET_PCIE_MSTR_UR_ATTN_MASK 0x00001000
-#define BCHP_PCIE_0_INTR2_PCI_MASK_SET_PCIE_MSTR_UR_ATTN_SHIFT 12
-#define BCHP_PCIE_0_INTR2_PCI_MASK_SET_PCIE_MSTR_UR_ATTN_DEFAULT 0x00000001
-
-/* PCIE_0_INTR2 :: PCI_MASK_SET :: UNASSIGNED_11 [11:11] */
-#define BCHP_PCIE_0_INTR2_PCI_MASK_SET_UNASSIGNED_11_MASK 0x00000800
-#define BCHP_PCIE_0_INTR2_PCI_MASK_SET_UNASSIGNED_11_SHIFT 11
-#define BCHP_PCIE_0_INTR2_PCI_MASK_SET_UNASSIGNED_11_DEFAULT 0x00000001
-
-/* PCIE_0_INTR2 :: PCI_MASK_SET :: UNASSIGNED_10 [10:10] */
-#define BCHP_PCIE_0_INTR2_PCI_MASK_SET_UNASSIGNED_10_MASK 0x00000400
-#define BCHP_PCIE_0_INTR2_PCI_MASK_SET_UNASSIGNED_10_SHIFT 10
-#define BCHP_PCIE_0_INTR2_PCI_MASK_SET_UNASSIGNED_10_DEFAULT 0x00000001
-
-/* PCIE_0_INTR2 :: PCI_MASK_SET :: PCIE_TGT_BAD_ACCESS [09:09] */
-#define BCHP_PCIE_0_INTR2_PCI_MASK_SET_PCIE_TGT_BAD_ACCESS_MASK 0x00000200
-#define BCHP_PCIE_0_INTR2_PCI_MASK_SET_PCIE_TGT_BAD_ACCESS_SHIFT 9
-#define BCHP_PCIE_0_INTR2_PCI_MASK_SET_PCIE_TGT_BAD_ACCESS_DEFAULT 0x00000001
-
-/* PCIE_0_INTR2 :: PCI_MASK_SET :: PCIE_TGT_BAD_ADDRESS [08:08] */
-#define BCHP_PCIE_0_INTR2_PCI_MASK_SET_PCIE_TGT_BAD_ADDRESS_MASK 0x00000100
-#define BCHP_PCIE_0_INTR2_PCI_MASK_SET_PCIE_TGT_BAD_ADDRESS_SHIFT 8
-#define BCHP_PCIE_0_INTR2_PCI_MASK_SET_PCIE_TGT_BAD_ADDRESS_DEFAULT 0x00000001
-
-/* PCIE_0_INTR2 :: PCI_MASK_SET :: L1_RX_DMA_ERR_INTR [07:07] */
-#define BCHP_PCIE_0_INTR2_PCI_MASK_SET_L1_RX_DMA_ERR_INTR_MASK 0x00000080
-#define BCHP_PCIE_0_INTR2_PCI_MASK_SET_L1_RX_DMA_ERR_INTR_SHIFT 7
-#define BCHP_PCIE_0_INTR2_PCI_MASK_SET_L1_RX_DMA_ERR_INTR_DEFAULT 0x00000001
-
-/* PCIE_0_INTR2 :: PCI_MASK_SET :: L1_RX_DMA_DONE_INTR [06:06] */
-#define BCHP_PCIE_0_INTR2_PCI_MASK_SET_L1_RX_DMA_DONE_INTR_MASK 0x00000040
-#define BCHP_PCIE_0_INTR2_PCI_MASK_SET_L1_RX_DMA_DONE_INTR_SHIFT 6
-#define BCHP_PCIE_0_INTR2_PCI_MASK_SET_L1_RX_DMA_DONE_INTR_DEFAULT 0x00000001
-
-/* PCIE_0_INTR2 :: PCI_MASK_SET :: L1_TX_DMA_ERR_INTR [05:05] */
-#define BCHP_PCIE_0_INTR2_PCI_MASK_SET_L1_TX_DMA_ERR_INTR_MASK 0x00000020
-#define BCHP_PCIE_0_INTR2_PCI_MASK_SET_L1_TX_DMA_ERR_INTR_SHIFT 5
-#define BCHP_PCIE_0_INTR2_PCI_MASK_SET_L1_TX_DMA_ERR_INTR_DEFAULT 0x00000001
-
-/* PCIE_0_INTR2 :: PCI_MASK_SET :: L1_TX_DMA_DONE_INTR [04:04] */
-#define BCHP_PCIE_0_INTR2_PCI_MASK_SET_L1_TX_DMA_DONE_INTR_MASK 0x00000010
-#define BCHP_PCIE_0_INTR2_PCI_MASK_SET_L1_TX_DMA_DONE_INTR_SHIFT 4
-#define BCHP_PCIE_0_INTR2_PCI_MASK_SET_L1_TX_DMA_DONE_INTR_DEFAULT 0x00000001
-
-/* PCIE_0_INTR2 :: PCI_MASK_SET :: L0_RX_DMA_ERR_INTR [03:03] */
-#define BCHP_PCIE_0_INTR2_PCI_MASK_SET_L0_RX_DMA_ERR_INTR_MASK 0x00000008
-#define BCHP_PCIE_0_INTR2_PCI_MASK_SET_L0_RX_DMA_ERR_INTR_SHIFT 3
-#define BCHP_PCIE_0_INTR2_PCI_MASK_SET_L0_RX_DMA_ERR_INTR_DEFAULT 0x00000001
-
-/* PCIE_0_INTR2 :: PCI_MASK_SET :: L0_RX_DMA_DONE_INTR [02:02] */
-#define BCHP_PCIE_0_INTR2_PCI_MASK_SET_L0_RX_DMA_DONE_INTR_MASK 0x00000004
-#define BCHP_PCIE_0_INTR2_PCI_MASK_SET_L0_RX_DMA_DONE_INTR_SHIFT 2
-#define BCHP_PCIE_0_INTR2_PCI_MASK_SET_L0_RX_DMA_DONE_INTR_DEFAULT 0x00000001
-
-/* PCIE_0_INTR2 :: PCI_MASK_SET :: L0_TX_DMA_ERR_INTR [01:01] */
-#define BCHP_PCIE_0_INTR2_PCI_MASK_SET_L0_TX_DMA_ERR_INTR_MASK 0x00000002
-#define BCHP_PCIE_0_INTR2_PCI_MASK_SET_L0_TX_DMA_ERR_INTR_SHIFT 1
-#define BCHP_PCIE_0_INTR2_PCI_MASK_SET_L0_TX_DMA_ERR_INTR_DEFAULT 0x00000001
-
-/* PCIE_0_INTR2 :: PCI_MASK_SET :: L0_TX_DMA_DONE_INTR [00:00] */
-#define BCHP_PCIE_0_INTR2_PCI_MASK_SET_L0_TX_DMA_DONE_INTR_MASK 0x00000001
-#define BCHP_PCIE_0_INTR2_PCI_MASK_SET_L0_TX_DMA_DONE_INTR_SHIFT 0
-#define BCHP_PCIE_0_INTR2_PCI_MASK_SET_L0_TX_DMA_DONE_INTR_DEFAULT 0x00000001
-
-/***************************************************************************
- *PCI_MASK_CLEAR - PCI interrupt Mask Clear Register
- ***************************************************************************/
-/* PCIE_0_INTR2 :: PCI_MASK_CLEAR :: MSI_INTR07 [31:31] */
-#define BCHP_PCIE_0_INTR2_PCI_MASK_CLEAR_MSI_INTR07_MASK 0x80000000
-#define BCHP_PCIE_0_INTR2_PCI_MASK_CLEAR_MSI_INTR07_SHIFT 31
-#define BCHP_PCIE_0_INTR2_PCI_MASK_CLEAR_MSI_INTR07_DEFAULT 0x00000001
-
-/* PCIE_0_INTR2 :: PCI_MASK_CLEAR :: MSI_INTR06 [30:30] */
-#define BCHP_PCIE_0_INTR2_PCI_MASK_CLEAR_MSI_INTR06_MASK 0x40000000
-#define BCHP_PCIE_0_INTR2_PCI_MASK_CLEAR_MSI_INTR06_SHIFT 30
-#define BCHP_PCIE_0_INTR2_PCI_MASK_CLEAR_MSI_INTR06_DEFAULT 0x00000001
-
-/* PCIE_0_INTR2 :: PCI_MASK_CLEAR :: MSI_INTR05 [29:29] */
-#define BCHP_PCIE_0_INTR2_PCI_MASK_CLEAR_MSI_INTR05_MASK 0x20000000
-#define BCHP_PCIE_0_INTR2_PCI_MASK_CLEAR_MSI_INTR05_SHIFT 29
-#define BCHP_PCIE_0_INTR2_PCI_MASK_CLEAR_MSI_INTR05_DEFAULT 0x00000001
-
-/* PCIE_0_INTR2 :: PCI_MASK_CLEAR :: MSI_INTR04 [28:28] */
-#define BCHP_PCIE_0_INTR2_PCI_MASK_CLEAR_MSI_INTR04_MASK 0x10000000
-#define BCHP_PCIE_0_INTR2_PCI_MASK_CLEAR_MSI_INTR04_SHIFT 28
-#define BCHP_PCIE_0_INTR2_PCI_MASK_CLEAR_MSI_INTR04_DEFAULT 0x00000001
-
-/* PCIE_0_INTR2 :: PCI_MASK_CLEAR :: MSI_INTR03 [27:27] */
-#define BCHP_PCIE_0_INTR2_PCI_MASK_CLEAR_MSI_INTR03_MASK 0x08000000
-#define BCHP_PCIE_0_INTR2_PCI_MASK_CLEAR_MSI_INTR03_SHIFT 27
-#define BCHP_PCIE_0_INTR2_PCI_MASK_CLEAR_MSI_INTR03_DEFAULT 0x00000001
-
-/* PCIE_0_INTR2 :: PCI_MASK_CLEAR :: MSI_INTR02 [26:26] */
-#define BCHP_PCIE_0_INTR2_PCI_MASK_CLEAR_MSI_INTR02_MASK 0x04000000
-#define BCHP_PCIE_0_INTR2_PCI_MASK_CLEAR_MSI_INTR02_SHIFT 26
-#define BCHP_PCIE_0_INTR2_PCI_MASK_CLEAR_MSI_INTR02_DEFAULT 0x00000001
-
-/* PCIE_0_INTR2 :: PCI_MASK_CLEAR :: MSI_INTR01 [25:25] */
-#define BCHP_PCIE_0_INTR2_PCI_MASK_CLEAR_MSI_INTR01_MASK 0x02000000
-#define BCHP_PCIE_0_INTR2_PCI_MASK_CLEAR_MSI_INTR01_SHIFT 25
-#define BCHP_PCIE_0_INTR2_PCI_MASK_CLEAR_MSI_INTR01_DEFAULT 0x00000001
-
-/* PCIE_0_INTR2 :: PCI_MASK_CLEAR :: MSI_INTR00 [24:24] */
-#define BCHP_PCIE_0_INTR2_PCI_MASK_CLEAR_MSI_INTR00_MASK 0x01000000
-#define BCHP_PCIE_0_INTR2_PCI_MASK_CLEAR_MSI_INTR00_SHIFT 24
-#define BCHP_PCIE_0_INTR2_PCI_MASK_CLEAR_MSI_INTR00_DEFAULT 0x00000001
-
-/* PCIE_0_INTR2 :: PCI_MASK_CLEAR :: UNASSIGNED_23 [23:23] */
-#define BCHP_PCIE_0_INTR2_PCI_MASK_CLEAR_UNASSIGNED_23_MASK 0x00800000
-#define BCHP_PCIE_0_INTR2_PCI_MASK_CLEAR_UNASSIGNED_23_SHIFT 23
-#define BCHP_PCIE_0_INTR2_PCI_MASK_CLEAR_UNASSIGNED_23_DEFAULT 0x00000001
-
-/* PCIE_0_INTR2 :: PCI_MASK_CLEAR :: UNASSIGNED_22 [22:22] */
-#define BCHP_PCIE_0_INTR2_PCI_MASK_CLEAR_UNASSIGNED_22_MASK 0x00400000
-#define BCHP_PCIE_0_INTR2_PCI_MASK_CLEAR_UNASSIGNED_22_SHIFT 22
-#define BCHP_PCIE_0_INTR2_PCI_MASK_CLEAR_UNASSIGNED_22_DEFAULT 0x00000001
-
-/* PCIE_0_INTR2 :: PCI_MASK_CLEAR :: UNASSIGNED_21 [21:21] */
-#define BCHP_PCIE_0_INTR2_PCI_MASK_CLEAR_UNASSIGNED_21_MASK 0x00200000
-#define BCHP_PCIE_0_INTR2_PCI_MASK_CLEAR_UNASSIGNED_21_SHIFT 21
-#define BCHP_PCIE_0_INTR2_PCI_MASK_CLEAR_UNASSIGNED_21_DEFAULT 0x00000001
-
-/* PCIE_0_INTR2 :: PCI_MASK_CLEAR :: UNASSIGNED_20 [20:20] */
-#define BCHP_PCIE_0_INTR2_PCI_MASK_CLEAR_UNASSIGNED_20_MASK 0x00100000
-#define BCHP_PCIE_0_INTR2_PCI_MASK_CLEAR_UNASSIGNED_20_SHIFT 20
-#define BCHP_PCIE_0_INTR2_PCI_MASK_CLEAR_UNASSIGNED_20_DEFAULT 0x00000001
-
-/* PCIE_0_INTR2 :: PCI_MASK_CLEAR :: MAILBOX_3 [19:19] */
-#define BCHP_PCIE_0_INTR2_PCI_MASK_CLEAR_MAILBOX_3_MASK 0x00080000
-#define BCHP_PCIE_0_INTR2_PCI_MASK_CLEAR_MAILBOX_3_SHIFT 19
-#define BCHP_PCIE_0_INTR2_PCI_MASK_CLEAR_MAILBOX_3_DEFAULT 0x00000001
-
-/* PCIE_0_INTR2 :: PCI_MASK_CLEAR :: MAILBOX_2 [18:18] */
-#define BCHP_PCIE_0_INTR2_PCI_MASK_CLEAR_MAILBOX_2_MASK 0x00040000
-#define BCHP_PCIE_0_INTR2_PCI_MASK_CLEAR_MAILBOX_2_SHIFT 18
-#define BCHP_PCIE_0_INTR2_PCI_MASK_CLEAR_MAILBOX_2_DEFAULT 0x00000001
-
-/* PCIE_0_INTR2 :: PCI_MASK_CLEAR :: MAILBOX_1 [17:17] */
-#define BCHP_PCIE_0_INTR2_PCI_MASK_CLEAR_MAILBOX_1_MASK 0x00020000
-#define BCHP_PCIE_0_INTR2_PCI_MASK_CLEAR_MAILBOX_1_SHIFT 17
-#define BCHP_PCIE_0_INTR2_PCI_MASK_CLEAR_MAILBOX_1_DEFAULT 0x00000001
-
-/* PCIE_0_INTR2 :: PCI_MASK_CLEAR :: MAILBOX_0 [16:16] */
-#define BCHP_PCIE_0_INTR2_PCI_MASK_CLEAR_MAILBOX_0_MASK 0x00010000
-#define BCHP_PCIE_0_INTR2_PCI_MASK_CLEAR_MAILBOX_0_SHIFT 16
-#define BCHP_PCIE_0_INTR2_PCI_MASK_CLEAR_MAILBOX_0_DEFAULT 0x00000001
-
-/* PCIE_0_INTR2 :: PCI_MASK_CLEAR :: PCIE_MSTR_FWD_ERR [15:15] */
-#define BCHP_PCIE_0_INTR2_PCI_MASK_CLEAR_PCIE_MSTR_FWD_ERR_MASK 0x00008000
-#define BCHP_PCIE_0_INTR2_PCI_MASK_CLEAR_PCIE_MSTR_FWD_ERR_SHIFT 15
-#define BCHP_PCIE_0_INTR2_PCI_MASK_CLEAR_PCIE_MSTR_FWD_ERR_DEFAULT 0x00000001
-
-/* PCIE_0_INTR2 :: PCI_MASK_CLEAR :: PCIE_MSTR_RETRY_TIMEOUT [14:14] */
-#define BCHP_PCIE_0_INTR2_PCI_MASK_CLEAR_PCIE_MSTR_RETRY_TIMEOUT_MASK 0x00004000
-#define BCHP_PCIE_0_INTR2_PCI_MASK_CLEAR_PCIE_MSTR_RETRY_TIMEOUT_SHIFT 14
-#define BCHP_PCIE_0_INTR2_PCI_MASK_CLEAR_PCIE_MSTR_RETRY_TIMEOUT_DEFAULT 0x00000001
-
-/* PCIE_0_INTR2 :: PCI_MASK_CLEAR :: PCIE_MSTR_CA_ATTN [13:13] */
-#define BCHP_PCIE_0_INTR2_PCI_MASK_CLEAR_PCIE_MSTR_CA_ATTN_MASK 0x00002000
-#define BCHP_PCIE_0_INTR2_PCI_MASK_CLEAR_PCIE_MSTR_CA_ATTN_SHIFT 13
-#define BCHP_PCIE_0_INTR2_PCI_MASK_CLEAR_PCIE_MSTR_CA_ATTN_DEFAULT 0x00000001
-
-/* PCIE_0_INTR2 :: PCI_MASK_CLEAR :: PCIE_MSTR_UR_ATTN [12:12] */
-#define BCHP_PCIE_0_INTR2_PCI_MASK_CLEAR_PCIE_MSTR_UR_ATTN_MASK 0x00001000
-#define BCHP_PCIE_0_INTR2_PCI_MASK_CLEAR_PCIE_MSTR_UR_ATTN_SHIFT 12
-#define BCHP_PCIE_0_INTR2_PCI_MASK_CLEAR_PCIE_MSTR_UR_ATTN_DEFAULT 0x00000001
-
-/* PCIE_0_INTR2 :: PCI_MASK_CLEAR :: UNASSIGNED_11 [11:11] */
-#define BCHP_PCIE_0_INTR2_PCI_MASK_CLEAR_UNASSIGNED_11_MASK 0x00000800
-#define BCHP_PCIE_0_INTR2_PCI_MASK_CLEAR_UNASSIGNED_11_SHIFT 11
-#define BCHP_PCIE_0_INTR2_PCI_MASK_CLEAR_UNASSIGNED_11_DEFAULT 0x00000001
-
-/* PCIE_0_INTR2 :: PCI_MASK_CLEAR :: UNASSIGNED_10 [10:10] */
-#define BCHP_PCIE_0_INTR2_PCI_MASK_CLEAR_UNASSIGNED_10_MASK 0x00000400
-#define BCHP_PCIE_0_INTR2_PCI_MASK_CLEAR_UNASSIGNED_10_SHIFT 10
-#define BCHP_PCIE_0_INTR2_PCI_MASK_CLEAR_UNASSIGNED_10_DEFAULT 0x00000001
-
-/* PCIE_0_INTR2 :: PCI_MASK_CLEAR :: PCIE_TGT_BAD_ACCESS [09:09] */
-#define BCHP_PCIE_0_INTR2_PCI_MASK_CLEAR_PCIE_TGT_BAD_ACCESS_MASK 0x00000200
-#define BCHP_PCIE_0_INTR2_PCI_MASK_CLEAR_PCIE_TGT_BAD_ACCESS_SHIFT 9
-#define BCHP_PCIE_0_INTR2_PCI_MASK_CLEAR_PCIE_TGT_BAD_ACCESS_DEFAULT 0x00000001
-
-/* PCIE_0_INTR2 :: PCI_MASK_CLEAR :: PCIE_TGT_BAD_ADDRESS [08:08] */
-#define BCHP_PCIE_0_INTR2_PCI_MASK_CLEAR_PCIE_TGT_BAD_ADDRESS_MASK 0x00000100
-#define BCHP_PCIE_0_INTR2_PCI_MASK_CLEAR_PCIE_TGT_BAD_ADDRESS_SHIFT 8
-#define BCHP_PCIE_0_INTR2_PCI_MASK_CLEAR_PCIE_TGT_BAD_ADDRESS_DEFAULT 0x00000001
-
-/* PCIE_0_INTR2 :: PCI_MASK_CLEAR :: L1_RX_DMA_ERR_INTR [07:07] */
-#define BCHP_PCIE_0_INTR2_PCI_MASK_CLEAR_L1_RX_DMA_ERR_INTR_MASK 0x00000080
-#define BCHP_PCIE_0_INTR2_PCI_MASK_CLEAR_L1_RX_DMA_ERR_INTR_SHIFT 7
-#define BCHP_PCIE_0_INTR2_PCI_MASK_CLEAR_L1_RX_DMA_ERR_INTR_DEFAULT 0x00000001
-
-/* PCIE_0_INTR2 :: PCI_MASK_CLEAR :: L1_RX_DMA_DONE_INTR [06:06] */
-#define BCHP_PCIE_0_INTR2_PCI_MASK_CLEAR_L1_RX_DMA_DONE_INTR_MASK 0x00000040
-#define BCHP_PCIE_0_INTR2_PCI_MASK_CLEAR_L1_RX_DMA_DONE_INTR_SHIFT 6
-#define BCHP_PCIE_0_INTR2_PCI_MASK_CLEAR_L1_RX_DMA_DONE_INTR_DEFAULT 0x00000001
-
-/* PCIE_0_INTR2 :: PCI_MASK_CLEAR :: L1_TX_DMA_ERR_INTR [05:05] */
-#define BCHP_PCIE_0_INTR2_PCI_MASK_CLEAR_L1_TX_DMA_ERR_INTR_MASK 0x00000020
-#define BCHP_PCIE_0_INTR2_PCI_MASK_CLEAR_L1_TX_DMA_ERR_INTR_SHIFT 5
-#define BCHP_PCIE_0_INTR2_PCI_MASK_CLEAR_L1_TX_DMA_ERR_INTR_DEFAULT 0x00000001
-
-/* PCIE_0_INTR2 :: PCI_MASK_CLEAR :: L1_TX_DMA_DONE_INTR [04:04] */
-#define BCHP_PCIE_0_INTR2_PCI_MASK_CLEAR_L1_TX_DMA_DONE_INTR_MASK 0x00000010
-#define BCHP_PCIE_0_INTR2_PCI_MASK_CLEAR_L1_TX_DMA_DONE_INTR_SHIFT 4
-#define BCHP_PCIE_0_INTR2_PCI_MASK_CLEAR_L1_TX_DMA_DONE_INTR_DEFAULT 0x00000001
-
-/* PCIE_0_INTR2 :: PCI_MASK_CLEAR :: L0_RX_DMA_ERR_INTR [03:03] */
-#define BCHP_PCIE_0_INTR2_PCI_MASK_CLEAR_L0_RX_DMA_ERR_INTR_MASK 0x00000008
-#define BCHP_PCIE_0_INTR2_PCI_MASK_CLEAR_L0_RX_DMA_ERR_INTR_SHIFT 3
-#define BCHP_PCIE_0_INTR2_PCI_MASK_CLEAR_L0_RX_DMA_ERR_INTR_DEFAULT 0x00000001
-
-/* PCIE_0_INTR2 :: PCI_MASK_CLEAR :: L0_RX_DMA_DONE_INTR [02:02] */
-#define BCHP_PCIE_0_INTR2_PCI_MASK_CLEAR_L0_RX_DMA_DONE_INTR_MASK 0x00000004
-#define BCHP_PCIE_0_INTR2_PCI_MASK_CLEAR_L0_RX_DMA_DONE_INTR_SHIFT 2
-#define BCHP_PCIE_0_INTR2_PCI_MASK_CLEAR_L0_RX_DMA_DONE_INTR_DEFAULT 0x00000001
-
-/* PCIE_0_INTR2 :: PCI_MASK_CLEAR :: L0_TX_DMA_ERR_INTR [01:01] */
-#define BCHP_PCIE_0_INTR2_PCI_MASK_CLEAR_L0_TX_DMA_ERR_INTR_MASK 0x00000002
-#define BCHP_PCIE_0_INTR2_PCI_MASK_CLEAR_L0_TX_DMA_ERR_INTR_SHIFT 1
-#define BCHP_PCIE_0_INTR2_PCI_MASK_CLEAR_L0_TX_DMA_ERR_INTR_DEFAULT 0x00000001
-
-/* PCIE_0_INTR2 :: PCI_MASK_CLEAR :: L0_TX_DMA_DONE_INTR [00:00] */
-#define BCHP_PCIE_0_INTR2_PCI_MASK_CLEAR_L0_TX_DMA_DONE_INTR_MASK 0x00000001
-#define BCHP_PCIE_0_INTR2_PCI_MASK_CLEAR_L0_TX_DMA_DONE_INTR_SHIFT 0
-#define BCHP_PCIE_0_INTR2_PCI_MASK_CLEAR_L0_TX_DMA_DONE_INTR_DEFAULT 0x00000001
-
-#endif /* #ifndef BCHP_PCIE_0_INTR2_H__ */
-
-/* End of File */
diff --git a/include/linux/brcmstb/7366b0/bchp_pcie_0_misc.h b/include/linux/brcmstb/7366b0/bchp_pcie_0_misc.h
deleted file mode 100644
index cd1da94..0000000
--- a/include/linux/brcmstb/7366b0/bchp_pcie_0_misc.h
+++ /dev/null
@@ -1,995 +0,0 @@
-/***************************************************************************
- * Copyright (c) 1999-2014, Broadcom Corporation
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
- *
- * Module Description:
- * DO NOT EDIT THIS FILE DIRECTLY
- *
- * This module was generated magically with RDB from a source description
- * file. You must edit the source file for changes to be made to this file.
- *
- *
- * Date: Generated on Thu Apr 24 03:08:57 2014
- * Full Compile MD5 Checksum 1af2c2cf28828ece5496e1312aac0166
- * (minus title and desc)
- * MD5 Checksum 3203ffce85e3fc9a10f84123e54057b0
- *
- * Compiled with: RDB Utility combo_header.pl
- * RDB Parser 3.0
- * unknown unknown
- * Perl Interpreter 5.008008
- * Operating System linux
- *
- * Revision History:
- *
- * $brcm_Log: $
- *
- ***************************************************************************/
-
-#ifndef BCHP_PCIE_0_MISC_H__
-#define BCHP_PCIE_0_MISC_H__
-
-/***************************************************************************
- *PCIE_0_MISC - PCI-E Miscellaneous Registers
- ***************************************************************************/
-#define BCHP_PCIE_0_MISC_RESET_CTRL 0x00474000 /* Reset Control Register */
-#define BCHP_PCIE_0_MISC_ECO_CTRL_CORE 0x00474004 /* ECO Core Reset Control Register */
-#define BCHP_PCIE_0_MISC_MISC_CTRL 0x00474008 /* MISC Control Register */
-#define BCHP_PCIE_0_MISC_CPU_2_PCIE_MEM_WIN0_LO 0x0047400c /* CPU to PCIe Memory Window 0 Low */
-#define BCHP_PCIE_0_MISC_CPU_2_PCIE_MEM_WIN0_HI 0x00474010 /* CPU to PCIe Memory Window 0 High */
-#define BCHP_PCIE_0_MISC_CPU_2_PCIE_MEM_WIN1_LO 0x00474014 /* CPU to PCIe Memory Window 1 Low */
-#define BCHP_PCIE_0_MISC_CPU_2_PCIE_MEM_WIN1_HI 0x00474018 /* CPU to PCIe Memory Window 1 High */
-#define BCHP_PCIE_0_MISC_CPU_2_PCIE_MEM_WIN2_LO 0x0047401c /* CPU to PCIe Memory Window 2 Low */
-#define BCHP_PCIE_0_MISC_CPU_2_PCIE_MEM_WIN2_HI 0x00474020 /* CPU to PCIe Memory Window 2 High */
-#define BCHP_PCIE_0_MISC_CPU_2_PCIE_MEM_WIN3_LO 0x00474024 /* CPU to PCIe Memory Window 3 Low */
-#define BCHP_PCIE_0_MISC_CPU_2_PCIE_MEM_WIN3_HI 0x00474028 /* CPU to PCIe Memory Window 3 High */
-#define BCHP_PCIE_0_MISC_RC_BAR1_CONFIG_LO 0x0047402c /* RC BAR1 Configuration Low Register */
-#define BCHP_PCIE_0_MISC_RC_BAR1_CONFIG_HI 0x00474030 /* RC BAR1 Configuration High Register */
-#define BCHP_PCIE_0_MISC_RC_BAR2_CONFIG_LO 0x00474034 /* RC BAR2 Configuration Low Register */
-#define BCHP_PCIE_0_MISC_RC_BAR2_CONFIG_HI 0x00474038 /* RC BAR2 Configuration High Register */
-#define BCHP_PCIE_0_MISC_RC_BAR3_CONFIG_LO 0x0047403c /* RC BAR3 Configuration Low Register */
-#define BCHP_PCIE_0_MISC_RC_BAR3_CONFIG_HI 0x00474040 /* RC BAR3 Configuration High Register */
-#define BCHP_PCIE_0_MISC_MSI_BAR_CONFIG_LO 0x00474044 /* Message Signaled Interrupt Base Address Low Register */
-#define BCHP_PCIE_0_MISC_MSI_BAR_CONFIG_HI 0x00474048 /* Message Signaled Interrupt Base Address High Register */
-#define BCHP_PCIE_0_MISC_MSI_DATA_CONFIG 0x0047404c /* Message Signaled Interrupt Data Configuration Register */
-#define BCHP_PCIE_0_MISC_RC_BAD_ADDRESS_LO 0x00474050 /* RC Bad Address Register Low */
-#define BCHP_PCIE_0_MISC_RC_BAD_ADDRESS_HI 0x00474054 /* RC Bad Address Register High */
-#define BCHP_PCIE_0_MISC_RC_BAD_DATA 0x00474058 /* RC Bad Data Register */
-#define BCHP_PCIE_0_MISC_RC_CONFIG_RETRY_TIMEOUT 0x0047405c /* RC Configuration Retry Timeout Register */
-#define BCHP_PCIE_0_MISC_EOI_CTRL 0x00474060 /* End of Interrupt Control Register */
-#define BCHP_PCIE_0_MISC_PCIE_CTRL 0x00474064 /* PCIe Control */
-#define BCHP_PCIE_0_MISC_PCIE_STATUS 0x00474068 /* PCIe Status */
-#define BCHP_PCIE_0_MISC_REVISION 0x0047406c /* PCIe Revision */
-#define BCHP_PCIE_0_MISC_CPU_2_PCIE_MEM_WIN0_BASE_LIMIT 0x00474070 /* CPU to PCIe Memory Window 0 base/limit */
-#define BCHP_PCIE_0_MISC_CPU_2_PCIE_MEM_WIN1_BASE_LIMIT 0x00474074 /* CPU to PCIe Memory Window 1 base/limit */
-#define BCHP_PCIE_0_MISC_CPU_2_PCIE_MEM_WIN2_BASE_LIMIT 0x00474078 /* CPU to PCIe Memory Window 2 base/limit */
-#define BCHP_PCIE_0_MISC_CPU_2_PCIE_MEM_WIN3_BASE_LIMIT 0x0047407c /* CPU to PCIe Memory Window 3 base/limit */
-#define BCHP_PCIE_0_MISC_CPU_2_PCIE_MEM_WIN0_BASE_HI 0x00474080 /* CPU to PCIe Memory Window 0 base high */
-#define BCHP_PCIE_0_MISC_CPU_2_PCIE_MEM_WIN0_LIMIT_HI 0x00474084 /* CPU to PCIe Memory Window 0 limit high */
-#define BCHP_PCIE_0_MISC_CPU_2_PCIE_MEM_WIN1_BASE_HI 0x00474088 /* CPU to PCIe Memory Window 1 base high */
-#define BCHP_PCIE_0_MISC_CPU_2_PCIE_MEM_WIN1_LIMIT_HI 0x0047408c /* CPU to PCIe Memory Window 1 limit high */
-#define BCHP_PCIE_0_MISC_CPU_2_PCIE_MEM_WIN2_BASE_HI 0x00474090 /* CPU to PCIe Memory Window 2 base high */
-#define BCHP_PCIE_0_MISC_CPU_2_PCIE_MEM_WIN2_LIMIT_HI 0x00474094 /* CPU to PCIe Memory Window 2 limit high */
-#define BCHP_PCIE_0_MISC_CPU_2_PCIE_MEM_WIN3_BASE_HI 0x00474098 /* CPU to PCIe Memory Window 3 base high */
-#define BCHP_PCIE_0_MISC_CPU_2_PCIE_MEM_WIN3_LIMIT_HI 0x0047409c /* CPU to PCIe Memory Window 3 limit high */
-#define BCHP_PCIE_0_MISC_MISC_CTRL_1 0x004740a0 /* MISC Control Register 1 */
-#define BCHP_PCIE_0_MISC_UBUS_CTRL 0x004740a4 /* Unused */
-#define BCHP_PCIE_0_MISC_UBUS_TIMEOUT 0x004740a8 /* Unused */
-#define BCHP_PCIE_0_MISC_UBUS_BAR1_CONFIG_REMAP 0x004740ac /* Unused */
-#define BCHP_PCIE_0_MISC_UBUS_BAR1_CONFIG_REMAP_HI 0x004740b0 /* Unused */
-#define BCHP_PCIE_0_MISC_UBUS_BAR2_CONFIG_REMAP 0x004740b4 /* Unused */
-#define BCHP_PCIE_0_MISC_UBUS_BAR2_CONFIG_REMAP_HI 0x004740b8 /* Unused */
-#define BCHP_PCIE_0_MISC_UBUS_BAR3_CONFIG_REMAP 0x004740bc /* Unused */
-#define BCHP_PCIE_0_MISC_UBUS_BAR3_CONFIG_REMAP_HI 0x004740c0 /* Unused */
-#define BCHP_PCIE_0_MISC_UBUS_STATUS 0x004740c4 /* Unused */
-#define BCHP_PCIE_0_MISC_SCB_STATUS 0x004740c8 /* SCB Status */
-
-/***************************************************************************
- *RESET_CTRL - Reset Control Register
- ***************************************************************************/
-/* PCIE_0_MISC :: RESET_CTRL :: reserved0 [31:01] */
-#define BCHP_PCIE_0_MISC_RESET_CTRL_reserved0_MASK 0xfffffffe
-#define BCHP_PCIE_0_MISC_RESET_CTRL_reserved0_SHIFT 1
-
-/* PCIE_0_MISC :: RESET_CTRL :: CORE_RESET [00:00] */
-#define BCHP_PCIE_0_MISC_RESET_CTRL_CORE_RESET_MASK 0x00000001
-#define BCHP_PCIE_0_MISC_RESET_CTRL_CORE_RESET_SHIFT 0
-#define BCHP_PCIE_0_MISC_RESET_CTRL_CORE_RESET_DEFAULT 0x00000000
-
-/***************************************************************************
- *ECO_CTRL_CORE - ECO Core Reset Control Register
- ***************************************************************************/
-/* PCIE_0_MISC :: ECO_CTRL_CORE :: reserved0 [31:16] */
-#define BCHP_PCIE_0_MISC_ECO_CTRL_CORE_reserved0_MASK 0xffff0000
-#define BCHP_PCIE_0_MISC_ECO_CTRL_CORE_reserved0_SHIFT 16
-
-/* PCIE_0_MISC :: ECO_CTRL_CORE :: ECO_CORE_RST_N [15:00] */
-#define BCHP_PCIE_0_MISC_ECO_CTRL_CORE_ECO_CORE_RST_N_MASK 0x0000ffff
-#define BCHP_PCIE_0_MISC_ECO_CTRL_CORE_ECO_CORE_RST_N_SHIFT 0
-#define BCHP_PCIE_0_MISC_ECO_CTRL_CORE_ECO_CORE_RST_N_DEFAULT 0x00000000
-
-/***************************************************************************
- *MISC_CTRL - MISC Control Register
- ***************************************************************************/
-/* PCIE_0_MISC :: MISC_CTRL :: SCB0_SIZE [31:27] */
-#define BCHP_PCIE_0_MISC_MISC_CTRL_SCB0_SIZE_MASK 0xf8000000
-#define BCHP_PCIE_0_MISC_MISC_CTRL_SCB0_SIZE_SHIFT 27
-#define BCHP_PCIE_0_MISC_MISC_CTRL_SCB0_SIZE_DEFAULT 0x00000000
-
-/* PCIE_0_MISC :: MISC_CTRL :: SCB1_SIZE [26:22] */
-#define BCHP_PCIE_0_MISC_MISC_CTRL_SCB1_SIZE_MASK 0x07c00000
-#define BCHP_PCIE_0_MISC_MISC_CTRL_SCB1_SIZE_SHIFT 22
-#define BCHP_PCIE_0_MISC_MISC_CTRL_SCB1_SIZE_DEFAULT 0x00000000
-
-/* PCIE_0_MISC :: MISC_CTRL :: MAX_BURST_SIZE [21:20] */
-#define BCHP_PCIE_0_MISC_MISC_CTRL_MAX_BURST_SIZE_MASK 0x00300000
-#define BCHP_PCIE_0_MISC_MISC_CTRL_MAX_BURST_SIZE_SHIFT 20
-#define BCHP_PCIE_0_MISC_MISC_CTRL_MAX_BURST_SIZE_DEFAULT 0x00000000
-
-/* PCIE_0_MISC :: MISC_CTRL :: BURST_ALIGN [19:19] */
-#define BCHP_PCIE_0_MISC_MISC_CTRL_BURST_ALIGN_MASK 0x00080000
-#define BCHP_PCIE_0_MISC_MISC_CTRL_BURST_ALIGN_SHIFT 19
-#define BCHP_PCIE_0_MISC_MISC_CTRL_BURST_ALIGN_DEFAULT 0x00000000
-
-/* PCIE_0_MISC :: MISC_CTRL :: TBD_OPTION_18 [18:18] */
-#define BCHP_PCIE_0_MISC_MISC_CTRL_TBD_OPTION_18_MASK 0x00040000
-#define BCHP_PCIE_0_MISC_MISC_CTRL_TBD_OPTION_18_SHIFT 18
-#define BCHP_PCIE_0_MISC_MISC_CTRL_TBD_OPTION_18_DEFAULT 0x00000000
-
-/* PCIE_0_MISC :: MISC_CTRL :: CSR_CFG_MODE [17:17] */
-#define BCHP_PCIE_0_MISC_MISC_CTRL_CSR_CFG_MODE_MASK 0x00020000
-#define BCHP_PCIE_0_MISC_MISC_CTRL_CSR_CFG_MODE_SHIFT 17
-#define BCHP_PCIE_0_MISC_MISC_CTRL_CSR_CFG_MODE_DEFAULT 0x00000000
-
-/* PCIE_0_MISC :: MISC_CTRL :: CSR_CFG_RETRY_EN [16:16] */
-#define BCHP_PCIE_0_MISC_MISC_CTRL_CSR_CFG_RETRY_EN_MASK 0x00010000
-#define BCHP_PCIE_0_MISC_MISC_CTRL_CSR_CFG_RETRY_EN_SHIFT 16
-#define BCHP_PCIE_0_MISC_MISC_CTRL_CSR_CFG_RETRY_EN_DEFAULT 0x00000000
-
-/* PCIE_0_MISC :: MISC_CTRL :: TBD_OPTION_15 [15:15] */
-#define BCHP_PCIE_0_MISC_MISC_CTRL_TBD_OPTION_15_MASK 0x00008000
-#define BCHP_PCIE_0_MISC_MISC_CTRL_TBD_OPTION_15_SHIFT 15
-#define BCHP_PCIE_0_MISC_MISC_CTRL_TBD_OPTION_15_DEFAULT 0x00000000
-
-/* PCIE_0_MISC :: MISC_CTRL :: TBD_OPTION_14 [14:14] */
-#define BCHP_PCIE_0_MISC_MISC_CTRL_TBD_OPTION_14_MASK 0x00004000
-#define BCHP_PCIE_0_MISC_MISC_CTRL_TBD_OPTION_14_SHIFT 14
-#define BCHP_PCIE_0_MISC_MISC_CTRL_TBD_OPTION_14_DEFAULT 0x00000000
-
-/* PCIE_0_MISC :: MISC_CTRL :: CFG_READ_UR_MODE [13:13] */
-#define BCHP_PCIE_0_MISC_MISC_CTRL_CFG_READ_UR_MODE_MASK 0x00002000
-#define BCHP_PCIE_0_MISC_MISC_CTRL_CFG_READ_UR_MODE_SHIFT 13
-#define BCHP_PCIE_0_MISC_MISC_CTRL_CFG_READ_UR_MODE_DEFAULT 0x00000000
-
-/* PCIE_0_MISC :: MISC_CTRL :: SCB_ACCESS_EN [12:12] */
-#define BCHP_PCIE_0_MISC_MISC_CTRL_SCB_ACCESS_EN_MASK 0x00001000
-#define BCHP_PCIE_0_MISC_MISC_CTRL_SCB_ACCESS_EN_SHIFT 12
-#define BCHP_PCIE_0_MISC_MISC_CTRL_SCB_ACCESS_EN_DEFAULT 0x00000000
-
-/* PCIE_0_MISC :: MISC_CTRL :: PCIE_IN_WR_COMBINE [11:11] */
-#define BCHP_PCIE_0_MISC_MISC_CTRL_PCIE_IN_WR_COMBINE_MASK 0x00000800
-#define BCHP_PCIE_0_MISC_MISC_CTRL_PCIE_IN_WR_COMBINE_SHIFT 11
-#define BCHP_PCIE_0_MISC_MISC_CTRL_PCIE_IN_WR_COMBINE_DEFAULT 0x00000000
-
-/* PCIE_0_MISC :: MISC_CTRL :: PCIE_RCB_MPS_MODE [10:10] */
-#define BCHP_PCIE_0_MISC_MISC_CTRL_PCIE_RCB_MPS_MODE_MASK 0x00000400
-#define BCHP_PCIE_0_MISC_MISC_CTRL_PCIE_RCB_MPS_MODE_SHIFT 10
-#define BCHP_PCIE_0_MISC_MISC_CTRL_PCIE_RCB_MPS_MODE_DEFAULT 0x00000000
-
-/* PCIE_0_MISC :: MISC_CTRL :: DESC_PRIORITY_EN [09:09] */
-#define BCHP_PCIE_0_MISC_MISC_CTRL_DESC_PRIORITY_EN_MASK 0x00000200
-#define BCHP_PCIE_0_MISC_MISC_CTRL_DESC_PRIORITY_EN_SHIFT 9
-#define BCHP_PCIE_0_MISC_MISC_CTRL_DESC_PRIORITY_EN_DEFAULT 0x00000000
-
-/* PCIE_0_MISC :: MISC_CTRL :: READ_PRIORITY_EN [08:08] */
-#define BCHP_PCIE_0_MISC_MISC_CTRL_READ_PRIORITY_EN_MASK 0x00000100
-#define BCHP_PCIE_0_MISC_MISC_CTRL_READ_PRIORITY_EN_SHIFT 8
-#define BCHP_PCIE_0_MISC_MISC_CTRL_READ_PRIORITY_EN_DEFAULT 0x00000000
-
-/* PCIE_0_MISC :: MISC_CTRL :: PCIE_RCB_64B_MODE [07:07] */
-#define BCHP_PCIE_0_MISC_MISC_CTRL_PCIE_RCB_64B_MODE_MASK 0x00000080
-#define BCHP_PCIE_0_MISC_MISC_CTRL_PCIE_RCB_64B_MODE_SHIFT 7
-#define BCHP_PCIE_0_MISC_MISC_CTRL_PCIE_RCB_64B_MODE_DEFAULT 0x00000000
-
-/* PCIE_0_MISC :: MISC_CTRL :: PCIE_OUT_CPL_RO [06:06] */
-#define BCHP_PCIE_0_MISC_MISC_CTRL_PCIE_OUT_CPL_RO_MASK 0x00000040
-#define BCHP_PCIE_0_MISC_MISC_CTRL_PCIE_OUT_CPL_RO_SHIFT 6
-#define BCHP_PCIE_0_MISC_MISC_CTRL_PCIE_OUT_CPL_RO_DEFAULT 0x00000000
-
-/* PCIE_0_MISC :: MISC_CTRL :: PCIE_IN_CPL_RO [05:05] */
-#define BCHP_PCIE_0_MISC_MISC_CTRL_PCIE_IN_CPL_RO_MASK 0x00000020
-#define BCHP_PCIE_0_MISC_MISC_CTRL_PCIE_IN_CPL_RO_SHIFT 5
-#define BCHP_PCIE_0_MISC_MISC_CTRL_PCIE_IN_CPL_RO_DEFAULT 0x00000000
-
-/* PCIE_0_MISC :: MISC_CTRL :: SCB2_SIZE [04:00] */
-#define BCHP_PCIE_0_MISC_MISC_CTRL_SCB2_SIZE_MASK 0x0000001f
-#define BCHP_PCIE_0_MISC_MISC_CTRL_SCB2_SIZE_SHIFT 0
-#define BCHP_PCIE_0_MISC_MISC_CTRL_SCB2_SIZE_DEFAULT 0x00000000
-
-/***************************************************************************
- *CPU_2_PCIE_MEM_WIN0_LO - CPU to PCIe Memory Window 0 Low
- ***************************************************************************/
-/* PCIE_0_MISC :: CPU_2_PCIE_MEM_WIN0_LO :: BASE_ADDR [31:20] */
-#define BCHP_PCIE_0_MISC_CPU_2_PCIE_MEM_WIN0_LO_BASE_ADDR_MASK 0xfff00000
-#define BCHP_PCIE_0_MISC_CPU_2_PCIE_MEM_WIN0_LO_BASE_ADDR_SHIFT 20
-#define BCHP_PCIE_0_MISC_CPU_2_PCIE_MEM_WIN0_LO_BASE_ADDR_DEFAULT 0x00000000
-
-/* PCIE_0_MISC :: CPU_2_PCIE_MEM_WIN0_LO :: reserved0 [19:02] */
-#define BCHP_PCIE_0_MISC_CPU_2_PCIE_MEM_WIN0_LO_reserved0_MASK 0x000ffffc
-#define BCHP_PCIE_0_MISC_CPU_2_PCIE_MEM_WIN0_LO_reserved0_SHIFT 2
-
-/* PCIE_0_MISC :: CPU_2_PCIE_MEM_WIN0_LO :: ENDIAN_MODE [01:00] */
-#define BCHP_PCIE_0_MISC_CPU_2_PCIE_MEM_WIN0_LO_ENDIAN_MODE_MASK 0x00000003
-#define BCHP_PCIE_0_MISC_CPU_2_PCIE_MEM_WIN0_LO_ENDIAN_MODE_SHIFT 0
-#define BCHP_PCIE_0_MISC_CPU_2_PCIE_MEM_WIN0_LO_ENDIAN_MODE_DEFAULT 0x00000000
-
-/***************************************************************************
- *CPU_2_PCIE_MEM_WIN0_HI - CPU to PCIe Memory Window 0 High
- ***************************************************************************/
-/* PCIE_0_MISC :: CPU_2_PCIE_MEM_WIN0_HI :: BASE_ADDR [31:00] */
-#define BCHP_PCIE_0_MISC_CPU_2_PCIE_MEM_WIN0_HI_BASE_ADDR_MASK 0xffffffff
-#define BCHP_PCIE_0_MISC_CPU_2_PCIE_MEM_WIN0_HI_BASE_ADDR_SHIFT 0
-#define BCHP_PCIE_0_MISC_CPU_2_PCIE_MEM_WIN0_HI_BASE_ADDR_DEFAULT 0x00000000
-
-/***************************************************************************
- *CPU_2_PCIE_MEM_WIN1_LO - CPU to PCIe Memory Window 1 Low
- ***************************************************************************/
-/* PCIE_0_MISC :: CPU_2_PCIE_MEM_WIN1_LO :: BASE_ADDR [31:20] */
-#define BCHP_PCIE_0_MISC_CPU_2_PCIE_MEM_WIN1_LO_BASE_ADDR_MASK 0xfff00000
-#define BCHP_PCIE_0_MISC_CPU_2_PCIE_MEM_WIN1_LO_BASE_ADDR_SHIFT 20
-#define BCHP_PCIE_0_MISC_CPU_2_PCIE_MEM_WIN1_LO_BASE_ADDR_DEFAULT 0x00000000
-
-/* PCIE_0_MISC :: CPU_2_PCIE_MEM_WIN1_LO :: reserved0 [19:02] */
-#define BCHP_PCIE_0_MISC_CPU_2_PCIE_MEM_WIN1_LO_reserved0_MASK 0x000ffffc
-#define BCHP_PCIE_0_MISC_CPU_2_PCIE_MEM_WIN1_LO_reserved0_SHIFT 2
-
-/* PCIE_0_MISC :: CPU_2_PCIE_MEM_WIN1_LO :: ENDIAN_MODE [01:00] */
-#define BCHP_PCIE_0_MISC_CPU_2_PCIE_MEM_WIN1_LO_ENDIAN_MODE_MASK 0x00000003
-#define BCHP_PCIE_0_MISC_CPU_2_PCIE_MEM_WIN1_LO_ENDIAN_MODE_SHIFT 0
-#define BCHP_PCIE_0_MISC_CPU_2_PCIE_MEM_WIN1_LO_ENDIAN_MODE_DEFAULT 0x00000000
-
-/***************************************************************************
- *CPU_2_PCIE_MEM_WIN1_HI - CPU to PCIe Memory Window 1 High
- ***************************************************************************/
-/* PCIE_0_MISC :: CPU_2_PCIE_MEM_WIN1_HI :: BASE_ADDR [31:00] */
-#define BCHP_PCIE_0_MISC_CPU_2_PCIE_MEM_WIN1_HI_BASE_ADDR_MASK 0xffffffff
-#define BCHP_PCIE_0_MISC_CPU_2_PCIE_MEM_WIN1_HI_BASE_ADDR_SHIFT 0
-#define BCHP_PCIE_0_MISC_CPU_2_PCIE_MEM_WIN1_HI_BASE_ADDR_DEFAULT 0x00000000
-
-/***************************************************************************
- *CPU_2_PCIE_MEM_WIN2_LO - CPU to PCIe Memory Window 2 Low
- ***************************************************************************/
-/* PCIE_0_MISC :: CPU_2_PCIE_MEM_WIN2_LO :: BASE_ADDR [31:20] */
-#define BCHP_PCIE_0_MISC_CPU_2_PCIE_MEM_WIN2_LO_BASE_ADDR_MASK 0xfff00000
-#define BCHP_PCIE_0_MISC_CPU_2_PCIE_MEM_WIN2_LO_BASE_ADDR_SHIFT 20
-#define BCHP_PCIE_0_MISC_CPU_2_PCIE_MEM_WIN2_LO_BASE_ADDR_DEFAULT 0x00000000
-
-/* PCIE_0_MISC :: CPU_2_PCIE_MEM_WIN2_LO :: reserved0 [19:02] */
-#define BCHP_PCIE_0_MISC_CPU_2_PCIE_MEM_WIN2_LO_reserved0_MASK 0x000ffffc
-#define BCHP_PCIE_0_MISC_CPU_2_PCIE_MEM_WIN2_LO_reserved0_SHIFT 2
-
-/* PCIE_0_MISC :: CPU_2_PCIE_MEM_WIN2_LO :: ENDIAN_MODE [01:00] */
-#define BCHP_PCIE_0_MISC_CPU_2_PCIE_MEM_WIN2_LO_ENDIAN_MODE_MASK 0x00000003
-#define BCHP_PCIE_0_MISC_CPU_2_PCIE_MEM_WIN2_LO_ENDIAN_MODE_SHIFT 0
-#define BCHP_PCIE_0_MISC_CPU_2_PCIE_MEM_WIN2_LO_ENDIAN_MODE_DEFAULT 0x00000000
-
-/***************************************************************************
- *CPU_2_PCIE_MEM_WIN2_HI - CPU to PCIe Memory Window 2 High
- ***************************************************************************/
-/* PCIE_0_MISC :: CPU_2_PCIE_MEM_WIN2_HI :: BASE_ADDR [31:00] */
-#define BCHP_PCIE_0_MISC_CPU_2_PCIE_MEM_WIN2_HI_BASE_ADDR_MASK 0xffffffff
-#define BCHP_PCIE_0_MISC_CPU_2_PCIE_MEM_WIN2_HI_BASE_ADDR_SHIFT 0
-#define BCHP_PCIE_0_MISC_CPU_2_PCIE_MEM_WIN2_HI_BASE_ADDR_DEFAULT 0x00000000
-
-/***************************************************************************
- *CPU_2_PCIE_MEM_WIN3_LO - CPU to PCIe Memory Window 3 Low
- ***************************************************************************/
-/* PCIE_0_MISC :: CPU_2_PCIE_MEM_WIN3_LO :: BASE_ADDR [31:20] */
-#define BCHP_PCIE_0_MISC_CPU_2_PCIE_MEM_WIN3_LO_BASE_ADDR_MASK 0xfff00000
-#define BCHP_PCIE_0_MISC_CPU_2_PCIE_MEM_WIN3_LO_BASE_ADDR_SHIFT 20
-#define BCHP_PCIE_0_MISC_CPU_2_PCIE_MEM_WIN3_LO_BASE_ADDR_DEFAULT 0x00000000
-
-/* PCIE_0_MISC :: CPU_2_PCIE_MEM_WIN3_LO :: reserved0 [19:02] */
-#define BCHP_PCIE_0_MISC_CPU_2_PCIE_MEM_WIN3_LO_reserved0_MASK 0x000ffffc
-#define BCHP_PCIE_0_MISC_CPU_2_PCIE_MEM_WIN3_LO_reserved0_SHIFT 2
-
-/* PCIE_0_MISC :: CPU_2_PCIE_MEM_WIN3_LO :: ENDIAN_MODE [01:00] */
-#define BCHP_PCIE_0_MISC_CPU_2_PCIE_MEM_WIN3_LO_ENDIAN_MODE_MASK 0x00000003
-#define BCHP_PCIE_0_MISC_CPU_2_PCIE_MEM_WIN3_LO_ENDIAN_MODE_SHIFT 0
-#define BCHP_PCIE_0_MISC_CPU_2_PCIE_MEM_WIN3_LO_ENDIAN_MODE_DEFAULT 0x00000000
-
-/***************************************************************************
- *CPU_2_PCIE_MEM_WIN3_HI - CPU to PCIe Memory Window 3 High
- ***************************************************************************/
-/* PCIE_0_MISC :: CPU_2_PCIE_MEM_WIN3_HI :: BASE_ADDR [31:00] */
-#define BCHP_PCIE_0_MISC_CPU_2_PCIE_MEM_WIN3_HI_BASE_ADDR_MASK 0xffffffff
-#define BCHP_PCIE_0_MISC_CPU_2_PCIE_MEM_WIN3_HI_BASE_ADDR_SHIFT 0
-#define BCHP_PCIE_0_MISC_CPU_2_PCIE_MEM_WIN3_HI_BASE_ADDR_DEFAULT 0x00000000
-
-/***************************************************************************
- *RC_BAR1_CONFIG_LO - RC BAR1 Configuration Low Register
- ***************************************************************************/
-/* PCIE_0_MISC :: RC_BAR1_CONFIG_LO :: MATCH_ADDRESS [31:12] */
-#define BCHP_PCIE_0_MISC_RC_BAR1_CONFIG_LO_MATCH_ADDRESS_MASK 0xfffff000
-#define BCHP_PCIE_0_MISC_RC_BAR1_CONFIG_LO_MATCH_ADDRESS_SHIFT 12
-#define BCHP_PCIE_0_MISC_RC_BAR1_CONFIG_LO_MATCH_ADDRESS_DEFAULT 0x00000000
-
-/* PCIE_0_MISC :: RC_BAR1_CONFIG_LO :: reserved0 [11:05] */
-#define BCHP_PCIE_0_MISC_RC_BAR1_CONFIG_LO_reserved0_MASK 0x00000fe0
-#define BCHP_PCIE_0_MISC_RC_BAR1_CONFIG_LO_reserved0_SHIFT 5
-
-/* PCIE_0_MISC :: RC_BAR1_CONFIG_LO :: SIZE [04:00] */
-#define BCHP_PCIE_0_MISC_RC_BAR1_CONFIG_LO_SIZE_MASK 0x0000001f
-#define BCHP_PCIE_0_MISC_RC_BAR1_CONFIG_LO_SIZE_SHIFT 0
-#define BCHP_PCIE_0_MISC_RC_BAR1_CONFIG_LO_SIZE_DEFAULT 0x00000000
-
-/***************************************************************************
- *RC_BAR1_CONFIG_HI - RC BAR1 Configuration High Register
- ***************************************************************************/
-/* PCIE_0_MISC :: RC_BAR1_CONFIG_HI :: MATCH_ADDRESS [31:00] */
-#define BCHP_PCIE_0_MISC_RC_BAR1_CONFIG_HI_MATCH_ADDRESS_MASK 0xffffffff
-#define BCHP_PCIE_0_MISC_RC_BAR1_CONFIG_HI_MATCH_ADDRESS_SHIFT 0
-#define BCHP_PCIE_0_MISC_RC_BAR1_CONFIG_HI_MATCH_ADDRESS_DEFAULT 0x00000000
-
-/***************************************************************************
- *RC_BAR2_CONFIG_LO - RC BAR2 Configuration Low Register
- ***************************************************************************/
-/* PCIE_0_MISC :: RC_BAR2_CONFIG_LO :: MATCH_ADDRESS [31:12] */
-#define BCHP_PCIE_0_MISC_RC_BAR2_CONFIG_LO_MATCH_ADDRESS_MASK 0xfffff000
-#define BCHP_PCIE_0_MISC_RC_BAR2_CONFIG_LO_MATCH_ADDRESS_SHIFT 12
-#define BCHP_PCIE_0_MISC_RC_BAR2_CONFIG_LO_MATCH_ADDRESS_DEFAULT 0x00000000
-
-/* PCIE_0_MISC :: RC_BAR2_CONFIG_LO :: reserved0 [11:05] */
-#define BCHP_PCIE_0_MISC_RC_BAR2_CONFIG_LO_reserved0_MASK 0x00000fe0
-#define BCHP_PCIE_0_MISC_RC_BAR2_CONFIG_LO_reserved0_SHIFT 5
-
-/* PCIE_0_MISC :: RC_BAR2_CONFIG_LO :: SIZE [04:00] */
-#define BCHP_PCIE_0_MISC_RC_BAR2_CONFIG_LO_SIZE_MASK 0x0000001f
-#define BCHP_PCIE_0_MISC_RC_BAR2_CONFIG_LO_SIZE_SHIFT 0
-#define BCHP_PCIE_0_MISC_RC_BAR2_CONFIG_LO_SIZE_DEFAULT 0x00000000
-
-/***************************************************************************
- *RC_BAR2_CONFIG_HI - RC BAR2 Configuration High Register
- ***************************************************************************/
-/* PCIE_0_MISC :: RC_BAR2_CONFIG_HI :: MATCH_ADDRESS [31:00] */
-#define BCHP_PCIE_0_MISC_RC_BAR2_CONFIG_HI_MATCH_ADDRESS_MASK 0xffffffff
-#define BCHP_PCIE_0_MISC_RC_BAR2_CONFIG_HI_MATCH_ADDRESS_SHIFT 0
-#define BCHP_PCIE_0_MISC_RC_BAR2_CONFIG_HI_MATCH_ADDRESS_DEFAULT 0x00000000
-
-/***************************************************************************
- *RC_BAR3_CONFIG_LO - RC BAR3 Configuration Low Register
- ***************************************************************************/
-/* PCIE_0_MISC :: RC_BAR3_CONFIG_LO :: MATCH_ADDRESS [31:12] */
-#define BCHP_PCIE_0_MISC_RC_BAR3_CONFIG_LO_MATCH_ADDRESS_MASK 0xfffff000
-#define BCHP_PCIE_0_MISC_RC_BAR3_CONFIG_LO_MATCH_ADDRESS_SHIFT 12
-#define BCHP_PCIE_0_MISC_RC_BAR3_CONFIG_LO_MATCH_ADDRESS_DEFAULT 0x00000000
-
-/* PCIE_0_MISC :: RC_BAR3_CONFIG_LO :: reserved0 [11:05] */
-#define BCHP_PCIE_0_MISC_RC_BAR3_CONFIG_LO_reserved0_MASK 0x00000fe0
-#define BCHP_PCIE_0_MISC_RC_BAR3_CONFIG_LO_reserved0_SHIFT 5
-
-/* PCIE_0_MISC :: RC_BAR3_CONFIG_LO :: SIZE [04:00] */
-#define BCHP_PCIE_0_MISC_RC_BAR3_CONFIG_LO_SIZE_MASK 0x0000001f
-#define BCHP_PCIE_0_MISC_RC_BAR3_CONFIG_LO_SIZE_SHIFT 0
-#define BCHP_PCIE_0_MISC_RC_BAR3_CONFIG_LO_SIZE_DEFAULT 0x00000000
-
-/***************************************************************************
- *RC_BAR3_CONFIG_HI - RC BAR3 Configuration High Register
- ***************************************************************************/
-/* PCIE_0_MISC :: RC_BAR3_CONFIG_HI :: MATCH_ADDRESS [31:00] */
-#define BCHP_PCIE_0_MISC_RC_BAR3_CONFIG_HI_MATCH_ADDRESS_MASK 0xffffffff
-#define BCHP_PCIE_0_MISC_RC_BAR3_CONFIG_HI_MATCH_ADDRESS_SHIFT 0
-#define BCHP_PCIE_0_MISC_RC_BAR3_CONFIG_HI_MATCH_ADDRESS_DEFAULT 0x00000000
-
-/***************************************************************************
- *MSI_BAR_CONFIG_LO - Message Signaled Interrupt Base Address Low Register
- ***************************************************************************/
-/* PCIE_0_MISC :: MSI_BAR_CONFIG_LO :: MATCH_ADDRESS [31:02] */
-#define BCHP_PCIE_0_MISC_MSI_BAR_CONFIG_LO_MATCH_ADDRESS_MASK 0xfffffffc
-#define BCHP_PCIE_0_MISC_MSI_BAR_CONFIG_LO_MATCH_ADDRESS_SHIFT 2
-#define BCHP_PCIE_0_MISC_MSI_BAR_CONFIG_LO_MATCH_ADDRESS_DEFAULT 0x00000000
-
-/* PCIE_0_MISC :: MSI_BAR_CONFIG_LO :: reserved0 [01:01] */
-#define BCHP_PCIE_0_MISC_MSI_BAR_CONFIG_LO_reserved0_MASK 0x00000002
-#define BCHP_PCIE_0_MISC_MSI_BAR_CONFIG_LO_reserved0_SHIFT 1
-
-/* PCIE_0_MISC :: MSI_BAR_CONFIG_LO :: ENABLE [00:00] */
-#define BCHP_PCIE_0_MISC_MSI_BAR_CONFIG_LO_ENABLE_MASK 0x00000001
-#define BCHP_PCIE_0_MISC_MSI_BAR_CONFIG_LO_ENABLE_SHIFT 0
-#define BCHP_PCIE_0_MISC_MSI_BAR_CONFIG_LO_ENABLE_DEFAULT 0x00000000
-
-/***************************************************************************
- *MSI_BAR_CONFIG_HI - Message Signaled Interrupt Base Address High Register
- ***************************************************************************/
-/* PCIE_0_MISC :: MSI_BAR_CONFIG_HI :: MATCH_ADDRESS [31:00] */
-#define BCHP_PCIE_0_MISC_MSI_BAR_CONFIG_HI_MATCH_ADDRESS_MASK 0xffffffff
-#define BCHP_PCIE_0_MISC_MSI_BAR_CONFIG_HI_MATCH_ADDRESS_SHIFT 0
-#define BCHP_PCIE_0_MISC_MSI_BAR_CONFIG_HI_MATCH_ADDRESS_DEFAULT 0x00000000
-
-/***************************************************************************
- *MSI_DATA_CONFIG - Message Signaled Interrupt Data Configuration Register
- ***************************************************************************/
-/* PCIE_0_MISC :: MSI_DATA_CONFIG :: MASK [31:16] */
-#define BCHP_PCIE_0_MISC_MSI_DATA_CONFIG_MASK_MASK 0xffff0000
-#define BCHP_PCIE_0_MISC_MSI_DATA_CONFIG_MASK_SHIFT 16
-#define BCHP_PCIE_0_MISC_MSI_DATA_CONFIG_MASK_DEFAULT 0x00000000
-
-/* PCIE_0_MISC :: MSI_DATA_CONFIG :: DATA [15:00] */
-#define BCHP_PCIE_0_MISC_MSI_DATA_CONFIG_DATA_MASK 0x0000ffff
-#define BCHP_PCIE_0_MISC_MSI_DATA_CONFIG_DATA_SHIFT 0
-#define BCHP_PCIE_0_MISC_MSI_DATA_CONFIG_DATA_DEFAULT 0x00000000
-
-/***************************************************************************
- *RC_BAD_ADDRESS_LO - RC Bad Address Register Low
- ***************************************************************************/
-/* PCIE_0_MISC :: RC_BAD_ADDRESS_LO :: ADDRESS [31:02] */
-#define BCHP_PCIE_0_MISC_RC_BAD_ADDRESS_LO_ADDRESS_MASK 0xfffffffc
-#define BCHP_PCIE_0_MISC_RC_BAD_ADDRESS_LO_ADDRESS_SHIFT 2
-#define BCHP_PCIE_0_MISC_RC_BAD_ADDRESS_LO_ADDRESS_DEFAULT 0x00000000
-
-/* PCIE_0_MISC :: RC_BAD_ADDRESS_LO :: reserved0 [01:01] */
-#define BCHP_PCIE_0_MISC_RC_BAD_ADDRESS_LO_reserved0_MASK 0x00000002
-#define BCHP_PCIE_0_MISC_RC_BAD_ADDRESS_LO_reserved0_SHIFT 1
-
-/* PCIE_0_MISC :: RC_BAD_ADDRESS_LO :: VALID [00:00] */
-#define BCHP_PCIE_0_MISC_RC_BAD_ADDRESS_LO_VALID_MASK 0x00000001
-#define BCHP_PCIE_0_MISC_RC_BAD_ADDRESS_LO_VALID_SHIFT 0
-#define BCHP_PCIE_0_MISC_RC_BAD_ADDRESS_LO_VALID_DEFAULT 0x00000000
-
-/***************************************************************************
- *RC_BAD_ADDRESS_HI - RC Bad Address Register High
- ***************************************************************************/
-/* PCIE_0_MISC :: RC_BAD_ADDRESS_HI :: ADDRESS [31:00] */
-#define BCHP_PCIE_0_MISC_RC_BAD_ADDRESS_HI_ADDRESS_MASK 0xffffffff
-#define BCHP_PCIE_0_MISC_RC_BAD_ADDRESS_HI_ADDRESS_SHIFT 0
-#define BCHP_PCIE_0_MISC_RC_BAD_ADDRESS_HI_ADDRESS_DEFAULT 0x00000000
-
-/***************************************************************************
- *RC_BAD_DATA - RC Bad Data Register
- ***************************************************************************/
-/* PCIE_0_MISC :: RC_BAD_DATA :: DATA [31:00] */
-#define BCHP_PCIE_0_MISC_RC_BAD_DATA_DATA_MASK 0xffffffff
-#define BCHP_PCIE_0_MISC_RC_BAD_DATA_DATA_SHIFT 0
-#define BCHP_PCIE_0_MISC_RC_BAD_DATA_DATA_DEFAULT 0x00000000
-
-/***************************************************************************
- *RC_CONFIG_RETRY_TIMEOUT - RC Configuration Retry Timeout Register
- ***************************************************************************/
-/* PCIE_0_MISC :: RC_CONFIG_RETRY_TIMEOUT :: TIMER_VALUE [31:00] */
-#define BCHP_PCIE_0_MISC_RC_CONFIG_RETRY_TIMEOUT_TIMER_VALUE_MASK 0xffffffff
-#define BCHP_PCIE_0_MISC_RC_CONFIG_RETRY_TIMEOUT_TIMER_VALUE_SHIFT 0
-#define BCHP_PCIE_0_MISC_RC_CONFIG_RETRY_TIMEOUT_TIMER_VALUE_DEFAULT 0x00000000
-
-/***************************************************************************
- *EOI_CTRL - End of Interrupt Control Register
- ***************************************************************************/
-/* PCIE_0_MISC :: EOI_CTRL :: reserved0 [31:01] */
-#define BCHP_PCIE_0_MISC_EOI_CTRL_reserved0_MASK 0xfffffffe
-#define BCHP_PCIE_0_MISC_EOI_CTRL_reserved0_SHIFT 1
-
-/* PCIE_0_MISC :: EOI_CTRL :: EOI [00:00] */
-#define BCHP_PCIE_0_MISC_EOI_CTRL_EOI_MASK 0x00000001
-#define BCHP_PCIE_0_MISC_EOI_CTRL_EOI_SHIFT 0
-#define BCHP_PCIE_0_MISC_EOI_CTRL_EOI_DEFAULT 0x00000000
-
-/***************************************************************************
- *PCIE_CTRL - PCIe Control
- ***************************************************************************/
-/* PCIE_0_MISC :: PCIE_CTRL :: reserved0 [31:02] */
-#define BCHP_PCIE_0_MISC_PCIE_CTRL_reserved0_MASK 0xfffffffc
-#define BCHP_PCIE_0_MISC_PCIE_CTRL_reserved0_SHIFT 2
-
-/* PCIE_0_MISC :: PCIE_CTRL :: PCIE_PME_REQUEST [01:01] */
-#define BCHP_PCIE_0_MISC_PCIE_CTRL_PCIE_PME_REQUEST_MASK 0x00000002
-#define BCHP_PCIE_0_MISC_PCIE_CTRL_PCIE_PME_REQUEST_SHIFT 1
-#define BCHP_PCIE_0_MISC_PCIE_CTRL_PCIE_PME_REQUEST_DEFAULT 0x00000000
-
-/* PCIE_0_MISC :: PCIE_CTRL :: PCIE_L23_REQUEST [00:00] */
-#define BCHP_PCIE_0_MISC_PCIE_CTRL_PCIE_L23_REQUEST_MASK 0x00000001
-#define BCHP_PCIE_0_MISC_PCIE_CTRL_PCIE_L23_REQUEST_SHIFT 0
-#define BCHP_PCIE_0_MISC_PCIE_CTRL_PCIE_L23_REQUEST_DEFAULT 0x00000000
-
-/***************************************************************************
- *PCIE_STATUS - PCIe Status
- ***************************************************************************/
-/* PCIE_0_MISC :: PCIE_STATUS :: reserved0 [31:13] */
-#define BCHP_PCIE_0_MISC_PCIE_STATUS_reserved0_MASK 0xffffe000
-#define BCHP_PCIE_0_MISC_PCIE_STATUS_reserved0_SHIFT 13
-
-/* PCIE_0_MISC :: PCIE_STATUS :: PCIE_SSC_STATUS [12:12] */
-#define BCHP_PCIE_0_MISC_PCIE_STATUS_PCIE_SSC_STATUS_MASK 0x00001000
-#define BCHP_PCIE_0_MISC_PCIE_STATUS_PCIE_SSC_STATUS_SHIFT 12
-#define BCHP_PCIE_0_MISC_PCIE_STATUS_PCIE_SSC_STATUS_DEFAULT 0x00000000
-
-/* PCIE_0_MISC :: PCIE_STATUS :: PCIE_PM_STATE [11:10] */
-#define BCHP_PCIE_0_MISC_PCIE_STATUS_PCIE_PM_STATE_MASK 0x00000c00
-#define BCHP_PCIE_0_MISC_PCIE_STATUS_PCIE_PM_STATE_SHIFT 10
-#define BCHP_PCIE_0_MISC_PCIE_STATUS_PCIE_PM_STATE_DEFAULT 0x00000000
-
-/* PCIE_0_MISC :: PCIE_STATUS :: PCIE_WAKE [09:09] */
-#define BCHP_PCIE_0_MISC_PCIE_STATUS_PCIE_WAKE_MASK 0x00000200
-#define BCHP_PCIE_0_MISC_PCIE_STATUS_PCIE_WAKE_SHIFT 9
-#define BCHP_PCIE_0_MISC_PCIE_STATUS_PCIE_WAKE_DEFAULT 0x00000000
-
-/* PCIE_0_MISC :: PCIE_STATUS :: PCIE_PME_EVENT [08:08] */
-#define BCHP_PCIE_0_MISC_PCIE_STATUS_PCIE_PME_EVENT_MASK 0x00000100
-#define BCHP_PCIE_0_MISC_PCIE_STATUS_PCIE_PME_EVENT_SHIFT 8
-#define BCHP_PCIE_0_MISC_PCIE_STATUS_PCIE_PME_EVENT_DEFAULT 0x00000000
-
-/* PCIE_0_MISC :: PCIE_STATUS :: PCIE_PORT [07:07] */
-#define BCHP_PCIE_0_MISC_PCIE_STATUS_PCIE_PORT_MASK 0x00000080
-#define BCHP_PCIE_0_MISC_PCIE_STATUS_PCIE_PORT_SHIFT 7
-
-/* PCIE_0_MISC :: PCIE_STATUS :: PCIE_LINK_IN_L23 [06:06] */
-#define BCHP_PCIE_0_MISC_PCIE_STATUS_PCIE_LINK_IN_L23_MASK 0x00000040
-#define BCHP_PCIE_0_MISC_PCIE_STATUS_PCIE_LINK_IN_L23_SHIFT 6
-#define BCHP_PCIE_0_MISC_PCIE_STATUS_PCIE_LINK_IN_L23_DEFAULT 0x00000000
-
-/* PCIE_0_MISC :: PCIE_STATUS :: PCIE_DL_ACTIVE [05:05] */
-#define BCHP_PCIE_0_MISC_PCIE_STATUS_PCIE_DL_ACTIVE_MASK 0x00000020
-#define BCHP_PCIE_0_MISC_PCIE_STATUS_PCIE_DL_ACTIVE_SHIFT 5
-#define BCHP_PCIE_0_MISC_PCIE_STATUS_PCIE_DL_ACTIVE_DEFAULT 0x00000000
-
-/* PCIE_0_MISC :: PCIE_STATUS :: PCIE_PHYLINKUP [04:04] */
-#define BCHP_PCIE_0_MISC_PCIE_STATUS_PCIE_PHYLINKUP_MASK 0x00000010
-#define BCHP_PCIE_0_MISC_PCIE_STATUS_PCIE_PHYLINKUP_SHIFT 4
-#define BCHP_PCIE_0_MISC_PCIE_STATUS_PCIE_PHYLINKUP_DEFAULT 0x00000000
-
-/* PCIE_0_MISC :: PCIE_STATUS :: PCIE_ERR_STATUS [03:00] */
-#define BCHP_PCIE_0_MISC_PCIE_STATUS_PCIE_ERR_STATUS_MASK 0x0000000f
-#define BCHP_PCIE_0_MISC_PCIE_STATUS_PCIE_ERR_STATUS_SHIFT 0
-#define BCHP_PCIE_0_MISC_PCIE_STATUS_PCIE_ERR_STATUS_DEFAULT 0x00000000
-
-/***************************************************************************
- *REVISION - PCIe Revision
- ***************************************************************************/
-/* PCIE_0_MISC :: REVISION :: reserved0 [31:16] */
-#define BCHP_PCIE_0_MISC_REVISION_reserved0_MASK 0xffff0000
-#define BCHP_PCIE_0_MISC_REVISION_reserved0_SHIFT 16
-
-/* PCIE_0_MISC :: REVISION :: MAJOR [15:08] */
-#define BCHP_PCIE_0_MISC_REVISION_MAJOR_MASK 0x0000ff00
-#define BCHP_PCIE_0_MISC_REVISION_MAJOR_SHIFT 8
-#define BCHP_PCIE_0_MISC_REVISION_MAJOR_DEFAULT 0x00000003
-
-/* PCIE_0_MISC :: REVISION :: MINOR [07:00] */
-#define BCHP_PCIE_0_MISC_REVISION_MINOR_MASK 0x000000ff
-#define BCHP_PCIE_0_MISC_REVISION_MINOR_SHIFT 0
-#define BCHP_PCIE_0_MISC_REVISION_MINOR_DEFAULT 0x00000001
-
-/***************************************************************************
- *CPU_2_PCIE_MEM_WIN0_BASE_LIMIT - CPU to PCIe Memory Window 0 base/limit
- ***************************************************************************/
-/* PCIE_0_MISC :: CPU_2_PCIE_MEM_WIN0_BASE_LIMIT :: LIMIT [31:20] */
-#define BCHP_PCIE_0_MISC_CPU_2_PCIE_MEM_WIN0_BASE_LIMIT_LIMIT_MASK 0xfff00000
-#define BCHP_PCIE_0_MISC_CPU_2_PCIE_MEM_WIN0_BASE_LIMIT_LIMIT_SHIFT 20
-#define BCHP_PCIE_0_MISC_CPU_2_PCIE_MEM_WIN0_BASE_LIMIT_LIMIT_DEFAULT 0x00000000
-
-/* PCIE_0_MISC :: CPU_2_PCIE_MEM_WIN0_BASE_LIMIT :: reserved0 [19:16] */
-#define BCHP_PCIE_0_MISC_CPU_2_PCIE_MEM_WIN0_BASE_LIMIT_reserved0_MASK 0x000f0000
-#define BCHP_PCIE_0_MISC_CPU_2_PCIE_MEM_WIN0_BASE_LIMIT_reserved0_SHIFT 16
-
-/* PCIE_0_MISC :: CPU_2_PCIE_MEM_WIN0_BASE_LIMIT :: BASE [15:04] */
-#define BCHP_PCIE_0_MISC_CPU_2_PCIE_MEM_WIN0_BASE_LIMIT_BASE_MASK 0x0000fff0
-#define BCHP_PCIE_0_MISC_CPU_2_PCIE_MEM_WIN0_BASE_LIMIT_BASE_SHIFT 4
-#define BCHP_PCIE_0_MISC_CPU_2_PCIE_MEM_WIN0_BASE_LIMIT_BASE_DEFAULT 0x00000001
-
-/* PCIE_0_MISC :: CPU_2_PCIE_MEM_WIN0_BASE_LIMIT :: reserved1 [03:00] */
-#define BCHP_PCIE_0_MISC_CPU_2_PCIE_MEM_WIN0_BASE_LIMIT_reserved1_MASK 0x0000000f
-#define BCHP_PCIE_0_MISC_CPU_2_PCIE_MEM_WIN0_BASE_LIMIT_reserved1_SHIFT 0
-
-/***************************************************************************
- *CPU_2_PCIE_MEM_WIN1_BASE_LIMIT - CPU to PCIe Memory Window 1 base/limit
- ***************************************************************************/
-/* PCIE_0_MISC :: CPU_2_PCIE_MEM_WIN1_BASE_LIMIT :: LIMIT [31:20] */
-#define BCHP_PCIE_0_MISC_CPU_2_PCIE_MEM_WIN1_BASE_LIMIT_LIMIT_MASK 0xfff00000
-#define BCHP_PCIE_0_MISC_CPU_2_PCIE_MEM_WIN1_BASE_LIMIT_LIMIT_SHIFT 20
-#define BCHP_PCIE_0_MISC_CPU_2_PCIE_MEM_WIN1_BASE_LIMIT_LIMIT_DEFAULT 0x00000000
-
-/* PCIE_0_MISC :: CPU_2_PCIE_MEM_WIN1_BASE_LIMIT :: reserved0 [19:16] */
-#define BCHP_PCIE_0_MISC_CPU_2_PCIE_MEM_WIN1_BASE_LIMIT_reserved0_MASK 0x000f0000
-#define BCHP_PCIE_0_MISC_CPU_2_PCIE_MEM_WIN1_BASE_LIMIT_reserved0_SHIFT 16
-
-/* PCIE_0_MISC :: CPU_2_PCIE_MEM_WIN1_BASE_LIMIT :: BASE [15:04] */
-#define BCHP_PCIE_0_MISC_CPU_2_PCIE_MEM_WIN1_BASE_LIMIT_BASE_MASK 0x0000fff0
-#define BCHP_PCIE_0_MISC_CPU_2_PCIE_MEM_WIN1_BASE_LIMIT_BASE_SHIFT 4
-#define BCHP_PCIE_0_MISC_CPU_2_PCIE_MEM_WIN1_BASE_LIMIT_BASE_DEFAULT 0x00000001
-
-/* PCIE_0_MISC :: CPU_2_PCIE_MEM_WIN1_BASE_LIMIT :: reserved1 [03:00] */
-#define BCHP_PCIE_0_MISC_CPU_2_PCIE_MEM_WIN1_BASE_LIMIT_reserved1_MASK 0x0000000f
-#define BCHP_PCIE_0_MISC_CPU_2_PCIE_MEM_WIN1_BASE_LIMIT_reserved1_SHIFT 0
-
-/***************************************************************************
- *CPU_2_PCIE_MEM_WIN2_BASE_LIMIT - CPU to PCIe Memory Window 2 base/limit
- ***************************************************************************/
-/* PCIE_0_MISC :: CPU_2_PCIE_MEM_WIN2_BASE_LIMIT :: LIMIT [31:20] */
-#define BCHP_PCIE_0_MISC_CPU_2_PCIE_MEM_WIN2_BASE_LIMIT_LIMIT_MASK 0xfff00000
-#define BCHP_PCIE_0_MISC_CPU_2_PCIE_MEM_WIN2_BASE_LIMIT_LIMIT_SHIFT 20
-#define BCHP_PCIE_0_MISC_CPU_2_PCIE_MEM_WIN2_BASE_LIMIT_LIMIT_DEFAULT 0x00000000
-
-/* PCIE_0_MISC :: CPU_2_PCIE_MEM_WIN2_BASE_LIMIT :: reserved0 [19:16] */
-#define BCHP_PCIE_0_MISC_CPU_2_PCIE_MEM_WIN2_BASE_LIMIT_reserved0_MASK 0x000f0000
-#define BCHP_PCIE_0_MISC_CPU_2_PCIE_MEM_WIN2_BASE_LIMIT_reserved0_SHIFT 16
-
-/* PCIE_0_MISC :: CPU_2_PCIE_MEM_WIN2_BASE_LIMIT :: BASE [15:04] */
-#define BCHP_PCIE_0_MISC_CPU_2_PCIE_MEM_WIN2_BASE_LIMIT_BASE_MASK 0x0000fff0
-#define BCHP_PCIE_0_MISC_CPU_2_PCIE_MEM_WIN2_BASE_LIMIT_BASE_SHIFT 4
-#define BCHP_PCIE_0_MISC_CPU_2_PCIE_MEM_WIN2_BASE_LIMIT_BASE_DEFAULT 0x00000001
-
-/* PCIE_0_MISC :: CPU_2_PCIE_MEM_WIN2_BASE_LIMIT :: reserved1 [03:00] */
-#define BCHP_PCIE_0_MISC_CPU_2_PCIE_MEM_WIN2_BASE_LIMIT_reserved1_MASK 0x0000000f
-#define BCHP_PCIE_0_MISC_CPU_2_PCIE_MEM_WIN2_BASE_LIMIT_reserved1_SHIFT 0
-
-/***************************************************************************
- *CPU_2_PCIE_MEM_WIN3_BASE_LIMIT - CPU to PCIe Memory Window 3 base/limit
- ***************************************************************************/
-/* PCIE_0_MISC :: CPU_2_PCIE_MEM_WIN3_BASE_LIMIT :: LIMIT [31:20] */
-#define BCHP_PCIE_0_MISC_CPU_2_PCIE_MEM_WIN3_BASE_LIMIT_LIMIT_MASK 0xfff00000
-#define BCHP_PCIE_0_MISC_CPU_2_PCIE_MEM_WIN3_BASE_LIMIT_LIMIT_SHIFT 20
-#define BCHP_PCIE_0_MISC_CPU_2_PCIE_MEM_WIN3_BASE_LIMIT_LIMIT_DEFAULT 0x00000000
-
-/* PCIE_0_MISC :: CPU_2_PCIE_MEM_WIN3_BASE_LIMIT :: reserved0 [19:16] */
-#define BCHP_PCIE_0_MISC_CPU_2_PCIE_MEM_WIN3_BASE_LIMIT_reserved0_MASK 0x000f0000
-#define BCHP_PCIE_0_MISC_CPU_2_PCIE_MEM_WIN3_BASE_LIMIT_reserved0_SHIFT 16
-
-/* PCIE_0_MISC :: CPU_2_PCIE_MEM_WIN3_BASE_LIMIT :: BASE [15:04] */
-#define BCHP_PCIE_0_MISC_CPU_2_PCIE_MEM_WIN3_BASE_LIMIT_BASE_MASK 0x0000fff0
-#define BCHP_PCIE_0_MISC_CPU_2_PCIE_MEM_WIN3_BASE_LIMIT_BASE_SHIFT 4
-#define BCHP_PCIE_0_MISC_CPU_2_PCIE_MEM_WIN3_BASE_LIMIT_BASE_DEFAULT 0x00000001
-
-/* PCIE_0_MISC :: CPU_2_PCIE_MEM_WIN3_BASE_LIMIT :: reserved1 [03:00] */
-#define BCHP_PCIE_0_MISC_CPU_2_PCIE_MEM_WIN3_BASE_LIMIT_reserved1_MASK 0x0000000f
-#define BCHP_PCIE_0_MISC_CPU_2_PCIE_MEM_WIN3_BASE_LIMIT_reserved1_SHIFT 0
-
-/***************************************************************************
- *CPU_2_PCIE_MEM_WIN0_BASE_HI - CPU to PCIe Memory Window 0 base high
- ***************************************************************************/
-/* PCIE_0_MISC :: CPU_2_PCIE_MEM_WIN0_BASE_HI :: reserved0 [31:08] */
-#define BCHP_PCIE_0_MISC_CPU_2_PCIE_MEM_WIN0_BASE_HI_reserved0_MASK 0xffffff00
-#define BCHP_PCIE_0_MISC_CPU_2_PCIE_MEM_WIN0_BASE_HI_reserved0_SHIFT 8
-
-/* PCIE_0_MISC :: CPU_2_PCIE_MEM_WIN0_BASE_HI :: BASE [07:00] */
-#define BCHP_PCIE_0_MISC_CPU_2_PCIE_MEM_WIN0_BASE_HI_BASE_MASK 0x000000ff
-#define BCHP_PCIE_0_MISC_CPU_2_PCIE_MEM_WIN0_BASE_HI_BASE_SHIFT 0
-#define BCHP_PCIE_0_MISC_CPU_2_PCIE_MEM_WIN0_BASE_HI_BASE_DEFAULT 0x00000000
-
-/***************************************************************************
- *CPU_2_PCIE_MEM_WIN0_LIMIT_HI - CPU to PCIe Memory Window 0 limit high
- ***************************************************************************/
-/* PCIE_0_MISC :: CPU_2_PCIE_MEM_WIN0_LIMIT_HI :: reserved0 [31:08] */
-#define BCHP_PCIE_0_MISC_CPU_2_PCIE_MEM_WIN0_LIMIT_HI_reserved0_MASK 0xffffff00
-#define BCHP_PCIE_0_MISC_CPU_2_PCIE_MEM_WIN0_LIMIT_HI_reserved0_SHIFT 8
-
-/* PCIE_0_MISC :: CPU_2_PCIE_MEM_WIN0_LIMIT_HI :: LIMIT [07:00] */
-#define BCHP_PCIE_0_MISC_CPU_2_PCIE_MEM_WIN0_LIMIT_HI_LIMIT_MASK 0x000000ff
-#define BCHP_PCIE_0_MISC_CPU_2_PCIE_MEM_WIN0_LIMIT_HI_LIMIT_SHIFT 0
-#define BCHP_PCIE_0_MISC_CPU_2_PCIE_MEM_WIN0_LIMIT_HI_LIMIT_DEFAULT 0x00000000
-
-/***************************************************************************
- *CPU_2_PCIE_MEM_WIN1_BASE_HI - CPU to PCIe Memory Window 1 base high
- ***************************************************************************/
-/* PCIE_0_MISC :: CPU_2_PCIE_MEM_WIN1_BASE_HI :: reserved0 [31:08] */
-#define BCHP_PCIE_0_MISC_CPU_2_PCIE_MEM_WIN1_BASE_HI_reserved0_MASK 0xffffff00
-#define BCHP_PCIE_0_MISC_CPU_2_PCIE_MEM_WIN1_BASE_HI_reserved0_SHIFT 8
-
-/* PCIE_0_MISC :: CPU_2_PCIE_MEM_WIN1_BASE_HI :: BASE [07:00] */
-#define BCHP_PCIE_0_MISC_CPU_2_PCIE_MEM_WIN1_BASE_HI_BASE_MASK 0x000000ff
-#define BCHP_PCIE_0_MISC_CPU_2_PCIE_MEM_WIN1_BASE_HI_BASE_SHIFT 0
-#define BCHP_PCIE_0_MISC_CPU_2_PCIE_MEM_WIN1_BASE_HI_BASE_DEFAULT 0x00000000
-
-/***************************************************************************
- *CPU_2_PCIE_MEM_WIN1_LIMIT_HI - CPU to PCIe Memory Window 1 limit high
- ***************************************************************************/
-/* PCIE_0_MISC :: CPU_2_PCIE_MEM_WIN1_LIMIT_HI :: reserved0 [31:08] */
-#define BCHP_PCIE_0_MISC_CPU_2_PCIE_MEM_WIN1_LIMIT_HI_reserved0_MASK 0xffffff00
-#define BCHP_PCIE_0_MISC_CPU_2_PCIE_MEM_WIN1_LIMIT_HI_reserved0_SHIFT 8
-
-/* PCIE_0_MISC :: CPU_2_PCIE_MEM_WIN1_LIMIT_HI :: LIMIT [07:00] */
-#define BCHP_PCIE_0_MISC_CPU_2_PCIE_MEM_WIN1_LIMIT_HI_LIMIT_MASK 0x000000ff
-#define BCHP_PCIE_0_MISC_CPU_2_PCIE_MEM_WIN1_LIMIT_HI_LIMIT_SHIFT 0
-#define BCHP_PCIE_0_MISC_CPU_2_PCIE_MEM_WIN1_LIMIT_HI_LIMIT_DEFAULT 0x00000000
-
-/***************************************************************************
- *CPU_2_PCIE_MEM_WIN2_BASE_HI - CPU to PCIe Memory Window 2 base high
- ***************************************************************************/
-/* PCIE_0_MISC :: CPU_2_PCIE_MEM_WIN2_BASE_HI :: reserved0 [31:08] */
-#define BCHP_PCIE_0_MISC_CPU_2_PCIE_MEM_WIN2_BASE_HI_reserved0_MASK 0xffffff00
-#define BCHP_PCIE_0_MISC_CPU_2_PCIE_MEM_WIN2_BASE_HI_reserved0_SHIFT 8
-
-/* PCIE_0_MISC :: CPU_2_PCIE_MEM_WIN2_BASE_HI :: BASE [07:00] */
-#define BCHP_PCIE_0_MISC_CPU_2_PCIE_MEM_WIN2_BASE_HI_BASE_MASK 0x000000ff
-#define BCHP_PCIE_0_MISC_CPU_2_PCIE_MEM_WIN2_BASE_HI_BASE_SHIFT 0
-#define BCHP_PCIE_0_MISC_CPU_2_PCIE_MEM_WIN2_BASE_HI_BASE_DEFAULT 0x00000000
-
-/***************************************************************************
- *CPU_2_PCIE_MEM_WIN2_LIMIT_HI - CPU to PCIe Memory Window 2 limit high
- ***************************************************************************/
-/* PCIE_0_MISC :: CPU_2_PCIE_MEM_WIN2_LIMIT_HI :: reserved0 [31:08] */
-#define BCHP_PCIE_0_MISC_CPU_2_PCIE_MEM_WIN2_LIMIT_HI_reserved0_MASK 0xffffff00
-#define BCHP_PCIE_0_MISC_CPU_2_PCIE_MEM_WIN2_LIMIT_HI_reserved0_SHIFT 8
-
-/* PCIE_0_MISC :: CPU_2_PCIE_MEM_WIN2_LIMIT_HI :: LIMIT [07:00] */
-#define BCHP_PCIE_0_MISC_CPU_2_PCIE_MEM_WIN2_LIMIT_HI_LIMIT_MASK 0x000000ff
-#define BCHP_PCIE_0_MISC_CPU_2_PCIE_MEM_WIN2_LIMIT_HI_LIMIT_SHIFT 0
-#define BCHP_PCIE_0_MISC_CPU_2_PCIE_MEM_WIN2_LIMIT_HI_LIMIT_DEFAULT 0x00000000
-
-/***************************************************************************
- *CPU_2_PCIE_MEM_WIN3_BASE_HI - CPU to PCIe Memory Window 3 base high
- ***************************************************************************/
-/* PCIE_0_MISC :: CPU_2_PCIE_MEM_WIN3_BASE_HI :: reserved0 [31:08] */
-#define BCHP_PCIE_0_MISC_CPU_2_PCIE_MEM_WIN3_BASE_HI_reserved0_MASK 0xffffff00
-#define BCHP_PCIE_0_MISC_CPU_2_PCIE_MEM_WIN3_BASE_HI_reserved0_SHIFT 8
-
-/* PCIE_0_MISC :: CPU_2_PCIE_MEM_WIN3_BASE_HI :: BASE [07:00] */
-#define BCHP_PCIE_0_MISC_CPU_2_PCIE_MEM_WIN3_BASE_HI_BASE_MASK 0x000000ff
-#define BCHP_PCIE_0_MISC_CPU_2_PCIE_MEM_WIN3_BASE_HI_BASE_SHIFT 0
-#define BCHP_PCIE_0_MISC_CPU_2_PCIE_MEM_WIN3_BASE_HI_BASE_DEFAULT 0x00000000
-
-/***************************************************************************
- *CPU_2_PCIE_MEM_WIN3_LIMIT_HI - CPU to PCIe Memory Window 3 limit high
- ***************************************************************************/
-/* PCIE_0_MISC :: CPU_2_PCIE_MEM_WIN3_LIMIT_HI :: reserved0 [31:08] */
-#define BCHP_PCIE_0_MISC_CPU_2_PCIE_MEM_WIN3_LIMIT_HI_reserved0_MASK 0xffffff00
-#define BCHP_PCIE_0_MISC_CPU_2_PCIE_MEM_WIN3_LIMIT_HI_reserved0_SHIFT 8
-
-/* PCIE_0_MISC :: CPU_2_PCIE_MEM_WIN3_LIMIT_HI :: LIMIT [07:00] */
-#define BCHP_PCIE_0_MISC_CPU_2_PCIE_MEM_WIN3_LIMIT_HI_LIMIT_MASK 0x000000ff
-#define BCHP_PCIE_0_MISC_CPU_2_PCIE_MEM_WIN3_LIMIT_HI_LIMIT_SHIFT 0
-#define BCHP_PCIE_0_MISC_CPU_2_PCIE_MEM_WIN3_LIMIT_HI_LIMIT_DEFAULT 0x00000000
-
-/***************************************************************************
- *MISC_CTRL_1 - MISC Control Register 1
- ***************************************************************************/
-/* PCIE_0_MISC :: MISC_CTRL_1 :: reserved0 [31:16] */
-#define BCHP_PCIE_0_MISC_MISC_CTRL_1_reserved0_MASK 0xffff0000
-#define BCHP_PCIE_0_MISC_MISC_CTRL_1_reserved0_SHIFT 16
-
-/* PCIE_0_MISC :: MISC_CTRL_1 :: TBD_OPTION_15_5 [15:05] */
-#define BCHP_PCIE_0_MISC_MISC_CTRL_1_TBD_OPTION_15_5_MASK 0x0000ffe0
-#define BCHP_PCIE_0_MISC_MISC_CTRL_1_TBD_OPTION_15_5_SHIFT 5
-#define BCHP_PCIE_0_MISC_MISC_CTRL_1_TBD_OPTION_15_5_DEFAULT 0x00000000
-
-/* PCIE_0_MISC :: MISC_CTRL_1 :: RELAXED_ORDERING [04:04] */
-#define BCHP_PCIE_0_MISC_MISC_CTRL_1_RELAXED_ORDERING_MASK 0x00000010
-#define BCHP_PCIE_0_MISC_MISC_CTRL_1_RELAXED_ORDERING_SHIFT 4
-#define BCHP_PCIE_0_MISC_MISC_CTRL_1_RELAXED_ORDERING_DEFAULT 0x00000000
-
-/* PCIE_0_MISC :: MISC_CTRL_1 :: NO_SNOOP [03:03] */
-#define BCHP_PCIE_0_MISC_MISC_CTRL_1_NO_SNOOP_MASK 0x00000008
-#define BCHP_PCIE_0_MISC_MISC_CTRL_1_NO_SNOOP_SHIFT 3
-#define BCHP_PCIE_0_MISC_MISC_CTRL_1_NO_SNOOP_DEFAULT 0x00000000
-
-/* PCIE_0_MISC :: MISC_CTRL_1 :: TRAFFIC_CLASS [02:00] */
-#define BCHP_PCIE_0_MISC_MISC_CTRL_1_TRAFFIC_CLASS_MASK 0x00000007
-#define BCHP_PCIE_0_MISC_MISC_CTRL_1_TRAFFIC_CLASS_SHIFT 0
-#define BCHP_PCIE_0_MISC_MISC_CTRL_1_TRAFFIC_CLASS_DEFAULT 0x00000000
-
-/***************************************************************************
- *UBUS_CTRL - Unused
- ***************************************************************************/
-/* PCIE_0_MISC :: UBUS_CTRL :: TBD_OPTION_31_19 [31:19] */
-#define BCHP_PCIE_0_MISC_UBUS_CTRL_TBD_OPTION_31_19_MASK 0xfff80000
-#define BCHP_PCIE_0_MISC_UBUS_CTRL_TBD_OPTION_31_19_SHIFT 19
-#define BCHP_PCIE_0_MISC_UBUS_CTRL_TBD_OPTION_31_19_DEFAULT 0x00000000
-
-/* PCIE_0_MISC :: UBUS_CTRL :: REQOUT_PRIORITY [18:18] */
-#define BCHP_PCIE_0_MISC_UBUS_CTRL_REQOUT_PRIORITY_MASK 0x00040000
-#define BCHP_PCIE_0_MISC_UBUS_CTRL_REQOUT_PRIORITY_SHIFT 18
-#define BCHP_PCIE_0_MISC_UBUS_CTRL_REQOUT_PRIORITY_DEFAULT 0x00000000
-
-/* PCIE_0_MISC :: UBUS_CTRL :: REPOUT_PRIORITY [17:17] */
-#define BCHP_PCIE_0_MISC_UBUS_CTRL_REPOUT_PRIORITY_MASK 0x00020000
-#define BCHP_PCIE_0_MISC_UBUS_CTRL_REPOUT_PRIORITY_SHIFT 17
-#define BCHP_PCIE_0_MISC_UBUS_CTRL_REPOUT_PRIORITY_DEFAULT 0x00000000
-
-/* PCIE_0_MISC :: UBUS_CTRL :: UBUS_DMA_WR_WITH_REPLY [16:15] */
-#define BCHP_PCIE_0_MISC_UBUS_CTRL_UBUS_DMA_WR_WITH_REPLY_MASK 0x00018000
-#define BCHP_PCIE_0_MISC_UBUS_CTRL_UBUS_DMA_WR_WITH_REPLY_SHIFT 15
-#define BCHP_PCIE_0_MISC_UBUS_CTRL_UBUS_DMA_WR_WITH_REPLY_DEFAULT 0x00000000
-
-/* PCIE_0_MISC :: UBUS_CTRL :: UBUS_WR_WITH_REPLY [14:14] */
-#define BCHP_PCIE_0_MISC_UBUS_CTRL_UBUS_WR_WITH_REPLY_MASK 0x00004000
-#define BCHP_PCIE_0_MISC_UBUS_CTRL_UBUS_WR_WITH_REPLY_SHIFT 14
-#define BCHP_PCIE_0_MISC_UBUS_CTRL_UBUS_WR_WITH_REPLY_DEFAULT 0x00000000
-
-/* PCIE_0_MISC :: UBUS_CTRL :: UBUS_PCIE_REPLY_ERR_DIS [13:13] */
-#define BCHP_PCIE_0_MISC_UBUS_CTRL_UBUS_PCIE_REPLY_ERR_DIS_MASK 0x00002000
-#define BCHP_PCIE_0_MISC_UBUS_CTRL_UBUS_PCIE_REPLY_ERR_DIS_SHIFT 13
-#define BCHP_PCIE_0_MISC_UBUS_CTRL_UBUS_PCIE_REPLY_ERR_DIS_DEFAULT 0x00000000
-
-/* PCIE_0_MISC :: UBUS_CTRL :: UBUS_REG_ACCESS_RO [12:12] */
-#define BCHP_PCIE_0_MISC_UBUS_CTRL_UBUS_REG_ACCESS_RO_MASK 0x00001000
-#define BCHP_PCIE_0_MISC_UBUS_CTRL_UBUS_REG_ACCESS_RO_SHIFT 12
-#define BCHP_PCIE_0_MISC_UBUS_CTRL_UBUS_REG_ACCESS_RO_DEFAULT 0x00000000
-
-/* PCIE_0_MISC :: UBUS_CTRL :: TBD_OPTION_11_0 [11:00] */
-#define BCHP_PCIE_0_MISC_UBUS_CTRL_TBD_OPTION_11_0_MASK 0x00000fff
-#define BCHP_PCIE_0_MISC_UBUS_CTRL_TBD_OPTION_11_0_SHIFT 0
-#define BCHP_PCIE_0_MISC_UBUS_CTRL_TBD_OPTION_11_0_DEFAULT 0x00000000
-
-/***************************************************************************
- *UBUS_TIMEOUT - Unused
- ***************************************************************************/
-/* PCIE_0_MISC :: UBUS_TIMEOUT :: TIMER_VALUE [31:00] */
-#define BCHP_PCIE_0_MISC_UBUS_TIMEOUT_TIMER_VALUE_MASK 0xffffffff
-#define BCHP_PCIE_0_MISC_UBUS_TIMEOUT_TIMER_VALUE_SHIFT 0
-#define BCHP_PCIE_0_MISC_UBUS_TIMEOUT_TIMER_VALUE_DEFAULT 0x00080000
-
-/***************************************************************************
- *UBUS_BAR1_CONFIG_REMAP - Unused
- ***************************************************************************/
-/* PCIE_0_MISC :: UBUS_BAR1_CONFIG_REMAP :: OFFSET [31:12] */
-#define BCHP_PCIE_0_MISC_UBUS_BAR1_CONFIG_REMAP_OFFSET_MASK 0xfffff000
-#define BCHP_PCIE_0_MISC_UBUS_BAR1_CONFIG_REMAP_OFFSET_SHIFT 12
-#define BCHP_PCIE_0_MISC_UBUS_BAR1_CONFIG_REMAP_OFFSET_DEFAULT 0x00000000
-
-/* PCIE_0_MISC :: UBUS_BAR1_CONFIG_REMAP :: reserved0 [11:04] */
-#define BCHP_PCIE_0_MISC_UBUS_BAR1_CONFIG_REMAP_reserved0_MASK 0x00000ff0
-#define BCHP_PCIE_0_MISC_UBUS_BAR1_CONFIG_REMAP_reserved0_SHIFT 4
-
-/* PCIE_0_MISC :: UBUS_BAR1_CONFIG_REMAP :: UNUSED_3_2 [03:02] */
-#define BCHP_PCIE_0_MISC_UBUS_BAR1_CONFIG_REMAP_UNUSED_3_2_MASK 0x0000000c
-#define BCHP_PCIE_0_MISC_UBUS_BAR1_CONFIG_REMAP_UNUSED_3_2_SHIFT 2
-#define BCHP_PCIE_0_MISC_UBUS_BAR1_CONFIG_REMAP_UNUSED_3_2_DEFAULT 0x00000000
-
-/* PCIE_0_MISC :: UBUS_BAR1_CONFIG_REMAP :: WR_COMBINE [01:01] */
-#define BCHP_PCIE_0_MISC_UBUS_BAR1_CONFIG_REMAP_WR_COMBINE_MASK 0x00000002
-#define BCHP_PCIE_0_MISC_UBUS_BAR1_CONFIG_REMAP_WR_COMBINE_SHIFT 1
-#define BCHP_PCIE_0_MISC_UBUS_BAR1_CONFIG_REMAP_WR_COMBINE_DEFAULT 0x00000000
-
-/* PCIE_0_MISC :: UBUS_BAR1_CONFIG_REMAP :: ACCESS_EN [00:00] */
-#define BCHP_PCIE_0_MISC_UBUS_BAR1_CONFIG_REMAP_ACCESS_EN_MASK 0x00000001
-#define BCHP_PCIE_0_MISC_UBUS_BAR1_CONFIG_REMAP_ACCESS_EN_SHIFT 0
-#define BCHP_PCIE_0_MISC_UBUS_BAR1_CONFIG_REMAP_ACCESS_EN_DEFAULT 0x00000000
-
-/***************************************************************************
- *UBUS_BAR1_CONFIG_REMAP_HI - Unused
- ***************************************************************************/
-/* PCIE_0_MISC :: UBUS_BAR1_CONFIG_REMAP_HI :: reserved0 [31:08] */
-#define BCHP_PCIE_0_MISC_UBUS_BAR1_CONFIG_REMAP_HI_reserved0_MASK 0xffffff00
-#define BCHP_PCIE_0_MISC_UBUS_BAR1_CONFIG_REMAP_HI_reserved0_SHIFT 8
-
-/* PCIE_0_MISC :: UBUS_BAR1_CONFIG_REMAP_HI :: OFFSET [07:00] */
-#define BCHP_PCIE_0_MISC_UBUS_BAR1_CONFIG_REMAP_HI_OFFSET_MASK 0x000000ff
-#define BCHP_PCIE_0_MISC_UBUS_BAR1_CONFIG_REMAP_HI_OFFSET_SHIFT 0
-#define BCHP_PCIE_0_MISC_UBUS_BAR1_CONFIG_REMAP_HI_OFFSET_DEFAULT 0x00000000
-
-/***************************************************************************
- *UBUS_BAR2_CONFIG_REMAP - Unused
- ***************************************************************************/
-/* PCIE_0_MISC :: UBUS_BAR2_CONFIG_REMAP :: OFFSET [31:12] */
-#define BCHP_PCIE_0_MISC_UBUS_BAR2_CONFIG_REMAP_OFFSET_MASK 0xfffff000
-#define BCHP_PCIE_0_MISC_UBUS_BAR2_CONFIG_REMAP_OFFSET_SHIFT 12
-#define BCHP_PCIE_0_MISC_UBUS_BAR2_CONFIG_REMAP_OFFSET_DEFAULT 0x00000000
-
-/* PCIE_0_MISC :: UBUS_BAR2_CONFIG_REMAP :: reserved0 [11:04] */
-#define BCHP_PCIE_0_MISC_UBUS_BAR2_CONFIG_REMAP_reserved0_MASK 0x00000ff0
-#define BCHP_PCIE_0_MISC_UBUS_BAR2_CONFIG_REMAP_reserved0_SHIFT 4
-
-/* PCIE_0_MISC :: UBUS_BAR2_CONFIG_REMAP :: UNUSED_3_2 [03:02] */
-#define BCHP_PCIE_0_MISC_UBUS_BAR2_CONFIG_REMAP_UNUSED_3_2_MASK 0x0000000c
-#define BCHP_PCIE_0_MISC_UBUS_BAR2_CONFIG_REMAP_UNUSED_3_2_SHIFT 2
-#define BCHP_PCIE_0_MISC_UBUS_BAR2_CONFIG_REMAP_UNUSED_3_2_DEFAULT 0x00000000
-
-/* PCIE_0_MISC :: UBUS_BAR2_CONFIG_REMAP :: WR_COMBINE [01:01] */
-#define BCHP_PCIE_0_MISC_UBUS_BAR2_CONFIG_REMAP_WR_COMBINE_MASK 0x00000002
-#define BCHP_PCIE_0_MISC_UBUS_BAR2_CONFIG_REMAP_WR_COMBINE_SHIFT 1
-#define BCHP_PCIE_0_MISC_UBUS_BAR2_CONFIG_REMAP_WR_COMBINE_DEFAULT 0x00000000
-
-/* PCIE_0_MISC :: UBUS_BAR2_CONFIG_REMAP :: ACCESS_EN [00:00] */
-#define BCHP_PCIE_0_MISC_UBUS_BAR2_CONFIG_REMAP_ACCESS_EN_MASK 0x00000001
-#define BCHP_PCIE_0_MISC_UBUS_BAR2_CONFIG_REMAP_ACCESS_EN_SHIFT 0
-#define BCHP_PCIE_0_MISC_UBUS_BAR2_CONFIG_REMAP_ACCESS_EN_DEFAULT 0x00000000
-
-/***************************************************************************
- *UBUS_BAR2_CONFIG_REMAP_HI - Unused
- ***************************************************************************/
-/* PCIE_0_MISC :: UBUS_BAR2_CONFIG_REMAP_HI :: reserved0 [31:08] */
-#define BCHP_PCIE_0_MISC_UBUS_BAR2_CONFIG_REMAP_HI_reserved0_MASK 0xffffff00
-#define BCHP_PCIE_0_MISC_UBUS_BAR2_CONFIG_REMAP_HI_reserved0_SHIFT 8
-
-/* PCIE_0_MISC :: UBUS_BAR2_CONFIG_REMAP_HI :: OFFSET [07:00] */
-#define BCHP_PCIE_0_MISC_UBUS_BAR2_CONFIG_REMAP_HI_OFFSET_MASK 0x000000ff
-#define BCHP_PCIE_0_MISC_UBUS_BAR2_CONFIG_REMAP_HI_OFFSET_SHIFT 0
-#define BCHP_PCIE_0_MISC_UBUS_BAR2_CONFIG_REMAP_HI_OFFSET_DEFAULT 0x00000000
-
-/***************************************************************************
- *UBUS_BAR3_CONFIG_REMAP - Unused
- ***************************************************************************/
-/* PCIE_0_MISC :: UBUS_BAR3_CONFIG_REMAP :: OFFSET [31:12] */
-#define BCHP_PCIE_0_MISC_UBUS_BAR3_CONFIG_REMAP_OFFSET_MASK 0xfffff000
-#define BCHP_PCIE_0_MISC_UBUS_BAR3_CONFIG_REMAP_OFFSET_SHIFT 12
-#define BCHP_PCIE_0_MISC_UBUS_BAR3_CONFIG_REMAP_OFFSET_DEFAULT 0x00000000
-
-/* PCIE_0_MISC :: UBUS_BAR3_CONFIG_REMAP :: reserved0 [11:04] */
-#define BCHP_PCIE_0_MISC_UBUS_BAR3_CONFIG_REMAP_reserved0_MASK 0x00000ff0
-#define BCHP_PCIE_0_MISC_UBUS_BAR3_CONFIG_REMAP_reserved0_SHIFT 4
-
-/* PCIE_0_MISC :: UBUS_BAR3_CONFIG_REMAP :: UNUSED_3_2 [03:02] */
-#define BCHP_PCIE_0_MISC_UBUS_BAR3_CONFIG_REMAP_UNUSED_3_2_MASK 0x0000000c
-#define BCHP_PCIE_0_MISC_UBUS_BAR3_CONFIG_REMAP_UNUSED_3_2_SHIFT 2
-#define BCHP_PCIE_0_MISC_UBUS_BAR3_CONFIG_REMAP_UNUSED_3_2_DEFAULT 0x00000000
-
-/* PCIE_0_MISC :: UBUS_BAR3_CONFIG_REMAP :: WR_COMBINE [01:01] */
-#define BCHP_PCIE_0_MISC_UBUS_BAR3_CONFIG_REMAP_WR_COMBINE_MASK 0x00000002
-#define BCHP_PCIE_0_MISC_UBUS_BAR3_CONFIG_REMAP_WR_COMBINE_SHIFT 1
-#define BCHP_PCIE_0_MISC_UBUS_BAR3_CONFIG_REMAP_WR_COMBINE_DEFAULT 0x00000000
-
-/* PCIE_0_MISC :: UBUS_BAR3_CONFIG_REMAP :: ACCESS_EN [00:00] */
-#define BCHP_PCIE_0_MISC_UBUS_BAR3_CONFIG_REMAP_ACCESS_EN_MASK 0x00000001
-#define BCHP_PCIE_0_MISC_UBUS_BAR3_CONFIG_REMAP_ACCESS_EN_SHIFT 0
-#define BCHP_PCIE_0_MISC_UBUS_BAR3_CONFIG_REMAP_ACCESS_EN_DEFAULT 0x00000000
-
-/***************************************************************************
- *UBUS_BAR3_CONFIG_REMAP_HI - Unused
- ***************************************************************************/
-/* PCIE_0_MISC :: UBUS_BAR3_CONFIG_REMAP_HI :: reserved0 [31:08] */
-#define BCHP_PCIE_0_MISC_UBUS_BAR3_CONFIG_REMAP_HI_reserved0_MASK 0xffffff00
-#define BCHP_PCIE_0_MISC_UBUS_BAR3_CONFIG_REMAP_HI_reserved0_SHIFT 8
-
-/* PCIE_0_MISC :: UBUS_BAR3_CONFIG_REMAP_HI :: OFFSET [07:00] */
-#define BCHP_PCIE_0_MISC_UBUS_BAR3_CONFIG_REMAP_HI_OFFSET_MASK 0x000000ff
-#define BCHP_PCIE_0_MISC_UBUS_BAR3_CONFIG_REMAP_HI_OFFSET_SHIFT 0
-#define BCHP_PCIE_0_MISC_UBUS_BAR3_CONFIG_REMAP_HI_OFFSET_DEFAULT 0x00000000
-
-/***************************************************************************
- *UBUS_STATUS - Unused
- ***************************************************************************/
-/* PCIE_0_MISC :: UBUS_STATUS :: SLAVE_REPOUT_HSPACE [31:24] */
-#define BCHP_PCIE_0_MISC_UBUS_STATUS_SLAVE_REPOUT_HSPACE_MASK 0xff000000
-#define BCHP_PCIE_0_MISC_UBUS_STATUS_SLAVE_REPOUT_HSPACE_SHIFT 24
-#define BCHP_PCIE_0_MISC_UBUS_STATUS_SLAVE_REPOUT_HSPACE_DEFAULT 0x00000000
-
-/* PCIE_0_MISC :: UBUS_STATUS :: SLAVE_REPOUT_DSPACE [23:16] */
-#define BCHP_PCIE_0_MISC_UBUS_STATUS_SLAVE_REPOUT_DSPACE_MASK 0x00ff0000
-#define BCHP_PCIE_0_MISC_UBUS_STATUS_SLAVE_REPOUT_DSPACE_SHIFT 16
-#define BCHP_PCIE_0_MISC_UBUS_STATUS_SLAVE_REPOUT_DSPACE_DEFAULT 0x00000000
-
-/* PCIE_0_MISC :: UBUS_STATUS :: MASTER_REQOUT_HSPACE [15:08] */
-#define BCHP_PCIE_0_MISC_UBUS_STATUS_MASTER_REQOUT_HSPACE_MASK 0x0000ff00
-#define BCHP_PCIE_0_MISC_UBUS_STATUS_MASTER_REQOUT_HSPACE_SHIFT 8
-#define BCHP_PCIE_0_MISC_UBUS_STATUS_MASTER_REQOUT_HSPACE_DEFAULT 0x00000000
-
-/* PCIE_0_MISC :: UBUS_STATUS :: MASTER_REQOUT_DSPACE [07:00] */
-#define BCHP_PCIE_0_MISC_UBUS_STATUS_MASTER_REQOUT_DSPACE_MASK 0x000000ff
-#define BCHP_PCIE_0_MISC_UBUS_STATUS_MASTER_REQOUT_DSPACE_SHIFT 0
-#define BCHP_PCIE_0_MISC_UBUS_STATUS_MASTER_REQOUT_DSPACE_DEFAULT 0x00000000
-
-/***************************************************************************
- *SCB_STATUS - SCB Status
- ***************************************************************************/
-/* PCIE_0_MISC :: SCB_STATUS :: UNUSED_31_3 [31:03] */
-#define BCHP_PCIE_0_MISC_SCB_STATUS_UNUSED_31_3_MASK 0xfffffff8
-#define BCHP_PCIE_0_MISC_SCB_STATUS_UNUSED_31_3_SHIFT 3
-#define BCHP_PCIE_0_MISC_SCB_STATUS_UNUSED_31_3_DEFAULT 0x00000000
-
-/* PCIE_0_MISC :: SCB_STATUS :: SCB2_INIT_STATE [02:02] */
-#define BCHP_PCIE_0_MISC_SCB_STATUS_SCB2_INIT_STATE_MASK 0x00000004
-#define BCHP_PCIE_0_MISC_SCB_STATUS_SCB2_INIT_STATE_SHIFT 2
-#define BCHP_PCIE_0_MISC_SCB_STATUS_SCB2_INIT_STATE_DEFAULT 0x00000000
-
-/* PCIE_0_MISC :: SCB_STATUS :: SCB1_INIT_STATE [01:01] */
-#define BCHP_PCIE_0_MISC_SCB_STATUS_SCB1_INIT_STATE_MASK 0x00000002
-#define BCHP_PCIE_0_MISC_SCB_STATUS_SCB1_INIT_STATE_SHIFT 1
-#define BCHP_PCIE_0_MISC_SCB_STATUS_SCB1_INIT_STATE_DEFAULT 0x00000000
-
-/* PCIE_0_MISC :: SCB_STATUS :: SCB0_INIT_STATE [00:00] */
-#define BCHP_PCIE_0_MISC_SCB_STATUS_SCB0_INIT_STATE_MASK 0x00000001
-#define BCHP_PCIE_0_MISC_SCB_STATUS_SCB0_INIT_STATE_SHIFT 0
-#define BCHP_PCIE_0_MISC_SCB_STATUS_SCB0_INIT_STATE_DEFAULT 0x00000000
-
-#endif /* #ifndef BCHP_PCIE_0_MISC_H__ */
-
-/* End of File */
diff --git a/include/linux/brcmstb/7366b0/bchp_pcie_0_misc_perst.h b/include/linux/brcmstb/7366b0/bchp_pcie_0_misc_perst.h
deleted file mode 100644
index 8b4ed4c..0000000
--- a/include/linux/brcmstb/7366b0/bchp_pcie_0_misc_perst.h
+++ /dev/null
@@ -1,85 +0,0 @@
-/***************************************************************************
- * Copyright (c) 1999-2013, Broadcom Corporation
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
- *
- * Module Description:
- * DO NOT EDIT THIS FILE DIRECTLY
- *
- * This module was generated magically with RDB from a source description
- * file. You must edit the source file for changes to be made to this file.
- *
- *
- * Date: Generated on Sat Apr 20 03:07:46 2013
- * MD5 Checksum d41d8cd98f00b204e9800998ecf8427e
- *
- * Compiled with: RDB Utility combo_header.pl
- * RDB Parser 3.0
- * unknown unknown
- * Perl Interpreter 5.008008
- * Operating System linux
- *
- * Revision History:
- *
- * $brcm_Log: $
- *
- ***************************************************************************/
-
-#ifndef BCHP_PCIE_0_MISC_PERST_H__
-#define BCHP_PCIE_0_MISC_PERST_H__
-
-/***************************************************************************
- *PCIE_0_MISC_PERST - PCI-E Miscellaneous Registers (Fundamental reset)
- ***************************************************************************/
-#define BCHP_PCIE_0_MISC_PERST_ECO_CTRL_PERST 0x00474100 /* ECO PCIE Reset Control Register */
-#define BCHP_PCIE_0_MISC_PERST_CCE_STATUS 0x00474104 /* Config Copy Engine Status */
-
-/***************************************************************************
- *ECO_CTRL_PERST - ECO PCIE Reset Control Register
- ***************************************************************************/
-/* PCIE_0_MISC_PERST :: ECO_CTRL_PERST :: reserved0 [31:16] */
-#define BCHP_PCIE_0_MISC_PERST_ECO_CTRL_PERST_reserved0_MASK 0xffff0000
-#define BCHP_PCIE_0_MISC_PERST_ECO_CTRL_PERST_reserved0_SHIFT 16
-
-/* PCIE_0_MISC_PERST :: ECO_CTRL_PERST :: ECO_PERST_N [15:00] */
-#define BCHP_PCIE_0_MISC_PERST_ECO_CTRL_PERST_ECO_PERST_N_MASK 0x0000ffff
-#define BCHP_PCIE_0_MISC_PERST_ECO_CTRL_PERST_ECO_PERST_N_SHIFT 0
-#define BCHP_PCIE_0_MISC_PERST_ECO_CTRL_PERST_ECO_PERST_N_DEFAULT 0x00000000
-
-/***************************************************************************
- *CCE_STATUS - Config Copy Engine Status
- ***************************************************************************/
-/* PCIE_0_MISC_PERST :: CCE_STATUS :: CCE_DONE [31:31] */
-#define BCHP_PCIE_0_MISC_PERST_CCE_STATUS_CCE_DONE_MASK 0x80000000
-#define BCHP_PCIE_0_MISC_PERST_CCE_STATUS_CCE_DONE_SHIFT 31
-
-/* PCIE_0_MISC_PERST :: CCE_STATUS :: reserved0 [30:03] */
-#define BCHP_PCIE_0_MISC_PERST_CCE_STATUS_reserved0_MASK 0x7ffffff8
-#define BCHP_PCIE_0_MISC_PERST_CCE_STATUS_reserved0_SHIFT 3
-
-/* PCIE_0_MISC_PERST :: CCE_STATUS :: CCE_BAD_GISB_ACCESS [02:02] */
-#define BCHP_PCIE_0_MISC_PERST_CCE_STATUS_CCE_BAD_GISB_ACCESS_MASK 0x00000004
-#define BCHP_PCIE_0_MISC_PERST_CCE_STATUS_CCE_BAD_GISB_ACCESS_SHIFT 2
-
-/* PCIE_0_MISC_PERST :: CCE_STATUS :: CCE_BAD_I2C_ACCESS [01:01] */
-#define BCHP_PCIE_0_MISC_PERST_CCE_STATUS_CCE_BAD_I2C_ACCESS_MASK 0x00000002
-#define BCHP_PCIE_0_MISC_PERST_CCE_STATUS_CCE_BAD_I2C_ACCESS_SHIFT 1
-
-/* PCIE_0_MISC_PERST :: CCE_STATUS :: CCE_BAD_SECTION_ID [00:00] */
-#define BCHP_PCIE_0_MISC_PERST_CCE_STATUS_CCE_BAD_SECTION_ID_MASK 0x00000001
-#define BCHP_PCIE_0_MISC_PERST_CCE_STATUS_CCE_BAD_SECTION_ID_SHIFT 0
-
-#endif /* #ifndef BCHP_PCIE_0_MISC_PERST_H__ */
-
-/* End of File */
diff --git a/include/linux/brcmstb/7366b0/bchp_pcie_0_rc_cfg_pcie.h b/include/linux/brcmstb/7366b0/bchp_pcie_0_rc_cfg_pcie.h
deleted file mode 100644
index 449f202..0000000
--- a/include/linux/brcmstb/7366b0/bchp_pcie_0_rc_cfg_pcie.h
+++ /dev/null
@@ -1,644 +0,0 @@
-/***************************************************************************
- * Copyright (c) 1999-2013, Broadcom Corporation
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
- *
- * Module Description:
- * DO NOT EDIT THIS FILE DIRECTLY
- *
- * This module was generated magically with RDB from a source description
- * file. You must edit the source file for changes to be made to this file.
- *
- *
- * Date: Generated on Sat Apr 20 03:07:46 2013
- * MD5 Checksum d41d8cd98f00b204e9800998ecf8427e
- *
- * Compiled with: RDB Utility combo_header.pl
- * RDB Parser 3.0
- * unknown unknown
- * Perl Interpreter 5.008008
- * Operating System linux
- *
- * Revision History:
- *
- * $brcm_Log: $
- *
- ***************************************************************************/
-
-#ifndef BCHP_PCIE_0_RC_CFG_PCIE_H__
-#define BCHP_PCIE_0_RC_CFG_PCIE_H__
-
-/***************************************************************************
- *PCIE_0_RC_CFG_PCIE
- ***************************************************************************/
-#define BCHP_PCIE_0_RC_CFG_PCIE_PCIE_CAPABILITY 0x004700ac /* pcie_capability */
-#define BCHP_PCIE_0_RC_CFG_PCIE_DEVICE_CAPABILITY 0x004700b0 /* device_capability */
-#define BCHP_PCIE_0_RC_CFG_PCIE_DEVICE_STATUS_CONTROL 0x004700b4 /* device_status_control */
-#define BCHP_PCIE_0_RC_CFG_PCIE_LINK_CAPABILITY 0x004700b8 /* link_capability */
-#define BCHP_PCIE_0_RC_CFG_PCIE_LINK_STATUS_CONTROL 0x004700bc /* link_status_control */
-#define BCHP_PCIE_0_RC_CFG_PCIE_SLOT_CAPABILITY 0x004700c0 /* slot_capability */
-#define BCHP_PCIE_0_RC_CFG_PCIE_SLOT_CONTROL_STATUS 0x004700c4 /* slot_control_status */
-#define BCHP_PCIE_0_RC_CFG_PCIE_ROOT_CAP_CONTROL 0x004700c8 /* root_cap_control */
-#define BCHP_PCIE_0_RC_CFG_PCIE_ROOT_STATUS 0x004700cc /* root_status */
-#define BCHP_PCIE_0_RC_CFG_PCIE_DEVICE_CAPABILITY_2 0x004700d0 /* device_capability_2 */
-#define BCHP_PCIE_0_RC_CFG_PCIE_DEVICE_STATUS_CONTROL_2 0x004700d4 /* device_status_control_2 */
-#define BCHP_PCIE_0_RC_CFG_PCIE_LINK_CAPABILITY_2 0x004700d8 /* link_capability_2 */
-#define BCHP_PCIE_0_RC_CFG_PCIE_LINK_STATUS_CONTROL_2 0x004700dc /* link_status_control_2 */
-#define BCHP_PCIE_0_RC_CFG_PCIE_SLOT_CAPABILITY_2 0x004700e0 /* slot_capability_2 */
-#define BCHP_PCIE_0_RC_CFG_PCIE_SLOT_STATUS_CONTROL_2 0x004700e4 /* slot_status_control_2 */
-
-/***************************************************************************
- *PCIE_CAPABILITY - pcie_capability
- ***************************************************************************/
-/* PCIE_0_RC_CFG_PCIE :: PCIE_CAPABILITY :: RESERVED0 [31:30] */
-#define BCHP_PCIE_0_RC_CFG_PCIE_PCIE_CAPABILITY_RESERVED0_MASK 0xc0000000
-#define BCHP_PCIE_0_RC_CFG_PCIE_PCIE_CAPABILITY_RESERVED0_SHIFT 30
-
-/* PCIE_0_RC_CFG_PCIE :: PCIE_CAPABILITY :: MSG_NUM [29:25] */
-#define BCHP_PCIE_0_RC_CFG_PCIE_PCIE_CAPABILITY_MSG_NUM_MASK 0x3e000000
-#define BCHP_PCIE_0_RC_CFG_PCIE_PCIE_CAPABILITY_MSG_NUM_SHIFT 25
-#define BCHP_PCIE_0_RC_CFG_PCIE_PCIE_CAPABILITY_MSG_NUM_DEFAULT 0x00000000
-
-/* PCIE_0_RC_CFG_PCIE :: PCIE_CAPABILITY :: SLOT_IMPLEMENTED [24:24] */
-#define BCHP_PCIE_0_RC_CFG_PCIE_PCIE_CAPABILITY_SLOT_IMPLEMENTED_MASK 0x01000000
-#define BCHP_PCIE_0_RC_CFG_PCIE_PCIE_CAPABILITY_SLOT_IMPLEMENTED_SHIFT 24
-#define BCHP_PCIE_0_RC_CFG_PCIE_PCIE_CAPABILITY_SLOT_IMPLEMENTED_DEFAULT 0x00000000
-
-/* PCIE_0_RC_CFG_PCIE :: PCIE_CAPABILITY :: TYPE [23:20] */
-#define BCHP_PCIE_0_RC_CFG_PCIE_PCIE_CAPABILITY_TYPE_MASK 0x00f00000
-#define BCHP_PCIE_0_RC_CFG_PCIE_PCIE_CAPABILITY_TYPE_SHIFT 20
-#define BCHP_PCIE_0_RC_CFG_PCIE_PCIE_CAPABILITY_TYPE_DEFAULT 0x00000004
-
-/* PCIE_0_RC_CFG_PCIE :: PCIE_CAPABILITY :: VER [19:16] */
-#define BCHP_PCIE_0_RC_CFG_PCIE_PCIE_CAPABILITY_VER_MASK 0x000f0000
-#define BCHP_PCIE_0_RC_CFG_PCIE_PCIE_CAPABILITY_VER_SHIFT 16
-#define BCHP_PCIE_0_RC_CFG_PCIE_PCIE_CAPABILITY_VER_DEFAULT 0x00000002
-
-/* PCIE_0_RC_CFG_PCIE :: PCIE_CAPABILITY :: PCIE_NEXT_CAP_PTR [15:08] */
-#define BCHP_PCIE_0_RC_CFG_PCIE_PCIE_CAPABILITY_PCIE_NEXT_CAP_PTR_MASK 0x0000ff00
-#define BCHP_PCIE_0_RC_CFG_PCIE_PCIE_CAPABILITY_PCIE_NEXT_CAP_PTR_SHIFT 8
-#define BCHP_PCIE_0_RC_CFG_PCIE_PCIE_CAPABILITY_PCIE_NEXT_CAP_PTR_DEFAULT 0x00000000
-
-/* PCIE_0_RC_CFG_PCIE :: PCIE_CAPABILITY :: PCIE_CAP_ID [07:00] */
-#define BCHP_PCIE_0_RC_CFG_PCIE_PCIE_CAPABILITY_PCIE_CAP_ID_MASK 0x000000ff
-#define BCHP_PCIE_0_RC_CFG_PCIE_PCIE_CAPABILITY_PCIE_CAP_ID_SHIFT 0
-#define BCHP_PCIE_0_RC_CFG_PCIE_PCIE_CAPABILITY_PCIE_CAP_ID_DEFAULT 0x00000010
-
-/***************************************************************************
- *DEVICE_CAPABILITY - device_capability
- ***************************************************************************/
-/* PCIE_0_RC_CFG_PCIE :: DEVICE_CAPABILITY :: RESERVED3 [31:28] */
-#define BCHP_PCIE_0_RC_CFG_PCIE_DEVICE_CAPABILITY_RESERVED3_MASK 0xf0000000
-#define BCHP_PCIE_0_RC_CFG_PCIE_DEVICE_CAPABILITY_RESERVED3_SHIFT 28
-
-/* PCIE_0_RC_CFG_PCIE :: DEVICE_CAPABILITY :: CAPTURED_SLOT_PWR_SCALE [27:26] */
-#define BCHP_PCIE_0_RC_CFG_PCIE_DEVICE_CAPABILITY_CAPTURED_SLOT_PWR_SCALE_MASK 0x0c000000
-#define BCHP_PCIE_0_RC_CFG_PCIE_DEVICE_CAPABILITY_CAPTURED_SLOT_PWR_SCALE_SHIFT 26
-#define BCHP_PCIE_0_RC_CFG_PCIE_DEVICE_CAPABILITY_CAPTURED_SLOT_PWR_SCALE_DEFAULT 0x00000000
-
-/* PCIE_0_RC_CFG_PCIE :: DEVICE_CAPABILITY :: CAPTURED_SLOT_PWR_VAL [25:18] */
-#define BCHP_PCIE_0_RC_CFG_PCIE_DEVICE_CAPABILITY_CAPTURED_SLOT_PWR_VAL_MASK 0x03fc0000
-#define BCHP_PCIE_0_RC_CFG_PCIE_DEVICE_CAPABILITY_CAPTURED_SLOT_PWR_VAL_SHIFT 18
-#define BCHP_PCIE_0_RC_CFG_PCIE_DEVICE_CAPABILITY_CAPTURED_SLOT_PWR_VAL_DEFAULT 0x00000000
-
-/* PCIE_0_RC_CFG_PCIE :: DEVICE_CAPABILITY :: RESERVED2 [17:16] */
-#define BCHP_PCIE_0_RC_CFG_PCIE_DEVICE_CAPABILITY_RESERVED2_MASK 0x00030000
-#define BCHP_PCIE_0_RC_CFG_PCIE_DEVICE_CAPABILITY_RESERVED2_SHIFT 16
-
-/* PCIE_0_RC_CFG_PCIE :: DEVICE_CAPABILITY :: ROLE_BASED_ERR_RPT [15:15] */
-#define BCHP_PCIE_0_RC_CFG_PCIE_DEVICE_CAPABILITY_ROLE_BASED_ERR_RPT_MASK 0x00008000
-#define BCHP_PCIE_0_RC_CFG_PCIE_DEVICE_CAPABILITY_ROLE_BASED_ERR_RPT_SHIFT 15
-#define BCHP_PCIE_0_RC_CFG_PCIE_DEVICE_CAPABILITY_ROLE_BASED_ERR_RPT_DEFAULT 0x00000001
-
-/* PCIE_0_RC_CFG_PCIE :: DEVICE_CAPABILITY :: RESERVED1 [14:12] */
-#define BCHP_PCIE_0_RC_CFG_PCIE_DEVICE_CAPABILITY_RESERVED1_MASK 0x00007000
-#define BCHP_PCIE_0_RC_CFG_PCIE_DEVICE_CAPABILITY_RESERVED1_SHIFT 12
-
-/* PCIE_0_RC_CFG_PCIE :: DEVICE_CAPABILITY :: L1_ACCEPTABLE_LATENCY [11:09] */
-#define BCHP_PCIE_0_RC_CFG_PCIE_DEVICE_CAPABILITY_L1_ACCEPTABLE_LATENCY_MASK 0x00000e00
-#define BCHP_PCIE_0_RC_CFG_PCIE_DEVICE_CAPABILITY_L1_ACCEPTABLE_LATENCY_SHIFT 9
-#define BCHP_PCIE_0_RC_CFG_PCIE_DEVICE_CAPABILITY_L1_ACCEPTABLE_LATENCY_DEFAULT 0x00000000
-
-/* PCIE_0_RC_CFG_PCIE :: DEVICE_CAPABILITY :: L0S_ACCEPTABLE_LATENCY [08:06] */
-#define BCHP_PCIE_0_RC_CFG_PCIE_DEVICE_CAPABILITY_L0S_ACCEPTABLE_LATENCY_MASK 0x000001c0
-#define BCHP_PCIE_0_RC_CFG_PCIE_DEVICE_CAPABILITY_L0S_ACCEPTABLE_LATENCY_SHIFT 6
-#define BCHP_PCIE_0_RC_CFG_PCIE_DEVICE_CAPABILITY_L0S_ACCEPTABLE_LATENCY_DEFAULT 0x00000000
-
-/* PCIE_0_RC_CFG_PCIE :: DEVICE_CAPABILITY :: EXTENDED_TAG_SUPPORT [05:05] */
-#define BCHP_PCIE_0_RC_CFG_PCIE_DEVICE_CAPABILITY_EXTENDED_TAG_SUPPORT_MASK 0x00000020
-#define BCHP_PCIE_0_RC_CFG_PCIE_DEVICE_CAPABILITY_EXTENDED_TAG_SUPPORT_SHIFT 5
-#define BCHP_PCIE_0_RC_CFG_PCIE_DEVICE_CAPABILITY_EXTENDED_TAG_SUPPORT_DEFAULT 0x00000000
-
-/* PCIE_0_RC_CFG_PCIE :: DEVICE_CAPABILITY :: RESERVED0 [04:03] */
-#define BCHP_PCIE_0_RC_CFG_PCIE_DEVICE_CAPABILITY_RESERVED0_MASK 0x00000018
-#define BCHP_PCIE_0_RC_CFG_PCIE_DEVICE_CAPABILITY_RESERVED0_SHIFT 3
-
-/* PCIE_0_RC_CFG_PCIE :: DEVICE_CAPABILITY :: MAX_PL_SIZE_SUPPORTED [02:00] */
-#define BCHP_PCIE_0_RC_CFG_PCIE_DEVICE_CAPABILITY_MAX_PL_SIZE_SUPPORTED_MASK 0x00000007
-#define BCHP_PCIE_0_RC_CFG_PCIE_DEVICE_CAPABILITY_MAX_PL_SIZE_SUPPORTED_SHIFT 0
-#define BCHP_PCIE_0_RC_CFG_PCIE_DEVICE_CAPABILITY_MAX_PL_SIZE_SUPPORTED_DEFAULT 0x00000002
-
-/***************************************************************************
- *DEVICE_STATUS_CONTROL - device_status_control
- ***************************************************************************/
-/* PCIE_0_RC_CFG_PCIE :: DEVICE_STATUS_CONTROL :: RESERVED2 [31:22] */
-#define BCHP_PCIE_0_RC_CFG_PCIE_DEVICE_STATUS_CONTROL_RESERVED2_MASK 0xffc00000
-#define BCHP_PCIE_0_RC_CFG_PCIE_DEVICE_STATUS_CONTROL_RESERVED2_SHIFT 22
-
-/* PCIE_0_RC_CFG_PCIE :: DEVICE_STATUS_CONTROL :: NP_TRANSACTION_PEND [21:21] */
-#define BCHP_PCIE_0_RC_CFG_PCIE_DEVICE_STATUS_CONTROL_NP_TRANSACTION_PEND_MASK 0x00200000
-#define BCHP_PCIE_0_RC_CFG_PCIE_DEVICE_STATUS_CONTROL_NP_TRANSACTION_PEND_SHIFT 21
-#define BCHP_PCIE_0_RC_CFG_PCIE_DEVICE_STATUS_CONTROL_NP_TRANSACTION_PEND_DEFAULT 0x00000000
-
-/* PCIE_0_RC_CFG_PCIE :: DEVICE_STATUS_CONTROL :: AUX_PWR_DET [20:20] */
-#define BCHP_PCIE_0_RC_CFG_PCIE_DEVICE_STATUS_CONTROL_AUX_PWR_DET_MASK 0x00100000
-#define BCHP_PCIE_0_RC_CFG_PCIE_DEVICE_STATUS_CONTROL_AUX_PWR_DET_SHIFT 20
-#define BCHP_PCIE_0_RC_CFG_PCIE_DEVICE_STATUS_CONTROL_AUX_PWR_DET_DEFAULT 0x00000001
-
-/* PCIE_0_RC_CFG_PCIE :: DEVICE_STATUS_CONTROL :: UNSUP_REQ_DET [19:19] */
-#define BCHP_PCIE_0_RC_CFG_PCIE_DEVICE_STATUS_CONTROL_UNSUP_REQ_DET_MASK 0x00080000
-#define BCHP_PCIE_0_RC_CFG_PCIE_DEVICE_STATUS_CONTROL_UNSUP_REQ_DET_SHIFT 19
-#define BCHP_PCIE_0_RC_CFG_PCIE_DEVICE_STATUS_CONTROL_UNSUP_REQ_DET_DEFAULT 0x00000000
-
-/* PCIE_0_RC_CFG_PCIE :: DEVICE_STATUS_CONTROL :: FATAL_ERR_DET [18:18] */
-#define BCHP_PCIE_0_RC_CFG_PCIE_DEVICE_STATUS_CONTROL_FATAL_ERR_DET_MASK 0x00040000
-#define BCHP_PCIE_0_RC_CFG_PCIE_DEVICE_STATUS_CONTROL_FATAL_ERR_DET_SHIFT 18
-#define BCHP_PCIE_0_RC_CFG_PCIE_DEVICE_STATUS_CONTROL_FATAL_ERR_DET_DEFAULT 0x00000000
-
-/* PCIE_0_RC_CFG_PCIE :: DEVICE_STATUS_CONTROL :: NON_FATAL_ERR_DET [17:17] */
-#define BCHP_PCIE_0_RC_CFG_PCIE_DEVICE_STATUS_CONTROL_NON_FATAL_ERR_DET_MASK 0x00020000
-#define BCHP_PCIE_0_RC_CFG_PCIE_DEVICE_STATUS_CONTROL_NON_FATAL_ERR_DET_SHIFT 17
-#define BCHP_PCIE_0_RC_CFG_PCIE_DEVICE_STATUS_CONTROL_NON_FATAL_ERR_DET_DEFAULT 0x00000000
-
-/* PCIE_0_RC_CFG_PCIE :: DEVICE_STATUS_CONTROL :: CORR_ERR_DET [16:16] */
-#define BCHP_PCIE_0_RC_CFG_PCIE_DEVICE_STATUS_CONTROL_CORR_ERR_DET_MASK 0x00010000
-#define BCHP_PCIE_0_RC_CFG_PCIE_DEVICE_STATUS_CONTROL_CORR_ERR_DET_SHIFT 16
-#define BCHP_PCIE_0_RC_CFG_PCIE_DEVICE_STATUS_CONTROL_CORR_ERR_DET_DEFAULT 0x00000000
-
-/* PCIE_0_RC_CFG_PCIE :: DEVICE_STATUS_CONTROL :: RESERVED1 [15:15] */
-#define BCHP_PCIE_0_RC_CFG_PCIE_DEVICE_STATUS_CONTROL_RESERVED1_MASK 0x00008000
-#define BCHP_PCIE_0_RC_CFG_PCIE_DEVICE_STATUS_CONTROL_RESERVED1_SHIFT 15
-
-/* PCIE_0_RC_CFG_PCIE :: DEVICE_STATUS_CONTROL :: MAX_READ_REQ_SIZ [14:12] */
-#define BCHP_PCIE_0_RC_CFG_PCIE_DEVICE_STATUS_CONTROL_MAX_READ_REQ_SIZ_MASK 0x00007000
-#define BCHP_PCIE_0_RC_CFG_PCIE_DEVICE_STATUS_CONTROL_MAX_READ_REQ_SIZ_SHIFT 12
-#define BCHP_PCIE_0_RC_CFG_PCIE_DEVICE_STATUS_CONTROL_MAX_READ_REQ_SIZ_DEFAULT 0x00000002
-
-/* PCIE_0_RC_CFG_PCIE :: DEVICE_STATUS_CONTROL :: NO_SNOOP_ENABLE [11:11] */
-#define BCHP_PCIE_0_RC_CFG_PCIE_DEVICE_STATUS_CONTROL_NO_SNOOP_ENABLE_MASK 0x00000800
-#define BCHP_PCIE_0_RC_CFG_PCIE_DEVICE_STATUS_CONTROL_NO_SNOOP_ENABLE_SHIFT 11
-#define BCHP_PCIE_0_RC_CFG_PCIE_DEVICE_STATUS_CONTROL_NO_SNOOP_ENABLE_DEFAULT 0x00000001
-
-/* PCIE_0_RC_CFG_PCIE :: DEVICE_STATUS_CONTROL :: AUX_PWR_PM_ENA [10:10] */
-#define BCHP_PCIE_0_RC_CFG_PCIE_DEVICE_STATUS_CONTROL_AUX_PWR_PM_ENA_MASK 0x00000400
-#define BCHP_PCIE_0_RC_CFG_PCIE_DEVICE_STATUS_CONTROL_AUX_PWR_PM_ENA_SHIFT 10
-#define BCHP_PCIE_0_RC_CFG_PCIE_DEVICE_STATUS_CONTROL_AUX_PWR_PM_ENA_DEFAULT 0x00000001
-
-/* PCIE_0_RC_CFG_PCIE :: DEVICE_STATUS_CONTROL :: RESERVED0 [09:09] */
-#define BCHP_PCIE_0_RC_CFG_PCIE_DEVICE_STATUS_CONTROL_RESERVED0_MASK 0x00000200
-#define BCHP_PCIE_0_RC_CFG_PCIE_DEVICE_STATUS_CONTROL_RESERVED0_SHIFT 9
-
-/* PCIE_0_RC_CFG_PCIE :: DEVICE_STATUS_CONTROL :: EXTENDED_TAG_EN [08:08] */
-#define BCHP_PCIE_0_RC_CFG_PCIE_DEVICE_STATUS_CONTROL_EXTENDED_TAG_EN_MASK 0x00000100
-#define BCHP_PCIE_0_RC_CFG_PCIE_DEVICE_STATUS_CONTROL_EXTENDED_TAG_EN_SHIFT 8
-#define BCHP_PCIE_0_RC_CFG_PCIE_DEVICE_STATUS_CONTROL_EXTENDED_TAG_EN_DEFAULT 0x00000000
-
-/* PCIE_0_RC_CFG_PCIE :: DEVICE_STATUS_CONTROL :: MAX_PAYLOAD_SIZE [07:05] */
-#define BCHP_PCIE_0_RC_CFG_PCIE_DEVICE_STATUS_CONTROL_MAX_PAYLOAD_SIZE_MASK 0x000000e0
-#define BCHP_PCIE_0_RC_CFG_PCIE_DEVICE_STATUS_CONTROL_MAX_PAYLOAD_SIZE_SHIFT 5
-#define BCHP_PCIE_0_RC_CFG_PCIE_DEVICE_STATUS_CONTROL_MAX_PAYLOAD_SIZE_DEFAULT 0x00000000
-
-/* PCIE_0_RC_CFG_PCIE :: DEVICE_STATUS_CONTROL :: RELAX_ORDERING_ENABLE [04:04] */
-#define BCHP_PCIE_0_RC_CFG_PCIE_DEVICE_STATUS_CONTROL_RELAX_ORDERING_ENABLE_MASK 0x00000010
-#define BCHP_PCIE_0_RC_CFG_PCIE_DEVICE_STATUS_CONTROL_RELAX_ORDERING_ENABLE_SHIFT 4
-#define BCHP_PCIE_0_RC_CFG_PCIE_DEVICE_STATUS_CONTROL_RELAX_ORDERING_ENABLE_DEFAULT 0x00000001
-
-/* PCIE_0_RC_CFG_PCIE :: DEVICE_STATUS_CONTROL :: U_REQ_REPORT_EN [03:03] */
-#define BCHP_PCIE_0_RC_CFG_PCIE_DEVICE_STATUS_CONTROL_U_REQ_REPORT_EN_MASK 0x00000008
-#define BCHP_PCIE_0_RC_CFG_PCIE_DEVICE_STATUS_CONTROL_U_REQ_REPORT_EN_SHIFT 3
-#define BCHP_PCIE_0_RC_CFG_PCIE_DEVICE_STATUS_CONTROL_U_REQ_REPORT_EN_DEFAULT 0x00000000
-
-/* PCIE_0_RC_CFG_PCIE :: DEVICE_STATUS_CONTROL :: FATAL_ERR_REPORT_EN [02:02] */
-#define BCHP_PCIE_0_RC_CFG_PCIE_DEVICE_STATUS_CONTROL_FATAL_ERR_REPORT_EN_MASK 0x00000004
-#define BCHP_PCIE_0_RC_CFG_PCIE_DEVICE_STATUS_CONTROL_FATAL_ERR_REPORT_EN_SHIFT 2
-#define BCHP_PCIE_0_RC_CFG_PCIE_DEVICE_STATUS_CONTROL_FATAL_ERR_REPORT_EN_DEFAULT 0x00000000
-
-/* PCIE_0_RC_CFG_PCIE :: DEVICE_STATUS_CONTROL :: NFATAL_ERR_REPORT_EN [01:01] */
-#define BCHP_PCIE_0_RC_CFG_PCIE_DEVICE_STATUS_CONTROL_NFATAL_ERR_REPORT_EN_MASK 0x00000002
-#define BCHP_PCIE_0_RC_CFG_PCIE_DEVICE_STATUS_CONTROL_NFATAL_ERR_REPORT_EN_SHIFT 1
-#define BCHP_PCIE_0_RC_CFG_PCIE_DEVICE_STATUS_CONTROL_NFATAL_ERR_REPORT_EN_DEFAULT 0x00000000
-
-/* PCIE_0_RC_CFG_PCIE :: DEVICE_STATUS_CONTROL :: CORR_ERR_REPORT_EN [00:00] */
-#define BCHP_PCIE_0_RC_CFG_PCIE_DEVICE_STATUS_CONTROL_CORR_ERR_REPORT_EN_MASK 0x00000001
-#define BCHP_PCIE_0_RC_CFG_PCIE_DEVICE_STATUS_CONTROL_CORR_ERR_REPORT_EN_SHIFT 0
-#define BCHP_PCIE_0_RC_CFG_PCIE_DEVICE_STATUS_CONTROL_CORR_ERR_REPORT_EN_DEFAULT 0x00000000
-
-/***************************************************************************
- *LINK_CAPABILITY - link_capability
- ***************************************************************************/
-/* PCIE_0_RC_CFG_PCIE :: LINK_CAPABILITY :: PORT_NUMBER [31:24] */
-#define BCHP_PCIE_0_RC_CFG_PCIE_LINK_CAPABILITY_PORT_NUMBER_MASK 0xff000000
-#define BCHP_PCIE_0_RC_CFG_PCIE_LINK_CAPABILITY_PORT_NUMBER_SHIFT 24
-#define BCHP_PCIE_0_RC_CFG_PCIE_LINK_CAPABILITY_PORT_NUMBER_DEFAULT 0x00000000
-
-/* PCIE_0_RC_CFG_PCIE :: LINK_CAPABILITY :: RESERVED0 [23:23] */
-#define BCHP_PCIE_0_RC_CFG_PCIE_LINK_CAPABILITY_RESERVED0_MASK 0x00800000
-#define BCHP_PCIE_0_RC_CFG_PCIE_LINK_CAPABILITY_RESERVED0_SHIFT 23
-
-/* PCIE_0_RC_CFG_PCIE :: LINK_CAPABILITY :: ASPM_OPTIONALITY [22:22] */
-#define BCHP_PCIE_0_RC_CFG_PCIE_LINK_CAPABILITY_ASPM_OPTIONALITY_MASK 0x00400000
-#define BCHP_PCIE_0_RC_CFG_PCIE_LINK_CAPABILITY_ASPM_OPTIONALITY_SHIFT 22
-#define BCHP_PCIE_0_RC_CFG_PCIE_LINK_CAPABILITY_ASPM_OPTIONALITY_DEFAULT 0x00000001
-
-/* PCIE_0_RC_CFG_PCIE :: LINK_CAPABILITY :: LINK_BW_NOTIFY [21:21] */
-#define BCHP_PCIE_0_RC_CFG_PCIE_LINK_CAPABILITY_LINK_BW_NOTIFY_MASK 0x00200000
-#define BCHP_PCIE_0_RC_CFG_PCIE_LINK_CAPABILITY_LINK_BW_NOTIFY_SHIFT 21
-#define BCHP_PCIE_0_RC_CFG_PCIE_LINK_CAPABILITY_LINK_BW_NOTIFY_DEFAULT 0x00000000
-
-/* PCIE_0_RC_CFG_PCIE :: LINK_CAPABILITY :: DL_ACTIVE_REP [20:20] */
-#define BCHP_PCIE_0_RC_CFG_PCIE_LINK_CAPABILITY_DL_ACTIVE_REP_MASK 0x00100000
-#define BCHP_PCIE_0_RC_CFG_PCIE_LINK_CAPABILITY_DL_ACTIVE_REP_SHIFT 20
-#define BCHP_PCIE_0_RC_CFG_PCIE_LINK_CAPABILITY_DL_ACTIVE_REP_DEFAULT 0x00000000
-
-/* PCIE_0_RC_CFG_PCIE :: LINK_CAPABILITY :: SUR_DWN_ERR_REP [19:19] */
-#define BCHP_PCIE_0_RC_CFG_PCIE_LINK_CAPABILITY_SUR_DWN_ERR_REP_MASK 0x00080000
-#define BCHP_PCIE_0_RC_CFG_PCIE_LINK_CAPABILITY_SUR_DWN_ERR_REP_SHIFT 19
-#define BCHP_PCIE_0_RC_CFG_PCIE_LINK_CAPABILITY_SUR_DWN_ERR_REP_DEFAULT 0x00000000
-
-/* PCIE_0_RC_CFG_PCIE :: LINK_CAPABILITY :: CLK_PWR_MGMT [18:18] */
-#define BCHP_PCIE_0_RC_CFG_PCIE_LINK_CAPABILITY_CLK_PWR_MGMT_MASK 0x00040000
-#define BCHP_PCIE_0_RC_CFG_PCIE_LINK_CAPABILITY_CLK_PWR_MGMT_SHIFT 18
-#define BCHP_PCIE_0_RC_CFG_PCIE_LINK_CAPABILITY_CLK_PWR_MGMT_DEFAULT 0x00000001
-
-/* PCIE_0_RC_CFG_PCIE :: LINK_CAPABILITY :: L1_EXIT_LAT [17:15] */
-#define BCHP_PCIE_0_RC_CFG_PCIE_LINK_CAPABILITY_L1_EXIT_LAT_MASK 0x00038000
-#define BCHP_PCIE_0_RC_CFG_PCIE_LINK_CAPABILITY_L1_EXIT_LAT_SHIFT 15
-#define BCHP_PCIE_0_RC_CFG_PCIE_LINK_CAPABILITY_L1_EXIT_LAT_DEFAULT 0x00000002
-
-/* PCIE_0_RC_CFG_PCIE :: LINK_CAPABILITY :: L0S_EXIT_LAT [14:12] */
-#define BCHP_PCIE_0_RC_CFG_PCIE_LINK_CAPABILITY_L0S_EXIT_LAT_MASK 0x00007000
-#define BCHP_PCIE_0_RC_CFG_PCIE_LINK_CAPABILITY_L0S_EXIT_LAT_SHIFT 12
-#define BCHP_PCIE_0_RC_CFG_PCIE_LINK_CAPABILITY_L0S_EXIT_LAT_DEFAULT 0x00000005
-
-/* PCIE_0_RC_CFG_PCIE :: LINK_CAPABILITY :: ASPM_SUPT [11:10] */
-#define BCHP_PCIE_0_RC_CFG_PCIE_LINK_CAPABILITY_ASPM_SUPT_MASK 0x00000c00
-#define BCHP_PCIE_0_RC_CFG_PCIE_LINK_CAPABILITY_ASPM_SUPT_SHIFT 10
-#define BCHP_PCIE_0_RC_CFG_PCIE_LINK_CAPABILITY_ASPM_SUPT_DEFAULT 0x00000003
-
-/* PCIE_0_RC_CFG_PCIE :: LINK_CAPABILITY :: MAX_LINK_WIDTH [09:04] */
-#define BCHP_PCIE_0_RC_CFG_PCIE_LINK_CAPABILITY_MAX_LINK_WIDTH_MASK 0x000003f0
-#define BCHP_PCIE_0_RC_CFG_PCIE_LINK_CAPABILITY_MAX_LINK_WIDTH_SHIFT 4
-#define BCHP_PCIE_0_RC_CFG_PCIE_LINK_CAPABILITY_MAX_LINK_WIDTH_DEFAULT 0x00000001
-
-/* PCIE_0_RC_CFG_PCIE :: LINK_CAPABILITY :: MAX_LINK_SPEED [03:00] */
-#define BCHP_PCIE_0_RC_CFG_PCIE_LINK_CAPABILITY_MAX_LINK_SPEED_MASK 0x0000000f
-#define BCHP_PCIE_0_RC_CFG_PCIE_LINK_CAPABILITY_MAX_LINK_SPEED_SHIFT 0
-#define BCHP_PCIE_0_RC_CFG_PCIE_LINK_CAPABILITY_MAX_LINK_SPEED_DEFAULT 0x00000002
-
-/***************************************************************************
- *LINK_STATUS_CONTROL - link_status_control
- ***************************************************************************/
-/* PCIE_0_RC_CFG_PCIE :: LINK_STATUS_CONTROL :: RESERVED3 [31:30] */
-#define BCHP_PCIE_0_RC_CFG_PCIE_LINK_STATUS_CONTROL_RESERVED3_MASK 0xc0000000
-#define BCHP_PCIE_0_RC_CFG_PCIE_LINK_STATUS_CONTROL_RESERVED3_SHIFT 30
-
-/* PCIE_0_RC_CFG_PCIE :: LINK_STATUS_CONTROL :: DL_ACTIVE [29:29] */
-#define BCHP_PCIE_0_RC_CFG_PCIE_LINK_STATUS_CONTROL_DL_ACTIVE_MASK 0x20000000
-#define BCHP_PCIE_0_RC_CFG_PCIE_LINK_STATUS_CONTROL_DL_ACTIVE_SHIFT 29
-#define BCHP_PCIE_0_RC_CFG_PCIE_LINK_STATUS_CONTROL_DL_ACTIVE_DEFAULT 0x00000000
-
-/* PCIE_0_RC_CFG_PCIE :: LINK_STATUS_CONTROL :: SLOT_CLK_CONFIG [28:28] */
-#define BCHP_PCIE_0_RC_CFG_PCIE_LINK_STATUS_CONTROL_SLOT_CLK_CONFIG_MASK 0x10000000
-#define BCHP_PCIE_0_RC_CFG_PCIE_LINK_STATUS_CONTROL_SLOT_CLK_CONFIG_SHIFT 28
-#define BCHP_PCIE_0_RC_CFG_PCIE_LINK_STATUS_CONTROL_SLOT_CLK_CONFIG_DEFAULT 0x00000001
-
-/* PCIE_0_RC_CFG_PCIE :: LINK_STATUS_CONTROL :: LINK_TRAINING [27:27] */
-#define BCHP_PCIE_0_RC_CFG_PCIE_LINK_STATUS_CONTROL_LINK_TRAINING_MASK 0x08000000
-#define BCHP_PCIE_0_RC_CFG_PCIE_LINK_STATUS_CONTROL_LINK_TRAINING_SHIFT 27
-#define BCHP_PCIE_0_RC_CFG_PCIE_LINK_STATUS_CONTROL_LINK_TRAINING_DEFAULT 0x00000000
-
-/* PCIE_0_RC_CFG_PCIE :: LINK_STATUS_CONTROL :: RESERVED2 [26:26] */
-#define BCHP_PCIE_0_RC_CFG_PCIE_LINK_STATUS_CONTROL_RESERVED2_MASK 0x04000000
-#define BCHP_PCIE_0_RC_CFG_PCIE_LINK_STATUS_CONTROL_RESERVED2_SHIFT 26
-
-/* PCIE_0_RC_CFG_PCIE :: LINK_STATUS_CONTROL :: NEG_LINK_WIDTH [25:20] */
-#define BCHP_PCIE_0_RC_CFG_PCIE_LINK_STATUS_CONTROL_NEG_LINK_WIDTH_MASK 0x03f00000
-#define BCHP_PCIE_0_RC_CFG_PCIE_LINK_STATUS_CONTROL_NEG_LINK_WIDTH_SHIFT 20
-#define BCHP_PCIE_0_RC_CFG_PCIE_LINK_STATUS_CONTROL_NEG_LINK_WIDTH_DEFAULT 0x00000000
-
-/* PCIE_0_RC_CFG_PCIE :: LINK_STATUS_CONTROL :: NEG_LINK_SPEED [19:16] */
-#define BCHP_PCIE_0_RC_CFG_PCIE_LINK_STATUS_CONTROL_NEG_LINK_SPEED_MASK 0x000f0000
-#define BCHP_PCIE_0_RC_CFG_PCIE_LINK_STATUS_CONTROL_NEG_LINK_SPEED_SHIFT 16
-#define BCHP_PCIE_0_RC_CFG_PCIE_LINK_STATUS_CONTROL_NEG_LINK_SPEED_DEFAULT 0x00000000
-
-/* PCIE_0_RC_CFG_PCIE :: LINK_STATUS_CONTROL :: RESERVED1 [15:12] */
-#define BCHP_PCIE_0_RC_CFG_PCIE_LINK_STATUS_CONTROL_RESERVED1_MASK 0x0000f000
-#define BCHP_PCIE_0_RC_CFG_PCIE_LINK_STATUS_CONTROL_RESERVED1_SHIFT 12
-
-/* PCIE_0_RC_CFG_PCIE :: LINK_STATUS_CONTROL :: LINK_BW_INT_EN [11:11] */
-#define BCHP_PCIE_0_RC_CFG_PCIE_LINK_STATUS_CONTROL_LINK_BW_INT_EN_MASK 0x00000800
-#define BCHP_PCIE_0_RC_CFG_PCIE_LINK_STATUS_CONTROL_LINK_BW_INT_EN_SHIFT 11
-#define BCHP_PCIE_0_RC_CFG_PCIE_LINK_STATUS_CONTROL_LINK_BW_INT_EN_DEFAULT 0x00000000
-
-/* PCIE_0_RC_CFG_PCIE :: LINK_STATUS_CONTROL :: LINK_BW_MGMT_INT_EN [10:10] */
-#define BCHP_PCIE_0_RC_CFG_PCIE_LINK_STATUS_CONTROL_LINK_BW_MGMT_INT_EN_MASK 0x00000400
-#define BCHP_PCIE_0_RC_CFG_PCIE_LINK_STATUS_CONTROL_LINK_BW_MGMT_INT_EN_SHIFT 10
-#define BCHP_PCIE_0_RC_CFG_PCIE_LINK_STATUS_CONTROL_LINK_BW_MGMT_INT_EN_DEFAULT 0x00000000
-
-/* PCIE_0_RC_CFG_PCIE :: LINK_STATUS_CONTROL :: HW_AUTO_WIDTH_DIS [09:09] */
-#define BCHP_PCIE_0_RC_CFG_PCIE_LINK_STATUS_CONTROL_HW_AUTO_WIDTH_DIS_MASK 0x00000200
-#define BCHP_PCIE_0_RC_CFG_PCIE_LINK_STATUS_CONTROL_HW_AUTO_WIDTH_DIS_SHIFT 9
-#define BCHP_PCIE_0_RC_CFG_PCIE_LINK_STATUS_CONTROL_HW_AUTO_WIDTH_DIS_DEFAULT 0x00000000
-
-/* PCIE_0_RC_CFG_PCIE :: LINK_STATUS_CONTROL :: EN_CLK_PW_MGMT [08:08] */
-#define BCHP_PCIE_0_RC_CFG_PCIE_LINK_STATUS_CONTROL_EN_CLK_PW_MGMT_MASK 0x00000100
-#define BCHP_PCIE_0_RC_CFG_PCIE_LINK_STATUS_CONTROL_EN_CLK_PW_MGMT_SHIFT 8
-#define BCHP_PCIE_0_RC_CFG_PCIE_LINK_STATUS_CONTROL_EN_CLK_PW_MGMT_DEFAULT 0x00000000
-
-/* PCIE_0_RC_CFG_PCIE :: LINK_STATUS_CONTROL :: LINK_CR_EXT_SYNC [07:07] */
-#define BCHP_PCIE_0_RC_CFG_PCIE_LINK_STATUS_CONTROL_LINK_CR_EXT_SYNC_MASK 0x00000080
-#define BCHP_PCIE_0_RC_CFG_PCIE_LINK_STATUS_CONTROL_LINK_CR_EXT_SYNC_SHIFT 7
-#define BCHP_PCIE_0_RC_CFG_PCIE_LINK_STATUS_CONTROL_LINK_CR_EXT_SYNC_DEFAULT 0x00000000
-
-/* PCIE_0_RC_CFG_PCIE :: LINK_STATUS_CONTROL :: LINK_CR_COMMON_CLK [06:06] */
-#define BCHP_PCIE_0_RC_CFG_PCIE_LINK_STATUS_CONTROL_LINK_CR_COMMON_CLK_MASK 0x00000040
-#define BCHP_PCIE_0_RC_CFG_PCIE_LINK_STATUS_CONTROL_LINK_CR_COMMON_CLK_SHIFT 6
-#define BCHP_PCIE_0_RC_CFG_PCIE_LINK_STATUS_CONTROL_LINK_CR_COMMON_CLK_DEFAULT 0x00000000
-
-/* PCIE_0_RC_CFG_PCIE :: LINK_STATUS_CONTROL :: CFG_PSM_RETRAIN_LINK [05:05] */
-#define BCHP_PCIE_0_RC_CFG_PCIE_LINK_STATUS_CONTROL_CFG_PSM_RETRAIN_LINK_MASK 0x00000020
-#define BCHP_PCIE_0_RC_CFG_PCIE_LINK_STATUS_CONTROL_CFG_PSM_RETRAIN_LINK_SHIFT 5
-#define BCHP_PCIE_0_RC_CFG_PCIE_LINK_STATUS_CONTROL_CFG_PSM_RETRAIN_LINK_DEFAULT 0x00000000
-
-/* PCIE_0_RC_CFG_PCIE :: LINK_STATUS_CONTROL :: CFG_PSM_LINK_DISABLE [04:04] */
-#define BCHP_PCIE_0_RC_CFG_PCIE_LINK_STATUS_CONTROL_CFG_PSM_LINK_DISABLE_MASK 0x00000010
-#define BCHP_PCIE_0_RC_CFG_PCIE_LINK_STATUS_CONTROL_CFG_PSM_LINK_DISABLE_SHIFT 4
-#define BCHP_PCIE_0_RC_CFG_PCIE_LINK_STATUS_CONTROL_CFG_PSM_LINK_DISABLE_DEFAULT 0x00000000
-
-/* PCIE_0_RC_CFG_PCIE :: LINK_STATUS_CONTROL :: RCB [03:03] */
-#define BCHP_PCIE_0_RC_CFG_PCIE_LINK_STATUS_CONTROL_RCB_MASK 0x00000008
-#define BCHP_PCIE_0_RC_CFG_PCIE_LINK_STATUS_CONTROL_RCB_SHIFT 3
-#define BCHP_PCIE_0_RC_CFG_PCIE_LINK_STATUS_CONTROL_RCB_DEFAULT 0x00000000
-
-/* PCIE_0_RC_CFG_PCIE :: LINK_STATUS_CONTROL :: RESERVED0 [02:02] */
-#define BCHP_PCIE_0_RC_CFG_PCIE_LINK_STATUS_CONTROL_RESERVED0_MASK 0x00000004
-#define BCHP_PCIE_0_RC_CFG_PCIE_LINK_STATUS_CONTROL_RESERVED0_SHIFT 2
-
-/* PCIE_0_RC_CFG_PCIE :: LINK_STATUS_CONTROL :: ASPM_CTRL [01:00] */
-#define BCHP_PCIE_0_RC_CFG_PCIE_LINK_STATUS_CONTROL_ASPM_CTRL_MASK 0x00000003
-#define BCHP_PCIE_0_RC_CFG_PCIE_LINK_STATUS_CONTROL_ASPM_CTRL_SHIFT 0
-#define BCHP_PCIE_0_RC_CFG_PCIE_LINK_STATUS_CONTROL_ASPM_CTRL_DEFAULT 0x00000000
-
-/***************************************************************************
- *SLOT_CAPABILITY - slot_capability
- ***************************************************************************/
-/* PCIE_0_RC_CFG_PCIE :: SLOT_CAPABILITY :: PHYSICAL_SLOT_NUMBER [31:19] */
-#define BCHP_PCIE_0_RC_CFG_PCIE_SLOT_CAPABILITY_PHYSICAL_SLOT_NUMBER_MASK 0xfff80000
-#define BCHP_PCIE_0_RC_CFG_PCIE_SLOT_CAPABILITY_PHYSICAL_SLOT_NUMBER_SHIFT 19
-#define BCHP_PCIE_0_RC_CFG_PCIE_SLOT_CAPABILITY_PHYSICAL_SLOT_NUMBER_DEFAULT 0x00000000
-
-/* PCIE_0_RC_CFG_PCIE :: SLOT_CAPABILITY :: UNUSED [18:17] */
-#define BCHP_PCIE_0_RC_CFG_PCIE_SLOT_CAPABILITY_UNUSED_MASK 0x00060000
-#define BCHP_PCIE_0_RC_CFG_PCIE_SLOT_CAPABILITY_UNUSED_SHIFT 17
-#define BCHP_PCIE_0_RC_CFG_PCIE_SLOT_CAPABILITY_UNUSED_DEFAULT 0x00000000
-
-/* PCIE_0_RC_CFG_PCIE :: SLOT_CAPABILITY :: SLOT_POWER_LIMIT_SCALE [16:15] */
-#define BCHP_PCIE_0_RC_CFG_PCIE_SLOT_CAPABILITY_SLOT_POWER_LIMIT_SCALE_MASK 0x00018000
-#define BCHP_PCIE_0_RC_CFG_PCIE_SLOT_CAPABILITY_SLOT_POWER_LIMIT_SCALE_SHIFT 15
-#define BCHP_PCIE_0_RC_CFG_PCIE_SLOT_CAPABILITY_SLOT_POWER_LIMIT_SCALE_DEFAULT 0x00000000
-
-/* PCIE_0_RC_CFG_PCIE :: SLOT_CAPABILITY :: SLOT_POWER_LIMIT_VALUE [14:07] */
-#define BCHP_PCIE_0_RC_CFG_PCIE_SLOT_CAPABILITY_SLOT_POWER_LIMIT_VALUE_MASK 0x00007f80
-#define BCHP_PCIE_0_RC_CFG_PCIE_SLOT_CAPABILITY_SLOT_POWER_LIMIT_VALUE_SHIFT 7
-#define BCHP_PCIE_0_RC_CFG_PCIE_SLOT_CAPABILITY_SLOT_POWER_LIMIT_VALUE_DEFAULT 0x00000000
-
-/* PCIE_0_RC_CFG_PCIE :: SLOT_CAPABILITY :: UNUSED_2 [06:00] */
-#define BCHP_PCIE_0_RC_CFG_PCIE_SLOT_CAPABILITY_UNUSED_2_MASK 0x0000007f
-#define BCHP_PCIE_0_RC_CFG_PCIE_SLOT_CAPABILITY_UNUSED_2_SHIFT 0
-#define BCHP_PCIE_0_RC_CFG_PCIE_SLOT_CAPABILITY_UNUSED_2_DEFAULT 0x00000000
-
-/***************************************************************************
- *SLOT_CONTROL_STATUS - slot_control_status
- ***************************************************************************/
-/* PCIE_0_RC_CFG_PCIE :: SLOT_CONTROL_STATUS :: SLOT_STATUS [31:23] */
-#define BCHP_PCIE_0_RC_CFG_PCIE_SLOT_CONTROL_STATUS_SLOT_STATUS_MASK 0xff800000
-#define BCHP_PCIE_0_RC_CFG_PCIE_SLOT_CONTROL_STATUS_SLOT_STATUS_SHIFT 23
-#define BCHP_PCIE_0_RC_CFG_PCIE_SLOT_CONTROL_STATUS_SLOT_STATUS_DEFAULT 0x00000000
-
-/* PCIE_0_RC_CFG_PCIE :: SLOT_CONTROL_STATUS :: PRESENCE_DETECT [22:22] */
-#define BCHP_PCIE_0_RC_CFG_PCIE_SLOT_CONTROL_STATUS_PRESENCE_DETECT_MASK 0x00400000
-#define BCHP_PCIE_0_RC_CFG_PCIE_SLOT_CONTROL_STATUS_PRESENCE_DETECT_SHIFT 22
-#define BCHP_PCIE_0_RC_CFG_PCIE_SLOT_CONTROL_STATUS_PRESENCE_DETECT_DEFAULT 0x00000001
-
-/* PCIE_0_RC_CFG_PCIE :: SLOT_CONTROL_STATUS :: UNUSED_1 [21:16] */
-#define BCHP_PCIE_0_RC_CFG_PCIE_SLOT_CONTROL_STATUS_UNUSED_1_MASK 0x003f0000
-#define BCHP_PCIE_0_RC_CFG_PCIE_SLOT_CONTROL_STATUS_UNUSED_1_SHIFT 16
-#define BCHP_PCIE_0_RC_CFG_PCIE_SLOT_CONTROL_STATUS_UNUSED_1_DEFAULT 0x00000000
-
-/* PCIE_0_RC_CFG_PCIE :: SLOT_CONTROL_STATUS :: SLOT_CONTROL [15:00] */
-#define BCHP_PCIE_0_RC_CFG_PCIE_SLOT_CONTROL_STATUS_SLOT_CONTROL_MASK 0x0000ffff
-#define BCHP_PCIE_0_RC_CFG_PCIE_SLOT_CONTROL_STATUS_SLOT_CONTROL_SHIFT 0
-#define BCHP_PCIE_0_RC_CFG_PCIE_SLOT_CONTROL_STATUS_SLOT_CONTROL_DEFAULT 0x00000000
-
-/***************************************************************************
- *ROOT_CAP_CONTROL - root_cap_control
- ***************************************************************************/
-/* PCIE_0_RC_CFG_PCIE :: ROOT_CAP_CONTROL :: RESERVED1 [31:17] */
-#define BCHP_PCIE_0_RC_CFG_PCIE_ROOT_CAP_CONTROL_RESERVED1_MASK 0xfffe0000
-#define BCHP_PCIE_0_RC_CFG_PCIE_ROOT_CAP_CONTROL_RESERVED1_SHIFT 17
-
-/* PCIE_0_RC_CFG_PCIE :: ROOT_CAP_CONTROL :: RC_CRS_VISIBILITY [16:16] */
-#define BCHP_PCIE_0_RC_CFG_PCIE_ROOT_CAP_CONTROL_RC_CRS_VISIBILITY_MASK 0x00010000
-#define BCHP_PCIE_0_RC_CFG_PCIE_ROOT_CAP_CONTROL_RC_CRS_VISIBILITY_SHIFT 16
-#define BCHP_PCIE_0_RC_CFG_PCIE_ROOT_CAP_CONTROL_RC_CRS_VISIBILITY_DEFAULT 0x00000001
-
-/* PCIE_0_RC_CFG_PCIE :: ROOT_CAP_CONTROL :: RESERVED0 [15:05] */
-#define BCHP_PCIE_0_RC_CFG_PCIE_ROOT_CAP_CONTROL_RESERVED0_MASK 0x0000ffe0
-#define BCHP_PCIE_0_RC_CFG_PCIE_ROOT_CAP_CONTROL_RESERVED0_SHIFT 5
-
-/* PCIE_0_RC_CFG_PCIE :: ROOT_CAP_CONTROL :: RC_CRS_EN [04:04] */
-#define BCHP_PCIE_0_RC_CFG_PCIE_ROOT_CAP_CONTROL_RC_CRS_EN_MASK 0x00000010
-#define BCHP_PCIE_0_RC_CFG_PCIE_ROOT_CAP_CONTROL_RC_CRS_EN_SHIFT 4
-#define BCHP_PCIE_0_RC_CFG_PCIE_ROOT_CAP_CONTROL_RC_CRS_EN_DEFAULT 0x00000000
-
-/* PCIE_0_RC_CFG_PCIE :: ROOT_CAP_CONTROL :: RC_PME_INT_EN [03:03] */
-#define BCHP_PCIE_0_RC_CFG_PCIE_ROOT_CAP_CONTROL_RC_PME_INT_EN_MASK 0x00000008
-#define BCHP_PCIE_0_RC_CFG_PCIE_ROOT_CAP_CONTROL_RC_PME_INT_EN_SHIFT 3
-#define BCHP_PCIE_0_RC_CFG_PCIE_ROOT_CAP_CONTROL_RC_PME_INT_EN_DEFAULT 0x00000000
-
-/* PCIE_0_RC_CFG_PCIE :: ROOT_CAP_CONTROL :: RC_FATAL_SERR_EN [02:02] */
-#define BCHP_PCIE_0_RC_CFG_PCIE_ROOT_CAP_CONTROL_RC_FATAL_SERR_EN_MASK 0x00000004
-#define BCHP_PCIE_0_RC_CFG_PCIE_ROOT_CAP_CONTROL_RC_FATAL_SERR_EN_SHIFT 2
-#define BCHP_PCIE_0_RC_CFG_PCIE_ROOT_CAP_CONTROL_RC_FATAL_SERR_EN_DEFAULT 0x00000000
-
-/* PCIE_0_RC_CFG_PCIE :: ROOT_CAP_CONTROL :: RC_NONFATAL_SERR_EN [01:01] */
-#define BCHP_PCIE_0_RC_CFG_PCIE_ROOT_CAP_CONTROL_RC_NONFATAL_SERR_EN_MASK 0x00000002
-#define BCHP_PCIE_0_RC_CFG_PCIE_ROOT_CAP_CONTROL_RC_NONFATAL_SERR_EN_SHIFT 1
-#define BCHP_PCIE_0_RC_CFG_PCIE_ROOT_CAP_CONTROL_RC_NONFATAL_SERR_EN_DEFAULT 0x00000000
-
-/* PCIE_0_RC_CFG_PCIE :: ROOT_CAP_CONTROL :: RC_CORR_SERR_EN [00:00] */
-#define BCHP_PCIE_0_RC_CFG_PCIE_ROOT_CAP_CONTROL_RC_CORR_SERR_EN_MASK 0x00000001
-#define BCHP_PCIE_0_RC_CFG_PCIE_ROOT_CAP_CONTROL_RC_CORR_SERR_EN_SHIFT 0
-#define BCHP_PCIE_0_RC_CFG_PCIE_ROOT_CAP_CONTROL_RC_CORR_SERR_EN_DEFAULT 0x00000000
-
-/***************************************************************************
- *ROOT_STATUS - root_status
- ***************************************************************************/
-/* PCIE_0_RC_CFG_PCIE :: ROOT_STATUS :: RESERVED0 [31:18] */
-#define BCHP_PCIE_0_RC_CFG_PCIE_ROOT_STATUS_RESERVED0_MASK 0xfffc0000
-#define BCHP_PCIE_0_RC_CFG_PCIE_ROOT_STATUS_RESERVED0_SHIFT 18
-
-/* PCIE_0_RC_CFG_PCIE :: ROOT_STATUS :: RC_PME_PENDING [17:17] */
-#define BCHP_PCIE_0_RC_CFG_PCIE_ROOT_STATUS_RC_PME_PENDING_MASK 0x00020000
-#define BCHP_PCIE_0_RC_CFG_PCIE_ROOT_STATUS_RC_PME_PENDING_SHIFT 17
-#define BCHP_PCIE_0_RC_CFG_PCIE_ROOT_STATUS_RC_PME_PENDING_DEFAULT 0x00000000
-
-/* PCIE_0_RC_CFG_PCIE :: ROOT_STATUS :: RC_PME_STATUS [16:16] */
-#define BCHP_PCIE_0_RC_CFG_PCIE_ROOT_STATUS_RC_PME_STATUS_MASK 0x00010000
-#define BCHP_PCIE_0_RC_CFG_PCIE_ROOT_STATUS_RC_PME_STATUS_SHIFT 16
-#define BCHP_PCIE_0_RC_CFG_PCIE_ROOT_STATUS_RC_PME_STATUS_DEFAULT 0x00000000
-
-/* PCIE_0_RC_CFG_PCIE :: ROOT_STATUS :: RC_PME_REQ_ID [15:00] */
-#define BCHP_PCIE_0_RC_CFG_PCIE_ROOT_STATUS_RC_PME_REQ_ID_MASK 0x0000ffff
-#define BCHP_PCIE_0_RC_CFG_PCIE_ROOT_STATUS_RC_PME_REQ_ID_SHIFT 0
-#define BCHP_PCIE_0_RC_CFG_PCIE_ROOT_STATUS_RC_PME_REQ_ID_DEFAULT 0x00000000
-
-/***************************************************************************
- *DEVICE_CAPABILITY_2 - device_capability_2
- ***************************************************************************/
-/* PCIE_0_RC_CFG_PCIE :: DEVICE_CAPABILITY_2 :: RESERVED0 [31:05] */
-#define BCHP_PCIE_0_RC_CFG_PCIE_DEVICE_CAPABILITY_2_RESERVED0_MASK 0xffffffe0
-#define BCHP_PCIE_0_RC_CFG_PCIE_DEVICE_CAPABILITY_2_RESERVED0_SHIFT 5
-
-/* PCIE_0_RC_CFG_PCIE :: DEVICE_CAPABILITY_2 :: CMPL_TIMEOUT_DISABL_SUPPORTED [04:04] */
-#define BCHP_PCIE_0_RC_CFG_PCIE_DEVICE_CAPABILITY_2_CMPL_TIMEOUT_DISABL_SUPPORTED_MASK 0x00000010
-#define BCHP_PCIE_0_RC_CFG_PCIE_DEVICE_CAPABILITY_2_CMPL_TIMEOUT_DISABL_SUPPORTED_SHIFT 4
-#define BCHP_PCIE_0_RC_CFG_PCIE_DEVICE_CAPABILITY_2_CMPL_TIMEOUT_DISABL_SUPPORTED_DEFAULT 0x00000001
-
-/* PCIE_0_RC_CFG_PCIE :: DEVICE_CAPABILITY_2 :: CMPL_TIMEOUT_RANGES_SUPPORTED [03:00] */
-#define BCHP_PCIE_0_RC_CFG_PCIE_DEVICE_CAPABILITY_2_CMPL_TIMEOUT_RANGES_SUPPORTED_MASK 0x0000000f
-#define BCHP_PCIE_0_RC_CFG_PCIE_DEVICE_CAPABILITY_2_CMPL_TIMEOUT_RANGES_SUPPORTED_SHIFT 0
-#define BCHP_PCIE_0_RC_CFG_PCIE_DEVICE_CAPABILITY_2_CMPL_TIMEOUT_RANGES_SUPPORTED_DEFAULT 0x0000000f
-
-/***************************************************************************
- *DEVICE_STATUS_CONTROL_2 - device_status_control_2
- ***************************************************************************/
-/* PCIE_0_RC_CFG_PCIE :: DEVICE_STATUS_CONTROL_2 :: DEVICE_STATUS_2 [31:16] */
-#define BCHP_PCIE_0_RC_CFG_PCIE_DEVICE_STATUS_CONTROL_2_DEVICE_STATUS_2_MASK 0xffff0000
-#define BCHP_PCIE_0_RC_CFG_PCIE_DEVICE_STATUS_CONTROL_2_DEVICE_STATUS_2_SHIFT 16
-#define BCHP_PCIE_0_RC_CFG_PCIE_DEVICE_STATUS_CONTROL_2_DEVICE_STATUS_2_DEFAULT 0x00000000
-
-/* PCIE_0_RC_CFG_PCIE :: DEVICE_STATUS_CONTROL_2 :: RESERVED0 [15:05] */
-#define BCHP_PCIE_0_RC_CFG_PCIE_DEVICE_STATUS_CONTROL_2_RESERVED0_MASK 0x0000ffe0
-#define BCHP_PCIE_0_RC_CFG_PCIE_DEVICE_STATUS_CONTROL_2_RESERVED0_SHIFT 5
-
-/* PCIE_0_RC_CFG_PCIE :: DEVICE_STATUS_CONTROL_2 :: CMPL_TIMEOUT_DISABLE [04:04] */
-#define BCHP_PCIE_0_RC_CFG_PCIE_DEVICE_STATUS_CONTROL_2_CMPL_TIMEOUT_DISABLE_MASK 0x00000010
-#define BCHP_PCIE_0_RC_CFG_PCIE_DEVICE_STATUS_CONTROL_2_CMPL_TIMEOUT_DISABLE_SHIFT 4
-#define BCHP_PCIE_0_RC_CFG_PCIE_DEVICE_STATUS_CONTROL_2_CMPL_TIMEOUT_DISABLE_DEFAULT 0x00000000
-
-/* PCIE_0_RC_CFG_PCIE :: DEVICE_STATUS_CONTROL_2 :: CMPL_TIMEOUT_VALUE [03:00] */
-#define BCHP_PCIE_0_RC_CFG_PCIE_DEVICE_STATUS_CONTROL_2_CMPL_TIMEOUT_VALUE_MASK 0x0000000f
-#define BCHP_PCIE_0_RC_CFG_PCIE_DEVICE_STATUS_CONTROL_2_CMPL_TIMEOUT_VALUE_SHIFT 0
-#define BCHP_PCIE_0_RC_CFG_PCIE_DEVICE_STATUS_CONTROL_2_CMPL_TIMEOUT_VALUE_DEFAULT 0x00000000
-
-/***************************************************************************
- *LINK_CAPABILITY_2 - link_capability_2
- ***************************************************************************/
-/* PCIE_0_RC_CFG_PCIE :: LINK_CAPABILITY_2 :: LINK_CAPABILITY_2 [31:00] */
-#define BCHP_PCIE_0_RC_CFG_PCIE_LINK_CAPABILITY_2_LINK_CAPABILITY_2_MASK 0xffffffff
-#define BCHP_PCIE_0_RC_CFG_PCIE_LINK_CAPABILITY_2_LINK_CAPABILITY_2_SHIFT 0
-#define BCHP_PCIE_0_RC_CFG_PCIE_LINK_CAPABILITY_2_LINK_CAPABILITY_2_DEFAULT 0x00000000
-
-/***************************************************************************
- *LINK_STATUS_CONTROL_2 - link_status_control_2
- ***************************************************************************/
-/* PCIE_0_RC_CFG_PCIE :: LINK_STATUS_CONTROL_2 :: LINK_STATUS_2 [31:17] */
-#define BCHP_PCIE_0_RC_CFG_PCIE_LINK_STATUS_CONTROL_2_LINK_STATUS_2_MASK 0xfffe0000
-#define BCHP_PCIE_0_RC_CFG_PCIE_LINK_STATUS_CONTROL_2_LINK_STATUS_2_SHIFT 17
-#define BCHP_PCIE_0_RC_CFG_PCIE_LINK_STATUS_CONTROL_2_LINK_STATUS_2_DEFAULT 0x00000000
-
-/* PCIE_0_RC_CFG_PCIE :: LINK_STATUS_CONTROL_2 :: CURR_DEEMPH_LEVEL [16:16] */
-#define BCHP_PCIE_0_RC_CFG_PCIE_LINK_STATUS_CONTROL_2_CURR_DEEMPH_LEVEL_MASK 0x00010000
-#define BCHP_PCIE_0_RC_CFG_PCIE_LINK_STATUS_CONTROL_2_CURR_DEEMPH_LEVEL_SHIFT 16
-#define BCHP_PCIE_0_RC_CFG_PCIE_LINK_STATUS_CONTROL_2_CURR_DEEMPH_LEVEL_DEFAULT 0x00000000
-
-/* PCIE_0_RC_CFG_PCIE :: LINK_STATUS_CONTROL_2 :: RESERVED0 [15:13] */
-#define BCHP_PCIE_0_RC_CFG_PCIE_LINK_STATUS_CONTROL_2_RESERVED0_MASK 0x0000e000
-#define BCHP_PCIE_0_RC_CFG_PCIE_LINK_STATUS_CONTROL_2_RESERVED0_SHIFT 13
-
-/* PCIE_0_RC_CFG_PCIE :: LINK_STATUS_CONTROL_2 :: CFG_COMPLIANCE_DEEMPH [12:12] */
-#define BCHP_PCIE_0_RC_CFG_PCIE_LINK_STATUS_CONTROL_2_CFG_COMPLIANCE_DEEMPH_MASK 0x00001000
-#define BCHP_PCIE_0_RC_CFG_PCIE_LINK_STATUS_CONTROL_2_CFG_COMPLIANCE_DEEMPH_SHIFT 12
-#define BCHP_PCIE_0_RC_CFG_PCIE_LINK_STATUS_CONTROL_2_CFG_COMPLIANCE_DEEMPH_DEFAULT 0x00000000
-
-/* PCIE_0_RC_CFG_PCIE :: LINK_STATUS_CONTROL_2 :: CFG_COMPLIANCE_SOS [11:11] */
-#define BCHP_PCIE_0_RC_CFG_PCIE_LINK_STATUS_CONTROL_2_CFG_COMPLIANCE_SOS_MASK 0x00000800
-#define BCHP_PCIE_0_RC_CFG_PCIE_LINK_STATUS_CONTROL_2_CFG_COMPLIANCE_SOS_SHIFT 11
-#define BCHP_PCIE_0_RC_CFG_PCIE_LINK_STATUS_CONTROL_2_CFG_COMPLIANCE_SOS_DEFAULT 0x00000000
-
-/* PCIE_0_RC_CFG_PCIE :: LINK_STATUS_CONTROL_2 :: CFG_ENTER_MOD_COMPLIANCE [10:10] */
-#define BCHP_PCIE_0_RC_CFG_PCIE_LINK_STATUS_CONTROL_2_CFG_ENTER_MOD_COMPLIANCE_MASK 0x00000400
-#define BCHP_PCIE_0_RC_CFG_PCIE_LINK_STATUS_CONTROL_2_CFG_ENTER_MOD_COMPLIANCE_SHIFT 10
-#define BCHP_PCIE_0_RC_CFG_PCIE_LINK_STATUS_CONTROL_2_CFG_ENTER_MOD_COMPLIANCE_DEFAULT 0x00000000
-
-/* PCIE_0_RC_CFG_PCIE :: LINK_STATUS_CONTROL_2 :: CFG_TX_MARGIN [09:07] */
-#define BCHP_PCIE_0_RC_CFG_PCIE_LINK_STATUS_CONTROL_2_CFG_TX_MARGIN_MASK 0x00000380
-#define BCHP_PCIE_0_RC_CFG_PCIE_LINK_STATUS_CONTROL_2_CFG_TX_MARGIN_SHIFT 7
-#define BCHP_PCIE_0_RC_CFG_PCIE_LINK_STATUS_CONTROL_2_CFG_TX_MARGIN_DEFAULT 0x00000000
-
-/* PCIE_0_RC_CFG_PCIE :: LINK_STATUS_CONTROL_2 :: SEL_DEEMPHASIS [06:06] */
-#define BCHP_PCIE_0_RC_CFG_PCIE_LINK_STATUS_CONTROL_2_SEL_DEEMPHASIS_MASK 0x00000040
-#define BCHP_PCIE_0_RC_CFG_PCIE_LINK_STATUS_CONTROL_2_SEL_DEEMPHASIS_SHIFT 6
-#define BCHP_PCIE_0_RC_CFG_PCIE_LINK_STATUS_CONTROL_2_SEL_DEEMPHASIS_DEFAULT 0x00000000
-
-/* PCIE_0_RC_CFG_PCIE :: LINK_STATUS_CONTROL_2 :: HW_AUTO_SPEED_DISABLE [05:05] */
-#define BCHP_PCIE_0_RC_CFG_PCIE_LINK_STATUS_CONTROL_2_HW_AUTO_SPEED_DISABLE_MASK 0x00000020
-#define BCHP_PCIE_0_RC_CFG_PCIE_LINK_STATUS_CONTROL_2_HW_AUTO_SPEED_DISABLE_SHIFT 5
-#define BCHP_PCIE_0_RC_CFG_PCIE_LINK_STATUS_CONTROL_2_HW_AUTO_SPEED_DISABLE_DEFAULT 0x00000000
-
-/* PCIE_0_RC_CFG_PCIE :: LINK_STATUS_CONTROL_2 :: ENTER_COMPLIANCE [04:04] */
-#define BCHP_PCIE_0_RC_CFG_PCIE_LINK_STATUS_CONTROL_2_ENTER_COMPLIANCE_MASK 0x00000010
-#define BCHP_PCIE_0_RC_CFG_PCIE_LINK_STATUS_CONTROL_2_ENTER_COMPLIANCE_SHIFT 4
-#define BCHP_PCIE_0_RC_CFG_PCIE_LINK_STATUS_CONTROL_2_ENTER_COMPLIANCE_DEFAULT 0x00000000
-
-/* PCIE_0_RC_CFG_PCIE :: LINK_STATUS_CONTROL_2 :: TARGET_LINK_SPEED [03:00] */
-#define BCHP_PCIE_0_RC_CFG_PCIE_LINK_STATUS_CONTROL_2_TARGET_LINK_SPEED_MASK 0x0000000f
-#define BCHP_PCIE_0_RC_CFG_PCIE_LINK_STATUS_CONTROL_2_TARGET_LINK_SPEED_SHIFT 0
-#define BCHP_PCIE_0_RC_CFG_PCIE_LINK_STATUS_CONTROL_2_TARGET_LINK_SPEED_DEFAULT 0x00000001
-
-/***************************************************************************
- *SLOT_CAPABILITY_2 - slot_capability_2
- ***************************************************************************/
-/* PCIE_0_RC_CFG_PCIE :: SLOT_CAPABILITY_2 :: SLOT_CAPABILITY_2 [31:00] */
-#define BCHP_PCIE_0_RC_CFG_PCIE_SLOT_CAPABILITY_2_SLOT_CAPABILITY_2_MASK 0xffffffff
-#define BCHP_PCIE_0_RC_CFG_PCIE_SLOT_CAPABILITY_2_SLOT_CAPABILITY_2_SHIFT 0
-#define BCHP_PCIE_0_RC_CFG_PCIE_SLOT_CAPABILITY_2_SLOT_CAPABILITY_2_DEFAULT 0x00000000
-
-/***************************************************************************
- *SLOT_STATUS_CONTROL_2 - slot_status_control_2
- ***************************************************************************/
-/* PCIE_0_RC_CFG_PCIE :: SLOT_STATUS_CONTROL_2 :: SLOT_STATUS_2 [31:16] */
-#define BCHP_PCIE_0_RC_CFG_PCIE_SLOT_STATUS_CONTROL_2_SLOT_STATUS_2_MASK 0xffff0000
-#define BCHP_PCIE_0_RC_CFG_PCIE_SLOT_STATUS_CONTROL_2_SLOT_STATUS_2_SHIFT 16
-#define BCHP_PCIE_0_RC_CFG_PCIE_SLOT_STATUS_CONTROL_2_SLOT_STATUS_2_DEFAULT 0x00000000
-
-/* PCIE_0_RC_CFG_PCIE :: SLOT_STATUS_CONTROL_2 :: SLOT_CONTROL_2 [15:00] */
-#define BCHP_PCIE_0_RC_CFG_PCIE_SLOT_STATUS_CONTROL_2_SLOT_CONTROL_2_MASK 0x0000ffff
-#define BCHP_PCIE_0_RC_CFG_PCIE_SLOT_STATUS_CONTROL_2_SLOT_CONTROL_2_SHIFT 0
-#define BCHP_PCIE_0_RC_CFG_PCIE_SLOT_STATUS_CONTROL_2_SLOT_CONTROL_2_DEFAULT 0x00000000
-
-#endif /* #ifndef BCHP_PCIE_0_RC_CFG_PCIE_H__ */
-
-/* End of File */
diff --git a/include/linux/brcmstb/7366b0/bchp_pcie_0_rc_cfg_type1.h b/include/linux/brcmstb/7366b0/bchp_pcie_0_rc_cfg_type1.h
deleted file mode 100644
index 5089681..0000000
--- a/include/linux/brcmstb/7366b0/bchp_pcie_0_rc_cfg_type1.h
+++ /dev/null
@@ -1,526 +0,0 @@
-/***************************************************************************
- * Copyright (c) 1999-2013, Broadcom Corporation
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
- *
- * Module Description:
- * DO NOT EDIT THIS FILE DIRECTLY
- *
- * This module was generated magically with RDB from a source description
- * file. You must edit the source file for changes to be made to this file.
- *
- *
- * Date: Generated on Sat Apr 20 03:07:46 2013
- * MD5 Checksum d41d8cd98f00b204e9800998ecf8427e
- *
- * Compiled with: RDB Utility combo_header.pl
- * RDB Parser 3.0
- * unknown unknown
- * Perl Interpreter 5.008008
- * Operating System linux
- *
- * Revision History:
- *
- * $brcm_Log: $
- *
- ***************************************************************************/
-
-#ifndef BCHP_PCIE_0_RC_CFG_TYPE1_H__
-#define BCHP_PCIE_0_RC_CFG_TYPE1_H__
-
-/***************************************************************************
- *PCIE_0_RC_CFG_TYPE1
- ***************************************************************************/
-#define BCHP_PCIE_0_RC_CFG_TYPE1_DEVICE_VENDOR_ID 0x00470000 /* device_vendor_id */
-#define BCHP_PCIE_0_RC_CFG_TYPE1_STATUS_COMMAND 0x00470004 /* status_command */
-#define BCHP_PCIE_0_RC_CFG_TYPE1_REV_ID_CLASS_CODE 0x00470008 /* rev_id_class_code */
-#define BCHP_PCIE_0_RC_CFG_TYPE1_HEADERTYPE_LAT_CACHELINESIZE 0x0047000c /* headertype_lat_cachelinesize */
-#define BCHP_PCIE_0_RC_CFG_TYPE1_BAR_1 0x00470010 /* bar_1 */
-#define BCHP_PCIE_0_RC_CFG_TYPE1_BAR_2 0x00470014 /* bar_2 */
-#define BCHP_PCIE_0_RC_CFG_TYPE1_PRI_SEC_BUS_NO 0x00470018 /* pri_sec_bus_no */
-#define BCHP_PCIE_0_RC_CFG_TYPE1_SEC_STATUS_IO_BASE_LIMIT 0x0047001c /* sec_status_io_base_limit */
-#define BCHP_PCIE_0_RC_CFG_TYPE1_RC_MEM_BASE_LIMIT 0x00470020 /* rc_mem_base_limit */
-#define BCHP_PCIE_0_RC_CFG_TYPE1_RC_PREF_BASE_LIMIT 0x00470024 /* rc_pref_base_limit */
-#define BCHP_PCIE_0_RC_CFG_TYPE1_RC_PREF_BASE_HI 0x00470028 /* rc_pref_base_hi */
-#define BCHP_PCIE_0_RC_CFG_TYPE1_RC_PREF_LIM_HI 0x0047002c /* rc_pref_lim_hi */
-#define BCHP_PCIE_0_RC_CFG_TYPE1_RC_IO_BASE_LIMIT 0x00470030 /* rc_io_base_limit */
-#define BCHP_PCIE_0_RC_CFG_TYPE1_CAP_POINTER 0x00470034 /* cap_pointer */
-#define BCHP_PCIE_0_RC_CFG_TYPE1_EXP_ROM_BAR 0x00470038 /* exp_rom_bar */
-#define BCHP_PCIE_0_RC_CFG_TYPE1_BRIDGE_CONTROL 0x0047003c /* bridge_control */
-
-/***************************************************************************
- *DEVICE_VENDOR_ID - device_vendor_id
- ***************************************************************************/
-/* PCIE_0_RC_CFG_TYPE1 :: DEVICE_VENDOR_ID :: DEVICE_ID [31:16] */
-#define BCHP_PCIE_0_RC_CFG_TYPE1_DEVICE_VENDOR_ID_DEVICE_ID_MASK 0xffff0000
-#define BCHP_PCIE_0_RC_CFG_TYPE1_DEVICE_VENDOR_ID_DEVICE_ID_SHIFT 16
-
-/* PCIE_0_RC_CFG_TYPE1 :: DEVICE_VENDOR_ID :: VENDOR_ID [15:00] */
-#define BCHP_PCIE_0_RC_CFG_TYPE1_DEVICE_VENDOR_ID_VENDOR_ID_MASK 0x0000ffff
-#define BCHP_PCIE_0_RC_CFG_TYPE1_DEVICE_VENDOR_ID_VENDOR_ID_SHIFT 0
-#define BCHP_PCIE_0_RC_CFG_TYPE1_DEVICE_VENDOR_ID_VENDOR_ID_DEFAULT 0x000014e4
-
-/***************************************************************************
- *STATUS_COMMAND - status_command
- ***************************************************************************/
-/* PCIE_0_RC_CFG_TYPE1 :: STATUS_COMMAND :: PAR_ERR [31:31] */
-#define BCHP_PCIE_0_RC_CFG_TYPE1_STATUS_COMMAND_PAR_ERR_MASK 0x80000000
-#define BCHP_PCIE_0_RC_CFG_TYPE1_STATUS_COMMAND_PAR_ERR_SHIFT 31
-#define BCHP_PCIE_0_RC_CFG_TYPE1_STATUS_COMMAND_PAR_ERR_DEFAULT 0x00000000
-
-/* PCIE_0_RC_CFG_TYPE1 :: STATUS_COMMAND :: SIG_SERR [30:30] */
-#define BCHP_PCIE_0_RC_CFG_TYPE1_STATUS_COMMAND_SIG_SERR_MASK 0x40000000
-#define BCHP_PCIE_0_RC_CFG_TYPE1_STATUS_COMMAND_SIG_SERR_SHIFT 30
-#define BCHP_PCIE_0_RC_CFG_TYPE1_STATUS_COMMAND_SIG_SERR_DEFAULT 0x00000000
-
-/* PCIE_0_RC_CFG_TYPE1 :: STATUS_COMMAND :: RCV_MSTR_ABT [29:29] */
-#define BCHP_PCIE_0_RC_CFG_TYPE1_STATUS_COMMAND_RCV_MSTR_ABT_MASK 0x20000000
-#define BCHP_PCIE_0_RC_CFG_TYPE1_STATUS_COMMAND_RCV_MSTR_ABT_SHIFT 29
-#define BCHP_PCIE_0_RC_CFG_TYPE1_STATUS_COMMAND_RCV_MSTR_ABT_DEFAULT 0x00000000
-
-/* PCIE_0_RC_CFG_TYPE1 :: STATUS_COMMAND :: RCV_TGT_ABT [28:28] */
-#define BCHP_PCIE_0_RC_CFG_TYPE1_STATUS_COMMAND_RCV_TGT_ABT_MASK 0x10000000
-#define BCHP_PCIE_0_RC_CFG_TYPE1_STATUS_COMMAND_RCV_TGT_ABT_SHIFT 28
-#define BCHP_PCIE_0_RC_CFG_TYPE1_STATUS_COMMAND_RCV_TGT_ABT_DEFAULT 0x00000000
-
-/* PCIE_0_RC_CFG_TYPE1 :: STATUS_COMMAND :: SIG_TGT_ABT [27:27] */
-#define BCHP_PCIE_0_RC_CFG_TYPE1_STATUS_COMMAND_SIG_TGT_ABT_MASK 0x08000000
-#define BCHP_PCIE_0_RC_CFG_TYPE1_STATUS_COMMAND_SIG_TGT_ABT_SHIFT 27
-#define BCHP_PCIE_0_RC_CFG_TYPE1_STATUS_COMMAND_SIG_TGT_ABT_DEFAULT 0x00000000
-
-/* PCIE_0_RC_CFG_TYPE1 :: STATUS_COMMAND :: DEVSEL_TIMING [26:25] */
-#define BCHP_PCIE_0_RC_CFG_TYPE1_STATUS_COMMAND_DEVSEL_TIMING_MASK 0x06000000
-#define BCHP_PCIE_0_RC_CFG_TYPE1_STATUS_COMMAND_DEVSEL_TIMING_SHIFT 25
-#define BCHP_PCIE_0_RC_CFG_TYPE1_STATUS_COMMAND_DEVSEL_TIMING_DEFAULT 0x00000000
-
-/* PCIE_0_RC_CFG_TYPE1 :: STATUS_COMMAND :: MSTR_PERR [24:24] */
-#define BCHP_PCIE_0_RC_CFG_TYPE1_STATUS_COMMAND_MSTR_PERR_MASK 0x01000000
-#define BCHP_PCIE_0_RC_CFG_TYPE1_STATUS_COMMAND_MSTR_PERR_SHIFT 24
-#define BCHP_PCIE_0_RC_CFG_TYPE1_STATUS_COMMAND_MSTR_PERR_DEFAULT 0x00000000
-
-/* PCIE_0_RC_CFG_TYPE1 :: STATUS_COMMAND :: FAST_B2B_CAP [23:23] */
-#define BCHP_PCIE_0_RC_CFG_TYPE1_STATUS_COMMAND_FAST_B2B_CAP_MASK 0x00800000
-#define BCHP_PCIE_0_RC_CFG_TYPE1_STATUS_COMMAND_FAST_B2B_CAP_SHIFT 23
-#define BCHP_PCIE_0_RC_CFG_TYPE1_STATUS_COMMAND_FAST_B2B_CAP_DEFAULT 0x00000000
-
-/* PCIE_0_RC_CFG_TYPE1 :: STATUS_COMMAND :: RESERVED1 [22:22] */
-#define BCHP_PCIE_0_RC_CFG_TYPE1_STATUS_COMMAND_RESERVED1_MASK 0x00400000
-#define BCHP_PCIE_0_RC_CFG_TYPE1_STATUS_COMMAND_RESERVED1_SHIFT 22
-#define BCHP_PCIE_0_RC_CFG_TYPE1_STATUS_COMMAND_RESERVED1_DEFAULT 0x00000000
-
-/* PCIE_0_RC_CFG_TYPE1 :: STATUS_COMMAND :: CAP_66MHZ [21:21] */
-#define BCHP_PCIE_0_RC_CFG_TYPE1_STATUS_COMMAND_CAP_66MHZ_MASK 0x00200000
-#define BCHP_PCIE_0_RC_CFG_TYPE1_STATUS_COMMAND_CAP_66MHZ_SHIFT 21
-#define BCHP_PCIE_0_RC_CFG_TYPE1_STATUS_COMMAND_CAP_66MHZ_DEFAULT 0x00000000
-
-/* PCIE_0_RC_CFG_TYPE1 :: STATUS_COMMAND :: CAP_LIST [20:20] */
-#define BCHP_PCIE_0_RC_CFG_TYPE1_STATUS_COMMAND_CAP_LIST_MASK 0x00100000
-#define BCHP_PCIE_0_RC_CFG_TYPE1_STATUS_COMMAND_CAP_LIST_SHIFT 20
-#define BCHP_PCIE_0_RC_CFG_TYPE1_STATUS_COMMAND_CAP_LIST_DEFAULT 0x00000001
-
-/* PCIE_0_RC_CFG_TYPE1 :: STATUS_COMMAND :: INT_STATUS [19:19] */
-#define BCHP_PCIE_0_RC_CFG_TYPE1_STATUS_COMMAND_INT_STATUS_MASK 0x00080000
-#define BCHP_PCIE_0_RC_CFG_TYPE1_STATUS_COMMAND_INT_STATUS_SHIFT 19
-#define BCHP_PCIE_0_RC_CFG_TYPE1_STATUS_COMMAND_INT_STATUS_DEFAULT 0x00000000
-
-/* PCIE_0_RC_CFG_TYPE1 :: STATUS_COMMAND :: RESERVED2 [18:16] */
-#define BCHP_PCIE_0_RC_CFG_TYPE1_STATUS_COMMAND_RESERVED2_MASK 0x00070000
-#define BCHP_PCIE_0_RC_CFG_TYPE1_STATUS_COMMAND_RESERVED2_SHIFT 16
-#define BCHP_PCIE_0_RC_CFG_TYPE1_STATUS_COMMAND_RESERVED2_DEFAULT 0x00000000
-
-/* PCIE_0_RC_CFG_TYPE1 :: STATUS_COMMAND :: RESERVED [15:11] */
-#define BCHP_PCIE_0_RC_CFG_TYPE1_STATUS_COMMAND_RESERVED_MASK 0x0000f800
-#define BCHP_PCIE_0_RC_CFG_TYPE1_STATUS_COMMAND_RESERVED_SHIFT 11
-#define BCHP_PCIE_0_RC_CFG_TYPE1_STATUS_COMMAND_RESERVED_DEFAULT 0x00000000
-
-/* PCIE_0_RC_CFG_TYPE1 :: STATUS_COMMAND :: INT_DISABLE [10:10] */
-#define BCHP_PCIE_0_RC_CFG_TYPE1_STATUS_COMMAND_INT_DISABLE_MASK 0x00000400
-#define BCHP_PCIE_0_RC_CFG_TYPE1_STATUS_COMMAND_INT_DISABLE_SHIFT 10
-#define BCHP_PCIE_0_RC_CFG_TYPE1_STATUS_COMMAND_INT_DISABLE_DEFAULT 0x00000000
-
-/* PCIE_0_RC_CFG_TYPE1 :: STATUS_COMMAND :: FAST_B2B [09:09] */
-#define BCHP_PCIE_0_RC_CFG_TYPE1_STATUS_COMMAND_FAST_B2B_MASK 0x00000200
-#define BCHP_PCIE_0_RC_CFG_TYPE1_STATUS_COMMAND_FAST_B2B_SHIFT 9
-#define BCHP_PCIE_0_RC_CFG_TYPE1_STATUS_COMMAND_FAST_B2B_DEFAULT 0x00000000
-
-/* PCIE_0_RC_CFG_TYPE1 :: STATUS_COMMAND :: SERR_ENA [08:08] */
-#define BCHP_PCIE_0_RC_CFG_TYPE1_STATUS_COMMAND_SERR_ENA_MASK 0x00000100
-#define BCHP_PCIE_0_RC_CFG_TYPE1_STATUS_COMMAND_SERR_ENA_SHIFT 8
-#define BCHP_PCIE_0_RC_CFG_TYPE1_STATUS_COMMAND_SERR_ENA_DEFAULT 0x00000000
-
-/* PCIE_0_RC_CFG_TYPE1 :: STATUS_COMMAND :: STEPPING [07:07] */
-#define BCHP_PCIE_0_RC_CFG_TYPE1_STATUS_COMMAND_STEPPING_MASK 0x00000080
-#define BCHP_PCIE_0_RC_CFG_TYPE1_STATUS_COMMAND_STEPPING_SHIFT 7
-#define BCHP_PCIE_0_RC_CFG_TYPE1_STATUS_COMMAND_STEPPING_DEFAULT 0x00000000
-
-/* PCIE_0_RC_CFG_TYPE1 :: STATUS_COMMAND :: PERR_ENA [06:06] */
-#define BCHP_PCIE_0_RC_CFG_TYPE1_STATUS_COMMAND_PERR_ENA_MASK 0x00000040
-#define BCHP_PCIE_0_RC_CFG_TYPE1_STATUS_COMMAND_PERR_ENA_SHIFT 6
-#define BCHP_PCIE_0_RC_CFG_TYPE1_STATUS_COMMAND_PERR_ENA_DEFAULT 0x00000000
-
-/* PCIE_0_RC_CFG_TYPE1 :: STATUS_COMMAND :: VGA_SNOOP [05:05] */
-#define BCHP_PCIE_0_RC_CFG_TYPE1_STATUS_COMMAND_VGA_SNOOP_MASK 0x00000020
-#define BCHP_PCIE_0_RC_CFG_TYPE1_STATUS_COMMAND_VGA_SNOOP_SHIFT 5
-#define BCHP_PCIE_0_RC_CFG_TYPE1_STATUS_COMMAND_VGA_SNOOP_DEFAULT 0x00000000
-
-/* PCIE_0_RC_CFG_TYPE1 :: STATUS_COMMAND :: MWI_CYCLES [04:04] */
-#define BCHP_PCIE_0_RC_CFG_TYPE1_STATUS_COMMAND_MWI_CYCLES_MASK 0x00000010
-#define BCHP_PCIE_0_RC_CFG_TYPE1_STATUS_COMMAND_MWI_CYCLES_SHIFT 4
-#define BCHP_PCIE_0_RC_CFG_TYPE1_STATUS_COMMAND_MWI_CYCLES_DEFAULT 0x00000000
-
-/* PCIE_0_RC_CFG_TYPE1 :: STATUS_COMMAND :: SPECIAL_CYCLES [03:03] */
-#define BCHP_PCIE_0_RC_CFG_TYPE1_STATUS_COMMAND_SPECIAL_CYCLES_MASK 0x00000008
-#define BCHP_PCIE_0_RC_CFG_TYPE1_STATUS_COMMAND_SPECIAL_CYCLES_SHIFT 3
-#define BCHP_PCIE_0_RC_CFG_TYPE1_STATUS_COMMAND_SPECIAL_CYCLES_DEFAULT 0x00000000
-
-/* PCIE_0_RC_CFG_TYPE1 :: STATUS_COMMAND :: BUS_MASTER [02:02] */
-#define BCHP_PCIE_0_RC_CFG_TYPE1_STATUS_COMMAND_BUS_MASTER_MASK 0x00000004
-#define BCHP_PCIE_0_RC_CFG_TYPE1_STATUS_COMMAND_BUS_MASTER_SHIFT 2
-#define BCHP_PCIE_0_RC_CFG_TYPE1_STATUS_COMMAND_BUS_MASTER_DEFAULT 0x00000000
-
-/* PCIE_0_RC_CFG_TYPE1 :: STATUS_COMMAND :: MEM_SPACE [01:01] */
-#define BCHP_PCIE_0_RC_CFG_TYPE1_STATUS_COMMAND_MEM_SPACE_MASK 0x00000002
-#define BCHP_PCIE_0_RC_CFG_TYPE1_STATUS_COMMAND_MEM_SPACE_SHIFT 1
-#define BCHP_PCIE_0_RC_CFG_TYPE1_STATUS_COMMAND_MEM_SPACE_DEFAULT 0x00000000
-
-/* PCIE_0_RC_CFG_TYPE1 :: STATUS_COMMAND :: IO_SPACE [00:00] */
-#define BCHP_PCIE_0_RC_CFG_TYPE1_STATUS_COMMAND_IO_SPACE_MASK 0x00000001
-#define BCHP_PCIE_0_RC_CFG_TYPE1_STATUS_COMMAND_IO_SPACE_SHIFT 0
-#define BCHP_PCIE_0_RC_CFG_TYPE1_STATUS_COMMAND_IO_SPACE_DEFAULT 0x00000000
-
-/***************************************************************************
- *REV_ID_CLASS_CODE - rev_id_class_code
- ***************************************************************************/
-/* PCIE_0_RC_CFG_TYPE1 :: REV_ID_CLASS_CODE :: CLASS_CODE [31:08] */
-#define BCHP_PCIE_0_RC_CFG_TYPE1_REV_ID_CLASS_CODE_CLASS_CODE_MASK 0xffffff00
-#define BCHP_PCIE_0_RC_CFG_TYPE1_REV_ID_CLASS_CODE_CLASS_CODE_SHIFT 8
-#define BCHP_PCIE_0_RC_CFG_TYPE1_REV_ID_CLASS_CODE_CLASS_CODE_DEFAULT 0x00020000
-
-/* PCIE_0_RC_CFG_TYPE1 :: REV_ID_CLASS_CODE :: REV_ID [07:00] */
-#define BCHP_PCIE_0_RC_CFG_TYPE1_REV_ID_CLASS_CODE_REV_ID_MASK 0x000000ff
-#define BCHP_PCIE_0_RC_CFG_TYPE1_REV_ID_CLASS_CODE_REV_ID_SHIFT 0
-
-/***************************************************************************
- *HEADERTYPE_LAT_CACHELINESIZE - headertype_lat_cachelinesize
- ***************************************************************************/
-/* PCIE_0_RC_CFG_TYPE1 :: HEADERTYPE_LAT_CACHELINESIZE :: BIST [31:24] */
-#define BCHP_PCIE_0_RC_CFG_TYPE1_HEADERTYPE_LAT_CACHELINESIZE_BIST_MASK 0xff000000
-#define BCHP_PCIE_0_RC_CFG_TYPE1_HEADERTYPE_LAT_CACHELINESIZE_BIST_SHIFT 24
-#define BCHP_PCIE_0_RC_CFG_TYPE1_HEADERTYPE_LAT_CACHELINESIZE_BIST_DEFAULT 0x00000000
-
-/* PCIE_0_RC_CFG_TYPE1 :: HEADERTYPE_LAT_CACHELINESIZE :: HEADER_TYPE [23:16] */
-#define BCHP_PCIE_0_RC_CFG_TYPE1_HEADERTYPE_LAT_CACHELINESIZE_HEADER_TYPE_MASK 0x00ff0000
-#define BCHP_PCIE_0_RC_CFG_TYPE1_HEADERTYPE_LAT_CACHELINESIZE_HEADER_TYPE_SHIFT 16
-#define BCHP_PCIE_0_RC_CFG_TYPE1_HEADERTYPE_LAT_CACHELINESIZE_HEADER_TYPE_DEFAULT 0x00000001
-
-/* PCIE_0_RC_CFG_TYPE1 :: HEADERTYPE_LAT_CACHELINESIZE :: LATENCY_TIMER [15:08] */
-#define BCHP_PCIE_0_RC_CFG_TYPE1_HEADERTYPE_LAT_CACHELINESIZE_LATENCY_TIMER_MASK 0x0000ff00
-#define BCHP_PCIE_0_RC_CFG_TYPE1_HEADERTYPE_LAT_CACHELINESIZE_LATENCY_TIMER_SHIFT 8
-#define BCHP_PCIE_0_RC_CFG_TYPE1_HEADERTYPE_LAT_CACHELINESIZE_LATENCY_TIMER_DEFAULT 0x00000000
-
-/* PCIE_0_RC_CFG_TYPE1 :: HEADERTYPE_LAT_CACHELINESIZE :: CACHE_LINE_SIZE [07:00] */
-#define BCHP_PCIE_0_RC_CFG_TYPE1_HEADERTYPE_LAT_CACHELINESIZE_CACHE_LINE_SIZE_MASK 0x000000ff
-#define BCHP_PCIE_0_RC_CFG_TYPE1_HEADERTYPE_LAT_CACHELINESIZE_CACHE_LINE_SIZE_SHIFT 0
-#define BCHP_PCIE_0_RC_CFG_TYPE1_HEADERTYPE_LAT_CACHELINESIZE_CACHE_LINE_SIZE_DEFAULT 0x00000000
-
-/***************************************************************************
- *BAR_1 - bar_1
- ***************************************************************************/
-/* PCIE_0_RC_CFG_TYPE1 :: BAR_1 :: ADDRESS [31:04] */
-#define BCHP_PCIE_0_RC_CFG_TYPE1_BAR_1_ADDRESS_MASK 0xfffffff0
-#define BCHP_PCIE_0_RC_CFG_TYPE1_BAR_1_ADDRESS_SHIFT 4
-#define BCHP_PCIE_0_RC_CFG_TYPE1_BAR_1_ADDRESS_DEFAULT 0x00000000
-
-/* PCIE_0_RC_CFG_TYPE1 :: BAR_1 :: PREFETCH [03:03] */
-#define BCHP_PCIE_0_RC_CFG_TYPE1_BAR_1_PREFETCH_MASK 0x00000008
-#define BCHP_PCIE_0_RC_CFG_TYPE1_BAR_1_PREFETCH_SHIFT 3
-#define BCHP_PCIE_0_RC_CFG_TYPE1_BAR_1_PREFETCH_DEFAULT 0x00000001
-
-/* PCIE_0_RC_CFG_TYPE1 :: BAR_1 :: SPACE_TYPE [02:01] */
-#define BCHP_PCIE_0_RC_CFG_TYPE1_BAR_1_SPACE_TYPE_MASK 0x00000006
-#define BCHP_PCIE_0_RC_CFG_TYPE1_BAR_1_SPACE_TYPE_SHIFT 1
-#define BCHP_PCIE_0_RC_CFG_TYPE1_BAR_1_SPACE_TYPE_DEFAULT 0x00000002
-
-/* PCIE_0_RC_CFG_TYPE1 :: BAR_1 :: MEM_SPACE [00:00] */
-#define BCHP_PCIE_0_RC_CFG_TYPE1_BAR_1_MEM_SPACE_MASK 0x00000001
-#define BCHP_PCIE_0_RC_CFG_TYPE1_BAR_1_MEM_SPACE_SHIFT 0
-#define BCHP_PCIE_0_RC_CFG_TYPE1_BAR_1_MEM_SPACE_DEFAULT 0x00000000
-
-/***************************************************************************
- *BAR_2 - bar_2
- ***************************************************************************/
-/* PCIE_0_RC_CFG_TYPE1 :: BAR_2 :: ADDR [31:00] */
-#define BCHP_PCIE_0_RC_CFG_TYPE1_BAR_2_ADDR_MASK 0xffffffff
-#define BCHP_PCIE_0_RC_CFG_TYPE1_BAR_2_ADDR_SHIFT 0
-#define BCHP_PCIE_0_RC_CFG_TYPE1_BAR_2_ADDR_DEFAULT 0x00000000
-
-/***************************************************************************
- *PRI_SEC_BUS_NO - pri_sec_bus_no
- ***************************************************************************/
-/* PCIE_0_RC_CFG_TYPE1 :: PRI_SEC_BUS_NO :: SEC_LATENCY_TIMER [31:24] */
-#define BCHP_PCIE_0_RC_CFG_TYPE1_PRI_SEC_BUS_NO_SEC_LATENCY_TIMER_MASK 0xff000000
-#define BCHP_PCIE_0_RC_CFG_TYPE1_PRI_SEC_BUS_NO_SEC_LATENCY_TIMER_SHIFT 24
-#define BCHP_PCIE_0_RC_CFG_TYPE1_PRI_SEC_BUS_NO_SEC_LATENCY_TIMER_DEFAULT 0x00000000
-
-/* PCIE_0_RC_CFG_TYPE1 :: PRI_SEC_BUS_NO :: SUB_BUS_NO [23:16] */
-#define BCHP_PCIE_0_RC_CFG_TYPE1_PRI_SEC_BUS_NO_SUB_BUS_NO_MASK 0x00ff0000
-#define BCHP_PCIE_0_RC_CFG_TYPE1_PRI_SEC_BUS_NO_SUB_BUS_NO_SHIFT 16
-#define BCHP_PCIE_0_RC_CFG_TYPE1_PRI_SEC_BUS_NO_SUB_BUS_NO_DEFAULT 0x00000000
-
-/* PCIE_0_RC_CFG_TYPE1 :: PRI_SEC_BUS_NO :: SEC_BUS_NO [15:08] */
-#define BCHP_PCIE_0_RC_CFG_TYPE1_PRI_SEC_BUS_NO_SEC_BUS_NO_MASK 0x0000ff00
-#define BCHP_PCIE_0_RC_CFG_TYPE1_PRI_SEC_BUS_NO_SEC_BUS_NO_SHIFT 8
-#define BCHP_PCIE_0_RC_CFG_TYPE1_PRI_SEC_BUS_NO_SEC_BUS_NO_DEFAULT 0x00000000
-
-/* PCIE_0_RC_CFG_TYPE1 :: PRI_SEC_BUS_NO :: PRI_BUS_NO [07:00] */
-#define BCHP_PCIE_0_RC_CFG_TYPE1_PRI_SEC_BUS_NO_PRI_BUS_NO_MASK 0x000000ff
-#define BCHP_PCIE_0_RC_CFG_TYPE1_PRI_SEC_BUS_NO_PRI_BUS_NO_SHIFT 0
-#define BCHP_PCIE_0_RC_CFG_TYPE1_PRI_SEC_BUS_NO_PRI_BUS_NO_DEFAULT 0x00000000
-
-/***************************************************************************
- *SEC_STATUS_IO_BASE_LIMIT - sec_status_io_base_limit
- ***************************************************************************/
-/* PCIE_0_RC_CFG_TYPE1 :: SEC_STATUS_IO_BASE_LIMIT :: SEC_DETECTED_PARITY_ERROR [31:31] */
-#define BCHP_PCIE_0_RC_CFG_TYPE1_SEC_STATUS_IO_BASE_LIMIT_SEC_DETECTED_PARITY_ERROR_MASK 0x80000000
-#define BCHP_PCIE_0_RC_CFG_TYPE1_SEC_STATUS_IO_BASE_LIMIT_SEC_DETECTED_PARITY_ERROR_SHIFT 31
-#define BCHP_PCIE_0_RC_CFG_TYPE1_SEC_STATUS_IO_BASE_LIMIT_SEC_DETECTED_PARITY_ERROR_DEFAULT 0x00000000
-
-/* PCIE_0_RC_CFG_TYPE1 :: SEC_STATUS_IO_BASE_LIMIT :: SEC_RECEIVED_SYSTEM_ERROR [30:30] */
-#define BCHP_PCIE_0_RC_CFG_TYPE1_SEC_STATUS_IO_BASE_LIMIT_SEC_RECEIVED_SYSTEM_ERROR_MASK 0x40000000
-#define BCHP_PCIE_0_RC_CFG_TYPE1_SEC_STATUS_IO_BASE_LIMIT_SEC_RECEIVED_SYSTEM_ERROR_SHIFT 30
-#define BCHP_PCIE_0_RC_CFG_TYPE1_SEC_STATUS_IO_BASE_LIMIT_SEC_RECEIVED_SYSTEM_ERROR_DEFAULT 0x00000000
-
-/* PCIE_0_RC_CFG_TYPE1 :: SEC_STATUS_IO_BASE_LIMIT :: SEC_RECEIVED_MASTER_ABORT [29:29] */
-#define BCHP_PCIE_0_RC_CFG_TYPE1_SEC_STATUS_IO_BASE_LIMIT_SEC_RECEIVED_MASTER_ABORT_MASK 0x20000000
-#define BCHP_PCIE_0_RC_CFG_TYPE1_SEC_STATUS_IO_BASE_LIMIT_SEC_RECEIVED_MASTER_ABORT_SHIFT 29
-#define BCHP_PCIE_0_RC_CFG_TYPE1_SEC_STATUS_IO_BASE_LIMIT_SEC_RECEIVED_MASTER_ABORT_DEFAULT 0x00000000
-
-/* PCIE_0_RC_CFG_TYPE1 :: SEC_STATUS_IO_BASE_LIMIT :: SEC_RECEIVED_TARGET_ABORT [28:28] */
-#define BCHP_PCIE_0_RC_CFG_TYPE1_SEC_STATUS_IO_BASE_LIMIT_SEC_RECEIVED_TARGET_ABORT_MASK 0x10000000
-#define BCHP_PCIE_0_RC_CFG_TYPE1_SEC_STATUS_IO_BASE_LIMIT_SEC_RECEIVED_TARGET_ABORT_SHIFT 28
-#define BCHP_PCIE_0_RC_CFG_TYPE1_SEC_STATUS_IO_BASE_LIMIT_SEC_RECEIVED_TARGET_ABORT_DEFAULT 0x00000000
-
-/* PCIE_0_RC_CFG_TYPE1 :: SEC_STATUS_IO_BASE_LIMIT :: SEC_SIGNALED_TARGET_ABORT [27:27] */
-#define BCHP_PCIE_0_RC_CFG_TYPE1_SEC_STATUS_IO_BASE_LIMIT_SEC_SIGNALED_TARGET_ABORT_MASK 0x08000000
-#define BCHP_PCIE_0_RC_CFG_TYPE1_SEC_STATUS_IO_BASE_LIMIT_SEC_SIGNALED_TARGET_ABORT_SHIFT 27
-#define BCHP_PCIE_0_RC_CFG_TYPE1_SEC_STATUS_IO_BASE_LIMIT_SEC_SIGNALED_TARGET_ABORT_DEFAULT 0x00000000
-
-/* PCIE_0_RC_CFG_TYPE1 :: SEC_STATUS_IO_BASE_LIMIT :: DEVICE_TIMING [26:25] */
-#define BCHP_PCIE_0_RC_CFG_TYPE1_SEC_STATUS_IO_BASE_LIMIT_DEVICE_TIMING_MASK 0x06000000
-#define BCHP_PCIE_0_RC_CFG_TYPE1_SEC_STATUS_IO_BASE_LIMIT_DEVICE_TIMING_SHIFT 25
-#define BCHP_PCIE_0_RC_CFG_TYPE1_SEC_STATUS_IO_BASE_LIMIT_DEVICE_TIMING_DEFAULT 0x00000000
-
-/* PCIE_0_RC_CFG_TYPE1 :: SEC_STATUS_IO_BASE_LIMIT :: SEC_MASTER_DATA_PARITY_ERROR [24:24] */
-#define BCHP_PCIE_0_RC_CFG_TYPE1_SEC_STATUS_IO_BASE_LIMIT_SEC_MASTER_DATA_PARITY_ERROR_MASK 0x01000000
-#define BCHP_PCIE_0_RC_CFG_TYPE1_SEC_STATUS_IO_BASE_LIMIT_SEC_MASTER_DATA_PARITY_ERROR_SHIFT 24
-#define BCHP_PCIE_0_RC_CFG_TYPE1_SEC_STATUS_IO_BASE_LIMIT_SEC_MASTER_DATA_PARITY_ERROR_DEFAULT 0x00000000
-
-/* PCIE_0_RC_CFG_TYPE1 :: SEC_STATUS_IO_BASE_LIMIT :: FAST_B2B [23:23] */
-#define BCHP_PCIE_0_RC_CFG_TYPE1_SEC_STATUS_IO_BASE_LIMIT_FAST_B2B_MASK 0x00800000
-#define BCHP_PCIE_0_RC_CFG_TYPE1_SEC_STATUS_IO_BASE_LIMIT_FAST_B2B_SHIFT 23
-#define BCHP_PCIE_0_RC_CFG_TYPE1_SEC_STATUS_IO_BASE_LIMIT_FAST_B2B_DEFAULT 0x00000000
-
-/* PCIE_0_RC_CFG_TYPE1 :: SEC_STATUS_IO_BASE_LIMIT :: RESERVED3 [22:22] */
-#define BCHP_PCIE_0_RC_CFG_TYPE1_SEC_STATUS_IO_BASE_LIMIT_RESERVED3_MASK 0x00400000
-#define BCHP_PCIE_0_RC_CFG_TYPE1_SEC_STATUS_IO_BASE_LIMIT_RESERVED3_SHIFT 22
-#define BCHP_PCIE_0_RC_CFG_TYPE1_SEC_STATUS_IO_BASE_LIMIT_RESERVED3_DEFAULT 0x00000000
-
-/* PCIE_0_RC_CFG_TYPE1 :: SEC_STATUS_IO_BASE_LIMIT :: CAP_66_MHZ [21:21] */
-#define BCHP_PCIE_0_RC_CFG_TYPE1_SEC_STATUS_IO_BASE_LIMIT_CAP_66_MHZ_MASK 0x00200000
-#define BCHP_PCIE_0_RC_CFG_TYPE1_SEC_STATUS_IO_BASE_LIMIT_CAP_66_MHZ_SHIFT 21
-#define BCHP_PCIE_0_RC_CFG_TYPE1_SEC_STATUS_IO_BASE_LIMIT_CAP_66_MHZ_DEFAULT 0x00000000
-
-/* PCIE_0_RC_CFG_TYPE1 :: SEC_STATUS_IO_BASE_LIMIT :: RESERVED4 [20:16] */
-#define BCHP_PCIE_0_RC_CFG_TYPE1_SEC_STATUS_IO_BASE_LIMIT_RESERVED4_MASK 0x001f0000
-#define BCHP_PCIE_0_RC_CFG_TYPE1_SEC_STATUS_IO_BASE_LIMIT_RESERVED4_SHIFT 16
-#define BCHP_PCIE_0_RC_CFG_TYPE1_SEC_STATUS_IO_BASE_LIMIT_RESERVED4_DEFAULT 0x00000000
-
-/* PCIE_0_RC_CFG_TYPE1 :: SEC_STATUS_IO_BASE_LIMIT :: IO_LIMIT [15:08] */
-#define BCHP_PCIE_0_RC_CFG_TYPE1_SEC_STATUS_IO_BASE_LIMIT_IO_LIMIT_MASK 0x0000ff00
-#define BCHP_PCIE_0_RC_CFG_TYPE1_SEC_STATUS_IO_BASE_LIMIT_IO_LIMIT_SHIFT 8
-#define BCHP_PCIE_0_RC_CFG_TYPE1_SEC_STATUS_IO_BASE_LIMIT_IO_LIMIT_DEFAULT 0x00000000
-
-/* PCIE_0_RC_CFG_TYPE1 :: SEC_STATUS_IO_BASE_LIMIT :: IO_BASE [07:00] */
-#define BCHP_PCIE_0_RC_CFG_TYPE1_SEC_STATUS_IO_BASE_LIMIT_IO_BASE_MASK 0x000000ff
-#define BCHP_PCIE_0_RC_CFG_TYPE1_SEC_STATUS_IO_BASE_LIMIT_IO_BASE_SHIFT 0
-#define BCHP_PCIE_0_RC_CFG_TYPE1_SEC_STATUS_IO_BASE_LIMIT_IO_BASE_DEFAULT 0x00000000
-
-/***************************************************************************
- *RC_MEM_BASE_LIMIT - rc_mem_base_limit
- ***************************************************************************/
-/* PCIE_0_RC_CFG_TYPE1 :: RC_MEM_BASE_LIMIT :: RC_MEM_LIMIT [31:20] */
-#define BCHP_PCIE_0_RC_CFG_TYPE1_RC_MEM_BASE_LIMIT_RC_MEM_LIMIT_MASK 0xfff00000
-#define BCHP_PCIE_0_RC_CFG_TYPE1_RC_MEM_BASE_LIMIT_RC_MEM_LIMIT_SHIFT 20
-#define BCHP_PCIE_0_RC_CFG_TYPE1_RC_MEM_BASE_LIMIT_RC_MEM_LIMIT_DEFAULT 0x00000000
-
-/* PCIE_0_RC_CFG_TYPE1 :: RC_MEM_BASE_LIMIT :: RC_MEM_LIMIT_3TO0 [19:16] */
-#define BCHP_PCIE_0_RC_CFG_TYPE1_RC_MEM_BASE_LIMIT_RC_MEM_LIMIT_3TO0_MASK 0x000f0000
-#define BCHP_PCIE_0_RC_CFG_TYPE1_RC_MEM_BASE_LIMIT_RC_MEM_LIMIT_3TO0_SHIFT 16
-#define BCHP_PCIE_0_RC_CFG_TYPE1_RC_MEM_BASE_LIMIT_RC_MEM_LIMIT_3TO0_DEFAULT 0x00000000
-
-/* PCIE_0_RC_CFG_TYPE1 :: RC_MEM_BASE_LIMIT :: RC_MEM_BASE [15:04] */
-#define BCHP_PCIE_0_RC_CFG_TYPE1_RC_MEM_BASE_LIMIT_RC_MEM_BASE_MASK 0x0000fff0
-#define BCHP_PCIE_0_RC_CFG_TYPE1_RC_MEM_BASE_LIMIT_RC_MEM_BASE_SHIFT 4
-#define BCHP_PCIE_0_RC_CFG_TYPE1_RC_MEM_BASE_LIMIT_RC_MEM_BASE_DEFAULT 0x00000000
-
-/* PCIE_0_RC_CFG_TYPE1 :: RC_MEM_BASE_LIMIT :: RC_MEM_BASE_3TO0 [03:00] */
-#define BCHP_PCIE_0_RC_CFG_TYPE1_RC_MEM_BASE_LIMIT_RC_MEM_BASE_3TO0_MASK 0x0000000f
-#define BCHP_PCIE_0_RC_CFG_TYPE1_RC_MEM_BASE_LIMIT_RC_MEM_BASE_3TO0_SHIFT 0
-#define BCHP_PCIE_0_RC_CFG_TYPE1_RC_MEM_BASE_LIMIT_RC_MEM_BASE_3TO0_DEFAULT 0x00000000
-
-/***************************************************************************
- *RC_PREF_BASE_LIMIT - rc_pref_base_limit
- ***************************************************************************/
-/* PCIE_0_RC_CFG_TYPE1 :: RC_PREF_BASE_LIMIT :: RC_PREF_LIM [31:20] */
-#define BCHP_PCIE_0_RC_CFG_TYPE1_RC_PREF_BASE_LIMIT_RC_PREF_LIM_MASK 0xfff00000
-#define BCHP_PCIE_0_RC_CFG_TYPE1_RC_PREF_BASE_LIMIT_RC_PREF_LIM_SHIFT 20
-#define BCHP_PCIE_0_RC_CFG_TYPE1_RC_PREF_BASE_LIMIT_RC_PREF_LIM_DEFAULT 0x00000000
-
-/* PCIE_0_RC_CFG_TYPE1 :: RC_PREF_BASE_LIMIT :: RC_PREF_LIMIT_3TO0 [19:16] */
-#define BCHP_PCIE_0_RC_CFG_TYPE1_RC_PREF_BASE_LIMIT_RC_PREF_LIMIT_3TO0_MASK 0x000f0000
-#define BCHP_PCIE_0_RC_CFG_TYPE1_RC_PREF_BASE_LIMIT_RC_PREF_LIMIT_3TO0_SHIFT 16
-#define BCHP_PCIE_0_RC_CFG_TYPE1_RC_PREF_BASE_LIMIT_RC_PREF_LIMIT_3TO0_DEFAULT 0x00000001
-
-/* PCIE_0_RC_CFG_TYPE1 :: RC_PREF_BASE_LIMIT :: RC_PREF_BASE [15:04] */
-#define BCHP_PCIE_0_RC_CFG_TYPE1_RC_PREF_BASE_LIMIT_RC_PREF_BASE_MASK 0x0000fff0
-#define BCHP_PCIE_0_RC_CFG_TYPE1_RC_PREF_BASE_LIMIT_RC_PREF_BASE_SHIFT 4
-#define BCHP_PCIE_0_RC_CFG_TYPE1_RC_PREF_BASE_LIMIT_RC_PREF_BASE_DEFAULT 0x00000000
-
-/* PCIE_0_RC_CFG_TYPE1 :: RC_PREF_BASE_LIMIT :: RC_PREF_BASE_3TO0 [03:00] */
-#define BCHP_PCIE_0_RC_CFG_TYPE1_RC_PREF_BASE_LIMIT_RC_PREF_BASE_3TO0_MASK 0x0000000f
-#define BCHP_PCIE_0_RC_CFG_TYPE1_RC_PREF_BASE_LIMIT_RC_PREF_BASE_3TO0_SHIFT 0
-#define BCHP_PCIE_0_RC_CFG_TYPE1_RC_PREF_BASE_LIMIT_RC_PREF_BASE_3TO0_DEFAULT 0x00000001
-
-/***************************************************************************
- *RC_PREF_BASE_HI - rc_pref_base_hi
- ***************************************************************************/
-/* PCIE_0_RC_CFG_TYPE1 :: RC_PREF_BASE_HI :: RC_PREF_BASE_HI [31:00] */
-#define BCHP_PCIE_0_RC_CFG_TYPE1_RC_PREF_BASE_HI_RC_PREF_BASE_HI_MASK 0xffffffff
-#define BCHP_PCIE_0_RC_CFG_TYPE1_RC_PREF_BASE_HI_RC_PREF_BASE_HI_SHIFT 0
-#define BCHP_PCIE_0_RC_CFG_TYPE1_RC_PREF_BASE_HI_RC_PREF_BASE_HI_DEFAULT 0x00000000
-
-/***************************************************************************
- *RC_PREF_LIM_HI - rc_pref_lim_hi
- ***************************************************************************/
-/* PCIE_0_RC_CFG_TYPE1 :: RC_PREF_LIM_HI :: RC_PREF_BASE_HI [31:00] */
-#define BCHP_PCIE_0_RC_CFG_TYPE1_RC_PREF_LIM_HI_RC_PREF_BASE_HI_MASK 0xffffffff
-#define BCHP_PCIE_0_RC_CFG_TYPE1_RC_PREF_LIM_HI_RC_PREF_BASE_HI_SHIFT 0
-#define BCHP_PCIE_0_RC_CFG_TYPE1_RC_PREF_LIM_HI_RC_PREF_BASE_HI_DEFAULT 0x00000000
-
-/***************************************************************************
- *RC_IO_BASE_LIMIT - rc_io_base_limit
- ***************************************************************************/
-/* PCIE_0_RC_CFG_TYPE1 :: RC_IO_BASE_LIMIT :: RC_IO_LIM_HI [31:16] */
-#define BCHP_PCIE_0_RC_CFG_TYPE1_RC_IO_BASE_LIMIT_RC_IO_LIM_HI_MASK 0xffff0000
-#define BCHP_PCIE_0_RC_CFG_TYPE1_RC_IO_BASE_LIMIT_RC_IO_LIM_HI_SHIFT 16
-#define BCHP_PCIE_0_RC_CFG_TYPE1_RC_IO_BASE_LIMIT_RC_IO_LIM_HI_DEFAULT 0x00000000
-
-/* PCIE_0_RC_CFG_TYPE1 :: RC_IO_BASE_LIMIT :: RC_IO_BASE_HI [15:00] */
-#define BCHP_PCIE_0_RC_CFG_TYPE1_RC_IO_BASE_LIMIT_RC_IO_BASE_HI_MASK 0x0000ffff
-#define BCHP_PCIE_0_RC_CFG_TYPE1_RC_IO_BASE_LIMIT_RC_IO_BASE_HI_SHIFT 0
-#define BCHP_PCIE_0_RC_CFG_TYPE1_RC_IO_BASE_LIMIT_RC_IO_BASE_HI_DEFAULT 0x00000000
-
-/***************************************************************************
- *CAP_POINTER - cap_pointer
- ***************************************************************************/
-/* PCIE_0_RC_CFG_TYPE1 :: CAP_POINTER :: RESERVED0 [31:08] */
-#define BCHP_PCIE_0_RC_CFG_TYPE1_CAP_POINTER_RESERVED0_MASK 0xffffff00
-#define BCHP_PCIE_0_RC_CFG_TYPE1_CAP_POINTER_RESERVED0_SHIFT 8
-
-/* PCIE_0_RC_CFG_TYPE1 :: CAP_POINTER :: CAP_POINTER [07:00] */
-#define BCHP_PCIE_0_RC_CFG_TYPE1_CAP_POINTER_CAP_POINTER_MASK 0x000000ff
-#define BCHP_PCIE_0_RC_CFG_TYPE1_CAP_POINTER_CAP_POINTER_SHIFT 0
-#define BCHP_PCIE_0_RC_CFG_TYPE1_CAP_POINTER_CAP_POINTER_DEFAULT 0x00000048
-
-/***************************************************************************
- *EXP_ROM_BAR - exp_rom_bar
- ***************************************************************************/
-/* PCIE_0_RC_CFG_TYPE1 :: EXP_ROM_BAR :: RESERVED0 [31:08] */
-#define BCHP_PCIE_0_RC_CFG_TYPE1_EXP_ROM_BAR_RESERVED0_MASK 0xffffff00
-#define BCHP_PCIE_0_RC_CFG_TYPE1_EXP_ROM_BAR_RESERVED0_SHIFT 8
-
-/* PCIE_0_RC_CFG_TYPE1 :: EXP_ROM_BAR :: EXP_ROM_BAR [07:00] */
-#define BCHP_PCIE_0_RC_CFG_TYPE1_EXP_ROM_BAR_EXP_ROM_BAR_MASK 0x000000ff
-#define BCHP_PCIE_0_RC_CFG_TYPE1_EXP_ROM_BAR_EXP_ROM_BAR_SHIFT 0
-#define BCHP_PCIE_0_RC_CFG_TYPE1_EXP_ROM_BAR_EXP_ROM_BAR_DEFAULT 0x00000000
-
-/***************************************************************************
- *BRIDGE_CONTROL - bridge_control
- ***************************************************************************/
-/* PCIE_0_RC_CFG_TYPE1 :: BRIDGE_CONTROL :: RESERVED1 [31:28] */
-#define BCHP_PCIE_0_RC_CFG_TYPE1_BRIDGE_CONTROL_RESERVED1_MASK 0xf0000000
-#define BCHP_PCIE_0_RC_CFG_TYPE1_BRIDGE_CONTROL_RESERVED1_SHIFT 28
-
-/* PCIE_0_RC_CFG_TYPE1 :: BRIDGE_CONTROL :: DISCARD_TIMER_SERR_EN [27:27] */
-#define BCHP_PCIE_0_RC_CFG_TYPE1_BRIDGE_CONTROL_DISCARD_TIMER_SERR_EN_MASK 0x08000000
-#define BCHP_PCIE_0_RC_CFG_TYPE1_BRIDGE_CONTROL_DISCARD_TIMER_SERR_EN_SHIFT 27
-#define BCHP_PCIE_0_RC_CFG_TYPE1_BRIDGE_CONTROL_DISCARD_TIMER_SERR_EN_DEFAULT 0x00000000
-
-/* PCIE_0_RC_CFG_TYPE1 :: BRIDGE_CONTROL :: DISCARD_TIMER_STATUS [26:26] */
-#define BCHP_PCIE_0_RC_CFG_TYPE1_BRIDGE_CONTROL_DISCARD_TIMER_STATUS_MASK 0x04000000
-#define BCHP_PCIE_0_RC_CFG_TYPE1_BRIDGE_CONTROL_DISCARD_TIMER_STATUS_SHIFT 26
-#define BCHP_PCIE_0_RC_CFG_TYPE1_BRIDGE_CONTROL_DISCARD_TIMER_STATUS_DEFAULT 0x00000000
-
-/* PCIE_0_RC_CFG_TYPE1 :: BRIDGE_CONTROL :: SEC_DISCARD_TIMER [25:25] */
-#define BCHP_PCIE_0_RC_CFG_TYPE1_BRIDGE_CONTROL_SEC_DISCARD_TIMER_MASK 0x02000000
-#define BCHP_PCIE_0_RC_CFG_TYPE1_BRIDGE_CONTROL_SEC_DISCARD_TIMER_SHIFT 25
-#define BCHP_PCIE_0_RC_CFG_TYPE1_BRIDGE_CONTROL_SEC_DISCARD_TIMER_DEFAULT 0x00000000
-
-/* PCIE_0_RC_CFG_TYPE1 :: BRIDGE_CONTROL :: PRIM_DISCARD_TIMER [24:24] */
-#define BCHP_PCIE_0_RC_CFG_TYPE1_BRIDGE_CONTROL_PRIM_DISCARD_TIMER_MASK 0x01000000
-#define BCHP_PCIE_0_RC_CFG_TYPE1_BRIDGE_CONTROL_PRIM_DISCARD_TIMER_SHIFT 24
-#define BCHP_PCIE_0_RC_CFG_TYPE1_BRIDGE_CONTROL_PRIM_DISCARD_TIMER_DEFAULT 0x00000000
-
-/* PCIE_0_RC_CFG_TYPE1 :: BRIDGE_CONTROL :: FAST_B2B_EN [23:23] */
-#define BCHP_PCIE_0_RC_CFG_TYPE1_BRIDGE_CONTROL_FAST_B2B_EN_MASK 0x00800000
-#define BCHP_PCIE_0_RC_CFG_TYPE1_BRIDGE_CONTROL_FAST_B2B_EN_SHIFT 23
-#define BCHP_PCIE_0_RC_CFG_TYPE1_BRIDGE_CONTROL_FAST_B2B_EN_DEFAULT 0x00000000
-
-/* PCIE_0_RC_CFG_TYPE1 :: BRIDGE_CONTROL :: SEC_BUS_RESET [22:22] */
-#define BCHP_PCIE_0_RC_CFG_TYPE1_BRIDGE_CONTROL_SEC_BUS_RESET_MASK 0x00400000
-#define BCHP_PCIE_0_RC_CFG_TYPE1_BRIDGE_CONTROL_SEC_BUS_RESET_SHIFT 22
-#define BCHP_PCIE_0_RC_CFG_TYPE1_BRIDGE_CONTROL_SEC_BUS_RESET_DEFAULT 0x00000000
-
-/* PCIE_0_RC_CFG_TYPE1 :: BRIDGE_CONTROL :: MASTER_ABORT_MODE [21:21] */
-#define BCHP_PCIE_0_RC_CFG_TYPE1_BRIDGE_CONTROL_MASTER_ABORT_MODE_MASK 0x00200000
-#define BCHP_PCIE_0_RC_CFG_TYPE1_BRIDGE_CONTROL_MASTER_ABORT_MODE_SHIFT 21
-#define BCHP_PCIE_0_RC_CFG_TYPE1_BRIDGE_CONTROL_MASTER_ABORT_MODE_DEFAULT 0x00000000
-
-/* PCIE_0_RC_CFG_TYPE1 :: BRIDGE_CONTROL :: RESERVED0 [20:18] */
-#define BCHP_PCIE_0_RC_CFG_TYPE1_BRIDGE_CONTROL_RESERVED0_MASK 0x001c0000
-#define BCHP_PCIE_0_RC_CFG_TYPE1_BRIDGE_CONTROL_RESERVED0_SHIFT 18
-
-/* PCIE_0_RC_CFG_TYPE1 :: BRIDGE_CONTROL :: SEC_SERR_EN [17:17] */
-#define BCHP_PCIE_0_RC_CFG_TYPE1_BRIDGE_CONTROL_SEC_SERR_EN_MASK 0x00020000
-#define BCHP_PCIE_0_RC_CFG_TYPE1_BRIDGE_CONTROL_SEC_SERR_EN_SHIFT 17
-#define BCHP_PCIE_0_RC_CFG_TYPE1_BRIDGE_CONTROL_SEC_SERR_EN_DEFAULT 0x00000000
-
-/* PCIE_0_RC_CFG_TYPE1 :: BRIDGE_CONTROL :: SEC_PERR_RESP_EN [16:16] */
-#define BCHP_PCIE_0_RC_CFG_TYPE1_BRIDGE_CONTROL_SEC_PERR_RESP_EN_MASK 0x00010000
-#define BCHP_PCIE_0_RC_CFG_TYPE1_BRIDGE_CONTROL_SEC_PERR_RESP_EN_SHIFT 16
-#define BCHP_PCIE_0_RC_CFG_TYPE1_BRIDGE_CONTROL_SEC_PERR_RESP_EN_DEFAULT 0x00000000
-
-/* PCIE_0_RC_CFG_TYPE1 :: BRIDGE_CONTROL :: INT_PIN [15:08] */
-#define BCHP_PCIE_0_RC_CFG_TYPE1_BRIDGE_CONTROL_INT_PIN_MASK 0x0000ff00
-#define BCHP_PCIE_0_RC_CFG_TYPE1_BRIDGE_CONTROL_INT_PIN_SHIFT 8
-#define BCHP_PCIE_0_RC_CFG_TYPE1_BRIDGE_CONTROL_INT_PIN_DEFAULT 0x00000001
-
-/* PCIE_0_RC_CFG_TYPE1 :: BRIDGE_CONTROL :: INT_LINE [07:00] */
-#define BCHP_PCIE_0_RC_CFG_TYPE1_BRIDGE_CONTROL_INT_LINE_MASK 0x000000ff
-#define BCHP_PCIE_0_RC_CFG_TYPE1_BRIDGE_CONTROL_INT_LINE_SHIFT 0
-#define BCHP_PCIE_0_RC_CFG_TYPE1_BRIDGE_CONTROL_INT_LINE_DEFAULT 0x00000000
-
-#endif /* #ifndef BCHP_PCIE_0_RC_CFG_TYPE1_H__ */
-
-/* End of File */
diff --git a/include/linux/brcmstb/7366b0/bchp_pcie_0_rc_cfg_vendor.h b/include/linux/brcmstb/7366b0/bchp_pcie_0_rc_cfg_vendor.h
deleted file mode 100644
index 33bf5a7..0000000
--- a/include/linux/brcmstb/7366b0/bchp_pcie_0_rc_cfg_vendor.h
+++ /dev/null
@@ -1,173 +0,0 @@
-/***************************************************************************
- * Copyright (c) 1999-2013, Broadcom Corporation
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
- *
- * Module Description:
- * DO NOT EDIT THIS FILE DIRECTLY
- *
- * This module was generated magically with RDB from a source description
- * file. You must edit the source file for changes to be made to this file.
- *
- *
- * Date: Generated on Sat Apr 20 03:07:43 2013
- * MD5 Checksum d41d8cd98f00b204e9800998ecf8427e
- *
- * Compiled with: RDB Utility combo_header.pl
- * RDB Parser 3.0
- * unknown unknown
- * Perl Interpreter 5.008008
- * Operating System linux
- *
- * Revision History:
- *
- * $brcm_Log: $
- *
- ***************************************************************************/
-
-#ifndef BCHP_PCIE_0_RC_CFG_VENDOR_H__
-#define BCHP_PCIE_0_RC_CFG_VENDOR_H__
-
-/***************************************************************************
- *PCIE_0_RC_CFG_VENDOR
- ***************************************************************************/
-#define BCHP_PCIE_0_RC_CFG_VENDOR_VENDOR_CAP 0x00470180 /* vendor_cap */
-#define BCHP_PCIE_0_RC_CFG_VENDOR_VENDOR_SPECIFIC_HEADER 0x00470184 /* vendor_specific_header */
-#define BCHP_PCIE_0_RC_CFG_VENDOR_VENDOR_SPECIFIC_REG1 0x00470188 /* Vendor Specific User Register 1 */
-#define BCHP_PCIE_0_RC_CFG_VENDOR_VENDOR_SPECIFIC_REG2 0x0047018c /* Vendor Specific User Register 2 */
-#define BCHP_PCIE_0_RC_CFG_VENDOR_VENDOR_SPECIFIC_REG3 0x00470190 /* Vendor Specific User Register 3 */
-#define BCHP_PCIE_0_RC_CFG_VENDOR_VENDOR_SPECIFIC_REG4 0x00470194 /* Vendor Specific User Register 4 */
-#define BCHP_PCIE_0_RC_CFG_VENDOR_VENDOR_SPECIFIC_REG5 0x00470198 /* Vendor Specific User Register 5 */
-#define BCHP_PCIE_0_RC_CFG_VENDOR_VENDOR_SPECIFIC_REG6 0x0047019c /* Vendor Specific User Register 6 */
-#define BCHP_PCIE_0_RC_CFG_VENDOR_VENDOR_SPECIFIC_REG7 0x004701a0 /* Vendor Specific User Register 7 */
-#define BCHP_PCIE_0_RC_CFG_VENDOR_VENDOR_SPECIFIC_REG8 0x004701a4 /* Vendor Specific User Register 8 */
-
-/***************************************************************************
- *VENDOR_CAP - vendor_cap
- ***************************************************************************/
-/* PCIE_0_RC_CFG_VENDOR :: VENDOR_CAP :: NEXT [31:20] */
-#define BCHP_PCIE_0_RC_CFG_VENDOR_VENDOR_CAP_NEXT_MASK 0xfff00000
-#define BCHP_PCIE_0_RC_CFG_VENDOR_VENDOR_CAP_NEXT_SHIFT 20
-#define BCHP_PCIE_0_RC_CFG_VENDOR_VENDOR_CAP_NEXT_DEFAULT 0x00000000
-
-/* PCIE_0_RC_CFG_VENDOR :: VENDOR_CAP :: CAP_VER [19:16] */
-#define BCHP_PCIE_0_RC_CFG_VENDOR_VENDOR_CAP_CAP_VER_MASK 0x000f0000
-#define BCHP_PCIE_0_RC_CFG_VENDOR_VENDOR_CAP_CAP_VER_SHIFT 16
-#define BCHP_PCIE_0_RC_CFG_VENDOR_VENDOR_CAP_CAP_VER_DEFAULT 0x00000001
-
-/* PCIE_0_RC_CFG_VENDOR :: VENDOR_CAP :: VENDOR_SPEC_CAP_ID [15:00] */
-#define BCHP_PCIE_0_RC_CFG_VENDOR_VENDOR_CAP_VENDOR_SPEC_CAP_ID_MASK 0x0000ffff
-#define BCHP_PCIE_0_RC_CFG_VENDOR_VENDOR_CAP_VENDOR_SPEC_CAP_ID_SHIFT 0
-#define BCHP_PCIE_0_RC_CFG_VENDOR_VENDOR_CAP_VENDOR_SPEC_CAP_ID_DEFAULT 0x0000000b
-
-/***************************************************************************
- *VENDOR_SPECIFIC_HEADER - vendor_specific_header
- ***************************************************************************/
-/* PCIE_0_RC_CFG_VENDOR :: VENDOR_SPECIFIC_HEADER :: VSEC_LENGTH [31:20] */
-#define BCHP_PCIE_0_RC_CFG_VENDOR_VENDOR_SPECIFIC_HEADER_VSEC_LENGTH_MASK 0xfff00000
-#define BCHP_PCIE_0_RC_CFG_VENDOR_VENDOR_SPECIFIC_HEADER_VSEC_LENGTH_SHIFT 20
-#define BCHP_PCIE_0_RC_CFG_VENDOR_VENDOR_SPECIFIC_HEADER_VSEC_LENGTH_DEFAULT 0x00000028
-
-/* PCIE_0_RC_CFG_VENDOR :: VENDOR_SPECIFIC_HEADER :: VSEC_REV [19:16] */
-#define BCHP_PCIE_0_RC_CFG_VENDOR_VENDOR_SPECIFIC_HEADER_VSEC_REV_MASK 0x000f0000
-#define BCHP_PCIE_0_RC_CFG_VENDOR_VENDOR_SPECIFIC_HEADER_VSEC_REV_SHIFT 16
-#define BCHP_PCIE_0_RC_CFG_VENDOR_VENDOR_SPECIFIC_HEADER_VSEC_REV_DEFAULT 0x00000000
-
-/* PCIE_0_RC_CFG_VENDOR :: VENDOR_SPECIFIC_HEADER :: VSEC_ID [15:00] */
-#define BCHP_PCIE_0_RC_CFG_VENDOR_VENDOR_SPECIFIC_HEADER_VSEC_ID_MASK 0x0000ffff
-#define BCHP_PCIE_0_RC_CFG_VENDOR_VENDOR_SPECIFIC_HEADER_VSEC_ID_SHIFT 0
-#define BCHP_PCIE_0_RC_CFG_VENDOR_VENDOR_SPECIFIC_HEADER_VSEC_ID_DEFAULT 0x00000000
-
-/***************************************************************************
- *VENDOR_SPECIFIC_REG1 - Vendor Specific User Register 1
- ***************************************************************************/
-/* PCIE_0_RC_CFG_VENDOR :: VENDOR_SPECIFIC_REG1 :: Undefined [31:06] */
-#define BCHP_PCIE_0_RC_CFG_VENDOR_VENDOR_SPECIFIC_REG1_Undefined_MASK 0xffffffc0
-#define BCHP_PCIE_0_RC_CFG_VENDOR_VENDOR_SPECIFIC_REG1_Undefined_SHIFT 6
-#define BCHP_PCIE_0_RC_CFG_VENDOR_VENDOR_SPECIFIC_REG1_Undefined_DEFAULT 0x00000000
-
-/* PCIE_0_RC_CFG_VENDOR :: VENDOR_SPECIFIC_REG1 :: ENDIAN_MODE_BAR3 [05:04] */
-#define BCHP_PCIE_0_RC_CFG_VENDOR_VENDOR_SPECIFIC_REG1_ENDIAN_MODE_BAR3_MASK 0x00000030
-#define BCHP_PCIE_0_RC_CFG_VENDOR_VENDOR_SPECIFIC_REG1_ENDIAN_MODE_BAR3_SHIFT 4
-#define BCHP_PCIE_0_RC_CFG_VENDOR_VENDOR_SPECIFIC_REG1_ENDIAN_MODE_BAR3_DEFAULT 0x00000000
-
-/* PCIE_0_RC_CFG_VENDOR :: VENDOR_SPECIFIC_REG1 :: ENDIAN_MODE_BAR2 [03:02] */
-#define BCHP_PCIE_0_RC_CFG_VENDOR_VENDOR_SPECIFIC_REG1_ENDIAN_MODE_BAR2_MASK 0x0000000c
-#define BCHP_PCIE_0_RC_CFG_VENDOR_VENDOR_SPECIFIC_REG1_ENDIAN_MODE_BAR2_SHIFT 2
-#define BCHP_PCIE_0_RC_CFG_VENDOR_VENDOR_SPECIFIC_REG1_ENDIAN_MODE_BAR2_DEFAULT 0x00000000
-
-/* PCIE_0_RC_CFG_VENDOR :: VENDOR_SPECIFIC_REG1 :: ENDIAN_MODE_BAR1 [01:00] */
-#define BCHP_PCIE_0_RC_CFG_VENDOR_VENDOR_SPECIFIC_REG1_ENDIAN_MODE_BAR1_MASK 0x00000003
-#define BCHP_PCIE_0_RC_CFG_VENDOR_VENDOR_SPECIFIC_REG1_ENDIAN_MODE_BAR1_SHIFT 0
-#define BCHP_PCIE_0_RC_CFG_VENDOR_VENDOR_SPECIFIC_REG1_ENDIAN_MODE_BAR1_DEFAULT 0x00000000
-
-/***************************************************************************
- *VENDOR_SPECIFIC_REG2 - Vendor Specific User Register 2
- ***************************************************************************/
-/* PCIE_0_RC_CFG_VENDOR :: VENDOR_SPECIFIC_REG2 :: Undefined [31:00] */
-#define BCHP_PCIE_0_RC_CFG_VENDOR_VENDOR_SPECIFIC_REG2_Undefined_MASK 0xffffffff
-#define BCHP_PCIE_0_RC_CFG_VENDOR_VENDOR_SPECIFIC_REG2_Undefined_SHIFT 0
-#define BCHP_PCIE_0_RC_CFG_VENDOR_VENDOR_SPECIFIC_REG2_Undefined_DEFAULT 0x00000000
-
-/***************************************************************************
- *VENDOR_SPECIFIC_REG3 - Vendor Specific User Register 3
- ***************************************************************************/
-/* PCIE_0_RC_CFG_VENDOR :: VENDOR_SPECIFIC_REG3 :: Undefined [31:00] */
-#define BCHP_PCIE_0_RC_CFG_VENDOR_VENDOR_SPECIFIC_REG3_Undefined_MASK 0xffffffff
-#define BCHP_PCIE_0_RC_CFG_VENDOR_VENDOR_SPECIFIC_REG3_Undefined_SHIFT 0
-#define BCHP_PCIE_0_RC_CFG_VENDOR_VENDOR_SPECIFIC_REG3_Undefined_DEFAULT 0x00000000
-
-/***************************************************************************
- *VENDOR_SPECIFIC_REG4 - Vendor Specific User Register 4
- ***************************************************************************/
-/* PCIE_0_RC_CFG_VENDOR :: VENDOR_SPECIFIC_REG4 :: Undefined [31:00] */
-#define BCHP_PCIE_0_RC_CFG_VENDOR_VENDOR_SPECIFIC_REG4_Undefined_MASK 0xffffffff
-#define BCHP_PCIE_0_RC_CFG_VENDOR_VENDOR_SPECIFIC_REG4_Undefined_SHIFT 0
-#define BCHP_PCIE_0_RC_CFG_VENDOR_VENDOR_SPECIFIC_REG4_Undefined_DEFAULT 0x00000000
-
-/***************************************************************************
- *VENDOR_SPECIFIC_REG5 - Vendor Specific User Register 5
- ***************************************************************************/
-/* PCIE_0_RC_CFG_VENDOR :: VENDOR_SPECIFIC_REG5 :: Undefined [31:00] */
-#define BCHP_PCIE_0_RC_CFG_VENDOR_VENDOR_SPECIFIC_REG5_Undefined_MASK 0xffffffff
-#define BCHP_PCIE_0_RC_CFG_VENDOR_VENDOR_SPECIFIC_REG5_Undefined_SHIFT 0
-#define BCHP_PCIE_0_RC_CFG_VENDOR_VENDOR_SPECIFIC_REG5_Undefined_DEFAULT 0x00000000
-
-/***************************************************************************
- *VENDOR_SPECIFIC_REG6 - Vendor Specific User Register 6
- ***************************************************************************/
-/* PCIE_0_RC_CFG_VENDOR :: VENDOR_SPECIFIC_REG6 :: Undefined [31:00] */
-#define BCHP_PCIE_0_RC_CFG_VENDOR_VENDOR_SPECIFIC_REG6_Undefined_MASK 0xffffffff
-#define BCHP_PCIE_0_RC_CFG_VENDOR_VENDOR_SPECIFIC_REG6_Undefined_SHIFT 0
-#define BCHP_PCIE_0_RC_CFG_VENDOR_VENDOR_SPECIFIC_REG6_Undefined_DEFAULT 0x00000000
-
-/***************************************************************************
- *VENDOR_SPECIFIC_REG7 - Vendor Specific User Register 7
- ***************************************************************************/
-/* PCIE_0_RC_CFG_VENDOR :: VENDOR_SPECIFIC_REG7 :: Undefined [31:00] */
-#define BCHP_PCIE_0_RC_CFG_VENDOR_VENDOR_SPECIFIC_REG7_Undefined_MASK 0xffffffff
-#define BCHP_PCIE_0_RC_CFG_VENDOR_VENDOR_SPECIFIC_REG7_Undefined_SHIFT 0
-#define BCHP_PCIE_0_RC_CFG_VENDOR_VENDOR_SPECIFIC_REG7_Undefined_DEFAULT 0x00000000
-
-/***************************************************************************
- *VENDOR_SPECIFIC_REG8 - Vendor Specific User Register 8
- ***************************************************************************/
-/* PCIE_0_RC_CFG_VENDOR :: VENDOR_SPECIFIC_REG8 :: Undefined [31:00] */
-#define BCHP_PCIE_0_RC_CFG_VENDOR_VENDOR_SPECIFIC_REG8_Undefined_MASK 0xffffffff
-#define BCHP_PCIE_0_RC_CFG_VENDOR_VENDOR_SPECIFIC_REG8_Undefined_SHIFT 0
-#define BCHP_PCIE_0_RC_CFG_VENDOR_VENDOR_SPECIFIC_REG8_Undefined_DEFAULT 0x00000000
-
-#endif /* #ifndef BCHP_PCIE_0_RC_CFG_VENDOR_H__ */
-
-/* End of File */
diff --git a/include/linux/brcmstb/7366b0/bchp_pcie_0_rgr1.h b/include/linux/brcmstb/7366b0/bchp_pcie_0_rgr1.h
deleted file mode 100644
index 9434be2..0000000
--- a/include/linux/brcmstb/7366b0/bchp_pcie_0_rgr1.h
+++ /dev/null
@@ -1,134 +0,0 @@
-/***************************************************************************
- * Copyright (c) 1999-2013, Broadcom Corporation
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
- *
- * Module Description:
- * DO NOT EDIT THIS FILE DIRECTLY
- *
- * This module was generated magically with RDB from a source description
- * file. You must edit the source file for changes to be made to this file.
- *
- *
- * Date: Generated on Sat Apr 20 03:07:46 2013
- * MD5 Checksum d41d8cd98f00b204e9800998ecf8427e
- *
- * Compiled with: RDB Utility combo_header.pl
- * RDB Parser 3.0
- * unknown unknown
- * Perl Interpreter 5.008008
- * Operating System linux
- *
- * Revision History:
- *
- * $brcm_Log: $
- *
- ***************************************************************************/
-
-#ifndef BCHP_PCIE_0_RGR1_H__
-#define BCHP_PCIE_0_RGR1_H__
-
-/***************************************************************************
- *PCIE_0_RGR1 - PCIe RBUS-GISB-RBUS Bridge Registers
- ***************************************************************************/
-#define BCHP_PCIE_0_RGR1_REVISION 0x00479200 /* RGR Bridge Revision */
-#define BCHP_PCIE_0_RGR1_CTRL 0x00479204 /* RGR Bridge Control Register */
-#define BCHP_PCIE_0_RGR1_RBUS_TIMER 0x00479208 /* RGR Bridge RBUS Timer Register */
-#define BCHP_PCIE_0_RGR1_SW_INIT_0 0x0047920c /* RGR Bridge Software Reset 0 Register */
-#define BCHP_PCIE_0_RGR1_SW_INIT_1 0x00479210 /* RGR Bridge Software Reset 1 Register */
-
-/***************************************************************************
- *REVISION - RGR Bridge Revision
- ***************************************************************************/
-/* PCIE_0_RGR1 :: REVISION :: reserved0 [31:16] */
-#define BCHP_PCIE_0_RGR1_REVISION_reserved0_MASK 0xffff0000
-#define BCHP_PCIE_0_RGR1_REVISION_reserved0_SHIFT 16
-
-/* PCIE_0_RGR1 :: REVISION :: MAJOR [15:08] */
-#define BCHP_PCIE_0_RGR1_REVISION_MAJOR_MASK 0x0000ff00
-#define BCHP_PCIE_0_RGR1_REVISION_MAJOR_SHIFT 8
-#define BCHP_PCIE_0_RGR1_REVISION_MAJOR_DEFAULT 0x00000002
-
-/* PCIE_0_RGR1 :: REVISION :: MINOR [07:00] */
-#define BCHP_PCIE_0_RGR1_REVISION_MINOR_MASK 0x000000ff
-#define BCHP_PCIE_0_RGR1_REVISION_MINOR_SHIFT 0
-#define BCHP_PCIE_0_RGR1_REVISION_MINOR_DEFAULT 0x00000000
-
-/***************************************************************************
- *CTRL - RGR Bridge Control Register
- ***************************************************************************/
-/* PCIE_0_RGR1 :: CTRL :: reserved0 [31:02] */
-#define BCHP_PCIE_0_RGR1_CTRL_reserved0_MASK 0xfffffffc
-#define BCHP_PCIE_0_RGR1_CTRL_reserved0_SHIFT 2
-
-/* PCIE_0_RGR1 :: CTRL :: rbus_error_intr [01:01] */
-#define BCHP_PCIE_0_RGR1_CTRL_rbus_error_intr_MASK 0x00000002
-#define BCHP_PCIE_0_RGR1_CTRL_rbus_error_intr_SHIFT 1
-#define BCHP_PCIE_0_RGR1_CTRL_rbus_error_intr_DEFAULT 0x00000000
-#define BCHP_PCIE_0_RGR1_CTRL_rbus_error_intr_INTR_DISABLE 0
-#define BCHP_PCIE_0_RGR1_CTRL_rbus_error_intr_INTR_ENABLE 1
-
-/* PCIE_0_RGR1 :: CTRL :: gisb_error_intr [00:00] */
-#define BCHP_PCIE_0_RGR1_CTRL_gisb_error_intr_MASK 0x00000001
-#define BCHP_PCIE_0_RGR1_CTRL_gisb_error_intr_SHIFT 0
-#define BCHP_PCIE_0_RGR1_CTRL_gisb_error_intr_DEFAULT 0x00000000
-#define BCHP_PCIE_0_RGR1_CTRL_gisb_error_intr_INTR_DISABLE 0
-#define BCHP_PCIE_0_RGR1_CTRL_gisb_error_intr_INTR_ENABLE 1
-
-/***************************************************************************
- *RBUS_TIMER - RGR Bridge RBUS Timer Register
- ***************************************************************************/
-/* PCIE_0_RGR1 :: RBUS_TIMER :: timer_value [31:00] */
-#define BCHP_PCIE_0_RGR1_RBUS_TIMER_timer_value_MASK 0xffffffff
-#define BCHP_PCIE_0_RGR1_RBUS_TIMER_timer_value_SHIFT 0
-#define BCHP_PCIE_0_RGR1_RBUS_TIMER_timer_value_DEFAULT 0x0e297d00
-
-/***************************************************************************
- *SW_INIT_0 - RGR Bridge Software Reset 0 Register
- ***************************************************************************/
-/* PCIE_0_RGR1 :: SW_INIT_0 :: reserved0 [31:01] */
-#define BCHP_PCIE_0_RGR1_SW_INIT_0_reserved0_MASK 0xfffffffe
-#define BCHP_PCIE_0_RGR1_SW_INIT_0_reserved0_SHIFT 1
-
-/* PCIE_0_RGR1 :: SW_INIT_0 :: SPARE_SW_INIT [00:00] */
-#define BCHP_PCIE_0_RGR1_SW_INIT_0_SPARE_SW_INIT_MASK 0x00000001
-#define BCHP_PCIE_0_RGR1_SW_INIT_0_SPARE_SW_INIT_SHIFT 0
-#define BCHP_PCIE_0_RGR1_SW_INIT_0_SPARE_SW_INIT_DEFAULT 0x00000000
-#define BCHP_PCIE_0_RGR1_SW_INIT_0_SPARE_SW_INIT_DEASSERT 0
-#define BCHP_PCIE_0_RGR1_SW_INIT_0_SPARE_SW_INIT_ASSERT 1
-
-/***************************************************************************
- *SW_INIT_1 - RGR Bridge Software Reset 1 Register
- ***************************************************************************/
-/* PCIE_0_RGR1 :: SW_INIT_1 :: reserved0 [31:02] */
-#define BCHP_PCIE_0_RGR1_SW_INIT_1_reserved0_MASK 0xfffffffc
-#define BCHP_PCIE_0_RGR1_SW_INIT_1_reserved0_SHIFT 2
-
-/* PCIE_0_RGR1 :: SW_INIT_1 :: PCIE_BRIDGE_SW_INIT [01:01] */
-#define BCHP_PCIE_0_RGR1_SW_INIT_1_PCIE_BRIDGE_SW_INIT_MASK 0x00000002
-#define BCHP_PCIE_0_RGR1_SW_INIT_1_PCIE_BRIDGE_SW_INIT_SHIFT 1
-#define BCHP_PCIE_0_RGR1_SW_INIT_1_PCIE_BRIDGE_SW_INIT_DEFAULT 0x00000001
-#define BCHP_PCIE_0_RGR1_SW_INIT_1_PCIE_BRIDGE_SW_INIT_DEASSERT 0
-#define BCHP_PCIE_0_RGR1_SW_INIT_1_PCIE_BRIDGE_SW_INIT_ASSERT 1
-
-/* PCIE_0_RGR1 :: SW_INIT_1 :: PCIE_SW_PERST [00:00] */
-#define BCHP_PCIE_0_RGR1_SW_INIT_1_PCIE_SW_PERST_MASK 0x00000001
-#define BCHP_PCIE_0_RGR1_SW_INIT_1_PCIE_SW_PERST_SHIFT 0
-#define BCHP_PCIE_0_RGR1_SW_INIT_1_PCIE_SW_PERST_DEFAULT 0x00000001
-#define BCHP_PCIE_0_RGR1_SW_INIT_1_PCIE_SW_PERST_DEASSERT 0
-#define BCHP_PCIE_0_RGR1_SW_INIT_1_PCIE_SW_PERST_ASSERT 1
-
-#endif /* #ifndef BCHP_PCIE_0_RGR1_H__ */
-
-/* End of File */
diff --git a/include/linux/brcmstb/7366b0/bchp_sdio_0_cfg.h b/include/linux/brcmstb/7366b0/bchp_sdio_0_cfg.h
deleted file mode 100644
index f824eff..0000000
--- a/include/linux/brcmstb/7366b0/bchp_sdio_0_cfg.h
+++ /dev/null
@@ -1,836 +0,0 @@
-/***************************************************************************
- * Copyright (c) 1999-2014, Broadcom Corporation
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
- *
- * Module Description:
- * DO NOT EDIT THIS FILE DIRECTLY
- *
- * This module was generated magically with RDB from a source description
- * file. You must edit the source file for changes to be made to this file.
- *
- *
- * Date: Generated on Wed Sep 3 15:00:00 2014
- * Full Compile MD5 Checksum 10187d4079392bab2546025f43274d34
- * (minus title and desc)
- * MD5 Checksum c1587c5e16f21f52e852e7c7a65c7811
- *
- * Compiled with: RDB Utility combo_header.pl
- * RDB Parser 3.0
- * unknown unknown
- * Perl Interpreter 5.008005
- * Operating System linux
- *
- * Revision History:
- *
- * $brcm_Log: $
- *
- ***************************************************************************/
-
-#ifndef BCHP_SDIO_0_CFG_H__
-#define BCHP_SDIO_0_CFG_H__
-
-/***************************************************************************
- *SDIO_0_CFG - SDIO (CARD0) Configuration Registers
- ***************************************************************************/
-#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1 0x00440100 /* SDIO EMMC Control Register */
-#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL2 0x00440104 /* SDIO EMMC Control Register */
-#define BCHP_SDIO_0_CFG_TP_OUT_SEL 0x00440108 /* SDIO TP_OUT Control Register */
-#define BCHP_SDIO_0_CFG_CAP_REG_OVERRIDE 0x0044010c /* SDIO CAPABILITIES override Register */
-#define BCHP_SDIO_0_CFG_CAP_REG0 0x00440110 /* SDIO CAPABILITIES override Register[31:0] */
-#define BCHP_SDIO_0_CFG_CAP_REG1 0x00440114 /* SDIO CAPABILITIES override Register[63:32] */
-#define BCHP_SDIO_0_CFG_PRESET1 0x00440118 /* SDIO PRESET_INIT/PRESET_DS override Register */
-#define BCHP_SDIO_0_CFG_PRESET2 0x0044011c /* SDIO PRESET_HS/PRESET_SDR12 override Register */
-#define BCHP_SDIO_0_CFG_PRESET3 0x00440120 /* SDIO PRESET_SDR25/PRESET_SDR50 override Register */
-#define BCHP_SDIO_0_CFG_PRESET4 0x00440124 /* SDIO PRESET_SDR104/PRESET_DDR50 override Register */
-#define BCHP_SDIO_0_CFG_SD_CLOCK_DELAY 0x00440128 /* SDIO Clock delay register */
-#define BCHP_SDIO_0_CFG_SD_PAD_DRV 0x0044012c /* SDIO Clock delay register */
-#define BCHP_SDIO_0_CFG_IP_DLY 0x00440130 /* SDIO Host input delay register */
-#define BCHP_SDIO_0_CFG_OP_DLY 0x00440134 /* SDIO Host output delay register */
-#define BCHP_SDIO_0_CFG_TUNING 0x00440138 /* SDIO Host tuning configuration register */
-#define BCHP_SDIO_0_CFG_VOLT_CTRL 0x0044013c /* SDIO Host 1p8V control logic select register */
-#define BCHP_SDIO_0_CFG_DEBUG_TAP_DLY 0x00440140 /* Debug TAP delay setting register */
-#define BCHP_SDIO_0_CFG_DEBUG_A2S_BRIDGE_STATUS 0x00440144 /* Debug A2S Bridge Status */
-#define BCHP_SDIO_0_CFG_DEBUG_A2S_REQ_START_ADDR 0x00440148 /* Debug register to read AHB req start address (32b) */
-#define BCHP_SDIO_0_CFG_DEBUG_A2S_REQ_END_ADDR 0x0044014c /* Debug register to read AHB req end address (32b) */
-#define BCHP_SDIO_0_CFG_DEBUG_DISABLE_CLIENT_INIT 0x00440150 /* Disable Client Init */
-#define BCHP_SDIO_0_CFG_SD_PIN_SEL 0x00440154 /* SD Pin Select */
-#define BCHP_SDIO_0_CFG_MAX_CURRENT 0x00440158 /* Max Current Override */
-#define BCHP_SDIO_0_CFG_VERSION 0x004401f0 /* SDIO VERSION Register */
-#define BCHP_SDIO_0_CFG_SCRATCH 0x004401fc /* SDIO Scratch Register */
-
-/***************************************************************************
- *SDIO_EMMC_CTRL1 - SDIO EMMC Control Register
- ***************************************************************************/
-/* SDIO_0_CFG :: SDIO_EMMC_CTRL1 :: SDCD_N_TEST_SEL_EN [31:31] */
-#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_SDCD_N_TEST_SEL_EN_MASK 0x80000000
-#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_SDCD_N_TEST_SEL_EN_SHIFT 31
-#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_SDCD_N_TEST_SEL_EN_DEFAULT 0x00000000
-
-/* SDIO_0_CFG :: SDIO_EMMC_CTRL1 :: SDCD_N_TEST_LEV [30:30] */
-#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_SDCD_N_TEST_LEV_MASK 0x40000000
-#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_SDCD_N_TEST_LEV_SHIFT 30
-#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_SDCD_N_TEST_LEV_DEFAULT 0x00000001
-
-/* SDIO_0_CFG :: SDIO_EMMC_CTRL1 :: reserved0 [29:29] */
-#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_reserved0_MASK 0x20000000
-#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_reserved0_SHIFT 29
-
-/* SDIO_0_CFG :: SDIO_EMMC_CTRL1 :: RETUNING_REQ [28:28] */
-#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_RETUNING_REQ_MASK 0x10000000
-#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_RETUNING_REQ_SHIFT 28
-#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_RETUNING_REQ_DEFAULT 0x00000000
-
-/* SDIO_0_CFG :: SDIO_EMMC_CTRL1 :: reserved1 [27:18] */
-#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_reserved1_MASK 0x0ffc0000
-#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_reserved1_SHIFT 18
-
-/* SDIO_0_CFG :: SDIO_EMMC_CTRL1 :: FORCE_WR_FLUSH [17:17] */
-#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_FORCE_WR_FLUSH_MASK 0x00020000
-#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_FORCE_WR_FLUSH_SHIFT 17
-#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_FORCE_WR_FLUSH_DEFAULT 0x00000000
-
-/* SDIO_0_CFG :: SDIO_EMMC_CTRL1 :: MF_NUM_WR [16:16] */
-#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_MF_NUM_WR_MASK 0x00010000
-#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_MF_NUM_WR_SHIFT 16
-#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_MF_NUM_WR_DEFAULT 0x00000000
-
-/* SDIO_0_CFG :: SDIO_EMMC_CTRL1 :: WORD_ABO [15:15] */
-#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_WORD_ABO_MASK 0x00008000
-#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_WORD_ABO_SHIFT 15
-#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_WORD_ABO_DEFAULT 0x00000000
-
-/* SDIO_0_CFG :: SDIO_EMMC_CTRL1 :: FRAME_NBO [14:14] */
-#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_FRAME_NBO_MASK 0x00004000
-#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_FRAME_NBO_SHIFT 14
-#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_FRAME_NBO_DEFAULT 0x00000000
-
-/* SDIO_0_CFG :: SDIO_EMMC_CTRL1 :: FRAME_NHW [13:13] */
-#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_FRAME_NHW_MASK 0x00002000
-#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_FRAME_NHW_SHIFT 13
-#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_FRAME_NHW_DEFAULT 0x00000001
-
-/* SDIO_0_CFG :: SDIO_EMMC_CTRL1 :: BUFFER_ABO [12:12] */
-#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_BUFFER_ABO_MASK 0x00001000
-#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_BUFFER_ABO_SHIFT 12
-#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_BUFFER_ABO_DEFAULT 0x00000001
-
-/* SDIO_0_CFG :: SDIO_EMMC_CTRL1 :: SCB_BUF_ACC [11:11] */
-#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_SCB_BUF_ACC_MASK 0x00000800
-#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_SCB_BUF_ACC_SHIFT 11
-#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_SCB_BUF_ACC_DEFAULT 0x00000001
-
-/* SDIO_0_CFG :: SDIO_EMMC_CTRL1 :: SCB_SEQ_EN [10:10] */
-#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_SCB_SEQ_EN_MASK 0x00000400
-#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_SCB_SEQ_EN_SHIFT 10
-#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_SCB_SEQ_EN_DEFAULT 0x00000001
-
-/* SDIO_0_CFG :: SDIO_EMMC_CTRL1 :: reserved2 [09:02] */
-#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_reserved2_MASK 0x000003fc
-#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_reserved2_SHIFT 2
-
-/* SDIO_0_CFG :: SDIO_EMMC_CTRL1 :: SCB_MAX_SIZE [01:00] */
-#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_SCB_MAX_SIZE_MASK 0x00000003
-#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_SCB_MAX_SIZE_SHIFT 0
-#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_SCB_MAX_SIZE_DEFAULT 0x00000003
-
-/***************************************************************************
- *SDIO_EMMC_CTRL2 - SDIO EMMC Control Register
- ***************************************************************************/
-/* SDIO_0_CFG :: SDIO_EMMC_CTRL2 :: reserved0 [31:08] */
-#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL2_reserved0_MASK 0xffffff00
-#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL2_reserved0_SHIFT 8
-
-/* SDIO_0_CFG :: SDIO_EMMC_CTRL2 :: REG_ADDR_MAP_BYTE [07:06] */
-#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL2_REG_ADDR_MAP_BYTE_MASK 0x000000c0
-#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL2_REG_ADDR_MAP_BYTE_SHIFT 6
-#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL2_REG_ADDR_MAP_BYTE_DEFAULT 0x00000000
-
-/* SDIO_0_CFG :: SDIO_EMMC_CTRL2 :: reserved1 [05:05] */
-#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL2_reserved1_MASK 0x00000020
-#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL2_reserved1_SHIFT 5
-
-/* SDIO_0_CFG :: SDIO_EMMC_CTRL2 :: REG_ADDR_MAP_HW [04:04] */
-#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL2_REG_ADDR_MAP_HW_MASK 0x00000010
-#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL2_REG_ADDR_MAP_HW_SHIFT 4
-#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL2_REG_ADDR_MAP_HW_DEFAULT 0x00000000
-
-/* SDIO_0_CFG :: SDIO_EMMC_CTRL2 :: REG_DATA_SWAP_RD [03:02] */
-#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL2_REG_DATA_SWAP_RD_MASK 0x0000000c
-#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL2_REG_DATA_SWAP_RD_SHIFT 2
-#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL2_REG_DATA_SWAP_RD_DEFAULT 0x00000000
-
-/* SDIO_0_CFG :: SDIO_EMMC_CTRL2 :: REG_DATA_SWAP_WR [01:00] */
-#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL2_REG_DATA_SWAP_WR_MASK 0x00000003
-#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL2_REG_DATA_SWAP_WR_SHIFT 0
-#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL2_REG_DATA_SWAP_WR_DEFAULT 0x00000000
-
-/***************************************************************************
- *TP_OUT_SEL - SDIO TP_OUT Control Register
- ***************************************************************************/
-/* SDIO_0_CFG :: TP_OUT_SEL :: reserved0 [31:02] */
-#define BCHP_SDIO_0_CFG_TP_OUT_SEL_reserved0_MASK 0xfffffffc
-#define BCHP_SDIO_0_CFG_TP_OUT_SEL_reserved0_SHIFT 2
-
-/* SDIO_0_CFG :: TP_OUT_SEL :: TP_OUT_SELECT [01:00] */
-#define BCHP_SDIO_0_CFG_TP_OUT_SEL_TP_OUT_SELECT_MASK 0x00000003
-#define BCHP_SDIO_0_CFG_TP_OUT_SEL_TP_OUT_SELECT_SHIFT 0
-#define BCHP_SDIO_0_CFG_TP_OUT_SEL_TP_OUT_SELECT_DEFAULT 0x00000000
-
-/***************************************************************************
- *CAP_REG_OVERRIDE - SDIO CAPABILITIES override Register
- ***************************************************************************/
-/* SDIO_0_CFG :: CAP_REG_OVERRIDE :: reserved0 [31:01] */
-#define BCHP_SDIO_0_CFG_CAP_REG_OVERRIDE_reserved0_MASK 0xfffffffe
-#define BCHP_SDIO_0_CFG_CAP_REG_OVERRIDE_reserved0_SHIFT 1
-
-/* SDIO_0_CFG :: CAP_REG_OVERRIDE :: CAP_REG_OVERRIDE [00:00] */
-#define BCHP_SDIO_0_CFG_CAP_REG_OVERRIDE_CAP_REG_OVERRIDE_MASK 0x00000001
-#define BCHP_SDIO_0_CFG_CAP_REG_OVERRIDE_CAP_REG_OVERRIDE_SHIFT 0
-#define BCHP_SDIO_0_CFG_CAP_REG_OVERRIDE_CAP_REG_OVERRIDE_DEFAULT 0x00000000
-
-/***************************************************************************
- *CAP_REG0 - SDIO CAPABILITIES override Register[31:0]
- ***************************************************************************/
-/* SDIO_0_CFG :: CAP_REG0 :: SLOT_TYPE [31:30] */
-#define BCHP_SDIO_0_CFG_CAP_REG0_SLOT_TYPE_MASK 0xc0000000
-#define BCHP_SDIO_0_CFG_CAP_REG0_SLOT_TYPE_SHIFT 30
-#define BCHP_SDIO_0_CFG_CAP_REG0_SLOT_TYPE_DEFAULT 0x00000000
-
-/* SDIO_0_CFG :: CAP_REG0 :: INT_MODE [29:29] */
-#define BCHP_SDIO_0_CFG_CAP_REG0_INT_MODE_MASK 0x20000000
-#define BCHP_SDIO_0_CFG_CAP_REG0_INT_MODE_SHIFT 29
-#define BCHP_SDIO_0_CFG_CAP_REG0_INT_MODE_DEFAULT 0x00000000
-
-/* SDIO_0_CFG :: CAP_REG0 :: SYS_BUS_64BIT [28:28] */
-#define BCHP_SDIO_0_CFG_CAP_REG0_SYS_BUS_64BIT_MASK 0x10000000
-#define BCHP_SDIO_0_CFG_CAP_REG0_SYS_BUS_64BIT_SHIFT 28
-#define BCHP_SDIO_0_CFG_CAP_REG0_SYS_BUS_64BIT_DEFAULT 0x00000000
-
-/* SDIO_0_CFG :: CAP_REG0 :: reserved0 [27:27] */
-#define BCHP_SDIO_0_CFG_CAP_REG0_reserved0_MASK 0x08000000
-#define BCHP_SDIO_0_CFG_CAP_REG0_reserved0_SHIFT 27
-
-/* SDIO_0_CFG :: CAP_REG0 :: VOLTAGE_1P8V [26:26] */
-#define BCHP_SDIO_0_CFG_CAP_REG0_VOLTAGE_1P8V_MASK 0x04000000
-#define BCHP_SDIO_0_CFG_CAP_REG0_VOLTAGE_1P8V_SHIFT 26
-#define BCHP_SDIO_0_CFG_CAP_REG0_VOLTAGE_1P8V_DEFAULT 0x00000000
-
-/* SDIO_0_CFG :: CAP_REG0 :: VOLTAGE_3P0V [25:25] */
-#define BCHP_SDIO_0_CFG_CAP_REG0_VOLTAGE_3P0V_MASK 0x02000000
-#define BCHP_SDIO_0_CFG_CAP_REG0_VOLTAGE_3P0V_SHIFT 25
-#define BCHP_SDIO_0_CFG_CAP_REG0_VOLTAGE_3P0V_DEFAULT 0x00000000
-
-/* SDIO_0_CFG :: CAP_REG0 :: VOLTAGE_3P3V [24:24] */
-#define BCHP_SDIO_0_CFG_CAP_REG0_VOLTAGE_3P3V_MASK 0x01000000
-#define BCHP_SDIO_0_CFG_CAP_REG0_VOLTAGE_3P3V_SHIFT 24
-#define BCHP_SDIO_0_CFG_CAP_REG0_VOLTAGE_3P3V_DEFAULT 0x00000000
-
-/* SDIO_0_CFG :: CAP_REG0 :: SUSPEND_RESUME [23:23] */
-#define BCHP_SDIO_0_CFG_CAP_REG0_SUSPEND_RESUME_MASK 0x00800000
-#define BCHP_SDIO_0_CFG_CAP_REG0_SUSPEND_RESUME_SHIFT 23
-#define BCHP_SDIO_0_CFG_CAP_REG0_SUSPEND_RESUME_DEFAULT 0x00000000
-
-/* SDIO_0_CFG :: CAP_REG0 :: SDMA [22:22] */
-#define BCHP_SDIO_0_CFG_CAP_REG0_SDMA_MASK 0x00400000
-#define BCHP_SDIO_0_CFG_CAP_REG0_SDMA_SHIFT 22
-#define BCHP_SDIO_0_CFG_CAP_REG0_SDMA_DEFAULT 0x00000000
-
-/* SDIO_0_CFG :: CAP_REG0 :: HIGH_SPEED [21:21] */
-#define BCHP_SDIO_0_CFG_CAP_REG0_HIGH_SPEED_MASK 0x00200000
-#define BCHP_SDIO_0_CFG_CAP_REG0_HIGH_SPEED_SHIFT 21
-#define BCHP_SDIO_0_CFG_CAP_REG0_HIGH_SPEED_DEFAULT 0x00000000
-
-/* SDIO_0_CFG :: CAP_REG0 :: reserved1 [20:20] */
-#define BCHP_SDIO_0_CFG_CAP_REG0_reserved1_MASK 0x00100000
-#define BCHP_SDIO_0_CFG_CAP_REG0_reserved1_SHIFT 20
-
-/* SDIO_0_CFG :: CAP_REG0 :: ADMA2 [19:19] */
-#define BCHP_SDIO_0_CFG_CAP_REG0_ADMA2_MASK 0x00080000
-#define BCHP_SDIO_0_CFG_CAP_REG0_ADMA2_SHIFT 19
-#define BCHP_SDIO_0_CFG_CAP_REG0_ADMA2_DEFAULT 0x00000000
-
-/* SDIO_0_CFG :: CAP_REG0 :: EXTENDED_MEDIA [18:18] */
-#define BCHP_SDIO_0_CFG_CAP_REG0_EXTENDED_MEDIA_MASK 0x00040000
-#define BCHP_SDIO_0_CFG_CAP_REG0_EXTENDED_MEDIA_SHIFT 18
-#define BCHP_SDIO_0_CFG_CAP_REG0_EXTENDED_MEDIA_DEFAULT 0x00000000
-
-/* SDIO_0_CFG :: CAP_REG0 :: MAX_BLOCK_LEN [17:16] */
-#define BCHP_SDIO_0_CFG_CAP_REG0_MAX_BLOCK_LEN_MASK 0x00030000
-#define BCHP_SDIO_0_CFG_CAP_REG0_MAX_BLOCK_LEN_SHIFT 16
-#define BCHP_SDIO_0_CFG_CAP_REG0_MAX_BLOCK_LEN_DEFAULT 0x00000000
-
-/* SDIO_0_CFG :: CAP_REG0 :: BASE_CLK_FREQ [15:08] */
-#define BCHP_SDIO_0_CFG_CAP_REG0_BASE_CLK_FREQ_MASK 0x0000ff00
-#define BCHP_SDIO_0_CFG_CAP_REG0_BASE_CLK_FREQ_SHIFT 8
-#define BCHP_SDIO_0_CFG_CAP_REG0_BASE_CLK_FREQ_DEFAULT 0x00000000
-
-/* SDIO_0_CFG :: CAP_REG0 :: TIMEOUT_UNIT [07:07] */
-#define BCHP_SDIO_0_CFG_CAP_REG0_TIMEOUT_UNIT_MASK 0x00000080
-#define BCHP_SDIO_0_CFG_CAP_REG0_TIMEOUT_UNIT_SHIFT 7
-#define BCHP_SDIO_0_CFG_CAP_REG0_TIMEOUT_UNIT_DEFAULT 0x00000000
-
-/* SDIO_0_CFG :: CAP_REG0 :: reserved2 [06:06] */
-#define BCHP_SDIO_0_CFG_CAP_REG0_reserved2_MASK 0x00000040
-#define BCHP_SDIO_0_CFG_CAP_REG0_reserved2_SHIFT 6
-
-/* SDIO_0_CFG :: CAP_REG0 :: TIMEOUT_CLK_FREQ [05:00] */
-#define BCHP_SDIO_0_CFG_CAP_REG0_TIMEOUT_CLK_FREQ_MASK 0x0000003f
-#define BCHP_SDIO_0_CFG_CAP_REG0_TIMEOUT_CLK_FREQ_SHIFT 0
-#define BCHP_SDIO_0_CFG_CAP_REG0_TIMEOUT_CLK_FREQ_DEFAULT 0x00000000
-
-/***************************************************************************
- *CAP_REG1 - SDIO CAPABILITIES override Register[63:32]
- ***************************************************************************/
-/* SDIO_0_CFG :: CAP_REG1 :: reserved0 [31:26] */
-#define BCHP_SDIO_0_CFG_CAP_REG1_reserved0_MASK 0xfc000000
-#define BCHP_SDIO_0_CFG_CAP_REG1_reserved0_SHIFT 26
-
-/* SDIO_0_CFG :: CAP_REG1 :: SPI_BLOCK_MODE [25:25] */
-#define BCHP_SDIO_0_CFG_CAP_REG1_SPI_BLOCK_MODE_MASK 0x02000000
-#define BCHP_SDIO_0_CFG_CAP_REG1_SPI_BLOCK_MODE_SHIFT 25
-#define BCHP_SDIO_0_CFG_CAP_REG1_SPI_BLOCK_MODE_DEFAULT 0x00000000
-
-/* SDIO_0_CFG :: CAP_REG1 :: SPI_MODE [24:24] */
-#define BCHP_SDIO_0_CFG_CAP_REG1_SPI_MODE_MASK 0x01000000
-#define BCHP_SDIO_0_CFG_CAP_REG1_SPI_MODE_SHIFT 24
-#define BCHP_SDIO_0_CFG_CAP_REG1_SPI_MODE_DEFAULT 0x00000000
-
-/* SDIO_0_CFG :: CAP_REG1 :: CLK_MULT [23:16] */
-#define BCHP_SDIO_0_CFG_CAP_REG1_CLK_MULT_MASK 0x00ff0000
-#define BCHP_SDIO_0_CFG_CAP_REG1_CLK_MULT_SHIFT 16
-#define BCHP_SDIO_0_CFG_CAP_REG1_CLK_MULT_DEFAULT 0x00000000
-
-/* SDIO_0_CFG :: CAP_REG1 :: RETUNING_MODE [15:14] */
-#define BCHP_SDIO_0_CFG_CAP_REG1_RETUNING_MODE_MASK 0x0000c000
-#define BCHP_SDIO_0_CFG_CAP_REG1_RETUNING_MODE_SHIFT 14
-#define BCHP_SDIO_0_CFG_CAP_REG1_RETUNING_MODE_DEFAULT 0x00000000
-
-/* SDIO_0_CFG :: CAP_REG1 :: TUNE_SDR50 [13:13] */
-#define BCHP_SDIO_0_CFG_CAP_REG1_TUNE_SDR50_MASK 0x00002000
-#define BCHP_SDIO_0_CFG_CAP_REG1_TUNE_SDR50_SHIFT 13
-#define BCHP_SDIO_0_CFG_CAP_REG1_TUNE_SDR50_DEFAULT 0x00000000
-
-/* SDIO_0_CFG :: CAP_REG1 :: reserved1 [12:12] */
-#define BCHP_SDIO_0_CFG_CAP_REG1_reserved1_MASK 0x00001000
-#define BCHP_SDIO_0_CFG_CAP_REG1_reserved1_SHIFT 12
-
-/* SDIO_0_CFG :: CAP_REG1 :: TIME_RETUNE [11:08] */
-#define BCHP_SDIO_0_CFG_CAP_REG1_TIME_RETUNE_MASK 0x00000f00
-#define BCHP_SDIO_0_CFG_CAP_REG1_TIME_RETUNE_SHIFT 8
-#define BCHP_SDIO_0_CFG_CAP_REG1_TIME_RETUNE_DEFAULT 0x00000000
-
-/* SDIO_0_CFG :: CAP_REG1 :: reserved2 [07:07] */
-#define BCHP_SDIO_0_CFG_CAP_REG1_reserved2_MASK 0x00000080
-#define BCHP_SDIO_0_CFG_CAP_REG1_reserved2_SHIFT 7
-
-/* SDIO_0_CFG :: CAP_REG1 :: DRIVER_D [06:06] */
-#define BCHP_SDIO_0_CFG_CAP_REG1_DRIVER_D_MASK 0x00000040
-#define BCHP_SDIO_0_CFG_CAP_REG1_DRIVER_D_SHIFT 6
-#define BCHP_SDIO_0_CFG_CAP_REG1_DRIVER_D_DEFAULT 0x00000000
-
-/* SDIO_0_CFG :: CAP_REG1 :: DRIVER_C [05:05] */
-#define BCHP_SDIO_0_CFG_CAP_REG1_DRIVER_C_MASK 0x00000020
-#define BCHP_SDIO_0_CFG_CAP_REG1_DRIVER_C_SHIFT 5
-#define BCHP_SDIO_0_CFG_CAP_REG1_DRIVER_C_DEFAULT 0x00000000
-
-/* SDIO_0_CFG :: CAP_REG1 :: DRIVER_A [04:04] */
-#define BCHP_SDIO_0_CFG_CAP_REG1_DRIVER_A_MASK 0x00000010
-#define BCHP_SDIO_0_CFG_CAP_REG1_DRIVER_A_SHIFT 4
-#define BCHP_SDIO_0_CFG_CAP_REG1_DRIVER_A_DEFAULT 0x00000000
-
-/* SDIO_0_CFG :: CAP_REG1 :: reserved3 [03:03] */
-#define BCHP_SDIO_0_CFG_CAP_REG1_reserved3_MASK 0x00000008
-#define BCHP_SDIO_0_CFG_CAP_REG1_reserved3_SHIFT 3
-
-/* SDIO_0_CFG :: CAP_REG1 :: DDR50 [02:02] */
-#define BCHP_SDIO_0_CFG_CAP_REG1_DDR50_MASK 0x00000004
-#define BCHP_SDIO_0_CFG_CAP_REG1_DDR50_SHIFT 2
-#define BCHP_SDIO_0_CFG_CAP_REG1_DDR50_DEFAULT 0x00000000
-
-/* SDIO_0_CFG :: CAP_REG1 :: SDR104 [01:01] */
-#define BCHP_SDIO_0_CFG_CAP_REG1_SDR104_MASK 0x00000002
-#define BCHP_SDIO_0_CFG_CAP_REG1_SDR104_SHIFT 1
-#define BCHP_SDIO_0_CFG_CAP_REG1_SDR104_DEFAULT 0x00000000
-
-/* SDIO_0_CFG :: CAP_REG1 :: SDR50 [00:00] */
-#define BCHP_SDIO_0_CFG_CAP_REG1_SDR50_MASK 0x00000001
-#define BCHP_SDIO_0_CFG_CAP_REG1_SDR50_SHIFT 0
-#define BCHP_SDIO_0_CFG_CAP_REG1_SDR50_DEFAULT 0x00000000
-
-/***************************************************************************
- *PRESET1 - SDIO PRESET_INIT/PRESET_DS override Register
- ***************************************************************************/
-/* SDIO_0_CFG :: PRESET1 :: PRESET1_OVERRIDE [31:31] */
-#define BCHP_SDIO_0_CFG_PRESET1_PRESET1_OVERRIDE_MASK 0x80000000
-#define BCHP_SDIO_0_CFG_PRESET1_PRESET1_OVERRIDE_SHIFT 31
-#define BCHP_SDIO_0_CFG_PRESET1_PRESET1_OVERRIDE_DEFAULT 0x00000000
-
-/* SDIO_0_CFG :: PRESET1 :: reserved0 [30:29] */
-#define BCHP_SDIO_0_CFG_PRESET1_reserved0_MASK 0x60000000
-#define BCHP_SDIO_0_CFG_PRESET1_reserved0_SHIFT 29
-
-/* SDIO_0_CFG :: PRESET1 :: PRESET_INIT [28:16] */
-#define BCHP_SDIO_0_CFG_PRESET1_PRESET_INIT_MASK 0x1fff0000
-#define BCHP_SDIO_0_CFG_PRESET1_PRESET_INIT_SHIFT 16
-#define BCHP_SDIO_0_CFG_PRESET1_PRESET_INIT_DEFAULT 0x00000000
-
-/* SDIO_0_CFG :: PRESET1 :: reserved1 [15:13] */
-#define BCHP_SDIO_0_CFG_PRESET1_reserved1_MASK 0x0000e000
-#define BCHP_SDIO_0_CFG_PRESET1_reserved1_SHIFT 13
-
-/* SDIO_0_CFG :: PRESET1 :: PRESET_DS [12:00] */
-#define BCHP_SDIO_0_CFG_PRESET1_PRESET_DS_MASK 0x00001fff
-#define BCHP_SDIO_0_CFG_PRESET1_PRESET_DS_SHIFT 0
-#define BCHP_SDIO_0_CFG_PRESET1_PRESET_DS_DEFAULT 0x00000001
-
-/***************************************************************************
- *PRESET2 - SDIO PRESET_HS/PRESET_SDR12 override Register
- ***************************************************************************/
-/* SDIO_0_CFG :: PRESET2 :: PRESET2_OVERRIDE [31:31] */
-#define BCHP_SDIO_0_CFG_PRESET2_PRESET2_OVERRIDE_MASK 0x80000000
-#define BCHP_SDIO_0_CFG_PRESET2_PRESET2_OVERRIDE_SHIFT 31
-#define BCHP_SDIO_0_CFG_PRESET2_PRESET2_OVERRIDE_DEFAULT 0x00000000
-
-/* SDIO_0_CFG :: PRESET2 :: reserved0 [30:29] */
-#define BCHP_SDIO_0_CFG_PRESET2_reserved0_MASK 0x60000000
-#define BCHP_SDIO_0_CFG_PRESET2_reserved0_SHIFT 29
-
-/* SDIO_0_CFG :: PRESET2 :: PRESET_SDR12 [28:16] */
-#define BCHP_SDIO_0_CFG_PRESET2_PRESET_SDR12_MASK 0x1fff0000
-#define BCHP_SDIO_0_CFG_PRESET2_PRESET_SDR12_SHIFT 16
-#define BCHP_SDIO_0_CFG_PRESET2_PRESET_SDR12_DEFAULT 0x00000002
-
-/* SDIO_0_CFG :: PRESET2 :: reserved1 [15:13] */
-#define BCHP_SDIO_0_CFG_PRESET2_reserved1_MASK 0x0000e000
-#define BCHP_SDIO_0_CFG_PRESET2_reserved1_SHIFT 13
-
-/* SDIO_0_CFG :: PRESET2 :: PRESET_HS [12:00] */
-#define BCHP_SDIO_0_CFG_PRESET2_PRESET_HS_MASK 0x00001fff
-#define BCHP_SDIO_0_CFG_PRESET2_PRESET_HS_SHIFT 0
-#define BCHP_SDIO_0_CFG_PRESET2_PRESET_HS_DEFAULT 0x00000003
-
-/***************************************************************************
- *PRESET3 - SDIO PRESET_SDR25/PRESET_SDR50 override Register
- ***************************************************************************/
-/* SDIO_0_CFG :: PRESET3 :: PRESET3_OVERRIDE [31:31] */
-#define BCHP_SDIO_0_CFG_PRESET3_PRESET3_OVERRIDE_MASK 0x80000000
-#define BCHP_SDIO_0_CFG_PRESET3_PRESET3_OVERRIDE_SHIFT 31
-#define BCHP_SDIO_0_CFG_PRESET3_PRESET3_OVERRIDE_DEFAULT 0x00000000
-
-/* SDIO_0_CFG :: PRESET3 :: reserved0 [30:29] */
-#define BCHP_SDIO_0_CFG_PRESET3_reserved0_MASK 0x60000000
-#define BCHP_SDIO_0_CFG_PRESET3_reserved0_SHIFT 29
-
-/* SDIO_0_CFG :: PRESET3 :: PRESET_SDR50 [28:16] */
-#define BCHP_SDIO_0_CFG_PRESET3_PRESET_SDR50_MASK 0x1fff0000
-#define BCHP_SDIO_0_CFG_PRESET3_PRESET_SDR50_SHIFT 16
-#define BCHP_SDIO_0_CFG_PRESET3_PRESET_SDR50_DEFAULT 0x00000002
-
-/* SDIO_0_CFG :: PRESET3 :: reserved1 [15:13] */
-#define BCHP_SDIO_0_CFG_PRESET3_reserved1_MASK 0x0000e000
-#define BCHP_SDIO_0_CFG_PRESET3_reserved1_SHIFT 13
-
-/* SDIO_0_CFG :: PRESET3 :: PRESET_SDR25 [12:00] */
-#define BCHP_SDIO_0_CFG_PRESET3_PRESET_SDR25_MASK 0x00001fff
-#define BCHP_SDIO_0_CFG_PRESET3_PRESET_SDR25_SHIFT 0
-#define BCHP_SDIO_0_CFG_PRESET3_PRESET_SDR25_DEFAULT 0x00000003
-
-/***************************************************************************
- *PRESET4 - SDIO PRESET_SDR104/PRESET_DDR50 override Register
- ***************************************************************************/
-/* SDIO_0_CFG :: PRESET4 :: PRESET4_OVERRIDE [31:31] */
-#define BCHP_SDIO_0_CFG_PRESET4_PRESET4_OVERRIDE_MASK 0x80000000
-#define BCHP_SDIO_0_CFG_PRESET4_PRESET4_OVERRIDE_SHIFT 31
-#define BCHP_SDIO_0_CFG_PRESET4_PRESET4_OVERRIDE_DEFAULT 0x00000000
-
-/* SDIO_0_CFG :: PRESET4 :: reserved0 [30:29] */
-#define BCHP_SDIO_0_CFG_PRESET4_reserved0_MASK 0x60000000
-#define BCHP_SDIO_0_CFG_PRESET4_reserved0_SHIFT 29
-
-/* SDIO_0_CFG :: PRESET4 :: PRESET_DDR50 [28:16] */
-#define BCHP_SDIO_0_CFG_PRESET4_PRESET_DDR50_MASK 0x1fff0000
-#define BCHP_SDIO_0_CFG_PRESET4_PRESET_DDR50_SHIFT 16
-#define BCHP_SDIO_0_CFG_PRESET4_PRESET_DDR50_DEFAULT 0x00000002
-
-/* SDIO_0_CFG :: PRESET4 :: reserved1 [15:13] */
-#define BCHP_SDIO_0_CFG_PRESET4_reserved1_MASK 0x0000e000
-#define BCHP_SDIO_0_CFG_PRESET4_reserved1_SHIFT 13
-
-/* SDIO_0_CFG :: PRESET4 :: PRESET_SDR104 [12:00] */
-#define BCHP_SDIO_0_CFG_PRESET4_PRESET_SDR104_MASK 0x00001fff
-#define BCHP_SDIO_0_CFG_PRESET4_PRESET_SDR104_SHIFT 0
-#define BCHP_SDIO_0_CFG_PRESET4_PRESET_SDR104_DEFAULT 0x00000003
-
-/***************************************************************************
- *SD_CLOCK_DELAY - SDIO Clock delay register
- ***************************************************************************/
-/* SDIO_0_CFG :: SD_CLOCK_DELAY :: reserved0 [31:31] */
-#define BCHP_SDIO_0_CFG_SD_CLOCK_DELAY_reserved0_MASK 0x80000000
-#define BCHP_SDIO_0_CFG_SD_CLOCK_DELAY_reserved0_SHIFT 31
-
-/* SDIO_0_CFG :: SD_CLOCK_DELAY :: CLOCK_DELAY_OVERRIDE [30:30] */
-#define BCHP_SDIO_0_CFG_SD_CLOCK_DELAY_CLOCK_DELAY_OVERRIDE_MASK 0x40000000
-#define BCHP_SDIO_0_CFG_SD_CLOCK_DELAY_CLOCK_DELAY_OVERRIDE_SHIFT 30
-#define BCHP_SDIO_0_CFG_SD_CLOCK_DELAY_CLOCK_DELAY_OVERRIDE_DEFAULT 0x00000001
-
-/* SDIO_0_CFG :: SD_CLOCK_DELAY :: INPUT_CLOCK_SEL [29:29] */
-#define BCHP_SDIO_0_CFG_SD_CLOCK_DELAY_INPUT_CLOCK_SEL_MASK 0x20000000
-#define BCHP_SDIO_0_CFG_SD_CLOCK_DELAY_INPUT_CLOCK_SEL_SHIFT 29
-
-/* SDIO_0_CFG :: SD_CLOCK_DELAY :: reserved1 [28:12] */
-#define BCHP_SDIO_0_CFG_SD_CLOCK_DELAY_reserved1_MASK 0x1ffff000
-#define BCHP_SDIO_0_CFG_SD_CLOCK_DELAY_reserved1_SHIFT 12
-
-/* SDIO_0_CFG :: SD_CLOCK_DELAY :: OUTPUT_CLOCK_DELAY [11:08] */
-#define BCHP_SDIO_0_CFG_SD_CLOCK_DELAY_OUTPUT_CLOCK_DELAY_MASK 0x00000f00
-#define BCHP_SDIO_0_CFG_SD_CLOCK_DELAY_OUTPUT_CLOCK_DELAY_SHIFT 8
-#define BCHP_SDIO_0_CFG_SD_CLOCK_DELAY_OUTPUT_CLOCK_DELAY_DEFAULT 0x00000000
-
-/* SDIO_0_CFG :: SD_CLOCK_DELAY :: INTERNAL_CLOCK_DELAY [07:04] */
-#define BCHP_SDIO_0_CFG_SD_CLOCK_DELAY_INTERNAL_CLOCK_DELAY_MASK 0x000000f0
-#define BCHP_SDIO_0_CFG_SD_CLOCK_DELAY_INTERNAL_CLOCK_DELAY_SHIFT 4
-#define BCHP_SDIO_0_CFG_SD_CLOCK_DELAY_INTERNAL_CLOCK_DELAY_DEFAULT 0x0000000f
-
-/* SDIO_0_CFG :: SD_CLOCK_DELAY :: INPUT_CLOCK_DELAY [03:00] */
-#define BCHP_SDIO_0_CFG_SD_CLOCK_DELAY_INPUT_CLOCK_DELAY_MASK 0x0000000f
-#define BCHP_SDIO_0_CFG_SD_CLOCK_DELAY_INPUT_CLOCK_DELAY_SHIFT 0
-#define BCHP_SDIO_0_CFG_SD_CLOCK_DELAY_INPUT_CLOCK_DELAY_DEFAULT 0x0000000f
-
-/***************************************************************************
- *SD_PAD_DRV - SDIO Clock delay register
- ***************************************************************************/
-/* SDIO_0_CFG :: SD_PAD_DRV :: OVERRIDE_EN [31:31] */
-#define BCHP_SDIO_0_CFG_SD_PAD_DRV_OVERRIDE_EN_MASK 0x80000000
-#define BCHP_SDIO_0_CFG_SD_PAD_DRV_OVERRIDE_EN_SHIFT 31
-#define BCHP_SDIO_0_CFG_SD_PAD_DRV_OVERRIDE_EN_DEFAULT 0x00000000
-
-/* SDIO_0_CFG :: SD_PAD_DRV :: reserved0 [30:23] */
-#define BCHP_SDIO_0_CFG_SD_PAD_DRV_reserved0_MASK 0x7f800000
-#define BCHP_SDIO_0_CFG_SD_PAD_DRV_reserved0_SHIFT 23
-
-/* SDIO_0_CFG :: SD_PAD_DRV :: CLK_VAL [22:20] */
-#define BCHP_SDIO_0_CFG_SD_PAD_DRV_CLK_VAL_MASK 0x00700000
-#define BCHP_SDIO_0_CFG_SD_PAD_DRV_CLK_VAL_SHIFT 20
-#define BCHP_SDIO_0_CFG_SD_PAD_DRV_CLK_VAL_DEFAULT 0x00000005
-
-/* SDIO_0_CFG :: SD_PAD_DRV :: reserved1 [19:19] */
-#define BCHP_SDIO_0_CFG_SD_PAD_DRV_reserved1_MASK 0x00080000
-#define BCHP_SDIO_0_CFG_SD_PAD_DRV_reserved1_SHIFT 19
-
-/* SDIO_0_CFG :: SD_PAD_DRV :: CMD_VAL [18:16] */
-#define BCHP_SDIO_0_CFG_SD_PAD_DRV_CMD_VAL_MASK 0x00070000
-#define BCHP_SDIO_0_CFG_SD_PAD_DRV_CMD_VAL_SHIFT 16
-#define BCHP_SDIO_0_CFG_SD_PAD_DRV_CMD_VAL_DEFAULT 0x00000005
-
-/* SDIO_0_CFG :: SD_PAD_DRV :: reserved2 [15:15] */
-#define BCHP_SDIO_0_CFG_SD_PAD_DRV_reserved2_MASK 0x00008000
-#define BCHP_SDIO_0_CFG_SD_PAD_DRV_reserved2_SHIFT 15
-
-/* SDIO_0_CFG :: SD_PAD_DRV :: DAT3_VAL [14:12] */
-#define BCHP_SDIO_0_CFG_SD_PAD_DRV_DAT3_VAL_MASK 0x00007000
-#define BCHP_SDIO_0_CFG_SD_PAD_DRV_DAT3_VAL_SHIFT 12
-#define BCHP_SDIO_0_CFG_SD_PAD_DRV_DAT3_VAL_DEFAULT 0x00000005
-
-/* SDIO_0_CFG :: SD_PAD_DRV :: reserved3 [11:11] */
-#define BCHP_SDIO_0_CFG_SD_PAD_DRV_reserved3_MASK 0x00000800
-#define BCHP_SDIO_0_CFG_SD_PAD_DRV_reserved3_SHIFT 11
-
-/* SDIO_0_CFG :: SD_PAD_DRV :: DAT2_VAL [10:08] */
-#define BCHP_SDIO_0_CFG_SD_PAD_DRV_DAT2_VAL_MASK 0x00000700
-#define BCHP_SDIO_0_CFG_SD_PAD_DRV_DAT2_VAL_SHIFT 8
-#define BCHP_SDIO_0_CFG_SD_PAD_DRV_DAT2_VAL_DEFAULT 0x00000005
-
-/* SDIO_0_CFG :: SD_PAD_DRV :: reserved4 [07:07] */
-#define BCHP_SDIO_0_CFG_SD_PAD_DRV_reserved4_MASK 0x00000080
-#define BCHP_SDIO_0_CFG_SD_PAD_DRV_reserved4_SHIFT 7
-
-/* SDIO_0_CFG :: SD_PAD_DRV :: DAT1_VAL [06:04] */
-#define BCHP_SDIO_0_CFG_SD_PAD_DRV_DAT1_VAL_MASK 0x00000070
-#define BCHP_SDIO_0_CFG_SD_PAD_DRV_DAT1_VAL_SHIFT 4
-#define BCHP_SDIO_0_CFG_SD_PAD_DRV_DAT1_VAL_DEFAULT 0x00000005
-
-/* SDIO_0_CFG :: SD_PAD_DRV :: reserved5 [03:03] */
-#define BCHP_SDIO_0_CFG_SD_PAD_DRV_reserved5_MASK 0x00000008
-#define BCHP_SDIO_0_CFG_SD_PAD_DRV_reserved5_SHIFT 3
-
-/* SDIO_0_CFG :: SD_PAD_DRV :: DAT0_VAL [02:00] */
-#define BCHP_SDIO_0_CFG_SD_PAD_DRV_DAT0_VAL_MASK 0x00000007
-#define BCHP_SDIO_0_CFG_SD_PAD_DRV_DAT0_VAL_SHIFT 0
-#define BCHP_SDIO_0_CFG_SD_PAD_DRV_DAT0_VAL_DEFAULT 0x00000005
-
-/***************************************************************************
- *IP_DLY - SDIO Host input delay register
- ***************************************************************************/
-/* SDIO_0_CFG :: IP_DLY :: IP_TAP_EN [31:31] */
-#define BCHP_SDIO_0_CFG_IP_DLY_IP_TAP_EN_MASK 0x80000000
-#define BCHP_SDIO_0_CFG_IP_DLY_IP_TAP_EN_SHIFT 31
-
-/* SDIO_0_CFG :: IP_DLY :: FORCE_USE_IP_TUNE_CLK [30:30] */
-#define BCHP_SDIO_0_CFG_IP_DLY_FORCE_USE_IP_TUNE_CLK_MASK 0x40000000
-#define BCHP_SDIO_0_CFG_IP_DLY_FORCE_USE_IP_TUNE_CLK_SHIFT 30
-#define BCHP_SDIO_0_CFG_IP_DLY_FORCE_USE_IP_TUNE_CLK_DEFAULT 0x00000000
-
-/* SDIO_0_CFG :: IP_DLY :: reserved0 [29:18] */
-#define BCHP_SDIO_0_CFG_IP_DLY_reserved0_MASK 0x3ffc0000
-#define BCHP_SDIO_0_CFG_IP_DLY_reserved0_SHIFT 18
-
-/* SDIO_0_CFG :: IP_DLY :: IP_DELAY_CTRL [17:16] */
-#define BCHP_SDIO_0_CFG_IP_DLY_IP_DELAY_CTRL_MASK 0x00030000
-#define BCHP_SDIO_0_CFG_IP_DLY_IP_DELAY_CTRL_SHIFT 16
-#define BCHP_SDIO_0_CFG_IP_DLY_IP_DELAY_CTRL_DEFAULT 0x00000000
-
-/* SDIO_0_CFG :: IP_DLY :: reserved1 [15:06] */
-#define BCHP_SDIO_0_CFG_IP_DLY_reserved1_MASK 0x0000ffc0
-#define BCHP_SDIO_0_CFG_IP_DLY_reserved1_SHIFT 6
-
-/* SDIO_0_CFG :: IP_DLY :: reserved_for_padding2 [05:05] */
-#define BCHP_SDIO_0_CFG_IP_DLY_reserved_for_padding2_MASK 0x00000020
-#define BCHP_SDIO_0_CFG_IP_DLY_reserved_for_padding2_SHIFT 5
-
-/* SDIO_0_CFG :: IP_DLY :: IP_TAP_DELAY [04:00] */
-#define BCHP_SDIO_0_CFG_IP_DLY_IP_TAP_DELAY_MASK 0x0000001f
-#define BCHP_SDIO_0_CFG_IP_DLY_IP_TAP_DELAY_SHIFT 0
-
-/***************************************************************************
- *OP_DLY - SDIO Host output delay register
- ***************************************************************************/
-/* SDIO_0_CFG :: OP_DLY :: OP_TAP_EN [31:31] */
-#define BCHP_SDIO_0_CFG_OP_DLY_OP_TAP_EN_MASK 0x80000000
-#define BCHP_SDIO_0_CFG_OP_DLY_OP_TAP_EN_SHIFT 31
-
-/* SDIO_0_CFG :: OP_DLY :: reserved0 [30:18] */
-#define BCHP_SDIO_0_CFG_OP_DLY_reserved0_MASK 0x7ffc0000
-#define BCHP_SDIO_0_CFG_OP_DLY_reserved0_SHIFT 18
-
-/* SDIO_0_CFG :: OP_DLY :: OP_DELAY_CTRL [17:16] */
-#define BCHP_SDIO_0_CFG_OP_DLY_OP_DELAY_CTRL_MASK 0x00030000
-#define BCHP_SDIO_0_CFG_OP_DLY_OP_DELAY_CTRL_SHIFT 16
-#define BCHP_SDIO_0_CFG_OP_DLY_OP_DELAY_CTRL_DEFAULT 0x00000000
-
-/* SDIO_0_CFG :: OP_DLY :: reserved1 [15:04] */
-#define BCHP_SDIO_0_CFG_OP_DLY_reserved1_MASK 0x0000fff0
-#define BCHP_SDIO_0_CFG_OP_DLY_reserved1_SHIFT 4
-
-/* SDIO_0_CFG :: OP_DLY :: OP_TAP_DELAY [03:00] */
-#define BCHP_SDIO_0_CFG_OP_DLY_OP_TAP_DELAY_MASK 0x0000000f
-#define BCHP_SDIO_0_CFG_OP_DLY_OP_TAP_DELAY_SHIFT 0
-
-/***************************************************************************
- *TUNING - SDIO Host tuning configuration register
- ***************************************************************************/
-/* SDIO_0_CFG :: TUNING :: reserved0 [31:06] */
-#define BCHP_SDIO_0_CFG_TUNING_reserved0_MASK 0xffffffc0
-#define BCHP_SDIO_0_CFG_TUNING_reserved0_SHIFT 6
-
-/* SDIO_0_CFG :: TUNING :: TUNING_COUNT [05:00] */
-#define BCHP_SDIO_0_CFG_TUNING_TUNING_COUNT_MASK 0x0000003f
-#define BCHP_SDIO_0_CFG_TUNING_TUNING_COUNT_SHIFT 0
-#define BCHP_SDIO_0_CFG_TUNING_TUNING_COUNT_DEFAULT 0x00000020
-
-/***************************************************************************
- *VOLT_CTRL - SDIO Host 1p8V control logic select register
- ***************************************************************************/
-/* SDIO_0_CFG :: VOLT_CTRL :: reserved0 [31:05] */
-#define BCHP_SDIO_0_CFG_VOLT_CTRL_reserved0_MASK 0xffffffe0
-#define BCHP_SDIO_0_CFG_VOLT_CTRL_reserved0_SHIFT 5
-
-/* SDIO_0_CFG :: VOLT_CTRL :: POW_INV_EN [04:04] */
-#define BCHP_SDIO_0_CFG_VOLT_CTRL_POW_INV_EN_MASK 0x00000010
-#define BCHP_SDIO_0_CFG_VOLT_CTRL_POW_INV_EN_SHIFT 4
-#define BCHP_SDIO_0_CFG_VOLT_CTRL_POW_INV_EN_DEFAULT 0x00000000
-
-/* SDIO_0_CFG :: VOLT_CTRL :: 1P8V_VAL [03:03] */
-#define BCHP_SDIO_0_CFG_VOLT_CTRL_1P8V_VAL_MASK 0x00000008
-#define BCHP_SDIO_0_CFG_VOLT_CTRL_1P8V_VAL_SHIFT 3
-#define BCHP_SDIO_0_CFG_VOLT_CTRL_1P8V_VAL_DEFAULT 0x00000000
-
-/* SDIO_0_CFG :: VOLT_CTRL :: 1P8V_INV_EN [02:02] */
-#define BCHP_SDIO_0_CFG_VOLT_CTRL_1P8V_INV_EN_MASK 0x00000004
-#define BCHP_SDIO_0_CFG_VOLT_CTRL_1P8V_INV_EN_SHIFT 2
-#define BCHP_SDIO_0_CFG_VOLT_CTRL_1P8V_INV_EN_DEFAULT 0x00000000
-
-/* SDIO_0_CFG :: VOLT_CTRL :: 1P8V_CTRL_SEL [01:00] */
-#define BCHP_SDIO_0_CFG_VOLT_CTRL_1P8V_CTRL_SEL_MASK 0x00000003
-#define BCHP_SDIO_0_CFG_VOLT_CTRL_1P8V_CTRL_SEL_SHIFT 0
-#define BCHP_SDIO_0_CFG_VOLT_CTRL_1P8V_CTRL_SEL_DEFAULT 0x00000000
-
-/***************************************************************************
- *DEBUG_TAP_DLY - Debug TAP delay setting register
- ***************************************************************************/
-/* SDIO_0_CFG :: DEBUG_TAP_DLY :: reserved0 [31:12] */
-#define BCHP_SDIO_0_CFG_DEBUG_TAP_DLY_reserved0_MASK 0xfffff000
-#define BCHP_SDIO_0_CFG_DEBUG_TAP_DLY_reserved0_SHIFT 12
-
-/* SDIO_0_CFG :: DEBUG_TAP_DLY :: DEBUG_OP_TAP_DELAY [11:08] */
-#define BCHP_SDIO_0_CFG_DEBUG_TAP_DLY_DEBUG_OP_TAP_DELAY_MASK 0x00000f00
-#define BCHP_SDIO_0_CFG_DEBUG_TAP_DLY_DEBUG_OP_TAP_DELAY_SHIFT 8
-
-/* SDIO_0_CFG :: DEBUG_TAP_DLY :: reserved1 [07:07] */
-#define BCHP_SDIO_0_CFG_DEBUG_TAP_DLY_reserved1_MASK 0x00000080
-#define BCHP_SDIO_0_CFG_DEBUG_TAP_DLY_reserved1_SHIFT 7
-
-/* SDIO_0_CFG :: DEBUG_TAP_DLY :: DEBUG_IP_TAP_DELAY [06:00] */
-#define BCHP_SDIO_0_CFG_DEBUG_TAP_DLY_DEBUG_IP_TAP_DELAY_MASK 0x0000007f
-#define BCHP_SDIO_0_CFG_DEBUG_TAP_DLY_DEBUG_IP_TAP_DELAY_SHIFT 0
-
-/***************************************************************************
- *DEBUG_A2S_BRIDGE_STATUS - Debug A2S Bridge Status
- ***************************************************************************/
-/* SDIO_0_CFG :: DEBUG_A2S_BRIDGE_STATUS :: s2a_req_done_sync [31:31] */
-#define BCHP_SDIO_0_CFG_DEBUG_A2S_BRIDGE_STATUS_s2a_req_done_sync_MASK 0x80000000
-#define BCHP_SDIO_0_CFG_DEBUG_A2S_BRIDGE_STATUS_s2a_req_done_sync_SHIFT 31
-
-/* SDIO_0_CFG :: DEBUG_A2S_BRIDGE_STATUS :: reserved0 [30:29] */
-#define BCHP_SDIO_0_CFG_DEBUG_A2S_BRIDGE_STATUS_reserved0_MASK 0x60000000
-#define BCHP_SDIO_0_CFG_DEBUG_A2S_BRIDGE_STATUS_reserved0_SHIFT 29
-
-/* SDIO_0_CFG :: DEBUG_A2S_BRIDGE_STATUS :: a2s_req_xfer [28:28] */
-#define BCHP_SDIO_0_CFG_DEBUG_A2S_BRIDGE_STATUS_a2s_req_xfer_MASK 0x10000000
-#define BCHP_SDIO_0_CFG_DEBUG_A2S_BRIDGE_STATUS_a2s_req_xfer_SHIFT 28
-
-/* SDIO_0_CFG :: DEBUG_A2S_BRIDGE_STATUS :: reserved1 [27:25] */
-#define BCHP_SDIO_0_CFG_DEBUG_A2S_BRIDGE_STATUS_reserved1_MASK 0x0e000000
-#define BCHP_SDIO_0_CFG_DEBUG_A2S_BRIDGE_STATUS_reserved1_SHIFT 25
-
-/* SDIO_0_CFG :: DEBUG_A2S_BRIDGE_STATUS :: a2s_req_write [24:24] */
-#define BCHP_SDIO_0_CFG_DEBUG_A2S_BRIDGE_STATUS_a2s_req_write_MASK 0x01000000
-#define BCHP_SDIO_0_CFG_DEBUG_A2S_BRIDGE_STATUS_a2s_req_write_SHIFT 24
-
-/* SDIO_0_CFG :: DEBUG_A2S_BRIDGE_STATUS :: a2s_first_bwe4 [23:20] */
-#define BCHP_SDIO_0_CFG_DEBUG_A2S_BRIDGE_STATUS_a2s_first_bwe4_MASK 0x00f00000
-#define BCHP_SDIO_0_CFG_DEBUG_A2S_BRIDGE_STATUS_a2s_first_bwe4_SHIFT 20
-
-/* SDIO_0_CFG :: DEBUG_A2S_BRIDGE_STATUS :: a2s_last_bwe4 [19:16] */
-#define BCHP_SDIO_0_CFG_DEBUG_A2S_BRIDGE_STATUS_a2s_last_bwe4_MASK 0x000f0000
-#define BCHP_SDIO_0_CFG_DEBUG_A2S_BRIDGE_STATUS_a2s_last_bwe4_SHIFT 16
-
-/* SDIO_0_CFG :: DEBUG_A2S_BRIDGE_STATUS :: reserved2 [15:07] */
-#define BCHP_SDIO_0_CFG_DEBUG_A2S_BRIDGE_STATUS_reserved2_MASK 0x0000ff80
-#define BCHP_SDIO_0_CFG_DEBUG_A2S_BRIDGE_STATUS_reserved2_SHIFT 7
-
-/* SDIO_0_CFG :: DEBUG_A2S_BRIDGE_STATUS :: scb_state [06:04] */
-#define BCHP_SDIO_0_CFG_DEBUG_A2S_BRIDGE_STATUS_scb_state_MASK 0x00000070
-#define BCHP_SDIO_0_CFG_DEBUG_A2S_BRIDGE_STATUS_scb_state_SHIFT 4
-
-/* SDIO_0_CFG :: DEBUG_A2S_BRIDGE_STATUS :: reserved3 [03:03] */
-#define BCHP_SDIO_0_CFG_DEBUG_A2S_BRIDGE_STATUS_reserved3_MASK 0x00000008
-#define BCHP_SDIO_0_CFG_DEBUG_A2S_BRIDGE_STATUS_reserved3_SHIFT 3
-
-/* SDIO_0_CFG :: DEBUG_A2S_BRIDGE_STATUS :: ahb_state [02:00] */
-#define BCHP_SDIO_0_CFG_DEBUG_A2S_BRIDGE_STATUS_ahb_state_MASK 0x00000007
-#define BCHP_SDIO_0_CFG_DEBUG_A2S_BRIDGE_STATUS_ahb_state_SHIFT 0
-
-/***************************************************************************
- *DEBUG_A2S_REQ_START_ADDR - Debug register to read AHB req start address (32b)
- ***************************************************************************/
-/* SDIO_0_CFG :: DEBUG_A2S_REQ_START_ADDR :: START_ADDR [31:00] */
-#define BCHP_SDIO_0_CFG_DEBUG_A2S_REQ_START_ADDR_START_ADDR_MASK 0xffffffff
-#define BCHP_SDIO_0_CFG_DEBUG_A2S_REQ_START_ADDR_START_ADDR_SHIFT 0
-
-/***************************************************************************
- *DEBUG_A2S_REQ_END_ADDR - Debug register to read AHB req end address (32b)
- ***************************************************************************/
-/* SDIO_0_CFG :: DEBUG_A2S_REQ_END_ADDR :: END_ADDR [31:00] */
-#define BCHP_SDIO_0_CFG_DEBUG_A2S_REQ_END_ADDR_END_ADDR_MASK 0xffffffff
-#define BCHP_SDIO_0_CFG_DEBUG_A2S_REQ_END_ADDR_END_ADDR_SHIFT 0
-
-/***************************************************************************
- *DEBUG_DISABLE_CLIENT_INIT - Disable Client Init
- ***************************************************************************/
-/* SDIO_0_CFG :: DEBUG_DISABLE_CLIENT_INIT :: reserved0 [31:01] */
-#define BCHP_SDIO_0_CFG_DEBUG_DISABLE_CLIENT_INIT_reserved0_MASK 0xfffffffe
-#define BCHP_SDIO_0_CFG_DEBUG_DISABLE_CLIENT_INIT_reserved0_SHIFT 1
-
-/* SDIO_0_CFG :: DEBUG_DISABLE_CLIENT_INIT :: diable_client_init [00:00] */
-#define BCHP_SDIO_0_CFG_DEBUG_DISABLE_CLIENT_INIT_diable_client_init_MASK 0x00000001
-#define BCHP_SDIO_0_CFG_DEBUG_DISABLE_CLIENT_INIT_diable_client_init_SHIFT 0
-#define BCHP_SDIO_0_CFG_DEBUG_DISABLE_CLIENT_INIT_diable_client_init_DEFAULT 0x00000000
-
-/***************************************************************************
- *SD_PIN_SEL - SD Pin Select
- ***************************************************************************/
-/* SDIO_0_CFG :: SD_PIN_SEL :: reserved0 [31:02] */
-#define BCHP_SDIO_0_CFG_SD_PIN_SEL_reserved0_MASK 0xfffffffc
-#define BCHP_SDIO_0_CFG_SD_PIN_SEL_reserved0_SHIFT 2
-
-/* SDIO_0_CFG :: SD_PIN_SEL :: PIN_SEL [01:00] */
-#define BCHP_SDIO_0_CFG_SD_PIN_SEL_PIN_SEL_MASK 0x00000003
-#define BCHP_SDIO_0_CFG_SD_PIN_SEL_PIN_SEL_SHIFT 0
-#define BCHP_SDIO_0_CFG_SD_PIN_SEL_PIN_SEL_DEFAULT 0x00000000
-
-/***************************************************************************
- *MAX_CURRENT - Max Current Override
- ***************************************************************************/
-/* SDIO_0_CFG :: MAX_CURRENT :: OVERRIDE [31:31] */
-#define BCHP_SDIO_0_CFG_MAX_CURRENT_OVERRIDE_MASK 0x80000000
-#define BCHP_SDIO_0_CFG_MAX_CURRENT_OVERRIDE_SHIFT 31
-#define BCHP_SDIO_0_CFG_MAX_CURRENT_OVERRIDE_DEFAULT 0x00000000
-
-/* SDIO_0_CFG :: MAX_CURRENT :: reserved0 [30:24] */
-#define BCHP_SDIO_0_CFG_MAX_CURRENT_reserved0_MASK 0x7f000000
-#define BCHP_SDIO_0_CFG_MAX_CURRENT_reserved0_SHIFT 24
-
-/* SDIO_0_CFG :: MAX_CURRENT :: OVERRIDE_1P8V [23:16] */
-#define BCHP_SDIO_0_CFG_MAX_CURRENT_OVERRIDE_1P8V_MASK 0x00ff0000
-#define BCHP_SDIO_0_CFG_MAX_CURRENT_OVERRIDE_1P8V_SHIFT 16
-#define BCHP_SDIO_0_CFG_MAX_CURRENT_OVERRIDE_1P8V_DEFAULT 0x00000000
-
-/* SDIO_0_CFG :: MAX_CURRENT :: OVERRIDE_3P3V [15:08] */
-#define BCHP_SDIO_0_CFG_MAX_CURRENT_OVERRIDE_3P3V_MASK 0x0000ff00
-#define BCHP_SDIO_0_CFG_MAX_CURRENT_OVERRIDE_3P3V_SHIFT 8
-#define BCHP_SDIO_0_CFG_MAX_CURRENT_OVERRIDE_3P3V_DEFAULT 0x00000000
-
-/* SDIO_0_CFG :: MAX_CURRENT :: OVERRIDE_3P0V [07:00] */
-#define BCHP_SDIO_0_CFG_MAX_CURRENT_OVERRIDE_3P0V_MASK 0x000000ff
-#define BCHP_SDIO_0_CFG_MAX_CURRENT_OVERRIDE_3P0V_SHIFT 0
-#define BCHP_SDIO_0_CFG_MAX_CURRENT_OVERRIDE_3P0V_DEFAULT 0x00000000
-
-/***************************************************************************
- *VERSION - SDIO VERSION Register
- ***************************************************************************/
-/* SDIO_0_CFG :: VERSION :: reserved0 [31:24] */
-#define BCHP_SDIO_0_CFG_VERSION_reserved0_MASK 0xff000000
-#define BCHP_SDIO_0_CFG_VERSION_reserved0_SHIFT 24
-
-/* SDIO_0_CFG :: VERSION :: MAJOR_ID [23:16] */
-#define BCHP_SDIO_0_CFG_VERSION_MAJOR_ID_MASK 0x00ff0000
-#define BCHP_SDIO_0_CFG_VERSION_MAJOR_ID_SHIFT 16
-#define BCHP_SDIO_0_CFG_VERSION_MAJOR_ID_DEFAULT 0x00000003
-
-/* SDIO_0_CFG :: VERSION :: MINOR_VER [15:08] */
-#define BCHP_SDIO_0_CFG_VERSION_MINOR_VER_MASK 0x0000ff00
-#define BCHP_SDIO_0_CFG_VERSION_MINOR_VER_SHIFT 8
-#define BCHP_SDIO_0_CFG_VERSION_MINOR_VER_DEFAULT 0x00000002
-
-/* SDIO_0_CFG :: VERSION :: reserved1 [07:04] */
-#define BCHP_SDIO_0_CFG_VERSION_reserved1_MASK 0x000000f0
-#define BCHP_SDIO_0_CFG_VERSION_reserved1_SHIFT 4
-
-/* SDIO_0_CFG :: VERSION :: METAL_VER [03:00] */
-#define BCHP_SDIO_0_CFG_VERSION_METAL_VER_MASK 0x0000000f
-#define BCHP_SDIO_0_CFG_VERSION_METAL_VER_SHIFT 0
-#define BCHP_SDIO_0_CFG_VERSION_METAL_VER_DEFAULT 0x00000000
-
-/***************************************************************************
- *SCRATCH - SDIO Scratch Register
- ***************************************************************************/
-/* SDIO_0_CFG :: SCRATCH :: SCRATCH_BITS [31:00] */
-#define BCHP_SDIO_0_CFG_SCRATCH_SCRATCH_BITS_MASK 0xffffffff
-#define BCHP_SDIO_0_CFG_SCRATCH_SCRATCH_BITS_SHIFT 0
-#define BCHP_SDIO_0_CFG_SCRATCH_SCRATCH_BITS_DEFAULT 0x00000000
-
-#endif /* #ifndef BCHP_SDIO_0_CFG_H__ */
-
-/* End of File */
diff --git a/include/linux/brcmstb/7366b0/bchp_shimphy_addr_cntl_0.h b/include/linux/brcmstb/7366b0/bchp_shimphy_addr_cntl_0.h
deleted file mode 100644
index 13e8d35..0000000
--- a/include/linux/brcmstb/7366b0/bchp_shimphy_addr_cntl_0.h
+++ /dev/null
@@ -1,631 +0,0 @@
-/***************************************************************************
- * Copyright (c) 1999-2014, Broadcom Corporation
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
- *
- * Module Description:
- * DO NOT EDIT THIS FILE DIRECTLY
- *
- * This module was generated magically with RDB from a source description
- * file. You must edit the source file for changes to be made to this file.
- *
- *
- * Date: Generated on Thu Apr 24 03:08:55 2014
- * Full Compile MD5 Checksum 1af2c2cf28828ece5496e1312aac0166
- * (minus title and desc)
- * MD5 Checksum 3203ffce85e3fc9a10f84123e54057b0
- *
- * Compiled with: RDB Utility combo_header.pl
- * RDB Parser 3.0
- * unknown unknown
- * Perl Interpreter 5.008008
- * Operating System linux
- *
- * Revision History:
- *
- * $brcm_Log: $
- *
- ***************************************************************************/
-
-#ifndef BCHP_SHIMPHY_ADDR_CNTL_0_H__
-#define BCHP_SHIMPHY_ADDR_CNTL_0_H__
-
-/***************************************************************************
- *SHIMPHY_ADDR_CNTL_0 - DDR SHIMPHY Control Registers
- ***************************************************************************/
-#define BCHP_SHIMPHY_ADDR_CNTL_0_CONFIG 0x00508000 /* SHIMPHY Config register */
-#define BCHP_SHIMPHY_ADDR_CNTL_0_SHIMPHY_REV_ID 0x00508004 /* SHIMPHY Revision ID Register. */
-#define BCHP_SHIMPHY_ADDR_CNTL_0_RESET 0x00508008 /* DDR soft reset register */
-#define BCHP_SHIMPHY_ADDR_CNTL_0_CMD_DATA_FIFO 0x00508028 /* Command and Data FIFO Status Register */
-#define BCHP_SHIMPHY_ADDR_CNTL_0_RD_DATAPATH 0x0050802c /* Read Datapath Status Register */
-#define BCHP_SHIMPHY_ADDR_CNTL_0_FLAG_BUS 0x00508030 /* TP_OUT bus value Register */
-#define BCHP_SHIMPHY_ADDR_CNTL_0_MISC 0x00508034 /* Miscellaneous Register */
-#define BCHP_SHIMPHY_ADDR_CNTL_0_DFI_CONTROL 0x00508038 /* DFI Interface Control Register */
-#define BCHP_SHIMPHY_ADDR_CNTL_0_DFI_STATUS 0x0050803c /* DFI Interface Status Register */
-#define BCHP_SHIMPHY_ADDR_CNTL_0_PHY_LPM_STAT 0x00508040 /* PHY Power Control Status Register */
-#define BCHP_SHIMPHY_ADDR_CNTL_0_ALERT_STATUS 0x00508044 /* DDR4 Alert Status Register */
-#define BCHP_SHIMPHY_ADDR_CNTL_0_IDLE_POWER_SAVING 0x00508048 /* DDR PHY Idle power saving Control register */
-#define BCHP_SHIMPHY_ADDR_CNTL_0_DDR_PAD_CNTRL 0x0050808c /* DDR Pad control register */
-#define BCHP_SHIMPHY_ADDR_CNTL_0_SHIMPHY_STATUS 0x0050809c /* SHIMPHY Status Register */
-#define BCHP_SHIMPHY_ADDR_CNTL_0_SPARE0_RW 0x005080a4 /* Spare register */
-#define BCHP_SHIMPHY_ADDR_CNTL_0_SPARE1_RW 0x005080a8 /* Spare register */
-#define BCHP_SHIMPHY_ADDR_CNTL_0_SPARE0_RO 0x005080ac /* Spare register */
-#define BCHP_SHIMPHY_ADDR_CNTL_0_SPARE1_RO 0x005080b0 /* Spare register */
-#define BCHP_SHIMPHY_ADDR_CNTL_0_DDR3_RESET_CNTRL 0x005080b4 /* FORCE_DDR3_RESET Deassert Register */
-#define BCHP_SHIMPHY_ADDR_CNTL_0_GDDR5_CRC_CONTROL 0x005080b8 /* GDDR5 CRC CONTROL Register */
-#define BCHP_SHIMPHY_ADDR_CNTL_0_GDDR5_CLIENT_CRC_EN_31_0 0x005080bc /* GDDR5 Client CRC Enable Register */
-#define BCHP_SHIMPHY_ADDR_CNTL_0_GDDR5_CLIENT_CRC_EN_63_32 0x005080c0 /* GDDR5 Client CRC Enable Register */
-#define BCHP_SHIMPHY_ADDR_CNTL_0_GDDR5_CLIENT_CRC_EN_95_64 0x005080c4 /* GDDR5 Client CRC Enable Register */
-#define BCHP_SHIMPHY_ADDR_CNTL_0_GDDR5_CLIENT_CRC_EN_127_96 0x005080c8 /* GDDR5 Client CRC Enable Register */
-#define BCHP_SHIMPHY_ADDR_CNTL_0_GDDR5_CLIENT_CRC_EN_159_128 0x005080cc /* GDDR5 Client CRC Enable Register */
-#define BCHP_SHIMPHY_ADDR_CNTL_0_GDDR5_CLIENT_CRC_EN_191_160 0x005080d0 /* GDDR5 Client CRC Enable Register */
-#define BCHP_SHIMPHY_ADDR_CNTL_0_GDDR5_CLIENT_CRC_EN_223_192 0x005080d4 /* GDDR5 Client CRC Enable Register */
-#define BCHP_SHIMPHY_ADDR_CNTL_0_GDDR5_CLIENT_CRC_EN_255_224 0x005080d8 /* GDDR5 Client CRC Enable Register */
-#define BCHP_SHIMPHY_ADDR_CNTL_0_GDDR5_CRC_WRITE_ERROR_CNT 0x005080dc /* GDDR5 Write CRC Error Count */
-#define BCHP_SHIMPHY_ADDR_CNTL_0_GDDR5_CRC_READ_ERROR_CNT 0x005080e0 /* GDDR5 Read CRC Error Count */
-
-/***************************************************************************
- *CONFIG - SHIMPHY Config register
- ***************************************************************************/
-/* SHIMPHY_ADDR_CNTL_0 :: CONFIG :: DFI_CLK_DISABLE [31:31] */
-#define BCHP_SHIMPHY_ADDR_CNTL_0_CONFIG_DFI_CLK_DISABLE_MASK 0x80000000
-#define BCHP_SHIMPHY_ADDR_CNTL_0_CONFIG_DFI_CLK_DISABLE_SHIFT 31
-#define BCHP_SHIMPHY_ADDR_CNTL_0_CONFIG_DFI_CLK_DISABLE_DEFAULT 0x00000000
-
-/* SHIMPHY_ADDR_CNTL_0 :: CONFIG :: DRAM_NOP_OR_DSEL_CMD [30:30] */
-#define BCHP_SHIMPHY_ADDR_CNTL_0_CONFIG_DRAM_NOP_OR_DSEL_CMD_MASK 0x40000000
-#define BCHP_SHIMPHY_ADDR_CNTL_0_CONFIG_DRAM_NOP_OR_DSEL_CMD_SHIFT 30
-#define BCHP_SHIMPHY_ADDR_CNTL_0_CONFIG_DRAM_NOP_OR_DSEL_CMD_DEFAULT 0x00000000
-
-/* SHIMPHY_ADDR_CNTL_0 :: CONFIG :: LAST_RD_STRETCH [29:29] */
-#define BCHP_SHIMPHY_ADDR_CNTL_0_CONFIG_LAST_RD_STRETCH_MASK 0x20000000
-#define BCHP_SHIMPHY_ADDR_CNTL_0_CONFIG_LAST_RD_STRETCH_SHIFT 29
-#define BCHP_SHIMPHY_ADDR_CNTL_0_CONFIG_LAST_RD_STRETCH_DEFAULT 0x00000000
-
-/* SHIMPHY_ADDR_CNTL_0 :: CONFIG :: reserved0 [28:24] */
-#define BCHP_SHIMPHY_ADDR_CNTL_0_CONFIG_reserved0_MASK 0x1f000000
-#define BCHP_SHIMPHY_ADDR_CNTL_0_CONFIG_reserved0_SHIFT 24
-
-/* SHIMPHY_ADDR_CNTL_0 :: CONFIG :: LAST_READ_LATENCY [23:16] */
-#define BCHP_SHIMPHY_ADDR_CNTL_0_CONFIG_LAST_READ_LATENCY_MASK 0x00ff0000
-#define BCHP_SHIMPHY_ADDR_CNTL_0_CONFIG_LAST_READ_LATENCY_SHIFT 16
-#define BCHP_SHIMPHY_ADDR_CNTL_0_CONFIG_LAST_READ_LATENCY_DEFAULT 0x0000000b
-
-/* SHIMPHY_ADDR_CNTL_0 :: CONFIG :: READ_LATENCY [15:08] */
-#define BCHP_SHIMPHY_ADDR_CNTL_0_CONFIG_READ_LATENCY_MASK 0x0000ff00
-#define BCHP_SHIMPHY_ADDR_CNTL_0_CONFIG_READ_LATENCY_SHIFT 8
-#define BCHP_SHIMPHY_ADDR_CNTL_0_CONFIG_READ_LATENCY_DEFAULT 0x00000007
-
-/* SHIMPHY_ADDR_CNTL_0 :: CONFIG :: WRITE_LATENCY [07:00] */
-#define BCHP_SHIMPHY_ADDR_CNTL_0_CONFIG_WRITE_LATENCY_MASK 0x000000ff
-#define BCHP_SHIMPHY_ADDR_CNTL_0_CONFIG_WRITE_LATENCY_SHIFT 0
-#define BCHP_SHIMPHY_ADDR_CNTL_0_CONFIG_WRITE_LATENCY_DEFAULT 0x0000000e
-
-/***************************************************************************
- *SHIMPHY_REV_ID - SHIMPHY Revision ID Register.
- ***************************************************************************/
-/* SHIMPHY_ADDR_CNTL_0 :: SHIMPHY_REV_ID :: reserved0 [31:16] */
-#define BCHP_SHIMPHY_ADDR_CNTL_0_SHIMPHY_REV_ID_reserved0_MASK 0xffff0000
-#define BCHP_SHIMPHY_ADDR_CNTL_0_SHIMPHY_REV_ID_reserved0_SHIFT 16
-
-/* SHIMPHY_ADDR_CNTL_0 :: SHIMPHY_REV_ID :: MAJOR_ID [15:08] */
-#define BCHP_SHIMPHY_ADDR_CNTL_0_SHIMPHY_REV_ID_MAJOR_ID_MASK 0x0000ff00
-#define BCHP_SHIMPHY_ADDR_CNTL_0_SHIMPHY_REV_ID_MAJOR_ID_SHIFT 8
-#define BCHP_SHIMPHY_ADDR_CNTL_0_SHIMPHY_REV_ID_MAJOR_ID_DEFAULT 0x00000001
-
-/* SHIMPHY_ADDR_CNTL_0 :: SHIMPHY_REV_ID :: MINOR_ID [07:00] */
-#define BCHP_SHIMPHY_ADDR_CNTL_0_SHIMPHY_REV_ID_MINOR_ID_MASK 0x000000ff
-#define BCHP_SHIMPHY_ADDR_CNTL_0_SHIMPHY_REV_ID_MINOR_ID_SHIFT 0
-#define BCHP_SHIMPHY_ADDR_CNTL_0_SHIMPHY_REV_ID_MINOR_ID_DEFAULT 0x00000000
-
-/***************************************************************************
- *RESET - DDR soft reset register
- ***************************************************************************/
-/* SHIMPHY_ADDR_CNTL_0 :: RESET :: reserved0 [31:03] */
-#define BCHP_SHIMPHY_ADDR_CNTL_0_RESET_reserved0_MASK 0xfffffff8
-#define BCHP_SHIMPHY_ADDR_CNTL_0_RESET_reserved0_SHIFT 3
-
-/* SHIMPHY_ADDR_CNTL_0 :: RESET :: DATAPATH_216_RESET [02:02] */
-#define BCHP_SHIMPHY_ADDR_CNTL_0_RESET_DATAPATH_216_RESET_MASK 0x00000004
-#define BCHP_SHIMPHY_ADDR_CNTL_0_RESET_DATAPATH_216_RESET_SHIFT 2
-#define BCHP_SHIMPHY_ADDR_CNTL_0_RESET_DATAPATH_216_RESET_DEFAULT 0x00000000
-
-/* SHIMPHY_ADDR_CNTL_0 :: RESET :: DATAPATH_DDR_RESET [01:01] */
-#define BCHP_SHIMPHY_ADDR_CNTL_0_RESET_DATAPATH_DDR_RESET_MASK 0x00000002
-#define BCHP_SHIMPHY_ADDR_CNTL_0_RESET_DATAPATH_DDR_RESET_SHIFT 1
-#define BCHP_SHIMPHY_ADDR_CNTL_0_RESET_DATAPATH_DDR_RESET_DEFAULT 0x00000001
-
-/* SHIMPHY_ADDR_CNTL_0 :: RESET :: PHY_PWRUP_RSB [00:00] */
-#define BCHP_SHIMPHY_ADDR_CNTL_0_RESET_PHY_PWRUP_RSB_MASK 0x00000001
-#define BCHP_SHIMPHY_ADDR_CNTL_0_RESET_PHY_PWRUP_RSB_SHIFT 0
-#define BCHP_SHIMPHY_ADDR_CNTL_0_RESET_PHY_PWRUP_RSB_DEFAULT 0x00000000
-
-/***************************************************************************
- *CMD_DATA_FIFO - Command and Data FIFO Status Register
- ***************************************************************************/
-/* SHIMPHY_ADDR_CNTL_0 :: CMD_DATA_FIFO :: reserved0 [31:26] */
-#define BCHP_SHIMPHY_ADDR_CNTL_0_CMD_DATA_FIFO_reserved0_MASK 0xfc000000
-#define BCHP_SHIMPHY_ADDR_CNTL_0_CMD_DATA_FIFO_reserved0_SHIFT 26
-
-/* SHIMPHY_ADDR_CNTL_0 :: CMD_DATA_FIFO :: FIFO_FULL [25:25] */
-#define BCHP_SHIMPHY_ADDR_CNTL_0_CMD_DATA_FIFO_FIFO_FULL_MASK 0x02000000
-#define BCHP_SHIMPHY_ADDR_CNTL_0_CMD_DATA_FIFO_FIFO_FULL_SHIFT 25
-
-/* SHIMPHY_ADDR_CNTL_0 :: CMD_DATA_FIFO :: FIFO_EMPTY [24:24] */
-#define BCHP_SHIMPHY_ADDR_CNTL_0_CMD_DATA_FIFO_FIFO_EMPTY_MASK 0x01000000
-#define BCHP_SHIMPHY_ADDR_CNTL_0_CMD_DATA_FIFO_FIFO_EMPTY_SHIFT 24
-
-/* SHIMPHY_ADDR_CNTL_0 :: CMD_DATA_FIFO :: reserved1 [23:10] */
-#define BCHP_SHIMPHY_ADDR_CNTL_0_CMD_DATA_FIFO_reserved1_MASK 0x00fffc00
-#define BCHP_SHIMPHY_ADDR_CNTL_0_CMD_DATA_FIFO_reserved1_SHIFT 10
-
-/* SHIMPHY_ADDR_CNTL_0 :: CMD_DATA_FIFO :: WR_PNTR [09:05] */
-#define BCHP_SHIMPHY_ADDR_CNTL_0_CMD_DATA_FIFO_WR_PNTR_MASK 0x000003e0
-#define BCHP_SHIMPHY_ADDR_CNTL_0_CMD_DATA_FIFO_WR_PNTR_SHIFT 5
-
-/* SHIMPHY_ADDR_CNTL_0 :: CMD_DATA_FIFO :: RD_PNTR [04:00] */
-#define BCHP_SHIMPHY_ADDR_CNTL_0_CMD_DATA_FIFO_RD_PNTR_MASK 0x0000001f
-#define BCHP_SHIMPHY_ADDR_CNTL_0_CMD_DATA_FIFO_RD_PNTR_SHIFT 0
-
-/***************************************************************************
- *RD_DATAPATH - Read Datapath Status Register
- ***************************************************************************/
-/* SHIMPHY_ADDR_CNTL_0 :: RD_DATAPATH :: reserved0 [31:10] */
-#define BCHP_SHIMPHY_ADDR_CNTL_0_RD_DATAPATH_reserved0_MASK 0xfffffc00
-#define BCHP_SHIMPHY_ADDR_CNTL_0_RD_DATAPATH_reserved0_SHIFT 10
-
-/* SHIMPHY_ADDR_CNTL_0 :: RD_DATAPATH :: WR_PNTR [09:05] */
-#define BCHP_SHIMPHY_ADDR_CNTL_0_RD_DATAPATH_WR_PNTR_MASK 0x000003e0
-#define BCHP_SHIMPHY_ADDR_CNTL_0_RD_DATAPATH_WR_PNTR_SHIFT 5
-
-/* SHIMPHY_ADDR_CNTL_0 :: RD_DATAPATH :: RD_PNTR [04:00] */
-#define BCHP_SHIMPHY_ADDR_CNTL_0_RD_DATAPATH_RD_PNTR_MASK 0x0000001f
-#define BCHP_SHIMPHY_ADDR_CNTL_0_RD_DATAPATH_RD_PNTR_SHIFT 0
-
-/***************************************************************************
- *FLAG_BUS - TP_OUT bus value Register
- ***************************************************************************/
-/* SHIMPHY_ADDR_CNTL_0 :: FLAG_BUS :: FLAG_BUS [31:00] */
-#define BCHP_SHIMPHY_ADDR_CNTL_0_FLAG_BUS_FLAG_BUS_MASK 0xffffffff
-#define BCHP_SHIMPHY_ADDR_CNTL_0_FLAG_BUS_FLAG_BUS_SHIFT 0
-
-/***************************************************************************
- *MISC - Miscellaneous Register
- ***************************************************************************/
-/* SHIMPHY_ADDR_CNTL_0 :: MISC :: reserved0 [31:20] */
-#define BCHP_SHIMPHY_ADDR_CNTL_0_MISC_reserved0_MASK 0xfff00000
-#define BCHP_SHIMPHY_ADDR_CNTL_0_MISC_reserved0_SHIFT 20
-
-/* SHIMPHY_ADDR_CNTL_0 :: MISC :: ASYNC_FIFO_AF_THRESHOLD [19:15] */
-#define BCHP_SHIMPHY_ADDR_CNTL_0_MISC_ASYNC_FIFO_AF_THRESHOLD_MASK 0x000f8000
-#define BCHP_SHIMPHY_ADDR_CNTL_0_MISC_ASYNC_FIFO_AF_THRESHOLD_SHIFT 15
-#define BCHP_SHIMPHY_ADDR_CNTL_0_MISC_ASYNC_FIFO_AF_THRESHOLD_DEFAULT 0x0000000a
-
-/* SHIMPHY_ADDR_CNTL_0 :: MISC :: reserved_for_eco1 [14:12] */
-#define BCHP_SHIMPHY_ADDR_CNTL_0_MISC_reserved_for_eco1_MASK 0x00007000
-#define BCHP_SHIMPHY_ADDR_CNTL_0_MISC_reserved_for_eco1_SHIFT 12
-#define BCHP_SHIMPHY_ADDR_CNTL_0_MISC_reserved_for_eco1_DEFAULT 0x00000000
-
-/* SHIMPHY_ADDR_CNTL_0 :: MISC :: DFI_ERROR_STATUS_CLR [11:11] */
-#define BCHP_SHIMPHY_ADDR_CNTL_0_MISC_DFI_ERROR_STATUS_CLR_MASK 0x00000800
-#define BCHP_SHIMPHY_ADDR_CNTL_0_MISC_DFI_ERROR_STATUS_CLR_SHIFT 11
-#define BCHP_SHIMPHY_ADDR_CNTL_0_MISC_DFI_ERROR_STATUS_CLR_DEFAULT 0x00000000
-
-/* SHIMPHY_ADDR_CNTL_0 :: MISC :: EDC_MONTIOR_STATUS_CLR [10:10] */
-#define BCHP_SHIMPHY_ADDR_CNTL_0_MISC_EDC_MONTIOR_STATUS_CLR_MASK 0x00000400
-#define BCHP_SHIMPHY_ADDR_CNTL_0_MISC_EDC_MONTIOR_STATUS_CLR_SHIFT 10
-#define BCHP_SHIMPHY_ADDR_CNTL_0_MISC_EDC_MONTIOR_STATUS_CLR_DEFAULT 0x00000000
-
-/* SHIMPHY_ADDR_CNTL_0 :: MISC :: VDL_MONITOR_STATUS_CLR [09:09] */
-#define BCHP_SHIMPHY_ADDR_CNTL_0_MISC_VDL_MONITOR_STATUS_CLR_MASK 0x00000200
-#define BCHP_SHIMPHY_ADDR_CNTL_0_MISC_VDL_MONITOR_STATUS_CLR_SHIFT 9
-#define BCHP_SHIMPHY_ADDR_CNTL_0_MISC_VDL_MONITOR_STATUS_CLR_DEFAULT 0x00000000
-
-/* SHIMPHY_ADDR_CNTL_0 :: MISC :: FUNC1 [08:08] */
-#define BCHP_SHIMPHY_ADDR_CNTL_0_MISC_FUNC1_MASK 0x00000100
-#define BCHP_SHIMPHY_ADDR_CNTL_0_MISC_FUNC1_SHIFT 8
-#define BCHP_SHIMPHY_ADDR_CNTL_0_MISC_FUNC1_DEFAULT 0x00000000
-
-/* SHIMPHY_ADDR_CNTL_0 :: MISC :: FUNC0 [07:07] */
-#define BCHP_SHIMPHY_ADDR_CNTL_0_MISC_FUNC0_MASK 0x00000080
-#define BCHP_SHIMPHY_ADDR_CNTL_0_MISC_FUNC0_SHIFT 7
-#define BCHP_SHIMPHY_ADDR_CNTL_0_MISC_FUNC0_DEFAULT 0x00000000
-
-/* SHIMPHY_ADDR_CNTL_0 :: MISC :: C2IO_INIT_RDY_OVR [06:06] */
-#define BCHP_SHIMPHY_ADDR_CNTL_0_MISC_C2IO_INIT_RDY_OVR_MASK 0x00000040
-#define BCHP_SHIMPHY_ADDR_CNTL_0_MISC_C2IO_INIT_RDY_OVR_SHIFT 6
-#define BCHP_SHIMPHY_ADDR_CNTL_0_MISC_C2IO_INIT_RDY_OVR_DEFAULT 0x00000000
-
-/* SHIMPHY_ADDR_CNTL_0 :: MISC :: RD_FIFO_HOLD_CLR [05:05] */
-#define BCHP_SHIMPHY_ADDR_CNTL_0_MISC_RD_FIFO_HOLD_CLR_MASK 0x00000020
-#define BCHP_SHIMPHY_ADDR_CNTL_0_MISC_RD_FIFO_HOLD_CLR_SHIFT 5
-#define BCHP_SHIMPHY_ADDR_CNTL_0_MISC_RD_FIFO_HOLD_CLR_DEFAULT 0x00000000
-
-/* SHIMPHY_ADDR_CNTL_0 :: MISC :: CMD_FIFO_HOLD_CLR [04:04] */
-#define BCHP_SHIMPHY_ADDR_CNTL_0_MISC_CMD_FIFO_HOLD_CLR_MASK 0x00000010
-#define BCHP_SHIMPHY_ADDR_CNTL_0_MISC_CMD_FIFO_HOLD_CLR_SHIFT 4
-#define BCHP_SHIMPHY_ADDR_CNTL_0_MISC_CMD_FIFO_HOLD_CLR_DEFAULT 0x00000000
-
-/* SHIMPHY_ADDR_CNTL_0 :: MISC :: reserved2 [03:01] */
-#define BCHP_SHIMPHY_ADDR_CNTL_0_MISC_reserved2_MASK 0x0000000e
-#define BCHP_SHIMPHY_ADDR_CNTL_0_MISC_reserved2_SHIFT 1
-
-/* SHIMPHY_ADDR_CNTL_0 :: MISC :: DATA_OVERRUN_CLR [00:00] */
-#define BCHP_SHIMPHY_ADDR_CNTL_0_MISC_DATA_OVERRUN_CLR_MASK 0x00000001
-#define BCHP_SHIMPHY_ADDR_CNTL_0_MISC_DATA_OVERRUN_CLR_SHIFT 0
-#define BCHP_SHIMPHY_ADDR_CNTL_0_MISC_DATA_OVERRUN_CLR_DEFAULT 0x00000000
-
-/***************************************************************************
- *DFI_CONTROL - DFI Interface Control Register
- ***************************************************************************/
-/* SHIMPHY_ADDR_CNTL_0 :: DFI_CONTROL :: DFI_ERROR_STATUS_INTR_ENA [31:16] */
-#define BCHP_SHIMPHY_ADDR_CNTL_0_DFI_CONTROL_DFI_ERROR_STATUS_INTR_ENA_MASK 0xffff0000
-#define BCHP_SHIMPHY_ADDR_CNTL_0_DFI_CONTROL_DFI_ERROR_STATUS_INTR_ENA_SHIFT 16
-#define BCHP_SHIMPHY_ADDR_CNTL_0_DFI_CONTROL_DFI_ERROR_STATUS_INTR_ENA_DEFAULT 0x00000000
-
-/* SHIMPHY_ADDR_CNTL_0 :: DFI_CONTROL :: PHY_PLL_RESETB [15:15] */
-#define BCHP_SHIMPHY_ADDR_CNTL_0_DFI_CONTROL_PHY_PLL_RESETB_MASK 0x00008000
-#define BCHP_SHIMPHY_ADDR_CNTL_0_DFI_CONTROL_PHY_PLL_RESETB_SHIFT 15
-#define BCHP_SHIMPHY_ADDR_CNTL_0_DFI_CONTROL_PHY_PLL_RESETB_DEFAULT 0x00000001
-
-/* SHIMPHY_ADDR_CNTL_0 :: DFI_CONTROL :: PHY_ODT [14:14] */
-#define BCHP_SHIMPHY_ADDR_CNTL_0_DFI_CONTROL_PHY_ODT_MASK 0x00004000
-#define BCHP_SHIMPHY_ADDR_CNTL_0_DFI_CONTROL_PHY_ODT_SHIFT 14
-#define BCHP_SHIMPHY_ADDR_CNTL_0_DFI_CONTROL_PHY_ODT_DEFAULT 0x00000001
-
-/* SHIMPHY_ADDR_CNTL_0 :: DFI_CONTROL :: PHY_ISO_PHY_PLL [13:13] */
-#define BCHP_SHIMPHY_ADDR_CNTL_0_DFI_CONTROL_PHY_ISO_PHY_PLL_MASK 0x00002000
-#define BCHP_SHIMPHY_ADDR_CNTL_0_DFI_CONTROL_PHY_ISO_PHY_PLL_SHIFT 13
-#define BCHP_SHIMPHY_ADDR_CNTL_0_DFI_CONTROL_PHY_ISO_PHY_PLL_DEFAULT 0x00000000
-
-/* SHIMPHY_ADDR_CNTL_0 :: DFI_CONTROL :: PHY_PLL_PWRDWN [12:12] */
-#define BCHP_SHIMPHY_ADDR_CNTL_0_DFI_CONTROL_PHY_PLL_PWRDWN_MASK 0x00001000
-#define BCHP_SHIMPHY_ADDR_CNTL_0_DFI_CONTROL_PHY_PLL_PWRDWN_SHIFT 12
-#define BCHP_SHIMPHY_ADDR_CNTL_0_DFI_CONTROL_PHY_PLL_PWRDWN_DEFAULT 0x00000000
-
-/* SHIMPHY_ADDR_CNTL_0 :: DFI_CONTROL :: PHY_PLL_CTRL_RDB_OVERRIDE [11:11] */
-#define BCHP_SHIMPHY_ADDR_CNTL_0_DFI_CONTROL_PHY_PLL_CTRL_RDB_OVERRIDE_MASK 0x00000800
-#define BCHP_SHIMPHY_ADDR_CNTL_0_DFI_CONTROL_PHY_PLL_CTRL_RDB_OVERRIDE_SHIFT 11
-#define BCHP_SHIMPHY_ADDR_CNTL_0_DFI_CONTROL_PHY_PLL_CTRL_RDB_OVERRIDE_DEFAULT 0x00000001
-
-/* SHIMPHY_ADDR_CNTL_0 :: DFI_CONTROL :: PHY_FORCE_CKE_RSTB [10:10] */
-#define BCHP_SHIMPHY_ADDR_CNTL_0_DFI_CONTROL_PHY_FORCE_CKE_RSTB_MASK 0x00000400
-#define BCHP_SHIMPHY_ADDR_CNTL_0_DFI_CONTROL_PHY_FORCE_CKE_RSTB_SHIFT 10
-#define BCHP_SHIMPHY_ADDR_CNTL_0_DFI_CONTROL_PHY_FORCE_CKE_RSTB_DEFAULT 0x00000000
-
-/* SHIMPHY_ADDR_CNTL_0 :: DFI_CONTROL :: TM2_MUX_SEL [09:09] */
-#define BCHP_SHIMPHY_ADDR_CNTL_0_DFI_CONTROL_TM2_MUX_SEL_MASK 0x00000200
-#define BCHP_SHIMPHY_ADDR_CNTL_0_DFI_CONTROL_TM2_MUX_SEL_SHIFT 9
-#define BCHP_SHIMPHY_ADDR_CNTL_0_DFI_CONTROL_TM2_MUX_SEL_DEFAULT 0x00000000
-
-/* SHIMPHY_ADDR_CNTL_0 :: DFI_CONTROL :: PHY_PLL_HOLD_CH [08:08] */
-#define BCHP_SHIMPHY_ADDR_CNTL_0_DFI_CONTROL_PHY_PLL_HOLD_CH_MASK 0x00000100
-#define BCHP_SHIMPHY_ADDR_CNTL_0_DFI_CONTROL_PHY_PLL_HOLD_CH_SHIFT 8
-#define BCHP_SHIMPHY_ADDR_CNTL_0_DFI_CONTROL_PHY_PLL_HOLD_CH_DEFAULT 0x00000000
-
-/* SHIMPHY_ADDR_CNTL_0 :: DFI_CONTROL :: CS1_OVERRIDE_VALUE [07:07] */
-#define BCHP_SHIMPHY_ADDR_CNTL_0_DFI_CONTROL_CS1_OVERRIDE_VALUE_MASK 0x00000080
-#define BCHP_SHIMPHY_ADDR_CNTL_0_DFI_CONTROL_CS1_OVERRIDE_VALUE_SHIFT 7
-#define BCHP_SHIMPHY_ADDR_CNTL_0_DFI_CONTROL_CS1_OVERRIDE_VALUE_DEFAULT 0x00000000
-
-/* SHIMPHY_ADDR_CNTL_0 :: DFI_CONTROL :: CS1_OVERRIDE [06:06] */
-#define BCHP_SHIMPHY_ADDR_CNTL_0_DFI_CONTROL_CS1_OVERRIDE_MASK 0x00000040
-#define BCHP_SHIMPHY_ADDR_CNTL_0_DFI_CONTROL_CS1_OVERRIDE_SHIFT 6
-#define BCHP_SHIMPHY_ADDR_CNTL_0_DFI_CONTROL_CS1_OVERRIDE_DEFAULT 0x00000000
-
-/* SHIMPHY_ADDR_CNTL_0 :: DFI_CONTROL :: CS0_OVERRIDE_VALUE [05:05] */
-#define BCHP_SHIMPHY_ADDR_CNTL_0_DFI_CONTROL_CS0_OVERRIDE_VALUE_MASK 0x00000020
-#define BCHP_SHIMPHY_ADDR_CNTL_0_DFI_CONTROL_CS0_OVERRIDE_VALUE_SHIFT 5
-#define BCHP_SHIMPHY_ADDR_CNTL_0_DFI_CONTROL_CS0_OVERRIDE_VALUE_DEFAULT 0x00000000
-
-/* SHIMPHY_ADDR_CNTL_0 :: DFI_CONTROL :: CS0_OVERRIDE [04:04] */
-#define BCHP_SHIMPHY_ADDR_CNTL_0_DFI_CONTROL_CS0_OVERRIDE_MASK 0x00000010
-#define BCHP_SHIMPHY_ADDR_CNTL_0_DFI_CONTROL_CS0_OVERRIDE_SHIFT 4
-#define BCHP_SHIMPHY_ADDR_CNTL_0_DFI_CONTROL_CS0_OVERRIDE_DEFAULT 0x00000000
-
-/* SHIMPHY_ADDR_CNTL_0 :: DFI_CONTROL :: reserved0 [03:01] */
-#define BCHP_SHIMPHY_ADDR_CNTL_0_DFI_CONTROL_reserved0_MASK 0x0000000e
-#define BCHP_SHIMPHY_ADDR_CNTL_0_DFI_CONTROL_reserved0_SHIFT 1
-
-/* SHIMPHY_ADDR_CNTL_0 :: DFI_CONTROL :: LATCH_FIRST_ERROR [00:00] */
-#define BCHP_SHIMPHY_ADDR_CNTL_0_DFI_CONTROL_LATCH_FIRST_ERROR_MASK 0x00000001
-#define BCHP_SHIMPHY_ADDR_CNTL_0_DFI_CONTROL_LATCH_FIRST_ERROR_SHIFT 0
-#define BCHP_SHIMPHY_ADDR_CNTL_0_DFI_CONTROL_LATCH_FIRST_ERROR_DEFAULT 0x00000001
-
-/***************************************************************************
- *DFI_STATUS - DFI Interface Status Register
- ***************************************************************************/
-/* SHIMPHY_ADDR_CNTL_0 :: DFI_STATUS :: reserved0 [31:19] */
-#define BCHP_SHIMPHY_ADDR_CNTL_0_DFI_STATUS_reserved0_MASK 0xfff80000
-#define BCHP_SHIMPHY_ADDR_CNTL_0_DFI_STATUS_reserved0_SHIFT 19
-
-/* SHIMPHY_ADDR_CNTL_0 :: DFI_STATUS :: PHY_PLL_LOCK [18:18] */
-#define BCHP_SHIMPHY_ADDR_CNTL_0_DFI_STATUS_PHY_PLL_LOCK_MASK 0x00040000
-#define BCHP_SHIMPHY_ADDR_CNTL_0_DFI_STATUS_PHY_PLL_LOCK_SHIFT 18
-#define BCHP_SHIMPHY_ADDR_CNTL_0_DFI_STATUS_PHY_PLL_LOCK_DEFAULT 0x00000000
-
-/* SHIMPHY_ADDR_CNTL_0 :: DFI_STATUS :: PHY_EDC_MONITOR_STATUS [17:17] */
-#define BCHP_SHIMPHY_ADDR_CNTL_0_DFI_STATUS_PHY_EDC_MONITOR_STATUS_MASK 0x00020000
-#define BCHP_SHIMPHY_ADDR_CNTL_0_DFI_STATUS_PHY_EDC_MONITOR_STATUS_SHIFT 17
-#define BCHP_SHIMPHY_ADDR_CNTL_0_DFI_STATUS_PHY_EDC_MONITOR_STATUS_DEFAULT 0x00000000
-
-/* SHIMPHY_ADDR_CNTL_0 :: DFI_STATUS :: PHY_VDL_MONITOR_STATUS [16:16] */
-#define BCHP_SHIMPHY_ADDR_CNTL_0_DFI_STATUS_PHY_VDL_MONITOR_STATUS_MASK 0x00010000
-#define BCHP_SHIMPHY_ADDR_CNTL_0_DFI_STATUS_PHY_VDL_MONITOR_STATUS_SHIFT 16
-#define BCHP_SHIMPHY_ADDR_CNTL_0_DFI_STATUS_PHY_VDL_MONITOR_STATUS_DEFAULT 0x00000000
-
-/* SHIMPHY_ADDR_CNTL_0 :: DFI_STATUS :: reserved1 [15:09] */
-#define BCHP_SHIMPHY_ADDR_CNTL_0_DFI_STATUS_reserved1_MASK 0x0000fe00
-#define BCHP_SHIMPHY_ADDR_CNTL_0_DFI_STATUS_reserved1_SHIFT 9
-
-/* SHIMPHY_ADDR_CNTL_0 :: DFI_STATUS :: ERROR_VALID [08:08] */
-#define BCHP_SHIMPHY_ADDR_CNTL_0_DFI_STATUS_ERROR_VALID_MASK 0x00000100
-#define BCHP_SHIMPHY_ADDR_CNTL_0_DFI_STATUS_ERROR_VALID_SHIFT 8
-#define BCHP_SHIMPHY_ADDR_CNTL_0_DFI_STATUS_ERROR_VALID_DEFAULT 0x00000000
-
-/* SHIMPHY_ADDR_CNTL_0 :: DFI_STATUS :: reserved2 [07:04] */
-#define BCHP_SHIMPHY_ADDR_CNTL_0_DFI_STATUS_reserved2_MASK 0x000000f0
-#define BCHP_SHIMPHY_ADDR_CNTL_0_DFI_STATUS_reserved2_SHIFT 4
-
-/* SHIMPHY_ADDR_CNTL_0 :: DFI_STATUS :: ERROR_INFO [03:00] */
-#define BCHP_SHIMPHY_ADDR_CNTL_0_DFI_STATUS_ERROR_INFO_MASK 0x0000000f
-#define BCHP_SHIMPHY_ADDR_CNTL_0_DFI_STATUS_ERROR_INFO_SHIFT 0
-#define BCHP_SHIMPHY_ADDR_CNTL_0_DFI_STATUS_ERROR_INFO_DEFAULT 0x00000000
-
-/***************************************************************************
- *PHY_LPM_STAT - PHY Power Control Status Register
- ***************************************************************************/
-/* SHIMPHY_ADDR_CNTL_0 :: PHY_LPM_STAT :: reserved0 [31:10] */
-#define BCHP_SHIMPHY_ADDR_CNTL_0_PHY_LPM_STAT_reserved0_MASK 0xfffffc00
-#define BCHP_SHIMPHY_ADDR_CNTL_0_PHY_LPM_STAT_reserved0_SHIFT 10
-
-/* SHIMPHY_ADDR_CNTL_0 :: PHY_LPM_STAT :: PHY_RBUS_IS_IDLE [09:09] */
-#define BCHP_SHIMPHY_ADDR_CNTL_0_PHY_LPM_STAT_PHY_RBUS_IS_IDLE_MASK 0x00000200
-#define BCHP_SHIMPHY_ADDR_CNTL_0_PHY_LPM_STAT_PHY_RBUS_IS_IDLE_SHIFT 9
-#define BCHP_SHIMPHY_ADDR_CNTL_0_PHY_LPM_STAT_PHY_RBUS_IS_IDLE_DEFAULT 0x00000000
-
-/* SHIMPHY_ADDR_CNTL_0 :: PHY_LPM_STAT :: PHY_IS_IDLE [08:08] */
-#define BCHP_SHIMPHY_ADDR_CNTL_0_PHY_LPM_STAT_PHY_IS_IDLE_MASK 0x00000100
-#define BCHP_SHIMPHY_ADDR_CNTL_0_PHY_LPM_STAT_PHY_IS_IDLE_SHIFT 8
-#define BCHP_SHIMPHY_ADDR_CNTL_0_PHY_LPM_STAT_PHY_IS_IDLE_DEFAULT 0x00000000
-
-/* SHIMPHY_ADDR_CNTL_0 :: PHY_LPM_STAT :: reserved1 [07:00] */
-#define BCHP_SHIMPHY_ADDR_CNTL_0_PHY_LPM_STAT_reserved1_MASK 0x000000ff
-#define BCHP_SHIMPHY_ADDR_CNTL_0_PHY_LPM_STAT_reserved1_SHIFT 0
-
-/***************************************************************************
- *ALERT_STATUS - DDR4 Alert Status Register
- ***************************************************************************/
-/* SHIMPHY_ADDR_CNTL_0 :: ALERT_STATUS :: reserved0 [31:02] */
-#define BCHP_SHIMPHY_ADDR_CNTL_0_ALERT_STATUS_reserved0_MASK 0xfffffffc
-#define BCHP_SHIMPHY_ADDR_CNTL_0_ALERT_STATUS_reserved0_SHIFT 2
-
-/* SHIMPHY_ADDR_CNTL_0 :: ALERT_STATUS :: ERROR_CRC_WRITE [01:01] */
-#define BCHP_SHIMPHY_ADDR_CNTL_0_ALERT_STATUS_ERROR_CRC_WRITE_MASK 0x00000002
-#define BCHP_SHIMPHY_ADDR_CNTL_0_ALERT_STATUS_ERROR_CRC_WRITE_SHIFT 1
-#define BCHP_SHIMPHY_ADDR_CNTL_0_ALERT_STATUS_ERROR_CRC_WRITE_DEFAULT 0x00000000
-
-/* SHIMPHY_ADDR_CNTL_0 :: ALERT_STATUS :: ERROR_CMD_PARITY [00:00] */
-#define BCHP_SHIMPHY_ADDR_CNTL_0_ALERT_STATUS_ERROR_CMD_PARITY_MASK 0x00000001
-#define BCHP_SHIMPHY_ADDR_CNTL_0_ALERT_STATUS_ERROR_CMD_PARITY_SHIFT 0
-#define BCHP_SHIMPHY_ADDR_CNTL_0_ALERT_STATUS_ERROR_CMD_PARITY_DEFAULT 0x00000000
-
-/***************************************************************************
- *IDLE_POWER_SAVING - DDR PHY Idle power saving Control register
- ***************************************************************************/
-/* SHIMPHY_ADDR_CNTL_0 :: IDLE_POWER_SAVING :: reserved0 [31:05] */
-#define BCHP_SHIMPHY_ADDR_CNTL_0_IDLE_POWER_SAVING_reserved0_MASK 0xffffffe0
-#define BCHP_SHIMPHY_ADDR_CNTL_0_IDLE_POWER_SAVING_reserved0_SHIFT 5
-
-/* SHIMPHY_ADDR_CNTL_0 :: IDLE_POWER_SAVING :: PhyAddrCntl [04:04] */
-#define BCHP_SHIMPHY_ADDR_CNTL_0_IDLE_POWER_SAVING_PhyAddrCntl_MASK 0x00000010
-#define BCHP_SHIMPHY_ADDR_CNTL_0_IDLE_POWER_SAVING_PhyAddrCntl_SHIFT 4
-#define BCHP_SHIMPHY_ADDR_CNTL_0_IDLE_POWER_SAVING_PhyAddrCntl_DEFAULT 0x00000000
-
-/* SHIMPHY_ADDR_CNTL_0 :: IDLE_POWER_SAVING :: reserved1 [03:00] */
-#define BCHP_SHIMPHY_ADDR_CNTL_0_IDLE_POWER_SAVING_reserved1_MASK 0x0000000f
-#define BCHP_SHIMPHY_ADDR_CNTL_0_IDLE_POWER_SAVING_reserved1_SHIFT 0
-
-/***************************************************************************
- *DDR_PAD_CNTRL - DDR Pad control register
- ***************************************************************************/
-/* SHIMPHY_ADDR_CNTL_0 :: DDR_PAD_CNTRL :: reserved0 [31:10] */
-#define BCHP_SHIMPHY_ADDR_CNTL_0_DDR_PAD_CNTRL_reserved0_MASK 0xfffffc00
-#define BCHP_SHIMPHY_ADDR_CNTL_0_DDR_PAD_CNTRL_reserved0_SHIFT 10
-
-/* SHIMPHY_ADDR_CNTL_0 :: DDR_PAD_CNTRL :: GATE_PLL_S3 [09:09] */
-#define BCHP_SHIMPHY_ADDR_CNTL_0_DDR_PAD_CNTRL_GATE_PLL_S3_MASK 0x00000200
-#define BCHP_SHIMPHY_ADDR_CNTL_0_DDR_PAD_CNTRL_GATE_PLL_S3_SHIFT 9
-#define BCHP_SHIMPHY_ADDR_CNTL_0_DDR_PAD_CNTRL_GATE_PLL_S3_DEFAULT 0x00000000
-
-/* SHIMPHY_ADDR_CNTL_0 :: DDR_PAD_CNTRL :: GATE_PLL_ON_SELFREF [08:08] */
-#define BCHP_SHIMPHY_ADDR_CNTL_0_DDR_PAD_CNTRL_GATE_PLL_ON_SELFREF_MASK 0x00000100
-#define BCHP_SHIMPHY_ADDR_CNTL_0_DDR_PAD_CNTRL_GATE_PLL_ON_SELFREF_SHIFT 8
-#define BCHP_SHIMPHY_ADDR_CNTL_0_DDR_PAD_CNTRL_GATE_PLL_ON_SELFREF_DEFAULT 0x00000000
-
-/* SHIMPHY_ADDR_CNTL_0 :: DDR_PAD_CNTRL :: reserved1 [07:07] */
-#define BCHP_SHIMPHY_ADDR_CNTL_0_DDR_PAD_CNTRL_reserved1_MASK 0x00000080
-#define BCHP_SHIMPHY_ADDR_CNTL_0_DDR_PAD_CNTRL_reserved1_SHIFT 7
-
-/* SHIMPHY_ADDR_CNTL_0 :: DDR_PAD_CNTRL :: IDDQ_MODE_ON_SELFREF [06:06] */
-#define BCHP_SHIMPHY_ADDR_CNTL_0_DDR_PAD_CNTRL_IDDQ_MODE_ON_SELFREF_MASK 0x00000040
-#define BCHP_SHIMPHY_ADDR_CNTL_0_DDR_PAD_CNTRL_IDDQ_MODE_ON_SELFREF_SHIFT 6
-#define BCHP_SHIMPHY_ADDR_CNTL_0_DDR_PAD_CNTRL_IDDQ_MODE_ON_SELFREF_DEFAULT 0x00000000
-
-/* SHIMPHY_ADDR_CNTL_0 :: DDR_PAD_CNTRL :: PHY_IDLE_ENABLE [05:05] */
-#define BCHP_SHIMPHY_ADDR_CNTL_0_DDR_PAD_CNTRL_PHY_IDLE_ENABLE_MASK 0x00000020
-#define BCHP_SHIMPHY_ADDR_CNTL_0_DDR_PAD_CNTRL_PHY_IDLE_ENABLE_SHIFT 5
-#define BCHP_SHIMPHY_ADDR_CNTL_0_DDR_PAD_CNTRL_PHY_IDLE_ENABLE_DEFAULT 0x00000000
-
-/* SHIMPHY_ADDR_CNTL_0 :: DDR_PAD_CNTRL :: reserved2 [04:04] */
-#define BCHP_SHIMPHY_ADDR_CNTL_0_DDR_PAD_CNTRL_reserved2_MASK 0x00000010
-#define BCHP_SHIMPHY_ADDR_CNTL_0_DDR_PAD_CNTRL_reserved2_SHIFT 4
-
-/* SHIMPHY_ADDR_CNTL_0 :: DDR_PAD_CNTRL :: CNTRL [03:00] */
-#define BCHP_SHIMPHY_ADDR_CNTL_0_DDR_PAD_CNTRL_CNTRL_MASK 0x0000000f
-#define BCHP_SHIMPHY_ADDR_CNTL_0_DDR_PAD_CNTRL_CNTRL_SHIFT 0
-#define BCHP_SHIMPHY_ADDR_CNTL_0_DDR_PAD_CNTRL_CNTRL_DEFAULT 0x00000000
-
-/***************************************************************************
- *SHIMPHY_STATUS - SHIMPHY Status Register
- ***************************************************************************/
-/* SHIMPHY_ADDR_CNTL_0 :: SHIMPHY_STATUS :: reserved0 [31:01] */
-#define BCHP_SHIMPHY_ADDR_CNTL_0_SHIMPHY_STATUS_reserved0_MASK 0xfffffffe
-#define BCHP_SHIMPHY_ADDR_CNTL_0_SHIMPHY_STATUS_reserved0_SHIFT 1
-
-/* SHIMPHY_ADDR_CNTL_0 :: SHIMPHY_STATUS :: READY [00:00] */
-#define BCHP_SHIMPHY_ADDR_CNTL_0_SHIMPHY_STATUS_READY_MASK 0x00000001
-#define BCHP_SHIMPHY_ADDR_CNTL_0_SHIMPHY_STATUS_READY_SHIFT 0
-#define BCHP_SHIMPHY_ADDR_CNTL_0_SHIMPHY_STATUS_READY_DEFAULT 0x00000000
-
-/***************************************************************************
- *SPARE0_RW - Spare register
- ***************************************************************************/
-/* SHIMPHY_ADDR_CNTL_0 :: SPARE0_RW :: reserved_for_eco0 [31:00] */
-#define BCHP_SHIMPHY_ADDR_CNTL_0_SPARE0_RW_reserved_for_eco0_MASK 0xffffffff
-#define BCHP_SHIMPHY_ADDR_CNTL_0_SPARE0_RW_reserved_for_eco0_SHIFT 0
-#define BCHP_SHIMPHY_ADDR_CNTL_0_SPARE0_RW_reserved_for_eco0_DEFAULT 0x00000000
-
-/***************************************************************************
- *SPARE1_RW - Spare register
- ***************************************************************************/
-/* SHIMPHY_ADDR_CNTL_0 :: SPARE1_RW :: reserved_for_eco0 [31:00] */
-#define BCHP_SHIMPHY_ADDR_CNTL_0_SPARE1_RW_reserved_for_eco0_MASK 0xffffffff
-#define BCHP_SHIMPHY_ADDR_CNTL_0_SPARE1_RW_reserved_for_eco0_SHIFT 0
-#define BCHP_SHIMPHY_ADDR_CNTL_0_SPARE1_RW_reserved_for_eco0_DEFAULT 0x00000000
-
-/***************************************************************************
- *SPARE0_RO - Spare register
- ***************************************************************************/
-/* SHIMPHY_ADDR_CNTL_0 :: SPARE0_RO :: reserved_for_eco0 [31:00] */
-#define BCHP_SHIMPHY_ADDR_CNTL_0_SPARE0_RO_reserved_for_eco0_MASK 0xffffffff
-#define BCHP_SHIMPHY_ADDR_CNTL_0_SPARE0_RO_reserved_for_eco0_SHIFT 0
-#define BCHP_SHIMPHY_ADDR_CNTL_0_SPARE0_RO_reserved_for_eco0_DEFAULT 0x00000000
-
-/***************************************************************************
- *SPARE1_RO - Spare register
- ***************************************************************************/
-/* SHIMPHY_ADDR_CNTL_0 :: SPARE1_RO :: reserved_for_eco0 [31:00] */
-#define BCHP_SHIMPHY_ADDR_CNTL_0_SPARE1_RO_reserved_for_eco0_MASK 0xffffffff
-#define BCHP_SHIMPHY_ADDR_CNTL_0_SPARE1_RO_reserved_for_eco0_SHIFT 0
-#define BCHP_SHIMPHY_ADDR_CNTL_0_SPARE1_RO_reserved_for_eco0_DEFAULT 0x00000000
-
-/***************************************************************************
- *DDR3_RESET_CNTRL - FORCE_DDR3_RESET Deassert Register
- ***************************************************************************/
-/* SHIMPHY_ADDR_CNTL_0 :: DDR3_RESET_CNTRL :: UNUSED [31:01] */
-#define BCHP_SHIMPHY_ADDR_CNTL_0_DDR3_RESET_CNTRL_UNUSED_MASK 0xfffffffe
-#define BCHP_SHIMPHY_ADDR_CNTL_0_DDR3_RESET_CNTRL_UNUSED_SHIFT 1
-#define BCHP_SHIMPHY_ADDR_CNTL_0_DDR3_RESET_CNTRL_UNUSED_DEFAULT 0x00000000
-
-/* SHIMPHY_ADDR_CNTL_0 :: DDR3_RESET_CNTRL :: FORCE_DDR3_RESET [00:00] */
-#define BCHP_SHIMPHY_ADDR_CNTL_0_DDR3_RESET_CNTRL_FORCE_DDR3_RESET_MASK 0x00000001
-#define BCHP_SHIMPHY_ADDR_CNTL_0_DDR3_RESET_CNTRL_FORCE_DDR3_RESET_SHIFT 0
-#define BCHP_SHIMPHY_ADDR_CNTL_0_DDR3_RESET_CNTRL_FORCE_DDR3_RESET_DEFAULT 0x00000001
-
-/***************************************************************************
- *GDDR5_CRC_CONTROL - GDDR5 CRC CONTROL Register
- ***************************************************************************/
-/* SHIMPHY_ADDR_CNTL_0 :: GDDR5_CRC_CONTROL :: reserved0 [31:01] */
-#define BCHP_SHIMPHY_ADDR_CNTL_0_GDDR5_CRC_CONTROL_reserved0_MASK 0xfffffffe
-#define BCHP_SHIMPHY_ADDR_CNTL_0_GDDR5_CRC_CONTROL_reserved0_SHIFT 1
-
-/* SHIMPHY_ADDR_CNTL_0 :: GDDR5_CRC_CONTROL :: GDDR5_CRC_ENABLE [00:00] */
-#define BCHP_SHIMPHY_ADDR_CNTL_0_GDDR5_CRC_CONTROL_GDDR5_CRC_ENABLE_MASK 0x00000001
-#define BCHP_SHIMPHY_ADDR_CNTL_0_GDDR5_CRC_CONTROL_GDDR5_CRC_ENABLE_SHIFT 0
-#define BCHP_SHIMPHY_ADDR_CNTL_0_GDDR5_CRC_CONTROL_GDDR5_CRC_ENABLE_DEFAULT 0x00000000
-
-/***************************************************************************
- *GDDR5_CLIENT_CRC_EN_31_0 - GDDR5 Client CRC Enable Register
- ***************************************************************************/
-/* SHIMPHY_ADDR_CNTL_0 :: GDDR5_CLIENT_CRC_EN_31_0 :: GDDR5_CLIENT_CRC_EN [31:00] */
-#define BCHP_SHIMPHY_ADDR_CNTL_0_GDDR5_CLIENT_CRC_EN_31_0_GDDR5_CLIENT_CRC_EN_MASK 0xffffffff
-#define BCHP_SHIMPHY_ADDR_CNTL_0_GDDR5_CLIENT_CRC_EN_31_0_GDDR5_CLIENT_CRC_EN_SHIFT 0
-#define BCHP_SHIMPHY_ADDR_CNTL_0_GDDR5_CLIENT_CRC_EN_31_0_GDDR5_CLIENT_CRC_EN_DEFAULT 0x00000000
-
-/***************************************************************************
- *GDDR5_CLIENT_CRC_EN_63_32 - GDDR5 Client CRC Enable Register
- ***************************************************************************/
-/* SHIMPHY_ADDR_CNTL_0 :: GDDR5_CLIENT_CRC_EN_63_32 :: GDDR5_CLIENT_CRC_EN [31:00] */
-#define BCHP_SHIMPHY_ADDR_CNTL_0_GDDR5_CLIENT_CRC_EN_63_32_GDDR5_CLIENT_CRC_EN_MASK 0xffffffff
-#define BCHP_SHIMPHY_ADDR_CNTL_0_GDDR5_CLIENT_CRC_EN_63_32_GDDR5_CLIENT_CRC_EN_SHIFT 0
-#define BCHP_SHIMPHY_ADDR_CNTL_0_GDDR5_CLIENT_CRC_EN_63_32_GDDR5_CLIENT_CRC_EN_DEFAULT 0x00000000
-
-/***************************************************************************
- *GDDR5_CLIENT_CRC_EN_95_64 - GDDR5 Client CRC Enable Register
- ***************************************************************************/
-/* SHIMPHY_ADDR_CNTL_0 :: GDDR5_CLIENT_CRC_EN_95_64 :: GDDR5_CLIENT_CRC_EN [31:00] */
-#define BCHP_SHIMPHY_ADDR_CNTL_0_GDDR5_CLIENT_CRC_EN_95_64_GDDR5_CLIENT_CRC_EN_MASK 0xffffffff
-#define BCHP_SHIMPHY_ADDR_CNTL_0_GDDR5_CLIENT_CRC_EN_95_64_GDDR5_CLIENT_CRC_EN_SHIFT 0
-#define BCHP_SHIMPHY_ADDR_CNTL_0_GDDR5_CLIENT_CRC_EN_95_64_GDDR5_CLIENT_CRC_EN_DEFAULT 0x00000000
-
-/***************************************************************************
- *GDDR5_CLIENT_CRC_EN_127_96 - GDDR5 Client CRC Enable Register
- ***************************************************************************/
-/* SHIMPHY_ADDR_CNTL_0 :: GDDR5_CLIENT_CRC_EN_127_96 :: GDDR5_CLIENT_CRC_EN [31:00] */
-#define BCHP_SHIMPHY_ADDR_CNTL_0_GDDR5_CLIENT_CRC_EN_127_96_GDDR5_CLIENT_CRC_EN_MASK 0xffffffff
-#define BCHP_SHIMPHY_ADDR_CNTL_0_GDDR5_CLIENT_CRC_EN_127_96_GDDR5_CLIENT_CRC_EN_SHIFT 0
-#define BCHP_SHIMPHY_ADDR_CNTL_0_GDDR5_CLIENT_CRC_EN_127_96_GDDR5_CLIENT_CRC_EN_DEFAULT 0x00000000
-
-/***************************************************************************
- *GDDR5_CLIENT_CRC_EN_159_128 - GDDR5 Client CRC Enable Register
- ***************************************************************************/
-/* SHIMPHY_ADDR_CNTL_0 :: GDDR5_CLIENT_CRC_EN_159_128 :: GDDR5_CLIENT_CRC_EN [31:00] */
-#define BCHP_SHIMPHY_ADDR_CNTL_0_GDDR5_CLIENT_CRC_EN_159_128_GDDR5_CLIENT_CRC_EN_MASK 0xffffffff
-#define BCHP_SHIMPHY_ADDR_CNTL_0_GDDR5_CLIENT_CRC_EN_159_128_GDDR5_CLIENT_CRC_EN_SHIFT 0
-#define BCHP_SHIMPHY_ADDR_CNTL_0_GDDR5_CLIENT_CRC_EN_159_128_GDDR5_CLIENT_CRC_EN_DEFAULT 0x00000000
-
-/***************************************************************************
- *GDDR5_CLIENT_CRC_EN_191_160 - GDDR5 Client CRC Enable Register
- ***************************************************************************/
-/* SHIMPHY_ADDR_CNTL_0 :: GDDR5_CLIENT_CRC_EN_191_160 :: GDDR5_CLIENT_CRC_EN [31:00] */
-#define BCHP_SHIMPHY_ADDR_CNTL_0_GDDR5_CLIENT_CRC_EN_191_160_GDDR5_CLIENT_CRC_EN_MASK 0xffffffff
-#define BCHP_SHIMPHY_ADDR_CNTL_0_GDDR5_CLIENT_CRC_EN_191_160_GDDR5_CLIENT_CRC_EN_SHIFT 0
-#define BCHP_SHIMPHY_ADDR_CNTL_0_GDDR5_CLIENT_CRC_EN_191_160_GDDR5_CLIENT_CRC_EN_DEFAULT 0x00000000
-
-/***************************************************************************
- *GDDR5_CLIENT_CRC_EN_223_192 - GDDR5 Client CRC Enable Register
- ***************************************************************************/
-/* SHIMPHY_ADDR_CNTL_0 :: GDDR5_CLIENT_CRC_EN_223_192 :: GDDR5_CLIENT_CRC_EN [31:00] */
-#define BCHP_SHIMPHY_ADDR_CNTL_0_GDDR5_CLIENT_CRC_EN_223_192_GDDR5_CLIENT_CRC_EN_MASK 0xffffffff
-#define BCHP_SHIMPHY_ADDR_CNTL_0_GDDR5_CLIENT_CRC_EN_223_192_GDDR5_CLIENT_CRC_EN_SHIFT 0
-#define BCHP_SHIMPHY_ADDR_CNTL_0_GDDR5_CLIENT_CRC_EN_223_192_GDDR5_CLIENT_CRC_EN_DEFAULT 0x00000000
-
-/***************************************************************************
- *GDDR5_CLIENT_CRC_EN_255_224 - GDDR5 Client CRC Enable Register
- ***************************************************************************/
-/* SHIMPHY_ADDR_CNTL_0 :: GDDR5_CLIENT_CRC_EN_255_224 :: GDDR5_CLIENT_CRC_EN [31:00] */
-#define BCHP_SHIMPHY_ADDR_CNTL_0_GDDR5_CLIENT_CRC_EN_255_224_GDDR5_CLIENT_CRC_EN_MASK 0xffffffff
-#define BCHP_SHIMPHY_ADDR_CNTL_0_GDDR5_CLIENT_CRC_EN_255_224_GDDR5_CLIENT_CRC_EN_SHIFT 0
-#define BCHP_SHIMPHY_ADDR_CNTL_0_GDDR5_CLIENT_CRC_EN_255_224_GDDR5_CLIENT_CRC_EN_DEFAULT 0x00000000
-
-/***************************************************************************
- *GDDR5_CRC_WRITE_ERROR_CNT - GDDR5 Write CRC Error Count
- ***************************************************************************/
-/* SHIMPHY_ADDR_CNTL_0 :: GDDR5_CRC_WRITE_ERROR_CNT :: GDDR5_CRC_ERROR_CNT [31:00] */
-#define BCHP_SHIMPHY_ADDR_CNTL_0_GDDR5_CRC_WRITE_ERROR_CNT_GDDR5_CRC_ERROR_CNT_MASK 0xffffffff
-#define BCHP_SHIMPHY_ADDR_CNTL_0_GDDR5_CRC_WRITE_ERROR_CNT_GDDR5_CRC_ERROR_CNT_SHIFT 0
-#define BCHP_SHIMPHY_ADDR_CNTL_0_GDDR5_CRC_WRITE_ERROR_CNT_GDDR5_CRC_ERROR_CNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *GDDR5_CRC_READ_ERROR_CNT - GDDR5 Read CRC Error Count
- ***************************************************************************/
-/* SHIMPHY_ADDR_CNTL_0 :: GDDR5_CRC_READ_ERROR_CNT :: GDDR5_CRC_ERROR_CNT [31:00] */
-#define BCHP_SHIMPHY_ADDR_CNTL_0_GDDR5_CRC_READ_ERROR_CNT_GDDR5_CRC_ERROR_CNT_MASK 0xffffffff
-#define BCHP_SHIMPHY_ADDR_CNTL_0_GDDR5_CRC_READ_ERROR_CNT_GDDR5_CRC_ERROR_CNT_SHIFT 0
-#define BCHP_SHIMPHY_ADDR_CNTL_0_GDDR5_CRC_READ_ERROR_CNT_GDDR5_CRC_ERROR_CNT_DEFAULT 0x00000000
-
-#endif /* #ifndef BCHP_SHIMPHY_ADDR_CNTL_0_H__ */
-
-/* End of File */
diff --git a/include/linux/brcmstb/7366b0/bchp_sun_top_ctrl.h b/include/linux/brcmstb/7366b0/bchp_sun_top_ctrl.h
deleted file mode 100644
index e9cf1a8..0000000
--- a/include/linux/brcmstb/7366b0/bchp_sun_top_ctrl.h
+++ /dev/null
@@ -1,8932 +0,0 @@
-/***************************************************************************
- * Copyright (c) 1999-2014, Broadcom Corporation
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
- *
- * Module Description:
- * DO NOT EDIT THIS FILE DIRECTLY
- *
- * This module was generated magically with RDB from a source description
- * file. You must edit the source file for changes to be made to this file.
- *
- *
- * Date: Generated on Wed Jul 2 03:12:38 2014
- * Full Compile MD5 Checksum 7dc2787604a7d66ecd88cf44bdf8b9f2
- * (minus title and desc)
- * MD5 Checksum fac21eb3a5c0bbaa870b50b1cab81ef9
- *
- * Compiled with: RDB Utility combo_header.pl
- * RDB Parser 3.0
- * unknown unknown
- * Perl Interpreter 5.008008
- * Operating System linux
- *
- * Revision History:
- *
- * $brcm_Log: $
- *
- ***************************************************************************/
-
-#ifndef BCHP_SUN_TOP_CTRL_H__
-#define BCHP_SUN_TOP_CTRL_H__
-
-/***************************************************************************
- *SUN_TOP_CTRL - Top Control registers
- ***************************************************************************/
-#define BCHP_SUN_TOP_CTRL_CHIP_FAMILY_ID 0x00404000 /* Chip family ID */
-#define BCHP_SUN_TOP_CTRL_PRODUCT_ID 0x00404004 /* Product Revision ID */
-#define BCHP_SUN_TOP_CTRL_BSP_FEATURE_TABLE_ADDR 0x00404008 /* BSP feature table address */
-#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0 0x0040401c /* Strapping values */
-#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_1 0x00404020 /* Strapping values */
-#define BCHP_SUN_TOP_CTRL_BOND_STATUS 0x00404024 /* Bond option value register */
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0 0x00404028 /* OTP option test register */
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1 0x0040402c /* OTP option test register */
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0 0x00404030 /* OTP option status register */
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1 0x00404034 /* OTP option status register */
-#define BCHP_SUN_TOP_CTRL_SEMAPHORE_0 0x00404038 /* Semaphore channel 0 */
-#define BCHP_SUN_TOP_CTRL_SEMAPHORE_1 0x0040403c /* Semaphore channel 1 */
-#define BCHP_SUN_TOP_CTRL_SEMAPHORE_2 0x00404040 /* Semaphore channel 2 */
-#define BCHP_SUN_TOP_CTRL_SEMAPHORE_3 0x00404044 /* Semaphore channel 3 */
-#define BCHP_SUN_TOP_CTRL_SEMAPHORE_4 0x00404048 /* Semaphore channel 4 */
-#define BCHP_SUN_TOP_CTRL_SEMAPHORE_5 0x0040404c /* Semaphore channel 5 */
-#define BCHP_SUN_TOP_CTRL_SEMAPHORE_6 0x00404050 /* Semaphore channel 6 */
-#define BCHP_SUN_TOP_CTRL_SEMAPHORE_7 0x00404054 /* Semaphore channel 7 */
-#define BCHP_SUN_TOP_CTRL_SEMAPHORE_8 0x00404058 /* Semaphore channel 8 */
-#define BCHP_SUN_TOP_CTRL_SEMAPHORE_9 0x0040405c /* Semaphore channel 9 */
-#define BCHP_SUN_TOP_CTRL_SEMAPHORE_10 0x00404060 /* Semaphore channel 10 */
-#define BCHP_SUN_TOP_CTRL_SEMAPHORE_11 0x00404064 /* Semaphore channel 11 */
-#define BCHP_SUN_TOP_CTRL_SEMAPHORE_12 0x00404068 /* Semaphore channel 12 */
-#define BCHP_SUN_TOP_CTRL_SEMAPHORE_13 0x0040406c /* Semaphore channel 13 */
-#define BCHP_SUN_TOP_CTRL_SEMAPHORE_14 0x00404070 /* Semaphore channel 14 */
-#define BCHP_SUN_TOP_CTRL_SEMAPHORE_15 0x00404074 /* Semaphore channel 15 */
-#define BCHP_SUN_TOP_CTRL_GEN_WATCHDOG_0 0x00404078 /* General watchdog timer 0 */
-#define BCHP_SUN_TOP_CTRL_GEN_WATCHDOG_1 0x0040407c /* General watchdog timer 1 */
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0 0x00404080 /* General control register 0 */
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1 0x00404084 /* General control register 1 */
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_2 0x00404088 /* General control register 2 */
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_3 0x0040408c /* General control register 3 */
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_4 0x00404090 /* General control register 4 */
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_5 0x00404094 /* General control register 5 */
-#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0 0x00404098 /* General status register 0 */
-#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_1 0x0040409c /* General status register 1 */
-#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_2 0x004040a0 /* General status register 2 */
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0 0x004040a4 /* General control register without scan 0 */
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1 0x004040a8 /* General control register without scan 1 */
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2 0x004040ac /* General control register without scan 2 */
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3 0x004040b0 /* General control register without scan 3 */
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_4 0x004040b4 /* General control register without scan 4 */
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5 0x004040b8 /* General control register without scan 5 */
-#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_3 0x004040bc /* General status register 3 */
-#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_4 0x004040c0 /* General status register 4 */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0 0x00404100 /* Pinmux control register 0 */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1 0x00404104 /* Pinmux control register 1 */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2 0x00404108 /* Pinmux control register 2 */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3 0x0040410c /* Pinmux control register 3 */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4 0x00404110 /* Pinmux control register 4 */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5 0x00404114 /* Pinmux control register 5 */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6 0x00404118 /* Pinmux control register 6 */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7 0x0040411c /* Pinmux control register 7 */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8 0x00404120 /* Pinmux control register 8 */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9 0x00404124 /* Pinmux control register 9 */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10 0x00404128 /* Pinmux control register 10 */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11 0x0040412c /* Pinmux control register 11 */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12 0x00404130 /* Pinmux control register 12 */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13 0x00404134 /* Pinmux control register 13 */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14 0x00404138 /* Pinmux control register 14 */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15 0x0040413c /* Pinmux control register 15 */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16 0x00404140 /* Pinmux control register 16 */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17 0x00404144 /* Pinmux control register 17 */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18 0x00404148 /* Pinmux control register 18 */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_19 0x0040414c /* Pinmux control register 19 */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_20 0x00404150 /* Pinmux control register 20 */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_21 0x00404154 /* Pinmux control register 21 */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0 0x00404158 /* Pad pull-up/pull-down control register 0 */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1 0x0040415c /* Pad pull-up/pull-down control register 1 */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2 0x00404160 /* Pad pull-up/pull-down control register 2 */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3 0x00404164 /* Pad pull-up/pull-down control register 3 */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4 0x00404168 /* Pad pull-up/pull-down control register 4 */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5 0x0040416c /* Pad pull-up/pull-down control register 5 */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6 0x00404170 /* Pad pull-up/pull-down control register 6 */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7 0x00404174 /* Pad pull-up/pull-down control register 7 */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8 0x00404178 /* Pad pull-up/pull-down control register 8 */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9 0x0040417c /* Pad pull-up/pull-down control register 9 */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10 0x00404180 /* Pad pull-up/pull-down control register 10 */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11 0x00404184 /* Pad pull-up/pull-down control register 11 */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_12 0x00404188 /* Pad pull-up/pull-down control register 12 */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_13 0x0040418c /* Pad pull-up/pull-down control register 13 */
-#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0 0x00404190 /* Bypass clock unselect register 0 */
-#define BCHP_SUN_TOP_CTRL_RESET_CTRL 0x00404300 /* Reset control */
-#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE 0x00404304 /* Reset source enable */
-#define BCHP_SUN_TOP_CTRL_SW_MASTER_RESET 0x00404308 /* Software master reset */
-#define BCHP_SUN_TOP_CTRL_HW_RESET_EXTENSION 0x0040430c /* Hardware reset extension */
-#define BCHP_SUN_TOP_CTRL_RESET_MONITOR 0x00404310 /* Reset Monitor */
-#define BCHP_SUN_TOP_CTRL_RESET_HISTORY 0x00404314 /* Reset history */
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET 0x00404318 /* Software init 0 set */
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR 0x0040431c /* Software init 0 clear */
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS 0x00404320 /* Software init 0 status */
-#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR 0x00404324 /* Security software init 0 monitor */
-#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR 0x00404328 /* Test configuration software init 0 monitor */
-#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR 0x0040432c /* Final software init 0 monitor */
-#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET 0x00404330 /* Software init 1 set */
-#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR 0x00404334 /* Software init 1 clear */
-#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS 0x00404338 /* Software init 1 status */
-#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR 0x0040433c /* Security software init 1 monitor */
-#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR 0x00404340 /* Test configuration software init 1 monitor */
-#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR 0x00404344 /* Final software init 1 monitor */
-#define BCHP_SUN_TOP_CTRL_SW_INIT_ONE_SHOT_TRIGGER 0x00404348 /* Software init one-shot trigger */
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_WIDTH 0x0040434c /* One-shot 0 width */
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK 0x00404350 /* One-shot 0 mask for software init 0 */
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK 0x00404354 /* One-shot 0 mask for software init 1 */
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_WIDTH 0x00404358 /* One-shot 1 width */
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK 0x0040435c /* One-shot 1 mask for software init 0 */
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK 0x00404360 /* One-shot 1 mask for software init 1 */
-#define BCHP_SUN_TOP_CTRL_UNCLEARED_SCRATCH 0x00404364 /* Scratch register */
-#define BCHP_SUN_TOP_CTRL_SPARE_CTRL 0x00404368 /* Spare control bits reserved for future use */
-#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL 0x00404380 /* Test port control */
-#define BCHP_SUN_TOP_CTRL_TEST_PORT_OUT_PEEK 0x00404384 /* Testport peek register */
-#define BCHP_SUN_TOP_CTRL_TEST_PORT_OUT_POKE 0x00404388 /* Testport poke register */
-#define BCHP_SUN_TOP_CTRL_TEST_PORT_IN_PEEK 0x0040438c /* Testport peek register */
-#define BCHP_SUN_TOP_CTRL_TEST_PORT_IN_POKE 0x00404390 /* Testport poke register */
-#define BCHP_SUN_TOP_CTRL_EJTAG_INPUT_EN 0x00404394 /* EJTAG input bus enables */
-#define BCHP_SUN_TOP_CTRL_EJTAG_OUTPUT_SEL 0x00404398 /* EJTAG output select */
-#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL 0x004043a0 /* VTRAP Control */
-#define BCHP_SUN_TOP_CTRL_VTRAP_STATUS 0x004043a4 /* VTRAP Status */
-#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0 0x004043a8 /* UART Router select 0 */
-#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1 0x004043ac /* UART Router select 1 */
-#define BCHP_SUN_TOP_CTRL_SSP_CONFIG 0x00404400 /* Serial Slave Port configuration register */
-#define BCHP_SUN_TOP_CTRL_SERS_REV 0x00404420 /* SERS Revision Register */
-#define BCHP_SUN_TOP_CTRL_SERS_CFG 0x00404424 /* SERS Configuration Register */
-#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL 0x00404514 /* Block select for RO testmode */
-#define BCHP_SUN_TOP_CTRL_TEST_CONFIGURATION 0x00404518 /* Test configuration */
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_2 0x0040451c /* OTP option test register */
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_2 0x00404520 /* OTP option status register */
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_6 0x00404528 /* General control register 6 */
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_7 0x0040452c /* General control register 7 */
-
-/***************************************************************************
- *CHIP_FAMILY_ID - Chip family ID
- ***************************************************************************/
-/* SUN_TOP_CTRL :: CHIP_FAMILY_ID :: chip_family_id [31:00] */
-#define BCHP_SUN_TOP_CTRL_CHIP_FAMILY_ID_chip_family_id_MASK 0xffffffff
-#define BCHP_SUN_TOP_CTRL_CHIP_FAMILY_ID_chip_family_id_SHIFT 0
-#define BCHP_SUN_TOP_CTRL_CHIP_FAMILY_ID_chip_family_id_DEFAULT 0x73660010
-
-/***************************************************************************
- *PRODUCT_ID - Product Revision ID
- ***************************************************************************/
-/* SUN_TOP_CTRL :: PRODUCT_ID :: product_id [31:00] */
-#define BCHP_SUN_TOP_CTRL_PRODUCT_ID_product_id_MASK 0xffffffff
-#define BCHP_SUN_TOP_CTRL_PRODUCT_ID_product_id_SHIFT 0
-#define BCHP_SUN_TOP_CTRL_PRODUCT_ID_product_id_DEFAULT 0x73660010
-
-/***************************************************************************
- *BSP_FEATURE_TABLE_ADDR - BSP feature table address
- ***************************************************************************/
-/* SUN_TOP_CTRL :: BSP_FEATURE_TABLE_ADDR :: bsp_feature_table_addr [31:00] */
-#define BCHP_SUN_TOP_CTRL_BSP_FEATURE_TABLE_ADDR_bsp_feature_table_addr_MASK 0xffffffff
-#define BCHP_SUN_TOP_CTRL_BSP_FEATURE_TABLE_ADDR_bsp_feature_table_addr_SHIFT 0
-#define BCHP_SUN_TOP_CTRL_BSP_FEATURE_TABLE_ADDR_bsp_feature_table_addr_DEFAULT 0x00000000
-
-/***************************************************************************
- *STRAP_VALUE_0 - Strapping values
- ***************************************************************************/
-/* SUN_TOP_CTRL :: STRAP_VALUE_0 :: reserved0 [31:10] */
-#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0_reserved0_MASK 0xfffffc00
-#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0_reserved0_SHIFT 10
-
-/* SUN_TOP_CTRL :: STRAP_VALUE_0 :: strap_system_big_endian [09:09] */
-#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0_strap_system_big_endian_MASK 0x00000200
-#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0_strap_system_big_endian_SHIFT 9
-#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0_strap_system_big_endian_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: STRAP_VALUE_0 :: strap_boot_shape [08:04] */
-#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0_strap_boot_shape_MASK 0x000001f0
-#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0_strap_boot_shape_SHIFT 4
-#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0_strap_boot_shape_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: STRAP_VALUE_0 :: strap_pcie_rc_ep [03:02] */
-#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0_strap_pcie_rc_ep_MASK 0x0000000c
-#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0_strap_pcie_rc_ep_SHIFT 2
-#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0_strap_pcie_rc_ep_DEFAULT 0x00000001
-
-/* SUN_TOP_CTRL :: STRAP_VALUE_0 :: strap_pcie_sata_combo_sel [01:01] */
-#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0_strap_pcie_sata_combo_sel_MASK 0x00000002
-#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0_strap_pcie_sata_combo_sel_SHIFT 1
-#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0_strap_pcie_sata_combo_sel_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: STRAP_VALUE_0 :: strap_reset_outb_def_val [00:00] */
-#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0_strap_reset_outb_def_val_MASK 0x00000001
-#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0_strap_reset_outb_def_val_SHIFT 0
-#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0_strap_reset_outb_def_val_DEFAULT 0x00000000
-
-/***************************************************************************
- *STRAP_VALUE_1 - Strapping values
- ***************************************************************************/
-/* SUN_TOP_CTRL :: STRAP_VALUE_1 :: reserved0 [31:05] */
-#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_1_reserved0_MASK 0xffffffe0
-#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_1_reserved0_SHIFT 5
-
-/* SUN_TOP_CTRL :: STRAP_VALUE_1 :: strap_hipass_xtal [04:04] */
-#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_1_strap_hipass_xtal_MASK 0x00000010
-#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_1_strap_hipass_xtal_SHIFT 4
-#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_1_strap_hipass_xtal_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: STRAP_VALUE_1 :: strap_xcore_bias [03:00] */
-#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_1_strap_xcore_bias_MASK 0x0000000f
-#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_1_strap_xcore_bias_SHIFT 0
-#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_1_strap_xcore_bias_DEFAULT 0x00000004
-
-/***************************************************************************
- *BOND_STATUS - Bond option value register
- ***************************************************************************/
-/* SUN_TOP_CTRL :: BOND_STATUS :: reserved0 [31:01] */
-#define BCHP_SUN_TOP_CTRL_BOND_STATUS_reserved0_MASK 0xfffffffe
-#define BCHP_SUN_TOP_CTRL_BOND_STATUS_reserved0_SHIFT 1
-
-/* SUN_TOP_CTRL :: BOND_STATUS :: bond_reserved [00:00] */
-#define BCHP_SUN_TOP_CTRL_BOND_STATUS_bond_reserved_MASK 0x00000001
-#define BCHP_SUN_TOP_CTRL_BOND_STATUS_bond_reserved_SHIFT 0
-
-/***************************************************************************
- *OTP_OPTION_TEST_0 - OTP option test register
- ***************************************************************************/
-/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_moca_disable [31:31] */
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_moca_disable_MASK 0x80000000
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_moca_disable_SHIFT 31
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_moca_disable_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_pcie0_disable [30:30] */
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_pcie0_disable_MASK 0x40000000
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_pcie0_disable_SHIFT 30
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_pcie0_disable_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_av_output_disable [29:29] */
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_av_output_disable_MASK 0x20000000
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_av_output_disable_SHIFT 29
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_av_output_disable_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_vc4_disable [28:28] */
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_vc4_disable_MASK 0x10000000
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_vc4_disable_SHIFT 28
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_vc4_disable_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_4kx2k_disable [27:27] */
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_4kx2k_disable_MASK 0x08000000
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_4kx2k_disable_SHIFT 27
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_4kx2k_disable_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_sata_disable [26:26] */
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_sata_disable_MASK 0x04000000
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_sata_disable_SHIFT 26
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_sata_disable_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_macrovision_disable [25:25] */
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_macrovision_disable_MASK 0x02000000
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_macrovision_disable_SHIFT 25
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_macrovision_disable_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_hdcp_disable [24:24] */
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_hdcp_disable_MASK 0x01000000
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_hdcp_disable_SHIFT 24
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_hdcp_disable_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_hdmi_pass_thru_disable [23:23] */
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_hdmi_pass_thru_disable_MASK 0x00800000
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_hdmi_pass_thru_disable_SHIFT 23
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_hdmi_pass_thru_disable_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_hdmi_rx_disable [22:22] */
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_hdmi_rx_disable_MASK 0x00400000
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_hdmi_rx_disable_SHIFT 22
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_hdmi_rx_disable_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_rv9_disable [21:21] */
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_rv9_disable_MASK 0x00200000
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_rv9_disable_SHIFT 21
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_rv9_disable_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: reserved0 [20:16] */
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_reserved0_MASK 0x001f0000
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_reserved0_SHIFT 16
-
-/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_memsys_1_disable [15:15] */
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_memsys_1_disable_MASK 0x00008000
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_memsys_1_disable_SHIFT 15
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_memsys_1_disable_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: reserved1 [14:13] */
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_reserved1_MASK 0x00006000
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_reserved1_SHIFT 13
-
-/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_hvd0_disable [12:12] */
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_hvd0_disable_MASK 0x00001000
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_hvd0_disable_SHIFT 12
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_hvd0_disable_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: reserved2 [11:11] */
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_reserved2_MASK 0x00000800
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_reserved2_SHIFT 11
-
-/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_vice2_0_disable [10:10] */
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_vice2_0_disable_MASK 0x00000400
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_vice2_0_disable_SHIFT 10
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_vice2_0_disable_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_avs_disable [09:09] */
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_avs_disable_MASK 0x00000200
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_avs_disable_SHIFT 9
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_avs_disable_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_audio_spdif_disable [08:08] */
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_audio_spdif_disable_MASK 0x00000100
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_audio_spdif_disable_SHIFT 8
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_audio_spdif_disable_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_en_testport [07:07] */
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_en_testport_MASK 0x00000080
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_en_testport_SHIFT 7
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_en_testport_DEFAULT 0x00000001
-
-/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_en_cr [06:05] */
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_en_cr_MASK 0x00000060
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_en_cr_SHIFT 5
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_en_cr_DEFAULT 0x00000003
-
-/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_rave_verify_enable [04:04] */
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_rave_verify_enable_MASK 0x00000010
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_rave_verify_enable_SHIFT 4
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_rave_verify_enable_DEFAULT 0x00000001
-
-/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_bsp_spares [03:00] */
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_bsp_spares_MASK 0x0000000f
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_bsp_spares_SHIFT 0
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_bsp_spares_DEFAULT 0x00000000
-
-/***************************************************************************
- *OTP_OPTION_TEST_1 - OTP option test register
- ***************************************************************************/
-/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_capsense_disable [31:31] */
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_capsense_disable_MASK 0x80000000
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_capsense_disable_SHIFT 31
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_capsense_disable_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_moca2_disable [30:30] */
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_moca2_disable_MASK 0x40000000
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_moca2_disable_SHIFT 30
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_moca2_disable_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_directv_disable [29:29] */
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_directv_disable_MASK 0x20000000
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_directv_disable_SHIFT 29
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_directv_disable_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_ldpc_disable [28:21] */
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_ldpc_disable_MASK 0x1fe00000
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_ldpc_disable_SHIFT 21
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_ldpc_disable_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_cpus_to_use [20:20] */
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_cpus_to_use_MASK 0x00100000
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_cpus_to_use_SHIFT 20
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_cpus_to_use_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_tfec_disable [19:19] */
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_tfec_disable_MASK 0x00080000
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_tfec_disable_SHIFT 19
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_tfec_disable_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_5 [18:18] */
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_5_MASK 0x00040000
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_5_SHIFT 18
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_5_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_4 [17:17] */
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_4_MASK 0x00020000
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_4_SHIFT 17
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_4_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_3 [16:16] */
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_3_MASK 0x00010000
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_3_SHIFT 16
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_3_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_2 [15:15] */
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_2_MASK 0x00008000
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_2_SHIFT 15
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_2_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_1 [14:14] */
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_1_MASK 0x00004000
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_1_SHIFT 14
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_1_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_usb30_disable [13:13] */
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_usb30_disable_MASK 0x00002000
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_usb30_disable_SHIFT 13
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_usb30_disable_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_audio_1_disable [12:12] */
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_audio_1_disable_MASK 0x00001000
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_audio_1_disable_SHIFT 12
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_audio_1_disable_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_audio_0_disable [11:11] */
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_audio_0_disable_MASK 0x00000800
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_audio_0_disable_SHIFT 11
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_audio_0_disable_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_tuner_disable [10:08] */
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_tuner_disable_MASK 0x00000700
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_tuner_disable_SHIFT 8
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_tuner_disable_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_hdcp22_disable [07:07] */
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_hdcp22_disable_MASK 0x00000080
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_hdcp22_disable_SHIFT 7
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_hdcp22_disable_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_pcie1_disable [06:06] */
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_pcie1_disable_MASK 0x00000040
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_pcie1_disable_SHIFT 6
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_pcie1_disable_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_rfm_disable [05:05] */
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_rfm_disable_MASK 0x00000020
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_rfm_disable_SHIFT 5
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_rfm_disable_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_usb3_disable [04:04] */
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_usb3_disable_MASK 0x00000010
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_usb3_disable_SHIFT 4
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_usb3_disable_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_usb2_disable [03:03] */
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_usb2_disable_MASK 0x00000008
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_usb2_disable_SHIFT 3
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_usb2_disable_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_usb1_disable [02:02] */
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_usb1_disable_MASK 0x00000004
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_usb1_disable_SHIFT 2
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_usb1_disable_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_usb0_disable [01:01] */
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_usb0_disable_MASK 0x00000002
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_usb0_disable_SHIFT 1
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_usb0_disable_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_hdmi_tx1_disable [00:00] */
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_hdmi_tx1_disable_MASK 0x00000001
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_hdmi_tx1_disable_SHIFT 0
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_hdmi_tx1_disable_DEFAULT 0x00000000
-
-/***************************************************************************
- *OTP_OPTION_STATUS_0 - OTP option status register
- ***************************************************************************/
-/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_moca_disable [31:31] */
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_moca_disable_MASK 0x80000000
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_moca_disable_SHIFT 31
-
-/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_pcie0_disable [30:30] */
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_pcie0_disable_MASK 0x40000000
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_pcie0_disable_SHIFT 30
-
-/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_av_output_disable [29:29] */
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_av_output_disable_MASK 0x20000000
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_av_output_disable_SHIFT 29
-
-/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_vc4_disable [28:28] */
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_vc4_disable_MASK 0x10000000
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_vc4_disable_SHIFT 28
-
-/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_4kx2k_disable [27:27] */
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_4kx2k_disable_MASK 0x08000000
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_4kx2k_disable_SHIFT 27
-
-/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_sata_disable [26:26] */
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_sata_disable_MASK 0x04000000
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_sata_disable_SHIFT 26
-
-/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_macrovision_disable [25:25] */
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_macrovision_disable_MASK 0x02000000
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_macrovision_disable_SHIFT 25
-
-/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_hdcp_disable [24:24] */
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_hdcp_disable_MASK 0x01000000
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_hdcp_disable_SHIFT 24
-
-/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_hdmi_pass_thru_disable [23:23] */
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_hdmi_pass_thru_disable_MASK 0x00800000
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_hdmi_pass_thru_disable_SHIFT 23
-
-/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_hdmi_rx_disable [22:22] */
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_hdmi_rx_disable_MASK 0x00400000
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_hdmi_rx_disable_SHIFT 22
-
-/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_rv9_disable [21:21] */
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_rv9_disable_MASK 0x00200000
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_rv9_disable_SHIFT 21
-
-/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: reserved0 [20:16] */
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_reserved0_MASK 0x001f0000
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_reserved0_SHIFT 16
-
-/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_memsys_1_disable [15:15] */
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_memsys_1_disable_MASK 0x00008000
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_memsys_1_disable_SHIFT 15
-
-/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: reserved1 [14:13] */
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_reserved1_MASK 0x00006000
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_reserved1_SHIFT 13
-
-/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_hvd0_disable [12:12] */
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_hvd0_disable_MASK 0x00001000
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_hvd0_disable_SHIFT 12
-
-/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: reserved2 [11:11] */
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_reserved2_MASK 0x00000800
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_reserved2_SHIFT 11
-
-/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_vice2_0_disable [10:10] */
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_vice2_0_disable_MASK 0x00000400
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_vice2_0_disable_SHIFT 10
-
-/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_avs_disable [09:09] */
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_avs_disable_MASK 0x00000200
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_avs_disable_SHIFT 9
-
-/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_audio_spdif_disable [08:08] */
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_audio_spdif_disable_MASK 0x00000100
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_audio_spdif_disable_SHIFT 8
-
-/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_en_testport [07:07] */
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_en_testport_MASK 0x00000080
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_en_testport_SHIFT 7
-
-/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_en_cr [06:05] */
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_en_cr_MASK 0x00000060
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_en_cr_SHIFT 5
-
-/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_rave_verify_enable [04:04] */
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_rave_verify_enable_MASK 0x00000010
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_rave_verify_enable_SHIFT 4
-
-/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_bsp_spares [03:00] */
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_bsp_spares_MASK 0x0000000f
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_bsp_spares_SHIFT 0
-
-/***************************************************************************
- *OTP_OPTION_STATUS_1 - OTP option status register
- ***************************************************************************/
-/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_capsense_disable [31:31] */
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_capsense_disable_MASK 0x80000000
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_capsense_disable_SHIFT 31
-
-/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_moca2_disable [30:30] */
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_moca2_disable_MASK 0x40000000
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_moca2_disable_SHIFT 30
-
-/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_directv_disable [29:29] */
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_directv_disable_MASK 0x20000000
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_directv_disable_SHIFT 29
-
-/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_ldpc_disable [28:21] */
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_ldpc_disable_MASK 0x1fe00000
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_ldpc_disable_SHIFT 21
-
-/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_cpus_to_use [20:20] */
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_cpus_to_use_MASK 0x00100000
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_cpus_to_use_SHIFT 20
-
-/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_tfec_disable [19:19] */
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_tfec_disable_MASK 0x00080000
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_tfec_disable_SHIFT 19
-
-/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_5 [18:18] */
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_5_MASK 0x00040000
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_5_SHIFT 18
-
-/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_4 [17:17] */
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_4_MASK 0x00020000
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_4_SHIFT 17
-
-/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_3 [16:16] */
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_3_MASK 0x00010000
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_3_SHIFT 16
-
-/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_2 [15:15] */
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_2_MASK 0x00008000
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_2_SHIFT 15
-
-/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_1 [14:14] */
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_1_MASK 0x00004000
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_1_SHIFT 14
-
-/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_usb30_disable [13:13] */
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_usb30_disable_MASK 0x00002000
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_usb30_disable_SHIFT 13
-
-/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_audio_1_disable [12:12] */
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_audio_1_disable_MASK 0x00001000
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_audio_1_disable_SHIFT 12
-
-/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_audio_0_disable [11:11] */
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_audio_0_disable_MASK 0x00000800
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_audio_0_disable_SHIFT 11
-
-/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_tuner_disable [10:08] */
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_tuner_disable_MASK 0x00000700
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_tuner_disable_SHIFT 8
-
-/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_hdcp22_disable [07:07] */
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_hdcp22_disable_MASK 0x00000080
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_hdcp22_disable_SHIFT 7
-
-/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_pcie1_disable [06:06] */
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_pcie1_disable_MASK 0x00000040
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_pcie1_disable_SHIFT 6
-
-/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_rfm_disable [05:05] */
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_rfm_disable_MASK 0x00000020
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_rfm_disable_SHIFT 5
-
-/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_usb3_disable [04:04] */
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_usb3_disable_MASK 0x00000010
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_usb3_disable_SHIFT 4
-
-/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_usb2_disable [03:03] */
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_usb2_disable_MASK 0x00000008
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_usb2_disable_SHIFT 3
-
-/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_usb1_disable [02:02] */
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_usb1_disable_MASK 0x00000004
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_usb1_disable_SHIFT 2
-
-/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_usb0_disable [01:01] */
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_usb0_disable_MASK 0x00000002
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_usb0_disable_SHIFT 1
-
-/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_hdmi_tx1_disable [00:00] */
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_hdmi_tx1_disable_MASK 0x00000001
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_hdmi_tx1_disable_SHIFT 0
-
-/***************************************************************************
- *SEMAPHORE_0 - Semaphore channel 0
- ***************************************************************************/
-/* SUN_TOP_CTRL :: SEMAPHORE_0 :: reserved0 [31:08] */
-#define BCHP_SUN_TOP_CTRL_SEMAPHORE_0_reserved0_MASK 0xffffff00
-#define BCHP_SUN_TOP_CTRL_SEMAPHORE_0_reserved0_SHIFT 8
-
-/* SUN_TOP_CTRL :: SEMAPHORE_0 :: semaphore_ctrl [07:00] */
-#define BCHP_SUN_TOP_CTRL_SEMAPHORE_0_semaphore_ctrl_MASK 0x000000ff
-#define BCHP_SUN_TOP_CTRL_SEMAPHORE_0_semaphore_ctrl_SHIFT 0
-#define BCHP_SUN_TOP_CTRL_SEMAPHORE_0_semaphore_ctrl_DEFAULT 0x00000000
-
-/***************************************************************************
- *SEMAPHORE_1 - Semaphore channel 1
- ***************************************************************************/
-/* SUN_TOP_CTRL :: SEMAPHORE_1 :: reserved0 [31:08] */
-#define BCHP_SUN_TOP_CTRL_SEMAPHORE_1_reserved0_MASK 0xffffff00
-#define BCHP_SUN_TOP_CTRL_SEMAPHORE_1_reserved0_SHIFT 8
-
-/* SUN_TOP_CTRL :: SEMAPHORE_1 :: semaphore_ctrl [07:00] */
-#define BCHP_SUN_TOP_CTRL_SEMAPHORE_1_semaphore_ctrl_MASK 0x000000ff
-#define BCHP_SUN_TOP_CTRL_SEMAPHORE_1_semaphore_ctrl_SHIFT 0
-#define BCHP_SUN_TOP_CTRL_SEMAPHORE_1_semaphore_ctrl_DEFAULT 0x00000000
-
-/***************************************************************************
- *SEMAPHORE_2 - Semaphore channel 2
- ***************************************************************************/
-/* SUN_TOP_CTRL :: SEMAPHORE_2 :: reserved0 [31:08] */
-#define BCHP_SUN_TOP_CTRL_SEMAPHORE_2_reserved0_MASK 0xffffff00
-#define BCHP_SUN_TOP_CTRL_SEMAPHORE_2_reserved0_SHIFT 8
-
-/* SUN_TOP_CTRL :: SEMAPHORE_2 :: semaphore_ctrl [07:00] */
-#define BCHP_SUN_TOP_CTRL_SEMAPHORE_2_semaphore_ctrl_MASK 0x000000ff
-#define BCHP_SUN_TOP_CTRL_SEMAPHORE_2_semaphore_ctrl_SHIFT 0
-#define BCHP_SUN_TOP_CTRL_SEMAPHORE_2_semaphore_ctrl_DEFAULT 0x00000000
-
-/***************************************************************************
- *SEMAPHORE_3 - Semaphore channel 3
- ***************************************************************************/
-/* SUN_TOP_CTRL :: SEMAPHORE_3 :: reserved0 [31:08] */
-#define BCHP_SUN_TOP_CTRL_SEMAPHORE_3_reserved0_MASK 0xffffff00
-#define BCHP_SUN_TOP_CTRL_SEMAPHORE_3_reserved0_SHIFT 8
-
-/* SUN_TOP_CTRL :: SEMAPHORE_3 :: semaphore_ctrl [07:00] */
-#define BCHP_SUN_TOP_CTRL_SEMAPHORE_3_semaphore_ctrl_MASK 0x000000ff
-#define BCHP_SUN_TOP_CTRL_SEMAPHORE_3_semaphore_ctrl_SHIFT 0
-#define BCHP_SUN_TOP_CTRL_SEMAPHORE_3_semaphore_ctrl_DEFAULT 0x00000000
-
-/***************************************************************************
- *SEMAPHORE_4 - Semaphore channel 4
- ***************************************************************************/
-/* SUN_TOP_CTRL :: SEMAPHORE_4 :: reserved0 [31:08] */
-#define BCHP_SUN_TOP_CTRL_SEMAPHORE_4_reserved0_MASK 0xffffff00
-#define BCHP_SUN_TOP_CTRL_SEMAPHORE_4_reserved0_SHIFT 8
-
-/* SUN_TOP_CTRL :: SEMAPHORE_4 :: semaphore_ctrl [07:00] */
-#define BCHP_SUN_TOP_CTRL_SEMAPHORE_4_semaphore_ctrl_MASK 0x000000ff
-#define BCHP_SUN_TOP_CTRL_SEMAPHORE_4_semaphore_ctrl_SHIFT 0
-#define BCHP_SUN_TOP_CTRL_SEMAPHORE_4_semaphore_ctrl_DEFAULT 0x00000000
-
-/***************************************************************************
- *SEMAPHORE_5 - Semaphore channel 5
- ***************************************************************************/
-/* SUN_TOP_CTRL :: SEMAPHORE_5 :: reserved0 [31:08] */
-#define BCHP_SUN_TOP_CTRL_SEMAPHORE_5_reserved0_MASK 0xffffff00
-#define BCHP_SUN_TOP_CTRL_SEMAPHORE_5_reserved0_SHIFT 8
-
-/* SUN_TOP_CTRL :: SEMAPHORE_5 :: semaphore_ctrl [07:00] */
-#define BCHP_SUN_TOP_CTRL_SEMAPHORE_5_semaphore_ctrl_MASK 0x000000ff
-#define BCHP_SUN_TOP_CTRL_SEMAPHORE_5_semaphore_ctrl_SHIFT 0
-#define BCHP_SUN_TOP_CTRL_SEMAPHORE_5_semaphore_ctrl_DEFAULT 0x00000000
-
-/***************************************************************************
- *SEMAPHORE_6 - Semaphore channel 6
- ***************************************************************************/
-/* SUN_TOP_CTRL :: SEMAPHORE_6 :: reserved0 [31:08] */
-#define BCHP_SUN_TOP_CTRL_SEMAPHORE_6_reserved0_MASK 0xffffff00
-#define BCHP_SUN_TOP_CTRL_SEMAPHORE_6_reserved0_SHIFT 8
-
-/* SUN_TOP_CTRL :: SEMAPHORE_6 :: semaphore_ctrl [07:00] */
-#define BCHP_SUN_TOP_CTRL_SEMAPHORE_6_semaphore_ctrl_MASK 0x000000ff
-#define BCHP_SUN_TOP_CTRL_SEMAPHORE_6_semaphore_ctrl_SHIFT 0
-#define BCHP_SUN_TOP_CTRL_SEMAPHORE_6_semaphore_ctrl_DEFAULT 0x00000000
-
-/***************************************************************************
- *SEMAPHORE_7 - Semaphore channel 7
- ***************************************************************************/
-/* SUN_TOP_CTRL :: SEMAPHORE_7 :: reserved0 [31:08] */
-#define BCHP_SUN_TOP_CTRL_SEMAPHORE_7_reserved0_MASK 0xffffff00
-#define BCHP_SUN_TOP_CTRL_SEMAPHORE_7_reserved0_SHIFT 8
-
-/* SUN_TOP_CTRL :: SEMAPHORE_7 :: semaphore_ctrl [07:00] */
-#define BCHP_SUN_TOP_CTRL_SEMAPHORE_7_semaphore_ctrl_MASK 0x000000ff
-#define BCHP_SUN_TOP_CTRL_SEMAPHORE_7_semaphore_ctrl_SHIFT 0
-#define BCHP_SUN_TOP_CTRL_SEMAPHORE_7_semaphore_ctrl_DEFAULT 0x00000000
-
-/***************************************************************************
- *SEMAPHORE_8 - Semaphore channel 8
- ***************************************************************************/
-/* SUN_TOP_CTRL :: SEMAPHORE_8 :: reserved0 [31:08] */
-#define BCHP_SUN_TOP_CTRL_SEMAPHORE_8_reserved0_MASK 0xffffff00
-#define BCHP_SUN_TOP_CTRL_SEMAPHORE_8_reserved0_SHIFT 8
-
-/* SUN_TOP_CTRL :: SEMAPHORE_8 :: semaphore_ctrl [07:00] */
-#define BCHP_SUN_TOP_CTRL_SEMAPHORE_8_semaphore_ctrl_MASK 0x000000ff
-#define BCHP_SUN_TOP_CTRL_SEMAPHORE_8_semaphore_ctrl_SHIFT 0
-#define BCHP_SUN_TOP_CTRL_SEMAPHORE_8_semaphore_ctrl_DEFAULT 0x00000000
-
-/***************************************************************************
- *SEMAPHORE_9 - Semaphore channel 9
- ***************************************************************************/
-/* SUN_TOP_CTRL :: SEMAPHORE_9 :: reserved0 [31:08] */
-#define BCHP_SUN_TOP_CTRL_SEMAPHORE_9_reserved0_MASK 0xffffff00
-#define BCHP_SUN_TOP_CTRL_SEMAPHORE_9_reserved0_SHIFT 8
-
-/* SUN_TOP_CTRL :: SEMAPHORE_9 :: semaphore_ctrl [07:00] */
-#define BCHP_SUN_TOP_CTRL_SEMAPHORE_9_semaphore_ctrl_MASK 0x000000ff
-#define BCHP_SUN_TOP_CTRL_SEMAPHORE_9_semaphore_ctrl_SHIFT 0
-#define BCHP_SUN_TOP_CTRL_SEMAPHORE_9_semaphore_ctrl_DEFAULT 0x00000000
-
-/***************************************************************************
- *SEMAPHORE_10 - Semaphore channel 10
- ***************************************************************************/
-/* SUN_TOP_CTRL :: SEMAPHORE_10 :: reserved0 [31:08] */
-#define BCHP_SUN_TOP_CTRL_SEMAPHORE_10_reserved0_MASK 0xffffff00
-#define BCHP_SUN_TOP_CTRL_SEMAPHORE_10_reserved0_SHIFT 8
-
-/* SUN_TOP_CTRL :: SEMAPHORE_10 :: semaphore_ctrl [07:00] */
-#define BCHP_SUN_TOP_CTRL_SEMAPHORE_10_semaphore_ctrl_MASK 0x000000ff
-#define BCHP_SUN_TOP_CTRL_SEMAPHORE_10_semaphore_ctrl_SHIFT 0
-#define BCHP_SUN_TOP_CTRL_SEMAPHORE_10_semaphore_ctrl_DEFAULT 0x00000000
-
-/***************************************************************************
- *SEMAPHORE_11 - Semaphore channel 11
- ***************************************************************************/
-/* SUN_TOP_CTRL :: SEMAPHORE_11 :: reserved0 [31:08] */
-#define BCHP_SUN_TOP_CTRL_SEMAPHORE_11_reserved0_MASK 0xffffff00
-#define BCHP_SUN_TOP_CTRL_SEMAPHORE_11_reserved0_SHIFT 8
-
-/* SUN_TOP_CTRL :: SEMAPHORE_11 :: semaphore_ctrl [07:00] */
-#define BCHP_SUN_TOP_CTRL_SEMAPHORE_11_semaphore_ctrl_MASK 0x000000ff
-#define BCHP_SUN_TOP_CTRL_SEMAPHORE_11_semaphore_ctrl_SHIFT 0
-#define BCHP_SUN_TOP_CTRL_SEMAPHORE_11_semaphore_ctrl_DEFAULT 0x00000000
-
-/***************************************************************************
- *SEMAPHORE_12 - Semaphore channel 12
- ***************************************************************************/
-/* SUN_TOP_CTRL :: SEMAPHORE_12 :: reserved0 [31:08] */
-#define BCHP_SUN_TOP_CTRL_SEMAPHORE_12_reserved0_MASK 0xffffff00
-#define BCHP_SUN_TOP_CTRL_SEMAPHORE_12_reserved0_SHIFT 8
-
-/* SUN_TOP_CTRL :: SEMAPHORE_12 :: semaphore_ctrl [07:00] */
-#define BCHP_SUN_TOP_CTRL_SEMAPHORE_12_semaphore_ctrl_MASK 0x000000ff
-#define BCHP_SUN_TOP_CTRL_SEMAPHORE_12_semaphore_ctrl_SHIFT 0
-#define BCHP_SUN_TOP_CTRL_SEMAPHORE_12_semaphore_ctrl_DEFAULT 0x00000000
-
-/***************************************************************************
- *SEMAPHORE_13 - Semaphore channel 13
- ***************************************************************************/
-/* SUN_TOP_CTRL :: SEMAPHORE_13 :: reserved0 [31:08] */
-#define BCHP_SUN_TOP_CTRL_SEMAPHORE_13_reserved0_MASK 0xffffff00
-#define BCHP_SUN_TOP_CTRL_SEMAPHORE_13_reserved0_SHIFT 8
-
-/* SUN_TOP_CTRL :: SEMAPHORE_13 :: semaphore_ctrl [07:00] */
-#define BCHP_SUN_TOP_CTRL_SEMAPHORE_13_semaphore_ctrl_MASK 0x000000ff
-#define BCHP_SUN_TOP_CTRL_SEMAPHORE_13_semaphore_ctrl_SHIFT 0
-#define BCHP_SUN_TOP_CTRL_SEMAPHORE_13_semaphore_ctrl_DEFAULT 0x00000000
-
-/***************************************************************************
- *SEMAPHORE_14 - Semaphore channel 14
- ***************************************************************************/
-/* SUN_TOP_CTRL :: SEMAPHORE_14 :: reserved0 [31:08] */
-#define BCHP_SUN_TOP_CTRL_SEMAPHORE_14_reserved0_MASK 0xffffff00
-#define BCHP_SUN_TOP_CTRL_SEMAPHORE_14_reserved0_SHIFT 8
-
-/* SUN_TOP_CTRL :: SEMAPHORE_14 :: semaphore_ctrl [07:00] */
-#define BCHP_SUN_TOP_CTRL_SEMAPHORE_14_semaphore_ctrl_MASK 0x000000ff
-#define BCHP_SUN_TOP_CTRL_SEMAPHORE_14_semaphore_ctrl_SHIFT 0
-#define BCHP_SUN_TOP_CTRL_SEMAPHORE_14_semaphore_ctrl_DEFAULT 0x00000000
-
-/***************************************************************************
- *SEMAPHORE_15 - Semaphore channel 15
- ***************************************************************************/
-/* SUN_TOP_CTRL :: SEMAPHORE_15 :: reserved0 [31:08] */
-#define BCHP_SUN_TOP_CTRL_SEMAPHORE_15_reserved0_MASK 0xffffff00
-#define BCHP_SUN_TOP_CTRL_SEMAPHORE_15_reserved0_SHIFT 8
-
-/* SUN_TOP_CTRL :: SEMAPHORE_15 :: semaphore_ctrl [07:00] */
-#define BCHP_SUN_TOP_CTRL_SEMAPHORE_15_semaphore_ctrl_MASK 0x000000ff
-#define BCHP_SUN_TOP_CTRL_SEMAPHORE_15_semaphore_ctrl_SHIFT 0
-#define BCHP_SUN_TOP_CTRL_SEMAPHORE_15_semaphore_ctrl_DEFAULT 0x00000000
-
-/***************************************************************************
- *GEN_WATCHDOG_0 - General watchdog timer 0
- ***************************************************************************/
-/* SUN_TOP_CTRL :: GEN_WATCHDOG_0 :: watchdog_timeout_value [31:00] */
-#define BCHP_SUN_TOP_CTRL_GEN_WATCHDOG_0_watchdog_timeout_value_MASK 0xffffffff
-#define BCHP_SUN_TOP_CTRL_GEN_WATCHDOG_0_watchdog_timeout_value_SHIFT 0
-#define BCHP_SUN_TOP_CTRL_GEN_WATCHDOG_0_watchdog_timeout_value_DEFAULT 0x00000000
-
-/***************************************************************************
- *GEN_WATCHDOG_1 - General watchdog timer 1
- ***************************************************************************/
-/* SUN_TOP_CTRL :: GEN_WATCHDOG_1 :: watchdog_timeout_value [31:00] */
-#define BCHP_SUN_TOP_CTRL_GEN_WATCHDOG_1_watchdog_timeout_value_MASK 0xffffffff
-#define BCHP_SUN_TOP_CTRL_GEN_WATCHDOG_1_watchdog_timeout_value_SHIFT 0
-#define BCHP_SUN_TOP_CTRL_GEN_WATCHDOG_1_watchdog_timeout_value_DEFAULT 0x00000000
-
-/***************************************************************************
- *GENERAL_CTRL_0 - General control register 0
- ***************************************************************************/
-/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_31 [31:31] */
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_31_MASK 0x80000000
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_31_SHIFT 31
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_31_DEFAULT 0x00000001
-
-/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_30 [30:30] */
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_30_MASK 0x40000000
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_30_SHIFT 30
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_30_DEFAULT 0x00000001
-
-/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_29 [29:29] */
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_29_MASK 0x20000000
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_29_SHIFT 29
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_29_DEFAULT 0x00000001
-
-/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_28 [28:28] */
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_28_MASK 0x10000000
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_28_SHIFT 28
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_28_DEFAULT 0x00000001
-
-/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_27 [27:27] */
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_27_MASK 0x08000000
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_27_SHIFT 27
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_27_DEFAULT 0x00000001
-
-/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_26 [26:26] */
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_26_MASK 0x04000000
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_26_SHIFT 26
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_26_DEFAULT 0x00000001
-
-/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_25 [25:25] */
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_25_MASK 0x02000000
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_25_SHIFT 25
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_25_DEFAULT 0x00000001
-
-/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_24 [24:24] */
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_24_MASK 0x01000000
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_24_SHIFT 24
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_24_DEFAULT 0x00000001
-
-/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_23 [23:23] */
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_23_MASK 0x00800000
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_23_SHIFT 23
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_23_DEFAULT 0x00000001
-
-/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_22 [22:22] */
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_22_MASK 0x00400000
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_22_SHIFT 22
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_22_DEFAULT 0x00000001
-
-/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_21 [21:21] */
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_21_MASK 0x00200000
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_21_SHIFT 21
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_21_DEFAULT 0x00000001
-
-/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_20 [20:20] */
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_20_MASK 0x00100000
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_20_SHIFT 20
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_20_DEFAULT 0x00000001
-
-/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_19 [19:19] */
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_19_MASK 0x00080000
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_19_SHIFT 19
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_19_DEFAULT 0x00000001
-
-/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_18 [18:18] */
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_18_MASK 0x00040000
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_18_SHIFT 18
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_18_DEFAULT 0x00000001
-
-/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_17 [17:17] */
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_17_MASK 0x00020000
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_17_SHIFT 17
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_17_DEFAULT 0x00000001
-
-/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_16 [16:16] */
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_16_MASK 0x00010000
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_16_SHIFT 16
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_16_DEFAULT 0x00000001
-
-/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_15 [15:15] */
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_15_MASK 0x00008000
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_15_SHIFT 15
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_15_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_14 [14:14] */
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_14_MASK 0x00004000
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_14_SHIFT 14
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_14_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_13 [13:13] */
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_13_MASK 0x00002000
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_13_SHIFT 13
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_13_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_12 [12:12] */
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_12_MASK 0x00001000
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_12_SHIFT 12
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_12_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_11 [11:11] */
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_11_MASK 0x00000800
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_11_SHIFT 11
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_11_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_10 [10:10] */
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_10_MASK 0x00000400
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_10_SHIFT 10
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_10_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_9 [09:09] */
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_9_MASK 0x00000200
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_9_SHIFT 9
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_9_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: bert_pinmux_ctrl [08:06] */
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_bert_pinmux_ctrl_MASK 0x000001c0
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_bert_pinmux_ctrl_SHIFT 6
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_bert_pinmux_ctrl_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_5 [05:05] */
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_5_MASK 0x00000020
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_5_SHIFT 5
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_5_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: ana_detect_sdio_1_pd [04:04] */
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_ana_detect_sdio_1_pd_MASK 0x00000010
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_ana_detect_sdio_1_pd_SHIFT 4
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_ana_detect_sdio_1_pd_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: ana_detect_sdio_0_pd [03:03] */
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_ana_detect_sdio_0_pd_MASK 0x00000008
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_ana_detect_sdio_0_pd_SHIFT 3
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_ana_detect_sdio_0_pd_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: sdio_1_pad_modehv_override [02:02] */
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_sdio_1_pad_modehv_override_MASK 0x00000004
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_sdio_1_pad_modehv_override_SHIFT 2
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_sdio_1_pad_modehv_override_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: sdio_0_pad_modehv_override [01:01] */
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_sdio_0_pad_modehv_override_MASK 0x00000002
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_sdio_0_pad_modehv_override_SHIFT 1
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_sdio_0_pad_modehv_override_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: mii_genet_mac_select [00:00] */
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_mii_genet_mac_select_MASK 0x00000001
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_mii_genet_mac_select_SHIFT 0
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_mii_genet_mac_select_DEFAULT 0x00000000
-
-/***************************************************************************
- *GENERAL_CTRL_1 - General control register 1
- ***************************************************************************/
-/* SUN_TOP_CTRL :: GENERAL_CTRL_1 :: reserved0 [31:04] */
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_reserved0_MASK 0xfffffff0
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_reserved0_SHIFT 4
-
-/* SUN_TOP_CTRL :: GENERAL_CTRL_1 :: general_ctrl1_3 [03:03] */
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_3_MASK 0x00000008
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_3_SHIFT 3
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_3_DEFAULT 0x00000001
-
-/* SUN_TOP_CTRL :: GENERAL_CTRL_1 :: general_ctrl1_2 [02:02] */
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_2_MASK 0x00000004
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_2_SHIFT 2
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_2_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: GENERAL_CTRL_1 :: fsk_test_dac_edge_sel [01:01] */
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_fsk_test_dac_edge_sel_MASK 0x00000002
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_fsk_test_dac_edge_sel_SHIFT 1
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_fsk_test_dac_edge_sel_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: GENERAL_CTRL_1 :: fsk_test_dac_en [00:00] */
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_fsk_test_dac_en_MASK 0x00000001
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_fsk_test_dac_en_SHIFT 0
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_fsk_test_dac_en_DEFAULT 0x00000000
-
-/***************************************************************************
- *GENERAL_CTRL_2 - General control register 2
- ***************************************************************************/
-/* SUN_TOP_CTRL :: GENERAL_CTRL_2 :: reserved0 [31:02] */
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_2_reserved0_MASK 0xfffffffc
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_2_reserved0_SHIFT 2
-
-/* SUN_TOP_CTRL :: GENERAL_CTRL_2 :: general_ctrl2_1 [01:01] */
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_2_general_ctrl2_1_MASK 0x00000002
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_2_general_ctrl2_1_SHIFT 1
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_2_general_ctrl2_1_DEFAULT 0x00000001
-
-/* SUN_TOP_CTRL :: GENERAL_CTRL_2 :: general_ctrl2_0 [00:00] */
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_2_general_ctrl2_0_MASK 0x00000001
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_2_general_ctrl2_0_SHIFT 0
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_2_general_ctrl2_0_DEFAULT 0x00000000
-
-/***************************************************************************
- *GENERAL_CTRL_3 - General control register 3
- ***************************************************************************/
-/* SUN_TOP_CTRL :: GENERAL_CTRL_3 :: reserved0 [31:02] */
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_3_reserved0_MASK 0xfffffffc
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_3_reserved0_SHIFT 2
-
-/* SUN_TOP_CTRL :: GENERAL_CTRL_3 :: general_ctrl3_1 [01:01] */
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_3_general_ctrl3_1_MASK 0x00000002
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_3_general_ctrl3_1_SHIFT 1
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_3_general_ctrl3_1_DEFAULT 0x00000001
-
-/* SUN_TOP_CTRL :: GENERAL_CTRL_3 :: general_ctrl3_0 [00:00] */
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_3_general_ctrl3_0_MASK 0x00000001
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_3_general_ctrl3_0_SHIFT 0
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_3_general_ctrl3_0_DEFAULT 0x00000000
-
-/***************************************************************************
- *GENERAL_CTRL_4 - General control register 4
- ***************************************************************************/
-/* SUN_TOP_CTRL :: GENERAL_CTRL_4 :: reserved0 [31:02] */
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_4_reserved0_MASK 0xfffffffc
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_4_reserved0_SHIFT 2
-
-/* SUN_TOP_CTRL :: GENERAL_CTRL_4 :: general_ctrl4_1 [01:01] */
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_4_general_ctrl4_1_MASK 0x00000002
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_4_general_ctrl4_1_SHIFT 1
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_4_general_ctrl4_1_DEFAULT 0x00000001
-
-/* SUN_TOP_CTRL :: GENERAL_CTRL_4 :: general_ctrl4_0 [00:00] */
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_4_general_ctrl4_0_MASK 0x00000001
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_4_general_ctrl4_0_SHIFT 0
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_4_general_ctrl4_0_DEFAULT 0x00000000
-
-/***************************************************************************
- *GENERAL_CTRL_5 - General control register 5
- ***************************************************************************/
-/* SUN_TOP_CTRL :: GENERAL_CTRL_5 :: reserved0 [31:02] */
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_5_reserved0_MASK 0xfffffffc
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_5_reserved0_SHIFT 2
-
-/* SUN_TOP_CTRL :: GENERAL_CTRL_5 :: general_ctrl5_1 [01:01] */
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_5_general_ctrl5_1_MASK 0x00000002
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_5_general_ctrl5_1_SHIFT 1
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_5_general_ctrl5_1_DEFAULT 0x00000001
-
-/* SUN_TOP_CTRL :: GENERAL_CTRL_5 :: general_ctrl5_0 [00:00] */
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_5_general_ctrl5_0_MASK 0x00000001
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_5_general_ctrl5_0_SHIFT 0
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_5_general_ctrl5_0_DEFAULT 0x00000000
-
-/***************************************************************************
- *GENERAL_STATUS_0 - General status register 0
- ***************************************************************************/
-/* SUN_TOP_CTRL :: GENERAL_STATUS_0 :: reserved0 [31:08] */
-#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0_reserved0_MASK 0xffffff00
-#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0_reserved0_SHIFT 8
-
-/* SUN_TOP_CTRL :: GENERAL_STATUS_0 :: general_status0_7 [07:07] */
-#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0_general_status0_7_MASK 0x00000080
-#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0_general_status0_7_SHIFT 7
-
-/* SUN_TOP_CTRL :: GENERAL_STATUS_0 :: general_status0_6 [06:06] */
-#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0_general_status0_6_MASK 0x00000040
-#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0_general_status0_6_SHIFT 6
-
-/* SUN_TOP_CTRL :: GENERAL_STATUS_0 :: general_status0_5 [05:05] */
-#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0_general_status0_5_MASK 0x00000020
-#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0_general_status0_5_SHIFT 5
-
-/* SUN_TOP_CTRL :: GENERAL_STATUS_0 :: general_status0_4 [04:04] */
-#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0_general_status0_4_MASK 0x00000010
-#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0_general_status0_4_SHIFT 4
-
-/* SUN_TOP_CTRL :: GENERAL_STATUS_0 :: general_status0_3 [03:03] */
-#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0_general_status0_3_MASK 0x00000008
-#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0_general_status0_3_SHIFT 3
-
-/* SUN_TOP_CTRL :: GENERAL_STATUS_0 :: general_status0_2 [02:02] */
-#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0_general_status0_2_MASK 0x00000004
-#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0_general_status0_2_SHIFT 2
-
-/* SUN_TOP_CTRL :: GENERAL_STATUS_0 :: ebi_pad_config [01:01] */
-#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0_ebi_pad_config_MASK 0x00000002
-#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0_ebi_pad_config_SHIFT 1
-
-/* SUN_TOP_CTRL :: GENERAL_STATUS_0 :: hif_strap_invalid [00:00] */
-#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0_hif_strap_invalid_MASK 0x00000001
-#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0_hif_strap_invalid_SHIFT 0
-
-/***************************************************************************
- *GENERAL_STATUS_1 - General status register 1
- ***************************************************************************/
-/* SUN_TOP_CTRL :: GENERAL_STATUS_1 :: reserved0 [31:02] */
-#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_1_reserved0_MASK 0xfffffffc
-#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_1_reserved0_SHIFT 2
-
-/* SUN_TOP_CTRL :: GENERAL_STATUS_1 :: sdio_1_pad_vddo [01:01] */
-#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_1_sdio_1_pad_vddo_MASK 0x00000002
-#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_1_sdio_1_pad_vddo_SHIFT 1
-
-/* SUN_TOP_CTRL :: GENERAL_STATUS_1 :: sdio_0_pad_vddo [00:00] */
-#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_1_sdio_0_pad_vddo_MASK 0x00000001
-#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_1_sdio_0_pad_vddo_SHIFT 0
-
-/***************************************************************************
- *GENERAL_STATUS_2 - General status register 2
- ***************************************************************************/
-/* SUN_TOP_CTRL :: GENERAL_STATUS_2 :: reserved0 [31:02] */
-#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_2_reserved0_MASK 0xfffffffc
-#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_2_reserved0_SHIFT 2
-
-/* SUN_TOP_CTRL :: GENERAL_STATUS_2 :: general_status2_1 [01:01] */
-#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_2_general_status2_1_MASK 0x00000002
-#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_2_general_status2_1_SHIFT 1
-
-/* SUN_TOP_CTRL :: GENERAL_STATUS_2 :: general_status2_0 [00:00] */
-#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_2_general_status2_0_MASK 0x00000001
-#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_2_general_status2_0_SHIFT 0
-
-/***************************************************************************
- *GENERAL_CTRL_NO_SCAN_0 - General control register without scan 0
- ***************************************************************************/
-/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: reserved0 [31:18] */
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_reserved0_MASK 0xfffc0000
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_reserved0_SHIFT 18
-
-/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: mtsif_0_pad_amp_en [17:17] */
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_mtsif_0_pad_amp_en_MASK 0x00020000
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_mtsif_0_pad_amp_en_SHIFT 17
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_mtsif_0_pad_amp_en_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: mtsif_0_pad_sel_gmii [16:16] */
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_mtsif_0_pad_sel_gmii_MASK 0x00010000
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_mtsif_0_pad_sel_gmii_SHIFT 16
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_mtsif_0_pad_sel_gmii_DEFAULT 0x00000001
-
-/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: mtsif_0_pad_modehv [15:15] */
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_mtsif_0_pad_modehv_MASK 0x00008000
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_mtsif_0_pad_modehv_SHIFT 15
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_mtsif_0_pad_modehv_DEFAULT 0x00000001
-
-/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: mtsif_0_pad_sel [14:12] */
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_mtsif_0_pad_sel_MASK 0x00007000
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_mtsif_0_pad_sel_SHIFT 12
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_mtsif_0_pad_sel_DEFAULT 0x00000003
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_mtsif_0_pad_sel_DRIVE_2MA 0
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_mtsif_0_pad_sel_DRIVE_4MA 1
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_mtsif_0_pad_sel_DRIVE_6MA 2
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_mtsif_0_pad_sel_DRIVE_8MA 3
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_mtsif_0_pad_sel_DRIVE_10MA 4
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_mtsif_0_pad_sel_DRIVE_12MA 5
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_mtsif_0_pad_sel_DRIVE_14MA 6
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_mtsif_0_pad_sel_DRIVE_16MA 7
-
-/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: mtsif_1_pad_amp_en [11:11] */
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_mtsif_1_pad_amp_en_MASK 0x00000800
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_mtsif_1_pad_amp_en_SHIFT 11
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_mtsif_1_pad_amp_en_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: mtsif_1_pad_sel_gmii [10:10] */
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_mtsif_1_pad_sel_gmii_MASK 0x00000400
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_mtsif_1_pad_sel_gmii_SHIFT 10
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_mtsif_1_pad_sel_gmii_DEFAULT 0x00000001
-
-/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: mtsif_1_pad_modehv [09:09] */
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_mtsif_1_pad_modehv_MASK 0x00000200
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_mtsif_1_pad_modehv_SHIFT 9
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_mtsif_1_pad_modehv_DEFAULT 0x00000001
-
-/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: mtsif_1_pad_sel [08:06] */
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_mtsif_1_pad_sel_MASK 0x000001c0
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_mtsif_1_pad_sel_SHIFT 6
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_mtsif_1_pad_sel_DEFAULT 0x00000003
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_mtsif_1_pad_sel_DRIVE_2MA 0
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_mtsif_1_pad_sel_DRIVE_4MA 1
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_mtsif_1_pad_sel_DRIVE_6MA 2
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_mtsif_1_pad_sel_DRIVE_8MA 3
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_mtsif_1_pad_sel_DRIVE_10MA 4
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_mtsif_1_pad_sel_DRIVE_12MA 5
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_mtsif_1_pad_sel_DRIVE_14MA 6
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_mtsif_1_pad_sel_DRIVE_16MA 7
-
-/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: rgmii_0_pad_amp_en [05:05] */
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_rgmii_0_pad_amp_en_MASK 0x00000020
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_rgmii_0_pad_amp_en_SHIFT 5
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_rgmii_0_pad_amp_en_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: rgmii_0_pad_sel_gmii [04:04] */
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_rgmii_0_pad_sel_gmii_MASK 0x00000010
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_rgmii_0_pad_sel_gmii_SHIFT 4
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_rgmii_0_pad_sel_gmii_DEFAULT 0x00000001
-
-/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: rgmii_0_pad_modehv [03:03] */
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_rgmii_0_pad_modehv_MASK 0x00000008
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_rgmii_0_pad_modehv_SHIFT 3
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_rgmii_0_pad_modehv_DEFAULT 0x00000001
-
-/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: rgmii_0_pad_sel [02:00] */
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_rgmii_0_pad_sel_MASK 0x00000007
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_rgmii_0_pad_sel_SHIFT 0
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_rgmii_0_pad_sel_DEFAULT 0x00000003
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_rgmii_0_pad_sel_DRIVE_2MA 0
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_rgmii_0_pad_sel_DRIVE_4MA 1
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_rgmii_0_pad_sel_DRIVE_6MA 2
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_rgmii_0_pad_sel_DRIVE_8MA 3
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_rgmii_0_pad_sel_DRIVE_10MA 4
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_rgmii_0_pad_sel_DRIVE_12MA 5
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_rgmii_0_pad_sel_DRIVE_14MA 6
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_rgmii_0_pad_sel_DRIVE_16MA 7
-
-/***************************************************************************
- *GENERAL_CTRL_NO_SCAN_1 - General control register without scan 1
- ***************************************************************************/
-/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_1 :: reserved0 [31:28] */
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_reserved0_MASK 0xf0000000
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_reserved0_SHIFT 28
-
-/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_1 :: pad_mode_gpio_057 [27:27] */
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_057_MASK 0x08000000
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_057_SHIFT 27
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_057_DEFAULT 0x00000001
-
-/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_1 :: pad_mode_gpio_056 [26:26] */
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_056_MASK 0x04000000
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_056_SHIFT 26
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_056_DEFAULT 0x00000001
-
-/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_1 :: pad_mode_gpio_055 [25:25] */
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_055_MASK 0x02000000
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_055_SHIFT 25
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_055_DEFAULT 0x00000001
-
-/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_1 :: pad_mode_gpio_054 [24:24] */
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_054_MASK 0x01000000
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_054_SHIFT 24
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_054_DEFAULT 0x00000001
-
-/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_1 :: pad_mode_gpio_053 [23:23] */
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_053_MASK 0x00800000
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_053_SHIFT 23
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_053_DEFAULT 0x00000001
-
-/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_1 :: pad_mode_gpio_052 [22:22] */
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_052_MASK 0x00400000
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_052_SHIFT 22
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_052_DEFAULT 0x00000001
-
-/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_1 :: pad_mode_gpio_051 [21:21] */
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_051_MASK 0x00200000
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_051_SHIFT 21
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_051_DEFAULT 0x00000001
-
-/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_1 :: pad_mode_gpio_050 [20:20] */
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_050_MASK 0x00100000
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_050_SHIFT 20
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_050_DEFAULT 0x00000001
-
-/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_1 :: pad_mode_gpio_049 [19:19] */
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_049_MASK 0x00080000
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_049_SHIFT 19
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_049_DEFAULT 0x00000001
-
-/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_1 :: pad_mode_gpio_048 [18:18] */
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_048_MASK 0x00040000
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_048_SHIFT 18
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_048_DEFAULT 0x00000001
-
-/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_1 :: pad_mode_gpio_047 [17:17] */
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_047_MASK 0x00020000
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_047_SHIFT 17
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_047_DEFAULT 0x00000001
-
-/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_1 :: pad_mode_gpio_046 [16:16] */
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_046_MASK 0x00010000
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_046_SHIFT 16
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_046_DEFAULT 0x00000001
-
-/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_1 :: pad_mode_gpio_045 [15:15] */
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_045_MASK 0x00008000
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_045_SHIFT 15
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_045_DEFAULT 0x00000001
-
-/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_1 :: pad_mode_gpio_044 [14:14] */
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_044_MASK 0x00004000
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_044_SHIFT 14
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_044_DEFAULT 0x00000001
-
-/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_1 :: pad_mode_gpio_043 [13:13] */
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_043_MASK 0x00002000
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_043_SHIFT 13
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_043_DEFAULT 0x00000001
-
-/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_1 :: pad_mode_gpio_042 [12:12] */
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_042_MASK 0x00001000
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_042_SHIFT 12
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_042_DEFAULT 0x00000001
-
-/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_1 :: pad_mode_gpio_041 [11:11] */
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_041_MASK 0x00000800
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_041_SHIFT 11
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_041_DEFAULT 0x00000001
-
-/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_1 :: pad_mode_gpio_040 [10:10] */
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_040_MASK 0x00000400
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_040_SHIFT 10
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_040_DEFAULT 0x00000001
-
-/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_1 :: pad_mode_gpio_039 [09:09] */
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_039_MASK 0x00000200
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_039_SHIFT 9
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_039_DEFAULT 0x00000001
-
-/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_1 :: pad_mode_gpio_038 [08:08] */
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_038_MASK 0x00000100
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_038_SHIFT 8
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_038_DEFAULT 0x00000001
-
-/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_1 :: pad_mode_gpio_037 [07:07] */
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_037_MASK 0x00000080
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_037_SHIFT 7
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_037_DEFAULT 0x00000001
-
-/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_1 :: pad_mode_gpio_036 [06:06] */
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_036_MASK 0x00000040
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_036_SHIFT 6
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_036_DEFAULT 0x00000001
-
-/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_1 :: pad_mode_gpio_035 [05:05] */
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_035_MASK 0x00000020
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_035_SHIFT 5
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_035_DEFAULT 0x00000001
-
-/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_1 :: pad_mode_gpio_034 [04:04] */
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_034_MASK 0x00000010
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_034_SHIFT 4
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_034_DEFAULT 0x00000001
-
-/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_1 :: pad_mode_gpio_033 [03:03] */
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_033_MASK 0x00000008
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_033_SHIFT 3
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_033_DEFAULT 0x00000001
-
-/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_1 :: pad_mode_gpio_032 [02:02] */
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_032_MASK 0x00000004
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_032_SHIFT 2
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_032_DEFAULT 0x00000001
-
-/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_1 :: pad_mode_gpio_031 [01:01] */
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_031_MASK 0x00000002
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_031_SHIFT 1
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_031_DEFAULT 0x00000001
-
-/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_1 :: pad_mode_gpio_030 [00:00] */
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_030_MASK 0x00000001
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_030_SHIFT 0
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_030_DEFAULT 0x00000001
-
-/***************************************************************************
- *GENERAL_CTRL_NO_SCAN_2 - General control register without scan 2
- ***************************************************************************/
-/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_2 :: reserved0 [31:30] */
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_reserved0_MASK 0xc0000000
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_reserved0_SHIFT 30
-
-/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_2 :: sdio_1_pad_slew [29:29] */
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_sdio_1_pad_slew_MASK 0x20000000
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_sdio_1_pad_slew_SHIFT 29
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_sdio_1_pad_slew_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_2 :: sdio_0_pad_slew [28:28] */
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_sdio_0_pad_slew_MASK 0x10000000
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_sdio_0_pad_slew_SHIFT 28
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_sdio_0_pad_slew_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_2 :: emmc_pad_slew [27:27] */
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_emmc_pad_slew_MASK 0x08000000
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_emmc_pad_slew_SHIFT 27
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_emmc_pad_slew_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_2 :: emmc_pad_sel [26:24] */
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_emmc_pad_sel_MASK 0x07000000
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_emmc_pad_sel_SHIFT 24
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_emmc_pad_sel_DEFAULT 0x00000003
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_emmc_pad_sel_DRIVE_2MA 0
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_emmc_pad_sel_DRIVE_4MA 1
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_emmc_pad_sel_DRIVE_6MA 2
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_emmc_pad_sel_DRIVE_8MA 3
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_emmc_pad_sel_DRIVE_10MA 4
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_emmc_pad_sel_DRIVE_12MA 5
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_emmc_pad_sel_DRIVE_14MA 6
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_emmc_pad_sel_DRIVE_16MA 7
-
-/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_2 :: bspi_pad_src [23:23] */
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_bspi_pad_src_MASK 0x00800000
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_bspi_pad_src_SHIFT 23
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_bspi_pad_src_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_2 :: bspi_pad_sel [22:20] */
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_bspi_pad_sel_MASK 0x00700000
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_bspi_pad_sel_SHIFT 20
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_bspi_pad_sel_DEFAULT 0x00000003
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_bspi_pad_sel_DRIVE_2MA 0
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_bspi_pad_sel_DRIVE_4MA 1
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_bspi_pad_sel_DRIVE_6MA 2
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_bspi_pad_sel_DRIVE_8MA 3
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_bspi_pad_sel_DRIVE_10MA 4
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_bspi_pad_sel_DRIVE_12MA 5
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_bspi_pad_sel_DRIVE_14MA 6
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_bspi_pad_sel_DRIVE_16MA 7
-
-/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_2 :: ebi_4_pad_src [19:19] */
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_4_pad_src_MASK 0x00080000
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_4_pad_src_SHIFT 19
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_4_pad_src_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_2 :: ebi_4_pad_sel [18:16] */
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_4_pad_sel_MASK 0x00070000
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_4_pad_sel_SHIFT 16
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_4_pad_sel_DEFAULT 0x00000003
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_4_pad_sel_DRIVE_2MA 0
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_4_pad_sel_DRIVE_4MA 1
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_4_pad_sel_DRIVE_6MA 2
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_4_pad_sel_DRIVE_8MA 3
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_4_pad_sel_DRIVE_10MA 4
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_4_pad_sel_DRIVE_12MA 5
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_4_pad_sel_DRIVE_14MA 6
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_4_pad_sel_DRIVE_16MA 7
-
-/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_2 :: ebi_3_pad_src [15:15] */
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_3_pad_src_MASK 0x00008000
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_3_pad_src_SHIFT 15
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_3_pad_src_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_2 :: ebi_3_pad_sel [14:12] */
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_3_pad_sel_MASK 0x00007000
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_3_pad_sel_SHIFT 12
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_3_pad_sel_DEFAULT 0x00000003
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_3_pad_sel_DRIVE_2MA 0
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_3_pad_sel_DRIVE_4MA 1
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_3_pad_sel_DRIVE_6MA 2
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_3_pad_sel_DRIVE_8MA 3
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_3_pad_sel_DRIVE_10MA 4
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_3_pad_sel_DRIVE_12MA 5
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_3_pad_sel_DRIVE_14MA 6
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_3_pad_sel_DRIVE_16MA 7
-
-/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_2 :: ebi_2_pad_src [11:11] */
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_2_pad_src_MASK 0x00000800
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_2_pad_src_SHIFT 11
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_2_pad_src_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_2 :: ebi_2_pad_sel [10:08] */
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_2_pad_sel_MASK 0x00000700
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_2_pad_sel_SHIFT 8
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_2_pad_sel_DEFAULT 0x00000003
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_2_pad_sel_DRIVE_2MA 0
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_2_pad_sel_DRIVE_4MA 1
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_2_pad_sel_DRIVE_6MA 2
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_2_pad_sel_DRIVE_8MA 3
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_2_pad_sel_DRIVE_10MA 4
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_2_pad_sel_DRIVE_12MA 5
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_2_pad_sel_DRIVE_14MA 6
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_2_pad_sel_DRIVE_16MA 7
-
-/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_2 :: ebi_1_pad_src [07:07] */
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_1_pad_src_MASK 0x00000080
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_1_pad_src_SHIFT 7
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_1_pad_src_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_2 :: ebi_1_pad_sel [06:04] */
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_1_pad_sel_MASK 0x00000070
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_1_pad_sel_SHIFT 4
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_1_pad_sel_DEFAULT 0x00000003
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_1_pad_sel_DRIVE_2MA 0
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_1_pad_sel_DRIVE_4MA 1
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_1_pad_sel_DRIVE_6MA 2
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_1_pad_sel_DRIVE_8MA 3
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_1_pad_sel_DRIVE_10MA 4
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_1_pad_sel_DRIVE_12MA 5
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_1_pad_sel_DRIVE_14MA 6
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_1_pad_sel_DRIVE_16MA 7
-
-/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_2 :: ebi_0_pad_src [03:03] */
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_0_pad_src_MASK 0x00000008
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_0_pad_src_SHIFT 3
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_0_pad_src_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_2 :: ebi_0_pad_sel [02:00] */
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_0_pad_sel_MASK 0x00000007
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_0_pad_sel_SHIFT 0
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_0_pad_sel_DEFAULT 0x00000003
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_0_pad_sel_DRIVE_2MA 0
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_0_pad_sel_DRIVE_4MA 1
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_0_pad_sel_DRIVE_6MA 2
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_0_pad_sel_DRIVE_8MA 3
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_0_pad_sel_DRIVE_10MA 4
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_0_pad_sel_DRIVE_12MA 5
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_0_pad_sel_DRIVE_14MA 6
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_0_pad_sel_DRIVE_16MA 7
-
-/***************************************************************************
- *GENERAL_CTRL_NO_SCAN_3 - General control register without scan 3
- ***************************************************************************/
-/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_3 :: reserved0 [31:02] */
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_reserved0_MASK 0xfffffffc
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_reserved0_SHIFT 2
-
-/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_3 :: general_ctrl_no_scan3_1 [01:01] */
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_general_ctrl_no_scan3_1_MASK 0x00000002
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_general_ctrl_no_scan3_1_SHIFT 1
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_general_ctrl_no_scan3_1_DEFAULT 0x00000001
-
-/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_3 :: general_ctrl_no_scan3_0 [00:00] */
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_general_ctrl_no_scan3_0_MASK 0x00000001
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_general_ctrl_no_scan3_0_SHIFT 0
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_general_ctrl_no_scan3_0_DEFAULT 0x00000000
-
-/***************************************************************************
- *GENERAL_CTRL_NO_SCAN_4 - General control register without scan 4
- ***************************************************************************/
-/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_4 :: reserved0 [31:02] */
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_4_reserved0_MASK 0xfffffffc
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_4_reserved0_SHIFT 2
-
-/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_4 :: general_ctrl_no_scan4_1 [01:01] */
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_4_general_ctrl_no_scan4_1_MASK 0x00000002
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_4_general_ctrl_no_scan4_1_SHIFT 1
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_4_general_ctrl_no_scan4_1_DEFAULT 0x00000001
-
-/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_4 :: general_ctrl_no_scan4_0 [00:00] */
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_4_general_ctrl_no_scan4_0_MASK 0x00000001
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_4_general_ctrl_no_scan4_0_SHIFT 0
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_4_general_ctrl_no_scan4_0_DEFAULT 0x00000000
-
-/***************************************************************************
- *GENERAL_CTRL_NO_SCAN_5 - General control register without scan 5
- ***************************************************************************/
-/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_5 :: reserved0 [31:08] */
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_reserved0_MASK 0xffffff00
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_reserved0_SHIFT 8
-
-/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_5 :: egphy_test_pin_mux_sel [07:07] */
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_egphy_test_pin_mux_sel_MASK 0x00000080
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_egphy_test_pin_mux_sel_SHIFT 7
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_egphy_test_pin_mux_sel_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_5 :: test_thp_hys_en [06:06] */
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_test_thp_hys_en_MASK 0x00000040
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_test_thp_hys_en_SHIFT 6
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_test_thp_hys_en_DEFAULT 0x00000001
-
-/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_5 :: test_thp_oeb [05:05] */
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_test_thp_oeb_MASK 0x00000020
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_test_thp_oeb_SHIFT 5
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_test_thp_oeb_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_5 :: test_thp_do [04:04] */
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_test_thp_do_MASK 0x00000010
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_test_thp_do_SHIFT 4
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_test_thp_do_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_5 :: test_drive_src [03:03] */
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_test_drive_src_MASK 0x00000008
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_test_drive_src_SHIFT 3
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_test_drive_src_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_5 :: test_drive_sel [02:00] */
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_test_drive_sel_MASK 0x00000007
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_test_drive_sel_SHIFT 0
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_test_drive_sel_DEFAULT 0x00000003
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_test_drive_sel_DRIVE_2MA 0
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_test_drive_sel_DRIVE_4MA 1
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_test_drive_sel_DRIVE_6MA 2
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_test_drive_sel_DRIVE_8MA 3
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_test_drive_sel_DRIVE_10MA 4
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_test_drive_sel_DRIVE_12MA 5
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_test_drive_sel_DRIVE_14MA 6
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_test_drive_sel_DRIVE_16MA 7
-
-/***************************************************************************
- *GENERAL_STATUS_3 - General status register 3
- ***************************************************************************/
-/* SUN_TOP_CTRL :: GENERAL_STATUS_3 :: cpu_system_counter [31:00] */
-#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_3_cpu_system_counter_MASK 0xffffffff
-#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_3_cpu_system_counter_SHIFT 0
-
-/***************************************************************************
- *GENERAL_STATUS_4 - General status register 4
- ***************************************************************************/
-/* SUN_TOP_CTRL :: GENERAL_STATUS_4 :: cpu_system_counter [31:00] */
-#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_4_cpu_system_counter_MASK 0xffffffff
-#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_4_cpu_system_counter_SHIFT 0
-
-/***************************************************************************
- *PIN_MUX_CTRL_0 - Pinmux control register 0
- ***************************************************************************/
-/* SUN_TOP_CTRL :: PIN_MUX_CTRL_0 :: aon_ir_in0 [31:28] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_aon_ir_in0_MASK 0xf0000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_aon_ir_in0_SHIFT 28
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_aon_ir_in0_DEFAULT 0x00000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_aon_ir_in0_AON_IR_IN0 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_aon_ir_in0_TSPI_S0_MOSI 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_aon_ir_in0_ALT_TP_IN_12 2
-
-/* SUN_TOP_CTRL :: PIN_MUX_CTRL_0 :: gpio_137 [27:24] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_137_MASK 0x0f000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_137_SHIFT 24
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_137_DEFAULT 0x00000001
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_137_GPIO_137 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_137_SC0_SPU 1
-
-/* SUN_TOP_CTRL :: PIN_MUX_CTRL_0 :: gpio_136 [23:20] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_136_MASK 0x00f00000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_136_SHIFT 20
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_136_DEFAULT 0x00000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_136_GPIO_136 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_136_SC0_AUX2 1
-
-/* SUN_TOP_CTRL :: PIN_MUX_CTRL_0 :: gpio_135 [19:16] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_135_MASK 0x000f0000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_135_SHIFT 16
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_135_DEFAULT 0x00000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_135_GPIO_135 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_135_SC0_AUX1 1
-
-/* SUN_TOP_CTRL :: PIN_MUX_CTRL_0 :: gpio_134 [15:12] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_134_MASK 0x0000f000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_134_SHIFT 12
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_134_DEFAULT 0x00000001
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_134_GPIO_134 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_134_SC0_IO 1
-
-/* SUN_TOP_CTRL :: PIN_MUX_CTRL_0 :: gpio_133 [11:08] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_133_MASK 0x00000f00
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_133_SHIFT 8
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_133_DEFAULT 0x00000001
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_133_GPIO_133 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_133_SC0_CLK 1
-
-/* SUN_TOP_CTRL :: PIN_MUX_CTRL_0 :: gpio_132 [07:04] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_132_MASK 0x000000f0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_132_SHIFT 4
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_132_DEFAULT 0x00000001
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_132_GPIO_132 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_132_SC0_RST 1
-
-/* SUN_TOP_CTRL :: PIN_MUX_CTRL_0 :: gpio_131 [03:00] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_131_MASK 0x0000000f
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_131_SHIFT 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_131_DEFAULT 0x00000001
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_131_GPIO_131 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_131_SC0_PRES 1
-
-/***************************************************************************
- *PIN_MUX_CTRL_1 - Pinmux control register 1
- ***************************************************************************/
-/* SUN_TOP_CTRL :: PIN_MUX_CTRL_1 :: ebi_data_06 [31:28] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_ebi_data_06_MASK 0xf0000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_ebi_data_06_SHIFT 28
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_ebi_data_06_DEFAULT 0x00000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_ebi_data_06_EBI_DATA_06 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_ebi_data_06_TP_IN_06 1
-
-/* SUN_TOP_CTRL :: PIN_MUX_CTRL_1 :: ebi_data_05 [27:24] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_ebi_data_05_MASK 0x0f000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_ebi_data_05_SHIFT 24
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_ebi_data_05_DEFAULT 0x00000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_ebi_data_05_EBI_DATA_05 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_ebi_data_05_TP_IN_05 1
-
-/* SUN_TOP_CTRL :: PIN_MUX_CTRL_1 :: ebi_data_04 [23:20] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_ebi_data_04_MASK 0x00f00000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_ebi_data_04_SHIFT 20
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_ebi_data_04_DEFAULT 0x00000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_ebi_data_04_EBI_DATA_04 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_ebi_data_04_TP_IN_04 1
-
-/* SUN_TOP_CTRL :: PIN_MUX_CTRL_1 :: ebi_data_03 [19:16] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_ebi_data_03_MASK 0x000f0000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_ebi_data_03_SHIFT 16
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_ebi_data_03_DEFAULT 0x00000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_ebi_data_03_EBI_DATA_03 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_ebi_data_03_TP_IN_03 1
-
-/* SUN_TOP_CTRL :: PIN_MUX_CTRL_1 :: ebi_data_02 [15:12] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_ebi_data_02_MASK 0x0000f000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_ebi_data_02_SHIFT 12
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_ebi_data_02_DEFAULT 0x00000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_ebi_data_02_EBI_DATA_02 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_ebi_data_02_TP_IN_02 1
-
-/* SUN_TOP_CTRL :: PIN_MUX_CTRL_1 :: ebi_data_01 [11:08] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_ebi_data_01_MASK 0x00000f00
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_ebi_data_01_SHIFT 8
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_ebi_data_01_DEFAULT 0x00000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_ebi_data_01_EBI_DATA_01 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_ebi_data_01_TP_IN_01 1
-
-/* SUN_TOP_CTRL :: PIN_MUX_CTRL_1 :: ebi_data_00 [07:04] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_ebi_data_00_MASK 0x000000f0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_ebi_data_00_SHIFT 4
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_ebi_data_00_DEFAULT 0x00000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_ebi_data_00_EBI_DATA_00 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_ebi_data_00_TP_IN_00 1
-
-/* SUN_TOP_CTRL :: PIN_MUX_CTRL_1 :: ir_out [03:00] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_ir_out_MASK 0x0000000f
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_ir_out_SHIFT 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_ir_out_DEFAULT 0x00000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_ir_out_IR_OUT 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_ir_out_TSPI_S0_SCK 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_ir_out_ALT_TP_OUT_18 2
-
-/***************************************************************************
- *PIN_MUX_CTRL_2 - Pinmux control register 2
- ***************************************************************************/
-/* SUN_TOP_CTRL :: PIN_MUX_CTRL_2 :: ebi_rwb [31:28] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_ebi_rwb_MASK 0xf0000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_ebi_rwb_SHIFT 28
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_ebi_rwb_DEFAULT 0x00000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_ebi_rwb_EBI_RWB 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_ebi_rwb_TP_IN_16 1
-
-/* SUN_TOP_CTRL :: PIN_MUX_CTRL_2 :: ebi_cs5b [27:24] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_ebi_cs5b_MASK 0x0f000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_ebi_cs5b_SHIFT 24
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_ebi_cs5b_DEFAULT 0x00000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_ebi_cs5b_EBI_CS5B 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_ebi_cs5b_EBI_ADDR_14 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_ebi_cs5b_TP_IN_15 2
-
-/* SUN_TOP_CTRL :: PIN_MUX_CTRL_2 :: ebi_cs4b [23:20] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_ebi_cs4b_MASK 0x00f00000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_ebi_cs4b_SHIFT 20
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_ebi_cs4b_DEFAULT 0x00000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_ebi_cs4b_EBI_CS4B 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_ebi_cs4b_EBI_ADDR_13 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_ebi_cs4b_TP_IN_14 2
-
-/* SUN_TOP_CTRL :: PIN_MUX_CTRL_2 :: ebi_cs3b [19:16] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_ebi_cs3b_MASK 0x000f0000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_ebi_cs3b_SHIFT 16
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_ebi_cs3b_DEFAULT 0x00000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_ebi_cs3b_EBI_CS3B 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_ebi_cs3b_TP_IN_13 1
-
-/* SUN_TOP_CTRL :: PIN_MUX_CTRL_2 :: ebi_cs2b [15:12] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_ebi_cs2b_MASK 0x0000f000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_ebi_cs2b_SHIFT 12
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_ebi_cs2b_DEFAULT 0x00000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_ebi_cs2b_EBI_CS2B 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_ebi_cs2b_TP_IN_11 1
-
-/* SUN_TOP_CTRL :: PIN_MUX_CTRL_2 :: ebi_cs1b [11:08] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_ebi_cs1b_MASK 0x00000f00
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_ebi_cs1b_SHIFT 8
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_ebi_cs1b_DEFAULT 0x00000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_ebi_cs1b_EBI_CS1B 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_ebi_cs1b_TP_IN_09 1
-
-/* SUN_TOP_CTRL :: PIN_MUX_CTRL_2 :: ebi_cs0b [07:04] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_ebi_cs0b_MASK 0x000000f0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_ebi_cs0b_SHIFT 4
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_ebi_cs0b_DEFAULT 0x00000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_ebi_cs0b_EBI_CS0B 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_ebi_cs0b_TP_IN_08 1
-
-/* SUN_TOP_CTRL :: PIN_MUX_CTRL_2 :: ebi_data_07 [03:00] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_ebi_data_07_MASK 0x0000000f
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_ebi_data_07_SHIFT 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_ebi_data_07_DEFAULT 0x00000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_ebi_data_07_EBI_DATA_07 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_ebi_data_07_TP_IN_07 1
-
-/***************************************************************************
- *PIN_MUX_CTRL_3 - Pinmux control register 3
- ***************************************************************************/
-/* SUN_TOP_CTRL :: PIN_MUX_CTRL_3 :: ebi_nand_dqs [31:28] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_ebi_nand_dqs_MASK 0xf0000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_ebi_nand_dqs_SHIFT 28
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_ebi_nand_dqs_DEFAULT 0x00000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_ebi_nand_dqs_EBI_NAND_DQS 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_ebi_nand_dqs_TSPI_S3_MOSI 1
-
-/* SUN_TOP_CTRL :: PIN_MUX_CTRL_3 :: ebi_nand_wpb [27:24] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_ebi_nand_wpb_MASK 0x0f000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_ebi_nand_wpb_SHIFT 24
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_ebi_nand_wpb_DEFAULT 0x00000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_ebi_nand_wpb_EBI_NAND_WPB 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_ebi_nand_wpb_TSPI_S3_SS0B 1
-
-/* SUN_TOP_CTRL :: PIN_MUX_CTRL_3 :: ebi_nand_rbb [23:20] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_ebi_nand_rbb_MASK 0x00f00000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_ebi_nand_rbb_SHIFT 20
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_ebi_nand_rbb_DEFAULT 0x00000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_ebi_nand_rbb_EBI_NAND_RBB 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_ebi_nand_rbb_TP_IN_22 1
-
-/* SUN_TOP_CTRL :: PIN_MUX_CTRL_3 :: ebi_dsb [19:16] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_ebi_dsb_MASK 0x000f0000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_ebi_dsb_SHIFT 16
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_ebi_dsb_DEFAULT 0x00000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_ebi_dsb_EBI_DSB 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_ebi_dsb_TP_IN_21 1
-
-/* SUN_TOP_CTRL :: PIN_MUX_CTRL_3 :: ebi_tsb [15:12] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_ebi_tsb_MASK 0x0000f000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_ebi_tsb_SHIFT 12
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_ebi_tsb_DEFAULT 0x00000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_ebi_tsb_EBI_TSB 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_ebi_tsb_TP_IN_20 1
-
-/* SUN_TOP_CTRL :: PIN_MUX_CTRL_3 :: ebi_rdb [11:08] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_ebi_rdb_MASK 0x00000f00
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_ebi_rdb_SHIFT 8
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_ebi_rdb_DEFAULT 0x00000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_ebi_rdb_EBI_RDB 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_ebi_rdb_TP_IN_19 1
-
-/* SUN_TOP_CTRL :: PIN_MUX_CTRL_3 :: ebi_we1b [07:04] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_ebi_we1b_MASK 0x000000f0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_ebi_we1b_SHIFT 4
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_ebi_we1b_DEFAULT 0x00000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_ebi_we1b_EBI_WE1B 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_ebi_we1b_TP_IN_18 1
-
-/* SUN_TOP_CTRL :: PIN_MUX_CTRL_3 :: ebi_we0b [03:00] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_ebi_we0b_MASK 0x0000000f
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_ebi_we0b_SHIFT 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_ebi_we0b_DEFAULT 0x00000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_ebi_we0b_EBI_WE0B 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_ebi_we0b_TP_IN_17 1
-
-/***************************************************************************
- *PIN_MUX_CTRL_4 - Pinmux control register 4
- ***************************************************************************/
-/* SUN_TOP_CTRL :: PIN_MUX_CTRL_4 :: gpio_007 [31:28] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_007_MASK 0xf0000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_007_SHIFT 28
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_007_DEFAULT 0x00000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_007_GPIO_007 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_007_EBI_DATA_15 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_007_SD_CARD1_CLK_IN 2
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_007_SPI_M_MISO 3
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_007_LED_LD_15 4
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_007_CPU_TRACE_DATA11 5
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_007_TP_IN_27 6
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_007_PM_GPIO_007 7
-
-/* SUN_TOP_CTRL :: PIN_MUX_CTRL_4 :: gpio_006 [27:24] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_006_MASK 0x0f000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_006_SHIFT 24
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_006_DEFAULT 0x00000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_006_GPIO_006 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_006_EBI_DATA_14 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_006_SD_CARD1_PRES 2
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_006_SPI_M_SCK 3
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_006_LED_LD_14 4
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_006_CPU_TRACE_DATA10 5
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_006_TP_IN_26 6
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_006_PM_GPIO_006 7
-
-/* SUN_TOP_CTRL :: PIN_MUX_CTRL_4 :: gpio_005 [23:20] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_005_MASK 0x00f00000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_005_SHIFT 20
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_005_DEFAULT 0x00000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_005_GPIO_005 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_005_EBI_DATA_13 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_005_SD_CARD1_DAT3 2
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_005_UART_TXD_2 3
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_005_LED_LD_13 4
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_005_CPU_TRACE_DATA9 5
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_005_VEC_VSYNC 6
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_005_TSPI_S1_MOSI 7
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_005_ALT_TP_OUT_04 8
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_005_PM_GPIO_005 9
-
-/* SUN_TOP_CTRL :: PIN_MUX_CTRL_4 :: gpio_004 [19:16] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_004_MASK 0x000f0000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_004_SHIFT 16
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_004_DEFAULT 0x00000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_004_GPIO_004 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_004_EBI_DATA_12 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_004_SD_CARD1_DAT2 2
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_004_UART_RXD_2 3
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_004_LED_LD_12 4
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_004_CPU_TRACE_DATA8 5
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_004_VEC_HSYNC 6
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_004_TP_IN_25 7
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_004_PM_GPIO_004 8
-
-/* SUN_TOP_CTRL :: PIN_MUX_CTRL_4 :: gpio_003 [15:12] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_003_MASK 0x0000f000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_003_SHIFT 12
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_003_DEFAULT 0x00000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_003_GPIO_003 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_003_EBI_DATA_11 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_003_SD_CARD1_DAT1 2
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_003_UART_TXD_1 3
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_003_LED_LD_11 4
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_003_CPU_TRACE_DATA7 5
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_003_IR_IN1 6
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_003_TSPI_S1_SS0B 7
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_003_ALT_TP_OUT_03 8
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_003_PM_GPIO_003 9
-
-/* SUN_TOP_CTRL :: PIN_MUX_CTRL_4 :: gpio_002 [11:08] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_002_MASK 0x00000f00
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_002_SHIFT 8
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_002_DEFAULT 0x00000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_002_GPIO_002 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_002_EBI_DATA_10 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_002_SD_CARD1_DAT0 2
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_002_UART_RXD_1 3
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_002_LED_LD_10 4
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_002_CPU_TRACE_DATA6 5
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_002_IR_INT 6
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_002_TP_IN_24 7
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_002_PM_GPIO_002 8
-
-/* SUN_TOP_CTRL :: PIN_MUX_CTRL_4 :: gpio_001 [07:04] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_001_MASK 0x000000f0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_001_SHIFT 4
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_001_DEFAULT 0x00000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_001_GPIO_001 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_001_EBI_DATA_09 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_001_SD_CARD1_CLK 2
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_001_UART_TXD_0 3
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_001_LED_LD_9 4
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_001_CPU_TRACE_DATA5 5
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_001_RGMII_A_RX_OK 6
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_001_TSPI_S1_SCK 7
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_001_ALT_TP_OUT_02 8
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_001_PM_GPIO_001 9
-
-/* SUN_TOP_CTRL :: PIN_MUX_CTRL_4 :: gpio_000 [03:00] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_000_MASK 0x0000000f
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_000_SHIFT 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_000_DEFAULT 0x00000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_000_GPIO_000 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_000_EBI_DATA_08 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_000_SD_CARD1_CMD 2
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_000_UART_RXD_0 3
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_000_LED_LD_8 4
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_000_CPU_TRACE_DATA4 5
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_000_RGMII_A_START_STOP 6
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_000_TP_IN_23 7
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_000_PM_GPIO_000 8
-
-/***************************************************************************
- *PIN_MUX_CTRL_5 - Pinmux control register 5
- ***************************************************************************/
-/* SUN_TOP_CTRL :: PIN_MUX_CTRL_5 :: gpio_015 [31:28] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_015_MASK 0xf0000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_015_SHIFT 28
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_015_DEFAULT 0x00000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_015_GPIO_015 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_015_EBI_ADDR_09 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_015_PKT_ERROR0 2
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_015_CHIP2POD_SCTL1 3
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_015_RMX_SYNC0 4
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_015_ENET1_ACTIVITY 5
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_015_TP_OUT_31 6
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_015_PM_GPIO_015 7
-
-/* SUN_TOP_CTRL :: PIN_MUX_CTRL_5 :: gpio_014 [27:24] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_014_MASK 0x0f000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_014_SHIFT 24
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_014_DEFAULT 0x00000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_014_GPIO_014 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_014_EBI_ADDR_08 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_014_PKT_SYNC0 2
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_014_CHIP2POD_SDO1 3
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_014_RMX_DATA0 4
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_014_ENET1_LINK 5
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_014_TP_OUT_30 6
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_014_PM_GPIO_014 7
-
-/* SUN_TOP_CTRL :: PIN_MUX_CTRL_5 :: gpio_013 [23:20] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_013_MASK 0x00f00000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_013_SHIFT 20
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_013_DEFAULT 0x00000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_013_GPIO_013 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_013_EBI_ADDR_07 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_013_PKT_DATA0 2
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_013_POD2CHIP_SDI1 3
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_013_RMX_CLK0 4
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_013_ENET0_ACTIVITY 5
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_013_TSPI_S2_SS0B 6
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_013_ALT_TP_IN_02 7
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_013_PM_GPIO_013 8
-
-/* SUN_TOP_CTRL :: PIN_MUX_CTRL_5 :: gpio_012 [19:16] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_012_MASK 0x000f0000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_012_SHIFT 16
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_012_DEFAULT 0x00000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_012_GPIO_012 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_012_EBI_ADDR_06 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_012_PKT_CLK0 2
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_012_CHIP2POD_SCLK1 3
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_012_ENET0_LINK 4
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_012_TSPI_S2_SCK 5
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_012_ALT_TP_IN_01 6
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_012_PM_GPIO_012 7
-
-/* SUN_TOP_CTRL :: PIN_MUX_CTRL_5 :: gpio_011 [15:12] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_011_MASK 0x0000f000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_011_SHIFT 12
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_011_DEFAULT 0x00000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_011_GPIO_011 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_011_EBI_ADDR_05 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_011_SD_CARD1_VOLT 2
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_011_PWM2 3
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_011_CPU_TRACE_DATA15 4
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_011_TSPI_S1_MISO 5
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_011_ALT_TP_OUT_10 6
-
-/* SUN_TOP_CTRL :: PIN_MUX_CTRL_5 :: gpio_010 [11:08] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_010_MASK 0x00000f00
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_010_SHIFT 8
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_010_DEFAULT 0x00000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_010_GPIO_010 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_010_EBI_ADDR_04 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_010_SD_CARD1_LED 2
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_010_SPI_M_SS1B 3
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_010_PWM3 4
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_010_CPU_TRACE_DATA14 5
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_010_TSPI_S2_MOSI 6
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_010_ALT_TP_IN_00 7
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_010_PM_GPIO_010 8
-
-/* SUN_TOP_CTRL :: PIN_MUX_CTRL_5 :: gpio_009 [07:04] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_009_MASK 0x000000f0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_009_SHIFT 4
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_009_DEFAULT 0x00000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_009_GPIO_009 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_009_EBI_ADDR_03 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_009_SD_CARD1_PWR0 2
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_009_SPI_M_SS0B 3
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_009_PWM0 4
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_009_CPU_TRACE_DATA13 5
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_009_TP_IN_31 6
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_009_PM_GPIO_009 7
-
-/* SUN_TOP_CTRL :: PIN_MUX_CTRL_5 :: gpio_008 [03:00] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_008_MASK 0x0000000f
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_008_SHIFT 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_008_DEFAULT 0x00000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_008_GPIO_008 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_008_EBI_WAITB 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_008_SD_CARD1_WPROT 2
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_008_SPI_M_MOSI 3
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_008_PWM1 4
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_008_CPU_TRACE_DATA12 5
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_008_TP_IN_28 6
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_008_PM_GPIO_008 7
-
-/***************************************************************************
- *PIN_MUX_CTRL_6 - Pinmux control register 6
- ***************************************************************************/
-/* SUN_TOP_CTRL :: PIN_MUX_CTRL_6 :: gpio_023 [31:28] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_023_MASK 0xf0000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_023_SHIFT 28
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_023_DEFAULT 0x00000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_023_GPIO_023 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_023_MTSIF1_RX_DATA2 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_023_MTSIF1_TX_DATA2 2
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_023_PKT_CLK1_ALT2 3
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_023_PM_GPIO_023 4
-
-/* SUN_TOP_CTRL :: PIN_MUX_CTRL_6 :: gpio_022 [27:24] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_022_MASK 0x0f000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_022_SHIFT 24
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_022_DEFAULT 0x00000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_022_GPIO_022 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_022_PKT_VALID0_ALT2 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_022_ENET2_ACTIVITY 2
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_022_ENET0_ACTIVITY 3
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_022_PM_GPIO_022 4
-
-/* SUN_TOP_CTRL :: PIN_MUX_CTRL_6 :: gpio_021 [23:20] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_021_MASK 0x00f00000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_021_SHIFT 20
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_021_DEFAULT 0x00000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_021_GPIO_021 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_021_MTSIF1_RX_DATA1 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_021_MTSIF1_TX_DATA1 2
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_021_PKT_ERROR0_ALT2 3
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_021_PM_GPIO_021 4
-
-/* SUN_TOP_CTRL :: PIN_MUX_CTRL_6 :: gpio_020 [19:16] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_020_MASK 0x000f0000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_020_SHIFT 16
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_020_DEFAULT 0x00000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_020_GPIO_020 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_020_MTSIF1_RX_SYNC 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_020_MTSIF1_TX_SYNC 2
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_020_PKT_SYNC0_ALT2 3
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_020_PM_GPIO_020 4
-
-/* SUN_TOP_CTRL :: PIN_MUX_CTRL_6 :: gpio_019 [15:12] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_019_MASK 0x0000f000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_019_SHIFT 12
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_019_DEFAULT 0x00000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_019_GPIO_019 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_019_MTSIF1_RX_DATA0 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_019_MTSIF1_TX_DATA0 2
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_019_PKT_DATA0_ALT2 3
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_019_PM_GPIO_019 4
-
-/* SUN_TOP_CTRL :: PIN_MUX_CTRL_6 :: gpio_018 [11:08] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_018_MASK 0x00000f00
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_018_SHIFT 8
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_018_DEFAULT 0x00000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_018_GPIO_018 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_018_MTSIF1_RX_CLK 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_018_MTSIF1_TX_CLK 2
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_018_PKT_CLK0_ALT2 3
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_018_PM_GPIO_018 4
-
-/* SUN_TOP_CTRL :: PIN_MUX_CTRL_6 :: gpio_017 [07:04] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_017_MASK 0x000000f0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_017_SHIFT 4
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_017_DEFAULT 0x00000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_017_GPIO_017 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_017_EBI_ADDR_11 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_017_MTSIF_ATS_INC 2
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_017_TSIO_VCTRL 3
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_017_RMX_PAUSE0 4
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_017_ENET2_ACTIVITY 5
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_017_DEMOD_MTSIF_ATS_INC 6
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_017_ALT_TP_IN_16 7
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_017_PM_GPIO_017 8
-
-/* SUN_TOP_CTRL :: PIN_MUX_CTRL_6 :: gpio_016 [03:00] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_016_MASK 0x0000000f
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_016_SHIFT 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_016_DEFAULT 0x00000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_016_GPIO_016 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_016_EBI_ADDR_10 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_016_PKT_VALID0 2
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_016_MTSIF_ATS_RST 3
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_016_RMX_VALID0 4
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_016_ENET2_LINK 5
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_016_DEMOD_MTSIF_ATS_RST 6
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_016_TP_OUT_27 7
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_016_PM_GPIO_016 8
-
-/***************************************************************************
- *PIN_MUX_CTRL_7 - Pinmux control register 7
- ***************************************************************************/
-/* SUN_TOP_CTRL :: PIN_MUX_CTRL_7 :: gpio_031 [31:28] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_031_MASK 0xf0000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_031_SHIFT 28
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_031_DEFAULT 0x00000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_031_GPIO_031 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_031_CHIP2POD_MCLKO 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_031_RMXP_CLK 2
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_031_EBI_ADDR_15 3
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_031_ALT_TP_IN_03 4
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_031_PM_GPIO_031 5
-
-/* SUN_TOP_CTRL :: PIN_MUX_CTRL_7 :: gpio_030 [27:24] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_030_MASK 0x0f000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_030_SHIFT 24
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_030_DEFAULT 0x00000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_030_GPIO_030 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_030_POD2CHIP_MCLKI 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_030_PPKT_CLK 2
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_030_EBI_ADDR_14 3
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_030_ALT_TP_OUT_17 4
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_030_PM_GPIO_030 5
-
-/* SUN_TOP_CTRL :: PIN_MUX_CTRL_7 :: gpio_029 [23:20] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_029_MASK 0x00f00000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_029_SHIFT 20
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_029_DEFAULT 0x00000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_029_GPIO_029 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_029_PWM0 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_029_ENET0_ACTIVITY 2
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_029_IR_IN1 3
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_029_PM_GPIO_029 4
-
-/* SUN_TOP_CTRL :: PIN_MUX_CTRL_7 :: gpio_028 [19:16] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_028_MASK 0x000f0000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_028_SHIFT 16
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_028_DEFAULT 0x00000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_028_GPIO_028 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_028_MTSIF1_RX_DATA7 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_028_MTSIF1_TX_DATA7 2
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_028_ENET0_LINK 3
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_028_PM_GPIO_028 4
-
-/* SUN_TOP_CTRL :: PIN_MUX_CTRL_7 :: gpio_027 [15:12] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_027_MASK 0x0000f000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_027_SHIFT 12
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_027_DEFAULT 0x00000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_027_GPIO_027 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_027_MTSIF1_RX_DATA6 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_027_MTSIF1_TX_DATA6 2
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_027_PKT_VALID1_ALT2 3
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_027_PM_GPIO_027 4
-
-/* SUN_TOP_CTRL :: PIN_MUX_CTRL_7 :: gpio_026 [11:08] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_026_MASK 0x00000f00
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_026_SHIFT 8
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_026_DEFAULT 0x00000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_026_GPIO_026 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_026_MTSIF1_RX_DATA5 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_026_MTSIF1_TX_DATA5 2
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_026_PKT_ERROR1_ALT2 3
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_026_PM_GPIO_026 4
-
-/* SUN_TOP_CTRL :: PIN_MUX_CTRL_7 :: gpio_025 [07:04] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_025_MASK 0x000000f0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_025_SHIFT 4
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_025_DEFAULT 0x00000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_025_GPIO_025 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_025_MTSIF1_RX_DATA4 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_025_MTSIF1_TX_DATA4 2
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_025_PKT_SYNC1_ALT2 3
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_025_PM_GPIO_025 4
-
-/* SUN_TOP_CTRL :: PIN_MUX_CTRL_7 :: gpio_024 [03:00] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_024_MASK 0x0000000f
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_024_SHIFT 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_024_DEFAULT 0x00000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_024_GPIO_024 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_024_MTSIF1_RX_DATA3 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_024_MTSIF1_TX_DATA3 2
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_024_PKT_DATA1_ALT2 3
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_024_PM_GPIO_024 4
-
-/***************************************************************************
- *PIN_MUX_CTRL_8 - Pinmux control register 8
- ***************************************************************************/
-/* SUN_TOP_CTRL :: PIN_MUX_CTRL_8 :: gpio_039 [31:28] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_039_MASK 0xf0000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_039_SHIFT 28
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_039_DEFAULT 0x00000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_039_GPIO_039 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_039_POD2CHIP_MDI1 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_039_PPKT_DATA1 2
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_039_UART_RXD_1 3
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_039_ALT_TP_IN_10 4
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_039_PM_GPIO_039 5
-
-/* SUN_TOP_CTRL :: PIN_MUX_CTRL_8 :: gpio_038 [27:24] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_038_MASK 0x0f000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_038_SHIFT 24
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_038_DEFAULT 0x00000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_038_GPIO_038 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_038_POD2CHIP_MDI0 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_038_PPKT_DATA0 2
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_038_UART_TXD_0 3
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_038_ALT_TP_OUT_11 4
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_038_PM_GPIO_038 5
-
-/* SUN_TOP_CTRL :: PIN_MUX_CTRL_8 :: gpio_037 [23:20] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_037_MASK 0x00f00000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_037_SHIFT 20
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_037_DEFAULT 0x00000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_037_GPIO_037 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_037_POD2CHIP_MIVAL 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_037_PPKT_VALID 2
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_037_UART_RXD_0 3
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_037_ALT_TP_IN_09 4
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_037_PM_GPIO_037 5
-
-/* SUN_TOP_CTRL :: PIN_MUX_CTRL_8 :: gpio_036 [19:16] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_036_MASK 0x000f0000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_036_SHIFT 16
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_036_DEFAULT 0x00000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_036_GPIO_036 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_036_POD2CHIP_MISTRT 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_036_PPKT_SYNC 2
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_036_ALT_TP_IN_08 3
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_036_PM_GPIO_036 4
-
-/* SUN_TOP_CTRL :: PIN_MUX_CTRL_8 :: gpio_035 [15:12] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_035_MASK 0x0000f000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_035_SHIFT 12
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_035_DEFAULT 0x00000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_035_GPIO_035 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_035_CHIP2POD_SCTL0 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_035_SPI_M_SS0B 2
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_035_EBI_ADDR_02 3
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_035_VEC_VSYNC 4
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_035_ALT_TP_IN_07 5
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_035_PM_GPIO_035 6
-
-/* SUN_TOP_CTRL :: PIN_MUX_CTRL_8 :: gpio_034 [11:08] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_034_MASK 0x00000f00
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_034_SHIFT 8
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_034_DEFAULT 0x00000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_034_GPIO_034 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_034_CHIP2POD_SDO0 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_034_SPI_M_MOSI 2
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_034_EBI_ADDR_00 3
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_034_VEC_HSYNC 4
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_034_ALT_TP_IN_06 5
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_034_PM_GPIO_034 6
-
-/* SUN_TOP_CTRL :: PIN_MUX_CTRL_8 :: gpio_033 [07:04] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_033_MASK 0x000000f0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_033_SHIFT 4
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_033_DEFAULT 0x00000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_033_GPIO_033 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_033_POD2CHIP_SDI0 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_033_SPI_M_MISO 2
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_033_ALT_TP_IN_05 3
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_033_PM_GPIO_033 4
-
-/* SUN_TOP_CTRL :: PIN_MUX_CTRL_8 :: gpio_032 [03:00] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_032_MASK 0x0000000f
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_032_SHIFT 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_032_DEFAULT 0x00000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_032_GPIO_032 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_032_CHIP2POD_SCLK0 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_032_SPI_M_SCK 2
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_032_EBI_ADDR_01 3
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_032_ALT_TP_IN_04 4
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_032_PM_GPIO_032 5
-
-/***************************************************************************
- *PIN_MUX_CTRL_9 - Pinmux control register 9
- ***************************************************************************/
-/* SUN_TOP_CTRL :: PIN_MUX_CTRL_9 :: gpio_047 [31:28] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_047_MASK 0xf0000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_047_SHIFT 28
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_047_DEFAULT 0x00000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_047_GPIO_047 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_047_CHIP2POD_MOVAL 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_047_RMXP_VALID 2
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_047_EBI_ADDR_16 3
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_047_SC1_VCC 4
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_047_ALT_TP_IN_22 5
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_047_PM_GPIO_047 6
-
-/* SUN_TOP_CTRL :: PIN_MUX_CTRL_9 :: gpio_046 [27:24] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_046_MASK 0x0f000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_046_SHIFT 24
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_046_DEFAULT 0x00000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_046_GPIO_046 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_046_POD2CHIP_MICLK 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_046_PPKT_CLK 2
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_046_EBI_ADDR_13 3
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_046_POD2CHIP_MCLKI 4
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_046_ALT_TP_IN_21 5
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_046_PM_GPIO_046 6
-
-/* SUN_TOP_CTRL :: PIN_MUX_CTRL_9 :: gpio_045 [23:20] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_045_MASK 0x00f00000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_045_SHIFT 20
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_045_DEFAULT 0x00000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_045_GPIO_045 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_045_POD2CHIP_MDI7 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_045_PPKT_DATA7 2
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_045_ALT_TP_IN_20 3
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_045_PM_GPIO_045 4
-
-/* SUN_TOP_CTRL :: PIN_MUX_CTRL_9 :: gpio_044 [19:16] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_044_MASK 0x000f0000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_044_SHIFT 16
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_044_DEFAULT 0x00000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_044_GPIO_044 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_044_POD2CHIP_MDI6 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_044_PPKT_DATA6 2
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_044_ALT_TP_IN_19 3
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_044_PM_GPIO_044 4
-
-/* SUN_TOP_CTRL :: PIN_MUX_CTRL_9 :: gpio_043 [15:12] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_043_MASK 0x0000f000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_043_SHIFT 12
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_043_DEFAULT 0x00000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_043_GPIO_043 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_043_POD2CHIP_MDI5 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_043_PPKT_DATA5 2
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_043_ALT_TP_IN_18 3
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_043_PM_GPIO_043 4
-
-/* SUN_TOP_CTRL :: PIN_MUX_CTRL_9 :: gpio_042 [11:08] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_042_MASK 0x00000f00
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_042_SHIFT 8
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_042_DEFAULT 0x00000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_042_GPIO_042 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_042_POD2CHIP_MDI4 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_042_PPKT_DATA4 2
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_042_UART_TXD_2 3
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_042_ALT_TP_OUT_13 4
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_042_PM_GPIO_042 5
-
-/* SUN_TOP_CTRL :: PIN_MUX_CTRL_9 :: gpio_041 [07:04] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_041_MASK 0x000000f0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_041_SHIFT 4
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_041_DEFAULT 0x00000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_041_GPIO_041 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_041_POD2CHIP_MDI3 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_041_PPKT_DATA3 2
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_041_UART_RXD_2 3
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_041_ALT_TP_IN_11 4
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_041_PM_GPIO_041 5
-
-/* SUN_TOP_CTRL :: PIN_MUX_CTRL_9 :: gpio_040 [03:00] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_040_MASK 0x0000000f
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_040_SHIFT 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_040_DEFAULT 0x00000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_040_GPIO_040 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_040_POD2CHIP_MDI2 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_040_PPKT_DATA2 2
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_040_UART_TXD_1 3
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_040_ALT_TP_OUT_12 4
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_040_PM_GPIO_040 5
-
-/***************************************************************************
- *PIN_MUX_CTRL_10 - Pinmux control register 10
- ***************************************************************************/
-/* SUN_TOP_CTRL :: PIN_MUX_CTRL_10 :: gpio_055 [31:28] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_055_MASK 0xf0000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_055_SHIFT 28
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_055_DEFAULT 0x00000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_055_GPIO_055 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_055_CHIP2POD_MDO6 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_055_RMXP_DATA6 2
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_055_EBI_ADDR_24 3
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_055_ALT_TP_IN_30 4
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_055_PM_GPIO_055 5
-
-/* SUN_TOP_CTRL :: PIN_MUX_CTRL_10 :: gpio_054 [27:24] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_054_MASK 0x0f000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_054_SHIFT 24
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_054_DEFAULT 0x00000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_054_GPIO_054 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_054_CHIP2POD_MDO5 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_054_RMXP_DATA5 2
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_054_EBI_ADDR_23 3
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_054_SC1_VPP 4
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_054_ALT_TP_IN_29 5
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_054_PM_GPIO_054 6
-
-/* SUN_TOP_CTRL :: PIN_MUX_CTRL_10 :: gpio_053 [23:20] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_053_MASK 0x00f00000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_053_SHIFT 20
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_053_DEFAULT 0x00000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_053_GPIO_053 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_053_CHIP2POD_MDO4 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_053_RMXP_DATA4 2
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_053_EBI_ADDR_22 3
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_053_SC1_AUX2 4
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_053_ALT_TP_IN_28 5
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_053_PM_GPIO_053 6
-
-/* SUN_TOP_CTRL :: PIN_MUX_CTRL_10 :: gpio_052 [19:16] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_052_MASK 0x000f0000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_052_SHIFT 16
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_052_DEFAULT 0x00000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_052_GPIO_052 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_052_CHIP2POD_MDO3 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_052_RMXP_DATA3 2
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_052_EBI_ADDR_21 3
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_052_SC1_AUX1 4
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_052_EXT_IRQB_7 5
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_052_ALT_TP_IN_27 6
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_052_PM_GPIO_052 7
-
-/* SUN_TOP_CTRL :: PIN_MUX_CTRL_10 :: gpio_051 [15:12] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_051_MASK 0x0000f000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_051_SHIFT 12
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_051_DEFAULT 0x00000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_051_GPIO_051 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_051_CHIP2POD_MDO2 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_051_RMXP_DATA2 2
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_051_EBI_ADDR_20 3
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_051_SC1_PRES 4
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_051_EXT_IRQB_6 5
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_051_ALT_TP_IN_26 6
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_051_PM_GPIO_051 7
-
-/* SUN_TOP_CTRL :: PIN_MUX_CTRL_10 :: gpio_050 [11:08] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_050_MASK 0x00000f00
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_050_SHIFT 8
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_050_DEFAULT 0x00000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_050_GPIO_050 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_050_CHIP2POD_MDO1 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_050_RMXP_DATA1 2
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_050_EBI_ADDR_19 3
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_050_SC1_IO 4
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_050_EXT_IRQB_5 5
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_050_ALT_TP_IN_25 6
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_050_PM_GPIO_050 7
-
-/* SUN_TOP_CTRL :: PIN_MUX_CTRL_10 :: gpio_049 [07:04] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_049_MASK 0x000000f0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_049_SHIFT 4
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_049_DEFAULT 0x00000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_049_GPIO_049 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_049_CHIP2POD_MDO0 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_049_RMXP_DATA0 2
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_049_EBI_ADDR_18 3
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_049_SC1_RST 4
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_049_EXT_IRQB_4 5
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_049_ALT_TP_IN_24 6
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_049_PM_GPIO_049 7
-
-/* SUN_TOP_CTRL :: PIN_MUX_CTRL_10 :: gpio_048 [03:00] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_048_MASK 0x0000000f
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_048_SHIFT 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_048_DEFAULT 0x00000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_048_GPIO_048 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_048_CHIP2POD_MOSTRT 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_048_RMXP_SYNC 2
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_048_EBI_ADDR_17 3
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_048_SC1_CLK 4
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_048_ALT_TP_IN_23 5
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_048_PM_GPIO_048 6
-
-/***************************************************************************
- *PIN_MUX_CTRL_11 - Pinmux control register 11
- ***************************************************************************/
-/* SUN_TOP_CTRL :: PIN_MUX_CTRL_11 :: gpio_063 [31:28] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_063_MASK 0xf0000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_063_SHIFT 28
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_063_DEFAULT 0x00000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_063_GPIO_063 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_063_SC0_AUX1 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_063_I2S_CLK0_OUT 2
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_063_I2S_CLK0_IN 3
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_063_TP_OUT_22 4
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_063_PM_GPIO_063 5
-
-/* SUN_TOP_CTRL :: PIN_MUX_CTRL_11 :: gpio_062 [27:24] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_062_MASK 0x0f000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_062_SHIFT 24
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_062_DEFAULT 0x00000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_062_GPIO_062 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_062_SC0_PRES 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_062_TP_OUT_21 2
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_062_PM_GPIO_062 3
-
-/* SUN_TOP_CTRL :: PIN_MUX_CTRL_11 :: gpio_061 [23:20] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_061_MASK 0x00f00000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_061_SHIFT 20
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_061_DEFAULT 0x00000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_061_GPIO_061 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_061_SC0_IO 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_061_IR_IN1 2
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_061_TP_OUT_20 3
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_061_PM_GPIO_061 4
-
-/* SUN_TOP_CTRL :: PIN_MUX_CTRL_11 :: gpio_060 [19:16] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_060_MASK 0x000f0000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_060_SHIFT 16
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_060_DEFAULT 0x00000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_060_GPIO_060 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_060_SC0_RST 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_060_IR_INT 2
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_060_TP_OUT_19 3
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_060_PM_GPIO_060 4
-
-/* SUN_TOP_CTRL :: PIN_MUX_CTRL_11 :: gpio_059 [15:12] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_059_MASK 0x0000f000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_059_SHIFT 12
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_059_DEFAULT 0x00000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_059_GPIO_059 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_059_SC0_CLK 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_059_TP_OUT_18 2
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_059_PM_GPIO_059 3
-
-/* SUN_TOP_CTRL :: PIN_MUX_CTRL_11 :: gpio_058 [11:08] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_058_MASK 0x00000f00
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_058_SHIFT 8
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_058_DEFAULT 0x00000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_058_GPIO_058 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_058_SC0_VCC 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_058_TEST_THP 2
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_058_TP_OUT_17 3
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_058_PM_GPIO_058 4
-
-/* SUN_TOP_CTRL :: PIN_MUX_CTRL_11 :: gpio_057 [07:04] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_057_MASK 0x000000f0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_057_SHIFT 4
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_057_DEFAULT 0x00000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_057_GPIO_057 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_057_CHIP2POD_MOCLK 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_057_RMXP_CLK 2
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_057_EBI_ADDR_12 3
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_057_CHIP2POD_MCLKO 4
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_057_ALT_TP_OUT_16 5
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_057_PM_GPIO_057 6
-
-/* SUN_TOP_CTRL :: PIN_MUX_CTRL_11 :: gpio_056 [03:00] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_056_MASK 0x0000000f
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_056_SHIFT 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_056_DEFAULT 0x00000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_056_GPIO_056 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_056_CHIP2POD_MDO7 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_056_RMXP_DATA7 2
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_056_EBI_ADDR_25 3
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_056_ALT_TP_IN_15 4
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_056_PM_GPIO_056 5
-
-/***************************************************************************
- *PIN_MUX_CTRL_12 - Pinmux control register 12
- ***************************************************************************/
-/* SUN_TOP_CTRL :: PIN_MUX_CTRL_12 :: gpio_071 [31:28] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_071_MASK 0xf0000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_071_SHIFT 28
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_071_DEFAULT 0x00000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_071_GPIO_071 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_071_MTSIF0_RX_DATA2 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_071_PKT_CLK3 2
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_071_UART_RTS_1 3
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_071_EXT_IRQB_4 4
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_071_ALT_TP_OUT_26 5
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_071_PM_GPIO_071 6
-
-/* SUN_TOP_CTRL :: PIN_MUX_CTRL_12 :: gpio_070 [27:24] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_070_MASK 0x0f000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_070_SHIFT 24
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_070_DEFAULT 0x00000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_070_GPIO_070 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_070_PKT_VALID2 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_070_UART_CTS_1 2
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_070_EXT_IRQB_3 3
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_070_ENET2_LINK 4
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_070_ENET0_LINK 5
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_070_ALT_TP_OUT_25 6
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_070_PM_GPIO_070 7
-
-/* SUN_TOP_CTRL :: PIN_MUX_CTRL_12 :: gpio_069 [23:20] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_069_MASK 0x00f00000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_069_SHIFT 20
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_069_DEFAULT 0x00000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_069_GPIO_069 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_069_MTSIF0_RX_DATA1 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_069_PKT_ERROR2 2
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_069_UART_TXD_0 3
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_069_IR_IN1 4
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_069_ALT_TP_OUT_19 5
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_069_PM_GPIO_069 6
-
-/* SUN_TOP_CTRL :: PIN_MUX_CTRL_12 :: gpio_068 [19:16] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_068_MASK 0x000f0000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_068_SHIFT 16
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_068_DEFAULT 0x00000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_068_GPIO_068 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_068_MTSIF0_RX_SYNC 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_068_PKT_SYNC2 2
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_068_UART_RXD_0 3
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_068_EXT_IRQB_2 4
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_068_ALT_TP_IN_17 5
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_068_PM_GPIO_068 6
-
-/* SUN_TOP_CTRL :: PIN_MUX_CTRL_12 :: gpio_067 [15:12] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_067_MASK 0x0000f000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_067_SHIFT 12
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_067_DEFAULT 0x00000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_067_GPIO_067 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_067_MTSIF0_RX_DATA0 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_067_PKT_DATA2 2
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_067_UART_RTS_0 3
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_067_EXT_IRQB_1 4
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_067_ALT_TP_OUT_24 5
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_067_PM_GPIO_067 6
-
-/* SUN_TOP_CTRL :: PIN_MUX_CTRL_12 :: gpio_066 [11:08] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_066_MASK 0x00000f00
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_066_SHIFT 8
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_066_DEFAULT 0x00000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_066_GPIO_066 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_066_MTSIF0_RX_CLK 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_066_PKT_CLK2 2
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_066_UART_CTS_0 3
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_066_EXT_IRQB_0 4
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_066_ALT_TP_OUT_23 5
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_066_PM_GPIO_066 6
-
-/* SUN_TOP_CTRL :: PIN_MUX_CTRL_12 :: gpio_065 [07:04] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_065_MASK 0x000000f0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_065_SHIFT 4
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_065_DEFAULT 0x00000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_065_GPIO_065 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_065_SC0_VPP 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_065_I2S_LR0_OUT 2
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_065_I2S_LR0_IN 3
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_065_TP_OUT_24 4
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_065_PM_GPIO_065 5
-
-/* SUN_TOP_CTRL :: PIN_MUX_CTRL_12 :: gpio_064 [03:00] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_064_MASK 0x0000000f
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_064_SHIFT 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_064_DEFAULT 0x00000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_064_GPIO_064 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_064_SC0_AUX2 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_064_I2S_DATA0_OUT 2
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_064_I2S_DATA0_IN 3
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_064_TP_OUT_23 4
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_064_PM_GPIO_064 5
-
-/***************************************************************************
- *PIN_MUX_CTRL_13 - Pinmux control register 13
- ***************************************************************************/
-/* SUN_TOP_CTRL :: PIN_MUX_CTRL_13 :: gpio_079 [31:28] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_079_MASK 0xf0000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_079_SHIFT 28
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_079_DEFAULT 0x00000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_079_GPIO_079 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_079_RGMII_A_RX_CLK 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_079_PKT_CLK0_ALT 2
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_079_VO0_656_0 3
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_079_IR_IN1 4
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_079_PM_GPIO_079 5
-
-/* SUN_TOP_CTRL :: PIN_MUX_CTRL_13 :: gpio_078 [27:24] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_078_MASK 0x0f000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_078_SHIFT 24
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_078_DEFAULT 0x00000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_078_GPIO_078 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_078_MTSIF_ATS_RST 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_078_DEMOD_MTSIF_ATS_RST 2
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_078_ALT_TP_OUT_22 3
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_078_PM_GPIO_078 4
-
-/* SUN_TOP_CTRL :: PIN_MUX_CTRL_13 :: gpio_077 [23:20] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_077_MASK 0x00f00000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_077_SHIFT 20
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_077_DEFAULT 0x00000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_077_GPIO_077 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_077_MTSIF_ATS_INC 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_077_DEMOD_MTSIF_ATS_INC 2
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_077_UART_RTS_2 3
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_077_ALT_TP_OUT_21 4
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_077_PM_GPIO_077 5
-
-/* SUN_TOP_CTRL :: PIN_MUX_CTRL_13 :: gpio_076 [19:16] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_076_MASK 0x000f0000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_076_SHIFT 16
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_076_DEFAULT 0x00000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_076_GPIO_076 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_076_MTSIF0_RX_DATA7 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_076_PKT_VALID2 2
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_076_UART_CTS_2 3
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_076_ALT_TP_OUT_20 4
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_076_PM_GPIO_076 5
-
-/* SUN_TOP_CTRL :: PIN_MUX_CTRL_13 :: gpio_075 [15:12] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_075_MASK 0x0000f000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_075_SHIFT 12
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_075_DEFAULT 0x00000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_075_GPIO_075 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_075_MTSIF0_RX_DATA6 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_075_PKT_VALID3 2
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_075_UART_TXD_2 3
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_075_ALT_TP_OUT_15 4
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_075_PM_GPIO_075 5
-
-/* SUN_TOP_CTRL :: PIN_MUX_CTRL_13 :: gpio_074 [11:08] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_074_MASK 0x00000f00
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_074_SHIFT 8
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_074_DEFAULT 0x00000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_074_GPIO_074 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_074_MTSIF0_RX_DATA5 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_074_PKT_ERROR3 2
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_074_UART_RXD_2 3
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_074_ALT_TP_IN_14 4
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_074_PM_GPIO_074 5
-
-/* SUN_TOP_CTRL :: PIN_MUX_CTRL_13 :: gpio_073 [07:04] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_073_MASK 0x000000f0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_073_SHIFT 4
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_073_DEFAULT 0x00000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_073_GPIO_073 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_073_MTSIF0_RX_DATA4 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_073_PKT_SYNC3 2
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_073_UART_TXD_1 3
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_073_ALT_TP_OUT_14 4
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_073_PM_GPIO_073 5
-
-/* SUN_TOP_CTRL :: PIN_MUX_CTRL_13 :: gpio_072 [03:00] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_072_MASK 0x0000000f
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_072_SHIFT 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_072_DEFAULT 0x00000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_072_GPIO_072 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_072_MTSIF0_RX_DATA3 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_072_PKT_DATA3 2
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_072_UART_RXD_1 3
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_072_EXT_IRQB_5 4
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_072_ALT_TP_IN_13 5
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_072_PM_GPIO_072 6
-
-/***************************************************************************
- *PIN_MUX_CTRL_14 - Pinmux control register 14
- ***************************************************************************/
-/* SUN_TOP_CTRL :: PIN_MUX_CTRL_14 :: gpio_087 [31:28] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_087_MASK 0xf0000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_087_SHIFT 28
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_087_DEFAULT 0x00000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_087_GPIO_087 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_087_RGMII_A_TXD_00 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_087_PKT_ERROR1 2
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_087_VO0_656_CLK 3
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_087_UART_RXD_2 4
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_087_PM_GPIO_087 5
-
-/* SUN_TOP_CTRL :: PIN_MUX_CTRL_14 :: gpio_086 [27:24] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_086_MASK 0x0f000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_086_SHIFT 24
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_086_DEFAULT 0x00000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_086_GPIO_086 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_086_RGMII_A_TX_EN_CTL 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_086_PKT_SYNC1 2
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_086_VO0_656_7 3
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_086_UART_RTS_1 4
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_086_PM_GPIO_086 5
-
-/* SUN_TOP_CTRL :: PIN_MUX_CTRL_14 :: gpio_085 [23:20] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_085_MASK 0x00f00000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_085_SHIFT 20
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_085_DEFAULT 0x00000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_085_GPIO_085 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_085_RGMII_A_TX_CLK 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_085_PKT_DATA1 2
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_085_VO0_656_6 3
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_085_UART_CTS_1 4
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_085_PM_GPIO_085 5
-
-/* SUN_TOP_CTRL :: PIN_MUX_CTRL_14 :: gpio_084 [19:16] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_084_MASK 0x000f0000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_084_SHIFT 16
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_084_DEFAULT 0x00000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_084_GPIO_084 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_084_RGMII_A_RXD_03 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_084_PKT_CLK1 2
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_084_VO0_656_5 3
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_084_UART_TXD_1 4
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_084_PM_GPIO_084 5
-
-/* SUN_TOP_CTRL :: PIN_MUX_CTRL_14 :: gpio_083 [15:12] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_083_MASK 0x0000f000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_083_SHIFT 12
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_083_DEFAULT 0x00000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_083_GPIO_083 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_083_RGMII_A_RXD_02 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_083_PKT_VALID0_ALT 2
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_083_VO0_656_4 3
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_083_UART_RXD_1 4
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_083_PM_GPIO_083 5
-
-/* SUN_TOP_CTRL :: PIN_MUX_CTRL_14 :: gpio_082 [11:08] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_082_MASK 0x00000f00
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_082_SHIFT 8
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_082_DEFAULT 0x00000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_082_GPIO_082 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_082_RGMII_A_RXD_01 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_082_PKT_ERROR0_ALT 2
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_082_VO0_656_3 3
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_082_UART_RTS_0 4
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_082_PM_GPIO_082 5
-
-/* SUN_TOP_CTRL :: PIN_MUX_CTRL_14 :: gpio_081 [07:04] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_081_MASK 0x000000f0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_081_SHIFT 4
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_081_DEFAULT 0x00000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_081_GPIO_081 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_081_RGMII_A_RXD_00 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_081_PKT_SYNC0_ALT 2
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_081_VO0_656_2 3
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_081_UART_CTS_0 4
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_081_PM_GPIO_081 5
-
-/* SUN_TOP_CTRL :: PIN_MUX_CTRL_14 :: gpio_080 [03:00] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_080_MASK 0x0000000f
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_080_SHIFT 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_080_DEFAULT 0x00000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_080_GPIO_080 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_080_RGMII_A_RX_EN_CTL 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_080_PKT_DATA0_ALT 2
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_080_VO0_656_1 3
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_080_PM_GPIO_080 4
-
-/***************************************************************************
- *PIN_MUX_CTRL_15 - Pinmux control register 15
- ***************************************************************************/
-/* SUN_TOP_CTRL :: PIN_MUX_CTRL_15 :: gpio_095 [31:28] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_095_MASK 0xf0000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_095_SHIFT 28
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_095_DEFAULT 0x00000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_095_GPIO_095 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_095_RGMIIA_IRQ 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_095_SPI_M_SCK 2
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_095_I2S_LR0_OUT 3
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_095_RMX_SYNC0 4
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_095_ALT_TP_OUT_29 5
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_095_PM_GPIO_095 6
-
-/* SUN_TOP_CTRL :: PIN_MUX_CTRL_15 :: gpio_094 [27:24] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_094_MASK 0x0f000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_094_SHIFT 24
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_094_DEFAULT 0x00000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_094_GPIO_094 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_094_MII_A_TX_ERR 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_094_SPI_M_SS0B 2
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_094_I2S_DATA0_OUT 3
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_094_RMX_DATA0 4
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_094_ENET0_ACTIVITY 5
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_094_SDS_BERT_DATA 6
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_094_ALT_TP_OUT_28 7
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_094_PM_GPIO_094 8
-
-/* SUN_TOP_CTRL :: PIN_MUX_CTRL_15 :: gpio_093 [23:20] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_093_MASK 0x00f00000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_093_SHIFT 20
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_093_DEFAULT 0x00000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_093_GPIO_093 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_093_MII_A_RX_ERR 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_093_SPI_M_MOSI 2
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_093_I2S_CLK0_OUT 3
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_093_RMX_CLK0 4
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_093_ENET0_LINK 5
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_093_SDS_BERT_CLK 6
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_093_ALT_TP_OUT_27 7
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_093_PM_GPIO_093 8
-
-/* SUN_TOP_CTRL :: PIN_MUX_CTRL_15 :: gpio_092 [19:16] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_092_MASK 0x000f0000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_092_SHIFT 16
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_092_DEFAULT 0x00000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_092_GPIO_092 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_092_RGMII_A_MDC 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_092_UART_TXD_0 2
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_092_PM_GPIO_092 3
-
-/* SUN_TOP_CTRL :: PIN_MUX_CTRL_15 :: gpio_091 [15:12] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_091_MASK 0x0000f000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_091_SHIFT 12
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_091_DEFAULT 0x00000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_091_GPIO_091 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_091_RGMII_A_MDIO 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_091_UART_RXD_0 2
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_091_PM_GPIO_091 3
-
-/* SUN_TOP_CTRL :: PIN_MUX_CTRL_15 :: gpio_090 [11:08] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_090_MASK 0x00000f00
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_090_SHIFT 8
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_090_DEFAULT 0x00000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_090_GPIO_090 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_090_RGMII_A_TXD_03 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_090_VEC_VSYNC 2
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_090_UART_RTS_2 3
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_090_PM_GPIO_090 4
-
-/* SUN_TOP_CTRL :: PIN_MUX_CTRL_15 :: gpio_089 [07:04] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_089_MASK 0x000000f0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_089_SHIFT 4
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_089_DEFAULT 0x00000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_089_GPIO_089 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_089_RGMII_A_TXD_02 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_089_VEC_HSYNC 2
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_089_TTX0_REQ 3
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_089_UART_CTS_2 4
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_089_PM_GPIO_089 5
-
-/* SUN_TOP_CTRL :: PIN_MUX_CTRL_15 :: gpio_088 [03:00] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_088_MASK 0x0000000f
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_088_SHIFT 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_088_DEFAULT 0x00000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_088_GPIO_088 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_088_RGMII_A_TXD_01 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_088_PKT_VALID1 2
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_088_TTX0_DATA 3
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_088_UART_TXD_2 4
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_088_PM_GPIO_088 5
-
-/***************************************************************************
- *PIN_MUX_CTRL_16 - Pinmux control register 16
- ***************************************************************************/
-/* SUN_TOP_CTRL :: PIN_MUX_CTRL_16 :: gpio_103 [31:28] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_103_MASK 0xf0000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_103_SHIFT 28
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_103_DEFAULT 0x00000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_103_GPIO_103 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_103_SD_CARD0_DAT3 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_103_UART_RTS_1 2
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_103_EXT_IRQB_4 3
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_103_CPU_TRACE_DATA3 4
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_103_TP_OUT_29 5
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_103_PM_GPIO_103 6
-
-/* SUN_TOP_CTRL :: PIN_MUX_CTRL_16 :: gpio_102 [27:24] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_102_MASK 0x0f000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_102_SHIFT 24
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_102_DEFAULT 0x00000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_102_GPIO_102 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_102_SD_CARD0_DAT2 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_102_PKT_VALID1_ALT 2
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_102_UART_CTS_1 3
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_102_EXT_IRQB_3 4
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_102_CPU_TRACE_DATA2 5
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_102_TP_OUT_28 6
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_102_PM_GPIO_102 7
-
-/* SUN_TOP_CTRL :: PIN_MUX_CTRL_16 :: gpio_101 [23:20] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_101_MASK 0x00f00000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_101_SHIFT 20
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_101_DEFAULT 0x00000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_101_GPIO_101 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_101_SD_CARD0_DAT1 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_101_PKT_ERROR1_ALT 2
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_101_UART_TXD_1 3
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_101_EXT_IRQB_2 4
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_101_CPU_TRACE_DATA1 5
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_101_TSPI_S3_SCK 6
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_101_ALT_TP_OUT_05 7
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_101_PM_GPIO_101 8
-
-/* SUN_TOP_CTRL :: PIN_MUX_CTRL_16 :: gpio_100 [19:16] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_100_MASK 0x000f0000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_100_SHIFT 16
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_100_DEFAULT 0x00000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_100_GPIO_100 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_100_SD_CARD0_DAT0 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_100_PKT_SYNC1_ALT 2
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_100_UART_RXD_1 3
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_100_EXT_IRQB_1 4
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_100_CPU_TRACE_DATA0 5
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_100_TP_IN_30 6
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_100_PM_GPIO_100 7
-
-/* SUN_TOP_CTRL :: PIN_MUX_CTRL_16 :: gpio_099 [15:12] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_099_MASK 0x0000f000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_099_SHIFT 12
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_099_DEFAULT 0x00000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_099_GPIO_099 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_099_SD_CARD0_CLK 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_099_PKT_DATA1_ALT 2
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_099_UART_RTS_0 3
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_099_EXT_IRQB_0 4
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_099_CPU_TRACE_CLK 5
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_099_TP_OUT_26 6
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_099_PM_GPIO_099 7
-
-/* SUN_TOP_CTRL :: PIN_MUX_CTRL_16 :: gpio_098 [11:08] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_098_MASK 0x00000f00
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_098_SHIFT 8
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_098_DEFAULT 0x00000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_098_GPIO_098 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_098_SD_CARD0_CMD 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_098_PKT_CLK1_ALT 2
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_098_UART_CTS_0 3
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_098_EXT_IRQB_5 4
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_098_TP_OUT_25 5
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_098_PM_GPIO_098 6
-
-/* SUN_TOP_CTRL :: PIN_MUX_CTRL_16 :: gpio_097 [07:04] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_097_MASK 0x000000f0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_097_SHIFT 4
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_097_DEFAULT 0x00000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_097_GPIO_097 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_097_MII_A_COL 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_097_EXT_SC_CLK 2
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_097_SPI_M_SS1B 3
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_097_ENET1_ACTIVITY 4
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_097_RMX_PAUSE0 5
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_097_MTSIF_ATS_RST 6
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_097_DEMOD_MTSIF_ATS_RST 7
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_097_ALT_TP_OUT_31 8
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_097_PM_GPIO_097 9
-
-/* SUN_TOP_CTRL :: PIN_MUX_CTRL_16 :: gpio_096 [03:00] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_096_MASK 0x0000000f
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_096_SHIFT 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_096_DEFAULT 0x00000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_096_GPIO_096 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_096_MII_A_CRS 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_096_SC_CLK_OUT 2
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_096_SPI_M_MISO 3
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_096_ENET1_LINK 4
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_096_RMX_VALID0 5
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_096_MTSIF_ATS_INC 6
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_096_DEMOD_MTSIF_ATS_INC 7
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_096_ALT_TP_OUT_30 8
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_096_PM_GPIO_096 9
-
-/***************************************************************************
- *PIN_MUX_CTRL_17 - Pinmux control register 17
- ***************************************************************************/
-/* SUN_TOP_CTRL :: PIN_MUX_CTRL_17 :: gpio_111 [31:28] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_111_MASK 0xf0000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_111_SHIFT 28
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_111_DEFAULT 0x00000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_111_GPIO_111 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_111_UART_RXD_0 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_111_EXT_SC_CLK 2
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_111_AUD_FS_CLK0 3
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_111_SPI_S_SS0B 4
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_111_ALT_TP_IN_31 5
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_111_PM_GPIO_111 6
-
-/* SUN_TOP_CTRL :: PIN_MUX_CTRL_17 :: gpio_110 [27:24] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_110_MASK 0x0f000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_110_SHIFT 24
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_110_DEFAULT 0x00000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_110_GPIO_110 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_110_UART_TXD_0 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_110_SC_CLK_OUT 2
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_110_IR_INT 3
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_110_SPI_S_MISO 4
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_110_ALT_TP_OUT_07 5
-
-/* SUN_TOP_CTRL :: PIN_MUX_CTRL_17 :: gpio_109 [23:20] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_109_MASK 0x00f00000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_109_SHIFT 20
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_109_DEFAULT 0x00000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_109_GPIO_109 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_109_SD_CARD0_VOLT 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_109_TSPI_S3_MISO 2
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_109_ALT_TP_OUT_09 3
-
-/* SUN_TOP_CTRL :: PIN_MUX_CTRL_17 :: gpio_108 [19:16] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_108_MASK 0x000f0000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_108_SHIFT 16
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_108_DEFAULT 0x00000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_108_GPIO_108 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_108_SD_CARD0_PWR0 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_108_RMX_VALID1 2
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_108_PWM2 3
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_108_TSPI_S2_MISO 4
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_108_ALT_TP_OUT_08 5
-
-/* SUN_TOP_CTRL :: PIN_MUX_CTRL_17 :: gpio_107 [15:12] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_107_MASK 0x0000f000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_107_SHIFT 12
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_107_DEFAULT 0x00000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_107_GPIO_107 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_107_SD_CARD0_WPROT 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_107_RMX_PAUSE1 2
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_107_UART_RTS_2 3
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_107_PWM3 4
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_107_TP_OUT_05 5
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_107_PM_GPIO_107 6
-
-/* SUN_TOP_CTRL :: PIN_MUX_CTRL_17 :: gpio_106 [11:08] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_106_MASK 0x00000f00
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_106_SHIFT 8
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_106_DEFAULT 0x00000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_106_GPIO_106 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_106_SD_CARD0_CLK_IN 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_106_RMX_SYNC1 2
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_106_UART_CTS_2 3
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_106_PWM0 4
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_106_SATA_MDIO 5
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_106_TP_OUT_04 6
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_106_PM_GPIO_106 7
-
-/* SUN_TOP_CTRL :: PIN_MUX_CTRL_17 :: gpio_105 [07:04] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_105_MASK 0x000000f0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_105_SHIFT 4
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_105_DEFAULT 0x00000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_105_GPIO_105 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_105_SD_CARD0_LED 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_105_RMX_DATA1 2
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_105_UART_TXD_2 3
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_105_PWM1 4
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_105_AUD_FS_CLK0 5
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_105_SC_CLK_OUT 6
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_105_SATA_MDCLK 7
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_105_ALT_TP_OUT_06 8
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_105_PM_GPIO_105 9
-
-/* SUN_TOP_CTRL :: PIN_MUX_CTRL_17 :: gpio_104 [03:00] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_104_MASK 0x0000000f
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_104_SHIFT 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_104_DEFAULT 0x00000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_104_GPIO_104 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_104_SD_CARD0_PRES 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_104_RMX_CLK1 2
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_104_UART_RXD_2 3
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_104_IR_IN1 4
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_104_TP_IN_29 5
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_104_PM_GPIO_104 6
-
-/***************************************************************************
- *PIN_MUX_CTRL_18 - Pinmux control register 18
- ***************************************************************************/
-/* SUN_TOP_CTRL :: PIN_MUX_CTRL_18 :: gpio_119 [31:28] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_gpio_119_MASK 0xf0000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_gpio_119_SHIFT 28
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_gpio_119_DEFAULT 0x00000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_gpio_119_GPIO_119 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_gpio_119_RGMII_A_TX_EN_CTL 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_gpio_119_VO0_656_7 2
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_gpio_119_UART_RTS_1 3
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_gpio_119_PM_GPIO_119 4
-
-/* SUN_TOP_CTRL :: PIN_MUX_CTRL_18 :: gpio_118 [27:24] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_gpio_118_MASK 0x0f000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_gpio_118_SHIFT 24
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_gpio_118_DEFAULT 0x00000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_gpio_118_GPIO_118 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_gpio_118_RGMII_A_TX_CLK 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_gpio_118_VO0_656_6 2
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_gpio_118_UART_CTS_1 3
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_gpio_118_PM_GPIO_118 4
-
-/* SUN_TOP_CTRL :: PIN_MUX_CTRL_18 :: gpio_117 [23:20] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_gpio_117_MASK 0x00f00000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_gpio_117_SHIFT 20
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_gpio_117_DEFAULT 0x00000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_gpio_117_GPIO_117 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_gpio_117_RGMII_A_RXD_03 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_gpio_117_VO0_656_5 2
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_gpio_117_UART_TXD_1 3
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_gpio_117_PM_GPIO_117 4
-
-/* SUN_TOP_CTRL :: PIN_MUX_CTRL_18 :: gpio_116 [19:16] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_gpio_116_MASK 0x000f0000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_gpio_116_SHIFT 16
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_gpio_116_DEFAULT 0x00000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_gpio_116_GPIO_116 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_gpio_116_RGMII_A_RXD_02 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_gpio_116_VO0_656_4 2
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_gpio_116_UART_RXD_1 3
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_gpio_116_PM_GPIO_116 4
-
-/* SUN_TOP_CTRL :: PIN_MUX_CTRL_18 :: gpio_115 [15:12] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_gpio_115_MASK 0x0000f000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_gpio_115_SHIFT 12
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_gpio_115_DEFAULT 0x00000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_gpio_115_GPIO_115 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_gpio_115_RGMII_A_RXD_01 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_gpio_115_VO0_656_3 2
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_gpio_115_UART_RTS_0 3
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_gpio_115_PM_GPIO_115 4
-
-/* SUN_TOP_CTRL :: PIN_MUX_CTRL_18 :: gpio_114 [11:08] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_gpio_114_MASK 0x00000f00
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_gpio_114_SHIFT 8
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_gpio_114_DEFAULT 0x00000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_gpio_114_GPIO_114 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_gpio_114_RGMII_A_RXD_00 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_gpio_114_VO0_656_2 2
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_gpio_114_UART_CTS_0 3
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_gpio_114_PM_GPIO_114 4
-
-/* SUN_TOP_CTRL :: PIN_MUX_CTRL_18 :: gpio_113 [07:04] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_gpio_113_MASK 0x000000f0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_gpio_113_SHIFT 4
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_gpio_113_DEFAULT 0x00000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_gpio_113_GPIO_113 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_gpio_113_RGMII_A_RX_EN_CTL 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_gpio_113_VO0_656_1 2
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_gpio_113_PM_GPIO_113 3
-
-/* SUN_TOP_CTRL :: PIN_MUX_CTRL_18 :: gpio_112 [03:00] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_gpio_112_MASK 0x0000000f
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_gpio_112_SHIFT 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_gpio_112_DEFAULT 0x00000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_gpio_112_GPIO_112 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_gpio_112_RGMII_A_RX_CLK 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_gpio_112_VO0_656_0 2
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_gpio_112_IR_IN1 3
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_gpio_112_PM_GPIO_112 4
-
-/***************************************************************************
- *PIN_MUX_CTRL_19 - Pinmux control register 19
- ***************************************************************************/
-/* SUN_TOP_CTRL :: PIN_MUX_CTRL_19 :: gpio_127 [31:28] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_19_gpio_127_MASK 0xf0000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_19_gpio_127_SHIFT 28
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_19_gpio_127_DEFAULT 0x00000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_19_gpio_127_GPIO_127 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_19_gpio_127_MII_A_TX_ERR 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_19_gpio_127_SPI_M_SS0B 2
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_19_gpio_127_I2S_DATA0_OUT 3
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_19_gpio_127_ENET0_ACTIVITY 4
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_19_gpio_127_PM_GPIO_127 5
-
-/* SUN_TOP_CTRL :: PIN_MUX_CTRL_19 :: gpio_126 [27:24] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_19_gpio_126_MASK 0x0f000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_19_gpio_126_SHIFT 24
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_19_gpio_126_DEFAULT 0x00000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_19_gpio_126_GPIO_126 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_19_gpio_126_MII_A_RX_ERR 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_19_gpio_126_SPI_M_MOSI 2
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_19_gpio_126_I2S_CLK0_OUT 3
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_19_gpio_126_ENET0_LINK 4
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_19_gpio_126_PM_GPIO_126 5
-
-/* SUN_TOP_CTRL :: PIN_MUX_CTRL_19 :: gpio_125 [23:20] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_19_gpio_125_MASK 0x00f00000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_19_gpio_125_SHIFT 20
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_19_gpio_125_DEFAULT 0x00000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_19_gpio_125_GPIO_125 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_19_gpio_125_RGMII_A_MDC 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_19_gpio_125_SPI_S_SS0B 2
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_19_gpio_125_UART_TXD_0 3
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_19_gpio_125_PM_GPIO_125 4
-
-/* SUN_TOP_CTRL :: PIN_MUX_CTRL_19 :: gpio_124 [19:16] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_19_gpio_124_MASK 0x000f0000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_19_gpio_124_SHIFT 16
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_19_gpio_124_DEFAULT 0x00000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_19_gpio_124_GPIO_124 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_19_gpio_124_RGMII_A_MDIO 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_19_gpio_124_SPI_S_MISO 2
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_19_gpio_124_UART_RXD_0 3
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_19_gpio_124_PM_GPIO_124 4
-
-/* SUN_TOP_CTRL :: PIN_MUX_CTRL_19 :: gpio_123 [15:12] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_19_gpio_123_MASK 0x0000f000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_19_gpio_123_SHIFT 12
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_19_gpio_123_DEFAULT 0x00000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_19_gpio_123_GPIO_123 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_19_gpio_123_RGMII_A_TXD_03 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_19_gpio_123_VEC_VSYNC 2
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_19_gpio_123_UART_RTS_2 3
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_19_gpio_123_PM_GPIO_123 4
-
-/* SUN_TOP_CTRL :: PIN_MUX_CTRL_19 :: gpio_122 [11:08] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_19_gpio_122_MASK 0x00000f00
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_19_gpio_122_SHIFT 8
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_19_gpio_122_DEFAULT 0x00000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_19_gpio_122_GPIO_122 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_19_gpio_122_RGMII_A_TXD_02 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_19_gpio_122_VEC_HSYNC 2
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_19_gpio_122_UART_CTS_2 3
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_19_gpio_122_TTX0_REQ 4
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_19_gpio_122_PM_GPIO_122 5
-
-/* SUN_TOP_CTRL :: PIN_MUX_CTRL_19 :: gpio_121 [07:04] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_19_gpio_121_MASK 0x000000f0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_19_gpio_121_SHIFT 4
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_19_gpio_121_DEFAULT 0x00000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_19_gpio_121_GPIO_121 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_19_gpio_121_RGMII_A_TXD_01 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_19_gpio_121_UART_TXD_2 2
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_19_gpio_121_TTX0_DATA 3
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_19_gpio_121_PM_GPIO_121 4
-
-/* SUN_TOP_CTRL :: PIN_MUX_CTRL_19 :: gpio_120 [03:00] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_19_gpio_120_MASK 0x0000000f
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_19_gpio_120_SHIFT 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_19_gpio_120_DEFAULT 0x00000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_19_gpio_120_GPIO_120 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_19_gpio_120_RGMII_A_TXD_00 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_19_gpio_120_VO0_656_CLK 2
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_19_gpio_120_UART_RXD_2 3
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_19_gpio_120_PM_GPIO_120 4
-
-/***************************************************************************
- *PIN_MUX_CTRL_20 - Pinmux control register 20
- ***************************************************************************/
-/* SUN_TOP_CTRL :: PIN_MUX_CTRL_20 :: sgpio_04 [31:28] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_20_sgpio_04_MASK 0xf0000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_20_sgpio_04_SHIFT 28
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_20_sgpio_04_DEFAULT 0x00000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_20_sgpio_04_SGPIO_04 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_20_sgpio_04_MOCA_BSC_SCL 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_20_sgpio_04_BSC_M6_SCL 2
-
-/* SUN_TOP_CTRL :: PIN_MUX_CTRL_20 :: sgpio_03 [27:24] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_20_sgpio_03_MASK 0x0f000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_20_sgpio_03_SHIFT 24
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_20_sgpio_03_DEFAULT 0x00000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_20_sgpio_03_SGPIO_03 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_20_sgpio_03_BSC_M5_SDA 1
-
-/* SUN_TOP_CTRL :: PIN_MUX_CTRL_20 :: sgpio_02 [23:20] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_20_sgpio_02_MASK 0x00f00000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_20_sgpio_02_SHIFT 20
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_20_sgpio_02_DEFAULT 0x00000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_20_sgpio_02_SGPIO_02 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_20_sgpio_02_BSC_M5_SCL 1
-
-/* SUN_TOP_CTRL :: PIN_MUX_CTRL_20 :: sgpio_01 [19:16] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_20_sgpio_01_MASK 0x000f0000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_20_sgpio_01_SHIFT 16
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_20_sgpio_01_DEFAULT 0x00000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_20_sgpio_01_SGPIO_01 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_20_sgpio_01_BSC_M4_SDA 1
-
-/* SUN_TOP_CTRL :: PIN_MUX_CTRL_20 :: sgpio_00 [15:12] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_20_sgpio_00_MASK 0x0000f000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_20_sgpio_00_SHIFT 12
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_20_sgpio_00_DEFAULT 0x00000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_20_sgpio_00_SGPIO_00 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_20_sgpio_00_BSC_M4_SCL 1
-
-/* SUN_TOP_CTRL :: PIN_MUX_CTRL_20 :: gpio_130 [11:08] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_20_gpio_130_MASK 0x00000f00
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_20_gpio_130_SHIFT 8
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_20_gpio_130_DEFAULT 0x00000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_20_gpio_130_GPIO_130 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_20_gpio_130_MII_A_COL 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_20_gpio_130_SPI_M_SS1B 2
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_20_gpio_130_MTSIF_ATS_RST 3
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_20_gpio_130_DEMOD_MTSIF_ATS_RST 4
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_20_gpio_130_ENET1_ACTIVITY 5
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_20_gpio_130_PM_GPIO_130 6
-
-/* SUN_TOP_CTRL :: PIN_MUX_CTRL_20 :: gpio_129 [07:04] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_20_gpio_129_MASK 0x000000f0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_20_gpio_129_SHIFT 4
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_20_gpio_129_DEFAULT 0x00000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_20_gpio_129_GPIO_129 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_20_gpio_129_MII_A_CRS 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_20_gpio_129_SPI_M_MISO 2
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_20_gpio_129_MTSIF_ATS_INC 3
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_20_gpio_129_DEMOD_MTSIF_ATS_INC 4
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_20_gpio_129_ENET1_LINK 5
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_20_gpio_129_PM_GPIO_129 6
-
-/* SUN_TOP_CTRL :: PIN_MUX_CTRL_20 :: gpio_128 [03:00] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_20_gpio_128_MASK 0x0000000f
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_20_gpio_128_SHIFT 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_20_gpio_128_DEFAULT 0x00000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_20_gpio_128_GPIO_128 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_20_gpio_128_RGMIIA_IRQ 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_20_gpio_128_SPI_M_SCK 2
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_20_gpio_128_I2S_LR0_OUT 3
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_20_gpio_128_PM_GPIO_128 4
-
-/***************************************************************************
- *PIN_MUX_CTRL_21 - Pinmux control register 21
- ***************************************************************************/
-/* SUN_TOP_CTRL :: PIN_MUX_CTRL_21 :: reserved0 [31:12] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_21_reserved0_MASK 0xfffff000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_21_reserved0_SHIFT 12
-
-/* SUN_TOP_CTRL :: PIN_MUX_CTRL_21 :: byp_clk_1 [11:08] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_21_byp_clk_1_MASK 0x00000f00
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_21_byp_clk_1_SHIFT 8
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_21_byp_clk_1_DEFAULT 0x00000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_21_byp_clk_1_BYP_CLK_1 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_21_byp_clk_1_OBSRV_CLK_1 1
-
-/* SUN_TOP_CTRL :: PIN_MUX_CTRL_21 :: byp_clk_0 [07:04] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_21_byp_clk_0_MASK 0x000000f0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_21_byp_clk_0_SHIFT 4
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_21_byp_clk_0_DEFAULT 0x00000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_21_byp_clk_0_BYP_CLK_0 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_21_byp_clk_0_OBSRV_CLK_0 1
-
-/* SUN_TOP_CTRL :: PIN_MUX_CTRL_21 :: sgpio_05 [03:00] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_21_sgpio_05_MASK 0x0000000f
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_21_sgpio_05_SHIFT 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_21_sgpio_05_DEFAULT 0x00000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_21_sgpio_05_SGPIO_05 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_21_sgpio_05_MOCA_BSC_SDA 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_21_sgpio_05_BSC_M6_SDA 2
-
-/***************************************************************************
- *PIN_MUX_PAD_CTRL_0 - Pad pull-up/pull-down control register 0
- ***************************************************************************/
-/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_0 :: spare_pad_ctrl_0 [31:30] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_spare_pad_ctrl_0_MASK 0xc0000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_spare_pad_ctrl_0_SHIFT 30
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_spare_pad_ctrl_0_DEFAULT 0x00000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_spare_pad_ctrl_0_PULL_NONE 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_spare_pad_ctrl_0_PULL_DOWN 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_spare_pad_ctrl_0_PULL_UP 2
-
-/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_0 :: reserved0 [29:28] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_reserved0_MASK 0x30000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_reserved0_SHIFT 28
-
-/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_0 :: pcie_clkreqb_pad_ctrl [27:26] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_pcie_clkreqb_pad_ctrl_MASK 0x0c000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_pcie_clkreqb_pad_ctrl_SHIFT 26
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_pcie_clkreqb_pad_ctrl_DEFAULT 0x00000002
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_pcie_clkreqb_pad_ctrl_PULL_NONE 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_pcie_clkreqb_pad_ctrl_PULL_DOWN 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_pcie_clkreqb_pad_ctrl_PULL_UP 2
-
-/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_0 :: pcie_rstb_pad_ctrl [25:24] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_pcie_rstb_pad_ctrl_MASK 0x03000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_pcie_rstb_pad_ctrl_SHIFT 24
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_pcie_rstb_pad_ctrl_DEFAULT 0x00000001
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_pcie_rstb_pad_ctrl_PULL_NONE 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_pcie_rstb_pad_ctrl_PULL_DOWN 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_pcie_rstb_pad_ctrl_PULL_UP 2
-
-/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_0 :: reserved1 [23:00] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_reserved1_MASK 0x00ffffff
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_reserved1_SHIFT 0
-
-/***************************************************************************
- *PIN_MUX_PAD_CTRL_1 - Pad pull-up/pull-down control register 1
- ***************************************************************************/
-/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_1 :: spare_pad_ctrl_1 [31:30] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_spare_pad_ctrl_1_MASK 0xc0000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_spare_pad_ctrl_1_SHIFT 30
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_spare_pad_ctrl_1_DEFAULT 0x00000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_spare_pad_ctrl_1_PULL_NONE 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_spare_pad_ctrl_1_PULL_DOWN 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_spare_pad_ctrl_1_PULL_UP 2
-
-/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_1 :: emmc_cmd_pad_ctrl [29:28] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_emmc_cmd_pad_ctrl_MASK 0x30000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_emmc_cmd_pad_ctrl_SHIFT 28
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_emmc_cmd_pad_ctrl_DEFAULT 0x00000002
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_emmc_cmd_pad_ctrl_PULL_NONE 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_emmc_cmd_pad_ctrl_PULL_DOWN 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_emmc_cmd_pad_ctrl_PULL_UP 2
-
-/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_1 :: sf_wpb_pad_ctrl [27:26] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_sf_wpb_pad_ctrl_MASK 0x0c000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_sf_wpb_pad_ctrl_SHIFT 26
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_sf_wpb_pad_ctrl_DEFAULT 0x00000002
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_sf_wpb_pad_ctrl_PULL_NONE 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_sf_wpb_pad_ctrl_PULL_DOWN 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_sf_wpb_pad_ctrl_PULL_UP 2
-
-/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_1 :: sf_holdb_pad_ctrl [25:24] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_sf_holdb_pad_ctrl_MASK 0x03000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_sf_holdb_pad_ctrl_SHIFT 24
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_sf_holdb_pad_ctrl_DEFAULT 0x00000002
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_sf_holdb_pad_ctrl_PULL_NONE 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_sf_holdb_pad_ctrl_PULL_DOWN 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_sf_holdb_pad_ctrl_PULL_UP 2
-
-/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_1 :: sf_mosi_pad_ctrl [23:22] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_sf_mosi_pad_ctrl_MASK 0x00c00000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_sf_mosi_pad_ctrl_SHIFT 22
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_sf_mosi_pad_ctrl_DEFAULT 0x00000002
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_sf_mosi_pad_ctrl_PULL_NONE 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_sf_mosi_pad_ctrl_PULL_DOWN 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_sf_mosi_pad_ctrl_PULL_UP 2
-
-/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_1 :: sf_miso_pad_ctrl [21:20] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_sf_miso_pad_ctrl_MASK 0x00300000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_sf_miso_pad_ctrl_SHIFT 20
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_sf_miso_pad_ctrl_DEFAULT 0x00000002
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_sf_miso_pad_ctrl_PULL_NONE 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_sf_miso_pad_ctrl_PULL_DOWN 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_sf_miso_pad_ctrl_PULL_UP 2
-
-/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_1 :: sf_sck_pad_ctrl [19:18] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_sf_sck_pad_ctrl_MASK 0x000c0000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_sf_sck_pad_ctrl_SHIFT 18
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_sf_sck_pad_ctrl_DEFAULT 0x00000002
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_sf_sck_pad_ctrl_PULL_NONE 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_sf_sck_pad_ctrl_PULL_DOWN 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_sf_sck_pad_ctrl_PULL_UP 2
-
-/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_1 :: reserved0 [17:10] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_reserved0_MASK 0x0003fc00
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_reserved0_SHIFT 10
-
-/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_1 :: pcie1_clkreqb_pad_ctrl [09:08] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_pcie1_clkreqb_pad_ctrl_MASK 0x00000300
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_pcie1_clkreqb_pad_ctrl_SHIFT 8
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_pcie1_clkreqb_pad_ctrl_DEFAULT 0x00000002
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_pcie1_clkreqb_pad_ctrl_PULL_NONE 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_pcie1_clkreqb_pad_ctrl_PULL_DOWN 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_pcie1_clkreqb_pad_ctrl_PULL_UP 2
-
-/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_1 :: pcie1_rstb_pad_ctrl [07:06] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_pcie1_rstb_pad_ctrl_MASK 0x000000c0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_pcie1_rstb_pad_ctrl_SHIFT 6
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_pcie1_rstb_pad_ctrl_DEFAULT 0x00000001
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_pcie1_rstb_pad_ctrl_PULL_NONE 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_pcie1_rstb_pad_ctrl_PULL_DOWN 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_pcie1_rstb_pad_ctrl_PULL_UP 2
-
-/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_1 :: reserved1 [05:00] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_reserved1_MASK 0x0000003f
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_reserved1_SHIFT 0
-
-/***************************************************************************
- *PIN_MUX_PAD_CTRL_2 - Pad pull-up/pull-down control register 2
- ***************************************************************************/
-/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_2 :: spare_pad_ctrl_2 [31:30] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_spare_pad_ctrl_2_MASK 0xc0000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_spare_pad_ctrl_2_SHIFT 30
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_spare_pad_ctrl_2_DEFAULT 0x00000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_spare_pad_ctrl_2_PULL_NONE 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_spare_pad_ctrl_2_PULL_DOWN 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_spare_pad_ctrl_2_PULL_UP 2
-
-/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_2 :: ebi_cs5b_pad_ctrl [29:28] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_ebi_cs5b_pad_ctrl_MASK 0x30000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_ebi_cs5b_pad_ctrl_SHIFT 28
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_ebi_cs5b_pad_ctrl_DEFAULT 0x00000002
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_ebi_cs5b_pad_ctrl_PULL_NONE 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_ebi_cs5b_pad_ctrl_PULL_DOWN 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_ebi_cs5b_pad_ctrl_PULL_UP 2
-
-/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_2 :: ebi_cs4b_pad_ctrl [27:26] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_ebi_cs4b_pad_ctrl_MASK 0x0c000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_ebi_cs4b_pad_ctrl_SHIFT 26
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_ebi_cs4b_pad_ctrl_DEFAULT 0x00000002
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_ebi_cs4b_pad_ctrl_PULL_NONE 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_ebi_cs4b_pad_ctrl_PULL_DOWN 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_ebi_cs4b_pad_ctrl_PULL_UP 2
-
-/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_2 :: ebi_cs3b_pad_ctrl [25:24] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_ebi_cs3b_pad_ctrl_MASK 0x03000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_ebi_cs3b_pad_ctrl_SHIFT 24
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_ebi_cs3b_pad_ctrl_DEFAULT 0x00000002
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_ebi_cs3b_pad_ctrl_PULL_NONE 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_ebi_cs3b_pad_ctrl_PULL_DOWN 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_ebi_cs3b_pad_ctrl_PULL_UP 2
-
-/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_2 :: ebi_cs2b_pad_ctrl [23:22] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_ebi_cs2b_pad_ctrl_MASK 0x00c00000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_ebi_cs2b_pad_ctrl_SHIFT 22
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_ebi_cs2b_pad_ctrl_DEFAULT 0x00000002
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_ebi_cs2b_pad_ctrl_PULL_NONE 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_ebi_cs2b_pad_ctrl_PULL_DOWN 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_ebi_cs2b_pad_ctrl_PULL_UP 2
-
-/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_2 :: ebi_cs1b_pad_ctrl [21:20] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_ebi_cs1b_pad_ctrl_MASK 0x00300000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_ebi_cs1b_pad_ctrl_SHIFT 20
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_ebi_cs1b_pad_ctrl_DEFAULT 0x00000002
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_ebi_cs1b_pad_ctrl_PULL_NONE 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_ebi_cs1b_pad_ctrl_PULL_DOWN 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_ebi_cs1b_pad_ctrl_PULL_UP 2
-
-/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_2 :: ebi_cs0b_pad_ctrl [19:18] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_ebi_cs0b_pad_ctrl_MASK 0x000c0000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_ebi_cs0b_pad_ctrl_SHIFT 18
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_ebi_cs0b_pad_ctrl_DEFAULT 0x00000002
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_ebi_cs0b_pad_ctrl_PULL_NONE 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_ebi_cs0b_pad_ctrl_PULL_DOWN 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_ebi_cs0b_pad_ctrl_PULL_UP 2
-
-/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_2 :: ebi_data_07_pad_ctrl [17:16] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_ebi_data_07_pad_ctrl_MASK 0x00030000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_ebi_data_07_pad_ctrl_SHIFT 16
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_ebi_data_07_pad_ctrl_DEFAULT 0x00000002
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_ebi_data_07_pad_ctrl_PULL_NONE 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_ebi_data_07_pad_ctrl_PULL_DOWN 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_ebi_data_07_pad_ctrl_PULL_UP 2
-
-/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_2 :: ebi_data_06_pad_ctrl [15:14] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_ebi_data_06_pad_ctrl_MASK 0x0000c000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_ebi_data_06_pad_ctrl_SHIFT 14
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_ebi_data_06_pad_ctrl_DEFAULT 0x00000002
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_ebi_data_06_pad_ctrl_PULL_NONE 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_ebi_data_06_pad_ctrl_PULL_DOWN 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_ebi_data_06_pad_ctrl_PULL_UP 2
-
-/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_2 :: ebi_data_05_pad_ctrl [13:12] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_ebi_data_05_pad_ctrl_MASK 0x00003000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_ebi_data_05_pad_ctrl_SHIFT 12
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_ebi_data_05_pad_ctrl_DEFAULT 0x00000002
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_ebi_data_05_pad_ctrl_PULL_NONE 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_ebi_data_05_pad_ctrl_PULL_DOWN 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_ebi_data_05_pad_ctrl_PULL_UP 2
-
-/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_2 :: ebi_data_04_pad_ctrl [11:10] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_ebi_data_04_pad_ctrl_MASK 0x00000c00
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_ebi_data_04_pad_ctrl_SHIFT 10
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_ebi_data_04_pad_ctrl_DEFAULT 0x00000002
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_ebi_data_04_pad_ctrl_PULL_NONE 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_ebi_data_04_pad_ctrl_PULL_DOWN 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_ebi_data_04_pad_ctrl_PULL_UP 2
-
-/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_2 :: ebi_data_03_pad_ctrl [09:08] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_ebi_data_03_pad_ctrl_MASK 0x00000300
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_ebi_data_03_pad_ctrl_SHIFT 8
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_ebi_data_03_pad_ctrl_DEFAULT 0x00000002
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_ebi_data_03_pad_ctrl_PULL_NONE 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_ebi_data_03_pad_ctrl_PULL_DOWN 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_ebi_data_03_pad_ctrl_PULL_UP 2
-
-/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_2 :: ebi_data_02_pad_ctrl [07:06] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_ebi_data_02_pad_ctrl_MASK 0x000000c0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_ebi_data_02_pad_ctrl_SHIFT 6
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_ebi_data_02_pad_ctrl_DEFAULT 0x00000002
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_ebi_data_02_pad_ctrl_PULL_NONE 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_ebi_data_02_pad_ctrl_PULL_DOWN 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_ebi_data_02_pad_ctrl_PULL_UP 2
-
-/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_2 :: ebi_data_01_pad_ctrl [05:04] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_ebi_data_01_pad_ctrl_MASK 0x00000030
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_ebi_data_01_pad_ctrl_SHIFT 4
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_ebi_data_01_pad_ctrl_DEFAULT 0x00000002
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_ebi_data_01_pad_ctrl_PULL_NONE 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_ebi_data_01_pad_ctrl_PULL_DOWN 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_ebi_data_01_pad_ctrl_PULL_UP 2
-
-/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_2 :: ebi_data_00_pad_ctrl [03:02] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_ebi_data_00_pad_ctrl_MASK 0x0000000c
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_ebi_data_00_pad_ctrl_SHIFT 2
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_ebi_data_00_pad_ctrl_DEFAULT 0x00000002
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_ebi_data_00_pad_ctrl_PULL_NONE 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_ebi_data_00_pad_ctrl_PULL_DOWN 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_ebi_data_00_pad_ctrl_PULL_UP 2
-
-/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_2 :: emmc_clk_pad_ctrl [01:00] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_emmc_clk_pad_ctrl_MASK 0x00000003
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_emmc_clk_pad_ctrl_SHIFT 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_emmc_clk_pad_ctrl_DEFAULT 0x00000002
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_emmc_clk_pad_ctrl_PULL_NONE 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_emmc_clk_pad_ctrl_PULL_DOWN 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_emmc_clk_pad_ctrl_PULL_UP 2
-
-/***************************************************************************
- *PIN_MUX_PAD_CTRL_3 - Pad pull-up/pull-down control register 3
- ***************************************************************************/
-/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_3 :: spare_pad_ctrl_3 [31:30] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_spare_pad_ctrl_3_MASK 0xc0000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_spare_pad_ctrl_3_SHIFT 30
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_spare_pad_ctrl_3_DEFAULT 0x00000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_spare_pad_ctrl_3_PULL_NONE 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_spare_pad_ctrl_3_PULL_DOWN 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_spare_pad_ctrl_3_PULL_UP 2
-
-/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_3 :: gpio_005_pad_ctrl [29:28] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_005_pad_ctrl_MASK 0x30000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_005_pad_ctrl_SHIFT 28
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_005_pad_ctrl_DEFAULT 0x00000001
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_005_pad_ctrl_PULL_NONE 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_005_pad_ctrl_PULL_DOWN 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_005_pad_ctrl_PULL_UP 2
-
-/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_3 :: gpio_004_pad_ctrl [27:26] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_004_pad_ctrl_MASK 0x0c000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_004_pad_ctrl_SHIFT 26
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_004_pad_ctrl_DEFAULT 0x00000001
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_004_pad_ctrl_PULL_NONE 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_004_pad_ctrl_PULL_DOWN 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_004_pad_ctrl_PULL_UP 2
-
-/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_3 :: gpio_003_pad_ctrl [25:24] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_003_pad_ctrl_MASK 0x03000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_003_pad_ctrl_SHIFT 24
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_003_pad_ctrl_DEFAULT 0x00000001
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_003_pad_ctrl_PULL_NONE 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_003_pad_ctrl_PULL_DOWN 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_003_pad_ctrl_PULL_UP 2
-
-/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_3 :: gpio_002_pad_ctrl [23:22] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_002_pad_ctrl_MASK 0x00c00000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_002_pad_ctrl_SHIFT 22
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_002_pad_ctrl_DEFAULT 0x00000001
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_002_pad_ctrl_PULL_NONE 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_002_pad_ctrl_PULL_DOWN 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_002_pad_ctrl_PULL_UP 2
-
-/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_3 :: gpio_001_pad_ctrl [21:20] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_001_pad_ctrl_MASK 0x00300000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_001_pad_ctrl_SHIFT 20
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_001_pad_ctrl_DEFAULT 0x00000001
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_001_pad_ctrl_PULL_NONE 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_001_pad_ctrl_PULL_DOWN 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_001_pad_ctrl_PULL_UP 2
-
-/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_3 :: gpio_000_pad_ctrl [19:18] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_000_pad_ctrl_MASK 0x000c0000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_000_pad_ctrl_SHIFT 18
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_000_pad_ctrl_DEFAULT 0x00000001
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_000_pad_ctrl_PULL_NONE 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_000_pad_ctrl_PULL_DOWN 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_000_pad_ctrl_PULL_UP 2
-
-/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_3 :: ebi_nand_dqs_pad_ctrl [17:16] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_ebi_nand_dqs_pad_ctrl_MASK 0x00030000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_ebi_nand_dqs_pad_ctrl_SHIFT 16
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_ebi_nand_dqs_pad_ctrl_DEFAULT 0x00000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_ebi_nand_dqs_pad_ctrl_PULL_NONE 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_ebi_nand_dqs_pad_ctrl_PULL_DOWN 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_ebi_nand_dqs_pad_ctrl_PULL_UP 2
-
-/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_3 :: ebi_nand_wpb_pad_ctrl [15:14] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_ebi_nand_wpb_pad_ctrl_MASK 0x0000c000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_ebi_nand_wpb_pad_ctrl_SHIFT 14
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_ebi_nand_wpb_pad_ctrl_DEFAULT 0x00000001
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_ebi_nand_wpb_pad_ctrl_PULL_NONE 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_ebi_nand_wpb_pad_ctrl_PULL_DOWN 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_ebi_nand_wpb_pad_ctrl_PULL_UP 2
-
-/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_3 :: ebi_nand_rbb_pad_ctrl [13:12] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_ebi_nand_rbb_pad_ctrl_MASK 0x00003000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_ebi_nand_rbb_pad_ctrl_SHIFT 12
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_ebi_nand_rbb_pad_ctrl_DEFAULT 0x00000002
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_ebi_nand_rbb_pad_ctrl_PULL_NONE 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_ebi_nand_rbb_pad_ctrl_PULL_DOWN 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_ebi_nand_rbb_pad_ctrl_PULL_UP 2
-
-/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_3 :: ebi_dsb_pad_ctrl [11:10] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_ebi_dsb_pad_ctrl_MASK 0x00000c00
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_ebi_dsb_pad_ctrl_SHIFT 10
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_ebi_dsb_pad_ctrl_DEFAULT 0x00000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_ebi_dsb_pad_ctrl_PULL_NONE 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_ebi_dsb_pad_ctrl_PULL_DOWN 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_ebi_dsb_pad_ctrl_PULL_UP 2
-
-/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_3 :: ebi_tsb_pad_ctrl [09:08] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_ebi_tsb_pad_ctrl_MASK 0x00000300
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_ebi_tsb_pad_ctrl_SHIFT 8
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_ebi_tsb_pad_ctrl_DEFAULT 0x00000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_ebi_tsb_pad_ctrl_PULL_NONE 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_ebi_tsb_pad_ctrl_PULL_DOWN 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_ebi_tsb_pad_ctrl_PULL_UP 2
-
-/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_3 :: ebi_rdb_pad_ctrl [07:06] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_ebi_rdb_pad_ctrl_MASK 0x000000c0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_ebi_rdb_pad_ctrl_SHIFT 6
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_ebi_rdb_pad_ctrl_DEFAULT 0x00000002
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_ebi_rdb_pad_ctrl_PULL_NONE 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_ebi_rdb_pad_ctrl_PULL_DOWN 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_ebi_rdb_pad_ctrl_PULL_UP 2
-
-/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_3 :: ebi_we1b_pad_ctrl [05:04] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_ebi_we1b_pad_ctrl_MASK 0x00000030
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_ebi_we1b_pad_ctrl_SHIFT 4
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_ebi_we1b_pad_ctrl_DEFAULT 0x00000002
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_ebi_we1b_pad_ctrl_PULL_NONE 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_ebi_we1b_pad_ctrl_PULL_DOWN 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_ebi_we1b_pad_ctrl_PULL_UP 2
-
-/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_3 :: ebi_we0b_pad_ctrl [03:02] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_ebi_we0b_pad_ctrl_MASK 0x0000000c
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_ebi_we0b_pad_ctrl_SHIFT 2
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_ebi_we0b_pad_ctrl_DEFAULT 0x00000002
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_ebi_we0b_pad_ctrl_PULL_NONE 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_ebi_we0b_pad_ctrl_PULL_DOWN 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_ebi_we0b_pad_ctrl_PULL_UP 2
-
-/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_3 :: ebi_rwb_pad_ctrl [01:00] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_ebi_rwb_pad_ctrl_MASK 0x00000003
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_ebi_rwb_pad_ctrl_SHIFT 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_ebi_rwb_pad_ctrl_DEFAULT 0x00000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_ebi_rwb_pad_ctrl_PULL_NONE 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_ebi_rwb_pad_ctrl_PULL_DOWN 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_ebi_rwb_pad_ctrl_PULL_UP 2
-
-/***************************************************************************
- *PIN_MUX_PAD_CTRL_4 - Pad pull-up/pull-down control register 4
- ***************************************************************************/
-/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_4 :: spare_pad_ctrl_4 [31:30] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_spare_pad_ctrl_4_MASK 0xc0000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_spare_pad_ctrl_4_SHIFT 30
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_spare_pad_ctrl_4_DEFAULT 0x00000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_spare_pad_ctrl_4_PULL_NONE 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_spare_pad_ctrl_4_PULL_DOWN 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_spare_pad_ctrl_4_PULL_UP 2
-
-/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_4 :: gpio_020_pad_ctrl [29:28] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_020_pad_ctrl_MASK 0x30000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_020_pad_ctrl_SHIFT 28
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_020_pad_ctrl_DEFAULT 0x00000001
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_020_pad_ctrl_PULL_NONE 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_020_pad_ctrl_PULL_DOWN 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_020_pad_ctrl_PULL_UP 2
-
-/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_4 :: gpio_019_pad_ctrl [27:26] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_019_pad_ctrl_MASK 0x0c000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_019_pad_ctrl_SHIFT 26
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_019_pad_ctrl_DEFAULT 0x00000001
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_019_pad_ctrl_PULL_NONE 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_019_pad_ctrl_PULL_DOWN 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_019_pad_ctrl_PULL_UP 2
-
-/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_4 :: gpio_018_pad_ctrl [25:24] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_018_pad_ctrl_MASK 0x03000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_018_pad_ctrl_SHIFT 24
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_018_pad_ctrl_DEFAULT 0x00000001
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_018_pad_ctrl_PULL_NONE 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_018_pad_ctrl_PULL_DOWN 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_018_pad_ctrl_PULL_UP 2
-
-/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_4 :: gpio_017_pad_ctrl [23:22] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_017_pad_ctrl_MASK 0x00c00000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_017_pad_ctrl_SHIFT 22
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_017_pad_ctrl_DEFAULT 0x00000001
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_017_pad_ctrl_PULL_NONE 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_017_pad_ctrl_PULL_DOWN 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_017_pad_ctrl_PULL_UP 2
-
-/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_4 :: gpio_016_pad_ctrl [21:20] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_016_pad_ctrl_MASK 0x00300000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_016_pad_ctrl_SHIFT 20
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_016_pad_ctrl_DEFAULT 0x00000001
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_016_pad_ctrl_PULL_NONE 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_016_pad_ctrl_PULL_DOWN 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_016_pad_ctrl_PULL_UP 2
-
-/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_4 :: gpio_015_pad_ctrl [19:18] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_015_pad_ctrl_MASK 0x000c0000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_015_pad_ctrl_SHIFT 18
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_015_pad_ctrl_DEFAULT 0x00000001
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_015_pad_ctrl_PULL_NONE 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_015_pad_ctrl_PULL_DOWN 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_015_pad_ctrl_PULL_UP 2
-
-/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_4 :: gpio_014_pad_ctrl [17:16] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_014_pad_ctrl_MASK 0x00030000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_014_pad_ctrl_SHIFT 16
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_014_pad_ctrl_DEFAULT 0x00000001
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_014_pad_ctrl_PULL_NONE 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_014_pad_ctrl_PULL_DOWN 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_014_pad_ctrl_PULL_UP 2
-
-/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_4 :: gpio_013_pad_ctrl [15:14] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_013_pad_ctrl_MASK 0x0000c000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_013_pad_ctrl_SHIFT 14
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_013_pad_ctrl_DEFAULT 0x00000001
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_013_pad_ctrl_PULL_NONE 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_013_pad_ctrl_PULL_DOWN 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_013_pad_ctrl_PULL_UP 2
-
-/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_4 :: gpio_012_pad_ctrl [13:12] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_012_pad_ctrl_MASK 0x00003000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_012_pad_ctrl_SHIFT 12
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_012_pad_ctrl_DEFAULT 0x00000001
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_012_pad_ctrl_PULL_NONE 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_012_pad_ctrl_PULL_DOWN 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_012_pad_ctrl_PULL_UP 2
-
-/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_4 :: reserved0 [11:10] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_reserved0_MASK 0x00000c00
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_reserved0_SHIFT 10
-
-/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_4 :: gpio_010_pad_ctrl [09:08] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_010_pad_ctrl_MASK 0x00000300
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_010_pad_ctrl_SHIFT 8
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_010_pad_ctrl_DEFAULT 0x00000001
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_010_pad_ctrl_PULL_NONE 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_010_pad_ctrl_PULL_DOWN 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_010_pad_ctrl_PULL_UP 2
-
-/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_4 :: gpio_009_pad_ctrl [07:06] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_009_pad_ctrl_MASK 0x000000c0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_009_pad_ctrl_SHIFT 6
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_009_pad_ctrl_DEFAULT 0x00000001
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_009_pad_ctrl_PULL_NONE 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_009_pad_ctrl_PULL_DOWN 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_009_pad_ctrl_PULL_UP 2
-
-/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_4 :: gpio_008_pad_ctrl [05:04] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_008_pad_ctrl_MASK 0x00000030
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_008_pad_ctrl_SHIFT 4
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_008_pad_ctrl_DEFAULT 0x00000001
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_008_pad_ctrl_PULL_NONE 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_008_pad_ctrl_PULL_DOWN 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_008_pad_ctrl_PULL_UP 2
-
-/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_4 :: gpio_007_pad_ctrl [03:02] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_007_pad_ctrl_MASK 0x0000000c
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_007_pad_ctrl_SHIFT 2
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_007_pad_ctrl_DEFAULT 0x00000001
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_007_pad_ctrl_PULL_NONE 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_007_pad_ctrl_PULL_DOWN 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_007_pad_ctrl_PULL_UP 2
-
-/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_4 :: gpio_006_pad_ctrl [01:00] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_006_pad_ctrl_MASK 0x00000003
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_006_pad_ctrl_SHIFT 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_006_pad_ctrl_DEFAULT 0x00000001
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_006_pad_ctrl_PULL_NONE 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_006_pad_ctrl_PULL_DOWN 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_006_pad_ctrl_PULL_UP 2
-
-/***************************************************************************
- *PIN_MUX_PAD_CTRL_5 - Pad pull-up/pull-down control register 5
- ***************************************************************************/
-/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_5 :: spare_pad_ctrl_5 [31:30] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_spare_pad_ctrl_5_MASK 0xc0000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_spare_pad_ctrl_5_SHIFT 30
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_spare_pad_ctrl_5_DEFAULT 0x00000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_spare_pad_ctrl_5_PULL_NONE 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_spare_pad_ctrl_5_PULL_DOWN 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_spare_pad_ctrl_5_PULL_UP 2
-
-/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_5 :: gpio_035_pad_ctrl [29:28] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_035_pad_ctrl_MASK 0x30000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_035_pad_ctrl_SHIFT 28
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_035_pad_ctrl_DEFAULT 0x00000001
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_035_pad_ctrl_PULL_NONE 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_035_pad_ctrl_PULL_DOWN 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_035_pad_ctrl_PULL_UP 2
-
-/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_5 :: gpio_034_pad_ctrl [27:26] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_034_pad_ctrl_MASK 0x0c000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_034_pad_ctrl_SHIFT 26
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_034_pad_ctrl_DEFAULT 0x00000001
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_034_pad_ctrl_PULL_NONE 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_034_pad_ctrl_PULL_DOWN 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_034_pad_ctrl_PULL_UP 2
-
-/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_5 :: gpio_033_pad_ctrl [25:24] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_033_pad_ctrl_MASK 0x03000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_033_pad_ctrl_SHIFT 24
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_033_pad_ctrl_DEFAULT 0x00000001
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_033_pad_ctrl_PULL_NONE 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_033_pad_ctrl_PULL_DOWN 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_033_pad_ctrl_PULL_UP 2
-
-/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_5 :: gpio_032_pad_ctrl [23:22] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_032_pad_ctrl_MASK 0x00c00000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_032_pad_ctrl_SHIFT 22
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_032_pad_ctrl_DEFAULT 0x00000001
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_032_pad_ctrl_PULL_NONE 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_032_pad_ctrl_PULL_DOWN 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_032_pad_ctrl_PULL_UP 2
-
-/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_5 :: gpio_031_pad_ctrl [21:20] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_031_pad_ctrl_MASK 0x00300000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_031_pad_ctrl_SHIFT 20
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_031_pad_ctrl_DEFAULT 0x00000001
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_031_pad_ctrl_PULL_NONE 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_031_pad_ctrl_PULL_DOWN 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_031_pad_ctrl_PULL_UP 2
-
-/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_5 :: gpio_030_pad_ctrl [19:18] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_030_pad_ctrl_MASK 0x000c0000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_030_pad_ctrl_SHIFT 18
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_030_pad_ctrl_DEFAULT 0x00000001
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_030_pad_ctrl_PULL_NONE 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_030_pad_ctrl_PULL_DOWN 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_030_pad_ctrl_PULL_UP 2
-
-/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_5 :: gpio_029_pad_ctrl [17:16] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_029_pad_ctrl_MASK 0x00030000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_029_pad_ctrl_SHIFT 16
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_029_pad_ctrl_DEFAULT 0x00000001
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_029_pad_ctrl_PULL_NONE 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_029_pad_ctrl_PULL_DOWN 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_029_pad_ctrl_PULL_UP 2
-
-/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_5 :: gpio_028_pad_ctrl [15:14] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_028_pad_ctrl_MASK 0x0000c000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_028_pad_ctrl_SHIFT 14
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_028_pad_ctrl_DEFAULT 0x00000001
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_028_pad_ctrl_PULL_NONE 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_028_pad_ctrl_PULL_DOWN 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_028_pad_ctrl_PULL_UP 2
-
-/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_5 :: gpio_027_pad_ctrl [13:12] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_027_pad_ctrl_MASK 0x00003000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_027_pad_ctrl_SHIFT 12
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_027_pad_ctrl_DEFAULT 0x00000001
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_027_pad_ctrl_PULL_NONE 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_027_pad_ctrl_PULL_DOWN 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_027_pad_ctrl_PULL_UP 2
-
-/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_5 :: gpio_026_pad_ctrl [11:10] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_026_pad_ctrl_MASK 0x00000c00
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_026_pad_ctrl_SHIFT 10
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_026_pad_ctrl_DEFAULT 0x00000001
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_026_pad_ctrl_PULL_NONE 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_026_pad_ctrl_PULL_DOWN 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_026_pad_ctrl_PULL_UP 2
-
-/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_5 :: gpio_025_pad_ctrl [09:08] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_025_pad_ctrl_MASK 0x00000300
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_025_pad_ctrl_SHIFT 8
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_025_pad_ctrl_DEFAULT 0x00000001
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_025_pad_ctrl_PULL_NONE 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_025_pad_ctrl_PULL_DOWN 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_025_pad_ctrl_PULL_UP 2
-
-/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_5 :: gpio_024_pad_ctrl [07:06] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_024_pad_ctrl_MASK 0x000000c0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_024_pad_ctrl_SHIFT 6
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_024_pad_ctrl_DEFAULT 0x00000001
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_024_pad_ctrl_PULL_NONE 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_024_pad_ctrl_PULL_DOWN 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_024_pad_ctrl_PULL_UP 2
-
-/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_5 :: gpio_023_pad_ctrl [05:04] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_023_pad_ctrl_MASK 0x00000030
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_023_pad_ctrl_SHIFT 4
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_023_pad_ctrl_DEFAULT 0x00000001
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_023_pad_ctrl_PULL_NONE 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_023_pad_ctrl_PULL_DOWN 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_023_pad_ctrl_PULL_UP 2
-
-/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_5 :: gpio_022_pad_ctrl [03:02] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_022_pad_ctrl_MASK 0x0000000c
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_022_pad_ctrl_SHIFT 2
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_022_pad_ctrl_DEFAULT 0x00000001
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_022_pad_ctrl_PULL_NONE 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_022_pad_ctrl_PULL_DOWN 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_022_pad_ctrl_PULL_UP 2
-
-/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_5 :: gpio_021_pad_ctrl [01:00] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_021_pad_ctrl_MASK 0x00000003
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_021_pad_ctrl_SHIFT 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_021_pad_ctrl_DEFAULT 0x00000001
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_021_pad_ctrl_PULL_NONE 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_021_pad_ctrl_PULL_DOWN 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_021_pad_ctrl_PULL_UP 2
-
-/***************************************************************************
- *PIN_MUX_PAD_CTRL_6 - Pad pull-up/pull-down control register 6
- ***************************************************************************/
-/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_6 :: spare_pad_ctrl_6 [31:30] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_spare_pad_ctrl_6_MASK 0xc0000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_spare_pad_ctrl_6_SHIFT 30
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_spare_pad_ctrl_6_DEFAULT 0x00000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_spare_pad_ctrl_6_PULL_NONE 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_spare_pad_ctrl_6_PULL_DOWN 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_spare_pad_ctrl_6_PULL_UP 2
-
-/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_6 :: gpio_050_pad_ctrl [29:28] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_050_pad_ctrl_MASK 0x30000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_050_pad_ctrl_SHIFT 28
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_050_pad_ctrl_DEFAULT 0x00000001
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_050_pad_ctrl_PULL_NONE 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_050_pad_ctrl_PULL_DOWN 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_050_pad_ctrl_PULL_UP 2
-
-/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_6 :: gpio_049_pad_ctrl [27:26] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_049_pad_ctrl_MASK 0x0c000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_049_pad_ctrl_SHIFT 26
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_049_pad_ctrl_DEFAULT 0x00000001
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_049_pad_ctrl_PULL_NONE 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_049_pad_ctrl_PULL_DOWN 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_049_pad_ctrl_PULL_UP 2
-
-/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_6 :: gpio_048_pad_ctrl [25:24] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_048_pad_ctrl_MASK 0x03000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_048_pad_ctrl_SHIFT 24
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_048_pad_ctrl_DEFAULT 0x00000001
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_048_pad_ctrl_PULL_NONE 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_048_pad_ctrl_PULL_DOWN 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_048_pad_ctrl_PULL_UP 2
-
-/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_6 :: gpio_047_pad_ctrl [23:22] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_047_pad_ctrl_MASK 0x00c00000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_047_pad_ctrl_SHIFT 22
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_047_pad_ctrl_DEFAULT 0x00000001
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_047_pad_ctrl_PULL_NONE 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_047_pad_ctrl_PULL_DOWN 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_047_pad_ctrl_PULL_UP 2
-
-/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_6 :: gpio_046_pad_ctrl [21:20] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_046_pad_ctrl_MASK 0x00300000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_046_pad_ctrl_SHIFT 20
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_046_pad_ctrl_DEFAULT 0x00000001
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_046_pad_ctrl_PULL_NONE 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_046_pad_ctrl_PULL_DOWN 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_046_pad_ctrl_PULL_UP 2
-
-/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_6 :: gpio_045_pad_ctrl [19:18] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_045_pad_ctrl_MASK 0x000c0000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_045_pad_ctrl_SHIFT 18
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_045_pad_ctrl_DEFAULT 0x00000001
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_045_pad_ctrl_PULL_NONE 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_045_pad_ctrl_PULL_DOWN 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_045_pad_ctrl_PULL_UP 2
-
-/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_6 :: gpio_044_pad_ctrl [17:16] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_044_pad_ctrl_MASK 0x00030000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_044_pad_ctrl_SHIFT 16
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_044_pad_ctrl_DEFAULT 0x00000001
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_044_pad_ctrl_PULL_NONE 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_044_pad_ctrl_PULL_DOWN 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_044_pad_ctrl_PULL_UP 2
-
-/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_6 :: gpio_043_pad_ctrl [15:14] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_043_pad_ctrl_MASK 0x0000c000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_043_pad_ctrl_SHIFT 14
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_043_pad_ctrl_DEFAULT 0x00000001
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_043_pad_ctrl_PULL_NONE 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_043_pad_ctrl_PULL_DOWN 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_043_pad_ctrl_PULL_UP 2
-
-/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_6 :: gpio_042_pad_ctrl [13:12] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_042_pad_ctrl_MASK 0x00003000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_042_pad_ctrl_SHIFT 12
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_042_pad_ctrl_DEFAULT 0x00000001
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_042_pad_ctrl_PULL_NONE 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_042_pad_ctrl_PULL_DOWN 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_042_pad_ctrl_PULL_UP 2
-
-/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_6 :: gpio_041_pad_ctrl [11:10] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_041_pad_ctrl_MASK 0x00000c00
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_041_pad_ctrl_SHIFT 10
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_041_pad_ctrl_DEFAULT 0x00000001
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_041_pad_ctrl_PULL_NONE 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_041_pad_ctrl_PULL_DOWN 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_041_pad_ctrl_PULL_UP 2
-
-/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_6 :: gpio_040_pad_ctrl [09:08] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_040_pad_ctrl_MASK 0x00000300
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_040_pad_ctrl_SHIFT 8
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_040_pad_ctrl_DEFAULT 0x00000001
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_040_pad_ctrl_PULL_NONE 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_040_pad_ctrl_PULL_DOWN 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_040_pad_ctrl_PULL_UP 2
-
-/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_6 :: gpio_039_pad_ctrl [07:06] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_039_pad_ctrl_MASK 0x000000c0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_039_pad_ctrl_SHIFT 6
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_039_pad_ctrl_DEFAULT 0x00000001
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_039_pad_ctrl_PULL_NONE 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_039_pad_ctrl_PULL_DOWN 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_039_pad_ctrl_PULL_UP 2
-
-/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_6 :: gpio_038_pad_ctrl [05:04] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_038_pad_ctrl_MASK 0x00000030
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_038_pad_ctrl_SHIFT 4
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_038_pad_ctrl_DEFAULT 0x00000001
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_038_pad_ctrl_PULL_NONE 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_038_pad_ctrl_PULL_DOWN 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_038_pad_ctrl_PULL_UP 2
-
-/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_6 :: gpio_037_pad_ctrl [03:02] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_037_pad_ctrl_MASK 0x0000000c
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_037_pad_ctrl_SHIFT 2
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_037_pad_ctrl_DEFAULT 0x00000001
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_037_pad_ctrl_PULL_NONE 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_037_pad_ctrl_PULL_DOWN 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_037_pad_ctrl_PULL_UP 2
-
-/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_6 :: gpio_036_pad_ctrl [01:00] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_036_pad_ctrl_MASK 0x00000003
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_036_pad_ctrl_SHIFT 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_036_pad_ctrl_DEFAULT 0x00000001
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_036_pad_ctrl_PULL_NONE 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_036_pad_ctrl_PULL_DOWN 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_036_pad_ctrl_PULL_UP 2
-
-/***************************************************************************
- *PIN_MUX_PAD_CTRL_7 - Pad pull-up/pull-down control register 7
- ***************************************************************************/
-/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_7 :: spare_pad_ctrl_7 [31:30] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_spare_pad_ctrl_7_MASK 0xc0000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_spare_pad_ctrl_7_SHIFT 30
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_spare_pad_ctrl_7_DEFAULT 0x00000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_spare_pad_ctrl_7_PULL_NONE 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_spare_pad_ctrl_7_PULL_DOWN 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_spare_pad_ctrl_7_PULL_UP 2
-
-/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_7 :: gpio_065_pad_ctrl [29:28] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_065_pad_ctrl_MASK 0x30000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_065_pad_ctrl_SHIFT 28
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_065_pad_ctrl_DEFAULT 0x00000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_065_pad_ctrl_PULL_NONE 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_065_pad_ctrl_PULL_DOWN 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_065_pad_ctrl_PULL_UP 2
-
-/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_7 :: gpio_064_pad_ctrl [27:26] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_064_pad_ctrl_MASK 0x0c000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_064_pad_ctrl_SHIFT 26
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_064_pad_ctrl_DEFAULT 0x00000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_064_pad_ctrl_PULL_NONE 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_064_pad_ctrl_PULL_DOWN 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_064_pad_ctrl_PULL_UP 2
-
-/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_7 :: gpio_063_pad_ctrl [25:24] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_063_pad_ctrl_MASK 0x03000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_063_pad_ctrl_SHIFT 24
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_063_pad_ctrl_DEFAULT 0x00000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_063_pad_ctrl_PULL_NONE 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_063_pad_ctrl_PULL_DOWN 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_063_pad_ctrl_PULL_UP 2
-
-/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_7 :: gpio_062_pad_ctrl [23:22] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_062_pad_ctrl_MASK 0x00c00000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_062_pad_ctrl_SHIFT 22
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_062_pad_ctrl_DEFAULT 0x00000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_062_pad_ctrl_PULL_NONE 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_062_pad_ctrl_PULL_DOWN 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_062_pad_ctrl_PULL_UP 2
-
-/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_7 :: gpio_061_pad_ctrl [21:20] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_061_pad_ctrl_MASK 0x00300000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_061_pad_ctrl_SHIFT 20
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_061_pad_ctrl_DEFAULT 0x00000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_061_pad_ctrl_PULL_NONE 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_061_pad_ctrl_PULL_DOWN 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_061_pad_ctrl_PULL_UP 2
-
-/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_7 :: gpio_060_pad_ctrl [19:18] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_060_pad_ctrl_MASK 0x000c0000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_060_pad_ctrl_SHIFT 18
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_060_pad_ctrl_DEFAULT 0x00000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_060_pad_ctrl_PULL_NONE 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_060_pad_ctrl_PULL_DOWN 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_060_pad_ctrl_PULL_UP 2
-
-/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_7 :: gpio_059_pad_ctrl [17:16] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_059_pad_ctrl_MASK 0x00030000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_059_pad_ctrl_SHIFT 16
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_059_pad_ctrl_DEFAULT 0x00000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_059_pad_ctrl_PULL_NONE 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_059_pad_ctrl_PULL_DOWN 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_059_pad_ctrl_PULL_UP 2
-
-/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_7 :: gpio_058_pad_ctrl [15:14] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_058_pad_ctrl_MASK 0x0000c000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_058_pad_ctrl_SHIFT 14
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_058_pad_ctrl_DEFAULT 0x00000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_058_pad_ctrl_PULL_NONE 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_058_pad_ctrl_PULL_DOWN 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_058_pad_ctrl_PULL_UP 2
-
-/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_7 :: gpio_057_pad_ctrl [13:12] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_057_pad_ctrl_MASK 0x00003000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_057_pad_ctrl_SHIFT 12
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_057_pad_ctrl_DEFAULT 0x00000001
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_057_pad_ctrl_PULL_NONE 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_057_pad_ctrl_PULL_DOWN 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_057_pad_ctrl_PULL_UP 2
-
-/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_7 :: gpio_056_pad_ctrl [11:10] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_056_pad_ctrl_MASK 0x00000c00
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_056_pad_ctrl_SHIFT 10
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_056_pad_ctrl_DEFAULT 0x00000001
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_056_pad_ctrl_PULL_NONE 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_056_pad_ctrl_PULL_DOWN 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_056_pad_ctrl_PULL_UP 2
-
-/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_7 :: gpio_055_pad_ctrl [09:08] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_055_pad_ctrl_MASK 0x00000300
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_055_pad_ctrl_SHIFT 8
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_055_pad_ctrl_DEFAULT 0x00000001
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_055_pad_ctrl_PULL_NONE 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_055_pad_ctrl_PULL_DOWN 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_055_pad_ctrl_PULL_UP 2
-
-/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_7 :: gpio_054_pad_ctrl [07:06] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_054_pad_ctrl_MASK 0x000000c0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_054_pad_ctrl_SHIFT 6
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_054_pad_ctrl_DEFAULT 0x00000001
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_054_pad_ctrl_PULL_NONE 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_054_pad_ctrl_PULL_DOWN 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_054_pad_ctrl_PULL_UP 2
-
-/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_7 :: gpio_053_pad_ctrl [05:04] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_053_pad_ctrl_MASK 0x00000030
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_053_pad_ctrl_SHIFT 4
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_053_pad_ctrl_DEFAULT 0x00000001
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_053_pad_ctrl_PULL_NONE 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_053_pad_ctrl_PULL_DOWN 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_053_pad_ctrl_PULL_UP 2
-
-/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_7 :: gpio_052_pad_ctrl [03:02] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_052_pad_ctrl_MASK 0x0000000c
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_052_pad_ctrl_SHIFT 2
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_052_pad_ctrl_DEFAULT 0x00000001
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_052_pad_ctrl_PULL_NONE 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_052_pad_ctrl_PULL_DOWN 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_052_pad_ctrl_PULL_UP 2
-
-/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_7 :: gpio_051_pad_ctrl [01:00] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_051_pad_ctrl_MASK 0x00000003
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_051_pad_ctrl_SHIFT 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_051_pad_ctrl_DEFAULT 0x00000001
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_051_pad_ctrl_PULL_NONE 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_051_pad_ctrl_PULL_DOWN 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_051_pad_ctrl_PULL_UP 2
-
-/***************************************************************************
- *PIN_MUX_PAD_CTRL_8 - Pad pull-up/pull-down control register 8
- ***************************************************************************/
-/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_8 :: spare_pad_ctrl_8 [31:30] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_spare_pad_ctrl_8_MASK 0xc0000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_spare_pad_ctrl_8_SHIFT 30
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_spare_pad_ctrl_8_DEFAULT 0x00000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_spare_pad_ctrl_8_PULL_NONE 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_spare_pad_ctrl_8_PULL_DOWN 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_spare_pad_ctrl_8_PULL_UP 2
-
-/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_8 :: gpio_080_pad_ctrl [29:28] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_080_pad_ctrl_MASK 0x30000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_080_pad_ctrl_SHIFT 28
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_080_pad_ctrl_DEFAULT 0x00000001
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_080_pad_ctrl_PULL_NONE 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_080_pad_ctrl_PULL_DOWN 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_080_pad_ctrl_PULL_UP 2
-
-/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_8 :: gpio_079_pad_ctrl [27:26] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_079_pad_ctrl_MASK 0x0c000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_079_pad_ctrl_SHIFT 26
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_079_pad_ctrl_DEFAULT 0x00000001
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_079_pad_ctrl_PULL_NONE 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_079_pad_ctrl_PULL_DOWN 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_079_pad_ctrl_PULL_UP 2
-
-/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_8 :: gpio_078_pad_ctrl [25:24] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_078_pad_ctrl_MASK 0x03000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_078_pad_ctrl_SHIFT 24
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_078_pad_ctrl_DEFAULT 0x00000001
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_078_pad_ctrl_PULL_NONE 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_078_pad_ctrl_PULL_DOWN 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_078_pad_ctrl_PULL_UP 2
-
-/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_8 :: gpio_077_pad_ctrl [23:22] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_077_pad_ctrl_MASK 0x00c00000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_077_pad_ctrl_SHIFT 22
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_077_pad_ctrl_DEFAULT 0x00000001
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_077_pad_ctrl_PULL_NONE 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_077_pad_ctrl_PULL_DOWN 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_077_pad_ctrl_PULL_UP 2
-
-/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_8 :: gpio_076_pad_ctrl [21:20] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_076_pad_ctrl_MASK 0x00300000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_076_pad_ctrl_SHIFT 20
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_076_pad_ctrl_DEFAULT 0x00000001
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_076_pad_ctrl_PULL_NONE 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_076_pad_ctrl_PULL_DOWN 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_076_pad_ctrl_PULL_UP 2
-
-/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_8 :: gpio_075_pad_ctrl [19:18] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_075_pad_ctrl_MASK 0x000c0000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_075_pad_ctrl_SHIFT 18
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_075_pad_ctrl_DEFAULT 0x00000001
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_075_pad_ctrl_PULL_NONE 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_075_pad_ctrl_PULL_DOWN 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_075_pad_ctrl_PULL_UP 2
-
-/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_8 :: gpio_074_pad_ctrl [17:16] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_074_pad_ctrl_MASK 0x00030000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_074_pad_ctrl_SHIFT 16
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_074_pad_ctrl_DEFAULT 0x00000001
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_074_pad_ctrl_PULL_NONE 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_074_pad_ctrl_PULL_DOWN 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_074_pad_ctrl_PULL_UP 2
-
-/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_8 :: gpio_073_pad_ctrl [15:14] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_073_pad_ctrl_MASK 0x0000c000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_073_pad_ctrl_SHIFT 14
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_073_pad_ctrl_DEFAULT 0x00000001
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_073_pad_ctrl_PULL_NONE 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_073_pad_ctrl_PULL_DOWN 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_073_pad_ctrl_PULL_UP 2
-
-/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_8 :: gpio_072_pad_ctrl [13:12] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_072_pad_ctrl_MASK 0x00003000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_072_pad_ctrl_SHIFT 12
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_072_pad_ctrl_DEFAULT 0x00000001
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_072_pad_ctrl_PULL_NONE 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_072_pad_ctrl_PULL_DOWN 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_072_pad_ctrl_PULL_UP 2
-
-/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_8 :: gpio_071_pad_ctrl [11:10] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_071_pad_ctrl_MASK 0x00000c00
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_071_pad_ctrl_SHIFT 10
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_071_pad_ctrl_DEFAULT 0x00000001
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_071_pad_ctrl_PULL_NONE 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_071_pad_ctrl_PULL_DOWN 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_071_pad_ctrl_PULL_UP 2
-
-/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_8 :: gpio_070_pad_ctrl [09:08] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_070_pad_ctrl_MASK 0x00000300
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_070_pad_ctrl_SHIFT 8
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_070_pad_ctrl_DEFAULT 0x00000001
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_070_pad_ctrl_PULL_NONE 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_070_pad_ctrl_PULL_DOWN 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_070_pad_ctrl_PULL_UP 2
-
-/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_8 :: gpio_069_pad_ctrl [07:06] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_069_pad_ctrl_MASK 0x000000c0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_069_pad_ctrl_SHIFT 6
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_069_pad_ctrl_DEFAULT 0x00000001
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_069_pad_ctrl_PULL_NONE 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_069_pad_ctrl_PULL_DOWN 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_069_pad_ctrl_PULL_UP 2
-
-/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_8 :: gpio_068_pad_ctrl [05:04] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_068_pad_ctrl_MASK 0x00000030
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_068_pad_ctrl_SHIFT 4
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_068_pad_ctrl_DEFAULT 0x00000001
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_068_pad_ctrl_PULL_NONE 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_068_pad_ctrl_PULL_DOWN 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_068_pad_ctrl_PULL_UP 2
-
-/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_8 :: gpio_067_pad_ctrl [03:02] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_067_pad_ctrl_MASK 0x0000000c
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_067_pad_ctrl_SHIFT 2
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_067_pad_ctrl_DEFAULT 0x00000001
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_067_pad_ctrl_PULL_NONE 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_067_pad_ctrl_PULL_DOWN 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_067_pad_ctrl_PULL_UP 2
-
-/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_8 :: gpio_066_pad_ctrl [01:00] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_066_pad_ctrl_MASK 0x00000003
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_066_pad_ctrl_SHIFT 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_066_pad_ctrl_DEFAULT 0x00000001
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_066_pad_ctrl_PULL_NONE 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_066_pad_ctrl_PULL_DOWN 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_066_pad_ctrl_PULL_UP 2
-
-/***************************************************************************
- *PIN_MUX_PAD_CTRL_9 - Pad pull-up/pull-down control register 9
- ***************************************************************************/
-/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_9 :: spare_pad_ctrl_9 [31:30] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_spare_pad_ctrl_9_MASK 0xc0000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_spare_pad_ctrl_9_SHIFT 30
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_spare_pad_ctrl_9_DEFAULT 0x00000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_spare_pad_ctrl_9_PULL_NONE 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_spare_pad_ctrl_9_PULL_DOWN 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_spare_pad_ctrl_9_PULL_UP 2
-
-/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_9 :: gpio_095_pad_ctrl [29:28] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_095_pad_ctrl_MASK 0x30000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_095_pad_ctrl_SHIFT 28
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_095_pad_ctrl_DEFAULT 0x00000001
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_095_pad_ctrl_PULL_NONE 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_095_pad_ctrl_PULL_DOWN 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_095_pad_ctrl_PULL_UP 2
-
-/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_9 :: gpio_094_pad_ctrl [27:26] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_094_pad_ctrl_MASK 0x0c000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_094_pad_ctrl_SHIFT 26
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_094_pad_ctrl_DEFAULT 0x00000001
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_094_pad_ctrl_PULL_NONE 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_094_pad_ctrl_PULL_DOWN 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_094_pad_ctrl_PULL_UP 2
-
-/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_9 :: gpio_093_pad_ctrl [25:24] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_093_pad_ctrl_MASK 0x03000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_093_pad_ctrl_SHIFT 24
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_093_pad_ctrl_DEFAULT 0x00000001
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_093_pad_ctrl_PULL_NONE 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_093_pad_ctrl_PULL_DOWN 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_093_pad_ctrl_PULL_UP 2
-
-/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_9 :: gpio_092_pad_ctrl [23:22] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_092_pad_ctrl_MASK 0x00c00000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_092_pad_ctrl_SHIFT 22
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_092_pad_ctrl_DEFAULT 0x00000001
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_092_pad_ctrl_PULL_NONE 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_092_pad_ctrl_PULL_DOWN 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_092_pad_ctrl_PULL_UP 2
-
-/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_9 :: gpio_091_pad_ctrl [21:20] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_091_pad_ctrl_MASK 0x00300000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_091_pad_ctrl_SHIFT 20
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_091_pad_ctrl_DEFAULT 0x00000001
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_091_pad_ctrl_PULL_NONE 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_091_pad_ctrl_PULL_DOWN 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_091_pad_ctrl_PULL_UP 2
-
-/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_9 :: gpio_090_pad_ctrl [19:18] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_090_pad_ctrl_MASK 0x000c0000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_090_pad_ctrl_SHIFT 18
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_090_pad_ctrl_DEFAULT 0x00000001
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_090_pad_ctrl_PULL_NONE 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_090_pad_ctrl_PULL_DOWN 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_090_pad_ctrl_PULL_UP 2
-
-/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_9 :: gpio_089_pad_ctrl [17:16] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_089_pad_ctrl_MASK 0x00030000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_089_pad_ctrl_SHIFT 16
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_089_pad_ctrl_DEFAULT 0x00000001
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_089_pad_ctrl_PULL_NONE 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_089_pad_ctrl_PULL_DOWN 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_089_pad_ctrl_PULL_UP 2
-
-/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_9 :: gpio_088_pad_ctrl [15:14] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_088_pad_ctrl_MASK 0x0000c000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_088_pad_ctrl_SHIFT 14
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_088_pad_ctrl_DEFAULT 0x00000001
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_088_pad_ctrl_PULL_NONE 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_088_pad_ctrl_PULL_DOWN 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_088_pad_ctrl_PULL_UP 2
-
-/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_9 :: gpio_087_pad_ctrl [13:12] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_087_pad_ctrl_MASK 0x00003000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_087_pad_ctrl_SHIFT 12
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_087_pad_ctrl_DEFAULT 0x00000001
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_087_pad_ctrl_PULL_NONE 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_087_pad_ctrl_PULL_DOWN 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_087_pad_ctrl_PULL_UP 2
-
-/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_9 :: gpio_086_pad_ctrl [11:10] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_086_pad_ctrl_MASK 0x00000c00
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_086_pad_ctrl_SHIFT 10
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_086_pad_ctrl_DEFAULT 0x00000001
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_086_pad_ctrl_PULL_NONE 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_086_pad_ctrl_PULL_DOWN 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_086_pad_ctrl_PULL_UP 2
-
-/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_9 :: gpio_085_pad_ctrl [09:08] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_085_pad_ctrl_MASK 0x00000300
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_085_pad_ctrl_SHIFT 8
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_085_pad_ctrl_DEFAULT 0x00000001
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_085_pad_ctrl_PULL_NONE 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_085_pad_ctrl_PULL_DOWN 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_085_pad_ctrl_PULL_UP 2
-
-/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_9 :: gpio_084_pad_ctrl [07:06] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_084_pad_ctrl_MASK 0x000000c0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_084_pad_ctrl_SHIFT 6
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_084_pad_ctrl_DEFAULT 0x00000001
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_084_pad_ctrl_PULL_NONE 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_084_pad_ctrl_PULL_DOWN 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_084_pad_ctrl_PULL_UP 2
-
-/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_9 :: gpio_083_pad_ctrl [05:04] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_083_pad_ctrl_MASK 0x00000030
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_083_pad_ctrl_SHIFT 4
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_083_pad_ctrl_DEFAULT 0x00000001
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_083_pad_ctrl_PULL_NONE 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_083_pad_ctrl_PULL_DOWN 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_083_pad_ctrl_PULL_UP 2
-
-/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_9 :: gpio_082_pad_ctrl [03:02] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_082_pad_ctrl_MASK 0x0000000c
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_082_pad_ctrl_SHIFT 2
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_082_pad_ctrl_DEFAULT 0x00000001
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_082_pad_ctrl_PULL_NONE 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_082_pad_ctrl_PULL_DOWN 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_082_pad_ctrl_PULL_UP 2
-
-/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_9 :: gpio_081_pad_ctrl [01:00] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_081_pad_ctrl_MASK 0x00000003
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_081_pad_ctrl_SHIFT 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_081_pad_ctrl_DEFAULT 0x00000001
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_081_pad_ctrl_PULL_NONE 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_081_pad_ctrl_PULL_DOWN 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_081_pad_ctrl_PULL_UP 2
-
-/***************************************************************************
- *PIN_MUX_PAD_CTRL_10 - Pad pull-up/pull-down control register 10
- ***************************************************************************/
-/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_10 :: spare_pad_ctrl_10 [31:30] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_spare_pad_ctrl_10_MASK 0xc0000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_spare_pad_ctrl_10_SHIFT 30
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_spare_pad_ctrl_10_DEFAULT 0x00000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_spare_pad_ctrl_10_PULL_NONE 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_spare_pad_ctrl_10_PULL_DOWN 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_spare_pad_ctrl_10_PULL_UP 2
-
-/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_10 :: reserved0 [29:24] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_reserved0_MASK 0x3f000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_reserved0_SHIFT 24
-
-/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_10 :: gpio_107_pad_ctrl [23:22] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_107_pad_ctrl_MASK 0x00c00000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_107_pad_ctrl_SHIFT 22
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_107_pad_ctrl_DEFAULT 0x00000001
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_107_pad_ctrl_PULL_NONE 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_107_pad_ctrl_PULL_DOWN 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_107_pad_ctrl_PULL_UP 2
-
-/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_10 :: gpio_106_pad_ctrl [21:20] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_106_pad_ctrl_MASK 0x00300000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_106_pad_ctrl_SHIFT 20
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_106_pad_ctrl_DEFAULT 0x00000001
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_106_pad_ctrl_PULL_NONE 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_106_pad_ctrl_PULL_DOWN 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_106_pad_ctrl_PULL_UP 2
-
-/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_10 :: gpio_105_pad_ctrl [19:18] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_105_pad_ctrl_MASK 0x000c0000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_105_pad_ctrl_SHIFT 18
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_105_pad_ctrl_DEFAULT 0x00000001
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_105_pad_ctrl_PULL_NONE 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_105_pad_ctrl_PULL_DOWN 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_105_pad_ctrl_PULL_UP 2
-
-/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_10 :: gpio_104_pad_ctrl [17:16] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_104_pad_ctrl_MASK 0x00030000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_104_pad_ctrl_SHIFT 16
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_104_pad_ctrl_DEFAULT 0x00000001
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_104_pad_ctrl_PULL_NONE 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_104_pad_ctrl_PULL_DOWN 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_104_pad_ctrl_PULL_UP 2
-
-/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_10 :: gpio_103_pad_ctrl [15:14] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_103_pad_ctrl_MASK 0x0000c000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_103_pad_ctrl_SHIFT 14
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_103_pad_ctrl_DEFAULT 0x00000001
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_103_pad_ctrl_PULL_NONE 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_103_pad_ctrl_PULL_DOWN 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_103_pad_ctrl_PULL_UP 2
-
-/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_10 :: gpio_102_pad_ctrl [13:12] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_102_pad_ctrl_MASK 0x00003000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_102_pad_ctrl_SHIFT 12
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_102_pad_ctrl_DEFAULT 0x00000001
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_102_pad_ctrl_PULL_NONE 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_102_pad_ctrl_PULL_DOWN 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_102_pad_ctrl_PULL_UP 2
-
-/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_10 :: gpio_101_pad_ctrl [11:10] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_101_pad_ctrl_MASK 0x00000c00
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_101_pad_ctrl_SHIFT 10
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_101_pad_ctrl_DEFAULT 0x00000001
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_101_pad_ctrl_PULL_NONE 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_101_pad_ctrl_PULL_DOWN 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_101_pad_ctrl_PULL_UP 2
-
-/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_10 :: gpio_100_pad_ctrl [09:08] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_100_pad_ctrl_MASK 0x00000300
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_100_pad_ctrl_SHIFT 8
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_100_pad_ctrl_DEFAULT 0x00000001
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_100_pad_ctrl_PULL_NONE 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_100_pad_ctrl_PULL_DOWN 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_100_pad_ctrl_PULL_UP 2
-
-/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_10 :: gpio_099_pad_ctrl [07:06] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_099_pad_ctrl_MASK 0x000000c0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_099_pad_ctrl_SHIFT 6
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_099_pad_ctrl_DEFAULT 0x00000001
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_099_pad_ctrl_PULL_NONE 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_099_pad_ctrl_PULL_DOWN 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_099_pad_ctrl_PULL_UP 2
-
-/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_10 :: gpio_098_pad_ctrl [05:04] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_098_pad_ctrl_MASK 0x00000030
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_098_pad_ctrl_SHIFT 4
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_098_pad_ctrl_DEFAULT 0x00000001
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_098_pad_ctrl_PULL_NONE 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_098_pad_ctrl_PULL_DOWN 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_098_pad_ctrl_PULL_UP 2
-
-/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_10 :: gpio_097_pad_ctrl [03:02] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_097_pad_ctrl_MASK 0x0000000c
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_097_pad_ctrl_SHIFT 2
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_097_pad_ctrl_DEFAULT 0x00000001
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_097_pad_ctrl_PULL_NONE 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_097_pad_ctrl_PULL_DOWN 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_097_pad_ctrl_PULL_UP 2
-
-/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_10 :: gpio_096_pad_ctrl [01:00] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_096_pad_ctrl_MASK 0x00000003
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_096_pad_ctrl_SHIFT 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_096_pad_ctrl_DEFAULT 0x00000001
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_096_pad_ctrl_PULL_NONE 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_096_pad_ctrl_PULL_DOWN 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_096_pad_ctrl_PULL_UP 2
-
-/***************************************************************************
- *PIN_MUX_PAD_CTRL_11 - Pad pull-up/pull-down control register 11
- ***************************************************************************/
-/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_11 :: spare_pad_ctrl_11 [31:30] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11_spare_pad_ctrl_11_MASK 0xc0000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11_spare_pad_ctrl_11_SHIFT 30
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11_spare_pad_ctrl_11_DEFAULT 0x00000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11_spare_pad_ctrl_11_PULL_NONE 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11_spare_pad_ctrl_11_PULL_DOWN 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11_spare_pad_ctrl_11_PULL_UP 2
-
-/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_11 :: gpio_125_pad_ctrl [29:28] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11_gpio_125_pad_ctrl_MASK 0x30000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11_gpio_125_pad_ctrl_SHIFT 28
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11_gpio_125_pad_ctrl_DEFAULT 0x00000001
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11_gpio_125_pad_ctrl_PULL_NONE 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11_gpio_125_pad_ctrl_PULL_DOWN 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11_gpio_125_pad_ctrl_PULL_UP 2
-
-/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_11 :: gpio_124_pad_ctrl [27:26] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11_gpio_124_pad_ctrl_MASK 0x0c000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11_gpio_124_pad_ctrl_SHIFT 26
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11_gpio_124_pad_ctrl_DEFAULT 0x00000001
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11_gpio_124_pad_ctrl_PULL_NONE 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11_gpio_124_pad_ctrl_PULL_DOWN 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11_gpio_124_pad_ctrl_PULL_UP 2
-
-/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_11 :: gpio_123_pad_ctrl [25:24] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11_gpio_123_pad_ctrl_MASK 0x03000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11_gpio_123_pad_ctrl_SHIFT 24
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11_gpio_123_pad_ctrl_DEFAULT 0x00000001
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11_gpio_123_pad_ctrl_PULL_NONE 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11_gpio_123_pad_ctrl_PULL_DOWN 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11_gpio_123_pad_ctrl_PULL_UP 2
-
-/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_11 :: gpio_122_pad_ctrl [23:22] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11_gpio_122_pad_ctrl_MASK 0x00c00000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11_gpio_122_pad_ctrl_SHIFT 22
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11_gpio_122_pad_ctrl_DEFAULT 0x00000001
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11_gpio_122_pad_ctrl_PULL_NONE 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11_gpio_122_pad_ctrl_PULL_DOWN 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11_gpio_122_pad_ctrl_PULL_UP 2
-
-/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_11 :: gpio_121_pad_ctrl [21:20] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11_gpio_121_pad_ctrl_MASK 0x00300000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11_gpio_121_pad_ctrl_SHIFT 20
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11_gpio_121_pad_ctrl_DEFAULT 0x00000001
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11_gpio_121_pad_ctrl_PULL_NONE 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11_gpio_121_pad_ctrl_PULL_DOWN 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11_gpio_121_pad_ctrl_PULL_UP 2
-
-/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_11 :: gpio_120_pad_ctrl [19:18] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11_gpio_120_pad_ctrl_MASK 0x000c0000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11_gpio_120_pad_ctrl_SHIFT 18
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11_gpio_120_pad_ctrl_DEFAULT 0x00000001
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11_gpio_120_pad_ctrl_PULL_NONE 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11_gpio_120_pad_ctrl_PULL_DOWN 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11_gpio_120_pad_ctrl_PULL_UP 2
-
-/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_11 :: gpio_119_pad_ctrl [17:16] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11_gpio_119_pad_ctrl_MASK 0x00030000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11_gpio_119_pad_ctrl_SHIFT 16
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11_gpio_119_pad_ctrl_DEFAULT 0x00000001
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11_gpio_119_pad_ctrl_PULL_NONE 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11_gpio_119_pad_ctrl_PULL_DOWN 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11_gpio_119_pad_ctrl_PULL_UP 2
-
-/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_11 :: gpio_118_pad_ctrl [15:14] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11_gpio_118_pad_ctrl_MASK 0x0000c000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11_gpio_118_pad_ctrl_SHIFT 14
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11_gpio_118_pad_ctrl_DEFAULT 0x00000001
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11_gpio_118_pad_ctrl_PULL_NONE 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11_gpio_118_pad_ctrl_PULL_DOWN 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11_gpio_118_pad_ctrl_PULL_UP 2
-
-/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_11 :: gpio_117_pad_ctrl [13:12] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11_gpio_117_pad_ctrl_MASK 0x00003000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11_gpio_117_pad_ctrl_SHIFT 12
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11_gpio_117_pad_ctrl_DEFAULT 0x00000001
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11_gpio_117_pad_ctrl_PULL_NONE 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11_gpio_117_pad_ctrl_PULL_DOWN 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11_gpio_117_pad_ctrl_PULL_UP 2
-
-/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_11 :: gpio_116_pad_ctrl [11:10] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11_gpio_116_pad_ctrl_MASK 0x00000c00
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11_gpio_116_pad_ctrl_SHIFT 10
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11_gpio_116_pad_ctrl_DEFAULT 0x00000001
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11_gpio_116_pad_ctrl_PULL_NONE 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11_gpio_116_pad_ctrl_PULL_DOWN 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11_gpio_116_pad_ctrl_PULL_UP 2
-
-/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_11 :: gpio_115_pad_ctrl [09:08] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11_gpio_115_pad_ctrl_MASK 0x00000300
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11_gpio_115_pad_ctrl_SHIFT 8
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11_gpio_115_pad_ctrl_DEFAULT 0x00000001
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11_gpio_115_pad_ctrl_PULL_NONE 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11_gpio_115_pad_ctrl_PULL_DOWN 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11_gpio_115_pad_ctrl_PULL_UP 2
-
-/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_11 :: gpio_114_pad_ctrl [07:06] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11_gpio_114_pad_ctrl_MASK 0x000000c0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11_gpio_114_pad_ctrl_SHIFT 6
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11_gpio_114_pad_ctrl_DEFAULT 0x00000001
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11_gpio_114_pad_ctrl_PULL_NONE 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11_gpio_114_pad_ctrl_PULL_DOWN 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11_gpio_114_pad_ctrl_PULL_UP 2
-
-/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_11 :: gpio_113_pad_ctrl [05:04] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11_gpio_113_pad_ctrl_MASK 0x00000030
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11_gpio_113_pad_ctrl_SHIFT 4
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11_gpio_113_pad_ctrl_DEFAULT 0x00000001
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11_gpio_113_pad_ctrl_PULL_NONE 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11_gpio_113_pad_ctrl_PULL_DOWN 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11_gpio_113_pad_ctrl_PULL_UP 2
-
-/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_11 :: gpio_112_pad_ctrl [03:02] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11_gpio_112_pad_ctrl_MASK 0x0000000c
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11_gpio_112_pad_ctrl_SHIFT 2
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11_gpio_112_pad_ctrl_DEFAULT 0x00000001
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11_gpio_112_pad_ctrl_PULL_NONE 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11_gpio_112_pad_ctrl_PULL_DOWN 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11_gpio_112_pad_ctrl_PULL_UP 2
-
-/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_11 :: gpio_111_pad_ctrl [01:00] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11_gpio_111_pad_ctrl_MASK 0x00000003
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11_gpio_111_pad_ctrl_SHIFT 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11_gpio_111_pad_ctrl_DEFAULT 0x00000001
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11_gpio_111_pad_ctrl_PULL_NONE 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11_gpio_111_pad_ctrl_PULL_DOWN 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11_gpio_111_pad_ctrl_PULL_UP 2
-
-/***************************************************************************
- *PIN_MUX_PAD_CTRL_12 - Pad pull-up/pull-down control register 12
- ***************************************************************************/
-/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_12 :: spare_pad_ctrl_12 [31:30] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_12_spare_pad_ctrl_12_MASK 0xc0000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_12_spare_pad_ctrl_12_SHIFT 30
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_12_spare_pad_ctrl_12_DEFAULT 0x00000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_12_spare_pad_ctrl_12_PULL_NONE 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_12_spare_pad_ctrl_12_PULL_DOWN 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_12_spare_pad_ctrl_12_PULL_UP 2
-
-/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_12 :: reserved0 [29:10] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_12_reserved0_MASK 0x3ffffc00
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_12_reserved0_SHIFT 10
-
-/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_12 :: gpio_130_pad_ctrl [09:08] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_12_gpio_130_pad_ctrl_MASK 0x00000300
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_12_gpio_130_pad_ctrl_SHIFT 8
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_12_gpio_130_pad_ctrl_DEFAULT 0x00000001
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_12_gpio_130_pad_ctrl_PULL_NONE 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_12_gpio_130_pad_ctrl_PULL_DOWN 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_12_gpio_130_pad_ctrl_PULL_UP 2
-
-/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_12 :: gpio_129_pad_ctrl [07:06] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_12_gpio_129_pad_ctrl_MASK 0x000000c0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_12_gpio_129_pad_ctrl_SHIFT 6
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_12_gpio_129_pad_ctrl_DEFAULT 0x00000001
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_12_gpio_129_pad_ctrl_PULL_NONE 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_12_gpio_129_pad_ctrl_PULL_DOWN 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_12_gpio_129_pad_ctrl_PULL_UP 2
-
-/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_12 :: gpio_128_pad_ctrl [05:04] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_12_gpio_128_pad_ctrl_MASK 0x00000030
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_12_gpio_128_pad_ctrl_SHIFT 4
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_12_gpio_128_pad_ctrl_DEFAULT 0x00000001
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_12_gpio_128_pad_ctrl_PULL_NONE 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_12_gpio_128_pad_ctrl_PULL_DOWN 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_12_gpio_128_pad_ctrl_PULL_UP 2
-
-/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_12 :: gpio_127_pad_ctrl [03:02] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_12_gpio_127_pad_ctrl_MASK 0x0000000c
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_12_gpio_127_pad_ctrl_SHIFT 2
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_12_gpio_127_pad_ctrl_DEFAULT 0x00000001
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_12_gpio_127_pad_ctrl_PULL_NONE 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_12_gpio_127_pad_ctrl_PULL_DOWN 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_12_gpio_127_pad_ctrl_PULL_UP 2
-
-/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_12 :: gpio_126_pad_ctrl [01:00] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_12_gpio_126_pad_ctrl_MASK 0x00000003
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_12_gpio_126_pad_ctrl_SHIFT 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_12_gpio_126_pad_ctrl_DEFAULT 0x00000001
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_12_gpio_126_pad_ctrl_PULL_NONE 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_12_gpio_126_pad_ctrl_PULL_DOWN 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_12_gpio_126_pad_ctrl_PULL_UP 2
-
-/***************************************************************************
- *PIN_MUX_PAD_CTRL_13 - Pad pull-up/pull-down control register 13
- ***************************************************************************/
-/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_13 :: reserved0 [31:26] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_13_reserved0_MASK 0xfc000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_13_reserved0_SHIFT 26
-
-/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_13 :: spare_pad_ctrl_13 [25:24] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_13_spare_pad_ctrl_13_MASK 0x03000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_13_spare_pad_ctrl_13_SHIFT 24
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_13_spare_pad_ctrl_13_DEFAULT 0x00000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_13_spare_pad_ctrl_13_PULL_NONE 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_13_spare_pad_ctrl_13_PULL_DOWN 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_13_spare_pad_ctrl_13_PULL_UP 2
-
-/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_13 :: reserved1 [23:00] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_13_reserved1_MASK 0x00ffffff
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_13_reserved1_SHIFT 0
-
-/***************************************************************************
- *BYP_CLK_UNSELECT_0 - Bypass clock unselect register 0
- ***************************************************************************/
-/* SUN_TOP_CTRL :: BYP_CLK_UNSELECT_0 :: reserved0 [31:16] */
-#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_reserved0_MASK 0xffff0000
-#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_reserved0_SHIFT 16
-
-/* SUN_TOP_CTRL :: BYP_CLK_UNSELECT_0 :: unsel_byp_clk_on_byp_clk_15 [15:15] */
-#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_byp_clk_15_MASK 0x00008000
-#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_byp_clk_15_SHIFT 15
-#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_byp_clk_15_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: BYP_CLK_UNSELECT_0 :: unsel_byp_clk_on_byp_clk_14 [14:14] */
-#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_byp_clk_14_MASK 0x00004000
-#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_byp_clk_14_SHIFT 14
-#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_byp_clk_14_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: BYP_CLK_UNSELECT_0 :: unsel_byp_clk_on_byp_clk_13 [13:13] */
-#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_byp_clk_13_MASK 0x00002000
-#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_byp_clk_13_SHIFT 13
-#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_byp_clk_13_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: BYP_CLK_UNSELECT_0 :: unsel_byp_clk_on_byp_clk_12 [12:12] */
-#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_byp_clk_12_MASK 0x00001000
-#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_byp_clk_12_SHIFT 12
-#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_byp_clk_12_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: BYP_CLK_UNSELECT_0 :: unsel_byp_clk_on_byp_clk_11 [11:11] */
-#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_byp_clk_11_MASK 0x00000800
-#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_byp_clk_11_SHIFT 11
-#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_byp_clk_11_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: BYP_CLK_UNSELECT_0 :: unsel_byp_clk_on_byp_clk_10 [10:10] */
-#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_byp_clk_10_MASK 0x00000400
-#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_byp_clk_10_SHIFT 10
-#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_byp_clk_10_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: BYP_CLK_UNSELECT_0 :: unsel_byp_clk_on_byp_clk_9 [09:09] */
-#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_byp_clk_9_MASK 0x00000200
-#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_byp_clk_9_SHIFT 9
-#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_byp_clk_9_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: BYP_CLK_UNSELECT_0 :: unsel_byp_clk_on_byp_clk_8 [08:08] */
-#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_byp_clk_8_MASK 0x00000100
-#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_byp_clk_8_SHIFT 8
-#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_byp_clk_8_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: BYP_CLK_UNSELECT_0 :: unsel_byp_clk_on_byp_clk_7 [07:07] */
-#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_byp_clk_7_MASK 0x00000080
-#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_byp_clk_7_SHIFT 7
-#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_byp_clk_7_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: BYP_CLK_UNSELECT_0 :: unsel_byp_clk_on_byp_clk_6 [06:06] */
-#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_byp_clk_6_MASK 0x00000040
-#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_byp_clk_6_SHIFT 6
-#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_byp_clk_6_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: BYP_CLK_UNSELECT_0 :: unsel_byp_clk_on_byp_clk_5 [05:05] */
-#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_byp_clk_5_MASK 0x00000020
-#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_byp_clk_5_SHIFT 5
-#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_byp_clk_5_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: BYP_CLK_UNSELECT_0 :: unsel_byp_clk_on_byp_clk_4 [04:04] */
-#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_byp_clk_4_MASK 0x00000010
-#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_byp_clk_4_SHIFT 4
-#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_byp_clk_4_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: BYP_CLK_UNSELECT_0 :: unsel_byp_clk_on_byp_clk_3 [03:03] */
-#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_byp_clk_3_MASK 0x00000008
-#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_byp_clk_3_SHIFT 3
-#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_byp_clk_3_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: BYP_CLK_UNSELECT_0 :: unsel_byp_clk_on_byp_clk_2 [02:02] */
-#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_byp_clk_2_MASK 0x00000004
-#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_byp_clk_2_SHIFT 2
-#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_byp_clk_2_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: BYP_CLK_UNSELECT_0 :: unsel_byp_clk_on_byp_clk_1 [01:01] */
-#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_byp_clk_1_MASK 0x00000002
-#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_byp_clk_1_SHIFT 1
-#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_byp_clk_1_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: BYP_CLK_UNSELECT_0 :: unsel_byp_clk_on_byp_clk_0 [00:00] */
-#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_byp_clk_0_MASK 0x00000001
-#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_byp_clk_0_SHIFT 0
-#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_byp_clk_0_DEFAULT 0x00000000
-
-/***************************************************************************
- *RESET_CTRL - Reset control
- ***************************************************************************/
-/* SUN_TOP_CTRL :: RESET_CTRL :: reserved0 [31:01] */
-#define BCHP_SUN_TOP_CTRL_RESET_CTRL_reserved0_MASK 0xfffffffe
-#define BCHP_SUN_TOP_CTRL_RESET_CTRL_reserved0_SHIFT 1
-
-/* SUN_TOP_CTRL :: RESET_CTRL :: clear_reset_history [00:00] */
-#define BCHP_SUN_TOP_CTRL_RESET_CTRL_clear_reset_history_MASK 0x00000001
-#define BCHP_SUN_TOP_CTRL_RESET_CTRL_clear_reset_history_SHIFT 0
-#define BCHP_SUN_TOP_CTRL_RESET_CTRL_clear_reset_history_DEFAULT 0x00000000
-
-/***************************************************************************
- *RESET_SOURCE_ENABLE - Reset source enable
- ***************************************************************************/
-/* SUN_TOP_CTRL :: RESET_SOURCE_ENABLE :: reserved0 [31:10] */
-#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_reserved0_MASK 0xfffffc00
-#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_reserved0_SHIFT 10
-
-/* SUN_TOP_CTRL :: RESET_SOURCE_ENABLE :: aux_chip_level_reset_1_en_lock [09:09] */
-#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_level_reset_1_en_lock_MASK 0x00000200
-#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_level_reset_1_en_lock_SHIFT 9
-#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_level_reset_1_en_lock_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: RESET_SOURCE_ENABLE :: aux_chip_level_reset_1_enable [08:08] */
-#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_level_reset_1_enable_MASK 0x00000100
-#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_level_reset_1_enable_SHIFT 8
-#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_level_reset_1_enable_DEFAULT 0x00000001
-
-/* SUN_TOP_CTRL :: RESET_SOURCE_ENABLE :: aux_chip_level_reset_0_en_lock [07:07] */
-#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_level_reset_0_en_lock_MASK 0x00000080
-#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_level_reset_0_en_lock_SHIFT 7
-#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_level_reset_0_en_lock_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: RESET_SOURCE_ENABLE :: aux_chip_level_reset_0_enable [06:06] */
-#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_level_reset_0_enable_MASK 0x00000040
-#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_level_reset_0_enable_SHIFT 6
-#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_level_reset_0_enable_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: RESET_SOURCE_ENABLE :: aux_chip_edge_reset_1_en_lock [05:05] */
-#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_edge_reset_1_en_lock_MASK 0x00000020
-#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_edge_reset_1_en_lock_SHIFT 5
-#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_edge_reset_1_en_lock_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: RESET_SOURCE_ENABLE :: aux_chip_edge_reset_1_enable [04:04] */
-#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_edge_reset_1_enable_MASK 0x00000010
-#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_edge_reset_1_enable_SHIFT 4
-#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_edge_reset_1_enable_DEFAULT 0x00000001
-
-/* SUN_TOP_CTRL :: RESET_SOURCE_ENABLE :: aux_chip_edge_reset_0_en_lock [03:03] */
-#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_edge_reset_0_en_lock_MASK 0x00000008
-#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_edge_reset_0_en_lock_SHIFT 3
-#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_edge_reset_0_en_lock_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: RESET_SOURCE_ENABLE :: aux_chip_edge_reset_0_enable [02:02] */
-#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_edge_reset_0_enable_MASK 0x00000004
-#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_edge_reset_0_enable_SHIFT 2
-#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_edge_reset_0_enable_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: RESET_SOURCE_ENABLE :: sw_master_reset_en_lock [01:01] */
-#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_sw_master_reset_en_lock_MASK 0x00000002
-#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_sw_master_reset_en_lock_SHIFT 1
-#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_sw_master_reset_en_lock_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: RESET_SOURCE_ENABLE :: sw_master_reset_enable [00:00] */
-#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_sw_master_reset_enable_MASK 0x00000001
-#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_sw_master_reset_enable_SHIFT 0
-#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_sw_master_reset_enable_DEFAULT 0x00000000
-
-/***************************************************************************
- *SW_MASTER_RESET - Software master reset
- ***************************************************************************/
-/* SUN_TOP_CTRL :: SW_MASTER_RESET :: reserved0 [31:01] */
-#define BCHP_SUN_TOP_CTRL_SW_MASTER_RESET_reserved0_MASK 0xfffffffe
-#define BCHP_SUN_TOP_CTRL_SW_MASTER_RESET_reserved0_SHIFT 1
-
-/* SUN_TOP_CTRL :: SW_MASTER_RESET :: chip_master_reset [00:00] */
-#define BCHP_SUN_TOP_CTRL_SW_MASTER_RESET_chip_master_reset_MASK 0x00000001
-#define BCHP_SUN_TOP_CTRL_SW_MASTER_RESET_chip_master_reset_SHIFT 0
-#define BCHP_SUN_TOP_CTRL_SW_MASTER_RESET_chip_master_reset_DEFAULT 0x00000000
-
-/***************************************************************************
- *HW_RESET_EXTENSION - Hardware reset extension
- ***************************************************************************/
-/* SUN_TOP_CTRL :: HW_RESET_EXTENSION :: reserved0 [31:28] */
-#define BCHP_SUN_TOP_CTRL_HW_RESET_EXTENSION_reserved0_MASK 0xf0000000
-#define BCHP_SUN_TOP_CTRL_HW_RESET_EXTENSION_reserved0_SHIFT 28
-
-/* SUN_TOP_CTRL :: HW_RESET_EXTENSION :: hw_reset_extension [27:00] */
-#define BCHP_SUN_TOP_CTRL_HW_RESET_EXTENSION_hw_reset_extension_MASK 0x0fffffff
-#define BCHP_SUN_TOP_CTRL_HW_RESET_EXTENSION_hw_reset_extension_SHIFT 0
-#define BCHP_SUN_TOP_CTRL_HW_RESET_EXTENSION_hw_reset_extension_DEFAULT 0x00000000
-
-/***************************************************************************
- *RESET_MONITOR - Reset Monitor
- ***************************************************************************/
-/* SUN_TOP_CTRL :: RESET_MONITOR :: reserved0 [31:08] */
-#define BCHP_SUN_TOP_CTRL_RESET_MONITOR_reserved0_MASK 0xffffff00
-#define BCHP_SUN_TOP_CTRL_RESET_MONITOR_reserved0_SHIFT 8
-
-/* SUN_TOP_CTRL :: RESET_MONITOR :: cpu_sw_init_def_val [07:07] */
-#define BCHP_SUN_TOP_CTRL_RESET_MONITOR_cpu_sw_init_def_val_MASK 0x00000080
-#define BCHP_SUN_TOP_CTRL_RESET_MONITOR_cpu_sw_init_def_val_SHIFT 7
-
-/* SUN_TOP_CTRL :: RESET_MONITOR :: reset_outb_def_val [06:06] */
-#define BCHP_SUN_TOP_CTRL_RESET_MONITOR_reset_outb_def_val_MASK 0x00000040
-#define BCHP_SUN_TOP_CTRL_RESET_MONITOR_reset_outb_def_val_SHIFT 6
-
-/* SUN_TOP_CTRL :: RESET_MONITOR :: hold_cpu_in_reset_monitor [05:05] */
-#define BCHP_SUN_TOP_CTRL_RESET_MONITOR_hold_cpu_in_reset_monitor_MASK 0x00000020
-#define BCHP_SUN_TOP_CTRL_RESET_MONITOR_hold_cpu_in_reset_monitor_SHIFT 5
-
-/* SUN_TOP_CTRL :: RESET_MONITOR :: reset_outb_monitor [04:04] */
-#define BCHP_SUN_TOP_CTRL_RESET_MONITOR_reset_outb_monitor_MASK 0x00000010
-#define BCHP_SUN_TOP_CTRL_RESET_MONITOR_reset_outb_monitor_SHIFT 4
-
-/* SUN_TOP_CTRL :: RESET_MONITOR :: front_panel_reset_monitor [03:03] */
-#define BCHP_SUN_TOP_CTRL_RESET_MONITOR_front_panel_reset_monitor_MASK 0x00000008
-#define BCHP_SUN_TOP_CTRL_RESET_MONITOR_front_panel_reset_monitor_SHIFT 3
-
-/* SUN_TOP_CTRL :: RESET_MONITOR :: reset_ext_mode_monitor [02:02] */
-#define BCHP_SUN_TOP_CTRL_RESET_MONITOR_reset_ext_mode_monitor_MASK 0x00000004
-#define BCHP_SUN_TOP_CTRL_RESET_MONITOR_reset_ext_mode_monitor_SHIFT 2
-
-/* SUN_TOP_CTRL :: RESET_MONITOR :: phase5_reset_timer_monitor [01:01] */
-#define BCHP_SUN_TOP_CTRL_RESET_MONITOR_phase5_reset_timer_monitor_MASK 0x00000002
-#define BCHP_SUN_TOP_CTRL_RESET_MONITOR_phase5_reset_timer_monitor_SHIFT 1
-
-/* SUN_TOP_CTRL :: RESET_MONITOR :: phase4_reset_timer_monitor [00:00] */
-#define BCHP_SUN_TOP_CTRL_RESET_MONITOR_phase4_reset_timer_monitor_MASK 0x00000001
-#define BCHP_SUN_TOP_CTRL_RESET_MONITOR_phase4_reset_timer_monitor_SHIFT 0
-
-/***************************************************************************
- *RESET_HISTORY - Reset history
- ***************************************************************************/
-/* SUN_TOP_CTRL :: RESET_HISTORY :: reserved0 [31:20] */
-#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_reserved0_MASK 0xfff00000
-#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_reserved0_SHIFT 20
-
-/* SUN_TOP_CTRL :: RESET_HISTORY :: aux_chip_level_reset_1 [19:19] */
-#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_aux_chip_level_reset_1_MASK 0x00080000
-#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_aux_chip_level_reset_1_SHIFT 19
-
-/* SUN_TOP_CTRL :: RESET_HISTORY :: aux_chip_level_reset_0 [18:18] */
-#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_aux_chip_level_reset_0_MASK 0x00040000
-#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_aux_chip_level_reset_0_SHIFT 18
-
-/* SUN_TOP_CTRL :: RESET_HISTORY :: aux_chip_edge_reset_1 [17:17] */
-#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_aux_chip_edge_reset_1_MASK 0x00020000
-#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_aux_chip_edge_reset_1_SHIFT 17
-
-/* SUN_TOP_CTRL :: RESET_HISTORY :: aux_chip_edge_reset_0 [16:16] */
-#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_aux_chip_edge_reset_0_MASK 0x00010000
-#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_aux_chip_edge_reset_0_SHIFT 16
-
-/* SUN_TOP_CTRL :: RESET_HISTORY :: gen_watchdog_1_reset [15:15] */
-#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_gen_watchdog_1_reset_MASK 0x00008000
-#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_gen_watchdog_1_reset_SHIFT 15
-#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_gen_watchdog_1_reset_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: RESET_HISTORY :: undervoltage_0_reset [14:14] */
-#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_undervoltage_0_reset_MASK 0x00004000
-#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_undervoltage_0_reset_SHIFT 14
-
-/* SUN_TOP_CTRL :: RESET_HISTORY :: undervoltage_1_reset [13:13] */
-#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_undervoltage_1_reset_MASK 0x00002000
-#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_undervoltage_1_reset_SHIFT 13
-
-/* SUN_TOP_CTRL :: RESET_HISTORY :: overvoltage_1_reset [12:12] */
-#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_overvoltage_1_reset_MASK 0x00001000
-#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_overvoltage_1_reset_SHIFT 12
-
-/* SUN_TOP_CTRL :: RESET_HISTORY :: overtemp_reset [11:11] */
-#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_overtemp_reset_MASK 0x00000800
-#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_overtemp_reset_SHIFT 11
-
-/* SUN_TOP_CTRL :: RESET_HISTORY :: scpu_ejtag_reset [10:10] */
-#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_scpu_ejtag_reset_MASK 0x00000400
-#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_scpu_ejtag_reset_SHIFT 10
-
-/* SUN_TOP_CTRL :: RESET_HISTORY :: cpu_ejtag_reset [09:09] */
-#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_cpu_ejtag_reset_MASK 0x00000200
-#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_cpu_ejtag_reset_SHIFT 9
-
-/* SUN_TOP_CTRL :: RESET_HISTORY :: security_master_reset [08:08] */
-#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_security_master_reset_MASK 0x00000100
-#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_security_master_reset_SHIFT 8
-
-/* SUN_TOP_CTRL :: RESET_HISTORY :: software_master_reset [07:07] */
-#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_software_master_reset_MASK 0x00000080
-#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_software_master_reset_SHIFT 7
-
-/* SUN_TOP_CTRL :: RESET_HISTORY :: front_panel_4sec_reset [06:06] */
-#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_front_panel_4sec_reset_MASK 0x00000040
-#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_front_panel_4sec_reset_SHIFT 6
-
-/* SUN_TOP_CTRL :: RESET_HISTORY :: pcie_1_hot_boot_reset [05:05] */
-#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_pcie_1_hot_boot_reset_MASK 0x00000020
-#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_pcie_1_hot_boot_reset_SHIFT 5
-
-/* SUN_TOP_CTRL :: RESET_HISTORY :: pcie_0_hot_boot_reset [04:04] */
-#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_pcie_0_hot_boot_reset_MASK 0x00000010
-#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_pcie_0_hot_boot_reset_SHIFT 4
-
-/* SUN_TOP_CTRL :: RESET_HISTORY :: watchdog_timer_reset [03:03] */
-#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_watchdog_timer_reset_MASK 0x00000008
-#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_watchdog_timer_reset_SHIFT 3
-
-/* SUN_TOP_CTRL :: RESET_HISTORY :: smartcard_insert_reset [02:02] */
-#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_smartcard_insert_reset_MASK 0x00000004
-#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_smartcard_insert_reset_SHIFT 2
-
-/* SUN_TOP_CTRL :: RESET_HISTORY :: main_chip_reset_input [01:01] */
-#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_main_chip_reset_input_MASK 0x00000002
-#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_main_chip_reset_input_SHIFT 1
-
-/* SUN_TOP_CTRL :: RESET_HISTORY :: power_on_reset [00:00] */
-#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_power_on_reset_MASK 0x00000001
-#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_power_on_reset_SHIFT 0
-
-/***************************************************************************
- *SW_INIT_0_SET - Software init 0 set
- ***************************************************************************/
-/* SUN_TOP_CTRL :: SW_INIT_0_SET :: reserved_for_padding0 [31:31] */
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_reserved_for_padding0_MASK 0x80000000
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_reserved_for_padding0_SHIFT 31
-
-/* SUN_TOP_CTRL :: SW_INIT_0_SET :: not_used_sw_init_30 [30:30] */
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_30_MASK 0x40000000
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_30_SHIFT 30
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_30_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: SW_INIT_0_SET :: sata_sw_init [29:29] */
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_sata_sw_init_MASK 0x20000000
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_sata_sw_init_SHIFT 29
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_sata_sw_init_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: SW_INIT_0_SET :: moca_sw_init [28:28] */
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_moca_sw_init_MASK 0x10000000
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_moca_sw_init_SHIFT 28
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_moca_sw_init_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: SW_INIT_0_SET :: genet1_sw_init [27:27] */
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_genet1_sw_init_MASK 0x08000000
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_genet1_sw_init_SHIFT 27
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_genet1_sw_init_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: SW_INIT_0_SET :: genet0_sw_init [26:26] */
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_genet0_sw_init_MASK 0x04000000
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_genet0_sw_init_SHIFT 26
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_genet0_sw_init_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: SW_INIT_0_SET :: usb1_sw_init [25:25] */
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_usb1_sw_init_MASK 0x02000000
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_usb1_sw_init_SHIFT 25
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_usb1_sw_init_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: SW_INIT_0_SET :: usb0_sw_init [24:24] */
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_usb0_sw_init_MASK 0x01000000
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_usb0_sw_init_SHIFT 24
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_usb0_sw_init_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: SW_INIT_0_SET :: not_used_sw_init_23 [23:23] */
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_23_MASK 0x00800000
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_23_SHIFT 23
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_23_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: SW_INIT_0_SET :: ddr1_sw_init [22:22] */
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_ddr1_sw_init_MASK 0x00400000
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_ddr1_sw_init_SHIFT 22
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_ddr1_sw_init_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: SW_INIT_0_SET :: ddr0_sw_init [21:21] */
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_ddr0_sw_init_MASK 0x00200000
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_ddr0_sw_init_SHIFT 21
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_ddr0_sw_init_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: SW_INIT_0_SET :: memc1_sw_init [20:20] */
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_memc1_sw_init_MASK 0x00100000
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_memc1_sw_init_SHIFT 20
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_memc1_sw_init_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: SW_INIT_0_SET :: memc0_sw_init [19:19] */
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_memc0_sw_init_MASK 0x00080000
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_memc0_sw_init_SHIFT 19
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_memc0_sw_init_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: SW_INIT_0_SET :: xpt_sw_init [18:18] */
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_xpt_sw_init_MASK 0x00040000
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_xpt_sw_init_SHIFT 18
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_xpt_sw_init_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: SW_INIT_0_SET :: not_used_sw_init_17 [17:17] */
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_17_MASK 0x00020000
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_17_SHIFT 17
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_17_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: SW_INIT_0_SET :: raaga0_sw_init [16:16] */
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_raaga0_sw_init_MASK 0x00010000
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_raaga0_sw_init_SHIFT 16
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_raaga0_sw_init_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: SW_INIT_0_SET :: aio_sw_init [15:15] */
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_aio_sw_init_MASK 0x00008000
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_aio_sw_init_SHIFT 15
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_aio_sw_init_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: SW_INIT_0_SET :: gfx_sw_init [14:14] */
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_gfx_sw_init_MASK 0x00004000
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_gfx_sw_init_SHIFT 14
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_gfx_sw_init_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: SW_INIT_0_SET :: not_used_sw_init_13 [13:13] */
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_13_MASK 0x00002000
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_13_SHIFT 13
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_13_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: SW_INIT_0_SET :: hvd0_sw_init [12:12] */
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_hvd0_sw_init_MASK 0x00001000
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_hvd0_sw_init_SHIFT 12
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_hvd0_sw_init_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: SW_INIT_0_SET :: reserved_for_padding1 [11:11] */
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_reserved_for_padding1_MASK 0x00000800
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_reserved_for_padding1_SHIFT 11
-
-/* SUN_TOP_CTRL :: SW_INIT_0_SET :: dvp_ht0_sw_init [10:10] */
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_dvp_ht0_sw_init_MASK 0x00000400
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_dvp_ht0_sw_init_SHIFT 10
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_dvp_ht0_sw_init_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: SW_INIT_0_SET :: vec_sw_init [09:09] */
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_vec_sw_init_MASK 0x00000200
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_vec_sw_init_SHIFT 9
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_vec_sw_init_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: SW_INIT_0_SET :: bvn_sw_init [08:08] */
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_bvn_sw_init_MASK 0x00000100
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_bvn_sw_init_SHIFT 8
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_bvn_sw_init_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: SW_INIT_0_SET :: pcie1_sw_init [07:07] */
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_pcie1_sw_init_MASK 0x00000080
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_pcie1_sw_init_SHIFT 7
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_pcie1_sw_init_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: SW_INIT_0_SET :: ebi_sw_init [06:06] */
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_ebi_sw_init_MASK 0x00000040
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_ebi_sw_init_SHIFT 6
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_ebi_sw_init_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: SW_INIT_0_SET :: pcie0_sw_init [05:05] */
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_pcie0_sw_init_MASK 0x00000020
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_pcie0_sw_init_SHIFT 5
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_pcie0_sw_init_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: SW_INIT_0_SET :: webcpu_start_sw_init [04:04] */
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_webcpu_start_sw_init_MASK 0x00000010
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_webcpu_start_sw_init_SHIFT 4
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_webcpu_start_sw_init_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: SW_INIT_0_SET :: webcpu_sw_init [03:03] */
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_webcpu_sw_init_MASK 0x00000008
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_webcpu_sw_init_SHIFT 3
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_webcpu_sw_init_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: SW_INIT_0_SET :: ext_sys_sw_init [02:02] */
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_ext_sys_sw_init_MASK 0x00000004
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_ext_sys_sw_init_SHIFT 2
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_ext_sys_sw_init_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: SW_INIT_0_SET :: cpu_sw_init [01:01] */
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_cpu_sw_init_MASK 0x00000002
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_cpu_sw_init_SHIFT 1
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_cpu_sw_init_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: SW_INIT_0_SET :: sys_ctrl_sw_init [00:00] */
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_sys_ctrl_sw_init_MASK 0x00000001
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_sys_ctrl_sw_init_SHIFT 0
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_sys_ctrl_sw_init_DEFAULT 0x00000000
-
-/***************************************************************************
- *SW_INIT_0_CLEAR - Software init 0 clear
- ***************************************************************************/
-/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: reserved_for_padding0 [31:31] */
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_reserved_for_padding0_MASK 0x80000000
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_reserved_for_padding0_SHIFT 31
-
-/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: not_used_sw_init_30 [30:30] */
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_30_MASK 0x40000000
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_30_SHIFT 30
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_30_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: sata_sw_init [29:29] */
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_sata_sw_init_MASK 0x20000000
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_sata_sw_init_SHIFT 29
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_sata_sw_init_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: moca_sw_init [28:28] */
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_moca_sw_init_MASK 0x10000000
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_moca_sw_init_SHIFT 28
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_moca_sw_init_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: genet1_sw_init [27:27] */
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_genet1_sw_init_MASK 0x08000000
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_genet1_sw_init_SHIFT 27
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_genet1_sw_init_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: genet0_sw_init [26:26] */
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_genet0_sw_init_MASK 0x04000000
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_genet0_sw_init_SHIFT 26
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_genet0_sw_init_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: usb1_sw_init [25:25] */
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_usb1_sw_init_MASK 0x02000000
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_usb1_sw_init_SHIFT 25
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_usb1_sw_init_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: usb0_sw_init [24:24] */
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_usb0_sw_init_MASK 0x01000000
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_usb0_sw_init_SHIFT 24
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_usb0_sw_init_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: not_used_sw_init_23 [23:23] */
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_23_MASK 0x00800000
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_23_SHIFT 23
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_23_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: ddr1_sw_init [22:22] */
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_ddr1_sw_init_MASK 0x00400000
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_ddr1_sw_init_SHIFT 22
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_ddr1_sw_init_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: ddr0_sw_init [21:21] */
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_ddr0_sw_init_MASK 0x00200000
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_ddr0_sw_init_SHIFT 21
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_ddr0_sw_init_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: memc1_sw_init [20:20] */
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_memc1_sw_init_MASK 0x00100000
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_memc1_sw_init_SHIFT 20
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_memc1_sw_init_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: memc0_sw_init [19:19] */
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_memc0_sw_init_MASK 0x00080000
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_memc0_sw_init_SHIFT 19
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_memc0_sw_init_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: xpt_sw_init [18:18] */
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_xpt_sw_init_MASK 0x00040000
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_xpt_sw_init_SHIFT 18
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_xpt_sw_init_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: not_used_sw_init_17 [17:17] */
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_17_MASK 0x00020000
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_17_SHIFT 17
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_17_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: raaga0_sw_init [16:16] */
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_raaga0_sw_init_MASK 0x00010000
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_raaga0_sw_init_SHIFT 16
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_raaga0_sw_init_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: aio_sw_init [15:15] */
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_aio_sw_init_MASK 0x00008000
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_aio_sw_init_SHIFT 15
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_aio_sw_init_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: gfx_sw_init [14:14] */
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_gfx_sw_init_MASK 0x00004000
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_gfx_sw_init_SHIFT 14
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_gfx_sw_init_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: not_used_sw_init_13 [13:13] */
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_13_MASK 0x00002000
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_13_SHIFT 13
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_13_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: hvd0_sw_init [12:12] */
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_hvd0_sw_init_MASK 0x00001000
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_hvd0_sw_init_SHIFT 12
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_hvd0_sw_init_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: reserved_for_padding1 [11:11] */
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_reserved_for_padding1_MASK 0x00000800
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_reserved_for_padding1_SHIFT 11
-
-/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: dvp_ht0_sw_init [10:10] */
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_dvp_ht0_sw_init_MASK 0x00000400
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_dvp_ht0_sw_init_SHIFT 10
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_dvp_ht0_sw_init_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: vec_sw_init [09:09] */
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_vec_sw_init_MASK 0x00000200
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_vec_sw_init_SHIFT 9
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_vec_sw_init_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: bvn_sw_init [08:08] */
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_bvn_sw_init_MASK 0x00000100
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_bvn_sw_init_SHIFT 8
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_bvn_sw_init_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: pcie1_sw_init [07:07] */
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_pcie1_sw_init_MASK 0x00000080
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_pcie1_sw_init_SHIFT 7
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_pcie1_sw_init_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: ebi_sw_init [06:06] */
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_ebi_sw_init_MASK 0x00000040
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_ebi_sw_init_SHIFT 6
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_ebi_sw_init_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: pcie0_sw_init [05:05] */
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_pcie0_sw_init_MASK 0x00000020
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_pcie0_sw_init_SHIFT 5
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_pcie0_sw_init_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: webcpu_start_sw_init [04:04] */
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_webcpu_start_sw_init_MASK 0x00000010
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_webcpu_start_sw_init_SHIFT 4
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_webcpu_start_sw_init_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: webcpu_sw_init [03:03] */
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_webcpu_sw_init_MASK 0x00000008
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_webcpu_sw_init_SHIFT 3
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_webcpu_sw_init_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: ext_sys_sw_init [02:02] */
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_ext_sys_sw_init_MASK 0x00000004
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_ext_sys_sw_init_SHIFT 2
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_ext_sys_sw_init_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: cpu_sw_init [01:01] */
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_cpu_sw_init_MASK 0x00000002
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_cpu_sw_init_SHIFT 1
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_cpu_sw_init_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: sys_ctrl_sw_init [00:00] */
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_sys_ctrl_sw_init_MASK 0x00000001
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_sys_ctrl_sw_init_SHIFT 0
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_sys_ctrl_sw_init_DEFAULT 0x00000000
-
-/***************************************************************************
- *SW_INIT_0_STATUS - Software init 0 status
- ***************************************************************************/
-/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: reserved_for_padding0 [31:31] */
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_reserved_for_padding0_MASK 0x80000000
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_reserved_for_padding0_SHIFT 31
-
-/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: not_used_sw_init_30 [30:30] */
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_30_MASK 0x40000000
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_30_SHIFT 30
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_30_DEFAULT 0x00000001
-
-/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: sata_sw_init [29:29] */
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_sata_sw_init_MASK 0x20000000
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_sata_sw_init_SHIFT 29
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_sata_sw_init_DEFAULT 0x00000001
-
-/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: moca_sw_init [28:28] */
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_moca_sw_init_MASK 0x10000000
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_moca_sw_init_SHIFT 28
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_moca_sw_init_DEFAULT 0x00000001
-
-/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: genet1_sw_init [27:27] */
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_genet1_sw_init_MASK 0x08000000
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_genet1_sw_init_SHIFT 27
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_genet1_sw_init_DEFAULT 0x00000001
-
-/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: genet0_sw_init [26:26] */
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_genet0_sw_init_MASK 0x04000000
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_genet0_sw_init_SHIFT 26
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_genet0_sw_init_DEFAULT 0x00000001
-
-/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: usb1_sw_init [25:25] */
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_usb1_sw_init_MASK 0x02000000
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_usb1_sw_init_SHIFT 25
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_usb1_sw_init_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: usb0_sw_init [24:24] */
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_usb0_sw_init_MASK 0x01000000
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_usb0_sw_init_SHIFT 24
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_usb0_sw_init_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: not_used_sw_init_23 [23:23] */
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_23_MASK 0x00800000
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_23_SHIFT 23
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_23_DEFAULT 0x00000001
-
-/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: ddr1_sw_init [22:22] */
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_ddr1_sw_init_MASK 0x00400000
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_ddr1_sw_init_SHIFT 22
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_ddr1_sw_init_DEFAULT 0x00000001
-
-/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: ddr0_sw_init [21:21] */
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_ddr0_sw_init_MASK 0x00200000
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_ddr0_sw_init_SHIFT 21
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_ddr0_sw_init_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: memc1_sw_init [20:20] */
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_memc1_sw_init_MASK 0x00100000
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_memc1_sw_init_SHIFT 20
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_memc1_sw_init_DEFAULT 0x00000001
-
-/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: memc0_sw_init [19:19] */
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_memc0_sw_init_MASK 0x00080000
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_memc0_sw_init_SHIFT 19
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_memc0_sw_init_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: xpt_sw_init [18:18] */
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_xpt_sw_init_MASK 0x00040000
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_xpt_sw_init_SHIFT 18
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_xpt_sw_init_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: not_used_sw_init_17 [17:17] */
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_17_MASK 0x00020000
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_17_SHIFT 17
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_17_DEFAULT 0x00000001
-
-/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: raaga0_sw_init [16:16] */
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_raaga0_sw_init_MASK 0x00010000
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_raaga0_sw_init_SHIFT 16
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_raaga0_sw_init_DEFAULT 0x00000001
-
-/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: aio_sw_init [15:15] */
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_aio_sw_init_MASK 0x00008000
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_aio_sw_init_SHIFT 15
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_aio_sw_init_DEFAULT 0x00000001
-
-/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: gfx_sw_init [14:14] */
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_gfx_sw_init_MASK 0x00004000
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_gfx_sw_init_SHIFT 14
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_gfx_sw_init_DEFAULT 0x00000001
-
-/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: not_used_sw_init_13 [13:13] */
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_13_MASK 0x00002000
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_13_SHIFT 13
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_13_DEFAULT 0x00000001
-
-/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: hvd0_sw_init [12:12] */
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_hvd0_sw_init_MASK 0x00001000
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_hvd0_sw_init_SHIFT 12
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_hvd0_sw_init_DEFAULT 0x00000001
-
-/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: reserved_for_padding1 [11:11] */
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_reserved_for_padding1_MASK 0x00000800
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_reserved_for_padding1_SHIFT 11
-
-/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: dvp_ht0_sw_init [10:10] */
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_dvp_ht0_sw_init_MASK 0x00000400
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_dvp_ht0_sw_init_SHIFT 10
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_dvp_ht0_sw_init_DEFAULT 0x00000001
-
-/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: vec_sw_init [09:09] */
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_vec_sw_init_MASK 0x00000200
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_vec_sw_init_SHIFT 9
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_vec_sw_init_DEFAULT 0x00000001
-
-/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: bvn_sw_init [08:08] */
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_bvn_sw_init_MASK 0x00000100
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_bvn_sw_init_SHIFT 8
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_bvn_sw_init_DEFAULT 0x00000001
-
-/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: pcie1_sw_init [07:07] */
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_pcie1_sw_init_MASK 0x00000080
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_pcie1_sw_init_SHIFT 7
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_pcie1_sw_init_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: ebi_sw_init [06:06] */
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_ebi_sw_init_MASK 0x00000040
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_ebi_sw_init_SHIFT 6
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_ebi_sw_init_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: pcie0_sw_init [05:05] */
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_pcie0_sw_init_MASK 0x00000020
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_pcie0_sw_init_SHIFT 5
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_pcie0_sw_init_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: webcpu_start_sw_init [04:04] */
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_webcpu_start_sw_init_MASK 0x00000010
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_webcpu_start_sw_init_SHIFT 4
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_webcpu_start_sw_init_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: webcpu_sw_init [03:03] */
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_webcpu_sw_init_MASK 0x00000008
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_webcpu_sw_init_SHIFT 3
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_webcpu_sw_init_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: ext_sys_sw_init [02:02] */
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_ext_sys_sw_init_MASK 0x00000004
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_ext_sys_sw_init_SHIFT 2
-
-/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: cpu_sw_init [01:01] */
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_cpu_sw_init_MASK 0x00000002
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_cpu_sw_init_SHIFT 1
-
-/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: sys_ctrl_sw_init [00:00] */
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_sys_ctrl_sw_init_MASK 0x00000001
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_sys_ctrl_sw_init_SHIFT 0
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_sys_ctrl_sw_init_DEFAULT 0x00000000
-
-/***************************************************************************
- *SEC_SW_INIT_0_MONITOR - Security software init 0 monitor
- ***************************************************************************/
-/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: reserved_for_padding0 [31:31] */
-#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_reserved_for_padding0_MASK 0x80000000
-#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_reserved_for_padding0_SHIFT 31
-
-/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: not_used_sw_init_30 [30:30] */
-#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_not_used_sw_init_30_MASK 0x40000000
-#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_not_used_sw_init_30_SHIFT 30
-
-/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: sata_sw_init [29:29] */
-#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_sata_sw_init_MASK 0x20000000
-#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_sata_sw_init_SHIFT 29
-
-/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: moca_sw_init [28:28] */
-#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_moca_sw_init_MASK 0x10000000
-#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_moca_sw_init_SHIFT 28
-
-/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: genet1_sw_init [27:27] */
-#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_genet1_sw_init_MASK 0x08000000
-#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_genet1_sw_init_SHIFT 27
-
-/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: genet0_sw_init [26:26] */
-#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_genet0_sw_init_MASK 0x04000000
-#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_genet0_sw_init_SHIFT 26
-
-/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: usb1_sw_init [25:25] */
-#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_usb1_sw_init_MASK 0x02000000
-#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_usb1_sw_init_SHIFT 25
-
-/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: usb0_sw_init [24:24] */
-#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_usb0_sw_init_MASK 0x01000000
-#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_usb0_sw_init_SHIFT 24
-
-/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: not_used_sw_init_23 [23:23] */
-#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_not_used_sw_init_23_MASK 0x00800000
-#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_not_used_sw_init_23_SHIFT 23
-
-/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: ddr1_sw_init [22:22] */
-#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_ddr1_sw_init_MASK 0x00400000
-#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_ddr1_sw_init_SHIFT 22
-
-/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: ddr0_sw_init [21:21] */
-#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_ddr0_sw_init_MASK 0x00200000
-#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_ddr0_sw_init_SHIFT 21
-
-/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: memc1_sw_init [20:20] */
-#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_memc1_sw_init_MASK 0x00100000
-#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_memc1_sw_init_SHIFT 20
-
-/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: memc0_sw_init [19:19] */
-#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_memc0_sw_init_MASK 0x00080000
-#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_memc0_sw_init_SHIFT 19
-
-/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: xpt_sw_init [18:18] */
-#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_xpt_sw_init_MASK 0x00040000
-#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_xpt_sw_init_SHIFT 18
-
-/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: not_used_sw_init_17 [17:17] */
-#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_not_used_sw_init_17_MASK 0x00020000
-#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_not_used_sw_init_17_SHIFT 17
-
-/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: raaga0_sw_init [16:16] */
-#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_raaga0_sw_init_MASK 0x00010000
-#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_raaga0_sw_init_SHIFT 16
-
-/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: aio_sw_init [15:15] */
-#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_aio_sw_init_MASK 0x00008000
-#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_aio_sw_init_SHIFT 15
-
-/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: gfx_sw_init [14:14] */
-#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_gfx_sw_init_MASK 0x00004000
-#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_gfx_sw_init_SHIFT 14
-
-/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: not_used_sw_init_13 [13:13] */
-#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_not_used_sw_init_13_MASK 0x00002000
-#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_not_used_sw_init_13_SHIFT 13
-
-/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: hvd0_sw_init [12:12] */
-#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_hvd0_sw_init_MASK 0x00001000
-#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_hvd0_sw_init_SHIFT 12
-
-/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: reserved_for_padding1 [11:11] */
-#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_reserved_for_padding1_MASK 0x00000800
-#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_reserved_for_padding1_SHIFT 11
-
-/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: dvp_ht0_sw_init [10:10] */
-#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_dvp_ht0_sw_init_MASK 0x00000400
-#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_dvp_ht0_sw_init_SHIFT 10
-
-/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: vec_sw_init [09:09] */
-#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_vec_sw_init_MASK 0x00000200
-#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_vec_sw_init_SHIFT 9
-
-/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: bvn_sw_init [08:08] */
-#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_bvn_sw_init_MASK 0x00000100
-#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_bvn_sw_init_SHIFT 8
-
-/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: pcie1_sw_init [07:07] */
-#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_pcie1_sw_init_MASK 0x00000080
-#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_pcie1_sw_init_SHIFT 7
-
-/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: ebi_sw_init [06:06] */
-#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_ebi_sw_init_MASK 0x00000040
-#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_ebi_sw_init_SHIFT 6
-
-/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: pcie0_sw_init [05:05] */
-#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_pcie0_sw_init_MASK 0x00000020
-#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_pcie0_sw_init_SHIFT 5
-
-/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: webcpu_start_sw_init [04:04] */
-#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_webcpu_start_sw_init_MASK 0x00000010
-#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_webcpu_start_sw_init_SHIFT 4
-
-/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: webcpu_sw_init [03:03] */
-#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_webcpu_sw_init_MASK 0x00000008
-#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_webcpu_sw_init_SHIFT 3
-
-/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: ext_sys_sw_init [02:02] */
-#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_ext_sys_sw_init_MASK 0x00000004
-#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_ext_sys_sw_init_SHIFT 2
-
-/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: cpu_sw_init [01:01] */
-#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_cpu_sw_init_MASK 0x00000002
-#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_cpu_sw_init_SHIFT 1
-
-/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: sys_ctrl_sw_init [00:00] */
-#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_sys_ctrl_sw_init_MASK 0x00000001
-#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_sys_ctrl_sw_init_SHIFT 0
-
-/***************************************************************************
- *TEST_CONFIG_SW_INIT_0_MONITOR - Test configuration software init 0 monitor
- ***************************************************************************/
-/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: reserved_for_padding0 [31:31] */
-#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_reserved_for_padding0_MASK 0x80000000
-#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_reserved_for_padding0_SHIFT 31
-
-/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: not_used_sw_init_30 [30:30] */
-#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_not_used_sw_init_30_MASK 0x40000000
-#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_not_used_sw_init_30_SHIFT 30
-
-/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: sata_sw_init [29:29] */
-#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_sata_sw_init_MASK 0x20000000
-#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_sata_sw_init_SHIFT 29
-
-/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: moca_sw_init [28:28] */
-#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_moca_sw_init_MASK 0x10000000
-#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_moca_sw_init_SHIFT 28
-
-/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: genet1_sw_init [27:27] */
-#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_genet1_sw_init_MASK 0x08000000
-#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_genet1_sw_init_SHIFT 27
-
-/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: genet0_sw_init [26:26] */
-#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_genet0_sw_init_MASK 0x04000000
-#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_genet0_sw_init_SHIFT 26
-
-/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: usb1_sw_init [25:25] */
-#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_usb1_sw_init_MASK 0x02000000
-#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_usb1_sw_init_SHIFT 25
-
-/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: usb0_sw_init [24:24] */
-#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_usb0_sw_init_MASK 0x01000000
-#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_usb0_sw_init_SHIFT 24
-
-/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: not_used_sw_init_23 [23:23] */
-#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_not_used_sw_init_23_MASK 0x00800000
-#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_not_used_sw_init_23_SHIFT 23
-
-/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: ddr1_sw_init [22:22] */
-#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_ddr1_sw_init_MASK 0x00400000
-#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_ddr1_sw_init_SHIFT 22
-
-/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: ddr0_sw_init [21:21] */
-#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_ddr0_sw_init_MASK 0x00200000
-#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_ddr0_sw_init_SHIFT 21
-
-/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: memc1_sw_init [20:20] */
-#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_memc1_sw_init_MASK 0x00100000
-#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_memc1_sw_init_SHIFT 20
-
-/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: memc0_sw_init [19:19] */
-#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_memc0_sw_init_MASK 0x00080000
-#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_memc0_sw_init_SHIFT 19
-
-/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: xpt_sw_init [18:18] */
-#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_xpt_sw_init_MASK 0x00040000
-#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_xpt_sw_init_SHIFT 18
-
-/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: not_used_sw_init_17 [17:17] */
-#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_not_used_sw_init_17_MASK 0x00020000
-#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_not_used_sw_init_17_SHIFT 17
-
-/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: raaga0_sw_init [16:16] */
-#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_raaga0_sw_init_MASK 0x00010000
-#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_raaga0_sw_init_SHIFT 16
-
-/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: aio_sw_init [15:15] */
-#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_aio_sw_init_MASK 0x00008000
-#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_aio_sw_init_SHIFT 15
-
-/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: gfx_sw_init [14:14] */
-#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_gfx_sw_init_MASK 0x00004000
-#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_gfx_sw_init_SHIFT 14
-
-/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: not_used_sw_init_13 [13:13] */
-#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_not_used_sw_init_13_MASK 0x00002000
-#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_not_used_sw_init_13_SHIFT 13
-
-/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: hvd0_sw_init [12:12] */
-#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_hvd0_sw_init_MASK 0x00001000
-#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_hvd0_sw_init_SHIFT 12
-
-/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: reserved_for_padding1 [11:11] */
-#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_reserved_for_padding1_MASK 0x00000800
-#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_reserved_for_padding1_SHIFT 11
-
-/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: dvp_ht0_sw_init [10:10] */
-#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_dvp_ht0_sw_init_MASK 0x00000400
-#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_dvp_ht0_sw_init_SHIFT 10
-
-/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: vec_sw_init [09:09] */
-#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_vec_sw_init_MASK 0x00000200
-#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_vec_sw_init_SHIFT 9
-
-/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: bvn_sw_init [08:08] */
-#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_bvn_sw_init_MASK 0x00000100
-#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_bvn_sw_init_SHIFT 8
-
-/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: pcie1_sw_init [07:07] */
-#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_pcie1_sw_init_MASK 0x00000080
-#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_pcie1_sw_init_SHIFT 7
-
-/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: ebi_sw_init [06:06] */
-#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_ebi_sw_init_MASK 0x00000040
-#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_ebi_sw_init_SHIFT 6
-
-/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: pcie0_sw_init [05:05] */
-#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_pcie0_sw_init_MASK 0x00000020
-#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_pcie0_sw_init_SHIFT 5
-
-/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: webcpu_start_sw_init [04:04] */
-#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_webcpu_start_sw_init_MASK 0x00000010
-#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_webcpu_start_sw_init_SHIFT 4
-
-/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: webcpu_sw_init [03:03] */
-#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_webcpu_sw_init_MASK 0x00000008
-#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_webcpu_sw_init_SHIFT 3
-
-/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: ext_sys_sw_init [02:02] */
-#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_ext_sys_sw_init_MASK 0x00000004
-#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_ext_sys_sw_init_SHIFT 2
-
-/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: cpu_sw_init [01:01] */
-#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_cpu_sw_init_MASK 0x00000002
-#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_cpu_sw_init_SHIFT 1
-
-/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: sys_ctrl_sw_init [00:00] */
-#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_sys_ctrl_sw_init_MASK 0x00000001
-#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_sys_ctrl_sw_init_SHIFT 0
-
-/***************************************************************************
- *FINAL_SW_INIT_0_MONITOR - Final software init 0 monitor
- ***************************************************************************/
-/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: reserved_for_padding0 [31:31] */
-#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_reserved_for_padding0_MASK 0x80000000
-#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_reserved_for_padding0_SHIFT 31
-
-/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: not_used_sw_init_30 [30:30] */
-#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_not_used_sw_init_30_MASK 0x40000000
-#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_not_used_sw_init_30_SHIFT 30
-
-/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: sata_sw_init [29:29] */
-#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_sata_sw_init_MASK 0x20000000
-#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_sata_sw_init_SHIFT 29
-
-/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: moca_sw_init [28:28] */
-#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_moca_sw_init_MASK 0x10000000
-#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_moca_sw_init_SHIFT 28
-
-/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: genet1_sw_init [27:27] */
-#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_genet1_sw_init_MASK 0x08000000
-#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_genet1_sw_init_SHIFT 27
-
-/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: genet0_sw_init [26:26] */
-#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_genet0_sw_init_MASK 0x04000000
-#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_genet0_sw_init_SHIFT 26
-
-/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: usb1_sw_init [25:25] */
-#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_usb1_sw_init_MASK 0x02000000
-#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_usb1_sw_init_SHIFT 25
-
-/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: usb0_sw_init [24:24] */
-#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_usb0_sw_init_MASK 0x01000000
-#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_usb0_sw_init_SHIFT 24
-
-/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: not_used_sw_init_23 [23:23] */
-#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_not_used_sw_init_23_MASK 0x00800000
-#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_not_used_sw_init_23_SHIFT 23
-
-/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: ddr1_sw_init [22:22] */
-#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_ddr1_sw_init_MASK 0x00400000
-#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_ddr1_sw_init_SHIFT 22
-
-/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: ddr0_sw_init [21:21] */
-#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_ddr0_sw_init_MASK 0x00200000
-#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_ddr0_sw_init_SHIFT 21
-
-/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: memc1_sw_init [20:20] */
-#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_memc1_sw_init_MASK 0x00100000
-#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_memc1_sw_init_SHIFT 20
-
-/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: memc0_sw_init [19:19] */
-#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_memc0_sw_init_MASK 0x00080000
-#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_memc0_sw_init_SHIFT 19
-
-/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: xpt_sw_init [18:18] */
-#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_xpt_sw_init_MASK 0x00040000
-#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_xpt_sw_init_SHIFT 18
-
-/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: not_used_sw_init_17 [17:17] */
-#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_not_used_sw_init_17_MASK 0x00020000
-#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_not_used_sw_init_17_SHIFT 17
-
-/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: raaga0_sw_init [16:16] */
-#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_raaga0_sw_init_MASK 0x00010000
-#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_raaga0_sw_init_SHIFT 16
-
-/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: aio_sw_init [15:15] */
-#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_aio_sw_init_MASK 0x00008000
-#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_aio_sw_init_SHIFT 15
-
-/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: gfx_sw_init [14:14] */
-#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_gfx_sw_init_MASK 0x00004000
-#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_gfx_sw_init_SHIFT 14
-
-/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: not_used_sw_init_13 [13:13] */
-#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_not_used_sw_init_13_MASK 0x00002000
-#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_not_used_sw_init_13_SHIFT 13
-
-/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: hvd0_sw_init [12:12] */
-#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_hvd0_sw_init_MASK 0x00001000
-#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_hvd0_sw_init_SHIFT 12
-
-/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: reserved_for_padding1 [11:11] */
-#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_reserved_for_padding1_MASK 0x00000800
-#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_reserved_for_padding1_SHIFT 11
-
-/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: dvp_ht0_sw_init [10:10] */
-#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_dvp_ht0_sw_init_MASK 0x00000400
-#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_dvp_ht0_sw_init_SHIFT 10
-
-/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: vec_sw_init [09:09] */
-#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_vec_sw_init_MASK 0x00000200
-#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_vec_sw_init_SHIFT 9
-
-/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: bvn_sw_init [08:08] */
-#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_bvn_sw_init_MASK 0x00000100
-#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_bvn_sw_init_SHIFT 8
-
-/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: pcie1_sw_init [07:07] */
-#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_pcie1_sw_init_MASK 0x00000080
-#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_pcie1_sw_init_SHIFT 7
-
-/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: ebi_sw_init [06:06] */
-#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_ebi_sw_init_MASK 0x00000040
-#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_ebi_sw_init_SHIFT 6
-
-/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: pcie0_sw_init [05:05] */
-#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_pcie0_sw_init_MASK 0x00000020
-#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_pcie0_sw_init_SHIFT 5
-
-/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: webcpu_start_sw_init [04:04] */
-#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_webcpu_start_sw_init_MASK 0x00000010
-#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_webcpu_start_sw_init_SHIFT 4
-
-/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: webcpu_sw_init [03:03] */
-#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_webcpu_sw_init_MASK 0x00000008
-#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_webcpu_sw_init_SHIFT 3
-
-/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: ext_sys_sw_init [02:02] */
-#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_ext_sys_sw_init_MASK 0x00000004
-#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_ext_sys_sw_init_SHIFT 2
-
-/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: cpu_sw_init [01:01] */
-#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_cpu_sw_init_MASK 0x00000002
-#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_cpu_sw_init_SHIFT 1
-
-/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: sys_ctrl_sw_init [00:00] */
-#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_sys_ctrl_sw_init_MASK 0x00000001
-#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_sys_ctrl_sw_init_SHIFT 0
-
-/***************************************************************************
- *SW_INIT_1_SET - Software init 1 set
- ***************************************************************************/
-/* SUN_TOP_CTRL :: SW_INIT_1_SET :: spare0_sw_init [31:31] */
-#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_spare0_sw_init_MASK 0x80000000
-#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_spare0_sw_init_SHIFT 31
-#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_spare0_sw_init_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: SW_INIT_1_SET :: demod_xpt_sw_init [30:30] */
-#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_demod_xpt_sw_init_MASK 0x40000000
-#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_demod_xpt_sw_init_SHIFT 30
-#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_demod_xpt_sw_init_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: SW_INIT_1_SET :: sdio1_sw_init [29:29] */
-#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_sdio1_sw_init_MASK 0x20000000
-#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_sdio1_sw_init_SHIFT 29
-#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_sdio1_sw_init_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: SW_INIT_1_SET :: sdio0_sw_init [28:28] */
-#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_sdio0_sw_init_MASK 0x10000000
-#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_sdio0_sw_init_SHIFT 28
-#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_sdio0_sw_init_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: SW_INIT_1_SET :: rf4ce_top_sw_init [27:27] */
-#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_rf4ce_top_sw_init_MASK 0x08000000
-#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_rf4ce_top_sw_init_SHIFT 27
-#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_rf4ce_top_sw_init_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: SW_INIT_1_SET :: avs_top_sw_init [26:26] */
-#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_avs_top_sw_init_MASK 0x04000000
-#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_avs_top_sw_init_SHIFT 26
-#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_avs_top_sw_init_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: SW_INIT_1_SET :: hdmi_aon_sw_init [25:25] */
-#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_hdmi_aon_sw_init_MASK 0x02000000
-#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_hdmi_aon_sw_init_SHIFT 25
-#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_hdmi_aon_sw_init_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: SW_INIT_1_SET :: stb_chan_top_sw_init [24:24] */
-#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_stb_chan_top_sw_init_MASK 0x01000000
-#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_stb_chan_top_sw_init_SHIFT 24
-#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_stb_chan_top_sw_init_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: SW_INIT_1_SET :: aif_wb_stat_top1_sw_init [23:23] */
-#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_aif_wb_stat_top1_sw_init_MASK 0x00800000
-#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_aif_wb_stat_top1_sw_init_SHIFT 23
-#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_aif_wb_stat_top1_sw_init_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: SW_INIT_1_SET :: aif_wb_stat_top0_sw_init [22:22] */
-#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_aif_wb_stat_top0_sw_init_MASK 0x00400000
-#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_aif_wb_stat_top0_sw_init_SHIFT 22
-#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_aif_wb_stat_top0_sw_init_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: SW_INIT_1_SET :: aif_mdac_cal_top_sw_init [21:21] */
-#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_aif_mdac_cal_top_sw_init_MASK 0x00200000
-#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_aif_mdac_cal_top_sw_init_SHIFT 21
-#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_aif_mdac_cal_top_sw_init_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: SW_INIT_1_SET :: sds_afec3_sw_init [20:20] */
-#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_sds_afec3_sw_init_MASK 0x00100000
-#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_sds_afec3_sw_init_SHIFT 20
-#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_sds_afec3_sw_init_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: SW_INIT_1_SET :: sds_afec2_sw_init [19:19] */
-#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_sds_afec2_sw_init_MASK 0x00080000
-#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_sds_afec2_sw_init_SHIFT 19
-#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_sds_afec2_sw_init_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: SW_INIT_1_SET :: sds_afec1_sw_init [18:18] */
-#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_sds_afec1_sw_init_MASK 0x00040000
-#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_sds_afec1_sw_init_SHIFT 18
-#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_sds_afec1_sw_init_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: SW_INIT_1_SET :: sds_afec0_sw_init [17:17] */
-#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_sds_afec0_sw_init_MASK 0x00020000
-#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_sds_afec0_sw_init_SHIFT 17
-#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_sds_afec0_sw_init_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: SW_INIT_1_SET :: sds1_top3_sw_init [16:16] */
-#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_sds1_top3_sw_init_MASK 0x00010000
-#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_sds1_top3_sw_init_SHIFT 16
-#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_sds1_top3_sw_init_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: SW_INIT_1_SET :: sds0_top3_sw_init [15:15] */
-#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_sds0_top3_sw_init_MASK 0x00008000
-#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_sds0_top3_sw_init_SHIFT 15
-#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_sds0_top3_sw_init_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: SW_INIT_1_SET :: sds1_top2_sw_init [14:14] */
-#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_sds1_top2_sw_init_MASK 0x00004000
-#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_sds1_top2_sw_init_SHIFT 14
-#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_sds1_top2_sw_init_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: SW_INIT_1_SET :: sds0_top2_sw_init [13:13] */
-#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_sds0_top2_sw_init_MASK 0x00002000
-#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_sds0_top2_sw_init_SHIFT 13
-#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_sds0_top2_sw_init_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: SW_INIT_1_SET :: sds1_top1_sw_init [12:12] */
-#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_sds1_top1_sw_init_MASK 0x00001000
-#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_sds1_top1_sw_init_SHIFT 12
-#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_sds1_top1_sw_init_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: SW_INIT_1_SET :: sds0_top1_sw_init [11:11] */
-#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_sds0_top1_sw_init_MASK 0x00000800
-#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_sds0_top1_sw_init_SHIFT 11
-#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_sds0_top1_sw_init_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: SW_INIT_1_SET :: sds1_top0_sw_init [10:10] */
-#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_sds1_top0_sw_init_MASK 0x00000400
-#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_sds1_top0_sw_init_SHIFT 10
-#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_sds1_top0_sw_init_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: SW_INIT_1_SET :: sds0_top0_sw_init [09:09] */
-#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_sds0_top0_sw_init_MASK 0x00000200
-#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_sds0_top0_sw_init_SHIFT 9
-#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_sds0_top0_sw_init_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: SW_INIT_1_SET :: fsk_top_sw_init [08:08] */
-#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_fsk_top_sw_init_MASK 0x00000100
-#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_fsk_top_sw_init_SHIFT 8
-#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_fsk_top_sw_init_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: SW_INIT_1_SET :: leap_sw_init [07:07] */
-#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_leap_sw_init_MASK 0x00000080
-#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_leap_sw_init_SHIFT 7
-#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_leap_sw_init_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: SW_INIT_1_SET :: reserved_for_padding0 [06:06] */
-#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_reserved_for_padding0_MASK 0x00000040
-#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_reserved_for_padding0_SHIFT 6
-
-/* SUN_TOP_CTRL :: SW_INIT_1_SET :: gphy_sw_init [05:05] */
-#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_gphy_sw_init_MASK 0x00000020
-#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_gphy_sw_init_SHIFT 5
-#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_gphy_sw_init_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: SW_INIT_1_SET :: genet2_sw_init [04:04] */
-#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_genet2_sw_init_MASK 0x00000010
-#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_genet2_sw_init_SHIFT 4
-#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_genet2_sw_init_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: SW_INIT_1_SET :: m2mc1_sw_init [03:03] */
-#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_m2mc1_sw_init_MASK 0x00000008
-#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_m2mc1_sw_init_SHIFT 3
-#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_m2mc1_sw_init_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: SW_INIT_1_SET :: v3d_top_sw_init [02:02] */
-#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_v3d_top_sw_init_MASK 0x00000004
-#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_v3d_top_sw_init_SHIFT 2
-#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_v3d_top_sw_init_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: SW_INIT_1_SET :: vice20_sw_init [01:01] */
-#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_vice20_sw_init_MASK 0x00000002
-#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_vice20_sw_init_SHIFT 1
-#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_vice20_sw_init_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: SW_INIT_1_SET :: sid_sw_init [00:00] */
-#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_sid_sw_init_MASK 0x00000001
-#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_sid_sw_init_SHIFT 0
-#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_sid_sw_init_DEFAULT 0x00000000
-
-/***************************************************************************
- *SW_INIT_1_CLEAR - Software init 1 clear
- ***************************************************************************/
-/* SUN_TOP_CTRL :: SW_INIT_1_CLEAR :: spare0_sw_init [31:31] */
-#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_spare0_sw_init_MASK 0x80000000
-#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_spare0_sw_init_SHIFT 31
-#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_spare0_sw_init_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: SW_INIT_1_CLEAR :: demod_xpt_sw_init [30:30] */
-#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_demod_xpt_sw_init_MASK 0x40000000
-#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_demod_xpt_sw_init_SHIFT 30
-#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_demod_xpt_sw_init_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: SW_INIT_1_CLEAR :: sdio1_sw_init [29:29] */
-#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_sdio1_sw_init_MASK 0x20000000
-#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_sdio1_sw_init_SHIFT 29
-#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_sdio1_sw_init_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: SW_INIT_1_CLEAR :: sdio0_sw_init [28:28] */
-#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_sdio0_sw_init_MASK 0x10000000
-#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_sdio0_sw_init_SHIFT 28
-#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_sdio0_sw_init_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: SW_INIT_1_CLEAR :: rf4ce_top_sw_init [27:27] */
-#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_rf4ce_top_sw_init_MASK 0x08000000
-#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_rf4ce_top_sw_init_SHIFT 27
-#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_rf4ce_top_sw_init_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: SW_INIT_1_CLEAR :: avs_top_sw_init [26:26] */
-#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_avs_top_sw_init_MASK 0x04000000
-#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_avs_top_sw_init_SHIFT 26
-#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_avs_top_sw_init_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: SW_INIT_1_CLEAR :: hdmi_aon_sw_init [25:25] */
-#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_hdmi_aon_sw_init_MASK 0x02000000
-#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_hdmi_aon_sw_init_SHIFT 25
-#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_hdmi_aon_sw_init_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: SW_INIT_1_CLEAR :: stb_chan_top_sw_init [24:24] */
-#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_stb_chan_top_sw_init_MASK 0x01000000
-#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_stb_chan_top_sw_init_SHIFT 24
-#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_stb_chan_top_sw_init_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: SW_INIT_1_CLEAR :: aif_wb_stat_top1_sw_init [23:23] */
-#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_aif_wb_stat_top1_sw_init_MASK 0x00800000
-#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_aif_wb_stat_top1_sw_init_SHIFT 23
-#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_aif_wb_stat_top1_sw_init_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: SW_INIT_1_CLEAR :: aif_wb_stat_top0_sw_init [22:22] */
-#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_aif_wb_stat_top0_sw_init_MASK 0x00400000
-#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_aif_wb_stat_top0_sw_init_SHIFT 22
-#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_aif_wb_stat_top0_sw_init_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: SW_INIT_1_CLEAR :: aif_mdac_cal_top_sw_init [21:21] */
-#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_aif_mdac_cal_top_sw_init_MASK 0x00200000
-#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_aif_mdac_cal_top_sw_init_SHIFT 21
-#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_aif_mdac_cal_top_sw_init_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: SW_INIT_1_CLEAR :: sds_afec3_sw_init [20:20] */
-#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_sds_afec3_sw_init_MASK 0x00100000
-#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_sds_afec3_sw_init_SHIFT 20
-#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_sds_afec3_sw_init_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: SW_INIT_1_CLEAR :: sds_afec2_sw_init [19:19] */
-#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_sds_afec2_sw_init_MASK 0x00080000
-#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_sds_afec2_sw_init_SHIFT 19
-#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_sds_afec2_sw_init_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: SW_INIT_1_CLEAR :: sds_afec1_sw_init [18:18] */
-#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_sds_afec1_sw_init_MASK 0x00040000
-#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_sds_afec1_sw_init_SHIFT 18
-#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_sds_afec1_sw_init_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: SW_INIT_1_CLEAR :: sds_afec0_sw_init [17:17] */
-#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_sds_afec0_sw_init_MASK 0x00020000
-#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_sds_afec0_sw_init_SHIFT 17
-#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_sds_afec0_sw_init_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: SW_INIT_1_CLEAR :: sds1_top3_sw_init [16:16] */
-#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_sds1_top3_sw_init_MASK 0x00010000
-#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_sds1_top3_sw_init_SHIFT 16
-#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_sds1_top3_sw_init_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: SW_INIT_1_CLEAR :: sds0_top3_sw_init [15:15] */
-#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_sds0_top3_sw_init_MASK 0x00008000
-#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_sds0_top3_sw_init_SHIFT 15
-#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_sds0_top3_sw_init_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: SW_INIT_1_CLEAR :: sds1_top2_sw_init [14:14] */
-#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_sds1_top2_sw_init_MASK 0x00004000
-#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_sds1_top2_sw_init_SHIFT 14
-#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_sds1_top2_sw_init_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: SW_INIT_1_CLEAR :: sds0_top2_sw_init [13:13] */
-#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_sds0_top2_sw_init_MASK 0x00002000
-#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_sds0_top2_sw_init_SHIFT 13
-#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_sds0_top2_sw_init_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: SW_INIT_1_CLEAR :: sds1_top1_sw_init [12:12] */
-#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_sds1_top1_sw_init_MASK 0x00001000
-#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_sds1_top1_sw_init_SHIFT 12
-#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_sds1_top1_sw_init_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: SW_INIT_1_CLEAR :: sds0_top1_sw_init [11:11] */
-#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_sds0_top1_sw_init_MASK 0x00000800
-#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_sds0_top1_sw_init_SHIFT 11
-#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_sds0_top1_sw_init_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: SW_INIT_1_CLEAR :: sds1_top0_sw_init [10:10] */
-#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_sds1_top0_sw_init_MASK 0x00000400
-#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_sds1_top0_sw_init_SHIFT 10
-#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_sds1_top0_sw_init_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: SW_INIT_1_CLEAR :: sds0_top0_sw_init [09:09] */
-#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_sds0_top0_sw_init_MASK 0x00000200
-#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_sds0_top0_sw_init_SHIFT 9
-#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_sds0_top0_sw_init_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: SW_INIT_1_CLEAR :: fsk_top_sw_init [08:08] */
-#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_fsk_top_sw_init_MASK 0x00000100
-#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_fsk_top_sw_init_SHIFT 8
-#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_fsk_top_sw_init_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: SW_INIT_1_CLEAR :: leap_sw_init [07:07] */
-#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_leap_sw_init_MASK 0x00000080
-#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_leap_sw_init_SHIFT 7
-#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_leap_sw_init_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: SW_INIT_1_CLEAR :: reserved_for_padding0 [06:06] */
-#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_reserved_for_padding0_MASK 0x00000040
-#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_reserved_for_padding0_SHIFT 6
-
-/* SUN_TOP_CTRL :: SW_INIT_1_CLEAR :: gphy_sw_init [05:05] */
-#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_gphy_sw_init_MASK 0x00000020
-#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_gphy_sw_init_SHIFT 5
-#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_gphy_sw_init_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: SW_INIT_1_CLEAR :: genet2_sw_init [04:04] */
-#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_genet2_sw_init_MASK 0x00000010
-#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_genet2_sw_init_SHIFT 4
-#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_genet2_sw_init_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: SW_INIT_1_CLEAR :: m2mc1_sw_init [03:03] */
-#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_m2mc1_sw_init_MASK 0x00000008
-#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_m2mc1_sw_init_SHIFT 3
-#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_m2mc1_sw_init_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: SW_INIT_1_CLEAR :: v3d_top_sw_init [02:02] */
-#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_v3d_top_sw_init_MASK 0x00000004
-#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_v3d_top_sw_init_SHIFT 2
-#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_v3d_top_sw_init_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: SW_INIT_1_CLEAR :: vice20_sw_init [01:01] */
-#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_vice20_sw_init_MASK 0x00000002
-#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_vice20_sw_init_SHIFT 1
-#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_vice20_sw_init_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: SW_INIT_1_CLEAR :: sid_sw_init [00:00] */
-#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_sid_sw_init_MASK 0x00000001
-#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_sid_sw_init_SHIFT 0
-#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_sid_sw_init_DEFAULT 0x00000000
-
-/***************************************************************************
- *SW_INIT_1_STATUS - Software init 1 status
- ***************************************************************************/
-/* SUN_TOP_CTRL :: SW_INIT_1_STATUS :: spare0_sw_init [31:31] */
-#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_spare0_sw_init_MASK 0x80000000
-#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_spare0_sw_init_SHIFT 31
-#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_spare0_sw_init_DEFAULT 0x00000001
-
-/* SUN_TOP_CTRL :: SW_INIT_1_STATUS :: demod_xpt_sw_init [30:30] */
-#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_demod_xpt_sw_init_MASK 0x40000000
-#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_demod_xpt_sw_init_SHIFT 30
-#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_demod_xpt_sw_init_DEFAULT 0x00000001
-
-/* SUN_TOP_CTRL :: SW_INIT_1_STATUS :: sdio1_sw_init [29:29] */
-#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_sdio1_sw_init_MASK 0x20000000
-#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_sdio1_sw_init_SHIFT 29
-#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_sdio1_sw_init_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: SW_INIT_1_STATUS :: sdio0_sw_init [28:28] */
-#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_sdio0_sw_init_MASK 0x10000000
-#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_sdio0_sw_init_SHIFT 28
-#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_sdio0_sw_init_DEFAULT 0x00000001
-
-/* SUN_TOP_CTRL :: SW_INIT_1_STATUS :: rf4ce_top_sw_init [27:27] */
-#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_rf4ce_top_sw_init_MASK 0x08000000
-#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_rf4ce_top_sw_init_SHIFT 27
-#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_rf4ce_top_sw_init_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: SW_INIT_1_STATUS :: avs_top_sw_init [26:26] */
-#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_avs_top_sw_init_MASK 0x04000000
-#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_avs_top_sw_init_SHIFT 26
-#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_avs_top_sw_init_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: SW_INIT_1_STATUS :: hdmi_aon_sw_init [25:25] */
-#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_hdmi_aon_sw_init_MASK 0x02000000
-#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_hdmi_aon_sw_init_SHIFT 25
-#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_hdmi_aon_sw_init_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: SW_INIT_1_STATUS :: stb_chan_top_sw_init [24:24] */
-#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_stb_chan_top_sw_init_MASK 0x01000000
-#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_stb_chan_top_sw_init_SHIFT 24
-#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_stb_chan_top_sw_init_DEFAULT 0x00000001
-
-/* SUN_TOP_CTRL :: SW_INIT_1_STATUS :: aif_wb_stat_top1_sw_init [23:23] */
-#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_aif_wb_stat_top1_sw_init_MASK 0x00800000
-#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_aif_wb_stat_top1_sw_init_SHIFT 23
-#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_aif_wb_stat_top1_sw_init_DEFAULT 0x00000001
-
-/* SUN_TOP_CTRL :: SW_INIT_1_STATUS :: aif_wb_stat_top0_sw_init [22:22] */
-#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_aif_wb_stat_top0_sw_init_MASK 0x00400000
-#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_aif_wb_stat_top0_sw_init_SHIFT 22
-#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_aif_wb_stat_top0_sw_init_DEFAULT 0x00000001
-
-/* SUN_TOP_CTRL :: SW_INIT_1_STATUS :: aif_mdac_cal_top_sw_init [21:21] */
-#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_aif_mdac_cal_top_sw_init_MASK 0x00200000
-#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_aif_mdac_cal_top_sw_init_SHIFT 21
-#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_aif_mdac_cal_top_sw_init_DEFAULT 0x00000001
-
-/* SUN_TOP_CTRL :: SW_INIT_1_STATUS :: sds_afec3_sw_init [20:20] */
-#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_sds_afec3_sw_init_MASK 0x00100000
-#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_sds_afec3_sw_init_SHIFT 20
-#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_sds_afec3_sw_init_DEFAULT 0x00000001
-
-/* SUN_TOP_CTRL :: SW_INIT_1_STATUS :: sds_afec2_sw_init [19:19] */
-#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_sds_afec2_sw_init_MASK 0x00080000
-#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_sds_afec2_sw_init_SHIFT 19
-#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_sds_afec2_sw_init_DEFAULT 0x00000001
-
-/* SUN_TOP_CTRL :: SW_INIT_1_STATUS :: sds_afec1_sw_init [18:18] */
-#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_sds_afec1_sw_init_MASK 0x00040000
-#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_sds_afec1_sw_init_SHIFT 18
-#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_sds_afec1_sw_init_DEFAULT 0x00000001
-
-/* SUN_TOP_CTRL :: SW_INIT_1_STATUS :: sds_afec0_sw_init [17:17] */
-#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_sds_afec0_sw_init_MASK 0x00020000
-#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_sds_afec0_sw_init_SHIFT 17
-#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_sds_afec0_sw_init_DEFAULT 0x00000001
-
-/* SUN_TOP_CTRL :: SW_INIT_1_STATUS :: sds1_top3_sw_init [16:16] */
-#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_sds1_top3_sw_init_MASK 0x00010000
-#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_sds1_top3_sw_init_SHIFT 16
-#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_sds1_top3_sw_init_DEFAULT 0x00000001
-
-/* SUN_TOP_CTRL :: SW_INIT_1_STATUS :: sds0_top3_sw_init [15:15] */
-#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_sds0_top3_sw_init_MASK 0x00008000
-#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_sds0_top3_sw_init_SHIFT 15
-#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_sds0_top3_sw_init_DEFAULT 0x00000001
-
-/* SUN_TOP_CTRL :: SW_INIT_1_STATUS :: sds1_top2_sw_init [14:14] */
-#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_sds1_top2_sw_init_MASK 0x00004000
-#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_sds1_top2_sw_init_SHIFT 14
-#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_sds1_top2_sw_init_DEFAULT 0x00000001
-
-/* SUN_TOP_CTRL :: SW_INIT_1_STATUS :: sds0_top2_sw_init [13:13] */
-#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_sds0_top2_sw_init_MASK 0x00002000
-#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_sds0_top2_sw_init_SHIFT 13
-#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_sds0_top2_sw_init_DEFAULT 0x00000001
-
-/* SUN_TOP_CTRL :: SW_INIT_1_STATUS :: sds1_top1_sw_init [12:12] */
-#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_sds1_top1_sw_init_MASK 0x00001000
-#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_sds1_top1_sw_init_SHIFT 12
-#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_sds1_top1_sw_init_DEFAULT 0x00000001
-
-/* SUN_TOP_CTRL :: SW_INIT_1_STATUS :: sds0_top1_sw_init [11:11] */
-#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_sds0_top1_sw_init_MASK 0x00000800
-#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_sds0_top1_sw_init_SHIFT 11
-#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_sds0_top1_sw_init_DEFAULT 0x00000001
-
-/* SUN_TOP_CTRL :: SW_INIT_1_STATUS :: sds1_top0_sw_init [10:10] */
-#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_sds1_top0_sw_init_MASK 0x00000400
-#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_sds1_top0_sw_init_SHIFT 10
-#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_sds1_top0_sw_init_DEFAULT 0x00000001
-
-/* SUN_TOP_CTRL :: SW_INIT_1_STATUS :: sds0_top0_sw_init [09:09] */
-#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_sds0_top0_sw_init_MASK 0x00000200
-#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_sds0_top0_sw_init_SHIFT 9
-#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_sds0_top0_sw_init_DEFAULT 0x00000001
-
-/* SUN_TOP_CTRL :: SW_INIT_1_STATUS :: fsk_top_sw_init [08:08] */
-#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_fsk_top_sw_init_MASK 0x00000100
-#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_fsk_top_sw_init_SHIFT 8
-#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_fsk_top_sw_init_DEFAULT 0x00000001
-
-/* SUN_TOP_CTRL :: SW_INIT_1_STATUS :: leap_sw_init [07:07] */
-#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_leap_sw_init_MASK 0x00000080
-#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_leap_sw_init_SHIFT 7
-#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_leap_sw_init_DEFAULT 0x00000001
-
-/* SUN_TOP_CTRL :: SW_INIT_1_STATUS :: reserved_for_padding0 [06:06] */
-#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_reserved_for_padding0_MASK 0x00000040
-#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_reserved_for_padding0_SHIFT 6
-
-/* SUN_TOP_CTRL :: SW_INIT_1_STATUS :: gphy_sw_init [05:05] */
-#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_gphy_sw_init_MASK 0x00000020
-#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_gphy_sw_init_SHIFT 5
-#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_gphy_sw_init_DEFAULT 0x00000001
-
-/* SUN_TOP_CTRL :: SW_INIT_1_STATUS :: genet2_sw_init [04:04] */
-#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_genet2_sw_init_MASK 0x00000010
-#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_genet2_sw_init_SHIFT 4
-#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_genet2_sw_init_DEFAULT 0x00000001
-
-/* SUN_TOP_CTRL :: SW_INIT_1_STATUS :: m2mc1_sw_init [03:03] */
-#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_m2mc1_sw_init_MASK 0x00000008
-#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_m2mc1_sw_init_SHIFT 3
-#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_m2mc1_sw_init_DEFAULT 0x00000001
-
-/* SUN_TOP_CTRL :: SW_INIT_1_STATUS :: v3d_top_sw_init [02:02] */
-#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_v3d_top_sw_init_MASK 0x00000004
-#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_v3d_top_sw_init_SHIFT 2
-#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_v3d_top_sw_init_DEFAULT 0x00000001
-
-/* SUN_TOP_CTRL :: SW_INIT_1_STATUS :: vice20_sw_init [01:01] */
-#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_vice20_sw_init_MASK 0x00000002
-#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_vice20_sw_init_SHIFT 1
-#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_vice20_sw_init_DEFAULT 0x00000001
-
-/* SUN_TOP_CTRL :: SW_INIT_1_STATUS :: sid_sw_init [00:00] */
-#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_sid_sw_init_MASK 0x00000001
-#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_sid_sw_init_SHIFT 0
-#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_sid_sw_init_DEFAULT 0x00000001
-
-/***************************************************************************
- *SEC_SW_INIT_1_MONITOR - Security software init 1 monitor
- ***************************************************************************/
-/* SUN_TOP_CTRL :: SEC_SW_INIT_1_MONITOR :: spare0_sw_init [31:31] */
-#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_spare0_sw_init_MASK 0x80000000
-#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_spare0_sw_init_SHIFT 31
-
-/* SUN_TOP_CTRL :: SEC_SW_INIT_1_MONITOR :: demod_xpt_sw_init [30:30] */
-#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_demod_xpt_sw_init_MASK 0x40000000
-#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_demod_xpt_sw_init_SHIFT 30
-
-/* SUN_TOP_CTRL :: SEC_SW_INIT_1_MONITOR :: sdio1_sw_init [29:29] */
-#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_sdio1_sw_init_MASK 0x20000000
-#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_sdio1_sw_init_SHIFT 29
-
-/* SUN_TOP_CTRL :: SEC_SW_INIT_1_MONITOR :: sdio0_sw_init [28:28] */
-#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_sdio0_sw_init_MASK 0x10000000
-#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_sdio0_sw_init_SHIFT 28
-
-/* SUN_TOP_CTRL :: SEC_SW_INIT_1_MONITOR :: rf4ce_top_sw_init [27:27] */
-#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_rf4ce_top_sw_init_MASK 0x08000000
-#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_rf4ce_top_sw_init_SHIFT 27
-
-/* SUN_TOP_CTRL :: SEC_SW_INIT_1_MONITOR :: avs_top_sw_init [26:26] */
-#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_avs_top_sw_init_MASK 0x04000000
-#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_avs_top_sw_init_SHIFT 26
-
-/* SUN_TOP_CTRL :: SEC_SW_INIT_1_MONITOR :: hdmi_aon_sw_init [25:25] */
-#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_hdmi_aon_sw_init_MASK 0x02000000
-#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_hdmi_aon_sw_init_SHIFT 25
-
-/* SUN_TOP_CTRL :: SEC_SW_INIT_1_MONITOR :: stb_chan_top_sw_init [24:24] */
-#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_stb_chan_top_sw_init_MASK 0x01000000
-#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_stb_chan_top_sw_init_SHIFT 24
-
-/* SUN_TOP_CTRL :: SEC_SW_INIT_1_MONITOR :: aif_wb_stat_top1_sw_init [23:23] */
-#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_aif_wb_stat_top1_sw_init_MASK 0x00800000
-#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_aif_wb_stat_top1_sw_init_SHIFT 23
-
-/* SUN_TOP_CTRL :: SEC_SW_INIT_1_MONITOR :: aif_wb_stat_top0_sw_init [22:22] */
-#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_aif_wb_stat_top0_sw_init_MASK 0x00400000
-#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_aif_wb_stat_top0_sw_init_SHIFT 22
-
-/* SUN_TOP_CTRL :: SEC_SW_INIT_1_MONITOR :: aif_mdac_cal_top_sw_init [21:21] */
-#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_aif_mdac_cal_top_sw_init_MASK 0x00200000
-#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_aif_mdac_cal_top_sw_init_SHIFT 21
-
-/* SUN_TOP_CTRL :: SEC_SW_INIT_1_MONITOR :: sds_afec3_sw_init [20:20] */
-#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_sds_afec3_sw_init_MASK 0x00100000
-#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_sds_afec3_sw_init_SHIFT 20
-
-/* SUN_TOP_CTRL :: SEC_SW_INIT_1_MONITOR :: sds_afec2_sw_init [19:19] */
-#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_sds_afec2_sw_init_MASK 0x00080000
-#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_sds_afec2_sw_init_SHIFT 19
-
-/* SUN_TOP_CTRL :: SEC_SW_INIT_1_MONITOR :: sds_afec1_sw_init [18:18] */
-#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_sds_afec1_sw_init_MASK 0x00040000
-#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_sds_afec1_sw_init_SHIFT 18
-
-/* SUN_TOP_CTRL :: SEC_SW_INIT_1_MONITOR :: sds_afec0_sw_init [17:17] */
-#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_sds_afec0_sw_init_MASK 0x00020000
-#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_sds_afec0_sw_init_SHIFT 17
-
-/* SUN_TOP_CTRL :: SEC_SW_INIT_1_MONITOR :: sds1_top3_sw_init [16:16] */
-#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_sds1_top3_sw_init_MASK 0x00010000
-#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_sds1_top3_sw_init_SHIFT 16
-
-/* SUN_TOP_CTRL :: SEC_SW_INIT_1_MONITOR :: sds0_top3_sw_init [15:15] */
-#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_sds0_top3_sw_init_MASK 0x00008000
-#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_sds0_top3_sw_init_SHIFT 15
-
-/* SUN_TOP_CTRL :: SEC_SW_INIT_1_MONITOR :: sds1_top2_sw_init [14:14] */
-#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_sds1_top2_sw_init_MASK 0x00004000
-#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_sds1_top2_sw_init_SHIFT 14
-
-/* SUN_TOP_CTRL :: SEC_SW_INIT_1_MONITOR :: sds0_top2_sw_init [13:13] */
-#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_sds0_top2_sw_init_MASK 0x00002000
-#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_sds0_top2_sw_init_SHIFT 13
-
-/* SUN_TOP_CTRL :: SEC_SW_INIT_1_MONITOR :: sds1_top1_sw_init [12:12] */
-#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_sds1_top1_sw_init_MASK 0x00001000
-#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_sds1_top1_sw_init_SHIFT 12
-
-/* SUN_TOP_CTRL :: SEC_SW_INIT_1_MONITOR :: sds0_top1_sw_init [11:11] */
-#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_sds0_top1_sw_init_MASK 0x00000800
-#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_sds0_top1_sw_init_SHIFT 11
-
-/* SUN_TOP_CTRL :: SEC_SW_INIT_1_MONITOR :: sds1_top0_sw_init [10:10] */
-#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_sds1_top0_sw_init_MASK 0x00000400
-#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_sds1_top0_sw_init_SHIFT 10
-
-/* SUN_TOP_CTRL :: SEC_SW_INIT_1_MONITOR :: sds0_top0_sw_init [09:09] */
-#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_sds0_top0_sw_init_MASK 0x00000200
-#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_sds0_top0_sw_init_SHIFT 9
-
-/* SUN_TOP_CTRL :: SEC_SW_INIT_1_MONITOR :: fsk_top_sw_init [08:08] */
-#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_fsk_top_sw_init_MASK 0x00000100
-#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_fsk_top_sw_init_SHIFT 8
-
-/* SUN_TOP_CTRL :: SEC_SW_INIT_1_MONITOR :: leap_sw_init [07:07] */
-#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_leap_sw_init_MASK 0x00000080
-#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_leap_sw_init_SHIFT 7
-
-/* SUN_TOP_CTRL :: SEC_SW_INIT_1_MONITOR :: reserved_for_padding0 [06:06] */
-#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_reserved_for_padding0_MASK 0x00000040
-#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_reserved_for_padding0_SHIFT 6
-
-/* SUN_TOP_CTRL :: SEC_SW_INIT_1_MONITOR :: gphy_sw_init [05:05] */
-#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_gphy_sw_init_MASK 0x00000020
-#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_gphy_sw_init_SHIFT 5
-
-/* SUN_TOP_CTRL :: SEC_SW_INIT_1_MONITOR :: genet2_sw_init [04:04] */
-#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_genet2_sw_init_MASK 0x00000010
-#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_genet2_sw_init_SHIFT 4
-
-/* SUN_TOP_CTRL :: SEC_SW_INIT_1_MONITOR :: m2mc1_sw_init [03:03] */
-#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_m2mc1_sw_init_MASK 0x00000008
-#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_m2mc1_sw_init_SHIFT 3
-
-/* SUN_TOP_CTRL :: SEC_SW_INIT_1_MONITOR :: v3d_top_sw_init [02:02] */
-#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_v3d_top_sw_init_MASK 0x00000004
-#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_v3d_top_sw_init_SHIFT 2
-
-/* SUN_TOP_CTRL :: SEC_SW_INIT_1_MONITOR :: vice20_sw_init [01:01] */
-#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_vice20_sw_init_MASK 0x00000002
-#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_vice20_sw_init_SHIFT 1
-
-/* SUN_TOP_CTRL :: SEC_SW_INIT_1_MONITOR :: sid_sw_init [00:00] */
-#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_sid_sw_init_MASK 0x00000001
-#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_sid_sw_init_SHIFT 0
-
-/***************************************************************************
- *TEST_CONFIG_SW_INIT_1_MONITOR - Test configuration software init 1 monitor
- ***************************************************************************/
-/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_1_MONITOR :: spare0_sw_init [31:31] */
-#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_spare0_sw_init_MASK 0x80000000
-#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_spare0_sw_init_SHIFT 31
-
-/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_1_MONITOR :: demod_xpt_sw_init [30:30] */
-#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_demod_xpt_sw_init_MASK 0x40000000
-#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_demod_xpt_sw_init_SHIFT 30
-
-/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_1_MONITOR :: sdio1_sw_init [29:29] */
-#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_sdio1_sw_init_MASK 0x20000000
-#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_sdio1_sw_init_SHIFT 29
-
-/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_1_MONITOR :: sdio0_sw_init [28:28] */
-#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_sdio0_sw_init_MASK 0x10000000
-#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_sdio0_sw_init_SHIFT 28
-
-/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_1_MONITOR :: rf4ce_top_sw_init [27:27] */
-#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_rf4ce_top_sw_init_MASK 0x08000000
-#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_rf4ce_top_sw_init_SHIFT 27
-
-/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_1_MONITOR :: avs_top_sw_init [26:26] */
-#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_avs_top_sw_init_MASK 0x04000000
-#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_avs_top_sw_init_SHIFT 26
-
-/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_1_MONITOR :: hdmi_aon_sw_init [25:25] */
-#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_hdmi_aon_sw_init_MASK 0x02000000
-#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_hdmi_aon_sw_init_SHIFT 25
-
-/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_1_MONITOR :: stb_chan_top_sw_init [24:24] */
-#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_stb_chan_top_sw_init_MASK 0x01000000
-#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_stb_chan_top_sw_init_SHIFT 24
-
-/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_1_MONITOR :: aif_wb_stat_top1_sw_init [23:23] */
-#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_aif_wb_stat_top1_sw_init_MASK 0x00800000
-#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_aif_wb_stat_top1_sw_init_SHIFT 23
-
-/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_1_MONITOR :: aif_wb_stat_top0_sw_init [22:22] */
-#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_aif_wb_stat_top0_sw_init_MASK 0x00400000
-#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_aif_wb_stat_top0_sw_init_SHIFT 22
-
-/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_1_MONITOR :: aif_mdac_cal_top_sw_init [21:21] */
-#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_aif_mdac_cal_top_sw_init_MASK 0x00200000
-#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_aif_mdac_cal_top_sw_init_SHIFT 21
-
-/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_1_MONITOR :: sds_afec3_sw_init [20:20] */
-#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_sds_afec3_sw_init_MASK 0x00100000
-#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_sds_afec3_sw_init_SHIFT 20
-
-/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_1_MONITOR :: sds_afec2_sw_init [19:19] */
-#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_sds_afec2_sw_init_MASK 0x00080000
-#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_sds_afec2_sw_init_SHIFT 19
-
-/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_1_MONITOR :: sds_afec1_sw_init [18:18] */
-#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_sds_afec1_sw_init_MASK 0x00040000
-#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_sds_afec1_sw_init_SHIFT 18
-
-/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_1_MONITOR :: sds_afec0_sw_init [17:17] */
-#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_sds_afec0_sw_init_MASK 0x00020000
-#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_sds_afec0_sw_init_SHIFT 17
-
-/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_1_MONITOR :: sds1_top3_sw_init [16:16] */
-#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_sds1_top3_sw_init_MASK 0x00010000
-#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_sds1_top3_sw_init_SHIFT 16
-
-/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_1_MONITOR :: sds0_top3_sw_init [15:15] */
-#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_sds0_top3_sw_init_MASK 0x00008000
-#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_sds0_top3_sw_init_SHIFT 15
-
-/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_1_MONITOR :: sds1_top2_sw_init [14:14] */
-#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_sds1_top2_sw_init_MASK 0x00004000
-#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_sds1_top2_sw_init_SHIFT 14
-
-/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_1_MONITOR :: sds0_top2_sw_init [13:13] */
-#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_sds0_top2_sw_init_MASK 0x00002000
-#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_sds0_top2_sw_init_SHIFT 13
-
-/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_1_MONITOR :: sds1_top1_sw_init [12:12] */
-#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_sds1_top1_sw_init_MASK 0x00001000
-#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_sds1_top1_sw_init_SHIFT 12
-
-/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_1_MONITOR :: sds0_top1_sw_init [11:11] */
-#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_sds0_top1_sw_init_MASK 0x00000800
-#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_sds0_top1_sw_init_SHIFT 11
-
-/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_1_MONITOR :: sds1_top0_sw_init [10:10] */
-#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_sds1_top0_sw_init_MASK 0x00000400
-#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_sds1_top0_sw_init_SHIFT 10
-
-/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_1_MONITOR :: sds0_top0_sw_init [09:09] */
-#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_sds0_top0_sw_init_MASK 0x00000200
-#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_sds0_top0_sw_init_SHIFT 9
-
-/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_1_MONITOR :: fsk_top_sw_init [08:08] */
-#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_fsk_top_sw_init_MASK 0x00000100
-#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_fsk_top_sw_init_SHIFT 8
-
-/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_1_MONITOR :: leap_sw_init [07:07] */
-#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_leap_sw_init_MASK 0x00000080
-#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_leap_sw_init_SHIFT 7
-
-/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_1_MONITOR :: reserved_for_padding0 [06:06] */
-#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_reserved_for_padding0_MASK 0x00000040
-#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_reserved_for_padding0_SHIFT 6
-
-/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_1_MONITOR :: gphy_sw_init [05:05] */
-#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_gphy_sw_init_MASK 0x00000020
-#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_gphy_sw_init_SHIFT 5
-
-/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_1_MONITOR :: genet2_sw_init [04:04] */
-#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_genet2_sw_init_MASK 0x00000010
-#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_genet2_sw_init_SHIFT 4
-
-/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_1_MONITOR :: m2mc1_sw_init [03:03] */
-#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_m2mc1_sw_init_MASK 0x00000008
-#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_m2mc1_sw_init_SHIFT 3
-
-/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_1_MONITOR :: v3d_top_sw_init [02:02] */
-#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_v3d_top_sw_init_MASK 0x00000004
-#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_v3d_top_sw_init_SHIFT 2
-
-/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_1_MONITOR :: vice20_sw_init [01:01] */
-#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_vice20_sw_init_MASK 0x00000002
-#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_vice20_sw_init_SHIFT 1
-
-/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_1_MONITOR :: sid_sw_init [00:00] */
-#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_sid_sw_init_MASK 0x00000001
-#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_sid_sw_init_SHIFT 0
-
-/***************************************************************************
- *FINAL_SW_INIT_1_MONITOR - Final software init 1 monitor
- ***************************************************************************/
-/* SUN_TOP_CTRL :: FINAL_SW_INIT_1_MONITOR :: spare0_sw_init [31:31] */
-#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_spare0_sw_init_MASK 0x80000000
-#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_spare0_sw_init_SHIFT 31
-
-/* SUN_TOP_CTRL :: FINAL_SW_INIT_1_MONITOR :: demod_xpt_sw_init [30:30] */
-#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_demod_xpt_sw_init_MASK 0x40000000
-#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_demod_xpt_sw_init_SHIFT 30
-
-/* SUN_TOP_CTRL :: FINAL_SW_INIT_1_MONITOR :: sdio1_sw_init [29:29] */
-#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_sdio1_sw_init_MASK 0x20000000
-#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_sdio1_sw_init_SHIFT 29
-
-/* SUN_TOP_CTRL :: FINAL_SW_INIT_1_MONITOR :: sdio0_sw_init [28:28] */
-#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_sdio0_sw_init_MASK 0x10000000
-#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_sdio0_sw_init_SHIFT 28
-
-/* SUN_TOP_CTRL :: FINAL_SW_INIT_1_MONITOR :: rf4ce_top_sw_init [27:27] */
-#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_rf4ce_top_sw_init_MASK 0x08000000
-#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_rf4ce_top_sw_init_SHIFT 27
-
-/* SUN_TOP_CTRL :: FINAL_SW_INIT_1_MONITOR :: avs_top_sw_init [26:26] */
-#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_avs_top_sw_init_MASK 0x04000000
-#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_avs_top_sw_init_SHIFT 26
-
-/* SUN_TOP_CTRL :: FINAL_SW_INIT_1_MONITOR :: hdmi_aon_sw_init [25:25] */
-#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_hdmi_aon_sw_init_MASK 0x02000000
-#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_hdmi_aon_sw_init_SHIFT 25
-
-/* SUN_TOP_CTRL :: FINAL_SW_INIT_1_MONITOR :: stb_chan_top_sw_init [24:24] */
-#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_stb_chan_top_sw_init_MASK 0x01000000
-#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_stb_chan_top_sw_init_SHIFT 24
-
-/* SUN_TOP_CTRL :: FINAL_SW_INIT_1_MONITOR :: aif_wb_stat_top1_sw_init [23:23] */
-#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_aif_wb_stat_top1_sw_init_MASK 0x00800000
-#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_aif_wb_stat_top1_sw_init_SHIFT 23
-
-/* SUN_TOP_CTRL :: FINAL_SW_INIT_1_MONITOR :: aif_wb_stat_top0_sw_init [22:22] */
-#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_aif_wb_stat_top0_sw_init_MASK 0x00400000
-#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_aif_wb_stat_top0_sw_init_SHIFT 22
-
-/* SUN_TOP_CTRL :: FINAL_SW_INIT_1_MONITOR :: aif_mdac_cal_top_sw_init [21:21] */
-#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_aif_mdac_cal_top_sw_init_MASK 0x00200000
-#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_aif_mdac_cal_top_sw_init_SHIFT 21
-
-/* SUN_TOP_CTRL :: FINAL_SW_INIT_1_MONITOR :: sds_afec3_sw_init [20:20] */
-#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_sds_afec3_sw_init_MASK 0x00100000
-#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_sds_afec3_sw_init_SHIFT 20
-
-/* SUN_TOP_CTRL :: FINAL_SW_INIT_1_MONITOR :: sds_afec2_sw_init [19:19] */
-#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_sds_afec2_sw_init_MASK 0x00080000
-#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_sds_afec2_sw_init_SHIFT 19
-
-/* SUN_TOP_CTRL :: FINAL_SW_INIT_1_MONITOR :: sds_afec1_sw_init [18:18] */
-#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_sds_afec1_sw_init_MASK 0x00040000
-#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_sds_afec1_sw_init_SHIFT 18
-
-/* SUN_TOP_CTRL :: FINAL_SW_INIT_1_MONITOR :: sds_afec0_sw_init [17:17] */
-#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_sds_afec0_sw_init_MASK 0x00020000
-#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_sds_afec0_sw_init_SHIFT 17
-
-/* SUN_TOP_CTRL :: FINAL_SW_INIT_1_MONITOR :: sds1_top3_sw_init [16:16] */
-#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_sds1_top3_sw_init_MASK 0x00010000
-#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_sds1_top3_sw_init_SHIFT 16
-
-/* SUN_TOP_CTRL :: FINAL_SW_INIT_1_MONITOR :: sds0_top3_sw_init [15:15] */
-#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_sds0_top3_sw_init_MASK 0x00008000
-#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_sds0_top3_sw_init_SHIFT 15
-
-/* SUN_TOP_CTRL :: FINAL_SW_INIT_1_MONITOR :: sds1_top2_sw_init [14:14] */
-#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_sds1_top2_sw_init_MASK 0x00004000
-#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_sds1_top2_sw_init_SHIFT 14
-
-/* SUN_TOP_CTRL :: FINAL_SW_INIT_1_MONITOR :: sds0_top2_sw_init [13:13] */
-#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_sds0_top2_sw_init_MASK 0x00002000
-#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_sds0_top2_sw_init_SHIFT 13
-
-/* SUN_TOP_CTRL :: FINAL_SW_INIT_1_MONITOR :: sds1_top1_sw_init [12:12] */
-#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_sds1_top1_sw_init_MASK 0x00001000
-#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_sds1_top1_sw_init_SHIFT 12
-
-/* SUN_TOP_CTRL :: FINAL_SW_INIT_1_MONITOR :: sds0_top1_sw_init [11:11] */
-#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_sds0_top1_sw_init_MASK 0x00000800
-#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_sds0_top1_sw_init_SHIFT 11
-
-/* SUN_TOP_CTRL :: FINAL_SW_INIT_1_MONITOR :: sds1_top0_sw_init [10:10] */
-#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_sds1_top0_sw_init_MASK 0x00000400
-#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_sds1_top0_sw_init_SHIFT 10
-
-/* SUN_TOP_CTRL :: FINAL_SW_INIT_1_MONITOR :: sds0_top0_sw_init [09:09] */
-#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_sds0_top0_sw_init_MASK 0x00000200
-#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_sds0_top0_sw_init_SHIFT 9
-
-/* SUN_TOP_CTRL :: FINAL_SW_INIT_1_MONITOR :: fsk_top_sw_init [08:08] */
-#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_fsk_top_sw_init_MASK 0x00000100
-#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_fsk_top_sw_init_SHIFT 8
-
-/* SUN_TOP_CTRL :: FINAL_SW_INIT_1_MONITOR :: leap_sw_init [07:07] */
-#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_leap_sw_init_MASK 0x00000080
-#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_leap_sw_init_SHIFT 7
-
-/* SUN_TOP_CTRL :: FINAL_SW_INIT_1_MONITOR :: reserved_for_padding0 [06:06] */
-#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_reserved_for_padding0_MASK 0x00000040
-#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_reserved_for_padding0_SHIFT 6
-
-/* SUN_TOP_CTRL :: FINAL_SW_INIT_1_MONITOR :: gphy_sw_init [05:05] */
-#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_gphy_sw_init_MASK 0x00000020
-#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_gphy_sw_init_SHIFT 5
-
-/* SUN_TOP_CTRL :: FINAL_SW_INIT_1_MONITOR :: genet2_sw_init [04:04] */
-#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_genet2_sw_init_MASK 0x00000010
-#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_genet2_sw_init_SHIFT 4
-
-/* SUN_TOP_CTRL :: FINAL_SW_INIT_1_MONITOR :: m2mc1_sw_init [03:03] */
-#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_m2mc1_sw_init_MASK 0x00000008
-#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_m2mc1_sw_init_SHIFT 3
-
-/* SUN_TOP_CTRL :: FINAL_SW_INIT_1_MONITOR :: v3d_top_sw_init [02:02] */
-#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_v3d_top_sw_init_MASK 0x00000004
-#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_v3d_top_sw_init_SHIFT 2
-
-/* SUN_TOP_CTRL :: FINAL_SW_INIT_1_MONITOR :: vice20_sw_init [01:01] */
-#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_vice20_sw_init_MASK 0x00000002
-#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_vice20_sw_init_SHIFT 1
-
-/* SUN_TOP_CTRL :: FINAL_SW_INIT_1_MONITOR :: sid_sw_init [00:00] */
-#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_sid_sw_init_MASK 0x00000001
-#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_sid_sw_init_SHIFT 0
-
-/***************************************************************************
- *SW_INIT_ONE_SHOT_TRIGGER - Software init one-shot trigger
- ***************************************************************************/
-/* SUN_TOP_CTRL :: SW_INIT_ONE_SHOT_TRIGGER :: reserved0 [31:02] */
-#define BCHP_SUN_TOP_CTRL_SW_INIT_ONE_SHOT_TRIGGER_reserved0_MASK 0xfffffffc
-#define BCHP_SUN_TOP_CTRL_SW_INIT_ONE_SHOT_TRIGGER_reserved0_SHIFT 2
-
-/* SUN_TOP_CTRL :: SW_INIT_ONE_SHOT_TRIGGER :: trigger_one_shot_1 [01:01] */
-#define BCHP_SUN_TOP_CTRL_SW_INIT_ONE_SHOT_TRIGGER_trigger_one_shot_1_MASK 0x00000002
-#define BCHP_SUN_TOP_CTRL_SW_INIT_ONE_SHOT_TRIGGER_trigger_one_shot_1_SHIFT 1
-#define BCHP_SUN_TOP_CTRL_SW_INIT_ONE_SHOT_TRIGGER_trigger_one_shot_1_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: SW_INIT_ONE_SHOT_TRIGGER :: trigger_one_shot_0 [00:00] */
-#define BCHP_SUN_TOP_CTRL_SW_INIT_ONE_SHOT_TRIGGER_trigger_one_shot_0_MASK 0x00000001
-#define BCHP_SUN_TOP_CTRL_SW_INIT_ONE_SHOT_TRIGGER_trigger_one_shot_0_SHIFT 0
-#define BCHP_SUN_TOP_CTRL_SW_INIT_ONE_SHOT_TRIGGER_trigger_one_shot_0_DEFAULT 0x00000000
-
-/***************************************************************************
- *ONE_SHOT_0_SW_INIT_WIDTH - One-shot 0 width
- ***************************************************************************/
-/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_WIDTH :: reserved0 [31:28] */
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_WIDTH_reserved0_MASK 0xf0000000
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_WIDTH_reserved0_SHIFT 28
-
-/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_WIDTH :: one_shot_0_width [27:00] */
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_WIDTH_one_shot_0_width_MASK 0x0fffffff
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_WIDTH_one_shot_0_width_SHIFT 0
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_WIDTH_one_shot_0_width_DEFAULT 0x00000000
-
-/***************************************************************************
- *ONE_SHOT_0_SW_INIT_0_MASK - One-shot 0 mask for software init 0
- ***************************************************************************/
-/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: reserved_for_padding0 [31:31] */
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_reserved_for_padding0_MASK 0x80000000
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_reserved_for_padding0_SHIFT 31
-
-/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: not_used_sw_init_30 [30:30] */
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_30_MASK 0x40000000
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_30_SHIFT 30
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_30_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: sata_sw_init [29:29] */
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_sata_sw_init_MASK 0x20000000
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_sata_sw_init_SHIFT 29
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_sata_sw_init_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: moca_sw_init [28:28] */
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_moca_sw_init_MASK 0x10000000
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_moca_sw_init_SHIFT 28
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_moca_sw_init_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: genet1_sw_init [27:27] */
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_genet1_sw_init_MASK 0x08000000
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_genet1_sw_init_SHIFT 27
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_genet1_sw_init_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: genet0_sw_init [26:26] */
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_genet0_sw_init_MASK 0x04000000
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_genet0_sw_init_SHIFT 26
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_genet0_sw_init_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: usb1_sw_init [25:25] */
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_usb1_sw_init_MASK 0x02000000
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_usb1_sw_init_SHIFT 25
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_usb1_sw_init_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: usb0_sw_init [24:24] */
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_usb0_sw_init_MASK 0x01000000
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_usb0_sw_init_SHIFT 24
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_usb0_sw_init_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: not_used_sw_init_23 [23:23] */
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_23_MASK 0x00800000
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_23_SHIFT 23
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_23_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: ddr1_sw_init [22:22] */
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_ddr1_sw_init_MASK 0x00400000
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_ddr1_sw_init_SHIFT 22
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_ddr1_sw_init_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: ddr0_sw_init [21:21] */
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_ddr0_sw_init_MASK 0x00200000
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_ddr0_sw_init_SHIFT 21
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_ddr0_sw_init_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: memc1_sw_init [20:20] */
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_memc1_sw_init_MASK 0x00100000
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_memc1_sw_init_SHIFT 20
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_memc1_sw_init_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: memc0_sw_init [19:19] */
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_memc0_sw_init_MASK 0x00080000
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_memc0_sw_init_SHIFT 19
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_memc0_sw_init_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: xpt_sw_init [18:18] */
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_xpt_sw_init_MASK 0x00040000
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_xpt_sw_init_SHIFT 18
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_xpt_sw_init_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: not_used_sw_init_17 [17:17] */
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_17_MASK 0x00020000
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_17_SHIFT 17
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_17_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: raaga0_sw_init [16:16] */
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_raaga0_sw_init_MASK 0x00010000
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_raaga0_sw_init_SHIFT 16
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_raaga0_sw_init_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: aio_sw_init [15:15] */
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_aio_sw_init_MASK 0x00008000
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_aio_sw_init_SHIFT 15
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_aio_sw_init_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: gfx_sw_init [14:14] */
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_gfx_sw_init_MASK 0x00004000
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_gfx_sw_init_SHIFT 14
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_gfx_sw_init_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: not_used_sw_init_13 [13:13] */
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_13_MASK 0x00002000
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_13_SHIFT 13
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_13_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: hvd0_sw_init [12:12] */
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_hvd0_sw_init_MASK 0x00001000
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_hvd0_sw_init_SHIFT 12
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_hvd0_sw_init_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: reserved_for_padding1 [11:11] */
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_reserved_for_padding1_MASK 0x00000800
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_reserved_for_padding1_SHIFT 11
-
-/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: dvp_ht0_sw_init [10:10] */
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_dvp_ht0_sw_init_MASK 0x00000400
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_dvp_ht0_sw_init_SHIFT 10
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_dvp_ht0_sw_init_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: vec_sw_init [09:09] */
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_vec_sw_init_MASK 0x00000200
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_vec_sw_init_SHIFT 9
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_vec_sw_init_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: bvn_sw_init [08:08] */
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_bvn_sw_init_MASK 0x00000100
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_bvn_sw_init_SHIFT 8
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_bvn_sw_init_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: pcie1_sw_init [07:07] */
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_pcie1_sw_init_MASK 0x00000080
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_pcie1_sw_init_SHIFT 7
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_pcie1_sw_init_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: ebi_sw_init [06:06] */
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_ebi_sw_init_MASK 0x00000040
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_ebi_sw_init_SHIFT 6
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_ebi_sw_init_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: pcie0_sw_init [05:05] */
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_pcie0_sw_init_MASK 0x00000020
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_pcie0_sw_init_SHIFT 5
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_pcie0_sw_init_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: webcpu_start_sw_init [04:04] */
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_webcpu_start_sw_init_MASK 0x00000010
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_webcpu_start_sw_init_SHIFT 4
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_webcpu_start_sw_init_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: webcpu_sw_init [03:03] */
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_webcpu_sw_init_MASK 0x00000008
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_webcpu_sw_init_SHIFT 3
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_webcpu_sw_init_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: ext_sys_sw_init [02:02] */
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_ext_sys_sw_init_MASK 0x00000004
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_ext_sys_sw_init_SHIFT 2
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_ext_sys_sw_init_DEFAULT 0x00000001
-
-/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: cpu_sw_init [01:01] */
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_cpu_sw_init_MASK 0x00000002
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_cpu_sw_init_SHIFT 1
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_cpu_sw_init_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: sys_ctrl_sw_init [00:00] */
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_sys_ctrl_sw_init_MASK 0x00000001
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_sys_ctrl_sw_init_SHIFT 0
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_sys_ctrl_sw_init_DEFAULT 0x00000000
-
-/***************************************************************************
- *ONE_SHOT_0_SW_INIT_1_MASK - One-shot 0 mask for software init 1
- ***************************************************************************/
-/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_1_MASK :: spare0_sw_init [31:31] */
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_spare0_sw_init_MASK 0x80000000
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_spare0_sw_init_SHIFT 31
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_spare0_sw_init_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_1_MASK :: demod_xpt_sw_init [30:30] */
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_demod_xpt_sw_init_MASK 0x40000000
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_demod_xpt_sw_init_SHIFT 30
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_demod_xpt_sw_init_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_1_MASK :: sdio1_sw_init [29:29] */
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_sdio1_sw_init_MASK 0x20000000
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_sdio1_sw_init_SHIFT 29
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_sdio1_sw_init_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_1_MASK :: sdio0_sw_init [28:28] */
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_sdio0_sw_init_MASK 0x10000000
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_sdio0_sw_init_SHIFT 28
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_sdio0_sw_init_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_1_MASK :: rf4ce_top_sw_init [27:27] */
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_rf4ce_top_sw_init_MASK 0x08000000
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_rf4ce_top_sw_init_SHIFT 27
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_rf4ce_top_sw_init_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_1_MASK :: avs_top_sw_init [26:26] */
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_avs_top_sw_init_MASK 0x04000000
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_avs_top_sw_init_SHIFT 26
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_avs_top_sw_init_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_1_MASK :: hdmi_aon_sw_init [25:25] */
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_hdmi_aon_sw_init_MASK 0x02000000
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_hdmi_aon_sw_init_SHIFT 25
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_hdmi_aon_sw_init_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_1_MASK :: stb_chan_top_sw_init [24:24] */
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_stb_chan_top_sw_init_MASK 0x01000000
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_stb_chan_top_sw_init_SHIFT 24
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_stb_chan_top_sw_init_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_1_MASK :: aif_wb_stat_top1_sw_init [23:23] */
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_aif_wb_stat_top1_sw_init_MASK 0x00800000
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_aif_wb_stat_top1_sw_init_SHIFT 23
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_aif_wb_stat_top1_sw_init_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_1_MASK :: aif_wb_stat_top0_sw_init [22:22] */
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_aif_wb_stat_top0_sw_init_MASK 0x00400000
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_aif_wb_stat_top0_sw_init_SHIFT 22
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_aif_wb_stat_top0_sw_init_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_1_MASK :: aif_mdac_cal_top_sw_init [21:21] */
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_aif_mdac_cal_top_sw_init_MASK 0x00200000
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_aif_mdac_cal_top_sw_init_SHIFT 21
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_aif_mdac_cal_top_sw_init_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_1_MASK :: sds_afec3_sw_init [20:20] */
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_sds_afec3_sw_init_MASK 0x00100000
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_sds_afec3_sw_init_SHIFT 20
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_sds_afec3_sw_init_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_1_MASK :: sds_afec2_sw_init [19:19] */
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_sds_afec2_sw_init_MASK 0x00080000
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_sds_afec2_sw_init_SHIFT 19
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_sds_afec2_sw_init_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_1_MASK :: sds_afec1_sw_init [18:18] */
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_sds_afec1_sw_init_MASK 0x00040000
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_sds_afec1_sw_init_SHIFT 18
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_sds_afec1_sw_init_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_1_MASK :: sds_afec0_sw_init [17:17] */
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_sds_afec0_sw_init_MASK 0x00020000
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_sds_afec0_sw_init_SHIFT 17
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_sds_afec0_sw_init_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_1_MASK :: sds1_top3_sw_init [16:16] */
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_sds1_top3_sw_init_MASK 0x00010000
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_sds1_top3_sw_init_SHIFT 16
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_sds1_top3_sw_init_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_1_MASK :: sds0_top3_sw_init [15:15] */
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_sds0_top3_sw_init_MASK 0x00008000
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_sds0_top3_sw_init_SHIFT 15
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_sds0_top3_sw_init_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_1_MASK :: sds1_top2_sw_init [14:14] */
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_sds1_top2_sw_init_MASK 0x00004000
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_sds1_top2_sw_init_SHIFT 14
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_sds1_top2_sw_init_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_1_MASK :: sds0_top2_sw_init [13:13] */
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_sds0_top2_sw_init_MASK 0x00002000
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_sds0_top2_sw_init_SHIFT 13
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_sds0_top2_sw_init_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_1_MASK :: sds1_top1_sw_init [12:12] */
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_sds1_top1_sw_init_MASK 0x00001000
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_sds1_top1_sw_init_SHIFT 12
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_sds1_top1_sw_init_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_1_MASK :: sds0_top1_sw_init [11:11] */
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_sds0_top1_sw_init_MASK 0x00000800
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_sds0_top1_sw_init_SHIFT 11
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_sds0_top1_sw_init_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_1_MASK :: sds1_top0_sw_init [10:10] */
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_sds1_top0_sw_init_MASK 0x00000400
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_sds1_top0_sw_init_SHIFT 10
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_sds1_top0_sw_init_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_1_MASK :: sds0_top0_sw_init [09:09] */
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_sds0_top0_sw_init_MASK 0x00000200
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_sds0_top0_sw_init_SHIFT 9
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_sds0_top0_sw_init_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_1_MASK :: fsk_top_sw_init [08:08] */
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_fsk_top_sw_init_MASK 0x00000100
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_fsk_top_sw_init_SHIFT 8
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_fsk_top_sw_init_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_1_MASK :: leap_sw_init [07:07] */
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_leap_sw_init_MASK 0x00000080
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_leap_sw_init_SHIFT 7
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_leap_sw_init_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_1_MASK :: reserved_for_padding0 [06:06] */
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_reserved_for_padding0_MASK 0x00000040
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_reserved_for_padding0_SHIFT 6
-
-/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_1_MASK :: gphy_sw_init [05:05] */
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_gphy_sw_init_MASK 0x00000020
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_gphy_sw_init_SHIFT 5
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_gphy_sw_init_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_1_MASK :: genet2_sw_init [04:04] */
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_genet2_sw_init_MASK 0x00000010
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_genet2_sw_init_SHIFT 4
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_genet2_sw_init_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_1_MASK :: m2mc1_sw_init [03:03] */
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_m2mc1_sw_init_MASK 0x00000008
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_m2mc1_sw_init_SHIFT 3
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_m2mc1_sw_init_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_1_MASK :: v3d_top_sw_init [02:02] */
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_v3d_top_sw_init_MASK 0x00000004
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_v3d_top_sw_init_SHIFT 2
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_v3d_top_sw_init_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_1_MASK :: vice20_sw_init [01:01] */
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_vice20_sw_init_MASK 0x00000002
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_vice20_sw_init_SHIFT 1
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_vice20_sw_init_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_1_MASK :: sid_sw_init [00:00] */
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_sid_sw_init_MASK 0x00000001
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_sid_sw_init_SHIFT 0
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_sid_sw_init_DEFAULT 0x00000000
-
-/***************************************************************************
- *ONE_SHOT_1_SW_INIT_WIDTH - One-shot 1 width
- ***************************************************************************/
-/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_WIDTH :: reserved0 [31:28] */
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_WIDTH_reserved0_MASK 0xf0000000
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_WIDTH_reserved0_SHIFT 28
-
-/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_WIDTH :: one_shot_1_width [27:00] */
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_WIDTH_one_shot_1_width_MASK 0x0fffffff
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_WIDTH_one_shot_1_width_SHIFT 0
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_WIDTH_one_shot_1_width_DEFAULT 0x00000000
-
-/***************************************************************************
- *ONE_SHOT_1_SW_INIT_0_MASK - One-shot 1 mask for software init 0
- ***************************************************************************/
-/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: reserved_for_padding0 [31:31] */
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_reserved_for_padding0_MASK 0x80000000
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_reserved_for_padding0_SHIFT 31
-
-/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: not_used_sw_init_30 [30:30] */
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_30_MASK 0x40000000
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_30_SHIFT 30
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_30_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: sata_sw_init [29:29] */
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_sata_sw_init_MASK 0x20000000
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_sata_sw_init_SHIFT 29
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_sata_sw_init_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: moca_sw_init [28:28] */
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_moca_sw_init_MASK 0x10000000
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_moca_sw_init_SHIFT 28
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_moca_sw_init_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: genet1_sw_init [27:27] */
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_genet1_sw_init_MASK 0x08000000
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_genet1_sw_init_SHIFT 27
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_genet1_sw_init_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: genet0_sw_init [26:26] */
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_genet0_sw_init_MASK 0x04000000
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_genet0_sw_init_SHIFT 26
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_genet0_sw_init_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: usb1_sw_init [25:25] */
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_usb1_sw_init_MASK 0x02000000
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_usb1_sw_init_SHIFT 25
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_usb1_sw_init_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: usb0_sw_init [24:24] */
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_usb0_sw_init_MASK 0x01000000
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_usb0_sw_init_SHIFT 24
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_usb0_sw_init_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: not_used_sw_init_23 [23:23] */
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_23_MASK 0x00800000
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_23_SHIFT 23
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_23_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: ddr1_sw_init [22:22] */
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_ddr1_sw_init_MASK 0x00400000
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_ddr1_sw_init_SHIFT 22
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_ddr1_sw_init_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: ddr0_sw_init [21:21] */
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_ddr0_sw_init_MASK 0x00200000
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_ddr0_sw_init_SHIFT 21
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_ddr0_sw_init_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: memc1_sw_init [20:20] */
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_memc1_sw_init_MASK 0x00100000
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_memc1_sw_init_SHIFT 20
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_memc1_sw_init_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: memc0_sw_init [19:19] */
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_memc0_sw_init_MASK 0x00080000
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_memc0_sw_init_SHIFT 19
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_memc0_sw_init_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: xpt_sw_init [18:18] */
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_xpt_sw_init_MASK 0x00040000
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_xpt_sw_init_SHIFT 18
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_xpt_sw_init_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: not_used_sw_init_17 [17:17] */
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_17_MASK 0x00020000
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_17_SHIFT 17
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_17_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: raaga0_sw_init [16:16] */
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_raaga0_sw_init_MASK 0x00010000
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_raaga0_sw_init_SHIFT 16
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_raaga0_sw_init_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: aio_sw_init [15:15] */
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_aio_sw_init_MASK 0x00008000
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_aio_sw_init_SHIFT 15
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_aio_sw_init_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: gfx_sw_init [14:14] */
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_gfx_sw_init_MASK 0x00004000
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_gfx_sw_init_SHIFT 14
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_gfx_sw_init_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: not_used_sw_init_13 [13:13] */
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_13_MASK 0x00002000
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_13_SHIFT 13
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_13_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: hvd0_sw_init [12:12] */
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_hvd0_sw_init_MASK 0x00001000
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_hvd0_sw_init_SHIFT 12
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_hvd0_sw_init_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: reserved_for_padding1 [11:11] */
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_reserved_for_padding1_MASK 0x00000800
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_reserved_for_padding1_SHIFT 11
-
-/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: dvp_ht0_sw_init [10:10] */
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_dvp_ht0_sw_init_MASK 0x00000400
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_dvp_ht0_sw_init_SHIFT 10
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_dvp_ht0_sw_init_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: vec_sw_init [09:09] */
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_vec_sw_init_MASK 0x00000200
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_vec_sw_init_SHIFT 9
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_vec_sw_init_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: bvn_sw_init [08:08] */
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_bvn_sw_init_MASK 0x00000100
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_bvn_sw_init_SHIFT 8
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_bvn_sw_init_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: pcie1_sw_init [07:07] */
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_pcie1_sw_init_MASK 0x00000080
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_pcie1_sw_init_SHIFT 7
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_pcie1_sw_init_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: ebi_sw_init [06:06] */
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_ebi_sw_init_MASK 0x00000040
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_ebi_sw_init_SHIFT 6
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_ebi_sw_init_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: pcie0_sw_init [05:05] */
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_pcie0_sw_init_MASK 0x00000020
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_pcie0_sw_init_SHIFT 5
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_pcie0_sw_init_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: webcpu_start_sw_init [04:04] */
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_webcpu_start_sw_init_MASK 0x00000010
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_webcpu_start_sw_init_SHIFT 4
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_webcpu_start_sw_init_DEFAULT 0x00000001
-
-/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: webcpu_sw_init [03:03] */
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_webcpu_sw_init_MASK 0x00000008
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_webcpu_sw_init_SHIFT 3
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_webcpu_sw_init_DEFAULT 0x00000001
-
-/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: ext_sys_sw_init [02:02] */
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_ext_sys_sw_init_MASK 0x00000004
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_ext_sys_sw_init_SHIFT 2
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_ext_sys_sw_init_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: cpu_sw_init [01:01] */
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_cpu_sw_init_MASK 0x00000002
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_cpu_sw_init_SHIFT 1
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_cpu_sw_init_DEFAULT 0x00000001
-
-/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: sys_ctrl_sw_init [00:00] */
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_sys_ctrl_sw_init_MASK 0x00000001
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_sys_ctrl_sw_init_SHIFT 0
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_sys_ctrl_sw_init_DEFAULT 0x00000000
-
-/***************************************************************************
- *ONE_SHOT_1_SW_INIT_1_MASK - One-shot 1 mask for software init 1
- ***************************************************************************/
-/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_1_MASK :: spare0_sw_init [31:31] */
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_spare0_sw_init_MASK 0x80000000
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_spare0_sw_init_SHIFT 31
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_spare0_sw_init_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_1_MASK :: demod_xpt_sw_init [30:30] */
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_demod_xpt_sw_init_MASK 0x40000000
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_demod_xpt_sw_init_SHIFT 30
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_demod_xpt_sw_init_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_1_MASK :: sdio1_sw_init [29:29] */
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_sdio1_sw_init_MASK 0x20000000
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_sdio1_sw_init_SHIFT 29
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_sdio1_sw_init_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_1_MASK :: sdio0_sw_init [28:28] */
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_sdio0_sw_init_MASK 0x10000000
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_sdio0_sw_init_SHIFT 28
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_sdio0_sw_init_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_1_MASK :: rf4ce_top_sw_init [27:27] */
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_rf4ce_top_sw_init_MASK 0x08000000
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_rf4ce_top_sw_init_SHIFT 27
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_rf4ce_top_sw_init_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_1_MASK :: avs_top_sw_init [26:26] */
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_avs_top_sw_init_MASK 0x04000000
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_avs_top_sw_init_SHIFT 26
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_avs_top_sw_init_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_1_MASK :: hdmi_aon_sw_init [25:25] */
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_hdmi_aon_sw_init_MASK 0x02000000
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_hdmi_aon_sw_init_SHIFT 25
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_hdmi_aon_sw_init_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_1_MASK :: stb_chan_top_sw_init [24:24] */
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_stb_chan_top_sw_init_MASK 0x01000000
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_stb_chan_top_sw_init_SHIFT 24
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_stb_chan_top_sw_init_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_1_MASK :: aif_wb_stat_top1_sw_init [23:23] */
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_aif_wb_stat_top1_sw_init_MASK 0x00800000
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_aif_wb_stat_top1_sw_init_SHIFT 23
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_aif_wb_stat_top1_sw_init_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_1_MASK :: aif_wb_stat_top0_sw_init [22:22] */
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_aif_wb_stat_top0_sw_init_MASK 0x00400000
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_aif_wb_stat_top0_sw_init_SHIFT 22
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_aif_wb_stat_top0_sw_init_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_1_MASK :: aif_mdac_cal_top_sw_init [21:21] */
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_aif_mdac_cal_top_sw_init_MASK 0x00200000
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_aif_mdac_cal_top_sw_init_SHIFT 21
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_aif_mdac_cal_top_sw_init_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_1_MASK :: sds_afec3_sw_init [20:20] */
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_sds_afec3_sw_init_MASK 0x00100000
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_sds_afec3_sw_init_SHIFT 20
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_sds_afec3_sw_init_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_1_MASK :: sds_afec2_sw_init [19:19] */
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_sds_afec2_sw_init_MASK 0x00080000
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_sds_afec2_sw_init_SHIFT 19
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_sds_afec2_sw_init_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_1_MASK :: sds_afec1_sw_init [18:18] */
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_sds_afec1_sw_init_MASK 0x00040000
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_sds_afec1_sw_init_SHIFT 18
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_sds_afec1_sw_init_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_1_MASK :: sds_afec0_sw_init [17:17] */
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_sds_afec0_sw_init_MASK 0x00020000
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_sds_afec0_sw_init_SHIFT 17
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_sds_afec0_sw_init_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_1_MASK :: sds1_top3_sw_init [16:16] */
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_sds1_top3_sw_init_MASK 0x00010000
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_sds1_top3_sw_init_SHIFT 16
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_sds1_top3_sw_init_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_1_MASK :: sds0_top3_sw_init [15:15] */
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_sds0_top3_sw_init_MASK 0x00008000
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_sds0_top3_sw_init_SHIFT 15
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_sds0_top3_sw_init_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_1_MASK :: sds1_top2_sw_init [14:14] */
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_sds1_top2_sw_init_MASK 0x00004000
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_sds1_top2_sw_init_SHIFT 14
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_sds1_top2_sw_init_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_1_MASK :: sds0_top2_sw_init [13:13] */
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_sds0_top2_sw_init_MASK 0x00002000
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_sds0_top2_sw_init_SHIFT 13
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_sds0_top2_sw_init_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_1_MASK :: sds1_top1_sw_init [12:12] */
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_sds1_top1_sw_init_MASK 0x00001000
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_sds1_top1_sw_init_SHIFT 12
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_sds1_top1_sw_init_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_1_MASK :: sds0_top1_sw_init [11:11] */
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_sds0_top1_sw_init_MASK 0x00000800
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_sds0_top1_sw_init_SHIFT 11
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_sds0_top1_sw_init_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_1_MASK :: sds1_top0_sw_init [10:10] */
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_sds1_top0_sw_init_MASK 0x00000400
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_sds1_top0_sw_init_SHIFT 10
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_sds1_top0_sw_init_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_1_MASK :: sds0_top0_sw_init [09:09] */
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_sds0_top0_sw_init_MASK 0x00000200
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_sds0_top0_sw_init_SHIFT 9
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_sds0_top0_sw_init_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_1_MASK :: fsk_top_sw_init [08:08] */
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_fsk_top_sw_init_MASK 0x00000100
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_fsk_top_sw_init_SHIFT 8
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_fsk_top_sw_init_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_1_MASK :: leap_sw_init [07:07] */
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_leap_sw_init_MASK 0x00000080
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_leap_sw_init_SHIFT 7
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_leap_sw_init_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_1_MASK :: reserved_for_padding0 [06:06] */
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_reserved_for_padding0_MASK 0x00000040
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_reserved_for_padding0_SHIFT 6
-
-/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_1_MASK :: gphy_sw_init [05:05] */
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_gphy_sw_init_MASK 0x00000020
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_gphy_sw_init_SHIFT 5
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_gphy_sw_init_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_1_MASK :: genet2_sw_init [04:04] */
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_genet2_sw_init_MASK 0x00000010
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_genet2_sw_init_SHIFT 4
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_genet2_sw_init_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_1_MASK :: m2mc1_sw_init [03:03] */
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_m2mc1_sw_init_MASK 0x00000008
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_m2mc1_sw_init_SHIFT 3
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_m2mc1_sw_init_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_1_MASK :: v3d_top_sw_init [02:02] */
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_v3d_top_sw_init_MASK 0x00000004
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_v3d_top_sw_init_SHIFT 2
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_v3d_top_sw_init_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_1_MASK :: vice20_sw_init [01:01] */
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_vice20_sw_init_MASK 0x00000002
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_vice20_sw_init_SHIFT 1
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_vice20_sw_init_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_1_MASK :: sid_sw_init [00:00] */
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_sid_sw_init_MASK 0x00000001
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_sid_sw_init_SHIFT 0
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_sid_sw_init_DEFAULT 0x00000000
-
-/***************************************************************************
- *UNCLEARED_SCRATCH - Scratch register
- ***************************************************************************/
-/* SUN_TOP_CTRL :: UNCLEARED_SCRATCH :: uncleared_scratch [31:00] */
-#define BCHP_SUN_TOP_CTRL_UNCLEARED_SCRATCH_uncleared_scratch_MASK 0xffffffff
-#define BCHP_SUN_TOP_CTRL_UNCLEARED_SCRATCH_uncleared_scratch_SHIFT 0
-#define BCHP_SUN_TOP_CTRL_UNCLEARED_SCRATCH_uncleared_scratch_DEFAULT 0x00000000
-
-/***************************************************************************
- *SPARE_CTRL - Spare control bits reserved for future use
- ***************************************************************************/
-/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_31 [31:31] */
-#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_31_MASK 0x80000000
-#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_31_SHIFT 31
-#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_31_DEFAULT 0x00000001
-
-/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_30 [30:30] */
-#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_30_MASK 0x40000000
-#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_30_SHIFT 30
-#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_30_DEFAULT 0x00000001
-
-/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_29 [29:29] */
-#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_29_MASK 0x20000000
-#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_29_SHIFT 29
-#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_29_DEFAULT 0x00000001
-
-/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_28 [28:28] */
-#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_28_MASK 0x10000000
-#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_28_SHIFT 28
-#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_28_DEFAULT 0x00000001
-
-/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_27 [27:27] */
-#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_27_MASK 0x08000000
-#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_27_SHIFT 27
-#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_27_DEFAULT 0x00000001
-
-/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_26 [26:26] */
-#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_26_MASK 0x04000000
-#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_26_SHIFT 26
-#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_26_DEFAULT 0x00000001
-
-/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_25 [25:25] */
-#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_25_MASK 0x02000000
-#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_25_SHIFT 25
-#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_25_DEFAULT 0x00000001
-
-/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_24 [24:24] */
-#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_24_MASK 0x01000000
-#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_24_SHIFT 24
-#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_24_DEFAULT 0x00000001
-
-/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_23 [23:23] */
-#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_23_MASK 0x00800000
-#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_23_SHIFT 23
-#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_23_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_22 [22:22] */
-#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_22_MASK 0x00400000
-#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_22_SHIFT 22
-#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_22_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_21 [21:21] */
-#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_21_MASK 0x00200000
-#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_21_SHIFT 21
-#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_21_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_20 [20:20] */
-#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_20_MASK 0x00100000
-#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_20_SHIFT 20
-#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_20_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_19 [19:19] */
-#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_19_MASK 0x00080000
-#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_19_SHIFT 19
-#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_19_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_18 [18:18] */
-#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_18_MASK 0x00040000
-#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_18_SHIFT 18
-#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_18_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_17 [17:17] */
-#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_17_MASK 0x00020000
-#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_17_SHIFT 17
-#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_17_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_16 [16:16] */
-#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_16_MASK 0x00010000
-#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_16_SHIFT 16
-#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_16_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_15 [15:15] */
-#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_15_MASK 0x00008000
-#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_15_SHIFT 15
-#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_15_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_14 [14:14] */
-#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_14_MASK 0x00004000
-#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_14_SHIFT 14
-#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_14_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_13 [13:13] */
-#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_13_MASK 0x00002000
-#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_13_SHIFT 13
-#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_13_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_12 [12:12] */
-#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_12_MASK 0x00001000
-#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_12_SHIFT 12
-#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_12_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_11 [11:11] */
-#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_11_MASK 0x00000800
-#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_11_SHIFT 11
-#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_11_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_10 [10:10] */
-#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_10_MASK 0x00000400
-#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_10_SHIFT 10
-#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_10_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_09 [09:09] */
-#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_09_MASK 0x00000200
-#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_09_SHIFT 9
-#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_09_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_08 [08:08] */
-#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_08_MASK 0x00000100
-#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_08_SHIFT 8
-#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_08_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_07 [07:07] */
-#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_07_MASK 0x00000080
-#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_07_SHIFT 7
-#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_07_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_06 [06:06] */
-#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_06_MASK 0x00000040
-#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_06_SHIFT 6
-#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_06_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_05 [05:05] */
-#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_05_MASK 0x00000020
-#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_05_SHIFT 5
-#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_05_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_04 [04:04] */
-#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_04_MASK 0x00000010
-#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_04_SHIFT 4
-#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_04_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_03 [03:03] */
-#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_03_MASK 0x00000008
-#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_03_SHIFT 3
-#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_03_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_02 [02:02] */
-#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_02_MASK 0x00000004
-#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_02_SHIFT 2
-#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_02_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_01 [01:01] */
-#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_01_MASK 0x00000002
-#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_01_SHIFT 1
-#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_01_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_00 [00:00] */
-#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_00_MASK 0x00000001
-#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_00_SHIFT 0
-#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_00_DEFAULT 0x00000000
-
-/***************************************************************************
- *TEST_PORT_CTRL - Test port control
- ***************************************************************************/
-/* SUN_TOP_CTRL :: TEST_PORT_CTRL :: sys_ctrl_local_tp_out_sel [31:28] */
-#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sys_ctrl_local_tp_out_sel_MASK 0xf0000000
-#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sys_ctrl_local_tp_out_sel_SHIFT 28
-#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sys_ctrl_local_tp_out_sel_DEFAULT 0x00000000
-#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sys_ctrl_local_tp_out_sel_SEMAPHORE_0 0
-#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sys_ctrl_local_tp_out_sel_SEMAPHORE_1 1
-#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sys_ctrl_local_tp_out_sel_UNUSED_02 2
-#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sys_ctrl_local_tp_out_sel_MISC_TEST 3
-#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sys_ctrl_local_tp_out_sel_SSP 4
-#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sys_ctrl_local_tp_out_sel_TP_OUT_POKE_REG 5
-#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sys_ctrl_local_tp_out_sel_TP_IN 6
-#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sys_ctrl_local_tp_out_sel_UNUSED_07 7
-#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sys_ctrl_local_tp_out_sel_UNUSED_08 8
-#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sys_ctrl_local_tp_out_sel_UNUSED_09 9
-#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sys_ctrl_local_tp_out_sel_UNUSED_10 10
-#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sys_ctrl_local_tp_out_sel_UNUSED_11 11
-#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sys_ctrl_local_tp_out_sel_UPG_TP_OUT 12
-#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sys_ctrl_local_tp_out_sel_UNUSED_13 13
-#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sys_ctrl_local_tp_out_sel_ICID_TP_OUT 14
-#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sys_ctrl_local_tp_out_sel_TOP_AUX_TP_OUT 15
-
-/* SUN_TOP_CTRL :: TEST_PORT_CTRL :: reserved0 [27:10] */
-#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_reserved0_MASK 0x0ffffc00
-#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_reserved0_SHIFT 10
-
-/* SUN_TOP_CTRL :: TEST_PORT_CTRL :: tp_in_source_select [09:09] */
-#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_tp_in_source_select_MASK 0x00000200
-#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_tp_in_source_select_SHIFT 9
-#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_tp_in_source_select_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: TEST_PORT_CTRL :: tp_select [08:07] */
-#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_tp_select_MASK 0x00000180
-#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_tp_select_SHIFT 7
-#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_tp_select_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: TEST_PORT_CTRL :: encoded_tp_enable [06:00] */
-#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_MASK 0x0000007f
-#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_SHIFT 0
-#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_DEFAULT 0x0000007f
-#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_GENET0 0
-#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_SATA 1
-#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_RF4CE_TOP 2
-#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_AIF_MDAC_CAL_TOP 12
-#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_AIF_WB_SAT_TOP0 13
-#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_AIF_WB_SAT_TOP1 14
-#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_STB_CHAN_TOP 15
-#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_SYS 16
-#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_CLK 17
-#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_AON 18
-#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_HIF 19
-#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_AVS 20
-#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_BSP 21
-#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_VEC 22
-#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_AIO 23
-#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_HVD0 25
-#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_RAAGA0 28
-#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_XPT 30
-#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_MEMC0 31
-#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_MEMC1 32
-#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_GENET1 34
-#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_GENET2 35
-#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_PCIE0 36
-#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_PCIE1 37
-#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_USB0 38
-#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_USB1 39
-#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_MOCA 40
-#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_V3D_TOP 41
-#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_RFM 42
-#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_FSK_TOP 43
-#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_SDS0_R_0 44
-#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_SDS0_T_0 45
-#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_SDS1_R_0 46
-#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_SDS1_T_0 47
-#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_SDS0_R_1 48
-#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_SDS0_T_1 49
-#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_SDS1_R_1 50
-#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_SDS1_T_1 51
-#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_SDS0_R_2 52
-#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_SDS0_T_2 53
-#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_SDS1_R_2 54
-#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_SDS1_T_2 55
-#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_SDS0_R_3 56
-#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_SDS0_T_3 57
-#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_SDS1_R_3 58
-#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_SDS1_T_3 59
-#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_SDS_AFEC0 60
-#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_SDS_AFEC1 61
-#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_SDS_AFEC2 62
-#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_SDS_AFEC3 63
-
-/***************************************************************************
- *TEST_PORT_OUT_PEEK - Testport peek register
- ***************************************************************************/
-/* SUN_TOP_CTRL :: TEST_PORT_OUT_PEEK :: test_port_out_peek_value [31:00] */
-#define BCHP_SUN_TOP_CTRL_TEST_PORT_OUT_PEEK_test_port_out_peek_value_MASK 0xffffffff
-#define BCHP_SUN_TOP_CTRL_TEST_PORT_OUT_PEEK_test_port_out_peek_value_SHIFT 0
-
-/***************************************************************************
- *TEST_PORT_OUT_POKE - Testport poke register
- ***************************************************************************/
-/* SUN_TOP_CTRL :: TEST_PORT_OUT_POKE :: test_port_out_poke_value [31:00] */
-#define BCHP_SUN_TOP_CTRL_TEST_PORT_OUT_POKE_test_port_out_poke_value_MASK 0xffffffff
-#define BCHP_SUN_TOP_CTRL_TEST_PORT_OUT_POKE_test_port_out_poke_value_SHIFT 0
-#define BCHP_SUN_TOP_CTRL_TEST_PORT_OUT_POKE_test_port_out_poke_value_DEFAULT 0x00000000
-
-/***************************************************************************
- *TEST_PORT_IN_PEEK - Testport peek register
- ***************************************************************************/
-/* SUN_TOP_CTRL :: TEST_PORT_IN_PEEK :: test_port_in_peek_value [31:00] */
-#define BCHP_SUN_TOP_CTRL_TEST_PORT_IN_PEEK_test_port_in_peek_value_MASK 0xffffffff
-#define BCHP_SUN_TOP_CTRL_TEST_PORT_IN_PEEK_test_port_in_peek_value_SHIFT 0
-
-/***************************************************************************
- *TEST_PORT_IN_POKE - Testport poke register
- ***************************************************************************/
-/* SUN_TOP_CTRL :: TEST_PORT_IN_POKE :: test_port_in_poke_value [31:00] */
-#define BCHP_SUN_TOP_CTRL_TEST_PORT_IN_POKE_test_port_in_poke_value_MASK 0xffffffff
-#define BCHP_SUN_TOP_CTRL_TEST_PORT_IN_POKE_test_port_in_poke_value_SHIFT 0
-#define BCHP_SUN_TOP_CTRL_TEST_PORT_IN_POKE_test_port_in_poke_value_DEFAULT 0x00000000
-
-/***************************************************************************
- *EJTAG_INPUT_EN - EJTAG input bus enables
- ***************************************************************************/
-/* SUN_TOP_CTRL :: EJTAG_INPUT_EN :: reserved0 [31:11] */
-#define BCHP_SUN_TOP_CTRL_EJTAG_INPUT_EN_reserved0_MASK 0xfffff800
-#define BCHP_SUN_TOP_CTRL_EJTAG_INPUT_EN_reserved0_SHIFT 11
-
-/* SUN_TOP_CTRL :: EJTAG_INPUT_EN :: ejtag_input_enable [10:00] */
-#define BCHP_SUN_TOP_CTRL_EJTAG_INPUT_EN_ejtag_input_enable_MASK 0x000007ff
-#define BCHP_SUN_TOP_CTRL_EJTAG_INPUT_EN_ejtag_input_enable_SHIFT 0
-#define BCHP_SUN_TOP_CTRL_EJTAG_INPUT_EN_ejtag_input_enable_DEFAULT 0x00000002
-#define BCHP_SUN_TOP_CTRL_EJTAG_INPUT_EN_ejtag_input_enable_DO_NOT_USE_CPU_ONE_HOT 1
-#define BCHP_SUN_TOP_CTRL_EJTAG_INPUT_EN_ejtag_input_enable_MAIN_CPU_ONE_HOT 2
-#define BCHP_SUN_TOP_CTRL_EJTAG_INPUT_EN_ejtag_input_enable_MOCA0_CPU_ONE_HOT 4
-#define BCHP_SUN_TOP_CTRL_EJTAG_INPUT_EN_ejtag_input_enable_MOCA1_CPU_ONE_HOT 8
-#define BCHP_SUN_TOP_CTRL_EJTAG_INPUT_EN_ejtag_input_enable_VICE20_ARC0_CPU_ONE_HOT 16
-#define BCHP_SUN_TOP_CTRL_EJTAG_INPUT_EN_ejtag_input_enable_VICE20_ARC1_CPU_ONE_HOT 32
-#define BCHP_SUN_TOP_CTRL_EJTAG_INPUT_EN_ejtag_input_enable_AVS_CPU_ONE_HOT 64
-#define BCHP_SUN_TOP_CTRL_EJTAG_INPUT_EN_ejtag_input_enable_LEAP_CPU_ONE_HOT 128
-#define BCHP_SUN_TOP_CTRL_EJTAG_INPUT_EN_ejtag_input_enable_RF4CE_CPU_ONE_HOT 256
-#define BCHP_SUN_TOP_CTRL_EJTAG_INPUT_EN_ejtag_input_enable_SCPU_CPU_ONE_HOT 512
-#define BCHP_SUN_TOP_CTRL_EJTAG_INPUT_EN_ejtag_input_enable_BSP_CPU_ONE_HOT 1024
-
-/***************************************************************************
- *EJTAG_OUTPUT_SEL - EJTAG output select
- ***************************************************************************/
-/* SUN_TOP_CTRL :: EJTAG_OUTPUT_SEL :: reserved0 [31:04] */
-#define BCHP_SUN_TOP_CTRL_EJTAG_OUTPUT_SEL_reserved0_MASK 0xfffffff0
-#define BCHP_SUN_TOP_CTRL_EJTAG_OUTPUT_SEL_reserved0_SHIFT 4
-
-/* SUN_TOP_CTRL :: EJTAG_OUTPUT_SEL :: ejtag_output_sel [03:00] */
-#define BCHP_SUN_TOP_CTRL_EJTAG_OUTPUT_SEL_ejtag_output_sel_MASK 0x0000000f
-#define BCHP_SUN_TOP_CTRL_EJTAG_OUTPUT_SEL_ejtag_output_sel_SHIFT 0
-#define BCHP_SUN_TOP_CTRL_EJTAG_OUTPUT_SEL_ejtag_output_sel_DEFAULT 0x00000001
-#define BCHP_SUN_TOP_CTRL_EJTAG_OUTPUT_SEL_ejtag_output_sel_DO_NOT_USE_CPU 0
-#define BCHP_SUN_TOP_CTRL_EJTAG_OUTPUT_SEL_ejtag_output_sel_MAIN_CPU 1
-#define BCHP_SUN_TOP_CTRL_EJTAG_OUTPUT_SEL_ejtag_output_sel_MOCA0_CPU 2
-#define BCHP_SUN_TOP_CTRL_EJTAG_OUTPUT_SEL_ejtag_output_sel_MOCA1_CPU 3
-#define BCHP_SUN_TOP_CTRL_EJTAG_OUTPUT_SEL_ejtag_output_sel_VICE20_ARC0_CPU 4
-#define BCHP_SUN_TOP_CTRL_EJTAG_OUTPUT_SEL_ejtag_output_sel_VICE20_ARC1_CPU 5
-#define BCHP_SUN_TOP_CTRL_EJTAG_OUTPUT_SEL_ejtag_output_sel_AVS_CPU 6
-#define BCHP_SUN_TOP_CTRL_EJTAG_OUTPUT_SEL_ejtag_output_sel_LEAP_CPU 7
-#define BCHP_SUN_TOP_CTRL_EJTAG_OUTPUT_SEL_ejtag_output_sel_RF4CE_CPU 8
-#define BCHP_SUN_TOP_CTRL_EJTAG_OUTPUT_SEL_ejtag_output_sel_SCPU_CPU 9
-#define BCHP_SUN_TOP_CTRL_EJTAG_OUTPUT_SEL_ejtag_output_sel_BSP_CPU 10
-
-/***************************************************************************
- *VTRAP_CTRL - VTRAP Control
- ***************************************************************************/
-/* SUN_TOP_CTRL :: VTRAP_CTRL :: reserved0 [31:23] */
-#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_reserved0_MASK 0xff800000
-#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_reserved0_SHIFT 23
-
-/* SUN_TOP_CTRL :: VTRAP_CTRL :: vtrap_enable_max_1_threshold [22:22] */
-#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_enable_max_1_threshold_MASK 0x00400000
-#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_enable_max_1_threshold_SHIFT 22
-#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_enable_max_1_threshold_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: VTRAP_CTRL :: vtrap_enable_min_1_threshold [21:21] */
-#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_enable_min_1_threshold_MASK 0x00200000
-#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_enable_min_1_threshold_SHIFT 21
-#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_enable_min_1_threshold_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: VTRAP_CTRL :: vtrap_enable_min_0_threshold [20:20] */
-#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_enable_min_0_threshold_MASK 0x00100000
-#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_enable_min_0_threshold_SHIFT 20
-#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_enable_min_0_threshold_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: VTRAP_CTRL :: vtrap_enable_warning_1_threshold [19:19] */
-#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_enable_warning_1_threshold_MASK 0x00080000
-#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_enable_warning_1_threshold_SHIFT 19
-#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_enable_warning_1_threshold_DEFAULT 0x00000001
-
-/* SUN_TOP_CTRL :: VTRAP_CTRL :: vtrap_enable_warning_0_threshold [18:18] */
-#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_enable_warning_0_threshold_MASK 0x00040000
-#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_enable_warning_0_threshold_SHIFT 18
-#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_enable_warning_0_threshold_DEFAULT 0x00000001
-
-/* SUN_TOP_CTRL :: VTRAP_CTRL :: vtrap_vddcmon_test_trim_code [17:05] */
-#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_vddcmon_test_trim_code_MASK 0x0003ffe0
-#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_vddcmon_test_trim_code_SHIFT 5
-#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_vddcmon_test_trim_code_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: VTRAP_CTRL :: vtrap_threshold_warning_1_status_clear [04:04] */
-#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_threshold_warning_1_status_clear_MASK 0x00000010
-#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_threshold_warning_1_status_clear_SHIFT 4
-#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_threshold_warning_1_status_clear_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: VTRAP_CTRL :: vtrap_threshold_warning_0_status_clear [03:03] */
-#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_threshold_warning_0_status_clear_MASK 0x00000008
-#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_threshold_warning_0_status_clear_SHIFT 3
-#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_threshold_warning_0_status_clear_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: VTRAP_CTRL :: vtrap_threshold_min_1_status_clear [02:02] */
-#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_threshold_min_1_status_clear_MASK 0x00000004
-#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_threshold_min_1_status_clear_SHIFT 2
-#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_threshold_min_1_status_clear_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: VTRAP_CTRL :: vtrap_threshold_min_0_status_clear [01:01] */
-#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_threshold_min_0_status_clear_MASK 0x00000002
-#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_threshold_min_0_status_clear_SHIFT 1
-#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_threshold_min_0_status_clear_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: VTRAP_CTRL :: vtrap_threshold_max_1_status_clear [00:00] */
-#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_threshold_max_1_status_clear_MASK 0x00000001
-#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_threshold_max_1_status_clear_SHIFT 0
-#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_threshold_max_1_status_clear_DEFAULT 0x00000000
-
-/***************************************************************************
- *VTRAP_STATUS - VTRAP Status
- ***************************************************************************/
-/* SUN_TOP_CTRL :: VTRAP_STATUS :: reserved0 [31:05] */
-#define BCHP_SUN_TOP_CTRL_VTRAP_STATUS_reserved0_MASK 0xffffffe0
-#define BCHP_SUN_TOP_CTRL_VTRAP_STATUS_reserved0_SHIFT 5
-
-/* SUN_TOP_CTRL :: VTRAP_STATUS :: vtrap_threshold_warning_1_status [04:04] */
-#define BCHP_SUN_TOP_CTRL_VTRAP_STATUS_vtrap_threshold_warning_1_status_MASK 0x00000010
-#define BCHP_SUN_TOP_CTRL_VTRAP_STATUS_vtrap_threshold_warning_1_status_SHIFT 4
-#define BCHP_SUN_TOP_CTRL_VTRAP_STATUS_vtrap_threshold_warning_1_status_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: VTRAP_STATUS :: vtrap_threshold_warning_0_status [03:03] */
-#define BCHP_SUN_TOP_CTRL_VTRAP_STATUS_vtrap_threshold_warning_0_status_MASK 0x00000008
-#define BCHP_SUN_TOP_CTRL_VTRAP_STATUS_vtrap_threshold_warning_0_status_SHIFT 3
-#define BCHP_SUN_TOP_CTRL_VTRAP_STATUS_vtrap_threshold_warning_0_status_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: VTRAP_STATUS :: vtrap_threshold_min_1_status [02:02] */
-#define BCHP_SUN_TOP_CTRL_VTRAP_STATUS_vtrap_threshold_min_1_status_MASK 0x00000004
-#define BCHP_SUN_TOP_CTRL_VTRAP_STATUS_vtrap_threshold_min_1_status_SHIFT 2
-#define BCHP_SUN_TOP_CTRL_VTRAP_STATUS_vtrap_threshold_min_1_status_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: VTRAP_STATUS :: vtrap_threshold_min_0_status [01:01] */
-#define BCHP_SUN_TOP_CTRL_VTRAP_STATUS_vtrap_threshold_min_0_status_MASK 0x00000002
-#define BCHP_SUN_TOP_CTRL_VTRAP_STATUS_vtrap_threshold_min_0_status_SHIFT 1
-#define BCHP_SUN_TOP_CTRL_VTRAP_STATUS_vtrap_threshold_min_0_status_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: VTRAP_STATUS :: vtrap_threshold_max_1_status [00:00] */
-#define BCHP_SUN_TOP_CTRL_VTRAP_STATUS_vtrap_threshold_max_1_status_MASK 0x00000001
-#define BCHP_SUN_TOP_CTRL_VTRAP_STATUS_vtrap_threshold_max_1_status_SHIFT 0
-#define BCHP_SUN_TOP_CTRL_VTRAP_STATUS_vtrap_threshold_max_1_status_DEFAULT 0x00000000
-
-/***************************************************************************
- *UART_ROUTER_SEL_0 - UART Router select 0
- ***************************************************************************/
-/* SUN_TOP_CTRL :: UART_ROUTER_SEL_0 :: reserved0 [31:30] */
-#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_reserved0_MASK 0xc0000000
-#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_reserved0_SHIFT 30
-
-/* SUN_TOP_CTRL :: UART_ROUTER_SEL_0 :: port_5_cpu_sel [29:25] */
-#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_5_cpu_sel_MASK 0x3e000000
-#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_5_cpu_sel_SHIFT 25
-#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_5_cpu_sel_DEFAULT 0x00000000
-#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_5_cpu_sel_NO_CPU 0
-#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_5_cpu_sel_AUDIO_FP0 1
-#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_5_cpu_sel_HVD0_OL 2
-#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_5_cpu_sel_HVD0_IL 3
-#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_5_cpu_sel_HVD0_ILP2 4
-#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_5_cpu_sel_SID 5
-#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_5_cpu_sel_VICE20_ARC0 6
-#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_5_cpu_sel_VICE20_ARC1 7
-#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_5_cpu_sel_AVS_TOP 8
-#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_5_cpu_sel_LEAP 9
-#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_5_cpu_sel_RF4CE_TOP 10
-#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_5_cpu_sel_SCPU 11
-
-/* SUN_TOP_CTRL :: UART_ROUTER_SEL_0 :: port_4_cpu_sel [24:20] */
-#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_4_cpu_sel_MASK 0x01f00000
-#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_4_cpu_sel_SHIFT 20
-#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_4_cpu_sel_DEFAULT 0x00000000
-#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_4_cpu_sel_NO_CPU 0
-#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_4_cpu_sel_AUDIO_FP0 1
-#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_4_cpu_sel_HVD0_OL 2
-#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_4_cpu_sel_HVD0_IL 3
-#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_4_cpu_sel_HVD0_ILP2 4
-#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_4_cpu_sel_SID 5
-#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_4_cpu_sel_VICE20_ARC0 6
-#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_4_cpu_sel_VICE20_ARC1 7
-#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_4_cpu_sel_AVS_TOP 8
-#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_4_cpu_sel_LEAP 9
-#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_4_cpu_sel_RF4CE_TOP 10
-#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_4_cpu_sel_SCPU 11
-
-/* SUN_TOP_CTRL :: UART_ROUTER_SEL_0 :: port_3_cpu_sel [19:15] */
-#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_3_cpu_sel_MASK 0x000f8000
-#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_3_cpu_sel_SHIFT 15
-#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_3_cpu_sel_DEFAULT 0x00000000
-#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_3_cpu_sel_NO_CPU 0
-#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_3_cpu_sel_AUDIO_FP0 1
-#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_3_cpu_sel_HVD0_OL 2
-#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_3_cpu_sel_HVD0_IL 3
-#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_3_cpu_sel_HVD0_ILP2 4
-#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_3_cpu_sel_SID 5
-#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_3_cpu_sel_VICE20_ARC0 6
-#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_3_cpu_sel_VICE20_ARC1 7
-#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_3_cpu_sel_AVS_TOP 8
-#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_3_cpu_sel_LEAP 9
-#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_3_cpu_sel_RF4CE_TOP 10
-#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_3_cpu_sel_SCPU 11
-
-/* SUN_TOP_CTRL :: UART_ROUTER_SEL_0 :: port_2_cpu_sel [14:10] */
-#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_2_cpu_sel_MASK 0x00007c00
-#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_2_cpu_sel_SHIFT 10
-#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_2_cpu_sel_DEFAULT 0x00000000
-#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_2_cpu_sel_NO_CPU 0
-#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_2_cpu_sel_AUDIO_FP0 1
-#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_2_cpu_sel_HVD0_OL 2
-#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_2_cpu_sel_HVD0_IL 3
-#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_2_cpu_sel_HVD0_ILP2 4
-#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_2_cpu_sel_SID 5
-#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_2_cpu_sel_VICE20_ARC0 6
-#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_2_cpu_sel_VICE20_ARC1 7
-#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_2_cpu_sel_AVS_TOP 8
-#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_2_cpu_sel_LEAP 9
-#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_2_cpu_sel_RF4CE_TOP 10
-#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_2_cpu_sel_SCPU 11
-
-/* SUN_TOP_CTRL :: UART_ROUTER_SEL_0 :: port_1_cpu_sel [09:05] */
-#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_1_cpu_sel_MASK 0x000003e0
-#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_1_cpu_sel_SHIFT 5
-#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_1_cpu_sel_DEFAULT 0x00000000
-#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_1_cpu_sel_NO_CPU 0
-#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_1_cpu_sel_AUDIO_FP0 1
-#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_1_cpu_sel_HVD0_OL 2
-#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_1_cpu_sel_HVD0_IL 3
-#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_1_cpu_sel_HVD0_ILP2 4
-#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_1_cpu_sel_SID 5
-#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_1_cpu_sel_VICE20_ARC0 6
-#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_1_cpu_sel_VICE20_ARC1 7
-#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_1_cpu_sel_AVS_TOP 8
-#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_1_cpu_sel_LEAP 9
-#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_1_cpu_sel_RF4CE_TOP 10
-#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_1_cpu_sel_SCPU 11
-
-/* SUN_TOP_CTRL :: UART_ROUTER_SEL_0 :: port_0_cpu_sel [04:00] */
-#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_0_cpu_sel_MASK 0x0000001f
-#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_0_cpu_sel_SHIFT 0
-#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_0_cpu_sel_DEFAULT 0x00000000
-#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_0_cpu_sel_NO_CPU 0
-#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_0_cpu_sel_AUDIO_FP0 1
-#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_0_cpu_sel_HVD0_OL 2
-#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_0_cpu_sel_HVD0_IL 3
-#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_0_cpu_sel_HVD0_ILP2 4
-#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_0_cpu_sel_SID 5
-#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_0_cpu_sel_VICE20_ARC0 6
-#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_0_cpu_sel_VICE20_ARC1 7
-#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_0_cpu_sel_AVS_TOP 8
-#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_0_cpu_sel_LEAP 9
-#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_0_cpu_sel_RF4CE_TOP 10
-#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_0_cpu_sel_SCPU 11
-
-/***************************************************************************
- *UART_ROUTER_SEL_1 - UART Router select 1
- ***************************************************************************/
-/* SUN_TOP_CTRL :: UART_ROUTER_SEL_1 :: reserved0 [31:30] */
-#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_reserved0_MASK 0xc0000000
-#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_reserved0_SHIFT 30
-
-/* SUN_TOP_CTRL :: UART_ROUTER_SEL_1 :: port_11_cpu_sel [29:25] */
-#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_11_cpu_sel_MASK 0x3e000000
-#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_11_cpu_sel_SHIFT 25
-#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_11_cpu_sel_DEFAULT 0x00000000
-#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_11_cpu_sel_NO_CPU 0
-#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_11_cpu_sel_AUDIO_FP0 1
-#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_11_cpu_sel_HVD0_OL 2
-#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_11_cpu_sel_HVD0_IL 3
-#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_11_cpu_sel_HVD0_ILP2 4
-#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_11_cpu_sel_SID 5
-#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_11_cpu_sel_VICE20_ARC0 6
-#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_11_cpu_sel_VICE20_ARC1 7
-#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_11_cpu_sel_AVS_TOP 8
-#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_11_cpu_sel_LEAP 9
-#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_11_cpu_sel_RF4CE_TOP 10
-#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_11_cpu_sel_SCPU 11
-
-/* SUN_TOP_CTRL :: UART_ROUTER_SEL_1 :: port_10_cpu_sel [24:20] */
-#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_10_cpu_sel_MASK 0x01f00000
-#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_10_cpu_sel_SHIFT 20
-#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_10_cpu_sel_DEFAULT 0x00000000
-#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_10_cpu_sel_NO_CPU 0
-#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_10_cpu_sel_AUDIO_FP0 1
-#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_10_cpu_sel_HVD0_OL 2
-#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_10_cpu_sel_HVD0_IL 3
-#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_10_cpu_sel_HVD0_ILP2 4
-#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_10_cpu_sel_SID 5
-#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_10_cpu_sel_VICE20_ARC0 6
-#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_10_cpu_sel_VICE20_ARC1 7
-#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_10_cpu_sel_AVS_TOP 8
-#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_10_cpu_sel_LEAP 9
-#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_10_cpu_sel_RF4CE_TOP 10
-#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_10_cpu_sel_SCPU 11
-
-/* SUN_TOP_CTRL :: UART_ROUTER_SEL_1 :: port_9_cpu_sel [19:15] */
-#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_9_cpu_sel_MASK 0x000f8000
-#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_9_cpu_sel_SHIFT 15
-#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_9_cpu_sel_DEFAULT 0x00000000
-#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_9_cpu_sel_NO_CPU 0
-#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_9_cpu_sel_AUDIO_FP0 1
-#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_9_cpu_sel_HVD0_OL 2
-#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_9_cpu_sel_HVD0_IL 3
-#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_9_cpu_sel_HVD0_ILP2 4
-#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_9_cpu_sel_SID 5
-#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_9_cpu_sel_VICE20_ARC0 6
-#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_9_cpu_sel_VICE20_ARC1 7
-#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_9_cpu_sel_AVS_TOP 8
-#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_9_cpu_sel_LEAP 9
-#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_9_cpu_sel_RF4CE_TOP 10
-#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_9_cpu_sel_SCPU 11
-
-/* SUN_TOP_CTRL :: UART_ROUTER_SEL_1 :: port_8_cpu_sel [14:10] */
-#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_8_cpu_sel_MASK 0x00007c00
-#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_8_cpu_sel_SHIFT 10
-#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_8_cpu_sel_DEFAULT 0x00000000
-#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_8_cpu_sel_NO_CPU 0
-#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_8_cpu_sel_AUDIO_FP0 1
-#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_8_cpu_sel_HVD0_OL 2
-#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_8_cpu_sel_HVD0_IL 3
-#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_8_cpu_sel_HVD0_ILP2 4
-#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_8_cpu_sel_SID 5
-#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_8_cpu_sel_VICE20_ARC0 6
-#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_8_cpu_sel_VICE20_ARC1 7
-#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_8_cpu_sel_AVS_TOP 8
-#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_8_cpu_sel_LEAP 9
-#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_8_cpu_sel_RF4CE_TOP 10
-#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_8_cpu_sel_SCPU 11
-
-/* SUN_TOP_CTRL :: UART_ROUTER_SEL_1 :: port_7_cpu_sel [09:05] */
-#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_7_cpu_sel_MASK 0x000003e0
-#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_7_cpu_sel_SHIFT 5
-#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_7_cpu_sel_DEFAULT 0x00000000
-#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_7_cpu_sel_NO_CPU 0
-#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_7_cpu_sel_AUDIO_FP0 1
-#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_7_cpu_sel_HVD0_OL 2
-#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_7_cpu_sel_HVD0_IL 3
-#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_7_cpu_sel_HVD0_ILP2 4
-#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_7_cpu_sel_SID 5
-#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_7_cpu_sel_VICE20_ARC0 6
-#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_7_cpu_sel_VICE20_ARC1 7
-#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_7_cpu_sel_AVS_TOP 8
-#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_7_cpu_sel_LEAP 9
-#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_7_cpu_sel_RF4CE_TOP 10
-#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_7_cpu_sel_SCPU 11
-
-/* SUN_TOP_CTRL :: UART_ROUTER_SEL_1 :: port_6_cpu_sel [04:00] */
-#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_6_cpu_sel_MASK 0x0000001f
-#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_6_cpu_sel_SHIFT 0
-#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_6_cpu_sel_DEFAULT 0x00000000
-#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_6_cpu_sel_NO_CPU 0
-#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_6_cpu_sel_AUDIO_FP0 1
-#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_6_cpu_sel_HVD0_OL 2
-#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_6_cpu_sel_HVD0_IL 3
-#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_6_cpu_sel_HVD0_ILP2 4
-#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_6_cpu_sel_SID 5
-#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_6_cpu_sel_VICE20_ARC0 6
-#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_6_cpu_sel_VICE20_ARC1 7
-#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_6_cpu_sel_AVS_TOP 8
-#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_6_cpu_sel_LEAP 9
-#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_6_cpu_sel_RF4CE_TOP 10
-#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_6_cpu_sel_SCPU 11
-
-/***************************************************************************
- *SSP_CONFIG - Serial Slave Port configuration register
- ***************************************************************************/
-/* SUN_TOP_CTRL :: SSP_CONFIG :: reserved0 [31:11] */
-#define BCHP_SUN_TOP_CTRL_SSP_CONFIG_reserved0_MASK 0xfffff800
-#define BCHP_SUN_TOP_CTRL_SSP_CONFIG_reserved0_SHIFT 11
-
-/* SUN_TOP_CTRL :: SSP_CONFIG :: serial_adr_cfg [10:07] */
-#define BCHP_SUN_TOP_CTRL_SSP_CONFIG_serial_adr_cfg_MASK 0x00000780
-#define BCHP_SUN_TOP_CTRL_SSP_CONFIG_serial_adr_cfg_SHIFT 7
-#define BCHP_SUN_TOP_CTRL_SSP_CONFIG_serial_adr_cfg_DEFAULT 0x00000004
-
-/* SUN_TOP_CTRL :: SSP_CONFIG :: probe_mux_sel [06:03] */
-#define BCHP_SUN_TOP_CTRL_SSP_CONFIG_probe_mux_sel_MASK 0x00000078
-#define BCHP_SUN_TOP_CTRL_SSP_CONFIG_probe_mux_sel_SHIFT 3
-#define BCHP_SUN_TOP_CTRL_SSP_CONFIG_probe_mux_sel_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: SSP_CONFIG :: dly_disable [02:02] */
-#define BCHP_SUN_TOP_CTRL_SSP_CONFIG_dly_disable_MASK 0x00000004
-#define BCHP_SUN_TOP_CTRL_SSP_CONFIG_dly_disable_SHIFT 2
-#define BCHP_SUN_TOP_CTRL_SSP_CONFIG_dly_disable_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: SSP_CONFIG :: spi_mode [01:01] */
-#define BCHP_SUN_TOP_CTRL_SSP_CONFIG_spi_mode_MASK 0x00000002
-#define BCHP_SUN_TOP_CTRL_SSP_CONFIG_spi_mode_SHIFT 1
-
-/* SUN_TOP_CTRL :: SSP_CONFIG :: ssp_module_enable [00:00] */
-#define BCHP_SUN_TOP_CTRL_SSP_CONFIG_ssp_module_enable_MASK 0x00000001
-#define BCHP_SUN_TOP_CTRL_SSP_CONFIG_ssp_module_enable_SHIFT 0
-#define BCHP_SUN_TOP_CTRL_SSP_CONFIG_ssp_module_enable_DEFAULT 0x00000001
-
-/***************************************************************************
- *SERS_REV - SERS Revision Register
- ***************************************************************************/
-/* SUN_TOP_CTRL :: SERS_REV :: reserved0 [31:16] */
-#define BCHP_SUN_TOP_CTRL_SERS_REV_reserved0_MASK 0xffff0000
-#define BCHP_SUN_TOP_CTRL_SERS_REV_reserved0_SHIFT 16
-
-/* SUN_TOP_CTRL :: SERS_REV :: reserved_for_eco1 [15:08] */
-#define BCHP_SUN_TOP_CTRL_SERS_REV_reserved_for_eco1_MASK 0x0000ff00
-#define BCHP_SUN_TOP_CTRL_SERS_REV_reserved_for_eco1_SHIFT 8
-#define BCHP_SUN_TOP_CTRL_SERS_REV_reserved_for_eco1_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: SERS_REV :: BLOCK_SERS_REVISION [07:00] */
-#define BCHP_SUN_TOP_CTRL_SERS_REV_BLOCK_SERS_REVISION_MASK 0x000000ff
-#define BCHP_SUN_TOP_CTRL_SERS_REV_BLOCK_SERS_REVISION_SHIFT 0
-#define BCHP_SUN_TOP_CTRL_SERS_REV_BLOCK_SERS_REVISION_DEFAULT 0x00000000
-
-/***************************************************************************
- *SERS_CFG - SERS Configuration Register
- ***************************************************************************/
-/* SUN_TOP_CTRL :: SERS_CFG :: reserved_for_eco0 [31:29] */
-#define BCHP_SUN_TOP_CTRL_SERS_CFG_reserved_for_eco0_MASK 0xe0000000
-#define BCHP_SUN_TOP_CTRL_SERS_CFG_reserved_for_eco0_SHIFT 29
-#define BCHP_SUN_TOP_CTRL_SERS_CFG_reserved_for_eco0_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: SERS_CFG :: CMD_MODE [28:28] */
-#define BCHP_SUN_TOP_CTRL_SERS_CFG_CMD_MODE_MASK 0x10000000
-#define BCHP_SUN_TOP_CTRL_SERS_CFG_CMD_MODE_SHIFT 28
-#define BCHP_SUN_TOP_CTRL_SERS_CFG_CMD_MODE_DEFAULT 0x00000001
-#define BCHP_SUN_TOP_CTRL_SERS_CFG_CMD_MODE_mapped_buffer_mode 0
-#define BCHP_SUN_TOP_CTRL_SERS_CFG_CMD_MODE_cmd_fifo_mode 1
-
-/* SUN_TOP_CTRL :: SERS_CFG :: Little_Endian [27:27] */
-#define BCHP_SUN_TOP_CTRL_SERS_CFG_Little_Endian_MASK 0x08000000
-#define BCHP_SUN_TOP_CTRL_SERS_CFG_Little_Endian_SHIFT 27
-#define BCHP_SUN_TOP_CTRL_SERS_CFG_Little_Endian_DEFAULT 0x00000000
-
-/* union - case mapped_buffer_mode [26:08] */
-/* SUN_TOP_CTRL :: SERS_CFG :: mapped_buffer_mode :: W_PKT_OFFSET_4 [26:22] */
-#define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_W_PKT_OFFSET_4_MASK 0x07c00000
-#define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_W_PKT_OFFSET_4_SHIFT 22
-
-/* SUN_TOP_CTRL :: SERS_CFG :: mapped_buffer_mode :: W_PKT_OFFSET_3 [21:17] */
-#define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_W_PKT_OFFSET_3_MASK 0x003e0000
-#define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_W_PKT_OFFSET_3_SHIFT 17
-
-/* SUN_TOP_CTRL :: SERS_CFG :: mapped_buffer_mode :: W_PKT_OFFSET_2 [16:12] */
-#define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_W_PKT_OFFSET_2_MASK 0x0001f000
-#define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_W_PKT_OFFSET_2_SHIFT 12
-
-/* SUN_TOP_CTRL :: SERS_CFG :: mapped_buffer_mode :: DATA_CHG_IRQ_ONLY_4 [11:11] */
-#define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_DATA_CHG_IRQ_ONLY_4_MASK 0x00000800
-#define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_DATA_CHG_IRQ_ONLY_4_SHIFT 11
-#define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_DATA_CHG_IRQ_ONLY_4_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: SERS_CFG :: mapped_buffer_mode :: DATA_CHG_IRQ_ONLY_3 [10:10] */
-#define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_DATA_CHG_IRQ_ONLY_3_MASK 0x00000400
-#define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_DATA_CHG_IRQ_ONLY_3_SHIFT 10
-#define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_DATA_CHG_IRQ_ONLY_3_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: SERS_CFG :: mapped_buffer_mode :: DATA_CHG_IRQ_ONLY_2 [09:09] */
-#define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_DATA_CHG_IRQ_ONLY_2_MASK 0x00000200
-#define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_DATA_CHG_IRQ_ONLY_2_SHIFT 9
-#define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_DATA_CHG_IRQ_ONLY_2_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: SERS_CFG :: mapped_buffer_mode :: DATA_CHG_IRQ_ONLY_1 [08:08] */
-#define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_DATA_CHG_IRQ_ONLY_1_MASK 0x00000100
-#define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_DATA_CHG_IRQ_ONLY_1_SHIFT 8
-#define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_DATA_CHG_IRQ_ONLY_1_DEFAULT 0x00000000
-
-/* union - case cmd_fifo_mode [26:08] */
-/* SUN_TOP_CTRL :: SERS_CFG :: cmd_fifo_mode :: CMD_W_PTR [26:22] */
-#define BCHP_SUN_TOP_CTRL_SERS_CFG_cmd_fifo_mode_CMD_W_PTR_MASK 0x07c00000
-#define BCHP_SUN_TOP_CTRL_SERS_CFG_cmd_fifo_mode_CMD_W_PTR_SHIFT 22
-#define BCHP_SUN_TOP_CTRL_SERS_CFG_cmd_fifo_mode_CMD_W_PTR_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: SERS_CFG :: cmd_fifo_mode :: CMD_R_PTR [21:17] */
-#define BCHP_SUN_TOP_CTRL_SERS_CFG_cmd_fifo_mode_CMD_R_PTR_MASK 0x003e0000
-#define BCHP_SUN_TOP_CTRL_SERS_CFG_cmd_fifo_mode_CMD_R_PTR_SHIFT 17
-#define BCHP_SUN_TOP_CTRL_SERS_CFG_cmd_fifo_mode_CMD_R_PTR_DEFAULT 0x0000001f
-
-/* SUN_TOP_CTRL :: SERS_CFG :: cmd_fifo_mode :: FIFO_THRESHOLD [16:12] */
-#define BCHP_SUN_TOP_CTRL_SERS_CFG_cmd_fifo_mode_FIFO_THRESHOLD_MASK 0x0001f000
-#define BCHP_SUN_TOP_CTRL_SERS_CFG_cmd_fifo_mode_FIFO_THRESHOLD_SHIFT 12
-#define BCHP_SUN_TOP_CTRL_SERS_CFG_cmd_fifo_mode_FIFO_THRESHOLD_DEFAULT 0x00000010
-
-/* SUN_TOP_CTRL :: SERS_CFG :: cmd_fifo_mode :: NOT_USED [11:10] */
-#define BCHP_SUN_TOP_CTRL_SERS_CFG_cmd_fifo_mode_NOT_USED_MASK 0x00000c00
-#define BCHP_SUN_TOP_CTRL_SERS_CFG_cmd_fifo_mode_NOT_USED_SHIFT 10
-#define BCHP_SUN_TOP_CTRL_SERS_CFG_cmd_fifo_mode_NOT_USED_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: SERS_CFG :: cmd_fifo_mode :: CMD_FIFO_OV [09:09] */
-#define BCHP_SUN_TOP_CTRL_SERS_CFG_cmd_fifo_mode_CMD_FIFO_OV_MASK 0x00000200
-#define BCHP_SUN_TOP_CTRL_SERS_CFG_cmd_fifo_mode_CMD_FIFO_OV_SHIFT 9
-#define BCHP_SUN_TOP_CTRL_SERS_CFG_cmd_fifo_mode_CMD_FIFO_OV_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: SERS_CFG :: cmd_fifo_mode :: DROP_CMDS [08:08] */
-#define BCHP_SUN_TOP_CTRL_SERS_CFG_cmd_fifo_mode_DROP_CMDS_MASK 0x00000100
-#define BCHP_SUN_TOP_CTRL_SERS_CFG_cmd_fifo_mode_DROP_CMDS_SHIFT 8
-#define BCHP_SUN_TOP_CTRL_SERS_CFG_cmd_fifo_mode_DROP_CMDS_DEFAULT 0x00000001
-
-/* SUN_TOP_CTRL :: SERS_CFG :: SER_ADR [07:01] */
-#define BCHP_SUN_TOP_CTRL_SERS_CFG_SER_ADR_MASK 0x000000fe
-#define BCHP_SUN_TOP_CTRL_SERS_CFG_SER_ADR_SHIFT 1
-#define BCHP_SUN_TOP_CTRL_SERS_CFG_SER_ADR_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: SERS_CFG :: SOFT_SER_ADR [00:00] */
-#define BCHP_SUN_TOP_CTRL_SERS_CFG_SOFT_SER_ADR_MASK 0x00000001
-#define BCHP_SUN_TOP_CTRL_SERS_CFG_SOFT_SER_ADR_SHIFT 0
-#define BCHP_SUN_TOP_CTRL_SERS_CFG_SOFT_SER_ADR_DEFAULT 0x00000000
-
-/***************************************************************************
- *SERS_CMD_BUF_%i - Host Serial Write Command Buffer
- ***************************************************************************/
-#define BCHP_SUN_TOP_CTRL_SERS_CMD_BUF_i_ARRAY_BASE 0x00404428
-#define BCHP_SUN_TOP_CTRL_SERS_CMD_BUF_i_ARRAY_START 0
-#define BCHP_SUN_TOP_CTRL_SERS_CMD_BUF_i_ARRAY_END 7
-#define BCHP_SUN_TOP_CTRL_SERS_CMD_BUF_i_ARRAY_ELEMENT_SIZE 32
-
-/***************************************************************************
- *SERS_CMD_BUF_%i - Host Serial Write Command Buffer
- ***************************************************************************/
-/* SUN_TOP_CTRL :: SERS_CMD_BUF_i :: SERS_CMD_BUF [31:00] */
-#define BCHP_SUN_TOP_CTRL_SERS_CMD_BUF_i_SERS_CMD_BUF_MASK 0xffffffff
-#define BCHP_SUN_TOP_CTRL_SERS_CMD_BUF_i_SERS_CMD_BUF_SHIFT 0
-
-
-/***************************************************************************
- *SERS_STAT_BUF_%i - Host Serial Read Status Buffer
- ***************************************************************************/
-#define BCHP_SUN_TOP_CTRL_SERS_STAT_BUF_i_ARRAY_BASE 0x00404448
-#define BCHP_SUN_TOP_CTRL_SERS_STAT_BUF_i_ARRAY_START 0
-#define BCHP_SUN_TOP_CTRL_SERS_STAT_BUF_i_ARRAY_END 1
-#define BCHP_SUN_TOP_CTRL_SERS_STAT_BUF_i_ARRAY_ELEMENT_SIZE 32
-
-/***************************************************************************
- *SERS_STAT_BUF_%i - Host Serial Read Status Buffer
- ***************************************************************************/
-/* SUN_TOP_CTRL :: SERS_STAT_BUF_i :: SERS_STAT_BUF [31:00] */
-#define BCHP_SUN_TOP_CTRL_SERS_STAT_BUF_i_SERS_STAT_BUF_MASK 0xffffffff
-#define BCHP_SUN_TOP_CTRL_SERS_STAT_BUF_i_SERS_STAT_BUF_SHIFT 0
-
-
-/***************************************************************************
- *RO_TEST_BLOCK_SEL - Block select for RO testmode
- ***************************************************************************/
-/* SUN_TOP_CTRL :: RO_TEST_BLOCK_SEL :: reserved0 [31:18] */
-#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_reserved0_MASK 0xfffc0000
-#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_reserved0_SHIFT 18
-
-/* SUN_TOP_CTRL :: RO_TEST_BLOCK_SEL :: ro_test_sub_block_select [17:14] */
-#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_sub_block_select_MASK 0x0003c000
-#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_sub_block_select_SHIFT 14
-#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_sub_block_select_DEFAULT 0x00000000
-#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_sub_block_select_STANDARD_VT_CMOS 0
-#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_sub_block_select_SUPER_HVT_CMOS 1
-#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_sub_block_select_SUPER_LVT_CMOS 2
-#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_sub_block_select_STANDARD_VT_NMOS 3
-#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_sub_block_select_SUPER_HVT_NMOS 4
-#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_sub_block_select_SUPER_LVT_NMOS 5
-#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_sub_block_select_STANDARD_VT_PMOS 6
-#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_sub_block_select_SUPER_HVT_PMOS 7
-#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_sub_block_select_SUPER_LVT_PMOS 8
-#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_sub_block_select_IO_CMOS 9
-#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_sub_block_select_IO_NMOS 10
-#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_sub_block_select_IO_PMOS 11
-
-/* SUN_TOP_CTRL :: RO_TEST_BLOCK_SEL :: ro_test_sub_block_en [13:02] */
-#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_sub_block_en_MASK 0x00003ffc
-#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_sub_block_en_SHIFT 2
-#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_sub_block_en_DEFAULT 0x00000000
-#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_sub_block_en_DISABLE_RO 0
-#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_sub_block_en_STANDARD_VT_CMOS_ONE_HOT 1
-#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_sub_block_en_SUPER_HVT_CMOS_ONE_HOT 2
-#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_sub_block_en_SUPER_LVT_CMOS_ONE_HOT 4
-#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_sub_block_en_STANDARD_VT_NMOS_ONE_HOT 8
-#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_sub_block_en_SUPER_HVT_NMOS_ONE_HOT 16
-#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_sub_block_en_SUPER_LVT_NMOS_ONE_HOT 32
-#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_sub_block_en_STANDARD_VT_PMOS_ONE_HOT 64
-#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_sub_block_en_SUPER_HVT_PMOS_ONE_HOT 128
-#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_sub_block_en_SUPER_LVT_PMOS_ONE_HOT 256
-#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_sub_block_en_IO_CMOS_ONE_HOT 512
-#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_sub_block_en_IO_NMOS_ONE_HOT 1024
-#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_sub_block_en_IO_PMOS_ONE_HOT 2048
-
-/* SUN_TOP_CTRL :: RO_TEST_BLOCK_SEL :: ro_test_block_select [01:00] */
-#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_block_select_MASK 0x00000003
-#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_block_select_SHIFT 0
-#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_block_select_DEFAULT 0x00000000
-#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_block_select_DO_NOT_USE_RO_TEST_ID 0
-#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_block_select_PROD_OSC0_RO_TEST_ID 1
-#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_block_select_PROD_OSC1_RO_TEST_ID 2
-#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_block_select_UNUSED_3_RO_TEST_ID 3
-
-/***************************************************************************
- *TEST_CONFIGURATION - Test configuration
- ***************************************************************************/
-/* SUN_TOP_CTRL :: TEST_CONFIGURATION :: reserved0 [31:04] */
-#define BCHP_SUN_TOP_CTRL_TEST_CONFIGURATION_reserved0_MASK 0xfffffff0
-#define BCHP_SUN_TOP_CTRL_TEST_CONFIGURATION_reserved0_SHIFT 4
-
-/* SUN_TOP_CTRL :: TEST_CONFIGURATION :: test_configuration [03:00] */
-#define BCHP_SUN_TOP_CTRL_TEST_CONFIGURATION_test_configuration_MASK 0x0000000f
-#define BCHP_SUN_TOP_CTRL_TEST_CONFIGURATION_test_configuration_SHIFT 0
-#define BCHP_SUN_TOP_CTRL_TEST_CONFIGURATION_test_configuration_DEFAULT 0x00000000
-
-/***************************************************************************
- *OTP_OPTION_TEST_2 - OTP option test register
- ***************************************************************************/
-/* SUN_TOP_CTRL :: OTP_OPTION_TEST_2 :: otp_option_spare_23 [31:31] */
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_2_otp_option_spare_23_MASK 0x80000000
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_2_otp_option_spare_23_SHIFT 31
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_2_otp_option_spare_23_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: OTP_OPTION_TEST_2 :: otp_option_spare_22 [30:30] */
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_2_otp_option_spare_22_MASK 0x40000000
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_2_otp_option_spare_22_SHIFT 30
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_2_otp_option_spare_22_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: OTP_OPTION_TEST_2 :: otp_option_spare_21 [29:29] */
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_2_otp_option_spare_21_MASK 0x20000000
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_2_otp_option_spare_21_SHIFT 29
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_2_otp_option_spare_21_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: OTP_OPTION_TEST_2 :: otp_option_spare_20 [28:28] */
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_2_otp_option_spare_20_MASK 0x10000000
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_2_otp_option_spare_20_SHIFT 28
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_2_otp_option_spare_20_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: OTP_OPTION_TEST_2 :: otp_option_spare_19 [27:27] */
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_2_otp_option_spare_19_MASK 0x08000000
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_2_otp_option_spare_19_SHIFT 27
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_2_otp_option_spare_19_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: OTP_OPTION_TEST_2 :: otp_option_spare_18 [26:26] */
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_2_otp_option_spare_18_MASK 0x04000000
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_2_otp_option_spare_18_SHIFT 26
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_2_otp_option_spare_18_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: OTP_OPTION_TEST_2 :: otp_option_spare_17 [25:25] */
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_2_otp_option_spare_17_MASK 0x02000000
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_2_otp_option_spare_17_SHIFT 25
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_2_otp_option_spare_17_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: OTP_OPTION_TEST_2 :: otp_option_spare_16 [24:24] */
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_2_otp_option_spare_16_MASK 0x01000000
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_2_otp_option_spare_16_SHIFT 24
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_2_otp_option_spare_16_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: OTP_OPTION_TEST_2 :: otp_option_spare_15 [23:23] */
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_2_otp_option_spare_15_MASK 0x00800000
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_2_otp_option_spare_15_SHIFT 23
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_2_otp_option_spare_15_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: OTP_OPTION_TEST_2 :: otp_option_spare_14 [22:22] */
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_2_otp_option_spare_14_MASK 0x00400000
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_2_otp_option_spare_14_SHIFT 22
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_2_otp_option_spare_14_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: OTP_OPTION_TEST_2 :: otp_option_spare_13 [21:21] */
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_2_otp_option_spare_13_MASK 0x00200000
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_2_otp_option_spare_13_SHIFT 21
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_2_otp_option_spare_13_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: OTP_OPTION_TEST_2 :: otp_option_spare_12 [20:20] */
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_2_otp_option_spare_12_MASK 0x00100000
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_2_otp_option_spare_12_SHIFT 20
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_2_otp_option_spare_12_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: OTP_OPTION_TEST_2 :: otp_option_spare_11 [19:19] */
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_2_otp_option_spare_11_MASK 0x00080000
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_2_otp_option_spare_11_SHIFT 19
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_2_otp_option_spare_11_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: OTP_OPTION_TEST_2 :: otp_option_spare_10 [18:18] */
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_2_otp_option_spare_10_MASK 0x00040000
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_2_otp_option_spare_10_SHIFT 18
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_2_otp_option_spare_10_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: OTP_OPTION_TEST_2 :: otp_option_spare_9 [17:17] */
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_2_otp_option_spare_9_MASK 0x00020000
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_2_otp_option_spare_9_SHIFT 17
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_2_otp_option_spare_9_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: OTP_OPTION_TEST_2 :: otp_option_spare_8 [16:16] */
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_2_otp_option_spare_8_MASK 0x00010000
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_2_otp_option_spare_8_SHIFT 16
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_2_otp_option_spare_8_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: OTP_OPTION_TEST_2 :: otp_option_spare_7 [15:15] */
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_2_otp_option_spare_7_MASK 0x00008000
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_2_otp_option_spare_7_SHIFT 15
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_2_otp_option_spare_7_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: OTP_OPTION_TEST_2 :: otp_option_spare_6 [14:14] */
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_2_otp_option_spare_6_MASK 0x00004000
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_2_otp_option_spare_6_SHIFT 14
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_2_otp_option_spare_6_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: OTP_OPTION_TEST_2 :: otp_option_spare_5 [13:13] */
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_2_otp_option_spare_5_MASK 0x00002000
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_2_otp_option_spare_5_SHIFT 13
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_2_otp_option_spare_5_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: OTP_OPTION_TEST_2 :: otp_option_spare_4 [12:12] */
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_2_otp_option_spare_4_MASK 0x00001000
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_2_otp_option_spare_4_SHIFT 12
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_2_otp_option_spare_4_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: OTP_OPTION_TEST_2 :: otp_option_spare_3 [11:11] */
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_2_otp_option_spare_3_MASK 0x00000800
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_2_otp_option_spare_3_SHIFT 11
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_2_otp_option_spare_3_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: OTP_OPTION_TEST_2 :: otp_option_spare_2 [10:10] */
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_2_otp_option_spare_2_MASK 0x00000400
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_2_otp_option_spare_2_SHIFT 10
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_2_otp_option_spare_2_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: OTP_OPTION_TEST_2 :: otp_option_spare_1 [09:09] */
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_2_otp_option_spare_1_MASK 0x00000200
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_2_otp_option_spare_1_SHIFT 9
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_2_otp_option_spare_1_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: OTP_OPTION_TEST_2 :: otp_option_spare_0 [08:08] */
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_2_otp_option_spare_0_MASK 0x00000100
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_2_otp_option_spare_0_SHIFT 8
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_2_otp_option_spare_0_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: OTP_OPTION_TEST_2 :: otp_option_sds_channel_disable [07:00] */
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_2_otp_option_sds_channel_disable_MASK 0x000000ff
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_2_otp_option_sds_channel_disable_SHIFT 0
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_2_otp_option_sds_channel_disable_DEFAULT 0x00000000
-
-/***************************************************************************
- *OTP_OPTION_STATUS_2 - OTP option status register
- ***************************************************************************/
-/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_2 :: otp_option_spare_23 [31:31] */
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_2_otp_option_spare_23_MASK 0x80000000
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_2_otp_option_spare_23_SHIFT 31
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_2_otp_option_spare_23_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_2 :: otp_option_spare_22 [30:30] */
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_2_otp_option_spare_22_MASK 0x40000000
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_2_otp_option_spare_22_SHIFT 30
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_2_otp_option_spare_22_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_2 :: otp_option_spare_21 [29:29] */
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_2_otp_option_spare_21_MASK 0x20000000
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_2_otp_option_spare_21_SHIFT 29
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_2_otp_option_spare_21_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_2 :: otp_option_spare_20 [28:28] */
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_2_otp_option_spare_20_MASK 0x10000000
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_2_otp_option_spare_20_SHIFT 28
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_2_otp_option_spare_20_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_2 :: otp_option_spare_19 [27:27] */
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_2_otp_option_spare_19_MASK 0x08000000
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_2_otp_option_spare_19_SHIFT 27
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_2_otp_option_spare_19_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_2 :: otp_option_spare_18 [26:26] */
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_2_otp_option_spare_18_MASK 0x04000000
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_2_otp_option_spare_18_SHIFT 26
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_2_otp_option_spare_18_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_2 :: otp_option_spare_17 [25:25] */
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_2_otp_option_spare_17_MASK 0x02000000
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_2_otp_option_spare_17_SHIFT 25
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_2_otp_option_spare_17_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_2 :: otp_option_spare_16 [24:24] */
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_2_otp_option_spare_16_MASK 0x01000000
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_2_otp_option_spare_16_SHIFT 24
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_2_otp_option_spare_16_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_2 :: otp_option_spare_15 [23:23] */
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_2_otp_option_spare_15_MASK 0x00800000
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_2_otp_option_spare_15_SHIFT 23
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_2_otp_option_spare_15_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_2 :: otp_option_spare_14 [22:22] */
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_2_otp_option_spare_14_MASK 0x00400000
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_2_otp_option_spare_14_SHIFT 22
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_2_otp_option_spare_14_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_2 :: otp_option_spare_13 [21:21] */
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_2_otp_option_spare_13_MASK 0x00200000
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_2_otp_option_spare_13_SHIFT 21
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_2_otp_option_spare_13_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_2 :: otp_option_spare_12 [20:20] */
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_2_otp_option_spare_12_MASK 0x00100000
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_2_otp_option_spare_12_SHIFT 20
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_2_otp_option_spare_12_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_2 :: otp_option_spare_11 [19:19] */
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_2_otp_option_spare_11_MASK 0x00080000
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_2_otp_option_spare_11_SHIFT 19
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_2_otp_option_spare_11_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_2 :: otp_option_spare_10 [18:18] */
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_2_otp_option_spare_10_MASK 0x00040000
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_2_otp_option_spare_10_SHIFT 18
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_2_otp_option_spare_10_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_2 :: otp_option_spare_9 [17:17] */
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_2_otp_option_spare_9_MASK 0x00020000
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_2_otp_option_spare_9_SHIFT 17
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_2_otp_option_spare_9_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_2 :: otp_option_spare_8 [16:16] */
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_2_otp_option_spare_8_MASK 0x00010000
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_2_otp_option_spare_8_SHIFT 16
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_2_otp_option_spare_8_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_2 :: otp_option_spare_7 [15:15] */
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_2_otp_option_spare_7_MASK 0x00008000
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_2_otp_option_spare_7_SHIFT 15
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_2_otp_option_spare_7_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_2 :: otp_option_spare_6 [14:14] */
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_2_otp_option_spare_6_MASK 0x00004000
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_2_otp_option_spare_6_SHIFT 14
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_2_otp_option_spare_6_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_2 :: otp_option_spare_5 [13:13] */
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_2_otp_option_spare_5_MASK 0x00002000
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_2_otp_option_spare_5_SHIFT 13
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_2_otp_option_spare_5_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_2 :: otp_option_spare_4 [12:12] */
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_2_otp_option_spare_4_MASK 0x00001000
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_2_otp_option_spare_4_SHIFT 12
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_2_otp_option_spare_4_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_2 :: otp_option_spare_3 [11:11] */
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_2_otp_option_spare_3_MASK 0x00000800
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_2_otp_option_spare_3_SHIFT 11
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_2_otp_option_spare_3_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_2 :: otp_option_spare_2 [10:10] */
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_2_otp_option_spare_2_MASK 0x00000400
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_2_otp_option_spare_2_SHIFT 10
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_2_otp_option_spare_2_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_2 :: otp_option_spare_1 [09:09] */
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_2_otp_option_spare_1_MASK 0x00000200
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_2_otp_option_spare_1_SHIFT 9
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_2_otp_option_spare_1_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_2 :: otp_option_spare_0 [08:08] */
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_2_otp_option_spare_0_MASK 0x00000100
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_2_otp_option_spare_0_SHIFT 8
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_2_otp_option_spare_0_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_2 :: otp_option_sds_channel_disable [07:00] */
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_2_otp_option_sds_channel_disable_MASK 0x000000ff
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_2_otp_option_sds_channel_disable_SHIFT 0
-
-/***************************************************************************
- *GENERAL_CTRL_6 - General control register 6
- ***************************************************************************/
-/* SUN_TOP_CTRL :: GENERAL_CTRL_6 :: reserved0 [31:01] */
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_6_reserved0_MASK 0xfffffffe
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_6_reserved0_SHIFT 1
-
-/* SUN_TOP_CTRL :: GENERAL_CTRL_6 :: demod_xpt_tb_disable [00:00] */
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_6_demod_xpt_tb_disable_MASK 0x00000001
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_6_demod_xpt_tb_disable_SHIFT 0
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_6_demod_xpt_tb_disable_DEFAULT 0x00000000
-
-/***************************************************************************
- *GENERAL_CTRL_7 - General control register 7
- ***************************************************************************/
-/* SUN_TOP_CTRL :: GENERAL_CTRL_7 :: demod_xpt_chip_signature [31:00] */
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_7_demod_xpt_chip_signature_MASK 0xffffffff
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_7_demod_xpt_chip_signature_SHIFT 0
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_7_demod_xpt_chip_signature_DEFAULT 0x00000000
-
-#endif /* #ifndef BCHP_SUN_TOP_CTRL_H__ */
-
-/* End of File */
diff --git a/include/linux/brcmstb/7366b0/bchp_usb_ctrl.h b/include/linux/brcmstb/7366b0/bchp_usb_ctrl.h
deleted file mode 100644
index 0aebbde..0000000
--- a/include/linux/brcmstb/7366b0/bchp_usb_ctrl.h
+++ /dev/null
@@ -1,1524 +0,0 @@
-/***************************************************************************
- * Copyright (c) 1999-2014, Broadcom Corporation
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
- *
- * Module Description:
- * DO NOT EDIT THIS FILE DIRECTLY
- *
- * This module was generated magically with RDB from a source description
- * file. You must edit the source file for changes to be made to this file.
- *
- *
- * Date: Generated on Wed Sep 3 15:00:03 2014
- * Full Compile MD5 Checksum 10187d4079392bab2546025f43274d34
- * (minus title and desc)
- * MD5 Checksum c1587c5e16f21f52e852e7c7a65c7811
- *
- * Compiled with: RDB Utility combo_header.pl
- * RDB Parser 3.0
- * unknown unknown
- * Perl Interpreter 5.008005
- * Operating System linux
- *
- * Revision History:
- *
- * $brcm_Log: $
- *
- ***************************************************************************/
-
-#ifndef BCHP_USB_CTRL_H__
-#define BCHP_USB_CTRL_H__
-
-/***************************************************************************
- *USB_CTRL - USB Control Registers
- ***************************************************************************/
-#define BCHP_USB_CTRL_SETUP 0x00480200 /* Setup Register */
-#define BCHP_USB_CTRL_PLL_CTL 0x00480204 /* PLL Control Register */
-#define BCHP_USB_CTRL_FLADJ_VALUE 0x00480208 /* Frame Adjust Value */
-#define BCHP_USB_CTRL_EBRIDGE 0x0048020c /* Control Register for EHCI Bridge */
-#define BCHP_USB_CTRL_OBRIDGE 0x00480210 /* Control Register for OHCI Bridge */
-#define BCHP_USB_CTRL_MDIO 0x00480214 /* MDIO Interface Programming Register */
-#define BCHP_USB_CTRL_MDIO2 0x00480218 /* MDIO Interface Read Register */
-#define BCHP_USB_CTRL_TEST_PORT_CTL 0x0048021c /* Test Port Control Register */
-#define BCHP_USB_CTRL_USB_SIMCTL 0x00480220 /* Simulation Register */
-#define BCHP_USB_CTRL_USB_TESTCTL 0x00480224 /* Throutput Test Control */
-#define BCHP_USB_CTRL_USB_TESTMON 0x00480228 /* Throughput Test Monitor */
-#define BCHP_USB_CTRL_UTMI_CTL_1 0x0048022c /* UTMI Control Register */
-#define BCHP_USB_CTRL_UTMI_CTL_2 0x00480230 /* UTMI Control 2 Register */
-#define BCHP_USB_CTRL_USB_PM 0x00480234 /* Power Management Register */
-#define BCHP_USB_CTRL_USB_PM_STATUS 0x00480238 /* usb20 Power Management Status Register */
-#define BCHP_USB_CTRL_OHCI_ADDR_EXT 0x0048023c /* OHCI ADDRESS Extension */
-#define BCHP_USB_CTRL_PLL_LDO_CTL 0x00480240 /* 28NM USBPHY LDO Control */
-#define BCHP_USB_CTRL_PLL_LDO_PLLBIAS 0x00480244 /* 28NM USBPHY PLLBIAS Control */
-#define BCHP_USB_CTRL_PLL_AFE_BG_CNTL 0x00480248 /* 28NM USBPHY AFE Bandgap Control */
-#define BCHP_USB_CTRL_AFE_USBIO_TST 0x0048024c /* 28NM USBPHY AFE Bandgap Control */
-#define BCHP_USB_CTRL_PLL_NDIV_FRAC 0x00480250 /* PLL Feedback Divider Control Register */
-#define BCHP_USB_CTRL_TP_DIAG 0x00480254 /* diagnostic for tp bus */
-#define BCHP_USB_CTRL_SPARE3 0x00480258 /* Spare1 Register for future use */
-#define BCHP_USB_CTRL_SPARE4 0x0048025c /* Spare1 Register for future use */
-#define BCHP_USB_CTRL_USB30_CTL1 0x00480260 /* USB30 CONTROL Register 1 */
-#define BCHP_USB_CTRL_USB30_CTL2 0x00480264 /* USB30 CONTROL Register 2 */
-#define BCHP_USB_CTRL_USB30_CTL3 0x00480268 /* USB30 CONTROL Register 3 */
-#define BCHP_USB_CTRL_USB30_CTL4 0x0048026c /* USB30 CONTROL Register 4 */
-#define BCHP_USB_CTRL_USB30_PCTL 0x00480270 /* USB30 PORT CONTROL Register */
-#define BCHP_USB_CTRL_USB30_CTL5 0x00480274 /* USB30 CONTROL Register 5 */
-#define BCHP_USB_CTRL_SPARE5 0x00480278 /* Spare1 Register for future use */
-#define BCHP_USB_CTRL_SPARE6 0x0048027c /* Spare2 Register for future use */
-#define BCHP_USB_CTRL_SCB0_BASE_RANGE 0x004802a0 /* SCB0 base start and end address */
-#define BCHP_USB_CTRL_SCB1_BASE_RANGE 0x004802a4 /* SCB1 base start and end address */
-#define BCHP_USB_CTRL_SCB2_BASE_RANGE 0x004802a8 /* SCB2 base start and end address */
-#define BCHP_USB_CTRL_SCB0_EXTN_RANGE 0x004802ac /* SCB0 extn start and end address */
-#define BCHP_USB_CTRL_SCB1_EXTN_RANGE 0x004802b0 /* SCB1 extn start and end address */
-#define BCHP_USB_CTRL_SCB2_EXTN_RANGE 0x004802b4 /* SCB2 extn start and end address */
-#define BCHP_USB_CTRL_USB_REVID 0x004802fc /* USB REVID */
-
-/***************************************************************************
- *SETUP - Setup Register
- ***************************************************************************/
-/* USB_CTRL :: SETUP :: OC3_DISABLE [31:30] */
-#define BCHP_USB_CTRL_SETUP_OC3_DISABLE_MASK 0xc0000000
-#define BCHP_USB_CTRL_SETUP_OC3_DISABLE_SHIFT 30
-#define BCHP_USB_CTRL_SETUP_OC3_DISABLE_DEFAULT 0x00000000
-
-/* USB_CTRL :: SETUP :: OC_DISABLE [29:28] */
-#define BCHP_USB_CTRL_SETUP_OC_DISABLE_MASK 0x30000000
-#define BCHP_USB_CTRL_SETUP_OC_DISABLE_SHIFT 28
-#define BCHP_USB_CTRL_SETUP_OC_DISABLE_DEFAULT 0x00000000
-
-/* USB_CTRL :: SETUP :: usb_pwron_force [27:27] */
-#define BCHP_USB_CTRL_SETUP_usb_pwron_force_MASK 0x08000000
-#define BCHP_USB_CTRL_SETUP_usb_pwron_force_SHIFT 27
-#define BCHP_USB_CTRL_SETUP_usb_pwron_force_DEFAULT 0x00000000
-
-/* USB_CTRL :: SETUP :: usb_pwron_val [26:26] */
-#define BCHP_USB_CTRL_SETUP_usb_pwron_val_MASK 0x04000000
-#define BCHP_USB_CTRL_SETUP_usb_pwron_val_SHIFT 26
-#define BCHP_USB_CTRL_SETUP_usb_pwron_val_DEFAULT 0x00000000
-
-/* USB_CTRL :: SETUP :: SETUP_SPARE [25:20] */
-#define BCHP_USB_CTRL_SETUP_SETUP_SPARE_MASK 0x03f00000
-#define BCHP_USB_CTRL_SETUP_SETUP_SPARE_SHIFT 20
-#define BCHP_USB_CTRL_SETUP_SETUP_SPARE_DEFAULT 0x00000000
-
-/* USB_CTRL :: SETUP :: ohci_susp_lgcy [19:19] */
-#define BCHP_USB_CTRL_SETUP_ohci_susp_lgcy_MASK 0x00080000
-#define BCHP_USB_CTRL_SETUP_ohci_susp_lgcy_SHIFT 19
-#define BCHP_USB_CTRL_SETUP_ohci_susp_lgcy_DEFAULT 0x00000000
-
-/* USB_CTRL :: SETUP :: ss_ulpi_pp2vbus [18:18] */
-#define BCHP_USB_CTRL_SETUP_ss_ulpi_pp2vbus_MASK 0x00040000
-#define BCHP_USB_CTRL_SETUP_ss_ulpi_pp2vbus_SHIFT 18
-#define BCHP_USB_CTRL_SETUP_ss_ulpi_pp2vbus_DEFAULT 0x00000000
-
-/* USB_CTRL :: SETUP :: ss_ehci64bit_en [17:17] */
-#define BCHP_USB_CTRL_SETUP_ss_ehci64bit_en_MASK 0x00020000
-#define BCHP_USB_CTRL_SETUP_ss_ehci64bit_en_SHIFT 17
-#define BCHP_USB_CTRL_SETUP_ss_ehci64bit_en_DEFAULT 0x00000001
-
-/* USB_CTRL :: SETUP :: async_expire_dis [16:16] */
-#define BCHP_USB_CTRL_SETUP_async_expire_dis_MASK 0x00010000
-#define BCHP_USB_CTRL_SETUP_async_expire_dis_SHIFT 16
-#define BCHP_USB_CTRL_SETUP_async_expire_dis_DEFAULT 0x00000000
-
-/* USB_CTRL :: SETUP :: scb2_en [15:15] */
-#define BCHP_USB_CTRL_SETUP_scb2_en_MASK 0x00008000
-#define BCHP_USB_CTRL_SETUP_scb2_en_SHIFT 15
-#define BCHP_USB_CTRL_SETUP_scb2_en_DEFAULT 0x00000000
-
-/* USB_CTRL :: SETUP :: scb1_en [14:14] */
-#define BCHP_USB_CTRL_SETUP_scb1_en_MASK 0x00004000
-#define BCHP_USB_CTRL_SETUP_scb1_en_SHIFT 14
-#define BCHP_USB_CTRL_SETUP_scb1_en_DEFAULT 0x00000001
-
-/* USB_CTRL :: SETUP :: scb0_en [13:13] */
-#define BCHP_USB_CTRL_SETUP_scb0_en_MASK 0x00002000
-#define BCHP_USB_CTRL_SETUP_scb0_en_SHIFT 13
-#define BCHP_USB_CTRL_SETUP_scb0_en_DEFAULT 0x00000001
-
-/* USB_CTRL :: SETUP :: scb_client_swap [12:12] */
-#define BCHP_USB_CTRL_SETUP_scb_client_swap_MASK 0x00001000
-#define BCHP_USB_CTRL_SETUP_scb_client_swap_SHIFT 12
-#define BCHP_USB_CTRL_SETUP_scb_client_swap_DEFAULT 0x00000000
-
-/* USB_CTRL :: SETUP :: setup_spare1 [11:10] */
-#define BCHP_USB_CTRL_SETUP_setup_spare1_MASK 0x00000c00
-#define BCHP_USB_CTRL_SETUP_setup_spare1_SHIFT 10
-#define BCHP_USB_CTRL_SETUP_setup_spare1_DEFAULT 0x00000000
-
-/* USB_CTRL :: SETUP :: soft_shutdown [09:09] */
-#define BCHP_USB_CTRL_SETUP_soft_shutdown_MASK 0x00000200
-#define BCHP_USB_CTRL_SETUP_soft_shutdown_SHIFT 9
-#define BCHP_USB_CTRL_SETUP_soft_shutdown_DEFAULT 0x00000000
-
-/* USB_CTRL :: SETUP :: utmi_bkward_en [08:08] */
-#define BCHP_USB_CTRL_SETUP_utmi_bkward_en_MASK 0x00000100
-#define BCHP_USB_CTRL_SETUP_utmi_bkward_en_SHIFT 8
-#define BCHP_USB_CTRL_SETUP_utmi_bkward_en_DEFAULT 0x00000000
-
-/* USB_CTRL :: SETUP :: utmi_pls_en [07:07] */
-#define BCHP_USB_CTRL_SETUP_utmi_pls_en_MASK 0x00000080
-#define BCHP_USB_CTRL_SETUP_utmi_pls_en_SHIFT 7
-#define BCHP_USB_CTRL_SETUP_utmi_pls_en_DEFAULT 0x00000000
-
-/* USB_CTRL :: SETUP :: soft_reset [06:06] */
-#define BCHP_USB_CTRL_SETUP_soft_reset_MASK 0x00000040
-#define BCHP_USB_CTRL_SETUP_soft_reset_SHIFT 6
-#define BCHP_USB_CTRL_SETUP_soft_reset_DEFAULT 0x00000000
-
-/* USB_CTRL :: SETUP :: IPP [05:05] */
-#define BCHP_USB_CTRL_SETUP_IPP_MASK 0x00000020
-#define BCHP_USB_CTRL_SETUP_IPP_SHIFT 5
-#define BCHP_USB_CTRL_SETUP_IPP_DEFAULT 0x00000000
-
-/* USB_CTRL :: SETUP :: IOC [04:04] */
-#define BCHP_USB_CTRL_SETUP_IOC_MASK 0x00000010
-#define BCHP_USB_CTRL_SETUP_IOC_SHIFT 4
-#define BCHP_USB_CTRL_SETUP_IOC_DEFAULT 0x00000000
-
-/* USB_CTRL :: SETUP :: WABO [03:03] */
-#define BCHP_USB_CTRL_SETUP_WABO_MASK 0x00000008
-#define BCHP_USB_CTRL_SETUP_WABO_SHIFT 3
-#define BCHP_USB_CTRL_SETUP_WABO_DEFAULT 0x00000000
-
-/* USB_CTRL :: SETUP :: FNBO [02:02] */
-#define BCHP_USB_CTRL_SETUP_FNBO_MASK 0x00000004
-#define BCHP_USB_CTRL_SETUP_FNBO_SHIFT 2
-#define BCHP_USB_CTRL_SETUP_FNBO_DEFAULT 0x00000000
-
-/* USB_CTRL :: SETUP :: FNHW [01:01] */
-#define BCHP_USB_CTRL_SETUP_FNHW_MASK 0x00000002
-#define BCHP_USB_CTRL_SETUP_FNHW_SHIFT 1
-#define BCHP_USB_CTRL_SETUP_FNHW_DEFAULT 0x00000000
-
-/* USB_CTRL :: SETUP :: BABO [00:00] */
-#define BCHP_USB_CTRL_SETUP_BABO_MASK 0x00000001
-#define BCHP_USB_CTRL_SETUP_BABO_SHIFT 0
-#define BCHP_USB_CTRL_SETUP_BABO_DEFAULT 0x00000000
-
-/***************************************************************************
- *PLL_CTL - PLL Control Register
- ***************************************************************************/
-/* USB_CTRL :: PLL_CTL :: PLL_IDDQ_PWRDN [31:31] */
-#define BCHP_USB_CTRL_PLL_CTL_PLL_IDDQ_PWRDN_MASK 0x80000000
-#define BCHP_USB_CTRL_PLL_CTL_PLL_IDDQ_PWRDN_SHIFT 31
-#define BCHP_USB_CTRL_PLL_CTL_PLL_IDDQ_PWRDN_DEFAULT 0x00000001
-
-/* USB_CTRL :: PLL_CTL :: PLL_RESETB [30:30] */
-#define BCHP_USB_CTRL_PLL_CTL_PLL_RESETB_MASK 0x40000000
-#define BCHP_USB_CTRL_PLL_CTL_PLL_RESETB_SHIFT 30
-#define BCHP_USB_CTRL_PLL_CTL_PLL_RESETB_DEFAULT 0x00000001
-
-/* USB_CTRL :: PLL_CTL :: PHYPLL_BYP [29:29] */
-#define BCHP_USB_CTRL_PLL_CTL_PHYPLL_BYP_MASK 0x20000000
-#define BCHP_USB_CTRL_PLL_CTL_PHYPLL_BYP_SHIFT 29
-#define BCHP_USB_CTRL_PLL_CTL_PHYPLL_BYP_DEFAULT 0x00000000
-
-/* USB_CTRL :: PLL_CTL :: PLL_PWRDWNB [28:28] */
-#define BCHP_USB_CTRL_PLL_CTL_PLL_PWRDWNB_MASK 0x10000000
-#define BCHP_USB_CTRL_PLL_CTL_PLL_PWRDWNB_SHIFT 28
-#define BCHP_USB_CTRL_PLL_CTL_PLL_PWRDWNB_DEFAULT 0x00000001
-
-/* USB_CTRL :: PLL_CTL :: PLL_SUSPEND_EN [27:27] */
-#define BCHP_USB_CTRL_PLL_CTL_PLL_SUSPEND_EN_MASK 0x08000000
-#define BCHP_USB_CTRL_PLL_CTL_PLL_SUSPEND_EN_SHIFT 27
-#define BCHP_USB_CTRL_PLL_CTL_PLL_SUSPEND_EN_DEFAULT 0x00000000
-
-/* USB_CTRL :: PLL_CTL :: PLL_Ka [26:24] */
-#define BCHP_USB_CTRL_PLL_CTL_PLL_Ka_MASK 0x07000000
-#define BCHP_USB_CTRL_PLL_CTL_PLL_Ka_SHIFT 24
-#define BCHP_USB_CTRL_PLL_CTL_PLL_Ka_DEFAULT 0x00000000
-
-/* USB_CTRL :: PLL_CTL :: PLLCTL_SPARE3 [23:23] */
-#define BCHP_USB_CTRL_PLL_CTL_PLLCTL_SPARE3_MASK 0x00800000
-#define BCHP_USB_CTRL_PLL_CTL_PLLCTL_SPARE3_SHIFT 23
-#define BCHP_USB_CTRL_PLL_CTL_PLLCTL_SPARE3_DEFAULT 0x00000000
-
-/* USB_CTRL :: PLL_CTL :: PLL_Ki [22:20] */
-#define BCHP_USB_CTRL_PLL_CTL_PLL_Ki_MASK 0x00700000
-#define BCHP_USB_CTRL_PLL_CTL_PLL_Ki_SHIFT 20
-#define BCHP_USB_CTRL_PLL_CTL_PLL_Ki_DEFAULT 0x00000004
-
-/* USB_CTRL :: PLL_CTL :: PLL_Kp [19:16] */
-#define BCHP_USB_CTRL_PLL_CTL_PLL_Kp_MASK 0x000f0000
-#define BCHP_USB_CTRL_PLL_CTL_PLL_Kp_SHIFT 16
-#define BCHP_USB_CTRL_PLL_CTL_PLL_Kp_DEFAULT 0x0000000a
-
-/* USB_CTRL :: PLL_CTL :: PLL_pdiv [15:12] */
-#define BCHP_USB_CTRL_PLL_CTL_PLL_pdiv_MASK 0x0000f000
-#define BCHP_USB_CTRL_PLL_CTL_PLL_pdiv_SHIFT 12
-#define BCHP_USB_CTRL_PLL_CTL_PLL_pdiv_DEFAULT 0x00000001
-
-/* USB_CTRL :: PLL_CTL :: PLLCTL_SPARE1 [11:10] */
-#define BCHP_USB_CTRL_PLL_CTL_PLLCTL_SPARE1_MASK 0x00000c00
-#define BCHP_USB_CTRL_PLL_CTL_PLLCTL_SPARE1_SHIFT 10
-#define BCHP_USB_CTRL_PLL_CTL_PLLCTL_SPARE1_DEFAULT 0x00000000
-
-/* USB_CTRL :: PLL_CTL :: PLL_ndiv [09:00] */
-#define BCHP_USB_CTRL_PLL_CTL_PLL_ndiv_MASK 0x000003ff
-#define BCHP_USB_CTRL_PLL_CTL_PLL_ndiv_SHIFT 0
-#define BCHP_USB_CTRL_PLL_CTL_PLL_ndiv_DEFAULT 0x00000020
-
-/***************************************************************************
- *FLADJ_VALUE - Frame Adjust Value
- ***************************************************************************/
-/* USB_CTRL :: FLADJ_VALUE :: FLADJ_VAL [31:00] */
-#define BCHP_USB_CTRL_FLADJ_VALUE_FLADJ_VAL_MASK 0xffffffff
-#define BCHP_USB_CTRL_FLADJ_VALUE_FLADJ_VAL_SHIFT 0
-#define BCHP_USB_CTRL_FLADJ_VALUE_FLADJ_VAL_DEFAULT 0x000c0020
-
-/***************************************************************************
- *EBRIDGE - Control Register for EHCI Bridge
- ***************************************************************************/
-/* USB_CTRL :: EBRIDGE :: EBR_SOFT_RESET [31:31] */
-#define BCHP_USB_CTRL_EBRIDGE_EBR_SOFT_RESET_MASK 0x80000000
-#define BCHP_USB_CTRL_EBRIDGE_EBR_SOFT_RESET_SHIFT 31
-#define BCHP_USB_CTRL_EBRIDGE_EBR_SOFT_RESET_DEFAULT 0x00000000
-
-/* USB_CTRL :: EBRIDGE :: ebrff_reset [30:30] */
-#define BCHP_USB_CTRL_EBRIDGE_ebrff_reset_MASK 0x40000000
-#define BCHP_USB_CTRL_EBRIDGE_ebrff_reset_SHIFT 30
-#define BCHP_USB_CTRL_EBRIDGE_ebrff_reset_DEFAULT 0x00000000
-
-/* USB_CTRL :: EBRIDGE :: ebr_wrgwordcnt_sel [29:29] */
-#define BCHP_USB_CTRL_EBRIDGE_ebr_wrgwordcnt_sel_MASK 0x20000000
-#define BCHP_USB_CTRL_EBRIDGE_ebr_wrgwordcnt_sel_SHIFT 29
-#define BCHP_USB_CTRL_EBRIDGE_ebr_wrgwordcnt_sel_DEFAULT 0x00000000
-
-/* USB_CTRL :: EBRIDGE :: ebr_size_sel [28:28] */
-#define BCHP_USB_CTRL_EBRIDGE_ebr_size_sel_MASK 0x10000000
-#define BCHP_USB_CTRL_EBRIDGE_ebr_size_sel_SHIFT 28
-#define BCHP_USB_CTRL_EBRIDGE_ebr_size_sel_DEFAULT 0x00000000
-
-/* USB_CTRL :: EBRIDGE :: EBR_SPARE [27:18] */
-#define BCHP_USB_CTRL_EBRIDGE_EBR_SPARE_MASK 0x0ffc0000
-#define BCHP_USB_CTRL_EBRIDGE_EBR_SPARE_SHIFT 18
-#define BCHP_USB_CTRL_EBRIDGE_EBR_SPARE_DEFAULT 0x00000000
-
-/* USB_CTRL :: EBRIDGE :: ESTOP_SCB_REQ [17:17] */
-#define BCHP_USB_CTRL_EBRIDGE_ESTOP_SCB_REQ_MASK 0x00020000
-#define BCHP_USB_CTRL_EBRIDGE_ESTOP_SCB_REQ_SHIFT 17
-#define BCHP_USB_CTRL_EBRIDGE_ESTOP_SCB_REQ_DEFAULT 0x00000000
-
-/* USB_CTRL :: EBRIDGE :: EBR_RD_THRESH [16:12] */
-#define BCHP_USB_CTRL_EBRIDGE_EBR_RD_THRESH_MASK 0x0001f000
-#define BCHP_USB_CTRL_EBRIDGE_EBR_RD_THRESH_SHIFT 12
-#define BCHP_USB_CTRL_EBRIDGE_EBR_RD_THRESH_DEFAULT 0x00000002
-
-/* USB_CTRL :: EBRIDGE :: EBR_SCB_SIZE [11:07] */
-#define BCHP_USB_CTRL_EBRIDGE_EBR_SCB_SIZE_MASK 0x00000f80
-#define BCHP_USB_CTRL_EBRIDGE_EBR_SCB_SIZE_SHIFT 7
-#define BCHP_USB_CTRL_EBRIDGE_EBR_SCB_SIZE_DEFAULT 0x00000004
-
-/* USB_CTRL :: EBRIDGE :: EBR_MISC [06:01] */
-#define BCHP_USB_CTRL_EBRIDGE_EBR_MISC_MASK 0x0000007e
-#define BCHP_USB_CTRL_EBRIDGE_EBR_MISC_SHIFT 1
-#define BCHP_USB_CTRL_EBRIDGE_EBR_MISC_DEFAULT 0x00000000
-
-/* USB_CTRL :: EBRIDGE :: EBR_SEQ_EN [00:00] */
-#define BCHP_USB_CTRL_EBRIDGE_EBR_SEQ_EN_MASK 0x00000001
-#define BCHP_USB_CTRL_EBRIDGE_EBR_SEQ_EN_SHIFT 0
-#define BCHP_USB_CTRL_EBRIDGE_EBR_SEQ_EN_DEFAULT 0x00000000
-
-/***************************************************************************
- *OBRIDGE - Control Register for OHCI Bridge
- ***************************************************************************/
-/* USB_CTRL :: OBRIDGE :: OBR_SOFT_RESET [31:31] */
-#define BCHP_USB_CTRL_OBRIDGE_OBR_SOFT_RESET_MASK 0x80000000
-#define BCHP_USB_CTRL_OBRIDGE_OBR_SOFT_RESET_SHIFT 31
-#define BCHP_USB_CTRL_OBRIDGE_OBR_SOFT_RESET_DEFAULT 0x00000000
-
-/* USB_CTRL :: OBRIDGE :: obrff_reset [30:30] */
-#define BCHP_USB_CTRL_OBRIDGE_obrff_reset_MASK 0x40000000
-#define BCHP_USB_CTRL_OBRIDGE_obrff_reset_SHIFT 30
-#define BCHP_USB_CTRL_OBRIDGE_obrff_reset_DEFAULT 0x00000000
-
-/* USB_CTRL :: OBRIDGE :: obr_wrgwordcnt_sel [29:29] */
-#define BCHP_USB_CTRL_OBRIDGE_obr_wrgwordcnt_sel_MASK 0x20000000
-#define BCHP_USB_CTRL_OBRIDGE_obr_wrgwordcnt_sel_SHIFT 29
-#define BCHP_USB_CTRL_OBRIDGE_obr_wrgwordcnt_sel_DEFAULT 0x00000000
-
-/* USB_CTRL :: OBRIDGE :: obr_size_sel [28:28] */
-#define BCHP_USB_CTRL_OBRIDGE_obr_size_sel_MASK 0x10000000
-#define BCHP_USB_CTRL_OBRIDGE_obr_size_sel_SHIFT 28
-#define BCHP_USB_CTRL_OBRIDGE_obr_size_sel_DEFAULT 0x00000000
-
-/* USB_CTRL :: OBRIDGE :: OBR_SPARE [27:18] */
-#define BCHP_USB_CTRL_OBRIDGE_OBR_SPARE_MASK 0x0ffc0000
-#define BCHP_USB_CTRL_OBRIDGE_OBR_SPARE_SHIFT 18
-#define BCHP_USB_CTRL_OBRIDGE_OBR_SPARE_DEFAULT 0x00000000
-
-/* USB_CTRL :: OBRIDGE :: OSTOP_SCB_REQ [17:17] */
-#define BCHP_USB_CTRL_OBRIDGE_OSTOP_SCB_REQ_MASK 0x00020000
-#define BCHP_USB_CTRL_OBRIDGE_OSTOP_SCB_REQ_SHIFT 17
-#define BCHP_USB_CTRL_OBRIDGE_OSTOP_SCB_REQ_DEFAULT 0x00000000
-
-/* USB_CTRL :: OBRIDGE :: OBR_RD_THRESH [16:12] */
-#define BCHP_USB_CTRL_OBRIDGE_OBR_RD_THRESH_MASK 0x0001f000
-#define BCHP_USB_CTRL_OBRIDGE_OBR_RD_THRESH_SHIFT 12
-#define BCHP_USB_CTRL_OBRIDGE_OBR_RD_THRESH_DEFAULT 0x00000002
-
-/* USB_CTRL :: OBRIDGE :: OBR_SCB_SIZE [11:07] */
-#define BCHP_USB_CTRL_OBRIDGE_OBR_SCB_SIZE_MASK 0x00000f80
-#define BCHP_USB_CTRL_OBRIDGE_OBR_SCB_SIZE_SHIFT 7
-#define BCHP_USB_CTRL_OBRIDGE_OBR_SCB_SIZE_DEFAULT 0x00000004
-
-/* USB_CTRL :: OBRIDGE :: OBR_MISC [06:01] */
-#define BCHP_USB_CTRL_OBRIDGE_OBR_MISC_MASK 0x0000007e
-#define BCHP_USB_CTRL_OBRIDGE_OBR_MISC_SHIFT 1
-#define BCHP_USB_CTRL_OBRIDGE_OBR_MISC_DEFAULT 0x00000000
-
-/* USB_CTRL :: OBRIDGE :: OBR_SEQ_EN [00:00] */
-#define BCHP_USB_CTRL_OBRIDGE_OBR_SEQ_EN_MASK 0x00000001
-#define BCHP_USB_CTRL_OBRIDGE_OBR_SEQ_EN_SHIFT 0
-#define BCHP_USB_CTRL_OBRIDGE_OBR_SEQ_EN_DEFAULT 0x00000000
-
-/***************************************************************************
- *MDIO - MDIO Interface Programming Register
- ***************************************************************************/
-/* USB_CTRL :: MDIO :: MDIO_PHY_SEL [31:31] */
-#define BCHP_USB_CTRL_MDIO_MDIO_PHY_SEL_MASK 0x80000000
-#define BCHP_USB_CTRL_MDIO_MDIO_PHY_SEL_SHIFT 31
-#define BCHP_USB_CTRL_MDIO_MDIO_PHY_SEL_DEFAULT 0x00000000
-
-/* USB_CTRL :: MDIO :: MDIO_SPARE [30:26] */
-#define BCHP_USB_CTRL_MDIO_MDIO_SPARE_MASK 0x7c000000
-#define BCHP_USB_CTRL_MDIO_MDIO_SPARE_SHIFT 26
-#define BCHP_USB_CTRL_MDIO_MDIO_SPARE_DEFAULT 0x00000000
-
-/* USB_CTRL :: MDIO :: WR_START [25:25] */
-#define BCHP_USB_CTRL_MDIO_WR_START_MASK 0x02000000
-#define BCHP_USB_CTRL_MDIO_WR_START_SHIFT 25
-#define BCHP_USB_CTRL_MDIO_WR_START_DEFAULT 0x00000000
-
-/* USB_CTRL :: MDIO :: RD_START [24:24] */
-#define BCHP_USB_CTRL_MDIO_RD_START_MASK 0x01000000
-#define BCHP_USB_CTRL_MDIO_RD_START_SHIFT 24
-#define BCHP_USB_CTRL_MDIO_RD_START_DEFAULT 0x00000000
-
-/* USB_CTRL :: MDIO :: MDIO_ADDR [23:16] */
-#define BCHP_USB_CTRL_MDIO_MDIO_ADDR_MASK 0x00ff0000
-#define BCHP_USB_CTRL_MDIO_MDIO_ADDR_SHIFT 16
-#define BCHP_USB_CTRL_MDIO_MDIO_ADDR_DEFAULT 0x00000000
-
-/* USB_CTRL :: MDIO :: MDIO_DATA [15:00] */
-#define BCHP_USB_CTRL_MDIO_MDIO_DATA_MASK 0x0000ffff
-#define BCHP_USB_CTRL_MDIO_MDIO_DATA_SHIFT 0
-#define BCHP_USB_CTRL_MDIO_MDIO_DATA_DEFAULT 0x00000000
-
-/***************************************************************************
- *MDIO2 - MDIO Interface Read Register
- ***************************************************************************/
-/* USB_CTRL :: MDIO2 :: SYNOPSYS_CORE_ID [31:16] */
-#define BCHP_USB_CTRL_MDIO2_SYNOPSYS_CORE_ID_MASK 0xffff0000
-#define BCHP_USB_CTRL_MDIO2_SYNOPSYS_CORE_ID_SHIFT 16
-#define BCHP_USB_CTRL_MDIO2_SYNOPSYS_CORE_ID_DEFAULT 0x0000298a
-
-/* USB_CTRL :: MDIO2 :: MDIO_RD_DATA [15:00] */
-#define BCHP_USB_CTRL_MDIO2_MDIO_RD_DATA_MASK 0x0000ffff
-#define BCHP_USB_CTRL_MDIO2_MDIO_RD_DATA_SHIFT 0
-#define BCHP_USB_CTRL_MDIO2_MDIO_RD_DATA_DEFAULT 0x00000000
-
-/***************************************************************************
- *TEST_PORT_CTL - Test Port Control Register
- ***************************************************************************/
-/* USB_CTRL :: TEST_PORT_CTL :: TPCTL_SPARE [31:28] */
-#define BCHP_USB_CTRL_TEST_PORT_CTL_TPCTL_SPARE_MASK 0xf0000000
-#define BCHP_USB_CTRL_TEST_PORT_CTL_TPCTL_SPARE_SHIFT 28
-#define BCHP_USB_CTRL_TEST_PORT_CTL_TPCTL_SPARE_DEFAULT 0x00000000
-
-/* USB_CTRL :: TEST_PORT_CTL :: scb2_wr_data_sel [27:27] */
-#define BCHP_USB_CTRL_TEST_PORT_CTL_scb2_wr_data_sel_MASK 0x08000000
-#define BCHP_USB_CTRL_TEST_PORT_CTL_scb2_wr_data_sel_SHIFT 27
-#define BCHP_USB_CTRL_TEST_PORT_CTL_scb2_wr_data_sel_DEFAULT 0x00000000
-
-/* USB_CTRL :: TEST_PORT_CTL :: scb1_wr_data_sel [26:26] */
-#define BCHP_USB_CTRL_TEST_PORT_CTL_scb1_wr_data_sel_MASK 0x04000000
-#define BCHP_USB_CTRL_TEST_PORT_CTL_scb1_wr_data_sel_SHIFT 26
-#define BCHP_USB_CTRL_TEST_PORT_CTL_scb1_wr_data_sel_DEFAULT 0x00000000
-
-/* USB_CTRL :: TEST_PORT_CTL :: scb0_wr_data_sel [25:25] */
-#define BCHP_USB_CTRL_TEST_PORT_CTL_scb0_wr_data_sel_MASK 0x02000000
-#define BCHP_USB_CTRL_TEST_PORT_CTL_scb0_wr_data_sel_SHIFT 25
-#define BCHP_USB_CTRL_TEST_PORT_CTL_scb0_wr_data_sel_DEFAULT 0x00000000
-
-/* USB_CTRL :: TEST_PORT_CTL :: testclk_sel [24:23] */
-#define BCHP_USB_CTRL_TEST_PORT_CTL_testclk_sel_MASK 0x01800000
-#define BCHP_USB_CTRL_TEST_PORT_CTL_testclk_sel_SHIFT 23
-#define BCHP_USB_CTRL_TEST_PORT_CTL_testclk_sel_DEFAULT 0x00000000
-
-/* USB_CTRL :: TEST_PORT_CTL :: pwrflt_testsel [22:21] */
-#define BCHP_USB_CTRL_TEST_PORT_CTL_pwrflt_testsel_MASK 0x00600000
-#define BCHP_USB_CTRL_TEST_PORT_CTL_pwrflt_testsel_SHIFT 21
-#define BCHP_USB_CTRL_TEST_PORT_CTL_pwrflt_testsel_DEFAULT 0x00000000
-
-/* USB_CTRL :: TEST_PORT_CTL :: pwrflt1_oe [20:20] */
-#define BCHP_USB_CTRL_TEST_PORT_CTL_pwrflt1_oe_MASK 0x00100000
-#define BCHP_USB_CTRL_TEST_PORT_CTL_pwrflt1_oe_SHIFT 20
-#define BCHP_USB_CTRL_TEST_PORT_CTL_pwrflt1_oe_DEFAULT 0x00000000
-
-/* USB_CTRL :: TEST_PORT_CTL :: pwrflt0_oe [19:19] */
-#define BCHP_USB_CTRL_TEST_PORT_CTL_pwrflt0_oe_MASK 0x00080000
-#define BCHP_USB_CTRL_TEST_PORT_CTL_pwrflt0_oe_SHIFT 19
-#define BCHP_USB_CTRL_TEST_PORT_CTL_pwrflt0_oe_DEFAULT 0x00000000
-
-/* USB_CTRL :: TEST_PORT_CTL :: pwron1_testsel [18:18] */
-#define BCHP_USB_CTRL_TEST_PORT_CTL_pwron1_testsel_MASK 0x00040000
-#define BCHP_USB_CTRL_TEST_PORT_CTL_pwron1_testsel_SHIFT 18
-#define BCHP_USB_CTRL_TEST_PORT_CTL_pwron1_testsel_DEFAULT 0x00000000
-
-/* USB_CTRL :: TEST_PORT_CTL :: pwron0_testsel [17:17] */
-#define BCHP_USB_CTRL_TEST_PORT_CTL_pwron0_testsel_MASK 0x00020000
-#define BCHP_USB_CTRL_TEST_PORT_CTL_pwron0_testsel_SHIFT 17
-#define BCHP_USB_CTRL_TEST_PORT_CTL_pwron0_testsel_DEFAULT 0x00000000
-
-/* USB_CTRL :: TEST_PORT_CTL :: tpin_sel [16:16] */
-#define BCHP_USB_CTRL_TEST_PORT_CTL_tpin_sel_MASK 0x00010000
-#define BCHP_USB_CTRL_TEST_PORT_CTL_tpin_sel_SHIFT 16
-#define BCHP_USB_CTRL_TEST_PORT_CTL_tpin_sel_DEFAULT 0x00000000
-
-/* USB_CTRL :: TEST_PORT_CTL :: UTMI_TP_SEL [15:08] */
-#define BCHP_USB_CTRL_TEST_PORT_CTL_UTMI_TP_SEL_MASK 0x0000ff00
-#define BCHP_USB_CTRL_TEST_PORT_CTL_UTMI_TP_SEL_SHIFT 8
-#define BCHP_USB_CTRL_TEST_PORT_CTL_UTMI_TP_SEL_DEFAULT 0x00000000
-
-/* USB_CTRL :: TEST_PORT_CTL :: TPOUT_SEL [07:00] */
-#define BCHP_USB_CTRL_TEST_PORT_CTL_TPOUT_SEL_MASK 0x000000ff
-#define BCHP_USB_CTRL_TEST_PORT_CTL_TPOUT_SEL_SHIFT 0
-#define BCHP_USB_CTRL_TEST_PORT_CTL_TPOUT_SEL_DEFAULT 0x00000000
-#define BCHP_USB_CTRL_TEST_PORT_CTL_TPOUT_SEL_hc_diag0 0
-#define BCHP_USB_CTRL_TEST_PORT_CTL_TPOUT_SEL_hc_diag1 1
-#define BCHP_USB_CTRL_TEST_PORT_CTL_TPOUT_SEL_hc_diag2 2
-#define BCHP_USB_CTRL_TEST_PORT_CTL_TPOUT_SEL_hc_diag3 3
-#define BCHP_USB_CTRL_TEST_PORT_CTL_TPOUT_SEL_hc_diag4 4
-#define BCHP_USB_CTRL_TEST_PORT_CTL_TPOUT_SEL_hc_diag5 5
-#define BCHP_USB_CTRL_TEST_PORT_CTL_TPOUT_SEL_hc_diag6 6
-#define BCHP_USB_CTRL_TEST_PORT_CTL_TPOUT_SEL_hc_diag7 7
-#define BCHP_USB_CTRL_TEST_PORT_CTL_TPOUT_SEL_hc_diag8 8
-#define BCHP_USB_CTRL_TEST_PORT_CTL_TPOUT_SEL_hc_diag9 9
-#define BCHP_USB_CTRL_TEST_PORT_CTL_TPOUT_SEL_hc_diag10 10
-#define BCHP_USB_CTRL_TEST_PORT_CTL_TPOUT_SEL_hc_diag11 11
-#define BCHP_USB_CTRL_TEST_PORT_CTL_TPOUT_SEL_hc_diag12 12
-#define BCHP_USB_CTRL_TEST_PORT_CTL_TPOUT_SEL_hc_diag13 13
-#define BCHP_USB_CTRL_TEST_PORT_CTL_TPOUT_SEL_hc_diag14 14
-#define BCHP_USB_CTRL_TEST_PORT_CTL_TPOUT_SEL_hc_diag15 15
-#define BCHP_USB_CTRL_TEST_PORT_CTL_TPOUT_SEL_hc_diag16 16
-#define BCHP_USB_CTRL_TEST_PORT_CTL_TPOUT_SEL_hc_diag17 17
-#define BCHP_USB_CTRL_TEST_PORT_CTL_TPOUT_SEL_hc_diag18 18
-#define BCHP_USB_CTRL_TEST_PORT_CTL_TPOUT_SEL_hc_diag19 19
-#define BCHP_USB_CTRL_TEST_PORT_CTL_TPOUT_SEL_hc_diag20 20
-#define BCHP_USB_CTRL_TEST_PORT_CTL_TPOUT_SEL_hc_diag21 21
-#define BCHP_USB_CTRL_TEST_PORT_CTL_TPOUT_SEL_hc_diag22 22
-#define BCHP_USB_CTRL_TEST_PORT_CTL_TPOUT_SEL_hc_diag23 23
-#define BCHP_USB_CTRL_TEST_PORT_CTL_TPOUT_SEL_hc_diag24 24
-#define BCHP_USB_CTRL_TEST_PORT_CTL_TPOUT_SEL_hc_diag25 25
-
-/***************************************************************************
- *USB_SIMCTL - Simulation Register
- ***************************************************************************/
-/* USB_CTRL :: USB_SIMCTL :: sim_mode_en [31:31] */
-#define BCHP_USB_CTRL_USB_SIMCTL_sim_mode_en_MASK 0x80000000
-#define BCHP_USB_CTRL_USB_SIMCTL_sim_mode_en_SHIFT 31
-#define BCHP_USB_CTRL_USB_SIMCTL_sim_mode_en_DEFAULT 0x00000000
-
-/* USB_CTRL :: USB_SIMCTL :: scale_down_en [30:30] */
-#define BCHP_USB_CTRL_USB_SIMCTL_scale_down_en_MASK 0x40000000
-#define BCHP_USB_CTRL_USB_SIMCTL_scale_down_en_SHIFT 30
-#define BCHP_USB_CTRL_USB_SIMCTL_scale_down_en_DEFAULT 0x00000000
-
-/* USB_CTRL :: USB_SIMCTL :: otg_scale_down_en [29:28] */
-#define BCHP_USB_CTRL_USB_SIMCTL_otg_scale_down_en_MASK 0x30000000
-#define BCHP_USB_CTRL_USB_SIMCTL_otg_scale_down_en_SHIFT 28
-#define BCHP_USB_CTRL_USB_SIMCTL_otg_scale_down_en_DEFAULT 0x00000000
-
-/* USB_CTRL :: USB_SIMCTL :: intr_test [27:27] */
-#define BCHP_USB_CTRL_USB_SIMCTL_intr_test_MASK 0x08000000
-#define BCHP_USB_CTRL_USB_SIMCTL_intr_test_SHIFT 27
-#define BCHP_USB_CTRL_USB_SIMCTL_intr_test_DEFAULT 0x00000000
-
-/* USB_CTRL :: USB_SIMCTL :: AUTOPPD_ON_OVERCUR_EN [26:26] */
-#define BCHP_USB_CTRL_USB_SIMCTL_AUTOPPD_ON_OVERCUR_EN_MASK 0x04000000
-#define BCHP_USB_CTRL_USB_SIMCTL_AUTOPPD_ON_OVERCUR_EN_SHIFT 26
-#define BCHP_USB_CTRL_USB_SIMCTL_AUTOPPD_ON_OVERCUR_EN_DEFAULT 0x00000000
-
-/* USB_CTRL :: USB_SIMCTL :: SIMCTL_SPARE [25:10] */
-#define BCHP_USB_CTRL_USB_SIMCTL_SIMCTL_SPARE_MASK 0x03fffc00
-#define BCHP_USB_CTRL_USB_SIMCTL_SIMCTL_SPARE_SHIFT 10
-#define BCHP_USB_CTRL_USB_SIMCTL_SIMCTL_SPARE_DEFAULT 0x00000000
-
-/* USB_CTRL :: USB_SIMCTL :: ss_hubsetup_min [09:09] */
-#define BCHP_USB_CTRL_USB_SIMCTL_ss_hubsetup_min_MASK 0x00000200
-#define BCHP_USB_CTRL_USB_SIMCTL_ss_hubsetup_min_SHIFT 9
-#define BCHP_USB_CTRL_USB_SIMCTL_ss_hubsetup_min_DEFAULT 0x00000000
-
-/* USB_CTRL :: USB_SIMCTL :: ohci_memreq_disable [08:08] */
-#define BCHP_USB_CTRL_USB_SIMCTL_ohci_memreq_disable_MASK 0x00000100
-#define BCHP_USB_CTRL_USB_SIMCTL_ohci_memreq_disable_SHIFT 8
-#define BCHP_USB_CTRL_USB_SIMCTL_ohci_memreq_disable_DEFAULT 0x00000000
-
-/* USB_CTRL :: USB_SIMCTL :: SIMCTL_SPARE2 [07:07] */
-#define BCHP_USB_CTRL_USB_SIMCTL_SIMCTL_SPARE2_MASK 0x00000080
-#define BCHP_USB_CTRL_USB_SIMCTL_SIMCTL_SPARE2_SHIFT 7
-#define BCHP_USB_CTRL_USB_SIMCTL_SIMCTL_SPARE2_DEFAULT 0x00000000
-
-/* USB_CTRL :: USB_SIMCTL :: usb_cap_dis [06:06] */
-#define BCHP_USB_CTRL_USB_SIMCTL_usb_cap_dis_MASK 0x00000040
-#define BCHP_USB_CTRL_USB_SIMCTL_usb_cap_dis_SHIFT 6
-#define BCHP_USB_CTRL_USB_SIMCTL_usb_cap_dis_DEFAULT 0x00000000
-
-/* USB_CTRL :: USB_SIMCTL :: scb_req_lgcy [05:05] */
-#define BCHP_USB_CTRL_USB_SIMCTL_scb_req_lgcy_MASK 0x00000020
-#define BCHP_USB_CTRL_USB_SIMCTL_scb_req_lgcy_SHIFT 5
-#define BCHP_USB_CTRL_USB_SIMCTL_scb_req_lgcy_DEFAULT 0x00000000
-
-/* USB_CTRL :: USB_SIMCTL :: rel_270a_comp [04:04] */
-#define BCHP_USB_CTRL_USB_SIMCTL_rel_270a_comp_MASK 0x00000010
-#define BCHP_USB_CTRL_USB_SIMCTL_rel_270a_comp_SHIFT 4
-#define BCHP_USB_CTRL_USB_SIMCTL_rel_270a_comp_DEFAULT 0x00000000
-
-/* USB_CTRL :: USB_SIMCTL :: SIMCTL_SPARE1 [03:00] */
-#define BCHP_USB_CTRL_USB_SIMCTL_SIMCTL_SPARE1_MASK 0x0000000f
-#define BCHP_USB_CTRL_USB_SIMCTL_SIMCTL_SPARE1_SHIFT 0
-#define BCHP_USB_CTRL_USB_SIMCTL_SIMCTL_SPARE1_DEFAULT 0x00000000
-
-/***************************************************************************
- *USB_TESTCTL - Throutput Test Control
- ***************************************************************************/
-/* USB_CTRL :: USB_TESTCTL :: TESTCTL_SPARE2 [31:23] */
-#define BCHP_USB_CTRL_USB_TESTCTL_TESTCTL_SPARE2_MASK 0xff800000
-#define BCHP_USB_CTRL_USB_TESTCTL_TESTCTL_SPARE2_SHIFT 23
-#define BCHP_USB_CTRL_USB_TESTCTL_TESTCTL_SPARE2_DEFAULT 0x00000000
-
-/* USB_CTRL :: USB_TESTCTL :: CONTROLLER_SEL [22:21] */
-#define BCHP_USB_CTRL_USB_TESTCTL_CONTROLLER_SEL_MASK 0x00600000
-#define BCHP_USB_CTRL_USB_TESTCTL_CONTROLLER_SEL_SHIFT 21
-#define BCHP_USB_CTRL_USB_TESTCTL_CONTROLLER_SEL_DEFAULT 0x00000000
-
-/* USB_CTRL :: USB_TESTCTL :: DCNT_EN [20:20] */
-#define BCHP_USB_CTRL_USB_TESTCTL_DCNT_EN_MASK 0x00100000
-#define BCHP_USB_CTRL_USB_TESTCTL_DCNT_EN_SHIFT 20
-#define BCHP_USB_CTRL_USB_TESTCTL_DCNT_EN_DEFAULT 0x00000000
-
-/* USB_CTRL :: USB_TESTCTL :: SPEED_SEL [19:19] */
-#define BCHP_USB_CTRL_USB_TESTCTL_SPEED_SEL_MASK 0x00080000
-#define BCHP_USB_CTRL_USB_TESTCTL_SPEED_SEL_SHIFT 19
-#define BCHP_USB_CTRL_USB_TESTCTL_SPEED_SEL_DEFAULT 0x00000000
-
-/* USB_CTRL :: USB_TESTCTL :: DCNT_SEL [18:16] */
-#define BCHP_USB_CTRL_USB_TESTCTL_DCNT_SEL_MASK 0x00070000
-#define BCHP_USB_CTRL_USB_TESTCTL_DCNT_SEL_SHIFT 16
-#define BCHP_USB_CTRL_USB_TESTCTL_DCNT_SEL_DEFAULT 0x00000000
-
-/* USB_CTRL :: USB_TESTCTL :: TESTCTL_SPARE1 [15:10] */
-#define BCHP_USB_CTRL_USB_TESTCTL_TESTCTL_SPARE1_MASK 0x0000fc00
-#define BCHP_USB_CTRL_USB_TESTCTL_TESTCTL_SPARE1_SHIFT 10
-#define BCHP_USB_CTRL_USB_TESTCTL_TESTCTL_SPARE1_DEFAULT 0x00000000
-
-/* USB_CTRL :: USB_TESTCTL :: MSEC_PRESCALER [09:00] */
-#define BCHP_USB_CTRL_USB_TESTCTL_MSEC_PRESCALER_MASK 0x000003ff
-#define BCHP_USB_CTRL_USB_TESTCTL_MSEC_PRESCALER_SHIFT 0
-#define BCHP_USB_CTRL_USB_TESTCTL_MSEC_PRESCALER_DEFAULT 0x00000000
-
-/***************************************************************************
- *USB_TESTMON - Throughput Test Monitor
- ***************************************************************************/
-/* USB_CTRL :: USB_TESTMON :: PLL_SS_LOCK [31:31] */
-#define BCHP_USB_CTRL_USB_TESTMON_PLL_SS_LOCK_MASK 0x80000000
-#define BCHP_USB_CTRL_USB_TESTMON_PLL_SS_LOCK_SHIFT 31
-#define BCHP_USB_CTRL_USB_TESTMON_PLL_SS_LOCK_DEFAULT 0x00000000
-
-/* USB_CTRL :: USB_TESTMON :: PLL_HS_LOCK [30:30] */
-#define BCHP_USB_CTRL_USB_TESTMON_PLL_HS_LOCK_MASK 0x40000000
-#define BCHP_USB_CTRL_USB_TESTMON_PLL_HS_LOCK_SHIFT 30
-#define BCHP_USB_CTRL_USB_TESTMON_PLL_HS_LOCK_DEFAULT 0x00000000
-
-/* USB_CTRL :: USB_TESTMON :: LDO_FLAG_ON [29:29] */
-#define BCHP_USB_CTRL_USB_TESTMON_LDO_FLAG_ON_MASK 0x20000000
-#define BCHP_USB_CTRL_USB_TESTMON_LDO_FLAG_ON_SHIFT 29
-#define BCHP_USB_CTRL_USB_TESTMON_LDO_FLAG_ON_DEFAULT 0x00000000
-
-/* USB_CTRL :: USB_TESTMON :: TESTMON_STAT [28:00] */
-#define BCHP_USB_CTRL_USB_TESTMON_TESTMON_STAT_MASK 0x1fffffff
-#define BCHP_USB_CTRL_USB_TESTMON_TESTMON_STAT_SHIFT 0
-
-/***************************************************************************
- *UTMI_CTL_1 - UTMI Control Register
- ***************************************************************************/
-/* USB_CTRL :: UTMI_CTL_1 :: USB11_TX_OEB_P1 [31:31] */
-#define BCHP_USB_CTRL_UTMI_CTL_1_USB11_TX_OEB_P1_MASK 0x80000000
-#define BCHP_USB_CTRL_UTMI_CTL_1_USB11_TX_OEB_P1_SHIFT 31
-#define BCHP_USB_CTRL_UTMI_CTL_1_USB11_TX_OEB_P1_DEFAULT 0x00000000
-
-/* USB_CTRL :: UTMI_CTL_1 :: SYNC_DET_LENG_P1 [30:28] */
-#define BCHP_USB_CTRL_UTMI_CTL_1_SYNC_DET_LENG_P1_MASK 0x70000000
-#define BCHP_USB_CTRL_UTMI_CTL_1_SYNC_DET_LENG_P1_SHIFT 28
-#define BCHP_USB_CTRL_UTMI_CTL_1_SYNC_DET_LENG_P1_DEFAULT 0x00000000
-
-/* USB_CTRL :: UTMI_CTL_1 :: POWER_UP_FSM_EN_P1 [27:27] */
-#define BCHP_USB_CTRL_UTMI_CTL_1_POWER_UP_FSM_EN_P1_MASK 0x08000000
-#define BCHP_USB_CTRL_UTMI_CTL_1_POWER_UP_FSM_EN_P1_SHIFT 27
-#define BCHP_USB_CTRL_UTMI_CTL_1_POWER_UP_FSM_EN_P1_DEFAULT 0x00000001
-
-/* USB_CTRL :: UTMI_CTL_1 :: NO_R45_CALIB_P1 [26:26] */
-#define BCHP_USB_CTRL_UTMI_CTL_1_NO_R45_CALIB_P1_MASK 0x04000000
-#define BCHP_USB_CTRL_UTMI_CTL_1_NO_R45_CALIB_P1_SHIFT 26
-#define BCHP_USB_CTRL_UTMI_CTL_1_NO_R45_CALIB_P1_DEFAULT 0x00000000
-
-/* USB_CTRL :: UTMI_CTL_1 :: BC10_ACTIVE_IDLE_PU_P1 [25:25] */
-#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_ACTIVE_IDLE_PU_P1_MASK 0x02000000
-#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_ACTIVE_IDLE_PU_P1_SHIFT 25
-#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_ACTIVE_IDLE_PU_P1_DEFAULT 0x00000000
-
-/* USB_CTRL :: UTMI_CTL_1 :: POWER_UP_FSM_SPEED_P1 [24:24] */
-#define BCHP_USB_CTRL_UTMI_CTL_1_POWER_UP_FSM_SPEED_P1_MASK 0x01000000
-#define BCHP_USB_CTRL_UTMI_CTL_1_POWER_UP_FSM_SPEED_P1_SHIFT 24
-#define BCHP_USB_CTRL_UTMI_CTL_1_POWER_UP_FSM_SPEED_P1_DEFAULT 0x00000000
-
-/* USB_CTRL :: UTMI_CTL_1 :: BC10_DM_PU_P1 [23:23] */
-#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_DM_PU_P1_MASK 0x00800000
-#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_DM_PU_P1_SHIFT 23
-#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_DM_PU_P1_DEFAULT 0x00000000
-
-/* USB_CTRL :: UTMI_CTL_1 :: BC10_DP_PU_P1 [22:22] */
-#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_DP_PU_P1_MASK 0x00400000
-#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_DP_PU_P1_SHIFT 22
-#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_DP_PU_P1_DEFAULT 0x00000000
-
-/* USB_CTRL :: UTMI_CTL_1 :: BC10_DM_PD_P1 [21:21] */
-#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_DM_PD_P1_MASK 0x00200000
-#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_DM_PD_P1_SHIFT 21
-#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_DM_PD_P1_DEFAULT 0x00000000
-
-/* USB_CTRL :: UTMI_CTL_1 :: BC10_DP_PD_P1 [20:20] */
-#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_DP_PD_P1_MASK 0x00100000
-#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_DP_PD_P1_SHIFT 20
-#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_DP_PD_P1_DEFAULT 0x00000000
-
-/* USB_CTRL :: UTMI_CTL_1 :: PHY_MODE_P1 [19:18] */
-#define BCHP_USB_CTRL_UTMI_CTL_1_PHY_MODE_P1_MASK 0x000c0000
-#define BCHP_USB_CTRL_UTMI_CTL_1_PHY_MODE_P1_SHIFT 18
-#define BCHP_USB_CTRL_UTMI_CTL_1_PHY_MODE_P1_DEFAULT 0x00000000
-#define BCHP_USB_CTRL_UTMI_CTL_1_PHY_MODE_P1_Host 0
-#define BCHP_USB_CTRL_UTMI_CTL_1_PHY_MODE_P1_Device 1
-#define BCHP_USB_CTRL_UTMI_CTL_1_PHY_MODE_P1_OTG 2
-#define BCHP_USB_CTRL_UTMI_CTL_1_PHY_MODE_P1_BC10 3
-
-/* USB_CTRL :: UTMI_CTL_1 :: UTMI_SOFT_RESETB_P1 [17:17] */
-#define BCHP_USB_CTRL_UTMI_CTL_1_UTMI_SOFT_RESETB_P1_MASK 0x00020000
-#define BCHP_USB_CTRL_UTMI_CTL_1_UTMI_SOFT_RESETB_P1_SHIFT 17
-#define BCHP_USB_CTRL_UTMI_CTL_1_UTMI_SOFT_RESETB_P1_DEFAULT 0x00000001
-
-/* USB_CTRL :: UTMI_CTL_1 :: AFE_NON_DRIVING_P1 [16:16] */
-#define BCHP_USB_CTRL_UTMI_CTL_1_AFE_NON_DRIVING_P1_MASK 0x00010000
-#define BCHP_USB_CTRL_UTMI_CTL_1_AFE_NON_DRIVING_P1_SHIFT 16
-#define BCHP_USB_CTRL_UTMI_CTL_1_AFE_NON_DRIVING_P1_DEFAULT 0x00000000
-
-/* USB_CTRL :: UTMI_CTL_1 :: USB11_TX_OEB [15:15] */
-#define BCHP_USB_CTRL_UTMI_CTL_1_USB11_TX_OEB_MASK 0x00008000
-#define BCHP_USB_CTRL_UTMI_CTL_1_USB11_TX_OEB_SHIFT 15
-#define BCHP_USB_CTRL_UTMI_CTL_1_USB11_TX_OEB_DEFAULT 0x00000000
-
-/* USB_CTRL :: UTMI_CTL_1 :: SYNC_DET_LENG [14:12] */
-#define BCHP_USB_CTRL_UTMI_CTL_1_SYNC_DET_LENG_MASK 0x00007000
-#define BCHP_USB_CTRL_UTMI_CTL_1_SYNC_DET_LENG_SHIFT 12
-#define BCHP_USB_CTRL_UTMI_CTL_1_SYNC_DET_LENG_DEFAULT 0x00000000
-
-/* USB_CTRL :: UTMI_CTL_1 :: POWER_UP_FSM_EN [11:11] */
-#define BCHP_USB_CTRL_UTMI_CTL_1_POWER_UP_FSM_EN_MASK 0x00000800
-#define BCHP_USB_CTRL_UTMI_CTL_1_POWER_UP_FSM_EN_SHIFT 11
-#define BCHP_USB_CTRL_UTMI_CTL_1_POWER_UP_FSM_EN_DEFAULT 0x00000001
-
-/* USB_CTRL :: UTMI_CTL_1 :: NO_R45_CALIB [10:10] */
-#define BCHP_USB_CTRL_UTMI_CTL_1_NO_R45_CALIB_MASK 0x00000400
-#define BCHP_USB_CTRL_UTMI_CTL_1_NO_R45_CALIB_SHIFT 10
-#define BCHP_USB_CTRL_UTMI_CTL_1_NO_R45_CALIB_DEFAULT 0x00000000
-
-/* USB_CTRL :: UTMI_CTL_1 :: BC10_ACTIVE_IDLE_PU [09:09] */
-#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_ACTIVE_IDLE_PU_MASK 0x00000200
-#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_ACTIVE_IDLE_PU_SHIFT 9
-#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_ACTIVE_IDLE_PU_DEFAULT 0x00000000
-
-/* USB_CTRL :: UTMI_CTL_1 :: POWER_UP_FSM_SPEED [08:08] */
-#define BCHP_USB_CTRL_UTMI_CTL_1_POWER_UP_FSM_SPEED_MASK 0x00000100
-#define BCHP_USB_CTRL_UTMI_CTL_1_POWER_UP_FSM_SPEED_SHIFT 8
-#define BCHP_USB_CTRL_UTMI_CTL_1_POWER_UP_FSM_SPEED_DEFAULT 0x00000000
-
-/* USB_CTRL :: UTMI_CTL_1 :: BC10_DM_PU [07:07] */
-#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_DM_PU_MASK 0x00000080
-#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_DM_PU_SHIFT 7
-#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_DM_PU_DEFAULT 0x00000000
-
-/* USB_CTRL :: UTMI_CTL_1 :: BC10_DP_PU [06:06] */
-#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_DP_PU_MASK 0x00000040
-#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_DP_PU_SHIFT 6
-#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_DP_PU_DEFAULT 0x00000000
-
-/* USB_CTRL :: UTMI_CTL_1 :: BC10_DM_PD [05:05] */
-#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_DM_PD_MASK 0x00000020
-#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_DM_PD_SHIFT 5
-#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_DM_PD_DEFAULT 0x00000000
-
-/* USB_CTRL :: UTMI_CTL_1 :: BC10_DP_PD [04:04] */
-#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_DP_PD_MASK 0x00000010
-#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_DP_PD_SHIFT 4
-#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_DP_PD_DEFAULT 0x00000000
-
-/* USB_CTRL :: UTMI_CTL_1 :: PHY_MODE [03:02] */
-#define BCHP_USB_CTRL_UTMI_CTL_1_PHY_MODE_MASK 0x0000000c
-#define BCHP_USB_CTRL_UTMI_CTL_1_PHY_MODE_SHIFT 2
-#define BCHP_USB_CTRL_UTMI_CTL_1_PHY_MODE_DEFAULT 0x00000000
-#define BCHP_USB_CTRL_UTMI_CTL_1_PHY_MODE_Host 0
-#define BCHP_USB_CTRL_UTMI_CTL_1_PHY_MODE_Device 1
-#define BCHP_USB_CTRL_UTMI_CTL_1_PHY_MODE_OTG 2
-#define BCHP_USB_CTRL_UTMI_CTL_1_PHY_MODE_BC10 3
-
-/* USB_CTRL :: UTMI_CTL_1 :: UTMI_SOFT_RESETB [01:01] */
-#define BCHP_USB_CTRL_UTMI_CTL_1_UTMI_SOFT_RESETB_MASK 0x00000002
-#define BCHP_USB_CTRL_UTMI_CTL_1_UTMI_SOFT_RESETB_SHIFT 1
-#define BCHP_USB_CTRL_UTMI_CTL_1_UTMI_SOFT_RESETB_DEFAULT 0x00000001
-
-/* USB_CTRL :: UTMI_CTL_1 :: AFE_NON_DRIVING [00:00] */
-#define BCHP_USB_CTRL_UTMI_CTL_1_AFE_NON_DRIVING_MASK 0x00000001
-#define BCHP_USB_CTRL_UTMI_CTL_1_AFE_NON_DRIVING_SHIFT 0
-#define BCHP_USB_CTRL_UTMI_CTL_1_AFE_NON_DRIVING_DEFAULT 0x00000000
-
-/***************************************************************************
- *UTMI_CTL_2 - UTMI Control 2 Register
- ***************************************************************************/
-/* USB_CTRL :: UTMI_CTL_2 :: UTMICTL2_SPARE [31:00] */
-#define BCHP_USB_CTRL_UTMI_CTL_2_UTMICTL2_SPARE_MASK 0xffffffff
-#define BCHP_USB_CTRL_UTMI_CTL_2_UTMICTL2_SPARE_SHIFT 0
-#define BCHP_USB_CTRL_UTMI_CTL_2_UTMICTL2_SPARE_DEFAULT 0x00000000
-
-/***************************************************************************
- *USB_PM - Power Management Register
- ***************************************************************************/
-/* USB_CTRL :: USB_PM :: xdc_soft_resetb [31:31] */
-#define BCHP_USB_CTRL_USB_PM_xdc_soft_resetb_MASK 0x80000000
-#define BCHP_USB_CTRL_USB_PM_xdc_soft_resetb_SHIFT 31
-#define BCHP_USB_CTRL_USB_PM_xdc_soft_resetb_DEFAULT 0x00000000
-
-/* USB_CTRL :: USB_PM :: xhc_soft_resetb [30:30] */
-#define BCHP_USB_CTRL_USB_PM_xhc_soft_resetb_MASK 0x40000000
-#define BCHP_USB_CTRL_USB_PM_xhc_soft_resetb_SHIFT 30
-#define BCHP_USB_CTRL_USB_PM_xhc_soft_resetb_DEFAULT 0x00000000
-
-/* USB_CTRL :: USB_PM :: usb20_hc1_resetb [29:29] */
-#define BCHP_USB_CTRL_USB_PM_usb20_hc1_resetb_MASK 0x20000000
-#define BCHP_USB_CTRL_USB_PM_usb20_hc1_resetb_SHIFT 29
-#define BCHP_USB_CTRL_USB_PM_usb20_hc1_resetb_DEFAULT 0x00000001
-
-/* USB_CTRL :: USB_PM :: usb20_hc0_resetb [28:28] */
-#define BCHP_USB_CTRL_USB_PM_usb20_hc0_resetb_MASK 0x10000000
-#define BCHP_USB_CTRL_USB_PM_usb20_hc0_resetb_SHIFT 28
-#define BCHP_USB_CTRL_USB_PM_usb20_hc0_resetb_DEFAULT 0x00000001
-
-/* USB_CTRL :: USB_PM :: USB_PM_SPARE1 [27:16] */
-#define BCHP_USB_CTRL_USB_PM_USB_PM_SPARE1_MASK 0x0fff0000
-#define BCHP_USB_CTRL_USB_PM_USB_PM_SPARE1_SHIFT 16
-#define BCHP_USB_CTRL_USB_PM_USB_PM_SPARE1_DEFAULT 0x00000000
-
-/* USB_CTRL :: USB_PM :: ehci_rmtwkup_override [15:15] */
-#define BCHP_USB_CTRL_USB_PM_ehci_rmtwkup_override_MASK 0x00008000
-#define BCHP_USB_CTRL_USB_PM_ehci_rmtwkup_override_SHIFT 15
-#define BCHP_USB_CTRL_USB_PM_ehci_rmtwkup_override_DEFAULT 0x00000000
-
-/* USB_CTRL :: USB_PM :: ohci_rmtwkup_override [14:14] */
-#define BCHP_USB_CTRL_USB_PM_ohci_rmtwkup_override_MASK 0x00004000
-#define BCHP_USB_CTRL_USB_PM_ohci_rmtwkup_override_SHIFT 14
-#define BCHP_USB_CTRL_USB_PM_ohci_rmtwkup_override_DEFAULT 0x00000000
-
-/* USB_CTRL :: USB_PM :: USB_PM_SPARE [13:05] */
-#define BCHP_USB_CTRL_USB_PM_USB_PM_SPARE_MASK 0x00003fe0
-#define BCHP_USB_CTRL_USB_PM_USB_PM_SPARE_SHIFT 5
-#define BCHP_USB_CTRL_USB_PM_USB_PM_SPARE_DEFAULT 0x00000000
-
-/* USB_CTRL :: USB_PM :: xhc_pme_en [04:04] */
-#define BCHP_USB_CTRL_USB_PM_xhc_pme_en_MASK 0x00000010
-#define BCHP_USB_CTRL_USB_PM_xhc_pme_en_SHIFT 4
-#define BCHP_USB_CTRL_USB_PM_xhc_pme_en_DEFAULT 0x00000000
-
-/* USB_CTRL :: USB_PM :: S2_discon_intr_en [03:03] */
-#define BCHP_USB_CTRL_USB_PM_S2_discon_intr_en_MASK 0x00000008
-#define BCHP_USB_CTRL_USB_PM_S2_discon_intr_en_SHIFT 3
-#define BCHP_USB_CTRL_USB_PM_S2_discon_intr_en_DEFAULT 0x00000000
-
-/* USB_CTRL :: USB_PM :: S0_discon_intr_en [02:02] */
-#define BCHP_USB_CTRL_USB_PM_S0_discon_intr_en_MASK 0x00000004
-#define BCHP_USB_CTRL_USB_PM_S0_discon_intr_en_SHIFT 2
-#define BCHP_USB_CTRL_USB_PM_S0_discon_intr_en_DEFAULT 0x00000000
-
-/* USB_CTRL :: USB_PM :: con_intr_en [01:01] */
-#define BCHP_USB_CTRL_USB_PM_con_intr_en_MASK 0x00000002
-#define BCHP_USB_CTRL_USB_PM_con_intr_en_SHIFT 1
-#define BCHP_USB_CTRL_USB_PM_con_intr_en_DEFAULT 0x00000000
-
-/* USB_CTRL :: USB_PM :: rmtwkup_en [00:00] */
-#define BCHP_USB_CTRL_USB_PM_rmtwkup_en_MASK 0x00000001
-#define BCHP_USB_CTRL_USB_PM_rmtwkup_en_SHIFT 0
-#define BCHP_USB_CTRL_USB_PM_rmtwkup_en_DEFAULT 0x00000000
-
-/***************************************************************************
- *USB_PM_STATUS - usb20 Power Management Status Register
- ***************************************************************************/
-/* USB_CTRL :: USB_PM_STATUS :: SPARE1_BITS [31:16] */
-#define BCHP_USB_CTRL_USB_PM_STATUS_SPARE1_BITS_MASK 0xffff0000
-#define BCHP_USB_CTRL_USB_PM_STATUS_SPARE1_BITS_SHIFT 16
-#define BCHP_USB_CTRL_USB_PM_STATUS_SPARE1_BITS_DEFAULT 0x00000000
-
-/* USB_CTRL :: USB_PM_STATUS :: PM_STATUS [15:00] */
-#define BCHP_USB_CTRL_USB_PM_STATUS_PM_STATUS_MASK 0x0000ffff
-#define BCHP_USB_CTRL_USB_PM_STATUS_PM_STATUS_SHIFT 0
-#define BCHP_USB_CTRL_USB_PM_STATUS_PM_STATUS_DEFAULT 0x00000000
-
-/***************************************************************************
- *OHCI_ADDR_EXT - OHCI ADDRESS Extension
- ***************************************************************************/
-/* USB_CTRL :: OHCI_ADDR_EXT :: OHCI_ADDR_SPARE [31:08] */
-#define BCHP_USB_CTRL_OHCI_ADDR_EXT_OHCI_ADDR_SPARE_MASK 0xffffff00
-#define BCHP_USB_CTRL_OHCI_ADDR_EXT_OHCI_ADDR_SPARE_SHIFT 8
-#define BCHP_USB_CTRL_OHCI_ADDR_EXT_OHCI_ADDR_SPARE_DEFAULT 0x00000000
-
-/* USB_CTRL :: OHCI_ADDR_EXT :: OHCI_ADDR_EXT [07:00] */
-#define BCHP_USB_CTRL_OHCI_ADDR_EXT_OHCI_ADDR_EXT_MASK 0x000000ff
-#define BCHP_USB_CTRL_OHCI_ADDR_EXT_OHCI_ADDR_EXT_SHIFT 0
-#define BCHP_USB_CTRL_OHCI_ADDR_EXT_OHCI_ADDR_EXT_DEFAULT 0x00000000
-
-/***************************************************************************
- *PLL_LDO_CTL - 28NM USBPHY LDO Control
- ***************************************************************************/
-/* USB_CTRL :: PLL_LDO_CTL :: AFE_PLL_LDO_CNTL [31:16] */
-#define BCHP_USB_CTRL_PLL_LDO_CTL_AFE_PLL_LDO_CNTL_MASK 0xffff0000
-#define BCHP_USB_CTRL_PLL_LDO_CTL_AFE_PLL_LDO_CNTL_SHIFT 16
-#define BCHP_USB_CTRL_PLL_LDO_CTL_AFE_PLL_LDO_CNTL_DEFAULT 0x00000000
-
-/* USB_CTRL :: PLL_LDO_CTL :: DFE_LDO_CNTL [15:12] */
-#define BCHP_USB_CTRL_PLL_LDO_CTL_DFE_LDO_CNTL_MASK 0x0000f000
-#define BCHP_USB_CTRL_PLL_LDO_CTL_DFE_LDO_CNTL_SHIFT 12
-#define BCHP_USB_CTRL_PLL_LDO_CTL_DFE_LDO_CNTL_DEFAULT 0x00000000
-
-/* USB_CTRL :: PLL_LDO_CTL :: AFE_LDO_CNTL [11:08] */
-#define BCHP_USB_CTRL_PLL_LDO_CTL_AFE_LDO_CNTL_MASK 0x00000f00
-#define BCHP_USB_CTRL_PLL_LDO_CTL_AFE_LDO_CNTL_SHIFT 8
-#define BCHP_USB_CTRL_PLL_LDO_CTL_AFE_LDO_CNTL_DEFAULT 0x00000000
-
-/* USB_CTRL :: PLL_LDO_CTL :: AFE_LDO_SPARE [07:03] */
-#define BCHP_USB_CTRL_PLL_LDO_CTL_AFE_LDO_SPARE_MASK 0x000000f8
-#define BCHP_USB_CTRL_PLL_LDO_CTL_AFE_LDO_SPARE_SHIFT 3
-#define BCHP_USB_CTRL_PLL_LDO_CTL_AFE_LDO_SPARE_DEFAULT 0x00000000
-
-/* USB_CTRL :: PLL_LDO_CTL :: AFE_CORERDY_VDDC [02:02] */
-#define BCHP_USB_CTRL_PLL_LDO_CTL_AFE_CORERDY_VDDC_MASK 0x00000004
-#define BCHP_USB_CTRL_PLL_LDO_CTL_AFE_CORERDY_VDDC_SHIFT 2
-#define BCHP_USB_CTRL_PLL_LDO_CTL_AFE_CORERDY_VDDC_DEFAULT 0x00000001
-
-/* USB_CTRL :: PLL_LDO_CTL :: AFE_LDO_PWRDWNB [01:01] */
-#define BCHP_USB_CTRL_PLL_LDO_CTL_AFE_LDO_PWRDWNB_MASK 0x00000002
-#define BCHP_USB_CTRL_PLL_LDO_CTL_AFE_LDO_PWRDWNB_SHIFT 1
-#define BCHP_USB_CTRL_PLL_LDO_CTL_AFE_LDO_PWRDWNB_DEFAULT 0x00000001
-
-/* USB_CTRL :: PLL_LDO_CTL :: AFE_BG_PWRDWNB [00:00] */
-#define BCHP_USB_CTRL_PLL_LDO_CTL_AFE_BG_PWRDWNB_MASK 0x00000001
-#define BCHP_USB_CTRL_PLL_LDO_CTL_AFE_BG_PWRDWNB_SHIFT 0
-#define BCHP_USB_CTRL_PLL_LDO_CTL_AFE_BG_PWRDWNB_DEFAULT 0x00000001
-
-/***************************************************************************
- *PLL_LDO_PLLBIAS - 28NM USBPHY PLLBIAS Control
- ***************************************************************************/
-/* USB_CTRL :: PLL_LDO_PLLBIAS :: PLLBIAS_SPARE [31:18] */
-#define BCHP_USB_CTRL_PLL_LDO_PLLBIAS_PLLBIAS_SPARE_MASK 0xfffc0000
-#define BCHP_USB_CTRL_PLL_LDO_PLLBIAS_PLLBIAS_SPARE_SHIFT 18
-#define BCHP_USB_CTRL_PLL_LDO_PLLBIAS_PLLBIAS_SPARE_DEFAULT 0x00000000
-
-/* USB_CTRL :: PLL_LDO_PLLBIAS :: AFE_PLLBIAS_TESTMODE [17:00] */
-#define BCHP_USB_CTRL_PLL_LDO_PLLBIAS_AFE_PLLBIAS_TESTMODE_MASK 0x0003ffff
-#define BCHP_USB_CTRL_PLL_LDO_PLLBIAS_AFE_PLLBIAS_TESTMODE_SHIFT 0
-#define BCHP_USB_CTRL_PLL_LDO_PLLBIAS_AFE_PLLBIAS_TESTMODE_DEFAULT 0x00000000
-
-/***************************************************************************
- *PLL_AFE_BG_CNTL - 28NM USBPHY AFE Bandgap Control
- ***************************************************************************/
-/* USB_CTRL :: PLL_AFE_BG_CNTL :: PLL_AFE_BG_SPARE [31:17] */
-#define BCHP_USB_CTRL_PLL_AFE_BG_CNTL_PLL_AFE_BG_SPARE_MASK 0xfffe0000
-#define BCHP_USB_CTRL_PLL_AFE_BG_CNTL_PLL_AFE_BG_SPARE_SHIFT 17
-#define BCHP_USB_CTRL_PLL_AFE_BG_CNTL_PLL_AFE_BG_SPARE_DEFAULT 0x00000000
-
-/* USB_CTRL :: PLL_AFE_BG_CNTL :: AFE_BG_PRGM [16:12] */
-#define BCHP_USB_CTRL_PLL_AFE_BG_CNTL_AFE_BG_PRGM_MASK 0x0001f000
-#define BCHP_USB_CTRL_PLL_AFE_BG_CNTL_AFE_BG_PRGM_SHIFT 12
-#define BCHP_USB_CTRL_PLL_AFE_BG_CNTL_AFE_BG_PRGM_DEFAULT 0x00000000
-
-/* USB_CTRL :: PLL_AFE_BG_CNTL :: AFE_BG_VREF0P7_AFE_PRGM [11:08] */
-#define BCHP_USB_CTRL_PLL_AFE_BG_CNTL_AFE_BG_VREF0P7_AFE_PRGM_MASK 0x00000f00
-#define BCHP_USB_CTRL_PLL_AFE_BG_CNTL_AFE_BG_VREF0P7_AFE_PRGM_SHIFT 8
-#define BCHP_USB_CTRL_PLL_AFE_BG_CNTL_AFE_BG_VREF0P7_AFE_PRGM_DEFAULT 0x00000000
-
-/* USB_CTRL :: PLL_AFE_BG_CNTL :: AFE_BG_VREF0P7_DFE_PRGM [07:04] */
-#define BCHP_USB_CTRL_PLL_AFE_BG_CNTL_AFE_BG_VREF0P7_DFE_PRGM_MASK 0x000000f0
-#define BCHP_USB_CTRL_PLL_AFE_BG_CNTL_AFE_BG_VREF0P7_DFE_PRGM_SHIFT 4
-#define BCHP_USB_CTRL_PLL_AFE_BG_CNTL_AFE_BG_VREF0P7_DFE_PRGM_DEFAULT 0x00000000
-
-/* USB_CTRL :: PLL_AFE_BG_CNTL :: AFE_BG_VREF1P0_TRIM [03:00] */
-#define BCHP_USB_CTRL_PLL_AFE_BG_CNTL_AFE_BG_VREF1P0_TRIM_MASK 0x0000000f
-#define BCHP_USB_CTRL_PLL_AFE_BG_CNTL_AFE_BG_VREF1P0_TRIM_SHIFT 0
-#define BCHP_USB_CTRL_PLL_AFE_BG_CNTL_AFE_BG_VREF1P0_TRIM_DEFAULT 0x00000000
-
-/***************************************************************************
- *AFE_USBIO_TST - 28NM USBPHY AFE Bandgap Control
- ***************************************************************************/
-/* USB_CTRL :: AFE_USBIO_TST :: ANALOG_TESTMODE [31:31] */
-#define BCHP_USB_CTRL_AFE_USBIO_TST_ANALOG_TESTMODE_MASK 0x80000000
-#define BCHP_USB_CTRL_AFE_USBIO_TST_ANALOG_TESTMODE_SHIFT 31
-#define BCHP_USB_CTRL_AFE_USBIO_TST_ANALOG_TESTMODE_DEFAULT 0x00000000
-
-/* USB_CTRL :: AFE_USBIO_TST :: PHY_ISO [30:30] */
-#define BCHP_USB_CTRL_AFE_USBIO_TST_PHY_ISO_MASK 0x40000000
-#define BCHP_USB_CTRL_AFE_USBIO_TST_PHY_ISO_SHIFT 30
-#define BCHP_USB_CTRL_AFE_USBIO_TST_PHY_ISO_DEFAULT 0x00000000
-
-/* USB_CTRL :: AFE_USBIO_TST :: AFE_USBIO_TST_SPARE [29:16] */
-#define BCHP_USB_CTRL_AFE_USBIO_TST_AFE_USBIO_TST_SPARE_MASK 0x3fff0000
-#define BCHP_USB_CTRL_AFE_USBIO_TST_AFE_USBIO_TST_SPARE_SHIFT 16
-#define BCHP_USB_CTRL_AFE_USBIO_TST_AFE_USBIO_TST_SPARE_DEFAULT 0x00000000
-
-/* USB_CTRL :: AFE_USBIO_TST :: AFE_USBIO_TST_P2 [15:08] */
-#define BCHP_USB_CTRL_AFE_USBIO_TST_AFE_USBIO_TST_P2_MASK 0x0000ff00
-#define BCHP_USB_CTRL_AFE_USBIO_TST_AFE_USBIO_TST_P2_SHIFT 8
-#define BCHP_USB_CTRL_AFE_USBIO_TST_AFE_USBIO_TST_P2_DEFAULT 0x00000000
-
-/* USB_CTRL :: AFE_USBIO_TST :: AFE_USBIO_TST_P1 [07:00] */
-#define BCHP_USB_CTRL_AFE_USBIO_TST_AFE_USBIO_TST_P1_MASK 0x000000ff
-#define BCHP_USB_CTRL_AFE_USBIO_TST_AFE_USBIO_TST_P1_SHIFT 0
-#define BCHP_USB_CTRL_AFE_USBIO_TST_AFE_USBIO_TST_P1_DEFAULT 0x00000000
-
-/***************************************************************************
- *PLL_NDIV_FRAC - PLL Feedback Divider Control Register
- ***************************************************************************/
-/* USB_CTRL :: PLL_NDIV_FRAC :: PLL_NDIV_FRAC_SPARE2 [31:20] */
-#define BCHP_USB_CTRL_PLL_NDIV_FRAC_PLL_NDIV_FRAC_SPARE2_MASK 0xfff00000
-#define BCHP_USB_CTRL_PLL_NDIV_FRAC_PLL_NDIV_FRAC_SPARE2_SHIFT 20
-#define BCHP_USB_CTRL_PLL_NDIV_FRAC_PLL_NDIV_FRAC_SPARE2_DEFAULT 0x00000000
-
-/* USB_CTRL :: PLL_NDIV_FRAC :: pll_ndiv_frac [19:00] */
-#define BCHP_USB_CTRL_PLL_NDIV_FRAC_pll_ndiv_frac_MASK 0x000fffff
-#define BCHP_USB_CTRL_PLL_NDIV_FRAC_pll_ndiv_frac_SHIFT 0
-#define BCHP_USB_CTRL_PLL_NDIV_FRAC_pll_ndiv_frac_DEFAULT 0x00000000
-
-/***************************************************************************
- *TP_DIAG - diagnostic for tp bus
- ***************************************************************************/
-/* USB_CTRL :: TP_DIAG :: TP_DIAG_BITS [31:00] */
-#define BCHP_USB_CTRL_TP_DIAG_TP_DIAG_BITS_MASK 0xffffffff
-#define BCHP_USB_CTRL_TP_DIAG_TP_DIAG_BITS_SHIFT 0
-#define BCHP_USB_CTRL_TP_DIAG_TP_DIAG_BITS_DEFAULT 0x00000000
-
-/***************************************************************************
- *SPARE3 - Spare1 Register for future use
- ***************************************************************************/
-/* USB_CTRL :: SPARE3 :: SPARE3_BITS [31:00] */
-#define BCHP_USB_CTRL_SPARE3_SPARE3_BITS_MASK 0xffffffff
-#define BCHP_USB_CTRL_SPARE3_SPARE3_BITS_SHIFT 0
-#define BCHP_USB_CTRL_SPARE3_SPARE3_BITS_DEFAULT 0x00000000
-
-/***************************************************************************
- *SPARE4 - Spare1 Register for future use
- ***************************************************************************/
-/* USB_CTRL :: SPARE4 :: SPARE4_BITS [31:00] */
-#define BCHP_USB_CTRL_SPARE4_SPARE4_BITS_MASK 0xffffffff
-#define BCHP_USB_CTRL_SPARE4_SPARE4_BITS_SHIFT 0
-#define BCHP_USB_CTRL_SPARE4_SPARE4_BITS_DEFAULT 0x00000000
-
-/***************************************************************************
- *USB30_CTL1 - USB30 CONTROL Register 1
- ***************************************************************************/
-/* USB_CTRL :: USB30_CTL1 :: usb30_ctl1_spare2 [31:22] */
-#define BCHP_USB_CTRL_USB30_CTL1_usb30_ctl1_spare2_MASK 0xffc00000
-#define BCHP_USB_CTRL_USB30_CTL1_usb30_ctl1_spare2_SHIFT 22
-#define BCHP_USB_CTRL_USB30_CTL1_usb30_ctl1_spare2_DEFAULT 0x00000000
-
-/* USB_CTRL :: USB30_CTL1 :: usb30_sspll_suspend_en [21:21] */
-#define BCHP_USB_CTRL_USB30_CTL1_usb30_sspll_suspend_en_MASK 0x00200000
-#define BCHP_USB_CTRL_USB30_CTL1_usb30_sspll_suspend_en_SHIFT 21
-#define BCHP_USB_CTRL_USB30_CTL1_usb30_sspll_suspend_en_DEFAULT 0x00000000
-
-/* USB_CTRL :: USB30_CTL1 :: usb30_pipe_resetb [20:20] */
-#define BCHP_USB_CTRL_USB30_CTL1_usb30_pipe_resetb_MASK 0x00100000
-#define BCHP_USB_CTRL_USB30_CTL1_usb30_pipe_resetb_SHIFT 20
-#define BCHP_USB_CTRL_USB30_CTL1_usb30_pipe_resetb_DEFAULT 0x00000001
-
-/* USB_CTRL :: USB30_CTL1 :: mdio_resetb [19:19] */
-#define BCHP_USB_CTRL_USB30_CTL1_mdio_resetb_MASK 0x00080000
-#define BCHP_USB_CTRL_USB30_CTL1_mdio_resetb_SHIFT 19
-#define BCHP_USB_CTRL_USB30_CTL1_mdio_resetb_DEFAULT 0x00000001
-
-/* USB_CTRL :: USB30_CTL1 :: aux_resetb [18:18] */
-#define BCHP_USB_CTRL_USB30_CTL1_aux_resetb_MASK 0x00040000
-#define BCHP_USB_CTRL_USB30_CTL1_aux_resetb_SHIFT 18
-#define BCHP_USB_CTRL_USB30_CTL1_aux_resetb_DEFAULT 0x00000000
-
-/* USB_CTRL :: USB30_CTL1 :: cdr_reset [17:17] */
-#define BCHP_USB_CTRL_USB30_CTL1_cdr_reset_MASK 0x00020000
-#define BCHP_USB_CTRL_USB30_CTL1_cdr_reset_SHIFT 17
-#define BCHP_USB_CTRL_USB30_CTL1_cdr_reset_DEFAULT 0x00000000
-
-/* USB_CTRL :: USB30_CTL1 :: phy3_resetb [16:16] */
-#define BCHP_USB_CTRL_USB30_CTL1_phy3_resetb_MASK 0x00010000
-#define BCHP_USB_CTRL_USB30_CTL1_phy3_resetb_SHIFT 16
-#define BCHP_USB_CTRL_USB30_CTL1_phy3_resetb_DEFAULT 0x00000001
-
-/* USB_CTRL :: USB30_CTL1 :: usb30_ctl1_spare1 [15:07] */
-#define BCHP_USB_CTRL_USB30_CTL1_usb30_ctl1_spare1_MASK 0x0000ff80
-#define BCHP_USB_CTRL_USB30_CTL1_usb30_ctl1_spare1_SHIFT 7
-#define BCHP_USB_CTRL_USB30_CTL1_usb30_ctl1_spare1_DEFAULT 0x00000000
-
-/* USB_CTRL :: USB30_CTL1 :: phy3_standalonemode [06:06] */
-#define BCHP_USB_CTRL_USB30_CTL1_phy3_standalonemode_MASK 0x00000040
-#define BCHP_USB_CTRL_USB30_CTL1_phy3_standalonemode_SHIFT 6
-#define BCHP_USB_CTRL_USB30_CTL1_phy3_standalonemode_DEFAULT 0x00000000
-
-/* USB_CTRL :: USB30_CTL1 :: phy3_phy_iso [05:05] */
-#define BCHP_USB_CTRL_USB30_CTL1_phy3_phy_iso_MASK 0x00000020
-#define BCHP_USB_CTRL_USB30_CTL1_phy3_phy_iso_SHIFT 5
-#define BCHP_USB_CTRL_USB30_CTL1_phy3_phy_iso_DEFAULT 0x00000000
-
-/* USB_CTRL :: USB30_CTL1 :: phy3_pll_seq_start [04:04] */
-#define BCHP_USB_CTRL_USB30_CTL1_phy3_pll_seq_start_MASK 0x00000010
-#define BCHP_USB_CTRL_USB30_CTL1_phy3_pll_seq_start_SHIFT 4
-#define BCHP_USB_CTRL_USB30_CTL1_phy3_pll_seq_start_DEFAULT 0x00000000
-
-/* USB_CTRL :: USB30_CTL1 :: phy3_pll_refclk_sel [03:01] */
-#define BCHP_USB_CTRL_USB30_CTL1_phy3_pll_refclk_sel_MASK 0x0000000e
-#define BCHP_USB_CTRL_USB30_CTL1_phy3_pll_refclk_sel_SHIFT 1
-#define BCHP_USB_CTRL_USB30_CTL1_phy3_pll_refclk_sel_DEFAULT 0x00000004
-#define BCHP_USB_CTRL_USB30_CTL1_phy3_pll_refclk_sel_CML_Refclk 0
-#define BCHP_USB_CTRL_USB30_CTL1_phy3_pll_refclk_sel_XTAL 1
-#define BCHP_USB_CTRL_USB30_CTL1_phy3_pll_refclk_sel_REFCLKP_N 2
-#define BCHP_USB_CTRL_USB30_CTL1_phy3_pll_refclk_sel_REFCLKP_N_with_Termination 3
-#define BCHP_USB_CTRL_USB30_CTL1_phy3_pll_refclk_sel_Cmos_Refclk 4
-
-/* USB_CTRL :: USB30_CTL1 :: phy3_pll_auxclk_sel [00:00] */
-#define BCHP_USB_CTRL_USB30_CTL1_phy3_pll_auxclk_sel_MASK 0x00000001
-#define BCHP_USB_CTRL_USB30_CTL1_phy3_pll_auxclk_sel_SHIFT 0
-#define BCHP_USB_CTRL_USB30_CTL1_phy3_pll_auxclk_sel_DEFAULT 0x00000000
-
-/***************************************************************************
- *USB30_CTL2 - USB30 CONTROL Register 2
- ***************************************************************************/
-/* USB_CTRL :: USB30_CTL2 :: usb30_ctl2_spare2 [31:30] */
-#define BCHP_USB_CTRL_USB30_CTL2_usb30_ctl2_spare2_MASK 0xc0000000
-#define BCHP_USB_CTRL_USB30_CTL2_usb30_ctl2_spare2_SHIFT 30
-#define BCHP_USB_CTRL_USB30_CTL2_usb30_ctl2_spare2_DEFAULT 0x00000000
-
-/* USB_CTRL :: USB30_CTL2 :: xhci_max_scb_size [29:24] */
-#define BCHP_USB_CTRL_USB30_CTL2_xhci_max_scb_size_MASK 0x3f000000
-#define BCHP_USB_CTRL_USB30_CTL2_xhci_max_scb_size_SHIFT 24
-#define BCHP_USB_CTRL_USB30_CTL2_xhci_max_scb_size_DEFAULT 0x00000020
-
-/* USB_CTRL :: USB30_CTL2 :: xhci_wrfifo_thrshld [23:16] */
-#define BCHP_USB_CTRL_USB30_CTL2_xhci_wrfifo_thrshld_MASK 0x00ff0000
-#define BCHP_USB_CTRL_USB30_CTL2_xhci_wrfifo_thrshld_SHIFT 16
-#define BCHP_USB_CTRL_USB30_CTL2_xhci_wrfifo_thrshld_DEFAULT 0x00000000
-
-/* USB_CTRL :: USB30_CTL2 :: xhci_rdfifo_thrshld [15:08] */
-#define BCHP_USB_CTRL_USB30_CTL2_xhci_rdfifo_thrshld_MASK 0x0000ff00
-#define BCHP_USB_CTRL_USB30_CTL2_xhci_rdfifo_thrshld_SHIFT 8
-#define BCHP_USB_CTRL_USB30_CTL2_xhci_rdfifo_thrshld_DEFAULT 0x00000000
-
-/* USB_CTRL :: USB30_CTL2 :: usb30_ctl2_spare1 [07:03] */
-#define BCHP_USB_CTRL_USB30_CTL2_usb30_ctl2_spare1_MASK 0x000000f8
-#define BCHP_USB_CTRL_USB30_CTL2_usb30_ctl2_spare1_SHIFT 3
-#define BCHP_USB_CTRL_USB30_CTL2_usb30_ctl2_spare1_DEFAULT 0x00000000
-
-/* USB_CTRL :: USB30_CTL2 :: xhci_cntl_client_en [02:02] */
-#define BCHP_USB_CTRL_USB30_CTL2_xhci_cntl_client_en_MASK 0x00000004
-#define BCHP_USB_CTRL_USB30_CTL2_xhci_cntl_client_en_SHIFT 2
-#define BCHP_USB_CTRL_USB30_CTL2_xhci_cntl_client_en_DEFAULT 0x00000001
-
-/* USB_CTRL :: USB30_CTL2 :: xhci_swap_mode [01:00] */
-#define BCHP_USB_CTRL_USB30_CTL2_xhci_swap_mode_MASK 0x00000003
-#define BCHP_USB_CTRL_USB30_CTL2_xhci_swap_mode_SHIFT 0
-#define BCHP_USB_CTRL_USB30_CTL2_xhci_swap_mode_DEFAULT 0x00000000
-
-/***************************************************************************
- *USB30_CTL3 - USB30 CONTROL Register 3
- ***************************************************************************/
-/* USB_CTRL :: USB30_CTL3 :: usb30_ctl3_spare2 [31:30] */
-#define BCHP_USB_CTRL_USB30_CTL3_usb30_ctl3_spare2_MASK 0xc0000000
-#define BCHP_USB_CTRL_USB30_CTL3_usb30_ctl3_spare2_SHIFT 30
-#define BCHP_USB_CTRL_USB30_CTL3_usb30_ctl3_spare2_DEFAULT 0x00000000
-
-/* USB_CTRL :: USB30_CTL3 :: phy3_pipe_txdeemph_en_p1 [29:29] */
-#define BCHP_USB_CTRL_USB30_CTL3_phy3_pipe_txdeemph_en_p1_MASK 0x20000000
-#define BCHP_USB_CTRL_USB30_CTL3_phy3_pipe_txdeemph_en_p1_SHIFT 29
-#define BCHP_USB_CTRL_USB30_CTL3_phy3_pipe_txdeemph_en_p1_DEFAULT 0x00000000
-
-/* USB_CTRL :: USB30_CTL3 :: phy3_pipe_txdeemph_p1 [28:24] */
-#define BCHP_USB_CTRL_USB30_CTL3_phy3_pipe_txdeemph_p1_MASK 0x1f000000
-#define BCHP_USB_CTRL_USB30_CTL3_phy3_pipe_txdeemph_p1_SHIFT 24
-#define BCHP_USB_CTRL_USB30_CTL3_phy3_pipe_txdeemph_p1_DEFAULT 0x00000009
-
-/* USB_CTRL :: USB30_CTL3 :: phy3_pipe_txmargin_p1 [23:20] */
-#define BCHP_USB_CTRL_USB30_CTL3_phy3_pipe_txmargin_p1_MASK 0x00f00000
-#define BCHP_USB_CTRL_USB30_CTL3_phy3_pipe_txmargin_p1_SHIFT 20
-#define BCHP_USB_CTRL_USB30_CTL3_phy3_pipe_txmargin_p1_DEFAULT 0x00000007
-
-/* USB_CTRL :: USB30_CTL3 :: phy3_rxebufmode_p1 [19:19] */
-#define BCHP_USB_CTRL_USB30_CTL3_phy3_rxebufmode_p1_MASK 0x00080000
-#define BCHP_USB_CTRL_USB30_CTL3_phy3_rxebufmode_p1_SHIFT 19
-#define BCHP_USB_CTRL_USB30_CTL3_phy3_rxebufmode_p1_DEFAULT 0x00000000
-
-/* USB_CTRL :: USB30_CTL3 :: phy3_pipe_txmargin_en_p1 [18:18] */
-#define BCHP_USB_CTRL_USB30_CTL3_phy3_pipe_txmargin_en_p1_MASK 0x00040000
-#define BCHP_USB_CTRL_USB30_CTL3_phy3_pipe_txmargin_en_p1_SHIFT 18
-#define BCHP_USB_CTRL_USB30_CTL3_phy3_pipe_txmargin_en_p1_DEFAULT 0x00000000
-
-/* USB_CTRL :: USB30_CTL3 :: phy3_pipe_txswing_p1 [17:17] */
-#define BCHP_USB_CTRL_USB30_CTL3_phy3_pipe_txswing_p1_MASK 0x00020000
-#define BCHP_USB_CTRL_USB30_CTL3_phy3_pipe_txswing_p1_SHIFT 17
-#define BCHP_USB_CTRL_USB30_CTL3_phy3_pipe_txswing_p1_DEFAULT 0x00000000
-
-/* USB_CTRL :: USB30_CTL3 :: phy3_pipe_mode_p1 [16:16] */
-#define BCHP_USB_CTRL_USB30_CTL3_phy3_pipe_mode_p1_MASK 0x00010000
-#define BCHP_USB_CTRL_USB30_CTL3_phy3_pipe_mode_p1_SHIFT 16
-#define BCHP_USB_CTRL_USB30_CTL3_phy3_pipe_mode_p1_DEFAULT 0x00000001
-
-/* USB_CTRL :: USB30_CTL3 :: usb30_ctl3_spare1 [15:14] */
-#define BCHP_USB_CTRL_USB30_CTL3_usb30_ctl3_spare1_MASK 0x0000c000
-#define BCHP_USB_CTRL_USB30_CTL3_usb30_ctl3_spare1_SHIFT 14
-#define BCHP_USB_CTRL_USB30_CTL3_usb30_ctl3_spare1_DEFAULT 0x00000000
-
-/* USB_CTRL :: USB30_CTL3 :: phy3_pipe_txdeemph_en [13:13] */
-#define BCHP_USB_CTRL_USB30_CTL3_phy3_pipe_txdeemph_en_MASK 0x00002000
-#define BCHP_USB_CTRL_USB30_CTL3_phy3_pipe_txdeemph_en_SHIFT 13
-#define BCHP_USB_CTRL_USB30_CTL3_phy3_pipe_txdeemph_en_DEFAULT 0x00000000
-
-/* USB_CTRL :: USB30_CTL3 :: phy3_pipe_txdeemph [12:08] */
-#define BCHP_USB_CTRL_USB30_CTL3_phy3_pipe_txdeemph_MASK 0x00001f00
-#define BCHP_USB_CTRL_USB30_CTL3_phy3_pipe_txdeemph_SHIFT 8
-#define BCHP_USB_CTRL_USB30_CTL3_phy3_pipe_txdeemph_DEFAULT 0x00000009
-
-/* USB_CTRL :: USB30_CTL3 :: phy3_pipe_txmargin [07:04] */
-#define BCHP_USB_CTRL_USB30_CTL3_phy3_pipe_txmargin_MASK 0x000000f0
-#define BCHP_USB_CTRL_USB30_CTL3_phy3_pipe_txmargin_SHIFT 4
-#define BCHP_USB_CTRL_USB30_CTL3_phy3_pipe_txmargin_DEFAULT 0x00000007
-
-/* USB_CTRL :: USB30_CTL3 :: phy3_rxebufmode [03:03] */
-#define BCHP_USB_CTRL_USB30_CTL3_phy3_rxebufmode_MASK 0x00000008
-#define BCHP_USB_CTRL_USB30_CTL3_phy3_rxebufmode_SHIFT 3
-#define BCHP_USB_CTRL_USB30_CTL3_phy3_rxebufmode_DEFAULT 0x00000000
-
-/* USB_CTRL :: USB30_CTL3 :: phy3_pipe_txmargin_en [02:02] */
-#define BCHP_USB_CTRL_USB30_CTL3_phy3_pipe_txmargin_en_MASK 0x00000004
-#define BCHP_USB_CTRL_USB30_CTL3_phy3_pipe_txmargin_en_SHIFT 2
-#define BCHP_USB_CTRL_USB30_CTL3_phy3_pipe_txmargin_en_DEFAULT 0x00000000
-
-/* USB_CTRL :: USB30_CTL3 :: phy3_pipe_txswing [01:01] */
-#define BCHP_USB_CTRL_USB30_CTL3_phy3_pipe_txswing_MASK 0x00000002
-#define BCHP_USB_CTRL_USB30_CTL3_phy3_pipe_txswing_SHIFT 1
-#define BCHP_USB_CTRL_USB30_CTL3_phy3_pipe_txswing_DEFAULT 0x00000000
-
-/* USB_CTRL :: USB30_CTL3 :: phy3_pipe_mode [00:00] */
-#define BCHP_USB_CTRL_USB30_CTL3_phy3_pipe_mode_MASK 0x00000001
-#define BCHP_USB_CTRL_USB30_CTL3_phy3_pipe_mode_SHIFT 0
-#define BCHP_USB_CTRL_USB30_CTL3_phy3_pipe_mode_DEFAULT 0x00000001
-
-/***************************************************************************
- *USB30_CTL4 - USB30 CONTROL Register 4
- ***************************************************************************/
-/* USB_CTRL :: USB30_CTL4 :: usb30_ctl4_spare1 [31:24] */
-#define BCHP_USB_CTRL_USB30_CTL4_usb30_ctl4_spare1_MASK 0xff000000
-#define BCHP_USB_CTRL_USB30_CTL4_usb30_ctl4_spare1_SHIFT 24
-#define BCHP_USB_CTRL_USB30_CTL4_usb30_ctl4_spare1_DEFAULT 0x00000000
-
-/* USB_CTRL :: USB30_CTL4 :: phy3_tpout_sel [23:16] */
-#define BCHP_USB_CTRL_USB30_CTL4_phy3_tpout_sel_MASK 0x00ff0000
-#define BCHP_USB_CTRL_USB30_CTL4_phy3_tpout_sel_SHIFT 16
-#define BCHP_USB_CTRL_USB30_CTL4_phy3_tpout_sel_DEFAULT 0x00000000
-
-/* USB_CTRL :: USB30_CTL4 :: xhci_tpout_sel [15:00] */
-#define BCHP_USB_CTRL_USB30_CTL4_xhci_tpout_sel_MASK 0x0000ffff
-#define BCHP_USB_CTRL_USB30_CTL4_xhci_tpout_sel_SHIFT 0
-#define BCHP_USB_CTRL_USB30_CTL4_xhci_tpout_sel_DEFAULT 0x00000000
-
-/***************************************************************************
- *USB30_PCTL - USB30 PORT CONTROL Register
- ***************************************************************************/
-/* USB_CTRL :: USB30_PCTL :: USB3_PCTL_SPARE2 [31:29] */
-#define BCHP_USB_CTRL_USB30_PCTL_USB3_PCTL_SPARE2_MASK 0xe0000000
-#define BCHP_USB_CTRL_USB30_PCTL_USB3_PCTL_SPARE2_SHIFT 29
-#define BCHP_USB_CTRL_USB30_PCTL_USB3_PCTL_SPARE2_DEFAULT 0x00000000
-
-/* USB_CTRL :: USB30_PCTL :: PHY3_BYP_CLKMUX_P1 [28:28] */
-#define BCHP_USB_CTRL_USB30_PCTL_PHY3_BYP_CLKMUX_P1_MASK 0x10000000
-#define BCHP_USB_CTRL_USB30_PCTL_PHY3_BYP_CLKMUX_P1_SHIFT 28
-#define BCHP_USB_CTRL_USB30_PCTL_PHY3_BYP_CLKMUX_P1_DEFAULT 0x00000001
-
-/* USB_CTRL :: USB30_PCTL :: PHY3_PIPE_PWRDWN_OVERRIDE_EN_P1 [27:27] */
-#define BCHP_USB_CTRL_USB30_PCTL_PHY3_PIPE_PWRDWN_OVERRIDE_EN_P1_MASK 0x08000000
-#define BCHP_USB_CTRL_USB30_PCTL_PHY3_PIPE_PWRDWN_OVERRIDE_EN_P1_SHIFT 27
-#define BCHP_USB_CTRL_USB30_PCTL_PHY3_PIPE_PWRDWN_OVERRIDE_EN_P1_DEFAULT 0x00000000
-
-/* USB_CTRL :: USB30_PCTL :: PHY3_PIPE_PWRDWN_OVERRIDE_VALUE_P1 [26:25] */
-#define BCHP_USB_CTRL_USB30_PCTL_PHY3_PIPE_PWRDWN_OVERRIDE_VALUE_P1_MASK 0x06000000
-#define BCHP_USB_CTRL_USB30_PCTL_PHY3_PIPE_PWRDWN_OVERRIDE_VALUE_P1_SHIFT 25
-#define BCHP_USB_CTRL_USB30_PCTL_PHY3_PIPE_PWRDWN_OVERRIDE_VALUE_P1_DEFAULT 0x00000000
-
-/* USB_CTRL :: USB30_PCTL :: PHY3_TX_RxDetOut_OVERRIDE_P1 [24:24] */
-#define BCHP_USB_CTRL_USB30_PCTL_PHY3_TX_RxDetOut_OVERRIDE_P1_MASK 0x01000000
-#define BCHP_USB_CTRL_USB30_PCTL_PHY3_TX_RxDetOut_OVERRIDE_P1_SHIFT 24
-#define BCHP_USB_CTRL_USB30_PCTL_PHY3_TX_RxDetOut_OVERRIDE_P1_DEFAULT 0x00000000
-
-/* USB_CTRL :: USB30_PCTL :: PHY3_TX_ElecIdle_OVERRIDE_P1 [23:23] */
-#define BCHP_USB_CTRL_USB30_PCTL_PHY3_TX_ElecIdle_OVERRIDE_P1_MASK 0x00800000
-#define BCHP_USB_CTRL_USB30_PCTL_PHY3_TX_ElecIdle_OVERRIDE_P1_SHIFT 23
-#define BCHP_USB_CTRL_USB30_PCTL_PHY3_TX_ElecIdle_OVERRIDE_P1_DEFAULT 0x00000000
-
-/* USB_CTRL :: USB30_PCTL :: PHY3_TX_RxDetReq_OVERRIDE_P1 [22:22] */
-#define BCHP_USB_CTRL_USB30_PCTL_PHY3_TX_RxDetReq_OVERRIDE_P1_MASK 0x00400000
-#define BCHP_USB_CTRL_USB30_PCTL_PHY3_TX_RxDetReq_OVERRIDE_P1_SHIFT 22
-#define BCHP_USB_CTRL_USB30_PCTL_PHY3_TX_RxDetReq_OVERRIDE_P1_DEFAULT 0x00000000
-
-/* USB_CTRL :: USB30_PCTL :: PHY3_TX_PD_OVERRIDE_P1 [21:21] */
-#define BCHP_USB_CTRL_USB30_PCTL_PHY3_TX_PD_OVERRIDE_P1_MASK 0x00200000
-#define BCHP_USB_CTRL_USB30_PCTL_PHY3_TX_PD_OVERRIDE_P1_SHIFT 21
-#define BCHP_USB_CTRL_USB30_PCTL_PHY3_TX_PD_OVERRIDE_P1_DEFAULT 0x00000000
-
-/* USB_CTRL :: USB30_PCTL :: PHY3_RX_PD_OVERRIDE_P1 [20:20] */
-#define BCHP_USB_CTRL_USB30_PCTL_PHY3_RX_PD_OVERRIDE_P1_MASK 0x00100000
-#define BCHP_USB_CTRL_USB30_PCTL_PHY3_RX_PD_OVERRIDE_P1_SHIFT 20
-#define BCHP_USB_CTRL_USB30_PCTL_PHY3_RX_PD_OVERRIDE_P1_DEFAULT 0x00000000
-
-/* USB_CTRL :: USB30_PCTL :: PHY3_MODE_P1 [19:18] */
-#define BCHP_USB_CTRL_USB30_PCTL_PHY3_MODE_P1_MASK 0x000c0000
-#define BCHP_USB_CTRL_USB30_PCTL_PHY3_MODE_P1_SHIFT 18
-#define BCHP_USB_CTRL_USB30_PCTL_PHY3_MODE_P1_DEFAULT 0x00000000
-
-/* USB_CTRL :: USB30_PCTL :: PHY3_SOFT_RESETB_P1 [17:17] */
-#define BCHP_USB_CTRL_USB30_PCTL_PHY3_SOFT_RESETB_P1_MASK 0x00020000
-#define BCHP_USB_CTRL_USB30_PCTL_PHY3_SOFT_RESETB_P1_SHIFT 17
-#define BCHP_USB_CTRL_USB30_PCTL_PHY3_SOFT_RESETB_P1_DEFAULT 0x00000001
-
-/* USB_CTRL :: USB30_PCTL :: PHY3_AFE_NON_DRIVING_P1 [16:16] */
-#define BCHP_USB_CTRL_USB30_PCTL_PHY3_AFE_NON_DRIVING_P1_MASK 0x00010000
-#define BCHP_USB_CTRL_USB30_PCTL_PHY3_AFE_NON_DRIVING_P1_SHIFT 16
-#define BCHP_USB_CTRL_USB30_PCTL_PHY3_AFE_NON_DRIVING_P1_DEFAULT 0x00000000
-
-/* USB_CTRL :: USB30_PCTL :: PHY3_IDDQ_OVERRIDE [15:15] */
-#define BCHP_USB_CTRL_USB30_PCTL_PHY3_IDDQ_OVERRIDE_MASK 0x00008000
-#define BCHP_USB_CTRL_USB30_PCTL_PHY3_IDDQ_OVERRIDE_SHIFT 15
-#define BCHP_USB_CTRL_USB30_PCTL_PHY3_IDDQ_OVERRIDE_DEFAULT 0x00000000
-
-/* USB_CTRL :: USB30_PCTL :: USB3_PCTL_SPARE1 [14:13] */
-#define BCHP_USB_CTRL_USB30_PCTL_USB3_PCTL_SPARE1_MASK 0x00006000
-#define BCHP_USB_CTRL_USB30_PCTL_USB3_PCTL_SPARE1_SHIFT 13
-#define BCHP_USB_CTRL_USB30_PCTL_USB3_PCTL_SPARE1_DEFAULT 0x00000000
-
-/* USB_CTRL :: USB30_PCTL :: PHY3_BYP_CLKMUX [12:12] */
-#define BCHP_USB_CTRL_USB30_PCTL_PHY3_BYP_CLKMUX_MASK 0x00001000
-#define BCHP_USB_CTRL_USB30_PCTL_PHY3_BYP_CLKMUX_SHIFT 12
-#define BCHP_USB_CTRL_USB30_PCTL_PHY3_BYP_CLKMUX_DEFAULT 0x00000001
-
-/* USB_CTRL :: USB30_PCTL :: PHY3_PIPE_PWRDWN_OVERRIDE_EN [11:11] */
-#define BCHP_USB_CTRL_USB30_PCTL_PHY3_PIPE_PWRDWN_OVERRIDE_EN_MASK 0x00000800
-#define BCHP_USB_CTRL_USB30_PCTL_PHY3_PIPE_PWRDWN_OVERRIDE_EN_SHIFT 11
-#define BCHP_USB_CTRL_USB30_PCTL_PHY3_PIPE_PWRDWN_OVERRIDE_EN_DEFAULT 0x00000000
-
-/* USB_CTRL :: USB30_PCTL :: PHY3_PIPE_PWRDWN_OVERRIDE_VALUE [10:09] */
-#define BCHP_USB_CTRL_USB30_PCTL_PHY3_PIPE_PWRDWN_OVERRIDE_VALUE_MASK 0x00000600
-#define BCHP_USB_CTRL_USB30_PCTL_PHY3_PIPE_PWRDWN_OVERRIDE_VALUE_SHIFT 9
-#define BCHP_USB_CTRL_USB30_PCTL_PHY3_PIPE_PWRDWN_OVERRIDE_VALUE_DEFAULT 0x00000000
-
-/* USB_CTRL :: USB30_PCTL :: PHY3_TX_RxDetOut_OVERRIDE [08:08] */
-#define BCHP_USB_CTRL_USB30_PCTL_PHY3_TX_RxDetOut_OVERRIDE_MASK 0x00000100
-#define BCHP_USB_CTRL_USB30_PCTL_PHY3_TX_RxDetOut_OVERRIDE_SHIFT 8
-#define BCHP_USB_CTRL_USB30_PCTL_PHY3_TX_RxDetOut_OVERRIDE_DEFAULT 0x00000000
-
-/* USB_CTRL :: USB30_PCTL :: PHY3_TX_ElecIdle_OVERRIDE [07:07] */
-#define BCHP_USB_CTRL_USB30_PCTL_PHY3_TX_ElecIdle_OVERRIDE_MASK 0x00000080
-#define BCHP_USB_CTRL_USB30_PCTL_PHY3_TX_ElecIdle_OVERRIDE_SHIFT 7
-#define BCHP_USB_CTRL_USB30_PCTL_PHY3_TX_ElecIdle_OVERRIDE_DEFAULT 0x00000000
-
-/* USB_CTRL :: USB30_PCTL :: PHY3_TX_RxDetReq_OVERRIDE [06:06] */
-#define BCHP_USB_CTRL_USB30_PCTL_PHY3_TX_RxDetReq_OVERRIDE_MASK 0x00000040
-#define BCHP_USB_CTRL_USB30_PCTL_PHY3_TX_RxDetReq_OVERRIDE_SHIFT 6
-#define BCHP_USB_CTRL_USB30_PCTL_PHY3_TX_RxDetReq_OVERRIDE_DEFAULT 0x00000000
-
-/* USB_CTRL :: USB30_PCTL :: PHY3_TX_PD_OVERRIDE [05:05] */
-#define BCHP_USB_CTRL_USB30_PCTL_PHY3_TX_PD_OVERRIDE_MASK 0x00000020
-#define BCHP_USB_CTRL_USB30_PCTL_PHY3_TX_PD_OVERRIDE_SHIFT 5
-#define BCHP_USB_CTRL_USB30_PCTL_PHY3_TX_PD_OVERRIDE_DEFAULT 0x00000000
-
-/* USB_CTRL :: USB30_PCTL :: PHY3_RX_PD_OVERRIDE [04:04] */
-#define BCHP_USB_CTRL_USB30_PCTL_PHY3_RX_PD_OVERRIDE_MASK 0x00000010
-#define BCHP_USB_CTRL_USB30_PCTL_PHY3_RX_PD_OVERRIDE_SHIFT 4
-#define BCHP_USB_CTRL_USB30_PCTL_PHY3_RX_PD_OVERRIDE_DEFAULT 0x00000000
-
-/* USB_CTRL :: USB30_PCTL :: PHY3_MODE [03:02] */
-#define BCHP_USB_CTRL_USB30_PCTL_PHY3_MODE_MASK 0x0000000c
-#define BCHP_USB_CTRL_USB30_PCTL_PHY3_MODE_SHIFT 2
-#define BCHP_USB_CTRL_USB30_PCTL_PHY3_MODE_DEFAULT 0x00000000
-
-/* USB_CTRL :: USB30_PCTL :: PHY3_SOFT_RESETB [01:01] */
-#define BCHP_USB_CTRL_USB30_PCTL_PHY3_SOFT_RESETB_MASK 0x00000002
-#define BCHP_USB_CTRL_USB30_PCTL_PHY3_SOFT_RESETB_SHIFT 1
-#define BCHP_USB_CTRL_USB30_PCTL_PHY3_SOFT_RESETB_DEFAULT 0x00000001
-
-/* USB_CTRL :: USB30_PCTL :: PHY3_AFE_NON_DRIVING [00:00] */
-#define BCHP_USB_CTRL_USB30_PCTL_PHY3_AFE_NON_DRIVING_MASK 0x00000001
-#define BCHP_USB_CTRL_USB30_PCTL_PHY3_AFE_NON_DRIVING_SHIFT 0
-#define BCHP_USB_CTRL_USB30_PCTL_PHY3_AFE_NON_DRIVING_DEFAULT 0x00000000
-
-/***************************************************************************
- *USB30_CTL5 - USB30 CONTROL Register 5
- ***************************************************************************/
-/* USB_CTRL :: USB30_CTL5 :: USB30_CTL5 [31:00] */
-#define BCHP_USB_CTRL_USB30_CTL5_USB30_CTL5_MASK 0xffffffff
-#define BCHP_USB_CTRL_USB30_CTL5_USB30_CTL5_SHIFT 0
-#define BCHP_USB_CTRL_USB30_CTL5_USB30_CTL5_DEFAULT 0x00000000
-
-/***************************************************************************
- *SPARE5 - Spare1 Register for future use
- ***************************************************************************/
-/* USB_CTRL :: SPARE5 :: SPARE5_BITS [31:00] */
-#define BCHP_USB_CTRL_SPARE5_SPARE5_BITS_MASK 0xffffffff
-#define BCHP_USB_CTRL_SPARE5_SPARE5_BITS_SHIFT 0
-#define BCHP_USB_CTRL_SPARE5_SPARE5_BITS_DEFAULT 0x00000000
-
-/***************************************************************************
- *SPARE6 - Spare2 Register for future use
- ***************************************************************************/
-/* USB_CTRL :: SPARE6 :: SPARE6_BITS [31:00] */
-#define BCHP_USB_CTRL_SPARE6_SPARE6_BITS_MASK 0xffffffff
-#define BCHP_USB_CTRL_SPARE6_SPARE6_BITS_SHIFT 0
-#define BCHP_USB_CTRL_SPARE6_SPARE6_BITS_DEFAULT 0x00000000
-
-/***************************************************************************
- *SCB0_BASE_RANGE - SCB0 base start and end address
- ***************************************************************************/
-/* USB_CTRL :: SCB0_BASE_RANGE :: SCB0_BASE_SPARE_BITS [31:24] */
-#define BCHP_USB_CTRL_SCB0_BASE_RANGE_SCB0_BASE_SPARE_BITS_MASK 0xff000000
-#define BCHP_USB_CTRL_SCB0_BASE_RANGE_SCB0_BASE_SPARE_BITS_SHIFT 24
-#define BCHP_USB_CTRL_SCB0_BASE_RANGE_SCB0_BASE_SPARE_BITS_DEFAULT 0x00000000
-
-/* USB_CTRL :: SCB0_BASE_RANGE :: SCB0_BASE_END_ADDR [23:12] */
-#define BCHP_USB_CTRL_SCB0_BASE_RANGE_SCB0_BASE_END_ADDR_MASK 0x00fff000
-#define BCHP_USB_CTRL_SCB0_BASE_RANGE_SCB0_BASE_END_ADDR_SHIFT 12
-#define BCHP_USB_CTRL_SCB0_BASE_RANGE_SCB0_BASE_END_ADDR_DEFAULT 0x00000007
-
-/* USB_CTRL :: SCB0_BASE_RANGE :: SCB0_BASE_START_ADDR [11:00] */
-#define BCHP_USB_CTRL_SCB0_BASE_RANGE_SCB0_BASE_START_ADDR_MASK 0x00000fff
-#define BCHP_USB_CTRL_SCB0_BASE_RANGE_SCB0_BASE_START_ADDR_SHIFT 0
-#define BCHP_USB_CTRL_SCB0_BASE_RANGE_SCB0_BASE_START_ADDR_DEFAULT 0x00000000
-
-/***************************************************************************
- *SCB1_BASE_RANGE - SCB1 base start and end address
- ***************************************************************************/
-/* USB_CTRL :: SCB1_BASE_RANGE :: SCB1_BASE_SPARE_BITS [31:24] */
-#define BCHP_USB_CTRL_SCB1_BASE_RANGE_SCB1_BASE_SPARE_BITS_MASK 0xff000000
-#define BCHP_USB_CTRL_SCB1_BASE_RANGE_SCB1_BASE_SPARE_BITS_SHIFT 24
-#define BCHP_USB_CTRL_SCB1_BASE_RANGE_SCB1_BASE_SPARE_BITS_DEFAULT 0x00000000
-
-/* USB_CTRL :: SCB1_BASE_RANGE :: SCB1_BASE_END_ADDR [23:12] */
-#define BCHP_USB_CTRL_SCB1_BASE_RANGE_SCB1_BASE_END_ADDR_MASK 0x00fff000
-#define BCHP_USB_CTRL_SCB1_BASE_RANGE_SCB1_BASE_END_ADDR_SHIFT 12
-#define BCHP_USB_CTRL_SCB1_BASE_RANGE_SCB1_BASE_END_ADDR_DEFAULT 0x0000000b
-
-/* USB_CTRL :: SCB1_BASE_RANGE :: SCB1_BASE_START_ADDR [11:00] */
-#define BCHP_USB_CTRL_SCB1_BASE_RANGE_SCB1_BASE_START_ADDR_MASK 0x00000fff
-#define BCHP_USB_CTRL_SCB1_BASE_RANGE_SCB1_BASE_START_ADDR_SHIFT 0
-#define BCHP_USB_CTRL_SCB1_BASE_RANGE_SCB1_BASE_START_ADDR_DEFAULT 0x00000008
-
-/***************************************************************************
- *SCB2_BASE_RANGE - SCB2 base start and end address
- ***************************************************************************/
-/* USB_CTRL :: SCB2_BASE_RANGE :: SCB2_BASE_SPARE_BITS [31:24] */
-#define BCHP_USB_CTRL_SCB2_BASE_RANGE_SCB2_BASE_SPARE_BITS_MASK 0xff000000
-#define BCHP_USB_CTRL_SCB2_BASE_RANGE_SCB2_BASE_SPARE_BITS_SHIFT 24
-#define BCHP_USB_CTRL_SCB2_BASE_RANGE_SCB2_BASE_SPARE_BITS_DEFAULT 0x00000000
-
-/* USB_CTRL :: SCB2_BASE_RANGE :: SCB2_BASE_END_ADDR [23:12] */
-#define BCHP_USB_CTRL_SCB2_BASE_RANGE_SCB2_BASE_END_ADDR_MASK 0x00fff000
-#define BCHP_USB_CTRL_SCB2_BASE_RANGE_SCB2_BASE_END_ADDR_SHIFT 12
-#define BCHP_USB_CTRL_SCB2_BASE_RANGE_SCB2_BASE_END_ADDR_DEFAULT 0x0000000b
-
-/* USB_CTRL :: SCB2_BASE_RANGE :: SCB2_BASE_START_ADDR [11:00] */
-#define BCHP_USB_CTRL_SCB2_BASE_RANGE_SCB2_BASE_START_ADDR_MASK 0x00000fff
-#define BCHP_USB_CTRL_SCB2_BASE_RANGE_SCB2_BASE_START_ADDR_SHIFT 0
-#define BCHP_USB_CTRL_SCB2_BASE_RANGE_SCB2_BASE_START_ADDR_DEFAULT 0x00000008
-
-/***************************************************************************
- *SCB0_EXTN_RANGE - SCB0 extn start and end address
- ***************************************************************************/
-/* USB_CTRL :: SCB0_EXTN_RANGE :: SCB0_EXTN_SPARE_BITS [31:24] */
-#define BCHP_USB_CTRL_SCB0_EXTN_RANGE_SCB0_EXTN_SPARE_BITS_MASK 0xff000000
-#define BCHP_USB_CTRL_SCB0_EXTN_RANGE_SCB0_EXTN_SPARE_BITS_SHIFT 24
-#define BCHP_USB_CTRL_SCB0_EXTN_RANGE_SCB0_EXTN_SPARE_BITS_DEFAULT 0x00000000
-
-/* USB_CTRL :: SCB0_EXTN_RANGE :: SCB0_EXTN_END_ADDR [23:12] */
-#define BCHP_USB_CTRL_SCB0_EXTN_RANGE_SCB0_EXTN_END_ADDR_MASK 0x00fff000
-#define BCHP_USB_CTRL_SCB0_EXTN_RANGE_SCB0_EXTN_END_ADDR_SHIFT 12
-#define BCHP_USB_CTRL_SCB0_EXTN_RANGE_SCB0_EXTN_END_ADDR_DEFAULT 0x00000017
-
-/* USB_CTRL :: SCB0_EXTN_RANGE :: SCB0_EXTN_START_ADDR [11:00] */
-#define BCHP_USB_CTRL_SCB0_EXTN_RANGE_SCB0_EXTN_START_ADDR_MASK 0x00000fff
-#define BCHP_USB_CTRL_SCB0_EXTN_RANGE_SCB0_EXTN_START_ADDR_SHIFT 0
-#define BCHP_USB_CTRL_SCB0_EXTN_RANGE_SCB0_EXTN_START_ADDR_DEFAULT 0x00000010
-
-/***************************************************************************
- *SCB1_EXTN_RANGE - SCB1 extn start and end address
- ***************************************************************************/
-/* USB_CTRL :: SCB1_EXTN_RANGE :: SCB1_EXTN_SPARE_BITS [31:24] */
-#define BCHP_USB_CTRL_SCB1_EXTN_RANGE_SCB1_EXTN_SPARE_BITS_MASK 0xff000000
-#define BCHP_USB_CTRL_SCB1_EXTN_RANGE_SCB1_EXTN_SPARE_BITS_SHIFT 24
-#define BCHP_USB_CTRL_SCB1_EXTN_RANGE_SCB1_EXTN_SPARE_BITS_DEFAULT 0x00000000
-
-/* USB_CTRL :: SCB1_EXTN_RANGE :: SCB1_EXTN_END_ADDR [23:12] */
-#define BCHP_USB_CTRL_SCB1_EXTN_RANGE_SCB1_EXTN_END_ADDR_MASK 0x00fff000
-#define BCHP_USB_CTRL_SCB1_EXTN_RANGE_SCB1_EXTN_END_ADDR_SHIFT 12
-#define BCHP_USB_CTRL_SCB1_EXTN_RANGE_SCB1_EXTN_END_ADDR_DEFAULT 0x0000003b
-
-/* USB_CTRL :: SCB1_EXTN_RANGE :: SCB1_EXTN_START_ADDR [11:00] */
-#define BCHP_USB_CTRL_SCB1_EXTN_RANGE_SCB1_EXTN_START_ADDR_MASK 0x00000fff
-#define BCHP_USB_CTRL_SCB1_EXTN_RANGE_SCB1_EXTN_START_ADDR_SHIFT 0
-#define BCHP_USB_CTRL_SCB1_EXTN_RANGE_SCB1_EXTN_START_ADDR_DEFAULT 0x00000030
-
-/***************************************************************************
- *SCB2_EXTN_RANGE - SCB2 extn start and end address
- ***************************************************************************/
-/* USB_CTRL :: SCB2_EXTN_RANGE :: SCB2_EXTN_SPARE_BITS [31:24] */
-#define BCHP_USB_CTRL_SCB2_EXTN_RANGE_SCB2_EXTN_SPARE_BITS_MASK 0xff000000
-#define BCHP_USB_CTRL_SCB2_EXTN_RANGE_SCB2_EXTN_SPARE_BITS_SHIFT 24
-#define BCHP_USB_CTRL_SCB2_EXTN_RANGE_SCB2_EXTN_SPARE_BITS_DEFAULT 0x00000000
-
-/* USB_CTRL :: SCB2_EXTN_RANGE :: SCB2_EXTN_END_ADDR [23:12] */
-#define BCHP_USB_CTRL_SCB2_EXTN_RANGE_SCB2_EXTN_END_ADDR_MASK 0x00fff000
-#define BCHP_USB_CTRL_SCB2_EXTN_RANGE_SCB2_EXTN_END_ADDR_SHIFT 12
-#define BCHP_USB_CTRL_SCB2_EXTN_RANGE_SCB2_EXTN_END_ADDR_DEFAULT 0x000000cb
-
-/* USB_CTRL :: SCB2_EXTN_RANGE :: SCB2_EXTN_START_ADDR [11:00] */
-#define BCHP_USB_CTRL_SCB2_EXTN_RANGE_SCB2_EXTN_START_ADDR_MASK 0x00000fff
-#define BCHP_USB_CTRL_SCB2_EXTN_RANGE_SCB2_EXTN_START_ADDR_SHIFT 0
-#define BCHP_USB_CTRL_SCB2_EXTN_RANGE_SCB2_EXTN_START_ADDR_DEFAULT 0x000000c0
-
-/***************************************************************************
- *USB_REVID - USB REVID
- ***************************************************************************/
-/* USB_CTRL :: USB_REVID :: USB_REVID [31:00] */
-#define BCHP_USB_CTRL_USB_REVID_USB_REVID_MASK 0xffffffff
-#define BCHP_USB_CTRL_USB_REVID_USB_REVID_SHIFT 0
-#define BCHP_USB_CTRL_USB_REVID_USB_REVID_DEFAULT 0x00000001
-
-#endif /* #ifndef BCHP_USB_CTRL_H__ */
-
-/* End of File */
diff --git a/include/linux/brcmstb/7366b0/bchp_xpt_bus_if.h b/include/linux/brcmstb/7366b0/bchp_xpt_bus_if.h
deleted file mode 100644
index e0a70c8..0000000
--- a/include/linux/brcmstb/7366b0/bchp_xpt_bus_if.h
+++ /dev/null
@@ -1,738 +0,0 @@
-/***************************************************************************
- * Copyright (c) 1999-2014, Broadcom Corporation
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
- *
- * Module Description:
- * DO NOT EDIT THIS FILE DIRECTLY
- *
- * This module was generated magically with RDB from a source description
- * file. You must edit the source file for changes to be made to this file.
- *
- *
- * Date: Generated on Sat Apr 12 03:17:56 2014
- * Full Compile MD5 Checksum 5f2af4819d5a3039f3fe1938baf5d1f2
- * (minus title and desc)
- * MD5 Checksum afc8344db5db4960ac3645d27d001fbc
- *
- * Compiled with: RDB Utility combo_header.pl
- * RDB Parser 3.0
- * unknown unknown
- * Perl Interpreter 5.008008
- * Operating System linux
- *
- * Revision History:
- *
- * $brcm_Log: $
- *
- ***************************************************************************/
-
-#ifndef BCHP_XPT_BUS_IF_H__
-#define BCHP_XPT_BUS_IF_H__
-
-/***************************************************************************
- *XPT_BUS_IF - Data Transport Configuration Registers
- ***************************************************************************/
-#define BCHP_XPT_BUS_IF_MISC_CTRL0 0x00a00080 /* Data Transport Misc Control 0 Register */
-#define BCHP_XPT_BUS_IF_TEST_MODE 0x00a00084 /* Data transport test register */
-#define BCHP_XPT_BUS_IF_REVISION 0x00a00088 /* Data Transport Revision Register */
-#define BCHP_XPT_BUS_IF_INTR_STATUS_REG 0x00a0008c /* Interrupt Status Register */
-#define BCHP_XPT_BUS_IF_INTR_STATUS_REG_EN 0x00a00090 /* Interrupt Status Enable Register */
-#define BCHP_XPT_BUS_IF_INTR_STATUS2_REG 0x00a00094 /* Interrupt Status2 Register */
-#define BCHP_XPT_BUS_IF_INTR_STATUS2_REG_EN 0x00a00098 /* Interrupt Status2 Enable Register */
-#define BCHP_XPT_BUS_IF_INTR_STATUS3_REG 0x00a0009c /* Interrupt Status3 Register */
-#define BCHP_XPT_BUS_IF_INTR_STATUS3_REG_EN 0x00a000a0 /* Interrupt Status3 Enable Register */
-#define BCHP_XPT_BUS_IF_INTR_STATUS4_REG 0x00a000a4 /* Interrupt Status4 Register */
-#define BCHP_XPT_BUS_IF_INTR_STATUS4_REG_EN 0x00a000a8 /* Interrupt Status4 Enable Register */
-#define BCHP_XPT_BUS_IF_INTR_STATUS5_REG 0x00a000ac /* Interrupt Status5 Register */
-#define BCHP_XPT_BUS_IF_INTR_STATUS5_REG_EN 0x00a000b0 /* Interrupt Status5 Enable Register */
-#define BCHP_XPT_BUS_IF_SUB_MODULE_SOFT_INIT_SET 0x00a000b4 /* Software initialization control for XPT sub-blocks */
-#define BCHP_XPT_BUS_IF_SUB_MODULE_SOFT_INIT_CLEAR 0x00a000b8 /* Software initialization control for XPT sub-blocks */
-#define BCHP_XPT_BUS_IF_SUB_MODULE_SOFT_INIT_STATUS 0x00a000bc /* Software initialization control for XPT sub-blocks */
-#define BCHP_XPT_BUS_IF_SUB_MODULE_SOFT_INIT_DO_MEM_INIT 0x00a000c0 /* Software initialization control for XPT sub-blocks */
-#define BCHP_XPT_BUS_IF_XMEMIF_RD_LC_DEBUG_REG_0 0x00a000cc /* LCIF to XMEMIF Debug Registers */
-#define BCHP_XPT_BUS_IF_XMEMIF_WR_LC_DEBUG_REG 0x00a000d0 /* LCIF to XMEMIF Debug Registers */
-#define BCHP_XPT_BUS_IF_MAX_PLAYBACKS 0x00a000d4 /* Data Transport max number of playbacks supported */
-#define BCHP_XPT_BUS_IF_MAX_PID_PARSERS 0x00a000d8 /* Data Transport max number of PID parsers supported */
-#define BCHP_XPT_BUS_IF_MAX_PID_CHANNELS 0x00a000dc /* Data Transport max number of PID channels supported excluding MEMDMA */
-#define BCHP_XPT_BUS_IF_MEMDMA_MAX_PID_CHANNELS 0x00a000e0 /* Data Transport max number of PID channels supported for MEMDMA */
-#define BCHP_XPT_BUS_IF_MAX_INPUT_BANDS 0x00a000e4 /* Data Transport max number of input bands supported */
-#define BCHP_XPT_BUS_IF_MAX_PCRS 0x00a000e8 /* Data Transport max number of PCRs supported */
-#define BCHP_XPT_BUS_IF_MAX_TPIT_CHANNELS 0x00a000ec /* Data Transport max number of TPIT channels supported */
-#define BCHP_XPT_BUS_IF_MAX_RAVE_CONTEXTS 0x00a000f0 /* Data Transport max number of RAVE contexts supported */
-#define BCHP_XPT_BUS_IF_MAX_RMX_CHANNELS 0x00a000f4 /* Data Transport max number of RMX channels supported */
-#define BCHP_XPT_BUS_IF_MAX_MSG_BUFFERS 0x00a000f8 /* Data Transport max number of MSG buffers supported */
-#define BCHP_XPT_BUS_IF_MAX_SCDS 0x00a000fc /* Data Transport max number of SCDs supported */
-
-/***************************************************************************
- *MISC_CTRL0 - Data Transport Misc Control 0 Register
- ***************************************************************************/
-/* XPT_BUS_IF :: MISC_CTRL0 :: reserved0 [31:07] */
-#define BCHP_XPT_BUS_IF_MISC_CTRL0_reserved0_MASK 0xffffff80
-#define BCHP_XPT_BUS_IF_MISC_CTRL0_reserved0_SHIFT 7
-
-/* XPT_BUS_IF :: MISC_CTRL0 :: XPT_COUNTER_SCF [06:05] */
-#define BCHP_XPT_BUS_IF_MISC_CTRL0_XPT_COUNTER_SCF_MASK 0x00000060
-#define BCHP_XPT_BUS_IF_MISC_CTRL0_XPT_COUNTER_SCF_SHIFT 5
-#define BCHP_XPT_BUS_IF_MISC_CTRL0_XPT_COUNTER_SCF_DEFAULT 0x00000003
-#define BCHP_XPT_BUS_IF_MISC_CTRL0_XPT_COUNTER_SCF_108MHz 0
-#define BCHP_XPT_BUS_IF_MISC_CTRL0_XPT_COUNTER_SCF_216MHz 1
-#define BCHP_XPT_BUS_IF_MISC_CTRL0_XPT_COUNTER_SCF_270MHz 2
-#define BCHP_XPT_BUS_IF_MISC_CTRL0_XPT_COUNTER_SCF_324MHz 3
-
-/* XPT_BUS_IF :: MISC_CTRL0 :: reserved1 [04:03] */
-#define BCHP_XPT_BUS_IF_MISC_CTRL0_reserved1_MASK 0x00000018
-#define BCHP_XPT_BUS_IF_MISC_CTRL0_reserved1_SHIFT 3
-
-/* XPT_BUS_IF :: MISC_CTRL0 :: ERROR_INT_TEST_MODE [02:02] */
-#define BCHP_XPT_BUS_IF_MISC_CTRL0_ERROR_INT_TEST_MODE_MASK 0x00000004
-#define BCHP_XPT_BUS_IF_MISC_CTRL0_ERROR_INT_TEST_MODE_SHIFT 2
-#define BCHP_XPT_BUS_IF_MISC_CTRL0_ERROR_INT_TEST_MODE_DEFAULT 0x00000000
-
-/* XPT_BUS_IF :: MISC_CTRL0 :: MPOD_INT_TEST_MODE [01:01] */
-#define BCHP_XPT_BUS_IF_MISC_CTRL0_MPOD_INT_TEST_MODE_MASK 0x00000002
-#define BCHP_XPT_BUS_IF_MISC_CTRL0_MPOD_INT_TEST_MODE_SHIFT 1
-#define BCHP_XPT_BUS_IF_MISC_CTRL0_MPOD_INT_TEST_MODE_DEFAULT 0x00000000
-
-/* XPT_BUS_IF :: MISC_CTRL0 :: LINK_LIST_DESC_ENDIAN_CTRL [00:00] */
-#define BCHP_XPT_BUS_IF_MISC_CTRL0_LINK_LIST_DESC_ENDIAN_CTRL_MASK 0x00000001
-#define BCHP_XPT_BUS_IF_MISC_CTRL0_LINK_LIST_DESC_ENDIAN_CTRL_SHIFT 0
-#define BCHP_XPT_BUS_IF_MISC_CTRL0_LINK_LIST_DESC_ENDIAN_CTRL_DEFAULT 0x00000000
-
-/***************************************************************************
- *TEST_MODE - Data transport test register
- ***************************************************************************/
-/* XPT_BUS_IF :: TEST_MODE :: reserved0 [31:01] */
-#define BCHP_XPT_BUS_IF_TEST_MODE_reserved0_MASK 0xfffffffe
-#define BCHP_XPT_BUS_IF_TEST_MODE_reserved0_SHIFT 1
-
-/* XPT_BUS_IF :: TEST_MODE :: PSG_SECRET_ENBLE [00:00] */
-#define BCHP_XPT_BUS_IF_TEST_MODE_PSG_SECRET_ENBLE_MASK 0x00000001
-#define BCHP_XPT_BUS_IF_TEST_MODE_PSG_SECRET_ENBLE_SHIFT 0
-#define BCHP_XPT_BUS_IF_TEST_MODE_PSG_SECRET_ENBLE_DEFAULT 0x00000000
-
-/***************************************************************************
- *REVISION - Data Transport Revision Register
- ***************************************************************************/
-/* XPT_BUS_IF :: REVISION :: reserved0 [31:16] */
-#define BCHP_XPT_BUS_IF_REVISION_reserved0_MASK 0xffff0000
-#define BCHP_XPT_BUS_IF_REVISION_reserved0_SHIFT 16
-
-/* XPT_BUS_IF :: REVISION :: MAJOR_REV_NUMBER [15:08] */
-#define BCHP_XPT_BUS_IF_REVISION_MAJOR_REV_NUMBER_MASK 0x0000ff00
-#define BCHP_XPT_BUS_IF_REVISION_MAJOR_REV_NUMBER_SHIFT 8
-#define BCHP_XPT_BUS_IF_REVISION_MAJOR_REV_NUMBER_DEFAULT 0x00000040
-
-/* XPT_BUS_IF :: REVISION :: MINOR_REV_NUMBER [07:00] */
-#define BCHP_XPT_BUS_IF_REVISION_MINOR_REV_NUMBER_MASK 0x000000ff
-#define BCHP_XPT_BUS_IF_REVISION_MINOR_REV_NUMBER_SHIFT 0
-
-/***************************************************************************
- *INTR_STATUS_REG - Interrupt Status Register
- ***************************************************************************/
-/* XPT_BUS_IF :: INTR_STATUS_REG :: reserved0 [31:28] */
-#define BCHP_XPT_BUS_IF_INTR_STATUS_REG_reserved0_MASK 0xf0000000
-#define BCHP_XPT_BUS_IF_INTR_STATUS_REG_reserved0_SHIFT 28
-
-/* XPT_BUS_IF :: INTR_STATUS_REG :: RSBUFF_TB_ERR_INTR [27:27] */
-#define BCHP_XPT_BUS_IF_INTR_STATUS_REG_RSBUFF_TB_ERR_INTR_MASK 0x08000000
-#define BCHP_XPT_BUS_IF_INTR_STATUS_REG_RSBUFF_TB_ERR_INTR_SHIFT 27
-#define BCHP_XPT_BUS_IF_INTR_STATUS_REG_RSBUFF_TB_ERR_INTR_DEFAULT 0x00000000
-
-/* XPT_BUS_IF :: INTR_STATUS_REG :: RSBUFF_PTR_OOR_INTR [26:26] */
-#define BCHP_XPT_BUS_IF_INTR_STATUS_REG_RSBUFF_PTR_OOR_INTR_MASK 0x04000000
-#define BCHP_XPT_BUS_IF_INTR_STATUS_REG_RSBUFF_PTR_OOR_INTR_SHIFT 26
-#define BCHP_XPT_BUS_IF_INTR_STATUS_REG_RSBUFF_PTR_OOR_INTR_DEFAULT 0x00000000
-
-/* XPT_BUS_IF :: INTR_STATUS_REG :: XCBUFF_PTR_OOR_INTR [25:25] */
-#define BCHP_XPT_BUS_IF_INTR_STATUS_REG_XCBUFF_PTR_OOR_INTR_MASK 0x02000000
-#define BCHP_XPT_BUS_IF_INTR_STATUS_REG_XCBUFF_PTR_OOR_INTR_SHIFT 25
-#define BCHP_XPT_BUS_IF_INTR_STATUS_REG_XCBUFF_PTR_OOR_INTR_DEFAULT 0x00000000
-
-/* XPT_BUS_IF :: INTR_STATUS_REG :: RSBUFF_OVERFLFLOW_INTR [24:24] */
-#define BCHP_XPT_BUS_IF_INTR_STATUS_REG_RSBUFF_OVERFLFLOW_INTR_MASK 0x01000000
-#define BCHP_XPT_BUS_IF_INTR_STATUS_REG_RSBUFF_OVERFLFLOW_INTR_SHIFT 24
-#define BCHP_XPT_BUS_IF_INTR_STATUS_REG_RSBUFF_OVERFLFLOW_INTR_DEFAULT 0x00000000
-
-/* XPT_BUS_IF :: INTR_STATUS_REG :: XCBUFF_OVERFLOW_INTR [23:23] */
-#define BCHP_XPT_BUS_IF_INTR_STATUS_REG_XCBUFF_OVERFLOW_INTR_MASK 0x00800000
-#define BCHP_XPT_BUS_IF_INTR_STATUS_REG_XCBUFF_OVERFLOW_INTR_SHIFT 23
-#define BCHP_XPT_BUS_IF_INTR_STATUS_REG_XCBUFF_OVERFLOW_INTR_DEFAULT 0x00000000
-
-/* XPT_BUS_IF :: INTR_STATUS_REG :: reserved1 [22:00] */
-#define BCHP_XPT_BUS_IF_INTR_STATUS_REG_reserved1_MASK 0x007fffff
-#define BCHP_XPT_BUS_IF_INTR_STATUS_REG_reserved1_SHIFT 0
-
-/***************************************************************************
- *INTR_STATUS_REG_EN - Interrupt Status Enable Register
- ***************************************************************************/
-/* XPT_BUS_IF :: INTR_STATUS_REG_EN :: reserved0 [31:28] */
-#define BCHP_XPT_BUS_IF_INTR_STATUS_REG_EN_reserved0_MASK 0xf0000000
-#define BCHP_XPT_BUS_IF_INTR_STATUS_REG_EN_reserved0_SHIFT 28
-
-/* XPT_BUS_IF :: INTR_STATUS_REG_EN :: RSBUFF_TB_ERR_INTR_EN [27:27] */
-#define BCHP_XPT_BUS_IF_INTR_STATUS_REG_EN_RSBUFF_TB_ERR_INTR_EN_MASK 0x08000000
-#define BCHP_XPT_BUS_IF_INTR_STATUS_REG_EN_RSBUFF_TB_ERR_INTR_EN_SHIFT 27
-#define BCHP_XPT_BUS_IF_INTR_STATUS_REG_EN_RSBUFF_TB_ERR_INTR_EN_DEFAULT 0x00000000
-
-/* XPT_BUS_IF :: INTR_STATUS_REG_EN :: RSBUFF_PTR_OOR_INTR_EN [26:26] */
-#define BCHP_XPT_BUS_IF_INTR_STATUS_REG_EN_RSBUFF_PTR_OOR_INTR_EN_MASK 0x04000000
-#define BCHP_XPT_BUS_IF_INTR_STATUS_REG_EN_RSBUFF_PTR_OOR_INTR_EN_SHIFT 26
-#define BCHP_XPT_BUS_IF_INTR_STATUS_REG_EN_RSBUFF_PTR_OOR_INTR_EN_DEFAULT 0x00000000
-
-/* XPT_BUS_IF :: INTR_STATUS_REG_EN :: XCBUFF_PTR_OOR_INTR_EN [25:25] */
-#define BCHP_XPT_BUS_IF_INTR_STATUS_REG_EN_XCBUFF_PTR_OOR_INTR_EN_MASK 0x02000000
-#define BCHP_XPT_BUS_IF_INTR_STATUS_REG_EN_XCBUFF_PTR_OOR_INTR_EN_SHIFT 25
-#define BCHP_XPT_BUS_IF_INTR_STATUS_REG_EN_XCBUFF_PTR_OOR_INTR_EN_DEFAULT 0x00000000
-
-/* XPT_BUS_IF :: INTR_STATUS_REG_EN :: RSBUFF_OVERFLFLOW_INTR_EN [24:24] */
-#define BCHP_XPT_BUS_IF_INTR_STATUS_REG_EN_RSBUFF_OVERFLFLOW_INTR_EN_MASK 0x01000000
-#define BCHP_XPT_BUS_IF_INTR_STATUS_REG_EN_RSBUFF_OVERFLFLOW_INTR_EN_SHIFT 24
-#define BCHP_XPT_BUS_IF_INTR_STATUS_REG_EN_RSBUFF_OVERFLFLOW_INTR_EN_DEFAULT 0x00000000
-
-/* XPT_BUS_IF :: INTR_STATUS_REG_EN :: XCBUFF_OVERFLOW_INTR_EN [23:23] */
-#define BCHP_XPT_BUS_IF_INTR_STATUS_REG_EN_XCBUFF_OVERFLOW_INTR_EN_MASK 0x00800000
-#define BCHP_XPT_BUS_IF_INTR_STATUS_REG_EN_XCBUFF_OVERFLOW_INTR_EN_SHIFT 23
-#define BCHP_XPT_BUS_IF_INTR_STATUS_REG_EN_XCBUFF_OVERFLOW_INTR_EN_DEFAULT 0x00000000
-
-/* XPT_BUS_IF :: INTR_STATUS_REG_EN :: reserved1 [22:00] */
-#define BCHP_XPT_BUS_IF_INTR_STATUS_REG_EN_reserved1_MASK 0x007fffff
-#define BCHP_XPT_BUS_IF_INTR_STATUS_REG_EN_reserved1_SHIFT 0
-
-/***************************************************************************
- *INTR_STATUS2_REG - Interrupt Status2 Register
- ***************************************************************************/
-/* XPT_BUS_IF :: INTR_STATUS2_REG :: reserved0 [31:03] */
-#define BCHP_XPT_BUS_IF_INTR_STATUS2_REG_reserved0_MASK 0xfffffff8
-#define BCHP_XPT_BUS_IF_INTR_STATUS2_REG_reserved0_SHIFT 3
-
-/* XPT_BUS_IF :: INTR_STATUS2_REG :: CA_ERR_INT [02:02] */
-#define BCHP_XPT_BUS_IF_INTR_STATUS2_REG_CA_ERR_INT_MASK 0x00000004
-#define BCHP_XPT_BUS_IF_INTR_STATUS2_REG_CA_ERR_INT_SHIFT 2
-#define BCHP_XPT_BUS_IF_INTR_STATUS2_REG_CA_ERR_INT_DEFAULT 0x00000000
-
-/* XPT_BUS_IF :: INTR_STATUS2_REG :: CP_DEC_ERR_INT [01:01] */
-#define BCHP_XPT_BUS_IF_INTR_STATUS2_REG_CP_DEC_ERR_INT_MASK 0x00000002
-#define BCHP_XPT_BUS_IF_INTR_STATUS2_REG_CP_DEC_ERR_INT_SHIFT 1
-#define BCHP_XPT_BUS_IF_INTR_STATUS2_REG_CP_DEC_ERR_INT_DEFAULT 0x00000000
-
-/* XPT_BUS_IF :: INTR_STATUS2_REG :: CP_ENC_ERR_INT [00:00] */
-#define BCHP_XPT_BUS_IF_INTR_STATUS2_REG_CP_ENC_ERR_INT_MASK 0x00000001
-#define BCHP_XPT_BUS_IF_INTR_STATUS2_REG_CP_ENC_ERR_INT_SHIFT 0
-#define BCHP_XPT_BUS_IF_INTR_STATUS2_REG_CP_ENC_ERR_INT_DEFAULT 0x00000000
-
-/***************************************************************************
- *INTR_STATUS2_REG_EN - Interrupt Status2 Enable Register
- ***************************************************************************/
-/* XPT_BUS_IF :: INTR_STATUS2_REG_EN :: reserved0 [31:03] */
-#define BCHP_XPT_BUS_IF_INTR_STATUS2_REG_EN_reserved0_MASK 0xfffffff8
-#define BCHP_XPT_BUS_IF_INTR_STATUS2_REG_EN_reserved0_SHIFT 3
-
-/* XPT_BUS_IF :: INTR_STATUS2_REG_EN :: CA_ERR_INT_EN [02:02] */
-#define BCHP_XPT_BUS_IF_INTR_STATUS2_REG_EN_CA_ERR_INT_EN_MASK 0x00000004
-#define BCHP_XPT_BUS_IF_INTR_STATUS2_REG_EN_CA_ERR_INT_EN_SHIFT 2
-#define BCHP_XPT_BUS_IF_INTR_STATUS2_REG_EN_CA_ERR_INT_EN_DEFAULT 0x00000000
-
-/* XPT_BUS_IF :: INTR_STATUS2_REG_EN :: CP_DEC_ERR_INT_EN [01:01] */
-#define BCHP_XPT_BUS_IF_INTR_STATUS2_REG_EN_CP_DEC_ERR_INT_EN_MASK 0x00000002
-#define BCHP_XPT_BUS_IF_INTR_STATUS2_REG_EN_CP_DEC_ERR_INT_EN_SHIFT 1
-#define BCHP_XPT_BUS_IF_INTR_STATUS2_REG_EN_CP_DEC_ERR_INT_EN_DEFAULT 0x00000000
-
-/* XPT_BUS_IF :: INTR_STATUS2_REG_EN :: CP_ENC_ERR_INT_EN [00:00] */
-#define BCHP_XPT_BUS_IF_INTR_STATUS2_REG_EN_CP_ENC_ERR_INT_EN_MASK 0x00000001
-#define BCHP_XPT_BUS_IF_INTR_STATUS2_REG_EN_CP_ENC_ERR_INT_EN_SHIFT 0
-#define BCHP_XPT_BUS_IF_INTR_STATUS2_REG_EN_CP_ENC_ERR_INT_EN_DEFAULT 0x00000000
-
-/***************************************************************************
- *INTR_STATUS3_REG - Interrupt Status3 Register
- ***************************************************************************/
-/* XPT_BUS_IF :: INTR_STATUS3_REG :: reserved0 [31:01] */
-#define BCHP_XPT_BUS_IF_INTR_STATUS3_REG_reserved0_MASK 0xfffffffe
-#define BCHP_XPT_BUS_IF_INTR_STATUS3_REG_reserved0_SHIFT 1
-
-/* XPT_BUS_IF :: INTR_STATUS3_REG :: MPOD_EXTRACTOR_CRC_ERROR [00:00] */
-#define BCHP_XPT_BUS_IF_INTR_STATUS3_REG_MPOD_EXTRACTOR_CRC_ERROR_MASK 0x00000001
-#define BCHP_XPT_BUS_IF_INTR_STATUS3_REG_MPOD_EXTRACTOR_CRC_ERROR_SHIFT 0
-#define BCHP_XPT_BUS_IF_INTR_STATUS3_REG_MPOD_EXTRACTOR_CRC_ERROR_DEFAULT 0x00000000
-
-/***************************************************************************
- *INTR_STATUS3_REG_EN - Interrupt Status3 Enable Register
- ***************************************************************************/
-/* XPT_BUS_IF :: INTR_STATUS3_REG_EN :: reserved0 [31:01] */
-#define BCHP_XPT_BUS_IF_INTR_STATUS3_REG_EN_reserved0_MASK 0xfffffffe
-#define BCHP_XPT_BUS_IF_INTR_STATUS3_REG_EN_reserved0_SHIFT 1
-
-/* XPT_BUS_IF :: INTR_STATUS3_REG_EN :: MPOD_EXTRACTOR_CRC_ERROR_EN [00:00] */
-#define BCHP_XPT_BUS_IF_INTR_STATUS3_REG_EN_MPOD_EXTRACTOR_CRC_ERROR_EN_MASK 0x00000001
-#define BCHP_XPT_BUS_IF_INTR_STATUS3_REG_EN_MPOD_EXTRACTOR_CRC_ERROR_EN_SHIFT 0
-#define BCHP_XPT_BUS_IF_INTR_STATUS3_REG_EN_MPOD_EXTRACTOR_CRC_ERROR_EN_DEFAULT 0x00000000
-
-/***************************************************************************
- *INTR_STATUS4_REG - Interrupt Status4 Register
- ***************************************************************************/
-/* XPT_BUS_IF :: INTR_STATUS4_REG :: reserved0 [31:28] */
-#define BCHP_XPT_BUS_IF_INTR_STATUS4_REG_reserved0_MASK 0xf0000000
-#define BCHP_XPT_BUS_IF_INTR_STATUS4_REG_reserved0_SHIFT 28
-
-/* XPT_BUS_IF :: INTR_STATUS4_REG :: GISB_BRIDGE [27:27] */
-#define BCHP_XPT_BUS_IF_INTR_STATUS4_REG_GISB_BRIDGE_MASK 0x08000000
-#define BCHP_XPT_BUS_IF_INTR_STATUS4_REG_GISB_BRIDGE_SHIFT 27
-#define BCHP_XPT_BUS_IF_INTR_STATUS4_REG_GISB_BRIDGE_DEFAULT 0x00000000
-
-/* XPT_BUS_IF :: INTR_STATUS4_REG :: reserved1 [26:16] */
-#define BCHP_XPT_BUS_IF_INTR_STATUS4_REG_reserved1_MASK 0x07ff0000
-#define BCHP_XPT_BUS_IF_INTR_STATUS4_REG_reserved1_SHIFT 16
-
-/* XPT_BUS_IF :: INTR_STATUS4_REG :: PSUB15_EOB_INT [15:15] */
-#define BCHP_XPT_BUS_IF_INTR_STATUS4_REG_PSUB15_EOB_INT_MASK 0x00008000
-#define BCHP_XPT_BUS_IF_INTR_STATUS4_REG_PSUB15_EOB_INT_SHIFT 15
-#define BCHP_XPT_BUS_IF_INTR_STATUS4_REG_PSUB15_EOB_INT_DEFAULT 0x00000000
-
-/* XPT_BUS_IF :: INTR_STATUS4_REG :: PSUB14_EOB_INT [14:14] */
-#define BCHP_XPT_BUS_IF_INTR_STATUS4_REG_PSUB14_EOB_INT_MASK 0x00004000
-#define BCHP_XPT_BUS_IF_INTR_STATUS4_REG_PSUB14_EOB_INT_SHIFT 14
-#define BCHP_XPT_BUS_IF_INTR_STATUS4_REG_PSUB14_EOB_INT_DEFAULT 0x00000000
-
-/* XPT_BUS_IF :: INTR_STATUS4_REG :: PSUB13_EOB_INT [13:13] */
-#define BCHP_XPT_BUS_IF_INTR_STATUS4_REG_PSUB13_EOB_INT_MASK 0x00002000
-#define BCHP_XPT_BUS_IF_INTR_STATUS4_REG_PSUB13_EOB_INT_SHIFT 13
-#define BCHP_XPT_BUS_IF_INTR_STATUS4_REG_PSUB13_EOB_INT_DEFAULT 0x00000000
-
-/* XPT_BUS_IF :: INTR_STATUS4_REG :: PSUB12_EOB_INT [12:12] */
-#define BCHP_XPT_BUS_IF_INTR_STATUS4_REG_PSUB12_EOB_INT_MASK 0x00001000
-#define BCHP_XPT_BUS_IF_INTR_STATUS4_REG_PSUB12_EOB_INT_SHIFT 12
-#define BCHP_XPT_BUS_IF_INTR_STATUS4_REG_PSUB12_EOB_INT_DEFAULT 0x00000000
-
-/* XPT_BUS_IF :: INTR_STATUS4_REG :: PSUB11_EOB_INT [11:11] */
-#define BCHP_XPT_BUS_IF_INTR_STATUS4_REG_PSUB11_EOB_INT_MASK 0x00000800
-#define BCHP_XPT_BUS_IF_INTR_STATUS4_REG_PSUB11_EOB_INT_SHIFT 11
-#define BCHP_XPT_BUS_IF_INTR_STATUS4_REG_PSUB11_EOB_INT_DEFAULT 0x00000000
-
-/* XPT_BUS_IF :: INTR_STATUS4_REG :: PSUB10_EOB_INT [10:10] */
-#define BCHP_XPT_BUS_IF_INTR_STATUS4_REG_PSUB10_EOB_INT_MASK 0x00000400
-#define BCHP_XPT_BUS_IF_INTR_STATUS4_REG_PSUB10_EOB_INT_SHIFT 10
-#define BCHP_XPT_BUS_IF_INTR_STATUS4_REG_PSUB10_EOB_INT_DEFAULT 0x00000000
-
-/* XPT_BUS_IF :: INTR_STATUS4_REG :: PSUB9_EOB_INT [09:09] */
-#define BCHP_XPT_BUS_IF_INTR_STATUS4_REG_PSUB9_EOB_INT_MASK 0x00000200
-#define BCHP_XPT_BUS_IF_INTR_STATUS4_REG_PSUB9_EOB_INT_SHIFT 9
-#define BCHP_XPT_BUS_IF_INTR_STATUS4_REG_PSUB9_EOB_INT_DEFAULT 0x00000000
-
-/* XPT_BUS_IF :: INTR_STATUS4_REG :: PSUB8_EOB_INT [08:08] */
-#define BCHP_XPT_BUS_IF_INTR_STATUS4_REG_PSUB8_EOB_INT_MASK 0x00000100
-#define BCHP_XPT_BUS_IF_INTR_STATUS4_REG_PSUB8_EOB_INT_SHIFT 8
-#define BCHP_XPT_BUS_IF_INTR_STATUS4_REG_PSUB8_EOB_INT_DEFAULT 0x00000000
-
-/* XPT_BUS_IF :: INTR_STATUS4_REG :: PSUB7_EOB_INT [07:07] */
-#define BCHP_XPT_BUS_IF_INTR_STATUS4_REG_PSUB7_EOB_INT_MASK 0x00000080
-#define BCHP_XPT_BUS_IF_INTR_STATUS4_REG_PSUB7_EOB_INT_SHIFT 7
-#define BCHP_XPT_BUS_IF_INTR_STATUS4_REG_PSUB7_EOB_INT_DEFAULT 0x00000000
-
-/* XPT_BUS_IF :: INTR_STATUS4_REG :: PSUB6_EOB_INT [06:06] */
-#define BCHP_XPT_BUS_IF_INTR_STATUS4_REG_PSUB6_EOB_INT_MASK 0x00000040
-#define BCHP_XPT_BUS_IF_INTR_STATUS4_REG_PSUB6_EOB_INT_SHIFT 6
-#define BCHP_XPT_BUS_IF_INTR_STATUS4_REG_PSUB6_EOB_INT_DEFAULT 0x00000000
-
-/* XPT_BUS_IF :: INTR_STATUS4_REG :: PSUB5_EOB_INT [05:05] */
-#define BCHP_XPT_BUS_IF_INTR_STATUS4_REG_PSUB5_EOB_INT_MASK 0x00000020
-#define BCHP_XPT_BUS_IF_INTR_STATUS4_REG_PSUB5_EOB_INT_SHIFT 5
-#define BCHP_XPT_BUS_IF_INTR_STATUS4_REG_PSUB5_EOB_INT_DEFAULT 0x00000000
-
-/* XPT_BUS_IF :: INTR_STATUS4_REG :: PSUB4_EOB_INT [04:04] */
-#define BCHP_XPT_BUS_IF_INTR_STATUS4_REG_PSUB4_EOB_INT_MASK 0x00000010
-#define BCHP_XPT_BUS_IF_INTR_STATUS4_REG_PSUB4_EOB_INT_SHIFT 4
-#define BCHP_XPT_BUS_IF_INTR_STATUS4_REG_PSUB4_EOB_INT_DEFAULT 0x00000000
-
-/* XPT_BUS_IF :: INTR_STATUS4_REG :: PSUB3_EOB_INT [03:03] */
-#define BCHP_XPT_BUS_IF_INTR_STATUS4_REG_PSUB3_EOB_INT_MASK 0x00000008
-#define BCHP_XPT_BUS_IF_INTR_STATUS4_REG_PSUB3_EOB_INT_SHIFT 3
-#define BCHP_XPT_BUS_IF_INTR_STATUS4_REG_PSUB3_EOB_INT_DEFAULT 0x00000000
-
-/* XPT_BUS_IF :: INTR_STATUS4_REG :: PSUB2_EOB_INT [02:02] */
-#define BCHP_XPT_BUS_IF_INTR_STATUS4_REG_PSUB2_EOB_INT_MASK 0x00000004
-#define BCHP_XPT_BUS_IF_INTR_STATUS4_REG_PSUB2_EOB_INT_SHIFT 2
-#define BCHP_XPT_BUS_IF_INTR_STATUS4_REG_PSUB2_EOB_INT_DEFAULT 0x00000000
-
-/* XPT_BUS_IF :: INTR_STATUS4_REG :: PSUB1_EOB_INT [01:01] */
-#define BCHP_XPT_BUS_IF_INTR_STATUS4_REG_PSUB1_EOB_INT_MASK 0x00000002
-#define BCHP_XPT_BUS_IF_INTR_STATUS4_REG_PSUB1_EOB_INT_SHIFT 1
-#define BCHP_XPT_BUS_IF_INTR_STATUS4_REG_PSUB1_EOB_INT_DEFAULT 0x00000000
-
-/* XPT_BUS_IF :: INTR_STATUS4_REG :: PSUB0_EOB_INT [00:00] */
-#define BCHP_XPT_BUS_IF_INTR_STATUS4_REG_PSUB0_EOB_INT_MASK 0x00000001
-#define BCHP_XPT_BUS_IF_INTR_STATUS4_REG_PSUB0_EOB_INT_SHIFT 0
-#define BCHP_XPT_BUS_IF_INTR_STATUS4_REG_PSUB0_EOB_INT_DEFAULT 0x00000000
-
-/***************************************************************************
- *INTR_STATUS4_REG_EN - Interrupt Status4 Enable Register
- ***************************************************************************/
-/* XPT_BUS_IF :: INTR_STATUS4_REG_EN :: reserved0 [31:28] */
-#define BCHP_XPT_BUS_IF_INTR_STATUS4_REG_EN_reserved0_MASK 0xf0000000
-#define BCHP_XPT_BUS_IF_INTR_STATUS4_REG_EN_reserved0_SHIFT 28
-
-/* XPT_BUS_IF :: INTR_STATUS4_REG_EN :: GISB_BRIDGE_EN [27:27] */
-#define BCHP_XPT_BUS_IF_INTR_STATUS4_REG_EN_GISB_BRIDGE_EN_MASK 0x08000000
-#define BCHP_XPT_BUS_IF_INTR_STATUS4_REG_EN_GISB_BRIDGE_EN_SHIFT 27
-#define BCHP_XPT_BUS_IF_INTR_STATUS4_REG_EN_GISB_BRIDGE_EN_DEFAULT 0x00000000
-
-/* XPT_BUS_IF :: INTR_STATUS4_REG_EN :: reserved1 [26:16] */
-#define BCHP_XPT_BUS_IF_INTR_STATUS4_REG_EN_reserved1_MASK 0x07ff0000
-#define BCHP_XPT_BUS_IF_INTR_STATUS4_REG_EN_reserved1_SHIFT 16
-
-/* XPT_BUS_IF :: INTR_STATUS4_REG_EN :: PSUB15_EOB_INT_EN [15:15] */
-#define BCHP_XPT_BUS_IF_INTR_STATUS4_REG_EN_PSUB15_EOB_INT_EN_MASK 0x00008000
-#define BCHP_XPT_BUS_IF_INTR_STATUS4_REG_EN_PSUB15_EOB_INT_EN_SHIFT 15
-#define BCHP_XPT_BUS_IF_INTR_STATUS4_REG_EN_PSUB15_EOB_INT_EN_DEFAULT 0x00000000
-
-/* XPT_BUS_IF :: INTR_STATUS4_REG_EN :: PSUB14_EOB_INT_EN [14:14] */
-#define BCHP_XPT_BUS_IF_INTR_STATUS4_REG_EN_PSUB14_EOB_INT_EN_MASK 0x00004000
-#define BCHP_XPT_BUS_IF_INTR_STATUS4_REG_EN_PSUB14_EOB_INT_EN_SHIFT 14
-#define BCHP_XPT_BUS_IF_INTR_STATUS4_REG_EN_PSUB14_EOB_INT_EN_DEFAULT 0x00000000
-
-/* XPT_BUS_IF :: INTR_STATUS4_REG_EN :: PSUB13_EOB_INT_EN [13:13] */
-#define BCHP_XPT_BUS_IF_INTR_STATUS4_REG_EN_PSUB13_EOB_INT_EN_MASK 0x00002000
-#define BCHP_XPT_BUS_IF_INTR_STATUS4_REG_EN_PSUB13_EOB_INT_EN_SHIFT 13
-#define BCHP_XPT_BUS_IF_INTR_STATUS4_REG_EN_PSUB13_EOB_INT_EN_DEFAULT 0x00000000
-
-/* XPT_BUS_IF :: INTR_STATUS4_REG_EN :: PSUB12_EOB_INT_EN [12:12] */
-#define BCHP_XPT_BUS_IF_INTR_STATUS4_REG_EN_PSUB12_EOB_INT_EN_MASK 0x00001000
-#define BCHP_XPT_BUS_IF_INTR_STATUS4_REG_EN_PSUB12_EOB_INT_EN_SHIFT 12
-#define BCHP_XPT_BUS_IF_INTR_STATUS4_REG_EN_PSUB12_EOB_INT_EN_DEFAULT 0x00000000
-
-/* XPT_BUS_IF :: INTR_STATUS4_REG_EN :: PSUB11_EOB_INT_EN [11:11] */
-#define BCHP_XPT_BUS_IF_INTR_STATUS4_REG_EN_PSUB11_EOB_INT_EN_MASK 0x00000800
-#define BCHP_XPT_BUS_IF_INTR_STATUS4_REG_EN_PSUB11_EOB_INT_EN_SHIFT 11
-#define BCHP_XPT_BUS_IF_INTR_STATUS4_REG_EN_PSUB11_EOB_INT_EN_DEFAULT 0x00000000
-
-/* XPT_BUS_IF :: INTR_STATUS4_REG_EN :: PSUB10_EOB_INT_EN [10:10] */
-#define BCHP_XPT_BUS_IF_INTR_STATUS4_REG_EN_PSUB10_EOB_INT_EN_MASK 0x00000400
-#define BCHP_XPT_BUS_IF_INTR_STATUS4_REG_EN_PSUB10_EOB_INT_EN_SHIFT 10
-#define BCHP_XPT_BUS_IF_INTR_STATUS4_REG_EN_PSUB10_EOB_INT_EN_DEFAULT 0x00000000
-
-/* XPT_BUS_IF :: INTR_STATUS4_REG_EN :: PSUB9_EOB_INT_EN [09:09] */
-#define BCHP_XPT_BUS_IF_INTR_STATUS4_REG_EN_PSUB9_EOB_INT_EN_MASK 0x00000200
-#define BCHP_XPT_BUS_IF_INTR_STATUS4_REG_EN_PSUB9_EOB_INT_EN_SHIFT 9
-#define BCHP_XPT_BUS_IF_INTR_STATUS4_REG_EN_PSUB9_EOB_INT_EN_DEFAULT 0x00000000
-
-/* XPT_BUS_IF :: INTR_STATUS4_REG_EN :: PSUB8_EOB_INT_EN [08:08] */
-#define BCHP_XPT_BUS_IF_INTR_STATUS4_REG_EN_PSUB8_EOB_INT_EN_MASK 0x00000100
-#define BCHP_XPT_BUS_IF_INTR_STATUS4_REG_EN_PSUB8_EOB_INT_EN_SHIFT 8
-#define BCHP_XPT_BUS_IF_INTR_STATUS4_REG_EN_PSUB8_EOB_INT_EN_DEFAULT 0x00000000
-
-/* XPT_BUS_IF :: INTR_STATUS4_REG_EN :: PSUB7_EOB_INT_EN [07:07] */
-#define BCHP_XPT_BUS_IF_INTR_STATUS4_REG_EN_PSUB7_EOB_INT_EN_MASK 0x00000080
-#define BCHP_XPT_BUS_IF_INTR_STATUS4_REG_EN_PSUB7_EOB_INT_EN_SHIFT 7
-#define BCHP_XPT_BUS_IF_INTR_STATUS4_REG_EN_PSUB7_EOB_INT_EN_DEFAULT 0x00000000
-
-/* XPT_BUS_IF :: INTR_STATUS4_REG_EN :: PSUB6_EOB_INT_EN [06:06] */
-#define BCHP_XPT_BUS_IF_INTR_STATUS4_REG_EN_PSUB6_EOB_INT_EN_MASK 0x00000040
-#define BCHP_XPT_BUS_IF_INTR_STATUS4_REG_EN_PSUB6_EOB_INT_EN_SHIFT 6
-#define BCHP_XPT_BUS_IF_INTR_STATUS4_REG_EN_PSUB6_EOB_INT_EN_DEFAULT 0x00000000
-
-/* XPT_BUS_IF :: INTR_STATUS4_REG_EN :: PSUB5_EOB_INT_EN [05:05] */
-#define BCHP_XPT_BUS_IF_INTR_STATUS4_REG_EN_PSUB5_EOB_INT_EN_MASK 0x00000020
-#define BCHP_XPT_BUS_IF_INTR_STATUS4_REG_EN_PSUB5_EOB_INT_EN_SHIFT 5
-#define BCHP_XPT_BUS_IF_INTR_STATUS4_REG_EN_PSUB5_EOB_INT_EN_DEFAULT 0x00000000
-
-/* XPT_BUS_IF :: INTR_STATUS4_REG_EN :: PSUB4_EOB_INT_EN [04:04] */
-#define BCHP_XPT_BUS_IF_INTR_STATUS4_REG_EN_PSUB4_EOB_INT_EN_MASK 0x00000010
-#define BCHP_XPT_BUS_IF_INTR_STATUS4_REG_EN_PSUB4_EOB_INT_EN_SHIFT 4
-#define BCHP_XPT_BUS_IF_INTR_STATUS4_REG_EN_PSUB4_EOB_INT_EN_DEFAULT 0x00000000
-
-/* XPT_BUS_IF :: INTR_STATUS4_REG_EN :: PSUB3_EOB_INT_EN [03:03] */
-#define BCHP_XPT_BUS_IF_INTR_STATUS4_REG_EN_PSUB3_EOB_INT_EN_MASK 0x00000008
-#define BCHP_XPT_BUS_IF_INTR_STATUS4_REG_EN_PSUB3_EOB_INT_EN_SHIFT 3
-#define BCHP_XPT_BUS_IF_INTR_STATUS4_REG_EN_PSUB3_EOB_INT_EN_DEFAULT 0x00000000
-
-/* XPT_BUS_IF :: INTR_STATUS4_REG_EN :: PSUB2_EOB_INT_EN [02:02] */
-#define BCHP_XPT_BUS_IF_INTR_STATUS4_REG_EN_PSUB2_EOB_INT_EN_MASK 0x00000004
-#define BCHP_XPT_BUS_IF_INTR_STATUS4_REG_EN_PSUB2_EOB_INT_EN_SHIFT 2
-#define BCHP_XPT_BUS_IF_INTR_STATUS4_REG_EN_PSUB2_EOB_INT_EN_DEFAULT 0x00000000
-
-/* XPT_BUS_IF :: INTR_STATUS4_REG_EN :: PSUB1_EOB_INT_EN [01:01] */
-#define BCHP_XPT_BUS_IF_INTR_STATUS4_REG_EN_PSUB1_EOB_INT_EN_MASK 0x00000002
-#define BCHP_XPT_BUS_IF_INTR_STATUS4_REG_EN_PSUB1_EOB_INT_EN_SHIFT 1
-#define BCHP_XPT_BUS_IF_INTR_STATUS4_REG_EN_PSUB1_EOB_INT_EN_DEFAULT 0x00000000
-
-/* XPT_BUS_IF :: INTR_STATUS4_REG_EN :: PSUB0_EOB_INT_EN [00:00] */
-#define BCHP_XPT_BUS_IF_INTR_STATUS4_REG_EN_PSUB0_EOB_INT_EN_MASK 0x00000001
-#define BCHP_XPT_BUS_IF_INTR_STATUS4_REG_EN_PSUB0_EOB_INT_EN_SHIFT 0
-#define BCHP_XPT_BUS_IF_INTR_STATUS4_REG_EN_PSUB0_EOB_INT_EN_DEFAULT 0x00000000
-
-/***************************************************************************
- *INTR_STATUS5_REG - Interrupt Status5 Register
- ***************************************************************************/
-/* XPT_BUS_IF :: INTR_STATUS5_REG :: reserved0 [31:01] */
-#define BCHP_XPT_BUS_IF_INTR_STATUS5_REG_reserved0_MASK 0xfffffffe
-#define BCHP_XPT_BUS_IF_INTR_STATUS5_REG_reserved0_SHIFT 1
-
-/* XPT_BUS_IF :: INTR_STATUS5_REG :: WRCHECKER_INT [00:00] */
-#define BCHP_XPT_BUS_IF_INTR_STATUS5_REG_WRCHECKER_INT_MASK 0x00000001
-#define BCHP_XPT_BUS_IF_INTR_STATUS5_REG_WRCHECKER_INT_SHIFT 0
-#define BCHP_XPT_BUS_IF_INTR_STATUS5_REG_WRCHECKER_INT_DEFAULT 0x00000000
-
-/***************************************************************************
- *INTR_STATUS5_REG_EN - Interrupt Status5 Enable Register
- ***************************************************************************/
-/* XPT_BUS_IF :: INTR_STATUS5_REG_EN :: reserved0 [31:01] */
-#define BCHP_XPT_BUS_IF_INTR_STATUS5_REG_EN_reserved0_MASK 0xfffffffe
-#define BCHP_XPT_BUS_IF_INTR_STATUS5_REG_EN_reserved0_SHIFT 1
-
-/* XPT_BUS_IF :: INTR_STATUS5_REG_EN :: WRCHECKER_INT [00:00] */
-#define BCHP_XPT_BUS_IF_INTR_STATUS5_REG_EN_WRCHECKER_INT_MASK 0x00000001
-#define BCHP_XPT_BUS_IF_INTR_STATUS5_REG_EN_WRCHECKER_INT_SHIFT 0
-#define BCHP_XPT_BUS_IF_INTR_STATUS5_REG_EN_WRCHECKER_INT_DEFAULT 0x00000000
-
-/***************************************************************************
- *SUB_MODULE_SOFT_INIT_SET - Software initialization control for XPT sub-blocks
- ***************************************************************************/
-/* XPT_BUS_IF :: SUB_MODULE_SOFT_INIT_SET :: reserved0 [31:02] */
-#define BCHP_XPT_BUS_IF_SUB_MODULE_SOFT_INIT_SET_reserved0_MASK 0xfffffffc
-#define BCHP_XPT_BUS_IF_SUB_MODULE_SOFT_INIT_SET_reserved0_SHIFT 2
-
-/* XPT_BUS_IF :: SUB_MODULE_SOFT_INIT_SET :: MEMDMA_MCPB_SOFT_INIT_SET [01:01] */
-#define BCHP_XPT_BUS_IF_SUB_MODULE_SOFT_INIT_SET_MEMDMA_MCPB_SOFT_INIT_SET_MASK 0x00000002
-#define BCHP_XPT_BUS_IF_SUB_MODULE_SOFT_INIT_SET_MEMDMA_MCPB_SOFT_INIT_SET_SHIFT 1
-#define BCHP_XPT_BUS_IF_SUB_MODULE_SOFT_INIT_SET_MEMDMA_MCPB_SOFT_INIT_SET_DEFAULT 0x00000000
-
-/* XPT_BUS_IF :: SUB_MODULE_SOFT_INIT_SET :: XPT_MCPB_SOFT_INIT_SET [00:00] */
-#define BCHP_XPT_BUS_IF_SUB_MODULE_SOFT_INIT_SET_XPT_MCPB_SOFT_INIT_SET_MASK 0x00000001
-#define BCHP_XPT_BUS_IF_SUB_MODULE_SOFT_INIT_SET_XPT_MCPB_SOFT_INIT_SET_SHIFT 0
-#define BCHP_XPT_BUS_IF_SUB_MODULE_SOFT_INIT_SET_XPT_MCPB_SOFT_INIT_SET_DEFAULT 0x00000000
-
-/***************************************************************************
- *SUB_MODULE_SOFT_INIT_CLEAR - Software initialization control for XPT sub-blocks
- ***************************************************************************/
-/* XPT_BUS_IF :: SUB_MODULE_SOFT_INIT_CLEAR :: reserved0 [31:02] */
-#define BCHP_XPT_BUS_IF_SUB_MODULE_SOFT_INIT_CLEAR_reserved0_MASK 0xfffffffc
-#define BCHP_XPT_BUS_IF_SUB_MODULE_SOFT_INIT_CLEAR_reserved0_SHIFT 2
-
-/* XPT_BUS_IF :: SUB_MODULE_SOFT_INIT_CLEAR :: MEMDMA_MCPB_SOFT_INIT_CLEAR [01:01] */
-#define BCHP_XPT_BUS_IF_SUB_MODULE_SOFT_INIT_CLEAR_MEMDMA_MCPB_SOFT_INIT_CLEAR_MASK 0x00000002
-#define BCHP_XPT_BUS_IF_SUB_MODULE_SOFT_INIT_CLEAR_MEMDMA_MCPB_SOFT_INIT_CLEAR_SHIFT 1
-#define BCHP_XPT_BUS_IF_SUB_MODULE_SOFT_INIT_CLEAR_MEMDMA_MCPB_SOFT_INIT_CLEAR_DEFAULT 0x00000000
-
-/* XPT_BUS_IF :: SUB_MODULE_SOFT_INIT_CLEAR :: XPT_MCPB_SOFT_INIT_CLEAR [00:00] */
-#define BCHP_XPT_BUS_IF_SUB_MODULE_SOFT_INIT_CLEAR_XPT_MCPB_SOFT_INIT_CLEAR_MASK 0x00000001
-#define BCHP_XPT_BUS_IF_SUB_MODULE_SOFT_INIT_CLEAR_XPT_MCPB_SOFT_INIT_CLEAR_SHIFT 0
-#define BCHP_XPT_BUS_IF_SUB_MODULE_SOFT_INIT_CLEAR_XPT_MCPB_SOFT_INIT_CLEAR_DEFAULT 0x00000000
-
-/***************************************************************************
- *SUB_MODULE_SOFT_INIT_STATUS - Software initialization control for XPT sub-blocks
- ***************************************************************************/
-/* XPT_BUS_IF :: SUB_MODULE_SOFT_INIT_STATUS :: reserved0 [31:02] */
-#define BCHP_XPT_BUS_IF_SUB_MODULE_SOFT_INIT_STATUS_reserved0_MASK 0xfffffffc
-#define BCHP_XPT_BUS_IF_SUB_MODULE_SOFT_INIT_STATUS_reserved0_SHIFT 2
-
-/* XPT_BUS_IF :: SUB_MODULE_SOFT_INIT_STATUS :: MEMDMA_MCPB_SOFT_INIT_STATUS [01:01] */
-#define BCHP_XPT_BUS_IF_SUB_MODULE_SOFT_INIT_STATUS_MEMDMA_MCPB_SOFT_INIT_STATUS_MASK 0x00000002
-#define BCHP_XPT_BUS_IF_SUB_MODULE_SOFT_INIT_STATUS_MEMDMA_MCPB_SOFT_INIT_STATUS_SHIFT 1
-#define BCHP_XPT_BUS_IF_SUB_MODULE_SOFT_INIT_STATUS_MEMDMA_MCPB_SOFT_INIT_STATUS_DEFAULT 0x00000000
-
-/* XPT_BUS_IF :: SUB_MODULE_SOFT_INIT_STATUS :: XPT_MCPB_SOFT_INIT_STATUS [00:00] */
-#define BCHP_XPT_BUS_IF_SUB_MODULE_SOFT_INIT_STATUS_XPT_MCPB_SOFT_INIT_STATUS_MASK 0x00000001
-#define BCHP_XPT_BUS_IF_SUB_MODULE_SOFT_INIT_STATUS_XPT_MCPB_SOFT_INIT_STATUS_SHIFT 0
-#define BCHP_XPT_BUS_IF_SUB_MODULE_SOFT_INIT_STATUS_XPT_MCPB_SOFT_INIT_STATUS_DEFAULT 0x00000000
-
-/***************************************************************************
- *SUB_MODULE_SOFT_INIT_DO_MEM_INIT - Software initialization control for XPT sub-blocks
- ***************************************************************************/
-/* XPT_BUS_IF :: SUB_MODULE_SOFT_INIT_DO_MEM_INIT :: reserved0 [31:02] */
-#define BCHP_XPT_BUS_IF_SUB_MODULE_SOFT_INIT_DO_MEM_INIT_reserved0_MASK 0xfffffffc
-#define BCHP_XPT_BUS_IF_SUB_MODULE_SOFT_INIT_DO_MEM_INIT_reserved0_SHIFT 2
-
-/* XPT_BUS_IF :: SUB_MODULE_SOFT_INIT_DO_MEM_INIT :: MEMDMA_MCPB_SOFT_INIT_DO_MEM_INIT [01:01] */
-#define BCHP_XPT_BUS_IF_SUB_MODULE_SOFT_INIT_DO_MEM_INIT_MEMDMA_MCPB_SOFT_INIT_DO_MEM_INIT_MASK 0x00000002
-#define BCHP_XPT_BUS_IF_SUB_MODULE_SOFT_INIT_DO_MEM_INIT_MEMDMA_MCPB_SOFT_INIT_DO_MEM_INIT_SHIFT 1
-#define BCHP_XPT_BUS_IF_SUB_MODULE_SOFT_INIT_DO_MEM_INIT_MEMDMA_MCPB_SOFT_INIT_DO_MEM_INIT_DEFAULT 0x00000001
-
-/* XPT_BUS_IF :: SUB_MODULE_SOFT_INIT_DO_MEM_INIT :: XPT_MCPB_SOFT_INIT_DO_MEM_INIT [00:00] */
-#define BCHP_XPT_BUS_IF_SUB_MODULE_SOFT_INIT_DO_MEM_INIT_XPT_MCPB_SOFT_INIT_DO_MEM_INIT_MASK 0x00000001
-#define BCHP_XPT_BUS_IF_SUB_MODULE_SOFT_INIT_DO_MEM_INIT_XPT_MCPB_SOFT_INIT_DO_MEM_INIT_SHIFT 0
-#define BCHP_XPT_BUS_IF_SUB_MODULE_SOFT_INIT_DO_MEM_INIT_XPT_MCPB_SOFT_INIT_DO_MEM_INIT_DEFAULT 0x00000001
-
-/***************************************************************************
- *XMEMIF_RD_LC_DEBUG_REG_0 - LCIF to XMEMIF Debug Registers
- ***************************************************************************/
-/* XPT_BUS_IF :: XMEMIF_RD_LC_DEBUG_REG_0 :: reserved0 [31:16] */
-#define BCHP_XPT_BUS_IF_XMEMIF_RD_LC_DEBUG_REG_0_reserved0_MASK 0xffff0000
-#define BCHP_XPT_BUS_IF_XMEMIF_RD_LC_DEBUG_REG_0_reserved0_SHIFT 16
-
-/* XPT_BUS_IF :: XMEMIF_RD_LC_DEBUG_REG_0 :: PSUB_DEBUG_REG [15:00] */
-#define BCHP_XPT_BUS_IF_XMEMIF_RD_LC_DEBUG_REG_0_PSUB_DEBUG_REG_MASK 0x0000ffff
-#define BCHP_XPT_BUS_IF_XMEMIF_RD_LC_DEBUG_REG_0_PSUB_DEBUG_REG_SHIFT 0
-#define BCHP_XPT_BUS_IF_XMEMIF_RD_LC_DEBUG_REG_0_PSUB_DEBUG_REG_DEFAULT 0x00000000
-
-/***************************************************************************
- *XMEMIF_WR_LC_DEBUG_REG - LCIF to XMEMIF Debug Registers
- ***************************************************************************/
-/* XPT_BUS_IF :: XMEMIF_WR_LC_DEBUG_REG :: reserved0 [31:05] */
-#define BCHP_XPT_BUS_IF_XMEMIF_WR_LC_DEBUG_REG_reserved0_MASK 0xffffffe0
-#define BCHP_XPT_BUS_IF_XMEMIF_WR_LC_DEBUG_REG_reserved0_SHIFT 5
-
-/* XPT_BUS_IF :: XMEMIF_WR_LC_DEBUG_REG :: RSBUFF_WR_DEBUG_REG [04:04] */
-#define BCHP_XPT_BUS_IF_XMEMIF_WR_LC_DEBUG_REG_RSBUFF_WR_DEBUG_REG_MASK 0x00000010
-#define BCHP_XPT_BUS_IF_XMEMIF_WR_LC_DEBUG_REG_RSBUFF_WR_DEBUG_REG_SHIFT 4
-#define BCHP_XPT_BUS_IF_XMEMIF_WR_LC_DEBUG_REG_RSBUFF_WR_DEBUG_REG_DEFAULT 0x00000000
-
-/* XPT_BUS_IF :: XMEMIF_WR_LC_DEBUG_REG :: XCBUFF_WR_DEBUG_REG [03:03] */
-#define BCHP_XPT_BUS_IF_XMEMIF_WR_LC_DEBUG_REG_XCBUFF_WR_DEBUG_REG_MASK 0x00000008
-#define BCHP_XPT_BUS_IF_XMEMIF_WR_LC_DEBUG_REG_XCBUFF_WR_DEBUG_REG_SHIFT 3
-#define BCHP_XPT_BUS_IF_XMEMIF_WR_LC_DEBUG_REG_XCBUFF_WR_DEBUG_REG_DEFAULT 0x00000000
-
-/* XPT_BUS_IF :: XMEMIF_WR_LC_DEBUG_REG :: MSG_DEBUG_REG [02:02] */
-#define BCHP_XPT_BUS_IF_XMEMIF_WR_LC_DEBUG_REG_MSG_DEBUG_REG_MASK 0x00000004
-#define BCHP_XPT_BUS_IF_XMEMIF_WR_LC_DEBUG_REG_MSG_DEBUG_REG_SHIFT 2
-#define BCHP_XPT_BUS_IF_XMEMIF_WR_LC_DEBUG_REG_MSG_DEBUG_REG_DEFAULT 0x00000000
-
-/* XPT_BUS_IF :: XMEMIF_WR_LC_DEBUG_REG :: RAVE_DEBUG_REG [01:00] */
-#define BCHP_XPT_BUS_IF_XMEMIF_WR_LC_DEBUG_REG_RAVE_DEBUG_REG_MASK 0x00000003
-#define BCHP_XPT_BUS_IF_XMEMIF_WR_LC_DEBUG_REG_RAVE_DEBUG_REG_SHIFT 0
-#define BCHP_XPT_BUS_IF_XMEMIF_WR_LC_DEBUG_REG_RAVE_DEBUG_REG_DEFAULT 0x00000000
-
-/***************************************************************************
- *MAX_PLAYBACKS - Data Transport max number of playbacks supported
- ***************************************************************************/
-/* XPT_BUS_IF :: MAX_PLAYBACKS :: reserved0 [31:06] */
-#define BCHP_XPT_BUS_IF_MAX_PLAYBACKS_reserved0_MASK 0xffffffc0
-#define BCHP_XPT_BUS_IF_MAX_PLAYBACKS_reserved0_SHIFT 6
-
-/* XPT_BUS_IF :: MAX_PLAYBACKS :: MAX_PLAYBACKS [05:00] */
-#define BCHP_XPT_BUS_IF_MAX_PLAYBACKS_MAX_PLAYBACKS_MASK 0x0000003f
-#define BCHP_XPT_BUS_IF_MAX_PLAYBACKS_MAX_PLAYBACKS_SHIFT 0
-#define BCHP_XPT_BUS_IF_MAX_PLAYBACKS_MAX_PLAYBACKS_DEFAULT 0x00000020
-
-/***************************************************************************
- *MAX_PID_PARSERS - Data Transport max number of PID parsers supported
- ***************************************************************************/
-/* XPT_BUS_IF :: MAX_PID_PARSERS :: reserved0 [31:06] */
-#define BCHP_XPT_BUS_IF_MAX_PID_PARSERS_reserved0_MASK 0xffffffc0
-#define BCHP_XPT_BUS_IF_MAX_PID_PARSERS_reserved0_SHIFT 6
-
-/* XPT_BUS_IF :: MAX_PID_PARSERS :: MAX_PID_PARSERS [05:00] */
-#define BCHP_XPT_BUS_IF_MAX_PID_PARSERS_MAX_PID_PARSERS_MASK 0x0000003f
-#define BCHP_XPT_BUS_IF_MAX_PID_PARSERS_MAX_PID_PARSERS_SHIFT 0
-#define BCHP_XPT_BUS_IF_MAX_PID_PARSERS_MAX_PID_PARSERS_DEFAULT 0x00000018
-
-/***************************************************************************
- *MAX_PID_CHANNELS - Data Transport max number of PID channels supported excluding MEMDMA
- ***************************************************************************/
-/* XPT_BUS_IF :: MAX_PID_CHANNELS :: reserved0 [31:12] */
-#define BCHP_XPT_BUS_IF_MAX_PID_CHANNELS_reserved0_MASK 0xfffff000
-#define BCHP_XPT_BUS_IF_MAX_PID_CHANNELS_reserved0_SHIFT 12
-
-/* XPT_BUS_IF :: MAX_PID_CHANNELS :: MAX_PID_CHANNELS [11:00] */
-#define BCHP_XPT_BUS_IF_MAX_PID_CHANNELS_MAX_PID_CHANNELS_MASK 0x00000fff
-#define BCHP_XPT_BUS_IF_MAX_PID_CHANNELS_MAX_PID_CHANNELS_SHIFT 0
-#define BCHP_XPT_BUS_IF_MAX_PID_CHANNELS_MAX_PID_CHANNELS_DEFAULT 0x00000300
-
-/***************************************************************************
- *MEMDMA_MAX_PID_CHANNELS - Data Transport max number of PID channels supported for MEMDMA
- ***************************************************************************/
-/* XPT_BUS_IF :: MEMDMA_MAX_PID_CHANNELS :: reserved0 [31:12] */
-#define BCHP_XPT_BUS_IF_MEMDMA_MAX_PID_CHANNELS_reserved0_MASK 0xfffff000
-#define BCHP_XPT_BUS_IF_MEMDMA_MAX_PID_CHANNELS_reserved0_SHIFT 12
-
-/* XPT_BUS_IF :: MEMDMA_MAX_PID_CHANNELS :: MAX_PID_CHANNELS [11:00] */
-#define BCHP_XPT_BUS_IF_MEMDMA_MAX_PID_CHANNELS_MAX_PID_CHANNELS_MASK 0x00000fff
-#define BCHP_XPT_BUS_IF_MEMDMA_MAX_PID_CHANNELS_MAX_PID_CHANNELS_SHIFT 0
-#define BCHP_XPT_BUS_IF_MEMDMA_MAX_PID_CHANNELS_MAX_PID_CHANNELS_DEFAULT 0x00000400
-
-/***************************************************************************
- *MAX_INPUT_BANDS - Data Transport max number of input bands supported
- ***************************************************************************/
-/* XPT_BUS_IF :: MAX_INPUT_BANDS :: reserved0 [31:05] */
-#define BCHP_XPT_BUS_IF_MAX_INPUT_BANDS_reserved0_MASK 0xffffffe0
-#define BCHP_XPT_BUS_IF_MAX_INPUT_BANDS_reserved0_SHIFT 5
-
-/* XPT_BUS_IF :: MAX_INPUT_BANDS :: MAX_INPUT_BANDS [04:00] */
-#define BCHP_XPT_BUS_IF_MAX_INPUT_BANDS_MAX_INPUT_BANDS_MASK 0x0000001f
-#define BCHP_XPT_BUS_IF_MAX_INPUT_BANDS_MAX_INPUT_BANDS_SHIFT 0
-#define BCHP_XPT_BUS_IF_MAX_INPUT_BANDS_MAX_INPUT_BANDS_DEFAULT 0x0000000d
-
-/***************************************************************************
- *MAX_PCRS - Data Transport max number of PCRs supported
- ***************************************************************************/
-/* XPT_BUS_IF :: MAX_PCRS :: reserved0 [31:04] */
-#define BCHP_XPT_BUS_IF_MAX_PCRS_reserved0_MASK 0xfffffff0
-#define BCHP_XPT_BUS_IF_MAX_PCRS_reserved0_SHIFT 4
-
-/* XPT_BUS_IF :: MAX_PCRS :: MAX_PCRS [03:00] */
-#define BCHP_XPT_BUS_IF_MAX_PCRS_MAX_PCRS_MASK 0x0000000f
-#define BCHP_XPT_BUS_IF_MAX_PCRS_MAX_PCRS_SHIFT 0
-#define BCHP_XPT_BUS_IF_MAX_PCRS_MAX_PCRS_DEFAULT 0x0000000e
-
-/***************************************************************************
- *MAX_TPIT_CHANNELS - Data Transport max number of TPIT channels supported
- ***************************************************************************/
-/* XPT_BUS_IF :: MAX_TPIT_CHANNELS :: reserved0 [31:05] */
-#define BCHP_XPT_BUS_IF_MAX_TPIT_CHANNELS_reserved0_MASK 0xffffffe0
-#define BCHP_XPT_BUS_IF_MAX_TPIT_CHANNELS_reserved0_SHIFT 5
-
-/* XPT_BUS_IF :: MAX_TPIT_CHANNELS :: MAX_TPIT_CHANNELS [04:00] */
-#define BCHP_XPT_BUS_IF_MAX_TPIT_CHANNELS_MAX_TPIT_CHANNELS_MASK 0x0000001f
-#define BCHP_XPT_BUS_IF_MAX_TPIT_CHANNELS_MAX_TPIT_CHANNELS_SHIFT 0
-#define BCHP_XPT_BUS_IF_MAX_TPIT_CHANNELS_MAX_TPIT_CHANNELS_DEFAULT 0x00000010
-
-/***************************************************************************
- *MAX_RAVE_CONTEXTS - Data Transport max number of RAVE contexts supported
- ***************************************************************************/
-/* XPT_BUS_IF :: MAX_RAVE_CONTEXTS :: reserved0 [31:08] */
-#define BCHP_XPT_BUS_IF_MAX_RAVE_CONTEXTS_reserved0_MASK 0xffffff00
-#define BCHP_XPT_BUS_IF_MAX_RAVE_CONTEXTS_reserved0_SHIFT 8
-
-/* XPT_BUS_IF :: MAX_RAVE_CONTEXTS :: MAX_RAVE_CONTEXTS [07:00] */
-#define BCHP_XPT_BUS_IF_MAX_RAVE_CONTEXTS_MAX_RAVE_CONTEXTS_MASK 0x000000ff
-#define BCHP_XPT_BUS_IF_MAX_RAVE_CONTEXTS_MAX_RAVE_CONTEXTS_SHIFT 0
-#define BCHP_XPT_BUS_IF_MAX_RAVE_CONTEXTS_MAX_RAVE_CONTEXTS_DEFAULT 0x00000030
-
-/***************************************************************************
- *MAX_RMX_CHANNELS - Data Transport max number of RMX channels supported
- ***************************************************************************/
-/* XPT_BUS_IF :: MAX_RMX_CHANNELS :: reserved0 [31:04] */
-#define BCHP_XPT_BUS_IF_MAX_RMX_CHANNELS_reserved0_MASK 0xfffffff0
-#define BCHP_XPT_BUS_IF_MAX_RMX_CHANNELS_reserved0_SHIFT 4
-
-/* XPT_BUS_IF :: MAX_RMX_CHANNELS :: MAX_RMX_CHANNELS [03:00] */
-#define BCHP_XPT_BUS_IF_MAX_RMX_CHANNELS_MAX_RMX_CHANNELS_MASK 0x0000000f
-#define BCHP_XPT_BUS_IF_MAX_RMX_CHANNELS_MAX_RMX_CHANNELS_SHIFT 0
-#define BCHP_XPT_BUS_IF_MAX_RMX_CHANNELS_MAX_RMX_CHANNELS_DEFAULT 0x00000002
-
-/***************************************************************************
- *MAX_MSG_BUFFERS - Data Transport max number of MSG buffers supported
- ***************************************************************************/
-/* XPT_BUS_IF :: MAX_MSG_BUFFERS :: reserved0 [31:09] */
-#define BCHP_XPT_BUS_IF_MAX_MSG_BUFFERS_reserved0_MASK 0xfffffe00
-#define BCHP_XPT_BUS_IF_MAX_MSG_BUFFERS_reserved0_SHIFT 9
-
-/* XPT_BUS_IF :: MAX_MSG_BUFFERS :: MAX_MSG_BUFFERS [08:00] */
-#define BCHP_XPT_BUS_IF_MAX_MSG_BUFFERS_MAX_MSG_BUFFERS_MASK 0x000001ff
-#define BCHP_XPT_BUS_IF_MAX_MSG_BUFFERS_MAX_MSG_BUFFERS_SHIFT 0
-#define BCHP_XPT_BUS_IF_MAX_MSG_BUFFERS_MAX_MSG_BUFFERS_DEFAULT 0x00000100
-
-/***************************************************************************
- *MAX_SCDS - Data Transport max number of SCDs supported
- ***************************************************************************/
-/* XPT_BUS_IF :: MAX_SCDS :: reserved0 [31:09] */
-#define BCHP_XPT_BUS_IF_MAX_SCDS_reserved0_MASK 0xfffffe00
-#define BCHP_XPT_BUS_IF_MAX_SCDS_reserved0_SHIFT 9
-
-/* XPT_BUS_IF :: MAX_SCDS :: MAX_SCDS [08:00] */
-#define BCHP_XPT_BUS_IF_MAX_SCDS_MAX_SCDS_MASK 0x000001ff
-#define BCHP_XPT_BUS_IF_MAX_SCDS_MAX_SCDS_SHIFT 0
-#define BCHP_XPT_BUS_IF_MAX_SCDS_MAX_SCDS_DEFAULT 0x00000040
-
-#endif /* #ifndef BCHP_XPT_BUS_IF_H__ */
-
-/* End of File */
diff --git a/include/linux/brcmstb/7366b0/bchp_xpt_fe.h b/include/linux/brcmstb/7366b0/bchp_xpt_fe.h
deleted file mode 100644
index 6927f3a..0000000
--- a/include/linux/brcmstb/7366b0/bchp_xpt_fe.h
+++ /dev/null
@@ -1,11836 +0,0 @@
-/***************************************************************************
- * Copyright (c) 1999-2014, Broadcom Corporation
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
- *
- * Module Description:
- * DO NOT EDIT THIS FILE DIRECTLY
- *
- * This module was generated magically with RDB from a source description
- * file. You must edit the source file for changes to be made to this file.
- *
- *
- * Date: Generated on Wed Sep 3 14:59:57 2014
- * Full Compile MD5 Checksum 10187d4079392bab2546025f43274d34
- * (minus title and desc)
- * MD5 Checksum c1587c5e16f21f52e852e7c7a65c7811
- *
- * Compiled with: RDB Utility combo_header.pl
- * RDB Parser 3.0
- * unknown unknown
- * Perl Interpreter 5.008005
- * Operating System linux
- *
- * Revision History:
- *
- * $brcm_Log: $
- *
- ***************************************************************************/
-
-#ifndef BCHP_XPT_FE_H__
-#define BCHP_XPT_FE_H__
-
-/***************************************************************************
- *XPT_FE - XPT FRONTEND Control Registers
- ***************************************************************************/
-#define BCHP_XPT_FE_FE_CTRL 0x00a20000 /* Data Transport Front-End Control Register */
-#define BCHP_XPT_FE_PWR_CTRL 0x00a20004 /* Data Transport Front-End Power Control Register */
-#define BCHP_XPT_FE_MAX_PID_CHANNEL 0x00a20008 /* Maximum Pid Channel number register */
-#define BCHP_XPT_FE_IB_SYNC_DETECT_CTRL 0x00a2000c /* Data Transport Input Band Sync detect control */
-#define BCHP_XPT_FE_INTR_STATUS0_REG 0x00a20010 /* Interrupt Status Register */
-#define BCHP_XPT_FE_INTR_STATUS1_REG 0x00a20014 /* Interrupt Status Register */
-#define BCHP_XPT_FE_INTR_STATUS2_REG 0x00a20018 /* Interrupt Status Register */
-#define BCHP_XPT_FE_INTR_STATUS0_REG_EN 0x00a20024 /* Interrupt Status Enable Register */
-#define BCHP_XPT_FE_INTR_STATUS1_REG_EN 0x00a20028 /* Interrupt Status Enable Register */
-#define BCHP_XPT_FE_INTR_STATUS2_REG_EN 0x00a2002c /* Interrupt Status Enable Register */
-#define BCHP_XPT_FE_TSMF_INTR_STATUS0_REG 0x00a20038 /* TSMF Demultiplexer Interrupt Status Register */
-#define BCHP_XPT_FE_TSMF_INTR_STATUS0_REG_EN 0x00a2003c /* TSMF Demultiplexer Interrupt Status Enable Register */
-#define BCHP_XPT_FE_MTSIF_RX_INTR_STATUS0_REG 0x00a20040 /* Interrupt Status Register */
-#define BCHP_XPT_FE_MTSIF_RX_INTR_STATUS0_REG_EN 0x00a20048 /* Interrupt Status Enable Register */
-#define BCHP_XPT_FE_PARSERS_TSMF_FRAME_ERROR_INTR_STATUS0_REG 0x00a20050 /* Interrupt Status Register */
-#define BCHP_XPT_FE_PARSERS_TSMF_SYNC_ERROR_INTR_STATUS0_REG 0x00a20058 /* Interrupt Status Register */
-#define BCHP_XPT_FE_PARSERS_INBUFF_OVFL_ERROR_INTR_STATUS0_REG 0x00a20060 /* Interrupt Status Register */
-#define BCHP_XPT_FE_PARSERS_TSMF_FRAME_ERROR_INTR_STATUS0_REG_EN 0x00a20068 /* Interrupt Status Enable Register */
-#define BCHP_XPT_FE_PARSERS_TSMF_SYNC_ERROR_INTR_STATUS0_REG_EN 0x00a20070 /* Interrupt Status Enable Register */
-#define BCHP_XPT_FE_PARSERS_INBUFF_OVFL_ERROR_INTR_STATUS0_REG_EN 0x00a20078 /* Interrupt Status Enable Register */
-#define BCHP_XPT_FE_ATS_COUNTER_CTRL 0x00a200a0 /* FE_ATS_COUNTER_CTRL */
-#define BCHP_XPT_FE_ATS_TS_MOD300 0x00a200a4 /* FE_ATS_TS_MOD300 */
-#define BCHP_XPT_FE_ATS_TS_BINARY 0x00a200a8 /* FE_ATS_TS_BINARY */
-#define BCHP_XPT_FE_TV_STATUS_0 0x00a200b0 /* TV Status_0 */
-#define BCHP_XPT_FE_TV_STATUS_1 0x00a200b4 /* TV Status_1 */
-#define BCHP_XPT_FE_TV_STATUS_2 0x00a200b8 /* TV Status_2 */
-#define BCHP_XPT_FE_TV_STATUS_3 0x00a200bc /* TV Status_3 */
-#define BCHP_XPT_FE_TV_STATUS_4 0x00a200c0 /* TV Status_4 */
-#define BCHP_XPT_FE_IB0_CTRL 0x00a20100 /* Data Transport Input Band 0 Control Register */
-#define BCHP_XPT_FE_IB0_SYNC_COUNT 0x00a20104 /* Data Transport Input Band 0 Sync counter Register */
-#define BCHP_XPT_FE_IB1_CTRL 0x00a20108 /* Data Transport Input Band 1 Control Register */
-#define BCHP_XPT_FE_IB1_SYNC_COUNT 0x00a2010c /* Data Transport Input Band 1 Sync counter Register */
-#define BCHP_XPT_FE_IB2_CTRL 0x00a20110 /* Data Transport Input Band 2 Control Register */
-#define BCHP_XPT_FE_IB2_SYNC_COUNT 0x00a20114 /* Data Transport Input Band 2 Sync counter Register */
-#define BCHP_XPT_FE_IB3_CTRL 0x00a20118 /* Data Transport Input Band 3 Control Register */
-#define BCHP_XPT_FE_IB3_SYNC_COUNT 0x00a2011c /* Data Transport Input Band 3 Sync counter Register */
-#define BCHP_XPT_FE_IB10_CTRL 0x00a20150 /* Data Transport Input Band 10 Control Register */
-#define BCHP_XPT_FE_IB10_SYNC_COUNT 0x00a20154 /* Data Transport Input Band 10 Sync counter Register */
-#define BCHP_XPT_FE_MINI_PID_PARSER0_CTRL1 0x00a20200 /* Data Transport Parser Band 0 Control Register */
-#define BCHP_XPT_FE_MINI_PID_PARSER0_CTRL2 0x00a20204 /* Data Transport Parser Band 0 Control Register 2 */
-#define BCHP_XPT_FE_MINI_PID_PARSER0_ALL_PASS_CTRL 0x00a20208 /* Data Transport Parser Band 0 Control Register */
-#define BCHP_XPT_FE_MINI_PID_PARSER1_CTRL1 0x00a2020c /* Data Transport Parser Band 1 Control Register */
-#define BCHP_XPT_FE_MINI_PID_PARSER1_CTRL2 0x00a20210 /* Data Transport Parser Band 1 Control Register 2 */
-#define BCHP_XPT_FE_MINI_PID_PARSER1_ALL_PASS_CTRL 0x00a20214 /* Data Transport Parser Band 1 Control Register */
-#define BCHP_XPT_FE_MINI_PID_PARSER2_CTRL1 0x00a20218 /* Data Transport Parser Band 2 Control Register */
-#define BCHP_XPT_FE_MINI_PID_PARSER2_CTRL2 0x00a2021c /* Data Transport Parser Band 2 Control Register 2 */
-#define BCHP_XPT_FE_MINI_PID_PARSER2_ALL_PASS_CTRL 0x00a20220 /* Data Transport Parser Band 2 Control Register */
-#define BCHP_XPT_FE_MINI_PID_PARSER3_CTRL1 0x00a20224 /* Data Transport Parser Band 3 Control Register */
-#define BCHP_XPT_FE_MINI_PID_PARSER3_CTRL2 0x00a20228 /* Data Transport Parser Band 3 Control Register 2 */
-#define BCHP_XPT_FE_MINI_PID_PARSER3_ALL_PASS_CTRL 0x00a2022c /* Data Transport Parser Band 3 Control Register */
-#define BCHP_XPT_FE_MINI_PID_PARSER4_CTRL1 0x00a20230 /* Data Transport Parser Band 4 Control Register */
-#define BCHP_XPT_FE_MINI_PID_PARSER4_CTRL2 0x00a20234 /* Data Transport Parser Band 4 Control Register 2 */
-#define BCHP_XPT_FE_MINI_PID_PARSER4_ALL_PASS_CTRL 0x00a20238 /* Data Transport Parser Band 4 Control Register */
-#define BCHP_XPT_FE_MINI_PID_PARSER5_CTRL1 0x00a2023c /* Data Transport Parser Band 5 Control Register */
-#define BCHP_XPT_FE_MINI_PID_PARSER5_CTRL2 0x00a20240 /* Data Transport Parser Band 5 Control Register 2 */
-#define BCHP_XPT_FE_MINI_PID_PARSER5_ALL_PASS_CTRL 0x00a20244 /* Data Transport Parser Band 5 Control Register */
-#define BCHP_XPT_FE_MINI_PID_PARSER6_CTRL1 0x00a20248 /* Data Transport Parser Band 6 Control Register */
-#define BCHP_XPT_FE_MINI_PID_PARSER6_CTRL2 0x00a2024c /* Data Transport Parser Band 6 Control Register 2 */
-#define BCHP_XPT_FE_MINI_PID_PARSER6_ALL_PASS_CTRL 0x00a20250 /* Data Transport Parser Band 6 Control Register */
-#define BCHP_XPT_FE_MINI_PID_PARSER7_CTRL1 0x00a20254 /* Data Transport Parser Band 7 Control Register */
-#define BCHP_XPT_FE_MINI_PID_PARSER7_CTRL2 0x00a20258 /* Data Transport Parser Band 7 Control Register 2 */
-#define BCHP_XPT_FE_MINI_PID_PARSER7_ALL_PASS_CTRL 0x00a2025c /* Data Transport Parser Band 7 Control Register */
-#define BCHP_XPT_FE_MINI_PID_PARSER8_CTRL1 0x00a20260 /* Data Transport Parser Band 8 Control Register */
-#define BCHP_XPT_FE_MINI_PID_PARSER8_CTRL2 0x00a20264 /* Data Transport Parser Band 8 Control Register 2 */
-#define BCHP_XPT_FE_MINI_PID_PARSER8_ALL_PASS_CTRL 0x00a20268 /* Data Transport Parser Band 8 Control Register */
-#define BCHP_XPT_FE_MINI_PID_PARSER9_CTRL1 0x00a2026c /* Data Transport Parser Band 9 Control Register */
-#define BCHP_XPT_FE_MINI_PID_PARSER9_CTRL2 0x00a20270 /* Data Transport Parser Band 9 Control Register 2 */
-#define BCHP_XPT_FE_MINI_PID_PARSER9_ALL_PASS_CTRL 0x00a20274 /* Data Transport Parser Band 9 Control Register */
-#define BCHP_XPT_FE_MINI_PID_PARSER10_CTRL1 0x00a20278 /* Data Transport Parser Band 10 Control Register */
-#define BCHP_XPT_FE_MINI_PID_PARSER10_CTRL2 0x00a2027c /* Data Transport Parser Band 10 Control Register 2 */
-#define BCHP_XPT_FE_MINI_PID_PARSER10_ALL_PASS_CTRL 0x00a20280 /* Data Transport Parser Band 10 Control Register */
-#define BCHP_XPT_FE_MINI_PID_PARSER11_CTRL1 0x00a20284 /* Data Transport Parser Band 11 Control Register */
-#define BCHP_XPT_FE_MINI_PID_PARSER11_CTRL2 0x00a20288 /* Data Transport Parser Band 11 Control Register 2 */
-#define BCHP_XPT_FE_MINI_PID_PARSER11_ALL_PASS_CTRL 0x00a2028c /* Data Transport Parser Band 11 Control Register */
-#define BCHP_XPT_FE_MINI_PID_PARSER12_CTRL1 0x00a20290 /* Data Transport Parser Band 12 Control Register */
-#define BCHP_XPT_FE_MINI_PID_PARSER12_CTRL2 0x00a20294 /* Data Transport Parser Band 12 Control Register 2 */
-#define BCHP_XPT_FE_MINI_PID_PARSER12_ALL_PASS_CTRL 0x00a20298 /* Data Transport Parser Band 12 Control Register */
-#define BCHP_XPT_FE_MINI_PID_PARSER13_CTRL1 0x00a2029c /* Data Transport Parser Band 13 Control Register */
-#define BCHP_XPT_FE_MINI_PID_PARSER13_CTRL2 0x00a202a0 /* Data Transport Parser Band 13 Control Register 2 */
-#define BCHP_XPT_FE_MINI_PID_PARSER13_ALL_PASS_CTRL 0x00a202a4 /* Data Transport Parser Band 13 Control Register */
-#define BCHP_XPT_FE_MINI_PID_PARSER14_CTRL1 0x00a202a8 /* Data Transport Parser Band 14 Control Register */
-#define BCHP_XPT_FE_MINI_PID_PARSER14_CTRL2 0x00a202ac /* Data Transport Parser Band 14 Control Register 2 */
-#define BCHP_XPT_FE_MINI_PID_PARSER14_ALL_PASS_CTRL 0x00a202b0 /* Data Transport Parser Band 14 Control Register */
-#define BCHP_XPT_FE_MINI_PID_PARSER15_CTRL1 0x00a202b4 /* Data Transport Parser Band 15 Control Register */
-#define BCHP_XPT_FE_MINI_PID_PARSER15_CTRL2 0x00a202b8 /* Data Transport Parser Band 15 Control Register 2 */
-#define BCHP_XPT_FE_MINI_PID_PARSER15_ALL_PASS_CTRL 0x00a202bc /* Data Transport Parser Band 15 Control Register */
-#define BCHP_XPT_FE_MINI_PID_PARSER16_CTRL1 0x00a202c0 /* Data Transport Parser Band 16 Control Register */
-#define BCHP_XPT_FE_MINI_PID_PARSER16_CTRL2 0x00a202c4 /* Data Transport Parser Band 16 Control Register 2 */
-#define BCHP_XPT_FE_MINI_PID_PARSER16_ALL_PASS_CTRL 0x00a202c8 /* Data Transport Parser Band 16 Control Register */
-#define BCHP_XPT_FE_MINI_PID_PARSER17_CTRL1 0x00a202cc /* Data Transport Parser Band 17 Control Register */
-#define BCHP_XPT_FE_MINI_PID_PARSER17_CTRL2 0x00a202d0 /* Data Transport Parser Band 17 Control Register 2 */
-#define BCHP_XPT_FE_MINI_PID_PARSER17_ALL_PASS_CTRL 0x00a202d4 /* Data Transport Parser Band 17 Control Register */
-#define BCHP_XPT_FE_MINI_PID_PARSER18_CTRL1 0x00a202d8 /* Data Transport Parser Band 18 Control Register */
-#define BCHP_XPT_FE_MINI_PID_PARSER18_CTRL2 0x00a202dc /* Data Transport Parser Band 18 Control Register 2 */
-#define BCHP_XPT_FE_MINI_PID_PARSER18_ALL_PASS_CTRL 0x00a202e0 /* Data Transport Parser Band 18 Control Register */
-#define BCHP_XPT_FE_MINI_PID_PARSER19_CTRL1 0x00a202e4 /* Data Transport Parser Band 19 Control Register */
-#define BCHP_XPT_FE_MINI_PID_PARSER19_CTRL2 0x00a202e8 /* Data Transport Parser Band 19 Control Register 2 */
-#define BCHP_XPT_FE_MINI_PID_PARSER19_ALL_PASS_CTRL 0x00a202ec /* Data Transport Parser Band 19 Control Register */
-#define BCHP_XPT_FE_MINI_PID_PARSER20_CTRL1 0x00a202f0 /* Data Transport Parser Band 20 Control Register */
-#define BCHP_XPT_FE_MINI_PID_PARSER20_CTRL2 0x00a202f4 /* Data Transport Parser Band 20 Control Register 2 */
-#define BCHP_XPT_FE_MINI_PID_PARSER20_ALL_PASS_CTRL 0x00a202f8 /* Data Transport Parser Band 20 Control Register */
-#define BCHP_XPT_FE_MINI_PID_PARSER21_CTRL1 0x00a202fc /* Data Transport Parser Band 21 Control Register */
-#define BCHP_XPT_FE_MINI_PID_PARSER21_CTRL2 0x00a20300 /* Data Transport Parser Band 21 Control Register 2 */
-#define BCHP_XPT_FE_MINI_PID_PARSER21_ALL_PASS_CTRL 0x00a20304 /* Data Transport Parser Band 21 Control Register */
-#define BCHP_XPT_FE_MINI_PID_PARSER22_CTRL1 0x00a20308 /* Data Transport Parser Band 22 Control Register */
-#define BCHP_XPT_FE_MINI_PID_PARSER22_CTRL2 0x00a2030c /* Data Transport Parser Band 22 Control Register 2 */
-#define BCHP_XPT_FE_MINI_PID_PARSER22_ALL_PASS_CTRL 0x00a20310 /* Data Transport Parser Band 22 Control Register */
-#define BCHP_XPT_FE_MINI_PID_PARSER23_CTRL1 0x00a20314 /* Data Transport Parser Band 23 Control Register */
-#define BCHP_XPT_FE_MINI_PID_PARSER23_CTRL2 0x00a20318 /* Data Transport Parser Band 23 Control Register 2 */
-#define BCHP_XPT_FE_MINI_PID_PARSER23_ALL_PASS_CTRL 0x00a2031c /* Data Transport Parser Band 23 Control Register */
-#define BCHP_XPT_FE_MINI_PID_PARSER0_TO_PARSER3_BAND_ID 0x00a20380 /* MINI PID PARSER0 to PARSER3 BAND ID */
-#define BCHP_XPT_FE_MINI_PID_PARSER4_TO_PARSER7_BAND_ID 0x00a20384 /* MINI PID PARSER4 to PARSER7 BAND ID */
-#define BCHP_XPT_FE_MINI_PID_PARSER8_TO_PARSER11_BAND_ID 0x00a20388 /* MINI PID PARSER8 to PARSER11 BAND ID */
-#define BCHP_XPT_FE_MINI_PID_PARSER12_TO_PARSER15_BAND_ID 0x00a2038c /* MINI PID PARSER12 to PARSER15 BAND ID */
-#define BCHP_XPT_FE_TSMF0_CTRL 0x00a203a0 /* Data Transport TSMF Demultiplexer -- Control Register */
-#define BCHP_XPT_FE_TSMF0_SLOT_MAP_LO 0x00a203a4 /* Data Transport TSMF Demultiplexer -- Slot Map Vector LSBs Register */
-#define BCHP_XPT_FE_TSMF0_SLOT_MAP_HI 0x00a203a8 /* Data Transport TSMF Demultiplexer -- Slot Map Vector MSBs Register */
-#define BCHP_XPT_FE_TSMF0_STATUS 0x00a203ac /* Data Transport TSMF Demultiplexer -- Status Register */
-#define BCHP_XPT_FE_TSMF1_CTRL 0x00a203b0 /* Data Transport TSMF Demultiplexer -- Control Register */
-#define BCHP_XPT_FE_TSMF1_SLOT_MAP_LO 0x00a203b4 /* Data Transport TSMF Demultiplexer -- Slot Map Vector LSBs Register */
-#define BCHP_XPT_FE_TSMF1_SLOT_MAP_HI 0x00a203b8 /* Data Transport TSMF Demultiplexer -- Slot Map Vector MSBs Register */
-#define BCHP_XPT_FE_TSMF1_STATUS 0x00a203bc /* Data Transport TSMF Demultiplexer -- Status Register */
-#define BCHP_XPT_FE_MTSIF_RX0_CTRL1 0x00a204a0 /* FE_MTSIF_RX0_CTRL1 */
-#define BCHP_XPT_FE_MTSIF_RX0_SECRET_WORD 0x00a204a4 /* MTSIF RX0 Secret Word Register */
-#define BCHP_XPT_FE_MTSIF_RX0_BAND0_BAND31_ID_DROP 0x00a204a8 /* MTSIF RX0 Band0 to Band31 ID Drop Register */
-#define BCHP_XPT_FE_MTSIF_RX0_BAND0_BAND3_ID 0x00a204ac /* MTSIF RX0 Band0 to Band3 ID Register */
-#define BCHP_XPT_FE_MTSIF_RX0_BAND4_BAND7_ID 0x00a204b0 /* MTSIF RX0 Band4 to Band7 ID Register */
-#define BCHP_XPT_FE_MTSIF_RX0_BAND8_BAND11_ID 0x00a204b4 /* MTSIF RX0 Band8 to Band11 ID Register */
-#define BCHP_XPT_FE_MTSIF_RX0_BAND12_BAND15_ID 0x00a204b8 /* MTSIF RX0 Band12 to Band15 ID Register */
-#define BCHP_XPT_FE_MTSIF_RX0_BAND16_BAND19_ID 0x00a204bc /* MTSIF RX0 Band16 to Band19 ID Register */
-#define BCHP_XPT_FE_MTSIF_RX0_BAND20_BAND23_ID 0x00a204c0 /* MTSIF RX0 Band20 to Band23 ID Register */
-#define BCHP_XPT_FE_MTSIF_RX0_BAND24_BAND27_ID 0x00a204c4 /* MTSIF RX0 Band24 to Band27 ID Register */
-#define BCHP_XPT_FE_MTSIF_RX0_BAND28_BAND31_ID 0x00a204c8 /* MTSIF RX0 Band28 to Band31 ID Register */
-#define BCHP_XPT_FE_MTSIF_RX0_BAND32_BAND35_ID 0x00a204cc /* MTSIF RX0 Band32 to Band35 ID Register */
-#define BCHP_XPT_FE_MTSIF_RX0_BAND36_BAND39_ID 0x00a204d0 /* MTSIF RX0 Band36 to Band39 ID Register */
-#define BCHP_XPT_FE_MTSIF_RX0_BAND40_BAND43_ID 0x00a204d4 /* MTSIF RX0 Band40 to Band43 ID Register */
-#define BCHP_XPT_FE_MTSIF_RX0_BAND44_BAND47_ID 0x00a204d8 /* MTSIF RX0 Band44 to Band47 ID Register */
-#define BCHP_XPT_FE_MTSIF_RX0_BAND48_BAND51_ID 0x00a204dc /* MTSIF RX0 Band48 to Band51 ID Register */
-#define BCHP_XPT_FE_MTSIF_RX0_BAND52_BAND55_ID 0x00a204e0 /* MTSIF RX0 Band52 to Band55 ID Register */
-#define BCHP_XPT_FE_MTSIF_RX0_BAND56_BAND59_ID 0x00a204e4 /* MTSIF RX0 Band56 to Band59 ID Register */
-#define BCHP_XPT_FE_MTSIF_RX0_BAND60_BAND63_ID 0x00a204e8 /* MTSIF RX0 Band60 to Band63 ID Register */
-#define BCHP_XPT_FE_MTSIF_RX0_PKT_BAND0_BAND31_DETECT 0x00a204ec /* MTSIF RX0 Packet Band0 to Band31 Detect Register */
-#define BCHP_XPT_FE_MTSIF_RX1_CTRL1 0x00a204f0 /* FE_MTSIF_RX1_CTRL1 */
-#define BCHP_XPT_FE_MTSIF_RX1_SECRET_WORD 0x00a204f4 /* MTSIF RX1 Secret Word Register */
-#define BCHP_XPT_FE_MTSIF_RX1_BAND0_BAND31_ID_DROP 0x00a204f8 /* MTSIF RX1 Band0 to Band31 ID Drop Register */
-#define BCHP_XPT_FE_MTSIF_RX1_BAND0_BAND3_ID 0x00a204fc /* MTSIF RX1 Band0 to Band3 ID Register */
-#define BCHP_XPT_FE_MTSIF_RX1_BAND4_BAND7_ID 0x00a20500 /* MTSIF RX1 Band4 to Band7 ID Register */
-#define BCHP_XPT_FE_MTSIF_RX1_BAND8_BAND11_ID 0x00a20504 /* MTSIF RX1 Band8 to Band11 ID Register */
-#define BCHP_XPT_FE_MTSIF_RX1_BAND12_BAND15_ID 0x00a20508 /* MTSIF RX1 Band12 to Band15 ID Register */
-#define BCHP_XPT_FE_MTSIF_RX1_BAND16_BAND19_ID 0x00a2050c /* MTSIF RX1 Band16 to Band19 ID Register */
-#define BCHP_XPT_FE_MTSIF_RX1_BAND20_BAND23_ID 0x00a20510 /* MTSIF RX1 Band20 to Band23 ID Register */
-#define BCHP_XPT_FE_MTSIF_RX1_BAND24_BAND27_ID 0x00a20514 /* MTSIF RX1 Band24 to Band27 ID Register */
-#define BCHP_XPT_FE_MTSIF_RX1_BAND28_BAND31_ID 0x00a20518 /* MTSIF RX1 Band28 to Band31 ID Register */
-#define BCHP_XPT_FE_MTSIF_RX1_BAND32_BAND35_ID 0x00a2051c /* MTSIF RX1 Band32 to Band35 ID Register */
-#define BCHP_XPT_FE_MTSIF_RX1_BAND36_BAND39_ID 0x00a20520 /* MTSIF RX1 Band36 to Band39 ID Register */
-#define BCHP_XPT_FE_MTSIF_RX1_BAND40_BAND43_ID 0x00a20524 /* MTSIF RX1 Band40 to Band43 ID Register */
-#define BCHP_XPT_FE_MTSIF_RX1_BAND44_BAND47_ID 0x00a20528 /* MTSIF RX1 Band44 to Band47 ID Register */
-#define BCHP_XPT_FE_MTSIF_RX1_BAND48_BAND51_ID 0x00a2052c /* MTSIF RX1 Band48 to Band51 ID Register */
-#define BCHP_XPT_FE_MTSIF_RX1_BAND52_BAND55_ID 0x00a20530 /* MTSIF RX1 Band52 to Band55 ID Register */
-#define BCHP_XPT_FE_MTSIF_RX1_BAND56_BAND59_ID 0x00a20534 /* MTSIF RX1 Band56 to Band59 ID Register */
-#define BCHP_XPT_FE_MTSIF_RX1_BAND60_BAND63_ID 0x00a20538 /* MTSIF RX1 Band60 to Band63 ID Register */
-#define BCHP_XPT_FE_MTSIF_RX1_PKT_BAND0_BAND31_DETECT 0x00a2053c /* MTSIF RX1 Packet Band0 to Band31 Detect Register */
-#define BCHP_XPT_FE_MTSIF_RX2_CTRL1 0x00a20540 /* FE_MTSIF_RX2_CTRL1 */
-#define BCHP_XPT_FE_MTSIF_RX2_SECRET_WORD 0x00a20544 /* MTSIF RX2 Secret Word Register */
-#define BCHP_XPT_FE_MTSIF_RX2_BAND0_BAND31_ID_DROP 0x00a20548 /* MTSIF RX2 Band0 to Band31 ID Drop Register */
-#define BCHP_XPT_FE_MTSIF_RX2_BAND0_BAND3_ID 0x00a2054c /* MTSIF RX2 Band0 to Band3 ID Register */
-#define BCHP_XPT_FE_MTSIF_RX2_BAND4_BAND7_ID 0x00a20550 /* MTSIF RX2 Band4 to Band7 ID Register */
-#define BCHP_XPT_FE_MTSIF_RX2_BAND8_BAND11_ID 0x00a20554 /* MTSIF RX2 Band8 to Band11 ID Register */
-#define BCHP_XPT_FE_MTSIF_RX2_BAND12_BAND15_ID 0x00a20558 /* MTSIF RX2 Band12 to Band15 ID Register */
-#define BCHP_XPT_FE_MTSIF_RX2_BAND16_BAND19_ID 0x00a2055c /* MTSIF RX2 Band16 to Band19 ID Register */
-#define BCHP_XPT_FE_MTSIF_RX2_BAND20_BAND23_ID 0x00a20560 /* MTSIF RX2 Band20 to Band23 ID Register */
-#define BCHP_XPT_FE_MTSIF_RX2_BAND24_BAND27_ID 0x00a20564 /* MTSIF RX2 Band24 to Band27 ID Register */
-#define BCHP_XPT_FE_MTSIF_RX2_BAND28_BAND31_ID 0x00a20568 /* MTSIF RX2 Band28 to Band31 ID Register */
-#define BCHP_XPT_FE_MTSIF_RX2_BAND32_BAND35_ID 0x00a2056c /* MTSIF RX2 Band32 to Band35 ID Register */
-#define BCHP_XPT_FE_MTSIF_RX2_BAND36_BAND39_ID 0x00a20570 /* MTSIF RX2 Band36 to Band39 ID Register */
-#define BCHP_XPT_FE_MTSIF_RX2_BAND40_BAND43_ID 0x00a20574 /* MTSIF RX2 Band40 to Band43 ID Register */
-#define BCHP_XPT_FE_MTSIF_RX2_BAND44_BAND47_ID 0x00a20578 /* MTSIF RX2 Band44 to Band47 ID Register */
-#define BCHP_XPT_FE_MTSIF_RX2_BAND48_BAND51_ID 0x00a2057c /* MTSIF RX2 Band48 to Band51 ID Register */
-#define BCHP_XPT_FE_MTSIF_RX2_BAND52_BAND55_ID 0x00a20580 /* MTSIF RX2 Band52 to Band55 ID Register */
-#define BCHP_XPT_FE_MTSIF_RX2_BAND56_BAND59_ID 0x00a20584 /* MTSIF RX2 Band56 to Band59 ID Register */
-#define BCHP_XPT_FE_MTSIF_RX2_BAND60_BAND63_ID 0x00a20588 /* MTSIF RX2 Band60 to Band63 ID Register */
-#define BCHP_XPT_FE_MTSIF_RX2_PKT_BAND0_BAND31_DETECT 0x00a2058c /* MTSIF RX2 Packet Band0 to Band31 Detect Register */
-#define BCHP_XPT_FE_MTSIF_RX3_CTRL1 0x00a20590 /* FE_MTSIF_RX3_CTRL1 */
-#define BCHP_XPT_FE_MTSIF_RX3_SECRET_WORD 0x00a20594 /* MTSIF RX3 Secret Word Register */
-#define BCHP_XPT_FE_MTSIF_RX3_BAND0_BAND31_ID_DROP 0x00a20598 /* MTSIF RX3 Band0 to Band31 ID Drop Register */
-#define BCHP_XPT_FE_MTSIF_RX3_BAND0_BAND3_ID 0x00a2059c /* MTSIF RX3 Band0 to Band3 ID Register */
-#define BCHP_XPT_FE_MTSIF_RX3_BAND4_BAND7_ID 0x00a205a0 /* MTSIF RX3 Band4 to Band7 ID Register */
-#define BCHP_XPT_FE_MTSIF_RX3_BAND8_BAND11_ID 0x00a205a4 /* MTSIF RX3 Band8 to Band11 ID Register */
-#define BCHP_XPT_FE_MTSIF_RX3_BAND12_BAND15_ID 0x00a205a8 /* MTSIF RX3 Band12 to Band15 ID Register */
-#define BCHP_XPT_FE_MTSIF_RX3_BAND16_BAND19_ID 0x00a205ac /* MTSIF RX3 Band16 to Band19 ID Register */
-#define BCHP_XPT_FE_MTSIF_RX3_BAND20_BAND23_ID 0x00a205b0 /* MTSIF RX3 Band20 to Band23 ID Register */
-#define BCHP_XPT_FE_MTSIF_RX3_BAND24_BAND27_ID 0x00a205b4 /* MTSIF RX3 Band24 to Band27 ID Register */
-#define BCHP_XPT_FE_MTSIF_RX3_BAND28_BAND31_ID 0x00a205b8 /* MTSIF RX3 Band28 to Band31 ID Register */
-#define BCHP_XPT_FE_MTSIF_RX3_BAND32_BAND35_ID 0x00a205bc /* MTSIF RX3 Band32 to Band35 ID Register */
-#define BCHP_XPT_FE_MTSIF_RX3_BAND36_BAND39_ID 0x00a205c0 /* MTSIF RX3 Band36 to Band39 ID Register */
-#define BCHP_XPT_FE_MTSIF_RX3_BAND40_BAND43_ID 0x00a205c4 /* MTSIF RX3 Band40 to Band43 ID Register */
-#define BCHP_XPT_FE_MTSIF_RX3_BAND44_BAND47_ID 0x00a205c8 /* MTSIF RX3 Band44 to Band47 ID Register */
-#define BCHP_XPT_FE_MTSIF_RX3_BAND48_BAND51_ID 0x00a205cc /* MTSIF RX3 Band48 to Band51 ID Register */
-#define BCHP_XPT_FE_MTSIF_RX3_BAND52_BAND55_ID 0x00a205d0 /* MTSIF RX3 Band52 to Band55 ID Register */
-#define BCHP_XPT_FE_MTSIF_RX3_BAND56_BAND59_ID 0x00a205d4 /* MTSIF RX3 Band56 to Band59 ID Register */
-#define BCHP_XPT_FE_MTSIF_RX3_BAND60_BAND63_ID 0x00a205d8 /* MTSIF RX3 Band60 to Band63 ID Register */
-#define BCHP_XPT_FE_MTSIF_RX3_PKT_BAND0_BAND31_DETECT 0x00a205dc /* MTSIF RX3 Packet Band0 to Band31 Detect Register */
-#define BCHP_XPT_FE_MINI_PID_PARSER0_TB_CTRL1 0x00a20800 /* Data Transport Parser Band 0 Transponder Bonding Control Register */
-#define BCHP_XPT_FE_MINI_PID_PARSER0_SYNC_COUNT 0x00a20804 /* Data Transport Parser Band 0 Transponder Bonding Sync Counter Register */
-#define BCHP_XPT_FE_MINI_PID_PARSER1_TB_CTRL1 0x00a20808 /* Data Transport Parser Band 1 Transponder Bonding Control Register */
-#define BCHP_XPT_FE_MINI_PID_PARSER1_SYNC_COUNT 0x00a2080c /* Data Transport Parser Band 1 Transponder Bonding Sync Counter Register */
-#define BCHP_XPT_FE_MINI_PID_PARSER2_TB_CTRL1 0x00a20810 /* Data Transport Parser Band 2 Transponder Bonding Control Register */
-#define BCHP_XPT_FE_MINI_PID_PARSER2_SYNC_COUNT 0x00a20814 /* Data Transport Parser Band 2 Transponder Bonding Sync Counter Register */
-#define BCHP_XPT_FE_MINI_PID_PARSER3_TB_CTRL1 0x00a20818 /* Data Transport Parser Band 3 Transponder Bonding Control Register */
-#define BCHP_XPT_FE_MINI_PID_PARSER3_SYNC_COUNT 0x00a2081c /* Data Transport Parser Band 3 Transponder Bonding Sync Counter Register */
-#define BCHP_XPT_FE_MINI_PID_PARSER4_TB_CTRL1 0x00a20820 /* Data Transport Parser Band 4 Transponder Bonding Control Register */
-#define BCHP_XPT_FE_MINI_PID_PARSER4_SYNC_COUNT 0x00a20824 /* Data Transport Parser Band 4 Transponder Bonding Sync Counter Register */
-#define BCHP_XPT_FE_MINI_PID_PARSER5_TB_CTRL1 0x00a20828 /* Data Transport Parser Band 5 Transponder Bonding Control Register */
-#define BCHP_XPT_FE_MINI_PID_PARSER5_SYNC_COUNT 0x00a2082c /* Data Transport Parser Band 5 Transponder Bonding Sync Counter Register */
-#define BCHP_XPT_FE_MINI_PID_PARSER6_TB_CTRL1 0x00a20830 /* Data Transport Parser Band 6 Transponder Bonding Control Register */
-#define BCHP_XPT_FE_MINI_PID_PARSER6_SYNC_COUNT 0x00a20834 /* Data Transport Parser Band 6 Transponder Bonding Sync Counter Register */
-#define BCHP_XPT_FE_MINI_PID_PARSER7_TB_CTRL1 0x00a20838 /* Data Transport Parser Band 7 Transponder Bonding Control Register */
-#define BCHP_XPT_FE_MINI_PID_PARSER7_SYNC_COUNT 0x00a2083c /* Data Transport Parser Band 7 Transponder Bonding Sync Counter Register */
-#define BCHP_XPT_FE_MINI_PID_PARSER8_TB_CTRL1 0x00a20840 /* Data Transport Parser Band 8 Transponder Bonding Control Register */
-#define BCHP_XPT_FE_MINI_PID_PARSER8_SYNC_COUNT 0x00a20844 /* Data Transport Parser Band 8 Transponder Bonding Sync Counter Register */
-#define BCHP_XPT_FE_MINI_PID_PARSER9_TB_CTRL1 0x00a20848 /* Data Transport Parser Band 9 Transponder Bonding Control Register */
-#define BCHP_XPT_FE_MINI_PID_PARSER9_SYNC_COUNT 0x00a2084c /* Data Transport Parser Band 9 Transponder Bonding Sync Counter Register */
-#define BCHP_XPT_FE_MINI_PID_PARSER10_TB_CTRL1 0x00a20850 /* Data Transport Parser Band 10 Transponder Bonding Control Register */
-#define BCHP_XPT_FE_MINI_PID_PARSER10_SYNC_COUNT 0x00a20854 /* Data Transport Parser Band 10 Transponder Bonding Sync Counter Register */
-#define BCHP_XPT_FE_MINI_PID_PARSER11_TB_CTRL1 0x00a20858 /* Data Transport Parser Band 11 Transponder Bonding Control Register */
-#define BCHP_XPT_FE_MINI_PID_PARSER11_SYNC_COUNT 0x00a2085c /* Data Transport Parser Band 11 Transponder Bonding Sync Counter Register */
-#define BCHP_XPT_FE_MINI_PID_PARSER12_TB_CTRL1 0x00a20860 /* Data Transport Parser Band 12 Transponder Bonding Control Register */
-#define BCHP_XPT_FE_MINI_PID_PARSER12_SYNC_COUNT 0x00a20864 /* Data Transport Parser Band 12 Transponder Bonding Sync Counter Register */
-#define BCHP_XPT_FE_MINI_PID_PARSER13_TB_CTRL1 0x00a20868 /* Data Transport Parser Band 13 Transponder Bonding Control Register */
-#define BCHP_XPT_FE_MINI_PID_PARSER13_SYNC_COUNT 0x00a2086c /* Data Transport Parser Band 13 Transponder Bonding Sync Counter Register */
-#define BCHP_XPT_FE_MINI_PID_PARSER14_TB_CTRL1 0x00a20870 /* Data Transport Parser Band 14 Transponder Bonding Control Register */
-#define BCHP_XPT_FE_MINI_PID_PARSER14_SYNC_COUNT 0x00a20874 /* Data Transport Parser Band 14 Transponder Bonding Sync Counter Register */
-#define BCHP_XPT_FE_MINI_PID_PARSER15_TB_CTRL1 0x00a20878 /* Data Transport Parser Band 15 Transponder Bonding Control Register */
-#define BCHP_XPT_FE_MINI_PID_PARSER15_SYNC_COUNT 0x00a2087c /* Data Transport Parser Band 15 Transponder Bonding Sync Counter Register */
-#define BCHP_XPT_FE_MINI_PID_PARSER16_TB_CTRL1 0x00a20880 /* Data Transport Parser Band 16 Transponder Bonding Control Register */
-#define BCHP_XPT_FE_MINI_PID_PARSER16_SYNC_COUNT 0x00a20884 /* Data Transport Parser Band 16 Transponder Bonding Sync Counter Register */
-#define BCHP_XPT_FE_MINI_PID_PARSER17_TB_CTRL1 0x00a20888 /* Data Transport Parser Band 17 Transponder Bonding Control Register */
-#define BCHP_XPT_FE_MINI_PID_PARSER17_SYNC_COUNT 0x00a2088c /* Data Transport Parser Band 17 Transponder Bonding Sync Counter Register */
-#define BCHP_XPT_FE_MINI_PID_PARSER18_TB_CTRL1 0x00a20890 /* Data Transport Parser Band 18 Transponder Bonding Control Register */
-#define BCHP_XPT_FE_MINI_PID_PARSER18_SYNC_COUNT 0x00a20894 /* Data Transport Parser Band 18 Transponder Bonding Sync Counter Register */
-#define BCHP_XPT_FE_MINI_PID_PARSER19_TB_CTRL1 0x00a20898 /* Data Transport Parser Band 19 Transponder Bonding Control Register */
-#define BCHP_XPT_FE_MINI_PID_PARSER19_SYNC_COUNT 0x00a2089c /* Data Transport Parser Band 19 Transponder Bonding Sync Counter Register */
-#define BCHP_XPT_FE_MINI_PID_PARSER20_TB_CTRL1 0x00a208a0 /* Data Transport Parser Band 20 Transponder Bonding Control Register */
-#define BCHP_XPT_FE_MINI_PID_PARSER20_SYNC_COUNT 0x00a208a4 /* Data Transport Parser Band 20 Transponder Bonding Sync Counter Register */
-#define BCHP_XPT_FE_MINI_PID_PARSER21_TB_CTRL1 0x00a208a8 /* Data Transport Parser Band 21 Transponder Bonding Control Register */
-#define BCHP_XPT_FE_MINI_PID_PARSER21_SYNC_COUNT 0x00a208ac /* Data Transport Parser Band 21 Transponder Bonding Sync Counter Register */
-#define BCHP_XPT_FE_MINI_PID_PARSER22_TB_CTRL1 0x00a208b0 /* Data Transport Parser Band 22 Transponder Bonding Control Register */
-#define BCHP_XPT_FE_MINI_PID_PARSER22_SYNC_COUNT 0x00a208b4 /* Data Transport Parser Band 22 Transponder Bonding Sync Counter Register */
-#define BCHP_XPT_FE_MINI_PID_PARSER23_TB_CTRL1 0x00a208b8 /* Data Transport Parser Band 23 Transponder Bonding Control Register */
-#define BCHP_XPT_FE_MINI_PID_PARSER23_SYNC_COUNT 0x00a208bc /* Data Transport Parser Band 23 Transponder Bonding Sync Counter Register */
-#define BCHP_XPT_FE_TB_GLOBAL_CTRL1 0x00a20900 /* Transponder Bonding Global Control Register 1 */
-#define BCHP_XPT_FE_TB_PARSERS_PRIVATE_DATA_LENGTH_ERROR_STATUS0_REG 0x00a2090c /* Parsers Private Data Length Error Status Register */
-#define BCHP_XPT_FE_TB_PARSERS_PRIVATE_DATA_FIELD_LENGTH_ERROR_STATUS0_REG 0x00a20910 /* Parsers Private Data Field Length Error Status Register */
-
-/***************************************************************************
- *FE_CTRL - Data Transport Front-End Control Register
- ***************************************************************************/
-/* XPT_FE :: FE_CTRL :: reserved0 [31:13] */
-#define BCHP_XPT_FE_FE_CTRL_reserved0_MASK 0xffffe000
-#define BCHP_XPT_FE_FE_CTRL_reserved0_SHIFT 13
-
-/* XPT_FE :: FE_CTRL :: SW_CTRL_PID_VERSION_INCR_EN [12:12] */
-#define BCHP_XPT_FE_FE_CTRL_SW_CTRL_PID_VERSION_INCR_EN_MASK 0x00001000
-#define BCHP_XPT_FE_FE_CTRL_SW_CTRL_PID_VERSION_INCR_EN_SHIFT 12
-#define BCHP_XPT_FE_FE_CTRL_SW_CTRL_PID_VERSION_INCR_EN_DEFAULT 0x00000000
-
-/* XPT_FE :: FE_CTRL :: reserved1 [11:09] */
-#define BCHP_XPT_FE_FE_CTRL_reserved1_MASK 0x00000e00
-#define BCHP_XPT_FE_FE_CTRL_reserved1_SHIFT 9
-
-/* XPT_FE :: FE_CTRL :: SPARE_FUNC [08:02] */
-#define BCHP_XPT_FE_FE_CTRL_SPARE_FUNC_MASK 0x000001fc
-#define BCHP_XPT_FE_FE_CTRL_SPARE_FUNC_SHIFT 2
-#define BCHP_XPT_FE_FE_CTRL_SPARE_FUNC_DEFAULT 0x00000000
-
-/* XPT_FE :: FE_CTRL :: MPOD_OP_PSUB_NULL_PKT_EN [01:01] */
-#define BCHP_XPT_FE_FE_CTRL_MPOD_OP_PSUB_NULL_PKT_EN_MASK 0x00000002
-#define BCHP_XPT_FE_FE_CTRL_MPOD_OP_PSUB_NULL_PKT_EN_SHIFT 1
-#define BCHP_XPT_FE_FE_CTRL_MPOD_OP_PSUB_NULL_PKT_EN_DEFAULT 0x00000000
-
-/* XPT_FE :: FE_CTRL :: ERROR_INT_TEST_MODE [00:00] */
-#define BCHP_XPT_FE_FE_CTRL_ERROR_INT_TEST_MODE_MASK 0x00000001
-#define BCHP_XPT_FE_FE_CTRL_ERROR_INT_TEST_MODE_SHIFT 0
-#define BCHP_XPT_FE_FE_CTRL_ERROR_INT_TEST_MODE_DEFAULT 0x00000000
-
-/***************************************************************************
- *PWR_CTRL - Data Transport Front-End Power Control Register
- ***************************************************************************/
-/* XPT_FE :: PWR_CTRL :: reserved0 [31:01] */
-#define BCHP_XPT_FE_PWR_CTRL_reserved0_MASK 0xfffffffe
-#define BCHP_XPT_FE_PWR_CTRL_reserved0_SHIFT 1
-
-/* XPT_FE :: PWR_CTRL :: FE_TIMESTAMP_DIS [00:00] */
-#define BCHP_XPT_FE_PWR_CTRL_FE_TIMESTAMP_DIS_MASK 0x00000001
-#define BCHP_XPT_FE_PWR_CTRL_FE_TIMESTAMP_DIS_SHIFT 0
-#define BCHP_XPT_FE_PWR_CTRL_FE_TIMESTAMP_DIS_DEFAULT 0x00000000
-
-/***************************************************************************
- *MAX_PID_CHANNEL - Maximum Pid Channel number register
- ***************************************************************************/
-/* XPT_FE :: MAX_PID_CHANNEL :: reserved0 [31:12] */
-#define BCHP_XPT_FE_MAX_PID_CHANNEL_reserved0_MASK 0xfffff000
-#define BCHP_XPT_FE_MAX_PID_CHANNEL_reserved0_SHIFT 12
-
-/* XPT_FE :: MAX_PID_CHANNEL :: MAX_PID_CHANNEL [11:00] */
-#define BCHP_XPT_FE_MAX_PID_CHANNEL_MAX_PID_CHANNEL_MASK 0x00000fff
-#define BCHP_XPT_FE_MAX_PID_CHANNEL_MAX_PID_CHANNEL_SHIFT 0
-#define BCHP_XPT_FE_MAX_PID_CHANNEL_MAX_PID_CHANNEL_DEFAULT 0x000003ff
-
-/***************************************************************************
- *IB_SYNC_DETECT_CTRL - Data Transport Input Band Sync detect control
- ***************************************************************************/
-/* XPT_FE :: IB_SYNC_DETECT_CTRL :: reserved0 [31:06] */
-#define BCHP_XPT_FE_IB_SYNC_DETECT_CTRL_reserved0_MASK 0xffffffc0
-#define BCHP_XPT_FE_IB_SYNC_DETECT_CTRL_reserved0_SHIFT 6
-
-/* XPT_FE :: IB_SYNC_DETECT_CTRL :: IB_SYNC_OUT_CNT [05:03] */
-#define BCHP_XPT_FE_IB_SYNC_DETECT_CTRL_IB_SYNC_OUT_CNT_MASK 0x00000038
-#define BCHP_XPT_FE_IB_SYNC_DETECT_CTRL_IB_SYNC_OUT_CNT_SHIFT 3
-#define BCHP_XPT_FE_IB_SYNC_DETECT_CTRL_IB_SYNC_OUT_CNT_DEFAULT 0x00000000
-
-/* XPT_FE :: IB_SYNC_DETECT_CTRL :: IB_SYNC_IN_CNT [02:00] */
-#define BCHP_XPT_FE_IB_SYNC_DETECT_CTRL_IB_SYNC_IN_CNT_MASK 0x00000007
-#define BCHP_XPT_FE_IB_SYNC_DETECT_CTRL_IB_SYNC_IN_CNT_SHIFT 0
-#define BCHP_XPT_FE_IB_SYNC_DETECT_CTRL_IB_SYNC_IN_CNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *INTR_STATUS0_REG - Interrupt Status Register
- ***************************************************************************/
-/* XPT_FE :: INTR_STATUS0_REG :: PARSER31_LENGTH_ERROR [31:31] */
-#define BCHP_XPT_FE_INTR_STATUS0_REG_PARSER31_LENGTH_ERROR_MASK 0x80000000
-#define BCHP_XPT_FE_INTR_STATUS0_REG_PARSER31_LENGTH_ERROR_SHIFT 31
-#define BCHP_XPT_FE_INTR_STATUS0_REG_PARSER31_LENGTH_ERROR_DEFAULT 0x00000000
-
-/* XPT_FE :: INTR_STATUS0_REG :: PARSER30_LENGTH_ERROR [30:30] */
-#define BCHP_XPT_FE_INTR_STATUS0_REG_PARSER30_LENGTH_ERROR_MASK 0x40000000
-#define BCHP_XPT_FE_INTR_STATUS0_REG_PARSER30_LENGTH_ERROR_SHIFT 30
-#define BCHP_XPT_FE_INTR_STATUS0_REG_PARSER30_LENGTH_ERROR_DEFAULT 0x00000000
-
-/* XPT_FE :: INTR_STATUS0_REG :: PARSER29_LENGTH_ERROR [29:29] */
-#define BCHP_XPT_FE_INTR_STATUS0_REG_PARSER29_LENGTH_ERROR_MASK 0x20000000
-#define BCHP_XPT_FE_INTR_STATUS0_REG_PARSER29_LENGTH_ERROR_SHIFT 29
-#define BCHP_XPT_FE_INTR_STATUS0_REG_PARSER29_LENGTH_ERROR_DEFAULT 0x00000000
-
-/* XPT_FE :: INTR_STATUS0_REG :: PARSER28_LENGTH_ERROR [28:28] */
-#define BCHP_XPT_FE_INTR_STATUS0_REG_PARSER28_LENGTH_ERROR_MASK 0x10000000
-#define BCHP_XPT_FE_INTR_STATUS0_REG_PARSER28_LENGTH_ERROR_SHIFT 28
-#define BCHP_XPT_FE_INTR_STATUS0_REG_PARSER28_LENGTH_ERROR_DEFAULT 0x00000000
-
-/* XPT_FE :: INTR_STATUS0_REG :: PARSER27_LENGTH_ERROR [27:27] */
-#define BCHP_XPT_FE_INTR_STATUS0_REG_PARSER27_LENGTH_ERROR_MASK 0x08000000
-#define BCHP_XPT_FE_INTR_STATUS0_REG_PARSER27_LENGTH_ERROR_SHIFT 27
-#define BCHP_XPT_FE_INTR_STATUS0_REG_PARSER27_LENGTH_ERROR_DEFAULT 0x00000000
-
-/* XPT_FE :: INTR_STATUS0_REG :: PARSER26_LENGTH_ERROR [26:26] */
-#define BCHP_XPT_FE_INTR_STATUS0_REG_PARSER26_LENGTH_ERROR_MASK 0x04000000
-#define BCHP_XPT_FE_INTR_STATUS0_REG_PARSER26_LENGTH_ERROR_SHIFT 26
-#define BCHP_XPT_FE_INTR_STATUS0_REG_PARSER26_LENGTH_ERROR_DEFAULT 0x00000000
-
-/* XPT_FE :: INTR_STATUS0_REG :: PARSER25_LENGTH_ERROR [25:25] */
-#define BCHP_XPT_FE_INTR_STATUS0_REG_PARSER25_LENGTH_ERROR_MASK 0x02000000
-#define BCHP_XPT_FE_INTR_STATUS0_REG_PARSER25_LENGTH_ERROR_SHIFT 25
-#define BCHP_XPT_FE_INTR_STATUS0_REG_PARSER25_LENGTH_ERROR_DEFAULT 0x00000000
-
-/* XPT_FE :: INTR_STATUS0_REG :: PARSER24_LENGTH_ERROR [24:24] */
-#define BCHP_XPT_FE_INTR_STATUS0_REG_PARSER24_LENGTH_ERROR_MASK 0x01000000
-#define BCHP_XPT_FE_INTR_STATUS0_REG_PARSER24_LENGTH_ERROR_SHIFT 24
-#define BCHP_XPT_FE_INTR_STATUS0_REG_PARSER24_LENGTH_ERROR_DEFAULT 0x00000000
-
-/* XPT_FE :: INTR_STATUS0_REG :: PARSER23_LENGTH_ERROR [23:23] */
-#define BCHP_XPT_FE_INTR_STATUS0_REG_PARSER23_LENGTH_ERROR_MASK 0x00800000
-#define BCHP_XPT_FE_INTR_STATUS0_REG_PARSER23_LENGTH_ERROR_SHIFT 23
-#define BCHP_XPT_FE_INTR_STATUS0_REG_PARSER23_LENGTH_ERROR_DEFAULT 0x00000000
-
-/* XPT_FE :: INTR_STATUS0_REG :: PARSER22_LENGTH_ERROR [22:22] */
-#define BCHP_XPT_FE_INTR_STATUS0_REG_PARSER22_LENGTH_ERROR_MASK 0x00400000
-#define BCHP_XPT_FE_INTR_STATUS0_REG_PARSER22_LENGTH_ERROR_SHIFT 22
-#define BCHP_XPT_FE_INTR_STATUS0_REG_PARSER22_LENGTH_ERROR_DEFAULT 0x00000000
-
-/* XPT_FE :: INTR_STATUS0_REG :: PARSER21_LENGTH_ERROR [21:21] */
-#define BCHP_XPT_FE_INTR_STATUS0_REG_PARSER21_LENGTH_ERROR_MASK 0x00200000
-#define BCHP_XPT_FE_INTR_STATUS0_REG_PARSER21_LENGTH_ERROR_SHIFT 21
-#define BCHP_XPT_FE_INTR_STATUS0_REG_PARSER21_LENGTH_ERROR_DEFAULT 0x00000000
-
-/* XPT_FE :: INTR_STATUS0_REG :: PARSER20_LENGTH_ERROR [20:20] */
-#define BCHP_XPT_FE_INTR_STATUS0_REG_PARSER20_LENGTH_ERROR_MASK 0x00100000
-#define BCHP_XPT_FE_INTR_STATUS0_REG_PARSER20_LENGTH_ERROR_SHIFT 20
-#define BCHP_XPT_FE_INTR_STATUS0_REG_PARSER20_LENGTH_ERROR_DEFAULT 0x00000000
-
-/* XPT_FE :: INTR_STATUS0_REG :: PARSER19_LENGTH_ERROR [19:19] */
-#define BCHP_XPT_FE_INTR_STATUS0_REG_PARSER19_LENGTH_ERROR_MASK 0x00080000
-#define BCHP_XPT_FE_INTR_STATUS0_REG_PARSER19_LENGTH_ERROR_SHIFT 19
-#define BCHP_XPT_FE_INTR_STATUS0_REG_PARSER19_LENGTH_ERROR_DEFAULT 0x00000000
-
-/* XPT_FE :: INTR_STATUS0_REG :: PARSER18_LENGTH_ERROR [18:18] */
-#define BCHP_XPT_FE_INTR_STATUS0_REG_PARSER18_LENGTH_ERROR_MASK 0x00040000
-#define BCHP_XPT_FE_INTR_STATUS0_REG_PARSER18_LENGTH_ERROR_SHIFT 18
-#define BCHP_XPT_FE_INTR_STATUS0_REG_PARSER18_LENGTH_ERROR_DEFAULT 0x00000000
-
-/* XPT_FE :: INTR_STATUS0_REG :: PARSER17_LENGTH_ERROR [17:17] */
-#define BCHP_XPT_FE_INTR_STATUS0_REG_PARSER17_LENGTH_ERROR_MASK 0x00020000
-#define BCHP_XPT_FE_INTR_STATUS0_REG_PARSER17_LENGTH_ERROR_SHIFT 17
-#define BCHP_XPT_FE_INTR_STATUS0_REG_PARSER17_LENGTH_ERROR_DEFAULT 0x00000000
-
-/* XPT_FE :: INTR_STATUS0_REG :: PARSER16_LENGTH_ERROR [16:16] */
-#define BCHP_XPT_FE_INTR_STATUS0_REG_PARSER16_LENGTH_ERROR_MASK 0x00010000
-#define BCHP_XPT_FE_INTR_STATUS0_REG_PARSER16_LENGTH_ERROR_SHIFT 16
-#define BCHP_XPT_FE_INTR_STATUS0_REG_PARSER16_LENGTH_ERROR_DEFAULT 0x00000000
-
-/* XPT_FE :: INTR_STATUS0_REG :: PARSER15_LENGTH_ERROR [15:15] */
-#define BCHP_XPT_FE_INTR_STATUS0_REG_PARSER15_LENGTH_ERROR_MASK 0x00008000
-#define BCHP_XPT_FE_INTR_STATUS0_REG_PARSER15_LENGTH_ERROR_SHIFT 15
-#define BCHP_XPT_FE_INTR_STATUS0_REG_PARSER15_LENGTH_ERROR_DEFAULT 0x00000000
-
-/* XPT_FE :: INTR_STATUS0_REG :: PARSER14_LENGTH_ERROR [14:14] */
-#define BCHP_XPT_FE_INTR_STATUS0_REG_PARSER14_LENGTH_ERROR_MASK 0x00004000
-#define BCHP_XPT_FE_INTR_STATUS0_REG_PARSER14_LENGTH_ERROR_SHIFT 14
-#define BCHP_XPT_FE_INTR_STATUS0_REG_PARSER14_LENGTH_ERROR_DEFAULT 0x00000000
-
-/* XPT_FE :: INTR_STATUS0_REG :: PARSER13_LENGTH_ERROR [13:13] */
-#define BCHP_XPT_FE_INTR_STATUS0_REG_PARSER13_LENGTH_ERROR_MASK 0x00002000
-#define BCHP_XPT_FE_INTR_STATUS0_REG_PARSER13_LENGTH_ERROR_SHIFT 13
-#define BCHP_XPT_FE_INTR_STATUS0_REG_PARSER13_LENGTH_ERROR_DEFAULT 0x00000000
-
-/* XPT_FE :: INTR_STATUS0_REG :: PARSER12_LENGTH_ERROR [12:12] */
-#define BCHP_XPT_FE_INTR_STATUS0_REG_PARSER12_LENGTH_ERROR_MASK 0x00001000
-#define BCHP_XPT_FE_INTR_STATUS0_REG_PARSER12_LENGTH_ERROR_SHIFT 12
-#define BCHP_XPT_FE_INTR_STATUS0_REG_PARSER12_LENGTH_ERROR_DEFAULT 0x00000000
-
-/* XPT_FE :: INTR_STATUS0_REG :: PARSER11_LENGTH_ERROR [11:11] */
-#define BCHP_XPT_FE_INTR_STATUS0_REG_PARSER11_LENGTH_ERROR_MASK 0x00000800
-#define BCHP_XPT_FE_INTR_STATUS0_REG_PARSER11_LENGTH_ERROR_SHIFT 11
-#define BCHP_XPT_FE_INTR_STATUS0_REG_PARSER11_LENGTH_ERROR_DEFAULT 0x00000000
-
-/* XPT_FE :: INTR_STATUS0_REG :: PARSER10_LENGTH_ERROR [10:10] */
-#define BCHP_XPT_FE_INTR_STATUS0_REG_PARSER10_LENGTH_ERROR_MASK 0x00000400
-#define BCHP_XPT_FE_INTR_STATUS0_REG_PARSER10_LENGTH_ERROR_SHIFT 10
-#define BCHP_XPT_FE_INTR_STATUS0_REG_PARSER10_LENGTH_ERROR_DEFAULT 0x00000000
-
-/* XPT_FE :: INTR_STATUS0_REG :: PARSER9_LENGTH_ERROR [09:09] */
-#define BCHP_XPT_FE_INTR_STATUS0_REG_PARSER9_LENGTH_ERROR_MASK 0x00000200
-#define BCHP_XPT_FE_INTR_STATUS0_REG_PARSER9_LENGTH_ERROR_SHIFT 9
-#define BCHP_XPT_FE_INTR_STATUS0_REG_PARSER9_LENGTH_ERROR_DEFAULT 0x00000000
-
-/* XPT_FE :: INTR_STATUS0_REG :: PARSER8_LENGTH_ERROR [08:08] */
-#define BCHP_XPT_FE_INTR_STATUS0_REG_PARSER8_LENGTH_ERROR_MASK 0x00000100
-#define BCHP_XPT_FE_INTR_STATUS0_REG_PARSER8_LENGTH_ERROR_SHIFT 8
-#define BCHP_XPT_FE_INTR_STATUS0_REG_PARSER8_LENGTH_ERROR_DEFAULT 0x00000000
-
-/* XPT_FE :: INTR_STATUS0_REG :: PARSER7_LENGTH_ERROR [07:07] */
-#define BCHP_XPT_FE_INTR_STATUS0_REG_PARSER7_LENGTH_ERROR_MASK 0x00000080
-#define BCHP_XPT_FE_INTR_STATUS0_REG_PARSER7_LENGTH_ERROR_SHIFT 7
-#define BCHP_XPT_FE_INTR_STATUS0_REG_PARSER7_LENGTH_ERROR_DEFAULT 0x00000000
-
-/* XPT_FE :: INTR_STATUS0_REG :: PARSER6_LENGTH_ERROR [06:06] */
-#define BCHP_XPT_FE_INTR_STATUS0_REG_PARSER6_LENGTH_ERROR_MASK 0x00000040
-#define BCHP_XPT_FE_INTR_STATUS0_REG_PARSER6_LENGTH_ERROR_SHIFT 6
-#define BCHP_XPT_FE_INTR_STATUS0_REG_PARSER6_LENGTH_ERROR_DEFAULT 0x00000000
-
-/* XPT_FE :: INTR_STATUS0_REG :: PARSER5_LENGTH_ERROR [05:05] */
-#define BCHP_XPT_FE_INTR_STATUS0_REG_PARSER5_LENGTH_ERROR_MASK 0x00000020
-#define BCHP_XPT_FE_INTR_STATUS0_REG_PARSER5_LENGTH_ERROR_SHIFT 5
-#define BCHP_XPT_FE_INTR_STATUS0_REG_PARSER5_LENGTH_ERROR_DEFAULT 0x00000000
-
-/* XPT_FE :: INTR_STATUS0_REG :: PARSER4_LENGTH_ERROR [04:04] */
-#define BCHP_XPT_FE_INTR_STATUS0_REG_PARSER4_LENGTH_ERROR_MASK 0x00000010
-#define BCHP_XPT_FE_INTR_STATUS0_REG_PARSER4_LENGTH_ERROR_SHIFT 4
-#define BCHP_XPT_FE_INTR_STATUS0_REG_PARSER4_LENGTH_ERROR_DEFAULT 0x00000000
-
-/* XPT_FE :: INTR_STATUS0_REG :: PARSER3_LENGTH_ERROR [03:03] */
-#define BCHP_XPT_FE_INTR_STATUS0_REG_PARSER3_LENGTH_ERROR_MASK 0x00000008
-#define BCHP_XPT_FE_INTR_STATUS0_REG_PARSER3_LENGTH_ERROR_SHIFT 3
-#define BCHP_XPT_FE_INTR_STATUS0_REG_PARSER3_LENGTH_ERROR_DEFAULT 0x00000000
-
-/* XPT_FE :: INTR_STATUS0_REG :: PARSER2_LENGTH_ERROR [02:02] */
-#define BCHP_XPT_FE_INTR_STATUS0_REG_PARSER2_LENGTH_ERROR_MASK 0x00000004
-#define BCHP_XPT_FE_INTR_STATUS0_REG_PARSER2_LENGTH_ERROR_SHIFT 2
-#define BCHP_XPT_FE_INTR_STATUS0_REG_PARSER2_LENGTH_ERROR_DEFAULT 0x00000000
-
-/* XPT_FE :: INTR_STATUS0_REG :: PARSER1_LENGTH_ERROR [01:01] */
-#define BCHP_XPT_FE_INTR_STATUS0_REG_PARSER1_LENGTH_ERROR_MASK 0x00000002
-#define BCHP_XPT_FE_INTR_STATUS0_REG_PARSER1_LENGTH_ERROR_SHIFT 1
-#define BCHP_XPT_FE_INTR_STATUS0_REG_PARSER1_LENGTH_ERROR_DEFAULT 0x00000000
-
-/* XPT_FE :: INTR_STATUS0_REG :: PARSER0_LENGTH_ERROR [00:00] */
-#define BCHP_XPT_FE_INTR_STATUS0_REG_PARSER0_LENGTH_ERROR_MASK 0x00000001
-#define BCHP_XPT_FE_INTR_STATUS0_REG_PARSER0_LENGTH_ERROR_SHIFT 0
-#define BCHP_XPT_FE_INTR_STATUS0_REG_PARSER0_LENGTH_ERROR_DEFAULT 0x00000000
-
-/***************************************************************************
- *INTR_STATUS1_REG - Interrupt Status Register
- ***************************************************************************/
-/* XPT_FE :: INTR_STATUS1_REG :: PARSER31_TRANSPORT_ERROR [31:31] */
-#define BCHP_XPT_FE_INTR_STATUS1_REG_PARSER31_TRANSPORT_ERROR_MASK 0x80000000
-#define BCHP_XPT_FE_INTR_STATUS1_REG_PARSER31_TRANSPORT_ERROR_SHIFT 31
-#define BCHP_XPT_FE_INTR_STATUS1_REG_PARSER31_TRANSPORT_ERROR_DEFAULT 0x00000000
-
-/* XPT_FE :: INTR_STATUS1_REG :: PARSER30_TRANSPORT_ERROR [30:30] */
-#define BCHP_XPT_FE_INTR_STATUS1_REG_PARSER30_TRANSPORT_ERROR_MASK 0x40000000
-#define BCHP_XPT_FE_INTR_STATUS1_REG_PARSER30_TRANSPORT_ERROR_SHIFT 30
-#define BCHP_XPT_FE_INTR_STATUS1_REG_PARSER30_TRANSPORT_ERROR_DEFAULT 0x00000000
-
-/* XPT_FE :: INTR_STATUS1_REG :: PARSER29_TRANSPORT_ERROR [29:29] */
-#define BCHP_XPT_FE_INTR_STATUS1_REG_PARSER29_TRANSPORT_ERROR_MASK 0x20000000
-#define BCHP_XPT_FE_INTR_STATUS1_REG_PARSER29_TRANSPORT_ERROR_SHIFT 29
-#define BCHP_XPT_FE_INTR_STATUS1_REG_PARSER29_TRANSPORT_ERROR_DEFAULT 0x00000000
-
-/* XPT_FE :: INTR_STATUS1_REG :: PARSER28_TRANSPORT_ERROR [28:28] */
-#define BCHP_XPT_FE_INTR_STATUS1_REG_PARSER28_TRANSPORT_ERROR_MASK 0x10000000
-#define BCHP_XPT_FE_INTR_STATUS1_REG_PARSER28_TRANSPORT_ERROR_SHIFT 28
-#define BCHP_XPT_FE_INTR_STATUS1_REG_PARSER28_TRANSPORT_ERROR_DEFAULT 0x00000000
-
-/* XPT_FE :: INTR_STATUS1_REG :: PARSER27_TRANSPORT_ERROR [27:27] */
-#define BCHP_XPT_FE_INTR_STATUS1_REG_PARSER27_TRANSPORT_ERROR_MASK 0x08000000
-#define BCHP_XPT_FE_INTR_STATUS1_REG_PARSER27_TRANSPORT_ERROR_SHIFT 27
-#define BCHP_XPT_FE_INTR_STATUS1_REG_PARSER27_TRANSPORT_ERROR_DEFAULT 0x00000000
-
-/* XPT_FE :: INTR_STATUS1_REG :: PARSER26_TRANSPORT_ERROR [26:26] */
-#define BCHP_XPT_FE_INTR_STATUS1_REG_PARSER26_TRANSPORT_ERROR_MASK 0x04000000
-#define BCHP_XPT_FE_INTR_STATUS1_REG_PARSER26_TRANSPORT_ERROR_SHIFT 26
-#define BCHP_XPT_FE_INTR_STATUS1_REG_PARSER26_TRANSPORT_ERROR_DEFAULT 0x00000000
-
-/* XPT_FE :: INTR_STATUS1_REG :: PARSER25_TRANSPORT_ERROR [25:25] */
-#define BCHP_XPT_FE_INTR_STATUS1_REG_PARSER25_TRANSPORT_ERROR_MASK 0x02000000
-#define BCHP_XPT_FE_INTR_STATUS1_REG_PARSER25_TRANSPORT_ERROR_SHIFT 25
-#define BCHP_XPT_FE_INTR_STATUS1_REG_PARSER25_TRANSPORT_ERROR_DEFAULT 0x00000000
-
-/* XPT_FE :: INTR_STATUS1_REG :: PARSER24_TRANSPORT_ERROR [24:24] */
-#define BCHP_XPT_FE_INTR_STATUS1_REG_PARSER24_TRANSPORT_ERROR_MASK 0x01000000
-#define BCHP_XPT_FE_INTR_STATUS1_REG_PARSER24_TRANSPORT_ERROR_SHIFT 24
-#define BCHP_XPT_FE_INTR_STATUS1_REG_PARSER24_TRANSPORT_ERROR_DEFAULT 0x00000000
-
-/* XPT_FE :: INTR_STATUS1_REG :: PARSER23_TRANSPORT_ERROR [23:23] */
-#define BCHP_XPT_FE_INTR_STATUS1_REG_PARSER23_TRANSPORT_ERROR_MASK 0x00800000
-#define BCHP_XPT_FE_INTR_STATUS1_REG_PARSER23_TRANSPORT_ERROR_SHIFT 23
-#define BCHP_XPT_FE_INTR_STATUS1_REG_PARSER23_TRANSPORT_ERROR_DEFAULT 0x00000000
-
-/* XPT_FE :: INTR_STATUS1_REG :: PARSER22_TRANSPORT_ERROR [22:22] */
-#define BCHP_XPT_FE_INTR_STATUS1_REG_PARSER22_TRANSPORT_ERROR_MASK 0x00400000
-#define BCHP_XPT_FE_INTR_STATUS1_REG_PARSER22_TRANSPORT_ERROR_SHIFT 22
-#define BCHP_XPT_FE_INTR_STATUS1_REG_PARSER22_TRANSPORT_ERROR_DEFAULT 0x00000000
-
-/* XPT_FE :: INTR_STATUS1_REG :: PARSER21_TRANSPORT_ERROR [21:21] */
-#define BCHP_XPT_FE_INTR_STATUS1_REG_PARSER21_TRANSPORT_ERROR_MASK 0x00200000
-#define BCHP_XPT_FE_INTR_STATUS1_REG_PARSER21_TRANSPORT_ERROR_SHIFT 21
-#define BCHP_XPT_FE_INTR_STATUS1_REG_PARSER21_TRANSPORT_ERROR_DEFAULT 0x00000000
-
-/* XPT_FE :: INTR_STATUS1_REG :: PARSER20_TRANSPORT_ERROR [20:20] */
-#define BCHP_XPT_FE_INTR_STATUS1_REG_PARSER20_TRANSPORT_ERROR_MASK 0x00100000
-#define BCHP_XPT_FE_INTR_STATUS1_REG_PARSER20_TRANSPORT_ERROR_SHIFT 20
-#define BCHP_XPT_FE_INTR_STATUS1_REG_PARSER20_TRANSPORT_ERROR_DEFAULT 0x00000000
-
-/* XPT_FE :: INTR_STATUS1_REG :: PARSER19_TRANSPORT_ERROR [19:19] */
-#define BCHP_XPT_FE_INTR_STATUS1_REG_PARSER19_TRANSPORT_ERROR_MASK 0x00080000
-#define BCHP_XPT_FE_INTR_STATUS1_REG_PARSER19_TRANSPORT_ERROR_SHIFT 19
-#define BCHP_XPT_FE_INTR_STATUS1_REG_PARSER19_TRANSPORT_ERROR_DEFAULT 0x00000000
-
-/* XPT_FE :: INTR_STATUS1_REG :: PARSER18_TRANSPORT_ERROR [18:18] */
-#define BCHP_XPT_FE_INTR_STATUS1_REG_PARSER18_TRANSPORT_ERROR_MASK 0x00040000
-#define BCHP_XPT_FE_INTR_STATUS1_REG_PARSER18_TRANSPORT_ERROR_SHIFT 18
-#define BCHP_XPT_FE_INTR_STATUS1_REG_PARSER18_TRANSPORT_ERROR_DEFAULT 0x00000000
-
-/* XPT_FE :: INTR_STATUS1_REG :: PARSER17_TRANSPORT_ERROR [17:17] */
-#define BCHP_XPT_FE_INTR_STATUS1_REG_PARSER17_TRANSPORT_ERROR_MASK 0x00020000
-#define BCHP_XPT_FE_INTR_STATUS1_REG_PARSER17_TRANSPORT_ERROR_SHIFT 17
-#define BCHP_XPT_FE_INTR_STATUS1_REG_PARSER17_TRANSPORT_ERROR_DEFAULT 0x00000000
-
-/* XPT_FE :: INTR_STATUS1_REG :: PARSER16_TRANSPORT_ERROR [16:16] */
-#define BCHP_XPT_FE_INTR_STATUS1_REG_PARSER16_TRANSPORT_ERROR_MASK 0x00010000
-#define BCHP_XPT_FE_INTR_STATUS1_REG_PARSER16_TRANSPORT_ERROR_SHIFT 16
-#define BCHP_XPT_FE_INTR_STATUS1_REG_PARSER16_TRANSPORT_ERROR_DEFAULT 0x00000000
-
-/* XPT_FE :: INTR_STATUS1_REG :: PARSER15_TRANSPORT_ERROR [15:15] */
-#define BCHP_XPT_FE_INTR_STATUS1_REG_PARSER15_TRANSPORT_ERROR_MASK 0x00008000
-#define BCHP_XPT_FE_INTR_STATUS1_REG_PARSER15_TRANSPORT_ERROR_SHIFT 15
-#define BCHP_XPT_FE_INTR_STATUS1_REG_PARSER15_TRANSPORT_ERROR_DEFAULT 0x00000000
-
-/* XPT_FE :: INTR_STATUS1_REG :: PARSER14_TRANSPORT_ERROR [14:14] */
-#define BCHP_XPT_FE_INTR_STATUS1_REG_PARSER14_TRANSPORT_ERROR_MASK 0x00004000
-#define BCHP_XPT_FE_INTR_STATUS1_REG_PARSER14_TRANSPORT_ERROR_SHIFT 14
-#define BCHP_XPT_FE_INTR_STATUS1_REG_PARSER14_TRANSPORT_ERROR_DEFAULT 0x00000000
-
-/* XPT_FE :: INTR_STATUS1_REG :: PARSER13_TRANSPORT_ERROR [13:13] */
-#define BCHP_XPT_FE_INTR_STATUS1_REG_PARSER13_TRANSPORT_ERROR_MASK 0x00002000
-#define BCHP_XPT_FE_INTR_STATUS1_REG_PARSER13_TRANSPORT_ERROR_SHIFT 13
-#define BCHP_XPT_FE_INTR_STATUS1_REG_PARSER13_TRANSPORT_ERROR_DEFAULT 0x00000000
-
-/* XPT_FE :: INTR_STATUS1_REG :: PARSER12_TRANSPORT_ERROR [12:12] */
-#define BCHP_XPT_FE_INTR_STATUS1_REG_PARSER12_TRANSPORT_ERROR_MASK 0x00001000
-#define BCHP_XPT_FE_INTR_STATUS1_REG_PARSER12_TRANSPORT_ERROR_SHIFT 12
-#define BCHP_XPT_FE_INTR_STATUS1_REG_PARSER12_TRANSPORT_ERROR_DEFAULT 0x00000000
-
-/* XPT_FE :: INTR_STATUS1_REG :: PARSER11_TRANSPORT_ERROR [11:11] */
-#define BCHP_XPT_FE_INTR_STATUS1_REG_PARSER11_TRANSPORT_ERROR_MASK 0x00000800
-#define BCHP_XPT_FE_INTR_STATUS1_REG_PARSER11_TRANSPORT_ERROR_SHIFT 11
-#define BCHP_XPT_FE_INTR_STATUS1_REG_PARSER11_TRANSPORT_ERROR_DEFAULT 0x00000000
-
-/* XPT_FE :: INTR_STATUS1_REG :: PARSER10_TRANSPORT_ERROR [10:10] */
-#define BCHP_XPT_FE_INTR_STATUS1_REG_PARSER10_TRANSPORT_ERROR_MASK 0x00000400
-#define BCHP_XPT_FE_INTR_STATUS1_REG_PARSER10_TRANSPORT_ERROR_SHIFT 10
-#define BCHP_XPT_FE_INTR_STATUS1_REG_PARSER10_TRANSPORT_ERROR_DEFAULT 0x00000000
-
-/* XPT_FE :: INTR_STATUS1_REG :: PARSER9_TRANSPORT_ERROR [09:09] */
-#define BCHP_XPT_FE_INTR_STATUS1_REG_PARSER9_TRANSPORT_ERROR_MASK 0x00000200
-#define BCHP_XPT_FE_INTR_STATUS1_REG_PARSER9_TRANSPORT_ERROR_SHIFT 9
-#define BCHP_XPT_FE_INTR_STATUS1_REG_PARSER9_TRANSPORT_ERROR_DEFAULT 0x00000000
-
-/* XPT_FE :: INTR_STATUS1_REG :: PARSER8_TRANSPORT_ERROR [08:08] */
-#define BCHP_XPT_FE_INTR_STATUS1_REG_PARSER8_TRANSPORT_ERROR_MASK 0x00000100
-#define BCHP_XPT_FE_INTR_STATUS1_REG_PARSER8_TRANSPORT_ERROR_SHIFT 8
-#define BCHP_XPT_FE_INTR_STATUS1_REG_PARSER8_TRANSPORT_ERROR_DEFAULT 0x00000000
-
-/* XPT_FE :: INTR_STATUS1_REG :: PARSER7_TRANSPORT_ERROR [07:07] */
-#define BCHP_XPT_FE_INTR_STATUS1_REG_PARSER7_TRANSPORT_ERROR_MASK 0x00000080
-#define BCHP_XPT_FE_INTR_STATUS1_REG_PARSER7_TRANSPORT_ERROR_SHIFT 7
-#define BCHP_XPT_FE_INTR_STATUS1_REG_PARSER7_TRANSPORT_ERROR_DEFAULT 0x00000000
-
-/* XPT_FE :: INTR_STATUS1_REG :: PARSER6_TRANSPORT_ERROR [06:06] */
-#define BCHP_XPT_FE_INTR_STATUS1_REG_PARSER6_TRANSPORT_ERROR_MASK 0x00000040
-#define BCHP_XPT_FE_INTR_STATUS1_REG_PARSER6_TRANSPORT_ERROR_SHIFT 6
-#define BCHP_XPT_FE_INTR_STATUS1_REG_PARSER6_TRANSPORT_ERROR_DEFAULT 0x00000000
-
-/* XPT_FE :: INTR_STATUS1_REG :: PARSER5_TRANSPORT_ERROR [05:05] */
-#define BCHP_XPT_FE_INTR_STATUS1_REG_PARSER5_TRANSPORT_ERROR_MASK 0x00000020
-#define BCHP_XPT_FE_INTR_STATUS1_REG_PARSER5_TRANSPORT_ERROR_SHIFT 5
-#define BCHP_XPT_FE_INTR_STATUS1_REG_PARSER5_TRANSPORT_ERROR_DEFAULT 0x00000000
-
-/* XPT_FE :: INTR_STATUS1_REG :: PARSER4_TRANSPORT_ERROR [04:04] */
-#define BCHP_XPT_FE_INTR_STATUS1_REG_PARSER4_TRANSPORT_ERROR_MASK 0x00000010
-#define BCHP_XPT_FE_INTR_STATUS1_REG_PARSER4_TRANSPORT_ERROR_SHIFT 4
-#define BCHP_XPT_FE_INTR_STATUS1_REG_PARSER4_TRANSPORT_ERROR_DEFAULT 0x00000000
-
-/* XPT_FE :: INTR_STATUS1_REG :: PARSER3_TRANSPORT_ERROR [03:03] */
-#define BCHP_XPT_FE_INTR_STATUS1_REG_PARSER3_TRANSPORT_ERROR_MASK 0x00000008
-#define BCHP_XPT_FE_INTR_STATUS1_REG_PARSER3_TRANSPORT_ERROR_SHIFT 3
-#define BCHP_XPT_FE_INTR_STATUS1_REG_PARSER3_TRANSPORT_ERROR_DEFAULT 0x00000000
-
-/* XPT_FE :: INTR_STATUS1_REG :: PARSER2_TRANSPORT_ERROR [02:02] */
-#define BCHP_XPT_FE_INTR_STATUS1_REG_PARSER2_TRANSPORT_ERROR_MASK 0x00000004
-#define BCHP_XPT_FE_INTR_STATUS1_REG_PARSER2_TRANSPORT_ERROR_SHIFT 2
-#define BCHP_XPT_FE_INTR_STATUS1_REG_PARSER2_TRANSPORT_ERROR_DEFAULT 0x00000000
-
-/* XPT_FE :: INTR_STATUS1_REG :: PARSER1_TRANSPORT_ERROR [01:01] */
-#define BCHP_XPT_FE_INTR_STATUS1_REG_PARSER1_TRANSPORT_ERROR_MASK 0x00000002
-#define BCHP_XPT_FE_INTR_STATUS1_REG_PARSER1_TRANSPORT_ERROR_SHIFT 1
-#define BCHP_XPT_FE_INTR_STATUS1_REG_PARSER1_TRANSPORT_ERROR_DEFAULT 0x00000000
-
-/* XPT_FE :: INTR_STATUS1_REG :: PARSER0_TRANSPORT_ERROR [00:00] */
-#define BCHP_XPT_FE_INTR_STATUS1_REG_PARSER0_TRANSPORT_ERROR_MASK 0x00000001
-#define BCHP_XPT_FE_INTR_STATUS1_REG_PARSER0_TRANSPORT_ERROR_SHIFT 0
-#define BCHP_XPT_FE_INTR_STATUS1_REG_PARSER0_TRANSPORT_ERROR_DEFAULT 0x00000000
-
-/***************************************************************************
- *INTR_STATUS2_REG - Interrupt Status Register
- ***************************************************************************/
-/* XPT_FE :: INTR_STATUS2_REG :: reserved0 [31:05] */
-#define BCHP_XPT_FE_INTR_STATUS2_REG_reserved0_MASK 0xffffffe0
-#define BCHP_XPT_FE_INTR_STATUS2_REG_reserved0_SHIFT 5
-
-/* XPT_FE :: INTR_STATUS2_REG :: MTSIF_RX3_MINI_PID_PARSER_LENGTH_ERROR [04:04] */
-#define BCHP_XPT_FE_INTR_STATUS2_REG_MTSIF_RX3_MINI_PID_PARSER_LENGTH_ERROR_MASK 0x00000010
-#define BCHP_XPT_FE_INTR_STATUS2_REG_MTSIF_RX3_MINI_PID_PARSER_LENGTH_ERROR_SHIFT 4
-#define BCHP_XPT_FE_INTR_STATUS2_REG_MTSIF_RX3_MINI_PID_PARSER_LENGTH_ERROR_DEFAULT 0x00000000
-
-/* XPT_FE :: INTR_STATUS2_REG :: MTSIF_RX2_MINI_PID_PARSER_LENGTH_ERROR [03:03] */
-#define BCHP_XPT_FE_INTR_STATUS2_REG_MTSIF_RX2_MINI_PID_PARSER_LENGTH_ERROR_MASK 0x00000008
-#define BCHP_XPT_FE_INTR_STATUS2_REG_MTSIF_RX2_MINI_PID_PARSER_LENGTH_ERROR_SHIFT 3
-#define BCHP_XPT_FE_INTR_STATUS2_REG_MTSIF_RX2_MINI_PID_PARSER_LENGTH_ERROR_DEFAULT 0x00000000
-
-/* XPT_FE :: INTR_STATUS2_REG :: MTSIF_RX1_MINI_PID_PARSER_LENGTH_ERROR [02:02] */
-#define BCHP_XPT_FE_INTR_STATUS2_REG_MTSIF_RX1_MINI_PID_PARSER_LENGTH_ERROR_MASK 0x00000004
-#define BCHP_XPT_FE_INTR_STATUS2_REG_MTSIF_RX1_MINI_PID_PARSER_LENGTH_ERROR_SHIFT 2
-#define BCHP_XPT_FE_INTR_STATUS2_REG_MTSIF_RX1_MINI_PID_PARSER_LENGTH_ERROR_DEFAULT 0x00000000
-
-/* XPT_FE :: INTR_STATUS2_REG :: MTSIF_RX0_MINI_PID_PARSER_LENGTH_ERROR [01:01] */
-#define BCHP_XPT_FE_INTR_STATUS2_REG_MTSIF_RX0_MINI_PID_PARSER_LENGTH_ERROR_MASK 0x00000002
-#define BCHP_XPT_FE_INTR_STATUS2_REG_MTSIF_RX0_MINI_PID_PARSER_LENGTH_ERROR_SHIFT 1
-#define BCHP_XPT_FE_INTR_STATUS2_REG_MTSIF_RX0_MINI_PID_PARSER_LENGTH_ERROR_DEFAULT 0x00000000
-
-/* XPT_FE :: INTR_STATUS2_REG :: INPUT_BUFFER_OVFL_ERR [00:00] */
-#define BCHP_XPT_FE_INTR_STATUS2_REG_INPUT_BUFFER_OVFL_ERR_MASK 0x00000001
-#define BCHP_XPT_FE_INTR_STATUS2_REG_INPUT_BUFFER_OVFL_ERR_SHIFT 0
-#define BCHP_XPT_FE_INTR_STATUS2_REG_INPUT_BUFFER_OVFL_ERR_DEFAULT 0x00000000
-
-/***************************************************************************
- *INTR_STATUS0_REG_EN - Interrupt Status Enable Register
- ***************************************************************************/
-/* XPT_FE :: INTR_STATUS0_REG_EN :: INTR_STATUS0_REG_EN [31:00] */
-#define BCHP_XPT_FE_INTR_STATUS0_REG_EN_INTR_STATUS0_REG_EN_MASK 0xffffffff
-#define BCHP_XPT_FE_INTR_STATUS0_REG_EN_INTR_STATUS0_REG_EN_SHIFT 0
-#define BCHP_XPT_FE_INTR_STATUS0_REG_EN_INTR_STATUS0_REG_EN_DEFAULT 0x00000000
-
-/***************************************************************************
- *INTR_STATUS1_REG_EN - Interrupt Status Enable Register
- ***************************************************************************/
-/* XPT_FE :: INTR_STATUS1_REG_EN :: INTR_STATUS0_REG_EN [31:00] */
-#define BCHP_XPT_FE_INTR_STATUS1_REG_EN_INTR_STATUS0_REG_EN_MASK 0xffffffff
-#define BCHP_XPT_FE_INTR_STATUS1_REG_EN_INTR_STATUS0_REG_EN_SHIFT 0
-#define BCHP_XPT_FE_INTR_STATUS1_REG_EN_INTR_STATUS0_REG_EN_DEFAULT 0x00000000
-
-/***************************************************************************
- *INTR_STATUS2_REG_EN - Interrupt Status Enable Register
- ***************************************************************************/
-/* XPT_FE :: INTR_STATUS2_REG_EN :: reserved0 [31:05] */
-#define BCHP_XPT_FE_INTR_STATUS2_REG_EN_reserved0_MASK 0xffffffe0
-#define BCHP_XPT_FE_INTR_STATUS2_REG_EN_reserved0_SHIFT 5
-
-/* XPT_FE :: INTR_STATUS2_REG_EN :: INTR_STATUS2_REG_EN [04:00] */
-#define BCHP_XPT_FE_INTR_STATUS2_REG_EN_INTR_STATUS2_REG_EN_MASK 0x0000001f
-#define BCHP_XPT_FE_INTR_STATUS2_REG_EN_INTR_STATUS2_REG_EN_SHIFT 0
-#define BCHP_XPT_FE_INTR_STATUS2_REG_EN_INTR_STATUS2_REG_EN_DEFAULT 0x00000000
-
-/***************************************************************************
- *TSMF_INTR_STATUS0_REG - TSMF Demultiplexer Interrupt Status Register
- ***************************************************************************/
-/* XPT_FE :: TSMF_INTR_STATUS0_REG :: TSMF15_SYNC_ERROR_EN [31:31] */
-#define BCHP_XPT_FE_TSMF_INTR_STATUS0_REG_TSMF15_SYNC_ERROR_EN_MASK 0x80000000
-#define BCHP_XPT_FE_TSMF_INTR_STATUS0_REG_TSMF15_SYNC_ERROR_EN_SHIFT 31
-#define BCHP_XPT_FE_TSMF_INTR_STATUS0_REG_TSMF15_SYNC_ERROR_EN_DEFAULT 0x00000000
-
-/* XPT_FE :: TSMF_INTR_STATUS0_REG :: TSMF14_SYNC_ERROR_EN [30:30] */
-#define BCHP_XPT_FE_TSMF_INTR_STATUS0_REG_TSMF14_SYNC_ERROR_EN_MASK 0x40000000
-#define BCHP_XPT_FE_TSMF_INTR_STATUS0_REG_TSMF14_SYNC_ERROR_EN_SHIFT 30
-#define BCHP_XPT_FE_TSMF_INTR_STATUS0_REG_TSMF14_SYNC_ERROR_EN_DEFAULT 0x00000000
-
-/* XPT_FE :: TSMF_INTR_STATUS0_REG :: TSMF13_SYNC_ERROR_EN [29:29] */
-#define BCHP_XPT_FE_TSMF_INTR_STATUS0_REG_TSMF13_SYNC_ERROR_EN_MASK 0x20000000
-#define BCHP_XPT_FE_TSMF_INTR_STATUS0_REG_TSMF13_SYNC_ERROR_EN_SHIFT 29
-#define BCHP_XPT_FE_TSMF_INTR_STATUS0_REG_TSMF13_SYNC_ERROR_EN_DEFAULT 0x00000000
-
-/* XPT_FE :: TSMF_INTR_STATUS0_REG :: TSMF12_SYNC_ERROR_EN [28:28] */
-#define BCHP_XPT_FE_TSMF_INTR_STATUS0_REG_TSMF12_SYNC_ERROR_EN_MASK 0x10000000
-#define BCHP_XPT_FE_TSMF_INTR_STATUS0_REG_TSMF12_SYNC_ERROR_EN_SHIFT 28
-#define BCHP_XPT_FE_TSMF_INTR_STATUS0_REG_TSMF12_SYNC_ERROR_EN_DEFAULT 0x00000000
-
-/* XPT_FE :: TSMF_INTR_STATUS0_REG :: TSMF11_SYNC_ERROR_EN [27:27] */
-#define BCHP_XPT_FE_TSMF_INTR_STATUS0_REG_TSMF11_SYNC_ERROR_EN_MASK 0x08000000
-#define BCHP_XPT_FE_TSMF_INTR_STATUS0_REG_TSMF11_SYNC_ERROR_EN_SHIFT 27
-#define BCHP_XPT_FE_TSMF_INTR_STATUS0_REG_TSMF11_SYNC_ERROR_EN_DEFAULT 0x00000000
-
-/* XPT_FE :: TSMF_INTR_STATUS0_REG :: TSMF10_SYNC_ERROR_EN [26:26] */
-#define BCHP_XPT_FE_TSMF_INTR_STATUS0_REG_TSMF10_SYNC_ERROR_EN_MASK 0x04000000
-#define BCHP_XPT_FE_TSMF_INTR_STATUS0_REG_TSMF10_SYNC_ERROR_EN_SHIFT 26
-#define BCHP_XPT_FE_TSMF_INTR_STATUS0_REG_TSMF10_SYNC_ERROR_EN_DEFAULT 0x00000000
-
-/* XPT_FE :: TSMF_INTR_STATUS0_REG :: TSMF9_SYNC_ERROR_EN [25:25] */
-#define BCHP_XPT_FE_TSMF_INTR_STATUS0_REG_TSMF9_SYNC_ERROR_EN_MASK 0x02000000
-#define BCHP_XPT_FE_TSMF_INTR_STATUS0_REG_TSMF9_SYNC_ERROR_EN_SHIFT 25
-#define BCHP_XPT_FE_TSMF_INTR_STATUS0_REG_TSMF9_SYNC_ERROR_EN_DEFAULT 0x00000000
-
-/* XPT_FE :: TSMF_INTR_STATUS0_REG :: TSMF8_SYNC_ERROR_EN [24:24] */
-#define BCHP_XPT_FE_TSMF_INTR_STATUS0_REG_TSMF8_SYNC_ERROR_EN_MASK 0x01000000
-#define BCHP_XPT_FE_TSMF_INTR_STATUS0_REG_TSMF8_SYNC_ERROR_EN_SHIFT 24
-#define BCHP_XPT_FE_TSMF_INTR_STATUS0_REG_TSMF8_SYNC_ERROR_EN_DEFAULT 0x00000000
-
-/* XPT_FE :: TSMF_INTR_STATUS0_REG :: TSMF7_SYNC_ERROR_EN [23:23] */
-#define BCHP_XPT_FE_TSMF_INTR_STATUS0_REG_TSMF7_SYNC_ERROR_EN_MASK 0x00800000
-#define BCHP_XPT_FE_TSMF_INTR_STATUS0_REG_TSMF7_SYNC_ERROR_EN_SHIFT 23
-#define BCHP_XPT_FE_TSMF_INTR_STATUS0_REG_TSMF7_SYNC_ERROR_EN_DEFAULT 0x00000000
-
-/* XPT_FE :: TSMF_INTR_STATUS0_REG :: TSMF6_SYNC_ERROR_EN [22:22] */
-#define BCHP_XPT_FE_TSMF_INTR_STATUS0_REG_TSMF6_SYNC_ERROR_EN_MASK 0x00400000
-#define BCHP_XPT_FE_TSMF_INTR_STATUS0_REG_TSMF6_SYNC_ERROR_EN_SHIFT 22
-#define BCHP_XPT_FE_TSMF_INTR_STATUS0_REG_TSMF6_SYNC_ERROR_EN_DEFAULT 0x00000000
-
-/* XPT_FE :: TSMF_INTR_STATUS0_REG :: TSMF5_SYNC_ERROR_EN [21:21] */
-#define BCHP_XPT_FE_TSMF_INTR_STATUS0_REG_TSMF5_SYNC_ERROR_EN_MASK 0x00200000
-#define BCHP_XPT_FE_TSMF_INTR_STATUS0_REG_TSMF5_SYNC_ERROR_EN_SHIFT 21
-#define BCHP_XPT_FE_TSMF_INTR_STATUS0_REG_TSMF5_SYNC_ERROR_EN_DEFAULT 0x00000000
-
-/* XPT_FE :: TSMF_INTR_STATUS0_REG :: TSMF4_SYNC_ERROR_EN [20:20] */
-#define BCHP_XPT_FE_TSMF_INTR_STATUS0_REG_TSMF4_SYNC_ERROR_EN_MASK 0x00100000
-#define BCHP_XPT_FE_TSMF_INTR_STATUS0_REG_TSMF4_SYNC_ERROR_EN_SHIFT 20
-#define BCHP_XPT_FE_TSMF_INTR_STATUS0_REG_TSMF4_SYNC_ERROR_EN_DEFAULT 0x00000000
-
-/* XPT_FE :: TSMF_INTR_STATUS0_REG :: TSMF3_SYNC_ERROR_EN [19:19] */
-#define BCHP_XPT_FE_TSMF_INTR_STATUS0_REG_TSMF3_SYNC_ERROR_EN_MASK 0x00080000
-#define BCHP_XPT_FE_TSMF_INTR_STATUS0_REG_TSMF3_SYNC_ERROR_EN_SHIFT 19
-#define BCHP_XPT_FE_TSMF_INTR_STATUS0_REG_TSMF3_SYNC_ERROR_EN_DEFAULT 0x00000000
-
-/* XPT_FE :: TSMF_INTR_STATUS0_REG :: TSMF2_SYNC_ERROR_EN [18:18] */
-#define BCHP_XPT_FE_TSMF_INTR_STATUS0_REG_TSMF2_SYNC_ERROR_EN_MASK 0x00040000
-#define BCHP_XPT_FE_TSMF_INTR_STATUS0_REG_TSMF2_SYNC_ERROR_EN_SHIFT 18
-#define BCHP_XPT_FE_TSMF_INTR_STATUS0_REG_TSMF2_SYNC_ERROR_EN_DEFAULT 0x00000000
-
-/* XPT_FE :: TSMF_INTR_STATUS0_REG :: TSMF1_SYNC_ERROR_EN [17:17] */
-#define BCHP_XPT_FE_TSMF_INTR_STATUS0_REG_TSMF1_SYNC_ERROR_EN_MASK 0x00020000
-#define BCHP_XPT_FE_TSMF_INTR_STATUS0_REG_TSMF1_SYNC_ERROR_EN_SHIFT 17
-#define BCHP_XPT_FE_TSMF_INTR_STATUS0_REG_TSMF1_SYNC_ERROR_EN_DEFAULT 0x00000000
-
-/* XPT_FE :: TSMF_INTR_STATUS0_REG :: TSMF0_SYNC_ERROR_EN [16:16] */
-#define BCHP_XPT_FE_TSMF_INTR_STATUS0_REG_TSMF0_SYNC_ERROR_EN_MASK 0x00010000
-#define BCHP_XPT_FE_TSMF_INTR_STATUS0_REG_TSMF0_SYNC_ERROR_EN_SHIFT 16
-#define BCHP_XPT_FE_TSMF_INTR_STATUS0_REG_TSMF0_SYNC_ERROR_EN_DEFAULT 0x00000000
-
-/* XPT_FE :: TSMF_INTR_STATUS0_REG :: TSMF15_FRAME_ERROR [15:15] */
-#define BCHP_XPT_FE_TSMF_INTR_STATUS0_REG_TSMF15_FRAME_ERROR_MASK 0x00008000
-#define BCHP_XPT_FE_TSMF_INTR_STATUS0_REG_TSMF15_FRAME_ERROR_SHIFT 15
-#define BCHP_XPT_FE_TSMF_INTR_STATUS0_REG_TSMF15_FRAME_ERROR_DEFAULT 0x00000000
-
-/* XPT_FE :: TSMF_INTR_STATUS0_REG :: TSMF14_FRAME_ERROR [14:14] */
-#define BCHP_XPT_FE_TSMF_INTR_STATUS0_REG_TSMF14_FRAME_ERROR_MASK 0x00004000
-#define BCHP_XPT_FE_TSMF_INTR_STATUS0_REG_TSMF14_FRAME_ERROR_SHIFT 14
-#define BCHP_XPT_FE_TSMF_INTR_STATUS0_REG_TSMF14_FRAME_ERROR_DEFAULT 0x00000000
-
-/* XPT_FE :: TSMF_INTR_STATUS0_REG :: TSMF13_FRAME_ERROR [13:13] */
-#define BCHP_XPT_FE_TSMF_INTR_STATUS0_REG_TSMF13_FRAME_ERROR_MASK 0x00002000
-#define BCHP_XPT_FE_TSMF_INTR_STATUS0_REG_TSMF13_FRAME_ERROR_SHIFT 13
-#define BCHP_XPT_FE_TSMF_INTR_STATUS0_REG_TSMF13_FRAME_ERROR_DEFAULT 0x00000000
-
-/* XPT_FE :: TSMF_INTR_STATUS0_REG :: TSMF12_FRAME_ERROR [12:12] */
-#define BCHP_XPT_FE_TSMF_INTR_STATUS0_REG_TSMF12_FRAME_ERROR_MASK 0x00001000
-#define BCHP_XPT_FE_TSMF_INTR_STATUS0_REG_TSMF12_FRAME_ERROR_SHIFT 12
-#define BCHP_XPT_FE_TSMF_INTR_STATUS0_REG_TSMF12_FRAME_ERROR_DEFAULT 0x00000000
-
-/* XPT_FE :: TSMF_INTR_STATUS0_REG :: TSMF11_FRAME_ERROR [11:11] */
-#define BCHP_XPT_FE_TSMF_INTR_STATUS0_REG_TSMF11_FRAME_ERROR_MASK 0x00000800
-#define BCHP_XPT_FE_TSMF_INTR_STATUS0_REG_TSMF11_FRAME_ERROR_SHIFT 11
-#define BCHP_XPT_FE_TSMF_INTR_STATUS0_REG_TSMF11_FRAME_ERROR_DEFAULT 0x00000000
-
-/* XPT_FE :: TSMF_INTR_STATUS0_REG :: TSMF10_FRAME_ERROR [10:10] */
-#define BCHP_XPT_FE_TSMF_INTR_STATUS0_REG_TSMF10_FRAME_ERROR_MASK 0x00000400
-#define BCHP_XPT_FE_TSMF_INTR_STATUS0_REG_TSMF10_FRAME_ERROR_SHIFT 10
-#define BCHP_XPT_FE_TSMF_INTR_STATUS0_REG_TSMF10_FRAME_ERROR_DEFAULT 0x00000000
-
-/* XPT_FE :: TSMF_INTR_STATUS0_REG :: TSMF9_FRAME_ERROR [09:09] */
-#define BCHP_XPT_FE_TSMF_INTR_STATUS0_REG_TSMF9_FRAME_ERROR_MASK 0x00000200
-#define BCHP_XPT_FE_TSMF_INTR_STATUS0_REG_TSMF9_FRAME_ERROR_SHIFT 9
-#define BCHP_XPT_FE_TSMF_INTR_STATUS0_REG_TSMF9_FRAME_ERROR_DEFAULT 0x00000000
-
-/* XPT_FE :: TSMF_INTR_STATUS0_REG :: TSMF8_FRAME_ERROR [08:08] */
-#define BCHP_XPT_FE_TSMF_INTR_STATUS0_REG_TSMF8_FRAME_ERROR_MASK 0x00000100
-#define BCHP_XPT_FE_TSMF_INTR_STATUS0_REG_TSMF8_FRAME_ERROR_SHIFT 8
-#define BCHP_XPT_FE_TSMF_INTR_STATUS0_REG_TSMF8_FRAME_ERROR_DEFAULT 0x00000000
-
-/* XPT_FE :: TSMF_INTR_STATUS0_REG :: TSMF7_FRAME_ERROR [07:07] */
-#define BCHP_XPT_FE_TSMF_INTR_STATUS0_REG_TSMF7_FRAME_ERROR_MASK 0x00000080
-#define BCHP_XPT_FE_TSMF_INTR_STATUS0_REG_TSMF7_FRAME_ERROR_SHIFT 7
-#define BCHP_XPT_FE_TSMF_INTR_STATUS0_REG_TSMF7_FRAME_ERROR_DEFAULT 0x00000000
-
-/* XPT_FE :: TSMF_INTR_STATUS0_REG :: TSMF6_FRAME_ERROR [06:06] */
-#define BCHP_XPT_FE_TSMF_INTR_STATUS0_REG_TSMF6_FRAME_ERROR_MASK 0x00000040
-#define BCHP_XPT_FE_TSMF_INTR_STATUS0_REG_TSMF6_FRAME_ERROR_SHIFT 6
-#define BCHP_XPT_FE_TSMF_INTR_STATUS0_REG_TSMF6_FRAME_ERROR_DEFAULT 0x00000000
-
-/* XPT_FE :: TSMF_INTR_STATUS0_REG :: TSMF5_FRAME_ERROR [05:05] */
-#define BCHP_XPT_FE_TSMF_INTR_STATUS0_REG_TSMF5_FRAME_ERROR_MASK 0x00000020
-#define BCHP_XPT_FE_TSMF_INTR_STATUS0_REG_TSMF5_FRAME_ERROR_SHIFT 5
-#define BCHP_XPT_FE_TSMF_INTR_STATUS0_REG_TSMF5_FRAME_ERROR_DEFAULT 0x00000000
-
-/* XPT_FE :: TSMF_INTR_STATUS0_REG :: TSMF4_FRAME_ERROR [04:04] */
-#define BCHP_XPT_FE_TSMF_INTR_STATUS0_REG_TSMF4_FRAME_ERROR_MASK 0x00000010
-#define BCHP_XPT_FE_TSMF_INTR_STATUS0_REG_TSMF4_FRAME_ERROR_SHIFT 4
-#define BCHP_XPT_FE_TSMF_INTR_STATUS0_REG_TSMF4_FRAME_ERROR_DEFAULT 0x00000000
-
-/* XPT_FE :: TSMF_INTR_STATUS0_REG :: TSMF3_FRAME_ERROR [03:03] */
-#define BCHP_XPT_FE_TSMF_INTR_STATUS0_REG_TSMF3_FRAME_ERROR_MASK 0x00000008
-#define BCHP_XPT_FE_TSMF_INTR_STATUS0_REG_TSMF3_FRAME_ERROR_SHIFT 3
-#define BCHP_XPT_FE_TSMF_INTR_STATUS0_REG_TSMF3_FRAME_ERROR_DEFAULT 0x00000000
-
-/* XPT_FE :: TSMF_INTR_STATUS0_REG :: TSMF2_FRAME_ERROR [02:02] */
-#define BCHP_XPT_FE_TSMF_INTR_STATUS0_REG_TSMF2_FRAME_ERROR_MASK 0x00000004
-#define BCHP_XPT_FE_TSMF_INTR_STATUS0_REG_TSMF2_FRAME_ERROR_SHIFT 2
-#define BCHP_XPT_FE_TSMF_INTR_STATUS0_REG_TSMF2_FRAME_ERROR_DEFAULT 0x00000000
-
-/* XPT_FE :: TSMF_INTR_STATUS0_REG :: TSMF1_FRAME_ERROR [01:01] */
-#define BCHP_XPT_FE_TSMF_INTR_STATUS0_REG_TSMF1_FRAME_ERROR_MASK 0x00000002
-#define BCHP_XPT_FE_TSMF_INTR_STATUS0_REG_TSMF1_FRAME_ERROR_SHIFT 1
-#define BCHP_XPT_FE_TSMF_INTR_STATUS0_REG_TSMF1_FRAME_ERROR_DEFAULT 0x00000000
-
-/* XPT_FE :: TSMF_INTR_STATUS0_REG :: TSMF0_FRAME_ERROR [00:00] */
-#define BCHP_XPT_FE_TSMF_INTR_STATUS0_REG_TSMF0_FRAME_ERROR_MASK 0x00000001
-#define BCHP_XPT_FE_TSMF_INTR_STATUS0_REG_TSMF0_FRAME_ERROR_SHIFT 0
-#define BCHP_XPT_FE_TSMF_INTR_STATUS0_REG_TSMF0_FRAME_ERROR_DEFAULT 0x00000000
-
-/***************************************************************************
- *TSMF_INTR_STATUS0_REG_EN - TSMF Demultiplexer Interrupt Status Enable Register
- ***************************************************************************/
-/* XPT_FE :: TSMF_INTR_STATUS0_REG_EN :: INTR_STATUS1_REG_EN [31:00] */
-#define BCHP_XPT_FE_TSMF_INTR_STATUS0_REG_EN_INTR_STATUS1_REG_EN_MASK 0xffffffff
-#define BCHP_XPT_FE_TSMF_INTR_STATUS0_REG_EN_INTR_STATUS1_REG_EN_SHIFT 0
-#define BCHP_XPT_FE_TSMF_INTR_STATUS0_REG_EN_INTR_STATUS1_REG_EN_DEFAULT 0x00000000
-
-/***************************************************************************
- *MTSIF_RX_INTR_STATUS0_REG - Interrupt Status Register
- ***************************************************************************/
-/* XPT_FE :: MTSIF_RX_INTR_STATUS0_REG :: PARSER31_LENGTH_MISMATCH [31:31] */
-#define BCHP_XPT_FE_MTSIF_RX_INTR_STATUS0_REG_PARSER31_LENGTH_MISMATCH_MASK 0x80000000
-#define BCHP_XPT_FE_MTSIF_RX_INTR_STATUS0_REG_PARSER31_LENGTH_MISMATCH_SHIFT 31
-#define BCHP_XPT_FE_MTSIF_RX_INTR_STATUS0_REG_PARSER31_LENGTH_MISMATCH_DEFAULT 0x00000000
-
-/* XPT_FE :: MTSIF_RX_INTR_STATUS0_REG :: PARSER30_LENGTH_MISMATCH [30:30] */
-#define BCHP_XPT_FE_MTSIF_RX_INTR_STATUS0_REG_PARSER30_LENGTH_MISMATCH_MASK 0x40000000
-#define BCHP_XPT_FE_MTSIF_RX_INTR_STATUS0_REG_PARSER30_LENGTH_MISMATCH_SHIFT 30
-#define BCHP_XPT_FE_MTSIF_RX_INTR_STATUS0_REG_PARSER30_LENGTH_MISMATCH_DEFAULT 0x00000000
-
-/* XPT_FE :: MTSIF_RX_INTR_STATUS0_REG :: PARSER29_LENGTH_MISMATCH [29:29] */
-#define BCHP_XPT_FE_MTSIF_RX_INTR_STATUS0_REG_PARSER29_LENGTH_MISMATCH_MASK 0x20000000
-#define BCHP_XPT_FE_MTSIF_RX_INTR_STATUS0_REG_PARSER29_LENGTH_MISMATCH_SHIFT 29
-#define BCHP_XPT_FE_MTSIF_RX_INTR_STATUS0_REG_PARSER29_LENGTH_MISMATCH_DEFAULT 0x00000000
-
-/* XPT_FE :: MTSIF_RX_INTR_STATUS0_REG :: PARSER28_LENGTH_MISMATCH [28:28] */
-#define BCHP_XPT_FE_MTSIF_RX_INTR_STATUS0_REG_PARSER28_LENGTH_MISMATCH_MASK 0x10000000
-#define BCHP_XPT_FE_MTSIF_RX_INTR_STATUS0_REG_PARSER28_LENGTH_MISMATCH_SHIFT 28
-#define BCHP_XPT_FE_MTSIF_RX_INTR_STATUS0_REG_PARSER28_LENGTH_MISMATCH_DEFAULT 0x00000000
-
-/* XPT_FE :: MTSIF_RX_INTR_STATUS0_REG :: PARSER27_LENGTH_MISMATCH [27:27] */
-#define BCHP_XPT_FE_MTSIF_RX_INTR_STATUS0_REG_PARSER27_LENGTH_MISMATCH_MASK 0x08000000
-#define BCHP_XPT_FE_MTSIF_RX_INTR_STATUS0_REG_PARSER27_LENGTH_MISMATCH_SHIFT 27
-#define BCHP_XPT_FE_MTSIF_RX_INTR_STATUS0_REG_PARSER27_LENGTH_MISMATCH_DEFAULT 0x00000000
-
-/* XPT_FE :: MTSIF_RX_INTR_STATUS0_REG :: PARSER26_LENGTH_MISMATCH [26:26] */
-#define BCHP_XPT_FE_MTSIF_RX_INTR_STATUS0_REG_PARSER26_LENGTH_MISMATCH_MASK 0x04000000
-#define BCHP_XPT_FE_MTSIF_RX_INTR_STATUS0_REG_PARSER26_LENGTH_MISMATCH_SHIFT 26
-#define BCHP_XPT_FE_MTSIF_RX_INTR_STATUS0_REG_PARSER26_LENGTH_MISMATCH_DEFAULT 0x00000000
-
-/* XPT_FE :: MTSIF_RX_INTR_STATUS0_REG :: PARSER25_LENGTH_MISMATCH [25:25] */
-#define BCHP_XPT_FE_MTSIF_RX_INTR_STATUS0_REG_PARSER25_LENGTH_MISMATCH_MASK 0x02000000
-#define BCHP_XPT_FE_MTSIF_RX_INTR_STATUS0_REG_PARSER25_LENGTH_MISMATCH_SHIFT 25
-#define BCHP_XPT_FE_MTSIF_RX_INTR_STATUS0_REG_PARSER25_LENGTH_MISMATCH_DEFAULT 0x00000000
-
-/* XPT_FE :: MTSIF_RX_INTR_STATUS0_REG :: PARSER24_LENGTH_MISMATCH [24:24] */
-#define BCHP_XPT_FE_MTSIF_RX_INTR_STATUS0_REG_PARSER24_LENGTH_MISMATCH_MASK 0x01000000
-#define BCHP_XPT_FE_MTSIF_RX_INTR_STATUS0_REG_PARSER24_LENGTH_MISMATCH_SHIFT 24
-#define BCHP_XPT_FE_MTSIF_RX_INTR_STATUS0_REG_PARSER24_LENGTH_MISMATCH_DEFAULT 0x00000000
-
-/* XPT_FE :: MTSIF_RX_INTR_STATUS0_REG :: PARSER23_LENGTH_MISMATCH [23:23] */
-#define BCHP_XPT_FE_MTSIF_RX_INTR_STATUS0_REG_PARSER23_LENGTH_MISMATCH_MASK 0x00800000
-#define BCHP_XPT_FE_MTSIF_RX_INTR_STATUS0_REG_PARSER23_LENGTH_MISMATCH_SHIFT 23
-#define BCHP_XPT_FE_MTSIF_RX_INTR_STATUS0_REG_PARSER23_LENGTH_MISMATCH_DEFAULT 0x00000000
-
-/* XPT_FE :: MTSIF_RX_INTR_STATUS0_REG :: PARSER22_LENGTH_MISMATCH [22:22] */
-#define BCHP_XPT_FE_MTSIF_RX_INTR_STATUS0_REG_PARSER22_LENGTH_MISMATCH_MASK 0x00400000
-#define BCHP_XPT_FE_MTSIF_RX_INTR_STATUS0_REG_PARSER22_LENGTH_MISMATCH_SHIFT 22
-#define BCHP_XPT_FE_MTSIF_RX_INTR_STATUS0_REG_PARSER22_LENGTH_MISMATCH_DEFAULT 0x00000000
-
-/* XPT_FE :: MTSIF_RX_INTR_STATUS0_REG :: PARSER21_LENGTH_MISMATCH [21:21] */
-#define BCHP_XPT_FE_MTSIF_RX_INTR_STATUS0_REG_PARSER21_LENGTH_MISMATCH_MASK 0x00200000
-#define BCHP_XPT_FE_MTSIF_RX_INTR_STATUS0_REG_PARSER21_LENGTH_MISMATCH_SHIFT 21
-#define BCHP_XPT_FE_MTSIF_RX_INTR_STATUS0_REG_PARSER21_LENGTH_MISMATCH_DEFAULT 0x00000000
-
-/* XPT_FE :: MTSIF_RX_INTR_STATUS0_REG :: PARSER20_LENGTH_MISMATCH [20:20] */
-#define BCHP_XPT_FE_MTSIF_RX_INTR_STATUS0_REG_PARSER20_LENGTH_MISMATCH_MASK 0x00100000
-#define BCHP_XPT_FE_MTSIF_RX_INTR_STATUS0_REG_PARSER20_LENGTH_MISMATCH_SHIFT 20
-#define BCHP_XPT_FE_MTSIF_RX_INTR_STATUS0_REG_PARSER20_LENGTH_MISMATCH_DEFAULT 0x00000000
-
-/* XPT_FE :: MTSIF_RX_INTR_STATUS0_REG :: PARSER19_LENGTH_MISMATCH [19:19] */
-#define BCHP_XPT_FE_MTSIF_RX_INTR_STATUS0_REG_PARSER19_LENGTH_MISMATCH_MASK 0x00080000
-#define BCHP_XPT_FE_MTSIF_RX_INTR_STATUS0_REG_PARSER19_LENGTH_MISMATCH_SHIFT 19
-#define BCHP_XPT_FE_MTSIF_RX_INTR_STATUS0_REG_PARSER19_LENGTH_MISMATCH_DEFAULT 0x00000000
-
-/* XPT_FE :: MTSIF_RX_INTR_STATUS0_REG :: PARSER18_LENGTH_MISMATCH [18:18] */
-#define BCHP_XPT_FE_MTSIF_RX_INTR_STATUS0_REG_PARSER18_LENGTH_MISMATCH_MASK 0x00040000
-#define BCHP_XPT_FE_MTSIF_RX_INTR_STATUS0_REG_PARSER18_LENGTH_MISMATCH_SHIFT 18
-#define BCHP_XPT_FE_MTSIF_RX_INTR_STATUS0_REG_PARSER18_LENGTH_MISMATCH_DEFAULT 0x00000000
-
-/* XPT_FE :: MTSIF_RX_INTR_STATUS0_REG :: PARSER17_LENGTH_MISMATCH [17:17] */
-#define BCHP_XPT_FE_MTSIF_RX_INTR_STATUS0_REG_PARSER17_LENGTH_MISMATCH_MASK 0x00020000
-#define BCHP_XPT_FE_MTSIF_RX_INTR_STATUS0_REG_PARSER17_LENGTH_MISMATCH_SHIFT 17
-#define BCHP_XPT_FE_MTSIF_RX_INTR_STATUS0_REG_PARSER17_LENGTH_MISMATCH_DEFAULT 0x00000000
-
-/* XPT_FE :: MTSIF_RX_INTR_STATUS0_REG :: PARSER16_LENGTH_MISMATCH [16:16] */
-#define BCHP_XPT_FE_MTSIF_RX_INTR_STATUS0_REG_PARSER16_LENGTH_MISMATCH_MASK 0x00010000
-#define BCHP_XPT_FE_MTSIF_RX_INTR_STATUS0_REG_PARSER16_LENGTH_MISMATCH_SHIFT 16
-#define BCHP_XPT_FE_MTSIF_RX_INTR_STATUS0_REG_PARSER16_LENGTH_MISMATCH_DEFAULT 0x00000000
-
-/* XPT_FE :: MTSIF_RX_INTR_STATUS0_REG :: PARSER15_LENGTH_MISMATCH [15:15] */
-#define BCHP_XPT_FE_MTSIF_RX_INTR_STATUS0_REG_PARSER15_LENGTH_MISMATCH_MASK 0x00008000
-#define BCHP_XPT_FE_MTSIF_RX_INTR_STATUS0_REG_PARSER15_LENGTH_MISMATCH_SHIFT 15
-#define BCHP_XPT_FE_MTSIF_RX_INTR_STATUS0_REG_PARSER15_LENGTH_MISMATCH_DEFAULT 0x00000000
-
-/* XPT_FE :: MTSIF_RX_INTR_STATUS0_REG :: PARSER14_LENGTH_MISMATCH [14:14] */
-#define BCHP_XPT_FE_MTSIF_RX_INTR_STATUS0_REG_PARSER14_LENGTH_MISMATCH_MASK 0x00004000
-#define BCHP_XPT_FE_MTSIF_RX_INTR_STATUS0_REG_PARSER14_LENGTH_MISMATCH_SHIFT 14
-#define BCHP_XPT_FE_MTSIF_RX_INTR_STATUS0_REG_PARSER14_LENGTH_MISMATCH_DEFAULT 0x00000000
-
-/* XPT_FE :: MTSIF_RX_INTR_STATUS0_REG :: PARSER13_LENGTH_MISMATCH [13:13] */
-#define BCHP_XPT_FE_MTSIF_RX_INTR_STATUS0_REG_PARSER13_LENGTH_MISMATCH_MASK 0x00002000
-#define BCHP_XPT_FE_MTSIF_RX_INTR_STATUS0_REG_PARSER13_LENGTH_MISMATCH_SHIFT 13
-#define BCHP_XPT_FE_MTSIF_RX_INTR_STATUS0_REG_PARSER13_LENGTH_MISMATCH_DEFAULT 0x00000000
-
-/* XPT_FE :: MTSIF_RX_INTR_STATUS0_REG :: PARSER12_LENGTH_MISMATCH [12:12] */
-#define BCHP_XPT_FE_MTSIF_RX_INTR_STATUS0_REG_PARSER12_LENGTH_MISMATCH_MASK 0x00001000
-#define BCHP_XPT_FE_MTSIF_RX_INTR_STATUS0_REG_PARSER12_LENGTH_MISMATCH_SHIFT 12
-#define BCHP_XPT_FE_MTSIF_RX_INTR_STATUS0_REG_PARSER12_LENGTH_MISMATCH_DEFAULT 0x00000000
-
-/* XPT_FE :: MTSIF_RX_INTR_STATUS0_REG :: PARSER11_LENGTH_MISMATCH [11:11] */
-#define BCHP_XPT_FE_MTSIF_RX_INTR_STATUS0_REG_PARSER11_LENGTH_MISMATCH_MASK 0x00000800
-#define BCHP_XPT_FE_MTSIF_RX_INTR_STATUS0_REG_PARSER11_LENGTH_MISMATCH_SHIFT 11
-#define BCHP_XPT_FE_MTSIF_RX_INTR_STATUS0_REG_PARSER11_LENGTH_MISMATCH_DEFAULT 0x00000000
-
-/* XPT_FE :: MTSIF_RX_INTR_STATUS0_REG :: PARSER10_LENGTH_MISMATCH [10:10] */
-#define BCHP_XPT_FE_MTSIF_RX_INTR_STATUS0_REG_PARSER10_LENGTH_MISMATCH_MASK 0x00000400
-#define BCHP_XPT_FE_MTSIF_RX_INTR_STATUS0_REG_PARSER10_LENGTH_MISMATCH_SHIFT 10
-#define BCHP_XPT_FE_MTSIF_RX_INTR_STATUS0_REG_PARSER10_LENGTH_MISMATCH_DEFAULT 0x00000000
-
-/* XPT_FE :: MTSIF_RX_INTR_STATUS0_REG :: PARSER9_LENGTH_MISMATCH [09:09] */
-#define BCHP_XPT_FE_MTSIF_RX_INTR_STATUS0_REG_PARSER9_LENGTH_MISMATCH_MASK 0x00000200
-#define BCHP_XPT_FE_MTSIF_RX_INTR_STATUS0_REG_PARSER9_LENGTH_MISMATCH_SHIFT 9
-#define BCHP_XPT_FE_MTSIF_RX_INTR_STATUS0_REG_PARSER9_LENGTH_MISMATCH_DEFAULT 0x00000000
-
-/* XPT_FE :: MTSIF_RX_INTR_STATUS0_REG :: PARSER8_LENGTH_MISMATCH [08:08] */
-#define BCHP_XPT_FE_MTSIF_RX_INTR_STATUS0_REG_PARSER8_LENGTH_MISMATCH_MASK 0x00000100
-#define BCHP_XPT_FE_MTSIF_RX_INTR_STATUS0_REG_PARSER8_LENGTH_MISMATCH_SHIFT 8
-#define BCHP_XPT_FE_MTSIF_RX_INTR_STATUS0_REG_PARSER8_LENGTH_MISMATCH_DEFAULT 0x00000000
-
-/* XPT_FE :: MTSIF_RX_INTR_STATUS0_REG :: PARSER7_LENGTH_MISMATCH [07:07] */
-#define BCHP_XPT_FE_MTSIF_RX_INTR_STATUS0_REG_PARSER7_LENGTH_MISMATCH_MASK 0x00000080
-#define BCHP_XPT_FE_MTSIF_RX_INTR_STATUS0_REG_PARSER7_LENGTH_MISMATCH_SHIFT 7
-#define BCHP_XPT_FE_MTSIF_RX_INTR_STATUS0_REG_PARSER7_LENGTH_MISMATCH_DEFAULT 0x00000000
-
-/* XPT_FE :: MTSIF_RX_INTR_STATUS0_REG :: PARSER6_LENGTH_MISMATCH [06:06] */
-#define BCHP_XPT_FE_MTSIF_RX_INTR_STATUS0_REG_PARSER6_LENGTH_MISMATCH_MASK 0x00000040
-#define BCHP_XPT_FE_MTSIF_RX_INTR_STATUS0_REG_PARSER6_LENGTH_MISMATCH_SHIFT 6
-#define BCHP_XPT_FE_MTSIF_RX_INTR_STATUS0_REG_PARSER6_LENGTH_MISMATCH_DEFAULT 0x00000000
-
-/* XPT_FE :: MTSIF_RX_INTR_STATUS0_REG :: PARSER5_LENGTH_MISMATCH [05:05] */
-#define BCHP_XPT_FE_MTSIF_RX_INTR_STATUS0_REG_PARSER5_LENGTH_MISMATCH_MASK 0x00000020
-#define BCHP_XPT_FE_MTSIF_RX_INTR_STATUS0_REG_PARSER5_LENGTH_MISMATCH_SHIFT 5
-#define BCHP_XPT_FE_MTSIF_RX_INTR_STATUS0_REG_PARSER5_LENGTH_MISMATCH_DEFAULT 0x00000000
-
-/* XPT_FE :: MTSIF_RX_INTR_STATUS0_REG :: PARSER4_LENGTH_MISMATCH [04:04] */
-#define BCHP_XPT_FE_MTSIF_RX_INTR_STATUS0_REG_PARSER4_LENGTH_MISMATCH_MASK 0x00000010
-#define BCHP_XPT_FE_MTSIF_RX_INTR_STATUS0_REG_PARSER4_LENGTH_MISMATCH_SHIFT 4
-#define BCHP_XPT_FE_MTSIF_RX_INTR_STATUS0_REG_PARSER4_LENGTH_MISMATCH_DEFAULT 0x00000000
-
-/* XPT_FE :: MTSIF_RX_INTR_STATUS0_REG :: PARSER3_LENGTH_MISMATCH [03:03] */
-#define BCHP_XPT_FE_MTSIF_RX_INTR_STATUS0_REG_PARSER3_LENGTH_MISMATCH_MASK 0x00000008
-#define BCHP_XPT_FE_MTSIF_RX_INTR_STATUS0_REG_PARSER3_LENGTH_MISMATCH_SHIFT 3
-#define BCHP_XPT_FE_MTSIF_RX_INTR_STATUS0_REG_PARSER3_LENGTH_MISMATCH_DEFAULT 0x00000000
-
-/* XPT_FE :: MTSIF_RX_INTR_STATUS0_REG :: PARSER2_LENGTH_MISMATCH [02:02] */
-#define BCHP_XPT_FE_MTSIF_RX_INTR_STATUS0_REG_PARSER2_LENGTH_MISMATCH_MASK 0x00000004
-#define BCHP_XPT_FE_MTSIF_RX_INTR_STATUS0_REG_PARSER2_LENGTH_MISMATCH_SHIFT 2
-#define BCHP_XPT_FE_MTSIF_RX_INTR_STATUS0_REG_PARSER2_LENGTH_MISMATCH_DEFAULT 0x00000000
-
-/* XPT_FE :: MTSIF_RX_INTR_STATUS0_REG :: PARSER1_LENGTH_MISMATCH [01:01] */
-#define BCHP_XPT_FE_MTSIF_RX_INTR_STATUS0_REG_PARSER1_LENGTH_MISMATCH_MASK 0x00000002
-#define BCHP_XPT_FE_MTSIF_RX_INTR_STATUS0_REG_PARSER1_LENGTH_MISMATCH_SHIFT 1
-#define BCHP_XPT_FE_MTSIF_RX_INTR_STATUS0_REG_PARSER1_LENGTH_MISMATCH_DEFAULT 0x00000000
-
-/* XPT_FE :: MTSIF_RX_INTR_STATUS0_REG :: PARSER0_LENGTH_MISMATCH [00:00] */
-#define BCHP_XPT_FE_MTSIF_RX_INTR_STATUS0_REG_PARSER0_LENGTH_MISMATCH_MASK 0x00000001
-#define BCHP_XPT_FE_MTSIF_RX_INTR_STATUS0_REG_PARSER0_LENGTH_MISMATCH_SHIFT 0
-#define BCHP_XPT_FE_MTSIF_RX_INTR_STATUS0_REG_PARSER0_LENGTH_MISMATCH_DEFAULT 0x00000000
-
-/***************************************************************************
- *MTSIF_RX_INTR_STATUS0_REG_EN - Interrupt Status Enable Register
- ***************************************************************************/
-/* XPT_FE :: MTSIF_RX_INTR_STATUS0_REG_EN :: INTR_STATUS0_REG_EN [31:00] */
-#define BCHP_XPT_FE_MTSIF_RX_INTR_STATUS0_REG_EN_INTR_STATUS0_REG_EN_MASK 0xffffffff
-#define BCHP_XPT_FE_MTSIF_RX_INTR_STATUS0_REG_EN_INTR_STATUS0_REG_EN_SHIFT 0
-#define BCHP_XPT_FE_MTSIF_RX_INTR_STATUS0_REG_EN_INTR_STATUS0_REG_EN_DEFAULT 0x00000000
-
-/***************************************************************************
- *PARSERS_TSMF_FRAME_ERROR_INTR_STATUS0_REG - Interrupt Status Register
- ***************************************************************************/
-/* XPT_FE :: PARSERS_TSMF_FRAME_ERROR_INTR_STATUS0_REG :: PARSER31_TSMF_FRAME_ERROR [31:31] */
-#define BCHP_XPT_FE_PARSERS_TSMF_FRAME_ERROR_INTR_STATUS0_REG_PARSER31_TSMF_FRAME_ERROR_MASK 0x80000000
-#define BCHP_XPT_FE_PARSERS_TSMF_FRAME_ERROR_INTR_STATUS0_REG_PARSER31_TSMF_FRAME_ERROR_SHIFT 31
-#define BCHP_XPT_FE_PARSERS_TSMF_FRAME_ERROR_INTR_STATUS0_REG_PARSER31_TSMF_FRAME_ERROR_DEFAULT 0x00000000
-
-/* XPT_FE :: PARSERS_TSMF_FRAME_ERROR_INTR_STATUS0_REG :: PARSER30_TSMF_FRAME_ERROR [30:30] */
-#define BCHP_XPT_FE_PARSERS_TSMF_FRAME_ERROR_INTR_STATUS0_REG_PARSER30_TSMF_FRAME_ERROR_MASK 0x40000000
-#define BCHP_XPT_FE_PARSERS_TSMF_FRAME_ERROR_INTR_STATUS0_REG_PARSER30_TSMF_FRAME_ERROR_SHIFT 30
-#define BCHP_XPT_FE_PARSERS_TSMF_FRAME_ERROR_INTR_STATUS0_REG_PARSER30_TSMF_FRAME_ERROR_DEFAULT 0x00000000
-
-/* XPT_FE :: PARSERS_TSMF_FRAME_ERROR_INTR_STATUS0_REG :: PARSER29_TSMF_FRAME_ERROR [29:29] */
-#define BCHP_XPT_FE_PARSERS_TSMF_FRAME_ERROR_INTR_STATUS0_REG_PARSER29_TSMF_FRAME_ERROR_MASK 0x20000000
-#define BCHP_XPT_FE_PARSERS_TSMF_FRAME_ERROR_INTR_STATUS0_REG_PARSER29_TSMF_FRAME_ERROR_SHIFT 29
-#define BCHP_XPT_FE_PARSERS_TSMF_FRAME_ERROR_INTR_STATUS0_REG_PARSER29_TSMF_FRAME_ERROR_DEFAULT 0x00000000
-
-/* XPT_FE :: PARSERS_TSMF_FRAME_ERROR_INTR_STATUS0_REG :: PARSER28_TSMF_FRAME_ERROR [28:28] */
-#define BCHP_XPT_FE_PARSERS_TSMF_FRAME_ERROR_INTR_STATUS0_REG_PARSER28_TSMF_FRAME_ERROR_MASK 0x10000000
-#define BCHP_XPT_FE_PARSERS_TSMF_FRAME_ERROR_INTR_STATUS0_REG_PARSER28_TSMF_FRAME_ERROR_SHIFT 28
-#define BCHP_XPT_FE_PARSERS_TSMF_FRAME_ERROR_INTR_STATUS0_REG_PARSER28_TSMF_FRAME_ERROR_DEFAULT 0x00000000
-
-/* XPT_FE :: PARSERS_TSMF_FRAME_ERROR_INTR_STATUS0_REG :: PARSER27_TSMF_FRAME_ERROR [27:27] */
-#define BCHP_XPT_FE_PARSERS_TSMF_FRAME_ERROR_INTR_STATUS0_REG_PARSER27_TSMF_FRAME_ERROR_MASK 0x08000000
-#define BCHP_XPT_FE_PARSERS_TSMF_FRAME_ERROR_INTR_STATUS0_REG_PARSER27_TSMF_FRAME_ERROR_SHIFT 27
-#define BCHP_XPT_FE_PARSERS_TSMF_FRAME_ERROR_INTR_STATUS0_REG_PARSER27_TSMF_FRAME_ERROR_DEFAULT 0x00000000
-
-/* XPT_FE :: PARSERS_TSMF_FRAME_ERROR_INTR_STATUS0_REG :: PARSER26_TSMF_FRAME_ERROR [26:26] */
-#define BCHP_XPT_FE_PARSERS_TSMF_FRAME_ERROR_INTR_STATUS0_REG_PARSER26_TSMF_FRAME_ERROR_MASK 0x04000000
-#define BCHP_XPT_FE_PARSERS_TSMF_FRAME_ERROR_INTR_STATUS0_REG_PARSER26_TSMF_FRAME_ERROR_SHIFT 26
-#define BCHP_XPT_FE_PARSERS_TSMF_FRAME_ERROR_INTR_STATUS0_REG_PARSER26_TSMF_FRAME_ERROR_DEFAULT 0x00000000
-
-/* XPT_FE :: PARSERS_TSMF_FRAME_ERROR_INTR_STATUS0_REG :: PARSER25_TSMF_FRAME_ERROR [25:25] */
-#define BCHP_XPT_FE_PARSERS_TSMF_FRAME_ERROR_INTR_STATUS0_REG_PARSER25_TSMF_FRAME_ERROR_MASK 0x02000000
-#define BCHP_XPT_FE_PARSERS_TSMF_FRAME_ERROR_INTR_STATUS0_REG_PARSER25_TSMF_FRAME_ERROR_SHIFT 25
-#define BCHP_XPT_FE_PARSERS_TSMF_FRAME_ERROR_INTR_STATUS0_REG_PARSER25_TSMF_FRAME_ERROR_DEFAULT 0x00000000
-
-/* XPT_FE :: PARSERS_TSMF_FRAME_ERROR_INTR_STATUS0_REG :: PARSER24_TSMF_FRAME_ERROR [24:24] */
-#define BCHP_XPT_FE_PARSERS_TSMF_FRAME_ERROR_INTR_STATUS0_REG_PARSER24_TSMF_FRAME_ERROR_MASK 0x01000000
-#define BCHP_XPT_FE_PARSERS_TSMF_FRAME_ERROR_INTR_STATUS0_REG_PARSER24_TSMF_FRAME_ERROR_SHIFT 24
-#define BCHP_XPT_FE_PARSERS_TSMF_FRAME_ERROR_INTR_STATUS0_REG_PARSER24_TSMF_FRAME_ERROR_DEFAULT 0x00000000
-
-/* XPT_FE :: PARSERS_TSMF_FRAME_ERROR_INTR_STATUS0_REG :: PARSER23_TSMF_FRAME_ERROR [23:23] */
-#define BCHP_XPT_FE_PARSERS_TSMF_FRAME_ERROR_INTR_STATUS0_REG_PARSER23_TSMF_FRAME_ERROR_MASK 0x00800000
-#define BCHP_XPT_FE_PARSERS_TSMF_FRAME_ERROR_INTR_STATUS0_REG_PARSER23_TSMF_FRAME_ERROR_SHIFT 23
-#define BCHP_XPT_FE_PARSERS_TSMF_FRAME_ERROR_INTR_STATUS0_REG_PARSER23_TSMF_FRAME_ERROR_DEFAULT 0x00000000
-
-/* XPT_FE :: PARSERS_TSMF_FRAME_ERROR_INTR_STATUS0_REG :: PARSER22_TSMF_FRAME_ERROR [22:22] */
-#define BCHP_XPT_FE_PARSERS_TSMF_FRAME_ERROR_INTR_STATUS0_REG_PARSER22_TSMF_FRAME_ERROR_MASK 0x00400000
-#define BCHP_XPT_FE_PARSERS_TSMF_FRAME_ERROR_INTR_STATUS0_REG_PARSER22_TSMF_FRAME_ERROR_SHIFT 22
-#define BCHP_XPT_FE_PARSERS_TSMF_FRAME_ERROR_INTR_STATUS0_REG_PARSER22_TSMF_FRAME_ERROR_DEFAULT 0x00000000
-
-/* XPT_FE :: PARSERS_TSMF_FRAME_ERROR_INTR_STATUS0_REG :: PARSER21_TSMF_FRAME_ERROR [21:21] */
-#define BCHP_XPT_FE_PARSERS_TSMF_FRAME_ERROR_INTR_STATUS0_REG_PARSER21_TSMF_FRAME_ERROR_MASK 0x00200000
-#define BCHP_XPT_FE_PARSERS_TSMF_FRAME_ERROR_INTR_STATUS0_REG_PARSER21_TSMF_FRAME_ERROR_SHIFT 21
-#define BCHP_XPT_FE_PARSERS_TSMF_FRAME_ERROR_INTR_STATUS0_REG_PARSER21_TSMF_FRAME_ERROR_DEFAULT 0x00000000
-
-/* XPT_FE :: PARSERS_TSMF_FRAME_ERROR_INTR_STATUS0_REG :: PARSER20_TSMF_FRAME_ERROR [20:20] */
-#define BCHP_XPT_FE_PARSERS_TSMF_FRAME_ERROR_INTR_STATUS0_REG_PARSER20_TSMF_FRAME_ERROR_MASK 0x00100000
-#define BCHP_XPT_FE_PARSERS_TSMF_FRAME_ERROR_INTR_STATUS0_REG_PARSER20_TSMF_FRAME_ERROR_SHIFT 20
-#define BCHP_XPT_FE_PARSERS_TSMF_FRAME_ERROR_INTR_STATUS0_REG_PARSER20_TSMF_FRAME_ERROR_DEFAULT 0x00000000
-
-/* XPT_FE :: PARSERS_TSMF_FRAME_ERROR_INTR_STATUS0_REG :: PARSER19_TSMF_FRAME_ERROR [19:19] */
-#define BCHP_XPT_FE_PARSERS_TSMF_FRAME_ERROR_INTR_STATUS0_REG_PARSER19_TSMF_FRAME_ERROR_MASK 0x00080000
-#define BCHP_XPT_FE_PARSERS_TSMF_FRAME_ERROR_INTR_STATUS0_REG_PARSER19_TSMF_FRAME_ERROR_SHIFT 19
-#define BCHP_XPT_FE_PARSERS_TSMF_FRAME_ERROR_INTR_STATUS0_REG_PARSER19_TSMF_FRAME_ERROR_DEFAULT 0x00000000
-
-/* XPT_FE :: PARSERS_TSMF_FRAME_ERROR_INTR_STATUS0_REG :: PARSER18_TSMF_FRAME_ERROR [18:18] */
-#define BCHP_XPT_FE_PARSERS_TSMF_FRAME_ERROR_INTR_STATUS0_REG_PARSER18_TSMF_FRAME_ERROR_MASK 0x00040000
-#define BCHP_XPT_FE_PARSERS_TSMF_FRAME_ERROR_INTR_STATUS0_REG_PARSER18_TSMF_FRAME_ERROR_SHIFT 18
-#define BCHP_XPT_FE_PARSERS_TSMF_FRAME_ERROR_INTR_STATUS0_REG_PARSER18_TSMF_FRAME_ERROR_DEFAULT 0x00000000
-
-/* XPT_FE :: PARSERS_TSMF_FRAME_ERROR_INTR_STATUS0_REG :: PARSER17_TSMF_FRAME_ERROR [17:17] */
-#define BCHP_XPT_FE_PARSERS_TSMF_FRAME_ERROR_INTR_STATUS0_REG_PARSER17_TSMF_FRAME_ERROR_MASK 0x00020000
-#define BCHP_XPT_FE_PARSERS_TSMF_FRAME_ERROR_INTR_STATUS0_REG_PARSER17_TSMF_FRAME_ERROR_SHIFT 17
-#define BCHP_XPT_FE_PARSERS_TSMF_FRAME_ERROR_INTR_STATUS0_REG_PARSER17_TSMF_FRAME_ERROR_DEFAULT 0x00000000
-
-/* XPT_FE :: PARSERS_TSMF_FRAME_ERROR_INTR_STATUS0_REG :: PARSER16_TSMF_FRAME_ERROR [16:16] */
-#define BCHP_XPT_FE_PARSERS_TSMF_FRAME_ERROR_INTR_STATUS0_REG_PARSER16_TSMF_FRAME_ERROR_MASK 0x00010000
-#define BCHP_XPT_FE_PARSERS_TSMF_FRAME_ERROR_INTR_STATUS0_REG_PARSER16_TSMF_FRAME_ERROR_SHIFT 16
-#define BCHP_XPT_FE_PARSERS_TSMF_FRAME_ERROR_INTR_STATUS0_REG_PARSER16_TSMF_FRAME_ERROR_DEFAULT 0x00000000
-
-/* XPT_FE :: PARSERS_TSMF_FRAME_ERROR_INTR_STATUS0_REG :: PARSER15_TSMF_FRAME_ERROR [15:15] */
-#define BCHP_XPT_FE_PARSERS_TSMF_FRAME_ERROR_INTR_STATUS0_REG_PARSER15_TSMF_FRAME_ERROR_MASK 0x00008000
-#define BCHP_XPT_FE_PARSERS_TSMF_FRAME_ERROR_INTR_STATUS0_REG_PARSER15_TSMF_FRAME_ERROR_SHIFT 15
-#define BCHP_XPT_FE_PARSERS_TSMF_FRAME_ERROR_INTR_STATUS0_REG_PARSER15_TSMF_FRAME_ERROR_DEFAULT 0x00000000
-
-/* XPT_FE :: PARSERS_TSMF_FRAME_ERROR_INTR_STATUS0_REG :: PARSER14_TSMF_FRAME_ERROR [14:14] */
-#define BCHP_XPT_FE_PARSERS_TSMF_FRAME_ERROR_INTR_STATUS0_REG_PARSER14_TSMF_FRAME_ERROR_MASK 0x00004000
-#define BCHP_XPT_FE_PARSERS_TSMF_FRAME_ERROR_INTR_STATUS0_REG_PARSER14_TSMF_FRAME_ERROR_SHIFT 14
-#define BCHP_XPT_FE_PARSERS_TSMF_FRAME_ERROR_INTR_STATUS0_REG_PARSER14_TSMF_FRAME_ERROR_DEFAULT 0x00000000
-
-/* XPT_FE :: PARSERS_TSMF_FRAME_ERROR_INTR_STATUS0_REG :: PARSER13_TSMF_FRAME_ERROR [13:13] */
-#define BCHP_XPT_FE_PARSERS_TSMF_FRAME_ERROR_INTR_STATUS0_REG_PARSER13_TSMF_FRAME_ERROR_MASK 0x00002000
-#define BCHP_XPT_FE_PARSERS_TSMF_FRAME_ERROR_INTR_STATUS0_REG_PARSER13_TSMF_FRAME_ERROR_SHIFT 13
-#define BCHP_XPT_FE_PARSERS_TSMF_FRAME_ERROR_INTR_STATUS0_REG_PARSER13_TSMF_FRAME_ERROR_DEFAULT 0x00000000
-
-/* XPT_FE :: PARSERS_TSMF_FRAME_ERROR_INTR_STATUS0_REG :: PARSER12_TSMF_FRAME_ERROR [12:12] */
-#define BCHP_XPT_FE_PARSERS_TSMF_FRAME_ERROR_INTR_STATUS0_REG_PARSER12_TSMF_FRAME_ERROR_MASK 0x00001000
-#define BCHP_XPT_FE_PARSERS_TSMF_FRAME_ERROR_INTR_STATUS0_REG_PARSER12_TSMF_FRAME_ERROR_SHIFT 12
-#define BCHP_XPT_FE_PARSERS_TSMF_FRAME_ERROR_INTR_STATUS0_REG_PARSER12_TSMF_FRAME_ERROR_DEFAULT 0x00000000
-
-/* XPT_FE :: PARSERS_TSMF_FRAME_ERROR_INTR_STATUS0_REG :: PARSER11_TSMF_FRAME_ERROR [11:11] */
-#define BCHP_XPT_FE_PARSERS_TSMF_FRAME_ERROR_INTR_STATUS0_REG_PARSER11_TSMF_FRAME_ERROR_MASK 0x00000800
-#define BCHP_XPT_FE_PARSERS_TSMF_FRAME_ERROR_INTR_STATUS0_REG_PARSER11_TSMF_FRAME_ERROR_SHIFT 11
-#define BCHP_XPT_FE_PARSERS_TSMF_FRAME_ERROR_INTR_STATUS0_REG_PARSER11_TSMF_FRAME_ERROR_DEFAULT 0x00000000
-
-/* XPT_FE :: PARSERS_TSMF_FRAME_ERROR_INTR_STATUS0_REG :: PARSER10_TSMF_FRAME_ERROR [10:10] */
-#define BCHP_XPT_FE_PARSERS_TSMF_FRAME_ERROR_INTR_STATUS0_REG_PARSER10_TSMF_FRAME_ERROR_MASK 0x00000400
-#define BCHP_XPT_FE_PARSERS_TSMF_FRAME_ERROR_INTR_STATUS0_REG_PARSER10_TSMF_FRAME_ERROR_SHIFT 10
-#define BCHP_XPT_FE_PARSERS_TSMF_FRAME_ERROR_INTR_STATUS0_REG_PARSER10_TSMF_FRAME_ERROR_DEFAULT 0x00000000
-
-/* XPT_FE :: PARSERS_TSMF_FRAME_ERROR_INTR_STATUS0_REG :: PARSER9_TSMF_FRAME_ERROR [09:09] */
-#define BCHP_XPT_FE_PARSERS_TSMF_FRAME_ERROR_INTR_STATUS0_REG_PARSER9_TSMF_FRAME_ERROR_MASK 0x00000200
-#define BCHP_XPT_FE_PARSERS_TSMF_FRAME_ERROR_INTR_STATUS0_REG_PARSER9_TSMF_FRAME_ERROR_SHIFT 9
-#define BCHP_XPT_FE_PARSERS_TSMF_FRAME_ERROR_INTR_STATUS0_REG_PARSER9_TSMF_FRAME_ERROR_DEFAULT 0x00000000
-
-/* XPT_FE :: PARSERS_TSMF_FRAME_ERROR_INTR_STATUS0_REG :: PARSER8_TSMF_FRAME_ERROR [08:08] */
-#define BCHP_XPT_FE_PARSERS_TSMF_FRAME_ERROR_INTR_STATUS0_REG_PARSER8_TSMF_FRAME_ERROR_MASK 0x00000100
-#define BCHP_XPT_FE_PARSERS_TSMF_FRAME_ERROR_INTR_STATUS0_REG_PARSER8_TSMF_FRAME_ERROR_SHIFT 8
-#define BCHP_XPT_FE_PARSERS_TSMF_FRAME_ERROR_INTR_STATUS0_REG_PARSER8_TSMF_FRAME_ERROR_DEFAULT 0x00000000
-
-/* XPT_FE :: PARSERS_TSMF_FRAME_ERROR_INTR_STATUS0_REG :: PARSER7_TSMF_FRAME_ERROR [07:07] */
-#define BCHP_XPT_FE_PARSERS_TSMF_FRAME_ERROR_INTR_STATUS0_REG_PARSER7_TSMF_FRAME_ERROR_MASK 0x00000080
-#define BCHP_XPT_FE_PARSERS_TSMF_FRAME_ERROR_INTR_STATUS0_REG_PARSER7_TSMF_FRAME_ERROR_SHIFT 7
-#define BCHP_XPT_FE_PARSERS_TSMF_FRAME_ERROR_INTR_STATUS0_REG_PARSER7_TSMF_FRAME_ERROR_DEFAULT 0x00000000
-
-/* XPT_FE :: PARSERS_TSMF_FRAME_ERROR_INTR_STATUS0_REG :: PARSER6_TSMF_FRAME_ERROR [06:06] */
-#define BCHP_XPT_FE_PARSERS_TSMF_FRAME_ERROR_INTR_STATUS0_REG_PARSER6_TSMF_FRAME_ERROR_MASK 0x00000040
-#define BCHP_XPT_FE_PARSERS_TSMF_FRAME_ERROR_INTR_STATUS0_REG_PARSER6_TSMF_FRAME_ERROR_SHIFT 6
-#define BCHP_XPT_FE_PARSERS_TSMF_FRAME_ERROR_INTR_STATUS0_REG_PARSER6_TSMF_FRAME_ERROR_DEFAULT 0x00000000
-
-/* XPT_FE :: PARSERS_TSMF_FRAME_ERROR_INTR_STATUS0_REG :: PARSER5_TSMF_FRAME_ERROR [05:05] */
-#define BCHP_XPT_FE_PARSERS_TSMF_FRAME_ERROR_INTR_STATUS0_REG_PARSER5_TSMF_FRAME_ERROR_MASK 0x00000020
-#define BCHP_XPT_FE_PARSERS_TSMF_FRAME_ERROR_INTR_STATUS0_REG_PARSER5_TSMF_FRAME_ERROR_SHIFT 5
-#define BCHP_XPT_FE_PARSERS_TSMF_FRAME_ERROR_INTR_STATUS0_REG_PARSER5_TSMF_FRAME_ERROR_DEFAULT 0x00000000
-
-/* XPT_FE :: PARSERS_TSMF_FRAME_ERROR_INTR_STATUS0_REG :: PARSER4_TSMF_FRAME_ERROR [04:04] */
-#define BCHP_XPT_FE_PARSERS_TSMF_FRAME_ERROR_INTR_STATUS0_REG_PARSER4_TSMF_FRAME_ERROR_MASK 0x00000010
-#define BCHP_XPT_FE_PARSERS_TSMF_FRAME_ERROR_INTR_STATUS0_REG_PARSER4_TSMF_FRAME_ERROR_SHIFT 4
-#define BCHP_XPT_FE_PARSERS_TSMF_FRAME_ERROR_INTR_STATUS0_REG_PARSER4_TSMF_FRAME_ERROR_DEFAULT 0x00000000
-
-/* XPT_FE :: PARSERS_TSMF_FRAME_ERROR_INTR_STATUS0_REG :: PARSER3_TSMF_FRAME_ERROR [03:03] */
-#define BCHP_XPT_FE_PARSERS_TSMF_FRAME_ERROR_INTR_STATUS0_REG_PARSER3_TSMF_FRAME_ERROR_MASK 0x00000008
-#define BCHP_XPT_FE_PARSERS_TSMF_FRAME_ERROR_INTR_STATUS0_REG_PARSER3_TSMF_FRAME_ERROR_SHIFT 3
-#define BCHP_XPT_FE_PARSERS_TSMF_FRAME_ERROR_INTR_STATUS0_REG_PARSER3_TSMF_FRAME_ERROR_DEFAULT 0x00000000
-
-/* XPT_FE :: PARSERS_TSMF_FRAME_ERROR_INTR_STATUS0_REG :: PARSER2_TSMF_FRAME_ERROR [02:02] */
-#define BCHP_XPT_FE_PARSERS_TSMF_FRAME_ERROR_INTR_STATUS0_REG_PARSER2_TSMF_FRAME_ERROR_MASK 0x00000004
-#define BCHP_XPT_FE_PARSERS_TSMF_FRAME_ERROR_INTR_STATUS0_REG_PARSER2_TSMF_FRAME_ERROR_SHIFT 2
-#define BCHP_XPT_FE_PARSERS_TSMF_FRAME_ERROR_INTR_STATUS0_REG_PARSER2_TSMF_FRAME_ERROR_DEFAULT 0x00000000
-
-/* XPT_FE :: PARSERS_TSMF_FRAME_ERROR_INTR_STATUS0_REG :: PARSER1_TSMF_FRAME_ERROR [01:01] */
-#define BCHP_XPT_FE_PARSERS_TSMF_FRAME_ERROR_INTR_STATUS0_REG_PARSER1_TSMF_FRAME_ERROR_MASK 0x00000002
-#define BCHP_XPT_FE_PARSERS_TSMF_FRAME_ERROR_INTR_STATUS0_REG_PARSER1_TSMF_FRAME_ERROR_SHIFT 1
-#define BCHP_XPT_FE_PARSERS_TSMF_FRAME_ERROR_INTR_STATUS0_REG_PARSER1_TSMF_FRAME_ERROR_DEFAULT 0x00000000
-
-/* XPT_FE :: PARSERS_TSMF_FRAME_ERROR_INTR_STATUS0_REG :: PARSER0_TSMF_FRAME_ERROR [00:00] */
-#define BCHP_XPT_FE_PARSERS_TSMF_FRAME_ERROR_INTR_STATUS0_REG_PARSER0_TSMF_FRAME_ERROR_MASK 0x00000001
-#define BCHP_XPT_FE_PARSERS_TSMF_FRAME_ERROR_INTR_STATUS0_REG_PARSER0_TSMF_FRAME_ERROR_SHIFT 0
-#define BCHP_XPT_FE_PARSERS_TSMF_FRAME_ERROR_INTR_STATUS0_REG_PARSER0_TSMF_FRAME_ERROR_DEFAULT 0x00000000
-
-/***************************************************************************
- *PARSERS_TSMF_SYNC_ERROR_INTR_STATUS0_REG - Interrupt Status Register
- ***************************************************************************/
-/* XPT_FE :: PARSERS_TSMF_SYNC_ERROR_INTR_STATUS0_REG :: PARSER31_TSMF_SYNC_ERROR [31:31] */
-#define BCHP_XPT_FE_PARSERS_TSMF_SYNC_ERROR_INTR_STATUS0_REG_PARSER31_TSMF_SYNC_ERROR_MASK 0x80000000
-#define BCHP_XPT_FE_PARSERS_TSMF_SYNC_ERROR_INTR_STATUS0_REG_PARSER31_TSMF_SYNC_ERROR_SHIFT 31
-#define BCHP_XPT_FE_PARSERS_TSMF_SYNC_ERROR_INTR_STATUS0_REG_PARSER31_TSMF_SYNC_ERROR_DEFAULT 0x00000000
-
-/* XPT_FE :: PARSERS_TSMF_SYNC_ERROR_INTR_STATUS0_REG :: PARSER30_TSMF_SYNC_ERROR [30:30] */
-#define BCHP_XPT_FE_PARSERS_TSMF_SYNC_ERROR_INTR_STATUS0_REG_PARSER30_TSMF_SYNC_ERROR_MASK 0x40000000
-#define BCHP_XPT_FE_PARSERS_TSMF_SYNC_ERROR_INTR_STATUS0_REG_PARSER30_TSMF_SYNC_ERROR_SHIFT 30
-#define BCHP_XPT_FE_PARSERS_TSMF_SYNC_ERROR_INTR_STATUS0_REG_PARSER30_TSMF_SYNC_ERROR_DEFAULT 0x00000000
-
-/* XPT_FE :: PARSERS_TSMF_SYNC_ERROR_INTR_STATUS0_REG :: PARSER29_TSMF_SYNC_ERROR [29:29] */
-#define BCHP_XPT_FE_PARSERS_TSMF_SYNC_ERROR_INTR_STATUS0_REG_PARSER29_TSMF_SYNC_ERROR_MASK 0x20000000
-#define BCHP_XPT_FE_PARSERS_TSMF_SYNC_ERROR_INTR_STATUS0_REG_PARSER29_TSMF_SYNC_ERROR_SHIFT 29
-#define BCHP_XPT_FE_PARSERS_TSMF_SYNC_ERROR_INTR_STATUS0_REG_PARSER29_TSMF_SYNC_ERROR_DEFAULT 0x00000000
-
-/* XPT_FE :: PARSERS_TSMF_SYNC_ERROR_INTR_STATUS0_REG :: PARSER28_TSMF_SYNC_ERROR [28:28] */
-#define BCHP_XPT_FE_PARSERS_TSMF_SYNC_ERROR_INTR_STATUS0_REG_PARSER28_TSMF_SYNC_ERROR_MASK 0x10000000
-#define BCHP_XPT_FE_PARSERS_TSMF_SYNC_ERROR_INTR_STATUS0_REG_PARSER28_TSMF_SYNC_ERROR_SHIFT 28
-#define BCHP_XPT_FE_PARSERS_TSMF_SYNC_ERROR_INTR_STATUS0_REG_PARSER28_TSMF_SYNC_ERROR_DEFAULT 0x00000000
-
-/* XPT_FE :: PARSERS_TSMF_SYNC_ERROR_INTR_STATUS0_REG :: PARSER27_TSMF_SYNC_ERROR [27:27] */
-#define BCHP_XPT_FE_PARSERS_TSMF_SYNC_ERROR_INTR_STATUS0_REG_PARSER27_TSMF_SYNC_ERROR_MASK 0x08000000
-#define BCHP_XPT_FE_PARSERS_TSMF_SYNC_ERROR_INTR_STATUS0_REG_PARSER27_TSMF_SYNC_ERROR_SHIFT 27
-#define BCHP_XPT_FE_PARSERS_TSMF_SYNC_ERROR_INTR_STATUS0_REG_PARSER27_TSMF_SYNC_ERROR_DEFAULT 0x00000000
-
-/* XPT_FE :: PARSERS_TSMF_SYNC_ERROR_INTR_STATUS0_REG :: PARSER26_TSMF_SYNC_ERROR [26:26] */
-#define BCHP_XPT_FE_PARSERS_TSMF_SYNC_ERROR_INTR_STATUS0_REG_PARSER26_TSMF_SYNC_ERROR_MASK 0x04000000
-#define BCHP_XPT_FE_PARSERS_TSMF_SYNC_ERROR_INTR_STATUS0_REG_PARSER26_TSMF_SYNC_ERROR_SHIFT 26
-#define BCHP_XPT_FE_PARSERS_TSMF_SYNC_ERROR_INTR_STATUS0_REG_PARSER26_TSMF_SYNC_ERROR_DEFAULT 0x00000000
-
-/* XPT_FE :: PARSERS_TSMF_SYNC_ERROR_INTR_STATUS0_REG :: PARSER25_TSMF_SYNC_ERROR [25:25] */
-#define BCHP_XPT_FE_PARSERS_TSMF_SYNC_ERROR_INTR_STATUS0_REG_PARSER25_TSMF_SYNC_ERROR_MASK 0x02000000
-#define BCHP_XPT_FE_PARSERS_TSMF_SYNC_ERROR_INTR_STATUS0_REG_PARSER25_TSMF_SYNC_ERROR_SHIFT 25
-#define BCHP_XPT_FE_PARSERS_TSMF_SYNC_ERROR_INTR_STATUS0_REG_PARSER25_TSMF_SYNC_ERROR_DEFAULT 0x00000000
-
-/* XPT_FE :: PARSERS_TSMF_SYNC_ERROR_INTR_STATUS0_REG :: PARSER24_TSMF_SYNC_ERROR [24:24] */
-#define BCHP_XPT_FE_PARSERS_TSMF_SYNC_ERROR_INTR_STATUS0_REG_PARSER24_TSMF_SYNC_ERROR_MASK 0x01000000
-#define BCHP_XPT_FE_PARSERS_TSMF_SYNC_ERROR_INTR_STATUS0_REG_PARSER24_TSMF_SYNC_ERROR_SHIFT 24
-#define BCHP_XPT_FE_PARSERS_TSMF_SYNC_ERROR_INTR_STATUS0_REG_PARSER24_TSMF_SYNC_ERROR_DEFAULT 0x00000000
-
-/* XPT_FE :: PARSERS_TSMF_SYNC_ERROR_INTR_STATUS0_REG :: PARSER23_TSMF_SYNC_ERROR [23:23] */
-#define BCHP_XPT_FE_PARSERS_TSMF_SYNC_ERROR_INTR_STATUS0_REG_PARSER23_TSMF_SYNC_ERROR_MASK 0x00800000
-#define BCHP_XPT_FE_PARSERS_TSMF_SYNC_ERROR_INTR_STATUS0_REG_PARSER23_TSMF_SYNC_ERROR_SHIFT 23
-#define BCHP_XPT_FE_PARSERS_TSMF_SYNC_ERROR_INTR_STATUS0_REG_PARSER23_TSMF_SYNC_ERROR_DEFAULT 0x00000000
-
-/* XPT_FE :: PARSERS_TSMF_SYNC_ERROR_INTR_STATUS0_REG :: PARSER22_TSMF_SYNC_ERROR [22:22] */
-#define BCHP_XPT_FE_PARSERS_TSMF_SYNC_ERROR_INTR_STATUS0_REG_PARSER22_TSMF_SYNC_ERROR_MASK 0x00400000
-#define BCHP_XPT_FE_PARSERS_TSMF_SYNC_ERROR_INTR_STATUS0_REG_PARSER22_TSMF_SYNC_ERROR_SHIFT 22
-#define BCHP_XPT_FE_PARSERS_TSMF_SYNC_ERROR_INTR_STATUS0_REG_PARSER22_TSMF_SYNC_ERROR_DEFAULT 0x00000000
-
-/* XPT_FE :: PARSERS_TSMF_SYNC_ERROR_INTR_STATUS0_REG :: PARSER21_TSMF_SYNC_ERROR [21:21] */
-#define BCHP_XPT_FE_PARSERS_TSMF_SYNC_ERROR_INTR_STATUS0_REG_PARSER21_TSMF_SYNC_ERROR_MASK 0x00200000
-#define BCHP_XPT_FE_PARSERS_TSMF_SYNC_ERROR_INTR_STATUS0_REG_PARSER21_TSMF_SYNC_ERROR_SHIFT 21
-#define BCHP_XPT_FE_PARSERS_TSMF_SYNC_ERROR_INTR_STATUS0_REG_PARSER21_TSMF_SYNC_ERROR_DEFAULT 0x00000000
-
-/* XPT_FE :: PARSERS_TSMF_SYNC_ERROR_INTR_STATUS0_REG :: PARSER20_TSMF_SYNC_ERROR [20:20] */
-#define BCHP_XPT_FE_PARSERS_TSMF_SYNC_ERROR_INTR_STATUS0_REG_PARSER20_TSMF_SYNC_ERROR_MASK 0x00100000
-#define BCHP_XPT_FE_PARSERS_TSMF_SYNC_ERROR_INTR_STATUS0_REG_PARSER20_TSMF_SYNC_ERROR_SHIFT 20
-#define BCHP_XPT_FE_PARSERS_TSMF_SYNC_ERROR_INTR_STATUS0_REG_PARSER20_TSMF_SYNC_ERROR_DEFAULT 0x00000000
-
-/* XPT_FE :: PARSERS_TSMF_SYNC_ERROR_INTR_STATUS0_REG :: PARSER19_TSMF_SYNC_ERROR [19:19] */
-#define BCHP_XPT_FE_PARSERS_TSMF_SYNC_ERROR_INTR_STATUS0_REG_PARSER19_TSMF_SYNC_ERROR_MASK 0x00080000
-#define BCHP_XPT_FE_PARSERS_TSMF_SYNC_ERROR_INTR_STATUS0_REG_PARSER19_TSMF_SYNC_ERROR_SHIFT 19
-#define BCHP_XPT_FE_PARSERS_TSMF_SYNC_ERROR_INTR_STATUS0_REG_PARSER19_TSMF_SYNC_ERROR_DEFAULT 0x00000000
-
-/* XPT_FE :: PARSERS_TSMF_SYNC_ERROR_INTR_STATUS0_REG :: PARSER18_TSMF_SYNC_ERROR [18:18] */
-#define BCHP_XPT_FE_PARSERS_TSMF_SYNC_ERROR_INTR_STATUS0_REG_PARSER18_TSMF_SYNC_ERROR_MASK 0x00040000
-#define BCHP_XPT_FE_PARSERS_TSMF_SYNC_ERROR_INTR_STATUS0_REG_PARSER18_TSMF_SYNC_ERROR_SHIFT 18
-#define BCHP_XPT_FE_PARSERS_TSMF_SYNC_ERROR_INTR_STATUS0_REG_PARSER18_TSMF_SYNC_ERROR_DEFAULT 0x00000000
-
-/* XPT_FE :: PARSERS_TSMF_SYNC_ERROR_INTR_STATUS0_REG :: PARSER17_TSMF_SYNC_ERROR [17:17] */
-#define BCHP_XPT_FE_PARSERS_TSMF_SYNC_ERROR_INTR_STATUS0_REG_PARSER17_TSMF_SYNC_ERROR_MASK 0x00020000
-#define BCHP_XPT_FE_PARSERS_TSMF_SYNC_ERROR_INTR_STATUS0_REG_PARSER17_TSMF_SYNC_ERROR_SHIFT 17
-#define BCHP_XPT_FE_PARSERS_TSMF_SYNC_ERROR_INTR_STATUS0_REG_PARSER17_TSMF_SYNC_ERROR_DEFAULT 0x00000000
-
-/* XPT_FE :: PARSERS_TSMF_SYNC_ERROR_INTR_STATUS0_REG :: PARSER16_TSMF_SYNC_ERROR [16:16] */
-#define BCHP_XPT_FE_PARSERS_TSMF_SYNC_ERROR_INTR_STATUS0_REG_PARSER16_TSMF_SYNC_ERROR_MASK 0x00010000
-#define BCHP_XPT_FE_PARSERS_TSMF_SYNC_ERROR_INTR_STATUS0_REG_PARSER16_TSMF_SYNC_ERROR_SHIFT 16
-#define BCHP_XPT_FE_PARSERS_TSMF_SYNC_ERROR_INTR_STATUS0_REG_PARSER16_TSMF_SYNC_ERROR_DEFAULT 0x00000000
-
-/* XPT_FE :: PARSERS_TSMF_SYNC_ERROR_INTR_STATUS0_REG :: PARSER15_TSMF_SYNC_ERROR [15:15] */
-#define BCHP_XPT_FE_PARSERS_TSMF_SYNC_ERROR_INTR_STATUS0_REG_PARSER15_TSMF_SYNC_ERROR_MASK 0x00008000
-#define BCHP_XPT_FE_PARSERS_TSMF_SYNC_ERROR_INTR_STATUS0_REG_PARSER15_TSMF_SYNC_ERROR_SHIFT 15
-#define BCHP_XPT_FE_PARSERS_TSMF_SYNC_ERROR_INTR_STATUS0_REG_PARSER15_TSMF_SYNC_ERROR_DEFAULT 0x00000000
-
-/* XPT_FE :: PARSERS_TSMF_SYNC_ERROR_INTR_STATUS0_REG :: PARSER14_TSMF_SYNC_ERROR [14:14] */
-#define BCHP_XPT_FE_PARSERS_TSMF_SYNC_ERROR_INTR_STATUS0_REG_PARSER14_TSMF_SYNC_ERROR_MASK 0x00004000
-#define BCHP_XPT_FE_PARSERS_TSMF_SYNC_ERROR_INTR_STATUS0_REG_PARSER14_TSMF_SYNC_ERROR_SHIFT 14
-#define BCHP_XPT_FE_PARSERS_TSMF_SYNC_ERROR_INTR_STATUS0_REG_PARSER14_TSMF_SYNC_ERROR_DEFAULT 0x00000000
-
-/* XPT_FE :: PARSERS_TSMF_SYNC_ERROR_INTR_STATUS0_REG :: PARSER13_TSMF_SYNC_ERROR [13:13] */
-#define BCHP_XPT_FE_PARSERS_TSMF_SYNC_ERROR_INTR_STATUS0_REG_PARSER13_TSMF_SYNC_ERROR_MASK 0x00002000
-#define BCHP_XPT_FE_PARSERS_TSMF_SYNC_ERROR_INTR_STATUS0_REG_PARSER13_TSMF_SYNC_ERROR_SHIFT 13
-#define BCHP_XPT_FE_PARSERS_TSMF_SYNC_ERROR_INTR_STATUS0_REG_PARSER13_TSMF_SYNC_ERROR_DEFAULT 0x00000000
-
-/* XPT_FE :: PARSERS_TSMF_SYNC_ERROR_INTR_STATUS0_REG :: PARSER12_TSMF_SYNC_ERROR [12:12] */
-#define BCHP_XPT_FE_PARSERS_TSMF_SYNC_ERROR_INTR_STATUS0_REG_PARSER12_TSMF_SYNC_ERROR_MASK 0x00001000
-#define BCHP_XPT_FE_PARSERS_TSMF_SYNC_ERROR_INTR_STATUS0_REG_PARSER12_TSMF_SYNC_ERROR_SHIFT 12
-#define BCHP_XPT_FE_PARSERS_TSMF_SYNC_ERROR_INTR_STATUS0_REG_PARSER12_TSMF_SYNC_ERROR_DEFAULT 0x00000000
-
-/* XPT_FE :: PARSERS_TSMF_SYNC_ERROR_INTR_STATUS0_REG :: PARSER11_TSMF_SYNC_ERROR [11:11] */
-#define BCHP_XPT_FE_PARSERS_TSMF_SYNC_ERROR_INTR_STATUS0_REG_PARSER11_TSMF_SYNC_ERROR_MASK 0x00000800
-#define BCHP_XPT_FE_PARSERS_TSMF_SYNC_ERROR_INTR_STATUS0_REG_PARSER11_TSMF_SYNC_ERROR_SHIFT 11
-#define BCHP_XPT_FE_PARSERS_TSMF_SYNC_ERROR_INTR_STATUS0_REG_PARSER11_TSMF_SYNC_ERROR_DEFAULT 0x00000000
-
-/* XPT_FE :: PARSERS_TSMF_SYNC_ERROR_INTR_STATUS0_REG :: PARSER10_TSMF_SYNC_ERROR [10:10] */
-#define BCHP_XPT_FE_PARSERS_TSMF_SYNC_ERROR_INTR_STATUS0_REG_PARSER10_TSMF_SYNC_ERROR_MASK 0x00000400
-#define BCHP_XPT_FE_PARSERS_TSMF_SYNC_ERROR_INTR_STATUS0_REG_PARSER10_TSMF_SYNC_ERROR_SHIFT 10
-#define BCHP_XPT_FE_PARSERS_TSMF_SYNC_ERROR_INTR_STATUS0_REG_PARSER10_TSMF_SYNC_ERROR_DEFAULT 0x00000000
-
-/* XPT_FE :: PARSERS_TSMF_SYNC_ERROR_INTR_STATUS0_REG :: PARSER9_TSMF_SYNC_ERROR [09:09] */
-#define BCHP_XPT_FE_PARSERS_TSMF_SYNC_ERROR_INTR_STATUS0_REG_PARSER9_TSMF_SYNC_ERROR_MASK 0x00000200
-#define BCHP_XPT_FE_PARSERS_TSMF_SYNC_ERROR_INTR_STATUS0_REG_PARSER9_TSMF_SYNC_ERROR_SHIFT 9
-#define BCHP_XPT_FE_PARSERS_TSMF_SYNC_ERROR_INTR_STATUS0_REG_PARSER9_TSMF_SYNC_ERROR_DEFAULT 0x00000000
-
-/* XPT_FE :: PARSERS_TSMF_SYNC_ERROR_INTR_STATUS0_REG :: PARSER8_TSMF_SYNC_ERROR [08:08] */
-#define BCHP_XPT_FE_PARSERS_TSMF_SYNC_ERROR_INTR_STATUS0_REG_PARSER8_TSMF_SYNC_ERROR_MASK 0x00000100
-#define BCHP_XPT_FE_PARSERS_TSMF_SYNC_ERROR_INTR_STATUS0_REG_PARSER8_TSMF_SYNC_ERROR_SHIFT 8
-#define BCHP_XPT_FE_PARSERS_TSMF_SYNC_ERROR_INTR_STATUS0_REG_PARSER8_TSMF_SYNC_ERROR_DEFAULT 0x00000000
-
-/* XPT_FE :: PARSERS_TSMF_SYNC_ERROR_INTR_STATUS0_REG :: PARSER7_TSMF_SYNC_ERROR [07:07] */
-#define BCHP_XPT_FE_PARSERS_TSMF_SYNC_ERROR_INTR_STATUS0_REG_PARSER7_TSMF_SYNC_ERROR_MASK 0x00000080
-#define BCHP_XPT_FE_PARSERS_TSMF_SYNC_ERROR_INTR_STATUS0_REG_PARSER7_TSMF_SYNC_ERROR_SHIFT 7
-#define BCHP_XPT_FE_PARSERS_TSMF_SYNC_ERROR_INTR_STATUS0_REG_PARSER7_TSMF_SYNC_ERROR_DEFAULT 0x00000000
-
-/* XPT_FE :: PARSERS_TSMF_SYNC_ERROR_INTR_STATUS0_REG :: PARSER6_TSMF_SYNC_ERROR [06:06] */
-#define BCHP_XPT_FE_PARSERS_TSMF_SYNC_ERROR_INTR_STATUS0_REG_PARSER6_TSMF_SYNC_ERROR_MASK 0x00000040
-#define BCHP_XPT_FE_PARSERS_TSMF_SYNC_ERROR_INTR_STATUS0_REG_PARSER6_TSMF_SYNC_ERROR_SHIFT 6
-#define BCHP_XPT_FE_PARSERS_TSMF_SYNC_ERROR_INTR_STATUS0_REG_PARSER6_TSMF_SYNC_ERROR_DEFAULT 0x00000000
-
-/* XPT_FE :: PARSERS_TSMF_SYNC_ERROR_INTR_STATUS0_REG :: PARSER5_TSMF_SYNC_ERROR [05:05] */
-#define BCHP_XPT_FE_PARSERS_TSMF_SYNC_ERROR_INTR_STATUS0_REG_PARSER5_TSMF_SYNC_ERROR_MASK 0x00000020
-#define BCHP_XPT_FE_PARSERS_TSMF_SYNC_ERROR_INTR_STATUS0_REG_PARSER5_TSMF_SYNC_ERROR_SHIFT 5
-#define BCHP_XPT_FE_PARSERS_TSMF_SYNC_ERROR_INTR_STATUS0_REG_PARSER5_TSMF_SYNC_ERROR_DEFAULT 0x00000000
-
-/* XPT_FE :: PARSERS_TSMF_SYNC_ERROR_INTR_STATUS0_REG :: PARSER4_TSMF_SYNC_ERROR [04:04] */
-#define BCHP_XPT_FE_PARSERS_TSMF_SYNC_ERROR_INTR_STATUS0_REG_PARSER4_TSMF_SYNC_ERROR_MASK 0x00000010
-#define BCHP_XPT_FE_PARSERS_TSMF_SYNC_ERROR_INTR_STATUS0_REG_PARSER4_TSMF_SYNC_ERROR_SHIFT 4
-#define BCHP_XPT_FE_PARSERS_TSMF_SYNC_ERROR_INTR_STATUS0_REG_PARSER4_TSMF_SYNC_ERROR_DEFAULT 0x00000000
-
-/* XPT_FE :: PARSERS_TSMF_SYNC_ERROR_INTR_STATUS0_REG :: PARSER3_TSMF_SYNC_ERROR [03:03] */
-#define BCHP_XPT_FE_PARSERS_TSMF_SYNC_ERROR_INTR_STATUS0_REG_PARSER3_TSMF_SYNC_ERROR_MASK 0x00000008
-#define BCHP_XPT_FE_PARSERS_TSMF_SYNC_ERROR_INTR_STATUS0_REG_PARSER3_TSMF_SYNC_ERROR_SHIFT 3
-#define BCHP_XPT_FE_PARSERS_TSMF_SYNC_ERROR_INTR_STATUS0_REG_PARSER3_TSMF_SYNC_ERROR_DEFAULT 0x00000000
-
-/* XPT_FE :: PARSERS_TSMF_SYNC_ERROR_INTR_STATUS0_REG :: PARSER2_TSMF_SYNC_ERROR [02:02] */
-#define BCHP_XPT_FE_PARSERS_TSMF_SYNC_ERROR_INTR_STATUS0_REG_PARSER2_TSMF_SYNC_ERROR_MASK 0x00000004
-#define BCHP_XPT_FE_PARSERS_TSMF_SYNC_ERROR_INTR_STATUS0_REG_PARSER2_TSMF_SYNC_ERROR_SHIFT 2
-#define BCHP_XPT_FE_PARSERS_TSMF_SYNC_ERROR_INTR_STATUS0_REG_PARSER2_TSMF_SYNC_ERROR_DEFAULT 0x00000000
-
-/* XPT_FE :: PARSERS_TSMF_SYNC_ERROR_INTR_STATUS0_REG :: PARSER1_TSMF_SYNC_ERROR [01:01] */
-#define BCHP_XPT_FE_PARSERS_TSMF_SYNC_ERROR_INTR_STATUS0_REG_PARSER1_TSMF_SYNC_ERROR_MASK 0x00000002
-#define BCHP_XPT_FE_PARSERS_TSMF_SYNC_ERROR_INTR_STATUS0_REG_PARSER1_TSMF_SYNC_ERROR_SHIFT 1
-#define BCHP_XPT_FE_PARSERS_TSMF_SYNC_ERROR_INTR_STATUS0_REG_PARSER1_TSMF_SYNC_ERROR_DEFAULT 0x00000000
-
-/* XPT_FE :: PARSERS_TSMF_SYNC_ERROR_INTR_STATUS0_REG :: PARSER0_TSMF_SYNC_ERROR [00:00] */
-#define BCHP_XPT_FE_PARSERS_TSMF_SYNC_ERROR_INTR_STATUS0_REG_PARSER0_TSMF_SYNC_ERROR_MASK 0x00000001
-#define BCHP_XPT_FE_PARSERS_TSMF_SYNC_ERROR_INTR_STATUS0_REG_PARSER0_TSMF_SYNC_ERROR_SHIFT 0
-#define BCHP_XPT_FE_PARSERS_TSMF_SYNC_ERROR_INTR_STATUS0_REG_PARSER0_TSMF_SYNC_ERROR_DEFAULT 0x00000000
-
-/***************************************************************************
- *PARSERS_INBUFF_OVFL_ERROR_INTR_STATUS0_REG - Interrupt Status Register
- ***************************************************************************/
-/* XPT_FE :: PARSERS_INBUFF_OVFL_ERROR_INTR_STATUS0_REG :: PARSER31_INBUFF_OVFL_ERROR [31:31] */
-#define BCHP_XPT_FE_PARSERS_INBUFF_OVFL_ERROR_INTR_STATUS0_REG_PARSER31_INBUFF_OVFL_ERROR_MASK 0x80000000
-#define BCHP_XPT_FE_PARSERS_INBUFF_OVFL_ERROR_INTR_STATUS0_REG_PARSER31_INBUFF_OVFL_ERROR_SHIFT 31
-#define BCHP_XPT_FE_PARSERS_INBUFF_OVFL_ERROR_INTR_STATUS0_REG_PARSER31_INBUFF_OVFL_ERROR_DEFAULT 0x00000000
-
-/* XPT_FE :: PARSERS_INBUFF_OVFL_ERROR_INTR_STATUS0_REG :: PARSER30_INBUFF_OVFL_ERROR [30:30] */
-#define BCHP_XPT_FE_PARSERS_INBUFF_OVFL_ERROR_INTR_STATUS0_REG_PARSER30_INBUFF_OVFL_ERROR_MASK 0x40000000
-#define BCHP_XPT_FE_PARSERS_INBUFF_OVFL_ERROR_INTR_STATUS0_REG_PARSER30_INBUFF_OVFL_ERROR_SHIFT 30
-#define BCHP_XPT_FE_PARSERS_INBUFF_OVFL_ERROR_INTR_STATUS0_REG_PARSER30_INBUFF_OVFL_ERROR_DEFAULT 0x00000000
-
-/* XPT_FE :: PARSERS_INBUFF_OVFL_ERROR_INTR_STATUS0_REG :: PARSER29_INBUFF_OVFL_ERROR [29:29] */
-#define BCHP_XPT_FE_PARSERS_INBUFF_OVFL_ERROR_INTR_STATUS0_REG_PARSER29_INBUFF_OVFL_ERROR_MASK 0x20000000
-#define BCHP_XPT_FE_PARSERS_INBUFF_OVFL_ERROR_INTR_STATUS0_REG_PARSER29_INBUFF_OVFL_ERROR_SHIFT 29
-#define BCHP_XPT_FE_PARSERS_INBUFF_OVFL_ERROR_INTR_STATUS0_REG_PARSER29_INBUFF_OVFL_ERROR_DEFAULT 0x00000000
-
-/* XPT_FE :: PARSERS_INBUFF_OVFL_ERROR_INTR_STATUS0_REG :: PARSER28_INBUFF_OVFL_ERROR [28:28] */
-#define BCHP_XPT_FE_PARSERS_INBUFF_OVFL_ERROR_INTR_STATUS0_REG_PARSER28_INBUFF_OVFL_ERROR_MASK 0x10000000
-#define BCHP_XPT_FE_PARSERS_INBUFF_OVFL_ERROR_INTR_STATUS0_REG_PARSER28_INBUFF_OVFL_ERROR_SHIFT 28
-#define BCHP_XPT_FE_PARSERS_INBUFF_OVFL_ERROR_INTR_STATUS0_REG_PARSER28_INBUFF_OVFL_ERROR_DEFAULT 0x00000000
-
-/* XPT_FE :: PARSERS_INBUFF_OVFL_ERROR_INTR_STATUS0_REG :: PARSER27_INBUFF_OVFL_ERROR [27:27] */
-#define BCHP_XPT_FE_PARSERS_INBUFF_OVFL_ERROR_INTR_STATUS0_REG_PARSER27_INBUFF_OVFL_ERROR_MASK 0x08000000
-#define BCHP_XPT_FE_PARSERS_INBUFF_OVFL_ERROR_INTR_STATUS0_REG_PARSER27_INBUFF_OVFL_ERROR_SHIFT 27
-#define BCHP_XPT_FE_PARSERS_INBUFF_OVFL_ERROR_INTR_STATUS0_REG_PARSER27_INBUFF_OVFL_ERROR_DEFAULT 0x00000000
-
-/* XPT_FE :: PARSERS_INBUFF_OVFL_ERROR_INTR_STATUS0_REG :: PARSER26_INBUFF_OVFL_ERROR [26:26] */
-#define BCHP_XPT_FE_PARSERS_INBUFF_OVFL_ERROR_INTR_STATUS0_REG_PARSER26_INBUFF_OVFL_ERROR_MASK 0x04000000
-#define BCHP_XPT_FE_PARSERS_INBUFF_OVFL_ERROR_INTR_STATUS0_REG_PARSER26_INBUFF_OVFL_ERROR_SHIFT 26
-#define BCHP_XPT_FE_PARSERS_INBUFF_OVFL_ERROR_INTR_STATUS0_REG_PARSER26_INBUFF_OVFL_ERROR_DEFAULT 0x00000000
-
-/* XPT_FE :: PARSERS_INBUFF_OVFL_ERROR_INTR_STATUS0_REG :: PARSER25_INBUFF_OVFL_ERROR [25:25] */
-#define BCHP_XPT_FE_PARSERS_INBUFF_OVFL_ERROR_INTR_STATUS0_REG_PARSER25_INBUFF_OVFL_ERROR_MASK 0x02000000
-#define BCHP_XPT_FE_PARSERS_INBUFF_OVFL_ERROR_INTR_STATUS0_REG_PARSER25_INBUFF_OVFL_ERROR_SHIFT 25
-#define BCHP_XPT_FE_PARSERS_INBUFF_OVFL_ERROR_INTR_STATUS0_REG_PARSER25_INBUFF_OVFL_ERROR_DEFAULT 0x00000000
-
-/* XPT_FE :: PARSERS_INBUFF_OVFL_ERROR_INTR_STATUS0_REG :: PARSER24_INBUFF_OVFL_ERROR [24:24] */
-#define BCHP_XPT_FE_PARSERS_INBUFF_OVFL_ERROR_INTR_STATUS0_REG_PARSER24_INBUFF_OVFL_ERROR_MASK 0x01000000
-#define BCHP_XPT_FE_PARSERS_INBUFF_OVFL_ERROR_INTR_STATUS0_REG_PARSER24_INBUFF_OVFL_ERROR_SHIFT 24
-#define BCHP_XPT_FE_PARSERS_INBUFF_OVFL_ERROR_INTR_STATUS0_REG_PARSER24_INBUFF_OVFL_ERROR_DEFAULT 0x00000000
-
-/* XPT_FE :: PARSERS_INBUFF_OVFL_ERROR_INTR_STATUS0_REG :: PARSER23_INBUFF_OVFL_ERROR [23:23] */
-#define BCHP_XPT_FE_PARSERS_INBUFF_OVFL_ERROR_INTR_STATUS0_REG_PARSER23_INBUFF_OVFL_ERROR_MASK 0x00800000
-#define BCHP_XPT_FE_PARSERS_INBUFF_OVFL_ERROR_INTR_STATUS0_REG_PARSER23_INBUFF_OVFL_ERROR_SHIFT 23
-#define BCHP_XPT_FE_PARSERS_INBUFF_OVFL_ERROR_INTR_STATUS0_REG_PARSER23_INBUFF_OVFL_ERROR_DEFAULT 0x00000000
-
-/* XPT_FE :: PARSERS_INBUFF_OVFL_ERROR_INTR_STATUS0_REG :: PARSER22_INBUFF_OVFL_ERROR [22:22] */
-#define BCHP_XPT_FE_PARSERS_INBUFF_OVFL_ERROR_INTR_STATUS0_REG_PARSER22_INBUFF_OVFL_ERROR_MASK 0x00400000
-#define BCHP_XPT_FE_PARSERS_INBUFF_OVFL_ERROR_INTR_STATUS0_REG_PARSER22_INBUFF_OVFL_ERROR_SHIFT 22
-#define BCHP_XPT_FE_PARSERS_INBUFF_OVFL_ERROR_INTR_STATUS0_REG_PARSER22_INBUFF_OVFL_ERROR_DEFAULT 0x00000000
-
-/* XPT_FE :: PARSERS_INBUFF_OVFL_ERROR_INTR_STATUS0_REG :: PARSER21_INBUFF_OVFL_ERROR [21:21] */
-#define BCHP_XPT_FE_PARSERS_INBUFF_OVFL_ERROR_INTR_STATUS0_REG_PARSER21_INBUFF_OVFL_ERROR_MASK 0x00200000
-#define BCHP_XPT_FE_PARSERS_INBUFF_OVFL_ERROR_INTR_STATUS0_REG_PARSER21_INBUFF_OVFL_ERROR_SHIFT 21
-#define BCHP_XPT_FE_PARSERS_INBUFF_OVFL_ERROR_INTR_STATUS0_REG_PARSER21_INBUFF_OVFL_ERROR_DEFAULT 0x00000000
-
-/* XPT_FE :: PARSERS_INBUFF_OVFL_ERROR_INTR_STATUS0_REG :: PARSER20_INBUFF_OVFL_ERROR [20:20] */
-#define BCHP_XPT_FE_PARSERS_INBUFF_OVFL_ERROR_INTR_STATUS0_REG_PARSER20_INBUFF_OVFL_ERROR_MASK 0x00100000
-#define BCHP_XPT_FE_PARSERS_INBUFF_OVFL_ERROR_INTR_STATUS0_REG_PARSER20_INBUFF_OVFL_ERROR_SHIFT 20
-#define BCHP_XPT_FE_PARSERS_INBUFF_OVFL_ERROR_INTR_STATUS0_REG_PARSER20_INBUFF_OVFL_ERROR_DEFAULT 0x00000000
-
-/* XPT_FE :: PARSERS_INBUFF_OVFL_ERROR_INTR_STATUS0_REG :: PARSER19_INBUFF_OVFL_ERROR [19:19] */
-#define BCHP_XPT_FE_PARSERS_INBUFF_OVFL_ERROR_INTR_STATUS0_REG_PARSER19_INBUFF_OVFL_ERROR_MASK 0x00080000
-#define BCHP_XPT_FE_PARSERS_INBUFF_OVFL_ERROR_INTR_STATUS0_REG_PARSER19_INBUFF_OVFL_ERROR_SHIFT 19
-#define BCHP_XPT_FE_PARSERS_INBUFF_OVFL_ERROR_INTR_STATUS0_REG_PARSER19_INBUFF_OVFL_ERROR_DEFAULT 0x00000000
-
-/* XPT_FE :: PARSERS_INBUFF_OVFL_ERROR_INTR_STATUS0_REG :: PARSER18_INBUFF_OVFL_ERROR [18:18] */
-#define BCHP_XPT_FE_PARSERS_INBUFF_OVFL_ERROR_INTR_STATUS0_REG_PARSER18_INBUFF_OVFL_ERROR_MASK 0x00040000
-#define BCHP_XPT_FE_PARSERS_INBUFF_OVFL_ERROR_INTR_STATUS0_REG_PARSER18_INBUFF_OVFL_ERROR_SHIFT 18
-#define BCHP_XPT_FE_PARSERS_INBUFF_OVFL_ERROR_INTR_STATUS0_REG_PARSER18_INBUFF_OVFL_ERROR_DEFAULT 0x00000000
-
-/* XPT_FE :: PARSERS_INBUFF_OVFL_ERROR_INTR_STATUS0_REG :: PARSER17_INBUFF_OVFL_ERROR [17:17] */
-#define BCHP_XPT_FE_PARSERS_INBUFF_OVFL_ERROR_INTR_STATUS0_REG_PARSER17_INBUFF_OVFL_ERROR_MASK 0x00020000
-#define BCHP_XPT_FE_PARSERS_INBUFF_OVFL_ERROR_INTR_STATUS0_REG_PARSER17_INBUFF_OVFL_ERROR_SHIFT 17
-#define BCHP_XPT_FE_PARSERS_INBUFF_OVFL_ERROR_INTR_STATUS0_REG_PARSER17_INBUFF_OVFL_ERROR_DEFAULT 0x00000000
-
-/* XPT_FE :: PARSERS_INBUFF_OVFL_ERROR_INTR_STATUS0_REG :: PARSER16_INBUFF_OVFL_ERROR [16:16] */
-#define BCHP_XPT_FE_PARSERS_INBUFF_OVFL_ERROR_INTR_STATUS0_REG_PARSER16_INBUFF_OVFL_ERROR_MASK 0x00010000
-#define BCHP_XPT_FE_PARSERS_INBUFF_OVFL_ERROR_INTR_STATUS0_REG_PARSER16_INBUFF_OVFL_ERROR_SHIFT 16
-#define BCHP_XPT_FE_PARSERS_INBUFF_OVFL_ERROR_INTR_STATUS0_REG_PARSER16_INBUFF_OVFL_ERROR_DEFAULT 0x00000000
-
-/* XPT_FE :: PARSERS_INBUFF_OVFL_ERROR_INTR_STATUS0_REG :: PARSER15_INBUFF_OVFL_ERROR [15:15] */
-#define BCHP_XPT_FE_PARSERS_INBUFF_OVFL_ERROR_INTR_STATUS0_REG_PARSER15_INBUFF_OVFL_ERROR_MASK 0x00008000
-#define BCHP_XPT_FE_PARSERS_INBUFF_OVFL_ERROR_INTR_STATUS0_REG_PARSER15_INBUFF_OVFL_ERROR_SHIFT 15
-#define BCHP_XPT_FE_PARSERS_INBUFF_OVFL_ERROR_INTR_STATUS0_REG_PARSER15_INBUFF_OVFL_ERROR_DEFAULT 0x00000000
-
-/* XPT_FE :: PARSERS_INBUFF_OVFL_ERROR_INTR_STATUS0_REG :: PARSER14_INBUFF_OVFL_ERROR [14:14] */
-#define BCHP_XPT_FE_PARSERS_INBUFF_OVFL_ERROR_INTR_STATUS0_REG_PARSER14_INBUFF_OVFL_ERROR_MASK 0x00004000
-#define BCHP_XPT_FE_PARSERS_INBUFF_OVFL_ERROR_INTR_STATUS0_REG_PARSER14_INBUFF_OVFL_ERROR_SHIFT 14
-#define BCHP_XPT_FE_PARSERS_INBUFF_OVFL_ERROR_INTR_STATUS0_REG_PARSER14_INBUFF_OVFL_ERROR_DEFAULT 0x00000000
-
-/* XPT_FE :: PARSERS_INBUFF_OVFL_ERROR_INTR_STATUS0_REG :: PARSER13_INBUFF_OVFL_ERROR [13:13] */
-#define BCHP_XPT_FE_PARSERS_INBUFF_OVFL_ERROR_INTR_STATUS0_REG_PARSER13_INBUFF_OVFL_ERROR_MASK 0x00002000
-#define BCHP_XPT_FE_PARSERS_INBUFF_OVFL_ERROR_INTR_STATUS0_REG_PARSER13_INBUFF_OVFL_ERROR_SHIFT 13
-#define BCHP_XPT_FE_PARSERS_INBUFF_OVFL_ERROR_INTR_STATUS0_REG_PARSER13_INBUFF_OVFL_ERROR_DEFAULT 0x00000000
-
-/* XPT_FE :: PARSERS_INBUFF_OVFL_ERROR_INTR_STATUS0_REG :: PARSER12_INBUFF_OVFL_ERROR [12:12] */
-#define BCHP_XPT_FE_PARSERS_INBUFF_OVFL_ERROR_INTR_STATUS0_REG_PARSER12_INBUFF_OVFL_ERROR_MASK 0x00001000
-#define BCHP_XPT_FE_PARSERS_INBUFF_OVFL_ERROR_INTR_STATUS0_REG_PARSER12_INBUFF_OVFL_ERROR_SHIFT 12
-#define BCHP_XPT_FE_PARSERS_INBUFF_OVFL_ERROR_INTR_STATUS0_REG_PARSER12_INBUFF_OVFL_ERROR_DEFAULT 0x00000000
-
-/* XPT_FE :: PARSERS_INBUFF_OVFL_ERROR_INTR_STATUS0_REG :: PARSER11_INBUFF_OVFL_ERROR [11:11] */
-#define BCHP_XPT_FE_PARSERS_INBUFF_OVFL_ERROR_INTR_STATUS0_REG_PARSER11_INBUFF_OVFL_ERROR_MASK 0x00000800
-#define BCHP_XPT_FE_PARSERS_INBUFF_OVFL_ERROR_INTR_STATUS0_REG_PARSER11_INBUFF_OVFL_ERROR_SHIFT 11
-#define BCHP_XPT_FE_PARSERS_INBUFF_OVFL_ERROR_INTR_STATUS0_REG_PARSER11_INBUFF_OVFL_ERROR_DEFAULT 0x00000000
-
-/* XPT_FE :: PARSERS_INBUFF_OVFL_ERROR_INTR_STATUS0_REG :: PARSER10_INBUFF_OVFL_ERROR [10:10] */
-#define BCHP_XPT_FE_PARSERS_INBUFF_OVFL_ERROR_INTR_STATUS0_REG_PARSER10_INBUFF_OVFL_ERROR_MASK 0x00000400
-#define BCHP_XPT_FE_PARSERS_INBUFF_OVFL_ERROR_INTR_STATUS0_REG_PARSER10_INBUFF_OVFL_ERROR_SHIFT 10
-#define BCHP_XPT_FE_PARSERS_INBUFF_OVFL_ERROR_INTR_STATUS0_REG_PARSER10_INBUFF_OVFL_ERROR_DEFAULT 0x00000000
-
-/* XPT_FE :: PARSERS_INBUFF_OVFL_ERROR_INTR_STATUS0_REG :: PARSER9_INBUFF_OVFL_ERROR [09:09] */
-#define BCHP_XPT_FE_PARSERS_INBUFF_OVFL_ERROR_INTR_STATUS0_REG_PARSER9_INBUFF_OVFL_ERROR_MASK 0x00000200
-#define BCHP_XPT_FE_PARSERS_INBUFF_OVFL_ERROR_INTR_STATUS0_REG_PARSER9_INBUFF_OVFL_ERROR_SHIFT 9
-#define BCHP_XPT_FE_PARSERS_INBUFF_OVFL_ERROR_INTR_STATUS0_REG_PARSER9_INBUFF_OVFL_ERROR_DEFAULT 0x00000000
-
-/* XPT_FE :: PARSERS_INBUFF_OVFL_ERROR_INTR_STATUS0_REG :: PARSER8_INBUFF_OVFL_ERROR [08:08] */
-#define BCHP_XPT_FE_PARSERS_INBUFF_OVFL_ERROR_INTR_STATUS0_REG_PARSER8_INBUFF_OVFL_ERROR_MASK 0x00000100
-#define BCHP_XPT_FE_PARSERS_INBUFF_OVFL_ERROR_INTR_STATUS0_REG_PARSER8_INBUFF_OVFL_ERROR_SHIFT 8
-#define BCHP_XPT_FE_PARSERS_INBUFF_OVFL_ERROR_INTR_STATUS0_REG_PARSER8_INBUFF_OVFL_ERROR_DEFAULT 0x00000000
-
-/* XPT_FE :: PARSERS_INBUFF_OVFL_ERROR_INTR_STATUS0_REG :: PARSER7_INBUFF_OVFL_ERROR [07:07] */
-#define BCHP_XPT_FE_PARSERS_INBUFF_OVFL_ERROR_INTR_STATUS0_REG_PARSER7_INBUFF_OVFL_ERROR_MASK 0x00000080
-#define BCHP_XPT_FE_PARSERS_INBUFF_OVFL_ERROR_INTR_STATUS0_REG_PARSER7_INBUFF_OVFL_ERROR_SHIFT 7
-#define BCHP_XPT_FE_PARSERS_INBUFF_OVFL_ERROR_INTR_STATUS0_REG_PARSER7_INBUFF_OVFL_ERROR_DEFAULT 0x00000000
-
-/* XPT_FE :: PARSERS_INBUFF_OVFL_ERROR_INTR_STATUS0_REG :: PARSER6_INBUFF_OVFL_ERROR [06:06] */
-#define BCHP_XPT_FE_PARSERS_INBUFF_OVFL_ERROR_INTR_STATUS0_REG_PARSER6_INBUFF_OVFL_ERROR_MASK 0x00000040
-#define BCHP_XPT_FE_PARSERS_INBUFF_OVFL_ERROR_INTR_STATUS0_REG_PARSER6_INBUFF_OVFL_ERROR_SHIFT 6
-#define BCHP_XPT_FE_PARSERS_INBUFF_OVFL_ERROR_INTR_STATUS0_REG_PARSER6_INBUFF_OVFL_ERROR_DEFAULT 0x00000000
-
-/* XPT_FE :: PARSERS_INBUFF_OVFL_ERROR_INTR_STATUS0_REG :: PARSER5_INBUFF_OVFL_ERROR [05:05] */
-#define BCHP_XPT_FE_PARSERS_INBUFF_OVFL_ERROR_INTR_STATUS0_REG_PARSER5_INBUFF_OVFL_ERROR_MASK 0x00000020
-#define BCHP_XPT_FE_PARSERS_INBUFF_OVFL_ERROR_INTR_STATUS0_REG_PARSER5_INBUFF_OVFL_ERROR_SHIFT 5
-#define BCHP_XPT_FE_PARSERS_INBUFF_OVFL_ERROR_INTR_STATUS0_REG_PARSER5_INBUFF_OVFL_ERROR_DEFAULT 0x00000000
-
-/* XPT_FE :: PARSERS_INBUFF_OVFL_ERROR_INTR_STATUS0_REG :: PARSER4_INBUFF_OVFL_ERROR [04:04] */
-#define BCHP_XPT_FE_PARSERS_INBUFF_OVFL_ERROR_INTR_STATUS0_REG_PARSER4_INBUFF_OVFL_ERROR_MASK 0x00000010
-#define BCHP_XPT_FE_PARSERS_INBUFF_OVFL_ERROR_INTR_STATUS0_REG_PARSER4_INBUFF_OVFL_ERROR_SHIFT 4
-#define BCHP_XPT_FE_PARSERS_INBUFF_OVFL_ERROR_INTR_STATUS0_REG_PARSER4_INBUFF_OVFL_ERROR_DEFAULT 0x00000000
-
-/* XPT_FE :: PARSERS_INBUFF_OVFL_ERROR_INTR_STATUS0_REG :: PARSER3_INBUFF_OVFL_ERROR [03:03] */
-#define BCHP_XPT_FE_PARSERS_INBUFF_OVFL_ERROR_INTR_STATUS0_REG_PARSER3_INBUFF_OVFL_ERROR_MASK 0x00000008
-#define BCHP_XPT_FE_PARSERS_INBUFF_OVFL_ERROR_INTR_STATUS0_REG_PARSER3_INBUFF_OVFL_ERROR_SHIFT 3
-#define BCHP_XPT_FE_PARSERS_INBUFF_OVFL_ERROR_INTR_STATUS0_REG_PARSER3_INBUFF_OVFL_ERROR_DEFAULT 0x00000000
-
-/* XPT_FE :: PARSERS_INBUFF_OVFL_ERROR_INTR_STATUS0_REG :: PARSER2_INBUFF_OVFL_ERROR [02:02] */
-#define BCHP_XPT_FE_PARSERS_INBUFF_OVFL_ERROR_INTR_STATUS0_REG_PARSER2_INBUFF_OVFL_ERROR_MASK 0x00000004
-#define BCHP_XPT_FE_PARSERS_INBUFF_OVFL_ERROR_INTR_STATUS0_REG_PARSER2_INBUFF_OVFL_ERROR_SHIFT 2
-#define BCHP_XPT_FE_PARSERS_INBUFF_OVFL_ERROR_INTR_STATUS0_REG_PARSER2_INBUFF_OVFL_ERROR_DEFAULT 0x00000000
-
-/* XPT_FE :: PARSERS_INBUFF_OVFL_ERROR_INTR_STATUS0_REG :: PARSER1_INBUFF_OVFL_ERROR [01:01] */
-#define BCHP_XPT_FE_PARSERS_INBUFF_OVFL_ERROR_INTR_STATUS0_REG_PARSER1_INBUFF_OVFL_ERROR_MASK 0x00000002
-#define BCHP_XPT_FE_PARSERS_INBUFF_OVFL_ERROR_INTR_STATUS0_REG_PARSER1_INBUFF_OVFL_ERROR_SHIFT 1
-#define BCHP_XPT_FE_PARSERS_INBUFF_OVFL_ERROR_INTR_STATUS0_REG_PARSER1_INBUFF_OVFL_ERROR_DEFAULT 0x00000000
-
-/* XPT_FE :: PARSERS_INBUFF_OVFL_ERROR_INTR_STATUS0_REG :: PARSER0_INBUFF_OVFL_ERROR [00:00] */
-#define BCHP_XPT_FE_PARSERS_INBUFF_OVFL_ERROR_INTR_STATUS0_REG_PARSER0_INBUFF_OVFL_ERROR_MASK 0x00000001
-#define BCHP_XPT_FE_PARSERS_INBUFF_OVFL_ERROR_INTR_STATUS0_REG_PARSER0_INBUFF_OVFL_ERROR_SHIFT 0
-#define BCHP_XPT_FE_PARSERS_INBUFF_OVFL_ERROR_INTR_STATUS0_REG_PARSER0_INBUFF_OVFL_ERROR_DEFAULT 0x00000000
-
-/***************************************************************************
- *PARSERS_TSMF_FRAME_ERROR_INTR_STATUS0_REG_EN - Interrupt Status Enable Register
- ***************************************************************************/
-/* XPT_FE :: PARSERS_TSMF_FRAME_ERROR_INTR_STATUS0_REG_EN :: INTR_STATUS0_REG_EN [31:00] */
-#define BCHP_XPT_FE_PARSERS_TSMF_FRAME_ERROR_INTR_STATUS0_REG_EN_INTR_STATUS0_REG_EN_MASK 0xffffffff
-#define BCHP_XPT_FE_PARSERS_TSMF_FRAME_ERROR_INTR_STATUS0_REG_EN_INTR_STATUS0_REG_EN_SHIFT 0
-#define BCHP_XPT_FE_PARSERS_TSMF_FRAME_ERROR_INTR_STATUS0_REG_EN_INTR_STATUS0_REG_EN_DEFAULT 0x00000000
-
-/***************************************************************************
- *PARSERS_TSMF_SYNC_ERROR_INTR_STATUS0_REG_EN - Interrupt Status Enable Register
- ***************************************************************************/
-/* XPT_FE :: PARSERS_TSMF_SYNC_ERROR_INTR_STATUS0_REG_EN :: INTR_STATUS0_REG_EN [31:00] */
-#define BCHP_XPT_FE_PARSERS_TSMF_SYNC_ERROR_INTR_STATUS0_REG_EN_INTR_STATUS0_REG_EN_MASK 0xffffffff
-#define BCHP_XPT_FE_PARSERS_TSMF_SYNC_ERROR_INTR_STATUS0_REG_EN_INTR_STATUS0_REG_EN_SHIFT 0
-#define BCHP_XPT_FE_PARSERS_TSMF_SYNC_ERROR_INTR_STATUS0_REG_EN_INTR_STATUS0_REG_EN_DEFAULT 0x00000000
-
-/***************************************************************************
- *PARSERS_INBUFF_OVFL_ERROR_INTR_STATUS0_REG_EN - Interrupt Status Enable Register
- ***************************************************************************/
-/* XPT_FE :: PARSERS_INBUFF_OVFL_ERROR_INTR_STATUS0_REG_EN :: INTR_STATUS0_REG_EN [31:00] */
-#define BCHP_XPT_FE_PARSERS_INBUFF_OVFL_ERROR_INTR_STATUS0_REG_EN_INTR_STATUS0_REG_EN_MASK 0xffffffff
-#define BCHP_XPT_FE_PARSERS_INBUFF_OVFL_ERROR_INTR_STATUS0_REG_EN_INTR_STATUS0_REG_EN_SHIFT 0
-#define BCHP_XPT_FE_PARSERS_INBUFF_OVFL_ERROR_INTR_STATUS0_REG_EN_INTR_STATUS0_REG_EN_DEFAULT 0x00000000
-
-/***************************************************************************
- *ATS_COUNTER_CTRL - FE_ATS_COUNTER_CTRL
- ***************************************************************************/
-/* XPT_FE :: ATS_COUNTER_CTRL :: reserved0 [31:25] */
-#define BCHP_XPT_FE_ATS_COUNTER_CTRL_reserved0_MASK 0xfe000000
-#define BCHP_XPT_FE_ATS_COUNTER_CTRL_reserved0_SHIFT 25
-
-/* XPT_FE :: ATS_COUNTER_CTRL :: EXT_RESET_ENABLE [24:24] */
-#define BCHP_XPT_FE_ATS_COUNTER_CTRL_EXT_RESET_ENABLE_MASK 0x01000000
-#define BCHP_XPT_FE_ATS_COUNTER_CTRL_EXT_RESET_ENABLE_SHIFT 24
-#define BCHP_XPT_FE_ATS_COUNTER_CTRL_EXT_RESET_ENABLE_DEFAULT 0x00000000
-
-/* XPT_FE :: ATS_COUNTER_CTRL :: COUNT_RESET [23:23] */
-#define BCHP_XPT_FE_ATS_COUNTER_CTRL_COUNT_RESET_MASK 0x00800000
-#define BCHP_XPT_FE_ATS_COUNTER_CTRL_COUNT_RESET_SHIFT 23
-#define BCHP_XPT_FE_ATS_COUNTER_CTRL_COUNT_RESET_DEFAULT 0x00000000
-
-/* XPT_FE :: ATS_COUNTER_CTRL :: INC_MUX_SEL [22:22] */
-#define BCHP_XPT_FE_ATS_COUNTER_CTRL_INC_MUX_SEL_MASK 0x00400000
-#define BCHP_XPT_FE_ATS_COUNTER_CTRL_INC_MUX_SEL_SHIFT 22
-#define BCHP_XPT_FE_ATS_COUNTER_CTRL_INC_MUX_SEL_DEFAULT 0x00000000
-
-/* XPT_FE :: ATS_COUNTER_CTRL :: SKIP_REPEAT_MODE [21:21] */
-#define BCHP_XPT_FE_ATS_COUNTER_CTRL_SKIP_REPEAT_MODE_MASK 0x00200000
-#define BCHP_XPT_FE_ATS_COUNTER_CTRL_SKIP_REPEAT_MODE_SHIFT 21
-#define BCHP_XPT_FE_ATS_COUNTER_CTRL_SKIP_REPEAT_MODE_DEFAULT 0x00000000
-
-/* XPT_FE :: ATS_COUNTER_CTRL :: SKIP_REPEAT_EN [20:20] */
-#define BCHP_XPT_FE_ATS_COUNTER_CTRL_SKIP_REPEAT_EN_MASK 0x00100000
-#define BCHP_XPT_FE_ATS_COUNTER_CTRL_SKIP_REPEAT_EN_SHIFT 20
-#define BCHP_XPT_FE_ATS_COUNTER_CTRL_SKIP_REPEAT_EN_DEFAULT 0x00000000
-
-/* XPT_FE :: ATS_COUNTER_CTRL :: SKIP_REPEAT_COUNT [19:00] */
-#define BCHP_XPT_FE_ATS_COUNTER_CTRL_SKIP_REPEAT_COUNT_MASK 0x000fffff
-#define BCHP_XPT_FE_ATS_COUNTER_CTRL_SKIP_REPEAT_COUNT_SHIFT 0
-#define BCHP_XPT_FE_ATS_COUNTER_CTRL_SKIP_REPEAT_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *ATS_TS_MOD300 - FE_ATS_TS_MOD300
- ***************************************************************************/
-/* XPT_FE :: ATS_TS_MOD300 :: TS_MOD300_UPPER [31:09] */
-#define BCHP_XPT_FE_ATS_TS_MOD300_TS_MOD300_UPPER_MASK 0xfffffe00
-#define BCHP_XPT_FE_ATS_TS_MOD300_TS_MOD300_UPPER_SHIFT 9
-#define BCHP_XPT_FE_ATS_TS_MOD300_TS_MOD300_UPPER_DEFAULT 0x00000000
-
-/* XPT_FE :: ATS_TS_MOD300 :: TS_MOD300_LOWER [08:00] */
-#define BCHP_XPT_FE_ATS_TS_MOD300_TS_MOD300_LOWER_MASK 0x000001ff
-#define BCHP_XPT_FE_ATS_TS_MOD300_TS_MOD300_LOWER_SHIFT 0
-#define BCHP_XPT_FE_ATS_TS_MOD300_TS_MOD300_LOWER_DEFAULT 0x00000000
-
-/***************************************************************************
- *ATS_TS_BINARY - FE_ATS_TS_BINARY
- ***************************************************************************/
-/* XPT_FE :: ATS_TS_BINARY :: TS_BINARY_COUNTER [31:00] */
-#define BCHP_XPT_FE_ATS_TS_BINARY_TS_BINARY_COUNTER_MASK 0xffffffff
-#define BCHP_XPT_FE_ATS_TS_BINARY_TS_BINARY_COUNTER_SHIFT 0
-#define BCHP_XPT_FE_ATS_TS_BINARY_TS_BINARY_COUNTER_DEFAULT 0x00000000
-
-/***************************************************************************
- *TV_STATUS_0 - TV Status_0
- ***************************************************************************/
-/* XPT_FE :: TV_STATUS_0 :: INPUT3_CRC [31:24] */
-#define BCHP_XPT_FE_TV_STATUS_0_INPUT3_CRC_MASK 0xff000000
-#define BCHP_XPT_FE_TV_STATUS_0_INPUT3_CRC_SHIFT 24
-#define BCHP_XPT_FE_TV_STATUS_0_INPUT3_CRC_DEFAULT 0x00000000
-
-/* XPT_FE :: TV_STATUS_0 :: INPUT2_CRC [23:16] */
-#define BCHP_XPT_FE_TV_STATUS_0_INPUT2_CRC_MASK 0x00ff0000
-#define BCHP_XPT_FE_TV_STATUS_0_INPUT2_CRC_SHIFT 16
-#define BCHP_XPT_FE_TV_STATUS_0_INPUT2_CRC_DEFAULT 0x00000000
-
-/* XPT_FE :: TV_STATUS_0 :: INPUT1_CRC [15:08] */
-#define BCHP_XPT_FE_TV_STATUS_0_INPUT1_CRC_MASK 0x0000ff00
-#define BCHP_XPT_FE_TV_STATUS_0_INPUT1_CRC_SHIFT 8
-#define BCHP_XPT_FE_TV_STATUS_0_INPUT1_CRC_DEFAULT 0x00000000
-
-/* XPT_FE :: TV_STATUS_0 :: INPUT0_CRC [07:00] */
-#define BCHP_XPT_FE_TV_STATUS_0_INPUT0_CRC_MASK 0x000000ff
-#define BCHP_XPT_FE_TV_STATUS_0_INPUT0_CRC_SHIFT 0
-#define BCHP_XPT_FE_TV_STATUS_0_INPUT0_CRC_DEFAULT 0x00000000
-
-/***************************************************************************
- *TV_STATUS_1 - TV Status_1
- ***************************************************************************/
-/* XPT_FE :: TV_STATUS_1 :: INPUT7_CRC [31:24] */
-#define BCHP_XPT_FE_TV_STATUS_1_INPUT7_CRC_MASK 0xff000000
-#define BCHP_XPT_FE_TV_STATUS_1_INPUT7_CRC_SHIFT 24
-#define BCHP_XPT_FE_TV_STATUS_1_INPUT7_CRC_DEFAULT 0x00000000
-
-/* XPT_FE :: TV_STATUS_1 :: INPUT6_CRC [23:16] */
-#define BCHP_XPT_FE_TV_STATUS_1_INPUT6_CRC_MASK 0x00ff0000
-#define BCHP_XPT_FE_TV_STATUS_1_INPUT6_CRC_SHIFT 16
-#define BCHP_XPT_FE_TV_STATUS_1_INPUT6_CRC_DEFAULT 0x00000000
-
-/* XPT_FE :: TV_STATUS_1 :: INPUT5_CRC [15:08] */
-#define BCHP_XPT_FE_TV_STATUS_1_INPUT5_CRC_MASK 0x0000ff00
-#define BCHP_XPT_FE_TV_STATUS_1_INPUT5_CRC_SHIFT 8
-#define BCHP_XPT_FE_TV_STATUS_1_INPUT5_CRC_DEFAULT 0x00000000
-
-/* XPT_FE :: TV_STATUS_1 :: INPUT4_CRC [07:00] */
-#define BCHP_XPT_FE_TV_STATUS_1_INPUT4_CRC_MASK 0x000000ff
-#define BCHP_XPT_FE_TV_STATUS_1_INPUT4_CRC_SHIFT 0
-#define BCHP_XPT_FE_TV_STATUS_1_INPUT4_CRC_DEFAULT 0x00000000
-
-/***************************************************************************
- *TV_STATUS_2 - TV Status_2
- ***************************************************************************/
-/* XPT_FE :: TV_STATUS_2 :: INPUT11_CRC [31:24] */
-#define BCHP_XPT_FE_TV_STATUS_2_INPUT11_CRC_MASK 0xff000000
-#define BCHP_XPT_FE_TV_STATUS_2_INPUT11_CRC_SHIFT 24
-#define BCHP_XPT_FE_TV_STATUS_2_INPUT11_CRC_DEFAULT 0x00000000
-
-/* XPT_FE :: TV_STATUS_2 :: INPUT10_CRC [23:16] */
-#define BCHP_XPT_FE_TV_STATUS_2_INPUT10_CRC_MASK 0x00ff0000
-#define BCHP_XPT_FE_TV_STATUS_2_INPUT10_CRC_SHIFT 16
-#define BCHP_XPT_FE_TV_STATUS_2_INPUT10_CRC_DEFAULT 0x00000000
-
-/* XPT_FE :: TV_STATUS_2 :: INPUT9_CRC [15:08] */
-#define BCHP_XPT_FE_TV_STATUS_2_INPUT9_CRC_MASK 0x0000ff00
-#define BCHP_XPT_FE_TV_STATUS_2_INPUT9_CRC_SHIFT 8
-#define BCHP_XPT_FE_TV_STATUS_2_INPUT9_CRC_DEFAULT 0x00000000
-
-/* XPT_FE :: TV_STATUS_2 :: INPUT8_CRC [07:00] */
-#define BCHP_XPT_FE_TV_STATUS_2_INPUT8_CRC_MASK 0x000000ff
-#define BCHP_XPT_FE_TV_STATUS_2_INPUT8_CRC_SHIFT 0
-#define BCHP_XPT_FE_TV_STATUS_2_INPUT8_CRC_DEFAULT 0x00000000
-
-/***************************************************************************
- *TV_STATUS_3 - TV Status_3
- ***************************************************************************/
-/* XPT_FE :: TV_STATUS_3 :: INPUT15_CRC [31:24] */
-#define BCHP_XPT_FE_TV_STATUS_3_INPUT15_CRC_MASK 0xff000000
-#define BCHP_XPT_FE_TV_STATUS_3_INPUT15_CRC_SHIFT 24
-#define BCHP_XPT_FE_TV_STATUS_3_INPUT15_CRC_DEFAULT 0x00000000
-
-/* XPT_FE :: TV_STATUS_3 :: INPUT14_CRC [23:16] */
-#define BCHP_XPT_FE_TV_STATUS_3_INPUT14_CRC_MASK 0x00ff0000
-#define BCHP_XPT_FE_TV_STATUS_3_INPUT14_CRC_SHIFT 16
-#define BCHP_XPT_FE_TV_STATUS_3_INPUT14_CRC_DEFAULT 0x00000000
-
-/* XPT_FE :: TV_STATUS_3 :: INPUT13_CRC [15:08] */
-#define BCHP_XPT_FE_TV_STATUS_3_INPUT13_CRC_MASK 0x0000ff00
-#define BCHP_XPT_FE_TV_STATUS_3_INPUT13_CRC_SHIFT 8
-#define BCHP_XPT_FE_TV_STATUS_3_INPUT13_CRC_DEFAULT 0x00000000
-
-/* XPT_FE :: TV_STATUS_3 :: INPUT12_CRC [07:00] */
-#define BCHP_XPT_FE_TV_STATUS_3_INPUT12_CRC_MASK 0x000000ff
-#define BCHP_XPT_FE_TV_STATUS_3_INPUT12_CRC_SHIFT 0
-#define BCHP_XPT_FE_TV_STATUS_3_INPUT12_CRC_DEFAULT 0x00000000
-
-/***************************************************************************
- *TV_STATUS_4 - TV Status_4
- ***************************************************************************/
-/* XPT_FE :: TV_STATUS_4 :: MTSIF_RX3_CRC [31:24] */
-#define BCHP_XPT_FE_TV_STATUS_4_MTSIF_RX3_CRC_MASK 0xff000000
-#define BCHP_XPT_FE_TV_STATUS_4_MTSIF_RX3_CRC_SHIFT 24
-#define BCHP_XPT_FE_TV_STATUS_4_MTSIF_RX3_CRC_DEFAULT 0x00000000
-
-/* XPT_FE :: TV_STATUS_4 :: MTSIF_RX2_CRC [23:16] */
-#define BCHP_XPT_FE_TV_STATUS_4_MTSIF_RX2_CRC_MASK 0x00ff0000
-#define BCHP_XPT_FE_TV_STATUS_4_MTSIF_RX2_CRC_SHIFT 16
-#define BCHP_XPT_FE_TV_STATUS_4_MTSIF_RX2_CRC_DEFAULT 0x00000000
-
-/* XPT_FE :: TV_STATUS_4 :: MTSIF_RX1_CRC [15:08] */
-#define BCHP_XPT_FE_TV_STATUS_4_MTSIF_RX1_CRC_MASK 0x0000ff00
-#define BCHP_XPT_FE_TV_STATUS_4_MTSIF_RX1_CRC_SHIFT 8
-#define BCHP_XPT_FE_TV_STATUS_4_MTSIF_RX1_CRC_DEFAULT 0x00000000
-
-/* XPT_FE :: TV_STATUS_4 :: MTSIF_RX0_CRC [07:00] */
-#define BCHP_XPT_FE_TV_STATUS_4_MTSIF_RX0_CRC_MASK 0x000000ff
-#define BCHP_XPT_FE_TV_STATUS_4_MTSIF_RX0_CRC_SHIFT 0
-#define BCHP_XPT_FE_TV_STATUS_4_MTSIF_RX0_CRC_DEFAULT 0x00000000
-
-/***************************************************************************
- *IB0_CTRL - Data Transport Input Band 0 Control Register
- ***************************************************************************/
-/* XPT_FE :: IB0_CTRL :: reserved0 [31:24] */
-#define BCHP_XPT_FE_IB0_CTRL_reserved0_MASK 0xff000000
-#define BCHP_XPT_FE_IB0_CTRL_reserved0_SHIFT 24
-
-/* XPT_FE :: IB0_CTRL :: IB_PKT_LENGTH [23:16] */
-#define BCHP_XPT_FE_IB0_CTRL_IB_PKT_LENGTH_MASK 0x00ff0000
-#define BCHP_XPT_FE_IB0_CTRL_IB_PKT_LENGTH_SHIFT 16
-#define BCHP_XPT_FE_IB0_CTRL_IB_PKT_LENGTH_DEFAULT 0x000000bc
-
-/* XPT_FE :: IB0_CTRL :: reserved1 [15:11] */
-#define BCHP_XPT_FE_IB0_CTRL_reserved1_MASK 0x0000f800
-#define BCHP_XPT_FE_IB0_CTRL_reserved1_SHIFT 11
-
-/* XPT_FE :: IB0_CTRL :: IB_PARALLEL_INPUT_SEL [10:10] */
-#define BCHP_XPT_FE_IB0_CTRL_IB_PARALLEL_INPUT_SEL_MASK 0x00000400
-#define BCHP_XPT_FE_IB0_CTRL_IB_PARALLEL_INPUT_SEL_SHIFT 10
-#define BCHP_XPT_FE_IB0_CTRL_IB_PARALLEL_INPUT_SEL_DEFAULT 0x00000000
-
-/* XPT_FE :: IB0_CTRL :: IB_LSB_FIRST [09:09] */
-#define BCHP_XPT_FE_IB0_CTRL_IB_LSB_FIRST_MASK 0x00000200
-#define BCHP_XPT_FE_IB0_CTRL_IB_LSB_FIRST_SHIFT 9
-#define BCHP_XPT_FE_IB0_CTRL_IB_LSB_FIRST_DEFAULT 0x00000000
-
-/* XPT_FE :: IB0_CTRL :: IB_FORCE_VALID [08:08] */
-#define BCHP_XPT_FE_IB0_CTRL_IB_FORCE_VALID_MASK 0x00000100
-#define BCHP_XPT_FE_IB0_CTRL_IB_FORCE_VALID_SHIFT 8
-#define BCHP_XPT_FE_IB0_CTRL_IB_FORCE_VALID_DEFAULT 0x00000000
-
-/* XPT_FE :: IB0_CTRL :: IB_USE_SYNC_AS_VALID [07:07] */
-#define BCHP_XPT_FE_IB0_CTRL_IB_USE_SYNC_AS_VALID_MASK 0x00000080
-#define BCHP_XPT_FE_IB0_CTRL_IB_USE_SYNC_AS_VALID_SHIFT 7
-#define BCHP_XPT_FE_IB0_CTRL_IB_USE_SYNC_AS_VALID_DEFAULT 0x00000000
-
-/* XPT_FE :: IB0_CTRL :: IB_SYNC_DETECT_EN [06:06] */
-#define BCHP_XPT_FE_IB0_CTRL_IB_SYNC_DETECT_EN_MASK 0x00000040
-#define BCHP_XPT_FE_IB0_CTRL_IB_SYNC_DETECT_EN_SHIFT 6
-#define BCHP_XPT_FE_IB0_CTRL_IB_SYNC_DETECT_EN_DEFAULT 0x00000000
-
-/* XPT_FE :: IB0_CTRL :: IB_ERROR_INPUT_EN [05:05] */
-#define BCHP_XPT_FE_IB0_CTRL_IB_ERROR_INPUT_EN_MASK 0x00000020
-#define BCHP_XPT_FE_IB0_CTRL_IB_ERROR_INPUT_EN_SHIFT 5
-#define BCHP_XPT_FE_IB0_CTRL_IB_ERROR_INPUT_EN_DEFAULT 0x00000000
-
-/* XPT_FE :: IB0_CTRL :: IB_ERROR_POL_SEL [04:04] */
-#define BCHP_XPT_FE_IB0_CTRL_IB_ERROR_POL_SEL_MASK 0x00000010
-#define BCHP_XPT_FE_IB0_CTRL_IB_ERROR_POL_SEL_SHIFT 4
-#define BCHP_XPT_FE_IB0_CTRL_IB_ERROR_POL_SEL_DEFAULT 0x00000000
-
-/* XPT_FE :: IB0_CTRL :: IB_VALID_POL_SEL [03:03] */
-#define BCHP_XPT_FE_IB0_CTRL_IB_VALID_POL_SEL_MASK 0x00000008
-#define BCHP_XPT_FE_IB0_CTRL_IB_VALID_POL_SEL_SHIFT 3
-#define BCHP_XPT_FE_IB0_CTRL_IB_VALID_POL_SEL_DEFAULT 0x00000000
-
-/* XPT_FE :: IB0_CTRL :: IB_DATA_POL_SEL [02:02] */
-#define BCHP_XPT_FE_IB0_CTRL_IB_DATA_POL_SEL_MASK 0x00000004
-#define BCHP_XPT_FE_IB0_CTRL_IB_DATA_POL_SEL_SHIFT 2
-#define BCHP_XPT_FE_IB0_CTRL_IB_DATA_POL_SEL_DEFAULT 0x00000000
-
-/* XPT_FE :: IB0_CTRL :: IB_SYNC_POL_SEL [01:01] */
-#define BCHP_XPT_FE_IB0_CTRL_IB_SYNC_POL_SEL_MASK 0x00000002
-#define BCHP_XPT_FE_IB0_CTRL_IB_SYNC_POL_SEL_SHIFT 1
-#define BCHP_XPT_FE_IB0_CTRL_IB_SYNC_POL_SEL_DEFAULT 0x00000000
-
-/* XPT_FE :: IB0_CTRL :: IB_CLOCK_POL_SEL [00:00] */
-#define BCHP_XPT_FE_IB0_CTRL_IB_CLOCK_POL_SEL_MASK 0x00000001
-#define BCHP_XPT_FE_IB0_CTRL_IB_CLOCK_POL_SEL_SHIFT 0
-#define BCHP_XPT_FE_IB0_CTRL_IB_CLOCK_POL_SEL_DEFAULT 0x00000000
-
-/***************************************************************************
- *IB0_SYNC_COUNT - Data Transport Input Band 0 Sync counter Register
- ***************************************************************************/
-/* XPT_FE :: IB0_SYNC_COUNT :: reserved0 [31:08] */
-#define BCHP_XPT_FE_IB0_SYNC_COUNT_reserved0_MASK 0xffffff00
-#define BCHP_XPT_FE_IB0_SYNC_COUNT_reserved0_SHIFT 8
-
-/* XPT_FE :: IB0_SYNC_COUNT :: SYNC_COUNT [07:00] */
-#define BCHP_XPT_FE_IB0_SYNC_COUNT_SYNC_COUNT_MASK 0x000000ff
-#define BCHP_XPT_FE_IB0_SYNC_COUNT_SYNC_COUNT_SHIFT 0
-#define BCHP_XPT_FE_IB0_SYNC_COUNT_SYNC_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *IB1_CTRL - Data Transport Input Band 1 Control Register
- ***************************************************************************/
-/* XPT_FE :: IB1_CTRL :: reserved0 [31:24] */
-#define BCHP_XPT_FE_IB1_CTRL_reserved0_MASK 0xff000000
-#define BCHP_XPT_FE_IB1_CTRL_reserved0_SHIFT 24
-
-/* XPT_FE :: IB1_CTRL :: IB_PKT_LENGTH [23:16] */
-#define BCHP_XPT_FE_IB1_CTRL_IB_PKT_LENGTH_MASK 0x00ff0000
-#define BCHP_XPT_FE_IB1_CTRL_IB_PKT_LENGTH_SHIFT 16
-#define BCHP_XPT_FE_IB1_CTRL_IB_PKT_LENGTH_DEFAULT 0x000000bc
-
-/* XPT_FE :: IB1_CTRL :: reserved1 [15:11] */
-#define BCHP_XPT_FE_IB1_CTRL_reserved1_MASK 0x0000f800
-#define BCHP_XPT_FE_IB1_CTRL_reserved1_SHIFT 11
-
-/* XPT_FE :: IB1_CTRL :: IB_PARALLEL_INPUT_SEL [10:10] */
-#define BCHP_XPT_FE_IB1_CTRL_IB_PARALLEL_INPUT_SEL_MASK 0x00000400
-#define BCHP_XPT_FE_IB1_CTRL_IB_PARALLEL_INPUT_SEL_SHIFT 10
-#define BCHP_XPT_FE_IB1_CTRL_IB_PARALLEL_INPUT_SEL_DEFAULT 0x00000000
-
-/* XPT_FE :: IB1_CTRL :: IB_LSB_FIRST [09:09] */
-#define BCHP_XPT_FE_IB1_CTRL_IB_LSB_FIRST_MASK 0x00000200
-#define BCHP_XPT_FE_IB1_CTRL_IB_LSB_FIRST_SHIFT 9
-#define BCHP_XPT_FE_IB1_CTRL_IB_LSB_FIRST_DEFAULT 0x00000000
-
-/* XPT_FE :: IB1_CTRL :: IB_FORCE_VALID [08:08] */
-#define BCHP_XPT_FE_IB1_CTRL_IB_FORCE_VALID_MASK 0x00000100
-#define BCHP_XPT_FE_IB1_CTRL_IB_FORCE_VALID_SHIFT 8
-#define BCHP_XPT_FE_IB1_CTRL_IB_FORCE_VALID_DEFAULT 0x00000000
-
-/* XPT_FE :: IB1_CTRL :: IB_USE_SYNC_AS_VALID [07:07] */
-#define BCHP_XPT_FE_IB1_CTRL_IB_USE_SYNC_AS_VALID_MASK 0x00000080
-#define BCHP_XPT_FE_IB1_CTRL_IB_USE_SYNC_AS_VALID_SHIFT 7
-#define BCHP_XPT_FE_IB1_CTRL_IB_USE_SYNC_AS_VALID_DEFAULT 0x00000000
-
-/* XPT_FE :: IB1_CTRL :: IB_SYNC_DETECT_EN [06:06] */
-#define BCHP_XPT_FE_IB1_CTRL_IB_SYNC_DETECT_EN_MASK 0x00000040
-#define BCHP_XPT_FE_IB1_CTRL_IB_SYNC_DETECT_EN_SHIFT 6
-#define BCHP_XPT_FE_IB1_CTRL_IB_SYNC_DETECT_EN_DEFAULT 0x00000000
-
-/* XPT_FE :: IB1_CTRL :: IB_ERROR_INPUT_EN [05:05] */
-#define BCHP_XPT_FE_IB1_CTRL_IB_ERROR_INPUT_EN_MASK 0x00000020
-#define BCHP_XPT_FE_IB1_CTRL_IB_ERROR_INPUT_EN_SHIFT 5
-#define BCHP_XPT_FE_IB1_CTRL_IB_ERROR_INPUT_EN_DEFAULT 0x00000000
-
-/* XPT_FE :: IB1_CTRL :: IB_ERROR_POL_SEL [04:04] */
-#define BCHP_XPT_FE_IB1_CTRL_IB_ERROR_POL_SEL_MASK 0x00000010
-#define BCHP_XPT_FE_IB1_CTRL_IB_ERROR_POL_SEL_SHIFT 4
-#define BCHP_XPT_FE_IB1_CTRL_IB_ERROR_POL_SEL_DEFAULT 0x00000000
-
-/* XPT_FE :: IB1_CTRL :: IB_VALID_POL_SEL [03:03] */
-#define BCHP_XPT_FE_IB1_CTRL_IB_VALID_POL_SEL_MASK 0x00000008
-#define BCHP_XPT_FE_IB1_CTRL_IB_VALID_POL_SEL_SHIFT 3
-#define BCHP_XPT_FE_IB1_CTRL_IB_VALID_POL_SEL_DEFAULT 0x00000000
-
-/* XPT_FE :: IB1_CTRL :: IB_DATA_POL_SEL [02:02] */
-#define BCHP_XPT_FE_IB1_CTRL_IB_DATA_POL_SEL_MASK 0x00000004
-#define BCHP_XPT_FE_IB1_CTRL_IB_DATA_POL_SEL_SHIFT 2
-#define BCHP_XPT_FE_IB1_CTRL_IB_DATA_POL_SEL_DEFAULT 0x00000000
-
-/* XPT_FE :: IB1_CTRL :: IB_SYNC_POL_SEL [01:01] */
-#define BCHP_XPT_FE_IB1_CTRL_IB_SYNC_POL_SEL_MASK 0x00000002
-#define BCHP_XPT_FE_IB1_CTRL_IB_SYNC_POL_SEL_SHIFT 1
-#define BCHP_XPT_FE_IB1_CTRL_IB_SYNC_POL_SEL_DEFAULT 0x00000000
-
-/* XPT_FE :: IB1_CTRL :: IB_CLOCK_POL_SEL [00:00] */
-#define BCHP_XPT_FE_IB1_CTRL_IB_CLOCK_POL_SEL_MASK 0x00000001
-#define BCHP_XPT_FE_IB1_CTRL_IB_CLOCK_POL_SEL_SHIFT 0
-#define BCHP_XPT_FE_IB1_CTRL_IB_CLOCK_POL_SEL_DEFAULT 0x00000000
-
-/***************************************************************************
- *IB1_SYNC_COUNT - Data Transport Input Band 1 Sync counter Register
- ***************************************************************************/
-/* XPT_FE :: IB1_SYNC_COUNT :: reserved0 [31:08] */
-#define BCHP_XPT_FE_IB1_SYNC_COUNT_reserved0_MASK 0xffffff00
-#define BCHP_XPT_FE_IB1_SYNC_COUNT_reserved0_SHIFT 8
-
-/* XPT_FE :: IB1_SYNC_COUNT :: SYNC_COUNT [07:00] */
-#define BCHP_XPT_FE_IB1_SYNC_COUNT_SYNC_COUNT_MASK 0x000000ff
-#define BCHP_XPT_FE_IB1_SYNC_COUNT_SYNC_COUNT_SHIFT 0
-#define BCHP_XPT_FE_IB1_SYNC_COUNT_SYNC_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *IB2_CTRL - Data Transport Input Band 2 Control Register
- ***************************************************************************/
-/* XPT_FE :: IB2_CTRL :: reserved0 [31:24] */
-#define BCHP_XPT_FE_IB2_CTRL_reserved0_MASK 0xff000000
-#define BCHP_XPT_FE_IB2_CTRL_reserved0_SHIFT 24
-
-/* XPT_FE :: IB2_CTRL :: IB_PKT_LENGTH [23:16] */
-#define BCHP_XPT_FE_IB2_CTRL_IB_PKT_LENGTH_MASK 0x00ff0000
-#define BCHP_XPT_FE_IB2_CTRL_IB_PKT_LENGTH_SHIFT 16
-#define BCHP_XPT_FE_IB2_CTRL_IB_PKT_LENGTH_DEFAULT 0x000000bc
-
-/* XPT_FE :: IB2_CTRL :: reserved1 [15:11] */
-#define BCHP_XPT_FE_IB2_CTRL_reserved1_MASK 0x0000f800
-#define BCHP_XPT_FE_IB2_CTRL_reserved1_SHIFT 11
-
-/* XPT_FE :: IB2_CTRL :: IB_PARALLEL_INPUT_SEL [10:10] */
-#define BCHP_XPT_FE_IB2_CTRL_IB_PARALLEL_INPUT_SEL_MASK 0x00000400
-#define BCHP_XPT_FE_IB2_CTRL_IB_PARALLEL_INPUT_SEL_SHIFT 10
-#define BCHP_XPT_FE_IB2_CTRL_IB_PARALLEL_INPUT_SEL_DEFAULT 0x00000000
-
-/* XPT_FE :: IB2_CTRL :: IB_LSB_FIRST [09:09] */
-#define BCHP_XPT_FE_IB2_CTRL_IB_LSB_FIRST_MASK 0x00000200
-#define BCHP_XPT_FE_IB2_CTRL_IB_LSB_FIRST_SHIFT 9
-#define BCHP_XPT_FE_IB2_CTRL_IB_LSB_FIRST_DEFAULT 0x00000000
-
-/* XPT_FE :: IB2_CTRL :: IB_FORCE_VALID [08:08] */
-#define BCHP_XPT_FE_IB2_CTRL_IB_FORCE_VALID_MASK 0x00000100
-#define BCHP_XPT_FE_IB2_CTRL_IB_FORCE_VALID_SHIFT 8
-#define BCHP_XPT_FE_IB2_CTRL_IB_FORCE_VALID_DEFAULT 0x00000000
-
-/* XPT_FE :: IB2_CTRL :: IB_USE_SYNC_AS_VALID [07:07] */
-#define BCHP_XPT_FE_IB2_CTRL_IB_USE_SYNC_AS_VALID_MASK 0x00000080
-#define BCHP_XPT_FE_IB2_CTRL_IB_USE_SYNC_AS_VALID_SHIFT 7
-#define BCHP_XPT_FE_IB2_CTRL_IB_USE_SYNC_AS_VALID_DEFAULT 0x00000000
-
-/* XPT_FE :: IB2_CTRL :: IB_SYNC_DETECT_EN [06:06] */
-#define BCHP_XPT_FE_IB2_CTRL_IB_SYNC_DETECT_EN_MASK 0x00000040
-#define BCHP_XPT_FE_IB2_CTRL_IB_SYNC_DETECT_EN_SHIFT 6
-#define BCHP_XPT_FE_IB2_CTRL_IB_SYNC_DETECT_EN_DEFAULT 0x00000000
-
-/* XPT_FE :: IB2_CTRL :: IB_ERROR_INPUT_EN [05:05] */
-#define BCHP_XPT_FE_IB2_CTRL_IB_ERROR_INPUT_EN_MASK 0x00000020
-#define BCHP_XPT_FE_IB2_CTRL_IB_ERROR_INPUT_EN_SHIFT 5
-#define BCHP_XPT_FE_IB2_CTRL_IB_ERROR_INPUT_EN_DEFAULT 0x00000000
-
-/* XPT_FE :: IB2_CTRL :: IB_ERROR_POL_SEL [04:04] */
-#define BCHP_XPT_FE_IB2_CTRL_IB_ERROR_POL_SEL_MASK 0x00000010
-#define BCHP_XPT_FE_IB2_CTRL_IB_ERROR_POL_SEL_SHIFT 4
-#define BCHP_XPT_FE_IB2_CTRL_IB_ERROR_POL_SEL_DEFAULT 0x00000000
-
-/* XPT_FE :: IB2_CTRL :: IB_VALID_POL_SEL [03:03] */
-#define BCHP_XPT_FE_IB2_CTRL_IB_VALID_POL_SEL_MASK 0x00000008
-#define BCHP_XPT_FE_IB2_CTRL_IB_VALID_POL_SEL_SHIFT 3
-#define BCHP_XPT_FE_IB2_CTRL_IB_VALID_POL_SEL_DEFAULT 0x00000000
-
-/* XPT_FE :: IB2_CTRL :: IB_DATA_POL_SEL [02:02] */
-#define BCHP_XPT_FE_IB2_CTRL_IB_DATA_POL_SEL_MASK 0x00000004
-#define BCHP_XPT_FE_IB2_CTRL_IB_DATA_POL_SEL_SHIFT 2
-#define BCHP_XPT_FE_IB2_CTRL_IB_DATA_POL_SEL_DEFAULT 0x00000000
-
-/* XPT_FE :: IB2_CTRL :: IB_SYNC_POL_SEL [01:01] */
-#define BCHP_XPT_FE_IB2_CTRL_IB_SYNC_POL_SEL_MASK 0x00000002
-#define BCHP_XPT_FE_IB2_CTRL_IB_SYNC_POL_SEL_SHIFT 1
-#define BCHP_XPT_FE_IB2_CTRL_IB_SYNC_POL_SEL_DEFAULT 0x00000000
-
-/* XPT_FE :: IB2_CTRL :: IB_CLOCK_POL_SEL [00:00] */
-#define BCHP_XPT_FE_IB2_CTRL_IB_CLOCK_POL_SEL_MASK 0x00000001
-#define BCHP_XPT_FE_IB2_CTRL_IB_CLOCK_POL_SEL_SHIFT 0
-#define BCHP_XPT_FE_IB2_CTRL_IB_CLOCK_POL_SEL_DEFAULT 0x00000000
-
-/***************************************************************************
- *IB2_SYNC_COUNT - Data Transport Input Band 2 Sync counter Register
- ***************************************************************************/
-/* XPT_FE :: IB2_SYNC_COUNT :: reserved0 [31:08] */
-#define BCHP_XPT_FE_IB2_SYNC_COUNT_reserved0_MASK 0xffffff00
-#define BCHP_XPT_FE_IB2_SYNC_COUNT_reserved0_SHIFT 8
-
-/* XPT_FE :: IB2_SYNC_COUNT :: SYNC_COUNT [07:00] */
-#define BCHP_XPT_FE_IB2_SYNC_COUNT_SYNC_COUNT_MASK 0x000000ff
-#define BCHP_XPT_FE_IB2_SYNC_COUNT_SYNC_COUNT_SHIFT 0
-#define BCHP_XPT_FE_IB2_SYNC_COUNT_SYNC_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *IB3_CTRL - Data Transport Input Band 3 Control Register
- ***************************************************************************/
-/* XPT_FE :: IB3_CTRL :: reserved0 [31:24] */
-#define BCHP_XPT_FE_IB3_CTRL_reserved0_MASK 0xff000000
-#define BCHP_XPT_FE_IB3_CTRL_reserved0_SHIFT 24
-
-/* XPT_FE :: IB3_CTRL :: IB_PKT_LENGTH [23:16] */
-#define BCHP_XPT_FE_IB3_CTRL_IB_PKT_LENGTH_MASK 0x00ff0000
-#define BCHP_XPT_FE_IB3_CTRL_IB_PKT_LENGTH_SHIFT 16
-#define BCHP_XPT_FE_IB3_CTRL_IB_PKT_LENGTH_DEFAULT 0x000000bc
-
-/* XPT_FE :: IB3_CTRL :: reserved1 [15:11] */
-#define BCHP_XPT_FE_IB3_CTRL_reserved1_MASK 0x0000f800
-#define BCHP_XPT_FE_IB3_CTRL_reserved1_SHIFT 11
-
-/* XPT_FE :: IB3_CTRL :: IB_PARALLEL_INPUT_SEL [10:10] */
-#define BCHP_XPT_FE_IB3_CTRL_IB_PARALLEL_INPUT_SEL_MASK 0x00000400
-#define BCHP_XPT_FE_IB3_CTRL_IB_PARALLEL_INPUT_SEL_SHIFT 10
-#define BCHP_XPT_FE_IB3_CTRL_IB_PARALLEL_INPUT_SEL_DEFAULT 0x00000000
-
-/* XPT_FE :: IB3_CTRL :: IB_LSB_FIRST [09:09] */
-#define BCHP_XPT_FE_IB3_CTRL_IB_LSB_FIRST_MASK 0x00000200
-#define BCHP_XPT_FE_IB3_CTRL_IB_LSB_FIRST_SHIFT 9
-#define BCHP_XPT_FE_IB3_CTRL_IB_LSB_FIRST_DEFAULT 0x00000000
-
-/* XPT_FE :: IB3_CTRL :: IB_FORCE_VALID [08:08] */
-#define BCHP_XPT_FE_IB3_CTRL_IB_FORCE_VALID_MASK 0x00000100
-#define BCHP_XPT_FE_IB3_CTRL_IB_FORCE_VALID_SHIFT 8
-#define BCHP_XPT_FE_IB3_CTRL_IB_FORCE_VALID_DEFAULT 0x00000000
-
-/* XPT_FE :: IB3_CTRL :: IB_USE_SYNC_AS_VALID [07:07] */
-#define BCHP_XPT_FE_IB3_CTRL_IB_USE_SYNC_AS_VALID_MASK 0x00000080
-#define BCHP_XPT_FE_IB3_CTRL_IB_USE_SYNC_AS_VALID_SHIFT 7
-#define BCHP_XPT_FE_IB3_CTRL_IB_USE_SYNC_AS_VALID_DEFAULT 0x00000000
-
-/* XPT_FE :: IB3_CTRL :: IB_SYNC_DETECT_EN [06:06] */
-#define BCHP_XPT_FE_IB3_CTRL_IB_SYNC_DETECT_EN_MASK 0x00000040
-#define BCHP_XPT_FE_IB3_CTRL_IB_SYNC_DETECT_EN_SHIFT 6
-#define BCHP_XPT_FE_IB3_CTRL_IB_SYNC_DETECT_EN_DEFAULT 0x00000000
-
-/* XPT_FE :: IB3_CTRL :: IB_ERROR_INPUT_EN [05:05] */
-#define BCHP_XPT_FE_IB3_CTRL_IB_ERROR_INPUT_EN_MASK 0x00000020
-#define BCHP_XPT_FE_IB3_CTRL_IB_ERROR_INPUT_EN_SHIFT 5
-#define BCHP_XPT_FE_IB3_CTRL_IB_ERROR_INPUT_EN_DEFAULT 0x00000000
-
-/* XPT_FE :: IB3_CTRL :: IB_ERROR_POL_SEL [04:04] */
-#define BCHP_XPT_FE_IB3_CTRL_IB_ERROR_POL_SEL_MASK 0x00000010
-#define BCHP_XPT_FE_IB3_CTRL_IB_ERROR_POL_SEL_SHIFT 4
-#define BCHP_XPT_FE_IB3_CTRL_IB_ERROR_POL_SEL_DEFAULT 0x00000000
-
-/* XPT_FE :: IB3_CTRL :: IB_VALID_POL_SEL [03:03] */
-#define BCHP_XPT_FE_IB3_CTRL_IB_VALID_POL_SEL_MASK 0x00000008
-#define BCHP_XPT_FE_IB3_CTRL_IB_VALID_POL_SEL_SHIFT 3
-#define BCHP_XPT_FE_IB3_CTRL_IB_VALID_POL_SEL_DEFAULT 0x00000000
-
-/* XPT_FE :: IB3_CTRL :: IB_DATA_POL_SEL [02:02] */
-#define BCHP_XPT_FE_IB3_CTRL_IB_DATA_POL_SEL_MASK 0x00000004
-#define BCHP_XPT_FE_IB3_CTRL_IB_DATA_POL_SEL_SHIFT 2
-#define BCHP_XPT_FE_IB3_CTRL_IB_DATA_POL_SEL_DEFAULT 0x00000000
-
-/* XPT_FE :: IB3_CTRL :: IB_SYNC_POL_SEL [01:01] */
-#define BCHP_XPT_FE_IB3_CTRL_IB_SYNC_POL_SEL_MASK 0x00000002
-#define BCHP_XPT_FE_IB3_CTRL_IB_SYNC_POL_SEL_SHIFT 1
-#define BCHP_XPT_FE_IB3_CTRL_IB_SYNC_POL_SEL_DEFAULT 0x00000000
-
-/* XPT_FE :: IB3_CTRL :: IB_CLOCK_POL_SEL [00:00] */
-#define BCHP_XPT_FE_IB3_CTRL_IB_CLOCK_POL_SEL_MASK 0x00000001
-#define BCHP_XPT_FE_IB3_CTRL_IB_CLOCK_POL_SEL_SHIFT 0
-#define BCHP_XPT_FE_IB3_CTRL_IB_CLOCK_POL_SEL_DEFAULT 0x00000000
-
-/***************************************************************************
- *IB3_SYNC_COUNT - Data Transport Input Band 3 Sync counter Register
- ***************************************************************************/
-/* XPT_FE :: IB3_SYNC_COUNT :: reserved0 [31:08] */
-#define BCHP_XPT_FE_IB3_SYNC_COUNT_reserved0_MASK 0xffffff00
-#define BCHP_XPT_FE_IB3_SYNC_COUNT_reserved0_SHIFT 8
-
-/* XPT_FE :: IB3_SYNC_COUNT :: SYNC_COUNT [07:00] */
-#define BCHP_XPT_FE_IB3_SYNC_COUNT_SYNC_COUNT_MASK 0x000000ff
-#define BCHP_XPT_FE_IB3_SYNC_COUNT_SYNC_COUNT_SHIFT 0
-#define BCHP_XPT_FE_IB3_SYNC_COUNT_SYNC_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *IB10_CTRL - Data Transport Input Band 10 Control Register
- ***************************************************************************/
-/* XPT_FE :: IB10_CTRL :: reserved0 [31:24] */
-#define BCHP_XPT_FE_IB10_CTRL_reserved0_MASK 0xff000000
-#define BCHP_XPT_FE_IB10_CTRL_reserved0_SHIFT 24
-
-/* XPT_FE :: IB10_CTRL :: IB_PKT_LENGTH [23:16] */
-#define BCHP_XPT_FE_IB10_CTRL_IB_PKT_LENGTH_MASK 0x00ff0000
-#define BCHP_XPT_FE_IB10_CTRL_IB_PKT_LENGTH_SHIFT 16
-#define BCHP_XPT_FE_IB10_CTRL_IB_PKT_LENGTH_DEFAULT 0x000000bc
-
-/* XPT_FE :: IB10_CTRL :: reserved1 [15:11] */
-#define BCHP_XPT_FE_IB10_CTRL_reserved1_MASK 0x0000f800
-#define BCHP_XPT_FE_IB10_CTRL_reserved1_SHIFT 11
-
-/* XPT_FE :: IB10_CTRL :: IB_PARALLEL_INPUT_SEL [10:10] */
-#define BCHP_XPT_FE_IB10_CTRL_IB_PARALLEL_INPUT_SEL_MASK 0x00000400
-#define BCHP_XPT_FE_IB10_CTRL_IB_PARALLEL_INPUT_SEL_SHIFT 10
-#define BCHP_XPT_FE_IB10_CTRL_IB_PARALLEL_INPUT_SEL_DEFAULT 0x00000000
-
-/* XPT_FE :: IB10_CTRL :: IB_LSB_FIRST [09:09] */
-#define BCHP_XPT_FE_IB10_CTRL_IB_LSB_FIRST_MASK 0x00000200
-#define BCHP_XPT_FE_IB10_CTRL_IB_LSB_FIRST_SHIFT 9
-#define BCHP_XPT_FE_IB10_CTRL_IB_LSB_FIRST_DEFAULT 0x00000000
-
-/* XPT_FE :: IB10_CTRL :: IB_FORCE_VALID [08:08] */
-#define BCHP_XPT_FE_IB10_CTRL_IB_FORCE_VALID_MASK 0x00000100
-#define BCHP_XPT_FE_IB10_CTRL_IB_FORCE_VALID_SHIFT 8
-#define BCHP_XPT_FE_IB10_CTRL_IB_FORCE_VALID_DEFAULT 0x00000000
-
-/* XPT_FE :: IB10_CTRL :: IB_USE_SYNC_AS_VALID [07:07] */
-#define BCHP_XPT_FE_IB10_CTRL_IB_USE_SYNC_AS_VALID_MASK 0x00000080
-#define BCHP_XPT_FE_IB10_CTRL_IB_USE_SYNC_AS_VALID_SHIFT 7
-#define BCHP_XPT_FE_IB10_CTRL_IB_USE_SYNC_AS_VALID_DEFAULT 0x00000000
-
-/* XPT_FE :: IB10_CTRL :: IB_SYNC_DETECT_EN [06:06] */
-#define BCHP_XPT_FE_IB10_CTRL_IB_SYNC_DETECT_EN_MASK 0x00000040
-#define BCHP_XPT_FE_IB10_CTRL_IB_SYNC_DETECT_EN_SHIFT 6
-#define BCHP_XPT_FE_IB10_CTRL_IB_SYNC_DETECT_EN_DEFAULT 0x00000000
-
-/* XPT_FE :: IB10_CTRL :: IB_ERROR_INPUT_EN [05:05] */
-#define BCHP_XPT_FE_IB10_CTRL_IB_ERROR_INPUT_EN_MASK 0x00000020
-#define BCHP_XPT_FE_IB10_CTRL_IB_ERROR_INPUT_EN_SHIFT 5
-#define BCHP_XPT_FE_IB10_CTRL_IB_ERROR_INPUT_EN_DEFAULT 0x00000000
-
-/* XPT_FE :: IB10_CTRL :: IB_ERROR_POL_SEL [04:04] */
-#define BCHP_XPT_FE_IB10_CTRL_IB_ERROR_POL_SEL_MASK 0x00000010
-#define BCHP_XPT_FE_IB10_CTRL_IB_ERROR_POL_SEL_SHIFT 4
-#define BCHP_XPT_FE_IB10_CTRL_IB_ERROR_POL_SEL_DEFAULT 0x00000000
-
-/* XPT_FE :: IB10_CTRL :: IB_VALID_POL_SEL [03:03] */
-#define BCHP_XPT_FE_IB10_CTRL_IB_VALID_POL_SEL_MASK 0x00000008
-#define BCHP_XPT_FE_IB10_CTRL_IB_VALID_POL_SEL_SHIFT 3
-#define BCHP_XPT_FE_IB10_CTRL_IB_VALID_POL_SEL_DEFAULT 0x00000000
-
-/* XPT_FE :: IB10_CTRL :: IB_DATA_POL_SEL [02:02] */
-#define BCHP_XPT_FE_IB10_CTRL_IB_DATA_POL_SEL_MASK 0x00000004
-#define BCHP_XPT_FE_IB10_CTRL_IB_DATA_POL_SEL_SHIFT 2
-#define BCHP_XPT_FE_IB10_CTRL_IB_DATA_POL_SEL_DEFAULT 0x00000000
-
-/* XPT_FE :: IB10_CTRL :: IB_SYNC_POL_SEL [01:01] */
-#define BCHP_XPT_FE_IB10_CTRL_IB_SYNC_POL_SEL_MASK 0x00000002
-#define BCHP_XPT_FE_IB10_CTRL_IB_SYNC_POL_SEL_SHIFT 1
-#define BCHP_XPT_FE_IB10_CTRL_IB_SYNC_POL_SEL_DEFAULT 0x00000000
-
-/* XPT_FE :: IB10_CTRL :: IB_CLOCK_POL_SEL [00:00] */
-#define BCHP_XPT_FE_IB10_CTRL_IB_CLOCK_POL_SEL_MASK 0x00000001
-#define BCHP_XPT_FE_IB10_CTRL_IB_CLOCK_POL_SEL_SHIFT 0
-#define BCHP_XPT_FE_IB10_CTRL_IB_CLOCK_POL_SEL_DEFAULT 0x00000000
-
-/***************************************************************************
- *IB10_SYNC_COUNT - Data Transport Input Band 10 Sync counter Register
- ***************************************************************************/
-/* XPT_FE :: IB10_SYNC_COUNT :: reserved0 [31:08] */
-#define BCHP_XPT_FE_IB10_SYNC_COUNT_reserved0_MASK 0xffffff00
-#define BCHP_XPT_FE_IB10_SYNC_COUNT_reserved0_SHIFT 8
-
-/* XPT_FE :: IB10_SYNC_COUNT :: SYNC_COUNT [07:00] */
-#define BCHP_XPT_FE_IB10_SYNC_COUNT_SYNC_COUNT_MASK 0x000000ff
-#define BCHP_XPT_FE_IB10_SYNC_COUNT_SYNC_COUNT_SHIFT 0
-#define BCHP_XPT_FE_IB10_SYNC_COUNT_SYNC_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *MINI_PID_PARSER0_CTRL1 - Data Transport Parser Band 0 Control Register
- ***************************************************************************/
-/* XPT_FE :: MINI_PID_PARSER0_CTRL1 :: reserved0 [31:29] */
-#define BCHP_XPT_FE_MINI_PID_PARSER0_CTRL1_reserved0_MASK 0xe0000000
-#define BCHP_XPT_FE_MINI_PID_PARSER0_CTRL1_reserved0_SHIFT 29
-
-/* XPT_FE :: MINI_PID_PARSER0_CTRL1 :: PARSER_TIMESTAMP_MODE [28:27] */
-#define BCHP_XPT_FE_MINI_PID_PARSER0_CTRL1_PARSER_TIMESTAMP_MODE_MASK 0x18000000
-#define BCHP_XPT_FE_MINI_PID_PARSER0_CTRL1_PARSER_TIMESTAMP_MODE_SHIFT 27
-#define BCHP_XPT_FE_MINI_PID_PARSER0_CTRL1_PARSER_TIMESTAMP_MODE_DEFAULT 0x00000002
-
-/* XPT_FE :: MINI_PID_PARSER0_CTRL1 :: PARSER_TSMF_SEL [26:23] */
-#define BCHP_XPT_FE_MINI_PID_PARSER0_CTRL1_PARSER_TSMF_SEL_MASK 0x07800000
-#define BCHP_XPT_FE_MINI_PID_PARSER0_CTRL1_PARSER_TSMF_SEL_SHIFT 23
-#define BCHP_XPT_FE_MINI_PID_PARSER0_CTRL1_PARSER_TSMF_SEL_DEFAULT 0x00000000
-
-/* XPT_FE :: MINI_PID_PARSER0_CTRL1 :: PARSER_TSMF_EN [22:22] */
-#define BCHP_XPT_FE_MINI_PID_PARSER0_CTRL1_PARSER_TSMF_EN_MASK 0x00400000
-#define BCHP_XPT_FE_MINI_PID_PARSER0_CTRL1_PARSER_TSMF_EN_SHIFT 22
-#define BCHP_XPT_FE_MINI_PID_PARSER0_CTRL1_PARSER_TSMF_EN_DEFAULT 0x00000000
-
-/* XPT_FE :: MINI_PID_PARSER0_CTRL1 :: PARSER_INPUT_SEL_MSB [21:21] */
-#define BCHP_XPT_FE_MINI_PID_PARSER0_CTRL1_PARSER_INPUT_SEL_MSB_MASK 0x00200000
-#define BCHP_XPT_FE_MINI_PID_PARSER0_CTRL1_PARSER_INPUT_SEL_MSB_SHIFT 21
-#define BCHP_XPT_FE_MINI_PID_PARSER0_CTRL1_PARSER_INPUT_SEL_MSB_DEFAULT 0x00000000
-
-/* XPT_FE :: MINI_PID_PARSER0_CTRL1 :: PARSER_ERROR_INPUT_TEI_IGNORE [20:20] */
-#define BCHP_XPT_FE_MINI_PID_PARSER0_CTRL1_PARSER_ERROR_INPUT_TEI_IGNORE_MASK 0x00100000
-#define BCHP_XPT_FE_MINI_PID_PARSER0_CTRL1_PARSER_ERROR_INPUT_TEI_IGNORE_SHIFT 20
-#define BCHP_XPT_FE_MINI_PID_PARSER0_CTRL1_PARSER_ERROR_INPUT_TEI_IGNORE_DEFAULT 0x00000000
-
-/* XPT_FE :: MINI_PID_PARSER0_CTRL1 :: PARSER_PKT_LENGTH [19:12] */
-#define BCHP_XPT_FE_MINI_PID_PARSER0_CTRL1_PARSER_PKT_LENGTH_MASK 0x000ff000
-#define BCHP_XPT_FE_MINI_PID_PARSER0_CTRL1_PARSER_PKT_LENGTH_SHIFT 12
-#define BCHP_XPT_FE_MINI_PID_PARSER0_CTRL1_PARSER_PKT_LENGTH_DEFAULT 0x000000bc
-
-/* XPT_FE :: MINI_PID_PARSER0_CTRL1 :: PARSER_INPUT_SEL [11:08] */
-#define BCHP_XPT_FE_MINI_PID_PARSER0_CTRL1_PARSER_INPUT_SEL_MASK 0x00000f00
-#define BCHP_XPT_FE_MINI_PID_PARSER0_CTRL1_PARSER_INPUT_SEL_SHIFT 8
-#define BCHP_XPT_FE_MINI_PID_PARSER0_CTRL1_PARSER_INPUT_SEL_DEFAULT 0x00000000
-
-/* XPT_FE :: MINI_PID_PARSER0_CTRL1 :: reserved1 [07:07] */
-#define BCHP_XPT_FE_MINI_PID_PARSER0_CTRL1_reserved1_MASK 0x00000080
-#define BCHP_XPT_FE_MINI_PID_PARSER0_CTRL1_reserved1_SHIFT 7
-
-/* XPT_FE :: MINI_PID_PARSER0_CTRL1 :: PARSER_PACKET_TYPE [06:05] */
-#define BCHP_XPT_FE_MINI_PID_PARSER0_CTRL1_PARSER_PACKET_TYPE_MASK 0x00000060
-#define BCHP_XPT_FE_MINI_PID_PARSER0_CTRL1_PARSER_PACKET_TYPE_SHIFT 5
-#define BCHP_XPT_FE_MINI_PID_PARSER0_CTRL1_PARSER_PACKET_TYPE_DEFAULT 0x00000000
-
-/* XPT_FE :: MINI_PID_PARSER0_CTRL1 :: PARSER_ACCEPT_NULL_PKT_PRE_MPOD [04:04] */
-#define BCHP_XPT_FE_MINI_PID_PARSER0_CTRL1_PARSER_ACCEPT_NULL_PKT_PRE_MPOD_MASK 0x00000010
-#define BCHP_XPT_FE_MINI_PID_PARSER0_CTRL1_PARSER_ACCEPT_NULL_PKT_PRE_MPOD_SHIFT 4
-#define BCHP_XPT_FE_MINI_PID_PARSER0_CTRL1_PARSER_ACCEPT_NULL_PKT_PRE_MPOD_DEFAULT 0x00000000
-
-/* XPT_FE :: MINI_PID_PARSER0_CTRL1 :: PARSER_ACCEPT_NULL_PKT_PRE_TSIO [03:03] */
-#define BCHP_XPT_FE_MINI_PID_PARSER0_CTRL1_PARSER_ACCEPT_NULL_PKT_PRE_TSIO_MASK 0x00000008
-#define BCHP_XPT_FE_MINI_PID_PARSER0_CTRL1_PARSER_ACCEPT_NULL_PKT_PRE_TSIO_SHIFT 3
-#define BCHP_XPT_FE_MINI_PID_PARSER0_CTRL1_PARSER_ACCEPT_NULL_PKT_PRE_TSIO_DEFAULT 0x00000000
-
-/* XPT_FE :: MINI_PID_PARSER0_CTRL1 :: PARSER_ALL_PASS_CTRL_PRE_TSIO [02:02] */
-#define BCHP_XPT_FE_MINI_PID_PARSER0_CTRL1_PARSER_ALL_PASS_CTRL_PRE_TSIO_MASK 0x00000004
-#define BCHP_XPT_FE_MINI_PID_PARSER0_CTRL1_PARSER_ALL_PASS_CTRL_PRE_TSIO_SHIFT 2
-#define BCHP_XPT_FE_MINI_PID_PARSER0_CTRL1_PARSER_ALL_PASS_CTRL_PRE_TSIO_DEFAULT 0x00000000
-
-/* XPT_FE :: MINI_PID_PARSER0_CTRL1 :: PARSER_ALL_PASS_CTRL_PRE_MPOD [01:01] */
-#define BCHP_XPT_FE_MINI_PID_PARSER0_CTRL1_PARSER_ALL_PASS_CTRL_PRE_MPOD_MASK 0x00000002
-#define BCHP_XPT_FE_MINI_PID_PARSER0_CTRL1_PARSER_ALL_PASS_CTRL_PRE_MPOD_SHIFT 1
-#define BCHP_XPT_FE_MINI_PID_PARSER0_CTRL1_PARSER_ALL_PASS_CTRL_PRE_MPOD_DEFAULT 0x00000000
-
-/* XPT_FE :: MINI_PID_PARSER0_CTRL1 :: PARSER_ENABLE [00:00] */
-#define BCHP_XPT_FE_MINI_PID_PARSER0_CTRL1_PARSER_ENABLE_MASK 0x00000001
-#define BCHP_XPT_FE_MINI_PID_PARSER0_CTRL1_PARSER_ENABLE_SHIFT 0
-#define BCHP_XPT_FE_MINI_PID_PARSER0_CTRL1_PARSER_ENABLE_DEFAULT 0x00000000
-
-/***************************************************************************
- *MINI_PID_PARSER0_CTRL2 - Data Transport Parser Band 0 Control Register 2
- ***************************************************************************/
-/* XPT_FE :: MINI_PID_PARSER0_CTRL2 :: reserved0 [31:14] */
-#define BCHP_XPT_FE_MINI_PID_PARSER0_CTRL2_reserved0_MASK 0xffffc000
-#define BCHP_XPT_FE_MINI_PID_PARSER0_CTRL2_reserved0_SHIFT 14
-
-/* XPT_FE :: MINI_PID_PARSER0_CTRL2 :: PARSER_STREAM_TIMESTAMP_EN [13:13] */
-#define BCHP_XPT_FE_MINI_PID_PARSER0_CTRL2_PARSER_STREAM_TIMESTAMP_EN_MASK 0x00002000
-#define BCHP_XPT_FE_MINI_PID_PARSER0_CTRL2_PARSER_STREAM_TIMESTAMP_EN_SHIFT 13
-#define BCHP_XPT_FE_MINI_PID_PARSER0_CTRL2_PARSER_STREAM_TIMESTAMP_EN_DEFAULT 0x00000000
-
-/* XPT_FE :: MINI_PID_PARSER0_CTRL2 :: PARSER_TIMESTREAM_BF_SYNC [12:12] */
-#define BCHP_XPT_FE_MINI_PID_PARSER0_CTRL2_PARSER_TIMESTREAM_BF_SYNC_MASK 0x00001000
-#define BCHP_XPT_FE_MINI_PID_PARSER0_CTRL2_PARSER_TIMESTREAM_BF_SYNC_SHIFT 12
-#define BCHP_XPT_FE_MINI_PID_PARSER0_CTRL2_PARSER_TIMESTREAM_BF_SYNC_DEFAULT 0x00000000
-
-/* XPT_FE :: MINI_PID_PARSER0_CTRL2 :: reserved1 [11:11] */
-#define BCHP_XPT_FE_MINI_PID_PARSER0_CTRL2_reserved1_MASK 0x00000800
-#define BCHP_XPT_FE_MINI_PID_PARSER0_CTRL2_reserved1_SHIFT 11
-
-/* XPT_FE :: MINI_PID_PARSER0_CTRL2 :: PARSER_TIMESTAMP_RESTAMP [10:10] */
-#define BCHP_XPT_FE_MINI_PID_PARSER0_CTRL2_PARSER_TIMESTAMP_RESTAMP_MASK 0x00000400
-#define BCHP_XPT_FE_MINI_PID_PARSER0_CTRL2_PARSER_TIMESTAMP_RESTAMP_SHIFT 10
-#define BCHP_XPT_FE_MINI_PID_PARSER0_CTRL2_PARSER_TIMESTAMP_RESTAMP_DEFAULT 0x00000001
-
-/* XPT_FE :: MINI_PID_PARSER0_CTRL2 :: TSIO_MODE_SEL [09:09] */
-#define BCHP_XPT_FE_MINI_PID_PARSER0_CTRL2_TSIO_MODE_SEL_MASK 0x00000200
-#define BCHP_XPT_FE_MINI_PID_PARSER0_CTRL2_TSIO_MODE_SEL_SHIFT 9
-#define BCHP_XPT_FE_MINI_PID_PARSER0_CTRL2_TSIO_MODE_SEL_DEFAULT 0x00000001
-
-/* XPT_FE :: MINI_PID_PARSER0_CTRL2 :: reserved2 [08:07] */
-#define BCHP_XPT_FE_MINI_PID_PARSER0_CTRL2_reserved2_MASK 0x00000180
-#define BCHP_XPT_FE_MINI_PID_PARSER0_CTRL2_reserved2_SHIFT 7
-
-/* XPT_FE :: MINI_PID_PARSER0_CTRL2 :: TSIO_EN [06:06] */
-#define BCHP_XPT_FE_MINI_PID_PARSER0_CTRL2_TSIO_EN_MASK 0x00000040
-#define BCHP_XPT_FE_MINI_PID_PARSER0_CTRL2_TSIO_EN_SHIFT 6
-#define BCHP_XPT_FE_MINI_PID_PARSER0_CTRL2_TSIO_EN_DEFAULT 0x00000000
-
-/* XPT_FE :: MINI_PID_PARSER0_CTRL2 :: reserved3 [05:05] */
-#define BCHP_XPT_FE_MINI_PID_PARSER0_CTRL2_reserved3_MASK 0x00000020
-#define BCHP_XPT_FE_MINI_PID_PARSER0_CTRL2_reserved3_SHIFT 5
-
-/* XPT_FE :: MINI_PID_PARSER0_CTRL2 :: MPOD_MODE_SEL [04:04] */
-#define BCHP_XPT_FE_MINI_PID_PARSER0_CTRL2_MPOD_MODE_SEL_MASK 0x00000010
-#define BCHP_XPT_FE_MINI_PID_PARSER0_CTRL2_MPOD_MODE_SEL_SHIFT 4
-#define BCHP_XPT_FE_MINI_PID_PARSER0_CTRL2_MPOD_MODE_SEL_DEFAULT 0x00000000
-
-/* XPT_FE :: MINI_PID_PARSER0_CTRL2 :: reserved4 [03:03] */
-#define BCHP_XPT_FE_MINI_PID_PARSER0_CTRL2_reserved4_MASK 0x00000008
-#define BCHP_XPT_FE_MINI_PID_PARSER0_CTRL2_reserved4_SHIFT 3
-
-/* XPT_FE :: MINI_PID_PARSER0_CTRL2 :: PARSER_ACCEPT_NULL_PKT_POST_MPOD [02:02] */
-#define BCHP_XPT_FE_MINI_PID_PARSER0_CTRL2_PARSER_ACCEPT_NULL_PKT_POST_MPOD_MASK 0x00000004
-#define BCHP_XPT_FE_MINI_PID_PARSER0_CTRL2_PARSER_ACCEPT_NULL_PKT_POST_MPOD_SHIFT 2
-#define BCHP_XPT_FE_MINI_PID_PARSER0_CTRL2_PARSER_ACCEPT_NULL_PKT_POST_MPOD_DEFAULT 0x00000000
-
-/* XPT_FE :: MINI_PID_PARSER0_CTRL2 :: PARSER_ALL_PASS_CTRL_POST_MPOD [01:01] */
-#define BCHP_XPT_FE_MINI_PID_PARSER0_CTRL2_PARSER_ALL_PASS_CTRL_POST_MPOD_MASK 0x00000002
-#define BCHP_XPT_FE_MINI_PID_PARSER0_CTRL2_PARSER_ALL_PASS_CTRL_POST_MPOD_SHIFT 1
-#define BCHP_XPT_FE_MINI_PID_PARSER0_CTRL2_PARSER_ALL_PASS_CTRL_POST_MPOD_DEFAULT 0x00000000
-
-/* XPT_FE :: MINI_PID_PARSER0_CTRL2 :: MPOD_EN [00:00] */
-#define BCHP_XPT_FE_MINI_PID_PARSER0_CTRL2_MPOD_EN_MASK 0x00000001
-#define BCHP_XPT_FE_MINI_PID_PARSER0_CTRL2_MPOD_EN_SHIFT 0
-#define BCHP_XPT_FE_MINI_PID_PARSER0_CTRL2_MPOD_EN_DEFAULT 0x00000000
-
-/***************************************************************************
- *MINI_PID_PARSER0_ALL_PASS_CTRL - Data Transport Parser Band 0 Control Register
- ***************************************************************************/
-/* XPT_FE :: MINI_PID_PARSER0_ALL_PASS_CTRL :: reserved0 [31:13] */
-#define BCHP_XPT_FE_MINI_PID_PARSER0_ALL_PASS_CTRL_reserved0_MASK 0xffffe000
-#define BCHP_XPT_FE_MINI_PID_PARSER0_ALL_PASS_CTRL_reserved0_SHIFT 13
-
-/* XPT_FE :: MINI_PID_PARSER0_ALL_PASS_CTRL :: PIDP_DEBUG_MODE [12:12] */
-#define BCHP_XPT_FE_MINI_PID_PARSER0_ALL_PASS_CTRL_PIDP_DEBUG_MODE_MASK 0x00001000
-#define BCHP_XPT_FE_MINI_PID_PARSER0_ALL_PASS_CTRL_PIDP_DEBUG_MODE_SHIFT 12
-#define BCHP_XPT_FE_MINI_PID_PARSER0_ALL_PASS_CTRL_PIDP_DEBUG_MODE_DEFAULT 0x00000000
-
-/* XPT_FE :: MINI_PID_PARSER0_ALL_PASS_CTRL :: ALL_PASS_PID_CH_NUM [11:00] */
-#define BCHP_XPT_FE_MINI_PID_PARSER0_ALL_PASS_CTRL_ALL_PASS_PID_CH_NUM_MASK 0x00000fff
-#define BCHP_XPT_FE_MINI_PID_PARSER0_ALL_PASS_CTRL_ALL_PASS_PID_CH_NUM_SHIFT 0
-#define BCHP_XPT_FE_MINI_PID_PARSER0_ALL_PASS_CTRL_ALL_PASS_PID_CH_NUM_DEFAULT 0x00000000
-
-/***************************************************************************
- *MINI_PID_PARSER1_CTRL1 - Data Transport Parser Band 1 Control Register
- ***************************************************************************/
-/* XPT_FE :: MINI_PID_PARSER1_CTRL1 :: reserved0 [31:29] */
-#define BCHP_XPT_FE_MINI_PID_PARSER1_CTRL1_reserved0_MASK 0xe0000000
-#define BCHP_XPT_FE_MINI_PID_PARSER1_CTRL1_reserved0_SHIFT 29
-
-/* XPT_FE :: MINI_PID_PARSER1_CTRL1 :: PARSER_TIMESTAMP_MODE [28:27] */
-#define BCHP_XPT_FE_MINI_PID_PARSER1_CTRL1_PARSER_TIMESTAMP_MODE_MASK 0x18000000
-#define BCHP_XPT_FE_MINI_PID_PARSER1_CTRL1_PARSER_TIMESTAMP_MODE_SHIFT 27
-#define BCHP_XPT_FE_MINI_PID_PARSER1_CTRL1_PARSER_TIMESTAMP_MODE_DEFAULT 0x00000002
-
-/* XPT_FE :: MINI_PID_PARSER1_CTRL1 :: PARSER_TSMF_SEL [26:23] */
-#define BCHP_XPT_FE_MINI_PID_PARSER1_CTRL1_PARSER_TSMF_SEL_MASK 0x07800000
-#define BCHP_XPT_FE_MINI_PID_PARSER1_CTRL1_PARSER_TSMF_SEL_SHIFT 23
-#define BCHP_XPT_FE_MINI_PID_PARSER1_CTRL1_PARSER_TSMF_SEL_DEFAULT 0x00000000
-
-/* XPT_FE :: MINI_PID_PARSER1_CTRL1 :: PARSER_TSMF_EN [22:22] */
-#define BCHP_XPT_FE_MINI_PID_PARSER1_CTRL1_PARSER_TSMF_EN_MASK 0x00400000
-#define BCHP_XPT_FE_MINI_PID_PARSER1_CTRL1_PARSER_TSMF_EN_SHIFT 22
-#define BCHP_XPT_FE_MINI_PID_PARSER1_CTRL1_PARSER_TSMF_EN_DEFAULT 0x00000000
-
-/* XPT_FE :: MINI_PID_PARSER1_CTRL1 :: PARSER_INPUT_SEL_MSB [21:21] */
-#define BCHP_XPT_FE_MINI_PID_PARSER1_CTRL1_PARSER_INPUT_SEL_MSB_MASK 0x00200000
-#define BCHP_XPT_FE_MINI_PID_PARSER1_CTRL1_PARSER_INPUT_SEL_MSB_SHIFT 21
-#define BCHP_XPT_FE_MINI_PID_PARSER1_CTRL1_PARSER_INPUT_SEL_MSB_DEFAULT 0x00000000
-
-/* XPT_FE :: MINI_PID_PARSER1_CTRL1 :: PARSER_ERROR_INPUT_TEI_IGNORE [20:20] */
-#define BCHP_XPT_FE_MINI_PID_PARSER1_CTRL1_PARSER_ERROR_INPUT_TEI_IGNORE_MASK 0x00100000
-#define BCHP_XPT_FE_MINI_PID_PARSER1_CTRL1_PARSER_ERROR_INPUT_TEI_IGNORE_SHIFT 20
-#define BCHP_XPT_FE_MINI_PID_PARSER1_CTRL1_PARSER_ERROR_INPUT_TEI_IGNORE_DEFAULT 0x00000000
-
-/* XPT_FE :: MINI_PID_PARSER1_CTRL1 :: PARSER_PKT_LENGTH [19:12] */
-#define BCHP_XPT_FE_MINI_PID_PARSER1_CTRL1_PARSER_PKT_LENGTH_MASK 0x000ff000
-#define BCHP_XPT_FE_MINI_PID_PARSER1_CTRL1_PARSER_PKT_LENGTH_SHIFT 12
-#define BCHP_XPT_FE_MINI_PID_PARSER1_CTRL1_PARSER_PKT_LENGTH_DEFAULT 0x000000bc
-
-/* XPT_FE :: MINI_PID_PARSER1_CTRL1 :: PARSER_INPUT_SEL [11:08] */
-#define BCHP_XPT_FE_MINI_PID_PARSER1_CTRL1_PARSER_INPUT_SEL_MASK 0x00000f00
-#define BCHP_XPT_FE_MINI_PID_PARSER1_CTRL1_PARSER_INPUT_SEL_SHIFT 8
-#define BCHP_XPT_FE_MINI_PID_PARSER1_CTRL1_PARSER_INPUT_SEL_DEFAULT 0x00000000
-
-/* XPT_FE :: MINI_PID_PARSER1_CTRL1 :: reserved1 [07:07] */
-#define BCHP_XPT_FE_MINI_PID_PARSER1_CTRL1_reserved1_MASK 0x00000080
-#define BCHP_XPT_FE_MINI_PID_PARSER1_CTRL1_reserved1_SHIFT 7
-
-/* XPT_FE :: MINI_PID_PARSER1_CTRL1 :: PARSER_PACKET_TYPE [06:05] */
-#define BCHP_XPT_FE_MINI_PID_PARSER1_CTRL1_PARSER_PACKET_TYPE_MASK 0x00000060
-#define BCHP_XPT_FE_MINI_PID_PARSER1_CTRL1_PARSER_PACKET_TYPE_SHIFT 5
-#define BCHP_XPT_FE_MINI_PID_PARSER1_CTRL1_PARSER_PACKET_TYPE_DEFAULT 0x00000000
-
-/* XPT_FE :: MINI_PID_PARSER1_CTRL1 :: PARSER_ACCEPT_NULL_PKT_PRE_MPOD [04:04] */
-#define BCHP_XPT_FE_MINI_PID_PARSER1_CTRL1_PARSER_ACCEPT_NULL_PKT_PRE_MPOD_MASK 0x00000010
-#define BCHP_XPT_FE_MINI_PID_PARSER1_CTRL1_PARSER_ACCEPT_NULL_PKT_PRE_MPOD_SHIFT 4
-#define BCHP_XPT_FE_MINI_PID_PARSER1_CTRL1_PARSER_ACCEPT_NULL_PKT_PRE_MPOD_DEFAULT 0x00000000
-
-/* XPT_FE :: MINI_PID_PARSER1_CTRL1 :: PARSER_ACCEPT_NULL_PKT_PRE_TSIO [03:03] */
-#define BCHP_XPT_FE_MINI_PID_PARSER1_CTRL1_PARSER_ACCEPT_NULL_PKT_PRE_TSIO_MASK 0x00000008
-#define BCHP_XPT_FE_MINI_PID_PARSER1_CTRL1_PARSER_ACCEPT_NULL_PKT_PRE_TSIO_SHIFT 3
-#define BCHP_XPT_FE_MINI_PID_PARSER1_CTRL1_PARSER_ACCEPT_NULL_PKT_PRE_TSIO_DEFAULT 0x00000000
-
-/* XPT_FE :: MINI_PID_PARSER1_CTRL1 :: PARSER_ALL_PASS_CTRL_PRE_TSIO [02:02] */
-#define BCHP_XPT_FE_MINI_PID_PARSER1_CTRL1_PARSER_ALL_PASS_CTRL_PRE_TSIO_MASK 0x00000004
-#define BCHP_XPT_FE_MINI_PID_PARSER1_CTRL1_PARSER_ALL_PASS_CTRL_PRE_TSIO_SHIFT 2
-#define BCHP_XPT_FE_MINI_PID_PARSER1_CTRL1_PARSER_ALL_PASS_CTRL_PRE_TSIO_DEFAULT 0x00000000
-
-/* XPT_FE :: MINI_PID_PARSER1_CTRL1 :: PARSER_ALL_PASS_CTRL_PRE_MPOD [01:01] */
-#define BCHP_XPT_FE_MINI_PID_PARSER1_CTRL1_PARSER_ALL_PASS_CTRL_PRE_MPOD_MASK 0x00000002
-#define BCHP_XPT_FE_MINI_PID_PARSER1_CTRL1_PARSER_ALL_PASS_CTRL_PRE_MPOD_SHIFT 1
-#define BCHP_XPT_FE_MINI_PID_PARSER1_CTRL1_PARSER_ALL_PASS_CTRL_PRE_MPOD_DEFAULT 0x00000000
-
-/* XPT_FE :: MINI_PID_PARSER1_CTRL1 :: PARSER_ENABLE [00:00] */
-#define BCHP_XPT_FE_MINI_PID_PARSER1_CTRL1_PARSER_ENABLE_MASK 0x00000001
-#define BCHP_XPT_FE_MINI_PID_PARSER1_CTRL1_PARSER_ENABLE_SHIFT 0
-#define BCHP_XPT_FE_MINI_PID_PARSER1_CTRL1_PARSER_ENABLE_DEFAULT 0x00000000
-
-/***************************************************************************
- *MINI_PID_PARSER1_CTRL2 - Data Transport Parser Band 1 Control Register 2
- ***************************************************************************/
-/* XPT_FE :: MINI_PID_PARSER1_CTRL2 :: reserved0 [31:14] */
-#define BCHP_XPT_FE_MINI_PID_PARSER1_CTRL2_reserved0_MASK 0xffffc000
-#define BCHP_XPT_FE_MINI_PID_PARSER1_CTRL2_reserved0_SHIFT 14
-
-/* XPT_FE :: MINI_PID_PARSER1_CTRL2 :: PARSER_STREAM_TIMESTAMP_EN [13:13] */
-#define BCHP_XPT_FE_MINI_PID_PARSER1_CTRL2_PARSER_STREAM_TIMESTAMP_EN_MASK 0x00002000
-#define BCHP_XPT_FE_MINI_PID_PARSER1_CTRL2_PARSER_STREAM_TIMESTAMP_EN_SHIFT 13
-#define BCHP_XPT_FE_MINI_PID_PARSER1_CTRL2_PARSER_STREAM_TIMESTAMP_EN_DEFAULT 0x00000000
-
-/* XPT_FE :: MINI_PID_PARSER1_CTRL2 :: PARSER_TIMESTREAM_BF_SYNC [12:12] */
-#define BCHP_XPT_FE_MINI_PID_PARSER1_CTRL2_PARSER_TIMESTREAM_BF_SYNC_MASK 0x00001000
-#define BCHP_XPT_FE_MINI_PID_PARSER1_CTRL2_PARSER_TIMESTREAM_BF_SYNC_SHIFT 12
-#define BCHP_XPT_FE_MINI_PID_PARSER1_CTRL2_PARSER_TIMESTREAM_BF_SYNC_DEFAULT 0x00000000
-
-/* XPT_FE :: MINI_PID_PARSER1_CTRL2 :: reserved1 [11:11] */
-#define BCHP_XPT_FE_MINI_PID_PARSER1_CTRL2_reserved1_MASK 0x00000800
-#define BCHP_XPT_FE_MINI_PID_PARSER1_CTRL2_reserved1_SHIFT 11
-
-/* XPT_FE :: MINI_PID_PARSER1_CTRL2 :: PARSER_TIMESTAMP_RESTAMP [10:10] */
-#define BCHP_XPT_FE_MINI_PID_PARSER1_CTRL2_PARSER_TIMESTAMP_RESTAMP_MASK 0x00000400
-#define BCHP_XPT_FE_MINI_PID_PARSER1_CTRL2_PARSER_TIMESTAMP_RESTAMP_SHIFT 10
-#define BCHP_XPT_FE_MINI_PID_PARSER1_CTRL2_PARSER_TIMESTAMP_RESTAMP_DEFAULT 0x00000001
-
-/* XPT_FE :: MINI_PID_PARSER1_CTRL2 :: TSIO_MODE_SEL [09:09] */
-#define BCHP_XPT_FE_MINI_PID_PARSER1_CTRL2_TSIO_MODE_SEL_MASK 0x00000200
-#define BCHP_XPT_FE_MINI_PID_PARSER1_CTRL2_TSIO_MODE_SEL_SHIFT 9
-#define BCHP_XPT_FE_MINI_PID_PARSER1_CTRL2_TSIO_MODE_SEL_DEFAULT 0x00000001
-
-/* XPT_FE :: MINI_PID_PARSER1_CTRL2 :: reserved2 [08:07] */
-#define BCHP_XPT_FE_MINI_PID_PARSER1_CTRL2_reserved2_MASK 0x00000180
-#define BCHP_XPT_FE_MINI_PID_PARSER1_CTRL2_reserved2_SHIFT 7
-
-/* XPT_FE :: MINI_PID_PARSER1_CTRL2 :: TSIO_EN [06:06] */
-#define BCHP_XPT_FE_MINI_PID_PARSER1_CTRL2_TSIO_EN_MASK 0x00000040
-#define BCHP_XPT_FE_MINI_PID_PARSER1_CTRL2_TSIO_EN_SHIFT 6
-#define BCHP_XPT_FE_MINI_PID_PARSER1_CTRL2_TSIO_EN_DEFAULT 0x00000000
-
-/* XPT_FE :: MINI_PID_PARSER1_CTRL2 :: reserved3 [05:05] */
-#define BCHP_XPT_FE_MINI_PID_PARSER1_CTRL2_reserved3_MASK 0x00000020
-#define BCHP_XPT_FE_MINI_PID_PARSER1_CTRL2_reserved3_SHIFT 5
-
-/* XPT_FE :: MINI_PID_PARSER1_CTRL2 :: MPOD_MODE_SEL [04:04] */
-#define BCHP_XPT_FE_MINI_PID_PARSER1_CTRL2_MPOD_MODE_SEL_MASK 0x00000010
-#define BCHP_XPT_FE_MINI_PID_PARSER1_CTRL2_MPOD_MODE_SEL_SHIFT 4
-#define BCHP_XPT_FE_MINI_PID_PARSER1_CTRL2_MPOD_MODE_SEL_DEFAULT 0x00000000
-
-/* XPT_FE :: MINI_PID_PARSER1_CTRL2 :: reserved4 [03:03] */
-#define BCHP_XPT_FE_MINI_PID_PARSER1_CTRL2_reserved4_MASK 0x00000008
-#define BCHP_XPT_FE_MINI_PID_PARSER1_CTRL2_reserved4_SHIFT 3
-
-/* XPT_FE :: MINI_PID_PARSER1_CTRL2 :: PARSER_ACCEPT_NULL_PKT_POST_MPOD [02:02] */
-#define BCHP_XPT_FE_MINI_PID_PARSER1_CTRL2_PARSER_ACCEPT_NULL_PKT_POST_MPOD_MASK 0x00000004
-#define BCHP_XPT_FE_MINI_PID_PARSER1_CTRL2_PARSER_ACCEPT_NULL_PKT_POST_MPOD_SHIFT 2
-#define BCHP_XPT_FE_MINI_PID_PARSER1_CTRL2_PARSER_ACCEPT_NULL_PKT_POST_MPOD_DEFAULT 0x00000000
-
-/* XPT_FE :: MINI_PID_PARSER1_CTRL2 :: PARSER_ALL_PASS_CTRL_POST_MPOD [01:01] */
-#define BCHP_XPT_FE_MINI_PID_PARSER1_CTRL2_PARSER_ALL_PASS_CTRL_POST_MPOD_MASK 0x00000002
-#define BCHP_XPT_FE_MINI_PID_PARSER1_CTRL2_PARSER_ALL_PASS_CTRL_POST_MPOD_SHIFT 1
-#define BCHP_XPT_FE_MINI_PID_PARSER1_CTRL2_PARSER_ALL_PASS_CTRL_POST_MPOD_DEFAULT 0x00000000
-
-/* XPT_FE :: MINI_PID_PARSER1_CTRL2 :: MPOD_EN [00:00] */
-#define BCHP_XPT_FE_MINI_PID_PARSER1_CTRL2_MPOD_EN_MASK 0x00000001
-#define BCHP_XPT_FE_MINI_PID_PARSER1_CTRL2_MPOD_EN_SHIFT 0
-#define BCHP_XPT_FE_MINI_PID_PARSER1_CTRL2_MPOD_EN_DEFAULT 0x00000000
-
-/***************************************************************************
- *MINI_PID_PARSER1_ALL_PASS_CTRL - Data Transport Parser Band 1 Control Register
- ***************************************************************************/
-/* XPT_FE :: MINI_PID_PARSER1_ALL_PASS_CTRL :: reserved0 [31:13] */
-#define BCHP_XPT_FE_MINI_PID_PARSER1_ALL_PASS_CTRL_reserved0_MASK 0xffffe000
-#define BCHP_XPT_FE_MINI_PID_PARSER1_ALL_PASS_CTRL_reserved0_SHIFT 13
-
-/* XPT_FE :: MINI_PID_PARSER1_ALL_PASS_CTRL :: PIDP_DEBUG_MODE [12:12] */
-#define BCHP_XPT_FE_MINI_PID_PARSER1_ALL_PASS_CTRL_PIDP_DEBUG_MODE_MASK 0x00001000
-#define BCHP_XPT_FE_MINI_PID_PARSER1_ALL_PASS_CTRL_PIDP_DEBUG_MODE_SHIFT 12
-#define BCHP_XPT_FE_MINI_PID_PARSER1_ALL_PASS_CTRL_PIDP_DEBUG_MODE_DEFAULT 0x00000000
-
-/* XPT_FE :: MINI_PID_PARSER1_ALL_PASS_CTRL :: ALL_PASS_PID_CH_NUM [11:00] */
-#define BCHP_XPT_FE_MINI_PID_PARSER1_ALL_PASS_CTRL_ALL_PASS_PID_CH_NUM_MASK 0x00000fff
-#define BCHP_XPT_FE_MINI_PID_PARSER1_ALL_PASS_CTRL_ALL_PASS_PID_CH_NUM_SHIFT 0
-#define BCHP_XPT_FE_MINI_PID_PARSER1_ALL_PASS_CTRL_ALL_PASS_PID_CH_NUM_DEFAULT 0x00000001
-
-/***************************************************************************
- *MINI_PID_PARSER2_CTRL1 - Data Transport Parser Band 2 Control Register
- ***************************************************************************/
-/* XPT_FE :: MINI_PID_PARSER2_CTRL1 :: reserved0 [31:29] */
-#define BCHP_XPT_FE_MINI_PID_PARSER2_CTRL1_reserved0_MASK 0xe0000000
-#define BCHP_XPT_FE_MINI_PID_PARSER2_CTRL1_reserved0_SHIFT 29
-
-/* XPT_FE :: MINI_PID_PARSER2_CTRL1 :: PARSER_TIMESTAMP_MODE [28:27] */
-#define BCHP_XPT_FE_MINI_PID_PARSER2_CTRL1_PARSER_TIMESTAMP_MODE_MASK 0x18000000
-#define BCHP_XPT_FE_MINI_PID_PARSER2_CTRL1_PARSER_TIMESTAMP_MODE_SHIFT 27
-#define BCHP_XPT_FE_MINI_PID_PARSER2_CTRL1_PARSER_TIMESTAMP_MODE_DEFAULT 0x00000002
-
-/* XPT_FE :: MINI_PID_PARSER2_CTRL1 :: PARSER_TSMF_SEL [26:23] */
-#define BCHP_XPT_FE_MINI_PID_PARSER2_CTRL1_PARSER_TSMF_SEL_MASK 0x07800000
-#define BCHP_XPT_FE_MINI_PID_PARSER2_CTRL1_PARSER_TSMF_SEL_SHIFT 23
-#define BCHP_XPT_FE_MINI_PID_PARSER2_CTRL1_PARSER_TSMF_SEL_DEFAULT 0x00000000
-
-/* XPT_FE :: MINI_PID_PARSER2_CTRL1 :: PARSER_TSMF_EN [22:22] */
-#define BCHP_XPT_FE_MINI_PID_PARSER2_CTRL1_PARSER_TSMF_EN_MASK 0x00400000
-#define BCHP_XPT_FE_MINI_PID_PARSER2_CTRL1_PARSER_TSMF_EN_SHIFT 22
-#define BCHP_XPT_FE_MINI_PID_PARSER2_CTRL1_PARSER_TSMF_EN_DEFAULT 0x00000000
-
-/* XPT_FE :: MINI_PID_PARSER2_CTRL1 :: PARSER_INPUT_SEL_MSB [21:21] */
-#define BCHP_XPT_FE_MINI_PID_PARSER2_CTRL1_PARSER_INPUT_SEL_MSB_MASK 0x00200000
-#define BCHP_XPT_FE_MINI_PID_PARSER2_CTRL1_PARSER_INPUT_SEL_MSB_SHIFT 21
-#define BCHP_XPT_FE_MINI_PID_PARSER2_CTRL1_PARSER_INPUT_SEL_MSB_DEFAULT 0x00000000
-
-/* XPT_FE :: MINI_PID_PARSER2_CTRL1 :: PARSER_ERROR_INPUT_TEI_IGNORE [20:20] */
-#define BCHP_XPT_FE_MINI_PID_PARSER2_CTRL1_PARSER_ERROR_INPUT_TEI_IGNORE_MASK 0x00100000
-#define BCHP_XPT_FE_MINI_PID_PARSER2_CTRL1_PARSER_ERROR_INPUT_TEI_IGNORE_SHIFT 20
-#define BCHP_XPT_FE_MINI_PID_PARSER2_CTRL1_PARSER_ERROR_INPUT_TEI_IGNORE_DEFAULT 0x00000000
-
-/* XPT_FE :: MINI_PID_PARSER2_CTRL1 :: PARSER_PKT_LENGTH [19:12] */
-#define BCHP_XPT_FE_MINI_PID_PARSER2_CTRL1_PARSER_PKT_LENGTH_MASK 0x000ff000
-#define BCHP_XPT_FE_MINI_PID_PARSER2_CTRL1_PARSER_PKT_LENGTH_SHIFT 12
-#define BCHP_XPT_FE_MINI_PID_PARSER2_CTRL1_PARSER_PKT_LENGTH_DEFAULT 0x000000bc
-
-/* XPT_FE :: MINI_PID_PARSER2_CTRL1 :: PARSER_INPUT_SEL [11:08] */
-#define BCHP_XPT_FE_MINI_PID_PARSER2_CTRL1_PARSER_INPUT_SEL_MASK 0x00000f00
-#define BCHP_XPT_FE_MINI_PID_PARSER2_CTRL1_PARSER_INPUT_SEL_SHIFT 8
-#define BCHP_XPT_FE_MINI_PID_PARSER2_CTRL1_PARSER_INPUT_SEL_DEFAULT 0x00000000
-
-/* XPT_FE :: MINI_PID_PARSER2_CTRL1 :: reserved1 [07:07] */
-#define BCHP_XPT_FE_MINI_PID_PARSER2_CTRL1_reserved1_MASK 0x00000080
-#define BCHP_XPT_FE_MINI_PID_PARSER2_CTRL1_reserved1_SHIFT 7
-
-/* XPT_FE :: MINI_PID_PARSER2_CTRL1 :: PARSER_PACKET_TYPE [06:05] */
-#define BCHP_XPT_FE_MINI_PID_PARSER2_CTRL1_PARSER_PACKET_TYPE_MASK 0x00000060
-#define BCHP_XPT_FE_MINI_PID_PARSER2_CTRL1_PARSER_PACKET_TYPE_SHIFT 5
-#define BCHP_XPT_FE_MINI_PID_PARSER2_CTRL1_PARSER_PACKET_TYPE_DEFAULT 0x00000000
-
-/* XPT_FE :: MINI_PID_PARSER2_CTRL1 :: PARSER_ACCEPT_NULL_PKT_PRE_MPOD [04:04] */
-#define BCHP_XPT_FE_MINI_PID_PARSER2_CTRL1_PARSER_ACCEPT_NULL_PKT_PRE_MPOD_MASK 0x00000010
-#define BCHP_XPT_FE_MINI_PID_PARSER2_CTRL1_PARSER_ACCEPT_NULL_PKT_PRE_MPOD_SHIFT 4
-#define BCHP_XPT_FE_MINI_PID_PARSER2_CTRL1_PARSER_ACCEPT_NULL_PKT_PRE_MPOD_DEFAULT 0x00000000
-
-/* XPT_FE :: MINI_PID_PARSER2_CTRL1 :: PARSER_ACCEPT_NULL_PKT_PRE_TSIO [03:03] */
-#define BCHP_XPT_FE_MINI_PID_PARSER2_CTRL1_PARSER_ACCEPT_NULL_PKT_PRE_TSIO_MASK 0x00000008
-#define BCHP_XPT_FE_MINI_PID_PARSER2_CTRL1_PARSER_ACCEPT_NULL_PKT_PRE_TSIO_SHIFT 3
-#define BCHP_XPT_FE_MINI_PID_PARSER2_CTRL1_PARSER_ACCEPT_NULL_PKT_PRE_TSIO_DEFAULT 0x00000000
-
-/* XPT_FE :: MINI_PID_PARSER2_CTRL1 :: PARSER_ALL_PASS_CTRL_PRE_TSIO [02:02] */
-#define BCHP_XPT_FE_MINI_PID_PARSER2_CTRL1_PARSER_ALL_PASS_CTRL_PRE_TSIO_MASK 0x00000004
-#define BCHP_XPT_FE_MINI_PID_PARSER2_CTRL1_PARSER_ALL_PASS_CTRL_PRE_TSIO_SHIFT 2
-#define BCHP_XPT_FE_MINI_PID_PARSER2_CTRL1_PARSER_ALL_PASS_CTRL_PRE_TSIO_DEFAULT 0x00000000
-
-/* XPT_FE :: MINI_PID_PARSER2_CTRL1 :: PARSER_ALL_PASS_CTRL_PRE_MPOD [01:01] */
-#define BCHP_XPT_FE_MINI_PID_PARSER2_CTRL1_PARSER_ALL_PASS_CTRL_PRE_MPOD_MASK 0x00000002
-#define BCHP_XPT_FE_MINI_PID_PARSER2_CTRL1_PARSER_ALL_PASS_CTRL_PRE_MPOD_SHIFT 1
-#define BCHP_XPT_FE_MINI_PID_PARSER2_CTRL1_PARSER_ALL_PASS_CTRL_PRE_MPOD_DEFAULT 0x00000000
-
-/* XPT_FE :: MINI_PID_PARSER2_CTRL1 :: PARSER_ENABLE [00:00] */
-#define BCHP_XPT_FE_MINI_PID_PARSER2_CTRL1_PARSER_ENABLE_MASK 0x00000001
-#define BCHP_XPT_FE_MINI_PID_PARSER2_CTRL1_PARSER_ENABLE_SHIFT 0
-#define BCHP_XPT_FE_MINI_PID_PARSER2_CTRL1_PARSER_ENABLE_DEFAULT 0x00000000
-
-/***************************************************************************
- *MINI_PID_PARSER2_CTRL2 - Data Transport Parser Band 2 Control Register 2
- ***************************************************************************/
-/* XPT_FE :: MINI_PID_PARSER2_CTRL2 :: reserved0 [31:14] */
-#define BCHP_XPT_FE_MINI_PID_PARSER2_CTRL2_reserved0_MASK 0xffffc000
-#define BCHP_XPT_FE_MINI_PID_PARSER2_CTRL2_reserved0_SHIFT 14
-
-/* XPT_FE :: MINI_PID_PARSER2_CTRL2 :: PARSER_STREAM_TIMESTAMP_EN [13:13] */
-#define BCHP_XPT_FE_MINI_PID_PARSER2_CTRL2_PARSER_STREAM_TIMESTAMP_EN_MASK 0x00002000
-#define BCHP_XPT_FE_MINI_PID_PARSER2_CTRL2_PARSER_STREAM_TIMESTAMP_EN_SHIFT 13
-#define BCHP_XPT_FE_MINI_PID_PARSER2_CTRL2_PARSER_STREAM_TIMESTAMP_EN_DEFAULT 0x00000000
-
-/* XPT_FE :: MINI_PID_PARSER2_CTRL2 :: PARSER_TIMESTREAM_BF_SYNC [12:12] */
-#define BCHP_XPT_FE_MINI_PID_PARSER2_CTRL2_PARSER_TIMESTREAM_BF_SYNC_MASK 0x00001000
-#define BCHP_XPT_FE_MINI_PID_PARSER2_CTRL2_PARSER_TIMESTREAM_BF_SYNC_SHIFT 12
-#define BCHP_XPT_FE_MINI_PID_PARSER2_CTRL2_PARSER_TIMESTREAM_BF_SYNC_DEFAULT 0x00000000
-
-/* XPT_FE :: MINI_PID_PARSER2_CTRL2 :: reserved1 [11:11] */
-#define BCHP_XPT_FE_MINI_PID_PARSER2_CTRL2_reserved1_MASK 0x00000800
-#define BCHP_XPT_FE_MINI_PID_PARSER2_CTRL2_reserved1_SHIFT 11
-
-/* XPT_FE :: MINI_PID_PARSER2_CTRL2 :: PARSER_TIMESTAMP_RESTAMP [10:10] */
-#define BCHP_XPT_FE_MINI_PID_PARSER2_CTRL2_PARSER_TIMESTAMP_RESTAMP_MASK 0x00000400
-#define BCHP_XPT_FE_MINI_PID_PARSER2_CTRL2_PARSER_TIMESTAMP_RESTAMP_SHIFT 10
-#define BCHP_XPT_FE_MINI_PID_PARSER2_CTRL2_PARSER_TIMESTAMP_RESTAMP_DEFAULT 0x00000001
-
-/* XPT_FE :: MINI_PID_PARSER2_CTRL2 :: TSIO_MODE_SEL [09:09] */
-#define BCHP_XPT_FE_MINI_PID_PARSER2_CTRL2_TSIO_MODE_SEL_MASK 0x00000200
-#define BCHP_XPT_FE_MINI_PID_PARSER2_CTRL2_TSIO_MODE_SEL_SHIFT 9
-#define BCHP_XPT_FE_MINI_PID_PARSER2_CTRL2_TSIO_MODE_SEL_DEFAULT 0x00000001
-
-/* XPT_FE :: MINI_PID_PARSER2_CTRL2 :: reserved2 [08:07] */
-#define BCHP_XPT_FE_MINI_PID_PARSER2_CTRL2_reserved2_MASK 0x00000180
-#define BCHP_XPT_FE_MINI_PID_PARSER2_CTRL2_reserved2_SHIFT 7
-
-/* XPT_FE :: MINI_PID_PARSER2_CTRL2 :: TSIO_EN [06:06] */
-#define BCHP_XPT_FE_MINI_PID_PARSER2_CTRL2_TSIO_EN_MASK 0x00000040
-#define BCHP_XPT_FE_MINI_PID_PARSER2_CTRL2_TSIO_EN_SHIFT 6
-#define BCHP_XPT_FE_MINI_PID_PARSER2_CTRL2_TSIO_EN_DEFAULT 0x00000000
-
-/* XPT_FE :: MINI_PID_PARSER2_CTRL2 :: reserved3 [05:05] */
-#define BCHP_XPT_FE_MINI_PID_PARSER2_CTRL2_reserved3_MASK 0x00000020
-#define BCHP_XPT_FE_MINI_PID_PARSER2_CTRL2_reserved3_SHIFT 5
-
-/* XPT_FE :: MINI_PID_PARSER2_CTRL2 :: MPOD_MODE_SEL [04:04] */
-#define BCHP_XPT_FE_MINI_PID_PARSER2_CTRL2_MPOD_MODE_SEL_MASK 0x00000010
-#define BCHP_XPT_FE_MINI_PID_PARSER2_CTRL2_MPOD_MODE_SEL_SHIFT 4
-#define BCHP_XPT_FE_MINI_PID_PARSER2_CTRL2_MPOD_MODE_SEL_DEFAULT 0x00000000
-
-/* XPT_FE :: MINI_PID_PARSER2_CTRL2 :: reserved4 [03:03] */
-#define BCHP_XPT_FE_MINI_PID_PARSER2_CTRL2_reserved4_MASK 0x00000008
-#define BCHP_XPT_FE_MINI_PID_PARSER2_CTRL2_reserved4_SHIFT 3
-
-/* XPT_FE :: MINI_PID_PARSER2_CTRL2 :: PARSER_ACCEPT_NULL_PKT_POST_MPOD [02:02] */
-#define BCHP_XPT_FE_MINI_PID_PARSER2_CTRL2_PARSER_ACCEPT_NULL_PKT_POST_MPOD_MASK 0x00000004
-#define BCHP_XPT_FE_MINI_PID_PARSER2_CTRL2_PARSER_ACCEPT_NULL_PKT_POST_MPOD_SHIFT 2
-#define BCHP_XPT_FE_MINI_PID_PARSER2_CTRL2_PARSER_ACCEPT_NULL_PKT_POST_MPOD_DEFAULT 0x00000000
-
-/* XPT_FE :: MINI_PID_PARSER2_CTRL2 :: PARSER_ALL_PASS_CTRL_POST_MPOD [01:01] */
-#define BCHP_XPT_FE_MINI_PID_PARSER2_CTRL2_PARSER_ALL_PASS_CTRL_POST_MPOD_MASK 0x00000002
-#define BCHP_XPT_FE_MINI_PID_PARSER2_CTRL2_PARSER_ALL_PASS_CTRL_POST_MPOD_SHIFT 1
-#define BCHP_XPT_FE_MINI_PID_PARSER2_CTRL2_PARSER_ALL_PASS_CTRL_POST_MPOD_DEFAULT 0x00000000
-
-/* XPT_FE :: MINI_PID_PARSER2_CTRL2 :: MPOD_EN [00:00] */
-#define BCHP_XPT_FE_MINI_PID_PARSER2_CTRL2_MPOD_EN_MASK 0x00000001
-#define BCHP_XPT_FE_MINI_PID_PARSER2_CTRL2_MPOD_EN_SHIFT 0
-#define BCHP_XPT_FE_MINI_PID_PARSER2_CTRL2_MPOD_EN_DEFAULT 0x00000000
-
-/***************************************************************************
- *MINI_PID_PARSER2_ALL_PASS_CTRL - Data Transport Parser Band 2 Control Register
- ***************************************************************************/
-/* XPT_FE :: MINI_PID_PARSER2_ALL_PASS_CTRL :: reserved0 [31:13] */
-#define BCHP_XPT_FE_MINI_PID_PARSER2_ALL_PASS_CTRL_reserved0_MASK 0xffffe000
-#define BCHP_XPT_FE_MINI_PID_PARSER2_ALL_PASS_CTRL_reserved0_SHIFT 13
-
-/* XPT_FE :: MINI_PID_PARSER2_ALL_PASS_CTRL :: PIDP_DEBUG_MODE [12:12] */
-#define BCHP_XPT_FE_MINI_PID_PARSER2_ALL_PASS_CTRL_PIDP_DEBUG_MODE_MASK 0x00001000
-#define BCHP_XPT_FE_MINI_PID_PARSER2_ALL_PASS_CTRL_PIDP_DEBUG_MODE_SHIFT 12
-#define BCHP_XPT_FE_MINI_PID_PARSER2_ALL_PASS_CTRL_PIDP_DEBUG_MODE_DEFAULT 0x00000000
-
-/* XPT_FE :: MINI_PID_PARSER2_ALL_PASS_CTRL :: ALL_PASS_PID_CH_NUM [11:00] */
-#define BCHP_XPT_FE_MINI_PID_PARSER2_ALL_PASS_CTRL_ALL_PASS_PID_CH_NUM_MASK 0x00000fff
-#define BCHP_XPT_FE_MINI_PID_PARSER2_ALL_PASS_CTRL_ALL_PASS_PID_CH_NUM_SHIFT 0
-#define BCHP_XPT_FE_MINI_PID_PARSER2_ALL_PASS_CTRL_ALL_PASS_PID_CH_NUM_DEFAULT 0x00000002
-
-/***************************************************************************
- *MINI_PID_PARSER3_CTRL1 - Data Transport Parser Band 3 Control Register
- ***************************************************************************/
-/* XPT_FE :: MINI_PID_PARSER3_CTRL1 :: reserved0 [31:29] */
-#define BCHP_XPT_FE_MINI_PID_PARSER3_CTRL1_reserved0_MASK 0xe0000000
-#define BCHP_XPT_FE_MINI_PID_PARSER3_CTRL1_reserved0_SHIFT 29
-
-/* XPT_FE :: MINI_PID_PARSER3_CTRL1 :: PARSER_TIMESTAMP_MODE [28:27] */
-#define BCHP_XPT_FE_MINI_PID_PARSER3_CTRL1_PARSER_TIMESTAMP_MODE_MASK 0x18000000
-#define BCHP_XPT_FE_MINI_PID_PARSER3_CTRL1_PARSER_TIMESTAMP_MODE_SHIFT 27
-#define BCHP_XPT_FE_MINI_PID_PARSER3_CTRL1_PARSER_TIMESTAMP_MODE_DEFAULT 0x00000002
-
-/* XPT_FE :: MINI_PID_PARSER3_CTRL1 :: PARSER_TSMF_SEL [26:23] */
-#define BCHP_XPT_FE_MINI_PID_PARSER3_CTRL1_PARSER_TSMF_SEL_MASK 0x07800000
-#define BCHP_XPT_FE_MINI_PID_PARSER3_CTRL1_PARSER_TSMF_SEL_SHIFT 23
-#define BCHP_XPT_FE_MINI_PID_PARSER3_CTRL1_PARSER_TSMF_SEL_DEFAULT 0x00000000
-
-/* XPT_FE :: MINI_PID_PARSER3_CTRL1 :: PARSER_TSMF_EN [22:22] */
-#define BCHP_XPT_FE_MINI_PID_PARSER3_CTRL1_PARSER_TSMF_EN_MASK 0x00400000
-#define BCHP_XPT_FE_MINI_PID_PARSER3_CTRL1_PARSER_TSMF_EN_SHIFT 22
-#define BCHP_XPT_FE_MINI_PID_PARSER3_CTRL1_PARSER_TSMF_EN_DEFAULT 0x00000000
-
-/* XPT_FE :: MINI_PID_PARSER3_CTRL1 :: PARSER_INPUT_SEL_MSB [21:21] */
-#define BCHP_XPT_FE_MINI_PID_PARSER3_CTRL1_PARSER_INPUT_SEL_MSB_MASK 0x00200000
-#define BCHP_XPT_FE_MINI_PID_PARSER3_CTRL1_PARSER_INPUT_SEL_MSB_SHIFT 21
-#define BCHP_XPT_FE_MINI_PID_PARSER3_CTRL1_PARSER_INPUT_SEL_MSB_DEFAULT 0x00000000
-
-/* XPT_FE :: MINI_PID_PARSER3_CTRL1 :: PARSER_ERROR_INPUT_TEI_IGNORE [20:20] */
-#define BCHP_XPT_FE_MINI_PID_PARSER3_CTRL1_PARSER_ERROR_INPUT_TEI_IGNORE_MASK 0x00100000
-#define BCHP_XPT_FE_MINI_PID_PARSER3_CTRL1_PARSER_ERROR_INPUT_TEI_IGNORE_SHIFT 20
-#define BCHP_XPT_FE_MINI_PID_PARSER3_CTRL1_PARSER_ERROR_INPUT_TEI_IGNORE_DEFAULT 0x00000000
-
-/* XPT_FE :: MINI_PID_PARSER3_CTRL1 :: PARSER_PKT_LENGTH [19:12] */
-#define BCHP_XPT_FE_MINI_PID_PARSER3_CTRL1_PARSER_PKT_LENGTH_MASK 0x000ff000
-#define BCHP_XPT_FE_MINI_PID_PARSER3_CTRL1_PARSER_PKT_LENGTH_SHIFT 12
-#define BCHP_XPT_FE_MINI_PID_PARSER3_CTRL1_PARSER_PKT_LENGTH_DEFAULT 0x000000bc
-
-/* XPT_FE :: MINI_PID_PARSER3_CTRL1 :: PARSER_INPUT_SEL [11:08] */
-#define BCHP_XPT_FE_MINI_PID_PARSER3_CTRL1_PARSER_INPUT_SEL_MASK 0x00000f00
-#define BCHP_XPT_FE_MINI_PID_PARSER3_CTRL1_PARSER_INPUT_SEL_SHIFT 8
-#define BCHP_XPT_FE_MINI_PID_PARSER3_CTRL1_PARSER_INPUT_SEL_DEFAULT 0x00000000
-
-/* XPT_FE :: MINI_PID_PARSER3_CTRL1 :: reserved1 [07:07] */
-#define BCHP_XPT_FE_MINI_PID_PARSER3_CTRL1_reserved1_MASK 0x00000080
-#define BCHP_XPT_FE_MINI_PID_PARSER3_CTRL1_reserved1_SHIFT 7
-
-/* XPT_FE :: MINI_PID_PARSER3_CTRL1 :: PARSER_PACKET_TYPE [06:05] */
-#define BCHP_XPT_FE_MINI_PID_PARSER3_CTRL1_PARSER_PACKET_TYPE_MASK 0x00000060
-#define BCHP_XPT_FE_MINI_PID_PARSER3_CTRL1_PARSER_PACKET_TYPE_SHIFT 5
-#define BCHP_XPT_FE_MINI_PID_PARSER3_CTRL1_PARSER_PACKET_TYPE_DEFAULT 0x00000000
-
-/* XPT_FE :: MINI_PID_PARSER3_CTRL1 :: PARSER_ACCEPT_NULL_PKT_PRE_MPOD [04:04] */
-#define BCHP_XPT_FE_MINI_PID_PARSER3_CTRL1_PARSER_ACCEPT_NULL_PKT_PRE_MPOD_MASK 0x00000010
-#define BCHP_XPT_FE_MINI_PID_PARSER3_CTRL1_PARSER_ACCEPT_NULL_PKT_PRE_MPOD_SHIFT 4
-#define BCHP_XPT_FE_MINI_PID_PARSER3_CTRL1_PARSER_ACCEPT_NULL_PKT_PRE_MPOD_DEFAULT 0x00000000
-
-/* XPT_FE :: MINI_PID_PARSER3_CTRL1 :: PARSER_ACCEPT_NULL_PKT_PRE_TSIO [03:03] */
-#define BCHP_XPT_FE_MINI_PID_PARSER3_CTRL1_PARSER_ACCEPT_NULL_PKT_PRE_TSIO_MASK 0x00000008
-#define BCHP_XPT_FE_MINI_PID_PARSER3_CTRL1_PARSER_ACCEPT_NULL_PKT_PRE_TSIO_SHIFT 3
-#define BCHP_XPT_FE_MINI_PID_PARSER3_CTRL1_PARSER_ACCEPT_NULL_PKT_PRE_TSIO_DEFAULT 0x00000000
-
-/* XPT_FE :: MINI_PID_PARSER3_CTRL1 :: PARSER_ALL_PASS_CTRL_PRE_TSIO [02:02] */
-#define BCHP_XPT_FE_MINI_PID_PARSER3_CTRL1_PARSER_ALL_PASS_CTRL_PRE_TSIO_MASK 0x00000004
-#define BCHP_XPT_FE_MINI_PID_PARSER3_CTRL1_PARSER_ALL_PASS_CTRL_PRE_TSIO_SHIFT 2
-#define BCHP_XPT_FE_MINI_PID_PARSER3_CTRL1_PARSER_ALL_PASS_CTRL_PRE_TSIO_DEFAULT 0x00000000
-
-/* XPT_FE :: MINI_PID_PARSER3_CTRL1 :: PARSER_ALL_PASS_CTRL_PRE_MPOD [01:01] */
-#define BCHP_XPT_FE_MINI_PID_PARSER3_CTRL1_PARSER_ALL_PASS_CTRL_PRE_MPOD_MASK 0x00000002
-#define BCHP_XPT_FE_MINI_PID_PARSER3_CTRL1_PARSER_ALL_PASS_CTRL_PRE_MPOD_SHIFT 1
-#define BCHP_XPT_FE_MINI_PID_PARSER3_CTRL1_PARSER_ALL_PASS_CTRL_PRE_MPOD_DEFAULT 0x00000000
-
-/* XPT_FE :: MINI_PID_PARSER3_CTRL1 :: PARSER_ENABLE [00:00] */
-#define BCHP_XPT_FE_MINI_PID_PARSER3_CTRL1_PARSER_ENABLE_MASK 0x00000001
-#define BCHP_XPT_FE_MINI_PID_PARSER3_CTRL1_PARSER_ENABLE_SHIFT 0
-#define BCHP_XPT_FE_MINI_PID_PARSER3_CTRL1_PARSER_ENABLE_DEFAULT 0x00000000
-
-/***************************************************************************
- *MINI_PID_PARSER3_CTRL2 - Data Transport Parser Band 3 Control Register 2
- ***************************************************************************/
-/* XPT_FE :: MINI_PID_PARSER3_CTRL2 :: reserved0 [31:14] */
-#define BCHP_XPT_FE_MINI_PID_PARSER3_CTRL2_reserved0_MASK 0xffffc000
-#define BCHP_XPT_FE_MINI_PID_PARSER3_CTRL2_reserved0_SHIFT 14
-
-/* XPT_FE :: MINI_PID_PARSER3_CTRL2 :: PARSER_STREAM_TIMESTAMP_EN [13:13] */
-#define BCHP_XPT_FE_MINI_PID_PARSER3_CTRL2_PARSER_STREAM_TIMESTAMP_EN_MASK 0x00002000
-#define BCHP_XPT_FE_MINI_PID_PARSER3_CTRL2_PARSER_STREAM_TIMESTAMP_EN_SHIFT 13
-#define BCHP_XPT_FE_MINI_PID_PARSER3_CTRL2_PARSER_STREAM_TIMESTAMP_EN_DEFAULT 0x00000000
-
-/* XPT_FE :: MINI_PID_PARSER3_CTRL2 :: PARSER_TIMESTREAM_BF_SYNC [12:12] */
-#define BCHP_XPT_FE_MINI_PID_PARSER3_CTRL2_PARSER_TIMESTREAM_BF_SYNC_MASK 0x00001000
-#define BCHP_XPT_FE_MINI_PID_PARSER3_CTRL2_PARSER_TIMESTREAM_BF_SYNC_SHIFT 12
-#define BCHP_XPT_FE_MINI_PID_PARSER3_CTRL2_PARSER_TIMESTREAM_BF_SYNC_DEFAULT 0x00000000
-
-/* XPT_FE :: MINI_PID_PARSER3_CTRL2 :: reserved1 [11:11] */
-#define BCHP_XPT_FE_MINI_PID_PARSER3_CTRL2_reserved1_MASK 0x00000800
-#define BCHP_XPT_FE_MINI_PID_PARSER3_CTRL2_reserved1_SHIFT 11
-
-/* XPT_FE :: MINI_PID_PARSER3_CTRL2 :: PARSER_TIMESTAMP_RESTAMP [10:10] */
-#define BCHP_XPT_FE_MINI_PID_PARSER3_CTRL2_PARSER_TIMESTAMP_RESTAMP_MASK 0x00000400
-#define BCHP_XPT_FE_MINI_PID_PARSER3_CTRL2_PARSER_TIMESTAMP_RESTAMP_SHIFT 10
-#define BCHP_XPT_FE_MINI_PID_PARSER3_CTRL2_PARSER_TIMESTAMP_RESTAMP_DEFAULT 0x00000001
-
-/* XPT_FE :: MINI_PID_PARSER3_CTRL2 :: TSIO_MODE_SEL [09:09] */
-#define BCHP_XPT_FE_MINI_PID_PARSER3_CTRL2_TSIO_MODE_SEL_MASK 0x00000200
-#define BCHP_XPT_FE_MINI_PID_PARSER3_CTRL2_TSIO_MODE_SEL_SHIFT 9
-#define BCHP_XPT_FE_MINI_PID_PARSER3_CTRL2_TSIO_MODE_SEL_DEFAULT 0x00000001
-
-/* XPT_FE :: MINI_PID_PARSER3_CTRL2 :: reserved2 [08:07] */
-#define BCHP_XPT_FE_MINI_PID_PARSER3_CTRL2_reserved2_MASK 0x00000180
-#define BCHP_XPT_FE_MINI_PID_PARSER3_CTRL2_reserved2_SHIFT 7
-
-/* XPT_FE :: MINI_PID_PARSER3_CTRL2 :: TSIO_EN [06:06] */
-#define BCHP_XPT_FE_MINI_PID_PARSER3_CTRL2_TSIO_EN_MASK 0x00000040
-#define BCHP_XPT_FE_MINI_PID_PARSER3_CTRL2_TSIO_EN_SHIFT 6
-#define BCHP_XPT_FE_MINI_PID_PARSER3_CTRL2_TSIO_EN_DEFAULT 0x00000000
-
-/* XPT_FE :: MINI_PID_PARSER3_CTRL2 :: reserved3 [05:05] */
-#define BCHP_XPT_FE_MINI_PID_PARSER3_CTRL2_reserved3_MASK 0x00000020
-#define BCHP_XPT_FE_MINI_PID_PARSER3_CTRL2_reserved3_SHIFT 5
-
-/* XPT_FE :: MINI_PID_PARSER3_CTRL2 :: MPOD_MODE_SEL [04:04] */
-#define BCHP_XPT_FE_MINI_PID_PARSER3_CTRL2_MPOD_MODE_SEL_MASK 0x00000010
-#define BCHP_XPT_FE_MINI_PID_PARSER3_CTRL2_MPOD_MODE_SEL_SHIFT 4
-#define BCHP_XPT_FE_MINI_PID_PARSER3_CTRL2_MPOD_MODE_SEL_DEFAULT 0x00000000
-
-/* XPT_FE :: MINI_PID_PARSER3_CTRL2 :: reserved4 [03:03] */
-#define BCHP_XPT_FE_MINI_PID_PARSER3_CTRL2_reserved4_MASK 0x00000008
-#define BCHP_XPT_FE_MINI_PID_PARSER3_CTRL2_reserved4_SHIFT 3
-
-/* XPT_FE :: MINI_PID_PARSER3_CTRL2 :: PARSER_ACCEPT_NULL_PKT_POST_MPOD [02:02] */
-#define BCHP_XPT_FE_MINI_PID_PARSER3_CTRL2_PARSER_ACCEPT_NULL_PKT_POST_MPOD_MASK 0x00000004
-#define BCHP_XPT_FE_MINI_PID_PARSER3_CTRL2_PARSER_ACCEPT_NULL_PKT_POST_MPOD_SHIFT 2
-#define BCHP_XPT_FE_MINI_PID_PARSER3_CTRL2_PARSER_ACCEPT_NULL_PKT_POST_MPOD_DEFAULT 0x00000000
-
-/* XPT_FE :: MINI_PID_PARSER3_CTRL2 :: PARSER_ALL_PASS_CTRL_POST_MPOD [01:01] */
-#define BCHP_XPT_FE_MINI_PID_PARSER3_CTRL2_PARSER_ALL_PASS_CTRL_POST_MPOD_MASK 0x00000002
-#define BCHP_XPT_FE_MINI_PID_PARSER3_CTRL2_PARSER_ALL_PASS_CTRL_POST_MPOD_SHIFT 1
-#define BCHP_XPT_FE_MINI_PID_PARSER3_CTRL2_PARSER_ALL_PASS_CTRL_POST_MPOD_DEFAULT 0x00000000
-
-/* XPT_FE :: MINI_PID_PARSER3_CTRL2 :: MPOD_EN [00:00] */
-#define BCHP_XPT_FE_MINI_PID_PARSER3_CTRL2_MPOD_EN_MASK 0x00000001
-#define BCHP_XPT_FE_MINI_PID_PARSER3_CTRL2_MPOD_EN_SHIFT 0
-#define BCHP_XPT_FE_MINI_PID_PARSER3_CTRL2_MPOD_EN_DEFAULT 0x00000000
-
-/***************************************************************************
- *MINI_PID_PARSER3_ALL_PASS_CTRL - Data Transport Parser Band 3 Control Register
- ***************************************************************************/
-/* XPT_FE :: MINI_PID_PARSER3_ALL_PASS_CTRL :: reserved0 [31:13] */
-#define BCHP_XPT_FE_MINI_PID_PARSER3_ALL_PASS_CTRL_reserved0_MASK 0xffffe000
-#define BCHP_XPT_FE_MINI_PID_PARSER3_ALL_PASS_CTRL_reserved0_SHIFT 13
-
-/* XPT_FE :: MINI_PID_PARSER3_ALL_PASS_CTRL :: PIDP_DEBUG_MODE [12:12] */
-#define BCHP_XPT_FE_MINI_PID_PARSER3_ALL_PASS_CTRL_PIDP_DEBUG_MODE_MASK 0x00001000
-#define BCHP_XPT_FE_MINI_PID_PARSER3_ALL_PASS_CTRL_PIDP_DEBUG_MODE_SHIFT 12
-#define BCHP_XPT_FE_MINI_PID_PARSER3_ALL_PASS_CTRL_PIDP_DEBUG_MODE_DEFAULT 0x00000000
-
-/* XPT_FE :: MINI_PID_PARSER3_ALL_PASS_CTRL :: ALL_PASS_PID_CH_NUM [11:00] */
-#define BCHP_XPT_FE_MINI_PID_PARSER3_ALL_PASS_CTRL_ALL_PASS_PID_CH_NUM_MASK 0x00000fff
-#define BCHP_XPT_FE_MINI_PID_PARSER3_ALL_PASS_CTRL_ALL_PASS_PID_CH_NUM_SHIFT 0
-#define BCHP_XPT_FE_MINI_PID_PARSER3_ALL_PASS_CTRL_ALL_PASS_PID_CH_NUM_DEFAULT 0x00000003
-
-/***************************************************************************
- *MINI_PID_PARSER4_CTRL1 - Data Transport Parser Band 4 Control Register
- ***************************************************************************/
-/* XPT_FE :: MINI_PID_PARSER4_CTRL1 :: reserved0 [31:29] */
-#define BCHP_XPT_FE_MINI_PID_PARSER4_CTRL1_reserved0_MASK 0xe0000000
-#define BCHP_XPT_FE_MINI_PID_PARSER4_CTRL1_reserved0_SHIFT 29
-
-/* XPT_FE :: MINI_PID_PARSER4_CTRL1 :: PARSER_TIMESTAMP_MODE [28:27] */
-#define BCHP_XPT_FE_MINI_PID_PARSER4_CTRL1_PARSER_TIMESTAMP_MODE_MASK 0x18000000
-#define BCHP_XPT_FE_MINI_PID_PARSER4_CTRL1_PARSER_TIMESTAMP_MODE_SHIFT 27
-#define BCHP_XPT_FE_MINI_PID_PARSER4_CTRL1_PARSER_TIMESTAMP_MODE_DEFAULT 0x00000002
-
-/* XPT_FE :: MINI_PID_PARSER4_CTRL1 :: PARSER_TSMF_SEL [26:23] */
-#define BCHP_XPT_FE_MINI_PID_PARSER4_CTRL1_PARSER_TSMF_SEL_MASK 0x07800000
-#define BCHP_XPT_FE_MINI_PID_PARSER4_CTRL1_PARSER_TSMF_SEL_SHIFT 23
-#define BCHP_XPT_FE_MINI_PID_PARSER4_CTRL1_PARSER_TSMF_SEL_DEFAULT 0x00000000
-
-/* XPT_FE :: MINI_PID_PARSER4_CTRL1 :: PARSER_TSMF_EN [22:22] */
-#define BCHP_XPT_FE_MINI_PID_PARSER4_CTRL1_PARSER_TSMF_EN_MASK 0x00400000
-#define BCHP_XPT_FE_MINI_PID_PARSER4_CTRL1_PARSER_TSMF_EN_SHIFT 22
-#define BCHP_XPT_FE_MINI_PID_PARSER4_CTRL1_PARSER_TSMF_EN_DEFAULT 0x00000000
-
-/* XPT_FE :: MINI_PID_PARSER4_CTRL1 :: PARSER_INPUT_SEL_MSB [21:21] */
-#define BCHP_XPT_FE_MINI_PID_PARSER4_CTRL1_PARSER_INPUT_SEL_MSB_MASK 0x00200000
-#define BCHP_XPT_FE_MINI_PID_PARSER4_CTRL1_PARSER_INPUT_SEL_MSB_SHIFT 21
-#define BCHP_XPT_FE_MINI_PID_PARSER4_CTRL1_PARSER_INPUT_SEL_MSB_DEFAULT 0x00000000
-
-/* XPT_FE :: MINI_PID_PARSER4_CTRL1 :: PARSER_ERROR_INPUT_TEI_IGNORE [20:20] */
-#define BCHP_XPT_FE_MINI_PID_PARSER4_CTRL1_PARSER_ERROR_INPUT_TEI_IGNORE_MASK 0x00100000
-#define BCHP_XPT_FE_MINI_PID_PARSER4_CTRL1_PARSER_ERROR_INPUT_TEI_IGNORE_SHIFT 20
-#define BCHP_XPT_FE_MINI_PID_PARSER4_CTRL1_PARSER_ERROR_INPUT_TEI_IGNORE_DEFAULT 0x00000000
-
-/* XPT_FE :: MINI_PID_PARSER4_CTRL1 :: PARSER_PKT_LENGTH [19:12] */
-#define BCHP_XPT_FE_MINI_PID_PARSER4_CTRL1_PARSER_PKT_LENGTH_MASK 0x000ff000
-#define BCHP_XPT_FE_MINI_PID_PARSER4_CTRL1_PARSER_PKT_LENGTH_SHIFT 12
-#define BCHP_XPT_FE_MINI_PID_PARSER4_CTRL1_PARSER_PKT_LENGTH_DEFAULT 0x000000bc
-
-/* XPT_FE :: MINI_PID_PARSER4_CTRL1 :: PARSER_INPUT_SEL [11:08] */
-#define BCHP_XPT_FE_MINI_PID_PARSER4_CTRL1_PARSER_INPUT_SEL_MASK 0x00000f00
-#define BCHP_XPT_FE_MINI_PID_PARSER4_CTRL1_PARSER_INPUT_SEL_SHIFT 8
-#define BCHP_XPT_FE_MINI_PID_PARSER4_CTRL1_PARSER_INPUT_SEL_DEFAULT 0x00000000
-
-/* XPT_FE :: MINI_PID_PARSER4_CTRL1 :: reserved1 [07:07] */
-#define BCHP_XPT_FE_MINI_PID_PARSER4_CTRL1_reserved1_MASK 0x00000080
-#define BCHP_XPT_FE_MINI_PID_PARSER4_CTRL1_reserved1_SHIFT 7
-
-/* XPT_FE :: MINI_PID_PARSER4_CTRL1 :: PARSER_PACKET_TYPE [06:05] */
-#define BCHP_XPT_FE_MINI_PID_PARSER4_CTRL1_PARSER_PACKET_TYPE_MASK 0x00000060
-#define BCHP_XPT_FE_MINI_PID_PARSER4_CTRL1_PARSER_PACKET_TYPE_SHIFT 5
-#define BCHP_XPT_FE_MINI_PID_PARSER4_CTRL1_PARSER_PACKET_TYPE_DEFAULT 0x00000000
-
-/* XPT_FE :: MINI_PID_PARSER4_CTRL1 :: PARSER_ACCEPT_NULL_PKT_PRE_MPOD [04:04] */
-#define BCHP_XPT_FE_MINI_PID_PARSER4_CTRL1_PARSER_ACCEPT_NULL_PKT_PRE_MPOD_MASK 0x00000010
-#define BCHP_XPT_FE_MINI_PID_PARSER4_CTRL1_PARSER_ACCEPT_NULL_PKT_PRE_MPOD_SHIFT 4
-#define BCHP_XPT_FE_MINI_PID_PARSER4_CTRL1_PARSER_ACCEPT_NULL_PKT_PRE_MPOD_DEFAULT 0x00000000
-
-/* XPT_FE :: MINI_PID_PARSER4_CTRL1 :: PARSER_ACCEPT_NULL_PKT_PRE_TSIO [03:03] */
-#define BCHP_XPT_FE_MINI_PID_PARSER4_CTRL1_PARSER_ACCEPT_NULL_PKT_PRE_TSIO_MASK 0x00000008
-#define BCHP_XPT_FE_MINI_PID_PARSER4_CTRL1_PARSER_ACCEPT_NULL_PKT_PRE_TSIO_SHIFT 3
-#define BCHP_XPT_FE_MINI_PID_PARSER4_CTRL1_PARSER_ACCEPT_NULL_PKT_PRE_TSIO_DEFAULT 0x00000000
-
-/* XPT_FE :: MINI_PID_PARSER4_CTRL1 :: PARSER_ALL_PASS_CTRL_PRE_TSIO [02:02] */
-#define BCHP_XPT_FE_MINI_PID_PARSER4_CTRL1_PARSER_ALL_PASS_CTRL_PRE_TSIO_MASK 0x00000004
-#define BCHP_XPT_FE_MINI_PID_PARSER4_CTRL1_PARSER_ALL_PASS_CTRL_PRE_TSIO_SHIFT 2
-#define BCHP_XPT_FE_MINI_PID_PARSER4_CTRL1_PARSER_ALL_PASS_CTRL_PRE_TSIO_DEFAULT 0x00000000
-
-/* XPT_FE :: MINI_PID_PARSER4_CTRL1 :: PARSER_ALL_PASS_CTRL_PRE_MPOD [01:01] */
-#define BCHP_XPT_FE_MINI_PID_PARSER4_CTRL1_PARSER_ALL_PASS_CTRL_PRE_MPOD_MASK 0x00000002
-#define BCHP_XPT_FE_MINI_PID_PARSER4_CTRL1_PARSER_ALL_PASS_CTRL_PRE_MPOD_SHIFT 1
-#define BCHP_XPT_FE_MINI_PID_PARSER4_CTRL1_PARSER_ALL_PASS_CTRL_PRE_MPOD_DEFAULT 0x00000000
-
-/* XPT_FE :: MINI_PID_PARSER4_CTRL1 :: PARSER_ENABLE [00:00] */
-#define BCHP_XPT_FE_MINI_PID_PARSER4_CTRL1_PARSER_ENABLE_MASK 0x00000001
-#define BCHP_XPT_FE_MINI_PID_PARSER4_CTRL1_PARSER_ENABLE_SHIFT 0
-#define BCHP_XPT_FE_MINI_PID_PARSER4_CTRL1_PARSER_ENABLE_DEFAULT 0x00000000
-
-/***************************************************************************
- *MINI_PID_PARSER4_CTRL2 - Data Transport Parser Band 4 Control Register 2
- ***************************************************************************/
-/* XPT_FE :: MINI_PID_PARSER4_CTRL2 :: reserved0 [31:14] */
-#define BCHP_XPT_FE_MINI_PID_PARSER4_CTRL2_reserved0_MASK 0xffffc000
-#define BCHP_XPT_FE_MINI_PID_PARSER4_CTRL2_reserved0_SHIFT 14
-
-/* XPT_FE :: MINI_PID_PARSER4_CTRL2 :: PARSER_STREAM_TIMESTAMP_EN [13:13] */
-#define BCHP_XPT_FE_MINI_PID_PARSER4_CTRL2_PARSER_STREAM_TIMESTAMP_EN_MASK 0x00002000
-#define BCHP_XPT_FE_MINI_PID_PARSER4_CTRL2_PARSER_STREAM_TIMESTAMP_EN_SHIFT 13
-#define BCHP_XPT_FE_MINI_PID_PARSER4_CTRL2_PARSER_STREAM_TIMESTAMP_EN_DEFAULT 0x00000000
-
-/* XPT_FE :: MINI_PID_PARSER4_CTRL2 :: PARSER_TIMESTREAM_BF_SYNC [12:12] */
-#define BCHP_XPT_FE_MINI_PID_PARSER4_CTRL2_PARSER_TIMESTREAM_BF_SYNC_MASK 0x00001000
-#define BCHP_XPT_FE_MINI_PID_PARSER4_CTRL2_PARSER_TIMESTREAM_BF_SYNC_SHIFT 12
-#define BCHP_XPT_FE_MINI_PID_PARSER4_CTRL2_PARSER_TIMESTREAM_BF_SYNC_DEFAULT 0x00000000
-
-/* XPT_FE :: MINI_PID_PARSER4_CTRL2 :: reserved1 [11:11] */
-#define BCHP_XPT_FE_MINI_PID_PARSER4_CTRL2_reserved1_MASK 0x00000800
-#define BCHP_XPT_FE_MINI_PID_PARSER4_CTRL2_reserved1_SHIFT 11
-
-/* XPT_FE :: MINI_PID_PARSER4_CTRL2 :: PARSER_TIMESTAMP_RESTAMP [10:10] */
-#define BCHP_XPT_FE_MINI_PID_PARSER4_CTRL2_PARSER_TIMESTAMP_RESTAMP_MASK 0x00000400
-#define BCHP_XPT_FE_MINI_PID_PARSER4_CTRL2_PARSER_TIMESTAMP_RESTAMP_SHIFT 10
-#define BCHP_XPT_FE_MINI_PID_PARSER4_CTRL2_PARSER_TIMESTAMP_RESTAMP_DEFAULT 0x00000001
-
-/* XPT_FE :: MINI_PID_PARSER4_CTRL2 :: TSIO_MODE_SEL [09:09] */
-#define BCHP_XPT_FE_MINI_PID_PARSER4_CTRL2_TSIO_MODE_SEL_MASK 0x00000200
-#define BCHP_XPT_FE_MINI_PID_PARSER4_CTRL2_TSIO_MODE_SEL_SHIFT 9
-#define BCHP_XPT_FE_MINI_PID_PARSER4_CTRL2_TSIO_MODE_SEL_DEFAULT 0x00000001
-
-/* XPT_FE :: MINI_PID_PARSER4_CTRL2 :: reserved2 [08:07] */
-#define BCHP_XPT_FE_MINI_PID_PARSER4_CTRL2_reserved2_MASK 0x00000180
-#define BCHP_XPT_FE_MINI_PID_PARSER4_CTRL2_reserved2_SHIFT 7
-
-/* XPT_FE :: MINI_PID_PARSER4_CTRL2 :: TSIO_EN [06:06] */
-#define BCHP_XPT_FE_MINI_PID_PARSER4_CTRL2_TSIO_EN_MASK 0x00000040
-#define BCHP_XPT_FE_MINI_PID_PARSER4_CTRL2_TSIO_EN_SHIFT 6
-#define BCHP_XPT_FE_MINI_PID_PARSER4_CTRL2_TSIO_EN_DEFAULT 0x00000000
-
-/* XPT_FE :: MINI_PID_PARSER4_CTRL2 :: reserved3 [05:05] */
-#define BCHP_XPT_FE_MINI_PID_PARSER4_CTRL2_reserved3_MASK 0x00000020
-#define BCHP_XPT_FE_MINI_PID_PARSER4_CTRL2_reserved3_SHIFT 5
-
-/* XPT_FE :: MINI_PID_PARSER4_CTRL2 :: MPOD_MODE_SEL [04:04] */
-#define BCHP_XPT_FE_MINI_PID_PARSER4_CTRL2_MPOD_MODE_SEL_MASK 0x00000010
-#define BCHP_XPT_FE_MINI_PID_PARSER4_CTRL2_MPOD_MODE_SEL_SHIFT 4
-#define BCHP_XPT_FE_MINI_PID_PARSER4_CTRL2_MPOD_MODE_SEL_DEFAULT 0x00000000
-
-/* XPT_FE :: MINI_PID_PARSER4_CTRL2 :: reserved4 [03:03] */
-#define BCHP_XPT_FE_MINI_PID_PARSER4_CTRL2_reserved4_MASK 0x00000008
-#define BCHP_XPT_FE_MINI_PID_PARSER4_CTRL2_reserved4_SHIFT 3
-
-/* XPT_FE :: MINI_PID_PARSER4_CTRL2 :: PARSER_ACCEPT_NULL_PKT_POST_MPOD [02:02] */
-#define BCHP_XPT_FE_MINI_PID_PARSER4_CTRL2_PARSER_ACCEPT_NULL_PKT_POST_MPOD_MASK 0x00000004
-#define BCHP_XPT_FE_MINI_PID_PARSER4_CTRL2_PARSER_ACCEPT_NULL_PKT_POST_MPOD_SHIFT 2
-#define BCHP_XPT_FE_MINI_PID_PARSER4_CTRL2_PARSER_ACCEPT_NULL_PKT_POST_MPOD_DEFAULT 0x00000000
-
-/* XPT_FE :: MINI_PID_PARSER4_CTRL2 :: PARSER_ALL_PASS_CTRL_POST_MPOD [01:01] */
-#define BCHP_XPT_FE_MINI_PID_PARSER4_CTRL2_PARSER_ALL_PASS_CTRL_POST_MPOD_MASK 0x00000002
-#define BCHP_XPT_FE_MINI_PID_PARSER4_CTRL2_PARSER_ALL_PASS_CTRL_POST_MPOD_SHIFT 1
-#define BCHP_XPT_FE_MINI_PID_PARSER4_CTRL2_PARSER_ALL_PASS_CTRL_POST_MPOD_DEFAULT 0x00000000
-
-/* XPT_FE :: MINI_PID_PARSER4_CTRL2 :: MPOD_EN [00:00] */
-#define BCHP_XPT_FE_MINI_PID_PARSER4_CTRL2_MPOD_EN_MASK 0x00000001
-#define BCHP_XPT_FE_MINI_PID_PARSER4_CTRL2_MPOD_EN_SHIFT 0
-#define BCHP_XPT_FE_MINI_PID_PARSER4_CTRL2_MPOD_EN_DEFAULT 0x00000000
-
-/***************************************************************************
- *MINI_PID_PARSER4_ALL_PASS_CTRL - Data Transport Parser Band 4 Control Register
- ***************************************************************************/
-/* XPT_FE :: MINI_PID_PARSER4_ALL_PASS_CTRL :: reserved0 [31:13] */
-#define BCHP_XPT_FE_MINI_PID_PARSER4_ALL_PASS_CTRL_reserved0_MASK 0xffffe000
-#define BCHP_XPT_FE_MINI_PID_PARSER4_ALL_PASS_CTRL_reserved0_SHIFT 13
-
-/* XPT_FE :: MINI_PID_PARSER4_ALL_PASS_CTRL :: PIDP_DEBUG_MODE [12:12] */
-#define BCHP_XPT_FE_MINI_PID_PARSER4_ALL_PASS_CTRL_PIDP_DEBUG_MODE_MASK 0x00001000
-#define BCHP_XPT_FE_MINI_PID_PARSER4_ALL_PASS_CTRL_PIDP_DEBUG_MODE_SHIFT 12
-#define BCHP_XPT_FE_MINI_PID_PARSER4_ALL_PASS_CTRL_PIDP_DEBUG_MODE_DEFAULT 0x00000000
-
-/* XPT_FE :: MINI_PID_PARSER4_ALL_PASS_CTRL :: ALL_PASS_PID_CH_NUM [11:00] */
-#define BCHP_XPT_FE_MINI_PID_PARSER4_ALL_PASS_CTRL_ALL_PASS_PID_CH_NUM_MASK 0x00000fff
-#define BCHP_XPT_FE_MINI_PID_PARSER4_ALL_PASS_CTRL_ALL_PASS_PID_CH_NUM_SHIFT 0
-#define BCHP_XPT_FE_MINI_PID_PARSER4_ALL_PASS_CTRL_ALL_PASS_PID_CH_NUM_DEFAULT 0x00000004
-
-/***************************************************************************
- *MINI_PID_PARSER5_CTRL1 - Data Transport Parser Band 5 Control Register
- ***************************************************************************/
-/* XPT_FE :: MINI_PID_PARSER5_CTRL1 :: reserved0 [31:29] */
-#define BCHP_XPT_FE_MINI_PID_PARSER5_CTRL1_reserved0_MASK 0xe0000000
-#define BCHP_XPT_FE_MINI_PID_PARSER5_CTRL1_reserved0_SHIFT 29
-
-/* XPT_FE :: MINI_PID_PARSER5_CTRL1 :: PARSER_TIMESTAMP_MODE [28:27] */
-#define BCHP_XPT_FE_MINI_PID_PARSER5_CTRL1_PARSER_TIMESTAMP_MODE_MASK 0x18000000
-#define BCHP_XPT_FE_MINI_PID_PARSER5_CTRL1_PARSER_TIMESTAMP_MODE_SHIFT 27
-#define BCHP_XPT_FE_MINI_PID_PARSER5_CTRL1_PARSER_TIMESTAMP_MODE_DEFAULT 0x00000002
-
-/* XPT_FE :: MINI_PID_PARSER5_CTRL1 :: PARSER_TSMF_SEL [26:23] */
-#define BCHP_XPT_FE_MINI_PID_PARSER5_CTRL1_PARSER_TSMF_SEL_MASK 0x07800000
-#define BCHP_XPT_FE_MINI_PID_PARSER5_CTRL1_PARSER_TSMF_SEL_SHIFT 23
-#define BCHP_XPT_FE_MINI_PID_PARSER5_CTRL1_PARSER_TSMF_SEL_DEFAULT 0x00000000
-
-/* XPT_FE :: MINI_PID_PARSER5_CTRL1 :: PARSER_TSMF_EN [22:22] */
-#define BCHP_XPT_FE_MINI_PID_PARSER5_CTRL1_PARSER_TSMF_EN_MASK 0x00400000
-#define BCHP_XPT_FE_MINI_PID_PARSER5_CTRL1_PARSER_TSMF_EN_SHIFT 22
-#define BCHP_XPT_FE_MINI_PID_PARSER5_CTRL1_PARSER_TSMF_EN_DEFAULT 0x00000000
-
-/* XPT_FE :: MINI_PID_PARSER5_CTRL1 :: PARSER_INPUT_SEL_MSB [21:21] */
-#define BCHP_XPT_FE_MINI_PID_PARSER5_CTRL1_PARSER_INPUT_SEL_MSB_MASK 0x00200000
-#define BCHP_XPT_FE_MINI_PID_PARSER5_CTRL1_PARSER_INPUT_SEL_MSB_SHIFT 21
-#define BCHP_XPT_FE_MINI_PID_PARSER5_CTRL1_PARSER_INPUT_SEL_MSB_DEFAULT 0x00000000
-
-/* XPT_FE :: MINI_PID_PARSER5_CTRL1 :: PARSER_ERROR_INPUT_TEI_IGNORE [20:20] */
-#define BCHP_XPT_FE_MINI_PID_PARSER5_CTRL1_PARSER_ERROR_INPUT_TEI_IGNORE_MASK 0x00100000
-#define BCHP_XPT_FE_MINI_PID_PARSER5_CTRL1_PARSER_ERROR_INPUT_TEI_IGNORE_SHIFT 20
-#define BCHP_XPT_FE_MINI_PID_PARSER5_CTRL1_PARSER_ERROR_INPUT_TEI_IGNORE_DEFAULT 0x00000000
-
-/* XPT_FE :: MINI_PID_PARSER5_CTRL1 :: PARSER_PKT_LENGTH [19:12] */
-#define BCHP_XPT_FE_MINI_PID_PARSER5_CTRL1_PARSER_PKT_LENGTH_MASK 0x000ff000
-#define BCHP_XPT_FE_MINI_PID_PARSER5_CTRL1_PARSER_PKT_LENGTH_SHIFT 12
-#define BCHP_XPT_FE_MINI_PID_PARSER5_CTRL1_PARSER_PKT_LENGTH_DEFAULT 0x000000bc
-
-/* XPT_FE :: MINI_PID_PARSER5_CTRL1 :: PARSER_INPUT_SEL [11:08] */
-#define BCHP_XPT_FE_MINI_PID_PARSER5_CTRL1_PARSER_INPUT_SEL_MASK 0x00000f00
-#define BCHP_XPT_FE_MINI_PID_PARSER5_CTRL1_PARSER_INPUT_SEL_SHIFT 8
-#define BCHP_XPT_FE_MINI_PID_PARSER5_CTRL1_PARSER_INPUT_SEL_DEFAULT 0x00000000
-
-/* XPT_FE :: MINI_PID_PARSER5_CTRL1 :: reserved1 [07:07] */
-#define BCHP_XPT_FE_MINI_PID_PARSER5_CTRL1_reserved1_MASK 0x00000080
-#define BCHP_XPT_FE_MINI_PID_PARSER5_CTRL1_reserved1_SHIFT 7
-
-/* XPT_FE :: MINI_PID_PARSER5_CTRL1 :: PARSER_PACKET_TYPE [06:05] */
-#define BCHP_XPT_FE_MINI_PID_PARSER5_CTRL1_PARSER_PACKET_TYPE_MASK 0x00000060
-#define BCHP_XPT_FE_MINI_PID_PARSER5_CTRL1_PARSER_PACKET_TYPE_SHIFT 5
-#define BCHP_XPT_FE_MINI_PID_PARSER5_CTRL1_PARSER_PACKET_TYPE_DEFAULT 0x00000000
-
-/* XPT_FE :: MINI_PID_PARSER5_CTRL1 :: PARSER_ACCEPT_NULL_PKT_PRE_MPOD [04:04] */
-#define BCHP_XPT_FE_MINI_PID_PARSER5_CTRL1_PARSER_ACCEPT_NULL_PKT_PRE_MPOD_MASK 0x00000010
-#define BCHP_XPT_FE_MINI_PID_PARSER5_CTRL1_PARSER_ACCEPT_NULL_PKT_PRE_MPOD_SHIFT 4
-#define BCHP_XPT_FE_MINI_PID_PARSER5_CTRL1_PARSER_ACCEPT_NULL_PKT_PRE_MPOD_DEFAULT 0x00000000
-
-/* XPT_FE :: MINI_PID_PARSER5_CTRL1 :: PARSER_ACCEPT_NULL_PKT_PRE_TSIO [03:03] */
-#define BCHP_XPT_FE_MINI_PID_PARSER5_CTRL1_PARSER_ACCEPT_NULL_PKT_PRE_TSIO_MASK 0x00000008
-#define BCHP_XPT_FE_MINI_PID_PARSER5_CTRL1_PARSER_ACCEPT_NULL_PKT_PRE_TSIO_SHIFT 3
-#define BCHP_XPT_FE_MINI_PID_PARSER5_CTRL1_PARSER_ACCEPT_NULL_PKT_PRE_TSIO_DEFAULT 0x00000000
-
-/* XPT_FE :: MINI_PID_PARSER5_CTRL1 :: PARSER_ALL_PASS_CTRL_PRE_TSIO [02:02] */
-#define BCHP_XPT_FE_MINI_PID_PARSER5_CTRL1_PARSER_ALL_PASS_CTRL_PRE_TSIO_MASK 0x00000004
-#define BCHP_XPT_FE_MINI_PID_PARSER5_CTRL1_PARSER_ALL_PASS_CTRL_PRE_TSIO_SHIFT 2
-#define BCHP_XPT_FE_MINI_PID_PARSER5_CTRL1_PARSER_ALL_PASS_CTRL_PRE_TSIO_DEFAULT 0x00000000
-
-/* XPT_FE :: MINI_PID_PARSER5_CTRL1 :: PARSER_ALL_PASS_CTRL_PRE_MPOD [01:01] */
-#define BCHP_XPT_FE_MINI_PID_PARSER5_CTRL1_PARSER_ALL_PASS_CTRL_PRE_MPOD_MASK 0x00000002
-#define BCHP_XPT_FE_MINI_PID_PARSER5_CTRL1_PARSER_ALL_PASS_CTRL_PRE_MPOD_SHIFT 1
-#define BCHP_XPT_FE_MINI_PID_PARSER5_CTRL1_PARSER_ALL_PASS_CTRL_PRE_MPOD_DEFAULT 0x00000000
-
-/* XPT_FE :: MINI_PID_PARSER5_CTRL1 :: PARSER_ENABLE [00:00] */
-#define BCHP_XPT_FE_MINI_PID_PARSER5_CTRL1_PARSER_ENABLE_MASK 0x00000001
-#define BCHP_XPT_FE_MINI_PID_PARSER5_CTRL1_PARSER_ENABLE_SHIFT 0
-#define BCHP_XPT_FE_MINI_PID_PARSER5_CTRL1_PARSER_ENABLE_DEFAULT 0x00000000
-
-/***************************************************************************
- *MINI_PID_PARSER5_CTRL2 - Data Transport Parser Band 5 Control Register 2
- ***************************************************************************/
-/* XPT_FE :: MINI_PID_PARSER5_CTRL2 :: reserved0 [31:14] */
-#define BCHP_XPT_FE_MINI_PID_PARSER5_CTRL2_reserved0_MASK 0xffffc000
-#define BCHP_XPT_FE_MINI_PID_PARSER5_CTRL2_reserved0_SHIFT 14
-
-/* XPT_FE :: MINI_PID_PARSER5_CTRL2 :: PARSER_STREAM_TIMESTAMP_EN [13:13] */
-#define BCHP_XPT_FE_MINI_PID_PARSER5_CTRL2_PARSER_STREAM_TIMESTAMP_EN_MASK 0x00002000
-#define BCHP_XPT_FE_MINI_PID_PARSER5_CTRL2_PARSER_STREAM_TIMESTAMP_EN_SHIFT 13
-#define BCHP_XPT_FE_MINI_PID_PARSER5_CTRL2_PARSER_STREAM_TIMESTAMP_EN_DEFAULT 0x00000000
-
-/* XPT_FE :: MINI_PID_PARSER5_CTRL2 :: PARSER_TIMESTREAM_BF_SYNC [12:12] */
-#define BCHP_XPT_FE_MINI_PID_PARSER5_CTRL2_PARSER_TIMESTREAM_BF_SYNC_MASK 0x00001000
-#define BCHP_XPT_FE_MINI_PID_PARSER5_CTRL2_PARSER_TIMESTREAM_BF_SYNC_SHIFT 12
-#define BCHP_XPT_FE_MINI_PID_PARSER5_CTRL2_PARSER_TIMESTREAM_BF_SYNC_DEFAULT 0x00000000
-
-/* XPT_FE :: MINI_PID_PARSER5_CTRL2 :: reserved1 [11:11] */
-#define BCHP_XPT_FE_MINI_PID_PARSER5_CTRL2_reserved1_MASK 0x00000800
-#define BCHP_XPT_FE_MINI_PID_PARSER5_CTRL2_reserved1_SHIFT 11
-
-/* XPT_FE :: MINI_PID_PARSER5_CTRL2 :: PARSER_TIMESTAMP_RESTAMP [10:10] */
-#define BCHP_XPT_FE_MINI_PID_PARSER5_CTRL2_PARSER_TIMESTAMP_RESTAMP_MASK 0x00000400
-#define BCHP_XPT_FE_MINI_PID_PARSER5_CTRL2_PARSER_TIMESTAMP_RESTAMP_SHIFT 10
-#define BCHP_XPT_FE_MINI_PID_PARSER5_CTRL2_PARSER_TIMESTAMP_RESTAMP_DEFAULT 0x00000001
-
-/* XPT_FE :: MINI_PID_PARSER5_CTRL2 :: TSIO_MODE_SEL [09:09] */
-#define BCHP_XPT_FE_MINI_PID_PARSER5_CTRL2_TSIO_MODE_SEL_MASK 0x00000200
-#define BCHP_XPT_FE_MINI_PID_PARSER5_CTRL2_TSIO_MODE_SEL_SHIFT 9
-#define BCHP_XPT_FE_MINI_PID_PARSER5_CTRL2_TSIO_MODE_SEL_DEFAULT 0x00000001
-
-/* XPT_FE :: MINI_PID_PARSER5_CTRL2 :: reserved2 [08:07] */
-#define BCHP_XPT_FE_MINI_PID_PARSER5_CTRL2_reserved2_MASK 0x00000180
-#define BCHP_XPT_FE_MINI_PID_PARSER5_CTRL2_reserved2_SHIFT 7
-
-/* XPT_FE :: MINI_PID_PARSER5_CTRL2 :: TSIO_EN [06:06] */
-#define BCHP_XPT_FE_MINI_PID_PARSER5_CTRL2_TSIO_EN_MASK 0x00000040
-#define BCHP_XPT_FE_MINI_PID_PARSER5_CTRL2_TSIO_EN_SHIFT 6
-#define BCHP_XPT_FE_MINI_PID_PARSER5_CTRL2_TSIO_EN_DEFAULT 0x00000000
-
-/* XPT_FE :: MINI_PID_PARSER5_CTRL2 :: reserved3 [05:05] */
-#define BCHP_XPT_FE_MINI_PID_PARSER5_CTRL2_reserved3_MASK 0x00000020
-#define BCHP_XPT_FE_MINI_PID_PARSER5_CTRL2_reserved3_SHIFT 5
-
-/* XPT_FE :: MINI_PID_PARSER5_CTRL2 :: MPOD_MODE_SEL [04:04] */
-#define BCHP_XPT_FE_MINI_PID_PARSER5_CTRL2_MPOD_MODE_SEL_MASK 0x00000010
-#define BCHP_XPT_FE_MINI_PID_PARSER5_CTRL2_MPOD_MODE_SEL_SHIFT 4
-#define BCHP_XPT_FE_MINI_PID_PARSER5_CTRL2_MPOD_MODE_SEL_DEFAULT 0x00000000
-
-/* XPT_FE :: MINI_PID_PARSER5_CTRL2 :: reserved4 [03:03] */
-#define BCHP_XPT_FE_MINI_PID_PARSER5_CTRL2_reserved4_MASK 0x00000008
-#define BCHP_XPT_FE_MINI_PID_PARSER5_CTRL2_reserved4_SHIFT 3
-
-/* XPT_FE :: MINI_PID_PARSER5_CTRL2 :: PARSER_ACCEPT_NULL_PKT_POST_MPOD [02:02] */
-#define BCHP_XPT_FE_MINI_PID_PARSER5_CTRL2_PARSER_ACCEPT_NULL_PKT_POST_MPOD_MASK 0x00000004
-#define BCHP_XPT_FE_MINI_PID_PARSER5_CTRL2_PARSER_ACCEPT_NULL_PKT_POST_MPOD_SHIFT 2
-#define BCHP_XPT_FE_MINI_PID_PARSER5_CTRL2_PARSER_ACCEPT_NULL_PKT_POST_MPOD_DEFAULT 0x00000000
-
-/* XPT_FE :: MINI_PID_PARSER5_CTRL2 :: PARSER_ALL_PASS_CTRL_POST_MPOD [01:01] */
-#define BCHP_XPT_FE_MINI_PID_PARSER5_CTRL2_PARSER_ALL_PASS_CTRL_POST_MPOD_MASK 0x00000002
-#define BCHP_XPT_FE_MINI_PID_PARSER5_CTRL2_PARSER_ALL_PASS_CTRL_POST_MPOD_SHIFT 1
-#define BCHP_XPT_FE_MINI_PID_PARSER5_CTRL2_PARSER_ALL_PASS_CTRL_POST_MPOD_DEFAULT 0x00000000
-
-/* XPT_FE :: MINI_PID_PARSER5_CTRL2 :: MPOD_EN [00:00] */
-#define BCHP_XPT_FE_MINI_PID_PARSER5_CTRL2_MPOD_EN_MASK 0x00000001
-#define BCHP_XPT_FE_MINI_PID_PARSER5_CTRL2_MPOD_EN_SHIFT 0
-#define BCHP_XPT_FE_MINI_PID_PARSER5_CTRL2_MPOD_EN_DEFAULT 0x00000000
-
-/***************************************************************************
- *MINI_PID_PARSER5_ALL_PASS_CTRL - Data Transport Parser Band 5 Control Register
- ***************************************************************************/
-/* XPT_FE :: MINI_PID_PARSER5_ALL_PASS_CTRL :: reserved0 [31:13] */
-#define BCHP_XPT_FE_MINI_PID_PARSER5_ALL_PASS_CTRL_reserved0_MASK 0xffffe000
-#define BCHP_XPT_FE_MINI_PID_PARSER5_ALL_PASS_CTRL_reserved0_SHIFT 13
-
-/* XPT_FE :: MINI_PID_PARSER5_ALL_PASS_CTRL :: PIDP_DEBUG_MODE [12:12] */
-#define BCHP_XPT_FE_MINI_PID_PARSER5_ALL_PASS_CTRL_PIDP_DEBUG_MODE_MASK 0x00001000
-#define BCHP_XPT_FE_MINI_PID_PARSER5_ALL_PASS_CTRL_PIDP_DEBUG_MODE_SHIFT 12
-#define BCHP_XPT_FE_MINI_PID_PARSER5_ALL_PASS_CTRL_PIDP_DEBUG_MODE_DEFAULT 0x00000000
-
-/* XPT_FE :: MINI_PID_PARSER5_ALL_PASS_CTRL :: ALL_PASS_PID_CH_NUM [11:00] */
-#define BCHP_XPT_FE_MINI_PID_PARSER5_ALL_PASS_CTRL_ALL_PASS_PID_CH_NUM_MASK 0x00000fff
-#define BCHP_XPT_FE_MINI_PID_PARSER5_ALL_PASS_CTRL_ALL_PASS_PID_CH_NUM_SHIFT 0
-#define BCHP_XPT_FE_MINI_PID_PARSER5_ALL_PASS_CTRL_ALL_PASS_PID_CH_NUM_DEFAULT 0x00000005
-
-/***************************************************************************
- *MINI_PID_PARSER6_CTRL1 - Data Transport Parser Band 6 Control Register
- ***************************************************************************/
-/* XPT_FE :: MINI_PID_PARSER6_CTRL1 :: reserved0 [31:29] */
-#define BCHP_XPT_FE_MINI_PID_PARSER6_CTRL1_reserved0_MASK 0xe0000000
-#define BCHP_XPT_FE_MINI_PID_PARSER6_CTRL1_reserved0_SHIFT 29
-
-/* XPT_FE :: MINI_PID_PARSER6_CTRL1 :: PARSER_TIMESTAMP_MODE [28:27] */
-#define BCHP_XPT_FE_MINI_PID_PARSER6_CTRL1_PARSER_TIMESTAMP_MODE_MASK 0x18000000
-#define BCHP_XPT_FE_MINI_PID_PARSER6_CTRL1_PARSER_TIMESTAMP_MODE_SHIFT 27
-#define BCHP_XPT_FE_MINI_PID_PARSER6_CTRL1_PARSER_TIMESTAMP_MODE_DEFAULT 0x00000002
-
-/* XPT_FE :: MINI_PID_PARSER6_CTRL1 :: PARSER_TSMF_SEL [26:23] */
-#define BCHP_XPT_FE_MINI_PID_PARSER6_CTRL1_PARSER_TSMF_SEL_MASK 0x07800000
-#define BCHP_XPT_FE_MINI_PID_PARSER6_CTRL1_PARSER_TSMF_SEL_SHIFT 23
-#define BCHP_XPT_FE_MINI_PID_PARSER6_CTRL1_PARSER_TSMF_SEL_DEFAULT 0x00000000
-
-/* XPT_FE :: MINI_PID_PARSER6_CTRL1 :: PARSER_TSMF_EN [22:22] */
-#define BCHP_XPT_FE_MINI_PID_PARSER6_CTRL1_PARSER_TSMF_EN_MASK 0x00400000
-#define BCHP_XPT_FE_MINI_PID_PARSER6_CTRL1_PARSER_TSMF_EN_SHIFT 22
-#define BCHP_XPT_FE_MINI_PID_PARSER6_CTRL1_PARSER_TSMF_EN_DEFAULT 0x00000000
-
-/* XPT_FE :: MINI_PID_PARSER6_CTRL1 :: PARSER_INPUT_SEL_MSB [21:21] */
-#define BCHP_XPT_FE_MINI_PID_PARSER6_CTRL1_PARSER_INPUT_SEL_MSB_MASK 0x00200000
-#define BCHP_XPT_FE_MINI_PID_PARSER6_CTRL1_PARSER_INPUT_SEL_MSB_SHIFT 21
-#define BCHP_XPT_FE_MINI_PID_PARSER6_CTRL1_PARSER_INPUT_SEL_MSB_DEFAULT 0x00000000
-
-/* XPT_FE :: MINI_PID_PARSER6_CTRL1 :: PARSER_ERROR_INPUT_TEI_IGNORE [20:20] */
-#define BCHP_XPT_FE_MINI_PID_PARSER6_CTRL1_PARSER_ERROR_INPUT_TEI_IGNORE_MASK 0x00100000
-#define BCHP_XPT_FE_MINI_PID_PARSER6_CTRL1_PARSER_ERROR_INPUT_TEI_IGNORE_SHIFT 20
-#define BCHP_XPT_FE_MINI_PID_PARSER6_CTRL1_PARSER_ERROR_INPUT_TEI_IGNORE_DEFAULT 0x00000000
-
-/* XPT_FE :: MINI_PID_PARSER6_CTRL1 :: PARSER_PKT_LENGTH [19:12] */
-#define BCHP_XPT_FE_MINI_PID_PARSER6_CTRL1_PARSER_PKT_LENGTH_MASK 0x000ff000
-#define BCHP_XPT_FE_MINI_PID_PARSER6_CTRL1_PARSER_PKT_LENGTH_SHIFT 12
-#define BCHP_XPT_FE_MINI_PID_PARSER6_CTRL1_PARSER_PKT_LENGTH_DEFAULT 0x000000bc
-
-/* XPT_FE :: MINI_PID_PARSER6_CTRL1 :: PARSER_INPUT_SEL [11:08] */
-#define BCHP_XPT_FE_MINI_PID_PARSER6_CTRL1_PARSER_INPUT_SEL_MASK 0x00000f00
-#define BCHP_XPT_FE_MINI_PID_PARSER6_CTRL1_PARSER_INPUT_SEL_SHIFT 8
-#define BCHP_XPT_FE_MINI_PID_PARSER6_CTRL1_PARSER_INPUT_SEL_DEFAULT 0x00000000
-
-/* XPT_FE :: MINI_PID_PARSER6_CTRL1 :: reserved1 [07:07] */
-#define BCHP_XPT_FE_MINI_PID_PARSER6_CTRL1_reserved1_MASK 0x00000080
-#define BCHP_XPT_FE_MINI_PID_PARSER6_CTRL1_reserved1_SHIFT 7
-
-/* XPT_FE :: MINI_PID_PARSER6_CTRL1 :: PARSER_PACKET_TYPE [06:05] */
-#define BCHP_XPT_FE_MINI_PID_PARSER6_CTRL1_PARSER_PACKET_TYPE_MASK 0x00000060
-#define BCHP_XPT_FE_MINI_PID_PARSER6_CTRL1_PARSER_PACKET_TYPE_SHIFT 5
-#define BCHP_XPT_FE_MINI_PID_PARSER6_CTRL1_PARSER_PACKET_TYPE_DEFAULT 0x00000000
-
-/* XPT_FE :: MINI_PID_PARSER6_CTRL1 :: PARSER_ACCEPT_NULL_PKT_PRE_MPOD [04:04] */
-#define BCHP_XPT_FE_MINI_PID_PARSER6_CTRL1_PARSER_ACCEPT_NULL_PKT_PRE_MPOD_MASK 0x00000010
-#define BCHP_XPT_FE_MINI_PID_PARSER6_CTRL1_PARSER_ACCEPT_NULL_PKT_PRE_MPOD_SHIFT 4
-#define BCHP_XPT_FE_MINI_PID_PARSER6_CTRL1_PARSER_ACCEPT_NULL_PKT_PRE_MPOD_DEFAULT 0x00000000
-
-/* XPT_FE :: MINI_PID_PARSER6_CTRL1 :: PARSER_ACCEPT_NULL_PKT_PRE_TSIO [03:03] */
-#define BCHP_XPT_FE_MINI_PID_PARSER6_CTRL1_PARSER_ACCEPT_NULL_PKT_PRE_TSIO_MASK 0x00000008
-#define BCHP_XPT_FE_MINI_PID_PARSER6_CTRL1_PARSER_ACCEPT_NULL_PKT_PRE_TSIO_SHIFT 3
-#define BCHP_XPT_FE_MINI_PID_PARSER6_CTRL1_PARSER_ACCEPT_NULL_PKT_PRE_TSIO_DEFAULT 0x00000000
-
-/* XPT_FE :: MINI_PID_PARSER6_CTRL1 :: PARSER_ALL_PASS_CTRL_PRE_TSIO [02:02] */
-#define BCHP_XPT_FE_MINI_PID_PARSER6_CTRL1_PARSER_ALL_PASS_CTRL_PRE_TSIO_MASK 0x00000004
-#define BCHP_XPT_FE_MINI_PID_PARSER6_CTRL1_PARSER_ALL_PASS_CTRL_PRE_TSIO_SHIFT 2
-#define BCHP_XPT_FE_MINI_PID_PARSER6_CTRL1_PARSER_ALL_PASS_CTRL_PRE_TSIO_DEFAULT 0x00000000
-
-/* XPT_FE :: MINI_PID_PARSER6_CTRL1 :: PARSER_ALL_PASS_CTRL_PRE_MPOD [01:01] */
-#define BCHP_XPT_FE_MINI_PID_PARSER6_CTRL1_PARSER_ALL_PASS_CTRL_PRE_MPOD_MASK 0x00000002
-#define BCHP_XPT_FE_MINI_PID_PARSER6_CTRL1_PARSER_ALL_PASS_CTRL_PRE_MPOD_SHIFT 1
-#define BCHP_XPT_FE_MINI_PID_PARSER6_CTRL1_PARSER_ALL_PASS_CTRL_PRE_MPOD_DEFAULT 0x00000000
-
-/* XPT_FE :: MINI_PID_PARSER6_CTRL1 :: PARSER_ENABLE [00:00] */
-#define BCHP_XPT_FE_MINI_PID_PARSER6_CTRL1_PARSER_ENABLE_MASK 0x00000001
-#define BCHP_XPT_FE_MINI_PID_PARSER6_CTRL1_PARSER_ENABLE_SHIFT 0
-#define BCHP_XPT_FE_MINI_PID_PARSER6_CTRL1_PARSER_ENABLE_DEFAULT 0x00000000
-
-/***************************************************************************
- *MINI_PID_PARSER6_CTRL2 - Data Transport Parser Band 6 Control Register 2
- ***************************************************************************/
-/* XPT_FE :: MINI_PID_PARSER6_CTRL2 :: reserved0 [31:14] */
-#define BCHP_XPT_FE_MINI_PID_PARSER6_CTRL2_reserved0_MASK 0xffffc000
-#define BCHP_XPT_FE_MINI_PID_PARSER6_CTRL2_reserved0_SHIFT 14
-
-/* XPT_FE :: MINI_PID_PARSER6_CTRL2 :: PARSER_STREAM_TIMESTAMP_EN [13:13] */
-#define BCHP_XPT_FE_MINI_PID_PARSER6_CTRL2_PARSER_STREAM_TIMESTAMP_EN_MASK 0x00002000
-#define BCHP_XPT_FE_MINI_PID_PARSER6_CTRL2_PARSER_STREAM_TIMESTAMP_EN_SHIFT 13
-#define BCHP_XPT_FE_MINI_PID_PARSER6_CTRL2_PARSER_STREAM_TIMESTAMP_EN_DEFAULT 0x00000000
-
-/* XPT_FE :: MINI_PID_PARSER6_CTRL2 :: PARSER_TIMESTREAM_BF_SYNC [12:12] */
-#define BCHP_XPT_FE_MINI_PID_PARSER6_CTRL2_PARSER_TIMESTREAM_BF_SYNC_MASK 0x00001000
-#define BCHP_XPT_FE_MINI_PID_PARSER6_CTRL2_PARSER_TIMESTREAM_BF_SYNC_SHIFT 12
-#define BCHP_XPT_FE_MINI_PID_PARSER6_CTRL2_PARSER_TIMESTREAM_BF_SYNC_DEFAULT 0x00000000
-
-/* XPT_FE :: MINI_PID_PARSER6_CTRL2 :: reserved1 [11:11] */
-#define BCHP_XPT_FE_MINI_PID_PARSER6_CTRL2_reserved1_MASK 0x00000800
-#define BCHP_XPT_FE_MINI_PID_PARSER6_CTRL2_reserved1_SHIFT 11
-
-/* XPT_FE :: MINI_PID_PARSER6_CTRL2 :: PARSER_TIMESTAMP_RESTAMP [10:10] */
-#define BCHP_XPT_FE_MINI_PID_PARSER6_CTRL2_PARSER_TIMESTAMP_RESTAMP_MASK 0x00000400
-#define BCHP_XPT_FE_MINI_PID_PARSER6_CTRL2_PARSER_TIMESTAMP_RESTAMP_SHIFT 10
-#define BCHP_XPT_FE_MINI_PID_PARSER6_CTRL2_PARSER_TIMESTAMP_RESTAMP_DEFAULT 0x00000001
-
-/* XPT_FE :: MINI_PID_PARSER6_CTRL2 :: TSIO_MODE_SEL [09:09] */
-#define BCHP_XPT_FE_MINI_PID_PARSER6_CTRL2_TSIO_MODE_SEL_MASK 0x00000200
-#define BCHP_XPT_FE_MINI_PID_PARSER6_CTRL2_TSIO_MODE_SEL_SHIFT 9
-#define BCHP_XPT_FE_MINI_PID_PARSER6_CTRL2_TSIO_MODE_SEL_DEFAULT 0x00000001
-
-/* XPT_FE :: MINI_PID_PARSER6_CTRL2 :: reserved2 [08:07] */
-#define BCHP_XPT_FE_MINI_PID_PARSER6_CTRL2_reserved2_MASK 0x00000180
-#define BCHP_XPT_FE_MINI_PID_PARSER6_CTRL2_reserved2_SHIFT 7
-
-/* XPT_FE :: MINI_PID_PARSER6_CTRL2 :: TSIO_EN [06:06] */
-#define BCHP_XPT_FE_MINI_PID_PARSER6_CTRL2_TSIO_EN_MASK 0x00000040
-#define BCHP_XPT_FE_MINI_PID_PARSER6_CTRL2_TSIO_EN_SHIFT 6
-#define BCHP_XPT_FE_MINI_PID_PARSER6_CTRL2_TSIO_EN_DEFAULT 0x00000000
-
-/* XPT_FE :: MINI_PID_PARSER6_CTRL2 :: reserved3 [05:05] */
-#define BCHP_XPT_FE_MINI_PID_PARSER6_CTRL2_reserved3_MASK 0x00000020
-#define BCHP_XPT_FE_MINI_PID_PARSER6_CTRL2_reserved3_SHIFT 5
-
-/* XPT_FE :: MINI_PID_PARSER6_CTRL2 :: MPOD_MODE_SEL [04:04] */
-#define BCHP_XPT_FE_MINI_PID_PARSER6_CTRL2_MPOD_MODE_SEL_MASK 0x00000010
-#define BCHP_XPT_FE_MINI_PID_PARSER6_CTRL2_MPOD_MODE_SEL_SHIFT 4
-#define BCHP_XPT_FE_MINI_PID_PARSER6_CTRL2_MPOD_MODE_SEL_DEFAULT 0x00000000
-
-/* XPT_FE :: MINI_PID_PARSER6_CTRL2 :: reserved4 [03:03] */
-#define BCHP_XPT_FE_MINI_PID_PARSER6_CTRL2_reserved4_MASK 0x00000008
-#define BCHP_XPT_FE_MINI_PID_PARSER6_CTRL2_reserved4_SHIFT 3
-
-/* XPT_FE :: MINI_PID_PARSER6_CTRL2 :: PARSER_ACCEPT_NULL_PKT_POST_MPOD [02:02] */
-#define BCHP_XPT_FE_MINI_PID_PARSER6_CTRL2_PARSER_ACCEPT_NULL_PKT_POST_MPOD_MASK 0x00000004
-#define BCHP_XPT_FE_MINI_PID_PARSER6_CTRL2_PARSER_ACCEPT_NULL_PKT_POST_MPOD_SHIFT 2
-#define BCHP_XPT_FE_MINI_PID_PARSER6_CTRL2_PARSER_ACCEPT_NULL_PKT_POST_MPOD_DEFAULT 0x00000000
-
-/* XPT_FE :: MINI_PID_PARSER6_CTRL2 :: PARSER_ALL_PASS_CTRL_POST_MPOD [01:01] */
-#define BCHP_XPT_FE_MINI_PID_PARSER6_CTRL2_PARSER_ALL_PASS_CTRL_POST_MPOD_MASK 0x00000002
-#define BCHP_XPT_FE_MINI_PID_PARSER6_CTRL2_PARSER_ALL_PASS_CTRL_POST_MPOD_SHIFT 1
-#define BCHP_XPT_FE_MINI_PID_PARSER6_CTRL2_PARSER_ALL_PASS_CTRL_POST_MPOD_DEFAULT 0x00000000
-
-/* XPT_FE :: MINI_PID_PARSER6_CTRL2 :: MPOD_EN [00:00] */
-#define BCHP_XPT_FE_MINI_PID_PARSER6_CTRL2_MPOD_EN_MASK 0x00000001
-#define BCHP_XPT_FE_MINI_PID_PARSER6_CTRL2_MPOD_EN_SHIFT 0
-#define BCHP_XPT_FE_MINI_PID_PARSER6_CTRL2_MPOD_EN_DEFAULT 0x00000000
-
-/***************************************************************************
- *MINI_PID_PARSER6_ALL_PASS_CTRL - Data Transport Parser Band 6 Control Register
- ***************************************************************************/
-/* XPT_FE :: MINI_PID_PARSER6_ALL_PASS_CTRL :: reserved0 [31:13] */
-#define BCHP_XPT_FE_MINI_PID_PARSER6_ALL_PASS_CTRL_reserved0_MASK 0xffffe000
-#define BCHP_XPT_FE_MINI_PID_PARSER6_ALL_PASS_CTRL_reserved0_SHIFT 13
-
-/* XPT_FE :: MINI_PID_PARSER6_ALL_PASS_CTRL :: PIDP_DEBUG_MODE [12:12] */
-#define BCHP_XPT_FE_MINI_PID_PARSER6_ALL_PASS_CTRL_PIDP_DEBUG_MODE_MASK 0x00001000
-#define BCHP_XPT_FE_MINI_PID_PARSER6_ALL_PASS_CTRL_PIDP_DEBUG_MODE_SHIFT 12
-#define BCHP_XPT_FE_MINI_PID_PARSER6_ALL_PASS_CTRL_PIDP_DEBUG_MODE_DEFAULT 0x00000000
-
-/* XPT_FE :: MINI_PID_PARSER6_ALL_PASS_CTRL :: ALL_PASS_PID_CH_NUM [11:00] */
-#define BCHP_XPT_FE_MINI_PID_PARSER6_ALL_PASS_CTRL_ALL_PASS_PID_CH_NUM_MASK 0x00000fff
-#define BCHP_XPT_FE_MINI_PID_PARSER6_ALL_PASS_CTRL_ALL_PASS_PID_CH_NUM_SHIFT 0
-#define BCHP_XPT_FE_MINI_PID_PARSER6_ALL_PASS_CTRL_ALL_PASS_PID_CH_NUM_DEFAULT 0x00000006
-
-/***************************************************************************
- *MINI_PID_PARSER7_CTRL1 - Data Transport Parser Band 7 Control Register
- ***************************************************************************/
-/* XPT_FE :: MINI_PID_PARSER7_CTRL1 :: reserved0 [31:29] */
-#define BCHP_XPT_FE_MINI_PID_PARSER7_CTRL1_reserved0_MASK 0xe0000000
-#define BCHP_XPT_FE_MINI_PID_PARSER7_CTRL1_reserved0_SHIFT 29
-
-/* XPT_FE :: MINI_PID_PARSER7_CTRL1 :: PARSER_TIMESTAMP_MODE [28:27] */
-#define BCHP_XPT_FE_MINI_PID_PARSER7_CTRL1_PARSER_TIMESTAMP_MODE_MASK 0x18000000
-#define BCHP_XPT_FE_MINI_PID_PARSER7_CTRL1_PARSER_TIMESTAMP_MODE_SHIFT 27
-#define BCHP_XPT_FE_MINI_PID_PARSER7_CTRL1_PARSER_TIMESTAMP_MODE_DEFAULT 0x00000002
-
-/* XPT_FE :: MINI_PID_PARSER7_CTRL1 :: PARSER_TSMF_SEL [26:23] */
-#define BCHP_XPT_FE_MINI_PID_PARSER7_CTRL1_PARSER_TSMF_SEL_MASK 0x07800000
-#define BCHP_XPT_FE_MINI_PID_PARSER7_CTRL1_PARSER_TSMF_SEL_SHIFT 23
-#define BCHP_XPT_FE_MINI_PID_PARSER7_CTRL1_PARSER_TSMF_SEL_DEFAULT 0x00000000
-
-/* XPT_FE :: MINI_PID_PARSER7_CTRL1 :: PARSER_TSMF_EN [22:22] */
-#define BCHP_XPT_FE_MINI_PID_PARSER7_CTRL1_PARSER_TSMF_EN_MASK 0x00400000
-#define BCHP_XPT_FE_MINI_PID_PARSER7_CTRL1_PARSER_TSMF_EN_SHIFT 22
-#define BCHP_XPT_FE_MINI_PID_PARSER7_CTRL1_PARSER_TSMF_EN_DEFAULT 0x00000000
-
-/* XPT_FE :: MINI_PID_PARSER7_CTRL1 :: PARSER_INPUT_SEL_MSB [21:21] */
-#define BCHP_XPT_FE_MINI_PID_PARSER7_CTRL1_PARSER_INPUT_SEL_MSB_MASK 0x00200000
-#define BCHP_XPT_FE_MINI_PID_PARSER7_CTRL1_PARSER_INPUT_SEL_MSB_SHIFT 21
-#define BCHP_XPT_FE_MINI_PID_PARSER7_CTRL1_PARSER_INPUT_SEL_MSB_DEFAULT 0x00000000
-
-/* XPT_FE :: MINI_PID_PARSER7_CTRL1 :: PARSER_ERROR_INPUT_TEI_IGNORE [20:20] */
-#define BCHP_XPT_FE_MINI_PID_PARSER7_CTRL1_PARSER_ERROR_INPUT_TEI_IGNORE_MASK 0x00100000
-#define BCHP_XPT_FE_MINI_PID_PARSER7_CTRL1_PARSER_ERROR_INPUT_TEI_IGNORE_SHIFT 20
-#define BCHP_XPT_FE_MINI_PID_PARSER7_CTRL1_PARSER_ERROR_INPUT_TEI_IGNORE_DEFAULT 0x00000000
-
-/* XPT_FE :: MINI_PID_PARSER7_CTRL1 :: PARSER_PKT_LENGTH [19:12] */
-#define BCHP_XPT_FE_MINI_PID_PARSER7_CTRL1_PARSER_PKT_LENGTH_MASK 0x000ff000
-#define BCHP_XPT_FE_MINI_PID_PARSER7_CTRL1_PARSER_PKT_LENGTH_SHIFT 12
-#define BCHP_XPT_FE_MINI_PID_PARSER7_CTRL1_PARSER_PKT_LENGTH_DEFAULT 0x000000bc
-
-/* XPT_FE :: MINI_PID_PARSER7_CTRL1 :: PARSER_INPUT_SEL [11:08] */
-#define BCHP_XPT_FE_MINI_PID_PARSER7_CTRL1_PARSER_INPUT_SEL_MASK 0x00000f00
-#define BCHP_XPT_FE_MINI_PID_PARSER7_CTRL1_PARSER_INPUT_SEL_SHIFT 8
-#define BCHP_XPT_FE_MINI_PID_PARSER7_CTRL1_PARSER_INPUT_SEL_DEFAULT 0x00000000
-
-/* XPT_FE :: MINI_PID_PARSER7_CTRL1 :: reserved1 [07:07] */
-#define BCHP_XPT_FE_MINI_PID_PARSER7_CTRL1_reserved1_MASK 0x00000080
-#define BCHP_XPT_FE_MINI_PID_PARSER7_CTRL1_reserved1_SHIFT 7
-
-/* XPT_FE :: MINI_PID_PARSER7_CTRL1 :: PARSER_PACKET_TYPE [06:05] */
-#define BCHP_XPT_FE_MINI_PID_PARSER7_CTRL1_PARSER_PACKET_TYPE_MASK 0x00000060
-#define BCHP_XPT_FE_MINI_PID_PARSER7_CTRL1_PARSER_PACKET_TYPE_SHIFT 5
-#define BCHP_XPT_FE_MINI_PID_PARSER7_CTRL1_PARSER_PACKET_TYPE_DEFAULT 0x00000000
-
-/* XPT_FE :: MINI_PID_PARSER7_CTRL1 :: PARSER_ACCEPT_NULL_PKT_PRE_MPOD [04:04] */
-#define BCHP_XPT_FE_MINI_PID_PARSER7_CTRL1_PARSER_ACCEPT_NULL_PKT_PRE_MPOD_MASK 0x00000010
-#define BCHP_XPT_FE_MINI_PID_PARSER7_CTRL1_PARSER_ACCEPT_NULL_PKT_PRE_MPOD_SHIFT 4
-#define BCHP_XPT_FE_MINI_PID_PARSER7_CTRL1_PARSER_ACCEPT_NULL_PKT_PRE_MPOD_DEFAULT 0x00000000
-
-/* XPT_FE :: MINI_PID_PARSER7_CTRL1 :: PARSER_ACCEPT_NULL_PKT_PRE_TSIO [03:03] */
-#define BCHP_XPT_FE_MINI_PID_PARSER7_CTRL1_PARSER_ACCEPT_NULL_PKT_PRE_TSIO_MASK 0x00000008
-#define BCHP_XPT_FE_MINI_PID_PARSER7_CTRL1_PARSER_ACCEPT_NULL_PKT_PRE_TSIO_SHIFT 3
-#define BCHP_XPT_FE_MINI_PID_PARSER7_CTRL1_PARSER_ACCEPT_NULL_PKT_PRE_TSIO_DEFAULT 0x00000000
-
-/* XPT_FE :: MINI_PID_PARSER7_CTRL1 :: PARSER_ALL_PASS_CTRL_PRE_TSIO [02:02] */
-#define BCHP_XPT_FE_MINI_PID_PARSER7_CTRL1_PARSER_ALL_PASS_CTRL_PRE_TSIO_MASK 0x00000004
-#define BCHP_XPT_FE_MINI_PID_PARSER7_CTRL1_PARSER_ALL_PASS_CTRL_PRE_TSIO_SHIFT 2
-#define BCHP_XPT_FE_MINI_PID_PARSER7_CTRL1_PARSER_ALL_PASS_CTRL_PRE_TSIO_DEFAULT 0x00000000
-
-/* XPT_FE :: MINI_PID_PARSER7_CTRL1 :: PARSER_ALL_PASS_CTRL_PRE_MPOD [01:01] */
-#define BCHP_XPT_FE_MINI_PID_PARSER7_CTRL1_PARSER_ALL_PASS_CTRL_PRE_MPOD_MASK 0x00000002
-#define BCHP_XPT_FE_MINI_PID_PARSER7_CTRL1_PARSER_ALL_PASS_CTRL_PRE_MPOD_SHIFT 1
-#define BCHP_XPT_FE_MINI_PID_PARSER7_CTRL1_PARSER_ALL_PASS_CTRL_PRE_MPOD_DEFAULT 0x00000000
-
-/* XPT_FE :: MINI_PID_PARSER7_CTRL1 :: PARSER_ENABLE [00:00] */
-#define BCHP_XPT_FE_MINI_PID_PARSER7_CTRL1_PARSER_ENABLE_MASK 0x00000001
-#define BCHP_XPT_FE_MINI_PID_PARSER7_CTRL1_PARSER_ENABLE_SHIFT 0
-#define BCHP_XPT_FE_MINI_PID_PARSER7_CTRL1_PARSER_ENABLE_DEFAULT 0x00000000
-
-/***************************************************************************
- *MINI_PID_PARSER7_CTRL2 - Data Transport Parser Band 7 Control Register 2
- ***************************************************************************/
-/* XPT_FE :: MINI_PID_PARSER7_CTRL2 :: reserved0 [31:14] */
-#define BCHP_XPT_FE_MINI_PID_PARSER7_CTRL2_reserved0_MASK 0xffffc000
-#define BCHP_XPT_FE_MINI_PID_PARSER7_CTRL2_reserved0_SHIFT 14
-
-/* XPT_FE :: MINI_PID_PARSER7_CTRL2 :: PARSER_STREAM_TIMESTAMP_EN [13:13] */
-#define BCHP_XPT_FE_MINI_PID_PARSER7_CTRL2_PARSER_STREAM_TIMESTAMP_EN_MASK 0x00002000
-#define BCHP_XPT_FE_MINI_PID_PARSER7_CTRL2_PARSER_STREAM_TIMESTAMP_EN_SHIFT 13
-#define BCHP_XPT_FE_MINI_PID_PARSER7_CTRL2_PARSER_STREAM_TIMESTAMP_EN_DEFAULT 0x00000000
-
-/* XPT_FE :: MINI_PID_PARSER7_CTRL2 :: PARSER_TIMESTREAM_BF_SYNC [12:12] */
-#define BCHP_XPT_FE_MINI_PID_PARSER7_CTRL2_PARSER_TIMESTREAM_BF_SYNC_MASK 0x00001000
-#define BCHP_XPT_FE_MINI_PID_PARSER7_CTRL2_PARSER_TIMESTREAM_BF_SYNC_SHIFT 12
-#define BCHP_XPT_FE_MINI_PID_PARSER7_CTRL2_PARSER_TIMESTREAM_BF_SYNC_DEFAULT 0x00000000
-
-/* XPT_FE :: MINI_PID_PARSER7_CTRL2 :: reserved1 [11:11] */
-#define BCHP_XPT_FE_MINI_PID_PARSER7_CTRL2_reserved1_MASK 0x00000800
-#define BCHP_XPT_FE_MINI_PID_PARSER7_CTRL2_reserved1_SHIFT 11
-
-/* XPT_FE :: MINI_PID_PARSER7_CTRL2 :: PARSER_TIMESTAMP_RESTAMP [10:10] */
-#define BCHP_XPT_FE_MINI_PID_PARSER7_CTRL2_PARSER_TIMESTAMP_RESTAMP_MASK 0x00000400
-#define BCHP_XPT_FE_MINI_PID_PARSER7_CTRL2_PARSER_TIMESTAMP_RESTAMP_SHIFT 10
-#define BCHP_XPT_FE_MINI_PID_PARSER7_CTRL2_PARSER_TIMESTAMP_RESTAMP_DEFAULT 0x00000001
-
-/* XPT_FE :: MINI_PID_PARSER7_CTRL2 :: TSIO_MODE_SEL [09:09] */
-#define BCHP_XPT_FE_MINI_PID_PARSER7_CTRL2_TSIO_MODE_SEL_MASK 0x00000200
-#define BCHP_XPT_FE_MINI_PID_PARSER7_CTRL2_TSIO_MODE_SEL_SHIFT 9
-#define BCHP_XPT_FE_MINI_PID_PARSER7_CTRL2_TSIO_MODE_SEL_DEFAULT 0x00000001
-
-/* XPT_FE :: MINI_PID_PARSER7_CTRL2 :: reserved2 [08:07] */
-#define BCHP_XPT_FE_MINI_PID_PARSER7_CTRL2_reserved2_MASK 0x00000180
-#define BCHP_XPT_FE_MINI_PID_PARSER7_CTRL2_reserved2_SHIFT 7
-
-/* XPT_FE :: MINI_PID_PARSER7_CTRL2 :: TSIO_EN [06:06] */
-#define BCHP_XPT_FE_MINI_PID_PARSER7_CTRL2_TSIO_EN_MASK 0x00000040
-#define BCHP_XPT_FE_MINI_PID_PARSER7_CTRL2_TSIO_EN_SHIFT 6
-#define BCHP_XPT_FE_MINI_PID_PARSER7_CTRL2_TSIO_EN_DEFAULT 0x00000000
-
-/* XPT_FE :: MINI_PID_PARSER7_CTRL2 :: reserved3 [05:05] */
-#define BCHP_XPT_FE_MINI_PID_PARSER7_CTRL2_reserved3_MASK 0x00000020
-#define BCHP_XPT_FE_MINI_PID_PARSER7_CTRL2_reserved3_SHIFT 5
-
-/* XPT_FE :: MINI_PID_PARSER7_CTRL2 :: MPOD_MODE_SEL [04:04] */
-#define BCHP_XPT_FE_MINI_PID_PARSER7_CTRL2_MPOD_MODE_SEL_MASK 0x00000010
-#define BCHP_XPT_FE_MINI_PID_PARSER7_CTRL2_MPOD_MODE_SEL_SHIFT 4
-#define BCHP_XPT_FE_MINI_PID_PARSER7_CTRL2_MPOD_MODE_SEL_DEFAULT 0x00000000
-
-/* XPT_FE :: MINI_PID_PARSER7_CTRL2 :: reserved4 [03:03] */
-#define BCHP_XPT_FE_MINI_PID_PARSER7_CTRL2_reserved4_MASK 0x00000008
-#define BCHP_XPT_FE_MINI_PID_PARSER7_CTRL2_reserved4_SHIFT 3
-
-/* XPT_FE :: MINI_PID_PARSER7_CTRL2 :: PARSER_ACCEPT_NULL_PKT_POST_MPOD [02:02] */
-#define BCHP_XPT_FE_MINI_PID_PARSER7_CTRL2_PARSER_ACCEPT_NULL_PKT_POST_MPOD_MASK 0x00000004
-#define BCHP_XPT_FE_MINI_PID_PARSER7_CTRL2_PARSER_ACCEPT_NULL_PKT_POST_MPOD_SHIFT 2
-#define BCHP_XPT_FE_MINI_PID_PARSER7_CTRL2_PARSER_ACCEPT_NULL_PKT_POST_MPOD_DEFAULT 0x00000000
-
-/* XPT_FE :: MINI_PID_PARSER7_CTRL2 :: PARSER_ALL_PASS_CTRL_POST_MPOD [01:01] */
-#define BCHP_XPT_FE_MINI_PID_PARSER7_CTRL2_PARSER_ALL_PASS_CTRL_POST_MPOD_MASK 0x00000002
-#define BCHP_XPT_FE_MINI_PID_PARSER7_CTRL2_PARSER_ALL_PASS_CTRL_POST_MPOD_SHIFT 1
-#define BCHP_XPT_FE_MINI_PID_PARSER7_CTRL2_PARSER_ALL_PASS_CTRL_POST_MPOD_DEFAULT 0x00000000
-
-/* XPT_FE :: MINI_PID_PARSER7_CTRL2 :: MPOD_EN [00:00] */
-#define BCHP_XPT_FE_MINI_PID_PARSER7_CTRL2_MPOD_EN_MASK 0x00000001
-#define BCHP_XPT_FE_MINI_PID_PARSER7_CTRL2_MPOD_EN_SHIFT 0
-#define BCHP_XPT_FE_MINI_PID_PARSER7_CTRL2_MPOD_EN_DEFAULT 0x00000000
-
-/***************************************************************************
- *MINI_PID_PARSER7_ALL_PASS_CTRL - Data Transport Parser Band 7 Control Register
- ***************************************************************************/
-/* XPT_FE :: MINI_PID_PARSER7_ALL_PASS_CTRL :: reserved0 [31:13] */
-#define BCHP_XPT_FE_MINI_PID_PARSER7_ALL_PASS_CTRL_reserved0_MASK 0xffffe000
-#define BCHP_XPT_FE_MINI_PID_PARSER7_ALL_PASS_CTRL_reserved0_SHIFT 13
-
-/* XPT_FE :: MINI_PID_PARSER7_ALL_PASS_CTRL :: PIDP_DEBUG_MODE [12:12] */
-#define BCHP_XPT_FE_MINI_PID_PARSER7_ALL_PASS_CTRL_PIDP_DEBUG_MODE_MASK 0x00001000
-#define BCHP_XPT_FE_MINI_PID_PARSER7_ALL_PASS_CTRL_PIDP_DEBUG_MODE_SHIFT 12
-#define BCHP_XPT_FE_MINI_PID_PARSER7_ALL_PASS_CTRL_PIDP_DEBUG_MODE_DEFAULT 0x00000000
-
-/* XPT_FE :: MINI_PID_PARSER7_ALL_PASS_CTRL :: ALL_PASS_PID_CH_NUM [11:00] */
-#define BCHP_XPT_FE_MINI_PID_PARSER7_ALL_PASS_CTRL_ALL_PASS_PID_CH_NUM_MASK 0x00000fff
-#define BCHP_XPT_FE_MINI_PID_PARSER7_ALL_PASS_CTRL_ALL_PASS_PID_CH_NUM_SHIFT 0
-#define BCHP_XPT_FE_MINI_PID_PARSER7_ALL_PASS_CTRL_ALL_PASS_PID_CH_NUM_DEFAULT 0x00000007
-
-/***************************************************************************
- *MINI_PID_PARSER8_CTRL1 - Data Transport Parser Band 8 Control Register
- ***************************************************************************/
-/* XPT_FE :: MINI_PID_PARSER8_CTRL1 :: reserved0 [31:29] */
-#define BCHP_XPT_FE_MINI_PID_PARSER8_CTRL1_reserved0_MASK 0xe0000000
-#define BCHP_XPT_FE_MINI_PID_PARSER8_CTRL1_reserved0_SHIFT 29
-
-/* XPT_FE :: MINI_PID_PARSER8_CTRL1 :: PARSER_TIMESTAMP_MODE [28:27] */
-#define BCHP_XPT_FE_MINI_PID_PARSER8_CTRL1_PARSER_TIMESTAMP_MODE_MASK 0x18000000
-#define BCHP_XPT_FE_MINI_PID_PARSER8_CTRL1_PARSER_TIMESTAMP_MODE_SHIFT 27
-#define BCHP_XPT_FE_MINI_PID_PARSER8_CTRL1_PARSER_TIMESTAMP_MODE_DEFAULT 0x00000002
-
-/* XPT_FE :: MINI_PID_PARSER8_CTRL1 :: PARSER_TSMF_SEL [26:23] */
-#define BCHP_XPT_FE_MINI_PID_PARSER8_CTRL1_PARSER_TSMF_SEL_MASK 0x07800000
-#define BCHP_XPT_FE_MINI_PID_PARSER8_CTRL1_PARSER_TSMF_SEL_SHIFT 23
-#define BCHP_XPT_FE_MINI_PID_PARSER8_CTRL1_PARSER_TSMF_SEL_DEFAULT 0x00000000
-
-/* XPT_FE :: MINI_PID_PARSER8_CTRL1 :: PARSER_TSMF_EN [22:22] */
-#define BCHP_XPT_FE_MINI_PID_PARSER8_CTRL1_PARSER_TSMF_EN_MASK 0x00400000
-#define BCHP_XPT_FE_MINI_PID_PARSER8_CTRL1_PARSER_TSMF_EN_SHIFT 22
-#define BCHP_XPT_FE_MINI_PID_PARSER8_CTRL1_PARSER_TSMF_EN_DEFAULT 0x00000000
-
-/* XPT_FE :: MINI_PID_PARSER8_CTRL1 :: PARSER_INPUT_SEL_MSB [21:21] */
-#define BCHP_XPT_FE_MINI_PID_PARSER8_CTRL1_PARSER_INPUT_SEL_MSB_MASK 0x00200000
-#define BCHP_XPT_FE_MINI_PID_PARSER8_CTRL1_PARSER_INPUT_SEL_MSB_SHIFT 21
-#define BCHP_XPT_FE_MINI_PID_PARSER8_CTRL1_PARSER_INPUT_SEL_MSB_DEFAULT 0x00000000
-
-/* XPT_FE :: MINI_PID_PARSER8_CTRL1 :: PARSER_ERROR_INPUT_TEI_IGNORE [20:20] */
-#define BCHP_XPT_FE_MINI_PID_PARSER8_CTRL1_PARSER_ERROR_INPUT_TEI_IGNORE_MASK 0x00100000
-#define BCHP_XPT_FE_MINI_PID_PARSER8_CTRL1_PARSER_ERROR_INPUT_TEI_IGNORE_SHIFT 20
-#define BCHP_XPT_FE_MINI_PID_PARSER8_CTRL1_PARSER_ERROR_INPUT_TEI_IGNORE_DEFAULT 0x00000000
-
-/* XPT_FE :: MINI_PID_PARSER8_CTRL1 :: PARSER_PKT_LENGTH [19:12] */
-#define BCHP_XPT_FE_MINI_PID_PARSER8_CTRL1_PARSER_PKT_LENGTH_MASK 0x000ff000
-#define BCHP_XPT_FE_MINI_PID_PARSER8_CTRL1_PARSER_PKT_LENGTH_SHIFT 12
-#define BCHP_XPT_FE_MINI_PID_PARSER8_CTRL1_PARSER_PKT_LENGTH_DEFAULT 0x000000bc
-
-/* XPT_FE :: MINI_PID_PARSER8_CTRL1 :: PARSER_INPUT_SEL [11:08] */
-#define BCHP_XPT_FE_MINI_PID_PARSER8_CTRL1_PARSER_INPUT_SEL_MASK 0x00000f00
-#define BCHP_XPT_FE_MINI_PID_PARSER8_CTRL1_PARSER_INPUT_SEL_SHIFT 8
-#define BCHP_XPT_FE_MINI_PID_PARSER8_CTRL1_PARSER_INPUT_SEL_DEFAULT 0x00000000
-
-/* XPT_FE :: MINI_PID_PARSER8_CTRL1 :: reserved1 [07:07] */
-#define BCHP_XPT_FE_MINI_PID_PARSER8_CTRL1_reserved1_MASK 0x00000080
-#define BCHP_XPT_FE_MINI_PID_PARSER8_CTRL1_reserved1_SHIFT 7
-
-/* XPT_FE :: MINI_PID_PARSER8_CTRL1 :: PARSER_PACKET_TYPE [06:05] */
-#define BCHP_XPT_FE_MINI_PID_PARSER8_CTRL1_PARSER_PACKET_TYPE_MASK 0x00000060
-#define BCHP_XPT_FE_MINI_PID_PARSER8_CTRL1_PARSER_PACKET_TYPE_SHIFT 5
-#define BCHP_XPT_FE_MINI_PID_PARSER8_CTRL1_PARSER_PACKET_TYPE_DEFAULT 0x00000000
-
-/* XPT_FE :: MINI_PID_PARSER8_CTRL1 :: PARSER_ACCEPT_NULL_PKT_PRE_MPOD [04:04] */
-#define BCHP_XPT_FE_MINI_PID_PARSER8_CTRL1_PARSER_ACCEPT_NULL_PKT_PRE_MPOD_MASK 0x00000010
-#define BCHP_XPT_FE_MINI_PID_PARSER8_CTRL1_PARSER_ACCEPT_NULL_PKT_PRE_MPOD_SHIFT 4
-#define BCHP_XPT_FE_MINI_PID_PARSER8_CTRL1_PARSER_ACCEPT_NULL_PKT_PRE_MPOD_DEFAULT 0x00000000
-
-/* XPT_FE :: MINI_PID_PARSER8_CTRL1 :: PARSER_ACCEPT_NULL_PKT_PRE_TSIO [03:03] */
-#define BCHP_XPT_FE_MINI_PID_PARSER8_CTRL1_PARSER_ACCEPT_NULL_PKT_PRE_TSIO_MASK 0x00000008
-#define BCHP_XPT_FE_MINI_PID_PARSER8_CTRL1_PARSER_ACCEPT_NULL_PKT_PRE_TSIO_SHIFT 3
-#define BCHP_XPT_FE_MINI_PID_PARSER8_CTRL1_PARSER_ACCEPT_NULL_PKT_PRE_TSIO_DEFAULT 0x00000000
-
-/* XPT_FE :: MINI_PID_PARSER8_CTRL1 :: PARSER_ALL_PASS_CTRL_PRE_TSIO [02:02] */
-#define BCHP_XPT_FE_MINI_PID_PARSER8_CTRL1_PARSER_ALL_PASS_CTRL_PRE_TSIO_MASK 0x00000004
-#define BCHP_XPT_FE_MINI_PID_PARSER8_CTRL1_PARSER_ALL_PASS_CTRL_PRE_TSIO_SHIFT 2
-#define BCHP_XPT_FE_MINI_PID_PARSER8_CTRL1_PARSER_ALL_PASS_CTRL_PRE_TSIO_DEFAULT 0x00000000
-
-/* XPT_FE :: MINI_PID_PARSER8_CTRL1 :: PARSER_ALL_PASS_CTRL_PRE_MPOD [01:01] */
-#define BCHP_XPT_FE_MINI_PID_PARSER8_CTRL1_PARSER_ALL_PASS_CTRL_PRE_MPOD_MASK 0x00000002
-#define BCHP_XPT_FE_MINI_PID_PARSER8_CTRL1_PARSER_ALL_PASS_CTRL_PRE_MPOD_SHIFT 1
-#define BCHP_XPT_FE_MINI_PID_PARSER8_CTRL1_PARSER_ALL_PASS_CTRL_PRE_MPOD_DEFAULT 0x00000000
-
-/* XPT_FE :: MINI_PID_PARSER8_CTRL1 :: PARSER_ENABLE [00:00] */
-#define BCHP_XPT_FE_MINI_PID_PARSER8_CTRL1_PARSER_ENABLE_MASK 0x00000001
-#define BCHP_XPT_FE_MINI_PID_PARSER8_CTRL1_PARSER_ENABLE_SHIFT 0
-#define BCHP_XPT_FE_MINI_PID_PARSER8_CTRL1_PARSER_ENABLE_DEFAULT 0x00000000
-
-/***************************************************************************
- *MINI_PID_PARSER8_CTRL2 - Data Transport Parser Band 8 Control Register 2
- ***************************************************************************/
-/* XPT_FE :: MINI_PID_PARSER8_CTRL2 :: reserved0 [31:14] */
-#define BCHP_XPT_FE_MINI_PID_PARSER8_CTRL2_reserved0_MASK 0xffffc000
-#define BCHP_XPT_FE_MINI_PID_PARSER8_CTRL2_reserved0_SHIFT 14
-
-/* XPT_FE :: MINI_PID_PARSER8_CTRL2 :: PARSER_STREAM_TIMESTAMP_EN [13:13] */
-#define BCHP_XPT_FE_MINI_PID_PARSER8_CTRL2_PARSER_STREAM_TIMESTAMP_EN_MASK 0x00002000
-#define BCHP_XPT_FE_MINI_PID_PARSER8_CTRL2_PARSER_STREAM_TIMESTAMP_EN_SHIFT 13
-#define BCHP_XPT_FE_MINI_PID_PARSER8_CTRL2_PARSER_STREAM_TIMESTAMP_EN_DEFAULT 0x00000000
-
-/* XPT_FE :: MINI_PID_PARSER8_CTRL2 :: PARSER_TIMESTREAM_BF_SYNC [12:12] */
-#define BCHP_XPT_FE_MINI_PID_PARSER8_CTRL2_PARSER_TIMESTREAM_BF_SYNC_MASK 0x00001000
-#define BCHP_XPT_FE_MINI_PID_PARSER8_CTRL2_PARSER_TIMESTREAM_BF_SYNC_SHIFT 12
-#define BCHP_XPT_FE_MINI_PID_PARSER8_CTRL2_PARSER_TIMESTREAM_BF_SYNC_DEFAULT 0x00000000
-
-/* XPT_FE :: MINI_PID_PARSER8_CTRL2 :: reserved1 [11:11] */
-#define BCHP_XPT_FE_MINI_PID_PARSER8_CTRL2_reserved1_MASK 0x00000800
-#define BCHP_XPT_FE_MINI_PID_PARSER8_CTRL2_reserved1_SHIFT 11
-
-/* XPT_FE :: MINI_PID_PARSER8_CTRL2 :: PARSER_TIMESTAMP_RESTAMP [10:10] */
-#define BCHP_XPT_FE_MINI_PID_PARSER8_CTRL2_PARSER_TIMESTAMP_RESTAMP_MASK 0x00000400
-#define BCHP_XPT_FE_MINI_PID_PARSER8_CTRL2_PARSER_TIMESTAMP_RESTAMP_SHIFT 10
-#define BCHP_XPT_FE_MINI_PID_PARSER8_CTRL2_PARSER_TIMESTAMP_RESTAMP_DEFAULT 0x00000001
-
-/* XPT_FE :: MINI_PID_PARSER8_CTRL2 :: TSIO_MODE_SEL [09:09] */
-#define BCHP_XPT_FE_MINI_PID_PARSER8_CTRL2_TSIO_MODE_SEL_MASK 0x00000200
-#define BCHP_XPT_FE_MINI_PID_PARSER8_CTRL2_TSIO_MODE_SEL_SHIFT 9
-#define BCHP_XPT_FE_MINI_PID_PARSER8_CTRL2_TSIO_MODE_SEL_DEFAULT 0x00000001
-
-/* XPT_FE :: MINI_PID_PARSER8_CTRL2 :: reserved2 [08:07] */
-#define BCHP_XPT_FE_MINI_PID_PARSER8_CTRL2_reserved2_MASK 0x00000180
-#define BCHP_XPT_FE_MINI_PID_PARSER8_CTRL2_reserved2_SHIFT 7
-
-/* XPT_FE :: MINI_PID_PARSER8_CTRL2 :: TSIO_EN [06:06] */
-#define BCHP_XPT_FE_MINI_PID_PARSER8_CTRL2_TSIO_EN_MASK 0x00000040
-#define BCHP_XPT_FE_MINI_PID_PARSER8_CTRL2_TSIO_EN_SHIFT 6
-#define BCHP_XPT_FE_MINI_PID_PARSER8_CTRL2_TSIO_EN_DEFAULT 0x00000000
-
-/* XPT_FE :: MINI_PID_PARSER8_CTRL2 :: reserved3 [05:05] */
-#define BCHP_XPT_FE_MINI_PID_PARSER8_CTRL2_reserved3_MASK 0x00000020
-#define BCHP_XPT_FE_MINI_PID_PARSER8_CTRL2_reserved3_SHIFT 5
-
-/* XPT_FE :: MINI_PID_PARSER8_CTRL2 :: MPOD_MODE_SEL [04:04] */
-#define BCHP_XPT_FE_MINI_PID_PARSER8_CTRL2_MPOD_MODE_SEL_MASK 0x00000010
-#define BCHP_XPT_FE_MINI_PID_PARSER8_CTRL2_MPOD_MODE_SEL_SHIFT 4
-#define BCHP_XPT_FE_MINI_PID_PARSER8_CTRL2_MPOD_MODE_SEL_DEFAULT 0x00000000
-
-/* XPT_FE :: MINI_PID_PARSER8_CTRL2 :: reserved4 [03:03] */
-#define BCHP_XPT_FE_MINI_PID_PARSER8_CTRL2_reserved4_MASK 0x00000008
-#define BCHP_XPT_FE_MINI_PID_PARSER8_CTRL2_reserved4_SHIFT 3
-
-/* XPT_FE :: MINI_PID_PARSER8_CTRL2 :: PARSER_ACCEPT_NULL_PKT_POST_MPOD [02:02] */
-#define BCHP_XPT_FE_MINI_PID_PARSER8_CTRL2_PARSER_ACCEPT_NULL_PKT_POST_MPOD_MASK 0x00000004
-#define BCHP_XPT_FE_MINI_PID_PARSER8_CTRL2_PARSER_ACCEPT_NULL_PKT_POST_MPOD_SHIFT 2
-#define BCHP_XPT_FE_MINI_PID_PARSER8_CTRL2_PARSER_ACCEPT_NULL_PKT_POST_MPOD_DEFAULT 0x00000000
-
-/* XPT_FE :: MINI_PID_PARSER8_CTRL2 :: PARSER_ALL_PASS_CTRL_POST_MPOD [01:01] */
-#define BCHP_XPT_FE_MINI_PID_PARSER8_CTRL2_PARSER_ALL_PASS_CTRL_POST_MPOD_MASK 0x00000002
-#define BCHP_XPT_FE_MINI_PID_PARSER8_CTRL2_PARSER_ALL_PASS_CTRL_POST_MPOD_SHIFT 1
-#define BCHP_XPT_FE_MINI_PID_PARSER8_CTRL2_PARSER_ALL_PASS_CTRL_POST_MPOD_DEFAULT 0x00000000
-
-/* XPT_FE :: MINI_PID_PARSER8_CTRL2 :: MPOD_EN [00:00] */
-#define BCHP_XPT_FE_MINI_PID_PARSER8_CTRL2_MPOD_EN_MASK 0x00000001
-#define BCHP_XPT_FE_MINI_PID_PARSER8_CTRL2_MPOD_EN_SHIFT 0
-#define BCHP_XPT_FE_MINI_PID_PARSER8_CTRL2_MPOD_EN_DEFAULT 0x00000000
-
-/***************************************************************************
- *MINI_PID_PARSER8_ALL_PASS_CTRL - Data Transport Parser Band 8 Control Register
- ***************************************************************************/
-/* XPT_FE :: MINI_PID_PARSER8_ALL_PASS_CTRL :: reserved0 [31:13] */
-#define BCHP_XPT_FE_MINI_PID_PARSER8_ALL_PASS_CTRL_reserved0_MASK 0xffffe000
-#define BCHP_XPT_FE_MINI_PID_PARSER8_ALL_PASS_CTRL_reserved0_SHIFT 13
-
-/* XPT_FE :: MINI_PID_PARSER8_ALL_PASS_CTRL :: PIDP_DEBUG_MODE [12:12] */
-#define BCHP_XPT_FE_MINI_PID_PARSER8_ALL_PASS_CTRL_PIDP_DEBUG_MODE_MASK 0x00001000
-#define BCHP_XPT_FE_MINI_PID_PARSER8_ALL_PASS_CTRL_PIDP_DEBUG_MODE_SHIFT 12
-#define BCHP_XPT_FE_MINI_PID_PARSER8_ALL_PASS_CTRL_PIDP_DEBUG_MODE_DEFAULT 0x00000000
-
-/* XPT_FE :: MINI_PID_PARSER8_ALL_PASS_CTRL :: ALL_PASS_PID_CH_NUM [11:00] */
-#define BCHP_XPT_FE_MINI_PID_PARSER8_ALL_PASS_CTRL_ALL_PASS_PID_CH_NUM_MASK 0x00000fff
-#define BCHP_XPT_FE_MINI_PID_PARSER8_ALL_PASS_CTRL_ALL_PASS_PID_CH_NUM_SHIFT 0
-#define BCHP_XPT_FE_MINI_PID_PARSER8_ALL_PASS_CTRL_ALL_PASS_PID_CH_NUM_DEFAULT 0x00000008
-
-/***************************************************************************
- *MINI_PID_PARSER9_CTRL1 - Data Transport Parser Band 9 Control Register
- ***************************************************************************/
-/* XPT_FE :: MINI_PID_PARSER9_CTRL1 :: reserved0 [31:29] */
-#define BCHP_XPT_FE_MINI_PID_PARSER9_CTRL1_reserved0_MASK 0xe0000000
-#define BCHP_XPT_FE_MINI_PID_PARSER9_CTRL1_reserved0_SHIFT 29
-
-/* XPT_FE :: MINI_PID_PARSER9_CTRL1 :: PARSER_TIMESTAMP_MODE [28:27] */
-#define BCHP_XPT_FE_MINI_PID_PARSER9_CTRL1_PARSER_TIMESTAMP_MODE_MASK 0x18000000
-#define BCHP_XPT_FE_MINI_PID_PARSER9_CTRL1_PARSER_TIMESTAMP_MODE_SHIFT 27
-#define BCHP_XPT_FE_MINI_PID_PARSER9_CTRL1_PARSER_TIMESTAMP_MODE_DEFAULT 0x00000002
-
-/* XPT_FE :: MINI_PID_PARSER9_CTRL1 :: PARSER_TSMF_SEL [26:23] */
-#define BCHP_XPT_FE_MINI_PID_PARSER9_CTRL1_PARSER_TSMF_SEL_MASK 0x07800000
-#define BCHP_XPT_FE_MINI_PID_PARSER9_CTRL1_PARSER_TSMF_SEL_SHIFT 23
-#define BCHP_XPT_FE_MINI_PID_PARSER9_CTRL1_PARSER_TSMF_SEL_DEFAULT 0x00000000
-
-/* XPT_FE :: MINI_PID_PARSER9_CTRL1 :: PARSER_TSMF_EN [22:22] */
-#define BCHP_XPT_FE_MINI_PID_PARSER9_CTRL1_PARSER_TSMF_EN_MASK 0x00400000
-#define BCHP_XPT_FE_MINI_PID_PARSER9_CTRL1_PARSER_TSMF_EN_SHIFT 22
-#define BCHP_XPT_FE_MINI_PID_PARSER9_CTRL1_PARSER_TSMF_EN_DEFAULT 0x00000000
-
-/* XPT_FE :: MINI_PID_PARSER9_CTRL1 :: PARSER_INPUT_SEL_MSB [21:21] */
-#define BCHP_XPT_FE_MINI_PID_PARSER9_CTRL1_PARSER_INPUT_SEL_MSB_MASK 0x00200000
-#define BCHP_XPT_FE_MINI_PID_PARSER9_CTRL1_PARSER_INPUT_SEL_MSB_SHIFT 21
-#define BCHP_XPT_FE_MINI_PID_PARSER9_CTRL1_PARSER_INPUT_SEL_MSB_DEFAULT 0x00000000
-
-/* XPT_FE :: MINI_PID_PARSER9_CTRL1 :: PARSER_ERROR_INPUT_TEI_IGNORE [20:20] */
-#define BCHP_XPT_FE_MINI_PID_PARSER9_CTRL1_PARSER_ERROR_INPUT_TEI_IGNORE_MASK 0x00100000
-#define BCHP_XPT_FE_MINI_PID_PARSER9_CTRL1_PARSER_ERROR_INPUT_TEI_IGNORE_SHIFT 20
-#define BCHP_XPT_FE_MINI_PID_PARSER9_CTRL1_PARSER_ERROR_INPUT_TEI_IGNORE_DEFAULT 0x00000000
-
-/* XPT_FE :: MINI_PID_PARSER9_CTRL1 :: PARSER_PKT_LENGTH [19:12] */
-#define BCHP_XPT_FE_MINI_PID_PARSER9_CTRL1_PARSER_PKT_LENGTH_MASK 0x000ff000
-#define BCHP_XPT_FE_MINI_PID_PARSER9_CTRL1_PARSER_PKT_LENGTH_SHIFT 12
-#define BCHP_XPT_FE_MINI_PID_PARSER9_CTRL1_PARSER_PKT_LENGTH_DEFAULT 0x000000bc
-
-/* XPT_FE :: MINI_PID_PARSER9_CTRL1 :: PARSER_INPUT_SEL [11:08] */
-#define BCHP_XPT_FE_MINI_PID_PARSER9_CTRL1_PARSER_INPUT_SEL_MASK 0x00000f00
-#define BCHP_XPT_FE_MINI_PID_PARSER9_CTRL1_PARSER_INPUT_SEL_SHIFT 8
-#define BCHP_XPT_FE_MINI_PID_PARSER9_CTRL1_PARSER_INPUT_SEL_DEFAULT 0x00000000
-
-/* XPT_FE :: MINI_PID_PARSER9_CTRL1 :: reserved1 [07:07] */
-#define BCHP_XPT_FE_MINI_PID_PARSER9_CTRL1_reserved1_MASK 0x00000080
-#define BCHP_XPT_FE_MINI_PID_PARSER9_CTRL1_reserved1_SHIFT 7
-
-/* XPT_FE :: MINI_PID_PARSER9_CTRL1 :: PARSER_PACKET_TYPE [06:05] */
-#define BCHP_XPT_FE_MINI_PID_PARSER9_CTRL1_PARSER_PACKET_TYPE_MASK 0x00000060
-#define BCHP_XPT_FE_MINI_PID_PARSER9_CTRL1_PARSER_PACKET_TYPE_SHIFT 5
-#define BCHP_XPT_FE_MINI_PID_PARSER9_CTRL1_PARSER_PACKET_TYPE_DEFAULT 0x00000000
-
-/* XPT_FE :: MINI_PID_PARSER9_CTRL1 :: PARSER_ACCEPT_NULL_PKT_PRE_MPOD [04:04] */
-#define BCHP_XPT_FE_MINI_PID_PARSER9_CTRL1_PARSER_ACCEPT_NULL_PKT_PRE_MPOD_MASK 0x00000010
-#define BCHP_XPT_FE_MINI_PID_PARSER9_CTRL1_PARSER_ACCEPT_NULL_PKT_PRE_MPOD_SHIFT 4
-#define BCHP_XPT_FE_MINI_PID_PARSER9_CTRL1_PARSER_ACCEPT_NULL_PKT_PRE_MPOD_DEFAULT 0x00000000
-
-/* XPT_FE :: MINI_PID_PARSER9_CTRL1 :: PARSER_ACCEPT_NULL_PKT_PRE_TSIO [03:03] */
-#define BCHP_XPT_FE_MINI_PID_PARSER9_CTRL1_PARSER_ACCEPT_NULL_PKT_PRE_TSIO_MASK 0x00000008
-#define BCHP_XPT_FE_MINI_PID_PARSER9_CTRL1_PARSER_ACCEPT_NULL_PKT_PRE_TSIO_SHIFT 3
-#define BCHP_XPT_FE_MINI_PID_PARSER9_CTRL1_PARSER_ACCEPT_NULL_PKT_PRE_TSIO_DEFAULT 0x00000000
-
-/* XPT_FE :: MINI_PID_PARSER9_CTRL1 :: PARSER_ALL_PASS_CTRL_PRE_TSIO [02:02] */
-#define BCHP_XPT_FE_MINI_PID_PARSER9_CTRL1_PARSER_ALL_PASS_CTRL_PRE_TSIO_MASK 0x00000004
-#define BCHP_XPT_FE_MINI_PID_PARSER9_CTRL1_PARSER_ALL_PASS_CTRL_PRE_TSIO_SHIFT 2
-#define BCHP_XPT_FE_MINI_PID_PARSER9_CTRL1_PARSER_ALL_PASS_CTRL_PRE_TSIO_DEFAULT 0x00000000
-
-/* XPT_FE :: MINI_PID_PARSER9_CTRL1 :: PARSER_ALL_PASS_CTRL_PRE_MPOD [01:01] */
-#define BCHP_XPT_FE_MINI_PID_PARSER9_CTRL1_PARSER_ALL_PASS_CTRL_PRE_MPOD_MASK 0x00000002
-#define BCHP_XPT_FE_MINI_PID_PARSER9_CTRL1_PARSER_ALL_PASS_CTRL_PRE_MPOD_SHIFT 1
-#define BCHP_XPT_FE_MINI_PID_PARSER9_CTRL1_PARSER_ALL_PASS_CTRL_PRE_MPOD_DEFAULT 0x00000000
-
-/* XPT_FE :: MINI_PID_PARSER9_CTRL1 :: PARSER_ENABLE [00:00] */
-#define BCHP_XPT_FE_MINI_PID_PARSER9_CTRL1_PARSER_ENABLE_MASK 0x00000001
-#define BCHP_XPT_FE_MINI_PID_PARSER9_CTRL1_PARSER_ENABLE_SHIFT 0
-#define BCHP_XPT_FE_MINI_PID_PARSER9_CTRL1_PARSER_ENABLE_DEFAULT 0x00000000
-
-/***************************************************************************
- *MINI_PID_PARSER9_CTRL2 - Data Transport Parser Band 9 Control Register 2
- ***************************************************************************/
-/* XPT_FE :: MINI_PID_PARSER9_CTRL2 :: reserved0 [31:14] */
-#define BCHP_XPT_FE_MINI_PID_PARSER9_CTRL2_reserved0_MASK 0xffffc000
-#define BCHP_XPT_FE_MINI_PID_PARSER9_CTRL2_reserved0_SHIFT 14
-
-/* XPT_FE :: MINI_PID_PARSER9_CTRL2 :: PARSER_STREAM_TIMESTAMP_EN [13:13] */
-#define BCHP_XPT_FE_MINI_PID_PARSER9_CTRL2_PARSER_STREAM_TIMESTAMP_EN_MASK 0x00002000
-#define BCHP_XPT_FE_MINI_PID_PARSER9_CTRL2_PARSER_STREAM_TIMESTAMP_EN_SHIFT 13
-#define BCHP_XPT_FE_MINI_PID_PARSER9_CTRL2_PARSER_STREAM_TIMESTAMP_EN_DEFAULT 0x00000000
-
-/* XPT_FE :: MINI_PID_PARSER9_CTRL2 :: PARSER_TIMESTREAM_BF_SYNC [12:12] */
-#define BCHP_XPT_FE_MINI_PID_PARSER9_CTRL2_PARSER_TIMESTREAM_BF_SYNC_MASK 0x00001000
-#define BCHP_XPT_FE_MINI_PID_PARSER9_CTRL2_PARSER_TIMESTREAM_BF_SYNC_SHIFT 12
-#define BCHP_XPT_FE_MINI_PID_PARSER9_CTRL2_PARSER_TIMESTREAM_BF_SYNC_DEFAULT 0x00000000
-
-/* XPT_FE :: MINI_PID_PARSER9_CTRL2 :: reserved1 [11:11] */
-#define BCHP_XPT_FE_MINI_PID_PARSER9_CTRL2_reserved1_MASK 0x00000800
-#define BCHP_XPT_FE_MINI_PID_PARSER9_CTRL2_reserved1_SHIFT 11
-
-/* XPT_FE :: MINI_PID_PARSER9_CTRL2 :: PARSER_TIMESTAMP_RESTAMP [10:10] */
-#define BCHP_XPT_FE_MINI_PID_PARSER9_CTRL2_PARSER_TIMESTAMP_RESTAMP_MASK 0x00000400
-#define BCHP_XPT_FE_MINI_PID_PARSER9_CTRL2_PARSER_TIMESTAMP_RESTAMP_SHIFT 10
-#define BCHP_XPT_FE_MINI_PID_PARSER9_CTRL2_PARSER_TIMESTAMP_RESTAMP_DEFAULT 0x00000001
-
-/* XPT_FE :: MINI_PID_PARSER9_CTRL2 :: TSIO_MODE_SEL [09:09] */
-#define BCHP_XPT_FE_MINI_PID_PARSER9_CTRL2_TSIO_MODE_SEL_MASK 0x00000200
-#define BCHP_XPT_FE_MINI_PID_PARSER9_CTRL2_TSIO_MODE_SEL_SHIFT 9
-#define BCHP_XPT_FE_MINI_PID_PARSER9_CTRL2_TSIO_MODE_SEL_DEFAULT 0x00000001
-
-/* XPT_FE :: MINI_PID_PARSER9_CTRL2 :: reserved2 [08:07] */
-#define BCHP_XPT_FE_MINI_PID_PARSER9_CTRL2_reserved2_MASK 0x00000180
-#define BCHP_XPT_FE_MINI_PID_PARSER9_CTRL2_reserved2_SHIFT 7
-
-/* XPT_FE :: MINI_PID_PARSER9_CTRL2 :: TSIO_EN [06:06] */
-#define BCHP_XPT_FE_MINI_PID_PARSER9_CTRL2_TSIO_EN_MASK 0x00000040
-#define BCHP_XPT_FE_MINI_PID_PARSER9_CTRL2_TSIO_EN_SHIFT 6
-#define BCHP_XPT_FE_MINI_PID_PARSER9_CTRL2_TSIO_EN_DEFAULT 0x00000000
-
-/* XPT_FE :: MINI_PID_PARSER9_CTRL2 :: reserved3 [05:05] */
-#define BCHP_XPT_FE_MINI_PID_PARSER9_CTRL2_reserved3_MASK 0x00000020
-#define BCHP_XPT_FE_MINI_PID_PARSER9_CTRL2_reserved3_SHIFT 5
-
-/* XPT_FE :: MINI_PID_PARSER9_CTRL2 :: MPOD_MODE_SEL [04:04] */
-#define BCHP_XPT_FE_MINI_PID_PARSER9_CTRL2_MPOD_MODE_SEL_MASK 0x00000010
-#define BCHP_XPT_FE_MINI_PID_PARSER9_CTRL2_MPOD_MODE_SEL_SHIFT 4
-#define BCHP_XPT_FE_MINI_PID_PARSER9_CTRL2_MPOD_MODE_SEL_DEFAULT 0x00000000
-
-/* XPT_FE :: MINI_PID_PARSER9_CTRL2 :: reserved4 [03:03] */
-#define BCHP_XPT_FE_MINI_PID_PARSER9_CTRL2_reserved4_MASK 0x00000008
-#define BCHP_XPT_FE_MINI_PID_PARSER9_CTRL2_reserved4_SHIFT 3
-
-/* XPT_FE :: MINI_PID_PARSER9_CTRL2 :: PARSER_ACCEPT_NULL_PKT_POST_MPOD [02:02] */
-#define BCHP_XPT_FE_MINI_PID_PARSER9_CTRL2_PARSER_ACCEPT_NULL_PKT_POST_MPOD_MASK 0x00000004
-#define BCHP_XPT_FE_MINI_PID_PARSER9_CTRL2_PARSER_ACCEPT_NULL_PKT_POST_MPOD_SHIFT 2
-#define BCHP_XPT_FE_MINI_PID_PARSER9_CTRL2_PARSER_ACCEPT_NULL_PKT_POST_MPOD_DEFAULT 0x00000000
-
-/* XPT_FE :: MINI_PID_PARSER9_CTRL2 :: PARSER_ALL_PASS_CTRL_POST_MPOD [01:01] */
-#define BCHP_XPT_FE_MINI_PID_PARSER9_CTRL2_PARSER_ALL_PASS_CTRL_POST_MPOD_MASK 0x00000002
-#define BCHP_XPT_FE_MINI_PID_PARSER9_CTRL2_PARSER_ALL_PASS_CTRL_POST_MPOD_SHIFT 1
-#define BCHP_XPT_FE_MINI_PID_PARSER9_CTRL2_PARSER_ALL_PASS_CTRL_POST_MPOD_DEFAULT 0x00000000
-
-/* XPT_FE :: MINI_PID_PARSER9_CTRL2 :: MPOD_EN [00:00] */
-#define BCHP_XPT_FE_MINI_PID_PARSER9_CTRL2_MPOD_EN_MASK 0x00000001
-#define BCHP_XPT_FE_MINI_PID_PARSER9_CTRL2_MPOD_EN_SHIFT 0
-#define BCHP_XPT_FE_MINI_PID_PARSER9_CTRL2_MPOD_EN_DEFAULT 0x00000000
-
-/***************************************************************************
- *MINI_PID_PARSER9_ALL_PASS_CTRL - Data Transport Parser Band 9 Control Register
- ***************************************************************************/
-/* XPT_FE :: MINI_PID_PARSER9_ALL_PASS_CTRL :: reserved0 [31:13] */
-#define BCHP_XPT_FE_MINI_PID_PARSER9_ALL_PASS_CTRL_reserved0_MASK 0xffffe000
-#define BCHP_XPT_FE_MINI_PID_PARSER9_ALL_PASS_CTRL_reserved0_SHIFT 13
-
-/* XPT_FE :: MINI_PID_PARSER9_ALL_PASS_CTRL :: PIDP_DEBUG_MODE [12:12] */
-#define BCHP_XPT_FE_MINI_PID_PARSER9_ALL_PASS_CTRL_PIDP_DEBUG_MODE_MASK 0x00001000
-#define BCHP_XPT_FE_MINI_PID_PARSER9_ALL_PASS_CTRL_PIDP_DEBUG_MODE_SHIFT 12
-#define BCHP_XPT_FE_MINI_PID_PARSER9_ALL_PASS_CTRL_PIDP_DEBUG_MODE_DEFAULT 0x00000000
-
-/* XPT_FE :: MINI_PID_PARSER9_ALL_PASS_CTRL :: ALL_PASS_PID_CH_NUM [11:00] */
-#define BCHP_XPT_FE_MINI_PID_PARSER9_ALL_PASS_CTRL_ALL_PASS_PID_CH_NUM_MASK 0x00000fff
-#define BCHP_XPT_FE_MINI_PID_PARSER9_ALL_PASS_CTRL_ALL_PASS_PID_CH_NUM_SHIFT 0
-#define BCHP_XPT_FE_MINI_PID_PARSER9_ALL_PASS_CTRL_ALL_PASS_PID_CH_NUM_DEFAULT 0x00000009
-
-/***************************************************************************
- *MINI_PID_PARSER10_CTRL1 - Data Transport Parser Band 10 Control Register
- ***************************************************************************/
-/* XPT_FE :: MINI_PID_PARSER10_CTRL1 :: reserved0 [31:29] */
-#define BCHP_XPT_FE_MINI_PID_PARSER10_CTRL1_reserved0_MASK 0xe0000000
-#define BCHP_XPT_FE_MINI_PID_PARSER10_CTRL1_reserved0_SHIFT 29
-
-/* XPT_FE :: MINI_PID_PARSER10_CTRL1 :: PARSER_TIMESTAMP_MODE [28:27] */
-#define BCHP_XPT_FE_MINI_PID_PARSER10_CTRL1_PARSER_TIMESTAMP_MODE_MASK 0x18000000
-#define BCHP_XPT_FE_MINI_PID_PARSER10_CTRL1_PARSER_TIMESTAMP_MODE_SHIFT 27
-#define BCHP_XPT_FE_MINI_PID_PARSER10_CTRL1_PARSER_TIMESTAMP_MODE_DEFAULT 0x00000002
-
-/* XPT_FE :: MINI_PID_PARSER10_CTRL1 :: PARSER_TSMF_SEL [26:23] */
-#define BCHP_XPT_FE_MINI_PID_PARSER10_CTRL1_PARSER_TSMF_SEL_MASK 0x07800000
-#define BCHP_XPT_FE_MINI_PID_PARSER10_CTRL1_PARSER_TSMF_SEL_SHIFT 23
-#define BCHP_XPT_FE_MINI_PID_PARSER10_CTRL1_PARSER_TSMF_SEL_DEFAULT 0x00000000
-
-/* XPT_FE :: MINI_PID_PARSER10_CTRL1 :: PARSER_TSMF_EN [22:22] */
-#define BCHP_XPT_FE_MINI_PID_PARSER10_CTRL1_PARSER_TSMF_EN_MASK 0x00400000
-#define BCHP_XPT_FE_MINI_PID_PARSER10_CTRL1_PARSER_TSMF_EN_SHIFT 22
-#define BCHP_XPT_FE_MINI_PID_PARSER10_CTRL1_PARSER_TSMF_EN_DEFAULT 0x00000000
-
-/* XPT_FE :: MINI_PID_PARSER10_CTRL1 :: PARSER_INPUT_SEL_MSB [21:21] */
-#define BCHP_XPT_FE_MINI_PID_PARSER10_CTRL1_PARSER_INPUT_SEL_MSB_MASK 0x00200000
-#define BCHP_XPT_FE_MINI_PID_PARSER10_CTRL1_PARSER_INPUT_SEL_MSB_SHIFT 21
-#define BCHP_XPT_FE_MINI_PID_PARSER10_CTRL1_PARSER_INPUT_SEL_MSB_DEFAULT 0x00000000
-
-/* XPT_FE :: MINI_PID_PARSER10_CTRL1 :: PARSER_ERROR_INPUT_TEI_IGNORE [20:20] */
-#define BCHP_XPT_FE_MINI_PID_PARSER10_CTRL1_PARSER_ERROR_INPUT_TEI_IGNORE_MASK 0x00100000
-#define BCHP_XPT_FE_MINI_PID_PARSER10_CTRL1_PARSER_ERROR_INPUT_TEI_IGNORE_SHIFT 20
-#define BCHP_XPT_FE_MINI_PID_PARSER10_CTRL1_PARSER_ERROR_INPUT_TEI_IGNORE_DEFAULT 0x00000000
-
-/* XPT_FE :: MINI_PID_PARSER10_CTRL1 :: PARSER_PKT_LENGTH [19:12] */
-#define BCHP_XPT_FE_MINI_PID_PARSER10_CTRL1_PARSER_PKT_LENGTH_MASK 0x000ff000
-#define BCHP_XPT_FE_MINI_PID_PARSER10_CTRL1_PARSER_PKT_LENGTH_SHIFT 12
-#define BCHP_XPT_FE_MINI_PID_PARSER10_CTRL1_PARSER_PKT_LENGTH_DEFAULT 0x000000bc
-
-/* XPT_FE :: MINI_PID_PARSER10_CTRL1 :: PARSER_INPUT_SEL [11:08] */
-#define BCHP_XPT_FE_MINI_PID_PARSER10_CTRL1_PARSER_INPUT_SEL_MASK 0x00000f00
-#define BCHP_XPT_FE_MINI_PID_PARSER10_CTRL1_PARSER_INPUT_SEL_SHIFT 8
-#define BCHP_XPT_FE_MINI_PID_PARSER10_CTRL1_PARSER_INPUT_SEL_DEFAULT 0x00000000
-
-/* XPT_FE :: MINI_PID_PARSER10_CTRL1 :: reserved1 [07:07] */
-#define BCHP_XPT_FE_MINI_PID_PARSER10_CTRL1_reserved1_MASK 0x00000080
-#define BCHP_XPT_FE_MINI_PID_PARSER10_CTRL1_reserved1_SHIFT 7
-
-/* XPT_FE :: MINI_PID_PARSER10_CTRL1 :: PARSER_PACKET_TYPE [06:05] */
-#define BCHP_XPT_FE_MINI_PID_PARSER10_CTRL1_PARSER_PACKET_TYPE_MASK 0x00000060
-#define BCHP_XPT_FE_MINI_PID_PARSER10_CTRL1_PARSER_PACKET_TYPE_SHIFT 5
-#define BCHP_XPT_FE_MINI_PID_PARSER10_CTRL1_PARSER_PACKET_TYPE_DEFAULT 0x00000000
-
-/* XPT_FE :: MINI_PID_PARSER10_CTRL1 :: PARSER_ACCEPT_NULL_PKT_PRE_MPOD [04:04] */
-#define BCHP_XPT_FE_MINI_PID_PARSER10_CTRL1_PARSER_ACCEPT_NULL_PKT_PRE_MPOD_MASK 0x00000010
-#define BCHP_XPT_FE_MINI_PID_PARSER10_CTRL1_PARSER_ACCEPT_NULL_PKT_PRE_MPOD_SHIFT 4
-#define BCHP_XPT_FE_MINI_PID_PARSER10_CTRL1_PARSER_ACCEPT_NULL_PKT_PRE_MPOD_DEFAULT 0x00000000
-
-/* XPT_FE :: MINI_PID_PARSER10_CTRL1 :: PARSER_ACCEPT_NULL_PKT_PRE_TSIO [03:03] */
-#define BCHP_XPT_FE_MINI_PID_PARSER10_CTRL1_PARSER_ACCEPT_NULL_PKT_PRE_TSIO_MASK 0x00000008
-#define BCHP_XPT_FE_MINI_PID_PARSER10_CTRL1_PARSER_ACCEPT_NULL_PKT_PRE_TSIO_SHIFT 3
-#define BCHP_XPT_FE_MINI_PID_PARSER10_CTRL1_PARSER_ACCEPT_NULL_PKT_PRE_TSIO_DEFAULT 0x00000000
-
-/* XPT_FE :: MINI_PID_PARSER10_CTRL1 :: PARSER_ALL_PASS_CTRL_PRE_TSIO [02:02] */
-#define BCHP_XPT_FE_MINI_PID_PARSER10_CTRL1_PARSER_ALL_PASS_CTRL_PRE_TSIO_MASK 0x00000004
-#define BCHP_XPT_FE_MINI_PID_PARSER10_CTRL1_PARSER_ALL_PASS_CTRL_PRE_TSIO_SHIFT 2
-#define BCHP_XPT_FE_MINI_PID_PARSER10_CTRL1_PARSER_ALL_PASS_CTRL_PRE_TSIO_DEFAULT 0x00000000
-
-/* XPT_FE :: MINI_PID_PARSER10_CTRL1 :: PARSER_ALL_PASS_CTRL_PRE_MPOD [01:01] */
-#define BCHP_XPT_FE_MINI_PID_PARSER10_CTRL1_PARSER_ALL_PASS_CTRL_PRE_MPOD_MASK 0x00000002
-#define BCHP_XPT_FE_MINI_PID_PARSER10_CTRL1_PARSER_ALL_PASS_CTRL_PRE_MPOD_SHIFT 1
-#define BCHP_XPT_FE_MINI_PID_PARSER10_CTRL1_PARSER_ALL_PASS_CTRL_PRE_MPOD_DEFAULT 0x00000000
-
-/* XPT_FE :: MINI_PID_PARSER10_CTRL1 :: PARSER_ENABLE [00:00] */
-#define BCHP_XPT_FE_MINI_PID_PARSER10_CTRL1_PARSER_ENABLE_MASK 0x00000001
-#define BCHP_XPT_FE_MINI_PID_PARSER10_CTRL1_PARSER_ENABLE_SHIFT 0
-#define BCHP_XPT_FE_MINI_PID_PARSER10_CTRL1_PARSER_ENABLE_DEFAULT 0x00000000
-
-/***************************************************************************
- *MINI_PID_PARSER10_CTRL2 - Data Transport Parser Band 10 Control Register 2
- ***************************************************************************/
-/* XPT_FE :: MINI_PID_PARSER10_CTRL2 :: reserved0 [31:14] */
-#define BCHP_XPT_FE_MINI_PID_PARSER10_CTRL2_reserved0_MASK 0xffffc000
-#define BCHP_XPT_FE_MINI_PID_PARSER10_CTRL2_reserved0_SHIFT 14
-
-/* XPT_FE :: MINI_PID_PARSER10_CTRL2 :: PARSER_STREAM_TIMESTAMP_EN [13:13] */
-#define BCHP_XPT_FE_MINI_PID_PARSER10_CTRL2_PARSER_STREAM_TIMESTAMP_EN_MASK 0x00002000
-#define BCHP_XPT_FE_MINI_PID_PARSER10_CTRL2_PARSER_STREAM_TIMESTAMP_EN_SHIFT 13
-#define BCHP_XPT_FE_MINI_PID_PARSER10_CTRL2_PARSER_STREAM_TIMESTAMP_EN_DEFAULT 0x00000000
-
-/* XPT_FE :: MINI_PID_PARSER10_CTRL2 :: PARSER_TIMESTREAM_BF_SYNC [12:12] */
-#define BCHP_XPT_FE_MINI_PID_PARSER10_CTRL2_PARSER_TIMESTREAM_BF_SYNC_MASK 0x00001000
-#define BCHP_XPT_FE_MINI_PID_PARSER10_CTRL2_PARSER_TIMESTREAM_BF_SYNC_SHIFT 12
-#define BCHP_XPT_FE_MINI_PID_PARSER10_CTRL2_PARSER_TIMESTREAM_BF_SYNC_DEFAULT 0x00000000
-
-/* XPT_FE :: MINI_PID_PARSER10_CTRL2 :: reserved1 [11:11] */
-#define BCHP_XPT_FE_MINI_PID_PARSER10_CTRL2_reserved1_MASK 0x00000800
-#define BCHP_XPT_FE_MINI_PID_PARSER10_CTRL2_reserved1_SHIFT 11
-
-/* XPT_FE :: MINI_PID_PARSER10_CTRL2 :: PARSER_TIMESTAMP_RESTAMP [10:10] */
-#define BCHP_XPT_FE_MINI_PID_PARSER10_CTRL2_PARSER_TIMESTAMP_RESTAMP_MASK 0x00000400
-#define BCHP_XPT_FE_MINI_PID_PARSER10_CTRL2_PARSER_TIMESTAMP_RESTAMP_SHIFT 10
-#define BCHP_XPT_FE_MINI_PID_PARSER10_CTRL2_PARSER_TIMESTAMP_RESTAMP_DEFAULT 0x00000001
-
-/* XPT_FE :: MINI_PID_PARSER10_CTRL2 :: TSIO_MODE_SEL [09:09] */
-#define BCHP_XPT_FE_MINI_PID_PARSER10_CTRL2_TSIO_MODE_SEL_MASK 0x00000200
-#define BCHP_XPT_FE_MINI_PID_PARSER10_CTRL2_TSIO_MODE_SEL_SHIFT 9
-#define BCHP_XPT_FE_MINI_PID_PARSER10_CTRL2_TSIO_MODE_SEL_DEFAULT 0x00000001
-
-/* XPT_FE :: MINI_PID_PARSER10_CTRL2 :: reserved2 [08:07] */
-#define BCHP_XPT_FE_MINI_PID_PARSER10_CTRL2_reserved2_MASK 0x00000180
-#define BCHP_XPT_FE_MINI_PID_PARSER10_CTRL2_reserved2_SHIFT 7
-
-/* XPT_FE :: MINI_PID_PARSER10_CTRL2 :: TSIO_EN [06:06] */
-#define BCHP_XPT_FE_MINI_PID_PARSER10_CTRL2_TSIO_EN_MASK 0x00000040
-#define BCHP_XPT_FE_MINI_PID_PARSER10_CTRL2_TSIO_EN_SHIFT 6
-#define BCHP_XPT_FE_MINI_PID_PARSER10_CTRL2_TSIO_EN_DEFAULT 0x00000000
-
-/* XPT_FE :: MINI_PID_PARSER10_CTRL2 :: reserved3 [05:05] */
-#define BCHP_XPT_FE_MINI_PID_PARSER10_CTRL2_reserved3_MASK 0x00000020
-#define BCHP_XPT_FE_MINI_PID_PARSER10_CTRL2_reserved3_SHIFT 5
-
-/* XPT_FE :: MINI_PID_PARSER10_CTRL2 :: MPOD_MODE_SEL [04:04] */
-#define BCHP_XPT_FE_MINI_PID_PARSER10_CTRL2_MPOD_MODE_SEL_MASK 0x00000010
-#define BCHP_XPT_FE_MINI_PID_PARSER10_CTRL2_MPOD_MODE_SEL_SHIFT 4
-#define BCHP_XPT_FE_MINI_PID_PARSER10_CTRL2_MPOD_MODE_SEL_DEFAULT 0x00000000
-
-/* XPT_FE :: MINI_PID_PARSER10_CTRL2 :: reserved4 [03:03] */
-#define BCHP_XPT_FE_MINI_PID_PARSER10_CTRL2_reserved4_MASK 0x00000008
-#define BCHP_XPT_FE_MINI_PID_PARSER10_CTRL2_reserved4_SHIFT 3
-
-/* XPT_FE :: MINI_PID_PARSER10_CTRL2 :: PARSER_ACCEPT_NULL_PKT_POST_MPOD [02:02] */
-#define BCHP_XPT_FE_MINI_PID_PARSER10_CTRL2_PARSER_ACCEPT_NULL_PKT_POST_MPOD_MASK 0x00000004
-#define BCHP_XPT_FE_MINI_PID_PARSER10_CTRL2_PARSER_ACCEPT_NULL_PKT_POST_MPOD_SHIFT 2
-#define BCHP_XPT_FE_MINI_PID_PARSER10_CTRL2_PARSER_ACCEPT_NULL_PKT_POST_MPOD_DEFAULT 0x00000000
-
-/* XPT_FE :: MINI_PID_PARSER10_CTRL2 :: PARSER_ALL_PASS_CTRL_POST_MPOD [01:01] */
-#define BCHP_XPT_FE_MINI_PID_PARSER10_CTRL2_PARSER_ALL_PASS_CTRL_POST_MPOD_MASK 0x00000002
-#define BCHP_XPT_FE_MINI_PID_PARSER10_CTRL2_PARSER_ALL_PASS_CTRL_POST_MPOD_SHIFT 1
-#define BCHP_XPT_FE_MINI_PID_PARSER10_CTRL2_PARSER_ALL_PASS_CTRL_POST_MPOD_DEFAULT 0x00000000
-
-/* XPT_FE :: MINI_PID_PARSER10_CTRL2 :: MPOD_EN [00:00] */
-#define BCHP_XPT_FE_MINI_PID_PARSER10_CTRL2_MPOD_EN_MASK 0x00000001
-#define BCHP_XPT_FE_MINI_PID_PARSER10_CTRL2_MPOD_EN_SHIFT 0
-#define BCHP_XPT_FE_MINI_PID_PARSER10_CTRL2_MPOD_EN_DEFAULT 0x00000000
-
-/***************************************************************************
- *MINI_PID_PARSER10_ALL_PASS_CTRL - Data Transport Parser Band 10 Control Register
- ***************************************************************************/
-/* XPT_FE :: MINI_PID_PARSER10_ALL_PASS_CTRL :: reserved0 [31:13] */
-#define BCHP_XPT_FE_MINI_PID_PARSER10_ALL_PASS_CTRL_reserved0_MASK 0xffffe000
-#define BCHP_XPT_FE_MINI_PID_PARSER10_ALL_PASS_CTRL_reserved0_SHIFT 13
-
-/* XPT_FE :: MINI_PID_PARSER10_ALL_PASS_CTRL :: PIDP_DEBUG_MODE [12:12] */
-#define BCHP_XPT_FE_MINI_PID_PARSER10_ALL_PASS_CTRL_PIDP_DEBUG_MODE_MASK 0x00001000
-#define BCHP_XPT_FE_MINI_PID_PARSER10_ALL_PASS_CTRL_PIDP_DEBUG_MODE_SHIFT 12
-#define BCHP_XPT_FE_MINI_PID_PARSER10_ALL_PASS_CTRL_PIDP_DEBUG_MODE_DEFAULT 0x00000000
-
-/* XPT_FE :: MINI_PID_PARSER10_ALL_PASS_CTRL :: ALL_PASS_PID_CH_NUM [11:00] */
-#define BCHP_XPT_FE_MINI_PID_PARSER10_ALL_PASS_CTRL_ALL_PASS_PID_CH_NUM_MASK 0x00000fff
-#define BCHP_XPT_FE_MINI_PID_PARSER10_ALL_PASS_CTRL_ALL_PASS_PID_CH_NUM_SHIFT 0
-#define BCHP_XPT_FE_MINI_PID_PARSER10_ALL_PASS_CTRL_ALL_PASS_PID_CH_NUM_DEFAULT 0x0000000a
-
-/***************************************************************************
- *MINI_PID_PARSER11_CTRL1 - Data Transport Parser Band 11 Control Register
- ***************************************************************************/
-/* XPT_FE :: MINI_PID_PARSER11_CTRL1 :: reserved0 [31:29] */
-#define BCHP_XPT_FE_MINI_PID_PARSER11_CTRL1_reserved0_MASK 0xe0000000
-#define BCHP_XPT_FE_MINI_PID_PARSER11_CTRL1_reserved0_SHIFT 29
-
-/* XPT_FE :: MINI_PID_PARSER11_CTRL1 :: PARSER_TIMESTAMP_MODE [28:27] */
-#define BCHP_XPT_FE_MINI_PID_PARSER11_CTRL1_PARSER_TIMESTAMP_MODE_MASK 0x18000000
-#define BCHP_XPT_FE_MINI_PID_PARSER11_CTRL1_PARSER_TIMESTAMP_MODE_SHIFT 27
-#define BCHP_XPT_FE_MINI_PID_PARSER11_CTRL1_PARSER_TIMESTAMP_MODE_DEFAULT 0x00000002
-
-/* XPT_FE :: MINI_PID_PARSER11_CTRL1 :: PARSER_TSMF_SEL [26:23] */
-#define BCHP_XPT_FE_MINI_PID_PARSER11_CTRL1_PARSER_TSMF_SEL_MASK 0x07800000
-#define BCHP_XPT_FE_MINI_PID_PARSER11_CTRL1_PARSER_TSMF_SEL_SHIFT 23
-#define BCHP_XPT_FE_MINI_PID_PARSER11_CTRL1_PARSER_TSMF_SEL_DEFAULT 0x00000000
-
-/* XPT_FE :: MINI_PID_PARSER11_CTRL1 :: PARSER_TSMF_EN [22:22] */
-#define BCHP_XPT_FE_MINI_PID_PARSER11_CTRL1_PARSER_TSMF_EN_MASK 0x00400000
-#define BCHP_XPT_FE_MINI_PID_PARSER11_CTRL1_PARSER_TSMF_EN_SHIFT 22
-#define BCHP_XPT_FE_MINI_PID_PARSER11_CTRL1_PARSER_TSMF_EN_DEFAULT 0x00000000
-
-/* XPT_FE :: MINI_PID_PARSER11_CTRL1 :: PARSER_INPUT_SEL_MSB [21:21] */
-#define BCHP_XPT_FE_MINI_PID_PARSER11_CTRL1_PARSER_INPUT_SEL_MSB_MASK 0x00200000
-#define BCHP_XPT_FE_MINI_PID_PARSER11_CTRL1_PARSER_INPUT_SEL_MSB_SHIFT 21
-#define BCHP_XPT_FE_MINI_PID_PARSER11_CTRL1_PARSER_INPUT_SEL_MSB_DEFAULT 0x00000000
-
-/* XPT_FE :: MINI_PID_PARSER11_CTRL1 :: PARSER_ERROR_INPUT_TEI_IGNORE [20:20] */
-#define BCHP_XPT_FE_MINI_PID_PARSER11_CTRL1_PARSER_ERROR_INPUT_TEI_IGNORE_MASK 0x00100000
-#define BCHP_XPT_FE_MINI_PID_PARSER11_CTRL1_PARSER_ERROR_INPUT_TEI_IGNORE_SHIFT 20
-#define BCHP_XPT_FE_MINI_PID_PARSER11_CTRL1_PARSER_ERROR_INPUT_TEI_IGNORE_DEFAULT 0x00000000
-
-/* XPT_FE :: MINI_PID_PARSER11_CTRL1 :: PARSER_PKT_LENGTH [19:12] */
-#define BCHP_XPT_FE_MINI_PID_PARSER11_CTRL1_PARSER_PKT_LENGTH_MASK 0x000ff000
-#define BCHP_XPT_FE_MINI_PID_PARSER11_CTRL1_PARSER_PKT_LENGTH_SHIFT 12
-#define BCHP_XPT_FE_MINI_PID_PARSER11_CTRL1_PARSER_PKT_LENGTH_DEFAULT 0x000000bc
-
-/* XPT_FE :: MINI_PID_PARSER11_CTRL1 :: PARSER_INPUT_SEL [11:08] */
-#define BCHP_XPT_FE_MINI_PID_PARSER11_CTRL1_PARSER_INPUT_SEL_MASK 0x00000f00
-#define BCHP_XPT_FE_MINI_PID_PARSER11_CTRL1_PARSER_INPUT_SEL_SHIFT 8
-#define BCHP_XPT_FE_MINI_PID_PARSER11_CTRL1_PARSER_INPUT_SEL_DEFAULT 0x00000000
-
-/* XPT_FE :: MINI_PID_PARSER11_CTRL1 :: reserved1 [07:07] */
-#define BCHP_XPT_FE_MINI_PID_PARSER11_CTRL1_reserved1_MASK 0x00000080
-#define BCHP_XPT_FE_MINI_PID_PARSER11_CTRL1_reserved1_SHIFT 7
-
-/* XPT_FE :: MINI_PID_PARSER11_CTRL1 :: PARSER_PACKET_TYPE [06:05] */
-#define BCHP_XPT_FE_MINI_PID_PARSER11_CTRL1_PARSER_PACKET_TYPE_MASK 0x00000060
-#define BCHP_XPT_FE_MINI_PID_PARSER11_CTRL1_PARSER_PACKET_TYPE_SHIFT 5
-#define BCHP_XPT_FE_MINI_PID_PARSER11_CTRL1_PARSER_PACKET_TYPE_DEFAULT 0x00000000
-
-/* XPT_FE :: MINI_PID_PARSER11_CTRL1 :: PARSER_ACCEPT_NULL_PKT_PRE_MPOD [04:04] */
-#define BCHP_XPT_FE_MINI_PID_PARSER11_CTRL1_PARSER_ACCEPT_NULL_PKT_PRE_MPOD_MASK 0x00000010
-#define BCHP_XPT_FE_MINI_PID_PARSER11_CTRL1_PARSER_ACCEPT_NULL_PKT_PRE_MPOD_SHIFT 4
-#define BCHP_XPT_FE_MINI_PID_PARSER11_CTRL1_PARSER_ACCEPT_NULL_PKT_PRE_MPOD_DEFAULT 0x00000000
-
-/* XPT_FE :: MINI_PID_PARSER11_CTRL1 :: PARSER_ACCEPT_NULL_PKT_PRE_TSIO [03:03] */
-#define BCHP_XPT_FE_MINI_PID_PARSER11_CTRL1_PARSER_ACCEPT_NULL_PKT_PRE_TSIO_MASK 0x00000008
-#define BCHP_XPT_FE_MINI_PID_PARSER11_CTRL1_PARSER_ACCEPT_NULL_PKT_PRE_TSIO_SHIFT 3
-#define BCHP_XPT_FE_MINI_PID_PARSER11_CTRL1_PARSER_ACCEPT_NULL_PKT_PRE_TSIO_DEFAULT 0x00000000
-
-/* XPT_FE :: MINI_PID_PARSER11_CTRL1 :: PARSER_ALL_PASS_CTRL_PRE_TSIO [02:02] */
-#define BCHP_XPT_FE_MINI_PID_PARSER11_CTRL1_PARSER_ALL_PASS_CTRL_PRE_TSIO_MASK 0x00000004
-#define BCHP_XPT_FE_MINI_PID_PARSER11_CTRL1_PARSER_ALL_PASS_CTRL_PRE_TSIO_SHIFT 2
-#define BCHP_XPT_FE_MINI_PID_PARSER11_CTRL1_PARSER_ALL_PASS_CTRL_PRE_TSIO_DEFAULT 0x00000000
-
-/* XPT_FE :: MINI_PID_PARSER11_CTRL1 :: PARSER_ALL_PASS_CTRL_PRE_MPOD [01:01] */
-#define BCHP_XPT_FE_MINI_PID_PARSER11_CTRL1_PARSER_ALL_PASS_CTRL_PRE_MPOD_MASK 0x00000002
-#define BCHP_XPT_FE_MINI_PID_PARSER11_CTRL1_PARSER_ALL_PASS_CTRL_PRE_MPOD_SHIFT 1
-#define BCHP_XPT_FE_MINI_PID_PARSER11_CTRL1_PARSER_ALL_PASS_CTRL_PRE_MPOD_DEFAULT 0x00000000
-
-/* XPT_FE :: MINI_PID_PARSER11_CTRL1 :: PARSER_ENABLE [00:00] */
-#define BCHP_XPT_FE_MINI_PID_PARSER11_CTRL1_PARSER_ENABLE_MASK 0x00000001
-#define BCHP_XPT_FE_MINI_PID_PARSER11_CTRL1_PARSER_ENABLE_SHIFT 0
-#define BCHP_XPT_FE_MINI_PID_PARSER11_CTRL1_PARSER_ENABLE_DEFAULT 0x00000000
-
-/***************************************************************************
- *MINI_PID_PARSER11_CTRL2 - Data Transport Parser Band 11 Control Register 2
- ***************************************************************************/
-/* XPT_FE :: MINI_PID_PARSER11_CTRL2 :: reserved0 [31:14] */
-#define BCHP_XPT_FE_MINI_PID_PARSER11_CTRL2_reserved0_MASK 0xffffc000
-#define BCHP_XPT_FE_MINI_PID_PARSER11_CTRL2_reserved0_SHIFT 14
-
-/* XPT_FE :: MINI_PID_PARSER11_CTRL2 :: PARSER_STREAM_TIMESTAMP_EN [13:13] */
-#define BCHP_XPT_FE_MINI_PID_PARSER11_CTRL2_PARSER_STREAM_TIMESTAMP_EN_MASK 0x00002000
-#define BCHP_XPT_FE_MINI_PID_PARSER11_CTRL2_PARSER_STREAM_TIMESTAMP_EN_SHIFT 13
-#define BCHP_XPT_FE_MINI_PID_PARSER11_CTRL2_PARSER_STREAM_TIMESTAMP_EN_DEFAULT 0x00000000
-
-/* XPT_FE :: MINI_PID_PARSER11_CTRL2 :: PARSER_TIMESTREAM_BF_SYNC [12:12] */
-#define BCHP_XPT_FE_MINI_PID_PARSER11_CTRL2_PARSER_TIMESTREAM_BF_SYNC_MASK 0x00001000
-#define BCHP_XPT_FE_MINI_PID_PARSER11_CTRL2_PARSER_TIMESTREAM_BF_SYNC_SHIFT 12
-#define BCHP_XPT_FE_MINI_PID_PARSER11_CTRL2_PARSER_TIMESTREAM_BF_SYNC_DEFAULT 0x00000000
-
-/* XPT_FE :: MINI_PID_PARSER11_CTRL2 :: reserved1 [11:11] */
-#define BCHP_XPT_FE_MINI_PID_PARSER11_CTRL2_reserved1_MASK 0x00000800
-#define BCHP_XPT_FE_MINI_PID_PARSER11_CTRL2_reserved1_SHIFT 11
-
-/* XPT_FE :: MINI_PID_PARSER11_CTRL2 :: PARSER_TIMESTAMP_RESTAMP [10:10] */
-#define BCHP_XPT_FE_MINI_PID_PARSER11_CTRL2_PARSER_TIMESTAMP_RESTAMP_MASK 0x00000400
-#define BCHP_XPT_FE_MINI_PID_PARSER11_CTRL2_PARSER_TIMESTAMP_RESTAMP_SHIFT 10
-#define BCHP_XPT_FE_MINI_PID_PARSER11_CTRL2_PARSER_TIMESTAMP_RESTAMP_DEFAULT 0x00000001
-
-/* XPT_FE :: MINI_PID_PARSER11_CTRL2 :: TSIO_MODE_SEL [09:09] */
-#define BCHP_XPT_FE_MINI_PID_PARSER11_CTRL2_TSIO_MODE_SEL_MASK 0x00000200
-#define BCHP_XPT_FE_MINI_PID_PARSER11_CTRL2_TSIO_MODE_SEL_SHIFT 9
-#define BCHP_XPT_FE_MINI_PID_PARSER11_CTRL2_TSIO_MODE_SEL_DEFAULT 0x00000001
-
-/* XPT_FE :: MINI_PID_PARSER11_CTRL2 :: reserved2 [08:07] */
-#define BCHP_XPT_FE_MINI_PID_PARSER11_CTRL2_reserved2_MASK 0x00000180
-#define BCHP_XPT_FE_MINI_PID_PARSER11_CTRL2_reserved2_SHIFT 7
-
-/* XPT_FE :: MINI_PID_PARSER11_CTRL2 :: TSIO_EN [06:06] */
-#define BCHP_XPT_FE_MINI_PID_PARSER11_CTRL2_TSIO_EN_MASK 0x00000040
-#define BCHP_XPT_FE_MINI_PID_PARSER11_CTRL2_TSIO_EN_SHIFT 6
-#define BCHP_XPT_FE_MINI_PID_PARSER11_CTRL2_TSIO_EN_DEFAULT 0x00000000
-
-/* XPT_FE :: MINI_PID_PARSER11_CTRL2 :: reserved3 [05:05] */
-#define BCHP_XPT_FE_MINI_PID_PARSER11_CTRL2_reserved3_MASK 0x00000020
-#define BCHP_XPT_FE_MINI_PID_PARSER11_CTRL2_reserved3_SHIFT 5
-
-/* XPT_FE :: MINI_PID_PARSER11_CTRL2 :: MPOD_MODE_SEL [04:04] */
-#define BCHP_XPT_FE_MINI_PID_PARSER11_CTRL2_MPOD_MODE_SEL_MASK 0x00000010
-#define BCHP_XPT_FE_MINI_PID_PARSER11_CTRL2_MPOD_MODE_SEL_SHIFT 4
-#define BCHP_XPT_FE_MINI_PID_PARSER11_CTRL2_MPOD_MODE_SEL_DEFAULT 0x00000000
-
-/* XPT_FE :: MINI_PID_PARSER11_CTRL2 :: reserved4 [03:03] */
-#define BCHP_XPT_FE_MINI_PID_PARSER11_CTRL2_reserved4_MASK 0x00000008
-#define BCHP_XPT_FE_MINI_PID_PARSER11_CTRL2_reserved4_SHIFT 3
-
-/* XPT_FE :: MINI_PID_PARSER11_CTRL2 :: PARSER_ACCEPT_NULL_PKT_POST_MPOD [02:02] */
-#define BCHP_XPT_FE_MINI_PID_PARSER11_CTRL2_PARSER_ACCEPT_NULL_PKT_POST_MPOD_MASK 0x00000004
-#define BCHP_XPT_FE_MINI_PID_PARSER11_CTRL2_PARSER_ACCEPT_NULL_PKT_POST_MPOD_SHIFT 2
-#define BCHP_XPT_FE_MINI_PID_PARSER11_CTRL2_PARSER_ACCEPT_NULL_PKT_POST_MPOD_DEFAULT 0x00000000
-
-/* XPT_FE :: MINI_PID_PARSER11_CTRL2 :: PARSER_ALL_PASS_CTRL_POST_MPOD [01:01] */
-#define BCHP_XPT_FE_MINI_PID_PARSER11_CTRL2_PARSER_ALL_PASS_CTRL_POST_MPOD_MASK 0x00000002
-#define BCHP_XPT_FE_MINI_PID_PARSER11_CTRL2_PARSER_ALL_PASS_CTRL_POST_MPOD_SHIFT 1
-#define BCHP_XPT_FE_MINI_PID_PARSER11_CTRL2_PARSER_ALL_PASS_CTRL_POST_MPOD_DEFAULT 0x00000000
-
-/* XPT_FE :: MINI_PID_PARSER11_CTRL2 :: MPOD_EN [00:00] */
-#define BCHP_XPT_FE_MINI_PID_PARSER11_CTRL2_MPOD_EN_MASK 0x00000001
-#define BCHP_XPT_FE_MINI_PID_PARSER11_CTRL2_MPOD_EN_SHIFT 0
-#define BCHP_XPT_FE_MINI_PID_PARSER11_CTRL2_MPOD_EN_DEFAULT 0x00000000
-
-/***************************************************************************
- *MINI_PID_PARSER11_ALL_PASS_CTRL - Data Transport Parser Band 11 Control Register
- ***************************************************************************/
-/* XPT_FE :: MINI_PID_PARSER11_ALL_PASS_CTRL :: reserved0 [31:13] */
-#define BCHP_XPT_FE_MINI_PID_PARSER11_ALL_PASS_CTRL_reserved0_MASK 0xffffe000
-#define BCHP_XPT_FE_MINI_PID_PARSER11_ALL_PASS_CTRL_reserved0_SHIFT 13
-
-/* XPT_FE :: MINI_PID_PARSER11_ALL_PASS_CTRL :: PIDP_DEBUG_MODE [12:12] */
-#define BCHP_XPT_FE_MINI_PID_PARSER11_ALL_PASS_CTRL_PIDP_DEBUG_MODE_MASK 0x00001000
-#define BCHP_XPT_FE_MINI_PID_PARSER11_ALL_PASS_CTRL_PIDP_DEBUG_MODE_SHIFT 12
-#define BCHP_XPT_FE_MINI_PID_PARSER11_ALL_PASS_CTRL_PIDP_DEBUG_MODE_DEFAULT 0x00000000
-
-/* XPT_FE :: MINI_PID_PARSER11_ALL_PASS_CTRL :: ALL_PASS_PID_CH_NUM [11:00] */
-#define BCHP_XPT_FE_MINI_PID_PARSER11_ALL_PASS_CTRL_ALL_PASS_PID_CH_NUM_MASK 0x00000fff
-#define BCHP_XPT_FE_MINI_PID_PARSER11_ALL_PASS_CTRL_ALL_PASS_PID_CH_NUM_SHIFT 0
-#define BCHP_XPT_FE_MINI_PID_PARSER11_ALL_PASS_CTRL_ALL_PASS_PID_CH_NUM_DEFAULT 0x0000000b
-
-/***************************************************************************
- *MINI_PID_PARSER12_CTRL1 - Data Transport Parser Band 12 Control Register
- ***************************************************************************/
-/* XPT_FE :: MINI_PID_PARSER12_CTRL1 :: reserved0 [31:29] */
-#define BCHP_XPT_FE_MINI_PID_PARSER12_CTRL1_reserved0_MASK 0xe0000000
-#define BCHP_XPT_FE_MINI_PID_PARSER12_CTRL1_reserved0_SHIFT 29
-
-/* XPT_FE :: MINI_PID_PARSER12_CTRL1 :: PARSER_TIMESTAMP_MODE [28:27] */
-#define BCHP_XPT_FE_MINI_PID_PARSER12_CTRL1_PARSER_TIMESTAMP_MODE_MASK 0x18000000
-#define BCHP_XPT_FE_MINI_PID_PARSER12_CTRL1_PARSER_TIMESTAMP_MODE_SHIFT 27
-#define BCHP_XPT_FE_MINI_PID_PARSER12_CTRL1_PARSER_TIMESTAMP_MODE_DEFAULT 0x00000002
-
-/* XPT_FE :: MINI_PID_PARSER12_CTRL1 :: PARSER_TSMF_SEL [26:23] */
-#define BCHP_XPT_FE_MINI_PID_PARSER12_CTRL1_PARSER_TSMF_SEL_MASK 0x07800000
-#define BCHP_XPT_FE_MINI_PID_PARSER12_CTRL1_PARSER_TSMF_SEL_SHIFT 23
-#define BCHP_XPT_FE_MINI_PID_PARSER12_CTRL1_PARSER_TSMF_SEL_DEFAULT 0x00000000
-
-/* XPT_FE :: MINI_PID_PARSER12_CTRL1 :: PARSER_TSMF_EN [22:22] */
-#define BCHP_XPT_FE_MINI_PID_PARSER12_CTRL1_PARSER_TSMF_EN_MASK 0x00400000
-#define BCHP_XPT_FE_MINI_PID_PARSER12_CTRL1_PARSER_TSMF_EN_SHIFT 22
-#define BCHP_XPT_FE_MINI_PID_PARSER12_CTRL1_PARSER_TSMF_EN_DEFAULT 0x00000000
-
-/* XPT_FE :: MINI_PID_PARSER12_CTRL1 :: PARSER_INPUT_SEL_MSB [21:21] */
-#define BCHP_XPT_FE_MINI_PID_PARSER12_CTRL1_PARSER_INPUT_SEL_MSB_MASK 0x00200000
-#define BCHP_XPT_FE_MINI_PID_PARSER12_CTRL1_PARSER_INPUT_SEL_MSB_SHIFT 21
-#define BCHP_XPT_FE_MINI_PID_PARSER12_CTRL1_PARSER_INPUT_SEL_MSB_DEFAULT 0x00000000
-
-/* XPT_FE :: MINI_PID_PARSER12_CTRL1 :: PARSER_ERROR_INPUT_TEI_IGNORE [20:20] */
-#define BCHP_XPT_FE_MINI_PID_PARSER12_CTRL1_PARSER_ERROR_INPUT_TEI_IGNORE_MASK 0x00100000
-#define BCHP_XPT_FE_MINI_PID_PARSER12_CTRL1_PARSER_ERROR_INPUT_TEI_IGNORE_SHIFT 20
-#define BCHP_XPT_FE_MINI_PID_PARSER12_CTRL1_PARSER_ERROR_INPUT_TEI_IGNORE_DEFAULT 0x00000000
-
-/* XPT_FE :: MINI_PID_PARSER12_CTRL1 :: PARSER_PKT_LENGTH [19:12] */
-#define BCHP_XPT_FE_MINI_PID_PARSER12_CTRL1_PARSER_PKT_LENGTH_MASK 0x000ff000
-#define BCHP_XPT_FE_MINI_PID_PARSER12_CTRL1_PARSER_PKT_LENGTH_SHIFT 12
-#define BCHP_XPT_FE_MINI_PID_PARSER12_CTRL1_PARSER_PKT_LENGTH_DEFAULT 0x000000bc
-
-/* XPT_FE :: MINI_PID_PARSER12_CTRL1 :: PARSER_INPUT_SEL [11:08] */
-#define BCHP_XPT_FE_MINI_PID_PARSER12_CTRL1_PARSER_INPUT_SEL_MASK 0x00000f00
-#define BCHP_XPT_FE_MINI_PID_PARSER12_CTRL1_PARSER_INPUT_SEL_SHIFT 8
-#define BCHP_XPT_FE_MINI_PID_PARSER12_CTRL1_PARSER_INPUT_SEL_DEFAULT 0x00000000
-
-/* XPT_FE :: MINI_PID_PARSER12_CTRL1 :: reserved1 [07:07] */
-#define BCHP_XPT_FE_MINI_PID_PARSER12_CTRL1_reserved1_MASK 0x00000080
-#define BCHP_XPT_FE_MINI_PID_PARSER12_CTRL1_reserved1_SHIFT 7
-
-/* XPT_FE :: MINI_PID_PARSER12_CTRL1 :: PARSER_PACKET_TYPE [06:05] */
-#define BCHP_XPT_FE_MINI_PID_PARSER12_CTRL1_PARSER_PACKET_TYPE_MASK 0x00000060
-#define BCHP_XPT_FE_MINI_PID_PARSER12_CTRL1_PARSER_PACKET_TYPE_SHIFT 5
-#define BCHP_XPT_FE_MINI_PID_PARSER12_CTRL1_PARSER_PACKET_TYPE_DEFAULT 0x00000000
-
-/* XPT_FE :: MINI_PID_PARSER12_CTRL1 :: PARSER_ACCEPT_NULL_PKT_PRE_MPOD [04:04] */
-#define BCHP_XPT_FE_MINI_PID_PARSER12_CTRL1_PARSER_ACCEPT_NULL_PKT_PRE_MPOD_MASK 0x00000010
-#define BCHP_XPT_FE_MINI_PID_PARSER12_CTRL1_PARSER_ACCEPT_NULL_PKT_PRE_MPOD_SHIFT 4
-#define BCHP_XPT_FE_MINI_PID_PARSER12_CTRL1_PARSER_ACCEPT_NULL_PKT_PRE_MPOD_DEFAULT 0x00000000
-
-/* XPT_FE :: MINI_PID_PARSER12_CTRL1 :: PARSER_ACCEPT_NULL_PKT_PRE_TSIO [03:03] */
-#define BCHP_XPT_FE_MINI_PID_PARSER12_CTRL1_PARSER_ACCEPT_NULL_PKT_PRE_TSIO_MASK 0x00000008
-#define BCHP_XPT_FE_MINI_PID_PARSER12_CTRL1_PARSER_ACCEPT_NULL_PKT_PRE_TSIO_SHIFT 3
-#define BCHP_XPT_FE_MINI_PID_PARSER12_CTRL1_PARSER_ACCEPT_NULL_PKT_PRE_TSIO_DEFAULT 0x00000000
-
-/* XPT_FE :: MINI_PID_PARSER12_CTRL1 :: PARSER_ALL_PASS_CTRL_PRE_TSIO [02:02] */
-#define BCHP_XPT_FE_MINI_PID_PARSER12_CTRL1_PARSER_ALL_PASS_CTRL_PRE_TSIO_MASK 0x00000004
-#define BCHP_XPT_FE_MINI_PID_PARSER12_CTRL1_PARSER_ALL_PASS_CTRL_PRE_TSIO_SHIFT 2
-#define BCHP_XPT_FE_MINI_PID_PARSER12_CTRL1_PARSER_ALL_PASS_CTRL_PRE_TSIO_DEFAULT 0x00000000
-
-/* XPT_FE :: MINI_PID_PARSER12_CTRL1 :: PARSER_ALL_PASS_CTRL_PRE_MPOD [01:01] */
-#define BCHP_XPT_FE_MINI_PID_PARSER12_CTRL1_PARSER_ALL_PASS_CTRL_PRE_MPOD_MASK 0x00000002
-#define BCHP_XPT_FE_MINI_PID_PARSER12_CTRL1_PARSER_ALL_PASS_CTRL_PRE_MPOD_SHIFT 1
-#define BCHP_XPT_FE_MINI_PID_PARSER12_CTRL1_PARSER_ALL_PASS_CTRL_PRE_MPOD_DEFAULT 0x00000000
-
-/* XPT_FE :: MINI_PID_PARSER12_CTRL1 :: PARSER_ENABLE [00:00] */
-#define BCHP_XPT_FE_MINI_PID_PARSER12_CTRL1_PARSER_ENABLE_MASK 0x00000001
-#define BCHP_XPT_FE_MINI_PID_PARSER12_CTRL1_PARSER_ENABLE_SHIFT 0
-#define BCHP_XPT_FE_MINI_PID_PARSER12_CTRL1_PARSER_ENABLE_DEFAULT 0x00000000
-
-/***************************************************************************
- *MINI_PID_PARSER12_CTRL2 - Data Transport Parser Band 12 Control Register 2
- ***************************************************************************/
-/* XPT_FE :: MINI_PID_PARSER12_CTRL2 :: reserved0 [31:14] */
-#define BCHP_XPT_FE_MINI_PID_PARSER12_CTRL2_reserved0_MASK 0xffffc000
-#define BCHP_XPT_FE_MINI_PID_PARSER12_CTRL2_reserved0_SHIFT 14
-
-/* XPT_FE :: MINI_PID_PARSER12_CTRL2 :: PARSER_STREAM_TIMESTAMP_EN [13:13] */
-#define BCHP_XPT_FE_MINI_PID_PARSER12_CTRL2_PARSER_STREAM_TIMESTAMP_EN_MASK 0x00002000
-#define BCHP_XPT_FE_MINI_PID_PARSER12_CTRL2_PARSER_STREAM_TIMESTAMP_EN_SHIFT 13
-#define BCHP_XPT_FE_MINI_PID_PARSER12_CTRL2_PARSER_STREAM_TIMESTAMP_EN_DEFAULT 0x00000000
-
-/* XPT_FE :: MINI_PID_PARSER12_CTRL2 :: PARSER_TIMESTREAM_BF_SYNC [12:12] */
-#define BCHP_XPT_FE_MINI_PID_PARSER12_CTRL2_PARSER_TIMESTREAM_BF_SYNC_MASK 0x00001000
-#define BCHP_XPT_FE_MINI_PID_PARSER12_CTRL2_PARSER_TIMESTREAM_BF_SYNC_SHIFT 12
-#define BCHP_XPT_FE_MINI_PID_PARSER12_CTRL2_PARSER_TIMESTREAM_BF_SYNC_DEFAULT 0x00000000
-
-/* XPT_FE :: MINI_PID_PARSER12_CTRL2 :: reserved1 [11:11] */
-#define BCHP_XPT_FE_MINI_PID_PARSER12_CTRL2_reserved1_MASK 0x00000800
-#define BCHP_XPT_FE_MINI_PID_PARSER12_CTRL2_reserved1_SHIFT 11
-
-/* XPT_FE :: MINI_PID_PARSER12_CTRL2 :: PARSER_TIMESTAMP_RESTAMP [10:10] */
-#define BCHP_XPT_FE_MINI_PID_PARSER12_CTRL2_PARSER_TIMESTAMP_RESTAMP_MASK 0x00000400
-#define BCHP_XPT_FE_MINI_PID_PARSER12_CTRL2_PARSER_TIMESTAMP_RESTAMP_SHIFT 10
-#define BCHP_XPT_FE_MINI_PID_PARSER12_CTRL2_PARSER_TIMESTAMP_RESTAMP_DEFAULT 0x00000001
-
-/* XPT_FE :: MINI_PID_PARSER12_CTRL2 :: TSIO_MODE_SEL [09:09] */
-#define BCHP_XPT_FE_MINI_PID_PARSER12_CTRL2_TSIO_MODE_SEL_MASK 0x00000200
-#define BCHP_XPT_FE_MINI_PID_PARSER12_CTRL2_TSIO_MODE_SEL_SHIFT 9
-#define BCHP_XPT_FE_MINI_PID_PARSER12_CTRL2_TSIO_MODE_SEL_DEFAULT 0x00000001
-
-/* XPT_FE :: MINI_PID_PARSER12_CTRL2 :: reserved2 [08:07] */
-#define BCHP_XPT_FE_MINI_PID_PARSER12_CTRL2_reserved2_MASK 0x00000180
-#define BCHP_XPT_FE_MINI_PID_PARSER12_CTRL2_reserved2_SHIFT 7
-
-/* XPT_FE :: MINI_PID_PARSER12_CTRL2 :: TSIO_EN [06:06] */
-#define BCHP_XPT_FE_MINI_PID_PARSER12_CTRL2_TSIO_EN_MASK 0x00000040
-#define BCHP_XPT_FE_MINI_PID_PARSER12_CTRL2_TSIO_EN_SHIFT 6
-#define BCHP_XPT_FE_MINI_PID_PARSER12_CTRL2_TSIO_EN_DEFAULT 0x00000000
-
-/* XPT_FE :: MINI_PID_PARSER12_CTRL2 :: reserved3 [05:05] */
-#define BCHP_XPT_FE_MINI_PID_PARSER12_CTRL2_reserved3_MASK 0x00000020
-#define BCHP_XPT_FE_MINI_PID_PARSER12_CTRL2_reserved3_SHIFT 5
-
-/* XPT_FE :: MINI_PID_PARSER12_CTRL2 :: MPOD_MODE_SEL [04:04] */
-#define BCHP_XPT_FE_MINI_PID_PARSER12_CTRL2_MPOD_MODE_SEL_MASK 0x00000010
-#define BCHP_XPT_FE_MINI_PID_PARSER12_CTRL2_MPOD_MODE_SEL_SHIFT 4
-#define BCHP_XPT_FE_MINI_PID_PARSER12_CTRL2_MPOD_MODE_SEL_DEFAULT 0x00000000
-
-/* XPT_FE :: MINI_PID_PARSER12_CTRL2 :: reserved4 [03:03] */
-#define BCHP_XPT_FE_MINI_PID_PARSER12_CTRL2_reserved4_MASK 0x00000008
-#define BCHP_XPT_FE_MINI_PID_PARSER12_CTRL2_reserved4_SHIFT 3
-
-/* XPT_FE :: MINI_PID_PARSER12_CTRL2 :: PARSER_ACCEPT_NULL_PKT_POST_MPOD [02:02] */
-#define BCHP_XPT_FE_MINI_PID_PARSER12_CTRL2_PARSER_ACCEPT_NULL_PKT_POST_MPOD_MASK 0x00000004
-#define BCHP_XPT_FE_MINI_PID_PARSER12_CTRL2_PARSER_ACCEPT_NULL_PKT_POST_MPOD_SHIFT 2
-#define BCHP_XPT_FE_MINI_PID_PARSER12_CTRL2_PARSER_ACCEPT_NULL_PKT_POST_MPOD_DEFAULT 0x00000000
-
-/* XPT_FE :: MINI_PID_PARSER12_CTRL2 :: PARSER_ALL_PASS_CTRL_POST_MPOD [01:01] */
-#define BCHP_XPT_FE_MINI_PID_PARSER12_CTRL2_PARSER_ALL_PASS_CTRL_POST_MPOD_MASK 0x00000002
-#define BCHP_XPT_FE_MINI_PID_PARSER12_CTRL2_PARSER_ALL_PASS_CTRL_POST_MPOD_SHIFT 1
-#define BCHP_XPT_FE_MINI_PID_PARSER12_CTRL2_PARSER_ALL_PASS_CTRL_POST_MPOD_DEFAULT 0x00000000
-
-/* XPT_FE :: MINI_PID_PARSER12_CTRL2 :: MPOD_EN [00:00] */
-#define BCHP_XPT_FE_MINI_PID_PARSER12_CTRL2_MPOD_EN_MASK 0x00000001
-#define BCHP_XPT_FE_MINI_PID_PARSER12_CTRL2_MPOD_EN_SHIFT 0
-#define BCHP_XPT_FE_MINI_PID_PARSER12_CTRL2_MPOD_EN_DEFAULT 0x00000000
-
-/***************************************************************************
- *MINI_PID_PARSER12_ALL_PASS_CTRL - Data Transport Parser Band 12 Control Register
- ***************************************************************************/
-/* XPT_FE :: MINI_PID_PARSER12_ALL_PASS_CTRL :: reserved0 [31:13] */
-#define BCHP_XPT_FE_MINI_PID_PARSER12_ALL_PASS_CTRL_reserved0_MASK 0xffffe000
-#define BCHP_XPT_FE_MINI_PID_PARSER12_ALL_PASS_CTRL_reserved0_SHIFT 13
-
-/* XPT_FE :: MINI_PID_PARSER12_ALL_PASS_CTRL :: PIDP_DEBUG_MODE [12:12] */
-#define BCHP_XPT_FE_MINI_PID_PARSER12_ALL_PASS_CTRL_PIDP_DEBUG_MODE_MASK 0x00001000
-#define BCHP_XPT_FE_MINI_PID_PARSER12_ALL_PASS_CTRL_PIDP_DEBUG_MODE_SHIFT 12
-#define BCHP_XPT_FE_MINI_PID_PARSER12_ALL_PASS_CTRL_PIDP_DEBUG_MODE_DEFAULT 0x00000000
-
-/* XPT_FE :: MINI_PID_PARSER12_ALL_PASS_CTRL :: ALL_PASS_PID_CH_NUM [11:00] */
-#define BCHP_XPT_FE_MINI_PID_PARSER12_ALL_PASS_CTRL_ALL_PASS_PID_CH_NUM_MASK 0x00000fff
-#define BCHP_XPT_FE_MINI_PID_PARSER12_ALL_PASS_CTRL_ALL_PASS_PID_CH_NUM_SHIFT 0
-#define BCHP_XPT_FE_MINI_PID_PARSER12_ALL_PASS_CTRL_ALL_PASS_PID_CH_NUM_DEFAULT 0x0000000c
-
-/***************************************************************************
- *MINI_PID_PARSER13_CTRL1 - Data Transport Parser Band 13 Control Register
- ***************************************************************************/
-/* XPT_FE :: MINI_PID_PARSER13_CTRL1 :: reserved0 [31:29] */
-#define BCHP_XPT_FE_MINI_PID_PARSER13_CTRL1_reserved0_MASK 0xe0000000
-#define BCHP_XPT_FE_MINI_PID_PARSER13_CTRL1_reserved0_SHIFT 29
-
-/* XPT_FE :: MINI_PID_PARSER13_CTRL1 :: PARSER_TIMESTAMP_MODE [28:27] */
-#define BCHP_XPT_FE_MINI_PID_PARSER13_CTRL1_PARSER_TIMESTAMP_MODE_MASK 0x18000000
-#define BCHP_XPT_FE_MINI_PID_PARSER13_CTRL1_PARSER_TIMESTAMP_MODE_SHIFT 27
-#define BCHP_XPT_FE_MINI_PID_PARSER13_CTRL1_PARSER_TIMESTAMP_MODE_DEFAULT 0x00000002
-
-/* XPT_FE :: MINI_PID_PARSER13_CTRL1 :: PARSER_TSMF_SEL [26:23] */
-#define BCHP_XPT_FE_MINI_PID_PARSER13_CTRL1_PARSER_TSMF_SEL_MASK 0x07800000
-#define BCHP_XPT_FE_MINI_PID_PARSER13_CTRL1_PARSER_TSMF_SEL_SHIFT 23
-#define BCHP_XPT_FE_MINI_PID_PARSER13_CTRL1_PARSER_TSMF_SEL_DEFAULT 0x00000000
-
-/* XPT_FE :: MINI_PID_PARSER13_CTRL1 :: PARSER_TSMF_EN [22:22] */
-#define BCHP_XPT_FE_MINI_PID_PARSER13_CTRL1_PARSER_TSMF_EN_MASK 0x00400000
-#define BCHP_XPT_FE_MINI_PID_PARSER13_CTRL1_PARSER_TSMF_EN_SHIFT 22
-#define BCHP_XPT_FE_MINI_PID_PARSER13_CTRL1_PARSER_TSMF_EN_DEFAULT 0x00000000
-
-/* XPT_FE :: MINI_PID_PARSER13_CTRL1 :: PARSER_INPUT_SEL_MSB [21:21] */
-#define BCHP_XPT_FE_MINI_PID_PARSER13_CTRL1_PARSER_INPUT_SEL_MSB_MASK 0x00200000
-#define BCHP_XPT_FE_MINI_PID_PARSER13_CTRL1_PARSER_INPUT_SEL_MSB_SHIFT 21
-#define BCHP_XPT_FE_MINI_PID_PARSER13_CTRL1_PARSER_INPUT_SEL_MSB_DEFAULT 0x00000000
-
-/* XPT_FE :: MINI_PID_PARSER13_CTRL1 :: PARSER_ERROR_INPUT_TEI_IGNORE [20:20] */
-#define BCHP_XPT_FE_MINI_PID_PARSER13_CTRL1_PARSER_ERROR_INPUT_TEI_IGNORE_MASK 0x00100000
-#define BCHP_XPT_FE_MINI_PID_PARSER13_CTRL1_PARSER_ERROR_INPUT_TEI_IGNORE_SHIFT 20
-#define BCHP_XPT_FE_MINI_PID_PARSER13_CTRL1_PARSER_ERROR_INPUT_TEI_IGNORE_DEFAULT 0x00000000
-
-/* XPT_FE :: MINI_PID_PARSER13_CTRL1 :: PARSER_PKT_LENGTH [19:12] */
-#define BCHP_XPT_FE_MINI_PID_PARSER13_CTRL1_PARSER_PKT_LENGTH_MASK 0x000ff000
-#define BCHP_XPT_FE_MINI_PID_PARSER13_CTRL1_PARSER_PKT_LENGTH_SHIFT 12
-#define BCHP_XPT_FE_MINI_PID_PARSER13_CTRL1_PARSER_PKT_LENGTH_DEFAULT 0x000000bc
-
-/* XPT_FE :: MINI_PID_PARSER13_CTRL1 :: PARSER_INPUT_SEL [11:08] */
-#define BCHP_XPT_FE_MINI_PID_PARSER13_CTRL1_PARSER_INPUT_SEL_MASK 0x00000f00
-#define BCHP_XPT_FE_MINI_PID_PARSER13_CTRL1_PARSER_INPUT_SEL_SHIFT 8
-#define BCHP_XPT_FE_MINI_PID_PARSER13_CTRL1_PARSER_INPUT_SEL_DEFAULT 0x00000000
-
-/* XPT_FE :: MINI_PID_PARSER13_CTRL1 :: reserved1 [07:07] */
-#define BCHP_XPT_FE_MINI_PID_PARSER13_CTRL1_reserved1_MASK 0x00000080
-#define BCHP_XPT_FE_MINI_PID_PARSER13_CTRL1_reserved1_SHIFT 7
-
-/* XPT_FE :: MINI_PID_PARSER13_CTRL1 :: PARSER_PACKET_TYPE [06:05] */
-#define BCHP_XPT_FE_MINI_PID_PARSER13_CTRL1_PARSER_PACKET_TYPE_MASK 0x00000060
-#define BCHP_XPT_FE_MINI_PID_PARSER13_CTRL1_PARSER_PACKET_TYPE_SHIFT 5
-#define BCHP_XPT_FE_MINI_PID_PARSER13_CTRL1_PARSER_PACKET_TYPE_DEFAULT 0x00000000
-
-/* XPT_FE :: MINI_PID_PARSER13_CTRL1 :: PARSER_ACCEPT_NULL_PKT_PRE_MPOD [04:04] */
-#define BCHP_XPT_FE_MINI_PID_PARSER13_CTRL1_PARSER_ACCEPT_NULL_PKT_PRE_MPOD_MASK 0x00000010
-#define BCHP_XPT_FE_MINI_PID_PARSER13_CTRL1_PARSER_ACCEPT_NULL_PKT_PRE_MPOD_SHIFT 4
-#define BCHP_XPT_FE_MINI_PID_PARSER13_CTRL1_PARSER_ACCEPT_NULL_PKT_PRE_MPOD_DEFAULT 0x00000000
-
-/* XPT_FE :: MINI_PID_PARSER13_CTRL1 :: PARSER_ACCEPT_NULL_PKT_PRE_TSIO [03:03] */
-#define BCHP_XPT_FE_MINI_PID_PARSER13_CTRL1_PARSER_ACCEPT_NULL_PKT_PRE_TSIO_MASK 0x00000008
-#define BCHP_XPT_FE_MINI_PID_PARSER13_CTRL1_PARSER_ACCEPT_NULL_PKT_PRE_TSIO_SHIFT 3
-#define BCHP_XPT_FE_MINI_PID_PARSER13_CTRL1_PARSER_ACCEPT_NULL_PKT_PRE_TSIO_DEFAULT 0x00000000
-
-/* XPT_FE :: MINI_PID_PARSER13_CTRL1 :: PARSER_ALL_PASS_CTRL_PRE_TSIO [02:02] */
-#define BCHP_XPT_FE_MINI_PID_PARSER13_CTRL1_PARSER_ALL_PASS_CTRL_PRE_TSIO_MASK 0x00000004
-#define BCHP_XPT_FE_MINI_PID_PARSER13_CTRL1_PARSER_ALL_PASS_CTRL_PRE_TSIO_SHIFT 2
-#define BCHP_XPT_FE_MINI_PID_PARSER13_CTRL1_PARSER_ALL_PASS_CTRL_PRE_TSIO_DEFAULT 0x00000000
-
-/* XPT_FE :: MINI_PID_PARSER13_CTRL1 :: PARSER_ALL_PASS_CTRL_PRE_MPOD [01:01] */
-#define BCHP_XPT_FE_MINI_PID_PARSER13_CTRL1_PARSER_ALL_PASS_CTRL_PRE_MPOD_MASK 0x00000002
-#define BCHP_XPT_FE_MINI_PID_PARSER13_CTRL1_PARSER_ALL_PASS_CTRL_PRE_MPOD_SHIFT 1
-#define BCHP_XPT_FE_MINI_PID_PARSER13_CTRL1_PARSER_ALL_PASS_CTRL_PRE_MPOD_DEFAULT 0x00000000
-
-/* XPT_FE :: MINI_PID_PARSER13_CTRL1 :: PARSER_ENABLE [00:00] */
-#define BCHP_XPT_FE_MINI_PID_PARSER13_CTRL1_PARSER_ENABLE_MASK 0x00000001
-#define BCHP_XPT_FE_MINI_PID_PARSER13_CTRL1_PARSER_ENABLE_SHIFT 0
-#define BCHP_XPT_FE_MINI_PID_PARSER13_CTRL1_PARSER_ENABLE_DEFAULT 0x00000000
-
-/***************************************************************************
- *MINI_PID_PARSER13_CTRL2 - Data Transport Parser Band 13 Control Register 2
- ***************************************************************************/
-/* XPT_FE :: MINI_PID_PARSER13_CTRL2 :: reserved0 [31:14] */
-#define BCHP_XPT_FE_MINI_PID_PARSER13_CTRL2_reserved0_MASK 0xffffc000
-#define BCHP_XPT_FE_MINI_PID_PARSER13_CTRL2_reserved0_SHIFT 14
-
-/* XPT_FE :: MINI_PID_PARSER13_CTRL2 :: PARSER_STREAM_TIMESTAMP_EN [13:13] */
-#define BCHP_XPT_FE_MINI_PID_PARSER13_CTRL2_PARSER_STREAM_TIMESTAMP_EN_MASK 0x00002000
-#define BCHP_XPT_FE_MINI_PID_PARSER13_CTRL2_PARSER_STREAM_TIMESTAMP_EN_SHIFT 13
-#define BCHP_XPT_FE_MINI_PID_PARSER13_CTRL2_PARSER_STREAM_TIMESTAMP_EN_DEFAULT 0x00000000
-
-/* XPT_FE :: MINI_PID_PARSER13_CTRL2 :: PARSER_TIMESTREAM_BF_SYNC [12:12] */
-#define BCHP_XPT_FE_MINI_PID_PARSER13_CTRL2_PARSER_TIMESTREAM_BF_SYNC_MASK 0x00001000
-#define BCHP_XPT_FE_MINI_PID_PARSER13_CTRL2_PARSER_TIMESTREAM_BF_SYNC_SHIFT 12
-#define BCHP_XPT_FE_MINI_PID_PARSER13_CTRL2_PARSER_TIMESTREAM_BF_SYNC_DEFAULT 0x00000000
-
-/* XPT_FE :: MINI_PID_PARSER13_CTRL2 :: reserved1 [11:11] */
-#define BCHP_XPT_FE_MINI_PID_PARSER13_CTRL2_reserved1_MASK 0x00000800
-#define BCHP_XPT_FE_MINI_PID_PARSER13_CTRL2_reserved1_SHIFT 11
-
-/* XPT_FE :: MINI_PID_PARSER13_CTRL2 :: PARSER_TIMESTAMP_RESTAMP [10:10] */
-#define BCHP_XPT_FE_MINI_PID_PARSER13_CTRL2_PARSER_TIMESTAMP_RESTAMP_MASK 0x00000400
-#define BCHP_XPT_FE_MINI_PID_PARSER13_CTRL2_PARSER_TIMESTAMP_RESTAMP_SHIFT 10
-#define BCHP_XPT_FE_MINI_PID_PARSER13_CTRL2_PARSER_TIMESTAMP_RESTAMP_DEFAULT 0x00000001
-
-/* XPT_FE :: MINI_PID_PARSER13_CTRL2 :: TSIO_MODE_SEL [09:09] */
-#define BCHP_XPT_FE_MINI_PID_PARSER13_CTRL2_TSIO_MODE_SEL_MASK 0x00000200
-#define BCHP_XPT_FE_MINI_PID_PARSER13_CTRL2_TSIO_MODE_SEL_SHIFT 9
-#define BCHP_XPT_FE_MINI_PID_PARSER13_CTRL2_TSIO_MODE_SEL_DEFAULT 0x00000001
-
-/* XPT_FE :: MINI_PID_PARSER13_CTRL2 :: reserved2 [08:07] */
-#define BCHP_XPT_FE_MINI_PID_PARSER13_CTRL2_reserved2_MASK 0x00000180
-#define BCHP_XPT_FE_MINI_PID_PARSER13_CTRL2_reserved2_SHIFT 7
-
-/* XPT_FE :: MINI_PID_PARSER13_CTRL2 :: TSIO_EN [06:06] */
-#define BCHP_XPT_FE_MINI_PID_PARSER13_CTRL2_TSIO_EN_MASK 0x00000040
-#define BCHP_XPT_FE_MINI_PID_PARSER13_CTRL2_TSIO_EN_SHIFT 6
-#define BCHP_XPT_FE_MINI_PID_PARSER13_CTRL2_TSIO_EN_DEFAULT 0x00000000
-
-/* XPT_FE :: MINI_PID_PARSER13_CTRL2 :: reserved3 [05:05] */
-#define BCHP_XPT_FE_MINI_PID_PARSER13_CTRL2_reserved3_MASK 0x00000020
-#define BCHP_XPT_FE_MINI_PID_PARSER13_CTRL2_reserved3_SHIFT 5
-
-/* XPT_FE :: MINI_PID_PARSER13_CTRL2 :: MPOD_MODE_SEL [04:04] */
-#define BCHP_XPT_FE_MINI_PID_PARSER13_CTRL2_MPOD_MODE_SEL_MASK 0x00000010
-#define BCHP_XPT_FE_MINI_PID_PARSER13_CTRL2_MPOD_MODE_SEL_SHIFT 4
-#define BCHP_XPT_FE_MINI_PID_PARSER13_CTRL2_MPOD_MODE_SEL_DEFAULT 0x00000000
-
-/* XPT_FE :: MINI_PID_PARSER13_CTRL2 :: reserved4 [03:03] */
-#define BCHP_XPT_FE_MINI_PID_PARSER13_CTRL2_reserved4_MASK 0x00000008
-#define BCHP_XPT_FE_MINI_PID_PARSER13_CTRL2_reserved4_SHIFT 3
-
-/* XPT_FE :: MINI_PID_PARSER13_CTRL2 :: PARSER_ACCEPT_NULL_PKT_POST_MPOD [02:02] */
-#define BCHP_XPT_FE_MINI_PID_PARSER13_CTRL2_PARSER_ACCEPT_NULL_PKT_POST_MPOD_MASK 0x00000004
-#define BCHP_XPT_FE_MINI_PID_PARSER13_CTRL2_PARSER_ACCEPT_NULL_PKT_POST_MPOD_SHIFT 2
-#define BCHP_XPT_FE_MINI_PID_PARSER13_CTRL2_PARSER_ACCEPT_NULL_PKT_POST_MPOD_DEFAULT 0x00000000
-
-/* XPT_FE :: MINI_PID_PARSER13_CTRL2 :: PARSER_ALL_PASS_CTRL_POST_MPOD [01:01] */
-#define BCHP_XPT_FE_MINI_PID_PARSER13_CTRL2_PARSER_ALL_PASS_CTRL_POST_MPOD_MASK 0x00000002
-#define BCHP_XPT_FE_MINI_PID_PARSER13_CTRL2_PARSER_ALL_PASS_CTRL_POST_MPOD_SHIFT 1
-#define BCHP_XPT_FE_MINI_PID_PARSER13_CTRL2_PARSER_ALL_PASS_CTRL_POST_MPOD_DEFAULT 0x00000000
-
-/* XPT_FE :: MINI_PID_PARSER13_CTRL2 :: MPOD_EN [00:00] */
-#define BCHP_XPT_FE_MINI_PID_PARSER13_CTRL2_MPOD_EN_MASK 0x00000001
-#define BCHP_XPT_FE_MINI_PID_PARSER13_CTRL2_MPOD_EN_SHIFT 0
-#define BCHP_XPT_FE_MINI_PID_PARSER13_CTRL2_MPOD_EN_DEFAULT 0x00000000
-
-/***************************************************************************
- *MINI_PID_PARSER13_ALL_PASS_CTRL - Data Transport Parser Band 13 Control Register
- ***************************************************************************/
-/* XPT_FE :: MINI_PID_PARSER13_ALL_PASS_CTRL :: reserved0 [31:13] */
-#define BCHP_XPT_FE_MINI_PID_PARSER13_ALL_PASS_CTRL_reserved0_MASK 0xffffe000
-#define BCHP_XPT_FE_MINI_PID_PARSER13_ALL_PASS_CTRL_reserved0_SHIFT 13
-
-/* XPT_FE :: MINI_PID_PARSER13_ALL_PASS_CTRL :: PIDP_DEBUG_MODE [12:12] */
-#define BCHP_XPT_FE_MINI_PID_PARSER13_ALL_PASS_CTRL_PIDP_DEBUG_MODE_MASK 0x00001000
-#define BCHP_XPT_FE_MINI_PID_PARSER13_ALL_PASS_CTRL_PIDP_DEBUG_MODE_SHIFT 12
-#define BCHP_XPT_FE_MINI_PID_PARSER13_ALL_PASS_CTRL_PIDP_DEBUG_MODE_DEFAULT 0x00000000
-
-/* XPT_FE :: MINI_PID_PARSER13_ALL_PASS_CTRL :: ALL_PASS_PID_CH_NUM [11:00] */
-#define BCHP_XPT_FE_MINI_PID_PARSER13_ALL_PASS_CTRL_ALL_PASS_PID_CH_NUM_MASK 0x00000fff
-#define BCHP_XPT_FE_MINI_PID_PARSER13_ALL_PASS_CTRL_ALL_PASS_PID_CH_NUM_SHIFT 0
-#define BCHP_XPT_FE_MINI_PID_PARSER13_ALL_PASS_CTRL_ALL_PASS_PID_CH_NUM_DEFAULT 0x0000000d
-
-/***************************************************************************
- *MINI_PID_PARSER14_CTRL1 - Data Transport Parser Band 14 Control Register
- ***************************************************************************/
-/* XPT_FE :: MINI_PID_PARSER14_CTRL1 :: reserved0 [31:29] */
-#define BCHP_XPT_FE_MINI_PID_PARSER14_CTRL1_reserved0_MASK 0xe0000000
-#define BCHP_XPT_FE_MINI_PID_PARSER14_CTRL1_reserved0_SHIFT 29
-
-/* XPT_FE :: MINI_PID_PARSER14_CTRL1 :: PARSER_TIMESTAMP_MODE [28:27] */
-#define BCHP_XPT_FE_MINI_PID_PARSER14_CTRL1_PARSER_TIMESTAMP_MODE_MASK 0x18000000
-#define BCHP_XPT_FE_MINI_PID_PARSER14_CTRL1_PARSER_TIMESTAMP_MODE_SHIFT 27
-#define BCHP_XPT_FE_MINI_PID_PARSER14_CTRL1_PARSER_TIMESTAMP_MODE_DEFAULT 0x00000002
-
-/* XPT_FE :: MINI_PID_PARSER14_CTRL1 :: PARSER_TSMF_SEL [26:23] */
-#define BCHP_XPT_FE_MINI_PID_PARSER14_CTRL1_PARSER_TSMF_SEL_MASK 0x07800000
-#define BCHP_XPT_FE_MINI_PID_PARSER14_CTRL1_PARSER_TSMF_SEL_SHIFT 23
-#define BCHP_XPT_FE_MINI_PID_PARSER14_CTRL1_PARSER_TSMF_SEL_DEFAULT 0x00000000
-
-/* XPT_FE :: MINI_PID_PARSER14_CTRL1 :: PARSER_TSMF_EN [22:22] */
-#define BCHP_XPT_FE_MINI_PID_PARSER14_CTRL1_PARSER_TSMF_EN_MASK 0x00400000
-#define BCHP_XPT_FE_MINI_PID_PARSER14_CTRL1_PARSER_TSMF_EN_SHIFT 22
-#define BCHP_XPT_FE_MINI_PID_PARSER14_CTRL1_PARSER_TSMF_EN_DEFAULT 0x00000000
-
-/* XPT_FE :: MINI_PID_PARSER14_CTRL1 :: PARSER_INPUT_SEL_MSB [21:21] */
-#define BCHP_XPT_FE_MINI_PID_PARSER14_CTRL1_PARSER_INPUT_SEL_MSB_MASK 0x00200000
-#define BCHP_XPT_FE_MINI_PID_PARSER14_CTRL1_PARSER_INPUT_SEL_MSB_SHIFT 21
-#define BCHP_XPT_FE_MINI_PID_PARSER14_CTRL1_PARSER_INPUT_SEL_MSB_DEFAULT 0x00000000
-
-/* XPT_FE :: MINI_PID_PARSER14_CTRL1 :: PARSER_ERROR_INPUT_TEI_IGNORE [20:20] */
-#define BCHP_XPT_FE_MINI_PID_PARSER14_CTRL1_PARSER_ERROR_INPUT_TEI_IGNORE_MASK 0x00100000
-#define BCHP_XPT_FE_MINI_PID_PARSER14_CTRL1_PARSER_ERROR_INPUT_TEI_IGNORE_SHIFT 20
-#define BCHP_XPT_FE_MINI_PID_PARSER14_CTRL1_PARSER_ERROR_INPUT_TEI_IGNORE_DEFAULT 0x00000000
-
-/* XPT_FE :: MINI_PID_PARSER14_CTRL1 :: PARSER_PKT_LENGTH [19:12] */
-#define BCHP_XPT_FE_MINI_PID_PARSER14_CTRL1_PARSER_PKT_LENGTH_MASK 0x000ff000
-#define BCHP_XPT_FE_MINI_PID_PARSER14_CTRL1_PARSER_PKT_LENGTH_SHIFT 12
-#define BCHP_XPT_FE_MINI_PID_PARSER14_CTRL1_PARSER_PKT_LENGTH_DEFAULT 0x000000bc
-
-/* XPT_FE :: MINI_PID_PARSER14_CTRL1 :: PARSER_INPUT_SEL [11:08] */
-#define BCHP_XPT_FE_MINI_PID_PARSER14_CTRL1_PARSER_INPUT_SEL_MASK 0x00000f00
-#define BCHP_XPT_FE_MINI_PID_PARSER14_CTRL1_PARSER_INPUT_SEL_SHIFT 8
-#define BCHP_XPT_FE_MINI_PID_PARSER14_CTRL1_PARSER_INPUT_SEL_DEFAULT 0x00000000
-
-/* XPT_FE :: MINI_PID_PARSER14_CTRL1 :: reserved1 [07:07] */
-#define BCHP_XPT_FE_MINI_PID_PARSER14_CTRL1_reserved1_MASK 0x00000080
-#define BCHP_XPT_FE_MINI_PID_PARSER14_CTRL1_reserved1_SHIFT 7
-
-/* XPT_FE :: MINI_PID_PARSER14_CTRL1 :: PARSER_PACKET_TYPE [06:05] */
-#define BCHP_XPT_FE_MINI_PID_PARSER14_CTRL1_PARSER_PACKET_TYPE_MASK 0x00000060
-#define BCHP_XPT_FE_MINI_PID_PARSER14_CTRL1_PARSER_PACKET_TYPE_SHIFT 5
-#define BCHP_XPT_FE_MINI_PID_PARSER14_CTRL1_PARSER_PACKET_TYPE_DEFAULT 0x00000000
-
-/* XPT_FE :: MINI_PID_PARSER14_CTRL1 :: PARSER_ACCEPT_NULL_PKT_PRE_MPOD [04:04] */
-#define BCHP_XPT_FE_MINI_PID_PARSER14_CTRL1_PARSER_ACCEPT_NULL_PKT_PRE_MPOD_MASK 0x00000010
-#define BCHP_XPT_FE_MINI_PID_PARSER14_CTRL1_PARSER_ACCEPT_NULL_PKT_PRE_MPOD_SHIFT 4
-#define BCHP_XPT_FE_MINI_PID_PARSER14_CTRL1_PARSER_ACCEPT_NULL_PKT_PRE_MPOD_DEFAULT 0x00000000
-
-/* XPT_FE :: MINI_PID_PARSER14_CTRL1 :: PARSER_ACCEPT_NULL_PKT_PRE_TSIO [03:03] */
-#define BCHP_XPT_FE_MINI_PID_PARSER14_CTRL1_PARSER_ACCEPT_NULL_PKT_PRE_TSIO_MASK 0x00000008
-#define BCHP_XPT_FE_MINI_PID_PARSER14_CTRL1_PARSER_ACCEPT_NULL_PKT_PRE_TSIO_SHIFT 3
-#define BCHP_XPT_FE_MINI_PID_PARSER14_CTRL1_PARSER_ACCEPT_NULL_PKT_PRE_TSIO_DEFAULT 0x00000000
-
-/* XPT_FE :: MINI_PID_PARSER14_CTRL1 :: PARSER_ALL_PASS_CTRL_PRE_TSIO [02:02] */
-#define BCHP_XPT_FE_MINI_PID_PARSER14_CTRL1_PARSER_ALL_PASS_CTRL_PRE_TSIO_MASK 0x00000004
-#define BCHP_XPT_FE_MINI_PID_PARSER14_CTRL1_PARSER_ALL_PASS_CTRL_PRE_TSIO_SHIFT 2
-#define BCHP_XPT_FE_MINI_PID_PARSER14_CTRL1_PARSER_ALL_PASS_CTRL_PRE_TSIO_DEFAULT 0x00000000
-
-/* XPT_FE :: MINI_PID_PARSER14_CTRL1 :: PARSER_ALL_PASS_CTRL_PRE_MPOD [01:01] */
-#define BCHP_XPT_FE_MINI_PID_PARSER14_CTRL1_PARSER_ALL_PASS_CTRL_PRE_MPOD_MASK 0x00000002
-#define BCHP_XPT_FE_MINI_PID_PARSER14_CTRL1_PARSER_ALL_PASS_CTRL_PRE_MPOD_SHIFT 1
-#define BCHP_XPT_FE_MINI_PID_PARSER14_CTRL1_PARSER_ALL_PASS_CTRL_PRE_MPOD_DEFAULT 0x00000000
-
-/* XPT_FE :: MINI_PID_PARSER14_CTRL1 :: PARSER_ENABLE [00:00] */
-#define BCHP_XPT_FE_MINI_PID_PARSER14_CTRL1_PARSER_ENABLE_MASK 0x00000001
-#define BCHP_XPT_FE_MINI_PID_PARSER14_CTRL1_PARSER_ENABLE_SHIFT 0
-#define BCHP_XPT_FE_MINI_PID_PARSER14_CTRL1_PARSER_ENABLE_DEFAULT 0x00000000
-
-/***************************************************************************
- *MINI_PID_PARSER14_CTRL2 - Data Transport Parser Band 14 Control Register 2
- ***************************************************************************/
-/* XPT_FE :: MINI_PID_PARSER14_CTRL2 :: reserved0 [31:14] */
-#define BCHP_XPT_FE_MINI_PID_PARSER14_CTRL2_reserved0_MASK 0xffffc000
-#define BCHP_XPT_FE_MINI_PID_PARSER14_CTRL2_reserved0_SHIFT 14
-
-/* XPT_FE :: MINI_PID_PARSER14_CTRL2 :: PARSER_STREAM_TIMESTAMP_EN [13:13] */
-#define BCHP_XPT_FE_MINI_PID_PARSER14_CTRL2_PARSER_STREAM_TIMESTAMP_EN_MASK 0x00002000
-#define BCHP_XPT_FE_MINI_PID_PARSER14_CTRL2_PARSER_STREAM_TIMESTAMP_EN_SHIFT 13
-#define BCHP_XPT_FE_MINI_PID_PARSER14_CTRL2_PARSER_STREAM_TIMESTAMP_EN_DEFAULT 0x00000000
-
-/* XPT_FE :: MINI_PID_PARSER14_CTRL2 :: PARSER_TIMESTREAM_BF_SYNC [12:12] */
-#define BCHP_XPT_FE_MINI_PID_PARSER14_CTRL2_PARSER_TIMESTREAM_BF_SYNC_MASK 0x00001000
-#define BCHP_XPT_FE_MINI_PID_PARSER14_CTRL2_PARSER_TIMESTREAM_BF_SYNC_SHIFT 12
-#define BCHP_XPT_FE_MINI_PID_PARSER14_CTRL2_PARSER_TIMESTREAM_BF_SYNC_DEFAULT 0x00000000
-
-/* XPT_FE :: MINI_PID_PARSER14_CTRL2 :: reserved1 [11:11] */
-#define BCHP_XPT_FE_MINI_PID_PARSER14_CTRL2_reserved1_MASK 0x00000800
-#define BCHP_XPT_FE_MINI_PID_PARSER14_CTRL2_reserved1_SHIFT 11
-
-/* XPT_FE :: MINI_PID_PARSER14_CTRL2 :: PARSER_TIMESTAMP_RESTAMP [10:10] */
-#define BCHP_XPT_FE_MINI_PID_PARSER14_CTRL2_PARSER_TIMESTAMP_RESTAMP_MASK 0x00000400
-#define BCHP_XPT_FE_MINI_PID_PARSER14_CTRL2_PARSER_TIMESTAMP_RESTAMP_SHIFT 10
-#define BCHP_XPT_FE_MINI_PID_PARSER14_CTRL2_PARSER_TIMESTAMP_RESTAMP_DEFAULT 0x00000001
-
-/* XPT_FE :: MINI_PID_PARSER14_CTRL2 :: TSIO_MODE_SEL [09:09] */
-#define BCHP_XPT_FE_MINI_PID_PARSER14_CTRL2_TSIO_MODE_SEL_MASK 0x00000200
-#define BCHP_XPT_FE_MINI_PID_PARSER14_CTRL2_TSIO_MODE_SEL_SHIFT 9
-#define BCHP_XPT_FE_MINI_PID_PARSER14_CTRL2_TSIO_MODE_SEL_DEFAULT 0x00000001
-
-/* XPT_FE :: MINI_PID_PARSER14_CTRL2 :: reserved2 [08:07] */
-#define BCHP_XPT_FE_MINI_PID_PARSER14_CTRL2_reserved2_MASK 0x00000180
-#define BCHP_XPT_FE_MINI_PID_PARSER14_CTRL2_reserved2_SHIFT 7
-
-/* XPT_FE :: MINI_PID_PARSER14_CTRL2 :: TSIO_EN [06:06] */
-#define BCHP_XPT_FE_MINI_PID_PARSER14_CTRL2_TSIO_EN_MASK 0x00000040
-#define BCHP_XPT_FE_MINI_PID_PARSER14_CTRL2_TSIO_EN_SHIFT 6
-#define BCHP_XPT_FE_MINI_PID_PARSER14_CTRL2_TSIO_EN_DEFAULT 0x00000000
-
-/* XPT_FE :: MINI_PID_PARSER14_CTRL2 :: reserved3 [05:05] */
-#define BCHP_XPT_FE_MINI_PID_PARSER14_CTRL2_reserved3_MASK 0x00000020
-#define BCHP_XPT_FE_MINI_PID_PARSER14_CTRL2_reserved3_SHIFT 5
-
-/* XPT_FE :: MINI_PID_PARSER14_CTRL2 :: MPOD_MODE_SEL [04:04] */
-#define BCHP_XPT_FE_MINI_PID_PARSER14_CTRL2_MPOD_MODE_SEL_MASK 0x00000010
-#define BCHP_XPT_FE_MINI_PID_PARSER14_CTRL2_MPOD_MODE_SEL_SHIFT 4
-#define BCHP_XPT_FE_MINI_PID_PARSER14_CTRL2_MPOD_MODE_SEL_DEFAULT 0x00000000
-
-/* XPT_FE :: MINI_PID_PARSER14_CTRL2 :: reserved4 [03:03] */
-#define BCHP_XPT_FE_MINI_PID_PARSER14_CTRL2_reserved4_MASK 0x00000008
-#define BCHP_XPT_FE_MINI_PID_PARSER14_CTRL2_reserved4_SHIFT 3
-
-/* XPT_FE :: MINI_PID_PARSER14_CTRL2 :: PARSER_ACCEPT_NULL_PKT_POST_MPOD [02:02] */
-#define BCHP_XPT_FE_MINI_PID_PARSER14_CTRL2_PARSER_ACCEPT_NULL_PKT_POST_MPOD_MASK 0x00000004
-#define BCHP_XPT_FE_MINI_PID_PARSER14_CTRL2_PARSER_ACCEPT_NULL_PKT_POST_MPOD_SHIFT 2
-#define BCHP_XPT_FE_MINI_PID_PARSER14_CTRL2_PARSER_ACCEPT_NULL_PKT_POST_MPOD_DEFAULT 0x00000000
-
-/* XPT_FE :: MINI_PID_PARSER14_CTRL2 :: PARSER_ALL_PASS_CTRL_POST_MPOD [01:01] */
-#define BCHP_XPT_FE_MINI_PID_PARSER14_CTRL2_PARSER_ALL_PASS_CTRL_POST_MPOD_MASK 0x00000002
-#define BCHP_XPT_FE_MINI_PID_PARSER14_CTRL2_PARSER_ALL_PASS_CTRL_POST_MPOD_SHIFT 1
-#define BCHP_XPT_FE_MINI_PID_PARSER14_CTRL2_PARSER_ALL_PASS_CTRL_POST_MPOD_DEFAULT 0x00000000
-
-/* XPT_FE :: MINI_PID_PARSER14_CTRL2 :: MPOD_EN [00:00] */
-#define BCHP_XPT_FE_MINI_PID_PARSER14_CTRL2_MPOD_EN_MASK 0x00000001
-#define BCHP_XPT_FE_MINI_PID_PARSER14_CTRL2_MPOD_EN_SHIFT 0
-#define BCHP_XPT_FE_MINI_PID_PARSER14_CTRL2_MPOD_EN_DEFAULT 0x00000000
-
-/***************************************************************************
- *MINI_PID_PARSER14_ALL_PASS_CTRL - Data Transport Parser Band 14 Control Register
- ***************************************************************************/
-/* XPT_FE :: MINI_PID_PARSER14_ALL_PASS_CTRL :: reserved0 [31:13] */
-#define BCHP_XPT_FE_MINI_PID_PARSER14_ALL_PASS_CTRL_reserved0_MASK 0xffffe000
-#define BCHP_XPT_FE_MINI_PID_PARSER14_ALL_PASS_CTRL_reserved0_SHIFT 13
-
-/* XPT_FE :: MINI_PID_PARSER14_ALL_PASS_CTRL :: PIDP_DEBUG_MODE [12:12] */
-#define BCHP_XPT_FE_MINI_PID_PARSER14_ALL_PASS_CTRL_PIDP_DEBUG_MODE_MASK 0x00001000
-#define BCHP_XPT_FE_MINI_PID_PARSER14_ALL_PASS_CTRL_PIDP_DEBUG_MODE_SHIFT 12
-#define BCHP_XPT_FE_MINI_PID_PARSER14_ALL_PASS_CTRL_PIDP_DEBUG_MODE_DEFAULT 0x00000000
-
-/* XPT_FE :: MINI_PID_PARSER14_ALL_PASS_CTRL :: ALL_PASS_PID_CH_NUM [11:00] */
-#define BCHP_XPT_FE_MINI_PID_PARSER14_ALL_PASS_CTRL_ALL_PASS_PID_CH_NUM_MASK 0x00000fff
-#define BCHP_XPT_FE_MINI_PID_PARSER14_ALL_PASS_CTRL_ALL_PASS_PID_CH_NUM_SHIFT 0
-#define BCHP_XPT_FE_MINI_PID_PARSER14_ALL_PASS_CTRL_ALL_PASS_PID_CH_NUM_DEFAULT 0x0000000e
-
-/***************************************************************************
- *MINI_PID_PARSER15_CTRL1 - Data Transport Parser Band 15 Control Register
- ***************************************************************************/
-/* XPT_FE :: MINI_PID_PARSER15_CTRL1 :: reserved0 [31:29] */
-#define BCHP_XPT_FE_MINI_PID_PARSER15_CTRL1_reserved0_MASK 0xe0000000
-#define BCHP_XPT_FE_MINI_PID_PARSER15_CTRL1_reserved0_SHIFT 29
-
-/* XPT_FE :: MINI_PID_PARSER15_CTRL1 :: PARSER_TIMESTAMP_MODE [28:27] */
-#define BCHP_XPT_FE_MINI_PID_PARSER15_CTRL1_PARSER_TIMESTAMP_MODE_MASK 0x18000000
-#define BCHP_XPT_FE_MINI_PID_PARSER15_CTRL1_PARSER_TIMESTAMP_MODE_SHIFT 27
-#define BCHP_XPT_FE_MINI_PID_PARSER15_CTRL1_PARSER_TIMESTAMP_MODE_DEFAULT 0x00000002
-
-/* XPT_FE :: MINI_PID_PARSER15_CTRL1 :: PARSER_TSMF_SEL [26:23] */
-#define BCHP_XPT_FE_MINI_PID_PARSER15_CTRL1_PARSER_TSMF_SEL_MASK 0x07800000
-#define BCHP_XPT_FE_MINI_PID_PARSER15_CTRL1_PARSER_TSMF_SEL_SHIFT 23
-#define BCHP_XPT_FE_MINI_PID_PARSER15_CTRL1_PARSER_TSMF_SEL_DEFAULT 0x00000000
-
-/* XPT_FE :: MINI_PID_PARSER15_CTRL1 :: PARSER_TSMF_EN [22:22] */
-#define BCHP_XPT_FE_MINI_PID_PARSER15_CTRL1_PARSER_TSMF_EN_MASK 0x00400000
-#define BCHP_XPT_FE_MINI_PID_PARSER15_CTRL1_PARSER_TSMF_EN_SHIFT 22
-#define BCHP_XPT_FE_MINI_PID_PARSER15_CTRL1_PARSER_TSMF_EN_DEFAULT 0x00000000
-
-/* XPT_FE :: MINI_PID_PARSER15_CTRL1 :: PARSER_INPUT_SEL_MSB [21:21] */
-#define BCHP_XPT_FE_MINI_PID_PARSER15_CTRL1_PARSER_INPUT_SEL_MSB_MASK 0x00200000
-#define BCHP_XPT_FE_MINI_PID_PARSER15_CTRL1_PARSER_INPUT_SEL_MSB_SHIFT 21
-#define BCHP_XPT_FE_MINI_PID_PARSER15_CTRL1_PARSER_INPUT_SEL_MSB_DEFAULT 0x00000000
-
-/* XPT_FE :: MINI_PID_PARSER15_CTRL1 :: PARSER_ERROR_INPUT_TEI_IGNORE [20:20] */
-#define BCHP_XPT_FE_MINI_PID_PARSER15_CTRL1_PARSER_ERROR_INPUT_TEI_IGNORE_MASK 0x00100000
-#define BCHP_XPT_FE_MINI_PID_PARSER15_CTRL1_PARSER_ERROR_INPUT_TEI_IGNORE_SHIFT 20
-#define BCHP_XPT_FE_MINI_PID_PARSER15_CTRL1_PARSER_ERROR_INPUT_TEI_IGNORE_DEFAULT 0x00000000
-
-/* XPT_FE :: MINI_PID_PARSER15_CTRL1 :: PARSER_PKT_LENGTH [19:12] */
-#define BCHP_XPT_FE_MINI_PID_PARSER15_CTRL1_PARSER_PKT_LENGTH_MASK 0x000ff000
-#define BCHP_XPT_FE_MINI_PID_PARSER15_CTRL1_PARSER_PKT_LENGTH_SHIFT 12
-#define BCHP_XPT_FE_MINI_PID_PARSER15_CTRL1_PARSER_PKT_LENGTH_DEFAULT 0x000000bc
-
-/* XPT_FE :: MINI_PID_PARSER15_CTRL1 :: PARSER_INPUT_SEL [11:08] */
-#define BCHP_XPT_FE_MINI_PID_PARSER15_CTRL1_PARSER_INPUT_SEL_MASK 0x00000f00
-#define BCHP_XPT_FE_MINI_PID_PARSER15_CTRL1_PARSER_INPUT_SEL_SHIFT 8
-#define BCHP_XPT_FE_MINI_PID_PARSER15_CTRL1_PARSER_INPUT_SEL_DEFAULT 0x00000000
-
-/* XPT_FE :: MINI_PID_PARSER15_CTRL1 :: reserved1 [07:07] */
-#define BCHP_XPT_FE_MINI_PID_PARSER15_CTRL1_reserved1_MASK 0x00000080
-#define BCHP_XPT_FE_MINI_PID_PARSER15_CTRL1_reserved1_SHIFT 7
-
-/* XPT_FE :: MINI_PID_PARSER15_CTRL1 :: PARSER_PACKET_TYPE [06:05] */
-#define BCHP_XPT_FE_MINI_PID_PARSER15_CTRL1_PARSER_PACKET_TYPE_MASK 0x00000060
-#define BCHP_XPT_FE_MINI_PID_PARSER15_CTRL1_PARSER_PACKET_TYPE_SHIFT 5
-#define BCHP_XPT_FE_MINI_PID_PARSER15_CTRL1_PARSER_PACKET_TYPE_DEFAULT 0x00000000
-
-/* XPT_FE :: MINI_PID_PARSER15_CTRL1 :: PARSER_ACCEPT_NULL_PKT_PRE_MPOD [04:04] */
-#define BCHP_XPT_FE_MINI_PID_PARSER15_CTRL1_PARSER_ACCEPT_NULL_PKT_PRE_MPOD_MASK 0x00000010
-#define BCHP_XPT_FE_MINI_PID_PARSER15_CTRL1_PARSER_ACCEPT_NULL_PKT_PRE_MPOD_SHIFT 4
-#define BCHP_XPT_FE_MINI_PID_PARSER15_CTRL1_PARSER_ACCEPT_NULL_PKT_PRE_MPOD_DEFAULT 0x00000000
-
-/* XPT_FE :: MINI_PID_PARSER15_CTRL1 :: PARSER_ACCEPT_NULL_PKT_PRE_TSIO [03:03] */
-#define BCHP_XPT_FE_MINI_PID_PARSER15_CTRL1_PARSER_ACCEPT_NULL_PKT_PRE_TSIO_MASK 0x00000008
-#define BCHP_XPT_FE_MINI_PID_PARSER15_CTRL1_PARSER_ACCEPT_NULL_PKT_PRE_TSIO_SHIFT 3
-#define BCHP_XPT_FE_MINI_PID_PARSER15_CTRL1_PARSER_ACCEPT_NULL_PKT_PRE_TSIO_DEFAULT 0x00000000
-
-/* XPT_FE :: MINI_PID_PARSER15_CTRL1 :: PARSER_ALL_PASS_CTRL_PRE_TSIO [02:02] */
-#define BCHP_XPT_FE_MINI_PID_PARSER15_CTRL1_PARSER_ALL_PASS_CTRL_PRE_TSIO_MASK 0x00000004
-#define BCHP_XPT_FE_MINI_PID_PARSER15_CTRL1_PARSER_ALL_PASS_CTRL_PRE_TSIO_SHIFT 2
-#define BCHP_XPT_FE_MINI_PID_PARSER15_CTRL1_PARSER_ALL_PASS_CTRL_PRE_TSIO_DEFAULT 0x00000000
-
-/* XPT_FE :: MINI_PID_PARSER15_CTRL1 :: PARSER_ALL_PASS_CTRL_PRE_MPOD [01:01] */
-#define BCHP_XPT_FE_MINI_PID_PARSER15_CTRL1_PARSER_ALL_PASS_CTRL_PRE_MPOD_MASK 0x00000002
-#define BCHP_XPT_FE_MINI_PID_PARSER15_CTRL1_PARSER_ALL_PASS_CTRL_PRE_MPOD_SHIFT 1
-#define BCHP_XPT_FE_MINI_PID_PARSER15_CTRL1_PARSER_ALL_PASS_CTRL_PRE_MPOD_DEFAULT 0x00000000
-
-/* XPT_FE :: MINI_PID_PARSER15_CTRL1 :: PARSER_ENABLE [00:00] */
-#define BCHP_XPT_FE_MINI_PID_PARSER15_CTRL1_PARSER_ENABLE_MASK 0x00000001
-#define BCHP_XPT_FE_MINI_PID_PARSER15_CTRL1_PARSER_ENABLE_SHIFT 0
-#define BCHP_XPT_FE_MINI_PID_PARSER15_CTRL1_PARSER_ENABLE_DEFAULT 0x00000000
-
-/***************************************************************************
- *MINI_PID_PARSER15_CTRL2 - Data Transport Parser Band 15 Control Register 2
- ***************************************************************************/
-/* XPT_FE :: MINI_PID_PARSER15_CTRL2 :: reserved0 [31:14] */
-#define BCHP_XPT_FE_MINI_PID_PARSER15_CTRL2_reserved0_MASK 0xffffc000
-#define BCHP_XPT_FE_MINI_PID_PARSER15_CTRL2_reserved0_SHIFT 14
-
-/* XPT_FE :: MINI_PID_PARSER15_CTRL2 :: PARSER_STREAM_TIMESTAMP_EN [13:13] */
-#define BCHP_XPT_FE_MINI_PID_PARSER15_CTRL2_PARSER_STREAM_TIMESTAMP_EN_MASK 0x00002000
-#define BCHP_XPT_FE_MINI_PID_PARSER15_CTRL2_PARSER_STREAM_TIMESTAMP_EN_SHIFT 13
-#define BCHP_XPT_FE_MINI_PID_PARSER15_CTRL2_PARSER_STREAM_TIMESTAMP_EN_DEFAULT 0x00000000
-
-/* XPT_FE :: MINI_PID_PARSER15_CTRL2 :: PARSER_TIMESTREAM_BF_SYNC [12:12] */
-#define BCHP_XPT_FE_MINI_PID_PARSER15_CTRL2_PARSER_TIMESTREAM_BF_SYNC_MASK 0x00001000
-#define BCHP_XPT_FE_MINI_PID_PARSER15_CTRL2_PARSER_TIMESTREAM_BF_SYNC_SHIFT 12
-#define BCHP_XPT_FE_MINI_PID_PARSER15_CTRL2_PARSER_TIMESTREAM_BF_SYNC_DEFAULT 0x00000000
-
-/* XPT_FE :: MINI_PID_PARSER15_CTRL2 :: reserved1 [11:11] */
-#define BCHP_XPT_FE_MINI_PID_PARSER15_CTRL2_reserved1_MASK 0x00000800
-#define BCHP_XPT_FE_MINI_PID_PARSER15_CTRL2_reserved1_SHIFT 11
-
-/* XPT_FE :: MINI_PID_PARSER15_CTRL2 :: PARSER_TIMESTAMP_RESTAMP [10:10] */
-#define BCHP_XPT_FE_MINI_PID_PARSER15_CTRL2_PARSER_TIMESTAMP_RESTAMP_MASK 0x00000400
-#define BCHP_XPT_FE_MINI_PID_PARSER15_CTRL2_PARSER_TIMESTAMP_RESTAMP_SHIFT 10
-#define BCHP_XPT_FE_MINI_PID_PARSER15_CTRL2_PARSER_TIMESTAMP_RESTAMP_DEFAULT 0x00000001
-
-/* XPT_FE :: MINI_PID_PARSER15_CTRL2 :: TSIO_MODE_SEL [09:09] */
-#define BCHP_XPT_FE_MINI_PID_PARSER15_CTRL2_TSIO_MODE_SEL_MASK 0x00000200
-#define BCHP_XPT_FE_MINI_PID_PARSER15_CTRL2_TSIO_MODE_SEL_SHIFT 9
-#define BCHP_XPT_FE_MINI_PID_PARSER15_CTRL2_TSIO_MODE_SEL_DEFAULT 0x00000001
-
-/* XPT_FE :: MINI_PID_PARSER15_CTRL2 :: reserved2 [08:07] */
-#define BCHP_XPT_FE_MINI_PID_PARSER15_CTRL2_reserved2_MASK 0x00000180
-#define BCHP_XPT_FE_MINI_PID_PARSER15_CTRL2_reserved2_SHIFT 7
-
-/* XPT_FE :: MINI_PID_PARSER15_CTRL2 :: TSIO_EN [06:06] */
-#define BCHP_XPT_FE_MINI_PID_PARSER15_CTRL2_TSIO_EN_MASK 0x00000040
-#define BCHP_XPT_FE_MINI_PID_PARSER15_CTRL2_TSIO_EN_SHIFT 6
-#define BCHP_XPT_FE_MINI_PID_PARSER15_CTRL2_TSIO_EN_DEFAULT 0x00000000
-
-/* XPT_FE :: MINI_PID_PARSER15_CTRL2 :: reserved3 [05:05] */
-#define BCHP_XPT_FE_MINI_PID_PARSER15_CTRL2_reserved3_MASK 0x00000020
-#define BCHP_XPT_FE_MINI_PID_PARSER15_CTRL2_reserved3_SHIFT 5
-
-/* XPT_FE :: MINI_PID_PARSER15_CTRL2 :: MPOD_MODE_SEL [04:04] */
-#define BCHP_XPT_FE_MINI_PID_PARSER15_CTRL2_MPOD_MODE_SEL_MASK 0x00000010
-#define BCHP_XPT_FE_MINI_PID_PARSER15_CTRL2_MPOD_MODE_SEL_SHIFT 4
-#define BCHP_XPT_FE_MINI_PID_PARSER15_CTRL2_MPOD_MODE_SEL_DEFAULT 0x00000000
-
-/* XPT_FE :: MINI_PID_PARSER15_CTRL2 :: reserved4 [03:03] */
-#define BCHP_XPT_FE_MINI_PID_PARSER15_CTRL2_reserved4_MASK 0x00000008
-#define BCHP_XPT_FE_MINI_PID_PARSER15_CTRL2_reserved4_SHIFT 3
-
-/* XPT_FE :: MINI_PID_PARSER15_CTRL2 :: PARSER_ACCEPT_NULL_PKT_POST_MPOD [02:02] */
-#define BCHP_XPT_FE_MINI_PID_PARSER15_CTRL2_PARSER_ACCEPT_NULL_PKT_POST_MPOD_MASK 0x00000004
-#define BCHP_XPT_FE_MINI_PID_PARSER15_CTRL2_PARSER_ACCEPT_NULL_PKT_POST_MPOD_SHIFT 2
-#define BCHP_XPT_FE_MINI_PID_PARSER15_CTRL2_PARSER_ACCEPT_NULL_PKT_POST_MPOD_DEFAULT 0x00000000
-
-/* XPT_FE :: MINI_PID_PARSER15_CTRL2 :: PARSER_ALL_PASS_CTRL_POST_MPOD [01:01] */
-#define BCHP_XPT_FE_MINI_PID_PARSER15_CTRL2_PARSER_ALL_PASS_CTRL_POST_MPOD_MASK 0x00000002
-#define BCHP_XPT_FE_MINI_PID_PARSER15_CTRL2_PARSER_ALL_PASS_CTRL_POST_MPOD_SHIFT 1
-#define BCHP_XPT_FE_MINI_PID_PARSER15_CTRL2_PARSER_ALL_PASS_CTRL_POST_MPOD_DEFAULT 0x00000000
-
-/* XPT_FE :: MINI_PID_PARSER15_CTRL2 :: MPOD_EN [00:00] */
-#define BCHP_XPT_FE_MINI_PID_PARSER15_CTRL2_MPOD_EN_MASK 0x00000001
-#define BCHP_XPT_FE_MINI_PID_PARSER15_CTRL2_MPOD_EN_SHIFT 0
-#define BCHP_XPT_FE_MINI_PID_PARSER15_CTRL2_MPOD_EN_DEFAULT 0x00000000
-
-/***************************************************************************
- *MINI_PID_PARSER15_ALL_PASS_CTRL - Data Transport Parser Band 15 Control Register
- ***************************************************************************/
-/* XPT_FE :: MINI_PID_PARSER15_ALL_PASS_CTRL :: reserved0 [31:13] */
-#define BCHP_XPT_FE_MINI_PID_PARSER15_ALL_PASS_CTRL_reserved0_MASK 0xffffe000
-#define BCHP_XPT_FE_MINI_PID_PARSER15_ALL_PASS_CTRL_reserved0_SHIFT 13
-
-/* XPT_FE :: MINI_PID_PARSER15_ALL_PASS_CTRL :: PIDP_DEBUG_MODE [12:12] */
-#define BCHP_XPT_FE_MINI_PID_PARSER15_ALL_PASS_CTRL_PIDP_DEBUG_MODE_MASK 0x00001000
-#define BCHP_XPT_FE_MINI_PID_PARSER15_ALL_PASS_CTRL_PIDP_DEBUG_MODE_SHIFT 12
-#define BCHP_XPT_FE_MINI_PID_PARSER15_ALL_PASS_CTRL_PIDP_DEBUG_MODE_DEFAULT 0x00000000
-
-/* XPT_FE :: MINI_PID_PARSER15_ALL_PASS_CTRL :: ALL_PASS_PID_CH_NUM [11:00] */
-#define BCHP_XPT_FE_MINI_PID_PARSER15_ALL_PASS_CTRL_ALL_PASS_PID_CH_NUM_MASK 0x00000fff
-#define BCHP_XPT_FE_MINI_PID_PARSER15_ALL_PASS_CTRL_ALL_PASS_PID_CH_NUM_SHIFT 0
-#define BCHP_XPT_FE_MINI_PID_PARSER15_ALL_PASS_CTRL_ALL_PASS_PID_CH_NUM_DEFAULT 0x0000000f
-
-/***************************************************************************
- *MINI_PID_PARSER16_CTRL1 - Data Transport Parser Band 16 Control Register
- ***************************************************************************/
-/* XPT_FE :: MINI_PID_PARSER16_CTRL1 :: reserved0 [31:29] */
-#define BCHP_XPT_FE_MINI_PID_PARSER16_CTRL1_reserved0_MASK 0xe0000000
-#define BCHP_XPT_FE_MINI_PID_PARSER16_CTRL1_reserved0_SHIFT 29
-
-/* XPT_FE :: MINI_PID_PARSER16_CTRL1 :: PARSER_TIMESTAMP_MODE [28:27] */
-#define BCHP_XPT_FE_MINI_PID_PARSER16_CTRL1_PARSER_TIMESTAMP_MODE_MASK 0x18000000
-#define BCHP_XPT_FE_MINI_PID_PARSER16_CTRL1_PARSER_TIMESTAMP_MODE_SHIFT 27
-#define BCHP_XPT_FE_MINI_PID_PARSER16_CTRL1_PARSER_TIMESTAMP_MODE_DEFAULT 0x00000002
-
-/* XPT_FE :: MINI_PID_PARSER16_CTRL1 :: PARSER_TSMF_SEL [26:23] */
-#define BCHP_XPT_FE_MINI_PID_PARSER16_CTRL1_PARSER_TSMF_SEL_MASK 0x07800000
-#define BCHP_XPT_FE_MINI_PID_PARSER16_CTRL1_PARSER_TSMF_SEL_SHIFT 23
-#define BCHP_XPT_FE_MINI_PID_PARSER16_CTRL1_PARSER_TSMF_SEL_DEFAULT 0x00000000
-
-/* XPT_FE :: MINI_PID_PARSER16_CTRL1 :: PARSER_TSMF_EN [22:22] */
-#define BCHP_XPT_FE_MINI_PID_PARSER16_CTRL1_PARSER_TSMF_EN_MASK 0x00400000
-#define BCHP_XPT_FE_MINI_PID_PARSER16_CTRL1_PARSER_TSMF_EN_SHIFT 22
-#define BCHP_XPT_FE_MINI_PID_PARSER16_CTRL1_PARSER_TSMF_EN_DEFAULT 0x00000000
-
-/* XPT_FE :: MINI_PID_PARSER16_CTRL1 :: PARSER_INPUT_SEL_MSB [21:21] */
-#define BCHP_XPT_FE_MINI_PID_PARSER16_CTRL1_PARSER_INPUT_SEL_MSB_MASK 0x00200000
-#define BCHP_XPT_FE_MINI_PID_PARSER16_CTRL1_PARSER_INPUT_SEL_MSB_SHIFT 21
-#define BCHP_XPT_FE_MINI_PID_PARSER16_CTRL1_PARSER_INPUT_SEL_MSB_DEFAULT 0x00000000
-
-/* XPT_FE :: MINI_PID_PARSER16_CTRL1 :: PARSER_ERROR_INPUT_TEI_IGNORE [20:20] */
-#define BCHP_XPT_FE_MINI_PID_PARSER16_CTRL1_PARSER_ERROR_INPUT_TEI_IGNORE_MASK 0x00100000
-#define BCHP_XPT_FE_MINI_PID_PARSER16_CTRL1_PARSER_ERROR_INPUT_TEI_IGNORE_SHIFT 20
-#define BCHP_XPT_FE_MINI_PID_PARSER16_CTRL1_PARSER_ERROR_INPUT_TEI_IGNORE_DEFAULT 0x00000000
-
-/* XPT_FE :: MINI_PID_PARSER16_CTRL1 :: PARSER_PKT_LENGTH [19:12] */
-#define BCHP_XPT_FE_MINI_PID_PARSER16_CTRL1_PARSER_PKT_LENGTH_MASK 0x000ff000
-#define BCHP_XPT_FE_MINI_PID_PARSER16_CTRL1_PARSER_PKT_LENGTH_SHIFT 12
-#define BCHP_XPT_FE_MINI_PID_PARSER16_CTRL1_PARSER_PKT_LENGTH_DEFAULT 0x000000bc
-
-/* XPT_FE :: MINI_PID_PARSER16_CTRL1 :: PARSER_INPUT_SEL [11:08] */
-#define BCHP_XPT_FE_MINI_PID_PARSER16_CTRL1_PARSER_INPUT_SEL_MASK 0x00000f00
-#define BCHP_XPT_FE_MINI_PID_PARSER16_CTRL1_PARSER_INPUT_SEL_SHIFT 8
-#define BCHP_XPT_FE_MINI_PID_PARSER16_CTRL1_PARSER_INPUT_SEL_DEFAULT 0x00000000
-
-/* XPT_FE :: MINI_PID_PARSER16_CTRL1 :: reserved1 [07:07] */
-#define BCHP_XPT_FE_MINI_PID_PARSER16_CTRL1_reserved1_MASK 0x00000080
-#define BCHP_XPT_FE_MINI_PID_PARSER16_CTRL1_reserved1_SHIFT 7
-
-/* XPT_FE :: MINI_PID_PARSER16_CTRL1 :: PARSER_PACKET_TYPE [06:05] */
-#define BCHP_XPT_FE_MINI_PID_PARSER16_CTRL1_PARSER_PACKET_TYPE_MASK 0x00000060
-#define BCHP_XPT_FE_MINI_PID_PARSER16_CTRL1_PARSER_PACKET_TYPE_SHIFT 5
-#define BCHP_XPT_FE_MINI_PID_PARSER16_CTRL1_PARSER_PACKET_TYPE_DEFAULT 0x00000000
-
-/* XPT_FE :: MINI_PID_PARSER16_CTRL1 :: PARSER_ACCEPT_NULL_PKT_PRE_MPOD [04:04] */
-#define BCHP_XPT_FE_MINI_PID_PARSER16_CTRL1_PARSER_ACCEPT_NULL_PKT_PRE_MPOD_MASK 0x00000010
-#define BCHP_XPT_FE_MINI_PID_PARSER16_CTRL1_PARSER_ACCEPT_NULL_PKT_PRE_MPOD_SHIFT 4
-#define BCHP_XPT_FE_MINI_PID_PARSER16_CTRL1_PARSER_ACCEPT_NULL_PKT_PRE_MPOD_DEFAULT 0x00000000
-
-/* XPT_FE :: MINI_PID_PARSER16_CTRL1 :: PARSER_ACCEPT_NULL_PKT_PRE_TSIO [03:03] */
-#define BCHP_XPT_FE_MINI_PID_PARSER16_CTRL1_PARSER_ACCEPT_NULL_PKT_PRE_TSIO_MASK 0x00000008
-#define BCHP_XPT_FE_MINI_PID_PARSER16_CTRL1_PARSER_ACCEPT_NULL_PKT_PRE_TSIO_SHIFT 3
-#define BCHP_XPT_FE_MINI_PID_PARSER16_CTRL1_PARSER_ACCEPT_NULL_PKT_PRE_TSIO_DEFAULT 0x00000000
-
-/* XPT_FE :: MINI_PID_PARSER16_CTRL1 :: PARSER_ALL_PASS_CTRL_PRE_TSIO [02:02] */
-#define BCHP_XPT_FE_MINI_PID_PARSER16_CTRL1_PARSER_ALL_PASS_CTRL_PRE_TSIO_MASK 0x00000004
-#define BCHP_XPT_FE_MINI_PID_PARSER16_CTRL1_PARSER_ALL_PASS_CTRL_PRE_TSIO_SHIFT 2
-#define BCHP_XPT_FE_MINI_PID_PARSER16_CTRL1_PARSER_ALL_PASS_CTRL_PRE_TSIO_DEFAULT 0x00000000
-
-/* XPT_FE :: MINI_PID_PARSER16_CTRL1 :: PARSER_ALL_PASS_CTRL_PRE_MPOD [01:01] */
-#define BCHP_XPT_FE_MINI_PID_PARSER16_CTRL1_PARSER_ALL_PASS_CTRL_PRE_MPOD_MASK 0x00000002
-#define BCHP_XPT_FE_MINI_PID_PARSER16_CTRL1_PARSER_ALL_PASS_CTRL_PRE_MPOD_SHIFT 1
-#define BCHP_XPT_FE_MINI_PID_PARSER16_CTRL1_PARSER_ALL_PASS_CTRL_PRE_MPOD_DEFAULT 0x00000000
-
-/* XPT_FE :: MINI_PID_PARSER16_CTRL1 :: PARSER_ENABLE [00:00] */
-#define BCHP_XPT_FE_MINI_PID_PARSER16_CTRL1_PARSER_ENABLE_MASK 0x00000001
-#define BCHP_XPT_FE_MINI_PID_PARSER16_CTRL1_PARSER_ENABLE_SHIFT 0
-#define BCHP_XPT_FE_MINI_PID_PARSER16_CTRL1_PARSER_ENABLE_DEFAULT 0x00000000
-
-/***************************************************************************
- *MINI_PID_PARSER16_CTRL2 - Data Transport Parser Band 16 Control Register 2
- ***************************************************************************/
-/* XPT_FE :: MINI_PID_PARSER16_CTRL2 :: reserved0 [31:14] */
-#define BCHP_XPT_FE_MINI_PID_PARSER16_CTRL2_reserved0_MASK 0xffffc000
-#define BCHP_XPT_FE_MINI_PID_PARSER16_CTRL2_reserved0_SHIFT 14
-
-/* XPT_FE :: MINI_PID_PARSER16_CTRL2 :: PARSER_STREAM_TIMESTAMP_EN [13:13] */
-#define BCHP_XPT_FE_MINI_PID_PARSER16_CTRL2_PARSER_STREAM_TIMESTAMP_EN_MASK 0x00002000
-#define BCHP_XPT_FE_MINI_PID_PARSER16_CTRL2_PARSER_STREAM_TIMESTAMP_EN_SHIFT 13
-#define BCHP_XPT_FE_MINI_PID_PARSER16_CTRL2_PARSER_STREAM_TIMESTAMP_EN_DEFAULT 0x00000000
-
-/* XPT_FE :: MINI_PID_PARSER16_CTRL2 :: PARSER_TIMESTREAM_BF_SYNC [12:12] */
-#define BCHP_XPT_FE_MINI_PID_PARSER16_CTRL2_PARSER_TIMESTREAM_BF_SYNC_MASK 0x00001000
-#define BCHP_XPT_FE_MINI_PID_PARSER16_CTRL2_PARSER_TIMESTREAM_BF_SYNC_SHIFT 12
-#define BCHP_XPT_FE_MINI_PID_PARSER16_CTRL2_PARSER_TIMESTREAM_BF_SYNC_DEFAULT 0x00000000
-
-/* XPT_FE :: MINI_PID_PARSER16_CTRL2 :: reserved1 [11:11] */
-#define BCHP_XPT_FE_MINI_PID_PARSER16_CTRL2_reserved1_MASK 0x00000800
-#define BCHP_XPT_FE_MINI_PID_PARSER16_CTRL2_reserved1_SHIFT 11
-
-/* XPT_FE :: MINI_PID_PARSER16_CTRL2 :: PARSER_TIMESTAMP_RESTAMP [10:10] */
-#define BCHP_XPT_FE_MINI_PID_PARSER16_CTRL2_PARSER_TIMESTAMP_RESTAMP_MASK 0x00000400
-#define BCHP_XPT_FE_MINI_PID_PARSER16_CTRL2_PARSER_TIMESTAMP_RESTAMP_SHIFT 10
-#define BCHP_XPT_FE_MINI_PID_PARSER16_CTRL2_PARSER_TIMESTAMP_RESTAMP_DEFAULT 0x00000001
-
-/* XPT_FE :: MINI_PID_PARSER16_CTRL2 :: TSIO_MODE_SEL [09:09] */
-#define BCHP_XPT_FE_MINI_PID_PARSER16_CTRL2_TSIO_MODE_SEL_MASK 0x00000200
-#define BCHP_XPT_FE_MINI_PID_PARSER16_CTRL2_TSIO_MODE_SEL_SHIFT 9
-#define BCHP_XPT_FE_MINI_PID_PARSER16_CTRL2_TSIO_MODE_SEL_DEFAULT 0x00000001
-
-/* XPT_FE :: MINI_PID_PARSER16_CTRL2 :: reserved2 [08:07] */
-#define BCHP_XPT_FE_MINI_PID_PARSER16_CTRL2_reserved2_MASK 0x00000180
-#define BCHP_XPT_FE_MINI_PID_PARSER16_CTRL2_reserved2_SHIFT 7
-
-/* XPT_FE :: MINI_PID_PARSER16_CTRL2 :: TSIO_EN [06:06] */
-#define BCHP_XPT_FE_MINI_PID_PARSER16_CTRL2_TSIO_EN_MASK 0x00000040
-#define BCHP_XPT_FE_MINI_PID_PARSER16_CTRL2_TSIO_EN_SHIFT 6
-#define BCHP_XPT_FE_MINI_PID_PARSER16_CTRL2_TSIO_EN_DEFAULT 0x00000000
-
-/* XPT_FE :: MINI_PID_PARSER16_CTRL2 :: reserved3 [05:05] */
-#define BCHP_XPT_FE_MINI_PID_PARSER16_CTRL2_reserved3_MASK 0x00000020
-#define BCHP_XPT_FE_MINI_PID_PARSER16_CTRL2_reserved3_SHIFT 5
-
-/* XPT_FE :: MINI_PID_PARSER16_CTRL2 :: MPOD_MODE_SEL [04:04] */
-#define BCHP_XPT_FE_MINI_PID_PARSER16_CTRL2_MPOD_MODE_SEL_MASK 0x00000010
-#define BCHP_XPT_FE_MINI_PID_PARSER16_CTRL2_MPOD_MODE_SEL_SHIFT 4
-#define BCHP_XPT_FE_MINI_PID_PARSER16_CTRL2_MPOD_MODE_SEL_DEFAULT 0x00000000
-
-/* XPT_FE :: MINI_PID_PARSER16_CTRL2 :: reserved4 [03:03] */
-#define BCHP_XPT_FE_MINI_PID_PARSER16_CTRL2_reserved4_MASK 0x00000008
-#define BCHP_XPT_FE_MINI_PID_PARSER16_CTRL2_reserved4_SHIFT 3
-
-/* XPT_FE :: MINI_PID_PARSER16_CTRL2 :: PARSER_ACCEPT_NULL_PKT_POST_MPOD [02:02] */
-#define BCHP_XPT_FE_MINI_PID_PARSER16_CTRL2_PARSER_ACCEPT_NULL_PKT_POST_MPOD_MASK 0x00000004
-#define BCHP_XPT_FE_MINI_PID_PARSER16_CTRL2_PARSER_ACCEPT_NULL_PKT_POST_MPOD_SHIFT 2
-#define BCHP_XPT_FE_MINI_PID_PARSER16_CTRL2_PARSER_ACCEPT_NULL_PKT_POST_MPOD_DEFAULT 0x00000000
-
-/* XPT_FE :: MINI_PID_PARSER16_CTRL2 :: PARSER_ALL_PASS_CTRL_POST_MPOD [01:01] */
-#define BCHP_XPT_FE_MINI_PID_PARSER16_CTRL2_PARSER_ALL_PASS_CTRL_POST_MPOD_MASK 0x00000002
-#define BCHP_XPT_FE_MINI_PID_PARSER16_CTRL2_PARSER_ALL_PASS_CTRL_POST_MPOD_SHIFT 1
-#define BCHP_XPT_FE_MINI_PID_PARSER16_CTRL2_PARSER_ALL_PASS_CTRL_POST_MPOD_DEFAULT 0x00000000
-
-/* XPT_FE :: MINI_PID_PARSER16_CTRL2 :: MPOD_EN [00:00] */
-#define BCHP_XPT_FE_MINI_PID_PARSER16_CTRL2_MPOD_EN_MASK 0x00000001
-#define BCHP_XPT_FE_MINI_PID_PARSER16_CTRL2_MPOD_EN_SHIFT 0
-#define BCHP_XPT_FE_MINI_PID_PARSER16_CTRL2_MPOD_EN_DEFAULT 0x00000000
-
-/***************************************************************************
- *MINI_PID_PARSER16_ALL_PASS_CTRL - Data Transport Parser Band 16 Control Register
- ***************************************************************************/
-/* XPT_FE :: MINI_PID_PARSER16_ALL_PASS_CTRL :: reserved0 [31:13] */
-#define BCHP_XPT_FE_MINI_PID_PARSER16_ALL_PASS_CTRL_reserved0_MASK 0xffffe000
-#define BCHP_XPT_FE_MINI_PID_PARSER16_ALL_PASS_CTRL_reserved0_SHIFT 13
-
-/* XPT_FE :: MINI_PID_PARSER16_ALL_PASS_CTRL :: PIDP_DEBUG_MODE [12:12] */
-#define BCHP_XPT_FE_MINI_PID_PARSER16_ALL_PASS_CTRL_PIDP_DEBUG_MODE_MASK 0x00001000
-#define BCHP_XPT_FE_MINI_PID_PARSER16_ALL_PASS_CTRL_PIDP_DEBUG_MODE_SHIFT 12
-#define BCHP_XPT_FE_MINI_PID_PARSER16_ALL_PASS_CTRL_PIDP_DEBUG_MODE_DEFAULT 0x00000000
-
-/* XPT_FE :: MINI_PID_PARSER16_ALL_PASS_CTRL :: ALL_PASS_PID_CH_NUM [11:00] */
-#define BCHP_XPT_FE_MINI_PID_PARSER16_ALL_PASS_CTRL_ALL_PASS_PID_CH_NUM_MASK 0x00000fff
-#define BCHP_XPT_FE_MINI_PID_PARSER16_ALL_PASS_CTRL_ALL_PASS_PID_CH_NUM_SHIFT 0
-#define BCHP_XPT_FE_MINI_PID_PARSER16_ALL_PASS_CTRL_ALL_PASS_PID_CH_NUM_DEFAULT 0x00000010
-
-/***************************************************************************
- *MINI_PID_PARSER17_CTRL1 - Data Transport Parser Band 17 Control Register
- ***************************************************************************/
-/* XPT_FE :: MINI_PID_PARSER17_CTRL1 :: reserved0 [31:29] */
-#define BCHP_XPT_FE_MINI_PID_PARSER17_CTRL1_reserved0_MASK 0xe0000000
-#define BCHP_XPT_FE_MINI_PID_PARSER17_CTRL1_reserved0_SHIFT 29
-
-/* XPT_FE :: MINI_PID_PARSER17_CTRL1 :: PARSER_TIMESTAMP_MODE [28:27] */
-#define BCHP_XPT_FE_MINI_PID_PARSER17_CTRL1_PARSER_TIMESTAMP_MODE_MASK 0x18000000
-#define BCHP_XPT_FE_MINI_PID_PARSER17_CTRL1_PARSER_TIMESTAMP_MODE_SHIFT 27
-#define BCHP_XPT_FE_MINI_PID_PARSER17_CTRL1_PARSER_TIMESTAMP_MODE_DEFAULT 0x00000002
-
-/* XPT_FE :: MINI_PID_PARSER17_CTRL1 :: PARSER_TSMF_SEL [26:23] */
-#define BCHP_XPT_FE_MINI_PID_PARSER17_CTRL1_PARSER_TSMF_SEL_MASK 0x07800000
-#define BCHP_XPT_FE_MINI_PID_PARSER17_CTRL1_PARSER_TSMF_SEL_SHIFT 23
-#define BCHP_XPT_FE_MINI_PID_PARSER17_CTRL1_PARSER_TSMF_SEL_DEFAULT 0x00000000
-
-/* XPT_FE :: MINI_PID_PARSER17_CTRL1 :: PARSER_TSMF_EN [22:22] */
-#define BCHP_XPT_FE_MINI_PID_PARSER17_CTRL1_PARSER_TSMF_EN_MASK 0x00400000
-#define BCHP_XPT_FE_MINI_PID_PARSER17_CTRL1_PARSER_TSMF_EN_SHIFT 22
-#define BCHP_XPT_FE_MINI_PID_PARSER17_CTRL1_PARSER_TSMF_EN_DEFAULT 0x00000000
-
-/* XPT_FE :: MINI_PID_PARSER17_CTRL1 :: PARSER_INPUT_SEL_MSB [21:21] */
-#define BCHP_XPT_FE_MINI_PID_PARSER17_CTRL1_PARSER_INPUT_SEL_MSB_MASK 0x00200000
-#define BCHP_XPT_FE_MINI_PID_PARSER17_CTRL1_PARSER_INPUT_SEL_MSB_SHIFT 21
-#define BCHP_XPT_FE_MINI_PID_PARSER17_CTRL1_PARSER_INPUT_SEL_MSB_DEFAULT 0x00000000
-
-/* XPT_FE :: MINI_PID_PARSER17_CTRL1 :: PARSER_ERROR_INPUT_TEI_IGNORE [20:20] */
-#define BCHP_XPT_FE_MINI_PID_PARSER17_CTRL1_PARSER_ERROR_INPUT_TEI_IGNORE_MASK 0x00100000
-#define BCHP_XPT_FE_MINI_PID_PARSER17_CTRL1_PARSER_ERROR_INPUT_TEI_IGNORE_SHIFT 20
-#define BCHP_XPT_FE_MINI_PID_PARSER17_CTRL1_PARSER_ERROR_INPUT_TEI_IGNORE_DEFAULT 0x00000000
-
-/* XPT_FE :: MINI_PID_PARSER17_CTRL1 :: PARSER_PKT_LENGTH [19:12] */
-#define BCHP_XPT_FE_MINI_PID_PARSER17_CTRL1_PARSER_PKT_LENGTH_MASK 0x000ff000
-#define BCHP_XPT_FE_MINI_PID_PARSER17_CTRL1_PARSER_PKT_LENGTH_SHIFT 12
-#define BCHP_XPT_FE_MINI_PID_PARSER17_CTRL1_PARSER_PKT_LENGTH_DEFAULT 0x000000bc
-
-/* XPT_FE :: MINI_PID_PARSER17_CTRL1 :: PARSER_INPUT_SEL [11:08] */
-#define BCHP_XPT_FE_MINI_PID_PARSER17_CTRL1_PARSER_INPUT_SEL_MASK 0x00000f00
-#define BCHP_XPT_FE_MINI_PID_PARSER17_CTRL1_PARSER_INPUT_SEL_SHIFT 8
-#define BCHP_XPT_FE_MINI_PID_PARSER17_CTRL1_PARSER_INPUT_SEL_DEFAULT 0x00000000
-
-/* XPT_FE :: MINI_PID_PARSER17_CTRL1 :: reserved1 [07:07] */
-#define BCHP_XPT_FE_MINI_PID_PARSER17_CTRL1_reserved1_MASK 0x00000080
-#define BCHP_XPT_FE_MINI_PID_PARSER17_CTRL1_reserved1_SHIFT 7
-
-/* XPT_FE :: MINI_PID_PARSER17_CTRL1 :: PARSER_PACKET_TYPE [06:05] */
-#define BCHP_XPT_FE_MINI_PID_PARSER17_CTRL1_PARSER_PACKET_TYPE_MASK 0x00000060
-#define BCHP_XPT_FE_MINI_PID_PARSER17_CTRL1_PARSER_PACKET_TYPE_SHIFT 5
-#define BCHP_XPT_FE_MINI_PID_PARSER17_CTRL1_PARSER_PACKET_TYPE_DEFAULT 0x00000000
-
-/* XPT_FE :: MINI_PID_PARSER17_CTRL1 :: PARSER_ACCEPT_NULL_PKT_PRE_MPOD [04:04] */
-#define BCHP_XPT_FE_MINI_PID_PARSER17_CTRL1_PARSER_ACCEPT_NULL_PKT_PRE_MPOD_MASK 0x00000010
-#define BCHP_XPT_FE_MINI_PID_PARSER17_CTRL1_PARSER_ACCEPT_NULL_PKT_PRE_MPOD_SHIFT 4
-#define BCHP_XPT_FE_MINI_PID_PARSER17_CTRL1_PARSER_ACCEPT_NULL_PKT_PRE_MPOD_DEFAULT 0x00000000
-
-/* XPT_FE :: MINI_PID_PARSER17_CTRL1 :: PARSER_ACCEPT_NULL_PKT_PRE_TSIO [03:03] */
-#define BCHP_XPT_FE_MINI_PID_PARSER17_CTRL1_PARSER_ACCEPT_NULL_PKT_PRE_TSIO_MASK 0x00000008
-#define BCHP_XPT_FE_MINI_PID_PARSER17_CTRL1_PARSER_ACCEPT_NULL_PKT_PRE_TSIO_SHIFT 3
-#define BCHP_XPT_FE_MINI_PID_PARSER17_CTRL1_PARSER_ACCEPT_NULL_PKT_PRE_TSIO_DEFAULT 0x00000000
-
-/* XPT_FE :: MINI_PID_PARSER17_CTRL1 :: PARSER_ALL_PASS_CTRL_PRE_TSIO [02:02] */
-#define BCHP_XPT_FE_MINI_PID_PARSER17_CTRL1_PARSER_ALL_PASS_CTRL_PRE_TSIO_MASK 0x00000004
-#define BCHP_XPT_FE_MINI_PID_PARSER17_CTRL1_PARSER_ALL_PASS_CTRL_PRE_TSIO_SHIFT 2
-#define BCHP_XPT_FE_MINI_PID_PARSER17_CTRL1_PARSER_ALL_PASS_CTRL_PRE_TSIO_DEFAULT 0x00000000
-
-/* XPT_FE :: MINI_PID_PARSER17_CTRL1 :: PARSER_ALL_PASS_CTRL_PRE_MPOD [01:01] */
-#define BCHP_XPT_FE_MINI_PID_PARSER17_CTRL1_PARSER_ALL_PASS_CTRL_PRE_MPOD_MASK 0x00000002
-#define BCHP_XPT_FE_MINI_PID_PARSER17_CTRL1_PARSER_ALL_PASS_CTRL_PRE_MPOD_SHIFT 1
-#define BCHP_XPT_FE_MINI_PID_PARSER17_CTRL1_PARSER_ALL_PASS_CTRL_PRE_MPOD_DEFAULT 0x00000000
-
-/* XPT_FE :: MINI_PID_PARSER17_CTRL1 :: PARSER_ENABLE [00:00] */
-#define BCHP_XPT_FE_MINI_PID_PARSER17_CTRL1_PARSER_ENABLE_MASK 0x00000001
-#define BCHP_XPT_FE_MINI_PID_PARSER17_CTRL1_PARSER_ENABLE_SHIFT 0
-#define BCHP_XPT_FE_MINI_PID_PARSER17_CTRL1_PARSER_ENABLE_DEFAULT 0x00000000
-
-/***************************************************************************
- *MINI_PID_PARSER17_CTRL2 - Data Transport Parser Band 17 Control Register 2
- ***************************************************************************/
-/* XPT_FE :: MINI_PID_PARSER17_CTRL2 :: reserved0 [31:14] */
-#define BCHP_XPT_FE_MINI_PID_PARSER17_CTRL2_reserved0_MASK 0xffffc000
-#define BCHP_XPT_FE_MINI_PID_PARSER17_CTRL2_reserved0_SHIFT 14
-
-/* XPT_FE :: MINI_PID_PARSER17_CTRL2 :: PARSER_STREAM_TIMESTAMP_EN [13:13] */
-#define BCHP_XPT_FE_MINI_PID_PARSER17_CTRL2_PARSER_STREAM_TIMESTAMP_EN_MASK 0x00002000
-#define BCHP_XPT_FE_MINI_PID_PARSER17_CTRL2_PARSER_STREAM_TIMESTAMP_EN_SHIFT 13
-#define BCHP_XPT_FE_MINI_PID_PARSER17_CTRL2_PARSER_STREAM_TIMESTAMP_EN_DEFAULT 0x00000000
-
-/* XPT_FE :: MINI_PID_PARSER17_CTRL2 :: PARSER_TIMESTREAM_BF_SYNC [12:12] */
-#define BCHP_XPT_FE_MINI_PID_PARSER17_CTRL2_PARSER_TIMESTREAM_BF_SYNC_MASK 0x00001000
-#define BCHP_XPT_FE_MINI_PID_PARSER17_CTRL2_PARSER_TIMESTREAM_BF_SYNC_SHIFT 12
-#define BCHP_XPT_FE_MINI_PID_PARSER17_CTRL2_PARSER_TIMESTREAM_BF_SYNC_DEFAULT 0x00000000
-
-/* XPT_FE :: MINI_PID_PARSER17_CTRL2 :: reserved1 [11:11] */
-#define BCHP_XPT_FE_MINI_PID_PARSER17_CTRL2_reserved1_MASK 0x00000800
-#define BCHP_XPT_FE_MINI_PID_PARSER17_CTRL2_reserved1_SHIFT 11
-
-/* XPT_FE :: MINI_PID_PARSER17_CTRL2 :: PARSER_TIMESTAMP_RESTAMP [10:10] */
-#define BCHP_XPT_FE_MINI_PID_PARSER17_CTRL2_PARSER_TIMESTAMP_RESTAMP_MASK 0x00000400
-#define BCHP_XPT_FE_MINI_PID_PARSER17_CTRL2_PARSER_TIMESTAMP_RESTAMP_SHIFT 10
-#define BCHP_XPT_FE_MINI_PID_PARSER17_CTRL2_PARSER_TIMESTAMP_RESTAMP_DEFAULT 0x00000001
-
-/* XPT_FE :: MINI_PID_PARSER17_CTRL2 :: TSIO_MODE_SEL [09:09] */
-#define BCHP_XPT_FE_MINI_PID_PARSER17_CTRL2_TSIO_MODE_SEL_MASK 0x00000200
-#define BCHP_XPT_FE_MINI_PID_PARSER17_CTRL2_TSIO_MODE_SEL_SHIFT 9
-#define BCHP_XPT_FE_MINI_PID_PARSER17_CTRL2_TSIO_MODE_SEL_DEFAULT 0x00000001
-
-/* XPT_FE :: MINI_PID_PARSER17_CTRL2 :: reserved2 [08:07] */
-#define BCHP_XPT_FE_MINI_PID_PARSER17_CTRL2_reserved2_MASK 0x00000180
-#define BCHP_XPT_FE_MINI_PID_PARSER17_CTRL2_reserved2_SHIFT 7
-
-/* XPT_FE :: MINI_PID_PARSER17_CTRL2 :: TSIO_EN [06:06] */
-#define BCHP_XPT_FE_MINI_PID_PARSER17_CTRL2_TSIO_EN_MASK 0x00000040
-#define BCHP_XPT_FE_MINI_PID_PARSER17_CTRL2_TSIO_EN_SHIFT 6
-#define BCHP_XPT_FE_MINI_PID_PARSER17_CTRL2_TSIO_EN_DEFAULT 0x00000000
-
-/* XPT_FE :: MINI_PID_PARSER17_CTRL2 :: reserved3 [05:05] */
-#define BCHP_XPT_FE_MINI_PID_PARSER17_CTRL2_reserved3_MASK 0x00000020
-#define BCHP_XPT_FE_MINI_PID_PARSER17_CTRL2_reserved3_SHIFT 5
-
-/* XPT_FE :: MINI_PID_PARSER17_CTRL2 :: MPOD_MODE_SEL [04:04] */
-#define BCHP_XPT_FE_MINI_PID_PARSER17_CTRL2_MPOD_MODE_SEL_MASK 0x00000010
-#define BCHP_XPT_FE_MINI_PID_PARSER17_CTRL2_MPOD_MODE_SEL_SHIFT 4
-#define BCHP_XPT_FE_MINI_PID_PARSER17_CTRL2_MPOD_MODE_SEL_DEFAULT 0x00000000
-
-/* XPT_FE :: MINI_PID_PARSER17_CTRL2 :: reserved4 [03:03] */
-#define BCHP_XPT_FE_MINI_PID_PARSER17_CTRL2_reserved4_MASK 0x00000008
-#define BCHP_XPT_FE_MINI_PID_PARSER17_CTRL2_reserved4_SHIFT 3
-
-/* XPT_FE :: MINI_PID_PARSER17_CTRL2 :: PARSER_ACCEPT_NULL_PKT_POST_MPOD [02:02] */
-#define BCHP_XPT_FE_MINI_PID_PARSER17_CTRL2_PARSER_ACCEPT_NULL_PKT_POST_MPOD_MASK 0x00000004
-#define BCHP_XPT_FE_MINI_PID_PARSER17_CTRL2_PARSER_ACCEPT_NULL_PKT_POST_MPOD_SHIFT 2
-#define BCHP_XPT_FE_MINI_PID_PARSER17_CTRL2_PARSER_ACCEPT_NULL_PKT_POST_MPOD_DEFAULT 0x00000000
-
-/* XPT_FE :: MINI_PID_PARSER17_CTRL2 :: PARSER_ALL_PASS_CTRL_POST_MPOD [01:01] */
-#define BCHP_XPT_FE_MINI_PID_PARSER17_CTRL2_PARSER_ALL_PASS_CTRL_POST_MPOD_MASK 0x00000002
-#define BCHP_XPT_FE_MINI_PID_PARSER17_CTRL2_PARSER_ALL_PASS_CTRL_POST_MPOD_SHIFT 1
-#define BCHP_XPT_FE_MINI_PID_PARSER17_CTRL2_PARSER_ALL_PASS_CTRL_POST_MPOD_DEFAULT 0x00000000
-
-/* XPT_FE :: MINI_PID_PARSER17_CTRL2 :: MPOD_EN [00:00] */
-#define BCHP_XPT_FE_MINI_PID_PARSER17_CTRL2_MPOD_EN_MASK 0x00000001
-#define BCHP_XPT_FE_MINI_PID_PARSER17_CTRL2_MPOD_EN_SHIFT 0
-#define BCHP_XPT_FE_MINI_PID_PARSER17_CTRL2_MPOD_EN_DEFAULT 0x00000000
-
-/***************************************************************************
- *MINI_PID_PARSER17_ALL_PASS_CTRL - Data Transport Parser Band 17 Control Register
- ***************************************************************************/
-/* XPT_FE :: MINI_PID_PARSER17_ALL_PASS_CTRL :: reserved0 [31:13] */
-#define BCHP_XPT_FE_MINI_PID_PARSER17_ALL_PASS_CTRL_reserved0_MASK 0xffffe000
-#define BCHP_XPT_FE_MINI_PID_PARSER17_ALL_PASS_CTRL_reserved0_SHIFT 13
-
-/* XPT_FE :: MINI_PID_PARSER17_ALL_PASS_CTRL :: PIDP_DEBUG_MODE [12:12] */
-#define BCHP_XPT_FE_MINI_PID_PARSER17_ALL_PASS_CTRL_PIDP_DEBUG_MODE_MASK 0x00001000
-#define BCHP_XPT_FE_MINI_PID_PARSER17_ALL_PASS_CTRL_PIDP_DEBUG_MODE_SHIFT 12
-#define BCHP_XPT_FE_MINI_PID_PARSER17_ALL_PASS_CTRL_PIDP_DEBUG_MODE_DEFAULT 0x00000000
-
-/* XPT_FE :: MINI_PID_PARSER17_ALL_PASS_CTRL :: ALL_PASS_PID_CH_NUM [11:00] */
-#define BCHP_XPT_FE_MINI_PID_PARSER17_ALL_PASS_CTRL_ALL_PASS_PID_CH_NUM_MASK 0x00000fff
-#define BCHP_XPT_FE_MINI_PID_PARSER17_ALL_PASS_CTRL_ALL_PASS_PID_CH_NUM_SHIFT 0
-#define BCHP_XPT_FE_MINI_PID_PARSER17_ALL_PASS_CTRL_ALL_PASS_PID_CH_NUM_DEFAULT 0x00000011
-
-/***************************************************************************
- *MINI_PID_PARSER18_CTRL1 - Data Transport Parser Band 18 Control Register
- ***************************************************************************/
-/* XPT_FE :: MINI_PID_PARSER18_CTRL1 :: reserved0 [31:29] */
-#define BCHP_XPT_FE_MINI_PID_PARSER18_CTRL1_reserved0_MASK 0xe0000000
-#define BCHP_XPT_FE_MINI_PID_PARSER18_CTRL1_reserved0_SHIFT 29
-
-/* XPT_FE :: MINI_PID_PARSER18_CTRL1 :: PARSER_TIMESTAMP_MODE [28:27] */
-#define BCHP_XPT_FE_MINI_PID_PARSER18_CTRL1_PARSER_TIMESTAMP_MODE_MASK 0x18000000
-#define BCHP_XPT_FE_MINI_PID_PARSER18_CTRL1_PARSER_TIMESTAMP_MODE_SHIFT 27
-#define BCHP_XPT_FE_MINI_PID_PARSER18_CTRL1_PARSER_TIMESTAMP_MODE_DEFAULT 0x00000002
-
-/* XPT_FE :: MINI_PID_PARSER18_CTRL1 :: PARSER_TSMF_SEL [26:23] */
-#define BCHP_XPT_FE_MINI_PID_PARSER18_CTRL1_PARSER_TSMF_SEL_MASK 0x07800000
-#define BCHP_XPT_FE_MINI_PID_PARSER18_CTRL1_PARSER_TSMF_SEL_SHIFT 23
-#define BCHP_XPT_FE_MINI_PID_PARSER18_CTRL1_PARSER_TSMF_SEL_DEFAULT 0x00000000
-
-/* XPT_FE :: MINI_PID_PARSER18_CTRL1 :: PARSER_TSMF_EN [22:22] */
-#define BCHP_XPT_FE_MINI_PID_PARSER18_CTRL1_PARSER_TSMF_EN_MASK 0x00400000
-#define BCHP_XPT_FE_MINI_PID_PARSER18_CTRL1_PARSER_TSMF_EN_SHIFT 22
-#define BCHP_XPT_FE_MINI_PID_PARSER18_CTRL1_PARSER_TSMF_EN_DEFAULT 0x00000000
-
-/* XPT_FE :: MINI_PID_PARSER18_CTRL1 :: PARSER_INPUT_SEL_MSB [21:21] */
-#define BCHP_XPT_FE_MINI_PID_PARSER18_CTRL1_PARSER_INPUT_SEL_MSB_MASK 0x00200000
-#define BCHP_XPT_FE_MINI_PID_PARSER18_CTRL1_PARSER_INPUT_SEL_MSB_SHIFT 21
-#define BCHP_XPT_FE_MINI_PID_PARSER18_CTRL1_PARSER_INPUT_SEL_MSB_DEFAULT 0x00000000
-
-/* XPT_FE :: MINI_PID_PARSER18_CTRL1 :: PARSER_ERROR_INPUT_TEI_IGNORE [20:20] */
-#define BCHP_XPT_FE_MINI_PID_PARSER18_CTRL1_PARSER_ERROR_INPUT_TEI_IGNORE_MASK 0x00100000
-#define BCHP_XPT_FE_MINI_PID_PARSER18_CTRL1_PARSER_ERROR_INPUT_TEI_IGNORE_SHIFT 20
-#define BCHP_XPT_FE_MINI_PID_PARSER18_CTRL1_PARSER_ERROR_INPUT_TEI_IGNORE_DEFAULT 0x00000000
-
-/* XPT_FE :: MINI_PID_PARSER18_CTRL1 :: PARSER_PKT_LENGTH [19:12] */
-#define BCHP_XPT_FE_MINI_PID_PARSER18_CTRL1_PARSER_PKT_LENGTH_MASK 0x000ff000
-#define BCHP_XPT_FE_MINI_PID_PARSER18_CTRL1_PARSER_PKT_LENGTH_SHIFT 12
-#define BCHP_XPT_FE_MINI_PID_PARSER18_CTRL1_PARSER_PKT_LENGTH_DEFAULT 0x000000bc
-
-/* XPT_FE :: MINI_PID_PARSER18_CTRL1 :: PARSER_INPUT_SEL [11:08] */
-#define BCHP_XPT_FE_MINI_PID_PARSER18_CTRL1_PARSER_INPUT_SEL_MASK 0x00000f00
-#define BCHP_XPT_FE_MINI_PID_PARSER18_CTRL1_PARSER_INPUT_SEL_SHIFT 8
-#define BCHP_XPT_FE_MINI_PID_PARSER18_CTRL1_PARSER_INPUT_SEL_DEFAULT 0x00000000
-
-/* XPT_FE :: MINI_PID_PARSER18_CTRL1 :: reserved1 [07:07] */
-#define BCHP_XPT_FE_MINI_PID_PARSER18_CTRL1_reserved1_MASK 0x00000080
-#define BCHP_XPT_FE_MINI_PID_PARSER18_CTRL1_reserved1_SHIFT 7
-
-/* XPT_FE :: MINI_PID_PARSER18_CTRL1 :: PARSER_PACKET_TYPE [06:05] */
-#define BCHP_XPT_FE_MINI_PID_PARSER18_CTRL1_PARSER_PACKET_TYPE_MASK 0x00000060
-#define BCHP_XPT_FE_MINI_PID_PARSER18_CTRL1_PARSER_PACKET_TYPE_SHIFT 5
-#define BCHP_XPT_FE_MINI_PID_PARSER18_CTRL1_PARSER_PACKET_TYPE_DEFAULT 0x00000000
-
-/* XPT_FE :: MINI_PID_PARSER18_CTRL1 :: PARSER_ACCEPT_NULL_PKT_PRE_MPOD [04:04] */
-#define BCHP_XPT_FE_MINI_PID_PARSER18_CTRL1_PARSER_ACCEPT_NULL_PKT_PRE_MPOD_MASK 0x00000010
-#define BCHP_XPT_FE_MINI_PID_PARSER18_CTRL1_PARSER_ACCEPT_NULL_PKT_PRE_MPOD_SHIFT 4
-#define BCHP_XPT_FE_MINI_PID_PARSER18_CTRL1_PARSER_ACCEPT_NULL_PKT_PRE_MPOD_DEFAULT 0x00000000
-
-/* XPT_FE :: MINI_PID_PARSER18_CTRL1 :: PARSER_ACCEPT_NULL_PKT_PRE_TSIO [03:03] */
-#define BCHP_XPT_FE_MINI_PID_PARSER18_CTRL1_PARSER_ACCEPT_NULL_PKT_PRE_TSIO_MASK 0x00000008
-#define BCHP_XPT_FE_MINI_PID_PARSER18_CTRL1_PARSER_ACCEPT_NULL_PKT_PRE_TSIO_SHIFT 3
-#define BCHP_XPT_FE_MINI_PID_PARSER18_CTRL1_PARSER_ACCEPT_NULL_PKT_PRE_TSIO_DEFAULT 0x00000000
-
-/* XPT_FE :: MINI_PID_PARSER18_CTRL1 :: PARSER_ALL_PASS_CTRL_PRE_TSIO [02:02] */
-#define BCHP_XPT_FE_MINI_PID_PARSER18_CTRL1_PARSER_ALL_PASS_CTRL_PRE_TSIO_MASK 0x00000004
-#define BCHP_XPT_FE_MINI_PID_PARSER18_CTRL1_PARSER_ALL_PASS_CTRL_PRE_TSIO_SHIFT 2
-#define BCHP_XPT_FE_MINI_PID_PARSER18_CTRL1_PARSER_ALL_PASS_CTRL_PRE_TSIO_DEFAULT 0x00000000
-
-/* XPT_FE :: MINI_PID_PARSER18_CTRL1 :: PARSER_ALL_PASS_CTRL_PRE_MPOD [01:01] */
-#define BCHP_XPT_FE_MINI_PID_PARSER18_CTRL1_PARSER_ALL_PASS_CTRL_PRE_MPOD_MASK 0x00000002
-#define BCHP_XPT_FE_MINI_PID_PARSER18_CTRL1_PARSER_ALL_PASS_CTRL_PRE_MPOD_SHIFT 1
-#define BCHP_XPT_FE_MINI_PID_PARSER18_CTRL1_PARSER_ALL_PASS_CTRL_PRE_MPOD_DEFAULT 0x00000000
-
-/* XPT_FE :: MINI_PID_PARSER18_CTRL1 :: PARSER_ENABLE [00:00] */
-#define BCHP_XPT_FE_MINI_PID_PARSER18_CTRL1_PARSER_ENABLE_MASK 0x00000001
-#define BCHP_XPT_FE_MINI_PID_PARSER18_CTRL1_PARSER_ENABLE_SHIFT 0
-#define BCHP_XPT_FE_MINI_PID_PARSER18_CTRL1_PARSER_ENABLE_DEFAULT 0x00000000
-
-/***************************************************************************
- *MINI_PID_PARSER18_CTRL2 - Data Transport Parser Band 18 Control Register 2
- ***************************************************************************/
-/* XPT_FE :: MINI_PID_PARSER18_CTRL2 :: reserved0 [31:14] */
-#define BCHP_XPT_FE_MINI_PID_PARSER18_CTRL2_reserved0_MASK 0xffffc000
-#define BCHP_XPT_FE_MINI_PID_PARSER18_CTRL2_reserved0_SHIFT 14
-
-/* XPT_FE :: MINI_PID_PARSER18_CTRL2 :: PARSER_STREAM_TIMESTAMP_EN [13:13] */
-#define BCHP_XPT_FE_MINI_PID_PARSER18_CTRL2_PARSER_STREAM_TIMESTAMP_EN_MASK 0x00002000
-#define BCHP_XPT_FE_MINI_PID_PARSER18_CTRL2_PARSER_STREAM_TIMESTAMP_EN_SHIFT 13
-#define BCHP_XPT_FE_MINI_PID_PARSER18_CTRL2_PARSER_STREAM_TIMESTAMP_EN_DEFAULT 0x00000000
-
-/* XPT_FE :: MINI_PID_PARSER18_CTRL2 :: PARSER_TIMESTREAM_BF_SYNC [12:12] */
-#define BCHP_XPT_FE_MINI_PID_PARSER18_CTRL2_PARSER_TIMESTREAM_BF_SYNC_MASK 0x00001000
-#define BCHP_XPT_FE_MINI_PID_PARSER18_CTRL2_PARSER_TIMESTREAM_BF_SYNC_SHIFT 12
-#define BCHP_XPT_FE_MINI_PID_PARSER18_CTRL2_PARSER_TIMESTREAM_BF_SYNC_DEFAULT 0x00000000
-
-/* XPT_FE :: MINI_PID_PARSER18_CTRL2 :: reserved1 [11:11] */
-#define BCHP_XPT_FE_MINI_PID_PARSER18_CTRL2_reserved1_MASK 0x00000800
-#define BCHP_XPT_FE_MINI_PID_PARSER18_CTRL2_reserved1_SHIFT 11
-
-/* XPT_FE :: MINI_PID_PARSER18_CTRL2 :: PARSER_TIMESTAMP_RESTAMP [10:10] */
-#define BCHP_XPT_FE_MINI_PID_PARSER18_CTRL2_PARSER_TIMESTAMP_RESTAMP_MASK 0x00000400
-#define BCHP_XPT_FE_MINI_PID_PARSER18_CTRL2_PARSER_TIMESTAMP_RESTAMP_SHIFT 10
-#define BCHP_XPT_FE_MINI_PID_PARSER18_CTRL2_PARSER_TIMESTAMP_RESTAMP_DEFAULT 0x00000001
-
-/* XPT_FE :: MINI_PID_PARSER18_CTRL2 :: TSIO_MODE_SEL [09:09] */
-#define BCHP_XPT_FE_MINI_PID_PARSER18_CTRL2_TSIO_MODE_SEL_MASK 0x00000200
-#define BCHP_XPT_FE_MINI_PID_PARSER18_CTRL2_TSIO_MODE_SEL_SHIFT 9
-#define BCHP_XPT_FE_MINI_PID_PARSER18_CTRL2_TSIO_MODE_SEL_DEFAULT 0x00000001
-
-/* XPT_FE :: MINI_PID_PARSER18_CTRL2 :: reserved2 [08:07] */
-#define BCHP_XPT_FE_MINI_PID_PARSER18_CTRL2_reserved2_MASK 0x00000180
-#define BCHP_XPT_FE_MINI_PID_PARSER18_CTRL2_reserved2_SHIFT 7
-
-/* XPT_FE :: MINI_PID_PARSER18_CTRL2 :: TSIO_EN [06:06] */
-#define BCHP_XPT_FE_MINI_PID_PARSER18_CTRL2_TSIO_EN_MASK 0x00000040
-#define BCHP_XPT_FE_MINI_PID_PARSER18_CTRL2_TSIO_EN_SHIFT 6
-#define BCHP_XPT_FE_MINI_PID_PARSER18_CTRL2_TSIO_EN_DEFAULT 0x00000000
-
-/* XPT_FE :: MINI_PID_PARSER18_CTRL2 :: reserved3 [05:05] */
-#define BCHP_XPT_FE_MINI_PID_PARSER18_CTRL2_reserved3_MASK 0x00000020
-#define BCHP_XPT_FE_MINI_PID_PARSER18_CTRL2_reserved3_SHIFT 5
-
-/* XPT_FE :: MINI_PID_PARSER18_CTRL2 :: MPOD_MODE_SEL [04:04] */
-#define BCHP_XPT_FE_MINI_PID_PARSER18_CTRL2_MPOD_MODE_SEL_MASK 0x00000010
-#define BCHP_XPT_FE_MINI_PID_PARSER18_CTRL2_MPOD_MODE_SEL_SHIFT 4
-#define BCHP_XPT_FE_MINI_PID_PARSER18_CTRL2_MPOD_MODE_SEL_DEFAULT 0x00000000
-
-/* XPT_FE :: MINI_PID_PARSER18_CTRL2 :: reserved4 [03:03] */
-#define BCHP_XPT_FE_MINI_PID_PARSER18_CTRL2_reserved4_MASK 0x00000008
-#define BCHP_XPT_FE_MINI_PID_PARSER18_CTRL2_reserved4_SHIFT 3
-
-/* XPT_FE :: MINI_PID_PARSER18_CTRL2 :: PARSER_ACCEPT_NULL_PKT_POST_MPOD [02:02] */
-#define BCHP_XPT_FE_MINI_PID_PARSER18_CTRL2_PARSER_ACCEPT_NULL_PKT_POST_MPOD_MASK 0x00000004
-#define BCHP_XPT_FE_MINI_PID_PARSER18_CTRL2_PARSER_ACCEPT_NULL_PKT_POST_MPOD_SHIFT 2
-#define BCHP_XPT_FE_MINI_PID_PARSER18_CTRL2_PARSER_ACCEPT_NULL_PKT_POST_MPOD_DEFAULT 0x00000000
-
-/* XPT_FE :: MINI_PID_PARSER18_CTRL2 :: PARSER_ALL_PASS_CTRL_POST_MPOD [01:01] */
-#define BCHP_XPT_FE_MINI_PID_PARSER18_CTRL2_PARSER_ALL_PASS_CTRL_POST_MPOD_MASK 0x00000002
-#define BCHP_XPT_FE_MINI_PID_PARSER18_CTRL2_PARSER_ALL_PASS_CTRL_POST_MPOD_SHIFT 1
-#define BCHP_XPT_FE_MINI_PID_PARSER18_CTRL2_PARSER_ALL_PASS_CTRL_POST_MPOD_DEFAULT 0x00000000
-
-/* XPT_FE :: MINI_PID_PARSER18_CTRL2 :: MPOD_EN [00:00] */
-#define BCHP_XPT_FE_MINI_PID_PARSER18_CTRL2_MPOD_EN_MASK 0x00000001
-#define BCHP_XPT_FE_MINI_PID_PARSER18_CTRL2_MPOD_EN_SHIFT 0
-#define BCHP_XPT_FE_MINI_PID_PARSER18_CTRL2_MPOD_EN_DEFAULT 0x00000000
-
-/***************************************************************************
- *MINI_PID_PARSER18_ALL_PASS_CTRL - Data Transport Parser Band 18 Control Register
- ***************************************************************************/
-/* XPT_FE :: MINI_PID_PARSER18_ALL_PASS_CTRL :: reserved0 [31:13] */
-#define BCHP_XPT_FE_MINI_PID_PARSER18_ALL_PASS_CTRL_reserved0_MASK 0xffffe000
-#define BCHP_XPT_FE_MINI_PID_PARSER18_ALL_PASS_CTRL_reserved0_SHIFT 13
-
-/* XPT_FE :: MINI_PID_PARSER18_ALL_PASS_CTRL :: PIDP_DEBUG_MODE [12:12] */
-#define BCHP_XPT_FE_MINI_PID_PARSER18_ALL_PASS_CTRL_PIDP_DEBUG_MODE_MASK 0x00001000
-#define BCHP_XPT_FE_MINI_PID_PARSER18_ALL_PASS_CTRL_PIDP_DEBUG_MODE_SHIFT 12
-#define BCHP_XPT_FE_MINI_PID_PARSER18_ALL_PASS_CTRL_PIDP_DEBUG_MODE_DEFAULT 0x00000000
-
-/* XPT_FE :: MINI_PID_PARSER18_ALL_PASS_CTRL :: ALL_PASS_PID_CH_NUM [11:00] */
-#define BCHP_XPT_FE_MINI_PID_PARSER18_ALL_PASS_CTRL_ALL_PASS_PID_CH_NUM_MASK 0x00000fff
-#define BCHP_XPT_FE_MINI_PID_PARSER18_ALL_PASS_CTRL_ALL_PASS_PID_CH_NUM_SHIFT 0
-#define BCHP_XPT_FE_MINI_PID_PARSER18_ALL_PASS_CTRL_ALL_PASS_PID_CH_NUM_DEFAULT 0x00000012
-
-/***************************************************************************
- *MINI_PID_PARSER19_CTRL1 - Data Transport Parser Band 19 Control Register
- ***************************************************************************/
-/* XPT_FE :: MINI_PID_PARSER19_CTRL1 :: reserved0 [31:29] */
-#define BCHP_XPT_FE_MINI_PID_PARSER19_CTRL1_reserved0_MASK 0xe0000000
-#define BCHP_XPT_FE_MINI_PID_PARSER19_CTRL1_reserved0_SHIFT 29
-
-/* XPT_FE :: MINI_PID_PARSER19_CTRL1 :: PARSER_TIMESTAMP_MODE [28:27] */
-#define BCHP_XPT_FE_MINI_PID_PARSER19_CTRL1_PARSER_TIMESTAMP_MODE_MASK 0x18000000
-#define BCHP_XPT_FE_MINI_PID_PARSER19_CTRL1_PARSER_TIMESTAMP_MODE_SHIFT 27
-#define BCHP_XPT_FE_MINI_PID_PARSER19_CTRL1_PARSER_TIMESTAMP_MODE_DEFAULT 0x00000002
-
-/* XPT_FE :: MINI_PID_PARSER19_CTRL1 :: PARSER_TSMF_SEL [26:23] */
-#define BCHP_XPT_FE_MINI_PID_PARSER19_CTRL1_PARSER_TSMF_SEL_MASK 0x07800000
-#define BCHP_XPT_FE_MINI_PID_PARSER19_CTRL1_PARSER_TSMF_SEL_SHIFT 23
-#define BCHP_XPT_FE_MINI_PID_PARSER19_CTRL1_PARSER_TSMF_SEL_DEFAULT 0x00000000
-
-/* XPT_FE :: MINI_PID_PARSER19_CTRL1 :: PARSER_TSMF_EN [22:22] */
-#define BCHP_XPT_FE_MINI_PID_PARSER19_CTRL1_PARSER_TSMF_EN_MASK 0x00400000
-#define BCHP_XPT_FE_MINI_PID_PARSER19_CTRL1_PARSER_TSMF_EN_SHIFT 22
-#define BCHP_XPT_FE_MINI_PID_PARSER19_CTRL1_PARSER_TSMF_EN_DEFAULT 0x00000000
-
-/* XPT_FE :: MINI_PID_PARSER19_CTRL1 :: PARSER_INPUT_SEL_MSB [21:21] */
-#define BCHP_XPT_FE_MINI_PID_PARSER19_CTRL1_PARSER_INPUT_SEL_MSB_MASK 0x00200000
-#define BCHP_XPT_FE_MINI_PID_PARSER19_CTRL1_PARSER_INPUT_SEL_MSB_SHIFT 21
-#define BCHP_XPT_FE_MINI_PID_PARSER19_CTRL1_PARSER_INPUT_SEL_MSB_DEFAULT 0x00000000
-
-/* XPT_FE :: MINI_PID_PARSER19_CTRL1 :: PARSER_ERROR_INPUT_TEI_IGNORE [20:20] */
-#define BCHP_XPT_FE_MINI_PID_PARSER19_CTRL1_PARSER_ERROR_INPUT_TEI_IGNORE_MASK 0x00100000
-#define BCHP_XPT_FE_MINI_PID_PARSER19_CTRL1_PARSER_ERROR_INPUT_TEI_IGNORE_SHIFT 20
-#define BCHP_XPT_FE_MINI_PID_PARSER19_CTRL1_PARSER_ERROR_INPUT_TEI_IGNORE_DEFAULT 0x00000000
-
-/* XPT_FE :: MINI_PID_PARSER19_CTRL1 :: PARSER_PKT_LENGTH [19:12] */
-#define BCHP_XPT_FE_MINI_PID_PARSER19_CTRL1_PARSER_PKT_LENGTH_MASK 0x000ff000
-#define BCHP_XPT_FE_MINI_PID_PARSER19_CTRL1_PARSER_PKT_LENGTH_SHIFT 12
-#define BCHP_XPT_FE_MINI_PID_PARSER19_CTRL1_PARSER_PKT_LENGTH_DEFAULT 0x000000bc
-
-/* XPT_FE :: MINI_PID_PARSER19_CTRL1 :: PARSER_INPUT_SEL [11:08] */
-#define BCHP_XPT_FE_MINI_PID_PARSER19_CTRL1_PARSER_INPUT_SEL_MASK 0x00000f00
-#define BCHP_XPT_FE_MINI_PID_PARSER19_CTRL1_PARSER_INPUT_SEL_SHIFT 8
-#define BCHP_XPT_FE_MINI_PID_PARSER19_CTRL1_PARSER_INPUT_SEL_DEFAULT 0x00000000
-
-/* XPT_FE :: MINI_PID_PARSER19_CTRL1 :: reserved1 [07:07] */
-#define BCHP_XPT_FE_MINI_PID_PARSER19_CTRL1_reserved1_MASK 0x00000080
-#define BCHP_XPT_FE_MINI_PID_PARSER19_CTRL1_reserved1_SHIFT 7
-
-/* XPT_FE :: MINI_PID_PARSER19_CTRL1 :: PARSER_PACKET_TYPE [06:05] */
-#define BCHP_XPT_FE_MINI_PID_PARSER19_CTRL1_PARSER_PACKET_TYPE_MASK 0x00000060
-#define BCHP_XPT_FE_MINI_PID_PARSER19_CTRL1_PARSER_PACKET_TYPE_SHIFT 5
-#define BCHP_XPT_FE_MINI_PID_PARSER19_CTRL1_PARSER_PACKET_TYPE_DEFAULT 0x00000000
-
-/* XPT_FE :: MINI_PID_PARSER19_CTRL1 :: PARSER_ACCEPT_NULL_PKT_PRE_MPOD [04:04] */
-#define BCHP_XPT_FE_MINI_PID_PARSER19_CTRL1_PARSER_ACCEPT_NULL_PKT_PRE_MPOD_MASK 0x00000010
-#define BCHP_XPT_FE_MINI_PID_PARSER19_CTRL1_PARSER_ACCEPT_NULL_PKT_PRE_MPOD_SHIFT 4
-#define BCHP_XPT_FE_MINI_PID_PARSER19_CTRL1_PARSER_ACCEPT_NULL_PKT_PRE_MPOD_DEFAULT 0x00000000
-
-/* XPT_FE :: MINI_PID_PARSER19_CTRL1 :: PARSER_ACCEPT_NULL_PKT_PRE_TSIO [03:03] */
-#define BCHP_XPT_FE_MINI_PID_PARSER19_CTRL1_PARSER_ACCEPT_NULL_PKT_PRE_TSIO_MASK 0x00000008
-#define BCHP_XPT_FE_MINI_PID_PARSER19_CTRL1_PARSER_ACCEPT_NULL_PKT_PRE_TSIO_SHIFT 3
-#define BCHP_XPT_FE_MINI_PID_PARSER19_CTRL1_PARSER_ACCEPT_NULL_PKT_PRE_TSIO_DEFAULT 0x00000000
-
-/* XPT_FE :: MINI_PID_PARSER19_CTRL1 :: PARSER_ALL_PASS_CTRL_PRE_TSIO [02:02] */
-#define BCHP_XPT_FE_MINI_PID_PARSER19_CTRL1_PARSER_ALL_PASS_CTRL_PRE_TSIO_MASK 0x00000004
-#define BCHP_XPT_FE_MINI_PID_PARSER19_CTRL1_PARSER_ALL_PASS_CTRL_PRE_TSIO_SHIFT 2
-#define BCHP_XPT_FE_MINI_PID_PARSER19_CTRL1_PARSER_ALL_PASS_CTRL_PRE_TSIO_DEFAULT 0x00000000
-
-/* XPT_FE :: MINI_PID_PARSER19_CTRL1 :: PARSER_ALL_PASS_CTRL_PRE_MPOD [01:01] */
-#define BCHP_XPT_FE_MINI_PID_PARSER19_CTRL1_PARSER_ALL_PASS_CTRL_PRE_MPOD_MASK 0x00000002
-#define BCHP_XPT_FE_MINI_PID_PARSER19_CTRL1_PARSER_ALL_PASS_CTRL_PRE_MPOD_SHIFT 1
-#define BCHP_XPT_FE_MINI_PID_PARSER19_CTRL1_PARSER_ALL_PASS_CTRL_PRE_MPOD_DEFAULT 0x00000000
-
-/* XPT_FE :: MINI_PID_PARSER19_CTRL1 :: PARSER_ENABLE [00:00] */
-#define BCHP_XPT_FE_MINI_PID_PARSER19_CTRL1_PARSER_ENABLE_MASK 0x00000001
-#define BCHP_XPT_FE_MINI_PID_PARSER19_CTRL1_PARSER_ENABLE_SHIFT 0
-#define BCHP_XPT_FE_MINI_PID_PARSER19_CTRL1_PARSER_ENABLE_DEFAULT 0x00000000
-
-/***************************************************************************
- *MINI_PID_PARSER19_CTRL2 - Data Transport Parser Band 19 Control Register 2
- ***************************************************************************/
-/* XPT_FE :: MINI_PID_PARSER19_CTRL2 :: reserved0 [31:14] */
-#define BCHP_XPT_FE_MINI_PID_PARSER19_CTRL2_reserved0_MASK 0xffffc000
-#define BCHP_XPT_FE_MINI_PID_PARSER19_CTRL2_reserved0_SHIFT 14
-
-/* XPT_FE :: MINI_PID_PARSER19_CTRL2 :: PARSER_STREAM_TIMESTAMP_EN [13:13] */
-#define BCHP_XPT_FE_MINI_PID_PARSER19_CTRL2_PARSER_STREAM_TIMESTAMP_EN_MASK 0x00002000
-#define BCHP_XPT_FE_MINI_PID_PARSER19_CTRL2_PARSER_STREAM_TIMESTAMP_EN_SHIFT 13
-#define BCHP_XPT_FE_MINI_PID_PARSER19_CTRL2_PARSER_STREAM_TIMESTAMP_EN_DEFAULT 0x00000000
-
-/* XPT_FE :: MINI_PID_PARSER19_CTRL2 :: PARSER_TIMESTREAM_BF_SYNC [12:12] */
-#define BCHP_XPT_FE_MINI_PID_PARSER19_CTRL2_PARSER_TIMESTREAM_BF_SYNC_MASK 0x00001000
-#define BCHP_XPT_FE_MINI_PID_PARSER19_CTRL2_PARSER_TIMESTREAM_BF_SYNC_SHIFT 12
-#define BCHP_XPT_FE_MINI_PID_PARSER19_CTRL2_PARSER_TIMESTREAM_BF_SYNC_DEFAULT 0x00000000
-
-/* XPT_FE :: MINI_PID_PARSER19_CTRL2 :: reserved1 [11:11] */
-#define BCHP_XPT_FE_MINI_PID_PARSER19_CTRL2_reserved1_MASK 0x00000800
-#define BCHP_XPT_FE_MINI_PID_PARSER19_CTRL2_reserved1_SHIFT 11
-
-/* XPT_FE :: MINI_PID_PARSER19_CTRL2 :: PARSER_TIMESTAMP_RESTAMP [10:10] */
-#define BCHP_XPT_FE_MINI_PID_PARSER19_CTRL2_PARSER_TIMESTAMP_RESTAMP_MASK 0x00000400
-#define BCHP_XPT_FE_MINI_PID_PARSER19_CTRL2_PARSER_TIMESTAMP_RESTAMP_SHIFT 10
-#define BCHP_XPT_FE_MINI_PID_PARSER19_CTRL2_PARSER_TIMESTAMP_RESTAMP_DEFAULT 0x00000001
-
-/* XPT_FE :: MINI_PID_PARSER19_CTRL2 :: TSIO_MODE_SEL [09:09] */
-#define BCHP_XPT_FE_MINI_PID_PARSER19_CTRL2_TSIO_MODE_SEL_MASK 0x00000200
-#define BCHP_XPT_FE_MINI_PID_PARSER19_CTRL2_TSIO_MODE_SEL_SHIFT 9
-#define BCHP_XPT_FE_MINI_PID_PARSER19_CTRL2_TSIO_MODE_SEL_DEFAULT 0x00000001
-
-/* XPT_FE :: MINI_PID_PARSER19_CTRL2 :: reserved2 [08:07] */
-#define BCHP_XPT_FE_MINI_PID_PARSER19_CTRL2_reserved2_MASK 0x00000180
-#define BCHP_XPT_FE_MINI_PID_PARSER19_CTRL2_reserved2_SHIFT 7
-
-/* XPT_FE :: MINI_PID_PARSER19_CTRL2 :: TSIO_EN [06:06] */
-#define BCHP_XPT_FE_MINI_PID_PARSER19_CTRL2_TSIO_EN_MASK 0x00000040
-#define BCHP_XPT_FE_MINI_PID_PARSER19_CTRL2_TSIO_EN_SHIFT 6
-#define BCHP_XPT_FE_MINI_PID_PARSER19_CTRL2_TSIO_EN_DEFAULT 0x00000000
-
-/* XPT_FE :: MINI_PID_PARSER19_CTRL2 :: reserved3 [05:05] */
-#define BCHP_XPT_FE_MINI_PID_PARSER19_CTRL2_reserved3_MASK 0x00000020
-#define BCHP_XPT_FE_MINI_PID_PARSER19_CTRL2_reserved3_SHIFT 5
-
-/* XPT_FE :: MINI_PID_PARSER19_CTRL2 :: MPOD_MODE_SEL [04:04] */
-#define BCHP_XPT_FE_MINI_PID_PARSER19_CTRL2_MPOD_MODE_SEL_MASK 0x00000010
-#define BCHP_XPT_FE_MINI_PID_PARSER19_CTRL2_MPOD_MODE_SEL_SHIFT 4
-#define BCHP_XPT_FE_MINI_PID_PARSER19_CTRL2_MPOD_MODE_SEL_DEFAULT 0x00000000
-
-/* XPT_FE :: MINI_PID_PARSER19_CTRL2 :: reserved4 [03:03] */
-#define BCHP_XPT_FE_MINI_PID_PARSER19_CTRL2_reserved4_MASK 0x00000008
-#define BCHP_XPT_FE_MINI_PID_PARSER19_CTRL2_reserved4_SHIFT 3
-
-/* XPT_FE :: MINI_PID_PARSER19_CTRL2 :: PARSER_ACCEPT_NULL_PKT_POST_MPOD [02:02] */
-#define BCHP_XPT_FE_MINI_PID_PARSER19_CTRL2_PARSER_ACCEPT_NULL_PKT_POST_MPOD_MASK 0x00000004
-#define BCHP_XPT_FE_MINI_PID_PARSER19_CTRL2_PARSER_ACCEPT_NULL_PKT_POST_MPOD_SHIFT 2
-#define BCHP_XPT_FE_MINI_PID_PARSER19_CTRL2_PARSER_ACCEPT_NULL_PKT_POST_MPOD_DEFAULT 0x00000000
-
-/* XPT_FE :: MINI_PID_PARSER19_CTRL2 :: PARSER_ALL_PASS_CTRL_POST_MPOD [01:01] */
-#define BCHP_XPT_FE_MINI_PID_PARSER19_CTRL2_PARSER_ALL_PASS_CTRL_POST_MPOD_MASK 0x00000002
-#define BCHP_XPT_FE_MINI_PID_PARSER19_CTRL2_PARSER_ALL_PASS_CTRL_POST_MPOD_SHIFT 1
-#define BCHP_XPT_FE_MINI_PID_PARSER19_CTRL2_PARSER_ALL_PASS_CTRL_POST_MPOD_DEFAULT 0x00000000
-
-/* XPT_FE :: MINI_PID_PARSER19_CTRL2 :: MPOD_EN [00:00] */
-#define BCHP_XPT_FE_MINI_PID_PARSER19_CTRL2_MPOD_EN_MASK 0x00000001
-#define BCHP_XPT_FE_MINI_PID_PARSER19_CTRL2_MPOD_EN_SHIFT 0
-#define BCHP_XPT_FE_MINI_PID_PARSER19_CTRL2_MPOD_EN_DEFAULT 0x00000000
-
-/***************************************************************************
- *MINI_PID_PARSER19_ALL_PASS_CTRL - Data Transport Parser Band 19 Control Register
- ***************************************************************************/
-/* XPT_FE :: MINI_PID_PARSER19_ALL_PASS_CTRL :: reserved0 [31:13] */
-#define BCHP_XPT_FE_MINI_PID_PARSER19_ALL_PASS_CTRL_reserved0_MASK 0xffffe000
-#define BCHP_XPT_FE_MINI_PID_PARSER19_ALL_PASS_CTRL_reserved0_SHIFT 13
-
-/* XPT_FE :: MINI_PID_PARSER19_ALL_PASS_CTRL :: PIDP_DEBUG_MODE [12:12] */
-#define BCHP_XPT_FE_MINI_PID_PARSER19_ALL_PASS_CTRL_PIDP_DEBUG_MODE_MASK 0x00001000
-#define BCHP_XPT_FE_MINI_PID_PARSER19_ALL_PASS_CTRL_PIDP_DEBUG_MODE_SHIFT 12
-#define BCHP_XPT_FE_MINI_PID_PARSER19_ALL_PASS_CTRL_PIDP_DEBUG_MODE_DEFAULT 0x00000000
-
-/* XPT_FE :: MINI_PID_PARSER19_ALL_PASS_CTRL :: ALL_PASS_PID_CH_NUM [11:00] */
-#define BCHP_XPT_FE_MINI_PID_PARSER19_ALL_PASS_CTRL_ALL_PASS_PID_CH_NUM_MASK 0x00000fff
-#define BCHP_XPT_FE_MINI_PID_PARSER19_ALL_PASS_CTRL_ALL_PASS_PID_CH_NUM_SHIFT 0
-#define BCHP_XPT_FE_MINI_PID_PARSER19_ALL_PASS_CTRL_ALL_PASS_PID_CH_NUM_DEFAULT 0x00000013
-
-/***************************************************************************
- *MINI_PID_PARSER20_CTRL1 - Data Transport Parser Band 20 Control Register
- ***************************************************************************/
-/* XPT_FE :: MINI_PID_PARSER20_CTRL1 :: reserved0 [31:29] */
-#define BCHP_XPT_FE_MINI_PID_PARSER20_CTRL1_reserved0_MASK 0xe0000000
-#define BCHP_XPT_FE_MINI_PID_PARSER20_CTRL1_reserved0_SHIFT 29
-
-/* XPT_FE :: MINI_PID_PARSER20_CTRL1 :: PARSER_TIMESTAMP_MODE [28:27] */
-#define BCHP_XPT_FE_MINI_PID_PARSER20_CTRL1_PARSER_TIMESTAMP_MODE_MASK 0x18000000
-#define BCHP_XPT_FE_MINI_PID_PARSER20_CTRL1_PARSER_TIMESTAMP_MODE_SHIFT 27
-#define BCHP_XPT_FE_MINI_PID_PARSER20_CTRL1_PARSER_TIMESTAMP_MODE_DEFAULT 0x00000002
-
-/* XPT_FE :: MINI_PID_PARSER20_CTRL1 :: PARSER_TSMF_SEL [26:23] */
-#define BCHP_XPT_FE_MINI_PID_PARSER20_CTRL1_PARSER_TSMF_SEL_MASK 0x07800000
-#define BCHP_XPT_FE_MINI_PID_PARSER20_CTRL1_PARSER_TSMF_SEL_SHIFT 23
-#define BCHP_XPT_FE_MINI_PID_PARSER20_CTRL1_PARSER_TSMF_SEL_DEFAULT 0x00000000
-
-/* XPT_FE :: MINI_PID_PARSER20_CTRL1 :: PARSER_TSMF_EN [22:22] */
-#define BCHP_XPT_FE_MINI_PID_PARSER20_CTRL1_PARSER_TSMF_EN_MASK 0x00400000
-#define BCHP_XPT_FE_MINI_PID_PARSER20_CTRL1_PARSER_TSMF_EN_SHIFT 22
-#define BCHP_XPT_FE_MINI_PID_PARSER20_CTRL1_PARSER_TSMF_EN_DEFAULT 0x00000000
-
-/* XPT_FE :: MINI_PID_PARSER20_CTRL1 :: PARSER_INPUT_SEL_MSB [21:21] */
-#define BCHP_XPT_FE_MINI_PID_PARSER20_CTRL1_PARSER_INPUT_SEL_MSB_MASK 0x00200000
-#define BCHP_XPT_FE_MINI_PID_PARSER20_CTRL1_PARSER_INPUT_SEL_MSB_SHIFT 21
-#define BCHP_XPT_FE_MINI_PID_PARSER20_CTRL1_PARSER_INPUT_SEL_MSB_DEFAULT 0x00000000
-
-/* XPT_FE :: MINI_PID_PARSER20_CTRL1 :: PARSER_ERROR_INPUT_TEI_IGNORE [20:20] */
-#define BCHP_XPT_FE_MINI_PID_PARSER20_CTRL1_PARSER_ERROR_INPUT_TEI_IGNORE_MASK 0x00100000
-#define BCHP_XPT_FE_MINI_PID_PARSER20_CTRL1_PARSER_ERROR_INPUT_TEI_IGNORE_SHIFT 20
-#define BCHP_XPT_FE_MINI_PID_PARSER20_CTRL1_PARSER_ERROR_INPUT_TEI_IGNORE_DEFAULT 0x00000000
-
-/* XPT_FE :: MINI_PID_PARSER20_CTRL1 :: PARSER_PKT_LENGTH [19:12] */
-#define BCHP_XPT_FE_MINI_PID_PARSER20_CTRL1_PARSER_PKT_LENGTH_MASK 0x000ff000
-#define BCHP_XPT_FE_MINI_PID_PARSER20_CTRL1_PARSER_PKT_LENGTH_SHIFT 12
-#define BCHP_XPT_FE_MINI_PID_PARSER20_CTRL1_PARSER_PKT_LENGTH_DEFAULT 0x000000bc
-
-/* XPT_FE :: MINI_PID_PARSER20_CTRL1 :: PARSER_INPUT_SEL [11:08] */
-#define BCHP_XPT_FE_MINI_PID_PARSER20_CTRL1_PARSER_INPUT_SEL_MASK 0x00000f00
-#define BCHP_XPT_FE_MINI_PID_PARSER20_CTRL1_PARSER_INPUT_SEL_SHIFT 8
-#define BCHP_XPT_FE_MINI_PID_PARSER20_CTRL1_PARSER_INPUT_SEL_DEFAULT 0x00000000
-
-/* XPT_FE :: MINI_PID_PARSER20_CTRL1 :: reserved1 [07:07] */
-#define BCHP_XPT_FE_MINI_PID_PARSER20_CTRL1_reserved1_MASK 0x00000080
-#define BCHP_XPT_FE_MINI_PID_PARSER20_CTRL1_reserved1_SHIFT 7
-
-/* XPT_FE :: MINI_PID_PARSER20_CTRL1 :: PARSER_PACKET_TYPE [06:05] */
-#define BCHP_XPT_FE_MINI_PID_PARSER20_CTRL1_PARSER_PACKET_TYPE_MASK 0x00000060
-#define BCHP_XPT_FE_MINI_PID_PARSER20_CTRL1_PARSER_PACKET_TYPE_SHIFT 5
-#define BCHP_XPT_FE_MINI_PID_PARSER20_CTRL1_PARSER_PACKET_TYPE_DEFAULT 0x00000000
-
-/* XPT_FE :: MINI_PID_PARSER20_CTRL1 :: PARSER_ACCEPT_NULL_PKT_PRE_MPOD [04:04] */
-#define BCHP_XPT_FE_MINI_PID_PARSER20_CTRL1_PARSER_ACCEPT_NULL_PKT_PRE_MPOD_MASK 0x00000010
-#define BCHP_XPT_FE_MINI_PID_PARSER20_CTRL1_PARSER_ACCEPT_NULL_PKT_PRE_MPOD_SHIFT 4
-#define BCHP_XPT_FE_MINI_PID_PARSER20_CTRL1_PARSER_ACCEPT_NULL_PKT_PRE_MPOD_DEFAULT 0x00000000
-
-/* XPT_FE :: MINI_PID_PARSER20_CTRL1 :: PARSER_ACCEPT_NULL_PKT_PRE_TSIO [03:03] */
-#define BCHP_XPT_FE_MINI_PID_PARSER20_CTRL1_PARSER_ACCEPT_NULL_PKT_PRE_TSIO_MASK 0x00000008
-#define BCHP_XPT_FE_MINI_PID_PARSER20_CTRL1_PARSER_ACCEPT_NULL_PKT_PRE_TSIO_SHIFT 3
-#define BCHP_XPT_FE_MINI_PID_PARSER20_CTRL1_PARSER_ACCEPT_NULL_PKT_PRE_TSIO_DEFAULT 0x00000000
-
-/* XPT_FE :: MINI_PID_PARSER20_CTRL1 :: PARSER_ALL_PASS_CTRL_PRE_TSIO [02:02] */
-#define BCHP_XPT_FE_MINI_PID_PARSER20_CTRL1_PARSER_ALL_PASS_CTRL_PRE_TSIO_MASK 0x00000004
-#define BCHP_XPT_FE_MINI_PID_PARSER20_CTRL1_PARSER_ALL_PASS_CTRL_PRE_TSIO_SHIFT 2
-#define BCHP_XPT_FE_MINI_PID_PARSER20_CTRL1_PARSER_ALL_PASS_CTRL_PRE_TSIO_DEFAULT 0x00000000
-
-/* XPT_FE :: MINI_PID_PARSER20_CTRL1 :: PARSER_ALL_PASS_CTRL_PRE_MPOD [01:01] */
-#define BCHP_XPT_FE_MINI_PID_PARSER20_CTRL1_PARSER_ALL_PASS_CTRL_PRE_MPOD_MASK 0x00000002
-#define BCHP_XPT_FE_MINI_PID_PARSER20_CTRL1_PARSER_ALL_PASS_CTRL_PRE_MPOD_SHIFT 1
-#define BCHP_XPT_FE_MINI_PID_PARSER20_CTRL1_PARSER_ALL_PASS_CTRL_PRE_MPOD_DEFAULT 0x00000000
-
-/* XPT_FE :: MINI_PID_PARSER20_CTRL1 :: PARSER_ENABLE [00:00] */
-#define BCHP_XPT_FE_MINI_PID_PARSER20_CTRL1_PARSER_ENABLE_MASK 0x00000001
-#define BCHP_XPT_FE_MINI_PID_PARSER20_CTRL1_PARSER_ENABLE_SHIFT 0
-#define BCHP_XPT_FE_MINI_PID_PARSER20_CTRL1_PARSER_ENABLE_DEFAULT 0x00000000
-
-/***************************************************************************
- *MINI_PID_PARSER20_CTRL2 - Data Transport Parser Band 20 Control Register 2
- ***************************************************************************/
-/* XPT_FE :: MINI_PID_PARSER20_CTRL2 :: reserved0 [31:14] */
-#define BCHP_XPT_FE_MINI_PID_PARSER20_CTRL2_reserved0_MASK 0xffffc000
-#define BCHP_XPT_FE_MINI_PID_PARSER20_CTRL2_reserved0_SHIFT 14
-
-/* XPT_FE :: MINI_PID_PARSER20_CTRL2 :: PARSER_STREAM_TIMESTAMP_EN [13:13] */
-#define BCHP_XPT_FE_MINI_PID_PARSER20_CTRL2_PARSER_STREAM_TIMESTAMP_EN_MASK 0x00002000
-#define BCHP_XPT_FE_MINI_PID_PARSER20_CTRL2_PARSER_STREAM_TIMESTAMP_EN_SHIFT 13
-#define BCHP_XPT_FE_MINI_PID_PARSER20_CTRL2_PARSER_STREAM_TIMESTAMP_EN_DEFAULT 0x00000000
-
-/* XPT_FE :: MINI_PID_PARSER20_CTRL2 :: PARSER_TIMESTREAM_BF_SYNC [12:12] */
-#define BCHP_XPT_FE_MINI_PID_PARSER20_CTRL2_PARSER_TIMESTREAM_BF_SYNC_MASK 0x00001000
-#define BCHP_XPT_FE_MINI_PID_PARSER20_CTRL2_PARSER_TIMESTREAM_BF_SYNC_SHIFT 12
-#define BCHP_XPT_FE_MINI_PID_PARSER20_CTRL2_PARSER_TIMESTREAM_BF_SYNC_DEFAULT 0x00000000
-
-/* XPT_FE :: MINI_PID_PARSER20_CTRL2 :: reserved1 [11:11] */
-#define BCHP_XPT_FE_MINI_PID_PARSER20_CTRL2_reserved1_MASK 0x00000800
-#define BCHP_XPT_FE_MINI_PID_PARSER20_CTRL2_reserved1_SHIFT 11
-
-/* XPT_FE :: MINI_PID_PARSER20_CTRL2 :: PARSER_TIMESTAMP_RESTAMP [10:10] */
-#define BCHP_XPT_FE_MINI_PID_PARSER20_CTRL2_PARSER_TIMESTAMP_RESTAMP_MASK 0x00000400
-#define BCHP_XPT_FE_MINI_PID_PARSER20_CTRL2_PARSER_TIMESTAMP_RESTAMP_SHIFT 10
-#define BCHP_XPT_FE_MINI_PID_PARSER20_CTRL2_PARSER_TIMESTAMP_RESTAMP_DEFAULT 0x00000001
-
-/* XPT_FE :: MINI_PID_PARSER20_CTRL2 :: TSIO_MODE_SEL [09:09] */
-#define BCHP_XPT_FE_MINI_PID_PARSER20_CTRL2_TSIO_MODE_SEL_MASK 0x00000200
-#define BCHP_XPT_FE_MINI_PID_PARSER20_CTRL2_TSIO_MODE_SEL_SHIFT 9
-#define BCHP_XPT_FE_MINI_PID_PARSER20_CTRL2_TSIO_MODE_SEL_DEFAULT 0x00000001
-
-/* XPT_FE :: MINI_PID_PARSER20_CTRL2 :: reserved2 [08:07] */
-#define BCHP_XPT_FE_MINI_PID_PARSER20_CTRL2_reserved2_MASK 0x00000180
-#define BCHP_XPT_FE_MINI_PID_PARSER20_CTRL2_reserved2_SHIFT 7
-
-/* XPT_FE :: MINI_PID_PARSER20_CTRL2 :: TSIO_EN [06:06] */
-#define BCHP_XPT_FE_MINI_PID_PARSER20_CTRL2_TSIO_EN_MASK 0x00000040
-#define BCHP_XPT_FE_MINI_PID_PARSER20_CTRL2_TSIO_EN_SHIFT 6
-#define BCHP_XPT_FE_MINI_PID_PARSER20_CTRL2_TSIO_EN_DEFAULT 0x00000000
-
-/* XPT_FE :: MINI_PID_PARSER20_CTRL2 :: reserved3 [05:05] */
-#define BCHP_XPT_FE_MINI_PID_PARSER20_CTRL2_reserved3_MASK 0x00000020
-#define BCHP_XPT_FE_MINI_PID_PARSER20_CTRL2_reserved3_SHIFT 5
-
-/* XPT_FE :: MINI_PID_PARSER20_CTRL2 :: MPOD_MODE_SEL [04:04] */
-#define BCHP_XPT_FE_MINI_PID_PARSER20_CTRL2_MPOD_MODE_SEL_MASK 0x00000010
-#define BCHP_XPT_FE_MINI_PID_PARSER20_CTRL2_MPOD_MODE_SEL_SHIFT 4
-#define BCHP_XPT_FE_MINI_PID_PARSER20_CTRL2_MPOD_MODE_SEL_DEFAULT 0x00000000
-
-/* XPT_FE :: MINI_PID_PARSER20_CTRL2 :: reserved4 [03:03] */
-#define BCHP_XPT_FE_MINI_PID_PARSER20_CTRL2_reserved4_MASK 0x00000008
-#define BCHP_XPT_FE_MINI_PID_PARSER20_CTRL2_reserved4_SHIFT 3
-
-/* XPT_FE :: MINI_PID_PARSER20_CTRL2 :: PARSER_ACCEPT_NULL_PKT_POST_MPOD [02:02] */
-#define BCHP_XPT_FE_MINI_PID_PARSER20_CTRL2_PARSER_ACCEPT_NULL_PKT_POST_MPOD_MASK 0x00000004
-#define BCHP_XPT_FE_MINI_PID_PARSER20_CTRL2_PARSER_ACCEPT_NULL_PKT_POST_MPOD_SHIFT 2
-#define BCHP_XPT_FE_MINI_PID_PARSER20_CTRL2_PARSER_ACCEPT_NULL_PKT_POST_MPOD_DEFAULT 0x00000000
-
-/* XPT_FE :: MINI_PID_PARSER20_CTRL2 :: PARSER_ALL_PASS_CTRL_POST_MPOD [01:01] */
-#define BCHP_XPT_FE_MINI_PID_PARSER20_CTRL2_PARSER_ALL_PASS_CTRL_POST_MPOD_MASK 0x00000002
-#define BCHP_XPT_FE_MINI_PID_PARSER20_CTRL2_PARSER_ALL_PASS_CTRL_POST_MPOD_SHIFT 1
-#define BCHP_XPT_FE_MINI_PID_PARSER20_CTRL2_PARSER_ALL_PASS_CTRL_POST_MPOD_DEFAULT 0x00000000
-
-/* XPT_FE :: MINI_PID_PARSER20_CTRL2 :: MPOD_EN [00:00] */
-#define BCHP_XPT_FE_MINI_PID_PARSER20_CTRL2_MPOD_EN_MASK 0x00000001
-#define BCHP_XPT_FE_MINI_PID_PARSER20_CTRL2_MPOD_EN_SHIFT 0
-#define BCHP_XPT_FE_MINI_PID_PARSER20_CTRL2_MPOD_EN_DEFAULT 0x00000000
-
-/***************************************************************************
- *MINI_PID_PARSER20_ALL_PASS_CTRL - Data Transport Parser Band 20 Control Register
- ***************************************************************************/
-/* XPT_FE :: MINI_PID_PARSER20_ALL_PASS_CTRL :: reserved0 [31:13] */
-#define BCHP_XPT_FE_MINI_PID_PARSER20_ALL_PASS_CTRL_reserved0_MASK 0xffffe000
-#define BCHP_XPT_FE_MINI_PID_PARSER20_ALL_PASS_CTRL_reserved0_SHIFT 13
-
-/* XPT_FE :: MINI_PID_PARSER20_ALL_PASS_CTRL :: PIDP_DEBUG_MODE [12:12] */
-#define BCHP_XPT_FE_MINI_PID_PARSER20_ALL_PASS_CTRL_PIDP_DEBUG_MODE_MASK 0x00001000
-#define BCHP_XPT_FE_MINI_PID_PARSER20_ALL_PASS_CTRL_PIDP_DEBUG_MODE_SHIFT 12
-#define BCHP_XPT_FE_MINI_PID_PARSER20_ALL_PASS_CTRL_PIDP_DEBUG_MODE_DEFAULT 0x00000000
-
-/* XPT_FE :: MINI_PID_PARSER20_ALL_PASS_CTRL :: ALL_PASS_PID_CH_NUM [11:00] */
-#define BCHP_XPT_FE_MINI_PID_PARSER20_ALL_PASS_CTRL_ALL_PASS_PID_CH_NUM_MASK 0x00000fff
-#define BCHP_XPT_FE_MINI_PID_PARSER20_ALL_PASS_CTRL_ALL_PASS_PID_CH_NUM_SHIFT 0
-#define BCHP_XPT_FE_MINI_PID_PARSER20_ALL_PASS_CTRL_ALL_PASS_PID_CH_NUM_DEFAULT 0x00000014
-
-/***************************************************************************
- *MINI_PID_PARSER21_CTRL1 - Data Transport Parser Band 21 Control Register
- ***************************************************************************/
-/* XPT_FE :: MINI_PID_PARSER21_CTRL1 :: reserved0 [31:29] */
-#define BCHP_XPT_FE_MINI_PID_PARSER21_CTRL1_reserved0_MASK 0xe0000000
-#define BCHP_XPT_FE_MINI_PID_PARSER21_CTRL1_reserved0_SHIFT 29
-
-/* XPT_FE :: MINI_PID_PARSER21_CTRL1 :: PARSER_TIMESTAMP_MODE [28:27] */
-#define BCHP_XPT_FE_MINI_PID_PARSER21_CTRL1_PARSER_TIMESTAMP_MODE_MASK 0x18000000
-#define BCHP_XPT_FE_MINI_PID_PARSER21_CTRL1_PARSER_TIMESTAMP_MODE_SHIFT 27
-#define BCHP_XPT_FE_MINI_PID_PARSER21_CTRL1_PARSER_TIMESTAMP_MODE_DEFAULT 0x00000002
-
-/* XPT_FE :: MINI_PID_PARSER21_CTRL1 :: PARSER_TSMF_SEL [26:23] */
-#define BCHP_XPT_FE_MINI_PID_PARSER21_CTRL1_PARSER_TSMF_SEL_MASK 0x07800000
-#define BCHP_XPT_FE_MINI_PID_PARSER21_CTRL1_PARSER_TSMF_SEL_SHIFT 23
-#define BCHP_XPT_FE_MINI_PID_PARSER21_CTRL1_PARSER_TSMF_SEL_DEFAULT 0x00000000
-
-/* XPT_FE :: MINI_PID_PARSER21_CTRL1 :: PARSER_TSMF_EN [22:22] */
-#define BCHP_XPT_FE_MINI_PID_PARSER21_CTRL1_PARSER_TSMF_EN_MASK 0x00400000
-#define BCHP_XPT_FE_MINI_PID_PARSER21_CTRL1_PARSER_TSMF_EN_SHIFT 22
-#define BCHP_XPT_FE_MINI_PID_PARSER21_CTRL1_PARSER_TSMF_EN_DEFAULT 0x00000000
-
-/* XPT_FE :: MINI_PID_PARSER21_CTRL1 :: PARSER_INPUT_SEL_MSB [21:21] */
-#define BCHP_XPT_FE_MINI_PID_PARSER21_CTRL1_PARSER_INPUT_SEL_MSB_MASK 0x00200000
-#define BCHP_XPT_FE_MINI_PID_PARSER21_CTRL1_PARSER_INPUT_SEL_MSB_SHIFT 21
-#define BCHP_XPT_FE_MINI_PID_PARSER21_CTRL1_PARSER_INPUT_SEL_MSB_DEFAULT 0x00000000
-
-/* XPT_FE :: MINI_PID_PARSER21_CTRL1 :: PARSER_ERROR_INPUT_TEI_IGNORE [20:20] */
-#define BCHP_XPT_FE_MINI_PID_PARSER21_CTRL1_PARSER_ERROR_INPUT_TEI_IGNORE_MASK 0x00100000
-#define BCHP_XPT_FE_MINI_PID_PARSER21_CTRL1_PARSER_ERROR_INPUT_TEI_IGNORE_SHIFT 20
-#define BCHP_XPT_FE_MINI_PID_PARSER21_CTRL1_PARSER_ERROR_INPUT_TEI_IGNORE_DEFAULT 0x00000000
-
-/* XPT_FE :: MINI_PID_PARSER21_CTRL1 :: PARSER_PKT_LENGTH [19:12] */
-#define BCHP_XPT_FE_MINI_PID_PARSER21_CTRL1_PARSER_PKT_LENGTH_MASK 0x000ff000
-#define BCHP_XPT_FE_MINI_PID_PARSER21_CTRL1_PARSER_PKT_LENGTH_SHIFT 12
-#define BCHP_XPT_FE_MINI_PID_PARSER21_CTRL1_PARSER_PKT_LENGTH_DEFAULT 0x000000bc
-
-/* XPT_FE :: MINI_PID_PARSER21_CTRL1 :: PARSER_INPUT_SEL [11:08] */
-#define BCHP_XPT_FE_MINI_PID_PARSER21_CTRL1_PARSER_INPUT_SEL_MASK 0x00000f00
-#define BCHP_XPT_FE_MINI_PID_PARSER21_CTRL1_PARSER_INPUT_SEL_SHIFT 8
-#define BCHP_XPT_FE_MINI_PID_PARSER21_CTRL1_PARSER_INPUT_SEL_DEFAULT 0x00000000
-
-/* XPT_FE :: MINI_PID_PARSER21_CTRL1 :: reserved1 [07:07] */
-#define BCHP_XPT_FE_MINI_PID_PARSER21_CTRL1_reserved1_MASK 0x00000080
-#define BCHP_XPT_FE_MINI_PID_PARSER21_CTRL1_reserved1_SHIFT 7
-
-/* XPT_FE :: MINI_PID_PARSER21_CTRL1 :: PARSER_PACKET_TYPE [06:05] */
-#define BCHP_XPT_FE_MINI_PID_PARSER21_CTRL1_PARSER_PACKET_TYPE_MASK 0x00000060
-#define BCHP_XPT_FE_MINI_PID_PARSER21_CTRL1_PARSER_PACKET_TYPE_SHIFT 5
-#define BCHP_XPT_FE_MINI_PID_PARSER21_CTRL1_PARSER_PACKET_TYPE_DEFAULT 0x00000000
-
-/* XPT_FE :: MINI_PID_PARSER21_CTRL1 :: PARSER_ACCEPT_NULL_PKT_PRE_MPOD [04:04] */
-#define BCHP_XPT_FE_MINI_PID_PARSER21_CTRL1_PARSER_ACCEPT_NULL_PKT_PRE_MPOD_MASK 0x00000010
-#define BCHP_XPT_FE_MINI_PID_PARSER21_CTRL1_PARSER_ACCEPT_NULL_PKT_PRE_MPOD_SHIFT 4
-#define BCHP_XPT_FE_MINI_PID_PARSER21_CTRL1_PARSER_ACCEPT_NULL_PKT_PRE_MPOD_DEFAULT 0x00000000
-
-/* XPT_FE :: MINI_PID_PARSER21_CTRL1 :: PARSER_ACCEPT_NULL_PKT_PRE_TSIO [03:03] */
-#define BCHP_XPT_FE_MINI_PID_PARSER21_CTRL1_PARSER_ACCEPT_NULL_PKT_PRE_TSIO_MASK 0x00000008
-#define BCHP_XPT_FE_MINI_PID_PARSER21_CTRL1_PARSER_ACCEPT_NULL_PKT_PRE_TSIO_SHIFT 3
-#define BCHP_XPT_FE_MINI_PID_PARSER21_CTRL1_PARSER_ACCEPT_NULL_PKT_PRE_TSIO_DEFAULT 0x00000000
-
-/* XPT_FE :: MINI_PID_PARSER21_CTRL1 :: PARSER_ALL_PASS_CTRL_PRE_TSIO [02:02] */
-#define BCHP_XPT_FE_MINI_PID_PARSER21_CTRL1_PARSER_ALL_PASS_CTRL_PRE_TSIO_MASK 0x00000004
-#define BCHP_XPT_FE_MINI_PID_PARSER21_CTRL1_PARSER_ALL_PASS_CTRL_PRE_TSIO_SHIFT 2
-#define BCHP_XPT_FE_MINI_PID_PARSER21_CTRL1_PARSER_ALL_PASS_CTRL_PRE_TSIO_DEFAULT 0x00000000
-
-/* XPT_FE :: MINI_PID_PARSER21_CTRL1 :: PARSER_ALL_PASS_CTRL_PRE_MPOD [01:01] */
-#define BCHP_XPT_FE_MINI_PID_PARSER21_CTRL1_PARSER_ALL_PASS_CTRL_PRE_MPOD_MASK 0x00000002
-#define BCHP_XPT_FE_MINI_PID_PARSER21_CTRL1_PARSER_ALL_PASS_CTRL_PRE_MPOD_SHIFT 1
-#define BCHP_XPT_FE_MINI_PID_PARSER21_CTRL1_PARSER_ALL_PASS_CTRL_PRE_MPOD_DEFAULT 0x00000000
-
-/* XPT_FE :: MINI_PID_PARSER21_CTRL1 :: PARSER_ENABLE [00:00] */
-#define BCHP_XPT_FE_MINI_PID_PARSER21_CTRL1_PARSER_ENABLE_MASK 0x00000001
-#define BCHP_XPT_FE_MINI_PID_PARSER21_CTRL1_PARSER_ENABLE_SHIFT 0
-#define BCHP_XPT_FE_MINI_PID_PARSER21_CTRL1_PARSER_ENABLE_DEFAULT 0x00000000
-
-/***************************************************************************
- *MINI_PID_PARSER21_CTRL2 - Data Transport Parser Band 21 Control Register 2
- ***************************************************************************/
-/* XPT_FE :: MINI_PID_PARSER21_CTRL2 :: reserved0 [31:14] */
-#define BCHP_XPT_FE_MINI_PID_PARSER21_CTRL2_reserved0_MASK 0xffffc000
-#define BCHP_XPT_FE_MINI_PID_PARSER21_CTRL2_reserved0_SHIFT 14
-
-/* XPT_FE :: MINI_PID_PARSER21_CTRL2 :: PARSER_STREAM_TIMESTAMP_EN [13:13] */
-#define BCHP_XPT_FE_MINI_PID_PARSER21_CTRL2_PARSER_STREAM_TIMESTAMP_EN_MASK 0x00002000
-#define BCHP_XPT_FE_MINI_PID_PARSER21_CTRL2_PARSER_STREAM_TIMESTAMP_EN_SHIFT 13
-#define BCHP_XPT_FE_MINI_PID_PARSER21_CTRL2_PARSER_STREAM_TIMESTAMP_EN_DEFAULT 0x00000000
-
-/* XPT_FE :: MINI_PID_PARSER21_CTRL2 :: PARSER_TIMESTREAM_BF_SYNC [12:12] */
-#define BCHP_XPT_FE_MINI_PID_PARSER21_CTRL2_PARSER_TIMESTREAM_BF_SYNC_MASK 0x00001000
-#define BCHP_XPT_FE_MINI_PID_PARSER21_CTRL2_PARSER_TIMESTREAM_BF_SYNC_SHIFT 12
-#define BCHP_XPT_FE_MINI_PID_PARSER21_CTRL2_PARSER_TIMESTREAM_BF_SYNC_DEFAULT 0x00000000
-
-/* XPT_FE :: MINI_PID_PARSER21_CTRL2 :: reserved1 [11:11] */
-#define BCHP_XPT_FE_MINI_PID_PARSER21_CTRL2_reserved1_MASK 0x00000800
-#define BCHP_XPT_FE_MINI_PID_PARSER21_CTRL2_reserved1_SHIFT 11
-
-/* XPT_FE :: MINI_PID_PARSER21_CTRL2 :: PARSER_TIMESTAMP_RESTAMP [10:10] */
-#define BCHP_XPT_FE_MINI_PID_PARSER21_CTRL2_PARSER_TIMESTAMP_RESTAMP_MASK 0x00000400
-#define BCHP_XPT_FE_MINI_PID_PARSER21_CTRL2_PARSER_TIMESTAMP_RESTAMP_SHIFT 10
-#define BCHP_XPT_FE_MINI_PID_PARSER21_CTRL2_PARSER_TIMESTAMP_RESTAMP_DEFAULT 0x00000001
-
-/* XPT_FE :: MINI_PID_PARSER21_CTRL2 :: TSIO_MODE_SEL [09:09] */
-#define BCHP_XPT_FE_MINI_PID_PARSER21_CTRL2_TSIO_MODE_SEL_MASK 0x00000200
-#define BCHP_XPT_FE_MINI_PID_PARSER21_CTRL2_TSIO_MODE_SEL_SHIFT 9
-#define BCHP_XPT_FE_MINI_PID_PARSER21_CTRL2_TSIO_MODE_SEL_DEFAULT 0x00000001
-
-/* XPT_FE :: MINI_PID_PARSER21_CTRL2 :: reserved2 [08:07] */
-#define BCHP_XPT_FE_MINI_PID_PARSER21_CTRL2_reserved2_MASK 0x00000180
-#define BCHP_XPT_FE_MINI_PID_PARSER21_CTRL2_reserved2_SHIFT 7
-
-/* XPT_FE :: MINI_PID_PARSER21_CTRL2 :: TSIO_EN [06:06] */
-#define BCHP_XPT_FE_MINI_PID_PARSER21_CTRL2_TSIO_EN_MASK 0x00000040
-#define BCHP_XPT_FE_MINI_PID_PARSER21_CTRL2_TSIO_EN_SHIFT 6
-#define BCHP_XPT_FE_MINI_PID_PARSER21_CTRL2_TSIO_EN_DEFAULT 0x00000000
-
-/* XPT_FE :: MINI_PID_PARSER21_CTRL2 :: reserved3 [05:05] */
-#define BCHP_XPT_FE_MINI_PID_PARSER21_CTRL2_reserved3_MASK 0x00000020
-#define BCHP_XPT_FE_MINI_PID_PARSER21_CTRL2_reserved3_SHIFT 5
-
-/* XPT_FE :: MINI_PID_PARSER21_CTRL2 :: MPOD_MODE_SEL [04:04] */
-#define BCHP_XPT_FE_MINI_PID_PARSER21_CTRL2_MPOD_MODE_SEL_MASK 0x00000010
-#define BCHP_XPT_FE_MINI_PID_PARSER21_CTRL2_MPOD_MODE_SEL_SHIFT 4
-#define BCHP_XPT_FE_MINI_PID_PARSER21_CTRL2_MPOD_MODE_SEL_DEFAULT 0x00000000
-
-/* XPT_FE :: MINI_PID_PARSER21_CTRL2 :: reserved4 [03:03] */
-#define BCHP_XPT_FE_MINI_PID_PARSER21_CTRL2_reserved4_MASK 0x00000008
-#define BCHP_XPT_FE_MINI_PID_PARSER21_CTRL2_reserved4_SHIFT 3
-
-/* XPT_FE :: MINI_PID_PARSER21_CTRL2 :: PARSER_ACCEPT_NULL_PKT_POST_MPOD [02:02] */
-#define BCHP_XPT_FE_MINI_PID_PARSER21_CTRL2_PARSER_ACCEPT_NULL_PKT_POST_MPOD_MASK 0x00000004
-#define BCHP_XPT_FE_MINI_PID_PARSER21_CTRL2_PARSER_ACCEPT_NULL_PKT_POST_MPOD_SHIFT 2
-#define BCHP_XPT_FE_MINI_PID_PARSER21_CTRL2_PARSER_ACCEPT_NULL_PKT_POST_MPOD_DEFAULT 0x00000000
-
-/* XPT_FE :: MINI_PID_PARSER21_CTRL2 :: PARSER_ALL_PASS_CTRL_POST_MPOD [01:01] */
-#define BCHP_XPT_FE_MINI_PID_PARSER21_CTRL2_PARSER_ALL_PASS_CTRL_POST_MPOD_MASK 0x00000002
-#define BCHP_XPT_FE_MINI_PID_PARSER21_CTRL2_PARSER_ALL_PASS_CTRL_POST_MPOD_SHIFT 1
-#define BCHP_XPT_FE_MINI_PID_PARSER21_CTRL2_PARSER_ALL_PASS_CTRL_POST_MPOD_DEFAULT 0x00000000
-
-/* XPT_FE :: MINI_PID_PARSER21_CTRL2 :: MPOD_EN [00:00] */
-#define BCHP_XPT_FE_MINI_PID_PARSER21_CTRL2_MPOD_EN_MASK 0x00000001
-#define BCHP_XPT_FE_MINI_PID_PARSER21_CTRL2_MPOD_EN_SHIFT 0
-#define BCHP_XPT_FE_MINI_PID_PARSER21_CTRL2_MPOD_EN_DEFAULT 0x00000000
-
-/***************************************************************************
- *MINI_PID_PARSER21_ALL_PASS_CTRL - Data Transport Parser Band 21 Control Register
- ***************************************************************************/
-/* XPT_FE :: MINI_PID_PARSER21_ALL_PASS_CTRL :: reserved0 [31:13] */
-#define BCHP_XPT_FE_MINI_PID_PARSER21_ALL_PASS_CTRL_reserved0_MASK 0xffffe000
-#define BCHP_XPT_FE_MINI_PID_PARSER21_ALL_PASS_CTRL_reserved0_SHIFT 13
-
-/* XPT_FE :: MINI_PID_PARSER21_ALL_PASS_CTRL :: PIDP_DEBUG_MODE [12:12] */
-#define BCHP_XPT_FE_MINI_PID_PARSER21_ALL_PASS_CTRL_PIDP_DEBUG_MODE_MASK 0x00001000
-#define BCHP_XPT_FE_MINI_PID_PARSER21_ALL_PASS_CTRL_PIDP_DEBUG_MODE_SHIFT 12
-#define BCHP_XPT_FE_MINI_PID_PARSER21_ALL_PASS_CTRL_PIDP_DEBUG_MODE_DEFAULT 0x00000000
-
-/* XPT_FE :: MINI_PID_PARSER21_ALL_PASS_CTRL :: ALL_PASS_PID_CH_NUM [11:00] */
-#define BCHP_XPT_FE_MINI_PID_PARSER21_ALL_PASS_CTRL_ALL_PASS_PID_CH_NUM_MASK 0x00000fff
-#define BCHP_XPT_FE_MINI_PID_PARSER21_ALL_PASS_CTRL_ALL_PASS_PID_CH_NUM_SHIFT 0
-#define BCHP_XPT_FE_MINI_PID_PARSER21_ALL_PASS_CTRL_ALL_PASS_PID_CH_NUM_DEFAULT 0x00000015
-
-/***************************************************************************
- *MINI_PID_PARSER22_CTRL1 - Data Transport Parser Band 22 Control Register
- ***************************************************************************/
-/* XPT_FE :: MINI_PID_PARSER22_CTRL1 :: reserved0 [31:29] */
-#define BCHP_XPT_FE_MINI_PID_PARSER22_CTRL1_reserved0_MASK 0xe0000000
-#define BCHP_XPT_FE_MINI_PID_PARSER22_CTRL1_reserved0_SHIFT 29
-
-/* XPT_FE :: MINI_PID_PARSER22_CTRL1 :: PARSER_TIMESTAMP_MODE [28:27] */
-#define BCHP_XPT_FE_MINI_PID_PARSER22_CTRL1_PARSER_TIMESTAMP_MODE_MASK 0x18000000
-#define BCHP_XPT_FE_MINI_PID_PARSER22_CTRL1_PARSER_TIMESTAMP_MODE_SHIFT 27
-#define BCHP_XPT_FE_MINI_PID_PARSER22_CTRL1_PARSER_TIMESTAMP_MODE_DEFAULT 0x00000002
-
-/* XPT_FE :: MINI_PID_PARSER22_CTRL1 :: PARSER_TSMF_SEL [26:23] */
-#define BCHP_XPT_FE_MINI_PID_PARSER22_CTRL1_PARSER_TSMF_SEL_MASK 0x07800000
-#define BCHP_XPT_FE_MINI_PID_PARSER22_CTRL1_PARSER_TSMF_SEL_SHIFT 23
-#define BCHP_XPT_FE_MINI_PID_PARSER22_CTRL1_PARSER_TSMF_SEL_DEFAULT 0x00000000
-
-/* XPT_FE :: MINI_PID_PARSER22_CTRL1 :: PARSER_TSMF_EN [22:22] */
-#define BCHP_XPT_FE_MINI_PID_PARSER22_CTRL1_PARSER_TSMF_EN_MASK 0x00400000
-#define BCHP_XPT_FE_MINI_PID_PARSER22_CTRL1_PARSER_TSMF_EN_SHIFT 22
-#define BCHP_XPT_FE_MINI_PID_PARSER22_CTRL1_PARSER_TSMF_EN_DEFAULT 0x00000000
-
-/* XPT_FE :: MINI_PID_PARSER22_CTRL1 :: PARSER_INPUT_SEL_MSB [21:21] */
-#define BCHP_XPT_FE_MINI_PID_PARSER22_CTRL1_PARSER_INPUT_SEL_MSB_MASK 0x00200000
-#define BCHP_XPT_FE_MINI_PID_PARSER22_CTRL1_PARSER_INPUT_SEL_MSB_SHIFT 21
-#define BCHP_XPT_FE_MINI_PID_PARSER22_CTRL1_PARSER_INPUT_SEL_MSB_DEFAULT 0x00000000
-
-/* XPT_FE :: MINI_PID_PARSER22_CTRL1 :: PARSER_ERROR_INPUT_TEI_IGNORE [20:20] */
-#define BCHP_XPT_FE_MINI_PID_PARSER22_CTRL1_PARSER_ERROR_INPUT_TEI_IGNORE_MASK 0x00100000
-#define BCHP_XPT_FE_MINI_PID_PARSER22_CTRL1_PARSER_ERROR_INPUT_TEI_IGNORE_SHIFT 20
-#define BCHP_XPT_FE_MINI_PID_PARSER22_CTRL1_PARSER_ERROR_INPUT_TEI_IGNORE_DEFAULT 0x00000000
-
-/* XPT_FE :: MINI_PID_PARSER22_CTRL1 :: PARSER_PKT_LENGTH [19:12] */
-#define BCHP_XPT_FE_MINI_PID_PARSER22_CTRL1_PARSER_PKT_LENGTH_MASK 0x000ff000
-#define BCHP_XPT_FE_MINI_PID_PARSER22_CTRL1_PARSER_PKT_LENGTH_SHIFT 12
-#define BCHP_XPT_FE_MINI_PID_PARSER22_CTRL1_PARSER_PKT_LENGTH_DEFAULT 0x000000bc
-
-/* XPT_FE :: MINI_PID_PARSER22_CTRL1 :: PARSER_INPUT_SEL [11:08] */
-#define BCHP_XPT_FE_MINI_PID_PARSER22_CTRL1_PARSER_INPUT_SEL_MASK 0x00000f00
-#define BCHP_XPT_FE_MINI_PID_PARSER22_CTRL1_PARSER_INPUT_SEL_SHIFT 8
-#define BCHP_XPT_FE_MINI_PID_PARSER22_CTRL1_PARSER_INPUT_SEL_DEFAULT 0x00000000
-
-/* XPT_FE :: MINI_PID_PARSER22_CTRL1 :: reserved1 [07:07] */
-#define BCHP_XPT_FE_MINI_PID_PARSER22_CTRL1_reserved1_MASK 0x00000080
-#define BCHP_XPT_FE_MINI_PID_PARSER22_CTRL1_reserved1_SHIFT 7
-
-/* XPT_FE :: MINI_PID_PARSER22_CTRL1 :: PARSER_PACKET_TYPE [06:05] */
-#define BCHP_XPT_FE_MINI_PID_PARSER22_CTRL1_PARSER_PACKET_TYPE_MASK 0x00000060
-#define BCHP_XPT_FE_MINI_PID_PARSER22_CTRL1_PARSER_PACKET_TYPE_SHIFT 5
-#define BCHP_XPT_FE_MINI_PID_PARSER22_CTRL1_PARSER_PACKET_TYPE_DEFAULT 0x00000000
-
-/* XPT_FE :: MINI_PID_PARSER22_CTRL1 :: PARSER_ACCEPT_NULL_PKT_PRE_MPOD [04:04] */
-#define BCHP_XPT_FE_MINI_PID_PARSER22_CTRL1_PARSER_ACCEPT_NULL_PKT_PRE_MPOD_MASK 0x00000010
-#define BCHP_XPT_FE_MINI_PID_PARSER22_CTRL1_PARSER_ACCEPT_NULL_PKT_PRE_MPOD_SHIFT 4
-#define BCHP_XPT_FE_MINI_PID_PARSER22_CTRL1_PARSER_ACCEPT_NULL_PKT_PRE_MPOD_DEFAULT 0x00000000
-
-/* XPT_FE :: MINI_PID_PARSER22_CTRL1 :: PARSER_ACCEPT_NULL_PKT_PRE_TSIO [03:03] */
-#define BCHP_XPT_FE_MINI_PID_PARSER22_CTRL1_PARSER_ACCEPT_NULL_PKT_PRE_TSIO_MASK 0x00000008
-#define BCHP_XPT_FE_MINI_PID_PARSER22_CTRL1_PARSER_ACCEPT_NULL_PKT_PRE_TSIO_SHIFT 3
-#define BCHP_XPT_FE_MINI_PID_PARSER22_CTRL1_PARSER_ACCEPT_NULL_PKT_PRE_TSIO_DEFAULT 0x00000000
-
-/* XPT_FE :: MINI_PID_PARSER22_CTRL1 :: PARSER_ALL_PASS_CTRL_PRE_TSIO [02:02] */
-#define BCHP_XPT_FE_MINI_PID_PARSER22_CTRL1_PARSER_ALL_PASS_CTRL_PRE_TSIO_MASK 0x00000004
-#define BCHP_XPT_FE_MINI_PID_PARSER22_CTRL1_PARSER_ALL_PASS_CTRL_PRE_TSIO_SHIFT 2
-#define BCHP_XPT_FE_MINI_PID_PARSER22_CTRL1_PARSER_ALL_PASS_CTRL_PRE_TSIO_DEFAULT 0x00000000
-
-/* XPT_FE :: MINI_PID_PARSER22_CTRL1 :: PARSER_ALL_PASS_CTRL_PRE_MPOD [01:01] */
-#define BCHP_XPT_FE_MINI_PID_PARSER22_CTRL1_PARSER_ALL_PASS_CTRL_PRE_MPOD_MASK 0x00000002
-#define BCHP_XPT_FE_MINI_PID_PARSER22_CTRL1_PARSER_ALL_PASS_CTRL_PRE_MPOD_SHIFT 1
-#define BCHP_XPT_FE_MINI_PID_PARSER22_CTRL1_PARSER_ALL_PASS_CTRL_PRE_MPOD_DEFAULT 0x00000000
-
-/* XPT_FE :: MINI_PID_PARSER22_CTRL1 :: PARSER_ENABLE [00:00] */
-#define BCHP_XPT_FE_MINI_PID_PARSER22_CTRL1_PARSER_ENABLE_MASK 0x00000001
-#define BCHP_XPT_FE_MINI_PID_PARSER22_CTRL1_PARSER_ENABLE_SHIFT 0
-#define BCHP_XPT_FE_MINI_PID_PARSER22_CTRL1_PARSER_ENABLE_DEFAULT 0x00000000
-
-/***************************************************************************
- *MINI_PID_PARSER22_CTRL2 - Data Transport Parser Band 22 Control Register 2
- ***************************************************************************/
-/* XPT_FE :: MINI_PID_PARSER22_CTRL2 :: reserved0 [31:14] */
-#define BCHP_XPT_FE_MINI_PID_PARSER22_CTRL2_reserved0_MASK 0xffffc000
-#define BCHP_XPT_FE_MINI_PID_PARSER22_CTRL2_reserved0_SHIFT 14
-
-/* XPT_FE :: MINI_PID_PARSER22_CTRL2 :: PARSER_STREAM_TIMESTAMP_EN [13:13] */
-#define BCHP_XPT_FE_MINI_PID_PARSER22_CTRL2_PARSER_STREAM_TIMESTAMP_EN_MASK 0x00002000
-#define BCHP_XPT_FE_MINI_PID_PARSER22_CTRL2_PARSER_STREAM_TIMESTAMP_EN_SHIFT 13
-#define BCHP_XPT_FE_MINI_PID_PARSER22_CTRL2_PARSER_STREAM_TIMESTAMP_EN_DEFAULT 0x00000000
-
-/* XPT_FE :: MINI_PID_PARSER22_CTRL2 :: PARSER_TIMESTREAM_BF_SYNC [12:12] */
-#define BCHP_XPT_FE_MINI_PID_PARSER22_CTRL2_PARSER_TIMESTREAM_BF_SYNC_MASK 0x00001000
-#define BCHP_XPT_FE_MINI_PID_PARSER22_CTRL2_PARSER_TIMESTREAM_BF_SYNC_SHIFT 12
-#define BCHP_XPT_FE_MINI_PID_PARSER22_CTRL2_PARSER_TIMESTREAM_BF_SYNC_DEFAULT 0x00000000
-
-/* XPT_FE :: MINI_PID_PARSER22_CTRL2 :: reserved1 [11:11] */
-#define BCHP_XPT_FE_MINI_PID_PARSER22_CTRL2_reserved1_MASK 0x00000800
-#define BCHP_XPT_FE_MINI_PID_PARSER22_CTRL2_reserved1_SHIFT 11
-
-/* XPT_FE :: MINI_PID_PARSER22_CTRL2 :: PARSER_TIMESTAMP_RESTAMP [10:10] */
-#define BCHP_XPT_FE_MINI_PID_PARSER22_CTRL2_PARSER_TIMESTAMP_RESTAMP_MASK 0x00000400
-#define BCHP_XPT_FE_MINI_PID_PARSER22_CTRL2_PARSER_TIMESTAMP_RESTAMP_SHIFT 10
-#define BCHP_XPT_FE_MINI_PID_PARSER22_CTRL2_PARSER_TIMESTAMP_RESTAMP_DEFAULT 0x00000001
-
-/* XPT_FE :: MINI_PID_PARSER22_CTRL2 :: TSIO_MODE_SEL [09:09] */
-#define BCHP_XPT_FE_MINI_PID_PARSER22_CTRL2_TSIO_MODE_SEL_MASK 0x00000200
-#define BCHP_XPT_FE_MINI_PID_PARSER22_CTRL2_TSIO_MODE_SEL_SHIFT 9
-#define BCHP_XPT_FE_MINI_PID_PARSER22_CTRL2_TSIO_MODE_SEL_DEFAULT 0x00000001
-
-/* XPT_FE :: MINI_PID_PARSER22_CTRL2 :: reserved2 [08:07] */
-#define BCHP_XPT_FE_MINI_PID_PARSER22_CTRL2_reserved2_MASK 0x00000180
-#define BCHP_XPT_FE_MINI_PID_PARSER22_CTRL2_reserved2_SHIFT 7
-
-/* XPT_FE :: MINI_PID_PARSER22_CTRL2 :: TSIO_EN [06:06] */
-#define BCHP_XPT_FE_MINI_PID_PARSER22_CTRL2_TSIO_EN_MASK 0x00000040
-#define BCHP_XPT_FE_MINI_PID_PARSER22_CTRL2_TSIO_EN_SHIFT 6
-#define BCHP_XPT_FE_MINI_PID_PARSER22_CTRL2_TSIO_EN_DEFAULT 0x00000000
-
-/* XPT_FE :: MINI_PID_PARSER22_CTRL2 :: reserved3 [05:05] */
-#define BCHP_XPT_FE_MINI_PID_PARSER22_CTRL2_reserved3_MASK 0x00000020
-#define BCHP_XPT_FE_MINI_PID_PARSER22_CTRL2_reserved3_SHIFT 5
-
-/* XPT_FE :: MINI_PID_PARSER22_CTRL2 :: MPOD_MODE_SEL [04:04] */
-#define BCHP_XPT_FE_MINI_PID_PARSER22_CTRL2_MPOD_MODE_SEL_MASK 0x00000010
-#define BCHP_XPT_FE_MINI_PID_PARSER22_CTRL2_MPOD_MODE_SEL_SHIFT 4
-#define BCHP_XPT_FE_MINI_PID_PARSER22_CTRL2_MPOD_MODE_SEL_DEFAULT 0x00000000
-
-/* XPT_FE :: MINI_PID_PARSER22_CTRL2 :: reserved4 [03:03] */
-#define BCHP_XPT_FE_MINI_PID_PARSER22_CTRL2_reserved4_MASK 0x00000008
-#define BCHP_XPT_FE_MINI_PID_PARSER22_CTRL2_reserved4_SHIFT 3
-
-/* XPT_FE :: MINI_PID_PARSER22_CTRL2 :: PARSER_ACCEPT_NULL_PKT_POST_MPOD [02:02] */
-#define BCHP_XPT_FE_MINI_PID_PARSER22_CTRL2_PARSER_ACCEPT_NULL_PKT_POST_MPOD_MASK 0x00000004
-#define BCHP_XPT_FE_MINI_PID_PARSER22_CTRL2_PARSER_ACCEPT_NULL_PKT_POST_MPOD_SHIFT 2
-#define BCHP_XPT_FE_MINI_PID_PARSER22_CTRL2_PARSER_ACCEPT_NULL_PKT_POST_MPOD_DEFAULT 0x00000000
-
-/* XPT_FE :: MINI_PID_PARSER22_CTRL2 :: PARSER_ALL_PASS_CTRL_POST_MPOD [01:01] */
-#define BCHP_XPT_FE_MINI_PID_PARSER22_CTRL2_PARSER_ALL_PASS_CTRL_POST_MPOD_MASK 0x00000002
-#define BCHP_XPT_FE_MINI_PID_PARSER22_CTRL2_PARSER_ALL_PASS_CTRL_POST_MPOD_SHIFT 1
-#define BCHP_XPT_FE_MINI_PID_PARSER22_CTRL2_PARSER_ALL_PASS_CTRL_POST_MPOD_DEFAULT 0x00000000
-
-/* XPT_FE :: MINI_PID_PARSER22_CTRL2 :: MPOD_EN [00:00] */
-#define BCHP_XPT_FE_MINI_PID_PARSER22_CTRL2_MPOD_EN_MASK 0x00000001
-#define BCHP_XPT_FE_MINI_PID_PARSER22_CTRL2_MPOD_EN_SHIFT 0
-#define BCHP_XPT_FE_MINI_PID_PARSER22_CTRL2_MPOD_EN_DEFAULT 0x00000000
-
-/***************************************************************************
- *MINI_PID_PARSER22_ALL_PASS_CTRL - Data Transport Parser Band 22 Control Register
- ***************************************************************************/
-/* XPT_FE :: MINI_PID_PARSER22_ALL_PASS_CTRL :: reserved0 [31:13] */
-#define BCHP_XPT_FE_MINI_PID_PARSER22_ALL_PASS_CTRL_reserved0_MASK 0xffffe000
-#define BCHP_XPT_FE_MINI_PID_PARSER22_ALL_PASS_CTRL_reserved0_SHIFT 13
-
-/* XPT_FE :: MINI_PID_PARSER22_ALL_PASS_CTRL :: PIDP_DEBUG_MODE [12:12] */
-#define BCHP_XPT_FE_MINI_PID_PARSER22_ALL_PASS_CTRL_PIDP_DEBUG_MODE_MASK 0x00001000
-#define BCHP_XPT_FE_MINI_PID_PARSER22_ALL_PASS_CTRL_PIDP_DEBUG_MODE_SHIFT 12
-#define BCHP_XPT_FE_MINI_PID_PARSER22_ALL_PASS_CTRL_PIDP_DEBUG_MODE_DEFAULT 0x00000000
-
-/* XPT_FE :: MINI_PID_PARSER22_ALL_PASS_CTRL :: ALL_PASS_PID_CH_NUM [11:00] */
-#define BCHP_XPT_FE_MINI_PID_PARSER22_ALL_PASS_CTRL_ALL_PASS_PID_CH_NUM_MASK 0x00000fff
-#define BCHP_XPT_FE_MINI_PID_PARSER22_ALL_PASS_CTRL_ALL_PASS_PID_CH_NUM_SHIFT 0
-#define BCHP_XPT_FE_MINI_PID_PARSER22_ALL_PASS_CTRL_ALL_PASS_PID_CH_NUM_DEFAULT 0x00000016
-
-/***************************************************************************
- *MINI_PID_PARSER23_CTRL1 - Data Transport Parser Band 23 Control Register
- ***************************************************************************/
-/* XPT_FE :: MINI_PID_PARSER23_CTRL1 :: reserved0 [31:29] */
-#define BCHP_XPT_FE_MINI_PID_PARSER23_CTRL1_reserved0_MASK 0xe0000000
-#define BCHP_XPT_FE_MINI_PID_PARSER23_CTRL1_reserved0_SHIFT 29
-
-/* XPT_FE :: MINI_PID_PARSER23_CTRL1 :: PARSER_TIMESTAMP_MODE [28:27] */
-#define BCHP_XPT_FE_MINI_PID_PARSER23_CTRL1_PARSER_TIMESTAMP_MODE_MASK 0x18000000
-#define BCHP_XPT_FE_MINI_PID_PARSER23_CTRL1_PARSER_TIMESTAMP_MODE_SHIFT 27
-#define BCHP_XPT_FE_MINI_PID_PARSER23_CTRL1_PARSER_TIMESTAMP_MODE_DEFAULT 0x00000002
-
-/* XPT_FE :: MINI_PID_PARSER23_CTRL1 :: PARSER_TSMF_SEL [26:23] */
-#define BCHP_XPT_FE_MINI_PID_PARSER23_CTRL1_PARSER_TSMF_SEL_MASK 0x07800000
-#define BCHP_XPT_FE_MINI_PID_PARSER23_CTRL1_PARSER_TSMF_SEL_SHIFT 23
-#define BCHP_XPT_FE_MINI_PID_PARSER23_CTRL1_PARSER_TSMF_SEL_DEFAULT 0x00000000
-
-/* XPT_FE :: MINI_PID_PARSER23_CTRL1 :: PARSER_TSMF_EN [22:22] */
-#define BCHP_XPT_FE_MINI_PID_PARSER23_CTRL1_PARSER_TSMF_EN_MASK 0x00400000
-#define BCHP_XPT_FE_MINI_PID_PARSER23_CTRL1_PARSER_TSMF_EN_SHIFT 22
-#define BCHP_XPT_FE_MINI_PID_PARSER23_CTRL1_PARSER_TSMF_EN_DEFAULT 0x00000000
-
-/* XPT_FE :: MINI_PID_PARSER23_CTRL1 :: PARSER_INPUT_SEL_MSB [21:21] */
-#define BCHP_XPT_FE_MINI_PID_PARSER23_CTRL1_PARSER_INPUT_SEL_MSB_MASK 0x00200000
-#define BCHP_XPT_FE_MINI_PID_PARSER23_CTRL1_PARSER_INPUT_SEL_MSB_SHIFT 21
-#define BCHP_XPT_FE_MINI_PID_PARSER23_CTRL1_PARSER_INPUT_SEL_MSB_DEFAULT 0x00000000
-
-/* XPT_FE :: MINI_PID_PARSER23_CTRL1 :: PARSER_ERROR_INPUT_TEI_IGNORE [20:20] */
-#define BCHP_XPT_FE_MINI_PID_PARSER23_CTRL1_PARSER_ERROR_INPUT_TEI_IGNORE_MASK 0x00100000
-#define BCHP_XPT_FE_MINI_PID_PARSER23_CTRL1_PARSER_ERROR_INPUT_TEI_IGNORE_SHIFT 20
-#define BCHP_XPT_FE_MINI_PID_PARSER23_CTRL1_PARSER_ERROR_INPUT_TEI_IGNORE_DEFAULT 0x00000000
-
-/* XPT_FE :: MINI_PID_PARSER23_CTRL1 :: PARSER_PKT_LENGTH [19:12] */
-#define BCHP_XPT_FE_MINI_PID_PARSER23_CTRL1_PARSER_PKT_LENGTH_MASK 0x000ff000
-#define BCHP_XPT_FE_MINI_PID_PARSER23_CTRL1_PARSER_PKT_LENGTH_SHIFT 12
-#define BCHP_XPT_FE_MINI_PID_PARSER23_CTRL1_PARSER_PKT_LENGTH_DEFAULT 0x000000bc
-
-/* XPT_FE :: MINI_PID_PARSER23_CTRL1 :: PARSER_INPUT_SEL [11:08] */
-#define BCHP_XPT_FE_MINI_PID_PARSER23_CTRL1_PARSER_INPUT_SEL_MASK 0x00000f00
-#define BCHP_XPT_FE_MINI_PID_PARSER23_CTRL1_PARSER_INPUT_SEL_SHIFT 8
-#define BCHP_XPT_FE_MINI_PID_PARSER23_CTRL1_PARSER_INPUT_SEL_DEFAULT 0x00000000
-
-/* XPT_FE :: MINI_PID_PARSER23_CTRL1 :: reserved1 [07:07] */
-#define BCHP_XPT_FE_MINI_PID_PARSER23_CTRL1_reserved1_MASK 0x00000080
-#define BCHP_XPT_FE_MINI_PID_PARSER23_CTRL1_reserved1_SHIFT 7
-
-/* XPT_FE :: MINI_PID_PARSER23_CTRL1 :: PARSER_PACKET_TYPE [06:05] */
-#define BCHP_XPT_FE_MINI_PID_PARSER23_CTRL1_PARSER_PACKET_TYPE_MASK 0x00000060
-#define BCHP_XPT_FE_MINI_PID_PARSER23_CTRL1_PARSER_PACKET_TYPE_SHIFT 5
-#define BCHP_XPT_FE_MINI_PID_PARSER23_CTRL1_PARSER_PACKET_TYPE_DEFAULT 0x00000000
-
-/* XPT_FE :: MINI_PID_PARSER23_CTRL1 :: PARSER_ACCEPT_NULL_PKT_PRE_MPOD [04:04] */
-#define BCHP_XPT_FE_MINI_PID_PARSER23_CTRL1_PARSER_ACCEPT_NULL_PKT_PRE_MPOD_MASK 0x00000010
-#define BCHP_XPT_FE_MINI_PID_PARSER23_CTRL1_PARSER_ACCEPT_NULL_PKT_PRE_MPOD_SHIFT 4
-#define BCHP_XPT_FE_MINI_PID_PARSER23_CTRL1_PARSER_ACCEPT_NULL_PKT_PRE_MPOD_DEFAULT 0x00000000
-
-/* XPT_FE :: MINI_PID_PARSER23_CTRL1 :: PARSER_ACCEPT_NULL_PKT_PRE_TSIO [03:03] */
-#define BCHP_XPT_FE_MINI_PID_PARSER23_CTRL1_PARSER_ACCEPT_NULL_PKT_PRE_TSIO_MASK 0x00000008
-#define BCHP_XPT_FE_MINI_PID_PARSER23_CTRL1_PARSER_ACCEPT_NULL_PKT_PRE_TSIO_SHIFT 3
-#define BCHP_XPT_FE_MINI_PID_PARSER23_CTRL1_PARSER_ACCEPT_NULL_PKT_PRE_TSIO_DEFAULT 0x00000000
-
-/* XPT_FE :: MINI_PID_PARSER23_CTRL1 :: PARSER_ALL_PASS_CTRL_PRE_TSIO [02:02] */
-#define BCHP_XPT_FE_MINI_PID_PARSER23_CTRL1_PARSER_ALL_PASS_CTRL_PRE_TSIO_MASK 0x00000004
-#define BCHP_XPT_FE_MINI_PID_PARSER23_CTRL1_PARSER_ALL_PASS_CTRL_PRE_TSIO_SHIFT 2
-#define BCHP_XPT_FE_MINI_PID_PARSER23_CTRL1_PARSER_ALL_PASS_CTRL_PRE_TSIO_DEFAULT 0x00000000
-
-/* XPT_FE :: MINI_PID_PARSER23_CTRL1 :: PARSER_ALL_PASS_CTRL_PRE_MPOD [01:01] */
-#define BCHP_XPT_FE_MINI_PID_PARSER23_CTRL1_PARSER_ALL_PASS_CTRL_PRE_MPOD_MASK 0x00000002
-#define BCHP_XPT_FE_MINI_PID_PARSER23_CTRL1_PARSER_ALL_PASS_CTRL_PRE_MPOD_SHIFT 1
-#define BCHP_XPT_FE_MINI_PID_PARSER23_CTRL1_PARSER_ALL_PASS_CTRL_PRE_MPOD_DEFAULT 0x00000000
-
-/* XPT_FE :: MINI_PID_PARSER23_CTRL1 :: PARSER_ENABLE [00:00] */
-#define BCHP_XPT_FE_MINI_PID_PARSER23_CTRL1_PARSER_ENABLE_MASK 0x00000001
-#define BCHP_XPT_FE_MINI_PID_PARSER23_CTRL1_PARSER_ENABLE_SHIFT 0
-#define BCHP_XPT_FE_MINI_PID_PARSER23_CTRL1_PARSER_ENABLE_DEFAULT 0x00000000
-
-/***************************************************************************
- *MINI_PID_PARSER23_CTRL2 - Data Transport Parser Band 23 Control Register 2
- ***************************************************************************/
-/* XPT_FE :: MINI_PID_PARSER23_CTRL2 :: reserved0 [31:14] */
-#define BCHP_XPT_FE_MINI_PID_PARSER23_CTRL2_reserved0_MASK 0xffffc000
-#define BCHP_XPT_FE_MINI_PID_PARSER23_CTRL2_reserved0_SHIFT 14
-
-/* XPT_FE :: MINI_PID_PARSER23_CTRL2 :: PARSER_STREAM_TIMESTAMP_EN [13:13] */
-#define BCHP_XPT_FE_MINI_PID_PARSER23_CTRL2_PARSER_STREAM_TIMESTAMP_EN_MASK 0x00002000
-#define BCHP_XPT_FE_MINI_PID_PARSER23_CTRL2_PARSER_STREAM_TIMESTAMP_EN_SHIFT 13
-#define BCHP_XPT_FE_MINI_PID_PARSER23_CTRL2_PARSER_STREAM_TIMESTAMP_EN_DEFAULT 0x00000000
-
-/* XPT_FE :: MINI_PID_PARSER23_CTRL2 :: PARSER_TIMESTREAM_BF_SYNC [12:12] */
-#define BCHP_XPT_FE_MINI_PID_PARSER23_CTRL2_PARSER_TIMESTREAM_BF_SYNC_MASK 0x00001000
-#define BCHP_XPT_FE_MINI_PID_PARSER23_CTRL2_PARSER_TIMESTREAM_BF_SYNC_SHIFT 12
-#define BCHP_XPT_FE_MINI_PID_PARSER23_CTRL2_PARSER_TIMESTREAM_BF_SYNC_DEFAULT 0x00000000
-
-/* XPT_FE :: MINI_PID_PARSER23_CTRL2 :: reserved1 [11:11] */
-#define BCHP_XPT_FE_MINI_PID_PARSER23_CTRL2_reserved1_MASK 0x00000800
-#define BCHP_XPT_FE_MINI_PID_PARSER23_CTRL2_reserved1_SHIFT 11
-
-/* XPT_FE :: MINI_PID_PARSER23_CTRL2 :: PARSER_TIMESTAMP_RESTAMP [10:10] */
-#define BCHP_XPT_FE_MINI_PID_PARSER23_CTRL2_PARSER_TIMESTAMP_RESTAMP_MASK 0x00000400
-#define BCHP_XPT_FE_MINI_PID_PARSER23_CTRL2_PARSER_TIMESTAMP_RESTAMP_SHIFT 10
-#define BCHP_XPT_FE_MINI_PID_PARSER23_CTRL2_PARSER_TIMESTAMP_RESTAMP_DEFAULT 0x00000001
-
-/* XPT_FE :: MINI_PID_PARSER23_CTRL2 :: TSIO_MODE_SEL [09:09] */
-#define BCHP_XPT_FE_MINI_PID_PARSER23_CTRL2_TSIO_MODE_SEL_MASK 0x00000200
-#define BCHP_XPT_FE_MINI_PID_PARSER23_CTRL2_TSIO_MODE_SEL_SHIFT 9
-#define BCHP_XPT_FE_MINI_PID_PARSER23_CTRL2_TSIO_MODE_SEL_DEFAULT 0x00000001
-
-/* XPT_FE :: MINI_PID_PARSER23_CTRL2 :: reserved2 [08:07] */
-#define BCHP_XPT_FE_MINI_PID_PARSER23_CTRL2_reserved2_MASK 0x00000180
-#define BCHP_XPT_FE_MINI_PID_PARSER23_CTRL2_reserved2_SHIFT 7
-
-/* XPT_FE :: MINI_PID_PARSER23_CTRL2 :: TSIO_EN [06:06] */
-#define BCHP_XPT_FE_MINI_PID_PARSER23_CTRL2_TSIO_EN_MASK 0x00000040
-#define BCHP_XPT_FE_MINI_PID_PARSER23_CTRL2_TSIO_EN_SHIFT 6
-#define BCHP_XPT_FE_MINI_PID_PARSER23_CTRL2_TSIO_EN_DEFAULT 0x00000000
-
-/* XPT_FE :: MINI_PID_PARSER23_CTRL2 :: reserved3 [05:05] */
-#define BCHP_XPT_FE_MINI_PID_PARSER23_CTRL2_reserved3_MASK 0x00000020
-#define BCHP_XPT_FE_MINI_PID_PARSER23_CTRL2_reserved3_SHIFT 5
-
-/* XPT_FE :: MINI_PID_PARSER23_CTRL2 :: MPOD_MODE_SEL [04:04] */
-#define BCHP_XPT_FE_MINI_PID_PARSER23_CTRL2_MPOD_MODE_SEL_MASK 0x00000010
-#define BCHP_XPT_FE_MINI_PID_PARSER23_CTRL2_MPOD_MODE_SEL_SHIFT 4
-#define BCHP_XPT_FE_MINI_PID_PARSER23_CTRL2_MPOD_MODE_SEL_DEFAULT 0x00000000
-
-/* XPT_FE :: MINI_PID_PARSER23_CTRL2 :: reserved4 [03:03] */
-#define BCHP_XPT_FE_MINI_PID_PARSER23_CTRL2_reserved4_MASK 0x00000008
-#define BCHP_XPT_FE_MINI_PID_PARSER23_CTRL2_reserved4_SHIFT 3
-
-/* XPT_FE :: MINI_PID_PARSER23_CTRL2 :: PARSER_ACCEPT_NULL_PKT_POST_MPOD [02:02] */
-#define BCHP_XPT_FE_MINI_PID_PARSER23_CTRL2_PARSER_ACCEPT_NULL_PKT_POST_MPOD_MASK 0x00000004
-#define BCHP_XPT_FE_MINI_PID_PARSER23_CTRL2_PARSER_ACCEPT_NULL_PKT_POST_MPOD_SHIFT 2
-#define BCHP_XPT_FE_MINI_PID_PARSER23_CTRL2_PARSER_ACCEPT_NULL_PKT_POST_MPOD_DEFAULT 0x00000000
-
-/* XPT_FE :: MINI_PID_PARSER23_CTRL2 :: PARSER_ALL_PASS_CTRL_POST_MPOD [01:01] */
-#define BCHP_XPT_FE_MINI_PID_PARSER23_CTRL2_PARSER_ALL_PASS_CTRL_POST_MPOD_MASK 0x00000002
-#define BCHP_XPT_FE_MINI_PID_PARSER23_CTRL2_PARSER_ALL_PASS_CTRL_POST_MPOD_SHIFT 1
-#define BCHP_XPT_FE_MINI_PID_PARSER23_CTRL2_PARSER_ALL_PASS_CTRL_POST_MPOD_DEFAULT 0x00000000
-
-/* XPT_FE :: MINI_PID_PARSER23_CTRL2 :: MPOD_EN [00:00] */
-#define BCHP_XPT_FE_MINI_PID_PARSER23_CTRL2_MPOD_EN_MASK 0x00000001
-#define BCHP_XPT_FE_MINI_PID_PARSER23_CTRL2_MPOD_EN_SHIFT 0
-#define BCHP_XPT_FE_MINI_PID_PARSER23_CTRL2_MPOD_EN_DEFAULT 0x00000000
-
-/***************************************************************************
- *MINI_PID_PARSER23_ALL_PASS_CTRL - Data Transport Parser Band 23 Control Register
- ***************************************************************************/
-/* XPT_FE :: MINI_PID_PARSER23_ALL_PASS_CTRL :: reserved0 [31:13] */
-#define BCHP_XPT_FE_MINI_PID_PARSER23_ALL_PASS_CTRL_reserved0_MASK 0xffffe000
-#define BCHP_XPT_FE_MINI_PID_PARSER23_ALL_PASS_CTRL_reserved0_SHIFT 13
-
-/* XPT_FE :: MINI_PID_PARSER23_ALL_PASS_CTRL :: PIDP_DEBUG_MODE [12:12] */
-#define BCHP_XPT_FE_MINI_PID_PARSER23_ALL_PASS_CTRL_PIDP_DEBUG_MODE_MASK 0x00001000
-#define BCHP_XPT_FE_MINI_PID_PARSER23_ALL_PASS_CTRL_PIDP_DEBUG_MODE_SHIFT 12
-#define BCHP_XPT_FE_MINI_PID_PARSER23_ALL_PASS_CTRL_PIDP_DEBUG_MODE_DEFAULT 0x00000000
-
-/* XPT_FE :: MINI_PID_PARSER23_ALL_PASS_CTRL :: ALL_PASS_PID_CH_NUM [11:00] */
-#define BCHP_XPT_FE_MINI_PID_PARSER23_ALL_PASS_CTRL_ALL_PASS_PID_CH_NUM_MASK 0x00000fff
-#define BCHP_XPT_FE_MINI_PID_PARSER23_ALL_PASS_CTRL_ALL_PASS_PID_CH_NUM_SHIFT 0
-#define BCHP_XPT_FE_MINI_PID_PARSER23_ALL_PASS_CTRL_ALL_PASS_PID_CH_NUM_DEFAULT 0x00000017
-
-/***************************************************************************
- *MINI_PID_PARSER0_TO_PARSER3_BAND_ID - MINI PID PARSER0 to PARSER3 BAND ID
- ***************************************************************************/
-/* XPT_FE :: MINI_PID_PARSER0_TO_PARSER3_BAND_ID :: PARSER3_PARSER_SEL [31:31] */
-#define BCHP_XPT_FE_MINI_PID_PARSER0_TO_PARSER3_BAND_ID_PARSER3_PARSER_SEL_MASK 0x80000000
-#define BCHP_XPT_FE_MINI_PID_PARSER0_TO_PARSER3_BAND_ID_PARSER3_PARSER_SEL_SHIFT 31
-#define BCHP_XPT_FE_MINI_PID_PARSER0_TO_PARSER3_BAND_ID_PARSER3_PARSER_SEL_DEFAULT 0x00000000
-
-/* XPT_FE :: MINI_PID_PARSER0_TO_PARSER3_BAND_ID :: reserved0 [30:30] */
-#define BCHP_XPT_FE_MINI_PID_PARSER0_TO_PARSER3_BAND_ID_reserved0_MASK 0x40000000
-#define BCHP_XPT_FE_MINI_PID_PARSER0_TO_PARSER3_BAND_ID_reserved0_SHIFT 30
-
-/* XPT_FE :: MINI_PID_PARSER0_TO_PARSER3_BAND_ID :: PARSER3_BAND_ID [29:24] */
-#define BCHP_XPT_FE_MINI_PID_PARSER0_TO_PARSER3_BAND_ID_PARSER3_BAND_ID_MASK 0x3f000000
-#define BCHP_XPT_FE_MINI_PID_PARSER0_TO_PARSER3_BAND_ID_PARSER3_BAND_ID_SHIFT 24
-#define BCHP_XPT_FE_MINI_PID_PARSER0_TO_PARSER3_BAND_ID_PARSER3_BAND_ID_DEFAULT 0x00000003
-
-/* XPT_FE :: MINI_PID_PARSER0_TO_PARSER3_BAND_ID :: PARSER2_PARSER_SEL [23:23] */
-#define BCHP_XPT_FE_MINI_PID_PARSER0_TO_PARSER3_BAND_ID_PARSER2_PARSER_SEL_MASK 0x00800000
-#define BCHP_XPT_FE_MINI_PID_PARSER0_TO_PARSER3_BAND_ID_PARSER2_PARSER_SEL_SHIFT 23
-#define BCHP_XPT_FE_MINI_PID_PARSER0_TO_PARSER3_BAND_ID_PARSER2_PARSER_SEL_DEFAULT 0x00000000
-
-/* XPT_FE :: MINI_PID_PARSER0_TO_PARSER3_BAND_ID :: reserved1 [22:22] */
-#define BCHP_XPT_FE_MINI_PID_PARSER0_TO_PARSER3_BAND_ID_reserved1_MASK 0x00400000
-#define BCHP_XPT_FE_MINI_PID_PARSER0_TO_PARSER3_BAND_ID_reserved1_SHIFT 22
-
-/* XPT_FE :: MINI_PID_PARSER0_TO_PARSER3_BAND_ID :: PARSER2_BAND_ID [21:16] */
-#define BCHP_XPT_FE_MINI_PID_PARSER0_TO_PARSER3_BAND_ID_PARSER2_BAND_ID_MASK 0x003f0000
-#define BCHP_XPT_FE_MINI_PID_PARSER0_TO_PARSER3_BAND_ID_PARSER2_BAND_ID_SHIFT 16
-#define BCHP_XPT_FE_MINI_PID_PARSER0_TO_PARSER3_BAND_ID_PARSER2_BAND_ID_DEFAULT 0x00000002
-
-/* XPT_FE :: MINI_PID_PARSER0_TO_PARSER3_BAND_ID :: PARSER1_PARSER_SEL [15:15] */
-#define BCHP_XPT_FE_MINI_PID_PARSER0_TO_PARSER3_BAND_ID_PARSER1_PARSER_SEL_MASK 0x00008000
-#define BCHP_XPT_FE_MINI_PID_PARSER0_TO_PARSER3_BAND_ID_PARSER1_PARSER_SEL_SHIFT 15
-#define BCHP_XPT_FE_MINI_PID_PARSER0_TO_PARSER3_BAND_ID_PARSER1_PARSER_SEL_DEFAULT 0x00000000
-
-/* XPT_FE :: MINI_PID_PARSER0_TO_PARSER3_BAND_ID :: reserved2 [14:14] */
-#define BCHP_XPT_FE_MINI_PID_PARSER0_TO_PARSER3_BAND_ID_reserved2_MASK 0x00004000
-#define BCHP_XPT_FE_MINI_PID_PARSER0_TO_PARSER3_BAND_ID_reserved2_SHIFT 14
-
-/* XPT_FE :: MINI_PID_PARSER0_TO_PARSER3_BAND_ID :: PARSER1_BAND_ID [13:08] */
-#define BCHP_XPT_FE_MINI_PID_PARSER0_TO_PARSER3_BAND_ID_PARSER1_BAND_ID_MASK 0x00003f00
-#define BCHP_XPT_FE_MINI_PID_PARSER0_TO_PARSER3_BAND_ID_PARSER1_BAND_ID_SHIFT 8
-#define BCHP_XPT_FE_MINI_PID_PARSER0_TO_PARSER3_BAND_ID_PARSER1_BAND_ID_DEFAULT 0x00000001
-
-/* XPT_FE :: MINI_PID_PARSER0_TO_PARSER3_BAND_ID :: PARSER0_PARSER_SEL [07:07] */
-#define BCHP_XPT_FE_MINI_PID_PARSER0_TO_PARSER3_BAND_ID_PARSER0_PARSER_SEL_MASK 0x00000080
-#define BCHP_XPT_FE_MINI_PID_PARSER0_TO_PARSER3_BAND_ID_PARSER0_PARSER_SEL_SHIFT 7
-#define BCHP_XPT_FE_MINI_PID_PARSER0_TO_PARSER3_BAND_ID_PARSER0_PARSER_SEL_DEFAULT 0x00000000
-
-/* XPT_FE :: MINI_PID_PARSER0_TO_PARSER3_BAND_ID :: reserved3 [06:06] */
-#define BCHP_XPT_FE_MINI_PID_PARSER0_TO_PARSER3_BAND_ID_reserved3_MASK 0x00000040
-#define BCHP_XPT_FE_MINI_PID_PARSER0_TO_PARSER3_BAND_ID_reserved3_SHIFT 6
-
-/* XPT_FE :: MINI_PID_PARSER0_TO_PARSER3_BAND_ID :: PARSER0_BAND_ID [05:00] */
-#define BCHP_XPT_FE_MINI_PID_PARSER0_TO_PARSER3_BAND_ID_PARSER0_BAND_ID_MASK 0x0000003f
-#define BCHP_XPT_FE_MINI_PID_PARSER0_TO_PARSER3_BAND_ID_PARSER0_BAND_ID_SHIFT 0
-#define BCHP_XPT_FE_MINI_PID_PARSER0_TO_PARSER3_BAND_ID_PARSER0_BAND_ID_DEFAULT 0x00000000
-
-/***************************************************************************
- *MINI_PID_PARSER4_TO_PARSER7_BAND_ID - MINI PID PARSER4 to PARSER7 BAND ID
- ***************************************************************************/
-/* XPT_FE :: MINI_PID_PARSER4_TO_PARSER7_BAND_ID :: PARSER7_PARSER_SEL [31:31] */
-#define BCHP_XPT_FE_MINI_PID_PARSER4_TO_PARSER7_BAND_ID_PARSER7_PARSER_SEL_MASK 0x80000000
-#define BCHP_XPT_FE_MINI_PID_PARSER4_TO_PARSER7_BAND_ID_PARSER7_PARSER_SEL_SHIFT 31
-#define BCHP_XPT_FE_MINI_PID_PARSER4_TO_PARSER7_BAND_ID_PARSER7_PARSER_SEL_DEFAULT 0x00000000
-
-/* XPT_FE :: MINI_PID_PARSER4_TO_PARSER7_BAND_ID :: reserved0 [30:30] */
-#define BCHP_XPT_FE_MINI_PID_PARSER4_TO_PARSER7_BAND_ID_reserved0_MASK 0x40000000
-#define BCHP_XPT_FE_MINI_PID_PARSER4_TO_PARSER7_BAND_ID_reserved0_SHIFT 30
-
-/* XPT_FE :: MINI_PID_PARSER4_TO_PARSER7_BAND_ID :: PARSER7_BAND_ID [29:24] */
-#define BCHP_XPT_FE_MINI_PID_PARSER4_TO_PARSER7_BAND_ID_PARSER7_BAND_ID_MASK 0x3f000000
-#define BCHP_XPT_FE_MINI_PID_PARSER4_TO_PARSER7_BAND_ID_PARSER7_BAND_ID_SHIFT 24
-#define BCHP_XPT_FE_MINI_PID_PARSER4_TO_PARSER7_BAND_ID_PARSER7_BAND_ID_DEFAULT 0x00000007
-
-/* XPT_FE :: MINI_PID_PARSER4_TO_PARSER7_BAND_ID :: PARSER6_PARSER_SEL [23:23] */
-#define BCHP_XPT_FE_MINI_PID_PARSER4_TO_PARSER7_BAND_ID_PARSER6_PARSER_SEL_MASK 0x00800000
-#define BCHP_XPT_FE_MINI_PID_PARSER4_TO_PARSER7_BAND_ID_PARSER6_PARSER_SEL_SHIFT 23
-#define BCHP_XPT_FE_MINI_PID_PARSER4_TO_PARSER7_BAND_ID_PARSER6_PARSER_SEL_DEFAULT 0x00000000
-
-/* XPT_FE :: MINI_PID_PARSER4_TO_PARSER7_BAND_ID :: reserved1 [22:22] */
-#define BCHP_XPT_FE_MINI_PID_PARSER4_TO_PARSER7_BAND_ID_reserved1_MASK 0x00400000
-#define BCHP_XPT_FE_MINI_PID_PARSER4_TO_PARSER7_BAND_ID_reserved1_SHIFT 22
-
-/* XPT_FE :: MINI_PID_PARSER4_TO_PARSER7_BAND_ID :: PARSER6_BAND_ID [21:16] */
-#define BCHP_XPT_FE_MINI_PID_PARSER4_TO_PARSER7_BAND_ID_PARSER6_BAND_ID_MASK 0x003f0000
-#define BCHP_XPT_FE_MINI_PID_PARSER4_TO_PARSER7_BAND_ID_PARSER6_BAND_ID_SHIFT 16
-#define BCHP_XPT_FE_MINI_PID_PARSER4_TO_PARSER7_BAND_ID_PARSER6_BAND_ID_DEFAULT 0x00000006
-
-/* XPT_FE :: MINI_PID_PARSER4_TO_PARSER7_BAND_ID :: PARSER5_PARSER_SEL [15:15] */
-#define BCHP_XPT_FE_MINI_PID_PARSER4_TO_PARSER7_BAND_ID_PARSER5_PARSER_SEL_MASK 0x00008000
-#define BCHP_XPT_FE_MINI_PID_PARSER4_TO_PARSER7_BAND_ID_PARSER5_PARSER_SEL_SHIFT 15
-#define BCHP_XPT_FE_MINI_PID_PARSER4_TO_PARSER7_BAND_ID_PARSER5_PARSER_SEL_DEFAULT 0x00000000
-
-/* XPT_FE :: MINI_PID_PARSER4_TO_PARSER7_BAND_ID :: reserved2 [14:14] */
-#define BCHP_XPT_FE_MINI_PID_PARSER4_TO_PARSER7_BAND_ID_reserved2_MASK 0x00004000
-#define BCHP_XPT_FE_MINI_PID_PARSER4_TO_PARSER7_BAND_ID_reserved2_SHIFT 14
-
-/* XPT_FE :: MINI_PID_PARSER4_TO_PARSER7_BAND_ID :: PARSER5_BAND_ID [13:08] */
-#define BCHP_XPT_FE_MINI_PID_PARSER4_TO_PARSER7_BAND_ID_PARSER5_BAND_ID_MASK 0x00003f00
-#define BCHP_XPT_FE_MINI_PID_PARSER4_TO_PARSER7_BAND_ID_PARSER5_BAND_ID_SHIFT 8
-#define BCHP_XPT_FE_MINI_PID_PARSER4_TO_PARSER7_BAND_ID_PARSER5_BAND_ID_DEFAULT 0x00000005
-
-/* XPT_FE :: MINI_PID_PARSER4_TO_PARSER7_BAND_ID :: PARSER4_PARSER_SEL [07:07] */
-#define BCHP_XPT_FE_MINI_PID_PARSER4_TO_PARSER7_BAND_ID_PARSER4_PARSER_SEL_MASK 0x00000080
-#define BCHP_XPT_FE_MINI_PID_PARSER4_TO_PARSER7_BAND_ID_PARSER4_PARSER_SEL_SHIFT 7
-#define BCHP_XPT_FE_MINI_PID_PARSER4_TO_PARSER7_BAND_ID_PARSER4_PARSER_SEL_DEFAULT 0x00000000
-
-/* XPT_FE :: MINI_PID_PARSER4_TO_PARSER7_BAND_ID :: reserved3 [06:06] */
-#define BCHP_XPT_FE_MINI_PID_PARSER4_TO_PARSER7_BAND_ID_reserved3_MASK 0x00000040
-#define BCHP_XPT_FE_MINI_PID_PARSER4_TO_PARSER7_BAND_ID_reserved3_SHIFT 6
-
-/* XPT_FE :: MINI_PID_PARSER4_TO_PARSER7_BAND_ID :: PARSER4_BAND_ID [05:00] */
-#define BCHP_XPT_FE_MINI_PID_PARSER4_TO_PARSER7_BAND_ID_PARSER4_BAND_ID_MASK 0x0000003f
-#define BCHP_XPT_FE_MINI_PID_PARSER4_TO_PARSER7_BAND_ID_PARSER4_BAND_ID_SHIFT 0
-#define BCHP_XPT_FE_MINI_PID_PARSER4_TO_PARSER7_BAND_ID_PARSER4_BAND_ID_DEFAULT 0x00000004
-
-/***************************************************************************
- *MINI_PID_PARSER8_TO_PARSER11_BAND_ID - MINI PID PARSER8 to PARSER11 BAND ID
- ***************************************************************************/
-/* XPT_FE :: MINI_PID_PARSER8_TO_PARSER11_BAND_ID :: PARSER11_PARSER_SEL [31:31] */
-#define BCHP_XPT_FE_MINI_PID_PARSER8_TO_PARSER11_BAND_ID_PARSER11_PARSER_SEL_MASK 0x80000000
-#define BCHP_XPT_FE_MINI_PID_PARSER8_TO_PARSER11_BAND_ID_PARSER11_PARSER_SEL_SHIFT 31
-#define BCHP_XPT_FE_MINI_PID_PARSER8_TO_PARSER11_BAND_ID_PARSER11_PARSER_SEL_DEFAULT 0x00000000
-
-/* XPT_FE :: MINI_PID_PARSER8_TO_PARSER11_BAND_ID :: reserved0 [30:30] */
-#define BCHP_XPT_FE_MINI_PID_PARSER8_TO_PARSER11_BAND_ID_reserved0_MASK 0x40000000
-#define BCHP_XPT_FE_MINI_PID_PARSER8_TO_PARSER11_BAND_ID_reserved0_SHIFT 30
-
-/* XPT_FE :: MINI_PID_PARSER8_TO_PARSER11_BAND_ID :: PARSER11_BAND_ID [29:24] */
-#define BCHP_XPT_FE_MINI_PID_PARSER8_TO_PARSER11_BAND_ID_PARSER11_BAND_ID_MASK 0x3f000000
-#define BCHP_XPT_FE_MINI_PID_PARSER8_TO_PARSER11_BAND_ID_PARSER11_BAND_ID_SHIFT 24
-#define BCHP_XPT_FE_MINI_PID_PARSER8_TO_PARSER11_BAND_ID_PARSER11_BAND_ID_DEFAULT 0x0000000b
-
-/* XPT_FE :: MINI_PID_PARSER8_TO_PARSER11_BAND_ID :: PARSER10_PARSER_SEL [23:23] */
-#define BCHP_XPT_FE_MINI_PID_PARSER8_TO_PARSER11_BAND_ID_PARSER10_PARSER_SEL_MASK 0x00800000
-#define BCHP_XPT_FE_MINI_PID_PARSER8_TO_PARSER11_BAND_ID_PARSER10_PARSER_SEL_SHIFT 23
-#define BCHP_XPT_FE_MINI_PID_PARSER8_TO_PARSER11_BAND_ID_PARSER10_PARSER_SEL_DEFAULT 0x00000000
-
-/* XPT_FE :: MINI_PID_PARSER8_TO_PARSER11_BAND_ID :: reserved1 [22:22] */
-#define BCHP_XPT_FE_MINI_PID_PARSER8_TO_PARSER11_BAND_ID_reserved1_MASK 0x00400000
-#define BCHP_XPT_FE_MINI_PID_PARSER8_TO_PARSER11_BAND_ID_reserved1_SHIFT 22
-
-/* XPT_FE :: MINI_PID_PARSER8_TO_PARSER11_BAND_ID :: PARSER10_BAND_ID [21:16] */
-#define BCHP_XPT_FE_MINI_PID_PARSER8_TO_PARSER11_BAND_ID_PARSER10_BAND_ID_MASK 0x003f0000
-#define BCHP_XPT_FE_MINI_PID_PARSER8_TO_PARSER11_BAND_ID_PARSER10_BAND_ID_SHIFT 16
-#define BCHP_XPT_FE_MINI_PID_PARSER8_TO_PARSER11_BAND_ID_PARSER10_BAND_ID_DEFAULT 0x0000000a
-
-/* XPT_FE :: MINI_PID_PARSER8_TO_PARSER11_BAND_ID :: PARSER9_PARSER_SEL [15:15] */
-#define BCHP_XPT_FE_MINI_PID_PARSER8_TO_PARSER11_BAND_ID_PARSER9_PARSER_SEL_MASK 0x00008000
-#define BCHP_XPT_FE_MINI_PID_PARSER8_TO_PARSER11_BAND_ID_PARSER9_PARSER_SEL_SHIFT 15
-#define BCHP_XPT_FE_MINI_PID_PARSER8_TO_PARSER11_BAND_ID_PARSER9_PARSER_SEL_DEFAULT 0x00000000
-
-/* XPT_FE :: MINI_PID_PARSER8_TO_PARSER11_BAND_ID :: reserved2 [14:14] */
-#define BCHP_XPT_FE_MINI_PID_PARSER8_TO_PARSER11_BAND_ID_reserved2_MASK 0x00004000
-#define BCHP_XPT_FE_MINI_PID_PARSER8_TO_PARSER11_BAND_ID_reserved2_SHIFT 14
-
-/* XPT_FE :: MINI_PID_PARSER8_TO_PARSER11_BAND_ID :: PARSER9_BAND_ID [13:08] */
-#define BCHP_XPT_FE_MINI_PID_PARSER8_TO_PARSER11_BAND_ID_PARSER9_BAND_ID_MASK 0x00003f00
-#define BCHP_XPT_FE_MINI_PID_PARSER8_TO_PARSER11_BAND_ID_PARSER9_BAND_ID_SHIFT 8
-#define BCHP_XPT_FE_MINI_PID_PARSER8_TO_PARSER11_BAND_ID_PARSER9_BAND_ID_DEFAULT 0x00000009
-
-/* XPT_FE :: MINI_PID_PARSER8_TO_PARSER11_BAND_ID :: PARSER8_PARSER_SEL [07:07] */
-#define BCHP_XPT_FE_MINI_PID_PARSER8_TO_PARSER11_BAND_ID_PARSER8_PARSER_SEL_MASK 0x00000080
-#define BCHP_XPT_FE_MINI_PID_PARSER8_TO_PARSER11_BAND_ID_PARSER8_PARSER_SEL_SHIFT 7
-#define BCHP_XPT_FE_MINI_PID_PARSER8_TO_PARSER11_BAND_ID_PARSER8_PARSER_SEL_DEFAULT 0x00000000
-
-/* XPT_FE :: MINI_PID_PARSER8_TO_PARSER11_BAND_ID :: reserved3 [06:06] */
-#define BCHP_XPT_FE_MINI_PID_PARSER8_TO_PARSER11_BAND_ID_reserved3_MASK 0x00000040
-#define BCHP_XPT_FE_MINI_PID_PARSER8_TO_PARSER11_BAND_ID_reserved3_SHIFT 6
-
-/* XPT_FE :: MINI_PID_PARSER8_TO_PARSER11_BAND_ID :: PARSER8_BAND_ID [05:00] */
-#define BCHP_XPT_FE_MINI_PID_PARSER8_TO_PARSER11_BAND_ID_PARSER8_BAND_ID_MASK 0x0000003f
-#define BCHP_XPT_FE_MINI_PID_PARSER8_TO_PARSER11_BAND_ID_PARSER8_BAND_ID_SHIFT 0
-#define BCHP_XPT_FE_MINI_PID_PARSER8_TO_PARSER11_BAND_ID_PARSER8_BAND_ID_DEFAULT 0x00000008
-
-/***************************************************************************
- *MINI_PID_PARSER12_TO_PARSER15_BAND_ID - MINI PID PARSER12 to PARSER15 BAND ID
- ***************************************************************************/
-/* XPT_FE :: MINI_PID_PARSER12_TO_PARSER15_BAND_ID :: PARSER15_PARSER_SEL [31:31] */
-#define BCHP_XPT_FE_MINI_PID_PARSER12_TO_PARSER15_BAND_ID_PARSER15_PARSER_SEL_MASK 0x80000000
-#define BCHP_XPT_FE_MINI_PID_PARSER12_TO_PARSER15_BAND_ID_PARSER15_PARSER_SEL_SHIFT 31
-#define BCHP_XPT_FE_MINI_PID_PARSER12_TO_PARSER15_BAND_ID_PARSER15_PARSER_SEL_DEFAULT 0x00000000
-
-/* XPT_FE :: MINI_PID_PARSER12_TO_PARSER15_BAND_ID :: reserved0 [30:30] */
-#define BCHP_XPT_FE_MINI_PID_PARSER12_TO_PARSER15_BAND_ID_reserved0_MASK 0x40000000
-#define BCHP_XPT_FE_MINI_PID_PARSER12_TO_PARSER15_BAND_ID_reserved0_SHIFT 30
-
-/* XPT_FE :: MINI_PID_PARSER12_TO_PARSER15_BAND_ID :: PARSER15_BAND_ID [29:24] */
-#define BCHP_XPT_FE_MINI_PID_PARSER12_TO_PARSER15_BAND_ID_PARSER15_BAND_ID_MASK 0x3f000000
-#define BCHP_XPT_FE_MINI_PID_PARSER12_TO_PARSER15_BAND_ID_PARSER15_BAND_ID_SHIFT 24
-#define BCHP_XPT_FE_MINI_PID_PARSER12_TO_PARSER15_BAND_ID_PARSER15_BAND_ID_DEFAULT 0x0000000f
-
-/* XPT_FE :: MINI_PID_PARSER12_TO_PARSER15_BAND_ID :: PARSER14_PARSER_SEL [23:23] */
-#define BCHP_XPT_FE_MINI_PID_PARSER12_TO_PARSER15_BAND_ID_PARSER14_PARSER_SEL_MASK 0x00800000
-#define BCHP_XPT_FE_MINI_PID_PARSER12_TO_PARSER15_BAND_ID_PARSER14_PARSER_SEL_SHIFT 23
-#define BCHP_XPT_FE_MINI_PID_PARSER12_TO_PARSER15_BAND_ID_PARSER14_PARSER_SEL_DEFAULT 0x00000000
-
-/* XPT_FE :: MINI_PID_PARSER12_TO_PARSER15_BAND_ID :: reserved1 [22:22] */
-#define BCHP_XPT_FE_MINI_PID_PARSER12_TO_PARSER15_BAND_ID_reserved1_MASK 0x00400000
-#define BCHP_XPT_FE_MINI_PID_PARSER12_TO_PARSER15_BAND_ID_reserved1_SHIFT 22
-
-/* XPT_FE :: MINI_PID_PARSER12_TO_PARSER15_BAND_ID :: PARSER14_BAND_ID [21:16] */
-#define BCHP_XPT_FE_MINI_PID_PARSER12_TO_PARSER15_BAND_ID_PARSER14_BAND_ID_MASK 0x003f0000
-#define BCHP_XPT_FE_MINI_PID_PARSER12_TO_PARSER15_BAND_ID_PARSER14_BAND_ID_SHIFT 16
-#define BCHP_XPT_FE_MINI_PID_PARSER12_TO_PARSER15_BAND_ID_PARSER14_BAND_ID_DEFAULT 0x0000000e
-
-/* XPT_FE :: MINI_PID_PARSER12_TO_PARSER15_BAND_ID :: PARSER13_PARSER_SEL [15:15] */
-#define BCHP_XPT_FE_MINI_PID_PARSER12_TO_PARSER15_BAND_ID_PARSER13_PARSER_SEL_MASK 0x00008000
-#define BCHP_XPT_FE_MINI_PID_PARSER12_TO_PARSER15_BAND_ID_PARSER13_PARSER_SEL_SHIFT 15
-#define BCHP_XPT_FE_MINI_PID_PARSER12_TO_PARSER15_BAND_ID_PARSER13_PARSER_SEL_DEFAULT 0x00000000
-
-/* XPT_FE :: MINI_PID_PARSER12_TO_PARSER15_BAND_ID :: reserved2 [14:14] */
-#define BCHP_XPT_FE_MINI_PID_PARSER12_TO_PARSER15_BAND_ID_reserved2_MASK 0x00004000
-#define BCHP_XPT_FE_MINI_PID_PARSER12_TO_PARSER15_BAND_ID_reserved2_SHIFT 14
-
-/* XPT_FE :: MINI_PID_PARSER12_TO_PARSER15_BAND_ID :: PARSER13_BAND_ID [13:08] */
-#define BCHP_XPT_FE_MINI_PID_PARSER12_TO_PARSER15_BAND_ID_PARSER13_BAND_ID_MASK 0x00003f00
-#define BCHP_XPT_FE_MINI_PID_PARSER12_TO_PARSER15_BAND_ID_PARSER13_BAND_ID_SHIFT 8
-#define BCHP_XPT_FE_MINI_PID_PARSER12_TO_PARSER15_BAND_ID_PARSER13_BAND_ID_DEFAULT 0x0000000d
-
-/* XPT_FE :: MINI_PID_PARSER12_TO_PARSER15_BAND_ID :: PARSER12_PARSER_SEL [07:07] */
-#define BCHP_XPT_FE_MINI_PID_PARSER12_TO_PARSER15_BAND_ID_PARSER12_PARSER_SEL_MASK 0x00000080
-#define BCHP_XPT_FE_MINI_PID_PARSER12_TO_PARSER15_BAND_ID_PARSER12_PARSER_SEL_SHIFT 7
-#define BCHP_XPT_FE_MINI_PID_PARSER12_TO_PARSER15_BAND_ID_PARSER12_PARSER_SEL_DEFAULT 0x00000000
-
-/* XPT_FE :: MINI_PID_PARSER12_TO_PARSER15_BAND_ID :: reserved3 [06:06] */
-#define BCHP_XPT_FE_MINI_PID_PARSER12_TO_PARSER15_BAND_ID_reserved3_MASK 0x00000040
-#define BCHP_XPT_FE_MINI_PID_PARSER12_TO_PARSER15_BAND_ID_reserved3_SHIFT 6
-
-/* XPT_FE :: MINI_PID_PARSER12_TO_PARSER15_BAND_ID :: PARSER12_BAND_ID [05:00] */
-#define BCHP_XPT_FE_MINI_PID_PARSER12_TO_PARSER15_BAND_ID_PARSER12_BAND_ID_MASK 0x0000003f
-#define BCHP_XPT_FE_MINI_PID_PARSER12_TO_PARSER15_BAND_ID_PARSER12_BAND_ID_SHIFT 0
-#define BCHP_XPT_FE_MINI_PID_PARSER12_TO_PARSER15_BAND_ID_PARSER12_BAND_ID_DEFAULT 0x0000000c
-
-/***************************************************************************
- *TSMF0_CTRL - Data Transport TSMF Demultiplexer -- Control Register
- ***************************************************************************/
-/* XPT_FE :: TSMF0_CTRL :: reserved0 [31:28] */
-#define BCHP_XPT_FE_TSMF0_CTRL_reserved0_MASK 0xf0000000
-#define BCHP_XPT_FE_TSMF0_CTRL_reserved0_SHIFT 28
-
-/* XPT_FE :: TSMF0_CTRL :: TSMF_INPUT_SEL_MSB [27:27] */
-#define BCHP_XPT_FE_TSMF0_CTRL_TSMF_INPUT_SEL_MSB_MASK 0x08000000
-#define BCHP_XPT_FE_TSMF0_CTRL_TSMF_INPUT_SEL_MSB_SHIFT 27
-#define BCHP_XPT_FE_TSMF0_CTRL_TSMF_INPUT_SEL_MSB_DEFAULT 0x00000000
-
-/* XPT_FE :: TSMF0_CTRL :: TSMF_CRC_CK_DIS [26:26] */
-#define BCHP_XPT_FE_TSMF0_CTRL_TSMF_CRC_CK_DIS_MASK 0x04000000
-#define BCHP_XPT_FE_TSMF0_CTRL_TSMF_CRC_CK_DIS_SHIFT 26
-#define BCHP_XPT_FE_TSMF0_CTRL_TSMF_CRC_CK_DIS_DEFAULT 0x00000000
-
-/* XPT_FE :: TSMF0_CTRL :: TSMF_REL_TS_STATUS_CK_DIS [25:25] */
-#define BCHP_XPT_FE_TSMF0_CTRL_TSMF_REL_TS_STATUS_CK_DIS_MASK 0x02000000
-#define BCHP_XPT_FE_TSMF0_CTRL_TSMF_REL_TS_STATUS_CK_DIS_SHIFT 25
-#define BCHP_XPT_FE_TSMF0_CTRL_TSMF_REL_TS_STATUS_CK_DIS_DEFAULT 0x00000000
-
-/* XPT_FE :: TSMF0_CTRL :: TSMF_FRAME_TYPE_CK_DIS [24:24] */
-#define BCHP_XPT_FE_TSMF0_CTRL_TSMF_FRAME_TYPE_CK_DIS_MASK 0x01000000
-#define BCHP_XPT_FE_TSMF0_CTRL_TSMF_FRAME_TYPE_CK_DIS_SHIFT 24
-#define BCHP_XPT_FE_TSMF0_CTRL_TSMF_FRAME_TYPE_CK_DIS_DEFAULT 0x00000000
-
-/* XPT_FE :: TSMF0_CTRL :: TSMF_REL_TS_MODE_CK_DIS [23:23] */
-#define BCHP_XPT_FE_TSMF0_CTRL_TSMF_REL_TS_MODE_CK_DIS_MASK 0x00800000
-#define BCHP_XPT_FE_TSMF0_CTRL_TSMF_REL_TS_MODE_CK_DIS_SHIFT 23
-#define BCHP_XPT_FE_TSMF0_CTRL_TSMF_REL_TS_MODE_CK_DIS_DEFAULT 0x00000000
-
-/* XPT_FE :: TSMF0_CTRL :: TSMF_SYNC_CK_DIS [22:22] */
-#define BCHP_XPT_FE_TSMF0_CTRL_TSMF_SYNC_CK_DIS_MASK 0x00400000
-#define BCHP_XPT_FE_TSMF0_CTRL_TSMF_SYNC_CK_DIS_SHIFT 22
-#define BCHP_XPT_FE_TSMF0_CTRL_TSMF_SYNC_CK_DIS_DEFAULT 0x00000000
-
-/* XPT_FE :: TSMF0_CTRL :: TSMF_CC_CK_DIS [21:21] */
-#define BCHP_XPT_FE_TSMF0_CTRL_TSMF_CC_CK_DIS_MASK 0x00200000
-#define BCHP_XPT_FE_TSMF0_CTRL_TSMF_CC_CK_DIS_SHIFT 21
-#define BCHP_XPT_FE_TSMF0_CTRL_TSMF_CC_CK_DIS_DEFAULT 0x00000000
-
-/* XPT_FE :: TSMF0_CTRL :: TSMF_ADAP_CK_DIS [20:20] */
-#define BCHP_XPT_FE_TSMF0_CTRL_TSMF_ADAP_CK_DIS_MASK 0x00100000
-#define BCHP_XPT_FE_TSMF0_CTRL_TSMF_ADAP_CK_DIS_SHIFT 20
-#define BCHP_XPT_FE_TSMF0_CTRL_TSMF_ADAP_CK_DIS_DEFAULT 0x00000000
-
-/* XPT_FE :: TSMF0_CTRL :: TSMF_SC_CK_DIS [19:19] */
-#define BCHP_XPT_FE_TSMF0_CTRL_TSMF_SC_CK_DIS_MASK 0x00080000
-#define BCHP_XPT_FE_TSMF0_CTRL_TSMF_SC_CK_DIS_SHIFT 19
-#define BCHP_XPT_FE_TSMF0_CTRL_TSMF_SC_CK_DIS_DEFAULT 0x00000000
-
-/* XPT_FE :: TSMF0_CTRL :: TSMF_TS_PRIOR_CK_DIS [18:18] */
-#define BCHP_XPT_FE_TSMF0_CTRL_TSMF_TS_PRIOR_CK_DIS_MASK 0x00040000
-#define BCHP_XPT_FE_TSMF0_CTRL_TSMF_TS_PRIOR_CK_DIS_SHIFT 18
-#define BCHP_XPT_FE_TSMF0_CTRL_TSMF_TS_PRIOR_CK_DIS_DEFAULT 0x00000000
-
-/* XPT_FE :: TSMF0_CTRL :: TSMF_PUSI_CK_DIS [17:17] */
-#define BCHP_XPT_FE_TSMF0_CTRL_TSMF_PUSI_CK_DIS_MASK 0x00020000
-#define BCHP_XPT_FE_TSMF0_CTRL_TSMF_PUSI_CK_DIS_SHIFT 17
-#define BCHP_XPT_FE_TSMF0_CTRL_TSMF_PUSI_CK_DIS_DEFAULT 0x00000000
-
-/* XPT_FE :: TSMF0_CTRL :: TSMF_TEI_CK_DIS [16:16] */
-#define BCHP_XPT_FE_TSMF0_CTRL_TSMF_TEI_CK_DIS_MASK 0x00010000
-#define BCHP_XPT_FE_TSMF0_CTRL_TSMF_TEI_CK_DIS_SHIFT 16
-#define BCHP_XPT_FE_TSMF0_CTRL_TSMF_TEI_CK_DIS_DEFAULT 0x00000000
-
-/* XPT_FE :: TSMF0_CTRL :: TSMF_REL_TS_NO [15:12] */
-#define BCHP_XPT_FE_TSMF0_CTRL_TSMF_REL_TS_NO_MASK 0x0000f000
-#define BCHP_XPT_FE_TSMF0_CTRL_TSMF_REL_TS_NO_SHIFT 12
-#define BCHP_XPT_FE_TSMF0_CTRL_TSMF_REL_TS_NO_DEFAULT 0x00000000
-
-/* XPT_FE :: TSMF0_CTRL :: TSMF_INPUT_SEL [11:08] */
-#define BCHP_XPT_FE_TSMF0_CTRL_TSMF_INPUT_SEL_MASK 0x00000f00
-#define BCHP_XPT_FE_TSMF0_CTRL_TSMF_INPUT_SEL_SHIFT 8
-#define BCHP_XPT_FE_TSMF0_CTRL_TSMF_INPUT_SEL_DEFAULT 0x00000000
-
-/* XPT_FE :: TSMF0_CTRL :: reserved1 [07:03] */
-#define BCHP_XPT_FE_TSMF0_CTRL_reserved1_MASK 0x000000f8
-#define BCHP_XPT_FE_TSMF0_CTRL_reserved1_SHIFT 3
-
-/* XPT_FE :: TSMF0_CTRL :: TSMF_VER_CHANGE_MODE [02:02] */
-#define BCHP_XPT_FE_TSMF0_CTRL_TSMF_VER_CHANGE_MODE_MASK 0x00000004
-#define BCHP_XPT_FE_TSMF0_CTRL_TSMF_VER_CHANGE_MODE_SHIFT 2
-#define BCHP_XPT_FE_TSMF0_CTRL_TSMF_VER_CHANGE_MODE_DEFAULT 0x00000000
-
-/* XPT_FE :: TSMF0_CTRL :: TSMF_AUTO_EN [01:01] */
-#define BCHP_XPT_FE_TSMF0_CTRL_TSMF_AUTO_EN_MASK 0x00000002
-#define BCHP_XPT_FE_TSMF0_CTRL_TSMF_AUTO_EN_SHIFT 1
-#define BCHP_XPT_FE_TSMF0_CTRL_TSMF_AUTO_EN_DEFAULT 0x00000000
-
-/* XPT_FE :: TSMF0_CTRL :: TSMF_ENABLE [00:00] */
-#define BCHP_XPT_FE_TSMF0_CTRL_TSMF_ENABLE_MASK 0x00000001
-#define BCHP_XPT_FE_TSMF0_CTRL_TSMF_ENABLE_SHIFT 0
-#define BCHP_XPT_FE_TSMF0_CTRL_TSMF_ENABLE_DEFAULT 0x00000000
-
-/***************************************************************************
- *TSMF0_SLOT_MAP_LO - Data Transport TSMF Demultiplexer -- Slot Map Vector LSBs Register
- ***************************************************************************/
-/* XPT_FE :: TSMF0_SLOT_MAP_LO :: SLOT_MAP_LO [31:00] */
-#define BCHP_XPT_FE_TSMF0_SLOT_MAP_LO_SLOT_MAP_LO_MASK 0xffffffff
-#define BCHP_XPT_FE_TSMF0_SLOT_MAP_LO_SLOT_MAP_LO_SHIFT 0
-#define BCHP_XPT_FE_TSMF0_SLOT_MAP_LO_SLOT_MAP_LO_DEFAULT 0x00000000
-
-/***************************************************************************
- *TSMF0_SLOT_MAP_HI - Data Transport TSMF Demultiplexer -- Slot Map Vector MSBs Register
- ***************************************************************************/
-/* XPT_FE :: TSMF0_SLOT_MAP_HI :: reserved0 [31:20] */
-#define BCHP_XPT_FE_TSMF0_SLOT_MAP_HI_reserved0_MASK 0xfff00000
-#define BCHP_XPT_FE_TSMF0_SLOT_MAP_HI_reserved0_SHIFT 20
-
-/* XPT_FE :: TSMF0_SLOT_MAP_HI :: SLOT_MAP_HI [19:00] */
-#define BCHP_XPT_FE_TSMF0_SLOT_MAP_HI_SLOT_MAP_HI_MASK 0x000fffff
-#define BCHP_XPT_FE_TSMF0_SLOT_MAP_HI_SLOT_MAP_HI_SHIFT 0
-#define BCHP_XPT_FE_TSMF0_SLOT_MAP_HI_SLOT_MAP_HI_DEFAULT 0x00000000
-
-/***************************************************************************
- *TSMF0_STATUS - Data Transport TSMF Demultiplexer -- Status Register
- ***************************************************************************/
-/* XPT_FE :: TSMF0_STATUS :: reserved0 [31:10] */
-#define BCHP_XPT_FE_TSMF0_STATUS_reserved0_MASK 0xfffffc00
-#define BCHP_XPT_FE_TSMF0_STATUS_reserved0_SHIFT 10
-
-/* XPT_FE :: TSMF0_STATUS :: TSMF_TEST [09:01] */
-#define BCHP_XPT_FE_TSMF0_STATUS_TSMF_TEST_MASK 0x000003fe
-#define BCHP_XPT_FE_TSMF0_STATUS_TSMF_TEST_SHIFT 1
-
-/* XPT_FE :: TSMF0_STATUS :: TSMF_OOS_STATUS [00:00] */
-#define BCHP_XPT_FE_TSMF0_STATUS_TSMF_OOS_STATUS_MASK 0x00000001
-#define BCHP_XPT_FE_TSMF0_STATUS_TSMF_OOS_STATUS_SHIFT 0
-
-/***************************************************************************
- *TSMF1_CTRL - Data Transport TSMF Demultiplexer -- Control Register
- ***************************************************************************/
-/* XPT_FE :: TSMF1_CTRL :: reserved0 [31:28] */
-#define BCHP_XPT_FE_TSMF1_CTRL_reserved0_MASK 0xf0000000
-#define BCHP_XPT_FE_TSMF1_CTRL_reserved0_SHIFT 28
-
-/* XPT_FE :: TSMF1_CTRL :: TSMF_INPUT_SEL_MSB [27:27] */
-#define BCHP_XPT_FE_TSMF1_CTRL_TSMF_INPUT_SEL_MSB_MASK 0x08000000
-#define BCHP_XPT_FE_TSMF1_CTRL_TSMF_INPUT_SEL_MSB_SHIFT 27
-#define BCHP_XPT_FE_TSMF1_CTRL_TSMF_INPUT_SEL_MSB_DEFAULT 0x00000000
-
-/* XPT_FE :: TSMF1_CTRL :: TSMF_CRC_CK_DIS [26:26] */
-#define BCHP_XPT_FE_TSMF1_CTRL_TSMF_CRC_CK_DIS_MASK 0x04000000
-#define BCHP_XPT_FE_TSMF1_CTRL_TSMF_CRC_CK_DIS_SHIFT 26
-#define BCHP_XPT_FE_TSMF1_CTRL_TSMF_CRC_CK_DIS_DEFAULT 0x00000000
-
-/* XPT_FE :: TSMF1_CTRL :: TSMF_REL_TS_STATUS_CK_DIS [25:25] */
-#define BCHP_XPT_FE_TSMF1_CTRL_TSMF_REL_TS_STATUS_CK_DIS_MASK 0x02000000
-#define BCHP_XPT_FE_TSMF1_CTRL_TSMF_REL_TS_STATUS_CK_DIS_SHIFT 25
-#define BCHP_XPT_FE_TSMF1_CTRL_TSMF_REL_TS_STATUS_CK_DIS_DEFAULT 0x00000000
-
-/* XPT_FE :: TSMF1_CTRL :: TSMF_FRAME_TYPE_CK_DIS [24:24] */
-#define BCHP_XPT_FE_TSMF1_CTRL_TSMF_FRAME_TYPE_CK_DIS_MASK 0x01000000
-#define BCHP_XPT_FE_TSMF1_CTRL_TSMF_FRAME_TYPE_CK_DIS_SHIFT 24
-#define BCHP_XPT_FE_TSMF1_CTRL_TSMF_FRAME_TYPE_CK_DIS_DEFAULT 0x00000000
-
-/* XPT_FE :: TSMF1_CTRL :: TSMF_REL_TS_MODE_CK_DIS [23:23] */
-#define BCHP_XPT_FE_TSMF1_CTRL_TSMF_REL_TS_MODE_CK_DIS_MASK 0x00800000
-#define BCHP_XPT_FE_TSMF1_CTRL_TSMF_REL_TS_MODE_CK_DIS_SHIFT 23
-#define BCHP_XPT_FE_TSMF1_CTRL_TSMF_REL_TS_MODE_CK_DIS_DEFAULT 0x00000000
-
-/* XPT_FE :: TSMF1_CTRL :: TSMF_SYNC_CK_DIS [22:22] */
-#define BCHP_XPT_FE_TSMF1_CTRL_TSMF_SYNC_CK_DIS_MASK 0x00400000
-#define BCHP_XPT_FE_TSMF1_CTRL_TSMF_SYNC_CK_DIS_SHIFT 22
-#define BCHP_XPT_FE_TSMF1_CTRL_TSMF_SYNC_CK_DIS_DEFAULT 0x00000000
-
-/* XPT_FE :: TSMF1_CTRL :: TSMF_CC_CK_DIS [21:21] */
-#define BCHP_XPT_FE_TSMF1_CTRL_TSMF_CC_CK_DIS_MASK 0x00200000
-#define BCHP_XPT_FE_TSMF1_CTRL_TSMF_CC_CK_DIS_SHIFT 21
-#define BCHP_XPT_FE_TSMF1_CTRL_TSMF_CC_CK_DIS_DEFAULT 0x00000000
-
-/* XPT_FE :: TSMF1_CTRL :: TSMF_ADAP_CK_DIS [20:20] */
-#define BCHP_XPT_FE_TSMF1_CTRL_TSMF_ADAP_CK_DIS_MASK 0x00100000
-#define BCHP_XPT_FE_TSMF1_CTRL_TSMF_ADAP_CK_DIS_SHIFT 20
-#define BCHP_XPT_FE_TSMF1_CTRL_TSMF_ADAP_CK_DIS_DEFAULT 0x00000000
-
-/* XPT_FE :: TSMF1_CTRL :: TSMF_SC_CK_DIS [19:19] */
-#define BCHP_XPT_FE_TSMF1_CTRL_TSMF_SC_CK_DIS_MASK 0x00080000
-#define BCHP_XPT_FE_TSMF1_CTRL_TSMF_SC_CK_DIS_SHIFT 19
-#define BCHP_XPT_FE_TSMF1_CTRL_TSMF_SC_CK_DIS_DEFAULT 0x00000000
-
-/* XPT_FE :: TSMF1_CTRL :: TSMF_TS_PRIOR_CK_DIS [18:18] */
-#define BCHP_XPT_FE_TSMF1_CTRL_TSMF_TS_PRIOR_CK_DIS_MASK 0x00040000
-#define BCHP_XPT_FE_TSMF1_CTRL_TSMF_TS_PRIOR_CK_DIS_SHIFT 18
-#define BCHP_XPT_FE_TSMF1_CTRL_TSMF_TS_PRIOR_CK_DIS_DEFAULT 0x00000000
-
-/* XPT_FE :: TSMF1_CTRL :: TSMF_PUSI_CK_DIS [17:17] */
-#define BCHP_XPT_FE_TSMF1_CTRL_TSMF_PUSI_CK_DIS_MASK 0x00020000
-#define BCHP_XPT_FE_TSMF1_CTRL_TSMF_PUSI_CK_DIS_SHIFT 17
-#define BCHP_XPT_FE_TSMF1_CTRL_TSMF_PUSI_CK_DIS_DEFAULT 0x00000000
-
-/* XPT_FE :: TSMF1_CTRL :: TSMF_TEI_CK_DIS [16:16] */
-#define BCHP_XPT_FE_TSMF1_CTRL_TSMF_TEI_CK_DIS_MASK 0x00010000
-#define BCHP_XPT_FE_TSMF1_CTRL_TSMF_TEI_CK_DIS_SHIFT 16
-#define BCHP_XPT_FE_TSMF1_CTRL_TSMF_TEI_CK_DIS_DEFAULT 0x00000000
-
-/* XPT_FE :: TSMF1_CTRL :: TSMF_REL_TS_NO [15:12] */
-#define BCHP_XPT_FE_TSMF1_CTRL_TSMF_REL_TS_NO_MASK 0x0000f000
-#define BCHP_XPT_FE_TSMF1_CTRL_TSMF_REL_TS_NO_SHIFT 12
-#define BCHP_XPT_FE_TSMF1_CTRL_TSMF_REL_TS_NO_DEFAULT 0x00000000
-
-/* XPT_FE :: TSMF1_CTRL :: TSMF_INPUT_SEL [11:08] */
-#define BCHP_XPT_FE_TSMF1_CTRL_TSMF_INPUT_SEL_MASK 0x00000f00
-#define BCHP_XPT_FE_TSMF1_CTRL_TSMF_INPUT_SEL_SHIFT 8
-#define BCHP_XPT_FE_TSMF1_CTRL_TSMF_INPUT_SEL_DEFAULT 0x00000000
-
-/* XPT_FE :: TSMF1_CTRL :: reserved1 [07:03] */
-#define BCHP_XPT_FE_TSMF1_CTRL_reserved1_MASK 0x000000f8
-#define BCHP_XPT_FE_TSMF1_CTRL_reserved1_SHIFT 3
-
-/* XPT_FE :: TSMF1_CTRL :: TSMF_VER_CHANGE_MODE [02:02] */
-#define BCHP_XPT_FE_TSMF1_CTRL_TSMF_VER_CHANGE_MODE_MASK 0x00000004
-#define BCHP_XPT_FE_TSMF1_CTRL_TSMF_VER_CHANGE_MODE_SHIFT 2
-#define BCHP_XPT_FE_TSMF1_CTRL_TSMF_VER_CHANGE_MODE_DEFAULT 0x00000000
-
-/* XPT_FE :: TSMF1_CTRL :: TSMF_AUTO_EN [01:01] */
-#define BCHP_XPT_FE_TSMF1_CTRL_TSMF_AUTO_EN_MASK 0x00000002
-#define BCHP_XPT_FE_TSMF1_CTRL_TSMF_AUTO_EN_SHIFT 1
-#define BCHP_XPT_FE_TSMF1_CTRL_TSMF_AUTO_EN_DEFAULT 0x00000000
-
-/* XPT_FE :: TSMF1_CTRL :: TSMF_ENABLE [00:00] */
-#define BCHP_XPT_FE_TSMF1_CTRL_TSMF_ENABLE_MASK 0x00000001
-#define BCHP_XPT_FE_TSMF1_CTRL_TSMF_ENABLE_SHIFT 0
-#define BCHP_XPT_FE_TSMF1_CTRL_TSMF_ENABLE_DEFAULT 0x00000000
-
-/***************************************************************************
- *TSMF1_SLOT_MAP_LO - Data Transport TSMF Demultiplexer -- Slot Map Vector LSBs Register
- ***************************************************************************/
-/* XPT_FE :: TSMF1_SLOT_MAP_LO :: SLOT_MAP_LO [31:00] */
-#define BCHP_XPT_FE_TSMF1_SLOT_MAP_LO_SLOT_MAP_LO_MASK 0xffffffff
-#define BCHP_XPT_FE_TSMF1_SLOT_MAP_LO_SLOT_MAP_LO_SHIFT 0
-#define BCHP_XPT_FE_TSMF1_SLOT_MAP_LO_SLOT_MAP_LO_DEFAULT 0x00000000
-
-/***************************************************************************
- *TSMF1_SLOT_MAP_HI - Data Transport TSMF Demultiplexer -- Slot Map Vector MSBs Register
- ***************************************************************************/
-/* XPT_FE :: TSMF1_SLOT_MAP_HI :: reserved0 [31:20] */
-#define BCHP_XPT_FE_TSMF1_SLOT_MAP_HI_reserved0_MASK 0xfff00000
-#define BCHP_XPT_FE_TSMF1_SLOT_MAP_HI_reserved0_SHIFT 20
-
-/* XPT_FE :: TSMF1_SLOT_MAP_HI :: SLOT_MAP_HI [19:00] */
-#define BCHP_XPT_FE_TSMF1_SLOT_MAP_HI_SLOT_MAP_HI_MASK 0x000fffff
-#define BCHP_XPT_FE_TSMF1_SLOT_MAP_HI_SLOT_MAP_HI_SHIFT 0
-#define BCHP_XPT_FE_TSMF1_SLOT_MAP_HI_SLOT_MAP_HI_DEFAULT 0x00000000
-
-/***************************************************************************
- *TSMF1_STATUS - Data Transport TSMF Demultiplexer -- Status Register
- ***************************************************************************/
-/* XPT_FE :: TSMF1_STATUS :: reserved0 [31:10] */
-#define BCHP_XPT_FE_TSMF1_STATUS_reserved0_MASK 0xfffffc00
-#define BCHP_XPT_FE_TSMF1_STATUS_reserved0_SHIFT 10
-
-/* XPT_FE :: TSMF1_STATUS :: TSMF_TEST [09:01] */
-#define BCHP_XPT_FE_TSMF1_STATUS_TSMF_TEST_MASK 0x000003fe
-#define BCHP_XPT_FE_TSMF1_STATUS_TSMF_TEST_SHIFT 1
-
-/* XPT_FE :: TSMF1_STATUS :: TSMF_OOS_STATUS [00:00] */
-#define BCHP_XPT_FE_TSMF1_STATUS_TSMF_OOS_STATUS_MASK 0x00000001
-#define BCHP_XPT_FE_TSMF1_STATUS_TSMF_OOS_STATUS_SHIFT 0
-
-/***************************************************************************
- *MTSIF_RX0_CTRL1 - FE_MTSIF_RX0_CTRL1
- ***************************************************************************/
-/* XPT_FE :: MTSIF_RX0_CTRL1 :: reserved0 [31:09] */
-#define BCHP_XPT_FE_MTSIF_RX0_CTRL1_reserved0_MASK 0xfffffe00
-#define BCHP_XPT_FE_MTSIF_RX0_CTRL1_reserved0_SHIFT 9
-
-/* XPT_FE :: MTSIF_RX0_CTRL1 :: MTSIF_RX_DECRYPTION_ENABLE_STATUS [08:08] */
-#define BCHP_XPT_FE_MTSIF_RX0_CTRL1_MTSIF_RX_DECRYPTION_ENABLE_STATUS_MASK 0x00000100
-#define BCHP_XPT_FE_MTSIF_RX0_CTRL1_MTSIF_RX_DECRYPTION_ENABLE_STATUS_SHIFT 8
-#define BCHP_XPT_FE_MTSIF_RX0_CTRL1_MTSIF_RX_DECRYPTION_ENABLE_STATUS_DEFAULT 0x00000001
-
-/* XPT_FE :: MTSIF_RX0_CTRL1 :: MTSIF_RX_PKT_BAND_DETECT_MODE [07:07] */
-#define BCHP_XPT_FE_MTSIF_RX0_CTRL1_MTSIF_RX_PKT_BAND_DETECT_MODE_MASK 0x00000080
-#define BCHP_XPT_FE_MTSIF_RX0_CTRL1_MTSIF_RX_PKT_BAND_DETECT_MODE_SHIFT 7
-#define BCHP_XPT_FE_MTSIF_RX0_CTRL1_MTSIF_RX_PKT_BAND_DETECT_MODE_DEFAULT 0x00000000
-
-/* XPT_FE :: MTSIF_RX0_CTRL1 :: MTSIF_RX_ERR_RPT_EN [06:06] */
-#define BCHP_XPT_FE_MTSIF_RX0_CTRL1_MTSIF_RX_ERR_RPT_EN_MASK 0x00000040
-#define BCHP_XPT_FE_MTSIF_RX0_CTRL1_MTSIF_RX_ERR_RPT_EN_SHIFT 6
-#define BCHP_XPT_FE_MTSIF_RX0_CTRL1_MTSIF_RX_ERR_RPT_EN_DEFAULT 0x00000000
-
-/* XPT_FE :: MTSIF_RX0_CTRL1 :: MTSIF_RX_IF_WIDTH [05:04] */
-#define BCHP_XPT_FE_MTSIF_RX0_CTRL1_MTSIF_RX_IF_WIDTH_MASK 0x00000030
-#define BCHP_XPT_FE_MTSIF_RX0_CTRL1_MTSIF_RX_IF_WIDTH_SHIFT 4
-#define BCHP_XPT_FE_MTSIF_RX0_CTRL1_MTSIF_RX_IF_WIDTH_DEFAULT 0x00000003
-
-/* XPT_FE :: MTSIF_RX0_CTRL1 :: reserved1 [03:02] */
-#define BCHP_XPT_FE_MTSIF_RX0_CTRL1_reserved1_MASK 0x0000000c
-#define BCHP_XPT_FE_MTSIF_RX0_CTRL1_reserved1_SHIFT 2
-
-/* XPT_FE :: MTSIF_RX0_CTRL1 :: MTSIF_RX_CLOCK_POL_SEL [01:01] */
-#define BCHP_XPT_FE_MTSIF_RX0_CTRL1_MTSIF_RX_CLOCK_POL_SEL_MASK 0x00000002
-#define BCHP_XPT_FE_MTSIF_RX0_CTRL1_MTSIF_RX_CLOCK_POL_SEL_SHIFT 1
-#define BCHP_XPT_FE_MTSIF_RX0_CTRL1_MTSIF_RX_CLOCK_POL_SEL_DEFAULT 0x00000001
-
-/* XPT_FE :: MTSIF_RX0_CTRL1 :: PARSER_ENABLE [00:00] */
-#define BCHP_XPT_FE_MTSIF_RX0_CTRL1_PARSER_ENABLE_MASK 0x00000001
-#define BCHP_XPT_FE_MTSIF_RX0_CTRL1_PARSER_ENABLE_SHIFT 0
-#define BCHP_XPT_FE_MTSIF_RX0_CTRL1_PARSER_ENABLE_DEFAULT 0x00000000
-
-/***************************************************************************
- *MTSIF_RX0_SECRET_WORD - MTSIF RX0 Secret Word Register
- ***************************************************************************/
-/* XPT_FE :: MTSIF_RX0_SECRET_WORD :: SECRET_WORD [31:00] */
-#define BCHP_XPT_FE_MTSIF_RX0_SECRET_WORD_SECRET_WORD_MASK 0xffffffff
-#define BCHP_XPT_FE_MTSIF_RX0_SECRET_WORD_SECRET_WORD_SHIFT 0
-#define BCHP_XPT_FE_MTSIF_RX0_SECRET_WORD_SECRET_WORD_DEFAULT 0x00000000
-
-/***************************************************************************
- *MTSIF_RX0_BAND0_BAND31_ID_DROP - MTSIF RX0 Band0 to Band31 ID Drop Register
- ***************************************************************************/
-/* XPT_FE :: MTSIF_RX0_BAND0_BAND31_ID_DROP :: DROP_EN [31:00] */
-#define BCHP_XPT_FE_MTSIF_RX0_BAND0_BAND31_ID_DROP_DROP_EN_MASK 0xffffffff
-#define BCHP_XPT_FE_MTSIF_RX0_BAND0_BAND31_ID_DROP_DROP_EN_SHIFT 0
-#define BCHP_XPT_FE_MTSIF_RX0_BAND0_BAND31_ID_DROP_DROP_EN_DEFAULT 0x00000000
-
-/***************************************************************************
- *MTSIF_RX0_BAND0_BAND3_ID - MTSIF RX0 Band0 to Band3 ID Register
- ***************************************************************************/
-/* XPT_FE :: MTSIF_RX0_BAND0_BAND3_ID :: reserved0 [31:30] */
-#define BCHP_XPT_FE_MTSIF_RX0_BAND0_BAND3_ID_reserved0_MASK 0xc0000000
-#define BCHP_XPT_FE_MTSIF_RX0_BAND0_BAND3_ID_reserved0_SHIFT 30
-
-/* XPT_FE :: MTSIF_RX0_BAND0_BAND3_ID :: MTSIF_BAND3_BAND_ID [29:24] */
-#define BCHP_XPT_FE_MTSIF_RX0_BAND0_BAND3_ID_MTSIF_BAND3_BAND_ID_MASK 0x3f000000
-#define BCHP_XPT_FE_MTSIF_RX0_BAND0_BAND3_ID_MTSIF_BAND3_BAND_ID_SHIFT 24
-#define BCHP_XPT_FE_MTSIF_RX0_BAND0_BAND3_ID_MTSIF_BAND3_BAND_ID_DEFAULT 0x00000003
-
-/* XPT_FE :: MTSIF_RX0_BAND0_BAND3_ID :: reserved1 [23:22] */
-#define BCHP_XPT_FE_MTSIF_RX0_BAND0_BAND3_ID_reserved1_MASK 0x00c00000
-#define BCHP_XPT_FE_MTSIF_RX0_BAND0_BAND3_ID_reserved1_SHIFT 22
-
-/* XPT_FE :: MTSIF_RX0_BAND0_BAND3_ID :: MTSIF_BAND2_BAND_ID [21:16] */
-#define BCHP_XPT_FE_MTSIF_RX0_BAND0_BAND3_ID_MTSIF_BAND2_BAND_ID_MASK 0x003f0000
-#define BCHP_XPT_FE_MTSIF_RX0_BAND0_BAND3_ID_MTSIF_BAND2_BAND_ID_SHIFT 16
-#define BCHP_XPT_FE_MTSIF_RX0_BAND0_BAND3_ID_MTSIF_BAND2_BAND_ID_DEFAULT 0x00000002
-
-/* XPT_FE :: MTSIF_RX0_BAND0_BAND3_ID :: reserved2 [15:14] */
-#define BCHP_XPT_FE_MTSIF_RX0_BAND0_BAND3_ID_reserved2_MASK 0x0000c000
-#define BCHP_XPT_FE_MTSIF_RX0_BAND0_BAND3_ID_reserved2_SHIFT 14
-
-/* XPT_FE :: MTSIF_RX0_BAND0_BAND3_ID :: MTSIF_BAND1_BAND_ID [13:08] */
-#define BCHP_XPT_FE_MTSIF_RX0_BAND0_BAND3_ID_MTSIF_BAND1_BAND_ID_MASK 0x00003f00
-#define BCHP_XPT_FE_MTSIF_RX0_BAND0_BAND3_ID_MTSIF_BAND1_BAND_ID_SHIFT 8
-#define BCHP_XPT_FE_MTSIF_RX0_BAND0_BAND3_ID_MTSIF_BAND1_BAND_ID_DEFAULT 0x00000001
-
-/* XPT_FE :: MTSIF_RX0_BAND0_BAND3_ID :: reserved3 [07:06] */
-#define BCHP_XPT_FE_MTSIF_RX0_BAND0_BAND3_ID_reserved3_MASK 0x000000c0
-#define BCHP_XPT_FE_MTSIF_RX0_BAND0_BAND3_ID_reserved3_SHIFT 6
-
-/* XPT_FE :: MTSIF_RX0_BAND0_BAND3_ID :: MTSIF_BAND0_BAND_ID [05:00] */
-#define BCHP_XPT_FE_MTSIF_RX0_BAND0_BAND3_ID_MTSIF_BAND0_BAND_ID_MASK 0x0000003f
-#define BCHP_XPT_FE_MTSIF_RX0_BAND0_BAND3_ID_MTSIF_BAND0_BAND_ID_SHIFT 0
-#define BCHP_XPT_FE_MTSIF_RX0_BAND0_BAND3_ID_MTSIF_BAND0_BAND_ID_DEFAULT 0x00000000
-
-/***************************************************************************
- *MTSIF_RX0_BAND4_BAND7_ID - MTSIF RX0 Band4 to Band7 ID Register
- ***************************************************************************/
-/* XPT_FE :: MTSIF_RX0_BAND4_BAND7_ID :: reserved0 [31:30] */
-#define BCHP_XPT_FE_MTSIF_RX0_BAND4_BAND7_ID_reserved0_MASK 0xc0000000
-#define BCHP_XPT_FE_MTSIF_RX0_BAND4_BAND7_ID_reserved0_SHIFT 30
-
-/* XPT_FE :: MTSIF_RX0_BAND4_BAND7_ID :: MTSIF_BAND7_BAND_ID [29:24] */
-#define BCHP_XPT_FE_MTSIF_RX0_BAND4_BAND7_ID_MTSIF_BAND7_BAND_ID_MASK 0x3f000000
-#define BCHP_XPT_FE_MTSIF_RX0_BAND4_BAND7_ID_MTSIF_BAND7_BAND_ID_SHIFT 24
-#define BCHP_XPT_FE_MTSIF_RX0_BAND4_BAND7_ID_MTSIF_BAND7_BAND_ID_DEFAULT 0x00000007
-
-/* XPT_FE :: MTSIF_RX0_BAND4_BAND7_ID :: reserved1 [23:22] */
-#define BCHP_XPT_FE_MTSIF_RX0_BAND4_BAND7_ID_reserved1_MASK 0x00c00000
-#define BCHP_XPT_FE_MTSIF_RX0_BAND4_BAND7_ID_reserved1_SHIFT 22
-
-/* XPT_FE :: MTSIF_RX0_BAND4_BAND7_ID :: MTSIF_BAND6_BAND_ID [21:16] */
-#define BCHP_XPT_FE_MTSIF_RX0_BAND4_BAND7_ID_MTSIF_BAND6_BAND_ID_MASK 0x003f0000
-#define BCHP_XPT_FE_MTSIF_RX0_BAND4_BAND7_ID_MTSIF_BAND6_BAND_ID_SHIFT 16
-#define BCHP_XPT_FE_MTSIF_RX0_BAND4_BAND7_ID_MTSIF_BAND6_BAND_ID_DEFAULT 0x00000006
-
-/* XPT_FE :: MTSIF_RX0_BAND4_BAND7_ID :: reserved2 [15:14] */
-#define BCHP_XPT_FE_MTSIF_RX0_BAND4_BAND7_ID_reserved2_MASK 0x0000c000
-#define BCHP_XPT_FE_MTSIF_RX0_BAND4_BAND7_ID_reserved2_SHIFT 14
-
-/* XPT_FE :: MTSIF_RX0_BAND4_BAND7_ID :: MTSIF_BAND5_BAND_ID [13:08] */
-#define BCHP_XPT_FE_MTSIF_RX0_BAND4_BAND7_ID_MTSIF_BAND5_BAND_ID_MASK 0x00003f00
-#define BCHP_XPT_FE_MTSIF_RX0_BAND4_BAND7_ID_MTSIF_BAND5_BAND_ID_SHIFT 8
-#define BCHP_XPT_FE_MTSIF_RX0_BAND4_BAND7_ID_MTSIF_BAND5_BAND_ID_DEFAULT 0x00000005
-
-/* XPT_FE :: MTSIF_RX0_BAND4_BAND7_ID :: reserved3 [07:06] */
-#define BCHP_XPT_FE_MTSIF_RX0_BAND4_BAND7_ID_reserved3_MASK 0x000000c0
-#define BCHP_XPT_FE_MTSIF_RX0_BAND4_BAND7_ID_reserved3_SHIFT 6
-
-/* XPT_FE :: MTSIF_RX0_BAND4_BAND7_ID :: MTSIF_BAND4_BAND_ID [05:00] */
-#define BCHP_XPT_FE_MTSIF_RX0_BAND4_BAND7_ID_MTSIF_BAND4_BAND_ID_MASK 0x0000003f
-#define BCHP_XPT_FE_MTSIF_RX0_BAND4_BAND7_ID_MTSIF_BAND4_BAND_ID_SHIFT 0
-#define BCHP_XPT_FE_MTSIF_RX0_BAND4_BAND7_ID_MTSIF_BAND4_BAND_ID_DEFAULT 0x00000004
-
-/***************************************************************************
- *MTSIF_RX0_BAND8_BAND11_ID - MTSIF RX0 Band8 to Band11 ID Register
- ***************************************************************************/
-/* XPT_FE :: MTSIF_RX0_BAND8_BAND11_ID :: reserved0 [31:30] */
-#define BCHP_XPT_FE_MTSIF_RX0_BAND8_BAND11_ID_reserved0_MASK 0xc0000000
-#define BCHP_XPT_FE_MTSIF_RX0_BAND8_BAND11_ID_reserved0_SHIFT 30
-
-/* XPT_FE :: MTSIF_RX0_BAND8_BAND11_ID :: MTSIF_BAND11_BAND_ID [29:24] */
-#define BCHP_XPT_FE_MTSIF_RX0_BAND8_BAND11_ID_MTSIF_BAND11_BAND_ID_MASK 0x3f000000
-#define BCHP_XPT_FE_MTSIF_RX0_BAND8_BAND11_ID_MTSIF_BAND11_BAND_ID_SHIFT 24
-#define BCHP_XPT_FE_MTSIF_RX0_BAND8_BAND11_ID_MTSIF_BAND11_BAND_ID_DEFAULT 0x0000000b
-
-/* XPT_FE :: MTSIF_RX0_BAND8_BAND11_ID :: reserved1 [23:22] */
-#define BCHP_XPT_FE_MTSIF_RX0_BAND8_BAND11_ID_reserved1_MASK 0x00c00000
-#define BCHP_XPT_FE_MTSIF_RX0_BAND8_BAND11_ID_reserved1_SHIFT 22
-
-/* XPT_FE :: MTSIF_RX0_BAND8_BAND11_ID :: MTSIF_BAND10_BAND_ID [21:16] */
-#define BCHP_XPT_FE_MTSIF_RX0_BAND8_BAND11_ID_MTSIF_BAND10_BAND_ID_MASK 0x003f0000
-#define BCHP_XPT_FE_MTSIF_RX0_BAND8_BAND11_ID_MTSIF_BAND10_BAND_ID_SHIFT 16
-#define BCHP_XPT_FE_MTSIF_RX0_BAND8_BAND11_ID_MTSIF_BAND10_BAND_ID_DEFAULT 0x0000000a
-
-/* XPT_FE :: MTSIF_RX0_BAND8_BAND11_ID :: reserved2 [15:14] */
-#define BCHP_XPT_FE_MTSIF_RX0_BAND8_BAND11_ID_reserved2_MASK 0x0000c000
-#define BCHP_XPT_FE_MTSIF_RX0_BAND8_BAND11_ID_reserved2_SHIFT 14
-
-/* XPT_FE :: MTSIF_RX0_BAND8_BAND11_ID :: MTSIF_BAND9_BAND_ID [13:08] */
-#define BCHP_XPT_FE_MTSIF_RX0_BAND8_BAND11_ID_MTSIF_BAND9_BAND_ID_MASK 0x00003f00
-#define BCHP_XPT_FE_MTSIF_RX0_BAND8_BAND11_ID_MTSIF_BAND9_BAND_ID_SHIFT 8
-#define BCHP_XPT_FE_MTSIF_RX0_BAND8_BAND11_ID_MTSIF_BAND9_BAND_ID_DEFAULT 0x00000009
-
-/* XPT_FE :: MTSIF_RX0_BAND8_BAND11_ID :: reserved3 [07:06] */
-#define BCHP_XPT_FE_MTSIF_RX0_BAND8_BAND11_ID_reserved3_MASK 0x000000c0
-#define BCHP_XPT_FE_MTSIF_RX0_BAND8_BAND11_ID_reserved3_SHIFT 6
-
-/* XPT_FE :: MTSIF_RX0_BAND8_BAND11_ID :: MTSIF_BAND8_BAND_ID [05:00] */
-#define BCHP_XPT_FE_MTSIF_RX0_BAND8_BAND11_ID_MTSIF_BAND8_BAND_ID_MASK 0x0000003f
-#define BCHP_XPT_FE_MTSIF_RX0_BAND8_BAND11_ID_MTSIF_BAND8_BAND_ID_SHIFT 0
-#define BCHP_XPT_FE_MTSIF_RX0_BAND8_BAND11_ID_MTSIF_BAND8_BAND_ID_DEFAULT 0x00000008
-
-/***************************************************************************
- *MTSIF_RX0_BAND12_BAND15_ID - MTSIF RX0 Band12 to Band15 ID Register
- ***************************************************************************/
-/* XPT_FE :: MTSIF_RX0_BAND12_BAND15_ID :: reserved0 [31:30] */
-#define BCHP_XPT_FE_MTSIF_RX0_BAND12_BAND15_ID_reserved0_MASK 0xc0000000
-#define BCHP_XPT_FE_MTSIF_RX0_BAND12_BAND15_ID_reserved0_SHIFT 30
-
-/* XPT_FE :: MTSIF_RX0_BAND12_BAND15_ID :: MTSIF_BAND15_BAND_ID [29:24] */
-#define BCHP_XPT_FE_MTSIF_RX0_BAND12_BAND15_ID_MTSIF_BAND15_BAND_ID_MASK 0x3f000000
-#define BCHP_XPT_FE_MTSIF_RX0_BAND12_BAND15_ID_MTSIF_BAND15_BAND_ID_SHIFT 24
-#define BCHP_XPT_FE_MTSIF_RX0_BAND12_BAND15_ID_MTSIF_BAND15_BAND_ID_DEFAULT 0x0000000f
-
-/* XPT_FE :: MTSIF_RX0_BAND12_BAND15_ID :: reserved1 [23:22] */
-#define BCHP_XPT_FE_MTSIF_RX0_BAND12_BAND15_ID_reserved1_MASK 0x00c00000
-#define BCHP_XPT_FE_MTSIF_RX0_BAND12_BAND15_ID_reserved1_SHIFT 22
-
-/* XPT_FE :: MTSIF_RX0_BAND12_BAND15_ID :: MTSIF_BAND14_BAND_ID [21:16] */
-#define BCHP_XPT_FE_MTSIF_RX0_BAND12_BAND15_ID_MTSIF_BAND14_BAND_ID_MASK 0x003f0000
-#define BCHP_XPT_FE_MTSIF_RX0_BAND12_BAND15_ID_MTSIF_BAND14_BAND_ID_SHIFT 16
-#define BCHP_XPT_FE_MTSIF_RX0_BAND12_BAND15_ID_MTSIF_BAND14_BAND_ID_DEFAULT 0x0000000e
-
-/* XPT_FE :: MTSIF_RX0_BAND12_BAND15_ID :: reserved2 [15:14] */
-#define BCHP_XPT_FE_MTSIF_RX0_BAND12_BAND15_ID_reserved2_MASK 0x0000c000
-#define BCHP_XPT_FE_MTSIF_RX0_BAND12_BAND15_ID_reserved2_SHIFT 14
-
-/* XPT_FE :: MTSIF_RX0_BAND12_BAND15_ID :: MTSIF_BAND13_BAND_ID [13:08] */
-#define BCHP_XPT_FE_MTSIF_RX0_BAND12_BAND15_ID_MTSIF_BAND13_BAND_ID_MASK 0x00003f00
-#define BCHP_XPT_FE_MTSIF_RX0_BAND12_BAND15_ID_MTSIF_BAND13_BAND_ID_SHIFT 8
-#define BCHP_XPT_FE_MTSIF_RX0_BAND12_BAND15_ID_MTSIF_BAND13_BAND_ID_DEFAULT 0x0000000d
-
-/* XPT_FE :: MTSIF_RX0_BAND12_BAND15_ID :: reserved3 [07:06] */
-#define BCHP_XPT_FE_MTSIF_RX0_BAND12_BAND15_ID_reserved3_MASK 0x000000c0
-#define BCHP_XPT_FE_MTSIF_RX0_BAND12_BAND15_ID_reserved3_SHIFT 6
-
-/* XPT_FE :: MTSIF_RX0_BAND12_BAND15_ID :: MTSIF_BAND12_BAND_ID [05:00] */
-#define BCHP_XPT_FE_MTSIF_RX0_BAND12_BAND15_ID_MTSIF_BAND12_BAND_ID_MASK 0x0000003f
-#define BCHP_XPT_FE_MTSIF_RX0_BAND12_BAND15_ID_MTSIF_BAND12_BAND_ID_SHIFT 0
-#define BCHP_XPT_FE_MTSIF_RX0_BAND12_BAND15_ID_MTSIF_BAND12_BAND_ID_DEFAULT 0x0000000c
-
-/***************************************************************************
- *MTSIF_RX0_BAND16_BAND19_ID - MTSIF RX0 Band16 to Band19 ID Register
- ***************************************************************************/
-/* XPT_FE :: MTSIF_RX0_BAND16_BAND19_ID :: reserved0 [31:30] */
-#define BCHP_XPT_FE_MTSIF_RX0_BAND16_BAND19_ID_reserved0_MASK 0xc0000000
-#define BCHP_XPT_FE_MTSIF_RX0_BAND16_BAND19_ID_reserved0_SHIFT 30
-
-/* XPT_FE :: MTSIF_RX0_BAND16_BAND19_ID :: MTSIF_BAND19_BAND_ID [29:24] */
-#define BCHP_XPT_FE_MTSIF_RX0_BAND16_BAND19_ID_MTSIF_BAND19_BAND_ID_MASK 0x3f000000
-#define BCHP_XPT_FE_MTSIF_RX0_BAND16_BAND19_ID_MTSIF_BAND19_BAND_ID_SHIFT 24
-#define BCHP_XPT_FE_MTSIF_RX0_BAND16_BAND19_ID_MTSIF_BAND19_BAND_ID_DEFAULT 0x00000013
-
-/* XPT_FE :: MTSIF_RX0_BAND16_BAND19_ID :: reserved1 [23:22] */
-#define BCHP_XPT_FE_MTSIF_RX0_BAND16_BAND19_ID_reserved1_MASK 0x00c00000
-#define BCHP_XPT_FE_MTSIF_RX0_BAND16_BAND19_ID_reserved1_SHIFT 22
-
-/* XPT_FE :: MTSIF_RX0_BAND16_BAND19_ID :: MTSIF_BAND18_BAND_ID [21:16] */
-#define BCHP_XPT_FE_MTSIF_RX0_BAND16_BAND19_ID_MTSIF_BAND18_BAND_ID_MASK 0x003f0000
-#define BCHP_XPT_FE_MTSIF_RX0_BAND16_BAND19_ID_MTSIF_BAND18_BAND_ID_SHIFT 16
-#define BCHP_XPT_FE_MTSIF_RX0_BAND16_BAND19_ID_MTSIF_BAND18_BAND_ID_DEFAULT 0x00000012
-
-/* XPT_FE :: MTSIF_RX0_BAND16_BAND19_ID :: reserved2 [15:14] */
-#define BCHP_XPT_FE_MTSIF_RX0_BAND16_BAND19_ID_reserved2_MASK 0x0000c000
-#define BCHP_XPT_FE_MTSIF_RX0_BAND16_BAND19_ID_reserved2_SHIFT 14
-
-/* XPT_FE :: MTSIF_RX0_BAND16_BAND19_ID :: MTSIF_BAND17_BAND_ID [13:08] */
-#define BCHP_XPT_FE_MTSIF_RX0_BAND16_BAND19_ID_MTSIF_BAND17_BAND_ID_MASK 0x00003f00
-#define BCHP_XPT_FE_MTSIF_RX0_BAND16_BAND19_ID_MTSIF_BAND17_BAND_ID_SHIFT 8
-#define BCHP_XPT_FE_MTSIF_RX0_BAND16_BAND19_ID_MTSIF_BAND17_BAND_ID_DEFAULT 0x00000011
-
-/* XPT_FE :: MTSIF_RX0_BAND16_BAND19_ID :: reserved3 [07:06] */
-#define BCHP_XPT_FE_MTSIF_RX0_BAND16_BAND19_ID_reserved3_MASK 0x000000c0
-#define BCHP_XPT_FE_MTSIF_RX0_BAND16_BAND19_ID_reserved3_SHIFT 6
-
-/* XPT_FE :: MTSIF_RX0_BAND16_BAND19_ID :: MTSIF_BAND16_BAND_ID [05:00] */
-#define BCHP_XPT_FE_MTSIF_RX0_BAND16_BAND19_ID_MTSIF_BAND16_BAND_ID_MASK 0x0000003f
-#define BCHP_XPT_FE_MTSIF_RX0_BAND16_BAND19_ID_MTSIF_BAND16_BAND_ID_SHIFT 0
-#define BCHP_XPT_FE_MTSIF_RX0_BAND16_BAND19_ID_MTSIF_BAND16_BAND_ID_DEFAULT 0x00000010
-
-/***************************************************************************
- *MTSIF_RX0_BAND20_BAND23_ID - MTSIF RX0 Band20 to Band23 ID Register
- ***************************************************************************/
-/* XPT_FE :: MTSIF_RX0_BAND20_BAND23_ID :: reserved0 [31:30] */
-#define BCHP_XPT_FE_MTSIF_RX0_BAND20_BAND23_ID_reserved0_MASK 0xc0000000
-#define BCHP_XPT_FE_MTSIF_RX0_BAND20_BAND23_ID_reserved0_SHIFT 30
-
-/* XPT_FE :: MTSIF_RX0_BAND20_BAND23_ID :: MTSIF_BAND23_BAND_ID [29:24] */
-#define BCHP_XPT_FE_MTSIF_RX0_BAND20_BAND23_ID_MTSIF_BAND23_BAND_ID_MASK 0x3f000000
-#define BCHP_XPT_FE_MTSIF_RX0_BAND20_BAND23_ID_MTSIF_BAND23_BAND_ID_SHIFT 24
-#define BCHP_XPT_FE_MTSIF_RX0_BAND20_BAND23_ID_MTSIF_BAND23_BAND_ID_DEFAULT 0x00000017
-
-/* XPT_FE :: MTSIF_RX0_BAND20_BAND23_ID :: reserved1 [23:22] */
-#define BCHP_XPT_FE_MTSIF_RX0_BAND20_BAND23_ID_reserved1_MASK 0x00c00000
-#define BCHP_XPT_FE_MTSIF_RX0_BAND20_BAND23_ID_reserved1_SHIFT 22
-
-/* XPT_FE :: MTSIF_RX0_BAND20_BAND23_ID :: MTSIF_BAND22_BAND_ID [21:16] */
-#define BCHP_XPT_FE_MTSIF_RX0_BAND20_BAND23_ID_MTSIF_BAND22_BAND_ID_MASK 0x003f0000
-#define BCHP_XPT_FE_MTSIF_RX0_BAND20_BAND23_ID_MTSIF_BAND22_BAND_ID_SHIFT 16
-#define BCHP_XPT_FE_MTSIF_RX0_BAND20_BAND23_ID_MTSIF_BAND22_BAND_ID_DEFAULT 0x00000016
-
-/* XPT_FE :: MTSIF_RX0_BAND20_BAND23_ID :: reserved2 [15:14] */
-#define BCHP_XPT_FE_MTSIF_RX0_BAND20_BAND23_ID_reserved2_MASK 0x0000c000
-#define BCHP_XPT_FE_MTSIF_RX0_BAND20_BAND23_ID_reserved2_SHIFT 14
-
-/* XPT_FE :: MTSIF_RX0_BAND20_BAND23_ID :: MTSIF_BAND21_BAND_ID [13:08] */
-#define BCHP_XPT_FE_MTSIF_RX0_BAND20_BAND23_ID_MTSIF_BAND21_BAND_ID_MASK 0x00003f00
-#define BCHP_XPT_FE_MTSIF_RX0_BAND20_BAND23_ID_MTSIF_BAND21_BAND_ID_SHIFT 8
-#define BCHP_XPT_FE_MTSIF_RX0_BAND20_BAND23_ID_MTSIF_BAND21_BAND_ID_DEFAULT 0x00000015
-
-/* XPT_FE :: MTSIF_RX0_BAND20_BAND23_ID :: reserved3 [07:06] */
-#define BCHP_XPT_FE_MTSIF_RX0_BAND20_BAND23_ID_reserved3_MASK 0x000000c0
-#define BCHP_XPT_FE_MTSIF_RX0_BAND20_BAND23_ID_reserved3_SHIFT 6
-
-/* XPT_FE :: MTSIF_RX0_BAND20_BAND23_ID :: MTSIF_BAND20_BAND_ID [05:00] */
-#define BCHP_XPT_FE_MTSIF_RX0_BAND20_BAND23_ID_MTSIF_BAND20_BAND_ID_MASK 0x0000003f
-#define BCHP_XPT_FE_MTSIF_RX0_BAND20_BAND23_ID_MTSIF_BAND20_BAND_ID_SHIFT 0
-#define BCHP_XPT_FE_MTSIF_RX0_BAND20_BAND23_ID_MTSIF_BAND20_BAND_ID_DEFAULT 0x00000014
-
-/***************************************************************************
- *MTSIF_RX0_BAND24_BAND27_ID - MTSIF RX0 Band24 to Band27 ID Register
- ***************************************************************************/
-/* XPT_FE :: MTSIF_RX0_BAND24_BAND27_ID :: reserved0 [31:30] */
-#define BCHP_XPT_FE_MTSIF_RX0_BAND24_BAND27_ID_reserved0_MASK 0xc0000000
-#define BCHP_XPT_FE_MTSIF_RX0_BAND24_BAND27_ID_reserved0_SHIFT 30
-
-/* XPT_FE :: MTSIF_RX0_BAND24_BAND27_ID :: MTSIF_BAND27_BAND_ID [29:24] */
-#define BCHP_XPT_FE_MTSIF_RX0_BAND24_BAND27_ID_MTSIF_BAND27_BAND_ID_MASK 0x3f000000
-#define BCHP_XPT_FE_MTSIF_RX0_BAND24_BAND27_ID_MTSIF_BAND27_BAND_ID_SHIFT 24
-#define BCHP_XPT_FE_MTSIF_RX0_BAND24_BAND27_ID_MTSIF_BAND27_BAND_ID_DEFAULT 0x0000001b
-
-/* XPT_FE :: MTSIF_RX0_BAND24_BAND27_ID :: reserved1 [23:22] */
-#define BCHP_XPT_FE_MTSIF_RX0_BAND24_BAND27_ID_reserved1_MASK 0x00c00000
-#define BCHP_XPT_FE_MTSIF_RX0_BAND24_BAND27_ID_reserved1_SHIFT 22
-
-/* XPT_FE :: MTSIF_RX0_BAND24_BAND27_ID :: MTSIF_BAND26_BAND_ID [21:16] */
-#define BCHP_XPT_FE_MTSIF_RX0_BAND24_BAND27_ID_MTSIF_BAND26_BAND_ID_MASK 0x003f0000
-#define BCHP_XPT_FE_MTSIF_RX0_BAND24_BAND27_ID_MTSIF_BAND26_BAND_ID_SHIFT 16
-#define BCHP_XPT_FE_MTSIF_RX0_BAND24_BAND27_ID_MTSIF_BAND26_BAND_ID_DEFAULT 0x0000001a
-
-/* XPT_FE :: MTSIF_RX0_BAND24_BAND27_ID :: reserved2 [15:14] */
-#define BCHP_XPT_FE_MTSIF_RX0_BAND24_BAND27_ID_reserved2_MASK 0x0000c000
-#define BCHP_XPT_FE_MTSIF_RX0_BAND24_BAND27_ID_reserved2_SHIFT 14
-
-/* XPT_FE :: MTSIF_RX0_BAND24_BAND27_ID :: MTSIF_BAND25_BAND_ID [13:08] */
-#define BCHP_XPT_FE_MTSIF_RX0_BAND24_BAND27_ID_MTSIF_BAND25_BAND_ID_MASK 0x00003f00
-#define BCHP_XPT_FE_MTSIF_RX0_BAND24_BAND27_ID_MTSIF_BAND25_BAND_ID_SHIFT 8
-#define BCHP_XPT_FE_MTSIF_RX0_BAND24_BAND27_ID_MTSIF_BAND25_BAND_ID_DEFAULT 0x00000019
-
-/* XPT_FE :: MTSIF_RX0_BAND24_BAND27_ID :: reserved3 [07:06] */
-#define BCHP_XPT_FE_MTSIF_RX0_BAND24_BAND27_ID_reserved3_MASK 0x000000c0
-#define BCHP_XPT_FE_MTSIF_RX0_BAND24_BAND27_ID_reserved3_SHIFT 6
-
-/* XPT_FE :: MTSIF_RX0_BAND24_BAND27_ID :: MTSIF_BAND24_BAND_ID [05:00] */
-#define BCHP_XPT_FE_MTSIF_RX0_BAND24_BAND27_ID_MTSIF_BAND24_BAND_ID_MASK 0x0000003f
-#define BCHP_XPT_FE_MTSIF_RX0_BAND24_BAND27_ID_MTSIF_BAND24_BAND_ID_SHIFT 0
-#define BCHP_XPT_FE_MTSIF_RX0_BAND24_BAND27_ID_MTSIF_BAND24_BAND_ID_DEFAULT 0x00000018
-
-/***************************************************************************
- *MTSIF_RX0_BAND28_BAND31_ID - MTSIF RX0 Band28 to Band31 ID Register
- ***************************************************************************/
-/* XPT_FE :: MTSIF_RX0_BAND28_BAND31_ID :: reserved0 [31:30] */
-#define BCHP_XPT_FE_MTSIF_RX0_BAND28_BAND31_ID_reserved0_MASK 0xc0000000
-#define BCHP_XPT_FE_MTSIF_RX0_BAND28_BAND31_ID_reserved0_SHIFT 30
-
-/* XPT_FE :: MTSIF_RX0_BAND28_BAND31_ID :: MTSIF_BAND31_BAND_ID [29:24] */
-#define BCHP_XPT_FE_MTSIF_RX0_BAND28_BAND31_ID_MTSIF_BAND31_BAND_ID_MASK 0x3f000000
-#define BCHP_XPT_FE_MTSIF_RX0_BAND28_BAND31_ID_MTSIF_BAND31_BAND_ID_SHIFT 24
-#define BCHP_XPT_FE_MTSIF_RX0_BAND28_BAND31_ID_MTSIF_BAND31_BAND_ID_DEFAULT 0x0000001f
-
-/* XPT_FE :: MTSIF_RX0_BAND28_BAND31_ID :: reserved1 [23:22] */
-#define BCHP_XPT_FE_MTSIF_RX0_BAND28_BAND31_ID_reserved1_MASK 0x00c00000
-#define BCHP_XPT_FE_MTSIF_RX0_BAND28_BAND31_ID_reserved1_SHIFT 22
-
-/* XPT_FE :: MTSIF_RX0_BAND28_BAND31_ID :: MTSIF_BAND30_BAND_ID [21:16] */
-#define BCHP_XPT_FE_MTSIF_RX0_BAND28_BAND31_ID_MTSIF_BAND30_BAND_ID_MASK 0x003f0000
-#define BCHP_XPT_FE_MTSIF_RX0_BAND28_BAND31_ID_MTSIF_BAND30_BAND_ID_SHIFT 16
-#define BCHP_XPT_FE_MTSIF_RX0_BAND28_BAND31_ID_MTSIF_BAND30_BAND_ID_DEFAULT 0x0000001e
-
-/* XPT_FE :: MTSIF_RX0_BAND28_BAND31_ID :: reserved2 [15:14] */
-#define BCHP_XPT_FE_MTSIF_RX0_BAND28_BAND31_ID_reserved2_MASK 0x0000c000
-#define BCHP_XPT_FE_MTSIF_RX0_BAND28_BAND31_ID_reserved2_SHIFT 14
-
-/* XPT_FE :: MTSIF_RX0_BAND28_BAND31_ID :: MTSIF_BAND29_BAND_ID [13:08] */
-#define BCHP_XPT_FE_MTSIF_RX0_BAND28_BAND31_ID_MTSIF_BAND29_BAND_ID_MASK 0x00003f00
-#define BCHP_XPT_FE_MTSIF_RX0_BAND28_BAND31_ID_MTSIF_BAND29_BAND_ID_SHIFT 8
-#define BCHP_XPT_FE_MTSIF_RX0_BAND28_BAND31_ID_MTSIF_BAND29_BAND_ID_DEFAULT 0x0000001d
-
-/* XPT_FE :: MTSIF_RX0_BAND28_BAND31_ID :: reserved3 [07:06] */
-#define BCHP_XPT_FE_MTSIF_RX0_BAND28_BAND31_ID_reserved3_MASK 0x000000c0
-#define BCHP_XPT_FE_MTSIF_RX0_BAND28_BAND31_ID_reserved3_SHIFT 6
-
-/* XPT_FE :: MTSIF_RX0_BAND28_BAND31_ID :: MTSIF_BAND28_BAND_ID [05:00] */
-#define BCHP_XPT_FE_MTSIF_RX0_BAND28_BAND31_ID_MTSIF_BAND28_BAND_ID_MASK 0x0000003f
-#define BCHP_XPT_FE_MTSIF_RX0_BAND28_BAND31_ID_MTSIF_BAND28_BAND_ID_SHIFT 0
-#define BCHP_XPT_FE_MTSIF_RX0_BAND28_BAND31_ID_MTSIF_BAND28_BAND_ID_DEFAULT 0x0000001c
-
-/***************************************************************************
- *MTSIF_RX0_BAND32_BAND35_ID - MTSIF RX0 Band32 to Band35 ID Register
- ***************************************************************************/
-/* XPT_FE :: MTSIF_RX0_BAND32_BAND35_ID :: reserved0 [31:30] */
-#define BCHP_XPT_FE_MTSIF_RX0_BAND32_BAND35_ID_reserved0_MASK 0xc0000000
-#define BCHP_XPT_FE_MTSIF_RX0_BAND32_BAND35_ID_reserved0_SHIFT 30
-
-/* XPT_FE :: MTSIF_RX0_BAND32_BAND35_ID :: MTSIF_BAND35_BAND_ID [29:24] */
-#define BCHP_XPT_FE_MTSIF_RX0_BAND32_BAND35_ID_MTSIF_BAND35_BAND_ID_MASK 0x3f000000
-#define BCHP_XPT_FE_MTSIF_RX0_BAND32_BAND35_ID_MTSIF_BAND35_BAND_ID_SHIFT 24
-#define BCHP_XPT_FE_MTSIF_RX0_BAND32_BAND35_ID_MTSIF_BAND35_BAND_ID_DEFAULT 0x00000023
-
-/* XPT_FE :: MTSIF_RX0_BAND32_BAND35_ID :: reserved1 [23:22] */
-#define BCHP_XPT_FE_MTSIF_RX0_BAND32_BAND35_ID_reserved1_MASK 0x00c00000
-#define BCHP_XPT_FE_MTSIF_RX0_BAND32_BAND35_ID_reserved1_SHIFT 22
-
-/* XPT_FE :: MTSIF_RX0_BAND32_BAND35_ID :: MTSIF_BAND34_BAND_ID [21:16] */
-#define BCHP_XPT_FE_MTSIF_RX0_BAND32_BAND35_ID_MTSIF_BAND34_BAND_ID_MASK 0x003f0000
-#define BCHP_XPT_FE_MTSIF_RX0_BAND32_BAND35_ID_MTSIF_BAND34_BAND_ID_SHIFT 16
-#define BCHP_XPT_FE_MTSIF_RX0_BAND32_BAND35_ID_MTSIF_BAND34_BAND_ID_DEFAULT 0x00000022
-
-/* XPT_FE :: MTSIF_RX0_BAND32_BAND35_ID :: reserved2 [15:14] */
-#define BCHP_XPT_FE_MTSIF_RX0_BAND32_BAND35_ID_reserved2_MASK 0x0000c000
-#define BCHP_XPT_FE_MTSIF_RX0_BAND32_BAND35_ID_reserved2_SHIFT 14
-
-/* XPT_FE :: MTSIF_RX0_BAND32_BAND35_ID :: MTSIF_BAND33_BAND_ID [13:08] */
-#define BCHP_XPT_FE_MTSIF_RX0_BAND32_BAND35_ID_MTSIF_BAND33_BAND_ID_MASK 0x00003f00
-#define BCHP_XPT_FE_MTSIF_RX0_BAND32_BAND35_ID_MTSIF_BAND33_BAND_ID_SHIFT 8
-#define BCHP_XPT_FE_MTSIF_RX0_BAND32_BAND35_ID_MTSIF_BAND33_BAND_ID_DEFAULT 0x00000021
-
-/* XPT_FE :: MTSIF_RX0_BAND32_BAND35_ID :: reserved3 [07:06] */
-#define BCHP_XPT_FE_MTSIF_RX0_BAND32_BAND35_ID_reserved3_MASK 0x000000c0
-#define BCHP_XPT_FE_MTSIF_RX0_BAND32_BAND35_ID_reserved3_SHIFT 6
-
-/* XPT_FE :: MTSIF_RX0_BAND32_BAND35_ID :: MTSIF_BAND32_BAND_ID [05:00] */
-#define BCHP_XPT_FE_MTSIF_RX0_BAND32_BAND35_ID_MTSIF_BAND32_BAND_ID_MASK 0x0000003f
-#define BCHP_XPT_FE_MTSIF_RX0_BAND32_BAND35_ID_MTSIF_BAND32_BAND_ID_SHIFT 0
-#define BCHP_XPT_FE_MTSIF_RX0_BAND32_BAND35_ID_MTSIF_BAND32_BAND_ID_DEFAULT 0x00000020
-
-/***************************************************************************
- *MTSIF_RX0_BAND36_BAND39_ID - MTSIF RX0 Band36 to Band39 ID Register
- ***************************************************************************/
-/* XPT_FE :: MTSIF_RX0_BAND36_BAND39_ID :: reserved0 [31:30] */
-#define BCHP_XPT_FE_MTSIF_RX0_BAND36_BAND39_ID_reserved0_MASK 0xc0000000
-#define BCHP_XPT_FE_MTSIF_RX0_BAND36_BAND39_ID_reserved0_SHIFT 30
-
-/* XPT_FE :: MTSIF_RX0_BAND36_BAND39_ID :: MTSIF_BAND39_BAND_ID [29:24] */
-#define BCHP_XPT_FE_MTSIF_RX0_BAND36_BAND39_ID_MTSIF_BAND39_BAND_ID_MASK 0x3f000000
-#define BCHP_XPT_FE_MTSIF_RX0_BAND36_BAND39_ID_MTSIF_BAND39_BAND_ID_SHIFT 24
-#define BCHP_XPT_FE_MTSIF_RX0_BAND36_BAND39_ID_MTSIF_BAND39_BAND_ID_DEFAULT 0x00000027
-
-/* XPT_FE :: MTSIF_RX0_BAND36_BAND39_ID :: reserved1 [23:22] */
-#define BCHP_XPT_FE_MTSIF_RX0_BAND36_BAND39_ID_reserved1_MASK 0x00c00000
-#define BCHP_XPT_FE_MTSIF_RX0_BAND36_BAND39_ID_reserved1_SHIFT 22
-
-/* XPT_FE :: MTSIF_RX0_BAND36_BAND39_ID :: MTSIF_BAND38_BAND_ID [21:16] */
-#define BCHP_XPT_FE_MTSIF_RX0_BAND36_BAND39_ID_MTSIF_BAND38_BAND_ID_MASK 0x003f0000
-#define BCHP_XPT_FE_MTSIF_RX0_BAND36_BAND39_ID_MTSIF_BAND38_BAND_ID_SHIFT 16
-#define BCHP_XPT_FE_MTSIF_RX0_BAND36_BAND39_ID_MTSIF_BAND38_BAND_ID_DEFAULT 0x00000026
-
-/* XPT_FE :: MTSIF_RX0_BAND36_BAND39_ID :: reserved2 [15:14] */
-#define BCHP_XPT_FE_MTSIF_RX0_BAND36_BAND39_ID_reserved2_MASK 0x0000c000
-#define BCHP_XPT_FE_MTSIF_RX0_BAND36_BAND39_ID_reserved2_SHIFT 14
-
-/* XPT_FE :: MTSIF_RX0_BAND36_BAND39_ID :: MTSIF_BAND37_BAND_ID [13:08] */
-#define BCHP_XPT_FE_MTSIF_RX0_BAND36_BAND39_ID_MTSIF_BAND37_BAND_ID_MASK 0x00003f00
-#define BCHP_XPT_FE_MTSIF_RX0_BAND36_BAND39_ID_MTSIF_BAND37_BAND_ID_SHIFT 8
-#define BCHP_XPT_FE_MTSIF_RX0_BAND36_BAND39_ID_MTSIF_BAND37_BAND_ID_DEFAULT 0x00000025
-
-/* XPT_FE :: MTSIF_RX0_BAND36_BAND39_ID :: reserved3 [07:06] */
-#define BCHP_XPT_FE_MTSIF_RX0_BAND36_BAND39_ID_reserved3_MASK 0x000000c0
-#define BCHP_XPT_FE_MTSIF_RX0_BAND36_BAND39_ID_reserved3_SHIFT 6
-
-/* XPT_FE :: MTSIF_RX0_BAND36_BAND39_ID :: MTSIF_BAND36_BAND_ID [05:00] */
-#define BCHP_XPT_FE_MTSIF_RX0_BAND36_BAND39_ID_MTSIF_BAND36_BAND_ID_MASK 0x0000003f
-#define BCHP_XPT_FE_MTSIF_RX0_BAND36_BAND39_ID_MTSIF_BAND36_BAND_ID_SHIFT 0
-#define BCHP_XPT_FE_MTSIF_RX0_BAND36_BAND39_ID_MTSIF_BAND36_BAND_ID_DEFAULT 0x00000024
-
-/***************************************************************************
- *MTSIF_RX0_BAND40_BAND43_ID - MTSIF RX0 Band40 to Band43 ID Register
- ***************************************************************************/
-/* XPT_FE :: MTSIF_RX0_BAND40_BAND43_ID :: reserved0 [31:30] */
-#define BCHP_XPT_FE_MTSIF_RX0_BAND40_BAND43_ID_reserved0_MASK 0xc0000000
-#define BCHP_XPT_FE_MTSIF_RX0_BAND40_BAND43_ID_reserved0_SHIFT 30
-
-/* XPT_FE :: MTSIF_RX0_BAND40_BAND43_ID :: MTSIF_BAND43_BAND_ID [29:24] */
-#define BCHP_XPT_FE_MTSIF_RX0_BAND40_BAND43_ID_MTSIF_BAND43_BAND_ID_MASK 0x3f000000
-#define BCHP_XPT_FE_MTSIF_RX0_BAND40_BAND43_ID_MTSIF_BAND43_BAND_ID_SHIFT 24
-#define BCHP_XPT_FE_MTSIF_RX0_BAND40_BAND43_ID_MTSIF_BAND43_BAND_ID_DEFAULT 0x0000002b
-
-/* XPT_FE :: MTSIF_RX0_BAND40_BAND43_ID :: reserved1 [23:22] */
-#define BCHP_XPT_FE_MTSIF_RX0_BAND40_BAND43_ID_reserved1_MASK 0x00c00000
-#define BCHP_XPT_FE_MTSIF_RX0_BAND40_BAND43_ID_reserved1_SHIFT 22
-
-/* XPT_FE :: MTSIF_RX0_BAND40_BAND43_ID :: MTSIF_BAND42_BAND_ID [21:16] */
-#define BCHP_XPT_FE_MTSIF_RX0_BAND40_BAND43_ID_MTSIF_BAND42_BAND_ID_MASK 0x003f0000
-#define BCHP_XPT_FE_MTSIF_RX0_BAND40_BAND43_ID_MTSIF_BAND42_BAND_ID_SHIFT 16
-#define BCHP_XPT_FE_MTSIF_RX0_BAND40_BAND43_ID_MTSIF_BAND42_BAND_ID_DEFAULT 0x0000002a
-
-/* XPT_FE :: MTSIF_RX0_BAND40_BAND43_ID :: reserved2 [15:14] */
-#define BCHP_XPT_FE_MTSIF_RX0_BAND40_BAND43_ID_reserved2_MASK 0x0000c000
-#define BCHP_XPT_FE_MTSIF_RX0_BAND40_BAND43_ID_reserved2_SHIFT 14
-
-/* XPT_FE :: MTSIF_RX0_BAND40_BAND43_ID :: MTSIF_BAND41_BAND_ID [13:08] */
-#define BCHP_XPT_FE_MTSIF_RX0_BAND40_BAND43_ID_MTSIF_BAND41_BAND_ID_MASK 0x00003f00
-#define BCHP_XPT_FE_MTSIF_RX0_BAND40_BAND43_ID_MTSIF_BAND41_BAND_ID_SHIFT 8
-#define BCHP_XPT_FE_MTSIF_RX0_BAND40_BAND43_ID_MTSIF_BAND41_BAND_ID_DEFAULT 0x00000029
-
-/* XPT_FE :: MTSIF_RX0_BAND40_BAND43_ID :: reserved3 [07:06] */
-#define BCHP_XPT_FE_MTSIF_RX0_BAND40_BAND43_ID_reserved3_MASK 0x000000c0
-#define BCHP_XPT_FE_MTSIF_RX0_BAND40_BAND43_ID_reserved3_SHIFT 6
-
-/* XPT_FE :: MTSIF_RX0_BAND40_BAND43_ID :: MTSIF_BAND40_BAND_ID [05:00] */
-#define BCHP_XPT_FE_MTSIF_RX0_BAND40_BAND43_ID_MTSIF_BAND40_BAND_ID_MASK 0x0000003f
-#define BCHP_XPT_FE_MTSIF_RX0_BAND40_BAND43_ID_MTSIF_BAND40_BAND_ID_SHIFT 0
-#define BCHP_XPT_FE_MTSIF_RX0_BAND40_BAND43_ID_MTSIF_BAND40_BAND_ID_DEFAULT 0x00000028
-
-/***************************************************************************
- *MTSIF_RX0_BAND44_BAND47_ID - MTSIF RX0 Band44 to Band47 ID Register
- ***************************************************************************/
-/* XPT_FE :: MTSIF_RX0_BAND44_BAND47_ID :: reserved0 [31:30] */
-#define BCHP_XPT_FE_MTSIF_RX0_BAND44_BAND47_ID_reserved0_MASK 0xc0000000
-#define BCHP_XPT_FE_MTSIF_RX0_BAND44_BAND47_ID_reserved0_SHIFT 30
-
-/* XPT_FE :: MTSIF_RX0_BAND44_BAND47_ID :: MTSIF_BAND47_BAND_ID [29:24] */
-#define BCHP_XPT_FE_MTSIF_RX0_BAND44_BAND47_ID_MTSIF_BAND47_BAND_ID_MASK 0x3f000000
-#define BCHP_XPT_FE_MTSIF_RX0_BAND44_BAND47_ID_MTSIF_BAND47_BAND_ID_SHIFT 24
-#define BCHP_XPT_FE_MTSIF_RX0_BAND44_BAND47_ID_MTSIF_BAND47_BAND_ID_DEFAULT 0x0000002f
-
-/* XPT_FE :: MTSIF_RX0_BAND44_BAND47_ID :: reserved1 [23:22] */
-#define BCHP_XPT_FE_MTSIF_RX0_BAND44_BAND47_ID_reserved1_MASK 0x00c00000
-#define BCHP_XPT_FE_MTSIF_RX0_BAND44_BAND47_ID_reserved1_SHIFT 22
-
-/* XPT_FE :: MTSIF_RX0_BAND44_BAND47_ID :: MTSIF_BAND46_BAND_ID [21:16] */
-#define BCHP_XPT_FE_MTSIF_RX0_BAND44_BAND47_ID_MTSIF_BAND46_BAND_ID_MASK 0x003f0000
-#define BCHP_XPT_FE_MTSIF_RX0_BAND44_BAND47_ID_MTSIF_BAND46_BAND_ID_SHIFT 16
-#define BCHP_XPT_FE_MTSIF_RX0_BAND44_BAND47_ID_MTSIF_BAND46_BAND_ID_DEFAULT 0x0000002e
-
-/* XPT_FE :: MTSIF_RX0_BAND44_BAND47_ID :: reserved2 [15:14] */
-#define BCHP_XPT_FE_MTSIF_RX0_BAND44_BAND47_ID_reserved2_MASK 0x0000c000
-#define BCHP_XPT_FE_MTSIF_RX0_BAND44_BAND47_ID_reserved2_SHIFT 14
-
-/* XPT_FE :: MTSIF_RX0_BAND44_BAND47_ID :: MTSIF_BAND45_BAND_ID [13:08] */
-#define BCHP_XPT_FE_MTSIF_RX0_BAND44_BAND47_ID_MTSIF_BAND45_BAND_ID_MASK 0x00003f00
-#define BCHP_XPT_FE_MTSIF_RX0_BAND44_BAND47_ID_MTSIF_BAND45_BAND_ID_SHIFT 8
-#define BCHP_XPT_FE_MTSIF_RX0_BAND44_BAND47_ID_MTSIF_BAND45_BAND_ID_DEFAULT 0x0000002d
-
-/* XPT_FE :: MTSIF_RX0_BAND44_BAND47_ID :: reserved3 [07:06] */
-#define BCHP_XPT_FE_MTSIF_RX0_BAND44_BAND47_ID_reserved3_MASK 0x000000c0
-#define BCHP_XPT_FE_MTSIF_RX0_BAND44_BAND47_ID_reserved3_SHIFT 6
-
-/* XPT_FE :: MTSIF_RX0_BAND44_BAND47_ID :: MTSIF_BAND44_BAND_ID [05:00] */
-#define BCHP_XPT_FE_MTSIF_RX0_BAND44_BAND47_ID_MTSIF_BAND44_BAND_ID_MASK 0x0000003f
-#define BCHP_XPT_FE_MTSIF_RX0_BAND44_BAND47_ID_MTSIF_BAND44_BAND_ID_SHIFT 0
-#define BCHP_XPT_FE_MTSIF_RX0_BAND44_BAND47_ID_MTSIF_BAND44_BAND_ID_DEFAULT 0x0000002c
-
-/***************************************************************************
- *MTSIF_RX0_BAND48_BAND51_ID - MTSIF RX0 Band48 to Band51 ID Register
- ***************************************************************************/
-/* XPT_FE :: MTSIF_RX0_BAND48_BAND51_ID :: reserved0 [31:30] */
-#define BCHP_XPT_FE_MTSIF_RX0_BAND48_BAND51_ID_reserved0_MASK 0xc0000000
-#define BCHP_XPT_FE_MTSIF_RX0_BAND48_BAND51_ID_reserved0_SHIFT 30
-
-/* XPT_FE :: MTSIF_RX0_BAND48_BAND51_ID :: MTSIF_BAND51_BAND_ID [29:24] */
-#define BCHP_XPT_FE_MTSIF_RX0_BAND48_BAND51_ID_MTSIF_BAND51_BAND_ID_MASK 0x3f000000
-#define BCHP_XPT_FE_MTSIF_RX0_BAND48_BAND51_ID_MTSIF_BAND51_BAND_ID_SHIFT 24
-#define BCHP_XPT_FE_MTSIF_RX0_BAND48_BAND51_ID_MTSIF_BAND51_BAND_ID_DEFAULT 0x00000033
-
-/* XPT_FE :: MTSIF_RX0_BAND48_BAND51_ID :: reserved1 [23:22] */
-#define BCHP_XPT_FE_MTSIF_RX0_BAND48_BAND51_ID_reserved1_MASK 0x00c00000
-#define BCHP_XPT_FE_MTSIF_RX0_BAND48_BAND51_ID_reserved1_SHIFT 22
-
-/* XPT_FE :: MTSIF_RX0_BAND48_BAND51_ID :: MTSIF_BAND50_BAND_ID [21:16] */
-#define BCHP_XPT_FE_MTSIF_RX0_BAND48_BAND51_ID_MTSIF_BAND50_BAND_ID_MASK 0x003f0000
-#define BCHP_XPT_FE_MTSIF_RX0_BAND48_BAND51_ID_MTSIF_BAND50_BAND_ID_SHIFT 16
-#define BCHP_XPT_FE_MTSIF_RX0_BAND48_BAND51_ID_MTSIF_BAND50_BAND_ID_DEFAULT 0x00000032
-
-/* XPT_FE :: MTSIF_RX0_BAND48_BAND51_ID :: reserved2 [15:14] */
-#define BCHP_XPT_FE_MTSIF_RX0_BAND48_BAND51_ID_reserved2_MASK 0x0000c000
-#define BCHP_XPT_FE_MTSIF_RX0_BAND48_BAND51_ID_reserved2_SHIFT 14
-
-/* XPT_FE :: MTSIF_RX0_BAND48_BAND51_ID :: MTSIF_BAND49_BAND_ID [13:08] */
-#define BCHP_XPT_FE_MTSIF_RX0_BAND48_BAND51_ID_MTSIF_BAND49_BAND_ID_MASK 0x00003f00
-#define BCHP_XPT_FE_MTSIF_RX0_BAND48_BAND51_ID_MTSIF_BAND49_BAND_ID_SHIFT 8
-#define BCHP_XPT_FE_MTSIF_RX0_BAND48_BAND51_ID_MTSIF_BAND49_BAND_ID_DEFAULT 0x00000031
-
-/* XPT_FE :: MTSIF_RX0_BAND48_BAND51_ID :: reserved3 [07:06] */
-#define BCHP_XPT_FE_MTSIF_RX0_BAND48_BAND51_ID_reserved3_MASK 0x000000c0
-#define BCHP_XPT_FE_MTSIF_RX0_BAND48_BAND51_ID_reserved3_SHIFT 6
-
-/* XPT_FE :: MTSIF_RX0_BAND48_BAND51_ID :: MTSIF_BAND48_BAND_ID [05:00] */
-#define BCHP_XPT_FE_MTSIF_RX0_BAND48_BAND51_ID_MTSIF_BAND48_BAND_ID_MASK 0x0000003f
-#define BCHP_XPT_FE_MTSIF_RX0_BAND48_BAND51_ID_MTSIF_BAND48_BAND_ID_SHIFT 0
-#define BCHP_XPT_FE_MTSIF_RX0_BAND48_BAND51_ID_MTSIF_BAND48_BAND_ID_DEFAULT 0x00000030
-
-/***************************************************************************
- *MTSIF_RX0_BAND52_BAND55_ID - MTSIF RX0 Band52 to Band55 ID Register
- ***************************************************************************/
-/* XPT_FE :: MTSIF_RX0_BAND52_BAND55_ID :: reserved0 [31:30] */
-#define BCHP_XPT_FE_MTSIF_RX0_BAND52_BAND55_ID_reserved0_MASK 0xc0000000
-#define BCHP_XPT_FE_MTSIF_RX0_BAND52_BAND55_ID_reserved0_SHIFT 30
-
-/* XPT_FE :: MTSIF_RX0_BAND52_BAND55_ID :: MTSIF_BAND55_BAND_ID [29:24] */
-#define BCHP_XPT_FE_MTSIF_RX0_BAND52_BAND55_ID_MTSIF_BAND55_BAND_ID_MASK 0x3f000000
-#define BCHP_XPT_FE_MTSIF_RX0_BAND52_BAND55_ID_MTSIF_BAND55_BAND_ID_SHIFT 24
-#define BCHP_XPT_FE_MTSIF_RX0_BAND52_BAND55_ID_MTSIF_BAND55_BAND_ID_DEFAULT 0x00000037
-
-/* XPT_FE :: MTSIF_RX0_BAND52_BAND55_ID :: reserved1 [23:22] */
-#define BCHP_XPT_FE_MTSIF_RX0_BAND52_BAND55_ID_reserved1_MASK 0x00c00000
-#define BCHP_XPT_FE_MTSIF_RX0_BAND52_BAND55_ID_reserved1_SHIFT 22
-
-/* XPT_FE :: MTSIF_RX0_BAND52_BAND55_ID :: MTSIF_BAND54_BAND_ID [21:16] */
-#define BCHP_XPT_FE_MTSIF_RX0_BAND52_BAND55_ID_MTSIF_BAND54_BAND_ID_MASK 0x003f0000
-#define BCHP_XPT_FE_MTSIF_RX0_BAND52_BAND55_ID_MTSIF_BAND54_BAND_ID_SHIFT 16
-#define BCHP_XPT_FE_MTSIF_RX0_BAND52_BAND55_ID_MTSIF_BAND54_BAND_ID_DEFAULT 0x00000036
-
-/* XPT_FE :: MTSIF_RX0_BAND52_BAND55_ID :: reserved2 [15:14] */
-#define BCHP_XPT_FE_MTSIF_RX0_BAND52_BAND55_ID_reserved2_MASK 0x0000c000
-#define BCHP_XPT_FE_MTSIF_RX0_BAND52_BAND55_ID_reserved2_SHIFT 14
-
-/* XPT_FE :: MTSIF_RX0_BAND52_BAND55_ID :: MTSIF_BAND53_BAND_ID [13:08] */
-#define BCHP_XPT_FE_MTSIF_RX0_BAND52_BAND55_ID_MTSIF_BAND53_BAND_ID_MASK 0x00003f00
-#define BCHP_XPT_FE_MTSIF_RX0_BAND52_BAND55_ID_MTSIF_BAND53_BAND_ID_SHIFT 8
-#define BCHP_XPT_FE_MTSIF_RX0_BAND52_BAND55_ID_MTSIF_BAND53_BAND_ID_DEFAULT 0x00000035
-
-/* XPT_FE :: MTSIF_RX0_BAND52_BAND55_ID :: reserved3 [07:06] */
-#define BCHP_XPT_FE_MTSIF_RX0_BAND52_BAND55_ID_reserved3_MASK 0x000000c0
-#define BCHP_XPT_FE_MTSIF_RX0_BAND52_BAND55_ID_reserved3_SHIFT 6
-
-/* XPT_FE :: MTSIF_RX0_BAND52_BAND55_ID :: MTSIF_BAND52_BAND_ID [05:00] */
-#define BCHP_XPT_FE_MTSIF_RX0_BAND52_BAND55_ID_MTSIF_BAND52_BAND_ID_MASK 0x0000003f
-#define BCHP_XPT_FE_MTSIF_RX0_BAND52_BAND55_ID_MTSIF_BAND52_BAND_ID_SHIFT 0
-#define BCHP_XPT_FE_MTSIF_RX0_BAND52_BAND55_ID_MTSIF_BAND52_BAND_ID_DEFAULT 0x00000034
-
-/***************************************************************************
- *MTSIF_RX0_BAND56_BAND59_ID - MTSIF RX0 Band56 to Band59 ID Register
- ***************************************************************************/
-/* XPT_FE :: MTSIF_RX0_BAND56_BAND59_ID :: reserved0 [31:30] */
-#define BCHP_XPT_FE_MTSIF_RX0_BAND56_BAND59_ID_reserved0_MASK 0xc0000000
-#define BCHP_XPT_FE_MTSIF_RX0_BAND56_BAND59_ID_reserved0_SHIFT 30
-
-/* XPT_FE :: MTSIF_RX0_BAND56_BAND59_ID :: MTSIF_BAND59_BAND_ID [29:24] */
-#define BCHP_XPT_FE_MTSIF_RX0_BAND56_BAND59_ID_MTSIF_BAND59_BAND_ID_MASK 0x3f000000
-#define BCHP_XPT_FE_MTSIF_RX0_BAND56_BAND59_ID_MTSIF_BAND59_BAND_ID_SHIFT 24
-#define BCHP_XPT_FE_MTSIF_RX0_BAND56_BAND59_ID_MTSIF_BAND59_BAND_ID_DEFAULT 0x0000003b
-
-/* XPT_FE :: MTSIF_RX0_BAND56_BAND59_ID :: reserved1 [23:22] */
-#define BCHP_XPT_FE_MTSIF_RX0_BAND56_BAND59_ID_reserved1_MASK 0x00c00000
-#define BCHP_XPT_FE_MTSIF_RX0_BAND56_BAND59_ID_reserved1_SHIFT 22
-
-/* XPT_FE :: MTSIF_RX0_BAND56_BAND59_ID :: MTSIF_BAND58_BAND_ID [21:16] */
-#define BCHP_XPT_FE_MTSIF_RX0_BAND56_BAND59_ID_MTSIF_BAND58_BAND_ID_MASK 0x003f0000
-#define BCHP_XPT_FE_MTSIF_RX0_BAND56_BAND59_ID_MTSIF_BAND58_BAND_ID_SHIFT 16
-#define BCHP_XPT_FE_MTSIF_RX0_BAND56_BAND59_ID_MTSIF_BAND58_BAND_ID_DEFAULT 0x0000003a
-
-/* XPT_FE :: MTSIF_RX0_BAND56_BAND59_ID :: reserved2 [15:14] */
-#define BCHP_XPT_FE_MTSIF_RX0_BAND56_BAND59_ID_reserved2_MASK 0x0000c000
-#define BCHP_XPT_FE_MTSIF_RX0_BAND56_BAND59_ID_reserved2_SHIFT 14
-
-/* XPT_FE :: MTSIF_RX0_BAND56_BAND59_ID :: MTSIF_BAND57_BAND_ID [13:08] */
-#define BCHP_XPT_FE_MTSIF_RX0_BAND56_BAND59_ID_MTSIF_BAND57_BAND_ID_MASK 0x00003f00
-#define BCHP_XPT_FE_MTSIF_RX0_BAND56_BAND59_ID_MTSIF_BAND57_BAND_ID_SHIFT 8
-#define BCHP_XPT_FE_MTSIF_RX0_BAND56_BAND59_ID_MTSIF_BAND57_BAND_ID_DEFAULT 0x00000039
-
-/* XPT_FE :: MTSIF_RX0_BAND56_BAND59_ID :: reserved3 [07:06] */
-#define BCHP_XPT_FE_MTSIF_RX0_BAND56_BAND59_ID_reserved3_MASK 0x000000c0
-#define BCHP_XPT_FE_MTSIF_RX0_BAND56_BAND59_ID_reserved3_SHIFT 6
-
-/* XPT_FE :: MTSIF_RX0_BAND56_BAND59_ID :: MTSIF_BAND56_BAND_ID [05:00] */
-#define BCHP_XPT_FE_MTSIF_RX0_BAND56_BAND59_ID_MTSIF_BAND56_BAND_ID_MASK 0x0000003f
-#define BCHP_XPT_FE_MTSIF_RX0_BAND56_BAND59_ID_MTSIF_BAND56_BAND_ID_SHIFT 0
-#define BCHP_XPT_FE_MTSIF_RX0_BAND56_BAND59_ID_MTSIF_BAND56_BAND_ID_DEFAULT 0x00000038
-
-/***************************************************************************
- *MTSIF_RX0_BAND60_BAND63_ID - MTSIF RX0 Band60 to Band63 ID Register
- ***************************************************************************/
-/* XPT_FE :: MTSIF_RX0_BAND60_BAND63_ID :: reserved0 [31:30] */
-#define BCHP_XPT_FE_MTSIF_RX0_BAND60_BAND63_ID_reserved0_MASK 0xc0000000
-#define BCHP_XPT_FE_MTSIF_RX0_BAND60_BAND63_ID_reserved0_SHIFT 30
-
-/* XPT_FE :: MTSIF_RX0_BAND60_BAND63_ID :: MTSIF_BAND63_BAND_ID [29:24] */
-#define BCHP_XPT_FE_MTSIF_RX0_BAND60_BAND63_ID_MTSIF_BAND63_BAND_ID_MASK 0x3f000000
-#define BCHP_XPT_FE_MTSIF_RX0_BAND60_BAND63_ID_MTSIF_BAND63_BAND_ID_SHIFT 24
-#define BCHP_XPT_FE_MTSIF_RX0_BAND60_BAND63_ID_MTSIF_BAND63_BAND_ID_DEFAULT 0x0000003f
-
-/* XPT_FE :: MTSIF_RX0_BAND60_BAND63_ID :: reserved1 [23:22] */
-#define BCHP_XPT_FE_MTSIF_RX0_BAND60_BAND63_ID_reserved1_MASK 0x00c00000
-#define BCHP_XPT_FE_MTSIF_RX0_BAND60_BAND63_ID_reserved1_SHIFT 22
-
-/* XPT_FE :: MTSIF_RX0_BAND60_BAND63_ID :: MTSIF_BAND62_BAND_ID [21:16] */
-#define BCHP_XPT_FE_MTSIF_RX0_BAND60_BAND63_ID_MTSIF_BAND62_BAND_ID_MASK 0x003f0000
-#define BCHP_XPT_FE_MTSIF_RX0_BAND60_BAND63_ID_MTSIF_BAND62_BAND_ID_SHIFT 16
-#define BCHP_XPT_FE_MTSIF_RX0_BAND60_BAND63_ID_MTSIF_BAND62_BAND_ID_DEFAULT 0x0000003e
-
-/* XPT_FE :: MTSIF_RX0_BAND60_BAND63_ID :: reserved2 [15:14] */
-#define BCHP_XPT_FE_MTSIF_RX0_BAND60_BAND63_ID_reserved2_MASK 0x0000c000
-#define BCHP_XPT_FE_MTSIF_RX0_BAND60_BAND63_ID_reserved2_SHIFT 14
-
-/* XPT_FE :: MTSIF_RX0_BAND60_BAND63_ID :: MTSIF_BAND61_BAND_ID [13:08] */
-#define BCHP_XPT_FE_MTSIF_RX0_BAND60_BAND63_ID_MTSIF_BAND61_BAND_ID_MASK 0x00003f00
-#define BCHP_XPT_FE_MTSIF_RX0_BAND60_BAND63_ID_MTSIF_BAND61_BAND_ID_SHIFT 8
-#define BCHP_XPT_FE_MTSIF_RX0_BAND60_BAND63_ID_MTSIF_BAND61_BAND_ID_DEFAULT 0x0000003d
-
-/* XPT_FE :: MTSIF_RX0_BAND60_BAND63_ID :: reserved3 [07:06] */
-#define BCHP_XPT_FE_MTSIF_RX0_BAND60_BAND63_ID_reserved3_MASK 0x000000c0
-#define BCHP_XPT_FE_MTSIF_RX0_BAND60_BAND63_ID_reserved3_SHIFT 6
-
-/* XPT_FE :: MTSIF_RX0_BAND60_BAND63_ID :: MTSIF_BAND60_BAND_ID [05:00] */
-#define BCHP_XPT_FE_MTSIF_RX0_BAND60_BAND63_ID_MTSIF_BAND60_BAND_ID_MASK 0x0000003f
-#define BCHP_XPT_FE_MTSIF_RX0_BAND60_BAND63_ID_MTSIF_BAND60_BAND_ID_SHIFT 0
-#define BCHP_XPT_FE_MTSIF_RX0_BAND60_BAND63_ID_MTSIF_BAND60_BAND_ID_DEFAULT 0x0000003c
-
-/***************************************************************************
- *MTSIF_RX0_PKT_BAND0_BAND31_DETECT - MTSIF RX0 Packet Band0 to Band31 Detect Register
- ***************************************************************************/
-/* XPT_FE :: MTSIF_RX0_PKT_BAND0_BAND31_DETECT :: BAND_ID31 [31:31] */
-#define BCHP_XPT_FE_MTSIF_RX0_PKT_BAND0_BAND31_DETECT_BAND_ID31_MASK 0x80000000
-#define BCHP_XPT_FE_MTSIF_RX0_PKT_BAND0_BAND31_DETECT_BAND_ID31_SHIFT 31
-#define BCHP_XPT_FE_MTSIF_RX0_PKT_BAND0_BAND31_DETECT_BAND_ID31_DEFAULT 0x00000000
-
-/* XPT_FE :: MTSIF_RX0_PKT_BAND0_BAND31_DETECT :: BAND_ID30 [30:30] */
-#define BCHP_XPT_FE_MTSIF_RX0_PKT_BAND0_BAND31_DETECT_BAND_ID30_MASK 0x40000000
-#define BCHP_XPT_FE_MTSIF_RX0_PKT_BAND0_BAND31_DETECT_BAND_ID30_SHIFT 30
-#define BCHP_XPT_FE_MTSIF_RX0_PKT_BAND0_BAND31_DETECT_BAND_ID30_DEFAULT 0x00000000
-
-/* XPT_FE :: MTSIF_RX0_PKT_BAND0_BAND31_DETECT :: BAND_ID29 [29:29] */
-#define BCHP_XPT_FE_MTSIF_RX0_PKT_BAND0_BAND31_DETECT_BAND_ID29_MASK 0x20000000
-#define BCHP_XPT_FE_MTSIF_RX0_PKT_BAND0_BAND31_DETECT_BAND_ID29_SHIFT 29
-#define BCHP_XPT_FE_MTSIF_RX0_PKT_BAND0_BAND31_DETECT_BAND_ID29_DEFAULT 0x00000000
-
-/* XPT_FE :: MTSIF_RX0_PKT_BAND0_BAND31_DETECT :: BAND_ID28 [28:28] */
-#define BCHP_XPT_FE_MTSIF_RX0_PKT_BAND0_BAND31_DETECT_BAND_ID28_MASK 0x10000000
-#define BCHP_XPT_FE_MTSIF_RX0_PKT_BAND0_BAND31_DETECT_BAND_ID28_SHIFT 28
-#define BCHP_XPT_FE_MTSIF_RX0_PKT_BAND0_BAND31_DETECT_BAND_ID28_DEFAULT 0x00000000
-
-/* XPT_FE :: MTSIF_RX0_PKT_BAND0_BAND31_DETECT :: BAND_ID27 [27:27] */
-#define BCHP_XPT_FE_MTSIF_RX0_PKT_BAND0_BAND31_DETECT_BAND_ID27_MASK 0x08000000
-#define BCHP_XPT_FE_MTSIF_RX0_PKT_BAND0_BAND31_DETECT_BAND_ID27_SHIFT 27
-#define BCHP_XPT_FE_MTSIF_RX0_PKT_BAND0_BAND31_DETECT_BAND_ID27_DEFAULT 0x00000000
-
-/* XPT_FE :: MTSIF_RX0_PKT_BAND0_BAND31_DETECT :: BAND_ID26 [26:26] */
-#define BCHP_XPT_FE_MTSIF_RX0_PKT_BAND0_BAND31_DETECT_BAND_ID26_MASK 0x04000000
-#define BCHP_XPT_FE_MTSIF_RX0_PKT_BAND0_BAND31_DETECT_BAND_ID26_SHIFT 26
-#define BCHP_XPT_FE_MTSIF_RX0_PKT_BAND0_BAND31_DETECT_BAND_ID26_DEFAULT 0x00000000
-
-/* XPT_FE :: MTSIF_RX0_PKT_BAND0_BAND31_DETECT :: BAND_ID25 [25:25] */
-#define BCHP_XPT_FE_MTSIF_RX0_PKT_BAND0_BAND31_DETECT_BAND_ID25_MASK 0x02000000
-#define BCHP_XPT_FE_MTSIF_RX0_PKT_BAND0_BAND31_DETECT_BAND_ID25_SHIFT 25
-#define BCHP_XPT_FE_MTSIF_RX0_PKT_BAND0_BAND31_DETECT_BAND_ID25_DEFAULT 0x00000000
-
-/* XPT_FE :: MTSIF_RX0_PKT_BAND0_BAND31_DETECT :: BAND_ID24 [24:24] */
-#define BCHP_XPT_FE_MTSIF_RX0_PKT_BAND0_BAND31_DETECT_BAND_ID24_MASK 0x01000000
-#define BCHP_XPT_FE_MTSIF_RX0_PKT_BAND0_BAND31_DETECT_BAND_ID24_SHIFT 24
-#define BCHP_XPT_FE_MTSIF_RX0_PKT_BAND0_BAND31_DETECT_BAND_ID24_DEFAULT 0x00000000
-
-/* XPT_FE :: MTSIF_RX0_PKT_BAND0_BAND31_DETECT :: BAND_ID23 [23:23] */
-#define BCHP_XPT_FE_MTSIF_RX0_PKT_BAND0_BAND31_DETECT_BAND_ID23_MASK 0x00800000
-#define BCHP_XPT_FE_MTSIF_RX0_PKT_BAND0_BAND31_DETECT_BAND_ID23_SHIFT 23
-#define BCHP_XPT_FE_MTSIF_RX0_PKT_BAND0_BAND31_DETECT_BAND_ID23_DEFAULT 0x00000000
-
-/* XPT_FE :: MTSIF_RX0_PKT_BAND0_BAND31_DETECT :: BAND_ID22 [22:22] */
-#define BCHP_XPT_FE_MTSIF_RX0_PKT_BAND0_BAND31_DETECT_BAND_ID22_MASK 0x00400000
-#define BCHP_XPT_FE_MTSIF_RX0_PKT_BAND0_BAND31_DETECT_BAND_ID22_SHIFT 22
-#define BCHP_XPT_FE_MTSIF_RX0_PKT_BAND0_BAND31_DETECT_BAND_ID22_DEFAULT 0x00000000
-
-/* XPT_FE :: MTSIF_RX0_PKT_BAND0_BAND31_DETECT :: BAND_ID21 [21:21] */
-#define BCHP_XPT_FE_MTSIF_RX0_PKT_BAND0_BAND31_DETECT_BAND_ID21_MASK 0x00200000
-#define BCHP_XPT_FE_MTSIF_RX0_PKT_BAND0_BAND31_DETECT_BAND_ID21_SHIFT 21
-#define BCHP_XPT_FE_MTSIF_RX0_PKT_BAND0_BAND31_DETECT_BAND_ID21_DEFAULT 0x00000000
-
-/* XPT_FE :: MTSIF_RX0_PKT_BAND0_BAND31_DETECT :: BAND_ID20 [20:20] */
-#define BCHP_XPT_FE_MTSIF_RX0_PKT_BAND0_BAND31_DETECT_BAND_ID20_MASK 0x00100000
-#define BCHP_XPT_FE_MTSIF_RX0_PKT_BAND0_BAND31_DETECT_BAND_ID20_SHIFT 20
-#define BCHP_XPT_FE_MTSIF_RX0_PKT_BAND0_BAND31_DETECT_BAND_ID20_DEFAULT 0x00000000
-
-/* XPT_FE :: MTSIF_RX0_PKT_BAND0_BAND31_DETECT :: BAND_ID19 [19:19] */
-#define BCHP_XPT_FE_MTSIF_RX0_PKT_BAND0_BAND31_DETECT_BAND_ID19_MASK 0x00080000
-#define BCHP_XPT_FE_MTSIF_RX0_PKT_BAND0_BAND31_DETECT_BAND_ID19_SHIFT 19
-#define BCHP_XPT_FE_MTSIF_RX0_PKT_BAND0_BAND31_DETECT_BAND_ID19_DEFAULT 0x00000000
-
-/* XPT_FE :: MTSIF_RX0_PKT_BAND0_BAND31_DETECT :: BAND_ID18 [18:18] */
-#define BCHP_XPT_FE_MTSIF_RX0_PKT_BAND0_BAND31_DETECT_BAND_ID18_MASK 0x00040000
-#define BCHP_XPT_FE_MTSIF_RX0_PKT_BAND0_BAND31_DETECT_BAND_ID18_SHIFT 18
-#define BCHP_XPT_FE_MTSIF_RX0_PKT_BAND0_BAND31_DETECT_BAND_ID18_DEFAULT 0x00000000
-
-/* XPT_FE :: MTSIF_RX0_PKT_BAND0_BAND31_DETECT :: BAND_ID17 [17:17] */
-#define BCHP_XPT_FE_MTSIF_RX0_PKT_BAND0_BAND31_DETECT_BAND_ID17_MASK 0x00020000
-#define BCHP_XPT_FE_MTSIF_RX0_PKT_BAND0_BAND31_DETECT_BAND_ID17_SHIFT 17
-#define BCHP_XPT_FE_MTSIF_RX0_PKT_BAND0_BAND31_DETECT_BAND_ID17_DEFAULT 0x00000000
-
-/* XPT_FE :: MTSIF_RX0_PKT_BAND0_BAND31_DETECT :: BAND_ID16 [16:16] */
-#define BCHP_XPT_FE_MTSIF_RX0_PKT_BAND0_BAND31_DETECT_BAND_ID16_MASK 0x00010000
-#define BCHP_XPT_FE_MTSIF_RX0_PKT_BAND0_BAND31_DETECT_BAND_ID16_SHIFT 16
-#define BCHP_XPT_FE_MTSIF_RX0_PKT_BAND0_BAND31_DETECT_BAND_ID16_DEFAULT 0x00000000
-
-/* XPT_FE :: MTSIF_RX0_PKT_BAND0_BAND31_DETECT :: BAND_ID15 [15:15] */
-#define BCHP_XPT_FE_MTSIF_RX0_PKT_BAND0_BAND31_DETECT_BAND_ID15_MASK 0x00008000
-#define BCHP_XPT_FE_MTSIF_RX0_PKT_BAND0_BAND31_DETECT_BAND_ID15_SHIFT 15
-#define BCHP_XPT_FE_MTSIF_RX0_PKT_BAND0_BAND31_DETECT_BAND_ID15_DEFAULT 0x00000000
-
-/* XPT_FE :: MTSIF_RX0_PKT_BAND0_BAND31_DETECT :: BAND_ID14 [14:14] */
-#define BCHP_XPT_FE_MTSIF_RX0_PKT_BAND0_BAND31_DETECT_BAND_ID14_MASK 0x00004000
-#define BCHP_XPT_FE_MTSIF_RX0_PKT_BAND0_BAND31_DETECT_BAND_ID14_SHIFT 14
-#define BCHP_XPT_FE_MTSIF_RX0_PKT_BAND0_BAND31_DETECT_BAND_ID14_DEFAULT 0x00000000
-
-/* XPT_FE :: MTSIF_RX0_PKT_BAND0_BAND31_DETECT :: BAND_ID13 [13:13] */
-#define BCHP_XPT_FE_MTSIF_RX0_PKT_BAND0_BAND31_DETECT_BAND_ID13_MASK 0x00002000
-#define BCHP_XPT_FE_MTSIF_RX0_PKT_BAND0_BAND31_DETECT_BAND_ID13_SHIFT 13
-#define BCHP_XPT_FE_MTSIF_RX0_PKT_BAND0_BAND31_DETECT_BAND_ID13_DEFAULT 0x00000000
-
-/* XPT_FE :: MTSIF_RX0_PKT_BAND0_BAND31_DETECT :: BAND_ID12 [12:12] */
-#define BCHP_XPT_FE_MTSIF_RX0_PKT_BAND0_BAND31_DETECT_BAND_ID12_MASK 0x00001000
-#define BCHP_XPT_FE_MTSIF_RX0_PKT_BAND0_BAND31_DETECT_BAND_ID12_SHIFT 12
-#define BCHP_XPT_FE_MTSIF_RX0_PKT_BAND0_BAND31_DETECT_BAND_ID12_DEFAULT 0x00000000
-
-/* XPT_FE :: MTSIF_RX0_PKT_BAND0_BAND31_DETECT :: BAND_ID11 [11:11] */
-#define BCHP_XPT_FE_MTSIF_RX0_PKT_BAND0_BAND31_DETECT_BAND_ID11_MASK 0x00000800
-#define BCHP_XPT_FE_MTSIF_RX0_PKT_BAND0_BAND31_DETECT_BAND_ID11_SHIFT 11
-#define BCHP_XPT_FE_MTSIF_RX0_PKT_BAND0_BAND31_DETECT_BAND_ID11_DEFAULT 0x00000000
-
-/* XPT_FE :: MTSIF_RX0_PKT_BAND0_BAND31_DETECT :: BAND_ID10 [10:10] */
-#define BCHP_XPT_FE_MTSIF_RX0_PKT_BAND0_BAND31_DETECT_BAND_ID10_MASK 0x00000400
-#define BCHP_XPT_FE_MTSIF_RX0_PKT_BAND0_BAND31_DETECT_BAND_ID10_SHIFT 10
-#define BCHP_XPT_FE_MTSIF_RX0_PKT_BAND0_BAND31_DETECT_BAND_ID10_DEFAULT 0x00000000
-
-/* XPT_FE :: MTSIF_RX0_PKT_BAND0_BAND31_DETECT :: BAND_ID9 [09:09] */
-#define BCHP_XPT_FE_MTSIF_RX0_PKT_BAND0_BAND31_DETECT_BAND_ID9_MASK 0x00000200
-#define BCHP_XPT_FE_MTSIF_RX0_PKT_BAND0_BAND31_DETECT_BAND_ID9_SHIFT 9
-#define BCHP_XPT_FE_MTSIF_RX0_PKT_BAND0_BAND31_DETECT_BAND_ID9_DEFAULT 0x00000000
-
-/* XPT_FE :: MTSIF_RX0_PKT_BAND0_BAND31_DETECT :: BAND_ID8 [08:08] */
-#define BCHP_XPT_FE_MTSIF_RX0_PKT_BAND0_BAND31_DETECT_BAND_ID8_MASK 0x00000100
-#define BCHP_XPT_FE_MTSIF_RX0_PKT_BAND0_BAND31_DETECT_BAND_ID8_SHIFT 8
-#define BCHP_XPT_FE_MTSIF_RX0_PKT_BAND0_BAND31_DETECT_BAND_ID8_DEFAULT 0x00000000
-
-/* XPT_FE :: MTSIF_RX0_PKT_BAND0_BAND31_DETECT :: BAND_ID7 [07:07] */
-#define BCHP_XPT_FE_MTSIF_RX0_PKT_BAND0_BAND31_DETECT_BAND_ID7_MASK 0x00000080
-#define BCHP_XPT_FE_MTSIF_RX0_PKT_BAND0_BAND31_DETECT_BAND_ID7_SHIFT 7
-#define BCHP_XPT_FE_MTSIF_RX0_PKT_BAND0_BAND31_DETECT_BAND_ID7_DEFAULT 0x00000000
-
-/* XPT_FE :: MTSIF_RX0_PKT_BAND0_BAND31_DETECT :: BAND_ID6 [06:06] */
-#define BCHP_XPT_FE_MTSIF_RX0_PKT_BAND0_BAND31_DETECT_BAND_ID6_MASK 0x00000040
-#define BCHP_XPT_FE_MTSIF_RX0_PKT_BAND0_BAND31_DETECT_BAND_ID6_SHIFT 6
-#define BCHP_XPT_FE_MTSIF_RX0_PKT_BAND0_BAND31_DETECT_BAND_ID6_DEFAULT 0x00000000
-
-/* XPT_FE :: MTSIF_RX0_PKT_BAND0_BAND31_DETECT :: BAND_ID5 [05:05] */
-#define BCHP_XPT_FE_MTSIF_RX0_PKT_BAND0_BAND31_DETECT_BAND_ID5_MASK 0x00000020
-#define BCHP_XPT_FE_MTSIF_RX0_PKT_BAND0_BAND31_DETECT_BAND_ID5_SHIFT 5
-#define BCHP_XPT_FE_MTSIF_RX0_PKT_BAND0_BAND31_DETECT_BAND_ID5_DEFAULT 0x00000000
-
-/* XPT_FE :: MTSIF_RX0_PKT_BAND0_BAND31_DETECT :: BAND_ID4 [04:04] */
-#define BCHP_XPT_FE_MTSIF_RX0_PKT_BAND0_BAND31_DETECT_BAND_ID4_MASK 0x00000010
-#define BCHP_XPT_FE_MTSIF_RX0_PKT_BAND0_BAND31_DETECT_BAND_ID4_SHIFT 4
-#define BCHP_XPT_FE_MTSIF_RX0_PKT_BAND0_BAND31_DETECT_BAND_ID4_DEFAULT 0x00000000
-
-/* XPT_FE :: MTSIF_RX0_PKT_BAND0_BAND31_DETECT :: BAND_ID3 [03:03] */
-#define BCHP_XPT_FE_MTSIF_RX0_PKT_BAND0_BAND31_DETECT_BAND_ID3_MASK 0x00000008
-#define BCHP_XPT_FE_MTSIF_RX0_PKT_BAND0_BAND31_DETECT_BAND_ID3_SHIFT 3
-#define BCHP_XPT_FE_MTSIF_RX0_PKT_BAND0_BAND31_DETECT_BAND_ID3_DEFAULT 0x00000000
-
-/* XPT_FE :: MTSIF_RX0_PKT_BAND0_BAND31_DETECT :: BAND_ID2 [02:02] */
-#define BCHP_XPT_FE_MTSIF_RX0_PKT_BAND0_BAND31_DETECT_BAND_ID2_MASK 0x00000004
-#define BCHP_XPT_FE_MTSIF_RX0_PKT_BAND0_BAND31_DETECT_BAND_ID2_SHIFT 2
-#define BCHP_XPT_FE_MTSIF_RX0_PKT_BAND0_BAND31_DETECT_BAND_ID2_DEFAULT 0x00000000
-
-/* XPT_FE :: MTSIF_RX0_PKT_BAND0_BAND31_DETECT :: BAND_ID1 [01:01] */
-#define BCHP_XPT_FE_MTSIF_RX0_PKT_BAND0_BAND31_DETECT_BAND_ID1_MASK 0x00000002
-#define BCHP_XPT_FE_MTSIF_RX0_PKT_BAND0_BAND31_DETECT_BAND_ID1_SHIFT 1
-#define BCHP_XPT_FE_MTSIF_RX0_PKT_BAND0_BAND31_DETECT_BAND_ID1_DEFAULT 0x00000000
-
-/* XPT_FE :: MTSIF_RX0_PKT_BAND0_BAND31_DETECT :: BAND_ID0 [00:00] */
-#define BCHP_XPT_FE_MTSIF_RX0_PKT_BAND0_BAND31_DETECT_BAND_ID0_MASK 0x00000001
-#define BCHP_XPT_FE_MTSIF_RX0_PKT_BAND0_BAND31_DETECT_BAND_ID0_SHIFT 0
-#define BCHP_XPT_FE_MTSIF_RX0_PKT_BAND0_BAND31_DETECT_BAND_ID0_DEFAULT 0x00000000
-
-/***************************************************************************
- *MTSIF_RX1_CTRL1 - FE_MTSIF_RX1_CTRL1
- ***************************************************************************/
-/* XPT_FE :: MTSIF_RX1_CTRL1 :: reserved0 [31:09] */
-#define BCHP_XPT_FE_MTSIF_RX1_CTRL1_reserved0_MASK 0xfffffe00
-#define BCHP_XPT_FE_MTSIF_RX1_CTRL1_reserved0_SHIFT 9
-
-/* XPT_FE :: MTSIF_RX1_CTRL1 :: MTSIF_RX_DECRYPTION_ENABLE_STATUS [08:08] */
-#define BCHP_XPT_FE_MTSIF_RX1_CTRL1_MTSIF_RX_DECRYPTION_ENABLE_STATUS_MASK 0x00000100
-#define BCHP_XPT_FE_MTSIF_RX1_CTRL1_MTSIF_RX_DECRYPTION_ENABLE_STATUS_SHIFT 8
-#define BCHP_XPT_FE_MTSIF_RX1_CTRL1_MTSIF_RX_DECRYPTION_ENABLE_STATUS_DEFAULT 0x00000001
-
-/* XPT_FE :: MTSIF_RX1_CTRL1 :: MTSIF_RX_PKT_BAND_DETECT_MODE [07:07] */
-#define BCHP_XPT_FE_MTSIF_RX1_CTRL1_MTSIF_RX_PKT_BAND_DETECT_MODE_MASK 0x00000080
-#define BCHP_XPT_FE_MTSIF_RX1_CTRL1_MTSIF_RX_PKT_BAND_DETECT_MODE_SHIFT 7
-#define BCHP_XPT_FE_MTSIF_RX1_CTRL1_MTSIF_RX_PKT_BAND_DETECT_MODE_DEFAULT 0x00000000
-
-/* XPT_FE :: MTSIF_RX1_CTRL1 :: MTSIF_RX_ERR_RPT_EN [06:06] */
-#define BCHP_XPT_FE_MTSIF_RX1_CTRL1_MTSIF_RX_ERR_RPT_EN_MASK 0x00000040
-#define BCHP_XPT_FE_MTSIF_RX1_CTRL1_MTSIF_RX_ERR_RPT_EN_SHIFT 6
-#define BCHP_XPT_FE_MTSIF_RX1_CTRL1_MTSIF_RX_ERR_RPT_EN_DEFAULT 0x00000000
-
-/* XPT_FE :: MTSIF_RX1_CTRL1 :: MTSIF_RX_IF_WIDTH [05:04] */
-#define BCHP_XPT_FE_MTSIF_RX1_CTRL1_MTSIF_RX_IF_WIDTH_MASK 0x00000030
-#define BCHP_XPT_FE_MTSIF_RX1_CTRL1_MTSIF_RX_IF_WIDTH_SHIFT 4
-#define BCHP_XPT_FE_MTSIF_RX1_CTRL1_MTSIF_RX_IF_WIDTH_DEFAULT 0x00000003
-
-/* XPT_FE :: MTSIF_RX1_CTRL1 :: reserved1 [03:02] */
-#define BCHP_XPT_FE_MTSIF_RX1_CTRL1_reserved1_MASK 0x0000000c
-#define BCHP_XPT_FE_MTSIF_RX1_CTRL1_reserved1_SHIFT 2
-
-/* XPT_FE :: MTSIF_RX1_CTRL1 :: MTSIF_RX_CLOCK_POL_SEL [01:01] */
-#define BCHP_XPT_FE_MTSIF_RX1_CTRL1_MTSIF_RX_CLOCK_POL_SEL_MASK 0x00000002
-#define BCHP_XPT_FE_MTSIF_RX1_CTRL1_MTSIF_RX_CLOCK_POL_SEL_SHIFT 1
-#define BCHP_XPT_FE_MTSIF_RX1_CTRL1_MTSIF_RX_CLOCK_POL_SEL_DEFAULT 0x00000001
-
-/* XPT_FE :: MTSIF_RX1_CTRL1 :: PARSER_ENABLE [00:00] */
-#define BCHP_XPT_FE_MTSIF_RX1_CTRL1_PARSER_ENABLE_MASK 0x00000001
-#define BCHP_XPT_FE_MTSIF_RX1_CTRL1_PARSER_ENABLE_SHIFT 0
-#define BCHP_XPT_FE_MTSIF_RX1_CTRL1_PARSER_ENABLE_DEFAULT 0x00000000
-
-/***************************************************************************
- *MTSIF_RX1_SECRET_WORD - MTSIF RX1 Secret Word Register
- ***************************************************************************/
-/* XPT_FE :: MTSIF_RX1_SECRET_WORD :: SECRET_WORD [31:00] */
-#define BCHP_XPT_FE_MTSIF_RX1_SECRET_WORD_SECRET_WORD_MASK 0xffffffff
-#define BCHP_XPT_FE_MTSIF_RX1_SECRET_WORD_SECRET_WORD_SHIFT 0
-#define BCHP_XPT_FE_MTSIF_RX1_SECRET_WORD_SECRET_WORD_DEFAULT 0x00000000
-
-/***************************************************************************
- *MTSIF_RX1_BAND0_BAND31_ID_DROP - MTSIF RX1 Band0 to Band31 ID Drop Register
- ***************************************************************************/
-/* XPT_FE :: MTSIF_RX1_BAND0_BAND31_ID_DROP :: DROP_EN [31:00] */
-#define BCHP_XPT_FE_MTSIF_RX1_BAND0_BAND31_ID_DROP_DROP_EN_MASK 0xffffffff
-#define BCHP_XPT_FE_MTSIF_RX1_BAND0_BAND31_ID_DROP_DROP_EN_SHIFT 0
-#define BCHP_XPT_FE_MTSIF_RX1_BAND0_BAND31_ID_DROP_DROP_EN_DEFAULT 0x00000000
-
-/***************************************************************************
- *MTSIF_RX1_BAND0_BAND3_ID - MTSIF RX1 Band0 to Band3 ID Register
- ***************************************************************************/
-/* XPT_FE :: MTSIF_RX1_BAND0_BAND3_ID :: reserved0 [31:30] */
-#define BCHP_XPT_FE_MTSIF_RX1_BAND0_BAND3_ID_reserved0_MASK 0xc0000000
-#define BCHP_XPT_FE_MTSIF_RX1_BAND0_BAND3_ID_reserved0_SHIFT 30
-
-/* XPT_FE :: MTSIF_RX1_BAND0_BAND3_ID :: MTSIF_BAND3_BAND_ID [29:24] */
-#define BCHP_XPT_FE_MTSIF_RX1_BAND0_BAND3_ID_MTSIF_BAND3_BAND_ID_MASK 0x3f000000
-#define BCHP_XPT_FE_MTSIF_RX1_BAND0_BAND3_ID_MTSIF_BAND3_BAND_ID_SHIFT 24
-#define BCHP_XPT_FE_MTSIF_RX1_BAND0_BAND3_ID_MTSIF_BAND3_BAND_ID_DEFAULT 0x00000003
-
-/* XPT_FE :: MTSIF_RX1_BAND0_BAND3_ID :: reserved1 [23:22] */
-#define BCHP_XPT_FE_MTSIF_RX1_BAND0_BAND3_ID_reserved1_MASK 0x00c00000
-#define BCHP_XPT_FE_MTSIF_RX1_BAND0_BAND3_ID_reserved1_SHIFT 22
-
-/* XPT_FE :: MTSIF_RX1_BAND0_BAND3_ID :: MTSIF_BAND2_BAND_ID [21:16] */
-#define BCHP_XPT_FE_MTSIF_RX1_BAND0_BAND3_ID_MTSIF_BAND2_BAND_ID_MASK 0x003f0000
-#define BCHP_XPT_FE_MTSIF_RX1_BAND0_BAND3_ID_MTSIF_BAND2_BAND_ID_SHIFT 16
-#define BCHP_XPT_FE_MTSIF_RX1_BAND0_BAND3_ID_MTSIF_BAND2_BAND_ID_DEFAULT 0x00000002
-
-/* XPT_FE :: MTSIF_RX1_BAND0_BAND3_ID :: reserved2 [15:14] */
-#define BCHP_XPT_FE_MTSIF_RX1_BAND0_BAND3_ID_reserved2_MASK 0x0000c000
-#define BCHP_XPT_FE_MTSIF_RX1_BAND0_BAND3_ID_reserved2_SHIFT 14
-
-/* XPT_FE :: MTSIF_RX1_BAND0_BAND3_ID :: MTSIF_BAND1_BAND_ID [13:08] */
-#define BCHP_XPT_FE_MTSIF_RX1_BAND0_BAND3_ID_MTSIF_BAND1_BAND_ID_MASK 0x00003f00
-#define BCHP_XPT_FE_MTSIF_RX1_BAND0_BAND3_ID_MTSIF_BAND1_BAND_ID_SHIFT 8
-#define BCHP_XPT_FE_MTSIF_RX1_BAND0_BAND3_ID_MTSIF_BAND1_BAND_ID_DEFAULT 0x00000001
-
-/* XPT_FE :: MTSIF_RX1_BAND0_BAND3_ID :: reserved3 [07:06] */
-#define BCHP_XPT_FE_MTSIF_RX1_BAND0_BAND3_ID_reserved3_MASK 0x000000c0
-#define BCHP_XPT_FE_MTSIF_RX1_BAND0_BAND3_ID_reserved3_SHIFT 6
-
-/* XPT_FE :: MTSIF_RX1_BAND0_BAND3_ID :: MTSIF_BAND0_BAND_ID [05:00] */
-#define BCHP_XPT_FE_MTSIF_RX1_BAND0_BAND3_ID_MTSIF_BAND0_BAND_ID_MASK 0x0000003f
-#define BCHP_XPT_FE_MTSIF_RX1_BAND0_BAND3_ID_MTSIF_BAND0_BAND_ID_SHIFT 0
-#define BCHP_XPT_FE_MTSIF_RX1_BAND0_BAND3_ID_MTSIF_BAND0_BAND_ID_DEFAULT 0x00000000
-
-/***************************************************************************
- *MTSIF_RX1_BAND4_BAND7_ID - MTSIF RX1 Band4 to Band7 ID Register
- ***************************************************************************/
-/* XPT_FE :: MTSIF_RX1_BAND4_BAND7_ID :: reserved0 [31:30] */
-#define BCHP_XPT_FE_MTSIF_RX1_BAND4_BAND7_ID_reserved0_MASK 0xc0000000
-#define BCHP_XPT_FE_MTSIF_RX1_BAND4_BAND7_ID_reserved0_SHIFT 30
-
-/* XPT_FE :: MTSIF_RX1_BAND4_BAND7_ID :: MTSIF_BAND7_BAND_ID [29:24] */
-#define BCHP_XPT_FE_MTSIF_RX1_BAND4_BAND7_ID_MTSIF_BAND7_BAND_ID_MASK 0x3f000000
-#define BCHP_XPT_FE_MTSIF_RX1_BAND4_BAND7_ID_MTSIF_BAND7_BAND_ID_SHIFT 24
-#define BCHP_XPT_FE_MTSIF_RX1_BAND4_BAND7_ID_MTSIF_BAND7_BAND_ID_DEFAULT 0x00000007
-
-/* XPT_FE :: MTSIF_RX1_BAND4_BAND7_ID :: reserved1 [23:22] */
-#define BCHP_XPT_FE_MTSIF_RX1_BAND4_BAND7_ID_reserved1_MASK 0x00c00000
-#define BCHP_XPT_FE_MTSIF_RX1_BAND4_BAND7_ID_reserved1_SHIFT 22
-
-/* XPT_FE :: MTSIF_RX1_BAND4_BAND7_ID :: MTSIF_BAND6_BAND_ID [21:16] */
-#define BCHP_XPT_FE_MTSIF_RX1_BAND4_BAND7_ID_MTSIF_BAND6_BAND_ID_MASK 0x003f0000
-#define BCHP_XPT_FE_MTSIF_RX1_BAND4_BAND7_ID_MTSIF_BAND6_BAND_ID_SHIFT 16
-#define BCHP_XPT_FE_MTSIF_RX1_BAND4_BAND7_ID_MTSIF_BAND6_BAND_ID_DEFAULT 0x00000006
-
-/* XPT_FE :: MTSIF_RX1_BAND4_BAND7_ID :: reserved2 [15:14] */
-#define BCHP_XPT_FE_MTSIF_RX1_BAND4_BAND7_ID_reserved2_MASK 0x0000c000
-#define BCHP_XPT_FE_MTSIF_RX1_BAND4_BAND7_ID_reserved2_SHIFT 14
-
-/* XPT_FE :: MTSIF_RX1_BAND4_BAND7_ID :: MTSIF_BAND5_BAND_ID [13:08] */
-#define BCHP_XPT_FE_MTSIF_RX1_BAND4_BAND7_ID_MTSIF_BAND5_BAND_ID_MASK 0x00003f00
-#define BCHP_XPT_FE_MTSIF_RX1_BAND4_BAND7_ID_MTSIF_BAND5_BAND_ID_SHIFT 8
-#define BCHP_XPT_FE_MTSIF_RX1_BAND4_BAND7_ID_MTSIF_BAND5_BAND_ID_DEFAULT 0x00000005
-
-/* XPT_FE :: MTSIF_RX1_BAND4_BAND7_ID :: reserved3 [07:06] */
-#define BCHP_XPT_FE_MTSIF_RX1_BAND4_BAND7_ID_reserved3_MASK 0x000000c0
-#define BCHP_XPT_FE_MTSIF_RX1_BAND4_BAND7_ID_reserved3_SHIFT 6
-
-/* XPT_FE :: MTSIF_RX1_BAND4_BAND7_ID :: MTSIF_BAND4_BAND_ID [05:00] */
-#define BCHP_XPT_FE_MTSIF_RX1_BAND4_BAND7_ID_MTSIF_BAND4_BAND_ID_MASK 0x0000003f
-#define BCHP_XPT_FE_MTSIF_RX1_BAND4_BAND7_ID_MTSIF_BAND4_BAND_ID_SHIFT 0
-#define BCHP_XPT_FE_MTSIF_RX1_BAND4_BAND7_ID_MTSIF_BAND4_BAND_ID_DEFAULT 0x00000004
-
-/***************************************************************************
- *MTSIF_RX1_BAND8_BAND11_ID - MTSIF RX1 Band8 to Band11 ID Register
- ***************************************************************************/
-/* XPT_FE :: MTSIF_RX1_BAND8_BAND11_ID :: reserved0 [31:30] */
-#define BCHP_XPT_FE_MTSIF_RX1_BAND8_BAND11_ID_reserved0_MASK 0xc0000000
-#define BCHP_XPT_FE_MTSIF_RX1_BAND8_BAND11_ID_reserved0_SHIFT 30
-
-/* XPT_FE :: MTSIF_RX1_BAND8_BAND11_ID :: MTSIF_BAND11_BAND_ID [29:24] */
-#define BCHP_XPT_FE_MTSIF_RX1_BAND8_BAND11_ID_MTSIF_BAND11_BAND_ID_MASK 0x3f000000
-#define BCHP_XPT_FE_MTSIF_RX1_BAND8_BAND11_ID_MTSIF_BAND11_BAND_ID_SHIFT 24
-#define BCHP_XPT_FE_MTSIF_RX1_BAND8_BAND11_ID_MTSIF_BAND11_BAND_ID_DEFAULT 0x0000000b
-
-/* XPT_FE :: MTSIF_RX1_BAND8_BAND11_ID :: reserved1 [23:22] */
-#define BCHP_XPT_FE_MTSIF_RX1_BAND8_BAND11_ID_reserved1_MASK 0x00c00000
-#define BCHP_XPT_FE_MTSIF_RX1_BAND8_BAND11_ID_reserved1_SHIFT 22
-
-/* XPT_FE :: MTSIF_RX1_BAND8_BAND11_ID :: MTSIF_BAND10_BAND_ID [21:16] */
-#define BCHP_XPT_FE_MTSIF_RX1_BAND8_BAND11_ID_MTSIF_BAND10_BAND_ID_MASK 0x003f0000
-#define BCHP_XPT_FE_MTSIF_RX1_BAND8_BAND11_ID_MTSIF_BAND10_BAND_ID_SHIFT 16
-#define BCHP_XPT_FE_MTSIF_RX1_BAND8_BAND11_ID_MTSIF_BAND10_BAND_ID_DEFAULT 0x0000000a
-
-/* XPT_FE :: MTSIF_RX1_BAND8_BAND11_ID :: reserved2 [15:14] */
-#define BCHP_XPT_FE_MTSIF_RX1_BAND8_BAND11_ID_reserved2_MASK 0x0000c000
-#define BCHP_XPT_FE_MTSIF_RX1_BAND8_BAND11_ID_reserved2_SHIFT 14
-
-/* XPT_FE :: MTSIF_RX1_BAND8_BAND11_ID :: MTSIF_BAND9_BAND_ID [13:08] */
-#define BCHP_XPT_FE_MTSIF_RX1_BAND8_BAND11_ID_MTSIF_BAND9_BAND_ID_MASK 0x00003f00
-#define BCHP_XPT_FE_MTSIF_RX1_BAND8_BAND11_ID_MTSIF_BAND9_BAND_ID_SHIFT 8
-#define BCHP_XPT_FE_MTSIF_RX1_BAND8_BAND11_ID_MTSIF_BAND9_BAND_ID_DEFAULT 0x00000009
-
-/* XPT_FE :: MTSIF_RX1_BAND8_BAND11_ID :: reserved3 [07:06] */
-#define BCHP_XPT_FE_MTSIF_RX1_BAND8_BAND11_ID_reserved3_MASK 0x000000c0
-#define BCHP_XPT_FE_MTSIF_RX1_BAND8_BAND11_ID_reserved3_SHIFT 6
-
-/* XPT_FE :: MTSIF_RX1_BAND8_BAND11_ID :: MTSIF_BAND8_BAND_ID [05:00] */
-#define BCHP_XPT_FE_MTSIF_RX1_BAND8_BAND11_ID_MTSIF_BAND8_BAND_ID_MASK 0x0000003f
-#define BCHP_XPT_FE_MTSIF_RX1_BAND8_BAND11_ID_MTSIF_BAND8_BAND_ID_SHIFT 0
-#define BCHP_XPT_FE_MTSIF_RX1_BAND8_BAND11_ID_MTSIF_BAND8_BAND_ID_DEFAULT 0x00000008
-
-/***************************************************************************
- *MTSIF_RX1_BAND12_BAND15_ID - MTSIF RX1 Band12 to Band15 ID Register
- ***************************************************************************/
-/* XPT_FE :: MTSIF_RX1_BAND12_BAND15_ID :: reserved0 [31:30] */
-#define BCHP_XPT_FE_MTSIF_RX1_BAND12_BAND15_ID_reserved0_MASK 0xc0000000
-#define BCHP_XPT_FE_MTSIF_RX1_BAND12_BAND15_ID_reserved0_SHIFT 30
-
-/* XPT_FE :: MTSIF_RX1_BAND12_BAND15_ID :: MTSIF_BAND15_BAND_ID [29:24] */
-#define BCHP_XPT_FE_MTSIF_RX1_BAND12_BAND15_ID_MTSIF_BAND15_BAND_ID_MASK 0x3f000000
-#define BCHP_XPT_FE_MTSIF_RX1_BAND12_BAND15_ID_MTSIF_BAND15_BAND_ID_SHIFT 24
-#define BCHP_XPT_FE_MTSIF_RX1_BAND12_BAND15_ID_MTSIF_BAND15_BAND_ID_DEFAULT 0x0000000f
-
-/* XPT_FE :: MTSIF_RX1_BAND12_BAND15_ID :: reserved1 [23:22] */
-#define BCHP_XPT_FE_MTSIF_RX1_BAND12_BAND15_ID_reserved1_MASK 0x00c00000
-#define BCHP_XPT_FE_MTSIF_RX1_BAND12_BAND15_ID_reserved1_SHIFT 22
-
-/* XPT_FE :: MTSIF_RX1_BAND12_BAND15_ID :: MTSIF_BAND14_BAND_ID [21:16] */
-#define BCHP_XPT_FE_MTSIF_RX1_BAND12_BAND15_ID_MTSIF_BAND14_BAND_ID_MASK 0x003f0000
-#define BCHP_XPT_FE_MTSIF_RX1_BAND12_BAND15_ID_MTSIF_BAND14_BAND_ID_SHIFT 16
-#define BCHP_XPT_FE_MTSIF_RX1_BAND12_BAND15_ID_MTSIF_BAND14_BAND_ID_DEFAULT 0x0000000e
-
-/* XPT_FE :: MTSIF_RX1_BAND12_BAND15_ID :: reserved2 [15:14] */
-#define BCHP_XPT_FE_MTSIF_RX1_BAND12_BAND15_ID_reserved2_MASK 0x0000c000
-#define BCHP_XPT_FE_MTSIF_RX1_BAND12_BAND15_ID_reserved2_SHIFT 14
-
-/* XPT_FE :: MTSIF_RX1_BAND12_BAND15_ID :: MTSIF_BAND13_BAND_ID [13:08] */
-#define BCHP_XPT_FE_MTSIF_RX1_BAND12_BAND15_ID_MTSIF_BAND13_BAND_ID_MASK 0x00003f00
-#define BCHP_XPT_FE_MTSIF_RX1_BAND12_BAND15_ID_MTSIF_BAND13_BAND_ID_SHIFT 8
-#define BCHP_XPT_FE_MTSIF_RX1_BAND12_BAND15_ID_MTSIF_BAND13_BAND_ID_DEFAULT 0x0000000d
-
-/* XPT_FE :: MTSIF_RX1_BAND12_BAND15_ID :: reserved3 [07:06] */
-#define BCHP_XPT_FE_MTSIF_RX1_BAND12_BAND15_ID_reserved3_MASK 0x000000c0
-#define BCHP_XPT_FE_MTSIF_RX1_BAND12_BAND15_ID_reserved3_SHIFT 6
-
-/* XPT_FE :: MTSIF_RX1_BAND12_BAND15_ID :: MTSIF_BAND12_BAND_ID [05:00] */
-#define BCHP_XPT_FE_MTSIF_RX1_BAND12_BAND15_ID_MTSIF_BAND12_BAND_ID_MASK 0x0000003f
-#define BCHP_XPT_FE_MTSIF_RX1_BAND12_BAND15_ID_MTSIF_BAND12_BAND_ID_SHIFT 0
-#define BCHP_XPT_FE_MTSIF_RX1_BAND12_BAND15_ID_MTSIF_BAND12_BAND_ID_DEFAULT 0x0000000c
-
-/***************************************************************************
- *MTSIF_RX1_BAND16_BAND19_ID - MTSIF RX1 Band16 to Band19 ID Register
- ***************************************************************************/
-/* XPT_FE :: MTSIF_RX1_BAND16_BAND19_ID :: reserved0 [31:30] */
-#define BCHP_XPT_FE_MTSIF_RX1_BAND16_BAND19_ID_reserved0_MASK 0xc0000000
-#define BCHP_XPT_FE_MTSIF_RX1_BAND16_BAND19_ID_reserved0_SHIFT 30
-
-/* XPT_FE :: MTSIF_RX1_BAND16_BAND19_ID :: MTSIF_BAND19_BAND_ID [29:24] */
-#define BCHP_XPT_FE_MTSIF_RX1_BAND16_BAND19_ID_MTSIF_BAND19_BAND_ID_MASK 0x3f000000
-#define BCHP_XPT_FE_MTSIF_RX1_BAND16_BAND19_ID_MTSIF_BAND19_BAND_ID_SHIFT 24
-#define BCHP_XPT_FE_MTSIF_RX1_BAND16_BAND19_ID_MTSIF_BAND19_BAND_ID_DEFAULT 0x00000013
-
-/* XPT_FE :: MTSIF_RX1_BAND16_BAND19_ID :: reserved1 [23:22] */
-#define BCHP_XPT_FE_MTSIF_RX1_BAND16_BAND19_ID_reserved1_MASK 0x00c00000
-#define BCHP_XPT_FE_MTSIF_RX1_BAND16_BAND19_ID_reserved1_SHIFT 22
-
-/* XPT_FE :: MTSIF_RX1_BAND16_BAND19_ID :: MTSIF_BAND18_BAND_ID [21:16] */
-#define BCHP_XPT_FE_MTSIF_RX1_BAND16_BAND19_ID_MTSIF_BAND18_BAND_ID_MASK 0x003f0000
-#define BCHP_XPT_FE_MTSIF_RX1_BAND16_BAND19_ID_MTSIF_BAND18_BAND_ID_SHIFT 16
-#define BCHP_XPT_FE_MTSIF_RX1_BAND16_BAND19_ID_MTSIF_BAND18_BAND_ID_DEFAULT 0x00000012
-
-/* XPT_FE :: MTSIF_RX1_BAND16_BAND19_ID :: reserved2 [15:14] */
-#define BCHP_XPT_FE_MTSIF_RX1_BAND16_BAND19_ID_reserved2_MASK 0x0000c000
-#define BCHP_XPT_FE_MTSIF_RX1_BAND16_BAND19_ID_reserved2_SHIFT 14
-
-/* XPT_FE :: MTSIF_RX1_BAND16_BAND19_ID :: MTSIF_BAND17_BAND_ID [13:08] */
-#define BCHP_XPT_FE_MTSIF_RX1_BAND16_BAND19_ID_MTSIF_BAND17_BAND_ID_MASK 0x00003f00
-#define BCHP_XPT_FE_MTSIF_RX1_BAND16_BAND19_ID_MTSIF_BAND17_BAND_ID_SHIFT 8
-#define BCHP_XPT_FE_MTSIF_RX1_BAND16_BAND19_ID_MTSIF_BAND17_BAND_ID_DEFAULT 0x00000011
-
-/* XPT_FE :: MTSIF_RX1_BAND16_BAND19_ID :: reserved3 [07:06] */
-#define BCHP_XPT_FE_MTSIF_RX1_BAND16_BAND19_ID_reserved3_MASK 0x000000c0
-#define BCHP_XPT_FE_MTSIF_RX1_BAND16_BAND19_ID_reserved3_SHIFT 6
-
-/* XPT_FE :: MTSIF_RX1_BAND16_BAND19_ID :: MTSIF_BAND16_BAND_ID [05:00] */
-#define BCHP_XPT_FE_MTSIF_RX1_BAND16_BAND19_ID_MTSIF_BAND16_BAND_ID_MASK 0x0000003f
-#define BCHP_XPT_FE_MTSIF_RX1_BAND16_BAND19_ID_MTSIF_BAND16_BAND_ID_SHIFT 0
-#define BCHP_XPT_FE_MTSIF_RX1_BAND16_BAND19_ID_MTSIF_BAND16_BAND_ID_DEFAULT 0x00000010
-
-/***************************************************************************
- *MTSIF_RX1_BAND20_BAND23_ID - MTSIF RX1 Band20 to Band23 ID Register
- ***************************************************************************/
-/* XPT_FE :: MTSIF_RX1_BAND20_BAND23_ID :: reserved0 [31:30] */
-#define BCHP_XPT_FE_MTSIF_RX1_BAND20_BAND23_ID_reserved0_MASK 0xc0000000
-#define BCHP_XPT_FE_MTSIF_RX1_BAND20_BAND23_ID_reserved0_SHIFT 30
-
-/* XPT_FE :: MTSIF_RX1_BAND20_BAND23_ID :: MTSIF_BAND23_BAND_ID [29:24] */
-#define BCHP_XPT_FE_MTSIF_RX1_BAND20_BAND23_ID_MTSIF_BAND23_BAND_ID_MASK 0x3f000000
-#define BCHP_XPT_FE_MTSIF_RX1_BAND20_BAND23_ID_MTSIF_BAND23_BAND_ID_SHIFT 24
-#define BCHP_XPT_FE_MTSIF_RX1_BAND20_BAND23_ID_MTSIF_BAND23_BAND_ID_DEFAULT 0x00000017
-
-/* XPT_FE :: MTSIF_RX1_BAND20_BAND23_ID :: reserved1 [23:22] */
-#define BCHP_XPT_FE_MTSIF_RX1_BAND20_BAND23_ID_reserved1_MASK 0x00c00000
-#define BCHP_XPT_FE_MTSIF_RX1_BAND20_BAND23_ID_reserved1_SHIFT 22
-
-/* XPT_FE :: MTSIF_RX1_BAND20_BAND23_ID :: MTSIF_BAND22_BAND_ID [21:16] */
-#define BCHP_XPT_FE_MTSIF_RX1_BAND20_BAND23_ID_MTSIF_BAND22_BAND_ID_MASK 0x003f0000
-#define BCHP_XPT_FE_MTSIF_RX1_BAND20_BAND23_ID_MTSIF_BAND22_BAND_ID_SHIFT 16
-#define BCHP_XPT_FE_MTSIF_RX1_BAND20_BAND23_ID_MTSIF_BAND22_BAND_ID_DEFAULT 0x00000016
-
-/* XPT_FE :: MTSIF_RX1_BAND20_BAND23_ID :: reserved2 [15:14] */
-#define BCHP_XPT_FE_MTSIF_RX1_BAND20_BAND23_ID_reserved2_MASK 0x0000c000
-#define BCHP_XPT_FE_MTSIF_RX1_BAND20_BAND23_ID_reserved2_SHIFT 14
-
-/* XPT_FE :: MTSIF_RX1_BAND20_BAND23_ID :: MTSIF_BAND21_BAND_ID [13:08] */
-#define BCHP_XPT_FE_MTSIF_RX1_BAND20_BAND23_ID_MTSIF_BAND21_BAND_ID_MASK 0x00003f00
-#define BCHP_XPT_FE_MTSIF_RX1_BAND20_BAND23_ID_MTSIF_BAND21_BAND_ID_SHIFT 8
-#define BCHP_XPT_FE_MTSIF_RX1_BAND20_BAND23_ID_MTSIF_BAND21_BAND_ID_DEFAULT 0x00000015
-
-/* XPT_FE :: MTSIF_RX1_BAND20_BAND23_ID :: reserved3 [07:06] */
-#define BCHP_XPT_FE_MTSIF_RX1_BAND20_BAND23_ID_reserved3_MASK 0x000000c0
-#define BCHP_XPT_FE_MTSIF_RX1_BAND20_BAND23_ID_reserved3_SHIFT 6
-
-/* XPT_FE :: MTSIF_RX1_BAND20_BAND23_ID :: MTSIF_BAND20_BAND_ID [05:00] */
-#define BCHP_XPT_FE_MTSIF_RX1_BAND20_BAND23_ID_MTSIF_BAND20_BAND_ID_MASK 0x0000003f
-#define BCHP_XPT_FE_MTSIF_RX1_BAND20_BAND23_ID_MTSIF_BAND20_BAND_ID_SHIFT 0
-#define BCHP_XPT_FE_MTSIF_RX1_BAND20_BAND23_ID_MTSIF_BAND20_BAND_ID_DEFAULT 0x00000014
-
-/***************************************************************************
- *MTSIF_RX1_BAND24_BAND27_ID - MTSIF RX1 Band24 to Band27 ID Register
- ***************************************************************************/
-/* XPT_FE :: MTSIF_RX1_BAND24_BAND27_ID :: reserved0 [31:30] */
-#define BCHP_XPT_FE_MTSIF_RX1_BAND24_BAND27_ID_reserved0_MASK 0xc0000000
-#define BCHP_XPT_FE_MTSIF_RX1_BAND24_BAND27_ID_reserved0_SHIFT 30
-
-/* XPT_FE :: MTSIF_RX1_BAND24_BAND27_ID :: MTSIF_BAND27_BAND_ID [29:24] */
-#define BCHP_XPT_FE_MTSIF_RX1_BAND24_BAND27_ID_MTSIF_BAND27_BAND_ID_MASK 0x3f000000
-#define BCHP_XPT_FE_MTSIF_RX1_BAND24_BAND27_ID_MTSIF_BAND27_BAND_ID_SHIFT 24
-#define BCHP_XPT_FE_MTSIF_RX1_BAND24_BAND27_ID_MTSIF_BAND27_BAND_ID_DEFAULT 0x0000001b
-
-/* XPT_FE :: MTSIF_RX1_BAND24_BAND27_ID :: reserved1 [23:22] */
-#define BCHP_XPT_FE_MTSIF_RX1_BAND24_BAND27_ID_reserved1_MASK 0x00c00000
-#define BCHP_XPT_FE_MTSIF_RX1_BAND24_BAND27_ID_reserved1_SHIFT 22
-
-/* XPT_FE :: MTSIF_RX1_BAND24_BAND27_ID :: MTSIF_BAND26_BAND_ID [21:16] */
-#define BCHP_XPT_FE_MTSIF_RX1_BAND24_BAND27_ID_MTSIF_BAND26_BAND_ID_MASK 0x003f0000
-#define BCHP_XPT_FE_MTSIF_RX1_BAND24_BAND27_ID_MTSIF_BAND26_BAND_ID_SHIFT 16
-#define BCHP_XPT_FE_MTSIF_RX1_BAND24_BAND27_ID_MTSIF_BAND26_BAND_ID_DEFAULT 0x0000001a
-
-/* XPT_FE :: MTSIF_RX1_BAND24_BAND27_ID :: reserved2 [15:14] */
-#define BCHP_XPT_FE_MTSIF_RX1_BAND24_BAND27_ID_reserved2_MASK 0x0000c000
-#define BCHP_XPT_FE_MTSIF_RX1_BAND24_BAND27_ID_reserved2_SHIFT 14
-
-/* XPT_FE :: MTSIF_RX1_BAND24_BAND27_ID :: MTSIF_BAND25_BAND_ID [13:08] */
-#define BCHP_XPT_FE_MTSIF_RX1_BAND24_BAND27_ID_MTSIF_BAND25_BAND_ID_MASK 0x00003f00
-#define BCHP_XPT_FE_MTSIF_RX1_BAND24_BAND27_ID_MTSIF_BAND25_BAND_ID_SHIFT 8
-#define BCHP_XPT_FE_MTSIF_RX1_BAND24_BAND27_ID_MTSIF_BAND25_BAND_ID_DEFAULT 0x00000019
-
-/* XPT_FE :: MTSIF_RX1_BAND24_BAND27_ID :: reserved3 [07:06] */
-#define BCHP_XPT_FE_MTSIF_RX1_BAND24_BAND27_ID_reserved3_MASK 0x000000c0
-#define BCHP_XPT_FE_MTSIF_RX1_BAND24_BAND27_ID_reserved3_SHIFT 6
-
-/* XPT_FE :: MTSIF_RX1_BAND24_BAND27_ID :: MTSIF_BAND24_BAND_ID [05:00] */
-#define BCHP_XPT_FE_MTSIF_RX1_BAND24_BAND27_ID_MTSIF_BAND24_BAND_ID_MASK 0x0000003f
-#define BCHP_XPT_FE_MTSIF_RX1_BAND24_BAND27_ID_MTSIF_BAND24_BAND_ID_SHIFT 0
-#define BCHP_XPT_FE_MTSIF_RX1_BAND24_BAND27_ID_MTSIF_BAND24_BAND_ID_DEFAULT 0x00000018
-
-/***************************************************************************
- *MTSIF_RX1_BAND28_BAND31_ID - MTSIF RX1 Band28 to Band31 ID Register
- ***************************************************************************/
-/* XPT_FE :: MTSIF_RX1_BAND28_BAND31_ID :: reserved0 [31:30] */
-#define BCHP_XPT_FE_MTSIF_RX1_BAND28_BAND31_ID_reserved0_MASK 0xc0000000
-#define BCHP_XPT_FE_MTSIF_RX1_BAND28_BAND31_ID_reserved0_SHIFT 30
-
-/* XPT_FE :: MTSIF_RX1_BAND28_BAND31_ID :: MTSIF_BAND31_BAND_ID [29:24] */
-#define BCHP_XPT_FE_MTSIF_RX1_BAND28_BAND31_ID_MTSIF_BAND31_BAND_ID_MASK 0x3f000000
-#define BCHP_XPT_FE_MTSIF_RX1_BAND28_BAND31_ID_MTSIF_BAND31_BAND_ID_SHIFT 24
-#define BCHP_XPT_FE_MTSIF_RX1_BAND28_BAND31_ID_MTSIF_BAND31_BAND_ID_DEFAULT 0x0000001f
-
-/* XPT_FE :: MTSIF_RX1_BAND28_BAND31_ID :: reserved1 [23:22] */
-#define BCHP_XPT_FE_MTSIF_RX1_BAND28_BAND31_ID_reserved1_MASK 0x00c00000
-#define BCHP_XPT_FE_MTSIF_RX1_BAND28_BAND31_ID_reserved1_SHIFT 22
-
-/* XPT_FE :: MTSIF_RX1_BAND28_BAND31_ID :: MTSIF_BAND30_BAND_ID [21:16] */
-#define BCHP_XPT_FE_MTSIF_RX1_BAND28_BAND31_ID_MTSIF_BAND30_BAND_ID_MASK 0x003f0000
-#define BCHP_XPT_FE_MTSIF_RX1_BAND28_BAND31_ID_MTSIF_BAND30_BAND_ID_SHIFT 16
-#define BCHP_XPT_FE_MTSIF_RX1_BAND28_BAND31_ID_MTSIF_BAND30_BAND_ID_DEFAULT 0x0000001e
-
-/* XPT_FE :: MTSIF_RX1_BAND28_BAND31_ID :: reserved2 [15:14] */
-#define BCHP_XPT_FE_MTSIF_RX1_BAND28_BAND31_ID_reserved2_MASK 0x0000c000
-#define BCHP_XPT_FE_MTSIF_RX1_BAND28_BAND31_ID_reserved2_SHIFT 14
-
-/* XPT_FE :: MTSIF_RX1_BAND28_BAND31_ID :: MTSIF_BAND29_BAND_ID [13:08] */
-#define BCHP_XPT_FE_MTSIF_RX1_BAND28_BAND31_ID_MTSIF_BAND29_BAND_ID_MASK 0x00003f00
-#define BCHP_XPT_FE_MTSIF_RX1_BAND28_BAND31_ID_MTSIF_BAND29_BAND_ID_SHIFT 8
-#define BCHP_XPT_FE_MTSIF_RX1_BAND28_BAND31_ID_MTSIF_BAND29_BAND_ID_DEFAULT 0x0000001d
-
-/* XPT_FE :: MTSIF_RX1_BAND28_BAND31_ID :: reserved3 [07:06] */
-#define BCHP_XPT_FE_MTSIF_RX1_BAND28_BAND31_ID_reserved3_MASK 0x000000c0
-#define BCHP_XPT_FE_MTSIF_RX1_BAND28_BAND31_ID_reserved3_SHIFT 6
-
-/* XPT_FE :: MTSIF_RX1_BAND28_BAND31_ID :: MTSIF_BAND28_BAND_ID [05:00] */
-#define BCHP_XPT_FE_MTSIF_RX1_BAND28_BAND31_ID_MTSIF_BAND28_BAND_ID_MASK 0x0000003f
-#define BCHP_XPT_FE_MTSIF_RX1_BAND28_BAND31_ID_MTSIF_BAND28_BAND_ID_SHIFT 0
-#define BCHP_XPT_FE_MTSIF_RX1_BAND28_BAND31_ID_MTSIF_BAND28_BAND_ID_DEFAULT 0x0000001c
-
-/***************************************************************************
- *MTSIF_RX1_BAND32_BAND35_ID - MTSIF RX1 Band32 to Band35 ID Register
- ***************************************************************************/
-/* XPT_FE :: MTSIF_RX1_BAND32_BAND35_ID :: reserved0 [31:30] */
-#define BCHP_XPT_FE_MTSIF_RX1_BAND32_BAND35_ID_reserved0_MASK 0xc0000000
-#define BCHP_XPT_FE_MTSIF_RX1_BAND32_BAND35_ID_reserved0_SHIFT 30
-
-/* XPT_FE :: MTSIF_RX1_BAND32_BAND35_ID :: MTSIF_BAND35_BAND_ID [29:24] */
-#define BCHP_XPT_FE_MTSIF_RX1_BAND32_BAND35_ID_MTSIF_BAND35_BAND_ID_MASK 0x3f000000
-#define BCHP_XPT_FE_MTSIF_RX1_BAND32_BAND35_ID_MTSIF_BAND35_BAND_ID_SHIFT 24
-#define BCHP_XPT_FE_MTSIF_RX1_BAND32_BAND35_ID_MTSIF_BAND35_BAND_ID_DEFAULT 0x00000023
-
-/* XPT_FE :: MTSIF_RX1_BAND32_BAND35_ID :: reserved1 [23:22] */
-#define BCHP_XPT_FE_MTSIF_RX1_BAND32_BAND35_ID_reserved1_MASK 0x00c00000
-#define BCHP_XPT_FE_MTSIF_RX1_BAND32_BAND35_ID_reserved1_SHIFT 22
-
-/* XPT_FE :: MTSIF_RX1_BAND32_BAND35_ID :: MTSIF_BAND34_BAND_ID [21:16] */
-#define BCHP_XPT_FE_MTSIF_RX1_BAND32_BAND35_ID_MTSIF_BAND34_BAND_ID_MASK 0x003f0000
-#define BCHP_XPT_FE_MTSIF_RX1_BAND32_BAND35_ID_MTSIF_BAND34_BAND_ID_SHIFT 16
-#define BCHP_XPT_FE_MTSIF_RX1_BAND32_BAND35_ID_MTSIF_BAND34_BAND_ID_DEFAULT 0x00000022
-
-/* XPT_FE :: MTSIF_RX1_BAND32_BAND35_ID :: reserved2 [15:14] */
-#define BCHP_XPT_FE_MTSIF_RX1_BAND32_BAND35_ID_reserved2_MASK 0x0000c000
-#define BCHP_XPT_FE_MTSIF_RX1_BAND32_BAND35_ID_reserved2_SHIFT 14
-
-/* XPT_FE :: MTSIF_RX1_BAND32_BAND35_ID :: MTSIF_BAND33_BAND_ID [13:08] */
-#define BCHP_XPT_FE_MTSIF_RX1_BAND32_BAND35_ID_MTSIF_BAND33_BAND_ID_MASK 0x00003f00
-#define BCHP_XPT_FE_MTSIF_RX1_BAND32_BAND35_ID_MTSIF_BAND33_BAND_ID_SHIFT 8
-#define BCHP_XPT_FE_MTSIF_RX1_BAND32_BAND35_ID_MTSIF_BAND33_BAND_ID_DEFAULT 0x00000021
-
-/* XPT_FE :: MTSIF_RX1_BAND32_BAND35_ID :: reserved3 [07:06] */
-#define BCHP_XPT_FE_MTSIF_RX1_BAND32_BAND35_ID_reserved3_MASK 0x000000c0
-#define BCHP_XPT_FE_MTSIF_RX1_BAND32_BAND35_ID_reserved3_SHIFT 6
-
-/* XPT_FE :: MTSIF_RX1_BAND32_BAND35_ID :: MTSIF_BAND32_BAND_ID [05:00] */
-#define BCHP_XPT_FE_MTSIF_RX1_BAND32_BAND35_ID_MTSIF_BAND32_BAND_ID_MASK 0x0000003f
-#define BCHP_XPT_FE_MTSIF_RX1_BAND32_BAND35_ID_MTSIF_BAND32_BAND_ID_SHIFT 0
-#define BCHP_XPT_FE_MTSIF_RX1_BAND32_BAND35_ID_MTSIF_BAND32_BAND_ID_DEFAULT 0x00000020
-
-/***************************************************************************
- *MTSIF_RX1_BAND36_BAND39_ID - MTSIF RX1 Band36 to Band39 ID Register
- ***************************************************************************/
-/* XPT_FE :: MTSIF_RX1_BAND36_BAND39_ID :: reserved0 [31:30] */
-#define BCHP_XPT_FE_MTSIF_RX1_BAND36_BAND39_ID_reserved0_MASK 0xc0000000
-#define BCHP_XPT_FE_MTSIF_RX1_BAND36_BAND39_ID_reserved0_SHIFT 30
-
-/* XPT_FE :: MTSIF_RX1_BAND36_BAND39_ID :: MTSIF_BAND39_BAND_ID [29:24] */
-#define BCHP_XPT_FE_MTSIF_RX1_BAND36_BAND39_ID_MTSIF_BAND39_BAND_ID_MASK 0x3f000000
-#define BCHP_XPT_FE_MTSIF_RX1_BAND36_BAND39_ID_MTSIF_BAND39_BAND_ID_SHIFT 24
-#define BCHP_XPT_FE_MTSIF_RX1_BAND36_BAND39_ID_MTSIF_BAND39_BAND_ID_DEFAULT 0x00000027
-
-/* XPT_FE :: MTSIF_RX1_BAND36_BAND39_ID :: reserved1 [23:22] */
-#define BCHP_XPT_FE_MTSIF_RX1_BAND36_BAND39_ID_reserved1_MASK 0x00c00000
-#define BCHP_XPT_FE_MTSIF_RX1_BAND36_BAND39_ID_reserved1_SHIFT 22
-
-/* XPT_FE :: MTSIF_RX1_BAND36_BAND39_ID :: MTSIF_BAND38_BAND_ID [21:16] */
-#define BCHP_XPT_FE_MTSIF_RX1_BAND36_BAND39_ID_MTSIF_BAND38_BAND_ID_MASK 0x003f0000
-#define BCHP_XPT_FE_MTSIF_RX1_BAND36_BAND39_ID_MTSIF_BAND38_BAND_ID_SHIFT 16
-#define BCHP_XPT_FE_MTSIF_RX1_BAND36_BAND39_ID_MTSIF_BAND38_BAND_ID_DEFAULT 0x00000026
-
-/* XPT_FE :: MTSIF_RX1_BAND36_BAND39_ID :: reserved2 [15:14] */
-#define BCHP_XPT_FE_MTSIF_RX1_BAND36_BAND39_ID_reserved2_MASK 0x0000c000
-#define BCHP_XPT_FE_MTSIF_RX1_BAND36_BAND39_ID_reserved2_SHIFT 14
-
-/* XPT_FE :: MTSIF_RX1_BAND36_BAND39_ID :: MTSIF_BAND37_BAND_ID [13:08] */
-#define BCHP_XPT_FE_MTSIF_RX1_BAND36_BAND39_ID_MTSIF_BAND37_BAND_ID_MASK 0x00003f00
-#define BCHP_XPT_FE_MTSIF_RX1_BAND36_BAND39_ID_MTSIF_BAND37_BAND_ID_SHIFT 8
-#define BCHP_XPT_FE_MTSIF_RX1_BAND36_BAND39_ID_MTSIF_BAND37_BAND_ID_DEFAULT 0x00000025
-
-/* XPT_FE :: MTSIF_RX1_BAND36_BAND39_ID :: reserved3 [07:06] */
-#define BCHP_XPT_FE_MTSIF_RX1_BAND36_BAND39_ID_reserved3_MASK 0x000000c0
-#define BCHP_XPT_FE_MTSIF_RX1_BAND36_BAND39_ID_reserved3_SHIFT 6
-
-/* XPT_FE :: MTSIF_RX1_BAND36_BAND39_ID :: MTSIF_BAND36_BAND_ID [05:00] */
-#define BCHP_XPT_FE_MTSIF_RX1_BAND36_BAND39_ID_MTSIF_BAND36_BAND_ID_MASK 0x0000003f
-#define BCHP_XPT_FE_MTSIF_RX1_BAND36_BAND39_ID_MTSIF_BAND36_BAND_ID_SHIFT 0
-#define BCHP_XPT_FE_MTSIF_RX1_BAND36_BAND39_ID_MTSIF_BAND36_BAND_ID_DEFAULT 0x00000024
-
-/***************************************************************************
- *MTSIF_RX1_BAND40_BAND43_ID - MTSIF RX1 Band40 to Band43 ID Register
- ***************************************************************************/
-/* XPT_FE :: MTSIF_RX1_BAND40_BAND43_ID :: reserved0 [31:30] */
-#define BCHP_XPT_FE_MTSIF_RX1_BAND40_BAND43_ID_reserved0_MASK 0xc0000000
-#define BCHP_XPT_FE_MTSIF_RX1_BAND40_BAND43_ID_reserved0_SHIFT 30
-
-/* XPT_FE :: MTSIF_RX1_BAND40_BAND43_ID :: MTSIF_BAND43_BAND_ID [29:24] */
-#define BCHP_XPT_FE_MTSIF_RX1_BAND40_BAND43_ID_MTSIF_BAND43_BAND_ID_MASK 0x3f000000
-#define BCHP_XPT_FE_MTSIF_RX1_BAND40_BAND43_ID_MTSIF_BAND43_BAND_ID_SHIFT 24
-#define BCHP_XPT_FE_MTSIF_RX1_BAND40_BAND43_ID_MTSIF_BAND43_BAND_ID_DEFAULT 0x0000002b
-
-/* XPT_FE :: MTSIF_RX1_BAND40_BAND43_ID :: reserved1 [23:22] */
-#define BCHP_XPT_FE_MTSIF_RX1_BAND40_BAND43_ID_reserved1_MASK 0x00c00000
-#define BCHP_XPT_FE_MTSIF_RX1_BAND40_BAND43_ID_reserved1_SHIFT 22
-
-/* XPT_FE :: MTSIF_RX1_BAND40_BAND43_ID :: MTSIF_BAND42_BAND_ID [21:16] */
-#define BCHP_XPT_FE_MTSIF_RX1_BAND40_BAND43_ID_MTSIF_BAND42_BAND_ID_MASK 0x003f0000
-#define BCHP_XPT_FE_MTSIF_RX1_BAND40_BAND43_ID_MTSIF_BAND42_BAND_ID_SHIFT 16
-#define BCHP_XPT_FE_MTSIF_RX1_BAND40_BAND43_ID_MTSIF_BAND42_BAND_ID_DEFAULT 0x0000002a
-
-/* XPT_FE :: MTSIF_RX1_BAND40_BAND43_ID :: reserved2 [15:14] */
-#define BCHP_XPT_FE_MTSIF_RX1_BAND40_BAND43_ID_reserved2_MASK 0x0000c000
-#define BCHP_XPT_FE_MTSIF_RX1_BAND40_BAND43_ID_reserved2_SHIFT 14
-
-/* XPT_FE :: MTSIF_RX1_BAND40_BAND43_ID :: MTSIF_BAND41_BAND_ID [13:08] */
-#define BCHP_XPT_FE_MTSIF_RX1_BAND40_BAND43_ID_MTSIF_BAND41_BAND_ID_MASK 0x00003f00
-#define BCHP_XPT_FE_MTSIF_RX1_BAND40_BAND43_ID_MTSIF_BAND41_BAND_ID_SHIFT 8
-#define BCHP_XPT_FE_MTSIF_RX1_BAND40_BAND43_ID_MTSIF_BAND41_BAND_ID_DEFAULT 0x00000029
-
-/* XPT_FE :: MTSIF_RX1_BAND40_BAND43_ID :: reserved3 [07:06] */
-#define BCHP_XPT_FE_MTSIF_RX1_BAND40_BAND43_ID_reserved3_MASK 0x000000c0
-#define BCHP_XPT_FE_MTSIF_RX1_BAND40_BAND43_ID_reserved3_SHIFT 6
-
-/* XPT_FE :: MTSIF_RX1_BAND40_BAND43_ID :: MTSIF_BAND40_BAND_ID [05:00] */
-#define BCHP_XPT_FE_MTSIF_RX1_BAND40_BAND43_ID_MTSIF_BAND40_BAND_ID_MASK 0x0000003f
-#define BCHP_XPT_FE_MTSIF_RX1_BAND40_BAND43_ID_MTSIF_BAND40_BAND_ID_SHIFT 0
-#define BCHP_XPT_FE_MTSIF_RX1_BAND40_BAND43_ID_MTSIF_BAND40_BAND_ID_DEFAULT 0x00000028
-
-/***************************************************************************
- *MTSIF_RX1_BAND44_BAND47_ID - MTSIF RX1 Band44 to Band47 ID Register
- ***************************************************************************/
-/* XPT_FE :: MTSIF_RX1_BAND44_BAND47_ID :: reserved0 [31:30] */
-#define BCHP_XPT_FE_MTSIF_RX1_BAND44_BAND47_ID_reserved0_MASK 0xc0000000
-#define BCHP_XPT_FE_MTSIF_RX1_BAND44_BAND47_ID_reserved0_SHIFT 30
-
-/* XPT_FE :: MTSIF_RX1_BAND44_BAND47_ID :: MTSIF_BAND47_BAND_ID [29:24] */
-#define BCHP_XPT_FE_MTSIF_RX1_BAND44_BAND47_ID_MTSIF_BAND47_BAND_ID_MASK 0x3f000000
-#define BCHP_XPT_FE_MTSIF_RX1_BAND44_BAND47_ID_MTSIF_BAND47_BAND_ID_SHIFT 24
-#define BCHP_XPT_FE_MTSIF_RX1_BAND44_BAND47_ID_MTSIF_BAND47_BAND_ID_DEFAULT 0x0000002f
-
-/* XPT_FE :: MTSIF_RX1_BAND44_BAND47_ID :: reserved1 [23:22] */
-#define BCHP_XPT_FE_MTSIF_RX1_BAND44_BAND47_ID_reserved1_MASK 0x00c00000
-#define BCHP_XPT_FE_MTSIF_RX1_BAND44_BAND47_ID_reserved1_SHIFT 22
-
-/* XPT_FE :: MTSIF_RX1_BAND44_BAND47_ID :: MTSIF_BAND46_BAND_ID [21:16] */
-#define BCHP_XPT_FE_MTSIF_RX1_BAND44_BAND47_ID_MTSIF_BAND46_BAND_ID_MASK 0x003f0000
-#define BCHP_XPT_FE_MTSIF_RX1_BAND44_BAND47_ID_MTSIF_BAND46_BAND_ID_SHIFT 16
-#define BCHP_XPT_FE_MTSIF_RX1_BAND44_BAND47_ID_MTSIF_BAND46_BAND_ID_DEFAULT 0x0000002e
-
-/* XPT_FE :: MTSIF_RX1_BAND44_BAND47_ID :: reserved2 [15:14] */
-#define BCHP_XPT_FE_MTSIF_RX1_BAND44_BAND47_ID_reserved2_MASK 0x0000c000
-#define BCHP_XPT_FE_MTSIF_RX1_BAND44_BAND47_ID_reserved2_SHIFT 14
-
-/* XPT_FE :: MTSIF_RX1_BAND44_BAND47_ID :: MTSIF_BAND45_BAND_ID [13:08] */
-#define BCHP_XPT_FE_MTSIF_RX1_BAND44_BAND47_ID_MTSIF_BAND45_BAND_ID_MASK 0x00003f00
-#define BCHP_XPT_FE_MTSIF_RX1_BAND44_BAND47_ID_MTSIF_BAND45_BAND_ID_SHIFT 8
-#define BCHP_XPT_FE_MTSIF_RX1_BAND44_BAND47_ID_MTSIF_BAND45_BAND_ID_DEFAULT 0x0000002d
-
-/* XPT_FE :: MTSIF_RX1_BAND44_BAND47_ID :: reserved3 [07:06] */
-#define BCHP_XPT_FE_MTSIF_RX1_BAND44_BAND47_ID_reserved3_MASK 0x000000c0
-#define BCHP_XPT_FE_MTSIF_RX1_BAND44_BAND47_ID_reserved3_SHIFT 6
-
-/* XPT_FE :: MTSIF_RX1_BAND44_BAND47_ID :: MTSIF_BAND44_BAND_ID [05:00] */
-#define BCHP_XPT_FE_MTSIF_RX1_BAND44_BAND47_ID_MTSIF_BAND44_BAND_ID_MASK 0x0000003f
-#define BCHP_XPT_FE_MTSIF_RX1_BAND44_BAND47_ID_MTSIF_BAND44_BAND_ID_SHIFT 0
-#define BCHP_XPT_FE_MTSIF_RX1_BAND44_BAND47_ID_MTSIF_BAND44_BAND_ID_DEFAULT 0x0000002c
-
-/***************************************************************************
- *MTSIF_RX1_BAND48_BAND51_ID - MTSIF RX1 Band48 to Band51 ID Register
- ***************************************************************************/
-/* XPT_FE :: MTSIF_RX1_BAND48_BAND51_ID :: reserved0 [31:30] */
-#define BCHP_XPT_FE_MTSIF_RX1_BAND48_BAND51_ID_reserved0_MASK 0xc0000000
-#define BCHP_XPT_FE_MTSIF_RX1_BAND48_BAND51_ID_reserved0_SHIFT 30
-
-/* XPT_FE :: MTSIF_RX1_BAND48_BAND51_ID :: MTSIF_BAND51_BAND_ID [29:24] */
-#define BCHP_XPT_FE_MTSIF_RX1_BAND48_BAND51_ID_MTSIF_BAND51_BAND_ID_MASK 0x3f000000
-#define BCHP_XPT_FE_MTSIF_RX1_BAND48_BAND51_ID_MTSIF_BAND51_BAND_ID_SHIFT 24
-#define BCHP_XPT_FE_MTSIF_RX1_BAND48_BAND51_ID_MTSIF_BAND51_BAND_ID_DEFAULT 0x00000033
-
-/* XPT_FE :: MTSIF_RX1_BAND48_BAND51_ID :: reserved1 [23:22] */
-#define BCHP_XPT_FE_MTSIF_RX1_BAND48_BAND51_ID_reserved1_MASK 0x00c00000
-#define BCHP_XPT_FE_MTSIF_RX1_BAND48_BAND51_ID_reserved1_SHIFT 22
-
-/* XPT_FE :: MTSIF_RX1_BAND48_BAND51_ID :: MTSIF_BAND50_BAND_ID [21:16] */
-#define BCHP_XPT_FE_MTSIF_RX1_BAND48_BAND51_ID_MTSIF_BAND50_BAND_ID_MASK 0x003f0000
-#define BCHP_XPT_FE_MTSIF_RX1_BAND48_BAND51_ID_MTSIF_BAND50_BAND_ID_SHIFT 16
-#define BCHP_XPT_FE_MTSIF_RX1_BAND48_BAND51_ID_MTSIF_BAND50_BAND_ID_DEFAULT 0x00000032
-
-/* XPT_FE :: MTSIF_RX1_BAND48_BAND51_ID :: reserved2 [15:14] */
-#define BCHP_XPT_FE_MTSIF_RX1_BAND48_BAND51_ID_reserved2_MASK 0x0000c000
-#define BCHP_XPT_FE_MTSIF_RX1_BAND48_BAND51_ID_reserved2_SHIFT 14
-
-/* XPT_FE :: MTSIF_RX1_BAND48_BAND51_ID :: MTSIF_BAND49_BAND_ID [13:08] */
-#define BCHP_XPT_FE_MTSIF_RX1_BAND48_BAND51_ID_MTSIF_BAND49_BAND_ID_MASK 0x00003f00
-#define BCHP_XPT_FE_MTSIF_RX1_BAND48_BAND51_ID_MTSIF_BAND49_BAND_ID_SHIFT 8
-#define BCHP_XPT_FE_MTSIF_RX1_BAND48_BAND51_ID_MTSIF_BAND49_BAND_ID_DEFAULT 0x00000031
-
-/* XPT_FE :: MTSIF_RX1_BAND48_BAND51_ID :: reserved3 [07:06] */
-#define BCHP_XPT_FE_MTSIF_RX1_BAND48_BAND51_ID_reserved3_MASK 0x000000c0
-#define BCHP_XPT_FE_MTSIF_RX1_BAND48_BAND51_ID_reserved3_SHIFT 6
-
-/* XPT_FE :: MTSIF_RX1_BAND48_BAND51_ID :: MTSIF_BAND48_BAND_ID [05:00] */
-#define BCHP_XPT_FE_MTSIF_RX1_BAND48_BAND51_ID_MTSIF_BAND48_BAND_ID_MASK 0x0000003f
-#define BCHP_XPT_FE_MTSIF_RX1_BAND48_BAND51_ID_MTSIF_BAND48_BAND_ID_SHIFT 0
-#define BCHP_XPT_FE_MTSIF_RX1_BAND48_BAND51_ID_MTSIF_BAND48_BAND_ID_DEFAULT 0x00000030
-
-/***************************************************************************
- *MTSIF_RX1_BAND52_BAND55_ID - MTSIF RX1 Band52 to Band55 ID Register
- ***************************************************************************/
-/* XPT_FE :: MTSIF_RX1_BAND52_BAND55_ID :: reserved0 [31:30] */
-#define BCHP_XPT_FE_MTSIF_RX1_BAND52_BAND55_ID_reserved0_MASK 0xc0000000
-#define BCHP_XPT_FE_MTSIF_RX1_BAND52_BAND55_ID_reserved0_SHIFT 30
-
-/* XPT_FE :: MTSIF_RX1_BAND52_BAND55_ID :: MTSIF_BAND55_BAND_ID [29:24] */
-#define BCHP_XPT_FE_MTSIF_RX1_BAND52_BAND55_ID_MTSIF_BAND55_BAND_ID_MASK 0x3f000000
-#define BCHP_XPT_FE_MTSIF_RX1_BAND52_BAND55_ID_MTSIF_BAND55_BAND_ID_SHIFT 24
-#define BCHP_XPT_FE_MTSIF_RX1_BAND52_BAND55_ID_MTSIF_BAND55_BAND_ID_DEFAULT 0x00000037
-
-/* XPT_FE :: MTSIF_RX1_BAND52_BAND55_ID :: reserved1 [23:22] */
-#define BCHP_XPT_FE_MTSIF_RX1_BAND52_BAND55_ID_reserved1_MASK 0x00c00000
-#define BCHP_XPT_FE_MTSIF_RX1_BAND52_BAND55_ID_reserved1_SHIFT 22
-
-/* XPT_FE :: MTSIF_RX1_BAND52_BAND55_ID :: MTSIF_BAND54_BAND_ID [21:16] */
-#define BCHP_XPT_FE_MTSIF_RX1_BAND52_BAND55_ID_MTSIF_BAND54_BAND_ID_MASK 0x003f0000
-#define BCHP_XPT_FE_MTSIF_RX1_BAND52_BAND55_ID_MTSIF_BAND54_BAND_ID_SHIFT 16
-#define BCHP_XPT_FE_MTSIF_RX1_BAND52_BAND55_ID_MTSIF_BAND54_BAND_ID_DEFAULT 0x00000036
-
-/* XPT_FE :: MTSIF_RX1_BAND52_BAND55_ID :: reserved2 [15:14] */
-#define BCHP_XPT_FE_MTSIF_RX1_BAND52_BAND55_ID_reserved2_MASK 0x0000c000
-#define BCHP_XPT_FE_MTSIF_RX1_BAND52_BAND55_ID_reserved2_SHIFT 14
-
-/* XPT_FE :: MTSIF_RX1_BAND52_BAND55_ID :: MTSIF_BAND53_BAND_ID [13:08] */
-#define BCHP_XPT_FE_MTSIF_RX1_BAND52_BAND55_ID_MTSIF_BAND53_BAND_ID_MASK 0x00003f00
-#define BCHP_XPT_FE_MTSIF_RX1_BAND52_BAND55_ID_MTSIF_BAND53_BAND_ID_SHIFT 8
-#define BCHP_XPT_FE_MTSIF_RX1_BAND52_BAND55_ID_MTSIF_BAND53_BAND_ID_DEFAULT 0x00000035
-
-/* XPT_FE :: MTSIF_RX1_BAND52_BAND55_ID :: reserved3 [07:06] */
-#define BCHP_XPT_FE_MTSIF_RX1_BAND52_BAND55_ID_reserved3_MASK 0x000000c0
-#define BCHP_XPT_FE_MTSIF_RX1_BAND52_BAND55_ID_reserved3_SHIFT 6
-
-/* XPT_FE :: MTSIF_RX1_BAND52_BAND55_ID :: MTSIF_BAND52_BAND_ID [05:00] */
-#define BCHP_XPT_FE_MTSIF_RX1_BAND52_BAND55_ID_MTSIF_BAND52_BAND_ID_MASK 0x0000003f
-#define BCHP_XPT_FE_MTSIF_RX1_BAND52_BAND55_ID_MTSIF_BAND52_BAND_ID_SHIFT 0
-#define BCHP_XPT_FE_MTSIF_RX1_BAND52_BAND55_ID_MTSIF_BAND52_BAND_ID_DEFAULT 0x00000034
-
-/***************************************************************************
- *MTSIF_RX1_BAND56_BAND59_ID - MTSIF RX1 Band56 to Band59 ID Register
- ***************************************************************************/
-/* XPT_FE :: MTSIF_RX1_BAND56_BAND59_ID :: reserved0 [31:30] */
-#define BCHP_XPT_FE_MTSIF_RX1_BAND56_BAND59_ID_reserved0_MASK 0xc0000000
-#define BCHP_XPT_FE_MTSIF_RX1_BAND56_BAND59_ID_reserved0_SHIFT 30
-
-/* XPT_FE :: MTSIF_RX1_BAND56_BAND59_ID :: MTSIF_BAND59_BAND_ID [29:24] */
-#define BCHP_XPT_FE_MTSIF_RX1_BAND56_BAND59_ID_MTSIF_BAND59_BAND_ID_MASK 0x3f000000
-#define BCHP_XPT_FE_MTSIF_RX1_BAND56_BAND59_ID_MTSIF_BAND59_BAND_ID_SHIFT 24
-#define BCHP_XPT_FE_MTSIF_RX1_BAND56_BAND59_ID_MTSIF_BAND59_BAND_ID_DEFAULT 0x0000003b
-
-/* XPT_FE :: MTSIF_RX1_BAND56_BAND59_ID :: reserved1 [23:22] */
-#define BCHP_XPT_FE_MTSIF_RX1_BAND56_BAND59_ID_reserved1_MASK 0x00c00000
-#define BCHP_XPT_FE_MTSIF_RX1_BAND56_BAND59_ID_reserved1_SHIFT 22
-
-/* XPT_FE :: MTSIF_RX1_BAND56_BAND59_ID :: MTSIF_BAND58_BAND_ID [21:16] */
-#define BCHP_XPT_FE_MTSIF_RX1_BAND56_BAND59_ID_MTSIF_BAND58_BAND_ID_MASK 0x003f0000
-#define BCHP_XPT_FE_MTSIF_RX1_BAND56_BAND59_ID_MTSIF_BAND58_BAND_ID_SHIFT 16
-#define BCHP_XPT_FE_MTSIF_RX1_BAND56_BAND59_ID_MTSIF_BAND58_BAND_ID_DEFAULT 0x0000003a
-
-/* XPT_FE :: MTSIF_RX1_BAND56_BAND59_ID :: reserved2 [15:14] */
-#define BCHP_XPT_FE_MTSIF_RX1_BAND56_BAND59_ID_reserved2_MASK 0x0000c000
-#define BCHP_XPT_FE_MTSIF_RX1_BAND56_BAND59_ID_reserved2_SHIFT 14
-
-/* XPT_FE :: MTSIF_RX1_BAND56_BAND59_ID :: MTSIF_BAND57_BAND_ID [13:08] */
-#define BCHP_XPT_FE_MTSIF_RX1_BAND56_BAND59_ID_MTSIF_BAND57_BAND_ID_MASK 0x00003f00
-#define BCHP_XPT_FE_MTSIF_RX1_BAND56_BAND59_ID_MTSIF_BAND57_BAND_ID_SHIFT 8
-#define BCHP_XPT_FE_MTSIF_RX1_BAND56_BAND59_ID_MTSIF_BAND57_BAND_ID_DEFAULT 0x00000039
-
-/* XPT_FE :: MTSIF_RX1_BAND56_BAND59_ID :: reserved3 [07:06] */
-#define BCHP_XPT_FE_MTSIF_RX1_BAND56_BAND59_ID_reserved3_MASK 0x000000c0
-#define BCHP_XPT_FE_MTSIF_RX1_BAND56_BAND59_ID_reserved3_SHIFT 6
-
-/* XPT_FE :: MTSIF_RX1_BAND56_BAND59_ID :: MTSIF_BAND56_BAND_ID [05:00] */
-#define BCHP_XPT_FE_MTSIF_RX1_BAND56_BAND59_ID_MTSIF_BAND56_BAND_ID_MASK 0x0000003f
-#define BCHP_XPT_FE_MTSIF_RX1_BAND56_BAND59_ID_MTSIF_BAND56_BAND_ID_SHIFT 0
-#define BCHP_XPT_FE_MTSIF_RX1_BAND56_BAND59_ID_MTSIF_BAND56_BAND_ID_DEFAULT 0x00000038
-
-/***************************************************************************
- *MTSIF_RX1_BAND60_BAND63_ID - MTSIF RX1 Band60 to Band63 ID Register
- ***************************************************************************/
-/* XPT_FE :: MTSIF_RX1_BAND60_BAND63_ID :: reserved0 [31:30] */
-#define BCHP_XPT_FE_MTSIF_RX1_BAND60_BAND63_ID_reserved0_MASK 0xc0000000
-#define BCHP_XPT_FE_MTSIF_RX1_BAND60_BAND63_ID_reserved0_SHIFT 30
-
-/* XPT_FE :: MTSIF_RX1_BAND60_BAND63_ID :: MTSIF_BAND63_BAND_ID [29:24] */
-#define BCHP_XPT_FE_MTSIF_RX1_BAND60_BAND63_ID_MTSIF_BAND63_BAND_ID_MASK 0x3f000000
-#define BCHP_XPT_FE_MTSIF_RX1_BAND60_BAND63_ID_MTSIF_BAND63_BAND_ID_SHIFT 24
-#define BCHP_XPT_FE_MTSIF_RX1_BAND60_BAND63_ID_MTSIF_BAND63_BAND_ID_DEFAULT 0x0000003f
-
-/* XPT_FE :: MTSIF_RX1_BAND60_BAND63_ID :: reserved1 [23:22] */
-#define BCHP_XPT_FE_MTSIF_RX1_BAND60_BAND63_ID_reserved1_MASK 0x00c00000
-#define BCHP_XPT_FE_MTSIF_RX1_BAND60_BAND63_ID_reserved1_SHIFT 22
-
-/* XPT_FE :: MTSIF_RX1_BAND60_BAND63_ID :: MTSIF_BAND62_BAND_ID [21:16] */
-#define BCHP_XPT_FE_MTSIF_RX1_BAND60_BAND63_ID_MTSIF_BAND62_BAND_ID_MASK 0x003f0000
-#define BCHP_XPT_FE_MTSIF_RX1_BAND60_BAND63_ID_MTSIF_BAND62_BAND_ID_SHIFT 16
-#define BCHP_XPT_FE_MTSIF_RX1_BAND60_BAND63_ID_MTSIF_BAND62_BAND_ID_DEFAULT 0x0000003e
-
-/* XPT_FE :: MTSIF_RX1_BAND60_BAND63_ID :: reserved2 [15:14] */
-#define BCHP_XPT_FE_MTSIF_RX1_BAND60_BAND63_ID_reserved2_MASK 0x0000c000
-#define BCHP_XPT_FE_MTSIF_RX1_BAND60_BAND63_ID_reserved2_SHIFT 14
-
-/* XPT_FE :: MTSIF_RX1_BAND60_BAND63_ID :: MTSIF_BAND61_BAND_ID [13:08] */
-#define BCHP_XPT_FE_MTSIF_RX1_BAND60_BAND63_ID_MTSIF_BAND61_BAND_ID_MASK 0x00003f00
-#define BCHP_XPT_FE_MTSIF_RX1_BAND60_BAND63_ID_MTSIF_BAND61_BAND_ID_SHIFT 8
-#define BCHP_XPT_FE_MTSIF_RX1_BAND60_BAND63_ID_MTSIF_BAND61_BAND_ID_DEFAULT 0x0000003d
-
-/* XPT_FE :: MTSIF_RX1_BAND60_BAND63_ID :: reserved3 [07:06] */
-#define BCHP_XPT_FE_MTSIF_RX1_BAND60_BAND63_ID_reserved3_MASK 0x000000c0
-#define BCHP_XPT_FE_MTSIF_RX1_BAND60_BAND63_ID_reserved3_SHIFT 6
-
-/* XPT_FE :: MTSIF_RX1_BAND60_BAND63_ID :: MTSIF_BAND60_BAND_ID [05:00] */
-#define BCHP_XPT_FE_MTSIF_RX1_BAND60_BAND63_ID_MTSIF_BAND60_BAND_ID_MASK 0x0000003f
-#define BCHP_XPT_FE_MTSIF_RX1_BAND60_BAND63_ID_MTSIF_BAND60_BAND_ID_SHIFT 0
-#define BCHP_XPT_FE_MTSIF_RX1_BAND60_BAND63_ID_MTSIF_BAND60_BAND_ID_DEFAULT 0x0000003c
-
-/***************************************************************************
- *MTSIF_RX1_PKT_BAND0_BAND31_DETECT - MTSIF RX1 Packet Band0 to Band31 Detect Register
- ***************************************************************************/
-/* XPT_FE :: MTSIF_RX1_PKT_BAND0_BAND31_DETECT :: BAND_ID31 [31:31] */
-#define BCHP_XPT_FE_MTSIF_RX1_PKT_BAND0_BAND31_DETECT_BAND_ID31_MASK 0x80000000
-#define BCHP_XPT_FE_MTSIF_RX1_PKT_BAND0_BAND31_DETECT_BAND_ID31_SHIFT 31
-#define BCHP_XPT_FE_MTSIF_RX1_PKT_BAND0_BAND31_DETECT_BAND_ID31_DEFAULT 0x00000000
-
-/* XPT_FE :: MTSIF_RX1_PKT_BAND0_BAND31_DETECT :: BAND_ID30 [30:30] */
-#define BCHP_XPT_FE_MTSIF_RX1_PKT_BAND0_BAND31_DETECT_BAND_ID30_MASK 0x40000000
-#define BCHP_XPT_FE_MTSIF_RX1_PKT_BAND0_BAND31_DETECT_BAND_ID30_SHIFT 30
-#define BCHP_XPT_FE_MTSIF_RX1_PKT_BAND0_BAND31_DETECT_BAND_ID30_DEFAULT 0x00000000
-
-/* XPT_FE :: MTSIF_RX1_PKT_BAND0_BAND31_DETECT :: BAND_ID29 [29:29] */
-#define BCHP_XPT_FE_MTSIF_RX1_PKT_BAND0_BAND31_DETECT_BAND_ID29_MASK 0x20000000
-#define BCHP_XPT_FE_MTSIF_RX1_PKT_BAND0_BAND31_DETECT_BAND_ID29_SHIFT 29
-#define BCHP_XPT_FE_MTSIF_RX1_PKT_BAND0_BAND31_DETECT_BAND_ID29_DEFAULT 0x00000000
-
-/* XPT_FE :: MTSIF_RX1_PKT_BAND0_BAND31_DETECT :: BAND_ID28 [28:28] */
-#define BCHP_XPT_FE_MTSIF_RX1_PKT_BAND0_BAND31_DETECT_BAND_ID28_MASK 0x10000000
-#define BCHP_XPT_FE_MTSIF_RX1_PKT_BAND0_BAND31_DETECT_BAND_ID28_SHIFT 28
-#define BCHP_XPT_FE_MTSIF_RX1_PKT_BAND0_BAND31_DETECT_BAND_ID28_DEFAULT 0x00000000
-
-/* XPT_FE :: MTSIF_RX1_PKT_BAND0_BAND31_DETECT :: BAND_ID27 [27:27] */
-#define BCHP_XPT_FE_MTSIF_RX1_PKT_BAND0_BAND31_DETECT_BAND_ID27_MASK 0x08000000
-#define BCHP_XPT_FE_MTSIF_RX1_PKT_BAND0_BAND31_DETECT_BAND_ID27_SHIFT 27
-#define BCHP_XPT_FE_MTSIF_RX1_PKT_BAND0_BAND31_DETECT_BAND_ID27_DEFAULT 0x00000000
-
-/* XPT_FE :: MTSIF_RX1_PKT_BAND0_BAND31_DETECT :: BAND_ID26 [26:26] */
-#define BCHP_XPT_FE_MTSIF_RX1_PKT_BAND0_BAND31_DETECT_BAND_ID26_MASK 0x04000000
-#define BCHP_XPT_FE_MTSIF_RX1_PKT_BAND0_BAND31_DETECT_BAND_ID26_SHIFT 26
-#define BCHP_XPT_FE_MTSIF_RX1_PKT_BAND0_BAND31_DETECT_BAND_ID26_DEFAULT 0x00000000
-
-/* XPT_FE :: MTSIF_RX1_PKT_BAND0_BAND31_DETECT :: BAND_ID25 [25:25] */
-#define BCHP_XPT_FE_MTSIF_RX1_PKT_BAND0_BAND31_DETECT_BAND_ID25_MASK 0x02000000
-#define BCHP_XPT_FE_MTSIF_RX1_PKT_BAND0_BAND31_DETECT_BAND_ID25_SHIFT 25
-#define BCHP_XPT_FE_MTSIF_RX1_PKT_BAND0_BAND31_DETECT_BAND_ID25_DEFAULT 0x00000000
-
-/* XPT_FE :: MTSIF_RX1_PKT_BAND0_BAND31_DETECT :: BAND_ID24 [24:24] */
-#define BCHP_XPT_FE_MTSIF_RX1_PKT_BAND0_BAND31_DETECT_BAND_ID24_MASK 0x01000000
-#define BCHP_XPT_FE_MTSIF_RX1_PKT_BAND0_BAND31_DETECT_BAND_ID24_SHIFT 24
-#define BCHP_XPT_FE_MTSIF_RX1_PKT_BAND0_BAND31_DETECT_BAND_ID24_DEFAULT 0x00000000
-
-/* XPT_FE :: MTSIF_RX1_PKT_BAND0_BAND31_DETECT :: BAND_ID23 [23:23] */
-#define BCHP_XPT_FE_MTSIF_RX1_PKT_BAND0_BAND31_DETECT_BAND_ID23_MASK 0x00800000
-#define BCHP_XPT_FE_MTSIF_RX1_PKT_BAND0_BAND31_DETECT_BAND_ID23_SHIFT 23
-#define BCHP_XPT_FE_MTSIF_RX1_PKT_BAND0_BAND31_DETECT_BAND_ID23_DEFAULT 0x00000000
-
-/* XPT_FE :: MTSIF_RX1_PKT_BAND0_BAND31_DETECT :: BAND_ID22 [22:22] */
-#define BCHP_XPT_FE_MTSIF_RX1_PKT_BAND0_BAND31_DETECT_BAND_ID22_MASK 0x00400000
-#define BCHP_XPT_FE_MTSIF_RX1_PKT_BAND0_BAND31_DETECT_BAND_ID22_SHIFT 22
-#define BCHP_XPT_FE_MTSIF_RX1_PKT_BAND0_BAND31_DETECT_BAND_ID22_DEFAULT 0x00000000
-
-/* XPT_FE :: MTSIF_RX1_PKT_BAND0_BAND31_DETECT :: BAND_ID21 [21:21] */
-#define BCHP_XPT_FE_MTSIF_RX1_PKT_BAND0_BAND31_DETECT_BAND_ID21_MASK 0x00200000
-#define BCHP_XPT_FE_MTSIF_RX1_PKT_BAND0_BAND31_DETECT_BAND_ID21_SHIFT 21
-#define BCHP_XPT_FE_MTSIF_RX1_PKT_BAND0_BAND31_DETECT_BAND_ID21_DEFAULT 0x00000000
-
-/* XPT_FE :: MTSIF_RX1_PKT_BAND0_BAND31_DETECT :: BAND_ID20 [20:20] */
-#define BCHP_XPT_FE_MTSIF_RX1_PKT_BAND0_BAND31_DETECT_BAND_ID20_MASK 0x00100000
-#define BCHP_XPT_FE_MTSIF_RX1_PKT_BAND0_BAND31_DETECT_BAND_ID20_SHIFT 20
-#define BCHP_XPT_FE_MTSIF_RX1_PKT_BAND0_BAND31_DETECT_BAND_ID20_DEFAULT 0x00000000
-
-/* XPT_FE :: MTSIF_RX1_PKT_BAND0_BAND31_DETECT :: BAND_ID19 [19:19] */
-#define BCHP_XPT_FE_MTSIF_RX1_PKT_BAND0_BAND31_DETECT_BAND_ID19_MASK 0x00080000
-#define BCHP_XPT_FE_MTSIF_RX1_PKT_BAND0_BAND31_DETECT_BAND_ID19_SHIFT 19
-#define BCHP_XPT_FE_MTSIF_RX1_PKT_BAND0_BAND31_DETECT_BAND_ID19_DEFAULT 0x00000000
-
-/* XPT_FE :: MTSIF_RX1_PKT_BAND0_BAND31_DETECT :: BAND_ID18 [18:18] */
-#define BCHP_XPT_FE_MTSIF_RX1_PKT_BAND0_BAND31_DETECT_BAND_ID18_MASK 0x00040000
-#define BCHP_XPT_FE_MTSIF_RX1_PKT_BAND0_BAND31_DETECT_BAND_ID18_SHIFT 18
-#define BCHP_XPT_FE_MTSIF_RX1_PKT_BAND0_BAND31_DETECT_BAND_ID18_DEFAULT 0x00000000
-
-/* XPT_FE :: MTSIF_RX1_PKT_BAND0_BAND31_DETECT :: BAND_ID17 [17:17] */
-#define BCHP_XPT_FE_MTSIF_RX1_PKT_BAND0_BAND31_DETECT_BAND_ID17_MASK 0x00020000
-#define BCHP_XPT_FE_MTSIF_RX1_PKT_BAND0_BAND31_DETECT_BAND_ID17_SHIFT 17
-#define BCHP_XPT_FE_MTSIF_RX1_PKT_BAND0_BAND31_DETECT_BAND_ID17_DEFAULT 0x00000000
-
-/* XPT_FE :: MTSIF_RX1_PKT_BAND0_BAND31_DETECT :: BAND_ID16 [16:16] */
-#define BCHP_XPT_FE_MTSIF_RX1_PKT_BAND0_BAND31_DETECT_BAND_ID16_MASK 0x00010000
-#define BCHP_XPT_FE_MTSIF_RX1_PKT_BAND0_BAND31_DETECT_BAND_ID16_SHIFT 16
-#define BCHP_XPT_FE_MTSIF_RX1_PKT_BAND0_BAND31_DETECT_BAND_ID16_DEFAULT 0x00000000
-
-/* XPT_FE :: MTSIF_RX1_PKT_BAND0_BAND31_DETECT :: BAND_ID15 [15:15] */
-#define BCHP_XPT_FE_MTSIF_RX1_PKT_BAND0_BAND31_DETECT_BAND_ID15_MASK 0x00008000
-#define BCHP_XPT_FE_MTSIF_RX1_PKT_BAND0_BAND31_DETECT_BAND_ID15_SHIFT 15
-#define BCHP_XPT_FE_MTSIF_RX1_PKT_BAND0_BAND31_DETECT_BAND_ID15_DEFAULT 0x00000000
-
-/* XPT_FE :: MTSIF_RX1_PKT_BAND0_BAND31_DETECT :: BAND_ID14 [14:14] */
-#define BCHP_XPT_FE_MTSIF_RX1_PKT_BAND0_BAND31_DETECT_BAND_ID14_MASK 0x00004000
-#define BCHP_XPT_FE_MTSIF_RX1_PKT_BAND0_BAND31_DETECT_BAND_ID14_SHIFT 14
-#define BCHP_XPT_FE_MTSIF_RX1_PKT_BAND0_BAND31_DETECT_BAND_ID14_DEFAULT 0x00000000
-
-/* XPT_FE :: MTSIF_RX1_PKT_BAND0_BAND31_DETECT :: BAND_ID13 [13:13] */
-#define BCHP_XPT_FE_MTSIF_RX1_PKT_BAND0_BAND31_DETECT_BAND_ID13_MASK 0x00002000
-#define BCHP_XPT_FE_MTSIF_RX1_PKT_BAND0_BAND31_DETECT_BAND_ID13_SHIFT 13
-#define BCHP_XPT_FE_MTSIF_RX1_PKT_BAND0_BAND31_DETECT_BAND_ID13_DEFAULT 0x00000000
-
-/* XPT_FE :: MTSIF_RX1_PKT_BAND0_BAND31_DETECT :: BAND_ID12 [12:12] */
-#define BCHP_XPT_FE_MTSIF_RX1_PKT_BAND0_BAND31_DETECT_BAND_ID12_MASK 0x00001000
-#define BCHP_XPT_FE_MTSIF_RX1_PKT_BAND0_BAND31_DETECT_BAND_ID12_SHIFT 12
-#define BCHP_XPT_FE_MTSIF_RX1_PKT_BAND0_BAND31_DETECT_BAND_ID12_DEFAULT 0x00000000
-
-/* XPT_FE :: MTSIF_RX1_PKT_BAND0_BAND31_DETECT :: BAND_ID11 [11:11] */
-#define BCHP_XPT_FE_MTSIF_RX1_PKT_BAND0_BAND31_DETECT_BAND_ID11_MASK 0x00000800
-#define BCHP_XPT_FE_MTSIF_RX1_PKT_BAND0_BAND31_DETECT_BAND_ID11_SHIFT 11
-#define BCHP_XPT_FE_MTSIF_RX1_PKT_BAND0_BAND31_DETECT_BAND_ID11_DEFAULT 0x00000000
-
-/* XPT_FE :: MTSIF_RX1_PKT_BAND0_BAND31_DETECT :: BAND_ID10 [10:10] */
-#define BCHP_XPT_FE_MTSIF_RX1_PKT_BAND0_BAND31_DETECT_BAND_ID10_MASK 0x00000400
-#define BCHP_XPT_FE_MTSIF_RX1_PKT_BAND0_BAND31_DETECT_BAND_ID10_SHIFT 10
-#define BCHP_XPT_FE_MTSIF_RX1_PKT_BAND0_BAND31_DETECT_BAND_ID10_DEFAULT 0x00000000
-
-/* XPT_FE :: MTSIF_RX1_PKT_BAND0_BAND31_DETECT :: BAND_ID9 [09:09] */
-#define BCHP_XPT_FE_MTSIF_RX1_PKT_BAND0_BAND31_DETECT_BAND_ID9_MASK 0x00000200
-#define BCHP_XPT_FE_MTSIF_RX1_PKT_BAND0_BAND31_DETECT_BAND_ID9_SHIFT 9
-#define BCHP_XPT_FE_MTSIF_RX1_PKT_BAND0_BAND31_DETECT_BAND_ID9_DEFAULT 0x00000000
-
-/* XPT_FE :: MTSIF_RX1_PKT_BAND0_BAND31_DETECT :: BAND_ID8 [08:08] */
-#define BCHP_XPT_FE_MTSIF_RX1_PKT_BAND0_BAND31_DETECT_BAND_ID8_MASK 0x00000100
-#define BCHP_XPT_FE_MTSIF_RX1_PKT_BAND0_BAND31_DETECT_BAND_ID8_SHIFT 8
-#define BCHP_XPT_FE_MTSIF_RX1_PKT_BAND0_BAND31_DETECT_BAND_ID8_DEFAULT 0x00000000
-
-/* XPT_FE :: MTSIF_RX1_PKT_BAND0_BAND31_DETECT :: BAND_ID7 [07:07] */
-#define BCHP_XPT_FE_MTSIF_RX1_PKT_BAND0_BAND31_DETECT_BAND_ID7_MASK 0x00000080
-#define BCHP_XPT_FE_MTSIF_RX1_PKT_BAND0_BAND31_DETECT_BAND_ID7_SHIFT 7
-#define BCHP_XPT_FE_MTSIF_RX1_PKT_BAND0_BAND31_DETECT_BAND_ID7_DEFAULT 0x00000000
-
-/* XPT_FE :: MTSIF_RX1_PKT_BAND0_BAND31_DETECT :: BAND_ID6 [06:06] */
-#define BCHP_XPT_FE_MTSIF_RX1_PKT_BAND0_BAND31_DETECT_BAND_ID6_MASK 0x00000040
-#define BCHP_XPT_FE_MTSIF_RX1_PKT_BAND0_BAND31_DETECT_BAND_ID6_SHIFT 6
-#define BCHP_XPT_FE_MTSIF_RX1_PKT_BAND0_BAND31_DETECT_BAND_ID6_DEFAULT 0x00000000
-
-/* XPT_FE :: MTSIF_RX1_PKT_BAND0_BAND31_DETECT :: BAND_ID5 [05:05] */
-#define BCHP_XPT_FE_MTSIF_RX1_PKT_BAND0_BAND31_DETECT_BAND_ID5_MASK 0x00000020
-#define BCHP_XPT_FE_MTSIF_RX1_PKT_BAND0_BAND31_DETECT_BAND_ID5_SHIFT 5
-#define BCHP_XPT_FE_MTSIF_RX1_PKT_BAND0_BAND31_DETECT_BAND_ID5_DEFAULT 0x00000000
-
-/* XPT_FE :: MTSIF_RX1_PKT_BAND0_BAND31_DETECT :: BAND_ID4 [04:04] */
-#define BCHP_XPT_FE_MTSIF_RX1_PKT_BAND0_BAND31_DETECT_BAND_ID4_MASK 0x00000010
-#define BCHP_XPT_FE_MTSIF_RX1_PKT_BAND0_BAND31_DETECT_BAND_ID4_SHIFT 4
-#define BCHP_XPT_FE_MTSIF_RX1_PKT_BAND0_BAND31_DETECT_BAND_ID4_DEFAULT 0x00000000
-
-/* XPT_FE :: MTSIF_RX1_PKT_BAND0_BAND31_DETECT :: BAND_ID3 [03:03] */
-#define BCHP_XPT_FE_MTSIF_RX1_PKT_BAND0_BAND31_DETECT_BAND_ID3_MASK 0x00000008
-#define BCHP_XPT_FE_MTSIF_RX1_PKT_BAND0_BAND31_DETECT_BAND_ID3_SHIFT 3
-#define BCHP_XPT_FE_MTSIF_RX1_PKT_BAND0_BAND31_DETECT_BAND_ID3_DEFAULT 0x00000000
-
-/* XPT_FE :: MTSIF_RX1_PKT_BAND0_BAND31_DETECT :: BAND_ID2 [02:02] */
-#define BCHP_XPT_FE_MTSIF_RX1_PKT_BAND0_BAND31_DETECT_BAND_ID2_MASK 0x00000004
-#define BCHP_XPT_FE_MTSIF_RX1_PKT_BAND0_BAND31_DETECT_BAND_ID2_SHIFT 2
-#define BCHP_XPT_FE_MTSIF_RX1_PKT_BAND0_BAND31_DETECT_BAND_ID2_DEFAULT 0x00000000
-
-/* XPT_FE :: MTSIF_RX1_PKT_BAND0_BAND31_DETECT :: BAND_ID1 [01:01] */
-#define BCHP_XPT_FE_MTSIF_RX1_PKT_BAND0_BAND31_DETECT_BAND_ID1_MASK 0x00000002
-#define BCHP_XPT_FE_MTSIF_RX1_PKT_BAND0_BAND31_DETECT_BAND_ID1_SHIFT 1
-#define BCHP_XPT_FE_MTSIF_RX1_PKT_BAND0_BAND31_DETECT_BAND_ID1_DEFAULT 0x00000000
-
-/* XPT_FE :: MTSIF_RX1_PKT_BAND0_BAND31_DETECT :: BAND_ID0 [00:00] */
-#define BCHP_XPT_FE_MTSIF_RX1_PKT_BAND0_BAND31_DETECT_BAND_ID0_MASK 0x00000001
-#define BCHP_XPT_FE_MTSIF_RX1_PKT_BAND0_BAND31_DETECT_BAND_ID0_SHIFT 0
-#define BCHP_XPT_FE_MTSIF_RX1_PKT_BAND0_BAND31_DETECT_BAND_ID0_DEFAULT 0x00000000
-
-/***************************************************************************
- *MTSIF_RX2_CTRL1 - FE_MTSIF_RX2_CTRL1
- ***************************************************************************/
-/* XPT_FE :: MTSIF_RX2_CTRL1 :: reserved0 [31:09] */
-#define BCHP_XPT_FE_MTSIF_RX2_CTRL1_reserved0_MASK 0xfffffe00
-#define BCHP_XPT_FE_MTSIF_RX2_CTRL1_reserved0_SHIFT 9
-
-/* XPT_FE :: MTSIF_RX2_CTRL1 :: MTSIF_RX_DECRYPTION_ENABLE_STATUS [08:08] */
-#define BCHP_XPT_FE_MTSIF_RX2_CTRL1_MTSIF_RX_DECRYPTION_ENABLE_STATUS_MASK 0x00000100
-#define BCHP_XPT_FE_MTSIF_RX2_CTRL1_MTSIF_RX_DECRYPTION_ENABLE_STATUS_SHIFT 8
-#define BCHP_XPT_FE_MTSIF_RX2_CTRL1_MTSIF_RX_DECRYPTION_ENABLE_STATUS_DEFAULT 0x00000001
-
-/* XPT_FE :: MTSIF_RX2_CTRL1 :: MTSIF_RX_PKT_BAND_DETECT_MODE [07:07] */
-#define BCHP_XPT_FE_MTSIF_RX2_CTRL1_MTSIF_RX_PKT_BAND_DETECT_MODE_MASK 0x00000080
-#define BCHP_XPT_FE_MTSIF_RX2_CTRL1_MTSIF_RX_PKT_BAND_DETECT_MODE_SHIFT 7
-#define BCHP_XPT_FE_MTSIF_RX2_CTRL1_MTSIF_RX_PKT_BAND_DETECT_MODE_DEFAULT 0x00000000
-
-/* XPT_FE :: MTSIF_RX2_CTRL1 :: MTSIF_RX_ERR_RPT_EN [06:06] */
-#define BCHP_XPT_FE_MTSIF_RX2_CTRL1_MTSIF_RX_ERR_RPT_EN_MASK 0x00000040
-#define BCHP_XPT_FE_MTSIF_RX2_CTRL1_MTSIF_RX_ERR_RPT_EN_SHIFT 6
-#define BCHP_XPT_FE_MTSIF_RX2_CTRL1_MTSIF_RX_ERR_RPT_EN_DEFAULT 0x00000000
-
-/* XPT_FE :: MTSIF_RX2_CTRL1 :: MTSIF_RX_IF_WIDTH [05:04] */
-#define BCHP_XPT_FE_MTSIF_RX2_CTRL1_MTSIF_RX_IF_WIDTH_MASK 0x00000030
-#define BCHP_XPT_FE_MTSIF_RX2_CTRL1_MTSIF_RX_IF_WIDTH_SHIFT 4
-#define BCHP_XPT_FE_MTSIF_RX2_CTRL1_MTSIF_RX_IF_WIDTH_DEFAULT 0x00000003
-
-/* XPT_FE :: MTSIF_RX2_CTRL1 :: reserved1 [03:02] */
-#define BCHP_XPT_FE_MTSIF_RX2_CTRL1_reserved1_MASK 0x0000000c
-#define BCHP_XPT_FE_MTSIF_RX2_CTRL1_reserved1_SHIFT 2
-
-/* XPT_FE :: MTSIF_RX2_CTRL1 :: MTSIF_RX_CLOCK_POL_SEL [01:01] */
-#define BCHP_XPT_FE_MTSIF_RX2_CTRL1_MTSIF_RX_CLOCK_POL_SEL_MASK 0x00000002
-#define BCHP_XPT_FE_MTSIF_RX2_CTRL1_MTSIF_RX_CLOCK_POL_SEL_SHIFT 1
-#define BCHP_XPT_FE_MTSIF_RX2_CTRL1_MTSIF_RX_CLOCK_POL_SEL_DEFAULT 0x00000001
-
-/* XPT_FE :: MTSIF_RX2_CTRL1 :: PARSER_ENABLE [00:00] */
-#define BCHP_XPT_FE_MTSIF_RX2_CTRL1_PARSER_ENABLE_MASK 0x00000001
-#define BCHP_XPT_FE_MTSIF_RX2_CTRL1_PARSER_ENABLE_SHIFT 0
-#define BCHP_XPT_FE_MTSIF_RX2_CTRL1_PARSER_ENABLE_DEFAULT 0x00000000
-
-/***************************************************************************
- *MTSIF_RX2_SECRET_WORD - MTSIF RX2 Secret Word Register
- ***************************************************************************/
-/* XPT_FE :: MTSIF_RX2_SECRET_WORD :: SECRET_WORD [31:00] */
-#define BCHP_XPT_FE_MTSIF_RX2_SECRET_WORD_SECRET_WORD_MASK 0xffffffff
-#define BCHP_XPT_FE_MTSIF_RX2_SECRET_WORD_SECRET_WORD_SHIFT 0
-#define BCHP_XPT_FE_MTSIF_RX2_SECRET_WORD_SECRET_WORD_DEFAULT 0x00000000
-
-/***************************************************************************
- *MTSIF_RX2_BAND0_BAND31_ID_DROP - MTSIF RX2 Band0 to Band31 ID Drop Register
- ***************************************************************************/
-/* XPT_FE :: MTSIF_RX2_BAND0_BAND31_ID_DROP :: DROP_EN [31:00] */
-#define BCHP_XPT_FE_MTSIF_RX2_BAND0_BAND31_ID_DROP_DROP_EN_MASK 0xffffffff
-#define BCHP_XPT_FE_MTSIF_RX2_BAND0_BAND31_ID_DROP_DROP_EN_SHIFT 0
-#define BCHP_XPT_FE_MTSIF_RX2_BAND0_BAND31_ID_DROP_DROP_EN_DEFAULT 0x00000000
-
-/***************************************************************************
- *MTSIF_RX2_BAND0_BAND3_ID - MTSIF RX2 Band0 to Band3 ID Register
- ***************************************************************************/
-/* XPT_FE :: MTSIF_RX2_BAND0_BAND3_ID :: reserved0 [31:30] */
-#define BCHP_XPT_FE_MTSIF_RX2_BAND0_BAND3_ID_reserved0_MASK 0xc0000000
-#define BCHP_XPT_FE_MTSIF_RX2_BAND0_BAND3_ID_reserved0_SHIFT 30
-
-/* XPT_FE :: MTSIF_RX2_BAND0_BAND3_ID :: MTSIF_BAND3_BAND_ID [29:24] */
-#define BCHP_XPT_FE_MTSIF_RX2_BAND0_BAND3_ID_MTSIF_BAND3_BAND_ID_MASK 0x3f000000
-#define BCHP_XPT_FE_MTSIF_RX2_BAND0_BAND3_ID_MTSIF_BAND3_BAND_ID_SHIFT 24
-#define BCHP_XPT_FE_MTSIF_RX2_BAND0_BAND3_ID_MTSIF_BAND3_BAND_ID_DEFAULT 0x00000003
-
-/* XPT_FE :: MTSIF_RX2_BAND0_BAND3_ID :: reserved1 [23:22] */
-#define BCHP_XPT_FE_MTSIF_RX2_BAND0_BAND3_ID_reserved1_MASK 0x00c00000
-#define BCHP_XPT_FE_MTSIF_RX2_BAND0_BAND3_ID_reserved1_SHIFT 22
-
-/* XPT_FE :: MTSIF_RX2_BAND0_BAND3_ID :: MTSIF_BAND2_BAND_ID [21:16] */
-#define BCHP_XPT_FE_MTSIF_RX2_BAND0_BAND3_ID_MTSIF_BAND2_BAND_ID_MASK 0x003f0000
-#define BCHP_XPT_FE_MTSIF_RX2_BAND0_BAND3_ID_MTSIF_BAND2_BAND_ID_SHIFT 16
-#define BCHP_XPT_FE_MTSIF_RX2_BAND0_BAND3_ID_MTSIF_BAND2_BAND_ID_DEFAULT 0x00000002
-
-/* XPT_FE :: MTSIF_RX2_BAND0_BAND3_ID :: reserved2 [15:14] */
-#define BCHP_XPT_FE_MTSIF_RX2_BAND0_BAND3_ID_reserved2_MASK 0x0000c000
-#define BCHP_XPT_FE_MTSIF_RX2_BAND0_BAND3_ID_reserved2_SHIFT 14
-
-/* XPT_FE :: MTSIF_RX2_BAND0_BAND3_ID :: MTSIF_BAND1_BAND_ID [13:08] */
-#define BCHP_XPT_FE_MTSIF_RX2_BAND0_BAND3_ID_MTSIF_BAND1_BAND_ID_MASK 0x00003f00
-#define BCHP_XPT_FE_MTSIF_RX2_BAND0_BAND3_ID_MTSIF_BAND1_BAND_ID_SHIFT 8
-#define BCHP_XPT_FE_MTSIF_RX2_BAND0_BAND3_ID_MTSIF_BAND1_BAND_ID_DEFAULT 0x00000001
-
-/* XPT_FE :: MTSIF_RX2_BAND0_BAND3_ID :: reserved3 [07:06] */
-#define BCHP_XPT_FE_MTSIF_RX2_BAND0_BAND3_ID_reserved3_MASK 0x000000c0
-#define BCHP_XPT_FE_MTSIF_RX2_BAND0_BAND3_ID_reserved3_SHIFT 6
-
-/* XPT_FE :: MTSIF_RX2_BAND0_BAND3_ID :: MTSIF_BAND0_BAND_ID [05:00] */
-#define BCHP_XPT_FE_MTSIF_RX2_BAND0_BAND3_ID_MTSIF_BAND0_BAND_ID_MASK 0x0000003f
-#define BCHP_XPT_FE_MTSIF_RX2_BAND0_BAND3_ID_MTSIF_BAND0_BAND_ID_SHIFT 0
-#define BCHP_XPT_FE_MTSIF_RX2_BAND0_BAND3_ID_MTSIF_BAND0_BAND_ID_DEFAULT 0x00000000
-
-/***************************************************************************
- *MTSIF_RX2_BAND4_BAND7_ID - MTSIF RX2 Band4 to Band7 ID Register
- ***************************************************************************/
-/* XPT_FE :: MTSIF_RX2_BAND4_BAND7_ID :: reserved0 [31:30] */
-#define BCHP_XPT_FE_MTSIF_RX2_BAND4_BAND7_ID_reserved0_MASK 0xc0000000
-#define BCHP_XPT_FE_MTSIF_RX2_BAND4_BAND7_ID_reserved0_SHIFT 30
-
-/* XPT_FE :: MTSIF_RX2_BAND4_BAND7_ID :: MTSIF_BAND7_BAND_ID [29:24] */
-#define BCHP_XPT_FE_MTSIF_RX2_BAND4_BAND7_ID_MTSIF_BAND7_BAND_ID_MASK 0x3f000000
-#define BCHP_XPT_FE_MTSIF_RX2_BAND4_BAND7_ID_MTSIF_BAND7_BAND_ID_SHIFT 24
-#define BCHP_XPT_FE_MTSIF_RX2_BAND4_BAND7_ID_MTSIF_BAND7_BAND_ID_DEFAULT 0x00000007
-
-/* XPT_FE :: MTSIF_RX2_BAND4_BAND7_ID :: reserved1 [23:22] */
-#define BCHP_XPT_FE_MTSIF_RX2_BAND4_BAND7_ID_reserved1_MASK 0x00c00000
-#define BCHP_XPT_FE_MTSIF_RX2_BAND4_BAND7_ID_reserved1_SHIFT 22
-
-/* XPT_FE :: MTSIF_RX2_BAND4_BAND7_ID :: MTSIF_BAND6_BAND_ID [21:16] */
-#define BCHP_XPT_FE_MTSIF_RX2_BAND4_BAND7_ID_MTSIF_BAND6_BAND_ID_MASK 0x003f0000
-#define BCHP_XPT_FE_MTSIF_RX2_BAND4_BAND7_ID_MTSIF_BAND6_BAND_ID_SHIFT 16
-#define BCHP_XPT_FE_MTSIF_RX2_BAND4_BAND7_ID_MTSIF_BAND6_BAND_ID_DEFAULT 0x00000006
-
-/* XPT_FE :: MTSIF_RX2_BAND4_BAND7_ID :: reserved2 [15:14] */
-#define BCHP_XPT_FE_MTSIF_RX2_BAND4_BAND7_ID_reserved2_MASK 0x0000c000
-#define BCHP_XPT_FE_MTSIF_RX2_BAND4_BAND7_ID_reserved2_SHIFT 14
-
-/* XPT_FE :: MTSIF_RX2_BAND4_BAND7_ID :: MTSIF_BAND5_BAND_ID [13:08] */
-#define BCHP_XPT_FE_MTSIF_RX2_BAND4_BAND7_ID_MTSIF_BAND5_BAND_ID_MASK 0x00003f00
-#define BCHP_XPT_FE_MTSIF_RX2_BAND4_BAND7_ID_MTSIF_BAND5_BAND_ID_SHIFT 8
-#define BCHP_XPT_FE_MTSIF_RX2_BAND4_BAND7_ID_MTSIF_BAND5_BAND_ID_DEFAULT 0x00000005
-
-/* XPT_FE :: MTSIF_RX2_BAND4_BAND7_ID :: reserved3 [07:06] */
-#define BCHP_XPT_FE_MTSIF_RX2_BAND4_BAND7_ID_reserved3_MASK 0x000000c0
-#define BCHP_XPT_FE_MTSIF_RX2_BAND4_BAND7_ID_reserved3_SHIFT 6
-
-/* XPT_FE :: MTSIF_RX2_BAND4_BAND7_ID :: MTSIF_BAND4_BAND_ID [05:00] */
-#define BCHP_XPT_FE_MTSIF_RX2_BAND4_BAND7_ID_MTSIF_BAND4_BAND_ID_MASK 0x0000003f
-#define BCHP_XPT_FE_MTSIF_RX2_BAND4_BAND7_ID_MTSIF_BAND4_BAND_ID_SHIFT 0
-#define BCHP_XPT_FE_MTSIF_RX2_BAND4_BAND7_ID_MTSIF_BAND4_BAND_ID_DEFAULT 0x00000004
-
-/***************************************************************************
- *MTSIF_RX2_BAND8_BAND11_ID - MTSIF RX2 Band8 to Band11 ID Register
- ***************************************************************************/
-/* XPT_FE :: MTSIF_RX2_BAND8_BAND11_ID :: reserved0 [31:30] */
-#define BCHP_XPT_FE_MTSIF_RX2_BAND8_BAND11_ID_reserved0_MASK 0xc0000000
-#define BCHP_XPT_FE_MTSIF_RX2_BAND8_BAND11_ID_reserved0_SHIFT 30
-
-/* XPT_FE :: MTSIF_RX2_BAND8_BAND11_ID :: MTSIF_BAND11_BAND_ID [29:24] */
-#define BCHP_XPT_FE_MTSIF_RX2_BAND8_BAND11_ID_MTSIF_BAND11_BAND_ID_MASK 0x3f000000
-#define BCHP_XPT_FE_MTSIF_RX2_BAND8_BAND11_ID_MTSIF_BAND11_BAND_ID_SHIFT 24
-#define BCHP_XPT_FE_MTSIF_RX2_BAND8_BAND11_ID_MTSIF_BAND11_BAND_ID_DEFAULT 0x0000000b
-
-/* XPT_FE :: MTSIF_RX2_BAND8_BAND11_ID :: reserved1 [23:22] */
-#define BCHP_XPT_FE_MTSIF_RX2_BAND8_BAND11_ID_reserved1_MASK 0x00c00000
-#define BCHP_XPT_FE_MTSIF_RX2_BAND8_BAND11_ID_reserved1_SHIFT 22
-
-/* XPT_FE :: MTSIF_RX2_BAND8_BAND11_ID :: MTSIF_BAND10_BAND_ID [21:16] */
-#define BCHP_XPT_FE_MTSIF_RX2_BAND8_BAND11_ID_MTSIF_BAND10_BAND_ID_MASK 0x003f0000
-#define BCHP_XPT_FE_MTSIF_RX2_BAND8_BAND11_ID_MTSIF_BAND10_BAND_ID_SHIFT 16
-#define BCHP_XPT_FE_MTSIF_RX2_BAND8_BAND11_ID_MTSIF_BAND10_BAND_ID_DEFAULT 0x0000000a
-
-/* XPT_FE :: MTSIF_RX2_BAND8_BAND11_ID :: reserved2 [15:14] */
-#define BCHP_XPT_FE_MTSIF_RX2_BAND8_BAND11_ID_reserved2_MASK 0x0000c000
-#define BCHP_XPT_FE_MTSIF_RX2_BAND8_BAND11_ID_reserved2_SHIFT 14
-
-/* XPT_FE :: MTSIF_RX2_BAND8_BAND11_ID :: MTSIF_BAND9_BAND_ID [13:08] */
-#define BCHP_XPT_FE_MTSIF_RX2_BAND8_BAND11_ID_MTSIF_BAND9_BAND_ID_MASK 0x00003f00
-#define BCHP_XPT_FE_MTSIF_RX2_BAND8_BAND11_ID_MTSIF_BAND9_BAND_ID_SHIFT 8
-#define BCHP_XPT_FE_MTSIF_RX2_BAND8_BAND11_ID_MTSIF_BAND9_BAND_ID_DEFAULT 0x00000009
-
-/* XPT_FE :: MTSIF_RX2_BAND8_BAND11_ID :: reserved3 [07:06] */
-#define BCHP_XPT_FE_MTSIF_RX2_BAND8_BAND11_ID_reserved3_MASK 0x000000c0
-#define BCHP_XPT_FE_MTSIF_RX2_BAND8_BAND11_ID_reserved3_SHIFT 6
-
-/* XPT_FE :: MTSIF_RX2_BAND8_BAND11_ID :: MTSIF_BAND8_BAND_ID [05:00] */
-#define BCHP_XPT_FE_MTSIF_RX2_BAND8_BAND11_ID_MTSIF_BAND8_BAND_ID_MASK 0x0000003f
-#define BCHP_XPT_FE_MTSIF_RX2_BAND8_BAND11_ID_MTSIF_BAND8_BAND_ID_SHIFT 0
-#define BCHP_XPT_FE_MTSIF_RX2_BAND8_BAND11_ID_MTSIF_BAND8_BAND_ID_DEFAULT 0x00000008
-
-/***************************************************************************
- *MTSIF_RX2_BAND12_BAND15_ID - MTSIF RX2 Band12 to Band15 ID Register
- ***************************************************************************/
-/* XPT_FE :: MTSIF_RX2_BAND12_BAND15_ID :: reserved0 [31:30] */
-#define BCHP_XPT_FE_MTSIF_RX2_BAND12_BAND15_ID_reserved0_MASK 0xc0000000
-#define BCHP_XPT_FE_MTSIF_RX2_BAND12_BAND15_ID_reserved0_SHIFT 30
-
-/* XPT_FE :: MTSIF_RX2_BAND12_BAND15_ID :: MTSIF_BAND15_BAND_ID [29:24] */
-#define BCHP_XPT_FE_MTSIF_RX2_BAND12_BAND15_ID_MTSIF_BAND15_BAND_ID_MASK 0x3f000000
-#define BCHP_XPT_FE_MTSIF_RX2_BAND12_BAND15_ID_MTSIF_BAND15_BAND_ID_SHIFT 24
-#define BCHP_XPT_FE_MTSIF_RX2_BAND12_BAND15_ID_MTSIF_BAND15_BAND_ID_DEFAULT 0x0000000f
-
-/* XPT_FE :: MTSIF_RX2_BAND12_BAND15_ID :: reserved1 [23:22] */
-#define BCHP_XPT_FE_MTSIF_RX2_BAND12_BAND15_ID_reserved1_MASK 0x00c00000
-#define BCHP_XPT_FE_MTSIF_RX2_BAND12_BAND15_ID_reserved1_SHIFT 22
-
-/* XPT_FE :: MTSIF_RX2_BAND12_BAND15_ID :: MTSIF_BAND14_BAND_ID [21:16] */
-#define BCHP_XPT_FE_MTSIF_RX2_BAND12_BAND15_ID_MTSIF_BAND14_BAND_ID_MASK 0x003f0000
-#define BCHP_XPT_FE_MTSIF_RX2_BAND12_BAND15_ID_MTSIF_BAND14_BAND_ID_SHIFT 16
-#define BCHP_XPT_FE_MTSIF_RX2_BAND12_BAND15_ID_MTSIF_BAND14_BAND_ID_DEFAULT 0x0000000e
-
-/* XPT_FE :: MTSIF_RX2_BAND12_BAND15_ID :: reserved2 [15:14] */
-#define BCHP_XPT_FE_MTSIF_RX2_BAND12_BAND15_ID_reserved2_MASK 0x0000c000
-#define BCHP_XPT_FE_MTSIF_RX2_BAND12_BAND15_ID_reserved2_SHIFT 14
-
-/* XPT_FE :: MTSIF_RX2_BAND12_BAND15_ID :: MTSIF_BAND13_BAND_ID [13:08] */
-#define BCHP_XPT_FE_MTSIF_RX2_BAND12_BAND15_ID_MTSIF_BAND13_BAND_ID_MASK 0x00003f00
-#define BCHP_XPT_FE_MTSIF_RX2_BAND12_BAND15_ID_MTSIF_BAND13_BAND_ID_SHIFT 8
-#define BCHP_XPT_FE_MTSIF_RX2_BAND12_BAND15_ID_MTSIF_BAND13_BAND_ID_DEFAULT 0x0000000d
-
-/* XPT_FE :: MTSIF_RX2_BAND12_BAND15_ID :: reserved3 [07:06] */
-#define BCHP_XPT_FE_MTSIF_RX2_BAND12_BAND15_ID_reserved3_MASK 0x000000c0
-#define BCHP_XPT_FE_MTSIF_RX2_BAND12_BAND15_ID_reserved3_SHIFT 6
-
-/* XPT_FE :: MTSIF_RX2_BAND12_BAND15_ID :: MTSIF_BAND12_BAND_ID [05:00] */
-#define BCHP_XPT_FE_MTSIF_RX2_BAND12_BAND15_ID_MTSIF_BAND12_BAND_ID_MASK 0x0000003f
-#define BCHP_XPT_FE_MTSIF_RX2_BAND12_BAND15_ID_MTSIF_BAND12_BAND_ID_SHIFT 0
-#define BCHP_XPT_FE_MTSIF_RX2_BAND12_BAND15_ID_MTSIF_BAND12_BAND_ID_DEFAULT 0x0000000c
-
-/***************************************************************************
- *MTSIF_RX2_BAND16_BAND19_ID - MTSIF RX2 Band16 to Band19 ID Register
- ***************************************************************************/
-/* XPT_FE :: MTSIF_RX2_BAND16_BAND19_ID :: reserved0 [31:30] */
-#define BCHP_XPT_FE_MTSIF_RX2_BAND16_BAND19_ID_reserved0_MASK 0xc0000000
-#define BCHP_XPT_FE_MTSIF_RX2_BAND16_BAND19_ID_reserved0_SHIFT 30
-
-/* XPT_FE :: MTSIF_RX2_BAND16_BAND19_ID :: MTSIF_BAND19_BAND_ID [29:24] */
-#define BCHP_XPT_FE_MTSIF_RX2_BAND16_BAND19_ID_MTSIF_BAND19_BAND_ID_MASK 0x3f000000
-#define BCHP_XPT_FE_MTSIF_RX2_BAND16_BAND19_ID_MTSIF_BAND19_BAND_ID_SHIFT 24
-#define BCHP_XPT_FE_MTSIF_RX2_BAND16_BAND19_ID_MTSIF_BAND19_BAND_ID_DEFAULT 0x00000013
-
-/* XPT_FE :: MTSIF_RX2_BAND16_BAND19_ID :: reserved1 [23:22] */
-#define BCHP_XPT_FE_MTSIF_RX2_BAND16_BAND19_ID_reserved1_MASK 0x00c00000
-#define BCHP_XPT_FE_MTSIF_RX2_BAND16_BAND19_ID_reserved1_SHIFT 22
-
-/* XPT_FE :: MTSIF_RX2_BAND16_BAND19_ID :: MTSIF_BAND18_BAND_ID [21:16] */
-#define BCHP_XPT_FE_MTSIF_RX2_BAND16_BAND19_ID_MTSIF_BAND18_BAND_ID_MASK 0x003f0000
-#define BCHP_XPT_FE_MTSIF_RX2_BAND16_BAND19_ID_MTSIF_BAND18_BAND_ID_SHIFT 16
-#define BCHP_XPT_FE_MTSIF_RX2_BAND16_BAND19_ID_MTSIF_BAND18_BAND_ID_DEFAULT 0x00000012
-
-/* XPT_FE :: MTSIF_RX2_BAND16_BAND19_ID :: reserved2 [15:14] */
-#define BCHP_XPT_FE_MTSIF_RX2_BAND16_BAND19_ID_reserved2_MASK 0x0000c000
-#define BCHP_XPT_FE_MTSIF_RX2_BAND16_BAND19_ID_reserved2_SHIFT 14
-
-/* XPT_FE :: MTSIF_RX2_BAND16_BAND19_ID :: MTSIF_BAND17_BAND_ID [13:08] */
-#define BCHP_XPT_FE_MTSIF_RX2_BAND16_BAND19_ID_MTSIF_BAND17_BAND_ID_MASK 0x00003f00
-#define BCHP_XPT_FE_MTSIF_RX2_BAND16_BAND19_ID_MTSIF_BAND17_BAND_ID_SHIFT 8
-#define BCHP_XPT_FE_MTSIF_RX2_BAND16_BAND19_ID_MTSIF_BAND17_BAND_ID_DEFAULT 0x00000011
-
-/* XPT_FE :: MTSIF_RX2_BAND16_BAND19_ID :: reserved3 [07:06] */
-#define BCHP_XPT_FE_MTSIF_RX2_BAND16_BAND19_ID_reserved3_MASK 0x000000c0
-#define BCHP_XPT_FE_MTSIF_RX2_BAND16_BAND19_ID_reserved3_SHIFT 6
-
-/* XPT_FE :: MTSIF_RX2_BAND16_BAND19_ID :: MTSIF_BAND16_BAND_ID [05:00] */
-#define BCHP_XPT_FE_MTSIF_RX2_BAND16_BAND19_ID_MTSIF_BAND16_BAND_ID_MASK 0x0000003f
-#define BCHP_XPT_FE_MTSIF_RX2_BAND16_BAND19_ID_MTSIF_BAND16_BAND_ID_SHIFT 0
-#define BCHP_XPT_FE_MTSIF_RX2_BAND16_BAND19_ID_MTSIF_BAND16_BAND_ID_DEFAULT 0x00000010
-
-/***************************************************************************
- *MTSIF_RX2_BAND20_BAND23_ID - MTSIF RX2 Band20 to Band23 ID Register
- ***************************************************************************/
-/* XPT_FE :: MTSIF_RX2_BAND20_BAND23_ID :: reserved0 [31:30] */
-#define BCHP_XPT_FE_MTSIF_RX2_BAND20_BAND23_ID_reserved0_MASK 0xc0000000
-#define BCHP_XPT_FE_MTSIF_RX2_BAND20_BAND23_ID_reserved0_SHIFT 30
-
-/* XPT_FE :: MTSIF_RX2_BAND20_BAND23_ID :: MTSIF_BAND23_BAND_ID [29:24] */
-#define BCHP_XPT_FE_MTSIF_RX2_BAND20_BAND23_ID_MTSIF_BAND23_BAND_ID_MASK 0x3f000000
-#define BCHP_XPT_FE_MTSIF_RX2_BAND20_BAND23_ID_MTSIF_BAND23_BAND_ID_SHIFT 24
-#define BCHP_XPT_FE_MTSIF_RX2_BAND20_BAND23_ID_MTSIF_BAND23_BAND_ID_DEFAULT 0x00000017
-
-/* XPT_FE :: MTSIF_RX2_BAND20_BAND23_ID :: reserved1 [23:22] */
-#define BCHP_XPT_FE_MTSIF_RX2_BAND20_BAND23_ID_reserved1_MASK 0x00c00000
-#define BCHP_XPT_FE_MTSIF_RX2_BAND20_BAND23_ID_reserved1_SHIFT 22
-
-/* XPT_FE :: MTSIF_RX2_BAND20_BAND23_ID :: MTSIF_BAND22_BAND_ID [21:16] */
-#define BCHP_XPT_FE_MTSIF_RX2_BAND20_BAND23_ID_MTSIF_BAND22_BAND_ID_MASK 0x003f0000
-#define BCHP_XPT_FE_MTSIF_RX2_BAND20_BAND23_ID_MTSIF_BAND22_BAND_ID_SHIFT 16
-#define BCHP_XPT_FE_MTSIF_RX2_BAND20_BAND23_ID_MTSIF_BAND22_BAND_ID_DEFAULT 0x00000016
-
-/* XPT_FE :: MTSIF_RX2_BAND20_BAND23_ID :: reserved2 [15:14] */
-#define BCHP_XPT_FE_MTSIF_RX2_BAND20_BAND23_ID_reserved2_MASK 0x0000c000
-#define BCHP_XPT_FE_MTSIF_RX2_BAND20_BAND23_ID_reserved2_SHIFT 14
-
-/* XPT_FE :: MTSIF_RX2_BAND20_BAND23_ID :: MTSIF_BAND21_BAND_ID [13:08] */
-#define BCHP_XPT_FE_MTSIF_RX2_BAND20_BAND23_ID_MTSIF_BAND21_BAND_ID_MASK 0x00003f00
-#define BCHP_XPT_FE_MTSIF_RX2_BAND20_BAND23_ID_MTSIF_BAND21_BAND_ID_SHIFT 8
-#define BCHP_XPT_FE_MTSIF_RX2_BAND20_BAND23_ID_MTSIF_BAND21_BAND_ID_DEFAULT 0x00000015
-
-/* XPT_FE :: MTSIF_RX2_BAND20_BAND23_ID :: reserved3 [07:06] */
-#define BCHP_XPT_FE_MTSIF_RX2_BAND20_BAND23_ID_reserved3_MASK 0x000000c0
-#define BCHP_XPT_FE_MTSIF_RX2_BAND20_BAND23_ID_reserved3_SHIFT 6
-
-/* XPT_FE :: MTSIF_RX2_BAND20_BAND23_ID :: MTSIF_BAND20_BAND_ID [05:00] */
-#define BCHP_XPT_FE_MTSIF_RX2_BAND20_BAND23_ID_MTSIF_BAND20_BAND_ID_MASK 0x0000003f
-#define BCHP_XPT_FE_MTSIF_RX2_BAND20_BAND23_ID_MTSIF_BAND20_BAND_ID_SHIFT 0
-#define BCHP_XPT_FE_MTSIF_RX2_BAND20_BAND23_ID_MTSIF_BAND20_BAND_ID_DEFAULT 0x00000014
-
-/***************************************************************************
- *MTSIF_RX2_BAND24_BAND27_ID - MTSIF RX2 Band24 to Band27 ID Register
- ***************************************************************************/
-/* XPT_FE :: MTSIF_RX2_BAND24_BAND27_ID :: reserved0 [31:30] */
-#define BCHP_XPT_FE_MTSIF_RX2_BAND24_BAND27_ID_reserved0_MASK 0xc0000000
-#define BCHP_XPT_FE_MTSIF_RX2_BAND24_BAND27_ID_reserved0_SHIFT 30
-
-/* XPT_FE :: MTSIF_RX2_BAND24_BAND27_ID :: MTSIF_BAND27_BAND_ID [29:24] */
-#define BCHP_XPT_FE_MTSIF_RX2_BAND24_BAND27_ID_MTSIF_BAND27_BAND_ID_MASK 0x3f000000
-#define BCHP_XPT_FE_MTSIF_RX2_BAND24_BAND27_ID_MTSIF_BAND27_BAND_ID_SHIFT 24
-#define BCHP_XPT_FE_MTSIF_RX2_BAND24_BAND27_ID_MTSIF_BAND27_BAND_ID_DEFAULT 0x0000001b
-
-/* XPT_FE :: MTSIF_RX2_BAND24_BAND27_ID :: reserved1 [23:22] */
-#define BCHP_XPT_FE_MTSIF_RX2_BAND24_BAND27_ID_reserved1_MASK 0x00c00000
-#define BCHP_XPT_FE_MTSIF_RX2_BAND24_BAND27_ID_reserved1_SHIFT 22
-
-/* XPT_FE :: MTSIF_RX2_BAND24_BAND27_ID :: MTSIF_BAND26_BAND_ID [21:16] */
-#define BCHP_XPT_FE_MTSIF_RX2_BAND24_BAND27_ID_MTSIF_BAND26_BAND_ID_MASK 0x003f0000
-#define BCHP_XPT_FE_MTSIF_RX2_BAND24_BAND27_ID_MTSIF_BAND26_BAND_ID_SHIFT 16
-#define BCHP_XPT_FE_MTSIF_RX2_BAND24_BAND27_ID_MTSIF_BAND26_BAND_ID_DEFAULT 0x0000001a
-
-/* XPT_FE :: MTSIF_RX2_BAND24_BAND27_ID :: reserved2 [15:14] */
-#define BCHP_XPT_FE_MTSIF_RX2_BAND24_BAND27_ID_reserved2_MASK 0x0000c000
-#define BCHP_XPT_FE_MTSIF_RX2_BAND24_BAND27_ID_reserved2_SHIFT 14
-
-/* XPT_FE :: MTSIF_RX2_BAND24_BAND27_ID :: MTSIF_BAND25_BAND_ID [13:08] */
-#define BCHP_XPT_FE_MTSIF_RX2_BAND24_BAND27_ID_MTSIF_BAND25_BAND_ID_MASK 0x00003f00
-#define BCHP_XPT_FE_MTSIF_RX2_BAND24_BAND27_ID_MTSIF_BAND25_BAND_ID_SHIFT 8
-#define BCHP_XPT_FE_MTSIF_RX2_BAND24_BAND27_ID_MTSIF_BAND25_BAND_ID_DEFAULT 0x00000019
-
-/* XPT_FE :: MTSIF_RX2_BAND24_BAND27_ID :: reserved3 [07:06] */
-#define BCHP_XPT_FE_MTSIF_RX2_BAND24_BAND27_ID_reserved3_MASK 0x000000c0
-#define BCHP_XPT_FE_MTSIF_RX2_BAND24_BAND27_ID_reserved3_SHIFT 6
-
-/* XPT_FE :: MTSIF_RX2_BAND24_BAND27_ID :: MTSIF_BAND24_BAND_ID [05:00] */
-#define BCHP_XPT_FE_MTSIF_RX2_BAND24_BAND27_ID_MTSIF_BAND24_BAND_ID_MASK 0x0000003f
-#define BCHP_XPT_FE_MTSIF_RX2_BAND24_BAND27_ID_MTSIF_BAND24_BAND_ID_SHIFT 0
-#define BCHP_XPT_FE_MTSIF_RX2_BAND24_BAND27_ID_MTSIF_BAND24_BAND_ID_DEFAULT 0x00000018
-
-/***************************************************************************
- *MTSIF_RX2_BAND28_BAND31_ID - MTSIF RX2 Band28 to Band31 ID Register
- ***************************************************************************/
-/* XPT_FE :: MTSIF_RX2_BAND28_BAND31_ID :: reserved0 [31:30] */
-#define BCHP_XPT_FE_MTSIF_RX2_BAND28_BAND31_ID_reserved0_MASK 0xc0000000
-#define BCHP_XPT_FE_MTSIF_RX2_BAND28_BAND31_ID_reserved0_SHIFT 30
-
-/* XPT_FE :: MTSIF_RX2_BAND28_BAND31_ID :: MTSIF_BAND31_BAND_ID [29:24] */
-#define BCHP_XPT_FE_MTSIF_RX2_BAND28_BAND31_ID_MTSIF_BAND31_BAND_ID_MASK 0x3f000000
-#define BCHP_XPT_FE_MTSIF_RX2_BAND28_BAND31_ID_MTSIF_BAND31_BAND_ID_SHIFT 24
-#define BCHP_XPT_FE_MTSIF_RX2_BAND28_BAND31_ID_MTSIF_BAND31_BAND_ID_DEFAULT 0x0000001f
-
-/* XPT_FE :: MTSIF_RX2_BAND28_BAND31_ID :: reserved1 [23:22] */
-#define BCHP_XPT_FE_MTSIF_RX2_BAND28_BAND31_ID_reserved1_MASK 0x00c00000
-#define BCHP_XPT_FE_MTSIF_RX2_BAND28_BAND31_ID_reserved1_SHIFT 22
-
-/* XPT_FE :: MTSIF_RX2_BAND28_BAND31_ID :: MTSIF_BAND30_BAND_ID [21:16] */
-#define BCHP_XPT_FE_MTSIF_RX2_BAND28_BAND31_ID_MTSIF_BAND30_BAND_ID_MASK 0x003f0000
-#define BCHP_XPT_FE_MTSIF_RX2_BAND28_BAND31_ID_MTSIF_BAND30_BAND_ID_SHIFT 16
-#define BCHP_XPT_FE_MTSIF_RX2_BAND28_BAND31_ID_MTSIF_BAND30_BAND_ID_DEFAULT 0x0000001e
-
-/* XPT_FE :: MTSIF_RX2_BAND28_BAND31_ID :: reserved2 [15:14] */
-#define BCHP_XPT_FE_MTSIF_RX2_BAND28_BAND31_ID_reserved2_MASK 0x0000c000
-#define BCHP_XPT_FE_MTSIF_RX2_BAND28_BAND31_ID_reserved2_SHIFT 14
-
-/* XPT_FE :: MTSIF_RX2_BAND28_BAND31_ID :: MTSIF_BAND29_BAND_ID [13:08] */
-#define BCHP_XPT_FE_MTSIF_RX2_BAND28_BAND31_ID_MTSIF_BAND29_BAND_ID_MASK 0x00003f00
-#define BCHP_XPT_FE_MTSIF_RX2_BAND28_BAND31_ID_MTSIF_BAND29_BAND_ID_SHIFT 8
-#define BCHP_XPT_FE_MTSIF_RX2_BAND28_BAND31_ID_MTSIF_BAND29_BAND_ID_DEFAULT 0x0000001d
-
-/* XPT_FE :: MTSIF_RX2_BAND28_BAND31_ID :: reserved3 [07:06] */
-#define BCHP_XPT_FE_MTSIF_RX2_BAND28_BAND31_ID_reserved3_MASK 0x000000c0
-#define BCHP_XPT_FE_MTSIF_RX2_BAND28_BAND31_ID_reserved3_SHIFT 6
-
-/* XPT_FE :: MTSIF_RX2_BAND28_BAND31_ID :: MTSIF_BAND28_BAND_ID [05:00] */
-#define BCHP_XPT_FE_MTSIF_RX2_BAND28_BAND31_ID_MTSIF_BAND28_BAND_ID_MASK 0x0000003f
-#define BCHP_XPT_FE_MTSIF_RX2_BAND28_BAND31_ID_MTSIF_BAND28_BAND_ID_SHIFT 0
-#define BCHP_XPT_FE_MTSIF_RX2_BAND28_BAND31_ID_MTSIF_BAND28_BAND_ID_DEFAULT 0x0000001c
-
-/***************************************************************************
- *MTSIF_RX2_BAND32_BAND35_ID - MTSIF RX2 Band32 to Band35 ID Register
- ***************************************************************************/
-/* XPT_FE :: MTSIF_RX2_BAND32_BAND35_ID :: reserved0 [31:30] */
-#define BCHP_XPT_FE_MTSIF_RX2_BAND32_BAND35_ID_reserved0_MASK 0xc0000000
-#define BCHP_XPT_FE_MTSIF_RX2_BAND32_BAND35_ID_reserved0_SHIFT 30
-
-/* XPT_FE :: MTSIF_RX2_BAND32_BAND35_ID :: MTSIF_BAND35_BAND_ID [29:24] */
-#define BCHP_XPT_FE_MTSIF_RX2_BAND32_BAND35_ID_MTSIF_BAND35_BAND_ID_MASK 0x3f000000
-#define BCHP_XPT_FE_MTSIF_RX2_BAND32_BAND35_ID_MTSIF_BAND35_BAND_ID_SHIFT 24
-#define BCHP_XPT_FE_MTSIF_RX2_BAND32_BAND35_ID_MTSIF_BAND35_BAND_ID_DEFAULT 0x00000023
-
-/* XPT_FE :: MTSIF_RX2_BAND32_BAND35_ID :: reserved1 [23:22] */
-#define BCHP_XPT_FE_MTSIF_RX2_BAND32_BAND35_ID_reserved1_MASK 0x00c00000
-#define BCHP_XPT_FE_MTSIF_RX2_BAND32_BAND35_ID_reserved1_SHIFT 22
-
-/* XPT_FE :: MTSIF_RX2_BAND32_BAND35_ID :: MTSIF_BAND34_BAND_ID [21:16] */
-#define BCHP_XPT_FE_MTSIF_RX2_BAND32_BAND35_ID_MTSIF_BAND34_BAND_ID_MASK 0x003f0000
-#define BCHP_XPT_FE_MTSIF_RX2_BAND32_BAND35_ID_MTSIF_BAND34_BAND_ID_SHIFT 16
-#define BCHP_XPT_FE_MTSIF_RX2_BAND32_BAND35_ID_MTSIF_BAND34_BAND_ID_DEFAULT 0x00000022
-
-/* XPT_FE :: MTSIF_RX2_BAND32_BAND35_ID :: reserved2 [15:14] */
-#define BCHP_XPT_FE_MTSIF_RX2_BAND32_BAND35_ID_reserved2_MASK 0x0000c000
-#define BCHP_XPT_FE_MTSIF_RX2_BAND32_BAND35_ID_reserved2_SHIFT 14
-
-/* XPT_FE :: MTSIF_RX2_BAND32_BAND35_ID :: MTSIF_BAND33_BAND_ID [13:08] */
-#define BCHP_XPT_FE_MTSIF_RX2_BAND32_BAND35_ID_MTSIF_BAND33_BAND_ID_MASK 0x00003f00
-#define BCHP_XPT_FE_MTSIF_RX2_BAND32_BAND35_ID_MTSIF_BAND33_BAND_ID_SHIFT 8
-#define BCHP_XPT_FE_MTSIF_RX2_BAND32_BAND35_ID_MTSIF_BAND33_BAND_ID_DEFAULT 0x00000021
-
-/* XPT_FE :: MTSIF_RX2_BAND32_BAND35_ID :: reserved3 [07:06] */
-#define BCHP_XPT_FE_MTSIF_RX2_BAND32_BAND35_ID_reserved3_MASK 0x000000c0
-#define BCHP_XPT_FE_MTSIF_RX2_BAND32_BAND35_ID_reserved3_SHIFT 6
-
-/* XPT_FE :: MTSIF_RX2_BAND32_BAND35_ID :: MTSIF_BAND32_BAND_ID [05:00] */
-#define BCHP_XPT_FE_MTSIF_RX2_BAND32_BAND35_ID_MTSIF_BAND32_BAND_ID_MASK 0x0000003f
-#define BCHP_XPT_FE_MTSIF_RX2_BAND32_BAND35_ID_MTSIF_BAND32_BAND_ID_SHIFT 0
-#define BCHP_XPT_FE_MTSIF_RX2_BAND32_BAND35_ID_MTSIF_BAND32_BAND_ID_DEFAULT 0x00000020
-
-/***************************************************************************
- *MTSIF_RX2_BAND36_BAND39_ID - MTSIF RX2 Band36 to Band39 ID Register
- ***************************************************************************/
-/* XPT_FE :: MTSIF_RX2_BAND36_BAND39_ID :: reserved0 [31:30] */
-#define BCHP_XPT_FE_MTSIF_RX2_BAND36_BAND39_ID_reserved0_MASK 0xc0000000
-#define BCHP_XPT_FE_MTSIF_RX2_BAND36_BAND39_ID_reserved0_SHIFT 30
-
-/* XPT_FE :: MTSIF_RX2_BAND36_BAND39_ID :: MTSIF_BAND39_BAND_ID [29:24] */
-#define BCHP_XPT_FE_MTSIF_RX2_BAND36_BAND39_ID_MTSIF_BAND39_BAND_ID_MASK 0x3f000000
-#define BCHP_XPT_FE_MTSIF_RX2_BAND36_BAND39_ID_MTSIF_BAND39_BAND_ID_SHIFT 24
-#define BCHP_XPT_FE_MTSIF_RX2_BAND36_BAND39_ID_MTSIF_BAND39_BAND_ID_DEFAULT 0x00000027
-
-/* XPT_FE :: MTSIF_RX2_BAND36_BAND39_ID :: reserved1 [23:22] */
-#define BCHP_XPT_FE_MTSIF_RX2_BAND36_BAND39_ID_reserved1_MASK 0x00c00000
-#define BCHP_XPT_FE_MTSIF_RX2_BAND36_BAND39_ID_reserved1_SHIFT 22
-
-/* XPT_FE :: MTSIF_RX2_BAND36_BAND39_ID :: MTSIF_BAND38_BAND_ID [21:16] */
-#define BCHP_XPT_FE_MTSIF_RX2_BAND36_BAND39_ID_MTSIF_BAND38_BAND_ID_MASK 0x003f0000
-#define BCHP_XPT_FE_MTSIF_RX2_BAND36_BAND39_ID_MTSIF_BAND38_BAND_ID_SHIFT 16
-#define BCHP_XPT_FE_MTSIF_RX2_BAND36_BAND39_ID_MTSIF_BAND38_BAND_ID_DEFAULT 0x00000026
-
-/* XPT_FE :: MTSIF_RX2_BAND36_BAND39_ID :: reserved2 [15:14] */
-#define BCHP_XPT_FE_MTSIF_RX2_BAND36_BAND39_ID_reserved2_MASK 0x0000c000
-#define BCHP_XPT_FE_MTSIF_RX2_BAND36_BAND39_ID_reserved2_SHIFT 14
-
-/* XPT_FE :: MTSIF_RX2_BAND36_BAND39_ID :: MTSIF_BAND37_BAND_ID [13:08] */
-#define BCHP_XPT_FE_MTSIF_RX2_BAND36_BAND39_ID_MTSIF_BAND37_BAND_ID_MASK 0x00003f00
-#define BCHP_XPT_FE_MTSIF_RX2_BAND36_BAND39_ID_MTSIF_BAND37_BAND_ID_SHIFT 8
-#define BCHP_XPT_FE_MTSIF_RX2_BAND36_BAND39_ID_MTSIF_BAND37_BAND_ID_DEFAULT 0x00000025
-
-/* XPT_FE :: MTSIF_RX2_BAND36_BAND39_ID :: reserved3 [07:06] */
-#define BCHP_XPT_FE_MTSIF_RX2_BAND36_BAND39_ID_reserved3_MASK 0x000000c0
-#define BCHP_XPT_FE_MTSIF_RX2_BAND36_BAND39_ID_reserved3_SHIFT 6
-
-/* XPT_FE :: MTSIF_RX2_BAND36_BAND39_ID :: MTSIF_BAND36_BAND_ID [05:00] */
-#define BCHP_XPT_FE_MTSIF_RX2_BAND36_BAND39_ID_MTSIF_BAND36_BAND_ID_MASK 0x0000003f
-#define BCHP_XPT_FE_MTSIF_RX2_BAND36_BAND39_ID_MTSIF_BAND36_BAND_ID_SHIFT 0
-#define BCHP_XPT_FE_MTSIF_RX2_BAND36_BAND39_ID_MTSIF_BAND36_BAND_ID_DEFAULT 0x00000024
-
-/***************************************************************************
- *MTSIF_RX2_BAND40_BAND43_ID - MTSIF RX2 Band40 to Band43 ID Register
- ***************************************************************************/
-/* XPT_FE :: MTSIF_RX2_BAND40_BAND43_ID :: reserved0 [31:30] */
-#define BCHP_XPT_FE_MTSIF_RX2_BAND40_BAND43_ID_reserved0_MASK 0xc0000000
-#define BCHP_XPT_FE_MTSIF_RX2_BAND40_BAND43_ID_reserved0_SHIFT 30
-
-/* XPT_FE :: MTSIF_RX2_BAND40_BAND43_ID :: MTSIF_BAND43_BAND_ID [29:24] */
-#define BCHP_XPT_FE_MTSIF_RX2_BAND40_BAND43_ID_MTSIF_BAND43_BAND_ID_MASK 0x3f000000
-#define BCHP_XPT_FE_MTSIF_RX2_BAND40_BAND43_ID_MTSIF_BAND43_BAND_ID_SHIFT 24
-#define BCHP_XPT_FE_MTSIF_RX2_BAND40_BAND43_ID_MTSIF_BAND43_BAND_ID_DEFAULT 0x0000002b
-
-/* XPT_FE :: MTSIF_RX2_BAND40_BAND43_ID :: reserved1 [23:22] */
-#define BCHP_XPT_FE_MTSIF_RX2_BAND40_BAND43_ID_reserved1_MASK 0x00c00000
-#define BCHP_XPT_FE_MTSIF_RX2_BAND40_BAND43_ID_reserved1_SHIFT 22
-
-/* XPT_FE :: MTSIF_RX2_BAND40_BAND43_ID :: MTSIF_BAND42_BAND_ID [21:16] */
-#define BCHP_XPT_FE_MTSIF_RX2_BAND40_BAND43_ID_MTSIF_BAND42_BAND_ID_MASK 0x003f0000
-#define BCHP_XPT_FE_MTSIF_RX2_BAND40_BAND43_ID_MTSIF_BAND42_BAND_ID_SHIFT 16
-#define BCHP_XPT_FE_MTSIF_RX2_BAND40_BAND43_ID_MTSIF_BAND42_BAND_ID_DEFAULT 0x0000002a
-
-/* XPT_FE :: MTSIF_RX2_BAND40_BAND43_ID :: reserved2 [15:14] */
-#define BCHP_XPT_FE_MTSIF_RX2_BAND40_BAND43_ID_reserved2_MASK 0x0000c000
-#define BCHP_XPT_FE_MTSIF_RX2_BAND40_BAND43_ID_reserved2_SHIFT 14
-
-/* XPT_FE :: MTSIF_RX2_BAND40_BAND43_ID :: MTSIF_BAND41_BAND_ID [13:08] */
-#define BCHP_XPT_FE_MTSIF_RX2_BAND40_BAND43_ID_MTSIF_BAND41_BAND_ID_MASK 0x00003f00
-#define BCHP_XPT_FE_MTSIF_RX2_BAND40_BAND43_ID_MTSIF_BAND41_BAND_ID_SHIFT 8
-#define BCHP_XPT_FE_MTSIF_RX2_BAND40_BAND43_ID_MTSIF_BAND41_BAND_ID_DEFAULT 0x00000029
-
-/* XPT_FE :: MTSIF_RX2_BAND40_BAND43_ID :: reserved3 [07:06] */
-#define BCHP_XPT_FE_MTSIF_RX2_BAND40_BAND43_ID_reserved3_MASK 0x000000c0
-#define BCHP_XPT_FE_MTSIF_RX2_BAND40_BAND43_ID_reserved3_SHIFT 6
-
-/* XPT_FE :: MTSIF_RX2_BAND40_BAND43_ID :: MTSIF_BAND40_BAND_ID [05:00] */
-#define BCHP_XPT_FE_MTSIF_RX2_BAND40_BAND43_ID_MTSIF_BAND40_BAND_ID_MASK 0x0000003f
-#define BCHP_XPT_FE_MTSIF_RX2_BAND40_BAND43_ID_MTSIF_BAND40_BAND_ID_SHIFT 0
-#define BCHP_XPT_FE_MTSIF_RX2_BAND40_BAND43_ID_MTSIF_BAND40_BAND_ID_DEFAULT 0x00000028
-
-/***************************************************************************
- *MTSIF_RX2_BAND44_BAND47_ID - MTSIF RX2 Band44 to Band47 ID Register
- ***************************************************************************/
-/* XPT_FE :: MTSIF_RX2_BAND44_BAND47_ID :: reserved0 [31:30] */
-#define BCHP_XPT_FE_MTSIF_RX2_BAND44_BAND47_ID_reserved0_MASK 0xc0000000
-#define BCHP_XPT_FE_MTSIF_RX2_BAND44_BAND47_ID_reserved0_SHIFT 30
-
-/* XPT_FE :: MTSIF_RX2_BAND44_BAND47_ID :: MTSIF_BAND47_BAND_ID [29:24] */
-#define BCHP_XPT_FE_MTSIF_RX2_BAND44_BAND47_ID_MTSIF_BAND47_BAND_ID_MASK 0x3f000000
-#define BCHP_XPT_FE_MTSIF_RX2_BAND44_BAND47_ID_MTSIF_BAND47_BAND_ID_SHIFT 24
-#define BCHP_XPT_FE_MTSIF_RX2_BAND44_BAND47_ID_MTSIF_BAND47_BAND_ID_DEFAULT 0x0000002f
-
-/* XPT_FE :: MTSIF_RX2_BAND44_BAND47_ID :: reserved1 [23:22] */
-#define BCHP_XPT_FE_MTSIF_RX2_BAND44_BAND47_ID_reserved1_MASK 0x00c00000
-#define BCHP_XPT_FE_MTSIF_RX2_BAND44_BAND47_ID_reserved1_SHIFT 22
-
-/* XPT_FE :: MTSIF_RX2_BAND44_BAND47_ID :: MTSIF_BAND46_BAND_ID [21:16] */
-#define BCHP_XPT_FE_MTSIF_RX2_BAND44_BAND47_ID_MTSIF_BAND46_BAND_ID_MASK 0x003f0000
-#define BCHP_XPT_FE_MTSIF_RX2_BAND44_BAND47_ID_MTSIF_BAND46_BAND_ID_SHIFT 16
-#define BCHP_XPT_FE_MTSIF_RX2_BAND44_BAND47_ID_MTSIF_BAND46_BAND_ID_DEFAULT 0x0000002e
-
-/* XPT_FE :: MTSIF_RX2_BAND44_BAND47_ID :: reserved2 [15:14] */
-#define BCHP_XPT_FE_MTSIF_RX2_BAND44_BAND47_ID_reserved2_MASK 0x0000c000
-#define BCHP_XPT_FE_MTSIF_RX2_BAND44_BAND47_ID_reserved2_SHIFT 14
-
-/* XPT_FE :: MTSIF_RX2_BAND44_BAND47_ID :: MTSIF_BAND45_BAND_ID [13:08] */
-#define BCHP_XPT_FE_MTSIF_RX2_BAND44_BAND47_ID_MTSIF_BAND45_BAND_ID_MASK 0x00003f00
-#define BCHP_XPT_FE_MTSIF_RX2_BAND44_BAND47_ID_MTSIF_BAND45_BAND_ID_SHIFT 8
-#define BCHP_XPT_FE_MTSIF_RX2_BAND44_BAND47_ID_MTSIF_BAND45_BAND_ID_DEFAULT 0x0000002d
-
-/* XPT_FE :: MTSIF_RX2_BAND44_BAND47_ID :: reserved3 [07:06] */
-#define BCHP_XPT_FE_MTSIF_RX2_BAND44_BAND47_ID_reserved3_MASK 0x000000c0
-#define BCHP_XPT_FE_MTSIF_RX2_BAND44_BAND47_ID_reserved3_SHIFT 6
-
-/* XPT_FE :: MTSIF_RX2_BAND44_BAND47_ID :: MTSIF_BAND44_BAND_ID [05:00] */
-#define BCHP_XPT_FE_MTSIF_RX2_BAND44_BAND47_ID_MTSIF_BAND44_BAND_ID_MASK 0x0000003f
-#define BCHP_XPT_FE_MTSIF_RX2_BAND44_BAND47_ID_MTSIF_BAND44_BAND_ID_SHIFT 0
-#define BCHP_XPT_FE_MTSIF_RX2_BAND44_BAND47_ID_MTSIF_BAND44_BAND_ID_DEFAULT 0x0000002c
-
-/***************************************************************************
- *MTSIF_RX2_BAND48_BAND51_ID - MTSIF RX2 Band48 to Band51 ID Register
- ***************************************************************************/
-/* XPT_FE :: MTSIF_RX2_BAND48_BAND51_ID :: reserved0 [31:30] */
-#define BCHP_XPT_FE_MTSIF_RX2_BAND48_BAND51_ID_reserved0_MASK 0xc0000000
-#define BCHP_XPT_FE_MTSIF_RX2_BAND48_BAND51_ID_reserved0_SHIFT 30
-
-/* XPT_FE :: MTSIF_RX2_BAND48_BAND51_ID :: MTSIF_BAND51_BAND_ID [29:24] */
-#define BCHP_XPT_FE_MTSIF_RX2_BAND48_BAND51_ID_MTSIF_BAND51_BAND_ID_MASK 0x3f000000
-#define BCHP_XPT_FE_MTSIF_RX2_BAND48_BAND51_ID_MTSIF_BAND51_BAND_ID_SHIFT 24
-#define BCHP_XPT_FE_MTSIF_RX2_BAND48_BAND51_ID_MTSIF_BAND51_BAND_ID_DEFAULT 0x00000033
-
-/* XPT_FE :: MTSIF_RX2_BAND48_BAND51_ID :: reserved1 [23:22] */
-#define BCHP_XPT_FE_MTSIF_RX2_BAND48_BAND51_ID_reserved1_MASK 0x00c00000
-#define BCHP_XPT_FE_MTSIF_RX2_BAND48_BAND51_ID_reserved1_SHIFT 22
-
-/* XPT_FE :: MTSIF_RX2_BAND48_BAND51_ID :: MTSIF_BAND50_BAND_ID [21:16] */
-#define BCHP_XPT_FE_MTSIF_RX2_BAND48_BAND51_ID_MTSIF_BAND50_BAND_ID_MASK 0x003f0000
-#define BCHP_XPT_FE_MTSIF_RX2_BAND48_BAND51_ID_MTSIF_BAND50_BAND_ID_SHIFT 16
-#define BCHP_XPT_FE_MTSIF_RX2_BAND48_BAND51_ID_MTSIF_BAND50_BAND_ID_DEFAULT 0x00000032
-
-/* XPT_FE :: MTSIF_RX2_BAND48_BAND51_ID :: reserved2 [15:14] */
-#define BCHP_XPT_FE_MTSIF_RX2_BAND48_BAND51_ID_reserved2_MASK 0x0000c000
-#define BCHP_XPT_FE_MTSIF_RX2_BAND48_BAND51_ID_reserved2_SHIFT 14
-
-/* XPT_FE :: MTSIF_RX2_BAND48_BAND51_ID :: MTSIF_BAND49_BAND_ID [13:08] */
-#define BCHP_XPT_FE_MTSIF_RX2_BAND48_BAND51_ID_MTSIF_BAND49_BAND_ID_MASK 0x00003f00
-#define BCHP_XPT_FE_MTSIF_RX2_BAND48_BAND51_ID_MTSIF_BAND49_BAND_ID_SHIFT 8
-#define BCHP_XPT_FE_MTSIF_RX2_BAND48_BAND51_ID_MTSIF_BAND49_BAND_ID_DEFAULT 0x00000031
-
-/* XPT_FE :: MTSIF_RX2_BAND48_BAND51_ID :: reserved3 [07:06] */
-#define BCHP_XPT_FE_MTSIF_RX2_BAND48_BAND51_ID_reserved3_MASK 0x000000c0
-#define BCHP_XPT_FE_MTSIF_RX2_BAND48_BAND51_ID_reserved3_SHIFT 6
-
-/* XPT_FE :: MTSIF_RX2_BAND48_BAND51_ID :: MTSIF_BAND48_BAND_ID [05:00] */
-#define BCHP_XPT_FE_MTSIF_RX2_BAND48_BAND51_ID_MTSIF_BAND48_BAND_ID_MASK 0x0000003f
-#define BCHP_XPT_FE_MTSIF_RX2_BAND48_BAND51_ID_MTSIF_BAND48_BAND_ID_SHIFT 0
-#define BCHP_XPT_FE_MTSIF_RX2_BAND48_BAND51_ID_MTSIF_BAND48_BAND_ID_DEFAULT 0x00000030
-
-/***************************************************************************
- *MTSIF_RX2_BAND52_BAND55_ID - MTSIF RX2 Band52 to Band55 ID Register
- ***************************************************************************/
-/* XPT_FE :: MTSIF_RX2_BAND52_BAND55_ID :: reserved0 [31:30] */
-#define BCHP_XPT_FE_MTSIF_RX2_BAND52_BAND55_ID_reserved0_MASK 0xc0000000
-#define BCHP_XPT_FE_MTSIF_RX2_BAND52_BAND55_ID_reserved0_SHIFT 30
-
-/* XPT_FE :: MTSIF_RX2_BAND52_BAND55_ID :: MTSIF_BAND55_BAND_ID [29:24] */
-#define BCHP_XPT_FE_MTSIF_RX2_BAND52_BAND55_ID_MTSIF_BAND55_BAND_ID_MASK 0x3f000000
-#define BCHP_XPT_FE_MTSIF_RX2_BAND52_BAND55_ID_MTSIF_BAND55_BAND_ID_SHIFT 24
-#define BCHP_XPT_FE_MTSIF_RX2_BAND52_BAND55_ID_MTSIF_BAND55_BAND_ID_DEFAULT 0x00000037
-
-/* XPT_FE :: MTSIF_RX2_BAND52_BAND55_ID :: reserved1 [23:22] */
-#define BCHP_XPT_FE_MTSIF_RX2_BAND52_BAND55_ID_reserved1_MASK 0x00c00000
-#define BCHP_XPT_FE_MTSIF_RX2_BAND52_BAND55_ID_reserved1_SHIFT 22
-
-/* XPT_FE :: MTSIF_RX2_BAND52_BAND55_ID :: MTSIF_BAND54_BAND_ID [21:16] */
-#define BCHP_XPT_FE_MTSIF_RX2_BAND52_BAND55_ID_MTSIF_BAND54_BAND_ID_MASK 0x003f0000
-#define BCHP_XPT_FE_MTSIF_RX2_BAND52_BAND55_ID_MTSIF_BAND54_BAND_ID_SHIFT 16
-#define BCHP_XPT_FE_MTSIF_RX2_BAND52_BAND55_ID_MTSIF_BAND54_BAND_ID_DEFAULT 0x00000036
-
-/* XPT_FE :: MTSIF_RX2_BAND52_BAND55_ID :: reserved2 [15:14] */
-#define BCHP_XPT_FE_MTSIF_RX2_BAND52_BAND55_ID_reserved2_MASK 0x0000c000
-#define BCHP_XPT_FE_MTSIF_RX2_BAND52_BAND55_ID_reserved2_SHIFT 14
-
-/* XPT_FE :: MTSIF_RX2_BAND52_BAND55_ID :: MTSIF_BAND53_BAND_ID [13:08] */
-#define BCHP_XPT_FE_MTSIF_RX2_BAND52_BAND55_ID_MTSIF_BAND53_BAND_ID_MASK 0x00003f00
-#define BCHP_XPT_FE_MTSIF_RX2_BAND52_BAND55_ID_MTSIF_BAND53_BAND_ID_SHIFT 8
-#define BCHP_XPT_FE_MTSIF_RX2_BAND52_BAND55_ID_MTSIF_BAND53_BAND_ID_DEFAULT 0x00000035
-
-/* XPT_FE :: MTSIF_RX2_BAND52_BAND55_ID :: reserved3 [07:06] */
-#define BCHP_XPT_FE_MTSIF_RX2_BAND52_BAND55_ID_reserved3_MASK 0x000000c0
-#define BCHP_XPT_FE_MTSIF_RX2_BAND52_BAND55_ID_reserved3_SHIFT 6
-
-/* XPT_FE :: MTSIF_RX2_BAND52_BAND55_ID :: MTSIF_BAND52_BAND_ID [05:00] */
-#define BCHP_XPT_FE_MTSIF_RX2_BAND52_BAND55_ID_MTSIF_BAND52_BAND_ID_MASK 0x0000003f
-#define BCHP_XPT_FE_MTSIF_RX2_BAND52_BAND55_ID_MTSIF_BAND52_BAND_ID_SHIFT 0
-#define BCHP_XPT_FE_MTSIF_RX2_BAND52_BAND55_ID_MTSIF_BAND52_BAND_ID_DEFAULT 0x00000034
-
-/***************************************************************************
- *MTSIF_RX2_BAND56_BAND59_ID - MTSIF RX2 Band56 to Band59 ID Register
- ***************************************************************************/
-/* XPT_FE :: MTSIF_RX2_BAND56_BAND59_ID :: reserved0 [31:30] */
-#define BCHP_XPT_FE_MTSIF_RX2_BAND56_BAND59_ID_reserved0_MASK 0xc0000000
-#define BCHP_XPT_FE_MTSIF_RX2_BAND56_BAND59_ID_reserved0_SHIFT 30
-
-/* XPT_FE :: MTSIF_RX2_BAND56_BAND59_ID :: MTSIF_BAND59_BAND_ID [29:24] */
-#define BCHP_XPT_FE_MTSIF_RX2_BAND56_BAND59_ID_MTSIF_BAND59_BAND_ID_MASK 0x3f000000
-#define BCHP_XPT_FE_MTSIF_RX2_BAND56_BAND59_ID_MTSIF_BAND59_BAND_ID_SHIFT 24
-#define BCHP_XPT_FE_MTSIF_RX2_BAND56_BAND59_ID_MTSIF_BAND59_BAND_ID_DEFAULT 0x0000003b
-
-/* XPT_FE :: MTSIF_RX2_BAND56_BAND59_ID :: reserved1 [23:22] */
-#define BCHP_XPT_FE_MTSIF_RX2_BAND56_BAND59_ID_reserved1_MASK 0x00c00000
-#define BCHP_XPT_FE_MTSIF_RX2_BAND56_BAND59_ID_reserved1_SHIFT 22
-
-/* XPT_FE :: MTSIF_RX2_BAND56_BAND59_ID :: MTSIF_BAND58_BAND_ID [21:16] */
-#define BCHP_XPT_FE_MTSIF_RX2_BAND56_BAND59_ID_MTSIF_BAND58_BAND_ID_MASK 0x003f0000
-#define BCHP_XPT_FE_MTSIF_RX2_BAND56_BAND59_ID_MTSIF_BAND58_BAND_ID_SHIFT 16
-#define BCHP_XPT_FE_MTSIF_RX2_BAND56_BAND59_ID_MTSIF_BAND58_BAND_ID_DEFAULT 0x0000003a
-
-/* XPT_FE :: MTSIF_RX2_BAND56_BAND59_ID :: reserved2 [15:14] */
-#define BCHP_XPT_FE_MTSIF_RX2_BAND56_BAND59_ID_reserved2_MASK 0x0000c000
-#define BCHP_XPT_FE_MTSIF_RX2_BAND56_BAND59_ID_reserved2_SHIFT 14
-
-/* XPT_FE :: MTSIF_RX2_BAND56_BAND59_ID :: MTSIF_BAND57_BAND_ID [13:08] */
-#define BCHP_XPT_FE_MTSIF_RX2_BAND56_BAND59_ID_MTSIF_BAND57_BAND_ID_MASK 0x00003f00
-#define BCHP_XPT_FE_MTSIF_RX2_BAND56_BAND59_ID_MTSIF_BAND57_BAND_ID_SHIFT 8
-#define BCHP_XPT_FE_MTSIF_RX2_BAND56_BAND59_ID_MTSIF_BAND57_BAND_ID_DEFAULT 0x00000039
-
-/* XPT_FE :: MTSIF_RX2_BAND56_BAND59_ID :: reserved3 [07:06] */
-#define BCHP_XPT_FE_MTSIF_RX2_BAND56_BAND59_ID_reserved3_MASK 0x000000c0
-#define BCHP_XPT_FE_MTSIF_RX2_BAND56_BAND59_ID_reserved3_SHIFT 6
-
-/* XPT_FE :: MTSIF_RX2_BAND56_BAND59_ID :: MTSIF_BAND56_BAND_ID [05:00] */
-#define BCHP_XPT_FE_MTSIF_RX2_BAND56_BAND59_ID_MTSIF_BAND56_BAND_ID_MASK 0x0000003f
-#define BCHP_XPT_FE_MTSIF_RX2_BAND56_BAND59_ID_MTSIF_BAND56_BAND_ID_SHIFT 0
-#define BCHP_XPT_FE_MTSIF_RX2_BAND56_BAND59_ID_MTSIF_BAND56_BAND_ID_DEFAULT 0x00000038
-
-/***************************************************************************
- *MTSIF_RX2_BAND60_BAND63_ID - MTSIF RX2 Band60 to Band63 ID Register
- ***************************************************************************/
-/* XPT_FE :: MTSIF_RX2_BAND60_BAND63_ID :: reserved0 [31:30] */
-#define BCHP_XPT_FE_MTSIF_RX2_BAND60_BAND63_ID_reserved0_MASK 0xc0000000
-#define BCHP_XPT_FE_MTSIF_RX2_BAND60_BAND63_ID_reserved0_SHIFT 30
-
-/* XPT_FE :: MTSIF_RX2_BAND60_BAND63_ID :: MTSIF_BAND63_BAND_ID [29:24] */
-#define BCHP_XPT_FE_MTSIF_RX2_BAND60_BAND63_ID_MTSIF_BAND63_BAND_ID_MASK 0x3f000000
-#define BCHP_XPT_FE_MTSIF_RX2_BAND60_BAND63_ID_MTSIF_BAND63_BAND_ID_SHIFT 24
-#define BCHP_XPT_FE_MTSIF_RX2_BAND60_BAND63_ID_MTSIF_BAND63_BAND_ID_DEFAULT 0x0000003f
-
-/* XPT_FE :: MTSIF_RX2_BAND60_BAND63_ID :: reserved1 [23:22] */
-#define BCHP_XPT_FE_MTSIF_RX2_BAND60_BAND63_ID_reserved1_MASK 0x00c00000
-#define BCHP_XPT_FE_MTSIF_RX2_BAND60_BAND63_ID_reserved1_SHIFT 22
-
-/* XPT_FE :: MTSIF_RX2_BAND60_BAND63_ID :: MTSIF_BAND62_BAND_ID [21:16] */
-#define BCHP_XPT_FE_MTSIF_RX2_BAND60_BAND63_ID_MTSIF_BAND62_BAND_ID_MASK 0x003f0000
-#define BCHP_XPT_FE_MTSIF_RX2_BAND60_BAND63_ID_MTSIF_BAND62_BAND_ID_SHIFT 16
-#define BCHP_XPT_FE_MTSIF_RX2_BAND60_BAND63_ID_MTSIF_BAND62_BAND_ID_DEFAULT 0x0000003e
-
-/* XPT_FE :: MTSIF_RX2_BAND60_BAND63_ID :: reserved2 [15:14] */
-#define BCHP_XPT_FE_MTSIF_RX2_BAND60_BAND63_ID_reserved2_MASK 0x0000c000
-#define BCHP_XPT_FE_MTSIF_RX2_BAND60_BAND63_ID_reserved2_SHIFT 14
-
-/* XPT_FE :: MTSIF_RX2_BAND60_BAND63_ID :: MTSIF_BAND61_BAND_ID [13:08] */
-#define BCHP_XPT_FE_MTSIF_RX2_BAND60_BAND63_ID_MTSIF_BAND61_BAND_ID_MASK 0x00003f00
-#define BCHP_XPT_FE_MTSIF_RX2_BAND60_BAND63_ID_MTSIF_BAND61_BAND_ID_SHIFT 8
-#define BCHP_XPT_FE_MTSIF_RX2_BAND60_BAND63_ID_MTSIF_BAND61_BAND_ID_DEFAULT 0x0000003d
-
-/* XPT_FE :: MTSIF_RX2_BAND60_BAND63_ID :: reserved3 [07:06] */
-#define BCHP_XPT_FE_MTSIF_RX2_BAND60_BAND63_ID_reserved3_MASK 0x000000c0
-#define BCHP_XPT_FE_MTSIF_RX2_BAND60_BAND63_ID_reserved3_SHIFT 6
-
-/* XPT_FE :: MTSIF_RX2_BAND60_BAND63_ID :: MTSIF_BAND60_BAND_ID [05:00] */
-#define BCHP_XPT_FE_MTSIF_RX2_BAND60_BAND63_ID_MTSIF_BAND60_BAND_ID_MASK 0x0000003f
-#define BCHP_XPT_FE_MTSIF_RX2_BAND60_BAND63_ID_MTSIF_BAND60_BAND_ID_SHIFT 0
-#define BCHP_XPT_FE_MTSIF_RX2_BAND60_BAND63_ID_MTSIF_BAND60_BAND_ID_DEFAULT 0x0000003c
-
-/***************************************************************************
- *MTSIF_RX2_PKT_BAND0_BAND31_DETECT - MTSIF RX2 Packet Band0 to Band31 Detect Register
- ***************************************************************************/
-/* XPT_FE :: MTSIF_RX2_PKT_BAND0_BAND31_DETECT :: BAND_ID31 [31:31] */
-#define BCHP_XPT_FE_MTSIF_RX2_PKT_BAND0_BAND31_DETECT_BAND_ID31_MASK 0x80000000
-#define BCHP_XPT_FE_MTSIF_RX2_PKT_BAND0_BAND31_DETECT_BAND_ID31_SHIFT 31
-#define BCHP_XPT_FE_MTSIF_RX2_PKT_BAND0_BAND31_DETECT_BAND_ID31_DEFAULT 0x00000000
-
-/* XPT_FE :: MTSIF_RX2_PKT_BAND0_BAND31_DETECT :: BAND_ID30 [30:30] */
-#define BCHP_XPT_FE_MTSIF_RX2_PKT_BAND0_BAND31_DETECT_BAND_ID30_MASK 0x40000000
-#define BCHP_XPT_FE_MTSIF_RX2_PKT_BAND0_BAND31_DETECT_BAND_ID30_SHIFT 30
-#define BCHP_XPT_FE_MTSIF_RX2_PKT_BAND0_BAND31_DETECT_BAND_ID30_DEFAULT 0x00000000
-
-/* XPT_FE :: MTSIF_RX2_PKT_BAND0_BAND31_DETECT :: BAND_ID29 [29:29] */
-#define BCHP_XPT_FE_MTSIF_RX2_PKT_BAND0_BAND31_DETECT_BAND_ID29_MASK 0x20000000
-#define BCHP_XPT_FE_MTSIF_RX2_PKT_BAND0_BAND31_DETECT_BAND_ID29_SHIFT 29
-#define BCHP_XPT_FE_MTSIF_RX2_PKT_BAND0_BAND31_DETECT_BAND_ID29_DEFAULT 0x00000000
-
-/* XPT_FE :: MTSIF_RX2_PKT_BAND0_BAND31_DETECT :: BAND_ID28 [28:28] */
-#define BCHP_XPT_FE_MTSIF_RX2_PKT_BAND0_BAND31_DETECT_BAND_ID28_MASK 0x10000000
-#define BCHP_XPT_FE_MTSIF_RX2_PKT_BAND0_BAND31_DETECT_BAND_ID28_SHIFT 28
-#define BCHP_XPT_FE_MTSIF_RX2_PKT_BAND0_BAND31_DETECT_BAND_ID28_DEFAULT 0x00000000
-
-/* XPT_FE :: MTSIF_RX2_PKT_BAND0_BAND31_DETECT :: BAND_ID27 [27:27] */
-#define BCHP_XPT_FE_MTSIF_RX2_PKT_BAND0_BAND31_DETECT_BAND_ID27_MASK 0x08000000
-#define BCHP_XPT_FE_MTSIF_RX2_PKT_BAND0_BAND31_DETECT_BAND_ID27_SHIFT 27
-#define BCHP_XPT_FE_MTSIF_RX2_PKT_BAND0_BAND31_DETECT_BAND_ID27_DEFAULT 0x00000000
-
-/* XPT_FE :: MTSIF_RX2_PKT_BAND0_BAND31_DETECT :: BAND_ID26 [26:26] */
-#define BCHP_XPT_FE_MTSIF_RX2_PKT_BAND0_BAND31_DETECT_BAND_ID26_MASK 0x04000000
-#define BCHP_XPT_FE_MTSIF_RX2_PKT_BAND0_BAND31_DETECT_BAND_ID26_SHIFT 26
-#define BCHP_XPT_FE_MTSIF_RX2_PKT_BAND0_BAND31_DETECT_BAND_ID26_DEFAULT 0x00000000
-
-/* XPT_FE :: MTSIF_RX2_PKT_BAND0_BAND31_DETECT :: BAND_ID25 [25:25] */
-#define BCHP_XPT_FE_MTSIF_RX2_PKT_BAND0_BAND31_DETECT_BAND_ID25_MASK 0x02000000
-#define BCHP_XPT_FE_MTSIF_RX2_PKT_BAND0_BAND31_DETECT_BAND_ID25_SHIFT 25
-#define BCHP_XPT_FE_MTSIF_RX2_PKT_BAND0_BAND31_DETECT_BAND_ID25_DEFAULT 0x00000000
-
-/* XPT_FE :: MTSIF_RX2_PKT_BAND0_BAND31_DETECT :: BAND_ID24 [24:24] */
-#define BCHP_XPT_FE_MTSIF_RX2_PKT_BAND0_BAND31_DETECT_BAND_ID24_MASK 0x01000000
-#define BCHP_XPT_FE_MTSIF_RX2_PKT_BAND0_BAND31_DETECT_BAND_ID24_SHIFT 24
-#define BCHP_XPT_FE_MTSIF_RX2_PKT_BAND0_BAND31_DETECT_BAND_ID24_DEFAULT 0x00000000
-
-/* XPT_FE :: MTSIF_RX2_PKT_BAND0_BAND31_DETECT :: BAND_ID23 [23:23] */
-#define BCHP_XPT_FE_MTSIF_RX2_PKT_BAND0_BAND31_DETECT_BAND_ID23_MASK 0x00800000
-#define BCHP_XPT_FE_MTSIF_RX2_PKT_BAND0_BAND31_DETECT_BAND_ID23_SHIFT 23
-#define BCHP_XPT_FE_MTSIF_RX2_PKT_BAND0_BAND31_DETECT_BAND_ID23_DEFAULT 0x00000000
-
-/* XPT_FE :: MTSIF_RX2_PKT_BAND0_BAND31_DETECT :: BAND_ID22 [22:22] */
-#define BCHP_XPT_FE_MTSIF_RX2_PKT_BAND0_BAND31_DETECT_BAND_ID22_MASK 0x00400000
-#define BCHP_XPT_FE_MTSIF_RX2_PKT_BAND0_BAND31_DETECT_BAND_ID22_SHIFT 22
-#define BCHP_XPT_FE_MTSIF_RX2_PKT_BAND0_BAND31_DETECT_BAND_ID22_DEFAULT 0x00000000
-
-/* XPT_FE :: MTSIF_RX2_PKT_BAND0_BAND31_DETECT :: BAND_ID21 [21:21] */
-#define BCHP_XPT_FE_MTSIF_RX2_PKT_BAND0_BAND31_DETECT_BAND_ID21_MASK 0x00200000
-#define BCHP_XPT_FE_MTSIF_RX2_PKT_BAND0_BAND31_DETECT_BAND_ID21_SHIFT 21
-#define BCHP_XPT_FE_MTSIF_RX2_PKT_BAND0_BAND31_DETECT_BAND_ID21_DEFAULT 0x00000000
-
-/* XPT_FE :: MTSIF_RX2_PKT_BAND0_BAND31_DETECT :: BAND_ID20 [20:20] */
-#define BCHP_XPT_FE_MTSIF_RX2_PKT_BAND0_BAND31_DETECT_BAND_ID20_MASK 0x00100000
-#define BCHP_XPT_FE_MTSIF_RX2_PKT_BAND0_BAND31_DETECT_BAND_ID20_SHIFT 20
-#define BCHP_XPT_FE_MTSIF_RX2_PKT_BAND0_BAND31_DETECT_BAND_ID20_DEFAULT 0x00000000
-
-/* XPT_FE :: MTSIF_RX2_PKT_BAND0_BAND31_DETECT :: BAND_ID19 [19:19] */
-#define BCHP_XPT_FE_MTSIF_RX2_PKT_BAND0_BAND31_DETECT_BAND_ID19_MASK 0x00080000
-#define BCHP_XPT_FE_MTSIF_RX2_PKT_BAND0_BAND31_DETECT_BAND_ID19_SHIFT 19
-#define BCHP_XPT_FE_MTSIF_RX2_PKT_BAND0_BAND31_DETECT_BAND_ID19_DEFAULT 0x00000000
-
-/* XPT_FE :: MTSIF_RX2_PKT_BAND0_BAND31_DETECT :: BAND_ID18 [18:18] */
-#define BCHP_XPT_FE_MTSIF_RX2_PKT_BAND0_BAND31_DETECT_BAND_ID18_MASK 0x00040000
-#define BCHP_XPT_FE_MTSIF_RX2_PKT_BAND0_BAND31_DETECT_BAND_ID18_SHIFT 18
-#define BCHP_XPT_FE_MTSIF_RX2_PKT_BAND0_BAND31_DETECT_BAND_ID18_DEFAULT 0x00000000
-
-/* XPT_FE :: MTSIF_RX2_PKT_BAND0_BAND31_DETECT :: BAND_ID17 [17:17] */
-#define BCHP_XPT_FE_MTSIF_RX2_PKT_BAND0_BAND31_DETECT_BAND_ID17_MASK 0x00020000
-#define BCHP_XPT_FE_MTSIF_RX2_PKT_BAND0_BAND31_DETECT_BAND_ID17_SHIFT 17
-#define BCHP_XPT_FE_MTSIF_RX2_PKT_BAND0_BAND31_DETECT_BAND_ID17_DEFAULT 0x00000000
-
-/* XPT_FE :: MTSIF_RX2_PKT_BAND0_BAND31_DETECT :: BAND_ID16 [16:16] */
-#define BCHP_XPT_FE_MTSIF_RX2_PKT_BAND0_BAND31_DETECT_BAND_ID16_MASK 0x00010000
-#define BCHP_XPT_FE_MTSIF_RX2_PKT_BAND0_BAND31_DETECT_BAND_ID16_SHIFT 16
-#define BCHP_XPT_FE_MTSIF_RX2_PKT_BAND0_BAND31_DETECT_BAND_ID16_DEFAULT 0x00000000
-
-/* XPT_FE :: MTSIF_RX2_PKT_BAND0_BAND31_DETECT :: BAND_ID15 [15:15] */
-#define BCHP_XPT_FE_MTSIF_RX2_PKT_BAND0_BAND31_DETECT_BAND_ID15_MASK 0x00008000
-#define BCHP_XPT_FE_MTSIF_RX2_PKT_BAND0_BAND31_DETECT_BAND_ID15_SHIFT 15
-#define BCHP_XPT_FE_MTSIF_RX2_PKT_BAND0_BAND31_DETECT_BAND_ID15_DEFAULT 0x00000000
-
-/* XPT_FE :: MTSIF_RX2_PKT_BAND0_BAND31_DETECT :: BAND_ID14 [14:14] */
-#define BCHP_XPT_FE_MTSIF_RX2_PKT_BAND0_BAND31_DETECT_BAND_ID14_MASK 0x00004000
-#define BCHP_XPT_FE_MTSIF_RX2_PKT_BAND0_BAND31_DETECT_BAND_ID14_SHIFT 14
-#define BCHP_XPT_FE_MTSIF_RX2_PKT_BAND0_BAND31_DETECT_BAND_ID14_DEFAULT 0x00000000
-
-/* XPT_FE :: MTSIF_RX2_PKT_BAND0_BAND31_DETECT :: BAND_ID13 [13:13] */
-#define BCHP_XPT_FE_MTSIF_RX2_PKT_BAND0_BAND31_DETECT_BAND_ID13_MASK 0x00002000
-#define BCHP_XPT_FE_MTSIF_RX2_PKT_BAND0_BAND31_DETECT_BAND_ID13_SHIFT 13
-#define BCHP_XPT_FE_MTSIF_RX2_PKT_BAND0_BAND31_DETECT_BAND_ID13_DEFAULT 0x00000000
-
-/* XPT_FE :: MTSIF_RX2_PKT_BAND0_BAND31_DETECT :: BAND_ID12 [12:12] */
-#define BCHP_XPT_FE_MTSIF_RX2_PKT_BAND0_BAND31_DETECT_BAND_ID12_MASK 0x00001000
-#define BCHP_XPT_FE_MTSIF_RX2_PKT_BAND0_BAND31_DETECT_BAND_ID12_SHIFT 12
-#define BCHP_XPT_FE_MTSIF_RX2_PKT_BAND0_BAND31_DETECT_BAND_ID12_DEFAULT 0x00000000
-
-/* XPT_FE :: MTSIF_RX2_PKT_BAND0_BAND31_DETECT :: BAND_ID11 [11:11] */
-#define BCHP_XPT_FE_MTSIF_RX2_PKT_BAND0_BAND31_DETECT_BAND_ID11_MASK 0x00000800
-#define BCHP_XPT_FE_MTSIF_RX2_PKT_BAND0_BAND31_DETECT_BAND_ID11_SHIFT 11
-#define BCHP_XPT_FE_MTSIF_RX2_PKT_BAND0_BAND31_DETECT_BAND_ID11_DEFAULT 0x00000000
-
-/* XPT_FE :: MTSIF_RX2_PKT_BAND0_BAND31_DETECT :: BAND_ID10 [10:10] */
-#define BCHP_XPT_FE_MTSIF_RX2_PKT_BAND0_BAND31_DETECT_BAND_ID10_MASK 0x00000400
-#define BCHP_XPT_FE_MTSIF_RX2_PKT_BAND0_BAND31_DETECT_BAND_ID10_SHIFT 10
-#define BCHP_XPT_FE_MTSIF_RX2_PKT_BAND0_BAND31_DETECT_BAND_ID10_DEFAULT 0x00000000
-
-/* XPT_FE :: MTSIF_RX2_PKT_BAND0_BAND31_DETECT :: BAND_ID9 [09:09] */
-#define BCHP_XPT_FE_MTSIF_RX2_PKT_BAND0_BAND31_DETECT_BAND_ID9_MASK 0x00000200
-#define BCHP_XPT_FE_MTSIF_RX2_PKT_BAND0_BAND31_DETECT_BAND_ID9_SHIFT 9
-#define BCHP_XPT_FE_MTSIF_RX2_PKT_BAND0_BAND31_DETECT_BAND_ID9_DEFAULT 0x00000000
-
-/* XPT_FE :: MTSIF_RX2_PKT_BAND0_BAND31_DETECT :: BAND_ID8 [08:08] */
-#define BCHP_XPT_FE_MTSIF_RX2_PKT_BAND0_BAND31_DETECT_BAND_ID8_MASK 0x00000100
-#define BCHP_XPT_FE_MTSIF_RX2_PKT_BAND0_BAND31_DETECT_BAND_ID8_SHIFT 8
-#define BCHP_XPT_FE_MTSIF_RX2_PKT_BAND0_BAND31_DETECT_BAND_ID8_DEFAULT 0x00000000
-
-/* XPT_FE :: MTSIF_RX2_PKT_BAND0_BAND31_DETECT :: BAND_ID7 [07:07] */
-#define BCHP_XPT_FE_MTSIF_RX2_PKT_BAND0_BAND31_DETECT_BAND_ID7_MASK 0x00000080
-#define BCHP_XPT_FE_MTSIF_RX2_PKT_BAND0_BAND31_DETECT_BAND_ID7_SHIFT 7
-#define BCHP_XPT_FE_MTSIF_RX2_PKT_BAND0_BAND31_DETECT_BAND_ID7_DEFAULT 0x00000000
-
-/* XPT_FE :: MTSIF_RX2_PKT_BAND0_BAND31_DETECT :: BAND_ID6 [06:06] */
-#define BCHP_XPT_FE_MTSIF_RX2_PKT_BAND0_BAND31_DETECT_BAND_ID6_MASK 0x00000040
-#define BCHP_XPT_FE_MTSIF_RX2_PKT_BAND0_BAND31_DETECT_BAND_ID6_SHIFT 6
-#define BCHP_XPT_FE_MTSIF_RX2_PKT_BAND0_BAND31_DETECT_BAND_ID6_DEFAULT 0x00000000
-
-/* XPT_FE :: MTSIF_RX2_PKT_BAND0_BAND31_DETECT :: BAND_ID5 [05:05] */
-#define BCHP_XPT_FE_MTSIF_RX2_PKT_BAND0_BAND31_DETECT_BAND_ID5_MASK 0x00000020
-#define BCHP_XPT_FE_MTSIF_RX2_PKT_BAND0_BAND31_DETECT_BAND_ID5_SHIFT 5
-#define BCHP_XPT_FE_MTSIF_RX2_PKT_BAND0_BAND31_DETECT_BAND_ID5_DEFAULT 0x00000000
-
-/* XPT_FE :: MTSIF_RX2_PKT_BAND0_BAND31_DETECT :: BAND_ID4 [04:04] */
-#define BCHP_XPT_FE_MTSIF_RX2_PKT_BAND0_BAND31_DETECT_BAND_ID4_MASK 0x00000010
-#define BCHP_XPT_FE_MTSIF_RX2_PKT_BAND0_BAND31_DETECT_BAND_ID4_SHIFT 4
-#define BCHP_XPT_FE_MTSIF_RX2_PKT_BAND0_BAND31_DETECT_BAND_ID4_DEFAULT 0x00000000
-
-/* XPT_FE :: MTSIF_RX2_PKT_BAND0_BAND31_DETECT :: BAND_ID3 [03:03] */
-#define BCHP_XPT_FE_MTSIF_RX2_PKT_BAND0_BAND31_DETECT_BAND_ID3_MASK 0x00000008
-#define BCHP_XPT_FE_MTSIF_RX2_PKT_BAND0_BAND31_DETECT_BAND_ID3_SHIFT 3
-#define BCHP_XPT_FE_MTSIF_RX2_PKT_BAND0_BAND31_DETECT_BAND_ID3_DEFAULT 0x00000000
-
-/* XPT_FE :: MTSIF_RX2_PKT_BAND0_BAND31_DETECT :: BAND_ID2 [02:02] */
-#define BCHP_XPT_FE_MTSIF_RX2_PKT_BAND0_BAND31_DETECT_BAND_ID2_MASK 0x00000004
-#define BCHP_XPT_FE_MTSIF_RX2_PKT_BAND0_BAND31_DETECT_BAND_ID2_SHIFT 2
-#define BCHP_XPT_FE_MTSIF_RX2_PKT_BAND0_BAND31_DETECT_BAND_ID2_DEFAULT 0x00000000
-
-/* XPT_FE :: MTSIF_RX2_PKT_BAND0_BAND31_DETECT :: BAND_ID1 [01:01] */
-#define BCHP_XPT_FE_MTSIF_RX2_PKT_BAND0_BAND31_DETECT_BAND_ID1_MASK 0x00000002
-#define BCHP_XPT_FE_MTSIF_RX2_PKT_BAND0_BAND31_DETECT_BAND_ID1_SHIFT 1
-#define BCHP_XPT_FE_MTSIF_RX2_PKT_BAND0_BAND31_DETECT_BAND_ID1_DEFAULT 0x00000000
-
-/* XPT_FE :: MTSIF_RX2_PKT_BAND0_BAND31_DETECT :: BAND_ID0 [00:00] */
-#define BCHP_XPT_FE_MTSIF_RX2_PKT_BAND0_BAND31_DETECT_BAND_ID0_MASK 0x00000001
-#define BCHP_XPT_FE_MTSIF_RX2_PKT_BAND0_BAND31_DETECT_BAND_ID0_SHIFT 0
-#define BCHP_XPT_FE_MTSIF_RX2_PKT_BAND0_BAND31_DETECT_BAND_ID0_DEFAULT 0x00000000
-
-/***************************************************************************
- *MTSIF_RX3_CTRL1 - FE_MTSIF_RX3_CTRL1
- ***************************************************************************/
-/* XPT_FE :: MTSIF_RX3_CTRL1 :: reserved0 [31:09] */
-#define BCHP_XPT_FE_MTSIF_RX3_CTRL1_reserved0_MASK 0xfffffe00
-#define BCHP_XPT_FE_MTSIF_RX3_CTRL1_reserved0_SHIFT 9
-
-/* XPT_FE :: MTSIF_RX3_CTRL1 :: MTSIF_RX_DECRYPTION_ENABLE_STATUS [08:08] */
-#define BCHP_XPT_FE_MTSIF_RX3_CTRL1_MTSIF_RX_DECRYPTION_ENABLE_STATUS_MASK 0x00000100
-#define BCHP_XPT_FE_MTSIF_RX3_CTRL1_MTSIF_RX_DECRYPTION_ENABLE_STATUS_SHIFT 8
-#define BCHP_XPT_FE_MTSIF_RX3_CTRL1_MTSIF_RX_DECRYPTION_ENABLE_STATUS_DEFAULT 0x00000001
-
-/* XPT_FE :: MTSIF_RX3_CTRL1 :: MTSIF_RX_PKT_BAND_DETECT_MODE [07:07] */
-#define BCHP_XPT_FE_MTSIF_RX3_CTRL1_MTSIF_RX_PKT_BAND_DETECT_MODE_MASK 0x00000080
-#define BCHP_XPT_FE_MTSIF_RX3_CTRL1_MTSIF_RX_PKT_BAND_DETECT_MODE_SHIFT 7
-#define BCHP_XPT_FE_MTSIF_RX3_CTRL1_MTSIF_RX_PKT_BAND_DETECT_MODE_DEFAULT 0x00000000
-
-/* XPT_FE :: MTSIF_RX3_CTRL1 :: MTSIF_RX_ERR_RPT_EN [06:06] */
-#define BCHP_XPT_FE_MTSIF_RX3_CTRL1_MTSIF_RX_ERR_RPT_EN_MASK 0x00000040
-#define BCHP_XPT_FE_MTSIF_RX3_CTRL1_MTSIF_RX_ERR_RPT_EN_SHIFT 6
-#define BCHP_XPT_FE_MTSIF_RX3_CTRL1_MTSIF_RX_ERR_RPT_EN_DEFAULT 0x00000000
-
-/* XPT_FE :: MTSIF_RX3_CTRL1 :: MTSIF_RX_IF_WIDTH [05:04] */
-#define BCHP_XPT_FE_MTSIF_RX3_CTRL1_MTSIF_RX_IF_WIDTH_MASK 0x00000030
-#define BCHP_XPT_FE_MTSIF_RX3_CTRL1_MTSIF_RX_IF_WIDTH_SHIFT 4
-#define BCHP_XPT_FE_MTSIF_RX3_CTRL1_MTSIF_RX_IF_WIDTH_DEFAULT 0x00000003
-
-/* XPT_FE :: MTSIF_RX3_CTRL1 :: reserved1 [03:02] */
-#define BCHP_XPT_FE_MTSIF_RX3_CTRL1_reserved1_MASK 0x0000000c
-#define BCHP_XPT_FE_MTSIF_RX3_CTRL1_reserved1_SHIFT 2
-
-/* XPT_FE :: MTSIF_RX3_CTRL1 :: MTSIF_RX_CLOCK_POL_SEL [01:01] */
-#define BCHP_XPT_FE_MTSIF_RX3_CTRL1_MTSIF_RX_CLOCK_POL_SEL_MASK 0x00000002
-#define BCHP_XPT_FE_MTSIF_RX3_CTRL1_MTSIF_RX_CLOCK_POL_SEL_SHIFT 1
-#define BCHP_XPT_FE_MTSIF_RX3_CTRL1_MTSIF_RX_CLOCK_POL_SEL_DEFAULT 0x00000001
-
-/* XPT_FE :: MTSIF_RX3_CTRL1 :: PARSER_ENABLE [00:00] */
-#define BCHP_XPT_FE_MTSIF_RX3_CTRL1_PARSER_ENABLE_MASK 0x00000001
-#define BCHP_XPT_FE_MTSIF_RX3_CTRL1_PARSER_ENABLE_SHIFT 0
-#define BCHP_XPT_FE_MTSIF_RX3_CTRL1_PARSER_ENABLE_DEFAULT 0x00000000
-
-/***************************************************************************
- *MTSIF_RX3_SECRET_WORD - MTSIF RX3 Secret Word Register
- ***************************************************************************/
-/* XPT_FE :: MTSIF_RX3_SECRET_WORD :: SECRET_WORD [31:00] */
-#define BCHP_XPT_FE_MTSIF_RX3_SECRET_WORD_SECRET_WORD_MASK 0xffffffff
-#define BCHP_XPT_FE_MTSIF_RX3_SECRET_WORD_SECRET_WORD_SHIFT 0
-#define BCHP_XPT_FE_MTSIF_RX3_SECRET_WORD_SECRET_WORD_DEFAULT 0x00000000
-
-/***************************************************************************
- *MTSIF_RX3_BAND0_BAND31_ID_DROP - MTSIF RX3 Band0 to Band31 ID Drop Register
- ***************************************************************************/
-/* XPT_FE :: MTSIF_RX3_BAND0_BAND31_ID_DROP :: DROP_EN [31:00] */
-#define BCHP_XPT_FE_MTSIF_RX3_BAND0_BAND31_ID_DROP_DROP_EN_MASK 0xffffffff
-#define BCHP_XPT_FE_MTSIF_RX3_BAND0_BAND31_ID_DROP_DROP_EN_SHIFT 0
-#define BCHP_XPT_FE_MTSIF_RX3_BAND0_BAND31_ID_DROP_DROP_EN_DEFAULT 0x00000000
-
-/***************************************************************************
- *MTSIF_RX3_BAND0_BAND3_ID - MTSIF RX3 Band0 to Band3 ID Register
- ***************************************************************************/
-/* XPT_FE :: MTSIF_RX3_BAND0_BAND3_ID :: reserved0 [31:30] */
-#define BCHP_XPT_FE_MTSIF_RX3_BAND0_BAND3_ID_reserved0_MASK 0xc0000000
-#define BCHP_XPT_FE_MTSIF_RX3_BAND0_BAND3_ID_reserved0_SHIFT 30
-
-/* XPT_FE :: MTSIF_RX3_BAND0_BAND3_ID :: MTSIF_BAND3_BAND_ID [29:24] */
-#define BCHP_XPT_FE_MTSIF_RX3_BAND0_BAND3_ID_MTSIF_BAND3_BAND_ID_MASK 0x3f000000
-#define BCHP_XPT_FE_MTSIF_RX3_BAND0_BAND3_ID_MTSIF_BAND3_BAND_ID_SHIFT 24
-#define BCHP_XPT_FE_MTSIF_RX3_BAND0_BAND3_ID_MTSIF_BAND3_BAND_ID_DEFAULT 0x00000003
-
-/* XPT_FE :: MTSIF_RX3_BAND0_BAND3_ID :: reserved1 [23:22] */
-#define BCHP_XPT_FE_MTSIF_RX3_BAND0_BAND3_ID_reserved1_MASK 0x00c00000
-#define BCHP_XPT_FE_MTSIF_RX3_BAND0_BAND3_ID_reserved1_SHIFT 22
-
-/* XPT_FE :: MTSIF_RX3_BAND0_BAND3_ID :: MTSIF_BAND2_BAND_ID [21:16] */
-#define BCHP_XPT_FE_MTSIF_RX3_BAND0_BAND3_ID_MTSIF_BAND2_BAND_ID_MASK 0x003f0000
-#define BCHP_XPT_FE_MTSIF_RX3_BAND0_BAND3_ID_MTSIF_BAND2_BAND_ID_SHIFT 16
-#define BCHP_XPT_FE_MTSIF_RX3_BAND0_BAND3_ID_MTSIF_BAND2_BAND_ID_DEFAULT 0x00000002
-
-/* XPT_FE :: MTSIF_RX3_BAND0_BAND3_ID :: reserved2 [15:14] */
-#define BCHP_XPT_FE_MTSIF_RX3_BAND0_BAND3_ID_reserved2_MASK 0x0000c000
-#define BCHP_XPT_FE_MTSIF_RX3_BAND0_BAND3_ID_reserved2_SHIFT 14
-
-/* XPT_FE :: MTSIF_RX3_BAND0_BAND3_ID :: MTSIF_BAND1_BAND_ID [13:08] */
-#define BCHP_XPT_FE_MTSIF_RX3_BAND0_BAND3_ID_MTSIF_BAND1_BAND_ID_MASK 0x00003f00
-#define BCHP_XPT_FE_MTSIF_RX3_BAND0_BAND3_ID_MTSIF_BAND1_BAND_ID_SHIFT 8
-#define BCHP_XPT_FE_MTSIF_RX3_BAND0_BAND3_ID_MTSIF_BAND1_BAND_ID_DEFAULT 0x00000001
-
-/* XPT_FE :: MTSIF_RX3_BAND0_BAND3_ID :: reserved3 [07:06] */
-#define BCHP_XPT_FE_MTSIF_RX3_BAND0_BAND3_ID_reserved3_MASK 0x000000c0
-#define BCHP_XPT_FE_MTSIF_RX3_BAND0_BAND3_ID_reserved3_SHIFT 6
-
-/* XPT_FE :: MTSIF_RX3_BAND0_BAND3_ID :: MTSIF_BAND0_BAND_ID [05:00] */
-#define BCHP_XPT_FE_MTSIF_RX3_BAND0_BAND3_ID_MTSIF_BAND0_BAND_ID_MASK 0x0000003f
-#define BCHP_XPT_FE_MTSIF_RX3_BAND0_BAND3_ID_MTSIF_BAND0_BAND_ID_SHIFT 0
-#define BCHP_XPT_FE_MTSIF_RX3_BAND0_BAND3_ID_MTSIF_BAND0_BAND_ID_DEFAULT 0x00000000
-
-/***************************************************************************
- *MTSIF_RX3_BAND4_BAND7_ID - MTSIF RX3 Band4 to Band7 ID Register
- ***************************************************************************/
-/* XPT_FE :: MTSIF_RX3_BAND4_BAND7_ID :: reserved0 [31:30] */
-#define BCHP_XPT_FE_MTSIF_RX3_BAND4_BAND7_ID_reserved0_MASK 0xc0000000
-#define BCHP_XPT_FE_MTSIF_RX3_BAND4_BAND7_ID_reserved0_SHIFT 30
-
-/* XPT_FE :: MTSIF_RX3_BAND4_BAND7_ID :: MTSIF_BAND7_BAND_ID [29:24] */
-#define BCHP_XPT_FE_MTSIF_RX3_BAND4_BAND7_ID_MTSIF_BAND7_BAND_ID_MASK 0x3f000000
-#define BCHP_XPT_FE_MTSIF_RX3_BAND4_BAND7_ID_MTSIF_BAND7_BAND_ID_SHIFT 24
-#define BCHP_XPT_FE_MTSIF_RX3_BAND4_BAND7_ID_MTSIF_BAND7_BAND_ID_DEFAULT 0x00000007
-
-/* XPT_FE :: MTSIF_RX3_BAND4_BAND7_ID :: reserved1 [23:22] */
-#define BCHP_XPT_FE_MTSIF_RX3_BAND4_BAND7_ID_reserved1_MASK 0x00c00000
-#define BCHP_XPT_FE_MTSIF_RX3_BAND4_BAND7_ID_reserved1_SHIFT 22
-
-/* XPT_FE :: MTSIF_RX3_BAND4_BAND7_ID :: MTSIF_BAND6_BAND_ID [21:16] */
-#define BCHP_XPT_FE_MTSIF_RX3_BAND4_BAND7_ID_MTSIF_BAND6_BAND_ID_MASK 0x003f0000
-#define BCHP_XPT_FE_MTSIF_RX3_BAND4_BAND7_ID_MTSIF_BAND6_BAND_ID_SHIFT 16
-#define BCHP_XPT_FE_MTSIF_RX3_BAND4_BAND7_ID_MTSIF_BAND6_BAND_ID_DEFAULT 0x00000006
-
-/* XPT_FE :: MTSIF_RX3_BAND4_BAND7_ID :: reserved2 [15:14] */
-#define BCHP_XPT_FE_MTSIF_RX3_BAND4_BAND7_ID_reserved2_MASK 0x0000c000
-#define BCHP_XPT_FE_MTSIF_RX3_BAND4_BAND7_ID_reserved2_SHIFT 14
-
-/* XPT_FE :: MTSIF_RX3_BAND4_BAND7_ID :: MTSIF_BAND5_BAND_ID [13:08] */
-#define BCHP_XPT_FE_MTSIF_RX3_BAND4_BAND7_ID_MTSIF_BAND5_BAND_ID_MASK 0x00003f00
-#define BCHP_XPT_FE_MTSIF_RX3_BAND4_BAND7_ID_MTSIF_BAND5_BAND_ID_SHIFT 8
-#define BCHP_XPT_FE_MTSIF_RX3_BAND4_BAND7_ID_MTSIF_BAND5_BAND_ID_DEFAULT 0x00000005
-
-/* XPT_FE :: MTSIF_RX3_BAND4_BAND7_ID :: reserved3 [07:06] */
-#define BCHP_XPT_FE_MTSIF_RX3_BAND4_BAND7_ID_reserved3_MASK 0x000000c0
-#define BCHP_XPT_FE_MTSIF_RX3_BAND4_BAND7_ID_reserved3_SHIFT 6
-
-/* XPT_FE :: MTSIF_RX3_BAND4_BAND7_ID :: MTSIF_BAND4_BAND_ID [05:00] */
-#define BCHP_XPT_FE_MTSIF_RX3_BAND4_BAND7_ID_MTSIF_BAND4_BAND_ID_MASK 0x0000003f
-#define BCHP_XPT_FE_MTSIF_RX3_BAND4_BAND7_ID_MTSIF_BAND4_BAND_ID_SHIFT 0
-#define BCHP_XPT_FE_MTSIF_RX3_BAND4_BAND7_ID_MTSIF_BAND4_BAND_ID_DEFAULT 0x00000004
-
-/***************************************************************************
- *MTSIF_RX3_BAND8_BAND11_ID - MTSIF RX3 Band8 to Band11 ID Register
- ***************************************************************************/
-/* XPT_FE :: MTSIF_RX3_BAND8_BAND11_ID :: reserved0 [31:30] */
-#define BCHP_XPT_FE_MTSIF_RX3_BAND8_BAND11_ID_reserved0_MASK 0xc0000000
-#define BCHP_XPT_FE_MTSIF_RX3_BAND8_BAND11_ID_reserved0_SHIFT 30
-
-/* XPT_FE :: MTSIF_RX3_BAND8_BAND11_ID :: MTSIF_BAND11_BAND_ID [29:24] */
-#define BCHP_XPT_FE_MTSIF_RX3_BAND8_BAND11_ID_MTSIF_BAND11_BAND_ID_MASK 0x3f000000
-#define BCHP_XPT_FE_MTSIF_RX3_BAND8_BAND11_ID_MTSIF_BAND11_BAND_ID_SHIFT 24
-#define BCHP_XPT_FE_MTSIF_RX3_BAND8_BAND11_ID_MTSIF_BAND11_BAND_ID_DEFAULT 0x0000000b
-
-/* XPT_FE :: MTSIF_RX3_BAND8_BAND11_ID :: reserved1 [23:22] */
-#define BCHP_XPT_FE_MTSIF_RX3_BAND8_BAND11_ID_reserved1_MASK 0x00c00000
-#define BCHP_XPT_FE_MTSIF_RX3_BAND8_BAND11_ID_reserved1_SHIFT 22
-
-/* XPT_FE :: MTSIF_RX3_BAND8_BAND11_ID :: MTSIF_BAND10_BAND_ID [21:16] */
-#define BCHP_XPT_FE_MTSIF_RX3_BAND8_BAND11_ID_MTSIF_BAND10_BAND_ID_MASK 0x003f0000
-#define BCHP_XPT_FE_MTSIF_RX3_BAND8_BAND11_ID_MTSIF_BAND10_BAND_ID_SHIFT 16
-#define BCHP_XPT_FE_MTSIF_RX3_BAND8_BAND11_ID_MTSIF_BAND10_BAND_ID_DEFAULT 0x0000000a
-
-/* XPT_FE :: MTSIF_RX3_BAND8_BAND11_ID :: reserved2 [15:14] */
-#define BCHP_XPT_FE_MTSIF_RX3_BAND8_BAND11_ID_reserved2_MASK 0x0000c000
-#define BCHP_XPT_FE_MTSIF_RX3_BAND8_BAND11_ID_reserved2_SHIFT 14
-
-/* XPT_FE :: MTSIF_RX3_BAND8_BAND11_ID :: MTSIF_BAND9_BAND_ID [13:08] */
-#define BCHP_XPT_FE_MTSIF_RX3_BAND8_BAND11_ID_MTSIF_BAND9_BAND_ID_MASK 0x00003f00
-#define BCHP_XPT_FE_MTSIF_RX3_BAND8_BAND11_ID_MTSIF_BAND9_BAND_ID_SHIFT 8
-#define BCHP_XPT_FE_MTSIF_RX3_BAND8_BAND11_ID_MTSIF_BAND9_BAND_ID_DEFAULT 0x00000009
-
-/* XPT_FE :: MTSIF_RX3_BAND8_BAND11_ID :: reserved3 [07:06] */
-#define BCHP_XPT_FE_MTSIF_RX3_BAND8_BAND11_ID_reserved3_MASK 0x000000c0
-#define BCHP_XPT_FE_MTSIF_RX3_BAND8_BAND11_ID_reserved3_SHIFT 6
-
-/* XPT_FE :: MTSIF_RX3_BAND8_BAND11_ID :: MTSIF_BAND8_BAND_ID [05:00] */
-#define BCHP_XPT_FE_MTSIF_RX3_BAND8_BAND11_ID_MTSIF_BAND8_BAND_ID_MASK 0x0000003f
-#define BCHP_XPT_FE_MTSIF_RX3_BAND8_BAND11_ID_MTSIF_BAND8_BAND_ID_SHIFT 0
-#define BCHP_XPT_FE_MTSIF_RX3_BAND8_BAND11_ID_MTSIF_BAND8_BAND_ID_DEFAULT 0x00000008
-
-/***************************************************************************
- *MTSIF_RX3_BAND12_BAND15_ID - MTSIF RX3 Band12 to Band15 ID Register
- ***************************************************************************/
-/* XPT_FE :: MTSIF_RX3_BAND12_BAND15_ID :: reserved0 [31:30] */
-#define BCHP_XPT_FE_MTSIF_RX3_BAND12_BAND15_ID_reserved0_MASK 0xc0000000
-#define BCHP_XPT_FE_MTSIF_RX3_BAND12_BAND15_ID_reserved0_SHIFT 30
-
-/* XPT_FE :: MTSIF_RX3_BAND12_BAND15_ID :: MTSIF_BAND15_BAND_ID [29:24] */
-#define BCHP_XPT_FE_MTSIF_RX3_BAND12_BAND15_ID_MTSIF_BAND15_BAND_ID_MASK 0x3f000000
-#define BCHP_XPT_FE_MTSIF_RX3_BAND12_BAND15_ID_MTSIF_BAND15_BAND_ID_SHIFT 24
-#define BCHP_XPT_FE_MTSIF_RX3_BAND12_BAND15_ID_MTSIF_BAND15_BAND_ID_DEFAULT 0x0000000f
-
-/* XPT_FE :: MTSIF_RX3_BAND12_BAND15_ID :: reserved1 [23:22] */
-#define BCHP_XPT_FE_MTSIF_RX3_BAND12_BAND15_ID_reserved1_MASK 0x00c00000
-#define BCHP_XPT_FE_MTSIF_RX3_BAND12_BAND15_ID_reserved1_SHIFT 22
-
-/* XPT_FE :: MTSIF_RX3_BAND12_BAND15_ID :: MTSIF_BAND14_BAND_ID [21:16] */
-#define BCHP_XPT_FE_MTSIF_RX3_BAND12_BAND15_ID_MTSIF_BAND14_BAND_ID_MASK 0x003f0000
-#define BCHP_XPT_FE_MTSIF_RX3_BAND12_BAND15_ID_MTSIF_BAND14_BAND_ID_SHIFT 16
-#define BCHP_XPT_FE_MTSIF_RX3_BAND12_BAND15_ID_MTSIF_BAND14_BAND_ID_DEFAULT 0x0000000e
-
-/* XPT_FE :: MTSIF_RX3_BAND12_BAND15_ID :: reserved2 [15:14] */
-#define BCHP_XPT_FE_MTSIF_RX3_BAND12_BAND15_ID_reserved2_MASK 0x0000c000
-#define BCHP_XPT_FE_MTSIF_RX3_BAND12_BAND15_ID_reserved2_SHIFT 14
-
-/* XPT_FE :: MTSIF_RX3_BAND12_BAND15_ID :: MTSIF_BAND13_BAND_ID [13:08] */
-#define BCHP_XPT_FE_MTSIF_RX3_BAND12_BAND15_ID_MTSIF_BAND13_BAND_ID_MASK 0x00003f00
-#define BCHP_XPT_FE_MTSIF_RX3_BAND12_BAND15_ID_MTSIF_BAND13_BAND_ID_SHIFT 8
-#define BCHP_XPT_FE_MTSIF_RX3_BAND12_BAND15_ID_MTSIF_BAND13_BAND_ID_DEFAULT 0x0000000d
-
-/* XPT_FE :: MTSIF_RX3_BAND12_BAND15_ID :: reserved3 [07:06] */
-#define BCHP_XPT_FE_MTSIF_RX3_BAND12_BAND15_ID_reserved3_MASK 0x000000c0
-#define BCHP_XPT_FE_MTSIF_RX3_BAND12_BAND15_ID_reserved3_SHIFT 6
-
-/* XPT_FE :: MTSIF_RX3_BAND12_BAND15_ID :: MTSIF_BAND12_BAND_ID [05:00] */
-#define BCHP_XPT_FE_MTSIF_RX3_BAND12_BAND15_ID_MTSIF_BAND12_BAND_ID_MASK 0x0000003f
-#define BCHP_XPT_FE_MTSIF_RX3_BAND12_BAND15_ID_MTSIF_BAND12_BAND_ID_SHIFT 0
-#define BCHP_XPT_FE_MTSIF_RX3_BAND12_BAND15_ID_MTSIF_BAND12_BAND_ID_DEFAULT 0x0000000c
-
-/***************************************************************************
- *MTSIF_RX3_BAND16_BAND19_ID - MTSIF RX3 Band16 to Band19 ID Register
- ***************************************************************************/
-/* XPT_FE :: MTSIF_RX3_BAND16_BAND19_ID :: reserved0 [31:30] */
-#define BCHP_XPT_FE_MTSIF_RX3_BAND16_BAND19_ID_reserved0_MASK 0xc0000000
-#define BCHP_XPT_FE_MTSIF_RX3_BAND16_BAND19_ID_reserved0_SHIFT 30
-
-/* XPT_FE :: MTSIF_RX3_BAND16_BAND19_ID :: MTSIF_BAND19_BAND_ID [29:24] */
-#define BCHP_XPT_FE_MTSIF_RX3_BAND16_BAND19_ID_MTSIF_BAND19_BAND_ID_MASK 0x3f000000
-#define BCHP_XPT_FE_MTSIF_RX3_BAND16_BAND19_ID_MTSIF_BAND19_BAND_ID_SHIFT 24
-#define BCHP_XPT_FE_MTSIF_RX3_BAND16_BAND19_ID_MTSIF_BAND19_BAND_ID_DEFAULT 0x00000013
-
-/* XPT_FE :: MTSIF_RX3_BAND16_BAND19_ID :: reserved1 [23:22] */
-#define BCHP_XPT_FE_MTSIF_RX3_BAND16_BAND19_ID_reserved1_MASK 0x00c00000
-#define BCHP_XPT_FE_MTSIF_RX3_BAND16_BAND19_ID_reserved1_SHIFT 22
-
-/* XPT_FE :: MTSIF_RX3_BAND16_BAND19_ID :: MTSIF_BAND18_BAND_ID [21:16] */
-#define BCHP_XPT_FE_MTSIF_RX3_BAND16_BAND19_ID_MTSIF_BAND18_BAND_ID_MASK 0x003f0000
-#define BCHP_XPT_FE_MTSIF_RX3_BAND16_BAND19_ID_MTSIF_BAND18_BAND_ID_SHIFT 16
-#define BCHP_XPT_FE_MTSIF_RX3_BAND16_BAND19_ID_MTSIF_BAND18_BAND_ID_DEFAULT 0x00000012
-
-/* XPT_FE :: MTSIF_RX3_BAND16_BAND19_ID :: reserved2 [15:14] */
-#define BCHP_XPT_FE_MTSIF_RX3_BAND16_BAND19_ID_reserved2_MASK 0x0000c000
-#define BCHP_XPT_FE_MTSIF_RX3_BAND16_BAND19_ID_reserved2_SHIFT 14
-
-/* XPT_FE :: MTSIF_RX3_BAND16_BAND19_ID :: MTSIF_BAND17_BAND_ID [13:08] */
-#define BCHP_XPT_FE_MTSIF_RX3_BAND16_BAND19_ID_MTSIF_BAND17_BAND_ID_MASK 0x00003f00
-#define BCHP_XPT_FE_MTSIF_RX3_BAND16_BAND19_ID_MTSIF_BAND17_BAND_ID_SHIFT 8
-#define BCHP_XPT_FE_MTSIF_RX3_BAND16_BAND19_ID_MTSIF_BAND17_BAND_ID_DEFAULT 0x00000011
-
-/* XPT_FE :: MTSIF_RX3_BAND16_BAND19_ID :: reserved3 [07:06] */
-#define BCHP_XPT_FE_MTSIF_RX3_BAND16_BAND19_ID_reserved3_MASK 0x000000c0
-#define BCHP_XPT_FE_MTSIF_RX3_BAND16_BAND19_ID_reserved3_SHIFT 6
-
-/* XPT_FE :: MTSIF_RX3_BAND16_BAND19_ID :: MTSIF_BAND16_BAND_ID [05:00] */
-#define BCHP_XPT_FE_MTSIF_RX3_BAND16_BAND19_ID_MTSIF_BAND16_BAND_ID_MASK 0x0000003f
-#define BCHP_XPT_FE_MTSIF_RX3_BAND16_BAND19_ID_MTSIF_BAND16_BAND_ID_SHIFT 0
-#define BCHP_XPT_FE_MTSIF_RX3_BAND16_BAND19_ID_MTSIF_BAND16_BAND_ID_DEFAULT 0x00000010
-
-/***************************************************************************
- *MTSIF_RX3_BAND20_BAND23_ID - MTSIF RX3 Band20 to Band23 ID Register
- ***************************************************************************/
-/* XPT_FE :: MTSIF_RX3_BAND20_BAND23_ID :: reserved0 [31:30] */
-#define BCHP_XPT_FE_MTSIF_RX3_BAND20_BAND23_ID_reserved0_MASK 0xc0000000
-#define BCHP_XPT_FE_MTSIF_RX3_BAND20_BAND23_ID_reserved0_SHIFT 30
-
-/* XPT_FE :: MTSIF_RX3_BAND20_BAND23_ID :: MTSIF_BAND23_BAND_ID [29:24] */
-#define BCHP_XPT_FE_MTSIF_RX3_BAND20_BAND23_ID_MTSIF_BAND23_BAND_ID_MASK 0x3f000000
-#define BCHP_XPT_FE_MTSIF_RX3_BAND20_BAND23_ID_MTSIF_BAND23_BAND_ID_SHIFT 24
-#define BCHP_XPT_FE_MTSIF_RX3_BAND20_BAND23_ID_MTSIF_BAND23_BAND_ID_DEFAULT 0x00000017
-
-/* XPT_FE :: MTSIF_RX3_BAND20_BAND23_ID :: reserved1 [23:22] */
-#define BCHP_XPT_FE_MTSIF_RX3_BAND20_BAND23_ID_reserved1_MASK 0x00c00000
-#define BCHP_XPT_FE_MTSIF_RX3_BAND20_BAND23_ID_reserved1_SHIFT 22
-
-/* XPT_FE :: MTSIF_RX3_BAND20_BAND23_ID :: MTSIF_BAND22_BAND_ID [21:16] */
-#define BCHP_XPT_FE_MTSIF_RX3_BAND20_BAND23_ID_MTSIF_BAND22_BAND_ID_MASK 0x003f0000
-#define BCHP_XPT_FE_MTSIF_RX3_BAND20_BAND23_ID_MTSIF_BAND22_BAND_ID_SHIFT 16
-#define BCHP_XPT_FE_MTSIF_RX3_BAND20_BAND23_ID_MTSIF_BAND22_BAND_ID_DEFAULT 0x00000016
-
-/* XPT_FE :: MTSIF_RX3_BAND20_BAND23_ID :: reserved2 [15:14] */
-#define BCHP_XPT_FE_MTSIF_RX3_BAND20_BAND23_ID_reserved2_MASK 0x0000c000
-#define BCHP_XPT_FE_MTSIF_RX3_BAND20_BAND23_ID_reserved2_SHIFT 14
-
-/* XPT_FE :: MTSIF_RX3_BAND20_BAND23_ID :: MTSIF_BAND21_BAND_ID [13:08] */
-#define BCHP_XPT_FE_MTSIF_RX3_BAND20_BAND23_ID_MTSIF_BAND21_BAND_ID_MASK 0x00003f00
-#define BCHP_XPT_FE_MTSIF_RX3_BAND20_BAND23_ID_MTSIF_BAND21_BAND_ID_SHIFT 8
-#define BCHP_XPT_FE_MTSIF_RX3_BAND20_BAND23_ID_MTSIF_BAND21_BAND_ID_DEFAULT 0x00000015
-
-/* XPT_FE :: MTSIF_RX3_BAND20_BAND23_ID :: reserved3 [07:06] */
-#define BCHP_XPT_FE_MTSIF_RX3_BAND20_BAND23_ID_reserved3_MASK 0x000000c0
-#define BCHP_XPT_FE_MTSIF_RX3_BAND20_BAND23_ID_reserved3_SHIFT 6
-
-/* XPT_FE :: MTSIF_RX3_BAND20_BAND23_ID :: MTSIF_BAND20_BAND_ID [05:00] */
-#define BCHP_XPT_FE_MTSIF_RX3_BAND20_BAND23_ID_MTSIF_BAND20_BAND_ID_MASK 0x0000003f
-#define BCHP_XPT_FE_MTSIF_RX3_BAND20_BAND23_ID_MTSIF_BAND20_BAND_ID_SHIFT 0
-#define BCHP_XPT_FE_MTSIF_RX3_BAND20_BAND23_ID_MTSIF_BAND20_BAND_ID_DEFAULT 0x00000014
-
-/***************************************************************************
- *MTSIF_RX3_BAND24_BAND27_ID - MTSIF RX3 Band24 to Band27 ID Register
- ***************************************************************************/
-/* XPT_FE :: MTSIF_RX3_BAND24_BAND27_ID :: reserved0 [31:30] */
-#define BCHP_XPT_FE_MTSIF_RX3_BAND24_BAND27_ID_reserved0_MASK 0xc0000000
-#define BCHP_XPT_FE_MTSIF_RX3_BAND24_BAND27_ID_reserved0_SHIFT 30
-
-/* XPT_FE :: MTSIF_RX3_BAND24_BAND27_ID :: MTSIF_BAND27_BAND_ID [29:24] */
-#define BCHP_XPT_FE_MTSIF_RX3_BAND24_BAND27_ID_MTSIF_BAND27_BAND_ID_MASK 0x3f000000
-#define BCHP_XPT_FE_MTSIF_RX3_BAND24_BAND27_ID_MTSIF_BAND27_BAND_ID_SHIFT 24
-#define BCHP_XPT_FE_MTSIF_RX3_BAND24_BAND27_ID_MTSIF_BAND27_BAND_ID_DEFAULT 0x0000001b
-
-/* XPT_FE :: MTSIF_RX3_BAND24_BAND27_ID :: reserved1 [23:22] */
-#define BCHP_XPT_FE_MTSIF_RX3_BAND24_BAND27_ID_reserved1_MASK 0x00c00000
-#define BCHP_XPT_FE_MTSIF_RX3_BAND24_BAND27_ID_reserved1_SHIFT 22
-
-/* XPT_FE :: MTSIF_RX3_BAND24_BAND27_ID :: MTSIF_BAND26_BAND_ID [21:16] */
-#define BCHP_XPT_FE_MTSIF_RX3_BAND24_BAND27_ID_MTSIF_BAND26_BAND_ID_MASK 0x003f0000
-#define BCHP_XPT_FE_MTSIF_RX3_BAND24_BAND27_ID_MTSIF_BAND26_BAND_ID_SHIFT 16
-#define BCHP_XPT_FE_MTSIF_RX3_BAND24_BAND27_ID_MTSIF_BAND26_BAND_ID_DEFAULT 0x0000001a
-
-/* XPT_FE :: MTSIF_RX3_BAND24_BAND27_ID :: reserved2 [15:14] */
-#define BCHP_XPT_FE_MTSIF_RX3_BAND24_BAND27_ID_reserved2_MASK 0x0000c000
-#define BCHP_XPT_FE_MTSIF_RX3_BAND24_BAND27_ID_reserved2_SHIFT 14
-
-/* XPT_FE :: MTSIF_RX3_BAND24_BAND27_ID :: MTSIF_BAND25_BAND_ID [13:08] */
-#define BCHP_XPT_FE_MTSIF_RX3_BAND24_BAND27_ID_MTSIF_BAND25_BAND_ID_MASK 0x00003f00
-#define BCHP_XPT_FE_MTSIF_RX3_BAND24_BAND27_ID_MTSIF_BAND25_BAND_ID_SHIFT 8
-#define BCHP_XPT_FE_MTSIF_RX3_BAND24_BAND27_ID_MTSIF_BAND25_BAND_ID_DEFAULT 0x00000019
-
-/* XPT_FE :: MTSIF_RX3_BAND24_BAND27_ID :: reserved3 [07:06] */
-#define BCHP_XPT_FE_MTSIF_RX3_BAND24_BAND27_ID_reserved3_MASK 0x000000c0
-#define BCHP_XPT_FE_MTSIF_RX3_BAND24_BAND27_ID_reserved3_SHIFT 6
-
-/* XPT_FE :: MTSIF_RX3_BAND24_BAND27_ID :: MTSIF_BAND24_BAND_ID [05:00] */
-#define BCHP_XPT_FE_MTSIF_RX3_BAND24_BAND27_ID_MTSIF_BAND24_BAND_ID_MASK 0x0000003f
-#define BCHP_XPT_FE_MTSIF_RX3_BAND24_BAND27_ID_MTSIF_BAND24_BAND_ID_SHIFT 0
-#define BCHP_XPT_FE_MTSIF_RX3_BAND24_BAND27_ID_MTSIF_BAND24_BAND_ID_DEFAULT 0x00000018
-
-/***************************************************************************
- *MTSIF_RX3_BAND28_BAND31_ID - MTSIF RX3 Band28 to Band31 ID Register
- ***************************************************************************/
-/* XPT_FE :: MTSIF_RX3_BAND28_BAND31_ID :: reserved0 [31:30] */
-#define BCHP_XPT_FE_MTSIF_RX3_BAND28_BAND31_ID_reserved0_MASK 0xc0000000
-#define BCHP_XPT_FE_MTSIF_RX3_BAND28_BAND31_ID_reserved0_SHIFT 30
-
-/* XPT_FE :: MTSIF_RX3_BAND28_BAND31_ID :: MTSIF_BAND31_BAND_ID [29:24] */
-#define BCHP_XPT_FE_MTSIF_RX3_BAND28_BAND31_ID_MTSIF_BAND31_BAND_ID_MASK 0x3f000000
-#define BCHP_XPT_FE_MTSIF_RX3_BAND28_BAND31_ID_MTSIF_BAND31_BAND_ID_SHIFT 24
-#define BCHP_XPT_FE_MTSIF_RX3_BAND28_BAND31_ID_MTSIF_BAND31_BAND_ID_DEFAULT 0x0000001f
-
-/* XPT_FE :: MTSIF_RX3_BAND28_BAND31_ID :: reserved1 [23:22] */
-#define BCHP_XPT_FE_MTSIF_RX3_BAND28_BAND31_ID_reserved1_MASK 0x00c00000
-#define BCHP_XPT_FE_MTSIF_RX3_BAND28_BAND31_ID_reserved1_SHIFT 22
-
-/* XPT_FE :: MTSIF_RX3_BAND28_BAND31_ID :: MTSIF_BAND30_BAND_ID [21:16] */
-#define BCHP_XPT_FE_MTSIF_RX3_BAND28_BAND31_ID_MTSIF_BAND30_BAND_ID_MASK 0x003f0000
-#define BCHP_XPT_FE_MTSIF_RX3_BAND28_BAND31_ID_MTSIF_BAND30_BAND_ID_SHIFT 16
-#define BCHP_XPT_FE_MTSIF_RX3_BAND28_BAND31_ID_MTSIF_BAND30_BAND_ID_DEFAULT 0x0000001e
-
-/* XPT_FE :: MTSIF_RX3_BAND28_BAND31_ID :: reserved2 [15:14] */
-#define BCHP_XPT_FE_MTSIF_RX3_BAND28_BAND31_ID_reserved2_MASK 0x0000c000
-#define BCHP_XPT_FE_MTSIF_RX3_BAND28_BAND31_ID_reserved2_SHIFT 14
-
-/* XPT_FE :: MTSIF_RX3_BAND28_BAND31_ID :: MTSIF_BAND29_BAND_ID [13:08] */
-#define BCHP_XPT_FE_MTSIF_RX3_BAND28_BAND31_ID_MTSIF_BAND29_BAND_ID_MASK 0x00003f00
-#define BCHP_XPT_FE_MTSIF_RX3_BAND28_BAND31_ID_MTSIF_BAND29_BAND_ID_SHIFT 8
-#define BCHP_XPT_FE_MTSIF_RX3_BAND28_BAND31_ID_MTSIF_BAND29_BAND_ID_DEFAULT 0x0000001d
-
-/* XPT_FE :: MTSIF_RX3_BAND28_BAND31_ID :: reserved3 [07:06] */
-#define BCHP_XPT_FE_MTSIF_RX3_BAND28_BAND31_ID_reserved3_MASK 0x000000c0
-#define BCHP_XPT_FE_MTSIF_RX3_BAND28_BAND31_ID_reserved3_SHIFT 6
-
-/* XPT_FE :: MTSIF_RX3_BAND28_BAND31_ID :: MTSIF_BAND28_BAND_ID [05:00] */
-#define BCHP_XPT_FE_MTSIF_RX3_BAND28_BAND31_ID_MTSIF_BAND28_BAND_ID_MASK 0x0000003f
-#define BCHP_XPT_FE_MTSIF_RX3_BAND28_BAND31_ID_MTSIF_BAND28_BAND_ID_SHIFT 0
-#define BCHP_XPT_FE_MTSIF_RX3_BAND28_BAND31_ID_MTSIF_BAND28_BAND_ID_DEFAULT 0x0000001c
-
-/***************************************************************************
- *MTSIF_RX3_BAND32_BAND35_ID - MTSIF RX3 Band32 to Band35 ID Register
- ***************************************************************************/
-/* XPT_FE :: MTSIF_RX3_BAND32_BAND35_ID :: reserved0 [31:30] */
-#define BCHP_XPT_FE_MTSIF_RX3_BAND32_BAND35_ID_reserved0_MASK 0xc0000000
-#define BCHP_XPT_FE_MTSIF_RX3_BAND32_BAND35_ID_reserved0_SHIFT 30
-
-/* XPT_FE :: MTSIF_RX3_BAND32_BAND35_ID :: MTSIF_BAND35_BAND_ID [29:24] */
-#define BCHP_XPT_FE_MTSIF_RX3_BAND32_BAND35_ID_MTSIF_BAND35_BAND_ID_MASK 0x3f000000
-#define BCHP_XPT_FE_MTSIF_RX3_BAND32_BAND35_ID_MTSIF_BAND35_BAND_ID_SHIFT 24
-#define BCHP_XPT_FE_MTSIF_RX3_BAND32_BAND35_ID_MTSIF_BAND35_BAND_ID_DEFAULT 0x00000023
-
-/* XPT_FE :: MTSIF_RX3_BAND32_BAND35_ID :: reserved1 [23:22] */
-#define BCHP_XPT_FE_MTSIF_RX3_BAND32_BAND35_ID_reserved1_MASK 0x00c00000
-#define BCHP_XPT_FE_MTSIF_RX3_BAND32_BAND35_ID_reserved1_SHIFT 22
-
-/* XPT_FE :: MTSIF_RX3_BAND32_BAND35_ID :: MTSIF_BAND34_BAND_ID [21:16] */
-#define BCHP_XPT_FE_MTSIF_RX3_BAND32_BAND35_ID_MTSIF_BAND34_BAND_ID_MASK 0x003f0000
-#define BCHP_XPT_FE_MTSIF_RX3_BAND32_BAND35_ID_MTSIF_BAND34_BAND_ID_SHIFT 16
-#define BCHP_XPT_FE_MTSIF_RX3_BAND32_BAND35_ID_MTSIF_BAND34_BAND_ID_DEFAULT 0x00000022
-
-/* XPT_FE :: MTSIF_RX3_BAND32_BAND35_ID :: reserved2 [15:14] */
-#define BCHP_XPT_FE_MTSIF_RX3_BAND32_BAND35_ID_reserved2_MASK 0x0000c000
-#define BCHP_XPT_FE_MTSIF_RX3_BAND32_BAND35_ID_reserved2_SHIFT 14
-
-/* XPT_FE :: MTSIF_RX3_BAND32_BAND35_ID :: MTSIF_BAND33_BAND_ID [13:08] */
-#define BCHP_XPT_FE_MTSIF_RX3_BAND32_BAND35_ID_MTSIF_BAND33_BAND_ID_MASK 0x00003f00
-#define BCHP_XPT_FE_MTSIF_RX3_BAND32_BAND35_ID_MTSIF_BAND33_BAND_ID_SHIFT 8
-#define BCHP_XPT_FE_MTSIF_RX3_BAND32_BAND35_ID_MTSIF_BAND33_BAND_ID_DEFAULT 0x00000021
-
-/* XPT_FE :: MTSIF_RX3_BAND32_BAND35_ID :: reserved3 [07:06] */
-#define BCHP_XPT_FE_MTSIF_RX3_BAND32_BAND35_ID_reserved3_MASK 0x000000c0
-#define BCHP_XPT_FE_MTSIF_RX3_BAND32_BAND35_ID_reserved3_SHIFT 6
-
-/* XPT_FE :: MTSIF_RX3_BAND32_BAND35_ID :: MTSIF_BAND32_BAND_ID [05:00] */
-#define BCHP_XPT_FE_MTSIF_RX3_BAND32_BAND35_ID_MTSIF_BAND32_BAND_ID_MASK 0x0000003f
-#define BCHP_XPT_FE_MTSIF_RX3_BAND32_BAND35_ID_MTSIF_BAND32_BAND_ID_SHIFT 0
-#define BCHP_XPT_FE_MTSIF_RX3_BAND32_BAND35_ID_MTSIF_BAND32_BAND_ID_DEFAULT 0x00000020
-
-/***************************************************************************
- *MTSIF_RX3_BAND36_BAND39_ID - MTSIF RX3 Band36 to Band39 ID Register
- ***************************************************************************/
-/* XPT_FE :: MTSIF_RX3_BAND36_BAND39_ID :: reserved0 [31:30] */
-#define BCHP_XPT_FE_MTSIF_RX3_BAND36_BAND39_ID_reserved0_MASK 0xc0000000
-#define BCHP_XPT_FE_MTSIF_RX3_BAND36_BAND39_ID_reserved0_SHIFT 30
-
-/* XPT_FE :: MTSIF_RX3_BAND36_BAND39_ID :: MTSIF_BAND39_BAND_ID [29:24] */
-#define BCHP_XPT_FE_MTSIF_RX3_BAND36_BAND39_ID_MTSIF_BAND39_BAND_ID_MASK 0x3f000000
-#define BCHP_XPT_FE_MTSIF_RX3_BAND36_BAND39_ID_MTSIF_BAND39_BAND_ID_SHIFT 24
-#define BCHP_XPT_FE_MTSIF_RX3_BAND36_BAND39_ID_MTSIF_BAND39_BAND_ID_DEFAULT 0x00000027
-
-/* XPT_FE :: MTSIF_RX3_BAND36_BAND39_ID :: reserved1 [23:22] */
-#define BCHP_XPT_FE_MTSIF_RX3_BAND36_BAND39_ID_reserved1_MASK 0x00c00000
-#define BCHP_XPT_FE_MTSIF_RX3_BAND36_BAND39_ID_reserved1_SHIFT 22
-
-/* XPT_FE :: MTSIF_RX3_BAND36_BAND39_ID :: MTSIF_BAND38_BAND_ID [21:16] */
-#define BCHP_XPT_FE_MTSIF_RX3_BAND36_BAND39_ID_MTSIF_BAND38_BAND_ID_MASK 0x003f0000
-#define BCHP_XPT_FE_MTSIF_RX3_BAND36_BAND39_ID_MTSIF_BAND38_BAND_ID_SHIFT 16
-#define BCHP_XPT_FE_MTSIF_RX3_BAND36_BAND39_ID_MTSIF_BAND38_BAND_ID_DEFAULT 0x00000026
-
-/* XPT_FE :: MTSIF_RX3_BAND36_BAND39_ID :: reserved2 [15:14] */
-#define BCHP_XPT_FE_MTSIF_RX3_BAND36_BAND39_ID_reserved2_MASK 0x0000c000
-#define BCHP_XPT_FE_MTSIF_RX3_BAND36_BAND39_ID_reserved2_SHIFT 14
-
-/* XPT_FE :: MTSIF_RX3_BAND36_BAND39_ID :: MTSIF_BAND37_BAND_ID [13:08] */
-#define BCHP_XPT_FE_MTSIF_RX3_BAND36_BAND39_ID_MTSIF_BAND37_BAND_ID_MASK 0x00003f00
-#define BCHP_XPT_FE_MTSIF_RX3_BAND36_BAND39_ID_MTSIF_BAND37_BAND_ID_SHIFT 8
-#define BCHP_XPT_FE_MTSIF_RX3_BAND36_BAND39_ID_MTSIF_BAND37_BAND_ID_DEFAULT 0x00000025
-
-/* XPT_FE :: MTSIF_RX3_BAND36_BAND39_ID :: reserved3 [07:06] */
-#define BCHP_XPT_FE_MTSIF_RX3_BAND36_BAND39_ID_reserved3_MASK 0x000000c0
-#define BCHP_XPT_FE_MTSIF_RX3_BAND36_BAND39_ID_reserved3_SHIFT 6
-
-/* XPT_FE :: MTSIF_RX3_BAND36_BAND39_ID :: MTSIF_BAND36_BAND_ID [05:00] */
-#define BCHP_XPT_FE_MTSIF_RX3_BAND36_BAND39_ID_MTSIF_BAND36_BAND_ID_MASK 0x0000003f
-#define BCHP_XPT_FE_MTSIF_RX3_BAND36_BAND39_ID_MTSIF_BAND36_BAND_ID_SHIFT 0
-#define BCHP_XPT_FE_MTSIF_RX3_BAND36_BAND39_ID_MTSIF_BAND36_BAND_ID_DEFAULT 0x00000024
-
-/***************************************************************************
- *MTSIF_RX3_BAND40_BAND43_ID - MTSIF RX3 Band40 to Band43 ID Register
- ***************************************************************************/
-/* XPT_FE :: MTSIF_RX3_BAND40_BAND43_ID :: reserved0 [31:30] */
-#define BCHP_XPT_FE_MTSIF_RX3_BAND40_BAND43_ID_reserved0_MASK 0xc0000000
-#define BCHP_XPT_FE_MTSIF_RX3_BAND40_BAND43_ID_reserved0_SHIFT 30
-
-/* XPT_FE :: MTSIF_RX3_BAND40_BAND43_ID :: MTSIF_BAND43_BAND_ID [29:24] */
-#define BCHP_XPT_FE_MTSIF_RX3_BAND40_BAND43_ID_MTSIF_BAND43_BAND_ID_MASK 0x3f000000
-#define BCHP_XPT_FE_MTSIF_RX3_BAND40_BAND43_ID_MTSIF_BAND43_BAND_ID_SHIFT 24
-#define BCHP_XPT_FE_MTSIF_RX3_BAND40_BAND43_ID_MTSIF_BAND43_BAND_ID_DEFAULT 0x0000002b
-
-/* XPT_FE :: MTSIF_RX3_BAND40_BAND43_ID :: reserved1 [23:22] */
-#define BCHP_XPT_FE_MTSIF_RX3_BAND40_BAND43_ID_reserved1_MASK 0x00c00000
-#define BCHP_XPT_FE_MTSIF_RX3_BAND40_BAND43_ID_reserved1_SHIFT 22
-
-/* XPT_FE :: MTSIF_RX3_BAND40_BAND43_ID :: MTSIF_BAND42_BAND_ID [21:16] */
-#define BCHP_XPT_FE_MTSIF_RX3_BAND40_BAND43_ID_MTSIF_BAND42_BAND_ID_MASK 0x003f0000
-#define BCHP_XPT_FE_MTSIF_RX3_BAND40_BAND43_ID_MTSIF_BAND42_BAND_ID_SHIFT 16
-#define BCHP_XPT_FE_MTSIF_RX3_BAND40_BAND43_ID_MTSIF_BAND42_BAND_ID_DEFAULT 0x0000002a
-
-/* XPT_FE :: MTSIF_RX3_BAND40_BAND43_ID :: reserved2 [15:14] */
-#define BCHP_XPT_FE_MTSIF_RX3_BAND40_BAND43_ID_reserved2_MASK 0x0000c000
-#define BCHP_XPT_FE_MTSIF_RX3_BAND40_BAND43_ID_reserved2_SHIFT 14
-
-/* XPT_FE :: MTSIF_RX3_BAND40_BAND43_ID :: MTSIF_BAND41_BAND_ID [13:08] */
-#define BCHP_XPT_FE_MTSIF_RX3_BAND40_BAND43_ID_MTSIF_BAND41_BAND_ID_MASK 0x00003f00
-#define BCHP_XPT_FE_MTSIF_RX3_BAND40_BAND43_ID_MTSIF_BAND41_BAND_ID_SHIFT 8
-#define BCHP_XPT_FE_MTSIF_RX3_BAND40_BAND43_ID_MTSIF_BAND41_BAND_ID_DEFAULT 0x00000029
-
-/* XPT_FE :: MTSIF_RX3_BAND40_BAND43_ID :: reserved3 [07:06] */
-#define BCHP_XPT_FE_MTSIF_RX3_BAND40_BAND43_ID_reserved3_MASK 0x000000c0
-#define BCHP_XPT_FE_MTSIF_RX3_BAND40_BAND43_ID_reserved3_SHIFT 6
-
-/* XPT_FE :: MTSIF_RX3_BAND40_BAND43_ID :: MTSIF_BAND40_BAND_ID [05:00] */
-#define BCHP_XPT_FE_MTSIF_RX3_BAND40_BAND43_ID_MTSIF_BAND40_BAND_ID_MASK 0x0000003f
-#define BCHP_XPT_FE_MTSIF_RX3_BAND40_BAND43_ID_MTSIF_BAND40_BAND_ID_SHIFT 0
-#define BCHP_XPT_FE_MTSIF_RX3_BAND40_BAND43_ID_MTSIF_BAND40_BAND_ID_DEFAULT 0x00000028
-
-/***************************************************************************
- *MTSIF_RX3_BAND44_BAND47_ID - MTSIF RX3 Band44 to Band47 ID Register
- ***************************************************************************/
-/* XPT_FE :: MTSIF_RX3_BAND44_BAND47_ID :: reserved0 [31:30] */
-#define BCHP_XPT_FE_MTSIF_RX3_BAND44_BAND47_ID_reserved0_MASK 0xc0000000
-#define BCHP_XPT_FE_MTSIF_RX3_BAND44_BAND47_ID_reserved0_SHIFT 30
-
-/* XPT_FE :: MTSIF_RX3_BAND44_BAND47_ID :: MTSIF_BAND47_BAND_ID [29:24] */
-#define BCHP_XPT_FE_MTSIF_RX3_BAND44_BAND47_ID_MTSIF_BAND47_BAND_ID_MASK 0x3f000000
-#define BCHP_XPT_FE_MTSIF_RX3_BAND44_BAND47_ID_MTSIF_BAND47_BAND_ID_SHIFT 24
-#define BCHP_XPT_FE_MTSIF_RX3_BAND44_BAND47_ID_MTSIF_BAND47_BAND_ID_DEFAULT 0x0000002f
-
-/* XPT_FE :: MTSIF_RX3_BAND44_BAND47_ID :: reserved1 [23:22] */
-#define BCHP_XPT_FE_MTSIF_RX3_BAND44_BAND47_ID_reserved1_MASK 0x00c00000
-#define BCHP_XPT_FE_MTSIF_RX3_BAND44_BAND47_ID_reserved1_SHIFT 22
-
-/* XPT_FE :: MTSIF_RX3_BAND44_BAND47_ID :: MTSIF_BAND46_BAND_ID [21:16] */
-#define BCHP_XPT_FE_MTSIF_RX3_BAND44_BAND47_ID_MTSIF_BAND46_BAND_ID_MASK 0x003f0000
-#define BCHP_XPT_FE_MTSIF_RX3_BAND44_BAND47_ID_MTSIF_BAND46_BAND_ID_SHIFT 16
-#define BCHP_XPT_FE_MTSIF_RX3_BAND44_BAND47_ID_MTSIF_BAND46_BAND_ID_DEFAULT 0x0000002e
-
-/* XPT_FE :: MTSIF_RX3_BAND44_BAND47_ID :: reserved2 [15:14] */
-#define BCHP_XPT_FE_MTSIF_RX3_BAND44_BAND47_ID_reserved2_MASK 0x0000c000
-#define BCHP_XPT_FE_MTSIF_RX3_BAND44_BAND47_ID_reserved2_SHIFT 14
-
-/* XPT_FE :: MTSIF_RX3_BAND44_BAND47_ID :: MTSIF_BAND45_BAND_ID [13:08] */
-#define BCHP_XPT_FE_MTSIF_RX3_BAND44_BAND47_ID_MTSIF_BAND45_BAND_ID_MASK 0x00003f00
-#define BCHP_XPT_FE_MTSIF_RX3_BAND44_BAND47_ID_MTSIF_BAND45_BAND_ID_SHIFT 8
-#define BCHP_XPT_FE_MTSIF_RX3_BAND44_BAND47_ID_MTSIF_BAND45_BAND_ID_DEFAULT 0x0000002d
-
-/* XPT_FE :: MTSIF_RX3_BAND44_BAND47_ID :: reserved3 [07:06] */
-#define BCHP_XPT_FE_MTSIF_RX3_BAND44_BAND47_ID_reserved3_MASK 0x000000c0
-#define BCHP_XPT_FE_MTSIF_RX3_BAND44_BAND47_ID_reserved3_SHIFT 6
-
-/* XPT_FE :: MTSIF_RX3_BAND44_BAND47_ID :: MTSIF_BAND44_BAND_ID [05:00] */
-#define BCHP_XPT_FE_MTSIF_RX3_BAND44_BAND47_ID_MTSIF_BAND44_BAND_ID_MASK 0x0000003f
-#define BCHP_XPT_FE_MTSIF_RX3_BAND44_BAND47_ID_MTSIF_BAND44_BAND_ID_SHIFT 0
-#define BCHP_XPT_FE_MTSIF_RX3_BAND44_BAND47_ID_MTSIF_BAND44_BAND_ID_DEFAULT 0x0000002c
-
-/***************************************************************************
- *MTSIF_RX3_BAND48_BAND51_ID - MTSIF RX3 Band48 to Band51 ID Register
- ***************************************************************************/
-/* XPT_FE :: MTSIF_RX3_BAND48_BAND51_ID :: reserved0 [31:30] */
-#define BCHP_XPT_FE_MTSIF_RX3_BAND48_BAND51_ID_reserved0_MASK 0xc0000000
-#define BCHP_XPT_FE_MTSIF_RX3_BAND48_BAND51_ID_reserved0_SHIFT 30
-
-/* XPT_FE :: MTSIF_RX3_BAND48_BAND51_ID :: MTSIF_BAND51_BAND_ID [29:24] */
-#define BCHP_XPT_FE_MTSIF_RX3_BAND48_BAND51_ID_MTSIF_BAND51_BAND_ID_MASK 0x3f000000
-#define BCHP_XPT_FE_MTSIF_RX3_BAND48_BAND51_ID_MTSIF_BAND51_BAND_ID_SHIFT 24
-#define BCHP_XPT_FE_MTSIF_RX3_BAND48_BAND51_ID_MTSIF_BAND51_BAND_ID_DEFAULT 0x00000033
-
-/* XPT_FE :: MTSIF_RX3_BAND48_BAND51_ID :: reserved1 [23:22] */
-#define BCHP_XPT_FE_MTSIF_RX3_BAND48_BAND51_ID_reserved1_MASK 0x00c00000
-#define BCHP_XPT_FE_MTSIF_RX3_BAND48_BAND51_ID_reserved1_SHIFT 22
-
-/* XPT_FE :: MTSIF_RX3_BAND48_BAND51_ID :: MTSIF_BAND50_BAND_ID [21:16] */
-#define BCHP_XPT_FE_MTSIF_RX3_BAND48_BAND51_ID_MTSIF_BAND50_BAND_ID_MASK 0x003f0000
-#define BCHP_XPT_FE_MTSIF_RX3_BAND48_BAND51_ID_MTSIF_BAND50_BAND_ID_SHIFT 16
-#define BCHP_XPT_FE_MTSIF_RX3_BAND48_BAND51_ID_MTSIF_BAND50_BAND_ID_DEFAULT 0x00000032
-
-/* XPT_FE :: MTSIF_RX3_BAND48_BAND51_ID :: reserved2 [15:14] */
-#define BCHP_XPT_FE_MTSIF_RX3_BAND48_BAND51_ID_reserved2_MASK 0x0000c000
-#define BCHP_XPT_FE_MTSIF_RX3_BAND48_BAND51_ID_reserved2_SHIFT 14
-
-/* XPT_FE :: MTSIF_RX3_BAND48_BAND51_ID :: MTSIF_BAND49_BAND_ID [13:08] */
-#define BCHP_XPT_FE_MTSIF_RX3_BAND48_BAND51_ID_MTSIF_BAND49_BAND_ID_MASK 0x00003f00
-#define BCHP_XPT_FE_MTSIF_RX3_BAND48_BAND51_ID_MTSIF_BAND49_BAND_ID_SHIFT 8
-#define BCHP_XPT_FE_MTSIF_RX3_BAND48_BAND51_ID_MTSIF_BAND49_BAND_ID_DEFAULT 0x00000031
-
-/* XPT_FE :: MTSIF_RX3_BAND48_BAND51_ID :: reserved3 [07:06] */
-#define BCHP_XPT_FE_MTSIF_RX3_BAND48_BAND51_ID_reserved3_MASK 0x000000c0
-#define BCHP_XPT_FE_MTSIF_RX3_BAND48_BAND51_ID_reserved3_SHIFT 6
-
-/* XPT_FE :: MTSIF_RX3_BAND48_BAND51_ID :: MTSIF_BAND48_BAND_ID [05:00] */
-#define BCHP_XPT_FE_MTSIF_RX3_BAND48_BAND51_ID_MTSIF_BAND48_BAND_ID_MASK 0x0000003f
-#define BCHP_XPT_FE_MTSIF_RX3_BAND48_BAND51_ID_MTSIF_BAND48_BAND_ID_SHIFT 0
-#define BCHP_XPT_FE_MTSIF_RX3_BAND48_BAND51_ID_MTSIF_BAND48_BAND_ID_DEFAULT 0x00000030
-
-/***************************************************************************
- *MTSIF_RX3_BAND52_BAND55_ID - MTSIF RX3 Band52 to Band55 ID Register
- ***************************************************************************/
-/* XPT_FE :: MTSIF_RX3_BAND52_BAND55_ID :: reserved0 [31:30] */
-#define BCHP_XPT_FE_MTSIF_RX3_BAND52_BAND55_ID_reserved0_MASK 0xc0000000
-#define BCHP_XPT_FE_MTSIF_RX3_BAND52_BAND55_ID_reserved0_SHIFT 30
-
-/* XPT_FE :: MTSIF_RX3_BAND52_BAND55_ID :: MTSIF_BAND55_BAND_ID [29:24] */
-#define BCHP_XPT_FE_MTSIF_RX3_BAND52_BAND55_ID_MTSIF_BAND55_BAND_ID_MASK 0x3f000000
-#define BCHP_XPT_FE_MTSIF_RX3_BAND52_BAND55_ID_MTSIF_BAND55_BAND_ID_SHIFT 24
-#define BCHP_XPT_FE_MTSIF_RX3_BAND52_BAND55_ID_MTSIF_BAND55_BAND_ID_DEFAULT 0x00000037
-
-/* XPT_FE :: MTSIF_RX3_BAND52_BAND55_ID :: reserved1 [23:22] */
-#define BCHP_XPT_FE_MTSIF_RX3_BAND52_BAND55_ID_reserved1_MASK 0x00c00000
-#define BCHP_XPT_FE_MTSIF_RX3_BAND52_BAND55_ID_reserved1_SHIFT 22
-
-/* XPT_FE :: MTSIF_RX3_BAND52_BAND55_ID :: MTSIF_BAND54_BAND_ID [21:16] */
-#define BCHP_XPT_FE_MTSIF_RX3_BAND52_BAND55_ID_MTSIF_BAND54_BAND_ID_MASK 0x003f0000
-#define BCHP_XPT_FE_MTSIF_RX3_BAND52_BAND55_ID_MTSIF_BAND54_BAND_ID_SHIFT 16
-#define BCHP_XPT_FE_MTSIF_RX3_BAND52_BAND55_ID_MTSIF_BAND54_BAND_ID_DEFAULT 0x00000036
-
-/* XPT_FE :: MTSIF_RX3_BAND52_BAND55_ID :: reserved2 [15:14] */
-#define BCHP_XPT_FE_MTSIF_RX3_BAND52_BAND55_ID_reserved2_MASK 0x0000c000
-#define BCHP_XPT_FE_MTSIF_RX3_BAND52_BAND55_ID_reserved2_SHIFT 14
-
-/* XPT_FE :: MTSIF_RX3_BAND52_BAND55_ID :: MTSIF_BAND53_BAND_ID [13:08] */
-#define BCHP_XPT_FE_MTSIF_RX3_BAND52_BAND55_ID_MTSIF_BAND53_BAND_ID_MASK 0x00003f00
-#define BCHP_XPT_FE_MTSIF_RX3_BAND52_BAND55_ID_MTSIF_BAND53_BAND_ID_SHIFT 8
-#define BCHP_XPT_FE_MTSIF_RX3_BAND52_BAND55_ID_MTSIF_BAND53_BAND_ID_DEFAULT 0x00000035
-
-/* XPT_FE :: MTSIF_RX3_BAND52_BAND55_ID :: reserved3 [07:06] */
-#define BCHP_XPT_FE_MTSIF_RX3_BAND52_BAND55_ID_reserved3_MASK 0x000000c0
-#define BCHP_XPT_FE_MTSIF_RX3_BAND52_BAND55_ID_reserved3_SHIFT 6
-
-/* XPT_FE :: MTSIF_RX3_BAND52_BAND55_ID :: MTSIF_BAND52_BAND_ID [05:00] */
-#define BCHP_XPT_FE_MTSIF_RX3_BAND52_BAND55_ID_MTSIF_BAND52_BAND_ID_MASK 0x0000003f
-#define BCHP_XPT_FE_MTSIF_RX3_BAND52_BAND55_ID_MTSIF_BAND52_BAND_ID_SHIFT 0
-#define BCHP_XPT_FE_MTSIF_RX3_BAND52_BAND55_ID_MTSIF_BAND52_BAND_ID_DEFAULT 0x00000034
-
-/***************************************************************************
- *MTSIF_RX3_BAND56_BAND59_ID - MTSIF RX3 Band56 to Band59 ID Register
- ***************************************************************************/
-/* XPT_FE :: MTSIF_RX3_BAND56_BAND59_ID :: reserved0 [31:30] */
-#define BCHP_XPT_FE_MTSIF_RX3_BAND56_BAND59_ID_reserved0_MASK 0xc0000000
-#define BCHP_XPT_FE_MTSIF_RX3_BAND56_BAND59_ID_reserved0_SHIFT 30
-
-/* XPT_FE :: MTSIF_RX3_BAND56_BAND59_ID :: MTSIF_BAND59_BAND_ID [29:24] */
-#define BCHP_XPT_FE_MTSIF_RX3_BAND56_BAND59_ID_MTSIF_BAND59_BAND_ID_MASK 0x3f000000
-#define BCHP_XPT_FE_MTSIF_RX3_BAND56_BAND59_ID_MTSIF_BAND59_BAND_ID_SHIFT 24
-#define BCHP_XPT_FE_MTSIF_RX3_BAND56_BAND59_ID_MTSIF_BAND59_BAND_ID_DEFAULT 0x0000003b
-
-/* XPT_FE :: MTSIF_RX3_BAND56_BAND59_ID :: reserved1 [23:22] */
-#define BCHP_XPT_FE_MTSIF_RX3_BAND56_BAND59_ID_reserved1_MASK 0x00c00000
-#define BCHP_XPT_FE_MTSIF_RX3_BAND56_BAND59_ID_reserved1_SHIFT 22
-
-/* XPT_FE :: MTSIF_RX3_BAND56_BAND59_ID :: MTSIF_BAND58_BAND_ID [21:16] */
-#define BCHP_XPT_FE_MTSIF_RX3_BAND56_BAND59_ID_MTSIF_BAND58_BAND_ID_MASK 0x003f0000
-#define BCHP_XPT_FE_MTSIF_RX3_BAND56_BAND59_ID_MTSIF_BAND58_BAND_ID_SHIFT 16
-#define BCHP_XPT_FE_MTSIF_RX3_BAND56_BAND59_ID_MTSIF_BAND58_BAND_ID_DEFAULT 0x0000003a
-
-/* XPT_FE :: MTSIF_RX3_BAND56_BAND59_ID :: reserved2 [15:14] */
-#define BCHP_XPT_FE_MTSIF_RX3_BAND56_BAND59_ID_reserved2_MASK 0x0000c000
-#define BCHP_XPT_FE_MTSIF_RX3_BAND56_BAND59_ID_reserved2_SHIFT 14
-
-/* XPT_FE :: MTSIF_RX3_BAND56_BAND59_ID :: MTSIF_BAND57_BAND_ID [13:08] */
-#define BCHP_XPT_FE_MTSIF_RX3_BAND56_BAND59_ID_MTSIF_BAND57_BAND_ID_MASK 0x00003f00
-#define BCHP_XPT_FE_MTSIF_RX3_BAND56_BAND59_ID_MTSIF_BAND57_BAND_ID_SHIFT 8
-#define BCHP_XPT_FE_MTSIF_RX3_BAND56_BAND59_ID_MTSIF_BAND57_BAND_ID_DEFAULT 0x00000039
-
-/* XPT_FE :: MTSIF_RX3_BAND56_BAND59_ID :: reserved3 [07:06] */
-#define BCHP_XPT_FE_MTSIF_RX3_BAND56_BAND59_ID_reserved3_MASK 0x000000c0
-#define BCHP_XPT_FE_MTSIF_RX3_BAND56_BAND59_ID_reserved3_SHIFT 6
-
-/* XPT_FE :: MTSIF_RX3_BAND56_BAND59_ID :: MTSIF_BAND56_BAND_ID [05:00] */
-#define BCHP_XPT_FE_MTSIF_RX3_BAND56_BAND59_ID_MTSIF_BAND56_BAND_ID_MASK 0x0000003f
-#define BCHP_XPT_FE_MTSIF_RX3_BAND56_BAND59_ID_MTSIF_BAND56_BAND_ID_SHIFT 0
-#define BCHP_XPT_FE_MTSIF_RX3_BAND56_BAND59_ID_MTSIF_BAND56_BAND_ID_DEFAULT 0x00000038
-
-/***************************************************************************
- *MTSIF_RX3_BAND60_BAND63_ID - MTSIF RX3 Band60 to Band63 ID Register
- ***************************************************************************/
-/* XPT_FE :: MTSIF_RX3_BAND60_BAND63_ID :: reserved0 [31:30] */
-#define BCHP_XPT_FE_MTSIF_RX3_BAND60_BAND63_ID_reserved0_MASK 0xc0000000
-#define BCHP_XPT_FE_MTSIF_RX3_BAND60_BAND63_ID_reserved0_SHIFT 30
-
-/* XPT_FE :: MTSIF_RX3_BAND60_BAND63_ID :: MTSIF_BAND63_BAND_ID [29:24] */
-#define BCHP_XPT_FE_MTSIF_RX3_BAND60_BAND63_ID_MTSIF_BAND63_BAND_ID_MASK 0x3f000000
-#define BCHP_XPT_FE_MTSIF_RX3_BAND60_BAND63_ID_MTSIF_BAND63_BAND_ID_SHIFT 24
-#define BCHP_XPT_FE_MTSIF_RX3_BAND60_BAND63_ID_MTSIF_BAND63_BAND_ID_DEFAULT 0x0000003f
-
-/* XPT_FE :: MTSIF_RX3_BAND60_BAND63_ID :: reserved1 [23:22] */
-#define BCHP_XPT_FE_MTSIF_RX3_BAND60_BAND63_ID_reserved1_MASK 0x00c00000
-#define BCHP_XPT_FE_MTSIF_RX3_BAND60_BAND63_ID_reserved1_SHIFT 22
-
-/* XPT_FE :: MTSIF_RX3_BAND60_BAND63_ID :: MTSIF_BAND62_BAND_ID [21:16] */
-#define BCHP_XPT_FE_MTSIF_RX3_BAND60_BAND63_ID_MTSIF_BAND62_BAND_ID_MASK 0x003f0000
-#define BCHP_XPT_FE_MTSIF_RX3_BAND60_BAND63_ID_MTSIF_BAND62_BAND_ID_SHIFT 16
-#define BCHP_XPT_FE_MTSIF_RX3_BAND60_BAND63_ID_MTSIF_BAND62_BAND_ID_DEFAULT 0x0000003e
-
-/* XPT_FE :: MTSIF_RX3_BAND60_BAND63_ID :: reserved2 [15:14] */
-#define BCHP_XPT_FE_MTSIF_RX3_BAND60_BAND63_ID_reserved2_MASK 0x0000c000
-#define BCHP_XPT_FE_MTSIF_RX3_BAND60_BAND63_ID_reserved2_SHIFT 14
-
-/* XPT_FE :: MTSIF_RX3_BAND60_BAND63_ID :: MTSIF_BAND61_BAND_ID [13:08] */
-#define BCHP_XPT_FE_MTSIF_RX3_BAND60_BAND63_ID_MTSIF_BAND61_BAND_ID_MASK 0x00003f00
-#define BCHP_XPT_FE_MTSIF_RX3_BAND60_BAND63_ID_MTSIF_BAND61_BAND_ID_SHIFT 8
-#define BCHP_XPT_FE_MTSIF_RX3_BAND60_BAND63_ID_MTSIF_BAND61_BAND_ID_DEFAULT 0x0000003d
-
-/* XPT_FE :: MTSIF_RX3_BAND60_BAND63_ID :: reserved3 [07:06] */
-#define BCHP_XPT_FE_MTSIF_RX3_BAND60_BAND63_ID_reserved3_MASK 0x000000c0
-#define BCHP_XPT_FE_MTSIF_RX3_BAND60_BAND63_ID_reserved3_SHIFT 6
-
-/* XPT_FE :: MTSIF_RX3_BAND60_BAND63_ID :: MTSIF_BAND60_BAND_ID [05:00] */
-#define BCHP_XPT_FE_MTSIF_RX3_BAND60_BAND63_ID_MTSIF_BAND60_BAND_ID_MASK 0x0000003f
-#define BCHP_XPT_FE_MTSIF_RX3_BAND60_BAND63_ID_MTSIF_BAND60_BAND_ID_SHIFT 0
-#define BCHP_XPT_FE_MTSIF_RX3_BAND60_BAND63_ID_MTSIF_BAND60_BAND_ID_DEFAULT 0x0000003c
-
-/***************************************************************************
- *MTSIF_RX3_PKT_BAND0_BAND31_DETECT - MTSIF RX3 Packet Band0 to Band31 Detect Register
- ***************************************************************************/
-/* XPT_FE :: MTSIF_RX3_PKT_BAND0_BAND31_DETECT :: BAND_ID31 [31:31] */
-#define BCHP_XPT_FE_MTSIF_RX3_PKT_BAND0_BAND31_DETECT_BAND_ID31_MASK 0x80000000
-#define BCHP_XPT_FE_MTSIF_RX3_PKT_BAND0_BAND31_DETECT_BAND_ID31_SHIFT 31
-#define BCHP_XPT_FE_MTSIF_RX3_PKT_BAND0_BAND31_DETECT_BAND_ID31_DEFAULT 0x00000000
-
-/* XPT_FE :: MTSIF_RX3_PKT_BAND0_BAND31_DETECT :: BAND_ID30 [30:30] */
-#define BCHP_XPT_FE_MTSIF_RX3_PKT_BAND0_BAND31_DETECT_BAND_ID30_MASK 0x40000000
-#define BCHP_XPT_FE_MTSIF_RX3_PKT_BAND0_BAND31_DETECT_BAND_ID30_SHIFT 30
-#define BCHP_XPT_FE_MTSIF_RX3_PKT_BAND0_BAND31_DETECT_BAND_ID30_DEFAULT 0x00000000
-
-/* XPT_FE :: MTSIF_RX3_PKT_BAND0_BAND31_DETECT :: BAND_ID29 [29:29] */
-#define BCHP_XPT_FE_MTSIF_RX3_PKT_BAND0_BAND31_DETECT_BAND_ID29_MASK 0x20000000
-#define BCHP_XPT_FE_MTSIF_RX3_PKT_BAND0_BAND31_DETECT_BAND_ID29_SHIFT 29
-#define BCHP_XPT_FE_MTSIF_RX3_PKT_BAND0_BAND31_DETECT_BAND_ID29_DEFAULT 0x00000000
-
-/* XPT_FE :: MTSIF_RX3_PKT_BAND0_BAND31_DETECT :: BAND_ID28 [28:28] */
-#define BCHP_XPT_FE_MTSIF_RX3_PKT_BAND0_BAND31_DETECT_BAND_ID28_MASK 0x10000000
-#define BCHP_XPT_FE_MTSIF_RX3_PKT_BAND0_BAND31_DETECT_BAND_ID28_SHIFT 28
-#define BCHP_XPT_FE_MTSIF_RX3_PKT_BAND0_BAND31_DETECT_BAND_ID28_DEFAULT 0x00000000
-
-/* XPT_FE :: MTSIF_RX3_PKT_BAND0_BAND31_DETECT :: BAND_ID27 [27:27] */
-#define BCHP_XPT_FE_MTSIF_RX3_PKT_BAND0_BAND31_DETECT_BAND_ID27_MASK 0x08000000
-#define BCHP_XPT_FE_MTSIF_RX3_PKT_BAND0_BAND31_DETECT_BAND_ID27_SHIFT 27
-#define BCHP_XPT_FE_MTSIF_RX3_PKT_BAND0_BAND31_DETECT_BAND_ID27_DEFAULT 0x00000000
-
-/* XPT_FE :: MTSIF_RX3_PKT_BAND0_BAND31_DETECT :: BAND_ID26 [26:26] */
-#define BCHP_XPT_FE_MTSIF_RX3_PKT_BAND0_BAND31_DETECT_BAND_ID26_MASK 0x04000000
-#define BCHP_XPT_FE_MTSIF_RX3_PKT_BAND0_BAND31_DETECT_BAND_ID26_SHIFT 26
-#define BCHP_XPT_FE_MTSIF_RX3_PKT_BAND0_BAND31_DETECT_BAND_ID26_DEFAULT 0x00000000
-
-/* XPT_FE :: MTSIF_RX3_PKT_BAND0_BAND31_DETECT :: BAND_ID25 [25:25] */
-#define BCHP_XPT_FE_MTSIF_RX3_PKT_BAND0_BAND31_DETECT_BAND_ID25_MASK 0x02000000
-#define BCHP_XPT_FE_MTSIF_RX3_PKT_BAND0_BAND31_DETECT_BAND_ID25_SHIFT 25
-#define BCHP_XPT_FE_MTSIF_RX3_PKT_BAND0_BAND31_DETECT_BAND_ID25_DEFAULT 0x00000000
-
-/* XPT_FE :: MTSIF_RX3_PKT_BAND0_BAND31_DETECT :: BAND_ID24 [24:24] */
-#define BCHP_XPT_FE_MTSIF_RX3_PKT_BAND0_BAND31_DETECT_BAND_ID24_MASK 0x01000000
-#define BCHP_XPT_FE_MTSIF_RX3_PKT_BAND0_BAND31_DETECT_BAND_ID24_SHIFT 24
-#define BCHP_XPT_FE_MTSIF_RX3_PKT_BAND0_BAND31_DETECT_BAND_ID24_DEFAULT 0x00000000
-
-/* XPT_FE :: MTSIF_RX3_PKT_BAND0_BAND31_DETECT :: BAND_ID23 [23:23] */
-#define BCHP_XPT_FE_MTSIF_RX3_PKT_BAND0_BAND31_DETECT_BAND_ID23_MASK 0x00800000
-#define BCHP_XPT_FE_MTSIF_RX3_PKT_BAND0_BAND31_DETECT_BAND_ID23_SHIFT 23
-#define BCHP_XPT_FE_MTSIF_RX3_PKT_BAND0_BAND31_DETECT_BAND_ID23_DEFAULT 0x00000000
-
-/* XPT_FE :: MTSIF_RX3_PKT_BAND0_BAND31_DETECT :: BAND_ID22 [22:22] */
-#define BCHP_XPT_FE_MTSIF_RX3_PKT_BAND0_BAND31_DETECT_BAND_ID22_MASK 0x00400000
-#define BCHP_XPT_FE_MTSIF_RX3_PKT_BAND0_BAND31_DETECT_BAND_ID22_SHIFT 22
-#define BCHP_XPT_FE_MTSIF_RX3_PKT_BAND0_BAND31_DETECT_BAND_ID22_DEFAULT 0x00000000
-
-/* XPT_FE :: MTSIF_RX3_PKT_BAND0_BAND31_DETECT :: BAND_ID21 [21:21] */
-#define BCHP_XPT_FE_MTSIF_RX3_PKT_BAND0_BAND31_DETECT_BAND_ID21_MASK 0x00200000
-#define BCHP_XPT_FE_MTSIF_RX3_PKT_BAND0_BAND31_DETECT_BAND_ID21_SHIFT 21
-#define BCHP_XPT_FE_MTSIF_RX3_PKT_BAND0_BAND31_DETECT_BAND_ID21_DEFAULT 0x00000000
-
-/* XPT_FE :: MTSIF_RX3_PKT_BAND0_BAND31_DETECT :: BAND_ID20 [20:20] */
-#define BCHP_XPT_FE_MTSIF_RX3_PKT_BAND0_BAND31_DETECT_BAND_ID20_MASK 0x00100000
-#define BCHP_XPT_FE_MTSIF_RX3_PKT_BAND0_BAND31_DETECT_BAND_ID20_SHIFT 20
-#define BCHP_XPT_FE_MTSIF_RX3_PKT_BAND0_BAND31_DETECT_BAND_ID20_DEFAULT 0x00000000
-
-/* XPT_FE :: MTSIF_RX3_PKT_BAND0_BAND31_DETECT :: BAND_ID19 [19:19] */
-#define BCHP_XPT_FE_MTSIF_RX3_PKT_BAND0_BAND31_DETECT_BAND_ID19_MASK 0x00080000
-#define BCHP_XPT_FE_MTSIF_RX3_PKT_BAND0_BAND31_DETECT_BAND_ID19_SHIFT 19
-#define BCHP_XPT_FE_MTSIF_RX3_PKT_BAND0_BAND31_DETECT_BAND_ID19_DEFAULT 0x00000000
-
-/* XPT_FE :: MTSIF_RX3_PKT_BAND0_BAND31_DETECT :: BAND_ID18 [18:18] */
-#define BCHP_XPT_FE_MTSIF_RX3_PKT_BAND0_BAND31_DETECT_BAND_ID18_MASK 0x00040000
-#define BCHP_XPT_FE_MTSIF_RX3_PKT_BAND0_BAND31_DETECT_BAND_ID18_SHIFT 18
-#define BCHP_XPT_FE_MTSIF_RX3_PKT_BAND0_BAND31_DETECT_BAND_ID18_DEFAULT 0x00000000
-
-/* XPT_FE :: MTSIF_RX3_PKT_BAND0_BAND31_DETECT :: BAND_ID17 [17:17] */
-#define BCHP_XPT_FE_MTSIF_RX3_PKT_BAND0_BAND31_DETECT_BAND_ID17_MASK 0x00020000
-#define BCHP_XPT_FE_MTSIF_RX3_PKT_BAND0_BAND31_DETECT_BAND_ID17_SHIFT 17
-#define BCHP_XPT_FE_MTSIF_RX3_PKT_BAND0_BAND31_DETECT_BAND_ID17_DEFAULT 0x00000000
-
-/* XPT_FE :: MTSIF_RX3_PKT_BAND0_BAND31_DETECT :: BAND_ID16 [16:16] */
-#define BCHP_XPT_FE_MTSIF_RX3_PKT_BAND0_BAND31_DETECT_BAND_ID16_MASK 0x00010000
-#define BCHP_XPT_FE_MTSIF_RX3_PKT_BAND0_BAND31_DETECT_BAND_ID16_SHIFT 16
-#define BCHP_XPT_FE_MTSIF_RX3_PKT_BAND0_BAND31_DETECT_BAND_ID16_DEFAULT 0x00000000
-
-/* XPT_FE :: MTSIF_RX3_PKT_BAND0_BAND31_DETECT :: BAND_ID15 [15:15] */
-#define BCHP_XPT_FE_MTSIF_RX3_PKT_BAND0_BAND31_DETECT_BAND_ID15_MASK 0x00008000
-#define BCHP_XPT_FE_MTSIF_RX3_PKT_BAND0_BAND31_DETECT_BAND_ID15_SHIFT 15
-#define BCHP_XPT_FE_MTSIF_RX3_PKT_BAND0_BAND31_DETECT_BAND_ID15_DEFAULT 0x00000000
-
-/* XPT_FE :: MTSIF_RX3_PKT_BAND0_BAND31_DETECT :: BAND_ID14 [14:14] */
-#define BCHP_XPT_FE_MTSIF_RX3_PKT_BAND0_BAND31_DETECT_BAND_ID14_MASK 0x00004000
-#define BCHP_XPT_FE_MTSIF_RX3_PKT_BAND0_BAND31_DETECT_BAND_ID14_SHIFT 14
-#define BCHP_XPT_FE_MTSIF_RX3_PKT_BAND0_BAND31_DETECT_BAND_ID14_DEFAULT 0x00000000
-
-/* XPT_FE :: MTSIF_RX3_PKT_BAND0_BAND31_DETECT :: BAND_ID13 [13:13] */
-#define BCHP_XPT_FE_MTSIF_RX3_PKT_BAND0_BAND31_DETECT_BAND_ID13_MASK 0x00002000
-#define BCHP_XPT_FE_MTSIF_RX3_PKT_BAND0_BAND31_DETECT_BAND_ID13_SHIFT 13
-#define BCHP_XPT_FE_MTSIF_RX3_PKT_BAND0_BAND31_DETECT_BAND_ID13_DEFAULT 0x00000000
-
-/* XPT_FE :: MTSIF_RX3_PKT_BAND0_BAND31_DETECT :: BAND_ID12 [12:12] */
-#define BCHP_XPT_FE_MTSIF_RX3_PKT_BAND0_BAND31_DETECT_BAND_ID12_MASK 0x00001000
-#define BCHP_XPT_FE_MTSIF_RX3_PKT_BAND0_BAND31_DETECT_BAND_ID12_SHIFT 12
-#define BCHP_XPT_FE_MTSIF_RX3_PKT_BAND0_BAND31_DETECT_BAND_ID12_DEFAULT 0x00000000
-
-/* XPT_FE :: MTSIF_RX3_PKT_BAND0_BAND31_DETECT :: BAND_ID11 [11:11] */
-#define BCHP_XPT_FE_MTSIF_RX3_PKT_BAND0_BAND31_DETECT_BAND_ID11_MASK 0x00000800
-#define BCHP_XPT_FE_MTSIF_RX3_PKT_BAND0_BAND31_DETECT_BAND_ID11_SHIFT 11
-#define BCHP_XPT_FE_MTSIF_RX3_PKT_BAND0_BAND31_DETECT_BAND_ID11_DEFAULT 0x00000000
-
-/* XPT_FE :: MTSIF_RX3_PKT_BAND0_BAND31_DETECT :: BAND_ID10 [10:10] */
-#define BCHP_XPT_FE_MTSIF_RX3_PKT_BAND0_BAND31_DETECT_BAND_ID10_MASK 0x00000400
-#define BCHP_XPT_FE_MTSIF_RX3_PKT_BAND0_BAND31_DETECT_BAND_ID10_SHIFT 10
-#define BCHP_XPT_FE_MTSIF_RX3_PKT_BAND0_BAND31_DETECT_BAND_ID10_DEFAULT 0x00000000
-
-/* XPT_FE :: MTSIF_RX3_PKT_BAND0_BAND31_DETECT :: BAND_ID9 [09:09] */
-#define BCHP_XPT_FE_MTSIF_RX3_PKT_BAND0_BAND31_DETECT_BAND_ID9_MASK 0x00000200
-#define BCHP_XPT_FE_MTSIF_RX3_PKT_BAND0_BAND31_DETECT_BAND_ID9_SHIFT 9
-#define BCHP_XPT_FE_MTSIF_RX3_PKT_BAND0_BAND31_DETECT_BAND_ID9_DEFAULT 0x00000000
-
-/* XPT_FE :: MTSIF_RX3_PKT_BAND0_BAND31_DETECT :: BAND_ID8 [08:08] */
-#define BCHP_XPT_FE_MTSIF_RX3_PKT_BAND0_BAND31_DETECT_BAND_ID8_MASK 0x00000100
-#define BCHP_XPT_FE_MTSIF_RX3_PKT_BAND0_BAND31_DETECT_BAND_ID8_SHIFT 8
-#define BCHP_XPT_FE_MTSIF_RX3_PKT_BAND0_BAND31_DETECT_BAND_ID8_DEFAULT 0x00000000
-
-/* XPT_FE :: MTSIF_RX3_PKT_BAND0_BAND31_DETECT :: BAND_ID7 [07:07] */
-#define BCHP_XPT_FE_MTSIF_RX3_PKT_BAND0_BAND31_DETECT_BAND_ID7_MASK 0x00000080
-#define BCHP_XPT_FE_MTSIF_RX3_PKT_BAND0_BAND31_DETECT_BAND_ID7_SHIFT 7
-#define BCHP_XPT_FE_MTSIF_RX3_PKT_BAND0_BAND31_DETECT_BAND_ID7_DEFAULT 0x00000000
-
-/* XPT_FE :: MTSIF_RX3_PKT_BAND0_BAND31_DETECT :: BAND_ID6 [06:06] */
-#define BCHP_XPT_FE_MTSIF_RX3_PKT_BAND0_BAND31_DETECT_BAND_ID6_MASK 0x00000040
-#define BCHP_XPT_FE_MTSIF_RX3_PKT_BAND0_BAND31_DETECT_BAND_ID6_SHIFT 6
-#define BCHP_XPT_FE_MTSIF_RX3_PKT_BAND0_BAND31_DETECT_BAND_ID6_DEFAULT 0x00000000
-
-/* XPT_FE :: MTSIF_RX3_PKT_BAND0_BAND31_DETECT :: BAND_ID5 [05:05] */
-#define BCHP_XPT_FE_MTSIF_RX3_PKT_BAND0_BAND31_DETECT_BAND_ID5_MASK 0x00000020
-#define BCHP_XPT_FE_MTSIF_RX3_PKT_BAND0_BAND31_DETECT_BAND_ID5_SHIFT 5
-#define BCHP_XPT_FE_MTSIF_RX3_PKT_BAND0_BAND31_DETECT_BAND_ID5_DEFAULT 0x00000000
-
-/* XPT_FE :: MTSIF_RX3_PKT_BAND0_BAND31_DETECT :: BAND_ID4 [04:04] */
-#define BCHP_XPT_FE_MTSIF_RX3_PKT_BAND0_BAND31_DETECT_BAND_ID4_MASK 0x00000010
-#define BCHP_XPT_FE_MTSIF_RX3_PKT_BAND0_BAND31_DETECT_BAND_ID4_SHIFT 4
-#define BCHP_XPT_FE_MTSIF_RX3_PKT_BAND0_BAND31_DETECT_BAND_ID4_DEFAULT 0x00000000
-
-/* XPT_FE :: MTSIF_RX3_PKT_BAND0_BAND31_DETECT :: BAND_ID3 [03:03] */
-#define BCHP_XPT_FE_MTSIF_RX3_PKT_BAND0_BAND31_DETECT_BAND_ID3_MASK 0x00000008
-#define BCHP_XPT_FE_MTSIF_RX3_PKT_BAND0_BAND31_DETECT_BAND_ID3_SHIFT 3
-#define BCHP_XPT_FE_MTSIF_RX3_PKT_BAND0_BAND31_DETECT_BAND_ID3_DEFAULT 0x00000000
-
-/* XPT_FE :: MTSIF_RX3_PKT_BAND0_BAND31_DETECT :: BAND_ID2 [02:02] */
-#define BCHP_XPT_FE_MTSIF_RX3_PKT_BAND0_BAND31_DETECT_BAND_ID2_MASK 0x00000004
-#define BCHP_XPT_FE_MTSIF_RX3_PKT_BAND0_BAND31_DETECT_BAND_ID2_SHIFT 2
-#define BCHP_XPT_FE_MTSIF_RX3_PKT_BAND0_BAND31_DETECT_BAND_ID2_DEFAULT 0x00000000
-
-/* XPT_FE :: MTSIF_RX3_PKT_BAND0_BAND31_DETECT :: BAND_ID1 [01:01] */
-#define BCHP_XPT_FE_MTSIF_RX3_PKT_BAND0_BAND31_DETECT_BAND_ID1_MASK 0x00000002
-#define BCHP_XPT_FE_MTSIF_RX3_PKT_BAND0_BAND31_DETECT_BAND_ID1_SHIFT 1
-#define BCHP_XPT_FE_MTSIF_RX3_PKT_BAND0_BAND31_DETECT_BAND_ID1_DEFAULT 0x00000000
-
-/* XPT_FE :: MTSIF_RX3_PKT_BAND0_BAND31_DETECT :: BAND_ID0 [00:00] */
-#define BCHP_XPT_FE_MTSIF_RX3_PKT_BAND0_BAND31_DETECT_BAND_ID0_MASK 0x00000001
-#define BCHP_XPT_FE_MTSIF_RX3_PKT_BAND0_BAND31_DETECT_BAND_ID0_SHIFT 0
-#define BCHP_XPT_FE_MTSIF_RX3_PKT_BAND0_BAND31_DETECT_BAND_ID0_DEFAULT 0x00000000
-
-/***************************************************************************
- *MINI_PID_PARSER0_TB_CTRL1 - Data Transport Parser Band 0 Transponder Bonding Control Register
- ***************************************************************************/
-/* XPT_FE :: MINI_PID_PARSER0_TB_CTRL1 :: reserved0 [31:28] */
-#define BCHP_XPT_FE_MINI_PID_PARSER0_TB_CTRL1_reserved0_MASK 0xf0000000
-#define BCHP_XPT_FE_MINI_PID_PARSER0_TB_CTRL1_reserved0_SHIFT 28
-
-/* XPT_FE :: MINI_PID_PARSER0_TB_CTRL1 :: TB_PARSER_PID_CH_NUM [27:16] */
-#define BCHP_XPT_FE_MINI_PID_PARSER0_TB_CTRL1_TB_PARSER_PID_CH_NUM_MASK 0x0fff0000
-#define BCHP_XPT_FE_MINI_PID_PARSER0_TB_CTRL1_TB_PARSER_PID_CH_NUM_SHIFT 16
-#define BCHP_XPT_FE_MINI_PID_PARSER0_TB_CTRL1_TB_PARSER_PID_CH_NUM_DEFAULT 0x00000000
-
-/* XPT_FE :: MINI_PID_PARSER0_TB_CTRL1 :: reserved1 [15:15] */
-#define BCHP_XPT_FE_MINI_PID_PARSER0_TB_CTRL1_reserved1_MASK 0x00008000
-#define BCHP_XPT_FE_MINI_PID_PARSER0_TB_CTRL1_reserved1_SHIFT 15
-
-/* XPT_FE :: MINI_PID_PARSER0_TB_CTRL1 :: TBG_PRI_BAND_NUM [14:08] */
-#define BCHP_XPT_FE_MINI_PID_PARSER0_TB_CTRL1_TBG_PRI_BAND_NUM_MASK 0x00007f00
-#define BCHP_XPT_FE_MINI_PID_PARSER0_TB_CTRL1_TBG_PRI_BAND_NUM_SHIFT 8
-#define BCHP_XPT_FE_MINI_PID_PARSER0_TB_CTRL1_TBG_PRI_BAND_NUM_DEFAULT 0x00000000
-
-/* XPT_FE :: MINI_PID_PARSER0_TB_CTRL1 :: reserved2 [07:04] */
-#define BCHP_XPT_FE_MINI_PID_PARSER0_TB_CTRL1_reserved2_MASK 0x000000f0
-#define BCHP_XPT_FE_MINI_PID_PARSER0_TB_CTRL1_reserved2_SHIFT 4
-
-/* XPT_FE :: MINI_PID_PARSER0_TB_CTRL1 :: TB_SKIP_ADAP_PRIVATE_DATA_PARSING [03:03] */
-#define BCHP_XPT_FE_MINI_PID_PARSER0_TB_CTRL1_TB_SKIP_ADAP_PRIVATE_DATA_PARSING_MASK 0x00000008
-#define BCHP_XPT_FE_MINI_PID_PARSER0_TB_CTRL1_TB_SKIP_ADAP_PRIVATE_DATA_PARSING_SHIFT 3
-#define BCHP_XPT_FE_MINI_PID_PARSER0_TB_CTRL1_TB_SKIP_ADAP_PRIVATE_DATA_PARSING_DEFAULT 0x00000000
-
-/* XPT_FE :: MINI_PID_PARSER0_TB_CTRL1 :: TB_IGNORE_TS_PRIORITY [02:02] */
-#define BCHP_XPT_FE_MINI_PID_PARSER0_TB_CTRL1_TB_IGNORE_TS_PRIORITY_MASK 0x00000004
-#define BCHP_XPT_FE_MINI_PID_PARSER0_TB_CTRL1_TB_IGNORE_TS_PRIORITY_SHIFT 2
-#define BCHP_XPT_FE_MINI_PID_PARSER0_TB_CTRL1_TB_IGNORE_TS_PRIORITY_DEFAULT 0x00000000
-
-/* XPT_FE :: MINI_PID_PARSER0_TB_CTRL1 :: TB_DROP_BEF_FIRST_MARKER_PKT [01:01] */
-#define BCHP_XPT_FE_MINI_PID_PARSER0_TB_CTRL1_TB_DROP_BEF_FIRST_MARKER_PKT_MASK 0x00000002
-#define BCHP_XPT_FE_MINI_PID_PARSER0_TB_CTRL1_TB_DROP_BEF_FIRST_MARKER_PKT_SHIFT 1
-#define BCHP_XPT_FE_MINI_PID_PARSER0_TB_CTRL1_TB_DROP_BEF_FIRST_MARKER_PKT_DEFAULT 0x00000000
-
-/* XPT_FE :: MINI_PID_PARSER0_TB_CTRL1 :: TB_ENABLE [00:00] */
-#define BCHP_XPT_FE_MINI_PID_PARSER0_TB_CTRL1_TB_ENABLE_MASK 0x00000001
-#define BCHP_XPT_FE_MINI_PID_PARSER0_TB_CTRL1_TB_ENABLE_SHIFT 0
-#define BCHP_XPT_FE_MINI_PID_PARSER0_TB_CTRL1_TB_ENABLE_DEFAULT 0x00000000
-
-/***************************************************************************
- *MINI_PID_PARSER0_SYNC_COUNT - Data Transport Parser Band 0 Transponder Bonding Sync Counter Register
- ***************************************************************************/
-/* XPT_FE :: MINI_PID_PARSER0_SYNC_COUNT :: reserved0 [31:10] */
-#define BCHP_XPT_FE_MINI_PID_PARSER0_SYNC_COUNT_reserved0_MASK 0xfffffc00
-#define BCHP_XPT_FE_MINI_PID_PARSER0_SYNC_COUNT_reserved0_SHIFT 10
-
-/* XPT_FE :: MINI_PID_PARSER0_SYNC_COUNT :: SYNC_COUNT [09:00] */
-#define BCHP_XPT_FE_MINI_PID_PARSER0_SYNC_COUNT_SYNC_COUNT_MASK 0x000003ff
-#define BCHP_XPT_FE_MINI_PID_PARSER0_SYNC_COUNT_SYNC_COUNT_SHIFT 0
-#define BCHP_XPT_FE_MINI_PID_PARSER0_SYNC_COUNT_SYNC_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *MINI_PID_PARSER1_TB_CTRL1 - Data Transport Parser Band 1 Transponder Bonding Control Register
- ***************************************************************************/
-/* XPT_FE :: MINI_PID_PARSER1_TB_CTRL1 :: reserved0 [31:28] */
-#define BCHP_XPT_FE_MINI_PID_PARSER1_TB_CTRL1_reserved0_MASK 0xf0000000
-#define BCHP_XPT_FE_MINI_PID_PARSER1_TB_CTRL1_reserved0_SHIFT 28
-
-/* XPT_FE :: MINI_PID_PARSER1_TB_CTRL1 :: TB_PARSER_PID_CH_NUM [27:16] */
-#define BCHP_XPT_FE_MINI_PID_PARSER1_TB_CTRL1_TB_PARSER_PID_CH_NUM_MASK 0x0fff0000
-#define BCHP_XPT_FE_MINI_PID_PARSER1_TB_CTRL1_TB_PARSER_PID_CH_NUM_SHIFT 16
-#define BCHP_XPT_FE_MINI_PID_PARSER1_TB_CTRL1_TB_PARSER_PID_CH_NUM_DEFAULT 0x00000000
-
-/* XPT_FE :: MINI_PID_PARSER1_TB_CTRL1 :: reserved1 [15:15] */
-#define BCHP_XPT_FE_MINI_PID_PARSER1_TB_CTRL1_reserved1_MASK 0x00008000
-#define BCHP_XPT_FE_MINI_PID_PARSER1_TB_CTRL1_reserved1_SHIFT 15
-
-/* XPT_FE :: MINI_PID_PARSER1_TB_CTRL1 :: TBG_PRI_BAND_NUM [14:08] */
-#define BCHP_XPT_FE_MINI_PID_PARSER1_TB_CTRL1_TBG_PRI_BAND_NUM_MASK 0x00007f00
-#define BCHP_XPT_FE_MINI_PID_PARSER1_TB_CTRL1_TBG_PRI_BAND_NUM_SHIFT 8
-#define BCHP_XPT_FE_MINI_PID_PARSER1_TB_CTRL1_TBG_PRI_BAND_NUM_DEFAULT 0x00000000
-
-/* XPT_FE :: MINI_PID_PARSER1_TB_CTRL1 :: reserved2 [07:04] */
-#define BCHP_XPT_FE_MINI_PID_PARSER1_TB_CTRL1_reserved2_MASK 0x000000f0
-#define BCHP_XPT_FE_MINI_PID_PARSER1_TB_CTRL1_reserved2_SHIFT 4
-
-/* XPT_FE :: MINI_PID_PARSER1_TB_CTRL1 :: TB_SKIP_ADAP_PRIVATE_DATA_PARSING [03:03] */
-#define BCHP_XPT_FE_MINI_PID_PARSER1_TB_CTRL1_TB_SKIP_ADAP_PRIVATE_DATA_PARSING_MASK 0x00000008
-#define BCHP_XPT_FE_MINI_PID_PARSER1_TB_CTRL1_TB_SKIP_ADAP_PRIVATE_DATA_PARSING_SHIFT 3
-#define BCHP_XPT_FE_MINI_PID_PARSER1_TB_CTRL1_TB_SKIP_ADAP_PRIVATE_DATA_PARSING_DEFAULT 0x00000000
-
-/* XPT_FE :: MINI_PID_PARSER1_TB_CTRL1 :: TB_IGNORE_TS_PRIORITY [02:02] */
-#define BCHP_XPT_FE_MINI_PID_PARSER1_TB_CTRL1_TB_IGNORE_TS_PRIORITY_MASK 0x00000004
-#define BCHP_XPT_FE_MINI_PID_PARSER1_TB_CTRL1_TB_IGNORE_TS_PRIORITY_SHIFT 2
-#define BCHP_XPT_FE_MINI_PID_PARSER1_TB_CTRL1_TB_IGNORE_TS_PRIORITY_DEFAULT 0x00000000
-
-/* XPT_FE :: MINI_PID_PARSER1_TB_CTRL1 :: TB_DROP_BEF_FIRST_MARKER_PKT [01:01] */
-#define BCHP_XPT_FE_MINI_PID_PARSER1_TB_CTRL1_TB_DROP_BEF_FIRST_MARKER_PKT_MASK 0x00000002
-#define BCHP_XPT_FE_MINI_PID_PARSER1_TB_CTRL1_TB_DROP_BEF_FIRST_MARKER_PKT_SHIFT 1
-#define BCHP_XPT_FE_MINI_PID_PARSER1_TB_CTRL1_TB_DROP_BEF_FIRST_MARKER_PKT_DEFAULT 0x00000000
-
-/* XPT_FE :: MINI_PID_PARSER1_TB_CTRL1 :: TB_ENABLE [00:00] */
-#define BCHP_XPT_FE_MINI_PID_PARSER1_TB_CTRL1_TB_ENABLE_MASK 0x00000001
-#define BCHP_XPT_FE_MINI_PID_PARSER1_TB_CTRL1_TB_ENABLE_SHIFT 0
-#define BCHP_XPT_FE_MINI_PID_PARSER1_TB_CTRL1_TB_ENABLE_DEFAULT 0x00000000
-
-/***************************************************************************
- *MINI_PID_PARSER1_SYNC_COUNT - Data Transport Parser Band 1 Transponder Bonding Sync Counter Register
- ***************************************************************************/
-/* XPT_FE :: MINI_PID_PARSER1_SYNC_COUNT :: reserved0 [31:10] */
-#define BCHP_XPT_FE_MINI_PID_PARSER1_SYNC_COUNT_reserved0_MASK 0xfffffc00
-#define BCHP_XPT_FE_MINI_PID_PARSER1_SYNC_COUNT_reserved0_SHIFT 10
-
-/* XPT_FE :: MINI_PID_PARSER1_SYNC_COUNT :: SYNC_COUNT [09:00] */
-#define BCHP_XPT_FE_MINI_PID_PARSER1_SYNC_COUNT_SYNC_COUNT_MASK 0x000003ff
-#define BCHP_XPT_FE_MINI_PID_PARSER1_SYNC_COUNT_SYNC_COUNT_SHIFT 0
-#define BCHP_XPT_FE_MINI_PID_PARSER1_SYNC_COUNT_SYNC_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *MINI_PID_PARSER2_TB_CTRL1 - Data Transport Parser Band 2 Transponder Bonding Control Register
- ***************************************************************************/
-/* XPT_FE :: MINI_PID_PARSER2_TB_CTRL1 :: reserved0 [31:28] */
-#define BCHP_XPT_FE_MINI_PID_PARSER2_TB_CTRL1_reserved0_MASK 0xf0000000
-#define BCHP_XPT_FE_MINI_PID_PARSER2_TB_CTRL1_reserved0_SHIFT 28
-
-/* XPT_FE :: MINI_PID_PARSER2_TB_CTRL1 :: TB_PARSER_PID_CH_NUM [27:16] */
-#define BCHP_XPT_FE_MINI_PID_PARSER2_TB_CTRL1_TB_PARSER_PID_CH_NUM_MASK 0x0fff0000
-#define BCHP_XPT_FE_MINI_PID_PARSER2_TB_CTRL1_TB_PARSER_PID_CH_NUM_SHIFT 16
-#define BCHP_XPT_FE_MINI_PID_PARSER2_TB_CTRL1_TB_PARSER_PID_CH_NUM_DEFAULT 0x00000000
-
-/* XPT_FE :: MINI_PID_PARSER2_TB_CTRL1 :: reserved1 [15:15] */
-#define BCHP_XPT_FE_MINI_PID_PARSER2_TB_CTRL1_reserved1_MASK 0x00008000
-#define BCHP_XPT_FE_MINI_PID_PARSER2_TB_CTRL1_reserved1_SHIFT 15
-
-/* XPT_FE :: MINI_PID_PARSER2_TB_CTRL1 :: TBG_PRI_BAND_NUM [14:08] */
-#define BCHP_XPT_FE_MINI_PID_PARSER2_TB_CTRL1_TBG_PRI_BAND_NUM_MASK 0x00007f00
-#define BCHP_XPT_FE_MINI_PID_PARSER2_TB_CTRL1_TBG_PRI_BAND_NUM_SHIFT 8
-#define BCHP_XPT_FE_MINI_PID_PARSER2_TB_CTRL1_TBG_PRI_BAND_NUM_DEFAULT 0x00000000
-
-/* XPT_FE :: MINI_PID_PARSER2_TB_CTRL1 :: reserved2 [07:04] */
-#define BCHP_XPT_FE_MINI_PID_PARSER2_TB_CTRL1_reserved2_MASK 0x000000f0
-#define BCHP_XPT_FE_MINI_PID_PARSER2_TB_CTRL1_reserved2_SHIFT 4
-
-/* XPT_FE :: MINI_PID_PARSER2_TB_CTRL1 :: TB_SKIP_ADAP_PRIVATE_DATA_PARSING [03:03] */
-#define BCHP_XPT_FE_MINI_PID_PARSER2_TB_CTRL1_TB_SKIP_ADAP_PRIVATE_DATA_PARSING_MASK 0x00000008
-#define BCHP_XPT_FE_MINI_PID_PARSER2_TB_CTRL1_TB_SKIP_ADAP_PRIVATE_DATA_PARSING_SHIFT 3
-#define BCHP_XPT_FE_MINI_PID_PARSER2_TB_CTRL1_TB_SKIP_ADAP_PRIVATE_DATA_PARSING_DEFAULT 0x00000000
-
-/* XPT_FE :: MINI_PID_PARSER2_TB_CTRL1 :: TB_IGNORE_TS_PRIORITY [02:02] */
-#define BCHP_XPT_FE_MINI_PID_PARSER2_TB_CTRL1_TB_IGNORE_TS_PRIORITY_MASK 0x00000004
-#define BCHP_XPT_FE_MINI_PID_PARSER2_TB_CTRL1_TB_IGNORE_TS_PRIORITY_SHIFT 2
-#define BCHP_XPT_FE_MINI_PID_PARSER2_TB_CTRL1_TB_IGNORE_TS_PRIORITY_DEFAULT 0x00000000
-
-/* XPT_FE :: MINI_PID_PARSER2_TB_CTRL1 :: TB_DROP_BEF_FIRST_MARKER_PKT [01:01] */
-#define BCHP_XPT_FE_MINI_PID_PARSER2_TB_CTRL1_TB_DROP_BEF_FIRST_MARKER_PKT_MASK 0x00000002
-#define BCHP_XPT_FE_MINI_PID_PARSER2_TB_CTRL1_TB_DROP_BEF_FIRST_MARKER_PKT_SHIFT 1
-#define BCHP_XPT_FE_MINI_PID_PARSER2_TB_CTRL1_TB_DROP_BEF_FIRST_MARKER_PKT_DEFAULT 0x00000000
-
-/* XPT_FE :: MINI_PID_PARSER2_TB_CTRL1 :: TB_ENABLE [00:00] */
-#define BCHP_XPT_FE_MINI_PID_PARSER2_TB_CTRL1_TB_ENABLE_MASK 0x00000001
-#define BCHP_XPT_FE_MINI_PID_PARSER2_TB_CTRL1_TB_ENABLE_SHIFT 0
-#define BCHP_XPT_FE_MINI_PID_PARSER2_TB_CTRL1_TB_ENABLE_DEFAULT 0x00000000
-
-/***************************************************************************
- *MINI_PID_PARSER2_SYNC_COUNT - Data Transport Parser Band 2 Transponder Bonding Sync Counter Register
- ***************************************************************************/
-/* XPT_FE :: MINI_PID_PARSER2_SYNC_COUNT :: reserved0 [31:10] */
-#define BCHP_XPT_FE_MINI_PID_PARSER2_SYNC_COUNT_reserved0_MASK 0xfffffc00
-#define BCHP_XPT_FE_MINI_PID_PARSER2_SYNC_COUNT_reserved0_SHIFT 10
-
-/* XPT_FE :: MINI_PID_PARSER2_SYNC_COUNT :: SYNC_COUNT [09:00] */
-#define BCHP_XPT_FE_MINI_PID_PARSER2_SYNC_COUNT_SYNC_COUNT_MASK 0x000003ff
-#define BCHP_XPT_FE_MINI_PID_PARSER2_SYNC_COUNT_SYNC_COUNT_SHIFT 0
-#define BCHP_XPT_FE_MINI_PID_PARSER2_SYNC_COUNT_SYNC_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *MINI_PID_PARSER3_TB_CTRL1 - Data Transport Parser Band 3 Transponder Bonding Control Register
- ***************************************************************************/
-/* XPT_FE :: MINI_PID_PARSER3_TB_CTRL1 :: reserved0 [31:28] */
-#define BCHP_XPT_FE_MINI_PID_PARSER3_TB_CTRL1_reserved0_MASK 0xf0000000
-#define BCHP_XPT_FE_MINI_PID_PARSER3_TB_CTRL1_reserved0_SHIFT 28
-
-/* XPT_FE :: MINI_PID_PARSER3_TB_CTRL1 :: TB_PARSER_PID_CH_NUM [27:16] */
-#define BCHP_XPT_FE_MINI_PID_PARSER3_TB_CTRL1_TB_PARSER_PID_CH_NUM_MASK 0x0fff0000
-#define BCHP_XPT_FE_MINI_PID_PARSER3_TB_CTRL1_TB_PARSER_PID_CH_NUM_SHIFT 16
-#define BCHP_XPT_FE_MINI_PID_PARSER3_TB_CTRL1_TB_PARSER_PID_CH_NUM_DEFAULT 0x00000000
-
-/* XPT_FE :: MINI_PID_PARSER3_TB_CTRL1 :: reserved1 [15:15] */
-#define BCHP_XPT_FE_MINI_PID_PARSER3_TB_CTRL1_reserved1_MASK 0x00008000
-#define BCHP_XPT_FE_MINI_PID_PARSER3_TB_CTRL1_reserved1_SHIFT 15
-
-/* XPT_FE :: MINI_PID_PARSER3_TB_CTRL1 :: TBG_PRI_BAND_NUM [14:08] */
-#define BCHP_XPT_FE_MINI_PID_PARSER3_TB_CTRL1_TBG_PRI_BAND_NUM_MASK 0x00007f00
-#define BCHP_XPT_FE_MINI_PID_PARSER3_TB_CTRL1_TBG_PRI_BAND_NUM_SHIFT 8
-#define BCHP_XPT_FE_MINI_PID_PARSER3_TB_CTRL1_TBG_PRI_BAND_NUM_DEFAULT 0x00000000
-
-/* XPT_FE :: MINI_PID_PARSER3_TB_CTRL1 :: reserved2 [07:04] */
-#define BCHP_XPT_FE_MINI_PID_PARSER3_TB_CTRL1_reserved2_MASK 0x000000f0
-#define BCHP_XPT_FE_MINI_PID_PARSER3_TB_CTRL1_reserved2_SHIFT 4
-
-/* XPT_FE :: MINI_PID_PARSER3_TB_CTRL1 :: TB_SKIP_ADAP_PRIVATE_DATA_PARSING [03:03] */
-#define BCHP_XPT_FE_MINI_PID_PARSER3_TB_CTRL1_TB_SKIP_ADAP_PRIVATE_DATA_PARSING_MASK 0x00000008
-#define BCHP_XPT_FE_MINI_PID_PARSER3_TB_CTRL1_TB_SKIP_ADAP_PRIVATE_DATA_PARSING_SHIFT 3
-#define BCHP_XPT_FE_MINI_PID_PARSER3_TB_CTRL1_TB_SKIP_ADAP_PRIVATE_DATA_PARSING_DEFAULT 0x00000000
-
-/* XPT_FE :: MINI_PID_PARSER3_TB_CTRL1 :: TB_IGNORE_TS_PRIORITY [02:02] */
-#define BCHP_XPT_FE_MINI_PID_PARSER3_TB_CTRL1_TB_IGNORE_TS_PRIORITY_MASK 0x00000004
-#define BCHP_XPT_FE_MINI_PID_PARSER3_TB_CTRL1_TB_IGNORE_TS_PRIORITY_SHIFT 2
-#define BCHP_XPT_FE_MINI_PID_PARSER3_TB_CTRL1_TB_IGNORE_TS_PRIORITY_DEFAULT 0x00000000
-
-/* XPT_FE :: MINI_PID_PARSER3_TB_CTRL1 :: TB_DROP_BEF_FIRST_MARKER_PKT [01:01] */
-#define BCHP_XPT_FE_MINI_PID_PARSER3_TB_CTRL1_TB_DROP_BEF_FIRST_MARKER_PKT_MASK 0x00000002
-#define BCHP_XPT_FE_MINI_PID_PARSER3_TB_CTRL1_TB_DROP_BEF_FIRST_MARKER_PKT_SHIFT 1
-#define BCHP_XPT_FE_MINI_PID_PARSER3_TB_CTRL1_TB_DROP_BEF_FIRST_MARKER_PKT_DEFAULT 0x00000000
-
-/* XPT_FE :: MINI_PID_PARSER3_TB_CTRL1 :: TB_ENABLE [00:00] */
-#define BCHP_XPT_FE_MINI_PID_PARSER3_TB_CTRL1_TB_ENABLE_MASK 0x00000001
-#define BCHP_XPT_FE_MINI_PID_PARSER3_TB_CTRL1_TB_ENABLE_SHIFT 0
-#define BCHP_XPT_FE_MINI_PID_PARSER3_TB_CTRL1_TB_ENABLE_DEFAULT 0x00000000
-
-/***************************************************************************
- *MINI_PID_PARSER3_SYNC_COUNT - Data Transport Parser Band 3 Transponder Bonding Sync Counter Register
- ***************************************************************************/
-/* XPT_FE :: MINI_PID_PARSER3_SYNC_COUNT :: reserved0 [31:10] */
-#define BCHP_XPT_FE_MINI_PID_PARSER3_SYNC_COUNT_reserved0_MASK 0xfffffc00
-#define BCHP_XPT_FE_MINI_PID_PARSER3_SYNC_COUNT_reserved0_SHIFT 10
-
-/* XPT_FE :: MINI_PID_PARSER3_SYNC_COUNT :: SYNC_COUNT [09:00] */
-#define BCHP_XPT_FE_MINI_PID_PARSER3_SYNC_COUNT_SYNC_COUNT_MASK 0x000003ff
-#define BCHP_XPT_FE_MINI_PID_PARSER3_SYNC_COUNT_SYNC_COUNT_SHIFT 0
-#define BCHP_XPT_FE_MINI_PID_PARSER3_SYNC_COUNT_SYNC_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *MINI_PID_PARSER4_TB_CTRL1 - Data Transport Parser Band 4 Transponder Bonding Control Register
- ***************************************************************************/
-/* XPT_FE :: MINI_PID_PARSER4_TB_CTRL1 :: reserved0 [31:28] */
-#define BCHP_XPT_FE_MINI_PID_PARSER4_TB_CTRL1_reserved0_MASK 0xf0000000
-#define BCHP_XPT_FE_MINI_PID_PARSER4_TB_CTRL1_reserved0_SHIFT 28
-
-/* XPT_FE :: MINI_PID_PARSER4_TB_CTRL1 :: TB_PARSER_PID_CH_NUM [27:16] */
-#define BCHP_XPT_FE_MINI_PID_PARSER4_TB_CTRL1_TB_PARSER_PID_CH_NUM_MASK 0x0fff0000
-#define BCHP_XPT_FE_MINI_PID_PARSER4_TB_CTRL1_TB_PARSER_PID_CH_NUM_SHIFT 16
-#define BCHP_XPT_FE_MINI_PID_PARSER4_TB_CTRL1_TB_PARSER_PID_CH_NUM_DEFAULT 0x00000000
-
-/* XPT_FE :: MINI_PID_PARSER4_TB_CTRL1 :: reserved1 [15:15] */
-#define BCHP_XPT_FE_MINI_PID_PARSER4_TB_CTRL1_reserved1_MASK 0x00008000
-#define BCHP_XPT_FE_MINI_PID_PARSER4_TB_CTRL1_reserved1_SHIFT 15
-
-/* XPT_FE :: MINI_PID_PARSER4_TB_CTRL1 :: TBG_PRI_BAND_NUM [14:08] */
-#define BCHP_XPT_FE_MINI_PID_PARSER4_TB_CTRL1_TBG_PRI_BAND_NUM_MASK 0x00007f00
-#define BCHP_XPT_FE_MINI_PID_PARSER4_TB_CTRL1_TBG_PRI_BAND_NUM_SHIFT 8
-#define BCHP_XPT_FE_MINI_PID_PARSER4_TB_CTRL1_TBG_PRI_BAND_NUM_DEFAULT 0x00000000
-
-/* XPT_FE :: MINI_PID_PARSER4_TB_CTRL1 :: reserved2 [07:04] */
-#define BCHP_XPT_FE_MINI_PID_PARSER4_TB_CTRL1_reserved2_MASK 0x000000f0
-#define BCHP_XPT_FE_MINI_PID_PARSER4_TB_CTRL1_reserved2_SHIFT 4
-
-/* XPT_FE :: MINI_PID_PARSER4_TB_CTRL1 :: TB_SKIP_ADAP_PRIVATE_DATA_PARSING [03:03] */
-#define BCHP_XPT_FE_MINI_PID_PARSER4_TB_CTRL1_TB_SKIP_ADAP_PRIVATE_DATA_PARSING_MASK 0x00000008
-#define BCHP_XPT_FE_MINI_PID_PARSER4_TB_CTRL1_TB_SKIP_ADAP_PRIVATE_DATA_PARSING_SHIFT 3
-#define BCHP_XPT_FE_MINI_PID_PARSER4_TB_CTRL1_TB_SKIP_ADAP_PRIVATE_DATA_PARSING_DEFAULT 0x00000000
-
-/* XPT_FE :: MINI_PID_PARSER4_TB_CTRL1 :: TB_IGNORE_TS_PRIORITY [02:02] */
-#define BCHP_XPT_FE_MINI_PID_PARSER4_TB_CTRL1_TB_IGNORE_TS_PRIORITY_MASK 0x00000004
-#define BCHP_XPT_FE_MINI_PID_PARSER4_TB_CTRL1_TB_IGNORE_TS_PRIORITY_SHIFT 2
-#define BCHP_XPT_FE_MINI_PID_PARSER4_TB_CTRL1_TB_IGNORE_TS_PRIORITY_DEFAULT 0x00000000
-
-/* XPT_FE :: MINI_PID_PARSER4_TB_CTRL1 :: TB_DROP_BEF_FIRST_MARKER_PKT [01:01] */
-#define BCHP_XPT_FE_MINI_PID_PARSER4_TB_CTRL1_TB_DROP_BEF_FIRST_MARKER_PKT_MASK 0x00000002
-#define BCHP_XPT_FE_MINI_PID_PARSER4_TB_CTRL1_TB_DROP_BEF_FIRST_MARKER_PKT_SHIFT 1
-#define BCHP_XPT_FE_MINI_PID_PARSER4_TB_CTRL1_TB_DROP_BEF_FIRST_MARKER_PKT_DEFAULT 0x00000000
-
-/* XPT_FE :: MINI_PID_PARSER4_TB_CTRL1 :: TB_ENABLE [00:00] */
-#define BCHP_XPT_FE_MINI_PID_PARSER4_TB_CTRL1_TB_ENABLE_MASK 0x00000001
-#define BCHP_XPT_FE_MINI_PID_PARSER4_TB_CTRL1_TB_ENABLE_SHIFT 0
-#define BCHP_XPT_FE_MINI_PID_PARSER4_TB_CTRL1_TB_ENABLE_DEFAULT 0x00000000
-
-/***************************************************************************
- *MINI_PID_PARSER4_SYNC_COUNT - Data Transport Parser Band 4 Transponder Bonding Sync Counter Register
- ***************************************************************************/
-/* XPT_FE :: MINI_PID_PARSER4_SYNC_COUNT :: reserved0 [31:10] */
-#define BCHP_XPT_FE_MINI_PID_PARSER4_SYNC_COUNT_reserved0_MASK 0xfffffc00
-#define BCHP_XPT_FE_MINI_PID_PARSER4_SYNC_COUNT_reserved0_SHIFT 10
-
-/* XPT_FE :: MINI_PID_PARSER4_SYNC_COUNT :: SYNC_COUNT [09:00] */
-#define BCHP_XPT_FE_MINI_PID_PARSER4_SYNC_COUNT_SYNC_COUNT_MASK 0x000003ff
-#define BCHP_XPT_FE_MINI_PID_PARSER4_SYNC_COUNT_SYNC_COUNT_SHIFT 0
-#define BCHP_XPT_FE_MINI_PID_PARSER4_SYNC_COUNT_SYNC_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *MINI_PID_PARSER5_TB_CTRL1 - Data Transport Parser Band 5 Transponder Bonding Control Register
- ***************************************************************************/
-/* XPT_FE :: MINI_PID_PARSER5_TB_CTRL1 :: reserved0 [31:28] */
-#define BCHP_XPT_FE_MINI_PID_PARSER5_TB_CTRL1_reserved0_MASK 0xf0000000
-#define BCHP_XPT_FE_MINI_PID_PARSER5_TB_CTRL1_reserved0_SHIFT 28
-
-/* XPT_FE :: MINI_PID_PARSER5_TB_CTRL1 :: TB_PARSER_PID_CH_NUM [27:16] */
-#define BCHP_XPT_FE_MINI_PID_PARSER5_TB_CTRL1_TB_PARSER_PID_CH_NUM_MASK 0x0fff0000
-#define BCHP_XPT_FE_MINI_PID_PARSER5_TB_CTRL1_TB_PARSER_PID_CH_NUM_SHIFT 16
-#define BCHP_XPT_FE_MINI_PID_PARSER5_TB_CTRL1_TB_PARSER_PID_CH_NUM_DEFAULT 0x00000000
-
-/* XPT_FE :: MINI_PID_PARSER5_TB_CTRL1 :: reserved1 [15:15] */
-#define BCHP_XPT_FE_MINI_PID_PARSER5_TB_CTRL1_reserved1_MASK 0x00008000
-#define BCHP_XPT_FE_MINI_PID_PARSER5_TB_CTRL1_reserved1_SHIFT 15
-
-/* XPT_FE :: MINI_PID_PARSER5_TB_CTRL1 :: TBG_PRI_BAND_NUM [14:08] */
-#define BCHP_XPT_FE_MINI_PID_PARSER5_TB_CTRL1_TBG_PRI_BAND_NUM_MASK 0x00007f00
-#define BCHP_XPT_FE_MINI_PID_PARSER5_TB_CTRL1_TBG_PRI_BAND_NUM_SHIFT 8
-#define BCHP_XPT_FE_MINI_PID_PARSER5_TB_CTRL1_TBG_PRI_BAND_NUM_DEFAULT 0x00000000
-
-/* XPT_FE :: MINI_PID_PARSER5_TB_CTRL1 :: reserved2 [07:04] */
-#define BCHP_XPT_FE_MINI_PID_PARSER5_TB_CTRL1_reserved2_MASK 0x000000f0
-#define BCHP_XPT_FE_MINI_PID_PARSER5_TB_CTRL1_reserved2_SHIFT 4
-
-/* XPT_FE :: MINI_PID_PARSER5_TB_CTRL1 :: TB_SKIP_ADAP_PRIVATE_DATA_PARSING [03:03] */
-#define BCHP_XPT_FE_MINI_PID_PARSER5_TB_CTRL1_TB_SKIP_ADAP_PRIVATE_DATA_PARSING_MASK 0x00000008
-#define BCHP_XPT_FE_MINI_PID_PARSER5_TB_CTRL1_TB_SKIP_ADAP_PRIVATE_DATA_PARSING_SHIFT 3
-#define BCHP_XPT_FE_MINI_PID_PARSER5_TB_CTRL1_TB_SKIP_ADAP_PRIVATE_DATA_PARSING_DEFAULT 0x00000000
-
-/* XPT_FE :: MINI_PID_PARSER5_TB_CTRL1 :: TB_IGNORE_TS_PRIORITY [02:02] */
-#define BCHP_XPT_FE_MINI_PID_PARSER5_TB_CTRL1_TB_IGNORE_TS_PRIORITY_MASK 0x00000004
-#define BCHP_XPT_FE_MINI_PID_PARSER5_TB_CTRL1_TB_IGNORE_TS_PRIORITY_SHIFT 2
-#define BCHP_XPT_FE_MINI_PID_PARSER5_TB_CTRL1_TB_IGNORE_TS_PRIORITY_DEFAULT 0x00000000
-
-/* XPT_FE :: MINI_PID_PARSER5_TB_CTRL1 :: TB_DROP_BEF_FIRST_MARKER_PKT [01:01] */
-#define BCHP_XPT_FE_MINI_PID_PARSER5_TB_CTRL1_TB_DROP_BEF_FIRST_MARKER_PKT_MASK 0x00000002
-#define BCHP_XPT_FE_MINI_PID_PARSER5_TB_CTRL1_TB_DROP_BEF_FIRST_MARKER_PKT_SHIFT 1
-#define BCHP_XPT_FE_MINI_PID_PARSER5_TB_CTRL1_TB_DROP_BEF_FIRST_MARKER_PKT_DEFAULT 0x00000000
-
-/* XPT_FE :: MINI_PID_PARSER5_TB_CTRL1 :: TB_ENABLE [00:00] */
-#define BCHP_XPT_FE_MINI_PID_PARSER5_TB_CTRL1_TB_ENABLE_MASK 0x00000001
-#define BCHP_XPT_FE_MINI_PID_PARSER5_TB_CTRL1_TB_ENABLE_SHIFT 0
-#define BCHP_XPT_FE_MINI_PID_PARSER5_TB_CTRL1_TB_ENABLE_DEFAULT 0x00000000
-
-/***************************************************************************
- *MINI_PID_PARSER5_SYNC_COUNT - Data Transport Parser Band 5 Transponder Bonding Sync Counter Register
- ***************************************************************************/
-/* XPT_FE :: MINI_PID_PARSER5_SYNC_COUNT :: reserved0 [31:10] */
-#define BCHP_XPT_FE_MINI_PID_PARSER5_SYNC_COUNT_reserved0_MASK 0xfffffc00
-#define BCHP_XPT_FE_MINI_PID_PARSER5_SYNC_COUNT_reserved0_SHIFT 10
-
-/* XPT_FE :: MINI_PID_PARSER5_SYNC_COUNT :: SYNC_COUNT [09:00] */
-#define BCHP_XPT_FE_MINI_PID_PARSER5_SYNC_COUNT_SYNC_COUNT_MASK 0x000003ff
-#define BCHP_XPT_FE_MINI_PID_PARSER5_SYNC_COUNT_SYNC_COUNT_SHIFT 0
-#define BCHP_XPT_FE_MINI_PID_PARSER5_SYNC_COUNT_SYNC_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *MINI_PID_PARSER6_TB_CTRL1 - Data Transport Parser Band 6 Transponder Bonding Control Register
- ***************************************************************************/
-/* XPT_FE :: MINI_PID_PARSER6_TB_CTRL1 :: reserved0 [31:28] */
-#define BCHP_XPT_FE_MINI_PID_PARSER6_TB_CTRL1_reserved0_MASK 0xf0000000
-#define BCHP_XPT_FE_MINI_PID_PARSER6_TB_CTRL1_reserved0_SHIFT 28
-
-/* XPT_FE :: MINI_PID_PARSER6_TB_CTRL1 :: TB_PARSER_PID_CH_NUM [27:16] */
-#define BCHP_XPT_FE_MINI_PID_PARSER6_TB_CTRL1_TB_PARSER_PID_CH_NUM_MASK 0x0fff0000
-#define BCHP_XPT_FE_MINI_PID_PARSER6_TB_CTRL1_TB_PARSER_PID_CH_NUM_SHIFT 16
-#define BCHP_XPT_FE_MINI_PID_PARSER6_TB_CTRL1_TB_PARSER_PID_CH_NUM_DEFAULT 0x00000000
-
-/* XPT_FE :: MINI_PID_PARSER6_TB_CTRL1 :: reserved1 [15:15] */
-#define BCHP_XPT_FE_MINI_PID_PARSER6_TB_CTRL1_reserved1_MASK 0x00008000
-#define BCHP_XPT_FE_MINI_PID_PARSER6_TB_CTRL1_reserved1_SHIFT 15
-
-/* XPT_FE :: MINI_PID_PARSER6_TB_CTRL1 :: TBG_PRI_BAND_NUM [14:08] */
-#define BCHP_XPT_FE_MINI_PID_PARSER6_TB_CTRL1_TBG_PRI_BAND_NUM_MASK 0x00007f00
-#define BCHP_XPT_FE_MINI_PID_PARSER6_TB_CTRL1_TBG_PRI_BAND_NUM_SHIFT 8
-#define BCHP_XPT_FE_MINI_PID_PARSER6_TB_CTRL1_TBG_PRI_BAND_NUM_DEFAULT 0x00000000
-
-/* XPT_FE :: MINI_PID_PARSER6_TB_CTRL1 :: reserved2 [07:04] */
-#define BCHP_XPT_FE_MINI_PID_PARSER6_TB_CTRL1_reserved2_MASK 0x000000f0
-#define BCHP_XPT_FE_MINI_PID_PARSER6_TB_CTRL1_reserved2_SHIFT 4
-
-/* XPT_FE :: MINI_PID_PARSER6_TB_CTRL1 :: TB_SKIP_ADAP_PRIVATE_DATA_PARSING [03:03] */
-#define BCHP_XPT_FE_MINI_PID_PARSER6_TB_CTRL1_TB_SKIP_ADAP_PRIVATE_DATA_PARSING_MASK 0x00000008
-#define BCHP_XPT_FE_MINI_PID_PARSER6_TB_CTRL1_TB_SKIP_ADAP_PRIVATE_DATA_PARSING_SHIFT 3
-#define BCHP_XPT_FE_MINI_PID_PARSER6_TB_CTRL1_TB_SKIP_ADAP_PRIVATE_DATA_PARSING_DEFAULT 0x00000000
-
-/* XPT_FE :: MINI_PID_PARSER6_TB_CTRL1 :: TB_IGNORE_TS_PRIORITY [02:02] */
-#define BCHP_XPT_FE_MINI_PID_PARSER6_TB_CTRL1_TB_IGNORE_TS_PRIORITY_MASK 0x00000004
-#define BCHP_XPT_FE_MINI_PID_PARSER6_TB_CTRL1_TB_IGNORE_TS_PRIORITY_SHIFT 2
-#define BCHP_XPT_FE_MINI_PID_PARSER6_TB_CTRL1_TB_IGNORE_TS_PRIORITY_DEFAULT 0x00000000
-
-/* XPT_FE :: MINI_PID_PARSER6_TB_CTRL1 :: TB_DROP_BEF_FIRST_MARKER_PKT [01:01] */
-#define BCHP_XPT_FE_MINI_PID_PARSER6_TB_CTRL1_TB_DROP_BEF_FIRST_MARKER_PKT_MASK 0x00000002
-#define BCHP_XPT_FE_MINI_PID_PARSER6_TB_CTRL1_TB_DROP_BEF_FIRST_MARKER_PKT_SHIFT 1
-#define BCHP_XPT_FE_MINI_PID_PARSER6_TB_CTRL1_TB_DROP_BEF_FIRST_MARKER_PKT_DEFAULT 0x00000000
-
-/* XPT_FE :: MINI_PID_PARSER6_TB_CTRL1 :: TB_ENABLE [00:00] */
-#define BCHP_XPT_FE_MINI_PID_PARSER6_TB_CTRL1_TB_ENABLE_MASK 0x00000001
-#define BCHP_XPT_FE_MINI_PID_PARSER6_TB_CTRL1_TB_ENABLE_SHIFT 0
-#define BCHP_XPT_FE_MINI_PID_PARSER6_TB_CTRL1_TB_ENABLE_DEFAULT 0x00000000
-
-/***************************************************************************
- *MINI_PID_PARSER6_SYNC_COUNT - Data Transport Parser Band 6 Transponder Bonding Sync Counter Register
- ***************************************************************************/
-/* XPT_FE :: MINI_PID_PARSER6_SYNC_COUNT :: reserved0 [31:10] */
-#define BCHP_XPT_FE_MINI_PID_PARSER6_SYNC_COUNT_reserved0_MASK 0xfffffc00
-#define BCHP_XPT_FE_MINI_PID_PARSER6_SYNC_COUNT_reserved0_SHIFT 10
-
-/* XPT_FE :: MINI_PID_PARSER6_SYNC_COUNT :: SYNC_COUNT [09:00] */
-#define BCHP_XPT_FE_MINI_PID_PARSER6_SYNC_COUNT_SYNC_COUNT_MASK 0x000003ff
-#define BCHP_XPT_FE_MINI_PID_PARSER6_SYNC_COUNT_SYNC_COUNT_SHIFT 0
-#define BCHP_XPT_FE_MINI_PID_PARSER6_SYNC_COUNT_SYNC_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *MINI_PID_PARSER7_TB_CTRL1 - Data Transport Parser Band 7 Transponder Bonding Control Register
- ***************************************************************************/
-/* XPT_FE :: MINI_PID_PARSER7_TB_CTRL1 :: reserved0 [31:28] */
-#define BCHP_XPT_FE_MINI_PID_PARSER7_TB_CTRL1_reserved0_MASK 0xf0000000
-#define BCHP_XPT_FE_MINI_PID_PARSER7_TB_CTRL1_reserved0_SHIFT 28
-
-/* XPT_FE :: MINI_PID_PARSER7_TB_CTRL1 :: TB_PARSER_PID_CH_NUM [27:16] */
-#define BCHP_XPT_FE_MINI_PID_PARSER7_TB_CTRL1_TB_PARSER_PID_CH_NUM_MASK 0x0fff0000
-#define BCHP_XPT_FE_MINI_PID_PARSER7_TB_CTRL1_TB_PARSER_PID_CH_NUM_SHIFT 16
-#define BCHP_XPT_FE_MINI_PID_PARSER7_TB_CTRL1_TB_PARSER_PID_CH_NUM_DEFAULT 0x00000000
-
-/* XPT_FE :: MINI_PID_PARSER7_TB_CTRL1 :: reserved1 [15:15] */
-#define BCHP_XPT_FE_MINI_PID_PARSER7_TB_CTRL1_reserved1_MASK 0x00008000
-#define BCHP_XPT_FE_MINI_PID_PARSER7_TB_CTRL1_reserved1_SHIFT 15
-
-/* XPT_FE :: MINI_PID_PARSER7_TB_CTRL1 :: TBG_PRI_BAND_NUM [14:08] */
-#define BCHP_XPT_FE_MINI_PID_PARSER7_TB_CTRL1_TBG_PRI_BAND_NUM_MASK 0x00007f00
-#define BCHP_XPT_FE_MINI_PID_PARSER7_TB_CTRL1_TBG_PRI_BAND_NUM_SHIFT 8
-#define BCHP_XPT_FE_MINI_PID_PARSER7_TB_CTRL1_TBG_PRI_BAND_NUM_DEFAULT 0x00000000
-
-/* XPT_FE :: MINI_PID_PARSER7_TB_CTRL1 :: reserved2 [07:04] */
-#define BCHP_XPT_FE_MINI_PID_PARSER7_TB_CTRL1_reserved2_MASK 0x000000f0
-#define BCHP_XPT_FE_MINI_PID_PARSER7_TB_CTRL1_reserved2_SHIFT 4
-
-/* XPT_FE :: MINI_PID_PARSER7_TB_CTRL1 :: TB_SKIP_ADAP_PRIVATE_DATA_PARSING [03:03] */
-#define BCHP_XPT_FE_MINI_PID_PARSER7_TB_CTRL1_TB_SKIP_ADAP_PRIVATE_DATA_PARSING_MASK 0x00000008
-#define BCHP_XPT_FE_MINI_PID_PARSER7_TB_CTRL1_TB_SKIP_ADAP_PRIVATE_DATA_PARSING_SHIFT 3
-#define BCHP_XPT_FE_MINI_PID_PARSER7_TB_CTRL1_TB_SKIP_ADAP_PRIVATE_DATA_PARSING_DEFAULT 0x00000000
-
-/* XPT_FE :: MINI_PID_PARSER7_TB_CTRL1 :: TB_IGNORE_TS_PRIORITY [02:02] */
-#define BCHP_XPT_FE_MINI_PID_PARSER7_TB_CTRL1_TB_IGNORE_TS_PRIORITY_MASK 0x00000004
-#define BCHP_XPT_FE_MINI_PID_PARSER7_TB_CTRL1_TB_IGNORE_TS_PRIORITY_SHIFT 2
-#define BCHP_XPT_FE_MINI_PID_PARSER7_TB_CTRL1_TB_IGNORE_TS_PRIORITY_DEFAULT 0x00000000
-
-/* XPT_FE :: MINI_PID_PARSER7_TB_CTRL1 :: TB_DROP_BEF_FIRST_MARKER_PKT [01:01] */
-#define BCHP_XPT_FE_MINI_PID_PARSER7_TB_CTRL1_TB_DROP_BEF_FIRST_MARKER_PKT_MASK 0x00000002
-#define BCHP_XPT_FE_MINI_PID_PARSER7_TB_CTRL1_TB_DROP_BEF_FIRST_MARKER_PKT_SHIFT 1
-#define BCHP_XPT_FE_MINI_PID_PARSER7_TB_CTRL1_TB_DROP_BEF_FIRST_MARKER_PKT_DEFAULT 0x00000000
-
-/* XPT_FE :: MINI_PID_PARSER7_TB_CTRL1 :: TB_ENABLE [00:00] */
-#define BCHP_XPT_FE_MINI_PID_PARSER7_TB_CTRL1_TB_ENABLE_MASK 0x00000001
-#define BCHP_XPT_FE_MINI_PID_PARSER7_TB_CTRL1_TB_ENABLE_SHIFT 0
-#define BCHP_XPT_FE_MINI_PID_PARSER7_TB_CTRL1_TB_ENABLE_DEFAULT 0x00000000
-
-/***************************************************************************
- *MINI_PID_PARSER7_SYNC_COUNT - Data Transport Parser Band 7 Transponder Bonding Sync Counter Register
- ***************************************************************************/
-/* XPT_FE :: MINI_PID_PARSER7_SYNC_COUNT :: reserved0 [31:10] */
-#define BCHP_XPT_FE_MINI_PID_PARSER7_SYNC_COUNT_reserved0_MASK 0xfffffc00
-#define BCHP_XPT_FE_MINI_PID_PARSER7_SYNC_COUNT_reserved0_SHIFT 10
-
-/* XPT_FE :: MINI_PID_PARSER7_SYNC_COUNT :: SYNC_COUNT [09:00] */
-#define BCHP_XPT_FE_MINI_PID_PARSER7_SYNC_COUNT_SYNC_COUNT_MASK 0x000003ff
-#define BCHP_XPT_FE_MINI_PID_PARSER7_SYNC_COUNT_SYNC_COUNT_SHIFT 0
-#define BCHP_XPT_FE_MINI_PID_PARSER7_SYNC_COUNT_SYNC_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *MINI_PID_PARSER8_TB_CTRL1 - Data Transport Parser Band 8 Transponder Bonding Control Register
- ***************************************************************************/
-/* XPT_FE :: MINI_PID_PARSER8_TB_CTRL1 :: reserved0 [31:28] */
-#define BCHP_XPT_FE_MINI_PID_PARSER8_TB_CTRL1_reserved0_MASK 0xf0000000
-#define BCHP_XPT_FE_MINI_PID_PARSER8_TB_CTRL1_reserved0_SHIFT 28
-
-/* XPT_FE :: MINI_PID_PARSER8_TB_CTRL1 :: TB_PARSER_PID_CH_NUM [27:16] */
-#define BCHP_XPT_FE_MINI_PID_PARSER8_TB_CTRL1_TB_PARSER_PID_CH_NUM_MASK 0x0fff0000
-#define BCHP_XPT_FE_MINI_PID_PARSER8_TB_CTRL1_TB_PARSER_PID_CH_NUM_SHIFT 16
-#define BCHP_XPT_FE_MINI_PID_PARSER8_TB_CTRL1_TB_PARSER_PID_CH_NUM_DEFAULT 0x00000000
-
-/* XPT_FE :: MINI_PID_PARSER8_TB_CTRL1 :: reserved1 [15:15] */
-#define BCHP_XPT_FE_MINI_PID_PARSER8_TB_CTRL1_reserved1_MASK 0x00008000
-#define BCHP_XPT_FE_MINI_PID_PARSER8_TB_CTRL1_reserved1_SHIFT 15
-
-/* XPT_FE :: MINI_PID_PARSER8_TB_CTRL1 :: TBG_PRI_BAND_NUM [14:08] */
-#define BCHP_XPT_FE_MINI_PID_PARSER8_TB_CTRL1_TBG_PRI_BAND_NUM_MASK 0x00007f00
-#define BCHP_XPT_FE_MINI_PID_PARSER8_TB_CTRL1_TBG_PRI_BAND_NUM_SHIFT 8
-#define BCHP_XPT_FE_MINI_PID_PARSER8_TB_CTRL1_TBG_PRI_BAND_NUM_DEFAULT 0x00000000
-
-/* XPT_FE :: MINI_PID_PARSER8_TB_CTRL1 :: reserved2 [07:04] */
-#define BCHP_XPT_FE_MINI_PID_PARSER8_TB_CTRL1_reserved2_MASK 0x000000f0
-#define BCHP_XPT_FE_MINI_PID_PARSER8_TB_CTRL1_reserved2_SHIFT 4
-
-/* XPT_FE :: MINI_PID_PARSER8_TB_CTRL1 :: TB_SKIP_ADAP_PRIVATE_DATA_PARSING [03:03] */
-#define BCHP_XPT_FE_MINI_PID_PARSER8_TB_CTRL1_TB_SKIP_ADAP_PRIVATE_DATA_PARSING_MASK 0x00000008
-#define BCHP_XPT_FE_MINI_PID_PARSER8_TB_CTRL1_TB_SKIP_ADAP_PRIVATE_DATA_PARSING_SHIFT 3
-#define BCHP_XPT_FE_MINI_PID_PARSER8_TB_CTRL1_TB_SKIP_ADAP_PRIVATE_DATA_PARSING_DEFAULT 0x00000000
-
-/* XPT_FE :: MINI_PID_PARSER8_TB_CTRL1 :: TB_IGNORE_TS_PRIORITY [02:02] */
-#define BCHP_XPT_FE_MINI_PID_PARSER8_TB_CTRL1_TB_IGNORE_TS_PRIORITY_MASK 0x00000004
-#define BCHP_XPT_FE_MINI_PID_PARSER8_TB_CTRL1_TB_IGNORE_TS_PRIORITY_SHIFT 2
-#define BCHP_XPT_FE_MINI_PID_PARSER8_TB_CTRL1_TB_IGNORE_TS_PRIORITY_DEFAULT 0x00000000
-
-/* XPT_FE :: MINI_PID_PARSER8_TB_CTRL1 :: TB_DROP_BEF_FIRST_MARKER_PKT [01:01] */
-#define BCHP_XPT_FE_MINI_PID_PARSER8_TB_CTRL1_TB_DROP_BEF_FIRST_MARKER_PKT_MASK 0x00000002
-#define BCHP_XPT_FE_MINI_PID_PARSER8_TB_CTRL1_TB_DROP_BEF_FIRST_MARKER_PKT_SHIFT 1
-#define BCHP_XPT_FE_MINI_PID_PARSER8_TB_CTRL1_TB_DROP_BEF_FIRST_MARKER_PKT_DEFAULT 0x00000000
-
-/* XPT_FE :: MINI_PID_PARSER8_TB_CTRL1 :: TB_ENABLE [00:00] */
-#define BCHP_XPT_FE_MINI_PID_PARSER8_TB_CTRL1_TB_ENABLE_MASK 0x00000001
-#define BCHP_XPT_FE_MINI_PID_PARSER8_TB_CTRL1_TB_ENABLE_SHIFT 0
-#define BCHP_XPT_FE_MINI_PID_PARSER8_TB_CTRL1_TB_ENABLE_DEFAULT 0x00000000
-
-/***************************************************************************
- *MINI_PID_PARSER8_SYNC_COUNT - Data Transport Parser Band 8 Transponder Bonding Sync Counter Register
- ***************************************************************************/
-/* XPT_FE :: MINI_PID_PARSER8_SYNC_COUNT :: reserved0 [31:10] */
-#define BCHP_XPT_FE_MINI_PID_PARSER8_SYNC_COUNT_reserved0_MASK 0xfffffc00
-#define BCHP_XPT_FE_MINI_PID_PARSER8_SYNC_COUNT_reserved0_SHIFT 10
-
-/* XPT_FE :: MINI_PID_PARSER8_SYNC_COUNT :: SYNC_COUNT [09:00] */
-#define BCHP_XPT_FE_MINI_PID_PARSER8_SYNC_COUNT_SYNC_COUNT_MASK 0x000003ff
-#define BCHP_XPT_FE_MINI_PID_PARSER8_SYNC_COUNT_SYNC_COUNT_SHIFT 0
-#define BCHP_XPT_FE_MINI_PID_PARSER8_SYNC_COUNT_SYNC_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *MINI_PID_PARSER9_TB_CTRL1 - Data Transport Parser Band 9 Transponder Bonding Control Register
- ***************************************************************************/
-/* XPT_FE :: MINI_PID_PARSER9_TB_CTRL1 :: reserved0 [31:28] */
-#define BCHP_XPT_FE_MINI_PID_PARSER9_TB_CTRL1_reserved0_MASK 0xf0000000
-#define BCHP_XPT_FE_MINI_PID_PARSER9_TB_CTRL1_reserved0_SHIFT 28
-
-/* XPT_FE :: MINI_PID_PARSER9_TB_CTRL1 :: TB_PARSER_PID_CH_NUM [27:16] */
-#define BCHP_XPT_FE_MINI_PID_PARSER9_TB_CTRL1_TB_PARSER_PID_CH_NUM_MASK 0x0fff0000
-#define BCHP_XPT_FE_MINI_PID_PARSER9_TB_CTRL1_TB_PARSER_PID_CH_NUM_SHIFT 16
-#define BCHP_XPT_FE_MINI_PID_PARSER9_TB_CTRL1_TB_PARSER_PID_CH_NUM_DEFAULT 0x00000000
-
-/* XPT_FE :: MINI_PID_PARSER9_TB_CTRL1 :: reserved1 [15:15] */
-#define BCHP_XPT_FE_MINI_PID_PARSER9_TB_CTRL1_reserved1_MASK 0x00008000
-#define BCHP_XPT_FE_MINI_PID_PARSER9_TB_CTRL1_reserved1_SHIFT 15
-
-/* XPT_FE :: MINI_PID_PARSER9_TB_CTRL1 :: TBG_PRI_BAND_NUM [14:08] */
-#define BCHP_XPT_FE_MINI_PID_PARSER9_TB_CTRL1_TBG_PRI_BAND_NUM_MASK 0x00007f00
-#define BCHP_XPT_FE_MINI_PID_PARSER9_TB_CTRL1_TBG_PRI_BAND_NUM_SHIFT 8
-#define BCHP_XPT_FE_MINI_PID_PARSER9_TB_CTRL1_TBG_PRI_BAND_NUM_DEFAULT 0x00000000
-
-/* XPT_FE :: MINI_PID_PARSER9_TB_CTRL1 :: reserved2 [07:04] */
-#define BCHP_XPT_FE_MINI_PID_PARSER9_TB_CTRL1_reserved2_MASK 0x000000f0
-#define BCHP_XPT_FE_MINI_PID_PARSER9_TB_CTRL1_reserved2_SHIFT 4
-
-/* XPT_FE :: MINI_PID_PARSER9_TB_CTRL1 :: TB_SKIP_ADAP_PRIVATE_DATA_PARSING [03:03] */
-#define BCHP_XPT_FE_MINI_PID_PARSER9_TB_CTRL1_TB_SKIP_ADAP_PRIVATE_DATA_PARSING_MASK 0x00000008
-#define BCHP_XPT_FE_MINI_PID_PARSER9_TB_CTRL1_TB_SKIP_ADAP_PRIVATE_DATA_PARSING_SHIFT 3
-#define BCHP_XPT_FE_MINI_PID_PARSER9_TB_CTRL1_TB_SKIP_ADAP_PRIVATE_DATA_PARSING_DEFAULT 0x00000000
-
-/* XPT_FE :: MINI_PID_PARSER9_TB_CTRL1 :: TB_IGNORE_TS_PRIORITY [02:02] */
-#define BCHP_XPT_FE_MINI_PID_PARSER9_TB_CTRL1_TB_IGNORE_TS_PRIORITY_MASK 0x00000004
-#define BCHP_XPT_FE_MINI_PID_PARSER9_TB_CTRL1_TB_IGNORE_TS_PRIORITY_SHIFT 2
-#define BCHP_XPT_FE_MINI_PID_PARSER9_TB_CTRL1_TB_IGNORE_TS_PRIORITY_DEFAULT 0x00000000
-
-/* XPT_FE :: MINI_PID_PARSER9_TB_CTRL1 :: TB_DROP_BEF_FIRST_MARKER_PKT [01:01] */
-#define BCHP_XPT_FE_MINI_PID_PARSER9_TB_CTRL1_TB_DROP_BEF_FIRST_MARKER_PKT_MASK 0x00000002
-#define BCHP_XPT_FE_MINI_PID_PARSER9_TB_CTRL1_TB_DROP_BEF_FIRST_MARKER_PKT_SHIFT 1
-#define BCHP_XPT_FE_MINI_PID_PARSER9_TB_CTRL1_TB_DROP_BEF_FIRST_MARKER_PKT_DEFAULT 0x00000000
-
-/* XPT_FE :: MINI_PID_PARSER9_TB_CTRL1 :: TB_ENABLE [00:00] */
-#define BCHP_XPT_FE_MINI_PID_PARSER9_TB_CTRL1_TB_ENABLE_MASK 0x00000001
-#define BCHP_XPT_FE_MINI_PID_PARSER9_TB_CTRL1_TB_ENABLE_SHIFT 0
-#define BCHP_XPT_FE_MINI_PID_PARSER9_TB_CTRL1_TB_ENABLE_DEFAULT 0x00000000
-
-/***************************************************************************
- *MINI_PID_PARSER9_SYNC_COUNT - Data Transport Parser Band 9 Transponder Bonding Sync Counter Register
- ***************************************************************************/
-/* XPT_FE :: MINI_PID_PARSER9_SYNC_COUNT :: reserved0 [31:10] */
-#define BCHP_XPT_FE_MINI_PID_PARSER9_SYNC_COUNT_reserved0_MASK 0xfffffc00
-#define BCHP_XPT_FE_MINI_PID_PARSER9_SYNC_COUNT_reserved0_SHIFT 10
-
-/* XPT_FE :: MINI_PID_PARSER9_SYNC_COUNT :: SYNC_COUNT [09:00] */
-#define BCHP_XPT_FE_MINI_PID_PARSER9_SYNC_COUNT_SYNC_COUNT_MASK 0x000003ff
-#define BCHP_XPT_FE_MINI_PID_PARSER9_SYNC_COUNT_SYNC_COUNT_SHIFT 0
-#define BCHP_XPT_FE_MINI_PID_PARSER9_SYNC_COUNT_SYNC_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *MINI_PID_PARSER10_TB_CTRL1 - Data Transport Parser Band 10 Transponder Bonding Control Register
- ***************************************************************************/
-/* XPT_FE :: MINI_PID_PARSER10_TB_CTRL1 :: reserved0 [31:28] */
-#define BCHP_XPT_FE_MINI_PID_PARSER10_TB_CTRL1_reserved0_MASK 0xf0000000
-#define BCHP_XPT_FE_MINI_PID_PARSER10_TB_CTRL1_reserved0_SHIFT 28
-
-/* XPT_FE :: MINI_PID_PARSER10_TB_CTRL1 :: TB_PARSER_PID_CH_NUM [27:16] */
-#define BCHP_XPT_FE_MINI_PID_PARSER10_TB_CTRL1_TB_PARSER_PID_CH_NUM_MASK 0x0fff0000
-#define BCHP_XPT_FE_MINI_PID_PARSER10_TB_CTRL1_TB_PARSER_PID_CH_NUM_SHIFT 16
-#define BCHP_XPT_FE_MINI_PID_PARSER10_TB_CTRL1_TB_PARSER_PID_CH_NUM_DEFAULT 0x00000000
-
-/* XPT_FE :: MINI_PID_PARSER10_TB_CTRL1 :: reserved1 [15:15] */
-#define BCHP_XPT_FE_MINI_PID_PARSER10_TB_CTRL1_reserved1_MASK 0x00008000
-#define BCHP_XPT_FE_MINI_PID_PARSER10_TB_CTRL1_reserved1_SHIFT 15
-
-/* XPT_FE :: MINI_PID_PARSER10_TB_CTRL1 :: TBG_PRI_BAND_NUM [14:08] */
-#define BCHP_XPT_FE_MINI_PID_PARSER10_TB_CTRL1_TBG_PRI_BAND_NUM_MASK 0x00007f00
-#define BCHP_XPT_FE_MINI_PID_PARSER10_TB_CTRL1_TBG_PRI_BAND_NUM_SHIFT 8
-#define BCHP_XPT_FE_MINI_PID_PARSER10_TB_CTRL1_TBG_PRI_BAND_NUM_DEFAULT 0x00000000
-
-/* XPT_FE :: MINI_PID_PARSER10_TB_CTRL1 :: reserved2 [07:04] */
-#define BCHP_XPT_FE_MINI_PID_PARSER10_TB_CTRL1_reserved2_MASK 0x000000f0
-#define BCHP_XPT_FE_MINI_PID_PARSER10_TB_CTRL1_reserved2_SHIFT 4
-
-/* XPT_FE :: MINI_PID_PARSER10_TB_CTRL1 :: TB_SKIP_ADAP_PRIVATE_DATA_PARSING [03:03] */
-#define BCHP_XPT_FE_MINI_PID_PARSER10_TB_CTRL1_TB_SKIP_ADAP_PRIVATE_DATA_PARSING_MASK 0x00000008
-#define BCHP_XPT_FE_MINI_PID_PARSER10_TB_CTRL1_TB_SKIP_ADAP_PRIVATE_DATA_PARSING_SHIFT 3
-#define BCHP_XPT_FE_MINI_PID_PARSER10_TB_CTRL1_TB_SKIP_ADAP_PRIVATE_DATA_PARSING_DEFAULT 0x00000000
-
-/* XPT_FE :: MINI_PID_PARSER10_TB_CTRL1 :: TB_IGNORE_TS_PRIORITY [02:02] */
-#define BCHP_XPT_FE_MINI_PID_PARSER10_TB_CTRL1_TB_IGNORE_TS_PRIORITY_MASK 0x00000004
-#define BCHP_XPT_FE_MINI_PID_PARSER10_TB_CTRL1_TB_IGNORE_TS_PRIORITY_SHIFT 2
-#define BCHP_XPT_FE_MINI_PID_PARSER10_TB_CTRL1_TB_IGNORE_TS_PRIORITY_DEFAULT 0x00000000
-
-/* XPT_FE :: MINI_PID_PARSER10_TB_CTRL1 :: TB_DROP_BEF_FIRST_MARKER_PKT [01:01] */
-#define BCHP_XPT_FE_MINI_PID_PARSER10_TB_CTRL1_TB_DROP_BEF_FIRST_MARKER_PKT_MASK 0x00000002
-#define BCHP_XPT_FE_MINI_PID_PARSER10_TB_CTRL1_TB_DROP_BEF_FIRST_MARKER_PKT_SHIFT 1
-#define BCHP_XPT_FE_MINI_PID_PARSER10_TB_CTRL1_TB_DROP_BEF_FIRST_MARKER_PKT_DEFAULT 0x00000000
-
-/* XPT_FE :: MINI_PID_PARSER10_TB_CTRL1 :: TB_ENABLE [00:00] */
-#define BCHP_XPT_FE_MINI_PID_PARSER10_TB_CTRL1_TB_ENABLE_MASK 0x00000001
-#define BCHP_XPT_FE_MINI_PID_PARSER10_TB_CTRL1_TB_ENABLE_SHIFT 0
-#define BCHP_XPT_FE_MINI_PID_PARSER10_TB_CTRL1_TB_ENABLE_DEFAULT 0x00000000
-
-/***************************************************************************
- *MINI_PID_PARSER10_SYNC_COUNT - Data Transport Parser Band 10 Transponder Bonding Sync Counter Register
- ***************************************************************************/
-/* XPT_FE :: MINI_PID_PARSER10_SYNC_COUNT :: reserved0 [31:10] */
-#define BCHP_XPT_FE_MINI_PID_PARSER10_SYNC_COUNT_reserved0_MASK 0xfffffc00
-#define BCHP_XPT_FE_MINI_PID_PARSER10_SYNC_COUNT_reserved0_SHIFT 10
-
-/* XPT_FE :: MINI_PID_PARSER10_SYNC_COUNT :: SYNC_COUNT [09:00] */
-#define BCHP_XPT_FE_MINI_PID_PARSER10_SYNC_COUNT_SYNC_COUNT_MASK 0x000003ff
-#define BCHP_XPT_FE_MINI_PID_PARSER10_SYNC_COUNT_SYNC_COUNT_SHIFT 0
-#define BCHP_XPT_FE_MINI_PID_PARSER10_SYNC_COUNT_SYNC_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *MINI_PID_PARSER11_TB_CTRL1 - Data Transport Parser Band 11 Transponder Bonding Control Register
- ***************************************************************************/
-/* XPT_FE :: MINI_PID_PARSER11_TB_CTRL1 :: reserved0 [31:28] */
-#define BCHP_XPT_FE_MINI_PID_PARSER11_TB_CTRL1_reserved0_MASK 0xf0000000
-#define BCHP_XPT_FE_MINI_PID_PARSER11_TB_CTRL1_reserved0_SHIFT 28
-
-/* XPT_FE :: MINI_PID_PARSER11_TB_CTRL1 :: TB_PARSER_PID_CH_NUM [27:16] */
-#define BCHP_XPT_FE_MINI_PID_PARSER11_TB_CTRL1_TB_PARSER_PID_CH_NUM_MASK 0x0fff0000
-#define BCHP_XPT_FE_MINI_PID_PARSER11_TB_CTRL1_TB_PARSER_PID_CH_NUM_SHIFT 16
-#define BCHP_XPT_FE_MINI_PID_PARSER11_TB_CTRL1_TB_PARSER_PID_CH_NUM_DEFAULT 0x00000000
-
-/* XPT_FE :: MINI_PID_PARSER11_TB_CTRL1 :: reserved1 [15:15] */
-#define BCHP_XPT_FE_MINI_PID_PARSER11_TB_CTRL1_reserved1_MASK 0x00008000
-#define BCHP_XPT_FE_MINI_PID_PARSER11_TB_CTRL1_reserved1_SHIFT 15
-
-/* XPT_FE :: MINI_PID_PARSER11_TB_CTRL1 :: TBG_PRI_BAND_NUM [14:08] */
-#define BCHP_XPT_FE_MINI_PID_PARSER11_TB_CTRL1_TBG_PRI_BAND_NUM_MASK 0x00007f00
-#define BCHP_XPT_FE_MINI_PID_PARSER11_TB_CTRL1_TBG_PRI_BAND_NUM_SHIFT 8
-#define BCHP_XPT_FE_MINI_PID_PARSER11_TB_CTRL1_TBG_PRI_BAND_NUM_DEFAULT 0x00000000
-
-/* XPT_FE :: MINI_PID_PARSER11_TB_CTRL1 :: reserved2 [07:04] */
-#define BCHP_XPT_FE_MINI_PID_PARSER11_TB_CTRL1_reserved2_MASK 0x000000f0
-#define BCHP_XPT_FE_MINI_PID_PARSER11_TB_CTRL1_reserved2_SHIFT 4
-
-/* XPT_FE :: MINI_PID_PARSER11_TB_CTRL1 :: TB_SKIP_ADAP_PRIVATE_DATA_PARSING [03:03] */
-#define BCHP_XPT_FE_MINI_PID_PARSER11_TB_CTRL1_TB_SKIP_ADAP_PRIVATE_DATA_PARSING_MASK 0x00000008
-#define BCHP_XPT_FE_MINI_PID_PARSER11_TB_CTRL1_TB_SKIP_ADAP_PRIVATE_DATA_PARSING_SHIFT 3
-#define BCHP_XPT_FE_MINI_PID_PARSER11_TB_CTRL1_TB_SKIP_ADAP_PRIVATE_DATA_PARSING_DEFAULT 0x00000000
-
-/* XPT_FE :: MINI_PID_PARSER11_TB_CTRL1 :: TB_IGNORE_TS_PRIORITY [02:02] */
-#define BCHP_XPT_FE_MINI_PID_PARSER11_TB_CTRL1_TB_IGNORE_TS_PRIORITY_MASK 0x00000004
-#define BCHP_XPT_FE_MINI_PID_PARSER11_TB_CTRL1_TB_IGNORE_TS_PRIORITY_SHIFT 2
-#define BCHP_XPT_FE_MINI_PID_PARSER11_TB_CTRL1_TB_IGNORE_TS_PRIORITY_DEFAULT 0x00000000
-
-/* XPT_FE :: MINI_PID_PARSER11_TB_CTRL1 :: TB_DROP_BEF_FIRST_MARKER_PKT [01:01] */
-#define BCHP_XPT_FE_MINI_PID_PARSER11_TB_CTRL1_TB_DROP_BEF_FIRST_MARKER_PKT_MASK 0x00000002
-#define BCHP_XPT_FE_MINI_PID_PARSER11_TB_CTRL1_TB_DROP_BEF_FIRST_MARKER_PKT_SHIFT 1
-#define BCHP_XPT_FE_MINI_PID_PARSER11_TB_CTRL1_TB_DROP_BEF_FIRST_MARKER_PKT_DEFAULT 0x00000000
-
-/* XPT_FE :: MINI_PID_PARSER11_TB_CTRL1 :: TB_ENABLE [00:00] */
-#define BCHP_XPT_FE_MINI_PID_PARSER11_TB_CTRL1_TB_ENABLE_MASK 0x00000001
-#define BCHP_XPT_FE_MINI_PID_PARSER11_TB_CTRL1_TB_ENABLE_SHIFT 0
-#define BCHP_XPT_FE_MINI_PID_PARSER11_TB_CTRL1_TB_ENABLE_DEFAULT 0x00000000
-
-/***************************************************************************
- *MINI_PID_PARSER11_SYNC_COUNT - Data Transport Parser Band 11 Transponder Bonding Sync Counter Register
- ***************************************************************************/
-/* XPT_FE :: MINI_PID_PARSER11_SYNC_COUNT :: reserved0 [31:10] */
-#define BCHP_XPT_FE_MINI_PID_PARSER11_SYNC_COUNT_reserved0_MASK 0xfffffc00
-#define BCHP_XPT_FE_MINI_PID_PARSER11_SYNC_COUNT_reserved0_SHIFT 10
-
-/* XPT_FE :: MINI_PID_PARSER11_SYNC_COUNT :: SYNC_COUNT [09:00] */
-#define BCHP_XPT_FE_MINI_PID_PARSER11_SYNC_COUNT_SYNC_COUNT_MASK 0x000003ff
-#define BCHP_XPT_FE_MINI_PID_PARSER11_SYNC_COUNT_SYNC_COUNT_SHIFT 0
-#define BCHP_XPT_FE_MINI_PID_PARSER11_SYNC_COUNT_SYNC_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *MINI_PID_PARSER12_TB_CTRL1 - Data Transport Parser Band 12 Transponder Bonding Control Register
- ***************************************************************************/
-/* XPT_FE :: MINI_PID_PARSER12_TB_CTRL1 :: reserved0 [31:28] */
-#define BCHP_XPT_FE_MINI_PID_PARSER12_TB_CTRL1_reserved0_MASK 0xf0000000
-#define BCHP_XPT_FE_MINI_PID_PARSER12_TB_CTRL1_reserved0_SHIFT 28
-
-/* XPT_FE :: MINI_PID_PARSER12_TB_CTRL1 :: TB_PARSER_PID_CH_NUM [27:16] */
-#define BCHP_XPT_FE_MINI_PID_PARSER12_TB_CTRL1_TB_PARSER_PID_CH_NUM_MASK 0x0fff0000
-#define BCHP_XPT_FE_MINI_PID_PARSER12_TB_CTRL1_TB_PARSER_PID_CH_NUM_SHIFT 16
-#define BCHP_XPT_FE_MINI_PID_PARSER12_TB_CTRL1_TB_PARSER_PID_CH_NUM_DEFAULT 0x00000000
-
-/* XPT_FE :: MINI_PID_PARSER12_TB_CTRL1 :: reserved1 [15:15] */
-#define BCHP_XPT_FE_MINI_PID_PARSER12_TB_CTRL1_reserved1_MASK 0x00008000
-#define BCHP_XPT_FE_MINI_PID_PARSER12_TB_CTRL1_reserved1_SHIFT 15
-
-/* XPT_FE :: MINI_PID_PARSER12_TB_CTRL1 :: TBG_PRI_BAND_NUM [14:08] */
-#define BCHP_XPT_FE_MINI_PID_PARSER12_TB_CTRL1_TBG_PRI_BAND_NUM_MASK 0x00007f00
-#define BCHP_XPT_FE_MINI_PID_PARSER12_TB_CTRL1_TBG_PRI_BAND_NUM_SHIFT 8
-#define BCHP_XPT_FE_MINI_PID_PARSER12_TB_CTRL1_TBG_PRI_BAND_NUM_DEFAULT 0x00000000
-
-/* XPT_FE :: MINI_PID_PARSER12_TB_CTRL1 :: reserved2 [07:04] */
-#define BCHP_XPT_FE_MINI_PID_PARSER12_TB_CTRL1_reserved2_MASK 0x000000f0
-#define BCHP_XPT_FE_MINI_PID_PARSER12_TB_CTRL1_reserved2_SHIFT 4
-
-/* XPT_FE :: MINI_PID_PARSER12_TB_CTRL1 :: TB_SKIP_ADAP_PRIVATE_DATA_PARSING [03:03] */
-#define BCHP_XPT_FE_MINI_PID_PARSER12_TB_CTRL1_TB_SKIP_ADAP_PRIVATE_DATA_PARSING_MASK 0x00000008
-#define BCHP_XPT_FE_MINI_PID_PARSER12_TB_CTRL1_TB_SKIP_ADAP_PRIVATE_DATA_PARSING_SHIFT 3
-#define BCHP_XPT_FE_MINI_PID_PARSER12_TB_CTRL1_TB_SKIP_ADAP_PRIVATE_DATA_PARSING_DEFAULT 0x00000000
-
-/* XPT_FE :: MINI_PID_PARSER12_TB_CTRL1 :: TB_IGNORE_TS_PRIORITY [02:02] */
-#define BCHP_XPT_FE_MINI_PID_PARSER12_TB_CTRL1_TB_IGNORE_TS_PRIORITY_MASK 0x00000004
-#define BCHP_XPT_FE_MINI_PID_PARSER12_TB_CTRL1_TB_IGNORE_TS_PRIORITY_SHIFT 2
-#define BCHP_XPT_FE_MINI_PID_PARSER12_TB_CTRL1_TB_IGNORE_TS_PRIORITY_DEFAULT 0x00000000
-
-/* XPT_FE :: MINI_PID_PARSER12_TB_CTRL1 :: TB_DROP_BEF_FIRST_MARKER_PKT [01:01] */
-#define BCHP_XPT_FE_MINI_PID_PARSER12_TB_CTRL1_TB_DROP_BEF_FIRST_MARKER_PKT_MASK 0x00000002
-#define BCHP_XPT_FE_MINI_PID_PARSER12_TB_CTRL1_TB_DROP_BEF_FIRST_MARKER_PKT_SHIFT 1
-#define BCHP_XPT_FE_MINI_PID_PARSER12_TB_CTRL1_TB_DROP_BEF_FIRST_MARKER_PKT_DEFAULT 0x00000000
-
-/* XPT_FE :: MINI_PID_PARSER12_TB_CTRL1 :: TB_ENABLE [00:00] */
-#define BCHP_XPT_FE_MINI_PID_PARSER12_TB_CTRL1_TB_ENABLE_MASK 0x00000001
-#define BCHP_XPT_FE_MINI_PID_PARSER12_TB_CTRL1_TB_ENABLE_SHIFT 0
-#define BCHP_XPT_FE_MINI_PID_PARSER12_TB_CTRL1_TB_ENABLE_DEFAULT 0x00000000
-
-/***************************************************************************
- *MINI_PID_PARSER12_SYNC_COUNT - Data Transport Parser Band 12 Transponder Bonding Sync Counter Register
- ***************************************************************************/
-/* XPT_FE :: MINI_PID_PARSER12_SYNC_COUNT :: reserved0 [31:10] */
-#define BCHP_XPT_FE_MINI_PID_PARSER12_SYNC_COUNT_reserved0_MASK 0xfffffc00
-#define BCHP_XPT_FE_MINI_PID_PARSER12_SYNC_COUNT_reserved0_SHIFT 10
-
-/* XPT_FE :: MINI_PID_PARSER12_SYNC_COUNT :: SYNC_COUNT [09:00] */
-#define BCHP_XPT_FE_MINI_PID_PARSER12_SYNC_COUNT_SYNC_COUNT_MASK 0x000003ff
-#define BCHP_XPT_FE_MINI_PID_PARSER12_SYNC_COUNT_SYNC_COUNT_SHIFT 0
-#define BCHP_XPT_FE_MINI_PID_PARSER12_SYNC_COUNT_SYNC_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *MINI_PID_PARSER13_TB_CTRL1 - Data Transport Parser Band 13 Transponder Bonding Control Register
- ***************************************************************************/
-/* XPT_FE :: MINI_PID_PARSER13_TB_CTRL1 :: reserved0 [31:28] */
-#define BCHP_XPT_FE_MINI_PID_PARSER13_TB_CTRL1_reserved0_MASK 0xf0000000
-#define BCHP_XPT_FE_MINI_PID_PARSER13_TB_CTRL1_reserved0_SHIFT 28
-
-/* XPT_FE :: MINI_PID_PARSER13_TB_CTRL1 :: TB_PARSER_PID_CH_NUM [27:16] */
-#define BCHP_XPT_FE_MINI_PID_PARSER13_TB_CTRL1_TB_PARSER_PID_CH_NUM_MASK 0x0fff0000
-#define BCHP_XPT_FE_MINI_PID_PARSER13_TB_CTRL1_TB_PARSER_PID_CH_NUM_SHIFT 16
-#define BCHP_XPT_FE_MINI_PID_PARSER13_TB_CTRL1_TB_PARSER_PID_CH_NUM_DEFAULT 0x00000000
-
-/* XPT_FE :: MINI_PID_PARSER13_TB_CTRL1 :: reserved1 [15:15] */
-#define BCHP_XPT_FE_MINI_PID_PARSER13_TB_CTRL1_reserved1_MASK 0x00008000
-#define BCHP_XPT_FE_MINI_PID_PARSER13_TB_CTRL1_reserved1_SHIFT 15
-
-/* XPT_FE :: MINI_PID_PARSER13_TB_CTRL1 :: TBG_PRI_BAND_NUM [14:08] */
-#define BCHP_XPT_FE_MINI_PID_PARSER13_TB_CTRL1_TBG_PRI_BAND_NUM_MASK 0x00007f00
-#define BCHP_XPT_FE_MINI_PID_PARSER13_TB_CTRL1_TBG_PRI_BAND_NUM_SHIFT 8
-#define BCHP_XPT_FE_MINI_PID_PARSER13_TB_CTRL1_TBG_PRI_BAND_NUM_DEFAULT 0x00000000
-
-/* XPT_FE :: MINI_PID_PARSER13_TB_CTRL1 :: reserved2 [07:04] */
-#define BCHP_XPT_FE_MINI_PID_PARSER13_TB_CTRL1_reserved2_MASK 0x000000f0
-#define BCHP_XPT_FE_MINI_PID_PARSER13_TB_CTRL1_reserved2_SHIFT 4
-
-/* XPT_FE :: MINI_PID_PARSER13_TB_CTRL1 :: TB_SKIP_ADAP_PRIVATE_DATA_PARSING [03:03] */
-#define BCHP_XPT_FE_MINI_PID_PARSER13_TB_CTRL1_TB_SKIP_ADAP_PRIVATE_DATA_PARSING_MASK 0x00000008
-#define BCHP_XPT_FE_MINI_PID_PARSER13_TB_CTRL1_TB_SKIP_ADAP_PRIVATE_DATA_PARSING_SHIFT 3
-#define BCHP_XPT_FE_MINI_PID_PARSER13_TB_CTRL1_TB_SKIP_ADAP_PRIVATE_DATA_PARSING_DEFAULT 0x00000000
-
-/* XPT_FE :: MINI_PID_PARSER13_TB_CTRL1 :: TB_IGNORE_TS_PRIORITY [02:02] */
-#define BCHP_XPT_FE_MINI_PID_PARSER13_TB_CTRL1_TB_IGNORE_TS_PRIORITY_MASK 0x00000004
-#define BCHP_XPT_FE_MINI_PID_PARSER13_TB_CTRL1_TB_IGNORE_TS_PRIORITY_SHIFT 2
-#define BCHP_XPT_FE_MINI_PID_PARSER13_TB_CTRL1_TB_IGNORE_TS_PRIORITY_DEFAULT 0x00000000
-
-/* XPT_FE :: MINI_PID_PARSER13_TB_CTRL1 :: TB_DROP_BEF_FIRST_MARKER_PKT [01:01] */
-#define BCHP_XPT_FE_MINI_PID_PARSER13_TB_CTRL1_TB_DROP_BEF_FIRST_MARKER_PKT_MASK 0x00000002
-#define BCHP_XPT_FE_MINI_PID_PARSER13_TB_CTRL1_TB_DROP_BEF_FIRST_MARKER_PKT_SHIFT 1
-#define BCHP_XPT_FE_MINI_PID_PARSER13_TB_CTRL1_TB_DROP_BEF_FIRST_MARKER_PKT_DEFAULT 0x00000000
-
-/* XPT_FE :: MINI_PID_PARSER13_TB_CTRL1 :: TB_ENABLE [00:00] */
-#define BCHP_XPT_FE_MINI_PID_PARSER13_TB_CTRL1_TB_ENABLE_MASK 0x00000001
-#define BCHP_XPT_FE_MINI_PID_PARSER13_TB_CTRL1_TB_ENABLE_SHIFT 0
-#define BCHP_XPT_FE_MINI_PID_PARSER13_TB_CTRL1_TB_ENABLE_DEFAULT 0x00000000
-
-/***************************************************************************
- *MINI_PID_PARSER13_SYNC_COUNT - Data Transport Parser Band 13 Transponder Bonding Sync Counter Register
- ***************************************************************************/
-/* XPT_FE :: MINI_PID_PARSER13_SYNC_COUNT :: reserved0 [31:10] */
-#define BCHP_XPT_FE_MINI_PID_PARSER13_SYNC_COUNT_reserved0_MASK 0xfffffc00
-#define BCHP_XPT_FE_MINI_PID_PARSER13_SYNC_COUNT_reserved0_SHIFT 10
-
-/* XPT_FE :: MINI_PID_PARSER13_SYNC_COUNT :: SYNC_COUNT [09:00] */
-#define BCHP_XPT_FE_MINI_PID_PARSER13_SYNC_COUNT_SYNC_COUNT_MASK 0x000003ff
-#define BCHP_XPT_FE_MINI_PID_PARSER13_SYNC_COUNT_SYNC_COUNT_SHIFT 0
-#define BCHP_XPT_FE_MINI_PID_PARSER13_SYNC_COUNT_SYNC_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *MINI_PID_PARSER14_TB_CTRL1 - Data Transport Parser Band 14 Transponder Bonding Control Register
- ***************************************************************************/
-/* XPT_FE :: MINI_PID_PARSER14_TB_CTRL1 :: reserved0 [31:28] */
-#define BCHP_XPT_FE_MINI_PID_PARSER14_TB_CTRL1_reserved0_MASK 0xf0000000
-#define BCHP_XPT_FE_MINI_PID_PARSER14_TB_CTRL1_reserved0_SHIFT 28
-
-/* XPT_FE :: MINI_PID_PARSER14_TB_CTRL1 :: TB_PARSER_PID_CH_NUM [27:16] */
-#define BCHP_XPT_FE_MINI_PID_PARSER14_TB_CTRL1_TB_PARSER_PID_CH_NUM_MASK 0x0fff0000
-#define BCHP_XPT_FE_MINI_PID_PARSER14_TB_CTRL1_TB_PARSER_PID_CH_NUM_SHIFT 16
-#define BCHP_XPT_FE_MINI_PID_PARSER14_TB_CTRL1_TB_PARSER_PID_CH_NUM_DEFAULT 0x00000000
-
-/* XPT_FE :: MINI_PID_PARSER14_TB_CTRL1 :: reserved1 [15:15] */
-#define BCHP_XPT_FE_MINI_PID_PARSER14_TB_CTRL1_reserved1_MASK 0x00008000
-#define BCHP_XPT_FE_MINI_PID_PARSER14_TB_CTRL1_reserved1_SHIFT 15
-
-/* XPT_FE :: MINI_PID_PARSER14_TB_CTRL1 :: TBG_PRI_BAND_NUM [14:08] */
-#define BCHP_XPT_FE_MINI_PID_PARSER14_TB_CTRL1_TBG_PRI_BAND_NUM_MASK 0x00007f00
-#define BCHP_XPT_FE_MINI_PID_PARSER14_TB_CTRL1_TBG_PRI_BAND_NUM_SHIFT 8
-#define BCHP_XPT_FE_MINI_PID_PARSER14_TB_CTRL1_TBG_PRI_BAND_NUM_DEFAULT 0x00000000
-
-/* XPT_FE :: MINI_PID_PARSER14_TB_CTRL1 :: reserved2 [07:04] */
-#define BCHP_XPT_FE_MINI_PID_PARSER14_TB_CTRL1_reserved2_MASK 0x000000f0
-#define BCHP_XPT_FE_MINI_PID_PARSER14_TB_CTRL1_reserved2_SHIFT 4
-
-/* XPT_FE :: MINI_PID_PARSER14_TB_CTRL1 :: TB_SKIP_ADAP_PRIVATE_DATA_PARSING [03:03] */
-#define BCHP_XPT_FE_MINI_PID_PARSER14_TB_CTRL1_TB_SKIP_ADAP_PRIVATE_DATA_PARSING_MASK 0x00000008
-#define BCHP_XPT_FE_MINI_PID_PARSER14_TB_CTRL1_TB_SKIP_ADAP_PRIVATE_DATA_PARSING_SHIFT 3
-#define BCHP_XPT_FE_MINI_PID_PARSER14_TB_CTRL1_TB_SKIP_ADAP_PRIVATE_DATA_PARSING_DEFAULT 0x00000000
-
-/* XPT_FE :: MINI_PID_PARSER14_TB_CTRL1 :: TB_IGNORE_TS_PRIORITY [02:02] */
-#define BCHP_XPT_FE_MINI_PID_PARSER14_TB_CTRL1_TB_IGNORE_TS_PRIORITY_MASK 0x00000004
-#define BCHP_XPT_FE_MINI_PID_PARSER14_TB_CTRL1_TB_IGNORE_TS_PRIORITY_SHIFT 2
-#define BCHP_XPT_FE_MINI_PID_PARSER14_TB_CTRL1_TB_IGNORE_TS_PRIORITY_DEFAULT 0x00000000
-
-/* XPT_FE :: MINI_PID_PARSER14_TB_CTRL1 :: TB_DROP_BEF_FIRST_MARKER_PKT [01:01] */
-#define BCHP_XPT_FE_MINI_PID_PARSER14_TB_CTRL1_TB_DROP_BEF_FIRST_MARKER_PKT_MASK 0x00000002
-#define BCHP_XPT_FE_MINI_PID_PARSER14_TB_CTRL1_TB_DROP_BEF_FIRST_MARKER_PKT_SHIFT 1
-#define BCHP_XPT_FE_MINI_PID_PARSER14_TB_CTRL1_TB_DROP_BEF_FIRST_MARKER_PKT_DEFAULT 0x00000000
-
-/* XPT_FE :: MINI_PID_PARSER14_TB_CTRL1 :: TB_ENABLE [00:00] */
-#define BCHP_XPT_FE_MINI_PID_PARSER14_TB_CTRL1_TB_ENABLE_MASK 0x00000001
-#define BCHP_XPT_FE_MINI_PID_PARSER14_TB_CTRL1_TB_ENABLE_SHIFT 0
-#define BCHP_XPT_FE_MINI_PID_PARSER14_TB_CTRL1_TB_ENABLE_DEFAULT 0x00000000
-
-/***************************************************************************
- *MINI_PID_PARSER14_SYNC_COUNT - Data Transport Parser Band 14 Transponder Bonding Sync Counter Register
- ***************************************************************************/
-/* XPT_FE :: MINI_PID_PARSER14_SYNC_COUNT :: reserved0 [31:10] */
-#define BCHP_XPT_FE_MINI_PID_PARSER14_SYNC_COUNT_reserved0_MASK 0xfffffc00
-#define BCHP_XPT_FE_MINI_PID_PARSER14_SYNC_COUNT_reserved0_SHIFT 10
-
-/* XPT_FE :: MINI_PID_PARSER14_SYNC_COUNT :: SYNC_COUNT [09:00] */
-#define BCHP_XPT_FE_MINI_PID_PARSER14_SYNC_COUNT_SYNC_COUNT_MASK 0x000003ff
-#define BCHP_XPT_FE_MINI_PID_PARSER14_SYNC_COUNT_SYNC_COUNT_SHIFT 0
-#define BCHP_XPT_FE_MINI_PID_PARSER14_SYNC_COUNT_SYNC_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *MINI_PID_PARSER15_TB_CTRL1 - Data Transport Parser Band 15 Transponder Bonding Control Register
- ***************************************************************************/
-/* XPT_FE :: MINI_PID_PARSER15_TB_CTRL1 :: reserved0 [31:28] */
-#define BCHP_XPT_FE_MINI_PID_PARSER15_TB_CTRL1_reserved0_MASK 0xf0000000
-#define BCHP_XPT_FE_MINI_PID_PARSER15_TB_CTRL1_reserved0_SHIFT 28
-
-/* XPT_FE :: MINI_PID_PARSER15_TB_CTRL1 :: TB_PARSER_PID_CH_NUM [27:16] */
-#define BCHP_XPT_FE_MINI_PID_PARSER15_TB_CTRL1_TB_PARSER_PID_CH_NUM_MASK 0x0fff0000
-#define BCHP_XPT_FE_MINI_PID_PARSER15_TB_CTRL1_TB_PARSER_PID_CH_NUM_SHIFT 16
-#define BCHP_XPT_FE_MINI_PID_PARSER15_TB_CTRL1_TB_PARSER_PID_CH_NUM_DEFAULT 0x00000000
-
-/* XPT_FE :: MINI_PID_PARSER15_TB_CTRL1 :: reserved1 [15:15] */
-#define BCHP_XPT_FE_MINI_PID_PARSER15_TB_CTRL1_reserved1_MASK 0x00008000
-#define BCHP_XPT_FE_MINI_PID_PARSER15_TB_CTRL1_reserved1_SHIFT 15
-
-/* XPT_FE :: MINI_PID_PARSER15_TB_CTRL1 :: TBG_PRI_BAND_NUM [14:08] */
-#define BCHP_XPT_FE_MINI_PID_PARSER15_TB_CTRL1_TBG_PRI_BAND_NUM_MASK 0x00007f00
-#define BCHP_XPT_FE_MINI_PID_PARSER15_TB_CTRL1_TBG_PRI_BAND_NUM_SHIFT 8
-#define BCHP_XPT_FE_MINI_PID_PARSER15_TB_CTRL1_TBG_PRI_BAND_NUM_DEFAULT 0x00000000
-
-/* XPT_FE :: MINI_PID_PARSER15_TB_CTRL1 :: reserved2 [07:04] */
-#define BCHP_XPT_FE_MINI_PID_PARSER15_TB_CTRL1_reserved2_MASK 0x000000f0
-#define BCHP_XPT_FE_MINI_PID_PARSER15_TB_CTRL1_reserved2_SHIFT 4
-
-/* XPT_FE :: MINI_PID_PARSER15_TB_CTRL1 :: TB_SKIP_ADAP_PRIVATE_DATA_PARSING [03:03] */
-#define BCHP_XPT_FE_MINI_PID_PARSER15_TB_CTRL1_TB_SKIP_ADAP_PRIVATE_DATA_PARSING_MASK 0x00000008
-#define BCHP_XPT_FE_MINI_PID_PARSER15_TB_CTRL1_TB_SKIP_ADAP_PRIVATE_DATA_PARSING_SHIFT 3
-#define BCHP_XPT_FE_MINI_PID_PARSER15_TB_CTRL1_TB_SKIP_ADAP_PRIVATE_DATA_PARSING_DEFAULT 0x00000000
-
-/* XPT_FE :: MINI_PID_PARSER15_TB_CTRL1 :: TB_IGNORE_TS_PRIORITY [02:02] */
-#define BCHP_XPT_FE_MINI_PID_PARSER15_TB_CTRL1_TB_IGNORE_TS_PRIORITY_MASK 0x00000004
-#define BCHP_XPT_FE_MINI_PID_PARSER15_TB_CTRL1_TB_IGNORE_TS_PRIORITY_SHIFT 2
-#define BCHP_XPT_FE_MINI_PID_PARSER15_TB_CTRL1_TB_IGNORE_TS_PRIORITY_DEFAULT 0x00000000
-
-/* XPT_FE :: MINI_PID_PARSER15_TB_CTRL1 :: TB_DROP_BEF_FIRST_MARKER_PKT [01:01] */
-#define BCHP_XPT_FE_MINI_PID_PARSER15_TB_CTRL1_TB_DROP_BEF_FIRST_MARKER_PKT_MASK 0x00000002
-#define BCHP_XPT_FE_MINI_PID_PARSER15_TB_CTRL1_TB_DROP_BEF_FIRST_MARKER_PKT_SHIFT 1
-#define BCHP_XPT_FE_MINI_PID_PARSER15_TB_CTRL1_TB_DROP_BEF_FIRST_MARKER_PKT_DEFAULT 0x00000000
-
-/* XPT_FE :: MINI_PID_PARSER15_TB_CTRL1 :: TB_ENABLE [00:00] */
-#define BCHP_XPT_FE_MINI_PID_PARSER15_TB_CTRL1_TB_ENABLE_MASK 0x00000001
-#define BCHP_XPT_FE_MINI_PID_PARSER15_TB_CTRL1_TB_ENABLE_SHIFT 0
-#define BCHP_XPT_FE_MINI_PID_PARSER15_TB_CTRL1_TB_ENABLE_DEFAULT 0x00000000
-
-/***************************************************************************
- *MINI_PID_PARSER15_SYNC_COUNT - Data Transport Parser Band 15 Transponder Bonding Sync Counter Register
- ***************************************************************************/
-/* XPT_FE :: MINI_PID_PARSER15_SYNC_COUNT :: reserved0 [31:10] */
-#define BCHP_XPT_FE_MINI_PID_PARSER15_SYNC_COUNT_reserved0_MASK 0xfffffc00
-#define BCHP_XPT_FE_MINI_PID_PARSER15_SYNC_COUNT_reserved0_SHIFT 10
-
-/* XPT_FE :: MINI_PID_PARSER15_SYNC_COUNT :: SYNC_COUNT [09:00] */
-#define BCHP_XPT_FE_MINI_PID_PARSER15_SYNC_COUNT_SYNC_COUNT_MASK 0x000003ff
-#define BCHP_XPT_FE_MINI_PID_PARSER15_SYNC_COUNT_SYNC_COUNT_SHIFT 0
-#define BCHP_XPT_FE_MINI_PID_PARSER15_SYNC_COUNT_SYNC_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *MINI_PID_PARSER16_TB_CTRL1 - Data Transport Parser Band 16 Transponder Bonding Control Register
- ***************************************************************************/
-/* XPT_FE :: MINI_PID_PARSER16_TB_CTRL1 :: reserved0 [31:28] */
-#define BCHP_XPT_FE_MINI_PID_PARSER16_TB_CTRL1_reserved0_MASK 0xf0000000
-#define BCHP_XPT_FE_MINI_PID_PARSER16_TB_CTRL1_reserved0_SHIFT 28
-
-/* XPT_FE :: MINI_PID_PARSER16_TB_CTRL1 :: TB_PARSER_PID_CH_NUM [27:16] */
-#define BCHP_XPT_FE_MINI_PID_PARSER16_TB_CTRL1_TB_PARSER_PID_CH_NUM_MASK 0x0fff0000
-#define BCHP_XPT_FE_MINI_PID_PARSER16_TB_CTRL1_TB_PARSER_PID_CH_NUM_SHIFT 16
-#define BCHP_XPT_FE_MINI_PID_PARSER16_TB_CTRL1_TB_PARSER_PID_CH_NUM_DEFAULT 0x00000000
-
-/* XPT_FE :: MINI_PID_PARSER16_TB_CTRL1 :: reserved1 [15:15] */
-#define BCHP_XPT_FE_MINI_PID_PARSER16_TB_CTRL1_reserved1_MASK 0x00008000
-#define BCHP_XPT_FE_MINI_PID_PARSER16_TB_CTRL1_reserved1_SHIFT 15
-
-/* XPT_FE :: MINI_PID_PARSER16_TB_CTRL1 :: TBG_PRI_BAND_NUM [14:08] */
-#define BCHP_XPT_FE_MINI_PID_PARSER16_TB_CTRL1_TBG_PRI_BAND_NUM_MASK 0x00007f00
-#define BCHP_XPT_FE_MINI_PID_PARSER16_TB_CTRL1_TBG_PRI_BAND_NUM_SHIFT 8
-#define BCHP_XPT_FE_MINI_PID_PARSER16_TB_CTRL1_TBG_PRI_BAND_NUM_DEFAULT 0x00000000
-
-/* XPT_FE :: MINI_PID_PARSER16_TB_CTRL1 :: reserved2 [07:04] */
-#define BCHP_XPT_FE_MINI_PID_PARSER16_TB_CTRL1_reserved2_MASK 0x000000f0
-#define BCHP_XPT_FE_MINI_PID_PARSER16_TB_CTRL1_reserved2_SHIFT 4
-
-/* XPT_FE :: MINI_PID_PARSER16_TB_CTRL1 :: TB_SKIP_ADAP_PRIVATE_DATA_PARSING [03:03] */
-#define BCHP_XPT_FE_MINI_PID_PARSER16_TB_CTRL1_TB_SKIP_ADAP_PRIVATE_DATA_PARSING_MASK 0x00000008
-#define BCHP_XPT_FE_MINI_PID_PARSER16_TB_CTRL1_TB_SKIP_ADAP_PRIVATE_DATA_PARSING_SHIFT 3
-#define BCHP_XPT_FE_MINI_PID_PARSER16_TB_CTRL1_TB_SKIP_ADAP_PRIVATE_DATA_PARSING_DEFAULT 0x00000000
-
-/* XPT_FE :: MINI_PID_PARSER16_TB_CTRL1 :: TB_IGNORE_TS_PRIORITY [02:02] */
-#define BCHP_XPT_FE_MINI_PID_PARSER16_TB_CTRL1_TB_IGNORE_TS_PRIORITY_MASK 0x00000004
-#define BCHP_XPT_FE_MINI_PID_PARSER16_TB_CTRL1_TB_IGNORE_TS_PRIORITY_SHIFT 2
-#define BCHP_XPT_FE_MINI_PID_PARSER16_TB_CTRL1_TB_IGNORE_TS_PRIORITY_DEFAULT 0x00000000
-
-/* XPT_FE :: MINI_PID_PARSER16_TB_CTRL1 :: TB_DROP_BEF_FIRST_MARKER_PKT [01:01] */
-#define BCHP_XPT_FE_MINI_PID_PARSER16_TB_CTRL1_TB_DROP_BEF_FIRST_MARKER_PKT_MASK 0x00000002
-#define BCHP_XPT_FE_MINI_PID_PARSER16_TB_CTRL1_TB_DROP_BEF_FIRST_MARKER_PKT_SHIFT 1
-#define BCHP_XPT_FE_MINI_PID_PARSER16_TB_CTRL1_TB_DROP_BEF_FIRST_MARKER_PKT_DEFAULT 0x00000000
-
-/* XPT_FE :: MINI_PID_PARSER16_TB_CTRL1 :: TB_ENABLE [00:00] */
-#define BCHP_XPT_FE_MINI_PID_PARSER16_TB_CTRL1_TB_ENABLE_MASK 0x00000001
-#define BCHP_XPT_FE_MINI_PID_PARSER16_TB_CTRL1_TB_ENABLE_SHIFT 0
-#define BCHP_XPT_FE_MINI_PID_PARSER16_TB_CTRL1_TB_ENABLE_DEFAULT 0x00000000
-
-/***************************************************************************
- *MINI_PID_PARSER16_SYNC_COUNT - Data Transport Parser Band 16 Transponder Bonding Sync Counter Register
- ***************************************************************************/
-/* XPT_FE :: MINI_PID_PARSER16_SYNC_COUNT :: reserved0 [31:10] */
-#define BCHP_XPT_FE_MINI_PID_PARSER16_SYNC_COUNT_reserved0_MASK 0xfffffc00
-#define BCHP_XPT_FE_MINI_PID_PARSER16_SYNC_COUNT_reserved0_SHIFT 10
-
-/* XPT_FE :: MINI_PID_PARSER16_SYNC_COUNT :: SYNC_COUNT [09:00] */
-#define BCHP_XPT_FE_MINI_PID_PARSER16_SYNC_COUNT_SYNC_COUNT_MASK 0x000003ff
-#define BCHP_XPT_FE_MINI_PID_PARSER16_SYNC_COUNT_SYNC_COUNT_SHIFT 0
-#define BCHP_XPT_FE_MINI_PID_PARSER16_SYNC_COUNT_SYNC_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *MINI_PID_PARSER17_TB_CTRL1 - Data Transport Parser Band 17 Transponder Bonding Control Register
- ***************************************************************************/
-/* XPT_FE :: MINI_PID_PARSER17_TB_CTRL1 :: reserved0 [31:28] */
-#define BCHP_XPT_FE_MINI_PID_PARSER17_TB_CTRL1_reserved0_MASK 0xf0000000
-#define BCHP_XPT_FE_MINI_PID_PARSER17_TB_CTRL1_reserved0_SHIFT 28
-
-/* XPT_FE :: MINI_PID_PARSER17_TB_CTRL1 :: TB_PARSER_PID_CH_NUM [27:16] */
-#define BCHP_XPT_FE_MINI_PID_PARSER17_TB_CTRL1_TB_PARSER_PID_CH_NUM_MASK 0x0fff0000
-#define BCHP_XPT_FE_MINI_PID_PARSER17_TB_CTRL1_TB_PARSER_PID_CH_NUM_SHIFT 16
-#define BCHP_XPT_FE_MINI_PID_PARSER17_TB_CTRL1_TB_PARSER_PID_CH_NUM_DEFAULT 0x00000000
-
-/* XPT_FE :: MINI_PID_PARSER17_TB_CTRL1 :: reserved1 [15:15] */
-#define BCHP_XPT_FE_MINI_PID_PARSER17_TB_CTRL1_reserved1_MASK 0x00008000
-#define BCHP_XPT_FE_MINI_PID_PARSER17_TB_CTRL1_reserved1_SHIFT 15
-
-/* XPT_FE :: MINI_PID_PARSER17_TB_CTRL1 :: TBG_PRI_BAND_NUM [14:08] */
-#define BCHP_XPT_FE_MINI_PID_PARSER17_TB_CTRL1_TBG_PRI_BAND_NUM_MASK 0x00007f00
-#define BCHP_XPT_FE_MINI_PID_PARSER17_TB_CTRL1_TBG_PRI_BAND_NUM_SHIFT 8
-#define BCHP_XPT_FE_MINI_PID_PARSER17_TB_CTRL1_TBG_PRI_BAND_NUM_DEFAULT 0x00000000
-
-/* XPT_FE :: MINI_PID_PARSER17_TB_CTRL1 :: reserved2 [07:04] */
-#define BCHP_XPT_FE_MINI_PID_PARSER17_TB_CTRL1_reserved2_MASK 0x000000f0
-#define BCHP_XPT_FE_MINI_PID_PARSER17_TB_CTRL1_reserved2_SHIFT 4
-
-/* XPT_FE :: MINI_PID_PARSER17_TB_CTRL1 :: TB_SKIP_ADAP_PRIVATE_DATA_PARSING [03:03] */
-#define BCHP_XPT_FE_MINI_PID_PARSER17_TB_CTRL1_TB_SKIP_ADAP_PRIVATE_DATA_PARSING_MASK 0x00000008
-#define BCHP_XPT_FE_MINI_PID_PARSER17_TB_CTRL1_TB_SKIP_ADAP_PRIVATE_DATA_PARSING_SHIFT 3
-#define BCHP_XPT_FE_MINI_PID_PARSER17_TB_CTRL1_TB_SKIP_ADAP_PRIVATE_DATA_PARSING_DEFAULT 0x00000000
-
-/* XPT_FE :: MINI_PID_PARSER17_TB_CTRL1 :: TB_IGNORE_TS_PRIORITY [02:02] */
-#define BCHP_XPT_FE_MINI_PID_PARSER17_TB_CTRL1_TB_IGNORE_TS_PRIORITY_MASK 0x00000004
-#define BCHP_XPT_FE_MINI_PID_PARSER17_TB_CTRL1_TB_IGNORE_TS_PRIORITY_SHIFT 2
-#define BCHP_XPT_FE_MINI_PID_PARSER17_TB_CTRL1_TB_IGNORE_TS_PRIORITY_DEFAULT 0x00000000
-
-/* XPT_FE :: MINI_PID_PARSER17_TB_CTRL1 :: TB_DROP_BEF_FIRST_MARKER_PKT [01:01] */
-#define BCHP_XPT_FE_MINI_PID_PARSER17_TB_CTRL1_TB_DROP_BEF_FIRST_MARKER_PKT_MASK 0x00000002
-#define BCHP_XPT_FE_MINI_PID_PARSER17_TB_CTRL1_TB_DROP_BEF_FIRST_MARKER_PKT_SHIFT 1
-#define BCHP_XPT_FE_MINI_PID_PARSER17_TB_CTRL1_TB_DROP_BEF_FIRST_MARKER_PKT_DEFAULT 0x00000000
-
-/* XPT_FE :: MINI_PID_PARSER17_TB_CTRL1 :: TB_ENABLE [00:00] */
-#define BCHP_XPT_FE_MINI_PID_PARSER17_TB_CTRL1_TB_ENABLE_MASK 0x00000001
-#define BCHP_XPT_FE_MINI_PID_PARSER17_TB_CTRL1_TB_ENABLE_SHIFT 0
-#define BCHP_XPT_FE_MINI_PID_PARSER17_TB_CTRL1_TB_ENABLE_DEFAULT 0x00000000
-
-/***************************************************************************
- *MINI_PID_PARSER17_SYNC_COUNT - Data Transport Parser Band 17 Transponder Bonding Sync Counter Register
- ***************************************************************************/
-/* XPT_FE :: MINI_PID_PARSER17_SYNC_COUNT :: reserved0 [31:10] */
-#define BCHP_XPT_FE_MINI_PID_PARSER17_SYNC_COUNT_reserved0_MASK 0xfffffc00
-#define BCHP_XPT_FE_MINI_PID_PARSER17_SYNC_COUNT_reserved0_SHIFT 10
-
-/* XPT_FE :: MINI_PID_PARSER17_SYNC_COUNT :: SYNC_COUNT [09:00] */
-#define BCHP_XPT_FE_MINI_PID_PARSER17_SYNC_COUNT_SYNC_COUNT_MASK 0x000003ff
-#define BCHP_XPT_FE_MINI_PID_PARSER17_SYNC_COUNT_SYNC_COUNT_SHIFT 0
-#define BCHP_XPT_FE_MINI_PID_PARSER17_SYNC_COUNT_SYNC_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *MINI_PID_PARSER18_TB_CTRL1 - Data Transport Parser Band 18 Transponder Bonding Control Register
- ***************************************************************************/
-/* XPT_FE :: MINI_PID_PARSER18_TB_CTRL1 :: reserved0 [31:28] */
-#define BCHP_XPT_FE_MINI_PID_PARSER18_TB_CTRL1_reserved0_MASK 0xf0000000
-#define BCHP_XPT_FE_MINI_PID_PARSER18_TB_CTRL1_reserved0_SHIFT 28
-
-/* XPT_FE :: MINI_PID_PARSER18_TB_CTRL1 :: TB_PARSER_PID_CH_NUM [27:16] */
-#define BCHP_XPT_FE_MINI_PID_PARSER18_TB_CTRL1_TB_PARSER_PID_CH_NUM_MASK 0x0fff0000
-#define BCHP_XPT_FE_MINI_PID_PARSER18_TB_CTRL1_TB_PARSER_PID_CH_NUM_SHIFT 16
-#define BCHP_XPT_FE_MINI_PID_PARSER18_TB_CTRL1_TB_PARSER_PID_CH_NUM_DEFAULT 0x00000000
-
-/* XPT_FE :: MINI_PID_PARSER18_TB_CTRL1 :: reserved1 [15:15] */
-#define BCHP_XPT_FE_MINI_PID_PARSER18_TB_CTRL1_reserved1_MASK 0x00008000
-#define BCHP_XPT_FE_MINI_PID_PARSER18_TB_CTRL1_reserved1_SHIFT 15
-
-/* XPT_FE :: MINI_PID_PARSER18_TB_CTRL1 :: TBG_PRI_BAND_NUM [14:08] */
-#define BCHP_XPT_FE_MINI_PID_PARSER18_TB_CTRL1_TBG_PRI_BAND_NUM_MASK 0x00007f00
-#define BCHP_XPT_FE_MINI_PID_PARSER18_TB_CTRL1_TBG_PRI_BAND_NUM_SHIFT 8
-#define BCHP_XPT_FE_MINI_PID_PARSER18_TB_CTRL1_TBG_PRI_BAND_NUM_DEFAULT 0x00000000
-
-/* XPT_FE :: MINI_PID_PARSER18_TB_CTRL1 :: reserved2 [07:04] */
-#define BCHP_XPT_FE_MINI_PID_PARSER18_TB_CTRL1_reserved2_MASK 0x000000f0
-#define BCHP_XPT_FE_MINI_PID_PARSER18_TB_CTRL1_reserved2_SHIFT 4
-
-/* XPT_FE :: MINI_PID_PARSER18_TB_CTRL1 :: TB_SKIP_ADAP_PRIVATE_DATA_PARSING [03:03] */
-#define BCHP_XPT_FE_MINI_PID_PARSER18_TB_CTRL1_TB_SKIP_ADAP_PRIVATE_DATA_PARSING_MASK 0x00000008
-#define BCHP_XPT_FE_MINI_PID_PARSER18_TB_CTRL1_TB_SKIP_ADAP_PRIVATE_DATA_PARSING_SHIFT 3
-#define BCHP_XPT_FE_MINI_PID_PARSER18_TB_CTRL1_TB_SKIP_ADAP_PRIVATE_DATA_PARSING_DEFAULT 0x00000000
-
-/* XPT_FE :: MINI_PID_PARSER18_TB_CTRL1 :: TB_IGNORE_TS_PRIORITY [02:02] */
-#define BCHP_XPT_FE_MINI_PID_PARSER18_TB_CTRL1_TB_IGNORE_TS_PRIORITY_MASK 0x00000004
-#define BCHP_XPT_FE_MINI_PID_PARSER18_TB_CTRL1_TB_IGNORE_TS_PRIORITY_SHIFT 2
-#define BCHP_XPT_FE_MINI_PID_PARSER18_TB_CTRL1_TB_IGNORE_TS_PRIORITY_DEFAULT 0x00000000
-
-/* XPT_FE :: MINI_PID_PARSER18_TB_CTRL1 :: TB_DROP_BEF_FIRST_MARKER_PKT [01:01] */
-#define BCHP_XPT_FE_MINI_PID_PARSER18_TB_CTRL1_TB_DROP_BEF_FIRST_MARKER_PKT_MASK 0x00000002
-#define BCHP_XPT_FE_MINI_PID_PARSER18_TB_CTRL1_TB_DROP_BEF_FIRST_MARKER_PKT_SHIFT 1
-#define BCHP_XPT_FE_MINI_PID_PARSER18_TB_CTRL1_TB_DROP_BEF_FIRST_MARKER_PKT_DEFAULT 0x00000000
-
-/* XPT_FE :: MINI_PID_PARSER18_TB_CTRL1 :: TB_ENABLE [00:00] */
-#define BCHP_XPT_FE_MINI_PID_PARSER18_TB_CTRL1_TB_ENABLE_MASK 0x00000001
-#define BCHP_XPT_FE_MINI_PID_PARSER18_TB_CTRL1_TB_ENABLE_SHIFT 0
-#define BCHP_XPT_FE_MINI_PID_PARSER18_TB_CTRL1_TB_ENABLE_DEFAULT 0x00000000
-
-/***************************************************************************
- *MINI_PID_PARSER18_SYNC_COUNT - Data Transport Parser Band 18 Transponder Bonding Sync Counter Register
- ***************************************************************************/
-/* XPT_FE :: MINI_PID_PARSER18_SYNC_COUNT :: reserved0 [31:10] */
-#define BCHP_XPT_FE_MINI_PID_PARSER18_SYNC_COUNT_reserved0_MASK 0xfffffc00
-#define BCHP_XPT_FE_MINI_PID_PARSER18_SYNC_COUNT_reserved0_SHIFT 10
-
-/* XPT_FE :: MINI_PID_PARSER18_SYNC_COUNT :: SYNC_COUNT [09:00] */
-#define BCHP_XPT_FE_MINI_PID_PARSER18_SYNC_COUNT_SYNC_COUNT_MASK 0x000003ff
-#define BCHP_XPT_FE_MINI_PID_PARSER18_SYNC_COUNT_SYNC_COUNT_SHIFT 0
-#define BCHP_XPT_FE_MINI_PID_PARSER18_SYNC_COUNT_SYNC_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *MINI_PID_PARSER19_TB_CTRL1 - Data Transport Parser Band 19 Transponder Bonding Control Register
- ***************************************************************************/
-/* XPT_FE :: MINI_PID_PARSER19_TB_CTRL1 :: reserved0 [31:28] */
-#define BCHP_XPT_FE_MINI_PID_PARSER19_TB_CTRL1_reserved0_MASK 0xf0000000
-#define BCHP_XPT_FE_MINI_PID_PARSER19_TB_CTRL1_reserved0_SHIFT 28
-
-/* XPT_FE :: MINI_PID_PARSER19_TB_CTRL1 :: TB_PARSER_PID_CH_NUM [27:16] */
-#define BCHP_XPT_FE_MINI_PID_PARSER19_TB_CTRL1_TB_PARSER_PID_CH_NUM_MASK 0x0fff0000
-#define BCHP_XPT_FE_MINI_PID_PARSER19_TB_CTRL1_TB_PARSER_PID_CH_NUM_SHIFT 16
-#define BCHP_XPT_FE_MINI_PID_PARSER19_TB_CTRL1_TB_PARSER_PID_CH_NUM_DEFAULT 0x00000000
-
-/* XPT_FE :: MINI_PID_PARSER19_TB_CTRL1 :: reserved1 [15:15] */
-#define BCHP_XPT_FE_MINI_PID_PARSER19_TB_CTRL1_reserved1_MASK 0x00008000
-#define BCHP_XPT_FE_MINI_PID_PARSER19_TB_CTRL1_reserved1_SHIFT 15
-
-/* XPT_FE :: MINI_PID_PARSER19_TB_CTRL1 :: TBG_PRI_BAND_NUM [14:08] */
-#define BCHP_XPT_FE_MINI_PID_PARSER19_TB_CTRL1_TBG_PRI_BAND_NUM_MASK 0x00007f00
-#define BCHP_XPT_FE_MINI_PID_PARSER19_TB_CTRL1_TBG_PRI_BAND_NUM_SHIFT 8
-#define BCHP_XPT_FE_MINI_PID_PARSER19_TB_CTRL1_TBG_PRI_BAND_NUM_DEFAULT 0x00000000
-
-/* XPT_FE :: MINI_PID_PARSER19_TB_CTRL1 :: reserved2 [07:04] */
-#define BCHP_XPT_FE_MINI_PID_PARSER19_TB_CTRL1_reserved2_MASK 0x000000f0
-#define BCHP_XPT_FE_MINI_PID_PARSER19_TB_CTRL1_reserved2_SHIFT 4
-
-/* XPT_FE :: MINI_PID_PARSER19_TB_CTRL1 :: TB_SKIP_ADAP_PRIVATE_DATA_PARSING [03:03] */
-#define BCHP_XPT_FE_MINI_PID_PARSER19_TB_CTRL1_TB_SKIP_ADAP_PRIVATE_DATA_PARSING_MASK 0x00000008
-#define BCHP_XPT_FE_MINI_PID_PARSER19_TB_CTRL1_TB_SKIP_ADAP_PRIVATE_DATA_PARSING_SHIFT 3
-#define BCHP_XPT_FE_MINI_PID_PARSER19_TB_CTRL1_TB_SKIP_ADAP_PRIVATE_DATA_PARSING_DEFAULT 0x00000000
-
-/* XPT_FE :: MINI_PID_PARSER19_TB_CTRL1 :: TB_IGNORE_TS_PRIORITY [02:02] */
-#define BCHP_XPT_FE_MINI_PID_PARSER19_TB_CTRL1_TB_IGNORE_TS_PRIORITY_MASK 0x00000004
-#define BCHP_XPT_FE_MINI_PID_PARSER19_TB_CTRL1_TB_IGNORE_TS_PRIORITY_SHIFT 2
-#define BCHP_XPT_FE_MINI_PID_PARSER19_TB_CTRL1_TB_IGNORE_TS_PRIORITY_DEFAULT 0x00000000
-
-/* XPT_FE :: MINI_PID_PARSER19_TB_CTRL1 :: TB_DROP_BEF_FIRST_MARKER_PKT [01:01] */
-#define BCHP_XPT_FE_MINI_PID_PARSER19_TB_CTRL1_TB_DROP_BEF_FIRST_MARKER_PKT_MASK 0x00000002
-#define BCHP_XPT_FE_MINI_PID_PARSER19_TB_CTRL1_TB_DROP_BEF_FIRST_MARKER_PKT_SHIFT 1
-#define BCHP_XPT_FE_MINI_PID_PARSER19_TB_CTRL1_TB_DROP_BEF_FIRST_MARKER_PKT_DEFAULT 0x00000000
-
-/* XPT_FE :: MINI_PID_PARSER19_TB_CTRL1 :: TB_ENABLE [00:00] */
-#define BCHP_XPT_FE_MINI_PID_PARSER19_TB_CTRL1_TB_ENABLE_MASK 0x00000001
-#define BCHP_XPT_FE_MINI_PID_PARSER19_TB_CTRL1_TB_ENABLE_SHIFT 0
-#define BCHP_XPT_FE_MINI_PID_PARSER19_TB_CTRL1_TB_ENABLE_DEFAULT 0x00000000
-
-/***************************************************************************
- *MINI_PID_PARSER19_SYNC_COUNT - Data Transport Parser Band 19 Transponder Bonding Sync Counter Register
- ***************************************************************************/
-/* XPT_FE :: MINI_PID_PARSER19_SYNC_COUNT :: reserved0 [31:10] */
-#define BCHP_XPT_FE_MINI_PID_PARSER19_SYNC_COUNT_reserved0_MASK 0xfffffc00
-#define BCHP_XPT_FE_MINI_PID_PARSER19_SYNC_COUNT_reserved0_SHIFT 10
-
-/* XPT_FE :: MINI_PID_PARSER19_SYNC_COUNT :: SYNC_COUNT [09:00] */
-#define BCHP_XPT_FE_MINI_PID_PARSER19_SYNC_COUNT_SYNC_COUNT_MASK 0x000003ff
-#define BCHP_XPT_FE_MINI_PID_PARSER19_SYNC_COUNT_SYNC_COUNT_SHIFT 0
-#define BCHP_XPT_FE_MINI_PID_PARSER19_SYNC_COUNT_SYNC_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *MINI_PID_PARSER20_TB_CTRL1 - Data Transport Parser Band 20 Transponder Bonding Control Register
- ***************************************************************************/
-/* XPT_FE :: MINI_PID_PARSER20_TB_CTRL1 :: reserved0 [31:28] */
-#define BCHP_XPT_FE_MINI_PID_PARSER20_TB_CTRL1_reserved0_MASK 0xf0000000
-#define BCHP_XPT_FE_MINI_PID_PARSER20_TB_CTRL1_reserved0_SHIFT 28
-
-/* XPT_FE :: MINI_PID_PARSER20_TB_CTRL1 :: TB_PARSER_PID_CH_NUM [27:16] */
-#define BCHP_XPT_FE_MINI_PID_PARSER20_TB_CTRL1_TB_PARSER_PID_CH_NUM_MASK 0x0fff0000
-#define BCHP_XPT_FE_MINI_PID_PARSER20_TB_CTRL1_TB_PARSER_PID_CH_NUM_SHIFT 16
-#define BCHP_XPT_FE_MINI_PID_PARSER20_TB_CTRL1_TB_PARSER_PID_CH_NUM_DEFAULT 0x00000000
-
-/* XPT_FE :: MINI_PID_PARSER20_TB_CTRL1 :: reserved1 [15:15] */
-#define BCHP_XPT_FE_MINI_PID_PARSER20_TB_CTRL1_reserved1_MASK 0x00008000
-#define BCHP_XPT_FE_MINI_PID_PARSER20_TB_CTRL1_reserved1_SHIFT 15
-
-/* XPT_FE :: MINI_PID_PARSER20_TB_CTRL1 :: TBG_PRI_BAND_NUM [14:08] */
-#define BCHP_XPT_FE_MINI_PID_PARSER20_TB_CTRL1_TBG_PRI_BAND_NUM_MASK 0x00007f00
-#define BCHP_XPT_FE_MINI_PID_PARSER20_TB_CTRL1_TBG_PRI_BAND_NUM_SHIFT 8
-#define BCHP_XPT_FE_MINI_PID_PARSER20_TB_CTRL1_TBG_PRI_BAND_NUM_DEFAULT 0x00000000
-
-/* XPT_FE :: MINI_PID_PARSER20_TB_CTRL1 :: reserved2 [07:04] */
-#define BCHP_XPT_FE_MINI_PID_PARSER20_TB_CTRL1_reserved2_MASK 0x000000f0
-#define BCHP_XPT_FE_MINI_PID_PARSER20_TB_CTRL1_reserved2_SHIFT 4
-
-/* XPT_FE :: MINI_PID_PARSER20_TB_CTRL1 :: TB_SKIP_ADAP_PRIVATE_DATA_PARSING [03:03] */
-#define BCHP_XPT_FE_MINI_PID_PARSER20_TB_CTRL1_TB_SKIP_ADAP_PRIVATE_DATA_PARSING_MASK 0x00000008
-#define BCHP_XPT_FE_MINI_PID_PARSER20_TB_CTRL1_TB_SKIP_ADAP_PRIVATE_DATA_PARSING_SHIFT 3
-#define BCHP_XPT_FE_MINI_PID_PARSER20_TB_CTRL1_TB_SKIP_ADAP_PRIVATE_DATA_PARSING_DEFAULT 0x00000000
-
-/* XPT_FE :: MINI_PID_PARSER20_TB_CTRL1 :: TB_IGNORE_TS_PRIORITY [02:02] */
-#define BCHP_XPT_FE_MINI_PID_PARSER20_TB_CTRL1_TB_IGNORE_TS_PRIORITY_MASK 0x00000004
-#define BCHP_XPT_FE_MINI_PID_PARSER20_TB_CTRL1_TB_IGNORE_TS_PRIORITY_SHIFT 2
-#define BCHP_XPT_FE_MINI_PID_PARSER20_TB_CTRL1_TB_IGNORE_TS_PRIORITY_DEFAULT 0x00000000
-
-/* XPT_FE :: MINI_PID_PARSER20_TB_CTRL1 :: TB_DROP_BEF_FIRST_MARKER_PKT [01:01] */
-#define BCHP_XPT_FE_MINI_PID_PARSER20_TB_CTRL1_TB_DROP_BEF_FIRST_MARKER_PKT_MASK 0x00000002
-#define BCHP_XPT_FE_MINI_PID_PARSER20_TB_CTRL1_TB_DROP_BEF_FIRST_MARKER_PKT_SHIFT 1
-#define BCHP_XPT_FE_MINI_PID_PARSER20_TB_CTRL1_TB_DROP_BEF_FIRST_MARKER_PKT_DEFAULT 0x00000000
-
-/* XPT_FE :: MINI_PID_PARSER20_TB_CTRL1 :: TB_ENABLE [00:00] */
-#define BCHP_XPT_FE_MINI_PID_PARSER20_TB_CTRL1_TB_ENABLE_MASK 0x00000001
-#define BCHP_XPT_FE_MINI_PID_PARSER20_TB_CTRL1_TB_ENABLE_SHIFT 0
-#define BCHP_XPT_FE_MINI_PID_PARSER20_TB_CTRL1_TB_ENABLE_DEFAULT 0x00000000
-
-/***************************************************************************
- *MINI_PID_PARSER20_SYNC_COUNT - Data Transport Parser Band 20 Transponder Bonding Sync Counter Register
- ***************************************************************************/
-/* XPT_FE :: MINI_PID_PARSER20_SYNC_COUNT :: reserved0 [31:10] */
-#define BCHP_XPT_FE_MINI_PID_PARSER20_SYNC_COUNT_reserved0_MASK 0xfffffc00
-#define BCHP_XPT_FE_MINI_PID_PARSER20_SYNC_COUNT_reserved0_SHIFT 10
-
-/* XPT_FE :: MINI_PID_PARSER20_SYNC_COUNT :: SYNC_COUNT [09:00] */
-#define BCHP_XPT_FE_MINI_PID_PARSER20_SYNC_COUNT_SYNC_COUNT_MASK 0x000003ff
-#define BCHP_XPT_FE_MINI_PID_PARSER20_SYNC_COUNT_SYNC_COUNT_SHIFT 0
-#define BCHP_XPT_FE_MINI_PID_PARSER20_SYNC_COUNT_SYNC_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *MINI_PID_PARSER21_TB_CTRL1 - Data Transport Parser Band 21 Transponder Bonding Control Register
- ***************************************************************************/
-/* XPT_FE :: MINI_PID_PARSER21_TB_CTRL1 :: reserved0 [31:28] */
-#define BCHP_XPT_FE_MINI_PID_PARSER21_TB_CTRL1_reserved0_MASK 0xf0000000
-#define BCHP_XPT_FE_MINI_PID_PARSER21_TB_CTRL1_reserved0_SHIFT 28
-
-/* XPT_FE :: MINI_PID_PARSER21_TB_CTRL1 :: TB_PARSER_PID_CH_NUM [27:16] */
-#define BCHP_XPT_FE_MINI_PID_PARSER21_TB_CTRL1_TB_PARSER_PID_CH_NUM_MASK 0x0fff0000
-#define BCHP_XPT_FE_MINI_PID_PARSER21_TB_CTRL1_TB_PARSER_PID_CH_NUM_SHIFT 16
-#define BCHP_XPT_FE_MINI_PID_PARSER21_TB_CTRL1_TB_PARSER_PID_CH_NUM_DEFAULT 0x00000000
-
-/* XPT_FE :: MINI_PID_PARSER21_TB_CTRL1 :: reserved1 [15:15] */
-#define BCHP_XPT_FE_MINI_PID_PARSER21_TB_CTRL1_reserved1_MASK 0x00008000
-#define BCHP_XPT_FE_MINI_PID_PARSER21_TB_CTRL1_reserved1_SHIFT 15
-
-/* XPT_FE :: MINI_PID_PARSER21_TB_CTRL1 :: TBG_PRI_BAND_NUM [14:08] */
-#define BCHP_XPT_FE_MINI_PID_PARSER21_TB_CTRL1_TBG_PRI_BAND_NUM_MASK 0x00007f00
-#define BCHP_XPT_FE_MINI_PID_PARSER21_TB_CTRL1_TBG_PRI_BAND_NUM_SHIFT 8
-#define BCHP_XPT_FE_MINI_PID_PARSER21_TB_CTRL1_TBG_PRI_BAND_NUM_DEFAULT 0x00000000
-
-/* XPT_FE :: MINI_PID_PARSER21_TB_CTRL1 :: reserved2 [07:04] */
-#define BCHP_XPT_FE_MINI_PID_PARSER21_TB_CTRL1_reserved2_MASK 0x000000f0
-#define BCHP_XPT_FE_MINI_PID_PARSER21_TB_CTRL1_reserved2_SHIFT 4
-
-/* XPT_FE :: MINI_PID_PARSER21_TB_CTRL1 :: TB_SKIP_ADAP_PRIVATE_DATA_PARSING [03:03] */
-#define BCHP_XPT_FE_MINI_PID_PARSER21_TB_CTRL1_TB_SKIP_ADAP_PRIVATE_DATA_PARSING_MASK 0x00000008
-#define BCHP_XPT_FE_MINI_PID_PARSER21_TB_CTRL1_TB_SKIP_ADAP_PRIVATE_DATA_PARSING_SHIFT 3
-#define BCHP_XPT_FE_MINI_PID_PARSER21_TB_CTRL1_TB_SKIP_ADAP_PRIVATE_DATA_PARSING_DEFAULT 0x00000000
-
-/* XPT_FE :: MINI_PID_PARSER21_TB_CTRL1 :: TB_IGNORE_TS_PRIORITY [02:02] */
-#define BCHP_XPT_FE_MINI_PID_PARSER21_TB_CTRL1_TB_IGNORE_TS_PRIORITY_MASK 0x00000004
-#define BCHP_XPT_FE_MINI_PID_PARSER21_TB_CTRL1_TB_IGNORE_TS_PRIORITY_SHIFT 2
-#define BCHP_XPT_FE_MINI_PID_PARSER21_TB_CTRL1_TB_IGNORE_TS_PRIORITY_DEFAULT 0x00000000
-
-/* XPT_FE :: MINI_PID_PARSER21_TB_CTRL1 :: TB_DROP_BEF_FIRST_MARKER_PKT [01:01] */
-#define BCHP_XPT_FE_MINI_PID_PARSER21_TB_CTRL1_TB_DROP_BEF_FIRST_MARKER_PKT_MASK 0x00000002
-#define BCHP_XPT_FE_MINI_PID_PARSER21_TB_CTRL1_TB_DROP_BEF_FIRST_MARKER_PKT_SHIFT 1
-#define BCHP_XPT_FE_MINI_PID_PARSER21_TB_CTRL1_TB_DROP_BEF_FIRST_MARKER_PKT_DEFAULT 0x00000000
-
-/* XPT_FE :: MINI_PID_PARSER21_TB_CTRL1 :: TB_ENABLE [00:00] */
-#define BCHP_XPT_FE_MINI_PID_PARSER21_TB_CTRL1_TB_ENABLE_MASK 0x00000001
-#define BCHP_XPT_FE_MINI_PID_PARSER21_TB_CTRL1_TB_ENABLE_SHIFT 0
-#define BCHP_XPT_FE_MINI_PID_PARSER21_TB_CTRL1_TB_ENABLE_DEFAULT 0x00000000
-
-/***************************************************************************
- *MINI_PID_PARSER21_SYNC_COUNT - Data Transport Parser Band 21 Transponder Bonding Sync Counter Register
- ***************************************************************************/
-/* XPT_FE :: MINI_PID_PARSER21_SYNC_COUNT :: reserved0 [31:10] */
-#define BCHP_XPT_FE_MINI_PID_PARSER21_SYNC_COUNT_reserved0_MASK 0xfffffc00
-#define BCHP_XPT_FE_MINI_PID_PARSER21_SYNC_COUNT_reserved0_SHIFT 10
-
-/* XPT_FE :: MINI_PID_PARSER21_SYNC_COUNT :: SYNC_COUNT [09:00] */
-#define BCHP_XPT_FE_MINI_PID_PARSER21_SYNC_COUNT_SYNC_COUNT_MASK 0x000003ff
-#define BCHP_XPT_FE_MINI_PID_PARSER21_SYNC_COUNT_SYNC_COUNT_SHIFT 0
-#define BCHP_XPT_FE_MINI_PID_PARSER21_SYNC_COUNT_SYNC_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *MINI_PID_PARSER22_TB_CTRL1 - Data Transport Parser Band 22 Transponder Bonding Control Register
- ***************************************************************************/
-/* XPT_FE :: MINI_PID_PARSER22_TB_CTRL1 :: reserved0 [31:28] */
-#define BCHP_XPT_FE_MINI_PID_PARSER22_TB_CTRL1_reserved0_MASK 0xf0000000
-#define BCHP_XPT_FE_MINI_PID_PARSER22_TB_CTRL1_reserved0_SHIFT 28
-
-/* XPT_FE :: MINI_PID_PARSER22_TB_CTRL1 :: TB_PARSER_PID_CH_NUM [27:16] */
-#define BCHP_XPT_FE_MINI_PID_PARSER22_TB_CTRL1_TB_PARSER_PID_CH_NUM_MASK 0x0fff0000
-#define BCHP_XPT_FE_MINI_PID_PARSER22_TB_CTRL1_TB_PARSER_PID_CH_NUM_SHIFT 16
-#define BCHP_XPT_FE_MINI_PID_PARSER22_TB_CTRL1_TB_PARSER_PID_CH_NUM_DEFAULT 0x00000000
-
-/* XPT_FE :: MINI_PID_PARSER22_TB_CTRL1 :: reserved1 [15:15] */
-#define BCHP_XPT_FE_MINI_PID_PARSER22_TB_CTRL1_reserved1_MASK 0x00008000
-#define BCHP_XPT_FE_MINI_PID_PARSER22_TB_CTRL1_reserved1_SHIFT 15
-
-/* XPT_FE :: MINI_PID_PARSER22_TB_CTRL1 :: TBG_PRI_BAND_NUM [14:08] */
-#define BCHP_XPT_FE_MINI_PID_PARSER22_TB_CTRL1_TBG_PRI_BAND_NUM_MASK 0x00007f00
-#define BCHP_XPT_FE_MINI_PID_PARSER22_TB_CTRL1_TBG_PRI_BAND_NUM_SHIFT 8
-#define BCHP_XPT_FE_MINI_PID_PARSER22_TB_CTRL1_TBG_PRI_BAND_NUM_DEFAULT 0x00000000
-
-/* XPT_FE :: MINI_PID_PARSER22_TB_CTRL1 :: reserved2 [07:04] */
-#define BCHP_XPT_FE_MINI_PID_PARSER22_TB_CTRL1_reserved2_MASK 0x000000f0
-#define BCHP_XPT_FE_MINI_PID_PARSER22_TB_CTRL1_reserved2_SHIFT 4
-
-/* XPT_FE :: MINI_PID_PARSER22_TB_CTRL1 :: TB_SKIP_ADAP_PRIVATE_DATA_PARSING [03:03] */
-#define BCHP_XPT_FE_MINI_PID_PARSER22_TB_CTRL1_TB_SKIP_ADAP_PRIVATE_DATA_PARSING_MASK 0x00000008
-#define BCHP_XPT_FE_MINI_PID_PARSER22_TB_CTRL1_TB_SKIP_ADAP_PRIVATE_DATA_PARSING_SHIFT 3
-#define BCHP_XPT_FE_MINI_PID_PARSER22_TB_CTRL1_TB_SKIP_ADAP_PRIVATE_DATA_PARSING_DEFAULT 0x00000000
-
-/* XPT_FE :: MINI_PID_PARSER22_TB_CTRL1 :: TB_IGNORE_TS_PRIORITY [02:02] */
-#define BCHP_XPT_FE_MINI_PID_PARSER22_TB_CTRL1_TB_IGNORE_TS_PRIORITY_MASK 0x00000004
-#define BCHP_XPT_FE_MINI_PID_PARSER22_TB_CTRL1_TB_IGNORE_TS_PRIORITY_SHIFT 2
-#define BCHP_XPT_FE_MINI_PID_PARSER22_TB_CTRL1_TB_IGNORE_TS_PRIORITY_DEFAULT 0x00000000
-
-/* XPT_FE :: MINI_PID_PARSER22_TB_CTRL1 :: TB_DROP_BEF_FIRST_MARKER_PKT [01:01] */
-#define BCHP_XPT_FE_MINI_PID_PARSER22_TB_CTRL1_TB_DROP_BEF_FIRST_MARKER_PKT_MASK 0x00000002
-#define BCHP_XPT_FE_MINI_PID_PARSER22_TB_CTRL1_TB_DROP_BEF_FIRST_MARKER_PKT_SHIFT 1
-#define BCHP_XPT_FE_MINI_PID_PARSER22_TB_CTRL1_TB_DROP_BEF_FIRST_MARKER_PKT_DEFAULT 0x00000000
-
-/* XPT_FE :: MINI_PID_PARSER22_TB_CTRL1 :: TB_ENABLE [00:00] */
-#define BCHP_XPT_FE_MINI_PID_PARSER22_TB_CTRL1_TB_ENABLE_MASK 0x00000001
-#define BCHP_XPT_FE_MINI_PID_PARSER22_TB_CTRL1_TB_ENABLE_SHIFT 0
-#define BCHP_XPT_FE_MINI_PID_PARSER22_TB_CTRL1_TB_ENABLE_DEFAULT 0x00000000
-
-/***************************************************************************
- *MINI_PID_PARSER22_SYNC_COUNT - Data Transport Parser Band 22 Transponder Bonding Sync Counter Register
- ***************************************************************************/
-/* XPT_FE :: MINI_PID_PARSER22_SYNC_COUNT :: reserved0 [31:10] */
-#define BCHP_XPT_FE_MINI_PID_PARSER22_SYNC_COUNT_reserved0_MASK 0xfffffc00
-#define BCHP_XPT_FE_MINI_PID_PARSER22_SYNC_COUNT_reserved0_SHIFT 10
-
-/* XPT_FE :: MINI_PID_PARSER22_SYNC_COUNT :: SYNC_COUNT [09:00] */
-#define BCHP_XPT_FE_MINI_PID_PARSER22_SYNC_COUNT_SYNC_COUNT_MASK 0x000003ff
-#define BCHP_XPT_FE_MINI_PID_PARSER22_SYNC_COUNT_SYNC_COUNT_SHIFT 0
-#define BCHP_XPT_FE_MINI_PID_PARSER22_SYNC_COUNT_SYNC_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *MINI_PID_PARSER23_TB_CTRL1 - Data Transport Parser Band 23 Transponder Bonding Control Register
- ***************************************************************************/
-/* XPT_FE :: MINI_PID_PARSER23_TB_CTRL1 :: reserved0 [31:28] */
-#define BCHP_XPT_FE_MINI_PID_PARSER23_TB_CTRL1_reserved0_MASK 0xf0000000
-#define BCHP_XPT_FE_MINI_PID_PARSER23_TB_CTRL1_reserved0_SHIFT 28
-
-/* XPT_FE :: MINI_PID_PARSER23_TB_CTRL1 :: TB_PARSER_PID_CH_NUM [27:16] */
-#define BCHP_XPT_FE_MINI_PID_PARSER23_TB_CTRL1_TB_PARSER_PID_CH_NUM_MASK 0x0fff0000
-#define BCHP_XPT_FE_MINI_PID_PARSER23_TB_CTRL1_TB_PARSER_PID_CH_NUM_SHIFT 16
-#define BCHP_XPT_FE_MINI_PID_PARSER23_TB_CTRL1_TB_PARSER_PID_CH_NUM_DEFAULT 0x00000000
-
-/* XPT_FE :: MINI_PID_PARSER23_TB_CTRL1 :: reserved1 [15:15] */
-#define BCHP_XPT_FE_MINI_PID_PARSER23_TB_CTRL1_reserved1_MASK 0x00008000
-#define BCHP_XPT_FE_MINI_PID_PARSER23_TB_CTRL1_reserved1_SHIFT 15
-
-/* XPT_FE :: MINI_PID_PARSER23_TB_CTRL1 :: TBG_PRI_BAND_NUM [14:08] */
-#define BCHP_XPT_FE_MINI_PID_PARSER23_TB_CTRL1_TBG_PRI_BAND_NUM_MASK 0x00007f00
-#define BCHP_XPT_FE_MINI_PID_PARSER23_TB_CTRL1_TBG_PRI_BAND_NUM_SHIFT 8
-#define BCHP_XPT_FE_MINI_PID_PARSER23_TB_CTRL1_TBG_PRI_BAND_NUM_DEFAULT 0x00000000
-
-/* XPT_FE :: MINI_PID_PARSER23_TB_CTRL1 :: reserved2 [07:04] */
-#define BCHP_XPT_FE_MINI_PID_PARSER23_TB_CTRL1_reserved2_MASK 0x000000f0
-#define BCHP_XPT_FE_MINI_PID_PARSER23_TB_CTRL1_reserved2_SHIFT 4
-
-/* XPT_FE :: MINI_PID_PARSER23_TB_CTRL1 :: TB_SKIP_ADAP_PRIVATE_DATA_PARSING [03:03] */
-#define BCHP_XPT_FE_MINI_PID_PARSER23_TB_CTRL1_TB_SKIP_ADAP_PRIVATE_DATA_PARSING_MASK 0x00000008
-#define BCHP_XPT_FE_MINI_PID_PARSER23_TB_CTRL1_TB_SKIP_ADAP_PRIVATE_DATA_PARSING_SHIFT 3
-#define BCHP_XPT_FE_MINI_PID_PARSER23_TB_CTRL1_TB_SKIP_ADAP_PRIVATE_DATA_PARSING_DEFAULT 0x00000000
-
-/* XPT_FE :: MINI_PID_PARSER23_TB_CTRL1 :: TB_IGNORE_TS_PRIORITY [02:02] */
-#define BCHP_XPT_FE_MINI_PID_PARSER23_TB_CTRL1_TB_IGNORE_TS_PRIORITY_MASK 0x00000004
-#define BCHP_XPT_FE_MINI_PID_PARSER23_TB_CTRL1_TB_IGNORE_TS_PRIORITY_SHIFT 2
-#define BCHP_XPT_FE_MINI_PID_PARSER23_TB_CTRL1_TB_IGNORE_TS_PRIORITY_DEFAULT 0x00000000
-
-/* XPT_FE :: MINI_PID_PARSER23_TB_CTRL1 :: TB_DROP_BEF_FIRST_MARKER_PKT [01:01] */
-#define BCHP_XPT_FE_MINI_PID_PARSER23_TB_CTRL1_TB_DROP_BEF_FIRST_MARKER_PKT_MASK 0x00000002
-#define BCHP_XPT_FE_MINI_PID_PARSER23_TB_CTRL1_TB_DROP_BEF_FIRST_MARKER_PKT_SHIFT 1
-#define BCHP_XPT_FE_MINI_PID_PARSER23_TB_CTRL1_TB_DROP_BEF_FIRST_MARKER_PKT_DEFAULT 0x00000000
-
-/* XPT_FE :: MINI_PID_PARSER23_TB_CTRL1 :: TB_ENABLE [00:00] */
-#define BCHP_XPT_FE_MINI_PID_PARSER23_TB_CTRL1_TB_ENABLE_MASK 0x00000001
-#define BCHP_XPT_FE_MINI_PID_PARSER23_TB_CTRL1_TB_ENABLE_SHIFT 0
-#define BCHP_XPT_FE_MINI_PID_PARSER23_TB_CTRL1_TB_ENABLE_DEFAULT 0x00000000
-
-/***************************************************************************
- *MINI_PID_PARSER23_SYNC_COUNT - Data Transport Parser Band 23 Transponder Bonding Sync Counter Register
- ***************************************************************************/
-/* XPT_FE :: MINI_PID_PARSER23_SYNC_COUNT :: reserved0 [31:10] */
-#define BCHP_XPT_FE_MINI_PID_PARSER23_SYNC_COUNT_reserved0_MASK 0xfffffc00
-#define BCHP_XPT_FE_MINI_PID_PARSER23_SYNC_COUNT_reserved0_SHIFT 10
-
-/* XPT_FE :: MINI_PID_PARSER23_SYNC_COUNT :: SYNC_COUNT [09:00] */
-#define BCHP_XPT_FE_MINI_PID_PARSER23_SYNC_COUNT_SYNC_COUNT_MASK 0x000003ff
-#define BCHP_XPT_FE_MINI_PID_PARSER23_SYNC_COUNT_SYNC_COUNT_SHIFT 0
-#define BCHP_XPT_FE_MINI_PID_PARSER23_SYNC_COUNT_SYNC_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *TB_GLOBAL_CTRL1 - Transponder Bonding Global Control Register 1
- ***************************************************************************/
-/* XPT_FE :: TB_GLOBAL_CTRL1 :: reserved0 [31:24] */
-#define BCHP_XPT_FE_TB_GLOBAL_CTRL1_reserved0_MASK 0xff000000
-#define BCHP_XPT_FE_TB_GLOBAL_CTRL1_reserved0_SHIFT 24
-
-/* XPT_FE :: TB_GLOBAL_CTRL1 :: TB_MARKER_TAG [23:16] */
-#define BCHP_XPT_FE_TB_GLOBAL_CTRL1_TB_MARKER_TAG_MASK 0x00ff0000
-#define BCHP_XPT_FE_TB_GLOBAL_CTRL1_TB_MARKER_TAG_SHIFT 16
-#define BCHP_XPT_FE_TB_GLOBAL_CTRL1_TB_MARKER_TAG_DEFAULT 0x000000ba
-
-/* XPT_FE :: TB_GLOBAL_CTRL1 :: reserved1 [15:11] */
-#define BCHP_XPT_FE_TB_GLOBAL_CTRL1_reserved1_MASK 0x0000f800
-#define BCHP_XPT_FE_TB_GLOBAL_CTRL1_reserved1_SHIFT 11
-
-/* XPT_FE :: TB_GLOBAL_CTRL1 :: TB_SATURATE_SYNC_COUNT_EN [10:10] */
-#define BCHP_XPT_FE_TB_GLOBAL_CTRL1_TB_SATURATE_SYNC_COUNT_EN_MASK 0x00000400
-#define BCHP_XPT_FE_TB_GLOBAL_CTRL1_TB_SATURATE_SYNC_COUNT_EN_SHIFT 10
-#define BCHP_XPT_FE_TB_GLOBAL_CTRL1_TB_SATURATE_SYNC_COUNT_EN_DEFAULT 0x00000001
-
-/* XPT_FE :: TB_GLOBAL_CTRL1 :: TB_SATURATE_SYNC_COUNT [09:00] */
-#define BCHP_XPT_FE_TB_GLOBAL_CTRL1_TB_SATURATE_SYNC_COUNT_MASK 0x000003ff
-#define BCHP_XPT_FE_TB_GLOBAL_CTRL1_TB_SATURATE_SYNC_COUNT_SHIFT 0
-#define BCHP_XPT_FE_TB_GLOBAL_CTRL1_TB_SATURATE_SYNC_COUNT_DEFAULT 0x00000100
-
-/***************************************************************************
- *TB_PARSERS_PRIVATE_DATA_LENGTH_ERROR_STATUS0_REG - Parsers Private Data Length Error Status Register
- ***************************************************************************/
-/* XPT_FE :: TB_PARSERS_PRIVATE_DATA_LENGTH_ERROR_STATUS0_REG :: TB_PARSER31_PRIVATE_DATA_LENGTH_ERROR [31:31] */
-#define BCHP_XPT_FE_TB_PARSERS_PRIVATE_DATA_LENGTH_ERROR_STATUS0_REG_TB_PARSER31_PRIVATE_DATA_LENGTH_ERROR_MASK 0x80000000
-#define BCHP_XPT_FE_TB_PARSERS_PRIVATE_DATA_LENGTH_ERROR_STATUS0_REG_TB_PARSER31_PRIVATE_DATA_LENGTH_ERROR_SHIFT 31
-#define BCHP_XPT_FE_TB_PARSERS_PRIVATE_DATA_LENGTH_ERROR_STATUS0_REG_TB_PARSER31_PRIVATE_DATA_LENGTH_ERROR_DEFAULT 0x00000000
-
-/* XPT_FE :: TB_PARSERS_PRIVATE_DATA_LENGTH_ERROR_STATUS0_REG :: TB_PARSER30_PRIVATE_DATA_LENGTH_ERROR [30:30] */
-#define BCHP_XPT_FE_TB_PARSERS_PRIVATE_DATA_LENGTH_ERROR_STATUS0_REG_TB_PARSER30_PRIVATE_DATA_LENGTH_ERROR_MASK 0x40000000
-#define BCHP_XPT_FE_TB_PARSERS_PRIVATE_DATA_LENGTH_ERROR_STATUS0_REG_TB_PARSER30_PRIVATE_DATA_LENGTH_ERROR_SHIFT 30
-#define BCHP_XPT_FE_TB_PARSERS_PRIVATE_DATA_LENGTH_ERROR_STATUS0_REG_TB_PARSER30_PRIVATE_DATA_LENGTH_ERROR_DEFAULT 0x00000000
-
-/* XPT_FE :: TB_PARSERS_PRIVATE_DATA_LENGTH_ERROR_STATUS0_REG :: TB_PARSER29_PRIVATE_DATA_LENGTH_ERROR [29:29] */
-#define BCHP_XPT_FE_TB_PARSERS_PRIVATE_DATA_LENGTH_ERROR_STATUS0_REG_TB_PARSER29_PRIVATE_DATA_LENGTH_ERROR_MASK 0x20000000
-#define BCHP_XPT_FE_TB_PARSERS_PRIVATE_DATA_LENGTH_ERROR_STATUS0_REG_TB_PARSER29_PRIVATE_DATA_LENGTH_ERROR_SHIFT 29
-#define BCHP_XPT_FE_TB_PARSERS_PRIVATE_DATA_LENGTH_ERROR_STATUS0_REG_TB_PARSER29_PRIVATE_DATA_LENGTH_ERROR_DEFAULT 0x00000000
-
-/* XPT_FE :: TB_PARSERS_PRIVATE_DATA_LENGTH_ERROR_STATUS0_REG :: TB_PARSER28_PRIVATE_DATA_LENGTH_ERROR [28:28] */
-#define BCHP_XPT_FE_TB_PARSERS_PRIVATE_DATA_LENGTH_ERROR_STATUS0_REG_TB_PARSER28_PRIVATE_DATA_LENGTH_ERROR_MASK 0x10000000
-#define BCHP_XPT_FE_TB_PARSERS_PRIVATE_DATA_LENGTH_ERROR_STATUS0_REG_TB_PARSER28_PRIVATE_DATA_LENGTH_ERROR_SHIFT 28
-#define BCHP_XPT_FE_TB_PARSERS_PRIVATE_DATA_LENGTH_ERROR_STATUS0_REG_TB_PARSER28_PRIVATE_DATA_LENGTH_ERROR_DEFAULT 0x00000000
-
-/* XPT_FE :: TB_PARSERS_PRIVATE_DATA_LENGTH_ERROR_STATUS0_REG :: TB_PARSER27_PRIVATE_DATA_LENGTH_ERROR [27:27] */
-#define BCHP_XPT_FE_TB_PARSERS_PRIVATE_DATA_LENGTH_ERROR_STATUS0_REG_TB_PARSER27_PRIVATE_DATA_LENGTH_ERROR_MASK 0x08000000
-#define BCHP_XPT_FE_TB_PARSERS_PRIVATE_DATA_LENGTH_ERROR_STATUS0_REG_TB_PARSER27_PRIVATE_DATA_LENGTH_ERROR_SHIFT 27
-#define BCHP_XPT_FE_TB_PARSERS_PRIVATE_DATA_LENGTH_ERROR_STATUS0_REG_TB_PARSER27_PRIVATE_DATA_LENGTH_ERROR_DEFAULT 0x00000000
-
-/* XPT_FE :: TB_PARSERS_PRIVATE_DATA_LENGTH_ERROR_STATUS0_REG :: TB_PARSER26_PRIVATE_DATA_LENGTH_ERROR [26:26] */
-#define BCHP_XPT_FE_TB_PARSERS_PRIVATE_DATA_LENGTH_ERROR_STATUS0_REG_TB_PARSER26_PRIVATE_DATA_LENGTH_ERROR_MASK 0x04000000
-#define BCHP_XPT_FE_TB_PARSERS_PRIVATE_DATA_LENGTH_ERROR_STATUS0_REG_TB_PARSER26_PRIVATE_DATA_LENGTH_ERROR_SHIFT 26
-#define BCHP_XPT_FE_TB_PARSERS_PRIVATE_DATA_LENGTH_ERROR_STATUS0_REG_TB_PARSER26_PRIVATE_DATA_LENGTH_ERROR_DEFAULT 0x00000000
-
-/* XPT_FE :: TB_PARSERS_PRIVATE_DATA_LENGTH_ERROR_STATUS0_REG :: TB_PARSER25_PRIVATE_DATA_LENGTH_ERROR [25:25] */
-#define BCHP_XPT_FE_TB_PARSERS_PRIVATE_DATA_LENGTH_ERROR_STATUS0_REG_TB_PARSER25_PRIVATE_DATA_LENGTH_ERROR_MASK 0x02000000
-#define BCHP_XPT_FE_TB_PARSERS_PRIVATE_DATA_LENGTH_ERROR_STATUS0_REG_TB_PARSER25_PRIVATE_DATA_LENGTH_ERROR_SHIFT 25
-#define BCHP_XPT_FE_TB_PARSERS_PRIVATE_DATA_LENGTH_ERROR_STATUS0_REG_TB_PARSER25_PRIVATE_DATA_LENGTH_ERROR_DEFAULT 0x00000000
-
-/* XPT_FE :: TB_PARSERS_PRIVATE_DATA_LENGTH_ERROR_STATUS0_REG :: TB_PARSER24_PRIVATE_DATA_LENGTH_ERROR [24:24] */
-#define BCHP_XPT_FE_TB_PARSERS_PRIVATE_DATA_LENGTH_ERROR_STATUS0_REG_TB_PARSER24_PRIVATE_DATA_LENGTH_ERROR_MASK 0x01000000
-#define BCHP_XPT_FE_TB_PARSERS_PRIVATE_DATA_LENGTH_ERROR_STATUS0_REG_TB_PARSER24_PRIVATE_DATA_LENGTH_ERROR_SHIFT 24
-#define BCHP_XPT_FE_TB_PARSERS_PRIVATE_DATA_LENGTH_ERROR_STATUS0_REG_TB_PARSER24_PRIVATE_DATA_LENGTH_ERROR_DEFAULT 0x00000000
-
-/* XPT_FE :: TB_PARSERS_PRIVATE_DATA_LENGTH_ERROR_STATUS0_REG :: TB_PARSER23_PRIVATE_DATA_LENGTH_ERROR [23:23] */
-#define BCHP_XPT_FE_TB_PARSERS_PRIVATE_DATA_LENGTH_ERROR_STATUS0_REG_TB_PARSER23_PRIVATE_DATA_LENGTH_ERROR_MASK 0x00800000
-#define BCHP_XPT_FE_TB_PARSERS_PRIVATE_DATA_LENGTH_ERROR_STATUS0_REG_TB_PARSER23_PRIVATE_DATA_LENGTH_ERROR_SHIFT 23
-#define BCHP_XPT_FE_TB_PARSERS_PRIVATE_DATA_LENGTH_ERROR_STATUS0_REG_TB_PARSER23_PRIVATE_DATA_LENGTH_ERROR_DEFAULT 0x00000000
-
-/* XPT_FE :: TB_PARSERS_PRIVATE_DATA_LENGTH_ERROR_STATUS0_REG :: TB_PARSER22_PRIVATE_DATA_LENGTH_ERROR [22:22] */
-#define BCHP_XPT_FE_TB_PARSERS_PRIVATE_DATA_LENGTH_ERROR_STATUS0_REG_TB_PARSER22_PRIVATE_DATA_LENGTH_ERROR_MASK 0x00400000
-#define BCHP_XPT_FE_TB_PARSERS_PRIVATE_DATA_LENGTH_ERROR_STATUS0_REG_TB_PARSER22_PRIVATE_DATA_LENGTH_ERROR_SHIFT 22
-#define BCHP_XPT_FE_TB_PARSERS_PRIVATE_DATA_LENGTH_ERROR_STATUS0_REG_TB_PARSER22_PRIVATE_DATA_LENGTH_ERROR_DEFAULT 0x00000000
-
-/* XPT_FE :: TB_PARSERS_PRIVATE_DATA_LENGTH_ERROR_STATUS0_REG :: TB_PARSER21_PRIVATE_DATA_LENGTH_ERROR [21:21] */
-#define BCHP_XPT_FE_TB_PARSERS_PRIVATE_DATA_LENGTH_ERROR_STATUS0_REG_TB_PARSER21_PRIVATE_DATA_LENGTH_ERROR_MASK 0x00200000
-#define BCHP_XPT_FE_TB_PARSERS_PRIVATE_DATA_LENGTH_ERROR_STATUS0_REG_TB_PARSER21_PRIVATE_DATA_LENGTH_ERROR_SHIFT 21
-#define BCHP_XPT_FE_TB_PARSERS_PRIVATE_DATA_LENGTH_ERROR_STATUS0_REG_TB_PARSER21_PRIVATE_DATA_LENGTH_ERROR_DEFAULT 0x00000000
-
-/* XPT_FE :: TB_PARSERS_PRIVATE_DATA_LENGTH_ERROR_STATUS0_REG :: TB_PARSER20_PRIVATE_DATA_LENGTH_ERROR [20:20] */
-#define BCHP_XPT_FE_TB_PARSERS_PRIVATE_DATA_LENGTH_ERROR_STATUS0_REG_TB_PARSER20_PRIVATE_DATA_LENGTH_ERROR_MASK 0x00100000
-#define BCHP_XPT_FE_TB_PARSERS_PRIVATE_DATA_LENGTH_ERROR_STATUS0_REG_TB_PARSER20_PRIVATE_DATA_LENGTH_ERROR_SHIFT 20
-#define BCHP_XPT_FE_TB_PARSERS_PRIVATE_DATA_LENGTH_ERROR_STATUS0_REG_TB_PARSER20_PRIVATE_DATA_LENGTH_ERROR_DEFAULT 0x00000000
-
-/* XPT_FE :: TB_PARSERS_PRIVATE_DATA_LENGTH_ERROR_STATUS0_REG :: TB_PARSER19_PRIVATE_DATA_LENGTH_ERROR [19:19] */
-#define BCHP_XPT_FE_TB_PARSERS_PRIVATE_DATA_LENGTH_ERROR_STATUS0_REG_TB_PARSER19_PRIVATE_DATA_LENGTH_ERROR_MASK 0x00080000
-#define BCHP_XPT_FE_TB_PARSERS_PRIVATE_DATA_LENGTH_ERROR_STATUS0_REG_TB_PARSER19_PRIVATE_DATA_LENGTH_ERROR_SHIFT 19
-#define BCHP_XPT_FE_TB_PARSERS_PRIVATE_DATA_LENGTH_ERROR_STATUS0_REG_TB_PARSER19_PRIVATE_DATA_LENGTH_ERROR_DEFAULT 0x00000000
-
-/* XPT_FE :: TB_PARSERS_PRIVATE_DATA_LENGTH_ERROR_STATUS0_REG :: TB_PARSER18_PRIVATE_DATA_LENGTH_ERROR [18:18] */
-#define BCHP_XPT_FE_TB_PARSERS_PRIVATE_DATA_LENGTH_ERROR_STATUS0_REG_TB_PARSER18_PRIVATE_DATA_LENGTH_ERROR_MASK 0x00040000
-#define BCHP_XPT_FE_TB_PARSERS_PRIVATE_DATA_LENGTH_ERROR_STATUS0_REG_TB_PARSER18_PRIVATE_DATA_LENGTH_ERROR_SHIFT 18
-#define BCHP_XPT_FE_TB_PARSERS_PRIVATE_DATA_LENGTH_ERROR_STATUS0_REG_TB_PARSER18_PRIVATE_DATA_LENGTH_ERROR_DEFAULT 0x00000000
-
-/* XPT_FE :: TB_PARSERS_PRIVATE_DATA_LENGTH_ERROR_STATUS0_REG :: TB_PARSER17_PRIVATE_DATA_LENGTH_ERROR [17:17] */
-#define BCHP_XPT_FE_TB_PARSERS_PRIVATE_DATA_LENGTH_ERROR_STATUS0_REG_TB_PARSER17_PRIVATE_DATA_LENGTH_ERROR_MASK 0x00020000
-#define BCHP_XPT_FE_TB_PARSERS_PRIVATE_DATA_LENGTH_ERROR_STATUS0_REG_TB_PARSER17_PRIVATE_DATA_LENGTH_ERROR_SHIFT 17
-#define BCHP_XPT_FE_TB_PARSERS_PRIVATE_DATA_LENGTH_ERROR_STATUS0_REG_TB_PARSER17_PRIVATE_DATA_LENGTH_ERROR_DEFAULT 0x00000000
-
-/* XPT_FE :: TB_PARSERS_PRIVATE_DATA_LENGTH_ERROR_STATUS0_REG :: TB_PARSER16_PRIVATE_DATA_LENGTH_ERROR [16:16] */
-#define BCHP_XPT_FE_TB_PARSERS_PRIVATE_DATA_LENGTH_ERROR_STATUS0_REG_TB_PARSER16_PRIVATE_DATA_LENGTH_ERROR_MASK 0x00010000
-#define BCHP_XPT_FE_TB_PARSERS_PRIVATE_DATA_LENGTH_ERROR_STATUS0_REG_TB_PARSER16_PRIVATE_DATA_LENGTH_ERROR_SHIFT 16
-#define BCHP_XPT_FE_TB_PARSERS_PRIVATE_DATA_LENGTH_ERROR_STATUS0_REG_TB_PARSER16_PRIVATE_DATA_LENGTH_ERROR_DEFAULT 0x00000000
-
-/* XPT_FE :: TB_PARSERS_PRIVATE_DATA_LENGTH_ERROR_STATUS0_REG :: TB_PARSER15_PRIVATE_DATA_LENGTH_ERROR [15:15] */
-#define BCHP_XPT_FE_TB_PARSERS_PRIVATE_DATA_LENGTH_ERROR_STATUS0_REG_TB_PARSER15_PRIVATE_DATA_LENGTH_ERROR_MASK 0x00008000
-#define BCHP_XPT_FE_TB_PARSERS_PRIVATE_DATA_LENGTH_ERROR_STATUS0_REG_TB_PARSER15_PRIVATE_DATA_LENGTH_ERROR_SHIFT 15
-#define BCHP_XPT_FE_TB_PARSERS_PRIVATE_DATA_LENGTH_ERROR_STATUS0_REG_TB_PARSER15_PRIVATE_DATA_LENGTH_ERROR_DEFAULT 0x00000000
-
-/* XPT_FE :: TB_PARSERS_PRIVATE_DATA_LENGTH_ERROR_STATUS0_REG :: TB_PARSER14_PRIVATE_DATA_LENGTH_ERROR [14:14] */
-#define BCHP_XPT_FE_TB_PARSERS_PRIVATE_DATA_LENGTH_ERROR_STATUS0_REG_TB_PARSER14_PRIVATE_DATA_LENGTH_ERROR_MASK 0x00004000
-#define BCHP_XPT_FE_TB_PARSERS_PRIVATE_DATA_LENGTH_ERROR_STATUS0_REG_TB_PARSER14_PRIVATE_DATA_LENGTH_ERROR_SHIFT 14
-#define BCHP_XPT_FE_TB_PARSERS_PRIVATE_DATA_LENGTH_ERROR_STATUS0_REG_TB_PARSER14_PRIVATE_DATA_LENGTH_ERROR_DEFAULT 0x00000000
-
-/* XPT_FE :: TB_PARSERS_PRIVATE_DATA_LENGTH_ERROR_STATUS0_REG :: TB_PARSER13_PRIVATE_DATA_LENGTH_ERROR [13:13] */
-#define BCHP_XPT_FE_TB_PARSERS_PRIVATE_DATA_LENGTH_ERROR_STATUS0_REG_TB_PARSER13_PRIVATE_DATA_LENGTH_ERROR_MASK 0x00002000
-#define BCHP_XPT_FE_TB_PARSERS_PRIVATE_DATA_LENGTH_ERROR_STATUS0_REG_TB_PARSER13_PRIVATE_DATA_LENGTH_ERROR_SHIFT 13
-#define BCHP_XPT_FE_TB_PARSERS_PRIVATE_DATA_LENGTH_ERROR_STATUS0_REG_TB_PARSER13_PRIVATE_DATA_LENGTH_ERROR_DEFAULT 0x00000000
-
-/* XPT_FE :: TB_PARSERS_PRIVATE_DATA_LENGTH_ERROR_STATUS0_REG :: TB_PARSER12_PRIVATE_DATA_LENGTH_ERROR [12:12] */
-#define BCHP_XPT_FE_TB_PARSERS_PRIVATE_DATA_LENGTH_ERROR_STATUS0_REG_TB_PARSER12_PRIVATE_DATA_LENGTH_ERROR_MASK 0x00001000
-#define BCHP_XPT_FE_TB_PARSERS_PRIVATE_DATA_LENGTH_ERROR_STATUS0_REG_TB_PARSER12_PRIVATE_DATA_LENGTH_ERROR_SHIFT 12
-#define BCHP_XPT_FE_TB_PARSERS_PRIVATE_DATA_LENGTH_ERROR_STATUS0_REG_TB_PARSER12_PRIVATE_DATA_LENGTH_ERROR_DEFAULT 0x00000000
-
-/* XPT_FE :: TB_PARSERS_PRIVATE_DATA_LENGTH_ERROR_STATUS0_REG :: TB_PARSER11_PRIVATE_DATA_LENGTH_ERROR [11:11] */
-#define BCHP_XPT_FE_TB_PARSERS_PRIVATE_DATA_LENGTH_ERROR_STATUS0_REG_TB_PARSER11_PRIVATE_DATA_LENGTH_ERROR_MASK 0x00000800
-#define BCHP_XPT_FE_TB_PARSERS_PRIVATE_DATA_LENGTH_ERROR_STATUS0_REG_TB_PARSER11_PRIVATE_DATA_LENGTH_ERROR_SHIFT 11
-#define BCHP_XPT_FE_TB_PARSERS_PRIVATE_DATA_LENGTH_ERROR_STATUS0_REG_TB_PARSER11_PRIVATE_DATA_LENGTH_ERROR_DEFAULT 0x00000000
-
-/* XPT_FE :: TB_PARSERS_PRIVATE_DATA_LENGTH_ERROR_STATUS0_REG :: TB_PARSER10_PRIVATE_DATA_LENGTH_ERROR [10:10] */
-#define BCHP_XPT_FE_TB_PARSERS_PRIVATE_DATA_LENGTH_ERROR_STATUS0_REG_TB_PARSER10_PRIVATE_DATA_LENGTH_ERROR_MASK 0x00000400
-#define BCHP_XPT_FE_TB_PARSERS_PRIVATE_DATA_LENGTH_ERROR_STATUS0_REG_TB_PARSER10_PRIVATE_DATA_LENGTH_ERROR_SHIFT 10
-#define BCHP_XPT_FE_TB_PARSERS_PRIVATE_DATA_LENGTH_ERROR_STATUS0_REG_TB_PARSER10_PRIVATE_DATA_LENGTH_ERROR_DEFAULT 0x00000000
-
-/* XPT_FE :: TB_PARSERS_PRIVATE_DATA_LENGTH_ERROR_STATUS0_REG :: TB_PARSER9_PRIVATE_DATA_LENGTH_ERROR [09:09] */
-#define BCHP_XPT_FE_TB_PARSERS_PRIVATE_DATA_LENGTH_ERROR_STATUS0_REG_TB_PARSER9_PRIVATE_DATA_LENGTH_ERROR_MASK 0x00000200
-#define BCHP_XPT_FE_TB_PARSERS_PRIVATE_DATA_LENGTH_ERROR_STATUS0_REG_TB_PARSER9_PRIVATE_DATA_LENGTH_ERROR_SHIFT 9
-#define BCHP_XPT_FE_TB_PARSERS_PRIVATE_DATA_LENGTH_ERROR_STATUS0_REG_TB_PARSER9_PRIVATE_DATA_LENGTH_ERROR_DEFAULT 0x00000000
-
-/* XPT_FE :: TB_PARSERS_PRIVATE_DATA_LENGTH_ERROR_STATUS0_REG :: TB_PARSER8_PRIVATE_DATA_LENGTH_ERROR [08:08] */
-#define BCHP_XPT_FE_TB_PARSERS_PRIVATE_DATA_LENGTH_ERROR_STATUS0_REG_TB_PARSER8_PRIVATE_DATA_LENGTH_ERROR_MASK 0x00000100
-#define BCHP_XPT_FE_TB_PARSERS_PRIVATE_DATA_LENGTH_ERROR_STATUS0_REG_TB_PARSER8_PRIVATE_DATA_LENGTH_ERROR_SHIFT 8
-#define BCHP_XPT_FE_TB_PARSERS_PRIVATE_DATA_LENGTH_ERROR_STATUS0_REG_TB_PARSER8_PRIVATE_DATA_LENGTH_ERROR_DEFAULT 0x00000000
-
-/* XPT_FE :: TB_PARSERS_PRIVATE_DATA_LENGTH_ERROR_STATUS0_REG :: TB_PARSER7_PRIVATE_DATA_LENGTH_ERROR [07:07] */
-#define BCHP_XPT_FE_TB_PARSERS_PRIVATE_DATA_LENGTH_ERROR_STATUS0_REG_TB_PARSER7_PRIVATE_DATA_LENGTH_ERROR_MASK 0x00000080
-#define BCHP_XPT_FE_TB_PARSERS_PRIVATE_DATA_LENGTH_ERROR_STATUS0_REG_TB_PARSER7_PRIVATE_DATA_LENGTH_ERROR_SHIFT 7
-#define BCHP_XPT_FE_TB_PARSERS_PRIVATE_DATA_LENGTH_ERROR_STATUS0_REG_TB_PARSER7_PRIVATE_DATA_LENGTH_ERROR_DEFAULT 0x00000000
-
-/* XPT_FE :: TB_PARSERS_PRIVATE_DATA_LENGTH_ERROR_STATUS0_REG :: TB_PARSER6_PRIVATE_DATA_LENGTH_ERROR [06:06] */
-#define BCHP_XPT_FE_TB_PARSERS_PRIVATE_DATA_LENGTH_ERROR_STATUS0_REG_TB_PARSER6_PRIVATE_DATA_LENGTH_ERROR_MASK 0x00000040
-#define BCHP_XPT_FE_TB_PARSERS_PRIVATE_DATA_LENGTH_ERROR_STATUS0_REG_TB_PARSER6_PRIVATE_DATA_LENGTH_ERROR_SHIFT 6
-#define BCHP_XPT_FE_TB_PARSERS_PRIVATE_DATA_LENGTH_ERROR_STATUS0_REG_TB_PARSER6_PRIVATE_DATA_LENGTH_ERROR_DEFAULT 0x00000000
-
-/* XPT_FE :: TB_PARSERS_PRIVATE_DATA_LENGTH_ERROR_STATUS0_REG :: TB_PARSER5_PRIVATE_DATA_LENGTH_ERROR [05:05] */
-#define BCHP_XPT_FE_TB_PARSERS_PRIVATE_DATA_LENGTH_ERROR_STATUS0_REG_TB_PARSER5_PRIVATE_DATA_LENGTH_ERROR_MASK 0x00000020
-#define BCHP_XPT_FE_TB_PARSERS_PRIVATE_DATA_LENGTH_ERROR_STATUS0_REG_TB_PARSER5_PRIVATE_DATA_LENGTH_ERROR_SHIFT 5
-#define BCHP_XPT_FE_TB_PARSERS_PRIVATE_DATA_LENGTH_ERROR_STATUS0_REG_TB_PARSER5_PRIVATE_DATA_LENGTH_ERROR_DEFAULT 0x00000000
-
-/* XPT_FE :: TB_PARSERS_PRIVATE_DATA_LENGTH_ERROR_STATUS0_REG :: TB_PARSER4_PRIVATE_DATA_LENGTH_ERROR [04:04] */
-#define BCHP_XPT_FE_TB_PARSERS_PRIVATE_DATA_LENGTH_ERROR_STATUS0_REG_TB_PARSER4_PRIVATE_DATA_LENGTH_ERROR_MASK 0x00000010
-#define BCHP_XPT_FE_TB_PARSERS_PRIVATE_DATA_LENGTH_ERROR_STATUS0_REG_TB_PARSER4_PRIVATE_DATA_LENGTH_ERROR_SHIFT 4
-#define BCHP_XPT_FE_TB_PARSERS_PRIVATE_DATA_LENGTH_ERROR_STATUS0_REG_TB_PARSER4_PRIVATE_DATA_LENGTH_ERROR_DEFAULT 0x00000000
-
-/* XPT_FE :: TB_PARSERS_PRIVATE_DATA_LENGTH_ERROR_STATUS0_REG :: TB_PARSER3_PRIVATE_DATA_LENGTH_ERROR [03:03] */
-#define BCHP_XPT_FE_TB_PARSERS_PRIVATE_DATA_LENGTH_ERROR_STATUS0_REG_TB_PARSER3_PRIVATE_DATA_LENGTH_ERROR_MASK 0x00000008
-#define BCHP_XPT_FE_TB_PARSERS_PRIVATE_DATA_LENGTH_ERROR_STATUS0_REG_TB_PARSER3_PRIVATE_DATA_LENGTH_ERROR_SHIFT 3
-#define BCHP_XPT_FE_TB_PARSERS_PRIVATE_DATA_LENGTH_ERROR_STATUS0_REG_TB_PARSER3_PRIVATE_DATA_LENGTH_ERROR_DEFAULT 0x00000000
-
-/* XPT_FE :: TB_PARSERS_PRIVATE_DATA_LENGTH_ERROR_STATUS0_REG :: TB_PARSER2_PRIVATE_DATA_LENGTH_ERROR [02:02] */
-#define BCHP_XPT_FE_TB_PARSERS_PRIVATE_DATA_LENGTH_ERROR_STATUS0_REG_TB_PARSER2_PRIVATE_DATA_LENGTH_ERROR_MASK 0x00000004
-#define BCHP_XPT_FE_TB_PARSERS_PRIVATE_DATA_LENGTH_ERROR_STATUS0_REG_TB_PARSER2_PRIVATE_DATA_LENGTH_ERROR_SHIFT 2
-#define BCHP_XPT_FE_TB_PARSERS_PRIVATE_DATA_LENGTH_ERROR_STATUS0_REG_TB_PARSER2_PRIVATE_DATA_LENGTH_ERROR_DEFAULT 0x00000000
-
-/* XPT_FE :: TB_PARSERS_PRIVATE_DATA_LENGTH_ERROR_STATUS0_REG :: TB_PARSER1_PRIVATE_DATA_LENGTH_ERROR [01:01] */
-#define BCHP_XPT_FE_TB_PARSERS_PRIVATE_DATA_LENGTH_ERROR_STATUS0_REG_TB_PARSER1_PRIVATE_DATA_LENGTH_ERROR_MASK 0x00000002
-#define BCHP_XPT_FE_TB_PARSERS_PRIVATE_DATA_LENGTH_ERROR_STATUS0_REG_TB_PARSER1_PRIVATE_DATA_LENGTH_ERROR_SHIFT 1
-#define BCHP_XPT_FE_TB_PARSERS_PRIVATE_DATA_LENGTH_ERROR_STATUS0_REG_TB_PARSER1_PRIVATE_DATA_LENGTH_ERROR_DEFAULT 0x00000000
-
-/* XPT_FE :: TB_PARSERS_PRIVATE_DATA_LENGTH_ERROR_STATUS0_REG :: TB_PARSER0_PRIVATE_DATA_LENGTH_ERROR [00:00] */
-#define BCHP_XPT_FE_TB_PARSERS_PRIVATE_DATA_LENGTH_ERROR_STATUS0_REG_TB_PARSER0_PRIVATE_DATA_LENGTH_ERROR_MASK 0x00000001
-#define BCHP_XPT_FE_TB_PARSERS_PRIVATE_DATA_LENGTH_ERROR_STATUS0_REG_TB_PARSER0_PRIVATE_DATA_LENGTH_ERROR_SHIFT 0
-#define BCHP_XPT_FE_TB_PARSERS_PRIVATE_DATA_LENGTH_ERROR_STATUS0_REG_TB_PARSER0_PRIVATE_DATA_LENGTH_ERROR_DEFAULT 0x00000000
-
-/***************************************************************************
- *TB_PARSERS_PRIVATE_DATA_FIELD_LENGTH_ERROR_STATUS0_REG - Parsers Private Data Field Length Error Status Register
- ***************************************************************************/
-/* XPT_FE :: TB_PARSERS_PRIVATE_DATA_FIELD_LENGTH_ERROR_STATUS0_REG :: TB_PARSER31_PRIVATE_DATA_FIELD_LENGTH_ERROR [31:31] */
-#define BCHP_XPT_FE_TB_PARSERS_PRIVATE_DATA_FIELD_LENGTH_ERROR_STATUS0_REG_TB_PARSER31_PRIVATE_DATA_FIELD_LENGTH_ERROR_MASK 0x80000000
-#define BCHP_XPT_FE_TB_PARSERS_PRIVATE_DATA_FIELD_LENGTH_ERROR_STATUS0_REG_TB_PARSER31_PRIVATE_DATA_FIELD_LENGTH_ERROR_SHIFT 31
-#define BCHP_XPT_FE_TB_PARSERS_PRIVATE_DATA_FIELD_LENGTH_ERROR_STATUS0_REG_TB_PARSER31_PRIVATE_DATA_FIELD_LENGTH_ERROR_DEFAULT 0x00000000
-
-/* XPT_FE :: TB_PARSERS_PRIVATE_DATA_FIELD_LENGTH_ERROR_STATUS0_REG :: TB_PARSER30_PRIVATE_DATA_FIELD_LENGTH_ERROR [30:30] */
-#define BCHP_XPT_FE_TB_PARSERS_PRIVATE_DATA_FIELD_LENGTH_ERROR_STATUS0_REG_TB_PARSER30_PRIVATE_DATA_FIELD_LENGTH_ERROR_MASK 0x40000000
-#define BCHP_XPT_FE_TB_PARSERS_PRIVATE_DATA_FIELD_LENGTH_ERROR_STATUS0_REG_TB_PARSER30_PRIVATE_DATA_FIELD_LENGTH_ERROR_SHIFT 30
-#define BCHP_XPT_FE_TB_PARSERS_PRIVATE_DATA_FIELD_LENGTH_ERROR_STATUS0_REG_TB_PARSER30_PRIVATE_DATA_FIELD_LENGTH_ERROR_DEFAULT 0x00000000
-
-/* XPT_FE :: TB_PARSERS_PRIVATE_DATA_FIELD_LENGTH_ERROR_STATUS0_REG :: TB_PARSER29_PRIVATE_DATA_FIELD_LENGTH_ERROR [29:29] */
-#define BCHP_XPT_FE_TB_PARSERS_PRIVATE_DATA_FIELD_LENGTH_ERROR_STATUS0_REG_TB_PARSER29_PRIVATE_DATA_FIELD_LENGTH_ERROR_MASK 0x20000000
-#define BCHP_XPT_FE_TB_PARSERS_PRIVATE_DATA_FIELD_LENGTH_ERROR_STATUS0_REG_TB_PARSER29_PRIVATE_DATA_FIELD_LENGTH_ERROR_SHIFT 29
-#define BCHP_XPT_FE_TB_PARSERS_PRIVATE_DATA_FIELD_LENGTH_ERROR_STATUS0_REG_TB_PARSER29_PRIVATE_DATA_FIELD_LENGTH_ERROR_DEFAULT 0x00000000
-
-/* XPT_FE :: TB_PARSERS_PRIVATE_DATA_FIELD_LENGTH_ERROR_STATUS0_REG :: TB_PARSER28_PRIVATE_DATA_FIELD_LENGTH_ERROR [28:28] */
-#define BCHP_XPT_FE_TB_PARSERS_PRIVATE_DATA_FIELD_LENGTH_ERROR_STATUS0_REG_TB_PARSER28_PRIVATE_DATA_FIELD_LENGTH_ERROR_MASK 0x10000000
-#define BCHP_XPT_FE_TB_PARSERS_PRIVATE_DATA_FIELD_LENGTH_ERROR_STATUS0_REG_TB_PARSER28_PRIVATE_DATA_FIELD_LENGTH_ERROR_SHIFT 28
-#define BCHP_XPT_FE_TB_PARSERS_PRIVATE_DATA_FIELD_LENGTH_ERROR_STATUS0_REG_TB_PARSER28_PRIVATE_DATA_FIELD_LENGTH_ERROR_DEFAULT 0x00000000
-
-/* XPT_FE :: TB_PARSERS_PRIVATE_DATA_FIELD_LENGTH_ERROR_STATUS0_REG :: TB_PARSER27_PRIVATE_DATA_FIELD_LENGTH_ERROR [27:27] */
-#define BCHP_XPT_FE_TB_PARSERS_PRIVATE_DATA_FIELD_LENGTH_ERROR_STATUS0_REG_TB_PARSER27_PRIVATE_DATA_FIELD_LENGTH_ERROR_MASK 0x08000000
-#define BCHP_XPT_FE_TB_PARSERS_PRIVATE_DATA_FIELD_LENGTH_ERROR_STATUS0_REG_TB_PARSER27_PRIVATE_DATA_FIELD_LENGTH_ERROR_SHIFT 27
-#define BCHP_XPT_FE_TB_PARSERS_PRIVATE_DATA_FIELD_LENGTH_ERROR_STATUS0_REG_TB_PARSER27_PRIVATE_DATA_FIELD_LENGTH_ERROR_DEFAULT 0x00000000
-
-/* XPT_FE :: TB_PARSERS_PRIVATE_DATA_FIELD_LENGTH_ERROR_STATUS0_REG :: TB_PARSER26_PRIVATE_DATA_FIELD_LENGTH_ERROR [26:26] */
-#define BCHP_XPT_FE_TB_PARSERS_PRIVATE_DATA_FIELD_LENGTH_ERROR_STATUS0_REG_TB_PARSER26_PRIVATE_DATA_FIELD_LENGTH_ERROR_MASK 0x04000000
-#define BCHP_XPT_FE_TB_PARSERS_PRIVATE_DATA_FIELD_LENGTH_ERROR_STATUS0_REG_TB_PARSER26_PRIVATE_DATA_FIELD_LENGTH_ERROR_SHIFT 26
-#define BCHP_XPT_FE_TB_PARSERS_PRIVATE_DATA_FIELD_LENGTH_ERROR_STATUS0_REG_TB_PARSER26_PRIVATE_DATA_FIELD_LENGTH_ERROR_DEFAULT 0x00000000
-
-/* XPT_FE :: TB_PARSERS_PRIVATE_DATA_FIELD_LENGTH_ERROR_STATUS0_REG :: TB_PARSER25_PRIVATE_DATA_FIELD_LENGTH_ERROR [25:25] */
-#define BCHP_XPT_FE_TB_PARSERS_PRIVATE_DATA_FIELD_LENGTH_ERROR_STATUS0_REG_TB_PARSER25_PRIVATE_DATA_FIELD_LENGTH_ERROR_MASK 0x02000000
-#define BCHP_XPT_FE_TB_PARSERS_PRIVATE_DATA_FIELD_LENGTH_ERROR_STATUS0_REG_TB_PARSER25_PRIVATE_DATA_FIELD_LENGTH_ERROR_SHIFT 25
-#define BCHP_XPT_FE_TB_PARSERS_PRIVATE_DATA_FIELD_LENGTH_ERROR_STATUS0_REG_TB_PARSER25_PRIVATE_DATA_FIELD_LENGTH_ERROR_DEFAULT 0x00000000
-
-/* XPT_FE :: TB_PARSERS_PRIVATE_DATA_FIELD_LENGTH_ERROR_STATUS0_REG :: TB_PARSER24_PRIVATE_DATA_FIELD_LENGTH_ERROR [24:24] */
-#define BCHP_XPT_FE_TB_PARSERS_PRIVATE_DATA_FIELD_LENGTH_ERROR_STATUS0_REG_TB_PARSER24_PRIVATE_DATA_FIELD_LENGTH_ERROR_MASK 0x01000000
-#define BCHP_XPT_FE_TB_PARSERS_PRIVATE_DATA_FIELD_LENGTH_ERROR_STATUS0_REG_TB_PARSER24_PRIVATE_DATA_FIELD_LENGTH_ERROR_SHIFT 24
-#define BCHP_XPT_FE_TB_PARSERS_PRIVATE_DATA_FIELD_LENGTH_ERROR_STATUS0_REG_TB_PARSER24_PRIVATE_DATA_FIELD_LENGTH_ERROR_DEFAULT 0x00000000
-
-/* XPT_FE :: TB_PARSERS_PRIVATE_DATA_FIELD_LENGTH_ERROR_STATUS0_REG :: TB_PARSER23_PRIVATE_DATA_FIELD_LENGTH_ERROR [23:23] */
-#define BCHP_XPT_FE_TB_PARSERS_PRIVATE_DATA_FIELD_LENGTH_ERROR_STATUS0_REG_TB_PARSER23_PRIVATE_DATA_FIELD_LENGTH_ERROR_MASK 0x00800000
-#define BCHP_XPT_FE_TB_PARSERS_PRIVATE_DATA_FIELD_LENGTH_ERROR_STATUS0_REG_TB_PARSER23_PRIVATE_DATA_FIELD_LENGTH_ERROR_SHIFT 23
-#define BCHP_XPT_FE_TB_PARSERS_PRIVATE_DATA_FIELD_LENGTH_ERROR_STATUS0_REG_TB_PARSER23_PRIVATE_DATA_FIELD_LENGTH_ERROR_DEFAULT 0x00000000
-
-/* XPT_FE :: TB_PARSERS_PRIVATE_DATA_FIELD_LENGTH_ERROR_STATUS0_REG :: TB_PARSER22_PRIVATE_DATA_FIELD_LENGTH_ERROR [22:22] */
-#define BCHP_XPT_FE_TB_PARSERS_PRIVATE_DATA_FIELD_LENGTH_ERROR_STATUS0_REG_TB_PARSER22_PRIVATE_DATA_FIELD_LENGTH_ERROR_MASK 0x00400000
-#define BCHP_XPT_FE_TB_PARSERS_PRIVATE_DATA_FIELD_LENGTH_ERROR_STATUS0_REG_TB_PARSER22_PRIVATE_DATA_FIELD_LENGTH_ERROR_SHIFT 22
-#define BCHP_XPT_FE_TB_PARSERS_PRIVATE_DATA_FIELD_LENGTH_ERROR_STATUS0_REG_TB_PARSER22_PRIVATE_DATA_FIELD_LENGTH_ERROR_DEFAULT 0x00000000
-
-/* XPT_FE :: TB_PARSERS_PRIVATE_DATA_FIELD_LENGTH_ERROR_STATUS0_REG :: TB_PARSER21_PRIVATE_DATA_FIELD_LENGTH_ERROR [21:21] */
-#define BCHP_XPT_FE_TB_PARSERS_PRIVATE_DATA_FIELD_LENGTH_ERROR_STATUS0_REG_TB_PARSER21_PRIVATE_DATA_FIELD_LENGTH_ERROR_MASK 0x00200000
-#define BCHP_XPT_FE_TB_PARSERS_PRIVATE_DATA_FIELD_LENGTH_ERROR_STATUS0_REG_TB_PARSER21_PRIVATE_DATA_FIELD_LENGTH_ERROR_SHIFT 21
-#define BCHP_XPT_FE_TB_PARSERS_PRIVATE_DATA_FIELD_LENGTH_ERROR_STATUS0_REG_TB_PARSER21_PRIVATE_DATA_FIELD_LENGTH_ERROR_DEFAULT 0x00000000
-
-/* XPT_FE :: TB_PARSERS_PRIVATE_DATA_FIELD_LENGTH_ERROR_STATUS0_REG :: TB_PARSER20_PRIVATE_DATA_FIELD_LENGTH_ERROR [20:20] */
-#define BCHP_XPT_FE_TB_PARSERS_PRIVATE_DATA_FIELD_LENGTH_ERROR_STATUS0_REG_TB_PARSER20_PRIVATE_DATA_FIELD_LENGTH_ERROR_MASK 0x00100000
-#define BCHP_XPT_FE_TB_PARSERS_PRIVATE_DATA_FIELD_LENGTH_ERROR_STATUS0_REG_TB_PARSER20_PRIVATE_DATA_FIELD_LENGTH_ERROR_SHIFT 20
-#define BCHP_XPT_FE_TB_PARSERS_PRIVATE_DATA_FIELD_LENGTH_ERROR_STATUS0_REG_TB_PARSER20_PRIVATE_DATA_FIELD_LENGTH_ERROR_DEFAULT 0x00000000
-
-/* XPT_FE :: TB_PARSERS_PRIVATE_DATA_FIELD_LENGTH_ERROR_STATUS0_REG :: TB_PARSER19_PRIVATE_DATA_FIELD_LENGTH_ERROR [19:19] */
-#define BCHP_XPT_FE_TB_PARSERS_PRIVATE_DATA_FIELD_LENGTH_ERROR_STATUS0_REG_TB_PARSER19_PRIVATE_DATA_FIELD_LENGTH_ERROR_MASK 0x00080000
-#define BCHP_XPT_FE_TB_PARSERS_PRIVATE_DATA_FIELD_LENGTH_ERROR_STATUS0_REG_TB_PARSER19_PRIVATE_DATA_FIELD_LENGTH_ERROR_SHIFT 19
-#define BCHP_XPT_FE_TB_PARSERS_PRIVATE_DATA_FIELD_LENGTH_ERROR_STATUS0_REG_TB_PARSER19_PRIVATE_DATA_FIELD_LENGTH_ERROR_DEFAULT 0x00000000
-
-/* XPT_FE :: TB_PARSERS_PRIVATE_DATA_FIELD_LENGTH_ERROR_STATUS0_REG :: TB_PARSER18_PRIVATE_DATA_FIELD_LENGTH_ERROR [18:18] */
-#define BCHP_XPT_FE_TB_PARSERS_PRIVATE_DATA_FIELD_LENGTH_ERROR_STATUS0_REG_TB_PARSER18_PRIVATE_DATA_FIELD_LENGTH_ERROR_MASK 0x00040000
-#define BCHP_XPT_FE_TB_PARSERS_PRIVATE_DATA_FIELD_LENGTH_ERROR_STATUS0_REG_TB_PARSER18_PRIVATE_DATA_FIELD_LENGTH_ERROR_SHIFT 18
-#define BCHP_XPT_FE_TB_PARSERS_PRIVATE_DATA_FIELD_LENGTH_ERROR_STATUS0_REG_TB_PARSER18_PRIVATE_DATA_FIELD_LENGTH_ERROR_DEFAULT 0x00000000
-
-/* XPT_FE :: TB_PARSERS_PRIVATE_DATA_FIELD_LENGTH_ERROR_STATUS0_REG :: TB_PARSER17_PRIVATE_DATA_FIELD_LENGTH_ERROR [17:17] */
-#define BCHP_XPT_FE_TB_PARSERS_PRIVATE_DATA_FIELD_LENGTH_ERROR_STATUS0_REG_TB_PARSER17_PRIVATE_DATA_FIELD_LENGTH_ERROR_MASK 0x00020000
-#define BCHP_XPT_FE_TB_PARSERS_PRIVATE_DATA_FIELD_LENGTH_ERROR_STATUS0_REG_TB_PARSER17_PRIVATE_DATA_FIELD_LENGTH_ERROR_SHIFT 17
-#define BCHP_XPT_FE_TB_PARSERS_PRIVATE_DATA_FIELD_LENGTH_ERROR_STATUS0_REG_TB_PARSER17_PRIVATE_DATA_FIELD_LENGTH_ERROR_DEFAULT 0x00000000
-
-/* XPT_FE :: TB_PARSERS_PRIVATE_DATA_FIELD_LENGTH_ERROR_STATUS0_REG :: TB_PARSER16_PRIVATE_DATA_FIELD_LENGTH_ERROR [16:16] */
-#define BCHP_XPT_FE_TB_PARSERS_PRIVATE_DATA_FIELD_LENGTH_ERROR_STATUS0_REG_TB_PARSER16_PRIVATE_DATA_FIELD_LENGTH_ERROR_MASK 0x00010000
-#define BCHP_XPT_FE_TB_PARSERS_PRIVATE_DATA_FIELD_LENGTH_ERROR_STATUS0_REG_TB_PARSER16_PRIVATE_DATA_FIELD_LENGTH_ERROR_SHIFT 16
-#define BCHP_XPT_FE_TB_PARSERS_PRIVATE_DATA_FIELD_LENGTH_ERROR_STATUS0_REG_TB_PARSER16_PRIVATE_DATA_FIELD_LENGTH_ERROR_DEFAULT 0x00000000
-
-/* XPT_FE :: TB_PARSERS_PRIVATE_DATA_FIELD_LENGTH_ERROR_STATUS0_REG :: TB_PARSER15_PRIVATE_DATA_FIELD_LENGTH_ERROR [15:15] */
-#define BCHP_XPT_FE_TB_PARSERS_PRIVATE_DATA_FIELD_LENGTH_ERROR_STATUS0_REG_TB_PARSER15_PRIVATE_DATA_FIELD_LENGTH_ERROR_MASK 0x00008000
-#define BCHP_XPT_FE_TB_PARSERS_PRIVATE_DATA_FIELD_LENGTH_ERROR_STATUS0_REG_TB_PARSER15_PRIVATE_DATA_FIELD_LENGTH_ERROR_SHIFT 15
-#define BCHP_XPT_FE_TB_PARSERS_PRIVATE_DATA_FIELD_LENGTH_ERROR_STATUS0_REG_TB_PARSER15_PRIVATE_DATA_FIELD_LENGTH_ERROR_DEFAULT 0x00000000
-
-/* XPT_FE :: TB_PARSERS_PRIVATE_DATA_FIELD_LENGTH_ERROR_STATUS0_REG :: TB_PARSER14_PRIVATE_DATA_FIELD_LENGTH_ERROR [14:14] */
-#define BCHP_XPT_FE_TB_PARSERS_PRIVATE_DATA_FIELD_LENGTH_ERROR_STATUS0_REG_TB_PARSER14_PRIVATE_DATA_FIELD_LENGTH_ERROR_MASK 0x00004000
-#define BCHP_XPT_FE_TB_PARSERS_PRIVATE_DATA_FIELD_LENGTH_ERROR_STATUS0_REG_TB_PARSER14_PRIVATE_DATA_FIELD_LENGTH_ERROR_SHIFT 14
-#define BCHP_XPT_FE_TB_PARSERS_PRIVATE_DATA_FIELD_LENGTH_ERROR_STATUS0_REG_TB_PARSER14_PRIVATE_DATA_FIELD_LENGTH_ERROR_DEFAULT 0x00000000
-
-/* XPT_FE :: TB_PARSERS_PRIVATE_DATA_FIELD_LENGTH_ERROR_STATUS0_REG :: TB_PARSER13_PRIVATE_DATA_FIELD_LENGTH_ERROR [13:13] */
-#define BCHP_XPT_FE_TB_PARSERS_PRIVATE_DATA_FIELD_LENGTH_ERROR_STATUS0_REG_TB_PARSER13_PRIVATE_DATA_FIELD_LENGTH_ERROR_MASK 0x00002000
-#define BCHP_XPT_FE_TB_PARSERS_PRIVATE_DATA_FIELD_LENGTH_ERROR_STATUS0_REG_TB_PARSER13_PRIVATE_DATA_FIELD_LENGTH_ERROR_SHIFT 13
-#define BCHP_XPT_FE_TB_PARSERS_PRIVATE_DATA_FIELD_LENGTH_ERROR_STATUS0_REG_TB_PARSER13_PRIVATE_DATA_FIELD_LENGTH_ERROR_DEFAULT 0x00000000
-
-/* XPT_FE :: TB_PARSERS_PRIVATE_DATA_FIELD_LENGTH_ERROR_STATUS0_REG :: TB_PARSER12_PRIVATE_DATA_FIELD_LENGTH_ERROR [12:12] */
-#define BCHP_XPT_FE_TB_PARSERS_PRIVATE_DATA_FIELD_LENGTH_ERROR_STATUS0_REG_TB_PARSER12_PRIVATE_DATA_FIELD_LENGTH_ERROR_MASK 0x00001000
-#define BCHP_XPT_FE_TB_PARSERS_PRIVATE_DATA_FIELD_LENGTH_ERROR_STATUS0_REG_TB_PARSER12_PRIVATE_DATA_FIELD_LENGTH_ERROR_SHIFT 12
-#define BCHP_XPT_FE_TB_PARSERS_PRIVATE_DATA_FIELD_LENGTH_ERROR_STATUS0_REG_TB_PARSER12_PRIVATE_DATA_FIELD_LENGTH_ERROR_DEFAULT 0x00000000
-
-/* XPT_FE :: TB_PARSERS_PRIVATE_DATA_FIELD_LENGTH_ERROR_STATUS0_REG :: TB_PARSER11_PRIVATE_DATA_FIELD_LENGTH_ERROR [11:11] */
-#define BCHP_XPT_FE_TB_PARSERS_PRIVATE_DATA_FIELD_LENGTH_ERROR_STATUS0_REG_TB_PARSER11_PRIVATE_DATA_FIELD_LENGTH_ERROR_MASK 0x00000800
-#define BCHP_XPT_FE_TB_PARSERS_PRIVATE_DATA_FIELD_LENGTH_ERROR_STATUS0_REG_TB_PARSER11_PRIVATE_DATA_FIELD_LENGTH_ERROR_SHIFT 11
-#define BCHP_XPT_FE_TB_PARSERS_PRIVATE_DATA_FIELD_LENGTH_ERROR_STATUS0_REG_TB_PARSER11_PRIVATE_DATA_FIELD_LENGTH_ERROR_DEFAULT 0x00000000
-
-/* XPT_FE :: TB_PARSERS_PRIVATE_DATA_FIELD_LENGTH_ERROR_STATUS0_REG :: TB_PARSER10_PRIVATE_DATA_FIELD_LENGTH_ERROR [10:10] */
-#define BCHP_XPT_FE_TB_PARSERS_PRIVATE_DATA_FIELD_LENGTH_ERROR_STATUS0_REG_TB_PARSER10_PRIVATE_DATA_FIELD_LENGTH_ERROR_MASK 0x00000400
-#define BCHP_XPT_FE_TB_PARSERS_PRIVATE_DATA_FIELD_LENGTH_ERROR_STATUS0_REG_TB_PARSER10_PRIVATE_DATA_FIELD_LENGTH_ERROR_SHIFT 10
-#define BCHP_XPT_FE_TB_PARSERS_PRIVATE_DATA_FIELD_LENGTH_ERROR_STATUS0_REG_TB_PARSER10_PRIVATE_DATA_FIELD_LENGTH_ERROR_DEFAULT 0x00000000
-
-/* XPT_FE :: TB_PARSERS_PRIVATE_DATA_FIELD_LENGTH_ERROR_STATUS0_REG :: TB_PARSER9_PRIVATE_DATA_FIELD_LENGTH_ERROR [09:09] */
-#define BCHP_XPT_FE_TB_PARSERS_PRIVATE_DATA_FIELD_LENGTH_ERROR_STATUS0_REG_TB_PARSER9_PRIVATE_DATA_FIELD_LENGTH_ERROR_MASK 0x00000200
-#define BCHP_XPT_FE_TB_PARSERS_PRIVATE_DATA_FIELD_LENGTH_ERROR_STATUS0_REG_TB_PARSER9_PRIVATE_DATA_FIELD_LENGTH_ERROR_SHIFT 9
-#define BCHP_XPT_FE_TB_PARSERS_PRIVATE_DATA_FIELD_LENGTH_ERROR_STATUS0_REG_TB_PARSER9_PRIVATE_DATA_FIELD_LENGTH_ERROR_DEFAULT 0x00000000
-
-/* XPT_FE :: TB_PARSERS_PRIVATE_DATA_FIELD_LENGTH_ERROR_STATUS0_REG :: TB_PARSER8_PRIVATE_DATA_FIELD_LENGTH_ERROR [08:08] */
-#define BCHP_XPT_FE_TB_PARSERS_PRIVATE_DATA_FIELD_LENGTH_ERROR_STATUS0_REG_TB_PARSER8_PRIVATE_DATA_FIELD_LENGTH_ERROR_MASK 0x00000100
-#define BCHP_XPT_FE_TB_PARSERS_PRIVATE_DATA_FIELD_LENGTH_ERROR_STATUS0_REG_TB_PARSER8_PRIVATE_DATA_FIELD_LENGTH_ERROR_SHIFT 8
-#define BCHP_XPT_FE_TB_PARSERS_PRIVATE_DATA_FIELD_LENGTH_ERROR_STATUS0_REG_TB_PARSER8_PRIVATE_DATA_FIELD_LENGTH_ERROR_DEFAULT 0x00000000
-
-/* XPT_FE :: TB_PARSERS_PRIVATE_DATA_FIELD_LENGTH_ERROR_STATUS0_REG :: TB_PARSER7_PRIVATE_DATA_FIELD_LENGTH_ERROR [07:07] */
-#define BCHP_XPT_FE_TB_PARSERS_PRIVATE_DATA_FIELD_LENGTH_ERROR_STATUS0_REG_TB_PARSER7_PRIVATE_DATA_FIELD_LENGTH_ERROR_MASK 0x00000080
-#define BCHP_XPT_FE_TB_PARSERS_PRIVATE_DATA_FIELD_LENGTH_ERROR_STATUS0_REG_TB_PARSER7_PRIVATE_DATA_FIELD_LENGTH_ERROR_SHIFT 7
-#define BCHP_XPT_FE_TB_PARSERS_PRIVATE_DATA_FIELD_LENGTH_ERROR_STATUS0_REG_TB_PARSER7_PRIVATE_DATA_FIELD_LENGTH_ERROR_DEFAULT 0x00000000
-
-/* XPT_FE :: TB_PARSERS_PRIVATE_DATA_FIELD_LENGTH_ERROR_STATUS0_REG :: TB_PARSER6_PRIVATE_DATA_FIELD_LENGTH_ERROR [06:06] */
-#define BCHP_XPT_FE_TB_PARSERS_PRIVATE_DATA_FIELD_LENGTH_ERROR_STATUS0_REG_TB_PARSER6_PRIVATE_DATA_FIELD_LENGTH_ERROR_MASK 0x00000040
-#define BCHP_XPT_FE_TB_PARSERS_PRIVATE_DATA_FIELD_LENGTH_ERROR_STATUS0_REG_TB_PARSER6_PRIVATE_DATA_FIELD_LENGTH_ERROR_SHIFT 6
-#define BCHP_XPT_FE_TB_PARSERS_PRIVATE_DATA_FIELD_LENGTH_ERROR_STATUS0_REG_TB_PARSER6_PRIVATE_DATA_FIELD_LENGTH_ERROR_DEFAULT 0x00000000
-
-/* XPT_FE :: TB_PARSERS_PRIVATE_DATA_FIELD_LENGTH_ERROR_STATUS0_REG :: TB_PARSER5_PRIVATE_DATA_FIELD_LENGTH_ERROR [05:05] */
-#define BCHP_XPT_FE_TB_PARSERS_PRIVATE_DATA_FIELD_LENGTH_ERROR_STATUS0_REG_TB_PARSER5_PRIVATE_DATA_FIELD_LENGTH_ERROR_MASK 0x00000020
-#define BCHP_XPT_FE_TB_PARSERS_PRIVATE_DATA_FIELD_LENGTH_ERROR_STATUS0_REG_TB_PARSER5_PRIVATE_DATA_FIELD_LENGTH_ERROR_SHIFT 5
-#define BCHP_XPT_FE_TB_PARSERS_PRIVATE_DATA_FIELD_LENGTH_ERROR_STATUS0_REG_TB_PARSER5_PRIVATE_DATA_FIELD_LENGTH_ERROR_DEFAULT 0x00000000
-
-/* XPT_FE :: TB_PARSERS_PRIVATE_DATA_FIELD_LENGTH_ERROR_STATUS0_REG :: TB_PARSER4_PRIVATE_DATA_FIELD_LENGTH_ERROR [04:04] */
-#define BCHP_XPT_FE_TB_PARSERS_PRIVATE_DATA_FIELD_LENGTH_ERROR_STATUS0_REG_TB_PARSER4_PRIVATE_DATA_FIELD_LENGTH_ERROR_MASK 0x00000010
-#define BCHP_XPT_FE_TB_PARSERS_PRIVATE_DATA_FIELD_LENGTH_ERROR_STATUS0_REG_TB_PARSER4_PRIVATE_DATA_FIELD_LENGTH_ERROR_SHIFT 4
-#define BCHP_XPT_FE_TB_PARSERS_PRIVATE_DATA_FIELD_LENGTH_ERROR_STATUS0_REG_TB_PARSER4_PRIVATE_DATA_FIELD_LENGTH_ERROR_DEFAULT 0x00000000
-
-/* XPT_FE :: TB_PARSERS_PRIVATE_DATA_FIELD_LENGTH_ERROR_STATUS0_REG :: TB_PARSER3_PRIVATE_DATA_FIELD_LENGTH_ERROR [03:03] */
-#define BCHP_XPT_FE_TB_PARSERS_PRIVATE_DATA_FIELD_LENGTH_ERROR_STATUS0_REG_TB_PARSER3_PRIVATE_DATA_FIELD_LENGTH_ERROR_MASK 0x00000008
-#define BCHP_XPT_FE_TB_PARSERS_PRIVATE_DATA_FIELD_LENGTH_ERROR_STATUS0_REG_TB_PARSER3_PRIVATE_DATA_FIELD_LENGTH_ERROR_SHIFT 3
-#define BCHP_XPT_FE_TB_PARSERS_PRIVATE_DATA_FIELD_LENGTH_ERROR_STATUS0_REG_TB_PARSER3_PRIVATE_DATA_FIELD_LENGTH_ERROR_DEFAULT 0x00000000
-
-/* XPT_FE :: TB_PARSERS_PRIVATE_DATA_FIELD_LENGTH_ERROR_STATUS0_REG :: TB_PARSER2_PRIVATE_DATA_FIELD_LENGTH_ERROR [02:02] */
-#define BCHP_XPT_FE_TB_PARSERS_PRIVATE_DATA_FIELD_LENGTH_ERROR_STATUS0_REG_TB_PARSER2_PRIVATE_DATA_FIELD_LENGTH_ERROR_MASK 0x00000004
-#define BCHP_XPT_FE_TB_PARSERS_PRIVATE_DATA_FIELD_LENGTH_ERROR_STATUS0_REG_TB_PARSER2_PRIVATE_DATA_FIELD_LENGTH_ERROR_SHIFT 2
-#define BCHP_XPT_FE_TB_PARSERS_PRIVATE_DATA_FIELD_LENGTH_ERROR_STATUS0_REG_TB_PARSER2_PRIVATE_DATA_FIELD_LENGTH_ERROR_DEFAULT 0x00000000
-
-/* XPT_FE :: TB_PARSERS_PRIVATE_DATA_FIELD_LENGTH_ERROR_STATUS0_REG :: TB_PARSER1_PRIVATE_DATA_FIELD_LENGTH_ERROR [01:01] */
-#define BCHP_XPT_FE_TB_PARSERS_PRIVATE_DATA_FIELD_LENGTH_ERROR_STATUS0_REG_TB_PARSER1_PRIVATE_DATA_FIELD_LENGTH_ERROR_MASK 0x00000002
-#define BCHP_XPT_FE_TB_PARSERS_PRIVATE_DATA_FIELD_LENGTH_ERROR_STATUS0_REG_TB_PARSER1_PRIVATE_DATA_FIELD_LENGTH_ERROR_SHIFT 1
-#define BCHP_XPT_FE_TB_PARSERS_PRIVATE_DATA_FIELD_LENGTH_ERROR_STATUS0_REG_TB_PARSER1_PRIVATE_DATA_FIELD_LENGTH_ERROR_DEFAULT 0x00000000
-
-/* XPT_FE :: TB_PARSERS_PRIVATE_DATA_FIELD_LENGTH_ERROR_STATUS0_REG :: TB_PARSER0_PRIVATE_DATA_FIELD_LENGTH_ERROR [00:00] */
-#define BCHP_XPT_FE_TB_PARSERS_PRIVATE_DATA_FIELD_LENGTH_ERROR_STATUS0_REG_TB_PARSER0_PRIVATE_DATA_FIELD_LENGTH_ERROR_MASK 0x00000001
-#define BCHP_XPT_FE_TB_PARSERS_PRIVATE_DATA_FIELD_LENGTH_ERROR_STATUS0_REG_TB_PARSER0_PRIVATE_DATA_FIELD_LENGTH_ERROR_SHIFT 0
-#define BCHP_XPT_FE_TB_PARSERS_PRIVATE_DATA_FIELD_LENGTH_ERROR_STATUS0_REG_TB_PARSER0_PRIVATE_DATA_FIELD_LENGTH_ERROR_DEFAULT 0x00000000
-
-/***************************************************************************
- *PID_TABLE_%i - Data Transport Primary PID Table
- ***************************************************************************/
-#define BCHP_XPT_FE_PID_TABLE_i_ARRAY_BASE 0x00a21000
-#define BCHP_XPT_FE_PID_TABLE_i_ARRAY_START 0
-#define BCHP_XPT_FE_PID_TABLE_i_ARRAY_END 1023
-#define BCHP_XPT_FE_PID_TABLE_i_ARRAY_ELEMENT_SIZE 32
-
-/***************************************************************************
- *PID_TABLE_%i - Data Transport Primary PID Table
- ***************************************************************************/
-/* XPT_FE :: PID_TABLE_i :: SECURITY_OUTPUT_PIPE_SEL [31:30] */
-#define BCHP_XPT_FE_PID_TABLE_i_SECURITY_OUTPUT_PIPE_SEL_MASK 0xc0000000
-#define BCHP_XPT_FE_PID_TABLE_i_SECURITY_OUTPUT_PIPE_SEL_SHIFT 30
-
-/* XPT_FE :: PID_TABLE_i :: PARSER_OUTPUT_PIPE_SEL [29:28] */
-#define BCHP_XPT_FE_PID_TABLE_i_PARSER_OUTPUT_PIPE_SEL_MASK 0x30000000
-#define BCHP_XPT_FE_PID_TABLE_i_PARSER_OUTPUT_PIPE_SEL_SHIFT 28
-
-/* XPT_FE :: PID_TABLE_i :: IGNORE_PID_VERSION [27:27] */
-#define BCHP_XPT_FE_PID_TABLE_i_IGNORE_PID_VERSION_MASK 0x08000000
-#define BCHP_XPT_FE_PID_TABLE_i_IGNORE_PID_VERSION_SHIFT 27
-
-/* XPT_FE :: PID_TABLE_i :: PID_VERSION [26:24] */
-#define BCHP_XPT_FE_PID_TABLE_i_PID_VERSION_MASK 0x07000000
-#define BCHP_XPT_FE_PID_TABLE_i_PID_VERSION_SHIFT 24
-
-/* XPT_FE :: PID_TABLE_i :: PLAYBACK_FE_SEL [23:23] */
-#define BCHP_XPT_FE_PID_TABLE_i_PLAYBACK_FE_SEL_MASK 0x00800000
-#define BCHP_XPT_FE_PID_TABLE_i_PLAYBACK_FE_SEL_SHIFT 23
-
-/* union - case INPUT_BAND_PARSER [22:16] */
-/* XPT_FE :: PID_TABLE_i :: INPUT_BAND_PARSER :: PID_CHANNEL_INPUT_SELECT [22:16] */
-#define BCHP_XPT_FE_PID_TABLE_i_INPUT_BAND_PARSER_PID_CHANNEL_INPUT_SELECT_MASK 0x007f0000
-#define BCHP_XPT_FE_PID_TABLE_i_INPUT_BAND_PARSER_PID_CHANNEL_INPUT_SELECT_SHIFT 16
-
-/* union - case PLAYBACK_BAND_PARSER [22:16] */
-/* XPT_FE :: PID_TABLE_i :: PLAYBACK_BAND_PARSER :: PID_CHANNEL_INPUT_SELECT [22:16] */
-#define BCHP_XPT_FE_PID_TABLE_i_PLAYBACK_BAND_PARSER_PID_CHANNEL_INPUT_SELECT_MASK 0x007f0000
-#define BCHP_XPT_FE_PID_TABLE_i_PLAYBACK_BAND_PARSER_PID_CHANNEL_INPUT_SELECT_SHIFT 16
-
-/* XPT_FE :: PID_TABLE_i :: MPOD_BYPASS_EN [15:15] */
-#define BCHP_XPT_FE_PID_TABLE_i_MPOD_BYPASS_EN_MASK 0x00008000
-#define BCHP_XPT_FE_PID_TABLE_i_MPOD_BYPASS_EN_SHIFT 15
-
-/* XPT_FE :: PID_TABLE_i :: PID_CHANNEL_ENABLE [14:14] */
-#define BCHP_XPT_FE_PID_TABLE_i_PID_CHANNEL_ENABLE_MASK 0x00004000
-#define BCHP_XPT_FE_PID_TABLE_i_PID_CHANNEL_ENABLE_SHIFT 14
-
-/* XPT_FE :: PID_TABLE_i :: ENABLE_HD_FILTER [13:13] */
-#define BCHP_XPT_FE_PID_TABLE_i_ENABLE_HD_FILTER_MASK 0x00002000
-#define BCHP_XPT_FE_PID_TABLE_i_ENABLE_HD_FILTER_SHIFT 13
-
-/* union - case HD_FILT_EN [12:00] */
-/* XPT_FE :: PID_TABLE_i :: HD_FILT_EN :: HD_FILTER_TYPE [12:12] */
-#define BCHP_XPT_FE_PID_TABLE_i_HD_FILT_EN_HD_FILTER_TYPE_MASK 0x00001000
-#define BCHP_XPT_FE_PID_TABLE_i_HD_FILT_EN_HD_FILTER_TYPE_SHIFT 12
-
-/* XPT_FE :: PID_TABLE_i :: HD_FILT_EN :: PID_CHANNEL_SCID [11:00] */
-#define BCHP_XPT_FE_PID_TABLE_i_HD_FILT_EN_PID_CHANNEL_SCID_MASK 0x00000fff
-#define BCHP_XPT_FE_PID_TABLE_i_HD_FILT_EN_PID_CHANNEL_SCID_SHIFT 0
-
-/* union - case HD_FILT_DIS [12:00] */
-/* XPT_FE :: PID_TABLE_i :: HD_FILT_DIS :: PID_CHANNEL_PID [12:00] */
-#define BCHP_XPT_FE_PID_TABLE_i_HD_FILT_DIS_PID_CHANNEL_PID_MASK 0x00001fff
-#define BCHP_XPT_FE_PID_TABLE_i_HD_FILT_DIS_PID_CHANNEL_PID_SHIFT 0
-
-
-/***************************************************************************
- *SPID_TABLE_%i - Data Transport Secondary PID Table
- ***************************************************************************/
-#define BCHP_XPT_FE_SPID_TABLE_i_ARRAY_BASE 0x00a23000
-#define BCHP_XPT_FE_SPID_TABLE_i_ARRAY_START 0
-#define BCHP_XPT_FE_SPID_TABLE_i_ARRAY_END 1023
-#define BCHP_XPT_FE_SPID_TABLE_i_ARRAY_ELEMENT_SIZE 32
-
-/***************************************************************************
- *SPID_TABLE_%i - Data Transport Secondary PID Table
- ***************************************************************************/
-/* XPT_FE :: SPID_TABLE_i :: PID_DESTINATION [31:24] */
-#define BCHP_XPT_FE_SPID_TABLE_i_PID_DESTINATION_MASK 0xff000000
-#define BCHP_XPT_FE_SPID_TABLE_i_PID_DESTINATION_SHIFT 24
-
-/* XPT_FE :: SPID_TABLE_i :: TSIO_BYPASS_EN [23:23] */
-#define BCHP_XPT_FE_SPID_TABLE_i_TSIO_BYPASS_EN_MASK 0x00800000
-#define BCHP_XPT_FE_SPID_TABLE_i_TSIO_BYPASS_EN_SHIFT 23
-
-/* XPT_FE :: SPID_TABLE_i :: SPID_VERSION [22:20] */
-#define BCHP_XPT_FE_SPID_TABLE_i_SPID_VERSION_MASK 0x00700000
-#define BCHP_XPT_FE_SPID_TABLE_i_SPID_VERSION_SHIFT 20
-
-/* XPT_FE :: SPID_TABLE_i :: SPID_MODE [19:16] */
-#define BCHP_XPT_FE_SPID_TABLE_i_SPID_MODE_MASK 0x000f0000
-#define BCHP_XPT_FE_SPID_TABLE_i_SPID_MODE_SHIFT 16
-#define BCHP_XPT_FE_SPID_TABLE_i_SPID_MODE_DISABLE_SPID 0
-#define BCHP_XPT_FE_SPID_TABLE_i_SPID_MODE_PSG_PKT_SUBSTITUTION_NQ 1
-#define BCHP_XPT_FE_SPID_TABLE_i_SPID_MODE_PSG_PKT_SUBSTITUTION_Q 2
-#define BCHP_XPT_FE_SPID_TABLE_i_SPID_MODE_PSG_PKT_INSERTION 3
-#define BCHP_XPT_FE_SPID_TABLE_i_SPID_MODE_PSG_PKT_INSERTION_DELETION 4
-#define BCHP_XPT_FE_SPID_TABLE_i_SPID_MODE_PID_MERGE1 5
-#define BCHP_XPT_FE_SPID_TABLE_i_SPID_MODE_PID_MERGE2 6
-#define BCHP_XPT_FE_SPID_TABLE_i_SPID_MODE_PID_REMAP 7
-#define BCHP_XPT_FE_SPID_TABLE_i_SPID_MODE_STREAM_ID_FILTER 8
-#define BCHP_XPT_FE_SPID_TABLE_i_SPID_MODE_PID_MERGE0 9
-#define BCHP_XPT_FE_SPID_TABLE_i_SPID_MODE_STREAM_ID_RANGE 10
-#define BCHP_XPT_FE_SPID_TABLE_i_SPID_MODE_STREAM_ID_EXTENSION_FILTER 12
-#define BCHP_XPT_FE_SPID_TABLE_i_SPID_MODE_SUBSTREAM_ID_FILTER 14
-
-/* union - case STREAM_ID_FILTER [15:00] */
-/* XPT_FE :: SPID_TABLE_i :: STREAM_ID_FILTER :: STREAM_ID [15:08] */
-#define BCHP_XPT_FE_SPID_TABLE_i_STREAM_ID_FILTER_STREAM_ID_MASK 0x0000ff00
-#define BCHP_XPT_FE_SPID_TABLE_i_STREAM_ID_FILTER_STREAM_ID_SHIFT 8
-
-/* XPT_FE :: SPID_TABLE_i :: STREAM_ID_FILTER :: reserved0 [07:00] */
-#define BCHP_XPT_FE_SPID_TABLE_i_STREAM_ID_FILTER_reserved0_MASK 0x000000ff
-#define BCHP_XPT_FE_SPID_TABLE_i_STREAM_ID_FILTER_reserved0_SHIFT 0
-
-/* union - case STREAM_ID_RANGE [15:00] */
-/* XPT_FE :: SPID_TABLE_i :: STREAM_ID_RANGE :: STREAM_ID_HI [15:08] */
-#define BCHP_XPT_FE_SPID_TABLE_i_STREAM_ID_RANGE_STREAM_ID_HI_MASK 0x0000ff00
-#define BCHP_XPT_FE_SPID_TABLE_i_STREAM_ID_RANGE_STREAM_ID_HI_SHIFT 8
-
-/* XPT_FE :: SPID_TABLE_i :: STREAM_ID_RANGE :: STREAM_ID_LO [07:00] */
-#define BCHP_XPT_FE_SPID_TABLE_i_STREAM_ID_RANGE_STREAM_ID_LO_MASK 0x000000ff
-#define BCHP_XPT_FE_SPID_TABLE_i_STREAM_ID_RANGE_STREAM_ID_LO_SHIFT 0
-
-/* union - case STREAM_ID_EXTENSION_FILTER [15:00] */
-/* XPT_FE :: SPID_TABLE_i :: STREAM_ID_EXTENSION_FILTER :: STREAM_ID [15:08] */
-#define BCHP_XPT_FE_SPID_TABLE_i_STREAM_ID_EXTENSION_FILTER_STREAM_ID_MASK 0x0000ff00
-#define BCHP_XPT_FE_SPID_TABLE_i_STREAM_ID_EXTENSION_FILTER_STREAM_ID_SHIFT 8
-
-/* XPT_FE :: SPID_TABLE_i :: STREAM_ID_EXTENSION_FILTER :: STREAM_ID_EXTENSION [07:00] */
-#define BCHP_XPT_FE_SPID_TABLE_i_STREAM_ID_EXTENSION_FILTER_STREAM_ID_EXTENSION_MASK 0x000000ff
-#define BCHP_XPT_FE_SPID_TABLE_i_STREAM_ID_EXTENSION_FILTER_STREAM_ID_EXTENSION_SHIFT 0
-
-/* union - case SUBSTREAM_ID_FILTER [15:00] */
-/* XPT_FE :: SPID_TABLE_i :: SUBSTREAM_ID_FILTER :: STREAM_ID [15:08] */
-#define BCHP_XPT_FE_SPID_TABLE_i_SUBSTREAM_ID_FILTER_STREAM_ID_MASK 0x0000ff00
-#define BCHP_XPT_FE_SPID_TABLE_i_SUBSTREAM_ID_FILTER_STREAM_ID_SHIFT 8
-
-/* XPT_FE :: SPID_TABLE_i :: SUBSTREAM_ID_FILTER :: SUBSTREAM_ID [07:00] */
-#define BCHP_XPT_FE_SPID_TABLE_i_SUBSTREAM_ID_FILTER_SUBSTREAM_ID_MASK 0x000000ff
-#define BCHP_XPT_FE_SPID_TABLE_i_SUBSTREAM_ID_FILTER_SUBSTREAM_ID_SHIFT 0
-
-/* union - case PID_FUNCTIONS [15:00] */
-/* XPT_FE :: SPID_TABLE_i :: PID_FUNCTIONS :: reserved0 [15:13] */
-#define BCHP_XPT_FE_SPID_TABLE_i_PID_FUNCTIONS_reserved0_MASK 0x0000e000
-#define BCHP_XPT_FE_SPID_TABLE_i_PID_FUNCTIONS_reserved0_SHIFT 13
-
-/* XPT_FE :: SPID_TABLE_i :: PID_FUNCTIONS :: SPID_CHANNEL_PID [12:00] */
-#define BCHP_XPT_FE_SPID_TABLE_i_PID_FUNCTIONS_SPID_CHANNEL_PID_MASK 0x00001fff
-#define BCHP_XPT_FE_SPID_TABLE_i_PID_FUNCTIONS_SPID_CHANNEL_PID_SHIFT 0
-
-
-/***************************************************************************
- *SPID_EXT_TABLE_%i - Data Transport Secondary PID Extended Table
- ***************************************************************************/
-#define BCHP_XPT_FE_SPID_EXT_TABLE_i_ARRAY_BASE 0x00a25000
-#define BCHP_XPT_FE_SPID_EXT_TABLE_i_ARRAY_START 0
-#define BCHP_XPT_FE_SPID_EXT_TABLE_i_ARRAY_END 1023
-#define BCHP_XPT_FE_SPID_EXT_TABLE_i_ARRAY_ELEMENT_SIZE 32
-
-/***************************************************************************
- *SPID_EXT_TABLE_%i - Data Transport Secondary PID Extended Table
- ***************************************************************************/
-/* XPT_FE :: SPID_EXT_TABLE_i :: reserved0 [31:08] */
-#define BCHP_XPT_FE_SPID_EXT_TABLE_i_reserved0_MASK 0xffffff00
-#define BCHP_XPT_FE_SPID_EXT_TABLE_i_reserved0_SHIFT 8
-
-/* XPT_FE :: SPID_EXT_TABLE_i :: PID_DESTINATION_EXT [07:00] */
-#define BCHP_XPT_FE_SPID_EXT_TABLE_i_PID_DESTINATION_EXT_MASK 0x000000ff
-#define BCHP_XPT_FE_SPID_EXT_TABLE_i_PID_DESTINATION_EXT_SHIFT 0
-
-
-#endif /* #ifndef BCHP_XPT_FE_H__ */
-
-/* End of File */
diff --git a/include/linux/brcmstb/7366b0/bchp_xpt_memdma_mcpb.h b/include/linux/brcmstb/7366b0/bchp_xpt_memdma_mcpb.h
deleted file mode 100644
index 07d2265..0000000
--- a/include/linux/brcmstb/7366b0/bchp_xpt_memdma_mcpb.h
+++ /dev/null
@@ -1,4737 +0,0 @@
-/***************************************************************************
- * Copyright (c) 1999-2014, Broadcom Corporation
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
- *
- * Module Description:
- * DO NOT EDIT THIS FILE DIRECTLY
- *
- * This module was generated magically with RDB from a source description
- * file. You must edit the source file for changes to be made to this file.
- *
- *
- * Date: Generated on Sat Apr 12 03:17:53 2014
- * Full Compile MD5 Checksum 5f2af4819d5a3039f3fe1938baf5d1f2
- * (minus title and desc)
- * MD5 Checksum afc8344db5db4960ac3645d27d001fbc
- *
- * Compiled with: RDB Utility combo_header.pl
- * RDB Parser 3.0
- * unknown unknown
- * Perl Interpreter 5.008008
- * Operating System linux
- *
- * Revision History:
- *
- * $brcm_Log: $
- *
- ***************************************************************************/
-
-#ifndef BCHP_XPT_MEMDMA_MCPB_H__
-#define BCHP_XPT_MEMDMA_MCPB_H__
-
-/***************************************************************************
- *XPT_MEMDMA_MCPB - MCPB Top Control Registers
- ***************************************************************************/
-#define BCHP_XPT_MEMDMA_MCPB_RUN_SET_CLEAR 0x00a60800 /* Set and Clear for the RUN bit */
-#define BCHP_XPT_MEMDMA_MCPB_WAKE_SET 0x00a60804 /* Set for the WAKE bit */
-#define BCHP_XPT_MEMDMA_MCPB_WAKE_MODE_SET_CLEAR 0x00a60808 /* Set and Clear for the WAKE_MODE bit */
-#define BCHP_XPT_MEMDMA_MCPB_BUFF_DATA_RDY_SET 0x00a6080c /* Set for the BUFF_DATA_RDY bit */
-#define BCHP_XPT_MEMDMA_MCPB_PAUSE_AT_DESC_READ_CLEAR 0x00a60810 /* Clear for the PAUSE_AT_DESC_READ bit */
-#define BCHP_XPT_MEMDMA_MCPB_PAUSE_AT_DESC_END_CLEAR 0x00a60814 /* Clear for the PAUSE_AT_DESC_END bit */
-#define BCHP_XPT_MEMDMA_MCPB_PAUSE_AFTER_GROUP_PACKETS_CLEAR 0x00a60818 /* Clear for the PAUSE_AFTER_GROUP_PACKETS bit */
-#define BCHP_XPT_MEMDMA_MCPB_CRC_COMPARE_ERROR_PAUSE_CLEAR 0x00a6081c /* Clear for the CRC_COMPARE_ERROR_PAUSE bit */
-#define BCHP_XPT_MEMDMA_MCPB_MICRO_PAUSE_SET_CLEAR 0x00a60820 /* Set and Clear for the MICRO_PAUSE bit */
-#define BCHP_XPT_MEMDMA_MCPB_RUN_STATUS_0_31 0x00a60824 /* Run status for all the PB channels */
-#define BCHP_XPT_MEMDMA_MCPB_WAKE_STATUS_0_31 0x00a60828 /* Wake status for all the PB channels */
-#define BCHP_XPT_MEMDMA_MCPB_WAKE_MODE_STATUS_0_31 0x00a6082c /* Wake Mode status for all the PB channels */
-#define BCHP_XPT_MEMDMA_MCPB_PAUSE_AT_DESC_READ_STATUS_0_31 0x00a60830 /* Pause at descriptor read status for all the PB channels */
-#define BCHP_XPT_MEMDMA_MCPB_PAUSE_AT_DESC_END_STATUS_0_31 0x00a60834 /* Pause at descriptor end status for all the PB channels */
-#define BCHP_XPT_MEMDMA_MCPB_PAUSE_AFTER_GROUP_PACKETS_STATUS_0_31 0x00a60838 /* Pause after group of packets status for all the PB channels */
-#define BCHP_XPT_MEMDMA_MCPB_CRC_COMPARE_ERROR_PAUSE_STATUS_0_31 0x00a6083c /* CRC compare error pause status for all the PB channels */
-#define BCHP_XPT_MEMDMA_MCPB_MICRO_PAUSE_STATUS_0_31 0x00a60840 /* Micro Pause status for all the PB channels */
-#define BCHP_XPT_MEMDMA_MCPB_FINAL_PAUSE_STATUS_0_31 0x00a60844 /* Final Pause status for all the PB channels */
-#define BCHP_XPT_MEMDMA_MCPB_HW_PAUSE_STATUS_0_31 0x00a60848 /* Hardware Pause status for all the PB channels */
-#define BCHP_XPT_MEMDMA_MCPB_DESC_RD_IN_PROGRESS_0_31 0x00a6084c /* Descriptor Read in Progress status flag */
-#define BCHP_XPT_MEMDMA_MCPB_DATA_RD_IN_PROGRESS_0_31 0x00a60850 /* Data Read in Progress status flag */
-#define BCHP_XPT_MEMDMA_MCPB_BBUFF_RD_IN_PROGRESS_0_31 0x00a60854 /* Burst Buffer Read in Progress status flag */
-#define BCHP_XPT_MEMDMA_MCPB_LAST_DESC_REACHED_0_31 0x00a60858 /* Last Descriptor Reached status flag */
-#define BCHP_XPT_MEMDMA_MCPB_BUFF_DATA_RDY_0_31 0x00a6085c /* Buffer data ready status flag */
-#define BCHP_XPT_MEMDMA_MCPB_FIRST_DATA_RD_OPN_PRIORITY_0_31 0x00a60860 /* First data read operation priority flag */
-#define BCHP_XPT_MEMDMA_MCPB_RUN_INVALID_SET_CLEAR 0x00a60864 /* Set and Clear Run Invalid */
-#define BCHP_XPT_MEMDMA_MCPB_RUN_INVALID_STATUS_0_31 0x00a60868 /* Run Invalid status */
-#define BCHP_XPT_MEMDMA_MCPB_CHANNEL_PRIORITY_SET 0x00a6086c /* Set priority for channel arbitration */
-#define BCHP_XPT_MEMDMA_MCPB_CHANNEL_PRIORITY_STATUS_0_15 0x00a60870 /* Channel priority status for channels 0 to 15 */
-#define BCHP_XPT_MEMDMA_MCPB_CHANNEL_PRIORITY_STATUS_16_31 0x00a60874 /* Channel priority status for channels 16 to 31 */
-#define BCHP_XPT_MEMDMA_MCPB_BAND_PAUSE_MAPPING_VECTOR_0 0x00a60878 /* MCPB Band pause mapping vector for channel 0 */
-#define BCHP_XPT_MEMDMA_MCPB_BAND_PAUSE_MAPPING_VECTOR_1 0x00a6087c /* MCPB Band pause mapping vector for channel 1 */
-#define BCHP_XPT_MEMDMA_MCPB_BAND_PAUSE_MAPPING_VECTOR_2 0x00a60880 /* MCPB Band pause mapping vector for channel 2 */
-#define BCHP_XPT_MEMDMA_MCPB_BAND_PAUSE_MAPPING_VECTOR_3 0x00a60884 /* MCPB Band pause mapping vector for channel 3 */
-#define BCHP_XPT_MEMDMA_MCPB_BAND_PAUSE_MAPPING_VECTOR_4 0x00a60888 /* MCPB Band pause mapping vector for channel 4 */
-#define BCHP_XPT_MEMDMA_MCPB_BAND_PAUSE_MAPPING_VECTOR_5 0x00a6088c /* MCPB Band pause mapping vector for channel 5 */
-#define BCHP_XPT_MEMDMA_MCPB_BAND_PAUSE_MAPPING_VECTOR_6 0x00a60890 /* MCPB Band pause mapping vector for channel 6 */
-#define BCHP_XPT_MEMDMA_MCPB_BAND_PAUSE_MAPPING_VECTOR_7 0x00a60894 /* MCPB Band pause mapping vector for channel 7 */
-#define BCHP_XPT_MEMDMA_MCPB_BAND_PAUSE_MAPPING_VECTOR_8 0x00a60898 /* MCPB Band pause mapping vector for channel 8 */
-#define BCHP_XPT_MEMDMA_MCPB_BAND_PAUSE_MAPPING_VECTOR_9 0x00a6089c /* MCPB Band pause mapping vector for channel 9 */
-#define BCHP_XPT_MEMDMA_MCPB_BAND_PAUSE_MAPPING_VECTOR_10 0x00a608a0 /* MCPB Band pause mapping vector for channel 10 */
-#define BCHP_XPT_MEMDMA_MCPB_BAND_PAUSE_MAPPING_VECTOR_11 0x00a608a4 /* MCPB Band pause mapping vector for channel 11 */
-#define BCHP_XPT_MEMDMA_MCPB_BAND_PAUSE_MAPPING_VECTOR_12 0x00a608a8 /* MCPB Band pause mapping vector for channel 12 */
-#define BCHP_XPT_MEMDMA_MCPB_BAND_PAUSE_MAPPING_VECTOR_13 0x00a608ac /* MCPB Band pause mapping vector for channel 13 */
-#define BCHP_XPT_MEMDMA_MCPB_BAND_PAUSE_MAPPING_VECTOR_14 0x00a608b0 /* MCPB Band pause mapping vector for channel 14 */
-#define BCHP_XPT_MEMDMA_MCPB_BAND_PAUSE_MAPPING_VECTOR_15 0x00a608b4 /* MCPB Band pause mapping vector for channel 15 */
-#define BCHP_XPT_MEMDMA_MCPB_BAND_PAUSE_MAPPING_VECTOR_16 0x00a608b8 /* MCPB Band pause mapping vector for channel 16 */
-#define BCHP_XPT_MEMDMA_MCPB_BAND_PAUSE_MAPPING_VECTOR_17 0x00a608bc /* MCPB Band pause mapping vector for channel 17 */
-#define BCHP_XPT_MEMDMA_MCPB_BAND_PAUSE_MAPPING_VECTOR_18 0x00a608c0 /* MCPB Band pause mapping vector for channel 18 */
-#define BCHP_XPT_MEMDMA_MCPB_BAND_PAUSE_MAPPING_VECTOR_19 0x00a608c4 /* MCPB Band pause mapping vector for channel 19 */
-#define BCHP_XPT_MEMDMA_MCPB_BAND_PAUSE_MAPPING_VECTOR_20 0x00a608c8 /* MCPB Band pause mapping vector for channel 20 */
-#define BCHP_XPT_MEMDMA_MCPB_BAND_PAUSE_MAPPING_VECTOR_21 0x00a608cc /* MCPB Band pause mapping vector for channel 21 */
-#define BCHP_XPT_MEMDMA_MCPB_BAND_PAUSE_MAPPING_VECTOR_22 0x00a608d0 /* MCPB Band pause mapping vector for channel 22 */
-#define BCHP_XPT_MEMDMA_MCPB_BAND_PAUSE_MAPPING_VECTOR_23 0x00a608d4 /* MCPB Band pause mapping vector for channel 23 */
-#define BCHP_XPT_MEMDMA_MCPB_BAND_PAUSE_MAPPING_VECTOR_24 0x00a608d8 /* MCPB Band pause mapping vector for channel 24 */
-#define BCHP_XPT_MEMDMA_MCPB_BAND_PAUSE_MAPPING_VECTOR_25 0x00a608dc /* MCPB Band pause mapping vector for channel 25 */
-#define BCHP_XPT_MEMDMA_MCPB_BAND_PAUSE_MAPPING_VECTOR_26 0x00a608e0 /* MCPB Band pause mapping vector for channel 26 */
-#define BCHP_XPT_MEMDMA_MCPB_BAND_PAUSE_MAPPING_VECTOR_27 0x00a608e4 /* MCPB Band pause mapping vector for channel 27 */
-#define BCHP_XPT_MEMDMA_MCPB_BAND_PAUSE_MAPPING_VECTOR_28 0x00a608e8 /* MCPB Band pause mapping vector for channel 28 */
-#define BCHP_XPT_MEMDMA_MCPB_BAND_PAUSE_MAPPING_VECTOR_29 0x00a608ec /* MCPB Band pause mapping vector for channel 29 */
-#define BCHP_XPT_MEMDMA_MCPB_BAND_PAUSE_MAPPING_VECTOR_30 0x00a608f0 /* MCPB Band pause mapping vector for channel 30 */
-#define BCHP_XPT_MEMDMA_MCPB_BAND_PAUSE_MAPPING_VECTOR_31 0x00a608f4 /* MCPB Band pause mapping vector for channel 31 */
-#define BCHP_XPT_MEMDMA_MCPB_SP_GLOBAL_CFG_REG0 0x00a608f8 /* Channel independent Stream processor specific information */
-#define BCHP_XPT_MEMDMA_MCPB_SP_GLOBAL_CFG_REG1 0x00a608fc /* Channel independent Stream processor specific information */
-#define BCHP_XPT_MEMDMA_MCPB_TMEU_CHANNEL_BYPASS_SET_CLEAR 0x00a60900 /* Set and clear for TMEU channel bypass bit */
-#define BCHP_XPT_MEMDMA_MCPB_TMEU_CHANNEL_BYPASS_STATUS_0_31 0x00a60904 /* TMEU channel bypass status */
-#define BCHP_XPT_MEMDMA_MCPB_GPC0_CTRL 0x00a6090c /* MCPB GPC0 Control information */
-#define BCHP_XPT_MEMDMA_MCPB_GPC0_CURR_COUNTER_VAL 0x00a60910 /* MCPB GPC0 Current counter value */
-#define BCHP_XPT_MEMDMA_MCPB_GPC0_PAUSE_0_31 0x00a60914 /* MCPB GPC0 Current pause value */
-#define BCHP_XPT_MEMDMA_MCPB_GPC1_CTRL 0x00a60918 /* MCPB GPC1 Control information */
-#define BCHP_XPT_MEMDMA_MCPB_GPC1_CURR_COUNTER_VAL 0x00a6091c /* MCPB GPC1 Current counter value */
-#define BCHP_XPT_MEMDMA_MCPB_GPC1_PAUSE_0_31 0x00a60920 /* MCPB GPC1 Current pause value */
-#define BCHP_XPT_MEMDMA_MCPB_GPC2_CTRL 0x00a60924 /* MCPB GPC2 Control information */
-#define BCHP_XPT_MEMDMA_MCPB_GPC2_CURR_COUNTER_VAL 0x00a60928 /* MCPB GPC2 Current counter value */
-#define BCHP_XPT_MEMDMA_MCPB_GPC2_PAUSE_0_31 0x00a6092c /* MCPB GPC2 Current pause value */
-#define BCHP_XPT_MEMDMA_MCPB_GPC3_CTRL 0x00a60930 /* MCPB GPC3 Control information */
-#define BCHP_XPT_MEMDMA_MCPB_GPC3_CURR_COUNTER_VAL 0x00a60934 /* MCPB GPC3 Current counter value */
-#define BCHP_XPT_MEMDMA_MCPB_GPC3_PAUSE_0_31 0x00a60938 /* MCPB GPC3 Current pause value */
-#define BCHP_XPT_MEMDMA_MCPB_GPC4_CTRL 0x00a6093c /* MCPB GPC4 Control information */
-#define BCHP_XPT_MEMDMA_MCPB_GPC4_CURR_COUNTER_VAL 0x00a60940 /* MCPB GPC4 Current counter value */
-#define BCHP_XPT_MEMDMA_MCPB_GPC4_PAUSE_0_31 0x00a60944 /* MCPB GPC4 Current pause value */
-#define BCHP_XPT_MEMDMA_MCPB_GPC5_CTRL 0x00a60948 /* MCPB GPC5 Control information */
-#define BCHP_XPT_MEMDMA_MCPB_GPC5_CURR_COUNTER_VAL 0x00a6094c /* MCPB GPC5 Current counter value */
-#define BCHP_XPT_MEMDMA_MCPB_GPC5_PAUSE_0_31 0x00a60950 /* MCPB GPC5 Current pause value */
-#define BCHP_XPT_MEMDMA_MCPB_GPC6_CTRL 0x00a60954 /* MCPB GPC6 Control information */
-#define BCHP_XPT_MEMDMA_MCPB_GPC6_CURR_COUNTER_VAL 0x00a60958 /* MCPB GPC6 Current counter value */
-#define BCHP_XPT_MEMDMA_MCPB_GPC6_PAUSE_0_31 0x00a6095c /* MCPB GPC6 Current pause value */
-#define BCHP_XPT_MEMDMA_MCPB_GPC7_CTRL 0x00a60960 /* MCPB GPC7 Control information */
-#define BCHP_XPT_MEMDMA_MCPB_GPC7_CURR_COUNTER_VAL 0x00a60964 /* MCPB GPC7 Current counter value */
-#define BCHP_XPT_MEMDMA_MCPB_GPC7_PAUSE_0_31 0x00a60968 /* MCPB GPC7 Current pause value */
-#define BCHP_XPT_MEMDMA_MCPB_GPC8_CTRL 0x00a6096c /* MCPB GPC8 Control information */
-#define BCHP_XPT_MEMDMA_MCPB_GPC8_CURR_COUNTER_VAL 0x00a60970 /* MCPB GPC8 Current counter value */
-#define BCHP_XPT_MEMDMA_MCPB_GPC8_PAUSE_0_31 0x00a60974 /* MCPB GPC8 Current pause value */
-#define BCHP_XPT_MEMDMA_MCPB_GPC9_CTRL 0x00a60978 /* MCPB GPC9 Control information */
-#define BCHP_XPT_MEMDMA_MCPB_GPC9_CURR_COUNTER_VAL 0x00a6097c /* MCPB GPC9 Current counter value */
-#define BCHP_XPT_MEMDMA_MCPB_GPC9_PAUSE_0_31 0x00a60980 /* MCPB GPC9 Current pause value */
-#define BCHP_XPT_MEMDMA_MCPB_GPC10_CTRL 0x00a60984 /* MCPB GPC10 Control information */
-#define BCHP_XPT_MEMDMA_MCPB_GPC10_CURR_COUNTER_VAL 0x00a60988 /* MCPB GPC10 Current counter value */
-#define BCHP_XPT_MEMDMA_MCPB_GPC10_PAUSE_0_31 0x00a6098c /* MCPB GPC10 Current pause value */
-#define BCHP_XPT_MEMDMA_MCPB_GPC11_CTRL 0x00a60990 /* MCPB GPC11 Control information */
-#define BCHP_XPT_MEMDMA_MCPB_GPC11_CURR_COUNTER_VAL 0x00a60994 /* MCPB GPC11 Current counter value */
-#define BCHP_XPT_MEMDMA_MCPB_GPC11_PAUSE_0_31 0x00a60998 /* MCPB GPC11 Current pause value */
-#define BCHP_XPT_MEMDMA_MCPB_GPC12_CTRL 0x00a6099c /* MCPB GPC12 Control information */
-#define BCHP_XPT_MEMDMA_MCPB_GPC12_CURR_COUNTER_VAL 0x00a609a0 /* MCPB GPC12 Current counter value */
-#define BCHP_XPT_MEMDMA_MCPB_GPC12_PAUSE_0_31 0x00a609a4 /* MCPB GPC12 Current pause value */
-#define BCHP_XPT_MEMDMA_MCPB_GPC13_CTRL 0x00a609a8 /* MCPB GPC13 Control information */
-#define BCHP_XPT_MEMDMA_MCPB_GPC13_CURR_COUNTER_VAL 0x00a609ac /* MCPB GPC13 Current counter value */
-#define BCHP_XPT_MEMDMA_MCPB_GPC13_PAUSE_0_31 0x00a609b0 /* MCPB GPC13 Current pause value */
-#define BCHP_XPT_MEMDMA_MCPB_GPC14_CTRL 0x00a609b4 /* MCPB GPC14 Control information */
-#define BCHP_XPT_MEMDMA_MCPB_GPC14_CURR_COUNTER_VAL 0x00a609b8 /* MCPB GPC14 Current counter value */
-#define BCHP_XPT_MEMDMA_MCPB_GPC14_PAUSE_0_31 0x00a609bc /* MCPB GPC14 Current pause value */
-#define BCHP_XPT_MEMDMA_MCPB_GPC15_CTRL 0x00a609c0 /* MCPB GPC15 Control information */
-#define BCHP_XPT_MEMDMA_MCPB_GPC15_CURR_COUNTER_VAL 0x00a609c4 /* MCPB GPC15 Current counter value */
-#define BCHP_XPT_MEMDMA_MCPB_GPC15_PAUSE_0_31 0x00a609c8 /* MCPB GPC15 Current pause value */
-#define BCHP_XPT_MEMDMA_MCPB_GPC16_CTRL 0x00a609cc /* MCPB GPC16 Control information */
-#define BCHP_XPT_MEMDMA_MCPB_GPC16_CURR_COUNTER_VAL 0x00a609d0 /* MCPB GPC16 Current counter value */
-#define BCHP_XPT_MEMDMA_MCPB_GPC16_PAUSE_0_31 0x00a609d4 /* MCPB GPC16 Current pause value */
-#define BCHP_XPT_MEMDMA_MCPB_GPC17_CTRL 0x00a609d8 /* MCPB GPC17 Control information */
-#define BCHP_XPT_MEMDMA_MCPB_GPC17_CURR_COUNTER_VAL 0x00a609dc /* MCPB GPC17 Current counter value */
-#define BCHP_XPT_MEMDMA_MCPB_GPC17_PAUSE_0_31 0x00a609e0 /* MCPB GPC17 Current pause value */
-#define BCHP_XPT_MEMDMA_MCPB_GPC18_CTRL 0x00a609e4 /* MCPB GPC18 Control information */
-#define BCHP_XPT_MEMDMA_MCPB_GPC18_CURR_COUNTER_VAL 0x00a609e8 /* MCPB GPC18 Current counter value */
-#define BCHP_XPT_MEMDMA_MCPB_GPC18_PAUSE_0_31 0x00a609ec /* MCPB GPC18 Current pause value */
-#define BCHP_XPT_MEMDMA_MCPB_GPC19_CTRL 0x00a609f0 /* MCPB GPC19 Control information */
-#define BCHP_XPT_MEMDMA_MCPB_GPC19_CURR_COUNTER_VAL 0x00a609f4 /* MCPB GPC19 Current counter value */
-#define BCHP_XPT_MEMDMA_MCPB_GPC19_PAUSE_0_31 0x00a609f8 /* MCPB GPC19 Current pause value */
-#define BCHP_XPT_MEMDMA_MCPB_GPC20_CTRL 0x00a609fc /* MCPB GPC20 Control information */
-#define BCHP_XPT_MEMDMA_MCPB_GPC20_CURR_COUNTER_VAL 0x00a60a00 /* MCPB GPC20 Current counter value */
-#define BCHP_XPT_MEMDMA_MCPB_GPC20_PAUSE_0_31 0x00a60a04 /* MCPB GPC20 Current pause value */
-#define BCHP_XPT_MEMDMA_MCPB_GPC21_CTRL 0x00a60a08 /* MCPB GPC21 Control information */
-#define BCHP_XPT_MEMDMA_MCPB_GPC21_CURR_COUNTER_VAL 0x00a60a0c /* MCPB GPC21 Current counter value */
-#define BCHP_XPT_MEMDMA_MCPB_GPC21_PAUSE_0_31 0x00a60a10 /* MCPB GPC21 Current pause value */
-#define BCHP_XPT_MEMDMA_MCPB_GPC22_CTRL 0x00a60a14 /* MCPB GPC22 Control information */
-#define BCHP_XPT_MEMDMA_MCPB_GPC22_CURR_COUNTER_VAL 0x00a60a18 /* MCPB GPC22 Current counter value */
-#define BCHP_XPT_MEMDMA_MCPB_GPC22_PAUSE_0_31 0x00a60a1c /* MCPB GPC22 Current pause value */
-#define BCHP_XPT_MEMDMA_MCPB_GPC23_CTRL 0x00a60a20 /* MCPB GPC23 Control information */
-#define BCHP_XPT_MEMDMA_MCPB_GPC23_CURR_COUNTER_VAL 0x00a60a24 /* MCPB GPC23 Current counter value */
-#define BCHP_XPT_MEMDMA_MCPB_GPC23_PAUSE_0_31 0x00a60a28 /* MCPB GPC23 Current pause value */
-#define BCHP_XPT_MEMDMA_MCPB_GPC24_CTRL 0x00a60a2c /* MCPB GPC24 Control information */
-#define BCHP_XPT_MEMDMA_MCPB_GPC24_CURR_COUNTER_VAL 0x00a60a30 /* MCPB GPC24 Current counter value */
-#define BCHP_XPT_MEMDMA_MCPB_GPC24_PAUSE_0_31 0x00a60a34 /* MCPB GPC24 Current pause value */
-#define BCHP_XPT_MEMDMA_MCPB_GPC25_CTRL 0x00a60a38 /* MCPB GPC25 Control information */
-#define BCHP_XPT_MEMDMA_MCPB_GPC25_CURR_COUNTER_VAL 0x00a60a3c /* MCPB GPC25 Current counter value */
-#define BCHP_XPT_MEMDMA_MCPB_GPC25_PAUSE_0_31 0x00a60a40 /* MCPB GPC25 Current pause value */
-#define BCHP_XPT_MEMDMA_MCPB_GPC26_CTRL 0x00a60a44 /* MCPB GPC26 Control information */
-#define BCHP_XPT_MEMDMA_MCPB_GPC26_CURR_COUNTER_VAL 0x00a60a48 /* MCPB GPC26 Current counter value */
-#define BCHP_XPT_MEMDMA_MCPB_GPC26_PAUSE_0_31 0x00a60a4c /* MCPB GPC26 Current pause value */
-#define BCHP_XPT_MEMDMA_MCPB_GPC27_CTRL 0x00a60a50 /* MCPB GPC27 Control information */
-#define BCHP_XPT_MEMDMA_MCPB_GPC27_CURR_COUNTER_VAL 0x00a60a54 /* MCPB GPC27 Current counter value */
-#define BCHP_XPT_MEMDMA_MCPB_GPC27_PAUSE_0_31 0x00a60a58 /* MCPB GPC27 Current pause value */
-#define BCHP_XPT_MEMDMA_MCPB_GPC28_CTRL 0x00a60a5c /* MCPB GPC28 Control information */
-#define BCHP_XPT_MEMDMA_MCPB_GPC28_CURR_COUNTER_VAL 0x00a60a60 /* MCPB GPC28 Current counter value */
-#define BCHP_XPT_MEMDMA_MCPB_GPC28_PAUSE_0_31 0x00a60a64 /* MCPB GPC28 Current pause value */
-#define BCHP_XPT_MEMDMA_MCPB_GPC29_CTRL 0x00a60a68 /* MCPB GPC29 Control information */
-#define BCHP_XPT_MEMDMA_MCPB_GPC29_CURR_COUNTER_VAL 0x00a60a6c /* MCPB GPC29 Current counter value */
-#define BCHP_XPT_MEMDMA_MCPB_GPC29_PAUSE_0_31 0x00a60a70 /* MCPB GPC29 Current pause value */
-#define BCHP_XPT_MEMDMA_MCPB_GPC30_CTRL 0x00a60a74 /* MCPB GPC30 Control information */
-#define BCHP_XPT_MEMDMA_MCPB_GPC30_CURR_COUNTER_VAL 0x00a60a78 /* MCPB GPC30 Current counter value */
-#define BCHP_XPT_MEMDMA_MCPB_GPC30_PAUSE_0_31 0x00a60a7c /* MCPB GPC30 Current pause value */
-#define BCHP_XPT_MEMDMA_MCPB_GPC31_CTRL 0x00a60a80 /* MCPB GPC31 Control information */
-#define BCHP_XPT_MEMDMA_MCPB_GPC31_CURR_COUNTER_VAL 0x00a60a84 /* MCPB GPC31 Current counter value */
-#define BCHP_XPT_MEMDMA_MCPB_GPC31_PAUSE_0_31 0x00a60a88 /* MCPB GPC31 Current pause value */
-#define BCHP_XPT_MEMDMA_MCPB_TMEU_ARB_DELAY 0x00a60a8c /* MCPB Arbitration delay value */
-#define BCHP_XPT_MEMDMA_MCPB_DMA_MEM_ADDR_START 0x00a60a90 /* Address start for CFG DMA SP memory */
-#define BCHP_XPT_MEMDMA_MCPB_BBUFF_MEM_ADDR_START 0x00a60a94 /* Address start for CFG BBUFF memory */
-#define BCHP_XPT_MEMDMA_MCPB_TMEU_MEM_ADDR_START 0x00a60a98 /* Address start for TMEU memory */
-#define BCHP_XPT_MEMDMA_MCPB_DCPM_MEM_ADDR_START 0x00a60a9c /* Address start for DCPM memory */
-#define BCHP_XPT_MEMDMA_MCPB_PER_CH_MEM_ADDR_END 0x00a60aa0 /* Address end in configuration memory for each channel */
-#define BCHP_XPT_MEMDMA_MCPB_GLOBAL_CTRL_SIGNALS 0x00a60aa4 /* Global control signals */
-#define BCHP_XPT_MEMDMA_MCPB_MASK_CLEAR_PAUSE_AT_DESC_END_FROM_MEMDMA_SET_CLEAR 0x00a60aa8 /* Set and clear of Pause at descriptor end clear mask status bit */
-#define BCHP_XPT_MEMDMA_MCPB_MASK_CLEAR_PAUSE_AT_DESC_END_FROM_MEMDMA_STATUS_0_31 0x00a60aac /* Pause at descriptor end clear mask status bit for all PB channels */
-#define BCHP_XPT_MEMDMA_MCPB_MASK_CLEAR_PAUSE_AT_DESC_END_FROM_HOST_SET_CLEAR 0x00a60ab0 /* Set and clear of Pause at descriptor end clear mask status bit */
-#define BCHP_XPT_MEMDMA_MCPB_MASK_CLEAR_PAUSE_AT_DESC_END_FROM_HOST_STATUS_0_31 0x00a60ab4 /* Pause at descriptor end clear mask status bit for all PB channels */
-#define BCHP_XPT_MEMDMA_MCPB_DESCRIPTOR_LESS_MODE_SET_CLEAR 0x00a60ab8 /* Set and clear for DESCRIPTOR_LESS_MODE_STATUS bit */
-#define BCHP_XPT_MEMDMA_MCPB_DESCRIPTOR_LESS_MODE_STATUS_0_31 0x00a60abc /* Descriptorless status for all PB channels */
-#define BCHP_XPT_MEMDMA_MCPB_ARBITER_ZERO_BYTE_TRANS_PRIORITY_SET_CLEAR 0x00a60ac0 /* Set and clear for Zero Byte Transaction Priority bit */
-#define BCHP_XPT_MEMDMA_MCPB_ARBITER_ZERO_BYTE_TRANS_PRIORITY_STATUS_0_31 0x00a60ac4 /* Zero Byte Transaction Priority status for all PB channels */
-#define BCHP_XPT_MEMDMA_MCPB_ARBITER_SEND_DCP_ONLY_TRANS_AS_HIGH_PRIORITY_SET_CLEAR 0x00a60ac8 /* Set and clear for DCP-only-transaction priority bit */
-#define BCHP_XPT_MEMDMA_MCPB_ARBITER_SEND_DCP_ONLY_TRANS_AS_HIGH_PRIORITY_STATUS_0_31 0x00a60acc /* DCP-only-transaction priority status for all PB channels */
-#define BCHP_XPT_MEMDMA_MCPB_SEC_OUTPUT_PIPE_PACKET_GAPPER 0x00a60ad4 /* Packet gapper controls for SECURITY O/P pipe */
-#define BCHP_XPT_MEMDMA_MCPB_MANUAL_MODE_SEL_0 0x00a60ae4 /* Manual mode select signals Selection 0 */
-#define BCHP_XPT_MEMDMA_MCPB_MANUAL_MODE_SEL_1 0x00a60ae8 /* Manual mode select signals Selection 1 */
-#define BCHP_XPT_MEMDMA_MCPB_MANUAL_MODE_SEL_2 0x00a60aec /* Manual mode select signals Selection 2 */
-#define BCHP_XPT_MEMDMA_MCPB_MANUAL_MODE_SEL_3 0x00a60af0 /* Manual mode select signals Selection 3 */
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_0 0x00a60af4 /* Debug Register */
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_1 0x00a60af8 /* Debug Register */
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_2 0x00a60afc /* Debug Register */
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_3 0x00a60b00 /* Debug Register */
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_4 0x00a60b04 /* Debug Register */
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_5 0x00a60b08 /* Debug Register */
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_6 0x00a60b0c /* Debug Register */
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_7 0x00a60b10 /* Debug Register */
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_8 0x00a60b14 /* Debug Register */
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_9 0x00a60b18 /* Debug Register */
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_10 0x00a60b1c /* Debug Register */
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_11 0x00a60b20 /* Debug Register */
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_12 0x00a60b24 /* Debug Register */
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_13 0x00a60b28 /* Debug Register */
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_14 0x00a60b2c /* Debug Register */
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_15 0x00a60b30 /* Debug Register */
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_16 0x00a60b34 /* Debug Register */
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_17 0x00a60b38 /* Debug Register */
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_18 0x00a60b3c /* Debug Register */
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_19 0x00a60b40 /* Debug Register */
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_20 0x00a60b44 /* Debug Register */
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_21 0x00a60b48 /* Debug Register */
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_22 0x00a60b4c /* Debug Register */
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_23 0x00a60b50 /* Debug Register */
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_24 0x00a60b54 /* Debug Register */
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_25 0x00a60b58 /* Debug Register */
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_26 0x00a60b5c /* Debug Register */
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_27 0x00a60b60 /* Debug Register */
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_28 0x00a60b64 /* Debug Register */
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_29 0x00a60b68 /* Debug Register */
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_30 0x00a60b6c /* Debug Register */
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_31 0x00a60b70 /* Debug Register */
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_32 0x00a60b74 /* Debug Register */
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_33 0x00a60b78 /* Debug Register */
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_34 0x00a60b7c /* Debug Register */
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_35 0x00a60b80 /* Debug Register */
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_36 0x00a60b84 /* Debug Register */
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_37 0x00a60b88 /* Debug Register */
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_38 0x00a60b8c /* Debug Register */
-#define BCHP_XPT_MEMDMA_MCPB_SP_TIME_OUT_THRESHOLD 0x00a60b90 /* SP Timeout Threshold */
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_SP_FORCE_RECOVER 0x00a60b94 /* Debug SP Force Recover */
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_SP_TX_SLOT_CMD_AUTO_RECOVER_OVERWR 0x00a60b98 /* Debug SP TX Overwrite Slot Cmd Auto Recover Overwrite */
-
-/***************************************************************************
- *RUN_SET_CLEAR - Set and Clear for the RUN bit
- ***************************************************************************/
-/* XPT_MEMDMA_MCPB :: RUN_SET_CLEAR :: reserved0 [31:09] */
-#define BCHP_XPT_MEMDMA_MCPB_RUN_SET_CLEAR_reserved0_MASK 0xfffffe00
-#define BCHP_XPT_MEMDMA_MCPB_RUN_SET_CLEAR_reserved0_SHIFT 9
-
-/* XPT_MEMDMA_MCPB :: RUN_SET_CLEAR :: SET_CLEAR [08:08] */
-#define BCHP_XPT_MEMDMA_MCPB_RUN_SET_CLEAR_SET_CLEAR_MASK 0x00000100
-#define BCHP_XPT_MEMDMA_MCPB_RUN_SET_CLEAR_SET_CLEAR_SHIFT 8
-#define BCHP_XPT_MEMDMA_MCPB_RUN_SET_CLEAR_SET_CLEAR_DEFAULT 0x00000000
-
-/* XPT_MEMDMA_MCPB :: RUN_SET_CLEAR :: MCPB_CHANNEL_NUM [07:00] */
-#define BCHP_XPT_MEMDMA_MCPB_RUN_SET_CLEAR_MCPB_CHANNEL_NUM_MASK 0x000000ff
-#define BCHP_XPT_MEMDMA_MCPB_RUN_SET_CLEAR_MCPB_CHANNEL_NUM_SHIFT 0
-#define BCHP_XPT_MEMDMA_MCPB_RUN_SET_CLEAR_MCPB_CHANNEL_NUM_DEFAULT 0x00000000
-
-/***************************************************************************
- *WAKE_SET - Set for the WAKE bit
- ***************************************************************************/
-/* XPT_MEMDMA_MCPB :: WAKE_SET :: reserved0 [31:09] */
-#define BCHP_XPT_MEMDMA_MCPB_WAKE_SET_reserved0_MASK 0xfffffe00
-#define BCHP_XPT_MEMDMA_MCPB_WAKE_SET_reserved0_SHIFT 9
-
-/* XPT_MEMDMA_MCPB :: WAKE_SET :: SET [08:08] */
-#define BCHP_XPT_MEMDMA_MCPB_WAKE_SET_SET_MASK 0x00000100
-#define BCHP_XPT_MEMDMA_MCPB_WAKE_SET_SET_SHIFT 8
-#define BCHP_XPT_MEMDMA_MCPB_WAKE_SET_SET_DEFAULT 0x00000000
-
-/* XPT_MEMDMA_MCPB :: WAKE_SET :: MCPB_CHANNEL_NUM [07:00] */
-#define BCHP_XPT_MEMDMA_MCPB_WAKE_SET_MCPB_CHANNEL_NUM_MASK 0x000000ff
-#define BCHP_XPT_MEMDMA_MCPB_WAKE_SET_MCPB_CHANNEL_NUM_SHIFT 0
-#define BCHP_XPT_MEMDMA_MCPB_WAKE_SET_MCPB_CHANNEL_NUM_DEFAULT 0x00000000
-
-/***************************************************************************
- *WAKE_MODE_SET_CLEAR - Set and Clear for the WAKE_MODE bit
- ***************************************************************************/
-/* XPT_MEMDMA_MCPB :: WAKE_MODE_SET_CLEAR :: reserved0 [31:09] */
-#define BCHP_XPT_MEMDMA_MCPB_WAKE_MODE_SET_CLEAR_reserved0_MASK 0xfffffe00
-#define BCHP_XPT_MEMDMA_MCPB_WAKE_MODE_SET_CLEAR_reserved0_SHIFT 9
-
-/* XPT_MEMDMA_MCPB :: WAKE_MODE_SET_CLEAR :: SET_CLEAR [08:08] */
-#define BCHP_XPT_MEMDMA_MCPB_WAKE_MODE_SET_CLEAR_SET_CLEAR_MASK 0x00000100
-#define BCHP_XPT_MEMDMA_MCPB_WAKE_MODE_SET_CLEAR_SET_CLEAR_SHIFT 8
-#define BCHP_XPT_MEMDMA_MCPB_WAKE_MODE_SET_CLEAR_SET_CLEAR_DEFAULT 0x00000000
-
-/* XPT_MEMDMA_MCPB :: WAKE_MODE_SET_CLEAR :: MCPB_CHANNEL_NUM [07:00] */
-#define BCHP_XPT_MEMDMA_MCPB_WAKE_MODE_SET_CLEAR_MCPB_CHANNEL_NUM_MASK 0x000000ff
-#define BCHP_XPT_MEMDMA_MCPB_WAKE_MODE_SET_CLEAR_MCPB_CHANNEL_NUM_SHIFT 0
-#define BCHP_XPT_MEMDMA_MCPB_WAKE_MODE_SET_CLEAR_MCPB_CHANNEL_NUM_DEFAULT 0x00000000
-
-/***************************************************************************
- *BUFF_DATA_RDY_SET - Set for the BUFF_DATA_RDY bit
- ***************************************************************************/
-/* XPT_MEMDMA_MCPB :: BUFF_DATA_RDY_SET :: reserved0 [31:09] */
-#define BCHP_XPT_MEMDMA_MCPB_BUFF_DATA_RDY_SET_reserved0_MASK 0xfffffe00
-#define BCHP_XPT_MEMDMA_MCPB_BUFF_DATA_RDY_SET_reserved0_SHIFT 9
-
-/* XPT_MEMDMA_MCPB :: BUFF_DATA_RDY_SET :: SET [08:08] */
-#define BCHP_XPT_MEMDMA_MCPB_BUFF_DATA_RDY_SET_SET_MASK 0x00000100
-#define BCHP_XPT_MEMDMA_MCPB_BUFF_DATA_RDY_SET_SET_SHIFT 8
-#define BCHP_XPT_MEMDMA_MCPB_BUFF_DATA_RDY_SET_SET_DEFAULT 0x00000000
-
-/* XPT_MEMDMA_MCPB :: BUFF_DATA_RDY_SET :: MCPB_CHANNEL_NUM [07:00] */
-#define BCHP_XPT_MEMDMA_MCPB_BUFF_DATA_RDY_SET_MCPB_CHANNEL_NUM_MASK 0x000000ff
-#define BCHP_XPT_MEMDMA_MCPB_BUFF_DATA_RDY_SET_MCPB_CHANNEL_NUM_SHIFT 0
-#define BCHP_XPT_MEMDMA_MCPB_BUFF_DATA_RDY_SET_MCPB_CHANNEL_NUM_DEFAULT 0x00000000
-
-/***************************************************************************
- *PAUSE_AT_DESC_READ_CLEAR - Clear for the PAUSE_AT_DESC_READ bit
- ***************************************************************************/
-/* XPT_MEMDMA_MCPB :: PAUSE_AT_DESC_READ_CLEAR :: reserved0 [31:09] */
-#define BCHP_XPT_MEMDMA_MCPB_PAUSE_AT_DESC_READ_CLEAR_reserved0_MASK 0xfffffe00
-#define BCHP_XPT_MEMDMA_MCPB_PAUSE_AT_DESC_READ_CLEAR_reserved0_SHIFT 9
-
-/* XPT_MEMDMA_MCPB :: PAUSE_AT_DESC_READ_CLEAR :: CLEAR [08:08] */
-#define BCHP_XPT_MEMDMA_MCPB_PAUSE_AT_DESC_READ_CLEAR_CLEAR_MASK 0x00000100
-#define BCHP_XPT_MEMDMA_MCPB_PAUSE_AT_DESC_READ_CLEAR_CLEAR_SHIFT 8
-#define BCHP_XPT_MEMDMA_MCPB_PAUSE_AT_DESC_READ_CLEAR_CLEAR_DEFAULT 0x00000000
-
-/* XPT_MEMDMA_MCPB :: PAUSE_AT_DESC_READ_CLEAR :: MCPB_CHANNEL_NUM [07:00] */
-#define BCHP_XPT_MEMDMA_MCPB_PAUSE_AT_DESC_READ_CLEAR_MCPB_CHANNEL_NUM_MASK 0x000000ff
-#define BCHP_XPT_MEMDMA_MCPB_PAUSE_AT_DESC_READ_CLEAR_MCPB_CHANNEL_NUM_SHIFT 0
-#define BCHP_XPT_MEMDMA_MCPB_PAUSE_AT_DESC_READ_CLEAR_MCPB_CHANNEL_NUM_DEFAULT 0x00000000
-
-/***************************************************************************
- *PAUSE_AT_DESC_END_CLEAR - Clear for the PAUSE_AT_DESC_END bit
- ***************************************************************************/
-/* XPT_MEMDMA_MCPB :: PAUSE_AT_DESC_END_CLEAR :: reserved0 [31:09] */
-#define BCHP_XPT_MEMDMA_MCPB_PAUSE_AT_DESC_END_CLEAR_reserved0_MASK 0xfffffe00
-#define BCHP_XPT_MEMDMA_MCPB_PAUSE_AT_DESC_END_CLEAR_reserved0_SHIFT 9
-
-/* XPT_MEMDMA_MCPB :: PAUSE_AT_DESC_END_CLEAR :: CLEAR [08:08] */
-#define BCHP_XPT_MEMDMA_MCPB_PAUSE_AT_DESC_END_CLEAR_CLEAR_MASK 0x00000100
-#define BCHP_XPT_MEMDMA_MCPB_PAUSE_AT_DESC_END_CLEAR_CLEAR_SHIFT 8
-#define BCHP_XPT_MEMDMA_MCPB_PAUSE_AT_DESC_END_CLEAR_CLEAR_DEFAULT 0x00000000
-
-/* XPT_MEMDMA_MCPB :: PAUSE_AT_DESC_END_CLEAR :: MCPB_CHANNEL_NUM [07:00] */
-#define BCHP_XPT_MEMDMA_MCPB_PAUSE_AT_DESC_END_CLEAR_MCPB_CHANNEL_NUM_MASK 0x000000ff
-#define BCHP_XPT_MEMDMA_MCPB_PAUSE_AT_DESC_END_CLEAR_MCPB_CHANNEL_NUM_SHIFT 0
-#define BCHP_XPT_MEMDMA_MCPB_PAUSE_AT_DESC_END_CLEAR_MCPB_CHANNEL_NUM_DEFAULT 0x00000000
-
-/***************************************************************************
- *PAUSE_AFTER_GROUP_PACKETS_CLEAR - Clear for the PAUSE_AFTER_GROUP_PACKETS bit
- ***************************************************************************/
-/* XPT_MEMDMA_MCPB :: PAUSE_AFTER_GROUP_PACKETS_CLEAR :: reserved0 [31:09] */
-#define BCHP_XPT_MEMDMA_MCPB_PAUSE_AFTER_GROUP_PACKETS_CLEAR_reserved0_MASK 0xfffffe00
-#define BCHP_XPT_MEMDMA_MCPB_PAUSE_AFTER_GROUP_PACKETS_CLEAR_reserved0_SHIFT 9
-
-/* XPT_MEMDMA_MCPB :: PAUSE_AFTER_GROUP_PACKETS_CLEAR :: CLEAR [08:08] */
-#define BCHP_XPT_MEMDMA_MCPB_PAUSE_AFTER_GROUP_PACKETS_CLEAR_CLEAR_MASK 0x00000100
-#define BCHP_XPT_MEMDMA_MCPB_PAUSE_AFTER_GROUP_PACKETS_CLEAR_CLEAR_SHIFT 8
-#define BCHP_XPT_MEMDMA_MCPB_PAUSE_AFTER_GROUP_PACKETS_CLEAR_CLEAR_DEFAULT 0x00000000
-
-/* XPT_MEMDMA_MCPB :: PAUSE_AFTER_GROUP_PACKETS_CLEAR :: MCPB_CHANNEL_NUM [07:00] */
-#define BCHP_XPT_MEMDMA_MCPB_PAUSE_AFTER_GROUP_PACKETS_CLEAR_MCPB_CHANNEL_NUM_MASK 0x000000ff
-#define BCHP_XPT_MEMDMA_MCPB_PAUSE_AFTER_GROUP_PACKETS_CLEAR_MCPB_CHANNEL_NUM_SHIFT 0
-#define BCHP_XPT_MEMDMA_MCPB_PAUSE_AFTER_GROUP_PACKETS_CLEAR_MCPB_CHANNEL_NUM_DEFAULT 0x00000000
-
-/***************************************************************************
- *CRC_COMPARE_ERROR_PAUSE_CLEAR - Clear for the CRC_COMPARE_ERROR_PAUSE bit
- ***************************************************************************/
-/* XPT_MEMDMA_MCPB :: CRC_COMPARE_ERROR_PAUSE_CLEAR :: reserved0 [31:09] */
-#define BCHP_XPT_MEMDMA_MCPB_CRC_COMPARE_ERROR_PAUSE_CLEAR_reserved0_MASK 0xfffffe00
-#define BCHP_XPT_MEMDMA_MCPB_CRC_COMPARE_ERROR_PAUSE_CLEAR_reserved0_SHIFT 9
-
-/* XPT_MEMDMA_MCPB :: CRC_COMPARE_ERROR_PAUSE_CLEAR :: CLEAR [08:08] */
-#define BCHP_XPT_MEMDMA_MCPB_CRC_COMPARE_ERROR_PAUSE_CLEAR_CLEAR_MASK 0x00000100
-#define BCHP_XPT_MEMDMA_MCPB_CRC_COMPARE_ERROR_PAUSE_CLEAR_CLEAR_SHIFT 8
-#define BCHP_XPT_MEMDMA_MCPB_CRC_COMPARE_ERROR_PAUSE_CLEAR_CLEAR_DEFAULT 0x00000000
-
-/* XPT_MEMDMA_MCPB :: CRC_COMPARE_ERROR_PAUSE_CLEAR :: MCPB_CHANNEL_NUM [07:00] */
-#define BCHP_XPT_MEMDMA_MCPB_CRC_COMPARE_ERROR_PAUSE_CLEAR_MCPB_CHANNEL_NUM_MASK 0x000000ff
-#define BCHP_XPT_MEMDMA_MCPB_CRC_COMPARE_ERROR_PAUSE_CLEAR_MCPB_CHANNEL_NUM_SHIFT 0
-#define BCHP_XPT_MEMDMA_MCPB_CRC_COMPARE_ERROR_PAUSE_CLEAR_MCPB_CHANNEL_NUM_DEFAULT 0x00000000
-
-/***************************************************************************
- *MICRO_PAUSE_SET_CLEAR - Set and Clear for the MICRO_PAUSE bit
- ***************************************************************************/
-/* XPT_MEMDMA_MCPB :: MICRO_PAUSE_SET_CLEAR :: reserved0 [31:09] */
-#define BCHP_XPT_MEMDMA_MCPB_MICRO_PAUSE_SET_CLEAR_reserved0_MASK 0xfffffe00
-#define BCHP_XPT_MEMDMA_MCPB_MICRO_PAUSE_SET_CLEAR_reserved0_SHIFT 9
-
-/* XPT_MEMDMA_MCPB :: MICRO_PAUSE_SET_CLEAR :: SET_CLEAR [08:08] */
-#define BCHP_XPT_MEMDMA_MCPB_MICRO_PAUSE_SET_CLEAR_SET_CLEAR_MASK 0x00000100
-#define BCHP_XPT_MEMDMA_MCPB_MICRO_PAUSE_SET_CLEAR_SET_CLEAR_SHIFT 8
-#define BCHP_XPT_MEMDMA_MCPB_MICRO_PAUSE_SET_CLEAR_SET_CLEAR_DEFAULT 0x00000000
-
-/* XPT_MEMDMA_MCPB :: MICRO_PAUSE_SET_CLEAR :: MCPB_CHANNEL_NUM [07:00] */
-#define BCHP_XPT_MEMDMA_MCPB_MICRO_PAUSE_SET_CLEAR_MCPB_CHANNEL_NUM_MASK 0x000000ff
-#define BCHP_XPT_MEMDMA_MCPB_MICRO_PAUSE_SET_CLEAR_MCPB_CHANNEL_NUM_SHIFT 0
-#define BCHP_XPT_MEMDMA_MCPB_MICRO_PAUSE_SET_CLEAR_MCPB_CHANNEL_NUM_DEFAULT 0x00000000
-
-/***************************************************************************
- *RUN_STATUS_0_31 - Run status for all the PB channels
- ***************************************************************************/
-/* XPT_MEMDMA_MCPB :: RUN_STATUS_0_31 :: RUN_STATUS [31:00] */
-#define BCHP_XPT_MEMDMA_MCPB_RUN_STATUS_0_31_RUN_STATUS_MASK 0xffffffff
-#define BCHP_XPT_MEMDMA_MCPB_RUN_STATUS_0_31_RUN_STATUS_SHIFT 0
-#define BCHP_XPT_MEMDMA_MCPB_RUN_STATUS_0_31_RUN_STATUS_DEFAULT 0x00000000
-
-/***************************************************************************
- *WAKE_STATUS_0_31 - Wake status for all the PB channels
- ***************************************************************************/
-/* XPT_MEMDMA_MCPB :: WAKE_STATUS_0_31 :: WAKE_STATUS [31:00] */
-#define BCHP_XPT_MEMDMA_MCPB_WAKE_STATUS_0_31_WAKE_STATUS_MASK 0xffffffff
-#define BCHP_XPT_MEMDMA_MCPB_WAKE_STATUS_0_31_WAKE_STATUS_SHIFT 0
-#define BCHP_XPT_MEMDMA_MCPB_WAKE_STATUS_0_31_WAKE_STATUS_DEFAULT 0x00000000
-
-/***************************************************************************
- *WAKE_MODE_STATUS_0_31 - Wake Mode status for all the PB channels
- ***************************************************************************/
-/* XPT_MEMDMA_MCPB :: WAKE_MODE_STATUS_0_31 :: WAKE_MODE_STATUS [31:00] */
-#define BCHP_XPT_MEMDMA_MCPB_WAKE_MODE_STATUS_0_31_WAKE_MODE_STATUS_MASK 0xffffffff
-#define BCHP_XPT_MEMDMA_MCPB_WAKE_MODE_STATUS_0_31_WAKE_MODE_STATUS_SHIFT 0
-#define BCHP_XPT_MEMDMA_MCPB_WAKE_MODE_STATUS_0_31_WAKE_MODE_STATUS_DEFAULT 0x00000000
-
-/***************************************************************************
- *PAUSE_AT_DESC_READ_STATUS_0_31 - Pause at descriptor read status for all the PB channels
- ***************************************************************************/
-/* XPT_MEMDMA_MCPB :: PAUSE_AT_DESC_READ_STATUS_0_31 :: PAUSE_AT_DESC_READ_STATUS [31:00] */
-#define BCHP_XPT_MEMDMA_MCPB_PAUSE_AT_DESC_READ_STATUS_0_31_PAUSE_AT_DESC_READ_STATUS_MASK 0xffffffff
-#define BCHP_XPT_MEMDMA_MCPB_PAUSE_AT_DESC_READ_STATUS_0_31_PAUSE_AT_DESC_READ_STATUS_SHIFT 0
-#define BCHP_XPT_MEMDMA_MCPB_PAUSE_AT_DESC_READ_STATUS_0_31_PAUSE_AT_DESC_READ_STATUS_DEFAULT 0x00000000
-
-/***************************************************************************
- *PAUSE_AT_DESC_END_STATUS_0_31 - Pause at descriptor end status for all the PB channels
- ***************************************************************************/
-/* XPT_MEMDMA_MCPB :: PAUSE_AT_DESC_END_STATUS_0_31 :: PAUSE_AT_DESC_END_STATUS [31:00] */
-#define BCHP_XPT_MEMDMA_MCPB_PAUSE_AT_DESC_END_STATUS_0_31_PAUSE_AT_DESC_END_STATUS_MASK 0xffffffff
-#define BCHP_XPT_MEMDMA_MCPB_PAUSE_AT_DESC_END_STATUS_0_31_PAUSE_AT_DESC_END_STATUS_SHIFT 0
-#define BCHP_XPT_MEMDMA_MCPB_PAUSE_AT_DESC_END_STATUS_0_31_PAUSE_AT_DESC_END_STATUS_DEFAULT 0x00000000
-
-/***************************************************************************
- *PAUSE_AFTER_GROUP_PACKETS_STATUS_0_31 - Pause after group of packets status for all the PB channels
- ***************************************************************************/
-/* XPT_MEMDMA_MCPB :: PAUSE_AFTER_GROUP_PACKETS_STATUS_0_31 :: PAUSE_AFTER_GROUP_PACKETS_STATUS [31:00] */
-#define BCHP_XPT_MEMDMA_MCPB_PAUSE_AFTER_GROUP_PACKETS_STATUS_0_31_PAUSE_AFTER_GROUP_PACKETS_STATUS_MASK 0xffffffff
-#define BCHP_XPT_MEMDMA_MCPB_PAUSE_AFTER_GROUP_PACKETS_STATUS_0_31_PAUSE_AFTER_GROUP_PACKETS_STATUS_SHIFT 0
-#define BCHP_XPT_MEMDMA_MCPB_PAUSE_AFTER_GROUP_PACKETS_STATUS_0_31_PAUSE_AFTER_GROUP_PACKETS_STATUS_DEFAULT 0x00000000
-
-/***************************************************************************
- *CRC_COMPARE_ERROR_PAUSE_STATUS_0_31 - CRC compare error pause status for all the PB channels
- ***************************************************************************/
-/* XPT_MEMDMA_MCPB :: CRC_COMPARE_ERROR_PAUSE_STATUS_0_31 :: CRC_COMPARE_ERROR_PAUSE_STATUS [31:00] */
-#define BCHP_XPT_MEMDMA_MCPB_CRC_COMPARE_ERROR_PAUSE_STATUS_0_31_CRC_COMPARE_ERROR_PAUSE_STATUS_MASK 0xffffffff
-#define BCHP_XPT_MEMDMA_MCPB_CRC_COMPARE_ERROR_PAUSE_STATUS_0_31_CRC_COMPARE_ERROR_PAUSE_STATUS_SHIFT 0
-#define BCHP_XPT_MEMDMA_MCPB_CRC_COMPARE_ERROR_PAUSE_STATUS_0_31_CRC_COMPARE_ERROR_PAUSE_STATUS_DEFAULT 0x00000000
-
-/***************************************************************************
- *MICRO_PAUSE_STATUS_0_31 - Micro Pause status for all the PB channels
- ***************************************************************************/
-/* XPT_MEMDMA_MCPB :: MICRO_PAUSE_STATUS_0_31 :: MICRO_PAUSE_STATUS [31:00] */
-#define BCHP_XPT_MEMDMA_MCPB_MICRO_PAUSE_STATUS_0_31_MICRO_PAUSE_STATUS_MASK 0xffffffff
-#define BCHP_XPT_MEMDMA_MCPB_MICRO_PAUSE_STATUS_0_31_MICRO_PAUSE_STATUS_SHIFT 0
-#define BCHP_XPT_MEMDMA_MCPB_MICRO_PAUSE_STATUS_0_31_MICRO_PAUSE_STATUS_DEFAULT 0x00000000
-
-/***************************************************************************
- *FINAL_PAUSE_STATUS_0_31 - Final Pause status for all the PB channels
- ***************************************************************************/
-/* XPT_MEMDMA_MCPB :: FINAL_PAUSE_STATUS_0_31 :: FINAL_PAUSE_STATUS [31:00] */
-#define BCHP_XPT_MEMDMA_MCPB_FINAL_PAUSE_STATUS_0_31_FINAL_PAUSE_STATUS_MASK 0xffffffff
-#define BCHP_XPT_MEMDMA_MCPB_FINAL_PAUSE_STATUS_0_31_FINAL_PAUSE_STATUS_SHIFT 0
-#define BCHP_XPT_MEMDMA_MCPB_FINAL_PAUSE_STATUS_0_31_FINAL_PAUSE_STATUS_DEFAULT 0x00000000
-
-/***************************************************************************
- *HW_PAUSE_STATUS_0_31 - Hardware Pause status for all the PB channels
- ***************************************************************************/
-/* XPT_MEMDMA_MCPB :: HW_PAUSE_STATUS_0_31 :: HW_PAUSE_STATUS [31:00] */
-#define BCHP_XPT_MEMDMA_MCPB_HW_PAUSE_STATUS_0_31_HW_PAUSE_STATUS_MASK 0xffffffff
-#define BCHP_XPT_MEMDMA_MCPB_HW_PAUSE_STATUS_0_31_HW_PAUSE_STATUS_SHIFT 0
-#define BCHP_XPT_MEMDMA_MCPB_HW_PAUSE_STATUS_0_31_HW_PAUSE_STATUS_DEFAULT 0x00000000
-
-/***************************************************************************
- *DESC_RD_IN_PROGRESS_0_31 - Descriptor Read in Progress status flag
- ***************************************************************************/
-/* XPT_MEMDMA_MCPB :: DESC_RD_IN_PROGRESS_0_31 :: DESC_RD_IN_PROGRESS [31:00] */
-#define BCHP_XPT_MEMDMA_MCPB_DESC_RD_IN_PROGRESS_0_31_DESC_RD_IN_PROGRESS_MASK 0xffffffff
-#define BCHP_XPT_MEMDMA_MCPB_DESC_RD_IN_PROGRESS_0_31_DESC_RD_IN_PROGRESS_SHIFT 0
-#define BCHP_XPT_MEMDMA_MCPB_DESC_RD_IN_PROGRESS_0_31_DESC_RD_IN_PROGRESS_DEFAULT 0x00000000
-
-/***************************************************************************
- *DATA_RD_IN_PROGRESS_0_31 - Data Read in Progress status flag
- ***************************************************************************/
-/* XPT_MEMDMA_MCPB :: DATA_RD_IN_PROGRESS_0_31 :: DATA_RD_IN_PROGRESS [31:00] */
-#define BCHP_XPT_MEMDMA_MCPB_DATA_RD_IN_PROGRESS_0_31_DATA_RD_IN_PROGRESS_MASK 0xffffffff
-#define BCHP_XPT_MEMDMA_MCPB_DATA_RD_IN_PROGRESS_0_31_DATA_RD_IN_PROGRESS_SHIFT 0
-#define BCHP_XPT_MEMDMA_MCPB_DATA_RD_IN_PROGRESS_0_31_DATA_RD_IN_PROGRESS_DEFAULT 0x00000000
-
-/***************************************************************************
- *BBUFF_RD_IN_PROGRESS_0_31 - Burst Buffer Read in Progress status flag
- ***************************************************************************/
-/* XPT_MEMDMA_MCPB :: BBUFF_RD_IN_PROGRESS_0_31 :: BBUFF_RD_IN_PROGRESS [31:00] */
-#define BCHP_XPT_MEMDMA_MCPB_BBUFF_RD_IN_PROGRESS_0_31_BBUFF_RD_IN_PROGRESS_MASK 0xffffffff
-#define BCHP_XPT_MEMDMA_MCPB_BBUFF_RD_IN_PROGRESS_0_31_BBUFF_RD_IN_PROGRESS_SHIFT 0
-#define BCHP_XPT_MEMDMA_MCPB_BBUFF_RD_IN_PROGRESS_0_31_BBUFF_RD_IN_PROGRESS_DEFAULT 0x00000000
-
-/***************************************************************************
- *LAST_DESC_REACHED_0_31 - Last Descriptor Reached status flag
- ***************************************************************************/
-/* XPT_MEMDMA_MCPB :: LAST_DESC_REACHED_0_31 :: LAST_DESC_REACHED [31:00] */
-#define BCHP_XPT_MEMDMA_MCPB_LAST_DESC_REACHED_0_31_LAST_DESC_REACHED_MASK 0xffffffff
-#define BCHP_XPT_MEMDMA_MCPB_LAST_DESC_REACHED_0_31_LAST_DESC_REACHED_SHIFT 0
-#define BCHP_XPT_MEMDMA_MCPB_LAST_DESC_REACHED_0_31_LAST_DESC_REACHED_DEFAULT 0x00000000
-
-/***************************************************************************
- *BUFF_DATA_RDY_0_31 - Buffer data ready status flag
- ***************************************************************************/
-/* XPT_MEMDMA_MCPB :: BUFF_DATA_RDY_0_31 :: BUFF_DATA_RDY [31:00] */
-#define BCHP_XPT_MEMDMA_MCPB_BUFF_DATA_RDY_0_31_BUFF_DATA_RDY_MASK 0xffffffff
-#define BCHP_XPT_MEMDMA_MCPB_BUFF_DATA_RDY_0_31_BUFF_DATA_RDY_SHIFT 0
-#define BCHP_XPT_MEMDMA_MCPB_BUFF_DATA_RDY_0_31_BUFF_DATA_RDY_DEFAULT 0x00000000
-
-/***************************************************************************
- *FIRST_DATA_RD_OPN_PRIORITY_0_31 - First data read operation priority flag
- ***************************************************************************/
-/* XPT_MEMDMA_MCPB :: FIRST_DATA_RD_OPN_PRIORITY_0_31 :: FIRST_DATA_RD_OPN_PRIORITY [31:00] */
-#define BCHP_XPT_MEMDMA_MCPB_FIRST_DATA_RD_OPN_PRIORITY_0_31_FIRST_DATA_RD_OPN_PRIORITY_MASK 0xffffffff
-#define BCHP_XPT_MEMDMA_MCPB_FIRST_DATA_RD_OPN_PRIORITY_0_31_FIRST_DATA_RD_OPN_PRIORITY_SHIFT 0
-#define BCHP_XPT_MEMDMA_MCPB_FIRST_DATA_RD_OPN_PRIORITY_0_31_FIRST_DATA_RD_OPN_PRIORITY_DEFAULT 0x00000000
-
-/***************************************************************************
- *RUN_INVALID_SET_CLEAR - Set and Clear Run Invalid
- ***************************************************************************/
-/* XPT_MEMDMA_MCPB :: RUN_INVALID_SET_CLEAR :: reserved0 [31:09] */
-#define BCHP_XPT_MEMDMA_MCPB_RUN_INVALID_SET_CLEAR_reserved0_MASK 0xfffffe00
-#define BCHP_XPT_MEMDMA_MCPB_RUN_INVALID_SET_CLEAR_reserved0_SHIFT 9
-
-/* XPT_MEMDMA_MCPB :: RUN_INVALID_SET_CLEAR :: SET_CLEAR [08:08] */
-#define BCHP_XPT_MEMDMA_MCPB_RUN_INVALID_SET_CLEAR_SET_CLEAR_MASK 0x00000100
-#define BCHP_XPT_MEMDMA_MCPB_RUN_INVALID_SET_CLEAR_SET_CLEAR_SHIFT 8
-#define BCHP_XPT_MEMDMA_MCPB_RUN_INVALID_SET_CLEAR_SET_CLEAR_DEFAULT 0x00000000
-
-/* XPT_MEMDMA_MCPB :: RUN_INVALID_SET_CLEAR :: MCPB_CHANNEL_NUM [07:00] */
-#define BCHP_XPT_MEMDMA_MCPB_RUN_INVALID_SET_CLEAR_MCPB_CHANNEL_NUM_MASK 0x000000ff
-#define BCHP_XPT_MEMDMA_MCPB_RUN_INVALID_SET_CLEAR_MCPB_CHANNEL_NUM_SHIFT 0
-#define BCHP_XPT_MEMDMA_MCPB_RUN_INVALID_SET_CLEAR_MCPB_CHANNEL_NUM_DEFAULT 0x00000000
-
-/***************************************************************************
- *RUN_INVALID_STATUS_0_31 - Run Invalid status
- ***************************************************************************/
-/* XPT_MEMDMA_MCPB :: RUN_INVALID_STATUS_0_31 :: RUN_INVALID_STATUS [31:00] */
-#define BCHP_XPT_MEMDMA_MCPB_RUN_INVALID_STATUS_0_31_RUN_INVALID_STATUS_MASK 0xffffffff
-#define BCHP_XPT_MEMDMA_MCPB_RUN_INVALID_STATUS_0_31_RUN_INVALID_STATUS_SHIFT 0
-#define BCHP_XPT_MEMDMA_MCPB_RUN_INVALID_STATUS_0_31_RUN_INVALID_STATUS_DEFAULT 0x00000000
-
-/***************************************************************************
- *CHANNEL_PRIORITY_SET - Set priority for channel arbitration
- ***************************************************************************/
-/* XPT_MEMDMA_MCPB :: CHANNEL_PRIORITY_SET :: reserved0 [31:10] */
-#define BCHP_XPT_MEMDMA_MCPB_CHANNEL_PRIORITY_SET_reserved0_MASK 0xfffffc00
-#define BCHP_XPT_MEMDMA_MCPB_CHANNEL_PRIORITY_SET_reserved0_SHIFT 10
-
-/* XPT_MEMDMA_MCPB :: CHANNEL_PRIORITY_SET :: SET_PRIORITY [09:08] */
-#define BCHP_XPT_MEMDMA_MCPB_CHANNEL_PRIORITY_SET_SET_PRIORITY_MASK 0x00000300
-#define BCHP_XPT_MEMDMA_MCPB_CHANNEL_PRIORITY_SET_SET_PRIORITY_SHIFT 8
-#define BCHP_XPT_MEMDMA_MCPB_CHANNEL_PRIORITY_SET_SET_PRIORITY_DEFAULT 0x00000000
-
-/* XPT_MEMDMA_MCPB :: CHANNEL_PRIORITY_SET :: MCPB_CHANNEL_NUM [07:00] */
-#define BCHP_XPT_MEMDMA_MCPB_CHANNEL_PRIORITY_SET_MCPB_CHANNEL_NUM_MASK 0x000000ff
-#define BCHP_XPT_MEMDMA_MCPB_CHANNEL_PRIORITY_SET_MCPB_CHANNEL_NUM_SHIFT 0
-#define BCHP_XPT_MEMDMA_MCPB_CHANNEL_PRIORITY_SET_MCPB_CHANNEL_NUM_DEFAULT 0x00000000
-
-/***************************************************************************
- *CHANNEL_PRIORITY_STATUS_0_15 - Channel priority status for channels 0 to 15
- ***************************************************************************/
-/* XPT_MEMDMA_MCPB :: CHANNEL_PRIORITY_STATUS_0_15 :: CHAN_15_PRIORITY [31:30] */
-#define BCHP_XPT_MEMDMA_MCPB_CHANNEL_PRIORITY_STATUS_0_15_CHAN_15_PRIORITY_MASK 0xc0000000
-#define BCHP_XPT_MEMDMA_MCPB_CHANNEL_PRIORITY_STATUS_0_15_CHAN_15_PRIORITY_SHIFT 30
-#define BCHP_XPT_MEMDMA_MCPB_CHANNEL_PRIORITY_STATUS_0_15_CHAN_15_PRIORITY_DEFAULT 0x00000001
-
-/* XPT_MEMDMA_MCPB :: CHANNEL_PRIORITY_STATUS_0_15 :: CHAN_14_PRIORITY [29:28] */
-#define BCHP_XPT_MEMDMA_MCPB_CHANNEL_PRIORITY_STATUS_0_15_CHAN_14_PRIORITY_MASK 0x30000000
-#define BCHP_XPT_MEMDMA_MCPB_CHANNEL_PRIORITY_STATUS_0_15_CHAN_14_PRIORITY_SHIFT 28
-#define BCHP_XPT_MEMDMA_MCPB_CHANNEL_PRIORITY_STATUS_0_15_CHAN_14_PRIORITY_DEFAULT 0x00000001
-
-/* XPT_MEMDMA_MCPB :: CHANNEL_PRIORITY_STATUS_0_15 :: CHAN_13_PRIORITY [27:26] */
-#define BCHP_XPT_MEMDMA_MCPB_CHANNEL_PRIORITY_STATUS_0_15_CHAN_13_PRIORITY_MASK 0x0c000000
-#define BCHP_XPT_MEMDMA_MCPB_CHANNEL_PRIORITY_STATUS_0_15_CHAN_13_PRIORITY_SHIFT 26
-#define BCHP_XPT_MEMDMA_MCPB_CHANNEL_PRIORITY_STATUS_0_15_CHAN_13_PRIORITY_DEFAULT 0x00000001
-
-/* XPT_MEMDMA_MCPB :: CHANNEL_PRIORITY_STATUS_0_15 :: CHAN_12_PRIORITY [25:24] */
-#define BCHP_XPT_MEMDMA_MCPB_CHANNEL_PRIORITY_STATUS_0_15_CHAN_12_PRIORITY_MASK 0x03000000
-#define BCHP_XPT_MEMDMA_MCPB_CHANNEL_PRIORITY_STATUS_0_15_CHAN_12_PRIORITY_SHIFT 24
-#define BCHP_XPT_MEMDMA_MCPB_CHANNEL_PRIORITY_STATUS_0_15_CHAN_12_PRIORITY_DEFAULT 0x00000001
-
-/* XPT_MEMDMA_MCPB :: CHANNEL_PRIORITY_STATUS_0_15 :: CHAN_11_PRIORITY [23:22] */
-#define BCHP_XPT_MEMDMA_MCPB_CHANNEL_PRIORITY_STATUS_0_15_CHAN_11_PRIORITY_MASK 0x00c00000
-#define BCHP_XPT_MEMDMA_MCPB_CHANNEL_PRIORITY_STATUS_0_15_CHAN_11_PRIORITY_SHIFT 22
-#define BCHP_XPT_MEMDMA_MCPB_CHANNEL_PRIORITY_STATUS_0_15_CHAN_11_PRIORITY_DEFAULT 0x00000001
-
-/* XPT_MEMDMA_MCPB :: CHANNEL_PRIORITY_STATUS_0_15 :: CHAN_10_PRIORITY [21:20] */
-#define BCHP_XPT_MEMDMA_MCPB_CHANNEL_PRIORITY_STATUS_0_15_CHAN_10_PRIORITY_MASK 0x00300000
-#define BCHP_XPT_MEMDMA_MCPB_CHANNEL_PRIORITY_STATUS_0_15_CHAN_10_PRIORITY_SHIFT 20
-#define BCHP_XPT_MEMDMA_MCPB_CHANNEL_PRIORITY_STATUS_0_15_CHAN_10_PRIORITY_DEFAULT 0x00000001
-
-/* XPT_MEMDMA_MCPB :: CHANNEL_PRIORITY_STATUS_0_15 :: CHAN_9_PRIORITY [19:18] */
-#define BCHP_XPT_MEMDMA_MCPB_CHANNEL_PRIORITY_STATUS_0_15_CHAN_9_PRIORITY_MASK 0x000c0000
-#define BCHP_XPT_MEMDMA_MCPB_CHANNEL_PRIORITY_STATUS_0_15_CHAN_9_PRIORITY_SHIFT 18
-#define BCHP_XPT_MEMDMA_MCPB_CHANNEL_PRIORITY_STATUS_0_15_CHAN_9_PRIORITY_DEFAULT 0x00000001
-
-/* XPT_MEMDMA_MCPB :: CHANNEL_PRIORITY_STATUS_0_15 :: CHAN_8_PRIORITY [17:16] */
-#define BCHP_XPT_MEMDMA_MCPB_CHANNEL_PRIORITY_STATUS_0_15_CHAN_8_PRIORITY_MASK 0x00030000
-#define BCHP_XPT_MEMDMA_MCPB_CHANNEL_PRIORITY_STATUS_0_15_CHAN_8_PRIORITY_SHIFT 16
-#define BCHP_XPT_MEMDMA_MCPB_CHANNEL_PRIORITY_STATUS_0_15_CHAN_8_PRIORITY_DEFAULT 0x00000001
-
-/* XPT_MEMDMA_MCPB :: CHANNEL_PRIORITY_STATUS_0_15 :: CHAN_7_PRIORITY [15:14] */
-#define BCHP_XPT_MEMDMA_MCPB_CHANNEL_PRIORITY_STATUS_0_15_CHAN_7_PRIORITY_MASK 0x0000c000
-#define BCHP_XPT_MEMDMA_MCPB_CHANNEL_PRIORITY_STATUS_0_15_CHAN_7_PRIORITY_SHIFT 14
-#define BCHP_XPT_MEMDMA_MCPB_CHANNEL_PRIORITY_STATUS_0_15_CHAN_7_PRIORITY_DEFAULT 0x00000001
-
-/* XPT_MEMDMA_MCPB :: CHANNEL_PRIORITY_STATUS_0_15 :: CHAN_6_PRIORITY [13:12] */
-#define BCHP_XPT_MEMDMA_MCPB_CHANNEL_PRIORITY_STATUS_0_15_CHAN_6_PRIORITY_MASK 0x00003000
-#define BCHP_XPT_MEMDMA_MCPB_CHANNEL_PRIORITY_STATUS_0_15_CHAN_6_PRIORITY_SHIFT 12
-#define BCHP_XPT_MEMDMA_MCPB_CHANNEL_PRIORITY_STATUS_0_15_CHAN_6_PRIORITY_DEFAULT 0x00000001
-
-/* XPT_MEMDMA_MCPB :: CHANNEL_PRIORITY_STATUS_0_15 :: CHAN_5_PRIORITY [11:10] */
-#define BCHP_XPT_MEMDMA_MCPB_CHANNEL_PRIORITY_STATUS_0_15_CHAN_5_PRIORITY_MASK 0x00000c00
-#define BCHP_XPT_MEMDMA_MCPB_CHANNEL_PRIORITY_STATUS_0_15_CHAN_5_PRIORITY_SHIFT 10
-#define BCHP_XPT_MEMDMA_MCPB_CHANNEL_PRIORITY_STATUS_0_15_CHAN_5_PRIORITY_DEFAULT 0x00000001
-
-/* XPT_MEMDMA_MCPB :: CHANNEL_PRIORITY_STATUS_0_15 :: CHAN_4_PRIORITY [09:08] */
-#define BCHP_XPT_MEMDMA_MCPB_CHANNEL_PRIORITY_STATUS_0_15_CHAN_4_PRIORITY_MASK 0x00000300
-#define BCHP_XPT_MEMDMA_MCPB_CHANNEL_PRIORITY_STATUS_0_15_CHAN_4_PRIORITY_SHIFT 8
-#define BCHP_XPT_MEMDMA_MCPB_CHANNEL_PRIORITY_STATUS_0_15_CHAN_4_PRIORITY_DEFAULT 0x00000001
-
-/* XPT_MEMDMA_MCPB :: CHANNEL_PRIORITY_STATUS_0_15 :: CHAN_3_PRIORITY [07:06] */
-#define BCHP_XPT_MEMDMA_MCPB_CHANNEL_PRIORITY_STATUS_0_15_CHAN_3_PRIORITY_MASK 0x000000c0
-#define BCHP_XPT_MEMDMA_MCPB_CHANNEL_PRIORITY_STATUS_0_15_CHAN_3_PRIORITY_SHIFT 6
-#define BCHP_XPT_MEMDMA_MCPB_CHANNEL_PRIORITY_STATUS_0_15_CHAN_3_PRIORITY_DEFAULT 0x00000001
-
-/* XPT_MEMDMA_MCPB :: CHANNEL_PRIORITY_STATUS_0_15 :: CHAN_2_PRIORITY [05:04] */
-#define BCHP_XPT_MEMDMA_MCPB_CHANNEL_PRIORITY_STATUS_0_15_CHAN_2_PRIORITY_MASK 0x00000030
-#define BCHP_XPT_MEMDMA_MCPB_CHANNEL_PRIORITY_STATUS_0_15_CHAN_2_PRIORITY_SHIFT 4
-#define BCHP_XPT_MEMDMA_MCPB_CHANNEL_PRIORITY_STATUS_0_15_CHAN_2_PRIORITY_DEFAULT 0x00000001
-
-/* XPT_MEMDMA_MCPB :: CHANNEL_PRIORITY_STATUS_0_15 :: CHAN_1_PRIORITY [03:02] */
-#define BCHP_XPT_MEMDMA_MCPB_CHANNEL_PRIORITY_STATUS_0_15_CHAN_1_PRIORITY_MASK 0x0000000c
-#define BCHP_XPT_MEMDMA_MCPB_CHANNEL_PRIORITY_STATUS_0_15_CHAN_1_PRIORITY_SHIFT 2
-#define BCHP_XPT_MEMDMA_MCPB_CHANNEL_PRIORITY_STATUS_0_15_CHAN_1_PRIORITY_DEFAULT 0x00000001
-
-/* XPT_MEMDMA_MCPB :: CHANNEL_PRIORITY_STATUS_0_15 :: CHAN_0_PRIORITY [01:00] */
-#define BCHP_XPT_MEMDMA_MCPB_CHANNEL_PRIORITY_STATUS_0_15_CHAN_0_PRIORITY_MASK 0x00000003
-#define BCHP_XPT_MEMDMA_MCPB_CHANNEL_PRIORITY_STATUS_0_15_CHAN_0_PRIORITY_SHIFT 0
-#define BCHP_XPT_MEMDMA_MCPB_CHANNEL_PRIORITY_STATUS_0_15_CHAN_0_PRIORITY_DEFAULT 0x00000001
-
-/***************************************************************************
- *CHANNEL_PRIORITY_STATUS_16_31 - Channel priority status for channels 16 to 31
- ***************************************************************************/
-/* XPT_MEMDMA_MCPB :: CHANNEL_PRIORITY_STATUS_16_31 :: CHAN_31_PRIORITY [31:30] */
-#define BCHP_XPT_MEMDMA_MCPB_CHANNEL_PRIORITY_STATUS_16_31_CHAN_31_PRIORITY_MASK 0xc0000000
-#define BCHP_XPT_MEMDMA_MCPB_CHANNEL_PRIORITY_STATUS_16_31_CHAN_31_PRIORITY_SHIFT 30
-#define BCHP_XPT_MEMDMA_MCPB_CHANNEL_PRIORITY_STATUS_16_31_CHAN_31_PRIORITY_DEFAULT 0x00000001
-
-/* XPT_MEMDMA_MCPB :: CHANNEL_PRIORITY_STATUS_16_31 :: CHAN_30_PRIORITY [29:28] */
-#define BCHP_XPT_MEMDMA_MCPB_CHANNEL_PRIORITY_STATUS_16_31_CHAN_30_PRIORITY_MASK 0x30000000
-#define BCHP_XPT_MEMDMA_MCPB_CHANNEL_PRIORITY_STATUS_16_31_CHAN_30_PRIORITY_SHIFT 28
-#define BCHP_XPT_MEMDMA_MCPB_CHANNEL_PRIORITY_STATUS_16_31_CHAN_30_PRIORITY_DEFAULT 0x00000001
-
-/* XPT_MEMDMA_MCPB :: CHANNEL_PRIORITY_STATUS_16_31 :: CHAN_29_PRIORITY [27:26] */
-#define BCHP_XPT_MEMDMA_MCPB_CHANNEL_PRIORITY_STATUS_16_31_CHAN_29_PRIORITY_MASK 0x0c000000
-#define BCHP_XPT_MEMDMA_MCPB_CHANNEL_PRIORITY_STATUS_16_31_CHAN_29_PRIORITY_SHIFT 26
-#define BCHP_XPT_MEMDMA_MCPB_CHANNEL_PRIORITY_STATUS_16_31_CHAN_29_PRIORITY_DEFAULT 0x00000001
-
-/* XPT_MEMDMA_MCPB :: CHANNEL_PRIORITY_STATUS_16_31 :: CHAN_28_PRIORITY [25:24] */
-#define BCHP_XPT_MEMDMA_MCPB_CHANNEL_PRIORITY_STATUS_16_31_CHAN_28_PRIORITY_MASK 0x03000000
-#define BCHP_XPT_MEMDMA_MCPB_CHANNEL_PRIORITY_STATUS_16_31_CHAN_28_PRIORITY_SHIFT 24
-#define BCHP_XPT_MEMDMA_MCPB_CHANNEL_PRIORITY_STATUS_16_31_CHAN_28_PRIORITY_DEFAULT 0x00000001
-
-/* XPT_MEMDMA_MCPB :: CHANNEL_PRIORITY_STATUS_16_31 :: CHAN_27_PRIORITY [23:22] */
-#define BCHP_XPT_MEMDMA_MCPB_CHANNEL_PRIORITY_STATUS_16_31_CHAN_27_PRIORITY_MASK 0x00c00000
-#define BCHP_XPT_MEMDMA_MCPB_CHANNEL_PRIORITY_STATUS_16_31_CHAN_27_PRIORITY_SHIFT 22
-#define BCHP_XPT_MEMDMA_MCPB_CHANNEL_PRIORITY_STATUS_16_31_CHAN_27_PRIORITY_DEFAULT 0x00000001
-
-/* XPT_MEMDMA_MCPB :: CHANNEL_PRIORITY_STATUS_16_31 :: CHAN_26_PRIORITY [21:20] */
-#define BCHP_XPT_MEMDMA_MCPB_CHANNEL_PRIORITY_STATUS_16_31_CHAN_26_PRIORITY_MASK 0x00300000
-#define BCHP_XPT_MEMDMA_MCPB_CHANNEL_PRIORITY_STATUS_16_31_CHAN_26_PRIORITY_SHIFT 20
-#define BCHP_XPT_MEMDMA_MCPB_CHANNEL_PRIORITY_STATUS_16_31_CHAN_26_PRIORITY_DEFAULT 0x00000001
-
-/* XPT_MEMDMA_MCPB :: CHANNEL_PRIORITY_STATUS_16_31 :: CHAN_25_PRIORITY [19:18] */
-#define BCHP_XPT_MEMDMA_MCPB_CHANNEL_PRIORITY_STATUS_16_31_CHAN_25_PRIORITY_MASK 0x000c0000
-#define BCHP_XPT_MEMDMA_MCPB_CHANNEL_PRIORITY_STATUS_16_31_CHAN_25_PRIORITY_SHIFT 18
-#define BCHP_XPT_MEMDMA_MCPB_CHANNEL_PRIORITY_STATUS_16_31_CHAN_25_PRIORITY_DEFAULT 0x00000001
-
-/* XPT_MEMDMA_MCPB :: CHANNEL_PRIORITY_STATUS_16_31 :: CHAN_24_PRIORITY [17:16] */
-#define BCHP_XPT_MEMDMA_MCPB_CHANNEL_PRIORITY_STATUS_16_31_CHAN_24_PRIORITY_MASK 0x00030000
-#define BCHP_XPT_MEMDMA_MCPB_CHANNEL_PRIORITY_STATUS_16_31_CHAN_24_PRIORITY_SHIFT 16
-#define BCHP_XPT_MEMDMA_MCPB_CHANNEL_PRIORITY_STATUS_16_31_CHAN_24_PRIORITY_DEFAULT 0x00000001
-
-/* XPT_MEMDMA_MCPB :: CHANNEL_PRIORITY_STATUS_16_31 :: CHAN_23_PRIORITY [15:14] */
-#define BCHP_XPT_MEMDMA_MCPB_CHANNEL_PRIORITY_STATUS_16_31_CHAN_23_PRIORITY_MASK 0x0000c000
-#define BCHP_XPT_MEMDMA_MCPB_CHANNEL_PRIORITY_STATUS_16_31_CHAN_23_PRIORITY_SHIFT 14
-#define BCHP_XPT_MEMDMA_MCPB_CHANNEL_PRIORITY_STATUS_16_31_CHAN_23_PRIORITY_DEFAULT 0x00000001
-
-/* XPT_MEMDMA_MCPB :: CHANNEL_PRIORITY_STATUS_16_31 :: CHAN_22_PRIORITY [13:12] */
-#define BCHP_XPT_MEMDMA_MCPB_CHANNEL_PRIORITY_STATUS_16_31_CHAN_22_PRIORITY_MASK 0x00003000
-#define BCHP_XPT_MEMDMA_MCPB_CHANNEL_PRIORITY_STATUS_16_31_CHAN_22_PRIORITY_SHIFT 12
-#define BCHP_XPT_MEMDMA_MCPB_CHANNEL_PRIORITY_STATUS_16_31_CHAN_22_PRIORITY_DEFAULT 0x00000001
-
-/* XPT_MEMDMA_MCPB :: CHANNEL_PRIORITY_STATUS_16_31 :: CHAN_21_PRIORITY [11:10] */
-#define BCHP_XPT_MEMDMA_MCPB_CHANNEL_PRIORITY_STATUS_16_31_CHAN_21_PRIORITY_MASK 0x00000c00
-#define BCHP_XPT_MEMDMA_MCPB_CHANNEL_PRIORITY_STATUS_16_31_CHAN_21_PRIORITY_SHIFT 10
-#define BCHP_XPT_MEMDMA_MCPB_CHANNEL_PRIORITY_STATUS_16_31_CHAN_21_PRIORITY_DEFAULT 0x00000001
-
-/* XPT_MEMDMA_MCPB :: CHANNEL_PRIORITY_STATUS_16_31 :: CHAN_20_PRIORITY [09:08] */
-#define BCHP_XPT_MEMDMA_MCPB_CHANNEL_PRIORITY_STATUS_16_31_CHAN_20_PRIORITY_MASK 0x00000300
-#define BCHP_XPT_MEMDMA_MCPB_CHANNEL_PRIORITY_STATUS_16_31_CHAN_20_PRIORITY_SHIFT 8
-#define BCHP_XPT_MEMDMA_MCPB_CHANNEL_PRIORITY_STATUS_16_31_CHAN_20_PRIORITY_DEFAULT 0x00000001
-
-/* XPT_MEMDMA_MCPB :: CHANNEL_PRIORITY_STATUS_16_31 :: CHAN_19_PRIORITY [07:06] */
-#define BCHP_XPT_MEMDMA_MCPB_CHANNEL_PRIORITY_STATUS_16_31_CHAN_19_PRIORITY_MASK 0x000000c0
-#define BCHP_XPT_MEMDMA_MCPB_CHANNEL_PRIORITY_STATUS_16_31_CHAN_19_PRIORITY_SHIFT 6
-#define BCHP_XPT_MEMDMA_MCPB_CHANNEL_PRIORITY_STATUS_16_31_CHAN_19_PRIORITY_DEFAULT 0x00000001
-
-/* XPT_MEMDMA_MCPB :: CHANNEL_PRIORITY_STATUS_16_31 :: CHAN_18_PRIORITY [05:04] */
-#define BCHP_XPT_MEMDMA_MCPB_CHANNEL_PRIORITY_STATUS_16_31_CHAN_18_PRIORITY_MASK 0x00000030
-#define BCHP_XPT_MEMDMA_MCPB_CHANNEL_PRIORITY_STATUS_16_31_CHAN_18_PRIORITY_SHIFT 4
-#define BCHP_XPT_MEMDMA_MCPB_CHANNEL_PRIORITY_STATUS_16_31_CHAN_18_PRIORITY_DEFAULT 0x00000001
-
-/* XPT_MEMDMA_MCPB :: CHANNEL_PRIORITY_STATUS_16_31 :: CHAN_17_PRIORITY [03:02] */
-#define BCHP_XPT_MEMDMA_MCPB_CHANNEL_PRIORITY_STATUS_16_31_CHAN_17_PRIORITY_MASK 0x0000000c
-#define BCHP_XPT_MEMDMA_MCPB_CHANNEL_PRIORITY_STATUS_16_31_CHAN_17_PRIORITY_SHIFT 2
-#define BCHP_XPT_MEMDMA_MCPB_CHANNEL_PRIORITY_STATUS_16_31_CHAN_17_PRIORITY_DEFAULT 0x00000001
-
-/* XPT_MEMDMA_MCPB :: CHANNEL_PRIORITY_STATUS_16_31 :: CHAN_16_PRIORITY [01:00] */
-#define BCHP_XPT_MEMDMA_MCPB_CHANNEL_PRIORITY_STATUS_16_31_CHAN_16_PRIORITY_MASK 0x00000003
-#define BCHP_XPT_MEMDMA_MCPB_CHANNEL_PRIORITY_STATUS_16_31_CHAN_16_PRIORITY_SHIFT 0
-#define BCHP_XPT_MEMDMA_MCPB_CHANNEL_PRIORITY_STATUS_16_31_CHAN_16_PRIORITY_DEFAULT 0x00000001
-
-/***************************************************************************
- *BAND_PAUSE_MAPPING_VECTOR_0 - MCPB Band pause mapping vector for channel 0
- ***************************************************************************/
-/* XPT_MEMDMA_MCPB :: BAND_PAUSE_MAPPING_VECTOR_0 :: BAND_PAUSE_MAPPING_VECTOR [31:00] */
-#define BCHP_XPT_MEMDMA_MCPB_BAND_PAUSE_MAPPING_VECTOR_0_BAND_PAUSE_MAPPING_VECTOR_MASK 0xffffffff
-#define BCHP_XPT_MEMDMA_MCPB_BAND_PAUSE_MAPPING_VECTOR_0_BAND_PAUSE_MAPPING_VECTOR_SHIFT 0
-#define BCHP_XPT_MEMDMA_MCPB_BAND_PAUSE_MAPPING_VECTOR_0_BAND_PAUSE_MAPPING_VECTOR_DEFAULT 0x00000001
-
-/***************************************************************************
- *BAND_PAUSE_MAPPING_VECTOR_1 - MCPB Band pause mapping vector for channel 1
- ***************************************************************************/
-/* XPT_MEMDMA_MCPB :: BAND_PAUSE_MAPPING_VECTOR_1 :: BAND_PAUSE_MAPPING_VECTOR [31:00] */
-#define BCHP_XPT_MEMDMA_MCPB_BAND_PAUSE_MAPPING_VECTOR_1_BAND_PAUSE_MAPPING_VECTOR_MASK 0xffffffff
-#define BCHP_XPT_MEMDMA_MCPB_BAND_PAUSE_MAPPING_VECTOR_1_BAND_PAUSE_MAPPING_VECTOR_SHIFT 0
-#define BCHP_XPT_MEMDMA_MCPB_BAND_PAUSE_MAPPING_VECTOR_1_BAND_PAUSE_MAPPING_VECTOR_DEFAULT 0x00000002
-
-/***************************************************************************
- *BAND_PAUSE_MAPPING_VECTOR_2 - MCPB Band pause mapping vector for channel 2
- ***************************************************************************/
-/* XPT_MEMDMA_MCPB :: BAND_PAUSE_MAPPING_VECTOR_2 :: BAND_PAUSE_MAPPING_VECTOR [31:00] */
-#define BCHP_XPT_MEMDMA_MCPB_BAND_PAUSE_MAPPING_VECTOR_2_BAND_PAUSE_MAPPING_VECTOR_MASK 0xffffffff
-#define BCHP_XPT_MEMDMA_MCPB_BAND_PAUSE_MAPPING_VECTOR_2_BAND_PAUSE_MAPPING_VECTOR_SHIFT 0
-#define BCHP_XPT_MEMDMA_MCPB_BAND_PAUSE_MAPPING_VECTOR_2_BAND_PAUSE_MAPPING_VECTOR_DEFAULT 0x00000004
-
-/***************************************************************************
- *BAND_PAUSE_MAPPING_VECTOR_3 - MCPB Band pause mapping vector for channel 3
- ***************************************************************************/
-/* XPT_MEMDMA_MCPB :: BAND_PAUSE_MAPPING_VECTOR_3 :: BAND_PAUSE_MAPPING_VECTOR [31:00] */
-#define BCHP_XPT_MEMDMA_MCPB_BAND_PAUSE_MAPPING_VECTOR_3_BAND_PAUSE_MAPPING_VECTOR_MASK 0xffffffff
-#define BCHP_XPT_MEMDMA_MCPB_BAND_PAUSE_MAPPING_VECTOR_3_BAND_PAUSE_MAPPING_VECTOR_SHIFT 0
-#define BCHP_XPT_MEMDMA_MCPB_BAND_PAUSE_MAPPING_VECTOR_3_BAND_PAUSE_MAPPING_VECTOR_DEFAULT 0x00000008
-
-/***************************************************************************
- *BAND_PAUSE_MAPPING_VECTOR_4 - MCPB Band pause mapping vector for channel 4
- ***************************************************************************/
-/* XPT_MEMDMA_MCPB :: BAND_PAUSE_MAPPING_VECTOR_4 :: BAND_PAUSE_MAPPING_VECTOR [31:00] */
-#define BCHP_XPT_MEMDMA_MCPB_BAND_PAUSE_MAPPING_VECTOR_4_BAND_PAUSE_MAPPING_VECTOR_MASK 0xffffffff
-#define BCHP_XPT_MEMDMA_MCPB_BAND_PAUSE_MAPPING_VECTOR_4_BAND_PAUSE_MAPPING_VECTOR_SHIFT 0
-#define BCHP_XPT_MEMDMA_MCPB_BAND_PAUSE_MAPPING_VECTOR_4_BAND_PAUSE_MAPPING_VECTOR_DEFAULT 0x00000010
-
-/***************************************************************************
- *BAND_PAUSE_MAPPING_VECTOR_5 - MCPB Band pause mapping vector for channel 5
- ***************************************************************************/
-/* XPT_MEMDMA_MCPB :: BAND_PAUSE_MAPPING_VECTOR_5 :: BAND_PAUSE_MAPPING_VECTOR [31:00] */
-#define BCHP_XPT_MEMDMA_MCPB_BAND_PAUSE_MAPPING_VECTOR_5_BAND_PAUSE_MAPPING_VECTOR_MASK 0xffffffff
-#define BCHP_XPT_MEMDMA_MCPB_BAND_PAUSE_MAPPING_VECTOR_5_BAND_PAUSE_MAPPING_VECTOR_SHIFT 0
-#define BCHP_XPT_MEMDMA_MCPB_BAND_PAUSE_MAPPING_VECTOR_5_BAND_PAUSE_MAPPING_VECTOR_DEFAULT 0x00000020
-
-/***************************************************************************
- *BAND_PAUSE_MAPPING_VECTOR_6 - MCPB Band pause mapping vector for channel 6
- ***************************************************************************/
-/* XPT_MEMDMA_MCPB :: BAND_PAUSE_MAPPING_VECTOR_6 :: BAND_PAUSE_MAPPING_VECTOR [31:00] */
-#define BCHP_XPT_MEMDMA_MCPB_BAND_PAUSE_MAPPING_VECTOR_6_BAND_PAUSE_MAPPING_VECTOR_MASK 0xffffffff
-#define BCHP_XPT_MEMDMA_MCPB_BAND_PAUSE_MAPPING_VECTOR_6_BAND_PAUSE_MAPPING_VECTOR_SHIFT 0
-#define BCHP_XPT_MEMDMA_MCPB_BAND_PAUSE_MAPPING_VECTOR_6_BAND_PAUSE_MAPPING_VECTOR_DEFAULT 0x00000040
-
-/***************************************************************************
- *BAND_PAUSE_MAPPING_VECTOR_7 - MCPB Band pause mapping vector for channel 7
- ***************************************************************************/
-/* XPT_MEMDMA_MCPB :: BAND_PAUSE_MAPPING_VECTOR_7 :: BAND_PAUSE_MAPPING_VECTOR [31:00] */
-#define BCHP_XPT_MEMDMA_MCPB_BAND_PAUSE_MAPPING_VECTOR_7_BAND_PAUSE_MAPPING_VECTOR_MASK 0xffffffff
-#define BCHP_XPT_MEMDMA_MCPB_BAND_PAUSE_MAPPING_VECTOR_7_BAND_PAUSE_MAPPING_VECTOR_SHIFT 0
-#define BCHP_XPT_MEMDMA_MCPB_BAND_PAUSE_MAPPING_VECTOR_7_BAND_PAUSE_MAPPING_VECTOR_DEFAULT 0x00000080
-
-/***************************************************************************
- *BAND_PAUSE_MAPPING_VECTOR_8 - MCPB Band pause mapping vector for channel 8
- ***************************************************************************/
-/* XPT_MEMDMA_MCPB :: BAND_PAUSE_MAPPING_VECTOR_8 :: BAND_PAUSE_MAPPING_VECTOR [31:00] */
-#define BCHP_XPT_MEMDMA_MCPB_BAND_PAUSE_MAPPING_VECTOR_8_BAND_PAUSE_MAPPING_VECTOR_MASK 0xffffffff
-#define BCHP_XPT_MEMDMA_MCPB_BAND_PAUSE_MAPPING_VECTOR_8_BAND_PAUSE_MAPPING_VECTOR_SHIFT 0
-#define BCHP_XPT_MEMDMA_MCPB_BAND_PAUSE_MAPPING_VECTOR_8_BAND_PAUSE_MAPPING_VECTOR_DEFAULT 0x00000100
-
-/***************************************************************************
- *BAND_PAUSE_MAPPING_VECTOR_9 - MCPB Band pause mapping vector for channel 9
- ***************************************************************************/
-/* XPT_MEMDMA_MCPB :: BAND_PAUSE_MAPPING_VECTOR_9 :: BAND_PAUSE_MAPPING_VECTOR [31:00] */
-#define BCHP_XPT_MEMDMA_MCPB_BAND_PAUSE_MAPPING_VECTOR_9_BAND_PAUSE_MAPPING_VECTOR_MASK 0xffffffff
-#define BCHP_XPT_MEMDMA_MCPB_BAND_PAUSE_MAPPING_VECTOR_9_BAND_PAUSE_MAPPING_VECTOR_SHIFT 0
-#define BCHP_XPT_MEMDMA_MCPB_BAND_PAUSE_MAPPING_VECTOR_9_BAND_PAUSE_MAPPING_VECTOR_DEFAULT 0x00000200
-
-/***************************************************************************
- *BAND_PAUSE_MAPPING_VECTOR_10 - MCPB Band pause mapping vector for channel 10
- ***************************************************************************/
-/* XPT_MEMDMA_MCPB :: BAND_PAUSE_MAPPING_VECTOR_10 :: BAND_PAUSE_MAPPING_VECTOR [31:00] */
-#define BCHP_XPT_MEMDMA_MCPB_BAND_PAUSE_MAPPING_VECTOR_10_BAND_PAUSE_MAPPING_VECTOR_MASK 0xffffffff
-#define BCHP_XPT_MEMDMA_MCPB_BAND_PAUSE_MAPPING_VECTOR_10_BAND_PAUSE_MAPPING_VECTOR_SHIFT 0
-#define BCHP_XPT_MEMDMA_MCPB_BAND_PAUSE_MAPPING_VECTOR_10_BAND_PAUSE_MAPPING_VECTOR_DEFAULT 0x00000400
-
-/***************************************************************************
- *BAND_PAUSE_MAPPING_VECTOR_11 - MCPB Band pause mapping vector for channel 11
- ***************************************************************************/
-/* XPT_MEMDMA_MCPB :: BAND_PAUSE_MAPPING_VECTOR_11 :: BAND_PAUSE_MAPPING_VECTOR [31:00] */
-#define BCHP_XPT_MEMDMA_MCPB_BAND_PAUSE_MAPPING_VECTOR_11_BAND_PAUSE_MAPPING_VECTOR_MASK 0xffffffff
-#define BCHP_XPT_MEMDMA_MCPB_BAND_PAUSE_MAPPING_VECTOR_11_BAND_PAUSE_MAPPING_VECTOR_SHIFT 0
-#define BCHP_XPT_MEMDMA_MCPB_BAND_PAUSE_MAPPING_VECTOR_11_BAND_PAUSE_MAPPING_VECTOR_DEFAULT 0x00000800
-
-/***************************************************************************
- *BAND_PAUSE_MAPPING_VECTOR_12 - MCPB Band pause mapping vector for channel 12
- ***************************************************************************/
-/* XPT_MEMDMA_MCPB :: BAND_PAUSE_MAPPING_VECTOR_12 :: BAND_PAUSE_MAPPING_VECTOR [31:00] */
-#define BCHP_XPT_MEMDMA_MCPB_BAND_PAUSE_MAPPING_VECTOR_12_BAND_PAUSE_MAPPING_VECTOR_MASK 0xffffffff
-#define BCHP_XPT_MEMDMA_MCPB_BAND_PAUSE_MAPPING_VECTOR_12_BAND_PAUSE_MAPPING_VECTOR_SHIFT 0
-#define BCHP_XPT_MEMDMA_MCPB_BAND_PAUSE_MAPPING_VECTOR_12_BAND_PAUSE_MAPPING_VECTOR_DEFAULT 0x00001000
-
-/***************************************************************************
- *BAND_PAUSE_MAPPING_VECTOR_13 - MCPB Band pause mapping vector for channel 13
- ***************************************************************************/
-/* XPT_MEMDMA_MCPB :: BAND_PAUSE_MAPPING_VECTOR_13 :: BAND_PAUSE_MAPPING_VECTOR [31:00] */
-#define BCHP_XPT_MEMDMA_MCPB_BAND_PAUSE_MAPPING_VECTOR_13_BAND_PAUSE_MAPPING_VECTOR_MASK 0xffffffff
-#define BCHP_XPT_MEMDMA_MCPB_BAND_PAUSE_MAPPING_VECTOR_13_BAND_PAUSE_MAPPING_VECTOR_SHIFT 0
-#define BCHP_XPT_MEMDMA_MCPB_BAND_PAUSE_MAPPING_VECTOR_13_BAND_PAUSE_MAPPING_VECTOR_DEFAULT 0x00002000
-
-/***************************************************************************
- *BAND_PAUSE_MAPPING_VECTOR_14 - MCPB Band pause mapping vector for channel 14
- ***************************************************************************/
-/* XPT_MEMDMA_MCPB :: BAND_PAUSE_MAPPING_VECTOR_14 :: BAND_PAUSE_MAPPING_VECTOR [31:00] */
-#define BCHP_XPT_MEMDMA_MCPB_BAND_PAUSE_MAPPING_VECTOR_14_BAND_PAUSE_MAPPING_VECTOR_MASK 0xffffffff
-#define BCHP_XPT_MEMDMA_MCPB_BAND_PAUSE_MAPPING_VECTOR_14_BAND_PAUSE_MAPPING_VECTOR_SHIFT 0
-#define BCHP_XPT_MEMDMA_MCPB_BAND_PAUSE_MAPPING_VECTOR_14_BAND_PAUSE_MAPPING_VECTOR_DEFAULT 0x00004000
-
-/***************************************************************************
- *BAND_PAUSE_MAPPING_VECTOR_15 - MCPB Band pause mapping vector for channel 15
- ***************************************************************************/
-/* XPT_MEMDMA_MCPB :: BAND_PAUSE_MAPPING_VECTOR_15 :: BAND_PAUSE_MAPPING_VECTOR [31:00] */
-#define BCHP_XPT_MEMDMA_MCPB_BAND_PAUSE_MAPPING_VECTOR_15_BAND_PAUSE_MAPPING_VECTOR_MASK 0xffffffff
-#define BCHP_XPT_MEMDMA_MCPB_BAND_PAUSE_MAPPING_VECTOR_15_BAND_PAUSE_MAPPING_VECTOR_SHIFT 0
-#define BCHP_XPT_MEMDMA_MCPB_BAND_PAUSE_MAPPING_VECTOR_15_BAND_PAUSE_MAPPING_VECTOR_DEFAULT 0x00008000
-
-/***************************************************************************
- *BAND_PAUSE_MAPPING_VECTOR_16 - MCPB Band pause mapping vector for channel 16
- ***************************************************************************/
-/* XPT_MEMDMA_MCPB :: BAND_PAUSE_MAPPING_VECTOR_16 :: BAND_PAUSE_MAPPING_VECTOR [31:00] */
-#define BCHP_XPT_MEMDMA_MCPB_BAND_PAUSE_MAPPING_VECTOR_16_BAND_PAUSE_MAPPING_VECTOR_MASK 0xffffffff
-#define BCHP_XPT_MEMDMA_MCPB_BAND_PAUSE_MAPPING_VECTOR_16_BAND_PAUSE_MAPPING_VECTOR_SHIFT 0
-#define BCHP_XPT_MEMDMA_MCPB_BAND_PAUSE_MAPPING_VECTOR_16_BAND_PAUSE_MAPPING_VECTOR_DEFAULT 0x00010000
-
-/***************************************************************************
- *BAND_PAUSE_MAPPING_VECTOR_17 - MCPB Band pause mapping vector for channel 17
- ***************************************************************************/
-/* XPT_MEMDMA_MCPB :: BAND_PAUSE_MAPPING_VECTOR_17 :: BAND_PAUSE_MAPPING_VECTOR [31:00] */
-#define BCHP_XPT_MEMDMA_MCPB_BAND_PAUSE_MAPPING_VECTOR_17_BAND_PAUSE_MAPPING_VECTOR_MASK 0xffffffff
-#define BCHP_XPT_MEMDMA_MCPB_BAND_PAUSE_MAPPING_VECTOR_17_BAND_PAUSE_MAPPING_VECTOR_SHIFT 0
-#define BCHP_XPT_MEMDMA_MCPB_BAND_PAUSE_MAPPING_VECTOR_17_BAND_PAUSE_MAPPING_VECTOR_DEFAULT 0x00020000
-
-/***************************************************************************
- *BAND_PAUSE_MAPPING_VECTOR_18 - MCPB Band pause mapping vector for channel 18
- ***************************************************************************/
-/* XPT_MEMDMA_MCPB :: BAND_PAUSE_MAPPING_VECTOR_18 :: BAND_PAUSE_MAPPING_VECTOR [31:00] */
-#define BCHP_XPT_MEMDMA_MCPB_BAND_PAUSE_MAPPING_VECTOR_18_BAND_PAUSE_MAPPING_VECTOR_MASK 0xffffffff
-#define BCHP_XPT_MEMDMA_MCPB_BAND_PAUSE_MAPPING_VECTOR_18_BAND_PAUSE_MAPPING_VECTOR_SHIFT 0
-#define BCHP_XPT_MEMDMA_MCPB_BAND_PAUSE_MAPPING_VECTOR_18_BAND_PAUSE_MAPPING_VECTOR_DEFAULT 0x00040000
-
-/***************************************************************************
- *BAND_PAUSE_MAPPING_VECTOR_19 - MCPB Band pause mapping vector for channel 19
- ***************************************************************************/
-/* XPT_MEMDMA_MCPB :: BAND_PAUSE_MAPPING_VECTOR_19 :: BAND_PAUSE_MAPPING_VECTOR [31:00] */
-#define BCHP_XPT_MEMDMA_MCPB_BAND_PAUSE_MAPPING_VECTOR_19_BAND_PAUSE_MAPPING_VECTOR_MASK 0xffffffff
-#define BCHP_XPT_MEMDMA_MCPB_BAND_PAUSE_MAPPING_VECTOR_19_BAND_PAUSE_MAPPING_VECTOR_SHIFT 0
-#define BCHP_XPT_MEMDMA_MCPB_BAND_PAUSE_MAPPING_VECTOR_19_BAND_PAUSE_MAPPING_VECTOR_DEFAULT 0x00080000
-
-/***************************************************************************
- *BAND_PAUSE_MAPPING_VECTOR_20 - MCPB Band pause mapping vector for channel 20
- ***************************************************************************/
-/* XPT_MEMDMA_MCPB :: BAND_PAUSE_MAPPING_VECTOR_20 :: BAND_PAUSE_MAPPING_VECTOR [31:00] */
-#define BCHP_XPT_MEMDMA_MCPB_BAND_PAUSE_MAPPING_VECTOR_20_BAND_PAUSE_MAPPING_VECTOR_MASK 0xffffffff
-#define BCHP_XPT_MEMDMA_MCPB_BAND_PAUSE_MAPPING_VECTOR_20_BAND_PAUSE_MAPPING_VECTOR_SHIFT 0
-#define BCHP_XPT_MEMDMA_MCPB_BAND_PAUSE_MAPPING_VECTOR_20_BAND_PAUSE_MAPPING_VECTOR_DEFAULT 0x00100000
-
-/***************************************************************************
- *BAND_PAUSE_MAPPING_VECTOR_21 - MCPB Band pause mapping vector for channel 21
- ***************************************************************************/
-/* XPT_MEMDMA_MCPB :: BAND_PAUSE_MAPPING_VECTOR_21 :: BAND_PAUSE_MAPPING_VECTOR [31:00] */
-#define BCHP_XPT_MEMDMA_MCPB_BAND_PAUSE_MAPPING_VECTOR_21_BAND_PAUSE_MAPPING_VECTOR_MASK 0xffffffff
-#define BCHP_XPT_MEMDMA_MCPB_BAND_PAUSE_MAPPING_VECTOR_21_BAND_PAUSE_MAPPING_VECTOR_SHIFT 0
-#define BCHP_XPT_MEMDMA_MCPB_BAND_PAUSE_MAPPING_VECTOR_21_BAND_PAUSE_MAPPING_VECTOR_DEFAULT 0x00200000
-
-/***************************************************************************
- *BAND_PAUSE_MAPPING_VECTOR_22 - MCPB Band pause mapping vector for channel 22
- ***************************************************************************/
-/* XPT_MEMDMA_MCPB :: BAND_PAUSE_MAPPING_VECTOR_22 :: BAND_PAUSE_MAPPING_VECTOR [31:00] */
-#define BCHP_XPT_MEMDMA_MCPB_BAND_PAUSE_MAPPING_VECTOR_22_BAND_PAUSE_MAPPING_VECTOR_MASK 0xffffffff
-#define BCHP_XPT_MEMDMA_MCPB_BAND_PAUSE_MAPPING_VECTOR_22_BAND_PAUSE_MAPPING_VECTOR_SHIFT 0
-#define BCHP_XPT_MEMDMA_MCPB_BAND_PAUSE_MAPPING_VECTOR_22_BAND_PAUSE_MAPPING_VECTOR_DEFAULT 0x00400000
-
-/***************************************************************************
- *BAND_PAUSE_MAPPING_VECTOR_23 - MCPB Band pause mapping vector for channel 23
- ***************************************************************************/
-/* XPT_MEMDMA_MCPB :: BAND_PAUSE_MAPPING_VECTOR_23 :: BAND_PAUSE_MAPPING_VECTOR [31:00] */
-#define BCHP_XPT_MEMDMA_MCPB_BAND_PAUSE_MAPPING_VECTOR_23_BAND_PAUSE_MAPPING_VECTOR_MASK 0xffffffff
-#define BCHP_XPT_MEMDMA_MCPB_BAND_PAUSE_MAPPING_VECTOR_23_BAND_PAUSE_MAPPING_VECTOR_SHIFT 0
-#define BCHP_XPT_MEMDMA_MCPB_BAND_PAUSE_MAPPING_VECTOR_23_BAND_PAUSE_MAPPING_VECTOR_DEFAULT 0x00800000
-
-/***************************************************************************
- *BAND_PAUSE_MAPPING_VECTOR_24 - MCPB Band pause mapping vector for channel 24
- ***************************************************************************/
-/* XPT_MEMDMA_MCPB :: BAND_PAUSE_MAPPING_VECTOR_24 :: BAND_PAUSE_MAPPING_VECTOR [31:00] */
-#define BCHP_XPT_MEMDMA_MCPB_BAND_PAUSE_MAPPING_VECTOR_24_BAND_PAUSE_MAPPING_VECTOR_MASK 0xffffffff
-#define BCHP_XPT_MEMDMA_MCPB_BAND_PAUSE_MAPPING_VECTOR_24_BAND_PAUSE_MAPPING_VECTOR_SHIFT 0
-#define BCHP_XPT_MEMDMA_MCPB_BAND_PAUSE_MAPPING_VECTOR_24_BAND_PAUSE_MAPPING_VECTOR_DEFAULT 0x01000000
-
-/***************************************************************************
- *BAND_PAUSE_MAPPING_VECTOR_25 - MCPB Band pause mapping vector for channel 25
- ***************************************************************************/
-/* XPT_MEMDMA_MCPB :: BAND_PAUSE_MAPPING_VECTOR_25 :: BAND_PAUSE_MAPPING_VECTOR [31:00] */
-#define BCHP_XPT_MEMDMA_MCPB_BAND_PAUSE_MAPPING_VECTOR_25_BAND_PAUSE_MAPPING_VECTOR_MASK 0xffffffff
-#define BCHP_XPT_MEMDMA_MCPB_BAND_PAUSE_MAPPING_VECTOR_25_BAND_PAUSE_MAPPING_VECTOR_SHIFT 0
-#define BCHP_XPT_MEMDMA_MCPB_BAND_PAUSE_MAPPING_VECTOR_25_BAND_PAUSE_MAPPING_VECTOR_DEFAULT 0x02000000
-
-/***************************************************************************
- *BAND_PAUSE_MAPPING_VECTOR_26 - MCPB Band pause mapping vector for channel 26
- ***************************************************************************/
-/* XPT_MEMDMA_MCPB :: BAND_PAUSE_MAPPING_VECTOR_26 :: BAND_PAUSE_MAPPING_VECTOR [31:00] */
-#define BCHP_XPT_MEMDMA_MCPB_BAND_PAUSE_MAPPING_VECTOR_26_BAND_PAUSE_MAPPING_VECTOR_MASK 0xffffffff
-#define BCHP_XPT_MEMDMA_MCPB_BAND_PAUSE_MAPPING_VECTOR_26_BAND_PAUSE_MAPPING_VECTOR_SHIFT 0
-#define BCHP_XPT_MEMDMA_MCPB_BAND_PAUSE_MAPPING_VECTOR_26_BAND_PAUSE_MAPPING_VECTOR_DEFAULT 0x04000000
-
-/***************************************************************************
- *BAND_PAUSE_MAPPING_VECTOR_27 - MCPB Band pause mapping vector for channel 27
- ***************************************************************************/
-/* XPT_MEMDMA_MCPB :: BAND_PAUSE_MAPPING_VECTOR_27 :: BAND_PAUSE_MAPPING_VECTOR [31:00] */
-#define BCHP_XPT_MEMDMA_MCPB_BAND_PAUSE_MAPPING_VECTOR_27_BAND_PAUSE_MAPPING_VECTOR_MASK 0xffffffff
-#define BCHP_XPT_MEMDMA_MCPB_BAND_PAUSE_MAPPING_VECTOR_27_BAND_PAUSE_MAPPING_VECTOR_SHIFT 0
-#define BCHP_XPT_MEMDMA_MCPB_BAND_PAUSE_MAPPING_VECTOR_27_BAND_PAUSE_MAPPING_VECTOR_DEFAULT 0x08000000
-
-/***************************************************************************
- *BAND_PAUSE_MAPPING_VECTOR_28 - MCPB Band pause mapping vector for channel 28
- ***************************************************************************/
-/* XPT_MEMDMA_MCPB :: BAND_PAUSE_MAPPING_VECTOR_28 :: BAND_PAUSE_MAPPING_VECTOR [31:00] */
-#define BCHP_XPT_MEMDMA_MCPB_BAND_PAUSE_MAPPING_VECTOR_28_BAND_PAUSE_MAPPING_VECTOR_MASK 0xffffffff
-#define BCHP_XPT_MEMDMA_MCPB_BAND_PAUSE_MAPPING_VECTOR_28_BAND_PAUSE_MAPPING_VECTOR_SHIFT 0
-#define BCHP_XPT_MEMDMA_MCPB_BAND_PAUSE_MAPPING_VECTOR_28_BAND_PAUSE_MAPPING_VECTOR_DEFAULT 0x10000000
-
-/***************************************************************************
- *BAND_PAUSE_MAPPING_VECTOR_29 - MCPB Band pause mapping vector for channel 29
- ***************************************************************************/
-/* XPT_MEMDMA_MCPB :: BAND_PAUSE_MAPPING_VECTOR_29 :: BAND_PAUSE_MAPPING_VECTOR [31:00] */
-#define BCHP_XPT_MEMDMA_MCPB_BAND_PAUSE_MAPPING_VECTOR_29_BAND_PAUSE_MAPPING_VECTOR_MASK 0xffffffff
-#define BCHP_XPT_MEMDMA_MCPB_BAND_PAUSE_MAPPING_VECTOR_29_BAND_PAUSE_MAPPING_VECTOR_SHIFT 0
-#define BCHP_XPT_MEMDMA_MCPB_BAND_PAUSE_MAPPING_VECTOR_29_BAND_PAUSE_MAPPING_VECTOR_DEFAULT 0x20000000
-
-/***************************************************************************
- *BAND_PAUSE_MAPPING_VECTOR_30 - MCPB Band pause mapping vector for channel 30
- ***************************************************************************/
-/* XPT_MEMDMA_MCPB :: BAND_PAUSE_MAPPING_VECTOR_30 :: BAND_PAUSE_MAPPING_VECTOR [31:00] */
-#define BCHP_XPT_MEMDMA_MCPB_BAND_PAUSE_MAPPING_VECTOR_30_BAND_PAUSE_MAPPING_VECTOR_MASK 0xffffffff
-#define BCHP_XPT_MEMDMA_MCPB_BAND_PAUSE_MAPPING_VECTOR_30_BAND_PAUSE_MAPPING_VECTOR_SHIFT 0
-#define BCHP_XPT_MEMDMA_MCPB_BAND_PAUSE_MAPPING_VECTOR_30_BAND_PAUSE_MAPPING_VECTOR_DEFAULT 0x40000000
-
-/***************************************************************************
- *BAND_PAUSE_MAPPING_VECTOR_31 - MCPB Band pause mapping vector for channel 31
- ***************************************************************************/
-/* XPT_MEMDMA_MCPB :: BAND_PAUSE_MAPPING_VECTOR_31 :: BAND_PAUSE_MAPPING_VECTOR [31:00] */
-#define BCHP_XPT_MEMDMA_MCPB_BAND_PAUSE_MAPPING_VECTOR_31_BAND_PAUSE_MAPPING_VECTOR_MASK 0xffffffff
-#define BCHP_XPT_MEMDMA_MCPB_BAND_PAUSE_MAPPING_VECTOR_31_BAND_PAUSE_MAPPING_VECTOR_SHIFT 0
-#define BCHP_XPT_MEMDMA_MCPB_BAND_PAUSE_MAPPING_VECTOR_31_BAND_PAUSE_MAPPING_VECTOR_DEFAULT 0x80000000
-
-/***************************************************************************
- *SP_GLOBAL_CFG_REG0 - Channel independent Stream processor specific information
- ***************************************************************************/
-/* XPT_MEMDMA_MCPB :: SP_GLOBAL_CFG_REG0 :: reserved0 [31:25] */
-#define BCHP_XPT_MEMDMA_MCPB_SP_GLOBAL_CFG_REG0_reserved0_MASK 0xfe000000
-#define BCHP_XPT_MEMDMA_MCPB_SP_GLOBAL_CFG_REG0_reserved0_SHIFT 25
-
-/* XPT_MEMDMA_MCPB :: SP_GLOBAL_CFG_REG0 :: ASF_FIRST_BYTE_ECD [24:24] */
-#define BCHP_XPT_MEMDMA_MCPB_SP_GLOBAL_CFG_REG0_ASF_FIRST_BYTE_ECD_MASK 0x01000000
-#define BCHP_XPT_MEMDMA_MCPB_SP_GLOBAL_CFG_REG0_ASF_FIRST_BYTE_ECD_SHIFT 24
-#define BCHP_XPT_MEMDMA_MCPB_SP_GLOBAL_CFG_REG0_ASF_FIRST_BYTE_ECD_DEFAULT 0x00000000
-
-/* XPT_MEMDMA_MCPB :: SP_GLOBAL_CFG_REG0 :: ASF_SINGLE_SUB_PAYLOAD_PKT_TYPE [23:16] */
-#define BCHP_XPT_MEMDMA_MCPB_SP_GLOBAL_CFG_REG0_ASF_SINGLE_SUB_PAYLOAD_PKT_TYPE_MASK 0x00ff0000
-#define BCHP_XPT_MEMDMA_MCPB_SP_GLOBAL_CFG_REG0_ASF_SINGLE_SUB_PAYLOAD_PKT_TYPE_SHIFT 16
-#define BCHP_XPT_MEMDMA_MCPB_SP_GLOBAL_CFG_REG0_ASF_SINGLE_SUB_PAYLOAD_PKT_TYPE_DEFAULT 0x00000006
-
-/* XPT_MEMDMA_MCPB :: SP_GLOBAL_CFG_REG0 :: ASF_SUB_PAYLOAD_PKT_TYPE1 [15:08] */
-#define BCHP_XPT_MEMDMA_MCPB_SP_GLOBAL_CFG_REG0_ASF_SUB_PAYLOAD_PKT_TYPE1_MASK 0x0000ff00
-#define BCHP_XPT_MEMDMA_MCPB_SP_GLOBAL_CFG_REG0_ASF_SUB_PAYLOAD_PKT_TYPE1_SHIFT 8
-#define BCHP_XPT_MEMDMA_MCPB_SP_GLOBAL_CFG_REG0_ASF_SUB_PAYLOAD_PKT_TYPE1_DEFAULT 0x00000005
-
-/* XPT_MEMDMA_MCPB :: SP_GLOBAL_CFG_REG0 :: ASF_SUB_PAYLOAD_PKT_TYPE0 [07:00] */
-#define BCHP_XPT_MEMDMA_MCPB_SP_GLOBAL_CFG_REG0_ASF_SUB_PAYLOAD_PKT_TYPE0_MASK 0x000000ff
-#define BCHP_XPT_MEMDMA_MCPB_SP_GLOBAL_CFG_REG0_ASF_SUB_PAYLOAD_PKT_TYPE0_SHIFT 0
-#define BCHP_XPT_MEMDMA_MCPB_SP_GLOBAL_CFG_REG0_ASF_SUB_PAYLOAD_PKT_TYPE0_DEFAULT 0x00000004
-
-/***************************************************************************
- *SP_GLOBAL_CFG_REG1 - Channel independent Stream processor specific information
- ***************************************************************************/
-/* XPT_MEMDMA_MCPB :: SP_GLOBAL_CFG_REG1 :: reserved0 [31:24] */
-#define BCHP_XPT_MEMDMA_MCPB_SP_GLOBAL_CFG_REG1_reserved0_MASK 0xff000000
-#define BCHP_XPT_MEMDMA_MCPB_SP_GLOBAL_CFG_REG1_reserved0_SHIFT 24
-
-/* XPT_MEMDMA_MCPB :: SP_GLOBAL_CFG_REG1 :: ASF_SINGLE_PAYLOAD_PKT_TYPE [23:16] */
-#define BCHP_XPT_MEMDMA_MCPB_SP_GLOBAL_CFG_REG1_ASF_SINGLE_PAYLOAD_PKT_TYPE_MASK 0x00ff0000
-#define BCHP_XPT_MEMDMA_MCPB_SP_GLOBAL_CFG_REG1_ASF_SINGLE_PAYLOAD_PKT_TYPE_SHIFT 16
-#define BCHP_XPT_MEMDMA_MCPB_SP_GLOBAL_CFG_REG1_ASF_SINGLE_PAYLOAD_PKT_TYPE_DEFAULT 0x00000001
-
-/* XPT_MEMDMA_MCPB :: SP_GLOBAL_CFG_REG1 :: ASF_PAYLOAD_PKT_TYPE1 [15:08] */
-#define BCHP_XPT_MEMDMA_MCPB_SP_GLOBAL_CFG_REG1_ASF_PAYLOAD_PKT_TYPE1_MASK 0x0000ff00
-#define BCHP_XPT_MEMDMA_MCPB_SP_GLOBAL_CFG_REG1_ASF_PAYLOAD_PKT_TYPE1_SHIFT 8
-#define BCHP_XPT_MEMDMA_MCPB_SP_GLOBAL_CFG_REG1_ASF_PAYLOAD_PKT_TYPE1_DEFAULT 0x00000001
-
-/* XPT_MEMDMA_MCPB :: SP_GLOBAL_CFG_REG1 :: ASF_PAYLOAD_PKT_TYPE0 [07:00] */
-#define BCHP_XPT_MEMDMA_MCPB_SP_GLOBAL_CFG_REG1_ASF_PAYLOAD_PKT_TYPE0_MASK 0x000000ff
-#define BCHP_XPT_MEMDMA_MCPB_SP_GLOBAL_CFG_REG1_ASF_PAYLOAD_PKT_TYPE0_SHIFT 0
-#define BCHP_XPT_MEMDMA_MCPB_SP_GLOBAL_CFG_REG1_ASF_PAYLOAD_PKT_TYPE0_DEFAULT 0x00000000
-
-/***************************************************************************
- *TMEU_CHANNEL_BYPASS_SET_CLEAR - Set and clear for TMEU channel bypass bit
- ***************************************************************************/
-/* XPT_MEMDMA_MCPB :: TMEU_CHANNEL_BYPASS_SET_CLEAR :: reserved0 [31:09] */
-#define BCHP_XPT_MEMDMA_MCPB_TMEU_CHANNEL_BYPASS_SET_CLEAR_reserved0_MASK 0xfffffe00
-#define BCHP_XPT_MEMDMA_MCPB_TMEU_CHANNEL_BYPASS_SET_CLEAR_reserved0_SHIFT 9
-
-/* XPT_MEMDMA_MCPB :: TMEU_CHANNEL_BYPASS_SET_CLEAR :: SET_CLEAR [08:08] */
-#define BCHP_XPT_MEMDMA_MCPB_TMEU_CHANNEL_BYPASS_SET_CLEAR_SET_CLEAR_MASK 0x00000100
-#define BCHP_XPT_MEMDMA_MCPB_TMEU_CHANNEL_BYPASS_SET_CLEAR_SET_CLEAR_SHIFT 8
-#define BCHP_XPT_MEMDMA_MCPB_TMEU_CHANNEL_BYPASS_SET_CLEAR_SET_CLEAR_DEFAULT 0x00000000
-
-/* XPT_MEMDMA_MCPB :: TMEU_CHANNEL_BYPASS_SET_CLEAR :: MCPB_CHANNEL_NUM [07:00] */
-#define BCHP_XPT_MEMDMA_MCPB_TMEU_CHANNEL_BYPASS_SET_CLEAR_MCPB_CHANNEL_NUM_MASK 0x000000ff
-#define BCHP_XPT_MEMDMA_MCPB_TMEU_CHANNEL_BYPASS_SET_CLEAR_MCPB_CHANNEL_NUM_SHIFT 0
-#define BCHP_XPT_MEMDMA_MCPB_TMEU_CHANNEL_BYPASS_SET_CLEAR_MCPB_CHANNEL_NUM_DEFAULT 0x00000000
-
-/***************************************************************************
- *TMEU_CHANNEL_BYPASS_STATUS_0_31 - TMEU channel bypass status
- ***************************************************************************/
-/* XPT_MEMDMA_MCPB :: TMEU_CHANNEL_BYPASS_STATUS_0_31 :: BYPASS_STATUS [31:00] */
-#define BCHP_XPT_MEMDMA_MCPB_TMEU_CHANNEL_BYPASS_STATUS_0_31_BYPASS_STATUS_MASK 0xffffffff
-#define BCHP_XPT_MEMDMA_MCPB_TMEU_CHANNEL_BYPASS_STATUS_0_31_BYPASS_STATUS_SHIFT 0
-#define BCHP_XPT_MEMDMA_MCPB_TMEU_CHANNEL_BYPASS_STATUS_0_31_BYPASS_STATUS_DEFAULT 0x00000000
-
-/***************************************************************************
- *GPC0_CTRL - MCPB GPC0 Control information
- ***************************************************************************/
-/* XPT_MEMDMA_MCPB :: GPC0_CTRL :: FREE_RUN_OR_LOCKED_TIMEBASE [31:31] */
-#define BCHP_XPT_MEMDMA_MCPB_GPC0_CTRL_FREE_RUN_OR_LOCKED_TIMEBASE_MASK 0x80000000
-#define BCHP_XPT_MEMDMA_MCPB_GPC0_CTRL_FREE_RUN_OR_LOCKED_TIMEBASE_SHIFT 31
-#define BCHP_XPT_MEMDMA_MCPB_GPC0_CTRL_FREE_RUN_OR_LOCKED_TIMEBASE_DEFAULT 0x00000000
-
-/* XPT_MEMDMA_MCPB :: GPC0_CTRL :: TIMEBASE_SEL [30:26] */
-#define BCHP_XPT_MEMDMA_MCPB_GPC0_CTRL_TIMEBASE_SEL_MASK 0x7c000000
-#define BCHP_XPT_MEMDMA_MCPB_GPC0_CTRL_TIMEBASE_SEL_SHIFT 26
-#define BCHP_XPT_MEMDMA_MCPB_GPC0_CTRL_TIMEBASE_SEL_DEFAULT 0x00000000
-
-/* XPT_MEMDMA_MCPB :: GPC0_CTRL :: PACING_SPEED [25:23] */
-#define BCHP_XPT_MEMDMA_MCPB_GPC0_CTRL_PACING_SPEED_MASK 0x03800000
-#define BCHP_XPT_MEMDMA_MCPB_GPC0_CTRL_PACING_SPEED_SHIFT 23
-#define BCHP_XPT_MEMDMA_MCPB_GPC0_CTRL_PACING_SPEED_DEFAULT 0x00000000
-
-/* XPT_MEMDMA_MCPB :: GPC0_CTRL :: COUNTER_MODE [22:22] */
-#define BCHP_XPT_MEMDMA_MCPB_GPC0_CTRL_COUNTER_MODE_MASK 0x00400000
-#define BCHP_XPT_MEMDMA_MCPB_GPC0_CTRL_COUNTER_MODE_SHIFT 22
-#define BCHP_XPT_MEMDMA_MCPB_GPC0_CTRL_COUNTER_MODE_DEFAULT 0x00000000
-
-/* XPT_MEMDMA_MCPB :: GPC0_CTRL :: SKIP_REPEAT_MODE [21:21] */
-#define BCHP_XPT_MEMDMA_MCPB_GPC0_CTRL_SKIP_REPEAT_MODE_MASK 0x00200000
-#define BCHP_XPT_MEMDMA_MCPB_GPC0_CTRL_SKIP_REPEAT_MODE_SHIFT 21
-#define BCHP_XPT_MEMDMA_MCPB_GPC0_CTRL_SKIP_REPEAT_MODE_DEFAULT 0x00000000
-
-/* XPT_MEMDMA_MCPB :: GPC0_CTRL :: SKIP_REPEAT_EN [20:20] */
-#define BCHP_XPT_MEMDMA_MCPB_GPC0_CTRL_SKIP_REPEAT_EN_MASK 0x00100000
-#define BCHP_XPT_MEMDMA_MCPB_GPC0_CTRL_SKIP_REPEAT_EN_SHIFT 20
-#define BCHP_XPT_MEMDMA_MCPB_GPC0_CTRL_SKIP_REPEAT_EN_DEFAULT 0x00000000
-
-/* XPT_MEMDMA_MCPB :: GPC0_CTRL :: SKIP_REPEAT_COUNT [19:00] */
-#define BCHP_XPT_MEMDMA_MCPB_GPC0_CTRL_SKIP_REPEAT_COUNT_MASK 0x000fffff
-#define BCHP_XPT_MEMDMA_MCPB_GPC0_CTRL_SKIP_REPEAT_COUNT_SHIFT 0
-#define BCHP_XPT_MEMDMA_MCPB_GPC0_CTRL_SKIP_REPEAT_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *GPC0_CURR_COUNTER_VAL - MCPB GPC0 Current counter value
- ***************************************************************************/
-/* XPT_MEMDMA_MCPB :: GPC0_CURR_COUNTER_VAL :: COUNTER [31:00] */
-#define BCHP_XPT_MEMDMA_MCPB_GPC0_CURR_COUNTER_VAL_COUNTER_MASK 0xffffffff
-#define BCHP_XPT_MEMDMA_MCPB_GPC0_CURR_COUNTER_VAL_COUNTER_SHIFT 0
-#define BCHP_XPT_MEMDMA_MCPB_GPC0_CURR_COUNTER_VAL_COUNTER_DEFAULT 0x00000000
-
-/***************************************************************************
- *GPC0_PAUSE_0_31 - MCPB GPC0 Current pause value
- ***************************************************************************/
-/* XPT_MEMDMA_MCPB :: GPC0_PAUSE_0_31 :: GPC_PAUSE [31:00] */
-#define BCHP_XPT_MEMDMA_MCPB_GPC0_PAUSE_0_31_GPC_PAUSE_MASK 0xffffffff
-#define BCHP_XPT_MEMDMA_MCPB_GPC0_PAUSE_0_31_GPC_PAUSE_SHIFT 0
-#define BCHP_XPT_MEMDMA_MCPB_GPC0_PAUSE_0_31_GPC_PAUSE_DEFAULT 0x00000000
-
-/***************************************************************************
- *GPC1_CTRL - MCPB GPC1 Control information
- ***************************************************************************/
-/* XPT_MEMDMA_MCPB :: GPC1_CTRL :: FREE_RUN_OR_LOCKED_TIMEBASE [31:31] */
-#define BCHP_XPT_MEMDMA_MCPB_GPC1_CTRL_FREE_RUN_OR_LOCKED_TIMEBASE_MASK 0x80000000
-#define BCHP_XPT_MEMDMA_MCPB_GPC1_CTRL_FREE_RUN_OR_LOCKED_TIMEBASE_SHIFT 31
-#define BCHP_XPT_MEMDMA_MCPB_GPC1_CTRL_FREE_RUN_OR_LOCKED_TIMEBASE_DEFAULT 0x00000000
-
-/* XPT_MEMDMA_MCPB :: GPC1_CTRL :: TIMEBASE_SEL [30:26] */
-#define BCHP_XPT_MEMDMA_MCPB_GPC1_CTRL_TIMEBASE_SEL_MASK 0x7c000000
-#define BCHP_XPT_MEMDMA_MCPB_GPC1_CTRL_TIMEBASE_SEL_SHIFT 26
-#define BCHP_XPT_MEMDMA_MCPB_GPC1_CTRL_TIMEBASE_SEL_DEFAULT 0x00000000
-
-/* XPT_MEMDMA_MCPB :: GPC1_CTRL :: PACING_SPEED [25:23] */
-#define BCHP_XPT_MEMDMA_MCPB_GPC1_CTRL_PACING_SPEED_MASK 0x03800000
-#define BCHP_XPT_MEMDMA_MCPB_GPC1_CTRL_PACING_SPEED_SHIFT 23
-#define BCHP_XPT_MEMDMA_MCPB_GPC1_CTRL_PACING_SPEED_DEFAULT 0x00000000
-
-/* XPT_MEMDMA_MCPB :: GPC1_CTRL :: COUNTER_MODE [22:22] */
-#define BCHP_XPT_MEMDMA_MCPB_GPC1_CTRL_COUNTER_MODE_MASK 0x00400000
-#define BCHP_XPT_MEMDMA_MCPB_GPC1_CTRL_COUNTER_MODE_SHIFT 22
-#define BCHP_XPT_MEMDMA_MCPB_GPC1_CTRL_COUNTER_MODE_DEFAULT 0x00000000
-
-/* XPT_MEMDMA_MCPB :: GPC1_CTRL :: SKIP_REPEAT_MODE [21:21] */
-#define BCHP_XPT_MEMDMA_MCPB_GPC1_CTRL_SKIP_REPEAT_MODE_MASK 0x00200000
-#define BCHP_XPT_MEMDMA_MCPB_GPC1_CTRL_SKIP_REPEAT_MODE_SHIFT 21
-#define BCHP_XPT_MEMDMA_MCPB_GPC1_CTRL_SKIP_REPEAT_MODE_DEFAULT 0x00000000
-
-/* XPT_MEMDMA_MCPB :: GPC1_CTRL :: SKIP_REPEAT_EN [20:20] */
-#define BCHP_XPT_MEMDMA_MCPB_GPC1_CTRL_SKIP_REPEAT_EN_MASK 0x00100000
-#define BCHP_XPT_MEMDMA_MCPB_GPC1_CTRL_SKIP_REPEAT_EN_SHIFT 20
-#define BCHP_XPT_MEMDMA_MCPB_GPC1_CTRL_SKIP_REPEAT_EN_DEFAULT 0x00000000
-
-/* XPT_MEMDMA_MCPB :: GPC1_CTRL :: SKIP_REPEAT_COUNT [19:00] */
-#define BCHP_XPT_MEMDMA_MCPB_GPC1_CTRL_SKIP_REPEAT_COUNT_MASK 0x000fffff
-#define BCHP_XPT_MEMDMA_MCPB_GPC1_CTRL_SKIP_REPEAT_COUNT_SHIFT 0
-#define BCHP_XPT_MEMDMA_MCPB_GPC1_CTRL_SKIP_REPEAT_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *GPC1_CURR_COUNTER_VAL - MCPB GPC1 Current counter value
- ***************************************************************************/
-/* XPT_MEMDMA_MCPB :: GPC1_CURR_COUNTER_VAL :: COUNTER [31:00] */
-#define BCHP_XPT_MEMDMA_MCPB_GPC1_CURR_COUNTER_VAL_COUNTER_MASK 0xffffffff
-#define BCHP_XPT_MEMDMA_MCPB_GPC1_CURR_COUNTER_VAL_COUNTER_SHIFT 0
-#define BCHP_XPT_MEMDMA_MCPB_GPC1_CURR_COUNTER_VAL_COUNTER_DEFAULT 0x00000000
-
-/***************************************************************************
- *GPC1_PAUSE_0_31 - MCPB GPC1 Current pause value
- ***************************************************************************/
-/* XPT_MEMDMA_MCPB :: GPC1_PAUSE_0_31 :: GPC_PAUSE [31:00] */
-#define BCHP_XPT_MEMDMA_MCPB_GPC1_PAUSE_0_31_GPC_PAUSE_MASK 0xffffffff
-#define BCHP_XPT_MEMDMA_MCPB_GPC1_PAUSE_0_31_GPC_PAUSE_SHIFT 0
-#define BCHP_XPT_MEMDMA_MCPB_GPC1_PAUSE_0_31_GPC_PAUSE_DEFAULT 0x00000000
-
-/***************************************************************************
- *GPC2_CTRL - MCPB GPC2 Control information
- ***************************************************************************/
-/* XPT_MEMDMA_MCPB :: GPC2_CTRL :: FREE_RUN_OR_LOCKED_TIMEBASE [31:31] */
-#define BCHP_XPT_MEMDMA_MCPB_GPC2_CTRL_FREE_RUN_OR_LOCKED_TIMEBASE_MASK 0x80000000
-#define BCHP_XPT_MEMDMA_MCPB_GPC2_CTRL_FREE_RUN_OR_LOCKED_TIMEBASE_SHIFT 31
-#define BCHP_XPT_MEMDMA_MCPB_GPC2_CTRL_FREE_RUN_OR_LOCKED_TIMEBASE_DEFAULT 0x00000000
-
-/* XPT_MEMDMA_MCPB :: GPC2_CTRL :: TIMEBASE_SEL [30:26] */
-#define BCHP_XPT_MEMDMA_MCPB_GPC2_CTRL_TIMEBASE_SEL_MASK 0x7c000000
-#define BCHP_XPT_MEMDMA_MCPB_GPC2_CTRL_TIMEBASE_SEL_SHIFT 26
-#define BCHP_XPT_MEMDMA_MCPB_GPC2_CTRL_TIMEBASE_SEL_DEFAULT 0x00000000
-
-/* XPT_MEMDMA_MCPB :: GPC2_CTRL :: PACING_SPEED [25:23] */
-#define BCHP_XPT_MEMDMA_MCPB_GPC2_CTRL_PACING_SPEED_MASK 0x03800000
-#define BCHP_XPT_MEMDMA_MCPB_GPC2_CTRL_PACING_SPEED_SHIFT 23
-#define BCHP_XPT_MEMDMA_MCPB_GPC2_CTRL_PACING_SPEED_DEFAULT 0x00000000
-
-/* XPT_MEMDMA_MCPB :: GPC2_CTRL :: COUNTER_MODE [22:22] */
-#define BCHP_XPT_MEMDMA_MCPB_GPC2_CTRL_COUNTER_MODE_MASK 0x00400000
-#define BCHP_XPT_MEMDMA_MCPB_GPC2_CTRL_COUNTER_MODE_SHIFT 22
-#define BCHP_XPT_MEMDMA_MCPB_GPC2_CTRL_COUNTER_MODE_DEFAULT 0x00000000
-
-/* XPT_MEMDMA_MCPB :: GPC2_CTRL :: SKIP_REPEAT_MODE [21:21] */
-#define BCHP_XPT_MEMDMA_MCPB_GPC2_CTRL_SKIP_REPEAT_MODE_MASK 0x00200000
-#define BCHP_XPT_MEMDMA_MCPB_GPC2_CTRL_SKIP_REPEAT_MODE_SHIFT 21
-#define BCHP_XPT_MEMDMA_MCPB_GPC2_CTRL_SKIP_REPEAT_MODE_DEFAULT 0x00000000
-
-/* XPT_MEMDMA_MCPB :: GPC2_CTRL :: SKIP_REPEAT_EN [20:20] */
-#define BCHP_XPT_MEMDMA_MCPB_GPC2_CTRL_SKIP_REPEAT_EN_MASK 0x00100000
-#define BCHP_XPT_MEMDMA_MCPB_GPC2_CTRL_SKIP_REPEAT_EN_SHIFT 20
-#define BCHP_XPT_MEMDMA_MCPB_GPC2_CTRL_SKIP_REPEAT_EN_DEFAULT 0x00000000
-
-/* XPT_MEMDMA_MCPB :: GPC2_CTRL :: SKIP_REPEAT_COUNT [19:00] */
-#define BCHP_XPT_MEMDMA_MCPB_GPC2_CTRL_SKIP_REPEAT_COUNT_MASK 0x000fffff
-#define BCHP_XPT_MEMDMA_MCPB_GPC2_CTRL_SKIP_REPEAT_COUNT_SHIFT 0
-#define BCHP_XPT_MEMDMA_MCPB_GPC2_CTRL_SKIP_REPEAT_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *GPC2_CURR_COUNTER_VAL - MCPB GPC2 Current counter value
- ***************************************************************************/
-/* XPT_MEMDMA_MCPB :: GPC2_CURR_COUNTER_VAL :: COUNTER [31:00] */
-#define BCHP_XPT_MEMDMA_MCPB_GPC2_CURR_COUNTER_VAL_COUNTER_MASK 0xffffffff
-#define BCHP_XPT_MEMDMA_MCPB_GPC2_CURR_COUNTER_VAL_COUNTER_SHIFT 0
-#define BCHP_XPT_MEMDMA_MCPB_GPC2_CURR_COUNTER_VAL_COUNTER_DEFAULT 0x00000000
-
-/***************************************************************************
- *GPC2_PAUSE_0_31 - MCPB GPC2 Current pause value
- ***************************************************************************/
-/* XPT_MEMDMA_MCPB :: GPC2_PAUSE_0_31 :: GPC_PAUSE [31:00] */
-#define BCHP_XPT_MEMDMA_MCPB_GPC2_PAUSE_0_31_GPC_PAUSE_MASK 0xffffffff
-#define BCHP_XPT_MEMDMA_MCPB_GPC2_PAUSE_0_31_GPC_PAUSE_SHIFT 0
-#define BCHP_XPT_MEMDMA_MCPB_GPC2_PAUSE_0_31_GPC_PAUSE_DEFAULT 0x00000000
-
-/***************************************************************************
- *GPC3_CTRL - MCPB GPC3 Control information
- ***************************************************************************/
-/* XPT_MEMDMA_MCPB :: GPC3_CTRL :: FREE_RUN_OR_LOCKED_TIMEBASE [31:31] */
-#define BCHP_XPT_MEMDMA_MCPB_GPC3_CTRL_FREE_RUN_OR_LOCKED_TIMEBASE_MASK 0x80000000
-#define BCHP_XPT_MEMDMA_MCPB_GPC3_CTRL_FREE_RUN_OR_LOCKED_TIMEBASE_SHIFT 31
-#define BCHP_XPT_MEMDMA_MCPB_GPC3_CTRL_FREE_RUN_OR_LOCKED_TIMEBASE_DEFAULT 0x00000000
-
-/* XPT_MEMDMA_MCPB :: GPC3_CTRL :: TIMEBASE_SEL [30:26] */
-#define BCHP_XPT_MEMDMA_MCPB_GPC3_CTRL_TIMEBASE_SEL_MASK 0x7c000000
-#define BCHP_XPT_MEMDMA_MCPB_GPC3_CTRL_TIMEBASE_SEL_SHIFT 26
-#define BCHP_XPT_MEMDMA_MCPB_GPC3_CTRL_TIMEBASE_SEL_DEFAULT 0x00000000
-
-/* XPT_MEMDMA_MCPB :: GPC3_CTRL :: PACING_SPEED [25:23] */
-#define BCHP_XPT_MEMDMA_MCPB_GPC3_CTRL_PACING_SPEED_MASK 0x03800000
-#define BCHP_XPT_MEMDMA_MCPB_GPC3_CTRL_PACING_SPEED_SHIFT 23
-#define BCHP_XPT_MEMDMA_MCPB_GPC3_CTRL_PACING_SPEED_DEFAULT 0x00000000
-
-/* XPT_MEMDMA_MCPB :: GPC3_CTRL :: COUNTER_MODE [22:22] */
-#define BCHP_XPT_MEMDMA_MCPB_GPC3_CTRL_COUNTER_MODE_MASK 0x00400000
-#define BCHP_XPT_MEMDMA_MCPB_GPC3_CTRL_COUNTER_MODE_SHIFT 22
-#define BCHP_XPT_MEMDMA_MCPB_GPC3_CTRL_COUNTER_MODE_DEFAULT 0x00000000
-
-/* XPT_MEMDMA_MCPB :: GPC3_CTRL :: SKIP_REPEAT_MODE [21:21] */
-#define BCHP_XPT_MEMDMA_MCPB_GPC3_CTRL_SKIP_REPEAT_MODE_MASK 0x00200000
-#define BCHP_XPT_MEMDMA_MCPB_GPC3_CTRL_SKIP_REPEAT_MODE_SHIFT 21
-#define BCHP_XPT_MEMDMA_MCPB_GPC3_CTRL_SKIP_REPEAT_MODE_DEFAULT 0x00000000
-
-/* XPT_MEMDMA_MCPB :: GPC3_CTRL :: SKIP_REPEAT_EN [20:20] */
-#define BCHP_XPT_MEMDMA_MCPB_GPC3_CTRL_SKIP_REPEAT_EN_MASK 0x00100000
-#define BCHP_XPT_MEMDMA_MCPB_GPC3_CTRL_SKIP_REPEAT_EN_SHIFT 20
-#define BCHP_XPT_MEMDMA_MCPB_GPC3_CTRL_SKIP_REPEAT_EN_DEFAULT 0x00000000
-
-/* XPT_MEMDMA_MCPB :: GPC3_CTRL :: SKIP_REPEAT_COUNT [19:00] */
-#define BCHP_XPT_MEMDMA_MCPB_GPC3_CTRL_SKIP_REPEAT_COUNT_MASK 0x000fffff
-#define BCHP_XPT_MEMDMA_MCPB_GPC3_CTRL_SKIP_REPEAT_COUNT_SHIFT 0
-#define BCHP_XPT_MEMDMA_MCPB_GPC3_CTRL_SKIP_REPEAT_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *GPC3_CURR_COUNTER_VAL - MCPB GPC3 Current counter value
- ***************************************************************************/
-/* XPT_MEMDMA_MCPB :: GPC3_CURR_COUNTER_VAL :: COUNTER [31:00] */
-#define BCHP_XPT_MEMDMA_MCPB_GPC3_CURR_COUNTER_VAL_COUNTER_MASK 0xffffffff
-#define BCHP_XPT_MEMDMA_MCPB_GPC3_CURR_COUNTER_VAL_COUNTER_SHIFT 0
-#define BCHP_XPT_MEMDMA_MCPB_GPC3_CURR_COUNTER_VAL_COUNTER_DEFAULT 0x00000000
-
-/***************************************************************************
- *GPC3_PAUSE_0_31 - MCPB GPC3 Current pause value
- ***************************************************************************/
-/* XPT_MEMDMA_MCPB :: GPC3_PAUSE_0_31 :: GPC_PAUSE [31:00] */
-#define BCHP_XPT_MEMDMA_MCPB_GPC3_PAUSE_0_31_GPC_PAUSE_MASK 0xffffffff
-#define BCHP_XPT_MEMDMA_MCPB_GPC3_PAUSE_0_31_GPC_PAUSE_SHIFT 0
-#define BCHP_XPT_MEMDMA_MCPB_GPC3_PAUSE_0_31_GPC_PAUSE_DEFAULT 0x00000000
-
-/***************************************************************************
- *GPC4_CTRL - MCPB GPC4 Control information
- ***************************************************************************/
-/* XPT_MEMDMA_MCPB :: GPC4_CTRL :: FREE_RUN_OR_LOCKED_TIMEBASE [31:31] */
-#define BCHP_XPT_MEMDMA_MCPB_GPC4_CTRL_FREE_RUN_OR_LOCKED_TIMEBASE_MASK 0x80000000
-#define BCHP_XPT_MEMDMA_MCPB_GPC4_CTRL_FREE_RUN_OR_LOCKED_TIMEBASE_SHIFT 31
-#define BCHP_XPT_MEMDMA_MCPB_GPC4_CTRL_FREE_RUN_OR_LOCKED_TIMEBASE_DEFAULT 0x00000000
-
-/* XPT_MEMDMA_MCPB :: GPC4_CTRL :: TIMEBASE_SEL [30:26] */
-#define BCHP_XPT_MEMDMA_MCPB_GPC4_CTRL_TIMEBASE_SEL_MASK 0x7c000000
-#define BCHP_XPT_MEMDMA_MCPB_GPC4_CTRL_TIMEBASE_SEL_SHIFT 26
-#define BCHP_XPT_MEMDMA_MCPB_GPC4_CTRL_TIMEBASE_SEL_DEFAULT 0x00000000
-
-/* XPT_MEMDMA_MCPB :: GPC4_CTRL :: PACING_SPEED [25:23] */
-#define BCHP_XPT_MEMDMA_MCPB_GPC4_CTRL_PACING_SPEED_MASK 0x03800000
-#define BCHP_XPT_MEMDMA_MCPB_GPC4_CTRL_PACING_SPEED_SHIFT 23
-#define BCHP_XPT_MEMDMA_MCPB_GPC4_CTRL_PACING_SPEED_DEFAULT 0x00000000
-
-/* XPT_MEMDMA_MCPB :: GPC4_CTRL :: COUNTER_MODE [22:22] */
-#define BCHP_XPT_MEMDMA_MCPB_GPC4_CTRL_COUNTER_MODE_MASK 0x00400000
-#define BCHP_XPT_MEMDMA_MCPB_GPC4_CTRL_COUNTER_MODE_SHIFT 22
-#define BCHP_XPT_MEMDMA_MCPB_GPC4_CTRL_COUNTER_MODE_DEFAULT 0x00000000
-
-/* XPT_MEMDMA_MCPB :: GPC4_CTRL :: SKIP_REPEAT_MODE [21:21] */
-#define BCHP_XPT_MEMDMA_MCPB_GPC4_CTRL_SKIP_REPEAT_MODE_MASK 0x00200000
-#define BCHP_XPT_MEMDMA_MCPB_GPC4_CTRL_SKIP_REPEAT_MODE_SHIFT 21
-#define BCHP_XPT_MEMDMA_MCPB_GPC4_CTRL_SKIP_REPEAT_MODE_DEFAULT 0x00000000
-
-/* XPT_MEMDMA_MCPB :: GPC4_CTRL :: SKIP_REPEAT_EN [20:20] */
-#define BCHP_XPT_MEMDMA_MCPB_GPC4_CTRL_SKIP_REPEAT_EN_MASK 0x00100000
-#define BCHP_XPT_MEMDMA_MCPB_GPC4_CTRL_SKIP_REPEAT_EN_SHIFT 20
-#define BCHP_XPT_MEMDMA_MCPB_GPC4_CTRL_SKIP_REPEAT_EN_DEFAULT 0x00000000
-
-/* XPT_MEMDMA_MCPB :: GPC4_CTRL :: SKIP_REPEAT_COUNT [19:00] */
-#define BCHP_XPT_MEMDMA_MCPB_GPC4_CTRL_SKIP_REPEAT_COUNT_MASK 0x000fffff
-#define BCHP_XPT_MEMDMA_MCPB_GPC4_CTRL_SKIP_REPEAT_COUNT_SHIFT 0
-#define BCHP_XPT_MEMDMA_MCPB_GPC4_CTRL_SKIP_REPEAT_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *GPC4_CURR_COUNTER_VAL - MCPB GPC4 Current counter value
- ***************************************************************************/
-/* XPT_MEMDMA_MCPB :: GPC4_CURR_COUNTER_VAL :: COUNTER [31:00] */
-#define BCHP_XPT_MEMDMA_MCPB_GPC4_CURR_COUNTER_VAL_COUNTER_MASK 0xffffffff
-#define BCHP_XPT_MEMDMA_MCPB_GPC4_CURR_COUNTER_VAL_COUNTER_SHIFT 0
-#define BCHP_XPT_MEMDMA_MCPB_GPC4_CURR_COUNTER_VAL_COUNTER_DEFAULT 0x00000000
-
-/***************************************************************************
- *GPC4_PAUSE_0_31 - MCPB GPC4 Current pause value
- ***************************************************************************/
-/* XPT_MEMDMA_MCPB :: GPC4_PAUSE_0_31 :: GPC_PAUSE [31:00] */
-#define BCHP_XPT_MEMDMA_MCPB_GPC4_PAUSE_0_31_GPC_PAUSE_MASK 0xffffffff
-#define BCHP_XPT_MEMDMA_MCPB_GPC4_PAUSE_0_31_GPC_PAUSE_SHIFT 0
-#define BCHP_XPT_MEMDMA_MCPB_GPC4_PAUSE_0_31_GPC_PAUSE_DEFAULT 0x00000000
-
-/***************************************************************************
- *GPC5_CTRL - MCPB GPC5 Control information
- ***************************************************************************/
-/* XPT_MEMDMA_MCPB :: GPC5_CTRL :: FREE_RUN_OR_LOCKED_TIMEBASE [31:31] */
-#define BCHP_XPT_MEMDMA_MCPB_GPC5_CTRL_FREE_RUN_OR_LOCKED_TIMEBASE_MASK 0x80000000
-#define BCHP_XPT_MEMDMA_MCPB_GPC5_CTRL_FREE_RUN_OR_LOCKED_TIMEBASE_SHIFT 31
-#define BCHP_XPT_MEMDMA_MCPB_GPC5_CTRL_FREE_RUN_OR_LOCKED_TIMEBASE_DEFAULT 0x00000000
-
-/* XPT_MEMDMA_MCPB :: GPC5_CTRL :: TIMEBASE_SEL [30:26] */
-#define BCHP_XPT_MEMDMA_MCPB_GPC5_CTRL_TIMEBASE_SEL_MASK 0x7c000000
-#define BCHP_XPT_MEMDMA_MCPB_GPC5_CTRL_TIMEBASE_SEL_SHIFT 26
-#define BCHP_XPT_MEMDMA_MCPB_GPC5_CTRL_TIMEBASE_SEL_DEFAULT 0x00000000
-
-/* XPT_MEMDMA_MCPB :: GPC5_CTRL :: PACING_SPEED [25:23] */
-#define BCHP_XPT_MEMDMA_MCPB_GPC5_CTRL_PACING_SPEED_MASK 0x03800000
-#define BCHP_XPT_MEMDMA_MCPB_GPC5_CTRL_PACING_SPEED_SHIFT 23
-#define BCHP_XPT_MEMDMA_MCPB_GPC5_CTRL_PACING_SPEED_DEFAULT 0x00000000
-
-/* XPT_MEMDMA_MCPB :: GPC5_CTRL :: COUNTER_MODE [22:22] */
-#define BCHP_XPT_MEMDMA_MCPB_GPC5_CTRL_COUNTER_MODE_MASK 0x00400000
-#define BCHP_XPT_MEMDMA_MCPB_GPC5_CTRL_COUNTER_MODE_SHIFT 22
-#define BCHP_XPT_MEMDMA_MCPB_GPC5_CTRL_COUNTER_MODE_DEFAULT 0x00000000
-
-/* XPT_MEMDMA_MCPB :: GPC5_CTRL :: SKIP_REPEAT_MODE [21:21] */
-#define BCHP_XPT_MEMDMA_MCPB_GPC5_CTRL_SKIP_REPEAT_MODE_MASK 0x00200000
-#define BCHP_XPT_MEMDMA_MCPB_GPC5_CTRL_SKIP_REPEAT_MODE_SHIFT 21
-#define BCHP_XPT_MEMDMA_MCPB_GPC5_CTRL_SKIP_REPEAT_MODE_DEFAULT 0x00000000
-
-/* XPT_MEMDMA_MCPB :: GPC5_CTRL :: SKIP_REPEAT_EN [20:20] */
-#define BCHP_XPT_MEMDMA_MCPB_GPC5_CTRL_SKIP_REPEAT_EN_MASK 0x00100000
-#define BCHP_XPT_MEMDMA_MCPB_GPC5_CTRL_SKIP_REPEAT_EN_SHIFT 20
-#define BCHP_XPT_MEMDMA_MCPB_GPC5_CTRL_SKIP_REPEAT_EN_DEFAULT 0x00000000
-
-/* XPT_MEMDMA_MCPB :: GPC5_CTRL :: SKIP_REPEAT_COUNT [19:00] */
-#define BCHP_XPT_MEMDMA_MCPB_GPC5_CTRL_SKIP_REPEAT_COUNT_MASK 0x000fffff
-#define BCHP_XPT_MEMDMA_MCPB_GPC5_CTRL_SKIP_REPEAT_COUNT_SHIFT 0
-#define BCHP_XPT_MEMDMA_MCPB_GPC5_CTRL_SKIP_REPEAT_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *GPC5_CURR_COUNTER_VAL - MCPB GPC5 Current counter value
- ***************************************************************************/
-/* XPT_MEMDMA_MCPB :: GPC5_CURR_COUNTER_VAL :: COUNTER [31:00] */
-#define BCHP_XPT_MEMDMA_MCPB_GPC5_CURR_COUNTER_VAL_COUNTER_MASK 0xffffffff
-#define BCHP_XPT_MEMDMA_MCPB_GPC5_CURR_COUNTER_VAL_COUNTER_SHIFT 0
-#define BCHP_XPT_MEMDMA_MCPB_GPC5_CURR_COUNTER_VAL_COUNTER_DEFAULT 0x00000000
-
-/***************************************************************************
- *GPC5_PAUSE_0_31 - MCPB GPC5 Current pause value
- ***************************************************************************/
-/* XPT_MEMDMA_MCPB :: GPC5_PAUSE_0_31 :: GPC_PAUSE [31:00] */
-#define BCHP_XPT_MEMDMA_MCPB_GPC5_PAUSE_0_31_GPC_PAUSE_MASK 0xffffffff
-#define BCHP_XPT_MEMDMA_MCPB_GPC5_PAUSE_0_31_GPC_PAUSE_SHIFT 0
-#define BCHP_XPT_MEMDMA_MCPB_GPC5_PAUSE_0_31_GPC_PAUSE_DEFAULT 0x00000000
-
-/***************************************************************************
- *GPC6_CTRL - MCPB GPC6 Control information
- ***************************************************************************/
-/* XPT_MEMDMA_MCPB :: GPC6_CTRL :: FREE_RUN_OR_LOCKED_TIMEBASE [31:31] */
-#define BCHP_XPT_MEMDMA_MCPB_GPC6_CTRL_FREE_RUN_OR_LOCKED_TIMEBASE_MASK 0x80000000
-#define BCHP_XPT_MEMDMA_MCPB_GPC6_CTRL_FREE_RUN_OR_LOCKED_TIMEBASE_SHIFT 31
-#define BCHP_XPT_MEMDMA_MCPB_GPC6_CTRL_FREE_RUN_OR_LOCKED_TIMEBASE_DEFAULT 0x00000000
-
-/* XPT_MEMDMA_MCPB :: GPC6_CTRL :: TIMEBASE_SEL [30:26] */
-#define BCHP_XPT_MEMDMA_MCPB_GPC6_CTRL_TIMEBASE_SEL_MASK 0x7c000000
-#define BCHP_XPT_MEMDMA_MCPB_GPC6_CTRL_TIMEBASE_SEL_SHIFT 26
-#define BCHP_XPT_MEMDMA_MCPB_GPC6_CTRL_TIMEBASE_SEL_DEFAULT 0x00000000
-
-/* XPT_MEMDMA_MCPB :: GPC6_CTRL :: PACING_SPEED [25:23] */
-#define BCHP_XPT_MEMDMA_MCPB_GPC6_CTRL_PACING_SPEED_MASK 0x03800000
-#define BCHP_XPT_MEMDMA_MCPB_GPC6_CTRL_PACING_SPEED_SHIFT 23
-#define BCHP_XPT_MEMDMA_MCPB_GPC6_CTRL_PACING_SPEED_DEFAULT 0x00000000
-
-/* XPT_MEMDMA_MCPB :: GPC6_CTRL :: COUNTER_MODE [22:22] */
-#define BCHP_XPT_MEMDMA_MCPB_GPC6_CTRL_COUNTER_MODE_MASK 0x00400000
-#define BCHP_XPT_MEMDMA_MCPB_GPC6_CTRL_COUNTER_MODE_SHIFT 22
-#define BCHP_XPT_MEMDMA_MCPB_GPC6_CTRL_COUNTER_MODE_DEFAULT 0x00000000
-
-/* XPT_MEMDMA_MCPB :: GPC6_CTRL :: SKIP_REPEAT_MODE [21:21] */
-#define BCHP_XPT_MEMDMA_MCPB_GPC6_CTRL_SKIP_REPEAT_MODE_MASK 0x00200000
-#define BCHP_XPT_MEMDMA_MCPB_GPC6_CTRL_SKIP_REPEAT_MODE_SHIFT 21
-#define BCHP_XPT_MEMDMA_MCPB_GPC6_CTRL_SKIP_REPEAT_MODE_DEFAULT 0x00000000
-
-/* XPT_MEMDMA_MCPB :: GPC6_CTRL :: SKIP_REPEAT_EN [20:20] */
-#define BCHP_XPT_MEMDMA_MCPB_GPC6_CTRL_SKIP_REPEAT_EN_MASK 0x00100000
-#define BCHP_XPT_MEMDMA_MCPB_GPC6_CTRL_SKIP_REPEAT_EN_SHIFT 20
-#define BCHP_XPT_MEMDMA_MCPB_GPC6_CTRL_SKIP_REPEAT_EN_DEFAULT 0x00000000
-
-/* XPT_MEMDMA_MCPB :: GPC6_CTRL :: SKIP_REPEAT_COUNT [19:00] */
-#define BCHP_XPT_MEMDMA_MCPB_GPC6_CTRL_SKIP_REPEAT_COUNT_MASK 0x000fffff
-#define BCHP_XPT_MEMDMA_MCPB_GPC6_CTRL_SKIP_REPEAT_COUNT_SHIFT 0
-#define BCHP_XPT_MEMDMA_MCPB_GPC6_CTRL_SKIP_REPEAT_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *GPC6_CURR_COUNTER_VAL - MCPB GPC6 Current counter value
- ***************************************************************************/
-/* XPT_MEMDMA_MCPB :: GPC6_CURR_COUNTER_VAL :: COUNTER [31:00] */
-#define BCHP_XPT_MEMDMA_MCPB_GPC6_CURR_COUNTER_VAL_COUNTER_MASK 0xffffffff
-#define BCHP_XPT_MEMDMA_MCPB_GPC6_CURR_COUNTER_VAL_COUNTER_SHIFT 0
-#define BCHP_XPT_MEMDMA_MCPB_GPC6_CURR_COUNTER_VAL_COUNTER_DEFAULT 0x00000000
-
-/***************************************************************************
- *GPC6_PAUSE_0_31 - MCPB GPC6 Current pause value
- ***************************************************************************/
-/* XPT_MEMDMA_MCPB :: GPC6_PAUSE_0_31 :: GPC_PAUSE [31:00] */
-#define BCHP_XPT_MEMDMA_MCPB_GPC6_PAUSE_0_31_GPC_PAUSE_MASK 0xffffffff
-#define BCHP_XPT_MEMDMA_MCPB_GPC6_PAUSE_0_31_GPC_PAUSE_SHIFT 0
-#define BCHP_XPT_MEMDMA_MCPB_GPC6_PAUSE_0_31_GPC_PAUSE_DEFAULT 0x00000000
-
-/***************************************************************************
- *GPC7_CTRL - MCPB GPC7 Control information
- ***************************************************************************/
-/* XPT_MEMDMA_MCPB :: GPC7_CTRL :: FREE_RUN_OR_LOCKED_TIMEBASE [31:31] */
-#define BCHP_XPT_MEMDMA_MCPB_GPC7_CTRL_FREE_RUN_OR_LOCKED_TIMEBASE_MASK 0x80000000
-#define BCHP_XPT_MEMDMA_MCPB_GPC7_CTRL_FREE_RUN_OR_LOCKED_TIMEBASE_SHIFT 31
-#define BCHP_XPT_MEMDMA_MCPB_GPC7_CTRL_FREE_RUN_OR_LOCKED_TIMEBASE_DEFAULT 0x00000000
-
-/* XPT_MEMDMA_MCPB :: GPC7_CTRL :: TIMEBASE_SEL [30:26] */
-#define BCHP_XPT_MEMDMA_MCPB_GPC7_CTRL_TIMEBASE_SEL_MASK 0x7c000000
-#define BCHP_XPT_MEMDMA_MCPB_GPC7_CTRL_TIMEBASE_SEL_SHIFT 26
-#define BCHP_XPT_MEMDMA_MCPB_GPC7_CTRL_TIMEBASE_SEL_DEFAULT 0x00000000
-
-/* XPT_MEMDMA_MCPB :: GPC7_CTRL :: PACING_SPEED [25:23] */
-#define BCHP_XPT_MEMDMA_MCPB_GPC7_CTRL_PACING_SPEED_MASK 0x03800000
-#define BCHP_XPT_MEMDMA_MCPB_GPC7_CTRL_PACING_SPEED_SHIFT 23
-#define BCHP_XPT_MEMDMA_MCPB_GPC7_CTRL_PACING_SPEED_DEFAULT 0x00000000
-
-/* XPT_MEMDMA_MCPB :: GPC7_CTRL :: COUNTER_MODE [22:22] */
-#define BCHP_XPT_MEMDMA_MCPB_GPC7_CTRL_COUNTER_MODE_MASK 0x00400000
-#define BCHP_XPT_MEMDMA_MCPB_GPC7_CTRL_COUNTER_MODE_SHIFT 22
-#define BCHP_XPT_MEMDMA_MCPB_GPC7_CTRL_COUNTER_MODE_DEFAULT 0x00000000
-
-/* XPT_MEMDMA_MCPB :: GPC7_CTRL :: SKIP_REPEAT_MODE [21:21] */
-#define BCHP_XPT_MEMDMA_MCPB_GPC7_CTRL_SKIP_REPEAT_MODE_MASK 0x00200000
-#define BCHP_XPT_MEMDMA_MCPB_GPC7_CTRL_SKIP_REPEAT_MODE_SHIFT 21
-#define BCHP_XPT_MEMDMA_MCPB_GPC7_CTRL_SKIP_REPEAT_MODE_DEFAULT 0x00000000
-
-/* XPT_MEMDMA_MCPB :: GPC7_CTRL :: SKIP_REPEAT_EN [20:20] */
-#define BCHP_XPT_MEMDMA_MCPB_GPC7_CTRL_SKIP_REPEAT_EN_MASK 0x00100000
-#define BCHP_XPT_MEMDMA_MCPB_GPC7_CTRL_SKIP_REPEAT_EN_SHIFT 20
-#define BCHP_XPT_MEMDMA_MCPB_GPC7_CTRL_SKIP_REPEAT_EN_DEFAULT 0x00000000
-
-/* XPT_MEMDMA_MCPB :: GPC7_CTRL :: SKIP_REPEAT_COUNT [19:00] */
-#define BCHP_XPT_MEMDMA_MCPB_GPC7_CTRL_SKIP_REPEAT_COUNT_MASK 0x000fffff
-#define BCHP_XPT_MEMDMA_MCPB_GPC7_CTRL_SKIP_REPEAT_COUNT_SHIFT 0
-#define BCHP_XPT_MEMDMA_MCPB_GPC7_CTRL_SKIP_REPEAT_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *GPC7_CURR_COUNTER_VAL - MCPB GPC7 Current counter value
- ***************************************************************************/
-/* XPT_MEMDMA_MCPB :: GPC7_CURR_COUNTER_VAL :: COUNTER [31:00] */
-#define BCHP_XPT_MEMDMA_MCPB_GPC7_CURR_COUNTER_VAL_COUNTER_MASK 0xffffffff
-#define BCHP_XPT_MEMDMA_MCPB_GPC7_CURR_COUNTER_VAL_COUNTER_SHIFT 0
-#define BCHP_XPT_MEMDMA_MCPB_GPC7_CURR_COUNTER_VAL_COUNTER_DEFAULT 0x00000000
-
-/***************************************************************************
- *GPC7_PAUSE_0_31 - MCPB GPC7 Current pause value
- ***************************************************************************/
-/* XPT_MEMDMA_MCPB :: GPC7_PAUSE_0_31 :: GPC_PAUSE [31:00] */
-#define BCHP_XPT_MEMDMA_MCPB_GPC7_PAUSE_0_31_GPC_PAUSE_MASK 0xffffffff
-#define BCHP_XPT_MEMDMA_MCPB_GPC7_PAUSE_0_31_GPC_PAUSE_SHIFT 0
-#define BCHP_XPT_MEMDMA_MCPB_GPC7_PAUSE_0_31_GPC_PAUSE_DEFAULT 0x00000000
-
-/***************************************************************************
- *GPC8_CTRL - MCPB GPC8 Control information
- ***************************************************************************/
-/* XPT_MEMDMA_MCPB :: GPC8_CTRL :: FREE_RUN_OR_LOCKED_TIMEBASE [31:31] */
-#define BCHP_XPT_MEMDMA_MCPB_GPC8_CTRL_FREE_RUN_OR_LOCKED_TIMEBASE_MASK 0x80000000
-#define BCHP_XPT_MEMDMA_MCPB_GPC8_CTRL_FREE_RUN_OR_LOCKED_TIMEBASE_SHIFT 31
-#define BCHP_XPT_MEMDMA_MCPB_GPC8_CTRL_FREE_RUN_OR_LOCKED_TIMEBASE_DEFAULT 0x00000000
-
-/* XPT_MEMDMA_MCPB :: GPC8_CTRL :: TIMEBASE_SEL [30:26] */
-#define BCHP_XPT_MEMDMA_MCPB_GPC8_CTRL_TIMEBASE_SEL_MASK 0x7c000000
-#define BCHP_XPT_MEMDMA_MCPB_GPC8_CTRL_TIMEBASE_SEL_SHIFT 26
-#define BCHP_XPT_MEMDMA_MCPB_GPC8_CTRL_TIMEBASE_SEL_DEFAULT 0x00000000
-
-/* XPT_MEMDMA_MCPB :: GPC8_CTRL :: PACING_SPEED [25:23] */
-#define BCHP_XPT_MEMDMA_MCPB_GPC8_CTRL_PACING_SPEED_MASK 0x03800000
-#define BCHP_XPT_MEMDMA_MCPB_GPC8_CTRL_PACING_SPEED_SHIFT 23
-#define BCHP_XPT_MEMDMA_MCPB_GPC8_CTRL_PACING_SPEED_DEFAULT 0x00000000
-
-/* XPT_MEMDMA_MCPB :: GPC8_CTRL :: COUNTER_MODE [22:22] */
-#define BCHP_XPT_MEMDMA_MCPB_GPC8_CTRL_COUNTER_MODE_MASK 0x00400000
-#define BCHP_XPT_MEMDMA_MCPB_GPC8_CTRL_COUNTER_MODE_SHIFT 22
-#define BCHP_XPT_MEMDMA_MCPB_GPC8_CTRL_COUNTER_MODE_DEFAULT 0x00000000
-
-/* XPT_MEMDMA_MCPB :: GPC8_CTRL :: SKIP_REPEAT_MODE [21:21] */
-#define BCHP_XPT_MEMDMA_MCPB_GPC8_CTRL_SKIP_REPEAT_MODE_MASK 0x00200000
-#define BCHP_XPT_MEMDMA_MCPB_GPC8_CTRL_SKIP_REPEAT_MODE_SHIFT 21
-#define BCHP_XPT_MEMDMA_MCPB_GPC8_CTRL_SKIP_REPEAT_MODE_DEFAULT 0x00000000
-
-/* XPT_MEMDMA_MCPB :: GPC8_CTRL :: SKIP_REPEAT_EN [20:20] */
-#define BCHP_XPT_MEMDMA_MCPB_GPC8_CTRL_SKIP_REPEAT_EN_MASK 0x00100000
-#define BCHP_XPT_MEMDMA_MCPB_GPC8_CTRL_SKIP_REPEAT_EN_SHIFT 20
-#define BCHP_XPT_MEMDMA_MCPB_GPC8_CTRL_SKIP_REPEAT_EN_DEFAULT 0x00000000
-
-/* XPT_MEMDMA_MCPB :: GPC8_CTRL :: SKIP_REPEAT_COUNT [19:00] */
-#define BCHP_XPT_MEMDMA_MCPB_GPC8_CTRL_SKIP_REPEAT_COUNT_MASK 0x000fffff
-#define BCHP_XPT_MEMDMA_MCPB_GPC8_CTRL_SKIP_REPEAT_COUNT_SHIFT 0
-#define BCHP_XPT_MEMDMA_MCPB_GPC8_CTRL_SKIP_REPEAT_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *GPC8_CURR_COUNTER_VAL - MCPB GPC8 Current counter value
- ***************************************************************************/
-/* XPT_MEMDMA_MCPB :: GPC8_CURR_COUNTER_VAL :: COUNTER [31:00] */
-#define BCHP_XPT_MEMDMA_MCPB_GPC8_CURR_COUNTER_VAL_COUNTER_MASK 0xffffffff
-#define BCHP_XPT_MEMDMA_MCPB_GPC8_CURR_COUNTER_VAL_COUNTER_SHIFT 0
-#define BCHP_XPT_MEMDMA_MCPB_GPC8_CURR_COUNTER_VAL_COUNTER_DEFAULT 0x00000000
-
-/***************************************************************************
- *GPC8_PAUSE_0_31 - MCPB GPC8 Current pause value
- ***************************************************************************/
-/* XPT_MEMDMA_MCPB :: GPC8_PAUSE_0_31 :: GPC_PAUSE [31:00] */
-#define BCHP_XPT_MEMDMA_MCPB_GPC8_PAUSE_0_31_GPC_PAUSE_MASK 0xffffffff
-#define BCHP_XPT_MEMDMA_MCPB_GPC8_PAUSE_0_31_GPC_PAUSE_SHIFT 0
-#define BCHP_XPT_MEMDMA_MCPB_GPC8_PAUSE_0_31_GPC_PAUSE_DEFAULT 0x00000000
-
-/***************************************************************************
- *GPC9_CTRL - MCPB GPC9 Control information
- ***************************************************************************/
-/* XPT_MEMDMA_MCPB :: GPC9_CTRL :: FREE_RUN_OR_LOCKED_TIMEBASE [31:31] */
-#define BCHP_XPT_MEMDMA_MCPB_GPC9_CTRL_FREE_RUN_OR_LOCKED_TIMEBASE_MASK 0x80000000
-#define BCHP_XPT_MEMDMA_MCPB_GPC9_CTRL_FREE_RUN_OR_LOCKED_TIMEBASE_SHIFT 31
-#define BCHP_XPT_MEMDMA_MCPB_GPC9_CTRL_FREE_RUN_OR_LOCKED_TIMEBASE_DEFAULT 0x00000000
-
-/* XPT_MEMDMA_MCPB :: GPC9_CTRL :: TIMEBASE_SEL [30:26] */
-#define BCHP_XPT_MEMDMA_MCPB_GPC9_CTRL_TIMEBASE_SEL_MASK 0x7c000000
-#define BCHP_XPT_MEMDMA_MCPB_GPC9_CTRL_TIMEBASE_SEL_SHIFT 26
-#define BCHP_XPT_MEMDMA_MCPB_GPC9_CTRL_TIMEBASE_SEL_DEFAULT 0x00000000
-
-/* XPT_MEMDMA_MCPB :: GPC9_CTRL :: PACING_SPEED [25:23] */
-#define BCHP_XPT_MEMDMA_MCPB_GPC9_CTRL_PACING_SPEED_MASK 0x03800000
-#define BCHP_XPT_MEMDMA_MCPB_GPC9_CTRL_PACING_SPEED_SHIFT 23
-#define BCHP_XPT_MEMDMA_MCPB_GPC9_CTRL_PACING_SPEED_DEFAULT 0x00000000
-
-/* XPT_MEMDMA_MCPB :: GPC9_CTRL :: COUNTER_MODE [22:22] */
-#define BCHP_XPT_MEMDMA_MCPB_GPC9_CTRL_COUNTER_MODE_MASK 0x00400000
-#define BCHP_XPT_MEMDMA_MCPB_GPC9_CTRL_COUNTER_MODE_SHIFT 22
-#define BCHP_XPT_MEMDMA_MCPB_GPC9_CTRL_COUNTER_MODE_DEFAULT 0x00000000
-
-/* XPT_MEMDMA_MCPB :: GPC9_CTRL :: SKIP_REPEAT_MODE [21:21] */
-#define BCHP_XPT_MEMDMA_MCPB_GPC9_CTRL_SKIP_REPEAT_MODE_MASK 0x00200000
-#define BCHP_XPT_MEMDMA_MCPB_GPC9_CTRL_SKIP_REPEAT_MODE_SHIFT 21
-#define BCHP_XPT_MEMDMA_MCPB_GPC9_CTRL_SKIP_REPEAT_MODE_DEFAULT 0x00000000
-
-/* XPT_MEMDMA_MCPB :: GPC9_CTRL :: SKIP_REPEAT_EN [20:20] */
-#define BCHP_XPT_MEMDMA_MCPB_GPC9_CTRL_SKIP_REPEAT_EN_MASK 0x00100000
-#define BCHP_XPT_MEMDMA_MCPB_GPC9_CTRL_SKIP_REPEAT_EN_SHIFT 20
-#define BCHP_XPT_MEMDMA_MCPB_GPC9_CTRL_SKIP_REPEAT_EN_DEFAULT 0x00000000
-
-/* XPT_MEMDMA_MCPB :: GPC9_CTRL :: SKIP_REPEAT_COUNT [19:00] */
-#define BCHP_XPT_MEMDMA_MCPB_GPC9_CTRL_SKIP_REPEAT_COUNT_MASK 0x000fffff
-#define BCHP_XPT_MEMDMA_MCPB_GPC9_CTRL_SKIP_REPEAT_COUNT_SHIFT 0
-#define BCHP_XPT_MEMDMA_MCPB_GPC9_CTRL_SKIP_REPEAT_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *GPC9_CURR_COUNTER_VAL - MCPB GPC9 Current counter value
- ***************************************************************************/
-/* XPT_MEMDMA_MCPB :: GPC9_CURR_COUNTER_VAL :: COUNTER [31:00] */
-#define BCHP_XPT_MEMDMA_MCPB_GPC9_CURR_COUNTER_VAL_COUNTER_MASK 0xffffffff
-#define BCHP_XPT_MEMDMA_MCPB_GPC9_CURR_COUNTER_VAL_COUNTER_SHIFT 0
-#define BCHP_XPT_MEMDMA_MCPB_GPC9_CURR_COUNTER_VAL_COUNTER_DEFAULT 0x00000000
-
-/***************************************************************************
- *GPC9_PAUSE_0_31 - MCPB GPC9 Current pause value
- ***************************************************************************/
-/* XPT_MEMDMA_MCPB :: GPC9_PAUSE_0_31 :: GPC_PAUSE [31:00] */
-#define BCHP_XPT_MEMDMA_MCPB_GPC9_PAUSE_0_31_GPC_PAUSE_MASK 0xffffffff
-#define BCHP_XPT_MEMDMA_MCPB_GPC9_PAUSE_0_31_GPC_PAUSE_SHIFT 0
-#define BCHP_XPT_MEMDMA_MCPB_GPC9_PAUSE_0_31_GPC_PAUSE_DEFAULT 0x00000000
-
-/***************************************************************************
- *GPC10_CTRL - MCPB GPC10 Control information
- ***************************************************************************/
-/* XPT_MEMDMA_MCPB :: GPC10_CTRL :: FREE_RUN_OR_LOCKED_TIMEBASE [31:31] */
-#define BCHP_XPT_MEMDMA_MCPB_GPC10_CTRL_FREE_RUN_OR_LOCKED_TIMEBASE_MASK 0x80000000
-#define BCHP_XPT_MEMDMA_MCPB_GPC10_CTRL_FREE_RUN_OR_LOCKED_TIMEBASE_SHIFT 31
-#define BCHP_XPT_MEMDMA_MCPB_GPC10_CTRL_FREE_RUN_OR_LOCKED_TIMEBASE_DEFAULT 0x00000000
-
-/* XPT_MEMDMA_MCPB :: GPC10_CTRL :: TIMEBASE_SEL [30:26] */
-#define BCHP_XPT_MEMDMA_MCPB_GPC10_CTRL_TIMEBASE_SEL_MASK 0x7c000000
-#define BCHP_XPT_MEMDMA_MCPB_GPC10_CTRL_TIMEBASE_SEL_SHIFT 26
-#define BCHP_XPT_MEMDMA_MCPB_GPC10_CTRL_TIMEBASE_SEL_DEFAULT 0x00000000
-
-/* XPT_MEMDMA_MCPB :: GPC10_CTRL :: PACING_SPEED [25:23] */
-#define BCHP_XPT_MEMDMA_MCPB_GPC10_CTRL_PACING_SPEED_MASK 0x03800000
-#define BCHP_XPT_MEMDMA_MCPB_GPC10_CTRL_PACING_SPEED_SHIFT 23
-#define BCHP_XPT_MEMDMA_MCPB_GPC10_CTRL_PACING_SPEED_DEFAULT 0x00000000
-
-/* XPT_MEMDMA_MCPB :: GPC10_CTRL :: COUNTER_MODE [22:22] */
-#define BCHP_XPT_MEMDMA_MCPB_GPC10_CTRL_COUNTER_MODE_MASK 0x00400000
-#define BCHP_XPT_MEMDMA_MCPB_GPC10_CTRL_COUNTER_MODE_SHIFT 22
-#define BCHP_XPT_MEMDMA_MCPB_GPC10_CTRL_COUNTER_MODE_DEFAULT 0x00000000
-
-/* XPT_MEMDMA_MCPB :: GPC10_CTRL :: SKIP_REPEAT_MODE [21:21] */
-#define BCHP_XPT_MEMDMA_MCPB_GPC10_CTRL_SKIP_REPEAT_MODE_MASK 0x00200000
-#define BCHP_XPT_MEMDMA_MCPB_GPC10_CTRL_SKIP_REPEAT_MODE_SHIFT 21
-#define BCHP_XPT_MEMDMA_MCPB_GPC10_CTRL_SKIP_REPEAT_MODE_DEFAULT 0x00000000
-
-/* XPT_MEMDMA_MCPB :: GPC10_CTRL :: SKIP_REPEAT_EN [20:20] */
-#define BCHP_XPT_MEMDMA_MCPB_GPC10_CTRL_SKIP_REPEAT_EN_MASK 0x00100000
-#define BCHP_XPT_MEMDMA_MCPB_GPC10_CTRL_SKIP_REPEAT_EN_SHIFT 20
-#define BCHP_XPT_MEMDMA_MCPB_GPC10_CTRL_SKIP_REPEAT_EN_DEFAULT 0x00000000
-
-/* XPT_MEMDMA_MCPB :: GPC10_CTRL :: SKIP_REPEAT_COUNT [19:00] */
-#define BCHP_XPT_MEMDMA_MCPB_GPC10_CTRL_SKIP_REPEAT_COUNT_MASK 0x000fffff
-#define BCHP_XPT_MEMDMA_MCPB_GPC10_CTRL_SKIP_REPEAT_COUNT_SHIFT 0
-#define BCHP_XPT_MEMDMA_MCPB_GPC10_CTRL_SKIP_REPEAT_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *GPC10_CURR_COUNTER_VAL - MCPB GPC10 Current counter value
- ***************************************************************************/
-/* XPT_MEMDMA_MCPB :: GPC10_CURR_COUNTER_VAL :: COUNTER [31:00] */
-#define BCHP_XPT_MEMDMA_MCPB_GPC10_CURR_COUNTER_VAL_COUNTER_MASK 0xffffffff
-#define BCHP_XPT_MEMDMA_MCPB_GPC10_CURR_COUNTER_VAL_COUNTER_SHIFT 0
-#define BCHP_XPT_MEMDMA_MCPB_GPC10_CURR_COUNTER_VAL_COUNTER_DEFAULT 0x00000000
-
-/***************************************************************************
- *GPC10_PAUSE_0_31 - MCPB GPC10 Current pause value
- ***************************************************************************/
-/* XPT_MEMDMA_MCPB :: GPC10_PAUSE_0_31 :: GPC_PAUSE [31:00] */
-#define BCHP_XPT_MEMDMA_MCPB_GPC10_PAUSE_0_31_GPC_PAUSE_MASK 0xffffffff
-#define BCHP_XPT_MEMDMA_MCPB_GPC10_PAUSE_0_31_GPC_PAUSE_SHIFT 0
-#define BCHP_XPT_MEMDMA_MCPB_GPC10_PAUSE_0_31_GPC_PAUSE_DEFAULT 0x00000000
-
-/***************************************************************************
- *GPC11_CTRL - MCPB GPC11 Control information
- ***************************************************************************/
-/* XPT_MEMDMA_MCPB :: GPC11_CTRL :: FREE_RUN_OR_LOCKED_TIMEBASE [31:31] */
-#define BCHP_XPT_MEMDMA_MCPB_GPC11_CTRL_FREE_RUN_OR_LOCKED_TIMEBASE_MASK 0x80000000
-#define BCHP_XPT_MEMDMA_MCPB_GPC11_CTRL_FREE_RUN_OR_LOCKED_TIMEBASE_SHIFT 31
-#define BCHP_XPT_MEMDMA_MCPB_GPC11_CTRL_FREE_RUN_OR_LOCKED_TIMEBASE_DEFAULT 0x00000000
-
-/* XPT_MEMDMA_MCPB :: GPC11_CTRL :: TIMEBASE_SEL [30:26] */
-#define BCHP_XPT_MEMDMA_MCPB_GPC11_CTRL_TIMEBASE_SEL_MASK 0x7c000000
-#define BCHP_XPT_MEMDMA_MCPB_GPC11_CTRL_TIMEBASE_SEL_SHIFT 26
-#define BCHP_XPT_MEMDMA_MCPB_GPC11_CTRL_TIMEBASE_SEL_DEFAULT 0x00000000
-
-/* XPT_MEMDMA_MCPB :: GPC11_CTRL :: PACING_SPEED [25:23] */
-#define BCHP_XPT_MEMDMA_MCPB_GPC11_CTRL_PACING_SPEED_MASK 0x03800000
-#define BCHP_XPT_MEMDMA_MCPB_GPC11_CTRL_PACING_SPEED_SHIFT 23
-#define BCHP_XPT_MEMDMA_MCPB_GPC11_CTRL_PACING_SPEED_DEFAULT 0x00000000
-
-/* XPT_MEMDMA_MCPB :: GPC11_CTRL :: COUNTER_MODE [22:22] */
-#define BCHP_XPT_MEMDMA_MCPB_GPC11_CTRL_COUNTER_MODE_MASK 0x00400000
-#define BCHP_XPT_MEMDMA_MCPB_GPC11_CTRL_COUNTER_MODE_SHIFT 22
-#define BCHP_XPT_MEMDMA_MCPB_GPC11_CTRL_COUNTER_MODE_DEFAULT 0x00000000
-
-/* XPT_MEMDMA_MCPB :: GPC11_CTRL :: SKIP_REPEAT_MODE [21:21] */
-#define BCHP_XPT_MEMDMA_MCPB_GPC11_CTRL_SKIP_REPEAT_MODE_MASK 0x00200000
-#define BCHP_XPT_MEMDMA_MCPB_GPC11_CTRL_SKIP_REPEAT_MODE_SHIFT 21
-#define BCHP_XPT_MEMDMA_MCPB_GPC11_CTRL_SKIP_REPEAT_MODE_DEFAULT 0x00000000
-
-/* XPT_MEMDMA_MCPB :: GPC11_CTRL :: SKIP_REPEAT_EN [20:20] */
-#define BCHP_XPT_MEMDMA_MCPB_GPC11_CTRL_SKIP_REPEAT_EN_MASK 0x00100000
-#define BCHP_XPT_MEMDMA_MCPB_GPC11_CTRL_SKIP_REPEAT_EN_SHIFT 20
-#define BCHP_XPT_MEMDMA_MCPB_GPC11_CTRL_SKIP_REPEAT_EN_DEFAULT 0x00000000
-
-/* XPT_MEMDMA_MCPB :: GPC11_CTRL :: SKIP_REPEAT_COUNT [19:00] */
-#define BCHP_XPT_MEMDMA_MCPB_GPC11_CTRL_SKIP_REPEAT_COUNT_MASK 0x000fffff
-#define BCHP_XPT_MEMDMA_MCPB_GPC11_CTRL_SKIP_REPEAT_COUNT_SHIFT 0
-#define BCHP_XPT_MEMDMA_MCPB_GPC11_CTRL_SKIP_REPEAT_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *GPC11_CURR_COUNTER_VAL - MCPB GPC11 Current counter value
- ***************************************************************************/
-/* XPT_MEMDMA_MCPB :: GPC11_CURR_COUNTER_VAL :: COUNTER [31:00] */
-#define BCHP_XPT_MEMDMA_MCPB_GPC11_CURR_COUNTER_VAL_COUNTER_MASK 0xffffffff
-#define BCHP_XPT_MEMDMA_MCPB_GPC11_CURR_COUNTER_VAL_COUNTER_SHIFT 0
-#define BCHP_XPT_MEMDMA_MCPB_GPC11_CURR_COUNTER_VAL_COUNTER_DEFAULT 0x00000000
-
-/***************************************************************************
- *GPC11_PAUSE_0_31 - MCPB GPC11 Current pause value
- ***************************************************************************/
-/* XPT_MEMDMA_MCPB :: GPC11_PAUSE_0_31 :: GPC_PAUSE [31:00] */
-#define BCHP_XPT_MEMDMA_MCPB_GPC11_PAUSE_0_31_GPC_PAUSE_MASK 0xffffffff
-#define BCHP_XPT_MEMDMA_MCPB_GPC11_PAUSE_0_31_GPC_PAUSE_SHIFT 0
-#define BCHP_XPT_MEMDMA_MCPB_GPC11_PAUSE_0_31_GPC_PAUSE_DEFAULT 0x00000000
-
-/***************************************************************************
- *GPC12_CTRL - MCPB GPC12 Control information
- ***************************************************************************/
-/* XPT_MEMDMA_MCPB :: GPC12_CTRL :: FREE_RUN_OR_LOCKED_TIMEBASE [31:31] */
-#define BCHP_XPT_MEMDMA_MCPB_GPC12_CTRL_FREE_RUN_OR_LOCKED_TIMEBASE_MASK 0x80000000
-#define BCHP_XPT_MEMDMA_MCPB_GPC12_CTRL_FREE_RUN_OR_LOCKED_TIMEBASE_SHIFT 31
-#define BCHP_XPT_MEMDMA_MCPB_GPC12_CTRL_FREE_RUN_OR_LOCKED_TIMEBASE_DEFAULT 0x00000000
-
-/* XPT_MEMDMA_MCPB :: GPC12_CTRL :: TIMEBASE_SEL [30:26] */
-#define BCHP_XPT_MEMDMA_MCPB_GPC12_CTRL_TIMEBASE_SEL_MASK 0x7c000000
-#define BCHP_XPT_MEMDMA_MCPB_GPC12_CTRL_TIMEBASE_SEL_SHIFT 26
-#define BCHP_XPT_MEMDMA_MCPB_GPC12_CTRL_TIMEBASE_SEL_DEFAULT 0x00000000
-
-/* XPT_MEMDMA_MCPB :: GPC12_CTRL :: PACING_SPEED [25:23] */
-#define BCHP_XPT_MEMDMA_MCPB_GPC12_CTRL_PACING_SPEED_MASK 0x03800000
-#define BCHP_XPT_MEMDMA_MCPB_GPC12_CTRL_PACING_SPEED_SHIFT 23
-#define BCHP_XPT_MEMDMA_MCPB_GPC12_CTRL_PACING_SPEED_DEFAULT 0x00000000
-
-/* XPT_MEMDMA_MCPB :: GPC12_CTRL :: COUNTER_MODE [22:22] */
-#define BCHP_XPT_MEMDMA_MCPB_GPC12_CTRL_COUNTER_MODE_MASK 0x00400000
-#define BCHP_XPT_MEMDMA_MCPB_GPC12_CTRL_COUNTER_MODE_SHIFT 22
-#define BCHP_XPT_MEMDMA_MCPB_GPC12_CTRL_COUNTER_MODE_DEFAULT 0x00000000
-
-/* XPT_MEMDMA_MCPB :: GPC12_CTRL :: SKIP_REPEAT_MODE [21:21] */
-#define BCHP_XPT_MEMDMA_MCPB_GPC12_CTRL_SKIP_REPEAT_MODE_MASK 0x00200000
-#define BCHP_XPT_MEMDMA_MCPB_GPC12_CTRL_SKIP_REPEAT_MODE_SHIFT 21
-#define BCHP_XPT_MEMDMA_MCPB_GPC12_CTRL_SKIP_REPEAT_MODE_DEFAULT 0x00000000
-
-/* XPT_MEMDMA_MCPB :: GPC12_CTRL :: SKIP_REPEAT_EN [20:20] */
-#define BCHP_XPT_MEMDMA_MCPB_GPC12_CTRL_SKIP_REPEAT_EN_MASK 0x00100000
-#define BCHP_XPT_MEMDMA_MCPB_GPC12_CTRL_SKIP_REPEAT_EN_SHIFT 20
-#define BCHP_XPT_MEMDMA_MCPB_GPC12_CTRL_SKIP_REPEAT_EN_DEFAULT 0x00000000
-
-/* XPT_MEMDMA_MCPB :: GPC12_CTRL :: SKIP_REPEAT_COUNT [19:00] */
-#define BCHP_XPT_MEMDMA_MCPB_GPC12_CTRL_SKIP_REPEAT_COUNT_MASK 0x000fffff
-#define BCHP_XPT_MEMDMA_MCPB_GPC12_CTRL_SKIP_REPEAT_COUNT_SHIFT 0
-#define BCHP_XPT_MEMDMA_MCPB_GPC12_CTRL_SKIP_REPEAT_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *GPC12_CURR_COUNTER_VAL - MCPB GPC12 Current counter value
- ***************************************************************************/
-/* XPT_MEMDMA_MCPB :: GPC12_CURR_COUNTER_VAL :: COUNTER [31:00] */
-#define BCHP_XPT_MEMDMA_MCPB_GPC12_CURR_COUNTER_VAL_COUNTER_MASK 0xffffffff
-#define BCHP_XPT_MEMDMA_MCPB_GPC12_CURR_COUNTER_VAL_COUNTER_SHIFT 0
-#define BCHP_XPT_MEMDMA_MCPB_GPC12_CURR_COUNTER_VAL_COUNTER_DEFAULT 0x00000000
-
-/***************************************************************************
- *GPC12_PAUSE_0_31 - MCPB GPC12 Current pause value
- ***************************************************************************/
-/* XPT_MEMDMA_MCPB :: GPC12_PAUSE_0_31 :: GPC_PAUSE [31:00] */
-#define BCHP_XPT_MEMDMA_MCPB_GPC12_PAUSE_0_31_GPC_PAUSE_MASK 0xffffffff
-#define BCHP_XPT_MEMDMA_MCPB_GPC12_PAUSE_0_31_GPC_PAUSE_SHIFT 0
-#define BCHP_XPT_MEMDMA_MCPB_GPC12_PAUSE_0_31_GPC_PAUSE_DEFAULT 0x00000000
-
-/***************************************************************************
- *GPC13_CTRL - MCPB GPC13 Control information
- ***************************************************************************/
-/* XPT_MEMDMA_MCPB :: GPC13_CTRL :: FREE_RUN_OR_LOCKED_TIMEBASE [31:31] */
-#define BCHP_XPT_MEMDMA_MCPB_GPC13_CTRL_FREE_RUN_OR_LOCKED_TIMEBASE_MASK 0x80000000
-#define BCHP_XPT_MEMDMA_MCPB_GPC13_CTRL_FREE_RUN_OR_LOCKED_TIMEBASE_SHIFT 31
-#define BCHP_XPT_MEMDMA_MCPB_GPC13_CTRL_FREE_RUN_OR_LOCKED_TIMEBASE_DEFAULT 0x00000000
-
-/* XPT_MEMDMA_MCPB :: GPC13_CTRL :: TIMEBASE_SEL [30:26] */
-#define BCHP_XPT_MEMDMA_MCPB_GPC13_CTRL_TIMEBASE_SEL_MASK 0x7c000000
-#define BCHP_XPT_MEMDMA_MCPB_GPC13_CTRL_TIMEBASE_SEL_SHIFT 26
-#define BCHP_XPT_MEMDMA_MCPB_GPC13_CTRL_TIMEBASE_SEL_DEFAULT 0x00000000
-
-/* XPT_MEMDMA_MCPB :: GPC13_CTRL :: PACING_SPEED [25:23] */
-#define BCHP_XPT_MEMDMA_MCPB_GPC13_CTRL_PACING_SPEED_MASK 0x03800000
-#define BCHP_XPT_MEMDMA_MCPB_GPC13_CTRL_PACING_SPEED_SHIFT 23
-#define BCHP_XPT_MEMDMA_MCPB_GPC13_CTRL_PACING_SPEED_DEFAULT 0x00000000
-
-/* XPT_MEMDMA_MCPB :: GPC13_CTRL :: COUNTER_MODE [22:22] */
-#define BCHP_XPT_MEMDMA_MCPB_GPC13_CTRL_COUNTER_MODE_MASK 0x00400000
-#define BCHP_XPT_MEMDMA_MCPB_GPC13_CTRL_COUNTER_MODE_SHIFT 22
-#define BCHP_XPT_MEMDMA_MCPB_GPC13_CTRL_COUNTER_MODE_DEFAULT 0x00000000
-
-/* XPT_MEMDMA_MCPB :: GPC13_CTRL :: SKIP_REPEAT_MODE [21:21] */
-#define BCHP_XPT_MEMDMA_MCPB_GPC13_CTRL_SKIP_REPEAT_MODE_MASK 0x00200000
-#define BCHP_XPT_MEMDMA_MCPB_GPC13_CTRL_SKIP_REPEAT_MODE_SHIFT 21
-#define BCHP_XPT_MEMDMA_MCPB_GPC13_CTRL_SKIP_REPEAT_MODE_DEFAULT 0x00000000
-
-/* XPT_MEMDMA_MCPB :: GPC13_CTRL :: SKIP_REPEAT_EN [20:20] */
-#define BCHP_XPT_MEMDMA_MCPB_GPC13_CTRL_SKIP_REPEAT_EN_MASK 0x00100000
-#define BCHP_XPT_MEMDMA_MCPB_GPC13_CTRL_SKIP_REPEAT_EN_SHIFT 20
-#define BCHP_XPT_MEMDMA_MCPB_GPC13_CTRL_SKIP_REPEAT_EN_DEFAULT 0x00000000
-
-/* XPT_MEMDMA_MCPB :: GPC13_CTRL :: SKIP_REPEAT_COUNT [19:00] */
-#define BCHP_XPT_MEMDMA_MCPB_GPC13_CTRL_SKIP_REPEAT_COUNT_MASK 0x000fffff
-#define BCHP_XPT_MEMDMA_MCPB_GPC13_CTRL_SKIP_REPEAT_COUNT_SHIFT 0
-#define BCHP_XPT_MEMDMA_MCPB_GPC13_CTRL_SKIP_REPEAT_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *GPC13_CURR_COUNTER_VAL - MCPB GPC13 Current counter value
- ***************************************************************************/
-/* XPT_MEMDMA_MCPB :: GPC13_CURR_COUNTER_VAL :: COUNTER [31:00] */
-#define BCHP_XPT_MEMDMA_MCPB_GPC13_CURR_COUNTER_VAL_COUNTER_MASK 0xffffffff
-#define BCHP_XPT_MEMDMA_MCPB_GPC13_CURR_COUNTER_VAL_COUNTER_SHIFT 0
-#define BCHP_XPT_MEMDMA_MCPB_GPC13_CURR_COUNTER_VAL_COUNTER_DEFAULT 0x00000000
-
-/***************************************************************************
- *GPC13_PAUSE_0_31 - MCPB GPC13 Current pause value
- ***************************************************************************/
-/* XPT_MEMDMA_MCPB :: GPC13_PAUSE_0_31 :: GPC_PAUSE [31:00] */
-#define BCHP_XPT_MEMDMA_MCPB_GPC13_PAUSE_0_31_GPC_PAUSE_MASK 0xffffffff
-#define BCHP_XPT_MEMDMA_MCPB_GPC13_PAUSE_0_31_GPC_PAUSE_SHIFT 0
-#define BCHP_XPT_MEMDMA_MCPB_GPC13_PAUSE_0_31_GPC_PAUSE_DEFAULT 0x00000000
-
-/***************************************************************************
- *GPC14_CTRL - MCPB GPC14 Control information
- ***************************************************************************/
-/* XPT_MEMDMA_MCPB :: GPC14_CTRL :: FREE_RUN_OR_LOCKED_TIMEBASE [31:31] */
-#define BCHP_XPT_MEMDMA_MCPB_GPC14_CTRL_FREE_RUN_OR_LOCKED_TIMEBASE_MASK 0x80000000
-#define BCHP_XPT_MEMDMA_MCPB_GPC14_CTRL_FREE_RUN_OR_LOCKED_TIMEBASE_SHIFT 31
-#define BCHP_XPT_MEMDMA_MCPB_GPC14_CTRL_FREE_RUN_OR_LOCKED_TIMEBASE_DEFAULT 0x00000000
-
-/* XPT_MEMDMA_MCPB :: GPC14_CTRL :: TIMEBASE_SEL [30:26] */
-#define BCHP_XPT_MEMDMA_MCPB_GPC14_CTRL_TIMEBASE_SEL_MASK 0x7c000000
-#define BCHP_XPT_MEMDMA_MCPB_GPC14_CTRL_TIMEBASE_SEL_SHIFT 26
-#define BCHP_XPT_MEMDMA_MCPB_GPC14_CTRL_TIMEBASE_SEL_DEFAULT 0x00000000
-
-/* XPT_MEMDMA_MCPB :: GPC14_CTRL :: PACING_SPEED [25:23] */
-#define BCHP_XPT_MEMDMA_MCPB_GPC14_CTRL_PACING_SPEED_MASK 0x03800000
-#define BCHP_XPT_MEMDMA_MCPB_GPC14_CTRL_PACING_SPEED_SHIFT 23
-#define BCHP_XPT_MEMDMA_MCPB_GPC14_CTRL_PACING_SPEED_DEFAULT 0x00000000
-
-/* XPT_MEMDMA_MCPB :: GPC14_CTRL :: COUNTER_MODE [22:22] */
-#define BCHP_XPT_MEMDMA_MCPB_GPC14_CTRL_COUNTER_MODE_MASK 0x00400000
-#define BCHP_XPT_MEMDMA_MCPB_GPC14_CTRL_COUNTER_MODE_SHIFT 22
-#define BCHP_XPT_MEMDMA_MCPB_GPC14_CTRL_COUNTER_MODE_DEFAULT 0x00000000
-
-/* XPT_MEMDMA_MCPB :: GPC14_CTRL :: SKIP_REPEAT_MODE [21:21] */
-#define BCHP_XPT_MEMDMA_MCPB_GPC14_CTRL_SKIP_REPEAT_MODE_MASK 0x00200000
-#define BCHP_XPT_MEMDMA_MCPB_GPC14_CTRL_SKIP_REPEAT_MODE_SHIFT 21
-#define BCHP_XPT_MEMDMA_MCPB_GPC14_CTRL_SKIP_REPEAT_MODE_DEFAULT 0x00000000
-
-/* XPT_MEMDMA_MCPB :: GPC14_CTRL :: SKIP_REPEAT_EN [20:20] */
-#define BCHP_XPT_MEMDMA_MCPB_GPC14_CTRL_SKIP_REPEAT_EN_MASK 0x00100000
-#define BCHP_XPT_MEMDMA_MCPB_GPC14_CTRL_SKIP_REPEAT_EN_SHIFT 20
-#define BCHP_XPT_MEMDMA_MCPB_GPC14_CTRL_SKIP_REPEAT_EN_DEFAULT 0x00000000
-
-/* XPT_MEMDMA_MCPB :: GPC14_CTRL :: SKIP_REPEAT_COUNT [19:00] */
-#define BCHP_XPT_MEMDMA_MCPB_GPC14_CTRL_SKIP_REPEAT_COUNT_MASK 0x000fffff
-#define BCHP_XPT_MEMDMA_MCPB_GPC14_CTRL_SKIP_REPEAT_COUNT_SHIFT 0
-#define BCHP_XPT_MEMDMA_MCPB_GPC14_CTRL_SKIP_REPEAT_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *GPC14_CURR_COUNTER_VAL - MCPB GPC14 Current counter value
- ***************************************************************************/
-/* XPT_MEMDMA_MCPB :: GPC14_CURR_COUNTER_VAL :: COUNTER [31:00] */
-#define BCHP_XPT_MEMDMA_MCPB_GPC14_CURR_COUNTER_VAL_COUNTER_MASK 0xffffffff
-#define BCHP_XPT_MEMDMA_MCPB_GPC14_CURR_COUNTER_VAL_COUNTER_SHIFT 0
-#define BCHP_XPT_MEMDMA_MCPB_GPC14_CURR_COUNTER_VAL_COUNTER_DEFAULT 0x00000000
-
-/***************************************************************************
- *GPC14_PAUSE_0_31 - MCPB GPC14 Current pause value
- ***************************************************************************/
-/* XPT_MEMDMA_MCPB :: GPC14_PAUSE_0_31 :: GPC_PAUSE [31:00] */
-#define BCHP_XPT_MEMDMA_MCPB_GPC14_PAUSE_0_31_GPC_PAUSE_MASK 0xffffffff
-#define BCHP_XPT_MEMDMA_MCPB_GPC14_PAUSE_0_31_GPC_PAUSE_SHIFT 0
-#define BCHP_XPT_MEMDMA_MCPB_GPC14_PAUSE_0_31_GPC_PAUSE_DEFAULT 0x00000000
-
-/***************************************************************************
- *GPC15_CTRL - MCPB GPC15 Control information
- ***************************************************************************/
-/* XPT_MEMDMA_MCPB :: GPC15_CTRL :: FREE_RUN_OR_LOCKED_TIMEBASE [31:31] */
-#define BCHP_XPT_MEMDMA_MCPB_GPC15_CTRL_FREE_RUN_OR_LOCKED_TIMEBASE_MASK 0x80000000
-#define BCHP_XPT_MEMDMA_MCPB_GPC15_CTRL_FREE_RUN_OR_LOCKED_TIMEBASE_SHIFT 31
-#define BCHP_XPT_MEMDMA_MCPB_GPC15_CTRL_FREE_RUN_OR_LOCKED_TIMEBASE_DEFAULT 0x00000000
-
-/* XPT_MEMDMA_MCPB :: GPC15_CTRL :: TIMEBASE_SEL [30:26] */
-#define BCHP_XPT_MEMDMA_MCPB_GPC15_CTRL_TIMEBASE_SEL_MASK 0x7c000000
-#define BCHP_XPT_MEMDMA_MCPB_GPC15_CTRL_TIMEBASE_SEL_SHIFT 26
-#define BCHP_XPT_MEMDMA_MCPB_GPC15_CTRL_TIMEBASE_SEL_DEFAULT 0x00000000
-
-/* XPT_MEMDMA_MCPB :: GPC15_CTRL :: PACING_SPEED [25:23] */
-#define BCHP_XPT_MEMDMA_MCPB_GPC15_CTRL_PACING_SPEED_MASK 0x03800000
-#define BCHP_XPT_MEMDMA_MCPB_GPC15_CTRL_PACING_SPEED_SHIFT 23
-#define BCHP_XPT_MEMDMA_MCPB_GPC15_CTRL_PACING_SPEED_DEFAULT 0x00000000
-
-/* XPT_MEMDMA_MCPB :: GPC15_CTRL :: COUNTER_MODE [22:22] */
-#define BCHP_XPT_MEMDMA_MCPB_GPC15_CTRL_COUNTER_MODE_MASK 0x00400000
-#define BCHP_XPT_MEMDMA_MCPB_GPC15_CTRL_COUNTER_MODE_SHIFT 22
-#define BCHP_XPT_MEMDMA_MCPB_GPC15_CTRL_COUNTER_MODE_DEFAULT 0x00000000
-
-/* XPT_MEMDMA_MCPB :: GPC15_CTRL :: SKIP_REPEAT_MODE [21:21] */
-#define BCHP_XPT_MEMDMA_MCPB_GPC15_CTRL_SKIP_REPEAT_MODE_MASK 0x00200000
-#define BCHP_XPT_MEMDMA_MCPB_GPC15_CTRL_SKIP_REPEAT_MODE_SHIFT 21
-#define BCHP_XPT_MEMDMA_MCPB_GPC15_CTRL_SKIP_REPEAT_MODE_DEFAULT 0x00000000
-
-/* XPT_MEMDMA_MCPB :: GPC15_CTRL :: SKIP_REPEAT_EN [20:20] */
-#define BCHP_XPT_MEMDMA_MCPB_GPC15_CTRL_SKIP_REPEAT_EN_MASK 0x00100000
-#define BCHP_XPT_MEMDMA_MCPB_GPC15_CTRL_SKIP_REPEAT_EN_SHIFT 20
-#define BCHP_XPT_MEMDMA_MCPB_GPC15_CTRL_SKIP_REPEAT_EN_DEFAULT 0x00000000
-
-/* XPT_MEMDMA_MCPB :: GPC15_CTRL :: SKIP_REPEAT_COUNT [19:00] */
-#define BCHP_XPT_MEMDMA_MCPB_GPC15_CTRL_SKIP_REPEAT_COUNT_MASK 0x000fffff
-#define BCHP_XPT_MEMDMA_MCPB_GPC15_CTRL_SKIP_REPEAT_COUNT_SHIFT 0
-#define BCHP_XPT_MEMDMA_MCPB_GPC15_CTRL_SKIP_REPEAT_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *GPC15_CURR_COUNTER_VAL - MCPB GPC15 Current counter value
- ***************************************************************************/
-/* XPT_MEMDMA_MCPB :: GPC15_CURR_COUNTER_VAL :: COUNTER [31:00] */
-#define BCHP_XPT_MEMDMA_MCPB_GPC15_CURR_COUNTER_VAL_COUNTER_MASK 0xffffffff
-#define BCHP_XPT_MEMDMA_MCPB_GPC15_CURR_COUNTER_VAL_COUNTER_SHIFT 0
-#define BCHP_XPT_MEMDMA_MCPB_GPC15_CURR_COUNTER_VAL_COUNTER_DEFAULT 0x00000000
-
-/***************************************************************************
- *GPC15_PAUSE_0_31 - MCPB GPC15 Current pause value
- ***************************************************************************/
-/* XPT_MEMDMA_MCPB :: GPC15_PAUSE_0_31 :: GPC_PAUSE [31:00] */
-#define BCHP_XPT_MEMDMA_MCPB_GPC15_PAUSE_0_31_GPC_PAUSE_MASK 0xffffffff
-#define BCHP_XPT_MEMDMA_MCPB_GPC15_PAUSE_0_31_GPC_PAUSE_SHIFT 0
-#define BCHP_XPT_MEMDMA_MCPB_GPC15_PAUSE_0_31_GPC_PAUSE_DEFAULT 0x00000000
-
-/***************************************************************************
- *GPC16_CTRL - MCPB GPC16 Control information
- ***************************************************************************/
-/* XPT_MEMDMA_MCPB :: GPC16_CTRL :: FREE_RUN_OR_LOCKED_TIMEBASE [31:31] */
-#define BCHP_XPT_MEMDMA_MCPB_GPC16_CTRL_FREE_RUN_OR_LOCKED_TIMEBASE_MASK 0x80000000
-#define BCHP_XPT_MEMDMA_MCPB_GPC16_CTRL_FREE_RUN_OR_LOCKED_TIMEBASE_SHIFT 31
-#define BCHP_XPT_MEMDMA_MCPB_GPC16_CTRL_FREE_RUN_OR_LOCKED_TIMEBASE_DEFAULT 0x00000000
-
-/* XPT_MEMDMA_MCPB :: GPC16_CTRL :: TIMEBASE_SEL [30:26] */
-#define BCHP_XPT_MEMDMA_MCPB_GPC16_CTRL_TIMEBASE_SEL_MASK 0x7c000000
-#define BCHP_XPT_MEMDMA_MCPB_GPC16_CTRL_TIMEBASE_SEL_SHIFT 26
-#define BCHP_XPT_MEMDMA_MCPB_GPC16_CTRL_TIMEBASE_SEL_DEFAULT 0x00000000
-
-/* XPT_MEMDMA_MCPB :: GPC16_CTRL :: PACING_SPEED [25:23] */
-#define BCHP_XPT_MEMDMA_MCPB_GPC16_CTRL_PACING_SPEED_MASK 0x03800000
-#define BCHP_XPT_MEMDMA_MCPB_GPC16_CTRL_PACING_SPEED_SHIFT 23
-#define BCHP_XPT_MEMDMA_MCPB_GPC16_CTRL_PACING_SPEED_DEFAULT 0x00000000
-
-/* XPT_MEMDMA_MCPB :: GPC16_CTRL :: COUNTER_MODE [22:22] */
-#define BCHP_XPT_MEMDMA_MCPB_GPC16_CTRL_COUNTER_MODE_MASK 0x00400000
-#define BCHP_XPT_MEMDMA_MCPB_GPC16_CTRL_COUNTER_MODE_SHIFT 22
-#define BCHP_XPT_MEMDMA_MCPB_GPC16_CTRL_COUNTER_MODE_DEFAULT 0x00000000
-
-/* XPT_MEMDMA_MCPB :: GPC16_CTRL :: SKIP_REPEAT_MODE [21:21] */
-#define BCHP_XPT_MEMDMA_MCPB_GPC16_CTRL_SKIP_REPEAT_MODE_MASK 0x00200000
-#define BCHP_XPT_MEMDMA_MCPB_GPC16_CTRL_SKIP_REPEAT_MODE_SHIFT 21
-#define BCHP_XPT_MEMDMA_MCPB_GPC16_CTRL_SKIP_REPEAT_MODE_DEFAULT 0x00000000
-
-/* XPT_MEMDMA_MCPB :: GPC16_CTRL :: SKIP_REPEAT_EN [20:20] */
-#define BCHP_XPT_MEMDMA_MCPB_GPC16_CTRL_SKIP_REPEAT_EN_MASK 0x00100000
-#define BCHP_XPT_MEMDMA_MCPB_GPC16_CTRL_SKIP_REPEAT_EN_SHIFT 20
-#define BCHP_XPT_MEMDMA_MCPB_GPC16_CTRL_SKIP_REPEAT_EN_DEFAULT 0x00000000
-
-/* XPT_MEMDMA_MCPB :: GPC16_CTRL :: SKIP_REPEAT_COUNT [19:00] */
-#define BCHP_XPT_MEMDMA_MCPB_GPC16_CTRL_SKIP_REPEAT_COUNT_MASK 0x000fffff
-#define BCHP_XPT_MEMDMA_MCPB_GPC16_CTRL_SKIP_REPEAT_COUNT_SHIFT 0
-#define BCHP_XPT_MEMDMA_MCPB_GPC16_CTRL_SKIP_REPEAT_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *GPC16_CURR_COUNTER_VAL - MCPB GPC16 Current counter value
- ***************************************************************************/
-/* XPT_MEMDMA_MCPB :: GPC16_CURR_COUNTER_VAL :: COUNTER [31:00] */
-#define BCHP_XPT_MEMDMA_MCPB_GPC16_CURR_COUNTER_VAL_COUNTER_MASK 0xffffffff
-#define BCHP_XPT_MEMDMA_MCPB_GPC16_CURR_COUNTER_VAL_COUNTER_SHIFT 0
-#define BCHP_XPT_MEMDMA_MCPB_GPC16_CURR_COUNTER_VAL_COUNTER_DEFAULT 0x00000000
-
-/***************************************************************************
- *GPC16_PAUSE_0_31 - MCPB GPC16 Current pause value
- ***************************************************************************/
-/* XPT_MEMDMA_MCPB :: GPC16_PAUSE_0_31 :: GPC_PAUSE [31:00] */
-#define BCHP_XPT_MEMDMA_MCPB_GPC16_PAUSE_0_31_GPC_PAUSE_MASK 0xffffffff
-#define BCHP_XPT_MEMDMA_MCPB_GPC16_PAUSE_0_31_GPC_PAUSE_SHIFT 0
-#define BCHP_XPT_MEMDMA_MCPB_GPC16_PAUSE_0_31_GPC_PAUSE_DEFAULT 0x00000000
-
-/***************************************************************************
- *GPC17_CTRL - MCPB GPC17 Control information
- ***************************************************************************/
-/* XPT_MEMDMA_MCPB :: GPC17_CTRL :: FREE_RUN_OR_LOCKED_TIMEBASE [31:31] */
-#define BCHP_XPT_MEMDMA_MCPB_GPC17_CTRL_FREE_RUN_OR_LOCKED_TIMEBASE_MASK 0x80000000
-#define BCHP_XPT_MEMDMA_MCPB_GPC17_CTRL_FREE_RUN_OR_LOCKED_TIMEBASE_SHIFT 31
-#define BCHP_XPT_MEMDMA_MCPB_GPC17_CTRL_FREE_RUN_OR_LOCKED_TIMEBASE_DEFAULT 0x00000000
-
-/* XPT_MEMDMA_MCPB :: GPC17_CTRL :: TIMEBASE_SEL [30:26] */
-#define BCHP_XPT_MEMDMA_MCPB_GPC17_CTRL_TIMEBASE_SEL_MASK 0x7c000000
-#define BCHP_XPT_MEMDMA_MCPB_GPC17_CTRL_TIMEBASE_SEL_SHIFT 26
-#define BCHP_XPT_MEMDMA_MCPB_GPC17_CTRL_TIMEBASE_SEL_DEFAULT 0x00000000
-
-/* XPT_MEMDMA_MCPB :: GPC17_CTRL :: PACING_SPEED [25:23] */
-#define BCHP_XPT_MEMDMA_MCPB_GPC17_CTRL_PACING_SPEED_MASK 0x03800000
-#define BCHP_XPT_MEMDMA_MCPB_GPC17_CTRL_PACING_SPEED_SHIFT 23
-#define BCHP_XPT_MEMDMA_MCPB_GPC17_CTRL_PACING_SPEED_DEFAULT 0x00000000
-
-/* XPT_MEMDMA_MCPB :: GPC17_CTRL :: COUNTER_MODE [22:22] */
-#define BCHP_XPT_MEMDMA_MCPB_GPC17_CTRL_COUNTER_MODE_MASK 0x00400000
-#define BCHP_XPT_MEMDMA_MCPB_GPC17_CTRL_COUNTER_MODE_SHIFT 22
-#define BCHP_XPT_MEMDMA_MCPB_GPC17_CTRL_COUNTER_MODE_DEFAULT 0x00000000
-
-/* XPT_MEMDMA_MCPB :: GPC17_CTRL :: SKIP_REPEAT_MODE [21:21] */
-#define BCHP_XPT_MEMDMA_MCPB_GPC17_CTRL_SKIP_REPEAT_MODE_MASK 0x00200000
-#define BCHP_XPT_MEMDMA_MCPB_GPC17_CTRL_SKIP_REPEAT_MODE_SHIFT 21
-#define BCHP_XPT_MEMDMA_MCPB_GPC17_CTRL_SKIP_REPEAT_MODE_DEFAULT 0x00000000
-
-/* XPT_MEMDMA_MCPB :: GPC17_CTRL :: SKIP_REPEAT_EN [20:20] */
-#define BCHP_XPT_MEMDMA_MCPB_GPC17_CTRL_SKIP_REPEAT_EN_MASK 0x00100000
-#define BCHP_XPT_MEMDMA_MCPB_GPC17_CTRL_SKIP_REPEAT_EN_SHIFT 20
-#define BCHP_XPT_MEMDMA_MCPB_GPC17_CTRL_SKIP_REPEAT_EN_DEFAULT 0x00000000
-
-/* XPT_MEMDMA_MCPB :: GPC17_CTRL :: SKIP_REPEAT_COUNT [19:00] */
-#define BCHP_XPT_MEMDMA_MCPB_GPC17_CTRL_SKIP_REPEAT_COUNT_MASK 0x000fffff
-#define BCHP_XPT_MEMDMA_MCPB_GPC17_CTRL_SKIP_REPEAT_COUNT_SHIFT 0
-#define BCHP_XPT_MEMDMA_MCPB_GPC17_CTRL_SKIP_REPEAT_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *GPC17_CURR_COUNTER_VAL - MCPB GPC17 Current counter value
- ***************************************************************************/
-/* XPT_MEMDMA_MCPB :: GPC17_CURR_COUNTER_VAL :: COUNTER [31:00] */
-#define BCHP_XPT_MEMDMA_MCPB_GPC17_CURR_COUNTER_VAL_COUNTER_MASK 0xffffffff
-#define BCHP_XPT_MEMDMA_MCPB_GPC17_CURR_COUNTER_VAL_COUNTER_SHIFT 0
-#define BCHP_XPT_MEMDMA_MCPB_GPC17_CURR_COUNTER_VAL_COUNTER_DEFAULT 0x00000000
-
-/***************************************************************************
- *GPC17_PAUSE_0_31 - MCPB GPC17 Current pause value
- ***************************************************************************/
-/* XPT_MEMDMA_MCPB :: GPC17_PAUSE_0_31 :: GPC_PAUSE [31:00] */
-#define BCHP_XPT_MEMDMA_MCPB_GPC17_PAUSE_0_31_GPC_PAUSE_MASK 0xffffffff
-#define BCHP_XPT_MEMDMA_MCPB_GPC17_PAUSE_0_31_GPC_PAUSE_SHIFT 0
-#define BCHP_XPT_MEMDMA_MCPB_GPC17_PAUSE_0_31_GPC_PAUSE_DEFAULT 0x00000000
-
-/***************************************************************************
- *GPC18_CTRL - MCPB GPC18 Control information
- ***************************************************************************/
-/* XPT_MEMDMA_MCPB :: GPC18_CTRL :: FREE_RUN_OR_LOCKED_TIMEBASE [31:31] */
-#define BCHP_XPT_MEMDMA_MCPB_GPC18_CTRL_FREE_RUN_OR_LOCKED_TIMEBASE_MASK 0x80000000
-#define BCHP_XPT_MEMDMA_MCPB_GPC18_CTRL_FREE_RUN_OR_LOCKED_TIMEBASE_SHIFT 31
-#define BCHP_XPT_MEMDMA_MCPB_GPC18_CTRL_FREE_RUN_OR_LOCKED_TIMEBASE_DEFAULT 0x00000000
-
-/* XPT_MEMDMA_MCPB :: GPC18_CTRL :: TIMEBASE_SEL [30:26] */
-#define BCHP_XPT_MEMDMA_MCPB_GPC18_CTRL_TIMEBASE_SEL_MASK 0x7c000000
-#define BCHP_XPT_MEMDMA_MCPB_GPC18_CTRL_TIMEBASE_SEL_SHIFT 26
-#define BCHP_XPT_MEMDMA_MCPB_GPC18_CTRL_TIMEBASE_SEL_DEFAULT 0x00000000
-
-/* XPT_MEMDMA_MCPB :: GPC18_CTRL :: PACING_SPEED [25:23] */
-#define BCHP_XPT_MEMDMA_MCPB_GPC18_CTRL_PACING_SPEED_MASK 0x03800000
-#define BCHP_XPT_MEMDMA_MCPB_GPC18_CTRL_PACING_SPEED_SHIFT 23
-#define BCHP_XPT_MEMDMA_MCPB_GPC18_CTRL_PACING_SPEED_DEFAULT 0x00000000
-
-/* XPT_MEMDMA_MCPB :: GPC18_CTRL :: COUNTER_MODE [22:22] */
-#define BCHP_XPT_MEMDMA_MCPB_GPC18_CTRL_COUNTER_MODE_MASK 0x00400000
-#define BCHP_XPT_MEMDMA_MCPB_GPC18_CTRL_COUNTER_MODE_SHIFT 22
-#define BCHP_XPT_MEMDMA_MCPB_GPC18_CTRL_COUNTER_MODE_DEFAULT 0x00000000
-
-/* XPT_MEMDMA_MCPB :: GPC18_CTRL :: SKIP_REPEAT_MODE [21:21] */
-#define BCHP_XPT_MEMDMA_MCPB_GPC18_CTRL_SKIP_REPEAT_MODE_MASK 0x00200000
-#define BCHP_XPT_MEMDMA_MCPB_GPC18_CTRL_SKIP_REPEAT_MODE_SHIFT 21
-#define BCHP_XPT_MEMDMA_MCPB_GPC18_CTRL_SKIP_REPEAT_MODE_DEFAULT 0x00000000
-
-/* XPT_MEMDMA_MCPB :: GPC18_CTRL :: SKIP_REPEAT_EN [20:20] */
-#define BCHP_XPT_MEMDMA_MCPB_GPC18_CTRL_SKIP_REPEAT_EN_MASK 0x00100000
-#define BCHP_XPT_MEMDMA_MCPB_GPC18_CTRL_SKIP_REPEAT_EN_SHIFT 20
-#define BCHP_XPT_MEMDMA_MCPB_GPC18_CTRL_SKIP_REPEAT_EN_DEFAULT 0x00000000
-
-/* XPT_MEMDMA_MCPB :: GPC18_CTRL :: SKIP_REPEAT_COUNT [19:00] */
-#define BCHP_XPT_MEMDMA_MCPB_GPC18_CTRL_SKIP_REPEAT_COUNT_MASK 0x000fffff
-#define BCHP_XPT_MEMDMA_MCPB_GPC18_CTRL_SKIP_REPEAT_COUNT_SHIFT 0
-#define BCHP_XPT_MEMDMA_MCPB_GPC18_CTRL_SKIP_REPEAT_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *GPC18_CURR_COUNTER_VAL - MCPB GPC18 Current counter value
- ***************************************************************************/
-/* XPT_MEMDMA_MCPB :: GPC18_CURR_COUNTER_VAL :: COUNTER [31:00] */
-#define BCHP_XPT_MEMDMA_MCPB_GPC18_CURR_COUNTER_VAL_COUNTER_MASK 0xffffffff
-#define BCHP_XPT_MEMDMA_MCPB_GPC18_CURR_COUNTER_VAL_COUNTER_SHIFT 0
-#define BCHP_XPT_MEMDMA_MCPB_GPC18_CURR_COUNTER_VAL_COUNTER_DEFAULT 0x00000000
-
-/***************************************************************************
- *GPC18_PAUSE_0_31 - MCPB GPC18 Current pause value
- ***************************************************************************/
-/* XPT_MEMDMA_MCPB :: GPC18_PAUSE_0_31 :: GPC_PAUSE [31:00] */
-#define BCHP_XPT_MEMDMA_MCPB_GPC18_PAUSE_0_31_GPC_PAUSE_MASK 0xffffffff
-#define BCHP_XPT_MEMDMA_MCPB_GPC18_PAUSE_0_31_GPC_PAUSE_SHIFT 0
-#define BCHP_XPT_MEMDMA_MCPB_GPC18_PAUSE_0_31_GPC_PAUSE_DEFAULT 0x00000000
-
-/***************************************************************************
- *GPC19_CTRL - MCPB GPC19 Control information
- ***************************************************************************/
-/* XPT_MEMDMA_MCPB :: GPC19_CTRL :: FREE_RUN_OR_LOCKED_TIMEBASE [31:31] */
-#define BCHP_XPT_MEMDMA_MCPB_GPC19_CTRL_FREE_RUN_OR_LOCKED_TIMEBASE_MASK 0x80000000
-#define BCHP_XPT_MEMDMA_MCPB_GPC19_CTRL_FREE_RUN_OR_LOCKED_TIMEBASE_SHIFT 31
-#define BCHP_XPT_MEMDMA_MCPB_GPC19_CTRL_FREE_RUN_OR_LOCKED_TIMEBASE_DEFAULT 0x00000000
-
-/* XPT_MEMDMA_MCPB :: GPC19_CTRL :: TIMEBASE_SEL [30:26] */
-#define BCHP_XPT_MEMDMA_MCPB_GPC19_CTRL_TIMEBASE_SEL_MASK 0x7c000000
-#define BCHP_XPT_MEMDMA_MCPB_GPC19_CTRL_TIMEBASE_SEL_SHIFT 26
-#define BCHP_XPT_MEMDMA_MCPB_GPC19_CTRL_TIMEBASE_SEL_DEFAULT 0x00000000
-
-/* XPT_MEMDMA_MCPB :: GPC19_CTRL :: PACING_SPEED [25:23] */
-#define BCHP_XPT_MEMDMA_MCPB_GPC19_CTRL_PACING_SPEED_MASK 0x03800000
-#define BCHP_XPT_MEMDMA_MCPB_GPC19_CTRL_PACING_SPEED_SHIFT 23
-#define BCHP_XPT_MEMDMA_MCPB_GPC19_CTRL_PACING_SPEED_DEFAULT 0x00000000
-
-/* XPT_MEMDMA_MCPB :: GPC19_CTRL :: COUNTER_MODE [22:22] */
-#define BCHP_XPT_MEMDMA_MCPB_GPC19_CTRL_COUNTER_MODE_MASK 0x00400000
-#define BCHP_XPT_MEMDMA_MCPB_GPC19_CTRL_COUNTER_MODE_SHIFT 22
-#define BCHP_XPT_MEMDMA_MCPB_GPC19_CTRL_COUNTER_MODE_DEFAULT 0x00000000
-
-/* XPT_MEMDMA_MCPB :: GPC19_CTRL :: SKIP_REPEAT_MODE [21:21] */
-#define BCHP_XPT_MEMDMA_MCPB_GPC19_CTRL_SKIP_REPEAT_MODE_MASK 0x00200000
-#define BCHP_XPT_MEMDMA_MCPB_GPC19_CTRL_SKIP_REPEAT_MODE_SHIFT 21
-#define BCHP_XPT_MEMDMA_MCPB_GPC19_CTRL_SKIP_REPEAT_MODE_DEFAULT 0x00000000
-
-/* XPT_MEMDMA_MCPB :: GPC19_CTRL :: SKIP_REPEAT_EN [20:20] */
-#define BCHP_XPT_MEMDMA_MCPB_GPC19_CTRL_SKIP_REPEAT_EN_MASK 0x00100000
-#define BCHP_XPT_MEMDMA_MCPB_GPC19_CTRL_SKIP_REPEAT_EN_SHIFT 20
-#define BCHP_XPT_MEMDMA_MCPB_GPC19_CTRL_SKIP_REPEAT_EN_DEFAULT 0x00000000
-
-/* XPT_MEMDMA_MCPB :: GPC19_CTRL :: SKIP_REPEAT_COUNT [19:00] */
-#define BCHP_XPT_MEMDMA_MCPB_GPC19_CTRL_SKIP_REPEAT_COUNT_MASK 0x000fffff
-#define BCHP_XPT_MEMDMA_MCPB_GPC19_CTRL_SKIP_REPEAT_COUNT_SHIFT 0
-#define BCHP_XPT_MEMDMA_MCPB_GPC19_CTRL_SKIP_REPEAT_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *GPC19_CURR_COUNTER_VAL - MCPB GPC19 Current counter value
- ***************************************************************************/
-/* XPT_MEMDMA_MCPB :: GPC19_CURR_COUNTER_VAL :: COUNTER [31:00] */
-#define BCHP_XPT_MEMDMA_MCPB_GPC19_CURR_COUNTER_VAL_COUNTER_MASK 0xffffffff
-#define BCHP_XPT_MEMDMA_MCPB_GPC19_CURR_COUNTER_VAL_COUNTER_SHIFT 0
-#define BCHP_XPT_MEMDMA_MCPB_GPC19_CURR_COUNTER_VAL_COUNTER_DEFAULT 0x00000000
-
-/***************************************************************************
- *GPC19_PAUSE_0_31 - MCPB GPC19 Current pause value
- ***************************************************************************/
-/* XPT_MEMDMA_MCPB :: GPC19_PAUSE_0_31 :: GPC_PAUSE [31:00] */
-#define BCHP_XPT_MEMDMA_MCPB_GPC19_PAUSE_0_31_GPC_PAUSE_MASK 0xffffffff
-#define BCHP_XPT_MEMDMA_MCPB_GPC19_PAUSE_0_31_GPC_PAUSE_SHIFT 0
-#define BCHP_XPT_MEMDMA_MCPB_GPC19_PAUSE_0_31_GPC_PAUSE_DEFAULT 0x00000000
-
-/***************************************************************************
- *GPC20_CTRL - MCPB GPC20 Control information
- ***************************************************************************/
-/* XPT_MEMDMA_MCPB :: GPC20_CTRL :: FREE_RUN_OR_LOCKED_TIMEBASE [31:31] */
-#define BCHP_XPT_MEMDMA_MCPB_GPC20_CTRL_FREE_RUN_OR_LOCKED_TIMEBASE_MASK 0x80000000
-#define BCHP_XPT_MEMDMA_MCPB_GPC20_CTRL_FREE_RUN_OR_LOCKED_TIMEBASE_SHIFT 31
-#define BCHP_XPT_MEMDMA_MCPB_GPC20_CTRL_FREE_RUN_OR_LOCKED_TIMEBASE_DEFAULT 0x00000000
-
-/* XPT_MEMDMA_MCPB :: GPC20_CTRL :: TIMEBASE_SEL [30:26] */
-#define BCHP_XPT_MEMDMA_MCPB_GPC20_CTRL_TIMEBASE_SEL_MASK 0x7c000000
-#define BCHP_XPT_MEMDMA_MCPB_GPC20_CTRL_TIMEBASE_SEL_SHIFT 26
-#define BCHP_XPT_MEMDMA_MCPB_GPC20_CTRL_TIMEBASE_SEL_DEFAULT 0x00000000
-
-/* XPT_MEMDMA_MCPB :: GPC20_CTRL :: PACING_SPEED [25:23] */
-#define BCHP_XPT_MEMDMA_MCPB_GPC20_CTRL_PACING_SPEED_MASK 0x03800000
-#define BCHP_XPT_MEMDMA_MCPB_GPC20_CTRL_PACING_SPEED_SHIFT 23
-#define BCHP_XPT_MEMDMA_MCPB_GPC20_CTRL_PACING_SPEED_DEFAULT 0x00000000
-
-/* XPT_MEMDMA_MCPB :: GPC20_CTRL :: COUNTER_MODE [22:22] */
-#define BCHP_XPT_MEMDMA_MCPB_GPC20_CTRL_COUNTER_MODE_MASK 0x00400000
-#define BCHP_XPT_MEMDMA_MCPB_GPC20_CTRL_COUNTER_MODE_SHIFT 22
-#define BCHP_XPT_MEMDMA_MCPB_GPC20_CTRL_COUNTER_MODE_DEFAULT 0x00000000
-
-/* XPT_MEMDMA_MCPB :: GPC20_CTRL :: SKIP_REPEAT_MODE [21:21] */
-#define BCHP_XPT_MEMDMA_MCPB_GPC20_CTRL_SKIP_REPEAT_MODE_MASK 0x00200000
-#define BCHP_XPT_MEMDMA_MCPB_GPC20_CTRL_SKIP_REPEAT_MODE_SHIFT 21
-#define BCHP_XPT_MEMDMA_MCPB_GPC20_CTRL_SKIP_REPEAT_MODE_DEFAULT 0x00000000
-
-/* XPT_MEMDMA_MCPB :: GPC20_CTRL :: SKIP_REPEAT_EN [20:20] */
-#define BCHP_XPT_MEMDMA_MCPB_GPC20_CTRL_SKIP_REPEAT_EN_MASK 0x00100000
-#define BCHP_XPT_MEMDMA_MCPB_GPC20_CTRL_SKIP_REPEAT_EN_SHIFT 20
-#define BCHP_XPT_MEMDMA_MCPB_GPC20_CTRL_SKIP_REPEAT_EN_DEFAULT 0x00000000
-
-/* XPT_MEMDMA_MCPB :: GPC20_CTRL :: SKIP_REPEAT_COUNT [19:00] */
-#define BCHP_XPT_MEMDMA_MCPB_GPC20_CTRL_SKIP_REPEAT_COUNT_MASK 0x000fffff
-#define BCHP_XPT_MEMDMA_MCPB_GPC20_CTRL_SKIP_REPEAT_COUNT_SHIFT 0
-#define BCHP_XPT_MEMDMA_MCPB_GPC20_CTRL_SKIP_REPEAT_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *GPC20_CURR_COUNTER_VAL - MCPB GPC20 Current counter value
- ***************************************************************************/
-/* XPT_MEMDMA_MCPB :: GPC20_CURR_COUNTER_VAL :: COUNTER [31:00] */
-#define BCHP_XPT_MEMDMA_MCPB_GPC20_CURR_COUNTER_VAL_COUNTER_MASK 0xffffffff
-#define BCHP_XPT_MEMDMA_MCPB_GPC20_CURR_COUNTER_VAL_COUNTER_SHIFT 0
-#define BCHP_XPT_MEMDMA_MCPB_GPC20_CURR_COUNTER_VAL_COUNTER_DEFAULT 0x00000000
-
-/***************************************************************************
- *GPC20_PAUSE_0_31 - MCPB GPC20 Current pause value
- ***************************************************************************/
-/* XPT_MEMDMA_MCPB :: GPC20_PAUSE_0_31 :: GPC_PAUSE [31:00] */
-#define BCHP_XPT_MEMDMA_MCPB_GPC20_PAUSE_0_31_GPC_PAUSE_MASK 0xffffffff
-#define BCHP_XPT_MEMDMA_MCPB_GPC20_PAUSE_0_31_GPC_PAUSE_SHIFT 0
-#define BCHP_XPT_MEMDMA_MCPB_GPC20_PAUSE_0_31_GPC_PAUSE_DEFAULT 0x00000000
-
-/***************************************************************************
- *GPC21_CTRL - MCPB GPC21 Control information
- ***************************************************************************/
-/* XPT_MEMDMA_MCPB :: GPC21_CTRL :: FREE_RUN_OR_LOCKED_TIMEBASE [31:31] */
-#define BCHP_XPT_MEMDMA_MCPB_GPC21_CTRL_FREE_RUN_OR_LOCKED_TIMEBASE_MASK 0x80000000
-#define BCHP_XPT_MEMDMA_MCPB_GPC21_CTRL_FREE_RUN_OR_LOCKED_TIMEBASE_SHIFT 31
-#define BCHP_XPT_MEMDMA_MCPB_GPC21_CTRL_FREE_RUN_OR_LOCKED_TIMEBASE_DEFAULT 0x00000000
-
-/* XPT_MEMDMA_MCPB :: GPC21_CTRL :: TIMEBASE_SEL [30:26] */
-#define BCHP_XPT_MEMDMA_MCPB_GPC21_CTRL_TIMEBASE_SEL_MASK 0x7c000000
-#define BCHP_XPT_MEMDMA_MCPB_GPC21_CTRL_TIMEBASE_SEL_SHIFT 26
-#define BCHP_XPT_MEMDMA_MCPB_GPC21_CTRL_TIMEBASE_SEL_DEFAULT 0x00000000
-
-/* XPT_MEMDMA_MCPB :: GPC21_CTRL :: PACING_SPEED [25:23] */
-#define BCHP_XPT_MEMDMA_MCPB_GPC21_CTRL_PACING_SPEED_MASK 0x03800000
-#define BCHP_XPT_MEMDMA_MCPB_GPC21_CTRL_PACING_SPEED_SHIFT 23
-#define BCHP_XPT_MEMDMA_MCPB_GPC21_CTRL_PACING_SPEED_DEFAULT 0x00000000
-
-/* XPT_MEMDMA_MCPB :: GPC21_CTRL :: COUNTER_MODE [22:22] */
-#define BCHP_XPT_MEMDMA_MCPB_GPC21_CTRL_COUNTER_MODE_MASK 0x00400000
-#define BCHP_XPT_MEMDMA_MCPB_GPC21_CTRL_COUNTER_MODE_SHIFT 22
-#define BCHP_XPT_MEMDMA_MCPB_GPC21_CTRL_COUNTER_MODE_DEFAULT 0x00000000
-
-/* XPT_MEMDMA_MCPB :: GPC21_CTRL :: SKIP_REPEAT_MODE [21:21] */
-#define BCHP_XPT_MEMDMA_MCPB_GPC21_CTRL_SKIP_REPEAT_MODE_MASK 0x00200000
-#define BCHP_XPT_MEMDMA_MCPB_GPC21_CTRL_SKIP_REPEAT_MODE_SHIFT 21
-#define BCHP_XPT_MEMDMA_MCPB_GPC21_CTRL_SKIP_REPEAT_MODE_DEFAULT 0x00000000
-
-/* XPT_MEMDMA_MCPB :: GPC21_CTRL :: SKIP_REPEAT_EN [20:20] */
-#define BCHP_XPT_MEMDMA_MCPB_GPC21_CTRL_SKIP_REPEAT_EN_MASK 0x00100000
-#define BCHP_XPT_MEMDMA_MCPB_GPC21_CTRL_SKIP_REPEAT_EN_SHIFT 20
-#define BCHP_XPT_MEMDMA_MCPB_GPC21_CTRL_SKIP_REPEAT_EN_DEFAULT 0x00000000
-
-/* XPT_MEMDMA_MCPB :: GPC21_CTRL :: SKIP_REPEAT_COUNT [19:00] */
-#define BCHP_XPT_MEMDMA_MCPB_GPC21_CTRL_SKIP_REPEAT_COUNT_MASK 0x000fffff
-#define BCHP_XPT_MEMDMA_MCPB_GPC21_CTRL_SKIP_REPEAT_COUNT_SHIFT 0
-#define BCHP_XPT_MEMDMA_MCPB_GPC21_CTRL_SKIP_REPEAT_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *GPC21_CURR_COUNTER_VAL - MCPB GPC21 Current counter value
- ***************************************************************************/
-/* XPT_MEMDMA_MCPB :: GPC21_CURR_COUNTER_VAL :: COUNTER [31:00] */
-#define BCHP_XPT_MEMDMA_MCPB_GPC21_CURR_COUNTER_VAL_COUNTER_MASK 0xffffffff
-#define BCHP_XPT_MEMDMA_MCPB_GPC21_CURR_COUNTER_VAL_COUNTER_SHIFT 0
-#define BCHP_XPT_MEMDMA_MCPB_GPC21_CURR_COUNTER_VAL_COUNTER_DEFAULT 0x00000000
-
-/***************************************************************************
- *GPC21_PAUSE_0_31 - MCPB GPC21 Current pause value
- ***************************************************************************/
-/* XPT_MEMDMA_MCPB :: GPC21_PAUSE_0_31 :: GPC_PAUSE [31:00] */
-#define BCHP_XPT_MEMDMA_MCPB_GPC21_PAUSE_0_31_GPC_PAUSE_MASK 0xffffffff
-#define BCHP_XPT_MEMDMA_MCPB_GPC21_PAUSE_0_31_GPC_PAUSE_SHIFT 0
-#define BCHP_XPT_MEMDMA_MCPB_GPC21_PAUSE_0_31_GPC_PAUSE_DEFAULT 0x00000000
-
-/***************************************************************************
- *GPC22_CTRL - MCPB GPC22 Control information
- ***************************************************************************/
-/* XPT_MEMDMA_MCPB :: GPC22_CTRL :: FREE_RUN_OR_LOCKED_TIMEBASE [31:31] */
-#define BCHP_XPT_MEMDMA_MCPB_GPC22_CTRL_FREE_RUN_OR_LOCKED_TIMEBASE_MASK 0x80000000
-#define BCHP_XPT_MEMDMA_MCPB_GPC22_CTRL_FREE_RUN_OR_LOCKED_TIMEBASE_SHIFT 31
-#define BCHP_XPT_MEMDMA_MCPB_GPC22_CTRL_FREE_RUN_OR_LOCKED_TIMEBASE_DEFAULT 0x00000000
-
-/* XPT_MEMDMA_MCPB :: GPC22_CTRL :: TIMEBASE_SEL [30:26] */
-#define BCHP_XPT_MEMDMA_MCPB_GPC22_CTRL_TIMEBASE_SEL_MASK 0x7c000000
-#define BCHP_XPT_MEMDMA_MCPB_GPC22_CTRL_TIMEBASE_SEL_SHIFT 26
-#define BCHP_XPT_MEMDMA_MCPB_GPC22_CTRL_TIMEBASE_SEL_DEFAULT 0x00000000
-
-/* XPT_MEMDMA_MCPB :: GPC22_CTRL :: PACING_SPEED [25:23] */
-#define BCHP_XPT_MEMDMA_MCPB_GPC22_CTRL_PACING_SPEED_MASK 0x03800000
-#define BCHP_XPT_MEMDMA_MCPB_GPC22_CTRL_PACING_SPEED_SHIFT 23
-#define BCHP_XPT_MEMDMA_MCPB_GPC22_CTRL_PACING_SPEED_DEFAULT 0x00000000
-
-/* XPT_MEMDMA_MCPB :: GPC22_CTRL :: COUNTER_MODE [22:22] */
-#define BCHP_XPT_MEMDMA_MCPB_GPC22_CTRL_COUNTER_MODE_MASK 0x00400000
-#define BCHP_XPT_MEMDMA_MCPB_GPC22_CTRL_COUNTER_MODE_SHIFT 22
-#define BCHP_XPT_MEMDMA_MCPB_GPC22_CTRL_COUNTER_MODE_DEFAULT 0x00000000
-
-/* XPT_MEMDMA_MCPB :: GPC22_CTRL :: SKIP_REPEAT_MODE [21:21] */
-#define BCHP_XPT_MEMDMA_MCPB_GPC22_CTRL_SKIP_REPEAT_MODE_MASK 0x00200000
-#define BCHP_XPT_MEMDMA_MCPB_GPC22_CTRL_SKIP_REPEAT_MODE_SHIFT 21
-#define BCHP_XPT_MEMDMA_MCPB_GPC22_CTRL_SKIP_REPEAT_MODE_DEFAULT 0x00000000
-
-/* XPT_MEMDMA_MCPB :: GPC22_CTRL :: SKIP_REPEAT_EN [20:20] */
-#define BCHP_XPT_MEMDMA_MCPB_GPC22_CTRL_SKIP_REPEAT_EN_MASK 0x00100000
-#define BCHP_XPT_MEMDMA_MCPB_GPC22_CTRL_SKIP_REPEAT_EN_SHIFT 20
-#define BCHP_XPT_MEMDMA_MCPB_GPC22_CTRL_SKIP_REPEAT_EN_DEFAULT 0x00000000
-
-/* XPT_MEMDMA_MCPB :: GPC22_CTRL :: SKIP_REPEAT_COUNT [19:00] */
-#define BCHP_XPT_MEMDMA_MCPB_GPC22_CTRL_SKIP_REPEAT_COUNT_MASK 0x000fffff
-#define BCHP_XPT_MEMDMA_MCPB_GPC22_CTRL_SKIP_REPEAT_COUNT_SHIFT 0
-#define BCHP_XPT_MEMDMA_MCPB_GPC22_CTRL_SKIP_REPEAT_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *GPC22_CURR_COUNTER_VAL - MCPB GPC22 Current counter value
- ***************************************************************************/
-/* XPT_MEMDMA_MCPB :: GPC22_CURR_COUNTER_VAL :: COUNTER [31:00] */
-#define BCHP_XPT_MEMDMA_MCPB_GPC22_CURR_COUNTER_VAL_COUNTER_MASK 0xffffffff
-#define BCHP_XPT_MEMDMA_MCPB_GPC22_CURR_COUNTER_VAL_COUNTER_SHIFT 0
-#define BCHP_XPT_MEMDMA_MCPB_GPC22_CURR_COUNTER_VAL_COUNTER_DEFAULT 0x00000000
-
-/***************************************************************************
- *GPC22_PAUSE_0_31 - MCPB GPC22 Current pause value
- ***************************************************************************/
-/* XPT_MEMDMA_MCPB :: GPC22_PAUSE_0_31 :: GPC_PAUSE [31:00] */
-#define BCHP_XPT_MEMDMA_MCPB_GPC22_PAUSE_0_31_GPC_PAUSE_MASK 0xffffffff
-#define BCHP_XPT_MEMDMA_MCPB_GPC22_PAUSE_0_31_GPC_PAUSE_SHIFT 0
-#define BCHP_XPT_MEMDMA_MCPB_GPC22_PAUSE_0_31_GPC_PAUSE_DEFAULT 0x00000000
-
-/***************************************************************************
- *GPC23_CTRL - MCPB GPC23 Control information
- ***************************************************************************/
-/* XPT_MEMDMA_MCPB :: GPC23_CTRL :: FREE_RUN_OR_LOCKED_TIMEBASE [31:31] */
-#define BCHP_XPT_MEMDMA_MCPB_GPC23_CTRL_FREE_RUN_OR_LOCKED_TIMEBASE_MASK 0x80000000
-#define BCHP_XPT_MEMDMA_MCPB_GPC23_CTRL_FREE_RUN_OR_LOCKED_TIMEBASE_SHIFT 31
-#define BCHP_XPT_MEMDMA_MCPB_GPC23_CTRL_FREE_RUN_OR_LOCKED_TIMEBASE_DEFAULT 0x00000000
-
-/* XPT_MEMDMA_MCPB :: GPC23_CTRL :: TIMEBASE_SEL [30:26] */
-#define BCHP_XPT_MEMDMA_MCPB_GPC23_CTRL_TIMEBASE_SEL_MASK 0x7c000000
-#define BCHP_XPT_MEMDMA_MCPB_GPC23_CTRL_TIMEBASE_SEL_SHIFT 26
-#define BCHP_XPT_MEMDMA_MCPB_GPC23_CTRL_TIMEBASE_SEL_DEFAULT 0x00000000
-
-/* XPT_MEMDMA_MCPB :: GPC23_CTRL :: PACING_SPEED [25:23] */
-#define BCHP_XPT_MEMDMA_MCPB_GPC23_CTRL_PACING_SPEED_MASK 0x03800000
-#define BCHP_XPT_MEMDMA_MCPB_GPC23_CTRL_PACING_SPEED_SHIFT 23
-#define BCHP_XPT_MEMDMA_MCPB_GPC23_CTRL_PACING_SPEED_DEFAULT 0x00000000
-
-/* XPT_MEMDMA_MCPB :: GPC23_CTRL :: COUNTER_MODE [22:22] */
-#define BCHP_XPT_MEMDMA_MCPB_GPC23_CTRL_COUNTER_MODE_MASK 0x00400000
-#define BCHP_XPT_MEMDMA_MCPB_GPC23_CTRL_COUNTER_MODE_SHIFT 22
-#define BCHP_XPT_MEMDMA_MCPB_GPC23_CTRL_COUNTER_MODE_DEFAULT 0x00000000
-
-/* XPT_MEMDMA_MCPB :: GPC23_CTRL :: SKIP_REPEAT_MODE [21:21] */
-#define BCHP_XPT_MEMDMA_MCPB_GPC23_CTRL_SKIP_REPEAT_MODE_MASK 0x00200000
-#define BCHP_XPT_MEMDMA_MCPB_GPC23_CTRL_SKIP_REPEAT_MODE_SHIFT 21
-#define BCHP_XPT_MEMDMA_MCPB_GPC23_CTRL_SKIP_REPEAT_MODE_DEFAULT 0x00000000
-
-/* XPT_MEMDMA_MCPB :: GPC23_CTRL :: SKIP_REPEAT_EN [20:20] */
-#define BCHP_XPT_MEMDMA_MCPB_GPC23_CTRL_SKIP_REPEAT_EN_MASK 0x00100000
-#define BCHP_XPT_MEMDMA_MCPB_GPC23_CTRL_SKIP_REPEAT_EN_SHIFT 20
-#define BCHP_XPT_MEMDMA_MCPB_GPC23_CTRL_SKIP_REPEAT_EN_DEFAULT 0x00000000
-
-/* XPT_MEMDMA_MCPB :: GPC23_CTRL :: SKIP_REPEAT_COUNT [19:00] */
-#define BCHP_XPT_MEMDMA_MCPB_GPC23_CTRL_SKIP_REPEAT_COUNT_MASK 0x000fffff
-#define BCHP_XPT_MEMDMA_MCPB_GPC23_CTRL_SKIP_REPEAT_COUNT_SHIFT 0
-#define BCHP_XPT_MEMDMA_MCPB_GPC23_CTRL_SKIP_REPEAT_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *GPC23_CURR_COUNTER_VAL - MCPB GPC23 Current counter value
- ***************************************************************************/
-/* XPT_MEMDMA_MCPB :: GPC23_CURR_COUNTER_VAL :: COUNTER [31:00] */
-#define BCHP_XPT_MEMDMA_MCPB_GPC23_CURR_COUNTER_VAL_COUNTER_MASK 0xffffffff
-#define BCHP_XPT_MEMDMA_MCPB_GPC23_CURR_COUNTER_VAL_COUNTER_SHIFT 0
-#define BCHP_XPT_MEMDMA_MCPB_GPC23_CURR_COUNTER_VAL_COUNTER_DEFAULT 0x00000000
-
-/***************************************************************************
- *GPC23_PAUSE_0_31 - MCPB GPC23 Current pause value
- ***************************************************************************/
-/* XPT_MEMDMA_MCPB :: GPC23_PAUSE_0_31 :: GPC_PAUSE [31:00] */
-#define BCHP_XPT_MEMDMA_MCPB_GPC23_PAUSE_0_31_GPC_PAUSE_MASK 0xffffffff
-#define BCHP_XPT_MEMDMA_MCPB_GPC23_PAUSE_0_31_GPC_PAUSE_SHIFT 0
-#define BCHP_XPT_MEMDMA_MCPB_GPC23_PAUSE_0_31_GPC_PAUSE_DEFAULT 0x00000000
-
-/***************************************************************************
- *GPC24_CTRL - MCPB GPC24 Control information
- ***************************************************************************/
-/* XPT_MEMDMA_MCPB :: GPC24_CTRL :: FREE_RUN_OR_LOCKED_TIMEBASE [31:31] */
-#define BCHP_XPT_MEMDMA_MCPB_GPC24_CTRL_FREE_RUN_OR_LOCKED_TIMEBASE_MASK 0x80000000
-#define BCHP_XPT_MEMDMA_MCPB_GPC24_CTRL_FREE_RUN_OR_LOCKED_TIMEBASE_SHIFT 31
-#define BCHP_XPT_MEMDMA_MCPB_GPC24_CTRL_FREE_RUN_OR_LOCKED_TIMEBASE_DEFAULT 0x00000000
-
-/* XPT_MEMDMA_MCPB :: GPC24_CTRL :: TIMEBASE_SEL [30:26] */
-#define BCHP_XPT_MEMDMA_MCPB_GPC24_CTRL_TIMEBASE_SEL_MASK 0x7c000000
-#define BCHP_XPT_MEMDMA_MCPB_GPC24_CTRL_TIMEBASE_SEL_SHIFT 26
-#define BCHP_XPT_MEMDMA_MCPB_GPC24_CTRL_TIMEBASE_SEL_DEFAULT 0x00000000
-
-/* XPT_MEMDMA_MCPB :: GPC24_CTRL :: PACING_SPEED [25:23] */
-#define BCHP_XPT_MEMDMA_MCPB_GPC24_CTRL_PACING_SPEED_MASK 0x03800000
-#define BCHP_XPT_MEMDMA_MCPB_GPC24_CTRL_PACING_SPEED_SHIFT 23
-#define BCHP_XPT_MEMDMA_MCPB_GPC24_CTRL_PACING_SPEED_DEFAULT 0x00000000
-
-/* XPT_MEMDMA_MCPB :: GPC24_CTRL :: COUNTER_MODE [22:22] */
-#define BCHP_XPT_MEMDMA_MCPB_GPC24_CTRL_COUNTER_MODE_MASK 0x00400000
-#define BCHP_XPT_MEMDMA_MCPB_GPC24_CTRL_COUNTER_MODE_SHIFT 22
-#define BCHP_XPT_MEMDMA_MCPB_GPC24_CTRL_COUNTER_MODE_DEFAULT 0x00000000
-
-/* XPT_MEMDMA_MCPB :: GPC24_CTRL :: SKIP_REPEAT_MODE [21:21] */
-#define BCHP_XPT_MEMDMA_MCPB_GPC24_CTRL_SKIP_REPEAT_MODE_MASK 0x00200000
-#define BCHP_XPT_MEMDMA_MCPB_GPC24_CTRL_SKIP_REPEAT_MODE_SHIFT 21
-#define BCHP_XPT_MEMDMA_MCPB_GPC24_CTRL_SKIP_REPEAT_MODE_DEFAULT 0x00000000
-
-/* XPT_MEMDMA_MCPB :: GPC24_CTRL :: SKIP_REPEAT_EN [20:20] */
-#define BCHP_XPT_MEMDMA_MCPB_GPC24_CTRL_SKIP_REPEAT_EN_MASK 0x00100000
-#define BCHP_XPT_MEMDMA_MCPB_GPC24_CTRL_SKIP_REPEAT_EN_SHIFT 20
-#define BCHP_XPT_MEMDMA_MCPB_GPC24_CTRL_SKIP_REPEAT_EN_DEFAULT 0x00000000
-
-/* XPT_MEMDMA_MCPB :: GPC24_CTRL :: SKIP_REPEAT_COUNT [19:00] */
-#define BCHP_XPT_MEMDMA_MCPB_GPC24_CTRL_SKIP_REPEAT_COUNT_MASK 0x000fffff
-#define BCHP_XPT_MEMDMA_MCPB_GPC24_CTRL_SKIP_REPEAT_COUNT_SHIFT 0
-#define BCHP_XPT_MEMDMA_MCPB_GPC24_CTRL_SKIP_REPEAT_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *GPC24_CURR_COUNTER_VAL - MCPB GPC24 Current counter value
- ***************************************************************************/
-/* XPT_MEMDMA_MCPB :: GPC24_CURR_COUNTER_VAL :: COUNTER [31:00] */
-#define BCHP_XPT_MEMDMA_MCPB_GPC24_CURR_COUNTER_VAL_COUNTER_MASK 0xffffffff
-#define BCHP_XPT_MEMDMA_MCPB_GPC24_CURR_COUNTER_VAL_COUNTER_SHIFT 0
-#define BCHP_XPT_MEMDMA_MCPB_GPC24_CURR_COUNTER_VAL_COUNTER_DEFAULT 0x00000000
-
-/***************************************************************************
- *GPC24_PAUSE_0_31 - MCPB GPC24 Current pause value
- ***************************************************************************/
-/* XPT_MEMDMA_MCPB :: GPC24_PAUSE_0_31 :: GPC_PAUSE [31:00] */
-#define BCHP_XPT_MEMDMA_MCPB_GPC24_PAUSE_0_31_GPC_PAUSE_MASK 0xffffffff
-#define BCHP_XPT_MEMDMA_MCPB_GPC24_PAUSE_0_31_GPC_PAUSE_SHIFT 0
-#define BCHP_XPT_MEMDMA_MCPB_GPC24_PAUSE_0_31_GPC_PAUSE_DEFAULT 0x00000000
-
-/***************************************************************************
- *GPC25_CTRL - MCPB GPC25 Control information
- ***************************************************************************/
-/* XPT_MEMDMA_MCPB :: GPC25_CTRL :: FREE_RUN_OR_LOCKED_TIMEBASE [31:31] */
-#define BCHP_XPT_MEMDMA_MCPB_GPC25_CTRL_FREE_RUN_OR_LOCKED_TIMEBASE_MASK 0x80000000
-#define BCHP_XPT_MEMDMA_MCPB_GPC25_CTRL_FREE_RUN_OR_LOCKED_TIMEBASE_SHIFT 31
-#define BCHP_XPT_MEMDMA_MCPB_GPC25_CTRL_FREE_RUN_OR_LOCKED_TIMEBASE_DEFAULT 0x00000000
-
-/* XPT_MEMDMA_MCPB :: GPC25_CTRL :: TIMEBASE_SEL [30:26] */
-#define BCHP_XPT_MEMDMA_MCPB_GPC25_CTRL_TIMEBASE_SEL_MASK 0x7c000000
-#define BCHP_XPT_MEMDMA_MCPB_GPC25_CTRL_TIMEBASE_SEL_SHIFT 26
-#define BCHP_XPT_MEMDMA_MCPB_GPC25_CTRL_TIMEBASE_SEL_DEFAULT 0x00000000
-
-/* XPT_MEMDMA_MCPB :: GPC25_CTRL :: PACING_SPEED [25:23] */
-#define BCHP_XPT_MEMDMA_MCPB_GPC25_CTRL_PACING_SPEED_MASK 0x03800000
-#define BCHP_XPT_MEMDMA_MCPB_GPC25_CTRL_PACING_SPEED_SHIFT 23
-#define BCHP_XPT_MEMDMA_MCPB_GPC25_CTRL_PACING_SPEED_DEFAULT 0x00000000
-
-/* XPT_MEMDMA_MCPB :: GPC25_CTRL :: COUNTER_MODE [22:22] */
-#define BCHP_XPT_MEMDMA_MCPB_GPC25_CTRL_COUNTER_MODE_MASK 0x00400000
-#define BCHP_XPT_MEMDMA_MCPB_GPC25_CTRL_COUNTER_MODE_SHIFT 22
-#define BCHP_XPT_MEMDMA_MCPB_GPC25_CTRL_COUNTER_MODE_DEFAULT 0x00000000
-
-/* XPT_MEMDMA_MCPB :: GPC25_CTRL :: SKIP_REPEAT_MODE [21:21] */
-#define BCHP_XPT_MEMDMA_MCPB_GPC25_CTRL_SKIP_REPEAT_MODE_MASK 0x00200000
-#define BCHP_XPT_MEMDMA_MCPB_GPC25_CTRL_SKIP_REPEAT_MODE_SHIFT 21
-#define BCHP_XPT_MEMDMA_MCPB_GPC25_CTRL_SKIP_REPEAT_MODE_DEFAULT 0x00000000
-
-/* XPT_MEMDMA_MCPB :: GPC25_CTRL :: SKIP_REPEAT_EN [20:20] */
-#define BCHP_XPT_MEMDMA_MCPB_GPC25_CTRL_SKIP_REPEAT_EN_MASK 0x00100000
-#define BCHP_XPT_MEMDMA_MCPB_GPC25_CTRL_SKIP_REPEAT_EN_SHIFT 20
-#define BCHP_XPT_MEMDMA_MCPB_GPC25_CTRL_SKIP_REPEAT_EN_DEFAULT 0x00000000
-
-/* XPT_MEMDMA_MCPB :: GPC25_CTRL :: SKIP_REPEAT_COUNT [19:00] */
-#define BCHP_XPT_MEMDMA_MCPB_GPC25_CTRL_SKIP_REPEAT_COUNT_MASK 0x000fffff
-#define BCHP_XPT_MEMDMA_MCPB_GPC25_CTRL_SKIP_REPEAT_COUNT_SHIFT 0
-#define BCHP_XPT_MEMDMA_MCPB_GPC25_CTRL_SKIP_REPEAT_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *GPC25_CURR_COUNTER_VAL - MCPB GPC25 Current counter value
- ***************************************************************************/
-/* XPT_MEMDMA_MCPB :: GPC25_CURR_COUNTER_VAL :: COUNTER [31:00] */
-#define BCHP_XPT_MEMDMA_MCPB_GPC25_CURR_COUNTER_VAL_COUNTER_MASK 0xffffffff
-#define BCHP_XPT_MEMDMA_MCPB_GPC25_CURR_COUNTER_VAL_COUNTER_SHIFT 0
-#define BCHP_XPT_MEMDMA_MCPB_GPC25_CURR_COUNTER_VAL_COUNTER_DEFAULT 0x00000000
-
-/***************************************************************************
- *GPC25_PAUSE_0_31 - MCPB GPC25 Current pause value
- ***************************************************************************/
-/* XPT_MEMDMA_MCPB :: GPC25_PAUSE_0_31 :: GPC_PAUSE [31:00] */
-#define BCHP_XPT_MEMDMA_MCPB_GPC25_PAUSE_0_31_GPC_PAUSE_MASK 0xffffffff
-#define BCHP_XPT_MEMDMA_MCPB_GPC25_PAUSE_0_31_GPC_PAUSE_SHIFT 0
-#define BCHP_XPT_MEMDMA_MCPB_GPC25_PAUSE_0_31_GPC_PAUSE_DEFAULT 0x00000000
-
-/***************************************************************************
- *GPC26_CTRL - MCPB GPC26 Control information
- ***************************************************************************/
-/* XPT_MEMDMA_MCPB :: GPC26_CTRL :: FREE_RUN_OR_LOCKED_TIMEBASE [31:31] */
-#define BCHP_XPT_MEMDMA_MCPB_GPC26_CTRL_FREE_RUN_OR_LOCKED_TIMEBASE_MASK 0x80000000
-#define BCHP_XPT_MEMDMA_MCPB_GPC26_CTRL_FREE_RUN_OR_LOCKED_TIMEBASE_SHIFT 31
-#define BCHP_XPT_MEMDMA_MCPB_GPC26_CTRL_FREE_RUN_OR_LOCKED_TIMEBASE_DEFAULT 0x00000000
-
-/* XPT_MEMDMA_MCPB :: GPC26_CTRL :: TIMEBASE_SEL [30:26] */
-#define BCHP_XPT_MEMDMA_MCPB_GPC26_CTRL_TIMEBASE_SEL_MASK 0x7c000000
-#define BCHP_XPT_MEMDMA_MCPB_GPC26_CTRL_TIMEBASE_SEL_SHIFT 26
-#define BCHP_XPT_MEMDMA_MCPB_GPC26_CTRL_TIMEBASE_SEL_DEFAULT 0x00000000
-
-/* XPT_MEMDMA_MCPB :: GPC26_CTRL :: PACING_SPEED [25:23] */
-#define BCHP_XPT_MEMDMA_MCPB_GPC26_CTRL_PACING_SPEED_MASK 0x03800000
-#define BCHP_XPT_MEMDMA_MCPB_GPC26_CTRL_PACING_SPEED_SHIFT 23
-#define BCHP_XPT_MEMDMA_MCPB_GPC26_CTRL_PACING_SPEED_DEFAULT 0x00000000
-
-/* XPT_MEMDMA_MCPB :: GPC26_CTRL :: COUNTER_MODE [22:22] */
-#define BCHP_XPT_MEMDMA_MCPB_GPC26_CTRL_COUNTER_MODE_MASK 0x00400000
-#define BCHP_XPT_MEMDMA_MCPB_GPC26_CTRL_COUNTER_MODE_SHIFT 22
-#define BCHP_XPT_MEMDMA_MCPB_GPC26_CTRL_COUNTER_MODE_DEFAULT 0x00000000
-
-/* XPT_MEMDMA_MCPB :: GPC26_CTRL :: SKIP_REPEAT_MODE [21:21] */
-#define BCHP_XPT_MEMDMA_MCPB_GPC26_CTRL_SKIP_REPEAT_MODE_MASK 0x00200000
-#define BCHP_XPT_MEMDMA_MCPB_GPC26_CTRL_SKIP_REPEAT_MODE_SHIFT 21
-#define BCHP_XPT_MEMDMA_MCPB_GPC26_CTRL_SKIP_REPEAT_MODE_DEFAULT 0x00000000
-
-/* XPT_MEMDMA_MCPB :: GPC26_CTRL :: SKIP_REPEAT_EN [20:20] */
-#define BCHP_XPT_MEMDMA_MCPB_GPC26_CTRL_SKIP_REPEAT_EN_MASK 0x00100000
-#define BCHP_XPT_MEMDMA_MCPB_GPC26_CTRL_SKIP_REPEAT_EN_SHIFT 20
-#define BCHP_XPT_MEMDMA_MCPB_GPC26_CTRL_SKIP_REPEAT_EN_DEFAULT 0x00000000
-
-/* XPT_MEMDMA_MCPB :: GPC26_CTRL :: SKIP_REPEAT_COUNT [19:00] */
-#define BCHP_XPT_MEMDMA_MCPB_GPC26_CTRL_SKIP_REPEAT_COUNT_MASK 0x000fffff
-#define BCHP_XPT_MEMDMA_MCPB_GPC26_CTRL_SKIP_REPEAT_COUNT_SHIFT 0
-#define BCHP_XPT_MEMDMA_MCPB_GPC26_CTRL_SKIP_REPEAT_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *GPC26_CURR_COUNTER_VAL - MCPB GPC26 Current counter value
- ***************************************************************************/
-/* XPT_MEMDMA_MCPB :: GPC26_CURR_COUNTER_VAL :: COUNTER [31:00] */
-#define BCHP_XPT_MEMDMA_MCPB_GPC26_CURR_COUNTER_VAL_COUNTER_MASK 0xffffffff
-#define BCHP_XPT_MEMDMA_MCPB_GPC26_CURR_COUNTER_VAL_COUNTER_SHIFT 0
-#define BCHP_XPT_MEMDMA_MCPB_GPC26_CURR_COUNTER_VAL_COUNTER_DEFAULT 0x00000000
-
-/***************************************************************************
- *GPC26_PAUSE_0_31 - MCPB GPC26 Current pause value
- ***************************************************************************/
-/* XPT_MEMDMA_MCPB :: GPC26_PAUSE_0_31 :: GPC_PAUSE [31:00] */
-#define BCHP_XPT_MEMDMA_MCPB_GPC26_PAUSE_0_31_GPC_PAUSE_MASK 0xffffffff
-#define BCHP_XPT_MEMDMA_MCPB_GPC26_PAUSE_0_31_GPC_PAUSE_SHIFT 0
-#define BCHP_XPT_MEMDMA_MCPB_GPC26_PAUSE_0_31_GPC_PAUSE_DEFAULT 0x00000000
-
-/***************************************************************************
- *GPC27_CTRL - MCPB GPC27 Control information
- ***************************************************************************/
-/* XPT_MEMDMA_MCPB :: GPC27_CTRL :: FREE_RUN_OR_LOCKED_TIMEBASE [31:31] */
-#define BCHP_XPT_MEMDMA_MCPB_GPC27_CTRL_FREE_RUN_OR_LOCKED_TIMEBASE_MASK 0x80000000
-#define BCHP_XPT_MEMDMA_MCPB_GPC27_CTRL_FREE_RUN_OR_LOCKED_TIMEBASE_SHIFT 31
-#define BCHP_XPT_MEMDMA_MCPB_GPC27_CTRL_FREE_RUN_OR_LOCKED_TIMEBASE_DEFAULT 0x00000000
-
-/* XPT_MEMDMA_MCPB :: GPC27_CTRL :: TIMEBASE_SEL [30:26] */
-#define BCHP_XPT_MEMDMA_MCPB_GPC27_CTRL_TIMEBASE_SEL_MASK 0x7c000000
-#define BCHP_XPT_MEMDMA_MCPB_GPC27_CTRL_TIMEBASE_SEL_SHIFT 26
-#define BCHP_XPT_MEMDMA_MCPB_GPC27_CTRL_TIMEBASE_SEL_DEFAULT 0x00000000
-
-/* XPT_MEMDMA_MCPB :: GPC27_CTRL :: PACING_SPEED [25:23] */
-#define BCHP_XPT_MEMDMA_MCPB_GPC27_CTRL_PACING_SPEED_MASK 0x03800000
-#define BCHP_XPT_MEMDMA_MCPB_GPC27_CTRL_PACING_SPEED_SHIFT 23
-#define BCHP_XPT_MEMDMA_MCPB_GPC27_CTRL_PACING_SPEED_DEFAULT 0x00000000
-
-/* XPT_MEMDMA_MCPB :: GPC27_CTRL :: COUNTER_MODE [22:22] */
-#define BCHP_XPT_MEMDMA_MCPB_GPC27_CTRL_COUNTER_MODE_MASK 0x00400000
-#define BCHP_XPT_MEMDMA_MCPB_GPC27_CTRL_COUNTER_MODE_SHIFT 22
-#define BCHP_XPT_MEMDMA_MCPB_GPC27_CTRL_COUNTER_MODE_DEFAULT 0x00000000
-
-/* XPT_MEMDMA_MCPB :: GPC27_CTRL :: SKIP_REPEAT_MODE [21:21] */
-#define BCHP_XPT_MEMDMA_MCPB_GPC27_CTRL_SKIP_REPEAT_MODE_MASK 0x00200000
-#define BCHP_XPT_MEMDMA_MCPB_GPC27_CTRL_SKIP_REPEAT_MODE_SHIFT 21
-#define BCHP_XPT_MEMDMA_MCPB_GPC27_CTRL_SKIP_REPEAT_MODE_DEFAULT 0x00000000
-
-/* XPT_MEMDMA_MCPB :: GPC27_CTRL :: SKIP_REPEAT_EN [20:20] */
-#define BCHP_XPT_MEMDMA_MCPB_GPC27_CTRL_SKIP_REPEAT_EN_MASK 0x00100000
-#define BCHP_XPT_MEMDMA_MCPB_GPC27_CTRL_SKIP_REPEAT_EN_SHIFT 20
-#define BCHP_XPT_MEMDMA_MCPB_GPC27_CTRL_SKIP_REPEAT_EN_DEFAULT 0x00000000
-
-/* XPT_MEMDMA_MCPB :: GPC27_CTRL :: SKIP_REPEAT_COUNT [19:00] */
-#define BCHP_XPT_MEMDMA_MCPB_GPC27_CTRL_SKIP_REPEAT_COUNT_MASK 0x000fffff
-#define BCHP_XPT_MEMDMA_MCPB_GPC27_CTRL_SKIP_REPEAT_COUNT_SHIFT 0
-#define BCHP_XPT_MEMDMA_MCPB_GPC27_CTRL_SKIP_REPEAT_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *GPC27_CURR_COUNTER_VAL - MCPB GPC27 Current counter value
- ***************************************************************************/
-/* XPT_MEMDMA_MCPB :: GPC27_CURR_COUNTER_VAL :: COUNTER [31:00] */
-#define BCHP_XPT_MEMDMA_MCPB_GPC27_CURR_COUNTER_VAL_COUNTER_MASK 0xffffffff
-#define BCHP_XPT_MEMDMA_MCPB_GPC27_CURR_COUNTER_VAL_COUNTER_SHIFT 0
-#define BCHP_XPT_MEMDMA_MCPB_GPC27_CURR_COUNTER_VAL_COUNTER_DEFAULT 0x00000000
-
-/***************************************************************************
- *GPC27_PAUSE_0_31 - MCPB GPC27 Current pause value
- ***************************************************************************/
-/* XPT_MEMDMA_MCPB :: GPC27_PAUSE_0_31 :: GPC_PAUSE [31:00] */
-#define BCHP_XPT_MEMDMA_MCPB_GPC27_PAUSE_0_31_GPC_PAUSE_MASK 0xffffffff
-#define BCHP_XPT_MEMDMA_MCPB_GPC27_PAUSE_0_31_GPC_PAUSE_SHIFT 0
-#define BCHP_XPT_MEMDMA_MCPB_GPC27_PAUSE_0_31_GPC_PAUSE_DEFAULT 0x00000000
-
-/***************************************************************************
- *GPC28_CTRL - MCPB GPC28 Control information
- ***************************************************************************/
-/* XPT_MEMDMA_MCPB :: GPC28_CTRL :: FREE_RUN_OR_LOCKED_TIMEBASE [31:31] */
-#define BCHP_XPT_MEMDMA_MCPB_GPC28_CTRL_FREE_RUN_OR_LOCKED_TIMEBASE_MASK 0x80000000
-#define BCHP_XPT_MEMDMA_MCPB_GPC28_CTRL_FREE_RUN_OR_LOCKED_TIMEBASE_SHIFT 31
-#define BCHP_XPT_MEMDMA_MCPB_GPC28_CTRL_FREE_RUN_OR_LOCKED_TIMEBASE_DEFAULT 0x00000000
-
-/* XPT_MEMDMA_MCPB :: GPC28_CTRL :: TIMEBASE_SEL [30:26] */
-#define BCHP_XPT_MEMDMA_MCPB_GPC28_CTRL_TIMEBASE_SEL_MASK 0x7c000000
-#define BCHP_XPT_MEMDMA_MCPB_GPC28_CTRL_TIMEBASE_SEL_SHIFT 26
-#define BCHP_XPT_MEMDMA_MCPB_GPC28_CTRL_TIMEBASE_SEL_DEFAULT 0x00000000
-
-/* XPT_MEMDMA_MCPB :: GPC28_CTRL :: PACING_SPEED [25:23] */
-#define BCHP_XPT_MEMDMA_MCPB_GPC28_CTRL_PACING_SPEED_MASK 0x03800000
-#define BCHP_XPT_MEMDMA_MCPB_GPC28_CTRL_PACING_SPEED_SHIFT 23
-#define BCHP_XPT_MEMDMA_MCPB_GPC28_CTRL_PACING_SPEED_DEFAULT 0x00000000
-
-/* XPT_MEMDMA_MCPB :: GPC28_CTRL :: COUNTER_MODE [22:22] */
-#define BCHP_XPT_MEMDMA_MCPB_GPC28_CTRL_COUNTER_MODE_MASK 0x00400000
-#define BCHP_XPT_MEMDMA_MCPB_GPC28_CTRL_COUNTER_MODE_SHIFT 22
-#define BCHP_XPT_MEMDMA_MCPB_GPC28_CTRL_COUNTER_MODE_DEFAULT 0x00000000
-
-/* XPT_MEMDMA_MCPB :: GPC28_CTRL :: SKIP_REPEAT_MODE [21:21] */
-#define BCHP_XPT_MEMDMA_MCPB_GPC28_CTRL_SKIP_REPEAT_MODE_MASK 0x00200000
-#define BCHP_XPT_MEMDMA_MCPB_GPC28_CTRL_SKIP_REPEAT_MODE_SHIFT 21
-#define BCHP_XPT_MEMDMA_MCPB_GPC28_CTRL_SKIP_REPEAT_MODE_DEFAULT 0x00000000
-
-/* XPT_MEMDMA_MCPB :: GPC28_CTRL :: SKIP_REPEAT_EN [20:20] */
-#define BCHP_XPT_MEMDMA_MCPB_GPC28_CTRL_SKIP_REPEAT_EN_MASK 0x00100000
-#define BCHP_XPT_MEMDMA_MCPB_GPC28_CTRL_SKIP_REPEAT_EN_SHIFT 20
-#define BCHP_XPT_MEMDMA_MCPB_GPC28_CTRL_SKIP_REPEAT_EN_DEFAULT 0x00000000
-
-/* XPT_MEMDMA_MCPB :: GPC28_CTRL :: SKIP_REPEAT_COUNT [19:00] */
-#define BCHP_XPT_MEMDMA_MCPB_GPC28_CTRL_SKIP_REPEAT_COUNT_MASK 0x000fffff
-#define BCHP_XPT_MEMDMA_MCPB_GPC28_CTRL_SKIP_REPEAT_COUNT_SHIFT 0
-#define BCHP_XPT_MEMDMA_MCPB_GPC28_CTRL_SKIP_REPEAT_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *GPC28_CURR_COUNTER_VAL - MCPB GPC28 Current counter value
- ***************************************************************************/
-/* XPT_MEMDMA_MCPB :: GPC28_CURR_COUNTER_VAL :: COUNTER [31:00] */
-#define BCHP_XPT_MEMDMA_MCPB_GPC28_CURR_COUNTER_VAL_COUNTER_MASK 0xffffffff
-#define BCHP_XPT_MEMDMA_MCPB_GPC28_CURR_COUNTER_VAL_COUNTER_SHIFT 0
-#define BCHP_XPT_MEMDMA_MCPB_GPC28_CURR_COUNTER_VAL_COUNTER_DEFAULT 0x00000000
-
-/***************************************************************************
- *GPC28_PAUSE_0_31 - MCPB GPC28 Current pause value
- ***************************************************************************/
-/* XPT_MEMDMA_MCPB :: GPC28_PAUSE_0_31 :: GPC_PAUSE [31:00] */
-#define BCHP_XPT_MEMDMA_MCPB_GPC28_PAUSE_0_31_GPC_PAUSE_MASK 0xffffffff
-#define BCHP_XPT_MEMDMA_MCPB_GPC28_PAUSE_0_31_GPC_PAUSE_SHIFT 0
-#define BCHP_XPT_MEMDMA_MCPB_GPC28_PAUSE_0_31_GPC_PAUSE_DEFAULT 0x00000000
-
-/***************************************************************************
- *GPC29_CTRL - MCPB GPC29 Control information
- ***************************************************************************/
-/* XPT_MEMDMA_MCPB :: GPC29_CTRL :: FREE_RUN_OR_LOCKED_TIMEBASE [31:31] */
-#define BCHP_XPT_MEMDMA_MCPB_GPC29_CTRL_FREE_RUN_OR_LOCKED_TIMEBASE_MASK 0x80000000
-#define BCHP_XPT_MEMDMA_MCPB_GPC29_CTRL_FREE_RUN_OR_LOCKED_TIMEBASE_SHIFT 31
-#define BCHP_XPT_MEMDMA_MCPB_GPC29_CTRL_FREE_RUN_OR_LOCKED_TIMEBASE_DEFAULT 0x00000000
-
-/* XPT_MEMDMA_MCPB :: GPC29_CTRL :: TIMEBASE_SEL [30:26] */
-#define BCHP_XPT_MEMDMA_MCPB_GPC29_CTRL_TIMEBASE_SEL_MASK 0x7c000000
-#define BCHP_XPT_MEMDMA_MCPB_GPC29_CTRL_TIMEBASE_SEL_SHIFT 26
-#define BCHP_XPT_MEMDMA_MCPB_GPC29_CTRL_TIMEBASE_SEL_DEFAULT 0x00000000
-
-/* XPT_MEMDMA_MCPB :: GPC29_CTRL :: PACING_SPEED [25:23] */
-#define BCHP_XPT_MEMDMA_MCPB_GPC29_CTRL_PACING_SPEED_MASK 0x03800000
-#define BCHP_XPT_MEMDMA_MCPB_GPC29_CTRL_PACING_SPEED_SHIFT 23
-#define BCHP_XPT_MEMDMA_MCPB_GPC29_CTRL_PACING_SPEED_DEFAULT 0x00000000
-
-/* XPT_MEMDMA_MCPB :: GPC29_CTRL :: COUNTER_MODE [22:22] */
-#define BCHP_XPT_MEMDMA_MCPB_GPC29_CTRL_COUNTER_MODE_MASK 0x00400000
-#define BCHP_XPT_MEMDMA_MCPB_GPC29_CTRL_COUNTER_MODE_SHIFT 22
-#define BCHP_XPT_MEMDMA_MCPB_GPC29_CTRL_COUNTER_MODE_DEFAULT 0x00000000
-
-/* XPT_MEMDMA_MCPB :: GPC29_CTRL :: SKIP_REPEAT_MODE [21:21] */
-#define BCHP_XPT_MEMDMA_MCPB_GPC29_CTRL_SKIP_REPEAT_MODE_MASK 0x00200000
-#define BCHP_XPT_MEMDMA_MCPB_GPC29_CTRL_SKIP_REPEAT_MODE_SHIFT 21
-#define BCHP_XPT_MEMDMA_MCPB_GPC29_CTRL_SKIP_REPEAT_MODE_DEFAULT 0x00000000
-
-/* XPT_MEMDMA_MCPB :: GPC29_CTRL :: SKIP_REPEAT_EN [20:20] */
-#define BCHP_XPT_MEMDMA_MCPB_GPC29_CTRL_SKIP_REPEAT_EN_MASK 0x00100000
-#define BCHP_XPT_MEMDMA_MCPB_GPC29_CTRL_SKIP_REPEAT_EN_SHIFT 20
-#define BCHP_XPT_MEMDMA_MCPB_GPC29_CTRL_SKIP_REPEAT_EN_DEFAULT 0x00000000
-
-/* XPT_MEMDMA_MCPB :: GPC29_CTRL :: SKIP_REPEAT_COUNT [19:00] */
-#define BCHP_XPT_MEMDMA_MCPB_GPC29_CTRL_SKIP_REPEAT_COUNT_MASK 0x000fffff
-#define BCHP_XPT_MEMDMA_MCPB_GPC29_CTRL_SKIP_REPEAT_COUNT_SHIFT 0
-#define BCHP_XPT_MEMDMA_MCPB_GPC29_CTRL_SKIP_REPEAT_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *GPC29_CURR_COUNTER_VAL - MCPB GPC29 Current counter value
- ***************************************************************************/
-/* XPT_MEMDMA_MCPB :: GPC29_CURR_COUNTER_VAL :: COUNTER [31:00] */
-#define BCHP_XPT_MEMDMA_MCPB_GPC29_CURR_COUNTER_VAL_COUNTER_MASK 0xffffffff
-#define BCHP_XPT_MEMDMA_MCPB_GPC29_CURR_COUNTER_VAL_COUNTER_SHIFT 0
-#define BCHP_XPT_MEMDMA_MCPB_GPC29_CURR_COUNTER_VAL_COUNTER_DEFAULT 0x00000000
-
-/***************************************************************************
- *GPC29_PAUSE_0_31 - MCPB GPC29 Current pause value
- ***************************************************************************/
-/* XPT_MEMDMA_MCPB :: GPC29_PAUSE_0_31 :: GPC_PAUSE [31:00] */
-#define BCHP_XPT_MEMDMA_MCPB_GPC29_PAUSE_0_31_GPC_PAUSE_MASK 0xffffffff
-#define BCHP_XPT_MEMDMA_MCPB_GPC29_PAUSE_0_31_GPC_PAUSE_SHIFT 0
-#define BCHP_XPT_MEMDMA_MCPB_GPC29_PAUSE_0_31_GPC_PAUSE_DEFAULT 0x00000000
-
-/***************************************************************************
- *GPC30_CTRL - MCPB GPC30 Control information
- ***************************************************************************/
-/* XPT_MEMDMA_MCPB :: GPC30_CTRL :: FREE_RUN_OR_LOCKED_TIMEBASE [31:31] */
-#define BCHP_XPT_MEMDMA_MCPB_GPC30_CTRL_FREE_RUN_OR_LOCKED_TIMEBASE_MASK 0x80000000
-#define BCHP_XPT_MEMDMA_MCPB_GPC30_CTRL_FREE_RUN_OR_LOCKED_TIMEBASE_SHIFT 31
-#define BCHP_XPT_MEMDMA_MCPB_GPC30_CTRL_FREE_RUN_OR_LOCKED_TIMEBASE_DEFAULT 0x00000000
-
-/* XPT_MEMDMA_MCPB :: GPC30_CTRL :: TIMEBASE_SEL [30:26] */
-#define BCHP_XPT_MEMDMA_MCPB_GPC30_CTRL_TIMEBASE_SEL_MASK 0x7c000000
-#define BCHP_XPT_MEMDMA_MCPB_GPC30_CTRL_TIMEBASE_SEL_SHIFT 26
-#define BCHP_XPT_MEMDMA_MCPB_GPC30_CTRL_TIMEBASE_SEL_DEFAULT 0x00000000
-
-/* XPT_MEMDMA_MCPB :: GPC30_CTRL :: PACING_SPEED [25:23] */
-#define BCHP_XPT_MEMDMA_MCPB_GPC30_CTRL_PACING_SPEED_MASK 0x03800000
-#define BCHP_XPT_MEMDMA_MCPB_GPC30_CTRL_PACING_SPEED_SHIFT 23
-#define BCHP_XPT_MEMDMA_MCPB_GPC30_CTRL_PACING_SPEED_DEFAULT 0x00000000
-
-/* XPT_MEMDMA_MCPB :: GPC30_CTRL :: COUNTER_MODE [22:22] */
-#define BCHP_XPT_MEMDMA_MCPB_GPC30_CTRL_COUNTER_MODE_MASK 0x00400000
-#define BCHP_XPT_MEMDMA_MCPB_GPC30_CTRL_COUNTER_MODE_SHIFT 22
-#define BCHP_XPT_MEMDMA_MCPB_GPC30_CTRL_COUNTER_MODE_DEFAULT 0x00000000
-
-/* XPT_MEMDMA_MCPB :: GPC30_CTRL :: SKIP_REPEAT_MODE [21:21] */
-#define BCHP_XPT_MEMDMA_MCPB_GPC30_CTRL_SKIP_REPEAT_MODE_MASK 0x00200000
-#define BCHP_XPT_MEMDMA_MCPB_GPC30_CTRL_SKIP_REPEAT_MODE_SHIFT 21
-#define BCHP_XPT_MEMDMA_MCPB_GPC30_CTRL_SKIP_REPEAT_MODE_DEFAULT 0x00000000
-
-/* XPT_MEMDMA_MCPB :: GPC30_CTRL :: SKIP_REPEAT_EN [20:20] */
-#define BCHP_XPT_MEMDMA_MCPB_GPC30_CTRL_SKIP_REPEAT_EN_MASK 0x00100000
-#define BCHP_XPT_MEMDMA_MCPB_GPC30_CTRL_SKIP_REPEAT_EN_SHIFT 20
-#define BCHP_XPT_MEMDMA_MCPB_GPC30_CTRL_SKIP_REPEAT_EN_DEFAULT 0x00000000
-
-/* XPT_MEMDMA_MCPB :: GPC30_CTRL :: SKIP_REPEAT_COUNT [19:00] */
-#define BCHP_XPT_MEMDMA_MCPB_GPC30_CTRL_SKIP_REPEAT_COUNT_MASK 0x000fffff
-#define BCHP_XPT_MEMDMA_MCPB_GPC30_CTRL_SKIP_REPEAT_COUNT_SHIFT 0
-#define BCHP_XPT_MEMDMA_MCPB_GPC30_CTRL_SKIP_REPEAT_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *GPC30_CURR_COUNTER_VAL - MCPB GPC30 Current counter value
- ***************************************************************************/
-/* XPT_MEMDMA_MCPB :: GPC30_CURR_COUNTER_VAL :: COUNTER [31:00] */
-#define BCHP_XPT_MEMDMA_MCPB_GPC30_CURR_COUNTER_VAL_COUNTER_MASK 0xffffffff
-#define BCHP_XPT_MEMDMA_MCPB_GPC30_CURR_COUNTER_VAL_COUNTER_SHIFT 0
-#define BCHP_XPT_MEMDMA_MCPB_GPC30_CURR_COUNTER_VAL_COUNTER_DEFAULT 0x00000000
-
-/***************************************************************************
- *GPC30_PAUSE_0_31 - MCPB GPC30 Current pause value
- ***************************************************************************/
-/* XPT_MEMDMA_MCPB :: GPC30_PAUSE_0_31 :: GPC_PAUSE [31:00] */
-#define BCHP_XPT_MEMDMA_MCPB_GPC30_PAUSE_0_31_GPC_PAUSE_MASK 0xffffffff
-#define BCHP_XPT_MEMDMA_MCPB_GPC30_PAUSE_0_31_GPC_PAUSE_SHIFT 0
-#define BCHP_XPT_MEMDMA_MCPB_GPC30_PAUSE_0_31_GPC_PAUSE_DEFAULT 0x00000000
-
-/***************************************************************************
- *GPC31_CTRL - MCPB GPC31 Control information
- ***************************************************************************/
-/* XPT_MEMDMA_MCPB :: GPC31_CTRL :: FREE_RUN_OR_LOCKED_TIMEBASE [31:31] */
-#define BCHP_XPT_MEMDMA_MCPB_GPC31_CTRL_FREE_RUN_OR_LOCKED_TIMEBASE_MASK 0x80000000
-#define BCHP_XPT_MEMDMA_MCPB_GPC31_CTRL_FREE_RUN_OR_LOCKED_TIMEBASE_SHIFT 31
-#define BCHP_XPT_MEMDMA_MCPB_GPC31_CTRL_FREE_RUN_OR_LOCKED_TIMEBASE_DEFAULT 0x00000000
-
-/* XPT_MEMDMA_MCPB :: GPC31_CTRL :: TIMEBASE_SEL [30:26] */
-#define BCHP_XPT_MEMDMA_MCPB_GPC31_CTRL_TIMEBASE_SEL_MASK 0x7c000000
-#define BCHP_XPT_MEMDMA_MCPB_GPC31_CTRL_TIMEBASE_SEL_SHIFT 26
-#define BCHP_XPT_MEMDMA_MCPB_GPC31_CTRL_TIMEBASE_SEL_DEFAULT 0x00000000
-
-/* XPT_MEMDMA_MCPB :: GPC31_CTRL :: PACING_SPEED [25:23] */
-#define BCHP_XPT_MEMDMA_MCPB_GPC31_CTRL_PACING_SPEED_MASK 0x03800000
-#define BCHP_XPT_MEMDMA_MCPB_GPC31_CTRL_PACING_SPEED_SHIFT 23
-#define BCHP_XPT_MEMDMA_MCPB_GPC31_CTRL_PACING_SPEED_DEFAULT 0x00000000
-
-/* XPT_MEMDMA_MCPB :: GPC31_CTRL :: COUNTER_MODE [22:22] */
-#define BCHP_XPT_MEMDMA_MCPB_GPC31_CTRL_COUNTER_MODE_MASK 0x00400000
-#define BCHP_XPT_MEMDMA_MCPB_GPC31_CTRL_COUNTER_MODE_SHIFT 22
-#define BCHP_XPT_MEMDMA_MCPB_GPC31_CTRL_COUNTER_MODE_DEFAULT 0x00000000
-
-/* XPT_MEMDMA_MCPB :: GPC31_CTRL :: SKIP_REPEAT_MODE [21:21] */
-#define BCHP_XPT_MEMDMA_MCPB_GPC31_CTRL_SKIP_REPEAT_MODE_MASK 0x00200000
-#define BCHP_XPT_MEMDMA_MCPB_GPC31_CTRL_SKIP_REPEAT_MODE_SHIFT 21
-#define BCHP_XPT_MEMDMA_MCPB_GPC31_CTRL_SKIP_REPEAT_MODE_DEFAULT 0x00000000
-
-/* XPT_MEMDMA_MCPB :: GPC31_CTRL :: SKIP_REPEAT_EN [20:20] */
-#define BCHP_XPT_MEMDMA_MCPB_GPC31_CTRL_SKIP_REPEAT_EN_MASK 0x00100000
-#define BCHP_XPT_MEMDMA_MCPB_GPC31_CTRL_SKIP_REPEAT_EN_SHIFT 20
-#define BCHP_XPT_MEMDMA_MCPB_GPC31_CTRL_SKIP_REPEAT_EN_DEFAULT 0x00000000
-
-/* XPT_MEMDMA_MCPB :: GPC31_CTRL :: SKIP_REPEAT_COUNT [19:00] */
-#define BCHP_XPT_MEMDMA_MCPB_GPC31_CTRL_SKIP_REPEAT_COUNT_MASK 0x000fffff
-#define BCHP_XPT_MEMDMA_MCPB_GPC31_CTRL_SKIP_REPEAT_COUNT_SHIFT 0
-#define BCHP_XPT_MEMDMA_MCPB_GPC31_CTRL_SKIP_REPEAT_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *GPC31_CURR_COUNTER_VAL - MCPB GPC31 Current counter value
- ***************************************************************************/
-/* XPT_MEMDMA_MCPB :: GPC31_CURR_COUNTER_VAL :: COUNTER [31:00] */
-#define BCHP_XPT_MEMDMA_MCPB_GPC31_CURR_COUNTER_VAL_COUNTER_MASK 0xffffffff
-#define BCHP_XPT_MEMDMA_MCPB_GPC31_CURR_COUNTER_VAL_COUNTER_SHIFT 0
-#define BCHP_XPT_MEMDMA_MCPB_GPC31_CURR_COUNTER_VAL_COUNTER_DEFAULT 0x00000000
-
-/***************************************************************************
- *GPC31_PAUSE_0_31 - MCPB GPC31 Current pause value
- ***************************************************************************/
-/* XPT_MEMDMA_MCPB :: GPC31_PAUSE_0_31 :: GPC_PAUSE [31:00] */
-#define BCHP_XPT_MEMDMA_MCPB_GPC31_PAUSE_0_31_GPC_PAUSE_MASK 0xffffffff
-#define BCHP_XPT_MEMDMA_MCPB_GPC31_PAUSE_0_31_GPC_PAUSE_SHIFT 0
-#define BCHP_XPT_MEMDMA_MCPB_GPC31_PAUSE_0_31_GPC_PAUSE_DEFAULT 0x00000000
-
-/***************************************************************************
- *TMEU_ARB_DELAY - MCPB Arbitration delay value
- ***************************************************************************/
-/* XPT_MEMDMA_MCPB :: TMEU_ARB_DELAY :: reserved0 [31:16] */
-#define BCHP_XPT_MEMDMA_MCPB_TMEU_ARB_DELAY_reserved0_MASK 0xffff0000
-#define BCHP_XPT_MEMDMA_MCPB_TMEU_ARB_DELAY_reserved0_SHIFT 16
-
-/* XPT_MEMDMA_MCPB :: TMEU_ARB_DELAY :: ARB_DELAY [15:00] */
-#define BCHP_XPT_MEMDMA_MCPB_TMEU_ARB_DELAY_ARB_DELAY_MASK 0x0000ffff
-#define BCHP_XPT_MEMDMA_MCPB_TMEU_ARB_DELAY_ARB_DELAY_SHIFT 0
-#define BCHP_XPT_MEMDMA_MCPB_TMEU_ARB_DELAY_ARB_DELAY_DEFAULT 0x000000c8
-
-/***************************************************************************
- *DMA_MEM_ADDR_START - Address start for CFG DMA SP memory
- ***************************************************************************/
-/* XPT_MEMDMA_MCPB :: DMA_MEM_ADDR_START :: reserved0 [31:08] */
-#define BCHP_XPT_MEMDMA_MCPB_DMA_MEM_ADDR_START_reserved0_MASK 0xffffff00
-#define BCHP_XPT_MEMDMA_MCPB_DMA_MEM_ADDR_START_reserved0_SHIFT 8
-
-/* XPT_MEMDMA_MCPB :: DMA_MEM_ADDR_START :: ADDRESS [07:00] */
-#define BCHP_XPT_MEMDMA_MCPB_DMA_MEM_ADDR_START_ADDRESS_MASK 0x000000ff
-#define BCHP_XPT_MEMDMA_MCPB_DMA_MEM_ADDR_START_ADDRESS_SHIFT 0
-#define BCHP_XPT_MEMDMA_MCPB_DMA_MEM_ADDR_START_ADDRESS_DEFAULT 0x00000000
-
-/***************************************************************************
- *BBUFF_MEM_ADDR_START - Address start for CFG BBUFF memory
- ***************************************************************************/
-/* XPT_MEMDMA_MCPB :: BBUFF_MEM_ADDR_START :: reserved0 [31:08] */
-#define BCHP_XPT_MEMDMA_MCPB_BBUFF_MEM_ADDR_START_reserved0_MASK 0xffffff00
-#define BCHP_XPT_MEMDMA_MCPB_BBUFF_MEM_ADDR_START_reserved0_SHIFT 8
-
-/* XPT_MEMDMA_MCPB :: BBUFF_MEM_ADDR_START :: ADDRESS [07:00] */
-#define BCHP_XPT_MEMDMA_MCPB_BBUFF_MEM_ADDR_START_ADDRESS_MASK 0x000000ff
-#define BCHP_XPT_MEMDMA_MCPB_BBUFF_MEM_ADDR_START_ADDRESS_SHIFT 0
-#define BCHP_XPT_MEMDMA_MCPB_BBUFF_MEM_ADDR_START_ADDRESS_DEFAULT 0x00000032
-
-/***************************************************************************
- *TMEU_MEM_ADDR_START - Address start for TMEU memory
- ***************************************************************************/
-/* XPT_MEMDMA_MCPB :: TMEU_MEM_ADDR_START :: reserved0 [31:08] */
-#define BCHP_XPT_MEMDMA_MCPB_TMEU_MEM_ADDR_START_reserved0_MASK 0xffffff00
-#define BCHP_XPT_MEMDMA_MCPB_TMEU_MEM_ADDR_START_reserved0_SHIFT 8
-
-/* XPT_MEMDMA_MCPB :: TMEU_MEM_ADDR_START :: ADDRESS [07:00] */
-#define BCHP_XPT_MEMDMA_MCPB_TMEU_MEM_ADDR_START_ADDRESS_MASK 0x000000ff
-#define BCHP_XPT_MEMDMA_MCPB_TMEU_MEM_ADDR_START_ADDRESS_SHIFT 0
-#define BCHP_XPT_MEMDMA_MCPB_TMEU_MEM_ADDR_START_ADDRESS_DEFAULT 0x00000038
-
-/***************************************************************************
- *DCPM_MEM_ADDR_START - Address start for DCPM memory
- ***************************************************************************/
-/* XPT_MEMDMA_MCPB :: DCPM_MEM_ADDR_START :: reserved0 [31:08] */
-#define BCHP_XPT_MEMDMA_MCPB_DCPM_MEM_ADDR_START_reserved0_MASK 0xffffff00
-#define BCHP_XPT_MEMDMA_MCPB_DCPM_MEM_ADDR_START_reserved0_SHIFT 8
-
-/* XPT_MEMDMA_MCPB :: DCPM_MEM_ADDR_START :: ADDRESS [07:00] */
-#define BCHP_XPT_MEMDMA_MCPB_DCPM_MEM_ADDR_START_ADDRESS_MASK 0x000000ff
-#define BCHP_XPT_MEMDMA_MCPB_DCPM_MEM_ADDR_START_ADDRESS_SHIFT 0
-#define BCHP_XPT_MEMDMA_MCPB_DCPM_MEM_ADDR_START_ADDRESS_DEFAULT 0x00000048
-
-/***************************************************************************
- *PER_CH_MEM_ADDR_END - Address end in configuration memory for each channel
- ***************************************************************************/
-/* XPT_MEMDMA_MCPB :: PER_CH_MEM_ADDR_END :: reserved0 [31:08] */
-#define BCHP_XPT_MEMDMA_MCPB_PER_CH_MEM_ADDR_END_reserved0_MASK 0xffffff00
-#define BCHP_XPT_MEMDMA_MCPB_PER_CH_MEM_ADDR_END_reserved0_SHIFT 8
-
-/* XPT_MEMDMA_MCPB :: PER_CH_MEM_ADDR_END :: ADDRESS [07:00] */
-#define BCHP_XPT_MEMDMA_MCPB_PER_CH_MEM_ADDR_END_ADDRESS_MASK 0x000000ff
-#define BCHP_XPT_MEMDMA_MCPB_PER_CH_MEM_ADDR_END_ADDRESS_SHIFT 0
-#define BCHP_XPT_MEMDMA_MCPB_PER_CH_MEM_ADDR_END_ADDRESS_DEFAULT 0x00000058
-
-/***************************************************************************
- *GLOBAL_CTRL_SIGNALS - Global control signals
- ***************************************************************************/
-/* XPT_MEMDMA_MCPB :: GLOBAL_CTRL_SIGNALS :: reserved_for_padding0 [31:01] */
-#define BCHP_XPT_MEMDMA_MCPB_GLOBAL_CTRL_SIGNALS_reserved_for_padding0_MASK 0xfffffffe
-#define BCHP_XPT_MEMDMA_MCPB_GLOBAL_CTRL_SIGNALS_reserved_for_padding0_SHIFT 1
-
-/* XPT_MEMDMA_MCPB :: GLOBAL_CTRL_SIGNALS :: CS_EN_ALWAYS [00:00] */
-#define BCHP_XPT_MEMDMA_MCPB_GLOBAL_CTRL_SIGNALS_CS_EN_ALWAYS_MASK 0x00000001
-#define BCHP_XPT_MEMDMA_MCPB_GLOBAL_CTRL_SIGNALS_CS_EN_ALWAYS_SHIFT 0
-#define BCHP_XPT_MEMDMA_MCPB_GLOBAL_CTRL_SIGNALS_CS_EN_ALWAYS_DEFAULT 0x00000000
-
-/***************************************************************************
- *MASK_CLEAR_PAUSE_AT_DESC_END_FROM_MEMDMA_SET_CLEAR - Set and clear of Pause at descriptor end clear mask status bit
- ***************************************************************************/
-/* XPT_MEMDMA_MCPB :: MASK_CLEAR_PAUSE_AT_DESC_END_FROM_MEMDMA_SET_CLEAR :: reserved_for_padding0 [31:09] */
-#define BCHP_XPT_MEMDMA_MCPB_MASK_CLEAR_PAUSE_AT_DESC_END_FROM_MEMDMA_SET_CLEAR_reserved_for_padding0_MASK 0xfffffe00
-#define BCHP_XPT_MEMDMA_MCPB_MASK_CLEAR_PAUSE_AT_DESC_END_FROM_MEMDMA_SET_CLEAR_reserved_for_padding0_SHIFT 9
-
-/* XPT_MEMDMA_MCPB :: MASK_CLEAR_PAUSE_AT_DESC_END_FROM_MEMDMA_SET_CLEAR :: SET_CLEAR [08:08] */
-#define BCHP_XPT_MEMDMA_MCPB_MASK_CLEAR_PAUSE_AT_DESC_END_FROM_MEMDMA_SET_CLEAR_SET_CLEAR_MASK 0x00000100
-#define BCHP_XPT_MEMDMA_MCPB_MASK_CLEAR_PAUSE_AT_DESC_END_FROM_MEMDMA_SET_CLEAR_SET_CLEAR_SHIFT 8
-#define BCHP_XPT_MEMDMA_MCPB_MASK_CLEAR_PAUSE_AT_DESC_END_FROM_MEMDMA_SET_CLEAR_SET_CLEAR_DEFAULT 0x00000000
-
-/* XPT_MEMDMA_MCPB :: MASK_CLEAR_PAUSE_AT_DESC_END_FROM_MEMDMA_SET_CLEAR :: MCPB_CHANNEL_NUM [07:00] */
-#define BCHP_XPT_MEMDMA_MCPB_MASK_CLEAR_PAUSE_AT_DESC_END_FROM_MEMDMA_SET_CLEAR_MCPB_CHANNEL_NUM_MASK 0x000000ff
-#define BCHP_XPT_MEMDMA_MCPB_MASK_CLEAR_PAUSE_AT_DESC_END_FROM_MEMDMA_SET_CLEAR_MCPB_CHANNEL_NUM_SHIFT 0
-#define BCHP_XPT_MEMDMA_MCPB_MASK_CLEAR_PAUSE_AT_DESC_END_FROM_MEMDMA_SET_CLEAR_MCPB_CHANNEL_NUM_DEFAULT 0x00000000
-
-/***************************************************************************
- *MASK_CLEAR_PAUSE_AT_DESC_END_FROM_MEMDMA_STATUS_0_31 - Pause at descriptor end clear mask status bit for all PB channels
- ***************************************************************************/
-/* XPT_MEMDMA_MCPB :: MASK_CLEAR_PAUSE_AT_DESC_END_FROM_MEMDMA_STATUS_0_31 :: MASK_CLEAR_PAUSE_AT_DESC_END_FROM_MEMDMA_STATUS [31:00] */
-#define BCHP_XPT_MEMDMA_MCPB_MASK_CLEAR_PAUSE_AT_DESC_END_FROM_MEMDMA_STATUS_0_31_MASK_CLEAR_PAUSE_AT_DESC_END_FROM_MEMDMA_STATUS_MASK 0xffffffff
-#define BCHP_XPT_MEMDMA_MCPB_MASK_CLEAR_PAUSE_AT_DESC_END_FROM_MEMDMA_STATUS_0_31_MASK_CLEAR_PAUSE_AT_DESC_END_FROM_MEMDMA_STATUS_SHIFT 0
-#define BCHP_XPT_MEMDMA_MCPB_MASK_CLEAR_PAUSE_AT_DESC_END_FROM_MEMDMA_STATUS_0_31_MASK_CLEAR_PAUSE_AT_DESC_END_FROM_MEMDMA_STATUS_DEFAULT 0x00000000
-
-/***************************************************************************
- *MASK_CLEAR_PAUSE_AT_DESC_END_FROM_HOST_SET_CLEAR - Set and clear of Pause at descriptor end clear mask status bit
- ***************************************************************************/
-/* XPT_MEMDMA_MCPB :: MASK_CLEAR_PAUSE_AT_DESC_END_FROM_HOST_SET_CLEAR :: reserved_for_padding0 [31:09] */
-#define BCHP_XPT_MEMDMA_MCPB_MASK_CLEAR_PAUSE_AT_DESC_END_FROM_HOST_SET_CLEAR_reserved_for_padding0_MASK 0xfffffe00
-#define BCHP_XPT_MEMDMA_MCPB_MASK_CLEAR_PAUSE_AT_DESC_END_FROM_HOST_SET_CLEAR_reserved_for_padding0_SHIFT 9
-
-/* XPT_MEMDMA_MCPB :: MASK_CLEAR_PAUSE_AT_DESC_END_FROM_HOST_SET_CLEAR :: SET_CLEAR [08:08] */
-#define BCHP_XPT_MEMDMA_MCPB_MASK_CLEAR_PAUSE_AT_DESC_END_FROM_HOST_SET_CLEAR_SET_CLEAR_MASK 0x00000100
-#define BCHP_XPT_MEMDMA_MCPB_MASK_CLEAR_PAUSE_AT_DESC_END_FROM_HOST_SET_CLEAR_SET_CLEAR_SHIFT 8
-#define BCHP_XPT_MEMDMA_MCPB_MASK_CLEAR_PAUSE_AT_DESC_END_FROM_HOST_SET_CLEAR_SET_CLEAR_DEFAULT 0x00000000
-
-/* XPT_MEMDMA_MCPB :: MASK_CLEAR_PAUSE_AT_DESC_END_FROM_HOST_SET_CLEAR :: MCPB_CHANNEL_NUM [07:00] */
-#define BCHP_XPT_MEMDMA_MCPB_MASK_CLEAR_PAUSE_AT_DESC_END_FROM_HOST_SET_CLEAR_MCPB_CHANNEL_NUM_MASK 0x000000ff
-#define BCHP_XPT_MEMDMA_MCPB_MASK_CLEAR_PAUSE_AT_DESC_END_FROM_HOST_SET_CLEAR_MCPB_CHANNEL_NUM_SHIFT 0
-#define BCHP_XPT_MEMDMA_MCPB_MASK_CLEAR_PAUSE_AT_DESC_END_FROM_HOST_SET_CLEAR_MCPB_CHANNEL_NUM_DEFAULT 0x00000000
-
-/***************************************************************************
- *MASK_CLEAR_PAUSE_AT_DESC_END_FROM_HOST_STATUS_0_31 - Pause at descriptor end clear mask status bit for all PB channels
- ***************************************************************************/
-/* XPT_MEMDMA_MCPB :: MASK_CLEAR_PAUSE_AT_DESC_END_FROM_HOST_STATUS_0_31 :: MASK_CLEAR_PAUSE_AT_DESC_END_FROM_HOST_STATUS [31:00] */
-#define BCHP_XPT_MEMDMA_MCPB_MASK_CLEAR_PAUSE_AT_DESC_END_FROM_HOST_STATUS_0_31_MASK_CLEAR_PAUSE_AT_DESC_END_FROM_HOST_STATUS_MASK 0xffffffff
-#define BCHP_XPT_MEMDMA_MCPB_MASK_CLEAR_PAUSE_AT_DESC_END_FROM_HOST_STATUS_0_31_MASK_CLEAR_PAUSE_AT_DESC_END_FROM_HOST_STATUS_SHIFT 0
-#define BCHP_XPT_MEMDMA_MCPB_MASK_CLEAR_PAUSE_AT_DESC_END_FROM_HOST_STATUS_0_31_MASK_CLEAR_PAUSE_AT_DESC_END_FROM_HOST_STATUS_DEFAULT 0x00000000
-
-/***************************************************************************
- *DESCRIPTOR_LESS_MODE_SET_CLEAR - Set and clear for DESCRIPTOR_LESS_MODE_STATUS bit
- ***************************************************************************/
-/* XPT_MEMDMA_MCPB :: DESCRIPTOR_LESS_MODE_SET_CLEAR :: reserved0 [31:09] */
-#define BCHP_XPT_MEMDMA_MCPB_DESCRIPTOR_LESS_MODE_SET_CLEAR_reserved0_MASK 0xfffffe00
-#define BCHP_XPT_MEMDMA_MCPB_DESCRIPTOR_LESS_MODE_SET_CLEAR_reserved0_SHIFT 9
-
-/* XPT_MEMDMA_MCPB :: DESCRIPTOR_LESS_MODE_SET_CLEAR :: SET_CLEAR [08:08] */
-#define BCHP_XPT_MEMDMA_MCPB_DESCRIPTOR_LESS_MODE_SET_CLEAR_SET_CLEAR_MASK 0x00000100
-#define BCHP_XPT_MEMDMA_MCPB_DESCRIPTOR_LESS_MODE_SET_CLEAR_SET_CLEAR_SHIFT 8
-#define BCHP_XPT_MEMDMA_MCPB_DESCRIPTOR_LESS_MODE_SET_CLEAR_SET_CLEAR_DEFAULT 0x00000000
-
-/* XPT_MEMDMA_MCPB :: DESCRIPTOR_LESS_MODE_SET_CLEAR :: MCPB_CHANNEL_NUM [07:00] */
-#define BCHP_XPT_MEMDMA_MCPB_DESCRIPTOR_LESS_MODE_SET_CLEAR_MCPB_CHANNEL_NUM_MASK 0x000000ff
-#define BCHP_XPT_MEMDMA_MCPB_DESCRIPTOR_LESS_MODE_SET_CLEAR_MCPB_CHANNEL_NUM_SHIFT 0
-#define BCHP_XPT_MEMDMA_MCPB_DESCRIPTOR_LESS_MODE_SET_CLEAR_MCPB_CHANNEL_NUM_DEFAULT 0x00000000
-
-/***************************************************************************
- *DESCRIPTOR_LESS_MODE_STATUS_0_31 - Descriptorless status for all PB channels
- ***************************************************************************/
-/* XPT_MEMDMA_MCPB :: DESCRIPTOR_LESS_MODE_STATUS_0_31 :: DESCRIPTOR_LESS_MODE_STATUS [31:00] */
-#define BCHP_XPT_MEMDMA_MCPB_DESCRIPTOR_LESS_MODE_STATUS_0_31_DESCRIPTOR_LESS_MODE_STATUS_MASK 0xffffffff
-#define BCHP_XPT_MEMDMA_MCPB_DESCRIPTOR_LESS_MODE_STATUS_0_31_DESCRIPTOR_LESS_MODE_STATUS_SHIFT 0
-#define BCHP_XPT_MEMDMA_MCPB_DESCRIPTOR_LESS_MODE_STATUS_0_31_DESCRIPTOR_LESS_MODE_STATUS_DEFAULT 0x00000000
-
-/***************************************************************************
- *ARBITER_ZERO_BYTE_TRANS_PRIORITY_SET_CLEAR - Set and clear for Zero Byte Transaction Priority bit
- ***************************************************************************/
-/* XPT_MEMDMA_MCPB :: ARBITER_ZERO_BYTE_TRANS_PRIORITY_SET_CLEAR :: reserved_for_padding0 [31:09] */
-#define BCHP_XPT_MEMDMA_MCPB_ARBITER_ZERO_BYTE_TRANS_PRIORITY_SET_CLEAR_reserved_for_padding0_MASK 0xfffffe00
-#define BCHP_XPT_MEMDMA_MCPB_ARBITER_ZERO_BYTE_TRANS_PRIORITY_SET_CLEAR_reserved_for_padding0_SHIFT 9
-
-/* XPT_MEMDMA_MCPB :: ARBITER_ZERO_BYTE_TRANS_PRIORITY_SET_CLEAR :: SET_CLEAR [08:08] */
-#define BCHP_XPT_MEMDMA_MCPB_ARBITER_ZERO_BYTE_TRANS_PRIORITY_SET_CLEAR_SET_CLEAR_MASK 0x00000100
-#define BCHP_XPT_MEMDMA_MCPB_ARBITER_ZERO_BYTE_TRANS_PRIORITY_SET_CLEAR_SET_CLEAR_SHIFT 8
-#define BCHP_XPT_MEMDMA_MCPB_ARBITER_ZERO_BYTE_TRANS_PRIORITY_SET_CLEAR_SET_CLEAR_DEFAULT 0x00000000
-
-/* XPT_MEMDMA_MCPB :: ARBITER_ZERO_BYTE_TRANS_PRIORITY_SET_CLEAR :: MCPB_CHANNEL_NUM [07:00] */
-#define BCHP_XPT_MEMDMA_MCPB_ARBITER_ZERO_BYTE_TRANS_PRIORITY_SET_CLEAR_MCPB_CHANNEL_NUM_MASK 0x000000ff
-#define BCHP_XPT_MEMDMA_MCPB_ARBITER_ZERO_BYTE_TRANS_PRIORITY_SET_CLEAR_MCPB_CHANNEL_NUM_SHIFT 0
-#define BCHP_XPT_MEMDMA_MCPB_ARBITER_ZERO_BYTE_TRANS_PRIORITY_SET_CLEAR_MCPB_CHANNEL_NUM_DEFAULT 0x00000000
-
-/***************************************************************************
- *ARBITER_ZERO_BYTE_TRANS_PRIORITY_STATUS_0_31 - Zero Byte Transaction Priority status for all PB channels
- ***************************************************************************/
-/* XPT_MEMDMA_MCPB :: ARBITER_ZERO_BYTE_TRANS_PRIORITY_STATUS_0_31 :: ARBITER_ZERO_BYTE_TRANS_PRIORITY_STATUS [31:00] */
-#define BCHP_XPT_MEMDMA_MCPB_ARBITER_ZERO_BYTE_TRANS_PRIORITY_STATUS_0_31_ARBITER_ZERO_BYTE_TRANS_PRIORITY_STATUS_MASK 0xffffffff
-#define BCHP_XPT_MEMDMA_MCPB_ARBITER_ZERO_BYTE_TRANS_PRIORITY_STATUS_0_31_ARBITER_ZERO_BYTE_TRANS_PRIORITY_STATUS_SHIFT 0
-#define BCHP_XPT_MEMDMA_MCPB_ARBITER_ZERO_BYTE_TRANS_PRIORITY_STATUS_0_31_ARBITER_ZERO_BYTE_TRANS_PRIORITY_STATUS_DEFAULT 0xffffffff
-
-/***************************************************************************
- *ARBITER_SEND_DCP_ONLY_TRANS_AS_HIGH_PRIORITY_SET_CLEAR - Set and clear for DCP-only-transaction priority bit
- ***************************************************************************/
-/* XPT_MEMDMA_MCPB :: ARBITER_SEND_DCP_ONLY_TRANS_AS_HIGH_PRIORITY_SET_CLEAR :: reserved_for_padding0 [31:09] */
-#define BCHP_XPT_MEMDMA_MCPB_ARBITER_SEND_DCP_ONLY_TRANS_AS_HIGH_PRIORITY_SET_CLEAR_reserved_for_padding0_MASK 0xfffffe00
-#define BCHP_XPT_MEMDMA_MCPB_ARBITER_SEND_DCP_ONLY_TRANS_AS_HIGH_PRIORITY_SET_CLEAR_reserved_for_padding0_SHIFT 9
-
-/* XPT_MEMDMA_MCPB :: ARBITER_SEND_DCP_ONLY_TRANS_AS_HIGH_PRIORITY_SET_CLEAR :: SET_CLEAR [08:08] */
-#define BCHP_XPT_MEMDMA_MCPB_ARBITER_SEND_DCP_ONLY_TRANS_AS_HIGH_PRIORITY_SET_CLEAR_SET_CLEAR_MASK 0x00000100
-#define BCHP_XPT_MEMDMA_MCPB_ARBITER_SEND_DCP_ONLY_TRANS_AS_HIGH_PRIORITY_SET_CLEAR_SET_CLEAR_SHIFT 8
-#define BCHP_XPT_MEMDMA_MCPB_ARBITER_SEND_DCP_ONLY_TRANS_AS_HIGH_PRIORITY_SET_CLEAR_SET_CLEAR_DEFAULT 0x00000000
-
-/* XPT_MEMDMA_MCPB :: ARBITER_SEND_DCP_ONLY_TRANS_AS_HIGH_PRIORITY_SET_CLEAR :: MCPB_CHANNEL_NUM [07:00] */
-#define BCHP_XPT_MEMDMA_MCPB_ARBITER_SEND_DCP_ONLY_TRANS_AS_HIGH_PRIORITY_SET_CLEAR_MCPB_CHANNEL_NUM_MASK 0x000000ff
-#define BCHP_XPT_MEMDMA_MCPB_ARBITER_SEND_DCP_ONLY_TRANS_AS_HIGH_PRIORITY_SET_CLEAR_MCPB_CHANNEL_NUM_SHIFT 0
-#define BCHP_XPT_MEMDMA_MCPB_ARBITER_SEND_DCP_ONLY_TRANS_AS_HIGH_PRIORITY_SET_CLEAR_MCPB_CHANNEL_NUM_DEFAULT 0x00000000
-
-/***************************************************************************
- *ARBITER_SEND_DCP_ONLY_TRANS_AS_HIGH_PRIORITY_STATUS_0_31 - DCP-only-transaction priority status for all PB channels
- ***************************************************************************/
-/* XPT_MEMDMA_MCPB :: ARBITER_SEND_DCP_ONLY_TRANS_AS_HIGH_PRIORITY_STATUS_0_31 :: ARBITER_SEND_DCP_ONLY_TRANS_AS_HIGH_PRIORITY_STATUS [31:00] */
-#define BCHP_XPT_MEMDMA_MCPB_ARBITER_SEND_DCP_ONLY_TRANS_AS_HIGH_PRIORITY_STATUS_0_31_ARBITER_SEND_DCP_ONLY_TRANS_AS_HIGH_PRIORITY_STATUS_MASK 0xffffffff
-#define BCHP_XPT_MEMDMA_MCPB_ARBITER_SEND_DCP_ONLY_TRANS_AS_HIGH_PRIORITY_STATUS_0_31_ARBITER_SEND_DCP_ONLY_TRANS_AS_HIGH_PRIORITY_STATUS_SHIFT 0
-#define BCHP_XPT_MEMDMA_MCPB_ARBITER_SEND_DCP_ONLY_TRANS_AS_HIGH_PRIORITY_STATUS_0_31_ARBITER_SEND_DCP_ONLY_TRANS_AS_HIGH_PRIORITY_STATUS_DEFAULT 0xffffffff
-
-/***************************************************************************
- *SEC_OUTPUT_PIPE_PACKET_GAPPER - Packet gapper controls for SECURITY O/P pipe
- ***************************************************************************/
-/* XPT_MEMDMA_MCPB :: SEC_OUTPUT_PIPE_PACKET_GAPPER :: BLOCK_OUT_COUNT [31:00] */
-#define BCHP_XPT_MEMDMA_MCPB_SEC_OUTPUT_PIPE_PACKET_GAPPER_BLOCK_OUT_COUNT_MASK 0xffffffff
-#define BCHP_XPT_MEMDMA_MCPB_SEC_OUTPUT_PIPE_PACKET_GAPPER_BLOCK_OUT_COUNT_SHIFT 0
-#define BCHP_XPT_MEMDMA_MCPB_SEC_OUTPUT_PIPE_PACKET_GAPPER_BLOCK_OUT_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *MANUAL_MODE_SEL_0 - Manual mode select signals Selection 0
- ***************************************************************************/
-/* XPT_MEMDMA_MCPB :: MANUAL_MODE_SEL_0 :: reserved0 [31:19] */
-#define BCHP_XPT_MEMDMA_MCPB_MANUAL_MODE_SEL_0_reserved0_MASK 0xfff80000
-#define BCHP_XPT_MEMDMA_MCPB_MANUAL_MODE_SEL_0_reserved0_SHIFT 19
-
-/* XPT_MEMDMA_MCPB :: MANUAL_MODE_SEL_0 :: FORCE_TS_CONFIG_T4 [18:18] */
-#define BCHP_XPT_MEMDMA_MCPB_MANUAL_MODE_SEL_0_FORCE_TS_CONFIG_T4_MASK 0x00040000
-#define BCHP_XPT_MEMDMA_MCPB_MANUAL_MODE_SEL_0_FORCE_TS_CONFIG_T4_SHIFT 18
-#define BCHP_XPT_MEMDMA_MCPB_MANUAL_MODE_SEL_0_FORCE_TS_CONFIG_T4_DEFAULT 0x00000000
-
-/* XPT_MEMDMA_MCPB :: MANUAL_MODE_SEL_0 :: PUSH_RESIDUAL_BYTES_T4 [17:17] */
-#define BCHP_XPT_MEMDMA_MCPB_MANUAL_MODE_SEL_0_PUSH_RESIDUAL_BYTES_T4_MASK 0x00020000
-#define BCHP_XPT_MEMDMA_MCPB_MANUAL_MODE_SEL_0_PUSH_RESIDUAL_BYTES_T4_SHIFT 17
-#define BCHP_XPT_MEMDMA_MCPB_MANUAL_MODE_SEL_0_PUSH_RESIDUAL_BYTES_T4_DEFAULT 0x00000000
-
-/* XPT_MEMDMA_MCPB :: MANUAL_MODE_SEL_0 :: RESET_SP_PARSER_T4 [16:16] */
-#define BCHP_XPT_MEMDMA_MCPB_MANUAL_MODE_SEL_0_RESET_SP_PARSER_T4_MASK 0x00010000
-#define BCHP_XPT_MEMDMA_MCPB_MANUAL_MODE_SEL_0_RESET_SP_PARSER_T4_SHIFT 16
-#define BCHP_XPT_MEMDMA_MCPB_MANUAL_MODE_SEL_0_RESET_SP_PARSER_T4_DEFAULT 0x00000000
-
-/* XPT_MEMDMA_MCPB :: MANUAL_MODE_SEL_0 :: reserved1 [15:15] */
-#define BCHP_XPT_MEMDMA_MCPB_MANUAL_MODE_SEL_0_reserved1_MASK 0x00008000
-#define BCHP_XPT_MEMDMA_MCPB_MANUAL_MODE_SEL_0_reserved1_SHIFT 15
-
-/* XPT_MEMDMA_MCPB :: MANUAL_MODE_SEL_0 :: FORCE_TS_CONFIG_T3 [14:14] */
-#define BCHP_XPT_MEMDMA_MCPB_MANUAL_MODE_SEL_0_FORCE_TS_CONFIG_T3_MASK 0x00004000
-#define BCHP_XPT_MEMDMA_MCPB_MANUAL_MODE_SEL_0_FORCE_TS_CONFIG_T3_SHIFT 14
-#define BCHP_XPT_MEMDMA_MCPB_MANUAL_MODE_SEL_0_FORCE_TS_CONFIG_T3_DEFAULT 0x00000000
-
-/* XPT_MEMDMA_MCPB :: MANUAL_MODE_SEL_0 :: PUSH_RESIDUAL_BYTES_T3 [13:13] */
-#define BCHP_XPT_MEMDMA_MCPB_MANUAL_MODE_SEL_0_PUSH_RESIDUAL_BYTES_T3_MASK 0x00002000
-#define BCHP_XPT_MEMDMA_MCPB_MANUAL_MODE_SEL_0_PUSH_RESIDUAL_BYTES_T3_SHIFT 13
-#define BCHP_XPT_MEMDMA_MCPB_MANUAL_MODE_SEL_0_PUSH_RESIDUAL_BYTES_T3_DEFAULT 0x00000000
-
-/* XPT_MEMDMA_MCPB :: MANUAL_MODE_SEL_0 :: RESET_SP_PARSER_T3 [12:12] */
-#define BCHP_XPT_MEMDMA_MCPB_MANUAL_MODE_SEL_0_RESET_SP_PARSER_T3_MASK 0x00001000
-#define BCHP_XPT_MEMDMA_MCPB_MANUAL_MODE_SEL_0_RESET_SP_PARSER_T3_SHIFT 12
-#define BCHP_XPT_MEMDMA_MCPB_MANUAL_MODE_SEL_0_RESET_SP_PARSER_T3_DEFAULT 0x00000000
-
-/* XPT_MEMDMA_MCPB :: MANUAL_MODE_SEL_0 :: reserved2 [11:11] */
-#define BCHP_XPT_MEMDMA_MCPB_MANUAL_MODE_SEL_0_reserved2_MASK 0x00000800
-#define BCHP_XPT_MEMDMA_MCPB_MANUAL_MODE_SEL_0_reserved2_SHIFT 11
-
-/* XPT_MEMDMA_MCPB :: MANUAL_MODE_SEL_0 :: FORCE_TS_CONFIG_T2 [10:10] */
-#define BCHP_XPT_MEMDMA_MCPB_MANUAL_MODE_SEL_0_FORCE_TS_CONFIG_T2_MASK 0x00000400
-#define BCHP_XPT_MEMDMA_MCPB_MANUAL_MODE_SEL_0_FORCE_TS_CONFIG_T2_SHIFT 10
-#define BCHP_XPT_MEMDMA_MCPB_MANUAL_MODE_SEL_0_FORCE_TS_CONFIG_T2_DEFAULT 0x00000000
-
-/* XPT_MEMDMA_MCPB :: MANUAL_MODE_SEL_0 :: PUSH_RESIDUAL_BYTES_T2 [09:09] */
-#define BCHP_XPT_MEMDMA_MCPB_MANUAL_MODE_SEL_0_PUSH_RESIDUAL_BYTES_T2_MASK 0x00000200
-#define BCHP_XPT_MEMDMA_MCPB_MANUAL_MODE_SEL_0_PUSH_RESIDUAL_BYTES_T2_SHIFT 9
-#define BCHP_XPT_MEMDMA_MCPB_MANUAL_MODE_SEL_0_PUSH_RESIDUAL_BYTES_T2_DEFAULT 0x00000000
-
-/* XPT_MEMDMA_MCPB :: MANUAL_MODE_SEL_0 :: RESET_SP_PARSER_T2 [08:08] */
-#define BCHP_XPT_MEMDMA_MCPB_MANUAL_MODE_SEL_0_RESET_SP_PARSER_T2_MASK 0x00000100
-#define BCHP_XPT_MEMDMA_MCPB_MANUAL_MODE_SEL_0_RESET_SP_PARSER_T2_SHIFT 8
-#define BCHP_XPT_MEMDMA_MCPB_MANUAL_MODE_SEL_0_RESET_SP_PARSER_T2_DEFAULT 0x00000000
-
-/* XPT_MEMDMA_MCPB :: MANUAL_MODE_SEL_0 :: FORCE_TS_CONFIG_T1 [07:07] */
-#define BCHP_XPT_MEMDMA_MCPB_MANUAL_MODE_SEL_0_FORCE_TS_CONFIG_T1_MASK 0x00000080
-#define BCHP_XPT_MEMDMA_MCPB_MANUAL_MODE_SEL_0_FORCE_TS_CONFIG_T1_SHIFT 7
-#define BCHP_XPT_MEMDMA_MCPB_MANUAL_MODE_SEL_0_FORCE_TS_CONFIG_T1_DEFAULT 0x00000000
-
-/* XPT_MEMDMA_MCPB :: MANUAL_MODE_SEL_0 :: PUSH_RESIDUAL_BYTES_T1 [06:06] */
-#define BCHP_XPT_MEMDMA_MCPB_MANUAL_MODE_SEL_0_PUSH_RESIDUAL_BYTES_T1_MASK 0x00000040
-#define BCHP_XPT_MEMDMA_MCPB_MANUAL_MODE_SEL_0_PUSH_RESIDUAL_BYTES_T1_SHIFT 6
-#define BCHP_XPT_MEMDMA_MCPB_MANUAL_MODE_SEL_0_PUSH_RESIDUAL_BYTES_T1_DEFAULT 0x00000000
-
-/* XPT_MEMDMA_MCPB :: MANUAL_MODE_SEL_0 :: RESET_SP_PARSER_T1 [05:05] */
-#define BCHP_XPT_MEMDMA_MCPB_MANUAL_MODE_SEL_0_RESET_SP_PARSER_T1_MASK 0x00000020
-#define BCHP_XPT_MEMDMA_MCPB_MANUAL_MODE_SEL_0_RESET_SP_PARSER_T1_SHIFT 5
-#define BCHP_XPT_MEMDMA_MCPB_MANUAL_MODE_SEL_0_RESET_SP_PARSER_T1_DEFAULT 0x00000000
-
-/* XPT_MEMDMA_MCPB :: MANUAL_MODE_SEL_0 :: SEND_0_BYTE_TRANS_BEFORE_CUR_DATA_T1 [04:04] */
-#define BCHP_XPT_MEMDMA_MCPB_MANUAL_MODE_SEL_0_SEND_0_BYTE_TRANS_BEFORE_CUR_DATA_T1_MASK 0x00000010
-#define BCHP_XPT_MEMDMA_MCPB_MANUAL_MODE_SEL_0_SEND_0_BYTE_TRANS_BEFORE_CUR_DATA_T1_SHIFT 4
-#define BCHP_XPT_MEMDMA_MCPB_MANUAL_MODE_SEL_0_SEND_0_BYTE_TRANS_BEFORE_CUR_DATA_T1_DEFAULT 0x00000000
-
-/* XPT_MEMDMA_MCPB :: MANUAL_MODE_SEL_0 :: FORCE_TS_CONFIG_T0 [03:03] */
-#define BCHP_XPT_MEMDMA_MCPB_MANUAL_MODE_SEL_0_FORCE_TS_CONFIG_T0_MASK 0x00000008
-#define BCHP_XPT_MEMDMA_MCPB_MANUAL_MODE_SEL_0_FORCE_TS_CONFIG_T0_SHIFT 3
-#define BCHP_XPT_MEMDMA_MCPB_MANUAL_MODE_SEL_0_FORCE_TS_CONFIG_T0_DEFAULT 0x00000000
-
-/* XPT_MEMDMA_MCPB :: MANUAL_MODE_SEL_0 :: PUSH_RESIDUAL_BYTES_T0 [02:02] */
-#define BCHP_XPT_MEMDMA_MCPB_MANUAL_MODE_SEL_0_PUSH_RESIDUAL_BYTES_T0_MASK 0x00000004
-#define BCHP_XPT_MEMDMA_MCPB_MANUAL_MODE_SEL_0_PUSH_RESIDUAL_BYTES_T0_SHIFT 2
-#define BCHP_XPT_MEMDMA_MCPB_MANUAL_MODE_SEL_0_PUSH_RESIDUAL_BYTES_T0_DEFAULT 0x00000000
-
-/* XPT_MEMDMA_MCPB :: MANUAL_MODE_SEL_0 :: RESET_SP_PARSER_T0 [01:01] */
-#define BCHP_XPT_MEMDMA_MCPB_MANUAL_MODE_SEL_0_RESET_SP_PARSER_T0_MASK 0x00000002
-#define BCHP_XPT_MEMDMA_MCPB_MANUAL_MODE_SEL_0_RESET_SP_PARSER_T0_SHIFT 1
-#define BCHP_XPT_MEMDMA_MCPB_MANUAL_MODE_SEL_0_RESET_SP_PARSER_T0_DEFAULT 0x00000000
-
-/* XPT_MEMDMA_MCPB :: MANUAL_MODE_SEL_0 :: SEND_0_BYTE_TRANS_WITH_PREV_DESC_INFO_T0 [00:00] */
-#define BCHP_XPT_MEMDMA_MCPB_MANUAL_MODE_SEL_0_SEND_0_BYTE_TRANS_WITH_PREV_DESC_INFO_T0_MASK 0x00000001
-#define BCHP_XPT_MEMDMA_MCPB_MANUAL_MODE_SEL_0_SEND_0_BYTE_TRANS_WITH_PREV_DESC_INFO_T0_SHIFT 0
-#define BCHP_XPT_MEMDMA_MCPB_MANUAL_MODE_SEL_0_SEND_0_BYTE_TRANS_WITH_PREV_DESC_INFO_T0_DEFAULT 0x00000000
-
-/***************************************************************************
- *MANUAL_MODE_SEL_1 - Manual mode select signals Selection 1
- ***************************************************************************/
-/* XPT_MEMDMA_MCPB :: MANUAL_MODE_SEL_1 :: reserved0 [31:19] */
-#define BCHP_XPT_MEMDMA_MCPB_MANUAL_MODE_SEL_1_reserved0_MASK 0xfff80000
-#define BCHP_XPT_MEMDMA_MCPB_MANUAL_MODE_SEL_1_reserved0_SHIFT 19
-
-/* XPT_MEMDMA_MCPB :: MANUAL_MODE_SEL_1 :: FORCE_TS_CONFIG_T4 [18:18] */
-#define BCHP_XPT_MEMDMA_MCPB_MANUAL_MODE_SEL_1_FORCE_TS_CONFIG_T4_MASK 0x00040000
-#define BCHP_XPT_MEMDMA_MCPB_MANUAL_MODE_SEL_1_FORCE_TS_CONFIG_T4_SHIFT 18
-#define BCHP_XPT_MEMDMA_MCPB_MANUAL_MODE_SEL_1_FORCE_TS_CONFIG_T4_DEFAULT 0x00000000
-
-/* XPT_MEMDMA_MCPB :: MANUAL_MODE_SEL_1 :: PUSH_RESIDUAL_BYTES_T4 [17:17] */
-#define BCHP_XPT_MEMDMA_MCPB_MANUAL_MODE_SEL_1_PUSH_RESIDUAL_BYTES_T4_MASK 0x00020000
-#define BCHP_XPT_MEMDMA_MCPB_MANUAL_MODE_SEL_1_PUSH_RESIDUAL_BYTES_T4_SHIFT 17
-#define BCHP_XPT_MEMDMA_MCPB_MANUAL_MODE_SEL_1_PUSH_RESIDUAL_BYTES_T4_DEFAULT 0x00000000
-
-/* XPT_MEMDMA_MCPB :: MANUAL_MODE_SEL_1 :: RESET_SP_PARSER_T4 [16:16] */
-#define BCHP_XPT_MEMDMA_MCPB_MANUAL_MODE_SEL_1_RESET_SP_PARSER_T4_MASK 0x00010000
-#define BCHP_XPT_MEMDMA_MCPB_MANUAL_MODE_SEL_1_RESET_SP_PARSER_T4_SHIFT 16
-#define BCHP_XPT_MEMDMA_MCPB_MANUAL_MODE_SEL_1_RESET_SP_PARSER_T4_DEFAULT 0x00000000
-
-/* XPT_MEMDMA_MCPB :: MANUAL_MODE_SEL_1 :: reserved1 [15:15] */
-#define BCHP_XPT_MEMDMA_MCPB_MANUAL_MODE_SEL_1_reserved1_MASK 0x00008000
-#define BCHP_XPT_MEMDMA_MCPB_MANUAL_MODE_SEL_1_reserved1_SHIFT 15
-
-/* XPT_MEMDMA_MCPB :: MANUAL_MODE_SEL_1 :: FORCE_TS_CONFIG_T3 [14:14] */
-#define BCHP_XPT_MEMDMA_MCPB_MANUAL_MODE_SEL_1_FORCE_TS_CONFIG_T3_MASK 0x00004000
-#define BCHP_XPT_MEMDMA_MCPB_MANUAL_MODE_SEL_1_FORCE_TS_CONFIG_T3_SHIFT 14
-#define BCHP_XPT_MEMDMA_MCPB_MANUAL_MODE_SEL_1_FORCE_TS_CONFIG_T3_DEFAULT 0x00000000
-
-/* XPT_MEMDMA_MCPB :: MANUAL_MODE_SEL_1 :: PUSH_RESIDUAL_BYTES_T3 [13:13] */
-#define BCHP_XPT_MEMDMA_MCPB_MANUAL_MODE_SEL_1_PUSH_RESIDUAL_BYTES_T3_MASK 0x00002000
-#define BCHP_XPT_MEMDMA_MCPB_MANUAL_MODE_SEL_1_PUSH_RESIDUAL_BYTES_T3_SHIFT 13
-#define BCHP_XPT_MEMDMA_MCPB_MANUAL_MODE_SEL_1_PUSH_RESIDUAL_BYTES_T3_DEFAULT 0x00000000
-
-/* XPT_MEMDMA_MCPB :: MANUAL_MODE_SEL_1 :: RESET_SP_PARSER_T3 [12:12] */
-#define BCHP_XPT_MEMDMA_MCPB_MANUAL_MODE_SEL_1_RESET_SP_PARSER_T3_MASK 0x00001000
-#define BCHP_XPT_MEMDMA_MCPB_MANUAL_MODE_SEL_1_RESET_SP_PARSER_T3_SHIFT 12
-#define BCHP_XPT_MEMDMA_MCPB_MANUAL_MODE_SEL_1_RESET_SP_PARSER_T3_DEFAULT 0x00000000
-
-/* XPT_MEMDMA_MCPB :: MANUAL_MODE_SEL_1 :: reserved2 [11:11] */
-#define BCHP_XPT_MEMDMA_MCPB_MANUAL_MODE_SEL_1_reserved2_MASK 0x00000800
-#define BCHP_XPT_MEMDMA_MCPB_MANUAL_MODE_SEL_1_reserved2_SHIFT 11
-
-/* XPT_MEMDMA_MCPB :: MANUAL_MODE_SEL_1 :: FORCE_TS_CONFIG_T2 [10:10] */
-#define BCHP_XPT_MEMDMA_MCPB_MANUAL_MODE_SEL_1_FORCE_TS_CONFIG_T2_MASK 0x00000400
-#define BCHP_XPT_MEMDMA_MCPB_MANUAL_MODE_SEL_1_FORCE_TS_CONFIG_T2_SHIFT 10
-#define BCHP_XPT_MEMDMA_MCPB_MANUAL_MODE_SEL_1_FORCE_TS_CONFIG_T2_DEFAULT 0x00000000
-
-/* XPT_MEMDMA_MCPB :: MANUAL_MODE_SEL_1 :: PUSH_RESIDUAL_BYTES_T2 [09:09] */
-#define BCHP_XPT_MEMDMA_MCPB_MANUAL_MODE_SEL_1_PUSH_RESIDUAL_BYTES_T2_MASK 0x00000200
-#define BCHP_XPT_MEMDMA_MCPB_MANUAL_MODE_SEL_1_PUSH_RESIDUAL_BYTES_T2_SHIFT 9
-#define BCHP_XPT_MEMDMA_MCPB_MANUAL_MODE_SEL_1_PUSH_RESIDUAL_BYTES_T2_DEFAULT 0x00000000
-
-/* XPT_MEMDMA_MCPB :: MANUAL_MODE_SEL_1 :: RESET_SP_PARSER_T2 [08:08] */
-#define BCHP_XPT_MEMDMA_MCPB_MANUAL_MODE_SEL_1_RESET_SP_PARSER_T2_MASK 0x00000100
-#define BCHP_XPT_MEMDMA_MCPB_MANUAL_MODE_SEL_1_RESET_SP_PARSER_T2_SHIFT 8
-#define BCHP_XPT_MEMDMA_MCPB_MANUAL_MODE_SEL_1_RESET_SP_PARSER_T2_DEFAULT 0x00000000
-
-/* XPT_MEMDMA_MCPB :: MANUAL_MODE_SEL_1 :: FORCE_TS_CONFIG_T1 [07:07] */
-#define BCHP_XPT_MEMDMA_MCPB_MANUAL_MODE_SEL_1_FORCE_TS_CONFIG_T1_MASK 0x00000080
-#define BCHP_XPT_MEMDMA_MCPB_MANUAL_MODE_SEL_1_FORCE_TS_CONFIG_T1_SHIFT 7
-#define BCHP_XPT_MEMDMA_MCPB_MANUAL_MODE_SEL_1_FORCE_TS_CONFIG_T1_DEFAULT 0x00000000
-
-/* XPT_MEMDMA_MCPB :: MANUAL_MODE_SEL_1 :: PUSH_RESIDUAL_BYTES_T1 [06:06] */
-#define BCHP_XPT_MEMDMA_MCPB_MANUAL_MODE_SEL_1_PUSH_RESIDUAL_BYTES_T1_MASK 0x00000040
-#define BCHP_XPT_MEMDMA_MCPB_MANUAL_MODE_SEL_1_PUSH_RESIDUAL_BYTES_T1_SHIFT 6
-#define BCHP_XPT_MEMDMA_MCPB_MANUAL_MODE_SEL_1_PUSH_RESIDUAL_BYTES_T1_DEFAULT 0x00000000
-
-/* XPT_MEMDMA_MCPB :: MANUAL_MODE_SEL_1 :: RESET_SP_PARSER_T1 [05:05] */
-#define BCHP_XPT_MEMDMA_MCPB_MANUAL_MODE_SEL_1_RESET_SP_PARSER_T1_MASK 0x00000020
-#define BCHP_XPT_MEMDMA_MCPB_MANUAL_MODE_SEL_1_RESET_SP_PARSER_T1_SHIFT 5
-#define BCHP_XPT_MEMDMA_MCPB_MANUAL_MODE_SEL_1_RESET_SP_PARSER_T1_DEFAULT 0x00000000
-
-/* XPT_MEMDMA_MCPB :: MANUAL_MODE_SEL_1 :: SEND_0_BYTE_TRANS_BEFORE_CUR_DATA_T1 [04:04] */
-#define BCHP_XPT_MEMDMA_MCPB_MANUAL_MODE_SEL_1_SEND_0_BYTE_TRANS_BEFORE_CUR_DATA_T1_MASK 0x00000010
-#define BCHP_XPT_MEMDMA_MCPB_MANUAL_MODE_SEL_1_SEND_0_BYTE_TRANS_BEFORE_CUR_DATA_T1_SHIFT 4
-#define BCHP_XPT_MEMDMA_MCPB_MANUAL_MODE_SEL_1_SEND_0_BYTE_TRANS_BEFORE_CUR_DATA_T1_DEFAULT 0x00000000
-
-/* XPT_MEMDMA_MCPB :: MANUAL_MODE_SEL_1 :: FORCE_TS_CONFIG_T0 [03:03] */
-#define BCHP_XPT_MEMDMA_MCPB_MANUAL_MODE_SEL_1_FORCE_TS_CONFIG_T0_MASK 0x00000008
-#define BCHP_XPT_MEMDMA_MCPB_MANUAL_MODE_SEL_1_FORCE_TS_CONFIG_T0_SHIFT 3
-#define BCHP_XPT_MEMDMA_MCPB_MANUAL_MODE_SEL_1_FORCE_TS_CONFIG_T0_DEFAULT 0x00000000
-
-/* XPT_MEMDMA_MCPB :: MANUAL_MODE_SEL_1 :: PUSH_RESIDUAL_BYTES_T0 [02:02] */
-#define BCHP_XPT_MEMDMA_MCPB_MANUAL_MODE_SEL_1_PUSH_RESIDUAL_BYTES_T0_MASK 0x00000004
-#define BCHP_XPT_MEMDMA_MCPB_MANUAL_MODE_SEL_1_PUSH_RESIDUAL_BYTES_T0_SHIFT 2
-#define BCHP_XPT_MEMDMA_MCPB_MANUAL_MODE_SEL_1_PUSH_RESIDUAL_BYTES_T0_DEFAULT 0x00000000
-
-/* XPT_MEMDMA_MCPB :: MANUAL_MODE_SEL_1 :: RESET_SP_PARSER_T0 [01:01] */
-#define BCHP_XPT_MEMDMA_MCPB_MANUAL_MODE_SEL_1_RESET_SP_PARSER_T0_MASK 0x00000002
-#define BCHP_XPT_MEMDMA_MCPB_MANUAL_MODE_SEL_1_RESET_SP_PARSER_T0_SHIFT 1
-#define BCHP_XPT_MEMDMA_MCPB_MANUAL_MODE_SEL_1_RESET_SP_PARSER_T0_DEFAULT 0x00000000
-
-/* XPT_MEMDMA_MCPB :: MANUAL_MODE_SEL_1 :: SEND_0_BYTE_TRANS_WITH_PREV_DESC_INFO_T0 [00:00] */
-#define BCHP_XPT_MEMDMA_MCPB_MANUAL_MODE_SEL_1_SEND_0_BYTE_TRANS_WITH_PREV_DESC_INFO_T0_MASK 0x00000001
-#define BCHP_XPT_MEMDMA_MCPB_MANUAL_MODE_SEL_1_SEND_0_BYTE_TRANS_WITH_PREV_DESC_INFO_T0_SHIFT 0
-#define BCHP_XPT_MEMDMA_MCPB_MANUAL_MODE_SEL_1_SEND_0_BYTE_TRANS_WITH_PREV_DESC_INFO_T0_DEFAULT 0x00000000
-
-/***************************************************************************
- *MANUAL_MODE_SEL_2 - Manual mode select signals Selection 2
- ***************************************************************************/
-/* XPT_MEMDMA_MCPB :: MANUAL_MODE_SEL_2 :: reserved0 [31:19] */
-#define BCHP_XPT_MEMDMA_MCPB_MANUAL_MODE_SEL_2_reserved0_MASK 0xfff80000
-#define BCHP_XPT_MEMDMA_MCPB_MANUAL_MODE_SEL_2_reserved0_SHIFT 19
-
-/* XPT_MEMDMA_MCPB :: MANUAL_MODE_SEL_2 :: FORCE_TS_CONFIG_T4 [18:18] */
-#define BCHP_XPT_MEMDMA_MCPB_MANUAL_MODE_SEL_2_FORCE_TS_CONFIG_T4_MASK 0x00040000
-#define BCHP_XPT_MEMDMA_MCPB_MANUAL_MODE_SEL_2_FORCE_TS_CONFIG_T4_SHIFT 18
-#define BCHP_XPT_MEMDMA_MCPB_MANUAL_MODE_SEL_2_FORCE_TS_CONFIG_T4_DEFAULT 0x00000000
-
-/* XPT_MEMDMA_MCPB :: MANUAL_MODE_SEL_2 :: PUSH_RESIDUAL_BYTES_T4 [17:17] */
-#define BCHP_XPT_MEMDMA_MCPB_MANUAL_MODE_SEL_2_PUSH_RESIDUAL_BYTES_T4_MASK 0x00020000
-#define BCHP_XPT_MEMDMA_MCPB_MANUAL_MODE_SEL_2_PUSH_RESIDUAL_BYTES_T4_SHIFT 17
-#define BCHP_XPT_MEMDMA_MCPB_MANUAL_MODE_SEL_2_PUSH_RESIDUAL_BYTES_T4_DEFAULT 0x00000000
-
-/* XPT_MEMDMA_MCPB :: MANUAL_MODE_SEL_2 :: RESET_SP_PARSER_T4 [16:16] */
-#define BCHP_XPT_MEMDMA_MCPB_MANUAL_MODE_SEL_2_RESET_SP_PARSER_T4_MASK 0x00010000
-#define BCHP_XPT_MEMDMA_MCPB_MANUAL_MODE_SEL_2_RESET_SP_PARSER_T4_SHIFT 16
-#define BCHP_XPT_MEMDMA_MCPB_MANUAL_MODE_SEL_2_RESET_SP_PARSER_T4_DEFAULT 0x00000000
-
-/* XPT_MEMDMA_MCPB :: MANUAL_MODE_SEL_2 :: reserved1 [15:15] */
-#define BCHP_XPT_MEMDMA_MCPB_MANUAL_MODE_SEL_2_reserved1_MASK 0x00008000
-#define BCHP_XPT_MEMDMA_MCPB_MANUAL_MODE_SEL_2_reserved1_SHIFT 15
-
-/* XPT_MEMDMA_MCPB :: MANUAL_MODE_SEL_2 :: FORCE_TS_CONFIG_T3 [14:14] */
-#define BCHP_XPT_MEMDMA_MCPB_MANUAL_MODE_SEL_2_FORCE_TS_CONFIG_T3_MASK 0x00004000
-#define BCHP_XPT_MEMDMA_MCPB_MANUAL_MODE_SEL_2_FORCE_TS_CONFIG_T3_SHIFT 14
-#define BCHP_XPT_MEMDMA_MCPB_MANUAL_MODE_SEL_2_FORCE_TS_CONFIG_T3_DEFAULT 0x00000000
-
-/* XPT_MEMDMA_MCPB :: MANUAL_MODE_SEL_2 :: PUSH_RESIDUAL_BYTES_T3 [13:13] */
-#define BCHP_XPT_MEMDMA_MCPB_MANUAL_MODE_SEL_2_PUSH_RESIDUAL_BYTES_T3_MASK 0x00002000
-#define BCHP_XPT_MEMDMA_MCPB_MANUAL_MODE_SEL_2_PUSH_RESIDUAL_BYTES_T3_SHIFT 13
-#define BCHP_XPT_MEMDMA_MCPB_MANUAL_MODE_SEL_2_PUSH_RESIDUAL_BYTES_T3_DEFAULT 0x00000000
-
-/* XPT_MEMDMA_MCPB :: MANUAL_MODE_SEL_2 :: RESET_SP_PARSER_T3 [12:12] */
-#define BCHP_XPT_MEMDMA_MCPB_MANUAL_MODE_SEL_2_RESET_SP_PARSER_T3_MASK 0x00001000
-#define BCHP_XPT_MEMDMA_MCPB_MANUAL_MODE_SEL_2_RESET_SP_PARSER_T3_SHIFT 12
-#define BCHP_XPT_MEMDMA_MCPB_MANUAL_MODE_SEL_2_RESET_SP_PARSER_T3_DEFAULT 0x00000000
-
-/* XPT_MEMDMA_MCPB :: MANUAL_MODE_SEL_2 :: reserved2 [11:11] */
-#define BCHP_XPT_MEMDMA_MCPB_MANUAL_MODE_SEL_2_reserved2_MASK 0x00000800
-#define BCHP_XPT_MEMDMA_MCPB_MANUAL_MODE_SEL_2_reserved2_SHIFT 11
-
-/* XPT_MEMDMA_MCPB :: MANUAL_MODE_SEL_2 :: FORCE_TS_CONFIG_T2 [10:10] */
-#define BCHP_XPT_MEMDMA_MCPB_MANUAL_MODE_SEL_2_FORCE_TS_CONFIG_T2_MASK 0x00000400
-#define BCHP_XPT_MEMDMA_MCPB_MANUAL_MODE_SEL_2_FORCE_TS_CONFIG_T2_SHIFT 10
-#define BCHP_XPT_MEMDMA_MCPB_MANUAL_MODE_SEL_2_FORCE_TS_CONFIG_T2_DEFAULT 0x00000000
-
-/* XPT_MEMDMA_MCPB :: MANUAL_MODE_SEL_2 :: PUSH_RESIDUAL_BYTES_T2 [09:09] */
-#define BCHP_XPT_MEMDMA_MCPB_MANUAL_MODE_SEL_2_PUSH_RESIDUAL_BYTES_T2_MASK 0x00000200
-#define BCHP_XPT_MEMDMA_MCPB_MANUAL_MODE_SEL_2_PUSH_RESIDUAL_BYTES_T2_SHIFT 9
-#define BCHP_XPT_MEMDMA_MCPB_MANUAL_MODE_SEL_2_PUSH_RESIDUAL_BYTES_T2_DEFAULT 0x00000000
-
-/* XPT_MEMDMA_MCPB :: MANUAL_MODE_SEL_2 :: RESET_SP_PARSER_T2 [08:08] */
-#define BCHP_XPT_MEMDMA_MCPB_MANUAL_MODE_SEL_2_RESET_SP_PARSER_T2_MASK 0x00000100
-#define BCHP_XPT_MEMDMA_MCPB_MANUAL_MODE_SEL_2_RESET_SP_PARSER_T2_SHIFT 8
-#define BCHP_XPT_MEMDMA_MCPB_MANUAL_MODE_SEL_2_RESET_SP_PARSER_T2_DEFAULT 0x00000000
-
-/* XPT_MEMDMA_MCPB :: MANUAL_MODE_SEL_2 :: FORCE_TS_CONFIG_T1 [07:07] */
-#define BCHP_XPT_MEMDMA_MCPB_MANUAL_MODE_SEL_2_FORCE_TS_CONFIG_T1_MASK 0x00000080
-#define BCHP_XPT_MEMDMA_MCPB_MANUAL_MODE_SEL_2_FORCE_TS_CONFIG_T1_SHIFT 7
-#define BCHP_XPT_MEMDMA_MCPB_MANUAL_MODE_SEL_2_FORCE_TS_CONFIG_T1_DEFAULT 0x00000000
-
-/* XPT_MEMDMA_MCPB :: MANUAL_MODE_SEL_2 :: PUSH_RESIDUAL_BYTES_T1 [06:06] */
-#define BCHP_XPT_MEMDMA_MCPB_MANUAL_MODE_SEL_2_PUSH_RESIDUAL_BYTES_T1_MASK 0x00000040
-#define BCHP_XPT_MEMDMA_MCPB_MANUAL_MODE_SEL_2_PUSH_RESIDUAL_BYTES_T1_SHIFT 6
-#define BCHP_XPT_MEMDMA_MCPB_MANUAL_MODE_SEL_2_PUSH_RESIDUAL_BYTES_T1_DEFAULT 0x00000000
-
-/* XPT_MEMDMA_MCPB :: MANUAL_MODE_SEL_2 :: RESET_SP_PARSER_T1 [05:05] */
-#define BCHP_XPT_MEMDMA_MCPB_MANUAL_MODE_SEL_2_RESET_SP_PARSER_T1_MASK 0x00000020
-#define BCHP_XPT_MEMDMA_MCPB_MANUAL_MODE_SEL_2_RESET_SP_PARSER_T1_SHIFT 5
-#define BCHP_XPT_MEMDMA_MCPB_MANUAL_MODE_SEL_2_RESET_SP_PARSER_T1_DEFAULT 0x00000000
-
-/* XPT_MEMDMA_MCPB :: MANUAL_MODE_SEL_2 :: SEND_0_BYTE_TRANS_BEFORE_CUR_DATA_T1 [04:04] */
-#define BCHP_XPT_MEMDMA_MCPB_MANUAL_MODE_SEL_2_SEND_0_BYTE_TRANS_BEFORE_CUR_DATA_T1_MASK 0x00000010
-#define BCHP_XPT_MEMDMA_MCPB_MANUAL_MODE_SEL_2_SEND_0_BYTE_TRANS_BEFORE_CUR_DATA_T1_SHIFT 4
-#define BCHP_XPT_MEMDMA_MCPB_MANUAL_MODE_SEL_2_SEND_0_BYTE_TRANS_BEFORE_CUR_DATA_T1_DEFAULT 0x00000000
-
-/* XPT_MEMDMA_MCPB :: MANUAL_MODE_SEL_2 :: FORCE_TS_CONFIG_T0 [03:03] */
-#define BCHP_XPT_MEMDMA_MCPB_MANUAL_MODE_SEL_2_FORCE_TS_CONFIG_T0_MASK 0x00000008
-#define BCHP_XPT_MEMDMA_MCPB_MANUAL_MODE_SEL_2_FORCE_TS_CONFIG_T0_SHIFT 3
-#define BCHP_XPT_MEMDMA_MCPB_MANUAL_MODE_SEL_2_FORCE_TS_CONFIG_T0_DEFAULT 0x00000000
-
-/* XPT_MEMDMA_MCPB :: MANUAL_MODE_SEL_2 :: PUSH_RESIDUAL_BYTES_T0 [02:02] */
-#define BCHP_XPT_MEMDMA_MCPB_MANUAL_MODE_SEL_2_PUSH_RESIDUAL_BYTES_T0_MASK 0x00000004
-#define BCHP_XPT_MEMDMA_MCPB_MANUAL_MODE_SEL_2_PUSH_RESIDUAL_BYTES_T0_SHIFT 2
-#define BCHP_XPT_MEMDMA_MCPB_MANUAL_MODE_SEL_2_PUSH_RESIDUAL_BYTES_T0_DEFAULT 0x00000000
-
-/* XPT_MEMDMA_MCPB :: MANUAL_MODE_SEL_2 :: RESET_SP_PARSER_T0 [01:01] */
-#define BCHP_XPT_MEMDMA_MCPB_MANUAL_MODE_SEL_2_RESET_SP_PARSER_T0_MASK 0x00000002
-#define BCHP_XPT_MEMDMA_MCPB_MANUAL_MODE_SEL_2_RESET_SP_PARSER_T0_SHIFT 1
-#define BCHP_XPT_MEMDMA_MCPB_MANUAL_MODE_SEL_2_RESET_SP_PARSER_T0_DEFAULT 0x00000000
-
-/* XPT_MEMDMA_MCPB :: MANUAL_MODE_SEL_2 :: SEND_0_BYTE_TRANS_WITH_PREV_DESC_INFO_T0 [00:00] */
-#define BCHP_XPT_MEMDMA_MCPB_MANUAL_MODE_SEL_2_SEND_0_BYTE_TRANS_WITH_PREV_DESC_INFO_T0_MASK 0x00000001
-#define BCHP_XPT_MEMDMA_MCPB_MANUAL_MODE_SEL_2_SEND_0_BYTE_TRANS_WITH_PREV_DESC_INFO_T0_SHIFT 0
-#define BCHP_XPT_MEMDMA_MCPB_MANUAL_MODE_SEL_2_SEND_0_BYTE_TRANS_WITH_PREV_DESC_INFO_T0_DEFAULT 0x00000000
-
-/***************************************************************************
- *MANUAL_MODE_SEL_3 - Manual mode select signals Selection 3
- ***************************************************************************/
-/* XPT_MEMDMA_MCPB :: MANUAL_MODE_SEL_3 :: reserved0 [31:19] */
-#define BCHP_XPT_MEMDMA_MCPB_MANUAL_MODE_SEL_3_reserved0_MASK 0xfff80000
-#define BCHP_XPT_MEMDMA_MCPB_MANUAL_MODE_SEL_3_reserved0_SHIFT 19
-
-/* XPT_MEMDMA_MCPB :: MANUAL_MODE_SEL_3 :: FORCE_TS_CONFIG_T4 [18:18] */
-#define BCHP_XPT_MEMDMA_MCPB_MANUAL_MODE_SEL_3_FORCE_TS_CONFIG_T4_MASK 0x00040000
-#define BCHP_XPT_MEMDMA_MCPB_MANUAL_MODE_SEL_3_FORCE_TS_CONFIG_T4_SHIFT 18
-#define BCHP_XPT_MEMDMA_MCPB_MANUAL_MODE_SEL_3_FORCE_TS_CONFIG_T4_DEFAULT 0x00000000
-
-/* XPT_MEMDMA_MCPB :: MANUAL_MODE_SEL_3 :: PUSH_RESIDUAL_BYTES_T4 [17:17] */
-#define BCHP_XPT_MEMDMA_MCPB_MANUAL_MODE_SEL_3_PUSH_RESIDUAL_BYTES_T4_MASK 0x00020000
-#define BCHP_XPT_MEMDMA_MCPB_MANUAL_MODE_SEL_3_PUSH_RESIDUAL_BYTES_T4_SHIFT 17
-#define BCHP_XPT_MEMDMA_MCPB_MANUAL_MODE_SEL_3_PUSH_RESIDUAL_BYTES_T4_DEFAULT 0x00000000
-
-/* XPT_MEMDMA_MCPB :: MANUAL_MODE_SEL_3 :: RESET_SP_PARSER_T4 [16:16] */
-#define BCHP_XPT_MEMDMA_MCPB_MANUAL_MODE_SEL_3_RESET_SP_PARSER_T4_MASK 0x00010000
-#define BCHP_XPT_MEMDMA_MCPB_MANUAL_MODE_SEL_3_RESET_SP_PARSER_T4_SHIFT 16
-#define BCHP_XPT_MEMDMA_MCPB_MANUAL_MODE_SEL_3_RESET_SP_PARSER_T4_DEFAULT 0x00000000
-
-/* XPT_MEMDMA_MCPB :: MANUAL_MODE_SEL_3 :: reserved1 [15:15] */
-#define BCHP_XPT_MEMDMA_MCPB_MANUAL_MODE_SEL_3_reserved1_MASK 0x00008000
-#define BCHP_XPT_MEMDMA_MCPB_MANUAL_MODE_SEL_3_reserved1_SHIFT 15
-
-/* XPT_MEMDMA_MCPB :: MANUAL_MODE_SEL_3 :: FORCE_TS_CONFIG_T3 [14:14] */
-#define BCHP_XPT_MEMDMA_MCPB_MANUAL_MODE_SEL_3_FORCE_TS_CONFIG_T3_MASK 0x00004000
-#define BCHP_XPT_MEMDMA_MCPB_MANUAL_MODE_SEL_3_FORCE_TS_CONFIG_T3_SHIFT 14
-#define BCHP_XPT_MEMDMA_MCPB_MANUAL_MODE_SEL_3_FORCE_TS_CONFIG_T3_DEFAULT 0x00000000
-
-/* XPT_MEMDMA_MCPB :: MANUAL_MODE_SEL_3 :: PUSH_RESIDUAL_BYTES_T3 [13:13] */
-#define BCHP_XPT_MEMDMA_MCPB_MANUAL_MODE_SEL_3_PUSH_RESIDUAL_BYTES_T3_MASK 0x00002000
-#define BCHP_XPT_MEMDMA_MCPB_MANUAL_MODE_SEL_3_PUSH_RESIDUAL_BYTES_T3_SHIFT 13
-#define BCHP_XPT_MEMDMA_MCPB_MANUAL_MODE_SEL_3_PUSH_RESIDUAL_BYTES_T3_DEFAULT 0x00000000
-
-/* XPT_MEMDMA_MCPB :: MANUAL_MODE_SEL_3 :: RESET_SP_PARSER_T3 [12:12] */
-#define BCHP_XPT_MEMDMA_MCPB_MANUAL_MODE_SEL_3_RESET_SP_PARSER_T3_MASK 0x00001000
-#define BCHP_XPT_MEMDMA_MCPB_MANUAL_MODE_SEL_3_RESET_SP_PARSER_T3_SHIFT 12
-#define BCHP_XPT_MEMDMA_MCPB_MANUAL_MODE_SEL_3_RESET_SP_PARSER_T3_DEFAULT 0x00000000
-
-/* XPT_MEMDMA_MCPB :: MANUAL_MODE_SEL_3 :: reserved2 [11:11] */
-#define BCHP_XPT_MEMDMA_MCPB_MANUAL_MODE_SEL_3_reserved2_MASK 0x00000800
-#define BCHP_XPT_MEMDMA_MCPB_MANUAL_MODE_SEL_3_reserved2_SHIFT 11
-
-/* XPT_MEMDMA_MCPB :: MANUAL_MODE_SEL_3 :: FORCE_TS_CONFIG_T2 [10:10] */
-#define BCHP_XPT_MEMDMA_MCPB_MANUAL_MODE_SEL_3_FORCE_TS_CONFIG_T2_MASK 0x00000400
-#define BCHP_XPT_MEMDMA_MCPB_MANUAL_MODE_SEL_3_FORCE_TS_CONFIG_T2_SHIFT 10
-#define BCHP_XPT_MEMDMA_MCPB_MANUAL_MODE_SEL_3_FORCE_TS_CONFIG_T2_DEFAULT 0x00000000
-
-/* XPT_MEMDMA_MCPB :: MANUAL_MODE_SEL_3 :: PUSH_RESIDUAL_BYTES_T2 [09:09] */
-#define BCHP_XPT_MEMDMA_MCPB_MANUAL_MODE_SEL_3_PUSH_RESIDUAL_BYTES_T2_MASK 0x00000200
-#define BCHP_XPT_MEMDMA_MCPB_MANUAL_MODE_SEL_3_PUSH_RESIDUAL_BYTES_T2_SHIFT 9
-#define BCHP_XPT_MEMDMA_MCPB_MANUAL_MODE_SEL_3_PUSH_RESIDUAL_BYTES_T2_DEFAULT 0x00000000
-
-/* XPT_MEMDMA_MCPB :: MANUAL_MODE_SEL_3 :: RESET_SP_PARSER_T2 [08:08] */
-#define BCHP_XPT_MEMDMA_MCPB_MANUAL_MODE_SEL_3_RESET_SP_PARSER_T2_MASK 0x00000100
-#define BCHP_XPT_MEMDMA_MCPB_MANUAL_MODE_SEL_3_RESET_SP_PARSER_T2_SHIFT 8
-#define BCHP_XPT_MEMDMA_MCPB_MANUAL_MODE_SEL_3_RESET_SP_PARSER_T2_DEFAULT 0x00000000
-
-/* XPT_MEMDMA_MCPB :: MANUAL_MODE_SEL_3 :: FORCE_TS_CONFIG_T1 [07:07] */
-#define BCHP_XPT_MEMDMA_MCPB_MANUAL_MODE_SEL_3_FORCE_TS_CONFIG_T1_MASK 0x00000080
-#define BCHP_XPT_MEMDMA_MCPB_MANUAL_MODE_SEL_3_FORCE_TS_CONFIG_T1_SHIFT 7
-#define BCHP_XPT_MEMDMA_MCPB_MANUAL_MODE_SEL_3_FORCE_TS_CONFIG_T1_DEFAULT 0x00000000
-
-/* XPT_MEMDMA_MCPB :: MANUAL_MODE_SEL_3 :: PUSH_RESIDUAL_BYTES_T1 [06:06] */
-#define BCHP_XPT_MEMDMA_MCPB_MANUAL_MODE_SEL_3_PUSH_RESIDUAL_BYTES_T1_MASK 0x00000040
-#define BCHP_XPT_MEMDMA_MCPB_MANUAL_MODE_SEL_3_PUSH_RESIDUAL_BYTES_T1_SHIFT 6
-#define BCHP_XPT_MEMDMA_MCPB_MANUAL_MODE_SEL_3_PUSH_RESIDUAL_BYTES_T1_DEFAULT 0x00000000
-
-/* XPT_MEMDMA_MCPB :: MANUAL_MODE_SEL_3 :: RESET_SP_PARSER_T1 [05:05] */
-#define BCHP_XPT_MEMDMA_MCPB_MANUAL_MODE_SEL_3_RESET_SP_PARSER_T1_MASK 0x00000020
-#define BCHP_XPT_MEMDMA_MCPB_MANUAL_MODE_SEL_3_RESET_SP_PARSER_T1_SHIFT 5
-#define BCHP_XPT_MEMDMA_MCPB_MANUAL_MODE_SEL_3_RESET_SP_PARSER_T1_DEFAULT 0x00000000
-
-/* XPT_MEMDMA_MCPB :: MANUAL_MODE_SEL_3 :: SEND_0_BYTE_TRANS_BEFORE_CUR_DATA_T1 [04:04] */
-#define BCHP_XPT_MEMDMA_MCPB_MANUAL_MODE_SEL_3_SEND_0_BYTE_TRANS_BEFORE_CUR_DATA_T1_MASK 0x00000010
-#define BCHP_XPT_MEMDMA_MCPB_MANUAL_MODE_SEL_3_SEND_0_BYTE_TRANS_BEFORE_CUR_DATA_T1_SHIFT 4
-#define BCHP_XPT_MEMDMA_MCPB_MANUAL_MODE_SEL_3_SEND_0_BYTE_TRANS_BEFORE_CUR_DATA_T1_DEFAULT 0x00000000
-
-/* XPT_MEMDMA_MCPB :: MANUAL_MODE_SEL_3 :: FORCE_TS_CONFIG_T0 [03:03] */
-#define BCHP_XPT_MEMDMA_MCPB_MANUAL_MODE_SEL_3_FORCE_TS_CONFIG_T0_MASK 0x00000008
-#define BCHP_XPT_MEMDMA_MCPB_MANUAL_MODE_SEL_3_FORCE_TS_CONFIG_T0_SHIFT 3
-#define BCHP_XPT_MEMDMA_MCPB_MANUAL_MODE_SEL_3_FORCE_TS_CONFIG_T0_DEFAULT 0x00000000
-
-/* XPT_MEMDMA_MCPB :: MANUAL_MODE_SEL_3 :: PUSH_RESIDUAL_BYTES_T0 [02:02] */
-#define BCHP_XPT_MEMDMA_MCPB_MANUAL_MODE_SEL_3_PUSH_RESIDUAL_BYTES_T0_MASK 0x00000004
-#define BCHP_XPT_MEMDMA_MCPB_MANUAL_MODE_SEL_3_PUSH_RESIDUAL_BYTES_T0_SHIFT 2
-#define BCHP_XPT_MEMDMA_MCPB_MANUAL_MODE_SEL_3_PUSH_RESIDUAL_BYTES_T0_DEFAULT 0x00000000
-
-/* XPT_MEMDMA_MCPB :: MANUAL_MODE_SEL_3 :: RESET_SP_PARSER_T0 [01:01] */
-#define BCHP_XPT_MEMDMA_MCPB_MANUAL_MODE_SEL_3_RESET_SP_PARSER_T0_MASK 0x00000002
-#define BCHP_XPT_MEMDMA_MCPB_MANUAL_MODE_SEL_3_RESET_SP_PARSER_T0_SHIFT 1
-#define BCHP_XPT_MEMDMA_MCPB_MANUAL_MODE_SEL_3_RESET_SP_PARSER_T0_DEFAULT 0x00000000
-
-/* XPT_MEMDMA_MCPB :: MANUAL_MODE_SEL_3 :: SEND_0_BYTE_TRANS_WITH_PREV_DESC_INFO_T0 [00:00] */
-#define BCHP_XPT_MEMDMA_MCPB_MANUAL_MODE_SEL_3_SEND_0_BYTE_TRANS_WITH_PREV_DESC_INFO_T0_MASK 0x00000001
-#define BCHP_XPT_MEMDMA_MCPB_MANUAL_MODE_SEL_3_SEND_0_BYTE_TRANS_WITH_PREV_DESC_INFO_T0_SHIFT 0
-#define BCHP_XPT_MEMDMA_MCPB_MANUAL_MODE_SEL_3_SEND_0_BYTE_TRANS_WITH_PREV_DESC_INFO_T0_DEFAULT 0x00000000
-
-/***************************************************************************
- *DEBUG_0 - Debug Register
- ***************************************************************************/
-/* XPT_MEMDMA_MCPB :: DEBUG_0 :: VALUE [31:00] */
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_0_VALUE_MASK 0xffffffff
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_0_VALUE_SHIFT 0
-
-/***************************************************************************
- *DEBUG_1 - Debug Register
- ***************************************************************************/
-/* XPT_MEMDMA_MCPB :: DEBUG_1 :: VALUE [31:00] */
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_1_VALUE_MASK 0xffffffff
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_1_VALUE_SHIFT 0
-
-/***************************************************************************
- *DEBUG_2 - Debug Register
- ***************************************************************************/
-/* XPT_MEMDMA_MCPB :: DEBUG_2 :: VALUE [31:00] */
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_2_VALUE_MASK 0xffffffff
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_2_VALUE_SHIFT 0
-
-/***************************************************************************
- *DEBUG_3 - Debug Register
- ***************************************************************************/
-/* XPT_MEMDMA_MCPB :: DEBUG_3 :: VALUE [31:00] */
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_3_VALUE_MASK 0xffffffff
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_3_VALUE_SHIFT 0
-
-/***************************************************************************
- *DEBUG_4 - Debug Register
- ***************************************************************************/
-/* XPT_MEMDMA_MCPB :: DEBUG_4 :: VALUE [31:00] */
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_4_VALUE_MASK 0xffffffff
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_4_VALUE_SHIFT 0
-
-/***************************************************************************
- *DEBUG_5 - Debug Register
- ***************************************************************************/
-/* XPT_MEMDMA_MCPB :: DEBUG_5 :: VALUE_8 [31:27] */
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_5_VALUE_8_MASK 0xf8000000
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_5_VALUE_8_SHIFT 27
-
-/* XPT_MEMDMA_MCPB :: DEBUG_5 :: reserved0 [26:22] */
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_5_reserved0_MASK 0x07c00000
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_5_reserved0_SHIFT 22
-
-/* XPT_MEMDMA_MCPB :: DEBUG_5 :: VALUE_7 [21:19] */
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_5_VALUE_7_MASK 0x00380000
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_5_VALUE_7_SHIFT 19
-
-/* XPT_MEMDMA_MCPB :: DEBUG_5 :: VALUE_6 [18:18] */
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_5_VALUE_6_MASK 0x00040000
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_5_VALUE_6_SHIFT 18
-
-/* XPT_MEMDMA_MCPB :: DEBUG_5 :: VALUE_5 [17:17] */
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_5_VALUE_5_MASK 0x00020000
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_5_VALUE_5_SHIFT 17
-
-/* XPT_MEMDMA_MCPB :: DEBUG_5 :: VALUE_4 [16:16] */
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_5_VALUE_4_MASK 0x00010000
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_5_VALUE_4_SHIFT 16
-
-/* XPT_MEMDMA_MCPB :: DEBUG_5 :: reserved1 [15:10] */
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_5_reserved1_MASK 0x0000fc00
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_5_reserved1_SHIFT 10
-
-/* XPT_MEMDMA_MCPB :: DEBUG_5 :: VALUE_3 [09:05] */
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_5_VALUE_3_MASK 0x000003e0
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_5_VALUE_3_SHIFT 5
-
-/* XPT_MEMDMA_MCPB :: DEBUG_5 :: VALUE_2 [04:02] */
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_5_VALUE_2_MASK 0x0000001c
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_5_VALUE_2_SHIFT 2
-
-/* XPT_MEMDMA_MCPB :: DEBUG_5 :: VALUE_1 [01:01] */
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_5_VALUE_1_MASK 0x00000002
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_5_VALUE_1_SHIFT 1
-
-/* XPT_MEMDMA_MCPB :: DEBUG_5 :: VALUE_0 [00:00] */
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_5_VALUE_0_MASK 0x00000001
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_5_VALUE_0_SHIFT 0
-
-/***************************************************************************
- *DEBUG_6 - Debug Register
- ***************************************************************************/
-/* XPT_MEMDMA_MCPB :: DEBUG_6 :: VALUE [31:00] */
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_6_VALUE_MASK 0xffffffff
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_6_VALUE_SHIFT 0
-
-/***************************************************************************
- *DEBUG_7 - Debug Register
- ***************************************************************************/
-/* XPT_MEMDMA_MCPB :: DEBUG_7 :: reserved0 [31:28] */
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_7_reserved0_MASK 0xf0000000
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_7_reserved0_SHIFT 28
-
-/* XPT_MEMDMA_MCPB :: DEBUG_7 :: VALUE_9 [27:23] */
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_7_VALUE_9_MASK 0x0f800000
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_7_VALUE_9_SHIFT 23
-
-/* XPT_MEMDMA_MCPB :: DEBUG_7 :: VALUE_8 [22:22] */
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_7_VALUE_8_MASK 0x00400000
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_7_VALUE_8_SHIFT 22
-
-/* XPT_MEMDMA_MCPB :: DEBUG_7 :: VALUE_7 [21:21] */
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_7_VALUE_7_MASK 0x00200000
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_7_VALUE_7_SHIFT 21
-
-/* XPT_MEMDMA_MCPB :: DEBUG_7 :: VALUE_6 [20:20] */
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_7_VALUE_6_MASK 0x00100000
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_7_VALUE_6_SHIFT 20
-
-/* XPT_MEMDMA_MCPB :: DEBUG_7 :: VALUE_5 [19:19] */
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_7_VALUE_5_MASK 0x00080000
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_7_VALUE_5_SHIFT 19
-
-/* XPT_MEMDMA_MCPB :: DEBUG_7 :: VALUE_4 [18:16] */
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_7_VALUE_4_MASK 0x00070000
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_7_VALUE_4_SHIFT 16
-
-/* XPT_MEMDMA_MCPB :: DEBUG_7 :: reserved1 [15:11] */
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_7_reserved1_MASK 0x0000f800
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_7_reserved1_SHIFT 11
-
-/* XPT_MEMDMA_MCPB :: DEBUG_7 :: VALUE_3 [10:06] */
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_7_VALUE_3_MASK 0x000007c0
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_7_VALUE_3_SHIFT 6
-
-/* XPT_MEMDMA_MCPB :: DEBUG_7 :: VALUE_2 [05:02] */
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_7_VALUE_2_MASK 0x0000003c
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_7_VALUE_2_SHIFT 2
-
-/* XPT_MEMDMA_MCPB :: DEBUG_7 :: VALUE_1 [01:01] */
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_7_VALUE_1_MASK 0x00000002
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_7_VALUE_1_SHIFT 1
-
-/* XPT_MEMDMA_MCPB :: DEBUG_7 :: VALUE_0 [00:00] */
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_7_VALUE_0_MASK 0x00000001
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_7_VALUE_0_SHIFT 0
-
-/***************************************************************************
- *DEBUG_8 - Debug Register
- ***************************************************************************/
-/* XPT_MEMDMA_MCPB :: DEBUG_8 :: VALUE [31:00] */
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_8_VALUE_MASK 0xffffffff
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_8_VALUE_SHIFT 0
-
-/***************************************************************************
- *DEBUG_9 - Debug Register
- ***************************************************************************/
-/* XPT_MEMDMA_MCPB :: DEBUG_9 :: reserved0 [31:13] */
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_9_reserved0_MASK 0xffffe000
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_9_reserved0_SHIFT 13
-
-/* XPT_MEMDMA_MCPB :: DEBUG_9 :: VALUE_3 [12:12] */
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_9_VALUE_3_MASK 0x00001000
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_9_VALUE_3_SHIFT 12
-
-/* XPT_MEMDMA_MCPB :: DEBUG_9 :: VALUE_2 [11:08] */
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_9_VALUE_2_MASK 0x00000f00
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_9_VALUE_2_SHIFT 8
-
-/* XPT_MEMDMA_MCPB :: DEBUG_9 :: VALUE_1 [07:03] */
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_9_VALUE_1_MASK 0x000000f8
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_9_VALUE_1_SHIFT 3
-
-/* XPT_MEMDMA_MCPB :: DEBUG_9 :: VALUE_0 [02:00] */
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_9_VALUE_0_MASK 0x00000007
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_9_VALUE_0_SHIFT 0
-
-/***************************************************************************
- *DEBUG_10 - Debug Register
- ***************************************************************************/
-/* XPT_MEMDMA_MCPB :: DEBUG_10 :: TS_W0_OUT_DMA_END [31:31] */
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_10_TS_W0_OUT_DMA_END_MASK 0x80000000
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_10_TS_W0_OUT_DMA_END_SHIFT 31
-
-/* XPT_MEMDMA_MCPB :: DEBUG_10 :: TS_W1_OUT_DMA_END [30:30] */
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_10_TS_W1_OUT_DMA_END_MASK 0x40000000
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_10_TS_W1_OUT_DMA_END_SHIFT 30
-
-/* XPT_MEMDMA_MCPB :: DEBUG_10 :: TS_W2_OUT_DMA_END [29:29] */
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_10_TS_W2_OUT_DMA_END_MASK 0x20000000
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_10_TS_W2_OUT_DMA_END_SHIFT 29
-
-/* XPT_MEMDMA_MCPB :: DEBUG_10 :: TS_W3_OUT_DMA_END [28:28] */
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_10_TS_W3_OUT_DMA_END_MASK 0x10000000
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_10_TS_W3_OUT_DMA_END_SHIFT 28
-
-/* XPT_MEMDMA_MCPB :: DEBUG_10 :: TS_W4_OUT_DMA_END [27:27] */
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_10_TS_W4_OUT_DMA_END_MASK 0x08000000
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_10_TS_W4_OUT_DMA_END_SHIFT 27
-
-/* XPT_MEMDMA_MCPB :: DEBUG_10 :: TS_W0_OUT_READY [26:26] */
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_10_TS_W0_OUT_READY_MASK 0x04000000
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_10_TS_W0_OUT_READY_SHIFT 26
-
-/* XPT_MEMDMA_MCPB :: DEBUG_10 :: TS_W1_OUT_READY [25:25] */
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_10_TS_W1_OUT_READY_MASK 0x02000000
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_10_TS_W1_OUT_READY_SHIFT 25
-
-/* XPT_MEMDMA_MCPB :: DEBUG_10 :: TS_W2_OUT_READY [24:24] */
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_10_TS_W2_OUT_READY_MASK 0x01000000
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_10_TS_W2_OUT_READY_SHIFT 24
-
-/* XPT_MEMDMA_MCPB :: DEBUG_10 :: TS_W3_OUT_READY [23:23] */
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_10_TS_W3_OUT_READY_MASK 0x00800000
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_10_TS_W3_OUT_READY_SHIFT 23
-
-/* XPT_MEMDMA_MCPB :: DEBUG_10 :: TS_W4_OUT_READY [22:22] */
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_10_TS_W4_OUT_READY_MASK 0x00400000
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_10_TS_W4_OUT_READY_SHIFT 22
-
-/* XPT_MEMDMA_MCPB :: DEBUG_10 :: TS_W4_OUT_ACCEPT [21:21] */
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_10_TS_W4_OUT_ACCEPT_MASK 0x00200000
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_10_TS_W4_OUT_ACCEPT_SHIFT 21
-
-/* XPT_MEMDMA_MCPB :: DEBUG_10 :: TS_W5_IN_ACCEPT [20:20] */
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_10_TS_W5_IN_ACCEPT_MASK 0x00100000
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_10_TS_W5_IN_ACCEPT_SHIFT 20
-
-/* XPT_MEMDMA_MCPB :: DEBUG_10 :: TS_W5_IN_READY [19:19] */
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_10_TS_W5_IN_READY_MASK 0x00080000
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_10_TS_W5_IN_READY_SHIFT 19
-
-/* XPT_MEMDMA_MCPB :: DEBUG_10 :: TS_STATE [18:13] */
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_10_TS_STATE_MASK 0x0007e000
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_10_TS_STATE_SHIFT 13
-
-/* XPT_MEMDMA_MCPB :: DEBUG_10 :: TS_BAND_ID [12:05] */
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_10_TS_BAND_ID_MASK 0x00001fe0
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_10_TS_BAND_ID_SHIFT 5
-
-/* XPT_MEMDMA_MCPB :: DEBUG_10 :: TS_PKT_BUF2SP_DONE [04:04] */
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_10_TS_PKT_BUF2SP_DONE_MASK 0x00000010
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_10_TS_PKT_BUF2SP_DONE_SHIFT 4
-
-/* XPT_MEMDMA_MCPB :: DEBUG_10 :: TS_CFG_DCP2SP_DONE [03:03] */
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_10_TS_CFG_DCP2SP_DONE_MASK 0x00000008
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_10_TS_CFG_DCP2SP_DONE_SHIFT 3
-
-/* XPT_MEMDMA_MCPB :: DEBUG_10 :: TS_CFG_DMA_SP2SP_DONE [02:02] */
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_10_TS_CFG_DMA_SP2SP_DONE_MASK 0x00000004
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_10_TS_CFG_DMA_SP2SP_DONE_SHIFT 2
-
-/* XPT_MEMDMA_MCPB :: DEBUG_10 :: TS_SMU2SP_DONE [01:01] */
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_10_TS_SMU2SP_DONE_MASK 0x00000002
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_10_TS_SMU2SP_DONE_SHIFT 1
-
-/* XPT_MEMDMA_MCPB :: DEBUG_10 :: TS_SP2DMA_START [00:00] */
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_10_TS_SP2DMA_START_MASK 0x00000001
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_10_TS_SP2DMA_START_SHIFT 0
-
-/***************************************************************************
- *DEBUG_11 - Debug Register
- ***************************************************************************/
-/* XPT_MEMDMA_MCPB :: DEBUG_11 :: reserved0 [31:08] */
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_11_reserved0_MASK 0xffffff00
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_11_reserved0_SHIFT 8
-
-/* XPT_MEMDMA_MCPB :: DEBUG_11 :: TS_PT_SEARCH_IN_PROGRESS [07:07] */
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_11_TS_PT_SEARCH_IN_PROGRESS_MASK 0x00000080
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_11_TS_PT_SEARCH_IN_PROGRESS_SHIFT 7
-
-/* XPT_MEMDMA_MCPB :: DEBUG_11 :: TS_PT_SEARCH_DONE [06:06] */
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_11_TS_PT_SEARCH_DONE_MASK 0x00000040
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_11_TS_PT_SEARCH_DONE_SHIFT 6
-
-/* XPT_MEMDMA_MCPB :: DEBUG_11 :: TS_DMA_END [05:05] */
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_11_TS_DMA_END_MASK 0x00000020
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_11_TS_DMA_END_SHIFT 5
-
-/* XPT_MEMDMA_MCPB :: DEBUG_11 :: TS_PKT_END [04:04] */
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_11_TS_PKT_END_MASK 0x00000010
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_11_TS_PKT_END_SHIFT 4
-
-/* XPT_MEMDMA_MCPB :: DEBUG_11 :: TS_PKT_DONE [03:03] */
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_11_TS_PKT_DONE_MASK 0x00000008
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_11_TS_PKT_DONE_SHIFT 3
-
-/* XPT_MEMDMA_MCPB :: DEBUG_11 :: TS_LAST_TRANS [02:02] */
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_11_TS_LAST_TRANS_MASK 0x00000004
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_11_TS_LAST_TRANS_SHIFT 2
-
-/* XPT_MEMDMA_MCPB :: DEBUG_11 :: TS_SKIP_PKT_BUF2SP_DONE [01:01] */
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_11_TS_SKIP_PKT_BUF2SP_DONE_MASK 0x00000002
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_11_TS_SKIP_PKT_BUF2SP_DONE_SHIFT 1
-
-/* XPT_MEMDMA_MCPB :: DEBUG_11 :: TS_PARSING_IN_PROGRESS [00:00] */
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_11_TS_PARSING_IN_PROGRESS_MASK 0x00000001
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_11_TS_PARSING_IN_PROGRESS_SHIFT 0
-
-/***************************************************************************
- *DEBUG_12 - Debug Register
- ***************************************************************************/
-/* XPT_MEMDMA_MCPB :: DEBUG_12 :: PES_W0_OUT_DMA_END [31:31] */
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_12_PES_W0_OUT_DMA_END_MASK 0x80000000
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_12_PES_W0_OUT_DMA_END_SHIFT 31
-
-/* XPT_MEMDMA_MCPB :: DEBUG_12 :: PES_W1_OUT_DMA_END [30:30] */
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_12_PES_W1_OUT_DMA_END_MASK 0x40000000
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_12_PES_W1_OUT_DMA_END_SHIFT 30
-
-/* XPT_MEMDMA_MCPB :: DEBUG_12 :: PES_W2_OUT_DMA_END [29:29] */
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_12_PES_W2_OUT_DMA_END_MASK 0x20000000
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_12_PES_W2_OUT_DMA_END_SHIFT 29
-
-/* XPT_MEMDMA_MCPB :: DEBUG_12 :: PES_W3_OUT_DMA_END [28:28] */
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_12_PES_W3_OUT_DMA_END_MASK 0x10000000
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_12_PES_W3_OUT_DMA_END_SHIFT 28
-
-/* XPT_MEMDMA_MCPB :: DEBUG_12 :: PES_W4_OUT_DMA_END [27:27] */
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_12_PES_W4_OUT_DMA_END_MASK 0x08000000
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_12_PES_W4_OUT_DMA_END_SHIFT 27
-
-/* XPT_MEMDMA_MCPB :: DEBUG_12 :: PES_W0_OUT_READY [26:26] */
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_12_PES_W0_OUT_READY_MASK 0x04000000
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_12_PES_W0_OUT_READY_SHIFT 26
-
-/* XPT_MEMDMA_MCPB :: DEBUG_12 :: PES_W1_OUT_READY [25:25] */
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_12_PES_W1_OUT_READY_MASK 0x02000000
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_12_PES_W1_OUT_READY_SHIFT 25
-
-/* XPT_MEMDMA_MCPB :: DEBUG_12 :: PES_W2_OUT_READY [24:24] */
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_12_PES_W2_OUT_READY_MASK 0x01000000
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_12_PES_W2_OUT_READY_SHIFT 24
-
-/* XPT_MEMDMA_MCPB :: DEBUG_12 :: PES_W3_OUT_READY [23:23] */
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_12_PES_W3_OUT_READY_MASK 0x00800000
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_12_PES_W3_OUT_READY_SHIFT 23
-
-/* XPT_MEMDMA_MCPB :: DEBUG_12 :: PES_W4_OUT_READY [22:22] */
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_12_PES_W4_OUT_READY_MASK 0x00400000
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_12_PES_W4_OUT_READY_SHIFT 22
-
-/* XPT_MEMDMA_MCPB :: DEBUG_12 :: PES_W4_OUT_ACCEPT [21:21] */
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_12_PES_W4_OUT_ACCEPT_MASK 0x00200000
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_12_PES_W4_OUT_ACCEPT_SHIFT 21
-
-/* XPT_MEMDMA_MCPB :: DEBUG_12 :: PES_W5_IN_ACCEPT [20:20] */
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_12_PES_W5_IN_ACCEPT_MASK 0x00100000
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_12_PES_W5_IN_ACCEPT_SHIFT 20
-
-/* XPT_MEMDMA_MCPB :: DEBUG_12 :: PES_W5_IN_READY [19:19] */
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_12_PES_W5_IN_READY_MASK 0x00080000
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_12_PES_W5_IN_READY_SHIFT 19
-
-/* XPT_MEMDMA_MCPB :: DEBUG_12 :: PES_STATE [18:13] */
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_12_PES_STATE_MASK 0x0007e000
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_12_PES_STATE_SHIFT 13
-
-/* XPT_MEMDMA_MCPB :: DEBUG_12 :: PES_BAND_ID [12:05] */
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_12_PES_BAND_ID_MASK 0x00001fe0
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_12_PES_BAND_ID_SHIFT 5
-
-/* XPT_MEMDMA_MCPB :: DEBUG_12 :: PES_PKT_BUF2SP_DONE [04:04] */
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_12_PES_PKT_BUF2SP_DONE_MASK 0x00000010
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_12_PES_PKT_BUF2SP_DONE_SHIFT 4
-
-/* XPT_MEMDMA_MCPB :: DEBUG_12 :: PES_CFG_DCP2SP_DONE [03:03] */
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_12_PES_CFG_DCP2SP_DONE_MASK 0x00000008
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_12_PES_CFG_DCP2SP_DONE_SHIFT 3
-
-/* XPT_MEMDMA_MCPB :: DEBUG_12 :: PES_CFG_DMA_SP2SP_DONE [02:02] */
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_12_PES_CFG_DMA_SP2SP_DONE_MASK 0x00000004
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_12_PES_CFG_DMA_SP2SP_DONE_SHIFT 2
-
-/* XPT_MEMDMA_MCPB :: DEBUG_12 :: PES_SMU2SP_DONE [01:01] */
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_12_PES_SMU2SP_DONE_MASK 0x00000002
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_12_PES_SMU2SP_DONE_SHIFT 1
-
-/* XPT_MEMDMA_MCPB :: DEBUG_12 :: PES_SP2DMA_START [00:00] */
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_12_PES_SP2DMA_START_MASK 0x00000001
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_12_PES_SP2DMA_START_SHIFT 0
-
-/***************************************************************************
- *DEBUG_13 - Debug Register
- ***************************************************************************/
-/* XPT_MEMDMA_MCPB :: DEBUG_13 :: reserved0 [31:10] */
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_13_reserved0_MASK 0xfffffc00
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_13_reserved0_SHIFT 10
-
-/* XPT_MEMDMA_MCPB :: DEBUG_13 :: PES_SET_START_DCP [09:09] */
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_13_PES_SET_START_DCP_MASK 0x00000200
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_13_PES_SET_START_DCP_SHIFT 9
-
-/* XPT_MEMDMA_MCPB :: DEBUG_13 :: PES_VALID_PUSH_RESIDUAL_DATA [08:08] */
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_13_PES_VALID_PUSH_RESIDUAL_DATA_MASK 0x00000100
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_13_PES_VALID_PUSH_RESIDUAL_DATA_SHIFT 8
-
-/* XPT_MEMDMA_MCPB :: DEBUG_13 :: PES_PT_SEARCH_IN_PROGRESS [07:07] */
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_13_PES_PT_SEARCH_IN_PROGRESS_MASK 0x00000080
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_13_PES_PT_SEARCH_IN_PROGRESS_SHIFT 7
-
-/* XPT_MEMDMA_MCPB :: DEBUG_13 :: PES_PT_SEARCH_DONE [06:06] */
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_13_PES_PT_SEARCH_DONE_MASK 0x00000040
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_13_PES_PT_SEARCH_DONE_SHIFT 6
-
-/* XPT_MEMDMA_MCPB :: DEBUG_13 :: PES_DMA_END [05:05] */
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_13_PES_DMA_END_MASK 0x00000020
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_13_PES_DMA_END_SHIFT 5
-
-/* XPT_MEMDMA_MCPB :: DEBUG_13 :: PES_PKT_END [04:04] */
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_13_PES_PKT_END_MASK 0x00000010
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_13_PES_PKT_END_SHIFT 4
-
-/* XPT_MEMDMA_MCPB :: DEBUG_13 :: PES_PKT_DONE [03:03] */
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_13_PES_PKT_DONE_MASK 0x00000008
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_13_PES_PKT_DONE_SHIFT 3
-
-/* XPT_MEMDMA_MCPB :: DEBUG_13 :: PES_LAST_TRANS [02:02] */
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_13_PES_LAST_TRANS_MASK 0x00000004
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_13_PES_LAST_TRANS_SHIFT 2
-
-/* XPT_MEMDMA_MCPB :: DEBUG_13 :: PES_SKIP_PKT_BUF2SP_DONE [01:01] */
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_13_PES_SKIP_PKT_BUF2SP_DONE_MASK 0x00000002
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_13_PES_SKIP_PKT_BUF2SP_DONE_SHIFT 1
-
-/* XPT_MEMDMA_MCPB :: DEBUG_13 :: PES_PARSING_IN_PROGRESS [00:00] */
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_13_PES_PARSING_IN_PROGRESS_MASK 0x00000001
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_13_PES_PARSING_IN_PROGRESS_SHIFT 0
-
-/***************************************************************************
- *DEBUG_14 - Debug Register
- ***************************************************************************/
-/* XPT_MEMDMA_MCPB :: DEBUG_14 :: reserved0 [31:27] */
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_14_reserved0_MASK 0xf8000000
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_14_reserved0_SHIFT 27
-
-/* XPT_MEMDMA_MCPB :: DEBUG_14 :: VALUE_13 [26:22] */
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_14_VALUE_13_MASK 0x07c00000
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_14_VALUE_13_SHIFT 22
-
-/* XPT_MEMDMA_MCPB :: DEBUG_14 :: VALUE_12 [21:19] */
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_14_VALUE_12_MASK 0x00380000
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_14_VALUE_12_SHIFT 19
-
-/* XPT_MEMDMA_MCPB :: DEBUG_14 :: reserved1 [18:18] */
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_14_reserved1_MASK 0x00040000
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_14_reserved1_SHIFT 18
-
-/* XPT_MEMDMA_MCPB :: DEBUG_14 :: VALUE_11 [17:17] */
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_14_VALUE_11_MASK 0x00020000
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_14_VALUE_11_SHIFT 17
-
-/* XPT_MEMDMA_MCPB :: DEBUG_14 :: VALUE_10 [16:16] */
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_14_VALUE_10_MASK 0x00010000
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_14_VALUE_10_SHIFT 16
-
-/* XPT_MEMDMA_MCPB :: DEBUG_14 :: VALUE_9 [15:15] */
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_14_VALUE_9_MASK 0x00008000
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_14_VALUE_9_SHIFT 15
-
-/* XPT_MEMDMA_MCPB :: DEBUG_14 :: VALUE_8 [14:14] */
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_14_VALUE_8_MASK 0x00004000
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_14_VALUE_8_SHIFT 14
-
-/* XPT_MEMDMA_MCPB :: DEBUG_14 :: VALUE_7 [13:13] */
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_14_VALUE_7_MASK 0x00002000
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_14_VALUE_7_SHIFT 13
-
-/* XPT_MEMDMA_MCPB :: DEBUG_14 :: VALUE_6 [12:12] */
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_14_VALUE_6_MASK 0x00001000
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_14_VALUE_6_SHIFT 12
-
-/* XPT_MEMDMA_MCPB :: DEBUG_14 :: VALUE_5 [11:11] */
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_14_VALUE_5_MASK 0x00000800
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_14_VALUE_5_SHIFT 11
-
-/* XPT_MEMDMA_MCPB :: DEBUG_14 :: VALUE_4 [10:10] */
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_14_VALUE_4_MASK 0x00000400
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_14_VALUE_4_SHIFT 10
-
-/* XPT_MEMDMA_MCPB :: DEBUG_14 :: VALUE_3 [09:09] */
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_14_VALUE_3_MASK 0x00000200
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_14_VALUE_3_SHIFT 9
-
-/* XPT_MEMDMA_MCPB :: DEBUG_14 :: VALUE_2 [08:08] */
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_14_VALUE_2_MASK 0x00000100
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_14_VALUE_2_SHIFT 8
-
-/* XPT_MEMDMA_MCPB :: DEBUG_14 :: VALUE_1 [07:03] */
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_14_VALUE_1_MASK 0x000000f8
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_14_VALUE_1_SHIFT 3
-
-/* XPT_MEMDMA_MCPB :: DEBUG_14 :: VALUE_0 [02:00] */
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_14_VALUE_0_MASK 0x00000007
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_14_VALUE_0_SHIFT 0
-
-/***************************************************************************
- *DEBUG_15 - Debug Register
- ***************************************************************************/
-/* XPT_MEMDMA_MCPB :: DEBUG_15 :: reserved0 [31:28] */
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_15_reserved0_MASK 0xf0000000
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_15_reserved0_SHIFT 28
-
-/* XPT_MEMDMA_MCPB :: DEBUG_15 :: VALUE_5 [27:22] */
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_15_VALUE_5_MASK 0x0fc00000
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_15_VALUE_5_SHIFT 22
-
-/* XPT_MEMDMA_MCPB :: DEBUG_15 :: VALUE_4 [21:18] */
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_15_VALUE_4_MASK 0x003c0000
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_15_VALUE_4_SHIFT 18
-
-/* XPT_MEMDMA_MCPB :: DEBUG_15 :: VALUE_3 [17:16] */
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_15_VALUE_3_MASK 0x00030000
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_15_VALUE_3_SHIFT 16
-
-/* XPT_MEMDMA_MCPB :: DEBUG_15 :: reserved1 [15:11] */
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_15_reserved1_MASK 0x0000f800
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_15_reserved1_SHIFT 11
-
-/* XPT_MEMDMA_MCPB :: DEBUG_15 :: VALUE_2 [10:06] */
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_15_VALUE_2_MASK 0x000007c0
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_15_VALUE_2_SHIFT 6
-
-/* XPT_MEMDMA_MCPB :: DEBUG_15 :: VALUE_1 [05:02] */
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_15_VALUE_1_MASK 0x0000003c
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_15_VALUE_1_SHIFT 2
-
-/* XPT_MEMDMA_MCPB :: DEBUG_15 :: VALUE_0 [01:00] */
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_15_VALUE_0_MASK 0x00000003
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_15_VALUE_0_SHIFT 0
-
-/***************************************************************************
- *DEBUG_16 - Debug Register
- ***************************************************************************/
-/* XPT_MEMDMA_MCPB :: DEBUG_16 :: VALUE [31:00] */
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_16_VALUE_MASK 0xffffffff
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_16_VALUE_SHIFT 0
-
-/***************************************************************************
- *DEBUG_17 - Debug Register
- ***************************************************************************/
-/* XPT_MEMDMA_MCPB :: DEBUG_17 :: VALUE [31:00] */
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_17_VALUE_MASK 0xffffffff
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_17_VALUE_SHIFT 0
-
-/***************************************************************************
- *DEBUG_18 - Debug Register
- ***************************************************************************/
-/* XPT_MEMDMA_MCPB :: DEBUG_18 :: VALUE [31:00] */
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_18_VALUE_MASK 0xffffffff
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_18_VALUE_SHIFT 0
-
-/***************************************************************************
- *DEBUG_19 - Debug Register
- ***************************************************************************/
-/* XPT_MEMDMA_MCPB :: DEBUG_19 :: VALUE [31:00] */
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_19_VALUE_MASK 0xffffffff
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_19_VALUE_SHIFT 0
-
-/***************************************************************************
- *DEBUG_20 - Debug Register
- ***************************************************************************/
-/* XPT_MEMDMA_MCPB :: DEBUG_20 :: VALUE [31:00] */
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_20_VALUE_MASK 0xffffffff
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_20_VALUE_SHIFT 0
-
-/***************************************************************************
- *DEBUG_21 - Debug Register
- ***************************************************************************/
-/* XPT_MEMDMA_MCPB :: DEBUG_21 :: VALUE [31:00] */
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_21_VALUE_MASK 0xffffffff
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_21_VALUE_SHIFT 0
-
-/***************************************************************************
- *DEBUG_22 - Debug Register
- ***************************************************************************/
-/* XPT_MEMDMA_MCPB :: DEBUG_22 :: VALUE [31:00] */
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_22_VALUE_MASK 0xffffffff
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_22_VALUE_SHIFT 0
-
-/***************************************************************************
- *DEBUG_23 - Debug Register
- ***************************************************************************/
-/* XPT_MEMDMA_MCPB :: DEBUG_23 :: VALUE [31:00] */
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_23_VALUE_MASK 0xffffffff
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_23_VALUE_SHIFT 0
-
-/***************************************************************************
- *DEBUG_24 - Debug Register
- ***************************************************************************/
-/* XPT_MEMDMA_MCPB :: DEBUG_24 :: VALUE [31:00] */
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_24_VALUE_MASK 0xffffffff
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_24_VALUE_SHIFT 0
-
-/***************************************************************************
- *DEBUG_25 - Debug Register
- ***************************************************************************/
-/* XPT_MEMDMA_MCPB :: DEBUG_25 :: VALUE [31:00] */
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_25_VALUE_MASK 0xffffffff
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_25_VALUE_SHIFT 0
-
-/***************************************************************************
- *DEBUG_26 - Debug Register
- ***************************************************************************/
-/* XPT_MEMDMA_MCPB :: DEBUG_26 :: reserved0 [31:28] */
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_26_reserved0_MASK 0xf0000000
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_26_reserved0_SHIFT 28
-
-/* XPT_MEMDMA_MCPB :: DEBUG_26 :: VALUE_5 [27:22] */
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_26_VALUE_5_MASK 0x0fc00000
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_26_VALUE_5_SHIFT 22
-
-/* XPT_MEMDMA_MCPB :: DEBUG_26 :: VALUE_4 [21:18] */
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_26_VALUE_4_MASK 0x003c0000
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_26_VALUE_4_SHIFT 18
-
-/* XPT_MEMDMA_MCPB :: DEBUG_26 :: VALUE_3 [17:16] */
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_26_VALUE_3_MASK 0x00030000
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_26_VALUE_3_SHIFT 16
-
-/* XPT_MEMDMA_MCPB :: DEBUG_26 :: reserved1 [15:11] */
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_26_reserved1_MASK 0x0000f800
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_26_reserved1_SHIFT 11
-
-/* XPT_MEMDMA_MCPB :: DEBUG_26 :: VALUE_2 [10:06] */
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_26_VALUE_2_MASK 0x000007c0
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_26_VALUE_2_SHIFT 6
-
-/* XPT_MEMDMA_MCPB :: DEBUG_26 :: VALUE_1 [05:02] */
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_26_VALUE_1_MASK 0x0000003c
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_26_VALUE_1_SHIFT 2
-
-/* XPT_MEMDMA_MCPB :: DEBUG_26 :: VALUE_0 [01:00] */
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_26_VALUE_0_MASK 0x00000003
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_26_VALUE_0_SHIFT 0
-
-/***************************************************************************
- *DEBUG_27 - Debug Register
- ***************************************************************************/
-/* XPT_MEMDMA_MCPB :: DEBUG_27 :: BM_W0_OUT_DMA_END [31:31] */
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_27_BM_W0_OUT_DMA_END_MASK 0x80000000
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_27_BM_W0_OUT_DMA_END_SHIFT 31
-
-/* XPT_MEMDMA_MCPB :: DEBUG_27 :: BM_W1_OUT_DMA_END [30:30] */
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_27_BM_W1_OUT_DMA_END_MASK 0x40000000
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_27_BM_W1_OUT_DMA_END_SHIFT 30
-
-/* XPT_MEMDMA_MCPB :: DEBUG_27 :: BM_W2_OUT_DMA_END [29:29] */
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_27_BM_W2_OUT_DMA_END_MASK 0x20000000
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_27_BM_W2_OUT_DMA_END_SHIFT 29
-
-/* XPT_MEMDMA_MCPB :: DEBUG_27 :: BM_W3_OUT_DMA_END [28:28] */
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_27_BM_W3_OUT_DMA_END_MASK 0x10000000
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_27_BM_W3_OUT_DMA_END_SHIFT 28
-
-/* XPT_MEMDMA_MCPB :: DEBUG_27 :: BM_W4_OUT_DMA_END [27:27] */
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_27_BM_W4_OUT_DMA_END_MASK 0x08000000
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_27_BM_W4_OUT_DMA_END_SHIFT 27
-
-/* XPT_MEMDMA_MCPB :: DEBUG_27 :: BM_W5_OUT_DMA_END [26:26] */
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_27_BM_W5_OUT_DMA_END_MASK 0x04000000
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_27_BM_W5_OUT_DMA_END_SHIFT 26
-
-/* XPT_MEMDMA_MCPB :: DEBUG_27 :: BM_W0_OUT_READY [25:25] */
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_27_BM_W0_OUT_READY_MASK 0x02000000
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_27_BM_W0_OUT_READY_SHIFT 25
-
-/* XPT_MEMDMA_MCPB :: DEBUG_27 :: BM_W1_OUT_READY [24:24] */
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_27_BM_W1_OUT_READY_MASK 0x01000000
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_27_BM_W1_OUT_READY_SHIFT 24
-
-/* XPT_MEMDMA_MCPB :: DEBUG_27 :: BM_W2_OUT_READY [23:23] */
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_27_BM_W2_OUT_READY_MASK 0x00800000
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_27_BM_W2_OUT_READY_SHIFT 23
-
-/* XPT_MEMDMA_MCPB :: DEBUG_27 :: BM_W3_OUT_READY [22:22] */
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_27_BM_W3_OUT_READY_MASK 0x00400000
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_27_BM_W3_OUT_READY_SHIFT 22
-
-/* XPT_MEMDMA_MCPB :: DEBUG_27 :: BM_W4_OUT_READY [21:21] */
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_27_BM_W4_OUT_READY_MASK 0x00200000
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_27_BM_W4_OUT_READY_SHIFT 21
-
-/* XPT_MEMDMA_MCPB :: DEBUG_27 :: BM_W5_OUT_READY [20:20] */
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_27_BM_W5_OUT_READY_MASK 0x00100000
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_27_BM_W5_OUT_READY_SHIFT 20
-
-/* XPT_MEMDMA_MCPB :: DEBUG_27 :: BM_W5_OUT_ACCEPT [19:19] */
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_27_BM_W5_OUT_ACCEPT_MASK 0x00080000
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_27_BM_W5_OUT_ACCEPT_SHIFT 19
-
-/* XPT_MEMDMA_MCPB :: DEBUG_27 :: BM_W6_IN_ACCEPT [18:18] */
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_27_BM_W6_IN_ACCEPT_MASK 0x00040000
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_27_BM_W6_IN_ACCEPT_SHIFT 18
-
-/* XPT_MEMDMA_MCPB :: DEBUG_27 :: BM_W6_IN_READY [17:17] */
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_27_BM_W6_IN_READY_MASK 0x00020000
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_27_BM_W6_IN_READY_SHIFT 17
-
-/* XPT_MEMDMA_MCPB :: DEBUG_27 :: BM_STATE [16:13] */
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_27_BM_STATE_MASK 0x0001e000
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_27_BM_STATE_SHIFT 13
-
-/* XPT_MEMDMA_MCPB :: DEBUG_27 :: BM_BAND_ID [12:05] */
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_27_BM_BAND_ID_MASK 0x00001fe0
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_27_BM_BAND_ID_SHIFT 5
-
-/* XPT_MEMDMA_MCPB :: DEBUG_27 :: BM_PKT_BUF2SP_DONE [04:04] */
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_27_BM_PKT_BUF2SP_DONE_MASK 0x00000010
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_27_BM_PKT_BUF2SP_DONE_SHIFT 4
-
-/* XPT_MEMDMA_MCPB :: DEBUG_27 :: BM_CFG_DCP2SP_DONE [03:03] */
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_27_BM_CFG_DCP2SP_DONE_MASK 0x00000008
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_27_BM_CFG_DCP2SP_DONE_SHIFT 3
-
-/* XPT_MEMDMA_MCPB :: DEBUG_27 :: BM_CFG_DMA_SP2SP_DONE [02:02] */
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_27_BM_CFG_DMA_SP2SP_DONE_MASK 0x00000004
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_27_BM_CFG_DMA_SP2SP_DONE_SHIFT 2
-
-/* XPT_MEMDMA_MCPB :: DEBUG_27 :: BM_SMU2SP_DONE [01:01] */
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_27_BM_SMU2SP_DONE_MASK 0x00000002
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_27_BM_SMU2SP_DONE_SHIFT 1
-
-/* XPT_MEMDMA_MCPB :: DEBUG_27 :: BM_SP2DMA_START [00:00] */
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_27_BM_SP2DMA_START_MASK 0x00000001
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_27_BM_SP2DMA_START_SHIFT 0
-
-/***************************************************************************
- *DEBUG_28 - Debug Register
- ***************************************************************************/
-/* XPT_MEMDMA_MCPB :: DEBUG_28 :: reserved0 [31:12] */
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_28_reserved0_MASK 0xfffff000
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_28_reserved0_SHIFT 12
-
-/* XPT_MEMDMA_MCPB :: DEBUG_28 :: BM_NUM_BYTES [11:04] */
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_28_BM_NUM_BYTES_MASK 0x00000ff0
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_28_BM_NUM_BYTES_SHIFT 4
-
-/* XPT_MEMDMA_MCPB :: DEBUG_28 :: BM_PT_SEARCH_DONE [03:03] */
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_28_BM_PT_SEARCH_DONE_MASK 0x00000008
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_28_BM_PT_SEARCH_DONE_SHIFT 3
-
-/* XPT_MEMDMA_MCPB :: DEBUG_28 :: BM_DMA_END [02:02] */
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_28_BM_DMA_END_MASK 0x00000004
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_28_BM_DMA_END_SHIFT 2
-
-/* XPT_MEMDMA_MCPB :: DEBUG_28 :: BM_LAST_TRANS [01:01] */
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_28_BM_LAST_TRANS_MASK 0x00000002
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_28_BM_LAST_TRANS_SHIFT 1
-
-/* XPT_MEMDMA_MCPB :: DEBUG_28 :: BM_PARSING_IN_PROGRESS [00:00] */
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_28_BM_PARSING_IN_PROGRESS_MASK 0x00000001
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_28_BM_PARSING_IN_PROGRESS_SHIFT 0
-
-/***************************************************************************
- *DEBUG_29 - Debug Register
- ***************************************************************************/
-/* XPT_MEMDMA_MCPB :: DEBUG_29 :: reserved0 [31:11] */
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_29_reserved0_MASK 0xfffff800
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_29_reserved0_SHIFT 11
-
-/* XPT_MEMDMA_MCPB :: DEBUG_29 :: VALUE_2 [10:06] */
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_29_VALUE_2_MASK 0x000007c0
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_29_VALUE_2_SHIFT 6
-
-/* XPT_MEMDMA_MCPB :: DEBUG_29 :: VALUE_1 [05:02] */
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_29_VALUE_1_MASK 0x0000003c
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_29_VALUE_1_SHIFT 2
-
-/* XPT_MEMDMA_MCPB :: DEBUG_29 :: VALUE_0 [01:00] */
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_29_VALUE_0_MASK 0x00000003
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_29_VALUE_0_SHIFT 0
-
-/***************************************************************************
- *DEBUG_30 - Debug Register
- ***************************************************************************/
-/* XPT_MEMDMA_MCPB :: DEBUG_30 :: VALUE [31:00] */
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_30_VALUE_MASK 0xffffffff
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_30_VALUE_SHIFT 0
-
-/***************************************************************************
- *DEBUG_31 - Debug Register
- ***************************************************************************/
-/* XPT_MEMDMA_MCPB :: DEBUG_31 :: VALUE_12 [31:27] */
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_31_VALUE_12_MASK 0xf8000000
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_31_VALUE_12_SHIFT 27
-
-/* XPT_MEMDMA_MCPB :: DEBUG_31 :: VALUE_11 [26:18] */
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_31_VALUE_11_MASK 0x07fc0000
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_31_VALUE_11_SHIFT 18
-
-/* XPT_MEMDMA_MCPB :: DEBUG_31 :: VALUE_10 [17:17] */
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_31_VALUE_10_MASK 0x00020000
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_31_VALUE_10_SHIFT 17
-
-/* XPT_MEMDMA_MCPB :: DEBUG_31 :: VALUE_9 [16:16] */
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_31_VALUE_9_MASK 0x00010000
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_31_VALUE_9_SHIFT 16
-
-/* XPT_MEMDMA_MCPB :: DEBUG_31 :: VALUE_8 [15:15] */
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_31_VALUE_8_MASK 0x00008000
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_31_VALUE_8_SHIFT 15
-
-/* XPT_MEMDMA_MCPB :: DEBUG_31 :: VALUE_7 [14:14] */
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_31_VALUE_7_MASK 0x00004000
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_31_VALUE_7_SHIFT 14
-
-/* XPT_MEMDMA_MCPB :: DEBUG_31 :: VALUE_6 [13:13] */
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_31_VALUE_6_MASK 0x00002000
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_31_VALUE_6_SHIFT 13
-
-/* XPT_MEMDMA_MCPB :: DEBUG_31 :: VALUE_5 [12:12] */
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_31_VALUE_5_MASK 0x00001000
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_31_VALUE_5_SHIFT 12
-
-/* XPT_MEMDMA_MCPB :: DEBUG_31 :: VALUE_4 [11:04] */
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_31_VALUE_4_MASK 0x00000ff0
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_31_VALUE_4_SHIFT 4
-
-/* XPT_MEMDMA_MCPB :: DEBUG_31 :: VALUE_3 [03:03] */
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_31_VALUE_3_MASK 0x00000008
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_31_VALUE_3_SHIFT 3
-
-/* XPT_MEMDMA_MCPB :: DEBUG_31 :: VALUE_2 [02:02] */
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_31_VALUE_2_MASK 0x00000004
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_31_VALUE_2_SHIFT 2
-
-/* XPT_MEMDMA_MCPB :: DEBUG_31 :: VALUE_1 [01:01] */
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_31_VALUE_1_MASK 0x00000002
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_31_VALUE_1_SHIFT 1
-
-/* XPT_MEMDMA_MCPB :: DEBUG_31 :: VALUE_0 [00:00] */
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_31_VALUE_0_MASK 0x00000001
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_31_VALUE_0_SHIFT 0
-
-/***************************************************************************
- *DEBUG_32 - Debug Register
- ***************************************************************************/
-/* XPT_MEMDMA_MCPB :: DEBUG_32 :: reserved0 [31:21] */
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_32_reserved0_MASK 0xffe00000
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_32_reserved0_SHIFT 21
-
-/* XPT_MEMDMA_MCPB :: DEBUG_32 :: VALUE_8 [20:16] */
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_32_VALUE_8_MASK 0x001f0000
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_32_VALUE_8_SHIFT 16
-
-/* XPT_MEMDMA_MCPB :: DEBUG_32 :: VALUE_7 [15:07] */
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_32_VALUE_7_MASK 0x0000ff80
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_32_VALUE_7_SHIFT 7
-
-/* XPT_MEMDMA_MCPB :: DEBUG_32 :: VALUE_6 [06:06] */
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_32_VALUE_6_MASK 0x00000040
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_32_VALUE_6_SHIFT 6
-
-/* XPT_MEMDMA_MCPB :: DEBUG_32 :: VALUE_5 [05:05] */
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_32_VALUE_5_MASK 0x00000020
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_32_VALUE_5_SHIFT 5
-
-/* XPT_MEMDMA_MCPB :: DEBUG_32 :: VALUE_4 [04:04] */
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_32_VALUE_4_MASK 0x00000010
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_32_VALUE_4_SHIFT 4
-
-/* XPT_MEMDMA_MCPB :: DEBUG_32 :: VALUE_3 [03:03] */
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_32_VALUE_3_MASK 0x00000008
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_32_VALUE_3_SHIFT 3
-
-/* XPT_MEMDMA_MCPB :: DEBUG_32 :: VALUE_2 [02:02] */
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_32_VALUE_2_MASK 0x00000004
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_32_VALUE_2_SHIFT 2
-
-/* XPT_MEMDMA_MCPB :: DEBUG_32 :: VALUE_1 [01:01] */
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_32_VALUE_1_MASK 0x00000002
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_32_VALUE_1_SHIFT 1
-
-/* XPT_MEMDMA_MCPB :: DEBUG_32 :: VALUE_0 [00:00] */
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_32_VALUE_0_MASK 0x00000001
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_32_VALUE_0_SHIFT 0
-
-/***************************************************************************
- *DEBUG_33 - Debug Register
- ***************************************************************************/
-/* XPT_MEMDMA_MCPB :: DEBUG_33 :: reserved0 [31:26] */
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_33_reserved0_MASK 0xfc000000
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_33_reserved0_SHIFT 26
-
-/* XPT_MEMDMA_MCPB :: DEBUG_33 :: ASF_W0_OUT_DMA_END [25:25] */
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_33_ASF_W0_OUT_DMA_END_MASK 0x02000000
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_33_ASF_W0_OUT_DMA_END_SHIFT 25
-
-/* XPT_MEMDMA_MCPB :: DEBUG_33 :: ASF_W1_OUT_DMA_END [24:24] */
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_33_ASF_W1_OUT_DMA_END_MASK 0x01000000
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_33_ASF_W1_OUT_DMA_END_SHIFT 24
-
-/* XPT_MEMDMA_MCPB :: DEBUG_33 :: ASF_W2_OUT_DMA_END [23:23] */
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_33_ASF_W2_OUT_DMA_END_MASK 0x00800000
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_33_ASF_W2_OUT_DMA_END_SHIFT 23
-
-/* XPT_MEMDMA_MCPB :: DEBUG_33 :: ASF_W3_OUT_DMA_END [22:22] */
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_33_ASF_W3_OUT_DMA_END_MASK 0x00400000
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_33_ASF_W3_OUT_DMA_END_SHIFT 22
-
-/* XPT_MEMDMA_MCPB :: DEBUG_33 :: ASF_W4_OUT_DMA_END [21:21] */
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_33_ASF_W4_OUT_DMA_END_MASK 0x00200000
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_33_ASF_W4_OUT_DMA_END_SHIFT 21
-
-/* XPT_MEMDMA_MCPB :: DEBUG_33 :: ASF_W0_OUT_READY [20:20] */
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_33_ASF_W0_OUT_READY_MASK 0x00100000
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_33_ASF_W0_OUT_READY_SHIFT 20
-
-/* XPT_MEMDMA_MCPB :: DEBUG_33 :: ASF_W1_OUT_READY [19:19] */
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_33_ASF_W1_OUT_READY_MASK 0x00080000
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_33_ASF_W1_OUT_READY_SHIFT 19
-
-/* XPT_MEMDMA_MCPB :: DEBUG_33 :: ASF_W2_OUT_READY [18:18] */
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_33_ASF_W2_OUT_READY_MASK 0x00040000
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_33_ASF_W2_OUT_READY_SHIFT 18
-
-/* XPT_MEMDMA_MCPB :: DEBUG_33 :: ASF_W3_OUT_READY [17:17] */
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_33_ASF_W3_OUT_READY_MASK 0x00020000
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_33_ASF_W3_OUT_READY_SHIFT 17
-
-/* XPT_MEMDMA_MCPB :: DEBUG_33 :: ASF_W4_OUT_READY [16:16] */
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_33_ASF_W4_OUT_READY_MASK 0x00010000
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_33_ASF_W4_OUT_READY_SHIFT 16
-
-/* XPT_MEMDMA_MCPB :: DEBUG_33 :: ASF_W4_OUT_ACCEPT [15:15] */
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_33_ASF_W4_OUT_ACCEPT_MASK 0x00008000
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_33_ASF_W4_OUT_ACCEPT_SHIFT 15
-
-/* XPT_MEMDMA_MCPB :: DEBUG_33 :: ASF_W5_IN_ACCEPT [14:14] */
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_33_ASF_W5_IN_ACCEPT_MASK 0x00004000
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_33_ASF_W5_IN_ACCEPT_SHIFT 14
-
-/* XPT_MEMDMA_MCPB :: DEBUG_33 :: ASF_W5_IN_READY [13:13] */
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_33_ASF_W5_IN_READY_MASK 0x00002000
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_33_ASF_W5_IN_READY_SHIFT 13
-
-/* XPT_MEMDMA_MCPB :: DEBUG_33 :: ASF_BAND_ID [12:05] */
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_33_ASF_BAND_ID_MASK 0x00001fe0
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_33_ASF_BAND_ID_SHIFT 5
-
-/* XPT_MEMDMA_MCPB :: DEBUG_33 :: ASF_PKT_BUF2SP_DONE [04:04] */
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_33_ASF_PKT_BUF2SP_DONE_MASK 0x00000010
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_33_ASF_PKT_BUF2SP_DONE_SHIFT 4
-
-/* XPT_MEMDMA_MCPB :: DEBUG_33 :: ASF_CFG_DCP2SP_DONE [03:03] */
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_33_ASF_CFG_DCP2SP_DONE_MASK 0x00000008
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_33_ASF_CFG_DCP2SP_DONE_SHIFT 3
-
-/* XPT_MEMDMA_MCPB :: DEBUG_33 :: ASF_CFG_DMA_SP2SP_DONE [02:02] */
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_33_ASF_CFG_DMA_SP2SP_DONE_MASK 0x00000004
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_33_ASF_CFG_DMA_SP2SP_DONE_SHIFT 2
-
-/* XPT_MEMDMA_MCPB :: DEBUG_33 :: ASF_SMU2SP_DONE [01:01] */
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_33_ASF_SMU2SP_DONE_MASK 0x00000002
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_33_ASF_SMU2SP_DONE_SHIFT 1
-
-/* XPT_MEMDMA_MCPB :: DEBUG_33 :: ASF_SP2DMA_START [00:00] */
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_33_ASF_SP2DMA_START_MASK 0x00000001
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_33_ASF_SP2DMA_START_SHIFT 0
-
-/***************************************************************************
- *DEBUG_34 - Debug Register
- ***************************************************************************/
-/* XPT_MEMDMA_MCPB :: DEBUG_34 :: reserved0 [31:15] */
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_34_reserved0_MASK 0xffff8000
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_34_reserved0_SHIFT 15
-
-/* XPT_MEMDMA_MCPB :: DEBUG_34 :: ASF_STATE [14:08] */
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_34_ASF_STATE_MASK 0x00007f00
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_34_ASF_STATE_SHIFT 8
-
-/* XPT_MEMDMA_MCPB :: DEBUG_34 :: ASF_PT_SEARCH_IN_PROGRESS [07:07] */
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_34_ASF_PT_SEARCH_IN_PROGRESS_MASK 0x00000080
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_34_ASF_PT_SEARCH_IN_PROGRESS_SHIFT 7
-
-/* XPT_MEMDMA_MCPB :: DEBUG_34 :: ASF_PT_SEARCH_DONE [06:06] */
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_34_ASF_PT_SEARCH_DONE_MASK 0x00000040
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_34_ASF_PT_SEARCH_DONE_SHIFT 6
-
-/* XPT_MEMDMA_MCPB :: DEBUG_34 :: ASF_DMA_END [05:05] */
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_34_ASF_DMA_END_MASK 0x00000020
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_34_ASF_DMA_END_SHIFT 5
-
-/* XPT_MEMDMA_MCPB :: DEBUG_34 :: ASF_PKT_END [04:04] */
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_34_ASF_PKT_END_MASK 0x00000010
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_34_ASF_PKT_END_SHIFT 4
-
-/* XPT_MEMDMA_MCPB :: DEBUG_34 :: ASF_PKT_DONE [03:03] */
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_34_ASF_PKT_DONE_MASK 0x00000008
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_34_ASF_PKT_DONE_SHIFT 3
-
-/* XPT_MEMDMA_MCPB :: DEBUG_34 :: ASF_LAST_TRANS [02:02] */
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_34_ASF_LAST_TRANS_MASK 0x00000004
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_34_ASF_LAST_TRANS_SHIFT 2
-
-/* XPT_MEMDMA_MCPB :: DEBUG_34 :: ASF_SKIP_PKT_BUF2SP_DONE [01:01] */
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_34_ASF_SKIP_PKT_BUF2SP_DONE_MASK 0x00000002
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_34_ASF_SKIP_PKT_BUF2SP_DONE_SHIFT 1
-
-/* XPT_MEMDMA_MCPB :: DEBUG_34 :: ASF_PARSING_IN_PROGRESS [00:00] */
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_34_ASF_PARSING_IN_PROGRESS_MASK 0x00000001
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_34_ASF_PARSING_IN_PROGRESS_SHIFT 0
-
-/***************************************************************************
- *DEBUG_35 - Debug Register
- ***************************************************************************/
-/* XPT_MEMDMA_MCPB :: DEBUG_35 :: reserved0 [31:29] */
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_35_reserved0_MASK 0xe0000000
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_35_reserved0_SHIFT 29
-
-/* XPT_MEMDMA_MCPB :: DEBUG_35 :: SP_SLOT_BUS_DCP_SLOT_VALID [28:28] */
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_35_SP_SLOT_BUS_DCP_SLOT_VALID_MASK 0x10000000
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_35_SP_SLOT_BUS_DCP_SLOT_VALID_SHIFT 28
-
-/* XPT_MEMDMA_MCPB :: DEBUG_35 :: SP_TIME_OUT [27:27] */
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_35_SP_TIME_OUT_MASK 0x08000000
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_35_SP_TIME_OUT_SHIFT 27
-
-/* XPT_MEMDMA_MCPB :: DEBUG_35 :: DMA2SP_MCPB_CH_NUM [26:22] */
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_35_DMA2SP_MCPB_CH_NUM_MASK 0x07c00000
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_35_DMA2SP_MCPB_CH_NUM_SHIFT 22
-
-/* XPT_MEMDMA_MCPB :: DEBUG_35 :: PARSER_STREAM_TYPE [21:19] */
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_35_PARSER_STREAM_TYPE_MASK 0x00380000
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_35_PARSER_STREAM_TYPE_SHIFT 19
-
-/* XPT_MEMDMA_MCPB :: DEBUG_35 :: DMA2SP_PKT_SLOT_NUM [18:18] */
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_35_DMA2SP_PKT_SLOT_NUM_MASK 0x00040000
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_35_DMA2SP_PKT_SLOT_NUM_SHIFT 18
-
-/* XPT_MEMDMA_MCPB :: DEBUG_35 :: DMA2SP_DCP_SLOT_NUM [17:17] */
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_35_DMA2SP_DCP_SLOT_NUM_MASK 0x00020000
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_35_DMA2SP_DCP_SLOT_NUM_SHIFT 17
-
-/* XPT_MEMDMA_MCPB :: DEBUG_35 :: DMA2SP_DESC_SLOT_NUM [16:16] */
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_35_DMA2SP_DESC_SLOT_NUM_MASK 0x00010000
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_35_DMA2SP_DESC_SLOT_NUM_SHIFT 16
-
-/* XPT_MEMDMA_MCPB :: DEBUG_35 :: DMA2SP_PKT_SLOT_IN_USE [15:15] */
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_35_DMA2SP_PKT_SLOT_IN_USE_MASK 0x00008000
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_35_DMA2SP_PKT_SLOT_IN_USE_SHIFT 15
-
-/* XPT_MEMDMA_MCPB :: DEBUG_35 :: DMA2SP_D_REGION [14:07] */
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_35_DMA2SP_D_REGION_MASK 0x00007f80
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_35_DMA2SP_D_REGION_SHIFT 7
-
-/* XPT_MEMDMA_MCPB :: DEBUG_35 :: DMA2SP_ZERO_BYTE_TRANS [06:06] */
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_35_DMA2SP_ZERO_BYTE_TRANS_MASK 0x00000040
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_35_DMA2SP_ZERO_BYTE_TRANS_SHIFT 6
-
-/* XPT_MEMDMA_MCPB :: DEBUG_35 :: DMA2SP_FIRST_PKT_AFT_RUN_ASSERT [05:05] */
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_35_DMA2SP_FIRST_PKT_AFT_RUN_ASSERT_MASK 0x00000020
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_35_DMA2SP_FIRST_PKT_AFT_RUN_ASSERT_SHIFT 5
-
-/* XPT_MEMDMA_MCPB :: DEBUG_35 :: DMA2SP_LAST_TRANS [04:04] */
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_35_DMA2SP_LAST_TRANS_MASK 0x00000010
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_35_DMA2SP_LAST_TRANS_SHIFT 4
-
-/* XPT_MEMDMA_MCPB :: DEBUG_35 :: DMA2SP_RESET_PARSER [03:03] */
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_35_DMA2SP_RESET_PARSER_MASK 0x00000008
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_35_DMA2SP_RESET_PARSER_SHIFT 3
-
-/* XPT_MEMDMA_MCPB :: DEBUG_35 :: DMA2SP_PUSH_RESIDUAL_BYTES [02:02] */
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_35_DMA2SP_PUSH_RESIDUAL_BYTES_MASK 0x00000004
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_35_DMA2SP_PUSH_RESIDUAL_BYTES_SHIFT 2
-
-/* XPT_MEMDMA_MCPB :: DEBUG_35 :: DMA2SP_FORCE_TS_CFG [01:01] */
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_35_DMA2SP_FORCE_TS_CFG_MASK 0x00000002
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_35_DMA2SP_FORCE_TS_CFG_SHIFT 1
-
-/* XPT_MEMDMA_MCPB :: DEBUG_35 :: DMA2SP_GEN_BTP_PKT [00:00] */
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_35_DMA2SP_GEN_BTP_PKT_MASK 0x00000001
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_35_DMA2SP_GEN_BTP_PKT_SHIFT 0
-
-/***************************************************************************
- *DEBUG_36 - Debug Register
- ***************************************************************************/
-/* XPT_MEMDMA_MCPB :: DEBUG_36 :: DMA2SP_NUM_BYTES [31:23] */
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_36_DMA2SP_NUM_BYTES_MASK 0xff800000
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_36_DMA2SP_NUM_BYTES_SHIFT 23
-
-/* XPT_MEMDMA_MCPB :: DEBUG_36 :: SP_SLOT_BYS_PKT_SLOT_VALID [22:22] */
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_36_SP_SLOT_BYS_PKT_SLOT_VALID_MASK 0x00400000
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_36_SP_SLOT_BYS_PKT_SLOT_VALID_SHIFT 22
-
-/* XPT_MEMDMA_MCPB :: DEBUG_36 :: SP_SLOT_BUS_PKT_SLOT_IN_USE [21:21] */
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_36_SP_SLOT_BUS_PKT_SLOT_IN_USE_MASK 0x00200000
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_36_SP_SLOT_BUS_PKT_SLOT_IN_USE_SHIFT 21
-
-/* XPT_MEMDMA_MCPB :: DEBUG_36 :: SP_SLOT_BUS_OP_PIPE_SEL [20:18] */
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_36_SP_SLOT_BUS_OP_PIPE_SEL_MASK 0x001c0000
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_36_SP_SLOT_BUS_OP_PIPE_SEL_SHIFT 18
-
-/* XPT_MEMDMA_MCPB :: DEBUG_36 :: SP_SLOT_BUS_NUM_OF_DUP [17:14] */
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_36_SP_SLOT_BUS_NUM_OF_DUP_MASK 0x0003c000
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_36_SP_SLOT_BUS_NUM_OF_DUP_SHIFT 14
-
-/* XPT_MEMDMA_MCPB :: DEBUG_36 :: SP_SLOT_BUS_DCP_ONLY_FOR_PES_PACING [13:13] */
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_36_SP_SLOT_BUS_DCP_ONLY_FOR_PES_PACING_MASK 0x00002000
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_36_SP_SLOT_BUS_DCP_ONLY_FOR_PES_PACING_SHIFT 13
-
-/* XPT_MEMDMA_MCPB :: DEBUG_36 :: SP_SLOT_BUS_DROP_THE_PKT [12:12] */
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_36_SP_SLOT_BUS_DROP_THE_PKT_MASK 0x00001000
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_36_SP_SLOT_BUS_DROP_THE_PKT_SHIFT 12
-
-/* XPT_MEMDMA_MCPB :: DEBUG_36 :: SP_SLOT_BUS_PKT_SLOT_IN_USE_FOR_PES_PACING [11:11] */
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_36_SP_SLOT_BUS_PKT_SLOT_IN_USE_FOR_PES_PACING_MASK 0x00000800
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_36_SP_SLOT_BUS_PKT_SLOT_IN_USE_FOR_PES_PACING_SHIFT 11
-
-/* XPT_MEMDMA_MCPB :: DEBUG_36 :: SP_SLOT_BUS_ASF_PD_PKT_COMPLETE [10:10] */
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_36_SP_SLOT_BUS_ASF_PD_PKT_COMPLETE_MASK 0x00000400
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_36_SP_SLOT_BUS_ASF_PD_PKT_COMPLETE_SHIFT 10
-
-/* XPT_MEMDMA_MCPB :: DEBUG_36 :: SP_SLOT_BUS_PKT_DROP_AS_RUN_INVALID [09:09] */
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_36_SP_SLOT_BUS_PKT_DROP_AS_RUN_INVALID_MASK 0x00000200
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_36_SP_SLOT_BUS_PKT_DROP_AS_RUN_INVALID_SHIFT 9
-
-/* XPT_MEMDMA_MCPB :: DEBUG_36 :: SP_SLOT_BUS_NUM_BYTES [08:00] */
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_36_SP_SLOT_BUS_NUM_BYTES_MASK 0x000001ff
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_36_SP_SLOT_BUS_NUM_BYTES_SHIFT 0
-
-/***************************************************************************
- *DEBUG_37 - Debug Register
- ***************************************************************************/
-/* XPT_MEMDMA_MCPB :: DEBUG_37 :: reserved0 [31:25] */
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_37_reserved0_MASK 0xfe000000
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_37_reserved0_SHIFT 25
-
-/* XPT_MEMDMA_MCPB :: DEBUG_37 :: PKT_BUF_32_SP_READY [24:24] */
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_37_PKT_BUF_32_SP_READY_MASK 0x01000000
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_37_PKT_BUF_32_SP_READY_SHIFT 24
-
-/* XPT_MEMDMA_MCPB :: DEBUG_37 :: PKT_BUF_32_SP_ACCEPT [23:23] */
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_37_PKT_BUF_32_SP_ACCEPT_MASK 0x00800000
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_37_PKT_BUF_32_SP_ACCEPT_SHIFT 23
-
-/* XPT_MEMDMA_MCPB :: DEBUG_37 :: PKT_BUF_32_SP_DROP_FLAG [22:22] */
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_37_PKT_BUF_32_SP_DROP_FLAG_MASK 0x00400000
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_37_PKT_BUF_32_SP_DROP_FLAG_SHIFT 22
-
-/* XPT_MEMDMA_MCPB :: DEBUG_37 :: PKT_BUF_32_SP_DMA_END [21:21] */
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_37_PKT_BUF_32_SP_DMA_END_MASK 0x00200000
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_37_PKT_BUF_32_SP_DMA_END_SHIFT 21
-
-/* XPT_MEMDMA_MCPB :: DEBUG_37 :: PKT_BUF_32_OUT_BYTE_EN [20:13] */
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_37_PKT_BUF_32_OUT_BYTE_EN_MASK 0x001fe000
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_37_PKT_BUF_32_OUT_BYTE_EN_SHIFT 13
-
-/* XPT_MEMDMA_MCPB :: DEBUG_37 :: PKT_BUF_32_OUT_READY [12:12] */
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_37_PKT_BUF_32_OUT_READY_MASK 0x00001000
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_37_PKT_BUF_32_OUT_READY_SHIFT 12
-
-/* XPT_MEMDMA_MCPB :: DEBUG_37 :: PKT_BUF_32_OUT_ACCEPT [11:11] */
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_37_PKT_BUF_32_OUT_ACCEPT_MASK 0x00000800
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_37_PKT_BUF_32_OUT_ACCEPT_SHIFT 11
-
-/* XPT_MEMDMA_MCPB :: DEBUG_37 :: PKT_BUF_32_OFFSET_ADDR [10:03] */
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_37_PKT_BUF_32_OFFSET_ADDR_MASK 0x000007f8
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_37_PKT_BUF_32_OFFSET_ADDR_SHIFT 3
-
-/* XPT_MEMDMA_MCPB :: DEBUG_37 :: PKT_BUF_32_IN_STATE [02:00] */
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_37_PKT_BUF_32_IN_STATE_MASK 0x00000007
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_37_PKT_BUF_32_IN_STATE_SHIFT 0
-
-/***************************************************************************
- *DEBUG_38 - Debug Register
- ***************************************************************************/
-/* XPT_MEMDMA_MCPB :: DEBUG_38 :: reserved0 [31:26] */
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_38_reserved0_MASK 0xfc000000
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_38_reserved0_SHIFT 26
-
-/* XPT_MEMDMA_MCPB :: DEBUG_38 :: PKT_BUF_8_SP_READY [25:25] */
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_38_PKT_BUF_8_SP_READY_MASK 0x02000000
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_38_PKT_BUF_8_SP_READY_SHIFT 25
-
-/* XPT_MEMDMA_MCPB :: DEBUG_38 :: PKT_BUF_8_SP_ACCEPT [24:24] */
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_38_PKT_BUF_8_SP_ACCEPT_MASK 0x01000000
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_38_PKT_BUF_8_SP_ACCEPT_SHIFT 24
-
-/* XPT_MEMDMA_MCPB :: DEBUG_38 :: PKT_BUF_8_SP_DROP_FLAG [23:23] */
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_38_PKT_BUF_8_SP_DROP_FLAG_MASK 0x00800000
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_38_PKT_BUF_8_SP_DROP_FLAG_SHIFT 23
-
-/* XPT_MEMDMA_MCPB :: DEBUG_38 :: PKT_BUF_8_SP_DMA_END [22:22] */
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_38_PKT_BUF_8_SP_DMA_END_MASK 0x00400000
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_38_PKT_BUF_8_SP_DMA_END_SHIFT 22
-
-/* XPT_MEMDMA_MCPB :: DEBUG_38 :: PKT_BUF_8_OUT_BYTE_EN [21:14] */
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_38_PKT_BUF_8_OUT_BYTE_EN_MASK 0x003fc000
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_38_PKT_BUF_8_OUT_BYTE_EN_SHIFT 14
-
-/* XPT_MEMDMA_MCPB :: DEBUG_38 :: PKT_BUF_8_OUT_READY [13:13] */
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_38_PKT_BUF_8_OUT_READY_MASK 0x00002000
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_38_PKT_BUF_8_OUT_READY_SHIFT 13
-
-/* XPT_MEMDMA_MCPB :: DEBUG_38 :: PKT_BUF_8_OUT_ACCEPT [12:12] */
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_38_PKT_BUF_8_OUT_ACCEPT_MASK 0x00001000
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_38_PKT_BUF_8_OUT_ACCEPT_SHIFT 12
-
-/* XPT_MEMDMA_MCPB :: DEBUG_38 :: PKT_BUF_8_OFFSET_ADDR [11:04] */
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_38_PKT_BUF_8_OFFSET_ADDR_MASK 0x00000ff0
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_38_PKT_BUF_8_OFFSET_ADDR_SHIFT 4
-
-/* XPT_MEMDMA_MCPB :: DEBUG_38 :: PKT_BUF_8_IN_STATE [03:00] */
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_38_PKT_BUF_8_IN_STATE_MASK 0x0000000f
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_38_PKT_BUF_8_IN_STATE_SHIFT 0
-
-/***************************************************************************
- *SP_TIME_OUT_THRESHOLD - SP Timeout Threshold
- ***************************************************************************/
-/* XPT_MEMDMA_MCPB :: SP_TIME_OUT_THRESHOLD :: reserved0 [31:14] */
-#define BCHP_XPT_MEMDMA_MCPB_SP_TIME_OUT_THRESHOLD_reserved0_MASK 0xffffc000
-#define BCHP_XPT_MEMDMA_MCPB_SP_TIME_OUT_THRESHOLD_reserved0_SHIFT 14
-
-/* XPT_MEMDMA_MCPB :: SP_TIME_OUT_THRESHOLD :: AUTO_RECOVER_EN [13:13] */
-#define BCHP_XPT_MEMDMA_MCPB_SP_TIME_OUT_THRESHOLD_AUTO_RECOVER_EN_MASK 0x00002000
-#define BCHP_XPT_MEMDMA_MCPB_SP_TIME_OUT_THRESHOLD_AUTO_RECOVER_EN_SHIFT 13
-#define BCHP_XPT_MEMDMA_MCPB_SP_TIME_OUT_THRESHOLD_AUTO_RECOVER_EN_DEFAULT 0x00000001
-
-/* XPT_MEMDMA_MCPB :: SP_TIME_OUT_THRESHOLD :: TIMEOUT_INTR_EN [12:12] */
-#define BCHP_XPT_MEMDMA_MCPB_SP_TIME_OUT_THRESHOLD_TIMEOUT_INTR_EN_MASK 0x00001000
-#define BCHP_XPT_MEMDMA_MCPB_SP_TIME_OUT_THRESHOLD_TIMEOUT_INTR_EN_SHIFT 12
-#define BCHP_XPT_MEMDMA_MCPB_SP_TIME_OUT_THRESHOLD_TIMEOUT_INTR_EN_DEFAULT 0x00000001
-
-/* XPT_MEMDMA_MCPB :: SP_TIME_OUT_THRESHOLD :: SP_TIMEOUT_THRESHOLD [11:00] */
-#define BCHP_XPT_MEMDMA_MCPB_SP_TIME_OUT_THRESHOLD_SP_TIMEOUT_THRESHOLD_MASK 0x00000fff
-#define BCHP_XPT_MEMDMA_MCPB_SP_TIME_OUT_THRESHOLD_SP_TIMEOUT_THRESHOLD_SHIFT 0
-#define BCHP_XPT_MEMDMA_MCPB_SP_TIME_OUT_THRESHOLD_SP_TIMEOUT_THRESHOLD_DEFAULT 0x00000400
-
-/***************************************************************************
- *DEBUG_SP_FORCE_RECOVER - Debug SP Force Recover
- ***************************************************************************/
-/* XPT_MEMDMA_MCPB :: DEBUG_SP_FORCE_RECOVER :: reserved0 [31:05] */
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_SP_FORCE_RECOVER_reserved0_MASK 0xffffffe0
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_SP_FORCE_RECOVER_reserved0_SHIFT 5
-
-/* XPT_MEMDMA_MCPB :: DEBUG_SP_FORCE_RECOVER :: SP_FORCE_AUTO_RECOVER [04:04] */
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_SP_FORCE_RECOVER_SP_FORCE_AUTO_RECOVER_MASK 0x00000010
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_SP_FORCE_RECOVER_SP_FORCE_AUTO_RECOVER_SHIFT 4
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_SP_FORCE_RECOVER_SP_FORCE_AUTO_RECOVER_DEFAULT 0x00000000
-
-/* XPT_MEMDMA_MCPB :: DEBUG_SP_FORCE_RECOVER :: SP_FORCE_CFG_DCP_WRITE [03:03] */
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_SP_FORCE_RECOVER_SP_FORCE_CFG_DCP_WRITE_MASK 0x00000008
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_SP_FORCE_RECOVER_SP_FORCE_CFG_DCP_WRITE_SHIFT 3
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_SP_FORCE_RECOVER_SP_FORCE_CFG_DCP_WRITE_DEFAULT 0x00000000
-
-/* XPT_MEMDMA_MCPB :: DEBUG_SP_FORCE_RECOVER :: SP_FORCE_CFG_DMA_SP_WRITE [02:02] */
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_SP_FORCE_RECOVER_SP_FORCE_CFG_DMA_SP_WRITE_MASK 0x00000004
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_SP_FORCE_RECOVER_SP_FORCE_CFG_DMA_SP_WRITE_SHIFT 2
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_SP_FORCE_RECOVER_SP_FORCE_CFG_DMA_SP_WRITE_DEFAULT 0x00000000
-
-/* XPT_MEMDMA_MCPB :: DEBUG_SP_FORCE_RECOVER :: SP_FORCE_SMU_SLOT_BUS_START [01:01] */
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_SP_FORCE_RECOVER_SP_FORCE_SMU_SLOT_BUS_START_MASK 0x00000002
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_SP_FORCE_RECOVER_SP_FORCE_SMU_SLOT_BUS_START_SHIFT 1
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_SP_FORCE_RECOVER_SP_FORCE_SMU_SLOT_BUS_START_DEFAULT 0x00000000
-
-/* XPT_MEMDMA_MCPB :: DEBUG_SP_FORCE_RECOVER :: SP_FORCE_DMA_SLOT_BUS_START [00:00] */
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_SP_FORCE_RECOVER_SP_FORCE_DMA_SLOT_BUS_START_MASK 0x00000001
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_SP_FORCE_RECOVER_SP_FORCE_DMA_SLOT_BUS_START_SHIFT 0
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_SP_FORCE_RECOVER_SP_FORCE_DMA_SLOT_BUS_START_DEFAULT 0x00000000
-
-/***************************************************************************
- *DEBUG_SP_TX_SLOT_CMD_AUTO_RECOVER_OVERWR - Debug SP TX Overwrite Slot Cmd Auto Recover Overwrite
- ***************************************************************************/
-/* XPT_MEMDMA_MCPB :: DEBUG_SP_TX_SLOT_CMD_AUTO_RECOVER_OVERWR :: reserved0 [31:14] */
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_SP_TX_SLOT_CMD_AUTO_RECOVER_OVERWR_reserved0_MASK 0xffffc000
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_SP_TX_SLOT_CMD_AUTO_RECOVER_OVERWR_reserved0_SHIFT 14
-
-/* XPT_MEMDMA_MCPB :: DEBUG_SP_TX_SLOT_CMD_AUTO_RECOVER_OVERWR :: PKT_SLOT_VALID [13:12] */
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_SP_TX_SLOT_CMD_AUTO_RECOVER_OVERWR_PKT_SLOT_VALID_MASK 0x00003000
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_SP_TX_SLOT_CMD_AUTO_RECOVER_OVERWR_PKT_SLOT_VALID_SHIFT 12
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_SP_TX_SLOT_CMD_AUTO_RECOVER_OVERWR_PKT_SLOT_VALID_DEFAULT 0x00000000
-
-/* XPT_MEMDMA_MCPB :: DEBUG_SP_TX_SLOT_CMD_AUTO_RECOVER_OVERWR :: PKT_SLOT_IN_USE [11:10] */
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_SP_TX_SLOT_CMD_AUTO_RECOVER_OVERWR_PKT_SLOT_IN_USE_MASK 0x00000c00
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_SP_TX_SLOT_CMD_AUTO_RECOVER_OVERWR_PKT_SLOT_IN_USE_SHIFT 10
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_SP_TX_SLOT_CMD_AUTO_RECOVER_OVERWR_PKT_SLOT_IN_USE_DEFAULT 0x00000000
-
-/* XPT_MEMDMA_MCPB :: DEBUG_SP_TX_SLOT_CMD_AUTO_RECOVER_OVERWR :: RETRANSMIT_SLOT_CMD [09:08] */
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_SP_TX_SLOT_CMD_AUTO_RECOVER_OVERWR_RETRANSMIT_SLOT_CMD_MASK 0x00000300
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_SP_TX_SLOT_CMD_AUTO_RECOVER_OVERWR_RETRANSMIT_SLOT_CMD_SHIFT 8
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_SP_TX_SLOT_CMD_AUTO_RECOVER_OVERWR_RETRANSMIT_SLOT_CMD_DEFAULT 0x00000000
-
-/* XPT_MEMDMA_MCPB :: DEBUG_SP_TX_SLOT_CMD_AUTO_RECOVER_OVERWR :: LAST_DATA_TRANS [07:06] */
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_SP_TX_SLOT_CMD_AUTO_RECOVER_OVERWR_LAST_DATA_TRANS_MASK 0x000000c0
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_SP_TX_SLOT_CMD_AUTO_RECOVER_OVERWR_LAST_DATA_TRANS_SHIFT 6
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_SP_TX_SLOT_CMD_AUTO_RECOVER_OVERWR_LAST_DATA_TRANS_DEFAULT 0x00000002
-
-/* XPT_MEMDMA_MCPB :: DEBUG_SP_TX_SLOT_CMD_AUTO_RECOVER_OVERWR :: DROP_THE_PACKET [05:04] */
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_SP_TX_SLOT_CMD_AUTO_RECOVER_OVERWR_DROP_THE_PACKET_MASK 0x00000030
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_SP_TX_SLOT_CMD_AUTO_RECOVER_OVERWR_DROP_THE_PACKET_SHIFT 4
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_SP_TX_SLOT_CMD_AUTO_RECOVER_OVERWR_DROP_THE_PACKET_DEFAULT 0x00000001
-
-/* XPT_MEMDMA_MCPB :: DEBUG_SP_TX_SLOT_CMD_AUTO_RECOVER_OVERWR :: ASF_PD_PKT_COMPLETE [03:02] */
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_SP_TX_SLOT_CMD_AUTO_RECOVER_OVERWR_ASF_PD_PKT_COMPLETE_MASK 0x0000000c
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_SP_TX_SLOT_CMD_AUTO_RECOVER_OVERWR_ASF_PD_PKT_COMPLETE_SHIFT 2
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_SP_TX_SLOT_CMD_AUTO_RECOVER_OVERWR_ASF_PD_PKT_COMPLETE_DEFAULT 0x00000000
-
-/* XPT_MEMDMA_MCPB :: DEBUG_SP_TX_SLOT_CMD_AUTO_RECOVER_OVERWR :: PKT_DROP_AS_RUN_INVALID [01:00] */
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_SP_TX_SLOT_CMD_AUTO_RECOVER_OVERWR_PKT_DROP_AS_RUN_INVALID_MASK 0x00000003
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_SP_TX_SLOT_CMD_AUTO_RECOVER_OVERWR_PKT_DROP_AS_RUN_INVALID_SHIFT 0
-#define BCHP_XPT_MEMDMA_MCPB_DEBUG_SP_TX_SLOT_CMD_AUTO_RECOVER_OVERWR_PKT_DROP_AS_RUN_INVALID_DEFAULT 0x00000002
-
-#endif /* #ifndef BCHP_XPT_MEMDMA_MCPB_H__ */
-
-/* End of File */
diff --git a/include/linux/brcmstb/7366b0/bchp_xpt_memdma_mcpb_ch0.h b/include/linux/brcmstb/7366b0/bchp_xpt_memdma_mcpb_ch0.h
deleted file mode 100644
index 7fdaba9..0000000
--- a/include/linux/brcmstb/7366b0/bchp_xpt_memdma_mcpb_ch0.h
+++ /dev/null
@@ -1,2319 +0,0 @@
-/***************************************************************************
- * Copyright (c) 1999-2014, Broadcom Corporation
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
- *
- * Module Description:
- * DO NOT EDIT THIS FILE DIRECTLY
- *
- * This module was generated magically with RDB from a source description
- * file. You must edit the source file for changes to be made to this file.
- *
- *
- * Date: Generated on Sat Apr 12 03:17:57 2014
- * Full Compile MD5 Checksum 5f2af4819d5a3039f3fe1938baf5d1f2
- * (minus title and desc)
- * MD5 Checksum afc8344db5db4960ac3645d27d001fbc
- *
- * Compiled with: RDB Utility combo_header.pl
- * RDB Parser 3.0
- * unknown unknown
- * Perl Interpreter 5.008008
- * Operating System linux
- *
- * Revision History:
- *
- * $brcm_Log: $
- *
- ***************************************************************************/
-
-#ifndef BCHP_XPT_MEMDMA_MCPB_CH0_H__
-#define BCHP_XPT_MEMDMA_MCPB_CH0_H__
-
-/***************************************************************************
- *XPT_MEMDMA_MCPB_CH0 - MCPB Channel 0 Configuration
- ***************************************************************************/
-#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_DESC_CONTROL 0x00a60c00 /* MCPB Channel x Descriptor control information */
-#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_DATA_CONTROL 0x00a60c04 /* MCPB Channel x Data control information */
-#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_CURR_DESC_ADDRESS 0x00a60c08 /* MCPB Channel x Current Descriptor address information */
-#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_NEXT_DESC_ADDRESS 0x00a60c0c /* MCPB Channel x Next Descriptor address information */
-#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_BUFF_BASE_ADDRESS_UPPER 0x00a60c10 /* MCPB Channel x Data Buffer Base address */
-#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_BUFF_BASE_ADDRESS_LOWER 0x00a60c14 /* MCPB Channel x Data Buffer Base address */
-#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_BUFF_END_ADDRESS_UPPER 0x00a60c18 /* MCPB Channel x Data Buffer End address */
-#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_BUFF_END_ADDRESS_LOWER 0x00a60c1c /* MCPB Channel x Data Buffer End address */
-#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_BUFF_CURR_RD_ADDRESS_UPPER 0x00a60c20 /* MCPB Channel x Current Data Buffer Read address */
-#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_BUFF_CURR_RD_ADDRESS_LOWER 0x00a60c24 /* MCPB Channel x Current Data Buffer Read address */
-#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_BUFF_WRITE_ADDRESS_UPPER 0x00a60c28 /* MCPB Channel x Data Buffer Write address */
-#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_BUFF_WRITE_ADDRESS_LOWER 0x00a60c2c /* MCPB Channel x Data Buffer Write address */
-#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_STATUS_0 0x00a60c30 /* MCPB Channel x Status information */
-#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_STATUS_1 0x00a60c34 /* MCPB Channel x CRC value */
-#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_STATUS_2 0x00a60c38 /* MCPB Channel x Manual mode status */
-#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_DESC_SLOT0_STATUS_0 0x00a60c3c /* MCPB channel x Descriptor Slot 0 status information */
-#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_DESC_SLOT0_STATUS_1 0x00a60c40 /* MCPB channel x Descriptor Slot 0 status information */
-#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_DESC_SLOT0_CURR_DESC_ADDR 0x00a60c44 /* MCPB Channel x Descriptor Slot 0 Current Descriptor Address */
-#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_DESC_SLOT0_CURR_DATA_ADDR_UPPER 0x00a60c48 /* MCPB Channel x Descriptor Slot 0 Current Data Address */
-#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_DESC_SLOT0_CURR_DATA_ADDR_LOWER 0x00a60c4c /* MCPB Channel x Descriptor Slot 0 Current Data Address */
-#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_DESC_SLOT0_NEXT_TIMESTAMP 0x00a60c50 /* MCPB Channel x Descriptor Slot 0 Next Packet Timestamp */
-#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_DESC_SLOT0_PKT2PKT_TIMESTAMP_DELTA 0x00a60c54 /* MCPB Channel x Descriptor Slot 0 Packet to packet Timestamp delta */
-#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_DESC_SLOT1_STATUS_0 0x00a60c58 /* MCPB channel x Descriptor Slot 1 status information */
-#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_DESC_SLOT1_STATUS_1 0x00a60c5c /* MCPB channel x Descriptor Slot 1 status information */
-#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_DESC_SLOT1_CURR_DESC_ADDR 0x00a60c60 /* MCPB Channel x Descriptor Slot 1 Current Descriptor Address */
-#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_DESC_SLOT1_CURR_DATA_ADDR_UPPER 0x00a60c64 /* MCPB Channel x Descriptor Slot 1 Current Data Address */
-#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_DESC_SLOT1_CURR_DATA_ADDR_LOWER 0x00a60c68 /* MCPB Channel x Descriptor Slot 1 Current Data Address */
-#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_DESC_SLOT1_NEXT_TIMESTAMP 0x00a60c6c /* MCPB Channel x Descriptor Slot 1 Next Packet Timestamp */
-#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_DESC_SLOT1_PKT2PKT_TIMESTAMP_DELTA 0x00a60c70 /* MCPB Channel x Descriptor Slot 1 Packet to packet Timestamp delta */
-#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_PKT_LEN 0x00a60c74 /* MCPB Channel x Packet length control */
-#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_PARSER_CTRL 0x00a60c78 /* MCPB Channel x Parser control */
-#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_PARSER_CTRL1 0x00a60c7c /* MCPB Channel x Parser control 1 */
-#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_TS_CONFIG 0x00a60c80 /* MCPB Channel x TS Configuration */
-#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_PES_ES_CONFIG 0x00a60c84 /* MCPB Channel x PES and ES Configuration */
-#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_PES_SYNC_COUNTER 0x00a60c88 /* MCPB Channel x PES Sync counter */
-#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_ASF_CONFIG 0x00a60c8c /* MCPB Channel x ASF Configuration */
-#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_0 0x00a60c90 /* MCPB Channel x Stream Processor State Register 0 */
-#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_1 0x00a60c94 /* MCPB Channel x Stream Processor State Register 1 */
-#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_2 0x00a60c98 /* MCPB Channel x Stream Processor State Register 2 */
-#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_3 0x00a60c9c /* MCPB Channel x Stream Processor State Register 3 */
-#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_4 0x00a60ca0 /* MCPB Channel x Stream Processor State Register 4 */
-#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_5 0x00a60ca4 /* MCPB Channel x Stream Processor State Register 5 */
-#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_6 0x00a60ca8 /* MCPB Channel x Stream Processor State Register 6 */
-#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_7 0x00a60cac /* MCPB Channel x Stream Processor State Register 7 */
-#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_8 0x00a60cb0 /* MCPB Channel x Stream Processor State Register 8 */
-#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_9 0x00a60cb4 /* MCPB Channel x Stream Processor State Register 9 */
-#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_10 0x00a60cb8 /* MCPB Channel x Stream Processor State Register 10 */
-#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_11 0x00a60cbc /* MCPB Channel x Stream Processor State Register 11 */
-#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_12 0x00a60cc0 /* MCPB Channel x Stream Processor State Register 12 */
-#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_13 0x00a60cc4 /* MCPB Channel x Stream Processor State Register 13 */
-#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_BBUFF_CTRL 0x00a60cc8 /* MCPB Channel x Burst buffer control */
-#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_BBUFF_CRC 0x00a60ccc /* MCPB Channel x Current CRC value */
-#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_BBUFF0_RW_STATUS 0x00a60cd0 /* MCPB Channel x Burst buffer 0 data specific information */
-#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_BBUFF0_RO_STATUS 0x00a60cd4 /* MCPB Channel x Burst buffer 0 control specific information */
-#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_BBUFF1_RW_STATUS 0x00a60cd8 /* MCPB Channel x Burst buffer 1 data specific information */
-#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_BBUFF1_RO_STATUS 0x00a60cdc /* MCPB Channel x Burst buffer 1 control specific information */
-#define BCHP_XPT_MEMDMA_MCPB_CH0_TMEU_BLOCKOUT_CTRL 0x00a60ce0 /* MCPB Channel x Blockout control information */
-#define BCHP_XPT_MEMDMA_MCPB_CH0_TMEU_NEXT_BO_MON 0x00a60ce4 /* MCPB Channel x next Blockout monitor information */
-#define BCHP_XPT_MEMDMA_MCPB_CH0_TMEU_TIMING_CTRL 0x00a60ce8 /* MCPB Channel x next Blockout monitor information */
-#define BCHP_XPT_MEMDMA_MCPB_CH0_TMEU_REF_DIFF_VALUE_TS_MBOX 0x00a60cec /* MCPB Channel x reference difference value and next Timestamp information */
-#define BCHP_XPT_MEMDMA_MCPB_CH0_TMEU_TS_ERR_BOUND_EARLY 0x00a60cf0 /* MCPB Channel x TS error bound early information */
-#define BCHP_XPT_MEMDMA_MCPB_CH0_TMEU_TS_ERR_BOUND_LATE 0x00a60cf4 /* MCPB Channel x TS error bound late information */
-#define BCHP_XPT_MEMDMA_MCPB_CH0_TMEU_NEXT_GPC_MON 0x00a60cf8 /* MCPB Channel x next Global Pacing Counter and Timestamp monitor information */
-#define BCHP_XPT_MEMDMA_MCPB_CH0_TMEU_REF_DIFF_VALUE_SIGN 0x00a60cfc /* MCPB Channel x reference difference value sign information */
-#define BCHP_XPT_MEMDMA_MCPB_CH0_TMEU_PES_PACING_CTRL 0x00a60d00 /* MCPB Channel x PES pacing control information */
-#define BCHP_XPT_MEMDMA_MCPB_CH0_TMEU_SLOT_STATUS 0x00a60d04 /* MCPB Channel x Slot 0 and Slot 1 information */
-#define BCHP_XPT_MEMDMA_MCPB_CH0_TMEU_TIMING_INFO_SLOT0_REG1 0x00a60d08 /* MCPB Channel x timing information for Slot 0 */
-#define BCHP_XPT_MEMDMA_MCPB_CH0_TMEU_TIMING_INFO_SLOT0_REG2 0x00a60d0c /* MCPB Channel x timing information for Slot 0 */
-#define BCHP_XPT_MEMDMA_MCPB_CH0_TMEU_TIMING_INFO_SLOT1_REG1 0x00a60d10 /* MCPB Channel x timing information for Slot 1 */
-#define BCHP_XPT_MEMDMA_MCPB_CH0_TMEU_TIMING_INFO_SLOT1_REG2 0x00a60d14 /* MCPB Channel x timing information for Slot 1 */
-#define BCHP_XPT_MEMDMA_MCPB_CH0_TMEU_TIMING_INFO_LAST_TIMESTAMP_DELTA 0x00a60d18 /* MCPB Channel x last TS delta value */
-#define BCHP_XPT_MEMDMA_MCPB_CH0_TMEU_TIMING_INFO_LAST_NEXT_TIMESTAMP 0x00a60d1c /* MCPB Channel x last NEXT TS value */
-#define BCHP_XPT_MEMDMA_MCPB_CH0_DCPM_STATUS 0x00a60d20 /* MCPB Channel x DCPM status information */
-#define BCHP_XPT_MEMDMA_MCPB_CH0_DCPM_DESC_ADDR 0x00a60d24 /* MCPB Channel x DCPM descriptor address information */
-#define BCHP_XPT_MEMDMA_MCPB_CH0_DCPM_DESC_DONE_INT_ADDR 0x00a60d28 /* MCPB Channel x DCPM descriptor done interrupt address information */
-#define BCHP_XPT_MEMDMA_MCPB_CH0_DCPM_PAUSE_AFTER_GROUP_PACKETS_CTRL 0x00a60d2c /* MCPB Channel x Pause after group of packets control information */
-#define BCHP_XPT_MEMDMA_MCPB_CH0_DCPM_PAUSE_AFTER_GROUP_PACKETS_PKT_COUNTER 0x00a60d30 /* MCPB Channel x Pause after group of packets local packet counter */
-#define BCHP_XPT_MEMDMA_MCPB_CH0_DCPM_LOCAL_PACKET_COUNTER 0x00a60d34 /* MCPB Channel x local packet counter */
-#define BCHP_XPT_MEMDMA_MCPB_CH0_DCPM_DATA_ADDR_UPPER 0x00a60d38 /* MCPB Channel x DCPM data address information */
-#define BCHP_XPT_MEMDMA_MCPB_CH0_DCPM_DATA_ADDR_LOWER 0x00a60d3c /* MCPB Channel x DCPM data address information */
-#define BCHP_XPT_MEMDMA_MCPB_CH0_DCPM_CURR_DESC_ADDR 0x00a60d40 /* MCPB Channel x DCPM current descriptor address information */
-#define BCHP_XPT_MEMDMA_MCPB_CH0_DCPM_SLOT_STATUS 0x00a60d44 /* MCPB Channel x DCPM slot status information */
-#define BCHP_XPT_MEMDMA_MCPB_CH0_DCPM_DESC_ADDR_SLOT_0 0x00a60d48 /* MCPB Channel x DCPM completed slot 0 descriptor address information */
-#define BCHP_XPT_MEMDMA_MCPB_CH0_DCPM_DATA_ADDR_SLOT_0_UPPER 0x00a60d4c /* MCPB Channel x DCPM completed slot 0 data address information */
-#define BCHP_XPT_MEMDMA_MCPB_CH0_DCPM_DATA_ADDR_SLOT_0_LOWER 0x00a60d50 /* MCPB Channel x DCPM completed slot 0 data address information */
-#define BCHP_XPT_MEMDMA_MCPB_CH0_DCPM_DESC_ADDR_SLOT_1 0x00a60d54 /* MCPB Channel x DCPM completed slot 1 descriptor address information */
-#define BCHP_XPT_MEMDMA_MCPB_CH0_DCPM_DATA_ADDR_SLOT_1_UPPER 0x00a60d58 /* MCPB Channel x DCPM completed slot 1 data address information */
-#define BCHP_XPT_MEMDMA_MCPB_CH0_DCPM_DATA_ADDR_SLOT_1_LOWER 0x00a60d5c /* MCPB Channel x DCPM completed slot 1 data address information */
-
-/***************************************************************************
- *DMA_DESC_CONTROL - MCPB Channel x Descriptor control information
- ***************************************************************************/
-/* XPT_MEMDMA_MCPB_CH0 :: DMA_DESC_CONTROL :: FIRST_DESC_ADDRESS [31:04] */
-#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_DESC_CONTROL_FIRST_DESC_ADDRESS_MASK 0xfffffff0
-#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_DESC_CONTROL_FIRST_DESC_ADDRESS_SHIFT 4
-
-/* XPT_MEMDMA_MCPB_CH0 :: DMA_DESC_CONTROL :: reserved0 [03:02] */
-#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_DESC_CONTROL_reserved0_MASK 0x0000000c
-#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_DESC_CONTROL_reserved0_SHIFT 2
-
-/* XPT_MEMDMA_MCPB_CH0 :: DMA_DESC_CONTROL :: LLD_TYPE [01:00] */
-#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_DESC_CONTROL_LLD_TYPE_MASK 0x00000003
-#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_DESC_CONTROL_LLD_TYPE_SHIFT 0
-
-/***************************************************************************
- *DMA_DATA_CONTROL - MCPB Channel x Data control information
- ***************************************************************************/
-/* XPT_MEMDMA_MCPB_CH0 :: DMA_DATA_CONTROL :: reserved0 [31:16] */
-#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_DATA_CONTROL_reserved0_MASK 0xffff0000
-#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_DATA_CONTROL_reserved0_SHIFT 16
-
-/* XPT_MEMDMA_MCPB_CH0 :: DMA_DATA_CONTROL :: RUN_VERSION [15:11] */
-#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_DATA_CONTROL_RUN_VERSION_MASK 0x0000f800
-#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_DATA_CONTROL_RUN_VERSION_SHIFT 11
-
-/* XPT_MEMDMA_MCPB_CH0 :: DMA_DATA_CONTROL :: ENDIAN_CONTROL [10:10] */
-#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_DATA_CONTROL_ENDIAN_CONTROL_MASK 0x00000400
-#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_DATA_CONTROL_ENDIAN_CONTROL_SHIFT 10
-
-/* XPT_MEMDMA_MCPB_CH0 :: DMA_DATA_CONTROL :: DRAM_REQ_SIZE [09:00] */
-#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_DATA_CONTROL_DRAM_REQ_SIZE_MASK 0x000003ff
-#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_DATA_CONTROL_DRAM_REQ_SIZE_SHIFT 0
-
-/***************************************************************************
- *DMA_CURR_DESC_ADDRESS - MCPB Channel x Current Descriptor address information
- ***************************************************************************/
-/* XPT_MEMDMA_MCPB_CH0 :: DMA_CURR_DESC_ADDRESS :: CURR_DESC_ADDRESS [31:04] */
-#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_CURR_DESC_ADDRESS_CURR_DESC_ADDRESS_MASK 0xfffffff0
-#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_CURR_DESC_ADDRESS_CURR_DESC_ADDRESS_SHIFT 4
-
-/* XPT_MEMDMA_MCPB_CH0 :: DMA_CURR_DESC_ADDRESS :: reserved0 [03:00] */
-#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_CURR_DESC_ADDRESS_reserved0_MASK 0x0000000f
-#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_CURR_DESC_ADDRESS_reserved0_SHIFT 0
-
-/***************************************************************************
- *DMA_NEXT_DESC_ADDRESS - MCPB Channel x Next Descriptor address information
- ***************************************************************************/
-/* XPT_MEMDMA_MCPB_CH0 :: DMA_NEXT_DESC_ADDRESS :: NEXT_DESC_ADDRESS [31:04] */
-#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_NEXT_DESC_ADDRESS_NEXT_DESC_ADDRESS_MASK 0xfffffff0
-#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_NEXT_DESC_ADDRESS_NEXT_DESC_ADDRESS_SHIFT 4
-
-/* XPT_MEMDMA_MCPB_CH0 :: DMA_NEXT_DESC_ADDRESS :: reserved0 [03:00] */
-#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_NEXT_DESC_ADDRESS_reserved0_MASK 0x0000000f
-#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_NEXT_DESC_ADDRESS_reserved0_SHIFT 0
-
-/***************************************************************************
- *DMA_BUFF_BASE_ADDRESS_UPPER - MCPB Channel x Data Buffer Base address
- ***************************************************************************/
-/* XPT_MEMDMA_MCPB_CH0 :: DMA_BUFF_BASE_ADDRESS_UPPER :: reserved0 [31:08] */
-#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_BUFF_BASE_ADDRESS_UPPER_reserved0_MASK 0xffffff00
-#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_BUFF_BASE_ADDRESS_UPPER_reserved0_SHIFT 8
-
-/* XPT_MEMDMA_MCPB_CH0 :: DMA_BUFF_BASE_ADDRESS_UPPER :: BUFF_BASE_ADDRESS [07:00] */
-#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_BUFF_BASE_ADDRESS_UPPER_BUFF_BASE_ADDRESS_MASK 0x000000ff
-#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_BUFF_BASE_ADDRESS_UPPER_BUFF_BASE_ADDRESS_SHIFT 0
-
-/***************************************************************************
- *DMA_BUFF_BASE_ADDRESS_LOWER - MCPB Channel x Data Buffer Base address
- ***************************************************************************/
-/* XPT_MEMDMA_MCPB_CH0 :: DMA_BUFF_BASE_ADDRESS_LOWER :: BUFF_BASE_ADDRESS [31:00] */
-#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_BUFF_BASE_ADDRESS_LOWER_BUFF_BASE_ADDRESS_MASK 0xffffffff
-#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_BUFF_BASE_ADDRESS_LOWER_BUFF_BASE_ADDRESS_SHIFT 0
-
-/***************************************************************************
- *DMA_BUFF_END_ADDRESS_UPPER - MCPB Channel x Data Buffer End address
- ***************************************************************************/
-/* XPT_MEMDMA_MCPB_CH0 :: DMA_BUFF_END_ADDRESS_UPPER :: reserved0 [31:08] */
-#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_BUFF_END_ADDRESS_UPPER_reserved0_MASK 0xffffff00
-#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_BUFF_END_ADDRESS_UPPER_reserved0_SHIFT 8
-
-/* XPT_MEMDMA_MCPB_CH0 :: DMA_BUFF_END_ADDRESS_UPPER :: BUFF_END_ADDRESS [07:00] */
-#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_BUFF_END_ADDRESS_UPPER_BUFF_END_ADDRESS_MASK 0x000000ff
-#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_BUFF_END_ADDRESS_UPPER_BUFF_END_ADDRESS_SHIFT 0
-
-/***************************************************************************
- *DMA_BUFF_END_ADDRESS_LOWER - MCPB Channel x Data Buffer End address
- ***************************************************************************/
-/* XPT_MEMDMA_MCPB_CH0 :: DMA_BUFF_END_ADDRESS_LOWER :: BUFF_END_ADDRESS [31:00] */
-#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_BUFF_END_ADDRESS_LOWER_BUFF_END_ADDRESS_MASK 0xffffffff
-#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_BUFF_END_ADDRESS_LOWER_BUFF_END_ADDRESS_SHIFT 0
-
-/***************************************************************************
- *DMA_BUFF_CURR_RD_ADDRESS_UPPER - MCPB Channel x Current Data Buffer Read address
- ***************************************************************************/
-/* XPT_MEMDMA_MCPB_CH0 :: DMA_BUFF_CURR_RD_ADDRESS_UPPER :: reserved0 [31:08] */
-#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_BUFF_CURR_RD_ADDRESS_UPPER_reserved0_MASK 0xffffff00
-#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_BUFF_CURR_RD_ADDRESS_UPPER_reserved0_SHIFT 8
-
-/* XPT_MEMDMA_MCPB_CH0 :: DMA_BUFF_CURR_RD_ADDRESS_UPPER :: BUFF_CURR_RD_ADDRESS [07:00] */
-#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_BUFF_CURR_RD_ADDRESS_UPPER_BUFF_CURR_RD_ADDRESS_MASK 0x000000ff
-#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_BUFF_CURR_RD_ADDRESS_UPPER_BUFF_CURR_RD_ADDRESS_SHIFT 0
-
-/***************************************************************************
- *DMA_BUFF_CURR_RD_ADDRESS_LOWER - MCPB Channel x Current Data Buffer Read address
- ***************************************************************************/
-/* XPT_MEMDMA_MCPB_CH0 :: DMA_BUFF_CURR_RD_ADDRESS_LOWER :: BUFF_CURR_RD_ADDRESS [31:00] */
-#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_BUFF_CURR_RD_ADDRESS_LOWER_BUFF_CURR_RD_ADDRESS_MASK 0xffffffff
-#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_BUFF_CURR_RD_ADDRESS_LOWER_BUFF_CURR_RD_ADDRESS_SHIFT 0
-
-/***************************************************************************
- *DMA_BUFF_WRITE_ADDRESS_UPPER - MCPB Channel x Data Buffer Write address
- ***************************************************************************/
-/* XPT_MEMDMA_MCPB_CH0 :: DMA_BUFF_WRITE_ADDRESS_UPPER :: reserved0 [31:08] */
-#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_BUFF_WRITE_ADDRESS_UPPER_reserved0_MASK 0xffffff00
-#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_BUFF_WRITE_ADDRESS_UPPER_reserved0_SHIFT 8
-
-/* XPT_MEMDMA_MCPB_CH0 :: DMA_BUFF_WRITE_ADDRESS_UPPER :: BUFF_WRITE_ADDRESS [07:00] */
-#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_BUFF_WRITE_ADDRESS_UPPER_BUFF_WRITE_ADDRESS_MASK 0x000000ff
-#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_BUFF_WRITE_ADDRESS_UPPER_BUFF_WRITE_ADDRESS_SHIFT 0
-
-/***************************************************************************
- *DMA_BUFF_WRITE_ADDRESS_LOWER - MCPB Channel x Data Buffer Write address
- ***************************************************************************/
-/* XPT_MEMDMA_MCPB_CH0 :: DMA_BUFF_WRITE_ADDRESS_LOWER :: BUFF_WRITE_ADDRESS [31:00] */
-#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_BUFF_WRITE_ADDRESS_LOWER_BUFF_WRITE_ADDRESS_MASK 0xffffffff
-#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_BUFF_WRITE_ADDRESS_LOWER_BUFF_WRITE_ADDRESS_SHIFT 0
-
-/***************************************************************************
- *DMA_STATUS_0 - MCPB Channel x Status information
- ***************************************************************************/
-/* XPT_MEMDMA_MCPB_CH0 :: DMA_STATUS_0 :: reserved0 [31:31] */
-#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_STATUS_0_reserved0_MASK 0x80000000
-#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_STATUS_0_reserved0_SHIFT 31
-
-/* XPT_MEMDMA_MCPB_CH0 :: DMA_STATUS_0 :: DESC_SLOT_NUM_TO_USE [30:30] */
-#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_STATUS_0_DESC_SLOT_NUM_TO_USE_MASK 0x40000000
-#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_STATUS_0_DESC_SLOT_NUM_TO_USE_SHIFT 30
-
-/* XPT_MEMDMA_MCPB_CH0 :: DMA_STATUS_0 :: SEND_0B_BAND_ID_CHANGE_TRANS [29:29] */
-#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_STATUS_0_SEND_0B_BAND_ID_CHANGE_TRANS_MASK 0x20000000
-#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_STATUS_0_SEND_0B_BAND_ID_CHANGE_TRANS_SHIFT 29
-
-/* XPT_MEMDMA_MCPB_CH0 :: DMA_STATUS_0 :: SEND_0B_CONTROL_TRANS [28:28] */
-#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_STATUS_0_SEND_0B_CONTROL_TRANS_MASK 0x10000000
-#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_STATUS_0_SEND_0B_CONTROL_TRANS_SHIFT 28
-
-/* XPT_MEMDMA_MCPB_CH0 :: DMA_STATUS_0 :: SEND_RESET_PARSER_ON_1ST_NON_0_TRAN [27:27] */
-#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_STATUS_0_SEND_RESET_PARSER_ON_1ST_NON_0_TRAN_MASK 0x08000000
-#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_STATUS_0_SEND_RESET_PARSER_ON_1ST_NON_0_TRAN_SHIFT 27
-
-/* XPT_MEMDMA_MCPB_CH0 :: DMA_STATUS_0 :: FIRST_DESC_RD_AFTER_RUN_ASSERT [26:26] */
-#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_STATUS_0_FIRST_DESC_RD_AFTER_RUN_ASSERT_MASK 0x04000000
-#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_STATUS_0_FIRST_DESC_RD_AFTER_RUN_ASSERT_SHIFT 26
-
-/* XPT_MEMDMA_MCPB_CH0 :: DMA_STATUS_0 :: ZERO_BYTE_DESC [25:25] */
-#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_STATUS_0_ZERO_BYTE_DESC_MASK 0x02000000
-#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_STATUS_0_ZERO_BYTE_DESC_SHIFT 25
-
-/* XPT_MEMDMA_MCPB_CH0 :: DMA_STATUS_0 :: LAST_DESC_IND [24:24] */
-#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_STATUS_0_LAST_DESC_IND_MASK 0x01000000
-#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_STATUS_0_LAST_DESC_IND_SHIFT 24
-
-/* XPT_MEMDMA_MCPB_CH0 :: DMA_STATUS_0 :: HOST_DATA_INS_EN [23:23] */
-#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_STATUS_0_HOST_DATA_INS_EN_MASK 0x00800000
-#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_STATUS_0_HOST_DATA_INS_EN_SHIFT 23
-
-/* XPT_MEMDMA_MCPB_CH0 :: DMA_STATUS_0 :: FORCE_RESYNC [22:22] */
-#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_STATUS_0_FORCE_RESYNC_MASK 0x00400000
-#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_STATUS_0_FORCE_RESYNC_SHIFT 22
-
-/* XPT_MEMDMA_MCPB_CH0 :: DMA_STATUS_0 :: PUSH_PREV_PARTIAL_PACKET [21:21] */
-#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_STATUS_0_PUSH_PREV_PARTIAL_PACKET_MASK 0x00200000
-#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_STATUS_0_PUSH_PREV_PARTIAL_PACKET_SHIFT 21
-
-/* XPT_MEMDMA_MCPB_CH0 :: DMA_STATUS_0 :: PUSH_PARTIAL_PACKET [20:20] */
-#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_STATUS_0_PUSH_PARTIAL_PACKET_MASK 0x00100000
-#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_STATUS_0_PUSH_PARTIAL_PACKET_SHIFT 20
-
-/* XPT_MEMDMA_MCPB_CH0 :: DMA_STATUS_0 :: DESC_BAND_ID [19:12] */
-#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_STATUS_0_DESC_BAND_ID_MASK 0x000ff000
-#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_STATUS_0_DESC_BAND_ID_SHIFT 12
-
-/* XPT_MEMDMA_MCPB_CH0 :: DMA_STATUS_0 :: DESC_BAND_ID_EN [11:11] */
-#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_STATUS_0_DESC_BAND_ID_EN_MASK 0x00000800
-#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_STATUS_0_DESC_BAND_ID_EN_SHIFT 11
-
-/* XPT_MEMDMA_MCPB_CH0 :: DMA_STATUS_0 :: DESC_PARSER_SEL [10:10] */
-#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_STATUS_0_DESC_PARSER_SEL_MASK 0x00000400
-#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_STATUS_0_DESC_PARSER_SEL_SHIFT 10
-
-/* XPT_MEMDMA_MCPB_CH0 :: DMA_STATUS_0 :: RD_ENDIAN_STRAP_INV_CTRL [09:09] */
-#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_STATUS_0_RD_ENDIAN_STRAP_INV_CTRL_MASK 0x00000200
-#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_STATUS_0_RD_ENDIAN_STRAP_INV_CTRL_SHIFT 9
-
-/* XPT_MEMDMA_MCPB_CH0 :: DMA_STATUS_0 :: CRC_LOAD [08:08] */
-#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_STATUS_0_CRC_LOAD_MASK 0x00000100
-#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_STATUS_0_CRC_LOAD_SHIFT 8
-
-/* XPT_MEMDMA_MCPB_CH0 :: DMA_STATUS_0 :: CRC_COMPARE [07:07] */
-#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_STATUS_0_CRC_COMPARE_MASK 0x00000080
-#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_STATUS_0_CRC_COMPARE_SHIFT 7
-
-/* XPT_MEMDMA_MCPB_CH0 :: DMA_STATUS_0 :: CRC_COMPUTE [06:06] */
-#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_STATUS_0_CRC_COMPUTE_MASK 0x00000040
-#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_STATUS_0_CRC_COMPUTE_SHIFT 6
-
-/* XPT_MEMDMA_MCPB_CH0 :: DMA_STATUS_0 :: SCRAM_START [05:05] */
-#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_STATUS_0_SCRAM_START_MASK 0x00000020
-#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_STATUS_0_SCRAM_START_SHIFT 5
-
-/* XPT_MEMDMA_MCPB_CH0 :: DMA_STATUS_0 :: SCRAM_END [04:04] */
-#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_STATUS_0_SCRAM_END_MASK 0x00000010
-#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_STATUS_0_SCRAM_END_SHIFT 4
-
-/* XPT_MEMDMA_MCPB_CH0 :: DMA_STATUS_0 :: NEXT_TIMESTAMP_VALID [03:03] */
-#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_STATUS_0_NEXT_TIMESTAMP_VALID_MASK 0x00000008
-#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_STATUS_0_NEXT_TIMESTAMP_VALID_SHIFT 3
-
-/* XPT_MEMDMA_MCPB_CH0 :: DMA_STATUS_0 :: PKT2PKT_TIMESTAMP_DELTA_VALID [02:02] */
-#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_STATUS_0_PKT2PKT_TIMESTAMP_DELTA_VALID_MASK 0x00000004
-#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_STATUS_0_PKT2PKT_TIMESTAMP_DELTA_VALID_SHIFT 2
-
-/* XPT_MEMDMA_MCPB_CH0 :: DMA_STATUS_0 :: PAUSE_AT_DESC_READ [01:01] */
-#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_STATUS_0_PAUSE_AT_DESC_READ_MASK 0x00000002
-#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_STATUS_0_PAUSE_AT_DESC_READ_SHIFT 1
-
-/* XPT_MEMDMA_MCPB_CH0 :: DMA_STATUS_0 :: PAUSE_AT_DESC_END [00:00] */
-#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_STATUS_0_PAUSE_AT_DESC_END_MASK 0x00000001
-#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_STATUS_0_PAUSE_AT_DESC_END_SHIFT 0
-
-/***************************************************************************
- *DMA_STATUS_1 - MCPB Channel x CRC value
- ***************************************************************************/
-/* XPT_MEMDMA_MCPB_CH0 :: DMA_STATUS_1 :: CRC_IN [31:00] */
-#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_STATUS_1_CRC_IN_MASK 0xffffffff
-#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_STATUS_1_CRC_IN_SHIFT 0
-
-/***************************************************************************
- *DMA_STATUS_2 - MCPB Channel x Manual mode status
- ***************************************************************************/
-/* XPT_MEMDMA_MCPB_CH0 :: DMA_STATUS_2 :: reserved0 [31:03] */
-#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_STATUS_2_reserved0_MASK 0xfffffff8
-#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_STATUS_2_reserved0_SHIFT 3
-
-/* XPT_MEMDMA_MCPB_CH0 :: DMA_STATUS_2 :: SP_COMMAND_FROM_DESC_TYPE [02:01] */
-#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_STATUS_2_SP_COMMAND_FROM_DESC_TYPE_MASK 0x00000006
-#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_STATUS_2_SP_COMMAND_FROM_DESC_TYPE_SHIFT 1
-
-/* XPT_MEMDMA_MCPB_CH0 :: DMA_STATUS_2 :: SP_COMMAND_FROM_DESC_EN [00:00] */
-#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_STATUS_2_SP_COMMAND_FROM_DESC_EN_MASK 0x00000001
-#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_STATUS_2_SP_COMMAND_FROM_DESC_EN_SHIFT 0
-
-/***************************************************************************
- *DMA_DESC_SLOT0_STATUS_0 - MCPB channel x Descriptor Slot 0 status information
- ***************************************************************************/
-/* XPT_MEMDMA_MCPB_CH0 :: DMA_DESC_SLOT0_STATUS_0 :: reserved0 [31:19] */
-#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_DESC_SLOT0_STATUS_0_reserved0_MASK 0xfff80000
-#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_DESC_SLOT0_STATUS_0_reserved0_SHIFT 19
-
-/* XPT_MEMDMA_MCPB_CH0 :: DMA_DESC_SLOT0_STATUS_0 :: INTR_EN [18:18] */
-#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_DESC_SLOT0_STATUS_0_INTR_EN_MASK 0x00040000
-#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_DESC_SLOT0_STATUS_0_INTR_EN_SHIFT 18
-
-/* XPT_MEMDMA_MCPB_CH0 :: DMA_DESC_SLOT0_STATUS_0 :: PAUSE_AT_DESCRIPTOR_READ [17:17] */
-#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_DESC_SLOT0_STATUS_0_PAUSE_AT_DESCRIPTOR_READ_MASK 0x00020000
-#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_DESC_SLOT0_STATUS_0_PAUSE_AT_DESCRIPTOR_READ_SHIFT 17
-
-/* XPT_MEMDMA_MCPB_CH0 :: DMA_DESC_SLOT0_STATUS_0 :: PAUSE_AT_DESCRIPTOR_END [16:16] */
-#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_DESC_SLOT0_STATUS_0_PAUSE_AT_DESCRIPTOR_END_MASK 0x00010000
-#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_DESC_SLOT0_STATUS_0_PAUSE_AT_DESCRIPTOR_END_SHIFT 16
-
-/* XPT_MEMDMA_MCPB_CH0 :: DMA_DESC_SLOT0_STATUS_0 :: DESC_ID [15:12] */
-#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_DESC_SLOT0_STATUS_0_DESC_ID_MASK 0x0000f000
-#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_DESC_SLOT0_STATUS_0_DESC_ID_SHIFT 12
-
-/* XPT_MEMDMA_MCPB_CH0 :: DMA_DESC_SLOT0_STATUS_0 :: RANDOM_ACCESS_IND [11:11] */
-#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_DESC_SLOT0_STATUS_0_RANDOM_ACCESS_IND_MASK 0x00000800
-#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_DESC_SLOT0_STATUS_0_RANDOM_ACCESS_IND_SHIFT 11
-
-/* XPT_MEMDMA_MCPB_CH0 :: DMA_DESC_SLOT0_STATUS_0 :: RUN_VERSION [10:06] */
-#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_DESC_SLOT0_STATUS_0_RUN_VERSION_MASK 0x000007c0
-#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_DESC_SLOT0_STATUS_0_RUN_VERSION_SHIFT 6
-
-/* XPT_MEMDMA_MCPB_CH0 :: DMA_DESC_SLOT0_STATUS_0 :: HOST_DATA_INS_AS_BTP_PKT [05:05] */
-#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_DESC_SLOT0_STATUS_0_HOST_DATA_INS_AS_BTP_PKT_MASK 0x00000020
-#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_DESC_SLOT0_STATUS_0_HOST_DATA_INS_AS_BTP_PKT_SHIFT 5
-
-/* XPT_MEMDMA_MCPB_CH0 :: DMA_DESC_SLOT0_STATUS_0 :: SCRAM_START [04:04] */
-#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_DESC_SLOT0_STATUS_0_SCRAM_START_MASK 0x00000010
-#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_DESC_SLOT0_STATUS_0_SCRAM_START_SHIFT 4
-
-/* XPT_MEMDMA_MCPB_CH0 :: DMA_DESC_SLOT0_STATUS_0 :: SCRAM_END [03:03] */
-#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_DESC_SLOT0_STATUS_0_SCRAM_END_MASK 0x00000008
-#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_DESC_SLOT0_STATUS_0_SCRAM_END_SHIFT 3
-
-/* XPT_MEMDMA_MCPB_CH0 :: DMA_DESC_SLOT0_STATUS_0 :: SCRAM_INIT [02:02] */
-#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_DESC_SLOT0_STATUS_0_SCRAM_INIT_MASK 0x00000004
-#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_DESC_SLOT0_STATUS_0_SCRAM_INIT_SHIFT 2
-
-/* XPT_MEMDMA_MCPB_CH0 :: DMA_DESC_SLOT0_STATUS_0 :: NEXT_TIMESTAMP_VALID [01:01] */
-#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_DESC_SLOT0_STATUS_0_NEXT_TIMESTAMP_VALID_MASK 0x00000002
-#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_DESC_SLOT0_STATUS_0_NEXT_TIMESTAMP_VALID_SHIFT 1
-
-/* XPT_MEMDMA_MCPB_CH0 :: DMA_DESC_SLOT0_STATUS_0 :: PKT2PKT_TIMESTAMP_DELTA_VALID [00:00] */
-#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_DESC_SLOT0_STATUS_0_PKT2PKT_TIMESTAMP_DELTA_VALID_MASK 0x00000001
-#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_DESC_SLOT0_STATUS_0_PKT2PKT_TIMESTAMP_DELTA_VALID_SHIFT 0
-
-/***************************************************************************
- *DMA_DESC_SLOT0_STATUS_1 - MCPB channel x Descriptor Slot 0 status information
- ***************************************************************************/
-/* XPT_MEMDMA_MCPB_CH0 :: DMA_DESC_SLOT0_STATUS_1 :: reserved0 [31:21] */
-#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_DESC_SLOT0_STATUS_1_reserved0_MASK 0xffe00000
-#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_DESC_SLOT0_STATUS_1_reserved0_SHIFT 21
-
-/* XPT_MEMDMA_MCPB_CH0 :: DMA_DESC_SLOT0_STATUS_1 :: DESC_BAND_ID_EN [20:20] */
-#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_DESC_SLOT0_STATUS_1_DESC_BAND_ID_EN_MASK 0x00100000
-#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_DESC_SLOT0_STATUS_1_DESC_BAND_ID_EN_SHIFT 20
-
-/* XPT_MEMDMA_MCPB_CH0 :: DMA_DESC_SLOT0_STATUS_1 :: DESC_PARSER_SEL [19:19] */
-#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_DESC_SLOT0_STATUS_1_DESC_PARSER_SEL_MASK 0x00080000
-#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_DESC_SLOT0_STATUS_1_DESC_PARSER_SEL_SHIFT 19
-
-/* XPT_MEMDMA_MCPB_CH0 :: DMA_DESC_SLOT0_STATUS_1 :: DESC_BAND_ID [18:11] */
-#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_DESC_SLOT0_STATUS_1_DESC_BAND_ID_MASK 0x0007f800
-#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_DESC_SLOT0_STATUS_1_DESC_BAND_ID_SHIFT 11
-
-/* XPT_MEMDMA_MCPB_CH0 :: DMA_DESC_SLOT0_STATUS_1 :: PID_CHANNEL_VALID [10:10] */
-#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_DESC_SLOT0_STATUS_1_PID_CHANNEL_VALID_MASK 0x00000400
-#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_DESC_SLOT0_STATUS_1_PID_CHANNEL_VALID_SHIFT 10
-
-/* XPT_MEMDMA_MCPB_CH0 :: DMA_DESC_SLOT0_STATUS_1 :: PID_CHANNEL [09:00] */
-#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_DESC_SLOT0_STATUS_1_PID_CHANNEL_MASK 0x000003ff
-#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_DESC_SLOT0_STATUS_1_PID_CHANNEL_SHIFT 0
-
-/***************************************************************************
- *DMA_DESC_SLOT0_CURR_DESC_ADDR - MCPB Channel x Descriptor Slot 0 Current Descriptor Address
- ***************************************************************************/
-/* XPT_MEMDMA_MCPB_CH0 :: DMA_DESC_SLOT0_CURR_DESC_ADDR :: CUR_DESC_ADDR [31:00] */
-#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_DESC_SLOT0_CURR_DESC_ADDR_CUR_DESC_ADDR_MASK 0xffffffff
-#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_DESC_SLOT0_CURR_DESC_ADDR_CUR_DESC_ADDR_SHIFT 0
-
-/***************************************************************************
- *DMA_DESC_SLOT0_CURR_DATA_ADDR_UPPER - MCPB Channel x Descriptor Slot 0 Current Data Address
- ***************************************************************************/
-/* XPT_MEMDMA_MCPB_CH0 :: DMA_DESC_SLOT0_CURR_DATA_ADDR_UPPER :: reserved0 [31:08] */
-#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_DESC_SLOT0_CURR_DATA_ADDR_UPPER_reserved0_MASK 0xffffff00
-#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_DESC_SLOT0_CURR_DATA_ADDR_UPPER_reserved0_SHIFT 8
-
-/* XPT_MEMDMA_MCPB_CH0 :: DMA_DESC_SLOT0_CURR_DATA_ADDR_UPPER :: CUR_DATA_ADDR [07:00] */
-#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_DESC_SLOT0_CURR_DATA_ADDR_UPPER_CUR_DATA_ADDR_MASK 0x000000ff
-#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_DESC_SLOT0_CURR_DATA_ADDR_UPPER_CUR_DATA_ADDR_SHIFT 0
-
-/***************************************************************************
- *DMA_DESC_SLOT0_CURR_DATA_ADDR_LOWER - MCPB Channel x Descriptor Slot 0 Current Data Address
- ***************************************************************************/
-/* XPT_MEMDMA_MCPB_CH0 :: DMA_DESC_SLOT0_CURR_DATA_ADDR_LOWER :: CUR_DATA_ADDR [31:00] */
-#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_DESC_SLOT0_CURR_DATA_ADDR_LOWER_CUR_DATA_ADDR_MASK 0xffffffff
-#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_DESC_SLOT0_CURR_DATA_ADDR_LOWER_CUR_DATA_ADDR_SHIFT 0
-
-/***************************************************************************
- *DMA_DESC_SLOT0_NEXT_TIMESTAMP - MCPB Channel x Descriptor Slot 0 Next Packet Timestamp
- ***************************************************************************/
-/* XPT_MEMDMA_MCPB_CH0 :: DMA_DESC_SLOT0_NEXT_TIMESTAMP :: NEXT_TIMESTAMP [31:00] */
-#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_DESC_SLOT0_NEXT_TIMESTAMP_NEXT_TIMESTAMP_MASK 0xffffffff
-#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_DESC_SLOT0_NEXT_TIMESTAMP_NEXT_TIMESTAMP_SHIFT 0
-
-/***************************************************************************
- *DMA_DESC_SLOT0_PKT2PKT_TIMESTAMP_DELTA - MCPB Channel x Descriptor Slot 0 Packet to packet Timestamp delta
- ***************************************************************************/
-/* XPT_MEMDMA_MCPB_CH0 :: DMA_DESC_SLOT0_PKT2PKT_TIMESTAMP_DELTA :: PKT2PKT_TIMESTAMP_DELTA [31:00] */
-#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_DESC_SLOT0_PKT2PKT_TIMESTAMP_DELTA_PKT2PKT_TIMESTAMP_DELTA_MASK 0xffffffff
-#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_DESC_SLOT0_PKT2PKT_TIMESTAMP_DELTA_PKT2PKT_TIMESTAMP_DELTA_SHIFT 0
-
-/***************************************************************************
- *DMA_DESC_SLOT1_STATUS_0 - MCPB channel x Descriptor Slot 1 status information
- ***************************************************************************/
-/* XPT_MEMDMA_MCPB_CH0 :: DMA_DESC_SLOT1_STATUS_0 :: reserved0 [31:19] */
-#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_DESC_SLOT1_STATUS_0_reserved0_MASK 0xfff80000
-#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_DESC_SLOT1_STATUS_0_reserved0_SHIFT 19
-
-/* XPT_MEMDMA_MCPB_CH0 :: DMA_DESC_SLOT1_STATUS_0 :: INTR_EN [18:18] */
-#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_DESC_SLOT1_STATUS_0_INTR_EN_MASK 0x00040000
-#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_DESC_SLOT1_STATUS_0_INTR_EN_SHIFT 18
-
-/* XPT_MEMDMA_MCPB_CH0 :: DMA_DESC_SLOT1_STATUS_0 :: PAUSE_AT_DESCRIPTOR_READ [17:17] */
-#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_DESC_SLOT1_STATUS_0_PAUSE_AT_DESCRIPTOR_READ_MASK 0x00020000
-#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_DESC_SLOT1_STATUS_0_PAUSE_AT_DESCRIPTOR_READ_SHIFT 17
-
-/* XPT_MEMDMA_MCPB_CH0 :: DMA_DESC_SLOT1_STATUS_0 :: PAUSE_AT_DESCRIPTOR_END [16:16] */
-#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_DESC_SLOT1_STATUS_0_PAUSE_AT_DESCRIPTOR_END_MASK 0x00010000
-#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_DESC_SLOT1_STATUS_0_PAUSE_AT_DESCRIPTOR_END_SHIFT 16
-
-/* XPT_MEMDMA_MCPB_CH0 :: DMA_DESC_SLOT1_STATUS_0 :: DESC_ID [15:12] */
-#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_DESC_SLOT1_STATUS_0_DESC_ID_MASK 0x0000f000
-#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_DESC_SLOT1_STATUS_0_DESC_ID_SHIFT 12
-
-/* XPT_MEMDMA_MCPB_CH0 :: DMA_DESC_SLOT1_STATUS_0 :: RANDOM_ACCESS_IND [11:11] */
-#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_DESC_SLOT1_STATUS_0_RANDOM_ACCESS_IND_MASK 0x00000800
-#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_DESC_SLOT1_STATUS_0_RANDOM_ACCESS_IND_SHIFT 11
-
-/* XPT_MEMDMA_MCPB_CH0 :: DMA_DESC_SLOT1_STATUS_0 :: RUN_VERSION [10:06] */
-#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_DESC_SLOT1_STATUS_0_RUN_VERSION_MASK 0x000007c0
-#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_DESC_SLOT1_STATUS_0_RUN_VERSION_SHIFT 6
-
-/* XPT_MEMDMA_MCPB_CH0 :: DMA_DESC_SLOT1_STATUS_0 :: HOST_DATA_INS_AS_BTP_PKT [05:05] */
-#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_DESC_SLOT1_STATUS_0_HOST_DATA_INS_AS_BTP_PKT_MASK 0x00000020
-#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_DESC_SLOT1_STATUS_0_HOST_DATA_INS_AS_BTP_PKT_SHIFT 5
-
-/* XPT_MEMDMA_MCPB_CH0 :: DMA_DESC_SLOT1_STATUS_0 :: SCRAM_START [04:04] */
-#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_DESC_SLOT1_STATUS_0_SCRAM_START_MASK 0x00000010
-#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_DESC_SLOT1_STATUS_0_SCRAM_START_SHIFT 4
-
-/* XPT_MEMDMA_MCPB_CH0 :: DMA_DESC_SLOT1_STATUS_0 :: SCRAM_END [03:03] */
-#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_DESC_SLOT1_STATUS_0_SCRAM_END_MASK 0x00000008
-#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_DESC_SLOT1_STATUS_0_SCRAM_END_SHIFT 3
-
-/* XPT_MEMDMA_MCPB_CH0 :: DMA_DESC_SLOT1_STATUS_0 :: SCRAM_INIT [02:02] */
-#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_DESC_SLOT1_STATUS_0_SCRAM_INIT_MASK 0x00000004
-#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_DESC_SLOT1_STATUS_0_SCRAM_INIT_SHIFT 2
-
-/* XPT_MEMDMA_MCPB_CH0 :: DMA_DESC_SLOT1_STATUS_0 :: NEXT_TIMESTAMP_VALID [01:01] */
-#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_DESC_SLOT1_STATUS_0_NEXT_TIMESTAMP_VALID_MASK 0x00000002
-#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_DESC_SLOT1_STATUS_0_NEXT_TIMESTAMP_VALID_SHIFT 1
-
-/* XPT_MEMDMA_MCPB_CH0 :: DMA_DESC_SLOT1_STATUS_0 :: PKT2PKT_TIMESTAMP_DELTA_VALID [00:00] */
-#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_DESC_SLOT1_STATUS_0_PKT2PKT_TIMESTAMP_DELTA_VALID_MASK 0x00000001
-#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_DESC_SLOT1_STATUS_0_PKT2PKT_TIMESTAMP_DELTA_VALID_SHIFT 0
-
-/***************************************************************************
- *DMA_DESC_SLOT1_STATUS_1 - MCPB channel x Descriptor Slot 1 status information
- ***************************************************************************/
-/* XPT_MEMDMA_MCPB_CH0 :: DMA_DESC_SLOT1_STATUS_1 :: reserved0 [31:21] */
-#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_DESC_SLOT1_STATUS_1_reserved0_MASK 0xffe00000
-#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_DESC_SLOT1_STATUS_1_reserved0_SHIFT 21
-
-/* XPT_MEMDMA_MCPB_CH0 :: DMA_DESC_SLOT1_STATUS_1 :: DESC_BAND_ID_EN [20:20] */
-#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_DESC_SLOT1_STATUS_1_DESC_BAND_ID_EN_MASK 0x00100000
-#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_DESC_SLOT1_STATUS_1_DESC_BAND_ID_EN_SHIFT 20
-
-/* XPT_MEMDMA_MCPB_CH0 :: DMA_DESC_SLOT1_STATUS_1 :: DESC_PARSER_SEL [19:19] */
-#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_DESC_SLOT1_STATUS_1_DESC_PARSER_SEL_MASK 0x00080000
-#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_DESC_SLOT1_STATUS_1_DESC_PARSER_SEL_SHIFT 19
-
-/* XPT_MEMDMA_MCPB_CH0 :: DMA_DESC_SLOT1_STATUS_1 :: DESC_BAND_ID [18:11] */
-#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_DESC_SLOT1_STATUS_1_DESC_BAND_ID_MASK 0x0007f800
-#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_DESC_SLOT1_STATUS_1_DESC_BAND_ID_SHIFT 11
-
-/* XPT_MEMDMA_MCPB_CH0 :: DMA_DESC_SLOT1_STATUS_1 :: PID_CHANNEL_VALID [10:10] */
-#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_DESC_SLOT1_STATUS_1_PID_CHANNEL_VALID_MASK 0x00000400
-#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_DESC_SLOT1_STATUS_1_PID_CHANNEL_VALID_SHIFT 10
-
-/* XPT_MEMDMA_MCPB_CH0 :: DMA_DESC_SLOT1_STATUS_1 :: PID_CHANNEL [09:00] */
-#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_DESC_SLOT1_STATUS_1_PID_CHANNEL_MASK 0x000003ff
-#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_DESC_SLOT1_STATUS_1_PID_CHANNEL_SHIFT 0
-
-/***************************************************************************
- *DMA_DESC_SLOT1_CURR_DESC_ADDR - MCPB Channel x Descriptor Slot 1 Current Descriptor Address
- ***************************************************************************/
-/* XPT_MEMDMA_MCPB_CH0 :: DMA_DESC_SLOT1_CURR_DESC_ADDR :: CUR_DESC_ADDR [31:00] */
-#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_DESC_SLOT1_CURR_DESC_ADDR_CUR_DESC_ADDR_MASK 0xffffffff
-#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_DESC_SLOT1_CURR_DESC_ADDR_CUR_DESC_ADDR_SHIFT 0
-
-/***************************************************************************
- *DMA_DESC_SLOT1_CURR_DATA_ADDR_UPPER - MCPB Channel x Descriptor Slot 1 Current Data Address
- ***************************************************************************/
-/* XPT_MEMDMA_MCPB_CH0 :: DMA_DESC_SLOT1_CURR_DATA_ADDR_UPPER :: reserved0 [31:08] */
-#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_DESC_SLOT1_CURR_DATA_ADDR_UPPER_reserved0_MASK 0xffffff00
-#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_DESC_SLOT1_CURR_DATA_ADDR_UPPER_reserved0_SHIFT 8
-
-/* XPT_MEMDMA_MCPB_CH0 :: DMA_DESC_SLOT1_CURR_DATA_ADDR_UPPER :: CUR_DATA_ADDR [07:00] */
-#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_DESC_SLOT1_CURR_DATA_ADDR_UPPER_CUR_DATA_ADDR_MASK 0x000000ff
-#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_DESC_SLOT1_CURR_DATA_ADDR_UPPER_CUR_DATA_ADDR_SHIFT 0
-
-/***************************************************************************
- *DMA_DESC_SLOT1_CURR_DATA_ADDR_LOWER - MCPB Channel x Descriptor Slot 1 Current Data Address
- ***************************************************************************/
-/* XPT_MEMDMA_MCPB_CH0 :: DMA_DESC_SLOT1_CURR_DATA_ADDR_LOWER :: CUR_DATA_ADDR [31:00] */
-#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_DESC_SLOT1_CURR_DATA_ADDR_LOWER_CUR_DATA_ADDR_MASK 0xffffffff
-#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_DESC_SLOT1_CURR_DATA_ADDR_LOWER_CUR_DATA_ADDR_SHIFT 0
-
-/***************************************************************************
- *DMA_DESC_SLOT1_NEXT_TIMESTAMP - MCPB Channel x Descriptor Slot 1 Next Packet Timestamp
- ***************************************************************************/
-/* XPT_MEMDMA_MCPB_CH0 :: DMA_DESC_SLOT1_NEXT_TIMESTAMP :: NEXT_TIMESTAMP [31:00] */
-#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_DESC_SLOT1_NEXT_TIMESTAMP_NEXT_TIMESTAMP_MASK 0xffffffff
-#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_DESC_SLOT1_NEXT_TIMESTAMP_NEXT_TIMESTAMP_SHIFT 0
-
-/***************************************************************************
- *DMA_DESC_SLOT1_PKT2PKT_TIMESTAMP_DELTA - MCPB Channel x Descriptor Slot 1 Packet to packet Timestamp delta
- ***************************************************************************/
-/* XPT_MEMDMA_MCPB_CH0 :: DMA_DESC_SLOT1_PKT2PKT_TIMESTAMP_DELTA :: PKT2PKT_TIMESTAMP_DELTA [31:00] */
-#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_DESC_SLOT1_PKT2PKT_TIMESTAMP_DELTA_PKT2PKT_TIMESTAMP_DELTA_MASK 0xffffffff
-#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_DESC_SLOT1_PKT2PKT_TIMESTAMP_DELTA_PKT2PKT_TIMESTAMP_DELTA_SHIFT 0
-
-/***************************************************************************
- *SP_PKT_LEN - MCPB Channel x Packet length control
- ***************************************************************************/
-/* XPT_MEMDMA_MCPB_CH0 :: SP_PKT_LEN :: PACKET_LENGTH [31:00] */
-#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_PKT_LEN_PACKET_LENGTH_MASK 0xffffffff
-#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_PKT_LEN_PACKET_LENGTH_SHIFT 0
-
-/***************************************************************************
- *SP_PARSER_CTRL - MCPB Channel x Parser control
- ***************************************************************************/
-/* XPT_MEMDMA_MCPB_CH0 :: SP_PARSER_CTRL :: reserved0 [31:26] */
-#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_PARSER_CTRL_reserved0_MASK 0xfc000000
-#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_PARSER_CTRL_reserved0_SHIFT 26
-
-/* XPT_MEMDMA_MCPB_CH0 :: SP_PARSER_CTRL :: STANDALONE_BLOCK_MODE_MEM_DMA_GR_SEL [25:24] */
-#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_PARSER_CTRL_STANDALONE_BLOCK_MODE_MEM_DMA_GR_SEL_MASK 0x03000000
-#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_PARSER_CTRL_STANDALONE_BLOCK_MODE_MEM_DMA_GR_SEL_SHIFT 24
-
-/* XPT_MEMDMA_MCPB_CH0 :: SP_PARSER_CTRL :: STANDALONE_BLOCK_MODE_EN [23:23] */
-#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_PARSER_CTRL_STANDALONE_BLOCK_MODE_EN_MASK 0x00800000
-#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_PARSER_CTRL_STANDALONE_BLOCK_MODE_EN_SHIFT 23
-
-/* XPT_MEMDMA_MCPB_CH0 :: SP_PARSER_CTRL :: SCRAM_START_END_FOR_EVERY_PACKET [22:22] */
-#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_PARSER_CTRL_SCRAM_START_END_FOR_EVERY_PACKET_MASK 0x00400000
-#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_PARSER_CTRL_SCRAM_START_END_FOR_EVERY_PACKET_SHIFT 22
-
-/* XPT_MEMDMA_MCPB_CH0 :: SP_PARSER_CTRL :: reserved1 [21:18] */
-#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_PARSER_CTRL_reserved1_MASK 0x003c0000
-#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_PARSER_CTRL_reserved1_SHIFT 18
-
-/* XPT_MEMDMA_MCPB_CH0 :: SP_PARSER_CTRL :: PUSI_SET_DIS [17:17] */
-#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_PARSER_CTRL_PUSI_SET_DIS_MASK 0x00020000
-#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_PARSER_CTRL_PUSI_SET_DIS_SHIFT 17
-
-/* XPT_MEMDMA_MCPB_CH0 :: SP_PARSER_CTRL :: reserved2 [16:15] */
-#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_PARSER_CTRL_reserved2_MASK 0x00018000
-#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_PARSER_CTRL_reserved2_SHIFT 15
-
-/* XPT_MEMDMA_MCPB_CH0 :: SP_PARSER_CTRL :: PB_PARSER_SEL [14:14] */
-#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_PARSER_CTRL_PB_PARSER_SEL_MASK 0x00004000
-#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_PARSER_CTRL_PB_PARSER_SEL_SHIFT 14
-
-/* XPT_MEMDMA_MCPB_CH0 :: SP_PARSER_CTRL :: PB_PARSER_BAND_ID [13:06] */
-#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_PARSER_CTRL_PB_PARSER_BAND_ID_MASK 0x00003fc0
-#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_PARSER_CTRL_PB_PARSER_BAND_ID_SHIFT 6
-
-/* XPT_MEMDMA_MCPB_CH0 :: SP_PARSER_CTRL :: reserved3 [05:05] */
-#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_PARSER_CTRL_reserved3_MASK 0x00000020
-#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_PARSER_CTRL_reserved3_SHIFT 5
-
-/* XPT_MEMDMA_MCPB_CH0 :: SP_PARSER_CTRL :: PARSER_ALL_PASS_CTRL [04:04] */
-#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_PARSER_CTRL_PARSER_ALL_PASS_CTRL_MASK 0x00000010
-#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_PARSER_CTRL_PARSER_ALL_PASS_CTRL_SHIFT 4
-
-/* XPT_MEMDMA_MCPB_CH0 :: SP_PARSER_CTRL :: PARSER_STREAM_TYPE [03:01] */
-#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_PARSER_CTRL_PARSER_STREAM_TYPE_MASK 0x0000000e
-#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_PARSER_CTRL_PARSER_STREAM_TYPE_SHIFT 1
-
-/* XPT_MEMDMA_MCPB_CH0 :: SP_PARSER_CTRL :: PARSER_ENABLE [00:00] */
-#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_PARSER_CTRL_PARSER_ENABLE_MASK 0x00000001
-#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_PARSER_CTRL_PARSER_ENABLE_SHIFT 0
-
-/***************************************************************************
- *SP_PARSER_CTRL1 - MCPB Channel x Parser control 1
- ***************************************************************************/
-/* XPT_MEMDMA_MCPB_CH0 :: SP_PARSER_CTRL1 :: reserved0 [31:13] */
-#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_PARSER_CTRL1_reserved0_MASK 0xffffe000
-#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_PARSER_CTRL1_reserved0_SHIFT 13
-
-/* XPT_MEMDMA_MCPB_CH0 :: SP_PARSER_CTRL1 :: PIDP_DEBUG_MODE [12:12] */
-#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_PARSER_CTRL1_PIDP_DEBUG_MODE_MASK 0x00001000
-#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_PARSER_CTRL1_PIDP_DEBUG_MODE_SHIFT 12
-
-/* XPT_MEMDMA_MCPB_CH0 :: SP_PARSER_CTRL1 :: ALL_PASS_PID_CH_NUM [11:00] */
-#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_PARSER_CTRL1_ALL_PASS_PID_CH_NUM_MASK 0x00000fff
-#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_PARSER_CTRL1_ALL_PASS_PID_CH_NUM_SHIFT 0
-
-/***************************************************************************
- *SP_TS_CONFIG - MCPB Channel x TS Configuration
- ***************************************************************************/
-/* XPT_MEMDMA_MCPB_CH0 :: SP_TS_CONFIG :: reserved0 [31:31] */
-#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_TS_CONFIG_reserved0_MASK 0x80000000
-#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_TS_CONFIG_reserved0_SHIFT 31
-
-/* XPT_MEMDMA_MCPB_CH0 :: SP_TS_CONFIG :: IGNORE_AFID [30:30] */
-#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_TS_CONFIG_IGNORE_AFID_MASK 0x40000000
-#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_TS_CONFIG_IGNORE_AFID_SHIFT 30
-
-/* XPT_MEMDMA_MCPB_CH0 :: SP_TS_CONFIG :: IGNORE_CFF [29:29] */
-#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_TS_CONFIG_IGNORE_CFF_MASK 0x20000000
-#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_TS_CONFIG_IGNORE_CFF_SHIFT 29
-
-/* XPT_MEMDMA_MCPB_CH0 :: SP_TS_CONFIG :: IGNORE_RTS00 [28:28] */
-#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_TS_CONFIG_IGNORE_RTS00_MASK 0x10000000
-#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_TS_CONFIG_IGNORE_RTS00_SHIFT 28
-
-/* XPT_MEMDMA_MCPB_CH0 :: SP_TS_CONFIG :: IGNORE_AFS [27:27] */
-#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_TS_CONFIG_IGNORE_AFS_MASK 0x08000000
-#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_TS_CONFIG_IGNORE_AFS_SHIFT 27
-
-/* XPT_MEMDMA_MCPB_CH0 :: SP_TS_CONFIG :: IGNORE_CC [26:26] */
-#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_TS_CONFIG_IGNORE_CC_MASK 0x04000000
-#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_TS_CONFIG_IGNORE_CC_SHIFT 26
-
-/* XPT_MEMDMA_MCPB_CH0 :: SP_TS_CONFIG :: IGNORE_OCF [25:25] */
-#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_TS_CONFIG_IGNORE_OCF_MASK 0x02000000
-#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_TS_CONFIG_IGNORE_OCF_SHIFT 25
-
-/* XPT_MEMDMA_MCPB_CH0 :: SP_TS_CONFIG :: IGNORE_SCF [24:24] */
-#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_TS_CONFIG_IGNORE_SCF_MASK 0x01000000
-#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_TS_CONFIG_IGNORE_SCF_SHIFT 24
-
-/* XPT_MEMDMA_MCPB_CH0 :: SP_TS_CONFIG :: reserved1 [23:21] */
-#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_TS_CONFIG_reserved1_MASK 0x00e00000
-#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_TS_CONFIG_reserved1_SHIFT 21
-
-/* XPT_MEMDMA_MCPB_CH0 :: SP_TS_CONFIG :: PCR_PACING_PID [20:08] */
-#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_TS_CONFIG_PCR_PACING_PID_MASK 0x001fff00
-#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_TS_CONFIG_PCR_PACING_PID_SHIFT 8
-
-/* XPT_MEMDMA_MCPB_CH0 :: SP_TS_CONFIG :: reserved2 [07:06] */
-#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_TS_CONFIG_reserved2_MASK 0x000000c0
-#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_TS_CONFIG_reserved2_SHIFT 6
-
-/* XPT_MEMDMA_MCPB_CH0 :: SP_TS_CONFIG :: INPUT_TEI_IGNORE [05:05] */
-#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_TS_CONFIG_INPUT_TEI_IGNORE_MASK 0x00000020
-#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_TS_CONFIG_INPUT_TEI_IGNORE_SHIFT 5
-
-/* XPT_MEMDMA_MCPB_CH0 :: SP_TS_CONFIG :: reserved3 [04:04] */
-#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_TS_CONFIG_reserved3_MASK 0x00000010
-#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_TS_CONFIG_reserved3_SHIFT 4
-
-/* XPT_MEMDMA_MCPB_CH0 :: SP_TS_CONFIG :: PARSER_ACCEPT_NULL_PKT [03:03] */
-#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_TS_CONFIG_PARSER_ACCEPT_NULL_PKT_MASK 0x00000008
-#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_TS_CONFIG_PARSER_ACCEPT_NULL_PKT_SHIFT 3
-
-/* XPT_MEMDMA_MCPB_CH0 :: SP_TS_CONFIG :: ATS_PARITY_CHECK_DIS [02:02] */
-#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_TS_CONFIG_ATS_PARITY_CHECK_DIS_MASK 0x00000004
-#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_TS_CONFIG_ATS_PARITY_CHECK_DIS_SHIFT 2
-
-/* XPT_MEMDMA_MCPB_CH0 :: SP_TS_CONFIG :: INPUT_HAS_ATS [01:01] */
-#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_TS_CONFIG_INPUT_HAS_ATS_MASK 0x00000002
-#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_TS_CONFIG_INPUT_HAS_ATS_SHIFT 1
-
-/* XPT_MEMDMA_MCPB_CH0 :: SP_TS_CONFIG :: MPEG_TS_AUTO_SYNC_DETECT [00:00] */
-#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_TS_CONFIG_MPEG_TS_AUTO_SYNC_DETECT_MASK 0x00000001
-#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_TS_CONFIG_MPEG_TS_AUTO_SYNC_DETECT_SHIFT 0
-
-/***************************************************************************
- *SP_PES_ES_CONFIG - MCPB Channel x PES and ES Configuration
- ***************************************************************************/
-/* XPT_MEMDMA_MCPB_CH0 :: SP_PES_ES_CONFIG :: reserved0 [31:22] */
-#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_PES_ES_CONFIG_reserved0_MASK 0xffc00000
-#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_PES_ES_CONFIG_reserved0_SHIFT 22
-
-/* XPT_MEMDMA_MCPB_CH0 :: SP_PES_ES_CONFIG :: PKTZ_SC [21:20] */
-#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_PES_ES_CONFIG_PKTZ_SC_MASK 0x00300000
-#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_PES_ES_CONFIG_PKTZ_SC_SHIFT 20
-
-/* XPT_MEMDMA_MCPB_CH0 :: SP_PES_ES_CONFIG :: STREAM_ID_EXT_EN [19:19] */
-#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_PES_ES_CONFIG_STREAM_ID_EXT_EN_MASK 0x00080000
-#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_PES_ES_CONFIG_STREAM_ID_EXT_EN_SHIFT 19
-
-/* XPT_MEMDMA_MCPB_CH0 :: SP_PES_ES_CONFIG :: SUB_STREAM_ID_EXT_EN [18:18] */
-#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_PES_ES_CONFIG_SUB_STREAM_ID_EXT_EN_MASK 0x00040000
-#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_PES_ES_CONFIG_SUB_STREAM_ID_EXT_EN_SHIFT 18
-
-/* XPT_MEMDMA_MCPB_CH0 :: SP_PES_ES_CONFIG :: PROGRAM_STREAM_EN [17:17] */
-#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_PES_ES_CONFIG_PROGRAM_STREAM_EN_MASK 0x00020000
-#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_PES_ES_CONFIG_PROGRAM_STREAM_EN_SHIFT 17
-
-/* XPT_MEMDMA_MCPB_CH0 :: SP_PES_ES_CONFIG :: PROGRAM_STREAM_MODE [16:16] */
-#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_PES_ES_CONFIG_PROGRAM_STREAM_MODE_MASK 0x00010000
-#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_PES_ES_CONFIG_PROGRAM_STREAM_MODE_SHIFT 16
-
-/* XPT_MEMDMA_MCPB_CH0 :: SP_PES_ES_CONFIG :: SYNC_ID_HIGH [15:08] */
-#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_PES_ES_CONFIG_SYNC_ID_HIGH_MASK 0x0000ff00
-#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_PES_ES_CONFIG_SYNC_ID_HIGH_SHIFT 8
-
-/* XPT_MEMDMA_MCPB_CH0 :: SP_PES_ES_CONFIG :: SYNC_ID_LOW [07:00] */
-#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_PES_ES_CONFIG_SYNC_ID_LOW_MASK 0x000000ff
-#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_PES_ES_CONFIG_SYNC_ID_LOW_SHIFT 0
-
-/***************************************************************************
- *SP_PES_SYNC_COUNTER - MCPB Channel x PES Sync counter
- ***************************************************************************/
-/* XPT_MEMDMA_MCPB_CH0 :: SP_PES_SYNC_COUNTER :: PES_SYNC_COUNTER [31:00] */
-#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_PES_SYNC_COUNTER_PES_SYNC_COUNTER_MASK 0xffffffff
-#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_PES_SYNC_COUNTER_PES_SYNC_COUNTER_SHIFT 0
-
-/***************************************************************************
- *SP_ASF_CONFIG - MCPB Channel x ASF Configuration
- ***************************************************************************/
-/* XPT_MEMDMA_MCPB_CH0 :: SP_ASF_CONFIG :: reserved0 [31:24] */
-#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_ASF_CONFIG_reserved0_MASK 0xff000000
-#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_ASF_CONFIG_reserved0_SHIFT 24
-
-/* XPT_MEMDMA_MCPB_CH0 :: SP_ASF_CONFIG :: ASF_PAYLOAD_SPACE [23:16] */
-#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_ASF_CONFIG_ASF_PAYLOAD_SPACE_MASK 0x00ff0000
-#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_ASF_CONFIG_ASF_PAYLOAD_SPACE_SHIFT 16
-
-/* XPT_MEMDMA_MCPB_CH0 :: SP_ASF_CONFIG :: reserved1 [15:12] */
-#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_ASF_CONFIG_reserved1_MASK 0x0000f000
-#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_ASF_CONFIG_reserved1_SHIFT 12
-
-/* XPT_MEMDMA_MCPB_CH0 :: SP_ASF_CONFIG :: ASF_DATA_PACKET_LENGTH_VALID [11:11] */
-#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_ASF_CONFIG_ASF_DATA_PACKET_LENGTH_VALID_MASK 0x00000800
-#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_ASF_CONFIG_ASF_DATA_PACKET_LENGTH_VALID_SHIFT 11
-
-/* XPT_MEMDMA_MCPB_CH0 :: SP_ASF_CONFIG :: ASF_ADAPTIVE_PACKET_LENGTH_ENABLE [10:10] */
-#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_ASF_CONFIG_ASF_ADAPTIVE_PACKET_LENGTH_ENABLE_MASK 0x00000400
-#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_ASF_CONFIG_ASF_ADAPTIVE_PACKET_LENGTH_ENABLE_SHIFT 10
-
-/* XPT_MEMDMA_MCPB_CH0 :: SP_ASF_CONFIG :: ASF_PAYLOAD_SC [09:08] */
-#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_ASF_CONFIG_ASF_PAYLOAD_SC_MASK 0x00000300
-#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_ASF_CONFIG_ASF_PAYLOAD_SC_SHIFT 8
-
-/* XPT_MEMDMA_MCPB_CH0 :: SP_ASF_CONFIG :: ASF_SUB_PAYLOAD_SC [07:06] */
-#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_ASF_CONFIG_ASF_SUB_PAYLOAD_SC_MASK 0x000000c0
-#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_ASF_CONFIG_ASF_SUB_PAYLOAD_SC_SHIFT 6
-
-/* XPT_MEMDMA_MCPB_CH0 :: SP_ASF_CONFIG :: reserved2 [05:05] */
-#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_ASF_CONFIG_reserved2_MASK 0x00000020
-#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_ASF_CONFIG_reserved2_SHIFT 5
-
-/* XPT_MEMDMA_MCPB_CH0 :: SP_ASF_CONFIG :: ASF_TYPE_80_GEN_EN [04:04] */
-#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_ASF_CONFIG_ASF_TYPE_80_GEN_EN_MASK 0x00000010
-#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_ASF_CONFIG_ASF_TYPE_80_GEN_EN_SHIFT 4
-
-/* XPT_MEMDMA_MCPB_CH0 :: SP_ASF_CONFIG :: ASF_TYPE_8F_GEN_EN [03:03] */
-#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_ASF_CONFIG_ASF_TYPE_8F_GEN_EN_MASK 0x00000008
-#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_ASF_CONFIG_ASF_TYPE_8F_GEN_EN_SHIFT 3
-
-/* XPT_MEMDMA_MCPB_CH0 :: SP_ASF_CONFIG :: ASF_TEST_HALT [02:02] */
-#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_ASF_CONFIG_ASF_TEST_HALT_MASK 0x00000004
-#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_ASF_CONFIG_ASF_TEST_HALT_SHIFT 2
-
-/* XPT_MEMDMA_MCPB_CH0 :: SP_ASF_CONFIG :: ASF_STREAM_LENGTH_ENDIANESS [01:01] */
-#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_ASF_CONFIG_ASF_STREAM_LENGTH_ENDIANESS_MASK 0x00000002
-#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_ASF_CONFIG_ASF_STREAM_LENGTH_ENDIANESS_SHIFT 1
-
-/* XPT_MEMDMA_MCPB_CH0 :: SP_ASF_CONFIG :: reserved3 [00:00] */
-#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_ASF_CONFIG_reserved3_MASK 0x00000001
-#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_ASF_CONFIG_reserved3_SHIFT 0
-
-/***************************************************************************
- *SP_STATE_REG_0 - MCPB Channel x Stream Processor State Register 0
- ***************************************************************************/
-/* union - case NON_BLOCK_MODE [31:00] */
-/* XPT_MEMDMA_MCPB_CH0 :: SP_STATE_REG_0 :: NON_BLOCK_MODE :: RA1_BYTE4 [31:24] */
-#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_0_NON_BLOCK_MODE_RA1_BYTE4_MASK 0xff000000
-#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_0_NON_BLOCK_MODE_RA1_BYTE4_SHIFT 24
-
-/* XPT_MEMDMA_MCPB_CH0 :: SP_STATE_REG_0 :: NON_BLOCK_MODE :: RA1_BYTE3 [23:16] */
-#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_0_NON_BLOCK_MODE_RA1_BYTE3_MASK 0x00ff0000
-#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_0_NON_BLOCK_MODE_RA1_BYTE3_SHIFT 16
-
-/* XPT_MEMDMA_MCPB_CH0 :: SP_STATE_REG_0 :: NON_BLOCK_MODE :: RA1_BYTE2 [15:08] */
-#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_0_NON_BLOCK_MODE_RA1_BYTE2_MASK 0x0000ff00
-#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_0_NON_BLOCK_MODE_RA1_BYTE2_SHIFT 8
-
-/* XPT_MEMDMA_MCPB_CH0 :: SP_STATE_REG_0 :: NON_BLOCK_MODE :: RA1_BYTE1 [07:00] */
-#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_0_NON_BLOCK_MODE_RA1_BYTE1_MASK 0x000000ff
-#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_0_NON_BLOCK_MODE_RA1_BYTE1_SHIFT 0
-
-/* union - case BLOCK_MODE [31:00] */
-/* XPT_MEMDMA_MCPB_CH0 :: SP_STATE_REG_0 :: BLOCK_MODE :: RA1_WORD5 [31:00] */
-#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_0_BLOCK_MODE_RA1_WORD5_MASK 0xffffffff
-#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_0_BLOCK_MODE_RA1_WORD5_SHIFT 0
-
-/***************************************************************************
- *SP_STATE_REG_1 - MCPB Channel x Stream Processor State Register 1
- ***************************************************************************/
-/* union - case MPEG [31:00] */
-/* XPT_MEMDMA_MCPB_CH0 :: SP_STATE_REG_1 :: MPEG :: DATA_ACCUM_VALID [31:28] */
-#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_1_MPEG_DATA_ACCUM_VALID_MASK 0xf0000000
-#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_1_MPEG_DATA_ACCUM_VALID_SHIFT 28
-
-/* XPT_MEMDMA_MCPB_CH0 :: SP_STATE_REG_1 :: MPEG :: TS_STATE [27:22] */
-#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_1_MPEG_TS_STATE_MASK 0x0fc00000
-#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_1_MPEG_TS_STATE_SHIFT 22
-
-/* XPT_MEMDMA_MCPB_CH0 :: SP_STATE_REG_1 :: MPEG :: OUT_OF_SYNC [21:21] */
-#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_1_MPEG_OUT_OF_SYNC_MASK 0x00200000
-#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_1_MPEG_OUT_OF_SYNC_SHIFT 21
-
-/* XPT_MEMDMA_MCPB_CH0 :: SP_STATE_REG_1 :: MPEG :: TIMESTAMP_VALID [20:20] */
-#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_1_MPEG_TIMESTAMP_VALID_MASK 0x00100000
-#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_1_MPEG_TIMESTAMP_VALID_SHIFT 20
-
-/* XPT_MEMDMA_MCPB_CH0 :: SP_STATE_REG_1 :: MPEG :: ADP_CNTL_1 [19:19] */
-#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_1_MPEG_ADP_CNTL_1_MASK 0x00080000
-#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_1_MPEG_ADP_CNTL_1_SHIFT 19
-
-/* XPT_MEMDMA_MCPB_CH0 :: SP_STATE_REG_1 :: MPEG :: ADP_LEN [18:11] */
-#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_1_MPEG_ADP_LEN_MASK 0x0007f800
-#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_1_MPEG_ADP_LEN_SHIFT 11
-
-/* XPT_MEMDMA_MCPB_CH0 :: SP_STATE_REG_1 :: MPEG :: DISCONT_IND [10:10] */
-#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_1_MPEG_DISCONT_IND_MASK 0x00000400
-#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_1_MPEG_DISCONT_IND_SHIFT 10
-
-/* XPT_MEMDMA_MCPB_CH0 :: SP_STATE_REG_1 :: MPEG :: PCR_FLAG [09:09] */
-#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_1_MPEG_PCR_FLAG_MASK 0x00000200
-#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_1_MPEG_PCR_FLAG_SHIFT 9
-
-/* XPT_MEMDMA_MCPB_CH0 :: SP_STATE_REG_1 :: MPEG :: reserved0 [08:07] */
-#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_1_MPEG_reserved0_MASK 0x00000180
-#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_1_MPEG_reserved0_SHIFT 7
-
-/* XPT_MEMDMA_MCPB_CH0 :: SP_STATE_REG_1 :: MPEG :: DESC_BASE_PACING [06:06] */
-#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_1_MPEG_DESC_BASE_PACING_MASK 0x00000040
-#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_1_MPEG_DESC_BASE_PACING_SHIFT 6
-
-/* XPT_MEMDMA_MCPB_CH0 :: SP_STATE_REG_1 :: MPEG :: reserved1 [05:03] */
-#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_1_MPEG_reserved1_MASK 0x00000038
-#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_1_MPEG_reserved1_SHIFT 3
-
-/* XPT_MEMDMA_MCPB_CH0 :: SP_STATE_REG_1 :: MPEG :: SMU_PKT_DROP [02:02] */
-#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_1_MPEG_SMU_PKT_DROP_MASK 0x00000004
-#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_1_MPEG_SMU_PKT_DROP_SHIFT 2
-
-/* XPT_MEMDMA_MCPB_CH0 :: SP_STATE_REG_1 :: MPEG :: reserved2 [01:00] */
-#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_1_MPEG_reserved2_MASK 0x00000003
-#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_1_MPEG_reserved2_SHIFT 0
-
-/* union - case DSS [31:00] */
-/* XPT_MEMDMA_MCPB_CH0 :: SP_STATE_REG_1 :: DSS :: DATA_ACCUM_VALID [31:28] */
-#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_1_DSS_DATA_ACCUM_VALID_MASK 0xf0000000
-#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_1_DSS_DATA_ACCUM_VALID_SHIFT 28
-
-/* XPT_MEMDMA_MCPB_CH0 :: SP_STATE_REG_1 :: DSS :: TS_STATE [27:22] */
-#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_1_DSS_TS_STATE_MASK 0x0fc00000
-#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_1_DSS_TS_STATE_SHIFT 22
-
-/* XPT_MEMDMA_MCPB_CH0 :: SP_STATE_REG_1 :: DSS :: OUT_OF_SYNC [21:21] */
-#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_1_DSS_OUT_OF_SYNC_MASK 0x00200000
-#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_1_DSS_OUT_OF_SYNC_SHIFT 21
-
-/* XPT_MEMDMA_MCPB_CH0 :: SP_STATE_REG_1 :: DSS :: TIMESTAMP_VALID [20:20] */
-#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_1_DSS_TIMESTAMP_VALID_MASK 0x00100000
-#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_1_DSS_TIMESTAMP_VALID_SHIFT 20
-
-/* XPT_MEMDMA_MCPB_CH0 :: SP_STATE_REG_1 :: DSS :: CC_ZERO [19:19] */
-#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_1_DSS_CC_ZERO_MASK 0x00080000
-#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_1_DSS_CC_ZERO_SHIFT 19
-
-/* XPT_MEMDMA_MCPB_CH0 :: SP_STATE_REG_1 :: DSS :: HD_ZERO [18:18] */
-#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_1_DSS_HD_ZERO_MASK 0x00040000
-#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_1_DSS_HD_ZERO_SHIFT 18
-
-/* XPT_MEMDMA_MCPB_CH0 :: SP_STATE_REG_1 :: DSS :: CFF_ONE [17:17] */
-#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_1_DSS_CFF_ONE_MASK 0x00020000
-#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_1_DSS_CFF_ONE_SHIFT 17
-
-/* XPT_MEMDMA_MCPB_CH0 :: SP_STATE_REG_1 :: DSS :: AFID_THREE [16:16] */
-#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_1_DSS_AFID_THREE_MASK 0x00010000
-#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_1_DSS_AFID_THREE_SHIFT 16
-
-/* XPT_MEMDMA_MCPB_CH0 :: SP_STATE_REG_1 :: DSS :: AFS_7D [15:15] */
-#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_1_DSS_AFS_7D_MASK 0x00008000
-#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_1_DSS_AFS_7D_SHIFT 15
-
-/* XPT_MEMDMA_MCPB_CH0 :: SP_STATE_REG_1 :: DSS :: RTS00 [14:14] */
-#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_1_DSS_RTS00_MASK 0x00004000
-#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_1_DSS_RTS00_SHIFT 14
-
-/* XPT_MEMDMA_MCPB_CH0 :: SP_STATE_REG_1 :: DSS :: ORIG_CF [13:13] */
-#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_1_DSS_ORIG_CF_MASK 0x00002000
-#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_1_DSS_ORIG_CF_SHIFT 13
-
-/* XPT_MEMDMA_MCPB_CH0 :: SP_STATE_REG_1 :: DSS :: PF [12:12] */
-#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_1_DSS_PF_MASK 0x00001000
-#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_1_DSS_PF_SHIFT 12
-
-/* XPT_MEMDMA_MCPB_CH0 :: SP_STATE_REG_1 :: DSS :: reserved0 [11:07] */
-#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_1_DSS_reserved0_MASK 0x00000f80
-#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_1_DSS_reserved0_SHIFT 7
-
-/* XPT_MEMDMA_MCPB_CH0 :: SP_STATE_REG_1 :: DSS :: DESC_BASE_PACING [06:06] */
-#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_1_DSS_DESC_BASE_PACING_MASK 0x00000040
-#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_1_DSS_DESC_BASE_PACING_SHIFT 6
-
-/* XPT_MEMDMA_MCPB_CH0 :: SP_STATE_REG_1 :: DSS :: reserved1 [05:03] */
-#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_1_DSS_reserved1_MASK 0x00000038
-#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_1_DSS_reserved1_SHIFT 3
-
-/* XPT_MEMDMA_MCPB_CH0 :: SP_STATE_REG_1 :: DSS :: SMU_PKT_DROP [02:02] */
-#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_1_DSS_SMU_PKT_DROP_MASK 0x00000004
-#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_1_DSS_SMU_PKT_DROP_SHIFT 2
-
-/* XPT_MEMDMA_MCPB_CH0 :: SP_STATE_REG_1 :: DSS :: reserved2 [01:00] */
-#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_1_DSS_reserved2_MASK 0x00000003
-#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_1_DSS_reserved2_SHIFT 0
-
-/* union - case PES_ES_RAW [31:00] */
-/* XPT_MEMDMA_MCPB_CH0 :: SP_STATE_REG_1 :: PES_ES_RAW :: DATA_ACCUM_VALID [31:28] */
-#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_1_PES_ES_RAW_DATA_ACCUM_VALID_MASK 0xf0000000
-#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_1_PES_ES_RAW_DATA_ACCUM_VALID_SHIFT 28
-
-/* XPT_MEMDMA_MCPB_CH0 :: SP_STATE_REG_1 :: PES_ES_RAW :: PES_STATE [27:22] */
-#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_1_PES_ES_RAW_PES_STATE_MASK 0x0fc00000
-#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_1_PES_ES_RAW_PES_STATE_SHIFT 22
-
-/* XPT_MEMDMA_MCPB_CH0 :: SP_STATE_REG_1 :: PES_ES_RAW :: OUT_OF_SYNC [21:21] */
-#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_1_PES_ES_RAW_OUT_OF_SYNC_MASK 0x00200000
-#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_1_PES_ES_RAW_OUT_OF_SYNC_SHIFT 21
-
-/* XPT_MEMDMA_MCPB_CH0 :: SP_STATE_REG_1 :: PES_ES_RAW :: PTS_DTS_FLAGS [20:19] */
-#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_1_PES_ES_RAW_PTS_DTS_FLAGS_MASK 0x00180000
-#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_1_PES_ES_RAW_PTS_DTS_FLAGS_SHIFT 19
-
-/* XPT_MEMDMA_MCPB_CH0 :: SP_STATE_REG_1 :: PES_ES_RAW :: ESCR_FLAG [18:18] */
-#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_1_PES_ES_RAW_ESCR_FLAG_MASK 0x00040000
-#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_1_PES_ES_RAW_ESCR_FLAG_SHIFT 18
-
-/* XPT_MEMDMA_MCPB_CH0 :: SP_STATE_REG_1 :: PES_ES_RAW :: ES_RATE_FLAG [17:17] */
-#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_1_PES_ES_RAW_ES_RATE_FLAG_MASK 0x00020000
-#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_1_PES_ES_RAW_ES_RATE_FLAG_SHIFT 17
-
-/* XPT_MEMDMA_MCPB_CH0 :: SP_STATE_REG_1 :: PES_ES_RAW :: DSM_TRICK_MODE_FLAG [16:16] */
-#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_1_PES_ES_RAW_DSM_TRICK_MODE_FLAG_MASK 0x00010000
-#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_1_PES_ES_RAW_DSM_TRICK_MODE_FLAG_SHIFT 16
-
-/* XPT_MEMDMA_MCPB_CH0 :: SP_STATE_REG_1 :: PES_ES_RAW :: COPY_INFO_FLAG [15:15] */
-#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_1_PES_ES_RAW_COPY_INFO_FLAG_MASK 0x00008000
-#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_1_PES_ES_RAW_COPY_INFO_FLAG_SHIFT 15
-
-/* XPT_MEMDMA_MCPB_CH0 :: SP_STATE_REG_1 :: PES_ES_RAW :: PES_CRC_FLAG [14:14] */
-#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_1_PES_ES_RAW_PES_CRC_FLAG_MASK 0x00004000
-#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_1_PES_ES_RAW_PES_CRC_FLAG_SHIFT 14
-
-/* XPT_MEMDMA_MCPB_CH0 :: SP_STATE_REG_1 :: PES_ES_RAW :: PES_EXT1_FLAG [13:13] */
-#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_1_PES_ES_RAW_PES_EXT1_FLAG_MASK 0x00002000
-#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_1_PES_ES_RAW_PES_EXT1_FLAG_SHIFT 13
-
-/* XPT_MEMDMA_MCPB_CH0 :: SP_STATE_REG_1 :: PES_ES_RAW :: PES_PRIVATE_DATA_FLAG [12:12] */
-#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_1_PES_ES_RAW_PES_PRIVATE_DATA_FLAG_MASK 0x00001000
-#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_1_PES_ES_RAW_PES_PRIVATE_DATA_FLAG_SHIFT 12
-
-/* XPT_MEMDMA_MCPB_CH0 :: SP_STATE_REG_1 :: PES_ES_RAW :: PHF_FLAG [11:11] */
-#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_1_PES_ES_RAW_PHF_FLAG_MASK 0x00000800
-#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_1_PES_ES_RAW_PHF_FLAG_SHIFT 11
-
-/* XPT_MEMDMA_MCPB_CH0 :: SP_STATE_REG_1 :: PES_ES_RAW :: PGRM_PKT_SEQ_FLAG [10:10] */
-#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_1_PES_ES_RAW_PGRM_PKT_SEQ_FLAG_MASK 0x00000400
-#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_1_PES_ES_RAW_PGRM_PKT_SEQ_FLAG_SHIFT 10
-
-/* XPT_MEMDMA_MCPB_CH0 :: SP_STATE_REG_1 :: PES_ES_RAW :: PSTD_BUFFER_FLAG [09:09] */
-#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_1_PES_ES_RAW_PSTD_BUFFER_FLAG_MASK 0x00000200
-#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_1_PES_ES_RAW_PSTD_BUFFER_FLAG_SHIFT 9
-
-/* XPT_MEMDMA_MCPB_CH0 :: SP_STATE_REG_1 :: PES_ES_RAW :: PES_EXT2_FLAG [08:08] */
-#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_1_PES_ES_RAW_PES_EXT2_FLAG_MASK 0x00000100
-#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_1_PES_ES_RAW_PES_EXT2_FLAG_SHIFT 8
-
-/* XPT_MEMDMA_MCPB_CH0 :: SP_STATE_REG_1 :: PES_ES_RAW :: reserved0 [07:03] */
-#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_1_PES_ES_RAW_reserved0_MASK 0x000000f8
-#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_1_PES_ES_RAW_reserved0_SHIFT 3
-
-/* XPT_MEMDMA_MCPB_CH0 :: SP_STATE_REG_1 :: PES_ES_RAW :: SMU_PKT_DROP [02:02] */
-#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_1_PES_ES_RAW_SMU_PKT_DROP_MASK 0x00000004
-#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_1_PES_ES_RAW_SMU_PKT_DROP_SHIFT 2
-
-/* XPT_MEMDMA_MCPB_CH0 :: SP_STATE_REG_1 :: PES_ES_RAW :: NEW_PKT_START [01:01] */
-#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_1_PES_ES_RAW_NEW_PKT_START_MASK 0x00000002
-#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_1_PES_ES_RAW_NEW_PKT_START_SHIFT 1
-
-/* XPT_MEMDMA_MCPB_CH0 :: SP_STATE_REG_1 :: PES_ES_RAW :: reserved1 [00:00] */
-#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_1_PES_ES_RAW_reserved1_MASK 0x00000001
-#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_1_PES_ES_RAW_reserved1_SHIFT 0
-
-/* union - case ASF [31:00] */
-/* XPT_MEMDMA_MCPB_CH0 :: SP_STATE_REG_1 :: ASF :: DATA_ACCUM_VALID [31:28] */
-#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_1_ASF_DATA_ACCUM_VALID_MASK 0xf0000000
-#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_1_ASF_DATA_ACCUM_VALID_SHIFT 28
-
-/* XPT_MEMDMA_MCPB_CH0 :: SP_STATE_REG_1 :: ASF :: ASF_STATE [27:21] */
-#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_1_ASF_ASF_STATE_MASK 0x0fe00000
-#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_1_ASF_ASF_STATE_SHIFT 21
-
-/* XPT_MEMDMA_MCPB_CH0 :: SP_STATE_REG_1 :: ASF :: SEQUENCE_TYPE [20:19] */
-#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_1_ASF_SEQUENCE_TYPE_MASK 0x00180000
-#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_1_ASF_SEQUENCE_TYPE_SHIFT 19
-
-/* XPT_MEMDMA_MCPB_CH0 :: SP_STATE_REG_1 :: ASF :: PADDING_LEN_TYPE [18:17] */
-#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_1_ASF_PADDING_LEN_TYPE_MASK 0x00060000
-#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_1_ASF_PADDING_LEN_TYPE_SHIFT 17
-
-/* XPT_MEMDMA_MCPB_CH0 :: SP_STATE_REG_1 :: ASF :: PKT_LEN_TYPE [16:15] */
-#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_1_ASF_PKT_LEN_TYPE_MASK 0x00018000
-#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_1_ASF_PKT_LEN_TYPE_SHIFT 15
-
-/* XPT_MEMDMA_MCPB_CH0 :: SP_STATE_REG_1 :: ASF :: REP_DATA_LEN_TYPE [14:13] */
-#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_1_ASF_REP_DATA_LEN_TYPE_MASK 0x00006000
-#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_1_ASF_REP_DATA_LEN_TYPE_SHIFT 13
-
-/* XPT_MEMDMA_MCPB_CH0 :: SP_STATE_REG_1 :: ASF :: OFS_2MED_OBJ_NUM_LEN_TYPE [12:11] */
-#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_1_ASF_OFS_2MED_OBJ_NUM_LEN_TYPE_MASK 0x00001800
-#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_1_ASF_OFS_2MED_OBJ_NUM_LEN_TYPE_SHIFT 11
-
-/* XPT_MEMDMA_MCPB_CH0 :: SP_STATE_REG_1 :: ASF :: MD_OBJ_LEN_TYPE [10:09] */
-#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_1_ASF_MD_OBJ_LEN_TYPE_MASK 0x00000600
-#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_1_ASF_MD_OBJ_LEN_TYPE_SHIFT 9
-
-/* XPT_MEMDMA_MCPB_CH0 :: SP_STATE_REG_1 :: ASF :: PAYLD_LEN_TYPE [08:07] */
-#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_1_ASF_PAYLD_LEN_TYPE_MASK 0x00000180
-#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_1_ASF_PAYLD_LEN_TYPE_SHIFT 7
-
-/* XPT_MEMDMA_MCPB_CH0 :: SP_STATE_REG_1 :: ASF :: MUL_PAYLD_PRESENT [06:06] */
-#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_1_ASF_MUL_PAYLD_PRESENT_MASK 0x00000040
-#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_1_ASF_MUL_PAYLD_PRESENT_SHIFT 6
-
-/* XPT_MEMDMA_MCPB_CH0 :: SP_STATE_REG_1 :: ASF :: REP_DATA_LEN_EQ_ONE [05:05] */
-#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_1_ASF_REP_DATA_LEN_EQ_ONE_MASK 0x00000020
-#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_1_ASF_REP_DATA_LEN_EQ_ONE_SHIFT 5
-
-/* XPT_MEMDMA_MCPB_CH0 :: SP_STATE_REG_1 :: ASF :: reserved0 [04:03] */
-#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_1_ASF_reserved0_MASK 0x00000018
-#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_1_ASF_reserved0_SHIFT 3
-
-/* XPT_MEMDMA_MCPB_CH0 :: SP_STATE_REG_1 :: ASF :: SMU_PKT_DROP [02:02] */
-#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_1_ASF_SMU_PKT_DROP_MASK 0x00000004
-#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_1_ASF_SMU_PKT_DROP_SHIFT 2
-
-/* XPT_MEMDMA_MCPB_CH0 :: SP_STATE_REG_1 :: ASF :: OFS_2MED_OBJ_LEN_ZERO [01:01] */
-#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_1_ASF_OFS_2MED_OBJ_LEN_ZERO_MASK 0x00000002
-#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_1_ASF_OFS_2MED_OBJ_LEN_ZERO_SHIFT 1
-
-/* XPT_MEMDMA_MCPB_CH0 :: SP_STATE_REG_1 :: ASF :: reserved1 [00:00] */
-#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_1_ASF_reserved1_MASK 0x00000001
-#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_1_ASF_reserved1_SHIFT 0
-
-/* union - case BLOCK_MODE [31:00] */
-/* XPT_MEMDMA_MCPB_CH0 :: SP_STATE_REG_1 :: BLOCK_MODE :: RA1_WORD4 [31:00] */
-#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_1_BLOCK_MODE_RA1_WORD4_MASK 0xffffffff
-#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_1_BLOCK_MODE_RA1_WORD4_SHIFT 0
-
-/***************************************************************************
- *SP_STATE_REG_2 - MCPB Channel x Stream Processor State Register 2
- ***************************************************************************/
-/* XPT_MEMDMA_MCPB_CH0 :: SP_STATE_REG_2 :: reserved0 [31:30] */
-#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_2_reserved0_MASK 0xc0000000
-#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_2_reserved0_SHIFT 30
-
-/* XPT_MEMDMA_MCPB_CH0 :: SP_STATE_REG_2 :: PT_SEARCH_DONE [29:29] */
-#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_2_PT_SEARCH_DONE_MASK 0x20000000
-#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_2_PT_SEARCH_DONE_SHIFT 29
-
-/* XPT_MEMDMA_MCPB_CH0 :: SP_STATE_REG_2 :: PT_MATCH [28:28] */
-#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_2_PT_MATCH_MASK 0x10000000
-#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_2_PT_MATCH_SHIFT 28
-
-/* XPT_MEMDMA_MCPB_CH0 :: SP_STATE_REG_2 :: PKT_CH_NUM [27:16] */
-#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_2_PKT_CH_NUM_MASK 0x0fff0000
-#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_2_PKT_CH_NUM_SHIFT 16
-
-/* XPT_MEMDMA_MCPB_CH0 :: SP_STATE_REG_2 :: PKT_DESTINATION [15:00] */
-#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_2_PKT_DESTINATION_MASK 0x0000ffff
-#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_2_PKT_DESTINATION_SHIFT 0
-
-/***************************************************************************
- *SP_STATE_REG_3 - MCPB Channel x Stream Processor State Register 3
- ***************************************************************************/
-/* union - case MPEG [31:00] */
-/* XPT_MEMDMA_MCPB_CH0 :: SP_STATE_REG_3 :: MPEG :: PID [31:19] */
-#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_3_MPEG_PID_MASK 0xfff80000
-#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_3_MPEG_PID_SHIFT 19
-
-/* XPT_MEMDMA_MCPB_CH0 :: SP_STATE_REG_3 :: MPEG :: FIRST_PKT_AFT_RUN_ASSERT [18:18] */
-#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_3_MPEG_FIRST_PKT_AFT_RUN_ASSERT_MASK 0x00040000
-#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_3_MPEG_FIRST_PKT_AFT_RUN_ASSERT_SHIFT 18
-
-/* XPT_MEMDMA_MCPB_CH0 :: SP_STATE_REG_3 :: MPEG :: PCR_FIRST_PKT_AFT_FUN_ASSERT [17:17] */
-#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_3_MPEG_PCR_FIRST_PKT_AFT_FUN_ASSERT_MASK 0x00020000
-#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_3_MPEG_PCR_FIRST_PKT_AFT_FUN_ASSERT_SHIFT 17
-
-/* XPT_MEMDMA_MCPB_CH0 :: SP_STATE_REG_3 :: MPEG :: reserved0 [16:10] */
-#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_3_MPEG_reserved0_MASK 0x0001fc00
-#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_3_MPEG_reserved0_SHIFT 10
-
-/* XPT_MEMDMA_MCPB_CH0 :: SP_STATE_REG_3 :: MPEG :: FORCE_RESYNC [09:09] */
-#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_3_MPEG_FORCE_RESYNC_MASK 0x00000200
-#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_3_MPEG_FORCE_RESYNC_SHIFT 9
-
-/* XPT_MEMDMA_MCPB_CH0 :: SP_STATE_REG_3 :: MPEG :: PCR_FORCE_RESYNC [08:08] */
-#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_3_MPEG_PCR_FORCE_RESYNC_MASK 0x00000100
-#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_3_MPEG_PCR_FORCE_RESYNC_SHIFT 8
-
-/* XPT_MEMDMA_MCPB_CH0 :: SP_STATE_REG_3 :: MPEG :: reserved1 [07:00] */
-#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_3_MPEG_reserved1_MASK 0x000000ff
-#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_3_MPEG_reserved1_SHIFT 0
-
-/* union - case DSS [31:00] */
-/* XPT_MEMDMA_MCPB_CH0 :: SP_STATE_REG_3 :: DSS :: SCID [31:19] */
-#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_3_DSS_SCID_MASK 0xfff80000
-#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_3_DSS_SCID_SHIFT 19
-
-/* XPT_MEMDMA_MCPB_CH0 :: SP_STATE_REG_3 :: DSS :: FIRST_PKT_AFT_RUN_ASSERT [18:18] */
-#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_3_DSS_FIRST_PKT_AFT_RUN_ASSERT_MASK 0x00040000
-#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_3_DSS_FIRST_PKT_AFT_RUN_ASSERT_SHIFT 18
-
-/* XPT_MEMDMA_MCPB_CH0 :: SP_STATE_REG_3 :: DSS :: PCR_FIRST_PKT_AFT_FUN_ASSERT [17:17] */
-#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_3_DSS_PCR_FIRST_PKT_AFT_FUN_ASSERT_MASK 0x00020000
-#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_3_DSS_PCR_FIRST_PKT_AFT_FUN_ASSERT_SHIFT 17
-
-/* XPT_MEMDMA_MCPB_CH0 :: SP_STATE_REG_3 :: DSS :: reserved0 [16:10] */
-#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_3_DSS_reserved0_MASK 0x0001fc00
-#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_3_DSS_reserved0_SHIFT 10
-
-/* XPT_MEMDMA_MCPB_CH0 :: SP_STATE_REG_3 :: DSS :: FORCE_RESYNC [09:09] */
-#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_3_DSS_FORCE_RESYNC_MASK 0x00000200
-#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_3_DSS_FORCE_RESYNC_SHIFT 9
-
-/* XPT_MEMDMA_MCPB_CH0 :: SP_STATE_REG_3 :: DSS :: PCR_FORCE_RESYNC [08:08] */
-#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_3_DSS_PCR_FORCE_RESYNC_MASK 0x00000100
-#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_3_DSS_PCR_FORCE_RESYNC_SHIFT 8
-
-/* XPT_MEMDMA_MCPB_CH0 :: SP_STATE_REG_3 :: DSS :: reserved1 [07:00] */
-#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_3_DSS_reserved1_MASK 0x000000ff
-#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_3_DSS_reserved1_SHIFT 0
-
-/* union - case PES_or_ES_or_RAW [31:00] */
-/* XPT_MEMDMA_MCPB_CH0 :: SP_STATE_REG_3 :: PES_or_ES_or_RAW :: PID [31:19] */
-#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_3_PES_or_ES_or_RAW_PID_MASK 0xfff80000
-#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_3_PES_or_ES_or_RAW_PID_SHIFT 19
-
-/* XPT_MEMDMA_MCPB_CH0 :: SP_STATE_REG_3 :: PES_or_ES_or_RAW :: FIRST_PKT_AFT_RUN_ASSERT [18:18] */
-#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_3_PES_or_ES_or_RAW_FIRST_PKT_AFT_RUN_ASSERT_MASK 0x00040000
-#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_3_PES_or_ES_or_RAW_FIRST_PKT_AFT_RUN_ASSERT_SHIFT 18
-
-/* XPT_MEMDMA_MCPB_CH0 :: SP_STATE_REG_3 :: PES_or_ES_or_RAW :: PUSI [17:17] */
-#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_3_PES_or_ES_or_RAW_PUSI_MASK 0x00020000
-#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_3_PES_or_ES_or_RAW_PUSI_SHIFT 17
-
-/* XPT_MEMDMA_MCPB_CH0 :: SP_STATE_REG_3 :: PES_or_ES_or_RAW :: RAI [16:16] */
-#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_3_PES_or_ES_or_RAW_RAI_MASK 0x00010000
-#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_3_PES_or_ES_or_RAW_RAI_SHIFT 16
-
-/* XPT_MEMDMA_MCPB_CH0 :: SP_STATE_REG_3 :: PES_or_ES_or_RAW :: RAI_LEVEL_1 [15:15] */
-#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_3_PES_or_ES_or_RAW_RAI_LEVEL_1_MASK 0x00008000
-#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_3_PES_or_ES_or_RAW_RAI_LEVEL_1_SHIFT 15
-
-/* XPT_MEMDMA_MCPB_CH0 :: SP_STATE_REG_3 :: PES_or_ES_or_RAW :: reserved0 [14:14] */
-#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_3_PES_or_ES_or_RAW_reserved0_MASK 0x00004000
-#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_3_PES_or_ES_or_RAW_reserved0_SHIFT 14
-
-/* XPT_MEMDMA_MCPB_CH0 :: SP_STATE_REG_3 :: PES_or_ES_or_RAW :: AFC [13:12] */
-#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_3_PES_or_ES_or_RAW_AFC_MASK 0x00003000
-#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_3_PES_or_ES_or_RAW_AFC_SHIFT 12
-
-/* XPT_MEMDMA_MCPB_CH0 :: SP_STATE_REG_3 :: PES_or_ES_or_RAW :: reserved1 [11:10] */
-#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_3_PES_or_ES_or_RAW_reserved1_MASK 0x00000c00
-#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_3_PES_or_ES_or_RAW_reserved1_SHIFT 10
-
-/* XPT_MEMDMA_MCPB_CH0 :: SP_STATE_REG_3 :: PES_or_ES_or_RAW :: FORCE_RESYNC [09:09] */
-#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_3_PES_or_ES_or_RAW_FORCE_RESYNC_MASK 0x00000200
-#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_3_PES_or_ES_or_RAW_FORCE_RESYNC_SHIFT 9
-
-/* XPT_MEMDMA_MCPB_CH0 :: SP_STATE_REG_3 :: PES_or_ES_or_RAW :: reserved2 [08:00] */
-#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_3_PES_or_ES_or_RAW_reserved2_MASK 0x000001ff
-#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_3_PES_or_ES_or_RAW_reserved2_SHIFT 0
-
-/* union - case ASF [31:00] */
-/* XPT_MEMDMA_MCPB_CH0 :: SP_STATE_REG_3 :: ASF :: PID [31:19] */
-#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_3_ASF_PID_MASK 0xfff80000
-#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_3_ASF_PID_SHIFT 19
-
-/* XPT_MEMDMA_MCPB_CH0 :: SP_STATE_REG_3 :: ASF :: FIRST_PKT_AFT_RUN_ASSERT [18:18] */
-#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_3_ASF_FIRST_PKT_AFT_RUN_ASSERT_MASK 0x00040000
-#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_3_ASF_FIRST_PKT_AFT_RUN_ASSERT_SHIFT 18
-
-/* XPT_MEMDMA_MCPB_CH0 :: SP_STATE_REG_3 :: ASF :: PUSI [17:17] */
-#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_3_ASF_PUSI_MASK 0x00020000
-#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_3_ASF_PUSI_SHIFT 17
-
-/* XPT_MEMDMA_MCPB_CH0 :: SP_STATE_REG_3 :: ASF :: RAI [16:16] */
-#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_3_ASF_RAI_MASK 0x00010000
-#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_3_ASF_RAI_SHIFT 16
-
-/* XPT_MEMDMA_MCPB_CH0 :: SP_STATE_REG_3 :: ASF :: RAI_LEVEL_1 [15:15] */
-#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_3_ASF_RAI_LEVEL_1_MASK 0x00008000
-#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_3_ASF_RAI_LEVEL_1_SHIFT 15
-
-/* XPT_MEMDMA_MCPB_CH0 :: SP_STATE_REG_3 :: ASF :: reserved0 [14:14] */
-#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_3_ASF_reserved0_MASK 0x00004000
-#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_3_ASF_reserved0_SHIFT 14
-
-/* XPT_MEMDMA_MCPB_CH0 :: SP_STATE_REG_3 :: ASF :: AFC [13:12] */
-#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_3_ASF_AFC_MASK 0x00003000
-#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_3_ASF_AFC_SHIFT 12
-
-/* XPT_MEMDMA_MCPB_CH0 :: SP_STATE_REG_3 :: ASF :: reserved1 [11:10] */
-#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_3_ASF_reserved1_MASK 0x00000c00
-#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_3_ASF_reserved1_SHIFT 10
-
-/* XPT_MEMDMA_MCPB_CH0 :: SP_STATE_REG_3 :: ASF :: FORCE_RESYNC [09:09] */
-#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_3_ASF_FORCE_RESYNC_MASK 0x00000200
-#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_3_ASF_FORCE_RESYNC_SHIFT 9
-
-/* XPT_MEMDMA_MCPB_CH0 :: SP_STATE_REG_3 :: ASF :: reserved2 [08:06] */
-#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_3_ASF_reserved2_MASK 0x000001c0
-#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_3_ASF_reserved2_SHIFT 6
-
-/* XPT_MEMDMA_MCPB_CH0 :: SP_STATE_REG_3 :: ASF :: NUM_OF_PAYLD [05:00] */
-#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_3_ASF_NUM_OF_PAYLD_MASK 0x0000003f
-#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_3_ASF_NUM_OF_PAYLD_SHIFT 0
-
-/* union - case BLOCK_MODE [31:00] */
-/* XPT_MEMDMA_MCPB_CH0 :: SP_STATE_REG_3 :: BLOCK_MODE :: RA1_WORD3 [31:00] */
-#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_3_BLOCK_MODE_RA1_WORD3_MASK 0xffffffff
-#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_3_BLOCK_MODE_RA1_WORD3_SHIFT 0
-
-/***************************************************************************
- *SP_STATE_REG_4 - MCPB Channel x Stream Processor State Register 4
- ***************************************************************************/
-/* union - case MPEG_or_DSS [31:00] */
-/* XPT_MEMDMA_MCPB_CH0 :: SP_STATE_REG_4 :: MPEG_or_DSS :: GEN_COUNT0 [31:24] */
-#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_4_MPEG_or_DSS_GEN_COUNT0_MASK 0xff000000
-#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_4_MPEG_or_DSS_GEN_COUNT0_SHIFT 24
-
-/* XPT_MEMDMA_MCPB_CH0 :: SP_STATE_REG_4 :: MPEG_or_DSS :: reserved0 [23:00] */
-#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_4_MPEG_or_DSS_reserved0_MASK 0x00ffffff
-#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_4_MPEG_or_DSS_reserved0_SHIFT 0
-
-/* union - case PES_or_ES_or_RAW [31:00] */
-/* XPT_MEMDMA_MCPB_CH0 :: SP_STATE_REG_4 :: PES_or_ES_or_RAW :: GEN_COUNT0 [31:24] */
-#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_4_PES_or_ES_or_RAW_GEN_COUNT0_MASK 0xff000000
-#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_4_PES_or_ES_or_RAW_GEN_COUNT0_SHIFT 24
-
-/* XPT_MEMDMA_MCPB_CH0 :: SP_STATE_REG_4 :: PES_or_ES_or_RAW :: reserved0 [23:16] */
-#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_4_PES_or_ES_or_RAW_reserved0_MASK 0x00ff0000
-#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_4_PES_or_ES_or_RAW_reserved0_SHIFT 16
-
-/* XPT_MEMDMA_MCPB_CH0 :: SP_STATE_REG_4 :: PES_or_ES_or_RAW :: PAYLD_SECT_LEN [15:08] */
-#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_4_PES_or_ES_or_RAW_PAYLD_SECT_LEN_MASK 0x0000ff00
-#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_4_PES_or_ES_or_RAW_PAYLD_SECT_LEN_SHIFT 8
-
-/* XPT_MEMDMA_MCPB_CH0 :: SP_STATE_REG_4 :: PES_or_ES_or_RAW :: reserved1 [07:00] */
-#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_4_PES_or_ES_or_RAW_reserved1_MASK 0x000000ff
-#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_4_PES_or_ES_or_RAW_reserved1_SHIFT 0
-
-/* union - case ASF [31:00] */
-/* XPT_MEMDMA_MCPB_CH0 :: SP_STATE_REG_4 :: ASF :: GEN_COUNT0 [31:24] */
-#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_4_ASF_GEN_COUNT0_MASK 0xff000000
-#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_4_ASF_GEN_COUNT0_SHIFT 24
-
-/* XPT_MEMDMA_MCPB_CH0 :: SP_STATE_REG_4 :: ASF :: PRIVATE_DATA_SECT_LEN [23:16] */
-#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_4_ASF_PRIVATE_DATA_SECT_LEN_MASK 0x00ff0000
-#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_4_ASF_PRIVATE_DATA_SECT_LEN_SHIFT 16
-
-/* XPT_MEMDMA_MCPB_CH0 :: SP_STATE_REG_4 :: ASF :: PAYLD_SECT_LEN [15:08] */
-#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_4_ASF_PAYLD_SECT_LEN_MASK 0x0000ff00
-#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_4_ASF_PAYLD_SECT_LEN_SHIFT 8
-
-/* XPT_MEMDMA_MCPB_CH0 :: SP_STATE_REG_4 :: ASF :: reserved0 [07:00] */
-#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_4_ASF_reserved0_MASK 0x000000ff
-#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_4_ASF_reserved0_SHIFT 0
-
-/* union - case BLOCK_MODE [31:00] */
-/* XPT_MEMDMA_MCPB_CH0 :: SP_STATE_REG_4 :: BLOCK_MODE :: RA1_WORD2 [31:00] */
-#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_4_BLOCK_MODE_RA1_WORD2_MASK 0xffffffff
-#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_4_BLOCK_MODE_RA1_WORD2_SHIFT 0
-
-/***************************************************************************
- *SP_STATE_REG_5 - MCPB Channel x Stream Processor State Register 5
- ***************************************************************************/
-/* XPT_MEMDMA_MCPB_CH0 :: SP_STATE_REG_5 :: GEN_COUNT1 [31:00] */
-#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_5_GEN_COUNT1_MASK 0xffffffff
-#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_5_GEN_COUNT1_SHIFT 0
-
-/***************************************************************************
- *SP_STATE_REG_6 - MCPB Channel x Stream Processor State Register 6
- ***************************************************************************/
-/* XPT_MEMDMA_MCPB_CH0 :: SP_STATE_REG_6 :: GEN_COUNT2 [31:00] */
-#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_6_GEN_COUNT2_MASK 0xffffffff
-#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_6_GEN_COUNT2_SHIFT 0
-
-/***************************************************************************
- *SP_STATE_REG_7 - MCPB Channel x Stream Processor State Register 7
- ***************************************************************************/
-/* XPT_MEMDMA_MCPB_CH0 :: SP_STATE_REG_7 :: GEN_COUNT3 [31:00] */
-#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_7_GEN_COUNT3_MASK 0xffffffff
-#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_7_GEN_COUNT3_SHIFT 0
-
-/***************************************************************************
- *SP_STATE_REG_8 - MCPB Channel x Stream Processor State Register 8
- ***************************************************************************/
-/* union - case MPEG [31:00] */
-/* XPT_MEMDMA_MCPB_CH0 :: SP_STATE_REG_8 :: MPEG :: PCR_BASE [31:09] */
-#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_8_MPEG_PCR_BASE_MASK 0xfffffe00
-#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_8_MPEG_PCR_BASE_SHIFT 9
-
-/* XPT_MEMDMA_MCPB_CH0 :: SP_STATE_REG_8 :: MPEG :: PCR_EXT [08:00] */
-#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_8_MPEG_PCR_EXT_MASK 0x000001ff
-#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_8_MPEG_PCR_EXT_SHIFT 0
-
-/* union - case DSS [31:00] */
-/* XPT_MEMDMA_MCPB_CH0 :: SP_STATE_REG_8 :: DSS :: RTS [31:00] */
-#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_8_DSS_RTS_MASK 0xffffffff
-#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_8_DSS_RTS_SHIFT 0
-
-/* union - case PES_or_ES_or_RAW [31:00] */
-/* XPT_MEMDMA_MCPB_CH0 :: SP_STATE_REG_8 :: PES_or_ES_or_RAW :: STREAM_ID [31:24] */
-#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_8_PES_or_ES_or_RAW_STREAM_ID_MASK 0xff000000
-#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_8_PES_or_ES_or_RAW_STREAM_ID_SHIFT 24
-
-/* XPT_MEMDMA_MCPB_CH0 :: SP_STATE_REG_8 :: PES_or_ES_or_RAW :: STREAM_ID_EXT [23:16] */
-#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_8_PES_or_ES_or_RAW_STREAM_ID_EXT_MASK 0x00ff0000
-#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_8_PES_or_ES_or_RAW_STREAM_ID_EXT_SHIFT 16
-
-/* XPT_MEMDMA_MCPB_CH0 :: SP_STATE_REG_8 :: PES_or_ES_or_RAW :: SUB_ID [15:08] */
-#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_8_PES_or_ES_or_RAW_SUB_ID_MASK 0x0000ff00
-#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_8_PES_or_ES_or_RAW_SUB_ID_SHIFT 8
-
-/* XPT_MEMDMA_MCPB_CH0 :: SP_STATE_REG_8 :: PES_or_ES_or_RAW :: STREAM_ID_VALID [07:07] */
-#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_8_PES_or_ES_or_RAW_STREAM_ID_VALID_MASK 0x00000080
-#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_8_PES_or_ES_or_RAW_STREAM_ID_VALID_SHIFT 7
-
-/* XPT_MEMDMA_MCPB_CH0 :: SP_STATE_REG_8 :: PES_or_ES_or_RAW :: STREAM_ID_EXT_VALID [06:06] */
-#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_8_PES_or_ES_or_RAW_STREAM_ID_EXT_VALID_MASK 0x00000040
-#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_8_PES_or_ES_or_RAW_STREAM_ID_EXT_VALID_SHIFT 6
-
-/* XPT_MEMDMA_MCPB_CH0 :: SP_STATE_REG_8 :: PES_or_ES_or_RAW :: SUB_ID_VALID [05:05] */
-#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_8_PES_or_ES_or_RAW_SUB_ID_VALID_MASK 0x00000020
-#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_8_PES_or_ES_or_RAW_SUB_ID_VALID_SHIFT 5
-
-/* XPT_MEMDMA_MCPB_CH0 :: SP_STATE_REG_8 :: PES_or_ES_or_RAW :: reserved0 [04:00] */
-#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_8_PES_or_ES_or_RAW_reserved0_MASK 0x0000001f
-#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_8_PES_or_ES_or_RAW_reserved0_SHIFT 0
-
-/* union - case ASF [31:00] */
-/* XPT_MEMDMA_MCPB_CH0 :: SP_STATE_REG_8 :: ASF :: ASF_PKT_LEN [31:00] */
-#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_8_ASF_ASF_PKT_LEN_MASK 0xffffffff
-#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_8_ASF_ASF_PKT_LEN_SHIFT 0
-
-/* union - case BLOCK_MODE [31:00] */
-/* XPT_MEMDMA_MCPB_CH0 :: SP_STATE_REG_8 :: BLOCK_MODE :: RA1_WORD1 [31:00] */
-#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_8_BLOCK_MODE_RA1_WORD1_MASK 0xffffffff
-#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_8_BLOCK_MODE_RA1_WORD1_SHIFT 0
-
-/***************************************************************************
- *SP_STATE_REG_9 - MCPB Channel x Stream Processor State Register 9
- ***************************************************************************/
-/* XPT_MEMDMA_MCPB_CH0 :: SP_STATE_REG_9 :: DRAM_REGION [31:24] */
-#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_9_DRAM_REGION_MASK 0xff000000
-#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_9_DRAM_REGION_SHIFT 24
-
-/* XPT_MEMDMA_MCPB_CH0 :: SP_STATE_REG_9 :: SEC_OP_PIPE_SEL [23:22] */
-#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_9_SEC_OP_PIPE_SEL_MASK 0x00c00000
-#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_9_SEC_OP_PIPE_SEL_SHIFT 22
-
-/* XPT_MEMDMA_MCPB_CH0 :: SP_STATE_REG_9 :: SECONDARY_PACKET [21:21] */
-#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_9_SECONDARY_PACKET_MASK 0x00200000
-#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_9_SECONDARY_PACKET_SHIFT 21
-
-/* XPT_MEMDMA_MCPB_CH0 :: SP_STATE_REG_9 :: SPID_VERSION [20:18] */
-#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_9_SPID_VERSION_MASK 0x001c0000
-#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_9_SPID_VERSION_SHIFT 18
-
-/* XPT_MEMDMA_MCPB_CH0 :: SP_STATE_REG_9 :: PID_VERSION [17:15] */
-#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_9_PID_VERSION_MASK 0x00038000
-#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_9_PID_VERSION_SHIFT 15
-
-/* XPT_MEMDMA_MCPB_CH0 :: SP_STATE_REG_9 :: BUF_OP_PIPE_SEL [14:12] */
-#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_9_BUF_OP_PIPE_SEL_MASK 0x00007000
-#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_9_BUF_OP_PIPE_SEL_SHIFT 12
-
-/* XPT_MEMDMA_MCPB_CH0 :: SP_STATE_REG_9 :: LAST_CHUNK [11:11] */
-#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_9_LAST_CHUNK_MASK 0x00000800
-#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_9_LAST_CHUNK_SHIFT 11
-
-/* XPT_MEMDMA_MCPB_CH0 :: SP_STATE_REG_9 :: reserved0 [10:10] */
-#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_9_reserved0_MASK 0x00000400
-#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_9_reserved0_SHIFT 10
-
-/* XPT_MEMDMA_MCPB_CH0 :: SP_STATE_REG_9 :: SCRAM_INIT [09:09] */
-#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_9_SCRAM_INIT_MASK 0x00000200
-#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_9_SCRAM_INIT_SHIFT 9
-
-/* XPT_MEMDMA_MCPB_CH0 :: SP_STATE_REG_9 :: SCRAM_START [08:08] */
-#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_9_SCRAM_START_MASK 0x00000100
-#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_9_SCRAM_START_SHIFT 8
-
-/* XPT_MEMDMA_MCPB_CH0 :: SP_STATE_REG_9 :: PKT_BUF_POINTER [07:00] */
-#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_9_PKT_BUF_POINTER_MASK 0x000000ff
-#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_9_PKT_BUF_POINTER_SHIFT 0
-
-/***************************************************************************
- *SP_STATE_REG_10 - MCPB Channel x Stream Processor State Register 10
- ***************************************************************************/
-/* union - case NON_BLOCK_MODE [31:00] */
-/* XPT_MEMDMA_MCPB_CH0 :: SP_STATE_REG_10 :: NON_BLOCK_MODE :: reserved0 [31:16] */
-#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_10_NON_BLOCK_MODE_reserved0_MASK 0xffff0000
-#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_10_NON_BLOCK_MODE_reserved0_SHIFT 16
-
-/* XPT_MEMDMA_MCPB_CH0 :: SP_STATE_REG_10 :: NON_BLOCK_MODE :: EDR4 [15:12] */
-#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_10_NON_BLOCK_MODE_EDR4_MASK 0x0000f000
-#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_10_NON_BLOCK_MODE_EDR4_SHIFT 12
-
-/* XPT_MEMDMA_MCPB_CH0 :: SP_STATE_REG_10 :: NON_BLOCK_MODE :: EDR3 [11:08] */
-#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_10_NON_BLOCK_MODE_EDR3_MASK 0x00000f00
-#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_10_NON_BLOCK_MODE_EDR3_SHIFT 8
-
-/* XPT_MEMDMA_MCPB_CH0 :: SP_STATE_REG_10 :: NON_BLOCK_MODE :: EDR2 [07:04] */
-#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_10_NON_BLOCK_MODE_EDR2_MASK 0x000000f0
-#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_10_NON_BLOCK_MODE_EDR2_SHIFT 4
-
-/* XPT_MEMDMA_MCPB_CH0 :: SP_STATE_REG_10 :: NON_BLOCK_MODE :: EDR1 [03:00] */
-#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_10_NON_BLOCK_MODE_EDR1_MASK 0x0000000f
-#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_10_NON_BLOCK_MODE_EDR1_SHIFT 0
-
-/* union - case BLOCK_MODE [31:00] */
-/* XPT_MEMDMA_MCPB_CH0 :: SP_STATE_REG_10 :: BLOCK_MODE :: reserved0 [31:29] */
-#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_10_BLOCK_MODE_reserved0_MASK 0xe0000000
-#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_10_BLOCK_MODE_reserved0_SHIFT 29
-
-/* XPT_MEMDMA_MCPB_CH0 :: SP_STATE_REG_10 :: BLOCK_MODE :: BLOCK_MODE_STATES [28:25] */
-#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_10_BLOCK_MODE_BLOCK_MODE_STATES_MASK 0x1e000000
-#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_10_BLOCK_MODE_BLOCK_MODE_STATES_SHIFT 25
-
-/* XPT_MEMDMA_MCPB_CH0 :: SP_STATE_REG_10 :: BLOCK_MODE :: RA1_VALID_5_WORDS [24:20] */
-#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_10_BLOCK_MODE_RA1_VALID_5_WORDS_MASK 0x01f00000
-#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_10_BLOCK_MODE_RA1_VALID_5_WORDS_SHIFT 20
-
-/* XPT_MEMDMA_MCPB_CH0 :: SP_STATE_REG_10 :: BLOCK_MODE :: RA1_5_VALID [19:16] */
-#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_10_BLOCK_MODE_RA1_5_VALID_MASK 0x000f0000
-#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_10_BLOCK_MODE_RA1_5_VALID_SHIFT 16
-
-/* XPT_MEMDMA_MCPB_CH0 :: SP_STATE_REG_10 :: BLOCK_MODE :: RA1_4_VALID [15:12] */
-#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_10_BLOCK_MODE_RA1_4_VALID_MASK 0x0000f000
-#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_10_BLOCK_MODE_RA1_4_VALID_SHIFT 12
-
-/* XPT_MEMDMA_MCPB_CH0 :: SP_STATE_REG_10 :: BLOCK_MODE :: RA1_3_VALID [11:08] */
-#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_10_BLOCK_MODE_RA1_3_VALID_MASK 0x00000f00
-#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_10_BLOCK_MODE_RA1_3_VALID_SHIFT 8
-
-/* XPT_MEMDMA_MCPB_CH0 :: SP_STATE_REG_10 :: BLOCK_MODE :: RA1_2_VALID [07:04] */
-#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_10_BLOCK_MODE_RA1_2_VALID_MASK 0x000000f0
-#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_10_BLOCK_MODE_RA1_2_VALID_SHIFT 4
-
-/* XPT_MEMDMA_MCPB_CH0 :: SP_STATE_REG_10 :: BLOCK_MODE :: RA1_1_VALID [03:00] */
-#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_10_BLOCK_MODE_RA1_1_VALID_MASK 0x0000000f
-#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_10_BLOCK_MODE_RA1_1_VALID_SHIFT 0
-
-/***************************************************************************
- *SP_STATE_REG_11 - MCPB Channel x Stream Processor State Register 11
- ***************************************************************************/
-/* union - case BLOCK_MODE [31:00] */
-/* XPT_MEMDMA_MCPB_CH0 :: SP_STATE_REG_11 :: BLOCK_MODE :: EDR_W5 [31:16] */
-#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_11_BLOCK_MODE_EDR_W5_MASK 0xffff0000
-#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_11_BLOCK_MODE_EDR_W5_SHIFT 16
-
-/* XPT_MEMDMA_MCPB_CH0 :: SP_STATE_REG_11 :: BLOCK_MODE :: EDR_W4 [15:00] */
-#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_11_BLOCK_MODE_EDR_W4_MASK 0x0000ffff
-#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_11_BLOCK_MODE_EDR_W4_SHIFT 0
-
-/* union - case ASF [31:00] */
-/* XPT_MEMDMA_MCPB_CH0 :: SP_STATE_REG_11 :: ASF :: ASF_PPI_PKT_LEN [31:00] */
-#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_11_ASF_ASF_PPI_PKT_LEN_MASK 0xffffffff
-#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_11_ASF_ASF_PPI_PKT_LEN_SHIFT 0
-
-/***************************************************************************
- *SP_STATE_REG_12 - MCPB Channel x Stream Processor State Register 12
- ***************************************************************************/
-/* XPT_MEMDMA_MCPB_CH0 :: SP_STATE_REG_12 :: EDR_W3 [31:16] */
-#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_12_EDR_W3_MASK 0xffff0000
-#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_12_EDR_W3_SHIFT 16
-
-/* XPT_MEMDMA_MCPB_CH0 :: SP_STATE_REG_12 :: EDR_W2 [15:00] */
-#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_12_EDR_W2_MASK 0x0000ffff
-#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_12_EDR_W2_SHIFT 0
-
-/***************************************************************************
- *SP_STATE_REG_13 - MCPB Channel x Stream Processor State Register 13
- ***************************************************************************/
-/* XPT_MEMDMA_MCPB_CH0 :: SP_STATE_REG_13 :: EDR_W1 [31:16] */
-#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_13_EDR_W1_MASK 0xffff0000
-#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_13_EDR_W1_SHIFT 16
-
-/* XPT_MEMDMA_MCPB_CH0 :: SP_STATE_REG_13 :: reserved0 [15:00] */
-#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_13_reserved0_MASK 0x0000ffff
-#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_13_reserved0_SHIFT 0
-
-/***************************************************************************
- *DMA_BBUFF_CTRL - MCPB Channel x Burst buffer control
- ***************************************************************************/
-/* XPT_MEMDMA_MCPB_CH0 :: DMA_BBUFF_CTRL :: reserved0 [31:10] */
-#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_BBUFF_CTRL_reserved0_MASK 0xfffffc00
-#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_BBUFF_CTRL_reserved0_SHIFT 10
-
-/* XPT_MEMDMA_MCPB_CH0 :: DMA_BBUFF_CTRL :: CRC_ERROR_PAUSE_EN [09:09] */
-#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_BBUFF_CTRL_CRC_ERROR_PAUSE_EN_MASK 0x00000200
-#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_BBUFF_CTRL_CRC_ERROR_PAUSE_EN_SHIFT 9
-
-/* XPT_MEMDMA_MCPB_CH0 :: DMA_BBUFF_CTRL :: DMA_BBUFF_SLOT_WISE_READ_EN [08:08] */
-#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_BBUFF_CTRL_DMA_BBUFF_SLOT_WISE_READ_EN_MASK 0x00000100
-#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_BBUFF_CTRL_DMA_BBUFF_SLOT_WISE_READ_EN_SHIFT 8
-
-/* XPT_MEMDMA_MCPB_CH0 :: DMA_BBUFF_CTRL :: STREAM_PROC_FEED_SIZE [07:00] */
-#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_BBUFF_CTRL_STREAM_PROC_FEED_SIZE_MASK 0x000000ff
-#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_BBUFF_CTRL_STREAM_PROC_FEED_SIZE_SHIFT 0
-
-/***************************************************************************
- *DMA_BBUFF_CRC - MCPB Channel x Current CRC value
- ***************************************************************************/
-/* XPT_MEMDMA_MCPB_CH0 :: DMA_BBUFF_CRC :: CRC_VALUE [31:00] */
-#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_BBUFF_CRC_CRC_VALUE_MASK 0xffffffff
-#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_BBUFF_CRC_CRC_VALUE_SHIFT 0
-
-/***************************************************************************
- *DMA_BBUFF0_RW_STATUS - MCPB Channel x Burst buffer 0 data specific information
- ***************************************************************************/
-/* XPT_MEMDMA_MCPB_CH0 :: DMA_BBUFF0_RW_STATUS :: reserved0 [31:28] */
-#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_BBUFF0_RW_STATUS_reserved0_MASK 0xf0000000
-#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_BBUFF0_RW_STATUS_reserved0_SHIFT 28
-
-/* XPT_MEMDMA_MCPB_CH0 :: DMA_BBUFF0_RW_STATUS :: FIRST_TRANS_AFTER_RUN [27:27] */
-#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_BBUFF0_RW_STATUS_FIRST_TRANS_AFTER_RUN_MASK 0x08000000
-#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_BBUFF0_RW_STATUS_FIRST_TRANS_AFTER_RUN_SHIFT 27
-
-/* XPT_MEMDMA_MCPB_CH0 :: DMA_BBUFF0_RW_STATUS :: RESET_PARSER [26:26] */
-#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_BBUFF0_RW_STATUS_RESET_PARSER_MASK 0x04000000
-#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_BBUFF0_RW_STATUS_RESET_PARSER_SHIFT 26
-
-/* XPT_MEMDMA_MCPB_CH0 :: DMA_BBUFF0_RW_STATUS :: DEPTH [25:16] */
-#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_BBUFF0_RW_STATUS_DEPTH_MASK 0x03ff0000
-#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_BBUFF0_RW_STATUS_DEPTH_SHIFT 16
-
-/* XPT_MEMDMA_MCPB_CH0 :: DMA_BBUFF0_RW_STATUS :: reserved1 [15:11] */
-#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_BBUFF0_RW_STATUS_reserved1_MASK 0x0000f800
-#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_BBUFF0_RW_STATUS_reserved1_SHIFT 11
-
-/* XPT_MEMDMA_MCPB_CH0 :: DMA_BBUFF0_RW_STATUS :: BYTE_EN [10:07] */
-#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_BBUFF0_RW_STATUS_BYTE_EN_MASK 0x00000780
-#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_BBUFF0_RW_STATUS_BYTE_EN_SHIFT 7
-
-/* XPT_MEMDMA_MCPB_CH0 :: DMA_BBUFF0_RW_STATUS :: CURR_READ [06:00] */
-#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_BBUFF0_RW_STATUS_CURR_READ_MASK 0x0000007f
-#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_BBUFF0_RW_STATUS_CURR_READ_SHIFT 0
-
-/***************************************************************************
- *DMA_BBUFF0_RO_STATUS - MCPB Channel x Burst buffer 0 control specific information
- ***************************************************************************/
-/* XPT_MEMDMA_MCPB_CH0 :: DMA_BBUFF0_RO_STATUS :: reserved0 [31:16] */
-#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_BBUFF0_RO_STATUS_reserved0_MASK 0xffff0000
-#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_BBUFF0_RO_STATUS_reserved0_SHIFT 16
-
-/* XPT_MEMDMA_MCPB_CH0 :: DMA_BBUFF0_RO_STATUS :: PAUSE_AT_DESC_END [15:15] */
-#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_BBUFF0_RO_STATUS_PAUSE_AT_DESC_END_MASK 0x00008000
-#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_BBUFF0_RO_STATUS_PAUSE_AT_DESC_END_SHIFT 15
-
-/* XPT_MEMDMA_MCPB_CH0 :: DMA_BBUFF0_RO_STATUS :: PAUSE_AT_DESC_RD [14:14] */
-#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_BBUFF0_RO_STATUS_PAUSE_AT_DESC_RD_MASK 0x00004000
-#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_BBUFF0_RO_STATUS_PAUSE_AT_DESC_RD_SHIFT 14
-
-/* XPT_MEMDMA_MCPB_CH0 :: DMA_BBUFF0_RO_STATUS :: DESC_SLOT_NUM [13:13] */
-#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_BBUFF0_RO_STATUS_DESC_SLOT_NUM_MASK 0x00002000
-#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_BBUFF0_RO_STATUS_DESC_SLOT_NUM_SHIFT 13
-
-/* XPT_MEMDMA_MCPB_CH0 :: DMA_BBUFF0_RO_STATUS :: SECURE_RD [12:05] */
-#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_BBUFF0_RO_STATUS_SECURE_RD_MASK 0x00001fe0
-#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_BBUFF0_RO_STATUS_SECURE_RD_SHIFT 5
-
-/* XPT_MEMDMA_MCPB_CH0 :: DMA_BBUFF0_RO_STATUS :: ZERO_BYTE_TRAN [04:04] */
-#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_BBUFF0_RO_STATUS_ZERO_BYTE_TRAN_MASK 0x00000010
-#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_BBUFF0_RO_STATUS_ZERO_BYTE_TRAN_SHIFT 4
-
-/* XPT_MEMDMA_MCPB_CH0 :: DMA_BBUFF0_RO_STATUS :: LAST_DATA_TRANS [03:03] */
-#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_BBUFF0_RO_STATUS_LAST_DATA_TRANS_MASK 0x00000008
-#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_BBUFF0_RO_STATUS_LAST_DATA_TRANS_SHIFT 3
-
-/* XPT_MEMDMA_MCPB_CH0 :: DMA_BBUFF0_RO_STATUS :: PUSH_RESIDUAL_BYTES [02:02] */
-#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_BBUFF0_RO_STATUS_PUSH_RESIDUAL_BYTES_MASK 0x00000004
-#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_BBUFF0_RO_STATUS_PUSH_RESIDUAL_BYTES_SHIFT 2
-
-/* XPT_MEMDMA_MCPB_CH0 :: DMA_BBUFF0_RO_STATUS :: FORCE_TS_CONFIG [01:01] */
-#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_BBUFF0_RO_STATUS_FORCE_TS_CONFIG_MASK 0x00000002
-#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_BBUFF0_RO_STATUS_FORCE_TS_CONFIG_SHIFT 1
-
-/* XPT_MEMDMA_MCPB_CH0 :: DMA_BBUFF0_RO_STATUS :: IS_ASF_PD_PACKET [00:00] */
-#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_BBUFF0_RO_STATUS_IS_ASF_PD_PACKET_MASK 0x00000001
-#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_BBUFF0_RO_STATUS_IS_ASF_PD_PACKET_SHIFT 0
-
-/***************************************************************************
- *DMA_BBUFF1_RW_STATUS - MCPB Channel x Burst buffer 1 data specific information
- ***************************************************************************/
-/* XPT_MEMDMA_MCPB_CH0 :: DMA_BBUFF1_RW_STATUS :: reserved0 [31:28] */
-#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_BBUFF1_RW_STATUS_reserved0_MASK 0xf0000000
-#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_BBUFF1_RW_STATUS_reserved0_SHIFT 28
-
-/* XPT_MEMDMA_MCPB_CH0 :: DMA_BBUFF1_RW_STATUS :: FIRST_TRANS_AFTER_RUN [27:27] */
-#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_BBUFF1_RW_STATUS_FIRST_TRANS_AFTER_RUN_MASK 0x08000000
-#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_BBUFF1_RW_STATUS_FIRST_TRANS_AFTER_RUN_SHIFT 27
-
-/* XPT_MEMDMA_MCPB_CH0 :: DMA_BBUFF1_RW_STATUS :: RESET_PARSER [26:26] */
-#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_BBUFF1_RW_STATUS_RESET_PARSER_MASK 0x04000000
-#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_BBUFF1_RW_STATUS_RESET_PARSER_SHIFT 26
-
-/* XPT_MEMDMA_MCPB_CH0 :: DMA_BBUFF1_RW_STATUS :: DEPTH [25:16] */
-#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_BBUFF1_RW_STATUS_DEPTH_MASK 0x03ff0000
-#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_BBUFF1_RW_STATUS_DEPTH_SHIFT 16
-
-/* XPT_MEMDMA_MCPB_CH0 :: DMA_BBUFF1_RW_STATUS :: reserved1 [15:11] */
-#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_BBUFF1_RW_STATUS_reserved1_MASK 0x0000f800
-#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_BBUFF1_RW_STATUS_reserved1_SHIFT 11
-
-/* XPT_MEMDMA_MCPB_CH0 :: DMA_BBUFF1_RW_STATUS :: BYTE_EN [10:07] */
-#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_BBUFF1_RW_STATUS_BYTE_EN_MASK 0x00000780
-#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_BBUFF1_RW_STATUS_BYTE_EN_SHIFT 7
-
-/* XPT_MEMDMA_MCPB_CH0 :: DMA_BBUFF1_RW_STATUS :: CURR_READ [06:00] */
-#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_BBUFF1_RW_STATUS_CURR_READ_MASK 0x0000007f
-#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_BBUFF1_RW_STATUS_CURR_READ_SHIFT 0
-
-/***************************************************************************
- *DMA_BBUFF1_RO_STATUS - MCPB Channel x Burst buffer 1 control specific information
- ***************************************************************************/
-/* XPT_MEMDMA_MCPB_CH0 :: DMA_BBUFF1_RO_STATUS :: reserved0 [31:16] */
-#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_BBUFF1_RO_STATUS_reserved0_MASK 0xffff0000
-#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_BBUFF1_RO_STATUS_reserved0_SHIFT 16
-
-/* XPT_MEMDMA_MCPB_CH0 :: DMA_BBUFF1_RO_STATUS :: PAUSE_AT_DESC_END [15:15] */
-#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_BBUFF1_RO_STATUS_PAUSE_AT_DESC_END_MASK 0x00008000
-#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_BBUFF1_RO_STATUS_PAUSE_AT_DESC_END_SHIFT 15
-
-/* XPT_MEMDMA_MCPB_CH0 :: DMA_BBUFF1_RO_STATUS :: PAUSE_AT_DESC_RD [14:14] */
-#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_BBUFF1_RO_STATUS_PAUSE_AT_DESC_RD_MASK 0x00004000
-#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_BBUFF1_RO_STATUS_PAUSE_AT_DESC_RD_SHIFT 14
-
-/* XPT_MEMDMA_MCPB_CH0 :: DMA_BBUFF1_RO_STATUS :: DESC_SLOT_NUM [13:13] */
-#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_BBUFF1_RO_STATUS_DESC_SLOT_NUM_MASK 0x00002000
-#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_BBUFF1_RO_STATUS_DESC_SLOT_NUM_SHIFT 13
-
-/* XPT_MEMDMA_MCPB_CH0 :: DMA_BBUFF1_RO_STATUS :: SECURE_RD [12:05] */
-#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_BBUFF1_RO_STATUS_SECURE_RD_MASK 0x00001fe0
-#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_BBUFF1_RO_STATUS_SECURE_RD_SHIFT 5
-
-/* XPT_MEMDMA_MCPB_CH0 :: DMA_BBUFF1_RO_STATUS :: ZERO_BYTE_TRAN [04:04] */
-#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_BBUFF1_RO_STATUS_ZERO_BYTE_TRAN_MASK 0x00000010
-#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_BBUFF1_RO_STATUS_ZERO_BYTE_TRAN_SHIFT 4
-
-/* XPT_MEMDMA_MCPB_CH0 :: DMA_BBUFF1_RO_STATUS :: LAST_DATA_TRANS [03:03] */
-#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_BBUFF1_RO_STATUS_LAST_DATA_TRANS_MASK 0x00000008
-#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_BBUFF1_RO_STATUS_LAST_DATA_TRANS_SHIFT 3
-
-/* XPT_MEMDMA_MCPB_CH0 :: DMA_BBUFF1_RO_STATUS :: PUSH_RESIDUAL_BYTES [02:02] */
-#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_BBUFF1_RO_STATUS_PUSH_RESIDUAL_BYTES_MASK 0x00000004
-#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_BBUFF1_RO_STATUS_PUSH_RESIDUAL_BYTES_SHIFT 2
-
-/* XPT_MEMDMA_MCPB_CH0 :: DMA_BBUFF1_RO_STATUS :: FORCE_TS_CONFIG [01:01] */
-#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_BBUFF1_RO_STATUS_FORCE_TS_CONFIG_MASK 0x00000002
-#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_BBUFF1_RO_STATUS_FORCE_TS_CONFIG_SHIFT 1
-
-/* XPT_MEMDMA_MCPB_CH0 :: DMA_BBUFF1_RO_STATUS :: IS_ASF_PD_PACKET [00:00] */
-#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_BBUFF1_RO_STATUS_IS_ASF_PD_PACKET_MASK 0x00000001
-#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_BBUFF1_RO_STATUS_IS_ASF_PD_PACKET_SHIFT 0
-
-/***************************************************************************
- *TMEU_BLOCKOUT_CTRL - MCPB Channel x Blockout control information
- ***************************************************************************/
-/* XPT_MEMDMA_MCPB_CH0 :: TMEU_BLOCKOUT_CTRL :: reserved0 [31:31] */
-#define BCHP_XPT_MEMDMA_MCPB_CH0_TMEU_BLOCKOUT_CTRL_reserved0_MASK 0x80000000
-#define BCHP_XPT_MEMDMA_MCPB_CH0_TMEU_BLOCKOUT_CTRL_reserved0_SHIFT 31
-
-/* XPT_MEMDMA_MCPB_CH0 :: TMEU_BLOCKOUT_CTRL :: BO_SPARE_BW_EN [30:30] */
-#define BCHP_XPT_MEMDMA_MCPB_CH0_TMEU_BLOCKOUT_CTRL_BO_SPARE_BW_EN_MASK 0x40000000
-#define BCHP_XPT_MEMDMA_MCPB_CH0_TMEU_BLOCKOUT_CTRL_BO_SPARE_BW_EN_SHIFT 30
-
-/* XPT_MEMDMA_MCPB_CH0 :: TMEU_BLOCKOUT_CTRL :: BO_COUNT [29:00] */
-#define BCHP_XPT_MEMDMA_MCPB_CH0_TMEU_BLOCKOUT_CTRL_BO_COUNT_MASK 0x3fffffff
-#define BCHP_XPT_MEMDMA_MCPB_CH0_TMEU_BLOCKOUT_CTRL_BO_COUNT_SHIFT 0
-
-/***************************************************************************
- *TMEU_NEXT_BO_MON - MCPB Channel x next Blockout monitor information
- ***************************************************************************/
-/* XPT_MEMDMA_MCPB_CH0 :: TMEU_NEXT_BO_MON :: NEXT_BO_MON [31:00] */
-#define BCHP_XPT_MEMDMA_MCPB_CH0_TMEU_NEXT_BO_MON_NEXT_BO_MON_MASK 0xffffffff
-#define BCHP_XPT_MEMDMA_MCPB_CH0_TMEU_NEXT_BO_MON_NEXT_BO_MON_SHIFT 0
-
-/***************************************************************************
- *TMEU_TIMING_CTRL - MCPB Channel x next Blockout monitor information
- ***************************************************************************/
-/* XPT_MEMDMA_MCPB_CH0 :: TMEU_TIMING_CTRL :: reserved0 [31:25] */
-#define BCHP_XPT_MEMDMA_MCPB_CH0_TMEU_TIMING_CTRL_reserved0_MASK 0xfe000000
-#define BCHP_XPT_MEMDMA_MCPB_CH0_TMEU_TIMING_CTRL_reserved0_SHIFT 25
-
-/* XPT_MEMDMA_MCPB_CH0 :: TMEU_TIMING_CTRL :: PACING_PAUSE_EN [24:24] */
-#define BCHP_XPT_MEMDMA_MCPB_CH0_TMEU_TIMING_CTRL_PACING_PAUSE_EN_MASK 0x01000000
-#define BCHP_XPT_MEMDMA_MCPB_CH0_TMEU_TIMING_CTRL_PACING_PAUSE_EN_SHIFT 24
-
-/* XPT_MEMDMA_MCPB_CH0 :: TMEU_TIMING_CTRL :: reserved1 [23:22] */
-#define BCHP_XPT_MEMDMA_MCPB_CH0_TMEU_TIMING_CTRL_reserved1_MASK 0x00c00000
-#define BCHP_XPT_MEMDMA_MCPB_CH0_TMEU_TIMING_CTRL_reserved1_SHIFT 22
-
-/* XPT_MEMDMA_MCPB_CH0 :: TMEU_TIMING_CTRL :: PACING_RESTART [21:21] */
-#define BCHP_XPT_MEMDMA_MCPB_CH0_TMEU_TIMING_CTRL_PACING_RESTART_MASK 0x00200000
-#define BCHP_XPT_MEMDMA_MCPB_CH0_TMEU_TIMING_CTRL_PACING_RESTART_SHIFT 21
-
-/* XPT_MEMDMA_MCPB_CH0 :: TMEU_TIMING_CTRL :: PACING_AUTOSTART_ON_ERROR_EN [20:20] */
-#define BCHP_XPT_MEMDMA_MCPB_CH0_TMEU_TIMING_CTRL_PACING_AUTOSTART_ON_ERROR_EN_MASK 0x00100000
-#define BCHP_XPT_MEMDMA_MCPB_CH0_TMEU_TIMING_CTRL_PACING_AUTOSTART_ON_ERROR_EN_SHIFT 20
-
-/* XPT_MEMDMA_MCPB_CH0 :: TMEU_TIMING_CTRL :: PACING_AUTOSTART_ON_FORCE_RESYNC_EN [19:19] */
-#define BCHP_XPT_MEMDMA_MCPB_CH0_TMEU_TIMING_CTRL_PACING_AUTOSTART_ON_FORCE_RESYNC_EN_MASK 0x00080000
-#define BCHP_XPT_MEMDMA_MCPB_CH0_TMEU_TIMING_CTRL_PACING_AUTOSTART_ON_FORCE_RESYNC_EN_SHIFT 19
-
-/* XPT_MEMDMA_MCPB_CH0 :: TMEU_TIMING_CTRL :: PACING_TYPE [18:17] */
-#define BCHP_XPT_MEMDMA_MCPB_CH0_TMEU_TIMING_CTRL_PACING_TYPE_MASK 0x00060000
-#define BCHP_XPT_MEMDMA_MCPB_CH0_TMEU_TIMING_CTRL_PACING_TYPE_SHIFT 17
-
-/* XPT_MEMDMA_MCPB_CH0 :: TMEU_TIMING_CTRL :: PACING_EN [16:16] */
-#define BCHP_XPT_MEMDMA_MCPB_CH0_TMEU_TIMING_CTRL_PACING_EN_MASK 0x00010000
-#define BCHP_XPT_MEMDMA_MCPB_CH0_TMEU_TIMING_CTRL_PACING_EN_SHIFT 16
-
-/* XPT_MEMDMA_MCPB_CH0 :: TMEU_TIMING_CTRL :: reserved2 [15:09] */
-#define BCHP_XPT_MEMDMA_MCPB_CH0_TMEU_TIMING_CTRL_reserved2_MASK 0x0000fe00
-#define BCHP_XPT_MEMDMA_MCPB_CH0_TMEU_TIMING_CTRL_reserved2_SHIFT 9
-
-/* XPT_MEMDMA_MCPB_CH0 :: TMEU_TIMING_CTRL :: GPC_SELECT [08:04] */
-#define BCHP_XPT_MEMDMA_MCPB_CH0_TMEU_TIMING_CTRL_GPC_SELECT_MASK 0x000001f0
-#define BCHP_XPT_MEMDMA_MCPB_CH0_TMEU_TIMING_CTRL_GPC_SELECT_SHIFT 4
-
-/* XPT_MEMDMA_MCPB_CH0 :: TMEU_TIMING_CTRL :: RE_TIMESTAMP_EN [03:03] */
-#define BCHP_XPT_MEMDMA_MCPB_CH0_TMEU_TIMING_CTRL_RE_TIMESTAMP_EN_MASK 0x00000008
-#define BCHP_XPT_MEMDMA_MCPB_CH0_TMEU_TIMING_CTRL_RE_TIMESTAMP_EN_SHIFT 3
-
-/* XPT_MEMDMA_MCPB_CH0 :: TMEU_TIMING_CTRL :: OUTPUT_ATS_MODE [02:02] */
-#define BCHP_XPT_MEMDMA_MCPB_CH0_TMEU_TIMING_CTRL_OUTPUT_ATS_MODE_MASK 0x00000004
-#define BCHP_XPT_MEMDMA_MCPB_CH0_TMEU_TIMING_CTRL_OUTPUT_ATS_MODE_SHIFT 2
-
-/* XPT_MEMDMA_MCPB_CH0 :: TMEU_TIMING_CTRL :: INPUT_ATS_FORMAT [01:00] */
-#define BCHP_XPT_MEMDMA_MCPB_CH0_TMEU_TIMING_CTRL_INPUT_ATS_FORMAT_MASK 0x00000003
-#define BCHP_XPT_MEMDMA_MCPB_CH0_TMEU_TIMING_CTRL_INPUT_ATS_FORMAT_SHIFT 0
-
-/***************************************************************************
- *TMEU_REF_DIFF_VALUE_TS_MBOX - MCPB Channel x reference difference value and next Timestamp information
- ***************************************************************************/
-/* XPT_MEMDMA_MCPB_CH0 :: TMEU_REF_DIFF_VALUE_TS_MBOX :: REF_DIFF_VALUE_TS_MBOX [31:00] */
-#define BCHP_XPT_MEMDMA_MCPB_CH0_TMEU_REF_DIFF_VALUE_TS_MBOX_REF_DIFF_VALUE_TS_MBOX_MASK 0xffffffff
-#define BCHP_XPT_MEMDMA_MCPB_CH0_TMEU_REF_DIFF_VALUE_TS_MBOX_REF_DIFF_VALUE_TS_MBOX_SHIFT 0
-
-/***************************************************************************
- *TMEU_TS_ERR_BOUND_EARLY - MCPB Channel x TS error bound early information
- ***************************************************************************/
-/* XPT_MEMDMA_MCPB_CH0 :: TMEU_TS_ERR_BOUND_EARLY :: reserved0 [31:23] */
-#define BCHP_XPT_MEMDMA_MCPB_CH0_TMEU_TS_ERR_BOUND_EARLY_reserved0_MASK 0xff800000
-#define BCHP_XPT_MEMDMA_MCPB_CH0_TMEU_TS_ERR_BOUND_EARLY_reserved0_SHIFT 23
-
-/* XPT_MEMDMA_MCPB_CH0 :: TMEU_TS_ERR_BOUND_EARLY :: TS_ERROR_BOUND [22:00] */
-#define BCHP_XPT_MEMDMA_MCPB_CH0_TMEU_TS_ERR_BOUND_EARLY_TS_ERROR_BOUND_MASK 0x007fffff
-#define BCHP_XPT_MEMDMA_MCPB_CH0_TMEU_TS_ERR_BOUND_EARLY_TS_ERROR_BOUND_SHIFT 0
-
-/***************************************************************************
- *TMEU_TS_ERR_BOUND_LATE - MCPB Channel x TS error bound late information
- ***************************************************************************/
-/* XPT_MEMDMA_MCPB_CH0 :: TMEU_TS_ERR_BOUND_LATE :: reserved0 [31:23] */
-#define BCHP_XPT_MEMDMA_MCPB_CH0_TMEU_TS_ERR_BOUND_LATE_reserved0_MASK 0xff800000
-#define BCHP_XPT_MEMDMA_MCPB_CH0_TMEU_TS_ERR_BOUND_LATE_reserved0_SHIFT 23
-
-/* XPT_MEMDMA_MCPB_CH0 :: TMEU_TS_ERR_BOUND_LATE :: TS_ERROR_BOUND [22:00] */
-#define BCHP_XPT_MEMDMA_MCPB_CH0_TMEU_TS_ERR_BOUND_LATE_TS_ERROR_BOUND_MASK 0x007fffff
-#define BCHP_XPT_MEMDMA_MCPB_CH0_TMEU_TS_ERR_BOUND_LATE_TS_ERROR_BOUND_SHIFT 0
-
-/***************************************************************************
- *TMEU_NEXT_GPC_MON - MCPB Channel x next Global Pacing Counter and Timestamp monitor information
- ***************************************************************************/
-/* XPT_MEMDMA_MCPB_CH0 :: TMEU_NEXT_GPC_MON :: NEXT_GPC_MON [31:00] */
-#define BCHP_XPT_MEMDMA_MCPB_CH0_TMEU_NEXT_GPC_MON_NEXT_GPC_MON_MASK 0xffffffff
-#define BCHP_XPT_MEMDMA_MCPB_CH0_TMEU_NEXT_GPC_MON_NEXT_GPC_MON_SHIFT 0
-
-/***************************************************************************
- *TMEU_REF_DIFF_VALUE_SIGN - MCPB Channel x reference difference value sign information
- ***************************************************************************/
-/* XPT_MEMDMA_MCPB_CH0 :: TMEU_REF_DIFF_VALUE_SIGN :: reserved0 [31:14] */
-#define BCHP_XPT_MEMDMA_MCPB_CH0_TMEU_REF_DIFF_VALUE_SIGN_reserved0_MASK 0xffffc000
-#define BCHP_XPT_MEMDMA_MCPB_CH0_TMEU_REF_DIFF_VALUE_SIGN_reserved0_SHIFT 14
-
-/* XPT_MEMDMA_MCPB_CH0 :: TMEU_REF_DIFF_VALUE_SIGN :: LAST_NEXT_TS_VAL [13:13] */
-#define BCHP_XPT_MEMDMA_MCPB_CH0_TMEU_REF_DIFF_VALUE_SIGN_LAST_NEXT_TS_VAL_MASK 0x00002000
-#define BCHP_XPT_MEMDMA_MCPB_CH0_TMEU_REF_DIFF_VALUE_SIGN_LAST_NEXT_TS_VAL_SHIFT 13
-
-/* XPT_MEMDMA_MCPB_CH0 :: TMEU_REF_DIFF_VALUE_SIGN :: LAST_TS_DEL_VAL [12:12] */
-#define BCHP_XPT_MEMDMA_MCPB_CH0_TMEU_REF_DIFF_VALUE_SIGN_LAST_TS_DEL_VAL_MASK 0x00001000
-#define BCHP_XPT_MEMDMA_MCPB_CH0_TMEU_REF_DIFF_VALUE_SIGN_LAST_TS_DEL_VAL_SHIFT 12
-
-/* XPT_MEMDMA_MCPB_CH0 :: TMEU_REF_DIFF_VALUE_SIGN :: GPC_MON_NEXT_TS [11:11] */
-#define BCHP_XPT_MEMDMA_MCPB_CH0_TMEU_REF_DIFF_VALUE_SIGN_GPC_MON_NEXT_TS_MASK 0x00000800
-#define BCHP_XPT_MEMDMA_MCPB_CH0_TMEU_REF_DIFF_VALUE_SIGN_GPC_MON_NEXT_TS_SHIFT 11
-
-/* XPT_MEMDMA_MCPB_CH0 :: TMEU_REF_DIFF_VALUE_SIGN :: GPC_MON_TS_DEL [10:10] */
-#define BCHP_XPT_MEMDMA_MCPB_CH0_TMEU_REF_DIFF_VALUE_SIGN_GPC_MON_TS_DEL_MASK 0x00000400
-#define BCHP_XPT_MEMDMA_MCPB_CH0_TMEU_REF_DIFF_VALUE_SIGN_GPC_MON_TS_DEL_SHIFT 10
-
-/* XPT_MEMDMA_MCPB_CH0 :: TMEU_REF_DIFF_VALUE_SIGN :: GPC_MBOX_NEXT_TS [09:09] */
-#define BCHP_XPT_MEMDMA_MCPB_CH0_TMEU_REF_DIFF_VALUE_SIGN_GPC_MBOX_NEXT_TS_MASK 0x00000200
-#define BCHP_XPT_MEMDMA_MCPB_CH0_TMEU_REF_DIFF_VALUE_SIGN_GPC_MBOX_NEXT_TS_SHIFT 9
-
-/* XPT_MEMDMA_MCPB_CH0 :: TMEU_REF_DIFF_VALUE_SIGN :: GPC_MBOX_TS_DEL [08:08] */
-#define BCHP_XPT_MEMDMA_MCPB_CH0_TMEU_REF_DIFF_VALUE_SIGN_GPC_MBOX_TS_DEL_MASK 0x00000100
-#define BCHP_XPT_MEMDMA_MCPB_CH0_TMEU_REF_DIFF_VALUE_SIGN_GPC_MBOX_TS_DEL_SHIFT 8
-
-/* XPT_MEMDMA_MCPB_CH0 :: TMEU_REF_DIFF_VALUE_SIGN :: GPC_MS2_BITS [07:06] */
-#define BCHP_XPT_MEMDMA_MCPB_CH0_TMEU_REF_DIFF_VALUE_SIGN_GPC_MS2_BITS_MASK 0x000000c0
-#define BCHP_XPT_MEMDMA_MCPB_CH0_TMEU_REF_DIFF_VALUE_SIGN_GPC_MS2_BITS_SHIFT 6
-
-/* XPT_MEMDMA_MCPB_CH0 :: TMEU_REF_DIFF_VALUE_SIGN :: PCR_TS_MS2_BITS [05:04] */
-#define BCHP_XPT_MEMDMA_MCPB_CH0_TMEU_REF_DIFF_VALUE_SIGN_PCR_TS_MS2_BITS_MASK 0x00000030
-#define BCHP_XPT_MEMDMA_MCPB_CH0_TMEU_REF_DIFF_VALUE_SIGN_PCR_TS_MS2_BITS_SHIFT 4
-
-/* XPT_MEMDMA_MCPB_CH0 :: TMEU_REF_DIFF_VALUE_SIGN :: MSB_REF_DIFF_VALUE_SIGN [03:00] */
-#define BCHP_XPT_MEMDMA_MCPB_CH0_TMEU_REF_DIFF_VALUE_SIGN_MSB_REF_DIFF_VALUE_SIGN_MASK 0x0000000f
-#define BCHP_XPT_MEMDMA_MCPB_CH0_TMEU_REF_DIFF_VALUE_SIGN_MSB_REF_DIFF_VALUE_SIGN_SHIFT 0
-
-/***************************************************************************
- *TMEU_PES_PACING_CTRL - MCPB Channel x PES pacing control information
- ***************************************************************************/
-/* XPT_MEMDMA_MCPB_CH0 :: TMEU_PES_PACING_CTRL :: reserved0 [31:25] */
-#define BCHP_XPT_MEMDMA_MCPB_CH0_TMEU_PES_PACING_CTRL_reserved0_MASK 0xfe000000
-#define BCHP_XPT_MEMDMA_MCPB_CH0_TMEU_PES_PACING_CTRL_reserved0_SHIFT 25
-
-/* XPT_MEMDMA_MCPB_CH0 :: TMEU_PES_PACING_CTRL :: NEXT_PACKET_TIMESTAMP_ERROR_CHECK_EN [24:24] */
-#define BCHP_XPT_MEMDMA_MCPB_CH0_TMEU_PES_PACING_CTRL_NEXT_PACKET_TIMESTAMP_ERROR_CHECK_EN_MASK 0x01000000
-#define BCHP_XPT_MEMDMA_MCPB_CH0_TMEU_PES_PACING_CTRL_NEXT_PACKET_TIMESTAMP_ERROR_CHECK_EN_SHIFT 24
-
-/* XPT_MEMDMA_MCPB_CH0 :: TMEU_PES_PACING_CTRL :: reserved1 [23:23] */
-#define BCHP_XPT_MEMDMA_MCPB_CH0_TMEU_PES_PACING_CTRL_reserved1_MASK 0x00800000
-#define BCHP_XPT_MEMDMA_MCPB_CH0_TMEU_PES_PACING_CTRL_reserved1_SHIFT 23
-
-/* XPT_MEMDMA_MCPB_CH0 :: TMEU_PES_PACING_CTRL :: NEXT_PACKET_TIMESTAMP_ERROR_BOUND [22:00] */
-#define BCHP_XPT_MEMDMA_MCPB_CH0_TMEU_PES_PACING_CTRL_NEXT_PACKET_TIMESTAMP_ERROR_BOUND_MASK 0x007fffff
-#define BCHP_XPT_MEMDMA_MCPB_CH0_TMEU_PES_PACING_CTRL_NEXT_PACKET_TIMESTAMP_ERROR_BOUND_SHIFT 0
-
-/***************************************************************************
- *TMEU_SLOT_STATUS - MCPB Channel x Slot 0 and Slot 1 information
- ***************************************************************************/
-/* XPT_MEMDMA_MCPB_CH0 :: TMEU_SLOT_STATUS :: reserved0 [31:26] */
-#define BCHP_XPT_MEMDMA_MCPB_CH0_TMEU_SLOT_STATUS_reserved0_MASK 0xfc000000
-#define BCHP_XPT_MEMDMA_MCPB_CH0_TMEU_SLOT_STATUS_reserved0_SHIFT 26
-
-/* XPT_MEMDMA_MCPB_CH0 :: TMEU_SLOT_STATUS :: PARITY_ERROR_1 [25:25] */
-#define BCHP_XPT_MEMDMA_MCPB_CH0_TMEU_SLOT_STATUS_PARITY_ERROR_1_MASK 0x02000000
-#define BCHP_XPT_MEMDMA_MCPB_CH0_TMEU_SLOT_STATUS_PARITY_ERROR_1_SHIFT 25
-
-/* XPT_MEMDMA_MCPB_CH0 :: TMEU_SLOT_STATUS :: MARKED_DISCON_IND_1 [24:24] */
-#define BCHP_XPT_MEMDMA_MCPB_CH0_TMEU_SLOT_STATUS_MARKED_DISCON_IND_1_MASK 0x01000000
-#define BCHP_XPT_MEMDMA_MCPB_CH0_TMEU_SLOT_STATUS_MARKED_DISCON_IND_1_SHIFT 24
-
-/* XPT_MEMDMA_MCPB_CH0 :: TMEU_SLOT_STATUS :: PKT2PKT_TIMESTAMP_DELTA_VALID_1 [23:23] */
-#define BCHP_XPT_MEMDMA_MCPB_CH0_TMEU_SLOT_STATUS_PKT2PKT_TIMESTAMP_DELTA_VALID_1_MASK 0x00800000
-#define BCHP_XPT_MEMDMA_MCPB_CH0_TMEU_SLOT_STATUS_PKT2PKT_TIMESTAMP_DELTA_VALID_1_SHIFT 23
-
-/* XPT_MEMDMA_MCPB_CH0 :: TMEU_SLOT_STATUS :: NEXT_TIMESTAMP_VALID_1 [22:22] */
-#define BCHP_XPT_MEMDMA_MCPB_CH0_TMEU_SLOT_STATUS_NEXT_TIMESTAMP_VALID_1_MASK 0x00400000
-#define BCHP_XPT_MEMDMA_MCPB_CH0_TMEU_SLOT_STATUS_NEXT_TIMESTAMP_VALID_1_SHIFT 22
-
-/* XPT_MEMDMA_MCPB_CH0 :: TMEU_SLOT_STATUS :: PCR_FORCE_RESYNC_1 [21:21] */
-#define BCHP_XPT_MEMDMA_MCPB_CH0_TMEU_SLOT_STATUS_PCR_FORCE_RESYNC_1_MASK 0x00200000
-#define BCHP_XPT_MEMDMA_MCPB_CH0_TMEU_SLOT_STATUS_PCR_FORCE_RESYNC_1_SHIFT 21
-
-/* XPT_MEMDMA_MCPB_CH0 :: TMEU_SLOT_STATUS :: PCR_FIRST_PKT_AFTER_RUN_1 [20:20] */
-#define BCHP_XPT_MEMDMA_MCPB_CH0_TMEU_SLOT_STATUS_PCR_FIRST_PKT_AFTER_RUN_1_MASK 0x00100000
-#define BCHP_XPT_MEMDMA_MCPB_CH0_TMEU_SLOT_STATUS_PCR_FIRST_PKT_AFTER_RUN_1_SHIFT 20
-
-/* XPT_MEMDMA_MCPB_CH0 :: TMEU_SLOT_STATUS :: FORCE_RESYNC_1 [19:19] */
-#define BCHP_XPT_MEMDMA_MCPB_CH0_TMEU_SLOT_STATUS_FORCE_RESYNC_1_MASK 0x00080000
-#define BCHP_XPT_MEMDMA_MCPB_CH0_TMEU_SLOT_STATUS_FORCE_RESYNC_1_SHIFT 19
-
-/* XPT_MEMDMA_MCPB_CH0 :: TMEU_SLOT_STATUS :: FIRST_PKT_AFTER_RUN_1 [18:18] */
-#define BCHP_XPT_MEMDMA_MCPB_CH0_TMEU_SLOT_STATUS_FIRST_PKT_AFTER_RUN_1_MASK 0x00040000
-#define BCHP_XPT_MEMDMA_MCPB_CH0_TMEU_SLOT_STATUS_FIRST_PKT_AFTER_RUN_1_SHIFT 18
-
-/* XPT_MEMDMA_MCPB_CH0 :: TMEU_SLOT_STATUS :: PCR_VALID_1 [17:17] */
-#define BCHP_XPT_MEMDMA_MCPB_CH0_TMEU_SLOT_STATUS_PCR_VALID_1_MASK 0x00020000
-#define BCHP_XPT_MEMDMA_MCPB_CH0_TMEU_SLOT_STATUS_PCR_VALID_1_SHIFT 17
-
-/* XPT_MEMDMA_MCPB_CH0 :: TMEU_SLOT_STATUS :: TIMESTAMP_VALID_1 [16:16] */
-#define BCHP_XPT_MEMDMA_MCPB_CH0_TMEU_SLOT_STATUS_TIMESTAMP_VALID_1_MASK 0x00010000
-#define BCHP_XPT_MEMDMA_MCPB_CH0_TMEU_SLOT_STATUS_TIMESTAMP_VALID_1_SHIFT 16
-
-/* XPT_MEMDMA_MCPB_CH0 :: TMEU_SLOT_STATUS :: reserved1 [15:10] */
-#define BCHP_XPT_MEMDMA_MCPB_CH0_TMEU_SLOT_STATUS_reserved1_MASK 0x0000fc00
-#define BCHP_XPT_MEMDMA_MCPB_CH0_TMEU_SLOT_STATUS_reserved1_SHIFT 10
-
-/* XPT_MEMDMA_MCPB_CH0 :: TMEU_SLOT_STATUS :: PARITY_ERROR_0 [09:09] */
-#define BCHP_XPT_MEMDMA_MCPB_CH0_TMEU_SLOT_STATUS_PARITY_ERROR_0_MASK 0x00000200
-#define BCHP_XPT_MEMDMA_MCPB_CH0_TMEU_SLOT_STATUS_PARITY_ERROR_0_SHIFT 9
-
-/* XPT_MEMDMA_MCPB_CH0 :: TMEU_SLOT_STATUS :: MARKED_DISCON_IND_0 [08:08] */
-#define BCHP_XPT_MEMDMA_MCPB_CH0_TMEU_SLOT_STATUS_MARKED_DISCON_IND_0_MASK 0x00000100
-#define BCHP_XPT_MEMDMA_MCPB_CH0_TMEU_SLOT_STATUS_MARKED_DISCON_IND_0_SHIFT 8
-
-/* XPT_MEMDMA_MCPB_CH0 :: TMEU_SLOT_STATUS :: PKT2PKT_TIMESTAMP_DELTA_VALID_0 [07:07] */
-#define BCHP_XPT_MEMDMA_MCPB_CH0_TMEU_SLOT_STATUS_PKT2PKT_TIMESTAMP_DELTA_VALID_0_MASK 0x00000080
-#define BCHP_XPT_MEMDMA_MCPB_CH0_TMEU_SLOT_STATUS_PKT2PKT_TIMESTAMP_DELTA_VALID_0_SHIFT 7
-
-/* XPT_MEMDMA_MCPB_CH0 :: TMEU_SLOT_STATUS :: NEXT_TIMESTAMP_VALID_0 [06:06] */
-#define BCHP_XPT_MEMDMA_MCPB_CH0_TMEU_SLOT_STATUS_NEXT_TIMESTAMP_VALID_0_MASK 0x00000040
-#define BCHP_XPT_MEMDMA_MCPB_CH0_TMEU_SLOT_STATUS_NEXT_TIMESTAMP_VALID_0_SHIFT 6
-
-/* XPT_MEMDMA_MCPB_CH0 :: TMEU_SLOT_STATUS :: PCR_FORCE_RESYNC_0 [05:05] */
-#define BCHP_XPT_MEMDMA_MCPB_CH0_TMEU_SLOT_STATUS_PCR_FORCE_RESYNC_0_MASK 0x00000020
-#define BCHP_XPT_MEMDMA_MCPB_CH0_TMEU_SLOT_STATUS_PCR_FORCE_RESYNC_0_SHIFT 5
-
-/* XPT_MEMDMA_MCPB_CH0 :: TMEU_SLOT_STATUS :: PCR_FIRST_PKT_AFTER_RUN_0 [04:04] */
-#define BCHP_XPT_MEMDMA_MCPB_CH0_TMEU_SLOT_STATUS_PCR_FIRST_PKT_AFTER_RUN_0_MASK 0x00000010
-#define BCHP_XPT_MEMDMA_MCPB_CH0_TMEU_SLOT_STATUS_PCR_FIRST_PKT_AFTER_RUN_0_SHIFT 4
-
-/* XPT_MEMDMA_MCPB_CH0 :: TMEU_SLOT_STATUS :: FORCE_RESYNC_0 [03:03] */
-#define BCHP_XPT_MEMDMA_MCPB_CH0_TMEU_SLOT_STATUS_FORCE_RESYNC_0_MASK 0x00000008
-#define BCHP_XPT_MEMDMA_MCPB_CH0_TMEU_SLOT_STATUS_FORCE_RESYNC_0_SHIFT 3
-
-/* XPT_MEMDMA_MCPB_CH0 :: TMEU_SLOT_STATUS :: FIRST_PKT_AFTER_RUN_0 [02:02] */
-#define BCHP_XPT_MEMDMA_MCPB_CH0_TMEU_SLOT_STATUS_FIRST_PKT_AFTER_RUN_0_MASK 0x00000004
-#define BCHP_XPT_MEMDMA_MCPB_CH0_TMEU_SLOT_STATUS_FIRST_PKT_AFTER_RUN_0_SHIFT 2
-
-/* XPT_MEMDMA_MCPB_CH0 :: TMEU_SLOT_STATUS :: PCR_VALID_0 [01:01] */
-#define BCHP_XPT_MEMDMA_MCPB_CH0_TMEU_SLOT_STATUS_PCR_VALID_0_MASK 0x00000002
-#define BCHP_XPT_MEMDMA_MCPB_CH0_TMEU_SLOT_STATUS_PCR_VALID_0_SHIFT 1
-
-/* XPT_MEMDMA_MCPB_CH0 :: TMEU_SLOT_STATUS :: TIMESTAMP_VALID_0 [00:00] */
-#define BCHP_XPT_MEMDMA_MCPB_CH0_TMEU_SLOT_STATUS_TIMESTAMP_VALID_0_MASK 0x00000001
-#define BCHP_XPT_MEMDMA_MCPB_CH0_TMEU_SLOT_STATUS_TIMESTAMP_VALID_0_SHIFT 0
-
-/***************************************************************************
- *TMEU_TIMING_INFO_SLOT0_REG1 - MCPB Channel x timing information for Slot 0
- ***************************************************************************/
-/* XPT_MEMDMA_MCPB_CH0 :: TMEU_TIMING_INFO_SLOT0_REG1 :: TIMESTAMP_OR_NEXT_TS_0 [31:00] */
-#define BCHP_XPT_MEMDMA_MCPB_CH0_TMEU_TIMING_INFO_SLOT0_REG1_TIMESTAMP_OR_NEXT_TS_0_MASK 0xffffffff
-#define BCHP_XPT_MEMDMA_MCPB_CH0_TMEU_TIMING_INFO_SLOT0_REG1_TIMESTAMP_OR_NEXT_TS_0_SHIFT 0
-
-/***************************************************************************
- *TMEU_TIMING_INFO_SLOT0_REG2 - MCPB Channel x timing information for Slot 0
- ***************************************************************************/
-/* XPT_MEMDMA_MCPB_CH0 :: TMEU_TIMING_INFO_SLOT0_REG2 :: PCR_OR_TS_DELTA_0 [31:00] */
-#define BCHP_XPT_MEMDMA_MCPB_CH0_TMEU_TIMING_INFO_SLOT0_REG2_PCR_OR_TS_DELTA_0_MASK 0xffffffff
-#define BCHP_XPT_MEMDMA_MCPB_CH0_TMEU_TIMING_INFO_SLOT0_REG2_PCR_OR_TS_DELTA_0_SHIFT 0
-
-/***************************************************************************
- *TMEU_TIMING_INFO_SLOT1_REG1 - MCPB Channel x timing information for Slot 1
- ***************************************************************************/
-/* XPT_MEMDMA_MCPB_CH0 :: TMEU_TIMING_INFO_SLOT1_REG1 :: TIMESTAMP_OR_NEXT_TS_1 [31:00] */
-#define BCHP_XPT_MEMDMA_MCPB_CH0_TMEU_TIMING_INFO_SLOT1_REG1_TIMESTAMP_OR_NEXT_TS_1_MASK 0xffffffff
-#define BCHP_XPT_MEMDMA_MCPB_CH0_TMEU_TIMING_INFO_SLOT1_REG1_TIMESTAMP_OR_NEXT_TS_1_SHIFT 0
-
-/***************************************************************************
- *TMEU_TIMING_INFO_SLOT1_REG2 - MCPB Channel x timing information for Slot 1
- ***************************************************************************/
-/* XPT_MEMDMA_MCPB_CH0 :: TMEU_TIMING_INFO_SLOT1_REG2 :: PCR_OR_TS_DELTA_1 [31:00] */
-#define BCHP_XPT_MEMDMA_MCPB_CH0_TMEU_TIMING_INFO_SLOT1_REG2_PCR_OR_TS_DELTA_1_MASK 0xffffffff
-#define BCHP_XPT_MEMDMA_MCPB_CH0_TMEU_TIMING_INFO_SLOT1_REG2_PCR_OR_TS_DELTA_1_SHIFT 0
-
-/***************************************************************************
- *TMEU_TIMING_INFO_LAST_TIMESTAMP_DELTA - MCPB Channel x last TS delta value
- ***************************************************************************/
-/* XPT_MEMDMA_MCPB_CH0 :: TMEU_TIMING_INFO_LAST_TIMESTAMP_DELTA :: LAST_TIMESTAMP_DELTA [31:00] */
-#define BCHP_XPT_MEMDMA_MCPB_CH0_TMEU_TIMING_INFO_LAST_TIMESTAMP_DELTA_LAST_TIMESTAMP_DELTA_MASK 0xffffffff
-#define BCHP_XPT_MEMDMA_MCPB_CH0_TMEU_TIMING_INFO_LAST_TIMESTAMP_DELTA_LAST_TIMESTAMP_DELTA_SHIFT 0
-
-/***************************************************************************
- *TMEU_TIMING_INFO_LAST_NEXT_TIMESTAMP - MCPB Channel x last NEXT TS value
- ***************************************************************************/
-/* XPT_MEMDMA_MCPB_CH0 :: TMEU_TIMING_INFO_LAST_NEXT_TIMESTAMP :: LAST_NEXT_TIMESTAMP [31:00] */
-#define BCHP_XPT_MEMDMA_MCPB_CH0_TMEU_TIMING_INFO_LAST_NEXT_TIMESTAMP_LAST_NEXT_TIMESTAMP_MASK 0xffffffff
-#define BCHP_XPT_MEMDMA_MCPB_CH0_TMEU_TIMING_INFO_LAST_NEXT_TIMESTAMP_LAST_NEXT_TIMESTAMP_SHIFT 0
-
-/***************************************************************************
- *DCPM_STATUS - MCPB Channel x DCPM status information
- ***************************************************************************/
-/* XPT_MEMDMA_MCPB_CH0 :: DCPM_STATUS :: reserved0 [31:03] */
-#define BCHP_XPT_MEMDMA_MCPB_CH0_DCPM_STATUS_reserved0_MASK 0xfffffff8
-#define BCHP_XPT_MEMDMA_MCPB_CH0_DCPM_STATUS_reserved0_SHIFT 3
-
-/* XPT_MEMDMA_MCPB_CH0 :: DCPM_STATUS :: DESC_ADDRESS_STATUS [02:02] */
-#define BCHP_XPT_MEMDMA_MCPB_CH0_DCPM_STATUS_DESC_ADDRESS_STATUS_MASK 0x00000004
-#define BCHP_XPT_MEMDMA_MCPB_CH0_DCPM_STATUS_DESC_ADDRESS_STATUS_SHIFT 2
-
-/* XPT_MEMDMA_MCPB_CH0 :: DCPM_STATUS :: DESC_DONE_INT_ADDRESS_STATUS [01:01] */
-#define BCHP_XPT_MEMDMA_MCPB_CH0_DCPM_STATUS_DESC_DONE_INT_ADDRESS_STATUS_MASK 0x00000002
-#define BCHP_XPT_MEMDMA_MCPB_CH0_DCPM_STATUS_DESC_DONE_INT_ADDRESS_STATUS_SHIFT 1
-
-/* XPT_MEMDMA_MCPB_CH0 :: DCPM_STATUS :: DATA_ADDR_CUR_DESC_ADDR_STATUS [00:00] */
-#define BCHP_XPT_MEMDMA_MCPB_CH0_DCPM_STATUS_DATA_ADDR_CUR_DESC_ADDR_STATUS_MASK 0x00000001
-#define BCHP_XPT_MEMDMA_MCPB_CH0_DCPM_STATUS_DATA_ADDR_CUR_DESC_ADDR_STATUS_SHIFT 0
-
-/***************************************************************************
- *DCPM_DESC_ADDR - MCPB Channel x DCPM descriptor address information
- ***************************************************************************/
-/* XPT_MEMDMA_MCPB_CH0 :: DCPM_DESC_ADDR :: DESC_ADDRESS [31:04] */
-#define BCHP_XPT_MEMDMA_MCPB_CH0_DCPM_DESC_ADDR_DESC_ADDRESS_MASK 0xfffffff0
-#define BCHP_XPT_MEMDMA_MCPB_CH0_DCPM_DESC_ADDR_DESC_ADDRESS_SHIFT 4
-
-/* XPT_MEMDMA_MCPB_CH0 :: DCPM_DESC_ADDR :: DESC_ID [03:00] */
-#define BCHP_XPT_MEMDMA_MCPB_CH0_DCPM_DESC_ADDR_DESC_ID_MASK 0x0000000f
-#define BCHP_XPT_MEMDMA_MCPB_CH0_DCPM_DESC_ADDR_DESC_ID_SHIFT 0
-
-/***************************************************************************
- *DCPM_DESC_DONE_INT_ADDR - MCPB Channel x DCPM descriptor done interrupt address information
- ***************************************************************************/
-/* XPT_MEMDMA_MCPB_CH0 :: DCPM_DESC_DONE_INT_ADDR :: DESC_DONE_INT_ADDRESS [31:04] */
-#define BCHP_XPT_MEMDMA_MCPB_CH0_DCPM_DESC_DONE_INT_ADDR_DESC_DONE_INT_ADDRESS_MASK 0xfffffff0
-#define BCHP_XPT_MEMDMA_MCPB_CH0_DCPM_DESC_DONE_INT_ADDR_DESC_DONE_INT_ADDRESS_SHIFT 4
-
-/* XPT_MEMDMA_MCPB_CH0 :: DCPM_DESC_DONE_INT_ADDR :: DESC_DONE_INT_ID [03:00] */
-#define BCHP_XPT_MEMDMA_MCPB_CH0_DCPM_DESC_DONE_INT_ADDR_DESC_DONE_INT_ID_MASK 0x0000000f
-#define BCHP_XPT_MEMDMA_MCPB_CH0_DCPM_DESC_DONE_INT_ADDR_DESC_DONE_INT_ID_SHIFT 0
-
-/***************************************************************************
- *DCPM_PAUSE_AFTER_GROUP_PACKETS_CTRL - MCPB Channel x Pause after group of packets control information
- ***************************************************************************/
-/* XPT_MEMDMA_MCPB_CH0 :: DCPM_PAUSE_AFTER_GROUP_PACKETS_CTRL :: PAUSE_AFTER_PACKET_COUNT [31:16] */
-#define BCHP_XPT_MEMDMA_MCPB_CH0_DCPM_PAUSE_AFTER_GROUP_PACKETS_CTRL_PAUSE_AFTER_PACKET_COUNT_MASK 0xffff0000
-#define BCHP_XPT_MEMDMA_MCPB_CH0_DCPM_PAUSE_AFTER_GROUP_PACKETS_CTRL_PAUSE_AFTER_PACKET_COUNT_SHIFT 16
-
-/* XPT_MEMDMA_MCPB_CH0 :: DCPM_PAUSE_AFTER_GROUP_PACKETS_CTRL :: BTP_PACKET_GROUP_ID [15:08] */
-#define BCHP_XPT_MEMDMA_MCPB_CH0_DCPM_PAUSE_AFTER_GROUP_PACKETS_CTRL_BTP_PACKET_GROUP_ID_MASK 0x0000ff00
-#define BCHP_XPT_MEMDMA_MCPB_CH0_DCPM_PAUSE_AFTER_GROUP_PACKETS_CTRL_BTP_PACKET_GROUP_ID_SHIFT 8
-
-/* XPT_MEMDMA_MCPB_CH0 :: DCPM_PAUSE_AFTER_GROUP_PACKETS_CTRL :: reserved0 [07:03] */
-#define BCHP_XPT_MEMDMA_MCPB_CH0_DCPM_PAUSE_AFTER_GROUP_PACKETS_CTRL_reserved0_MASK 0x000000f8
-#define BCHP_XPT_MEMDMA_MCPB_CH0_DCPM_PAUSE_AFTER_GROUP_PACKETS_CTRL_reserved0_SHIFT 3
-
-/* XPT_MEMDMA_MCPB_CH0 :: DCPM_PAUSE_AFTER_GROUP_PACKETS_CTRL :: DIS_DUPLICATION_COUNTING [02:02] */
-#define BCHP_XPT_MEMDMA_MCPB_CH0_DCPM_PAUSE_AFTER_GROUP_PACKETS_CTRL_DIS_DUPLICATION_COUNTING_MASK 0x00000004
-#define BCHP_XPT_MEMDMA_MCPB_CH0_DCPM_PAUSE_AFTER_GROUP_PACKETS_CTRL_DIS_DUPLICATION_COUNTING_SHIFT 2
-
-/* XPT_MEMDMA_MCPB_CH0 :: DCPM_PAUSE_AFTER_GROUP_PACKETS_CTRL :: DONT_SEND_BTP_PACKET [01:01] */
-#define BCHP_XPT_MEMDMA_MCPB_CH0_DCPM_PAUSE_AFTER_GROUP_PACKETS_CTRL_DONT_SEND_BTP_PACKET_MASK 0x00000002
-#define BCHP_XPT_MEMDMA_MCPB_CH0_DCPM_PAUSE_AFTER_GROUP_PACKETS_CTRL_DONT_SEND_BTP_PACKET_SHIFT 1
-
-/* XPT_MEMDMA_MCPB_CH0 :: DCPM_PAUSE_AFTER_GROUP_PACKETS_CTRL :: ENABLE [00:00] */
-#define BCHP_XPT_MEMDMA_MCPB_CH0_DCPM_PAUSE_AFTER_GROUP_PACKETS_CTRL_ENABLE_MASK 0x00000001
-#define BCHP_XPT_MEMDMA_MCPB_CH0_DCPM_PAUSE_AFTER_GROUP_PACKETS_CTRL_ENABLE_SHIFT 0
-
-/***************************************************************************
- *DCPM_PAUSE_AFTER_GROUP_PACKETS_PKT_COUNTER - MCPB Channel x Pause after group of packets local packet counter
- ***************************************************************************/
-/* XPT_MEMDMA_MCPB_CH0 :: DCPM_PAUSE_AFTER_GROUP_PACKETS_PKT_COUNTER :: reserved0 [31:16] */
-#define BCHP_XPT_MEMDMA_MCPB_CH0_DCPM_PAUSE_AFTER_GROUP_PACKETS_PKT_COUNTER_reserved0_MASK 0xffff0000
-#define BCHP_XPT_MEMDMA_MCPB_CH0_DCPM_PAUSE_AFTER_GROUP_PACKETS_PKT_COUNTER_reserved0_SHIFT 16
-
-/* XPT_MEMDMA_MCPB_CH0 :: DCPM_PAUSE_AFTER_GROUP_PACKETS_PKT_COUNTER :: PKT_COUNTER [15:00] */
-#define BCHP_XPT_MEMDMA_MCPB_CH0_DCPM_PAUSE_AFTER_GROUP_PACKETS_PKT_COUNTER_PKT_COUNTER_MASK 0x0000ffff
-#define BCHP_XPT_MEMDMA_MCPB_CH0_DCPM_PAUSE_AFTER_GROUP_PACKETS_PKT_COUNTER_PKT_COUNTER_SHIFT 0
-
-/***************************************************************************
- *DCPM_LOCAL_PACKET_COUNTER - MCPB Channel x local packet counter
- ***************************************************************************/
-/* XPT_MEMDMA_MCPB_CH0 :: DCPM_LOCAL_PACKET_COUNTER :: PACKET_COUNTER [31:00] */
-#define BCHP_XPT_MEMDMA_MCPB_CH0_DCPM_LOCAL_PACKET_COUNTER_PACKET_COUNTER_MASK 0xffffffff
-#define BCHP_XPT_MEMDMA_MCPB_CH0_DCPM_LOCAL_PACKET_COUNTER_PACKET_COUNTER_SHIFT 0
-
-/***************************************************************************
- *DCPM_DATA_ADDR_UPPER - MCPB Channel x DCPM data address information
- ***************************************************************************/
-/* XPT_MEMDMA_MCPB_CH0 :: DCPM_DATA_ADDR_UPPER :: reserved0 [31:08] */
-#define BCHP_XPT_MEMDMA_MCPB_CH0_DCPM_DATA_ADDR_UPPER_reserved0_MASK 0xffffff00
-#define BCHP_XPT_MEMDMA_MCPB_CH0_DCPM_DATA_ADDR_UPPER_reserved0_SHIFT 8
-
-/* XPT_MEMDMA_MCPB_CH0 :: DCPM_DATA_ADDR_UPPER :: DATA_ADDR [07:00] */
-#define BCHP_XPT_MEMDMA_MCPB_CH0_DCPM_DATA_ADDR_UPPER_DATA_ADDR_MASK 0x000000ff
-#define BCHP_XPT_MEMDMA_MCPB_CH0_DCPM_DATA_ADDR_UPPER_DATA_ADDR_SHIFT 0
-
-/***************************************************************************
- *DCPM_DATA_ADDR_LOWER - MCPB Channel x DCPM data address information
- ***************************************************************************/
-/* XPT_MEMDMA_MCPB_CH0 :: DCPM_DATA_ADDR_LOWER :: DATA_ADDR [31:00] */
-#define BCHP_XPT_MEMDMA_MCPB_CH0_DCPM_DATA_ADDR_LOWER_DATA_ADDR_MASK 0xffffffff
-#define BCHP_XPT_MEMDMA_MCPB_CH0_DCPM_DATA_ADDR_LOWER_DATA_ADDR_SHIFT 0
-
-/***************************************************************************
- *DCPM_CURR_DESC_ADDR - MCPB Channel x DCPM current descriptor address information
- ***************************************************************************/
-/* XPT_MEMDMA_MCPB_CH0 :: DCPM_CURR_DESC_ADDR :: CUR_DESC_ADDR [31:00] */
-#define BCHP_XPT_MEMDMA_MCPB_CH0_DCPM_CURR_DESC_ADDR_CUR_DESC_ADDR_MASK 0xffffffff
-#define BCHP_XPT_MEMDMA_MCPB_CH0_DCPM_CURR_DESC_ADDR_CUR_DESC_ADDR_SHIFT 0
-
-/***************************************************************************
- *DCPM_SLOT_STATUS - MCPB Channel x DCPM slot status information
- ***************************************************************************/
-/* XPT_MEMDMA_MCPB_CH0 :: DCPM_SLOT_STATUS :: reserved0 [31:21] */
-#define BCHP_XPT_MEMDMA_MCPB_CH0_DCPM_SLOT_STATUS_reserved0_MASK 0xffe00000
-#define BCHP_XPT_MEMDMA_MCPB_CH0_DCPM_SLOT_STATUS_reserved0_SHIFT 21
-
-/* XPT_MEMDMA_MCPB_CH0 :: DCPM_SLOT_STATUS :: GENERATE_PAUSE_AT_DESC_READ_INTR_1 [20:20] */
-#define BCHP_XPT_MEMDMA_MCPB_CH0_DCPM_SLOT_STATUS_GENERATE_PAUSE_AT_DESC_READ_INTR_1_MASK 0x00100000
-#define BCHP_XPT_MEMDMA_MCPB_CH0_DCPM_SLOT_STATUS_GENERATE_PAUSE_AT_DESC_READ_INTR_1_SHIFT 20
-
-/* XPT_MEMDMA_MCPB_CH0 :: DCPM_SLOT_STATUS :: GENERATE_PAUSE_AT_DESC_END_INTR_1 [19:19] */
-#define BCHP_XPT_MEMDMA_MCPB_CH0_DCPM_SLOT_STATUS_GENERATE_PAUSE_AT_DESC_END_INTR_1_MASK 0x00080000
-#define BCHP_XPT_MEMDMA_MCPB_CH0_DCPM_SLOT_STATUS_GENERATE_PAUSE_AT_DESC_END_INTR_1_SHIFT 19
-
-/* XPT_MEMDMA_MCPB_CH0 :: DCPM_SLOT_STATUS :: DESC_UPDATE_1 [18:18] */
-#define BCHP_XPT_MEMDMA_MCPB_CH0_DCPM_SLOT_STATUS_DESC_UPDATE_1_MASK 0x00040000
-#define BCHP_XPT_MEMDMA_MCPB_CH0_DCPM_SLOT_STATUS_DESC_UPDATE_1_SHIFT 18
-
-/* XPT_MEMDMA_MCPB_CH0 :: DCPM_SLOT_STATUS :: DESC_DONE_INT_UPDATE_1 [17:17] */
-#define BCHP_XPT_MEMDMA_MCPB_CH0_DCPM_SLOT_STATUS_DESC_DONE_INT_UPDATE_1_MASK 0x00020000
-#define BCHP_XPT_MEMDMA_MCPB_CH0_DCPM_SLOT_STATUS_DESC_DONE_INT_UPDATE_1_SHIFT 17
-
-/* XPT_MEMDMA_MCPB_CH0 :: DCPM_SLOT_STATUS :: DATA_ADDR_CUR_DESC_ADDR_UPDATE_1 [16:16] */
-#define BCHP_XPT_MEMDMA_MCPB_CH0_DCPM_SLOT_STATUS_DATA_ADDR_CUR_DESC_ADDR_UPDATE_1_MASK 0x00010000
-#define BCHP_XPT_MEMDMA_MCPB_CH0_DCPM_SLOT_STATUS_DATA_ADDR_CUR_DESC_ADDR_UPDATE_1_SHIFT 16
-
-/* XPT_MEMDMA_MCPB_CH0 :: DCPM_SLOT_STATUS :: reserved1 [15:05] */
-#define BCHP_XPT_MEMDMA_MCPB_CH0_DCPM_SLOT_STATUS_reserved1_MASK 0x0000ffe0
-#define BCHP_XPT_MEMDMA_MCPB_CH0_DCPM_SLOT_STATUS_reserved1_SHIFT 5
-
-/* XPT_MEMDMA_MCPB_CH0 :: DCPM_SLOT_STATUS :: GENERATE_PAUSE_AT_DESC_READ_INTR_0 [04:04] */
-#define BCHP_XPT_MEMDMA_MCPB_CH0_DCPM_SLOT_STATUS_GENERATE_PAUSE_AT_DESC_READ_INTR_0_MASK 0x00000010
-#define BCHP_XPT_MEMDMA_MCPB_CH0_DCPM_SLOT_STATUS_GENERATE_PAUSE_AT_DESC_READ_INTR_0_SHIFT 4
-
-/* XPT_MEMDMA_MCPB_CH0 :: DCPM_SLOT_STATUS :: GENERATE_PAUSE_AT_DESC_END_INTR_0 [03:03] */
-#define BCHP_XPT_MEMDMA_MCPB_CH0_DCPM_SLOT_STATUS_GENERATE_PAUSE_AT_DESC_END_INTR_0_MASK 0x00000008
-#define BCHP_XPT_MEMDMA_MCPB_CH0_DCPM_SLOT_STATUS_GENERATE_PAUSE_AT_DESC_END_INTR_0_SHIFT 3
-
-/* XPT_MEMDMA_MCPB_CH0 :: DCPM_SLOT_STATUS :: DESC_UPDATE_0 [02:02] */
-#define BCHP_XPT_MEMDMA_MCPB_CH0_DCPM_SLOT_STATUS_DESC_UPDATE_0_MASK 0x00000004
-#define BCHP_XPT_MEMDMA_MCPB_CH0_DCPM_SLOT_STATUS_DESC_UPDATE_0_SHIFT 2
-
-/* XPT_MEMDMA_MCPB_CH0 :: DCPM_SLOT_STATUS :: DESC_DONE_INT_UPDATE_0 [01:01] */
-#define BCHP_XPT_MEMDMA_MCPB_CH0_DCPM_SLOT_STATUS_DESC_DONE_INT_UPDATE_0_MASK 0x00000002
-#define BCHP_XPT_MEMDMA_MCPB_CH0_DCPM_SLOT_STATUS_DESC_DONE_INT_UPDATE_0_SHIFT 1
-
-/* XPT_MEMDMA_MCPB_CH0 :: DCPM_SLOT_STATUS :: DATA_ADDR_CUR_DESC_ADDR_UPDATE_0 [00:00] */
-#define BCHP_XPT_MEMDMA_MCPB_CH0_DCPM_SLOT_STATUS_DATA_ADDR_CUR_DESC_ADDR_UPDATE_0_MASK 0x00000001
-#define BCHP_XPT_MEMDMA_MCPB_CH0_DCPM_SLOT_STATUS_DATA_ADDR_CUR_DESC_ADDR_UPDATE_0_SHIFT 0
-
-/***************************************************************************
- *DCPM_DESC_ADDR_SLOT_0 - MCPB Channel x DCPM completed slot 0 descriptor address information
- ***************************************************************************/
-/* XPT_MEMDMA_MCPB_CH0 :: DCPM_DESC_ADDR_SLOT_0 :: DESC_ADDR_SLOT_0 [31:04] */
-#define BCHP_XPT_MEMDMA_MCPB_CH0_DCPM_DESC_ADDR_SLOT_0_DESC_ADDR_SLOT_0_MASK 0xfffffff0
-#define BCHP_XPT_MEMDMA_MCPB_CH0_DCPM_DESC_ADDR_SLOT_0_DESC_ADDR_SLOT_0_SHIFT 4
-
-/* XPT_MEMDMA_MCPB_CH0 :: DCPM_DESC_ADDR_SLOT_0 :: DESC_ID_SLOT_0 [03:00] */
-#define BCHP_XPT_MEMDMA_MCPB_CH0_DCPM_DESC_ADDR_SLOT_0_DESC_ID_SLOT_0_MASK 0x0000000f
-#define BCHP_XPT_MEMDMA_MCPB_CH0_DCPM_DESC_ADDR_SLOT_0_DESC_ID_SLOT_0_SHIFT 0
-
-/***************************************************************************
- *DCPM_DATA_ADDR_SLOT_0_UPPER - MCPB Channel x DCPM completed slot 0 data address information
- ***************************************************************************/
-/* XPT_MEMDMA_MCPB_CH0 :: DCPM_DATA_ADDR_SLOT_0_UPPER :: reserved0 [31:08] */
-#define BCHP_XPT_MEMDMA_MCPB_CH0_DCPM_DATA_ADDR_SLOT_0_UPPER_reserved0_MASK 0xffffff00
-#define BCHP_XPT_MEMDMA_MCPB_CH0_DCPM_DATA_ADDR_SLOT_0_UPPER_reserved0_SHIFT 8
-
-/* XPT_MEMDMA_MCPB_CH0 :: DCPM_DATA_ADDR_SLOT_0_UPPER :: DATA_ADDR_0 [07:00] */
-#define BCHP_XPT_MEMDMA_MCPB_CH0_DCPM_DATA_ADDR_SLOT_0_UPPER_DATA_ADDR_0_MASK 0x000000ff
-#define BCHP_XPT_MEMDMA_MCPB_CH0_DCPM_DATA_ADDR_SLOT_0_UPPER_DATA_ADDR_0_SHIFT 0
-
-/***************************************************************************
- *DCPM_DATA_ADDR_SLOT_0_LOWER - MCPB Channel x DCPM completed slot 0 data address information
- ***************************************************************************/
-/* XPT_MEMDMA_MCPB_CH0 :: DCPM_DATA_ADDR_SLOT_0_LOWER :: DATA_ADDR_0 [31:00] */
-#define BCHP_XPT_MEMDMA_MCPB_CH0_DCPM_DATA_ADDR_SLOT_0_LOWER_DATA_ADDR_0_MASK 0xffffffff
-#define BCHP_XPT_MEMDMA_MCPB_CH0_DCPM_DATA_ADDR_SLOT_0_LOWER_DATA_ADDR_0_SHIFT 0
-
-/***************************************************************************
- *DCPM_DESC_ADDR_SLOT_1 - MCPB Channel x DCPM completed slot 1 descriptor address information
- ***************************************************************************/
-/* XPT_MEMDMA_MCPB_CH0 :: DCPM_DESC_ADDR_SLOT_1 :: DESC_ADDR_SLOT_1 [31:04] */
-#define BCHP_XPT_MEMDMA_MCPB_CH0_DCPM_DESC_ADDR_SLOT_1_DESC_ADDR_SLOT_1_MASK 0xfffffff0
-#define BCHP_XPT_MEMDMA_MCPB_CH0_DCPM_DESC_ADDR_SLOT_1_DESC_ADDR_SLOT_1_SHIFT 4
-
-/* XPT_MEMDMA_MCPB_CH0 :: DCPM_DESC_ADDR_SLOT_1 :: DESC_ID_SLOT_1 [03:00] */
-#define BCHP_XPT_MEMDMA_MCPB_CH0_DCPM_DESC_ADDR_SLOT_1_DESC_ID_SLOT_1_MASK 0x0000000f
-#define BCHP_XPT_MEMDMA_MCPB_CH0_DCPM_DESC_ADDR_SLOT_1_DESC_ID_SLOT_1_SHIFT 0
-
-/***************************************************************************
- *DCPM_DATA_ADDR_SLOT_1_UPPER - MCPB Channel x DCPM completed slot 1 data address information
- ***************************************************************************/
-/* XPT_MEMDMA_MCPB_CH0 :: DCPM_DATA_ADDR_SLOT_1_UPPER :: reserved0 [31:08] */
-#define BCHP_XPT_MEMDMA_MCPB_CH0_DCPM_DATA_ADDR_SLOT_1_UPPER_reserved0_MASK 0xffffff00
-#define BCHP_XPT_MEMDMA_MCPB_CH0_DCPM_DATA_ADDR_SLOT_1_UPPER_reserved0_SHIFT 8
-
-/* XPT_MEMDMA_MCPB_CH0 :: DCPM_DATA_ADDR_SLOT_1_UPPER :: DATA_ADDR_1 [07:00] */
-#define BCHP_XPT_MEMDMA_MCPB_CH0_DCPM_DATA_ADDR_SLOT_1_UPPER_DATA_ADDR_1_MASK 0x000000ff
-#define BCHP_XPT_MEMDMA_MCPB_CH0_DCPM_DATA_ADDR_SLOT_1_UPPER_DATA_ADDR_1_SHIFT 0
-
-/***************************************************************************
- *DCPM_DATA_ADDR_SLOT_1_LOWER - MCPB Channel x DCPM completed slot 1 data address information
- ***************************************************************************/
-/* XPT_MEMDMA_MCPB_CH0 :: DCPM_DATA_ADDR_SLOT_1_LOWER :: DATA_ADDR_1 [31:00] */
-#define BCHP_XPT_MEMDMA_MCPB_CH0_DCPM_DATA_ADDR_SLOT_1_LOWER_DATA_ADDR_1_MASK 0xffffffff
-#define BCHP_XPT_MEMDMA_MCPB_CH0_DCPM_DATA_ADDR_SLOT_1_LOWER_DATA_ADDR_1_SHIFT 0
-
-#endif /* #ifndef BCHP_XPT_MEMDMA_MCPB_CH0_H__ */
-
-/* End of File */
diff --git a/include/linux/brcmstb/7366b0/bchp_xpt_pmu.h b/include/linux/brcmstb/7366b0/bchp_xpt_pmu.h
deleted file mode 100644
index e4993db..0000000
--- a/include/linux/brcmstb/7366b0/bchp_xpt_pmu.h
+++ /dev/null
@@ -1,397 +0,0 @@
-/***************************************************************************
- * Copyright (c) 1999-2014, Broadcom Corporation
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
- *
- * Module Description:
- * DO NOT EDIT THIS FILE DIRECTLY
- *
- * This module was generated magically with RDB from a source description
- * file. You must edit the source file for changes to be made to this file.
- *
- *
- * Date: Generated on Wed Sep 3 14:59:59 2014
- * Full Compile MD5 Checksum 10187d4079392bab2546025f43274d34
- * (minus title and desc)
- * MD5 Checksum c1587c5e16f21f52e852e7c7a65c7811
- *
- * Compiled with: RDB Utility combo_header.pl
- * RDB Parser 3.0
- * unknown unknown
- * Perl Interpreter 5.008005
- * Operating System linux
- *
- * Revision History:
- *
- * $brcm_Log: $
- *
- ***************************************************************************/
-
-#ifndef BCHP_XPT_PMU_H__
-#define BCHP_XPT_PMU_H__
-
-/***************************************************************************
- *XPT_PMU - XPT PMU Control Registers
- ***************************************************************************/
-#define BCHP_XPT_PMU_CLK_CTRL 0x00a00200 /* Power Management control */
-#define BCHP_XPT_PMU_RBUS_RSP_CTRL 0x00a00204 /* Power Management control */
-#define BCHP_XPT_PMU_RBUS_RSP_VAL 0x00a00208 /* Power Management control */
-#define BCHP_XPT_PMU_PSM_VDD_CTRL 0x00a0020c /* Power Management control */
-#define BCHP_XPT_PMU_STBY_CTRL 0x00a00210 /* Power Management control */
-#define BCHP_XPT_PMU_MEM_INIT_CTRL 0x00a00214 /* Power Management control */
-#define BCHP_XPT_PMU_MEMDMA_SW_INIT_CTRL 0x00a00218 /* Power Management control */
-
-/***************************************************************************
- *CLK_CTRL - Power Management control
- ***************************************************************************/
-/* XPT_PMU :: CLK_CTRL :: reserved0 [31:20] */
-#define BCHP_XPT_PMU_CLK_CTRL_reserved0_MASK 0xfff00000
-#define BCHP_XPT_PMU_CLK_CTRL_reserved0_SHIFT 20
-
-/* XPT_PMU :: CLK_CTRL :: TSIO_DISABLE [19:19] */
-#define BCHP_XPT_PMU_CLK_CTRL_TSIO_DISABLE_MASK 0x00080000
-#define BCHP_XPT_PMU_CLK_CTRL_TSIO_DISABLE_SHIFT 19
-#define BCHP_XPT_PMU_CLK_CTRL_TSIO_DISABLE_DEFAULT 0x00000000
-
-/* XPT_PMU :: CLK_CTRL :: MEMDMA_DISABLE [18:18] */
-#define BCHP_XPT_PMU_CLK_CTRL_MEMDMA_DISABLE_MASK 0x00040000
-#define BCHP_XPT_PMU_CLK_CTRL_MEMDMA_DISABLE_SHIFT 18
-#define BCHP_XPT_PMU_CLK_CTRL_MEMDMA_DISABLE_DEFAULT 0x00000000
-
-/* XPT_PMU :: CLK_CTRL :: FULL_PID_PARSER_DISABLE [17:17] */
-#define BCHP_XPT_PMU_CLK_CTRL_FULL_PID_PARSER_DISABLE_MASK 0x00020000
-#define BCHP_XPT_PMU_CLK_CTRL_FULL_PID_PARSER_DISABLE_SHIFT 17
-#define BCHP_XPT_PMU_CLK_CTRL_FULL_PID_PARSER_DISABLE_DEFAULT 0x00000000
-
-/* XPT_PMU :: CLK_CTRL :: WAKEUP_DISABLE [16:16] */
-#define BCHP_XPT_PMU_CLK_CTRL_WAKEUP_DISABLE_MASK 0x00010000
-#define BCHP_XPT_PMU_CLK_CTRL_WAKEUP_DISABLE_SHIFT 16
-#define BCHP_XPT_PMU_CLK_CTRL_WAKEUP_DISABLE_DEFAULT 0x00000000
-
-/* XPT_PMU :: CLK_CTRL :: RMX1_DISABLE [15:15] */
-#define BCHP_XPT_PMU_CLK_CTRL_RMX1_DISABLE_MASK 0x00008000
-#define BCHP_XPT_PMU_CLK_CTRL_RMX1_DISABLE_SHIFT 15
-#define BCHP_XPT_PMU_CLK_CTRL_RMX1_DISABLE_DEFAULT 0x00000000
-
-/* XPT_PMU :: CLK_CTRL :: RMX0_DISABLE [14:14] */
-#define BCHP_XPT_PMU_CLK_CTRL_RMX0_DISABLE_MASK 0x00004000
-#define BCHP_XPT_PMU_CLK_CTRL_RMX0_DISABLE_SHIFT 14
-#define BCHP_XPT_PMU_CLK_CTRL_RMX0_DISABLE_DEFAULT 0x00000000
-
-/* XPT_PMU :: CLK_CTRL :: MPOD_DISABLE [13:13] */
-#define BCHP_XPT_PMU_CLK_CTRL_MPOD_DISABLE_MASK 0x00002000
-#define BCHP_XPT_PMU_CLK_CTRL_MPOD_DISABLE_SHIFT 13
-#define BCHP_XPT_PMU_CLK_CTRL_MPOD_DISABLE_DEFAULT 0x00000000
-
-/* XPT_PMU :: CLK_CTRL :: XPT_IO_DISABLE [12:12] */
-#define BCHP_XPT_PMU_CLK_CTRL_XPT_IO_DISABLE_MASK 0x00001000
-#define BCHP_XPT_PMU_CLK_CTRL_XPT_IO_DISABLE_SHIFT 12
-#define BCHP_XPT_PMU_CLK_CTRL_XPT_IO_DISABLE_DEFAULT 0x00000000
-
-/* XPT_PMU :: CLK_CTRL :: PB_DISABLE [11:11] */
-#define BCHP_XPT_PMU_CLK_CTRL_PB_DISABLE_MASK 0x00000800
-#define BCHP_XPT_PMU_CLK_CTRL_PB_DISABLE_SHIFT 11
-#define BCHP_XPT_PMU_CLK_CTRL_PB_DISABLE_DEFAULT 0x00000000
-
-/* XPT_PMU :: CLK_CTRL :: PSUB_DISABLE [10:10] */
-#define BCHP_XPT_PMU_CLK_CTRL_PSUB_DISABLE_MASK 0x00000400
-#define BCHP_XPT_PMU_CLK_CTRL_PSUB_DISABLE_SHIFT 10
-#define BCHP_XPT_PMU_CLK_CTRL_PSUB_DISABLE_DEFAULT 0x00000000
-
-/* XPT_PMU :: CLK_CTRL :: BUS_IF_DISABLE [09:09] */
-#define BCHP_XPT_PMU_CLK_CTRL_BUS_IF_DISABLE_MASK 0x00000200
-#define BCHP_XPT_PMU_CLK_CTRL_BUS_IF_DISABLE_SHIFT 9
-#define BCHP_XPT_PMU_CLK_CTRL_BUS_IF_DISABLE_DEFAULT 0x00000000
-
-/* XPT_PMU :: CLK_CTRL :: PCROFFSET_DISABLE [08:08] */
-#define BCHP_XPT_PMU_CLK_CTRL_PCROFFSET_DISABLE_MASK 0x00000100
-#define BCHP_XPT_PMU_CLK_CTRL_PCROFFSET_DISABLE_SHIFT 8
-#define BCHP_XPT_PMU_CLK_CTRL_PCROFFSET_DISABLE_DEFAULT 0x00000000
-
-/* XPT_PMU :: CLK_CTRL :: RAVE_DISABLE [07:07] */
-#define BCHP_XPT_PMU_CLK_CTRL_RAVE_DISABLE_MASK 0x00000080
-#define BCHP_XPT_PMU_CLK_CTRL_RAVE_DISABLE_SHIFT 7
-#define BCHP_XPT_PMU_CLK_CTRL_RAVE_DISABLE_DEFAULT 0x00000000
-
-/* XPT_PMU :: CLK_CTRL :: MSG_DISABLE [06:06] */
-#define BCHP_XPT_PMU_CLK_CTRL_MSG_DISABLE_MASK 0x00000040
-#define BCHP_XPT_PMU_CLK_CTRL_MSG_DISABLE_SHIFT 6
-#define BCHP_XPT_PMU_CLK_CTRL_MSG_DISABLE_DEFAULT 0x00000000
-
-/* XPT_PMU :: CLK_CTRL :: DPCR_DISABLE [05:05] */
-#define BCHP_XPT_PMU_CLK_CTRL_DPCR_DISABLE_MASK 0x00000020
-#define BCHP_XPT_PMU_CLK_CTRL_DPCR_DISABLE_SHIFT 5
-#define BCHP_XPT_PMU_CLK_CTRL_DPCR_DISABLE_DEFAULT 0x00000000
-
-/* XPT_PMU :: CLK_CTRL :: XMEMIF_216_DISABLE [04:04] */
-#define BCHP_XPT_PMU_CLK_CTRL_XMEMIF_216_DISABLE_MASK 0x00000010
-#define BCHP_XPT_PMU_CLK_CTRL_XMEMIF_216_DISABLE_SHIFT 4
-#define BCHP_XPT_PMU_CLK_CTRL_XMEMIF_216_DISABLE_DEFAULT 0x00000000
-
-/* XPT_PMU :: CLK_CTRL :: XMEMIF_108_DISABLE [03:03] */
-#define BCHP_XPT_PMU_CLK_CTRL_XMEMIF_108_DISABLE_MASK 0x00000008
-#define BCHP_XPT_PMU_CLK_CTRL_XMEMIF_108_DISABLE_SHIFT 3
-#define BCHP_XPT_PMU_CLK_CTRL_XMEMIF_108_DISABLE_DEFAULT 0x00000000
-
-/* XPT_PMU :: CLK_CTRL :: XCBUFF_DISABLE [02:02] */
-#define BCHP_XPT_PMU_CLK_CTRL_XCBUFF_DISABLE_MASK 0x00000004
-#define BCHP_XPT_PMU_CLK_CTRL_XCBUFF_DISABLE_SHIFT 2
-#define BCHP_XPT_PMU_CLK_CTRL_XCBUFF_DISABLE_DEFAULT 0x00000000
-
-/* XPT_PMU :: CLK_CTRL :: RSBUFF_DISABLE [01:01] */
-#define BCHP_XPT_PMU_CLK_CTRL_RSBUFF_DISABLE_MASK 0x00000002
-#define BCHP_XPT_PMU_CLK_CTRL_RSBUFF_DISABLE_SHIFT 1
-#define BCHP_XPT_PMU_CLK_CTRL_RSBUFF_DISABLE_DEFAULT 0x00000000
-
-/* XPT_PMU :: CLK_CTRL :: FE_DISABLE [00:00] */
-#define BCHP_XPT_PMU_CLK_CTRL_FE_DISABLE_MASK 0x00000001
-#define BCHP_XPT_PMU_CLK_CTRL_FE_DISABLE_SHIFT 0
-#define BCHP_XPT_PMU_CLK_CTRL_FE_DISABLE_DEFAULT 0x00000000
-
-/***************************************************************************
- *RBUS_RSP_CTRL - Power Management control
- ***************************************************************************/
-/* XPT_PMU :: RBUS_RSP_CTRL :: reserved0 [31:02] */
-#define BCHP_XPT_PMU_RBUS_RSP_CTRL_reserved0_MASK 0xfffffffc
-#define BCHP_XPT_PMU_RBUS_RSP_CTRL_reserved0_SHIFT 2
-
-/* XPT_PMU :: RBUS_RSP_CTRL :: RBUS_WR_RSP [01:01] */
-#define BCHP_XPT_PMU_RBUS_RSP_CTRL_RBUS_WR_RSP_MASK 0x00000002
-#define BCHP_XPT_PMU_RBUS_RSP_CTRL_RBUS_WR_RSP_SHIFT 1
-#define BCHP_XPT_PMU_RBUS_RSP_CTRL_RBUS_WR_RSP_DEFAULT 0x00000000
-
-/* XPT_PMU :: RBUS_RSP_CTRL :: RBUS_RD_RSP [00:00] */
-#define BCHP_XPT_PMU_RBUS_RSP_CTRL_RBUS_RD_RSP_MASK 0x00000001
-#define BCHP_XPT_PMU_RBUS_RSP_CTRL_RBUS_RD_RSP_SHIFT 0
-#define BCHP_XPT_PMU_RBUS_RSP_CTRL_RBUS_RD_RSP_DEFAULT 0x00000000
-
-/***************************************************************************
- *RBUS_RSP_VAL - Power Management control
- ***************************************************************************/
-/* XPT_PMU :: RBUS_RSP_VAL :: RD_RSP_VAL [31:00] */
-#define BCHP_XPT_PMU_RBUS_RSP_VAL_RD_RSP_VAL_MASK 0xffffffff
-#define BCHP_XPT_PMU_RBUS_RSP_VAL_RD_RSP_VAL_SHIFT 0
-#define BCHP_XPT_PMU_RBUS_RSP_VAL_RD_RSP_VAL_DEFAULT 0xdeaddead
-
-/***************************************************************************
- *PSM_VDD_CTRL - Power Management control
- ***************************************************************************/
-/* XPT_PMU :: PSM_VDD_CTRL :: reserved0 [31:14] */
-#define BCHP_XPT_PMU_PSM_VDD_CTRL_reserved0_MASK 0xffffc000
-#define BCHP_XPT_PMU_PSM_VDD_CTRL_reserved0_SHIFT 14
-
-/* XPT_PMU :: PSM_VDD_CTRL :: TSIO_DISABLE [13:13] */
-#define BCHP_XPT_PMU_PSM_VDD_CTRL_TSIO_DISABLE_MASK 0x00002000
-#define BCHP_XPT_PMU_PSM_VDD_CTRL_TSIO_DISABLE_SHIFT 13
-#define BCHP_XPT_PMU_PSM_VDD_CTRL_TSIO_DISABLE_DEFAULT 0x00000000
-
-/* XPT_PMU :: PSM_VDD_CTRL :: MEMDMA_DISABLE [12:12] */
-#define BCHP_XPT_PMU_PSM_VDD_CTRL_MEMDMA_DISABLE_MASK 0x00001000
-#define BCHP_XPT_PMU_PSM_VDD_CTRL_MEMDMA_DISABLE_SHIFT 12
-#define BCHP_XPT_PMU_PSM_VDD_CTRL_MEMDMA_DISABLE_DEFAULT 0x00000000
-
-/* XPT_PMU :: PSM_VDD_CTRL :: PB_DISABLE [11:11] */
-#define BCHP_XPT_PMU_PSM_VDD_CTRL_PB_DISABLE_MASK 0x00000800
-#define BCHP_XPT_PMU_PSM_VDD_CTRL_PB_DISABLE_SHIFT 11
-#define BCHP_XPT_PMU_PSM_VDD_CTRL_PB_DISABLE_DEFAULT 0x00000000
-
-/* XPT_PMU :: PSM_VDD_CTRL :: PSUB_DISABLE [10:10] */
-#define BCHP_XPT_PMU_PSM_VDD_CTRL_PSUB_DISABLE_MASK 0x00000400
-#define BCHP_XPT_PMU_PSM_VDD_CTRL_PSUB_DISABLE_SHIFT 10
-#define BCHP_XPT_PMU_PSM_VDD_CTRL_PSUB_DISABLE_DEFAULT 0x00000000
-
-/* XPT_PMU :: PSM_VDD_CTRL :: PCROFFSET_DISABLE [09:09] */
-#define BCHP_XPT_PMU_PSM_VDD_CTRL_PCROFFSET_DISABLE_MASK 0x00000200
-#define BCHP_XPT_PMU_PSM_VDD_CTRL_PCROFFSET_DISABLE_SHIFT 9
-#define BCHP_XPT_PMU_PSM_VDD_CTRL_PCROFFSET_DISABLE_DEFAULT 0x00000000
-
-/* XPT_PMU :: PSM_VDD_CTRL :: RAVE_DISABLE [08:08] */
-#define BCHP_XPT_PMU_PSM_VDD_CTRL_RAVE_DISABLE_MASK 0x00000100
-#define BCHP_XPT_PMU_PSM_VDD_CTRL_RAVE_DISABLE_SHIFT 8
-#define BCHP_XPT_PMU_PSM_VDD_CTRL_RAVE_DISABLE_DEFAULT 0x00000000
-
-/* XPT_PMU :: PSM_VDD_CTRL :: MSG_DISABLE [07:07] */
-#define BCHP_XPT_PMU_PSM_VDD_CTRL_MSG_DISABLE_MASK 0x00000080
-#define BCHP_XPT_PMU_PSM_VDD_CTRL_MSG_DISABLE_SHIFT 7
-#define BCHP_XPT_PMU_PSM_VDD_CTRL_MSG_DISABLE_DEFAULT 0x00000000
-
-/* XPT_PMU :: PSM_VDD_CTRL :: XMEMIF_DISABLE [06:06] */
-#define BCHP_XPT_PMU_PSM_VDD_CTRL_XMEMIF_DISABLE_MASK 0x00000040
-#define BCHP_XPT_PMU_PSM_VDD_CTRL_XMEMIF_DISABLE_SHIFT 6
-#define BCHP_XPT_PMU_PSM_VDD_CTRL_XMEMIF_DISABLE_DEFAULT 0x00000000
-
-/* XPT_PMU :: PSM_VDD_CTRL :: FPP_DISABLE [05:05] */
-#define BCHP_XPT_PMU_PSM_VDD_CTRL_FPP_DISABLE_MASK 0x00000020
-#define BCHP_XPT_PMU_PSM_VDD_CTRL_FPP_DISABLE_SHIFT 5
-#define BCHP_XPT_PMU_PSM_VDD_CTRL_FPP_DISABLE_DEFAULT 0x00000000
-
-/* XPT_PMU :: PSM_VDD_CTRL :: XCBUFF_DISABLE [04:04] */
-#define BCHP_XPT_PMU_PSM_VDD_CTRL_XCBUFF_DISABLE_MASK 0x00000010
-#define BCHP_XPT_PMU_PSM_VDD_CTRL_XCBUFF_DISABLE_SHIFT 4
-#define BCHP_XPT_PMU_PSM_VDD_CTRL_XCBUFF_DISABLE_DEFAULT 0x00000000
-
-/* XPT_PMU :: PSM_VDD_CTRL :: RSBUFF_DISABLE [03:03] */
-#define BCHP_XPT_PMU_PSM_VDD_CTRL_RSBUFF_DISABLE_MASK 0x00000008
-#define BCHP_XPT_PMU_PSM_VDD_CTRL_RSBUFF_DISABLE_SHIFT 3
-#define BCHP_XPT_PMU_PSM_VDD_CTRL_RSBUFF_DISABLE_DEFAULT 0x00000000
-
-/* XPT_PMU :: PSM_VDD_CTRL :: FE_DISABLE [02:02] */
-#define BCHP_XPT_PMU_PSM_VDD_CTRL_FE_DISABLE_MASK 0x00000004
-#define BCHP_XPT_PMU_PSM_VDD_CTRL_FE_DISABLE_SHIFT 2
-#define BCHP_XPT_PMU_PSM_VDD_CTRL_FE_DISABLE_DEFAULT 0x00000000
-
-/* XPT_PMU :: PSM_VDD_CTRL :: WAKEUP_CFG_DISABLE [01:01] */
-#define BCHP_XPT_PMU_PSM_VDD_CTRL_WAKEUP_CFG_DISABLE_MASK 0x00000002
-#define BCHP_XPT_PMU_PSM_VDD_CTRL_WAKEUP_CFG_DISABLE_SHIFT 1
-#define BCHP_XPT_PMU_PSM_VDD_CTRL_WAKEUP_CFG_DISABLE_DEFAULT 0x00000001
-
-/* XPT_PMU :: PSM_VDD_CTRL :: RAVE_IMEM_DISABLE [00:00] */
-#define BCHP_XPT_PMU_PSM_VDD_CTRL_RAVE_IMEM_DISABLE_MASK 0x00000001
-#define BCHP_XPT_PMU_PSM_VDD_CTRL_RAVE_IMEM_DISABLE_SHIFT 0
-#define BCHP_XPT_PMU_PSM_VDD_CTRL_RAVE_IMEM_DISABLE_DEFAULT 0x00000001
-
-/***************************************************************************
- *STBY_CTRL - Power Management control
- ***************************************************************************/
-/* XPT_PMU :: STBY_CTRL :: reserved0 [31:14] */
-#define BCHP_XPT_PMU_STBY_CTRL_reserved0_MASK 0xffffc000
-#define BCHP_XPT_PMU_STBY_CTRL_reserved0_SHIFT 14
-
-/* XPT_PMU :: STBY_CTRL :: TSIO_DISABLE [13:13] */
-#define BCHP_XPT_PMU_STBY_CTRL_TSIO_DISABLE_MASK 0x00002000
-#define BCHP_XPT_PMU_STBY_CTRL_TSIO_DISABLE_SHIFT 13
-#define BCHP_XPT_PMU_STBY_CTRL_TSIO_DISABLE_DEFAULT 0x00000000
-
-/* XPT_PMU :: STBY_CTRL :: MEMDMA_DISABLE [12:12] */
-#define BCHP_XPT_PMU_STBY_CTRL_MEMDMA_DISABLE_MASK 0x00001000
-#define BCHP_XPT_PMU_STBY_CTRL_MEMDMA_DISABLE_SHIFT 12
-#define BCHP_XPT_PMU_STBY_CTRL_MEMDMA_DISABLE_DEFAULT 0x00000000
-
-/* XPT_PMU :: STBY_CTRL :: PB_DISABLE [11:11] */
-#define BCHP_XPT_PMU_STBY_CTRL_PB_DISABLE_MASK 0x00000800
-#define BCHP_XPT_PMU_STBY_CTRL_PB_DISABLE_SHIFT 11
-#define BCHP_XPT_PMU_STBY_CTRL_PB_DISABLE_DEFAULT 0x00000000
-
-/* XPT_PMU :: STBY_CTRL :: PSUB_DISABLE [10:10] */
-#define BCHP_XPT_PMU_STBY_CTRL_PSUB_DISABLE_MASK 0x00000400
-#define BCHP_XPT_PMU_STBY_CTRL_PSUB_DISABLE_SHIFT 10
-#define BCHP_XPT_PMU_STBY_CTRL_PSUB_DISABLE_DEFAULT 0x00000000
-
-/* XPT_PMU :: STBY_CTRL :: PCROFFSET_DISABLE [09:09] */
-#define BCHP_XPT_PMU_STBY_CTRL_PCROFFSET_DISABLE_MASK 0x00000200
-#define BCHP_XPT_PMU_STBY_CTRL_PCROFFSET_DISABLE_SHIFT 9
-#define BCHP_XPT_PMU_STBY_CTRL_PCROFFSET_DISABLE_DEFAULT 0x00000000
-
-/* XPT_PMU :: STBY_CTRL :: RAVE_DISABLE [08:08] */
-#define BCHP_XPT_PMU_STBY_CTRL_RAVE_DISABLE_MASK 0x00000100
-#define BCHP_XPT_PMU_STBY_CTRL_RAVE_DISABLE_SHIFT 8
-#define BCHP_XPT_PMU_STBY_CTRL_RAVE_DISABLE_DEFAULT 0x00000000
-
-/* XPT_PMU :: STBY_CTRL :: MSG_DISABLE [07:07] */
-#define BCHP_XPT_PMU_STBY_CTRL_MSG_DISABLE_MASK 0x00000080
-#define BCHP_XPT_PMU_STBY_CTRL_MSG_DISABLE_SHIFT 7
-#define BCHP_XPT_PMU_STBY_CTRL_MSG_DISABLE_DEFAULT 0x00000000
-
-/* XPT_PMU :: STBY_CTRL :: XMEMIF_DISABLE [06:06] */
-#define BCHP_XPT_PMU_STBY_CTRL_XMEMIF_DISABLE_MASK 0x00000040
-#define BCHP_XPT_PMU_STBY_CTRL_XMEMIF_DISABLE_SHIFT 6
-#define BCHP_XPT_PMU_STBY_CTRL_XMEMIF_DISABLE_DEFAULT 0x00000000
-
-/* XPT_PMU :: STBY_CTRL :: FPP_DISABLE [05:05] */
-#define BCHP_XPT_PMU_STBY_CTRL_FPP_DISABLE_MASK 0x00000020
-#define BCHP_XPT_PMU_STBY_CTRL_FPP_DISABLE_SHIFT 5
-#define BCHP_XPT_PMU_STBY_CTRL_FPP_DISABLE_DEFAULT 0x00000000
-
-/* XPT_PMU :: STBY_CTRL :: XCBUFF_DISABLE [04:04] */
-#define BCHP_XPT_PMU_STBY_CTRL_XCBUFF_DISABLE_MASK 0x00000010
-#define BCHP_XPT_PMU_STBY_CTRL_XCBUFF_DISABLE_SHIFT 4
-#define BCHP_XPT_PMU_STBY_CTRL_XCBUFF_DISABLE_DEFAULT 0x00000000
-
-/* XPT_PMU :: STBY_CTRL :: RSBUFF_DISABLE [03:03] */
-#define BCHP_XPT_PMU_STBY_CTRL_RSBUFF_DISABLE_MASK 0x00000008
-#define BCHP_XPT_PMU_STBY_CTRL_RSBUFF_DISABLE_SHIFT 3
-#define BCHP_XPT_PMU_STBY_CTRL_RSBUFF_DISABLE_DEFAULT 0x00000000
-
-/* XPT_PMU :: STBY_CTRL :: FE_DISABLE [02:02] */
-#define BCHP_XPT_PMU_STBY_CTRL_FE_DISABLE_MASK 0x00000004
-#define BCHP_XPT_PMU_STBY_CTRL_FE_DISABLE_SHIFT 2
-#define BCHP_XPT_PMU_STBY_CTRL_FE_DISABLE_DEFAULT 0x00000000
-
-/* XPT_PMU :: STBY_CTRL :: WAKEUP_CFG_DISABLE [01:01] */
-#define BCHP_XPT_PMU_STBY_CTRL_WAKEUP_CFG_DISABLE_MASK 0x00000002
-#define BCHP_XPT_PMU_STBY_CTRL_WAKEUP_CFG_DISABLE_SHIFT 1
-#define BCHP_XPT_PMU_STBY_CTRL_WAKEUP_CFG_DISABLE_DEFAULT 0x00000001
-
-/* XPT_PMU :: STBY_CTRL :: RAVE_IMEM_DISABLE [00:00] */
-#define BCHP_XPT_PMU_STBY_CTRL_RAVE_IMEM_DISABLE_MASK 0x00000001
-#define BCHP_XPT_PMU_STBY_CTRL_RAVE_IMEM_DISABLE_SHIFT 0
-#define BCHP_XPT_PMU_STBY_CTRL_RAVE_IMEM_DISABLE_DEFAULT 0x00000001
-
-/***************************************************************************
- *MEM_INIT_CTRL - Power Management control
- ***************************************************************************/
-/* XPT_PMU :: MEM_INIT_CTRL :: reserved0 [31:06] */
-#define BCHP_XPT_PMU_MEM_INIT_CTRL_reserved0_MASK 0xffffffc0
-#define BCHP_XPT_PMU_MEM_INIT_CTRL_reserved0_SHIFT 6
-
-/* XPT_PMU :: MEM_INIT_CTRL :: FE_PID_SPID_MEM_INIT [05:05] */
-#define BCHP_XPT_PMU_MEM_INIT_CTRL_FE_PID_SPID_MEM_INIT_MASK 0x00000020
-#define BCHP_XPT_PMU_MEM_INIT_CTRL_FE_PID_SPID_MEM_INIT_SHIFT 5
-#define BCHP_XPT_PMU_MEM_INIT_CTRL_FE_PID_SPID_MEM_INIT_DEFAULT 0x00000000
-
-/* XPT_PMU :: MEM_INIT_CTRL :: FPP_SCM_INIT [04:04] */
-#define BCHP_XPT_PMU_MEM_INIT_CTRL_FPP_SCM_INIT_MASK 0x00000010
-#define BCHP_XPT_PMU_MEM_INIT_CTRL_FPP_SCM_INIT_SHIFT 4
-#define BCHP_XPT_PMU_MEM_INIT_CTRL_FPP_SCM_INIT_DEFAULT 0x00000000
-
-/* XPT_PMU :: MEM_INIT_CTRL :: PCROFFSET_PID_MEM_INIT [03:03] */
-#define BCHP_XPT_PMU_MEM_INIT_CTRL_PCROFFSET_PID_MEM_INIT_MASK 0x00000008
-#define BCHP_XPT_PMU_MEM_INIT_CTRL_PCROFFSET_PID_MEM_INIT_SHIFT 3
-#define BCHP_XPT_PMU_MEM_INIT_CTRL_PCROFFSET_PID_MEM_INIT_DEFAULT 0x00000000
-
-/* XPT_PMU :: MEM_INIT_CTRL :: PCROFFSET_CFG_MEM_INIT [02:02] */
-#define BCHP_XPT_PMU_MEM_INIT_CTRL_PCROFFSET_CFG_MEM_INIT_MASK 0x00000004
-#define BCHP_XPT_PMU_MEM_INIT_CTRL_PCROFFSET_CFG_MEM_INIT_SHIFT 2
-#define BCHP_XPT_PMU_MEM_INIT_CTRL_PCROFFSET_CFG_MEM_INIT_DEFAULT 0x00000000
-
-/* XPT_PMU :: MEM_INIT_CTRL :: MSG_PID2BUF_MEM_INIT [01:01] */
-#define BCHP_XPT_PMU_MEM_INIT_CTRL_MSG_PID2BUF_MEM_INIT_MASK 0x00000002
-#define BCHP_XPT_PMU_MEM_INIT_CTRL_MSG_PID2BUF_MEM_INIT_SHIFT 1
-#define BCHP_XPT_PMU_MEM_INIT_CTRL_MSG_PID2BUF_MEM_INIT_DEFAULT 0x00000000
-
-/* XPT_PMU :: MEM_INIT_CTRL :: WAKEUP_CFG_MEM_INIT [00:00] */
-#define BCHP_XPT_PMU_MEM_INIT_CTRL_WAKEUP_CFG_MEM_INIT_MASK 0x00000001
-#define BCHP_XPT_PMU_MEM_INIT_CTRL_WAKEUP_CFG_MEM_INIT_SHIFT 0
-#define BCHP_XPT_PMU_MEM_INIT_CTRL_WAKEUP_CFG_MEM_INIT_DEFAULT 0x00000000
-
-/***************************************************************************
- *MEMDMA_SW_INIT_CTRL - Power Management control
- ***************************************************************************/
-/* XPT_PMU :: MEMDMA_SW_INIT_CTRL :: reserved0 [31:02] */
-#define BCHP_XPT_PMU_MEMDMA_SW_INIT_CTRL_reserved0_MASK 0xfffffffc
-#define BCHP_XPT_PMU_MEMDMA_SW_INIT_CTRL_reserved0_SHIFT 2
-
-/* XPT_PMU :: MEMDMA_SW_INIT_CTRL :: PMU_MEMDMA_SW_INIT [01:01] */
-#define BCHP_XPT_PMU_MEMDMA_SW_INIT_CTRL_PMU_MEMDMA_SW_INIT_MASK 0x00000002
-#define BCHP_XPT_PMU_MEMDMA_SW_INIT_CTRL_PMU_MEMDMA_SW_INIT_SHIFT 1
-#define BCHP_XPT_PMU_MEMDMA_SW_INIT_CTRL_PMU_MEMDMA_SW_INIT_DEFAULT 0x00000000
-
-/* XPT_PMU :: MEMDMA_SW_INIT_CTRL :: PMU_MEMDMA_SW_INIT_SEL [00:00] */
-#define BCHP_XPT_PMU_MEMDMA_SW_INIT_CTRL_PMU_MEMDMA_SW_INIT_SEL_MASK 0x00000001
-#define BCHP_XPT_PMU_MEMDMA_SW_INIT_CTRL_PMU_MEMDMA_SW_INIT_SEL_SHIFT 0
-#define BCHP_XPT_PMU_MEMDMA_SW_INIT_CTRL_PMU_MEMDMA_SW_INIT_SEL_DEFAULT 0x00000000
-
-#endif /* #ifndef BCHP_XPT_PMU_H__ */
-
-/* End of File */
diff --git a/include/linux/brcmstb/7366b0/bchp_xpt_security_ns.h b/include/linux/brcmstb/7366b0/bchp_xpt_security_ns.h
deleted file mode 100644
index 6b3753b..0000000
--- a/include/linux/brcmstb/7366b0/bchp_xpt_security_ns.h
+++ /dev/null
@@ -1,593 +0,0 @@
-/***************************************************************************
- * Copyright (c) 1999-2014, Broadcom Corporation
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
- *
- * Module Description:
- * DO NOT EDIT THIS FILE DIRECTLY
- *
- * This module was generated magically with RDB from a source description
- * file. You must edit the source file for changes to be made to this file.
- *
- *
- * Date: Generated on Tue Mar 25 03:12:52 2014
- * Full Compile MD5 Checksum 4593e257971177815cc4a01913c4bcb6
- * (minus title and desc)
- * MD5 Checksum eacd1ac88c53d22793d18644f3aae7d3
- *
- * Compiled with: RDB Utility combo_header.pl
- * RDB Parser 3.0
- * unknown unknown
- * Perl Interpreter 5.008008
- * Operating System linux
- *
- * Revision History:
- *
- * $brcm_Log: $
- *
- ***************************************************************************/
-
-#ifndef BCHP_XPT_SECURITY_NS_H__
-#define BCHP_XPT_SECURITY_NS_H__
-
-/***************************************************************************
- *XPT_SECURITY_NS - XPT_SECURITY_NS Registers
- ***************************************************************************/
-#define BCHP_XPT_SECURITY_NS_S0_BLOCKOUT_COUNT0 0x00380200 /* Streamscram0 Blockout count 0 - RAVE */
-#define BCHP_XPT_SECURITY_NS_S0_BLOCKOUT_COUNT1 0x00380204 /* Streamscram0 Blockout count 1 - RS Buffer */
-#define BCHP_XPT_SECURITY_NS_S0_BLOCKOUT_COUNT2 0x00380208 /* Streamscram0 Blockout count 2 - Playback */
-#define BCHP_XPT_SECURITY_NS_S0_BLOCKOUT_COUNT3 0x0038020c /* Streamscram0 Blockout count 3 - DMA */
-#define BCHP_XPT_SECURITY_NS_S1_BLOCKOUT_COUNT0 0x00380210 /* Streamscram1 Blockout count 0 - RAVE */
-#define BCHP_XPT_SECURITY_NS_S1_BLOCKOUT_COUNT1 0x00380214 /* Streamscram1 Blockout count 1 - RS Buffer */
-#define BCHP_XPT_SECURITY_NS_S1_BLOCKOUT_COUNT2 0x00380218 /* Streamscram1 Blockout count 2 - Playback */
-#define BCHP_XPT_SECURITY_NS_S1_BLOCKOUT_COUNT3 0x0038021c /* Streamscram1 Blockout count 3 - DMA */
-#define BCHP_XPT_SECURITY_NS_BLOCKOUT_CTRL 0x00380220 /* Streamscram0/1 Blockout Control */
-#define BCHP_XPT_SECURITY_NS_WATCHDOG_CTRL 0x00380224 /* Watchdog timer control */
-#define BCHP_XPT_SECURITY_NS_SEC_POWAY_STATUS 0x00380228 /* SEC_POWAY cipher core status */
-#define BCHP_XPT_SECURITY_NS_MAC0_SEMAPHORE 0x0038022c /* semaphore for MAC0 (CMAC/CBCMAC) */
-#define BCHP_XPT_SECURITY_NS_MAC0_0 0x00380230 /* MAC0[31:0] */
-#define BCHP_XPT_SECURITY_NS_MAC0_1 0x00380234 /* MAC0[63:32] */
-#define BCHP_XPT_SECURITY_NS_MAC0_2 0x00380238 /* MAC0[95:64] */
-#define BCHP_XPT_SECURITY_NS_MAC0_3 0x0038023c /* MAC0[127:96] */
-#define BCHP_XPT_SECURITY_NS_MAC1_SEMAPHORE 0x00380240 /* semaphore for MAC1 (CMAC/CBCMAC) */
-#define BCHP_XPT_SECURITY_NS_MAC1_0 0x00380244 /* MAC1[31:0] */
-#define BCHP_XPT_SECURITY_NS_MAC1_1 0x00380248 /* MAC1[63:32] */
-#define BCHP_XPT_SECURITY_NS_MAC1_2 0x0038024c /* MAC1[95:64] */
-#define BCHP_XPT_SECURITY_NS_MAC1_3 0x00380250 /* MAC1[127:96] */
-#define BCHP_XPT_SECURITY_NS_MAC2_SEMAPHORE 0x00380254 /* semaphore for MAC2 (CMAC/CBCMAC) */
-#define BCHP_XPT_SECURITY_NS_MAC2_0 0x00380258 /* MAC2[31:0] */
-#define BCHP_XPT_SECURITY_NS_MAC2_1 0x0038025c /* MAC2[63:32] */
-#define BCHP_XPT_SECURITY_NS_MAC2_2 0x00380260 /* MAC2[95:64] */
-#define BCHP_XPT_SECURITY_NS_MAC2_3 0x00380264 /* MAC2[127:96] */
-#define BCHP_XPT_SECURITY_NS_MAC3_SEMAPHORE 0x00380268 /* semaphore for MAC3 (CMAC/CBCMAC) */
-#define BCHP_XPT_SECURITY_NS_MAC3_0 0x0038026c /* MAC3[31:0] */
-#define BCHP_XPT_SECURITY_NS_MAC3_1 0x00380270 /* MAC3[63:32] */
-#define BCHP_XPT_SECURITY_NS_MAC3_2 0x00380274 /* MAC3[95:64] */
-#define BCHP_XPT_SECURITY_NS_MAC3_3 0x00380278 /* MAC3[127:96] */
-#define BCHP_XPT_SECURITY_NS_SHA20_SEMAPHORE 0x0038027c /* semaphore for SHA20 */
-#define BCHP_XPT_SECURITY_NS_SHA20_CTRL 0x00380280 /* SHA2 Control for Module 0 */
-#define BCHP_XPT_SECURITY_NS_SHA20_0 0x00380284 /* SHA20[31:0] */
-#define BCHP_XPT_SECURITY_NS_SHA20_1 0x00380288 /* SHA20[63:32] */
-#define BCHP_XPT_SECURITY_NS_SHA20_2 0x0038028c /* SHA20[95:64] */
-#define BCHP_XPT_SECURITY_NS_SHA20_3 0x00380290 /* SHA20[127:96] */
-#define BCHP_XPT_SECURITY_NS_SHA20_4 0x00380294 /* SHA20[159:128] */
-#define BCHP_XPT_SECURITY_NS_SHA20_5 0x00380298 /* SHA20[191:160] */
-#define BCHP_XPT_SECURITY_NS_SHA20_6 0x0038029c /* SHA20[223:192] */
-#define BCHP_XPT_SECURITY_NS_SHA20_7 0x003802a0 /* SHA20[255:224] */
-#define BCHP_XPT_SECURITY_NS_SHA21_SEMAPHORE 0x003802a4 /* semaphore for SHA21 */
-#define BCHP_XPT_SECURITY_NS_SHA21_CTRL 0x003802a8 /* SHA2 Control for Module 1 */
-#define BCHP_XPT_SECURITY_NS_SHA21_0 0x003802ac /* SHA21[31:0] */
-#define BCHP_XPT_SECURITY_NS_SHA21_1 0x003802b0 /* SHA21[63:32] */
-#define BCHP_XPT_SECURITY_NS_SHA21_2 0x003802b4 /* SHA21[95:64] */
-#define BCHP_XPT_SECURITY_NS_SHA21_3 0x003802b8 /* SHA21[127:96] */
-#define BCHP_XPT_SECURITY_NS_SHA21_4 0x003802bc /* SHA21[159:128] */
-#define BCHP_XPT_SECURITY_NS_SHA21_5 0x003802c0 /* SHA21[191:160] */
-#define BCHP_XPT_SECURITY_NS_SHA21_6 0x003802c4 /* SHA21[223:192] */
-#define BCHP_XPT_SECURITY_NS_SHA21_7 0x003802c8 /* SHA21[255:224] */
-
-/***************************************************************************
- *S0_BLOCKOUT_COUNT0 - Streamscram0 Blockout count 0 - RAVE
- ***************************************************************************/
-/* XPT_SECURITY_NS :: S0_BLOCKOUT_COUNT0 :: reserved0 [31:16] */
-#define BCHP_XPT_SECURITY_NS_S0_BLOCKOUT_COUNT0_reserved0_MASK 0xffff0000
-#define BCHP_XPT_SECURITY_NS_S0_BLOCKOUT_COUNT0_reserved0_SHIFT 16
-
-/* XPT_SECURITY_NS :: S0_BLOCKOUT_COUNT0 :: BLOCKOUT_COUNT [15:00] */
-#define BCHP_XPT_SECURITY_NS_S0_BLOCKOUT_COUNT0_BLOCKOUT_COUNT_MASK 0x0000ffff
-#define BCHP_XPT_SECURITY_NS_S0_BLOCKOUT_COUNT0_BLOCKOUT_COUNT_SHIFT 0
-#define BCHP_XPT_SECURITY_NS_S0_BLOCKOUT_COUNT0_BLOCKOUT_COUNT_DEFAULT 0x0000032c
-
-/***************************************************************************
- *S0_BLOCKOUT_COUNT1 - Streamscram0 Blockout count 1 - RS Buffer
- ***************************************************************************/
-/* XPT_SECURITY_NS :: S0_BLOCKOUT_COUNT1 :: reserved0 [31:16] */
-#define BCHP_XPT_SECURITY_NS_S0_BLOCKOUT_COUNT1_reserved0_MASK 0xffff0000
-#define BCHP_XPT_SECURITY_NS_S0_BLOCKOUT_COUNT1_reserved0_SHIFT 16
-
-/* XPT_SECURITY_NS :: S0_BLOCKOUT_COUNT1 :: BLOCKOUT_COUNT [15:00] */
-#define BCHP_XPT_SECURITY_NS_S0_BLOCKOUT_COUNT1_BLOCKOUT_COUNT_MASK 0x0000ffff
-#define BCHP_XPT_SECURITY_NS_S0_BLOCKOUT_COUNT1_BLOCKOUT_COUNT_SHIFT 0
-#define BCHP_XPT_SECURITY_NS_S0_BLOCKOUT_COUNT1_BLOCKOUT_COUNT_DEFAULT 0x0000032c
-
-/***************************************************************************
- *S0_BLOCKOUT_COUNT2 - Streamscram0 Blockout count 2 - Playback
- ***************************************************************************/
-/* XPT_SECURITY_NS :: S0_BLOCKOUT_COUNT2 :: reserved0 [31:16] */
-#define BCHP_XPT_SECURITY_NS_S0_BLOCKOUT_COUNT2_reserved0_MASK 0xffff0000
-#define BCHP_XPT_SECURITY_NS_S0_BLOCKOUT_COUNT2_reserved0_SHIFT 16
-
-/* XPT_SECURITY_NS :: S0_BLOCKOUT_COUNT2 :: BLOCKOUT_COUNT [15:00] */
-#define BCHP_XPT_SECURITY_NS_S0_BLOCKOUT_COUNT2_BLOCKOUT_COUNT_MASK 0x0000ffff
-#define BCHP_XPT_SECURITY_NS_S0_BLOCKOUT_COUNT2_BLOCKOUT_COUNT_SHIFT 0
-#define BCHP_XPT_SECURITY_NS_S0_BLOCKOUT_COUNT2_BLOCKOUT_COUNT_DEFAULT 0x0000032c
-
-/***************************************************************************
- *S0_BLOCKOUT_COUNT3 - Streamscram0 Blockout count 3 - DMA
- ***************************************************************************/
-/* XPT_SECURITY_NS :: S0_BLOCKOUT_COUNT3 :: reserved0 [31:16] */
-#define BCHP_XPT_SECURITY_NS_S0_BLOCKOUT_COUNT3_reserved0_MASK 0xffff0000
-#define BCHP_XPT_SECURITY_NS_S0_BLOCKOUT_COUNT3_reserved0_SHIFT 16
-
-/* XPT_SECURITY_NS :: S0_BLOCKOUT_COUNT3 :: BLOCKOUT_COUNT [15:00] */
-#define BCHP_XPT_SECURITY_NS_S0_BLOCKOUT_COUNT3_BLOCKOUT_COUNT_MASK 0x0000ffff
-#define BCHP_XPT_SECURITY_NS_S0_BLOCKOUT_COUNT3_BLOCKOUT_COUNT_SHIFT 0
-#define BCHP_XPT_SECURITY_NS_S0_BLOCKOUT_COUNT3_BLOCKOUT_COUNT_DEFAULT 0x0000032c
-
-/***************************************************************************
- *S1_BLOCKOUT_COUNT0 - Streamscram1 Blockout count 0 - RAVE
- ***************************************************************************/
-/* XPT_SECURITY_NS :: S1_BLOCKOUT_COUNT0 :: reserved0 [31:16] */
-#define BCHP_XPT_SECURITY_NS_S1_BLOCKOUT_COUNT0_reserved0_MASK 0xffff0000
-#define BCHP_XPT_SECURITY_NS_S1_BLOCKOUT_COUNT0_reserved0_SHIFT 16
-
-/* XPT_SECURITY_NS :: S1_BLOCKOUT_COUNT0 :: BLOCKOUT_COUNT [15:00] */
-#define BCHP_XPT_SECURITY_NS_S1_BLOCKOUT_COUNT0_BLOCKOUT_COUNT_MASK 0x0000ffff
-#define BCHP_XPT_SECURITY_NS_S1_BLOCKOUT_COUNT0_BLOCKOUT_COUNT_SHIFT 0
-#define BCHP_XPT_SECURITY_NS_S1_BLOCKOUT_COUNT0_BLOCKOUT_COUNT_DEFAULT 0x0000032c
-
-/***************************************************************************
- *S1_BLOCKOUT_COUNT1 - Streamscram1 Blockout count 1 - RS Buffer
- ***************************************************************************/
-/* XPT_SECURITY_NS :: S1_BLOCKOUT_COUNT1 :: reserved0 [31:16] */
-#define BCHP_XPT_SECURITY_NS_S1_BLOCKOUT_COUNT1_reserved0_MASK 0xffff0000
-#define BCHP_XPT_SECURITY_NS_S1_BLOCKOUT_COUNT1_reserved0_SHIFT 16
-
-/* XPT_SECURITY_NS :: S1_BLOCKOUT_COUNT1 :: BLOCKOUT_COUNT [15:00] */
-#define BCHP_XPT_SECURITY_NS_S1_BLOCKOUT_COUNT1_BLOCKOUT_COUNT_MASK 0x0000ffff
-#define BCHP_XPT_SECURITY_NS_S1_BLOCKOUT_COUNT1_BLOCKOUT_COUNT_SHIFT 0
-#define BCHP_XPT_SECURITY_NS_S1_BLOCKOUT_COUNT1_BLOCKOUT_COUNT_DEFAULT 0x0000032c
-
-/***************************************************************************
- *S1_BLOCKOUT_COUNT2 - Streamscram1 Blockout count 2 - Playback
- ***************************************************************************/
-/* XPT_SECURITY_NS :: S1_BLOCKOUT_COUNT2 :: reserved0 [31:16] */
-#define BCHP_XPT_SECURITY_NS_S1_BLOCKOUT_COUNT2_reserved0_MASK 0xffff0000
-#define BCHP_XPT_SECURITY_NS_S1_BLOCKOUT_COUNT2_reserved0_SHIFT 16
-
-/* XPT_SECURITY_NS :: S1_BLOCKOUT_COUNT2 :: BLOCKOUT_COUNT [15:00] */
-#define BCHP_XPT_SECURITY_NS_S1_BLOCKOUT_COUNT2_BLOCKOUT_COUNT_MASK 0x0000ffff
-#define BCHP_XPT_SECURITY_NS_S1_BLOCKOUT_COUNT2_BLOCKOUT_COUNT_SHIFT 0
-#define BCHP_XPT_SECURITY_NS_S1_BLOCKOUT_COUNT2_BLOCKOUT_COUNT_DEFAULT 0x0000032c
-
-/***************************************************************************
- *S1_BLOCKOUT_COUNT3 - Streamscram1 Blockout count 3 - DMA
- ***************************************************************************/
-/* XPT_SECURITY_NS :: S1_BLOCKOUT_COUNT3 :: reserved0 [31:16] */
-#define BCHP_XPT_SECURITY_NS_S1_BLOCKOUT_COUNT3_reserved0_MASK 0xffff0000
-#define BCHP_XPT_SECURITY_NS_S1_BLOCKOUT_COUNT3_reserved0_SHIFT 16
-
-/* XPT_SECURITY_NS :: S1_BLOCKOUT_COUNT3 :: BLOCKOUT_COUNT [15:00] */
-#define BCHP_XPT_SECURITY_NS_S1_BLOCKOUT_COUNT3_BLOCKOUT_COUNT_MASK 0x0000ffff
-#define BCHP_XPT_SECURITY_NS_S1_BLOCKOUT_COUNT3_BLOCKOUT_COUNT_SHIFT 0
-#define BCHP_XPT_SECURITY_NS_S1_BLOCKOUT_COUNT3_BLOCKOUT_COUNT_DEFAULT 0x0000032c
-
-/***************************************************************************
- *BLOCKOUT_CTRL - Streamscram0/1 Blockout Control
- ***************************************************************************/
-/* XPT_SECURITY_NS :: BLOCKOUT_CTRL :: reserved0 [31:04] */
-#define BCHP_XPT_SECURITY_NS_BLOCKOUT_CTRL_reserved0_MASK 0xfffffff0
-#define BCHP_XPT_SECURITY_NS_BLOCKOUT_CTRL_reserved0_SHIFT 4
-
-/* XPT_SECURITY_NS :: BLOCKOUT_CTRL :: PIPE3_DISALLOW_UNUSED [03:03] */
-#define BCHP_XPT_SECURITY_NS_BLOCKOUT_CTRL_PIPE3_DISALLOW_UNUSED_MASK 0x00000008
-#define BCHP_XPT_SECURITY_NS_BLOCKOUT_CTRL_PIPE3_DISALLOW_UNUSED_SHIFT 3
-#define BCHP_XPT_SECURITY_NS_BLOCKOUT_CTRL_PIPE3_DISALLOW_UNUSED_DEFAULT 0x00000000
-
-/* XPT_SECURITY_NS :: BLOCKOUT_CTRL :: PIPE2_DISALLOW_UNUSED [02:02] */
-#define BCHP_XPT_SECURITY_NS_BLOCKOUT_CTRL_PIPE2_DISALLOW_UNUSED_MASK 0x00000004
-#define BCHP_XPT_SECURITY_NS_BLOCKOUT_CTRL_PIPE2_DISALLOW_UNUSED_SHIFT 2
-#define BCHP_XPT_SECURITY_NS_BLOCKOUT_CTRL_PIPE2_DISALLOW_UNUSED_DEFAULT 0x00000000
-
-/* XPT_SECURITY_NS :: BLOCKOUT_CTRL :: PIPE1_DISALLOW_UNUSED [01:01] */
-#define BCHP_XPT_SECURITY_NS_BLOCKOUT_CTRL_PIPE1_DISALLOW_UNUSED_MASK 0x00000002
-#define BCHP_XPT_SECURITY_NS_BLOCKOUT_CTRL_PIPE1_DISALLOW_UNUSED_SHIFT 1
-#define BCHP_XPT_SECURITY_NS_BLOCKOUT_CTRL_PIPE1_DISALLOW_UNUSED_DEFAULT 0x00000000
-
-/* XPT_SECURITY_NS :: BLOCKOUT_CTRL :: PIPE0_DISALLOW_UNUSED [00:00] */
-#define BCHP_XPT_SECURITY_NS_BLOCKOUT_CTRL_PIPE0_DISALLOW_UNUSED_MASK 0x00000001
-#define BCHP_XPT_SECURITY_NS_BLOCKOUT_CTRL_PIPE0_DISALLOW_UNUSED_SHIFT 0
-#define BCHP_XPT_SECURITY_NS_BLOCKOUT_CTRL_PIPE0_DISALLOW_UNUSED_DEFAULT 0x00000000
-
-/***************************************************************************
- *WATCHDOG_CTRL - Watchdog timer control
- ***************************************************************************/
-/* XPT_SECURITY_NS :: WATCHDOG_CTRL :: reserved0 [31:01] */
-#define BCHP_XPT_SECURITY_NS_WATCHDOG_CTRL_reserved0_MASK 0xfffffffe
-#define BCHP_XPT_SECURITY_NS_WATCHDOG_CTRL_reserved0_SHIFT 1
-
-/* XPT_SECURITY_NS :: WATCHDOG_CTRL :: WATCHDOG_EN [00:00] */
-#define BCHP_XPT_SECURITY_NS_WATCHDOG_CTRL_WATCHDOG_EN_MASK 0x00000001
-#define BCHP_XPT_SECURITY_NS_WATCHDOG_CTRL_WATCHDOG_EN_SHIFT 0
-#define BCHP_XPT_SECURITY_NS_WATCHDOG_CTRL_WATCHDOG_EN_DEFAULT 0x00000001
-
-/***************************************************************************
- *SEC_POWAY_STATUS - SEC_POWAY cipher core status
- ***************************************************************************/
-/* XPT_SECURITY_NS :: SEC_POWAY_STATUS :: SEC_POWAY_STATUS [31:00] */
-#define BCHP_XPT_SECURITY_NS_SEC_POWAY_STATUS_SEC_POWAY_STATUS_MASK 0xffffffff
-#define BCHP_XPT_SECURITY_NS_SEC_POWAY_STATUS_SEC_POWAY_STATUS_SHIFT 0
-
-/***************************************************************************
- *MAC0_SEMAPHORE - semaphore for MAC0 (CMAC/CBCMAC)
- ***************************************************************************/
-/* XPT_SECURITY_NS :: MAC0_SEMAPHORE :: reserved0 [31:08] */
-#define BCHP_XPT_SECURITY_NS_MAC0_SEMAPHORE_reserved0_MASK 0xffffff00
-#define BCHP_XPT_SECURITY_NS_MAC0_SEMAPHORE_reserved0_SHIFT 8
-
-/* XPT_SECURITY_NS :: MAC0_SEMAPHORE :: semaphore_ctrl [07:00] */
-#define BCHP_XPT_SECURITY_NS_MAC0_SEMAPHORE_semaphore_ctrl_MASK 0x000000ff
-#define BCHP_XPT_SECURITY_NS_MAC0_SEMAPHORE_semaphore_ctrl_SHIFT 0
-
-/***************************************************************************
- *MAC0_0 - MAC0[31:0]
- ***************************************************************************/
-/* XPT_SECURITY_NS :: MAC0_0 :: MAC_OUTPUT [31:00] */
-#define BCHP_XPT_SECURITY_NS_MAC0_0_MAC_OUTPUT_MASK 0xffffffff
-#define BCHP_XPT_SECURITY_NS_MAC0_0_MAC_OUTPUT_SHIFT 0
-
-/***************************************************************************
- *MAC0_1 - MAC0[63:32]
- ***************************************************************************/
-/* XPT_SECURITY_NS :: MAC0_1 :: MAC_OUTPUT [31:00] */
-#define BCHP_XPT_SECURITY_NS_MAC0_1_MAC_OUTPUT_MASK 0xffffffff
-#define BCHP_XPT_SECURITY_NS_MAC0_1_MAC_OUTPUT_SHIFT 0
-
-/***************************************************************************
- *MAC0_2 - MAC0[95:64]
- ***************************************************************************/
-/* XPT_SECURITY_NS :: MAC0_2 :: MAC_OUTPUT [31:00] */
-#define BCHP_XPT_SECURITY_NS_MAC0_2_MAC_OUTPUT_MASK 0xffffffff
-#define BCHP_XPT_SECURITY_NS_MAC0_2_MAC_OUTPUT_SHIFT 0
-
-/***************************************************************************
- *MAC0_3 - MAC0[127:96]
- ***************************************************************************/
-/* XPT_SECURITY_NS :: MAC0_3 :: MAC_OUTPUT [31:00] */
-#define BCHP_XPT_SECURITY_NS_MAC0_3_MAC_OUTPUT_MASK 0xffffffff
-#define BCHP_XPT_SECURITY_NS_MAC0_3_MAC_OUTPUT_SHIFT 0
-
-/***************************************************************************
- *MAC1_SEMAPHORE - semaphore for MAC1 (CMAC/CBCMAC)
- ***************************************************************************/
-/* XPT_SECURITY_NS :: MAC1_SEMAPHORE :: reserved0 [31:08] */
-#define BCHP_XPT_SECURITY_NS_MAC1_SEMAPHORE_reserved0_MASK 0xffffff00
-#define BCHP_XPT_SECURITY_NS_MAC1_SEMAPHORE_reserved0_SHIFT 8
-
-/* XPT_SECURITY_NS :: MAC1_SEMAPHORE :: semaphore_ctrl [07:00] */
-#define BCHP_XPT_SECURITY_NS_MAC1_SEMAPHORE_semaphore_ctrl_MASK 0x000000ff
-#define BCHP_XPT_SECURITY_NS_MAC1_SEMAPHORE_semaphore_ctrl_SHIFT 0
-
-/***************************************************************************
- *MAC1_0 - MAC1[31:0]
- ***************************************************************************/
-/* XPT_SECURITY_NS :: MAC1_0 :: MAC_OUTPUT [31:00] */
-#define BCHP_XPT_SECURITY_NS_MAC1_0_MAC_OUTPUT_MASK 0xffffffff
-#define BCHP_XPT_SECURITY_NS_MAC1_0_MAC_OUTPUT_SHIFT 0
-
-/***************************************************************************
- *MAC1_1 - MAC1[63:32]
- ***************************************************************************/
-/* XPT_SECURITY_NS :: MAC1_1 :: MAC_OUTPUT [31:00] */
-#define BCHP_XPT_SECURITY_NS_MAC1_1_MAC_OUTPUT_MASK 0xffffffff
-#define BCHP_XPT_SECURITY_NS_MAC1_1_MAC_OUTPUT_SHIFT 0
-
-/***************************************************************************
- *MAC1_2 - MAC1[95:64]
- ***************************************************************************/
-/* XPT_SECURITY_NS :: MAC1_2 :: MAC_OUTPUT [31:00] */
-#define BCHP_XPT_SECURITY_NS_MAC1_2_MAC_OUTPUT_MASK 0xffffffff
-#define BCHP_XPT_SECURITY_NS_MAC1_2_MAC_OUTPUT_SHIFT 0
-
-/***************************************************************************
- *MAC1_3 - MAC1[127:96]
- ***************************************************************************/
-/* XPT_SECURITY_NS :: MAC1_3 :: MAC_OUTPUT [31:00] */
-#define BCHP_XPT_SECURITY_NS_MAC1_3_MAC_OUTPUT_MASK 0xffffffff
-#define BCHP_XPT_SECURITY_NS_MAC1_3_MAC_OUTPUT_SHIFT 0
-
-/***************************************************************************
- *MAC2_SEMAPHORE - semaphore for MAC2 (CMAC/CBCMAC)
- ***************************************************************************/
-/* XPT_SECURITY_NS :: MAC2_SEMAPHORE :: reserved0 [31:08] */
-#define BCHP_XPT_SECURITY_NS_MAC2_SEMAPHORE_reserved0_MASK 0xffffff00
-#define BCHP_XPT_SECURITY_NS_MAC2_SEMAPHORE_reserved0_SHIFT 8
-
-/* XPT_SECURITY_NS :: MAC2_SEMAPHORE :: semaphore_ctrl [07:00] */
-#define BCHP_XPT_SECURITY_NS_MAC2_SEMAPHORE_semaphore_ctrl_MASK 0x000000ff
-#define BCHP_XPT_SECURITY_NS_MAC2_SEMAPHORE_semaphore_ctrl_SHIFT 0
-
-/***************************************************************************
- *MAC2_0 - MAC2[31:0]
- ***************************************************************************/
-/* XPT_SECURITY_NS :: MAC2_0 :: MAC_OUTPUT [31:00] */
-#define BCHP_XPT_SECURITY_NS_MAC2_0_MAC_OUTPUT_MASK 0xffffffff
-#define BCHP_XPT_SECURITY_NS_MAC2_0_MAC_OUTPUT_SHIFT 0
-
-/***************************************************************************
- *MAC2_1 - MAC2[63:32]
- ***************************************************************************/
-/* XPT_SECURITY_NS :: MAC2_1 :: MAC_OUTPUT [31:00] */
-#define BCHP_XPT_SECURITY_NS_MAC2_1_MAC_OUTPUT_MASK 0xffffffff
-#define BCHP_XPT_SECURITY_NS_MAC2_1_MAC_OUTPUT_SHIFT 0
-
-/***************************************************************************
- *MAC2_2 - MAC2[95:64]
- ***************************************************************************/
-/* XPT_SECURITY_NS :: MAC2_2 :: MAC_OUTPUT [31:00] */
-#define BCHP_XPT_SECURITY_NS_MAC2_2_MAC_OUTPUT_MASK 0xffffffff
-#define BCHP_XPT_SECURITY_NS_MAC2_2_MAC_OUTPUT_SHIFT 0
-
-/***************************************************************************
- *MAC2_3 - MAC2[127:96]
- ***************************************************************************/
-/* XPT_SECURITY_NS :: MAC2_3 :: MAC_OUTPUT [31:00] */
-#define BCHP_XPT_SECURITY_NS_MAC2_3_MAC_OUTPUT_MASK 0xffffffff
-#define BCHP_XPT_SECURITY_NS_MAC2_3_MAC_OUTPUT_SHIFT 0
-
-/***************************************************************************
- *MAC3_SEMAPHORE - semaphore for MAC3 (CMAC/CBCMAC)
- ***************************************************************************/
-/* XPT_SECURITY_NS :: MAC3_SEMAPHORE :: reserved0 [31:08] */
-#define BCHP_XPT_SECURITY_NS_MAC3_SEMAPHORE_reserved0_MASK 0xffffff00
-#define BCHP_XPT_SECURITY_NS_MAC3_SEMAPHORE_reserved0_SHIFT 8
-
-/* XPT_SECURITY_NS :: MAC3_SEMAPHORE :: semaphore_ctrl [07:00] */
-#define BCHP_XPT_SECURITY_NS_MAC3_SEMAPHORE_semaphore_ctrl_MASK 0x000000ff
-#define BCHP_XPT_SECURITY_NS_MAC3_SEMAPHORE_semaphore_ctrl_SHIFT 0
-
-/***************************************************************************
- *MAC3_0 - MAC3[31:0]
- ***************************************************************************/
-/* XPT_SECURITY_NS :: MAC3_0 :: MAC_OUTPUT [31:00] */
-#define BCHP_XPT_SECURITY_NS_MAC3_0_MAC_OUTPUT_MASK 0xffffffff
-#define BCHP_XPT_SECURITY_NS_MAC3_0_MAC_OUTPUT_SHIFT 0
-
-/***************************************************************************
- *MAC3_1 - MAC3[63:32]
- ***************************************************************************/
-/* XPT_SECURITY_NS :: MAC3_1 :: MAC_OUTPUT [31:00] */
-#define BCHP_XPT_SECURITY_NS_MAC3_1_MAC_OUTPUT_MASK 0xffffffff
-#define BCHP_XPT_SECURITY_NS_MAC3_1_MAC_OUTPUT_SHIFT 0
-
-/***************************************************************************
- *MAC3_2 - MAC3[95:64]
- ***************************************************************************/
-/* XPT_SECURITY_NS :: MAC3_2 :: MAC_OUTPUT [31:00] */
-#define BCHP_XPT_SECURITY_NS_MAC3_2_MAC_OUTPUT_MASK 0xffffffff
-#define BCHP_XPT_SECURITY_NS_MAC3_2_MAC_OUTPUT_SHIFT 0
-
-/***************************************************************************
- *MAC3_3 - MAC3[127:96]
- ***************************************************************************/
-/* XPT_SECURITY_NS :: MAC3_3 :: MAC_OUTPUT [31:00] */
-#define BCHP_XPT_SECURITY_NS_MAC3_3_MAC_OUTPUT_MASK 0xffffffff
-#define BCHP_XPT_SECURITY_NS_MAC3_3_MAC_OUTPUT_SHIFT 0
-
-/***************************************************************************
- *SHA20_SEMAPHORE - semaphore for SHA20
- ***************************************************************************/
-/* XPT_SECURITY_NS :: SHA20_SEMAPHORE :: reserved0 [31:08] */
-#define BCHP_XPT_SECURITY_NS_SHA20_SEMAPHORE_reserved0_MASK 0xffffff00
-#define BCHP_XPT_SECURITY_NS_SHA20_SEMAPHORE_reserved0_SHIFT 8
-
-/* XPT_SECURITY_NS :: SHA20_SEMAPHORE :: semaphore_ctrl [07:00] */
-#define BCHP_XPT_SECURITY_NS_SHA20_SEMAPHORE_semaphore_ctrl_MASK 0x000000ff
-#define BCHP_XPT_SECURITY_NS_SHA20_SEMAPHORE_semaphore_ctrl_SHIFT 0
-
-/***************************************************************************
- *SHA20_CTRL - SHA2 Control for Module 0
- ***************************************************************************/
-/* XPT_SECURITY_NS :: SHA20_CTRL :: reserved0 [31:11] */
-#define BCHP_XPT_SECURITY_NS_SHA20_CTRL_reserved0_MASK 0xfffff800
-#define BCHP_XPT_SECURITY_NS_SHA20_CTRL_reserved0_SHIFT 11
-
-/* XPT_SECURITY_NS :: SHA20_CTRL :: PB_BAND [10:10] */
-#define BCHP_XPT_SECURITY_NS_SHA20_CTRL_PB_BAND_MASK 0x00000400
-#define BCHP_XPT_SECURITY_NS_SHA20_CTRL_PB_BAND_SHIFT 10
-#define BCHP_XPT_SECURITY_NS_SHA20_CTRL_PB_BAND_DEFAULT 0x00000000
-
-/* XPT_SECURITY_NS :: SHA20_CTRL :: BAND_NUM [09:03] */
-#define BCHP_XPT_SECURITY_NS_SHA20_CTRL_BAND_NUM_MASK 0x000003f8
-#define BCHP_XPT_SECURITY_NS_SHA20_CTRL_BAND_NUM_SHIFT 3
-#define BCHP_XPT_SECURITY_NS_SHA20_CTRL_BAND_NUM_DEFAULT 0x00000000
-
-/* XPT_SECURITY_NS :: SHA20_CTRL :: SHA2_SEL [02:01] */
-#define BCHP_XPT_SECURITY_NS_SHA20_CTRL_SHA2_SEL_MASK 0x00000006
-#define BCHP_XPT_SECURITY_NS_SHA20_CTRL_SHA2_SEL_SHIFT 1
-#define BCHP_XPT_SECURITY_NS_SHA20_CTRL_SHA2_SEL_DEFAULT 0x00000000
-#define BCHP_XPT_SECURITY_NS_SHA20_CTRL_SHA2_SEL_SHA1 0
-#define BCHP_XPT_SECURITY_NS_SHA20_CTRL_SHA2_SEL_SHA224 1
-#define BCHP_XPT_SECURITY_NS_SHA20_CTRL_SHA2_SEL_SHA256 2
-
-/* XPT_SECURITY_NS :: SHA20_CTRL :: SHA2_EN [00:00] */
-#define BCHP_XPT_SECURITY_NS_SHA20_CTRL_SHA2_EN_MASK 0x00000001
-#define BCHP_XPT_SECURITY_NS_SHA20_CTRL_SHA2_EN_SHIFT 0
-#define BCHP_XPT_SECURITY_NS_SHA20_CTRL_SHA2_EN_DEFAULT 0x00000000
-
-/***************************************************************************
- *SHA20_0 - SHA20[31:0]
- ***************************************************************************/
-/* XPT_SECURITY_NS :: SHA20_0 :: SHA2_OUTPUT [31:00] */
-#define BCHP_XPT_SECURITY_NS_SHA20_0_SHA2_OUTPUT_MASK 0xffffffff
-#define BCHP_XPT_SECURITY_NS_SHA20_0_SHA2_OUTPUT_SHIFT 0
-
-/***************************************************************************
- *SHA20_1 - SHA20[63:32]
- ***************************************************************************/
-/* XPT_SECURITY_NS :: SHA20_1 :: SHA2_OUTPUT [31:00] */
-#define BCHP_XPT_SECURITY_NS_SHA20_1_SHA2_OUTPUT_MASK 0xffffffff
-#define BCHP_XPT_SECURITY_NS_SHA20_1_SHA2_OUTPUT_SHIFT 0
-
-/***************************************************************************
- *SHA20_2 - SHA20[95:64]
- ***************************************************************************/
-/* XPT_SECURITY_NS :: SHA20_2 :: SHA2_OUTPUT [31:00] */
-#define BCHP_XPT_SECURITY_NS_SHA20_2_SHA2_OUTPUT_MASK 0xffffffff
-#define BCHP_XPT_SECURITY_NS_SHA20_2_SHA2_OUTPUT_SHIFT 0
-
-/***************************************************************************
- *SHA20_3 - SHA20[127:96]
- ***************************************************************************/
-/* XPT_SECURITY_NS :: SHA20_3 :: SHA2_OUTPUT [31:00] */
-#define BCHP_XPT_SECURITY_NS_SHA20_3_SHA2_OUTPUT_MASK 0xffffffff
-#define BCHP_XPT_SECURITY_NS_SHA20_3_SHA2_OUTPUT_SHIFT 0
-
-/***************************************************************************
- *SHA20_4 - SHA20[159:128]
- ***************************************************************************/
-/* XPT_SECURITY_NS :: SHA20_4 :: SHA2_OUTPUT [31:00] */
-#define BCHP_XPT_SECURITY_NS_SHA20_4_SHA2_OUTPUT_MASK 0xffffffff
-#define BCHP_XPT_SECURITY_NS_SHA20_4_SHA2_OUTPUT_SHIFT 0
-
-/***************************************************************************
- *SHA20_5 - SHA20[191:160]
- ***************************************************************************/
-/* XPT_SECURITY_NS :: SHA20_5 :: SHA2_OUTPUT [31:00] */
-#define BCHP_XPT_SECURITY_NS_SHA20_5_SHA2_OUTPUT_MASK 0xffffffff
-#define BCHP_XPT_SECURITY_NS_SHA20_5_SHA2_OUTPUT_SHIFT 0
-
-/***************************************************************************
- *SHA20_6 - SHA20[223:192]
- ***************************************************************************/
-/* XPT_SECURITY_NS :: SHA20_6 :: SHA2_OUTPUT [31:00] */
-#define BCHP_XPT_SECURITY_NS_SHA20_6_SHA2_OUTPUT_MASK 0xffffffff
-#define BCHP_XPT_SECURITY_NS_SHA20_6_SHA2_OUTPUT_SHIFT 0
-
-/***************************************************************************
- *SHA20_7 - SHA20[255:224]
- ***************************************************************************/
-/* XPT_SECURITY_NS :: SHA20_7 :: SHA2_OUTPUT [31:00] */
-#define BCHP_XPT_SECURITY_NS_SHA20_7_SHA2_OUTPUT_MASK 0xffffffff
-#define BCHP_XPT_SECURITY_NS_SHA20_7_SHA2_OUTPUT_SHIFT 0
-
-/***************************************************************************
- *SHA21_SEMAPHORE - semaphore for SHA21
- ***************************************************************************/
-/* XPT_SECURITY_NS :: SHA21_SEMAPHORE :: reserved0 [31:08] */
-#define BCHP_XPT_SECURITY_NS_SHA21_SEMAPHORE_reserved0_MASK 0xffffff00
-#define BCHP_XPT_SECURITY_NS_SHA21_SEMAPHORE_reserved0_SHIFT 8
-
-/* XPT_SECURITY_NS :: SHA21_SEMAPHORE :: semaphore_ctrl [07:00] */
-#define BCHP_XPT_SECURITY_NS_SHA21_SEMAPHORE_semaphore_ctrl_MASK 0x000000ff
-#define BCHP_XPT_SECURITY_NS_SHA21_SEMAPHORE_semaphore_ctrl_SHIFT 0
-
-/***************************************************************************
- *SHA21_CTRL - SHA2 Control for Module 1
- ***************************************************************************/
-/* XPT_SECURITY_NS :: SHA21_CTRL :: reserved0 [31:11] */
-#define BCHP_XPT_SECURITY_NS_SHA21_CTRL_reserved0_MASK 0xfffff800
-#define BCHP_XPT_SECURITY_NS_SHA21_CTRL_reserved0_SHIFT 11
-
-/* XPT_SECURITY_NS :: SHA21_CTRL :: PB_BAND [10:10] */
-#define BCHP_XPT_SECURITY_NS_SHA21_CTRL_PB_BAND_MASK 0x00000400
-#define BCHP_XPT_SECURITY_NS_SHA21_CTRL_PB_BAND_SHIFT 10
-#define BCHP_XPT_SECURITY_NS_SHA21_CTRL_PB_BAND_DEFAULT 0x00000000
-
-/* XPT_SECURITY_NS :: SHA21_CTRL :: BAND_NUM [09:03] */
-#define BCHP_XPT_SECURITY_NS_SHA21_CTRL_BAND_NUM_MASK 0x000003f8
-#define BCHP_XPT_SECURITY_NS_SHA21_CTRL_BAND_NUM_SHIFT 3
-#define BCHP_XPT_SECURITY_NS_SHA21_CTRL_BAND_NUM_DEFAULT 0x00000000
-
-/* XPT_SECURITY_NS :: SHA21_CTRL :: SHA2_SEL [02:01] */
-#define BCHP_XPT_SECURITY_NS_SHA21_CTRL_SHA2_SEL_MASK 0x00000006
-#define BCHP_XPT_SECURITY_NS_SHA21_CTRL_SHA2_SEL_SHIFT 1
-#define BCHP_XPT_SECURITY_NS_SHA21_CTRL_SHA2_SEL_DEFAULT 0x00000000
-#define BCHP_XPT_SECURITY_NS_SHA21_CTRL_SHA2_SEL_SHA1 0
-#define BCHP_XPT_SECURITY_NS_SHA21_CTRL_SHA2_SEL_SHA224 1
-#define BCHP_XPT_SECURITY_NS_SHA21_CTRL_SHA2_SEL_SHA256 2
-
-/* XPT_SECURITY_NS :: SHA21_CTRL :: SHA2_EN [00:00] */
-#define BCHP_XPT_SECURITY_NS_SHA21_CTRL_SHA2_EN_MASK 0x00000001
-#define BCHP_XPT_SECURITY_NS_SHA21_CTRL_SHA2_EN_SHIFT 0
-#define BCHP_XPT_SECURITY_NS_SHA21_CTRL_SHA2_EN_DEFAULT 0x00000000
-
-/***************************************************************************
- *SHA21_0 - SHA21[31:0]
- ***************************************************************************/
-/* XPT_SECURITY_NS :: SHA21_0 :: SHA2_OUTPUT [31:00] */
-#define BCHP_XPT_SECURITY_NS_SHA21_0_SHA2_OUTPUT_MASK 0xffffffff
-#define BCHP_XPT_SECURITY_NS_SHA21_0_SHA2_OUTPUT_SHIFT 0
-
-/***************************************************************************
- *SHA21_1 - SHA21[63:32]
- ***************************************************************************/
-/* XPT_SECURITY_NS :: SHA21_1 :: SHA2_OUTPUT [31:00] */
-#define BCHP_XPT_SECURITY_NS_SHA21_1_SHA2_OUTPUT_MASK 0xffffffff
-#define BCHP_XPT_SECURITY_NS_SHA21_1_SHA2_OUTPUT_SHIFT 0
-
-/***************************************************************************
- *SHA21_2 - SHA21[95:64]
- ***************************************************************************/
-/* XPT_SECURITY_NS :: SHA21_2 :: SHA2_OUTPUT [31:00] */
-#define BCHP_XPT_SECURITY_NS_SHA21_2_SHA2_OUTPUT_MASK 0xffffffff
-#define BCHP_XPT_SECURITY_NS_SHA21_2_SHA2_OUTPUT_SHIFT 0
-
-/***************************************************************************
- *SHA21_3 - SHA21[127:96]
- ***************************************************************************/
-/* XPT_SECURITY_NS :: SHA21_3 :: SHA2_OUTPUT [31:00] */
-#define BCHP_XPT_SECURITY_NS_SHA21_3_SHA2_OUTPUT_MASK 0xffffffff
-#define BCHP_XPT_SECURITY_NS_SHA21_3_SHA2_OUTPUT_SHIFT 0
-
-/***************************************************************************
- *SHA21_4 - SHA21[159:128]
- ***************************************************************************/
-/* XPT_SECURITY_NS :: SHA21_4 :: SHA2_OUTPUT [31:00] */
-#define BCHP_XPT_SECURITY_NS_SHA21_4_SHA2_OUTPUT_MASK 0xffffffff
-#define BCHP_XPT_SECURITY_NS_SHA21_4_SHA2_OUTPUT_SHIFT 0
-
-/***************************************************************************
- *SHA21_5 - SHA21[191:160]
- ***************************************************************************/
-/* XPT_SECURITY_NS :: SHA21_5 :: SHA2_OUTPUT [31:00] */
-#define BCHP_XPT_SECURITY_NS_SHA21_5_SHA2_OUTPUT_MASK 0xffffffff
-#define BCHP_XPT_SECURITY_NS_SHA21_5_SHA2_OUTPUT_SHIFT 0
-
-/***************************************************************************
- *SHA21_6 - SHA21[223:192]
- ***************************************************************************/
-/* XPT_SECURITY_NS :: SHA21_6 :: SHA2_OUTPUT [31:00] */
-#define BCHP_XPT_SECURITY_NS_SHA21_6_SHA2_OUTPUT_MASK 0xffffffff
-#define BCHP_XPT_SECURITY_NS_SHA21_6_SHA2_OUTPUT_SHIFT 0
-
-/***************************************************************************
- *SHA21_7 - SHA21[255:224]
- ***************************************************************************/
-/* XPT_SECURITY_NS :: SHA21_7 :: SHA2_OUTPUT [31:00] */
-#define BCHP_XPT_SECURITY_NS_SHA21_7_SHA2_OUTPUT_MASK 0xffffffff
-#define BCHP_XPT_SECURITY_NS_SHA21_7_SHA2_OUTPUT_SHIFT 0
-
-#endif /* #ifndef BCHP_XPT_SECURITY_NS_H__ */
-
-/* End of File */
diff --git a/include/linux/brcmstb/7366b0/bchp_xpt_security_ns_intr2_0.h b/include/linux/brcmstb/7366b0/bchp_xpt_security_ns_intr2_0.h
deleted file mode 100644
index d688eb9..0000000
--- a/include/linux/brcmstb/7366b0/bchp_xpt_security_ns_intr2_0.h
+++ /dev/null
@@ -1,866 +0,0 @@
-/***************************************************************************
- * Copyright (c) 1999-2014, Broadcom Corporation
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
- *
- * Module Description:
- * DO NOT EDIT THIS FILE DIRECTLY
- *
- * This module was generated magically with RDB from a source description
- * file. You must edit the source file for changes to be made to this file.
- *
- *
- * Date: Generated on Tue Mar 25 03:12:55 2014
- * Full Compile MD5 Checksum 4593e257971177815cc4a01913c4bcb6
- * (minus title and desc)
- * MD5 Checksum eacd1ac88c53d22793d18644f3aae7d3
- *
- * Compiled with: RDB Utility combo_header.pl
- * RDB Parser 3.0
- * unknown unknown
- * Perl Interpreter 5.008008
- * Operating System linux
- *
- * Revision History:
- *
- * $brcm_Log: $
- *
- ***************************************************************************/
-
-#ifndef BCHP_XPT_SECURITY_NS_INTR2_0_H__
-#define BCHP_XPT_SECURITY_NS_INTR2_0_H__
-
-/***************************************************************************
- *XPT_SECURITY_NS_INTR2_0 - XPT_SECURITY_NS_INTR2_0 Registers
- ***************************************************************************/
-#define BCHP_XPT_SECURITY_NS_INTR2_0_CPU_STATUS 0x00380080 /* CPU interrupt Status Register */
-#define BCHP_XPT_SECURITY_NS_INTR2_0_CPU_SET 0x00380084 /* CPU interrupt Set Register */
-#define BCHP_XPT_SECURITY_NS_INTR2_0_CPU_CLEAR 0x00380088 /* CPU interrupt Clear Register */
-#define BCHP_XPT_SECURITY_NS_INTR2_0_CPU_MASK_STATUS 0x0038008c /* CPU interrupt Mask Status Register */
-#define BCHP_XPT_SECURITY_NS_INTR2_0_CPU_MASK_SET 0x00380090 /* CPU interrupt Mask Set Register */
-#define BCHP_XPT_SECURITY_NS_INTR2_0_CPU_MASK_CLEAR 0x00380094 /* CPU interrupt Mask Clear Register */
-#define BCHP_XPT_SECURITY_NS_INTR2_0_PCI_STATUS 0x00380098 /* PCI interrupt Status Register */
-#define BCHP_XPT_SECURITY_NS_INTR2_0_PCI_SET 0x0038009c /* PCI interrupt Set Register */
-#define BCHP_XPT_SECURITY_NS_INTR2_0_PCI_CLEAR 0x003800a0 /* PCI interrupt Clear Register */
-#define BCHP_XPT_SECURITY_NS_INTR2_0_PCI_MASK_STATUS 0x003800a4 /* PCI interrupt Mask Status Register */
-#define BCHP_XPT_SECURITY_NS_INTR2_0_PCI_MASK_SET 0x003800a8 /* PCI interrupt Mask Set Register */
-#define BCHP_XPT_SECURITY_NS_INTR2_0_PCI_MASK_CLEAR 0x003800ac /* PCI interrupt Mask Clear Register */
-
-/***************************************************************************
- *CPU_STATUS - CPU interrupt Status Register
- ***************************************************************************/
-/* XPT_SECURITY_NS_INTR2_0 :: CPU_STATUS :: reserved0 [31:12] */
-#define BCHP_XPT_SECURITY_NS_INTR2_0_CPU_STATUS_reserved0_MASK 0xfffff000
-#define BCHP_XPT_SECURITY_NS_INTR2_0_CPU_STATUS_reserved0_SHIFT 12
-
-/* XPT_SECURITY_NS_INTR2_0 :: CPU_STATUS :: SHA21_SEMAPHORE_FREED [11:11] */
-#define BCHP_XPT_SECURITY_NS_INTR2_0_CPU_STATUS_SHA21_SEMAPHORE_FREED_MASK 0x00000800
-#define BCHP_XPT_SECURITY_NS_INTR2_0_CPU_STATUS_SHA21_SEMAPHORE_FREED_SHIFT 11
-#define BCHP_XPT_SECURITY_NS_INTR2_0_CPU_STATUS_SHA21_SEMAPHORE_FREED_DEFAULT 0x00000000
-
-/* XPT_SECURITY_NS_INTR2_0 :: CPU_STATUS :: SHA21_READY [10:10] */
-#define BCHP_XPT_SECURITY_NS_INTR2_0_CPU_STATUS_SHA21_READY_MASK 0x00000400
-#define BCHP_XPT_SECURITY_NS_INTR2_0_CPU_STATUS_SHA21_READY_SHIFT 10
-#define BCHP_XPT_SECURITY_NS_INTR2_0_CPU_STATUS_SHA21_READY_DEFAULT 0x00000000
-
-/* XPT_SECURITY_NS_INTR2_0 :: CPU_STATUS :: SHA20_SEMAPHORE_FREED [09:09] */
-#define BCHP_XPT_SECURITY_NS_INTR2_0_CPU_STATUS_SHA20_SEMAPHORE_FREED_MASK 0x00000200
-#define BCHP_XPT_SECURITY_NS_INTR2_0_CPU_STATUS_SHA20_SEMAPHORE_FREED_SHIFT 9
-#define BCHP_XPT_SECURITY_NS_INTR2_0_CPU_STATUS_SHA20_SEMAPHORE_FREED_DEFAULT 0x00000000
-
-/* XPT_SECURITY_NS_INTR2_0 :: CPU_STATUS :: SHA20_READY [08:08] */
-#define BCHP_XPT_SECURITY_NS_INTR2_0_CPU_STATUS_SHA20_READY_MASK 0x00000100
-#define BCHP_XPT_SECURITY_NS_INTR2_0_CPU_STATUS_SHA20_READY_SHIFT 8
-#define BCHP_XPT_SECURITY_NS_INTR2_0_CPU_STATUS_SHA20_READY_DEFAULT 0x00000000
-
-/* XPT_SECURITY_NS_INTR2_0 :: CPU_STATUS :: MAC3_SEMAPHORE_FREED [07:07] */
-#define BCHP_XPT_SECURITY_NS_INTR2_0_CPU_STATUS_MAC3_SEMAPHORE_FREED_MASK 0x00000080
-#define BCHP_XPT_SECURITY_NS_INTR2_0_CPU_STATUS_MAC3_SEMAPHORE_FREED_SHIFT 7
-#define BCHP_XPT_SECURITY_NS_INTR2_0_CPU_STATUS_MAC3_SEMAPHORE_FREED_DEFAULT 0x00000000
-
-/* XPT_SECURITY_NS_INTR2_0 :: CPU_STATUS :: MAC3_READY [06:06] */
-#define BCHP_XPT_SECURITY_NS_INTR2_0_CPU_STATUS_MAC3_READY_MASK 0x00000040
-#define BCHP_XPT_SECURITY_NS_INTR2_0_CPU_STATUS_MAC3_READY_SHIFT 6
-#define BCHP_XPT_SECURITY_NS_INTR2_0_CPU_STATUS_MAC3_READY_DEFAULT 0x00000000
-
-/* XPT_SECURITY_NS_INTR2_0 :: CPU_STATUS :: MAC2_SEMAPHORE_FREED [05:05] */
-#define BCHP_XPT_SECURITY_NS_INTR2_0_CPU_STATUS_MAC2_SEMAPHORE_FREED_MASK 0x00000020
-#define BCHP_XPT_SECURITY_NS_INTR2_0_CPU_STATUS_MAC2_SEMAPHORE_FREED_SHIFT 5
-#define BCHP_XPT_SECURITY_NS_INTR2_0_CPU_STATUS_MAC2_SEMAPHORE_FREED_DEFAULT 0x00000000
-
-/* XPT_SECURITY_NS_INTR2_0 :: CPU_STATUS :: MAC2_READY [04:04] */
-#define BCHP_XPT_SECURITY_NS_INTR2_0_CPU_STATUS_MAC2_READY_MASK 0x00000010
-#define BCHP_XPT_SECURITY_NS_INTR2_0_CPU_STATUS_MAC2_READY_SHIFT 4
-#define BCHP_XPT_SECURITY_NS_INTR2_0_CPU_STATUS_MAC2_READY_DEFAULT 0x00000000
-
-/* XPT_SECURITY_NS_INTR2_0 :: CPU_STATUS :: MAC1_SEMAPHORE_FREED [03:03] */
-#define BCHP_XPT_SECURITY_NS_INTR2_0_CPU_STATUS_MAC1_SEMAPHORE_FREED_MASK 0x00000008
-#define BCHP_XPT_SECURITY_NS_INTR2_0_CPU_STATUS_MAC1_SEMAPHORE_FREED_SHIFT 3
-#define BCHP_XPT_SECURITY_NS_INTR2_0_CPU_STATUS_MAC1_SEMAPHORE_FREED_DEFAULT 0x00000000
-
-/* XPT_SECURITY_NS_INTR2_0 :: CPU_STATUS :: MAC1_READY [02:02] */
-#define BCHP_XPT_SECURITY_NS_INTR2_0_CPU_STATUS_MAC1_READY_MASK 0x00000004
-#define BCHP_XPT_SECURITY_NS_INTR2_0_CPU_STATUS_MAC1_READY_SHIFT 2
-#define BCHP_XPT_SECURITY_NS_INTR2_0_CPU_STATUS_MAC1_READY_DEFAULT 0x00000000
-
-/* XPT_SECURITY_NS_INTR2_0 :: CPU_STATUS :: MAC0_SEMAPHORE_FREED [01:01] */
-#define BCHP_XPT_SECURITY_NS_INTR2_0_CPU_STATUS_MAC0_SEMAPHORE_FREED_MASK 0x00000002
-#define BCHP_XPT_SECURITY_NS_INTR2_0_CPU_STATUS_MAC0_SEMAPHORE_FREED_SHIFT 1
-#define BCHP_XPT_SECURITY_NS_INTR2_0_CPU_STATUS_MAC0_SEMAPHORE_FREED_DEFAULT 0x00000000
-
-/* XPT_SECURITY_NS_INTR2_0 :: CPU_STATUS :: MAC0_READY [00:00] */
-#define BCHP_XPT_SECURITY_NS_INTR2_0_CPU_STATUS_MAC0_READY_MASK 0x00000001
-#define BCHP_XPT_SECURITY_NS_INTR2_0_CPU_STATUS_MAC0_READY_SHIFT 0
-#define BCHP_XPT_SECURITY_NS_INTR2_0_CPU_STATUS_MAC0_READY_DEFAULT 0x00000000
-
-/***************************************************************************
- *CPU_SET - CPU interrupt Set Register
- ***************************************************************************/
-/* XPT_SECURITY_NS_INTR2_0 :: CPU_SET :: reserved0 [31:12] */
-#define BCHP_XPT_SECURITY_NS_INTR2_0_CPU_SET_reserved0_MASK 0xfffff000
-#define BCHP_XPT_SECURITY_NS_INTR2_0_CPU_SET_reserved0_SHIFT 12
-
-/* XPT_SECURITY_NS_INTR2_0 :: CPU_SET :: SHA21_SEMAPHORE_FREED [11:11] */
-#define BCHP_XPT_SECURITY_NS_INTR2_0_CPU_SET_SHA21_SEMAPHORE_FREED_MASK 0x00000800
-#define BCHP_XPT_SECURITY_NS_INTR2_0_CPU_SET_SHA21_SEMAPHORE_FREED_SHIFT 11
-#define BCHP_XPT_SECURITY_NS_INTR2_0_CPU_SET_SHA21_SEMAPHORE_FREED_DEFAULT 0x00000000
-
-/* XPT_SECURITY_NS_INTR2_0 :: CPU_SET :: SHA21_READY [10:10] */
-#define BCHP_XPT_SECURITY_NS_INTR2_0_CPU_SET_SHA21_READY_MASK 0x00000400
-#define BCHP_XPT_SECURITY_NS_INTR2_0_CPU_SET_SHA21_READY_SHIFT 10
-#define BCHP_XPT_SECURITY_NS_INTR2_0_CPU_SET_SHA21_READY_DEFAULT 0x00000000
-
-/* XPT_SECURITY_NS_INTR2_0 :: CPU_SET :: SHA20_SEMAPHORE_FREED [09:09] */
-#define BCHP_XPT_SECURITY_NS_INTR2_0_CPU_SET_SHA20_SEMAPHORE_FREED_MASK 0x00000200
-#define BCHP_XPT_SECURITY_NS_INTR2_0_CPU_SET_SHA20_SEMAPHORE_FREED_SHIFT 9
-#define BCHP_XPT_SECURITY_NS_INTR2_0_CPU_SET_SHA20_SEMAPHORE_FREED_DEFAULT 0x00000000
-
-/* XPT_SECURITY_NS_INTR2_0 :: CPU_SET :: SHA20_READY [08:08] */
-#define BCHP_XPT_SECURITY_NS_INTR2_0_CPU_SET_SHA20_READY_MASK 0x00000100
-#define BCHP_XPT_SECURITY_NS_INTR2_0_CPU_SET_SHA20_READY_SHIFT 8
-#define BCHP_XPT_SECURITY_NS_INTR2_0_CPU_SET_SHA20_READY_DEFAULT 0x00000000
-
-/* XPT_SECURITY_NS_INTR2_0 :: CPU_SET :: MAC3_SEMAPHORE_FREED [07:07] */
-#define BCHP_XPT_SECURITY_NS_INTR2_0_CPU_SET_MAC3_SEMAPHORE_FREED_MASK 0x00000080
-#define BCHP_XPT_SECURITY_NS_INTR2_0_CPU_SET_MAC3_SEMAPHORE_FREED_SHIFT 7
-#define BCHP_XPT_SECURITY_NS_INTR2_0_CPU_SET_MAC3_SEMAPHORE_FREED_DEFAULT 0x00000000
-
-/* XPT_SECURITY_NS_INTR2_0 :: CPU_SET :: MAC3_READY [06:06] */
-#define BCHP_XPT_SECURITY_NS_INTR2_0_CPU_SET_MAC3_READY_MASK 0x00000040
-#define BCHP_XPT_SECURITY_NS_INTR2_0_CPU_SET_MAC3_READY_SHIFT 6
-#define BCHP_XPT_SECURITY_NS_INTR2_0_CPU_SET_MAC3_READY_DEFAULT 0x00000000
-
-/* XPT_SECURITY_NS_INTR2_0 :: CPU_SET :: MAC2_SEMAPHORE_FREED [05:05] */
-#define BCHP_XPT_SECURITY_NS_INTR2_0_CPU_SET_MAC2_SEMAPHORE_FREED_MASK 0x00000020
-#define BCHP_XPT_SECURITY_NS_INTR2_0_CPU_SET_MAC2_SEMAPHORE_FREED_SHIFT 5
-#define BCHP_XPT_SECURITY_NS_INTR2_0_CPU_SET_MAC2_SEMAPHORE_FREED_DEFAULT 0x00000000
-
-/* XPT_SECURITY_NS_INTR2_0 :: CPU_SET :: MAC2_READY [04:04] */
-#define BCHP_XPT_SECURITY_NS_INTR2_0_CPU_SET_MAC2_READY_MASK 0x00000010
-#define BCHP_XPT_SECURITY_NS_INTR2_0_CPU_SET_MAC2_READY_SHIFT 4
-#define BCHP_XPT_SECURITY_NS_INTR2_0_CPU_SET_MAC2_READY_DEFAULT 0x00000000
-
-/* XPT_SECURITY_NS_INTR2_0 :: CPU_SET :: MAC1_SEMAPHORE_FREED [03:03] */
-#define BCHP_XPT_SECURITY_NS_INTR2_0_CPU_SET_MAC1_SEMAPHORE_FREED_MASK 0x00000008
-#define BCHP_XPT_SECURITY_NS_INTR2_0_CPU_SET_MAC1_SEMAPHORE_FREED_SHIFT 3
-#define BCHP_XPT_SECURITY_NS_INTR2_0_CPU_SET_MAC1_SEMAPHORE_FREED_DEFAULT 0x00000000
-
-/* XPT_SECURITY_NS_INTR2_0 :: CPU_SET :: MAC1_READY [02:02] */
-#define BCHP_XPT_SECURITY_NS_INTR2_0_CPU_SET_MAC1_READY_MASK 0x00000004
-#define BCHP_XPT_SECURITY_NS_INTR2_0_CPU_SET_MAC1_READY_SHIFT 2
-#define BCHP_XPT_SECURITY_NS_INTR2_0_CPU_SET_MAC1_READY_DEFAULT 0x00000000
-
-/* XPT_SECURITY_NS_INTR2_0 :: CPU_SET :: MAC0_SEMAPHORE_FREED [01:01] */
-#define BCHP_XPT_SECURITY_NS_INTR2_0_CPU_SET_MAC0_SEMAPHORE_FREED_MASK 0x00000002
-#define BCHP_XPT_SECURITY_NS_INTR2_0_CPU_SET_MAC0_SEMAPHORE_FREED_SHIFT 1
-#define BCHP_XPT_SECURITY_NS_INTR2_0_CPU_SET_MAC0_SEMAPHORE_FREED_DEFAULT 0x00000000
-
-/* XPT_SECURITY_NS_INTR2_0 :: CPU_SET :: MAC0_READY [00:00] */
-#define BCHP_XPT_SECURITY_NS_INTR2_0_CPU_SET_MAC0_READY_MASK 0x00000001
-#define BCHP_XPT_SECURITY_NS_INTR2_0_CPU_SET_MAC0_READY_SHIFT 0
-#define BCHP_XPT_SECURITY_NS_INTR2_0_CPU_SET_MAC0_READY_DEFAULT 0x00000000
-
-/***************************************************************************
- *CPU_CLEAR - CPU interrupt Clear Register
- ***************************************************************************/
-/* XPT_SECURITY_NS_INTR2_0 :: CPU_CLEAR :: reserved0 [31:12] */
-#define BCHP_XPT_SECURITY_NS_INTR2_0_CPU_CLEAR_reserved0_MASK 0xfffff000
-#define BCHP_XPT_SECURITY_NS_INTR2_0_CPU_CLEAR_reserved0_SHIFT 12
-
-/* XPT_SECURITY_NS_INTR2_0 :: CPU_CLEAR :: SHA21_SEMAPHORE_FREED [11:11] */
-#define BCHP_XPT_SECURITY_NS_INTR2_0_CPU_CLEAR_SHA21_SEMAPHORE_FREED_MASK 0x00000800
-#define BCHP_XPT_SECURITY_NS_INTR2_0_CPU_CLEAR_SHA21_SEMAPHORE_FREED_SHIFT 11
-#define BCHP_XPT_SECURITY_NS_INTR2_0_CPU_CLEAR_SHA21_SEMAPHORE_FREED_DEFAULT 0x00000000
-
-/* XPT_SECURITY_NS_INTR2_0 :: CPU_CLEAR :: SHA21_READY [10:10] */
-#define BCHP_XPT_SECURITY_NS_INTR2_0_CPU_CLEAR_SHA21_READY_MASK 0x00000400
-#define BCHP_XPT_SECURITY_NS_INTR2_0_CPU_CLEAR_SHA21_READY_SHIFT 10
-#define BCHP_XPT_SECURITY_NS_INTR2_0_CPU_CLEAR_SHA21_READY_DEFAULT 0x00000000
-
-/* XPT_SECURITY_NS_INTR2_0 :: CPU_CLEAR :: SHA20_SEMAPHORE_FREED [09:09] */
-#define BCHP_XPT_SECURITY_NS_INTR2_0_CPU_CLEAR_SHA20_SEMAPHORE_FREED_MASK 0x00000200
-#define BCHP_XPT_SECURITY_NS_INTR2_0_CPU_CLEAR_SHA20_SEMAPHORE_FREED_SHIFT 9
-#define BCHP_XPT_SECURITY_NS_INTR2_0_CPU_CLEAR_SHA20_SEMAPHORE_FREED_DEFAULT 0x00000000
-
-/* XPT_SECURITY_NS_INTR2_0 :: CPU_CLEAR :: SHA20_READY [08:08] */
-#define BCHP_XPT_SECURITY_NS_INTR2_0_CPU_CLEAR_SHA20_READY_MASK 0x00000100
-#define BCHP_XPT_SECURITY_NS_INTR2_0_CPU_CLEAR_SHA20_READY_SHIFT 8
-#define BCHP_XPT_SECURITY_NS_INTR2_0_CPU_CLEAR_SHA20_READY_DEFAULT 0x00000000
-
-/* XPT_SECURITY_NS_INTR2_0 :: CPU_CLEAR :: MAC3_SEMAPHORE_FREED [07:07] */
-#define BCHP_XPT_SECURITY_NS_INTR2_0_CPU_CLEAR_MAC3_SEMAPHORE_FREED_MASK 0x00000080
-#define BCHP_XPT_SECURITY_NS_INTR2_0_CPU_CLEAR_MAC3_SEMAPHORE_FREED_SHIFT 7
-#define BCHP_XPT_SECURITY_NS_INTR2_0_CPU_CLEAR_MAC3_SEMAPHORE_FREED_DEFAULT 0x00000000
-
-/* XPT_SECURITY_NS_INTR2_0 :: CPU_CLEAR :: MAC3_READY [06:06] */
-#define BCHP_XPT_SECURITY_NS_INTR2_0_CPU_CLEAR_MAC3_READY_MASK 0x00000040
-#define BCHP_XPT_SECURITY_NS_INTR2_0_CPU_CLEAR_MAC3_READY_SHIFT 6
-#define BCHP_XPT_SECURITY_NS_INTR2_0_CPU_CLEAR_MAC3_READY_DEFAULT 0x00000000
-
-/* XPT_SECURITY_NS_INTR2_0 :: CPU_CLEAR :: MAC2_SEMAPHORE_FREED [05:05] */
-#define BCHP_XPT_SECURITY_NS_INTR2_0_CPU_CLEAR_MAC2_SEMAPHORE_FREED_MASK 0x00000020
-#define BCHP_XPT_SECURITY_NS_INTR2_0_CPU_CLEAR_MAC2_SEMAPHORE_FREED_SHIFT 5
-#define BCHP_XPT_SECURITY_NS_INTR2_0_CPU_CLEAR_MAC2_SEMAPHORE_FREED_DEFAULT 0x00000000
-
-/* XPT_SECURITY_NS_INTR2_0 :: CPU_CLEAR :: MAC2_READY [04:04] */
-#define BCHP_XPT_SECURITY_NS_INTR2_0_CPU_CLEAR_MAC2_READY_MASK 0x00000010
-#define BCHP_XPT_SECURITY_NS_INTR2_0_CPU_CLEAR_MAC2_READY_SHIFT 4
-#define BCHP_XPT_SECURITY_NS_INTR2_0_CPU_CLEAR_MAC2_READY_DEFAULT 0x00000000
-
-/* XPT_SECURITY_NS_INTR2_0 :: CPU_CLEAR :: MAC1_SEMAPHORE_FREED [03:03] */
-#define BCHP_XPT_SECURITY_NS_INTR2_0_CPU_CLEAR_MAC1_SEMAPHORE_FREED_MASK 0x00000008
-#define BCHP_XPT_SECURITY_NS_INTR2_0_CPU_CLEAR_MAC1_SEMAPHORE_FREED_SHIFT 3
-#define BCHP_XPT_SECURITY_NS_INTR2_0_CPU_CLEAR_MAC1_SEMAPHORE_FREED_DEFAULT 0x00000000
-
-/* XPT_SECURITY_NS_INTR2_0 :: CPU_CLEAR :: MAC1_READY [02:02] */
-#define BCHP_XPT_SECURITY_NS_INTR2_0_CPU_CLEAR_MAC1_READY_MASK 0x00000004
-#define BCHP_XPT_SECURITY_NS_INTR2_0_CPU_CLEAR_MAC1_READY_SHIFT 2
-#define BCHP_XPT_SECURITY_NS_INTR2_0_CPU_CLEAR_MAC1_READY_DEFAULT 0x00000000
-
-/* XPT_SECURITY_NS_INTR2_0 :: CPU_CLEAR :: MAC0_SEMAPHORE_FREED [01:01] */
-#define BCHP_XPT_SECURITY_NS_INTR2_0_CPU_CLEAR_MAC0_SEMAPHORE_FREED_MASK 0x00000002
-#define BCHP_XPT_SECURITY_NS_INTR2_0_CPU_CLEAR_MAC0_SEMAPHORE_FREED_SHIFT 1
-#define BCHP_XPT_SECURITY_NS_INTR2_0_CPU_CLEAR_MAC0_SEMAPHORE_FREED_DEFAULT 0x00000000
-
-/* XPT_SECURITY_NS_INTR2_0 :: CPU_CLEAR :: MAC0_READY [00:00] */
-#define BCHP_XPT_SECURITY_NS_INTR2_0_CPU_CLEAR_MAC0_READY_MASK 0x00000001
-#define BCHP_XPT_SECURITY_NS_INTR2_0_CPU_CLEAR_MAC0_READY_SHIFT 0
-#define BCHP_XPT_SECURITY_NS_INTR2_0_CPU_CLEAR_MAC0_READY_DEFAULT 0x00000000
-
-/***************************************************************************
- *CPU_MASK_STATUS - CPU interrupt Mask Status Register
- ***************************************************************************/
-/* XPT_SECURITY_NS_INTR2_0 :: CPU_MASK_STATUS :: reserved0 [31:12] */
-#define BCHP_XPT_SECURITY_NS_INTR2_0_CPU_MASK_STATUS_reserved0_MASK 0xfffff000
-#define BCHP_XPT_SECURITY_NS_INTR2_0_CPU_MASK_STATUS_reserved0_SHIFT 12
-
-/* XPT_SECURITY_NS_INTR2_0 :: CPU_MASK_STATUS :: SHA21_SEMAPHORE_FREED [11:11] */
-#define BCHP_XPT_SECURITY_NS_INTR2_0_CPU_MASK_STATUS_SHA21_SEMAPHORE_FREED_MASK 0x00000800
-#define BCHP_XPT_SECURITY_NS_INTR2_0_CPU_MASK_STATUS_SHA21_SEMAPHORE_FREED_SHIFT 11
-#define BCHP_XPT_SECURITY_NS_INTR2_0_CPU_MASK_STATUS_SHA21_SEMAPHORE_FREED_DEFAULT 0x00000000
-
-/* XPT_SECURITY_NS_INTR2_0 :: CPU_MASK_STATUS :: SHA21_READY [10:10] */
-#define BCHP_XPT_SECURITY_NS_INTR2_0_CPU_MASK_STATUS_SHA21_READY_MASK 0x00000400
-#define BCHP_XPT_SECURITY_NS_INTR2_0_CPU_MASK_STATUS_SHA21_READY_SHIFT 10
-#define BCHP_XPT_SECURITY_NS_INTR2_0_CPU_MASK_STATUS_SHA21_READY_DEFAULT 0x00000000
-
-/* XPT_SECURITY_NS_INTR2_0 :: CPU_MASK_STATUS :: SHA20_SEMAPHORE_FREED [09:09] */
-#define BCHP_XPT_SECURITY_NS_INTR2_0_CPU_MASK_STATUS_SHA20_SEMAPHORE_FREED_MASK 0x00000200
-#define BCHP_XPT_SECURITY_NS_INTR2_0_CPU_MASK_STATUS_SHA20_SEMAPHORE_FREED_SHIFT 9
-#define BCHP_XPT_SECURITY_NS_INTR2_0_CPU_MASK_STATUS_SHA20_SEMAPHORE_FREED_DEFAULT 0x00000000
-
-/* XPT_SECURITY_NS_INTR2_0 :: CPU_MASK_STATUS :: SHA20_READY [08:08] */
-#define BCHP_XPT_SECURITY_NS_INTR2_0_CPU_MASK_STATUS_SHA20_READY_MASK 0x00000100
-#define BCHP_XPT_SECURITY_NS_INTR2_0_CPU_MASK_STATUS_SHA20_READY_SHIFT 8
-#define BCHP_XPT_SECURITY_NS_INTR2_0_CPU_MASK_STATUS_SHA20_READY_DEFAULT 0x00000000
-
-/* XPT_SECURITY_NS_INTR2_0 :: CPU_MASK_STATUS :: MAC3_SEMAPHORE_FREED [07:07] */
-#define BCHP_XPT_SECURITY_NS_INTR2_0_CPU_MASK_STATUS_MAC3_SEMAPHORE_FREED_MASK 0x00000080
-#define BCHP_XPT_SECURITY_NS_INTR2_0_CPU_MASK_STATUS_MAC3_SEMAPHORE_FREED_SHIFT 7
-#define BCHP_XPT_SECURITY_NS_INTR2_0_CPU_MASK_STATUS_MAC3_SEMAPHORE_FREED_DEFAULT 0x00000000
-
-/* XPT_SECURITY_NS_INTR2_0 :: CPU_MASK_STATUS :: MAC3_READY [06:06] */
-#define BCHP_XPT_SECURITY_NS_INTR2_0_CPU_MASK_STATUS_MAC3_READY_MASK 0x00000040
-#define BCHP_XPT_SECURITY_NS_INTR2_0_CPU_MASK_STATUS_MAC3_READY_SHIFT 6
-#define BCHP_XPT_SECURITY_NS_INTR2_0_CPU_MASK_STATUS_MAC3_READY_DEFAULT 0x00000000
-
-/* XPT_SECURITY_NS_INTR2_0 :: CPU_MASK_STATUS :: MAC2_SEMAPHORE_FREED [05:05] */
-#define BCHP_XPT_SECURITY_NS_INTR2_0_CPU_MASK_STATUS_MAC2_SEMAPHORE_FREED_MASK 0x00000020
-#define BCHP_XPT_SECURITY_NS_INTR2_0_CPU_MASK_STATUS_MAC2_SEMAPHORE_FREED_SHIFT 5
-#define BCHP_XPT_SECURITY_NS_INTR2_0_CPU_MASK_STATUS_MAC2_SEMAPHORE_FREED_DEFAULT 0x00000000
-
-/* XPT_SECURITY_NS_INTR2_0 :: CPU_MASK_STATUS :: MAC2_READY [04:04] */
-#define BCHP_XPT_SECURITY_NS_INTR2_0_CPU_MASK_STATUS_MAC2_READY_MASK 0x00000010
-#define BCHP_XPT_SECURITY_NS_INTR2_0_CPU_MASK_STATUS_MAC2_READY_SHIFT 4
-#define BCHP_XPT_SECURITY_NS_INTR2_0_CPU_MASK_STATUS_MAC2_READY_DEFAULT 0x00000000
-
-/* XPT_SECURITY_NS_INTR2_0 :: CPU_MASK_STATUS :: MAC1_SEMAPHORE_FREED [03:03] */
-#define BCHP_XPT_SECURITY_NS_INTR2_0_CPU_MASK_STATUS_MAC1_SEMAPHORE_FREED_MASK 0x00000008
-#define BCHP_XPT_SECURITY_NS_INTR2_0_CPU_MASK_STATUS_MAC1_SEMAPHORE_FREED_SHIFT 3
-#define BCHP_XPT_SECURITY_NS_INTR2_0_CPU_MASK_STATUS_MAC1_SEMAPHORE_FREED_DEFAULT 0x00000000
-
-/* XPT_SECURITY_NS_INTR2_0 :: CPU_MASK_STATUS :: MAC1_READY [02:02] */
-#define BCHP_XPT_SECURITY_NS_INTR2_0_CPU_MASK_STATUS_MAC1_READY_MASK 0x00000004
-#define BCHP_XPT_SECURITY_NS_INTR2_0_CPU_MASK_STATUS_MAC1_READY_SHIFT 2
-#define BCHP_XPT_SECURITY_NS_INTR2_0_CPU_MASK_STATUS_MAC1_READY_DEFAULT 0x00000000
-
-/* XPT_SECURITY_NS_INTR2_0 :: CPU_MASK_STATUS :: MAC0_SEMAPHORE_FREED [01:01] */
-#define BCHP_XPT_SECURITY_NS_INTR2_0_CPU_MASK_STATUS_MAC0_SEMAPHORE_FREED_MASK 0x00000002
-#define BCHP_XPT_SECURITY_NS_INTR2_0_CPU_MASK_STATUS_MAC0_SEMAPHORE_FREED_SHIFT 1
-#define BCHP_XPT_SECURITY_NS_INTR2_0_CPU_MASK_STATUS_MAC0_SEMAPHORE_FREED_DEFAULT 0x00000000
-
-/* XPT_SECURITY_NS_INTR2_0 :: CPU_MASK_STATUS :: MAC0_READY [00:00] */
-#define BCHP_XPT_SECURITY_NS_INTR2_0_CPU_MASK_STATUS_MAC0_READY_MASK 0x00000001
-#define BCHP_XPT_SECURITY_NS_INTR2_0_CPU_MASK_STATUS_MAC0_READY_SHIFT 0
-#define BCHP_XPT_SECURITY_NS_INTR2_0_CPU_MASK_STATUS_MAC0_READY_DEFAULT 0x00000000
-
-/***************************************************************************
- *CPU_MASK_SET - CPU interrupt Mask Set Register
- ***************************************************************************/
-/* XPT_SECURITY_NS_INTR2_0 :: CPU_MASK_SET :: reserved0 [31:12] */
-#define BCHP_XPT_SECURITY_NS_INTR2_0_CPU_MASK_SET_reserved0_MASK 0xfffff000
-#define BCHP_XPT_SECURITY_NS_INTR2_0_CPU_MASK_SET_reserved0_SHIFT 12
-
-/* XPT_SECURITY_NS_INTR2_0 :: CPU_MASK_SET :: SHA21_SEMAPHORE_FREED [11:11] */
-#define BCHP_XPT_SECURITY_NS_INTR2_0_CPU_MASK_SET_SHA21_SEMAPHORE_FREED_MASK 0x00000800
-#define BCHP_XPT_SECURITY_NS_INTR2_0_CPU_MASK_SET_SHA21_SEMAPHORE_FREED_SHIFT 11
-#define BCHP_XPT_SECURITY_NS_INTR2_0_CPU_MASK_SET_SHA21_SEMAPHORE_FREED_DEFAULT 0x00000000
-
-/* XPT_SECURITY_NS_INTR2_0 :: CPU_MASK_SET :: SHA21_READY [10:10] */
-#define BCHP_XPT_SECURITY_NS_INTR2_0_CPU_MASK_SET_SHA21_READY_MASK 0x00000400
-#define BCHP_XPT_SECURITY_NS_INTR2_0_CPU_MASK_SET_SHA21_READY_SHIFT 10
-#define BCHP_XPT_SECURITY_NS_INTR2_0_CPU_MASK_SET_SHA21_READY_DEFAULT 0x00000000
-
-/* XPT_SECURITY_NS_INTR2_0 :: CPU_MASK_SET :: SHA20_SEMAPHORE_FREED [09:09] */
-#define BCHP_XPT_SECURITY_NS_INTR2_0_CPU_MASK_SET_SHA20_SEMAPHORE_FREED_MASK 0x00000200
-#define BCHP_XPT_SECURITY_NS_INTR2_0_CPU_MASK_SET_SHA20_SEMAPHORE_FREED_SHIFT 9
-#define BCHP_XPT_SECURITY_NS_INTR2_0_CPU_MASK_SET_SHA20_SEMAPHORE_FREED_DEFAULT 0x00000000
-
-/* XPT_SECURITY_NS_INTR2_0 :: CPU_MASK_SET :: SHA20_READY [08:08] */
-#define BCHP_XPT_SECURITY_NS_INTR2_0_CPU_MASK_SET_SHA20_READY_MASK 0x00000100
-#define BCHP_XPT_SECURITY_NS_INTR2_0_CPU_MASK_SET_SHA20_READY_SHIFT 8
-#define BCHP_XPT_SECURITY_NS_INTR2_0_CPU_MASK_SET_SHA20_READY_DEFAULT 0x00000000
-
-/* XPT_SECURITY_NS_INTR2_0 :: CPU_MASK_SET :: MAC3_SEMAPHORE_FREED [07:07] */
-#define BCHP_XPT_SECURITY_NS_INTR2_0_CPU_MASK_SET_MAC3_SEMAPHORE_FREED_MASK 0x00000080
-#define BCHP_XPT_SECURITY_NS_INTR2_0_CPU_MASK_SET_MAC3_SEMAPHORE_FREED_SHIFT 7
-#define BCHP_XPT_SECURITY_NS_INTR2_0_CPU_MASK_SET_MAC3_SEMAPHORE_FREED_DEFAULT 0x00000000
-
-/* XPT_SECURITY_NS_INTR2_0 :: CPU_MASK_SET :: MAC3_READY [06:06] */
-#define BCHP_XPT_SECURITY_NS_INTR2_0_CPU_MASK_SET_MAC3_READY_MASK 0x00000040
-#define BCHP_XPT_SECURITY_NS_INTR2_0_CPU_MASK_SET_MAC3_READY_SHIFT 6
-#define BCHP_XPT_SECURITY_NS_INTR2_0_CPU_MASK_SET_MAC3_READY_DEFAULT 0x00000000
-
-/* XPT_SECURITY_NS_INTR2_0 :: CPU_MASK_SET :: MAC2_SEMAPHORE_FREED [05:05] */
-#define BCHP_XPT_SECURITY_NS_INTR2_0_CPU_MASK_SET_MAC2_SEMAPHORE_FREED_MASK 0x00000020
-#define BCHP_XPT_SECURITY_NS_INTR2_0_CPU_MASK_SET_MAC2_SEMAPHORE_FREED_SHIFT 5
-#define BCHP_XPT_SECURITY_NS_INTR2_0_CPU_MASK_SET_MAC2_SEMAPHORE_FREED_DEFAULT 0x00000000
-
-/* XPT_SECURITY_NS_INTR2_0 :: CPU_MASK_SET :: MAC2_READY [04:04] */
-#define BCHP_XPT_SECURITY_NS_INTR2_0_CPU_MASK_SET_MAC2_READY_MASK 0x00000010
-#define BCHP_XPT_SECURITY_NS_INTR2_0_CPU_MASK_SET_MAC2_READY_SHIFT 4
-#define BCHP_XPT_SECURITY_NS_INTR2_0_CPU_MASK_SET_MAC2_READY_DEFAULT 0x00000000
-
-/* XPT_SECURITY_NS_INTR2_0 :: CPU_MASK_SET :: MAC1_SEMAPHORE_FREED [03:03] */
-#define BCHP_XPT_SECURITY_NS_INTR2_0_CPU_MASK_SET_MAC1_SEMAPHORE_FREED_MASK 0x00000008
-#define BCHP_XPT_SECURITY_NS_INTR2_0_CPU_MASK_SET_MAC1_SEMAPHORE_FREED_SHIFT 3
-#define BCHP_XPT_SECURITY_NS_INTR2_0_CPU_MASK_SET_MAC1_SEMAPHORE_FREED_DEFAULT 0x00000000
-
-/* XPT_SECURITY_NS_INTR2_0 :: CPU_MASK_SET :: MAC1_READY [02:02] */
-#define BCHP_XPT_SECURITY_NS_INTR2_0_CPU_MASK_SET_MAC1_READY_MASK 0x00000004
-#define BCHP_XPT_SECURITY_NS_INTR2_0_CPU_MASK_SET_MAC1_READY_SHIFT 2
-#define BCHP_XPT_SECURITY_NS_INTR2_0_CPU_MASK_SET_MAC1_READY_DEFAULT 0x00000000
-
-/* XPT_SECURITY_NS_INTR2_0 :: CPU_MASK_SET :: MAC0_SEMAPHORE_FREED [01:01] */
-#define BCHP_XPT_SECURITY_NS_INTR2_0_CPU_MASK_SET_MAC0_SEMAPHORE_FREED_MASK 0x00000002
-#define BCHP_XPT_SECURITY_NS_INTR2_0_CPU_MASK_SET_MAC0_SEMAPHORE_FREED_SHIFT 1
-#define BCHP_XPT_SECURITY_NS_INTR2_0_CPU_MASK_SET_MAC0_SEMAPHORE_FREED_DEFAULT 0x00000000
-
-/* XPT_SECURITY_NS_INTR2_0 :: CPU_MASK_SET :: MAC0_READY [00:00] */
-#define BCHP_XPT_SECURITY_NS_INTR2_0_CPU_MASK_SET_MAC0_READY_MASK 0x00000001
-#define BCHP_XPT_SECURITY_NS_INTR2_0_CPU_MASK_SET_MAC0_READY_SHIFT 0
-#define BCHP_XPT_SECURITY_NS_INTR2_0_CPU_MASK_SET_MAC0_READY_DEFAULT 0x00000000
-
-/***************************************************************************
- *CPU_MASK_CLEAR - CPU interrupt Mask Clear Register
- ***************************************************************************/
-/* XPT_SECURITY_NS_INTR2_0 :: CPU_MASK_CLEAR :: reserved0 [31:12] */
-#define BCHP_XPT_SECURITY_NS_INTR2_0_CPU_MASK_CLEAR_reserved0_MASK 0xfffff000
-#define BCHP_XPT_SECURITY_NS_INTR2_0_CPU_MASK_CLEAR_reserved0_SHIFT 12
-
-/* XPT_SECURITY_NS_INTR2_0 :: CPU_MASK_CLEAR :: SHA21_SEMAPHORE_FREED [11:11] */
-#define BCHP_XPT_SECURITY_NS_INTR2_0_CPU_MASK_CLEAR_SHA21_SEMAPHORE_FREED_MASK 0x00000800
-#define BCHP_XPT_SECURITY_NS_INTR2_0_CPU_MASK_CLEAR_SHA21_SEMAPHORE_FREED_SHIFT 11
-#define BCHP_XPT_SECURITY_NS_INTR2_0_CPU_MASK_CLEAR_SHA21_SEMAPHORE_FREED_DEFAULT 0x00000000
-
-/* XPT_SECURITY_NS_INTR2_0 :: CPU_MASK_CLEAR :: SHA21_READY [10:10] */
-#define BCHP_XPT_SECURITY_NS_INTR2_0_CPU_MASK_CLEAR_SHA21_READY_MASK 0x00000400
-#define BCHP_XPT_SECURITY_NS_INTR2_0_CPU_MASK_CLEAR_SHA21_READY_SHIFT 10
-#define BCHP_XPT_SECURITY_NS_INTR2_0_CPU_MASK_CLEAR_SHA21_READY_DEFAULT 0x00000000
-
-/* XPT_SECURITY_NS_INTR2_0 :: CPU_MASK_CLEAR :: SHA20_SEMAPHORE_FREED [09:09] */
-#define BCHP_XPT_SECURITY_NS_INTR2_0_CPU_MASK_CLEAR_SHA20_SEMAPHORE_FREED_MASK 0x00000200
-#define BCHP_XPT_SECURITY_NS_INTR2_0_CPU_MASK_CLEAR_SHA20_SEMAPHORE_FREED_SHIFT 9
-#define BCHP_XPT_SECURITY_NS_INTR2_0_CPU_MASK_CLEAR_SHA20_SEMAPHORE_FREED_DEFAULT 0x00000000
-
-/* XPT_SECURITY_NS_INTR2_0 :: CPU_MASK_CLEAR :: SHA20_READY [08:08] */
-#define BCHP_XPT_SECURITY_NS_INTR2_0_CPU_MASK_CLEAR_SHA20_READY_MASK 0x00000100
-#define BCHP_XPT_SECURITY_NS_INTR2_0_CPU_MASK_CLEAR_SHA20_READY_SHIFT 8
-#define BCHP_XPT_SECURITY_NS_INTR2_0_CPU_MASK_CLEAR_SHA20_READY_DEFAULT 0x00000000
-
-/* XPT_SECURITY_NS_INTR2_0 :: CPU_MASK_CLEAR :: MAC3_SEMAPHORE_FREED [07:07] */
-#define BCHP_XPT_SECURITY_NS_INTR2_0_CPU_MASK_CLEAR_MAC3_SEMAPHORE_FREED_MASK 0x00000080
-#define BCHP_XPT_SECURITY_NS_INTR2_0_CPU_MASK_CLEAR_MAC3_SEMAPHORE_FREED_SHIFT 7
-#define BCHP_XPT_SECURITY_NS_INTR2_0_CPU_MASK_CLEAR_MAC3_SEMAPHORE_FREED_DEFAULT 0x00000000
-
-/* XPT_SECURITY_NS_INTR2_0 :: CPU_MASK_CLEAR :: MAC3_READY [06:06] */
-#define BCHP_XPT_SECURITY_NS_INTR2_0_CPU_MASK_CLEAR_MAC3_READY_MASK 0x00000040
-#define BCHP_XPT_SECURITY_NS_INTR2_0_CPU_MASK_CLEAR_MAC3_READY_SHIFT 6
-#define BCHP_XPT_SECURITY_NS_INTR2_0_CPU_MASK_CLEAR_MAC3_READY_DEFAULT 0x00000000
-
-/* XPT_SECURITY_NS_INTR2_0 :: CPU_MASK_CLEAR :: MAC2_SEMAPHORE_FREED [05:05] */
-#define BCHP_XPT_SECURITY_NS_INTR2_0_CPU_MASK_CLEAR_MAC2_SEMAPHORE_FREED_MASK 0x00000020
-#define BCHP_XPT_SECURITY_NS_INTR2_0_CPU_MASK_CLEAR_MAC2_SEMAPHORE_FREED_SHIFT 5
-#define BCHP_XPT_SECURITY_NS_INTR2_0_CPU_MASK_CLEAR_MAC2_SEMAPHORE_FREED_DEFAULT 0x00000000
-
-/* XPT_SECURITY_NS_INTR2_0 :: CPU_MASK_CLEAR :: MAC2_READY [04:04] */
-#define BCHP_XPT_SECURITY_NS_INTR2_0_CPU_MASK_CLEAR_MAC2_READY_MASK 0x00000010
-#define BCHP_XPT_SECURITY_NS_INTR2_0_CPU_MASK_CLEAR_MAC2_READY_SHIFT 4
-#define BCHP_XPT_SECURITY_NS_INTR2_0_CPU_MASK_CLEAR_MAC2_READY_DEFAULT 0x00000000
-
-/* XPT_SECURITY_NS_INTR2_0 :: CPU_MASK_CLEAR :: MAC1_SEMAPHORE_FREED [03:03] */
-#define BCHP_XPT_SECURITY_NS_INTR2_0_CPU_MASK_CLEAR_MAC1_SEMAPHORE_FREED_MASK 0x00000008
-#define BCHP_XPT_SECURITY_NS_INTR2_0_CPU_MASK_CLEAR_MAC1_SEMAPHORE_FREED_SHIFT 3
-#define BCHP_XPT_SECURITY_NS_INTR2_0_CPU_MASK_CLEAR_MAC1_SEMAPHORE_FREED_DEFAULT 0x00000000
-
-/* XPT_SECURITY_NS_INTR2_0 :: CPU_MASK_CLEAR :: MAC1_READY [02:02] */
-#define BCHP_XPT_SECURITY_NS_INTR2_0_CPU_MASK_CLEAR_MAC1_READY_MASK 0x00000004
-#define BCHP_XPT_SECURITY_NS_INTR2_0_CPU_MASK_CLEAR_MAC1_READY_SHIFT 2
-#define BCHP_XPT_SECURITY_NS_INTR2_0_CPU_MASK_CLEAR_MAC1_READY_DEFAULT 0x00000000
-
-/* XPT_SECURITY_NS_INTR2_0 :: CPU_MASK_CLEAR :: MAC0_SEMAPHORE_FREED [01:01] */
-#define BCHP_XPT_SECURITY_NS_INTR2_0_CPU_MASK_CLEAR_MAC0_SEMAPHORE_FREED_MASK 0x00000002
-#define BCHP_XPT_SECURITY_NS_INTR2_0_CPU_MASK_CLEAR_MAC0_SEMAPHORE_FREED_SHIFT 1
-#define BCHP_XPT_SECURITY_NS_INTR2_0_CPU_MASK_CLEAR_MAC0_SEMAPHORE_FREED_DEFAULT 0x00000000
-
-/* XPT_SECURITY_NS_INTR2_0 :: CPU_MASK_CLEAR :: MAC0_READY [00:00] */
-#define BCHP_XPT_SECURITY_NS_INTR2_0_CPU_MASK_CLEAR_MAC0_READY_MASK 0x00000001
-#define BCHP_XPT_SECURITY_NS_INTR2_0_CPU_MASK_CLEAR_MAC0_READY_SHIFT 0
-#define BCHP_XPT_SECURITY_NS_INTR2_0_CPU_MASK_CLEAR_MAC0_READY_DEFAULT 0x00000000
-
-/***************************************************************************
- *PCI_STATUS - PCI interrupt Status Register
- ***************************************************************************/
-/* XPT_SECURITY_NS_INTR2_0 :: PCI_STATUS :: reserved0 [31:12] */
-#define BCHP_XPT_SECURITY_NS_INTR2_0_PCI_STATUS_reserved0_MASK 0xfffff000
-#define BCHP_XPT_SECURITY_NS_INTR2_0_PCI_STATUS_reserved0_SHIFT 12
-
-/* XPT_SECURITY_NS_INTR2_0 :: PCI_STATUS :: SHA21_SEMAPHORE_FREED [11:11] */
-#define BCHP_XPT_SECURITY_NS_INTR2_0_PCI_STATUS_SHA21_SEMAPHORE_FREED_MASK 0x00000800
-#define BCHP_XPT_SECURITY_NS_INTR2_0_PCI_STATUS_SHA21_SEMAPHORE_FREED_SHIFT 11
-#define BCHP_XPT_SECURITY_NS_INTR2_0_PCI_STATUS_SHA21_SEMAPHORE_FREED_DEFAULT 0x00000000
-
-/* XPT_SECURITY_NS_INTR2_0 :: PCI_STATUS :: SHA21_READY [10:10] */
-#define BCHP_XPT_SECURITY_NS_INTR2_0_PCI_STATUS_SHA21_READY_MASK 0x00000400
-#define BCHP_XPT_SECURITY_NS_INTR2_0_PCI_STATUS_SHA21_READY_SHIFT 10
-#define BCHP_XPT_SECURITY_NS_INTR2_0_PCI_STATUS_SHA21_READY_DEFAULT 0x00000000
-
-/* XPT_SECURITY_NS_INTR2_0 :: PCI_STATUS :: SHA20_SEMAPHORE_FREED [09:09] */
-#define BCHP_XPT_SECURITY_NS_INTR2_0_PCI_STATUS_SHA20_SEMAPHORE_FREED_MASK 0x00000200
-#define BCHP_XPT_SECURITY_NS_INTR2_0_PCI_STATUS_SHA20_SEMAPHORE_FREED_SHIFT 9
-#define BCHP_XPT_SECURITY_NS_INTR2_0_PCI_STATUS_SHA20_SEMAPHORE_FREED_DEFAULT 0x00000000
-
-/* XPT_SECURITY_NS_INTR2_0 :: PCI_STATUS :: SHA20_READY [08:08] */
-#define BCHP_XPT_SECURITY_NS_INTR2_0_PCI_STATUS_SHA20_READY_MASK 0x00000100
-#define BCHP_XPT_SECURITY_NS_INTR2_0_PCI_STATUS_SHA20_READY_SHIFT 8
-#define BCHP_XPT_SECURITY_NS_INTR2_0_PCI_STATUS_SHA20_READY_DEFAULT 0x00000000
-
-/* XPT_SECURITY_NS_INTR2_0 :: PCI_STATUS :: MAC3_SEMAPHORE_FREED [07:07] */
-#define BCHP_XPT_SECURITY_NS_INTR2_0_PCI_STATUS_MAC3_SEMAPHORE_FREED_MASK 0x00000080
-#define BCHP_XPT_SECURITY_NS_INTR2_0_PCI_STATUS_MAC3_SEMAPHORE_FREED_SHIFT 7
-#define BCHP_XPT_SECURITY_NS_INTR2_0_PCI_STATUS_MAC3_SEMAPHORE_FREED_DEFAULT 0x00000000
-
-/* XPT_SECURITY_NS_INTR2_0 :: PCI_STATUS :: MAC3_READY [06:06] */
-#define BCHP_XPT_SECURITY_NS_INTR2_0_PCI_STATUS_MAC3_READY_MASK 0x00000040
-#define BCHP_XPT_SECURITY_NS_INTR2_0_PCI_STATUS_MAC3_READY_SHIFT 6
-#define BCHP_XPT_SECURITY_NS_INTR2_0_PCI_STATUS_MAC3_READY_DEFAULT 0x00000000
-
-/* XPT_SECURITY_NS_INTR2_0 :: PCI_STATUS :: MAC2_SEMAPHORE_FREED [05:05] */
-#define BCHP_XPT_SECURITY_NS_INTR2_0_PCI_STATUS_MAC2_SEMAPHORE_FREED_MASK 0x00000020
-#define BCHP_XPT_SECURITY_NS_INTR2_0_PCI_STATUS_MAC2_SEMAPHORE_FREED_SHIFT 5
-#define BCHP_XPT_SECURITY_NS_INTR2_0_PCI_STATUS_MAC2_SEMAPHORE_FREED_DEFAULT 0x00000000
-
-/* XPT_SECURITY_NS_INTR2_0 :: PCI_STATUS :: MAC2_READY [04:04] */
-#define BCHP_XPT_SECURITY_NS_INTR2_0_PCI_STATUS_MAC2_READY_MASK 0x00000010
-#define BCHP_XPT_SECURITY_NS_INTR2_0_PCI_STATUS_MAC2_READY_SHIFT 4
-#define BCHP_XPT_SECURITY_NS_INTR2_0_PCI_STATUS_MAC2_READY_DEFAULT 0x00000000
-
-/* XPT_SECURITY_NS_INTR2_0 :: PCI_STATUS :: MAC1_SEMAPHORE_FREED [03:03] */
-#define BCHP_XPT_SECURITY_NS_INTR2_0_PCI_STATUS_MAC1_SEMAPHORE_FREED_MASK 0x00000008
-#define BCHP_XPT_SECURITY_NS_INTR2_0_PCI_STATUS_MAC1_SEMAPHORE_FREED_SHIFT 3
-#define BCHP_XPT_SECURITY_NS_INTR2_0_PCI_STATUS_MAC1_SEMAPHORE_FREED_DEFAULT 0x00000000
-
-/* XPT_SECURITY_NS_INTR2_0 :: PCI_STATUS :: MAC1_READY [02:02] */
-#define BCHP_XPT_SECURITY_NS_INTR2_0_PCI_STATUS_MAC1_READY_MASK 0x00000004
-#define BCHP_XPT_SECURITY_NS_INTR2_0_PCI_STATUS_MAC1_READY_SHIFT 2
-#define BCHP_XPT_SECURITY_NS_INTR2_0_PCI_STATUS_MAC1_READY_DEFAULT 0x00000000
-
-/* XPT_SECURITY_NS_INTR2_0 :: PCI_STATUS :: MAC0_SEMAPHORE_FREED [01:01] */
-#define BCHP_XPT_SECURITY_NS_INTR2_0_PCI_STATUS_MAC0_SEMAPHORE_FREED_MASK 0x00000002
-#define BCHP_XPT_SECURITY_NS_INTR2_0_PCI_STATUS_MAC0_SEMAPHORE_FREED_SHIFT 1
-#define BCHP_XPT_SECURITY_NS_INTR2_0_PCI_STATUS_MAC0_SEMAPHORE_FREED_DEFAULT 0x00000000
-
-/* XPT_SECURITY_NS_INTR2_0 :: PCI_STATUS :: MAC0_READY [00:00] */
-#define BCHP_XPT_SECURITY_NS_INTR2_0_PCI_STATUS_MAC0_READY_MASK 0x00000001
-#define BCHP_XPT_SECURITY_NS_INTR2_0_PCI_STATUS_MAC0_READY_SHIFT 0
-#define BCHP_XPT_SECURITY_NS_INTR2_0_PCI_STATUS_MAC0_READY_DEFAULT 0x00000000
-
-/***************************************************************************
- *PCI_SET - PCI interrupt Set Register
- ***************************************************************************/
-/* XPT_SECURITY_NS_INTR2_0 :: PCI_SET :: reserved0 [31:12] */
-#define BCHP_XPT_SECURITY_NS_INTR2_0_PCI_SET_reserved0_MASK 0xfffff000
-#define BCHP_XPT_SECURITY_NS_INTR2_0_PCI_SET_reserved0_SHIFT 12
-
-/* XPT_SECURITY_NS_INTR2_0 :: PCI_SET :: SHA21_SEMAPHORE_FREED [11:11] */
-#define BCHP_XPT_SECURITY_NS_INTR2_0_PCI_SET_SHA21_SEMAPHORE_FREED_MASK 0x00000800
-#define BCHP_XPT_SECURITY_NS_INTR2_0_PCI_SET_SHA21_SEMAPHORE_FREED_SHIFT 11
-#define BCHP_XPT_SECURITY_NS_INTR2_0_PCI_SET_SHA21_SEMAPHORE_FREED_DEFAULT 0x00000000
-
-/* XPT_SECURITY_NS_INTR2_0 :: PCI_SET :: SHA21_READY [10:10] */
-#define BCHP_XPT_SECURITY_NS_INTR2_0_PCI_SET_SHA21_READY_MASK 0x00000400
-#define BCHP_XPT_SECURITY_NS_INTR2_0_PCI_SET_SHA21_READY_SHIFT 10
-#define BCHP_XPT_SECURITY_NS_INTR2_0_PCI_SET_SHA21_READY_DEFAULT 0x00000000
-
-/* XPT_SECURITY_NS_INTR2_0 :: PCI_SET :: SHA20_SEMAPHORE_FREED [09:09] */
-#define BCHP_XPT_SECURITY_NS_INTR2_0_PCI_SET_SHA20_SEMAPHORE_FREED_MASK 0x00000200
-#define BCHP_XPT_SECURITY_NS_INTR2_0_PCI_SET_SHA20_SEMAPHORE_FREED_SHIFT 9
-#define BCHP_XPT_SECURITY_NS_INTR2_0_PCI_SET_SHA20_SEMAPHORE_FREED_DEFAULT 0x00000000
-
-/* XPT_SECURITY_NS_INTR2_0 :: PCI_SET :: SHA20_READY [08:08] */
-#define BCHP_XPT_SECURITY_NS_INTR2_0_PCI_SET_SHA20_READY_MASK 0x00000100
-#define BCHP_XPT_SECURITY_NS_INTR2_0_PCI_SET_SHA20_READY_SHIFT 8
-#define BCHP_XPT_SECURITY_NS_INTR2_0_PCI_SET_SHA20_READY_DEFAULT 0x00000000
-
-/* XPT_SECURITY_NS_INTR2_0 :: PCI_SET :: MAC3_SEMAPHORE_FREED [07:07] */
-#define BCHP_XPT_SECURITY_NS_INTR2_0_PCI_SET_MAC3_SEMAPHORE_FREED_MASK 0x00000080
-#define BCHP_XPT_SECURITY_NS_INTR2_0_PCI_SET_MAC3_SEMAPHORE_FREED_SHIFT 7
-#define BCHP_XPT_SECURITY_NS_INTR2_0_PCI_SET_MAC3_SEMAPHORE_FREED_DEFAULT 0x00000000
-
-/* XPT_SECURITY_NS_INTR2_0 :: PCI_SET :: MAC3_READY [06:06] */
-#define BCHP_XPT_SECURITY_NS_INTR2_0_PCI_SET_MAC3_READY_MASK 0x00000040
-#define BCHP_XPT_SECURITY_NS_INTR2_0_PCI_SET_MAC3_READY_SHIFT 6
-#define BCHP_XPT_SECURITY_NS_INTR2_0_PCI_SET_MAC3_READY_DEFAULT 0x00000000
-
-/* XPT_SECURITY_NS_INTR2_0 :: PCI_SET :: MAC2_SEMAPHORE_FREED [05:05] */
-#define BCHP_XPT_SECURITY_NS_INTR2_0_PCI_SET_MAC2_SEMAPHORE_FREED_MASK 0x00000020
-#define BCHP_XPT_SECURITY_NS_INTR2_0_PCI_SET_MAC2_SEMAPHORE_FREED_SHIFT 5
-#define BCHP_XPT_SECURITY_NS_INTR2_0_PCI_SET_MAC2_SEMAPHORE_FREED_DEFAULT 0x00000000
-
-/* XPT_SECURITY_NS_INTR2_0 :: PCI_SET :: MAC2_READY [04:04] */
-#define BCHP_XPT_SECURITY_NS_INTR2_0_PCI_SET_MAC2_READY_MASK 0x00000010
-#define BCHP_XPT_SECURITY_NS_INTR2_0_PCI_SET_MAC2_READY_SHIFT 4
-#define BCHP_XPT_SECURITY_NS_INTR2_0_PCI_SET_MAC2_READY_DEFAULT 0x00000000
-
-/* XPT_SECURITY_NS_INTR2_0 :: PCI_SET :: MAC1_SEMAPHORE_FREED [03:03] */
-#define BCHP_XPT_SECURITY_NS_INTR2_0_PCI_SET_MAC1_SEMAPHORE_FREED_MASK 0x00000008
-#define BCHP_XPT_SECURITY_NS_INTR2_0_PCI_SET_MAC1_SEMAPHORE_FREED_SHIFT 3
-#define BCHP_XPT_SECURITY_NS_INTR2_0_PCI_SET_MAC1_SEMAPHORE_FREED_DEFAULT 0x00000000
-
-/* XPT_SECURITY_NS_INTR2_0 :: PCI_SET :: MAC1_READY [02:02] */
-#define BCHP_XPT_SECURITY_NS_INTR2_0_PCI_SET_MAC1_READY_MASK 0x00000004
-#define BCHP_XPT_SECURITY_NS_INTR2_0_PCI_SET_MAC1_READY_SHIFT 2
-#define BCHP_XPT_SECURITY_NS_INTR2_0_PCI_SET_MAC1_READY_DEFAULT 0x00000000
-
-/* XPT_SECURITY_NS_INTR2_0 :: PCI_SET :: MAC0_SEMAPHORE_FREED [01:01] */
-#define BCHP_XPT_SECURITY_NS_INTR2_0_PCI_SET_MAC0_SEMAPHORE_FREED_MASK 0x00000002
-#define BCHP_XPT_SECURITY_NS_INTR2_0_PCI_SET_MAC0_SEMAPHORE_FREED_SHIFT 1
-#define BCHP_XPT_SECURITY_NS_INTR2_0_PCI_SET_MAC0_SEMAPHORE_FREED_DEFAULT 0x00000000
-
-/* XPT_SECURITY_NS_INTR2_0 :: PCI_SET :: MAC0_READY [00:00] */
-#define BCHP_XPT_SECURITY_NS_INTR2_0_PCI_SET_MAC0_READY_MASK 0x00000001
-#define BCHP_XPT_SECURITY_NS_INTR2_0_PCI_SET_MAC0_READY_SHIFT 0
-#define BCHP_XPT_SECURITY_NS_INTR2_0_PCI_SET_MAC0_READY_DEFAULT 0x00000000
-
-/***************************************************************************
- *PCI_CLEAR - PCI interrupt Clear Register
- ***************************************************************************/
-/* XPT_SECURITY_NS_INTR2_0 :: PCI_CLEAR :: reserved0 [31:12] */
-#define BCHP_XPT_SECURITY_NS_INTR2_0_PCI_CLEAR_reserved0_MASK 0xfffff000
-#define BCHP_XPT_SECURITY_NS_INTR2_0_PCI_CLEAR_reserved0_SHIFT 12
-
-/* XPT_SECURITY_NS_INTR2_0 :: PCI_CLEAR :: SHA21_SEMAPHORE_FREED [11:11] */
-#define BCHP_XPT_SECURITY_NS_INTR2_0_PCI_CLEAR_SHA21_SEMAPHORE_FREED_MASK 0x00000800
-#define BCHP_XPT_SECURITY_NS_INTR2_0_PCI_CLEAR_SHA21_SEMAPHORE_FREED_SHIFT 11
-#define BCHP_XPT_SECURITY_NS_INTR2_0_PCI_CLEAR_SHA21_SEMAPHORE_FREED_DEFAULT 0x00000000
-
-/* XPT_SECURITY_NS_INTR2_0 :: PCI_CLEAR :: SHA21_READY [10:10] */
-#define BCHP_XPT_SECURITY_NS_INTR2_0_PCI_CLEAR_SHA21_READY_MASK 0x00000400
-#define BCHP_XPT_SECURITY_NS_INTR2_0_PCI_CLEAR_SHA21_READY_SHIFT 10
-#define BCHP_XPT_SECURITY_NS_INTR2_0_PCI_CLEAR_SHA21_READY_DEFAULT 0x00000000
-
-/* XPT_SECURITY_NS_INTR2_0 :: PCI_CLEAR :: SHA20_SEMAPHORE_FREED [09:09] */
-#define BCHP_XPT_SECURITY_NS_INTR2_0_PCI_CLEAR_SHA20_SEMAPHORE_FREED_MASK 0x00000200
-#define BCHP_XPT_SECURITY_NS_INTR2_0_PCI_CLEAR_SHA20_SEMAPHORE_FREED_SHIFT 9
-#define BCHP_XPT_SECURITY_NS_INTR2_0_PCI_CLEAR_SHA20_SEMAPHORE_FREED_DEFAULT 0x00000000
-
-/* XPT_SECURITY_NS_INTR2_0 :: PCI_CLEAR :: SHA20_READY [08:08] */
-#define BCHP_XPT_SECURITY_NS_INTR2_0_PCI_CLEAR_SHA20_READY_MASK 0x00000100
-#define BCHP_XPT_SECURITY_NS_INTR2_0_PCI_CLEAR_SHA20_READY_SHIFT 8
-#define BCHP_XPT_SECURITY_NS_INTR2_0_PCI_CLEAR_SHA20_READY_DEFAULT 0x00000000
-
-/* XPT_SECURITY_NS_INTR2_0 :: PCI_CLEAR :: MAC3_SEMAPHORE_FREED [07:07] */
-#define BCHP_XPT_SECURITY_NS_INTR2_0_PCI_CLEAR_MAC3_SEMAPHORE_FREED_MASK 0x00000080
-#define BCHP_XPT_SECURITY_NS_INTR2_0_PCI_CLEAR_MAC3_SEMAPHORE_FREED_SHIFT 7
-#define BCHP_XPT_SECURITY_NS_INTR2_0_PCI_CLEAR_MAC3_SEMAPHORE_FREED_DEFAULT 0x00000000
-
-/* XPT_SECURITY_NS_INTR2_0 :: PCI_CLEAR :: MAC3_READY [06:06] */
-#define BCHP_XPT_SECURITY_NS_INTR2_0_PCI_CLEAR_MAC3_READY_MASK 0x00000040
-#define BCHP_XPT_SECURITY_NS_INTR2_0_PCI_CLEAR_MAC3_READY_SHIFT 6
-#define BCHP_XPT_SECURITY_NS_INTR2_0_PCI_CLEAR_MAC3_READY_DEFAULT 0x00000000
-
-/* XPT_SECURITY_NS_INTR2_0 :: PCI_CLEAR :: MAC2_SEMAPHORE_FREED [05:05] */
-#define BCHP_XPT_SECURITY_NS_INTR2_0_PCI_CLEAR_MAC2_SEMAPHORE_FREED_MASK 0x00000020
-#define BCHP_XPT_SECURITY_NS_INTR2_0_PCI_CLEAR_MAC2_SEMAPHORE_FREED_SHIFT 5
-#define BCHP_XPT_SECURITY_NS_INTR2_0_PCI_CLEAR_MAC2_SEMAPHORE_FREED_DEFAULT 0x00000000
-
-/* XPT_SECURITY_NS_INTR2_0 :: PCI_CLEAR :: MAC2_READY [04:04] */
-#define BCHP_XPT_SECURITY_NS_INTR2_0_PCI_CLEAR_MAC2_READY_MASK 0x00000010
-#define BCHP_XPT_SECURITY_NS_INTR2_0_PCI_CLEAR_MAC2_READY_SHIFT 4
-#define BCHP_XPT_SECURITY_NS_INTR2_0_PCI_CLEAR_MAC2_READY_DEFAULT 0x00000000
-
-/* XPT_SECURITY_NS_INTR2_0 :: PCI_CLEAR :: MAC1_SEMAPHORE_FREED [03:03] */
-#define BCHP_XPT_SECURITY_NS_INTR2_0_PCI_CLEAR_MAC1_SEMAPHORE_FREED_MASK 0x00000008
-#define BCHP_XPT_SECURITY_NS_INTR2_0_PCI_CLEAR_MAC1_SEMAPHORE_FREED_SHIFT 3
-#define BCHP_XPT_SECURITY_NS_INTR2_0_PCI_CLEAR_MAC1_SEMAPHORE_FREED_DEFAULT 0x00000000
-
-/* XPT_SECURITY_NS_INTR2_0 :: PCI_CLEAR :: MAC1_READY [02:02] */
-#define BCHP_XPT_SECURITY_NS_INTR2_0_PCI_CLEAR_MAC1_READY_MASK 0x00000004
-#define BCHP_XPT_SECURITY_NS_INTR2_0_PCI_CLEAR_MAC1_READY_SHIFT 2
-#define BCHP_XPT_SECURITY_NS_INTR2_0_PCI_CLEAR_MAC1_READY_DEFAULT 0x00000000
-
-/* XPT_SECURITY_NS_INTR2_0 :: PCI_CLEAR :: MAC0_SEMAPHORE_FREED [01:01] */
-#define BCHP_XPT_SECURITY_NS_INTR2_0_PCI_CLEAR_MAC0_SEMAPHORE_FREED_MASK 0x00000002
-#define BCHP_XPT_SECURITY_NS_INTR2_0_PCI_CLEAR_MAC0_SEMAPHORE_FREED_SHIFT 1
-#define BCHP_XPT_SECURITY_NS_INTR2_0_PCI_CLEAR_MAC0_SEMAPHORE_FREED_DEFAULT 0x00000000
-
-/* XPT_SECURITY_NS_INTR2_0 :: PCI_CLEAR :: MAC0_READY [00:00] */
-#define BCHP_XPT_SECURITY_NS_INTR2_0_PCI_CLEAR_MAC0_READY_MASK 0x00000001
-#define BCHP_XPT_SECURITY_NS_INTR2_0_PCI_CLEAR_MAC0_READY_SHIFT 0
-#define BCHP_XPT_SECURITY_NS_INTR2_0_PCI_CLEAR_MAC0_READY_DEFAULT 0x00000000
-
-/***************************************************************************
- *PCI_MASK_STATUS - PCI interrupt Mask Status Register
- ***************************************************************************/
-/* XPT_SECURITY_NS_INTR2_0 :: PCI_MASK_STATUS :: reserved0 [31:12] */
-#define BCHP_XPT_SECURITY_NS_INTR2_0_PCI_MASK_STATUS_reserved0_MASK 0xfffff000
-#define BCHP_XPT_SECURITY_NS_INTR2_0_PCI_MASK_STATUS_reserved0_SHIFT 12
-
-/* XPT_SECURITY_NS_INTR2_0 :: PCI_MASK_STATUS :: SHA21_SEMAPHORE_FREED [11:11] */
-#define BCHP_XPT_SECURITY_NS_INTR2_0_PCI_MASK_STATUS_SHA21_SEMAPHORE_FREED_MASK 0x00000800
-#define BCHP_XPT_SECURITY_NS_INTR2_0_PCI_MASK_STATUS_SHA21_SEMAPHORE_FREED_SHIFT 11
-#define BCHP_XPT_SECURITY_NS_INTR2_0_PCI_MASK_STATUS_SHA21_SEMAPHORE_FREED_DEFAULT 0x00000000
-
-/* XPT_SECURITY_NS_INTR2_0 :: PCI_MASK_STATUS :: SHA21_READY [10:10] */
-#define BCHP_XPT_SECURITY_NS_INTR2_0_PCI_MASK_STATUS_SHA21_READY_MASK 0x00000400
-#define BCHP_XPT_SECURITY_NS_INTR2_0_PCI_MASK_STATUS_SHA21_READY_SHIFT 10
-#define BCHP_XPT_SECURITY_NS_INTR2_0_PCI_MASK_STATUS_SHA21_READY_DEFAULT 0x00000000
-
-/* XPT_SECURITY_NS_INTR2_0 :: PCI_MASK_STATUS :: SHA20_SEMAPHORE_FREED [09:09] */
-#define BCHP_XPT_SECURITY_NS_INTR2_0_PCI_MASK_STATUS_SHA20_SEMAPHORE_FREED_MASK 0x00000200
-#define BCHP_XPT_SECURITY_NS_INTR2_0_PCI_MASK_STATUS_SHA20_SEMAPHORE_FREED_SHIFT 9
-#define BCHP_XPT_SECURITY_NS_INTR2_0_PCI_MASK_STATUS_SHA20_SEMAPHORE_FREED_DEFAULT 0x00000000
-
-/* XPT_SECURITY_NS_INTR2_0 :: PCI_MASK_STATUS :: SHA20_READY [08:08] */
-#define BCHP_XPT_SECURITY_NS_INTR2_0_PCI_MASK_STATUS_SHA20_READY_MASK 0x00000100
-#define BCHP_XPT_SECURITY_NS_INTR2_0_PCI_MASK_STATUS_SHA20_READY_SHIFT 8
-#define BCHP_XPT_SECURITY_NS_INTR2_0_PCI_MASK_STATUS_SHA20_READY_DEFAULT 0x00000000
-
-/* XPT_SECURITY_NS_INTR2_0 :: PCI_MASK_STATUS :: MAC3_SEMAPHORE_FREED [07:07] */
-#define BCHP_XPT_SECURITY_NS_INTR2_0_PCI_MASK_STATUS_MAC3_SEMAPHORE_FREED_MASK 0x00000080
-#define BCHP_XPT_SECURITY_NS_INTR2_0_PCI_MASK_STATUS_MAC3_SEMAPHORE_FREED_SHIFT 7
-#define BCHP_XPT_SECURITY_NS_INTR2_0_PCI_MASK_STATUS_MAC3_SEMAPHORE_FREED_DEFAULT 0x00000000
-
-/* XPT_SECURITY_NS_INTR2_0 :: PCI_MASK_STATUS :: MAC3_READY [06:06] */
-#define BCHP_XPT_SECURITY_NS_INTR2_0_PCI_MASK_STATUS_MAC3_READY_MASK 0x00000040
-#define BCHP_XPT_SECURITY_NS_INTR2_0_PCI_MASK_STATUS_MAC3_READY_SHIFT 6
-#define BCHP_XPT_SECURITY_NS_INTR2_0_PCI_MASK_STATUS_MAC3_READY_DEFAULT 0x00000000
-
-/* XPT_SECURITY_NS_INTR2_0 :: PCI_MASK_STATUS :: MAC2_SEMAPHORE_FREED [05:05] */
-#define BCHP_XPT_SECURITY_NS_INTR2_0_PCI_MASK_STATUS_MAC2_SEMAPHORE_FREED_MASK 0x00000020
-#define BCHP_XPT_SECURITY_NS_INTR2_0_PCI_MASK_STATUS_MAC2_SEMAPHORE_FREED_SHIFT 5
-#define BCHP_XPT_SECURITY_NS_INTR2_0_PCI_MASK_STATUS_MAC2_SEMAPHORE_FREED_DEFAULT 0x00000000
-
-/* XPT_SECURITY_NS_INTR2_0 :: PCI_MASK_STATUS :: MAC2_READY [04:04] */
-#define BCHP_XPT_SECURITY_NS_INTR2_0_PCI_MASK_STATUS_MAC2_READY_MASK 0x00000010
-#define BCHP_XPT_SECURITY_NS_INTR2_0_PCI_MASK_STATUS_MAC2_READY_SHIFT 4
-#define BCHP_XPT_SECURITY_NS_INTR2_0_PCI_MASK_STATUS_MAC2_READY_DEFAULT 0x00000000
-
-/* XPT_SECURITY_NS_INTR2_0 :: PCI_MASK_STATUS :: MAC1_SEMAPHORE_FREED [03:03] */
-#define BCHP_XPT_SECURITY_NS_INTR2_0_PCI_MASK_STATUS_MAC1_SEMAPHORE_FREED_MASK 0x00000008
-#define BCHP_XPT_SECURITY_NS_INTR2_0_PCI_MASK_STATUS_MAC1_SEMAPHORE_FREED_SHIFT 3
-#define BCHP_XPT_SECURITY_NS_INTR2_0_PCI_MASK_STATUS_MAC1_SEMAPHORE_FREED_DEFAULT 0x00000000
-
-/* XPT_SECURITY_NS_INTR2_0 :: PCI_MASK_STATUS :: MAC1_READY [02:02] */
-#define BCHP_XPT_SECURITY_NS_INTR2_0_PCI_MASK_STATUS_MAC1_READY_MASK 0x00000004
-#define BCHP_XPT_SECURITY_NS_INTR2_0_PCI_MASK_STATUS_MAC1_READY_SHIFT 2
-#define BCHP_XPT_SECURITY_NS_INTR2_0_PCI_MASK_STATUS_MAC1_READY_DEFAULT 0x00000000
-
-/* XPT_SECURITY_NS_INTR2_0 :: PCI_MASK_STATUS :: MAC0_SEMAPHORE_FREED [01:01] */
-#define BCHP_XPT_SECURITY_NS_INTR2_0_PCI_MASK_STATUS_MAC0_SEMAPHORE_FREED_MASK 0x00000002
-#define BCHP_XPT_SECURITY_NS_INTR2_0_PCI_MASK_STATUS_MAC0_SEMAPHORE_FREED_SHIFT 1
-#define BCHP_XPT_SECURITY_NS_INTR2_0_PCI_MASK_STATUS_MAC0_SEMAPHORE_FREED_DEFAULT 0x00000000
-
-/* XPT_SECURITY_NS_INTR2_0 :: PCI_MASK_STATUS :: MAC0_READY [00:00] */
-#define BCHP_XPT_SECURITY_NS_INTR2_0_PCI_MASK_STATUS_MAC0_READY_MASK 0x00000001
-#define BCHP_XPT_SECURITY_NS_INTR2_0_PCI_MASK_STATUS_MAC0_READY_SHIFT 0
-#define BCHP_XPT_SECURITY_NS_INTR2_0_PCI_MASK_STATUS_MAC0_READY_DEFAULT 0x00000000
-
-/***************************************************************************
- *PCI_MASK_SET - PCI interrupt Mask Set Register
- ***************************************************************************/
-/* XPT_SECURITY_NS_INTR2_0 :: PCI_MASK_SET :: reserved0 [31:12] */
-#define BCHP_XPT_SECURITY_NS_INTR2_0_PCI_MASK_SET_reserved0_MASK 0xfffff000
-#define BCHP_XPT_SECURITY_NS_INTR2_0_PCI_MASK_SET_reserved0_SHIFT 12
-
-/* XPT_SECURITY_NS_INTR2_0 :: PCI_MASK_SET :: SHA21_SEMAPHORE_FREED [11:11] */
-#define BCHP_XPT_SECURITY_NS_INTR2_0_PCI_MASK_SET_SHA21_SEMAPHORE_FREED_MASK 0x00000800
-#define BCHP_XPT_SECURITY_NS_INTR2_0_PCI_MASK_SET_SHA21_SEMAPHORE_FREED_SHIFT 11
-#define BCHP_XPT_SECURITY_NS_INTR2_0_PCI_MASK_SET_SHA21_SEMAPHORE_FREED_DEFAULT 0x00000000
-
-/* XPT_SECURITY_NS_INTR2_0 :: PCI_MASK_SET :: SHA21_READY [10:10] */
-#define BCHP_XPT_SECURITY_NS_INTR2_0_PCI_MASK_SET_SHA21_READY_MASK 0x00000400
-#define BCHP_XPT_SECURITY_NS_INTR2_0_PCI_MASK_SET_SHA21_READY_SHIFT 10
-#define BCHP_XPT_SECURITY_NS_INTR2_0_PCI_MASK_SET_SHA21_READY_DEFAULT 0x00000000
-
-/* XPT_SECURITY_NS_INTR2_0 :: PCI_MASK_SET :: SHA20_SEMAPHORE_FREED [09:09] */
-#define BCHP_XPT_SECURITY_NS_INTR2_0_PCI_MASK_SET_SHA20_SEMAPHORE_FREED_MASK 0x00000200
-#define BCHP_XPT_SECURITY_NS_INTR2_0_PCI_MASK_SET_SHA20_SEMAPHORE_FREED_SHIFT 9
-#define BCHP_XPT_SECURITY_NS_INTR2_0_PCI_MASK_SET_SHA20_SEMAPHORE_FREED_DEFAULT 0x00000000
-
-/* XPT_SECURITY_NS_INTR2_0 :: PCI_MASK_SET :: SHA20_READY [08:08] */
-#define BCHP_XPT_SECURITY_NS_INTR2_0_PCI_MASK_SET_SHA20_READY_MASK 0x00000100
-#define BCHP_XPT_SECURITY_NS_INTR2_0_PCI_MASK_SET_SHA20_READY_SHIFT 8
-#define BCHP_XPT_SECURITY_NS_INTR2_0_PCI_MASK_SET_SHA20_READY_DEFAULT 0x00000000
-
-/* XPT_SECURITY_NS_INTR2_0 :: PCI_MASK_SET :: MAC3_SEMAPHORE_FREED [07:07] */
-#define BCHP_XPT_SECURITY_NS_INTR2_0_PCI_MASK_SET_MAC3_SEMAPHORE_FREED_MASK 0x00000080
-#define BCHP_XPT_SECURITY_NS_INTR2_0_PCI_MASK_SET_MAC3_SEMAPHORE_FREED_SHIFT 7
-#define BCHP_XPT_SECURITY_NS_INTR2_0_PCI_MASK_SET_MAC3_SEMAPHORE_FREED_DEFAULT 0x00000000
-
-/* XPT_SECURITY_NS_INTR2_0 :: PCI_MASK_SET :: MAC3_READY [06:06] */
-#define BCHP_XPT_SECURITY_NS_INTR2_0_PCI_MASK_SET_MAC3_READY_MASK 0x00000040
-#define BCHP_XPT_SECURITY_NS_INTR2_0_PCI_MASK_SET_MAC3_READY_SHIFT 6
-#define BCHP_XPT_SECURITY_NS_INTR2_0_PCI_MASK_SET_MAC3_READY_DEFAULT 0x00000000
-
-/* XPT_SECURITY_NS_INTR2_0 :: PCI_MASK_SET :: MAC2_SEMAPHORE_FREED [05:05] */
-#define BCHP_XPT_SECURITY_NS_INTR2_0_PCI_MASK_SET_MAC2_SEMAPHORE_FREED_MASK 0x00000020
-#define BCHP_XPT_SECURITY_NS_INTR2_0_PCI_MASK_SET_MAC2_SEMAPHORE_FREED_SHIFT 5
-#define BCHP_XPT_SECURITY_NS_INTR2_0_PCI_MASK_SET_MAC2_SEMAPHORE_FREED_DEFAULT 0x00000000
-
-/* XPT_SECURITY_NS_INTR2_0 :: PCI_MASK_SET :: MAC2_READY [04:04] */
-#define BCHP_XPT_SECURITY_NS_INTR2_0_PCI_MASK_SET_MAC2_READY_MASK 0x00000010
-#define BCHP_XPT_SECURITY_NS_INTR2_0_PCI_MASK_SET_MAC2_READY_SHIFT 4
-#define BCHP_XPT_SECURITY_NS_INTR2_0_PCI_MASK_SET_MAC2_READY_DEFAULT 0x00000000
-
-/* XPT_SECURITY_NS_INTR2_0 :: PCI_MASK_SET :: MAC1_SEMAPHORE_FREED [03:03] */
-#define BCHP_XPT_SECURITY_NS_INTR2_0_PCI_MASK_SET_MAC1_SEMAPHORE_FREED_MASK 0x00000008
-#define BCHP_XPT_SECURITY_NS_INTR2_0_PCI_MASK_SET_MAC1_SEMAPHORE_FREED_SHIFT 3
-#define BCHP_XPT_SECURITY_NS_INTR2_0_PCI_MASK_SET_MAC1_SEMAPHORE_FREED_DEFAULT 0x00000000
-
-/* XPT_SECURITY_NS_INTR2_0 :: PCI_MASK_SET :: MAC1_READY [02:02] */
-#define BCHP_XPT_SECURITY_NS_INTR2_0_PCI_MASK_SET_MAC1_READY_MASK 0x00000004
-#define BCHP_XPT_SECURITY_NS_INTR2_0_PCI_MASK_SET_MAC1_READY_SHIFT 2
-#define BCHP_XPT_SECURITY_NS_INTR2_0_PCI_MASK_SET_MAC1_READY_DEFAULT 0x00000000
-
-/* XPT_SECURITY_NS_INTR2_0 :: PCI_MASK_SET :: MAC0_SEMAPHORE_FREED [01:01] */
-#define BCHP_XPT_SECURITY_NS_INTR2_0_PCI_MASK_SET_MAC0_SEMAPHORE_FREED_MASK 0x00000002
-#define BCHP_XPT_SECURITY_NS_INTR2_0_PCI_MASK_SET_MAC0_SEMAPHORE_FREED_SHIFT 1
-#define BCHP_XPT_SECURITY_NS_INTR2_0_PCI_MASK_SET_MAC0_SEMAPHORE_FREED_DEFAULT 0x00000000
-
-/* XPT_SECURITY_NS_INTR2_0 :: PCI_MASK_SET :: MAC0_READY [00:00] */
-#define BCHP_XPT_SECURITY_NS_INTR2_0_PCI_MASK_SET_MAC0_READY_MASK 0x00000001
-#define BCHP_XPT_SECURITY_NS_INTR2_0_PCI_MASK_SET_MAC0_READY_SHIFT 0
-#define BCHP_XPT_SECURITY_NS_INTR2_0_PCI_MASK_SET_MAC0_READY_DEFAULT 0x00000000
-
-/***************************************************************************
- *PCI_MASK_CLEAR - PCI interrupt Mask Clear Register
- ***************************************************************************/
-/* XPT_SECURITY_NS_INTR2_0 :: PCI_MASK_CLEAR :: reserved0 [31:12] */
-#define BCHP_XPT_SECURITY_NS_INTR2_0_PCI_MASK_CLEAR_reserved0_MASK 0xfffff000
-#define BCHP_XPT_SECURITY_NS_INTR2_0_PCI_MASK_CLEAR_reserved0_SHIFT 12
-
-/* XPT_SECURITY_NS_INTR2_0 :: PCI_MASK_CLEAR :: SHA21_SEMAPHORE_FREED [11:11] */
-#define BCHP_XPT_SECURITY_NS_INTR2_0_PCI_MASK_CLEAR_SHA21_SEMAPHORE_FREED_MASK 0x00000800
-#define BCHP_XPT_SECURITY_NS_INTR2_0_PCI_MASK_CLEAR_SHA21_SEMAPHORE_FREED_SHIFT 11
-#define BCHP_XPT_SECURITY_NS_INTR2_0_PCI_MASK_CLEAR_SHA21_SEMAPHORE_FREED_DEFAULT 0x00000000
-
-/* XPT_SECURITY_NS_INTR2_0 :: PCI_MASK_CLEAR :: SHA21_READY [10:10] */
-#define BCHP_XPT_SECURITY_NS_INTR2_0_PCI_MASK_CLEAR_SHA21_READY_MASK 0x00000400
-#define BCHP_XPT_SECURITY_NS_INTR2_0_PCI_MASK_CLEAR_SHA21_READY_SHIFT 10
-#define BCHP_XPT_SECURITY_NS_INTR2_0_PCI_MASK_CLEAR_SHA21_READY_DEFAULT 0x00000000
-
-/* XPT_SECURITY_NS_INTR2_0 :: PCI_MASK_CLEAR :: SHA20_SEMAPHORE_FREED [09:09] */
-#define BCHP_XPT_SECURITY_NS_INTR2_0_PCI_MASK_CLEAR_SHA20_SEMAPHORE_FREED_MASK 0x00000200
-#define BCHP_XPT_SECURITY_NS_INTR2_0_PCI_MASK_CLEAR_SHA20_SEMAPHORE_FREED_SHIFT 9
-#define BCHP_XPT_SECURITY_NS_INTR2_0_PCI_MASK_CLEAR_SHA20_SEMAPHORE_FREED_DEFAULT 0x00000000
-
-/* XPT_SECURITY_NS_INTR2_0 :: PCI_MASK_CLEAR :: SHA20_READY [08:08] */
-#define BCHP_XPT_SECURITY_NS_INTR2_0_PCI_MASK_CLEAR_SHA20_READY_MASK 0x00000100
-#define BCHP_XPT_SECURITY_NS_INTR2_0_PCI_MASK_CLEAR_SHA20_READY_SHIFT 8
-#define BCHP_XPT_SECURITY_NS_INTR2_0_PCI_MASK_CLEAR_SHA20_READY_DEFAULT 0x00000000
-
-/* XPT_SECURITY_NS_INTR2_0 :: PCI_MASK_CLEAR :: MAC3_SEMAPHORE_FREED [07:07] */
-#define BCHP_XPT_SECURITY_NS_INTR2_0_PCI_MASK_CLEAR_MAC3_SEMAPHORE_FREED_MASK 0x00000080
-#define BCHP_XPT_SECURITY_NS_INTR2_0_PCI_MASK_CLEAR_MAC3_SEMAPHORE_FREED_SHIFT 7
-#define BCHP_XPT_SECURITY_NS_INTR2_0_PCI_MASK_CLEAR_MAC3_SEMAPHORE_FREED_DEFAULT 0x00000000
-
-/* XPT_SECURITY_NS_INTR2_0 :: PCI_MASK_CLEAR :: MAC3_READY [06:06] */
-#define BCHP_XPT_SECURITY_NS_INTR2_0_PCI_MASK_CLEAR_MAC3_READY_MASK 0x00000040
-#define BCHP_XPT_SECURITY_NS_INTR2_0_PCI_MASK_CLEAR_MAC3_READY_SHIFT 6
-#define BCHP_XPT_SECURITY_NS_INTR2_0_PCI_MASK_CLEAR_MAC3_READY_DEFAULT 0x00000000
-
-/* XPT_SECURITY_NS_INTR2_0 :: PCI_MASK_CLEAR :: MAC2_SEMAPHORE_FREED [05:05] */
-#define BCHP_XPT_SECURITY_NS_INTR2_0_PCI_MASK_CLEAR_MAC2_SEMAPHORE_FREED_MASK 0x00000020
-#define BCHP_XPT_SECURITY_NS_INTR2_0_PCI_MASK_CLEAR_MAC2_SEMAPHORE_FREED_SHIFT 5
-#define BCHP_XPT_SECURITY_NS_INTR2_0_PCI_MASK_CLEAR_MAC2_SEMAPHORE_FREED_DEFAULT 0x00000000
-
-/* XPT_SECURITY_NS_INTR2_0 :: PCI_MASK_CLEAR :: MAC2_READY [04:04] */
-#define BCHP_XPT_SECURITY_NS_INTR2_0_PCI_MASK_CLEAR_MAC2_READY_MASK 0x00000010
-#define BCHP_XPT_SECURITY_NS_INTR2_0_PCI_MASK_CLEAR_MAC2_READY_SHIFT 4
-#define BCHP_XPT_SECURITY_NS_INTR2_0_PCI_MASK_CLEAR_MAC2_READY_DEFAULT 0x00000000
-
-/* XPT_SECURITY_NS_INTR2_0 :: PCI_MASK_CLEAR :: MAC1_SEMAPHORE_FREED [03:03] */
-#define BCHP_XPT_SECURITY_NS_INTR2_0_PCI_MASK_CLEAR_MAC1_SEMAPHORE_FREED_MASK 0x00000008
-#define BCHP_XPT_SECURITY_NS_INTR2_0_PCI_MASK_CLEAR_MAC1_SEMAPHORE_FREED_SHIFT 3
-#define BCHP_XPT_SECURITY_NS_INTR2_0_PCI_MASK_CLEAR_MAC1_SEMAPHORE_FREED_DEFAULT 0x00000000
-
-/* XPT_SECURITY_NS_INTR2_0 :: PCI_MASK_CLEAR :: MAC1_READY [02:02] */
-#define BCHP_XPT_SECURITY_NS_INTR2_0_PCI_MASK_CLEAR_MAC1_READY_MASK 0x00000004
-#define BCHP_XPT_SECURITY_NS_INTR2_0_PCI_MASK_CLEAR_MAC1_READY_SHIFT 2
-#define BCHP_XPT_SECURITY_NS_INTR2_0_PCI_MASK_CLEAR_MAC1_READY_DEFAULT 0x00000000
-
-/* XPT_SECURITY_NS_INTR2_0 :: PCI_MASK_CLEAR :: MAC0_SEMAPHORE_FREED [01:01] */
-#define BCHP_XPT_SECURITY_NS_INTR2_0_PCI_MASK_CLEAR_MAC0_SEMAPHORE_FREED_MASK 0x00000002
-#define BCHP_XPT_SECURITY_NS_INTR2_0_PCI_MASK_CLEAR_MAC0_SEMAPHORE_FREED_SHIFT 1
-#define BCHP_XPT_SECURITY_NS_INTR2_0_PCI_MASK_CLEAR_MAC0_SEMAPHORE_FREED_DEFAULT 0x00000000
-
-/* XPT_SECURITY_NS_INTR2_0 :: PCI_MASK_CLEAR :: MAC0_READY [00:00] */
-#define BCHP_XPT_SECURITY_NS_INTR2_0_PCI_MASK_CLEAR_MAC0_READY_MASK 0x00000001
-#define BCHP_XPT_SECURITY_NS_INTR2_0_PCI_MASK_CLEAR_MAC0_READY_SHIFT 0
-#define BCHP_XPT_SECURITY_NS_INTR2_0_PCI_MASK_CLEAR_MAC0_READY_DEFAULT 0x00000000
-
-#endif /* #ifndef BCHP_XPT_SECURITY_NS_INTR2_0_H__ */
-
-/* End of File */
diff --git a/include/linux/brcmstb/7366c0/bchp_usb_ctrl.h b/include/linux/brcmstb/7366c0/bchp_usb_ctrl.h
index badd51a..3c09d4a 100644
--- a/include/linux/brcmstb/7366c0/bchp_usb_ctrl.h
+++ b/include/linux/brcmstb/7366c0/bchp_usb_ctrl.h
@@ -1,4 +1,4 @@
-/***************************************************************************
+/****************************************************************************
* Copyright (c) 1999-2014, Broadcom Corporation
* All Rights Reserved
* Confidential Property of Broadcom Corporation
@@ -8,10 +8,6 @@
* AGREEMENT BETWEEN THE USER AND BROADCOM. YOU HAVE NO RIGHT TO USE OR
* EXPLOIT THIS MATERIAL EXCEPT SUBJECT TO THE TERMS OF SUCH AN AGREEMENT.
*
- * $brcm_Workfile: $
- * $brcm_Revision: $
- * $brcm_Date: $
- *
* Module Description:
* DO NOT EDIT THIS FILE DIRECTLY
*
@@ -19,20 +15,17 @@
* file. You must edit the source file for changes to be made to this file.
*
*
- * Date: Generated on Tue Dec 2 03:18:47 2014
- * Full Compile MD5 Checksum 3461841ff250f7118305e1f1650424cf
- * (minus title and desc)
- * MD5 Checksum 92044aba65695bbffdeefc8d096b8587
+ * Date: Generated on Wed Feb 18 03:13:18 2015
+ * Full Compile MD5 Checksum e2f31009bf32b83eddf082e72de66fc9
+ * (minus title and desc)
+ * MD5 Checksum 5d3a169247e37ce28e4167f85d3a548a
*
- * Compiled with: RDB Utility combo_header.pl
- * RDB Parser 3.0
- * unknown unknown
- * Perl Interpreter 5.008008
- * Operating System linux
+ * Compiled with: RDB Utility combo_header.pl
+ * RDB.pm 15517
+ * unknown unknown
+ * Perl Interpreter 5.008008
+ * Operating System linux
*
- * Revision History:
- *
- * $brcm_Log: $
*
***************************************************************************/
@@ -42,45 +35,45 @@
/***************************************************************************
*USB_CTRL - USB Control Registers
***************************************************************************/
-#define BCHP_USB_CTRL_SETUP 0x00480200 /* Setup Register */
-#define BCHP_USB_CTRL_PLL_CTL 0x00480204 /* PLL Control Register */
-#define BCHP_USB_CTRL_FLADJ_VALUE 0x00480208 /* Frame Adjust Value */
-#define BCHP_USB_CTRL_EBRIDGE 0x0048020c /* Control Register for EHCI Bridge */
-#define BCHP_USB_CTRL_OBRIDGE 0x00480210 /* Control Register for OHCI Bridge */
-#define BCHP_USB_CTRL_MDIO 0x00480214 /* MDIO Interface Programming Register */
-#define BCHP_USB_CTRL_MDIO2 0x00480218 /* MDIO Interface Read Register */
-#define BCHP_USB_CTRL_TEST_PORT_CTL 0x0048021c /* Test Port Control Register */
-#define BCHP_USB_CTRL_USB_SIMCTL 0x00480220 /* Simulation Register */
-#define BCHP_USB_CTRL_USB_TESTCTL 0x00480224 /* Throutput Test Control */
-#define BCHP_USB_CTRL_USB_TESTMON 0x00480228 /* Throughput Test Monitor */
-#define BCHP_USB_CTRL_UTMI_CTL_1 0x0048022c /* UTMI Control Register */
-#define BCHP_USB_CTRL_UTMI_CTL_2 0x00480230 /* UTMI Control 2 Register */
-#define BCHP_USB_CTRL_USB_PM 0x00480234 /* Power Management Register */
-#define BCHP_USB_CTRL_USB_PM_STATUS 0x00480238 /* usb20 Power Management Status Register */
-#define BCHP_USB_CTRL_OHCI_ADDR_EXT 0x0048023c /* OHCI ADDRESS Extension */
-#define BCHP_USB_CTRL_PLL_LDO_CTL 0x00480240 /* 28NM USBPHY LDO Control */
-#define BCHP_USB_CTRL_PLL_LDO_PLLBIAS 0x00480244 /* 28NM USBPHY PLLBIAS Control */
-#define BCHP_USB_CTRL_PLL_AFE_BG_CNTL 0x00480248 /* 28NM USBPHY AFE Bandgap Control */
-#define BCHP_USB_CTRL_AFE_USBIO_TST 0x0048024c /* 28NM USBPHY AFE Bandgap Control */
-#define BCHP_USB_CTRL_PLL_NDIV_FRAC 0x00480250 /* PLL Feedback Divider Control Register */
-#define BCHP_USB_CTRL_TP_DIAG 0x00480254 /* diagnostic for tp bus */
-#define BCHP_USB_CTRL_SPARE3 0x00480258 /* Spare1 Register for future use */
-#define BCHP_USB_CTRL_SPARE4 0x0048025c /* Spare1 Register for future use */
-#define BCHP_USB_CTRL_USB30_CTL1 0x00480260 /* USB30 CONTROL Register 1 */
-#define BCHP_USB_CTRL_USB30_CTL2 0x00480264 /* USB30 CONTROL Register 2 */
-#define BCHP_USB_CTRL_USB30_CTL3 0x00480268 /* USB30 CONTROL Register 3 */
-#define BCHP_USB_CTRL_USB30_CTL4 0x0048026c /* USB30 CONTROL Register 4 */
-#define BCHP_USB_CTRL_USB30_PCTL 0x00480270 /* USB30 PORT CONTROL Register */
-#define BCHP_USB_CTRL_USB30_CTL5 0x00480274 /* USB30 CONTROL Register 5 */
-#define BCHP_USB_CTRL_SPARE5 0x00480278 /* Spare1 Register for future use */
-#define BCHP_USB_CTRL_SPARE6 0x0048027c /* Spare2 Register for future use */
-#define BCHP_USB_CTRL_SCB0_BASE_RANGE 0x004802a0 /* SCB0 base start and end address */
-#define BCHP_USB_CTRL_SCB1_BASE_RANGE 0x004802a4 /* SCB1 base start and end address */
-#define BCHP_USB_CTRL_SCB2_BASE_RANGE 0x004802a8 /* SCB2 base start and end address */
-#define BCHP_USB_CTRL_SCB0_EXTN_RANGE 0x004802ac /* SCB0 extn start and end address */
-#define BCHP_USB_CTRL_SCB1_EXTN_RANGE 0x004802b0 /* SCB1 extn start and end address */
-#define BCHP_USB_CTRL_SCB2_EXTN_RANGE 0x004802b4 /* SCB2 extn start and end address */
-#define BCHP_USB_CTRL_USB_REVID 0x004802fc /* USB REVID */
+#define BCHP_USB_CTRL_SETUP 0x00480200 /* [RW] Setup Register */
+#define BCHP_USB_CTRL_PLL_CTL 0x00480204 /* [RW] PLL Control Register */
+#define BCHP_USB_CTRL_FLADJ_VALUE 0x00480208 /* [RW] Frame Adjust Value */
+#define BCHP_USB_CTRL_EBRIDGE 0x0048020c /* [RW] Control Register for EHCI Bridge */
+#define BCHP_USB_CTRL_OBRIDGE 0x00480210 /* [RW] Control Register for OHCI Bridge */
+#define BCHP_USB_CTRL_MDIO 0x00480214 /* [RW] MDIO Interface Programming Register */
+#define BCHP_USB_CTRL_MDIO2 0x00480218 /* [RO] MDIO Interface Read Register */
+#define BCHP_USB_CTRL_TEST_PORT_CTL 0x0048021c /* [RW] Test Port Control Register */
+#define BCHP_USB_CTRL_USB_SIMCTL 0x00480220 /* [RW] Simulation Register */
+#define BCHP_USB_CTRL_USB_TESTCTL 0x00480224 /* [RW] Throutput Test Control */
+#define BCHP_USB_CTRL_USB_TESTMON 0x00480228 /* [RO] Throughput Test Monitor */
+#define BCHP_USB_CTRL_UTMI_CTL_1 0x0048022c /* [RW] UTMI Control Register */
+#define BCHP_USB_CTRL_UTMI_CTL_2 0x00480230 /* [RW] UTMI Control 2 Register */
+#define BCHP_USB_CTRL_USB_PM 0x00480234 /* [RW] Power Management Register */
+#define BCHP_USB_CTRL_USB_PM_STATUS 0x00480238 /* [RW] usb20 Power Management Status Register */
+#define BCHP_USB_CTRL_OHCI_ADDR_EXT 0x0048023c /* [RW] OHCI ADDRESS Extension */
+#define BCHP_USB_CTRL_PLL_LDO_CTL 0x00480240 /* [RW] 28NM USBPHY LDO Control */
+#define BCHP_USB_CTRL_PLL_LDO_PLLBIAS 0x00480244 /* [RW] 28NM USBPHY PLLBIAS Control */
+#define BCHP_USB_CTRL_PLL_AFE_BG_CNTL 0x00480248 /* [RW] 28NM USBPHY AFE Bandgap Control */
+#define BCHP_USB_CTRL_AFE_USBIO_TST 0x0048024c /* [RW] 28NM USBPHY AFE Bandgap Control */
+#define BCHP_USB_CTRL_PLL_NDIV_FRAC 0x00480250 /* [RW] PLL Feedback Divider Control Register */
+#define BCHP_USB_CTRL_TP_DIAG 0x00480254 /* [RW] diagnostic for tp bus */
+#define BCHP_USB_CTRL_SPARE3 0x00480258 /* [RW] Spare1 Register for future use */
+#define BCHP_USB_CTRL_SPARE4 0x0048025c /* [RW] Spare1 Register for future use */
+#define BCHP_USB_CTRL_USB30_CTL1 0x00480260 /* [RW] USB30 CONTROL Register 1 */
+#define BCHP_USB_CTRL_USB30_CTL2 0x00480264 /* [RW] USB30 CONTROL Register 2 */
+#define BCHP_USB_CTRL_USB30_CTL3 0x00480268 /* [RW] USB30 CONTROL Register 3 */
+#define BCHP_USB_CTRL_USB30_CTL4 0x0048026c /* [RW] USB30 CONTROL Register 4 */
+#define BCHP_USB_CTRL_USB30_PCTL 0x00480270 /* [RW] USB30 PORT CONTROL Register */
+#define BCHP_USB_CTRL_USB30_CTL5 0x00480274 /* [RW] USB30 CONTROL Register 5 */
+#define BCHP_USB_CTRL_SPARE5 0x00480278 /* [RW] Spare1 Register for future use */
+#define BCHP_USB_CTRL_SPARE6 0x0048027c /* [RW] Spare2 Register for future use */
+#define BCHP_USB_CTRL_SCB0_BASE_RANGE 0x004802a0 /* [RW] SCB0 base start and end address */
+#define BCHP_USB_CTRL_SCB1_BASE_RANGE 0x004802a4 /* [RW] SCB1 base start and end address */
+#define BCHP_USB_CTRL_SCB2_BASE_RANGE 0x004802a8 /* [RW] SCB2 base start and end address */
+#define BCHP_USB_CTRL_SCB0_EXTN_RANGE 0x004802ac /* [RW] SCB0 extn start and end address */
+#define BCHP_USB_CTRL_SCB1_EXTN_RANGE 0x004802b0 /* [RW] SCB1 extn start and end address */
+#define BCHP_USB_CTRL_SCB2_EXTN_RANGE 0x004802b4 /* [RW] SCB2 extn start and end address */
+#define BCHP_USB_CTRL_USB_REVID 0x004802fc /* [RO] USB REVID */
/***************************************************************************
*SETUP - Setup Register
@@ -208,10 +201,10 @@
/***************************************************************************
*PLL_CTL - PLL Control Register
***************************************************************************/
-/* USB_CTRL :: PLL_CTL :: PLL_IDDQ_PWRDN [31:31] */
-#define BCHP_USB_CTRL_PLL_CTL_PLL_IDDQ_PWRDN_MASK 0x80000000
-#define BCHP_USB_CTRL_PLL_CTL_PLL_IDDQ_PWRDN_SHIFT 31
-#define BCHP_USB_CTRL_PLL_CTL_PLL_IDDQ_PWRDN_DEFAULT 0x00000000
+/* USB_CTRL :: PLL_CTL :: PLLCTL_SPARE [31:31] */
+#define BCHP_USB_CTRL_PLL_CTL_PLLCTL_SPARE_MASK 0x80000000
+#define BCHP_USB_CTRL_PLL_CTL_PLLCTL_SPARE_SHIFT 31
+#define BCHP_USB_CTRL_PLL_CTL_PLLCTL_SPARE_DEFAULT 0x00000000
/* USB_CTRL :: PLL_CTL :: PLL_RESETB [30:30] */
#define BCHP_USB_CTRL_PLL_CTL_PLL_RESETB_MASK 0x40000000
@@ -352,16 +345,11 @@
#define BCHP_USB_CTRL_OBRIDGE_obr_size_sel_SHIFT 28
#define BCHP_USB_CTRL_OBRIDGE_obr_size_sel_DEFAULT 0x00000000
-/* USB_CTRL :: OBRIDGE :: OBR_SPARE [27:18] */
-#define BCHP_USB_CTRL_OBRIDGE_OBR_SPARE_MASK 0x0ffc0000
-#define BCHP_USB_CTRL_OBRIDGE_OBR_SPARE_SHIFT 18
+/* USB_CTRL :: OBRIDGE :: OBR_SPARE [27:17] */
+#define BCHP_USB_CTRL_OBRIDGE_OBR_SPARE_MASK 0x0ffe0000
+#define BCHP_USB_CTRL_OBRIDGE_OBR_SPARE_SHIFT 17
#define BCHP_USB_CTRL_OBRIDGE_OBR_SPARE_DEFAULT 0x00000000
-/* USB_CTRL :: OBRIDGE :: OSTOP_SCB_REQ [17:17] */
-#define BCHP_USB_CTRL_OBRIDGE_OSTOP_SCB_REQ_MASK 0x00020000
-#define BCHP_USB_CTRL_OBRIDGE_OSTOP_SCB_REQ_SHIFT 17
-#define BCHP_USB_CTRL_OBRIDGE_OSTOP_SCB_REQ_DEFAULT 0x00000000
-
/* USB_CTRL :: OBRIDGE :: OBR_RD_THRESH [16:12] */
#define BCHP_USB_CTRL_OBRIDGE_OBR_RD_THRESH_MASK 0x0001f000
#define BCHP_USB_CTRL_OBRIDGE_OBR_RD_THRESH_SHIFT 12
@@ -802,10 +790,10 @@
/***************************************************************************
*USB_PM - Power Management Register
***************************************************************************/
-/* USB_CTRL :: USB_PM :: xdc_soft_resetb [31:31] */
-#define BCHP_USB_CTRL_USB_PM_xdc_soft_resetb_MASK 0x80000000
-#define BCHP_USB_CTRL_USB_PM_xdc_soft_resetb_SHIFT 31
-#define BCHP_USB_CTRL_USB_PM_xdc_soft_resetb_DEFAULT 0x00000001
+/* USB_CTRL :: USB_PM :: USB_PWRDN [31:31] */
+#define BCHP_USB_CTRL_USB_PM_USB_PWRDN_MASK 0x80000000
+#define BCHP_USB_CTRL_USB_PM_USB_PWRDN_SHIFT 31
+#define BCHP_USB_CTRL_USB_PM_USB_PWRDN_DEFAULT 0x00000001
/* USB_CTRL :: USB_PM :: xhc_soft_resetb [30:30] */
#define BCHP_USB_CTRL_USB_PM_xhc_soft_resetb_MASK 0x40000000
diff --git a/include/linux/brcmstb/74371a0/bchp_usb_xhci_ec.h b/include/linux/brcmstb/74371a0/bchp_usb_xhci_ec.h
new file mode 100644
index 0000000..b7b7b0b
--- /dev/null
+++ b/include/linux/brcmstb/74371a0/bchp_usb_xhci_ec.h
@@ -0,0 +1,384 @@
+/***************************************************************************
+ * Copyright (c) 1999-2014, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ * DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date: Generated on Thu Feb 19 03:16:48 2015
+ * Full Compile MD5 Checksum a5e4ec59635428e29d8011e790dc32b8
+ * (minus title and desc)
+ * MD5 Checksum db361cb744c5e0e017160da1bb1a3291
+ *
+ * Compiled with: RDB Utility combo_header.pl
+ * RDB.pm 15517
+ * unknown unknown
+ * Perl Interpreter 5.008008
+ * Operating System linux
+ *
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_USB_XHCI_EC_H__
+#define BCHP_USB_XHCI_EC_H__
+
+/***************************************************************************
+ *USB_XHCI_EC - USB XHCI Extended Capability Registers
+ ***************************************************************************/
+#define BCHP_USB_XHCI_EC_ECHSPT 0x00481940 /* [RW] Extended Capability Supported Protocols (SPT) Header */
+#define BCHP_USB_XHCI_EC_PNSTR 0x00481944 /* [RW] Extended Capability SPT Protocol name string register */
+#define BCHP_USB_XHCI_EC_PSUM 0x00481948 /* [RW] Extended Capability SPT Protocol summary register */
+#define BCHP_USB_XHCI_EC_ECHPMG 0x00481960 /* [RW] Extended Capability Power Management (PMG) Header */
+#define BCHP_USB_XHCI_EC_PMGCSD 0x00481964 /* [RW] Extended Capability PMG control, status and data register */
+#define BCHP_USB_XHCI_EC_ECHIOV 0x00481968 /* [RW] Extended Capability IO Virtualization (IOV) */
+#define BCHP_USB_XHCI_EC_ECHMSI 0x00481ae8 /* [RW] Extended Capability Message Signaled Interrupt (MSI) */
+#define BCHP_USB_XHCI_EC_ECHDBC 0x00481af8 /* [RW] Extended Capability Debug (DBC) */
+#define BCHP_USB_XHCI_EC_ECHRSVD 0x00481b38 /* [RW] Extended Capability Reserved */
+#define BCHP_USB_XHCI_EC_ECHCTT 0x00481bf0 /* [RW] Extended Capability Controller Testing */
+#define BCHP_USB_XHCI_EC_ECHBIU 0x00481c00 /* [RW] Extended Capability BIU Header */
+#define BCHP_USB_XHCI_EC_BIUSPC 0x00481c04 /* [RW] Extended Capability BIU Bus Specification */
+#define BCHP_USB_XHCI_EC_BIUSPC1 0x00481c08 /* [RW] Extended Capability BIU AXIWRA */
+#define BCHP_USB_XHCI_EC_BIUSPC2 0x00481c0c /* [RW] Extended Capability BIU AXIRDA */
+#define BCHP_USB_XHCI_EC_BIULPM 0x00481c10 /* [RW] Extended Capability BIU AXILPM */
+#define BCHP_USB_XHCI_EC_ECHCSR 0x00481c20 /* [RW] Extended capability CSR Header */
+#define BCHP_USB_XHCI_EC_ECHAIU 0x00481c30 /* [RW] Extended Capability AIU Header */
+#define BCHP_USB_XHCI_EC_AIUDMA 0x00481c34 /* [RW] Extended Capability AIU DMA priority specification */
+#define BCHP_USB_XHCI_EC_AIUSTM 0x00481c38 /* [RW] Extended Capability AIU Bulk stream configuration */
+#define BCHP_USB_XHCI_EC_AIUCFG 0x00481c3c /* [RW] Extended Capability AIU Resource Configuration and Policy Spec */
+#define BCHP_USB_XHCI_EC_ECHFSC 0x00481c40 /* [RW] Extended Capability Fifo and Sram Controller (FSC) Header */
+#define BCHP_USB_XHCI_EC_FSCPOC 0x00481c54 /* [RW] Extended Capability FSC Periodic OUT Channel Configuration */
+#define BCHP_USB_XHCI_EC_FSCGOC 0x00481c58 /* [RW] Extended Capability FSC Generic OUT Channel Configuration */
+#define BCHP_USB_XHCI_EC_FSCNOC 0x00481c5c /* [RW] Extended Capability FSC Non-Periodic OUT Channel Configuration */
+#define BCHP_USB_XHCI_EC_FSCAIC 0x00481c60 /* [RW] Extended Capability FSC All IN Channel Configuration */
+#define BCHP_USB_XHCI_EC_FSCGIC 0x00481c68 /* [RW] Extended Capability FSC Generic IN Channel Configuration */
+#define BCHP_USB_XHCI_EC_FSCNIC 0x00481c6c /* [RW] Extended Capability FSC Non-Periodic IN Channel Configuration */
+#define BCHP_USB_XHCI_EC_ECHPRT 0x00481c70 /* [RW] Extended capability SS Protocol Layer (PRT) Header */
+#define BCHP_USB_XHCI_EC_PRTHSC 0x00481c78 /* [RW] Extended capability PRT histogram timer and control */
+#define BCHP_USB_XHCI_EC_PRTHSR 0x00481c7c /* [RW] Extended capability PRT histogram reports */
+#define BCHP_USB_XHCI_EC_ECHSRH 0x00481c80 /* [RW] Extended capability SS Root Hub (SRH) Header */
+#define BCHP_USB_XHCI_EC_SRHDES 0x00481c84 /* [RW] Extended capability SRH SS Root Hub descriptor */
+#define BCHP_USB_XHCI_EC_ECHPHY 0x00481cb0 /* [RW] Extended capability SS Physical Layer (PHY) Header */
+#define BCHP_USB_XHCI_EC_ECHRSVD2 0x00481cc0 /* [RW] Extended capability Reserved 2 */
+#define BCHP_USB_XHCI_EC_ECHHRH 0x00481f50 /* [RW] Extended Capability HS Root Hub (HRH) Header */
+#define BCHP_USB_XHCI_EC_ECHU2P 0x00481f80 /* [RW] Extended Capability USB20 Physical Layer Hub (HRH) Header */
+#define BCHP_USB_XHCI_EC_ECHIRA 0x00481f90 /* [RW] Extended Capability Internal Register Access (IRA) Header */
+#define BCHP_USB_XHCI_EC_IRAADR 0x00481f98 /* [RW] Extended Capability IRA Address Register */
+#define BCHP_USB_XHCI_EC_IRADAT 0x00481f9c /* [RW] Extended Capability IRA Data Register */
+#define BCHP_USB_XHCI_EC_ECHHST 0x00481fa0 /* [RW] Extended Capability Host Operation (HST) Header */
+#define BCHP_USB_XHCI_EC_ECHRBV 0x00481fb0 /* [RW] Extended Capability Release and Build Version (RBV) Header */
+#define BCHP_USB_XHCI_EC_ECHSPARE 0x00481ffc /* [RW] Extended Capability SPARE */
+
+/***************************************************************************
+ *ECHSPT - Extended Capability Supported Protocols (SPT) Header
+ ***************************************************************************/
+/* USB_XHCI_EC :: ECHSPT :: NA [31:00] */
+#define BCHP_USB_XHCI_EC_ECHSPT_NA_MASK 0xffffffff
+#define BCHP_USB_XHCI_EC_ECHSPT_NA_SHIFT 0
+
+/***************************************************************************
+ *PNSTR - Extended Capability SPT Protocol name string register
+ ***************************************************************************/
+/* USB_XHCI_EC :: PNSTR :: NA [31:00] */
+#define BCHP_USB_XHCI_EC_PNSTR_NA_MASK 0xffffffff
+#define BCHP_USB_XHCI_EC_PNSTR_NA_SHIFT 0
+
+/***************************************************************************
+ *PSUM - Extended Capability SPT Protocol summary register
+ ***************************************************************************/
+/* USB_XHCI_EC :: PSUM :: NA [31:00] */
+#define BCHP_USB_XHCI_EC_PSUM_NA_MASK 0xffffffff
+#define BCHP_USB_XHCI_EC_PSUM_NA_SHIFT 0
+
+/***************************************************************************
+ *ECHPMG - Extended Capability Power Management (PMG) Header
+ ***************************************************************************/
+/* USB_XHCI_EC :: ECHPMG :: NA [31:00] */
+#define BCHP_USB_XHCI_EC_ECHPMG_NA_MASK 0xffffffff
+#define BCHP_USB_XHCI_EC_ECHPMG_NA_SHIFT 0
+
+/***************************************************************************
+ *PMGCSD - Extended Capability PMG control, status and data register
+ ***************************************************************************/
+/* USB_XHCI_EC :: PMGCSD :: NA [31:00] */
+#define BCHP_USB_XHCI_EC_PMGCSD_NA_MASK 0xffffffff
+#define BCHP_USB_XHCI_EC_PMGCSD_NA_SHIFT 0
+
+/***************************************************************************
+ *ECHIOV - Extended Capability IO Virtualization (IOV)
+ ***************************************************************************/
+/* USB_XHCI_EC :: ECHIOV :: NA [31:00] */
+#define BCHP_USB_XHCI_EC_ECHIOV_NA_MASK 0xffffffff
+#define BCHP_USB_XHCI_EC_ECHIOV_NA_SHIFT 0
+
+/***************************************************************************
+ *ECHMSI - Extended Capability Message Signaled Interrupt (MSI)
+ ***************************************************************************/
+/* USB_XHCI_EC :: ECHMSI :: NA [31:00] */
+#define BCHP_USB_XHCI_EC_ECHMSI_NA_MASK 0xffffffff
+#define BCHP_USB_XHCI_EC_ECHMSI_NA_SHIFT 0
+
+/***************************************************************************
+ *ECHDBC - Extended Capability Debug (DBC)
+ ***************************************************************************/
+/* USB_XHCI_EC :: ECHDBC :: NA [31:00] */
+#define BCHP_USB_XHCI_EC_ECHDBC_NA_MASK 0xffffffff
+#define BCHP_USB_XHCI_EC_ECHDBC_NA_SHIFT 0
+
+/***************************************************************************
+ *ECHRSVD - Extended Capability Reserved
+ ***************************************************************************/
+/* USB_XHCI_EC :: ECHRSVD :: NA [31:00] */
+#define BCHP_USB_XHCI_EC_ECHRSVD_NA_MASK 0xffffffff
+#define BCHP_USB_XHCI_EC_ECHRSVD_NA_SHIFT 0
+
+/***************************************************************************
+ *ECHCTT - Extended Capability Controller Testing
+ ***************************************************************************/
+/* USB_XHCI_EC :: ECHCTT :: NA [31:00] */
+#define BCHP_USB_XHCI_EC_ECHCTT_NA_MASK 0xffffffff
+#define BCHP_USB_XHCI_EC_ECHCTT_NA_SHIFT 0
+
+/***************************************************************************
+ *ECHBIU - Extended Capability BIU Header
+ ***************************************************************************/
+/* USB_XHCI_EC :: ECHBIU :: NA [31:00] */
+#define BCHP_USB_XHCI_EC_ECHBIU_NA_MASK 0xffffffff
+#define BCHP_USB_XHCI_EC_ECHBIU_NA_SHIFT 0
+
+/***************************************************************************
+ *BIUSPC - Extended Capability BIU Bus Specification
+ ***************************************************************************/
+/* USB_XHCI_EC :: BIUSPC :: NA [31:00] */
+#define BCHP_USB_XHCI_EC_BIUSPC_NA_MASK 0xffffffff
+#define BCHP_USB_XHCI_EC_BIUSPC_NA_SHIFT 0
+
+/***************************************************************************
+ *BIUSPC1 - Extended Capability BIU AXIWRA
+ ***************************************************************************/
+/* USB_XHCI_EC :: BIUSPC1 :: NA [31:00] */
+#define BCHP_USB_XHCI_EC_BIUSPC1_NA_MASK 0xffffffff
+#define BCHP_USB_XHCI_EC_BIUSPC1_NA_SHIFT 0
+
+/***************************************************************************
+ *BIUSPC2 - Extended Capability BIU AXIRDA
+ ***************************************************************************/
+/* USB_XHCI_EC :: BIUSPC2 :: NA [31:00] */
+#define BCHP_USB_XHCI_EC_BIUSPC2_NA_MASK 0xffffffff
+#define BCHP_USB_XHCI_EC_BIUSPC2_NA_SHIFT 0
+
+/***************************************************************************
+ *BIULPM - Extended Capability BIU AXILPM
+ ***************************************************************************/
+/* USB_XHCI_EC :: BIULPM :: NA [31:00] */
+#define BCHP_USB_XHCI_EC_BIULPM_NA_MASK 0xffffffff
+#define BCHP_USB_XHCI_EC_BIULPM_NA_SHIFT 0
+
+/***************************************************************************
+ *ECHCSR - Extended capability CSR Header
+ ***************************************************************************/
+/* USB_XHCI_EC :: ECHCSR :: NA [31:00] */
+#define BCHP_USB_XHCI_EC_ECHCSR_NA_MASK 0xffffffff
+#define BCHP_USB_XHCI_EC_ECHCSR_NA_SHIFT 0
+
+/***************************************************************************
+ *ECHAIU - Extended Capability AIU Header
+ ***************************************************************************/
+/* USB_XHCI_EC :: ECHAIU :: NA [31:00] */
+#define BCHP_USB_XHCI_EC_ECHAIU_NA_MASK 0xffffffff
+#define BCHP_USB_XHCI_EC_ECHAIU_NA_SHIFT 0
+
+/***************************************************************************
+ *AIUDMA - Extended Capability AIU DMA priority specification
+ ***************************************************************************/
+/* USB_XHCI_EC :: AIUDMA :: NA [31:00] */
+#define BCHP_USB_XHCI_EC_AIUDMA_NA_MASK 0xffffffff
+#define BCHP_USB_XHCI_EC_AIUDMA_NA_SHIFT 0
+
+/***************************************************************************
+ *AIUSTM - Extended Capability AIU Bulk stream configuration
+ ***************************************************************************/
+/* USB_XHCI_EC :: AIUSTM :: NA [31:00] */
+#define BCHP_USB_XHCI_EC_AIUSTM_NA_MASK 0xffffffff
+#define BCHP_USB_XHCI_EC_AIUSTM_NA_SHIFT 0
+
+/***************************************************************************
+ *AIUCFG - Extended Capability AIU Resource Configuration and Policy Spec
+ ***************************************************************************/
+/* USB_XHCI_EC :: AIUCFG :: NA [31:00] */
+#define BCHP_USB_XHCI_EC_AIUCFG_NA_MASK 0xffffffff
+#define BCHP_USB_XHCI_EC_AIUCFG_NA_SHIFT 0
+
+/***************************************************************************
+ *ECHFSC - Extended Capability Fifo and Sram Controller (FSC) Header
+ ***************************************************************************/
+/* USB_XHCI_EC :: ECHFSC :: NA [31:00] */
+#define BCHP_USB_XHCI_EC_ECHFSC_NA_MASK 0xffffffff
+#define BCHP_USB_XHCI_EC_ECHFSC_NA_SHIFT 0
+
+/***************************************************************************
+ *FSCPOC - Extended Capability FSC Periodic OUT Channel Configuration
+ ***************************************************************************/
+/* USB_XHCI_EC :: FSCPOC :: NA [31:00] */
+#define BCHP_USB_XHCI_EC_FSCPOC_NA_MASK 0xffffffff
+#define BCHP_USB_XHCI_EC_FSCPOC_NA_SHIFT 0
+
+/***************************************************************************
+ *FSCGOC - Extended Capability FSC Generic OUT Channel Configuration
+ ***************************************************************************/
+/* USB_XHCI_EC :: FSCGOC :: NA [31:00] */
+#define BCHP_USB_XHCI_EC_FSCGOC_NA_MASK 0xffffffff
+#define BCHP_USB_XHCI_EC_FSCGOC_NA_SHIFT 0
+
+/***************************************************************************
+ *FSCNOC - Extended Capability FSC Non-Periodic OUT Channel Configuration
+ ***************************************************************************/
+/* USB_XHCI_EC :: FSCNOC :: NA [31:00] */
+#define BCHP_USB_XHCI_EC_FSCNOC_NA_MASK 0xffffffff
+#define BCHP_USB_XHCI_EC_FSCNOC_NA_SHIFT 0
+
+/***************************************************************************
+ *FSCAIC - Extended Capability FSC All IN Channel Configuration
+ ***************************************************************************/
+/* USB_XHCI_EC :: FSCAIC :: NA [31:00] */
+#define BCHP_USB_XHCI_EC_FSCAIC_NA_MASK 0xffffffff
+#define BCHP_USB_XHCI_EC_FSCAIC_NA_SHIFT 0
+
+/***************************************************************************
+ *FSCGIC - Extended Capability FSC Generic IN Channel Configuration
+ ***************************************************************************/
+/* USB_XHCI_EC :: FSCGIC :: NA [31:00] */
+#define BCHP_USB_XHCI_EC_FSCGIC_NA_MASK 0xffffffff
+#define BCHP_USB_XHCI_EC_FSCGIC_NA_SHIFT 0
+
+/***************************************************************************
+ *FSCNIC - Extended Capability FSC Non-Periodic IN Channel Configuration
+ ***************************************************************************/
+/* USB_XHCI_EC :: FSCNIC :: NA [31:00] */
+#define BCHP_USB_XHCI_EC_FSCNIC_NA_MASK 0xffffffff
+#define BCHP_USB_XHCI_EC_FSCNIC_NA_SHIFT 0
+
+/***************************************************************************
+ *ECHPRT - Extended capability SS Protocol Layer (PRT) Header
+ ***************************************************************************/
+/* USB_XHCI_EC :: ECHPRT :: NA [31:00] */
+#define BCHP_USB_XHCI_EC_ECHPRT_NA_MASK 0xffffffff
+#define BCHP_USB_XHCI_EC_ECHPRT_NA_SHIFT 0
+
+/***************************************************************************
+ *PRTHSC - Extended capability PRT histogram timer and control
+ ***************************************************************************/
+/* USB_XHCI_EC :: PRTHSC :: NA [31:00] */
+#define BCHP_USB_XHCI_EC_PRTHSC_NA_MASK 0xffffffff
+#define BCHP_USB_XHCI_EC_PRTHSC_NA_SHIFT 0
+
+/***************************************************************************
+ *PRTHSR - Extended capability PRT histogram reports
+ ***************************************************************************/
+/* USB_XHCI_EC :: PRTHSR :: NA [31:00] */
+#define BCHP_USB_XHCI_EC_PRTHSR_NA_MASK 0xffffffff
+#define BCHP_USB_XHCI_EC_PRTHSR_NA_SHIFT 0
+
+/***************************************************************************
+ *ECHSRH - Extended capability SS Root Hub (SRH) Header
+ ***************************************************************************/
+/* USB_XHCI_EC :: ECHSRH :: NA [31:00] */
+#define BCHP_USB_XHCI_EC_ECHSRH_NA_MASK 0xffffffff
+#define BCHP_USB_XHCI_EC_ECHSRH_NA_SHIFT 0
+
+/***************************************************************************
+ *SRHDES - Extended capability SRH SS Root Hub descriptor
+ ***************************************************************************/
+/* USB_XHCI_EC :: SRHDES :: NA [31:00] */
+#define BCHP_USB_XHCI_EC_SRHDES_NA_MASK 0xffffffff
+#define BCHP_USB_XHCI_EC_SRHDES_NA_SHIFT 0
+
+/***************************************************************************
+ *ECHPHY - Extended capability SS Physical Layer (PHY) Header
+ ***************************************************************************/
+/* USB_XHCI_EC :: ECHPHY :: NA [31:00] */
+#define BCHP_USB_XHCI_EC_ECHPHY_NA_MASK 0xffffffff
+#define BCHP_USB_XHCI_EC_ECHPHY_NA_SHIFT 0
+
+/***************************************************************************
+ *ECHRSVD2 - Extended capability Reserved 2
+ ***************************************************************************/
+/* USB_XHCI_EC :: ECHRSVD2 :: NA [31:00] */
+#define BCHP_USB_XHCI_EC_ECHRSVD2_NA_MASK 0xffffffff
+#define BCHP_USB_XHCI_EC_ECHRSVD2_NA_SHIFT 0
+
+/***************************************************************************
+ *ECHHRH - Extended Capability HS Root Hub (HRH) Header
+ ***************************************************************************/
+/* USB_XHCI_EC :: ECHHRH :: NA [31:00] */
+#define BCHP_USB_XHCI_EC_ECHHRH_NA_MASK 0xffffffff
+#define BCHP_USB_XHCI_EC_ECHHRH_NA_SHIFT 0
+
+/***************************************************************************
+ *ECHU2P - Extended Capability USB20 Physical Layer Hub (HRH) Header
+ ***************************************************************************/
+/* USB_XHCI_EC :: ECHU2P :: NA [31:00] */
+#define BCHP_USB_XHCI_EC_ECHU2P_NA_MASK 0xffffffff
+#define BCHP_USB_XHCI_EC_ECHU2P_NA_SHIFT 0
+
+/***************************************************************************
+ *ECHIRA - Extended Capability Internal Register Access (IRA) Header
+ ***************************************************************************/
+/* USB_XHCI_EC :: ECHIRA :: NA [31:00] */
+#define BCHP_USB_XHCI_EC_ECHIRA_NA_MASK 0xffffffff
+#define BCHP_USB_XHCI_EC_ECHIRA_NA_SHIFT 0
+
+/***************************************************************************
+ *IRAADR - Extended Capability IRA Address Register
+ ***************************************************************************/
+/* USB_XHCI_EC :: IRAADR :: NA [31:00] */
+#define BCHP_USB_XHCI_EC_IRAADR_NA_MASK 0xffffffff
+#define BCHP_USB_XHCI_EC_IRAADR_NA_SHIFT 0
+
+/***************************************************************************
+ *IRADAT - Extended Capability IRA Data Register
+ ***************************************************************************/
+/* USB_XHCI_EC :: IRADAT :: NA [31:00] */
+#define BCHP_USB_XHCI_EC_IRADAT_NA_MASK 0xffffffff
+#define BCHP_USB_XHCI_EC_IRADAT_NA_SHIFT 0
+
+/***************************************************************************
+ *ECHHST - Extended Capability Host Operation (HST) Header
+ ***************************************************************************/
+/* USB_XHCI_EC :: ECHHST :: NA [31:00] */
+#define BCHP_USB_XHCI_EC_ECHHST_NA_MASK 0xffffffff
+#define BCHP_USB_XHCI_EC_ECHHST_NA_SHIFT 0
+
+/***************************************************************************
+ *ECHRBV - Extended Capability Release and Build Version (RBV) Header
+ ***************************************************************************/
+/* USB_XHCI_EC :: ECHRBV :: NA [31:00] */
+#define BCHP_USB_XHCI_EC_ECHRBV_NA_MASK 0xffffffff
+#define BCHP_USB_XHCI_EC_ECHRBV_NA_SHIFT 0
+
+/***************************************************************************
+ *ECHSPARE - Extended Capability SPARE
+ ***************************************************************************/
+/* USB_XHCI_EC :: ECHSPARE :: SPARE [31:00] */
+#define BCHP_USB_XHCI_EC_ECHSPARE_SPARE_MASK 0xffffffff
+#define BCHP_USB_XHCI_EC_ECHSPARE_SPARE_SHIFT 0
+#define BCHP_USB_XHCI_EC_ECHSPARE_SPARE_DEFAULT 0x00000000
+
+#endif /* #ifndef BCHP_USB_XHCI_EC_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7439a0/bchp_aon_ctrl.h b/include/linux/brcmstb/7439a0/bchp_aon_ctrl.h
deleted file mode 100644
index 9277f3d..0000000
--- a/include/linux/brcmstb/7439a0/bchp_aon_ctrl.h
+++ /dev/null
@@ -1,1639 +0,0 @@
-/***************************************************************************
- * Copyright (c) 1999-2013, Broadcom Corporation
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
- *
- * Module Description:
- * DO NOT EDIT THIS FILE DIRECTLY
- *
- * This module was generated magically with RDB from a source description
- * file. You must edit the source file for changes to be made to this file.
- *
- *
- * Date: Generated on Tue Apr 16 03:26:52 2013
- * MD5 Checksum d41d8cd98f00b204e9800998ecf8427e
- *
- * Compiled with: RDB Utility combo_header.pl
- * RDB Parser 3.0
- * unknown unknown
- * Perl Interpreter 5.008008
- * Operating System linux
- *
- * Revision History:
- *
- * $brcm_Log: $
- *
- ***************************************************************************/
-
-#ifndef BCHP_AON_CTRL_H__
-#define BCHP_AON_CTRL_H__
-
-/***************************************************************************
- *AON_CTRL - AON Control Registers
- ***************************************************************************/
-#define BCHP_AON_CTRL_RESET_CTRL 0x00410000 /* Reset Control register for AON */
-#define BCHP_AON_CTRL_PM_CTRL 0x00410004 /* Control register for Power Controller */
-#define BCHP_AON_CTRL_PM_STATUS 0x00410008 /* Status register for Power Controller */
-#define BCHP_AON_CTRL_PM_IRQ_INPUT_STATUS 0x0041000c /* Power Management IRQ input status */
-#define BCHP_AON_CTRL_PM_CPU_WAIT_COUNT 0x00410010 /* Power Management Wait counter in place of Wait for Host CPU IRQ */
-#define BCHP_AON_CTRL_PM_CPU_GUARDBAND_TIMER 0x00410014 /* Power Good Guardband Timer for Host CPU */
-#define BCHP_AON_CTRL_PM_S3_STANDBY_TIMER 0x00410018 /* Deep Standby Assertion Timer */
-#define BCHP_AON_CTRL_PM_S3_WAKEUP_TIMER 0x0041001c /* Deep Standby Wakeup Timer */
-#define BCHP_AON_CTRL_PM_FAST_PWRDN_PRECHARGE 0x00410020 /* Control register for Power Controller */
-#define BCHP_AON_CTRL_PM_LED_CTRL 0x00410024 /* LED set control register */
-#define BCHP_AON_CTRL_PM_LED_AUTO_ON_ENABLES 0x00410028 /* LED set control register */
-#define BCHP_AON_CTRL_HLCD_CTRL 0x00410030 /* HW LED Clock Driver Control */
-#define BCHP_AON_CTRL_SECOND_FRACTION_COUNTER 0x00410034 /* Second Fraction Counter Initial value */
-#define BCHP_AON_CTRL_TIME_COUNTER 0x00410038 /* Hour/Minute Counter Initial value */
-#define BCHP_AON_CTRL_LED_DIGIT_CODE_0 0x0041003c /* Digit Code for digit 0, 1, 2, 3 */
-#define BCHP_AON_CTRL_LED_DIGIT_CODE_1 0x00410040 /* Digit Code for digit 4, 5, 6, 7 */
-#define BCHP_AON_CTRL_LED_DIGIT_CODE_2 0x00410044 /* Digit Code for digit 8, 9 */
-#define BCHP_AON_CTRL_LED_DIGIT_ADDR_OFFSET 0x00410048 /* Hour MSD/LSD and minute MSD/LSD address offset */
-#define BCHP_AON_CTRL_LED_STATUS_CTRL 0x0041004c /* LED status control */
-#define BCHP_AON_CTRL_GENERAL_CTRL_0 0x00410050 /* General control register 0 */
-#define BCHP_AON_CTRL_GENERAL_STATUS_0 0x00410054 /* General status register 0 */
-#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0 0x00410058 /* General control register without scan 0 */
-#define BCHP_AON_CTRL_SPARE_CTRL_0 0x00410060 /* Spare control bits reserved for future use */
-#define BCHP_AON_CTRL_SPARE_CTRL_1 0x00410064 /* Spare control bits reserved for future use */
-#define BCHP_AON_CTRL_UNCLEARED_SCRATCH 0x00410068 /* Scratch register */
-#define BCHP_AON_CTRL_RESET_HISTORY 0x0041006c /* Reset History Register For AON */
-#define BCHP_AON_CTRL_NMI_CTRL 0x00410070 /* Control register for NMI */
-#define BCHP_AON_CTRL_ANA_XTAL_CONTROL 0x00410074 /* Ana xtal gisb control */
-#define BCHP_AON_CTRL_SUB_TEST_MODE_CTRL 0x00410078 /* Test_mode control register */
-#define BCHP_AON_CTRL_SUB_TEST_MODE 0x0041007c /* Register source for sub_test_mode */
-#define BCHP_AON_CTRL_LATCHED_TEST_MODE 0x00410080 /* Final latched testmode value */
-#define BCHP_AON_CTRL_LATCHED_SUB_TEST_MODE 0x00410084 /* Final latched sub-testmode value */
-#define BCHP_AON_CTRL_PM_INITIATE 0x00410088 /* Power down initiate */
-#define BCHP_AON_CTRL_HOST_MISC_CMDS 0x0041008c /* Power up restore */
-#define BCHP_AON_CTRL_ANA_XTAL_EXT_CML_CONTROL 0x00410090 /* Ana xtal external CML control */
-
-/***************************************************************************
- *RESET_CTRL - Reset Control register for AON
- ***************************************************************************/
-/* AON_CTRL :: RESET_CTRL :: reserved0 [31:04] */
-#define BCHP_AON_CTRL_RESET_CTRL_reserved0_MASK 0xfffffff0
-#define BCHP_AON_CTRL_RESET_CTRL_reserved0_SHIFT 4
-
-/* AON_CTRL :: RESET_CTRL :: front_panel_reset_enable_lock [03:03] */
-#define BCHP_AON_CTRL_RESET_CTRL_front_panel_reset_enable_lock_MASK 0x00000008
-#define BCHP_AON_CTRL_RESET_CTRL_front_panel_reset_enable_lock_SHIFT 3
-#define BCHP_AON_CTRL_RESET_CTRL_front_panel_reset_enable_lock_DEFAULT 0x00000000
-
-/* AON_CTRL :: RESET_CTRL :: front_panel_reset_enable [02:02] */
-#define BCHP_AON_CTRL_RESET_CTRL_front_panel_reset_enable_MASK 0x00000004
-#define BCHP_AON_CTRL_RESET_CTRL_front_panel_reset_enable_SHIFT 2
-#define BCHP_AON_CTRL_RESET_CTRL_front_panel_reset_enable_DEFAULT 0x00000000
-
-/* AON_CTRL :: RESET_CTRL :: front_panel_reset_polarity [01:01] */
-#define BCHP_AON_CTRL_RESET_CTRL_front_panel_reset_polarity_MASK 0x00000002
-#define BCHP_AON_CTRL_RESET_CTRL_front_panel_reset_polarity_SHIFT 1
-#define BCHP_AON_CTRL_RESET_CTRL_front_panel_reset_polarity_DEFAULT 0x00000000
-
-/* AON_CTRL :: RESET_CTRL :: clear_reset_history [00:00] */
-#define BCHP_AON_CTRL_RESET_CTRL_clear_reset_history_MASK 0x00000001
-#define BCHP_AON_CTRL_RESET_CTRL_clear_reset_history_SHIFT 0
-#define BCHP_AON_CTRL_RESET_CTRL_clear_reset_history_DEFAULT 0x00000000
-
-/***************************************************************************
- *PM_CTRL - Control register for Power Controller
- ***************************************************************************/
-/* AON_CTRL :: PM_CTRL :: reserved0 [31:08] */
-#define BCHP_AON_CTRL_PM_CTRL_reserved0_MASK 0xffffff00
-#define BCHP_AON_CTRL_PM_CTRL_reserved0_SHIFT 8
-
-/* AON_CTRL :: PM_CTRL :: min_s3_width_timer_bypass [07:07] */
-#define BCHP_AON_CTRL_PM_CTRL_min_s3_width_timer_bypass_MASK 0x00000080
-#define BCHP_AON_CTRL_PM_CTRL_min_s3_width_timer_bypass_SHIFT 7
-#define BCHP_AON_CTRL_PM_CTRL_min_s3_width_timer_bypass_DEFAULT 0x00000000
-
-/* AON_CTRL :: PM_CTRL :: pm_fast_power_down [06:06] */
-#define BCHP_AON_CTRL_PM_CTRL_pm_fast_power_down_MASK 0x00000040
-#define BCHP_AON_CTRL_PM_CTRL_pm_fast_power_down_SHIFT 6
-#define BCHP_AON_CTRL_PM_CTRL_pm_fast_power_down_DEFAULT 0x00000000
-
-/* AON_CTRL :: PM_CTRL :: pm_warm_boot [05:05] */
-#define BCHP_AON_CTRL_PM_CTRL_pm_warm_boot_MASK 0x00000020
-#define BCHP_AON_CTRL_PM_CTRL_pm_warm_boot_SHIFT 5
-#define BCHP_AON_CTRL_PM_CTRL_pm_warm_boot_DEFAULT 0x00000000
-
-/* AON_CTRL :: PM_CTRL :: pm_deep_standby [04:04] */
-#define BCHP_AON_CTRL_PM_CTRL_pm_deep_standby_MASK 0x00000010
-#define BCHP_AON_CTRL_PM_CTRL_pm_deep_standby_SHIFT 4
-#define BCHP_AON_CTRL_PM_CTRL_pm_deep_standby_DEFAULT 0x00000000
-
-/* AON_CTRL :: PM_CTRL :: pm_enable_cpu_pwrdn [03:03] */
-#define BCHP_AON_CTRL_PM_CTRL_pm_enable_cpu_pwrdn_MASK 0x00000008
-#define BCHP_AON_CTRL_PM_CTRL_pm_enable_cpu_pwrdn_SHIFT 3
-#define BCHP_AON_CTRL_PM_CTRL_pm_enable_cpu_pwrdn_DEFAULT 0x00000000
-
-/* AON_CTRL :: PM_CTRL :: pm_use_cpu_ready_ctrl [02:02] */
-#define BCHP_AON_CTRL_PM_CTRL_pm_use_cpu_ready_ctrl_MASK 0x00000004
-#define BCHP_AON_CTRL_PM_CTRL_pm_use_cpu_ready_ctrl_SHIFT 2
-#define BCHP_AON_CTRL_PM_CTRL_pm_use_cpu_ready_ctrl_DEFAULT 0x00000000
-
-/* AON_CTRL :: PM_CTRL :: pm_enable_pll_pwrdn [01:01] */
-#define BCHP_AON_CTRL_PM_CTRL_pm_enable_pll_pwrdn_MASK 0x00000002
-#define BCHP_AON_CTRL_PM_CTRL_pm_enable_pll_pwrdn_SHIFT 1
-#define BCHP_AON_CTRL_PM_CTRL_pm_enable_pll_pwrdn_DEFAULT 0x00000000
-
-/* AON_CTRL :: PM_CTRL :: pm_start_pwrdn [00:00] */
-#define BCHP_AON_CTRL_PM_CTRL_pm_start_pwrdn_MASK 0x00000001
-#define BCHP_AON_CTRL_PM_CTRL_pm_start_pwrdn_SHIFT 0
-
-/***************************************************************************
- *PM_STATUS - Status register for Power Controller
- ***************************************************************************/
-/* AON_CTRL :: PM_STATUS :: pm_wait_count_upper_bits [31:28] */
-#define BCHP_AON_CTRL_PM_STATUS_pm_wait_count_upper_bits_MASK 0xf0000000
-#define BCHP_AON_CTRL_PM_STATUS_pm_wait_count_upper_bits_SHIFT 28
-
-/* AON_CTRL :: PM_STATUS :: pm_wait_counter_active [27:27] */
-#define BCHP_AON_CTRL_PM_STATUS_pm_wait_counter_active_MASK 0x08000000
-#define BCHP_AON_CTRL_PM_STATUS_pm_wait_counter_active_SHIFT 27
-
-/* AON_CTRL :: PM_STATUS :: pm_power_down_cpu [26:26] */
-#define BCHP_AON_CTRL_PM_STATUS_pm_power_down_cpu_MASK 0x04000000
-#define BCHP_AON_CTRL_PM_STATUS_pm_power_down_cpu_SHIFT 26
-
-/* AON_CTRL :: PM_STATUS :: pm_cpu_reset_b [25:25] */
-#define BCHP_AON_CTRL_PM_STATUS_pm_cpu_reset_b_MASK 0x02000000
-#define BCHP_AON_CTRL_PM_STATUS_pm_cpu_reset_b_SHIFT 25
-
-/* AON_CTRL :: PM_STATUS :: pm_s3_wakeup_reset_ [24:24] */
-#define BCHP_AON_CTRL_PM_STATUS_pm_s3_wakeup_reset__MASK 0x01000000
-#define BCHP_AON_CTRL_PM_STATUS_pm_s3_wakeup_reset__SHIFT 24
-
-/* AON_CTRL :: PM_STATUS :: pm_boundary_scan_request [23:23] */
-#define BCHP_AON_CTRL_PM_STATUS_pm_boundary_scan_request_MASK 0x00800000
-#define BCHP_AON_CTRL_PM_STATUS_pm_boundary_scan_request_SHIFT 23
-
-/* AON_CTRL :: PM_STATUS :: pm_fast_pd_precharge_valid [22:22] */
-#define BCHP_AON_CTRL_PM_STATUS_pm_fast_pd_precharge_valid_MASK 0x00400000
-#define BCHP_AON_CTRL_PM_STATUS_pm_fast_pd_precharge_valid_SHIFT 22
-
-/* AON_CTRL :: PM_STATUS :: pm_led_out [21:21] */
-#define BCHP_AON_CTRL_PM_STATUS_pm_led_out_MASK 0x00200000
-#define BCHP_AON_CTRL_PM_STATUS_pm_led_out_SHIFT 21
-
-/* AON_CTRL :: PM_STATUS :: pm_standby_b [20:20] */
-#define BCHP_AON_CTRL_PM_STATUS_pm_standby_b_MASK 0x00100000
-#define BCHP_AON_CTRL_PM_STATUS_pm_standby_b_SHIFT 20
-
-/* AON_CTRL :: PM_STATUS :: pm_ignore_inputs_ng [19:19] */
-#define BCHP_AON_CTRL_PM_STATUS_pm_ignore_inputs_ng_MASK 0x00080000
-#define BCHP_AON_CTRL_PM_STATUS_pm_ignore_inputs_ng_SHIFT 19
-
-/* AON_CTRL :: PM_STATUS :: pm_ignore_inputs [18:18] */
-#define BCHP_AON_CTRL_PM_STATUS_pm_ignore_inputs_MASK 0x00040000
-#define BCHP_AON_CTRL_PM_STATUS_pm_ignore_inputs_SHIFT 18
-
-/* AON_CTRL :: PM_STATUS :: pm_s2_standby [17:17] */
-#define BCHP_AON_CTRL_PM_STATUS_pm_s2_standby_MASK 0x00020000
-#define BCHP_AON_CTRL_PM_STATUS_pm_s2_standby_SHIFT 17
-
-/* AON_CTRL :: PM_STATUS :: pm_pwrdn_pll_req [16:16] */
-#define BCHP_AON_CTRL_PM_STATUS_pm_pwrdn_pll_req_MASK 0x00010000
-#define BCHP_AON_CTRL_PM_STATUS_pm_pwrdn_pll_req_SHIFT 16
-
-/* AON_CTRL :: PM_STATUS :: pm_dis_xtal_clocks [15:15] */
-#define BCHP_AON_CTRL_PM_STATUS_pm_dis_xtal_clocks_MASK 0x00008000
-#define BCHP_AON_CTRL_PM_STATUS_pm_dis_xtal_clocks_SHIFT 15
-
-/* AON_CTRL :: PM_STATUS :: pm_dis_all_clocks [14:14] */
-#define BCHP_AON_CTRL_PM_STATUS_pm_dis_all_clocks_MASK 0x00004000
-#define BCHP_AON_CTRL_PM_STATUS_pm_dis_all_clocks_SHIFT 14
-
-/* AON_CTRL :: PM_STATUS :: pm_dphy_standby [13:13] */
-#define BCHP_AON_CTRL_PM_STATUS_pm_dphy_standby_MASK 0x00002000
-#define BCHP_AON_CTRL_PM_STATUS_pm_dphy_standby_SHIFT 13
-
-/* AON_CTRL :: PM_STATUS :: pm_dis_cpu_clock [12:12] */
-#define BCHP_AON_CTRL_PM_STATUS_pm_dis_cpu_clock_MASK 0x00001000
-#define BCHP_AON_CTRL_PM_STATUS_pm_dis_cpu_clock_SHIFT 12
-
-/* AON_CTRL :: PM_STATUS :: pm_dis_avd_rptd_clock [11:11] */
-#define BCHP_AON_CTRL_PM_STATUS_pm_dis_avd_rptd_clock_MASK 0x00000800
-#define BCHP_AON_CTRL_PM_STATUS_pm_dis_avd_rptd_clock_SHIFT 11
-
-/* AON_CTRL :: PM_STATUS :: pm_power_ctrl_disable [10:10] */
-#define BCHP_AON_CTRL_PM_STATUS_pm_power_ctrl_disable_MASK 0x00000400
-#define BCHP_AON_CTRL_PM_STATUS_pm_power_ctrl_disable_SHIFT 10
-
-/* AON_CTRL :: PM_STATUS :: pm_pll_lock [09:09] */
-#define BCHP_AON_CTRL_PM_STATUS_pm_pll_lock_MASK 0x00000200
-#define BCHP_AON_CTRL_PM_STATUS_pm_pll_lock_SHIFT 9
-
-/* AON_CTRL :: PM_STATUS :: pm_dram_ready_for_pwrdn [08:08] */
-#define BCHP_AON_CTRL_PM_STATUS_pm_dram_ready_for_pwrdn_MASK 0x00000100
-#define BCHP_AON_CTRL_PM_STATUS_pm_dram_ready_for_pwrdn_SHIFT 8
-
-/* AON_CTRL :: PM_STATUS :: pm_bsp_ready_for_pwrdn [07:07] */
-#define BCHP_AON_CTRL_PM_STATUS_pm_bsp_ready_for_pwrdn_MASK 0x00000080
-#define BCHP_AON_CTRL_PM_STATUS_pm_bsp_ready_for_pwrdn_SHIFT 7
-
-/* AON_CTRL :: PM_STATUS :: pm_cpu_ready_for_pwrdn [06:06] */
-#define BCHP_AON_CTRL_PM_STATUS_pm_cpu_ready_for_pwrdn_MASK 0x00000040
-#define BCHP_AON_CTRL_PM_STATUS_pm_cpu_ready_for_pwrdn_SHIFT 6
-
-/* AON_CTRL :: PM_STATUS :: pm_sec_avd_rptd_clk_disable [05:05] */
-#define BCHP_AON_CTRL_PM_STATUS_pm_sec_avd_rptd_clk_disable_MASK 0x00000020
-#define BCHP_AON_CTRL_PM_STATUS_pm_sec_avd_rptd_clk_disable_SHIFT 5
-
-/* AON_CTRL :: PM_STATUS :: pm_state [04:00] */
-#define BCHP_AON_CTRL_PM_STATUS_pm_state_MASK 0x0000001f
-#define BCHP_AON_CTRL_PM_STATUS_pm_state_SHIFT 0
-#define BCHP_AON_CTRL_PM_STATUS_pm_state_PM_ACTIVE 0
-#define BCHP_AON_CTRL_PM_STATUS_pm_state_PM_PWRDN_RDY 1
-#define BCHP_AON_CTRL_PM_STATUS_pm_state_PM_DISABLE_AVD_RPTD 2
-#define BCHP_AON_CTRL_PM_STATUS_pm_state_PM_DISABLE_CPU 3
-#define BCHP_AON_CTRL_PM_STATUS_pm_state_PM_TRANSITION_TO_STANDBY 4
-#define BCHP_AON_CTRL_PM_STATUS_pm_state_PM_STANDBY 5
-#define BCHP_AON_CTRL_PM_STATUS_pm_state_PM_STANDBY_WITH_PLLS_ON 6
-#define BCHP_AON_CTRL_PM_STATUS_pm_state_PM_HOLD_CPU_POWERED_DOWN 7
-#define BCHP_AON_CTRL_PM_STATUS_pm_state_PM_POWER_UP_CPU 8
-#define BCHP_AON_CTRL_PM_STATUS_pm_state_PM_TRANSITION_TO_ACTIVE 9
-#define BCHP_AON_CTRL_PM_STATUS_pm_state_PM_FAST_PWRDN 10
-#define BCHP_AON_CTRL_PM_STATUS_pm_state_PM_DEEP_STANDBY_ENTRY_S1 11
-#define BCHP_AON_CTRL_PM_STATUS_pm_state_PM_DEEP_STANDBY_COLD_ENTRY_S2 12
-#define BCHP_AON_CTRL_PM_STATUS_pm_state_PM_DEEP_STANDBY_WARM_ENTRY_S2 13
-#define BCHP_AON_CTRL_PM_STATUS_pm_state_PM_DEEP_STANDBY_ENTRY_S3 14
-#define BCHP_AON_CTRL_PM_STATUS_pm_state_PM_DEEP_STANDBY 15
-#define BCHP_AON_CTRL_PM_STATUS_pm_state_PM_DEEP_STANDBY_EXIT_S1 16
-#define BCHP_AON_CTRL_PM_STATUS_pm_state_PM_DEEP_STANDBY_EXIT_S2 17
-
-/***************************************************************************
- *PM_IRQ_INPUT_STATUS - Power Management IRQ input status
- ***************************************************************************/
-/* AON_CTRL :: PM_IRQ_INPUT_STATUS :: pm_irq_input_status [31:00] */
-#define BCHP_AON_CTRL_PM_IRQ_INPUT_STATUS_pm_irq_input_status_MASK 0xffffffff
-#define BCHP_AON_CTRL_PM_IRQ_INPUT_STATUS_pm_irq_input_status_SHIFT 0
-
-/***************************************************************************
- *PM_CPU_WAIT_COUNT - Power Management Wait counter in place of Wait for Host CPU IRQ
- ***************************************************************************/
-/* AON_CTRL :: PM_CPU_WAIT_COUNT :: reserved0 [31:16] */
-#define BCHP_AON_CTRL_PM_CPU_WAIT_COUNT_reserved0_MASK 0xffff0000
-#define BCHP_AON_CTRL_PM_CPU_WAIT_COUNT_reserved0_SHIFT 16
-
-/* AON_CTRL :: PM_CPU_WAIT_COUNT :: counter_start_value [15:00] */
-#define BCHP_AON_CTRL_PM_CPU_WAIT_COUNT_counter_start_value_MASK 0x0000ffff
-#define BCHP_AON_CTRL_PM_CPU_WAIT_COUNT_counter_start_value_SHIFT 0
-#define BCHP_AON_CTRL_PM_CPU_WAIT_COUNT_counter_start_value_DEFAULT 0x00000010
-
-/***************************************************************************
- *PM_CPU_GUARDBAND_TIMER - Power Good Guardband Timer for Host CPU
- ***************************************************************************/
-/* AON_CTRL :: PM_CPU_GUARDBAND_TIMER :: reserved0 [31:10] */
-#define BCHP_AON_CTRL_PM_CPU_GUARDBAND_TIMER_reserved0_MASK 0xfffffc00
-#define BCHP_AON_CTRL_PM_CPU_GUARDBAND_TIMER_reserved0_SHIFT 10
-
-/* AON_CTRL :: PM_CPU_GUARDBAND_TIMER :: counter_start_value [09:00] */
-#define BCHP_AON_CTRL_PM_CPU_GUARDBAND_TIMER_counter_start_value_MASK 0x000003ff
-#define BCHP_AON_CTRL_PM_CPU_GUARDBAND_TIMER_counter_start_value_SHIFT 0
-#define BCHP_AON_CTRL_PM_CPU_GUARDBAND_TIMER_counter_start_value_DEFAULT 0x0000007f
-
-/***************************************************************************
- *PM_S3_STANDBY_TIMER - Deep Standby Assertion Timer
- ***************************************************************************/
-/* AON_CTRL :: PM_S3_STANDBY_TIMER :: reserved0 [31:27] */
-#define BCHP_AON_CTRL_PM_S3_STANDBY_TIMER_reserved0_MASK 0xf8000000
-#define BCHP_AON_CTRL_PM_S3_STANDBY_TIMER_reserved0_SHIFT 27
-
-/* AON_CTRL :: PM_S3_STANDBY_TIMER :: counter_start_value [26:00] */
-#define BCHP_AON_CTRL_PM_S3_STANDBY_TIMER_counter_start_value_MASK 0x07ffffff
-#define BCHP_AON_CTRL_PM_S3_STANDBY_TIMER_counter_start_value_SHIFT 0
-#define BCHP_AON_CTRL_PM_S3_STANDBY_TIMER_counter_start_value_DEFAULT 0x00083d60
-
-/***************************************************************************
- *PM_S3_WAKEUP_TIMER - Deep Standby Wakeup Timer
- ***************************************************************************/
-/* AON_CTRL :: PM_S3_WAKEUP_TIMER :: reserved0 [31:27] */
-#define BCHP_AON_CTRL_PM_S3_WAKEUP_TIMER_reserved0_MASK 0xf8000000
-#define BCHP_AON_CTRL_PM_S3_WAKEUP_TIMER_reserved0_SHIFT 27
-
-/* AON_CTRL :: PM_S3_WAKEUP_TIMER :: counter_start_value [26:00] */
-#define BCHP_AON_CTRL_PM_S3_WAKEUP_TIMER_counter_start_value_MASK 0x07ffffff
-#define BCHP_AON_CTRL_PM_S3_WAKEUP_TIMER_counter_start_value_SHIFT 0
-#define BCHP_AON_CTRL_PM_S3_WAKEUP_TIMER_counter_start_value_DEFAULT 0x00083d60
-
-/***************************************************************************
- *PM_FAST_PWRDN_PRECHARGE - Control register for Power Controller
- ***************************************************************************/
-/* AON_CTRL :: PM_FAST_PWRDN_PRECHARGE :: reserved0 [31:24] */
-#define BCHP_AON_CTRL_PM_FAST_PWRDN_PRECHARGE_reserved0_MASK 0xff000000
-#define BCHP_AON_CTRL_PM_FAST_PWRDN_PRECHARGE_reserved0_SHIFT 24
-
-/* AON_CTRL :: PM_FAST_PWRDN_PRECHARGE :: pm_fast_power_down_precharge [23:00] */
-#define BCHP_AON_CTRL_PM_FAST_PWRDN_PRECHARGE_pm_fast_power_down_precharge_MASK 0x00ffffff
-#define BCHP_AON_CTRL_PM_FAST_PWRDN_PRECHARGE_pm_fast_power_down_precharge_SHIFT 0
-#define BCHP_AON_CTRL_PM_FAST_PWRDN_PRECHARGE_pm_fast_power_down_precharge_DEFAULT 0x00000000
-
-/***************************************************************************
- *PM_LED_CTRL - LED set control register
- ***************************************************************************/
-/* AON_CTRL :: PM_LED_CTRL :: reserved0 [31:03] */
-#define BCHP_AON_CTRL_PM_LED_CTRL_reserved0_MASK 0xfffffff8
-#define BCHP_AON_CTRL_PM_LED_CTRL_reserved0_SHIFT 3
-
-/* AON_CTRL :: PM_LED_CTRL :: led_status [02:02] */
-#define BCHP_AON_CTRL_PM_LED_CTRL_led_status_MASK 0x00000004
-#define BCHP_AON_CTRL_PM_LED_CTRL_led_status_SHIFT 2
-
-/* AON_CTRL :: PM_LED_CTRL :: led_turn_on [01:01] */
-#define BCHP_AON_CTRL_PM_LED_CTRL_led_turn_on_MASK 0x00000002
-#define BCHP_AON_CTRL_PM_LED_CTRL_led_turn_on_SHIFT 1
-
-/* AON_CTRL :: PM_LED_CTRL :: led_turn_off [00:00] */
-#define BCHP_AON_CTRL_PM_LED_CTRL_led_turn_off_MASK 0x00000001
-#define BCHP_AON_CTRL_PM_LED_CTRL_led_turn_off_SHIFT 0
-
-/***************************************************************************
- *PM_LED_AUTO_ON_ENABLES - LED set control register
- ***************************************************************************/
-/* AON_CTRL :: PM_LED_AUTO_ON_ENABLES :: led_status [31:00] */
-#define BCHP_AON_CTRL_PM_LED_AUTO_ON_ENABLES_led_status_MASK 0xffffffff
-#define BCHP_AON_CTRL_PM_LED_AUTO_ON_ENABLES_led_status_SHIFT 0
-#define BCHP_AON_CTRL_PM_LED_AUTO_ON_ENABLES_led_status_DEFAULT 0x00000000
-
-/***************************************************************************
- *HLCD_CTRL - HW LED Clock Driver Control
- ***************************************************************************/
-/* AON_CTRL :: HLCD_CTRL :: reserved0 [31:02] */
-#define BCHP_AON_CTRL_HLCD_CTRL_reserved0_MASK 0xfffffffc
-#define BCHP_AON_CTRL_HLCD_CTRL_reserved0_SHIFT 2
-
-/* AON_CTRL :: HLCD_CTRL :: hlcd_enable_status [01:01] */
-#define BCHP_AON_CTRL_HLCD_CTRL_hlcd_enable_status_MASK 0x00000002
-#define BCHP_AON_CTRL_HLCD_CTRL_hlcd_enable_status_SHIFT 1
-
-/* AON_CTRL :: HLCD_CTRL :: hlcd_enable [00:00] */
-#define BCHP_AON_CTRL_HLCD_CTRL_hlcd_enable_MASK 0x00000001
-#define BCHP_AON_CTRL_HLCD_CTRL_hlcd_enable_SHIFT 0
-#define BCHP_AON_CTRL_HLCD_CTRL_hlcd_enable_DEFAULT 0x00000000
-
-/***************************************************************************
- *SECOND_FRACTION_COUNTER - Second Fraction Counter Initial value
- ***************************************************************************/
-/* AON_CTRL :: SECOND_FRACTION_COUNTER :: reserved0 [31:25] */
-#define BCHP_AON_CTRL_SECOND_FRACTION_COUNTER_reserved0_MASK 0xfe000000
-#define BCHP_AON_CTRL_SECOND_FRACTION_COUNTER_reserved0_SHIFT 25
-
-/* AON_CTRL :: SECOND_FRACTION_COUNTER :: second_fraction_counter_init [24:00] */
-#define BCHP_AON_CTRL_SECOND_FRACTION_COUNTER_second_fraction_counter_init_MASK 0x01ffffff
-#define BCHP_AON_CTRL_SECOND_FRACTION_COUNTER_second_fraction_counter_init_SHIFT 0
-#define BCHP_AON_CTRL_SECOND_FRACTION_COUNTER_second_fraction_counter_init_DEFAULT 0x00000000
-
-/***************************************************************************
- *TIME_COUNTER - Hour/Minute Counter Initial value
- ***************************************************************************/
-/* AON_CTRL :: TIME_COUNTER :: reserved0 [31:20] */
-#define BCHP_AON_CTRL_TIME_COUNTER_reserved0_MASK 0xfff00000
-#define BCHP_AON_CTRL_TIME_COUNTER_reserved0_SHIFT 20
-
-/* AON_CTRL :: TIME_COUNTER :: hour_display_mode [19:19] */
-#define BCHP_AON_CTRL_TIME_COUNTER_hour_display_mode_MASK 0x00080000
-#define BCHP_AON_CTRL_TIME_COUNTER_hour_display_mode_SHIFT 19
-#define BCHP_AON_CTRL_TIME_COUNTER_hour_display_mode_DEFAULT 0x00000000
-
-/* AON_CTRL :: TIME_COUNTER :: mode_12h_24h_init [18:18] */
-#define BCHP_AON_CTRL_TIME_COUNTER_mode_12h_24h_init_MASK 0x00040000
-#define BCHP_AON_CTRL_TIME_COUNTER_mode_12h_24h_init_SHIFT 18
-#define BCHP_AON_CTRL_TIME_COUNTER_mode_12h_24h_init_DEFAULT 0x00000000
-
-/* AON_CTRL :: TIME_COUNTER :: am_pm_counter_init [17:17] */
-#define BCHP_AON_CTRL_TIME_COUNTER_am_pm_counter_init_MASK 0x00020000
-#define BCHP_AON_CTRL_TIME_COUNTER_am_pm_counter_init_SHIFT 17
-#define BCHP_AON_CTRL_TIME_COUNTER_am_pm_counter_init_DEFAULT 0x00000000
-
-/* AON_CTRL :: TIME_COUNTER :: hour_counter_init [16:12] */
-#define BCHP_AON_CTRL_TIME_COUNTER_hour_counter_init_MASK 0x0001f000
-#define BCHP_AON_CTRL_TIME_COUNTER_hour_counter_init_SHIFT 12
-#define BCHP_AON_CTRL_TIME_COUNTER_hour_counter_init_DEFAULT 0x00000000
-
-/* AON_CTRL :: TIME_COUNTER :: minute_counter_init [11:06] */
-#define BCHP_AON_CTRL_TIME_COUNTER_minute_counter_init_MASK 0x00000fc0
-#define BCHP_AON_CTRL_TIME_COUNTER_minute_counter_init_SHIFT 6
-#define BCHP_AON_CTRL_TIME_COUNTER_minute_counter_init_DEFAULT 0x00000000
-
-/* AON_CTRL :: TIME_COUNTER :: second_counter_init [05:00] */
-#define BCHP_AON_CTRL_TIME_COUNTER_second_counter_init_MASK 0x0000003f
-#define BCHP_AON_CTRL_TIME_COUNTER_second_counter_init_SHIFT 0
-#define BCHP_AON_CTRL_TIME_COUNTER_second_counter_init_DEFAULT 0x00000000
-
-/***************************************************************************
- *LED_DIGIT_CODE_0 - Digit Code for digit 0, 1, 2, 3
- ***************************************************************************/
-/* AON_CTRL :: LED_DIGIT_CODE_0 :: digit_code_3 [31:24] */
-#define BCHP_AON_CTRL_LED_DIGIT_CODE_0_digit_code_3_MASK 0xff000000
-#define BCHP_AON_CTRL_LED_DIGIT_CODE_0_digit_code_3_SHIFT 24
-#define BCHP_AON_CTRL_LED_DIGIT_CODE_0_digit_code_3_DEFAULT 0x00000000
-
-/* AON_CTRL :: LED_DIGIT_CODE_0 :: digit_code_2 [23:16] */
-#define BCHP_AON_CTRL_LED_DIGIT_CODE_0_digit_code_2_MASK 0x00ff0000
-#define BCHP_AON_CTRL_LED_DIGIT_CODE_0_digit_code_2_SHIFT 16
-#define BCHP_AON_CTRL_LED_DIGIT_CODE_0_digit_code_2_DEFAULT 0x00000000
-
-/* AON_CTRL :: LED_DIGIT_CODE_0 :: digit_code_1 [15:08] */
-#define BCHP_AON_CTRL_LED_DIGIT_CODE_0_digit_code_1_MASK 0x0000ff00
-#define BCHP_AON_CTRL_LED_DIGIT_CODE_0_digit_code_1_SHIFT 8
-#define BCHP_AON_CTRL_LED_DIGIT_CODE_0_digit_code_1_DEFAULT 0x00000000
-
-/* AON_CTRL :: LED_DIGIT_CODE_0 :: digit_code_0 [07:00] */
-#define BCHP_AON_CTRL_LED_DIGIT_CODE_0_digit_code_0_MASK 0x000000ff
-#define BCHP_AON_CTRL_LED_DIGIT_CODE_0_digit_code_0_SHIFT 0
-#define BCHP_AON_CTRL_LED_DIGIT_CODE_0_digit_code_0_DEFAULT 0x00000000
-
-/***************************************************************************
- *LED_DIGIT_CODE_1 - Digit Code for digit 4, 5, 6, 7
- ***************************************************************************/
-/* AON_CTRL :: LED_DIGIT_CODE_1 :: digit_code_7 [31:24] */
-#define BCHP_AON_CTRL_LED_DIGIT_CODE_1_digit_code_7_MASK 0xff000000
-#define BCHP_AON_CTRL_LED_DIGIT_CODE_1_digit_code_7_SHIFT 24
-#define BCHP_AON_CTRL_LED_DIGIT_CODE_1_digit_code_7_DEFAULT 0x00000000
-
-/* AON_CTRL :: LED_DIGIT_CODE_1 :: digit_code_6 [23:16] */
-#define BCHP_AON_CTRL_LED_DIGIT_CODE_1_digit_code_6_MASK 0x00ff0000
-#define BCHP_AON_CTRL_LED_DIGIT_CODE_1_digit_code_6_SHIFT 16
-#define BCHP_AON_CTRL_LED_DIGIT_CODE_1_digit_code_6_DEFAULT 0x00000000
-
-/* AON_CTRL :: LED_DIGIT_CODE_1 :: digit_code_5 [15:08] */
-#define BCHP_AON_CTRL_LED_DIGIT_CODE_1_digit_code_5_MASK 0x0000ff00
-#define BCHP_AON_CTRL_LED_DIGIT_CODE_1_digit_code_5_SHIFT 8
-#define BCHP_AON_CTRL_LED_DIGIT_CODE_1_digit_code_5_DEFAULT 0x00000000
-
-/* AON_CTRL :: LED_DIGIT_CODE_1 :: digit_code_4 [07:00] */
-#define BCHP_AON_CTRL_LED_DIGIT_CODE_1_digit_code_4_MASK 0x000000ff
-#define BCHP_AON_CTRL_LED_DIGIT_CODE_1_digit_code_4_SHIFT 0
-#define BCHP_AON_CTRL_LED_DIGIT_CODE_1_digit_code_4_DEFAULT 0x00000000
-
-/***************************************************************************
- *LED_DIGIT_CODE_2 - Digit Code for digit 8, 9
- ***************************************************************************/
-/* AON_CTRL :: LED_DIGIT_CODE_2 :: reserved0 [31:16] */
-#define BCHP_AON_CTRL_LED_DIGIT_CODE_2_reserved0_MASK 0xffff0000
-#define BCHP_AON_CTRL_LED_DIGIT_CODE_2_reserved0_SHIFT 16
-
-/* AON_CTRL :: LED_DIGIT_CODE_2 :: digit_code_9 [15:08] */
-#define BCHP_AON_CTRL_LED_DIGIT_CODE_2_digit_code_9_MASK 0x0000ff00
-#define BCHP_AON_CTRL_LED_DIGIT_CODE_2_digit_code_9_SHIFT 8
-#define BCHP_AON_CTRL_LED_DIGIT_CODE_2_digit_code_9_DEFAULT 0x00000000
-
-/* AON_CTRL :: LED_DIGIT_CODE_2 :: digit_code_8 [07:00] */
-#define BCHP_AON_CTRL_LED_DIGIT_CODE_2_digit_code_8_MASK 0x000000ff
-#define BCHP_AON_CTRL_LED_DIGIT_CODE_2_digit_code_8_SHIFT 0
-#define BCHP_AON_CTRL_LED_DIGIT_CODE_2_digit_code_8_DEFAULT 0x00000000
-
-/***************************************************************************
- *LED_DIGIT_ADDR_OFFSET - Hour MSD/LSD and minute MSD/LSD address offset
- ***************************************************************************/
-/* AON_CTRL :: LED_DIGIT_ADDR_OFFSET :: hour_msd_addr_offset [31:24] */
-#define BCHP_AON_CTRL_LED_DIGIT_ADDR_OFFSET_hour_msd_addr_offset_MASK 0xff000000
-#define BCHP_AON_CTRL_LED_DIGIT_ADDR_OFFSET_hour_msd_addr_offset_SHIFT 24
-#define BCHP_AON_CTRL_LED_DIGIT_ADDR_OFFSET_hour_msd_addr_offset_DEFAULT 0x00000020
-
-/* AON_CTRL :: LED_DIGIT_ADDR_OFFSET :: hour_lsd_addr_offset [23:16] */
-#define BCHP_AON_CTRL_LED_DIGIT_ADDR_OFFSET_hour_lsd_addr_offset_MASK 0x00ff0000
-#define BCHP_AON_CTRL_LED_DIGIT_ADDR_OFFSET_hour_lsd_addr_offset_SHIFT 16
-#define BCHP_AON_CTRL_LED_DIGIT_ADDR_OFFSET_hour_lsd_addr_offset_DEFAULT 0x00000024
-
-/* AON_CTRL :: LED_DIGIT_ADDR_OFFSET :: minute_msd_addr_offset [15:08] */
-#define BCHP_AON_CTRL_LED_DIGIT_ADDR_OFFSET_minute_msd_addr_offset_MASK 0x0000ff00
-#define BCHP_AON_CTRL_LED_DIGIT_ADDR_OFFSET_minute_msd_addr_offset_SHIFT 8
-#define BCHP_AON_CTRL_LED_DIGIT_ADDR_OFFSET_minute_msd_addr_offset_DEFAULT 0x00000018
-
-/* AON_CTRL :: LED_DIGIT_ADDR_OFFSET :: minute_lsd_addr_offset [07:00] */
-#define BCHP_AON_CTRL_LED_DIGIT_ADDR_OFFSET_minute_lsd_addr_offset_MASK 0x000000ff
-#define BCHP_AON_CTRL_LED_DIGIT_ADDR_OFFSET_minute_lsd_addr_offset_SHIFT 0
-#define BCHP_AON_CTRL_LED_DIGIT_ADDR_OFFSET_minute_lsd_addr_offset_DEFAULT 0x0000001c
-
-/***************************************************************************
- *LED_STATUS_CTRL - LED status control
- ***************************************************************************/
-/* AON_CTRL :: LED_STATUS_CTRL :: reserved0 [31:28] */
-#define BCHP_AON_CTRL_LED_STATUS_CTRL_reserved0_MASK 0xf0000000
-#define BCHP_AON_CTRL_LED_STATUS_CTRL_reserved0_SHIFT 28
-
-/* AON_CTRL :: LED_STATUS_CTRL :: hlcd_state [27:25] */
-#define BCHP_AON_CTRL_LED_STATUS_CTRL_hlcd_state_MASK 0x0e000000
-#define BCHP_AON_CTRL_LED_STATUS_CTRL_hlcd_state_SHIFT 25
-#define BCHP_AON_CTRL_LED_STATUS_CTRL_hlcd_state_HLCD_IDLE 0
-#define BCHP_AON_CTRL_LED_STATUS_CTRL_hlcd_state_HLCD_COUNT 1
-#define BCHP_AON_CTRL_LED_STATUS_CTRL_hlcd_state_HLCD_PROGRAM_MINUTE_LSD 2
-#define BCHP_AON_CTRL_LED_STATUS_CTRL_hlcd_state_HLCD_PROGRAM_MINUTE_MSD 3
-#define BCHP_AON_CTRL_LED_STATUS_CTRL_hlcd_state_HLCD_PROGRAM_HOUR_LSD 4
-#define BCHP_AON_CTRL_LED_STATUS_CTRL_hlcd_state_HLCD_PROGRAM_HOUR_MSD 5
-#define BCHP_AON_CTRL_LED_STATUS_CTRL_hlcd_state_HLCD_PROGRAM_STATUS 6
-
-/* AON_CTRL :: LED_STATUS_CTRL :: status_update_enable [24:24] */
-#define BCHP_AON_CTRL_LED_STATUS_CTRL_status_update_enable_MASK 0x01000000
-#define BCHP_AON_CTRL_LED_STATUS_CTRL_status_update_enable_SHIFT 24
-#define BCHP_AON_CTRL_LED_STATUS_CTRL_status_update_enable_DEFAULT 0x00000000
-
-/* AON_CTRL :: LED_STATUS_CTRL :: status_mask [23:12] */
-#define BCHP_AON_CTRL_LED_STATUS_CTRL_status_mask_MASK 0x00fff000
-#define BCHP_AON_CTRL_LED_STATUS_CTRL_status_mask_SHIFT 12
-#define BCHP_AON_CTRL_LED_STATUS_CTRL_status_mask_DEFAULT 0x00000000
-
-/* AON_CTRL :: LED_STATUS_CTRL :: status_bit_offset [11:08] */
-#define BCHP_AON_CTRL_LED_STATUS_CTRL_status_bit_offset_MASK 0x00000f00
-#define BCHP_AON_CTRL_LED_STATUS_CTRL_status_bit_offset_SHIFT 8
-#define BCHP_AON_CTRL_LED_STATUS_CTRL_status_bit_offset_DEFAULT 0x00000000
-
-/* AON_CTRL :: LED_STATUS_CTRL :: status_addr_offset [07:00] */
-#define BCHP_AON_CTRL_LED_STATUS_CTRL_status_addr_offset_MASK 0x000000ff
-#define BCHP_AON_CTRL_LED_STATUS_CTRL_status_addr_offset_SHIFT 0
-#define BCHP_AON_CTRL_LED_STATUS_CTRL_status_addr_offset_DEFAULT 0x00000000
-
-/***************************************************************************
- *GENERAL_CTRL_0 - General control register 0
- ***************************************************************************/
-/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_31 [31:31] */
-#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_31_MASK 0x80000000
-#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_31_SHIFT 31
-#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_31_DEFAULT 0x00000001
-
-/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_30 [30:30] */
-#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_30_MASK 0x40000000
-#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_30_SHIFT 30
-#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_30_DEFAULT 0x00000001
-
-/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_29 [29:29] */
-#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_29_MASK 0x20000000
-#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_29_SHIFT 29
-#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_29_DEFAULT 0x00000001
-
-/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_28 [28:28] */
-#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_28_MASK 0x10000000
-#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_28_SHIFT 28
-#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_28_DEFAULT 0x00000001
-
-/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_27 [27:27] */
-#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_27_MASK 0x08000000
-#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_27_SHIFT 27
-#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_27_DEFAULT 0x00000001
-
-/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_26 [26:26] */
-#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_26_MASK 0x04000000
-#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_26_SHIFT 26
-#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_26_DEFAULT 0x00000001
-
-/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_25 [25:25] */
-#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_25_MASK 0x02000000
-#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_25_SHIFT 25
-#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_25_DEFAULT 0x00000001
-
-/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_24 [24:24] */
-#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_24_MASK 0x01000000
-#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_24_SHIFT 24
-#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_24_DEFAULT 0x00000001
-
-/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_23 [23:23] */
-#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_23_MASK 0x00800000
-#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_23_SHIFT 23
-#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_23_DEFAULT 0x00000001
-
-/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_22 [22:22] */
-#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_22_MASK 0x00400000
-#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_22_SHIFT 22
-#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_22_DEFAULT 0x00000001
-
-/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_21 [21:21] */
-#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_21_MASK 0x00200000
-#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_21_SHIFT 21
-#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_21_DEFAULT 0x00000001
-
-/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_20 [20:20] */
-#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_20_MASK 0x00100000
-#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_20_SHIFT 20
-#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_20_DEFAULT 0x00000001
-
-/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_19 [19:19] */
-#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_19_MASK 0x00080000
-#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_19_SHIFT 19
-#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_19_DEFAULT 0x00000001
-
-/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_18 [18:18] */
-#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_18_MASK 0x00040000
-#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_18_SHIFT 18
-#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_18_DEFAULT 0x00000001
-
-/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_17 [17:17] */
-#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_17_MASK 0x00020000
-#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_17_SHIFT 17
-#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_17_DEFAULT 0x00000001
-
-/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_16 [16:16] */
-#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_16_MASK 0x00010000
-#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_16_SHIFT 16
-#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_16_DEFAULT 0x00000001
-
-/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_15 [15:15] */
-#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_15_MASK 0x00008000
-#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_15_SHIFT 15
-#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_15_DEFAULT 0x00000000
-
-/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_14 [14:14] */
-#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_14_MASK 0x00004000
-#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_14_SHIFT 14
-#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_14_DEFAULT 0x00000000
-
-/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_13 [13:13] */
-#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_13_MASK 0x00002000
-#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_13_SHIFT 13
-#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_13_DEFAULT 0x00000000
-
-/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_12 [12:12] */
-#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_12_MASK 0x00001000
-#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_12_SHIFT 12
-#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_12_DEFAULT 0x00000000
-
-/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_11 [11:11] */
-#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_11_MASK 0x00000800
-#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_11_SHIFT 11
-#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_11_DEFAULT 0x00000000
-
-/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_10 [10:10] */
-#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_10_MASK 0x00000400
-#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_10_SHIFT 10
-#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_10_DEFAULT 0x00000000
-
-/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_9 [09:09] */
-#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_9_MASK 0x00000200
-#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_9_SHIFT 9
-#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_9_DEFAULT 0x00000000
-
-/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_8 [08:08] */
-#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_8_MASK 0x00000100
-#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_8_SHIFT 8
-#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_8_DEFAULT 0x00000000
-
-/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_7 [07:07] */
-#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_7_MASK 0x00000080
-#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_7_SHIFT 7
-#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_7_DEFAULT 0x00000000
-
-/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_6 [06:06] */
-#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_6_MASK 0x00000040
-#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_6_SHIFT 6
-#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_6_DEFAULT 0x00000000
-
-/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_5 [05:05] */
-#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_5_MASK 0x00000020
-#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_5_SHIFT 5
-#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_5_DEFAULT 0x00000000
-
-/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_4 [04:04] */
-#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_4_MASK 0x00000010
-#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_4_SHIFT 4
-#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_4_DEFAULT 0x00000000
-
-/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_3 [03:03] */
-#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_3_MASK 0x00000008
-#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_3_SHIFT 3
-#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_3_DEFAULT 0x00000000
-
-/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_2 [02:02] */
-#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_2_MASK 0x00000004
-#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_2_SHIFT 2
-#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_2_DEFAULT 0x00000000
-
-/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_1 [01:01] */
-#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_1_MASK 0x00000002
-#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_1_SHIFT 1
-#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_1_DEFAULT 0x00000000
-
-/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_0 [00:00] */
-#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_0_MASK 0x00000001
-#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_0_SHIFT 0
-#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_0_DEFAULT 0x00000000
-
-/***************************************************************************
- *GENERAL_STATUS_0 - General status register 0
- ***************************************************************************/
-/* AON_CTRL :: GENERAL_STATUS_0 :: reserved0 [31:08] */
-#define BCHP_AON_CTRL_GENERAL_STATUS_0_reserved0_MASK 0xffffff00
-#define BCHP_AON_CTRL_GENERAL_STATUS_0_reserved0_SHIFT 8
-
-/* AON_CTRL :: GENERAL_STATUS_0 :: general_status0_7 [07:07] */
-#define BCHP_AON_CTRL_GENERAL_STATUS_0_general_status0_7_MASK 0x00000080
-#define BCHP_AON_CTRL_GENERAL_STATUS_0_general_status0_7_SHIFT 7
-
-/* AON_CTRL :: GENERAL_STATUS_0 :: general_status0_6 [06:06] */
-#define BCHP_AON_CTRL_GENERAL_STATUS_0_general_status0_6_MASK 0x00000040
-#define BCHP_AON_CTRL_GENERAL_STATUS_0_general_status0_6_SHIFT 6
-
-/* AON_CTRL :: GENERAL_STATUS_0 :: general_status0_5 [05:05] */
-#define BCHP_AON_CTRL_GENERAL_STATUS_0_general_status0_5_MASK 0x00000020
-#define BCHP_AON_CTRL_GENERAL_STATUS_0_general_status0_5_SHIFT 5
-
-/* AON_CTRL :: GENERAL_STATUS_0 :: general_status0_4 [04:04] */
-#define BCHP_AON_CTRL_GENERAL_STATUS_0_general_status0_4_MASK 0x00000010
-#define BCHP_AON_CTRL_GENERAL_STATUS_0_general_status0_4_SHIFT 4
-
-/* AON_CTRL :: GENERAL_STATUS_0 :: general_status0_3 [03:03] */
-#define BCHP_AON_CTRL_GENERAL_STATUS_0_general_status0_3_MASK 0x00000008
-#define BCHP_AON_CTRL_GENERAL_STATUS_0_general_status0_3_SHIFT 3
-
-/* AON_CTRL :: GENERAL_STATUS_0 :: general_status0_2 [02:02] */
-#define BCHP_AON_CTRL_GENERAL_STATUS_0_general_status0_2_MASK 0x00000004
-#define BCHP_AON_CTRL_GENERAL_STATUS_0_general_status0_2_SHIFT 2
-
-/* AON_CTRL :: GENERAL_STATUS_0 :: general_status0_1 [01:01] */
-#define BCHP_AON_CTRL_GENERAL_STATUS_0_general_status0_1_MASK 0x00000002
-#define BCHP_AON_CTRL_GENERAL_STATUS_0_general_status0_1_SHIFT 1
-
-/* AON_CTRL :: GENERAL_STATUS_0 :: ejtag_ce_wakeup_event [00:00] */
-#define BCHP_AON_CTRL_GENERAL_STATUS_0_ejtag_ce_wakeup_event_MASK 0x00000001
-#define BCHP_AON_CTRL_GENERAL_STATUS_0_ejtag_ce_wakeup_event_SHIFT 0
-
-/***************************************************************************
- *GENERAL_CTRL_NO_SCAN_0 - General control register without scan 0
- ***************************************************************************/
-/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_31 [31:31] */
-#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_31_MASK 0x80000000
-#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_31_SHIFT 31
-#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_31_DEFAULT 0x00000001
-
-/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_30 [30:30] */
-#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_30_MASK 0x40000000
-#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_30_SHIFT 30
-#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_30_DEFAULT 0x00000001
-
-/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_29 [29:29] */
-#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_29_MASK 0x20000000
-#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_29_SHIFT 29
-#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_29_DEFAULT 0x00000001
-
-/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_28 [28:28] */
-#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_28_MASK 0x10000000
-#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_28_SHIFT 28
-#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_28_DEFAULT 0x00000001
-
-/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_27 [27:27] */
-#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_27_MASK 0x08000000
-#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_27_SHIFT 27
-#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_27_DEFAULT 0x00000001
-
-/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_26 [26:26] */
-#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_26_MASK 0x04000000
-#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_26_SHIFT 26
-#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_26_DEFAULT 0x00000001
-
-/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_25 [25:25] */
-#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_25_MASK 0x02000000
-#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_25_SHIFT 25
-#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_25_DEFAULT 0x00000001
-
-/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_24 [24:24] */
-#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_24_MASK 0x01000000
-#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_24_SHIFT 24
-#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_24_DEFAULT 0x00000001
-
-/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_23 [23:23] */
-#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_23_MASK 0x00800000
-#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_23_SHIFT 23
-#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_23_DEFAULT 0x00000001
-
-/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_22 [22:22] */
-#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_22_MASK 0x00400000
-#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_22_SHIFT 22
-#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_22_DEFAULT 0x00000001
-
-/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_21 [21:21] */
-#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_21_MASK 0x00200000
-#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_21_SHIFT 21
-#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_21_DEFAULT 0x00000001
-
-/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_20 [20:20] */
-#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_20_MASK 0x00100000
-#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_20_SHIFT 20
-#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_20_DEFAULT 0x00000001
-
-/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_19 [19:19] */
-#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_19_MASK 0x00080000
-#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_19_SHIFT 19
-#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_19_DEFAULT 0x00000001
-
-/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_18 [18:18] */
-#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_18_MASK 0x00040000
-#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_18_SHIFT 18
-#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_18_DEFAULT 0x00000001
-
-/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_17 [17:17] */
-#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_17_MASK 0x00020000
-#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_17_SHIFT 17
-#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_17_DEFAULT 0x00000001
-
-/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_16 [16:16] */
-#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_16_MASK 0x00010000
-#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_16_SHIFT 16
-#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_16_DEFAULT 0x00000001
-
-/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_15 [15:15] */
-#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_15_MASK 0x00008000
-#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_15_SHIFT 15
-#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_15_DEFAULT 0x00000000
-
-/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_14 [14:14] */
-#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_14_MASK 0x00004000
-#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_14_SHIFT 14
-#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_14_DEFAULT 0x00000000
-
-/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_13 [13:13] */
-#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_13_MASK 0x00002000
-#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_13_SHIFT 13
-#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_13_DEFAULT 0x00000000
-
-/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_12 [12:12] */
-#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_12_MASK 0x00001000
-#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_12_SHIFT 12
-#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_12_DEFAULT 0x00000000
-
-/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_11 [11:11] */
-#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_11_MASK 0x00000800
-#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_11_SHIFT 11
-#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_11_DEFAULT 0x00000000
-
-/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_10 [10:10] */
-#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_10_MASK 0x00000400
-#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_10_SHIFT 10
-#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_10_DEFAULT 0x00000000
-
-/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_9 [09:09] */
-#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_9_MASK 0x00000200
-#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_9_SHIFT 9
-#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_9_DEFAULT 0x00000000
-
-/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_8 [08:08] */
-#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_8_MASK 0x00000100
-#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_8_SHIFT 8
-#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_8_DEFAULT 0x00000000
-
-/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_7 [07:07] */
-#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_7_MASK 0x00000080
-#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_7_SHIFT 7
-#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_7_DEFAULT 0x00000000
-
-/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_6 [06:06] */
-#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_6_MASK 0x00000040
-#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_6_SHIFT 6
-#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_6_DEFAULT 0x00000000
-
-/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_5 [05:05] */
-#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_5_MASK 0x00000020
-#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_5_SHIFT 5
-#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_5_DEFAULT 0x00000000
-
-/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_4 [04:04] */
-#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_4_MASK 0x00000010
-#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_4_SHIFT 4
-#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_4_DEFAULT 0x00000000
-
-/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_3 [03:03] */
-#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_3_MASK 0x00000008
-#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_3_SHIFT 3
-#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_3_DEFAULT 0x00000000
-
-/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_2 [02:02] */
-#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_2_MASK 0x00000004
-#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_2_SHIFT 2
-#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_2_DEFAULT 0x00000000
-
-/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_1 [01:01] */
-#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_1_MASK 0x00000002
-#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_1_SHIFT 1
-#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_1_DEFAULT 0x00000000
-
-/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_0 [00:00] */
-#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_0_MASK 0x00000001
-#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_0_SHIFT 0
-#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_0_DEFAULT 0x00000000
-
-/***************************************************************************
- *SPARE_CTRL_0 - Spare control bits reserved for future use
- ***************************************************************************/
-/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_31 [31:31] */
-#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_31_MASK 0x80000000
-#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_31_SHIFT 31
-#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_31_DEFAULT 0x00000001
-
-/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_30 [30:30] */
-#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_30_MASK 0x40000000
-#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_30_SHIFT 30
-#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_30_DEFAULT 0x00000001
-
-/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_29 [29:29] */
-#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_29_MASK 0x20000000
-#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_29_SHIFT 29
-#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_29_DEFAULT 0x00000001
-
-/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_28 [28:28] */
-#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_28_MASK 0x10000000
-#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_28_SHIFT 28
-#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_28_DEFAULT 0x00000001
-
-/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_27 [27:27] */
-#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_27_MASK 0x08000000
-#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_27_SHIFT 27
-#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_27_DEFAULT 0x00000001
-
-/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_26 [26:26] */
-#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_26_MASK 0x04000000
-#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_26_SHIFT 26
-#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_26_DEFAULT 0x00000001
-
-/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_25 [25:25] */
-#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_25_MASK 0x02000000
-#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_25_SHIFT 25
-#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_25_DEFAULT 0x00000001
-
-/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_24 [24:24] */
-#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_24_MASK 0x01000000
-#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_24_SHIFT 24
-#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_24_DEFAULT 0x00000001
-
-/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_23 [23:23] */
-#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_23_MASK 0x00800000
-#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_23_SHIFT 23
-#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_23_DEFAULT 0x00000000
-
-/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_22 [22:22] */
-#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_22_MASK 0x00400000
-#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_22_SHIFT 22
-#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_22_DEFAULT 0x00000000
-
-/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_21 [21:21] */
-#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_21_MASK 0x00200000
-#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_21_SHIFT 21
-#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_21_DEFAULT 0x00000000
-
-/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_20 [20:20] */
-#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_20_MASK 0x00100000
-#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_20_SHIFT 20
-#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_20_DEFAULT 0x00000000
-
-/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_19 [19:19] */
-#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_19_MASK 0x00080000
-#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_19_SHIFT 19
-#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_19_DEFAULT 0x00000000
-
-/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_18 [18:18] */
-#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_18_MASK 0x00040000
-#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_18_SHIFT 18
-#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_18_DEFAULT 0x00000000
-
-/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_17 [17:17] */
-#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_17_MASK 0x00020000
-#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_17_SHIFT 17
-#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_17_DEFAULT 0x00000000
-
-/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_16 [16:16] */
-#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_16_MASK 0x00010000
-#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_16_SHIFT 16
-#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_16_DEFAULT 0x00000000
-
-/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_15 [15:15] */
-#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_15_MASK 0x00008000
-#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_15_SHIFT 15
-#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_15_DEFAULT 0x00000000
-
-/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_14 [14:14] */
-#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_14_MASK 0x00004000
-#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_14_SHIFT 14
-#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_14_DEFAULT 0x00000000
-
-/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_13 [13:13] */
-#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_13_MASK 0x00002000
-#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_13_SHIFT 13
-#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_13_DEFAULT 0x00000000
-
-/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_12 [12:12] */
-#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_12_MASK 0x00001000
-#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_12_SHIFT 12
-#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_12_DEFAULT 0x00000000
-
-/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_11 [11:11] */
-#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_11_MASK 0x00000800
-#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_11_SHIFT 11
-#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_11_DEFAULT 0x00000000
-
-/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_10 [10:10] */
-#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_10_MASK 0x00000400
-#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_10_SHIFT 10
-#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_10_DEFAULT 0x00000000
-
-/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_09 [09:09] */
-#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_09_MASK 0x00000200
-#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_09_SHIFT 9
-#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_09_DEFAULT 0x00000000
-
-/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_08 [08:08] */
-#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_08_MASK 0x00000100
-#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_08_SHIFT 8
-#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_08_DEFAULT 0x00000000
-
-/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_07 [07:07] */
-#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_07_MASK 0x00000080
-#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_07_SHIFT 7
-#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_07_DEFAULT 0x00000000
-
-/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_06 [06:06] */
-#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_06_MASK 0x00000040
-#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_06_SHIFT 6
-#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_06_DEFAULT 0x00000000
-
-/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_05 [05:05] */
-#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_05_MASK 0x00000020
-#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_05_SHIFT 5
-#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_05_DEFAULT 0x00000000
-
-/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_04 [04:04] */
-#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_04_MASK 0x00000010
-#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_04_SHIFT 4
-#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_04_DEFAULT 0x00000000
-
-/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_03 [03:03] */
-#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_03_MASK 0x00000008
-#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_03_SHIFT 3
-#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_03_DEFAULT 0x00000000
-
-/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_02 [02:02] */
-#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_02_MASK 0x00000004
-#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_02_SHIFT 2
-#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_02_DEFAULT 0x00000000
-
-/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_01 [01:01] */
-#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_01_MASK 0x00000002
-#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_01_SHIFT 1
-#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_01_DEFAULT 0x00000000
-
-/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_00 [00:00] */
-#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_00_MASK 0x00000001
-#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_00_SHIFT 0
-#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_00_DEFAULT 0x00000000
-
-/***************************************************************************
- *SPARE_CTRL_1 - Spare control bits reserved for future use
- ***************************************************************************/
-/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_31 [31:31] */
-#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_31_MASK 0x80000000
-#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_31_SHIFT 31
-#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_31_DEFAULT 0x00000001
-
-/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_30 [30:30] */
-#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_30_MASK 0x40000000
-#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_30_SHIFT 30
-#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_30_DEFAULT 0x00000001
-
-/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_29 [29:29] */
-#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_29_MASK 0x20000000
-#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_29_SHIFT 29
-#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_29_DEFAULT 0x00000001
-
-/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_28 [28:28] */
-#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_28_MASK 0x10000000
-#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_28_SHIFT 28
-#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_28_DEFAULT 0x00000001
-
-/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_27 [27:27] */
-#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_27_MASK 0x08000000
-#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_27_SHIFT 27
-#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_27_DEFAULT 0x00000001
-
-/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_26 [26:26] */
-#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_26_MASK 0x04000000
-#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_26_SHIFT 26
-#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_26_DEFAULT 0x00000001
-
-/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_25 [25:25] */
-#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_25_MASK 0x02000000
-#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_25_SHIFT 25
-#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_25_DEFAULT 0x00000001
-
-/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_24 [24:24] */
-#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_24_MASK 0x01000000
-#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_24_SHIFT 24
-#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_24_DEFAULT 0x00000001
-
-/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_23 [23:23] */
-#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_23_MASK 0x00800000
-#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_23_SHIFT 23
-#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_23_DEFAULT 0x00000000
-
-/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_22 [22:22] */
-#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_22_MASK 0x00400000
-#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_22_SHIFT 22
-#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_22_DEFAULT 0x00000000
-
-/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_21 [21:21] */
-#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_21_MASK 0x00200000
-#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_21_SHIFT 21
-#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_21_DEFAULT 0x00000000
-
-/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_20 [20:20] */
-#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_20_MASK 0x00100000
-#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_20_SHIFT 20
-#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_20_DEFAULT 0x00000000
-
-/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_19 [19:19] */
-#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_19_MASK 0x00080000
-#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_19_SHIFT 19
-#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_19_DEFAULT 0x00000000
-
-/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_18 [18:18] */
-#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_18_MASK 0x00040000
-#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_18_SHIFT 18
-#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_18_DEFAULT 0x00000000
-
-/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_17 [17:17] */
-#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_17_MASK 0x00020000
-#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_17_SHIFT 17
-#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_17_DEFAULT 0x00000000
-
-/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_16 [16:16] */
-#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_16_MASK 0x00010000
-#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_16_SHIFT 16
-#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_16_DEFAULT 0x00000000
-
-/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_15 [15:15] */
-#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_15_MASK 0x00008000
-#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_15_SHIFT 15
-#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_15_DEFAULT 0x00000000
-
-/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_14 [14:14] */
-#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_14_MASK 0x00004000
-#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_14_SHIFT 14
-#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_14_DEFAULT 0x00000000
-
-/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_13 [13:13] */
-#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_13_MASK 0x00002000
-#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_13_SHIFT 13
-#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_13_DEFAULT 0x00000000
-
-/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_12 [12:12] */
-#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_12_MASK 0x00001000
-#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_12_SHIFT 12
-#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_12_DEFAULT 0x00000000
-
-/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_11 [11:11] */
-#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_11_MASK 0x00000800
-#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_11_SHIFT 11
-#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_11_DEFAULT 0x00000000
-
-/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_10 [10:10] */
-#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_10_MASK 0x00000400
-#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_10_SHIFT 10
-#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_10_DEFAULT 0x00000000
-
-/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_09 [09:09] */
-#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_09_MASK 0x00000200
-#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_09_SHIFT 9
-#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_09_DEFAULT 0x00000000
-
-/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_08 [08:08] */
-#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_08_MASK 0x00000100
-#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_08_SHIFT 8
-#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_08_DEFAULT 0x00000000
-
-/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_07 [07:07] */
-#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_07_MASK 0x00000080
-#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_07_SHIFT 7
-#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_07_DEFAULT 0x00000000
-
-/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_06 [06:06] */
-#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_06_MASK 0x00000040
-#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_06_SHIFT 6
-#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_06_DEFAULT 0x00000000
-
-/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_05 [05:05] */
-#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_05_MASK 0x00000020
-#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_05_SHIFT 5
-#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_05_DEFAULT 0x00000000
-
-/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_04 [04:04] */
-#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_04_MASK 0x00000010
-#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_04_SHIFT 4
-#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_04_DEFAULT 0x00000000
-
-/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_03 [03:03] */
-#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_03_MASK 0x00000008
-#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_03_SHIFT 3
-#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_03_DEFAULT 0x00000000
-
-/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_02 [02:02] */
-#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_02_MASK 0x00000004
-#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_02_SHIFT 2
-#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_02_DEFAULT 0x00000000
-
-/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_01 [01:01] */
-#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_01_MASK 0x00000002
-#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_01_SHIFT 1
-#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_01_DEFAULT 0x00000000
-
-/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_00 [00:00] */
-#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_00_MASK 0x00000001
-#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_00_SHIFT 0
-#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_00_DEFAULT 0x00000000
-
-/***************************************************************************
- *UNCLEARED_SCRATCH - Scratch register
- ***************************************************************************/
-/* AON_CTRL :: UNCLEARED_SCRATCH :: uncleared_scratch [31:00] */
-#define BCHP_AON_CTRL_UNCLEARED_SCRATCH_uncleared_scratch_MASK 0xffffffff
-#define BCHP_AON_CTRL_UNCLEARED_SCRATCH_uncleared_scratch_SHIFT 0
-#define BCHP_AON_CTRL_UNCLEARED_SCRATCH_uncleared_scratch_DEFAULT 0x00000000
-
-/***************************************************************************
- *RESET_HISTORY - Reset History Register For AON
- ***************************************************************************/
-/* AON_CTRL :: RESET_HISTORY :: reserved0 [31:21] */
-#define BCHP_AON_CTRL_RESET_HISTORY_reserved0_MASK 0xffe00000
-#define BCHP_AON_CTRL_RESET_HISTORY_reserved0_SHIFT 21
-
-/* AON_CTRL :: RESET_HISTORY :: aux_chip_level_reset_1 [20:20] */
-#define BCHP_AON_CTRL_RESET_HISTORY_aux_chip_level_reset_1_MASK 0x00100000
-#define BCHP_AON_CTRL_RESET_HISTORY_aux_chip_level_reset_1_SHIFT 20
-#define BCHP_AON_CTRL_RESET_HISTORY_aux_chip_level_reset_1_DEFAULT 0x00000000
-
-/* AON_CTRL :: RESET_HISTORY :: aux_chip_level_reset_0 [19:19] */
-#define BCHP_AON_CTRL_RESET_HISTORY_aux_chip_level_reset_0_MASK 0x00080000
-#define BCHP_AON_CTRL_RESET_HISTORY_aux_chip_level_reset_0_SHIFT 19
-#define BCHP_AON_CTRL_RESET_HISTORY_aux_chip_level_reset_0_DEFAULT 0x00000000
-
-/* AON_CTRL :: RESET_HISTORY :: aux_chip_edge_reset_1 [18:18] */
-#define BCHP_AON_CTRL_RESET_HISTORY_aux_chip_edge_reset_1_MASK 0x00040000
-#define BCHP_AON_CTRL_RESET_HISTORY_aux_chip_edge_reset_1_SHIFT 18
-#define BCHP_AON_CTRL_RESET_HISTORY_aux_chip_edge_reset_1_DEFAULT 0x00000000
-
-/* AON_CTRL :: RESET_HISTORY :: aux_chip_edge_reset_0 [17:17] */
-#define BCHP_AON_CTRL_RESET_HISTORY_aux_chip_edge_reset_0_MASK 0x00020000
-#define BCHP_AON_CTRL_RESET_HISTORY_aux_chip_edge_reset_0_SHIFT 17
-#define BCHP_AON_CTRL_RESET_HISTORY_aux_chip_edge_reset_0_DEFAULT 0x00000000
-
-/* AON_CTRL :: RESET_HISTORY :: scpu_ejtag_reset [16:16] */
-#define BCHP_AON_CTRL_RESET_HISTORY_scpu_ejtag_reset_MASK 0x00010000
-#define BCHP_AON_CTRL_RESET_HISTORY_scpu_ejtag_reset_SHIFT 16
-#define BCHP_AON_CTRL_RESET_HISTORY_scpu_ejtag_reset_DEFAULT 0x00000000
-
-/* AON_CTRL :: RESET_HISTORY :: cpu_ejtag_reset [15:15] */
-#define BCHP_AON_CTRL_RESET_HISTORY_cpu_ejtag_reset_MASK 0x00008000
-#define BCHP_AON_CTRL_RESET_HISTORY_cpu_ejtag_reset_SHIFT 15
-#define BCHP_AON_CTRL_RESET_HISTORY_cpu_ejtag_reset_DEFAULT 0x00000000
-
-/* AON_CTRL :: RESET_HISTORY :: overtemp_reset [14:14] */
-#define BCHP_AON_CTRL_RESET_HISTORY_overtemp_reset_MASK 0x00004000
-#define BCHP_AON_CTRL_RESET_HISTORY_overtemp_reset_SHIFT 14
-#define BCHP_AON_CTRL_RESET_HISTORY_overtemp_reset_DEFAULT 0x00000000
-
-/* AON_CTRL :: RESET_HISTORY :: overvoltage_1_reset [13:13] */
-#define BCHP_AON_CTRL_RESET_HISTORY_overvoltage_1_reset_MASK 0x00002000
-#define BCHP_AON_CTRL_RESET_HISTORY_overvoltage_1_reset_SHIFT 13
-#define BCHP_AON_CTRL_RESET_HISTORY_overvoltage_1_reset_DEFAULT 0x00000000
-
-/* AON_CTRL :: RESET_HISTORY :: undervoltage_1_reset [12:12] */
-#define BCHP_AON_CTRL_RESET_HISTORY_undervoltage_1_reset_MASK 0x00001000
-#define BCHP_AON_CTRL_RESET_HISTORY_undervoltage_1_reset_SHIFT 12
-#define BCHP_AON_CTRL_RESET_HISTORY_undervoltage_1_reset_DEFAULT 0x00000000
-
-/* AON_CTRL :: RESET_HISTORY :: undervoltage_0_reset [11:11] */
-#define BCHP_AON_CTRL_RESET_HISTORY_undervoltage_0_reset_MASK 0x00000800
-#define BCHP_AON_CTRL_RESET_HISTORY_undervoltage_0_reset_SHIFT 11
-#define BCHP_AON_CTRL_RESET_HISTORY_undervoltage_0_reset_DEFAULT 0x00000000
-
-/* AON_CTRL :: RESET_HISTORY :: security_master_reset [10:10] */
-#define BCHP_AON_CTRL_RESET_HISTORY_security_master_reset_MASK 0x00000400
-#define BCHP_AON_CTRL_RESET_HISTORY_security_master_reset_SHIFT 10
-#define BCHP_AON_CTRL_RESET_HISTORY_security_master_reset_DEFAULT 0x00000000
-
-/* AON_CTRL :: RESET_HISTORY :: software_master_reset [09:09] */
-#define BCHP_AON_CTRL_RESET_HISTORY_software_master_reset_MASK 0x00000200
-#define BCHP_AON_CTRL_RESET_HISTORY_software_master_reset_SHIFT 9
-#define BCHP_AON_CTRL_RESET_HISTORY_software_master_reset_DEFAULT 0x00000000
-
-/* AON_CTRL :: RESET_HISTORY :: pcie_1_hot_boot_reset [08:08] */
-#define BCHP_AON_CTRL_RESET_HISTORY_pcie_1_hot_boot_reset_MASK 0x00000100
-#define BCHP_AON_CTRL_RESET_HISTORY_pcie_1_hot_boot_reset_SHIFT 8
-#define BCHP_AON_CTRL_RESET_HISTORY_pcie_1_hot_boot_reset_DEFAULT 0x00000000
-
-/* AON_CTRL :: RESET_HISTORY :: pcie_0_hot_boot_reset [07:07] */
-#define BCHP_AON_CTRL_RESET_HISTORY_pcie_0_hot_boot_reset_MASK 0x00000080
-#define BCHP_AON_CTRL_RESET_HISTORY_pcie_0_hot_boot_reset_SHIFT 7
-#define BCHP_AON_CTRL_RESET_HISTORY_pcie_0_hot_boot_reset_DEFAULT 0x00000000
-
-/* AON_CTRL :: RESET_HISTORY :: watchdog_timer_reset [06:06] */
-#define BCHP_AON_CTRL_RESET_HISTORY_watchdog_timer_reset_MASK 0x00000040
-#define BCHP_AON_CTRL_RESET_HISTORY_watchdog_timer_reset_SHIFT 6
-#define BCHP_AON_CTRL_RESET_HISTORY_watchdog_timer_reset_DEFAULT 0x00000000
-
-/* AON_CTRL :: RESET_HISTORY :: smartcard_insert_reset [05:05] */
-#define BCHP_AON_CTRL_RESET_HISTORY_smartcard_insert_reset_MASK 0x00000020
-#define BCHP_AON_CTRL_RESET_HISTORY_smartcard_insert_reset_SHIFT 5
-#define BCHP_AON_CTRL_RESET_HISTORY_smartcard_insert_reset_DEFAULT 0x00000000
-
-/* AON_CTRL :: RESET_HISTORY :: s3_wakeup_reset [04:04] */
-#define BCHP_AON_CTRL_RESET_HISTORY_s3_wakeup_reset_MASK 0x00000010
-#define BCHP_AON_CTRL_RESET_HISTORY_s3_wakeup_reset_SHIFT 4
-#define BCHP_AON_CTRL_RESET_HISTORY_s3_wakeup_reset_DEFAULT 0x00000000
-
-/* AON_CTRL :: RESET_HISTORY :: front_panel_4sec_reset [03:03] */
-#define BCHP_AON_CTRL_RESET_HISTORY_front_panel_4sec_reset_MASK 0x00000008
-#define BCHP_AON_CTRL_RESET_HISTORY_front_panel_4sec_reset_SHIFT 3
-#define BCHP_AON_CTRL_RESET_HISTORY_front_panel_4sec_reset_DEFAULT 0x00000000
-
-/* AON_CTRL :: RESET_HISTORY :: tap_in_system_reset [02:02] */
-#define BCHP_AON_CTRL_RESET_HISTORY_tap_in_system_reset_MASK 0x00000004
-#define BCHP_AON_CTRL_RESET_HISTORY_tap_in_system_reset_SHIFT 2
-#define BCHP_AON_CTRL_RESET_HISTORY_tap_in_system_reset_DEFAULT 0x00000000
-
-/* AON_CTRL :: RESET_HISTORY :: main_chip_reset_input [01:01] */
-#define BCHP_AON_CTRL_RESET_HISTORY_main_chip_reset_input_MASK 0x00000002
-#define BCHP_AON_CTRL_RESET_HISTORY_main_chip_reset_input_SHIFT 1
-#define BCHP_AON_CTRL_RESET_HISTORY_main_chip_reset_input_DEFAULT 0x00000000
-
-/* AON_CTRL :: RESET_HISTORY :: power_on_reset [00:00] */
-#define BCHP_AON_CTRL_RESET_HISTORY_power_on_reset_MASK 0x00000001
-#define BCHP_AON_CTRL_RESET_HISTORY_power_on_reset_SHIFT 0
-#define BCHP_AON_CTRL_RESET_HISTORY_power_on_reset_DEFAULT 0x00000001
-
-/***************************************************************************
- *NMI_CTRL - Control register for NMI
- ***************************************************************************/
-/* AON_CTRL :: NMI_CTRL :: nmi_config_lock [31:31] */
-#define BCHP_AON_CTRL_NMI_CTRL_nmi_config_lock_MASK 0x80000000
-#define BCHP_AON_CTRL_NMI_CTRL_nmi_config_lock_SHIFT 31
-#define BCHP_AON_CTRL_NMI_CTRL_nmi_config_lock_DEFAULT 0x00000000
-
-/* AON_CTRL :: NMI_CTRL :: reserved0 [30:03] */
-#define BCHP_AON_CTRL_NMI_CTRL_reserved0_MASK 0x7ffffff8
-#define BCHP_AON_CTRL_NMI_CTRL_reserved0_SHIFT 3
-
-/* AON_CTRL :: NMI_CTRL :: nmi_pad_monitor [02:02] */
-#define BCHP_AON_CTRL_NMI_CTRL_nmi_pad_monitor_MASK 0x00000004
-#define BCHP_AON_CTRL_NMI_CTRL_nmi_pad_monitor_SHIFT 2
-
-/* AON_CTRL :: NMI_CTRL :: config_nmi_polarity [01:01] */
-#define BCHP_AON_CTRL_NMI_CTRL_config_nmi_polarity_MASK 0x00000002
-#define BCHP_AON_CTRL_NMI_CTRL_config_nmi_polarity_SHIFT 1
-#define BCHP_AON_CTRL_NMI_CTRL_config_nmi_polarity_DEFAULT 0x00000000
-
-/* AON_CTRL :: NMI_CTRL :: disable_pad_nmi [00:00] */
-#define BCHP_AON_CTRL_NMI_CTRL_disable_pad_nmi_MASK 0x00000001
-#define BCHP_AON_CTRL_NMI_CTRL_disable_pad_nmi_SHIFT 0
-#define BCHP_AON_CTRL_NMI_CTRL_disable_pad_nmi_DEFAULT 0x00000001
-
-/***************************************************************************
- *ANA_XTAL_CONTROL - Ana xtal gisb control
- ***************************************************************************/
-/* AON_CTRL :: ANA_XTAL_CONTROL :: reserved0 [31:12] */
-#define BCHP_AON_CTRL_ANA_XTAL_CONTROL_reserved0_MASK 0xfffff000
-#define BCHP_AON_CTRL_ANA_XTAL_CONTROL_reserved0_SHIFT 12
-
-/* AON_CTRL :: ANA_XTAL_CONTROL :: osc_ldo_ctrl [11:08] */
-#define BCHP_AON_CTRL_ANA_XTAL_CONTROL_osc_ldo_ctrl_MASK 0x00000f00
-#define BCHP_AON_CTRL_ANA_XTAL_CONTROL_osc_ldo_ctrl_SHIFT 8
-#define BCHP_AON_CTRL_ANA_XTAL_CONTROL_osc_ldo_ctrl_DEFAULT 0x00000005
-
-/* AON_CTRL :: ANA_XTAL_CONTROL :: osc_select_current_gisb_control [07:07] */
-#define BCHP_AON_CTRL_ANA_XTAL_CONTROL_osc_select_current_gisb_control_MASK 0x00000080
-#define BCHP_AON_CTRL_ANA_XTAL_CONTROL_osc_select_current_gisb_control_SHIFT 7
-#define BCHP_AON_CTRL_ANA_XTAL_CONTROL_osc_select_current_gisb_control_DEFAULT 0x00000000
-
-/* AON_CTRL :: ANA_XTAL_CONTROL :: osc_cml_sel_pd [06:03] */
-#define BCHP_AON_CTRL_ANA_XTAL_CONTROL_osc_cml_sel_pd_MASK 0x00000078
-#define BCHP_AON_CTRL_ANA_XTAL_CONTROL_osc_cml_sel_pd_SHIFT 3
-#define BCHP_AON_CTRL_ANA_XTAL_CONTROL_osc_cml_sel_pd_DEFAULT 0x00000000
-
-/* AON_CTRL :: ANA_XTAL_CONTROL :: osc_d2cbias_gisb_control [02:00] */
-#define BCHP_AON_CTRL_ANA_XTAL_CONTROL_osc_d2cbias_gisb_control_MASK 0x00000007
-#define BCHP_AON_CTRL_ANA_XTAL_CONTROL_osc_d2cbias_gisb_control_SHIFT 0
-#define BCHP_AON_CTRL_ANA_XTAL_CONTROL_osc_d2cbias_gisb_control_DEFAULT 0x00000004
-
-/***************************************************************************
- *SUB_TEST_MODE_CTRL - Test_mode control register
- ***************************************************************************/
-/* AON_CTRL :: SUB_TEST_MODE_CTRL :: reserved0 [31:01] */
-#define BCHP_AON_CTRL_SUB_TEST_MODE_CTRL_reserved0_MASK 0xfffffffe
-#define BCHP_AON_CTRL_SUB_TEST_MODE_CTRL_reserved0_SHIFT 1
-
-/* AON_CTRL :: SUB_TEST_MODE_CTRL :: use_sub_test_mode_reg_src [00:00] */
-#define BCHP_AON_CTRL_SUB_TEST_MODE_CTRL_use_sub_test_mode_reg_src_MASK 0x00000001
-#define BCHP_AON_CTRL_SUB_TEST_MODE_CTRL_use_sub_test_mode_reg_src_SHIFT 0
-#define BCHP_AON_CTRL_SUB_TEST_MODE_CTRL_use_sub_test_mode_reg_src_DEFAULT 0x00000000
-
-/***************************************************************************
- *SUB_TEST_MODE - Register source for sub_test_mode
- ***************************************************************************/
-/* AON_CTRL :: SUB_TEST_MODE :: reserved0 [31:09] */
-#define BCHP_AON_CTRL_SUB_TEST_MODE_reserved0_MASK 0xfffffe00
-#define BCHP_AON_CTRL_SUB_TEST_MODE_reserved0_SHIFT 9
-
-/* AON_CTRL :: SUB_TEST_MODE :: sub_test_mode_spare_1 [08:08] */
-#define BCHP_AON_CTRL_SUB_TEST_MODE_sub_test_mode_spare_1_MASK 0x00000100
-#define BCHP_AON_CTRL_SUB_TEST_MODE_sub_test_mode_spare_1_SHIFT 8
-#define BCHP_AON_CTRL_SUB_TEST_MODE_sub_test_mode_spare_1_DEFAULT 0x00000000
-
-/* AON_CTRL :: SUB_TEST_MODE :: sub_test_mode_spare_0 [07:07] */
-#define BCHP_AON_CTRL_SUB_TEST_MODE_sub_test_mode_spare_0_MASK 0x00000080
-#define BCHP_AON_CTRL_SUB_TEST_MODE_sub_test_mode_spare_0_SHIFT 7
-#define BCHP_AON_CTRL_SUB_TEST_MODE_sub_test_mode_spare_0_DEFAULT 0x00000000
-
-/* AON_CTRL :: SUB_TEST_MODE :: sub_test_mode_alt_spi_slave_enable [06:06] */
-#define BCHP_AON_CTRL_SUB_TEST_MODE_sub_test_mode_alt_spi_slave_enable_MASK 0x00000040
-#define BCHP_AON_CTRL_SUB_TEST_MODE_sub_test_mode_alt_spi_slave_enable_SHIFT 6
-#define BCHP_AON_CTRL_SUB_TEST_MODE_sub_test_mode_alt_spi_slave_enable_DEFAULT 0x00000000
-
-/* AON_CTRL :: SUB_TEST_MODE :: sub_test_mode_fast_tspi [05:05] */
-#define BCHP_AON_CTRL_SUB_TEST_MODE_sub_test_mode_fast_tspi_MASK 0x00000020
-#define BCHP_AON_CTRL_SUB_TEST_MODE_sub_test_mode_fast_tspi_SHIFT 5
-#define BCHP_AON_CTRL_SUB_TEST_MODE_sub_test_mode_fast_tspi_DEFAULT 0x00000000
-
-/* AON_CTRL :: SUB_TEST_MODE :: sub_test_mode_hold_cpu_in_reset [04:04] */
-#define BCHP_AON_CTRL_SUB_TEST_MODE_sub_test_mode_hold_cpu_in_reset_MASK 0x00000010
-#define BCHP_AON_CTRL_SUB_TEST_MODE_sub_test_mode_hold_cpu_in_reset_SHIFT 4
-#define BCHP_AON_CTRL_SUB_TEST_MODE_sub_test_mode_hold_cpu_in_reset_DEFAULT 0x00000000
-
-/* AON_CTRL :: SUB_TEST_MODE :: sub_test_mode_spi_slave_enable [03:03] */
-#define BCHP_AON_CTRL_SUB_TEST_MODE_sub_test_mode_spi_slave_enable_MASK 0x00000008
-#define BCHP_AON_CTRL_SUB_TEST_MODE_sub_test_mode_spi_slave_enable_SHIFT 3
-#define BCHP_AON_CTRL_SUB_TEST_MODE_sub_test_mode_spi_slave_enable_DEFAULT 0x00000000
-
-/* AON_CTRL :: SUB_TEST_MODE :: sub_test_mode_extend_reset [02:02] */
-#define BCHP_AON_CTRL_SUB_TEST_MODE_sub_test_mode_extend_reset_MASK 0x00000004
-#define BCHP_AON_CTRL_SUB_TEST_MODE_sub_test_mode_extend_reset_SHIFT 2
-#define BCHP_AON_CTRL_SUB_TEST_MODE_sub_test_mode_extend_reset_DEFAULT 0x00000000
-
-/* AON_CTRL :: SUB_TEST_MODE :: sub_test_mode_bsp_debug [01:00] */
-#define BCHP_AON_CTRL_SUB_TEST_MODE_sub_test_mode_bsp_debug_MASK 0x00000003
-#define BCHP_AON_CTRL_SUB_TEST_MODE_sub_test_mode_bsp_debug_SHIFT 0
-#define BCHP_AON_CTRL_SUB_TEST_MODE_sub_test_mode_bsp_debug_DEFAULT 0x00000000
-
-/***************************************************************************
- *LATCHED_TEST_MODE - Final latched testmode value
- ***************************************************************************/
-/* AON_CTRL :: LATCHED_TEST_MODE :: latched_test_mode [31:00] */
-#define BCHP_AON_CTRL_LATCHED_TEST_MODE_latched_test_mode_MASK 0xffffffff
-#define BCHP_AON_CTRL_LATCHED_TEST_MODE_latched_test_mode_SHIFT 0
-
-/***************************************************************************
- *LATCHED_SUB_TEST_MODE - Final latched sub-testmode value
- ***************************************************************************/
-/* AON_CTRL :: LATCHED_SUB_TEST_MODE :: latched_sub_test_mode [31:00] */
-#define BCHP_AON_CTRL_LATCHED_SUB_TEST_MODE_latched_sub_test_mode_MASK 0xffffffff
-#define BCHP_AON_CTRL_LATCHED_SUB_TEST_MODE_latched_sub_test_mode_SHIFT 0
-
-/***************************************************************************
- *PM_INITIATE - Power down initiate
- ***************************************************************************/
-/* AON_CTRL :: PM_INITIATE :: reserved0 [31:08] */
-#define BCHP_AON_CTRL_PM_INITIATE_reserved0_MASK 0xffffff00
-#define BCHP_AON_CTRL_PM_INITIATE_reserved0_SHIFT 8
-
-/* AON_CTRL :: PM_INITIATE :: pm_initiate_7 [07:07] */
-#define BCHP_AON_CTRL_PM_INITIATE_pm_initiate_7_MASK 0x00000080
-#define BCHP_AON_CTRL_PM_INITIATE_pm_initiate_7_SHIFT 7
-#define BCHP_AON_CTRL_PM_INITIATE_pm_initiate_7_DEFAULT 0x00000000
-
-/* AON_CTRL :: PM_INITIATE :: pm_initiate_6 [06:06] */
-#define BCHP_AON_CTRL_PM_INITIATE_pm_initiate_6_MASK 0x00000040
-#define BCHP_AON_CTRL_PM_INITIATE_pm_initiate_6_SHIFT 6
-#define BCHP_AON_CTRL_PM_INITIATE_pm_initiate_6_DEFAULT 0x00000000
-
-/* AON_CTRL :: PM_INITIATE :: pm_initiate_5 [05:05] */
-#define BCHP_AON_CTRL_PM_INITIATE_pm_initiate_5_MASK 0x00000020
-#define BCHP_AON_CTRL_PM_INITIATE_pm_initiate_5_SHIFT 5
-#define BCHP_AON_CTRL_PM_INITIATE_pm_initiate_5_DEFAULT 0x00000000
-
-/* AON_CTRL :: PM_INITIATE :: pm_initiate_4 [04:04] */
-#define BCHP_AON_CTRL_PM_INITIATE_pm_initiate_4_MASK 0x00000010
-#define BCHP_AON_CTRL_PM_INITIATE_pm_initiate_4_SHIFT 4
-#define BCHP_AON_CTRL_PM_INITIATE_pm_initiate_4_DEFAULT 0x00000000
-
-/* AON_CTRL :: PM_INITIATE :: pm_initiate_3 [03:03] */
-#define BCHP_AON_CTRL_PM_INITIATE_pm_initiate_3_MASK 0x00000008
-#define BCHP_AON_CTRL_PM_INITIATE_pm_initiate_3_SHIFT 3
-#define BCHP_AON_CTRL_PM_INITIATE_pm_initiate_3_DEFAULT 0x00000000
-
-/* AON_CTRL :: PM_INITIATE :: pm_initiate_2 [02:02] */
-#define BCHP_AON_CTRL_PM_INITIATE_pm_initiate_2_MASK 0x00000004
-#define BCHP_AON_CTRL_PM_INITIATE_pm_initiate_2_SHIFT 2
-#define BCHP_AON_CTRL_PM_INITIATE_pm_initiate_2_DEFAULT 0x00000000
-
-/* AON_CTRL :: PM_INITIATE :: pm_initiate_1 [01:01] */
-#define BCHP_AON_CTRL_PM_INITIATE_pm_initiate_1_MASK 0x00000002
-#define BCHP_AON_CTRL_PM_INITIATE_pm_initiate_1_SHIFT 1
-#define BCHP_AON_CTRL_PM_INITIATE_pm_initiate_1_DEFAULT 0x00000000
-
-/* AON_CTRL :: PM_INITIATE :: pm_initiate_0 [00:00] */
-#define BCHP_AON_CTRL_PM_INITIATE_pm_initiate_0_MASK 0x00000001
-#define BCHP_AON_CTRL_PM_INITIATE_pm_initiate_0_SHIFT 0
-#define BCHP_AON_CTRL_PM_INITIATE_pm_initiate_0_DEFAULT 0x00000000
-
-/***************************************************************************
- *HOST_MISC_CMDS - Power up restore
- ***************************************************************************/
-/* AON_CTRL :: HOST_MISC_CMDS :: reserved0 [31:08] */
-#define BCHP_AON_CTRL_HOST_MISC_CMDS_reserved0_MASK 0xffffff00
-#define BCHP_AON_CTRL_HOST_MISC_CMDS_reserved0_SHIFT 8
-
-/* AON_CTRL :: HOST_MISC_CMDS :: host_misc_cmds_7 [07:07] */
-#define BCHP_AON_CTRL_HOST_MISC_CMDS_host_misc_cmds_7_MASK 0x00000080
-#define BCHP_AON_CTRL_HOST_MISC_CMDS_host_misc_cmds_7_SHIFT 7
-#define BCHP_AON_CTRL_HOST_MISC_CMDS_host_misc_cmds_7_DEFAULT 0x00000000
-
-/* AON_CTRL :: HOST_MISC_CMDS :: host_misc_cmds_6 [06:06] */
-#define BCHP_AON_CTRL_HOST_MISC_CMDS_host_misc_cmds_6_MASK 0x00000040
-#define BCHP_AON_CTRL_HOST_MISC_CMDS_host_misc_cmds_6_SHIFT 6
-#define BCHP_AON_CTRL_HOST_MISC_CMDS_host_misc_cmds_6_DEFAULT 0x00000000
-
-/* AON_CTRL :: HOST_MISC_CMDS :: host_misc_cmds_5 [05:05] */
-#define BCHP_AON_CTRL_HOST_MISC_CMDS_host_misc_cmds_5_MASK 0x00000020
-#define BCHP_AON_CTRL_HOST_MISC_CMDS_host_misc_cmds_5_SHIFT 5
-#define BCHP_AON_CTRL_HOST_MISC_CMDS_host_misc_cmds_5_DEFAULT 0x00000000
-
-/* AON_CTRL :: HOST_MISC_CMDS :: host_misc_cmds_4 [04:04] */
-#define BCHP_AON_CTRL_HOST_MISC_CMDS_host_misc_cmds_4_MASK 0x00000010
-#define BCHP_AON_CTRL_HOST_MISC_CMDS_host_misc_cmds_4_SHIFT 4
-#define BCHP_AON_CTRL_HOST_MISC_CMDS_host_misc_cmds_4_DEFAULT 0x00000000
-
-/* AON_CTRL :: HOST_MISC_CMDS :: host_misc_cmds_3 [03:03] */
-#define BCHP_AON_CTRL_HOST_MISC_CMDS_host_misc_cmds_3_MASK 0x00000008
-#define BCHP_AON_CTRL_HOST_MISC_CMDS_host_misc_cmds_3_SHIFT 3
-#define BCHP_AON_CTRL_HOST_MISC_CMDS_host_misc_cmds_3_DEFAULT 0x00000000
-
-/* AON_CTRL :: HOST_MISC_CMDS :: host_misc_cmds_2 [02:02] */
-#define BCHP_AON_CTRL_HOST_MISC_CMDS_host_misc_cmds_2_MASK 0x00000004
-#define BCHP_AON_CTRL_HOST_MISC_CMDS_host_misc_cmds_2_SHIFT 2
-#define BCHP_AON_CTRL_HOST_MISC_CMDS_host_misc_cmds_2_DEFAULT 0x00000000
-
-/* AON_CTRL :: HOST_MISC_CMDS :: dram_scram_key_reuse_req [01:01] */
-#define BCHP_AON_CTRL_HOST_MISC_CMDS_dram_scram_key_reuse_req_MASK 0x00000002
-#define BCHP_AON_CTRL_HOST_MISC_CMDS_dram_scram_key_reuse_req_SHIFT 1
-#define BCHP_AON_CTRL_HOST_MISC_CMDS_dram_scram_key_reuse_req_DEFAULT 0x00000000
-
-/* AON_CTRL :: HOST_MISC_CMDS :: pm_restore [00:00] */
-#define BCHP_AON_CTRL_HOST_MISC_CMDS_pm_restore_MASK 0x00000001
-#define BCHP_AON_CTRL_HOST_MISC_CMDS_pm_restore_SHIFT 0
-#define BCHP_AON_CTRL_HOST_MISC_CMDS_pm_restore_DEFAULT 0x00000000
-
-/***************************************************************************
- *ANA_XTAL_EXT_CML_CONTROL - Ana xtal external CML control
- ***************************************************************************/
-/* AON_CTRL :: ANA_XTAL_EXT_CML_CONTROL :: reserved0 [31:06] */
-#define BCHP_AON_CTRL_ANA_XTAL_EXT_CML_CONTROL_reserved0_MASK 0xffffffc0
-#define BCHP_AON_CTRL_ANA_XTAL_EXT_CML_CONTROL_reserved0_SHIFT 6
-
-/* AON_CTRL :: ANA_XTAL_EXT_CML_CONTROL :: osc_PMSM_S3_pd_buffer [05:05] */
-#define BCHP_AON_CTRL_ANA_XTAL_EXT_CML_CONTROL_osc_PMSM_S3_pd_buffer_MASK 0x00000020
-#define BCHP_AON_CTRL_ANA_XTAL_EXT_CML_CONTROL_osc_PMSM_S3_pd_buffer_SHIFT 5
-#define BCHP_AON_CTRL_ANA_XTAL_EXT_CML_CONTROL_osc_PMSM_S3_pd_buffer_DEFAULT 0x00000000
-
-/* AON_CTRL :: ANA_XTAL_EXT_CML_CONTROL :: osc_override_strap [04:04] */
-#define BCHP_AON_CTRL_ANA_XTAL_EXT_CML_CONTROL_osc_override_strap_MASK 0x00000010
-#define BCHP_AON_CTRL_ANA_XTAL_EXT_CML_CONTROL_osc_override_strap_SHIFT 4
-#define BCHP_AON_CTRL_ANA_XTAL_EXT_CML_CONTROL_osc_override_strap_DEFAULT 0x00000000
-
-/* AON_CTRL :: ANA_XTAL_EXT_CML_CONTROL :: osc_pd_buffer [03:03] */
-#define BCHP_AON_CTRL_ANA_XTAL_EXT_CML_CONTROL_osc_pd_buffer_MASK 0x00000008
-#define BCHP_AON_CTRL_ANA_XTAL_EXT_CML_CONTROL_osc_pd_buffer_SHIFT 3
-#define BCHP_AON_CTRL_ANA_XTAL_EXT_CML_CONTROL_osc_pd_buffer_DEFAULT 0x00000000
-
-/* AON_CTRL :: ANA_XTAL_EXT_CML_CONTROL :: osc_div2_sel [02:02] */
-#define BCHP_AON_CTRL_ANA_XTAL_EXT_CML_CONTROL_osc_div2_sel_MASK 0x00000004
-#define BCHP_AON_CTRL_ANA_XTAL_EXT_CML_CONTROL_osc_div2_sel_SHIFT 2
-#define BCHP_AON_CTRL_ANA_XTAL_EXT_CML_CONTROL_osc_div2_sel_DEFAULT 0x00000001
-
-/* AON_CTRL :: ANA_XTAL_EXT_CML_CONTROL :: osc_current [01:00] */
-#define BCHP_AON_CTRL_ANA_XTAL_EXT_CML_CONTROL_osc_current_MASK 0x00000003
-#define BCHP_AON_CTRL_ANA_XTAL_EXT_CML_CONTROL_osc_current_SHIFT 0
-#define BCHP_AON_CTRL_ANA_XTAL_EXT_CML_CONTROL_osc_current_DEFAULT 0x00000001
-
-/***************************************************************************
- *SYSTEM_DATA_RAM%i - System Data RAM Address 0..127
- ***************************************************************************/
-#define BCHP_AON_CTRL_SYSTEM_DATA_RAMi_ARRAY_BASE 0x00410200
-#define BCHP_AON_CTRL_SYSTEM_DATA_RAMi_ARRAY_START 0
-#define BCHP_AON_CTRL_SYSTEM_DATA_RAMi_ARRAY_END 127
-#define BCHP_AON_CTRL_SYSTEM_DATA_RAMi_ARRAY_ELEMENT_SIZE 32
-
-/***************************************************************************
- *SYSTEM_DATA_RAM%i - System Data RAM Address 0..127
- ***************************************************************************/
-/* AON_CTRL :: SYSTEM_DATA_RAMi :: SYSTEM_DATA_RAM [31:00] */
-#define BCHP_AON_CTRL_SYSTEM_DATA_RAMi_SYSTEM_DATA_RAM_MASK 0xffffffff
-#define BCHP_AON_CTRL_SYSTEM_DATA_RAMi_SYSTEM_DATA_RAM_SHIFT 0
-
-
-#endif /* #ifndef BCHP_AON_CTRL_H__ */
-
-/* End of File */
diff --git a/include/linux/brcmstb/7439a0/bchp_aon_pin_ctrl.h b/include/linux/brcmstb/7439a0/bchp_aon_pin_ctrl.h
deleted file mode 100644
index cc59134..0000000
--- a/include/linux/brcmstb/7439a0/bchp_aon_pin_ctrl.h
+++ /dev/null
@@ -1,524 +0,0 @@
-/***************************************************************************
- * Copyright (c) 1999-2014, Broadcom Corporation
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
- *
- * Module Description:
- * DO NOT EDIT THIS FILE DIRECTLY
- *
- * This module was generated magically with RDB from a source description
- * file. You must edit the source file for changes to be made to this file.
- *
- *
- * Date: Generated on Wed Sep 3 14:30:55 2014
- * Full Compile MD5 Checksum edbc259d5ef948d04693ec04bc4d44b4
- * (minus title and desc)
- * MD5 Checksum de2524c7728bb833dc65ac44b70daaa5
- *
- * Compiled with: RDB Utility combo_header.pl
- * RDB Parser 3.0
- * unknown unknown
- * Perl Interpreter 5.008005
- * Operating System linux
- *
- * Revision History:
- *
- * $brcm_Log: $
- *
- ***************************************************************************/
-
-#ifndef BCHP_AON_PIN_CTRL_H__
-#define BCHP_AON_PIN_CTRL_H__
-
-/***************************************************************************
- *AON_PIN_CTRL - AON Pinmux Control Registers
- ***************************************************************************/
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0 0x00410500 /* Pinmux control register 0 */
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1 0x00410504 /* Pinmux control register 1 */
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2 0x00410508 /* Pinmux control register 2 */
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_3 0x0041050c /* Pinmux control register 3 */
-#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0 0x00410510 /* Pad pull-up/pull-down control register 0 */
-#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1 0x00410514 /* Pad pull-up/pull-down control register 1 */
-#define BCHP_AON_PIN_CTRL_BYP_CLK_UNSELECT_0 0x00410518 /* Bypass clock unselect register 0 */
-
-/***************************************************************************
- *PIN_MUX_CTRL_0 - Pinmux control register 0
- ***************************************************************************/
-/* AON_PIN_CTRL :: PIN_MUX_CTRL_0 :: aon_gpio_07 [31:28] */
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_07_MASK 0xf0000000
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_07_SHIFT 28
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_07_DEFAULT 0x00000000
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_07_AON_GPIO_07 0
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_07_LED_LS_0 1
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_07_LED_LD_12 2
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_07_TP_OUT_07 3
-
-/* AON_PIN_CTRL :: PIN_MUX_CTRL_0 :: aon_gpio_06 [27:24] */
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_06_MASK 0x0f000000
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_06_SHIFT 24
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_06_DEFAULT 0x00000000
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_06_AON_GPIO_06 0
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_06_LED_KD_3 1
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_06_LED_LD_11 2
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_06_I2S_LR0_OUT 3
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_06_ENET0_ACTIVITY 4
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_06_TP_OUT_06 5
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_06_PM_AON_GPIO_06 6
-
-/* AON_PIN_CTRL :: PIN_MUX_CTRL_0 :: aon_gpio_05 [23:20] */
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_05_MASK 0x00f00000
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_05_SHIFT 20
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_05_DEFAULT 0x00000000
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_05_AON_GPIO_05 0
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_05_LED_KD_2 1
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_05_LED_LD_10 2
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_05_I2S_DATA0_OUT 3
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_05_SATA_MDIO 4
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_05_PM_AON_GPIO_05 5
-
-/* AON_PIN_CTRL :: PIN_MUX_CTRL_0 :: aon_gpio_04 [19:16] */
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_04_MASK 0x000f0000
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_04_SHIFT 16
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_04_DEFAULT 0x00000000
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_04_AON_GPIO_04 0
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_04_LED_KD_1 1
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_04_LED_LD_9 2
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_04_I2S_CLK0_OUT 3
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_04_SATA_MDCLK 4
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_04_PM_AON_GPIO_04 5
-
-/* AON_PIN_CTRL :: PIN_MUX_CTRL_0 :: aon_gpio_03 [15:12] */
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_03_MASK 0x0000f000
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_03_SHIFT 12
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_03_DEFAULT 0x00000000
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_03_AON_GPIO_03 0
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_03_LED_KD_0 1
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_03_LED_LD_8 2
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_03_RGMII_B_MDIO 3
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_03_TP_OUT_03 4
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_03_PM_AON_GPIO_03 5
-
-/* AON_PIN_CTRL :: PIN_MUX_CTRL_0 :: aon_gpio_02 [11:08] */
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_02_MASK 0x00000f00
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_02_SHIFT 8
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_02_DEFAULT 0x00000000
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_02_AON_GPIO_02 0
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_02_ENET1_LINK 1
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_02_AUD_FS_CLK1 2
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_02_VEC_VSYNC 3
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_02_ENET0_ACTIVITY 5
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_02_TP_OUT_02 6
-
-/* AON_PIN_CTRL :: PIN_MUX_CTRL_0 :: aon_gpio_01 [07:04] */
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_01_MASK 0x000000f0
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_01_SHIFT 4
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_01_DEFAULT 0x00000000
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_01_AON_GPIO_01 0
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_01_ENET0_LINK 1
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_01_PWM0 2
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_01_VEC_HSYNC 3
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_01_SPI_M_SS1B 4
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_01_ENET1_ACTIVITY 5
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_01_TP_OUT_01 6
-
-/* AON_PIN_CTRL :: PIN_MUX_CTRL_0 :: aon_gpio_00 [03:00] */
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_00_MASK 0x0000000f
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_00_SHIFT 0
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_00_DEFAULT 0x00000000
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_00_AON_GPIO_00 0
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_00_IR_INT 1
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_00_PWM1 2
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_00_RGMII_B_MDC 3
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_00_SPI_M_SS2B 4
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_00_TP_OUT_00 6
-
-/***************************************************************************
- *PIN_MUX_CTRL_1 - Pinmux control register 1
- ***************************************************************************/
-/* AON_PIN_CTRL :: PIN_MUX_CTRL_1 :: aon_gpio_15 [31:28] */
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_15_MASK 0xf0000000
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_15_SHIFT 28
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_15_DEFAULT 0x00000000
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_15_AON_GPIO_15 0
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_15_LED_LD_3 1
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_15_UART_CTS_1 2
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_15_I2S_LR0_IN 3
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_15_SPI_S_MISO 4
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_15_PWM2 5
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_15_TP_OUT_13 6
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_15_PM_AON_GPIO_15 7
-
-/* AON_PIN_CTRL :: PIN_MUX_CTRL_1 :: aon_gpio_14 [27:24] */
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_14_MASK 0x0f000000
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_14_SHIFT 24
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_14_DEFAULT 0x00000000
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_14_AON_GPIO_14 0
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_14_LED_LD_2 1
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_14_UART_RTS_1 2
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_14_SPI_S_SS0B 3
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_14_PWM3 4
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_14_TP_OUT_12 5
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_14_PM_AON_GPIO_14 6
-
-/* AON_PIN_CTRL :: PIN_MUX_CTRL_1 :: aon_gpio_13 [23:20] */
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_13_MASK 0x00f00000
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_13_SHIFT 20
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_13_DEFAULT 0x00000000
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_13_AON_GPIO_13 0
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_13_LED_LD_1 1
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_13_UART_TXD_1 2
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_13_ENET0_LINK 3
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_13_ALT_TP_OUT_00 4
-
-/* AON_PIN_CTRL :: PIN_MUX_CTRL_1 :: aon_gpio_12 [19:16] */
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_12_MASK 0x000f0000
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_12_SHIFT 16
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_12_DEFAULT 0x00000000
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_12_AON_GPIO_12 0
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_12_LED_LD_0 1
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_12_UART_RXD_1 2
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_12_I2S_CLK0_IN 3
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_12_IR_IN1 4
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_12_TP_IN_10 5
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_12_PM_AON_GPIO_12 6
-
-/* AON_PIN_CTRL :: PIN_MUX_CTRL_1 :: aon_gpio_11 [15:12] */
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_11_MASK 0x0000f000
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_11_SHIFT 12
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_11_DEFAULT 0x00000000
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_11_AON_GPIO_11 0
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_11_LED_LS_4 1
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_11_UART_CTS_0 2
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_11_I2S_DATA0_IN 3
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_11_TP_OUT_11 4
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_11_PM_AON_GPIO_11 5
-
-/* AON_PIN_CTRL :: PIN_MUX_CTRL_1 :: aon_gpio_10 [11:08] */
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_10_MASK 0x00000f00
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_10_SHIFT 8
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_10_DEFAULT 0x00000000
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_10_AON_GPIO_10 0
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_10_LED_LS_3 1
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_10_UART_RTS_0 2
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_10_LED_LD_15 3
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_10_TP_OUT_10 4
-
-/* AON_PIN_CTRL :: PIN_MUX_CTRL_1 :: aon_gpio_09 [07:04] */
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_09_MASK 0x000000f0
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_09_SHIFT 4
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_09_DEFAULT 0x00000000
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_09_AON_GPIO_09 0
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_09_LED_LS_2 1
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_09_LED_LD_14 2
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_09_SPI_M_SS2B 3
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_09_TP_OUT_09 4
-
-/* AON_PIN_CTRL :: PIN_MUX_CTRL_1 :: aon_gpio_08 [03:00] */
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_08_MASK 0x0000000f
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_08_SHIFT 0
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_08_DEFAULT 0x00000000
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_08_AON_GPIO_08 0
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_08_LED_LS_1 1
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_08_LED_LD_13 2
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_08_SPI_M_SS1B 3
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_08_TP_OUT_08 4
-
-/***************************************************************************
- *PIN_MUX_CTRL_2 - Pinmux control register 2
- ***************************************************************************/
-/* AON_PIN_CTRL :: PIN_MUX_CTRL_2 :: aon_sgpio_02 [31:28] */
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_sgpio_02_MASK 0xf0000000
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_sgpio_02_SHIFT 28
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_sgpio_02_DEFAULT 0x00000000
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_sgpio_02_AON_SGPIO_02 0
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_sgpio_02_BSC_M1_SCL 1
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_sgpio_02_HDMI_TX1_BSC_SCL 2
-
-/* AON_PIN_CTRL :: PIN_MUX_CTRL_2 :: aon_sgpio_01 [27:24] */
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_sgpio_01_MASK 0x0f000000
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_sgpio_01_SHIFT 24
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_sgpio_01_DEFAULT 0x00000000
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_sgpio_01_AON_SGPIO_01 0
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_sgpio_01_BSC_M0_SDA 1
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_sgpio_01_HDMI_TX0_BSC_SDA 2
-
-/* AON_PIN_CTRL :: PIN_MUX_CTRL_2 :: aon_sgpio_00 [23:20] */
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_sgpio_00_MASK 0x00f00000
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_sgpio_00_SHIFT 20
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_sgpio_00_DEFAULT 0x00000000
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_sgpio_00_AON_SGPIO_00 0
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_sgpio_00_BSC_M0_SCL 1
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_sgpio_00_HDMI_TX0_BSC_SCL 2
-
-/* AON_PIN_CTRL :: PIN_MUX_CTRL_2 :: aon_gpio_20 [19:16] */
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_20_MASK 0x000f0000
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_20_SHIFT 16
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_20_DEFAULT 0x00000001
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_20_AON_GPIO_20 0
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_20_LED_OUT 1
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_20_ENET1_LINK 2
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_20_RGMII_B_IRQ 3
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_20_CODEC_MCLK 4
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_20_RO_OBSRV 5
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_20_IR_IN1 6
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_20_TP_OUT_16 7
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_20_PM_AON_GPIO_20 8
-
-/* AON_PIN_CTRL :: PIN_MUX_CTRL_2 :: aon_gpio_19 [15:12] */
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_19_MASK 0x0000f000
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_19_SHIFT 12
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_19_DEFAULT 0x00000000
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_19_AON_GPIO_19 0
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_19_LED_LD_7 1
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_19_UART_RTS_2 2
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_19_SPI_M_SS0B 3
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_19_TP_OUT_15 4
-
-/* AON_PIN_CTRL :: PIN_MUX_CTRL_2 :: aon_gpio_18 [11:08] */
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_18_MASK 0x00000f00
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_18_SHIFT 8
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_18_DEFAULT 0x00000000
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_18_AON_GPIO_18 0
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_18_LED_LD_6 1
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_18_UART_CTS_2 2
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_18_SPI_M_MISO 3
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_18_ENET0_ACTIVITY 4
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_18_ENET1_ACTIVITY 5
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_18_TP_OUT_14 6
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_18_PM_AON_GPIO_18 7
-
-/* AON_PIN_CTRL :: PIN_MUX_CTRL_2 :: aon_gpio_17 [07:04] */
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_17_MASK 0x000000f0
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_17_SHIFT 4
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_17_DEFAULT 0x00000000
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_17_AON_GPIO_17 0
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_17_LED_LD_5 1
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_17_UART_TXD_2 2
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_17_SPI_M_MOSI 3
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_17_ALT_TP_OUT_01 4
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_17_PM_AON_GPIO_17 5
-
-/* AON_PIN_CTRL :: PIN_MUX_CTRL_2 :: aon_gpio_16 [03:00] */
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_16_MASK 0x0000000f
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_16_SHIFT 0
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_16_DEFAULT 0x00000000
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_16_AON_GPIO_16 0
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_16_LED_LD_4 1
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_16_UART_RXD_2 2
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_16_SPI_M_SCK 3
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_16_ENET0_LINK 4
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_16_ENET1_LINK 5
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_16_TP_IN_12 6
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_16_PM_AON_GPIO_16 7
-
-/***************************************************************************
- *PIN_MUX_CTRL_3 - Pinmux control register 3
- ***************************************************************************/
-/* AON_PIN_CTRL :: PIN_MUX_CTRL_3 :: reserved0 [31:20] */
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_3_reserved0_MASK 0xfff00000
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_3_reserved0_SHIFT 20
-
-/* AON_PIN_CTRL :: PIN_MUX_CTRL_3 :: aon_sgpio_07 [19:16] */
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_3_aon_sgpio_07_MASK 0x000f0000
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_3_aon_sgpio_07_SHIFT 16
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_3_aon_sgpio_07_DEFAULT 0x00000000
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_3_aon_sgpio_07_AON_SGPIO_07 0
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_3_aon_sgpio_07_BSC_M3_SDA 1
-
-/* AON_PIN_CTRL :: PIN_MUX_CTRL_3 :: aon_sgpio_06 [15:12] */
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_3_aon_sgpio_06_MASK 0x0000f000
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_3_aon_sgpio_06_SHIFT 12
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_3_aon_sgpio_06_DEFAULT 0x00000000
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_3_aon_sgpio_06_AON_SGPIO_06 0
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_3_aon_sgpio_06_BSC_M3_SCL 1
-
-/* AON_PIN_CTRL :: PIN_MUX_CTRL_3 :: aon_sgpio_05 [11:08] */
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_3_aon_sgpio_05_MASK 0x00000f00
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_3_aon_sgpio_05_SHIFT 8
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_3_aon_sgpio_05_DEFAULT 0x00000000
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_3_aon_sgpio_05_AON_SGPIO_05 0
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_3_aon_sgpio_05_BSC_M2_SDA 1
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_3_aon_sgpio_05_HDMI_RX_BSC_SDA 2
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_3_aon_sgpio_05_BSC_S1_SDA 3
-
-/* AON_PIN_CTRL :: PIN_MUX_CTRL_3 :: aon_sgpio_04 [07:04] */
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_3_aon_sgpio_04_MASK 0x000000f0
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_3_aon_sgpio_04_SHIFT 4
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_3_aon_sgpio_04_DEFAULT 0x00000000
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_3_aon_sgpio_04_AON_SGPIO_04 0
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_3_aon_sgpio_04_BSC_M2_SCL 1
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_3_aon_sgpio_04_HDMI_RX_BSC_SCL 2
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_3_aon_sgpio_04_BSC_S1_SCL 3
-
-/* AON_PIN_CTRL :: PIN_MUX_CTRL_3 :: aon_sgpio_03 [03:00] */
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_3_aon_sgpio_03_MASK 0x0000000f
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_3_aon_sgpio_03_SHIFT 0
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_3_aon_sgpio_03_DEFAULT 0x00000000
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_3_aon_sgpio_03_AON_SGPIO_03 0
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_3_aon_sgpio_03_BSC_M1_SDA 1
-#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_3_aon_sgpio_03_HDMI_TX1_BSC_SDA 2
-
-/***************************************************************************
- *PIN_MUX_PAD_CTRL_0 - Pad pull-up/pull-down control register 0
- ***************************************************************************/
-/* AON_PIN_CTRL :: PIN_MUX_PAD_CTRL_0 :: spare_pad_ctrl_0 [31:30] */
-#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_spare_pad_ctrl_0_MASK 0xc0000000
-#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_spare_pad_ctrl_0_SHIFT 30
-#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_spare_pad_ctrl_0_DEFAULT 0x00000000
-#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_spare_pad_ctrl_0_PULL_NONE 0
-#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_spare_pad_ctrl_0_PULL_DOWN 1
-#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_spare_pad_ctrl_0_PULL_UP 2
-
-/* AON_PIN_CTRL :: PIN_MUX_PAD_CTRL_0 :: reserved0 [29:28] */
-#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_reserved0_MASK 0x30000000
-#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_reserved0_SHIFT 28
-
-/* AON_PIN_CTRL :: PIN_MUX_PAD_CTRL_0 :: aon_gpio_12_pad_ctrl [27:26] */
-#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_12_pad_ctrl_MASK 0x0c000000
-#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_12_pad_ctrl_SHIFT 26
-#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_12_pad_ctrl_DEFAULT 0x00000001
-#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_12_pad_ctrl_PULL_NONE 0
-#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_12_pad_ctrl_PULL_DOWN 1
-#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_12_pad_ctrl_PULL_UP 2
-
-/* AON_PIN_CTRL :: PIN_MUX_PAD_CTRL_0 :: aon_gpio_11_pad_ctrl [25:24] */
-#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_11_pad_ctrl_MASK 0x03000000
-#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_11_pad_ctrl_SHIFT 24
-#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_11_pad_ctrl_DEFAULT 0x00000001
-#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_11_pad_ctrl_PULL_NONE 0
-#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_11_pad_ctrl_PULL_DOWN 1
-#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_11_pad_ctrl_PULL_UP 2
-
-/* AON_PIN_CTRL :: PIN_MUX_PAD_CTRL_0 :: reserved1 [23:16] */
-#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_reserved1_MASK 0x00ff0000
-#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_reserved1_SHIFT 16
-
-/* AON_PIN_CTRL :: PIN_MUX_PAD_CTRL_0 :: aon_gpio_06_pad_ctrl [15:14] */
-#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_06_pad_ctrl_MASK 0x0000c000
-#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_06_pad_ctrl_SHIFT 14
-#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_06_pad_ctrl_DEFAULT 0x00000001
-#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_06_pad_ctrl_PULL_NONE 0
-#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_06_pad_ctrl_PULL_DOWN 1
-#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_06_pad_ctrl_PULL_UP 2
-
-/* AON_PIN_CTRL :: PIN_MUX_PAD_CTRL_0 :: aon_gpio_05_pad_ctrl [13:12] */
-#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_05_pad_ctrl_MASK 0x00003000
-#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_05_pad_ctrl_SHIFT 12
-#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_05_pad_ctrl_DEFAULT 0x00000001
-#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_05_pad_ctrl_PULL_NONE 0
-#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_05_pad_ctrl_PULL_DOWN 1
-#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_05_pad_ctrl_PULL_UP 2
-
-/* AON_PIN_CTRL :: PIN_MUX_PAD_CTRL_0 :: aon_gpio_04_pad_ctrl [11:10] */
-#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_04_pad_ctrl_MASK 0x00000c00
-#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_04_pad_ctrl_SHIFT 10
-#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_04_pad_ctrl_DEFAULT 0x00000001
-#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_04_pad_ctrl_PULL_NONE 0
-#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_04_pad_ctrl_PULL_DOWN 1
-#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_04_pad_ctrl_PULL_UP 2
-
-/* AON_PIN_CTRL :: PIN_MUX_PAD_CTRL_0 :: aon_gpio_03_pad_ctrl [09:08] */
-#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_03_pad_ctrl_MASK 0x00000300
-#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_03_pad_ctrl_SHIFT 8
-#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_03_pad_ctrl_DEFAULT 0x00000001
-#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_03_pad_ctrl_PULL_NONE 0
-#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_03_pad_ctrl_PULL_DOWN 1
-#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_03_pad_ctrl_PULL_UP 2
-
-/* AON_PIN_CTRL :: PIN_MUX_PAD_CTRL_0 :: reserved2 [07:00] */
-#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_reserved2_MASK 0x000000ff
-#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_reserved2_SHIFT 0
-
-/***************************************************************************
- *PIN_MUX_PAD_CTRL_1 - Pad pull-up/pull-down control register 1
- ***************************************************************************/
-/* AON_PIN_CTRL :: PIN_MUX_PAD_CTRL_1 :: spare_pad_ctrl_1 [31:30] */
-#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_spare_pad_ctrl_1_MASK 0xc0000000
-#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_spare_pad_ctrl_1_SHIFT 30
-#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_spare_pad_ctrl_1_DEFAULT 0x00000000
-#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_spare_pad_ctrl_1_PULL_NONE 0
-#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_spare_pad_ctrl_1_PULL_DOWN 1
-#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_spare_pad_ctrl_1_PULL_UP 2
-
-/* AON_PIN_CTRL :: PIN_MUX_PAD_CTRL_1 :: reserved0 [29:14] */
-#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_reserved0_MASK 0x3fffc000
-#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_reserved0_SHIFT 14
-
-/* AON_PIN_CTRL :: PIN_MUX_PAD_CTRL_1 :: aon_gpio_20_pad_ctrl [13:12] */
-#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_20_pad_ctrl_MASK 0x00003000
-#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_20_pad_ctrl_SHIFT 12
-#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_20_pad_ctrl_DEFAULT 0x00000001
-#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_20_pad_ctrl_PULL_NONE 0
-#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_20_pad_ctrl_PULL_DOWN 1
-#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_20_pad_ctrl_PULL_UP 2
-
-/* AON_PIN_CTRL :: PIN_MUX_PAD_CTRL_1 :: reserved1 [11:10] */
-#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_reserved1_MASK 0x00000c00
-#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_reserved1_SHIFT 10
-
-/* AON_PIN_CTRL :: PIN_MUX_PAD_CTRL_1 :: aon_gpio_18_pad_ctrl [09:08] */
-#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_18_pad_ctrl_MASK 0x00000300
-#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_18_pad_ctrl_SHIFT 8
-#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_18_pad_ctrl_DEFAULT 0x00000001
-#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_18_pad_ctrl_PULL_NONE 0
-#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_18_pad_ctrl_PULL_DOWN 1
-#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_18_pad_ctrl_PULL_UP 2
-
-/* AON_PIN_CTRL :: PIN_MUX_PAD_CTRL_1 :: aon_gpio_17_pad_ctrl [07:06] */
-#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_17_pad_ctrl_MASK 0x000000c0
-#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_17_pad_ctrl_SHIFT 6
-#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_17_pad_ctrl_DEFAULT 0x00000001
-#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_17_pad_ctrl_PULL_NONE 0
-#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_17_pad_ctrl_PULL_DOWN 1
-#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_17_pad_ctrl_PULL_UP 2
-
-/* AON_PIN_CTRL :: PIN_MUX_PAD_CTRL_1 :: aon_gpio_16_pad_ctrl [05:04] */
-#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_16_pad_ctrl_MASK 0x00000030
-#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_16_pad_ctrl_SHIFT 4
-#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_16_pad_ctrl_DEFAULT 0x00000001
-#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_16_pad_ctrl_PULL_NONE 0
-#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_16_pad_ctrl_PULL_DOWN 1
-#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_16_pad_ctrl_PULL_UP 2
-
-/* AON_PIN_CTRL :: PIN_MUX_PAD_CTRL_1 :: aon_gpio_15_pad_ctrl [03:02] */
-#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_15_pad_ctrl_MASK 0x0000000c
-#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_15_pad_ctrl_SHIFT 2
-#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_15_pad_ctrl_DEFAULT 0x00000001
-#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_15_pad_ctrl_PULL_NONE 0
-#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_15_pad_ctrl_PULL_DOWN 1
-#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_15_pad_ctrl_PULL_UP 2
-
-/* AON_PIN_CTRL :: PIN_MUX_PAD_CTRL_1 :: aon_gpio_14_pad_ctrl [01:00] */
-#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_14_pad_ctrl_MASK 0x00000003
-#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_14_pad_ctrl_SHIFT 0
-#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_14_pad_ctrl_DEFAULT 0x00000001
-#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_14_pad_ctrl_PULL_NONE 0
-#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_14_pad_ctrl_PULL_DOWN 1
-#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_14_pad_ctrl_PULL_UP 2
-
-/***************************************************************************
- *BYP_CLK_UNSELECT_0 - Bypass clock unselect register 0
- ***************************************************************************/
-/* AON_PIN_CTRL :: BYP_CLK_UNSELECT_0 :: reserved0 [31:01] */
-#define BCHP_AON_PIN_CTRL_BYP_CLK_UNSELECT_0_reserved0_MASK 0xfffffffe
-#define BCHP_AON_PIN_CTRL_BYP_CLK_UNSELECT_0_reserved0_SHIFT 1
-
-/* AON_PIN_CTRL :: BYP_CLK_UNSELECT_0 :: unsel_byp_clk_on_aon_gpio_04 [00:00] */
-#define BCHP_AON_PIN_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_aon_gpio_04_MASK 0x00000001
-#define BCHP_AON_PIN_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_aon_gpio_04_SHIFT 0
-#define BCHP_AON_PIN_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_aon_gpio_04_DEFAULT 0x00000000
-
-#endif /* #ifndef BCHP_AON_PIN_CTRL_H__ */
-
-/* End of File */
diff --git a/include/linux/brcmstb/7439a0/bchp_aon_pm_l2.h b/include/linux/brcmstb/7439a0/bchp_aon_pm_l2.h
deleted file mode 100644
index 8ec678d..0000000
--- a/include/linux/brcmstb/7439a0/bchp_aon_pm_l2.h
+++ /dev/null
@@ -1,1044 +0,0 @@
-/***************************************************************************
- * Copyright (c) 1999-2013, Broadcom Corporation
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
- *
- * Module Description:
- * DO NOT EDIT THIS FILE DIRECTLY
- *
- * This module was generated magically with RDB from a source description
- * file. You must edit the source file for changes to be made to this file.
- *
- *
- * Date: Generated on Tue Apr 16 03:26:49 2013
- * MD5 Checksum d41d8cd98f00b204e9800998ecf8427e
- *
- * Compiled with: RDB Utility combo_header.pl
- * RDB Parser 3.0
- * unknown unknown
- * Perl Interpreter 5.008008
- * Operating System linux
- *
- * Revision History:
- *
- * $brcm_Log: $
- *
- ***************************************************************************/
-
-#ifndef BCHP_AON_PM_L2_H__
-#define BCHP_AON_PM_L2_H__
-
-/***************************************************************************
- *AON_PM_L2 - AON Power Management L2 Interrupt Controller Registers
- ***************************************************************************/
-#define BCHP_AON_PM_L2_CPU_STATUS 0x00410440 /* CPU interrupt Status Register */
-#define BCHP_AON_PM_L2_CPU_SET 0x00410444 /* CPU interrupt Set Register */
-#define BCHP_AON_PM_L2_CPU_CLEAR 0x00410448 /* CPU interrupt Clear Register */
-#define BCHP_AON_PM_L2_CPU_MASK_STATUS 0x0041044c /* CPU interrupt Mask Status Register */
-#define BCHP_AON_PM_L2_CPU_MASK_SET 0x00410450 /* CPU interrupt Mask Set Register */
-#define BCHP_AON_PM_L2_CPU_MASK_CLEAR 0x00410454 /* CPU interrupt Mask Clear Register */
-#define BCHP_AON_PM_L2_PCI_STATUS 0x00410458 /* PCI interrupt Status Register */
-#define BCHP_AON_PM_L2_PCI_SET 0x0041045c /* PCI interrupt Set Register */
-#define BCHP_AON_PM_L2_PCI_CLEAR 0x00410460 /* PCI interrupt Clear Register */
-#define BCHP_AON_PM_L2_PCI_MASK_STATUS 0x00410464 /* PCI interrupt Mask Status Register */
-#define BCHP_AON_PM_L2_PCI_MASK_SET 0x00410468 /* PCI interrupt Mask Set Register */
-#define BCHP_AON_PM_L2_PCI_MASK_CLEAR 0x0041046c /* PCI interrupt Mask Clear Register */
-
-/***************************************************************************
- *CPU_STATUS - CPU interrupt Status Register
- ***************************************************************************/
-/* AON_PM_L2 :: CPU_STATUS :: reserved0 [31:15] */
-#define BCHP_AON_PM_L2_CPU_STATUS_reserved0_MASK 0xffff8000
-#define BCHP_AON_PM_L2_CPU_STATUS_reserved0_SHIFT 15
-
-/* AON_PM_L2 :: CPU_STATUS :: SPARE_WAKEUP_EVENT_0 [14:14] */
-#define BCHP_AON_PM_L2_CPU_STATUS_SPARE_WAKEUP_EVENT_0_MASK 0x00004000
-#define BCHP_AON_PM_L2_CPU_STATUS_SPARE_WAKEUP_EVENT_0_SHIFT 14
-#define BCHP_AON_PM_L2_CPU_STATUS_SPARE_WAKEUP_EVENT_0_DEFAULT 0x00000000
-
-/* AON_PM_L2 :: CPU_STATUS :: FP_RESET [13:13] */
-#define BCHP_AON_PM_L2_CPU_STATUS_FP_RESET_MASK 0x00002000
-#define BCHP_AON_PM_L2_CPU_STATUS_FP_RESET_SHIFT 13
-#define BCHP_AON_PM_L2_CPU_STATUS_FP_RESET_DEFAULT 0x00000000
-
-/* AON_PM_L2 :: CPU_STATUS :: BOUNDARY_SCAN_REQ [12:12] */
-#define BCHP_AON_PM_L2_CPU_STATUS_BOUNDARY_SCAN_REQ_MASK 0x00001000
-#define BCHP_AON_PM_L2_CPU_STATUS_BOUNDARY_SCAN_REQ_SHIFT 12
-#define BCHP_AON_PM_L2_CPU_STATUS_BOUNDARY_SCAN_REQ_DEFAULT 0x00000000
-
-/* AON_PM_L2 :: CPU_STATUS :: USB1 [11:11] */
-#define BCHP_AON_PM_L2_CPU_STATUS_USB1_MASK 0x00000800
-#define BCHP_AON_PM_L2_CPU_STATUS_USB1_SHIFT 11
-#define BCHP_AON_PM_L2_CPU_STATUS_USB1_DEFAULT 0x00000000
-
-/* AON_PM_L2 :: CPU_STATUS :: USB0 [10:10] */
-#define BCHP_AON_PM_L2_CPU_STATUS_USB0_MASK 0x00000400
-#define BCHP_AON_PM_L2_CPU_STATUS_USB0_SHIFT 10
-#define BCHP_AON_PM_L2_CPU_STATUS_USB0_DEFAULT 0x00000000
-
-/* AON_PM_L2 :: CPU_STATUS :: MOCA [09:09] */
-#define BCHP_AON_PM_L2_CPU_STATUS_MOCA_MASK 0x00000200
-#define BCHP_AON_PM_L2_CPU_STATUS_MOCA_SHIFT 9
-#define BCHP_AON_PM_L2_CPU_STATUS_MOCA_DEFAULT 0x00000000
-
-/* AON_PM_L2 :: CPU_STATUS :: XPT_PMU [08:08] */
-#define BCHP_AON_PM_L2_CPU_STATUS_XPT_PMU_MASK 0x00000100
-#define BCHP_AON_PM_L2_CPU_STATUS_XPT_PMU_SHIFT 8
-#define BCHP_AON_PM_L2_CPU_STATUS_XPT_PMU_DEFAULT 0x00000000
-
-/* AON_PM_L2 :: CPU_STATUS :: WOL_GENET1 [07:07] */
-#define BCHP_AON_PM_L2_CPU_STATUS_WOL_GENET1_MASK 0x00000080
-#define BCHP_AON_PM_L2_CPU_STATUS_WOL_GENET1_SHIFT 7
-#define BCHP_AON_PM_L2_CPU_STATUS_WOL_GENET1_DEFAULT 0x00000000
-
-/* AON_PM_L2 :: CPU_STATUS :: WOL_GENET0 [06:06] */
-#define BCHP_AON_PM_L2_CPU_STATUS_WOL_GENET0_MASK 0x00000040
-#define BCHP_AON_PM_L2_CPU_STATUS_WOL_GENET0_SHIFT 6
-#define BCHP_AON_PM_L2_CPU_STATUS_WOL_GENET0_DEFAULT 0x00000000
-
-/* AON_PM_L2 :: CPU_STATUS :: GPIO [05:05] */
-#define BCHP_AON_PM_L2_CPU_STATUS_GPIO_MASK 0x00000020
-#define BCHP_AON_PM_L2_CPU_STATUS_GPIO_SHIFT 5
-#define BCHP_AON_PM_L2_CPU_STATUS_GPIO_DEFAULT 0x00000000
-
-/* AON_PM_L2 :: CPU_STATUS :: NMI_B_INTR [04:04] */
-#define BCHP_AON_PM_L2_CPU_STATUS_NMI_B_INTR_MASK 0x00000010
-#define BCHP_AON_PM_L2_CPU_STATUS_NMI_B_INTR_SHIFT 4
-#define BCHP_AON_PM_L2_CPU_STATUS_NMI_B_INTR_DEFAULT 0x00000000
-
-/* AON_PM_L2 :: CPU_STATUS :: TIMER_INTR [03:03] */
-#define BCHP_AON_PM_L2_CPU_STATUS_TIMER_INTR_MASK 0x00000008
-#define BCHP_AON_PM_L2_CPU_STATUS_TIMER_INTR_SHIFT 3
-#define BCHP_AON_PM_L2_CPU_STATUS_TIMER_INTR_DEFAULT 0x00000000
-
-/* AON_PM_L2 :: CPU_STATUS :: KPD_INTR [02:02] */
-#define BCHP_AON_PM_L2_CPU_STATUS_KPD_INTR_MASK 0x00000004
-#define BCHP_AON_PM_L2_CPU_STATUS_KPD_INTR_SHIFT 2
-#define BCHP_AON_PM_L2_CPU_STATUS_KPD_INTR_DEFAULT 0x00000000
-
-/* AON_PM_L2 :: CPU_STATUS :: IRR_INTR [01:01] */
-#define BCHP_AON_PM_L2_CPU_STATUS_IRR_INTR_MASK 0x00000002
-#define BCHP_AON_PM_L2_CPU_STATUS_IRR_INTR_SHIFT 1
-#define BCHP_AON_PM_L2_CPU_STATUS_IRR_INTR_DEFAULT 0x00000000
-
-/* AON_PM_L2 :: CPU_STATUS :: CEC_INTR [00:00] */
-#define BCHP_AON_PM_L2_CPU_STATUS_CEC_INTR_MASK 0x00000001
-#define BCHP_AON_PM_L2_CPU_STATUS_CEC_INTR_SHIFT 0
-#define BCHP_AON_PM_L2_CPU_STATUS_CEC_INTR_DEFAULT 0x00000000
-
-/***************************************************************************
- *CPU_SET - CPU interrupt Set Register
- ***************************************************************************/
-/* AON_PM_L2 :: CPU_SET :: reserved0 [31:15] */
-#define BCHP_AON_PM_L2_CPU_SET_reserved0_MASK 0xffff8000
-#define BCHP_AON_PM_L2_CPU_SET_reserved0_SHIFT 15
-
-/* AON_PM_L2 :: CPU_SET :: SPARE_WAKEUP_EVENT_0 [14:14] */
-#define BCHP_AON_PM_L2_CPU_SET_SPARE_WAKEUP_EVENT_0_MASK 0x00004000
-#define BCHP_AON_PM_L2_CPU_SET_SPARE_WAKEUP_EVENT_0_SHIFT 14
-#define BCHP_AON_PM_L2_CPU_SET_SPARE_WAKEUP_EVENT_0_DEFAULT 0x00000000
-
-/* AON_PM_L2 :: CPU_SET :: FP_RESET [13:13] */
-#define BCHP_AON_PM_L2_CPU_SET_FP_RESET_MASK 0x00002000
-#define BCHP_AON_PM_L2_CPU_SET_FP_RESET_SHIFT 13
-#define BCHP_AON_PM_L2_CPU_SET_FP_RESET_DEFAULT 0x00000000
-
-/* AON_PM_L2 :: CPU_SET :: BOUNDARY_SCAN_REQ [12:12] */
-#define BCHP_AON_PM_L2_CPU_SET_BOUNDARY_SCAN_REQ_MASK 0x00001000
-#define BCHP_AON_PM_L2_CPU_SET_BOUNDARY_SCAN_REQ_SHIFT 12
-#define BCHP_AON_PM_L2_CPU_SET_BOUNDARY_SCAN_REQ_DEFAULT 0x00000000
-
-/* AON_PM_L2 :: CPU_SET :: USB1 [11:11] */
-#define BCHP_AON_PM_L2_CPU_SET_USB1_MASK 0x00000800
-#define BCHP_AON_PM_L2_CPU_SET_USB1_SHIFT 11
-#define BCHP_AON_PM_L2_CPU_SET_USB1_DEFAULT 0x00000000
-
-/* AON_PM_L2 :: CPU_SET :: USB0 [10:10] */
-#define BCHP_AON_PM_L2_CPU_SET_USB0_MASK 0x00000400
-#define BCHP_AON_PM_L2_CPU_SET_USB0_SHIFT 10
-#define BCHP_AON_PM_L2_CPU_SET_USB0_DEFAULT 0x00000000
-
-/* AON_PM_L2 :: CPU_SET :: MOCA [09:09] */
-#define BCHP_AON_PM_L2_CPU_SET_MOCA_MASK 0x00000200
-#define BCHP_AON_PM_L2_CPU_SET_MOCA_SHIFT 9
-#define BCHP_AON_PM_L2_CPU_SET_MOCA_DEFAULT 0x00000000
-
-/* AON_PM_L2 :: CPU_SET :: XPT_PMU [08:08] */
-#define BCHP_AON_PM_L2_CPU_SET_XPT_PMU_MASK 0x00000100
-#define BCHP_AON_PM_L2_CPU_SET_XPT_PMU_SHIFT 8
-#define BCHP_AON_PM_L2_CPU_SET_XPT_PMU_DEFAULT 0x00000000
-
-/* AON_PM_L2 :: CPU_SET :: WOL_GENET1 [07:07] */
-#define BCHP_AON_PM_L2_CPU_SET_WOL_GENET1_MASK 0x00000080
-#define BCHP_AON_PM_L2_CPU_SET_WOL_GENET1_SHIFT 7
-#define BCHP_AON_PM_L2_CPU_SET_WOL_GENET1_DEFAULT 0x00000000
-
-/* AON_PM_L2 :: CPU_SET :: WOL_GENET0 [06:06] */
-#define BCHP_AON_PM_L2_CPU_SET_WOL_GENET0_MASK 0x00000040
-#define BCHP_AON_PM_L2_CPU_SET_WOL_GENET0_SHIFT 6
-#define BCHP_AON_PM_L2_CPU_SET_WOL_GENET0_DEFAULT 0x00000000
-
-/* AON_PM_L2 :: CPU_SET :: GPIO [05:05] */
-#define BCHP_AON_PM_L2_CPU_SET_GPIO_MASK 0x00000020
-#define BCHP_AON_PM_L2_CPU_SET_GPIO_SHIFT 5
-#define BCHP_AON_PM_L2_CPU_SET_GPIO_DEFAULT 0x00000000
-
-/* AON_PM_L2 :: CPU_SET :: NMI_B_INTR [04:04] */
-#define BCHP_AON_PM_L2_CPU_SET_NMI_B_INTR_MASK 0x00000010
-#define BCHP_AON_PM_L2_CPU_SET_NMI_B_INTR_SHIFT 4
-#define BCHP_AON_PM_L2_CPU_SET_NMI_B_INTR_DEFAULT 0x00000000
-
-/* AON_PM_L2 :: CPU_SET :: TIMER_INTR [03:03] */
-#define BCHP_AON_PM_L2_CPU_SET_TIMER_INTR_MASK 0x00000008
-#define BCHP_AON_PM_L2_CPU_SET_TIMER_INTR_SHIFT 3
-#define BCHP_AON_PM_L2_CPU_SET_TIMER_INTR_DEFAULT 0x00000000
-
-/* AON_PM_L2 :: CPU_SET :: KPD_INTR [02:02] */
-#define BCHP_AON_PM_L2_CPU_SET_KPD_INTR_MASK 0x00000004
-#define BCHP_AON_PM_L2_CPU_SET_KPD_INTR_SHIFT 2
-#define BCHP_AON_PM_L2_CPU_SET_KPD_INTR_DEFAULT 0x00000000
-
-/* AON_PM_L2 :: CPU_SET :: IRR_INTR [01:01] */
-#define BCHP_AON_PM_L2_CPU_SET_IRR_INTR_MASK 0x00000002
-#define BCHP_AON_PM_L2_CPU_SET_IRR_INTR_SHIFT 1
-#define BCHP_AON_PM_L2_CPU_SET_IRR_INTR_DEFAULT 0x00000000
-
-/* AON_PM_L2 :: CPU_SET :: CEC_INTR [00:00] */
-#define BCHP_AON_PM_L2_CPU_SET_CEC_INTR_MASK 0x00000001
-#define BCHP_AON_PM_L2_CPU_SET_CEC_INTR_SHIFT 0
-#define BCHP_AON_PM_L2_CPU_SET_CEC_INTR_DEFAULT 0x00000000
-
-/***************************************************************************
- *CPU_CLEAR - CPU interrupt Clear Register
- ***************************************************************************/
-/* AON_PM_L2 :: CPU_CLEAR :: reserved0 [31:15] */
-#define BCHP_AON_PM_L2_CPU_CLEAR_reserved0_MASK 0xffff8000
-#define BCHP_AON_PM_L2_CPU_CLEAR_reserved0_SHIFT 15
-
-/* AON_PM_L2 :: CPU_CLEAR :: SPARE_WAKEUP_EVENT_0 [14:14] */
-#define BCHP_AON_PM_L2_CPU_CLEAR_SPARE_WAKEUP_EVENT_0_MASK 0x00004000
-#define BCHP_AON_PM_L2_CPU_CLEAR_SPARE_WAKEUP_EVENT_0_SHIFT 14
-#define BCHP_AON_PM_L2_CPU_CLEAR_SPARE_WAKEUP_EVENT_0_DEFAULT 0x00000000
-
-/* AON_PM_L2 :: CPU_CLEAR :: FP_RESET [13:13] */
-#define BCHP_AON_PM_L2_CPU_CLEAR_FP_RESET_MASK 0x00002000
-#define BCHP_AON_PM_L2_CPU_CLEAR_FP_RESET_SHIFT 13
-#define BCHP_AON_PM_L2_CPU_CLEAR_FP_RESET_DEFAULT 0x00000000
-
-/* AON_PM_L2 :: CPU_CLEAR :: BOUNDARY_SCAN_REQ [12:12] */
-#define BCHP_AON_PM_L2_CPU_CLEAR_BOUNDARY_SCAN_REQ_MASK 0x00001000
-#define BCHP_AON_PM_L2_CPU_CLEAR_BOUNDARY_SCAN_REQ_SHIFT 12
-#define BCHP_AON_PM_L2_CPU_CLEAR_BOUNDARY_SCAN_REQ_DEFAULT 0x00000000
-
-/* AON_PM_L2 :: CPU_CLEAR :: USB1 [11:11] */
-#define BCHP_AON_PM_L2_CPU_CLEAR_USB1_MASK 0x00000800
-#define BCHP_AON_PM_L2_CPU_CLEAR_USB1_SHIFT 11
-#define BCHP_AON_PM_L2_CPU_CLEAR_USB1_DEFAULT 0x00000000
-
-/* AON_PM_L2 :: CPU_CLEAR :: USB0 [10:10] */
-#define BCHP_AON_PM_L2_CPU_CLEAR_USB0_MASK 0x00000400
-#define BCHP_AON_PM_L2_CPU_CLEAR_USB0_SHIFT 10
-#define BCHP_AON_PM_L2_CPU_CLEAR_USB0_DEFAULT 0x00000000
-
-/* AON_PM_L2 :: CPU_CLEAR :: MOCA [09:09] */
-#define BCHP_AON_PM_L2_CPU_CLEAR_MOCA_MASK 0x00000200
-#define BCHP_AON_PM_L2_CPU_CLEAR_MOCA_SHIFT 9
-#define BCHP_AON_PM_L2_CPU_CLEAR_MOCA_DEFAULT 0x00000000
-
-/* AON_PM_L2 :: CPU_CLEAR :: XPT_PMU [08:08] */
-#define BCHP_AON_PM_L2_CPU_CLEAR_XPT_PMU_MASK 0x00000100
-#define BCHP_AON_PM_L2_CPU_CLEAR_XPT_PMU_SHIFT 8
-#define BCHP_AON_PM_L2_CPU_CLEAR_XPT_PMU_DEFAULT 0x00000000
-
-/* AON_PM_L2 :: CPU_CLEAR :: WOL_GENET1 [07:07] */
-#define BCHP_AON_PM_L2_CPU_CLEAR_WOL_GENET1_MASK 0x00000080
-#define BCHP_AON_PM_L2_CPU_CLEAR_WOL_GENET1_SHIFT 7
-#define BCHP_AON_PM_L2_CPU_CLEAR_WOL_GENET1_DEFAULT 0x00000000
-
-/* AON_PM_L2 :: CPU_CLEAR :: WOL_GENET0 [06:06] */
-#define BCHP_AON_PM_L2_CPU_CLEAR_WOL_GENET0_MASK 0x00000040
-#define BCHP_AON_PM_L2_CPU_CLEAR_WOL_GENET0_SHIFT 6
-#define BCHP_AON_PM_L2_CPU_CLEAR_WOL_GENET0_DEFAULT 0x00000000
-
-/* AON_PM_L2 :: CPU_CLEAR :: GPIO [05:05] */
-#define BCHP_AON_PM_L2_CPU_CLEAR_GPIO_MASK 0x00000020
-#define BCHP_AON_PM_L2_CPU_CLEAR_GPIO_SHIFT 5
-#define BCHP_AON_PM_L2_CPU_CLEAR_GPIO_DEFAULT 0x00000000
-
-/* AON_PM_L2 :: CPU_CLEAR :: NMI_B_INTR [04:04] */
-#define BCHP_AON_PM_L2_CPU_CLEAR_NMI_B_INTR_MASK 0x00000010
-#define BCHP_AON_PM_L2_CPU_CLEAR_NMI_B_INTR_SHIFT 4
-#define BCHP_AON_PM_L2_CPU_CLEAR_NMI_B_INTR_DEFAULT 0x00000000
-
-/* AON_PM_L2 :: CPU_CLEAR :: TIMER_INTR [03:03] */
-#define BCHP_AON_PM_L2_CPU_CLEAR_TIMER_INTR_MASK 0x00000008
-#define BCHP_AON_PM_L2_CPU_CLEAR_TIMER_INTR_SHIFT 3
-#define BCHP_AON_PM_L2_CPU_CLEAR_TIMER_INTR_DEFAULT 0x00000000
-
-/* AON_PM_L2 :: CPU_CLEAR :: KPD_INTR [02:02] */
-#define BCHP_AON_PM_L2_CPU_CLEAR_KPD_INTR_MASK 0x00000004
-#define BCHP_AON_PM_L2_CPU_CLEAR_KPD_INTR_SHIFT 2
-#define BCHP_AON_PM_L2_CPU_CLEAR_KPD_INTR_DEFAULT 0x00000000
-
-/* AON_PM_L2 :: CPU_CLEAR :: IRR_INTR [01:01] */
-#define BCHP_AON_PM_L2_CPU_CLEAR_IRR_INTR_MASK 0x00000002
-#define BCHP_AON_PM_L2_CPU_CLEAR_IRR_INTR_SHIFT 1
-#define BCHP_AON_PM_L2_CPU_CLEAR_IRR_INTR_DEFAULT 0x00000000
-
-/* AON_PM_L2 :: CPU_CLEAR :: CEC_INTR [00:00] */
-#define BCHP_AON_PM_L2_CPU_CLEAR_CEC_INTR_MASK 0x00000001
-#define BCHP_AON_PM_L2_CPU_CLEAR_CEC_INTR_SHIFT 0
-#define BCHP_AON_PM_L2_CPU_CLEAR_CEC_INTR_DEFAULT 0x00000000
-
-/***************************************************************************
- *CPU_MASK_STATUS - CPU interrupt Mask Status Register
- ***************************************************************************/
-/* AON_PM_L2 :: CPU_MASK_STATUS :: reserved0 [31:15] */
-#define BCHP_AON_PM_L2_CPU_MASK_STATUS_reserved0_MASK 0xffff8000
-#define BCHP_AON_PM_L2_CPU_MASK_STATUS_reserved0_SHIFT 15
-
-/* AON_PM_L2 :: CPU_MASK_STATUS :: SPARE_WAKEUP_EVENT_0 [14:14] */
-#define BCHP_AON_PM_L2_CPU_MASK_STATUS_SPARE_WAKEUP_EVENT_0_MASK 0x00004000
-#define BCHP_AON_PM_L2_CPU_MASK_STATUS_SPARE_WAKEUP_EVENT_0_SHIFT 14
-#define BCHP_AON_PM_L2_CPU_MASK_STATUS_SPARE_WAKEUP_EVENT_0_DEFAULT 0x00000001
-
-/* AON_PM_L2 :: CPU_MASK_STATUS :: FP_RESET [13:13] */
-#define BCHP_AON_PM_L2_CPU_MASK_STATUS_FP_RESET_MASK 0x00002000
-#define BCHP_AON_PM_L2_CPU_MASK_STATUS_FP_RESET_SHIFT 13
-#define BCHP_AON_PM_L2_CPU_MASK_STATUS_FP_RESET_DEFAULT 0x00000001
-
-/* AON_PM_L2 :: CPU_MASK_STATUS :: BOUNDARY_SCAN_REQ [12:12] */
-#define BCHP_AON_PM_L2_CPU_MASK_STATUS_BOUNDARY_SCAN_REQ_MASK 0x00001000
-#define BCHP_AON_PM_L2_CPU_MASK_STATUS_BOUNDARY_SCAN_REQ_SHIFT 12
-#define BCHP_AON_PM_L2_CPU_MASK_STATUS_BOUNDARY_SCAN_REQ_DEFAULT 0x00000001
-
-/* AON_PM_L2 :: CPU_MASK_STATUS :: USB1 [11:11] */
-#define BCHP_AON_PM_L2_CPU_MASK_STATUS_USB1_MASK 0x00000800
-#define BCHP_AON_PM_L2_CPU_MASK_STATUS_USB1_SHIFT 11
-#define BCHP_AON_PM_L2_CPU_MASK_STATUS_USB1_DEFAULT 0x00000001
-
-/* AON_PM_L2 :: CPU_MASK_STATUS :: USB0 [10:10] */
-#define BCHP_AON_PM_L2_CPU_MASK_STATUS_USB0_MASK 0x00000400
-#define BCHP_AON_PM_L2_CPU_MASK_STATUS_USB0_SHIFT 10
-#define BCHP_AON_PM_L2_CPU_MASK_STATUS_USB0_DEFAULT 0x00000001
-
-/* AON_PM_L2 :: CPU_MASK_STATUS :: MOCA [09:09] */
-#define BCHP_AON_PM_L2_CPU_MASK_STATUS_MOCA_MASK 0x00000200
-#define BCHP_AON_PM_L2_CPU_MASK_STATUS_MOCA_SHIFT 9
-#define BCHP_AON_PM_L2_CPU_MASK_STATUS_MOCA_DEFAULT 0x00000001
-
-/* AON_PM_L2 :: CPU_MASK_STATUS :: XPT_PMU [08:08] */
-#define BCHP_AON_PM_L2_CPU_MASK_STATUS_XPT_PMU_MASK 0x00000100
-#define BCHP_AON_PM_L2_CPU_MASK_STATUS_XPT_PMU_SHIFT 8
-#define BCHP_AON_PM_L2_CPU_MASK_STATUS_XPT_PMU_DEFAULT 0x00000001
-
-/* AON_PM_L2 :: CPU_MASK_STATUS :: WOL_GENET1 [07:07] */
-#define BCHP_AON_PM_L2_CPU_MASK_STATUS_WOL_GENET1_MASK 0x00000080
-#define BCHP_AON_PM_L2_CPU_MASK_STATUS_WOL_GENET1_SHIFT 7
-#define BCHP_AON_PM_L2_CPU_MASK_STATUS_WOL_GENET1_DEFAULT 0x00000001
-
-/* AON_PM_L2 :: CPU_MASK_STATUS :: WOL_GENET0 [06:06] */
-#define BCHP_AON_PM_L2_CPU_MASK_STATUS_WOL_GENET0_MASK 0x00000040
-#define BCHP_AON_PM_L2_CPU_MASK_STATUS_WOL_GENET0_SHIFT 6
-#define BCHP_AON_PM_L2_CPU_MASK_STATUS_WOL_GENET0_DEFAULT 0x00000001
-
-/* AON_PM_L2 :: CPU_MASK_STATUS :: GPIO [05:05] */
-#define BCHP_AON_PM_L2_CPU_MASK_STATUS_GPIO_MASK 0x00000020
-#define BCHP_AON_PM_L2_CPU_MASK_STATUS_GPIO_SHIFT 5
-#define BCHP_AON_PM_L2_CPU_MASK_STATUS_GPIO_DEFAULT 0x00000001
-
-/* AON_PM_L2 :: CPU_MASK_STATUS :: NMI_B_INTR [04:04] */
-#define BCHP_AON_PM_L2_CPU_MASK_STATUS_NMI_B_INTR_MASK 0x00000010
-#define BCHP_AON_PM_L2_CPU_MASK_STATUS_NMI_B_INTR_SHIFT 4
-#define BCHP_AON_PM_L2_CPU_MASK_STATUS_NMI_B_INTR_DEFAULT 0x00000001
-
-/* AON_PM_L2 :: CPU_MASK_STATUS :: TIMER_INTR [03:03] */
-#define BCHP_AON_PM_L2_CPU_MASK_STATUS_TIMER_INTR_MASK 0x00000008
-#define BCHP_AON_PM_L2_CPU_MASK_STATUS_TIMER_INTR_SHIFT 3
-#define BCHP_AON_PM_L2_CPU_MASK_STATUS_TIMER_INTR_DEFAULT 0x00000001
-
-/* AON_PM_L2 :: CPU_MASK_STATUS :: KPD_INTR [02:02] */
-#define BCHP_AON_PM_L2_CPU_MASK_STATUS_KPD_INTR_MASK 0x00000004
-#define BCHP_AON_PM_L2_CPU_MASK_STATUS_KPD_INTR_SHIFT 2
-#define BCHP_AON_PM_L2_CPU_MASK_STATUS_KPD_INTR_DEFAULT 0x00000001
-
-/* AON_PM_L2 :: CPU_MASK_STATUS :: IRR_INTR [01:01] */
-#define BCHP_AON_PM_L2_CPU_MASK_STATUS_IRR_INTR_MASK 0x00000002
-#define BCHP_AON_PM_L2_CPU_MASK_STATUS_IRR_INTR_SHIFT 1
-#define BCHP_AON_PM_L2_CPU_MASK_STATUS_IRR_INTR_DEFAULT 0x00000001
-
-/* AON_PM_L2 :: CPU_MASK_STATUS :: CEC_INTR [00:00] */
-#define BCHP_AON_PM_L2_CPU_MASK_STATUS_CEC_INTR_MASK 0x00000001
-#define BCHP_AON_PM_L2_CPU_MASK_STATUS_CEC_INTR_SHIFT 0
-#define BCHP_AON_PM_L2_CPU_MASK_STATUS_CEC_INTR_DEFAULT 0x00000001
-
-/***************************************************************************
- *CPU_MASK_SET - CPU interrupt Mask Set Register
- ***************************************************************************/
-/* AON_PM_L2 :: CPU_MASK_SET :: reserved0 [31:15] */
-#define BCHP_AON_PM_L2_CPU_MASK_SET_reserved0_MASK 0xffff8000
-#define BCHP_AON_PM_L2_CPU_MASK_SET_reserved0_SHIFT 15
-
-/* AON_PM_L2 :: CPU_MASK_SET :: SPARE_WAKEUP_EVENT_0 [14:14] */
-#define BCHP_AON_PM_L2_CPU_MASK_SET_SPARE_WAKEUP_EVENT_0_MASK 0x00004000
-#define BCHP_AON_PM_L2_CPU_MASK_SET_SPARE_WAKEUP_EVENT_0_SHIFT 14
-#define BCHP_AON_PM_L2_CPU_MASK_SET_SPARE_WAKEUP_EVENT_0_DEFAULT 0x00000001
-
-/* AON_PM_L2 :: CPU_MASK_SET :: FP_RESET [13:13] */
-#define BCHP_AON_PM_L2_CPU_MASK_SET_FP_RESET_MASK 0x00002000
-#define BCHP_AON_PM_L2_CPU_MASK_SET_FP_RESET_SHIFT 13
-#define BCHP_AON_PM_L2_CPU_MASK_SET_FP_RESET_DEFAULT 0x00000001
-
-/* AON_PM_L2 :: CPU_MASK_SET :: BOUNDARY_SCAN_REQ [12:12] */
-#define BCHP_AON_PM_L2_CPU_MASK_SET_BOUNDARY_SCAN_REQ_MASK 0x00001000
-#define BCHP_AON_PM_L2_CPU_MASK_SET_BOUNDARY_SCAN_REQ_SHIFT 12
-#define BCHP_AON_PM_L2_CPU_MASK_SET_BOUNDARY_SCAN_REQ_DEFAULT 0x00000001
-
-/* AON_PM_L2 :: CPU_MASK_SET :: USB1 [11:11] */
-#define BCHP_AON_PM_L2_CPU_MASK_SET_USB1_MASK 0x00000800
-#define BCHP_AON_PM_L2_CPU_MASK_SET_USB1_SHIFT 11
-#define BCHP_AON_PM_L2_CPU_MASK_SET_USB1_DEFAULT 0x00000001
-
-/* AON_PM_L2 :: CPU_MASK_SET :: USB0 [10:10] */
-#define BCHP_AON_PM_L2_CPU_MASK_SET_USB0_MASK 0x00000400
-#define BCHP_AON_PM_L2_CPU_MASK_SET_USB0_SHIFT 10
-#define BCHP_AON_PM_L2_CPU_MASK_SET_USB0_DEFAULT 0x00000001
-
-/* AON_PM_L2 :: CPU_MASK_SET :: MOCA [09:09] */
-#define BCHP_AON_PM_L2_CPU_MASK_SET_MOCA_MASK 0x00000200
-#define BCHP_AON_PM_L2_CPU_MASK_SET_MOCA_SHIFT 9
-#define BCHP_AON_PM_L2_CPU_MASK_SET_MOCA_DEFAULT 0x00000001
-
-/* AON_PM_L2 :: CPU_MASK_SET :: XPT_PMU [08:08] */
-#define BCHP_AON_PM_L2_CPU_MASK_SET_XPT_PMU_MASK 0x00000100
-#define BCHP_AON_PM_L2_CPU_MASK_SET_XPT_PMU_SHIFT 8
-#define BCHP_AON_PM_L2_CPU_MASK_SET_XPT_PMU_DEFAULT 0x00000001
-
-/* AON_PM_L2 :: CPU_MASK_SET :: WOL_GENET1 [07:07] */
-#define BCHP_AON_PM_L2_CPU_MASK_SET_WOL_GENET1_MASK 0x00000080
-#define BCHP_AON_PM_L2_CPU_MASK_SET_WOL_GENET1_SHIFT 7
-#define BCHP_AON_PM_L2_CPU_MASK_SET_WOL_GENET1_DEFAULT 0x00000001
-
-/* AON_PM_L2 :: CPU_MASK_SET :: WOL_GENET0 [06:06] */
-#define BCHP_AON_PM_L2_CPU_MASK_SET_WOL_GENET0_MASK 0x00000040
-#define BCHP_AON_PM_L2_CPU_MASK_SET_WOL_GENET0_SHIFT 6
-#define BCHP_AON_PM_L2_CPU_MASK_SET_WOL_GENET0_DEFAULT 0x00000001
-
-/* AON_PM_L2 :: CPU_MASK_SET :: GPIO [05:05] */
-#define BCHP_AON_PM_L2_CPU_MASK_SET_GPIO_MASK 0x00000020
-#define BCHP_AON_PM_L2_CPU_MASK_SET_GPIO_SHIFT 5
-#define BCHP_AON_PM_L2_CPU_MASK_SET_GPIO_DEFAULT 0x00000001
-
-/* AON_PM_L2 :: CPU_MASK_SET :: NMI_B_INTR [04:04] */
-#define BCHP_AON_PM_L2_CPU_MASK_SET_NMI_B_INTR_MASK 0x00000010
-#define BCHP_AON_PM_L2_CPU_MASK_SET_NMI_B_INTR_SHIFT 4
-#define BCHP_AON_PM_L2_CPU_MASK_SET_NMI_B_INTR_DEFAULT 0x00000001
-
-/* AON_PM_L2 :: CPU_MASK_SET :: TIMER_INTR [03:03] */
-#define BCHP_AON_PM_L2_CPU_MASK_SET_TIMER_INTR_MASK 0x00000008
-#define BCHP_AON_PM_L2_CPU_MASK_SET_TIMER_INTR_SHIFT 3
-#define BCHP_AON_PM_L2_CPU_MASK_SET_TIMER_INTR_DEFAULT 0x00000001
-
-/* AON_PM_L2 :: CPU_MASK_SET :: KPD_INTR [02:02] */
-#define BCHP_AON_PM_L2_CPU_MASK_SET_KPD_INTR_MASK 0x00000004
-#define BCHP_AON_PM_L2_CPU_MASK_SET_KPD_INTR_SHIFT 2
-#define BCHP_AON_PM_L2_CPU_MASK_SET_KPD_INTR_DEFAULT 0x00000001
-
-/* AON_PM_L2 :: CPU_MASK_SET :: IRR_INTR [01:01] */
-#define BCHP_AON_PM_L2_CPU_MASK_SET_IRR_INTR_MASK 0x00000002
-#define BCHP_AON_PM_L2_CPU_MASK_SET_IRR_INTR_SHIFT 1
-#define BCHP_AON_PM_L2_CPU_MASK_SET_IRR_INTR_DEFAULT 0x00000001
-
-/* AON_PM_L2 :: CPU_MASK_SET :: CEC_INTR [00:00] */
-#define BCHP_AON_PM_L2_CPU_MASK_SET_CEC_INTR_MASK 0x00000001
-#define BCHP_AON_PM_L2_CPU_MASK_SET_CEC_INTR_SHIFT 0
-#define BCHP_AON_PM_L2_CPU_MASK_SET_CEC_INTR_DEFAULT 0x00000001
-
-/***************************************************************************
- *CPU_MASK_CLEAR - CPU interrupt Mask Clear Register
- ***************************************************************************/
-/* AON_PM_L2 :: CPU_MASK_CLEAR :: reserved0 [31:15] */
-#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_reserved0_MASK 0xffff8000
-#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_reserved0_SHIFT 15
-
-/* AON_PM_L2 :: CPU_MASK_CLEAR :: SPARE_WAKEUP_EVENT_0 [14:14] */
-#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_SPARE_WAKEUP_EVENT_0_MASK 0x00004000
-#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_SPARE_WAKEUP_EVENT_0_SHIFT 14
-#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_SPARE_WAKEUP_EVENT_0_DEFAULT 0x00000001
-
-/* AON_PM_L2 :: CPU_MASK_CLEAR :: FP_RESET [13:13] */
-#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_FP_RESET_MASK 0x00002000
-#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_FP_RESET_SHIFT 13
-#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_FP_RESET_DEFAULT 0x00000001
-
-/* AON_PM_L2 :: CPU_MASK_CLEAR :: BOUNDARY_SCAN_REQ [12:12] */
-#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_BOUNDARY_SCAN_REQ_MASK 0x00001000
-#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_BOUNDARY_SCAN_REQ_SHIFT 12
-#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_BOUNDARY_SCAN_REQ_DEFAULT 0x00000001
-
-/* AON_PM_L2 :: CPU_MASK_CLEAR :: USB1 [11:11] */
-#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_USB1_MASK 0x00000800
-#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_USB1_SHIFT 11
-#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_USB1_DEFAULT 0x00000001
-
-/* AON_PM_L2 :: CPU_MASK_CLEAR :: USB0 [10:10] */
-#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_USB0_MASK 0x00000400
-#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_USB0_SHIFT 10
-#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_USB0_DEFAULT 0x00000001
-
-/* AON_PM_L2 :: CPU_MASK_CLEAR :: MOCA [09:09] */
-#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_MOCA_MASK 0x00000200
-#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_MOCA_SHIFT 9
-#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_MOCA_DEFAULT 0x00000001
-
-/* AON_PM_L2 :: CPU_MASK_CLEAR :: XPT_PMU [08:08] */
-#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_XPT_PMU_MASK 0x00000100
-#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_XPT_PMU_SHIFT 8
-#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_XPT_PMU_DEFAULT 0x00000001
-
-/* AON_PM_L2 :: CPU_MASK_CLEAR :: WOL_GENET1 [07:07] */
-#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_WOL_GENET1_MASK 0x00000080
-#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_WOL_GENET1_SHIFT 7
-#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_WOL_GENET1_DEFAULT 0x00000001
-
-/* AON_PM_L2 :: CPU_MASK_CLEAR :: WOL_GENET0 [06:06] */
-#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_WOL_GENET0_MASK 0x00000040
-#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_WOL_GENET0_SHIFT 6
-#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_WOL_GENET0_DEFAULT 0x00000001
-
-/* AON_PM_L2 :: CPU_MASK_CLEAR :: GPIO [05:05] */
-#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_GPIO_MASK 0x00000020
-#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_GPIO_SHIFT 5
-#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_GPIO_DEFAULT 0x00000001
-
-/* AON_PM_L2 :: CPU_MASK_CLEAR :: NMI_B_INTR [04:04] */
-#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_NMI_B_INTR_MASK 0x00000010
-#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_NMI_B_INTR_SHIFT 4
-#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_NMI_B_INTR_DEFAULT 0x00000001
-
-/* AON_PM_L2 :: CPU_MASK_CLEAR :: TIMER_INTR [03:03] */
-#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_TIMER_INTR_MASK 0x00000008
-#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_TIMER_INTR_SHIFT 3
-#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_TIMER_INTR_DEFAULT 0x00000001
-
-/* AON_PM_L2 :: CPU_MASK_CLEAR :: KPD_INTR [02:02] */
-#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_KPD_INTR_MASK 0x00000004
-#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_KPD_INTR_SHIFT 2
-#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_KPD_INTR_DEFAULT 0x00000001
-
-/* AON_PM_L2 :: CPU_MASK_CLEAR :: IRR_INTR [01:01] */
-#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_IRR_INTR_MASK 0x00000002
-#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_IRR_INTR_SHIFT 1
-#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_IRR_INTR_DEFAULT 0x00000001
-
-/* AON_PM_L2 :: CPU_MASK_CLEAR :: CEC_INTR [00:00] */
-#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_CEC_INTR_MASK 0x00000001
-#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_CEC_INTR_SHIFT 0
-#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_CEC_INTR_DEFAULT 0x00000001
-
-/***************************************************************************
- *PCI_STATUS - PCI interrupt Status Register
- ***************************************************************************/
-/* AON_PM_L2 :: PCI_STATUS :: reserved0 [31:15] */
-#define BCHP_AON_PM_L2_PCI_STATUS_reserved0_MASK 0xffff8000
-#define BCHP_AON_PM_L2_PCI_STATUS_reserved0_SHIFT 15
-
-/* AON_PM_L2 :: PCI_STATUS :: SPARE_WAKEUP_EVENT_0 [14:14] */
-#define BCHP_AON_PM_L2_PCI_STATUS_SPARE_WAKEUP_EVENT_0_MASK 0x00004000
-#define BCHP_AON_PM_L2_PCI_STATUS_SPARE_WAKEUP_EVENT_0_SHIFT 14
-#define BCHP_AON_PM_L2_PCI_STATUS_SPARE_WAKEUP_EVENT_0_DEFAULT 0x00000000
-
-/* AON_PM_L2 :: PCI_STATUS :: FP_RESET [13:13] */
-#define BCHP_AON_PM_L2_PCI_STATUS_FP_RESET_MASK 0x00002000
-#define BCHP_AON_PM_L2_PCI_STATUS_FP_RESET_SHIFT 13
-#define BCHP_AON_PM_L2_PCI_STATUS_FP_RESET_DEFAULT 0x00000000
-
-/* AON_PM_L2 :: PCI_STATUS :: BOUNDARY_SCAN_REQ [12:12] */
-#define BCHP_AON_PM_L2_PCI_STATUS_BOUNDARY_SCAN_REQ_MASK 0x00001000
-#define BCHP_AON_PM_L2_PCI_STATUS_BOUNDARY_SCAN_REQ_SHIFT 12
-#define BCHP_AON_PM_L2_PCI_STATUS_BOUNDARY_SCAN_REQ_DEFAULT 0x00000000
-
-/* AON_PM_L2 :: PCI_STATUS :: USB1 [11:11] */
-#define BCHP_AON_PM_L2_PCI_STATUS_USB1_MASK 0x00000800
-#define BCHP_AON_PM_L2_PCI_STATUS_USB1_SHIFT 11
-#define BCHP_AON_PM_L2_PCI_STATUS_USB1_DEFAULT 0x00000000
-
-/* AON_PM_L2 :: PCI_STATUS :: USB0 [10:10] */
-#define BCHP_AON_PM_L2_PCI_STATUS_USB0_MASK 0x00000400
-#define BCHP_AON_PM_L2_PCI_STATUS_USB0_SHIFT 10
-#define BCHP_AON_PM_L2_PCI_STATUS_USB0_DEFAULT 0x00000000
-
-/* AON_PM_L2 :: PCI_STATUS :: MOCA [09:09] */
-#define BCHP_AON_PM_L2_PCI_STATUS_MOCA_MASK 0x00000200
-#define BCHP_AON_PM_L2_PCI_STATUS_MOCA_SHIFT 9
-#define BCHP_AON_PM_L2_PCI_STATUS_MOCA_DEFAULT 0x00000000
-
-/* AON_PM_L2 :: PCI_STATUS :: XPT_PMU [08:08] */
-#define BCHP_AON_PM_L2_PCI_STATUS_XPT_PMU_MASK 0x00000100
-#define BCHP_AON_PM_L2_PCI_STATUS_XPT_PMU_SHIFT 8
-#define BCHP_AON_PM_L2_PCI_STATUS_XPT_PMU_DEFAULT 0x00000000
-
-/* AON_PM_L2 :: PCI_STATUS :: WOL_GENET1 [07:07] */
-#define BCHP_AON_PM_L2_PCI_STATUS_WOL_GENET1_MASK 0x00000080
-#define BCHP_AON_PM_L2_PCI_STATUS_WOL_GENET1_SHIFT 7
-#define BCHP_AON_PM_L2_PCI_STATUS_WOL_GENET1_DEFAULT 0x00000000
-
-/* AON_PM_L2 :: PCI_STATUS :: WOL_GENET0 [06:06] */
-#define BCHP_AON_PM_L2_PCI_STATUS_WOL_GENET0_MASK 0x00000040
-#define BCHP_AON_PM_L2_PCI_STATUS_WOL_GENET0_SHIFT 6
-#define BCHP_AON_PM_L2_PCI_STATUS_WOL_GENET0_DEFAULT 0x00000000
-
-/* AON_PM_L2 :: PCI_STATUS :: GPIO [05:05] */
-#define BCHP_AON_PM_L2_PCI_STATUS_GPIO_MASK 0x00000020
-#define BCHP_AON_PM_L2_PCI_STATUS_GPIO_SHIFT 5
-#define BCHP_AON_PM_L2_PCI_STATUS_GPIO_DEFAULT 0x00000000
-
-/* AON_PM_L2 :: PCI_STATUS :: NMI_B_INTR [04:04] */
-#define BCHP_AON_PM_L2_PCI_STATUS_NMI_B_INTR_MASK 0x00000010
-#define BCHP_AON_PM_L2_PCI_STATUS_NMI_B_INTR_SHIFT 4
-#define BCHP_AON_PM_L2_PCI_STATUS_NMI_B_INTR_DEFAULT 0x00000000
-
-/* AON_PM_L2 :: PCI_STATUS :: TIMER_INTR [03:03] */
-#define BCHP_AON_PM_L2_PCI_STATUS_TIMER_INTR_MASK 0x00000008
-#define BCHP_AON_PM_L2_PCI_STATUS_TIMER_INTR_SHIFT 3
-#define BCHP_AON_PM_L2_PCI_STATUS_TIMER_INTR_DEFAULT 0x00000000
-
-/* AON_PM_L2 :: PCI_STATUS :: KPD_INTR [02:02] */
-#define BCHP_AON_PM_L2_PCI_STATUS_KPD_INTR_MASK 0x00000004
-#define BCHP_AON_PM_L2_PCI_STATUS_KPD_INTR_SHIFT 2
-#define BCHP_AON_PM_L2_PCI_STATUS_KPD_INTR_DEFAULT 0x00000000
-
-/* AON_PM_L2 :: PCI_STATUS :: IRR_INTR [01:01] */
-#define BCHP_AON_PM_L2_PCI_STATUS_IRR_INTR_MASK 0x00000002
-#define BCHP_AON_PM_L2_PCI_STATUS_IRR_INTR_SHIFT 1
-#define BCHP_AON_PM_L2_PCI_STATUS_IRR_INTR_DEFAULT 0x00000000
-
-/* AON_PM_L2 :: PCI_STATUS :: CEC_INTR [00:00] */
-#define BCHP_AON_PM_L2_PCI_STATUS_CEC_INTR_MASK 0x00000001
-#define BCHP_AON_PM_L2_PCI_STATUS_CEC_INTR_SHIFT 0
-#define BCHP_AON_PM_L2_PCI_STATUS_CEC_INTR_DEFAULT 0x00000000
-
-/***************************************************************************
- *PCI_SET - PCI interrupt Set Register
- ***************************************************************************/
-/* AON_PM_L2 :: PCI_SET :: reserved0 [31:15] */
-#define BCHP_AON_PM_L2_PCI_SET_reserved0_MASK 0xffff8000
-#define BCHP_AON_PM_L2_PCI_SET_reserved0_SHIFT 15
-
-/* AON_PM_L2 :: PCI_SET :: SPARE_WAKEUP_EVENT_0 [14:14] */
-#define BCHP_AON_PM_L2_PCI_SET_SPARE_WAKEUP_EVENT_0_MASK 0x00004000
-#define BCHP_AON_PM_L2_PCI_SET_SPARE_WAKEUP_EVENT_0_SHIFT 14
-#define BCHP_AON_PM_L2_PCI_SET_SPARE_WAKEUP_EVENT_0_DEFAULT 0x00000000
-
-/* AON_PM_L2 :: PCI_SET :: FP_RESET [13:13] */
-#define BCHP_AON_PM_L2_PCI_SET_FP_RESET_MASK 0x00002000
-#define BCHP_AON_PM_L2_PCI_SET_FP_RESET_SHIFT 13
-#define BCHP_AON_PM_L2_PCI_SET_FP_RESET_DEFAULT 0x00000000
-
-/* AON_PM_L2 :: PCI_SET :: BOUNDARY_SCAN_REQ [12:12] */
-#define BCHP_AON_PM_L2_PCI_SET_BOUNDARY_SCAN_REQ_MASK 0x00001000
-#define BCHP_AON_PM_L2_PCI_SET_BOUNDARY_SCAN_REQ_SHIFT 12
-#define BCHP_AON_PM_L2_PCI_SET_BOUNDARY_SCAN_REQ_DEFAULT 0x00000000
-
-/* AON_PM_L2 :: PCI_SET :: USB1 [11:11] */
-#define BCHP_AON_PM_L2_PCI_SET_USB1_MASK 0x00000800
-#define BCHP_AON_PM_L2_PCI_SET_USB1_SHIFT 11
-#define BCHP_AON_PM_L2_PCI_SET_USB1_DEFAULT 0x00000000
-
-/* AON_PM_L2 :: PCI_SET :: USB0 [10:10] */
-#define BCHP_AON_PM_L2_PCI_SET_USB0_MASK 0x00000400
-#define BCHP_AON_PM_L2_PCI_SET_USB0_SHIFT 10
-#define BCHP_AON_PM_L2_PCI_SET_USB0_DEFAULT 0x00000000
-
-/* AON_PM_L2 :: PCI_SET :: MOCA [09:09] */
-#define BCHP_AON_PM_L2_PCI_SET_MOCA_MASK 0x00000200
-#define BCHP_AON_PM_L2_PCI_SET_MOCA_SHIFT 9
-#define BCHP_AON_PM_L2_PCI_SET_MOCA_DEFAULT 0x00000000
-
-/* AON_PM_L2 :: PCI_SET :: XPT_PMU [08:08] */
-#define BCHP_AON_PM_L2_PCI_SET_XPT_PMU_MASK 0x00000100
-#define BCHP_AON_PM_L2_PCI_SET_XPT_PMU_SHIFT 8
-#define BCHP_AON_PM_L2_PCI_SET_XPT_PMU_DEFAULT 0x00000000
-
-/* AON_PM_L2 :: PCI_SET :: WOL_GENET1 [07:07] */
-#define BCHP_AON_PM_L2_PCI_SET_WOL_GENET1_MASK 0x00000080
-#define BCHP_AON_PM_L2_PCI_SET_WOL_GENET1_SHIFT 7
-#define BCHP_AON_PM_L2_PCI_SET_WOL_GENET1_DEFAULT 0x00000000
-
-/* AON_PM_L2 :: PCI_SET :: WOL_GENET0 [06:06] */
-#define BCHP_AON_PM_L2_PCI_SET_WOL_GENET0_MASK 0x00000040
-#define BCHP_AON_PM_L2_PCI_SET_WOL_GENET0_SHIFT 6
-#define BCHP_AON_PM_L2_PCI_SET_WOL_GENET0_DEFAULT 0x00000000
-
-/* AON_PM_L2 :: PCI_SET :: GPIO [05:05] */
-#define BCHP_AON_PM_L2_PCI_SET_GPIO_MASK 0x00000020
-#define BCHP_AON_PM_L2_PCI_SET_GPIO_SHIFT 5
-#define BCHP_AON_PM_L2_PCI_SET_GPIO_DEFAULT 0x00000000
-
-/* AON_PM_L2 :: PCI_SET :: NMI_B_INTR [04:04] */
-#define BCHP_AON_PM_L2_PCI_SET_NMI_B_INTR_MASK 0x00000010
-#define BCHP_AON_PM_L2_PCI_SET_NMI_B_INTR_SHIFT 4
-#define BCHP_AON_PM_L2_PCI_SET_NMI_B_INTR_DEFAULT 0x00000000
-
-/* AON_PM_L2 :: PCI_SET :: TIMER_INTR [03:03] */
-#define BCHP_AON_PM_L2_PCI_SET_TIMER_INTR_MASK 0x00000008
-#define BCHP_AON_PM_L2_PCI_SET_TIMER_INTR_SHIFT 3
-#define BCHP_AON_PM_L2_PCI_SET_TIMER_INTR_DEFAULT 0x00000000
-
-/* AON_PM_L2 :: PCI_SET :: KPD_INTR [02:02] */
-#define BCHP_AON_PM_L2_PCI_SET_KPD_INTR_MASK 0x00000004
-#define BCHP_AON_PM_L2_PCI_SET_KPD_INTR_SHIFT 2
-#define BCHP_AON_PM_L2_PCI_SET_KPD_INTR_DEFAULT 0x00000000
-
-/* AON_PM_L2 :: PCI_SET :: IRR_INTR [01:01] */
-#define BCHP_AON_PM_L2_PCI_SET_IRR_INTR_MASK 0x00000002
-#define BCHP_AON_PM_L2_PCI_SET_IRR_INTR_SHIFT 1
-#define BCHP_AON_PM_L2_PCI_SET_IRR_INTR_DEFAULT 0x00000000
-
-/* AON_PM_L2 :: PCI_SET :: CEC_INTR [00:00] */
-#define BCHP_AON_PM_L2_PCI_SET_CEC_INTR_MASK 0x00000001
-#define BCHP_AON_PM_L2_PCI_SET_CEC_INTR_SHIFT 0
-#define BCHP_AON_PM_L2_PCI_SET_CEC_INTR_DEFAULT 0x00000000
-
-/***************************************************************************
- *PCI_CLEAR - PCI interrupt Clear Register
- ***************************************************************************/
-/* AON_PM_L2 :: PCI_CLEAR :: reserved0 [31:15] */
-#define BCHP_AON_PM_L2_PCI_CLEAR_reserved0_MASK 0xffff8000
-#define BCHP_AON_PM_L2_PCI_CLEAR_reserved0_SHIFT 15
-
-/* AON_PM_L2 :: PCI_CLEAR :: SPARE_WAKEUP_EVENT_0 [14:14] */
-#define BCHP_AON_PM_L2_PCI_CLEAR_SPARE_WAKEUP_EVENT_0_MASK 0x00004000
-#define BCHP_AON_PM_L2_PCI_CLEAR_SPARE_WAKEUP_EVENT_0_SHIFT 14
-#define BCHP_AON_PM_L2_PCI_CLEAR_SPARE_WAKEUP_EVENT_0_DEFAULT 0x00000000
-
-/* AON_PM_L2 :: PCI_CLEAR :: FP_RESET [13:13] */
-#define BCHP_AON_PM_L2_PCI_CLEAR_FP_RESET_MASK 0x00002000
-#define BCHP_AON_PM_L2_PCI_CLEAR_FP_RESET_SHIFT 13
-#define BCHP_AON_PM_L2_PCI_CLEAR_FP_RESET_DEFAULT 0x00000000
-
-/* AON_PM_L2 :: PCI_CLEAR :: BOUNDARY_SCAN_REQ [12:12] */
-#define BCHP_AON_PM_L2_PCI_CLEAR_BOUNDARY_SCAN_REQ_MASK 0x00001000
-#define BCHP_AON_PM_L2_PCI_CLEAR_BOUNDARY_SCAN_REQ_SHIFT 12
-#define BCHP_AON_PM_L2_PCI_CLEAR_BOUNDARY_SCAN_REQ_DEFAULT 0x00000000
-
-/* AON_PM_L2 :: PCI_CLEAR :: USB1 [11:11] */
-#define BCHP_AON_PM_L2_PCI_CLEAR_USB1_MASK 0x00000800
-#define BCHP_AON_PM_L2_PCI_CLEAR_USB1_SHIFT 11
-#define BCHP_AON_PM_L2_PCI_CLEAR_USB1_DEFAULT 0x00000000
-
-/* AON_PM_L2 :: PCI_CLEAR :: USB0 [10:10] */
-#define BCHP_AON_PM_L2_PCI_CLEAR_USB0_MASK 0x00000400
-#define BCHP_AON_PM_L2_PCI_CLEAR_USB0_SHIFT 10
-#define BCHP_AON_PM_L2_PCI_CLEAR_USB0_DEFAULT 0x00000000
-
-/* AON_PM_L2 :: PCI_CLEAR :: MOCA [09:09] */
-#define BCHP_AON_PM_L2_PCI_CLEAR_MOCA_MASK 0x00000200
-#define BCHP_AON_PM_L2_PCI_CLEAR_MOCA_SHIFT 9
-#define BCHP_AON_PM_L2_PCI_CLEAR_MOCA_DEFAULT 0x00000000
-
-/* AON_PM_L2 :: PCI_CLEAR :: XPT_PMU [08:08] */
-#define BCHP_AON_PM_L2_PCI_CLEAR_XPT_PMU_MASK 0x00000100
-#define BCHP_AON_PM_L2_PCI_CLEAR_XPT_PMU_SHIFT 8
-#define BCHP_AON_PM_L2_PCI_CLEAR_XPT_PMU_DEFAULT 0x00000000
-
-/* AON_PM_L2 :: PCI_CLEAR :: WOL_GENET1 [07:07] */
-#define BCHP_AON_PM_L2_PCI_CLEAR_WOL_GENET1_MASK 0x00000080
-#define BCHP_AON_PM_L2_PCI_CLEAR_WOL_GENET1_SHIFT 7
-#define BCHP_AON_PM_L2_PCI_CLEAR_WOL_GENET1_DEFAULT 0x00000000
-
-/* AON_PM_L2 :: PCI_CLEAR :: WOL_GENET0 [06:06] */
-#define BCHP_AON_PM_L2_PCI_CLEAR_WOL_GENET0_MASK 0x00000040
-#define BCHP_AON_PM_L2_PCI_CLEAR_WOL_GENET0_SHIFT 6
-#define BCHP_AON_PM_L2_PCI_CLEAR_WOL_GENET0_DEFAULT 0x00000000
-
-/* AON_PM_L2 :: PCI_CLEAR :: GPIO [05:05] */
-#define BCHP_AON_PM_L2_PCI_CLEAR_GPIO_MASK 0x00000020
-#define BCHP_AON_PM_L2_PCI_CLEAR_GPIO_SHIFT 5
-#define BCHP_AON_PM_L2_PCI_CLEAR_GPIO_DEFAULT 0x00000000
-
-/* AON_PM_L2 :: PCI_CLEAR :: NMI_B_INTR [04:04] */
-#define BCHP_AON_PM_L2_PCI_CLEAR_NMI_B_INTR_MASK 0x00000010
-#define BCHP_AON_PM_L2_PCI_CLEAR_NMI_B_INTR_SHIFT 4
-#define BCHP_AON_PM_L2_PCI_CLEAR_NMI_B_INTR_DEFAULT 0x00000000
-
-/* AON_PM_L2 :: PCI_CLEAR :: TIMER_INTR [03:03] */
-#define BCHP_AON_PM_L2_PCI_CLEAR_TIMER_INTR_MASK 0x00000008
-#define BCHP_AON_PM_L2_PCI_CLEAR_TIMER_INTR_SHIFT 3
-#define BCHP_AON_PM_L2_PCI_CLEAR_TIMER_INTR_DEFAULT 0x00000000
-
-/* AON_PM_L2 :: PCI_CLEAR :: KPD_INTR [02:02] */
-#define BCHP_AON_PM_L2_PCI_CLEAR_KPD_INTR_MASK 0x00000004
-#define BCHP_AON_PM_L2_PCI_CLEAR_KPD_INTR_SHIFT 2
-#define BCHP_AON_PM_L2_PCI_CLEAR_KPD_INTR_DEFAULT 0x00000000
-
-/* AON_PM_L2 :: PCI_CLEAR :: IRR_INTR [01:01] */
-#define BCHP_AON_PM_L2_PCI_CLEAR_IRR_INTR_MASK 0x00000002
-#define BCHP_AON_PM_L2_PCI_CLEAR_IRR_INTR_SHIFT 1
-#define BCHP_AON_PM_L2_PCI_CLEAR_IRR_INTR_DEFAULT 0x00000000
-
-/* AON_PM_L2 :: PCI_CLEAR :: CEC_INTR [00:00] */
-#define BCHP_AON_PM_L2_PCI_CLEAR_CEC_INTR_MASK 0x00000001
-#define BCHP_AON_PM_L2_PCI_CLEAR_CEC_INTR_SHIFT 0
-#define BCHP_AON_PM_L2_PCI_CLEAR_CEC_INTR_DEFAULT 0x00000000
-
-/***************************************************************************
- *PCI_MASK_STATUS - PCI interrupt Mask Status Register
- ***************************************************************************/
-/* AON_PM_L2 :: PCI_MASK_STATUS :: reserved0 [31:15] */
-#define BCHP_AON_PM_L2_PCI_MASK_STATUS_reserved0_MASK 0xffff8000
-#define BCHP_AON_PM_L2_PCI_MASK_STATUS_reserved0_SHIFT 15
-
-/* AON_PM_L2 :: PCI_MASK_STATUS :: SPARE_WAKEUP_EVENT_0 [14:14] */
-#define BCHP_AON_PM_L2_PCI_MASK_STATUS_SPARE_WAKEUP_EVENT_0_MASK 0x00004000
-#define BCHP_AON_PM_L2_PCI_MASK_STATUS_SPARE_WAKEUP_EVENT_0_SHIFT 14
-#define BCHP_AON_PM_L2_PCI_MASK_STATUS_SPARE_WAKEUP_EVENT_0_DEFAULT 0x00000001
-
-/* AON_PM_L2 :: PCI_MASK_STATUS :: FP_RESET [13:13] */
-#define BCHP_AON_PM_L2_PCI_MASK_STATUS_FP_RESET_MASK 0x00002000
-#define BCHP_AON_PM_L2_PCI_MASK_STATUS_FP_RESET_SHIFT 13
-#define BCHP_AON_PM_L2_PCI_MASK_STATUS_FP_RESET_DEFAULT 0x00000001
-
-/* AON_PM_L2 :: PCI_MASK_STATUS :: BOUNDARY_SCAN_REQ [12:12] */
-#define BCHP_AON_PM_L2_PCI_MASK_STATUS_BOUNDARY_SCAN_REQ_MASK 0x00001000
-#define BCHP_AON_PM_L2_PCI_MASK_STATUS_BOUNDARY_SCAN_REQ_SHIFT 12
-#define BCHP_AON_PM_L2_PCI_MASK_STATUS_BOUNDARY_SCAN_REQ_DEFAULT 0x00000001
-
-/* AON_PM_L2 :: PCI_MASK_STATUS :: USB1 [11:11] */
-#define BCHP_AON_PM_L2_PCI_MASK_STATUS_USB1_MASK 0x00000800
-#define BCHP_AON_PM_L2_PCI_MASK_STATUS_USB1_SHIFT 11
-#define BCHP_AON_PM_L2_PCI_MASK_STATUS_USB1_DEFAULT 0x00000001
-
-/* AON_PM_L2 :: PCI_MASK_STATUS :: USB0 [10:10] */
-#define BCHP_AON_PM_L2_PCI_MASK_STATUS_USB0_MASK 0x00000400
-#define BCHP_AON_PM_L2_PCI_MASK_STATUS_USB0_SHIFT 10
-#define BCHP_AON_PM_L2_PCI_MASK_STATUS_USB0_DEFAULT 0x00000001
-
-/* AON_PM_L2 :: PCI_MASK_STATUS :: MOCA [09:09] */
-#define BCHP_AON_PM_L2_PCI_MASK_STATUS_MOCA_MASK 0x00000200
-#define BCHP_AON_PM_L2_PCI_MASK_STATUS_MOCA_SHIFT 9
-#define BCHP_AON_PM_L2_PCI_MASK_STATUS_MOCA_DEFAULT 0x00000001
-
-/* AON_PM_L2 :: PCI_MASK_STATUS :: XPT_PMU [08:08] */
-#define BCHP_AON_PM_L2_PCI_MASK_STATUS_XPT_PMU_MASK 0x00000100
-#define BCHP_AON_PM_L2_PCI_MASK_STATUS_XPT_PMU_SHIFT 8
-#define BCHP_AON_PM_L2_PCI_MASK_STATUS_XPT_PMU_DEFAULT 0x00000001
-
-/* AON_PM_L2 :: PCI_MASK_STATUS :: WOL_GENET1 [07:07] */
-#define BCHP_AON_PM_L2_PCI_MASK_STATUS_WOL_GENET1_MASK 0x00000080
-#define BCHP_AON_PM_L2_PCI_MASK_STATUS_WOL_GENET1_SHIFT 7
-#define BCHP_AON_PM_L2_PCI_MASK_STATUS_WOL_GENET1_DEFAULT 0x00000001
-
-/* AON_PM_L2 :: PCI_MASK_STATUS :: WOL_GENET0 [06:06] */
-#define BCHP_AON_PM_L2_PCI_MASK_STATUS_WOL_GENET0_MASK 0x00000040
-#define BCHP_AON_PM_L2_PCI_MASK_STATUS_WOL_GENET0_SHIFT 6
-#define BCHP_AON_PM_L2_PCI_MASK_STATUS_WOL_GENET0_DEFAULT 0x00000001
-
-/* AON_PM_L2 :: PCI_MASK_STATUS :: GPIO [05:05] */
-#define BCHP_AON_PM_L2_PCI_MASK_STATUS_GPIO_MASK 0x00000020
-#define BCHP_AON_PM_L2_PCI_MASK_STATUS_GPIO_SHIFT 5
-#define BCHP_AON_PM_L2_PCI_MASK_STATUS_GPIO_DEFAULT 0x00000001
-
-/* AON_PM_L2 :: PCI_MASK_STATUS :: NMI_B_INTR [04:04] */
-#define BCHP_AON_PM_L2_PCI_MASK_STATUS_NMI_B_INTR_MASK 0x00000010
-#define BCHP_AON_PM_L2_PCI_MASK_STATUS_NMI_B_INTR_SHIFT 4
-#define BCHP_AON_PM_L2_PCI_MASK_STATUS_NMI_B_INTR_DEFAULT 0x00000001
-
-/* AON_PM_L2 :: PCI_MASK_STATUS :: TIMER_INTR [03:03] */
-#define BCHP_AON_PM_L2_PCI_MASK_STATUS_TIMER_INTR_MASK 0x00000008
-#define BCHP_AON_PM_L2_PCI_MASK_STATUS_TIMER_INTR_SHIFT 3
-#define BCHP_AON_PM_L2_PCI_MASK_STATUS_TIMER_INTR_DEFAULT 0x00000001
-
-/* AON_PM_L2 :: PCI_MASK_STATUS :: KPD_INTR [02:02] */
-#define BCHP_AON_PM_L2_PCI_MASK_STATUS_KPD_INTR_MASK 0x00000004
-#define BCHP_AON_PM_L2_PCI_MASK_STATUS_KPD_INTR_SHIFT 2
-#define BCHP_AON_PM_L2_PCI_MASK_STATUS_KPD_INTR_DEFAULT 0x00000001
-
-/* AON_PM_L2 :: PCI_MASK_STATUS :: IRR_INTR [01:01] */
-#define BCHP_AON_PM_L2_PCI_MASK_STATUS_IRR_INTR_MASK 0x00000002
-#define BCHP_AON_PM_L2_PCI_MASK_STATUS_IRR_INTR_SHIFT 1
-#define BCHP_AON_PM_L2_PCI_MASK_STATUS_IRR_INTR_DEFAULT 0x00000001
-
-/* AON_PM_L2 :: PCI_MASK_STATUS :: CEC_INTR [00:00] */
-#define BCHP_AON_PM_L2_PCI_MASK_STATUS_CEC_INTR_MASK 0x00000001
-#define BCHP_AON_PM_L2_PCI_MASK_STATUS_CEC_INTR_SHIFT 0
-#define BCHP_AON_PM_L2_PCI_MASK_STATUS_CEC_INTR_DEFAULT 0x00000001
-
-/***************************************************************************
- *PCI_MASK_SET - PCI interrupt Mask Set Register
- ***************************************************************************/
-/* AON_PM_L2 :: PCI_MASK_SET :: reserved0 [31:15] */
-#define BCHP_AON_PM_L2_PCI_MASK_SET_reserved0_MASK 0xffff8000
-#define BCHP_AON_PM_L2_PCI_MASK_SET_reserved0_SHIFT 15
-
-/* AON_PM_L2 :: PCI_MASK_SET :: SPARE_WAKEUP_EVENT_0 [14:14] */
-#define BCHP_AON_PM_L2_PCI_MASK_SET_SPARE_WAKEUP_EVENT_0_MASK 0x00004000
-#define BCHP_AON_PM_L2_PCI_MASK_SET_SPARE_WAKEUP_EVENT_0_SHIFT 14
-#define BCHP_AON_PM_L2_PCI_MASK_SET_SPARE_WAKEUP_EVENT_0_DEFAULT 0x00000001
-
-/* AON_PM_L2 :: PCI_MASK_SET :: FP_RESET [13:13] */
-#define BCHP_AON_PM_L2_PCI_MASK_SET_FP_RESET_MASK 0x00002000
-#define BCHP_AON_PM_L2_PCI_MASK_SET_FP_RESET_SHIFT 13
-#define BCHP_AON_PM_L2_PCI_MASK_SET_FP_RESET_DEFAULT 0x00000001
-
-/* AON_PM_L2 :: PCI_MASK_SET :: BOUNDARY_SCAN_REQ [12:12] */
-#define BCHP_AON_PM_L2_PCI_MASK_SET_BOUNDARY_SCAN_REQ_MASK 0x00001000
-#define BCHP_AON_PM_L2_PCI_MASK_SET_BOUNDARY_SCAN_REQ_SHIFT 12
-#define BCHP_AON_PM_L2_PCI_MASK_SET_BOUNDARY_SCAN_REQ_DEFAULT 0x00000001
-
-/* AON_PM_L2 :: PCI_MASK_SET :: USB1 [11:11] */
-#define BCHP_AON_PM_L2_PCI_MASK_SET_USB1_MASK 0x00000800
-#define BCHP_AON_PM_L2_PCI_MASK_SET_USB1_SHIFT 11
-#define BCHP_AON_PM_L2_PCI_MASK_SET_USB1_DEFAULT 0x00000001
-
-/* AON_PM_L2 :: PCI_MASK_SET :: USB0 [10:10] */
-#define BCHP_AON_PM_L2_PCI_MASK_SET_USB0_MASK 0x00000400
-#define BCHP_AON_PM_L2_PCI_MASK_SET_USB0_SHIFT 10
-#define BCHP_AON_PM_L2_PCI_MASK_SET_USB0_DEFAULT 0x00000001
-
-/* AON_PM_L2 :: PCI_MASK_SET :: MOCA [09:09] */
-#define BCHP_AON_PM_L2_PCI_MASK_SET_MOCA_MASK 0x00000200
-#define BCHP_AON_PM_L2_PCI_MASK_SET_MOCA_SHIFT 9
-#define BCHP_AON_PM_L2_PCI_MASK_SET_MOCA_DEFAULT 0x00000001
-
-/* AON_PM_L2 :: PCI_MASK_SET :: XPT_PMU [08:08] */
-#define BCHP_AON_PM_L2_PCI_MASK_SET_XPT_PMU_MASK 0x00000100
-#define BCHP_AON_PM_L2_PCI_MASK_SET_XPT_PMU_SHIFT 8
-#define BCHP_AON_PM_L2_PCI_MASK_SET_XPT_PMU_DEFAULT 0x00000001
-
-/* AON_PM_L2 :: PCI_MASK_SET :: WOL_GENET1 [07:07] */
-#define BCHP_AON_PM_L2_PCI_MASK_SET_WOL_GENET1_MASK 0x00000080
-#define BCHP_AON_PM_L2_PCI_MASK_SET_WOL_GENET1_SHIFT 7
-#define BCHP_AON_PM_L2_PCI_MASK_SET_WOL_GENET1_DEFAULT 0x00000001
-
-/* AON_PM_L2 :: PCI_MASK_SET :: WOL_GENET0 [06:06] */
-#define BCHP_AON_PM_L2_PCI_MASK_SET_WOL_GENET0_MASK 0x00000040
-#define BCHP_AON_PM_L2_PCI_MASK_SET_WOL_GENET0_SHIFT 6
-#define BCHP_AON_PM_L2_PCI_MASK_SET_WOL_GENET0_DEFAULT 0x00000001
-
-/* AON_PM_L2 :: PCI_MASK_SET :: GPIO [05:05] */
-#define BCHP_AON_PM_L2_PCI_MASK_SET_GPIO_MASK 0x00000020
-#define BCHP_AON_PM_L2_PCI_MASK_SET_GPIO_SHIFT 5
-#define BCHP_AON_PM_L2_PCI_MASK_SET_GPIO_DEFAULT 0x00000001
-
-/* AON_PM_L2 :: PCI_MASK_SET :: NMI_B_INTR [04:04] */
-#define BCHP_AON_PM_L2_PCI_MASK_SET_NMI_B_INTR_MASK 0x00000010
-#define BCHP_AON_PM_L2_PCI_MASK_SET_NMI_B_INTR_SHIFT 4
-#define BCHP_AON_PM_L2_PCI_MASK_SET_NMI_B_INTR_DEFAULT 0x00000001
-
-/* AON_PM_L2 :: PCI_MASK_SET :: TIMER_INTR [03:03] */
-#define BCHP_AON_PM_L2_PCI_MASK_SET_TIMER_INTR_MASK 0x00000008
-#define BCHP_AON_PM_L2_PCI_MASK_SET_TIMER_INTR_SHIFT 3
-#define BCHP_AON_PM_L2_PCI_MASK_SET_TIMER_INTR_DEFAULT 0x00000001
-
-/* AON_PM_L2 :: PCI_MASK_SET :: KPD_INTR [02:02] */
-#define BCHP_AON_PM_L2_PCI_MASK_SET_KPD_INTR_MASK 0x00000004
-#define BCHP_AON_PM_L2_PCI_MASK_SET_KPD_INTR_SHIFT 2
-#define BCHP_AON_PM_L2_PCI_MASK_SET_KPD_INTR_DEFAULT 0x00000001
-
-/* AON_PM_L2 :: PCI_MASK_SET :: IRR_INTR [01:01] */
-#define BCHP_AON_PM_L2_PCI_MASK_SET_IRR_INTR_MASK 0x00000002
-#define BCHP_AON_PM_L2_PCI_MASK_SET_IRR_INTR_SHIFT 1
-#define BCHP_AON_PM_L2_PCI_MASK_SET_IRR_INTR_DEFAULT 0x00000001
-
-/* AON_PM_L2 :: PCI_MASK_SET :: CEC_INTR [00:00] */
-#define BCHP_AON_PM_L2_PCI_MASK_SET_CEC_INTR_MASK 0x00000001
-#define BCHP_AON_PM_L2_PCI_MASK_SET_CEC_INTR_SHIFT 0
-#define BCHP_AON_PM_L2_PCI_MASK_SET_CEC_INTR_DEFAULT 0x00000001
-
-/***************************************************************************
- *PCI_MASK_CLEAR - PCI interrupt Mask Clear Register
- ***************************************************************************/
-/* AON_PM_L2 :: PCI_MASK_CLEAR :: reserved0 [31:15] */
-#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_reserved0_MASK 0xffff8000
-#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_reserved0_SHIFT 15
-
-/* AON_PM_L2 :: PCI_MASK_CLEAR :: SPARE_WAKEUP_EVENT_0 [14:14] */
-#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_SPARE_WAKEUP_EVENT_0_MASK 0x00004000
-#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_SPARE_WAKEUP_EVENT_0_SHIFT 14
-#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_SPARE_WAKEUP_EVENT_0_DEFAULT 0x00000001
-
-/* AON_PM_L2 :: PCI_MASK_CLEAR :: FP_RESET [13:13] */
-#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_FP_RESET_MASK 0x00002000
-#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_FP_RESET_SHIFT 13
-#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_FP_RESET_DEFAULT 0x00000001
-
-/* AON_PM_L2 :: PCI_MASK_CLEAR :: BOUNDARY_SCAN_REQ [12:12] */
-#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_BOUNDARY_SCAN_REQ_MASK 0x00001000
-#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_BOUNDARY_SCAN_REQ_SHIFT 12
-#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_BOUNDARY_SCAN_REQ_DEFAULT 0x00000001
-
-/* AON_PM_L2 :: PCI_MASK_CLEAR :: USB1 [11:11] */
-#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_USB1_MASK 0x00000800
-#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_USB1_SHIFT 11
-#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_USB1_DEFAULT 0x00000001
-
-/* AON_PM_L2 :: PCI_MASK_CLEAR :: USB0 [10:10] */
-#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_USB0_MASK 0x00000400
-#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_USB0_SHIFT 10
-#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_USB0_DEFAULT 0x00000001
-
-/* AON_PM_L2 :: PCI_MASK_CLEAR :: MOCA [09:09] */
-#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_MOCA_MASK 0x00000200
-#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_MOCA_SHIFT 9
-#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_MOCA_DEFAULT 0x00000001
-
-/* AON_PM_L2 :: PCI_MASK_CLEAR :: XPT_PMU [08:08] */
-#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_XPT_PMU_MASK 0x00000100
-#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_XPT_PMU_SHIFT 8
-#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_XPT_PMU_DEFAULT 0x00000001
-
-/* AON_PM_L2 :: PCI_MASK_CLEAR :: WOL_GENET1 [07:07] */
-#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_WOL_GENET1_MASK 0x00000080
-#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_WOL_GENET1_SHIFT 7
-#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_WOL_GENET1_DEFAULT 0x00000001
-
-/* AON_PM_L2 :: PCI_MASK_CLEAR :: WOL_GENET0 [06:06] */
-#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_WOL_GENET0_MASK 0x00000040
-#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_WOL_GENET0_SHIFT 6
-#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_WOL_GENET0_DEFAULT 0x00000001
-
-/* AON_PM_L2 :: PCI_MASK_CLEAR :: GPIO [05:05] */
-#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_GPIO_MASK 0x00000020
-#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_GPIO_SHIFT 5
-#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_GPIO_DEFAULT 0x00000001
-
-/* AON_PM_L2 :: PCI_MASK_CLEAR :: NMI_B_INTR [04:04] */
-#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_NMI_B_INTR_MASK 0x00000010
-#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_NMI_B_INTR_SHIFT 4
-#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_NMI_B_INTR_DEFAULT 0x00000001
-
-/* AON_PM_L2 :: PCI_MASK_CLEAR :: TIMER_INTR [03:03] */
-#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_TIMER_INTR_MASK 0x00000008
-#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_TIMER_INTR_SHIFT 3
-#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_TIMER_INTR_DEFAULT 0x00000001
-
-/* AON_PM_L2 :: PCI_MASK_CLEAR :: KPD_INTR [02:02] */
-#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_KPD_INTR_MASK 0x00000004
-#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_KPD_INTR_SHIFT 2
-#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_KPD_INTR_DEFAULT 0x00000001
-
-/* AON_PM_L2 :: PCI_MASK_CLEAR :: IRR_INTR [01:01] */
-#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_IRR_INTR_MASK 0x00000002
-#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_IRR_INTR_SHIFT 1
-#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_IRR_INTR_DEFAULT 0x00000001
-
-/* AON_PM_L2 :: PCI_MASK_CLEAR :: CEC_INTR [00:00] */
-#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_CEC_INTR_MASK 0x00000001
-#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_CEC_INTR_SHIFT 0
-#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_CEC_INTR_DEFAULT 0x00000001
-
-#endif /* #ifndef BCHP_AON_PM_L2_H__ */
-
-/* End of File */
diff --git a/include/linux/brcmstb/7439a0/bchp_bspi.h b/include/linux/brcmstb/7439a0/bchp_bspi.h
deleted file mode 100644
index c9cb22c..0000000
--- a/include/linux/brcmstb/7439a0/bchp_bspi.h
+++ /dev/null
@@ -1,443 +0,0 @@
-/***************************************************************************
- * Copyright (c) 1999-2013, Broadcom Corporation
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
- *
- * Module Description:
- * DO NOT EDIT THIS FILE DIRECTLY
- *
- * This module was generated magically with RDB from a source description
- * file. You must edit the source file for changes to be made to this file.
- *
- *
- * Date: Generated on Tue Apr 16 03:26:51 2013
- * MD5 Checksum d41d8cd98f00b204e9800998ecf8427e
- *
- * Compiled with: RDB Utility combo_header.pl
- * RDB Parser 3.0
- * unknown unknown
- * Perl Interpreter 5.008008
- * Operating System linux
- *
- * Revision History:
- *
- * $brcm_Log: $
- *
- ***************************************************************************/
-
-#ifndef BCHP_BSPI_H__
-#define BCHP_BSPI_H__
-
-/***************************************************************************
- *BSPI - Public BSPI Control Registers
- ***************************************************************************/
-#define BCHP_BSPI_REVISION_ID 0x00443200 /* Revision ID */
-#define BCHP_BSPI_SCRATCH 0x00443204 /* Revision ID */
-#define BCHP_BSPI_MAST_N_BOOT_CTRL 0x00443208 /* Master/Boot SPI Control Register */
-#define BCHP_BSPI_BUSY_STATUS 0x0044320c /* BSPI Busy Status Register */
-#define BCHP_BSPI_INTR_STATUS 0x00443210 /* Interrupt Status Register */
-#define BCHP_BSPI_B0_STATUS 0x00443214 /* Prefetch Buffer 0 Status Register */
-#define BCHP_BSPI_B0_CTRL 0x00443218 /* Prefetch Buffer 0 Control Register */
-#define BCHP_BSPI_B1_STATUS 0x0044321c /* Prefetch Buffer 1 Status Register */
-#define BCHP_BSPI_B1_CTRL 0x00443220 /* Prefetch Buffer 1 Control Register */
-#define BCHP_BSPI_STRAP_OVERRIDE_CTRL 0x00443224 /* Dual/Single Receive Mode Control Register */
-#define BCHP_BSPI_FLEX_MODE_ENABLE 0x00443228 /* Flexible Control Mode Enable Register */
-#define BCHP_BSPI_BITS_PER_CYCLE 0x0044322c /* Bits per cycle "b-p-c" Control Register */
-#define BCHP_BSPI_BITS_PER_PHASE 0x00443230 /* Bits per Phase "b-p-p" Control Register */
-#define BCHP_BSPI_CMD_AND_MODE_BYTE 0x00443234 /* Command and Mode Data Register */
-#define BCHP_BSPI_BSPI_FLASH_UPPER_ADDR_BYTE 0x00443238 /* Bspi FLash upper address byte register */
-#define BCHP_BSPI_BSPI_XOR_VALUE 0x0044323c /* BSPI FLASH XOR Value Register */
-#define BCHP_BSPI_BSPI_XOR_ENABLE 0x00443240 /* BSPI FLASH XOR Enable Register */
-#define BCHP_BSPI_BSPI_PIO_MODE_ENABLE 0x00443244 /* BSPI Pin Programmed IO Mode Enable Register */
-#define BCHP_BSPI_BSPI_PIO_IODIR 0x00443248 /* BSPI Pin Programmed IO Mode Direction Register */
-#define BCHP_BSPI_BSPI_PIO_DATA 0x0044324c /* BSPI Pin Programmed IO Mode Data Register */
-
-/***************************************************************************
- *REVISION_ID - Revision ID
- ***************************************************************************/
-/* BSPI :: REVISION_ID :: reserved0 [31:16] */
-#define BCHP_BSPI_REVISION_ID_reserved0_MASK 0xffff0000
-#define BCHP_BSPI_REVISION_ID_reserved0_SHIFT 16
-
-/* BSPI :: REVISION_ID :: MAJOR [15:08] */
-#define BCHP_BSPI_REVISION_ID_MAJOR_MASK 0x0000ff00
-#define BCHP_BSPI_REVISION_ID_MAJOR_SHIFT 8
-#define BCHP_BSPI_REVISION_ID_MAJOR_DEFAULT 0x00000004
-
-/* BSPI :: REVISION_ID :: MINOR [07:00] */
-#define BCHP_BSPI_REVISION_ID_MINOR_MASK 0x000000ff
-#define BCHP_BSPI_REVISION_ID_MINOR_SHIFT 0
-#define BCHP_BSPI_REVISION_ID_MINOR_DEFAULT 0x00000002
-
-/***************************************************************************
- *SCRATCH - Revision ID
- ***************************************************************************/
-/* BSPI :: SCRATCH :: SCRATCH [31:00] */
-#define BCHP_BSPI_SCRATCH_SCRATCH_MASK 0xffffffff
-#define BCHP_BSPI_SCRATCH_SCRATCH_SHIFT 0
-#define BCHP_BSPI_SCRATCH_SCRATCH_DEFAULT 0x00000000
-
-/***************************************************************************
- *MAST_N_BOOT_CTRL - Master/Boot SPI Control Register
- ***************************************************************************/
-/* BSPI :: MAST_N_BOOT_CTRL :: reserved0 [31:01] */
-#define BCHP_BSPI_MAST_N_BOOT_CTRL_reserved0_MASK 0xfffffffe
-#define BCHP_BSPI_MAST_N_BOOT_CTRL_reserved0_SHIFT 1
-
-/* BSPI :: MAST_N_BOOT_CTRL :: mast_n_boot [00:00] */
-#define BCHP_BSPI_MAST_N_BOOT_CTRL_mast_n_boot_MASK 0x00000001
-#define BCHP_BSPI_MAST_N_BOOT_CTRL_mast_n_boot_SHIFT 0
-#define BCHP_BSPI_MAST_N_BOOT_CTRL_mast_n_boot_DEFAULT 0x00000000
-
-/***************************************************************************
- *BUSY_STATUS - BSPI Busy Status Register
- ***************************************************************************/
-/* BSPI :: BUSY_STATUS :: reserved0 [31:01] */
-#define BCHP_BSPI_BUSY_STATUS_reserved0_MASK 0xfffffffe
-#define BCHP_BSPI_BUSY_STATUS_reserved0_SHIFT 1
-
-/* BSPI :: BUSY_STATUS :: busy [00:00] */
-#define BCHP_BSPI_BUSY_STATUS_busy_MASK 0x00000001
-#define BCHP_BSPI_BUSY_STATUS_busy_SHIFT 0
-#define BCHP_BSPI_BUSY_STATUS_busy_DEFAULT 0x00000000
-
-/***************************************************************************
- *INTR_STATUS - Interrupt Status Register
- ***************************************************************************/
-/* BSPI :: INTR_STATUS :: reserved0 [31:02] */
-#define BCHP_BSPI_INTR_STATUS_reserved0_MASK 0xfffffffc
-#define BCHP_BSPI_INTR_STATUS_reserved0_SHIFT 2
-
-/* BSPI :: INTR_STATUS :: intr_1 [01:01] */
-#define BCHP_BSPI_INTR_STATUS_intr_1_MASK 0x00000002
-#define BCHP_BSPI_INTR_STATUS_intr_1_SHIFT 1
-#define BCHP_BSPI_INTR_STATUS_intr_1_DEFAULT 0x00000000
-
-/* BSPI :: INTR_STATUS :: intr_0 [00:00] */
-#define BCHP_BSPI_INTR_STATUS_intr_0_MASK 0x00000001
-#define BCHP_BSPI_INTR_STATUS_intr_0_SHIFT 0
-#define BCHP_BSPI_INTR_STATUS_intr_0_DEFAULT 0x00000000
-
-/***************************************************************************
- *B0_STATUS - Prefetch Buffer 0 Status Register
- ***************************************************************************/
-/* BSPI :: B0_STATUS :: reserved0 [31:31] */
-#define BCHP_BSPI_B0_STATUS_reserved0_MASK 0x80000000
-#define BCHP_BSPI_B0_STATUS_reserved0_SHIFT 31
-
-/* BSPI :: B0_STATUS :: b0_prefetch_active [30:30] */
-#define BCHP_BSPI_B0_STATUS_b0_prefetch_active_MASK 0x40000000
-#define BCHP_BSPI_B0_STATUS_b0_prefetch_active_SHIFT 30
-#define BCHP_BSPI_B0_STATUS_b0_prefetch_active_DEFAULT 0x00000000
-
-/* BSPI :: B0_STATUS :: b0_full [29:29] */
-#define BCHP_BSPI_B0_STATUS_b0_full_MASK 0x20000000
-#define BCHP_BSPI_B0_STATUS_b0_full_SHIFT 29
-#define BCHP_BSPI_B0_STATUS_b0_full_DEFAULT 0x00000000
-
-/* BSPI :: B0_STATUS :: b0_empty [28:28] */
-#define BCHP_BSPI_B0_STATUS_b0_empty_MASK 0x10000000
-#define BCHP_BSPI_B0_STATUS_b0_empty_SHIFT 28
-#define BCHP_BSPI_B0_STATUS_b0_empty_DEFAULT 0x00000001
-
-/* BSPI :: B0_STATUS :: b0_miss [27:27] */
-#define BCHP_BSPI_B0_STATUS_b0_miss_MASK 0x08000000
-#define BCHP_BSPI_B0_STATUS_b0_miss_SHIFT 27
-#define BCHP_BSPI_B0_STATUS_b0_miss_DEFAULT 0x00000000
-
-/* BSPI :: B0_STATUS :: b0_hit [26:26] */
-#define BCHP_BSPI_B0_STATUS_b0_hit_MASK 0x04000000
-#define BCHP_BSPI_B0_STATUS_b0_hit_SHIFT 26
-#define BCHP_BSPI_B0_STATUS_b0_hit_DEFAULT 0x00000000
-
-/* BSPI :: B0_STATUS :: b0_address [25:00] */
-#define BCHP_BSPI_B0_STATUS_b0_address_MASK 0x03ffffff
-#define BCHP_BSPI_B0_STATUS_b0_address_SHIFT 0
-#define BCHP_BSPI_B0_STATUS_b0_address_DEFAULT 0x00000000
-
-/***************************************************************************
- *B0_CTRL - Prefetch Buffer 0 Control Register
- ***************************************************************************/
-/* BSPI :: B0_CTRL :: reserved0 [31:01] */
-#define BCHP_BSPI_B0_CTRL_reserved0_MASK 0xfffffffe
-#define BCHP_BSPI_B0_CTRL_reserved0_SHIFT 1
-
-/* BSPI :: B0_CTRL :: b0_flush [00:00] */
-#define BCHP_BSPI_B0_CTRL_b0_flush_MASK 0x00000001
-#define BCHP_BSPI_B0_CTRL_b0_flush_SHIFT 0
-#define BCHP_BSPI_B0_CTRL_b0_flush_DEFAULT 0x00000000
-
-/***************************************************************************
- *B1_STATUS - Prefetch Buffer 1 Status Register
- ***************************************************************************/
-/* BSPI :: B1_STATUS :: reserved0 [31:31] */
-#define BCHP_BSPI_B1_STATUS_reserved0_MASK 0x80000000
-#define BCHP_BSPI_B1_STATUS_reserved0_SHIFT 31
-
-/* BSPI :: B1_STATUS :: b1_prefetch_active [30:30] */
-#define BCHP_BSPI_B1_STATUS_b1_prefetch_active_MASK 0x40000000
-#define BCHP_BSPI_B1_STATUS_b1_prefetch_active_SHIFT 30
-#define BCHP_BSPI_B1_STATUS_b1_prefetch_active_DEFAULT 0x00000000
-
-/* BSPI :: B1_STATUS :: b1_full [29:29] */
-#define BCHP_BSPI_B1_STATUS_b1_full_MASK 0x20000000
-#define BCHP_BSPI_B1_STATUS_b1_full_SHIFT 29
-#define BCHP_BSPI_B1_STATUS_b1_full_DEFAULT 0x00000000
-
-/* BSPI :: B1_STATUS :: b1_empty [28:28] */
-#define BCHP_BSPI_B1_STATUS_b1_empty_MASK 0x10000000
-#define BCHP_BSPI_B1_STATUS_b1_empty_SHIFT 28
-#define BCHP_BSPI_B1_STATUS_b1_empty_DEFAULT 0x00000001
-
-/* BSPI :: B1_STATUS :: b1_miss [27:27] */
-#define BCHP_BSPI_B1_STATUS_b1_miss_MASK 0x08000000
-#define BCHP_BSPI_B1_STATUS_b1_miss_SHIFT 27
-#define BCHP_BSPI_B1_STATUS_b1_miss_DEFAULT 0x00000000
-
-/* BSPI :: B1_STATUS :: b1_hit [26:26] */
-#define BCHP_BSPI_B1_STATUS_b1_hit_MASK 0x04000000
-#define BCHP_BSPI_B1_STATUS_b1_hit_SHIFT 26
-#define BCHP_BSPI_B1_STATUS_b1_hit_DEFAULT 0x00000000
-
-/* BSPI :: B1_STATUS :: b1_address [25:00] */
-#define BCHP_BSPI_B1_STATUS_b1_address_MASK 0x03ffffff
-#define BCHP_BSPI_B1_STATUS_b1_address_SHIFT 0
-#define BCHP_BSPI_B1_STATUS_b1_address_DEFAULT 0x00000000
-
-/***************************************************************************
- *B1_CTRL - Prefetch Buffer 1 Control Register
- ***************************************************************************/
-/* BSPI :: B1_CTRL :: reserved0 [31:01] */
-#define BCHP_BSPI_B1_CTRL_reserved0_MASK 0xfffffffe
-#define BCHP_BSPI_B1_CTRL_reserved0_SHIFT 1
-
-/* BSPI :: B1_CTRL :: b1_flush [00:00] */
-#define BCHP_BSPI_B1_CTRL_b1_flush_MASK 0x00000001
-#define BCHP_BSPI_B1_CTRL_b1_flush_SHIFT 0
-#define BCHP_BSPI_B1_CTRL_b1_flush_DEFAULT 0x00000000
-
-/***************************************************************************
- *STRAP_OVERRIDE_CTRL - Dual/Single Receive Mode Control Register
- ***************************************************************************/
-/* BSPI :: STRAP_OVERRIDE_CTRL :: reserved0 [31:05] */
-#define BCHP_BSPI_STRAP_OVERRIDE_CTRL_reserved0_MASK 0xffffffe0
-#define BCHP_BSPI_STRAP_OVERRIDE_CTRL_reserved0_SHIFT 5
-
-/* BSPI :: STRAP_OVERRIDE_CTRL :: endian_mode [04:04] */
-#define BCHP_BSPI_STRAP_OVERRIDE_CTRL_endian_mode_MASK 0x00000010
-#define BCHP_BSPI_STRAP_OVERRIDE_CTRL_endian_mode_SHIFT 4
-#define BCHP_BSPI_STRAP_OVERRIDE_CTRL_endian_mode_DEFAULT 0x00000000
-
-/* BSPI :: STRAP_OVERRIDE_CTRL :: data_quad [03:03] */
-#define BCHP_BSPI_STRAP_OVERRIDE_CTRL_data_quad_MASK 0x00000008
-#define BCHP_BSPI_STRAP_OVERRIDE_CTRL_data_quad_SHIFT 3
-#define BCHP_BSPI_STRAP_OVERRIDE_CTRL_data_quad_DEFAULT 0x00000000
-
-/* BSPI :: STRAP_OVERRIDE_CTRL :: addr_4byte_n_3byte [02:02] */
-#define BCHP_BSPI_STRAP_OVERRIDE_CTRL_addr_4byte_n_3byte_MASK 0x00000004
-#define BCHP_BSPI_STRAP_OVERRIDE_CTRL_addr_4byte_n_3byte_SHIFT 2
-#define BCHP_BSPI_STRAP_OVERRIDE_CTRL_addr_4byte_n_3byte_DEFAULT 0x00000000
-
-/* BSPI :: STRAP_OVERRIDE_CTRL :: data_dual_n_sgl [01:01] */
-#define BCHP_BSPI_STRAP_OVERRIDE_CTRL_data_dual_n_sgl_MASK 0x00000002
-#define BCHP_BSPI_STRAP_OVERRIDE_CTRL_data_dual_n_sgl_SHIFT 1
-#define BCHP_BSPI_STRAP_OVERRIDE_CTRL_data_dual_n_sgl_DEFAULT 0x00000000
-
-/* BSPI :: STRAP_OVERRIDE_CTRL :: override [00:00] */
-#define BCHP_BSPI_STRAP_OVERRIDE_CTRL_override_MASK 0x00000001
-#define BCHP_BSPI_STRAP_OVERRIDE_CTRL_override_SHIFT 0
-#define BCHP_BSPI_STRAP_OVERRIDE_CTRL_override_DEFAULT 0x00000000
-
-/***************************************************************************
- *FLEX_MODE_ENABLE - Flexible Control Mode Enable Register
- ***************************************************************************/
-/* BSPI :: FLEX_MODE_ENABLE :: reserved0 [31:01] */
-#define BCHP_BSPI_FLEX_MODE_ENABLE_reserved0_MASK 0xfffffffe
-#define BCHP_BSPI_FLEX_MODE_ENABLE_reserved0_SHIFT 1
-
-/* BSPI :: FLEX_MODE_ENABLE :: bspi_flex_mode_enable [00:00] */
-#define BCHP_BSPI_FLEX_MODE_ENABLE_bspi_flex_mode_enable_MASK 0x00000001
-#define BCHP_BSPI_FLEX_MODE_ENABLE_bspi_flex_mode_enable_SHIFT 0
-#define BCHP_BSPI_FLEX_MODE_ENABLE_bspi_flex_mode_enable_DEFAULT 0x00000000
-
-/***************************************************************************
- *BITS_PER_CYCLE - Bits per cycle "b-p-c" Control Register
- ***************************************************************************/
-/* BSPI :: BITS_PER_CYCLE :: reserved0 [31:26] */
-#define BCHP_BSPI_BITS_PER_CYCLE_reserved0_MASK 0xfc000000
-#define BCHP_BSPI_BITS_PER_CYCLE_reserved0_SHIFT 26
-
-/* BSPI :: BITS_PER_CYCLE :: cmd_bpc_select [25:24] */
-#define BCHP_BSPI_BITS_PER_CYCLE_cmd_bpc_select_MASK 0x03000000
-#define BCHP_BSPI_BITS_PER_CYCLE_cmd_bpc_select_SHIFT 24
-#define BCHP_BSPI_BITS_PER_CYCLE_cmd_bpc_select_DEFAULT 0x00000000
-
-/* BSPI :: BITS_PER_CYCLE :: reserved1 [23:18] */
-#define BCHP_BSPI_BITS_PER_CYCLE_reserved1_MASK 0x00fc0000
-#define BCHP_BSPI_BITS_PER_CYCLE_reserved1_SHIFT 18
-
-/* BSPI :: BITS_PER_CYCLE :: addr_bpc_select [17:16] */
-#define BCHP_BSPI_BITS_PER_CYCLE_addr_bpc_select_MASK 0x00030000
-#define BCHP_BSPI_BITS_PER_CYCLE_addr_bpc_select_SHIFT 16
-#define BCHP_BSPI_BITS_PER_CYCLE_addr_bpc_select_DEFAULT 0x00000000
-
-/* BSPI :: BITS_PER_CYCLE :: reserved2 [15:10] */
-#define BCHP_BSPI_BITS_PER_CYCLE_reserved2_MASK 0x0000fc00
-#define BCHP_BSPI_BITS_PER_CYCLE_reserved2_SHIFT 10
-
-/* BSPI :: BITS_PER_CYCLE :: mode_bpc_select [09:08] */
-#define BCHP_BSPI_BITS_PER_CYCLE_mode_bpc_select_MASK 0x00000300
-#define BCHP_BSPI_BITS_PER_CYCLE_mode_bpc_select_SHIFT 8
-#define BCHP_BSPI_BITS_PER_CYCLE_mode_bpc_select_DEFAULT 0x00000000
-
-/* BSPI :: BITS_PER_CYCLE :: reserved3 [07:02] */
-#define BCHP_BSPI_BITS_PER_CYCLE_reserved3_MASK 0x000000fc
-#define BCHP_BSPI_BITS_PER_CYCLE_reserved3_SHIFT 2
-
-/* BSPI :: BITS_PER_CYCLE :: data_bpc_select [01:00] */
-#define BCHP_BSPI_BITS_PER_CYCLE_data_bpc_select_MASK 0x00000003
-#define BCHP_BSPI_BITS_PER_CYCLE_data_bpc_select_SHIFT 0
-#define BCHP_BSPI_BITS_PER_CYCLE_data_bpc_select_DEFAULT 0x00000000
-
-/***************************************************************************
- *BITS_PER_PHASE - Bits per Phase "b-p-p" Control Register
- ***************************************************************************/
-/* BSPI :: BITS_PER_PHASE :: reserved0 [31:25] */
-#define BCHP_BSPI_BITS_PER_PHASE_reserved0_MASK 0xfe000000
-#define BCHP_BSPI_BITS_PER_PHASE_reserved0_SHIFT 25
-
-/* BSPI :: BITS_PER_PHASE :: cmd_bpp_select [24:24] */
-#define BCHP_BSPI_BITS_PER_PHASE_cmd_bpp_select_MASK 0x01000000
-#define BCHP_BSPI_BITS_PER_PHASE_cmd_bpp_select_SHIFT 24
-#define BCHP_BSPI_BITS_PER_PHASE_cmd_bpp_select_DEFAULT 0x00000000
-
-/* BSPI :: BITS_PER_PHASE :: reserved1 [23:17] */
-#define BCHP_BSPI_BITS_PER_PHASE_reserved1_MASK 0x00fe0000
-#define BCHP_BSPI_BITS_PER_PHASE_reserved1_SHIFT 17
-
-/* BSPI :: BITS_PER_PHASE :: addr_bpp_select [16:16] */
-#define BCHP_BSPI_BITS_PER_PHASE_addr_bpp_select_MASK 0x00010000
-#define BCHP_BSPI_BITS_PER_PHASE_addr_bpp_select_SHIFT 16
-#define BCHP_BSPI_BITS_PER_PHASE_addr_bpp_select_DEFAULT 0x00000000
-
-/* BSPI :: BITS_PER_PHASE :: reserved2 [15:09] */
-#define BCHP_BSPI_BITS_PER_PHASE_reserved2_MASK 0x0000fe00
-#define BCHP_BSPI_BITS_PER_PHASE_reserved2_SHIFT 9
-
-/* BSPI :: BITS_PER_PHASE :: mode_bpp [08:08] */
-#define BCHP_BSPI_BITS_PER_PHASE_mode_bpp_MASK 0x00000100
-#define BCHP_BSPI_BITS_PER_PHASE_mode_bpp_SHIFT 8
-#define BCHP_BSPI_BITS_PER_PHASE_mode_bpp_DEFAULT 0x00000000
-
-/* BSPI :: BITS_PER_PHASE :: dummy_cycles [07:00] */
-#define BCHP_BSPI_BITS_PER_PHASE_dummy_cycles_MASK 0x000000ff
-#define BCHP_BSPI_BITS_PER_PHASE_dummy_cycles_SHIFT 0
-#define BCHP_BSPI_BITS_PER_PHASE_dummy_cycles_DEFAULT 0x00000008
-
-/***************************************************************************
- *CMD_AND_MODE_BYTE - Command and Mode Data Register
- ***************************************************************************/
-/* BSPI :: CMD_AND_MODE_BYTE :: reserved0 [31:24] */
-#define BCHP_BSPI_CMD_AND_MODE_BYTE_reserved0_MASK 0xff000000
-#define BCHP_BSPI_CMD_AND_MODE_BYTE_reserved0_SHIFT 24
-
-/* BSPI :: CMD_AND_MODE_BYTE :: bspi_mode_byte [23:16] */
-#define BCHP_BSPI_CMD_AND_MODE_BYTE_bspi_mode_byte_MASK 0x00ff0000
-#define BCHP_BSPI_CMD_AND_MODE_BYTE_bspi_mode_byte_SHIFT 16
-#define BCHP_BSPI_CMD_AND_MODE_BYTE_bspi_mode_byte_DEFAULT 0x00000000
-
-/* BSPI :: CMD_AND_MODE_BYTE :: reserved1 [15:08] */
-#define BCHP_BSPI_CMD_AND_MODE_BYTE_reserved1_MASK 0x0000ff00
-#define BCHP_BSPI_CMD_AND_MODE_BYTE_reserved1_SHIFT 8
-
-/* BSPI :: CMD_AND_MODE_BYTE :: bspi_cmd_byte [07:00] */
-#define BCHP_BSPI_CMD_AND_MODE_BYTE_bspi_cmd_byte_MASK 0x000000ff
-#define BCHP_BSPI_CMD_AND_MODE_BYTE_bspi_cmd_byte_SHIFT 0
-#define BCHP_BSPI_CMD_AND_MODE_BYTE_bspi_cmd_byte_DEFAULT 0x0000000b
-
-/***************************************************************************
- *BSPI_FLASH_UPPER_ADDR_BYTE - Bspi FLash upper address byte register
- ***************************************************************************/
-/* BSPI :: BSPI_FLASH_UPPER_ADDR_BYTE :: bspi_flash_upper_addr [31:24] */
-#define BCHP_BSPI_BSPI_FLASH_UPPER_ADDR_BYTE_bspi_flash_upper_addr_MASK 0xff000000
-#define BCHP_BSPI_BSPI_FLASH_UPPER_ADDR_BYTE_bspi_flash_upper_addr_SHIFT 24
-#define BCHP_BSPI_BSPI_FLASH_UPPER_ADDR_BYTE_bspi_flash_upper_addr_DEFAULT 0x00000000
-
-/* BSPI :: BSPI_FLASH_UPPER_ADDR_BYTE :: reserved0 [23:00] */
-#define BCHP_BSPI_BSPI_FLASH_UPPER_ADDR_BYTE_reserved0_MASK 0x00ffffff
-#define BCHP_BSPI_BSPI_FLASH_UPPER_ADDR_BYTE_reserved0_SHIFT 0
-
-/***************************************************************************
- *BSPI_XOR_VALUE - BSPI FLASH XOR Value Register
- ***************************************************************************/
-/* BSPI :: BSPI_XOR_VALUE :: bspi_xor_value [31:20] */
-#define BCHP_BSPI_BSPI_XOR_VALUE_bspi_xor_value_MASK 0xfff00000
-#define BCHP_BSPI_BSPI_XOR_VALUE_bspi_xor_value_SHIFT 20
-#define BCHP_BSPI_BSPI_XOR_VALUE_bspi_xor_value_DEFAULT 0x00000e00
-
-/* BSPI :: BSPI_XOR_VALUE :: reserved0 [19:00] */
-#define BCHP_BSPI_BSPI_XOR_VALUE_reserved0_MASK 0x000fffff
-#define BCHP_BSPI_BSPI_XOR_VALUE_reserved0_SHIFT 0
-
-/***************************************************************************
- *BSPI_XOR_ENABLE - BSPI FLASH XOR Enable Register
- ***************************************************************************/
-/* BSPI :: BSPI_XOR_ENABLE :: reserved0 [31:01] */
-#define BCHP_BSPI_BSPI_XOR_ENABLE_reserved0_MASK 0xfffffffe
-#define BCHP_BSPI_BSPI_XOR_ENABLE_reserved0_SHIFT 1
-
-/* BSPI :: BSPI_XOR_ENABLE :: bspi_xor_enable [00:00] */
-#define BCHP_BSPI_BSPI_XOR_ENABLE_bspi_xor_enable_MASK 0x00000001
-#define BCHP_BSPI_BSPI_XOR_ENABLE_bspi_xor_enable_SHIFT 0
-#define BCHP_BSPI_BSPI_XOR_ENABLE_bspi_xor_enable_DEFAULT 0x00000001
-
-/***************************************************************************
- *BSPI_PIO_MODE_ENABLE - BSPI Pin Programmed IO Mode Enable Register
- ***************************************************************************/
-/* BSPI :: BSPI_PIO_MODE_ENABLE :: reserved0 [31:01] */
-#define BCHP_BSPI_BSPI_PIO_MODE_ENABLE_reserved0_MASK 0xfffffffe
-#define BCHP_BSPI_BSPI_PIO_MODE_ENABLE_reserved0_SHIFT 1
-
-/* BSPI :: BSPI_PIO_MODE_ENABLE :: bspi_pio_mode [00:00] */
-#define BCHP_BSPI_BSPI_PIO_MODE_ENABLE_bspi_pio_mode_MASK 0x00000001
-#define BCHP_BSPI_BSPI_PIO_MODE_ENABLE_bspi_pio_mode_SHIFT 0
-#define BCHP_BSPI_BSPI_PIO_MODE_ENABLE_bspi_pio_mode_DEFAULT 0x00000000
-
-/***************************************************************************
- *BSPI_PIO_IODIR - BSPI Pin Programmed IO Mode Direction Register
- ***************************************************************************/
-/* BSPI :: BSPI_PIO_IODIR :: reserved0 [31:03] */
-#define BCHP_BSPI_BSPI_PIO_IODIR_reserved0_MASK 0xfffffff8
-#define BCHP_BSPI_BSPI_PIO_IODIR_reserved0_SHIFT 3
-
-/* BSPI :: BSPI_PIO_IODIR :: bspi_pio_dir [02:00] */
-#define BCHP_BSPI_BSPI_PIO_IODIR_bspi_pio_dir_MASK 0x00000007
-#define BCHP_BSPI_BSPI_PIO_IODIR_bspi_pio_dir_SHIFT 0
-#define BCHP_BSPI_BSPI_PIO_IODIR_bspi_pio_dir_DEFAULT 0x00000003
-
-/***************************************************************************
- *BSPI_PIO_DATA - BSPI Pin Programmed IO Mode Data Register
- ***************************************************************************/
-/* BSPI :: BSPI_PIO_DATA :: reserved0 [31:03] */
-#define BCHP_BSPI_BSPI_PIO_DATA_reserved0_MASK 0xfffffff8
-#define BCHP_BSPI_BSPI_PIO_DATA_reserved0_SHIFT 3
-
-/* BSPI :: BSPI_PIO_DATA :: bspi_pio_data [02:00] */
-#define BCHP_BSPI_BSPI_PIO_DATA_bspi_pio_data_MASK 0x00000007
-#define BCHP_BSPI_BSPI_PIO_DATA_bspi_pio_data_SHIFT 0
-#define BCHP_BSPI_BSPI_PIO_DATA_bspi_pio_data_DEFAULT 0x00000000
-
-#endif /* #ifndef BCHP_BSPI_H__ */
-
-/* End of File */
diff --git a/include/linux/brcmstb/7439a0/bchp_bspi_raf.h b/include/linux/brcmstb/7439a0/bchp_bspi_raf.h
deleted file mode 100644
index 21fadaa..0000000
--- a/include/linux/brcmstb/7439a0/bchp_bspi_raf.h
+++ /dev/null
@@ -1,160 +0,0 @@
-/***************************************************************************
- * Copyright (c) 1999-2012, Broadcom Corporation
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
- *
- * Module Description:
- * DO NOT EDIT THIS FILE DIRECTLY
- *
- * This module was generated magically with RDB from a source description
- * file. You must edit the source file for changes to be made to this file.
- *
- *
- * Date: Generated on Wed Oct 17 03:11:33 2012
- * MD5 Checksum d41d8cd98f00b204e9800998ecf8427e
- *
- * Compiled with: RDB Utility combo_header.pl
- * RDB Parser 3.0
- * unknown unknown
- * Perl Interpreter 5.008008
- * Operating System linux
- *
- * Revision History:
- *
- * $brcm_Log: $
- *
- ***************************************************************************/
-
-#ifndef BCHP_BSPI_RAF_H__
-#define BCHP_BSPI_RAF_H__
-
-/***************************************************************************
- *BSPI_RAF - Public Linear Read BSPI Pipe Registers
- ***************************************************************************/
-#define BCHP_BSPI_RAF_START_ADDR 0x00443300 /* Physical Starting Address Location in Flash device */
-#define BCHP_BSPI_RAF_NUM_WORDS 0x00443304 /* Number of Words to be fetched */
-#define BCHP_BSPI_RAF_CTRL 0x00443308 /* RAF Session Control Register */
-#define BCHP_BSPI_RAF_FULLNESS 0x0044330c /* Fullness indicator for the read ahead buffer */
-#define BCHP_BSPI_RAF_WATERMARK 0x00443310 /* Watermark level in the read ahead buffer that triggers an interrupt */
-#define BCHP_BSPI_RAF_STATUS 0x00443314 /* Linear Read Status Register */
-#define BCHP_BSPI_RAF_READ_DATA 0x00443318 /* Read data from Raf-buffer */
-#define BCHP_BSPI_RAF_WORD_CNT 0x0044331c /* Current number of words fetched from Flash */
-#define BCHP_BSPI_RAF_CURR_ADDR 0x00443320 /* Current read address for the linear read session */
-
-/***************************************************************************
- *START_ADDR - Physical Starting Address Location in Flash device
- ***************************************************************************/
-/* BSPI_RAF :: START_ADDR :: START_ADDR [31:00] */
-#define BCHP_BSPI_RAF_START_ADDR_START_ADDR_MASK 0xffffffff
-#define BCHP_BSPI_RAF_START_ADDR_START_ADDR_SHIFT 0
-#define BCHP_BSPI_RAF_START_ADDR_START_ADDR_DEFAULT 0x00000000
-
-/***************************************************************************
- *NUM_WORDS - Number of Words to be fetched
- ***************************************************************************/
-/* BSPI_RAF :: NUM_WORDS :: NumWords [31:00] */
-#define BCHP_BSPI_RAF_NUM_WORDS_NumWords_MASK 0xffffffff
-#define BCHP_BSPI_RAF_NUM_WORDS_NumWords_SHIFT 0
-#define BCHP_BSPI_RAF_NUM_WORDS_NumWords_DEFAULT 0x00000000
-
-/***************************************************************************
- *CTRL - RAF Session Control Register
- ***************************************************************************/
-/* BSPI_RAF :: CTRL :: reserved0 [31:02] */
-#define BCHP_BSPI_RAF_CTRL_reserved0_MASK 0xfffffffc
-#define BCHP_BSPI_RAF_CTRL_reserved0_SHIFT 2
-
-/* BSPI_RAF :: CTRL :: CLEAR [01:01] */
-#define BCHP_BSPI_RAF_CTRL_CLEAR_MASK 0x00000002
-#define BCHP_BSPI_RAF_CTRL_CLEAR_SHIFT 1
-#define BCHP_BSPI_RAF_CTRL_CLEAR_DEFAULT 0x00000000
-
-/* BSPI_RAF :: CTRL :: START [00:00] */
-#define BCHP_BSPI_RAF_CTRL_START_MASK 0x00000001
-#define BCHP_BSPI_RAF_CTRL_START_SHIFT 0
-#define BCHP_BSPI_RAF_CTRL_START_DEFAULT 0x00000000
-
-/***************************************************************************
- *FULLNESS - Fullness indicator for the read ahead buffer
- ***************************************************************************/
-/* BSPI_RAF :: FULLNESS :: reserved0 [31:07] */
-#define BCHP_BSPI_RAF_FULLNESS_reserved0_MASK 0xffffff80
-#define BCHP_BSPI_RAF_FULLNESS_reserved0_SHIFT 7
-
-/* BSPI_RAF :: FULLNESS :: FULLNESS [06:00] */
-#define BCHP_BSPI_RAF_FULLNESS_FULLNESS_MASK 0x0000007f
-#define BCHP_BSPI_RAF_FULLNESS_FULLNESS_SHIFT 0
-#define BCHP_BSPI_RAF_FULLNESS_FULLNESS_DEFAULT 0x00000000
-
-/***************************************************************************
- *WATERMARK - Watermark level in the read ahead buffer that triggers an interrupt
- ***************************************************************************/
-/* BSPI_RAF :: WATERMARK :: reserved0 [31:02] */
-#define BCHP_BSPI_RAF_WATERMARK_reserved0_MASK 0xfffffffc
-#define BCHP_BSPI_RAF_WATERMARK_reserved0_SHIFT 2
-
-/* BSPI_RAF :: WATERMARK :: FULLNESS_WATERMARK [01:00] */
-#define BCHP_BSPI_RAF_WATERMARK_FULLNESS_WATERMARK_MASK 0x00000003
-#define BCHP_BSPI_RAF_WATERMARK_FULLNESS_WATERMARK_SHIFT 0
-#define BCHP_BSPI_RAF_WATERMARK_FULLNESS_WATERMARK_DEFAULT 0x00000000
-
-/***************************************************************************
- *STATUS - Linear Read Status Register
- ***************************************************************************/
-/* BSPI_RAF :: STATUS :: reserved0 [31:03] */
-#define BCHP_BSPI_RAF_STATUS_reserved0_MASK 0xfffffff8
-#define BCHP_BSPI_RAF_STATUS_reserved0_SHIFT 3
-
-/* BSPI_RAF :: STATUS :: FIFO_FULL [02:02] */
-#define BCHP_BSPI_RAF_STATUS_FIFO_FULL_MASK 0x00000004
-#define BCHP_BSPI_RAF_STATUS_FIFO_FULL_SHIFT 2
-#define BCHP_BSPI_RAF_STATUS_FIFO_FULL_DEFAULT 0x00000000
-
-/* BSPI_RAF :: STATUS :: FIFO_EMPTY [01:01] */
-#define BCHP_BSPI_RAF_STATUS_FIFO_EMPTY_MASK 0x00000002
-#define BCHP_BSPI_RAF_STATUS_FIFO_EMPTY_SHIFT 1
-#define BCHP_BSPI_RAF_STATUS_FIFO_EMPTY_DEFAULT 0x00000001
-
-/* BSPI_RAF :: STATUS :: SESSION_BUSY [00:00] */
-#define BCHP_BSPI_RAF_STATUS_SESSION_BUSY_MASK 0x00000001
-#define BCHP_BSPI_RAF_STATUS_SESSION_BUSY_SHIFT 0
-#define BCHP_BSPI_RAF_STATUS_SESSION_BUSY_DEFAULT 0x00000000
-
-/***************************************************************************
- *READ_DATA - Read data from Raf-buffer
- ***************************************************************************/
-/* BSPI_RAF :: READ_DATA :: DATA [31:00] */
-#define BCHP_BSPI_RAF_READ_DATA_DATA_MASK 0xffffffff
-#define BCHP_BSPI_RAF_READ_DATA_DATA_SHIFT 0
-#define BCHP_BSPI_RAF_READ_DATA_DATA_DEFAULT 0x00000000
-
-/***************************************************************************
- *WORD_CNT - Current number of words fetched from Flash
- ***************************************************************************/
-/* BSPI_RAF :: WORD_CNT :: CURRENT_WORD_COUNT [31:00] */
-#define BCHP_BSPI_RAF_WORD_CNT_CURRENT_WORD_COUNT_MASK 0xffffffff
-#define BCHP_BSPI_RAF_WORD_CNT_CURRENT_WORD_COUNT_SHIFT 0
-#define BCHP_BSPI_RAF_WORD_CNT_CURRENT_WORD_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *CURR_ADDR - Current read address for the linear read session
- ***************************************************************************/
-/* BSPI_RAF :: CURR_ADDR :: CURRENT_ADDRESS [31:00] */
-#define BCHP_BSPI_RAF_CURR_ADDR_CURRENT_ADDRESS_MASK 0xffffffff
-#define BCHP_BSPI_RAF_CURR_ADDR_CURRENT_ADDRESS_SHIFT 0
-#define BCHP_BSPI_RAF_CURR_ADDR_CURRENT_ADDRESS_DEFAULT 0x00000000
-
-#endif /* #ifndef BCHP_BSPI_RAF_H__ */
-
-/* End of File */
diff --git a/include/linux/brcmstb/7439a0/bchp_clkgen.h b/include/linux/brcmstb/7439a0/bchp_clkgen.h
deleted file mode 100644
index d11df64..0000000
--- a/include/linux/brcmstb/7439a0/bchp_clkgen.h
+++ /dev/null
@@ -1,7808 +0,0 @@
-/***************************************************************************
- * Copyright (c) 1999-2014, Broadcom Corporation
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
- *
- * Module Description:
- * DO NOT EDIT THIS FILE DIRECTLY
- *
- * This module was generated magically with RDB from a source description
- * file. You must edit the source file for changes to be made to this file.
- *
- *
- * Date: Generated on Wed Sep 3 14:30:55 2014
- * Full Compile MD5 Checksum edbc259d5ef948d04693ec04bc4d44b4
- * (minus title and desc)
- * MD5 Checksum de2524c7728bb833dc65ac44b70daaa5
- *
- * Compiled with: RDB Utility combo_header.pl
- * RDB Parser 3.0
- * unknown unknown
- * Perl Interpreter 5.008005
- * Operating System linux
- *
- * Revision History:
- *
- * $brcm_Log: $
- *
- ***************************************************************************/
-
-#ifndef BCHP_CLKGEN_H__
-#define BCHP_CLKGEN_H__
-
-/***************************************************************************
- *CLKGEN - clkgen registers
- ***************************************************************************/
-#define BCHP_CLKGEN_PLL_CPU_PLL_CHANNEL_CTRL_CH_0 0x004e0000 /* PLL CHANNEL control CH 0 */
-#define BCHP_CLKGEN_PLL_CPU_PLL_CHANNEL_CTRL_CH_1 0x004e0004 /* PLL CHANNEL control CH 1 */
-#define BCHP_CLKGEN_PLL_CPU_PLL_DIV 0x004e0008 /* Pre multiplier */
-#define BCHP_CLKGEN_PLL_CPU_PLL_FRAC 0x004e000c /* Fractional */
-#define BCHP_CLKGEN_PLL_CPU_PLL_GAIN 0x004e0010 /* PLL GAIN */
-#define BCHP_CLKGEN_PLL_CPU_PLL_LDO_PWRON 0x004e0014 /* LDO Power on */
-#define BCHP_CLKGEN_PLL_CPU_PLL_LOCK_STATUS 0x004e0018 /* Lock Status */
-#define BCHP_CLKGEN_PLL_CPU_PLL_MISC 0x004e001c /* Mscellaneous control bus. */
-#define BCHP_CLKGEN_PLL_CPU_PLL_MISC2 0x004e0020 /* Mscellaneous control bus continued. */
-#define BCHP_CLKGEN_PLL_CPU_PLL_PWRON 0x004e0024 /* Poweron */
-#define BCHP_CLKGEN_PLL_CPU_PLL_RESET 0x004e0028 /* Resets */
-#define BCHP_CLKGEN_PLL_CPU_PLL_SSC_MODE_CONTROL_HIGH 0x004e002c /* Higher bits of Spread Spectrum mode control */
-#define BCHP_CLKGEN_PLL_CPU_PLL_SSC_MODE_CONTROL_LOW 0x004e0030 /* Lower bits of Spread Spectrum mode control */
-#define BCHP_CLKGEN_PLL_CPU_PLL_STATUS 0x004e0034 /* Status */
-#define BCHP_CLKGEN_PLL_HVD_PLL_CHANNEL_CTRL_CH_0 0x004e0038 /* PLL CHANNEL control CH 0 */
-#define BCHP_CLKGEN_PLL_HVD_PLL_CHANNEL_CTRL_CH_1 0x004e003c /* PLL CHANNEL control CH 1 */
-#define BCHP_CLKGEN_PLL_HVD_PLL_CHANNEL_CTRL_CH_4 0x004e0040 /* PLL CHANNEL control CH 4 */
-#define BCHP_CLKGEN_PLL_HVD_PLL_DIV 0x004e0044 /* Pre multiplier */
-#define BCHP_CLKGEN_PLL_HVD_PLL_FRAC 0x004e0048 /* Fractional */
-#define BCHP_CLKGEN_PLL_HVD_PLL_GAIN 0x004e004c /* PLL GAIN */
-#define BCHP_CLKGEN_PLL_HVD_PLL_LDO_PWRON 0x004e0050 /* LDO Power on */
-#define BCHP_CLKGEN_PLL_HVD_PLL_LOCK_STATUS 0x004e0054 /* Lock Status */
-#define BCHP_CLKGEN_PLL_HVD_PLL_MISC 0x004e0058 /* Mscellaneous control bus. */
-#define BCHP_CLKGEN_PLL_HVD_PLL_MISC2 0x004e005c /* Mscellaneous control bus continued. */
-#define BCHP_CLKGEN_PLL_HVD_PLL_PWRON 0x004e0060 /* Poweron */
-#define BCHP_CLKGEN_PLL_HVD_PLL_RESET 0x004e0064 /* Resets */
-#define BCHP_CLKGEN_PLL_HVD_PLL_SSC_MODE_CONTROL_HIGH 0x004e0068 /* Higher bits of Spread Spectrum mode control */
-#define BCHP_CLKGEN_PLL_HVD_PLL_SSC_MODE_CONTROL_LOW 0x004e006c /* Lower bits of Spread Spectrum mode control */
-#define BCHP_CLKGEN_PLL_HVD_PLL_STATUS 0x004e0070 /* Status */
-#define BCHP_CLKGEN_PLL_LC_PLL_CHANNEL_CTRL_CH_0 0x004e0074 /* PLL CHANNEL control CH 0 */
-#define BCHP_CLKGEN_PLL_LC_PLL_CHANNEL_CTRL_CH_1 0x004e0078 /* PLL CHANNEL control CH 1 */
-#define BCHP_CLKGEN_PLL_LC_PLL_CHANNEL_CTRL_CH_2 0x004e007c /* PLL CHANNEL control CH 2 */
-#define BCHP_CLKGEN_PLL_LC_PLL_CHANNEL_CTRL_CH_4 0x004e0080 /* PLL CHANNEL control CH 4 */
-#define BCHP_CLKGEN_PLL_LC_PLL_CHANNEL_CTRL_CH_5 0x004e0084 /* PLL CHANNEL control CH 5 */
-#define BCHP_CLKGEN_PLL_LC_PLL_CONTROL 0x004e0088 /* Miscellaneous Controls */
-#define BCHP_CLKGEN_PLL_LC_PLL_DIV 0x004e008c /* Pre multiplier */
-#define BCHP_CLKGEN_PLL_LC_PLL_GAIN 0x004e0090 /* PLL GAIN */
-#define BCHP_CLKGEN_PLL_LC_PLL_HOLD_CH_ALL 0x004e0094 /* Hold PLL all channels */
-#define BCHP_CLKGEN_PLL_LC_PLL_LDO_CTRL 0x004e0098 /* Ldo voltage control */
-#define BCHP_CLKGEN_PLL_LC_PLL_LDO_PWRON 0x004e009c /* LDO Power on */
-#define BCHP_CLKGEN_PLL_LC_PLL_LOCK_STATUS 0x004e00a0 /* Lock Status */
-#define BCHP_CLKGEN_PLL_LC_PLL_MISC 0x004e00a4 /* Mscellaneous control bus. */
-#define BCHP_CLKGEN_PLL_LC_PLL_MISC2 0x004e00a8 /* Mscellaneous control bus continued. */
-#define BCHP_CLKGEN_PLL_LC_PLL_OUTSEL_SEL 0x004e00ac /* selection of the output clock from the PLL core */
-#define BCHP_CLKGEN_PLL_LC_PLL_PWRON 0x004e00b0 /* Poweron */
-#define BCHP_CLKGEN_PLL_LC_PLL_RESET 0x004e00b4 /* Resets */
-#define BCHP_CLKGEN_PLL_LC_PLL_STATUS 0x004e00b8 /* Status */
-#define BCHP_CLKGEN_PLL_LC_PLL_TEST 0x004e00bc /* enable and selection pf PLL test */
-#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_0 0x004e00c0 /* PLL CHANNEL control CH 0 */
-#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_1 0x004e00c4 /* PLL CHANNEL control CH 1 */
-#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_2 0x004e00c8 /* PLL CHANNEL control CH 2 */
-#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_3 0x004e00cc /* PLL CHANNEL control CH 3 */
-#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_4 0x004e00d0 /* PLL CHANNEL control CH 4 */
-#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_5 0x004e00d4 /* PLL CHANNEL control CH 5 */
-#define BCHP_CLKGEN_PLL_MOCA_PLL_DIV 0x004e00d8 /* Pre multiplier */
-#define BCHP_CLKGEN_PLL_MOCA_PLL_GAIN 0x004e00dc /* PLL GAIN */
-#define BCHP_CLKGEN_PLL_MOCA_PLL_LDO_PWRON 0x004e00e0 /* LDO Power on */
-#define BCHP_CLKGEN_PLL_MOCA_PLL_LOCK_STATUS 0x004e00e4 /* Lock Status */
-#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC 0x004e00e8 /* Mscellaneous control bus. */
-#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC2 0x004e00ec /* Mscellaneous control bus continued. */
-#define BCHP_CLKGEN_PLL_MOCA_PLL_PWRON 0x004e00f0 /* Poweron */
-#define BCHP_CLKGEN_PLL_MOCA_PLL_RESET 0x004e00f4 /* Resets */
-#define BCHP_CLKGEN_PLL_MOCA_PLL_SSC_MODE_CONTROL_HIGH 0x004e00f8 /* Higher bits of Spread Spectrum mode control */
-#define BCHP_CLKGEN_PLL_MOCA_PLL_SSC_MODE_CONTROL_LOW 0x004e00fc /* Lower bits of Spread Spectrum mode control */
-#define BCHP_CLKGEN_PLL_MOCA_PLL_STATUS 0x004e0100 /* Status */
-#define BCHP_CLKGEN_PLL_NETWORK_PLL_CHANNEL_CTRL_CH_0 0x004e0104 /* PLL CHANNEL control CH 0 */
-#define BCHP_CLKGEN_PLL_NETWORK_PLL_CHANNEL_CTRL_CH_1 0x004e0108 /* PLL CHANNEL control CH 1 */
-#define BCHP_CLKGEN_PLL_NETWORK_PLL_CHANNEL_CTRL_CH_2 0x004e010c /* PLL CHANNEL control CH 2 */
-#define BCHP_CLKGEN_PLL_NETWORK_PLL_DIV 0x004e0110 /* Pre multiplier */
-#define BCHP_CLKGEN_PLL_NETWORK_PLL_GAIN 0x004e0114 /* PLL GAIN */
-#define BCHP_CLKGEN_PLL_NETWORK_PLL_LDO_PWRON 0x004e0118 /* LDO Power on */
-#define BCHP_CLKGEN_PLL_NETWORK_PLL_LOCK_STATUS 0x004e011c /* Lock Status */
-#define BCHP_CLKGEN_PLL_NETWORK_PLL_MISC 0x004e0120 /* Mscellaneous control bus. */
-#define BCHP_CLKGEN_PLL_NETWORK_PLL_MISC2 0x004e0124 /* Mscellaneous control bus continued. */
-#define BCHP_CLKGEN_PLL_NETWORK_PLL_PWRON 0x004e0128 /* Poweron */
-#define BCHP_CLKGEN_PLL_NETWORK_PLL_RESET 0x004e012c /* Resets */
-#define BCHP_CLKGEN_PLL_NETWORK_PLL_SSC_MODE_CONTROL_HIGH 0x004e0130 /* Higher bits of Spread Spectrum mode control */
-#define BCHP_CLKGEN_PLL_NETWORK_PLL_SSC_MODE_CONTROL_LOW 0x004e0134 /* Lower bits of Spread Spectrum mode control */
-#define BCHP_CLKGEN_PLL_NETWORK_PLL_STATUS 0x004e0138 /* Status */
-#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_0 0x004e013c /* PLL CHANNEL control CH 0 */
-#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_3 0x004e0140 /* PLL CHANNEL control CH 3 */
-#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_4 0x004e0144 /* PLL CHANNEL control CH 4 */
-#define BCHP_CLKGEN_PLL_RAAGA_PLL_DIV 0x004e0148 /* Pre multiplier */
-#define BCHP_CLKGEN_PLL_RAAGA_PLL_GAIN 0x004e014c /* PLL GAIN */
-#define BCHP_CLKGEN_PLL_RAAGA_PLL_LDO_PWRON 0x004e0150 /* LDO Power on */
-#define BCHP_CLKGEN_PLL_RAAGA_PLL_LOCK_STATUS 0x004e0154 /* Lock Status */
-#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC 0x004e0158 /* Mscellaneous control bus. */
-#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC2 0x004e015c /* Mscellaneous control bus continued. */
-#define BCHP_CLKGEN_PLL_RAAGA_PLL_PWRON 0x004e0160 /* Poweron */
-#define BCHP_CLKGEN_PLL_RAAGA_PLL_RESET 0x004e0164 /* Resets */
-#define BCHP_CLKGEN_PLL_RAAGA_PLL_SSC_MODE_CONTROL_HIGH 0x004e0168 /* Higher bits of Spread Spectrum mode control */
-#define BCHP_CLKGEN_PLL_RAAGA_PLL_SSC_MODE_CONTROL_LOW 0x004e016c /* Lower bits of Spread Spectrum mode control */
-#define BCHP_CLKGEN_PLL_RAAGA_PLL_STATUS 0x004e0170 /* Status */
-#define BCHP_CLKGEN_PLL_SC0_PLL_CHANNEL_CTRL_CH_0 0x004e0174 /* PLL CHANNEL control CH 0 */
-#define BCHP_CLKGEN_PLL_SC0_PLL_DIV 0x004e0178 /* Pre multiplier */
-#define BCHP_CLKGEN_PLL_SC0_PLL_FRAC 0x004e017c /* Fractional */
-#define BCHP_CLKGEN_PLL_SC0_PLL_GAIN 0x004e0180 /* PLL GAIN */
-#define BCHP_CLKGEN_PLL_SC0_PLL_LOCK_STATUS 0x004e0184 /* Lock Status */
-#define BCHP_CLKGEN_PLL_SC0_PLL_MISC 0x004e0188 /* Mscellaneous control bus. */
-#define BCHP_CLKGEN_PLL_SC0_PLL_MISC2 0x004e018c /* Mscellaneous control bus continued. */
-#define BCHP_CLKGEN_PLL_SC0_PLL_PWRON 0x004e0190 /* Poweron */
-#define BCHP_CLKGEN_PLL_SC0_PLL_RESET 0x004e0194 /* Resets */
-#define BCHP_CLKGEN_PLL_SC0_PLL_SSC_MODE_CONTROL_HIGH 0x004e0198 /* Higher bits of Spread Spectrum mode control */
-#define BCHP_CLKGEN_PLL_SC0_PLL_SSC_MODE_CONTROL_LOW 0x004e019c /* Lower bits of Spread Spectrum mode control */
-#define BCHP_CLKGEN_PLL_SC0_PLL_STATUS 0x004e01a0 /* Status */
-#define BCHP_CLKGEN_PLL_SC1_PLL_CHANNEL_CTRL_CH_0 0x004e01a4 /* PLL CHANNEL control CH 0 */
-#define BCHP_CLKGEN_PLL_SC1_PLL_DIV 0x004e01a8 /* Pre multiplier */
-#define BCHP_CLKGEN_PLL_SC1_PLL_FRAC 0x004e01ac /* Fractional */
-#define BCHP_CLKGEN_PLL_SC1_PLL_GAIN 0x004e01b0 /* PLL GAIN */
-#define BCHP_CLKGEN_PLL_SC1_PLL_LOCK_STATUS 0x004e01b4 /* Lock Status */
-#define BCHP_CLKGEN_PLL_SC1_PLL_MISC 0x004e01b8 /* Mscellaneous control bus. */
-#define BCHP_CLKGEN_PLL_SC1_PLL_MISC2 0x004e01bc /* Mscellaneous control bus continued. */
-#define BCHP_CLKGEN_PLL_SC1_PLL_PWRON 0x004e01c0 /* Poweron */
-#define BCHP_CLKGEN_PLL_SC1_PLL_RESET 0x004e01c4 /* Resets */
-#define BCHP_CLKGEN_PLL_SC1_PLL_SSC_MODE_CONTROL_HIGH 0x004e01c8 /* Higher bits of Spread Spectrum mode control */
-#define BCHP_CLKGEN_PLL_SC1_PLL_SSC_MODE_CONTROL_LOW 0x004e01cc /* Lower bits of Spread Spectrum mode control */
-#define BCHP_CLKGEN_PLL_SC1_PLL_STATUS 0x004e01d0 /* Status */
-#define BCHP_CLKGEN_PLL_SYS0_PLL_BG_PWRON 0x004e01d4 /* Bandgap Power on */
-#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_0 0x004e01d8 /* PLL CHANNEL control CH 0 */
-#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_1 0x004e01dc /* PLL CHANNEL control CH 1 */
-#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2 0x004e01e0 /* PLL CHANNEL control CH 2 */
-#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3 0x004e01e4 /* PLL CHANNEL control CH 3 */
-#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_4 0x004e01e8 /* PLL CHANNEL control CH 4 */
-#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_5 0x004e01ec /* PLL CHANNEL control CH 5 */
-#define BCHP_CLKGEN_PLL_SYS0_PLL_DIV 0x004e01f0 /* Pre multiplier */
-#define BCHP_CLKGEN_PLL_SYS0_PLL_GAIN 0x004e01f4 /* PLL GAIN */
-#define BCHP_CLKGEN_PLL_SYS0_PLL_HOLD_CH_ALL 0x004e01f8 /* Hold PLL all channels */
-#define BCHP_CLKGEN_PLL_SYS0_PLL_LDO_CTRL 0x004e01fc /* Ldo voltage control */
-#define BCHP_CLKGEN_PLL_SYS0_PLL_LDO_PWRON 0x004e0200 /* LDO Power on */
-#define BCHP_CLKGEN_PLL_SYS0_PLL_LOCK_STATUS 0x004e0204 /* Lock Status */
-#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC 0x004e0208 /* Mscellaneous control bus. */
-#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC2 0x004e020c /* Mscellaneous control bus continued. */
-#define BCHP_CLKGEN_PLL_SYS0_PLL_PWRON 0x004e0210 /* Poweron */
-#define BCHP_CLKGEN_PLL_SYS0_PLL_RESET 0x004e0214 /* Resets */
-#define BCHP_CLKGEN_PLL_SYS0_PLL_SSC_MODE_CONTROL_HIGH 0x004e0218 /* Higher bits of Spread Spectrum mode control */
-#define BCHP_CLKGEN_PLL_SYS0_PLL_SSC_MODE_CONTROL_LOW 0x004e021c /* Lower bits of Spread Spectrum mode control */
-#define BCHP_CLKGEN_PLL_SYS0_PLL_STATUS 0x004e0220 /* Status */
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_BG_PWRON 0x004e0224 /* Bandgap Power on */
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_CHANNEL_CTRL_CH_0 0x004e0228 /* PLL CHANNEL control CH 0 */
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_CHANNEL_CTRL_CH_1 0x004e022c /* PLL CHANNEL control CH 1 */
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_CHANNEL_CTRL_CH_2 0x004e0230 /* PLL CHANNEL control CH 2 */
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_DIV 0x004e0234 /* Pre multiplier */
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_FRAC 0x004e0238 /* Fractional */
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_GAIN 0x004e023c /* PLL GAIN */
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_HOLD_CH_ALL 0x004e0240 /* Hold PLL all channels */
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_LDO_CTRL 0x004e0244 /* Ldo voltage control */
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_LDO_PWRON 0x004e0248 /* LDO Power on */
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_LOCK_STATUS 0x004e024c /* Lock Status */
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_MISC 0x004e0250 /* Mscellaneous control bus. */
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_MISC2 0x004e0254 /* Mscellaneous control bus continued. */
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_PWRON 0x004e0258 /* Poweron */
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_RESET 0x004e025c /* Resets */
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_SSC_MODE_CONTROL_HIGH 0x004e0260 /* Higher bits of Spread Spectrum mode control */
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_SSC_MODE_CONTROL_LOW 0x004e0264 /* Lower bits of Spread Spectrum mode control */
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_STATUS 0x004e0268 /* Status */
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_BG_PWRON 0x004e026c /* Bandgap Power on */
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_CHANNEL_CTRL_CH_0 0x004e0270 /* PLL CHANNEL control CH 0 */
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_CHANNEL_CTRL_CH_1 0x004e0274 /* PLL CHANNEL control CH 1 */
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_CHANNEL_CTRL_CH_2 0x004e0278 /* PLL CHANNEL control CH 2 */
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_DIV 0x004e027c /* Pre multiplier */
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_FRAC 0x004e0280 /* Fractional */
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_GAIN 0x004e0284 /* PLL GAIN */
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_HOLD_CH_ALL 0x004e0288 /* Hold PLL all channels */
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_LDO_CTRL 0x004e028c /* Ldo voltage control */
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_LDO_PWRON 0x004e0290 /* LDO Power on */
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_LOCK_STATUS 0x004e0294 /* Lock Status */
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_MISC 0x004e0298 /* Mscellaneous control bus. */
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_MISC2 0x004e029c /* Mscellaneous control bus continued. */
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_PWRON 0x004e02a0 /* Poweron */
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_RESET 0x004e02a4 /* Resets */
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_SSC_MODE_CONTROL_HIGH 0x004e02a8 /* Higher bits of Spread Spectrum mode control */
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_SSC_MODE_CONTROL_LOW 0x004e02ac /* Lower bits of Spread Spectrum mode control */
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_STATUS 0x004e02b0 /* Status */
-#define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_0 0x004e02b4 /* PLL CHANNEL control CH 0 */
-#define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_1 0x004e02b8 /* PLL CHANNEL control CH 1 */
-#define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_2 0x004e02bc /* PLL CHANNEL control CH 2 */
-#define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_3 0x004e02c0 /* PLL CHANNEL control CH 3 */
-#define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_4 0x004e02c4 /* PLL CHANNEL control CH 4 */
-#define BCHP_CLKGEN_PLL_XPT_PLL_DIV 0x004e02c8 /* Pre multiplier */
-#define BCHP_CLKGEN_PLL_XPT_PLL_GAIN 0x004e02cc /* PLL GAIN */
-#define BCHP_CLKGEN_PLL_XPT_PLL_LDO_PWRON 0x004e02d0 /* LDO Power on */
-#define BCHP_CLKGEN_PLL_XPT_PLL_LOCK_STATUS 0x004e02d4 /* Lock Status */
-#define BCHP_CLKGEN_PLL_XPT_PLL_MISC 0x004e02d8 /* Mscellaneous control bus. */
-#define BCHP_CLKGEN_PLL_XPT_PLL_MISC2 0x004e02dc /* Mscellaneous control bus continued. */
-#define BCHP_CLKGEN_PLL_XPT_PLL_PWRON 0x004e02e0 /* Poweron */
-#define BCHP_CLKGEN_PLL_XPT_PLL_RESET 0x004e02e4 /* Resets */
-#define BCHP_CLKGEN_PLL_XPT_PLL_SSC_MODE_CONTROL_HIGH 0x004e02e8 /* Higher bits of Spread Spectrum mode control */
-#define BCHP_CLKGEN_PLL_XPT_PLL_SSC_MODE_CONTROL_LOW 0x004e02ec /* Lower bits of Spread Spectrum mode control */
-#define BCHP_CLKGEN_PLL_XPT_PLL_STATUS 0x004e02f0 /* Status */
-#define BCHP_CLKGEN_ANA_QDAC_TS28HPM_6MX_2MR_FC_H_E_INST_CLOCK_DISABLE 0x004e02f4 /* Disable ANA_QDAC_TS28HPM_6MX_2MR_FC_H_E_INST's clocks */
-#define BCHP_CLKGEN_ANA_QDAC_TS28HPM_6MX_2MR_FC_H_E_INST_CLOCK_DISABLE_STATUS 0x004e02f8 /* Clock Disable Status */
-#define BCHP_CLKGEN_ANA_SW_AVS_TS28HPM_6MX_2MR_FC_H_E_INST_CLOCK_DISABLE 0x004e02fc /* Disable ANA_SW_AVS_TS28HPM_6MX_2MR_FC_H_E_INST's clocks */
-#define BCHP_CLKGEN_ANA_SW_AVS_TS28HPM_6MX_2MR_FC_H_E_INST_CLOCK_DISABLE_STATUS 0x004e0300 /* Clock Disable Status */
-#define BCHP_CLKGEN_BVN_MVP_TOP_INST_CLOCK_ENABLE 0x004e0304 /* Bvn mvp top inst clock enable */
-#define BCHP_CLKGEN_BVN_MVP_TOP_INST_CLOCK_ENABLE_STATUS 0x004e0308 /* Clock Enable Status */
-#define BCHP_CLKGEN_BVN_TOP_INST_CLOCK_ENABLE 0x004e030c /* Bvn top inst clock enable */
-#define BCHP_CLKGEN_BVN_TOP_INST_CLOCK_ENABLE_STATUS 0x004e0310 /* Clock Enable Status */
-#define BCHP_CLKGEN_CLKGEN_CLOCK_DISABLE 0x004e0314 /* Disable CLKGEN's clocks */
-#define BCHP_CLKGEN_CLKGEN_CLOCK_DISABLE_STATUS 0x004e0318 /* Clock Disable Status */
-#define BCHP_CLKGEN_CLOCK_MONITOR_CONTROL 0x004e031c /* Clock Monitor Control */
-#define BCHP_CLKGEN_CLOCK_MONITOR_MAX_COUNT 0x004e0320 /* Clock Monitor Max Reference Count */
-#define BCHP_CLKGEN_CLOCK_MONITOR_REF_COUNTER 0x004e0324 /* Clock Monitor Reference Counter */
-#define BCHP_CLKGEN_CLOCK_MONITOR_REF_DONE 0x004e0328 /* Clock Monitor Reference Counter */
-#define BCHP_CLKGEN_CLOCK_MONITOR_VIEW_COUNTER 0x004e032c /* Clock Monitor View Counter */
-#define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_DISABLE 0x004e0330 /* Disable CORE_XPT_INST's clocks */
-#define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_DISABLE_STATUS 0x004e0334 /* Clock Disable Status */
-#define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_ENABLE 0x004e0338 /* Core xpt inst clock enable */
-#define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_ENABLE_STATUS 0x004e033c /* Clock Enable Status */
-#define BCHP_CLKGEN_CORE_XPT_INST_OBSERVE_CLOCK 0x004e0340 /* Core xpt inst observe clock */
-#define BCHP_CLKGEN_DISABLE_AVS_TOP_DURING_S2 0x004e0344 /* Disable AVS_TOP 54MHz clocks during S2 standby. */
-#define BCHP_CLKGEN_DISABLE_AVS_TOP_DURING_S2_SECURE 0x004e0348 /* Secure AVS_TOP clock disable. Set at start-up to guarantee AVS_TOP is clock gated in S2 standby. */
-#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_DISABLE 0x004e034c /* Disable DUAL_GENET_TOP_DUAL_RGMII_INST's clocks */
-#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_DISABLE_STATUS 0x004e0350 /* Clock Disable Status */
-#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE 0x004e0354 /* Dual genet top dual rgmii inst clock enable */
-#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET0 0x004e0358 /* Dual genet top dual rgmii inst clock enable genet0 */
-#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET0_STATUS 0x004e035c /* Clock Enable Status */
-#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET1 0x004e0360 /* Dual genet top dual rgmii inst clock enable genet1 */
-#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET1_STATUS 0x004e0364 /* Clock Enable Status */
-#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET2 0x004e0368 /* Dual genet top dual rgmii inst clock enable genet2 */
-#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET2_STATUS 0x004e036c /* Clock Enable Status */
-#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_STATUS 0x004e0370 /* Clock Enable Status */
-#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_SELECT_GENET0 0x004e0374 /* Dual genet top dual rgmii inst clock select genet0 */
-#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_SELECT_GENET1 0x004e0378 /* Dual genet top dual rgmii inst clock select genet1 */
-#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_OBSERVE_CLOCK 0x004e037c /* Dual genet top dual rgmii inst observe clock */
-#define BCHP_CLKGEN_DVP_HR_INST_CLOCK_DISABLE 0x004e0380 /* Disable DVP_HR_INST's clocks */
-#define BCHP_CLKGEN_DVP_HR_INST_CLOCK_DISABLE_STATUS 0x004e0384 /* Clock Disable Status */
-#define BCHP_CLKGEN_DVP_HR_INST_CLOCK_ENABLE 0x004e0388 /* Dvp hr inst clock enable */
-#define BCHP_CLKGEN_DVP_HR_INST_CLOCK_ENABLE0 0x004e038c /* Dvp hr inst clock enable0 */
-#define BCHP_CLKGEN_DVP_HR_INST_CLOCK_ENABLE0_STATUS 0x004e0390 /* Clock Enable Status */
-#define BCHP_CLKGEN_DVP_HR_INST_CLOCK_ENABLE_STATUS 0x004e0394 /* Clock Enable Status */
-#define BCHP_CLKGEN_DVP_HR_INST_OBSERVE_CLOCK 0x004e0398 /* Dvp hr inst observe clock */
-#define BCHP_CLKGEN_DVP_HT_DUAL_WRAPPER_INST_CLOCK_DISABLE 0x004e039c /* Disable DVP_HT_DUAL_WRAPPER_INST's clocks */
-#define BCHP_CLKGEN_DVP_HT_DUAL_WRAPPER_INST_CLOCK_DISABLE_STATUS 0x004e03a0 /* Clock Disable Status */
-#define BCHP_CLKGEN_DVP_HT_DUAL_WRAPPER_INST_CLOCK_ENABLE 0x004e03a4 /* Dvp ht dual wrapper inst clock enable */
-#define BCHP_CLKGEN_DVP_HT_DUAL_WRAPPER_INST_CLOCK_ENABLE_STATUS 0x004e03a8 /* Clock Enable Status */
-#define BCHP_CLKGEN_DVP_HT_DUAL_WRAPPER_INST_ENABLE 0x004e03ac /* Dvp ht dual wrapper inst enable */
-#define BCHP_CLKGEN_DVP_HT_DUAL_WRAPPER_INST_OBSERVE_CLOCK 0x004e03b0 /* Dvp ht dual wrapper inst observe clock */
-#define BCHP_CLKGEN_EAGLET_TOP_INST_CLOCK_DISABLE 0x004e03b4 /* Disable EAGLET_TOP_INST's clocks */
-#define BCHP_CLKGEN_EAGLET_TOP_INST_CLOCK_DISABLE_STATUS 0x004e03b8 /* Clock Disable Status */
-#define BCHP_CLKGEN_EAGLET_TOP_INST_CLOCK_ENABLE 0x004e03bc /* Eaglet top inst clock enable */
-#define BCHP_CLKGEN_EAGLET_TOP_INST_CLOCK_ENABLE_STATUS 0x004e03c0 /* Clock Enable Status */
-#define BCHP_CLKGEN_EGPHY28_1PORT_33V_90O_FC_INST_DIV5 0x004e03c4 /* Egphy28 1port 33v 90o fc inst div5 */
-#define BCHP_CLKGEN_EGPHY28_1PORT_33V_90O_FC_INST_SEL 0x004e03c8 /* Egphy28 1port 33v 90o fc inst sel */
-#define BCHP_CLKGEN_GRAPHICS_INST_ALT_CLOCK_ENABLE_M2MC 0x004e03cc /* Graphics inst alt clock enable m2mc */
-#define BCHP_CLKGEN_GRAPHICS_INST_CLOCK_ENABLE_M2MC 0x004e03d0 /* Graphics inst clock enable m2mc */
-#define BCHP_CLKGEN_GRAPHICS_INST_CLOCK_ENABLE_M2MC1 0x004e03d4 /* Graphics inst clock enable m2mc1 */
-#define BCHP_CLKGEN_GRAPHICS_INST_CLOCK_ENABLE_M2MC1_STATUS 0x004e03d8 /* Clock Enable Status */
-#define BCHP_CLKGEN_GRAPHICS_INST_CLOCK_ENABLE_M2MC_STATUS 0x004e03dc /* Clock Enable Status */
-#define BCHP_CLKGEN_GRAPHICS_INST_OBSERVE_CLOCK 0x004e03e0 /* Graphics inst observe clock */
-#define BCHP_CLKGEN_HIF_INST_CLOCK_DISABLE 0x004e03e4 /* Disable HIF_INST's clocks */
-#define BCHP_CLKGEN_HIF_INST_CLOCK_DISABLE_STATUS 0x004e03e8 /* Clock Disable Status */
-#define BCHP_CLKGEN_HIF_INST_CLOCK_ENABLE 0x004e03ec /* Hif inst clock enable */
-#define BCHP_CLKGEN_HIF_INST_CLOCK_ENABLE_STATUS 0x004e03f0 /* Clock Enable Status */
-#define BCHP_CLKGEN_HIF_INST_OBSERVE_CLOCK 0x004e03f4 /* Hif inst observe clock */
-#define BCHP_CLKGEN_HVD_SID0_TOP_INST_CLOCK_ENABLE 0x004e03f8 /* Hvd sid0 top inst clock enable */
-#define BCHP_CLKGEN_HVD_SID0_TOP_INST_CLOCK_ENABLE_SID 0x004e03fc /* Hvd sid0 top inst clock enable sid */
-#define BCHP_CLKGEN_HVD_SID0_TOP_INST_CLOCK_ENABLE_SID_STATUS 0x004e0400 /* Clock Enable Status */
-#define BCHP_CLKGEN_HVD_SID0_TOP_INST_CLOCK_ENABLE_STATUS 0x004e0404 /* Clock Enable Status */
-#define BCHP_CLKGEN_HVD_SID0_TOP_INST_OBSERVE_CLOCK 0x004e0408 /* Hvd sid0 top inst observe clock */
-#define BCHP_CLKGEN_INTERNAL_MUX_SELECT 0x004e040c /* Mux selects for Internal clocks */
-#define BCHP_CLKGEN_ITU656_0_MUX_SELECT 0x004e0410 /* Mux selects for itu656_0 clocks */
-#define BCHP_CLKGEN_MEMSYS_32_0_INST_CLOCK_ENABLE 0x004e0414 /* Memsys 32 0 inst clock enable */
-#define BCHP_CLKGEN_MEMSYS_32_0_INST_CLOCK_ENABLE_STATUS 0x004e0418 /* Clock Enable Status */
-#define BCHP_CLKGEN_MEMSYS_32_0_INST_OBSERVE_CLOCK 0x004e041c /* Memsys 32 0 inst observe clock */
-#define BCHP_CLKGEN_MEMSYS_32_0_INST_STATUS 0x004e0420 /* Memsys 32 0 inst status */
-#define BCHP_CLKGEN_MOCAMAC_TOP_INST_CLOCK_ENABLE 0x004e0424 /* Mocamac top inst clock enable */
-#define BCHP_CLKGEN_MOCAMAC_TOP_INST_CLOCK_ENABLE_STATUS 0x004e0428 /* Clock Enable Status */
-#define BCHP_CLKGEN_MOCAMAC_TOP_INST_OBSERVE_CLOCK 0x004e042c /* Mocamac top inst observe clock */
-#define BCHP_CLKGEN_MOCAPHY_TOP_INST_CLOCK_ENABLE 0x004e0430 /* Mocaphy top inst clock enable */
-#define BCHP_CLKGEN_MOCAPHY_TOP_INST_CLOCK_ENABLE_STATUS 0x004e0434 /* Clock Enable Status */
-#define BCHP_CLKGEN_MOCAPHY_TOP_INST_OBSERVE_CLOCK 0x004e0438 /* Mocaphy top inst observe clock */
-#define BCHP_CLKGEN_PAD_BYP_CLK_0_OBSERVATION 0x004e043c /* Select observation clk */
-#define BCHP_CLKGEN_PAD_BYP_CLK_1_OBSERVATION 0x004e0440 /* Select observation clk */
-#define BCHP_CLKGEN_PAD_CLOCK_DISABLE 0x004e0444 /* Disable PAD's clocks */
-#define BCHP_CLKGEN_PAD_CLOCK_DISABLE_STATUS 0x004e0448 /* Clock Disable Status */
-#define BCHP_CLKGEN_PAD_CODEC_MCLK_OBSERVATION 0x004e044c /* Select observation clk */
-#define BCHP_CLKGEN_PAD_MUX_SELECT 0x004e0450 /* Mux selects for Pad clocks */
-#define BCHP_CLKGEN_PCIE_X1_TOP_INST_CLOCK_DISABLE 0x004e0454 /* Disable PCIE_X1_TOP_INST's clocks */
-#define BCHP_CLKGEN_PCIE_X1_TOP_INST_CLOCK_DISABLE_STATUS 0x004e0458 /* Clock Disable Status */
-#define BCHP_CLKGEN_PCIE_X1_TOP_INST_CLOCK_ENABLE 0x004e045c /* Pcie x1 top inst clock enable */
-#define BCHP_CLKGEN_PCIE_X1_TOP_INST_CLOCK_ENABLE_STATUS 0x004e0460 /* Clock Enable Status */
-#define BCHP_CLKGEN_PCIE_X1_TOP_INST_OBSERVE_CLOCK 0x004e0464 /* Pcie x1 top inst observe clock */
-#define BCHP_CLKGEN_PLL_CPU_GLITCHLESS_SWITCH_REQUEST 0x004e0468 /* PLL_CPU Glitchless Clock Switching */
-#define BCHP_CLKGEN_PLL_CPU_GLITCHLESS_SWITCH_STATUS 0x004e046c /* PLL_CPU Glitchless Switching */
-#define BCHP_CLKGEN_PLL_CPU_PLL_RESET_STATUS 0x004e0470 /* PLL_CPU Reset Status */
-#define BCHP_CLKGEN_PLL_CPU_RDB_MACRO_CTRL 0x004e0474 /* PLL RDB Macro Disable */
-#define BCHP_CLKGEN_PLL_HVD_PLL_RESET_STATUS 0x004e0478 /* PLL_HVD Reset Status */
-#define BCHP_CLKGEN_PLL_HVD_RDB_MACRO_CTRL 0x004e047c /* PLL RDB Macro Disable */
-#define BCHP_CLKGEN_PLL_LC_PLL_RESET_STATUS 0x004e0480 /* PLL_LC Reset Status */
-#define BCHP_CLKGEN_PLL_MOCA_PLL_RESET_STATUS 0x004e0484 /* PLL_MOCA Reset Status */
-#define BCHP_CLKGEN_PLL_MOCA_RDB_MACRO_CTRL 0x004e0488 /* PLL RDB Macro Disable */
-#define BCHP_CLKGEN_PLL_NETWORK_PLL_RESET_STATUS 0x004e048c /* PLL_NETWORK Reset Status */
-#define BCHP_CLKGEN_PLL_RAAGA_PLL_RESET_STATUS 0x004e0490 /* PLL_RAAGA Reset Status */
-#define BCHP_CLKGEN_PLL_RAAGA_RDB_MACRO_CTRL 0x004e0494 /* PLL RDB Macro Disable */
-#define BCHP_CLKGEN_PLL_SC0_PLL_RESET_STATUS 0x004e0498 /* PLL_SC0 Reset Status */
-#define BCHP_CLKGEN_PLL_SC0_RDB_MACRO_CTRL 0x004e049c /* PLL RDB Macro Disable */
-#define BCHP_CLKGEN_PLL_SC1_PLL_RESET_STATUS 0x004e04a0 /* PLL_SC1 Reset Status */
-#define BCHP_CLKGEN_PLL_SC1_RDB_MACRO_CTRL 0x004e04a4 /* PLL RDB Macro Disable */
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_RESET_STATUS 0x004e04a8 /* PLL_VCXO0 Reset Status */
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_RESET_STATUS 0x004e04ac /* PLL_VCXO1 Reset Status */
-#define BCHP_CLKGEN_PM_CLOCK_Async_ALIVE_SEL 0x004e04b0 /* Select clocks that can stay alive during power management standby mode. */
-#define BCHP_CLKGEN_PM_PLL_ALIVE_SEL 0x004e04b4 /* PLL Alive in Standby Mode */
-#define BCHP_CLKGEN_PM_PLL_LDO_POWERUP 0x004e04b8 /* Power management LDO PLL */
-#define BCHP_CLKGEN_PROD_OTP_INST_CLOCK_DISABLE 0x004e04bc /* Disable PROD_OTP_INST's clocks */
-#define BCHP_CLKGEN_PROD_OTP_INST_CLOCK_DISABLE_STATUS 0x004e04c0 /* Clock Disable Status */
-#define BCHP_CLKGEN_PROD_OTP_INST_CLOCK_ENABLE 0x004e04c4 /* Prod otp inst clock enable */
-#define BCHP_CLKGEN_PROD_OTP_INST_CLOCK_ENABLE_STATUS 0x004e04c8 /* Clock Enable Status */
-#define BCHP_CLKGEN_RAAGA_DSP_TOP_0_INST_CLOCK_ENABLE 0x004e04cc /* Raaga dsp top 0 inst clock enable */
-#define BCHP_CLKGEN_RAAGA_DSP_TOP_0_INST_CLOCK_ENABLE_STATUS 0x004e04d0 /* Clock Enable Status */
-#define BCHP_CLKGEN_RAAGA_DSP_TOP_0_INST_OBSERVE_CLOCK 0x004e04d4 /* Raaga dsp top 0 inst observe clock */
-#define BCHP_CLKGEN_RFM_TOP_INST_CLOCK_ENABLE 0x004e04d8 /* Rfm top inst clock enable */
-#define BCHP_CLKGEN_RFM_TOP_INST_CLOCK_ENABLE_STATUS 0x004e04dc /* Clock Enable Status */
-#define BCHP_CLKGEN_RFM_TOP_INST_OBSERVE_CLOCK 0x004e04e0 /* Rfm top inst observe clock */
-#define BCHP_CLKGEN_SATA3_TOP_INST_CLOCK_DISABLE 0x004e04e4 /* Disable SATA3_TOP_INST's clocks */
-#define BCHP_CLKGEN_SATA3_TOP_INST_CLOCK_DISABLE_STATUS 0x004e04e8 /* Clock Disable Status */
-#define BCHP_CLKGEN_SATA3_TOP_INST_CLOCK_ENABLE 0x004e04ec /* Sata3 top inst clock enable */
-#define BCHP_CLKGEN_SATA3_TOP_INST_CLOCK_ENABLE_STATUS 0x004e04f0 /* Clock Enable Status */
-#define BCHP_CLKGEN_SATA3_TOP_INST_CLOCK_SELECT 0x004e04f4 /* Sata3 top inst clock select */
-#define BCHP_CLKGEN_SATA3_TOP_INST_OBSERVE_CLOCK 0x004e04f8 /* Sata3 top inst observe clock */
-#define BCHP_CLKGEN_SECTOP_INST_OBSERVE_CLOCK 0x004e04fc /* Sectop inst observe clock */
-#define BCHP_CLKGEN_SMARTCARD_MUX_SELECT 0x004e0500 /* Mux selects for Smartcard clocks */
-#define BCHP_CLKGEN_SPARE 0x004e0504 /* Spares */
-#define BCHP_CLKGEN_SYS_CTRL_INST_CLOCK_DISABLE 0x004e0508 /* Disable SYS_CTRL_INST's clocks */
-#define BCHP_CLKGEN_SYS_CTRL_INST_CLOCK_DISABLE_STATUS 0x004e050c /* Clock Disable Status */
-#define BCHP_CLKGEN_SYS_CTRL_INST_OBSERVE_CLOCK 0x004e0510 /* Sys ctrl inst observe clock */
-#define BCHP_CLKGEN_TESTPORT 0x004e0514 /* Special Testport Controls */
-#define BCHP_CLKGEN_USB0_TOP_INST_CLOCK_DISABLE 0x004e0518 /* Disable USB0_TOP_INST's clocks */
-#define BCHP_CLKGEN_USB0_TOP_INST_CLOCK_DISABLE_STATUS 0x004e051c /* Clock Disable Status */
-#define BCHP_CLKGEN_USB0_TOP_INST_CLOCK_ENABLE 0x004e0520 /* Usb0 top inst clock enable */
-#define BCHP_CLKGEN_USB0_TOP_INST_CLOCK_ENABLE_AHB 0x004e0524 /* Usb0 top inst clock enable ahb */
-#define BCHP_CLKGEN_USB0_TOP_INST_CLOCK_ENABLE_AHB_STATUS 0x004e0528 /* Clock Enable Status */
-#define BCHP_CLKGEN_USB0_TOP_INST_CLOCK_ENABLE_AXI 0x004e052c /* Usb0 top inst clock enable axi */
-#define BCHP_CLKGEN_USB0_TOP_INST_CLOCK_ENABLE_AXI_STATUS 0x004e0530 /* Clock Enable Status */
-#define BCHP_CLKGEN_USB0_TOP_INST_CLOCK_ENABLE_STATUS 0x004e0534 /* Clock Enable Status */
-#define BCHP_CLKGEN_USB0_TOP_INST_OBSERVE_CLOCK 0x004e0538 /* Usb0 top inst observe clock */
-#define BCHP_CLKGEN_USB1_TOP_INST_CLOCK_DISABLE 0x004e053c /* Disable USB1_TOP_INST's clocks */
-#define BCHP_CLKGEN_USB1_TOP_INST_CLOCK_DISABLE_STATUS 0x004e0540 /* Clock Disable Status */
-#define BCHP_CLKGEN_USB1_TOP_INST_CLOCK_ENABLE 0x004e0544 /* Usb1 top inst clock enable */
-#define BCHP_CLKGEN_USB1_TOP_INST_CLOCK_ENABLE_AHB 0x004e0548 /* Usb1 top inst clock enable ahb */
-#define BCHP_CLKGEN_USB1_TOP_INST_CLOCK_ENABLE_AHB_STATUS 0x004e054c /* Clock Enable Status */
-#define BCHP_CLKGEN_USB1_TOP_INST_CLOCK_ENABLE_AXI 0x004e0550 /* Usb1 top inst clock enable axi */
-#define BCHP_CLKGEN_USB1_TOP_INST_CLOCK_ENABLE_AXI_STATUS 0x004e0554 /* Clock Enable Status */
-#define BCHP_CLKGEN_USB1_TOP_INST_CLOCK_ENABLE_STATUS 0x004e0558 /* Clock Enable Status */
-#define BCHP_CLKGEN_USB1_TOP_INST_OBSERVE_CLOCK 0x004e055c /* Usb1 top inst observe clock */
-#define BCHP_CLKGEN_V3D_TOP_INST_CLOCK_ENABLE 0x004e0560 /* V3d top inst clock enable */
-#define BCHP_CLKGEN_V3D_TOP_INST_CLOCK_ENABLE_STATUS 0x004e0564 /* Clock Enable Status */
-#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_DISABLE 0x004e0568 /* Disable VEC_AIO_TOP_INST's clocks */
-#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_DISABLE_STATUS 0x004e056c /* Clock Disable Status */
-#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE 0x004e0570 /* Vec aio top inst clock enable */
-#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_AIO 0x004e0574 /* Vec aio top inst clock enable aio */
-#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_AIO_STATUS 0x004e0578 /* Clock Enable Status */
-#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_STATUS 0x004e057c /* Clock Enable Status */
-#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC 0x004e0580 /* Vec aio top inst clock enable vec */
-#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC_QDAC_INTF 0x004e0584 /* Vec aio top inst clock enable vec qdac intf */
-#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC_QDAC_INTF_STATUS 0x004e0588 /* Clock Enable Status */
-#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC_STATUS 0x004e058c /* Clock Enable Status */
-#define BCHP_CLKGEN_VEC_AIO_TOP_INST_ENABLE 0x004e0590 /* Vec aio top inst enable */
-#define BCHP_CLKGEN_VEC_AIO_TOP_INST_OBSERVE_CLOCK 0x004e0594 /* Vec aio top inst observe clock */
-#define BCHP_CLKGEN_VICE2_0_INST_CLOCK_ENABLE 0x004e0598 /* Vice2 0 inst clock enable */
-#define BCHP_CLKGEN_VICE2_0_INST_CLOCK_ENABLE_STATUS 0x004e059c /* Clock Enable Status */
-#define BCHP_CLKGEN_BSPI_CLOCK_SELECT 0x004e05a0 /* spi clock control */
-#define BCHP_CLKGEN_USBPHY_REF_CLOCK_BYPASS 0x004e05a4 /* bypass USBPHY reference clocks */
-#define BCHP_CLKGEN_EPHY_REF_CLOCK_BYPASS 0x004e05a8 /* bypass EPHY reference clocks */
-#define BCHP_CLKGEN_PLL_AUDIO0 0x004e05ac /* Ana pll4 1p8v ts28hpm 6mx 2mr fc x e pllaudio0 inst pll audio0 */
-#define BCHP_CLKGEN_PLL_AUDIO1 0x004e05b0 /* Ana pll4 rfmod 1p8v ts28hpm 6mx 2mr np x e pllaudio1 inst pll audio1 */
-
-/***************************************************************************
- *PLL_CPU_PLL_CHANNEL_CTRL_CH_0 - PLL CHANNEL control CH 0
- ***************************************************************************/
-/* CLKGEN :: PLL_CPU_PLL_CHANNEL_CTRL_CH_0 :: reserved0 [31:11] */
-#define BCHP_CLKGEN_PLL_CPU_PLL_CHANNEL_CTRL_CH_0_reserved0_MASK 0xfffff800
-#define BCHP_CLKGEN_PLL_CPU_PLL_CHANNEL_CTRL_CH_0_reserved0_SHIFT 11
-
-/* CLKGEN :: PLL_CPU_PLL_CHANNEL_CTRL_CH_0 :: POST_DIVIDER_HOLD_CH0 [10:10] */
-#define BCHP_CLKGEN_PLL_CPU_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_MASK 0x00000400
-#define BCHP_CLKGEN_PLL_CPU_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_SHIFT 10
-#define BCHP_CLKGEN_PLL_CPU_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_CPU_PLL_CHANNEL_CTRL_CH_0 :: PHASE_OFFSET_CH0 [09:09] */
-#define BCHP_CLKGEN_PLL_CPU_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_MASK 0x00000200
-#define BCHP_CLKGEN_PLL_CPU_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_SHIFT 9
-#define BCHP_CLKGEN_PLL_CPU_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_CPU_PLL_CHANNEL_CTRL_CH_0 :: MDIV_CH0 [08:01] */
-#define BCHP_CLKGEN_PLL_CPU_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_MASK 0x000001fe
-#define BCHP_CLKGEN_PLL_CPU_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_SHIFT 1
-#define BCHP_CLKGEN_PLL_CPU_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_DEFAULT 0x00000002
-
-/* CLKGEN :: PLL_CPU_PLL_CHANNEL_CTRL_CH_0 :: CLOCK_DIS_CH0 [00:00] */
-#define BCHP_CLKGEN_PLL_CPU_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_MASK 0x00000001
-#define BCHP_CLKGEN_PLL_CPU_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_SHIFT 0
-#define BCHP_CLKGEN_PLL_CPU_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_DEFAULT 0x00000000
-
-/***************************************************************************
- *PLL_CPU_PLL_CHANNEL_CTRL_CH_1 - PLL CHANNEL control CH 1
- ***************************************************************************/
-/* CLKGEN :: PLL_CPU_PLL_CHANNEL_CTRL_CH_1 :: reserved0 [31:11] */
-#define BCHP_CLKGEN_PLL_CPU_PLL_CHANNEL_CTRL_CH_1_reserved0_MASK 0xfffff800
-#define BCHP_CLKGEN_PLL_CPU_PLL_CHANNEL_CTRL_CH_1_reserved0_SHIFT 11
-
-/* CLKGEN :: PLL_CPU_PLL_CHANNEL_CTRL_CH_1 :: POST_DIVIDER_HOLD_CH1 [10:10] */
-#define BCHP_CLKGEN_PLL_CPU_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_MASK 0x00000400
-#define BCHP_CLKGEN_PLL_CPU_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_SHIFT 10
-#define BCHP_CLKGEN_PLL_CPU_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_CPU_PLL_CHANNEL_CTRL_CH_1 :: PHASE_OFFSET_CH1 [09:09] */
-#define BCHP_CLKGEN_PLL_CPU_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_MASK 0x00000200
-#define BCHP_CLKGEN_PLL_CPU_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_SHIFT 9
-#define BCHP_CLKGEN_PLL_CPU_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_CPU_PLL_CHANNEL_CTRL_CH_1 :: MDIV_CH1 [08:01] */
-#define BCHP_CLKGEN_PLL_CPU_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_MASK 0x000001fe
-#define BCHP_CLKGEN_PLL_CPU_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_SHIFT 1
-#define BCHP_CLKGEN_PLL_CPU_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_DEFAULT 0x00000064
-
-/* CLKGEN :: PLL_CPU_PLL_CHANNEL_CTRL_CH_1 :: CLOCK_DIS_CH1 [00:00] */
-#define BCHP_CLKGEN_PLL_CPU_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_MASK 0x00000001
-#define BCHP_CLKGEN_PLL_CPU_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_SHIFT 0
-#define BCHP_CLKGEN_PLL_CPU_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_DEFAULT 0x00000001
-
-/***************************************************************************
- *PLL_CPU_PLL_DIV - Pre multiplier
- ***************************************************************************/
-/* CLKGEN :: PLL_CPU_PLL_DIV :: reserved0 [31:14] */
-#define BCHP_CLKGEN_PLL_CPU_PLL_DIV_reserved0_MASK 0xffffc000
-#define BCHP_CLKGEN_PLL_CPU_PLL_DIV_reserved0_SHIFT 14
-
-/* CLKGEN :: PLL_CPU_PLL_DIV :: PDIV [13:10] */
-#define BCHP_CLKGEN_PLL_CPU_PLL_DIV_PDIV_MASK 0x00003c00
-#define BCHP_CLKGEN_PLL_CPU_PLL_DIV_PDIV_SHIFT 10
-#define BCHP_CLKGEN_PLL_CPU_PLL_DIV_PDIV_DEFAULT 0x00000003
-
-/* CLKGEN :: PLL_CPU_PLL_DIV :: NDIV_INT [09:00] */
-#define BCHP_CLKGEN_PLL_CPU_PLL_DIV_NDIV_INT_MASK 0x000003ff
-#define BCHP_CLKGEN_PLL_CPU_PLL_DIV_NDIV_INT_SHIFT 0
-#define BCHP_CLKGEN_PLL_CPU_PLL_DIV_NDIV_INT_DEFAULT 0x000000a7
-
-/***************************************************************************
- *PLL_CPU_PLL_FRAC - Fractional
- ***************************************************************************/
-/* CLKGEN :: PLL_CPU_PLL_FRAC :: reserved0 [31:20] */
-#define BCHP_CLKGEN_PLL_CPU_PLL_FRAC_reserved0_MASK 0xfff00000
-#define BCHP_CLKGEN_PLL_CPU_PLL_FRAC_reserved0_SHIFT 20
-
-/* CLKGEN :: PLL_CPU_PLL_FRAC :: FRAC_CONTROL [19:00] */
-#define BCHP_CLKGEN_PLL_CPU_PLL_FRAC_FRAC_CONTROL_MASK 0x000fffff
-#define BCHP_CLKGEN_PLL_CPU_PLL_FRAC_FRAC_CONTROL_SHIFT 0
-#define BCHP_CLKGEN_PLL_CPU_PLL_FRAC_FRAC_CONTROL_DEFAULT 0x00000000
-
-/***************************************************************************
- *PLL_CPU_PLL_GAIN - PLL GAIN
- ***************************************************************************/
-/* CLKGEN :: PLL_CPU_PLL_GAIN :: reserved0 [31:10] */
-#define BCHP_CLKGEN_PLL_CPU_PLL_GAIN_reserved0_MASK 0xfffffc00
-#define BCHP_CLKGEN_PLL_CPU_PLL_GAIN_reserved0_SHIFT 10
-
-/* CLKGEN :: PLL_CPU_PLL_GAIN :: LOOP_GAIN_PROPORTIONAL_IN_PHASE [09:06] */
-#define BCHP_CLKGEN_PLL_CPU_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_MASK 0x000003c0
-#define BCHP_CLKGEN_PLL_CPU_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_SHIFT 6
-#define BCHP_CLKGEN_PLL_CPU_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_DEFAULT 0x00000003
-
-/* CLKGEN :: PLL_CPU_PLL_GAIN :: LOOP_GAIN_IN_FREQ [05:03] */
-#define BCHP_CLKGEN_PLL_CPU_PLL_GAIN_LOOP_GAIN_IN_FREQ_MASK 0x00000038
-#define BCHP_CLKGEN_PLL_CPU_PLL_GAIN_LOOP_GAIN_IN_FREQ_SHIFT 3
-#define BCHP_CLKGEN_PLL_CPU_PLL_GAIN_LOOP_GAIN_IN_FREQ_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_CPU_PLL_GAIN :: LOOP_GAIN_INTEGRATOR_IN_PHASE [02:00] */
-#define BCHP_CLKGEN_PLL_CPU_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_MASK 0x00000007
-#define BCHP_CLKGEN_PLL_CPU_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_SHIFT 0
-#define BCHP_CLKGEN_PLL_CPU_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_DEFAULT 0x00000002
-
-/***************************************************************************
- *PLL_CPU_PLL_LDO_PWRON - LDO Power on
- ***************************************************************************/
-/* CLKGEN :: PLL_CPU_PLL_LDO_PWRON :: reserved0 [31:01] */
-#define BCHP_CLKGEN_PLL_CPU_PLL_LDO_PWRON_reserved0_MASK 0xfffffffe
-#define BCHP_CLKGEN_PLL_CPU_PLL_LDO_PWRON_reserved0_SHIFT 1
-
-/* CLKGEN :: PLL_CPU_PLL_LDO_PWRON :: LDO_PWRON_PLL [00:00] */
-#define BCHP_CLKGEN_PLL_CPU_PLL_LDO_PWRON_LDO_PWRON_PLL_MASK 0x00000001
-#define BCHP_CLKGEN_PLL_CPU_PLL_LDO_PWRON_LDO_PWRON_PLL_SHIFT 0
-#define BCHP_CLKGEN_PLL_CPU_PLL_LDO_PWRON_LDO_PWRON_PLL_DEFAULT 0x00000001
-
-/***************************************************************************
- *PLL_CPU_PLL_LOCK_STATUS - Lock Status
- ***************************************************************************/
-/* CLKGEN :: PLL_CPU_PLL_LOCK_STATUS :: reserved0 [31:02] */
-#define BCHP_CLKGEN_PLL_CPU_PLL_LOCK_STATUS_reserved0_MASK 0xfffffffc
-#define BCHP_CLKGEN_PLL_CPU_PLL_LOCK_STATUS_reserved0_SHIFT 2
-
-/* CLKGEN :: PLL_CPU_PLL_LOCK_STATUS :: LOCK_LOST [01:01] */
-#define BCHP_CLKGEN_PLL_CPU_PLL_LOCK_STATUS_LOCK_LOST_MASK 0x00000002
-#define BCHP_CLKGEN_PLL_CPU_PLL_LOCK_STATUS_LOCK_LOST_SHIFT 1
-
-/* CLKGEN :: PLL_CPU_PLL_LOCK_STATUS :: LOCK [00:00] */
-#define BCHP_CLKGEN_PLL_CPU_PLL_LOCK_STATUS_LOCK_MASK 0x00000001
-#define BCHP_CLKGEN_PLL_CPU_PLL_LOCK_STATUS_LOCK_SHIFT 0
-
-/***************************************************************************
- *PLL_CPU_PLL_MISC - Mscellaneous control bus.
- ***************************************************************************/
-/* CLKGEN :: PLL_CPU_PLL_MISC :: VCO_RANGE [31:30] */
-#define BCHP_CLKGEN_PLL_CPU_PLL_MISC_VCO_RANGE_MASK 0xc0000000
-#define BCHP_CLKGEN_PLL_CPU_PLL_MISC_VCO_RANGE_SHIFT 30
-#define BCHP_CLKGEN_PLL_CPU_PLL_MISC_VCO_RANGE_DEFAULT 0x00000002
-
-/* CLKGEN :: PLL_CPU_PLL_MISC :: VCO_FB_DIV2 [29:29] */
-#define BCHP_CLKGEN_PLL_CPU_PLL_MISC_VCO_FB_DIV2_MASK 0x20000000
-#define BCHP_CLKGEN_PLL_CPU_PLL_MISC_VCO_FB_DIV2_SHIFT 29
-#define BCHP_CLKGEN_PLL_CPU_PLL_MISC_VCO_FB_DIV2_DEFAULT 0x00000001
-
-/* CLKGEN :: PLL_CPU_PLL_MISC :: STAT_UPDATE [28:28] */
-#define BCHP_CLKGEN_PLL_CPU_PLL_MISC_STAT_UPDATE_MASK 0x10000000
-#define BCHP_CLKGEN_PLL_CPU_PLL_MISC_STAT_UPDATE_SHIFT 28
-#define BCHP_CLKGEN_PLL_CPU_PLL_MISC_STAT_UPDATE_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_CPU_PLL_MISC :: STAT_SELECT [27:25] */
-#define BCHP_CLKGEN_PLL_CPU_PLL_MISC_STAT_SELECT_MASK 0x0e000000
-#define BCHP_CLKGEN_PLL_CPU_PLL_MISC_STAT_SELECT_SHIFT 25
-#define BCHP_CLKGEN_PLL_CPU_PLL_MISC_STAT_SELECT_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_CPU_PLL_MISC :: STAT_RESET [24:24] */
-#define BCHP_CLKGEN_PLL_CPU_PLL_MISC_STAT_RESET_MASK 0x01000000
-#define BCHP_CLKGEN_PLL_CPU_PLL_MISC_STAT_RESET_SHIFT 24
-#define BCHP_CLKGEN_PLL_CPU_PLL_MISC_STAT_RESET_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_CPU_PLL_MISC :: STAT_MODE [23:22] */
-#define BCHP_CLKGEN_PLL_CPU_PLL_MISC_STAT_MODE_MASK 0x00c00000
-#define BCHP_CLKGEN_PLL_CPU_PLL_MISC_STAT_MODE_SHIFT 22
-#define BCHP_CLKGEN_PLL_CPU_PLL_MISC_STAT_MODE_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_CPU_PLL_MISC :: PWM_RATE [21:20] */
-#define BCHP_CLKGEN_PLL_CPU_PLL_MISC_PWM_RATE_MASK 0x00300000
-#define BCHP_CLKGEN_PLL_CPU_PLL_MISC_PWM_RATE_SHIFT 20
-#define BCHP_CLKGEN_PLL_CPU_PLL_MISC_PWM_RATE_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_CPU_PLL_MISC :: POST_CTRL_RESETB [19:18] */
-#define BCHP_CLKGEN_PLL_CPU_PLL_MISC_POST_CTRL_RESETB_MASK 0x000c0000
-#define BCHP_CLKGEN_PLL_CPU_PLL_MISC_POST_CTRL_RESETB_SHIFT 18
-#define BCHP_CLKGEN_PLL_CPU_PLL_MISC_POST_CTRL_RESETB_DEFAULT 0x00000003
-
-/* CLKGEN :: PLL_CPU_PLL_MISC :: PLLRESERVED2 [17:16] */
-#define BCHP_CLKGEN_PLL_CPU_PLL_MISC_PLLRESERVED2_MASK 0x00030000
-#define BCHP_CLKGEN_PLL_CPU_PLL_MISC_PLLRESERVED2_SHIFT 16
-#define BCHP_CLKGEN_PLL_CPU_PLL_MISC_PLLRESERVED2_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_CPU_PLL_MISC :: PLLRESERVED1 [15:15] */
-#define BCHP_CLKGEN_PLL_CPU_PLL_MISC_PLLRESERVED1_MASK 0x00008000
-#define BCHP_CLKGEN_PLL_CPU_PLL_MISC_PLLRESERVED1_SHIFT 15
-#define BCHP_CLKGEN_PLL_CPU_PLL_MISC_PLLRESERVED1_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_CPU_PLL_MISC :: NDIV_RELOCK [14:14] */
-#define BCHP_CLKGEN_PLL_CPU_PLL_MISC_NDIV_RELOCK_MASK 0x00004000
-#define BCHP_CLKGEN_PLL_CPU_PLL_MISC_NDIV_RELOCK_SHIFT 14
-#define BCHP_CLKGEN_PLL_CPU_PLL_MISC_NDIV_RELOCK_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_CPU_PLL_MISC :: FAST_LOCK [13:13] */
-#define BCHP_CLKGEN_PLL_CPU_PLL_MISC_FAST_LOCK_MASK 0x00002000
-#define BCHP_CLKGEN_PLL_CPU_PLL_MISC_FAST_LOCK_SHIFT 13
-#define BCHP_CLKGEN_PLL_CPU_PLL_MISC_FAST_LOCK_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_CPU_PLL_MISC :: DCO_CTRL_BYPASS_ENABLE [12:12] */
-#define BCHP_CLKGEN_PLL_CPU_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_MASK 0x00001000
-#define BCHP_CLKGEN_PLL_CPU_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_SHIFT 12
-#define BCHP_CLKGEN_PLL_CPU_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_CPU_PLL_MISC :: DCO_CTRL_BYPASS [11:00] */
-#define BCHP_CLKGEN_PLL_CPU_PLL_MISC_DCO_CTRL_BYPASS_MASK 0x00000fff
-#define BCHP_CLKGEN_PLL_CPU_PLL_MISC_DCO_CTRL_BYPASS_SHIFT 0
-#define BCHP_CLKGEN_PLL_CPU_PLL_MISC_DCO_CTRL_BYPASS_DEFAULT 0x00000000
-
-/***************************************************************************
- *PLL_CPU_PLL_MISC2 - Mscellaneous control bus continued.
- ***************************************************************************/
-/* CLKGEN :: PLL_CPU_PLL_MISC2 :: PLLRESERVED0 [31:00] */
-#define BCHP_CLKGEN_PLL_CPU_PLL_MISC2_PLLRESERVED0_MASK 0xffffffff
-#define BCHP_CLKGEN_PLL_CPU_PLL_MISC2_PLLRESERVED0_SHIFT 0
-#define BCHP_CLKGEN_PLL_CPU_PLL_MISC2_PLLRESERVED0_DEFAULT 0x00000001
-
-/***************************************************************************
- *PLL_CPU_PLL_PWRON - Poweron
- ***************************************************************************/
-/* CLKGEN :: PLL_CPU_PLL_PWRON :: reserved0 [31:01] */
-#define BCHP_CLKGEN_PLL_CPU_PLL_PWRON_reserved0_MASK 0xfffffffe
-#define BCHP_CLKGEN_PLL_CPU_PLL_PWRON_reserved0_SHIFT 1
-
-/* CLKGEN :: PLL_CPU_PLL_PWRON :: PWRON_PLL [00:00] */
-#define BCHP_CLKGEN_PLL_CPU_PLL_PWRON_PWRON_PLL_MASK 0x00000001
-#define BCHP_CLKGEN_PLL_CPU_PLL_PWRON_PWRON_PLL_SHIFT 0
-#define BCHP_CLKGEN_PLL_CPU_PLL_PWRON_PWRON_PLL_DEFAULT 0x00000001
-
-/***************************************************************************
- *PLL_CPU_PLL_RESET - Resets
- ***************************************************************************/
-/* CLKGEN :: PLL_CPU_PLL_RESET :: reserved0 [31:02] */
-#define BCHP_CLKGEN_PLL_CPU_PLL_RESET_reserved0_MASK 0xfffffffc
-#define BCHP_CLKGEN_PLL_CPU_PLL_RESET_reserved0_SHIFT 2
-
-/* CLKGEN :: PLL_CPU_PLL_RESET :: RESETD [01:01] */
-#define BCHP_CLKGEN_PLL_CPU_PLL_RESET_RESETD_MASK 0x00000002
-#define BCHP_CLKGEN_PLL_CPU_PLL_RESET_RESETD_SHIFT 1
-#define BCHP_CLKGEN_PLL_CPU_PLL_RESET_RESETD_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_CPU_PLL_RESET :: RESETA [00:00] */
-#define BCHP_CLKGEN_PLL_CPU_PLL_RESET_RESETA_MASK 0x00000001
-#define BCHP_CLKGEN_PLL_CPU_PLL_RESET_RESETA_SHIFT 0
-#define BCHP_CLKGEN_PLL_CPU_PLL_RESET_RESETA_DEFAULT 0x00000000
-
-/***************************************************************************
- *PLL_CPU_PLL_SSC_MODE_CONTROL_HIGH - Higher bits of Spread Spectrum mode control
- ***************************************************************************/
-/* CLKGEN :: PLL_CPU_PLL_SSC_MODE_CONTROL_HIGH :: reserved0 [31:16] */
-#define BCHP_CLKGEN_PLL_CPU_PLL_SSC_MODE_CONTROL_HIGH_reserved0_MASK 0xffff0000
-#define BCHP_CLKGEN_PLL_CPU_PLL_SSC_MODE_CONTROL_HIGH_reserved0_SHIFT 16
-
-/* CLKGEN :: PLL_CPU_PLL_SSC_MODE_CONTROL_HIGH :: SSC_STEP [15:00] */
-#define BCHP_CLKGEN_PLL_CPU_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_MASK 0x0000ffff
-#define BCHP_CLKGEN_PLL_CPU_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_SHIFT 0
-#define BCHP_CLKGEN_PLL_CPU_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *PLL_CPU_PLL_SSC_MODE_CONTROL_LOW - Lower bits of Spread Spectrum mode control
- ***************************************************************************/
-/* CLKGEN :: PLL_CPU_PLL_SSC_MODE_CONTROL_LOW :: reserved0 [31:23] */
-#define BCHP_CLKGEN_PLL_CPU_PLL_SSC_MODE_CONTROL_LOW_reserved0_MASK 0xff800000
-#define BCHP_CLKGEN_PLL_CPU_PLL_SSC_MODE_CONTROL_LOW_reserved0_SHIFT 23
-
-/* CLKGEN :: PLL_CPU_PLL_SSC_MODE_CONTROL_LOW :: SSC_MODE [22:22] */
-#define BCHP_CLKGEN_PLL_CPU_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_MASK 0x00400000
-#define BCHP_CLKGEN_PLL_CPU_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_SHIFT 22
-#define BCHP_CLKGEN_PLL_CPU_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_CPU_PLL_SSC_MODE_CONTROL_LOW :: SSC_LIMIT [21:00] */
-#define BCHP_CLKGEN_PLL_CPU_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_MASK 0x003fffff
-#define BCHP_CLKGEN_PLL_CPU_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_SHIFT 0
-#define BCHP_CLKGEN_PLL_CPU_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_DEFAULT 0x00000000
-
-/***************************************************************************
- *PLL_CPU_PLL_STATUS - Status
- ***************************************************************************/
-/* CLKGEN :: PLL_CPU_PLL_STATUS :: reserved0 [31:12] */
-#define BCHP_CLKGEN_PLL_CPU_PLL_STATUS_reserved0_MASK 0xfffff000
-#define BCHP_CLKGEN_PLL_CPU_PLL_STATUS_reserved0_SHIFT 12
-
-/* CLKGEN :: PLL_CPU_PLL_STATUS :: TEST_STATUS [11:00] */
-#define BCHP_CLKGEN_PLL_CPU_PLL_STATUS_TEST_STATUS_MASK 0x00000fff
-#define BCHP_CLKGEN_PLL_CPU_PLL_STATUS_TEST_STATUS_SHIFT 0
-
-/***************************************************************************
- *PLL_HVD_PLL_CHANNEL_CTRL_CH_0 - PLL CHANNEL control CH 0
- ***************************************************************************/
-/* CLKGEN :: PLL_HVD_PLL_CHANNEL_CTRL_CH_0 :: reserved0 [31:11] */
-#define BCHP_CLKGEN_PLL_HVD_PLL_CHANNEL_CTRL_CH_0_reserved0_MASK 0xfffff800
-#define BCHP_CLKGEN_PLL_HVD_PLL_CHANNEL_CTRL_CH_0_reserved0_SHIFT 11
-
-/* CLKGEN :: PLL_HVD_PLL_CHANNEL_CTRL_CH_0 :: POST_DIVIDER_HOLD_CH0 [10:10] */
-#define BCHP_CLKGEN_PLL_HVD_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_MASK 0x00000400
-#define BCHP_CLKGEN_PLL_HVD_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_SHIFT 10
-#define BCHP_CLKGEN_PLL_HVD_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_HVD_PLL_CHANNEL_CTRL_CH_0 :: PHASE_OFFSET_CH0 [09:09] */
-#define BCHP_CLKGEN_PLL_HVD_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_MASK 0x00000200
-#define BCHP_CLKGEN_PLL_HVD_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_SHIFT 9
-#define BCHP_CLKGEN_PLL_HVD_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_HVD_PLL_CHANNEL_CTRL_CH_0 :: MDIV_CH0 [08:01] */
-#define BCHP_CLKGEN_PLL_HVD_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_MASK 0x000001fe
-#define BCHP_CLKGEN_PLL_HVD_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_SHIFT 1
-#define BCHP_CLKGEN_PLL_HVD_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_DEFAULT 0x00000008
-
-/* CLKGEN :: PLL_HVD_PLL_CHANNEL_CTRL_CH_0 :: CLOCK_DIS_CH0 [00:00] */
-#define BCHP_CLKGEN_PLL_HVD_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_MASK 0x00000001
-#define BCHP_CLKGEN_PLL_HVD_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_SHIFT 0
-#define BCHP_CLKGEN_PLL_HVD_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_DEFAULT 0x00000000
-
-/***************************************************************************
- *PLL_HVD_PLL_CHANNEL_CTRL_CH_1 - PLL CHANNEL control CH 1
- ***************************************************************************/
-/* CLKGEN :: PLL_HVD_PLL_CHANNEL_CTRL_CH_1 :: reserved0 [31:11] */
-#define BCHP_CLKGEN_PLL_HVD_PLL_CHANNEL_CTRL_CH_1_reserved0_MASK 0xfffff800
-#define BCHP_CLKGEN_PLL_HVD_PLL_CHANNEL_CTRL_CH_1_reserved0_SHIFT 11
-
-/* CLKGEN :: PLL_HVD_PLL_CHANNEL_CTRL_CH_1 :: POST_DIVIDER_HOLD_CH1 [10:10] */
-#define BCHP_CLKGEN_PLL_HVD_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_MASK 0x00000400
-#define BCHP_CLKGEN_PLL_HVD_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_SHIFT 10
-#define BCHP_CLKGEN_PLL_HVD_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_HVD_PLL_CHANNEL_CTRL_CH_1 :: PHASE_OFFSET_CH1 [09:09] */
-#define BCHP_CLKGEN_PLL_HVD_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_MASK 0x00000200
-#define BCHP_CLKGEN_PLL_HVD_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_SHIFT 9
-#define BCHP_CLKGEN_PLL_HVD_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_HVD_PLL_CHANNEL_CTRL_CH_1 :: MDIV_CH1 [08:01] */
-#define BCHP_CLKGEN_PLL_HVD_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_MASK 0x000001fe
-#define BCHP_CLKGEN_PLL_HVD_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_SHIFT 1
-#define BCHP_CLKGEN_PLL_HVD_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_DEFAULT 0x00000006
-
-/* CLKGEN :: PLL_HVD_PLL_CHANNEL_CTRL_CH_1 :: CLOCK_DIS_CH1 [00:00] */
-#define BCHP_CLKGEN_PLL_HVD_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_MASK 0x00000001
-#define BCHP_CLKGEN_PLL_HVD_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_SHIFT 0
-#define BCHP_CLKGEN_PLL_HVD_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_DEFAULT 0x00000000
-
-/***************************************************************************
- *PLL_HVD_PLL_CHANNEL_CTRL_CH_4 - PLL CHANNEL control CH 4
- ***************************************************************************/
-/* CLKGEN :: PLL_HVD_PLL_CHANNEL_CTRL_CH_4 :: reserved0 [31:11] */
-#define BCHP_CLKGEN_PLL_HVD_PLL_CHANNEL_CTRL_CH_4_reserved0_MASK 0xfffff800
-#define BCHP_CLKGEN_PLL_HVD_PLL_CHANNEL_CTRL_CH_4_reserved0_SHIFT 11
-
-/* CLKGEN :: PLL_HVD_PLL_CHANNEL_CTRL_CH_4 :: POST_DIVIDER_HOLD_CH4 [10:10] */
-#define BCHP_CLKGEN_PLL_HVD_PLL_CHANNEL_CTRL_CH_4_POST_DIVIDER_HOLD_CH4_MASK 0x00000400
-#define BCHP_CLKGEN_PLL_HVD_PLL_CHANNEL_CTRL_CH_4_POST_DIVIDER_HOLD_CH4_SHIFT 10
-#define BCHP_CLKGEN_PLL_HVD_PLL_CHANNEL_CTRL_CH_4_POST_DIVIDER_HOLD_CH4_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_HVD_PLL_CHANNEL_CTRL_CH_4 :: PHASE_OFFSET_CH4 [09:09] */
-#define BCHP_CLKGEN_PLL_HVD_PLL_CHANNEL_CTRL_CH_4_PHASE_OFFSET_CH4_MASK 0x00000200
-#define BCHP_CLKGEN_PLL_HVD_PLL_CHANNEL_CTRL_CH_4_PHASE_OFFSET_CH4_SHIFT 9
-#define BCHP_CLKGEN_PLL_HVD_PLL_CHANNEL_CTRL_CH_4_PHASE_OFFSET_CH4_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_HVD_PLL_CHANNEL_CTRL_CH_4 :: MDIV_CH4 [08:01] */
-#define BCHP_CLKGEN_PLL_HVD_PLL_CHANNEL_CTRL_CH_4_MDIV_CH4_MASK 0x000001fe
-#define BCHP_CLKGEN_PLL_HVD_PLL_CHANNEL_CTRL_CH_4_MDIV_CH4_SHIFT 1
-#define BCHP_CLKGEN_PLL_HVD_PLL_CHANNEL_CTRL_CH_4_MDIV_CH4_DEFAULT 0x00000064
-
-/* CLKGEN :: PLL_HVD_PLL_CHANNEL_CTRL_CH_4 :: CLOCK_DIS_CH4 [00:00] */
-#define BCHP_CLKGEN_PLL_HVD_PLL_CHANNEL_CTRL_CH_4_CLOCK_DIS_CH4_MASK 0x00000001
-#define BCHP_CLKGEN_PLL_HVD_PLL_CHANNEL_CTRL_CH_4_CLOCK_DIS_CH4_SHIFT 0
-#define BCHP_CLKGEN_PLL_HVD_PLL_CHANNEL_CTRL_CH_4_CLOCK_DIS_CH4_DEFAULT 0x00000001
-
-/***************************************************************************
- *PLL_HVD_PLL_DIV - Pre multiplier
- ***************************************************************************/
-/* CLKGEN :: PLL_HVD_PLL_DIV :: reserved0 [31:14] */
-#define BCHP_CLKGEN_PLL_HVD_PLL_DIV_reserved0_MASK 0xffffc000
-#define BCHP_CLKGEN_PLL_HVD_PLL_DIV_reserved0_SHIFT 14
-
-/* CLKGEN :: PLL_HVD_PLL_DIV :: PDIV [13:10] */
-#define BCHP_CLKGEN_PLL_HVD_PLL_DIV_PDIV_MASK 0x00003c00
-#define BCHP_CLKGEN_PLL_HVD_PLL_DIV_PDIV_SHIFT 10
-#define BCHP_CLKGEN_PLL_HVD_PLL_DIV_PDIV_DEFAULT 0x00000003
-
-/* CLKGEN :: PLL_HVD_PLL_DIV :: NDIV_INT [09:00] */
-#define BCHP_CLKGEN_PLL_HVD_PLL_DIV_NDIV_INT_MASK 0x000003ff
-#define BCHP_CLKGEN_PLL_HVD_PLL_DIV_NDIV_INT_SHIFT 0
-#define BCHP_CLKGEN_PLL_HVD_PLL_DIV_NDIV_INT_DEFAULT 0x000000c8
-
-/***************************************************************************
- *PLL_HVD_PLL_FRAC - Fractional
- ***************************************************************************/
-/* CLKGEN :: PLL_HVD_PLL_FRAC :: reserved0 [31:20] */
-#define BCHP_CLKGEN_PLL_HVD_PLL_FRAC_reserved0_MASK 0xfff00000
-#define BCHP_CLKGEN_PLL_HVD_PLL_FRAC_reserved0_SHIFT 20
-
-/* CLKGEN :: PLL_HVD_PLL_FRAC :: FRAC_CONTROL [19:00] */
-#define BCHP_CLKGEN_PLL_HVD_PLL_FRAC_FRAC_CONTROL_MASK 0x000fffff
-#define BCHP_CLKGEN_PLL_HVD_PLL_FRAC_FRAC_CONTROL_SHIFT 0
-#define BCHP_CLKGEN_PLL_HVD_PLL_FRAC_FRAC_CONTROL_DEFAULT 0x00000000
-
-/***************************************************************************
- *PLL_HVD_PLL_GAIN - PLL GAIN
- ***************************************************************************/
-/* CLKGEN :: PLL_HVD_PLL_GAIN :: reserved0 [31:10] */
-#define BCHP_CLKGEN_PLL_HVD_PLL_GAIN_reserved0_MASK 0xfffffc00
-#define BCHP_CLKGEN_PLL_HVD_PLL_GAIN_reserved0_SHIFT 10
-
-/* CLKGEN :: PLL_HVD_PLL_GAIN :: LOOP_GAIN_PROPORTIONAL_IN_PHASE [09:06] */
-#define BCHP_CLKGEN_PLL_HVD_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_MASK 0x000003c0
-#define BCHP_CLKGEN_PLL_HVD_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_SHIFT 6
-#define BCHP_CLKGEN_PLL_HVD_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_DEFAULT 0x00000003
-
-/* CLKGEN :: PLL_HVD_PLL_GAIN :: LOOP_GAIN_IN_FREQ [05:03] */
-#define BCHP_CLKGEN_PLL_HVD_PLL_GAIN_LOOP_GAIN_IN_FREQ_MASK 0x00000038
-#define BCHP_CLKGEN_PLL_HVD_PLL_GAIN_LOOP_GAIN_IN_FREQ_SHIFT 3
-#define BCHP_CLKGEN_PLL_HVD_PLL_GAIN_LOOP_GAIN_IN_FREQ_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_HVD_PLL_GAIN :: LOOP_GAIN_INTEGRATOR_IN_PHASE [02:00] */
-#define BCHP_CLKGEN_PLL_HVD_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_MASK 0x00000007
-#define BCHP_CLKGEN_PLL_HVD_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_SHIFT 0
-#define BCHP_CLKGEN_PLL_HVD_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_DEFAULT 0x00000002
-
-/***************************************************************************
- *PLL_HVD_PLL_LDO_PWRON - LDO Power on
- ***************************************************************************/
-/* CLKGEN :: PLL_HVD_PLL_LDO_PWRON :: reserved0 [31:01] */
-#define BCHP_CLKGEN_PLL_HVD_PLL_LDO_PWRON_reserved0_MASK 0xfffffffe
-#define BCHP_CLKGEN_PLL_HVD_PLL_LDO_PWRON_reserved0_SHIFT 1
-
-/* CLKGEN :: PLL_HVD_PLL_LDO_PWRON :: LDO_PWRON_PLL [00:00] */
-#define BCHP_CLKGEN_PLL_HVD_PLL_LDO_PWRON_LDO_PWRON_PLL_MASK 0x00000001
-#define BCHP_CLKGEN_PLL_HVD_PLL_LDO_PWRON_LDO_PWRON_PLL_SHIFT 0
-#define BCHP_CLKGEN_PLL_HVD_PLL_LDO_PWRON_LDO_PWRON_PLL_DEFAULT 0x00000001
-
-/***************************************************************************
- *PLL_HVD_PLL_LOCK_STATUS - Lock Status
- ***************************************************************************/
-/* CLKGEN :: PLL_HVD_PLL_LOCK_STATUS :: reserved0 [31:02] */
-#define BCHP_CLKGEN_PLL_HVD_PLL_LOCK_STATUS_reserved0_MASK 0xfffffffc
-#define BCHP_CLKGEN_PLL_HVD_PLL_LOCK_STATUS_reserved0_SHIFT 2
-
-/* CLKGEN :: PLL_HVD_PLL_LOCK_STATUS :: LOCK_LOST [01:01] */
-#define BCHP_CLKGEN_PLL_HVD_PLL_LOCK_STATUS_LOCK_LOST_MASK 0x00000002
-#define BCHP_CLKGEN_PLL_HVD_PLL_LOCK_STATUS_LOCK_LOST_SHIFT 1
-
-/* CLKGEN :: PLL_HVD_PLL_LOCK_STATUS :: LOCK [00:00] */
-#define BCHP_CLKGEN_PLL_HVD_PLL_LOCK_STATUS_LOCK_MASK 0x00000001
-#define BCHP_CLKGEN_PLL_HVD_PLL_LOCK_STATUS_LOCK_SHIFT 0
-
-/***************************************************************************
- *PLL_HVD_PLL_MISC - Mscellaneous control bus.
- ***************************************************************************/
-/* CLKGEN :: PLL_HVD_PLL_MISC :: VCO_RANGE [31:30] */
-#define BCHP_CLKGEN_PLL_HVD_PLL_MISC_VCO_RANGE_MASK 0xc0000000
-#define BCHP_CLKGEN_PLL_HVD_PLL_MISC_VCO_RANGE_SHIFT 30
-#define BCHP_CLKGEN_PLL_HVD_PLL_MISC_VCO_RANGE_DEFAULT 0x00000002
-
-/* CLKGEN :: PLL_HVD_PLL_MISC :: VCO_FB_DIV2 [29:29] */
-#define BCHP_CLKGEN_PLL_HVD_PLL_MISC_VCO_FB_DIV2_MASK 0x20000000
-#define BCHP_CLKGEN_PLL_HVD_PLL_MISC_VCO_FB_DIV2_SHIFT 29
-#define BCHP_CLKGEN_PLL_HVD_PLL_MISC_VCO_FB_DIV2_DEFAULT 0x00000001
-
-/* CLKGEN :: PLL_HVD_PLL_MISC :: STAT_UPDATE [28:28] */
-#define BCHP_CLKGEN_PLL_HVD_PLL_MISC_STAT_UPDATE_MASK 0x10000000
-#define BCHP_CLKGEN_PLL_HVD_PLL_MISC_STAT_UPDATE_SHIFT 28
-#define BCHP_CLKGEN_PLL_HVD_PLL_MISC_STAT_UPDATE_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_HVD_PLL_MISC :: STAT_SELECT [27:25] */
-#define BCHP_CLKGEN_PLL_HVD_PLL_MISC_STAT_SELECT_MASK 0x0e000000
-#define BCHP_CLKGEN_PLL_HVD_PLL_MISC_STAT_SELECT_SHIFT 25
-#define BCHP_CLKGEN_PLL_HVD_PLL_MISC_STAT_SELECT_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_HVD_PLL_MISC :: STAT_RESET [24:24] */
-#define BCHP_CLKGEN_PLL_HVD_PLL_MISC_STAT_RESET_MASK 0x01000000
-#define BCHP_CLKGEN_PLL_HVD_PLL_MISC_STAT_RESET_SHIFT 24
-#define BCHP_CLKGEN_PLL_HVD_PLL_MISC_STAT_RESET_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_HVD_PLL_MISC :: STAT_MODE [23:22] */
-#define BCHP_CLKGEN_PLL_HVD_PLL_MISC_STAT_MODE_MASK 0x00c00000
-#define BCHP_CLKGEN_PLL_HVD_PLL_MISC_STAT_MODE_SHIFT 22
-#define BCHP_CLKGEN_PLL_HVD_PLL_MISC_STAT_MODE_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_HVD_PLL_MISC :: PWM_RATE [21:20] */
-#define BCHP_CLKGEN_PLL_HVD_PLL_MISC_PWM_RATE_MASK 0x00300000
-#define BCHP_CLKGEN_PLL_HVD_PLL_MISC_PWM_RATE_SHIFT 20
-#define BCHP_CLKGEN_PLL_HVD_PLL_MISC_PWM_RATE_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_HVD_PLL_MISC :: POST_CTRL_RESETB [19:18] */
-#define BCHP_CLKGEN_PLL_HVD_PLL_MISC_POST_CTRL_RESETB_MASK 0x000c0000
-#define BCHP_CLKGEN_PLL_HVD_PLL_MISC_POST_CTRL_RESETB_SHIFT 18
-#define BCHP_CLKGEN_PLL_HVD_PLL_MISC_POST_CTRL_RESETB_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_HVD_PLL_MISC :: PLLRESERVED2 [17:16] */
-#define BCHP_CLKGEN_PLL_HVD_PLL_MISC_PLLRESERVED2_MASK 0x00030000
-#define BCHP_CLKGEN_PLL_HVD_PLL_MISC_PLLRESERVED2_SHIFT 16
-#define BCHP_CLKGEN_PLL_HVD_PLL_MISC_PLLRESERVED2_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_HVD_PLL_MISC :: PLLRESERVED1 [15:15] */
-#define BCHP_CLKGEN_PLL_HVD_PLL_MISC_PLLRESERVED1_MASK 0x00008000
-#define BCHP_CLKGEN_PLL_HVD_PLL_MISC_PLLRESERVED1_SHIFT 15
-#define BCHP_CLKGEN_PLL_HVD_PLL_MISC_PLLRESERVED1_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_HVD_PLL_MISC :: NDIV_RELOCK [14:14] */
-#define BCHP_CLKGEN_PLL_HVD_PLL_MISC_NDIV_RELOCK_MASK 0x00004000
-#define BCHP_CLKGEN_PLL_HVD_PLL_MISC_NDIV_RELOCK_SHIFT 14
-#define BCHP_CLKGEN_PLL_HVD_PLL_MISC_NDIV_RELOCK_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_HVD_PLL_MISC :: FAST_LOCK [13:13] */
-#define BCHP_CLKGEN_PLL_HVD_PLL_MISC_FAST_LOCK_MASK 0x00002000
-#define BCHP_CLKGEN_PLL_HVD_PLL_MISC_FAST_LOCK_SHIFT 13
-#define BCHP_CLKGEN_PLL_HVD_PLL_MISC_FAST_LOCK_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_HVD_PLL_MISC :: DCO_CTRL_BYPASS_ENABLE [12:12] */
-#define BCHP_CLKGEN_PLL_HVD_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_MASK 0x00001000
-#define BCHP_CLKGEN_PLL_HVD_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_SHIFT 12
-#define BCHP_CLKGEN_PLL_HVD_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_HVD_PLL_MISC :: DCO_CTRL_BYPASS [11:00] */
-#define BCHP_CLKGEN_PLL_HVD_PLL_MISC_DCO_CTRL_BYPASS_MASK 0x00000fff
-#define BCHP_CLKGEN_PLL_HVD_PLL_MISC_DCO_CTRL_BYPASS_SHIFT 0
-#define BCHP_CLKGEN_PLL_HVD_PLL_MISC_DCO_CTRL_BYPASS_DEFAULT 0x00000000
-
-/***************************************************************************
- *PLL_HVD_PLL_MISC2 - Mscellaneous control bus continued.
- ***************************************************************************/
-/* CLKGEN :: PLL_HVD_PLL_MISC2 :: PLLRESERVED0 [31:00] */
-#define BCHP_CLKGEN_PLL_HVD_PLL_MISC2_PLLRESERVED0_MASK 0xffffffff
-#define BCHP_CLKGEN_PLL_HVD_PLL_MISC2_PLLRESERVED0_SHIFT 0
-#define BCHP_CLKGEN_PLL_HVD_PLL_MISC2_PLLRESERVED0_DEFAULT 0x00000001
-
-/***************************************************************************
- *PLL_HVD_PLL_PWRON - Poweron
- ***************************************************************************/
-/* CLKGEN :: PLL_HVD_PLL_PWRON :: reserved0 [31:01] */
-#define BCHP_CLKGEN_PLL_HVD_PLL_PWRON_reserved0_MASK 0xfffffffe
-#define BCHP_CLKGEN_PLL_HVD_PLL_PWRON_reserved0_SHIFT 1
-
-/* CLKGEN :: PLL_HVD_PLL_PWRON :: PWRON_PLL [00:00] */
-#define BCHP_CLKGEN_PLL_HVD_PLL_PWRON_PWRON_PLL_MASK 0x00000001
-#define BCHP_CLKGEN_PLL_HVD_PLL_PWRON_PWRON_PLL_SHIFT 0
-#define BCHP_CLKGEN_PLL_HVD_PLL_PWRON_PWRON_PLL_DEFAULT 0x00000001
-
-/***************************************************************************
- *PLL_HVD_PLL_RESET - Resets
- ***************************************************************************/
-/* CLKGEN :: PLL_HVD_PLL_RESET :: reserved0 [31:02] */
-#define BCHP_CLKGEN_PLL_HVD_PLL_RESET_reserved0_MASK 0xfffffffc
-#define BCHP_CLKGEN_PLL_HVD_PLL_RESET_reserved0_SHIFT 2
-
-/* CLKGEN :: PLL_HVD_PLL_RESET :: RESETD [01:01] */
-#define BCHP_CLKGEN_PLL_HVD_PLL_RESET_RESETD_MASK 0x00000002
-#define BCHP_CLKGEN_PLL_HVD_PLL_RESET_RESETD_SHIFT 1
-#define BCHP_CLKGEN_PLL_HVD_PLL_RESET_RESETD_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_HVD_PLL_RESET :: RESETA [00:00] */
-#define BCHP_CLKGEN_PLL_HVD_PLL_RESET_RESETA_MASK 0x00000001
-#define BCHP_CLKGEN_PLL_HVD_PLL_RESET_RESETA_SHIFT 0
-#define BCHP_CLKGEN_PLL_HVD_PLL_RESET_RESETA_DEFAULT 0x00000000
-
-/***************************************************************************
- *PLL_HVD_PLL_SSC_MODE_CONTROL_HIGH - Higher bits of Spread Spectrum mode control
- ***************************************************************************/
-/* CLKGEN :: PLL_HVD_PLL_SSC_MODE_CONTROL_HIGH :: reserved0 [31:16] */
-#define BCHP_CLKGEN_PLL_HVD_PLL_SSC_MODE_CONTROL_HIGH_reserved0_MASK 0xffff0000
-#define BCHP_CLKGEN_PLL_HVD_PLL_SSC_MODE_CONTROL_HIGH_reserved0_SHIFT 16
-
-/* CLKGEN :: PLL_HVD_PLL_SSC_MODE_CONTROL_HIGH :: SSC_STEP [15:00] */
-#define BCHP_CLKGEN_PLL_HVD_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_MASK 0x0000ffff
-#define BCHP_CLKGEN_PLL_HVD_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_SHIFT 0
-#define BCHP_CLKGEN_PLL_HVD_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *PLL_HVD_PLL_SSC_MODE_CONTROL_LOW - Lower bits of Spread Spectrum mode control
- ***************************************************************************/
-/* CLKGEN :: PLL_HVD_PLL_SSC_MODE_CONTROL_LOW :: reserved0 [31:23] */
-#define BCHP_CLKGEN_PLL_HVD_PLL_SSC_MODE_CONTROL_LOW_reserved0_MASK 0xff800000
-#define BCHP_CLKGEN_PLL_HVD_PLL_SSC_MODE_CONTROL_LOW_reserved0_SHIFT 23
-
-/* CLKGEN :: PLL_HVD_PLL_SSC_MODE_CONTROL_LOW :: SSC_MODE [22:22] */
-#define BCHP_CLKGEN_PLL_HVD_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_MASK 0x00400000
-#define BCHP_CLKGEN_PLL_HVD_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_SHIFT 22
-#define BCHP_CLKGEN_PLL_HVD_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_HVD_PLL_SSC_MODE_CONTROL_LOW :: SSC_LIMIT [21:00] */
-#define BCHP_CLKGEN_PLL_HVD_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_MASK 0x003fffff
-#define BCHP_CLKGEN_PLL_HVD_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_SHIFT 0
-#define BCHP_CLKGEN_PLL_HVD_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_DEFAULT 0x00000000
-
-/***************************************************************************
- *PLL_HVD_PLL_STATUS - Status
- ***************************************************************************/
-/* CLKGEN :: PLL_HVD_PLL_STATUS :: reserved0 [31:12] */
-#define BCHP_CLKGEN_PLL_HVD_PLL_STATUS_reserved0_MASK 0xfffff000
-#define BCHP_CLKGEN_PLL_HVD_PLL_STATUS_reserved0_SHIFT 12
-
-/* CLKGEN :: PLL_HVD_PLL_STATUS :: TEST_STATUS [11:00] */
-#define BCHP_CLKGEN_PLL_HVD_PLL_STATUS_TEST_STATUS_MASK 0x00000fff
-#define BCHP_CLKGEN_PLL_HVD_PLL_STATUS_TEST_STATUS_SHIFT 0
-
-/***************************************************************************
- *PLL_LC_PLL_CHANNEL_CTRL_CH_0 - PLL CHANNEL control CH 0
- ***************************************************************************/
-/* CLKGEN :: PLL_LC_PLL_CHANNEL_CTRL_CH_0 :: reserved0 [31:11] */
-#define BCHP_CLKGEN_PLL_LC_PLL_CHANNEL_CTRL_CH_0_reserved0_MASK 0xfffff800
-#define BCHP_CLKGEN_PLL_LC_PLL_CHANNEL_CTRL_CH_0_reserved0_SHIFT 11
-
-/* CLKGEN :: PLL_LC_PLL_CHANNEL_CTRL_CH_0 :: POST_DIVIDER_HOLD_CH0 [10:10] */
-#define BCHP_CLKGEN_PLL_LC_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_MASK 0x00000400
-#define BCHP_CLKGEN_PLL_LC_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_SHIFT 10
-#define BCHP_CLKGEN_PLL_LC_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_LC_PLL_CHANNEL_CTRL_CH_0 :: PHASE_OFFSET_CH0 [09:09] */
-#define BCHP_CLKGEN_PLL_LC_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_MASK 0x00000200
-#define BCHP_CLKGEN_PLL_LC_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_SHIFT 9
-#define BCHP_CLKGEN_PLL_LC_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_LC_PLL_CHANNEL_CTRL_CH_0 :: MDIV_CH0 [08:01] */
-#define BCHP_CLKGEN_PLL_LC_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_MASK 0x000001fe
-#define BCHP_CLKGEN_PLL_LC_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_SHIFT 1
-#define BCHP_CLKGEN_PLL_LC_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_DEFAULT 0x0000006c
-
-/* CLKGEN :: PLL_LC_PLL_CHANNEL_CTRL_CH_0 :: CLOCK_DIS_CH0 [00:00] */
-#define BCHP_CLKGEN_PLL_LC_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_MASK 0x00000001
-#define BCHP_CLKGEN_PLL_LC_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_SHIFT 0
-#define BCHP_CLKGEN_PLL_LC_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_DEFAULT 0x00000000
-
-/***************************************************************************
- *PLL_LC_PLL_CHANNEL_CTRL_CH_1 - PLL CHANNEL control CH 1
- ***************************************************************************/
-/* CLKGEN :: PLL_LC_PLL_CHANNEL_CTRL_CH_1 :: reserved0 [31:11] */
-#define BCHP_CLKGEN_PLL_LC_PLL_CHANNEL_CTRL_CH_1_reserved0_MASK 0xfffff800
-#define BCHP_CLKGEN_PLL_LC_PLL_CHANNEL_CTRL_CH_1_reserved0_SHIFT 11
-
-/* CLKGEN :: PLL_LC_PLL_CHANNEL_CTRL_CH_1 :: POST_DIVIDER_HOLD_CH1 [10:10] */
-#define BCHP_CLKGEN_PLL_LC_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_MASK 0x00000400
-#define BCHP_CLKGEN_PLL_LC_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_SHIFT 10
-#define BCHP_CLKGEN_PLL_LC_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_LC_PLL_CHANNEL_CTRL_CH_1 :: PHASE_OFFSET_CH1 [09:09] */
-#define BCHP_CLKGEN_PLL_LC_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_MASK 0x00000200
-#define BCHP_CLKGEN_PLL_LC_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_SHIFT 9
-#define BCHP_CLKGEN_PLL_LC_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_LC_PLL_CHANNEL_CTRL_CH_1 :: MDIV_CH1 [08:01] */
-#define BCHP_CLKGEN_PLL_LC_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_MASK 0x000001fe
-#define BCHP_CLKGEN_PLL_LC_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_SHIFT 1
-#define BCHP_CLKGEN_PLL_LC_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_DEFAULT 0x0000002d
-
-/* CLKGEN :: PLL_LC_PLL_CHANNEL_CTRL_CH_1 :: CLOCK_DIS_CH1 [00:00] */
-#define BCHP_CLKGEN_PLL_LC_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_MASK 0x00000001
-#define BCHP_CLKGEN_PLL_LC_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_SHIFT 0
-#define BCHP_CLKGEN_PLL_LC_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_DEFAULT 0x00000000
-
-/***************************************************************************
- *PLL_LC_PLL_CHANNEL_CTRL_CH_2 - PLL CHANNEL control CH 2
- ***************************************************************************/
-/* CLKGEN :: PLL_LC_PLL_CHANNEL_CTRL_CH_2 :: reserved0 [31:11] */
-#define BCHP_CLKGEN_PLL_LC_PLL_CHANNEL_CTRL_CH_2_reserved0_MASK 0xfffff800
-#define BCHP_CLKGEN_PLL_LC_PLL_CHANNEL_CTRL_CH_2_reserved0_SHIFT 11
-
-/* CLKGEN :: PLL_LC_PLL_CHANNEL_CTRL_CH_2 :: POST_DIVIDER_HOLD_CH2 [10:10] */
-#define BCHP_CLKGEN_PLL_LC_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_HOLD_CH2_MASK 0x00000400
-#define BCHP_CLKGEN_PLL_LC_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_HOLD_CH2_SHIFT 10
-#define BCHP_CLKGEN_PLL_LC_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_HOLD_CH2_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_LC_PLL_CHANNEL_CTRL_CH_2 :: PHASE_OFFSET_CH2 [09:09] */
-#define BCHP_CLKGEN_PLL_LC_PLL_CHANNEL_CTRL_CH_2_PHASE_OFFSET_CH2_MASK 0x00000200
-#define BCHP_CLKGEN_PLL_LC_PLL_CHANNEL_CTRL_CH_2_PHASE_OFFSET_CH2_SHIFT 9
-#define BCHP_CLKGEN_PLL_LC_PLL_CHANNEL_CTRL_CH_2_PHASE_OFFSET_CH2_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_LC_PLL_CHANNEL_CTRL_CH_2 :: MDIV_CH2 [08:01] */
-#define BCHP_CLKGEN_PLL_LC_PLL_CHANNEL_CTRL_CH_2_MDIV_CH2_MASK 0x000001fe
-#define BCHP_CLKGEN_PLL_LC_PLL_CHANNEL_CTRL_CH_2_MDIV_CH2_SHIFT 1
-#define BCHP_CLKGEN_PLL_LC_PLL_CHANNEL_CTRL_CH_2_MDIV_CH2_DEFAULT 0x0000002d
-
-/* CLKGEN :: PLL_LC_PLL_CHANNEL_CTRL_CH_2 :: CLOCK_DIS_CH2 [00:00] */
-#define BCHP_CLKGEN_PLL_LC_PLL_CHANNEL_CTRL_CH_2_CLOCK_DIS_CH2_MASK 0x00000001
-#define BCHP_CLKGEN_PLL_LC_PLL_CHANNEL_CTRL_CH_2_CLOCK_DIS_CH2_SHIFT 0
-#define BCHP_CLKGEN_PLL_LC_PLL_CHANNEL_CTRL_CH_2_CLOCK_DIS_CH2_DEFAULT 0x00000000
-
-/***************************************************************************
- *PLL_LC_PLL_CHANNEL_CTRL_CH_4 - PLL CHANNEL control CH 4
- ***************************************************************************/
-/* CLKGEN :: PLL_LC_PLL_CHANNEL_CTRL_CH_4 :: reserved0 [31:11] */
-#define BCHP_CLKGEN_PLL_LC_PLL_CHANNEL_CTRL_CH_4_reserved0_MASK 0xfffff800
-#define BCHP_CLKGEN_PLL_LC_PLL_CHANNEL_CTRL_CH_4_reserved0_SHIFT 11
-
-/* CLKGEN :: PLL_LC_PLL_CHANNEL_CTRL_CH_4 :: POST_DIVIDER_HOLD_CH4 [10:10] */
-#define BCHP_CLKGEN_PLL_LC_PLL_CHANNEL_CTRL_CH_4_POST_DIVIDER_HOLD_CH4_MASK 0x00000400
-#define BCHP_CLKGEN_PLL_LC_PLL_CHANNEL_CTRL_CH_4_POST_DIVIDER_HOLD_CH4_SHIFT 10
-#define BCHP_CLKGEN_PLL_LC_PLL_CHANNEL_CTRL_CH_4_POST_DIVIDER_HOLD_CH4_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_LC_PLL_CHANNEL_CTRL_CH_4 :: PHASE_OFFSET_CH4 [09:09] */
-#define BCHP_CLKGEN_PLL_LC_PLL_CHANNEL_CTRL_CH_4_PHASE_OFFSET_CH4_MASK 0x00000200
-#define BCHP_CLKGEN_PLL_LC_PLL_CHANNEL_CTRL_CH_4_PHASE_OFFSET_CH4_SHIFT 9
-#define BCHP_CLKGEN_PLL_LC_PLL_CHANNEL_CTRL_CH_4_PHASE_OFFSET_CH4_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_LC_PLL_CHANNEL_CTRL_CH_4 :: MDIV_CH4 [08:01] */
-#define BCHP_CLKGEN_PLL_LC_PLL_CHANNEL_CTRL_CH_4_MDIV_CH4_MASK 0x000001fe
-#define BCHP_CLKGEN_PLL_LC_PLL_CHANNEL_CTRL_CH_4_MDIV_CH4_SHIFT 1
-#define BCHP_CLKGEN_PLL_LC_PLL_CHANNEL_CTRL_CH_4_MDIV_CH4_DEFAULT 0x00000036
-
-/* CLKGEN :: PLL_LC_PLL_CHANNEL_CTRL_CH_4 :: CLOCK_DIS_CH4 [00:00] */
-#define BCHP_CLKGEN_PLL_LC_PLL_CHANNEL_CTRL_CH_4_CLOCK_DIS_CH4_MASK 0x00000001
-#define BCHP_CLKGEN_PLL_LC_PLL_CHANNEL_CTRL_CH_4_CLOCK_DIS_CH4_SHIFT 0
-#define BCHP_CLKGEN_PLL_LC_PLL_CHANNEL_CTRL_CH_4_CLOCK_DIS_CH4_DEFAULT 0x00000000
-
-/***************************************************************************
- *PLL_LC_PLL_CHANNEL_CTRL_CH_5 - PLL CHANNEL control CH 5
- ***************************************************************************/
-/* CLKGEN :: PLL_LC_PLL_CHANNEL_CTRL_CH_5 :: reserved0 [31:11] */
-#define BCHP_CLKGEN_PLL_LC_PLL_CHANNEL_CTRL_CH_5_reserved0_MASK 0xfffff800
-#define BCHP_CLKGEN_PLL_LC_PLL_CHANNEL_CTRL_CH_5_reserved0_SHIFT 11
-
-/* CLKGEN :: PLL_LC_PLL_CHANNEL_CTRL_CH_5 :: POST_DIVIDER_HOLD_CH5 [10:10] */
-#define BCHP_CLKGEN_PLL_LC_PLL_CHANNEL_CTRL_CH_5_POST_DIVIDER_HOLD_CH5_MASK 0x00000400
-#define BCHP_CLKGEN_PLL_LC_PLL_CHANNEL_CTRL_CH_5_POST_DIVIDER_HOLD_CH5_SHIFT 10
-#define BCHP_CLKGEN_PLL_LC_PLL_CHANNEL_CTRL_CH_5_POST_DIVIDER_HOLD_CH5_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_LC_PLL_CHANNEL_CTRL_CH_5 :: PHASE_OFFSET_CH5 [09:09] */
-#define BCHP_CLKGEN_PLL_LC_PLL_CHANNEL_CTRL_CH_5_PHASE_OFFSET_CH5_MASK 0x00000200
-#define BCHP_CLKGEN_PLL_LC_PLL_CHANNEL_CTRL_CH_5_PHASE_OFFSET_CH5_SHIFT 9
-#define BCHP_CLKGEN_PLL_LC_PLL_CHANNEL_CTRL_CH_5_PHASE_OFFSET_CH5_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_LC_PLL_CHANNEL_CTRL_CH_5 :: MDIV_CH5 [08:01] */
-#define BCHP_CLKGEN_PLL_LC_PLL_CHANNEL_CTRL_CH_5_MDIV_CH5_MASK 0x000001fe
-#define BCHP_CLKGEN_PLL_LC_PLL_CHANNEL_CTRL_CH_5_MDIV_CH5_SHIFT 1
-#define BCHP_CLKGEN_PLL_LC_PLL_CHANNEL_CTRL_CH_5_MDIV_CH5_DEFAULT 0x00000036
-
-/* CLKGEN :: PLL_LC_PLL_CHANNEL_CTRL_CH_5 :: CLOCK_DIS_CH5 [00:00] */
-#define BCHP_CLKGEN_PLL_LC_PLL_CHANNEL_CTRL_CH_5_CLOCK_DIS_CH5_MASK 0x00000001
-#define BCHP_CLKGEN_PLL_LC_PLL_CHANNEL_CTRL_CH_5_CLOCK_DIS_CH5_SHIFT 0
-#define BCHP_CLKGEN_PLL_LC_PLL_CHANNEL_CTRL_CH_5_CLOCK_DIS_CH5_DEFAULT 0x00000001
-
-/***************************************************************************
- *PLL_LC_PLL_CONTROL - Miscellaneous Controls
- ***************************************************************************/
-/* CLKGEN :: PLL_LC_PLL_CONTROL :: reserved0 [31:01] */
-#define BCHP_CLKGEN_PLL_LC_PLL_CONTROL_reserved0_MASK 0xfffffffe
-#define BCHP_CLKGEN_PLL_LC_PLL_CONTROL_reserved0_SHIFT 1
-
-/* CLKGEN :: PLL_LC_PLL_CONTROL :: REF_SEL [00:00] */
-#define BCHP_CLKGEN_PLL_LC_PLL_CONTROL_REF_SEL_MASK 0x00000001
-#define BCHP_CLKGEN_PLL_LC_PLL_CONTROL_REF_SEL_SHIFT 0
-#define BCHP_CLKGEN_PLL_LC_PLL_CONTROL_REF_SEL_DEFAULT 0x00000000
-
-/***************************************************************************
- *PLL_LC_PLL_DIV - Pre multiplier
- ***************************************************************************/
-/* CLKGEN :: PLL_LC_PLL_DIV :: reserved0 [31:14] */
-#define BCHP_CLKGEN_PLL_LC_PLL_DIV_reserved0_MASK 0xffffc000
-#define BCHP_CLKGEN_PLL_LC_PLL_DIV_reserved0_SHIFT 14
-
-/* CLKGEN :: PLL_LC_PLL_DIV :: PDIV [13:10] */
-#define BCHP_CLKGEN_PLL_LC_PLL_DIV_PDIV_MASK 0x00003c00
-#define BCHP_CLKGEN_PLL_LC_PLL_DIV_PDIV_SHIFT 10
-#define BCHP_CLKGEN_PLL_LC_PLL_DIV_PDIV_DEFAULT 0x00000002
-
-/* CLKGEN :: PLL_LC_PLL_DIV :: NDIV_INT [09:00] */
-#define BCHP_CLKGEN_PLL_LC_PLL_DIV_NDIV_INT_MASK 0x000003ff
-#define BCHP_CLKGEN_PLL_LC_PLL_DIV_NDIV_INT_SHIFT 0
-#define BCHP_CLKGEN_PLL_LC_PLL_DIV_NDIV_INT_DEFAULT 0x00000064
-
-/***************************************************************************
- *PLL_LC_PLL_GAIN - PLL GAIN
- ***************************************************************************/
-/* CLKGEN :: PLL_LC_PLL_GAIN :: reserved0 [31:07] */
-#define BCHP_CLKGEN_PLL_LC_PLL_GAIN_reserved0_MASK 0xffffff80
-#define BCHP_CLKGEN_PLL_LC_PLL_GAIN_reserved0_SHIFT 7
-
-/* CLKGEN :: PLL_LC_PLL_GAIN :: LOOP_GAIN_PROPORTIONAL_IN_PHASE [06:03] */
-#define BCHP_CLKGEN_PLL_LC_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_MASK 0x00000078
-#define BCHP_CLKGEN_PLL_LC_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_SHIFT 3
-#define BCHP_CLKGEN_PLL_LC_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_DEFAULT 0x00000006
-
-/* CLKGEN :: PLL_LC_PLL_GAIN :: LOOP_GAIN_INTEGRATOR_IN_PHASE [02:00] */
-#define BCHP_CLKGEN_PLL_LC_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_MASK 0x00000007
-#define BCHP_CLKGEN_PLL_LC_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_SHIFT 0
-#define BCHP_CLKGEN_PLL_LC_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_DEFAULT 0x00000002
-
-/***************************************************************************
- *PLL_LC_PLL_HOLD_CH_ALL - Hold PLL all channels
- ***************************************************************************/
-/* CLKGEN :: PLL_LC_PLL_HOLD_CH_ALL :: reserved0 [31:01] */
-#define BCHP_CLKGEN_PLL_LC_PLL_HOLD_CH_ALL_reserved0_MASK 0xfffffffe
-#define BCHP_CLKGEN_PLL_LC_PLL_HOLD_CH_ALL_reserved0_SHIFT 1
-
-/* CLKGEN :: PLL_LC_PLL_HOLD_CH_ALL :: HOLD_CH_ALL [00:00] */
-#define BCHP_CLKGEN_PLL_LC_PLL_HOLD_CH_ALL_HOLD_CH_ALL_MASK 0x00000001
-#define BCHP_CLKGEN_PLL_LC_PLL_HOLD_CH_ALL_HOLD_CH_ALL_SHIFT 0
-#define BCHP_CLKGEN_PLL_LC_PLL_HOLD_CH_ALL_HOLD_CH_ALL_DEFAULT 0x00000000
-
-/***************************************************************************
- *PLL_LC_PLL_LDO_CTRL - Ldo voltage control
- ***************************************************************************/
-/* CLKGEN :: PLL_LC_PLL_LDO_CTRL :: reserved0 [31:06] */
-#define BCHP_CLKGEN_PLL_LC_PLL_LDO_CTRL_reserved0_MASK 0xffffffc0
-#define BCHP_CLKGEN_PLL_LC_PLL_LDO_CTRL_reserved0_SHIFT 6
-
-/* CLKGEN :: PLL_LC_PLL_LDO_CTRL :: LDO_CTRL [05:00] */
-#define BCHP_CLKGEN_PLL_LC_PLL_LDO_CTRL_LDO_CTRL_MASK 0x0000003f
-#define BCHP_CLKGEN_PLL_LC_PLL_LDO_CTRL_LDO_CTRL_SHIFT 0
-#define BCHP_CLKGEN_PLL_LC_PLL_LDO_CTRL_LDO_CTRL_DEFAULT 0x00000000
-
-/***************************************************************************
- *PLL_LC_PLL_LDO_PWRON - LDO Power on
- ***************************************************************************/
-/* CLKGEN :: PLL_LC_PLL_LDO_PWRON :: reserved0 [31:01] */
-#define BCHP_CLKGEN_PLL_LC_PLL_LDO_PWRON_reserved0_MASK 0xfffffffe
-#define BCHP_CLKGEN_PLL_LC_PLL_LDO_PWRON_reserved0_SHIFT 1
-
-/* CLKGEN :: PLL_LC_PLL_LDO_PWRON :: LDO_PWRON_PLL [00:00] */
-#define BCHP_CLKGEN_PLL_LC_PLL_LDO_PWRON_LDO_PWRON_PLL_MASK 0x00000001
-#define BCHP_CLKGEN_PLL_LC_PLL_LDO_PWRON_LDO_PWRON_PLL_SHIFT 0
-#define BCHP_CLKGEN_PLL_LC_PLL_LDO_PWRON_LDO_PWRON_PLL_DEFAULT 0x00000001
-
-/***************************************************************************
- *PLL_LC_PLL_LOCK_STATUS - Lock Status
- ***************************************************************************/
-/* CLKGEN :: PLL_LC_PLL_LOCK_STATUS :: reserved0 [31:01] */
-#define BCHP_CLKGEN_PLL_LC_PLL_LOCK_STATUS_reserved0_MASK 0xfffffffe
-#define BCHP_CLKGEN_PLL_LC_PLL_LOCK_STATUS_reserved0_SHIFT 1
-
-/* CLKGEN :: PLL_LC_PLL_LOCK_STATUS :: LOCK [00:00] */
-#define BCHP_CLKGEN_PLL_LC_PLL_LOCK_STATUS_LOCK_MASK 0x00000001
-#define BCHP_CLKGEN_PLL_LC_PLL_LOCK_STATUS_LOCK_SHIFT 0
-
-/***************************************************************************
- *PLL_LC_PLL_MISC - Mscellaneous control bus.
- ***************************************************************************/
-/* CLKGEN :: PLL_LC_PLL_MISC :: VCO_PREDIV_RATIO [31:31] */
-#define BCHP_CLKGEN_PLL_LC_PLL_MISC_VCO_PREDIV_RATIO_MASK 0x80000000
-#define BCHP_CLKGEN_PLL_LC_PLL_MISC_VCO_PREDIV_RATIO_SHIFT 31
-#define BCHP_CLKGEN_PLL_LC_PLL_MISC_VCO_PREDIV_RATIO_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_LC_PLL_MISC :: T2D_DELAY_SEL_LOW [30:28] */
-#define BCHP_CLKGEN_PLL_LC_PLL_MISC_T2D_DELAY_SEL_LOW_MASK 0x70000000
-#define BCHP_CLKGEN_PLL_LC_PLL_MISC_T2D_DELAY_SEL_LOW_SHIFT 28
-#define BCHP_CLKGEN_PLL_LC_PLL_MISC_T2D_DELAY_SEL_LOW_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_LC_PLL_MISC :: SEL_MEASURE_UNIT [27:25] */
-#define BCHP_CLKGEN_PLL_LC_PLL_MISC_SEL_MEASURE_UNIT_MASK 0x0e000000
-#define BCHP_CLKGEN_PLL_LC_PLL_MISC_SEL_MEASURE_UNIT_SHIFT 25
-#define BCHP_CLKGEN_PLL_LC_PLL_MISC_SEL_MEASURE_UNIT_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_LC_PLL_MISC :: RESET_MEASURE_MODE [24:24] */
-#define BCHP_CLKGEN_PLL_LC_PLL_MISC_RESET_MEASURE_MODE_MASK 0x01000000
-#define BCHP_CLKGEN_PLL_LC_PLL_MISC_RESET_MEASURE_MODE_SHIFT 24
-#define BCHP_CLKGEN_PLL_LC_PLL_MISC_RESET_MEASURE_MODE_DEFAULT 0x00000001
-
-/* CLKGEN :: PLL_LC_PLL_MISC :: LOAD_DCO_BYP_WORD [23:23] */
-#define BCHP_CLKGEN_PLL_LC_PLL_MISC_LOAD_DCO_BYP_WORD_MASK 0x00800000
-#define BCHP_CLKGEN_PLL_LC_PLL_MISC_LOAD_DCO_BYP_WORD_SHIFT 23
-#define BCHP_CLKGEN_PLL_LC_PLL_MISC_LOAD_DCO_BYP_WORD_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_LC_PLL_MISC :: FREQ_BYP_WORD [22:07] */
-#define BCHP_CLKGEN_PLL_LC_PLL_MISC_FREQ_BYP_WORD_MASK 0x007fff80
-#define BCHP_CLKGEN_PLL_LC_PLL_MISC_FREQ_BYP_WORD_SHIFT 7
-#define BCHP_CLKGEN_PLL_LC_PLL_MISC_FREQ_BYP_WORD_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_LC_PLL_MISC :: EN_VCO_OUTPUT [06:06] */
-#define BCHP_CLKGEN_PLL_LC_PLL_MISC_EN_VCO_OUTPUT_MASK 0x00000040
-#define BCHP_CLKGEN_PLL_LC_PLL_MISC_EN_VCO_OUTPUT_SHIFT 6
-#define BCHP_CLKGEN_PLL_LC_PLL_MISC_EN_VCO_OUTPUT_DEFAULT 0x00000001
-
-/* CLKGEN :: PLL_LC_PLL_MISC :: EN_DCO_BYP_WORD [05:05] */
-#define BCHP_CLKGEN_PLL_LC_PLL_MISC_EN_DCO_BYP_WORD_MASK 0x00000020
-#define BCHP_CLKGEN_PLL_LC_PLL_MISC_EN_DCO_BYP_WORD_SHIFT 5
-#define BCHP_CLKGEN_PLL_LC_PLL_MISC_EN_DCO_BYP_WORD_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_LC_PLL_MISC :: EN_BANGBANG_MODE [04:04] */
-#define BCHP_CLKGEN_PLL_LC_PLL_MISC_EN_BANGBANG_MODE_MASK 0x00000010
-#define BCHP_CLKGEN_PLL_LC_PLL_MISC_EN_BANGBANG_MODE_SHIFT 4
-#define BCHP_CLKGEN_PLL_LC_PLL_MISC_EN_BANGBANG_MODE_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_LC_PLL_MISC :: CTRL_MEASURE_MODE [03:02] */
-#define BCHP_CLKGEN_PLL_LC_PLL_MISC_CTRL_MEASURE_MODE_MASK 0x0000000c
-#define BCHP_CLKGEN_PLL_LC_PLL_MISC_CTRL_MEASURE_MODE_SHIFT 2
-#define BCHP_CLKGEN_PLL_LC_PLL_MISC_CTRL_MEASURE_MODE_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_LC_PLL_MISC :: CHANGE_MEASURE_UNIT [01:01] */
-#define BCHP_CLKGEN_PLL_LC_PLL_MISC_CHANGE_MEASURE_UNIT_MASK 0x00000002
-#define BCHP_CLKGEN_PLL_LC_PLL_MISC_CHANGE_MEASURE_UNIT_SHIFT 1
-#define BCHP_CLKGEN_PLL_LC_PLL_MISC_CHANGE_MEASURE_UNIT_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_LC_PLL_MISC :: BOOST_BIAS_CIRCUIT [00:00] */
-#define BCHP_CLKGEN_PLL_LC_PLL_MISC_BOOST_BIAS_CIRCUIT_MASK 0x00000001
-#define BCHP_CLKGEN_PLL_LC_PLL_MISC_BOOST_BIAS_CIRCUIT_SHIFT 0
-#define BCHP_CLKGEN_PLL_LC_PLL_MISC_BOOST_BIAS_CIRCUIT_DEFAULT 0x00000000
-
-/***************************************************************************
- *PLL_LC_PLL_MISC2 - Mscellaneous control bus continued.
- ***************************************************************************/
-/* CLKGEN :: PLL_LC_PLL_MISC2 :: T2D_DELAY_SEL_HIGH [31:31] */
-#define BCHP_CLKGEN_PLL_LC_PLL_MISC2_T2D_DELAY_SEL_HIGH_MASK 0x80000000
-#define BCHP_CLKGEN_PLL_LC_PLL_MISC2_T2D_DELAY_SEL_HIGH_SHIFT 31
-#define BCHP_CLKGEN_PLL_LC_PLL_MISC2_T2D_DELAY_SEL_HIGH_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_LC_PLL_MISC2 :: SEL_TEST_CLK [30:30] */
-#define BCHP_CLKGEN_PLL_LC_PLL_MISC2_SEL_TEST_CLK_MASK 0x40000000
-#define BCHP_CLKGEN_PLL_LC_PLL_MISC2_SEL_TEST_CLK_SHIFT 30
-#define BCHP_CLKGEN_PLL_LC_PLL_MISC2_SEL_TEST_CLK_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_LC_PLL_MISC2 :: SEL_DIFF_REFCLK_SRC [29:29] */
-#define BCHP_CLKGEN_PLL_LC_PLL_MISC2_SEL_DIFF_REFCLK_SRC_MASK 0x20000000
-#define BCHP_CLKGEN_PLL_LC_PLL_MISC2_SEL_DIFF_REFCLK_SRC_SHIFT 29
-#define BCHP_CLKGEN_PLL_LC_PLL_MISC2_SEL_DIFF_REFCLK_SRC_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_LC_PLL_MISC2 :: PLLRESERVED0 [28:11] */
-#define BCHP_CLKGEN_PLL_LC_PLL_MISC2_PLLRESERVED0_MASK 0x1ffff800
-#define BCHP_CLKGEN_PLL_LC_PLL_MISC2_PLLRESERVED0_SHIFT 11
-#define BCHP_CLKGEN_PLL_LC_PLL_MISC2_PLLRESERVED0_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_LC_PLL_MISC2 :: INTERNAL_RESET_MODE [10:09] */
-#define BCHP_CLKGEN_PLL_LC_PLL_MISC2_INTERNAL_RESET_MODE_MASK 0x00000600
-#define BCHP_CLKGEN_PLL_LC_PLL_MISC2_INTERNAL_RESET_MODE_SHIFT 9
-#define BCHP_CLKGEN_PLL_LC_PLL_MISC2_INTERNAL_RESET_MODE_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_LC_PLL_MISC2 :: EN_TEST_CLK [08:08] */
-#define BCHP_CLKGEN_PLL_LC_PLL_MISC2_EN_TEST_CLK_MASK 0x00000100
-#define BCHP_CLKGEN_PLL_LC_PLL_MISC2_EN_TEST_CLK_SHIFT 8
-#define BCHP_CLKGEN_PLL_LC_PLL_MISC2_EN_TEST_CLK_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_LC_PLL_MISC2 :: EN_BYPCLK_1 [07:07] */
-#define BCHP_CLKGEN_PLL_LC_PLL_MISC2_EN_BYPCLK_1_MASK 0x00000080
-#define BCHP_CLKGEN_PLL_LC_PLL_MISC2_EN_BYPCLK_1_SHIFT 7
-#define BCHP_CLKGEN_PLL_LC_PLL_MISC2_EN_BYPCLK_1_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_LC_PLL_MISC2 :: EN_BYPCLK_0 [06:06] */
-#define BCHP_CLKGEN_PLL_LC_PLL_MISC2_EN_BYPCLK_0_MASK 0x00000040
-#define BCHP_CLKGEN_PLL_LC_PLL_MISC2_EN_BYPCLK_0_SHIFT 6
-#define BCHP_CLKGEN_PLL_LC_PLL_MISC2_EN_BYPCLK_0_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_LC_PLL_MISC2 :: DCO_PWM_RATE_CTRL [05:04] */
-#define BCHP_CLKGEN_PLL_LC_PLL_MISC2_DCO_PWM_RATE_CTRL_MASK 0x00000030
-#define BCHP_CLKGEN_PLL_LC_PLL_MISC2_DCO_PWM_RATE_CTRL_SHIFT 4
-#define BCHP_CLKGEN_PLL_LC_PLL_MISC2_DCO_PWM_RATE_CTRL_DEFAULT 0x00000002
-
-/* CLKGEN :: PLL_LC_PLL_MISC2 :: CTRL_2ND_POLE [03:00] */
-#define BCHP_CLKGEN_PLL_LC_PLL_MISC2_CTRL_2ND_POLE_MASK 0x0000000f
-#define BCHP_CLKGEN_PLL_LC_PLL_MISC2_CTRL_2ND_POLE_SHIFT 0
-#define BCHP_CLKGEN_PLL_LC_PLL_MISC2_CTRL_2ND_POLE_DEFAULT 0x00000000
-
-/***************************************************************************
- *PLL_LC_PLL_OUTSEL_SEL - selection of the output clock from the PLL core
- ***************************************************************************/
-/* CLKGEN :: PLL_LC_PLL_OUTSEL_SEL :: reserved0 [31:03] */
-#define BCHP_CLKGEN_PLL_LC_PLL_OUTSEL_SEL_reserved0_MASK 0xfffffff8
-#define BCHP_CLKGEN_PLL_LC_PLL_OUTSEL_SEL_reserved0_SHIFT 3
-
-/* CLKGEN :: PLL_LC_PLL_OUTSEL_SEL :: OUTPUT_SEL [02:00] */
-#define BCHP_CLKGEN_PLL_LC_PLL_OUTSEL_SEL_OUTPUT_SEL_MASK 0x00000007
-#define BCHP_CLKGEN_PLL_LC_PLL_OUTSEL_SEL_OUTPUT_SEL_SHIFT 0
-#define BCHP_CLKGEN_PLL_LC_PLL_OUTSEL_SEL_OUTPUT_SEL_DEFAULT 0x00000000
-
-/***************************************************************************
- *PLL_LC_PLL_PWRON - Poweron
- ***************************************************************************/
-/* CLKGEN :: PLL_LC_PLL_PWRON :: reserved0 [31:01] */
-#define BCHP_CLKGEN_PLL_LC_PLL_PWRON_reserved0_MASK 0xfffffffe
-#define BCHP_CLKGEN_PLL_LC_PLL_PWRON_reserved0_SHIFT 1
-
-/* CLKGEN :: PLL_LC_PLL_PWRON :: PWRON_PLL [00:00] */
-#define BCHP_CLKGEN_PLL_LC_PLL_PWRON_PWRON_PLL_MASK 0x00000001
-#define BCHP_CLKGEN_PLL_LC_PLL_PWRON_PWRON_PLL_SHIFT 0
-#define BCHP_CLKGEN_PLL_LC_PLL_PWRON_PWRON_PLL_DEFAULT 0x00000001
-
-/***************************************************************************
- *PLL_LC_PLL_RESET - Resets
- ***************************************************************************/
-/* CLKGEN :: PLL_LC_PLL_RESET :: reserved0 [31:02] */
-#define BCHP_CLKGEN_PLL_LC_PLL_RESET_reserved0_MASK 0xfffffffc
-#define BCHP_CLKGEN_PLL_LC_PLL_RESET_reserved0_SHIFT 2
-
-/* CLKGEN :: PLL_LC_PLL_RESET :: RESETD [01:01] */
-#define BCHP_CLKGEN_PLL_LC_PLL_RESET_RESETD_MASK 0x00000002
-#define BCHP_CLKGEN_PLL_LC_PLL_RESET_RESETD_SHIFT 1
-#define BCHP_CLKGEN_PLL_LC_PLL_RESET_RESETD_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_LC_PLL_RESET :: RESETA [00:00] */
-#define BCHP_CLKGEN_PLL_LC_PLL_RESET_RESETA_MASK 0x00000001
-#define BCHP_CLKGEN_PLL_LC_PLL_RESET_RESETA_SHIFT 0
-#define BCHP_CLKGEN_PLL_LC_PLL_RESET_RESETA_DEFAULT 0x00000000
-
-/***************************************************************************
- *PLL_LC_PLL_STATUS - Status
- ***************************************************************************/
-/* CLKGEN :: PLL_LC_PLL_STATUS :: TEST_STATUS [31:00] */
-#define BCHP_CLKGEN_PLL_LC_PLL_STATUS_TEST_STATUS_MASK 0xffffffff
-#define BCHP_CLKGEN_PLL_LC_PLL_STATUS_TEST_STATUS_SHIFT 0
-
-/***************************************************************************
- *PLL_LC_PLL_TEST - enable and selection pf PLL test
- ***************************************************************************/
-/* CLKGEN :: PLL_LC_PLL_TEST :: reserved0 [31:04] */
-#define BCHP_CLKGEN_PLL_LC_PLL_TEST_reserved0_MASK 0xfffffff0
-#define BCHP_CLKGEN_PLL_LC_PLL_TEST_reserved0_SHIFT 4
-
-/* CLKGEN :: PLL_LC_PLL_TEST :: TEST_SEL [03:01] */
-#define BCHP_CLKGEN_PLL_LC_PLL_TEST_TEST_SEL_MASK 0x0000000e
-#define BCHP_CLKGEN_PLL_LC_PLL_TEST_TEST_SEL_SHIFT 1
-#define BCHP_CLKGEN_PLL_LC_PLL_TEST_TEST_SEL_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_LC_PLL_TEST :: TEST_ENABLE [00:00] */
-#define BCHP_CLKGEN_PLL_LC_PLL_TEST_TEST_ENABLE_MASK 0x00000001
-#define BCHP_CLKGEN_PLL_LC_PLL_TEST_TEST_ENABLE_SHIFT 0
-#define BCHP_CLKGEN_PLL_LC_PLL_TEST_TEST_ENABLE_DEFAULT 0x00000000
-
-/***************************************************************************
- *PLL_MOCA_PLL_CHANNEL_CTRL_CH_0 - PLL CHANNEL control CH 0
- ***************************************************************************/
-/* CLKGEN :: PLL_MOCA_PLL_CHANNEL_CTRL_CH_0 :: reserved0 [31:11] */
-#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_0_reserved0_MASK 0xfffff800
-#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_0_reserved0_SHIFT 11
-
-/* CLKGEN :: PLL_MOCA_PLL_CHANNEL_CTRL_CH_0 :: POST_DIVIDER_HOLD_CH0 [10:10] */
-#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_MASK 0x00000400
-#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_SHIFT 10
-#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_MOCA_PLL_CHANNEL_CTRL_CH_0 :: PHASE_OFFSET_CH0 [09:09] */
-#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_MASK 0x00000200
-#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_SHIFT 9
-#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_MOCA_PLL_CHANNEL_CTRL_CH_0 :: MDIV_CH0 [08:01] */
-#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_MASK 0x000001fe
-#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_SHIFT 1
-#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_DEFAULT 0x00000009
-
-/* CLKGEN :: PLL_MOCA_PLL_CHANNEL_CTRL_CH_0 :: CLOCK_DIS_CH0 [00:00] */
-#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_MASK 0x00000001
-#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_SHIFT 0
-#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_DEFAULT 0x00000000
-
-/***************************************************************************
- *PLL_MOCA_PLL_CHANNEL_CTRL_CH_1 - PLL CHANNEL control CH 1
- ***************************************************************************/
-/* CLKGEN :: PLL_MOCA_PLL_CHANNEL_CTRL_CH_1 :: reserved0 [31:11] */
-#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_1_reserved0_MASK 0xfffff800
-#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_1_reserved0_SHIFT 11
-
-/* CLKGEN :: PLL_MOCA_PLL_CHANNEL_CTRL_CH_1 :: POST_DIVIDER_HOLD_CH1 [10:10] */
-#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_MASK 0x00000400
-#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_SHIFT 10
-#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_MOCA_PLL_CHANNEL_CTRL_CH_1 :: PHASE_OFFSET_CH1 [09:09] */
-#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_MASK 0x00000200
-#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_SHIFT 9
-#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_MOCA_PLL_CHANNEL_CTRL_CH_1 :: MDIV_CH1 [08:01] */
-#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_MASK 0x000001fe
-#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_SHIFT 1
-#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_DEFAULT 0x00000009
-
-/* CLKGEN :: PLL_MOCA_PLL_CHANNEL_CTRL_CH_1 :: CLOCK_DIS_CH1 [00:00] */
-#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_MASK 0x00000001
-#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_SHIFT 0
-#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_DEFAULT 0x00000000
-
-/***************************************************************************
- *PLL_MOCA_PLL_CHANNEL_CTRL_CH_2 - PLL CHANNEL control CH 2
- ***************************************************************************/
-/* CLKGEN :: PLL_MOCA_PLL_CHANNEL_CTRL_CH_2 :: reserved0 [31:11] */
-#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_2_reserved0_MASK 0xfffff800
-#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_2_reserved0_SHIFT 11
-
-/* CLKGEN :: PLL_MOCA_PLL_CHANNEL_CTRL_CH_2 :: POST_DIVIDER_HOLD_CH2 [10:10] */
-#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_HOLD_CH2_MASK 0x00000400
-#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_HOLD_CH2_SHIFT 10
-#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_HOLD_CH2_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_MOCA_PLL_CHANNEL_CTRL_CH_2 :: PHASE_OFFSET_CH2 [09:09] */
-#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_2_PHASE_OFFSET_CH2_MASK 0x00000200
-#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_2_PHASE_OFFSET_CH2_SHIFT 9
-#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_2_PHASE_OFFSET_CH2_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_MOCA_PLL_CHANNEL_CTRL_CH_2 :: MDIV_CH2 [08:01] */
-#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_2_MDIV_CH2_MASK 0x000001fe
-#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_2_MDIV_CH2_SHIFT 1
-#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_2_MDIV_CH2_DEFAULT 0x00000024
-
-/* CLKGEN :: PLL_MOCA_PLL_CHANNEL_CTRL_CH_2 :: CLOCK_DIS_CH2 [00:00] */
-#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_2_CLOCK_DIS_CH2_MASK 0x00000001
-#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_2_CLOCK_DIS_CH2_SHIFT 0
-#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_2_CLOCK_DIS_CH2_DEFAULT 0x00000000
-
-/***************************************************************************
- *PLL_MOCA_PLL_CHANNEL_CTRL_CH_3 - PLL CHANNEL control CH 3
- ***************************************************************************/
-/* CLKGEN :: PLL_MOCA_PLL_CHANNEL_CTRL_CH_3 :: reserved0 [31:11] */
-#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_3_reserved0_MASK 0xfffff800
-#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_3_reserved0_SHIFT 11
-
-/* CLKGEN :: PLL_MOCA_PLL_CHANNEL_CTRL_CH_3 :: POST_DIVIDER_HOLD_CH3 [10:10] */
-#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_HOLD_CH3_MASK 0x00000400
-#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_HOLD_CH3_SHIFT 10
-#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_HOLD_CH3_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_MOCA_PLL_CHANNEL_CTRL_CH_3 :: PHASE_OFFSET_CH3 [09:09] */
-#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_3_PHASE_OFFSET_CH3_MASK 0x00000200
-#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_3_PHASE_OFFSET_CH3_SHIFT 9
-#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_3_PHASE_OFFSET_CH3_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_MOCA_PLL_CHANNEL_CTRL_CH_3 :: MDIV_CH3 [08:01] */
-#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_3_MDIV_CH3_MASK 0x000001fe
-#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_3_MDIV_CH3_SHIFT 1
-#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_3_MDIV_CH3_DEFAULT 0x00000009
-
-/* CLKGEN :: PLL_MOCA_PLL_CHANNEL_CTRL_CH_3 :: CLOCK_DIS_CH3 [00:00] */
-#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_3_CLOCK_DIS_CH3_MASK 0x00000001
-#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_3_CLOCK_DIS_CH3_SHIFT 0
-#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_3_CLOCK_DIS_CH3_DEFAULT 0x00000000
-
-/***************************************************************************
- *PLL_MOCA_PLL_CHANNEL_CTRL_CH_4 - PLL CHANNEL control CH 4
- ***************************************************************************/
-/* CLKGEN :: PLL_MOCA_PLL_CHANNEL_CTRL_CH_4 :: reserved0 [31:11] */
-#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_4_reserved0_MASK 0xfffff800
-#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_4_reserved0_SHIFT 11
-
-/* CLKGEN :: PLL_MOCA_PLL_CHANNEL_CTRL_CH_4 :: POST_DIVIDER_HOLD_CH4 [10:10] */
-#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_4_POST_DIVIDER_HOLD_CH4_MASK 0x00000400
-#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_4_POST_DIVIDER_HOLD_CH4_SHIFT 10
-#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_4_POST_DIVIDER_HOLD_CH4_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_MOCA_PLL_CHANNEL_CTRL_CH_4 :: PHASE_OFFSET_CH4 [09:09] */
-#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_4_PHASE_OFFSET_CH4_MASK 0x00000200
-#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_4_PHASE_OFFSET_CH4_SHIFT 9
-#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_4_PHASE_OFFSET_CH4_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_MOCA_PLL_CHANNEL_CTRL_CH_4 :: MDIV_CH4 [08:01] */
-#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_4_MDIV_CH4_MASK 0x000001fe
-#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_4_MDIV_CH4_SHIFT 1
-#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_4_MDIV_CH4_DEFAULT 0x00000007
-
-/* CLKGEN :: PLL_MOCA_PLL_CHANNEL_CTRL_CH_4 :: CLOCK_DIS_CH4 [00:00] */
-#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_4_CLOCK_DIS_CH4_MASK 0x00000001
-#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_4_CLOCK_DIS_CH4_SHIFT 0
-#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_4_CLOCK_DIS_CH4_DEFAULT 0x00000000
-
-/***************************************************************************
- *PLL_MOCA_PLL_CHANNEL_CTRL_CH_5 - PLL CHANNEL control CH 5
- ***************************************************************************/
-/* CLKGEN :: PLL_MOCA_PLL_CHANNEL_CTRL_CH_5 :: reserved0 [31:11] */
-#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_5_reserved0_MASK 0xfffff800
-#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_5_reserved0_SHIFT 11
-
-/* CLKGEN :: PLL_MOCA_PLL_CHANNEL_CTRL_CH_5 :: POST_DIVIDER_HOLD_CH5 [10:10] */
-#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_5_POST_DIVIDER_HOLD_CH5_MASK 0x00000400
-#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_5_POST_DIVIDER_HOLD_CH5_SHIFT 10
-#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_5_POST_DIVIDER_HOLD_CH5_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_MOCA_PLL_CHANNEL_CTRL_CH_5 :: PHASE_OFFSET_CH5 [09:09] */
-#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_5_PHASE_OFFSET_CH5_MASK 0x00000200
-#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_5_PHASE_OFFSET_CH5_SHIFT 9
-#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_5_PHASE_OFFSET_CH5_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_MOCA_PLL_CHANNEL_CTRL_CH_5 :: MDIV_CH5 [08:01] */
-#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_5_MDIV_CH5_MASK 0x000001fe
-#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_5_MDIV_CH5_SHIFT 1
-#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_5_MDIV_CH5_DEFAULT 0x00000024
-
-/* CLKGEN :: PLL_MOCA_PLL_CHANNEL_CTRL_CH_5 :: CLOCK_DIS_CH5 [00:00] */
-#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_5_CLOCK_DIS_CH5_MASK 0x00000001
-#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_5_CLOCK_DIS_CH5_SHIFT 0
-#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_5_CLOCK_DIS_CH5_DEFAULT 0x00000000
-
-/***************************************************************************
- *PLL_MOCA_PLL_DIV - Pre multiplier
- ***************************************************************************/
-/* CLKGEN :: PLL_MOCA_PLL_DIV :: reserved0 [31:14] */
-#define BCHP_CLKGEN_PLL_MOCA_PLL_DIV_reserved0_MASK 0xffffc000
-#define BCHP_CLKGEN_PLL_MOCA_PLL_DIV_reserved0_SHIFT 14
-
-/* CLKGEN :: PLL_MOCA_PLL_DIV :: PDIV [13:10] */
-#define BCHP_CLKGEN_PLL_MOCA_PLL_DIV_PDIV_MASK 0x00003c00
-#define BCHP_CLKGEN_PLL_MOCA_PLL_DIV_PDIV_SHIFT 10
-#define BCHP_CLKGEN_PLL_MOCA_PLL_DIV_PDIV_DEFAULT 0x00000003
-
-/* CLKGEN :: PLL_MOCA_PLL_DIV :: NDIV_INT [09:00] */
-#define BCHP_CLKGEN_PLL_MOCA_PLL_DIV_NDIV_INT_MASK 0x000003ff
-#define BCHP_CLKGEN_PLL_MOCA_PLL_DIV_NDIV_INT_SHIFT 0
-#define BCHP_CLKGEN_PLL_MOCA_PLL_DIV_NDIV_INT_DEFAULT 0x000000c8
-
-/***************************************************************************
- *PLL_MOCA_PLL_GAIN - PLL GAIN
- ***************************************************************************/
-/* CLKGEN :: PLL_MOCA_PLL_GAIN :: reserved0 [31:10] */
-#define BCHP_CLKGEN_PLL_MOCA_PLL_GAIN_reserved0_MASK 0xfffffc00
-#define BCHP_CLKGEN_PLL_MOCA_PLL_GAIN_reserved0_SHIFT 10
-
-/* CLKGEN :: PLL_MOCA_PLL_GAIN :: LOOP_GAIN_PROPORTIONAL_IN_PHASE [09:06] */
-#define BCHP_CLKGEN_PLL_MOCA_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_MASK 0x000003c0
-#define BCHP_CLKGEN_PLL_MOCA_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_SHIFT 6
-#define BCHP_CLKGEN_PLL_MOCA_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_DEFAULT 0x00000003
-
-/* CLKGEN :: PLL_MOCA_PLL_GAIN :: LOOP_GAIN_IN_FREQ [05:03] */
-#define BCHP_CLKGEN_PLL_MOCA_PLL_GAIN_LOOP_GAIN_IN_FREQ_MASK 0x00000038
-#define BCHP_CLKGEN_PLL_MOCA_PLL_GAIN_LOOP_GAIN_IN_FREQ_SHIFT 3
-#define BCHP_CLKGEN_PLL_MOCA_PLL_GAIN_LOOP_GAIN_IN_FREQ_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_MOCA_PLL_GAIN :: LOOP_GAIN_INTEGRATOR_IN_PHASE [02:00] */
-#define BCHP_CLKGEN_PLL_MOCA_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_MASK 0x00000007
-#define BCHP_CLKGEN_PLL_MOCA_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_SHIFT 0
-#define BCHP_CLKGEN_PLL_MOCA_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_DEFAULT 0x00000002
-
-/***************************************************************************
- *PLL_MOCA_PLL_LDO_PWRON - LDO Power on
- ***************************************************************************/
-/* CLKGEN :: PLL_MOCA_PLL_LDO_PWRON :: reserved0 [31:01] */
-#define BCHP_CLKGEN_PLL_MOCA_PLL_LDO_PWRON_reserved0_MASK 0xfffffffe
-#define BCHP_CLKGEN_PLL_MOCA_PLL_LDO_PWRON_reserved0_SHIFT 1
-
-/* CLKGEN :: PLL_MOCA_PLL_LDO_PWRON :: LDO_PWRON_PLL [00:00] */
-#define BCHP_CLKGEN_PLL_MOCA_PLL_LDO_PWRON_LDO_PWRON_PLL_MASK 0x00000001
-#define BCHP_CLKGEN_PLL_MOCA_PLL_LDO_PWRON_LDO_PWRON_PLL_SHIFT 0
-#define BCHP_CLKGEN_PLL_MOCA_PLL_LDO_PWRON_LDO_PWRON_PLL_DEFAULT 0x00000001
-
-/***************************************************************************
- *PLL_MOCA_PLL_LOCK_STATUS - Lock Status
- ***************************************************************************/
-/* CLKGEN :: PLL_MOCA_PLL_LOCK_STATUS :: reserved0 [31:02] */
-#define BCHP_CLKGEN_PLL_MOCA_PLL_LOCK_STATUS_reserved0_MASK 0xfffffffc
-#define BCHP_CLKGEN_PLL_MOCA_PLL_LOCK_STATUS_reserved0_SHIFT 2
-
-/* CLKGEN :: PLL_MOCA_PLL_LOCK_STATUS :: LOCK_LOST [01:01] */
-#define BCHP_CLKGEN_PLL_MOCA_PLL_LOCK_STATUS_LOCK_LOST_MASK 0x00000002
-#define BCHP_CLKGEN_PLL_MOCA_PLL_LOCK_STATUS_LOCK_LOST_SHIFT 1
-
-/* CLKGEN :: PLL_MOCA_PLL_LOCK_STATUS :: LOCK [00:00] */
-#define BCHP_CLKGEN_PLL_MOCA_PLL_LOCK_STATUS_LOCK_MASK 0x00000001
-#define BCHP_CLKGEN_PLL_MOCA_PLL_LOCK_STATUS_LOCK_SHIFT 0
-
-/***************************************************************************
- *PLL_MOCA_PLL_MISC - Mscellaneous control bus.
- ***************************************************************************/
-/* CLKGEN :: PLL_MOCA_PLL_MISC :: VCO_RANGE [31:30] */
-#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_VCO_RANGE_MASK 0xc0000000
-#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_VCO_RANGE_SHIFT 30
-#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_VCO_RANGE_DEFAULT 0x00000002
-
-/* CLKGEN :: PLL_MOCA_PLL_MISC :: VCO_FB_DIV2 [29:29] */
-#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_VCO_FB_DIV2_MASK 0x20000000
-#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_VCO_FB_DIV2_SHIFT 29
-#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_VCO_FB_DIV2_DEFAULT 0x00000001
-
-/* CLKGEN :: PLL_MOCA_PLL_MISC :: STAT_UPDATE [28:28] */
-#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_STAT_UPDATE_MASK 0x10000000
-#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_STAT_UPDATE_SHIFT 28
-#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_STAT_UPDATE_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_MOCA_PLL_MISC :: STAT_SELECT [27:25] */
-#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_STAT_SELECT_MASK 0x0e000000
-#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_STAT_SELECT_SHIFT 25
-#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_STAT_SELECT_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_MOCA_PLL_MISC :: STAT_RESET [24:24] */
-#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_STAT_RESET_MASK 0x01000000
-#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_STAT_RESET_SHIFT 24
-#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_STAT_RESET_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_MOCA_PLL_MISC :: STAT_MODE [23:22] */
-#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_STAT_MODE_MASK 0x00c00000
-#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_STAT_MODE_SHIFT 22
-#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_STAT_MODE_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_MOCA_PLL_MISC :: PWM_RATE [21:20] */
-#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_PWM_RATE_MASK 0x00300000
-#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_PWM_RATE_SHIFT 20
-#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_PWM_RATE_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_MOCA_PLL_MISC :: POST_CTRL_RESETB [19:18] */
-#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_POST_CTRL_RESETB_MASK 0x000c0000
-#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_POST_CTRL_RESETB_SHIFT 18
-#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_POST_CTRL_RESETB_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_MOCA_PLL_MISC :: PLLRESERVED2 [17:16] */
-#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_PLLRESERVED2_MASK 0x00030000
-#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_PLLRESERVED2_SHIFT 16
-#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_PLLRESERVED2_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_MOCA_PLL_MISC :: PLLRESERVED1 [15:15] */
-#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_PLLRESERVED1_MASK 0x00008000
-#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_PLLRESERVED1_SHIFT 15
-#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_PLLRESERVED1_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_MOCA_PLL_MISC :: NDIV_RELOCK [14:14] */
-#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_NDIV_RELOCK_MASK 0x00004000
-#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_NDIV_RELOCK_SHIFT 14
-#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_NDIV_RELOCK_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_MOCA_PLL_MISC :: FAST_LOCK [13:13] */
-#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_FAST_LOCK_MASK 0x00002000
-#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_FAST_LOCK_SHIFT 13
-#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_FAST_LOCK_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_MOCA_PLL_MISC :: DCO_CTRL_BYPASS_ENABLE [12:12] */
-#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_MASK 0x00001000
-#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_SHIFT 12
-#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_MOCA_PLL_MISC :: DCO_CTRL_BYPASS [11:00] */
-#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_DCO_CTRL_BYPASS_MASK 0x00000fff
-#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_DCO_CTRL_BYPASS_SHIFT 0
-#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_DCO_CTRL_BYPASS_DEFAULT 0x00000000
-
-/***************************************************************************
- *PLL_MOCA_PLL_MISC2 - Mscellaneous control bus continued.
- ***************************************************************************/
-/* CLKGEN :: PLL_MOCA_PLL_MISC2 :: PLLRESERVED0 [31:00] */
-#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC2_PLLRESERVED0_MASK 0xffffffff
-#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC2_PLLRESERVED0_SHIFT 0
-#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC2_PLLRESERVED0_DEFAULT 0x00000001
-
-/***************************************************************************
- *PLL_MOCA_PLL_PWRON - Poweron
- ***************************************************************************/
-/* CLKGEN :: PLL_MOCA_PLL_PWRON :: reserved0 [31:01] */
-#define BCHP_CLKGEN_PLL_MOCA_PLL_PWRON_reserved0_MASK 0xfffffffe
-#define BCHP_CLKGEN_PLL_MOCA_PLL_PWRON_reserved0_SHIFT 1
-
-/* CLKGEN :: PLL_MOCA_PLL_PWRON :: PWRON_PLL [00:00] */
-#define BCHP_CLKGEN_PLL_MOCA_PLL_PWRON_PWRON_PLL_MASK 0x00000001
-#define BCHP_CLKGEN_PLL_MOCA_PLL_PWRON_PWRON_PLL_SHIFT 0
-#define BCHP_CLKGEN_PLL_MOCA_PLL_PWRON_PWRON_PLL_DEFAULT 0x00000001
-
-/***************************************************************************
- *PLL_MOCA_PLL_RESET - Resets
- ***************************************************************************/
-/* CLKGEN :: PLL_MOCA_PLL_RESET :: reserved0 [31:02] */
-#define BCHP_CLKGEN_PLL_MOCA_PLL_RESET_reserved0_MASK 0xfffffffc
-#define BCHP_CLKGEN_PLL_MOCA_PLL_RESET_reserved0_SHIFT 2
-
-/* CLKGEN :: PLL_MOCA_PLL_RESET :: RESETD [01:01] */
-#define BCHP_CLKGEN_PLL_MOCA_PLL_RESET_RESETD_MASK 0x00000002
-#define BCHP_CLKGEN_PLL_MOCA_PLL_RESET_RESETD_SHIFT 1
-#define BCHP_CLKGEN_PLL_MOCA_PLL_RESET_RESETD_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_MOCA_PLL_RESET :: RESETA [00:00] */
-#define BCHP_CLKGEN_PLL_MOCA_PLL_RESET_RESETA_MASK 0x00000001
-#define BCHP_CLKGEN_PLL_MOCA_PLL_RESET_RESETA_SHIFT 0
-#define BCHP_CLKGEN_PLL_MOCA_PLL_RESET_RESETA_DEFAULT 0x00000000
-
-/***************************************************************************
- *PLL_MOCA_PLL_SSC_MODE_CONTROL_HIGH - Higher bits of Spread Spectrum mode control
- ***************************************************************************/
-/* CLKGEN :: PLL_MOCA_PLL_SSC_MODE_CONTROL_HIGH :: reserved0 [31:16] */
-#define BCHP_CLKGEN_PLL_MOCA_PLL_SSC_MODE_CONTROL_HIGH_reserved0_MASK 0xffff0000
-#define BCHP_CLKGEN_PLL_MOCA_PLL_SSC_MODE_CONTROL_HIGH_reserved0_SHIFT 16
-
-/* CLKGEN :: PLL_MOCA_PLL_SSC_MODE_CONTROL_HIGH :: SSC_STEP [15:00] */
-#define BCHP_CLKGEN_PLL_MOCA_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_MASK 0x0000ffff
-#define BCHP_CLKGEN_PLL_MOCA_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_SHIFT 0
-#define BCHP_CLKGEN_PLL_MOCA_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *PLL_MOCA_PLL_SSC_MODE_CONTROL_LOW - Lower bits of Spread Spectrum mode control
- ***************************************************************************/
-/* CLKGEN :: PLL_MOCA_PLL_SSC_MODE_CONTROL_LOW :: reserved0 [31:23] */
-#define BCHP_CLKGEN_PLL_MOCA_PLL_SSC_MODE_CONTROL_LOW_reserved0_MASK 0xff800000
-#define BCHP_CLKGEN_PLL_MOCA_PLL_SSC_MODE_CONTROL_LOW_reserved0_SHIFT 23
-
-/* CLKGEN :: PLL_MOCA_PLL_SSC_MODE_CONTROL_LOW :: SSC_MODE [22:22] */
-#define BCHP_CLKGEN_PLL_MOCA_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_MASK 0x00400000
-#define BCHP_CLKGEN_PLL_MOCA_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_SHIFT 22
-#define BCHP_CLKGEN_PLL_MOCA_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_MOCA_PLL_SSC_MODE_CONTROL_LOW :: SSC_LIMIT [21:00] */
-#define BCHP_CLKGEN_PLL_MOCA_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_MASK 0x003fffff
-#define BCHP_CLKGEN_PLL_MOCA_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_SHIFT 0
-#define BCHP_CLKGEN_PLL_MOCA_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_DEFAULT 0x00000000
-
-/***************************************************************************
- *PLL_MOCA_PLL_STATUS - Status
- ***************************************************************************/
-/* CLKGEN :: PLL_MOCA_PLL_STATUS :: reserved0 [31:12] */
-#define BCHP_CLKGEN_PLL_MOCA_PLL_STATUS_reserved0_MASK 0xfffff000
-#define BCHP_CLKGEN_PLL_MOCA_PLL_STATUS_reserved0_SHIFT 12
-
-/* CLKGEN :: PLL_MOCA_PLL_STATUS :: TEST_STATUS [11:00] */
-#define BCHP_CLKGEN_PLL_MOCA_PLL_STATUS_TEST_STATUS_MASK 0x00000fff
-#define BCHP_CLKGEN_PLL_MOCA_PLL_STATUS_TEST_STATUS_SHIFT 0
-
-/***************************************************************************
- *PLL_NETWORK_PLL_CHANNEL_CTRL_CH_0 - PLL CHANNEL control CH 0
- ***************************************************************************/
-/* CLKGEN :: PLL_NETWORK_PLL_CHANNEL_CTRL_CH_0 :: reserved0 [31:11] */
-#define BCHP_CLKGEN_PLL_NETWORK_PLL_CHANNEL_CTRL_CH_0_reserved0_MASK 0xfffff800
-#define BCHP_CLKGEN_PLL_NETWORK_PLL_CHANNEL_CTRL_CH_0_reserved0_SHIFT 11
-
-/* CLKGEN :: PLL_NETWORK_PLL_CHANNEL_CTRL_CH_0 :: POST_DIVIDER_HOLD_CH0 [10:10] */
-#define BCHP_CLKGEN_PLL_NETWORK_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_MASK 0x00000400
-#define BCHP_CLKGEN_PLL_NETWORK_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_SHIFT 10
-#define BCHP_CLKGEN_PLL_NETWORK_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_NETWORK_PLL_CHANNEL_CTRL_CH_0 :: PHASE_OFFSET_CH0 [09:09] */
-#define BCHP_CLKGEN_PLL_NETWORK_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_MASK 0x00000200
-#define BCHP_CLKGEN_PLL_NETWORK_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_SHIFT 9
-#define BCHP_CLKGEN_PLL_NETWORK_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_NETWORK_PLL_CHANNEL_CTRL_CH_0 :: MDIV_CH0 [08:01] */
-#define BCHP_CLKGEN_PLL_NETWORK_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_MASK 0x000001fe
-#define BCHP_CLKGEN_PLL_NETWORK_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_SHIFT 1
-#define BCHP_CLKGEN_PLL_NETWORK_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_DEFAULT 0x00000009
-
-/* CLKGEN :: PLL_NETWORK_PLL_CHANNEL_CTRL_CH_0 :: CLOCK_DIS_CH0 [00:00] */
-#define BCHP_CLKGEN_PLL_NETWORK_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_MASK 0x00000001
-#define BCHP_CLKGEN_PLL_NETWORK_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_SHIFT 0
-#define BCHP_CLKGEN_PLL_NETWORK_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_DEFAULT 0x00000000
-
-/***************************************************************************
- *PLL_NETWORK_PLL_CHANNEL_CTRL_CH_1 - PLL CHANNEL control CH 1
- ***************************************************************************/
-/* CLKGEN :: PLL_NETWORK_PLL_CHANNEL_CTRL_CH_1 :: reserved0 [31:11] */
-#define BCHP_CLKGEN_PLL_NETWORK_PLL_CHANNEL_CTRL_CH_1_reserved0_MASK 0xfffff800
-#define BCHP_CLKGEN_PLL_NETWORK_PLL_CHANNEL_CTRL_CH_1_reserved0_SHIFT 11
-
-/* CLKGEN :: PLL_NETWORK_PLL_CHANNEL_CTRL_CH_1 :: POST_DIVIDER_HOLD_CH1 [10:10] */
-#define BCHP_CLKGEN_PLL_NETWORK_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_MASK 0x00000400
-#define BCHP_CLKGEN_PLL_NETWORK_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_SHIFT 10
-#define BCHP_CLKGEN_PLL_NETWORK_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_NETWORK_PLL_CHANNEL_CTRL_CH_1 :: PHASE_OFFSET_CH1 [09:09] */
-#define BCHP_CLKGEN_PLL_NETWORK_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_MASK 0x00000200
-#define BCHP_CLKGEN_PLL_NETWORK_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_SHIFT 9
-#define BCHP_CLKGEN_PLL_NETWORK_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_NETWORK_PLL_CHANNEL_CTRL_CH_1 :: MDIV_CH1 [08:01] */
-#define BCHP_CLKGEN_PLL_NETWORK_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_MASK 0x000001fe
-#define BCHP_CLKGEN_PLL_NETWORK_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_SHIFT 1
-#define BCHP_CLKGEN_PLL_NETWORK_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_DEFAULT 0x00000012
-
-/* CLKGEN :: PLL_NETWORK_PLL_CHANNEL_CTRL_CH_1 :: CLOCK_DIS_CH1 [00:00] */
-#define BCHP_CLKGEN_PLL_NETWORK_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_MASK 0x00000001
-#define BCHP_CLKGEN_PLL_NETWORK_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_SHIFT 0
-#define BCHP_CLKGEN_PLL_NETWORK_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_DEFAULT 0x00000000
-
-/***************************************************************************
- *PLL_NETWORK_PLL_CHANNEL_CTRL_CH_2 - PLL CHANNEL control CH 2
- ***************************************************************************/
-/* CLKGEN :: PLL_NETWORK_PLL_CHANNEL_CTRL_CH_2 :: reserved0 [31:11] */
-#define BCHP_CLKGEN_PLL_NETWORK_PLL_CHANNEL_CTRL_CH_2_reserved0_MASK 0xfffff800
-#define BCHP_CLKGEN_PLL_NETWORK_PLL_CHANNEL_CTRL_CH_2_reserved0_SHIFT 11
-
-/* CLKGEN :: PLL_NETWORK_PLL_CHANNEL_CTRL_CH_2 :: POST_DIVIDER_HOLD_CH2 [10:10] */
-#define BCHP_CLKGEN_PLL_NETWORK_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_HOLD_CH2_MASK 0x00000400
-#define BCHP_CLKGEN_PLL_NETWORK_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_HOLD_CH2_SHIFT 10
-#define BCHP_CLKGEN_PLL_NETWORK_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_HOLD_CH2_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_NETWORK_PLL_CHANNEL_CTRL_CH_2 :: PHASE_OFFSET_CH2 [09:09] */
-#define BCHP_CLKGEN_PLL_NETWORK_PLL_CHANNEL_CTRL_CH_2_PHASE_OFFSET_CH2_MASK 0x00000200
-#define BCHP_CLKGEN_PLL_NETWORK_PLL_CHANNEL_CTRL_CH_2_PHASE_OFFSET_CH2_SHIFT 9
-#define BCHP_CLKGEN_PLL_NETWORK_PLL_CHANNEL_CTRL_CH_2_PHASE_OFFSET_CH2_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_NETWORK_PLL_CHANNEL_CTRL_CH_2 :: MDIV_CH2 [08:01] */
-#define BCHP_CLKGEN_PLL_NETWORK_PLL_CHANNEL_CTRL_CH_2_MDIV_CH2_MASK 0x000001fe
-#define BCHP_CLKGEN_PLL_NETWORK_PLL_CHANNEL_CTRL_CH_2_MDIV_CH2_SHIFT 1
-#define BCHP_CLKGEN_PLL_NETWORK_PLL_CHANNEL_CTRL_CH_2_MDIV_CH2_DEFAULT 0x00000053
-
-/* CLKGEN :: PLL_NETWORK_PLL_CHANNEL_CTRL_CH_2 :: CLOCK_DIS_CH2 [00:00] */
-#define BCHP_CLKGEN_PLL_NETWORK_PLL_CHANNEL_CTRL_CH_2_CLOCK_DIS_CH2_MASK 0x00000001
-#define BCHP_CLKGEN_PLL_NETWORK_PLL_CHANNEL_CTRL_CH_2_CLOCK_DIS_CH2_SHIFT 0
-#define BCHP_CLKGEN_PLL_NETWORK_PLL_CHANNEL_CTRL_CH_2_CLOCK_DIS_CH2_DEFAULT 0x00000000
-
-/***************************************************************************
- *PLL_NETWORK_PLL_DIV - Pre multiplier
- ***************************************************************************/
-/* CLKGEN :: PLL_NETWORK_PLL_DIV :: reserved0 [31:14] */
-#define BCHP_CLKGEN_PLL_NETWORK_PLL_DIV_reserved0_MASK 0xffffc000
-#define BCHP_CLKGEN_PLL_NETWORK_PLL_DIV_reserved0_SHIFT 14
-
-/* CLKGEN :: PLL_NETWORK_PLL_DIV :: PDIV [13:10] */
-#define BCHP_CLKGEN_PLL_NETWORK_PLL_DIV_PDIV_MASK 0x00003c00
-#define BCHP_CLKGEN_PLL_NETWORK_PLL_DIV_PDIV_SHIFT 10
-#define BCHP_CLKGEN_PLL_NETWORK_PLL_DIV_PDIV_DEFAULT 0x00000003
-
-/* CLKGEN :: PLL_NETWORK_PLL_DIV :: NDIV_INT [09:00] */
-#define BCHP_CLKGEN_PLL_NETWORK_PLL_DIV_NDIV_INT_MASK 0x000003ff
-#define BCHP_CLKGEN_PLL_NETWORK_PLL_DIV_NDIV_INT_SHIFT 0
-#define BCHP_CLKGEN_PLL_NETWORK_PLL_DIV_NDIV_INT_DEFAULT 0x0000007d
-
-/***************************************************************************
- *PLL_NETWORK_PLL_GAIN - PLL GAIN
- ***************************************************************************/
-/* CLKGEN :: PLL_NETWORK_PLL_GAIN :: reserved0 [31:10] */
-#define BCHP_CLKGEN_PLL_NETWORK_PLL_GAIN_reserved0_MASK 0xfffffc00
-#define BCHP_CLKGEN_PLL_NETWORK_PLL_GAIN_reserved0_SHIFT 10
-
-/* CLKGEN :: PLL_NETWORK_PLL_GAIN :: LOOP_GAIN_PROPORTIONAL_IN_PHASE [09:06] */
-#define BCHP_CLKGEN_PLL_NETWORK_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_MASK 0x000003c0
-#define BCHP_CLKGEN_PLL_NETWORK_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_SHIFT 6
-#define BCHP_CLKGEN_PLL_NETWORK_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_DEFAULT 0x00000003
-
-/* CLKGEN :: PLL_NETWORK_PLL_GAIN :: LOOP_GAIN_IN_FREQ [05:03] */
-#define BCHP_CLKGEN_PLL_NETWORK_PLL_GAIN_LOOP_GAIN_IN_FREQ_MASK 0x00000038
-#define BCHP_CLKGEN_PLL_NETWORK_PLL_GAIN_LOOP_GAIN_IN_FREQ_SHIFT 3
-#define BCHP_CLKGEN_PLL_NETWORK_PLL_GAIN_LOOP_GAIN_IN_FREQ_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_NETWORK_PLL_GAIN :: LOOP_GAIN_INTEGRATOR_IN_PHASE [02:00] */
-#define BCHP_CLKGEN_PLL_NETWORK_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_MASK 0x00000007
-#define BCHP_CLKGEN_PLL_NETWORK_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_SHIFT 0
-#define BCHP_CLKGEN_PLL_NETWORK_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_DEFAULT 0x00000002
-
-/***************************************************************************
- *PLL_NETWORK_PLL_LDO_PWRON - LDO Power on
- ***************************************************************************/
-/* CLKGEN :: PLL_NETWORK_PLL_LDO_PWRON :: reserved0 [31:01] */
-#define BCHP_CLKGEN_PLL_NETWORK_PLL_LDO_PWRON_reserved0_MASK 0xfffffffe
-#define BCHP_CLKGEN_PLL_NETWORK_PLL_LDO_PWRON_reserved0_SHIFT 1
-
-/* CLKGEN :: PLL_NETWORK_PLL_LDO_PWRON :: LDO_PWRON_PLL [00:00] */
-#define BCHP_CLKGEN_PLL_NETWORK_PLL_LDO_PWRON_LDO_PWRON_PLL_MASK 0x00000001
-#define BCHP_CLKGEN_PLL_NETWORK_PLL_LDO_PWRON_LDO_PWRON_PLL_SHIFT 0
-#define BCHP_CLKGEN_PLL_NETWORK_PLL_LDO_PWRON_LDO_PWRON_PLL_DEFAULT 0x00000001
-
-/***************************************************************************
- *PLL_NETWORK_PLL_LOCK_STATUS - Lock Status
- ***************************************************************************/
-/* CLKGEN :: PLL_NETWORK_PLL_LOCK_STATUS :: reserved0 [31:02] */
-#define BCHP_CLKGEN_PLL_NETWORK_PLL_LOCK_STATUS_reserved0_MASK 0xfffffffc
-#define BCHP_CLKGEN_PLL_NETWORK_PLL_LOCK_STATUS_reserved0_SHIFT 2
-
-/* CLKGEN :: PLL_NETWORK_PLL_LOCK_STATUS :: LOCK_LOST [01:01] */
-#define BCHP_CLKGEN_PLL_NETWORK_PLL_LOCK_STATUS_LOCK_LOST_MASK 0x00000002
-#define BCHP_CLKGEN_PLL_NETWORK_PLL_LOCK_STATUS_LOCK_LOST_SHIFT 1
-
-/* CLKGEN :: PLL_NETWORK_PLL_LOCK_STATUS :: LOCK [00:00] */
-#define BCHP_CLKGEN_PLL_NETWORK_PLL_LOCK_STATUS_LOCK_MASK 0x00000001
-#define BCHP_CLKGEN_PLL_NETWORK_PLL_LOCK_STATUS_LOCK_SHIFT 0
-
-/***************************************************************************
- *PLL_NETWORK_PLL_MISC - Mscellaneous control bus.
- ***************************************************************************/
-/* CLKGEN :: PLL_NETWORK_PLL_MISC :: VCO_RANGE [31:30] */
-#define BCHP_CLKGEN_PLL_NETWORK_PLL_MISC_VCO_RANGE_MASK 0xc0000000
-#define BCHP_CLKGEN_PLL_NETWORK_PLL_MISC_VCO_RANGE_SHIFT 30
-#define BCHP_CLKGEN_PLL_NETWORK_PLL_MISC_VCO_RANGE_DEFAULT 0x00000002
-
-/* CLKGEN :: PLL_NETWORK_PLL_MISC :: VCO_FB_DIV2 [29:29] */
-#define BCHP_CLKGEN_PLL_NETWORK_PLL_MISC_VCO_FB_DIV2_MASK 0x20000000
-#define BCHP_CLKGEN_PLL_NETWORK_PLL_MISC_VCO_FB_DIV2_SHIFT 29
-#define BCHP_CLKGEN_PLL_NETWORK_PLL_MISC_VCO_FB_DIV2_DEFAULT 0x00000001
-
-/* CLKGEN :: PLL_NETWORK_PLL_MISC :: STAT_UPDATE [28:28] */
-#define BCHP_CLKGEN_PLL_NETWORK_PLL_MISC_STAT_UPDATE_MASK 0x10000000
-#define BCHP_CLKGEN_PLL_NETWORK_PLL_MISC_STAT_UPDATE_SHIFT 28
-#define BCHP_CLKGEN_PLL_NETWORK_PLL_MISC_STAT_UPDATE_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_NETWORK_PLL_MISC :: STAT_SELECT [27:25] */
-#define BCHP_CLKGEN_PLL_NETWORK_PLL_MISC_STAT_SELECT_MASK 0x0e000000
-#define BCHP_CLKGEN_PLL_NETWORK_PLL_MISC_STAT_SELECT_SHIFT 25
-#define BCHP_CLKGEN_PLL_NETWORK_PLL_MISC_STAT_SELECT_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_NETWORK_PLL_MISC :: STAT_RESET [24:24] */
-#define BCHP_CLKGEN_PLL_NETWORK_PLL_MISC_STAT_RESET_MASK 0x01000000
-#define BCHP_CLKGEN_PLL_NETWORK_PLL_MISC_STAT_RESET_SHIFT 24
-#define BCHP_CLKGEN_PLL_NETWORK_PLL_MISC_STAT_RESET_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_NETWORK_PLL_MISC :: STAT_MODE [23:22] */
-#define BCHP_CLKGEN_PLL_NETWORK_PLL_MISC_STAT_MODE_MASK 0x00c00000
-#define BCHP_CLKGEN_PLL_NETWORK_PLL_MISC_STAT_MODE_SHIFT 22
-#define BCHP_CLKGEN_PLL_NETWORK_PLL_MISC_STAT_MODE_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_NETWORK_PLL_MISC :: PWM_RATE [21:20] */
-#define BCHP_CLKGEN_PLL_NETWORK_PLL_MISC_PWM_RATE_MASK 0x00300000
-#define BCHP_CLKGEN_PLL_NETWORK_PLL_MISC_PWM_RATE_SHIFT 20
-#define BCHP_CLKGEN_PLL_NETWORK_PLL_MISC_PWM_RATE_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_NETWORK_PLL_MISC :: POST_CTRL_RESETB [19:18] */
-#define BCHP_CLKGEN_PLL_NETWORK_PLL_MISC_POST_CTRL_RESETB_MASK 0x000c0000
-#define BCHP_CLKGEN_PLL_NETWORK_PLL_MISC_POST_CTRL_RESETB_SHIFT 18
-#define BCHP_CLKGEN_PLL_NETWORK_PLL_MISC_POST_CTRL_RESETB_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_NETWORK_PLL_MISC :: PLLRESERVED2 [17:16] */
-#define BCHP_CLKGEN_PLL_NETWORK_PLL_MISC_PLLRESERVED2_MASK 0x00030000
-#define BCHP_CLKGEN_PLL_NETWORK_PLL_MISC_PLLRESERVED2_SHIFT 16
-#define BCHP_CLKGEN_PLL_NETWORK_PLL_MISC_PLLRESERVED2_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_NETWORK_PLL_MISC :: PLLRESERVED1 [15:15] */
-#define BCHP_CLKGEN_PLL_NETWORK_PLL_MISC_PLLRESERVED1_MASK 0x00008000
-#define BCHP_CLKGEN_PLL_NETWORK_PLL_MISC_PLLRESERVED1_SHIFT 15
-#define BCHP_CLKGEN_PLL_NETWORK_PLL_MISC_PLLRESERVED1_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_NETWORK_PLL_MISC :: NDIV_RELOCK [14:14] */
-#define BCHP_CLKGEN_PLL_NETWORK_PLL_MISC_NDIV_RELOCK_MASK 0x00004000
-#define BCHP_CLKGEN_PLL_NETWORK_PLL_MISC_NDIV_RELOCK_SHIFT 14
-#define BCHP_CLKGEN_PLL_NETWORK_PLL_MISC_NDIV_RELOCK_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_NETWORK_PLL_MISC :: FAST_LOCK [13:13] */
-#define BCHP_CLKGEN_PLL_NETWORK_PLL_MISC_FAST_LOCK_MASK 0x00002000
-#define BCHP_CLKGEN_PLL_NETWORK_PLL_MISC_FAST_LOCK_SHIFT 13
-#define BCHP_CLKGEN_PLL_NETWORK_PLL_MISC_FAST_LOCK_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_NETWORK_PLL_MISC :: DCO_CTRL_BYPASS_ENABLE [12:12] */
-#define BCHP_CLKGEN_PLL_NETWORK_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_MASK 0x00001000
-#define BCHP_CLKGEN_PLL_NETWORK_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_SHIFT 12
-#define BCHP_CLKGEN_PLL_NETWORK_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_NETWORK_PLL_MISC :: DCO_CTRL_BYPASS [11:00] */
-#define BCHP_CLKGEN_PLL_NETWORK_PLL_MISC_DCO_CTRL_BYPASS_MASK 0x00000fff
-#define BCHP_CLKGEN_PLL_NETWORK_PLL_MISC_DCO_CTRL_BYPASS_SHIFT 0
-#define BCHP_CLKGEN_PLL_NETWORK_PLL_MISC_DCO_CTRL_BYPASS_DEFAULT 0x00000000
-
-/***************************************************************************
- *PLL_NETWORK_PLL_MISC2 - Mscellaneous control bus continued.
- ***************************************************************************/
-/* CLKGEN :: PLL_NETWORK_PLL_MISC2 :: PLLRESERVED0 [31:00] */
-#define BCHP_CLKGEN_PLL_NETWORK_PLL_MISC2_PLLRESERVED0_MASK 0xffffffff
-#define BCHP_CLKGEN_PLL_NETWORK_PLL_MISC2_PLLRESERVED0_SHIFT 0
-#define BCHP_CLKGEN_PLL_NETWORK_PLL_MISC2_PLLRESERVED0_DEFAULT 0x00000001
-
-/***************************************************************************
- *PLL_NETWORK_PLL_PWRON - Poweron
- ***************************************************************************/
-/* CLKGEN :: PLL_NETWORK_PLL_PWRON :: reserved0 [31:01] */
-#define BCHP_CLKGEN_PLL_NETWORK_PLL_PWRON_reserved0_MASK 0xfffffffe
-#define BCHP_CLKGEN_PLL_NETWORK_PLL_PWRON_reserved0_SHIFT 1
-
-/* CLKGEN :: PLL_NETWORK_PLL_PWRON :: PWRON_PLL [00:00] */
-#define BCHP_CLKGEN_PLL_NETWORK_PLL_PWRON_PWRON_PLL_MASK 0x00000001
-#define BCHP_CLKGEN_PLL_NETWORK_PLL_PWRON_PWRON_PLL_SHIFT 0
-#define BCHP_CLKGEN_PLL_NETWORK_PLL_PWRON_PWRON_PLL_DEFAULT 0x00000001
-
-/***************************************************************************
- *PLL_NETWORK_PLL_RESET - Resets
- ***************************************************************************/
-/* CLKGEN :: PLL_NETWORK_PLL_RESET :: reserved0 [31:02] */
-#define BCHP_CLKGEN_PLL_NETWORK_PLL_RESET_reserved0_MASK 0xfffffffc
-#define BCHP_CLKGEN_PLL_NETWORK_PLL_RESET_reserved0_SHIFT 2
-
-/* CLKGEN :: PLL_NETWORK_PLL_RESET :: RESETD [01:01] */
-#define BCHP_CLKGEN_PLL_NETWORK_PLL_RESET_RESETD_MASK 0x00000002
-#define BCHP_CLKGEN_PLL_NETWORK_PLL_RESET_RESETD_SHIFT 1
-#define BCHP_CLKGEN_PLL_NETWORK_PLL_RESET_RESETD_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_NETWORK_PLL_RESET :: RESETA [00:00] */
-#define BCHP_CLKGEN_PLL_NETWORK_PLL_RESET_RESETA_MASK 0x00000001
-#define BCHP_CLKGEN_PLL_NETWORK_PLL_RESET_RESETA_SHIFT 0
-#define BCHP_CLKGEN_PLL_NETWORK_PLL_RESET_RESETA_DEFAULT 0x00000000
-
-/***************************************************************************
- *PLL_NETWORK_PLL_SSC_MODE_CONTROL_HIGH - Higher bits of Spread Spectrum mode control
- ***************************************************************************/
-/* CLKGEN :: PLL_NETWORK_PLL_SSC_MODE_CONTROL_HIGH :: reserved0 [31:16] */
-#define BCHP_CLKGEN_PLL_NETWORK_PLL_SSC_MODE_CONTROL_HIGH_reserved0_MASK 0xffff0000
-#define BCHP_CLKGEN_PLL_NETWORK_PLL_SSC_MODE_CONTROL_HIGH_reserved0_SHIFT 16
-
-/* CLKGEN :: PLL_NETWORK_PLL_SSC_MODE_CONTROL_HIGH :: SSC_STEP [15:00] */
-#define BCHP_CLKGEN_PLL_NETWORK_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_MASK 0x0000ffff
-#define BCHP_CLKGEN_PLL_NETWORK_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_SHIFT 0
-#define BCHP_CLKGEN_PLL_NETWORK_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *PLL_NETWORK_PLL_SSC_MODE_CONTROL_LOW - Lower bits of Spread Spectrum mode control
- ***************************************************************************/
-/* CLKGEN :: PLL_NETWORK_PLL_SSC_MODE_CONTROL_LOW :: reserved0 [31:23] */
-#define BCHP_CLKGEN_PLL_NETWORK_PLL_SSC_MODE_CONTROL_LOW_reserved0_MASK 0xff800000
-#define BCHP_CLKGEN_PLL_NETWORK_PLL_SSC_MODE_CONTROL_LOW_reserved0_SHIFT 23
-
-/* CLKGEN :: PLL_NETWORK_PLL_SSC_MODE_CONTROL_LOW :: SSC_MODE [22:22] */
-#define BCHP_CLKGEN_PLL_NETWORK_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_MASK 0x00400000
-#define BCHP_CLKGEN_PLL_NETWORK_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_SHIFT 22
-#define BCHP_CLKGEN_PLL_NETWORK_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_NETWORK_PLL_SSC_MODE_CONTROL_LOW :: SSC_LIMIT [21:00] */
-#define BCHP_CLKGEN_PLL_NETWORK_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_MASK 0x003fffff
-#define BCHP_CLKGEN_PLL_NETWORK_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_SHIFT 0
-#define BCHP_CLKGEN_PLL_NETWORK_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_DEFAULT 0x00000000
-
-/***************************************************************************
- *PLL_NETWORK_PLL_STATUS - Status
- ***************************************************************************/
-/* CLKGEN :: PLL_NETWORK_PLL_STATUS :: reserved0 [31:12] */
-#define BCHP_CLKGEN_PLL_NETWORK_PLL_STATUS_reserved0_MASK 0xfffff000
-#define BCHP_CLKGEN_PLL_NETWORK_PLL_STATUS_reserved0_SHIFT 12
-
-/* CLKGEN :: PLL_NETWORK_PLL_STATUS :: TEST_STATUS [11:00] */
-#define BCHP_CLKGEN_PLL_NETWORK_PLL_STATUS_TEST_STATUS_MASK 0x00000fff
-#define BCHP_CLKGEN_PLL_NETWORK_PLL_STATUS_TEST_STATUS_SHIFT 0
-
-/***************************************************************************
- *PLL_RAAGA_PLL_CHANNEL_CTRL_CH_0 - PLL CHANNEL control CH 0
- ***************************************************************************/
-/* CLKGEN :: PLL_RAAGA_PLL_CHANNEL_CTRL_CH_0 :: reserved0 [31:11] */
-#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_0_reserved0_MASK 0xfffff800
-#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_0_reserved0_SHIFT 11
-
-/* CLKGEN :: PLL_RAAGA_PLL_CHANNEL_CTRL_CH_0 :: POST_DIVIDER_HOLD_CH0 [10:10] */
-#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_MASK 0x00000400
-#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_SHIFT 10
-#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_RAAGA_PLL_CHANNEL_CTRL_CH_0 :: PHASE_OFFSET_CH0 [09:09] */
-#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_MASK 0x00000200
-#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_SHIFT 9
-#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_RAAGA_PLL_CHANNEL_CTRL_CH_0 :: MDIV_CH0 [08:01] */
-#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_MASK 0x000001fe
-#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_SHIFT 1
-#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_DEFAULT 0x00000007
-
-/* CLKGEN :: PLL_RAAGA_PLL_CHANNEL_CTRL_CH_0 :: CLOCK_DIS_CH0 [00:00] */
-#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_MASK 0x00000001
-#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_SHIFT 0
-#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_DEFAULT 0x00000000
-
-/***************************************************************************
- *PLL_RAAGA_PLL_CHANNEL_CTRL_CH_3 - PLL CHANNEL control CH 3
- ***************************************************************************/
-/* CLKGEN :: PLL_RAAGA_PLL_CHANNEL_CTRL_CH_3 :: reserved0 [31:11] */
-#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_3_reserved0_MASK 0xfffff800
-#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_3_reserved0_SHIFT 11
-
-/* CLKGEN :: PLL_RAAGA_PLL_CHANNEL_CTRL_CH_3 :: POST_DIVIDER_HOLD_CH3 [10:10] */
-#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_HOLD_CH3_MASK 0x00000400
-#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_HOLD_CH3_SHIFT 10
-#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_HOLD_CH3_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_RAAGA_PLL_CHANNEL_CTRL_CH_3 :: PHASE_OFFSET_CH3 [09:09] */
-#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_3_PHASE_OFFSET_CH3_MASK 0x00000200
-#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_3_PHASE_OFFSET_CH3_SHIFT 9
-#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_3_PHASE_OFFSET_CH3_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_RAAGA_PLL_CHANNEL_CTRL_CH_3 :: MDIV_CH3 [08:01] */
-#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_3_MDIV_CH3_MASK 0x000001fe
-#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_3_MDIV_CH3_SHIFT 1
-#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_3_MDIV_CH3_DEFAULT 0x0000000b
-
-/* CLKGEN :: PLL_RAAGA_PLL_CHANNEL_CTRL_CH_3 :: CLOCK_DIS_CH3 [00:00] */
-#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_3_CLOCK_DIS_CH3_MASK 0x00000001
-#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_3_CLOCK_DIS_CH3_SHIFT 0
-#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_3_CLOCK_DIS_CH3_DEFAULT 0x00000000
-
-/***************************************************************************
- *PLL_RAAGA_PLL_CHANNEL_CTRL_CH_4 - PLL CHANNEL control CH 4
- ***************************************************************************/
-/* CLKGEN :: PLL_RAAGA_PLL_CHANNEL_CTRL_CH_4 :: reserved0 [31:11] */
-#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_4_reserved0_MASK 0xfffff800
-#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_4_reserved0_SHIFT 11
-
-/* CLKGEN :: PLL_RAAGA_PLL_CHANNEL_CTRL_CH_4 :: POST_DIVIDER_HOLD_CH4 [10:10] */
-#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_4_POST_DIVIDER_HOLD_CH4_MASK 0x00000400
-#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_4_POST_DIVIDER_HOLD_CH4_SHIFT 10
-#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_4_POST_DIVIDER_HOLD_CH4_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_RAAGA_PLL_CHANNEL_CTRL_CH_4 :: PHASE_OFFSET_CH4 [09:09] */
-#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_4_PHASE_OFFSET_CH4_MASK 0x00000200
-#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_4_PHASE_OFFSET_CH4_SHIFT 9
-#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_4_PHASE_OFFSET_CH4_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_RAAGA_PLL_CHANNEL_CTRL_CH_4 :: MDIV_CH4 [08:01] */
-#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_4_MDIV_CH4_MASK 0x000001fe
-#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_4_MDIV_CH4_SHIFT 1
-#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_4_MDIV_CH4_DEFAULT 0x00000064
-
-/* CLKGEN :: PLL_RAAGA_PLL_CHANNEL_CTRL_CH_4 :: CLOCK_DIS_CH4 [00:00] */
-#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_4_CLOCK_DIS_CH4_MASK 0x00000001
-#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_4_CLOCK_DIS_CH4_SHIFT 0
-#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_4_CLOCK_DIS_CH4_DEFAULT 0x00000001
-
-/***************************************************************************
- *PLL_RAAGA_PLL_DIV - Pre multiplier
- ***************************************************************************/
-/* CLKGEN :: PLL_RAAGA_PLL_DIV :: reserved0 [31:14] */
-#define BCHP_CLKGEN_PLL_RAAGA_PLL_DIV_reserved0_MASK 0xffffc000
-#define BCHP_CLKGEN_PLL_RAAGA_PLL_DIV_reserved0_SHIFT 14
-
-/* CLKGEN :: PLL_RAAGA_PLL_DIV :: PDIV [13:10] */
-#define BCHP_CLKGEN_PLL_RAAGA_PLL_DIV_PDIV_MASK 0x00003c00
-#define BCHP_CLKGEN_PLL_RAAGA_PLL_DIV_PDIV_SHIFT 10
-#define BCHP_CLKGEN_PLL_RAAGA_PLL_DIV_PDIV_DEFAULT 0x00000002
-
-/* CLKGEN :: PLL_RAAGA_PLL_DIV :: NDIV_INT [09:00] */
-#define BCHP_CLKGEN_PLL_RAAGA_PLL_DIV_NDIV_INT_MASK 0x000003ff
-#define BCHP_CLKGEN_PLL_RAAGA_PLL_DIV_NDIV_INT_SHIFT 0
-#define BCHP_CLKGEN_PLL_RAAGA_PLL_DIV_NDIV_INT_DEFAULT 0x0000008f
-
-/***************************************************************************
- *PLL_RAAGA_PLL_GAIN - PLL GAIN
- ***************************************************************************/
-/* CLKGEN :: PLL_RAAGA_PLL_GAIN :: reserved0 [31:10] */
-#define BCHP_CLKGEN_PLL_RAAGA_PLL_GAIN_reserved0_MASK 0xfffffc00
-#define BCHP_CLKGEN_PLL_RAAGA_PLL_GAIN_reserved0_SHIFT 10
-
-/* CLKGEN :: PLL_RAAGA_PLL_GAIN :: LOOP_GAIN_PROPORTIONAL_IN_PHASE [09:06] */
-#define BCHP_CLKGEN_PLL_RAAGA_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_MASK 0x000003c0
-#define BCHP_CLKGEN_PLL_RAAGA_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_SHIFT 6
-#define BCHP_CLKGEN_PLL_RAAGA_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_DEFAULT 0x00000003
-
-/* CLKGEN :: PLL_RAAGA_PLL_GAIN :: LOOP_GAIN_IN_FREQ [05:03] */
-#define BCHP_CLKGEN_PLL_RAAGA_PLL_GAIN_LOOP_GAIN_IN_FREQ_MASK 0x00000038
-#define BCHP_CLKGEN_PLL_RAAGA_PLL_GAIN_LOOP_GAIN_IN_FREQ_SHIFT 3
-#define BCHP_CLKGEN_PLL_RAAGA_PLL_GAIN_LOOP_GAIN_IN_FREQ_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_RAAGA_PLL_GAIN :: LOOP_GAIN_INTEGRATOR_IN_PHASE [02:00] */
-#define BCHP_CLKGEN_PLL_RAAGA_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_MASK 0x00000007
-#define BCHP_CLKGEN_PLL_RAAGA_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_SHIFT 0
-#define BCHP_CLKGEN_PLL_RAAGA_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_DEFAULT 0x00000002
-
-/***************************************************************************
- *PLL_RAAGA_PLL_LDO_PWRON - LDO Power on
- ***************************************************************************/
-/* CLKGEN :: PLL_RAAGA_PLL_LDO_PWRON :: reserved0 [31:01] */
-#define BCHP_CLKGEN_PLL_RAAGA_PLL_LDO_PWRON_reserved0_MASK 0xfffffffe
-#define BCHP_CLKGEN_PLL_RAAGA_PLL_LDO_PWRON_reserved0_SHIFT 1
-
-/* CLKGEN :: PLL_RAAGA_PLL_LDO_PWRON :: LDO_PWRON_PLL [00:00] */
-#define BCHP_CLKGEN_PLL_RAAGA_PLL_LDO_PWRON_LDO_PWRON_PLL_MASK 0x00000001
-#define BCHP_CLKGEN_PLL_RAAGA_PLL_LDO_PWRON_LDO_PWRON_PLL_SHIFT 0
-#define BCHP_CLKGEN_PLL_RAAGA_PLL_LDO_PWRON_LDO_PWRON_PLL_DEFAULT 0x00000001
-
-/***************************************************************************
- *PLL_RAAGA_PLL_LOCK_STATUS - Lock Status
- ***************************************************************************/
-/* CLKGEN :: PLL_RAAGA_PLL_LOCK_STATUS :: reserved0 [31:02] */
-#define BCHP_CLKGEN_PLL_RAAGA_PLL_LOCK_STATUS_reserved0_MASK 0xfffffffc
-#define BCHP_CLKGEN_PLL_RAAGA_PLL_LOCK_STATUS_reserved0_SHIFT 2
-
-/* CLKGEN :: PLL_RAAGA_PLL_LOCK_STATUS :: LOCK_LOST [01:01] */
-#define BCHP_CLKGEN_PLL_RAAGA_PLL_LOCK_STATUS_LOCK_LOST_MASK 0x00000002
-#define BCHP_CLKGEN_PLL_RAAGA_PLL_LOCK_STATUS_LOCK_LOST_SHIFT 1
-
-/* CLKGEN :: PLL_RAAGA_PLL_LOCK_STATUS :: LOCK [00:00] */
-#define BCHP_CLKGEN_PLL_RAAGA_PLL_LOCK_STATUS_LOCK_MASK 0x00000001
-#define BCHP_CLKGEN_PLL_RAAGA_PLL_LOCK_STATUS_LOCK_SHIFT 0
-
-/***************************************************************************
- *PLL_RAAGA_PLL_MISC - Mscellaneous control bus.
- ***************************************************************************/
-/* CLKGEN :: PLL_RAAGA_PLL_MISC :: VCO_RANGE [31:30] */
-#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_VCO_RANGE_MASK 0xc0000000
-#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_VCO_RANGE_SHIFT 30
-#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_VCO_RANGE_DEFAULT 0x00000002
-
-/* CLKGEN :: PLL_RAAGA_PLL_MISC :: VCO_FB_DIV2 [29:29] */
-#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_VCO_FB_DIV2_MASK 0x20000000
-#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_VCO_FB_DIV2_SHIFT 29
-#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_VCO_FB_DIV2_DEFAULT 0x00000001
-
-/* CLKGEN :: PLL_RAAGA_PLL_MISC :: STAT_UPDATE [28:28] */
-#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_STAT_UPDATE_MASK 0x10000000
-#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_STAT_UPDATE_SHIFT 28
-#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_STAT_UPDATE_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_RAAGA_PLL_MISC :: STAT_SELECT [27:25] */
-#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_STAT_SELECT_MASK 0x0e000000
-#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_STAT_SELECT_SHIFT 25
-#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_STAT_SELECT_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_RAAGA_PLL_MISC :: STAT_RESET [24:24] */
-#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_STAT_RESET_MASK 0x01000000
-#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_STAT_RESET_SHIFT 24
-#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_STAT_RESET_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_RAAGA_PLL_MISC :: STAT_MODE [23:22] */
-#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_STAT_MODE_MASK 0x00c00000
-#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_STAT_MODE_SHIFT 22
-#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_STAT_MODE_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_RAAGA_PLL_MISC :: PWM_RATE [21:20] */
-#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_PWM_RATE_MASK 0x00300000
-#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_PWM_RATE_SHIFT 20
-#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_PWM_RATE_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_RAAGA_PLL_MISC :: POST_CTRL_RESETB [19:18] */
-#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_POST_CTRL_RESETB_MASK 0x000c0000
-#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_POST_CTRL_RESETB_SHIFT 18
-#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_POST_CTRL_RESETB_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_RAAGA_PLL_MISC :: PLLRESERVED2 [17:16] */
-#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_PLLRESERVED2_MASK 0x00030000
-#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_PLLRESERVED2_SHIFT 16
-#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_PLLRESERVED2_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_RAAGA_PLL_MISC :: PLLRESERVED1 [15:15] */
-#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_PLLRESERVED1_MASK 0x00008000
-#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_PLLRESERVED1_SHIFT 15
-#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_PLLRESERVED1_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_RAAGA_PLL_MISC :: NDIV_RELOCK [14:14] */
-#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_NDIV_RELOCK_MASK 0x00004000
-#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_NDIV_RELOCK_SHIFT 14
-#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_NDIV_RELOCK_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_RAAGA_PLL_MISC :: FAST_LOCK [13:13] */
-#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_FAST_LOCK_MASK 0x00002000
-#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_FAST_LOCK_SHIFT 13
-#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_FAST_LOCK_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_RAAGA_PLL_MISC :: DCO_CTRL_BYPASS_ENABLE [12:12] */
-#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_MASK 0x00001000
-#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_SHIFT 12
-#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_RAAGA_PLL_MISC :: DCO_CTRL_BYPASS [11:00] */
-#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_DCO_CTRL_BYPASS_MASK 0x00000fff
-#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_DCO_CTRL_BYPASS_SHIFT 0
-#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_DCO_CTRL_BYPASS_DEFAULT 0x00000000
-
-/***************************************************************************
- *PLL_RAAGA_PLL_MISC2 - Mscellaneous control bus continued.
- ***************************************************************************/
-/* CLKGEN :: PLL_RAAGA_PLL_MISC2 :: PLLRESERVED0 [31:00] */
-#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC2_PLLRESERVED0_MASK 0xffffffff
-#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC2_PLLRESERVED0_SHIFT 0
-#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC2_PLLRESERVED0_DEFAULT 0x00000001
-
-/***************************************************************************
- *PLL_RAAGA_PLL_PWRON - Poweron
- ***************************************************************************/
-/* CLKGEN :: PLL_RAAGA_PLL_PWRON :: reserved0 [31:01] */
-#define BCHP_CLKGEN_PLL_RAAGA_PLL_PWRON_reserved0_MASK 0xfffffffe
-#define BCHP_CLKGEN_PLL_RAAGA_PLL_PWRON_reserved0_SHIFT 1
-
-/* CLKGEN :: PLL_RAAGA_PLL_PWRON :: PWRON_PLL [00:00] */
-#define BCHP_CLKGEN_PLL_RAAGA_PLL_PWRON_PWRON_PLL_MASK 0x00000001
-#define BCHP_CLKGEN_PLL_RAAGA_PLL_PWRON_PWRON_PLL_SHIFT 0
-#define BCHP_CLKGEN_PLL_RAAGA_PLL_PWRON_PWRON_PLL_DEFAULT 0x00000001
-
-/***************************************************************************
- *PLL_RAAGA_PLL_RESET - Resets
- ***************************************************************************/
-/* CLKGEN :: PLL_RAAGA_PLL_RESET :: reserved0 [31:02] */
-#define BCHP_CLKGEN_PLL_RAAGA_PLL_RESET_reserved0_MASK 0xfffffffc
-#define BCHP_CLKGEN_PLL_RAAGA_PLL_RESET_reserved0_SHIFT 2
-
-/* CLKGEN :: PLL_RAAGA_PLL_RESET :: RESETD [01:01] */
-#define BCHP_CLKGEN_PLL_RAAGA_PLL_RESET_RESETD_MASK 0x00000002
-#define BCHP_CLKGEN_PLL_RAAGA_PLL_RESET_RESETD_SHIFT 1
-#define BCHP_CLKGEN_PLL_RAAGA_PLL_RESET_RESETD_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_RAAGA_PLL_RESET :: RESETA [00:00] */
-#define BCHP_CLKGEN_PLL_RAAGA_PLL_RESET_RESETA_MASK 0x00000001
-#define BCHP_CLKGEN_PLL_RAAGA_PLL_RESET_RESETA_SHIFT 0
-#define BCHP_CLKGEN_PLL_RAAGA_PLL_RESET_RESETA_DEFAULT 0x00000000
-
-/***************************************************************************
- *PLL_RAAGA_PLL_SSC_MODE_CONTROL_HIGH - Higher bits of Spread Spectrum mode control
- ***************************************************************************/
-/* CLKGEN :: PLL_RAAGA_PLL_SSC_MODE_CONTROL_HIGH :: reserved0 [31:16] */
-#define BCHP_CLKGEN_PLL_RAAGA_PLL_SSC_MODE_CONTROL_HIGH_reserved0_MASK 0xffff0000
-#define BCHP_CLKGEN_PLL_RAAGA_PLL_SSC_MODE_CONTROL_HIGH_reserved0_SHIFT 16
-
-/* CLKGEN :: PLL_RAAGA_PLL_SSC_MODE_CONTROL_HIGH :: SSC_STEP [15:00] */
-#define BCHP_CLKGEN_PLL_RAAGA_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_MASK 0x0000ffff
-#define BCHP_CLKGEN_PLL_RAAGA_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_SHIFT 0
-#define BCHP_CLKGEN_PLL_RAAGA_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *PLL_RAAGA_PLL_SSC_MODE_CONTROL_LOW - Lower bits of Spread Spectrum mode control
- ***************************************************************************/
-/* CLKGEN :: PLL_RAAGA_PLL_SSC_MODE_CONTROL_LOW :: reserved0 [31:23] */
-#define BCHP_CLKGEN_PLL_RAAGA_PLL_SSC_MODE_CONTROL_LOW_reserved0_MASK 0xff800000
-#define BCHP_CLKGEN_PLL_RAAGA_PLL_SSC_MODE_CONTROL_LOW_reserved0_SHIFT 23
-
-/* CLKGEN :: PLL_RAAGA_PLL_SSC_MODE_CONTROL_LOW :: SSC_MODE [22:22] */
-#define BCHP_CLKGEN_PLL_RAAGA_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_MASK 0x00400000
-#define BCHP_CLKGEN_PLL_RAAGA_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_SHIFT 22
-#define BCHP_CLKGEN_PLL_RAAGA_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_RAAGA_PLL_SSC_MODE_CONTROL_LOW :: SSC_LIMIT [21:00] */
-#define BCHP_CLKGEN_PLL_RAAGA_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_MASK 0x003fffff
-#define BCHP_CLKGEN_PLL_RAAGA_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_SHIFT 0
-#define BCHP_CLKGEN_PLL_RAAGA_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_DEFAULT 0x00000000
-
-/***************************************************************************
- *PLL_RAAGA_PLL_STATUS - Status
- ***************************************************************************/
-/* CLKGEN :: PLL_RAAGA_PLL_STATUS :: reserved0 [31:12] */
-#define BCHP_CLKGEN_PLL_RAAGA_PLL_STATUS_reserved0_MASK 0xfffff000
-#define BCHP_CLKGEN_PLL_RAAGA_PLL_STATUS_reserved0_SHIFT 12
-
-/* CLKGEN :: PLL_RAAGA_PLL_STATUS :: TEST_STATUS [11:00] */
-#define BCHP_CLKGEN_PLL_RAAGA_PLL_STATUS_TEST_STATUS_MASK 0x00000fff
-#define BCHP_CLKGEN_PLL_RAAGA_PLL_STATUS_TEST_STATUS_SHIFT 0
-
-/***************************************************************************
- *PLL_SC0_PLL_CHANNEL_CTRL_CH_0 - PLL CHANNEL control CH 0
- ***************************************************************************/
-/* CLKGEN :: PLL_SC0_PLL_CHANNEL_CTRL_CH_0 :: reserved0 [31:11] */
-#define BCHP_CLKGEN_PLL_SC0_PLL_CHANNEL_CTRL_CH_0_reserved0_MASK 0xfffff800
-#define BCHP_CLKGEN_PLL_SC0_PLL_CHANNEL_CTRL_CH_0_reserved0_SHIFT 11
-
-/* CLKGEN :: PLL_SC0_PLL_CHANNEL_CTRL_CH_0 :: POST_DIVIDER_HOLD_CH0 [10:10] */
-#define BCHP_CLKGEN_PLL_SC0_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_MASK 0x00000400
-#define BCHP_CLKGEN_PLL_SC0_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_SHIFT 10
-#define BCHP_CLKGEN_PLL_SC0_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_SC0_PLL_CHANNEL_CTRL_CH_0 :: PHASE_OFFSET_CH0 [09:09] */
-#define BCHP_CLKGEN_PLL_SC0_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_MASK 0x00000200
-#define BCHP_CLKGEN_PLL_SC0_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_SHIFT 9
-#define BCHP_CLKGEN_PLL_SC0_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_SC0_PLL_CHANNEL_CTRL_CH_0 :: MDIV_CH0 [08:01] */
-#define BCHP_CLKGEN_PLL_SC0_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_MASK 0x000001fe
-#define BCHP_CLKGEN_PLL_SC0_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_SHIFT 1
-#define BCHP_CLKGEN_PLL_SC0_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_DEFAULT 0x00000030
-
-/* CLKGEN :: PLL_SC0_PLL_CHANNEL_CTRL_CH_0 :: CLOCK_DIS_CH0 [00:00] */
-#define BCHP_CLKGEN_PLL_SC0_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_MASK 0x00000001
-#define BCHP_CLKGEN_PLL_SC0_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_SHIFT 0
-#define BCHP_CLKGEN_PLL_SC0_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_DEFAULT 0x00000000
-
-/***************************************************************************
- *PLL_SC0_PLL_DIV - Pre multiplier
- ***************************************************************************/
-/* CLKGEN :: PLL_SC0_PLL_DIV :: reserved0 [31:14] */
-#define BCHP_CLKGEN_PLL_SC0_PLL_DIV_reserved0_MASK 0xffffc000
-#define BCHP_CLKGEN_PLL_SC0_PLL_DIV_reserved0_SHIFT 14
-
-/* CLKGEN :: PLL_SC0_PLL_DIV :: PDIV [13:10] */
-#define BCHP_CLKGEN_PLL_SC0_PLL_DIV_PDIV_MASK 0x00003c00
-#define BCHP_CLKGEN_PLL_SC0_PLL_DIV_PDIV_SHIFT 10
-#define BCHP_CLKGEN_PLL_SC0_PLL_DIV_PDIV_DEFAULT 0x00000002
-
-/* CLKGEN :: PLL_SC0_PLL_DIV :: NDIV_INT [09:00] */
-#define BCHP_CLKGEN_PLL_SC0_PLL_DIV_NDIV_INT_MASK 0x000003ff
-#define BCHP_CLKGEN_PLL_SC0_PLL_DIV_NDIV_INT_SHIFT 0
-#define BCHP_CLKGEN_PLL_SC0_PLL_DIV_NDIV_INT_DEFAULT 0x00000030
-
-/***************************************************************************
- *PLL_SC0_PLL_FRAC - Fractional
- ***************************************************************************/
-/* CLKGEN :: PLL_SC0_PLL_FRAC :: reserved0 [31:20] */
-#define BCHP_CLKGEN_PLL_SC0_PLL_FRAC_reserved0_MASK 0xfff00000
-#define BCHP_CLKGEN_PLL_SC0_PLL_FRAC_reserved0_SHIFT 20
-
-/* CLKGEN :: PLL_SC0_PLL_FRAC :: FRAC_CONTROL [19:00] */
-#define BCHP_CLKGEN_PLL_SC0_PLL_FRAC_FRAC_CONTROL_MASK 0x000fffff
-#define BCHP_CLKGEN_PLL_SC0_PLL_FRAC_FRAC_CONTROL_SHIFT 0
-#define BCHP_CLKGEN_PLL_SC0_PLL_FRAC_FRAC_CONTROL_DEFAULT 0x00000000
-
-/***************************************************************************
- *PLL_SC0_PLL_GAIN - PLL GAIN
- ***************************************************************************/
-/* CLKGEN :: PLL_SC0_PLL_GAIN :: reserved0 [31:10] */
-#define BCHP_CLKGEN_PLL_SC0_PLL_GAIN_reserved0_MASK 0xfffffc00
-#define BCHP_CLKGEN_PLL_SC0_PLL_GAIN_reserved0_SHIFT 10
-
-/* CLKGEN :: PLL_SC0_PLL_GAIN :: LOOP_GAIN_PROPORTIONAL_IN_PHASE [09:06] */
-#define BCHP_CLKGEN_PLL_SC0_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_MASK 0x000003c0
-#define BCHP_CLKGEN_PLL_SC0_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_SHIFT 6
-#define BCHP_CLKGEN_PLL_SC0_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_DEFAULT 0x00000005
-
-/* CLKGEN :: PLL_SC0_PLL_GAIN :: LOOP_GAIN_IN_FREQ [05:03] */
-#define BCHP_CLKGEN_PLL_SC0_PLL_GAIN_LOOP_GAIN_IN_FREQ_MASK 0x00000038
-#define BCHP_CLKGEN_PLL_SC0_PLL_GAIN_LOOP_GAIN_IN_FREQ_SHIFT 3
-#define BCHP_CLKGEN_PLL_SC0_PLL_GAIN_LOOP_GAIN_IN_FREQ_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_SC0_PLL_GAIN :: LOOP_GAIN_INTEGRATOR_IN_PHASE [02:00] */
-#define BCHP_CLKGEN_PLL_SC0_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_MASK 0x00000007
-#define BCHP_CLKGEN_PLL_SC0_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_SHIFT 0
-#define BCHP_CLKGEN_PLL_SC0_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_DEFAULT 0x00000002
-
-/***************************************************************************
- *PLL_SC0_PLL_LOCK_STATUS - Lock Status
- ***************************************************************************/
-/* CLKGEN :: PLL_SC0_PLL_LOCK_STATUS :: reserved0 [31:02] */
-#define BCHP_CLKGEN_PLL_SC0_PLL_LOCK_STATUS_reserved0_MASK 0xfffffffc
-#define BCHP_CLKGEN_PLL_SC0_PLL_LOCK_STATUS_reserved0_SHIFT 2
-
-/* CLKGEN :: PLL_SC0_PLL_LOCK_STATUS :: LOCK_LOST [01:01] */
-#define BCHP_CLKGEN_PLL_SC0_PLL_LOCK_STATUS_LOCK_LOST_MASK 0x00000002
-#define BCHP_CLKGEN_PLL_SC0_PLL_LOCK_STATUS_LOCK_LOST_SHIFT 1
-
-/* CLKGEN :: PLL_SC0_PLL_LOCK_STATUS :: LOCK [00:00] */
-#define BCHP_CLKGEN_PLL_SC0_PLL_LOCK_STATUS_LOCK_MASK 0x00000001
-#define BCHP_CLKGEN_PLL_SC0_PLL_LOCK_STATUS_LOCK_SHIFT 0
-
-/***************************************************************************
- *PLL_SC0_PLL_MISC - Mscellaneous control bus.
- ***************************************************************************/
-/* CLKGEN :: PLL_SC0_PLL_MISC :: VCO_RANGE [31:30] */
-#define BCHP_CLKGEN_PLL_SC0_PLL_MISC_VCO_RANGE_MASK 0xc0000000
-#define BCHP_CLKGEN_PLL_SC0_PLL_MISC_VCO_RANGE_SHIFT 30
-#define BCHP_CLKGEN_PLL_SC0_PLL_MISC_VCO_RANGE_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_SC0_PLL_MISC :: VCO_FB_DIV2 [29:29] */
-#define BCHP_CLKGEN_PLL_SC0_PLL_MISC_VCO_FB_DIV2_MASK 0x20000000
-#define BCHP_CLKGEN_PLL_SC0_PLL_MISC_VCO_FB_DIV2_SHIFT 29
-#define BCHP_CLKGEN_PLL_SC0_PLL_MISC_VCO_FB_DIV2_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_SC0_PLL_MISC :: STAT_UPDATE [28:28] */
-#define BCHP_CLKGEN_PLL_SC0_PLL_MISC_STAT_UPDATE_MASK 0x10000000
-#define BCHP_CLKGEN_PLL_SC0_PLL_MISC_STAT_UPDATE_SHIFT 28
-#define BCHP_CLKGEN_PLL_SC0_PLL_MISC_STAT_UPDATE_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_SC0_PLL_MISC :: STAT_SELECT [27:25] */
-#define BCHP_CLKGEN_PLL_SC0_PLL_MISC_STAT_SELECT_MASK 0x0e000000
-#define BCHP_CLKGEN_PLL_SC0_PLL_MISC_STAT_SELECT_SHIFT 25
-#define BCHP_CLKGEN_PLL_SC0_PLL_MISC_STAT_SELECT_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_SC0_PLL_MISC :: STAT_RESET [24:24] */
-#define BCHP_CLKGEN_PLL_SC0_PLL_MISC_STAT_RESET_MASK 0x01000000
-#define BCHP_CLKGEN_PLL_SC0_PLL_MISC_STAT_RESET_SHIFT 24
-#define BCHP_CLKGEN_PLL_SC0_PLL_MISC_STAT_RESET_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_SC0_PLL_MISC :: STAT_MODE [23:22] */
-#define BCHP_CLKGEN_PLL_SC0_PLL_MISC_STAT_MODE_MASK 0x00c00000
-#define BCHP_CLKGEN_PLL_SC0_PLL_MISC_STAT_MODE_SHIFT 22
-#define BCHP_CLKGEN_PLL_SC0_PLL_MISC_STAT_MODE_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_SC0_PLL_MISC :: PWM_RATE [21:20] */
-#define BCHP_CLKGEN_PLL_SC0_PLL_MISC_PWM_RATE_MASK 0x00300000
-#define BCHP_CLKGEN_PLL_SC0_PLL_MISC_PWM_RATE_SHIFT 20
-#define BCHP_CLKGEN_PLL_SC0_PLL_MISC_PWM_RATE_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_SC0_PLL_MISC :: POST_CTRL_RESETB [19:18] */
-#define BCHP_CLKGEN_PLL_SC0_PLL_MISC_POST_CTRL_RESETB_MASK 0x000c0000
-#define BCHP_CLKGEN_PLL_SC0_PLL_MISC_POST_CTRL_RESETB_SHIFT 18
-#define BCHP_CLKGEN_PLL_SC0_PLL_MISC_POST_CTRL_RESETB_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_SC0_PLL_MISC :: PLLRESERVED2 [17:16] */
-#define BCHP_CLKGEN_PLL_SC0_PLL_MISC_PLLRESERVED2_MASK 0x00030000
-#define BCHP_CLKGEN_PLL_SC0_PLL_MISC_PLLRESERVED2_SHIFT 16
-#define BCHP_CLKGEN_PLL_SC0_PLL_MISC_PLLRESERVED2_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_SC0_PLL_MISC :: PLLRESERVED1 [15:15] */
-#define BCHP_CLKGEN_PLL_SC0_PLL_MISC_PLLRESERVED1_MASK 0x00008000
-#define BCHP_CLKGEN_PLL_SC0_PLL_MISC_PLLRESERVED1_SHIFT 15
-#define BCHP_CLKGEN_PLL_SC0_PLL_MISC_PLLRESERVED1_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_SC0_PLL_MISC :: NDIV_RELOCK [14:14] */
-#define BCHP_CLKGEN_PLL_SC0_PLL_MISC_NDIV_RELOCK_MASK 0x00004000
-#define BCHP_CLKGEN_PLL_SC0_PLL_MISC_NDIV_RELOCK_SHIFT 14
-#define BCHP_CLKGEN_PLL_SC0_PLL_MISC_NDIV_RELOCK_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_SC0_PLL_MISC :: FAST_LOCK [13:13] */
-#define BCHP_CLKGEN_PLL_SC0_PLL_MISC_FAST_LOCK_MASK 0x00002000
-#define BCHP_CLKGEN_PLL_SC0_PLL_MISC_FAST_LOCK_SHIFT 13
-#define BCHP_CLKGEN_PLL_SC0_PLL_MISC_FAST_LOCK_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_SC0_PLL_MISC :: DCO_CTRL_BYPASS_ENABLE [12:12] */
-#define BCHP_CLKGEN_PLL_SC0_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_MASK 0x00001000
-#define BCHP_CLKGEN_PLL_SC0_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_SHIFT 12
-#define BCHP_CLKGEN_PLL_SC0_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_SC0_PLL_MISC :: DCO_CTRL_BYPASS [11:00] */
-#define BCHP_CLKGEN_PLL_SC0_PLL_MISC_DCO_CTRL_BYPASS_MASK 0x00000fff
-#define BCHP_CLKGEN_PLL_SC0_PLL_MISC_DCO_CTRL_BYPASS_SHIFT 0
-#define BCHP_CLKGEN_PLL_SC0_PLL_MISC_DCO_CTRL_BYPASS_DEFAULT 0x00000000
-
-/***************************************************************************
- *PLL_SC0_PLL_MISC2 - Mscellaneous control bus continued.
- ***************************************************************************/
-/* CLKGEN :: PLL_SC0_PLL_MISC2 :: PLLRESERVED0 [31:00] */
-#define BCHP_CLKGEN_PLL_SC0_PLL_MISC2_PLLRESERVED0_MASK 0xffffffff
-#define BCHP_CLKGEN_PLL_SC0_PLL_MISC2_PLLRESERVED0_SHIFT 0
-#define BCHP_CLKGEN_PLL_SC0_PLL_MISC2_PLLRESERVED0_DEFAULT 0x00000000
-
-/***************************************************************************
- *PLL_SC0_PLL_PWRON - Poweron
- ***************************************************************************/
-/* CLKGEN :: PLL_SC0_PLL_PWRON :: reserved0 [31:01] */
-#define BCHP_CLKGEN_PLL_SC0_PLL_PWRON_reserved0_MASK 0xfffffffe
-#define BCHP_CLKGEN_PLL_SC0_PLL_PWRON_reserved0_SHIFT 1
-
-/* CLKGEN :: PLL_SC0_PLL_PWRON :: PWRON_PLL [00:00] */
-#define BCHP_CLKGEN_PLL_SC0_PLL_PWRON_PWRON_PLL_MASK 0x00000001
-#define BCHP_CLKGEN_PLL_SC0_PLL_PWRON_PWRON_PLL_SHIFT 0
-#define BCHP_CLKGEN_PLL_SC0_PLL_PWRON_PWRON_PLL_DEFAULT 0x00000001
-
-/***************************************************************************
- *PLL_SC0_PLL_RESET - Resets
- ***************************************************************************/
-/* CLKGEN :: PLL_SC0_PLL_RESET :: reserved0 [31:02] */
-#define BCHP_CLKGEN_PLL_SC0_PLL_RESET_reserved0_MASK 0xfffffffc
-#define BCHP_CLKGEN_PLL_SC0_PLL_RESET_reserved0_SHIFT 2
-
-/* CLKGEN :: PLL_SC0_PLL_RESET :: RESETD [01:01] */
-#define BCHP_CLKGEN_PLL_SC0_PLL_RESET_RESETD_MASK 0x00000002
-#define BCHP_CLKGEN_PLL_SC0_PLL_RESET_RESETD_SHIFT 1
-#define BCHP_CLKGEN_PLL_SC0_PLL_RESET_RESETD_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_SC0_PLL_RESET :: RESETA [00:00] */
-#define BCHP_CLKGEN_PLL_SC0_PLL_RESET_RESETA_MASK 0x00000001
-#define BCHP_CLKGEN_PLL_SC0_PLL_RESET_RESETA_SHIFT 0
-#define BCHP_CLKGEN_PLL_SC0_PLL_RESET_RESETA_DEFAULT 0x00000000
-
-/***************************************************************************
- *PLL_SC0_PLL_SSC_MODE_CONTROL_HIGH - Higher bits of Spread Spectrum mode control
- ***************************************************************************/
-/* CLKGEN :: PLL_SC0_PLL_SSC_MODE_CONTROL_HIGH :: reserved0 [31:16] */
-#define BCHP_CLKGEN_PLL_SC0_PLL_SSC_MODE_CONTROL_HIGH_reserved0_MASK 0xffff0000
-#define BCHP_CLKGEN_PLL_SC0_PLL_SSC_MODE_CONTROL_HIGH_reserved0_SHIFT 16
-
-/* CLKGEN :: PLL_SC0_PLL_SSC_MODE_CONTROL_HIGH :: SSC_STEP [15:00] */
-#define BCHP_CLKGEN_PLL_SC0_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_MASK 0x0000ffff
-#define BCHP_CLKGEN_PLL_SC0_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_SHIFT 0
-#define BCHP_CLKGEN_PLL_SC0_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *PLL_SC0_PLL_SSC_MODE_CONTROL_LOW - Lower bits of Spread Spectrum mode control
- ***************************************************************************/
-/* CLKGEN :: PLL_SC0_PLL_SSC_MODE_CONTROL_LOW :: reserved0 [31:23] */
-#define BCHP_CLKGEN_PLL_SC0_PLL_SSC_MODE_CONTROL_LOW_reserved0_MASK 0xff800000
-#define BCHP_CLKGEN_PLL_SC0_PLL_SSC_MODE_CONTROL_LOW_reserved0_SHIFT 23
-
-/* CLKGEN :: PLL_SC0_PLL_SSC_MODE_CONTROL_LOW :: SSC_MODE [22:22] */
-#define BCHP_CLKGEN_PLL_SC0_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_MASK 0x00400000
-#define BCHP_CLKGEN_PLL_SC0_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_SHIFT 22
-#define BCHP_CLKGEN_PLL_SC0_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_SC0_PLL_SSC_MODE_CONTROL_LOW :: SSC_LIMIT [21:00] */
-#define BCHP_CLKGEN_PLL_SC0_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_MASK 0x003fffff
-#define BCHP_CLKGEN_PLL_SC0_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_SHIFT 0
-#define BCHP_CLKGEN_PLL_SC0_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_DEFAULT 0x00000000
-
-/***************************************************************************
- *PLL_SC0_PLL_STATUS - Status
- ***************************************************************************/
-/* CLKGEN :: PLL_SC0_PLL_STATUS :: reserved0 [31:12] */
-#define BCHP_CLKGEN_PLL_SC0_PLL_STATUS_reserved0_MASK 0xfffff000
-#define BCHP_CLKGEN_PLL_SC0_PLL_STATUS_reserved0_SHIFT 12
-
-/* CLKGEN :: PLL_SC0_PLL_STATUS :: TEST_STATUS [11:00] */
-#define BCHP_CLKGEN_PLL_SC0_PLL_STATUS_TEST_STATUS_MASK 0x00000fff
-#define BCHP_CLKGEN_PLL_SC0_PLL_STATUS_TEST_STATUS_SHIFT 0
-
-/***************************************************************************
- *PLL_SC1_PLL_CHANNEL_CTRL_CH_0 - PLL CHANNEL control CH 0
- ***************************************************************************/
-/* CLKGEN :: PLL_SC1_PLL_CHANNEL_CTRL_CH_0 :: reserved0 [31:11] */
-#define BCHP_CLKGEN_PLL_SC1_PLL_CHANNEL_CTRL_CH_0_reserved0_MASK 0xfffff800
-#define BCHP_CLKGEN_PLL_SC1_PLL_CHANNEL_CTRL_CH_0_reserved0_SHIFT 11
-
-/* CLKGEN :: PLL_SC1_PLL_CHANNEL_CTRL_CH_0 :: POST_DIVIDER_HOLD_CH0 [10:10] */
-#define BCHP_CLKGEN_PLL_SC1_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_MASK 0x00000400
-#define BCHP_CLKGEN_PLL_SC1_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_SHIFT 10
-#define BCHP_CLKGEN_PLL_SC1_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_SC1_PLL_CHANNEL_CTRL_CH_0 :: PHASE_OFFSET_CH0 [09:09] */
-#define BCHP_CLKGEN_PLL_SC1_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_MASK 0x00000200
-#define BCHP_CLKGEN_PLL_SC1_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_SHIFT 9
-#define BCHP_CLKGEN_PLL_SC1_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_SC1_PLL_CHANNEL_CTRL_CH_0 :: MDIV_CH0 [08:01] */
-#define BCHP_CLKGEN_PLL_SC1_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_MASK 0x000001fe
-#define BCHP_CLKGEN_PLL_SC1_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_SHIFT 1
-#define BCHP_CLKGEN_PLL_SC1_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_DEFAULT 0x00000030
-
-/* CLKGEN :: PLL_SC1_PLL_CHANNEL_CTRL_CH_0 :: CLOCK_DIS_CH0 [00:00] */
-#define BCHP_CLKGEN_PLL_SC1_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_MASK 0x00000001
-#define BCHP_CLKGEN_PLL_SC1_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_SHIFT 0
-#define BCHP_CLKGEN_PLL_SC1_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_DEFAULT 0x00000000
-
-/***************************************************************************
- *PLL_SC1_PLL_DIV - Pre multiplier
- ***************************************************************************/
-/* CLKGEN :: PLL_SC1_PLL_DIV :: reserved0 [31:14] */
-#define BCHP_CLKGEN_PLL_SC1_PLL_DIV_reserved0_MASK 0xffffc000
-#define BCHP_CLKGEN_PLL_SC1_PLL_DIV_reserved0_SHIFT 14
-
-/* CLKGEN :: PLL_SC1_PLL_DIV :: PDIV [13:10] */
-#define BCHP_CLKGEN_PLL_SC1_PLL_DIV_PDIV_MASK 0x00003c00
-#define BCHP_CLKGEN_PLL_SC1_PLL_DIV_PDIV_SHIFT 10
-#define BCHP_CLKGEN_PLL_SC1_PLL_DIV_PDIV_DEFAULT 0x00000002
-
-/* CLKGEN :: PLL_SC1_PLL_DIV :: NDIV_INT [09:00] */
-#define BCHP_CLKGEN_PLL_SC1_PLL_DIV_NDIV_INT_MASK 0x000003ff
-#define BCHP_CLKGEN_PLL_SC1_PLL_DIV_NDIV_INT_SHIFT 0
-#define BCHP_CLKGEN_PLL_SC1_PLL_DIV_NDIV_INT_DEFAULT 0x00000030
-
-/***************************************************************************
- *PLL_SC1_PLL_FRAC - Fractional
- ***************************************************************************/
-/* CLKGEN :: PLL_SC1_PLL_FRAC :: reserved0 [31:20] */
-#define BCHP_CLKGEN_PLL_SC1_PLL_FRAC_reserved0_MASK 0xfff00000
-#define BCHP_CLKGEN_PLL_SC1_PLL_FRAC_reserved0_SHIFT 20
-
-/* CLKGEN :: PLL_SC1_PLL_FRAC :: FRAC_CONTROL [19:00] */
-#define BCHP_CLKGEN_PLL_SC1_PLL_FRAC_FRAC_CONTROL_MASK 0x000fffff
-#define BCHP_CLKGEN_PLL_SC1_PLL_FRAC_FRAC_CONTROL_SHIFT 0
-#define BCHP_CLKGEN_PLL_SC1_PLL_FRAC_FRAC_CONTROL_DEFAULT 0x00000000
-
-/***************************************************************************
- *PLL_SC1_PLL_GAIN - PLL GAIN
- ***************************************************************************/
-/* CLKGEN :: PLL_SC1_PLL_GAIN :: reserved0 [31:10] */
-#define BCHP_CLKGEN_PLL_SC1_PLL_GAIN_reserved0_MASK 0xfffffc00
-#define BCHP_CLKGEN_PLL_SC1_PLL_GAIN_reserved0_SHIFT 10
-
-/* CLKGEN :: PLL_SC1_PLL_GAIN :: LOOP_GAIN_PROPORTIONAL_IN_PHASE [09:06] */
-#define BCHP_CLKGEN_PLL_SC1_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_MASK 0x000003c0
-#define BCHP_CLKGEN_PLL_SC1_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_SHIFT 6
-#define BCHP_CLKGEN_PLL_SC1_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_DEFAULT 0x00000005
-
-/* CLKGEN :: PLL_SC1_PLL_GAIN :: LOOP_GAIN_IN_FREQ [05:03] */
-#define BCHP_CLKGEN_PLL_SC1_PLL_GAIN_LOOP_GAIN_IN_FREQ_MASK 0x00000038
-#define BCHP_CLKGEN_PLL_SC1_PLL_GAIN_LOOP_GAIN_IN_FREQ_SHIFT 3
-#define BCHP_CLKGEN_PLL_SC1_PLL_GAIN_LOOP_GAIN_IN_FREQ_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_SC1_PLL_GAIN :: LOOP_GAIN_INTEGRATOR_IN_PHASE [02:00] */
-#define BCHP_CLKGEN_PLL_SC1_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_MASK 0x00000007
-#define BCHP_CLKGEN_PLL_SC1_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_SHIFT 0
-#define BCHP_CLKGEN_PLL_SC1_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_DEFAULT 0x00000002
-
-/***************************************************************************
- *PLL_SC1_PLL_LOCK_STATUS - Lock Status
- ***************************************************************************/
-/* CLKGEN :: PLL_SC1_PLL_LOCK_STATUS :: reserved0 [31:02] */
-#define BCHP_CLKGEN_PLL_SC1_PLL_LOCK_STATUS_reserved0_MASK 0xfffffffc
-#define BCHP_CLKGEN_PLL_SC1_PLL_LOCK_STATUS_reserved0_SHIFT 2
-
-/* CLKGEN :: PLL_SC1_PLL_LOCK_STATUS :: LOCK_LOST [01:01] */
-#define BCHP_CLKGEN_PLL_SC1_PLL_LOCK_STATUS_LOCK_LOST_MASK 0x00000002
-#define BCHP_CLKGEN_PLL_SC1_PLL_LOCK_STATUS_LOCK_LOST_SHIFT 1
-
-/* CLKGEN :: PLL_SC1_PLL_LOCK_STATUS :: LOCK [00:00] */
-#define BCHP_CLKGEN_PLL_SC1_PLL_LOCK_STATUS_LOCK_MASK 0x00000001
-#define BCHP_CLKGEN_PLL_SC1_PLL_LOCK_STATUS_LOCK_SHIFT 0
-
-/***************************************************************************
- *PLL_SC1_PLL_MISC - Mscellaneous control bus.
- ***************************************************************************/
-/* CLKGEN :: PLL_SC1_PLL_MISC :: VCO_RANGE [31:30] */
-#define BCHP_CLKGEN_PLL_SC1_PLL_MISC_VCO_RANGE_MASK 0xc0000000
-#define BCHP_CLKGEN_PLL_SC1_PLL_MISC_VCO_RANGE_SHIFT 30
-#define BCHP_CLKGEN_PLL_SC1_PLL_MISC_VCO_RANGE_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_SC1_PLL_MISC :: VCO_FB_DIV2 [29:29] */
-#define BCHP_CLKGEN_PLL_SC1_PLL_MISC_VCO_FB_DIV2_MASK 0x20000000
-#define BCHP_CLKGEN_PLL_SC1_PLL_MISC_VCO_FB_DIV2_SHIFT 29
-#define BCHP_CLKGEN_PLL_SC1_PLL_MISC_VCO_FB_DIV2_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_SC1_PLL_MISC :: STAT_UPDATE [28:28] */
-#define BCHP_CLKGEN_PLL_SC1_PLL_MISC_STAT_UPDATE_MASK 0x10000000
-#define BCHP_CLKGEN_PLL_SC1_PLL_MISC_STAT_UPDATE_SHIFT 28
-#define BCHP_CLKGEN_PLL_SC1_PLL_MISC_STAT_UPDATE_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_SC1_PLL_MISC :: STAT_SELECT [27:25] */
-#define BCHP_CLKGEN_PLL_SC1_PLL_MISC_STAT_SELECT_MASK 0x0e000000
-#define BCHP_CLKGEN_PLL_SC1_PLL_MISC_STAT_SELECT_SHIFT 25
-#define BCHP_CLKGEN_PLL_SC1_PLL_MISC_STAT_SELECT_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_SC1_PLL_MISC :: STAT_RESET [24:24] */
-#define BCHP_CLKGEN_PLL_SC1_PLL_MISC_STAT_RESET_MASK 0x01000000
-#define BCHP_CLKGEN_PLL_SC1_PLL_MISC_STAT_RESET_SHIFT 24
-#define BCHP_CLKGEN_PLL_SC1_PLL_MISC_STAT_RESET_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_SC1_PLL_MISC :: STAT_MODE [23:22] */
-#define BCHP_CLKGEN_PLL_SC1_PLL_MISC_STAT_MODE_MASK 0x00c00000
-#define BCHP_CLKGEN_PLL_SC1_PLL_MISC_STAT_MODE_SHIFT 22
-#define BCHP_CLKGEN_PLL_SC1_PLL_MISC_STAT_MODE_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_SC1_PLL_MISC :: PWM_RATE [21:20] */
-#define BCHP_CLKGEN_PLL_SC1_PLL_MISC_PWM_RATE_MASK 0x00300000
-#define BCHP_CLKGEN_PLL_SC1_PLL_MISC_PWM_RATE_SHIFT 20
-#define BCHP_CLKGEN_PLL_SC1_PLL_MISC_PWM_RATE_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_SC1_PLL_MISC :: POST_CTRL_RESETB [19:18] */
-#define BCHP_CLKGEN_PLL_SC1_PLL_MISC_POST_CTRL_RESETB_MASK 0x000c0000
-#define BCHP_CLKGEN_PLL_SC1_PLL_MISC_POST_CTRL_RESETB_SHIFT 18
-#define BCHP_CLKGEN_PLL_SC1_PLL_MISC_POST_CTRL_RESETB_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_SC1_PLL_MISC :: PLLRESERVED2 [17:16] */
-#define BCHP_CLKGEN_PLL_SC1_PLL_MISC_PLLRESERVED2_MASK 0x00030000
-#define BCHP_CLKGEN_PLL_SC1_PLL_MISC_PLLRESERVED2_SHIFT 16
-#define BCHP_CLKGEN_PLL_SC1_PLL_MISC_PLLRESERVED2_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_SC1_PLL_MISC :: PLLRESERVED1 [15:15] */
-#define BCHP_CLKGEN_PLL_SC1_PLL_MISC_PLLRESERVED1_MASK 0x00008000
-#define BCHP_CLKGEN_PLL_SC1_PLL_MISC_PLLRESERVED1_SHIFT 15
-#define BCHP_CLKGEN_PLL_SC1_PLL_MISC_PLLRESERVED1_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_SC1_PLL_MISC :: NDIV_RELOCK [14:14] */
-#define BCHP_CLKGEN_PLL_SC1_PLL_MISC_NDIV_RELOCK_MASK 0x00004000
-#define BCHP_CLKGEN_PLL_SC1_PLL_MISC_NDIV_RELOCK_SHIFT 14
-#define BCHP_CLKGEN_PLL_SC1_PLL_MISC_NDIV_RELOCK_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_SC1_PLL_MISC :: FAST_LOCK [13:13] */
-#define BCHP_CLKGEN_PLL_SC1_PLL_MISC_FAST_LOCK_MASK 0x00002000
-#define BCHP_CLKGEN_PLL_SC1_PLL_MISC_FAST_LOCK_SHIFT 13
-#define BCHP_CLKGEN_PLL_SC1_PLL_MISC_FAST_LOCK_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_SC1_PLL_MISC :: DCO_CTRL_BYPASS_ENABLE [12:12] */
-#define BCHP_CLKGEN_PLL_SC1_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_MASK 0x00001000
-#define BCHP_CLKGEN_PLL_SC1_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_SHIFT 12
-#define BCHP_CLKGEN_PLL_SC1_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_SC1_PLL_MISC :: DCO_CTRL_BYPASS [11:00] */
-#define BCHP_CLKGEN_PLL_SC1_PLL_MISC_DCO_CTRL_BYPASS_MASK 0x00000fff
-#define BCHP_CLKGEN_PLL_SC1_PLL_MISC_DCO_CTRL_BYPASS_SHIFT 0
-#define BCHP_CLKGEN_PLL_SC1_PLL_MISC_DCO_CTRL_BYPASS_DEFAULT 0x00000000
-
-/***************************************************************************
- *PLL_SC1_PLL_MISC2 - Mscellaneous control bus continued.
- ***************************************************************************/
-/* CLKGEN :: PLL_SC1_PLL_MISC2 :: PLLRESERVED0 [31:00] */
-#define BCHP_CLKGEN_PLL_SC1_PLL_MISC2_PLLRESERVED0_MASK 0xffffffff
-#define BCHP_CLKGEN_PLL_SC1_PLL_MISC2_PLLRESERVED0_SHIFT 0
-#define BCHP_CLKGEN_PLL_SC1_PLL_MISC2_PLLRESERVED0_DEFAULT 0x00000000
-
-/***************************************************************************
- *PLL_SC1_PLL_PWRON - Poweron
- ***************************************************************************/
-/* CLKGEN :: PLL_SC1_PLL_PWRON :: reserved0 [31:01] */
-#define BCHP_CLKGEN_PLL_SC1_PLL_PWRON_reserved0_MASK 0xfffffffe
-#define BCHP_CLKGEN_PLL_SC1_PLL_PWRON_reserved0_SHIFT 1
-
-/* CLKGEN :: PLL_SC1_PLL_PWRON :: PWRON_PLL [00:00] */
-#define BCHP_CLKGEN_PLL_SC1_PLL_PWRON_PWRON_PLL_MASK 0x00000001
-#define BCHP_CLKGEN_PLL_SC1_PLL_PWRON_PWRON_PLL_SHIFT 0
-#define BCHP_CLKGEN_PLL_SC1_PLL_PWRON_PWRON_PLL_DEFAULT 0x00000001
-
-/***************************************************************************
- *PLL_SC1_PLL_RESET - Resets
- ***************************************************************************/
-/* CLKGEN :: PLL_SC1_PLL_RESET :: reserved0 [31:02] */
-#define BCHP_CLKGEN_PLL_SC1_PLL_RESET_reserved0_MASK 0xfffffffc
-#define BCHP_CLKGEN_PLL_SC1_PLL_RESET_reserved0_SHIFT 2
-
-/* CLKGEN :: PLL_SC1_PLL_RESET :: RESETD [01:01] */
-#define BCHP_CLKGEN_PLL_SC1_PLL_RESET_RESETD_MASK 0x00000002
-#define BCHP_CLKGEN_PLL_SC1_PLL_RESET_RESETD_SHIFT 1
-#define BCHP_CLKGEN_PLL_SC1_PLL_RESET_RESETD_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_SC1_PLL_RESET :: RESETA [00:00] */
-#define BCHP_CLKGEN_PLL_SC1_PLL_RESET_RESETA_MASK 0x00000001
-#define BCHP_CLKGEN_PLL_SC1_PLL_RESET_RESETA_SHIFT 0
-#define BCHP_CLKGEN_PLL_SC1_PLL_RESET_RESETA_DEFAULT 0x00000000
-
-/***************************************************************************
- *PLL_SC1_PLL_SSC_MODE_CONTROL_HIGH - Higher bits of Spread Spectrum mode control
- ***************************************************************************/
-/* CLKGEN :: PLL_SC1_PLL_SSC_MODE_CONTROL_HIGH :: reserved0 [31:16] */
-#define BCHP_CLKGEN_PLL_SC1_PLL_SSC_MODE_CONTROL_HIGH_reserved0_MASK 0xffff0000
-#define BCHP_CLKGEN_PLL_SC1_PLL_SSC_MODE_CONTROL_HIGH_reserved0_SHIFT 16
-
-/* CLKGEN :: PLL_SC1_PLL_SSC_MODE_CONTROL_HIGH :: SSC_STEP [15:00] */
-#define BCHP_CLKGEN_PLL_SC1_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_MASK 0x0000ffff
-#define BCHP_CLKGEN_PLL_SC1_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_SHIFT 0
-#define BCHP_CLKGEN_PLL_SC1_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *PLL_SC1_PLL_SSC_MODE_CONTROL_LOW - Lower bits of Spread Spectrum mode control
- ***************************************************************************/
-/* CLKGEN :: PLL_SC1_PLL_SSC_MODE_CONTROL_LOW :: reserved0 [31:23] */
-#define BCHP_CLKGEN_PLL_SC1_PLL_SSC_MODE_CONTROL_LOW_reserved0_MASK 0xff800000
-#define BCHP_CLKGEN_PLL_SC1_PLL_SSC_MODE_CONTROL_LOW_reserved0_SHIFT 23
-
-/* CLKGEN :: PLL_SC1_PLL_SSC_MODE_CONTROL_LOW :: SSC_MODE [22:22] */
-#define BCHP_CLKGEN_PLL_SC1_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_MASK 0x00400000
-#define BCHP_CLKGEN_PLL_SC1_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_SHIFT 22
-#define BCHP_CLKGEN_PLL_SC1_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_SC1_PLL_SSC_MODE_CONTROL_LOW :: SSC_LIMIT [21:00] */
-#define BCHP_CLKGEN_PLL_SC1_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_MASK 0x003fffff
-#define BCHP_CLKGEN_PLL_SC1_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_SHIFT 0
-#define BCHP_CLKGEN_PLL_SC1_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_DEFAULT 0x00000000
-
-/***************************************************************************
- *PLL_SC1_PLL_STATUS - Status
- ***************************************************************************/
-/* CLKGEN :: PLL_SC1_PLL_STATUS :: reserved0 [31:12] */
-#define BCHP_CLKGEN_PLL_SC1_PLL_STATUS_reserved0_MASK 0xfffff000
-#define BCHP_CLKGEN_PLL_SC1_PLL_STATUS_reserved0_SHIFT 12
-
-/* CLKGEN :: PLL_SC1_PLL_STATUS :: TEST_STATUS [11:00] */
-#define BCHP_CLKGEN_PLL_SC1_PLL_STATUS_TEST_STATUS_MASK 0x00000fff
-#define BCHP_CLKGEN_PLL_SC1_PLL_STATUS_TEST_STATUS_SHIFT 0
-
-/***************************************************************************
- *PLL_SYS0_PLL_BG_PWRON - Bandgap Power on
- ***************************************************************************/
-/* CLKGEN :: PLL_SYS0_PLL_BG_PWRON :: reserved0 [31:01] */
-#define BCHP_CLKGEN_PLL_SYS0_PLL_BG_PWRON_reserved0_MASK 0xfffffffe
-#define BCHP_CLKGEN_PLL_SYS0_PLL_BG_PWRON_reserved0_SHIFT 1
-
-/* CLKGEN :: PLL_SYS0_PLL_BG_PWRON :: BG_PWRON_PLL [00:00] */
-#define BCHP_CLKGEN_PLL_SYS0_PLL_BG_PWRON_BG_PWRON_PLL_MASK 0x00000001
-#define BCHP_CLKGEN_PLL_SYS0_PLL_BG_PWRON_BG_PWRON_PLL_SHIFT 0
-#define BCHP_CLKGEN_PLL_SYS0_PLL_BG_PWRON_BG_PWRON_PLL_DEFAULT 0x00000001
-
-/***************************************************************************
- *PLL_SYS0_PLL_CHANNEL_CTRL_CH_0 - PLL CHANNEL control CH 0
- ***************************************************************************/
-/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_0 :: reserved0 [31:11] */
-#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_0_reserved0_MASK 0xfffff800
-#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_0_reserved0_SHIFT 11
-
-/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_0 :: POST_DIVIDER_HOLD_CH0 [10:10] */
-#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_MASK 0x00000400
-#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_SHIFT 10
-#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_0 :: PHASE_OFFSET_CH0 [09:09] */
-#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_MASK 0x00000200
-#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_SHIFT 9
-#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_0 :: MDIV_CH0 [08:01] */
-#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_MASK 0x000001fe
-#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_SHIFT 1
-#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_DEFAULT 0x00000012
-
-/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_0 :: CLOCK_DIS_CH0 [00:00] */
-#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_MASK 0x00000001
-#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_SHIFT 0
-#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_DEFAULT 0x00000000
-
-/***************************************************************************
- *PLL_SYS0_PLL_CHANNEL_CTRL_CH_1 - PLL CHANNEL control CH 1
- ***************************************************************************/
-/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_1 :: reserved0 [31:11] */
-#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_1_reserved0_MASK 0xfffff800
-#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_1_reserved0_SHIFT 11
-
-/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_1 :: POST_DIVIDER_HOLD_CH1 [10:10] */
-#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_MASK 0x00000400
-#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_SHIFT 10
-#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_1 :: PHASE_OFFSET_CH1 [09:09] */
-#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_MASK 0x00000200
-#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_SHIFT 9
-#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_1 :: MDIV_CH1 [08:01] */
-#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_MASK 0x000001fe
-#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_SHIFT 1
-#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_DEFAULT 0x0000000c
-
-/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_1 :: CLOCK_DIS_CH1 [00:00] */
-#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_MASK 0x00000001
-#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_SHIFT 0
-#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_DEFAULT 0x00000000
-
-/***************************************************************************
- *PLL_SYS0_PLL_CHANNEL_CTRL_CH_2 - PLL CHANNEL control CH 2
- ***************************************************************************/
-/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_2 :: reserved0 [31:11] */
-#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2_reserved0_MASK 0xfffff800
-#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2_reserved0_SHIFT 11
-
-/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_2 :: POST_DIVIDER_HOLD_CH2 [10:10] */
-#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_HOLD_CH2_MASK 0x00000400
-#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_HOLD_CH2_SHIFT 10
-#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_HOLD_CH2_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_2 :: PHASE_OFFSET_CH2 [09:09] */
-#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2_PHASE_OFFSET_CH2_MASK 0x00000200
-#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2_PHASE_OFFSET_CH2_SHIFT 9
-#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2_PHASE_OFFSET_CH2_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_2 :: MDIV_CH2 [08:01] */
-#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2_MDIV_CH2_MASK 0x000001fe
-#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2_MDIV_CH2_SHIFT 1
-#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2_MDIV_CH2_DEFAULT 0x0000000c
-
-/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_2 :: CLOCK_DIS_CH2 [00:00] */
-#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2_CLOCK_DIS_CH2_MASK 0x00000001
-#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2_CLOCK_DIS_CH2_SHIFT 0
-#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2_CLOCK_DIS_CH2_DEFAULT 0x00000000
-
-/***************************************************************************
- *PLL_SYS0_PLL_CHANNEL_CTRL_CH_3 - PLL CHANNEL control CH 3
- ***************************************************************************/
-/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_3 :: reserved0 [31:11] */
-#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3_reserved0_MASK 0xfffff800
-#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3_reserved0_SHIFT 11
-
-/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_3 :: POST_DIVIDER_HOLD_CH3 [10:10] */
-#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_HOLD_CH3_MASK 0x00000400
-#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_HOLD_CH3_SHIFT 10
-#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_HOLD_CH3_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_3 :: PHASE_OFFSET_CH3 [09:09] */
-#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3_PHASE_OFFSET_CH3_MASK 0x00000200
-#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3_PHASE_OFFSET_CH3_SHIFT 9
-#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3_PHASE_OFFSET_CH3_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_3 :: MDIV_CH3 [08:01] */
-#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3_MDIV_CH3_MASK 0x000001fe
-#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3_MDIV_CH3_SHIFT 1
-#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3_MDIV_CH3_DEFAULT 0x0000000c
-
-/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_3 :: CLOCK_DIS_CH3 [00:00] */
-#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3_CLOCK_DIS_CH3_MASK 0x00000001
-#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3_CLOCK_DIS_CH3_SHIFT 0
-#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3_CLOCK_DIS_CH3_DEFAULT 0x00000000
-
-/***************************************************************************
- *PLL_SYS0_PLL_CHANNEL_CTRL_CH_4 - PLL CHANNEL control CH 4
- ***************************************************************************/
-/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_4 :: reserved0 [31:11] */
-#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_4_reserved0_MASK 0xfffff800
-#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_4_reserved0_SHIFT 11
-
-/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_4 :: POST_DIVIDER_HOLD_CH4 [10:10] */
-#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_4_POST_DIVIDER_HOLD_CH4_MASK 0x00000400
-#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_4_POST_DIVIDER_HOLD_CH4_SHIFT 10
-#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_4_POST_DIVIDER_HOLD_CH4_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_4 :: PHASE_OFFSET_CH4 [09:09] */
-#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_4_PHASE_OFFSET_CH4_MASK 0x00000200
-#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_4_PHASE_OFFSET_CH4_SHIFT 9
-#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_4_PHASE_OFFSET_CH4_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_4 :: MDIV_CH4 [08:01] */
-#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_4_MDIV_CH4_MASK 0x000001fe
-#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_4_MDIV_CH4_SHIFT 1
-#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_4_MDIV_CH4_DEFAULT 0x00000006
-
-/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_4 :: CLOCK_DIS_CH4 [00:00] */
-#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_4_CLOCK_DIS_CH4_MASK 0x00000001
-#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_4_CLOCK_DIS_CH4_SHIFT 0
-#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_4_CLOCK_DIS_CH4_DEFAULT 0x00000000
-
-/***************************************************************************
- *PLL_SYS0_PLL_CHANNEL_CTRL_CH_5 - PLL CHANNEL control CH 5
- ***************************************************************************/
-/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_5 :: reserved0 [31:11] */
-#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_5_reserved0_MASK 0xfffff800
-#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_5_reserved0_SHIFT 11
-
-/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_5 :: POST_DIVIDER_HOLD_CH5 [10:10] */
-#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_5_POST_DIVIDER_HOLD_CH5_MASK 0x00000400
-#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_5_POST_DIVIDER_HOLD_CH5_SHIFT 10
-#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_5_POST_DIVIDER_HOLD_CH5_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_5 :: PHASE_OFFSET_CH5 [09:09] */
-#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_5_PHASE_OFFSET_CH5_MASK 0x00000200
-#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_5_PHASE_OFFSET_CH5_SHIFT 9
-#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_5_PHASE_OFFSET_CH5_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_5 :: MDIV_CH5 [08:01] */
-#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_5_MDIV_CH5_MASK 0x000001fe
-#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_5_MDIV_CH5_SHIFT 1
-#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_5_MDIV_CH5_DEFAULT 0x00000006
-
-/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_5 :: CLOCK_DIS_CH5 [00:00] */
-#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_5_CLOCK_DIS_CH5_MASK 0x00000001
-#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_5_CLOCK_DIS_CH5_SHIFT 0
-#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_5_CLOCK_DIS_CH5_DEFAULT 0x00000000
-
-/***************************************************************************
- *PLL_SYS0_PLL_DIV - Pre multiplier
- ***************************************************************************/
-/* CLKGEN :: PLL_SYS0_PLL_DIV :: reserved0 [31:14] */
-#define BCHP_CLKGEN_PLL_SYS0_PLL_DIV_reserved0_MASK 0xffffc000
-#define BCHP_CLKGEN_PLL_SYS0_PLL_DIV_reserved0_SHIFT 14
-
-/* CLKGEN :: PLL_SYS0_PLL_DIV :: PDIV [13:10] */
-#define BCHP_CLKGEN_PLL_SYS0_PLL_DIV_PDIV_MASK 0x00003c00
-#define BCHP_CLKGEN_PLL_SYS0_PLL_DIV_PDIV_SHIFT 10
-#define BCHP_CLKGEN_PLL_SYS0_PLL_DIV_PDIV_DEFAULT 0x00000002
-
-/* CLKGEN :: PLL_SYS0_PLL_DIV :: NDIV_INT [09:00] */
-#define BCHP_CLKGEN_PLL_SYS0_PLL_DIV_NDIV_INT_MASK 0x000003ff
-#define BCHP_CLKGEN_PLL_SYS0_PLL_DIV_NDIV_INT_SHIFT 0
-#define BCHP_CLKGEN_PLL_SYS0_PLL_DIV_NDIV_INT_DEFAULT 0x00000090
-
-/***************************************************************************
- *PLL_SYS0_PLL_GAIN - PLL GAIN
- ***************************************************************************/
-/* CLKGEN :: PLL_SYS0_PLL_GAIN :: reserved0 [31:10] */
-#define BCHP_CLKGEN_PLL_SYS0_PLL_GAIN_reserved0_MASK 0xfffffc00
-#define BCHP_CLKGEN_PLL_SYS0_PLL_GAIN_reserved0_SHIFT 10
-
-/* CLKGEN :: PLL_SYS0_PLL_GAIN :: LOOP_GAIN_PROPORTIONAL_IN_PHASE [09:06] */
-#define BCHP_CLKGEN_PLL_SYS0_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_MASK 0x000003c0
-#define BCHP_CLKGEN_PLL_SYS0_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_SHIFT 6
-#define BCHP_CLKGEN_PLL_SYS0_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_DEFAULT 0x00000007
-
-/* CLKGEN :: PLL_SYS0_PLL_GAIN :: LOOP_GAIN_IN_FREQ [05:03] */
-#define BCHP_CLKGEN_PLL_SYS0_PLL_GAIN_LOOP_GAIN_IN_FREQ_MASK 0x00000038
-#define BCHP_CLKGEN_PLL_SYS0_PLL_GAIN_LOOP_GAIN_IN_FREQ_SHIFT 3
-#define BCHP_CLKGEN_PLL_SYS0_PLL_GAIN_LOOP_GAIN_IN_FREQ_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_SYS0_PLL_GAIN :: LOOP_GAIN_INTEGRATOR_IN_PHASE [02:00] */
-#define BCHP_CLKGEN_PLL_SYS0_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_MASK 0x00000007
-#define BCHP_CLKGEN_PLL_SYS0_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_SHIFT 0
-#define BCHP_CLKGEN_PLL_SYS0_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_DEFAULT 0x00000003
-
-/***************************************************************************
- *PLL_SYS0_PLL_HOLD_CH_ALL - Hold PLL all channels
- ***************************************************************************/
-/* CLKGEN :: PLL_SYS0_PLL_HOLD_CH_ALL :: reserved0 [31:01] */
-#define BCHP_CLKGEN_PLL_SYS0_PLL_HOLD_CH_ALL_reserved0_MASK 0xfffffffe
-#define BCHP_CLKGEN_PLL_SYS0_PLL_HOLD_CH_ALL_reserved0_SHIFT 1
-
-/* CLKGEN :: PLL_SYS0_PLL_HOLD_CH_ALL :: HOLD_CH_ALL [00:00] */
-#define BCHP_CLKGEN_PLL_SYS0_PLL_HOLD_CH_ALL_HOLD_CH_ALL_MASK 0x00000001
-#define BCHP_CLKGEN_PLL_SYS0_PLL_HOLD_CH_ALL_HOLD_CH_ALL_SHIFT 0
-#define BCHP_CLKGEN_PLL_SYS0_PLL_HOLD_CH_ALL_HOLD_CH_ALL_DEFAULT 0x00000000
-
-/***************************************************************************
- *PLL_SYS0_PLL_LDO_CTRL - Ldo voltage control
- ***************************************************************************/
-/* CLKGEN :: PLL_SYS0_PLL_LDO_CTRL :: reserved0 [31:16] */
-#define BCHP_CLKGEN_PLL_SYS0_PLL_LDO_CTRL_reserved0_MASK 0xffff0000
-#define BCHP_CLKGEN_PLL_SYS0_PLL_LDO_CTRL_reserved0_SHIFT 16
-
-/* CLKGEN :: PLL_SYS0_PLL_LDO_CTRL :: LDO_CTRL [15:00] */
-#define BCHP_CLKGEN_PLL_SYS0_PLL_LDO_CTRL_LDO_CTRL_MASK 0x0000ffff
-#define BCHP_CLKGEN_PLL_SYS0_PLL_LDO_CTRL_LDO_CTRL_SHIFT 0
-#define BCHP_CLKGEN_PLL_SYS0_PLL_LDO_CTRL_LDO_CTRL_DEFAULT 0x00005005
-
-/***************************************************************************
- *PLL_SYS0_PLL_LDO_PWRON - LDO Power on
- ***************************************************************************/
-/* CLKGEN :: PLL_SYS0_PLL_LDO_PWRON :: reserved0 [31:01] */
-#define BCHP_CLKGEN_PLL_SYS0_PLL_LDO_PWRON_reserved0_MASK 0xfffffffe
-#define BCHP_CLKGEN_PLL_SYS0_PLL_LDO_PWRON_reserved0_SHIFT 1
-
-/* CLKGEN :: PLL_SYS0_PLL_LDO_PWRON :: LDO_PWRON_PLL [00:00] */
-#define BCHP_CLKGEN_PLL_SYS0_PLL_LDO_PWRON_LDO_PWRON_PLL_MASK 0x00000001
-#define BCHP_CLKGEN_PLL_SYS0_PLL_LDO_PWRON_LDO_PWRON_PLL_SHIFT 0
-#define BCHP_CLKGEN_PLL_SYS0_PLL_LDO_PWRON_LDO_PWRON_PLL_DEFAULT 0x00000001
-
-/***************************************************************************
- *PLL_SYS0_PLL_LOCK_STATUS - Lock Status
- ***************************************************************************/
-/* CLKGEN :: PLL_SYS0_PLL_LOCK_STATUS :: reserved0 [31:02] */
-#define BCHP_CLKGEN_PLL_SYS0_PLL_LOCK_STATUS_reserved0_MASK 0xfffffffc
-#define BCHP_CLKGEN_PLL_SYS0_PLL_LOCK_STATUS_reserved0_SHIFT 2
-
-/* CLKGEN :: PLL_SYS0_PLL_LOCK_STATUS :: LOCK_LOST [01:01] */
-#define BCHP_CLKGEN_PLL_SYS0_PLL_LOCK_STATUS_LOCK_LOST_MASK 0x00000002
-#define BCHP_CLKGEN_PLL_SYS0_PLL_LOCK_STATUS_LOCK_LOST_SHIFT 1
-
-/* CLKGEN :: PLL_SYS0_PLL_LOCK_STATUS :: LOCK [00:00] */
-#define BCHP_CLKGEN_PLL_SYS0_PLL_LOCK_STATUS_LOCK_MASK 0x00000001
-#define BCHP_CLKGEN_PLL_SYS0_PLL_LOCK_STATUS_LOCK_SHIFT 0
-
-/***************************************************************************
- *PLL_SYS0_PLL_MISC - Mscellaneous control bus.
- ***************************************************************************/
-/* CLKGEN :: PLL_SYS0_PLL_MISC :: VCO_RANGE_LOW [31:31] */
-#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_VCO_RANGE_LOW_MASK 0x80000000
-#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_VCO_RANGE_LOW_SHIFT 31
-#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_VCO_RANGE_LOW_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_SYS0_PLL_MISC :: VCO_RANGE_HIGH [30:30] */
-#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_VCO_RANGE_HIGH_MASK 0x40000000
-#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_VCO_RANGE_HIGH_SHIFT 30
-#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_VCO_RANGE_HIGH_DEFAULT 0x00000001
-
-/* CLKGEN :: PLL_SYS0_PLL_MISC :: VCO_DIV2 [29:29] */
-#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_VCO_DIV2_MASK 0x20000000
-#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_VCO_DIV2_SHIFT 29
-#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_VCO_DIV2_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_SYS0_PLL_MISC :: STAT_UPDATE [28:28] */
-#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_STAT_UPDATE_MASK 0x10000000
-#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_STAT_UPDATE_SHIFT 28
-#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_STAT_UPDATE_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_SYS0_PLL_MISC :: STAT_SELECT [27:25] */
-#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_STAT_SELECT_MASK 0x0e000000
-#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_STAT_SELECT_SHIFT 25
-#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_STAT_SELECT_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_SYS0_PLL_MISC :: STAT_RESET [24:24] */
-#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_STAT_RESET_MASK 0x01000000
-#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_STAT_RESET_SHIFT 24
-#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_STAT_RESET_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_SYS0_PLL_MISC :: STAT_MODE [23:22] */
-#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_STAT_MODE_MASK 0x00c00000
-#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_STAT_MODE_SHIFT 22
-#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_STAT_MODE_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_SYS0_PLL_MISC :: REF_ALT_OFFS [21:21] */
-#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_REF_ALT_OFFS_MASK 0x00200000
-#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_REF_ALT_OFFS_SHIFT 21
-#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_REF_ALT_OFFS_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_SYS0_PLL_MISC :: PWM_RATE [20:19] */
-#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_PWM_RATE_MASK 0x00180000
-#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_PWM_RATE_SHIFT 19
-#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_PWM_RATE_DEFAULT 0x00000001
-
-/* CLKGEN :: PLL_SYS0_PLL_MISC :: POST_CTRL_RESETB [18:17] */
-#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_POST_CTRL_RESETB_MASK 0x00060000
-#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_POST_CTRL_RESETB_SHIFT 17
-#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_POST_CTRL_RESETB_DEFAULT 0x00000003
-
-/* CLKGEN :: PLL_SYS0_PLL_MISC :: NDIV_RELOCK [16:16] */
-#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_NDIV_RELOCK_MASK 0x00010000
-#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_NDIV_RELOCK_SHIFT 16
-#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_NDIV_RELOCK_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_SYS0_PLL_MISC :: FAST_LOCK [15:15] */
-#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_FAST_LOCK_MASK 0x00008000
-#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_FAST_LOCK_SHIFT 15
-#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_FAST_LOCK_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_SYS0_PLL_MISC :: DITHER_DISABLE [14:14] */
-#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_DITHER_DISABLE_MASK 0x00004000
-#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_DITHER_DISABLE_SHIFT 14
-#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_DITHER_DISABLE_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_SYS0_PLL_MISC :: DCO_CTRL_BYPASS_ENABLE [13:13] */
-#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_MASK 0x00002000
-#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_SHIFT 13
-#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_SYS0_PLL_MISC :: DCO_CTRL_BYPASS [12:01] */
-#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_DCO_CTRL_BYPASS_MASK 0x00001ffe
-#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_DCO_CTRL_BYPASS_SHIFT 1
-#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_DCO_CTRL_BYPASS_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_SYS0_PLL_MISC :: AUX_CTRL [00:00] */
-#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_AUX_CTRL_MASK 0x00000001
-#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_AUX_CTRL_SHIFT 0
-#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_AUX_CTRL_DEFAULT 0x00000000
-
-/***************************************************************************
- *PLL_SYS0_PLL_MISC2 - Mscellaneous control bus continued.
- ***************************************************************************/
-/* CLKGEN :: PLL_SYS0_PLL_MISC2 :: PLLRESERVED0 [31:01] */
-#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC2_PLLRESERVED0_MASK 0xfffffffe
-#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC2_PLLRESERVED0_SHIFT 1
-#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC2_PLLRESERVED0_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_SYS0_PLL_MISC2 :: DIG_INPUT_SEL [00:00] */
-#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC2_DIG_INPUT_SEL_MASK 0x00000001
-#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC2_DIG_INPUT_SEL_SHIFT 0
-#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC2_DIG_INPUT_SEL_DEFAULT 0x00000000
-
-/***************************************************************************
- *PLL_SYS0_PLL_PWRON - Poweron
- ***************************************************************************/
-/* CLKGEN :: PLL_SYS0_PLL_PWRON :: reserved0 [31:01] */
-#define BCHP_CLKGEN_PLL_SYS0_PLL_PWRON_reserved0_MASK 0xfffffffe
-#define BCHP_CLKGEN_PLL_SYS0_PLL_PWRON_reserved0_SHIFT 1
-
-/* CLKGEN :: PLL_SYS0_PLL_PWRON :: PWRON_PLL [00:00] */
-#define BCHP_CLKGEN_PLL_SYS0_PLL_PWRON_PWRON_PLL_MASK 0x00000001
-#define BCHP_CLKGEN_PLL_SYS0_PLL_PWRON_PWRON_PLL_SHIFT 0
-#define BCHP_CLKGEN_PLL_SYS0_PLL_PWRON_PWRON_PLL_DEFAULT 0x00000001
-
-/***************************************************************************
- *PLL_SYS0_PLL_RESET - Resets
- ***************************************************************************/
-/* CLKGEN :: PLL_SYS0_PLL_RESET :: reserved0 [31:01] */
-#define BCHP_CLKGEN_PLL_SYS0_PLL_RESET_reserved0_MASK 0xfffffffe
-#define BCHP_CLKGEN_PLL_SYS0_PLL_RESET_reserved0_SHIFT 1
-
-/* CLKGEN :: PLL_SYS0_PLL_RESET :: RESETD [00:00] */
-#define BCHP_CLKGEN_PLL_SYS0_PLL_RESET_RESETD_MASK 0x00000001
-#define BCHP_CLKGEN_PLL_SYS0_PLL_RESET_RESETD_SHIFT 0
-#define BCHP_CLKGEN_PLL_SYS0_PLL_RESET_RESETD_DEFAULT 0x00000000
-
-/***************************************************************************
- *PLL_SYS0_PLL_SSC_MODE_CONTROL_HIGH - Higher bits of Spread Spectrum mode control
- ***************************************************************************/
-/* CLKGEN :: PLL_SYS0_PLL_SSC_MODE_CONTROL_HIGH :: reserved0 [31:16] */
-#define BCHP_CLKGEN_PLL_SYS0_PLL_SSC_MODE_CONTROL_HIGH_reserved0_MASK 0xffff0000
-#define BCHP_CLKGEN_PLL_SYS0_PLL_SSC_MODE_CONTROL_HIGH_reserved0_SHIFT 16
-
-/* CLKGEN :: PLL_SYS0_PLL_SSC_MODE_CONTROL_HIGH :: SSC_STEP [15:00] */
-#define BCHP_CLKGEN_PLL_SYS0_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_MASK 0x0000ffff
-#define BCHP_CLKGEN_PLL_SYS0_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_SHIFT 0
-#define BCHP_CLKGEN_PLL_SYS0_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *PLL_SYS0_PLL_SSC_MODE_CONTROL_LOW - Lower bits of Spread Spectrum mode control
- ***************************************************************************/
-/* CLKGEN :: PLL_SYS0_PLL_SSC_MODE_CONTROL_LOW :: reserved0 [31:23] */
-#define BCHP_CLKGEN_PLL_SYS0_PLL_SSC_MODE_CONTROL_LOW_reserved0_MASK 0xff800000
-#define BCHP_CLKGEN_PLL_SYS0_PLL_SSC_MODE_CONTROL_LOW_reserved0_SHIFT 23
-
-/* CLKGEN :: PLL_SYS0_PLL_SSC_MODE_CONTROL_LOW :: SSC_MODE [22:22] */
-#define BCHP_CLKGEN_PLL_SYS0_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_MASK 0x00400000
-#define BCHP_CLKGEN_PLL_SYS0_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_SHIFT 22
-#define BCHP_CLKGEN_PLL_SYS0_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_SYS0_PLL_SSC_MODE_CONTROL_LOW :: SSC_LIMIT [21:00] */
-#define BCHP_CLKGEN_PLL_SYS0_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_MASK 0x003fffff
-#define BCHP_CLKGEN_PLL_SYS0_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_SHIFT 0
-#define BCHP_CLKGEN_PLL_SYS0_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_DEFAULT 0x00000000
-
-/***************************************************************************
- *PLL_SYS0_PLL_STATUS - Status
- ***************************************************************************/
-/* CLKGEN :: PLL_SYS0_PLL_STATUS :: reserved0 [31:12] */
-#define BCHP_CLKGEN_PLL_SYS0_PLL_STATUS_reserved0_MASK 0xfffff000
-#define BCHP_CLKGEN_PLL_SYS0_PLL_STATUS_reserved0_SHIFT 12
-
-/* CLKGEN :: PLL_SYS0_PLL_STATUS :: TEST_STATUS [11:00] */
-#define BCHP_CLKGEN_PLL_SYS0_PLL_STATUS_TEST_STATUS_MASK 0x00000fff
-#define BCHP_CLKGEN_PLL_SYS0_PLL_STATUS_TEST_STATUS_SHIFT 0
-
-/***************************************************************************
- *PLL_VCXO0_PLL_BG_PWRON - Bandgap Power on
- ***************************************************************************/
-/* CLKGEN :: PLL_VCXO0_PLL_BG_PWRON :: reserved0 [31:01] */
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_BG_PWRON_reserved0_MASK 0xfffffffe
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_BG_PWRON_reserved0_SHIFT 1
-
-/* CLKGEN :: PLL_VCXO0_PLL_BG_PWRON :: BG_PWRON_PLL [00:00] */
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_BG_PWRON_BG_PWRON_PLL_MASK 0x00000001
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_BG_PWRON_BG_PWRON_PLL_SHIFT 0
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_BG_PWRON_BG_PWRON_PLL_DEFAULT 0x00000001
-
-/***************************************************************************
- *PLL_VCXO0_PLL_CHANNEL_CTRL_CH_0 - PLL CHANNEL control CH 0
- ***************************************************************************/
-/* CLKGEN :: PLL_VCXO0_PLL_CHANNEL_CTRL_CH_0 :: reserved0 [31:11] */
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_CHANNEL_CTRL_CH_0_reserved0_MASK 0xfffff800
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_CHANNEL_CTRL_CH_0_reserved0_SHIFT 11
-
-/* CLKGEN :: PLL_VCXO0_PLL_CHANNEL_CTRL_CH_0 :: POST_DIVIDER_HOLD_CH0 [10:10] */
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_MASK 0x00000400
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_SHIFT 10
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_VCXO0_PLL_CHANNEL_CTRL_CH_0 :: PHASE_OFFSET_CH0 [09:09] */
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_MASK 0x00000200
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_SHIFT 9
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_VCXO0_PLL_CHANNEL_CTRL_CH_0 :: MDIV_CH0 [08:01] */
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_MASK 0x000001fe
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_SHIFT 1
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_DEFAULT 0x00000040
-
-/* CLKGEN :: PLL_VCXO0_PLL_CHANNEL_CTRL_CH_0 :: CLOCK_DIS_CH0 [00:00] */
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_MASK 0x00000001
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_SHIFT 0
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_DEFAULT 0x00000000
-
-/***************************************************************************
- *PLL_VCXO0_PLL_CHANNEL_CTRL_CH_1 - PLL CHANNEL control CH 1
- ***************************************************************************/
-/* CLKGEN :: PLL_VCXO0_PLL_CHANNEL_CTRL_CH_1 :: reserved0 [31:11] */
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_CHANNEL_CTRL_CH_1_reserved0_MASK 0xfffff800
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_CHANNEL_CTRL_CH_1_reserved0_SHIFT 11
-
-/* CLKGEN :: PLL_VCXO0_PLL_CHANNEL_CTRL_CH_1 :: POST_DIVIDER_HOLD_CH1 [10:10] */
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_MASK 0x00000400
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_SHIFT 10
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_VCXO0_PLL_CHANNEL_CTRL_CH_1 :: PHASE_OFFSET_CH1 [09:09] */
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_MASK 0x00000200
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_SHIFT 9
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_VCXO0_PLL_CHANNEL_CTRL_CH_1 :: MDIV_CH1 [08:01] */
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_MASK 0x000001fe
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_SHIFT 1
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_DEFAULT 0x000000fa
-
-/* CLKGEN :: PLL_VCXO0_PLL_CHANNEL_CTRL_CH_1 :: CLOCK_DIS_CH1 [00:00] */
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_MASK 0x00000001
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_SHIFT 0
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_DEFAULT 0x00000000
-
-/***************************************************************************
- *PLL_VCXO0_PLL_CHANNEL_CTRL_CH_2 - PLL CHANNEL control CH 2
- ***************************************************************************/
-/* CLKGEN :: PLL_VCXO0_PLL_CHANNEL_CTRL_CH_2 :: reserved0 [31:11] */
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_CHANNEL_CTRL_CH_2_reserved0_MASK 0xfffff800
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_CHANNEL_CTRL_CH_2_reserved0_SHIFT 11
-
-/* CLKGEN :: PLL_VCXO0_PLL_CHANNEL_CTRL_CH_2 :: POST_DIVIDER_HOLD_CH2 [10:10] */
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_HOLD_CH2_MASK 0x00000400
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_HOLD_CH2_SHIFT 10
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_HOLD_CH2_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_VCXO0_PLL_CHANNEL_CTRL_CH_2 :: PHASE_OFFSET_CH2 [09:09] */
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_CHANNEL_CTRL_CH_2_PHASE_OFFSET_CH2_MASK 0x00000200
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_CHANNEL_CTRL_CH_2_PHASE_OFFSET_CH2_SHIFT 9
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_CHANNEL_CTRL_CH_2_PHASE_OFFSET_CH2_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_VCXO0_PLL_CHANNEL_CTRL_CH_2 :: MDIV_CH2 [08:01] */
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_CHANNEL_CTRL_CH_2_MDIV_CH2_MASK 0x000001fe
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_CHANNEL_CTRL_CH_2_MDIV_CH2_SHIFT 1
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_CHANNEL_CTRL_CH_2_MDIV_CH2_DEFAULT 0x0000007d
-
-/* CLKGEN :: PLL_VCXO0_PLL_CHANNEL_CTRL_CH_2 :: CLOCK_DIS_CH2 [00:00] */
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_CHANNEL_CTRL_CH_2_CLOCK_DIS_CH2_MASK 0x00000001
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_CHANNEL_CTRL_CH_2_CLOCK_DIS_CH2_SHIFT 0
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_CHANNEL_CTRL_CH_2_CLOCK_DIS_CH2_DEFAULT 0x00000000
-
-/***************************************************************************
- *PLL_VCXO0_PLL_DIV - Pre multiplier
- ***************************************************************************/
-/* CLKGEN :: PLL_VCXO0_PLL_DIV :: reserved0 [31:14] */
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_DIV_reserved0_MASK 0xffffc000
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_DIV_reserved0_SHIFT 14
-
-/* CLKGEN :: PLL_VCXO0_PLL_DIV :: PDIV [13:10] */
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_DIV_PDIV_MASK 0x00003c00
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_DIV_PDIV_SHIFT 10
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_DIV_PDIV_DEFAULT 0x00000002
-
-/* CLKGEN :: PLL_VCXO0_PLL_DIV :: NDIV_INT [09:00] */
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_DIV_NDIV_INT_MASK 0x000003ff
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_DIV_NDIV_INT_SHIFT 0
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_DIV_NDIV_INT_DEFAULT 0x00000040
-
-/***************************************************************************
- *PLL_VCXO0_PLL_FRAC - Fractional
- ***************************************************************************/
-/* CLKGEN :: PLL_VCXO0_PLL_FRAC :: reserved0 [31:20] */
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_FRAC_reserved0_MASK 0xfff00000
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_FRAC_reserved0_SHIFT 20
-
-/* CLKGEN :: PLL_VCXO0_PLL_FRAC :: FRAC_CONTROL [19:00] */
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_FRAC_FRAC_CONTROL_MASK 0x000fffff
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_FRAC_FRAC_CONTROL_SHIFT 0
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_FRAC_FRAC_CONTROL_DEFAULT 0x00000000
-
-/***************************************************************************
- *PLL_VCXO0_PLL_GAIN - PLL GAIN
- ***************************************************************************/
-/* CLKGEN :: PLL_VCXO0_PLL_GAIN :: reserved0 [31:10] */
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_GAIN_reserved0_MASK 0xfffffc00
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_GAIN_reserved0_SHIFT 10
-
-/* CLKGEN :: PLL_VCXO0_PLL_GAIN :: LOOP_GAIN_PROPORTIONAL_IN_PHASE [09:06] */
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_MASK 0x000003c0
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_SHIFT 6
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_DEFAULT 0x00000007
-
-/* CLKGEN :: PLL_VCXO0_PLL_GAIN :: LOOP_GAIN_IN_FREQ [05:03] */
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_GAIN_LOOP_GAIN_IN_FREQ_MASK 0x00000038
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_GAIN_LOOP_GAIN_IN_FREQ_SHIFT 3
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_GAIN_LOOP_GAIN_IN_FREQ_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_VCXO0_PLL_GAIN :: LOOP_GAIN_INTEGRATOR_IN_PHASE [02:00] */
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_MASK 0x00000007
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_SHIFT 0
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_DEFAULT 0x00000004
-
-/***************************************************************************
- *PLL_VCXO0_PLL_HOLD_CH_ALL - Hold PLL all channels
- ***************************************************************************/
-/* CLKGEN :: PLL_VCXO0_PLL_HOLD_CH_ALL :: reserved0 [31:01] */
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_HOLD_CH_ALL_reserved0_MASK 0xfffffffe
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_HOLD_CH_ALL_reserved0_SHIFT 1
-
-/* CLKGEN :: PLL_VCXO0_PLL_HOLD_CH_ALL :: HOLD_CH_ALL [00:00] */
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_HOLD_CH_ALL_HOLD_CH_ALL_MASK 0x00000001
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_HOLD_CH_ALL_HOLD_CH_ALL_SHIFT 0
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_HOLD_CH_ALL_HOLD_CH_ALL_DEFAULT 0x00000000
-
-/***************************************************************************
- *PLL_VCXO0_PLL_LDO_CTRL - Ldo voltage control
- ***************************************************************************/
-/* CLKGEN :: PLL_VCXO0_PLL_LDO_CTRL :: reserved0 [31:16] */
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_LDO_CTRL_reserved0_MASK 0xffff0000
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_LDO_CTRL_reserved0_SHIFT 16
-
-/* CLKGEN :: PLL_VCXO0_PLL_LDO_CTRL :: LDO_CTRL [15:00] */
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_LDO_CTRL_LDO_CTRL_MASK 0x0000ffff
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_LDO_CTRL_LDO_CTRL_SHIFT 0
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_LDO_CTRL_LDO_CTRL_DEFAULT 0x00005005
-
-/***************************************************************************
- *PLL_VCXO0_PLL_LDO_PWRON - LDO Power on
- ***************************************************************************/
-/* CLKGEN :: PLL_VCXO0_PLL_LDO_PWRON :: reserved0 [31:01] */
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_LDO_PWRON_reserved0_MASK 0xfffffffe
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_LDO_PWRON_reserved0_SHIFT 1
-
-/* CLKGEN :: PLL_VCXO0_PLL_LDO_PWRON :: LDO_PWRON_PLL [00:00] */
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_LDO_PWRON_LDO_PWRON_PLL_MASK 0x00000001
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_LDO_PWRON_LDO_PWRON_PLL_SHIFT 0
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_LDO_PWRON_LDO_PWRON_PLL_DEFAULT 0x00000001
-
-/***************************************************************************
- *PLL_VCXO0_PLL_LOCK_STATUS - Lock Status
- ***************************************************************************/
-/* CLKGEN :: PLL_VCXO0_PLL_LOCK_STATUS :: reserved0 [31:02] */
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_LOCK_STATUS_reserved0_MASK 0xfffffffc
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_LOCK_STATUS_reserved0_SHIFT 2
-
-/* CLKGEN :: PLL_VCXO0_PLL_LOCK_STATUS :: LOCK_LOST [01:01] */
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_LOCK_STATUS_LOCK_LOST_MASK 0x00000002
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_LOCK_STATUS_LOCK_LOST_SHIFT 1
-
-/* CLKGEN :: PLL_VCXO0_PLL_LOCK_STATUS :: LOCK [00:00] */
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_LOCK_STATUS_LOCK_MASK 0x00000001
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_LOCK_STATUS_LOCK_SHIFT 0
-
-/***************************************************************************
- *PLL_VCXO0_PLL_MISC - Mscellaneous control bus.
- ***************************************************************************/
-/* CLKGEN :: PLL_VCXO0_PLL_MISC :: VCO_RANGE_LOW [31:31] */
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_MISC_VCO_RANGE_LOW_MASK 0x80000000
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_MISC_VCO_RANGE_LOW_SHIFT 31
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_MISC_VCO_RANGE_LOW_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_VCXO0_PLL_MISC :: VCO_RANGE_HIGH [30:30] */
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_MISC_VCO_RANGE_HIGH_MASK 0x40000000
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_MISC_VCO_RANGE_HIGH_SHIFT 30
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_MISC_VCO_RANGE_HIGH_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_VCXO0_PLL_MISC :: VCO_DIV2 [29:29] */
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_MISC_VCO_DIV2_MASK 0x20000000
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_MISC_VCO_DIV2_SHIFT 29
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_MISC_VCO_DIV2_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_VCXO0_PLL_MISC :: STAT_UPDATE [28:28] */
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_MISC_STAT_UPDATE_MASK 0x10000000
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_MISC_STAT_UPDATE_SHIFT 28
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_MISC_STAT_UPDATE_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_VCXO0_PLL_MISC :: STAT_SELECT [27:25] */
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_MISC_STAT_SELECT_MASK 0x0e000000
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_MISC_STAT_SELECT_SHIFT 25
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_MISC_STAT_SELECT_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_VCXO0_PLL_MISC :: STAT_RESET [24:24] */
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_MISC_STAT_RESET_MASK 0x01000000
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_MISC_STAT_RESET_SHIFT 24
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_MISC_STAT_RESET_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_VCXO0_PLL_MISC :: STAT_MODE [23:22] */
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_MISC_STAT_MODE_MASK 0x00c00000
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_MISC_STAT_MODE_SHIFT 22
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_MISC_STAT_MODE_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_VCXO0_PLL_MISC :: REF_ALT_OFFS [21:21] */
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_MISC_REF_ALT_OFFS_MASK 0x00200000
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_MISC_REF_ALT_OFFS_SHIFT 21
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_MISC_REF_ALT_OFFS_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_VCXO0_PLL_MISC :: PWM_RATE [20:19] */
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_MISC_PWM_RATE_MASK 0x00180000
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_MISC_PWM_RATE_SHIFT 19
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_MISC_PWM_RATE_DEFAULT 0x00000003
-
-/* CLKGEN :: PLL_VCXO0_PLL_MISC :: POST_CTRL_RESETB [18:17] */
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_MISC_POST_CTRL_RESETB_MASK 0x00060000
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_MISC_POST_CTRL_RESETB_SHIFT 17
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_MISC_POST_CTRL_RESETB_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_VCXO0_PLL_MISC :: NDIV_RELOCK [16:16] */
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_MISC_NDIV_RELOCK_MASK 0x00010000
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_MISC_NDIV_RELOCK_SHIFT 16
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_MISC_NDIV_RELOCK_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_VCXO0_PLL_MISC :: FAST_LOCK [15:15] */
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_MISC_FAST_LOCK_MASK 0x00008000
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_MISC_FAST_LOCK_SHIFT 15
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_MISC_FAST_LOCK_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_VCXO0_PLL_MISC :: DITHER_DISABLE [14:14] */
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_MISC_DITHER_DISABLE_MASK 0x00004000
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_MISC_DITHER_DISABLE_SHIFT 14
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_MISC_DITHER_DISABLE_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_VCXO0_PLL_MISC :: DCO_CTRL_BYPASS_ENABLE [13:13] */
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_MASK 0x00002000
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_SHIFT 13
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_VCXO0_PLL_MISC :: DCO_CTRL_BYPASS [12:01] */
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_MISC_DCO_CTRL_BYPASS_MASK 0x00001ffe
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_MISC_DCO_CTRL_BYPASS_SHIFT 1
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_MISC_DCO_CTRL_BYPASS_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_VCXO0_PLL_MISC :: AUX_CTRL [00:00] */
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_MISC_AUX_CTRL_MASK 0x00000001
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_MISC_AUX_CTRL_SHIFT 0
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_MISC_AUX_CTRL_DEFAULT 0x00000000
-
-/***************************************************************************
- *PLL_VCXO0_PLL_MISC2 - Mscellaneous control bus continued.
- ***************************************************************************/
-/* CLKGEN :: PLL_VCXO0_PLL_MISC2 :: PLLRESERVED0 [31:01] */
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_MISC2_PLLRESERVED0_MASK 0xfffffffe
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_MISC2_PLLRESERVED0_SHIFT 1
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_MISC2_PLLRESERVED0_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_VCXO0_PLL_MISC2 :: DIG_INPUT_SEL [00:00] */
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_MISC2_DIG_INPUT_SEL_MASK 0x00000001
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_MISC2_DIG_INPUT_SEL_SHIFT 0
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_MISC2_DIG_INPUT_SEL_DEFAULT 0x00000000
-
-/***************************************************************************
- *PLL_VCXO0_PLL_PWRON - Poweron
- ***************************************************************************/
-/* CLKGEN :: PLL_VCXO0_PLL_PWRON :: reserved0 [31:01] */
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_PWRON_reserved0_MASK 0xfffffffe
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_PWRON_reserved0_SHIFT 1
-
-/* CLKGEN :: PLL_VCXO0_PLL_PWRON :: PWRON_PLL [00:00] */
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_PWRON_PWRON_PLL_MASK 0x00000001
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_PWRON_PWRON_PLL_SHIFT 0
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_PWRON_PWRON_PLL_DEFAULT 0x00000001
-
-/***************************************************************************
- *PLL_VCXO0_PLL_RESET - Resets
- ***************************************************************************/
-/* CLKGEN :: PLL_VCXO0_PLL_RESET :: reserved0 [31:02] */
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_RESET_reserved0_MASK 0xfffffffc
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_RESET_reserved0_SHIFT 2
-
-/* CLKGEN :: PLL_VCXO0_PLL_RESET :: RESETD [01:01] */
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_RESET_RESETD_MASK 0x00000002
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_RESET_RESETD_SHIFT 1
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_RESET_RESETD_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_VCXO0_PLL_RESET :: RESETA [00:00] */
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_RESET_RESETA_MASK 0x00000001
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_RESET_RESETA_SHIFT 0
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_RESET_RESETA_DEFAULT 0x00000000
-
-/***************************************************************************
- *PLL_VCXO0_PLL_SSC_MODE_CONTROL_HIGH - Higher bits of Spread Spectrum mode control
- ***************************************************************************/
-/* CLKGEN :: PLL_VCXO0_PLL_SSC_MODE_CONTROL_HIGH :: reserved0 [31:16] */
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_SSC_MODE_CONTROL_HIGH_reserved0_MASK 0xffff0000
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_SSC_MODE_CONTROL_HIGH_reserved0_SHIFT 16
-
-/* CLKGEN :: PLL_VCXO0_PLL_SSC_MODE_CONTROL_HIGH :: SSC_STEP [15:00] */
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_MASK 0x0000ffff
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_SHIFT 0
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *PLL_VCXO0_PLL_SSC_MODE_CONTROL_LOW - Lower bits of Spread Spectrum mode control
- ***************************************************************************/
-/* CLKGEN :: PLL_VCXO0_PLL_SSC_MODE_CONTROL_LOW :: reserved0 [31:23] */
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_SSC_MODE_CONTROL_LOW_reserved0_MASK 0xff800000
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_SSC_MODE_CONTROL_LOW_reserved0_SHIFT 23
-
-/* CLKGEN :: PLL_VCXO0_PLL_SSC_MODE_CONTROL_LOW :: SSC_MODE [22:22] */
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_MASK 0x00400000
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_SHIFT 22
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_VCXO0_PLL_SSC_MODE_CONTROL_LOW :: SSC_LIMIT [21:00] */
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_MASK 0x003fffff
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_SHIFT 0
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_DEFAULT 0x00000000
-
-/***************************************************************************
- *PLL_VCXO0_PLL_STATUS - Status
- ***************************************************************************/
-/* CLKGEN :: PLL_VCXO0_PLL_STATUS :: reserved0 [31:12] */
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_STATUS_reserved0_MASK 0xfffff000
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_STATUS_reserved0_SHIFT 12
-
-/* CLKGEN :: PLL_VCXO0_PLL_STATUS :: TEST_STATUS [11:00] */
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_STATUS_TEST_STATUS_MASK 0x00000fff
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_STATUS_TEST_STATUS_SHIFT 0
-
-/***************************************************************************
- *PLL_VCXO1_PLL_BG_PWRON - Bandgap Power on
- ***************************************************************************/
-/* CLKGEN :: PLL_VCXO1_PLL_BG_PWRON :: reserved0 [31:01] */
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_BG_PWRON_reserved0_MASK 0xfffffffe
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_BG_PWRON_reserved0_SHIFT 1
-
-/* CLKGEN :: PLL_VCXO1_PLL_BG_PWRON :: BG_PWRON_PLL [00:00] */
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_BG_PWRON_BG_PWRON_PLL_MASK 0x00000001
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_BG_PWRON_BG_PWRON_PLL_SHIFT 0
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_BG_PWRON_BG_PWRON_PLL_DEFAULT 0x00000001
-
-/***************************************************************************
- *PLL_VCXO1_PLL_CHANNEL_CTRL_CH_0 - PLL CHANNEL control CH 0
- ***************************************************************************/
-/* CLKGEN :: PLL_VCXO1_PLL_CHANNEL_CTRL_CH_0 :: reserved0 [31:11] */
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_CHANNEL_CTRL_CH_0_reserved0_MASK 0xfffff800
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_CHANNEL_CTRL_CH_0_reserved0_SHIFT 11
-
-/* CLKGEN :: PLL_VCXO1_PLL_CHANNEL_CTRL_CH_0 :: POST_DIVIDER_HOLD_CH0 [10:10] */
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_MASK 0x00000400
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_SHIFT 10
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_VCXO1_PLL_CHANNEL_CTRL_CH_0 :: PHASE_OFFSET_CH0 [09:09] */
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_MASK 0x00000200
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_SHIFT 9
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_VCXO1_PLL_CHANNEL_CTRL_CH_0 :: MDIV_CH0 [08:01] */
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_MASK 0x000001fe
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_SHIFT 1
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_DEFAULT 0x00000040
-
-/* CLKGEN :: PLL_VCXO1_PLL_CHANNEL_CTRL_CH_0 :: CLOCK_DIS_CH0 [00:00] */
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_MASK 0x00000001
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_SHIFT 0
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_DEFAULT 0x00000000
-
-/***************************************************************************
- *PLL_VCXO1_PLL_CHANNEL_CTRL_CH_1 - PLL CHANNEL control CH 1
- ***************************************************************************/
-/* CLKGEN :: PLL_VCXO1_PLL_CHANNEL_CTRL_CH_1 :: reserved0 [31:11] */
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_CHANNEL_CTRL_CH_1_reserved0_MASK 0xfffff800
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_CHANNEL_CTRL_CH_1_reserved0_SHIFT 11
-
-/* CLKGEN :: PLL_VCXO1_PLL_CHANNEL_CTRL_CH_1 :: POST_DIVIDER_HOLD_CH1 [10:10] */
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_MASK 0x00000400
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_SHIFT 10
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_VCXO1_PLL_CHANNEL_CTRL_CH_1 :: PHASE_OFFSET_CH1 [09:09] */
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_MASK 0x00000200
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_SHIFT 9
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_VCXO1_PLL_CHANNEL_CTRL_CH_1 :: MDIV_CH1 [08:01] */
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_MASK 0x000001fe
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_SHIFT 1
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_DEFAULT 0x000000fa
-
-/* CLKGEN :: PLL_VCXO1_PLL_CHANNEL_CTRL_CH_1 :: CLOCK_DIS_CH1 [00:00] */
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_MASK 0x00000001
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_SHIFT 0
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_DEFAULT 0x00000000
-
-/***************************************************************************
- *PLL_VCXO1_PLL_CHANNEL_CTRL_CH_2 - PLL CHANNEL control CH 2
- ***************************************************************************/
-/* CLKGEN :: PLL_VCXO1_PLL_CHANNEL_CTRL_CH_2 :: reserved0 [31:11] */
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_CHANNEL_CTRL_CH_2_reserved0_MASK 0xfffff800
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_CHANNEL_CTRL_CH_2_reserved0_SHIFT 11
-
-/* CLKGEN :: PLL_VCXO1_PLL_CHANNEL_CTRL_CH_2 :: POST_DIVIDER_HOLD_CH2 [10:10] */
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_HOLD_CH2_MASK 0x00000400
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_HOLD_CH2_SHIFT 10
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_HOLD_CH2_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_VCXO1_PLL_CHANNEL_CTRL_CH_2 :: PHASE_OFFSET_CH2 [09:09] */
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_CHANNEL_CTRL_CH_2_PHASE_OFFSET_CH2_MASK 0x00000200
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_CHANNEL_CTRL_CH_2_PHASE_OFFSET_CH2_SHIFT 9
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_CHANNEL_CTRL_CH_2_PHASE_OFFSET_CH2_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_VCXO1_PLL_CHANNEL_CTRL_CH_2 :: MDIV_CH2 [08:01] */
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_CHANNEL_CTRL_CH_2_MDIV_CH2_MASK 0x000001fe
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_CHANNEL_CTRL_CH_2_MDIV_CH2_SHIFT 1
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_CHANNEL_CTRL_CH_2_MDIV_CH2_DEFAULT 0x0000007d
-
-/* CLKGEN :: PLL_VCXO1_PLL_CHANNEL_CTRL_CH_2 :: CLOCK_DIS_CH2 [00:00] */
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_CHANNEL_CTRL_CH_2_CLOCK_DIS_CH2_MASK 0x00000001
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_CHANNEL_CTRL_CH_2_CLOCK_DIS_CH2_SHIFT 0
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_CHANNEL_CTRL_CH_2_CLOCK_DIS_CH2_DEFAULT 0x00000000
-
-/***************************************************************************
- *PLL_VCXO1_PLL_DIV - Pre multiplier
- ***************************************************************************/
-/* CLKGEN :: PLL_VCXO1_PLL_DIV :: reserved0 [31:14] */
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_DIV_reserved0_MASK 0xffffc000
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_DIV_reserved0_SHIFT 14
-
-/* CLKGEN :: PLL_VCXO1_PLL_DIV :: PDIV [13:10] */
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_DIV_PDIV_MASK 0x00003c00
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_DIV_PDIV_SHIFT 10
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_DIV_PDIV_DEFAULT 0x00000002
-
-/* CLKGEN :: PLL_VCXO1_PLL_DIV :: NDIV_INT [09:00] */
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_DIV_NDIV_INT_MASK 0x000003ff
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_DIV_NDIV_INT_SHIFT 0
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_DIV_NDIV_INT_DEFAULT 0x00000040
-
-/***************************************************************************
- *PLL_VCXO1_PLL_FRAC - Fractional
- ***************************************************************************/
-/* CLKGEN :: PLL_VCXO1_PLL_FRAC :: reserved0 [31:20] */
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_FRAC_reserved0_MASK 0xfff00000
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_FRAC_reserved0_SHIFT 20
-
-/* CLKGEN :: PLL_VCXO1_PLL_FRAC :: FRAC_CONTROL [19:00] */
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_FRAC_FRAC_CONTROL_MASK 0x000fffff
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_FRAC_FRAC_CONTROL_SHIFT 0
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_FRAC_FRAC_CONTROL_DEFAULT 0x00000000
-
-/***************************************************************************
- *PLL_VCXO1_PLL_GAIN - PLL GAIN
- ***************************************************************************/
-/* CLKGEN :: PLL_VCXO1_PLL_GAIN :: reserved0 [31:10] */
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_GAIN_reserved0_MASK 0xfffffc00
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_GAIN_reserved0_SHIFT 10
-
-/* CLKGEN :: PLL_VCXO1_PLL_GAIN :: LOOP_GAIN_PROPORTIONAL_IN_PHASE [09:06] */
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_MASK 0x000003c0
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_SHIFT 6
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_DEFAULT 0x00000007
-
-/* CLKGEN :: PLL_VCXO1_PLL_GAIN :: LOOP_GAIN_IN_FREQ [05:03] */
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_GAIN_LOOP_GAIN_IN_FREQ_MASK 0x00000038
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_GAIN_LOOP_GAIN_IN_FREQ_SHIFT 3
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_GAIN_LOOP_GAIN_IN_FREQ_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_VCXO1_PLL_GAIN :: LOOP_GAIN_INTEGRATOR_IN_PHASE [02:00] */
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_MASK 0x00000007
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_SHIFT 0
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_DEFAULT 0x00000004
-
-/***************************************************************************
- *PLL_VCXO1_PLL_HOLD_CH_ALL - Hold PLL all channels
- ***************************************************************************/
-/* CLKGEN :: PLL_VCXO1_PLL_HOLD_CH_ALL :: reserved0 [31:01] */
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_HOLD_CH_ALL_reserved0_MASK 0xfffffffe
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_HOLD_CH_ALL_reserved0_SHIFT 1
-
-/* CLKGEN :: PLL_VCXO1_PLL_HOLD_CH_ALL :: HOLD_CH_ALL [00:00] */
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_HOLD_CH_ALL_HOLD_CH_ALL_MASK 0x00000001
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_HOLD_CH_ALL_HOLD_CH_ALL_SHIFT 0
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_HOLD_CH_ALL_HOLD_CH_ALL_DEFAULT 0x00000000
-
-/***************************************************************************
- *PLL_VCXO1_PLL_LDO_CTRL - Ldo voltage control
- ***************************************************************************/
-/* CLKGEN :: PLL_VCXO1_PLL_LDO_CTRL :: reserved0 [31:16] */
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_LDO_CTRL_reserved0_MASK 0xffff0000
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_LDO_CTRL_reserved0_SHIFT 16
-
-/* CLKGEN :: PLL_VCXO1_PLL_LDO_CTRL :: LDO_CTRL [15:00] */
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_LDO_CTRL_LDO_CTRL_MASK 0x0000ffff
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_LDO_CTRL_LDO_CTRL_SHIFT 0
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_LDO_CTRL_LDO_CTRL_DEFAULT 0x00005005
-
-/***************************************************************************
- *PLL_VCXO1_PLL_LDO_PWRON - LDO Power on
- ***************************************************************************/
-/* CLKGEN :: PLL_VCXO1_PLL_LDO_PWRON :: reserved0 [31:01] */
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_LDO_PWRON_reserved0_MASK 0xfffffffe
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_LDO_PWRON_reserved0_SHIFT 1
-
-/* CLKGEN :: PLL_VCXO1_PLL_LDO_PWRON :: LDO_PWRON_PLL [00:00] */
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_LDO_PWRON_LDO_PWRON_PLL_MASK 0x00000001
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_LDO_PWRON_LDO_PWRON_PLL_SHIFT 0
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_LDO_PWRON_LDO_PWRON_PLL_DEFAULT 0x00000001
-
-/***************************************************************************
- *PLL_VCXO1_PLL_LOCK_STATUS - Lock Status
- ***************************************************************************/
-/* CLKGEN :: PLL_VCXO1_PLL_LOCK_STATUS :: reserved0 [31:02] */
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_LOCK_STATUS_reserved0_MASK 0xfffffffc
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_LOCK_STATUS_reserved0_SHIFT 2
-
-/* CLKGEN :: PLL_VCXO1_PLL_LOCK_STATUS :: LOCK_LOST [01:01] */
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_LOCK_STATUS_LOCK_LOST_MASK 0x00000002
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_LOCK_STATUS_LOCK_LOST_SHIFT 1
-
-/* CLKGEN :: PLL_VCXO1_PLL_LOCK_STATUS :: LOCK [00:00] */
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_LOCK_STATUS_LOCK_MASK 0x00000001
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_LOCK_STATUS_LOCK_SHIFT 0
-
-/***************************************************************************
- *PLL_VCXO1_PLL_MISC - Mscellaneous control bus.
- ***************************************************************************/
-/* CLKGEN :: PLL_VCXO1_PLL_MISC :: VCO_RANGE_LOW [31:31] */
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_MISC_VCO_RANGE_LOW_MASK 0x80000000
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_MISC_VCO_RANGE_LOW_SHIFT 31
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_MISC_VCO_RANGE_LOW_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_VCXO1_PLL_MISC :: VCO_RANGE_HIGH [30:30] */
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_MISC_VCO_RANGE_HIGH_MASK 0x40000000
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_MISC_VCO_RANGE_HIGH_SHIFT 30
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_MISC_VCO_RANGE_HIGH_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_VCXO1_PLL_MISC :: VCO_DIV2 [29:29] */
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_MISC_VCO_DIV2_MASK 0x20000000
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_MISC_VCO_DIV2_SHIFT 29
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_MISC_VCO_DIV2_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_VCXO1_PLL_MISC :: STAT_UPDATE [28:28] */
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_MISC_STAT_UPDATE_MASK 0x10000000
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_MISC_STAT_UPDATE_SHIFT 28
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_MISC_STAT_UPDATE_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_VCXO1_PLL_MISC :: STAT_SELECT [27:25] */
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_MISC_STAT_SELECT_MASK 0x0e000000
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_MISC_STAT_SELECT_SHIFT 25
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_MISC_STAT_SELECT_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_VCXO1_PLL_MISC :: STAT_RESET [24:24] */
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_MISC_STAT_RESET_MASK 0x01000000
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_MISC_STAT_RESET_SHIFT 24
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_MISC_STAT_RESET_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_VCXO1_PLL_MISC :: STAT_MODE [23:22] */
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_MISC_STAT_MODE_MASK 0x00c00000
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_MISC_STAT_MODE_SHIFT 22
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_MISC_STAT_MODE_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_VCXO1_PLL_MISC :: REF_ALT_OFFS [21:21] */
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_MISC_REF_ALT_OFFS_MASK 0x00200000
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_MISC_REF_ALT_OFFS_SHIFT 21
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_MISC_REF_ALT_OFFS_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_VCXO1_PLL_MISC :: PWM_RATE [20:19] */
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_MISC_PWM_RATE_MASK 0x00180000
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_MISC_PWM_RATE_SHIFT 19
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_MISC_PWM_RATE_DEFAULT 0x00000003
-
-/* CLKGEN :: PLL_VCXO1_PLL_MISC :: POST_CTRL_RESETB [18:17] */
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_MISC_POST_CTRL_RESETB_MASK 0x00060000
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_MISC_POST_CTRL_RESETB_SHIFT 17
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_MISC_POST_CTRL_RESETB_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_VCXO1_PLL_MISC :: NDIV_RELOCK [16:16] */
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_MISC_NDIV_RELOCK_MASK 0x00010000
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_MISC_NDIV_RELOCK_SHIFT 16
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_MISC_NDIV_RELOCK_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_VCXO1_PLL_MISC :: FAST_LOCK [15:15] */
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_MISC_FAST_LOCK_MASK 0x00008000
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_MISC_FAST_LOCK_SHIFT 15
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_MISC_FAST_LOCK_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_VCXO1_PLL_MISC :: DITHER_DISABLE [14:14] */
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_MISC_DITHER_DISABLE_MASK 0x00004000
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_MISC_DITHER_DISABLE_SHIFT 14
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_MISC_DITHER_DISABLE_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_VCXO1_PLL_MISC :: DCO_CTRL_BYPASS_ENABLE [13:13] */
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_MASK 0x00002000
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_SHIFT 13
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_VCXO1_PLL_MISC :: DCO_CTRL_BYPASS [12:01] */
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_MISC_DCO_CTRL_BYPASS_MASK 0x00001ffe
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_MISC_DCO_CTRL_BYPASS_SHIFT 1
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_MISC_DCO_CTRL_BYPASS_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_VCXO1_PLL_MISC :: AUX_CTRL [00:00] */
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_MISC_AUX_CTRL_MASK 0x00000001
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_MISC_AUX_CTRL_SHIFT 0
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_MISC_AUX_CTRL_DEFAULT 0x00000000
-
-/***************************************************************************
- *PLL_VCXO1_PLL_MISC2 - Mscellaneous control bus continued.
- ***************************************************************************/
-/* CLKGEN :: PLL_VCXO1_PLL_MISC2 :: PLLRESERVED0 [31:01] */
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_MISC2_PLLRESERVED0_MASK 0xfffffffe
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_MISC2_PLLRESERVED0_SHIFT 1
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_MISC2_PLLRESERVED0_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_VCXO1_PLL_MISC2 :: DIG_INPUT_SEL [00:00] */
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_MISC2_DIG_INPUT_SEL_MASK 0x00000001
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_MISC2_DIG_INPUT_SEL_SHIFT 0
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_MISC2_DIG_INPUT_SEL_DEFAULT 0x00000000
-
-/***************************************************************************
- *PLL_VCXO1_PLL_PWRON - Poweron
- ***************************************************************************/
-/* CLKGEN :: PLL_VCXO1_PLL_PWRON :: reserved0 [31:01] */
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_PWRON_reserved0_MASK 0xfffffffe
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_PWRON_reserved0_SHIFT 1
-
-/* CLKGEN :: PLL_VCXO1_PLL_PWRON :: PWRON_PLL [00:00] */
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_PWRON_PWRON_PLL_MASK 0x00000001
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_PWRON_PWRON_PLL_SHIFT 0
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_PWRON_PWRON_PLL_DEFAULT 0x00000001
-
-/***************************************************************************
- *PLL_VCXO1_PLL_RESET - Resets
- ***************************************************************************/
-/* CLKGEN :: PLL_VCXO1_PLL_RESET :: reserved0 [31:02] */
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_RESET_reserved0_MASK 0xfffffffc
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_RESET_reserved0_SHIFT 2
-
-/* CLKGEN :: PLL_VCXO1_PLL_RESET :: RESETD [01:01] */
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_RESET_RESETD_MASK 0x00000002
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_RESET_RESETD_SHIFT 1
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_RESET_RESETD_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_VCXO1_PLL_RESET :: RESETA [00:00] */
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_RESET_RESETA_MASK 0x00000001
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_RESET_RESETA_SHIFT 0
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_RESET_RESETA_DEFAULT 0x00000000
-
-/***************************************************************************
- *PLL_VCXO1_PLL_SSC_MODE_CONTROL_HIGH - Higher bits of Spread Spectrum mode control
- ***************************************************************************/
-/* CLKGEN :: PLL_VCXO1_PLL_SSC_MODE_CONTROL_HIGH :: reserved0 [31:16] */
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_SSC_MODE_CONTROL_HIGH_reserved0_MASK 0xffff0000
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_SSC_MODE_CONTROL_HIGH_reserved0_SHIFT 16
-
-/* CLKGEN :: PLL_VCXO1_PLL_SSC_MODE_CONTROL_HIGH :: SSC_STEP [15:00] */
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_MASK 0x0000ffff
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_SHIFT 0
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *PLL_VCXO1_PLL_SSC_MODE_CONTROL_LOW - Lower bits of Spread Spectrum mode control
- ***************************************************************************/
-/* CLKGEN :: PLL_VCXO1_PLL_SSC_MODE_CONTROL_LOW :: reserved0 [31:23] */
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_SSC_MODE_CONTROL_LOW_reserved0_MASK 0xff800000
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_SSC_MODE_CONTROL_LOW_reserved0_SHIFT 23
-
-/* CLKGEN :: PLL_VCXO1_PLL_SSC_MODE_CONTROL_LOW :: SSC_MODE [22:22] */
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_MASK 0x00400000
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_SHIFT 22
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_VCXO1_PLL_SSC_MODE_CONTROL_LOW :: SSC_LIMIT [21:00] */
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_MASK 0x003fffff
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_SHIFT 0
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_DEFAULT 0x00000000
-
-/***************************************************************************
- *PLL_VCXO1_PLL_STATUS - Status
- ***************************************************************************/
-/* CLKGEN :: PLL_VCXO1_PLL_STATUS :: reserved0 [31:12] */
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_STATUS_reserved0_MASK 0xfffff000
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_STATUS_reserved0_SHIFT 12
-
-/* CLKGEN :: PLL_VCXO1_PLL_STATUS :: TEST_STATUS [11:00] */
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_STATUS_TEST_STATUS_MASK 0x00000fff
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_STATUS_TEST_STATUS_SHIFT 0
-
-/***************************************************************************
- *PLL_XPT_PLL_CHANNEL_CTRL_CH_0 - PLL CHANNEL control CH 0
- ***************************************************************************/
-/* CLKGEN :: PLL_XPT_PLL_CHANNEL_CTRL_CH_0 :: reserved0 [31:11] */
-#define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_0_reserved0_MASK 0xfffff800
-#define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_0_reserved0_SHIFT 11
-
-/* CLKGEN :: PLL_XPT_PLL_CHANNEL_CTRL_CH_0 :: POST_DIVIDER_HOLD_CH0 [10:10] */
-#define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_MASK 0x00000400
-#define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_SHIFT 10
-#define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_XPT_PLL_CHANNEL_CTRL_CH_0 :: PHASE_OFFSET_CH0 [09:09] */
-#define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_MASK 0x00000200
-#define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_SHIFT 9
-#define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_XPT_PLL_CHANNEL_CTRL_CH_0 :: MDIV_CH0 [08:01] */
-#define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_MASK 0x000001fe
-#define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_SHIFT 1
-#define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_DEFAULT 0x00000008
-
-/* CLKGEN :: PLL_XPT_PLL_CHANNEL_CTRL_CH_0 :: CLOCK_DIS_CH0 [00:00] */
-#define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_MASK 0x00000001
-#define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_SHIFT 0
-#define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_DEFAULT 0x00000000
-
-/***************************************************************************
- *PLL_XPT_PLL_CHANNEL_CTRL_CH_1 - PLL CHANNEL control CH 1
- ***************************************************************************/
-/* CLKGEN :: PLL_XPT_PLL_CHANNEL_CTRL_CH_1 :: reserved0 [31:11] */
-#define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_1_reserved0_MASK 0xfffff800
-#define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_1_reserved0_SHIFT 11
-
-/* CLKGEN :: PLL_XPT_PLL_CHANNEL_CTRL_CH_1 :: POST_DIVIDER_HOLD_CH1 [10:10] */
-#define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_MASK 0x00000400
-#define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_SHIFT 10
-#define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_XPT_PLL_CHANNEL_CTRL_CH_1 :: PHASE_OFFSET_CH1 [09:09] */
-#define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_MASK 0x00000200
-#define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_SHIFT 9
-#define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_XPT_PLL_CHANNEL_CTRL_CH_1 :: MDIV_CH1 [08:01] */
-#define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_MASK 0x000001fe
-#define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_SHIFT 1
-#define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_DEFAULT 0x00000008
-
-/* CLKGEN :: PLL_XPT_PLL_CHANNEL_CTRL_CH_1 :: CLOCK_DIS_CH1 [00:00] */
-#define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_MASK 0x00000001
-#define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_SHIFT 0
-#define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_DEFAULT 0x00000000
-
-/***************************************************************************
- *PLL_XPT_PLL_CHANNEL_CTRL_CH_2 - PLL CHANNEL control CH 2
- ***************************************************************************/
-/* CLKGEN :: PLL_XPT_PLL_CHANNEL_CTRL_CH_2 :: reserved0 [31:11] */
-#define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_2_reserved0_MASK 0xfffff800
-#define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_2_reserved0_SHIFT 11
-
-/* CLKGEN :: PLL_XPT_PLL_CHANNEL_CTRL_CH_2 :: POST_DIVIDER_HOLD_CH2 [10:10] */
-#define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_HOLD_CH2_MASK 0x00000400
-#define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_HOLD_CH2_SHIFT 10
-#define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_HOLD_CH2_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_XPT_PLL_CHANNEL_CTRL_CH_2 :: PHASE_OFFSET_CH2 [09:09] */
-#define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_2_PHASE_OFFSET_CH2_MASK 0x00000200
-#define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_2_PHASE_OFFSET_CH2_SHIFT 9
-#define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_2_PHASE_OFFSET_CH2_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_XPT_PLL_CHANNEL_CTRL_CH_2 :: MDIV_CH2 [08:01] */
-#define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_2_MDIV_CH2_MASK 0x000001fe
-#define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_2_MDIV_CH2_SHIFT 1
-#define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_2_MDIV_CH2_DEFAULT 0x0000000f
-
-/* CLKGEN :: PLL_XPT_PLL_CHANNEL_CTRL_CH_2 :: CLOCK_DIS_CH2 [00:00] */
-#define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_2_CLOCK_DIS_CH2_MASK 0x00000001
-#define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_2_CLOCK_DIS_CH2_SHIFT 0
-#define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_2_CLOCK_DIS_CH2_DEFAULT 0x00000000
-
-/***************************************************************************
- *PLL_XPT_PLL_CHANNEL_CTRL_CH_3 - PLL CHANNEL control CH 3
- ***************************************************************************/
-/* CLKGEN :: PLL_XPT_PLL_CHANNEL_CTRL_CH_3 :: reserved0 [31:11] */
-#define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_3_reserved0_MASK 0xfffff800
-#define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_3_reserved0_SHIFT 11
-
-/* CLKGEN :: PLL_XPT_PLL_CHANNEL_CTRL_CH_3 :: POST_DIVIDER_HOLD_CH3 [10:10] */
-#define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_HOLD_CH3_MASK 0x00000400
-#define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_HOLD_CH3_SHIFT 10
-#define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_HOLD_CH3_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_XPT_PLL_CHANNEL_CTRL_CH_3 :: PHASE_OFFSET_CH3 [09:09] */
-#define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_3_PHASE_OFFSET_CH3_MASK 0x00000200
-#define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_3_PHASE_OFFSET_CH3_SHIFT 9
-#define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_3_PHASE_OFFSET_CH3_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_XPT_PLL_CHANNEL_CTRL_CH_3 :: MDIV_CH3 [08:01] */
-#define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_3_MDIV_CH3_MASK 0x000001fe
-#define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_3_MDIV_CH3_SHIFT 1
-#define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_3_MDIV_CH3_DEFAULT 0x0000000c
-
-/* CLKGEN :: PLL_XPT_PLL_CHANNEL_CTRL_CH_3 :: CLOCK_DIS_CH3 [00:00] */
-#define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_3_CLOCK_DIS_CH3_MASK 0x00000001
-#define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_3_CLOCK_DIS_CH3_SHIFT 0
-#define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_3_CLOCK_DIS_CH3_DEFAULT 0x00000000
-
-/***************************************************************************
- *PLL_XPT_PLL_CHANNEL_CTRL_CH_4 - PLL CHANNEL control CH 4
- ***************************************************************************/
-/* CLKGEN :: PLL_XPT_PLL_CHANNEL_CTRL_CH_4 :: reserved0 [31:11] */
-#define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_4_reserved0_MASK 0xfffff800
-#define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_4_reserved0_SHIFT 11
-
-/* CLKGEN :: PLL_XPT_PLL_CHANNEL_CTRL_CH_4 :: POST_DIVIDER_HOLD_CH4 [10:10] */
-#define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_4_POST_DIVIDER_HOLD_CH4_MASK 0x00000400
-#define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_4_POST_DIVIDER_HOLD_CH4_SHIFT 10
-#define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_4_POST_DIVIDER_HOLD_CH4_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_XPT_PLL_CHANNEL_CTRL_CH_4 :: PHASE_OFFSET_CH4 [09:09] */
-#define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_4_PHASE_OFFSET_CH4_MASK 0x00000200
-#define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_4_PHASE_OFFSET_CH4_SHIFT 9
-#define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_4_PHASE_OFFSET_CH4_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_XPT_PLL_CHANNEL_CTRL_CH_4 :: MDIV_CH4 [08:01] */
-#define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_4_MDIV_CH4_MASK 0x000001fe
-#define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_4_MDIV_CH4_SHIFT 1
-#define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_4_MDIV_CH4_DEFAULT 0x00000064
-
-/* CLKGEN :: PLL_XPT_PLL_CHANNEL_CTRL_CH_4 :: CLOCK_DIS_CH4 [00:00] */
-#define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_4_CLOCK_DIS_CH4_MASK 0x00000001
-#define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_4_CLOCK_DIS_CH4_SHIFT 0
-#define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_4_CLOCK_DIS_CH4_DEFAULT 0x00000001
-
-/***************************************************************************
- *PLL_XPT_PLL_DIV - Pre multiplier
- ***************************************************************************/
-/* CLKGEN :: PLL_XPT_PLL_DIV :: reserved0 [31:14] */
-#define BCHP_CLKGEN_PLL_XPT_PLL_DIV_reserved0_MASK 0xffffc000
-#define BCHP_CLKGEN_PLL_XPT_PLL_DIV_reserved0_SHIFT 14
-
-/* CLKGEN :: PLL_XPT_PLL_DIV :: PDIV [13:10] */
-#define BCHP_CLKGEN_PLL_XPT_PLL_DIV_PDIV_MASK 0x00003c00
-#define BCHP_CLKGEN_PLL_XPT_PLL_DIV_PDIV_SHIFT 10
-#define BCHP_CLKGEN_PLL_XPT_PLL_DIV_PDIV_DEFAULT 0x00000002
-
-/* CLKGEN :: PLL_XPT_PLL_DIV :: NDIV_INT [09:00] */
-#define BCHP_CLKGEN_PLL_XPT_PLL_DIV_NDIV_INT_MASK 0x000003ff
-#define BCHP_CLKGEN_PLL_XPT_PLL_DIV_NDIV_INT_SHIFT 0
-#define BCHP_CLKGEN_PLL_XPT_PLL_DIV_NDIV_INT_DEFAULT 0x00000078
-
-/***************************************************************************
- *PLL_XPT_PLL_GAIN - PLL GAIN
- ***************************************************************************/
-/* CLKGEN :: PLL_XPT_PLL_GAIN :: reserved0 [31:10] */
-#define BCHP_CLKGEN_PLL_XPT_PLL_GAIN_reserved0_MASK 0xfffffc00
-#define BCHP_CLKGEN_PLL_XPT_PLL_GAIN_reserved0_SHIFT 10
-
-/* CLKGEN :: PLL_XPT_PLL_GAIN :: LOOP_GAIN_PROPORTIONAL_IN_PHASE [09:06] */
-#define BCHP_CLKGEN_PLL_XPT_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_MASK 0x000003c0
-#define BCHP_CLKGEN_PLL_XPT_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_SHIFT 6
-#define BCHP_CLKGEN_PLL_XPT_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_DEFAULT 0x00000003
-
-/* CLKGEN :: PLL_XPT_PLL_GAIN :: LOOP_GAIN_IN_FREQ [05:03] */
-#define BCHP_CLKGEN_PLL_XPT_PLL_GAIN_LOOP_GAIN_IN_FREQ_MASK 0x00000038
-#define BCHP_CLKGEN_PLL_XPT_PLL_GAIN_LOOP_GAIN_IN_FREQ_SHIFT 3
-#define BCHP_CLKGEN_PLL_XPT_PLL_GAIN_LOOP_GAIN_IN_FREQ_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_XPT_PLL_GAIN :: LOOP_GAIN_INTEGRATOR_IN_PHASE [02:00] */
-#define BCHP_CLKGEN_PLL_XPT_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_MASK 0x00000007
-#define BCHP_CLKGEN_PLL_XPT_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_SHIFT 0
-#define BCHP_CLKGEN_PLL_XPT_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_DEFAULT 0x00000002
-
-/***************************************************************************
- *PLL_XPT_PLL_LDO_PWRON - LDO Power on
- ***************************************************************************/
-/* CLKGEN :: PLL_XPT_PLL_LDO_PWRON :: reserved0 [31:01] */
-#define BCHP_CLKGEN_PLL_XPT_PLL_LDO_PWRON_reserved0_MASK 0xfffffffe
-#define BCHP_CLKGEN_PLL_XPT_PLL_LDO_PWRON_reserved0_SHIFT 1
-
-/* CLKGEN :: PLL_XPT_PLL_LDO_PWRON :: LDO_PWRON_PLL [00:00] */
-#define BCHP_CLKGEN_PLL_XPT_PLL_LDO_PWRON_LDO_PWRON_PLL_MASK 0x00000001
-#define BCHP_CLKGEN_PLL_XPT_PLL_LDO_PWRON_LDO_PWRON_PLL_SHIFT 0
-#define BCHP_CLKGEN_PLL_XPT_PLL_LDO_PWRON_LDO_PWRON_PLL_DEFAULT 0x00000001
-
-/***************************************************************************
- *PLL_XPT_PLL_LOCK_STATUS - Lock Status
- ***************************************************************************/
-/* CLKGEN :: PLL_XPT_PLL_LOCK_STATUS :: reserved0 [31:02] */
-#define BCHP_CLKGEN_PLL_XPT_PLL_LOCK_STATUS_reserved0_MASK 0xfffffffc
-#define BCHP_CLKGEN_PLL_XPT_PLL_LOCK_STATUS_reserved0_SHIFT 2
-
-/* CLKGEN :: PLL_XPT_PLL_LOCK_STATUS :: LOCK_LOST [01:01] */
-#define BCHP_CLKGEN_PLL_XPT_PLL_LOCK_STATUS_LOCK_LOST_MASK 0x00000002
-#define BCHP_CLKGEN_PLL_XPT_PLL_LOCK_STATUS_LOCK_LOST_SHIFT 1
-
-/* CLKGEN :: PLL_XPT_PLL_LOCK_STATUS :: LOCK [00:00] */
-#define BCHP_CLKGEN_PLL_XPT_PLL_LOCK_STATUS_LOCK_MASK 0x00000001
-#define BCHP_CLKGEN_PLL_XPT_PLL_LOCK_STATUS_LOCK_SHIFT 0
-
-/***************************************************************************
- *PLL_XPT_PLL_MISC - Mscellaneous control bus.
- ***************************************************************************/
-/* CLKGEN :: PLL_XPT_PLL_MISC :: VCO_RANGE [31:30] */
-#define BCHP_CLKGEN_PLL_XPT_PLL_MISC_VCO_RANGE_MASK 0xc0000000
-#define BCHP_CLKGEN_PLL_XPT_PLL_MISC_VCO_RANGE_SHIFT 30
-#define BCHP_CLKGEN_PLL_XPT_PLL_MISC_VCO_RANGE_DEFAULT 0x00000002
-
-/* CLKGEN :: PLL_XPT_PLL_MISC :: VCO_FB_DIV2 [29:29] */
-#define BCHP_CLKGEN_PLL_XPT_PLL_MISC_VCO_FB_DIV2_MASK 0x20000000
-#define BCHP_CLKGEN_PLL_XPT_PLL_MISC_VCO_FB_DIV2_SHIFT 29
-#define BCHP_CLKGEN_PLL_XPT_PLL_MISC_VCO_FB_DIV2_DEFAULT 0x00000001
-
-/* CLKGEN :: PLL_XPT_PLL_MISC :: STAT_UPDATE [28:28] */
-#define BCHP_CLKGEN_PLL_XPT_PLL_MISC_STAT_UPDATE_MASK 0x10000000
-#define BCHP_CLKGEN_PLL_XPT_PLL_MISC_STAT_UPDATE_SHIFT 28
-#define BCHP_CLKGEN_PLL_XPT_PLL_MISC_STAT_UPDATE_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_XPT_PLL_MISC :: STAT_SELECT [27:25] */
-#define BCHP_CLKGEN_PLL_XPT_PLL_MISC_STAT_SELECT_MASK 0x0e000000
-#define BCHP_CLKGEN_PLL_XPT_PLL_MISC_STAT_SELECT_SHIFT 25
-#define BCHP_CLKGEN_PLL_XPT_PLL_MISC_STAT_SELECT_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_XPT_PLL_MISC :: STAT_RESET [24:24] */
-#define BCHP_CLKGEN_PLL_XPT_PLL_MISC_STAT_RESET_MASK 0x01000000
-#define BCHP_CLKGEN_PLL_XPT_PLL_MISC_STAT_RESET_SHIFT 24
-#define BCHP_CLKGEN_PLL_XPT_PLL_MISC_STAT_RESET_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_XPT_PLL_MISC :: STAT_MODE [23:22] */
-#define BCHP_CLKGEN_PLL_XPT_PLL_MISC_STAT_MODE_MASK 0x00c00000
-#define BCHP_CLKGEN_PLL_XPT_PLL_MISC_STAT_MODE_SHIFT 22
-#define BCHP_CLKGEN_PLL_XPT_PLL_MISC_STAT_MODE_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_XPT_PLL_MISC :: PWM_RATE [21:20] */
-#define BCHP_CLKGEN_PLL_XPT_PLL_MISC_PWM_RATE_MASK 0x00300000
-#define BCHP_CLKGEN_PLL_XPT_PLL_MISC_PWM_RATE_SHIFT 20
-#define BCHP_CLKGEN_PLL_XPT_PLL_MISC_PWM_RATE_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_XPT_PLL_MISC :: POST_CTRL_RESETB [19:18] */
-#define BCHP_CLKGEN_PLL_XPT_PLL_MISC_POST_CTRL_RESETB_MASK 0x000c0000
-#define BCHP_CLKGEN_PLL_XPT_PLL_MISC_POST_CTRL_RESETB_SHIFT 18
-#define BCHP_CLKGEN_PLL_XPT_PLL_MISC_POST_CTRL_RESETB_DEFAULT 0x00000003
-
-/* CLKGEN :: PLL_XPT_PLL_MISC :: PLLRESERVED2 [17:16] */
-#define BCHP_CLKGEN_PLL_XPT_PLL_MISC_PLLRESERVED2_MASK 0x00030000
-#define BCHP_CLKGEN_PLL_XPT_PLL_MISC_PLLRESERVED2_SHIFT 16
-#define BCHP_CLKGEN_PLL_XPT_PLL_MISC_PLLRESERVED2_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_XPT_PLL_MISC :: PLLRESERVED1 [15:15] */
-#define BCHP_CLKGEN_PLL_XPT_PLL_MISC_PLLRESERVED1_MASK 0x00008000
-#define BCHP_CLKGEN_PLL_XPT_PLL_MISC_PLLRESERVED1_SHIFT 15
-#define BCHP_CLKGEN_PLL_XPT_PLL_MISC_PLLRESERVED1_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_XPT_PLL_MISC :: NDIV_RELOCK [14:14] */
-#define BCHP_CLKGEN_PLL_XPT_PLL_MISC_NDIV_RELOCK_MASK 0x00004000
-#define BCHP_CLKGEN_PLL_XPT_PLL_MISC_NDIV_RELOCK_SHIFT 14
-#define BCHP_CLKGEN_PLL_XPT_PLL_MISC_NDIV_RELOCK_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_XPT_PLL_MISC :: FAST_LOCK [13:13] */
-#define BCHP_CLKGEN_PLL_XPT_PLL_MISC_FAST_LOCK_MASK 0x00002000
-#define BCHP_CLKGEN_PLL_XPT_PLL_MISC_FAST_LOCK_SHIFT 13
-#define BCHP_CLKGEN_PLL_XPT_PLL_MISC_FAST_LOCK_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_XPT_PLL_MISC :: DCO_CTRL_BYPASS_ENABLE [12:12] */
-#define BCHP_CLKGEN_PLL_XPT_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_MASK 0x00001000
-#define BCHP_CLKGEN_PLL_XPT_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_SHIFT 12
-#define BCHP_CLKGEN_PLL_XPT_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_XPT_PLL_MISC :: DCO_CTRL_BYPASS [11:00] */
-#define BCHP_CLKGEN_PLL_XPT_PLL_MISC_DCO_CTRL_BYPASS_MASK 0x00000fff
-#define BCHP_CLKGEN_PLL_XPT_PLL_MISC_DCO_CTRL_BYPASS_SHIFT 0
-#define BCHP_CLKGEN_PLL_XPT_PLL_MISC_DCO_CTRL_BYPASS_DEFAULT 0x00000000
-
-/***************************************************************************
- *PLL_XPT_PLL_MISC2 - Mscellaneous control bus continued.
- ***************************************************************************/
-/* CLKGEN :: PLL_XPT_PLL_MISC2 :: PLLRESERVED0 [31:00] */
-#define BCHP_CLKGEN_PLL_XPT_PLL_MISC2_PLLRESERVED0_MASK 0xffffffff
-#define BCHP_CLKGEN_PLL_XPT_PLL_MISC2_PLLRESERVED0_SHIFT 0
-#define BCHP_CLKGEN_PLL_XPT_PLL_MISC2_PLLRESERVED0_DEFAULT 0x00000001
-
-/***************************************************************************
- *PLL_XPT_PLL_PWRON - Poweron
- ***************************************************************************/
-/* CLKGEN :: PLL_XPT_PLL_PWRON :: reserved0 [31:01] */
-#define BCHP_CLKGEN_PLL_XPT_PLL_PWRON_reserved0_MASK 0xfffffffe
-#define BCHP_CLKGEN_PLL_XPT_PLL_PWRON_reserved0_SHIFT 1
-
-/* CLKGEN :: PLL_XPT_PLL_PWRON :: PWRON_PLL [00:00] */
-#define BCHP_CLKGEN_PLL_XPT_PLL_PWRON_PWRON_PLL_MASK 0x00000001
-#define BCHP_CLKGEN_PLL_XPT_PLL_PWRON_PWRON_PLL_SHIFT 0
-#define BCHP_CLKGEN_PLL_XPT_PLL_PWRON_PWRON_PLL_DEFAULT 0x00000001
-
-/***************************************************************************
- *PLL_XPT_PLL_RESET - Resets
- ***************************************************************************/
-/* CLKGEN :: PLL_XPT_PLL_RESET :: reserved0 [31:01] */
-#define BCHP_CLKGEN_PLL_XPT_PLL_RESET_reserved0_MASK 0xfffffffe
-#define BCHP_CLKGEN_PLL_XPT_PLL_RESET_reserved0_SHIFT 1
-
-/* CLKGEN :: PLL_XPT_PLL_RESET :: RESETD [00:00] */
-#define BCHP_CLKGEN_PLL_XPT_PLL_RESET_RESETD_MASK 0x00000001
-#define BCHP_CLKGEN_PLL_XPT_PLL_RESET_RESETD_SHIFT 0
-#define BCHP_CLKGEN_PLL_XPT_PLL_RESET_RESETD_DEFAULT 0x00000000
-
-/***************************************************************************
- *PLL_XPT_PLL_SSC_MODE_CONTROL_HIGH - Higher bits of Spread Spectrum mode control
- ***************************************************************************/
-/* CLKGEN :: PLL_XPT_PLL_SSC_MODE_CONTROL_HIGH :: reserved0 [31:16] */
-#define BCHP_CLKGEN_PLL_XPT_PLL_SSC_MODE_CONTROL_HIGH_reserved0_MASK 0xffff0000
-#define BCHP_CLKGEN_PLL_XPT_PLL_SSC_MODE_CONTROL_HIGH_reserved0_SHIFT 16
-
-/* CLKGEN :: PLL_XPT_PLL_SSC_MODE_CONTROL_HIGH :: SSC_STEP [15:00] */
-#define BCHP_CLKGEN_PLL_XPT_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_MASK 0x0000ffff
-#define BCHP_CLKGEN_PLL_XPT_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_SHIFT 0
-#define BCHP_CLKGEN_PLL_XPT_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *PLL_XPT_PLL_SSC_MODE_CONTROL_LOW - Lower bits of Spread Spectrum mode control
- ***************************************************************************/
-/* CLKGEN :: PLL_XPT_PLL_SSC_MODE_CONTROL_LOW :: reserved0 [31:23] */
-#define BCHP_CLKGEN_PLL_XPT_PLL_SSC_MODE_CONTROL_LOW_reserved0_MASK 0xff800000
-#define BCHP_CLKGEN_PLL_XPT_PLL_SSC_MODE_CONTROL_LOW_reserved0_SHIFT 23
-
-/* CLKGEN :: PLL_XPT_PLL_SSC_MODE_CONTROL_LOW :: SSC_MODE [22:22] */
-#define BCHP_CLKGEN_PLL_XPT_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_MASK 0x00400000
-#define BCHP_CLKGEN_PLL_XPT_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_SHIFT 22
-#define BCHP_CLKGEN_PLL_XPT_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_XPT_PLL_SSC_MODE_CONTROL_LOW :: SSC_LIMIT [21:00] */
-#define BCHP_CLKGEN_PLL_XPT_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_MASK 0x003fffff
-#define BCHP_CLKGEN_PLL_XPT_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_SHIFT 0
-#define BCHP_CLKGEN_PLL_XPT_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_DEFAULT 0x00000000
-
-/***************************************************************************
- *PLL_XPT_PLL_STATUS - Status
- ***************************************************************************/
-/* CLKGEN :: PLL_XPT_PLL_STATUS :: reserved0 [31:12] */
-#define BCHP_CLKGEN_PLL_XPT_PLL_STATUS_reserved0_MASK 0xfffff000
-#define BCHP_CLKGEN_PLL_XPT_PLL_STATUS_reserved0_SHIFT 12
-
-/* CLKGEN :: PLL_XPT_PLL_STATUS :: TEST_STATUS [11:00] */
-#define BCHP_CLKGEN_PLL_XPT_PLL_STATUS_TEST_STATUS_MASK 0x00000fff
-#define BCHP_CLKGEN_PLL_XPT_PLL_STATUS_TEST_STATUS_SHIFT 0
-
-/***************************************************************************
- *ANA_QDAC_TS28HPM_6MX_2MR_FC_H_E_INST_CLOCK_DISABLE - Disable ANA_QDAC_TS28HPM_6MX_2MR_FC_H_E_INST's clocks
- ***************************************************************************/
-/* CLKGEN :: ANA_QDAC_TS28HPM_6MX_2MR_FC_H_E_INST_CLOCK_DISABLE :: reserved0 [31:01] */
-#define BCHP_CLKGEN_ANA_QDAC_TS28HPM_6MX_2MR_FC_H_E_INST_CLOCK_DISABLE_reserved0_MASK 0xfffffffe
-#define BCHP_CLKGEN_ANA_QDAC_TS28HPM_6MX_2MR_FC_H_E_INST_CLOCK_DISABLE_reserved0_SHIFT 1
-
-/* CLKGEN :: ANA_QDAC_TS28HPM_6MX_2MR_FC_H_E_INST_CLOCK_DISABLE :: DISABLE_QDAC_DACADC_CLOCK [00:00] */
-#define BCHP_CLKGEN_ANA_QDAC_TS28HPM_6MX_2MR_FC_H_E_INST_CLOCK_DISABLE_DISABLE_QDAC_DACADC_CLOCK_MASK 0x00000001
-#define BCHP_CLKGEN_ANA_QDAC_TS28HPM_6MX_2MR_FC_H_E_INST_CLOCK_DISABLE_DISABLE_QDAC_DACADC_CLOCK_SHIFT 0
-#define BCHP_CLKGEN_ANA_QDAC_TS28HPM_6MX_2MR_FC_H_E_INST_CLOCK_DISABLE_DISABLE_QDAC_DACADC_CLOCK_DEFAULT 0x00000000
-
-/***************************************************************************
- *ANA_QDAC_TS28HPM_6MX_2MR_FC_H_E_INST_CLOCK_DISABLE_STATUS - Clock Disable Status
- ***************************************************************************/
-/* CLKGEN :: ANA_QDAC_TS28HPM_6MX_2MR_FC_H_E_INST_CLOCK_DISABLE_STATUS :: reserved0 [31:01] */
-#define BCHP_CLKGEN_ANA_QDAC_TS28HPM_6MX_2MR_FC_H_E_INST_CLOCK_DISABLE_STATUS_reserved0_MASK 0xfffffffe
-#define BCHP_CLKGEN_ANA_QDAC_TS28HPM_6MX_2MR_FC_H_E_INST_CLOCK_DISABLE_STATUS_reserved0_SHIFT 1
-
-/* CLKGEN :: ANA_QDAC_TS28HPM_6MX_2MR_FC_H_E_INST_CLOCK_DISABLE_STATUS :: DISABLE_QDAC_DACADC_CLOCK_STATUS [00:00] */
-#define BCHP_CLKGEN_ANA_QDAC_TS28HPM_6MX_2MR_FC_H_E_INST_CLOCK_DISABLE_STATUS_DISABLE_QDAC_DACADC_CLOCK_STATUS_MASK 0x00000001
-#define BCHP_CLKGEN_ANA_QDAC_TS28HPM_6MX_2MR_FC_H_E_INST_CLOCK_DISABLE_STATUS_DISABLE_QDAC_DACADC_CLOCK_STATUS_SHIFT 0
-
-/***************************************************************************
- *ANA_SW_AVS_TS28HPM_6MX_2MR_FC_H_E_INST_CLOCK_DISABLE - Disable ANA_SW_AVS_TS28HPM_6MX_2MR_FC_H_E_INST's clocks
- ***************************************************************************/
-/* CLKGEN :: ANA_SW_AVS_TS28HPM_6MX_2MR_FC_H_E_INST_CLOCK_DISABLE :: reserved0 [31:01] */
-#define BCHP_CLKGEN_ANA_SW_AVS_TS28HPM_6MX_2MR_FC_H_E_INST_CLOCK_DISABLE_reserved0_MASK 0xfffffffe
-#define BCHP_CLKGEN_ANA_SW_AVS_TS28HPM_6MX_2MR_FC_H_E_INST_CLOCK_DISABLE_reserved0_SHIFT 1
-
-/* CLKGEN :: ANA_SW_AVS_TS28HPM_6MX_2MR_FC_H_E_INST_CLOCK_DISABLE :: DISABLE_SYSTEM_54_VR_CLOCK [00:00] */
-#define BCHP_CLKGEN_ANA_SW_AVS_TS28HPM_6MX_2MR_FC_H_E_INST_CLOCK_DISABLE_DISABLE_SYSTEM_54_VR_CLOCK_MASK 0x00000001
-#define BCHP_CLKGEN_ANA_SW_AVS_TS28HPM_6MX_2MR_FC_H_E_INST_CLOCK_DISABLE_DISABLE_SYSTEM_54_VR_CLOCK_SHIFT 0
-#define BCHP_CLKGEN_ANA_SW_AVS_TS28HPM_6MX_2MR_FC_H_E_INST_CLOCK_DISABLE_DISABLE_SYSTEM_54_VR_CLOCK_DEFAULT 0x00000000
-
-/***************************************************************************
- *ANA_SW_AVS_TS28HPM_6MX_2MR_FC_H_E_INST_CLOCK_DISABLE_STATUS - Clock Disable Status
- ***************************************************************************/
-/* CLKGEN :: ANA_SW_AVS_TS28HPM_6MX_2MR_FC_H_E_INST_CLOCK_DISABLE_STATUS :: reserved0 [31:01] */
-#define BCHP_CLKGEN_ANA_SW_AVS_TS28HPM_6MX_2MR_FC_H_E_INST_CLOCK_DISABLE_STATUS_reserved0_MASK 0xfffffffe
-#define BCHP_CLKGEN_ANA_SW_AVS_TS28HPM_6MX_2MR_FC_H_E_INST_CLOCK_DISABLE_STATUS_reserved0_SHIFT 1
-
-/* CLKGEN :: ANA_SW_AVS_TS28HPM_6MX_2MR_FC_H_E_INST_CLOCK_DISABLE_STATUS :: DISABLE_SYSTEM_54_VR_CLOCK_STATUS [00:00] */
-#define BCHP_CLKGEN_ANA_SW_AVS_TS28HPM_6MX_2MR_FC_H_E_INST_CLOCK_DISABLE_STATUS_DISABLE_SYSTEM_54_VR_CLOCK_STATUS_MASK 0x00000001
-#define BCHP_CLKGEN_ANA_SW_AVS_TS28HPM_6MX_2MR_FC_H_E_INST_CLOCK_DISABLE_STATUS_DISABLE_SYSTEM_54_VR_CLOCK_STATUS_SHIFT 0
-
-/***************************************************************************
- *BVN_MVP_TOP_INST_CLOCK_ENABLE - Bvn mvp top inst clock enable
- ***************************************************************************/
-/* CLKGEN :: BVN_MVP_TOP_INST_CLOCK_ENABLE :: reserved0 [31:04] */
-#define BCHP_CLKGEN_BVN_MVP_TOP_INST_CLOCK_ENABLE_reserved0_MASK 0xfffffff0
-#define BCHP_CLKGEN_BVN_MVP_TOP_INST_CLOCK_ENABLE_reserved0_SHIFT 4
-
-/* CLKGEN :: BVN_MVP_TOP_INST_CLOCK_ENABLE :: BVND_SCB_CLOCK_ENABLE [03:03] */
-#define BCHP_CLKGEN_BVN_MVP_TOP_INST_CLOCK_ENABLE_BVND_SCB_CLOCK_ENABLE_MASK 0x00000008
-#define BCHP_CLKGEN_BVN_MVP_TOP_INST_CLOCK_ENABLE_BVND_SCB_CLOCK_ENABLE_SHIFT 3
-#define BCHP_CLKGEN_BVN_MVP_TOP_INST_CLOCK_ENABLE_BVND_SCB_CLOCK_ENABLE_DEFAULT 0x00000001
-
-/* CLKGEN :: BVN_MVP_TOP_INST_CLOCK_ENABLE :: BVND_BVB_324_CLOCK_ENABLE [02:02] */
-#define BCHP_CLKGEN_BVN_MVP_TOP_INST_CLOCK_ENABLE_BVND_BVB_324_CLOCK_ENABLE_MASK 0x00000004
-#define BCHP_CLKGEN_BVN_MVP_TOP_INST_CLOCK_ENABLE_BVND_BVB_324_CLOCK_ENABLE_SHIFT 2
-#define BCHP_CLKGEN_BVN_MVP_TOP_INST_CLOCK_ENABLE_BVND_BVB_324_CLOCK_ENABLE_DEFAULT 0x00000001
-
-/* CLKGEN :: BVN_MVP_TOP_INST_CLOCK_ENABLE :: BVND_54_CLOCK_ENABLE [01:01] */
-#define BCHP_CLKGEN_BVN_MVP_TOP_INST_CLOCK_ENABLE_BVND_54_CLOCK_ENABLE_MASK 0x00000002
-#define BCHP_CLKGEN_BVN_MVP_TOP_INST_CLOCK_ENABLE_BVND_54_CLOCK_ENABLE_SHIFT 1
-#define BCHP_CLKGEN_BVN_MVP_TOP_INST_CLOCK_ENABLE_BVND_54_CLOCK_ENABLE_DEFAULT 0x00000001
-
-/* CLKGEN :: BVN_MVP_TOP_INST_CLOCK_ENABLE :: BVND_108_CLOCK_ENABLE [00:00] */
-#define BCHP_CLKGEN_BVN_MVP_TOP_INST_CLOCK_ENABLE_BVND_108_CLOCK_ENABLE_MASK 0x00000001
-#define BCHP_CLKGEN_BVN_MVP_TOP_INST_CLOCK_ENABLE_BVND_108_CLOCK_ENABLE_SHIFT 0
-#define BCHP_CLKGEN_BVN_MVP_TOP_INST_CLOCK_ENABLE_BVND_108_CLOCK_ENABLE_DEFAULT 0x00000001
-
-/***************************************************************************
- *BVN_MVP_TOP_INST_CLOCK_ENABLE_STATUS - Clock Enable Status
- ***************************************************************************/
-/* CLKGEN :: BVN_MVP_TOP_INST_CLOCK_ENABLE_STATUS :: reserved0 [31:04] */
-#define BCHP_CLKGEN_BVN_MVP_TOP_INST_CLOCK_ENABLE_STATUS_reserved0_MASK 0xfffffff0
-#define BCHP_CLKGEN_BVN_MVP_TOP_INST_CLOCK_ENABLE_STATUS_reserved0_SHIFT 4
-
-/* CLKGEN :: BVN_MVP_TOP_INST_CLOCK_ENABLE_STATUS :: BVND_SCB_CLOCK_ENABLE_STATUS [03:03] */
-#define BCHP_CLKGEN_BVN_MVP_TOP_INST_CLOCK_ENABLE_STATUS_BVND_SCB_CLOCK_ENABLE_STATUS_MASK 0x00000008
-#define BCHP_CLKGEN_BVN_MVP_TOP_INST_CLOCK_ENABLE_STATUS_BVND_SCB_CLOCK_ENABLE_STATUS_SHIFT 3
-
-/* CLKGEN :: BVN_MVP_TOP_INST_CLOCK_ENABLE_STATUS :: BVND_BVB_324_CLOCK_ENABLE_STATUS [02:02] */
-#define BCHP_CLKGEN_BVN_MVP_TOP_INST_CLOCK_ENABLE_STATUS_BVND_BVB_324_CLOCK_ENABLE_STATUS_MASK 0x00000004
-#define BCHP_CLKGEN_BVN_MVP_TOP_INST_CLOCK_ENABLE_STATUS_BVND_BVB_324_CLOCK_ENABLE_STATUS_SHIFT 2
-
-/* CLKGEN :: BVN_MVP_TOP_INST_CLOCK_ENABLE_STATUS :: BVND_54_CLOCK_ENABLE_STATUS [01:01] */
-#define BCHP_CLKGEN_BVN_MVP_TOP_INST_CLOCK_ENABLE_STATUS_BVND_54_CLOCK_ENABLE_STATUS_MASK 0x00000002
-#define BCHP_CLKGEN_BVN_MVP_TOP_INST_CLOCK_ENABLE_STATUS_BVND_54_CLOCK_ENABLE_STATUS_SHIFT 1
-
-/* CLKGEN :: BVN_MVP_TOP_INST_CLOCK_ENABLE_STATUS :: BVND_108_CLOCK_ENABLE_STATUS [00:00] */
-#define BCHP_CLKGEN_BVN_MVP_TOP_INST_CLOCK_ENABLE_STATUS_BVND_108_CLOCK_ENABLE_STATUS_MASK 0x00000001
-#define BCHP_CLKGEN_BVN_MVP_TOP_INST_CLOCK_ENABLE_STATUS_BVND_108_CLOCK_ENABLE_STATUS_SHIFT 0
-
-/***************************************************************************
- *BVN_TOP_INST_CLOCK_ENABLE - Bvn top inst clock enable
- ***************************************************************************/
-/* CLKGEN :: BVN_TOP_INST_CLOCK_ENABLE :: reserved0 [31:04] */
-#define BCHP_CLKGEN_BVN_TOP_INST_CLOCK_ENABLE_reserved0_MASK 0xfffffff0
-#define BCHP_CLKGEN_BVN_TOP_INST_CLOCK_ENABLE_reserved0_SHIFT 4
-
-/* CLKGEN :: BVN_TOP_INST_CLOCK_ENABLE :: BVN_SCB_CLOCK_ENABLE [03:03] */
-#define BCHP_CLKGEN_BVN_TOP_INST_CLOCK_ENABLE_BVN_SCB_CLOCK_ENABLE_MASK 0x00000008
-#define BCHP_CLKGEN_BVN_TOP_INST_CLOCK_ENABLE_BVN_SCB_CLOCK_ENABLE_SHIFT 3
-#define BCHP_CLKGEN_BVN_TOP_INST_CLOCK_ENABLE_BVN_SCB_CLOCK_ENABLE_DEFAULT 0x00000001
-
-/* CLKGEN :: BVN_TOP_INST_CLOCK_ENABLE :: BVN_GISB_CLOCK_ENABLE [02:02] */
-#define BCHP_CLKGEN_BVN_TOP_INST_CLOCK_ENABLE_BVN_GISB_CLOCK_ENABLE_MASK 0x00000004
-#define BCHP_CLKGEN_BVN_TOP_INST_CLOCK_ENABLE_BVN_GISB_CLOCK_ENABLE_SHIFT 2
-#define BCHP_CLKGEN_BVN_TOP_INST_CLOCK_ENABLE_BVN_GISB_CLOCK_ENABLE_DEFAULT 0x00000001
-
-/* CLKGEN :: BVN_TOP_INST_CLOCK_ENABLE :: BVN_BVB_324_CLOCK_ENABLE [01:01] */
-#define BCHP_CLKGEN_BVN_TOP_INST_CLOCK_ENABLE_BVN_BVB_324_CLOCK_ENABLE_MASK 0x00000002
-#define BCHP_CLKGEN_BVN_TOP_INST_CLOCK_ENABLE_BVN_BVB_324_CLOCK_ENABLE_SHIFT 1
-#define BCHP_CLKGEN_BVN_TOP_INST_CLOCK_ENABLE_BVN_BVB_324_CLOCK_ENABLE_DEFAULT 0x00000001
-
-/* CLKGEN :: BVN_TOP_INST_CLOCK_ENABLE :: BVN_54_CLOCK_ENABLE [00:00] */
-#define BCHP_CLKGEN_BVN_TOP_INST_CLOCK_ENABLE_BVN_54_CLOCK_ENABLE_MASK 0x00000001
-#define BCHP_CLKGEN_BVN_TOP_INST_CLOCK_ENABLE_BVN_54_CLOCK_ENABLE_SHIFT 0
-#define BCHP_CLKGEN_BVN_TOP_INST_CLOCK_ENABLE_BVN_54_CLOCK_ENABLE_DEFAULT 0x00000001
-
-/***************************************************************************
- *BVN_TOP_INST_CLOCK_ENABLE_STATUS - Clock Enable Status
- ***************************************************************************/
-/* CLKGEN :: BVN_TOP_INST_CLOCK_ENABLE_STATUS :: reserved0 [31:04] */
-#define BCHP_CLKGEN_BVN_TOP_INST_CLOCK_ENABLE_STATUS_reserved0_MASK 0xfffffff0
-#define BCHP_CLKGEN_BVN_TOP_INST_CLOCK_ENABLE_STATUS_reserved0_SHIFT 4
-
-/* CLKGEN :: BVN_TOP_INST_CLOCK_ENABLE_STATUS :: BVN_SCB_CLOCK_ENABLE_STATUS [03:03] */
-#define BCHP_CLKGEN_BVN_TOP_INST_CLOCK_ENABLE_STATUS_BVN_SCB_CLOCK_ENABLE_STATUS_MASK 0x00000008
-#define BCHP_CLKGEN_BVN_TOP_INST_CLOCK_ENABLE_STATUS_BVN_SCB_CLOCK_ENABLE_STATUS_SHIFT 3
-
-/* CLKGEN :: BVN_TOP_INST_CLOCK_ENABLE_STATUS :: BVN_GISB_CLOCK_ENABLE_STATUS [02:02] */
-#define BCHP_CLKGEN_BVN_TOP_INST_CLOCK_ENABLE_STATUS_BVN_GISB_CLOCK_ENABLE_STATUS_MASK 0x00000004
-#define BCHP_CLKGEN_BVN_TOP_INST_CLOCK_ENABLE_STATUS_BVN_GISB_CLOCK_ENABLE_STATUS_SHIFT 2
-
-/* CLKGEN :: BVN_TOP_INST_CLOCK_ENABLE_STATUS :: BVN_BVB_324_CLOCK_ENABLE_STATUS [01:01] */
-#define BCHP_CLKGEN_BVN_TOP_INST_CLOCK_ENABLE_STATUS_BVN_BVB_324_CLOCK_ENABLE_STATUS_MASK 0x00000002
-#define BCHP_CLKGEN_BVN_TOP_INST_CLOCK_ENABLE_STATUS_BVN_BVB_324_CLOCK_ENABLE_STATUS_SHIFT 1
-
-/* CLKGEN :: BVN_TOP_INST_CLOCK_ENABLE_STATUS :: BVN_54_CLOCK_ENABLE_STATUS [00:00] */
-#define BCHP_CLKGEN_BVN_TOP_INST_CLOCK_ENABLE_STATUS_BVN_54_CLOCK_ENABLE_STATUS_MASK 0x00000001
-#define BCHP_CLKGEN_BVN_TOP_INST_CLOCK_ENABLE_STATUS_BVN_54_CLOCK_ENABLE_STATUS_SHIFT 0
-
-/***************************************************************************
- *CLKGEN_CLOCK_DISABLE - Disable CLKGEN's clocks
- ***************************************************************************/
-/* CLKGEN :: CLKGEN_CLOCK_DISABLE :: reserved0 [31:01] */
-#define BCHP_CLKGEN_CLKGEN_CLOCK_DISABLE_reserved0_MASK 0xfffffffe
-#define BCHP_CLKGEN_CLKGEN_CLOCK_DISABLE_reserved0_SHIFT 1
-
-/* CLKGEN :: CLKGEN_CLOCK_DISABLE :: DISABLE_OSC_DIGITAL_CLOCK [00:00] */
-#define BCHP_CLKGEN_CLKGEN_CLOCK_DISABLE_DISABLE_OSC_DIGITAL_CLOCK_MASK 0x00000001
-#define BCHP_CLKGEN_CLKGEN_CLOCK_DISABLE_DISABLE_OSC_DIGITAL_CLOCK_SHIFT 0
-#define BCHP_CLKGEN_CLKGEN_CLOCK_DISABLE_DISABLE_OSC_DIGITAL_CLOCK_DEFAULT 0x00000000
-
-/***************************************************************************
- *CLKGEN_CLOCK_DISABLE_STATUS - Clock Disable Status
- ***************************************************************************/
-/* CLKGEN :: CLKGEN_CLOCK_DISABLE_STATUS :: reserved0 [31:01] */
-#define BCHP_CLKGEN_CLKGEN_CLOCK_DISABLE_STATUS_reserved0_MASK 0xfffffffe
-#define BCHP_CLKGEN_CLKGEN_CLOCK_DISABLE_STATUS_reserved0_SHIFT 1
-
-/* CLKGEN :: CLKGEN_CLOCK_DISABLE_STATUS :: DISABLE_OSC_DIGITAL_CLOCK_STATUS [00:00] */
-#define BCHP_CLKGEN_CLKGEN_CLOCK_DISABLE_STATUS_DISABLE_OSC_DIGITAL_CLOCK_STATUS_MASK 0x00000001
-#define BCHP_CLKGEN_CLKGEN_CLOCK_DISABLE_STATUS_DISABLE_OSC_DIGITAL_CLOCK_STATUS_SHIFT 0
-
-/***************************************************************************
- *CLOCK_MONITOR_CONTROL - Clock Monitor Control
- ***************************************************************************/
-/* CLKGEN :: CLOCK_MONITOR_CONTROL :: reserved0 [31:04] */
-#define BCHP_CLKGEN_CLOCK_MONITOR_CONTROL_reserved0_MASK 0xfffffff0
-#define BCHP_CLKGEN_CLOCK_MONITOR_CONTROL_reserved0_SHIFT 4
-
-/* CLKGEN :: CLOCK_MONITOR_CONTROL :: STOP_VIEW_COUNTER [03:03] */
-#define BCHP_CLKGEN_CLOCK_MONITOR_CONTROL_STOP_VIEW_COUNTER_MASK 0x00000008
-#define BCHP_CLKGEN_CLOCK_MONITOR_CONTROL_STOP_VIEW_COUNTER_SHIFT 3
-#define BCHP_CLKGEN_CLOCK_MONITOR_CONTROL_STOP_VIEW_COUNTER_DEFAULT 0x00000001
-
-/* CLKGEN :: CLOCK_MONITOR_CONTROL :: STOP_REF_COUNTER [02:02] */
-#define BCHP_CLKGEN_CLOCK_MONITOR_CONTROL_STOP_REF_COUNTER_MASK 0x00000004
-#define BCHP_CLKGEN_CLOCK_MONITOR_CONTROL_STOP_REF_COUNTER_SHIFT 2
-#define BCHP_CLKGEN_CLOCK_MONITOR_CONTROL_STOP_REF_COUNTER_DEFAULT 0x00000001
-
-/* CLKGEN :: CLOCK_MONITOR_CONTROL :: RESET_COUNTERS [01:01] */
-#define BCHP_CLKGEN_CLOCK_MONITOR_CONTROL_RESET_COUNTERS_MASK 0x00000002
-#define BCHP_CLKGEN_CLOCK_MONITOR_CONTROL_RESET_COUNTERS_SHIFT 1
-#define BCHP_CLKGEN_CLOCK_MONITOR_CONTROL_RESET_COUNTERS_DEFAULT 0x00000001
-
-/* CLKGEN :: CLOCK_MONITOR_CONTROL :: LAUNCH_AUTO_REF_COUNT [00:00] */
-#define BCHP_CLKGEN_CLOCK_MONITOR_CONTROL_LAUNCH_AUTO_REF_COUNT_MASK 0x00000001
-#define BCHP_CLKGEN_CLOCK_MONITOR_CONTROL_LAUNCH_AUTO_REF_COUNT_SHIFT 0
-#define BCHP_CLKGEN_CLOCK_MONITOR_CONTROL_LAUNCH_AUTO_REF_COUNT_DEFAULT 0x00000001
-
-/***************************************************************************
- *CLOCK_MONITOR_MAX_COUNT - Clock Monitor Max Reference Count
- ***************************************************************************/
-/* CLKGEN :: CLOCK_MONITOR_MAX_COUNT :: SET_MAX_REF_COUNT [31:00] */
-#define BCHP_CLKGEN_CLOCK_MONITOR_MAX_COUNT_SET_MAX_REF_COUNT_MASK 0xffffffff
-#define BCHP_CLKGEN_CLOCK_MONITOR_MAX_COUNT_SET_MAX_REF_COUNT_SHIFT 0
-#define BCHP_CLKGEN_CLOCK_MONITOR_MAX_COUNT_SET_MAX_REF_COUNT_DEFAULT 0xffffffff
-
-/***************************************************************************
- *CLOCK_MONITOR_REF_COUNTER - Clock Monitor Reference Counter
- ***************************************************************************/
-/* CLKGEN :: CLOCK_MONITOR_REF_COUNTER :: READ_MAX_COUNT [31:00] */
-#define BCHP_CLKGEN_CLOCK_MONITOR_REF_COUNTER_READ_MAX_COUNT_MASK 0xffffffff
-#define BCHP_CLKGEN_CLOCK_MONITOR_REF_COUNTER_READ_MAX_COUNT_SHIFT 0
-
-/***************************************************************************
- *CLOCK_MONITOR_REF_DONE - Clock Monitor Reference Counter
- ***************************************************************************/
-/* CLKGEN :: CLOCK_MONITOR_REF_DONE :: reserved0 [31:01] */
-#define BCHP_CLKGEN_CLOCK_MONITOR_REF_DONE_reserved0_MASK 0xfffffffe
-#define BCHP_CLKGEN_CLOCK_MONITOR_REF_DONE_reserved0_SHIFT 1
-
-/* CLKGEN :: CLOCK_MONITOR_REF_DONE :: REF_COUNT_DONE [00:00] */
-#define BCHP_CLKGEN_CLOCK_MONITOR_REF_DONE_REF_COUNT_DONE_MASK 0x00000001
-#define BCHP_CLKGEN_CLOCK_MONITOR_REF_DONE_REF_COUNT_DONE_SHIFT 0
-
-/***************************************************************************
- *CLOCK_MONITOR_VIEW_COUNTER - Clock Monitor View Counter
- ***************************************************************************/
-/* CLKGEN :: CLOCK_MONITOR_VIEW_COUNTER :: READ_MAX_COUNT [31:00] */
-#define BCHP_CLKGEN_CLOCK_MONITOR_VIEW_COUNTER_READ_MAX_COUNT_MASK 0xffffffff
-#define BCHP_CLKGEN_CLOCK_MONITOR_VIEW_COUNTER_READ_MAX_COUNT_SHIFT 0
-
-/***************************************************************************
- *CORE_XPT_INST_CLOCK_DISABLE - Disable CORE_XPT_INST's clocks
- ***************************************************************************/
-/* CLKGEN :: CORE_XPT_INST_CLOCK_DISABLE :: reserved0 [31:05] */
-#define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_DISABLE_reserved0_MASK 0xffffffe0
-#define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_DISABLE_reserved0_SHIFT 5
-
-/* CLKGEN :: CORE_XPT_INST_CLOCK_DISABLE :: DISABLE_XPT_81_CLOCK [04:04] */
-#define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_DISABLE_DISABLE_XPT_81_CLOCK_MASK 0x00000010
-#define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_DISABLE_DISABLE_XPT_81_CLOCK_SHIFT 4
-#define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_DISABLE_DISABLE_XPT_81_CLOCK_DEFAULT 0x00000000
-
-/* CLKGEN :: CORE_XPT_INST_CLOCK_DISABLE :: DISABLE_XPT_54_CLOCK [03:03] */
-#define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_DISABLE_DISABLE_XPT_54_CLOCK_MASK 0x00000008
-#define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_DISABLE_DISABLE_XPT_54_CLOCK_SHIFT 3
-#define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_DISABLE_DISABLE_XPT_54_CLOCK_DEFAULT 0x00000000
-
-/* CLKGEN :: CORE_XPT_INST_CLOCK_DISABLE :: DISABLE_XPT_40P5_CLOCK [02:02] */
-#define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_DISABLE_DISABLE_XPT_40P5_CLOCK_MASK 0x00000004
-#define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_DISABLE_DISABLE_XPT_40P5_CLOCK_SHIFT 2
-#define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_DISABLE_DISABLE_XPT_40P5_CLOCK_DEFAULT 0x00000000
-
-/* CLKGEN :: CORE_XPT_INST_CLOCK_DISABLE :: DISABLE_XPT_27_CLOCK [01:01] */
-#define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_DISABLE_DISABLE_XPT_27_CLOCK_MASK 0x00000002
-#define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_DISABLE_DISABLE_XPT_27_CLOCK_SHIFT 1
-#define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_DISABLE_DISABLE_XPT_27_CLOCK_DEFAULT 0x00000000
-
-/* CLKGEN :: CORE_XPT_INST_CLOCK_DISABLE :: DISABLE_XPT_20P25_CLOCK [00:00] */
-#define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_DISABLE_DISABLE_XPT_20P25_CLOCK_MASK 0x00000001
-#define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_DISABLE_DISABLE_XPT_20P25_CLOCK_SHIFT 0
-#define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_DISABLE_DISABLE_XPT_20P25_CLOCK_DEFAULT 0x00000000
-
-/***************************************************************************
- *CORE_XPT_INST_CLOCK_DISABLE_STATUS - Clock Disable Status
- ***************************************************************************/
-/* CLKGEN :: CORE_XPT_INST_CLOCK_DISABLE_STATUS :: reserved0 [31:05] */
-#define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_DISABLE_STATUS_reserved0_MASK 0xffffffe0
-#define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_DISABLE_STATUS_reserved0_SHIFT 5
-
-/* CLKGEN :: CORE_XPT_INST_CLOCK_DISABLE_STATUS :: DISABLE_XPT_81_CLOCK_STATUS [04:04] */
-#define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_DISABLE_STATUS_DISABLE_XPT_81_CLOCK_STATUS_MASK 0x00000010
-#define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_DISABLE_STATUS_DISABLE_XPT_81_CLOCK_STATUS_SHIFT 4
-
-/* CLKGEN :: CORE_XPT_INST_CLOCK_DISABLE_STATUS :: DISABLE_XPT_54_CLOCK_STATUS [03:03] */
-#define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_DISABLE_STATUS_DISABLE_XPT_54_CLOCK_STATUS_MASK 0x00000008
-#define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_DISABLE_STATUS_DISABLE_XPT_54_CLOCK_STATUS_SHIFT 3
-
-/* CLKGEN :: CORE_XPT_INST_CLOCK_DISABLE_STATUS :: DISABLE_XPT_40P5_CLOCK_STATUS [02:02] */
-#define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_DISABLE_STATUS_DISABLE_XPT_40P5_CLOCK_STATUS_MASK 0x00000004
-#define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_DISABLE_STATUS_DISABLE_XPT_40P5_CLOCK_STATUS_SHIFT 2
-
-/* CLKGEN :: CORE_XPT_INST_CLOCK_DISABLE_STATUS :: DISABLE_XPT_27_CLOCK_STATUS [01:01] */
-#define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_DISABLE_STATUS_DISABLE_XPT_27_CLOCK_STATUS_MASK 0x00000002
-#define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_DISABLE_STATUS_DISABLE_XPT_27_CLOCK_STATUS_SHIFT 1
-
-/* CLKGEN :: CORE_XPT_INST_CLOCK_DISABLE_STATUS :: DISABLE_XPT_20P25_CLOCK_STATUS [00:00] */
-#define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_DISABLE_STATUS_DISABLE_XPT_20P25_CLOCK_STATUS_MASK 0x00000001
-#define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_DISABLE_STATUS_DISABLE_XPT_20P25_CLOCK_STATUS_SHIFT 0
-
-/***************************************************************************
- *CORE_XPT_INST_CLOCK_ENABLE - Core xpt inst clock enable
- ***************************************************************************/
-/* CLKGEN :: CORE_XPT_INST_CLOCK_ENABLE :: reserved0 [31:05] */
-#define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_ENABLE_reserved0_MASK 0xffffffe0
-#define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_ENABLE_reserved0_SHIFT 5
-
-/* CLKGEN :: CORE_XPT_INST_CLOCK_ENABLE :: XPT_SCB_CLOCK_ENABLE [04:04] */
-#define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_ENABLE_XPT_SCB_CLOCK_ENABLE_MASK 0x00000010
-#define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_ENABLE_XPT_SCB_CLOCK_ENABLE_SHIFT 4
-#define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_ENABLE_XPT_SCB_CLOCK_ENABLE_DEFAULT 0x00000001
-
-/* CLKGEN :: CORE_XPT_INST_CLOCK_ENABLE :: XPT_GISB_CLOCK_ENABLE [03:03] */
-#define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_ENABLE_XPT_GISB_CLOCK_ENABLE_MASK 0x00000008
-#define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_ENABLE_XPT_GISB_CLOCK_ENABLE_SHIFT 3
-#define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_ENABLE_XPT_GISB_CLOCK_ENABLE_DEFAULT 0x00000001
-
-/* CLKGEN :: CORE_XPT_INST_CLOCK_ENABLE :: XPT_CORE_CLOCK_ENABLE [02:02] */
-#define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_ENABLE_XPT_CORE_CLOCK_ENABLE_MASK 0x00000004
-#define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_ENABLE_XPT_CORE_CLOCK_ENABLE_SHIFT 2
-#define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_ENABLE_XPT_CORE_CLOCK_ENABLE_DEFAULT 0x00000001
-
-/* CLKGEN :: CORE_XPT_INST_CLOCK_ENABLE :: XPT_54_CLOCK_ENABLE [01:01] */
-#define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_ENABLE_XPT_54_CLOCK_ENABLE_MASK 0x00000002
-#define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_ENABLE_XPT_54_CLOCK_ENABLE_SHIFT 1
-#define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_ENABLE_XPT_54_CLOCK_ENABLE_DEFAULT 0x00000001
-
-/* CLKGEN :: CORE_XPT_INST_CLOCK_ENABLE :: XPT_108_CLOCK_ENABLE [00:00] */
-#define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_ENABLE_XPT_108_CLOCK_ENABLE_MASK 0x00000001
-#define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_ENABLE_XPT_108_CLOCK_ENABLE_SHIFT 0
-#define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_ENABLE_XPT_108_CLOCK_ENABLE_DEFAULT 0x00000001
-
-/***************************************************************************
- *CORE_XPT_INST_CLOCK_ENABLE_STATUS - Clock Enable Status
- ***************************************************************************/
-/* CLKGEN :: CORE_XPT_INST_CLOCK_ENABLE_STATUS :: reserved0 [31:05] */
-#define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_ENABLE_STATUS_reserved0_MASK 0xffffffe0
-#define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_ENABLE_STATUS_reserved0_SHIFT 5
-
-/* CLKGEN :: CORE_XPT_INST_CLOCK_ENABLE_STATUS :: XPT_SCB_CLOCK_ENABLE_STATUS [04:04] */
-#define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_ENABLE_STATUS_XPT_SCB_CLOCK_ENABLE_STATUS_MASK 0x00000010
-#define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_ENABLE_STATUS_XPT_SCB_CLOCK_ENABLE_STATUS_SHIFT 4
-
-/* CLKGEN :: CORE_XPT_INST_CLOCK_ENABLE_STATUS :: XPT_GISB_CLOCK_ENABLE_STATUS [03:03] */
-#define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_ENABLE_STATUS_XPT_GISB_CLOCK_ENABLE_STATUS_MASK 0x00000008
-#define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_ENABLE_STATUS_XPT_GISB_CLOCK_ENABLE_STATUS_SHIFT 3
-
-/* CLKGEN :: CORE_XPT_INST_CLOCK_ENABLE_STATUS :: XPT_CORE_CLOCK_ENABLE_STATUS [02:02] */
-#define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_ENABLE_STATUS_XPT_CORE_CLOCK_ENABLE_STATUS_MASK 0x00000004
-#define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_ENABLE_STATUS_XPT_CORE_CLOCK_ENABLE_STATUS_SHIFT 2
-
-/* CLKGEN :: CORE_XPT_INST_CLOCK_ENABLE_STATUS :: XPT_54_CLOCK_ENABLE_STATUS [01:01] */
-#define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_ENABLE_STATUS_XPT_54_CLOCK_ENABLE_STATUS_MASK 0x00000002
-#define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_ENABLE_STATUS_XPT_54_CLOCK_ENABLE_STATUS_SHIFT 1
-
-/* CLKGEN :: CORE_XPT_INST_CLOCK_ENABLE_STATUS :: XPT_108_CLOCK_ENABLE_STATUS [00:00] */
-#define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_ENABLE_STATUS_XPT_108_CLOCK_ENABLE_STATUS_MASK 0x00000001
-#define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_ENABLE_STATUS_XPT_108_CLOCK_ENABLE_STATUS_SHIFT 0
-
-/***************************************************************************
- *CORE_XPT_INST_OBSERVE_CLOCK - Core xpt inst observe clock
- ***************************************************************************/
-/* CLKGEN :: CORE_XPT_INST_OBSERVE_CLOCK :: reserved0 [31:06] */
-#define BCHP_CLKGEN_CORE_XPT_INST_OBSERVE_CLOCK_reserved0_MASK 0xffffffc0
-#define BCHP_CLKGEN_CORE_XPT_INST_OBSERVE_CLOCK_reserved0_SHIFT 6
-
-/* CLKGEN :: CORE_XPT_INST_OBSERVE_CLOCK :: XPT_ENABLE_OBSERVE_CLOCK [05:05] */
-#define BCHP_CLKGEN_CORE_XPT_INST_OBSERVE_CLOCK_XPT_ENABLE_OBSERVE_CLOCK_MASK 0x00000020
-#define BCHP_CLKGEN_CORE_XPT_INST_OBSERVE_CLOCK_XPT_ENABLE_OBSERVE_CLOCK_SHIFT 5
-#define BCHP_CLKGEN_CORE_XPT_INST_OBSERVE_CLOCK_XPT_ENABLE_OBSERVE_CLOCK_DEFAULT 0x00000000
-
-/* CLKGEN :: CORE_XPT_INST_OBSERVE_CLOCK :: XPT_ENABLE_DIVIDER_OBSERVE_CLOCK [04:04] */
-#define BCHP_CLKGEN_CORE_XPT_INST_OBSERVE_CLOCK_XPT_ENABLE_DIVIDER_OBSERVE_CLOCK_MASK 0x00000010
-#define BCHP_CLKGEN_CORE_XPT_INST_OBSERVE_CLOCK_XPT_ENABLE_DIVIDER_OBSERVE_CLOCK_SHIFT 4
-#define BCHP_CLKGEN_CORE_XPT_INST_OBSERVE_CLOCK_XPT_ENABLE_DIVIDER_OBSERVE_CLOCK_DEFAULT 0x00000000
-
-/* CLKGEN :: CORE_XPT_INST_OBSERVE_CLOCK :: XPT_CONTROL_OBSERVE_CLOCK [03:00] */
-#define BCHP_CLKGEN_CORE_XPT_INST_OBSERVE_CLOCK_XPT_CONTROL_OBSERVE_CLOCK_MASK 0x0000000f
-#define BCHP_CLKGEN_CORE_XPT_INST_OBSERVE_CLOCK_XPT_CONTROL_OBSERVE_CLOCK_SHIFT 0
-#define BCHP_CLKGEN_CORE_XPT_INST_OBSERVE_CLOCK_XPT_CONTROL_OBSERVE_CLOCK_DEFAULT 0x00000000
-
-/***************************************************************************
- *DISABLE_AVS_TOP_DURING_S2 - Disable AVS_TOP 54MHz clocks during S2 standby.
- ***************************************************************************/
-/* CLKGEN :: DISABLE_AVS_TOP_DURING_S2 :: reserved0 [31:01] */
-#define BCHP_CLKGEN_DISABLE_AVS_TOP_DURING_S2_reserved0_MASK 0xfffffffe
-#define BCHP_CLKGEN_DISABLE_AVS_TOP_DURING_S2_reserved0_SHIFT 1
-
-/* CLKGEN :: DISABLE_AVS_TOP_DURING_S2 :: DISABLE_AVS_TOP [00:00] */
-#define BCHP_CLKGEN_DISABLE_AVS_TOP_DURING_S2_DISABLE_AVS_TOP_MASK 0x00000001
-#define BCHP_CLKGEN_DISABLE_AVS_TOP_DURING_S2_DISABLE_AVS_TOP_SHIFT 0
-#define BCHP_CLKGEN_DISABLE_AVS_TOP_DURING_S2_DISABLE_AVS_TOP_DEFAULT 0x00000000
-
-/***************************************************************************
- *DISABLE_AVS_TOP_DURING_S2_SECURE - Secure AVS_TOP clock disable. Set at start-up to guarantee AVS_TOP is clock gated in S2 standby.
- ***************************************************************************/
-/* CLKGEN :: DISABLE_AVS_TOP_DURING_S2_SECURE :: reserved0 [31:01] */
-#define BCHP_CLKGEN_DISABLE_AVS_TOP_DURING_S2_SECURE_reserved0_MASK 0xfffffffe
-#define BCHP_CLKGEN_DISABLE_AVS_TOP_DURING_S2_SECURE_reserved0_SHIFT 1
-
-/* CLKGEN :: DISABLE_AVS_TOP_DURING_S2_SECURE :: DISABLE_AVS_TOP_SECURE [00:00] */
-#define BCHP_CLKGEN_DISABLE_AVS_TOP_DURING_S2_SECURE_DISABLE_AVS_TOP_SECURE_MASK 0x00000001
-#define BCHP_CLKGEN_DISABLE_AVS_TOP_DURING_S2_SECURE_DISABLE_AVS_TOP_SECURE_SHIFT 0
-#define BCHP_CLKGEN_DISABLE_AVS_TOP_DURING_S2_SECURE_DISABLE_AVS_TOP_SECURE_DEFAULT 0x00000000
-
-/***************************************************************************
- *DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_DISABLE - Disable DUAL_GENET_TOP_DUAL_RGMII_INST's clocks
- ***************************************************************************/
-/* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_DISABLE :: reserved0 [31:08] */
-#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_DISABLE_reserved0_MASK 0xffffff00
-#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_DISABLE_reserved0_SHIFT 8
-
-/* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_DISABLE :: DISABLE_GENET1_SYSTEM_SLOW_CLOCK [07:07] */
-#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_DISABLE_DISABLE_GENET1_SYSTEM_SLOW_CLOCK_MASK 0x00000080
-#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_DISABLE_DISABLE_GENET1_SYSTEM_SLOW_CLOCK_SHIFT 7
-#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_DISABLE_DISABLE_GENET1_SYSTEM_SLOW_CLOCK_DEFAULT 0x00000000
-
-/* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_DISABLE :: DISABLE_GENET1_SYSTEM_PM_CLOCK [06:06] */
-#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_DISABLE_DISABLE_GENET1_SYSTEM_PM_CLOCK_MASK 0x00000040
-#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_DISABLE_DISABLE_GENET1_SYSTEM_PM_CLOCK_SHIFT 6
-#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_DISABLE_DISABLE_GENET1_SYSTEM_PM_CLOCK_DEFAULT 0x00000000
-
-/* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_DISABLE :: DISABLE_GENET1_SYSTEM_FAST_CLOCK [05:05] */
-#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_DISABLE_DISABLE_GENET1_SYSTEM_FAST_CLOCK_MASK 0x00000020
-#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_DISABLE_DISABLE_GENET1_SYSTEM_FAST_CLOCK_SHIFT 5
-#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_DISABLE_DISABLE_GENET1_SYSTEM_FAST_CLOCK_DEFAULT 0x00000000
-
-/* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_DISABLE :: DISABLE_GENET1_ALWAYSON_CLOCK [04:04] */
-#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_DISABLE_DISABLE_GENET1_ALWAYSON_CLOCK_MASK 0x00000010
-#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_DISABLE_DISABLE_GENET1_ALWAYSON_CLOCK_SHIFT 4
-#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_DISABLE_DISABLE_GENET1_ALWAYSON_CLOCK_DEFAULT 0x00000000
-
-/* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_DISABLE :: DISABLE_GENET0_SYSTEM_SLOW_CLOCK [03:03] */
-#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_DISABLE_DISABLE_GENET0_SYSTEM_SLOW_CLOCK_MASK 0x00000008
-#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_DISABLE_DISABLE_GENET0_SYSTEM_SLOW_CLOCK_SHIFT 3
-#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_DISABLE_DISABLE_GENET0_SYSTEM_SLOW_CLOCK_DEFAULT 0x00000000
-
-/* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_DISABLE :: DISABLE_GENET0_SYSTEM_PM_CLOCK [02:02] */
-#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_DISABLE_DISABLE_GENET0_SYSTEM_PM_CLOCK_MASK 0x00000004
-#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_DISABLE_DISABLE_GENET0_SYSTEM_PM_CLOCK_SHIFT 2
-#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_DISABLE_DISABLE_GENET0_SYSTEM_PM_CLOCK_DEFAULT 0x00000000
-
-/* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_DISABLE :: DISABLE_GENET0_SYSTEM_FAST_CLOCK [01:01] */
-#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_DISABLE_DISABLE_GENET0_SYSTEM_FAST_CLOCK_MASK 0x00000002
-#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_DISABLE_DISABLE_GENET0_SYSTEM_FAST_CLOCK_SHIFT 1
-#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_DISABLE_DISABLE_GENET0_SYSTEM_FAST_CLOCK_DEFAULT 0x00000000
-
-/* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_DISABLE :: DISABLE_GENET0_ALWAYSON_CLOCK [00:00] */
-#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_DISABLE_DISABLE_GENET0_ALWAYSON_CLOCK_MASK 0x00000001
-#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_DISABLE_DISABLE_GENET0_ALWAYSON_CLOCK_SHIFT 0
-#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_DISABLE_DISABLE_GENET0_ALWAYSON_CLOCK_DEFAULT 0x00000000
-
-/***************************************************************************
- *DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_DISABLE_STATUS - Clock Disable Status
- ***************************************************************************/
-/* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_DISABLE_STATUS :: reserved0 [31:08] */
-#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_DISABLE_STATUS_reserved0_MASK 0xffffff00
-#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_DISABLE_STATUS_reserved0_SHIFT 8
-
-/* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_DISABLE_STATUS :: DISABLE_GENET1_SYSTEM_SLOW_CLOCK_STATUS [07:07] */
-#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_DISABLE_STATUS_DISABLE_GENET1_SYSTEM_SLOW_CLOCK_STATUS_MASK 0x00000080
-#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_DISABLE_STATUS_DISABLE_GENET1_SYSTEM_SLOW_CLOCK_STATUS_SHIFT 7
-
-/* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_DISABLE_STATUS :: DISABLE_GENET1_SYSTEM_PM_CLOCK_STATUS [06:06] */
-#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_DISABLE_STATUS_DISABLE_GENET1_SYSTEM_PM_CLOCK_STATUS_MASK 0x00000040
-#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_DISABLE_STATUS_DISABLE_GENET1_SYSTEM_PM_CLOCK_STATUS_SHIFT 6
-
-/* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_DISABLE_STATUS :: DISABLE_GENET1_SYSTEM_FAST_CLOCK_STATUS [05:05] */
-#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_DISABLE_STATUS_DISABLE_GENET1_SYSTEM_FAST_CLOCK_STATUS_MASK 0x00000020
-#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_DISABLE_STATUS_DISABLE_GENET1_SYSTEM_FAST_CLOCK_STATUS_SHIFT 5
-
-/* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_DISABLE_STATUS :: DISABLE_GENET1_ALWAYSON_CLOCK_STATUS [04:04] */
-#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_DISABLE_STATUS_DISABLE_GENET1_ALWAYSON_CLOCK_STATUS_MASK 0x00000010
-#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_DISABLE_STATUS_DISABLE_GENET1_ALWAYSON_CLOCK_STATUS_SHIFT 4
-
-/* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_DISABLE_STATUS :: DISABLE_GENET0_SYSTEM_SLOW_CLOCK_STATUS [03:03] */
-#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_DISABLE_STATUS_DISABLE_GENET0_SYSTEM_SLOW_CLOCK_STATUS_MASK 0x00000008
-#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_DISABLE_STATUS_DISABLE_GENET0_SYSTEM_SLOW_CLOCK_STATUS_SHIFT 3
-
-/* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_DISABLE_STATUS :: DISABLE_GENET0_SYSTEM_PM_CLOCK_STATUS [02:02] */
-#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_DISABLE_STATUS_DISABLE_GENET0_SYSTEM_PM_CLOCK_STATUS_MASK 0x00000004
-#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_DISABLE_STATUS_DISABLE_GENET0_SYSTEM_PM_CLOCK_STATUS_SHIFT 2
-
-/* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_DISABLE_STATUS :: DISABLE_GENET0_SYSTEM_FAST_CLOCK_STATUS [01:01] */
-#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_DISABLE_STATUS_DISABLE_GENET0_SYSTEM_FAST_CLOCK_STATUS_MASK 0x00000002
-#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_DISABLE_STATUS_DISABLE_GENET0_SYSTEM_FAST_CLOCK_STATUS_SHIFT 1
-
-/* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_DISABLE_STATUS :: DISABLE_GENET0_ALWAYSON_CLOCK_STATUS [00:00] */
-#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_DISABLE_STATUS_DISABLE_GENET0_ALWAYSON_CLOCK_STATUS_MASK 0x00000001
-#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_DISABLE_STATUS_DISABLE_GENET0_ALWAYSON_CLOCK_STATUS_SHIFT 0
-
-/***************************************************************************
- *DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE - Dual genet top dual rgmii inst clock enable
- ***************************************************************************/
-/* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE :: reserved0 [31:02] */
-#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_reserved0_MASK 0xfffffffc
-#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_reserved0_SHIFT 2
-
-/* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE :: GENET_SCB_CLOCK_ENABLE [01:01] */
-#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET_SCB_CLOCK_ENABLE_MASK 0x00000002
-#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET_SCB_CLOCK_ENABLE_SHIFT 1
-#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET_SCB_CLOCK_ENABLE_DEFAULT 0x00000001
-
-/* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE :: GENET_54_CLOCK_ENABLE [00:00] */
-#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET_54_CLOCK_ENABLE_MASK 0x00000001
-#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET_54_CLOCK_ENABLE_SHIFT 0
-#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET_54_CLOCK_ENABLE_DEFAULT 0x00000001
-
-/***************************************************************************
- *DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET0 - Dual genet top dual rgmii inst clock enable genet0
- ***************************************************************************/
-/* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET0 :: reserved0 [31:09] */
-#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET0_reserved0_MASK 0xfffffe00
-#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET0_reserved0_SHIFT 9
-
-/* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET0 :: GENET0_UNIMAC_SYS_TX_CLOCK_ENABLE_GENET0 [08:08] */
-#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET0_GENET0_UNIMAC_SYS_TX_CLOCK_ENABLE_GENET0_MASK 0x00000100
-#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET0_GENET0_UNIMAC_SYS_TX_CLOCK_ENABLE_GENET0_SHIFT 8
-#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET0_GENET0_UNIMAC_SYS_TX_CLOCK_ENABLE_GENET0_DEFAULT 0x00000001
-
-/* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET0 :: GENET0_UNIMAC_SYS_RX_CLOCK_ENABLE_GENET0 [07:07] */
-#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET0_GENET0_UNIMAC_SYS_RX_CLOCK_ENABLE_GENET0_MASK 0x00000080
-#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET0_GENET0_UNIMAC_SYS_RX_CLOCK_ENABLE_GENET0_SHIFT 7
-#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET0_GENET0_UNIMAC_SYS_RX_CLOCK_ENABLE_GENET0_DEFAULT 0x00000001
-
-/* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET0 :: GENET0_SCB_CLOCK_ENABLE_GENET0 [06:06] */
-#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET0_GENET0_SCB_CLOCK_ENABLE_GENET0_MASK 0x00000040
-#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET0_GENET0_SCB_CLOCK_ENABLE_GENET0_SHIFT 6
-#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET0_GENET0_SCB_CLOCK_ENABLE_GENET0_DEFAULT 0x00000001
-
-/* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET0 :: GENET0_L2INTR_CLOCK_ENABLE_GENET0 [05:05] */
-#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET0_GENET0_L2INTR_CLOCK_ENABLE_GENET0_MASK 0x00000020
-#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET0_GENET0_L2INTR_CLOCK_ENABLE_GENET0_SHIFT 5
-#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET0_GENET0_L2INTR_CLOCK_ENABLE_GENET0_DEFAULT 0x00000001
-
-/* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET0 :: GENET0_HFB_CLOCK_ENABLE_GENET0 [04:04] */
-#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET0_GENET0_HFB_CLOCK_ENABLE_GENET0_MASK 0x00000010
-#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET0_GENET0_HFB_CLOCK_ENABLE_GENET0_SHIFT 4
-#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET0_GENET0_HFB_CLOCK_ENABLE_GENET0_DEFAULT 0x00000001
-
-/* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET0 :: GENET0_GMII_CLOCK_ENABLE_GENET0 [03:03] */
-#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET0_GENET0_GMII_CLOCK_ENABLE_GENET0_MASK 0x00000008
-#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET0_GENET0_GMII_CLOCK_ENABLE_GENET0_SHIFT 3
-#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET0_GENET0_GMII_CLOCK_ENABLE_GENET0_DEFAULT 0x00000001
-
-/* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET0 :: GENET0_GISB_CLOCK_ENABLE_GENET0 [02:02] */
-#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET0_GENET0_GISB_CLOCK_ENABLE_GENET0_MASK 0x00000004
-#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET0_GENET0_GISB_CLOCK_ENABLE_GENET0_SHIFT 2
-#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET0_GENET0_GISB_CLOCK_ENABLE_GENET0_DEFAULT 0x00000001
-
-/* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET0 :: GENET0_EEE_CLOCK_ENABLE_GENET0 [01:01] */
-#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET0_GENET0_EEE_CLOCK_ENABLE_GENET0_MASK 0x00000002
-#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET0_GENET0_EEE_CLOCK_ENABLE_GENET0_SHIFT 1
-#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET0_GENET0_EEE_CLOCK_ENABLE_GENET0_DEFAULT 0x00000001
-
-/* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET0 :: GENET0_CLK_250_CLOCK_ENABLE_GENET0 [00:00] */
-#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET0_GENET0_CLK_250_CLOCK_ENABLE_GENET0_MASK 0x00000001
-#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET0_GENET0_CLK_250_CLOCK_ENABLE_GENET0_SHIFT 0
-#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET0_GENET0_CLK_250_CLOCK_ENABLE_GENET0_DEFAULT 0x00000001
-
-/***************************************************************************
- *DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET0_STATUS - Clock Enable Status
- ***************************************************************************/
-/* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET0_STATUS :: reserved0 [31:09] */
-#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET0_STATUS_reserved0_MASK 0xfffffe00
-#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET0_STATUS_reserved0_SHIFT 9
-
-/* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET0_STATUS :: GENET0_UNIMAC_SYS_TX_CLOCK_ENABLE_GENET0_STATUS [08:08] */
-#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET0_STATUS_GENET0_UNIMAC_SYS_TX_CLOCK_ENABLE_GENET0_STATUS_MASK 0x00000100
-#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET0_STATUS_GENET0_UNIMAC_SYS_TX_CLOCK_ENABLE_GENET0_STATUS_SHIFT 8
-
-/* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET0_STATUS :: GENET0_UNIMAC_SYS_RX_CLOCK_ENABLE_GENET0_STATUS [07:07] */
-#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET0_STATUS_GENET0_UNIMAC_SYS_RX_CLOCK_ENABLE_GENET0_STATUS_MASK 0x00000080
-#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET0_STATUS_GENET0_UNIMAC_SYS_RX_CLOCK_ENABLE_GENET0_STATUS_SHIFT 7
-
-/* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET0_STATUS :: GENET0_SCB_CLOCK_ENABLE_GENET0_STATUS [06:06] */
-#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET0_STATUS_GENET0_SCB_CLOCK_ENABLE_GENET0_STATUS_MASK 0x00000040
-#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET0_STATUS_GENET0_SCB_CLOCK_ENABLE_GENET0_STATUS_SHIFT 6
-
-/* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET0_STATUS :: GENET0_L2INTR_CLOCK_ENABLE_GENET0_STATUS [05:05] */
-#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET0_STATUS_GENET0_L2INTR_CLOCK_ENABLE_GENET0_STATUS_MASK 0x00000020
-#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET0_STATUS_GENET0_L2INTR_CLOCK_ENABLE_GENET0_STATUS_SHIFT 5
-
-/* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET0_STATUS :: GENET0_HFB_CLOCK_ENABLE_GENET0_STATUS [04:04] */
-#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET0_STATUS_GENET0_HFB_CLOCK_ENABLE_GENET0_STATUS_MASK 0x00000010
-#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET0_STATUS_GENET0_HFB_CLOCK_ENABLE_GENET0_STATUS_SHIFT 4
-
-/* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET0_STATUS :: GENET0_GMII_CLOCK_ENABLE_GENET0_STATUS [03:03] */
-#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET0_STATUS_GENET0_GMII_CLOCK_ENABLE_GENET0_STATUS_MASK 0x00000008
-#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET0_STATUS_GENET0_GMII_CLOCK_ENABLE_GENET0_STATUS_SHIFT 3
-
-/* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET0_STATUS :: GENET0_GISB_CLOCK_ENABLE_GENET0_STATUS [02:02] */
-#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET0_STATUS_GENET0_GISB_CLOCK_ENABLE_GENET0_STATUS_MASK 0x00000004
-#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET0_STATUS_GENET0_GISB_CLOCK_ENABLE_GENET0_STATUS_SHIFT 2
-
-/* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET0_STATUS :: GENET0_EEE_CLOCK_ENABLE_GENET0_STATUS [01:01] */
-#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET0_STATUS_GENET0_EEE_CLOCK_ENABLE_GENET0_STATUS_MASK 0x00000002
-#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET0_STATUS_GENET0_EEE_CLOCK_ENABLE_GENET0_STATUS_SHIFT 1
-
-/* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET0_STATUS :: GENET0_CLK_250_CLOCK_ENABLE_GENET0_STATUS [00:00] */
-#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET0_STATUS_GENET0_CLK_250_CLOCK_ENABLE_GENET0_STATUS_MASK 0x00000001
-#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET0_STATUS_GENET0_CLK_250_CLOCK_ENABLE_GENET0_STATUS_SHIFT 0
-
-/***************************************************************************
- *DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET1 - Dual genet top dual rgmii inst clock enable genet1
- ***************************************************************************/
-/* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET1 :: reserved0 [31:09] */
-#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET1_reserved0_MASK 0xfffffe00
-#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET1_reserved0_SHIFT 9
-
-/* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET1 :: GENET1_UNIMAC_SYS_TX_CLOCK_ENABLE_GENET1 [08:08] */
-#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET1_GENET1_UNIMAC_SYS_TX_CLOCK_ENABLE_GENET1_MASK 0x00000100
-#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET1_GENET1_UNIMAC_SYS_TX_CLOCK_ENABLE_GENET1_SHIFT 8
-#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET1_GENET1_UNIMAC_SYS_TX_CLOCK_ENABLE_GENET1_DEFAULT 0x00000001
-
-/* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET1 :: GENET1_UNIMAC_SYS_RX_CLOCK_ENABLE_GENET1 [07:07] */
-#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET1_GENET1_UNIMAC_SYS_RX_CLOCK_ENABLE_GENET1_MASK 0x00000080
-#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET1_GENET1_UNIMAC_SYS_RX_CLOCK_ENABLE_GENET1_SHIFT 7
-#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET1_GENET1_UNIMAC_SYS_RX_CLOCK_ENABLE_GENET1_DEFAULT 0x00000001
-
-/* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET1 :: GENET1_SCB_CLOCK_ENABLE_GENET1 [06:06] */
-#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET1_GENET1_SCB_CLOCK_ENABLE_GENET1_MASK 0x00000040
-#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET1_GENET1_SCB_CLOCK_ENABLE_GENET1_SHIFT 6
-#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET1_GENET1_SCB_CLOCK_ENABLE_GENET1_DEFAULT 0x00000001
-
-/* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET1 :: GENET1_L2INTR_CLOCK_ENABLE_GENET1 [05:05] */
-#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET1_GENET1_L2INTR_CLOCK_ENABLE_GENET1_MASK 0x00000020
-#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET1_GENET1_L2INTR_CLOCK_ENABLE_GENET1_SHIFT 5
-#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET1_GENET1_L2INTR_CLOCK_ENABLE_GENET1_DEFAULT 0x00000001
-
-/* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET1 :: GENET1_HFB_CLOCK_ENABLE_GENET1 [04:04] */
-#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET1_GENET1_HFB_CLOCK_ENABLE_GENET1_MASK 0x00000010
-#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET1_GENET1_HFB_CLOCK_ENABLE_GENET1_SHIFT 4
-#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET1_GENET1_HFB_CLOCK_ENABLE_GENET1_DEFAULT 0x00000001
-
-/* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET1 :: GENET1_GMII_CLOCK_ENABLE_GENET1 [03:03] */
-#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET1_GENET1_GMII_CLOCK_ENABLE_GENET1_MASK 0x00000008
-#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET1_GENET1_GMII_CLOCK_ENABLE_GENET1_SHIFT 3
-#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET1_GENET1_GMII_CLOCK_ENABLE_GENET1_DEFAULT 0x00000001
-
-/* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET1 :: GENET1_GISB_CLOCK_ENABLE_GENET1 [02:02] */
-#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET1_GENET1_GISB_CLOCK_ENABLE_GENET1_MASK 0x00000004
-#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET1_GENET1_GISB_CLOCK_ENABLE_GENET1_SHIFT 2
-#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET1_GENET1_GISB_CLOCK_ENABLE_GENET1_DEFAULT 0x00000001
-
-/* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET1 :: GENET1_EEE_CLOCK_ENABLE_GENET1 [01:01] */
-#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET1_GENET1_EEE_CLOCK_ENABLE_GENET1_MASK 0x00000002
-#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET1_GENET1_EEE_CLOCK_ENABLE_GENET1_SHIFT 1
-#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET1_GENET1_EEE_CLOCK_ENABLE_GENET1_DEFAULT 0x00000001
-
-/* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET1 :: GENET1_CLK_250_CLOCK_ENABLE_GENET1 [00:00] */
-#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET1_GENET1_CLK_250_CLOCK_ENABLE_GENET1_MASK 0x00000001
-#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET1_GENET1_CLK_250_CLOCK_ENABLE_GENET1_SHIFT 0
-#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET1_GENET1_CLK_250_CLOCK_ENABLE_GENET1_DEFAULT 0x00000001
-
-/***************************************************************************
- *DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET1_STATUS - Clock Enable Status
- ***************************************************************************/
-/* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET1_STATUS :: reserved0 [31:09] */
-#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET1_STATUS_reserved0_MASK 0xfffffe00
-#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET1_STATUS_reserved0_SHIFT 9
-
-/* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET1_STATUS :: GENET1_UNIMAC_SYS_TX_CLOCK_ENABLE_GENET1_STATUS [08:08] */
-#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET1_STATUS_GENET1_UNIMAC_SYS_TX_CLOCK_ENABLE_GENET1_STATUS_MASK 0x00000100
-#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET1_STATUS_GENET1_UNIMAC_SYS_TX_CLOCK_ENABLE_GENET1_STATUS_SHIFT 8
-
-/* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET1_STATUS :: GENET1_UNIMAC_SYS_RX_CLOCK_ENABLE_GENET1_STATUS [07:07] */
-#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET1_STATUS_GENET1_UNIMAC_SYS_RX_CLOCK_ENABLE_GENET1_STATUS_MASK 0x00000080
-#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET1_STATUS_GENET1_UNIMAC_SYS_RX_CLOCK_ENABLE_GENET1_STATUS_SHIFT 7
-
-/* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET1_STATUS :: GENET1_SCB_CLOCK_ENABLE_GENET1_STATUS [06:06] */
-#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET1_STATUS_GENET1_SCB_CLOCK_ENABLE_GENET1_STATUS_MASK 0x00000040
-#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET1_STATUS_GENET1_SCB_CLOCK_ENABLE_GENET1_STATUS_SHIFT 6
-
-/* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET1_STATUS :: GENET1_L2INTR_CLOCK_ENABLE_GENET1_STATUS [05:05] */
-#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET1_STATUS_GENET1_L2INTR_CLOCK_ENABLE_GENET1_STATUS_MASK 0x00000020
-#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET1_STATUS_GENET1_L2INTR_CLOCK_ENABLE_GENET1_STATUS_SHIFT 5
-
-/* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET1_STATUS :: GENET1_HFB_CLOCK_ENABLE_GENET1_STATUS [04:04] */
-#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET1_STATUS_GENET1_HFB_CLOCK_ENABLE_GENET1_STATUS_MASK 0x00000010
-#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET1_STATUS_GENET1_HFB_CLOCK_ENABLE_GENET1_STATUS_SHIFT 4
-
-/* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET1_STATUS :: GENET1_GMII_CLOCK_ENABLE_GENET1_STATUS [03:03] */
-#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET1_STATUS_GENET1_GMII_CLOCK_ENABLE_GENET1_STATUS_MASK 0x00000008
-#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET1_STATUS_GENET1_GMII_CLOCK_ENABLE_GENET1_STATUS_SHIFT 3
-
-/* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET1_STATUS :: GENET1_GISB_CLOCK_ENABLE_GENET1_STATUS [02:02] */
-#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET1_STATUS_GENET1_GISB_CLOCK_ENABLE_GENET1_STATUS_MASK 0x00000004
-#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET1_STATUS_GENET1_GISB_CLOCK_ENABLE_GENET1_STATUS_SHIFT 2
-
-/* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET1_STATUS :: GENET1_EEE_CLOCK_ENABLE_GENET1_STATUS [01:01] */
-#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET1_STATUS_GENET1_EEE_CLOCK_ENABLE_GENET1_STATUS_MASK 0x00000002
-#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET1_STATUS_GENET1_EEE_CLOCK_ENABLE_GENET1_STATUS_SHIFT 1
-
-/* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET1_STATUS :: GENET1_CLK_250_CLOCK_ENABLE_GENET1_STATUS [00:00] */
-#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET1_STATUS_GENET1_CLK_250_CLOCK_ENABLE_GENET1_STATUS_MASK 0x00000001
-#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET1_STATUS_GENET1_CLK_250_CLOCK_ENABLE_GENET1_STATUS_SHIFT 0
-
-/***************************************************************************
- *DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET2 - Dual genet top dual rgmii inst clock enable genet2
- ***************************************************************************/
-/* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET2 :: reserved0 [31:02] */
-#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET2_reserved0_MASK 0xfffffffc
-#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET2_reserved0_SHIFT 2
-
-/* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET2 :: GENET2_SCB_CLOCK_ENABLE_GENET2 [01:01] */
-#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET2_GENET2_SCB_CLOCK_ENABLE_GENET2_MASK 0x00000002
-#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET2_GENET2_SCB_CLOCK_ENABLE_GENET2_SHIFT 1
-#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET2_GENET2_SCB_CLOCK_ENABLE_GENET2_DEFAULT 0x00000001
-
-/* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET2 :: GENET2_GISB_CLOCK_ENABLE_GENET2 [00:00] */
-#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET2_GENET2_GISB_CLOCK_ENABLE_GENET2_MASK 0x00000001
-#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET2_GENET2_GISB_CLOCK_ENABLE_GENET2_SHIFT 0
-#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET2_GENET2_GISB_CLOCK_ENABLE_GENET2_DEFAULT 0x00000001
-
-/***************************************************************************
- *DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET2_STATUS - Clock Enable Status
- ***************************************************************************/
-/* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET2_STATUS :: reserved0 [31:02] */
-#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET2_STATUS_reserved0_MASK 0xfffffffc
-#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET2_STATUS_reserved0_SHIFT 2
-
-/* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET2_STATUS :: GENET2_SCB_CLOCK_ENABLE_GENET2_STATUS [01:01] */
-#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET2_STATUS_GENET2_SCB_CLOCK_ENABLE_GENET2_STATUS_MASK 0x00000002
-#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET2_STATUS_GENET2_SCB_CLOCK_ENABLE_GENET2_STATUS_SHIFT 1
-
-/* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET2_STATUS :: GENET2_GISB_CLOCK_ENABLE_GENET2_STATUS [00:00] */
-#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET2_STATUS_GENET2_GISB_CLOCK_ENABLE_GENET2_STATUS_MASK 0x00000001
-#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET2_STATUS_GENET2_GISB_CLOCK_ENABLE_GENET2_STATUS_SHIFT 0
-
-/***************************************************************************
- *DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_STATUS - Clock Enable Status
- ***************************************************************************/
-/* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_STATUS :: reserved0 [31:02] */
-#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_STATUS_reserved0_MASK 0xfffffffc
-#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_STATUS_reserved0_SHIFT 2
-
-/* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_STATUS :: GENET_SCB_CLOCK_ENABLE_STATUS [01:01] */
-#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_STATUS_GENET_SCB_CLOCK_ENABLE_STATUS_MASK 0x00000002
-#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_STATUS_GENET_SCB_CLOCK_ENABLE_STATUS_SHIFT 1
-
-/* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_STATUS :: GENET_54_CLOCK_ENABLE_STATUS [00:00] */
-#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_STATUS_GENET_54_CLOCK_ENABLE_STATUS_MASK 0x00000001
-#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_STATUS_GENET_54_CLOCK_ENABLE_STATUS_SHIFT 0
-
-/***************************************************************************
- *DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_SELECT_GENET0 - Dual genet top dual rgmii inst clock select genet0
- ***************************************************************************/
-/* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_SELECT_GENET0 :: reserved0 [31:02] */
-#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_SELECT_GENET0_reserved0_MASK 0xfffffffc
-#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_SELECT_GENET0_reserved0_SHIFT 2
-
-/* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_SELECT_GENET0 :: GENET0_GMII_CLOCK_SELECT_GENET0 [01:01] */
-#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_SELECT_GENET0_GENET0_GMII_CLOCK_SELECT_GENET0_MASK 0x00000002
-#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_SELECT_GENET0_GENET0_GMII_CLOCK_SELECT_GENET0_SHIFT 1
-#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_SELECT_GENET0_GENET0_GMII_CLOCK_SELECT_GENET0_DEFAULT 0x00000000
-
-/* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_SELECT_GENET0 :: GENET0_CLOCK_SELECT_GENET0 [00:00] */
-#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_SELECT_GENET0_GENET0_CLOCK_SELECT_GENET0_MASK 0x00000001
-#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_SELECT_GENET0_GENET0_CLOCK_SELECT_GENET0_SHIFT 0
-#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_SELECT_GENET0_GENET0_CLOCK_SELECT_GENET0_DEFAULT 0x00000000
-
-/***************************************************************************
- *DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_SELECT_GENET1 - Dual genet top dual rgmii inst clock select genet1
- ***************************************************************************/
-/* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_SELECT_GENET1 :: reserved0 [31:02] */
-#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_SELECT_GENET1_reserved0_MASK 0xfffffffc
-#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_SELECT_GENET1_reserved0_SHIFT 2
-
-/* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_SELECT_GENET1 :: GENET1_GMII_CLOCK_SELECT_GENET1 [01:01] */
-#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_SELECT_GENET1_GENET1_GMII_CLOCK_SELECT_GENET1_MASK 0x00000002
-#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_SELECT_GENET1_GENET1_GMII_CLOCK_SELECT_GENET1_SHIFT 1
-#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_SELECT_GENET1_GENET1_GMII_CLOCK_SELECT_GENET1_DEFAULT 0x00000000
-
-/* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_SELECT_GENET1 :: GENET1_CLOCK_SELECT_GENET1 [00:00] */
-#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_SELECT_GENET1_GENET1_CLOCK_SELECT_GENET1_MASK 0x00000001
-#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_SELECT_GENET1_GENET1_CLOCK_SELECT_GENET1_SHIFT 0
-#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_SELECT_GENET1_GENET1_CLOCK_SELECT_GENET1_DEFAULT 0x00000000
-
-/***************************************************************************
- *DUAL_GENET_TOP_DUAL_RGMII_INST_OBSERVE_CLOCK - Dual genet top dual rgmii inst observe clock
- ***************************************************************************/
-/* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_INST_OBSERVE_CLOCK :: reserved0 [31:06] */
-#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_OBSERVE_CLOCK_reserved0_MASK 0xffffffc0
-#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_OBSERVE_CLOCK_reserved0_SHIFT 6
-
-/* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_INST_OBSERVE_CLOCK :: GENET_ENABLE_OBSERVE_CLOCK [05:05] */
-#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_OBSERVE_CLOCK_GENET_ENABLE_OBSERVE_CLOCK_MASK 0x00000020
-#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_OBSERVE_CLOCK_GENET_ENABLE_OBSERVE_CLOCK_SHIFT 5
-#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_OBSERVE_CLOCK_GENET_ENABLE_OBSERVE_CLOCK_DEFAULT 0x00000000
-
-/* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_INST_OBSERVE_CLOCK :: GENET_ENABLE_DIVIDER_OBSERVE_CLOCK [04:04] */
-#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_OBSERVE_CLOCK_GENET_ENABLE_DIVIDER_OBSERVE_CLOCK_MASK 0x00000010
-#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_OBSERVE_CLOCK_GENET_ENABLE_DIVIDER_OBSERVE_CLOCK_SHIFT 4
-#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_OBSERVE_CLOCK_GENET_ENABLE_DIVIDER_OBSERVE_CLOCK_DEFAULT 0x00000000
-
-/* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_INST_OBSERVE_CLOCK :: GENET_CONTROL_OBSERVE_CLOCK [03:00] */
-#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_OBSERVE_CLOCK_GENET_CONTROL_OBSERVE_CLOCK_MASK 0x0000000f
-#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_OBSERVE_CLOCK_GENET_CONTROL_OBSERVE_CLOCK_SHIFT 0
-#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_OBSERVE_CLOCK_GENET_CONTROL_OBSERVE_CLOCK_DEFAULT 0x00000000
-
-/***************************************************************************
- *DVP_HR_INST_CLOCK_DISABLE - Disable DVP_HR_INST's clocks
- ***************************************************************************/
-/* CLKGEN :: DVP_HR_INST_CLOCK_DISABLE :: reserved0 [31:01] */
-#define BCHP_CLKGEN_DVP_HR_INST_CLOCK_DISABLE_reserved0_MASK 0xfffffffe
-#define BCHP_CLKGEN_DVP_HR_INST_CLOCK_DISABLE_reserved0_SHIFT 1
-
-/* CLKGEN :: DVP_HR_INST_CLOCK_DISABLE :: DISABLE_DVPHR_ALWAYSON_CLOCK [00:00] */
-#define BCHP_CLKGEN_DVP_HR_INST_CLOCK_DISABLE_DISABLE_DVPHR_ALWAYSON_CLOCK_MASK 0x00000001
-#define BCHP_CLKGEN_DVP_HR_INST_CLOCK_DISABLE_DISABLE_DVPHR_ALWAYSON_CLOCK_SHIFT 0
-#define BCHP_CLKGEN_DVP_HR_INST_CLOCK_DISABLE_DISABLE_DVPHR_ALWAYSON_CLOCK_DEFAULT 0x00000000
-
-/***************************************************************************
- *DVP_HR_INST_CLOCK_DISABLE_STATUS - Clock Disable Status
- ***************************************************************************/
-/* CLKGEN :: DVP_HR_INST_CLOCK_DISABLE_STATUS :: reserved0 [31:01] */
-#define BCHP_CLKGEN_DVP_HR_INST_CLOCK_DISABLE_STATUS_reserved0_MASK 0xfffffffe
-#define BCHP_CLKGEN_DVP_HR_INST_CLOCK_DISABLE_STATUS_reserved0_SHIFT 1
-
-/* CLKGEN :: DVP_HR_INST_CLOCK_DISABLE_STATUS :: DISABLE_DVPHR_ALWAYSON_CLOCK_STATUS [00:00] */
-#define BCHP_CLKGEN_DVP_HR_INST_CLOCK_DISABLE_STATUS_DISABLE_DVPHR_ALWAYSON_CLOCK_STATUS_MASK 0x00000001
-#define BCHP_CLKGEN_DVP_HR_INST_CLOCK_DISABLE_STATUS_DISABLE_DVPHR_ALWAYSON_CLOCK_STATUS_SHIFT 0
-
-/***************************************************************************
- *DVP_HR_INST_CLOCK_ENABLE - Dvp hr inst clock enable
- ***************************************************************************/
-/* CLKGEN :: DVP_HR_INST_CLOCK_ENABLE :: reserved0 [31:03] */
-#define BCHP_CLKGEN_DVP_HR_INST_CLOCK_ENABLE_reserved0_MASK 0xfffffff8
-#define BCHP_CLKGEN_DVP_HR_INST_CLOCK_ENABLE_reserved0_SHIFT 3
-
-/* CLKGEN :: DVP_HR_INST_CLOCK_ENABLE :: DVPHR_HD_DVI_CLOCK_ENABLE [02:02] */
-#define BCHP_CLKGEN_DVP_HR_INST_CLOCK_ENABLE_DVPHR_HD_DVI_CLOCK_ENABLE_MASK 0x00000004
-#define BCHP_CLKGEN_DVP_HR_INST_CLOCK_ENABLE_DVPHR_HD_DVI_CLOCK_ENABLE_SHIFT 2
-#define BCHP_CLKGEN_DVP_HR_INST_CLOCK_ENABLE_DVPHR_HD_DVI_CLOCK_ENABLE_DEFAULT 0x00000001
-
-/* CLKGEN :: DVP_HR_INST_CLOCK_ENABLE :: DVPHR_BVB_324_CLOCK_ENABLE [01:01] */
-#define BCHP_CLKGEN_DVP_HR_INST_CLOCK_ENABLE_DVPHR_BVB_324_CLOCK_ENABLE_MASK 0x00000002
-#define BCHP_CLKGEN_DVP_HR_INST_CLOCK_ENABLE_DVPHR_BVB_324_CLOCK_ENABLE_SHIFT 1
-#define BCHP_CLKGEN_DVP_HR_INST_CLOCK_ENABLE_DVPHR_BVB_324_CLOCK_ENABLE_DEFAULT 0x00000001
-
-/* CLKGEN :: DVP_HR_INST_CLOCK_ENABLE :: DVPHR_54_CLOCK_ENABLE [00:00] */
-#define BCHP_CLKGEN_DVP_HR_INST_CLOCK_ENABLE_DVPHR_54_CLOCK_ENABLE_MASK 0x00000001
-#define BCHP_CLKGEN_DVP_HR_INST_CLOCK_ENABLE_DVPHR_54_CLOCK_ENABLE_SHIFT 0
-#define BCHP_CLKGEN_DVP_HR_INST_CLOCK_ENABLE_DVPHR_54_CLOCK_ENABLE_DEFAULT 0x00000001
-
-/***************************************************************************
- *DVP_HR_INST_CLOCK_ENABLE0 - Dvp hr inst clock enable0
- ***************************************************************************/
-/* CLKGEN :: DVP_HR_INST_CLOCK_ENABLE0 :: reserved0 [31:01] */
-#define BCHP_CLKGEN_DVP_HR_INST_CLOCK_ENABLE0_reserved0_MASK 0xfffffffe
-#define BCHP_CLKGEN_DVP_HR_INST_CLOCK_ENABLE0_reserved0_SHIFT 1
-
-/* CLKGEN :: DVP_HR_INST_CLOCK_ENABLE0 :: DVPHR_108_CLOCK_ENABLE0 [00:00] */
-#define BCHP_CLKGEN_DVP_HR_INST_CLOCK_ENABLE0_DVPHR_108_CLOCK_ENABLE0_MASK 0x00000001
-#define BCHP_CLKGEN_DVP_HR_INST_CLOCK_ENABLE0_DVPHR_108_CLOCK_ENABLE0_SHIFT 0
-#define BCHP_CLKGEN_DVP_HR_INST_CLOCK_ENABLE0_DVPHR_108_CLOCK_ENABLE0_DEFAULT 0x00000001
-
-/***************************************************************************
- *DVP_HR_INST_CLOCK_ENABLE0_STATUS - Clock Enable Status
- ***************************************************************************/
-/* CLKGEN :: DVP_HR_INST_CLOCK_ENABLE0_STATUS :: reserved0 [31:01] */
-#define BCHP_CLKGEN_DVP_HR_INST_CLOCK_ENABLE0_STATUS_reserved0_MASK 0xfffffffe
-#define BCHP_CLKGEN_DVP_HR_INST_CLOCK_ENABLE0_STATUS_reserved0_SHIFT 1
-
-/* CLKGEN :: DVP_HR_INST_CLOCK_ENABLE0_STATUS :: DVPHR_108_CLOCK_ENABLE0_STATUS [00:00] */
-#define BCHP_CLKGEN_DVP_HR_INST_CLOCK_ENABLE0_STATUS_DVPHR_108_CLOCK_ENABLE0_STATUS_MASK 0x00000001
-#define BCHP_CLKGEN_DVP_HR_INST_CLOCK_ENABLE0_STATUS_DVPHR_108_CLOCK_ENABLE0_STATUS_SHIFT 0
-
-/***************************************************************************
- *DVP_HR_INST_CLOCK_ENABLE_STATUS - Clock Enable Status
- ***************************************************************************/
-/* CLKGEN :: DVP_HR_INST_CLOCK_ENABLE_STATUS :: reserved0 [31:03] */
-#define BCHP_CLKGEN_DVP_HR_INST_CLOCK_ENABLE_STATUS_reserved0_MASK 0xfffffff8
-#define BCHP_CLKGEN_DVP_HR_INST_CLOCK_ENABLE_STATUS_reserved0_SHIFT 3
-
-/* CLKGEN :: DVP_HR_INST_CLOCK_ENABLE_STATUS :: DVPHR_HD_DVI_CLOCK_ENABLE_STATUS [02:02] */
-#define BCHP_CLKGEN_DVP_HR_INST_CLOCK_ENABLE_STATUS_DVPHR_HD_DVI_CLOCK_ENABLE_STATUS_MASK 0x00000004
-#define BCHP_CLKGEN_DVP_HR_INST_CLOCK_ENABLE_STATUS_DVPHR_HD_DVI_CLOCK_ENABLE_STATUS_SHIFT 2
-
-/* CLKGEN :: DVP_HR_INST_CLOCK_ENABLE_STATUS :: DVPHR_BVB_324_CLOCK_ENABLE_STATUS [01:01] */
-#define BCHP_CLKGEN_DVP_HR_INST_CLOCK_ENABLE_STATUS_DVPHR_BVB_324_CLOCK_ENABLE_STATUS_MASK 0x00000002
-#define BCHP_CLKGEN_DVP_HR_INST_CLOCK_ENABLE_STATUS_DVPHR_BVB_324_CLOCK_ENABLE_STATUS_SHIFT 1
-
-/* CLKGEN :: DVP_HR_INST_CLOCK_ENABLE_STATUS :: DVPHR_54_CLOCK_ENABLE_STATUS [00:00] */
-#define BCHP_CLKGEN_DVP_HR_INST_CLOCK_ENABLE_STATUS_DVPHR_54_CLOCK_ENABLE_STATUS_MASK 0x00000001
-#define BCHP_CLKGEN_DVP_HR_INST_CLOCK_ENABLE_STATUS_DVPHR_54_CLOCK_ENABLE_STATUS_SHIFT 0
-
-/***************************************************************************
- *DVP_HR_INST_OBSERVE_CLOCK - Dvp hr inst observe clock
- ***************************************************************************/
-/* CLKGEN :: DVP_HR_INST_OBSERVE_CLOCK :: reserved0 [31:06] */
-#define BCHP_CLKGEN_DVP_HR_INST_OBSERVE_CLOCK_reserved0_MASK 0xffffffc0
-#define BCHP_CLKGEN_DVP_HR_INST_OBSERVE_CLOCK_reserved0_SHIFT 6
-
-/* CLKGEN :: DVP_HR_INST_OBSERVE_CLOCK :: DVPHR_ENABLE_OBSERVE_CLOCK [05:05] */
-#define BCHP_CLKGEN_DVP_HR_INST_OBSERVE_CLOCK_DVPHR_ENABLE_OBSERVE_CLOCK_MASK 0x00000020
-#define BCHP_CLKGEN_DVP_HR_INST_OBSERVE_CLOCK_DVPHR_ENABLE_OBSERVE_CLOCK_SHIFT 5
-#define BCHP_CLKGEN_DVP_HR_INST_OBSERVE_CLOCK_DVPHR_ENABLE_OBSERVE_CLOCK_DEFAULT 0x00000000
-
-/* CLKGEN :: DVP_HR_INST_OBSERVE_CLOCK :: DVPHR_ENABLE_DIVIDER_OBSERVE_CLOCK [04:04] */
-#define BCHP_CLKGEN_DVP_HR_INST_OBSERVE_CLOCK_DVPHR_ENABLE_DIVIDER_OBSERVE_CLOCK_MASK 0x00000010
-#define BCHP_CLKGEN_DVP_HR_INST_OBSERVE_CLOCK_DVPHR_ENABLE_DIVIDER_OBSERVE_CLOCK_SHIFT 4
-#define BCHP_CLKGEN_DVP_HR_INST_OBSERVE_CLOCK_DVPHR_ENABLE_DIVIDER_OBSERVE_CLOCK_DEFAULT 0x00000000
-
-/* CLKGEN :: DVP_HR_INST_OBSERVE_CLOCK :: DVPHR_CONTROL_OBSERVE_CLOCK [03:00] */
-#define BCHP_CLKGEN_DVP_HR_INST_OBSERVE_CLOCK_DVPHR_CONTROL_OBSERVE_CLOCK_MASK 0x0000000f
-#define BCHP_CLKGEN_DVP_HR_INST_OBSERVE_CLOCK_DVPHR_CONTROL_OBSERVE_CLOCK_SHIFT 0
-#define BCHP_CLKGEN_DVP_HR_INST_OBSERVE_CLOCK_DVPHR_CONTROL_OBSERVE_CLOCK_DEFAULT 0x00000000
-
-/***************************************************************************
- *DVP_HT_DUAL_WRAPPER_INST_CLOCK_DISABLE - Disable DVP_HT_DUAL_WRAPPER_INST's clocks
- ***************************************************************************/
-/* CLKGEN :: DVP_HT_DUAL_WRAPPER_INST_CLOCK_DISABLE :: reserved0 [31:01] */
-#define BCHP_CLKGEN_DVP_HT_DUAL_WRAPPER_INST_CLOCK_DISABLE_reserved0_MASK 0xfffffffe
-#define BCHP_CLKGEN_DVP_HT_DUAL_WRAPPER_INST_CLOCK_DISABLE_reserved0_SHIFT 1
-
-/* CLKGEN :: DVP_HT_DUAL_WRAPPER_INST_CLOCK_DISABLE :: DISABLE_DVPHT_IIC_MASTER_CLOCK [00:00] */
-#define BCHP_CLKGEN_DVP_HT_DUAL_WRAPPER_INST_CLOCK_DISABLE_DISABLE_DVPHT_IIC_MASTER_CLOCK_MASK 0x00000001
-#define BCHP_CLKGEN_DVP_HT_DUAL_WRAPPER_INST_CLOCK_DISABLE_DISABLE_DVPHT_IIC_MASTER_CLOCK_SHIFT 0
-#define BCHP_CLKGEN_DVP_HT_DUAL_WRAPPER_INST_CLOCK_DISABLE_DISABLE_DVPHT_IIC_MASTER_CLOCK_DEFAULT 0x00000000
-
-/***************************************************************************
- *DVP_HT_DUAL_WRAPPER_INST_CLOCK_DISABLE_STATUS - Clock Disable Status
- ***************************************************************************/
-/* CLKGEN :: DVP_HT_DUAL_WRAPPER_INST_CLOCK_DISABLE_STATUS :: reserved0 [31:01] */
-#define BCHP_CLKGEN_DVP_HT_DUAL_WRAPPER_INST_CLOCK_DISABLE_STATUS_reserved0_MASK 0xfffffffe
-#define BCHP_CLKGEN_DVP_HT_DUAL_WRAPPER_INST_CLOCK_DISABLE_STATUS_reserved0_SHIFT 1
-
-/* CLKGEN :: DVP_HT_DUAL_WRAPPER_INST_CLOCK_DISABLE_STATUS :: DISABLE_DVPHT_IIC_MASTER_CLOCK_STATUS [00:00] */
-#define BCHP_CLKGEN_DVP_HT_DUAL_WRAPPER_INST_CLOCK_DISABLE_STATUS_DISABLE_DVPHT_IIC_MASTER_CLOCK_STATUS_MASK 0x00000001
-#define BCHP_CLKGEN_DVP_HT_DUAL_WRAPPER_INST_CLOCK_DISABLE_STATUS_DISABLE_DVPHT_IIC_MASTER_CLOCK_STATUS_SHIFT 0
-
-/***************************************************************************
- *DVP_HT_DUAL_WRAPPER_INST_CLOCK_ENABLE - Dvp ht dual wrapper inst clock enable
- ***************************************************************************/
-/* CLKGEN :: DVP_HT_DUAL_WRAPPER_INST_CLOCK_ENABLE :: reserved0 [31:04] */
-#define BCHP_CLKGEN_DVP_HT_DUAL_WRAPPER_INST_CLOCK_ENABLE_reserved0_MASK 0xfffffff0
-#define BCHP_CLKGEN_DVP_HT_DUAL_WRAPPER_INST_CLOCK_ENABLE_reserved0_SHIFT 4
-
-/* CLKGEN :: DVP_HT_DUAL_WRAPPER_INST_CLOCK_ENABLE :: DVPHT_54_CLOCK_ENABLE [03:03] */
-#define BCHP_CLKGEN_DVP_HT_DUAL_WRAPPER_INST_CLOCK_ENABLE_DVPHT_54_CLOCK_ENABLE_MASK 0x00000008
-#define BCHP_CLKGEN_DVP_HT_DUAL_WRAPPER_INST_CLOCK_ENABLE_DVPHT_54_CLOCK_ENABLE_SHIFT 3
-#define BCHP_CLKGEN_DVP_HT_DUAL_WRAPPER_INST_CLOCK_ENABLE_DVPHT_54_CLOCK_ENABLE_DEFAULT 0x00000001
-
-/* CLKGEN :: DVP_HT_DUAL_WRAPPER_INST_CLOCK_ENABLE :: DVPHT_1_54_CLOCK_ENABLE [02:02] */
-#define BCHP_CLKGEN_DVP_HT_DUAL_WRAPPER_INST_CLOCK_ENABLE_DVPHT_1_54_CLOCK_ENABLE_MASK 0x00000004
-#define BCHP_CLKGEN_DVP_HT_DUAL_WRAPPER_INST_CLOCK_ENABLE_DVPHT_1_54_CLOCK_ENABLE_SHIFT 2
-#define BCHP_CLKGEN_DVP_HT_DUAL_WRAPPER_INST_CLOCK_ENABLE_DVPHT_1_54_CLOCK_ENABLE_DEFAULT 0x00000001
-
-/* CLKGEN :: DVP_HT_DUAL_WRAPPER_INST_CLOCK_ENABLE :: DVPHT_1_108_CLOCK_ENABLE [01:01] */
-#define BCHP_CLKGEN_DVP_HT_DUAL_WRAPPER_INST_CLOCK_ENABLE_DVPHT_1_108_CLOCK_ENABLE_MASK 0x00000002
-#define BCHP_CLKGEN_DVP_HT_DUAL_WRAPPER_INST_CLOCK_ENABLE_DVPHT_1_108_CLOCK_ENABLE_SHIFT 1
-#define BCHP_CLKGEN_DVP_HT_DUAL_WRAPPER_INST_CLOCK_ENABLE_DVPHT_1_108_CLOCK_ENABLE_DEFAULT 0x00000001
-
-/* CLKGEN :: DVP_HT_DUAL_WRAPPER_INST_CLOCK_ENABLE :: DVPHT_108_CLOCK_ENABLE [00:00] */
-#define BCHP_CLKGEN_DVP_HT_DUAL_WRAPPER_INST_CLOCK_ENABLE_DVPHT_108_CLOCK_ENABLE_MASK 0x00000001
-#define BCHP_CLKGEN_DVP_HT_DUAL_WRAPPER_INST_CLOCK_ENABLE_DVPHT_108_CLOCK_ENABLE_SHIFT 0
-#define BCHP_CLKGEN_DVP_HT_DUAL_WRAPPER_INST_CLOCK_ENABLE_DVPHT_108_CLOCK_ENABLE_DEFAULT 0x00000001
-
-/***************************************************************************
- *DVP_HT_DUAL_WRAPPER_INST_CLOCK_ENABLE_STATUS - Clock Enable Status
- ***************************************************************************/
-/* CLKGEN :: DVP_HT_DUAL_WRAPPER_INST_CLOCK_ENABLE_STATUS :: reserved0 [31:04] */
-#define BCHP_CLKGEN_DVP_HT_DUAL_WRAPPER_INST_CLOCK_ENABLE_STATUS_reserved0_MASK 0xfffffff0
-#define BCHP_CLKGEN_DVP_HT_DUAL_WRAPPER_INST_CLOCK_ENABLE_STATUS_reserved0_SHIFT 4
-
-/* CLKGEN :: DVP_HT_DUAL_WRAPPER_INST_CLOCK_ENABLE_STATUS :: DVPHT_54_CLOCK_ENABLE_STATUS [03:03] */
-#define BCHP_CLKGEN_DVP_HT_DUAL_WRAPPER_INST_CLOCK_ENABLE_STATUS_DVPHT_54_CLOCK_ENABLE_STATUS_MASK 0x00000008
-#define BCHP_CLKGEN_DVP_HT_DUAL_WRAPPER_INST_CLOCK_ENABLE_STATUS_DVPHT_54_CLOCK_ENABLE_STATUS_SHIFT 3
-
-/* CLKGEN :: DVP_HT_DUAL_WRAPPER_INST_CLOCK_ENABLE_STATUS :: DVPHT_1_54_CLOCK_ENABLE_STATUS [02:02] */
-#define BCHP_CLKGEN_DVP_HT_DUAL_WRAPPER_INST_CLOCK_ENABLE_STATUS_DVPHT_1_54_CLOCK_ENABLE_STATUS_MASK 0x00000004
-#define BCHP_CLKGEN_DVP_HT_DUAL_WRAPPER_INST_CLOCK_ENABLE_STATUS_DVPHT_1_54_CLOCK_ENABLE_STATUS_SHIFT 2
-
-/* CLKGEN :: DVP_HT_DUAL_WRAPPER_INST_CLOCK_ENABLE_STATUS :: DVPHT_1_108_CLOCK_ENABLE_STATUS [01:01] */
-#define BCHP_CLKGEN_DVP_HT_DUAL_WRAPPER_INST_CLOCK_ENABLE_STATUS_DVPHT_1_108_CLOCK_ENABLE_STATUS_MASK 0x00000002
-#define BCHP_CLKGEN_DVP_HT_DUAL_WRAPPER_INST_CLOCK_ENABLE_STATUS_DVPHT_1_108_CLOCK_ENABLE_STATUS_SHIFT 1
-
-/* CLKGEN :: DVP_HT_DUAL_WRAPPER_INST_CLOCK_ENABLE_STATUS :: DVPHT_108_CLOCK_ENABLE_STATUS [00:00] */
-#define BCHP_CLKGEN_DVP_HT_DUAL_WRAPPER_INST_CLOCK_ENABLE_STATUS_DVPHT_108_CLOCK_ENABLE_STATUS_MASK 0x00000001
-#define BCHP_CLKGEN_DVP_HT_DUAL_WRAPPER_INST_CLOCK_ENABLE_STATUS_DVPHT_108_CLOCK_ENABLE_STATUS_SHIFT 0
-
-/***************************************************************************
- *DVP_HT_DUAL_WRAPPER_INST_ENABLE - Dvp ht dual wrapper inst enable
- ***************************************************************************/
-/* CLKGEN :: DVP_HT_DUAL_WRAPPER_INST_ENABLE :: reserved0 [31:04] */
-#define BCHP_CLKGEN_DVP_HT_DUAL_WRAPPER_INST_ENABLE_reserved0_MASK 0xfffffff0
-#define BCHP_CLKGEN_DVP_HT_DUAL_WRAPPER_INST_ENABLE_reserved0_SHIFT 4
-
-/* CLKGEN :: DVP_HT_DUAL_WRAPPER_INST_ENABLE :: DVPHT_CLK_VEC_ENABLE [03:03] */
-#define BCHP_CLKGEN_DVP_HT_DUAL_WRAPPER_INST_ENABLE_DVPHT_CLK_VEC_ENABLE_MASK 0x00000008
-#define BCHP_CLKGEN_DVP_HT_DUAL_WRAPPER_INST_ENABLE_DVPHT_CLK_VEC_ENABLE_SHIFT 3
-#define BCHP_CLKGEN_DVP_HT_DUAL_WRAPPER_INST_ENABLE_DVPHT_CLK_VEC_ENABLE_DEFAULT 0x00000001
-
-/* CLKGEN :: DVP_HT_DUAL_WRAPPER_INST_ENABLE :: DVPHT_CLK_MAX_ENABLE [02:02] */
-#define BCHP_CLKGEN_DVP_HT_DUAL_WRAPPER_INST_ENABLE_DVPHT_CLK_MAX_ENABLE_MASK 0x00000004
-#define BCHP_CLKGEN_DVP_HT_DUAL_WRAPPER_INST_ENABLE_DVPHT_CLK_MAX_ENABLE_SHIFT 2
-#define BCHP_CLKGEN_DVP_HT_DUAL_WRAPPER_INST_ENABLE_DVPHT_CLK_MAX_ENABLE_DEFAULT 0x00000001
-
-/* CLKGEN :: DVP_HT_DUAL_WRAPPER_INST_ENABLE :: DVPHT_1_CLK_VEC_ENABLE [01:01] */
-#define BCHP_CLKGEN_DVP_HT_DUAL_WRAPPER_INST_ENABLE_DVPHT_1_CLK_VEC_ENABLE_MASK 0x00000002
-#define BCHP_CLKGEN_DVP_HT_DUAL_WRAPPER_INST_ENABLE_DVPHT_1_CLK_VEC_ENABLE_SHIFT 1
-#define BCHP_CLKGEN_DVP_HT_DUAL_WRAPPER_INST_ENABLE_DVPHT_1_CLK_VEC_ENABLE_DEFAULT 0x00000001
-
-/* CLKGEN :: DVP_HT_DUAL_WRAPPER_INST_ENABLE :: DVPHT_1_CLK_MAX_ENABLE [00:00] */
-#define BCHP_CLKGEN_DVP_HT_DUAL_WRAPPER_INST_ENABLE_DVPHT_1_CLK_MAX_ENABLE_MASK 0x00000001
-#define BCHP_CLKGEN_DVP_HT_DUAL_WRAPPER_INST_ENABLE_DVPHT_1_CLK_MAX_ENABLE_SHIFT 0
-#define BCHP_CLKGEN_DVP_HT_DUAL_WRAPPER_INST_ENABLE_DVPHT_1_CLK_MAX_ENABLE_DEFAULT 0x00000001
-
-/***************************************************************************
- *DVP_HT_DUAL_WRAPPER_INST_OBSERVE_CLOCK - Dvp ht dual wrapper inst observe clock
- ***************************************************************************/
-/* CLKGEN :: DVP_HT_DUAL_WRAPPER_INST_OBSERVE_CLOCK :: reserved0 [31:12] */
-#define BCHP_CLKGEN_DVP_HT_DUAL_WRAPPER_INST_OBSERVE_CLOCK_reserved0_MASK 0xfffff000
-#define BCHP_CLKGEN_DVP_HT_DUAL_WRAPPER_INST_OBSERVE_CLOCK_reserved0_SHIFT 12
-
-/* CLKGEN :: DVP_HT_DUAL_WRAPPER_INST_OBSERVE_CLOCK :: DVPHT_ENABLE_OBSERVE_CLOCK [11:11] */
-#define BCHP_CLKGEN_DVP_HT_DUAL_WRAPPER_INST_OBSERVE_CLOCK_DVPHT_ENABLE_OBSERVE_CLOCK_MASK 0x00000800
-#define BCHP_CLKGEN_DVP_HT_DUAL_WRAPPER_INST_OBSERVE_CLOCK_DVPHT_ENABLE_OBSERVE_CLOCK_SHIFT 11
-#define BCHP_CLKGEN_DVP_HT_DUAL_WRAPPER_INST_OBSERVE_CLOCK_DVPHT_ENABLE_OBSERVE_CLOCK_DEFAULT 0x00000000
-
-/* CLKGEN :: DVP_HT_DUAL_WRAPPER_INST_OBSERVE_CLOCK :: DVPHT_ENABLE_DIVIDER_OBSERVE_CLOCK [10:10] */
-#define BCHP_CLKGEN_DVP_HT_DUAL_WRAPPER_INST_OBSERVE_CLOCK_DVPHT_ENABLE_DIVIDER_OBSERVE_CLOCK_MASK 0x00000400
-#define BCHP_CLKGEN_DVP_HT_DUAL_WRAPPER_INST_OBSERVE_CLOCK_DVPHT_ENABLE_DIVIDER_OBSERVE_CLOCK_SHIFT 10
-#define BCHP_CLKGEN_DVP_HT_DUAL_WRAPPER_INST_OBSERVE_CLOCK_DVPHT_ENABLE_DIVIDER_OBSERVE_CLOCK_DEFAULT 0x00000000
-
-/* CLKGEN :: DVP_HT_DUAL_WRAPPER_INST_OBSERVE_CLOCK :: DVPHT_CONTROL_OBSERVE_CLOCK [09:06] */
-#define BCHP_CLKGEN_DVP_HT_DUAL_WRAPPER_INST_OBSERVE_CLOCK_DVPHT_CONTROL_OBSERVE_CLOCK_MASK 0x000003c0
-#define BCHP_CLKGEN_DVP_HT_DUAL_WRAPPER_INST_OBSERVE_CLOCK_DVPHT_CONTROL_OBSERVE_CLOCK_SHIFT 6
-#define BCHP_CLKGEN_DVP_HT_DUAL_WRAPPER_INST_OBSERVE_CLOCK_DVPHT_CONTROL_OBSERVE_CLOCK_DEFAULT 0x00000000
-
-/* CLKGEN :: DVP_HT_DUAL_WRAPPER_INST_OBSERVE_CLOCK :: DVPHT_1_ENABLE_OBSERVE_CLOCK [05:05] */
-#define BCHP_CLKGEN_DVP_HT_DUAL_WRAPPER_INST_OBSERVE_CLOCK_DVPHT_1_ENABLE_OBSERVE_CLOCK_MASK 0x00000020
-#define BCHP_CLKGEN_DVP_HT_DUAL_WRAPPER_INST_OBSERVE_CLOCK_DVPHT_1_ENABLE_OBSERVE_CLOCK_SHIFT 5
-#define BCHP_CLKGEN_DVP_HT_DUAL_WRAPPER_INST_OBSERVE_CLOCK_DVPHT_1_ENABLE_OBSERVE_CLOCK_DEFAULT 0x00000000
-
-/* CLKGEN :: DVP_HT_DUAL_WRAPPER_INST_OBSERVE_CLOCK :: DVPHT_1_ENABLE_DIVIDER_OBSERVE_CLOCK [04:04] */
-#define BCHP_CLKGEN_DVP_HT_DUAL_WRAPPER_INST_OBSERVE_CLOCK_DVPHT_1_ENABLE_DIVIDER_OBSERVE_CLOCK_MASK 0x00000010
-#define BCHP_CLKGEN_DVP_HT_DUAL_WRAPPER_INST_OBSERVE_CLOCK_DVPHT_1_ENABLE_DIVIDER_OBSERVE_CLOCK_SHIFT 4
-#define BCHP_CLKGEN_DVP_HT_DUAL_WRAPPER_INST_OBSERVE_CLOCK_DVPHT_1_ENABLE_DIVIDER_OBSERVE_CLOCK_DEFAULT 0x00000000
-
-/* CLKGEN :: DVP_HT_DUAL_WRAPPER_INST_OBSERVE_CLOCK :: DVPHT_1_CONTROL_OBSERVE_CLOCK [03:00] */
-#define BCHP_CLKGEN_DVP_HT_DUAL_WRAPPER_INST_OBSERVE_CLOCK_DVPHT_1_CONTROL_OBSERVE_CLOCK_MASK 0x0000000f
-#define BCHP_CLKGEN_DVP_HT_DUAL_WRAPPER_INST_OBSERVE_CLOCK_DVPHT_1_CONTROL_OBSERVE_CLOCK_SHIFT 0
-#define BCHP_CLKGEN_DVP_HT_DUAL_WRAPPER_INST_OBSERVE_CLOCK_DVPHT_1_CONTROL_OBSERVE_CLOCK_DEFAULT 0x00000000
-
-/***************************************************************************
- *EAGLET_TOP_INST_CLOCK_DISABLE - Disable EAGLET_TOP_INST's clocks
- ***************************************************************************/
-/* CLKGEN :: EAGLET_TOP_INST_CLOCK_DISABLE :: reserved0 [31:01] */
-#define BCHP_CLKGEN_EAGLET_TOP_INST_CLOCK_DISABLE_reserved0_MASK 0xfffffffe
-#define BCHP_CLKGEN_EAGLET_TOP_INST_CLOCK_DISABLE_reserved0_SHIFT 1
-
-/* CLKGEN :: EAGLET_TOP_INST_CLOCK_DISABLE :: DISABLE_CPU_SLOWCPU_CLOCK [00:00] */
-#define BCHP_CLKGEN_EAGLET_TOP_INST_CLOCK_DISABLE_DISABLE_CPU_SLOWCPU_CLOCK_MASK 0x00000001
-#define BCHP_CLKGEN_EAGLET_TOP_INST_CLOCK_DISABLE_DISABLE_CPU_SLOWCPU_CLOCK_SHIFT 0
-#define BCHP_CLKGEN_EAGLET_TOP_INST_CLOCK_DISABLE_DISABLE_CPU_SLOWCPU_CLOCK_DEFAULT 0x00000000
-
-/***************************************************************************
- *EAGLET_TOP_INST_CLOCK_DISABLE_STATUS - Clock Disable Status
- ***************************************************************************/
-/* CLKGEN :: EAGLET_TOP_INST_CLOCK_DISABLE_STATUS :: reserved0 [31:01] */
-#define BCHP_CLKGEN_EAGLET_TOP_INST_CLOCK_DISABLE_STATUS_reserved0_MASK 0xfffffffe
-#define BCHP_CLKGEN_EAGLET_TOP_INST_CLOCK_DISABLE_STATUS_reserved0_SHIFT 1
-
-/* CLKGEN :: EAGLET_TOP_INST_CLOCK_DISABLE_STATUS :: DISABLE_CPU_SLOWCPU_CLOCK_STATUS [00:00] */
-#define BCHP_CLKGEN_EAGLET_TOP_INST_CLOCK_DISABLE_STATUS_DISABLE_CPU_SLOWCPU_CLOCK_STATUS_MASK 0x00000001
-#define BCHP_CLKGEN_EAGLET_TOP_INST_CLOCK_DISABLE_STATUS_DISABLE_CPU_SLOWCPU_CLOCK_STATUS_SHIFT 0
-
-/***************************************************************************
- *EAGLET_TOP_INST_CLOCK_ENABLE - Eaglet top inst clock enable
- ***************************************************************************/
-/* CLKGEN :: EAGLET_TOP_INST_CLOCK_ENABLE :: reserved0 [31:04] */
-#define BCHP_CLKGEN_EAGLET_TOP_INST_CLOCK_ENABLE_reserved0_MASK 0xfffffff0
-#define BCHP_CLKGEN_EAGLET_TOP_INST_CLOCK_ENABLE_reserved0_SHIFT 4
-
-/* CLKGEN :: EAGLET_TOP_INST_CLOCK_ENABLE :: CPU_SECURE_CLOCK_ENABLE [03:03] */
-#define BCHP_CLKGEN_EAGLET_TOP_INST_CLOCK_ENABLE_CPU_SECURE_CLOCK_ENABLE_MASK 0x00000008
-#define BCHP_CLKGEN_EAGLET_TOP_INST_CLOCK_ENABLE_CPU_SECURE_CLOCK_ENABLE_SHIFT 3
-#define BCHP_CLKGEN_EAGLET_TOP_INST_CLOCK_ENABLE_CPU_SECURE_CLOCK_ENABLE_DEFAULT 0x00000001
-
-/* CLKGEN :: EAGLET_TOP_INST_CLOCK_ENABLE :: CPU_SCB_CLOCK_ENABLE [02:02] */
-#define BCHP_CLKGEN_EAGLET_TOP_INST_CLOCK_ENABLE_CPU_SCB_CLOCK_ENABLE_MASK 0x00000004
-#define BCHP_CLKGEN_EAGLET_TOP_INST_CLOCK_ENABLE_CPU_SCB_CLOCK_ENABLE_SHIFT 2
-#define BCHP_CLKGEN_EAGLET_TOP_INST_CLOCK_ENABLE_CPU_SCB_CLOCK_ENABLE_DEFAULT 0x00000001
-
-/* CLKGEN :: EAGLET_TOP_INST_CLOCK_ENABLE :: CPU_GISB_CLOCK_ENABLE [01:01] */
-#define BCHP_CLKGEN_EAGLET_TOP_INST_CLOCK_ENABLE_CPU_GISB_CLOCK_ENABLE_MASK 0x00000002
-#define BCHP_CLKGEN_EAGLET_TOP_INST_CLOCK_ENABLE_CPU_GISB_CLOCK_ENABLE_SHIFT 1
-#define BCHP_CLKGEN_EAGLET_TOP_INST_CLOCK_ENABLE_CPU_GISB_CLOCK_ENABLE_DEFAULT 0x00000001
-
-/* CLKGEN :: EAGLET_TOP_INST_CLOCK_ENABLE :: CPU_54_CLOCK_ENABLE [00:00] */
-#define BCHP_CLKGEN_EAGLET_TOP_INST_CLOCK_ENABLE_CPU_54_CLOCK_ENABLE_MASK 0x00000001
-#define BCHP_CLKGEN_EAGLET_TOP_INST_CLOCK_ENABLE_CPU_54_CLOCK_ENABLE_SHIFT 0
-#define BCHP_CLKGEN_EAGLET_TOP_INST_CLOCK_ENABLE_CPU_54_CLOCK_ENABLE_DEFAULT 0x00000001
-
-/***************************************************************************
- *EAGLET_TOP_INST_CLOCK_ENABLE_STATUS - Clock Enable Status
- ***************************************************************************/
-/* CLKGEN :: EAGLET_TOP_INST_CLOCK_ENABLE_STATUS :: reserved0 [31:04] */
-#define BCHP_CLKGEN_EAGLET_TOP_INST_CLOCK_ENABLE_STATUS_reserved0_MASK 0xfffffff0
-#define BCHP_CLKGEN_EAGLET_TOP_INST_CLOCK_ENABLE_STATUS_reserved0_SHIFT 4
-
-/* CLKGEN :: EAGLET_TOP_INST_CLOCK_ENABLE_STATUS :: CPU_SECURE_CLOCK_ENABLE_STATUS [03:03] */
-#define BCHP_CLKGEN_EAGLET_TOP_INST_CLOCK_ENABLE_STATUS_CPU_SECURE_CLOCK_ENABLE_STATUS_MASK 0x00000008
-#define BCHP_CLKGEN_EAGLET_TOP_INST_CLOCK_ENABLE_STATUS_CPU_SECURE_CLOCK_ENABLE_STATUS_SHIFT 3
-
-/* CLKGEN :: EAGLET_TOP_INST_CLOCK_ENABLE_STATUS :: CPU_SCB_CLOCK_ENABLE_STATUS [02:02] */
-#define BCHP_CLKGEN_EAGLET_TOP_INST_CLOCK_ENABLE_STATUS_CPU_SCB_CLOCK_ENABLE_STATUS_MASK 0x00000004
-#define BCHP_CLKGEN_EAGLET_TOP_INST_CLOCK_ENABLE_STATUS_CPU_SCB_CLOCK_ENABLE_STATUS_SHIFT 2
-
-/* CLKGEN :: EAGLET_TOP_INST_CLOCK_ENABLE_STATUS :: CPU_GISB_CLOCK_ENABLE_STATUS [01:01] */
-#define BCHP_CLKGEN_EAGLET_TOP_INST_CLOCK_ENABLE_STATUS_CPU_GISB_CLOCK_ENABLE_STATUS_MASK 0x00000002
-#define BCHP_CLKGEN_EAGLET_TOP_INST_CLOCK_ENABLE_STATUS_CPU_GISB_CLOCK_ENABLE_STATUS_SHIFT 1
-
-/* CLKGEN :: EAGLET_TOP_INST_CLOCK_ENABLE_STATUS :: CPU_54_CLOCK_ENABLE_STATUS [00:00] */
-#define BCHP_CLKGEN_EAGLET_TOP_INST_CLOCK_ENABLE_STATUS_CPU_54_CLOCK_ENABLE_STATUS_MASK 0x00000001
-#define BCHP_CLKGEN_EAGLET_TOP_INST_CLOCK_ENABLE_STATUS_CPU_54_CLOCK_ENABLE_STATUS_SHIFT 0
-
-/***************************************************************************
- *EGPHY28_1PORT_33V_90O_FC_INST_DIV5 - Egphy28 1port 33v 90o fc inst div5
- ***************************************************************************/
-/* CLKGEN :: EGPHY28_1PORT_33V_90O_FC_INST_DIV5 :: reserved0 [31:01] */
-#define BCHP_CLKGEN_EGPHY28_1PORT_33V_90O_FC_INST_DIV5_reserved0_MASK 0xfffffffe
-#define BCHP_CLKGEN_EGPHY28_1PORT_33V_90O_FC_INST_DIV5_reserved0_SHIFT 1
-
-/* CLKGEN :: EGPHY28_1PORT_33V_90O_FC_INST_DIV5 :: EGPHY_PLL_SEL_DIV5 [00:00] */
-#define BCHP_CLKGEN_EGPHY28_1PORT_33V_90O_FC_INST_DIV5_EGPHY_PLL_SEL_DIV5_MASK 0x00000001
-#define BCHP_CLKGEN_EGPHY28_1PORT_33V_90O_FC_INST_DIV5_EGPHY_PLL_SEL_DIV5_SHIFT 0
-#define BCHP_CLKGEN_EGPHY28_1PORT_33V_90O_FC_INST_DIV5_EGPHY_PLL_SEL_DIV5_DEFAULT 0x00000000
-
-/***************************************************************************
- *EGPHY28_1PORT_33V_90O_FC_INST_SEL - Egphy28 1port 33v 90o fc inst sel
- ***************************************************************************/
-/* CLKGEN :: EGPHY28_1PORT_33V_90O_FC_INST_SEL :: reserved0 [31:01] */
-#define BCHP_CLKGEN_EGPHY28_1PORT_33V_90O_FC_INST_SEL_reserved0_MASK 0xfffffffe
-#define BCHP_CLKGEN_EGPHY28_1PORT_33V_90O_FC_INST_SEL_reserved0_SHIFT 1
-
-/* CLKGEN :: EGPHY28_1PORT_33V_90O_FC_INST_SEL :: EGPHY_PLL_CLK_SEL [00:00] */
-#define BCHP_CLKGEN_EGPHY28_1PORT_33V_90O_FC_INST_SEL_EGPHY_PLL_CLK_SEL_MASK 0x00000001
-#define BCHP_CLKGEN_EGPHY28_1PORT_33V_90O_FC_INST_SEL_EGPHY_PLL_CLK_SEL_SHIFT 0
-#define BCHP_CLKGEN_EGPHY28_1PORT_33V_90O_FC_INST_SEL_EGPHY_PLL_CLK_SEL_DEFAULT 0x00000000
-
-/***************************************************************************
- *GRAPHICS_INST_ALT_CLOCK_ENABLE_M2MC - Graphics inst alt clock enable m2mc
- ***************************************************************************/
-/* CLKGEN :: GRAPHICS_INST_ALT_CLOCK_ENABLE_M2MC :: reserved0 [31:01] */
-#define BCHP_CLKGEN_GRAPHICS_INST_ALT_CLOCK_ENABLE_M2MC_reserved0_MASK 0xfffffffe
-#define BCHP_CLKGEN_GRAPHICS_INST_ALT_CLOCK_ENABLE_M2MC_reserved0_SHIFT 1
-
-/* CLKGEN :: GRAPHICS_INST_ALT_CLOCK_ENABLE_M2MC :: GFX_GISB_ALT_CLOCK_ENABLE_M2MC [00:00] */
-#define BCHP_CLKGEN_GRAPHICS_INST_ALT_CLOCK_ENABLE_M2MC_GFX_GISB_ALT_CLOCK_ENABLE_M2MC_MASK 0x00000001
-#define BCHP_CLKGEN_GRAPHICS_INST_ALT_CLOCK_ENABLE_M2MC_GFX_GISB_ALT_CLOCK_ENABLE_M2MC_SHIFT 0
-#define BCHP_CLKGEN_GRAPHICS_INST_ALT_CLOCK_ENABLE_M2MC_GFX_GISB_ALT_CLOCK_ENABLE_M2MC_DEFAULT 0x00000001
-
-/***************************************************************************
- *GRAPHICS_INST_CLOCK_ENABLE_M2MC - Graphics inst clock enable m2mc
- ***************************************************************************/
-/* CLKGEN :: GRAPHICS_INST_CLOCK_ENABLE_M2MC :: reserved0 [31:04] */
-#define BCHP_CLKGEN_GRAPHICS_INST_CLOCK_ENABLE_M2MC_reserved0_MASK 0xfffffff0
-#define BCHP_CLKGEN_GRAPHICS_INST_CLOCK_ENABLE_M2MC_reserved0_SHIFT 4
-
-/* CLKGEN :: GRAPHICS_INST_CLOCK_ENABLE_M2MC :: GFX_SCB_CLOCK_ENABLE_M2MC [03:03] */
-#define BCHP_CLKGEN_GRAPHICS_INST_CLOCK_ENABLE_M2MC_GFX_SCB_CLOCK_ENABLE_M2MC_MASK 0x00000008
-#define BCHP_CLKGEN_GRAPHICS_INST_CLOCK_ENABLE_M2MC_GFX_SCB_CLOCK_ENABLE_M2MC_SHIFT 3
-#define BCHP_CLKGEN_GRAPHICS_INST_CLOCK_ENABLE_M2MC_GFX_SCB_CLOCK_ENABLE_M2MC_DEFAULT 0x00000001
-
-/* CLKGEN :: GRAPHICS_INST_CLOCK_ENABLE_M2MC :: GFX_GISB_CLOCK_ENABLE_M2MC [02:02] */
-#define BCHP_CLKGEN_GRAPHICS_INST_CLOCK_ENABLE_M2MC_GFX_GISB_CLOCK_ENABLE_M2MC_MASK 0x00000004
-#define BCHP_CLKGEN_GRAPHICS_INST_CLOCK_ENABLE_M2MC_GFX_GISB_CLOCK_ENABLE_M2MC_SHIFT 2
-#define BCHP_CLKGEN_GRAPHICS_INST_CLOCK_ENABLE_M2MC_GFX_GISB_CLOCK_ENABLE_M2MC_DEFAULT 0x00000001
-
-/* CLKGEN :: GRAPHICS_INST_CLOCK_ENABLE_M2MC :: GFX_54_CLOCK_ENABLE_M2MC [01:01] */
-#define BCHP_CLKGEN_GRAPHICS_INST_CLOCK_ENABLE_M2MC_GFX_54_CLOCK_ENABLE_M2MC_MASK 0x00000002
-#define BCHP_CLKGEN_GRAPHICS_INST_CLOCK_ENABLE_M2MC_GFX_54_CLOCK_ENABLE_M2MC_SHIFT 1
-#define BCHP_CLKGEN_GRAPHICS_INST_CLOCK_ENABLE_M2MC_GFX_54_CLOCK_ENABLE_M2MC_DEFAULT 0x00000001
-
-/* CLKGEN :: GRAPHICS_INST_CLOCK_ENABLE_M2MC :: GFX_CLOCK_ENABLE_M2MC [00:00] */
-#define BCHP_CLKGEN_GRAPHICS_INST_CLOCK_ENABLE_M2MC_GFX_CLOCK_ENABLE_M2MC_MASK 0x00000001
-#define BCHP_CLKGEN_GRAPHICS_INST_CLOCK_ENABLE_M2MC_GFX_CLOCK_ENABLE_M2MC_SHIFT 0
-#define BCHP_CLKGEN_GRAPHICS_INST_CLOCK_ENABLE_M2MC_GFX_CLOCK_ENABLE_M2MC_DEFAULT 0x00000001
-
-/***************************************************************************
- *GRAPHICS_INST_CLOCK_ENABLE_M2MC1 - Graphics inst clock enable m2mc1
- ***************************************************************************/
-/* CLKGEN :: GRAPHICS_INST_CLOCK_ENABLE_M2MC1 :: reserved0 [31:03] */
-#define BCHP_CLKGEN_GRAPHICS_INST_CLOCK_ENABLE_M2MC1_reserved0_MASK 0xfffffff8
-#define BCHP_CLKGEN_GRAPHICS_INST_CLOCK_ENABLE_M2MC1_reserved0_SHIFT 3
-
-/* CLKGEN :: GRAPHICS_INST_CLOCK_ENABLE_M2MC1 :: GFX_SCB_CLOCK_ENABLE_M2MC1 [02:02] */
-#define BCHP_CLKGEN_GRAPHICS_INST_CLOCK_ENABLE_M2MC1_GFX_SCB_CLOCK_ENABLE_M2MC1_MASK 0x00000004
-#define BCHP_CLKGEN_GRAPHICS_INST_CLOCK_ENABLE_M2MC1_GFX_SCB_CLOCK_ENABLE_M2MC1_SHIFT 2
-#define BCHP_CLKGEN_GRAPHICS_INST_CLOCK_ENABLE_M2MC1_GFX_SCB_CLOCK_ENABLE_M2MC1_DEFAULT 0x00000001
-
-/* CLKGEN :: GRAPHICS_INST_CLOCK_ENABLE_M2MC1 :: GFX_GISB_CLOCK_ENABLE_M2MC1 [01:01] */
-#define BCHP_CLKGEN_GRAPHICS_INST_CLOCK_ENABLE_M2MC1_GFX_GISB_CLOCK_ENABLE_M2MC1_MASK 0x00000002
-#define BCHP_CLKGEN_GRAPHICS_INST_CLOCK_ENABLE_M2MC1_GFX_GISB_CLOCK_ENABLE_M2MC1_SHIFT 1
-#define BCHP_CLKGEN_GRAPHICS_INST_CLOCK_ENABLE_M2MC1_GFX_GISB_CLOCK_ENABLE_M2MC1_DEFAULT 0x00000001
-
-/* CLKGEN :: GRAPHICS_INST_CLOCK_ENABLE_M2MC1 :: GFX_CLOCK_ENABLE_M2MC1 [00:00] */
-#define BCHP_CLKGEN_GRAPHICS_INST_CLOCK_ENABLE_M2MC1_GFX_CLOCK_ENABLE_M2MC1_MASK 0x00000001
-#define BCHP_CLKGEN_GRAPHICS_INST_CLOCK_ENABLE_M2MC1_GFX_CLOCK_ENABLE_M2MC1_SHIFT 0
-#define BCHP_CLKGEN_GRAPHICS_INST_CLOCK_ENABLE_M2MC1_GFX_CLOCK_ENABLE_M2MC1_DEFAULT 0x00000001
-
-/***************************************************************************
- *GRAPHICS_INST_CLOCK_ENABLE_M2MC1_STATUS - Clock Enable Status
- ***************************************************************************/
-/* CLKGEN :: GRAPHICS_INST_CLOCK_ENABLE_M2MC1_STATUS :: reserved0 [31:03] */
-#define BCHP_CLKGEN_GRAPHICS_INST_CLOCK_ENABLE_M2MC1_STATUS_reserved0_MASK 0xfffffff8
-#define BCHP_CLKGEN_GRAPHICS_INST_CLOCK_ENABLE_M2MC1_STATUS_reserved0_SHIFT 3
-
-/* CLKGEN :: GRAPHICS_INST_CLOCK_ENABLE_M2MC1_STATUS :: GFX_SCB_CLOCK_ENABLE_M2MC1_STATUS [02:02] */
-#define BCHP_CLKGEN_GRAPHICS_INST_CLOCK_ENABLE_M2MC1_STATUS_GFX_SCB_CLOCK_ENABLE_M2MC1_STATUS_MASK 0x00000004
-#define BCHP_CLKGEN_GRAPHICS_INST_CLOCK_ENABLE_M2MC1_STATUS_GFX_SCB_CLOCK_ENABLE_M2MC1_STATUS_SHIFT 2
-
-/* CLKGEN :: GRAPHICS_INST_CLOCK_ENABLE_M2MC1_STATUS :: GFX_GISB_CLOCK_ENABLE_M2MC1_STATUS [01:01] */
-#define BCHP_CLKGEN_GRAPHICS_INST_CLOCK_ENABLE_M2MC1_STATUS_GFX_GISB_CLOCK_ENABLE_M2MC1_STATUS_MASK 0x00000002
-#define BCHP_CLKGEN_GRAPHICS_INST_CLOCK_ENABLE_M2MC1_STATUS_GFX_GISB_CLOCK_ENABLE_M2MC1_STATUS_SHIFT 1
-
-/* CLKGEN :: GRAPHICS_INST_CLOCK_ENABLE_M2MC1_STATUS :: GFX_CLOCK_ENABLE_M2MC1_STATUS [00:00] */
-#define BCHP_CLKGEN_GRAPHICS_INST_CLOCK_ENABLE_M2MC1_STATUS_GFX_CLOCK_ENABLE_M2MC1_STATUS_MASK 0x00000001
-#define BCHP_CLKGEN_GRAPHICS_INST_CLOCK_ENABLE_M2MC1_STATUS_GFX_CLOCK_ENABLE_M2MC1_STATUS_SHIFT 0
-
-/***************************************************************************
- *GRAPHICS_INST_CLOCK_ENABLE_M2MC_STATUS - Clock Enable Status
- ***************************************************************************/
-/* CLKGEN :: GRAPHICS_INST_CLOCK_ENABLE_M2MC_STATUS :: reserved0 [31:04] */
-#define BCHP_CLKGEN_GRAPHICS_INST_CLOCK_ENABLE_M2MC_STATUS_reserved0_MASK 0xfffffff0
-#define BCHP_CLKGEN_GRAPHICS_INST_CLOCK_ENABLE_M2MC_STATUS_reserved0_SHIFT 4
-
-/* CLKGEN :: GRAPHICS_INST_CLOCK_ENABLE_M2MC_STATUS :: GFX_SCB_CLOCK_ENABLE_M2MC_STATUS [03:03] */
-#define BCHP_CLKGEN_GRAPHICS_INST_CLOCK_ENABLE_M2MC_STATUS_GFX_SCB_CLOCK_ENABLE_M2MC_STATUS_MASK 0x00000008
-#define BCHP_CLKGEN_GRAPHICS_INST_CLOCK_ENABLE_M2MC_STATUS_GFX_SCB_CLOCK_ENABLE_M2MC_STATUS_SHIFT 3
-
-/* CLKGEN :: GRAPHICS_INST_CLOCK_ENABLE_M2MC_STATUS :: GFX_GISB_CLOCK_ENABLE_M2MC_STATUS [02:02] */
-#define BCHP_CLKGEN_GRAPHICS_INST_CLOCK_ENABLE_M2MC_STATUS_GFX_GISB_CLOCK_ENABLE_M2MC_STATUS_MASK 0x00000004
-#define BCHP_CLKGEN_GRAPHICS_INST_CLOCK_ENABLE_M2MC_STATUS_GFX_GISB_CLOCK_ENABLE_M2MC_STATUS_SHIFT 2
-
-/* CLKGEN :: GRAPHICS_INST_CLOCK_ENABLE_M2MC_STATUS :: GFX_54_CLOCK_ENABLE_M2MC_STATUS [01:01] */
-#define BCHP_CLKGEN_GRAPHICS_INST_CLOCK_ENABLE_M2MC_STATUS_GFX_54_CLOCK_ENABLE_M2MC_STATUS_MASK 0x00000002
-#define BCHP_CLKGEN_GRAPHICS_INST_CLOCK_ENABLE_M2MC_STATUS_GFX_54_CLOCK_ENABLE_M2MC_STATUS_SHIFT 1
-
-/* CLKGEN :: GRAPHICS_INST_CLOCK_ENABLE_M2MC_STATUS :: GFX_CLOCK_ENABLE_M2MC_STATUS [00:00] */
-#define BCHP_CLKGEN_GRAPHICS_INST_CLOCK_ENABLE_M2MC_STATUS_GFX_CLOCK_ENABLE_M2MC_STATUS_MASK 0x00000001
-#define BCHP_CLKGEN_GRAPHICS_INST_CLOCK_ENABLE_M2MC_STATUS_GFX_CLOCK_ENABLE_M2MC_STATUS_SHIFT 0
-
-/***************************************************************************
- *GRAPHICS_INST_OBSERVE_CLOCK - Graphics inst observe clock
- ***************************************************************************/
-/* CLKGEN :: GRAPHICS_INST_OBSERVE_CLOCK :: reserved0 [31:06] */
-#define BCHP_CLKGEN_GRAPHICS_INST_OBSERVE_CLOCK_reserved0_MASK 0xffffffc0
-#define BCHP_CLKGEN_GRAPHICS_INST_OBSERVE_CLOCK_reserved0_SHIFT 6
-
-/* CLKGEN :: GRAPHICS_INST_OBSERVE_CLOCK :: GFX_ENABLE_OBSERVE_CLOCK [05:05] */
-#define BCHP_CLKGEN_GRAPHICS_INST_OBSERVE_CLOCK_GFX_ENABLE_OBSERVE_CLOCK_MASK 0x00000020
-#define BCHP_CLKGEN_GRAPHICS_INST_OBSERVE_CLOCK_GFX_ENABLE_OBSERVE_CLOCK_SHIFT 5
-#define BCHP_CLKGEN_GRAPHICS_INST_OBSERVE_CLOCK_GFX_ENABLE_OBSERVE_CLOCK_DEFAULT 0x00000000
-
-/* CLKGEN :: GRAPHICS_INST_OBSERVE_CLOCK :: GFX_ENABLE_DIVIDER_OBSERVE_CLOCK [04:04] */
-#define BCHP_CLKGEN_GRAPHICS_INST_OBSERVE_CLOCK_GFX_ENABLE_DIVIDER_OBSERVE_CLOCK_MASK 0x00000010
-#define BCHP_CLKGEN_GRAPHICS_INST_OBSERVE_CLOCK_GFX_ENABLE_DIVIDER_OBSERVE_CLOCK_SHIFT 4
-#define BCHP_CLKGEN_GRAPHICS_INST_OBSERVE_CLOCK_GFX_ENABLE_DIVIDER_OBSERVE_CLOCK_DEFAULT 0x00000000
-
-/* CLKGEN :: GRAPHICS_INST_OBSERVE_CLOCK :: GFX_CONTROL_OBSERVE_CLOCK [03:00] */
-#define BCHP_CLKGEN_GRAPHICS_INST_OBSERVE_CLOCK_GFX_CONTROL_OBSERVE_CLOCK_MASK 0x0000000f
-#define BCHP_CLKGEN_GRAPHICS_INST_OBSERVE_CLOCK_GFX_CONTROL_OBSERVE_CLOCK_SHIFT 0
-#define BCHP_CLKGEN_GRAPHICS_INST_OBSERVE_CLOCK_GFX_CONTROL_OBSERVE_CLOCK_DEFAULT 0x00000000
-
-/***************************************************************************
- *HIF_INST_CLOCK_DISABLE - Disable HIF_INST's clocks
- ***************************************************************************/
-/* CLKGEN :: HIF_INST_CLOCK_DISABLE :: reserved0 [31:06] */
-#define BCHP_CLKGEN_HIF_INST_CLOCK_DISABLE_reserved0_MASK 0xffffffc0
-#define BCHP_CLKGEN_HIF_INST_CLOCK_DISABLE_reserved0_SHIFT 6
-
-/* CLKGEN :: HIF_INST_CLOCK_DISABLE :: DISABLE_PAD_OUTPUT_EBI_CLOCK [05:05] */
-#define BCHP_CLKGEN_HIF_INST_CLOCK_DISABLE_DISABLE_PAD_OUTPUT_EBI_CLOCK_MASK 0x00000020
-#define BCHP_CLKGEN_HIF_INST_CLOCK_DISABLE_DISABLE_PAD_OUTPUT_EBI_CLOCK_SHIFT 5
-#define BCHP_CLKGEN_HIF_INST_CLOCK_DISABLE_DISABLE_PAD_OUTPUT_EBI_CLOCK_DEFAULT 0x00000000
-
-/* CLKGEN :: HIF_INST_CLOCK_DISABLE :: DISABLE_NAND_DDR_CLOCK [04:04] */
-#define BCHP_CLKGEN_HIF_INST_CLOCK_DISABLE_DISABLE_NAND_DDR_CLOCK_MASK 0x00000010
-#define BCHP_CLKGEN_HIF_INST_CLOCK_DISABLE_DISABLE_NAND_DDR_CLOCK_SHIFT 4
-#define BCHP_CLKGEN_HIF_INST_CLOCK_DISABLE_DISABLE_NAND_DDR_CLOCK_DEFAULT 0x00000000
-
-/* CLKGEN :: HIF_INST_CLOCK_DISABLE :: DISABLE_HIF_SPI_CLOCK [03:03] */
-#define BCHP_CLKGEN_HIF_INST_CLOCK_DISABLE_DISABLE_HIF_SPI_CLOCK_MASK 0x00000008
-#define BCHP_CLKGEN_HIF_INST_CLOCK_DISABLE_DISABLE_HIF_SPI_CLOCK_SHIFT 3
-#define BCHP_CLKGEN_HIF_INST_CLOCK_DISABLE_DISABLE_HIF_SPI_CLOCK_DEFAULT 0x00000000
-
-/* CLKGEN :: HIF_INST_CLOCK_DISABLE :: DISABLE_HIF_SDIO_EMMC_CLOCK [02:02] */
-#define BCHP_CLKGEN_HIF_INST_CLOCK_DISABLE_DISABLE_HIF_SDIO_EMMC_CLOCK_MASK 0x00000004
-#define BCHP_CLKGEN_HIF_INST_CLOCK_DISABLE_DISABLE_HIF_SDIO_EMMC_CLOCK_SHIFT 2
-#define BCHP_CLKGEN_HIF_INST_CLOCK_DISABLE_DISABLE_HIF_SDIO_EMMC_CLOCK_DEFAULT 0x00000000
-
-/* CLKGEN :: HIF_INST_CLOCK_DISABLE :: DISABLE_HIF_SDIO_CARD_CLOCK [01:01] */
-#define BCHP_CLKGEN_HIF_INST_CLOCK_DISABLE_DISABLE_HIF_SDIO_CARD_CLOCK_MASK 0x00000002
-#define BCHP_CLKGEN_HIF_INST_CLOCK_DISABLE_DISABLE_HIF_SDIO_CARD_CLOCK_SHIFT 1
-#define BCHP_CLKGEN_HIF_INST_CLOCK_DISABLE_DISABLE_HIF_SDIO_CARD_CLOCK_DEFAULT 0x00000000
-
-/* CLKGEN :: HIF_INST_CLOCK_DISABLE :: DISABLE_HIF_ALWAYSON_CLOCK [00:00] */
-#define BCHP_CLKGEN_HIF_INST_CLOCK_DISABLE_DISABLE_HIF_ALWAYSON_CLOCK_MASK 0x00000001
-#define BCHP_CLKGEN_HIF_INST_CLOCK_DISABLE_DISABLE_HIF_ALWAYSON_CLOCK_SHIFT 0
-#define BCHP_CLKGEN_HIF_INST_CLOCK_DISABLE_DISABLE_HIF_ALWAYSON_CLOCK_DEFAULT 0x00000000
-
-/***************************************************************************
- *HIF_INST_CLOCK_DISABLE_STATUS - Clock Disable Status
- ***************************************************************************/
-/* CLKGEN :: HIF_INST_CLOCK_DISABLE_STATUS :: reserved0 [31:06] */
-#define BCHP_CLKGEN_HIF_INST_CLOCK_DISABLE_STATUS_reserved0_MASK 0xffffffc0
-#define BCHP_CLKGEN_HIF_INST_CLOCK_DISABLE_STATUS_reserved0_SHIFT 6
-
-/* CLKGEN :: HIF_INST_CLOCK_DISABLE_STATUS :: DISABLE_PAD_OUTPUT_EBI_CLOCK_STATUS [05:05] */
-#define BCHP_CLKGEN_HIF_INST_CLOCK_DISABLE_STATUS_DISABLE_PAD_OUTPUT_EBI_CLOCK_STATUS_MASK 0x00000020
-#define BCHP_CLKGEN_HIF_INST_CLOCK_DISABLE_STATUS_DISABLE_PAD_OUTPUT_EBI_CLOCK_STATUS_SHIFT 5
-
-/* CLKGEN :: HIF_INST_CLOCK_DISABLE_STATUS :: DISABLE_NAND_DDR_CLOCK_STATUS [04:04] */
-#define BCHP_CLKGEN_HIF_INST_CLOCK_DISABLE_STATUS_DISABLE_NAND_DDR_CLOCK_STATUS_MASK 0x00000010
-#define BCHP_CLKGEN_HIF_INST_CLOCK_DISABLE_STATUS_DISABLE_NAND_DDR_CLOCK_STATUS_SHIFT 4
-
-/* CLKGEN :: HIF_INST_CLOCK_DISABLE_STATUS :: DISABLE_HIF_SPI_CLOCK_STATUS [03:03] */
-#define BCHP_CLKGEN_HIF_INST_CLOCK_DISABLE_STATUS_DISABLE_HIF_SPI_CLOCK_STATUS_MASK 0x00000008
-#define BCHP_CLKGEN_HIF_INST_CLOCK_DISABLE_STATUS_DISABLE_HIF_SPI_CLOCK_STATUS_SHIFT 3
-
-/* CLKGEN :: HIF_INST_CLOCK_DISABLE_STATUS :: DISABLE_HIF_SDIO_EMMC_CLOCK_STATUS [02:02] */
-#define BCHP_CLKGEN_HIF_INST_CLOCK_DISABLE_STATUS_DISABLE_HIF_SDIO_EMMC_CLOCK_STATUS_MASK 0x00000004
-#define BCHP_CLKGEN_HIF_INST_CLOCK_DISABLE_STATUS_DISABLE_HIF_SDIO_EMMC_CLOCK_STATUS_SHIFT 2
-
-/* CLKGEN :: HIF_INST_CLOCK_DISABLE_STATUS :: DISABLE_HIF_SDIO_CARD_CLOCK_STATUS [01:01] */
-#define BCHP_CLKGEN_HIF_INST_CLOCK_DISABLE_STATUS_DISABLE_HIF_SDIO_CARD_CLOCK_STATUS_MASK 0x00000002
-#define BCHP_CLKGEN_HIF_INST_CLOCK_DISABLE_STATUS_DISABLE_HIF_SDIO_CARD_CLOCK_STATUS_SHIFT 1
-
-/* CLKGEN :: HIF_INST_CLOCK_DISABLE_STATUS :: DISABLE_HIF_ALWAYSON_CLOCK_STATUS [00:00] */
-#define BCHP_CLKGEN_HIF_INST_CLOCK_DISABLE_STATUS_DISABLE_HIF_ALWAYSON_CLOCK_STATUS_MASK 0x00000001
-#define BCHP_CLKGEN_HIF_INST_CLOCK_DISABLE_STATUS_DISABLE_HIF_ALWAYSON_CLOCK_STATUS_SHIFT 0
-
-/***************************************************************************
- *HIF_INST_CLOCK_ENABLE - Hif inst clock enable
- ***************************************************************************/
-/* CLKGEN :: HIF_INST_CLOCK_ENABLE :: reserved0 [31:01] */
-#define BCHP_CLKGEN_HIF_INST_CLOCK_ENABLE_reserved0_MASK 0xfffffffe
-#define BCHP_CLKGEN_HIF_INST_CLOCK_ENABLE_reserved0_SHIFT 1
-
-/* CLKGEN :: HIF_INST_CLOCK_ENABLE :: HIF_54_CLOCK_ENABLE [00:00] */
-#define BCHP_CLKGEN_HIF_INST_CLOCK_ENABLE_HIF_54_CLOCK_ENABLE_MASK 0x00000001
-#define BCHP_CLKGEN_HIF_INST_CLOCK_ENABLE_HIF_54_CLOCK_ENABLE_SHIFT 0
-#define BCHP_CLKGEN_HIF_INST_CLOCK_ENABLE_HIF_54_CLOCK_ENABLE_DEFAULT 0x00000001
-
-/***************************************************************************
- *HIF_INST_CLOCK_ENABLE_STATUS - Clock Enable Status
- ***************************************************************************/
-/* CLKGEN :: HIF_INST_CLOCK_ENABLE_STATUS :: reserved0 [31:01] */
-#define BCHP_CLKGEN_HIF_INST_CLOCK_ENABLE_STATUS_reserved0_MASK 0xfffffffe
-#define BCHP_CLKGEN_HIF_INST_CLOCK_ENABLE_STATUS_reserved0_SHIFT 1
-
-/* CLKGEN :: HIF_INST_CLOCK_ENABLE_STATUS :: HIF_54_CLOCK_ENABLE_STATUS [00:00] */
-#define BCHP_CLKGEN_HIF_INST_CLOCK_ENABLE_STATUS_HIF_54_CLOCK_ENABLE_STATUS_MASK 0x00000001
-#define BCHP_CLKGEN_HIF_INST_CLOCK_ENABLE_STATUS_HIF_54_CLOCK_ENABLE_STATUS_SHIFT 0
-
-/***************************************************************************
- *HIF_INST_OBSERVE_CLOCK - Hif inst observe clock
- ***************************************************************************/
-/* CLKGEN :: HIF_INST_OBSERVE_CLOCK :: reserved0 [31:06] */
-#define BCHP_CLKGEN_HIF_INST_OBSERVE_CLOCK_reserved0_MASK 0xffffffc0
-#define BCHP_CLKGEN_HIF_INST_OBSERVE_CLOCK_reserved0_SHIFT 6
-
-/* CLKGEN :: HIF_INST_OBSERVE_CLOCK :: HIF_ENABLE_OBSERVE_CLOCK [05:05] */
-#define BCHP_CLKGEN_HIF_INST_OBSERVE_CLOCK_HIF_ENABLE_OBSERVE_CLOCK_MASK 0x00000020
-#define BCHP_CLKGEN_HIF_INST_OBSERVE_CLOCK_HIF_ENABLE_OBSERVE_CLOCK_SHIFT 5
-#define BCHP_CLKGEN_HIF_INST_OBSERVE_CLOCK_HIF_ENABLE_OBSERVE_CLOCK_DEFAULT 0x00000000
-
-/* CLKGEN :: HIF_INST_OBSERVE_CLOCK :: HIF_ENABLE_DIVIDER_OBSERVE_CLOCK [04:04] */
-#define BCHP_CLKGEN_HIF_INST_OBSERVE_CLOCK_HIF_ENABLE_DIVIDER_OBSERVE_CLOCK_MASK 0x00000010
-#define BCHP_CLKGEN_HIF_INST_OBSERVE_CLOCK_HIF_ENABLE_DIVIDER_OBSERVE_CLOCK_SHIFT 4
-#define BCHP_CLKGEN_HIF_INST_OBSERVE_CLOCK_HIF_ENABLE_DIVIDER_OBSERVE_CLOCK_DEFAULT 0x00000000
-
-/* CLKGEN :: HIF_INST_OBSERVE_CLOCK :: HIF_CONTROL_OBSERVE_CLOCK [03:00] */
-#define BCHP_CLKGEN_HIF_INST_OBSERVE_CLOCK_HIF_CONTROL_OBSERVE_CLOCK_MASK 0x0000000f
-#define BCHP_CLKGEN_HIF_INST_OBSERVE_CLOCK_HIF_CONTROL_OBSERVE_CLOCK_SHIFT 0
-#define BCHP_CLKGEN_HIF_INST_OBSERVE_CLOCK_HIF_CONTROL_OBSERVE_CLOCK_DEFAULT 0x00000000
-
-/***************************************************************************
- *HVD_SID0_TOP_INST_CLOCK_ENABLE - Hvd sid0 top inst clock enable
- ***************************************************************************/
-/* CLKGEN :: HVD_SID0_TOP_INST_CLOCK_ENABLE :: reserved0 [31:06] */
-#define BCHP_CLKGEN_HVD_SID0_TOP_INST_CLOCK_ENABLE_reserved0_MASK 0xffffffc0
-#define BCHP_CLKGEN_HVD_SID0_TOP_INST_CLOCK_ENABLE_reserved0_SHIFT 6
-
-/* CLKGEN :: HVD_SID0_TOP_INST_CLOCK_ENABLE :: HVD_SCB_CLOCK_ENABLE [05:05] */
-#define BCHP_CLKGEN_HVD_SID0_TOP_INST_CLOCK_ENABLE_HVD_SCB_CLOCK_ENABLE_MASK 0x00000020
-#define BCHP_CLKGEN_HVD_SID0_TOP_INST_CLOCK_ENABLE_HVD_SCB_CLOCK_ENABLE_SHIFT 5
-#define BCHP_CLKGEN_HVD_SID0_TOP_INST_CLOCK_ENABLE_HVD_SCB_CLOCK_ENABLE_DEFAULT 0x00000001
-
-/* CLKGEN :: HVD_SID0_TOP_INST_CLOCK_ENABLE :: HVD_GISB_CLOCK_ENABLE [04:04] */
-#define BCHP_CLKGEN_HVD_SID0_TOP_INST_CLOCK_ENABLE_HVD_GISB_CLOCK_ENABLE_MASK 0x00000010
-#define BCHP_CLKGEN_HVD_SID0_TOP_INST_CLOCK_ENABLE_HVD_GISB_CLOCK_ENABLE_SHIFT 4
-#define BCHP_CLKGEN_HVD_SID0_TOP_INST_CLOCK_ENABLE_HVD_GISB_CLOCK_ENABLE_DEFAULT 0x00000001
-
-/* CLKGEN :: HVD_SID0_TOP_INST_CLOCK_ENABLE :: HVD_CPU_CLOCK_ENABLE [03:03] */
-#define BCHP_CLKGEN_HVD_SID0_TOP_INST_CLOCK_ENABLE_HVD_CPU_CLOCK_ENABLE_MASK 0x00000008
-#define BCHP_CLKGEN_HVD_SID0_TOP_INST_CLOCK_ENABLE_HVD_CPU_CLOCK_ENABLE_SHIFT 3
-#define BCHP_CLKGEN_HVD_SID0_TOP_INST_CLOCK_ENABLE_HVD_CPU_CLOCK_ENABLE_DEFAULT 0x00000001
-
-/* CLKGEN :: HVD_SID0_TOP_INST_CLOCK_ENABLE :: HVD_CORE_CLOCK_ENABLE [02:02] */
-#define BCHP_CLKGEN_HVD_SID0_TOP_INST_CLOCK_ENABLE_HVD_CORE_CLOCK_ENABLE_MASK 0x00000004
-#define BCHP_CLKGEN_HVD_SID0_TOP_INST_CLOCK_ENABLE_HVD_CORE_CLOCK_ENABLE_SHIFT 2
-#define BCHP_CLKGEN_HVD_SID0_TOP_INST_CLOCK_ENABLE_HVD_CORE_CLOCK_ENABLE_DEFAULT 0x00000001
-
-/* CLKGEN :: HVD_SID0_TOP_INST_CLOCK_ENABLE :: HVD_54_CLOCK_ENABLE [01:01] */
-#define BCHP_CLKGEN_HVD_SID0_TOP_INST_CLOCK_ENABLE_HVD_54_CLOCK_ENABLE_MASK 0x00000002
-#define BCHP_CLKGEN_HVD_SID0_TOP_INST_CLOCK_ENABLE_HVD_54_CLOCK_ENABLE_SHIFT 1
-#define BCHP_CLKGEN_HVD_SID0_TOP_INST_CLOCK_ENABLE_HVD_54_CLOCK_ENABLE_DEFAULT 0x00000001
-
-/* CLKGEN :: HVD_SID0_TOP_INST_CLOCK_ENABLE :: HVD_108_CLOCK_ENABLE [00:00] */
-#define BCHP_CLKGEN_HVD_SID0_TOP_INST_CLOCK_ENABLE_HVD_108_CLOCK_ENABLE_MASK 0x00000001
-#define BCHP_CLKGEN_HVD_SID0_TOP_INST_CLOCK_ENABLE_HVD_108_CLOCK_ENABLE_SHIFT 0
-#define BCHP_CLKGEN_HVD_SID0_TOP_INST_CLOCK_ENABLE_HVD_108_CLOCK_ENABLE_DEFAULT 0x00000001
-
-/***************************************************************************
- *HVD_SID0_TOP_INST_CLOCK_ENABLE_SID - Hvd sid0 top inst clock enable sid
- ***************************************************************************/
-/* CLKGEN :: HVD_SID0_TOP_INST_CLOCK_ENABLE_SID :: reserved0 [31:01] */
-#define BCHP_CLKGEN_HVD_SID0_TOP_INST_CLOCK_ENABLE_SID_reserved0_MASK 0xfffffffe
-#define BCHP_CLKGEN_HVD_SID0_TOP_INST_CLOCK_ENABLE_SID_reserved0_SHIFT 1
-
-/* CLKGEN :: HVD_SID0_TOP_INST_CLOCK_ENABLE_SID :: HVD_CLOCK_ENABLE_SID [00:00] */
-#define BCHP_CLKGEN_HVD_SID0_TOP_INST_CLOCK_ENABLE_SID_HVD_CLOCK_ENABLE_SID_MASK 0x00000001
-#define BCHP_CLKGEN_HVD_SID0_TOP_INST_CLOCK_ENABLE_SID_HVD_CLOCK_ENABLE_SID_SHIFT 0
-#define BCHP_CLKGEN_HVD_SID0_TOP_INST_CLOCK_ENABLE_SID_HVD_CLOCK_ENABLE_SID_DEFAULT 0x00000001
-
-/***************************************************************************
- *HVD_SID0_TOP_INST_CLOCK_ENABLE_SID_STATUS - Clock Enable Status
- ***************************************************************************/
-/* CLKGEN :: HVD_SID0_TOP_INST_CLOCK_ENABLE_SID_STATUS :: reserved0 [31:01] */
-#define BCHP_CLKGEN_HVD_SID0_TOP_INST_CLOCK_ENABLE_SID_STATUS_reserved0_MASK 0xfffffffe
-#define BCHP_CLKGEN_HVD_SID0_TOP_INST_CLOCK_ENABLE_SID_STATUS_reserved0_SHIFT 1
-
-/* CLKGEN :: HVD_SID0_TOP_INST_CLOCK_ENABLE_SID_STATUS :: HVD_CLOCK_ENABLE_SID_STATUS [00:00] */
-#define BCHP_CLKGEN_HVD_SID0_TOP_INST_CLOCK_ENABLE_SID_STATUS_HVD_CLOCK_ENABLE_SID_STATUS_MASK 0x00000001
-#define BCHP_CLKGEN_HVD_SID0_TOP_INST_CLOCK_ENABLE_SID_STATUS_HVD_CLOCK_ENABLE_SID_STATUS_SHIFT 0
-
-/***************************************************************************
- *HVD_SID0_TOP_INST_CLOCK_ENABLE_STATUS - Clock Enable Status
- ***************************************************************************/
-/* CLKGEN :: HVD_SID0_TOP_INST_CLOCK_ENABLE_STATUS :: reserved0 [31:06] */
-#define BCHP_CLKGEN_HVD_SID0_TOP_INST_CLOCK_ENABLE_STATUS_reserved0_MASK 0xffffffc0
-#define BCHP_CLKGEN_HVD_SID0_TOP_INST_CLOCK_ENABLE_STATUS_reserved0_SHIFT 6
-
-/* CLKGEN :: HVD_SID0_TOP_INST_CLOCK_ENABLE_STATUS :: HVD_SCB_CLOCK_ENABLE_STATUS [05:05] */
-#define BCHP_CLKGEN_HVD_SID0_TOP_INST_CLOCK_ENABLE_STATUS_HVD_SCB_CLOCK_ENABLE_STATUS_MASK 0x00000020
-#define BCHP_CLKGEN_HVD_SID0_TOP_INST_CLOCK_ENABLE_STATUS_HVD_SCB_CLOCK_ENABLE_STATUS_SHIFT 5
-
-/* CLKGEN :: HVD_SID0_TOP_INST_CLOCK_ENABLE_STATUS :: HVD_GISB_CLOCK_ENABLE_STATUS [04:04] */
-#define BCHP_CLKGEN_HVD_SID0_TOP_INST_CLOCK_ENABLE_STATUS_HVD_GISB_CLOCK_ENABLE_STATUS_MASK 0x00000010
-#define BCHP_CLKGEN_HVD_SID0_TOP_INST_CLOCK_ENABLE_STATUS_HVD_GISB_CLOCK_ENABLE_STATUS_SHIFT 4
-
-/* CLKGEN :: HVD_SID0_TOP_INST_CLOCK_ENABLE_STATUS :: HVD_CPU_CLOCK_ENABLE_STATUS [03:03] */
-#define BCHP_CLKGEN_HVD_SID0_TOP_INST_CLOCK_ENABLE_STATUS_HVD_CPU_CLOCK_ENABLE_STATUS_MASK 0x00000008
-#define BCHP_CLKGEN_HVD_SID0_TOP_INST_CLOCK_ENABLE_STATUS_HVD_CPU_CLOCK_ENABLE_STATUS_SHIFT 3
-
-/* CLKGEN :: HVD_SID0_TOP_INST_CLOCK_ENABLE_STATUS :: HVD_CORE_CLOCK_ENABLE_STATUS [02:02] */
-#define BCHP_CLKGEN_HVD_SID0_TOP_INST_CLOCK_ENABLE_STATUS_HVD_CORE_CLOCK_ENABLE_STATUS_MASK 0x00000004
-#define BCHP_CLKGEN_HVD_SID0_TOP_INST_CLOCK_ENABLE_STATUS_HVD_CORE_CLOCK_ENABLE_STATUS_SHIFT 2
-
-/* CLKGEN :: HVD_SID0_TOP_INST_CLOCK_ENABLE_STATUS :: HVD_54_CLOCK_ENABLE_STATUS [01:01] */
-#define BCHP_CLKGEN_HVD_SID0_TOP_INST_CLOCK_ENABLE_STATUS_HVD_54_CLOCK_ENABLE_STATUS_MASK 0x00000002
-#define BCHP_CLKGEN_HVD_SID0_TOP_INST_CLOCK_ENABLE_STATUS_HVD_54_CLOCK_ENABLE_STATUS_SHIFT 1
-
-/* CLKGEN :: HVD_SID0_TOP_INST_CLOCK_ENABLE_STATUS :: HVD_108_CLOCK_ENABLE_STATUS [00:00] */
-#define BCHP_CLKGEN_HVD_SID0_TOP_INST_CLOCK_ENABLE_STATUS_HVD_108_CLOCK_ENABLE_STATUS_MASK 0x00000001
-#define BCHP_CLKGEN_HVD_SID0_TOP_INST_CLOCK_ENABLE_STATUS_HVD_108_CLOCK_ENABLE_STATUS_SHIFT 0
-
-/***************************************************************************
- *HVD_SID0_TOP_INST_OBSERVE_CLOCK - Hvd sid0 top inst observe clock
- ***************************************************************************/
-/* CLKGEN :: HVD_SID0_TOP_INST_OBSERVE_CLOCK :: reserved0 [31:06] */
-#define BCHP_CLKGEN_HVD_SID0_TOP_INST_OBSERVE_CLOCK_reserved0_MASK 0xffffffc0
-#define BCHP_CLKGEN_HVD_SID0_TOP_INST_OBSERVE_CLOCK_reserved0_SHIFT 6
-
-/* CLKGEN :: HVD_SID0_TOP_INST_OBSERVE_CLOCK :: HVD_ENABLE_OBSERVE_CLOCK [05:05] */
-#define BCHP_CLKGEN_HVD_SID0_TOP_INST_OBSERVE_CLOCK_HVD_ENABLE_OBSERVE_CLOCK_MASK 0x00000020
-#define BCHP_CLKGEN_HVD_SID0_TOP_INST_OBSERVE_CLOCK_HVD_ENABLE_OBSERVE_CLOCK_SHIFT 5
-#define BCHP_CLKGEN_HVD_SID0_TOP_INST_OBSERVE_CLOCK_HVD_ENABLE_OBSERVE_CLOCK_DEFAULT 0x00000000
-
-/* CLKGEN :: HVD_SID0_TOP_INST_OBSERVE_CLOCK :: HVD_ENABLE_DIVIDER_OBSERVE_CLOCK [04:04] */
-#define BCHP_CLKGEN_HVD_SID0_TOP_INST_OBSERVE_CLOCK_HVD_ENABLE_DIVIDER_OBSERVE_CLOCK_MASK 0x00000010
-#define BCHP_CLKGEN_HVD_SID0_TOP_INST_OBSERVE_CLOCK_HVD_ENABLE_DIVIDER_OBSERVE_CLOCK_SHIFT 4
-#define BCHP_CLKGEN_HVD_SID0_TOP_INST_OBSERVE_CLOCK_HVD_ENABLE_DIVIDER_OBSERVE_CLOCK_DEFAULT 0x00000000
-
-/* CLKGEN :: HVD_SID0_TOP_INST_OBSERVE_CLOCK :: HVD_CONTROL_OBSERVE_CLOCK [03:00] */
-#define BCHP_CLKGEN_HVD_SID0_TOP_INST_OBSERVE_CLOCK_HVD_CONTROL_OBSERVE_CLOCK_MASK 0x0000000f
-#define BCHP_CLKGEN_HVD_SID0_TOP_INST_OBSERVE_CLOCK_HVD_CONTROL_OBSERVE_CLOCK_SHIFT 0
-#define BCHP_CLKGEN_HVD_SID0_TOP_INST_OBSERVE_CLOCK_HVD_CONTROL_OBSERVE_CLOCK_DEFAULT 0x00000000
-
-/***************************************************************************
- *INTERNAL_MUX_SELECT - Mux selects for Internal clocks
- ***************************************************************************/
-/* CLKGEN :: INTERNAL_MUX_SELECT :: reserved0 [31:02] */
-#define BCHP_CLKGEN_INTERNAL_MUX_SELECT_reserved0_MASK 0xfffffffc
-#define BCHP_CLKGEN_INTERNAL_MUX_SELECT_reserved0_SHIFT 2
-
-/* CLKGEN :: INTERNAL_MUX_SELECT :: PLLAUDIO1_REFERENCE_CLOCK [01:01] */
-#define BCHP_CLKGEN_INTERNAL_MUX_SELECT_PLLAUDIO1_REFERENCE_CLOCK_MASK 0x00000002
-#define BCHP_CLKGEN_INTERNAL_MUX_SELECT_PLLAUDIO1_REFERENCE_CLOCK_SHIFT 1
-#define BCHP_CLKGEN_INTERNAL_MUX_SELECT_PLLAUDIO1_REFERENCE_CLOCK_DEFAULT 0x00000000
-
-/* CLKGEN :: INTERNAL_MUX_SELECT :: PLLAUDIO0_REFERENCE_CLOCK [00:00] */
-#define BCHP_CLKGEN_INTERNAL_MUX_SELECT_PLLAUDIO0_REFERENCE_CLOCK_MASK 0x00000001
-#define BCHP_CLKGEN_INTERNAL_MUX_SELECT_PLLAUDIO0_REFERENCE_CLOCK_SHIFT 0
-#define BCHP_CLKGEN_INTERNAL_MUX_SELECT_PLLAUDIO0_REFERENCE_CLOCK_DEFAULT 0x00000000
-
-/***************************************************************************
- *ITU656_0_MUX_SELECT - Mux selects for itu656_0 clocks
- ***************************************************************************/
-/* CLKGEN :: ITU656_0_MUX_SELECT :: reserved0 [31:02] */
-#define BCHP_CLKGEN_ITU656_0_MUX_SELECT_reserved0_MASK 0xfffffffc
-#define BCHP_CLKGEN_ITU656_0_MUX_SELECT_reserved0_SHIFT 2
-
-/* CLKGEN :: ITU656_0_MUX_SELECT :: VEC_ITU656_0_CLOCK [01:01] */
-#define BCHP_CLKGEN_ITU656_0_MUX_SELECT_VEC_ITU656_0_CLOCK_MASK 0x00000002
-#define BCHP_CLKGEN_ITU656_0_MUX_SELECT_VEC_ITU656_0_CLOCK_SHIFT 1
-#define BCHP_CLKGEN_ITU656_0_MUX_SELECT_VEC_ITU656_0_CLOCK_DEFAULT 0x00000000
-
-/* CLKGEN :: ITU656_0_MUX_SELECT :: ENABLE_INVERT_VEC_ITU656_0_CLOCK [00:00] */
-#define BCHP_CLKGEN_ITU656_0_MUX_SELECT_ENABLE_INVERT_VEC_ITU656_0_CLOCK_MASK 0x00000001
-#define BCHP_CLKGEN_ITU656_0_MUX_SELECT_ENABLE_INVERT_VEC_ITU656_0_CLOCK_SHIFT 0
-#define BCHP_CLKGEN_ITU656_0_MUX_SELECT_ENABLE_INVERT_VEC_ITU656_0_CLOCK_DEFAULT 0x00000000
-
-/***************************************************************************
- *MEMSYS_32_0_INST_CLOCK_ENABLE - Memsys 32 0 inst clock enable
- ***************************************************************************/
-/* CLKGEN :: MEMSYS_32_0_INST_CLOCK_ENABLE :: reserved0 [31:04] */
-#define BCHP_CLKGEN_MEMSYS_32_0_INST_CLOCK_ENABLE_reserved0_MASK 0xfffffff0
-#define BCHP_CLKGEN_MEMSYS_32_0_INST_CLOCK_ENABLE_reserved0_SHIFT 4
-
-/* CLKGEN :: MEMSYS_32_0_INST_CLOCK_ENABLE :: MEMSYS_108_CLOCK_ENABLE [03:03] */
-#define BCHP_CLKGEN_MEMSYS_32_0_INST_CLOCK_ENABLE_MEMSYS_108_CLOCK_ENABLE_MASK 0x00000008
-#define BCHP_CLKGEN_MEMSYS_32_0_INST_CLOCK_ENABLE_MEMSYS_108_CLOCK_ENABLE_SHIFT 3
-#define BCHP_CLKGEN_MEMSYS_32_0_INST_CLOCK_ENABLE_MEMSYS_108_CLOCK_ENABLE_DEFAULT 0x00000001
-
-/* CLKGEN :: MEMSYS_32_0_INST_CLOCK_ENABLE :: MEMSYS_SCB_CLOCK_ENABLE [02:02] */
-#define BCHP_CLKGEN_MEMSYS_32_0_INST_CLOCK_ENABLE_MEMSYS_SCB_CLOCK_ENABLE_MASK 0x00000004
-#define BCHP_CLKGEN_MEMSYS_32_0_INST_CLOCK_ENABLE_MEMSYS_SCB_CLOCK_ENABLE_SHIFT 2
-#define BCHP_CLKGEN_MEMSYS_32_0_INST_CLOCK_ENABLE_MEMSYS_SCB_CLOCK_ENABLE_DEFAULT 0x00000001
-
-/* CLKGEN :: MEMSYS_32_0_INST_CLOCK_ENABLE :: MEMSYS_GISB_CLOCK_ENABLE [01:01] */
-#define BCHP_CLKGEN_MEMSYS_32_0_INST_CLOCK_ENABLE_MEMSYS_GISB_CLOCK_ENABLE_MASK 0x00000002
-#define BCHP_CLKGEN_MEMSYS_32_0_INST_CLOCK_ENABLE_MEMSYS_GISB_CLOCK_ENABLE_SHIFT 1
-#define BCHP_CLKGEN_MEMSYS_32_0_INST_CLOCK_ENABLE_MEMSYS_GISB_CLOCK_ENABLE_DEFAULT 0x00000001
-
-/* CLKGEN :: MEMSYS_32_0_INST_CLOCK_ENABLE :: MEMSYS_54_CLOCK_ENABLE [00:00] */
-#define BCHP_CLKGEN_MEMSYS_32_0_INST_CLOCK_ENABLE_MEMSYS_54_CLOCK_ENABLE_MASK 0x00000001
-#define BCHP_CLKGEN_MEMSYS_32_0_INST_CLOCK_ENABLE_MEMSYS_54_CLOCK_ENABLE_SHIFT 0
-#define BCHP_CLKGEN_MEMSYS_32_0_INST_CLOCK_ENABLE_MEMSYS_54_CLOCK_ENABLE_DEFAULT 0x00000001
-
-/***************************************************************************
- *MEMSYS_32_0_INST_CLOCK_ENABLE_STATUS - Clock Enable Status
- ***************************************************************************/
-/* CLKGEN :: MEMSYS_32_0_INST_CLOCK_ENABLE_STATUS :: reserved0 [31:04] */
-#define BCHP_CLKGEN_MEMSYS_32_0_INST_CLOCK_ENABLE_STATUS_reserved0_MASK 0xfffffff0
-#define BCHP_CLKGEN_MEMSYS_32_0_INST_CLOCK_ENABLE_STATUS_reserved0_SHIFT 4
-
-/* CLKGEN :: MEMSYS_32_0_INST_CLOCK_ENABLE_STATUS :: MEMSYS_108_CLOCK_ENABLE_STATUS [03:03] */
-#define BCHP_CLKGEN_MEMSYS_32_0_INST_CLOCK_ENABLE_STATUS_MEMSYS_108_CLOCK_ENABLE_STATUS_MASK 0x00000008
-#define BCHP_CLKGEN_MEMSYS_32_0_INST_CLOCK_ENABLE_STATUS_MEMSYS_108_CLOCK_ENABLE_STATUS_SHIFT 3
-
-/* CLKGEN :: MEMSYS_32_0_INST_CLOCK_ENABLE_STATUS :: MEMSYS_SCB_CLOCK_ENABLE_STATUS [02:02] */
-#define BCHP_CLKGEN_MEMSYS_32_0_INST_CLOCK_ENABLE_STATUS_MEMSYS_SCB_CLOCK_ENABLE_STATUS_MASK 0x00000004
-#define BCHP_CLKGEN_MEMSYS_32_0_INST_CLOCK_ENABLE_STATUS_MEMSYS_SCB_CLOCK_ENABLE_STATUS_SHIFT 2
-
-/* CLKGEN :: MEMSYS_32_0_INST_CLOCK_ENABLE_STATUS :: MEMSYS_GISB_CLOCK_ENABLE_STATUS [01:01] */
-#define BCHP_CLKGEN_MEMSYS_32_0_INST_CLOCK_ENABLE_STATUS_MEMSYS_GISB_CLOCK_ENABLE_STATUS_MASK 0x00000002
-#define BCHP_CLKGEN_MEMSYS_32_0_INST_CLOCK_ENABLE_STATUS_MEMSYS_GISB_CLOCK_ENABLE_STATUS_SHIFT 1
-
-/* CLKGEN :: MEMSYS_32_0_INST_CLOCK_ENABLE_STATUS :: MEMSYS_54_CLOCK_ENABLE_STATUS [00:00] */
-#define BCHP_CLKGEN_MEMSYS_32_0_INST_CLOCK_ENABLE_STATUS_MEMSYS_54_CLOCK_ENABLE_STATUS_MASK 0x00000001
-#define BCHP_CLKGEN_MEMSYS_32_0_INST_CLOCK_ENABLE_STATUS_MEMSYS_54_CLOCK_ENABLE_STATUS_SHIFT 0
-
-/***************************************************************************
- *MEMSYS_32_0_INST_OBSERVE_CLOCK - Memsys 32 0 inst observe clock
- ***************************************************************************/
-/* CLKGEN :: MEMSYS_32_0_INST_OBSERVE_CLOCK :: reserved0 [31:06] */
-#define BCHP_CLKGEN_MEMSYS_32_0_INST_OBSERVE_CLOCK_reserved0_MASK 0xffffffc0
-#define BCHP_CLKGEN_MEMSYS_32_0_INST_OBSERVE_CLOCK_reserved0_SHIFT 6
-
-/* CLKGEN :: MEMSYS_32_0_INST_OBSERVE_CLOCK :: MEMSYS_ENABLE_OBSERVE_CLOCK [05:05] */
-#define BCHP_CLKGEN_MEMSYS_32_0_INST_OBSERVE_CLOCK_MEMSYS_ENABLE_OBSERVE_CLOCK_MASK 0x00000020
-#define BCHP_CLKGEN_MEMSYS_32_0_INST_OBSERVE_CLOCK_MEMSYS_ENABLE_OBSERVE_CLOCK_SHIFT 5
-#define BCHP_CLKGEN_MEMSYS_32_0_INST_OBSERVE_CLOCK_MEMSYS_ENABLE_OBSERVE_CLOCK_DEFAULT 0x00000000
-
-/* CLKGEN :: MEMSYS_32_0_INST_OBSERVE_CLOCK :: MEMSYS_ENABLE_DIVIDER_OBSERVE_CLOCK [04:04] */
-#define BCHP_CLKGEN_MEMSYS_32_0_INST_OBSERVE_CLOCK_MEMSYS_ENABLE_DIVIDER_OBSERVE_CLOCK_MASK 0x00000010
-#define BCHP_CLKGEN_MEMSYS_32_0_INST_OBSERVE_CLOCK_MEMSYS_ENABLE_DIVIDER_OBSERVE_CLOCK_SHIFT 4
-#define BCHP_CLKGEN_MEMSYS_32_0_INST_OBSERVE_CLOCK_MEMSYS_ENABLE_DIVIDER_OBSERVE_CLOCK_DEFAULT 0x00000000
-
-/* CLKGEN :: MEMSYS_32_0_INST_OBSERVE_CLOCK :: MEMSYS_CONTROL_OBSERVE_CLOCK [03:00] */
-#define BCHP_CLKGEN_MEMSYS_32_0_INST_OBSERVE_CLOCK_MEMSYS_CONTROL_OBSERVE_CLOCK_MASK 0x0000000f
-#define BCHP_CLKGEN_MEMSYS_32_0_INST_OBSERVE_CLOCK_MEMSYS_CONTROL_OBSERVE_CLOCK_SHIFT 0
-#define BCHP_CLKGEN_MEMSYS_32_0_INST_OBSERVE_CLOCK_MEMSYS_CONTROL_OBSERVE_CLOCK_DEFAULT 0x00000000
-
-/***************************************************************************
- *MEMSYS_32_0_INST_STATUS - Memsys 32 0 inst status
- ***************************************************************************/
-/* CLKGEN :: MEMSYS_32_0_INST_STATUS :: reserved0 [31:01] */
-#define BCHP_CLKGEN_MEMSYS_32_0_INST_STATUS_reserved0_MASK 0xfffffffe
-#define BCHP_CLKGEN_MEMSYS_32_0_INST_STATUS_reserved0_SHIFT 1
-
-/* CLKGEN :: MEMSYS_32_0_INST_STATUS :: MEMSYS_PLL_LOCKED_STATUS [00:00] */
-#define BCHP_CLKGEN_MEMSYS_32_0_INST_STATUS_MEMSYS_PLL_LOCKED_STATUS_MASK 0x00000001
-#define BCHP_CLKGEN_MEMSYS_32_0_INST_STATUS_MEMSYS_PLL_LOCKED_STATUS_SHIFT 0
-
-/***************************************************************************
- *MOCAMAC_TOP_INST_CLOCK_ENABLE - Mocamac top inst clock enable
- ***************************************************************************/
-/* CLKGEN :: MOCAMAC_TOP_INST_CLOCK_ENABLE :: reserved0 [31:03] */
-#define BCHP_CLKGEN_MOCAMAC_TOP_INST_CLOCK_ENABLE_reserved0_MASK 0xfffffff8
-#define BCHP_CLKGEN_MOCAMAC_TOP_INST_CLOCK_ENABLE_reserved0_SHIFT 3
-
-/* CLKGEN :: MOCAMAC_TOP_INST_CLOCK_ENABLE :: MOCAMAC_SCB_CLOCK_ENABLE [02:02] */
-#define BCHP_CLKGEN_MOCAMAC_TOP_INST_CLOCK_ENABLE_MOCAMAC_SCB_CLOCK_ENABLE_MASK 0x00000004
-#define BCHP_CLKGEN_MOCAMAC_TOP_INST_CLOCK_ENABLE_MOCAMAC_SCB_CLOCK_ENABLE_SHIFT 2
-#define BCHP_CLKGEN_MOCAMAC_TOP_INST_CLOCK_ENABLE_MOCAMAC_SCB_CLOCK_ENABLE_DEFAULT 0x00000001
-
-/* CLKGEN :: MOCAMAC_TOP_INST_CLOCK_ENABLE :: MOCAMAC_GISB_CLOCK_ENABLE [01:01] */
-#define BCHP_CLKGEN_MOCAMAC_TOP_INST_CLOCK_ENABLE_MOCAMAC_GISB_CLOCK_ENABLE_MASK 0x00000002
-#define BCHP_CLKGEN_MOCAMAC_TOP_INST_CLOCK_ENABLE_MOCAMAC_GISB_CLOCK_ENABLE_SHIFT 1
-#define BCHP_CLKGEN_MOCAMAC_TOP_INST_CLOCK_ENABLE_MOCAMAC_GISB_CLOCK_ENABLE_DEFAULT 0x00000001
-
-/* CLKGEN :: MOCAMAC_TOP_INST_CLOCK_ENABLE :: MOCAMAC_54_CLOCK_ENABLE [00:00] */
-#define BCHP_CLKGEN_MOCAMAC_TOP_INST_CLOCK_ENABLE_MOCAMAC_54_CLOCK_ENABLE_MASK 0x00000001
-#define BCHP_CLKGEN_MOCAMAC_TOP_INST_CLOCK_ENABLE_MOCAMAC_54_CLOCK_ENABLE_SHIFT 0
-#define BCHP_CLKGEN_MOCAMAC_TOP_INST_CLOCK_ENABLE_MOCAMAC_54_CLOCK_ENABLE_DEFAULT 0x00000001
-
-/***************************************************************************
- *MOCAMAC_TOP_INST_CLOCK_ENABLE_STATUS - Clock Enable Status
- ***************************************************************************/
-/* CLKGEN :: MOCAMAC_TOP_INST_CLOCK_ENABLE_STATUS :: reserved0 [31:03] */
-#define BCHP_CLKGEN_MOCAMAC_TOP_INST_CLOCK_ENABLE_STATUS_reserved0_MASK 0xfffffff8
-#define BCHP_CLKGEN_MOCAMAC_TOP_INST_CLOCK_ENABLE_STATUS_reserved0_SHIFT 3
-
-/* CLKGEN :: MOCAMAC_TOP_INST_CLOCK_ENABLE_STATUS :: MOCAMAC_SCB_CLOCK_ENABLE_STATUS [02:02] */
-#define BCHP_CLKGEN_MOCAMAC_TOP_INST_CLOCK_ENABLE_STATUS_MOCAMAC_SCB_CLOCK_ENABLE_STATUS_MASK 0x00000004
-#define BCHP_CLKGEN_MOCAMAC_TOP_INST_CLOCK_ENABLE_STATUS_MOCAMAC_SCB_CLOCK_ENABLE_STATUS_SHIFT 2
-
-/* CLKGEN :: MOCAMAC_TOP_INST_CLOCK_ENABLE_STATUS :: MOCAMAC_GISB_CLOCK_ENABLE_STATUS [01:01] */
-#define BCHP_CLKGEN_MOCAMAC_TOP_INST_CLOCK_ENABLE_STATUS_MOCAMAC_GISB_CLOCK_ENABLE_STATUS_MASK 0x00000002
-#define BCHP_CLKGEN_MOCAMAC_TOP_INST_CLOCK_ENABLE_STATUS_MOCAMAC_GISB_CLOCK_ENABLE_STATUS_SHIFT 1
-
-/* CLKGEN :: MOCAMAC_TOP_INST_CLOCK_ENABLE_STATUS :: MOCAMAC_54_CLOCK_ENABLE_STATUS [00:00] */
-#define BCHP_CLKGEN_MOCAMAC_TOP_INST_CLOCK_ENABLE_STATUS_MOCAMAC_54_CLOCK_ENABLE_STATUS_MASK 0x00000001
-#define BCHP_CLKGEN_MOCAMAC_TOP_INST_CLOCK_ENABLE_STATUS_MOCAMAC_54_CLOCK_ENABLE_STATUS_SHIFT 0
-
-/***************************************************************************
- *MOCAMAC_TOP_INST_OBSERVE_CLOCK - Mocamac top inst observe clock
- ***************************************************************************/
-/* CLKGEN :: MOCAMAC_TOP_INST_OBSERVE_CLOCK :: reserved0 [31:06] */
-#define BCHP_CLKGEN_MOCAMAC_TOP_INST_OBSERVE_CLOCK_reserved0_MASK 0xffffffc0
-#define BCHP_CLKGEN_MOCAMAC_TOP_INST_OBSERVE_CLOCK_reserved0_SHIFT 6
-
-/* CLKGEN :: MOCAMAC_TOP_INST_OBSERVE_CLOCK :: MOCAMAC_ENABLE_OBSERVE_CLOCK [05:05] */
-#define BCHP_CLKGEN_MOCAMAC_TOP_INST_OBSERVE_CLOCK_MOCAMAC_ENABLE_OBSERVE_CLOCK_MASK 0x00000020
-#define BCHP_CLKGEN_MOCAMAC_TOP_INST_OBSERVE_CLOCK_MOCAMAC_ENABLE_OBSERVE_CLOCK_SHIFT 5
-#define BCHP_CLKGEN_MOCAMAC_TOP_INST_OBSERVE_CLOCK_MOCAMAC_ENABLE_OBSERVE_CLOCK_DEFAULT 0x00000000
-
-/* CLKGEN :: MOCAMAC_TOP_INST_OBSERVE_CLOCK :: MOCAMAC_ENABLE_DIVIDER_OBSERVE_CLOCK [04:04] */
-#define BCHP_CLKGEN_MOCAMAC_TOP_INST_OBSERVE_CLOCK_MOCAMAC_ENABLE_DIVIDER_OBSERVE_CLOCK_MASK 0x00000010
-#define BCHP_CLKGEN_MOCAMAC_TOP_INST_OBSERVE_CLOCK_MOCAMAC_ENABLE_DIVIDER_OBSERVE_CLOCK_SHIFT 4
-#define BCHP_CLKGEN_MOCAMAC_TOP_INST_OBSERVE_CLOCK_MOCAMAC_ENABLE_DIVIDER_OBSERVE_CLOCK_DEFAULT 0x00000000
-
-/* CLKGEN :: MOCAMAC_TOP_INST_OBSERVE_CLOCK :: MOCAMAC_CONTROL_OBSERVE_CLOCK [03:00] */
-#define BCHP_CLKGEN_MOCAMAC_TOP_INST_OBSERVE_CLOCK_MOCAMAC_CONTROL_OBSERVE_CLOCK_MASK 0x0000000f
-#define BCHP_CLKGEN_MOCAMAC_TOP_INST_OBSERVE_CLOCK_MOCAMAC_CONTROL_OBSERVE_CLOCK_SHIFT 0
-#define BCHP_CLKGEN_MOCAMAC_TOP_INST_OBSERVE_CLOCK_MOCAMAC_CONTROL_OBSERVE_CLOCK_DEFAULT 0x00000000
-
-/***************************************************************************
- *MOCAPHY_TOP_INST_CLOCK_ENABLE - Mocaphy top inst clock enable
- ***************************************************************************/
-/* CLKGEN :: MOCAPHY_TOP_INST_CLOCK_ENABLE :: reserved0 [31:02] */
-#define BCHP_CLKGEN_MOCAPHY_TOP_INST_CLOCK_ENABLE_reserved0_MASK 0xfffffffc
-#define BCHP_CLKGEN_MOCAPHY_TOP_INST_CLOCK_ENABLE_reserved0_SHIFT 2
-
-/* CLKGEN :: MOCAPHY_TOP_INST_CLOCK_ENABLE :: MOCAPHY_GISB_CLOCK_ENABLE [01:01] */
-#define BCHP_CLKGEN_MOCAPHY_TOP_INST_CLOCK_ENABLE_MOCAPHY_GISB_CLOCK_ENABLE_MASK 0x00000002
-#define BCHP_CLKGEN_MOCAPHY_TOP_INST_CLOCK_ENABLE_MOCAPHY_GISB_CLOCK_ENABLE_SHIFT 1
-#define BCHP_CLKGEN_MOCAPHY_TOP_INST_CLOCK_ENABLE_MOCAPHY_GISB_CLOCK_ENABLE_DEFAULT 0x00000001
-
-/* CLKGEN :: MOCAPHY_TOP_INST_CLOCK_ENABLE :: MOCAPHY_54_CLOCK_ENABLE [00:00] */
-#define BCHP_CLKGEN_MOCAPHY_TOP_INST_CLOCK_ENABLE_MOCAPHY_54_CLOCK_ENABLE_MASK 0x00000001
-#define BCHP_CLKGEN_MOCAPHY_TOP_INST_CLOCK_ENABLE_MOCAPHY_54_CLOCK_ENABLE_SHIFT 0
-#define BCHP_CLKGEN_MOCAPHY_TOP_INST_CLOCK_ENABLE_MOCAPHY_54_CLOCK_ENABLE_DEFAULT 0x00000001
-
-/***************************************************************************
- *MOCAPHY_TOP_INST_CLOCK_ENABLE_STATUS - Clock Enable Status
- ***************************************************************************/
-/* CLKGEN :: MOCAPHY_TOP_INST_CLOCK_ENABLE_STATUS :: reserved0 [31:02] */
-#define BCHP_CLKGEN_MOCAPHY_TOP_INST_CLOCK_ENABLE_STATUS_reserved0_MASK 0xfffffffc
-#define BCHP_CLKGEN_MOCAPHY_TOP_INST_CLOCK_ENABLE_STATUS_reserved0_SHIFT 2
-
-/* CLKGEN :: MOCAPHY_TOP_INST_CLOCK_ENABLE_STATUS :: MOCAPHY_GISB_CLOCK_ENABLE_STATUS [01:01] */
-#define BCHP_CLKGEN_MOCAPHY_TOP_INST_CLOCK_ENABLE_STATUS_MOCAPHY_GISB_CLOCK_ENABLE_STATUS_MASK 0x00000002
-#define BCHP_CLKGEN_MOCAPHY_TOP_INST_CLOCK_ENABLE_STATUS_MOCAPHY_GISB_CLOCK_ENABLE_STATUS_SHIFT 1
-
-/* CLKGEN :: MOCAPHY_TOP_INST_CLOCK_ENABLE_STATUS :: MOCAPHY_54_CLOCK_ENABLE_STATUS [00:00] */
-#define BCHP_CLKGEN_MOCAPHY_TOP_INST_CLOCK_ENABLE_STATUS_MOCAPHY_54_CLOCK_ENABLE_STATUS_MASK 0x00000001
-#define BCHP_CLKGEN_MOCAPHY_TOP_INST_CLOCK_ENABLE_STATUS_MOCAPHY_54_CLOCK_ENABLE_STATUS_SHIFT 0
-
-/***************************************************************************
- *MOCAPHY_TOP_INST_OBSERVE_CLOCK - Mocaphy top inst observe clock
- ***************************************************************************/
-/* CLKGEN :: MOCAPHY_TOP_INST_OBSERVE_CLOCK :: reserved0 [31:06] */
-#define BCHP_CLKGEN_MOCAPHY_TOP_INST_OBSERVE_CLOCK_reserved0_MASK 0xffffffc0
-#define BCHP_CLKGEN_MOCAPHY_TOP_INST_OBSERVE_CLOCK_reserved0_SHIFT 6
-
-/* CLKGEN :: MOCAPHY_TOP_INST_OBSERVE_CLOCK :: MOCAPHY_ENABLE_OBSERVE_CLOCK [05:05] */
-#define BCHP_CLKGEN_MOCAPHY_TOP_INST_OBSERVE_CLOCK_MOCAPHY_ENABLE_OBSERVE_CLOCK_MASK 0x00000020
-#define BCHP_CLKGEN_MOCAPHY_TOP_INST_OBSERVE_CLOCK_MOCAPHY_ENABLE_OBSERVE_CLOCK_SHIFT 5
-#define BCHP_CLKGEN_MOCAPHY_TOP_INST_OBSERVE_CLOCK_MOCAPHY_ENABLE_OBSERVE_CLOCK_DEFAULT 0x00000000
-
-/* CLKGEN :: MOCAPHY_TOP_INST_OBSERVE_CLOCK :: MOCAPHY_ENABLE_DIVIDER_OBSERVE_CLOCK [04:04] */
-#define BCHP_CLKGEN_MOCAPHY_TOP_INST_OBSERVE_CLOCK_MOCAPHY_ENABLE_DIVIDER_OBSERVE_CLOCK_MASK 0x00000010
-#define BCHP_CLKGEN_MOCAPHY_TOP_INST_OBSERVE_CLOCK_MOCAPHY_ENABLE_DIVIDER_OBSERVE_CLOCK_SHIFT 4
-#define BCHP_CLKGEN_MOCAPHY_TOP_INST_OBSERVE_CLOCK_MOCAPHY_ENABLE_DIVIDER_OBSERVE_CLOCK_DEFAULT 0x00000000
-
-/* CLKGEN :: MOCAPHY_TOP_INST_OBSERVE_CLOCK :: MOCAPHY_CONTROL_OBSERVE_CLOCK [03:00] */
-#define BCHP_CLKGEN_MOCAPHY_TOP_INST_OBSERVE_CLOCK_MOCAPHY_CONTROL_OBSERVE_CLOCK_MASK 0x0000000f
-#define BCHP_CLKGEN_MOCAPHY_TOP_INST_OBSERVE_CLOCK_MOCAPHY_CONTROL_OBSERVE_CLOCK_SHIFT 0
-#define BCHP_CLKGEN_MOCAPHY_TOP_INST_OBSERVE_CLOCK_MOCAPHY_CONTROL_OBSERVE_CLOCK_DEFAULT 0x00000000
-
-/***************************************************************************
- *PAD_BYP_CLK_0_OBSERVATION - Select observation clk
- ***************************************************************************/
-/* CLKGEN :: PAD_BYP_CLK_0_OBSERVATION :: reserved0 [31:08] */
-#define BCHP_CLKGEN_PAD_BYP_CLK_0_OBSERVATION_reserved0_MASK 0xffffff00
-#define BCHP_CLKGEN_PAD_BYP_CLK_0_OBSERVATION_reserved0_SHIFT 8
-
-/* CLKGEN :: PAD_BYP_CLK_0_OBSERVATION :: SELECT_OBSERVE_CLK [07:07] */
-#define BCHP_CLKGEN_PAD_BYP_CLK_0_OBSERVATION_SELECT_OBSERVE_CLK_MASK 0x00000080
-#define BCHP_CLKGEN_PAD_BYP_CLK_0_OBSERVATION_SELECT_OBSERVE_CLK_SHIFT 7
-#define BCHP_CLKGEN_PAD_BYP_CLK_0_OBSERVATION_SELECT_OBSERVE_CLK_DEFAULT 0x00000000
-
-/* CLKGEN :: PAD_BYP_CLK_0_OBSERVATION :: OBSERVE_MUX_SELECT [06:01] */
-#define BCHP_CLKGEN_PAD_BYP_CLK_0_OBSERVATION_OBSERVE_MUX_SELECT_MASK 0x0000007e
-#define BCHP_CLKGEN_PAD_BYP_CLK_0_OBSERVATION_OBSERVE_MUX_SELECT_SHIFT 1
-#define BCHP_CLKGEN_PAD_BYP_CLK_0_OBSERVATION_OBSERVE_MUX_SELECT_DEFAULT 0x00000000
-
-/* CLKGEN :: PAD_BYP_CLK_0_OBSERVATION :: OBSERVE_DIV_ENABLE [00:00] */
-#define BCHP_CLKGEN_PAD_BYP_CLK_0_OBSERVATION_OBSERVE_DIV_ENABLE_MASK 0x00000001
-#define BCHP_CLKGEN_PAD_BYP_CLK_0_OBSERVATION_OBSERVE_DIV_ENABLE_SHIFT 0
-#define BCHP_CLKGEN_PAD_BYP_CLK_0_OBSERVATION_OBSERVE_DIV_ENABLE_DEFAULT 0x00000000
-
-/***************************************************************************
- *PAD_BYP_CLK_1_OBSERVATION - Select observation clk
- ***************************************************************************/
-/* CLKGEN :: PAD_BYP_CLK_1_OBSERVATION :: reserved0 [31:08] */
-#define BCHP_CLKGEN_PAD_BYP_CLK_1_OBSERVATION_reserved0_MASK 0xffffff00
-#define BCHP_CLKGEN_PAD_BYP_CLK_1_OBSERVATION_reserved0_SHIFT 8
-
-/* CLKGEN :: PAD_BYP_CLK_1_OBSERVATION :: SELECT_OBSERVE_CLK [07:07] */
-#define BCHP_CLKGEN_PAD_BYP_CLK_1_OBSERVATION_SELECT_OBSERVE_CLK_MASK 0x00000080
-#define BCHP_CLKGEN_PAD_BYP_CLK_1_OBSERVATION_SELECT_OBSERVE_CLK_SHIFT 7
-#define BCHP_CLKGEN_PAD_BYP_CLK_1_OBSERVATION_SELECT_OBSERVE_CLK_DEFAULT 0x00000000
-
-/* CLKGEN :: PAD_BYP_CLK_1_OBSERVATION :: OBSERVE_MUX_SELECT [06:01] */
-#define BCHP_CLKGEN_PAD_BYP_CLK_1_OBSERVATION_OBSERVE_MUX_SELECT_MASK 0x0000007e
-#define BCHP_CLKGEN_PAD_BYP_CLK_1_OBSERVATION_OBSERVE_MUX_SELECT_SHIFT 1
-#define BCHP_CLKGEN_PAD_BYP_CLK_1_OBSERVATION_OBSERVE_MUX_SELECT_DEFAULT 0x00000000
-
-/* CLKGEN :: PAD_BYP_CLK_1_OBSERVATION :: OBSERVE_DIV_ENABLE [00:00] */
-#define BCHP_CLKGEN_PAD_BYP_CLK_1_OBSERVATION_OBSERVE_DIV_ENABLE_MASK 0x00000001
-#define BCHP_CLKGEN_PAD_BYP_CLK_1_OBSERVATION_OBSERVE_DIV_ENABLE_SHIFT 0
-#define BCHP_CLKGEN_PAD_BYP_CLK_1_OBSERVATION_OBSERVE_DIV_ENABLE_DEFAULT 0x00000000
-
-/***************************************************************************
- *PAD_CLOCK_DISABLE - Disable PAD's clocks
- ***************************************************************************/
-/* CLKGEN :: PAD_CLOCK_DISABLE :: reserved0 [31:04] */
-#define BCHP_CLKGEN_PAD_CLOCK_DISABLE_reserved0_MASK 0xfffffff0
-#define BCHP_CLKGEN_PAD_CLOCK_DISABLE_reserved0_SHIFT 4
-
-/* CLKGEN :: PAD_CLOCK_DISABLE :: DISABLE_PAD_OUTPUT_SC_CLOCK [03:03] */
-#define BCHP_CLKGEN_PAD_CLOCK_DISABLE_DISABLE_PAD_OUTPUT_SC_CLOCK_MASK 0x00000008
-#define BCHP_CLKGEN_PAD_CLOCK_DISABLE_DISABLE_PAD_OUTPUT_SC_CLOCK_SHIFT 3
-#define BCHP_CLKGEN_PAD_CLOCK_DISABLE_DISABLE_PAD_OUTPUT_SC_CLOCK_DEFAULT 0x00000000
-
-/* CLKGEN :: PAD_CLOCK_DISABLE :: DISABLE_PAD_OUTPUT_CODECMCLK_CLOCK [02:02] */
-#define BCHP_CLKGEN_PAD_CLOCK_DISABLE_DISABLE_PAD_OUTPUT_CODECMCLK_CLOCK_MASK 0x00000004
-#define BCHP_CLKGEN_PAD_CLOCK_DISABLE_DISABLE_PAD_OUTPUT_CODECMCLK_CLOCK_SHIFT 2
-#define BCHP_CLKGEN_PAD_CLOCK_DISABLE_DISABLE_PAD_OUTPUT_CODECMCLK_CLOCK_DEFAULT 0x00000000
-
-/* CLKGEN :: PAD_CLOCK_DISABLE :: DISABLE_PAD_OUTPUT_BYPCLK1_CLOCK [01:01] */
-#define BCHP_CLKGEN_PAD_CLOCK_DISABLE_DISABLE_PAD_OUTPUT_BYPCLK1_CLOCK_MASK 0x00000002
-#define BCHP_CLKGEN_PAD_CLOCK_DISABLE_DISABLE_PAD_OUTPUT_BYPCLK1_CLOCK_SHIFT 1
-#define BCHP_CLKGEN_PAD_CLOCK_DISABLE_DISABLE_PAD_OUTPUT_BYPCLK1_CLOCK_DEFAULT 0x00000000
-
-/* CLKGEN :: PAD_CLOCK_DISABLE :: DISABLE_PAD_OUTPUT_BYPCLK0_CLOCK [00:00] */
-#define BCHP_CLKGEN_PAD_CLOCK_DISABLE_DISABLE_PAD_OUTPUT_BYPCLK0_CLOCK_MASK 0x00000001
-#define BCHP_CLKGEN_PAD_CLOCK_DISABLE_DISABLE_PAD_OUTPUT_BYPCLK0_CLOCK_SHIFT 0
-#define BCHP_CLKGEN_PAD_CLOCK_DISABLE_DISABLE_PAD_OUTPUT_BYPCLK0_CLOCK_DEFAULT 0x00000000
-
-/***************************************************************************
- *PAD_CLOCK_DISABLE_STATUS - Clock Disable Status
- ***************************************************************************/
-/* CLKGEN :: PAD_CLOCK_DISABLE_STATUS :: reserved0 [31:04] */
-#define BCHP_CLKGEN_PAD_CLOCK_DISABLE_STATUS_reserved0_MASK 0xfffffff0
-#define BCHP_CLKGEN_PAD_CLOCK_DISABLE_STATUS_reserved0_SHIFT 4
-
-/* CLKGEN :: PAD_CLOCK_DISABLE_STATUS :: DISABLE_PAD_OUTPUT_SC_CLOCK_STATUS [03:03] */
-#define BCHP_CLKGEN_PAD_CLOCK_DISABLE_STATUS_DISABLE_PAD_OUTPUT_SC_CLOCK_STATUS_MASK 0x00000008
-#define BCHP_CLKGEN_PAD_CLOCK_DISABLE_STATUS_DISABLE_PAD_OUTPUT_SC_CLOCK_STATUS_SHIFT 3
-
-/* CLKGEN :: PAD_CLOCK_DISABLE_STATUS :: DISABLE_PAD_OUTPUT_CODECMCLK_CLOCK_STATUS [02:02] */
-#define BCHP_CLKGEN_PAD_CLOCK_DISABLE_STATUS_DISABLE_PAD_OUTPUT_CODECMCLK_CLOCK_STATUS_MASK 0x00000004
-#define BCHP_CLKGEN_PAD_CLOCK_DISABLE_STATUS_DISABLE_PAD_OUTPUT_CODECMCLK_CLOCK_STATUS_SHIFT 2
-
-/* CLKGEN :: PAD_CLOCK_DISABLE_STATUS :: DISABLE_PAD_OUTPUT_BYPCLK1_CLOCK_STATUS [01:01] */
-#define BCHP_CLKGEN_PAD_CLOCK_DISABLE_STATUS_DISABLE_PAD_OUTPUT_BYPCLK1_CLOCK_STATUS_MASK 0x00000002
-#define BCHP_CLKGEN_PAD_CLOCK_DISABLE_STATUS_DISABLE_PAD_OUTPUT_BYPCLK1_CLOCK_STATUS_SHIFT 1
-
-/* CLKGEN :: PAD_CLOCK_DISABLE_STATUS :: DISABLE_PAD_OUTPUT_BYPCLK0_CLOCK_STATUS [00:00] */
-#define BCHP_CLKGEN_PAD_CLOCK_DISABLE_STATUS_DISABLE_PAD_OUTPUT_BYPCLK0_CLOCK_STATUS_MASK 0x00000001
-#define BCHP_CLKGEN_PAD_CLOCK_DISABLE_STATUS_DISABLE_PAD_OUTPUT_BYPCLK0_CLOCK_STATUS_SHIFT 0
-
-/***************************************************************************
- *PAD_CODEC_MCLK_OBSERVATION - Select observation clk
- ***************************************************************************/
-/* CLKGEN :: PAD_CODEC_MCLK_OBSERVATION :: reserved0 [31:08] */
-#define BCHP_CLKGEN_PAD_CODEC_MCLK_OBSERVATION_reserved0_MASK 0xffffff00
-#define BCHP_CLKGEN_PAD_CODEC_MCLK_OBSERVATION_reserved0_SHIFT 8
-
-/* CLKGEN :: PAD_CODEC_MCLK_OBSERVATION :: SELECT_OBSERVE_CLK [07:07] */
-#define BCHP_CLKGEN_PAD_CODEC_MCLK_OBSERVATION_SELECT_OBSERVE_CLK_MASK 0x00000080
-#define BCHP_CLKGEN_PAD_CODEC_MCLK_OBSERVATION_SELECT_OBSERVE_CLK_SHIFT 7
-#define BCHP_CLKGEN_PAD_CODEC_MCLK_OBSERVATION_SELECT_OBSERVE_CLK_DEFAULT 0x00000000
-
-/* CLKGEN :: PAD_CODEC_MCLK_OBSERVATION :: OBSERVE_MUX_SELECT [06:01] */
-#define BCHP_CLKGEN_PAD_CODEC_MCLK_OBSERVATION_OBSERVE_MUX_SELECT_MASK 0x0000007e
-#define BCHP_CLKGEN_PAD_CODEC_MCLK_OBSERVATION_OBSERVE_MUX_SELECT_SHIFT 1
-#define BCHP_CLKGEN_PAD_CODEC_MCLK_OBSERVATION_OBSERVE_MUX_SELECT_DEFAULT 0x00000000
-
-/* CLKGEN :: PAD_CODEC_MCLK_OBSERVATION :: OBSERVE_DIV_ENABLE [00:00] */
-#define BCHP_CLKGEN_PAD_CODEC_MCLK_OBSERVATION_OBSERVE_DIV_ENABLE_MASK 0x00000001
-#define BCHP_CLKGEN_PAD_CODEC_MCLK_OBSERVATION_OBSERVE_DIV_ENABLE_SHIFT 0
-#define BCHP_CLKGEN_PAD_CODEC_MCLK_OBSERVATION_OBSERVE_DIV_ENABLE_DEFAULT 0x00000000
-
-/***************************************************************************
- *PAD_MUX_SELECT - Mux selects for Pad clocks
- ***************************************************************************/
-/* CLKGEN :: PAD_MUX_SELECT :: reserved0 [31:01] */
-#define BCHP_CLKGEN_PAD_MUX_SELECT_reserved0_MASK 0xfffffffe
-#define BCHP_CLKGEN_PAD_MUX_SELECT_reserved0_SHIFT 1
-
-/* CLKGEN :: PAD_MUX_SELECT :: PAD_OUTPUT_SC_CLOCK [00:00] */
-#define BCHP_CLKGEN_PAD_MUX_SELECT_PAD_OUTPUT_SC_CLOCK_MASK 0x00000001
-#define BCHP_CLKGEN_PAD_MUX_SELECT_PAD_OUTPUT_SC_CLOCK_SHIFT 0
-#define BCHP_CLKGEN_PAD_MUX_SELECT_PAD_OUTPUT_SC_CLOCK_DEFAULT 0x00000000
-
-/***************************************************************************
- *PCIE_X1_TOP_INST_CLOCK_DISABLE - Disable PCIE_X1_TOP_INST's clocks
- ***************************************************************************/
-/* CLKGEN :: PCIE_X1_TOP_INST_CLOCK_DISABLE :: reserved0 [31:01] */
-#define BCHP_CLKGEN_PCIE_X1_TOP_INST_CLOCK_DISABLE_reserved0_MASK 0xfffffffe
-#define BCHP_CLKGEN_PCIE_X1_TOP_INST_CLOCK_DISABLE_reserved0_SHIFT 1
-
-/* CLKGEN :: PCIE_X1_TOP_INST_CLOCK_DISABLE :: DISABLE_PCIE_ALWAYSON_CLOCK [00:00] */
-#define BCHP_CLKGEN_PCIE_X1_TOP_INST_CLOCK_DISABLE_DISABLE_PCIE_ALWAYSON_CLOCK_MASK 0x00000001
-#define BCHP_CLKGEN_PCIE_X1_TOP_INST_CLOCK_DISABLE_DISABLE_PCIE_ALWAYSON_CLOCK_SHIFT 0
-#define BCHP_CLKGEN_PCIE_X1_TOP_INST_CLOCK_DISABLE_DISABLE_PCIE_ALWAYSON_CLOCK_DEFAULT 0x00000000
-
-/***************************************************************************
- *PCIE_X1_TOP_INST_CLOCK_DISABLE_STATUS - Clock Disable Status
- ***************************************************************************/
-/* CLKGEN :: PCIE_X1_TOP_INST_CLOCK_DISABLE_STATUS :: reserved0 [31:01] */
-#define BCHP_CLKGEN_PCIE_X1_TOP_INST_CLOCK_DISABLE_STATUS_reserved0_MASK 0xfffffffe
-#define BCHP_CLKGEN_PCIE_X1_TOP_INST_CLOCK_DISABLE_STATUS_reserved0_SHIFT 1
-
-/* CLKGEN :: PCIE_X1_TOP_INST_CLOCK_DISABLE_STATUS :: DISABLE_PCIE_ALWAYSON_CLOCK_STATUS [00:00] */
-#define BCHP_CLKGEN_PCIE_X1_TOP_INST_CLOCK_DISABLE_STATUS_DISABLE_PCIE_ALWAYSON_CLOCK_STATUS_MASK 0x00000001
-#define BCHP_CLKGEN_PCIE_X1_TOP_INST_CLOCK_DISABLE_STATUS_DISABLE_PCIE_ALWAYSON_CLOCK_STATUS_SHIFT 0
-
-/***************************************************************************
- *PCIE_X1_TOP_INST_CLOCK_ENABLE - Pcie x1 top inst clock enable
- ***************************************************************************/
-/* CLKGEN :: PCIE_X1_TOP_INST_CLOCK_ENABLE :: reserved0 [31:04] */
-#define BCHP_CLKGEN_PCIE_X1_TOP_INST_CLOCK_ENABLE_reserved0_MASK 0xfffffff0
-#define BCHP_CLKGEN_PCIE_X1_TOP_INST_CLOCK_ENABLE_reserved0_SHIFT 4
-
-/* CLKGEN :: PCIE_X1_TOP_INST_CLOCK_ENABLE :: PCIE_SCB_CLOCK_ENABLE [03:03] */
-#define BCHP_CLKGEN_PCIE_X1_TOP_INST_CLOCK_ENABLE_PCIE_SCB_CLOCK_ENABLE_MASK 0x00000008
-#define BCHP_CLKGEN_PCIE_X1_TOP_INST_CLOCK_ENABLE_PCIE_SCB_CLOCK_ENABLE_SHIFT 3
-#define BCHP_CLKGEN_PCIE_X1_TOP_INST_CLOCK_ENABLE_PCIE_SCB_CLOCK_ENABLE_DEFAULT 0x00000001
-
-/* CLKGEN :: PCIE_X1_TOP_INST_CLOCK_ENABLE :: PCIE_GISB_CLOCK_ENABLE [02:02] */
-#define BCHP_CLKGEN_PCIE_X1_TOP_INST_CLOCK_ENABLE_PCIE_GISB_CLOCK_ENABLE_MASK 0x00000004
-#define BCHP_CLKGEN_PCIE_X1_TOP_INST_CLOCK_ENABLE_PCIE_GISB_CLOCK_ENABLE_SHIFT 2
-#define BCHP_CLKGEN_PCIE_X1_TOP_INST_CLOCK_ENABLE_PCIE_GISB_CLOCK_ENABLE_DEFAULT 0x00000001
-
-/* CLKGEN :: PCIE_X1_TOP_INST_CLOCK_ENABLE :: PCIE_54_CLOCK_ENABLE [01:01] */
-#define BCHP_CLKGEN_PCIE_X1_TOP_INST_CLOCK_ENABLE_PCIE_54_CLOCK_ENABLE_MASK 0x00000002
-#define BCHP_CLKGEN_PCIE_X1_TOP_INST_CLOCK_ENABLE_PCIE_54_CLOCK_ENABLE_SHIFT 1
-#define BCHP_CLKGEN_PCIE_X1_TOP_INST_CLOCK_ENABLE_PCIE_54_CLOCK_ENABLE_DEFAULT 0x00000001
-
-/* CLKGEN :: PCIE_X1_TOP_INST_CLOCK_ENABLE :: PCIE_108_CLOCK_ENABLE [00:00] */
-#define BCHP_CLKGEN_PCIE_X1_TOP_INST_CLOCK_ENABLE_PCIE_108_CLOCK_ENABLE_MASK 0x00000001
-#define BCHP_CLKGEN_PCIE_X1_TOP_INST_CLOCK_ENABLE_PCIE_108_CLOCK_ENABLE_SHIFT 0
-#define BCHP_CLKGEN_PCIE_X1_TOP_INST_CLOCK_ENABLE_PCIE_108_CLOCK_ENABLE_DEFAULT 0x00000001
-
-/***************************************************************************
- *PCIE_X1_TOP_INST_CLOCK_ENABLE_STATUS - Clock Enable Status
- ***************************************************************************/
-/* CLKGEN :: PCIE_X1_TOP_INST_CLOCK_ENABLE_STATUS :: reserved0 [31:04] */
-#define BCHP_CLKGEN_PCIE_X1_TOP_INST_CLOCK_ENABLE_STATUS_reserved0_MASK 0xfffffff0
-#define BCHP_CLKGEN_PCIE_X1_TOP_INST_CLOCK_ENABLE_STATUS_reserved0_SHIFT 4
-
-/* CLKGEN :: PCIE_X1_TOP_INST_CLOCK_ENABLE_STATUS :: PCIE_SCB_CLOCK_ENABLE_STATUS [03:03] */
-#define BCHP_CLKGEN_PCIE_X1_TOP_INST_CLOCK_ENABLE_STATUS_PCIE_SCB_CLOCK_ENABLE_STATUS_MASK 0x00000008
-#define BCHP_CLKGEN_PCIE_X1_TOP_INST_CLOCK_ENABLE_STATUS_PCIE_SCB_CLOCK_ENABLE_STATUS_SHIFT 3
-
-/* CLKGEN :: PCIE_X1_TOP_INST_CLOCK_ENABLE_STATUS :: PCIE_GISB_CLOCK_ENABLE_STATUS [02:02] */
-#define BCHP_CLKGEN_PCIE_X1_TOP_INST_CLOCK_ENABLE_STATUS_PCIE_GISB_CLOCK_ENABLE_STATUS_MASK 0x00000004
-#define BCHP_CLKGEN_PCIE_X1_TOP_INST_CLOCK_ENABLE_STATUS_PCIE_GISB_CLOCK_ENABLE_STATUS_SHIFT 2
-
-/* CLKGEN :: PCIE_X1_TOP_INST_CLOCK_ENABLE_STATUS :: PCIE_54_CLOCK_ENABLE_STATUS [01:01] */
-#define BCHP_CLKGEN_PCIE_X1_TOP_INST_CLOCK_ENABLE_STATUS_PCIE_54_CLOCK_ENABLE_STATUS_MASK 0x00000002
-#define BCHP_CLKGEN_PCIE_X1_TOP_INST_CLOCK_ENABLE_STATUS_PCIE_54_CLOCK_ENABLE_STATUS_SHIFT 1
-
-/* CLKGEN :: PCIE_X1_TOP_INST_CLOCK_ENABLE_STATUS :: PCIE_108_CLOCK_ENABLE_STATUS [00:00] */
-#define BCHP_CLKGEN_PCIE_X1_TOP_INST_CLOCK_ENABLE_STATUS_PCIE_108_CLOCK_ENABLE_STATUS_MASK 0x00000001
-#define BCHP_CLKGEN_PCIE_X1_TOP_INST_CLOCK_ENABLE_STATUS_PCIE_108_CLOCK_ENABLE_STATUS_SHIFT 0
-
-/***************************************************************************
- *PCIE_X1_TOP_INST_OBSERVE_CLOCK - Pcie x1 top inst observe clock
- ***************************************************************************/
-/* CLKGEN :: PCIE_X1_TOP_INST_OBSERVE_CLOCK :: reserved0 [31:06] */
-#define BCHP_CLKGEN_PCIE_X1_TOP_INST_OBSERVE_CLOCK_reserved0_MASK 0xffffffc0
-#define BCHP_CLKGEN_PCIE_X1_TOP_INST_OBSERVE_CLOCK_reserved0_SHIFT 6
-
-/* CLKGEN :: PCIE_X1_TOP_INST_OBSERVE_CLOCK :: PCIE_ENABLE_OBSERVE_CLOCK [05:05] */
-#define BCHP_CLKGEN_PCIE_X1_TOP_INST_OBSERVE_CLOCK_PCIE_ENABLE_OBSERVE_CLOCK_MASK 0x00000020
-#define BCHP_CLKGEN_PCIE_X1_TOP_INST_OBSERVE_CLOCK_PCIE_ENABLE_OBSERVE_CLOCK_SHIFT 5
-#define BCHP_CLKGEN_PCIE_X1_TOP_INST_OBSERVE_CLOCK_PCIE_ENABLE_OBSERVE_CLOCK_DEFAULT 0x00000000
-
-/* CLKGEN :: PCIE_X1_TOP_INST_OBSERVE_CLOCK :: PCIE_ENABLE_DIVIDER_OBSERVE_CLOCK [04:04] */
-#define BCHP_CLKGEN_PCIE_X1_TOP_INST_OBSERVE_CLOCK_PCIE_ENABLE_DIVIDER_OBSERVE_CLOCK_MASK 0x00000010
-#define BCHP_CLKGEN_PCIE_X1_TOP_INST_OBSERVE_CLOCK_PCIE_ENABLE_DIVIDER_OBSERVE_CLOCK_SHIFT 4
-#define BCHP_CLKGEN_PCIE_X1_TOP_INST_OBSERVE_CLOCK_PCIE_ENABLE_DIVIDER_OBSERVE_CLOCK_DEFAULT 0x00000000
-
-/* CLKGEN :: PCIE_X1_TOP_INST_OBSERVE_CLOCK :: PCIE_CONTROL_OBSERVE_CLOCK [03:00] */
-#define BCHP_CLKGEN_PCIE_X1_TOP_INST_OBSERVE_CLOCK_PCIE_CONTROL_OBSERVE_CLOCK_MASK 0x0000000f
-#define BCHP_CLKGEN_PCIE_X1_TOP_INST_OBSERVE_CLOCK_PCIE_CONTROL_OBSERVE_CLOCK_SHIFT 0
-#define BCHP_CLKGEN_PCIE_X1_TOP_INST_OBSERVE_CLOCK_PCIE_CONTROL_OBSERVE_CLOCK_DEFAULT 0x00000000
-
-/***************************************************************************
- *PLL_CPU_GLITCHLESS_SWITCH_REQUEST - PLL_CPU Glitchless Clock Switching
- ***************************************************************************/
-/* CLKGEN :: PLL_CPU_GLITCHLESS_SWITCH_REQUEST :: reserved0 [31:09] */
-#define BCHP_CLKGEN_PLL_CPU_GLITCHLESS_SWITCH_REQUEST_reserved0_MASK 0xfffffe00
-#define BCHP_CLKGEN_PLL_CPU_GLITCHLESS_SWITCH_REQUEST_reserved0_SHIFT 9
-
-/* CLKGEN :: PLL_CPU_GLITCHLESS_SWITCH_REQUEST :: TRANSACTION_WAIT [08:01] */
-#define BCHP_CLKGEN_PLL_CPU_GLITCHLESS_SWITCH_REQUEST_TRANSACTION_WAIT_MASK 0x000001fe
-#define BCHP_CLKGEN_PLL_CPU_GLITCHLESS_SWITCH_REQUEST_TRANSACTION_WAIT_SHIFT 1
-#define BCHP_CLKGEN_PLL_CPU_GLITCHLESS_SWITCH_REQUEST_TRANSACTION_WAIT_DEFAULT 0x0000001f
-
-/* CLKGEN :: PLL_CPU_GLITCHLESS_SWITCH_REQUEST :: PLL_BYPASS_REQUEST [00:00] */
-#define BCHP_CLKGEN_PLL_CPU_GLITCHLESS_SWITCH_REQUEST_PLL_BYPASS_REQUEST_MASK 0x00000001
-#define BCHP_CLKGEN_PLL_CPU_GLITCHLESS_SWITCH_REQUEST_PLL_BYPASS_REQUEST_SHIFT 0
-#define BCHP_CLKGEN_PLL_CPU_GLITCHLESS_SWITCH_REQUEST_PLL_BYPASS_REQUEST_DEFAULT 0x00000000
-
-/***************************************************************************
- *PLL_CPU_GLITCHLESS_SWITCH_STATUS - PLL_CPU Glitchless Switching
- ***************************************************************************/
-/* CLKGEN :: PLL_CPU_GLITCHLESS_SWITCH_STATUS :: reserved0 [31:04] */
-#define BCHP_CLKGEN_PLL_CPU_GLITCHLESS_SWITCH_STATUS_reserved0_MASK 0xfffffff0
-#define BCHP_CLKGEN_PLL_CPU_GLITCHLESS_SWITCH_STATUS_reserved0_SHIFT 4
-
-/* CLKGEN :: PLL_CPU_GLITCHLESS_SWITCH_STATUS :: PLL_BYPASS_STATUS [03:00] */
-#define BCHP_CLKGEN_PLL_CPU_GLITCHLESS_SWITCH_STATUS_PLL_BYPASS_STATUS_MASK 0x0000000f
-#define BCHP_CLKGEN_PLL_CPU_GLITCHLESS_SWITCH_STATUS_PLL_BYPASS_STATUS_SHIFT 0
-
-/***************************************************************************
- *PLL_CPU_PLL_RESET_STATUS - PLL_CPU Reset Status
- ***************************************************************************/
-/* CLKGEN :: PLL_CPU_PLL_RESET_STATUS :: reserved0 [31:02] */
-#define BCHP_CLKGEN_PLL_CPU_PLL_RESET_STATUS_reserved0_MASK 0xfffffffc
-#define BCHP_CLKGEN_PLL_CPU_PLL_RESET_STATUS_reserved0_SHIFT 2
-
-/* CLKGEN :: PLL_CPU_PLL_RESET_STATUS :: PLL_DRESET_STATUS [01:01] */
-#define BCHP_CLKGEN_PLL_CPU_PLL_RESET_STATUS_PLL_DRESET_STATUS_MASK 0x00000002
-#define BCHP_CLKGEN_PLL_CPU_PLL_RESET_STATUS_PLL_DRESET_STATUS_SHIFT 1
-
-/* CLKGEN :: PLL_CPU_PLL_RESET_STATUS :: PLL_ARESET_STATUS [00:00] */
-#define BCHP_CLKGEN_PLL_CPU_PLL_RESET_STATUS_PLL_ARESET_STATUS_MASK 0x00000001
-#define BCHP_CLKGEN_PLL_CPU_PLL_RESET_STATUS_PLL_ARESET_STATUS_SHIFT 0
-
-/***************************************************************************
- *PLL_CPU_RDB_MACRO_CTRL - PLL RDB Macro Disable
- ***************************************************************************/
-/* CLKGEN :: PLL_CPU_RDB_MACRO_CTRL :: reserved0 [31:04] */
-#define BCHP_CLKGEN_PLL_CPU_RDB_MACRO_CTRL_reserved0_MASK 0xfffffff0
-#define BCHP_CLKGEN_PLL_CPU_RDB_MACRO_CTRL_reserved0_SHIFT 4
-
-/* CLKGEN :: PLL_CPU_RDB_MACRO_CTRL :: PLL_CPU_OPTIONS_DISABLE_RDB_MACRO [03:03] */
-#define BCHP_CLKGEN_PLL_CPU_RDB_MACRO_CTRL_PLL_CPU_OPTIONS_DISABLE_RDB_MACRO_MASK 0x00000008
-#define BCHP_CLKGEN_PLL_CPU_RDB_MACRO_CTRL_PLL_CPU_OPTIONS_DISABLE_RDB_MACRO_SHIFT 3
-#define BCHP_CLKGEN_PLL_CPU_RDB_MACRO_CTRL_PLL_CPU_OPTIONS_DISABLE_RDB_MACRO_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_CPU_RDB_MACRO_CTRL :: OPTIONS [02:00] */
-#define BCHP_CLKGEN_PLL_CPU_RDB_MACRO_CTRL_OPTIONS_MASK 0x00000007
-#define BCHP_CLKGEN_PLL_CPU_RDB_MACRO_CTRL_OPTIONS_SHIFT 0
-#define BCHP_CLKGEN_PLL_CPU_RDB_MACRO_CTRL_OPTIONS_DEFAULT 0x00000000
-
-/***************************************************************************
- *PLL_HVD_PLL_RESET_STATUS - PLL_HVD Reset Status
- ***************************************************************************/
-/* CLKGEN :: PLL_HVD_PLL_RESET_STATUS :: reserved0 [31:02] */
-#define BCHP_CLKGEN_PLL_HVD_PLL_RESET_STATUS_reserved0_MASK 0xfffffffc
-#define BCHP_CLKGEN_PLL_HVD_PLL_RESET_STATUS_reserved0_SHIFT 2
-
-/* CLKGEN :: PLL_HVD_PLL_RESET_STATUS :: PLL_DRESET_STATUS [01:01] */
-#define BCHP_CLKGEN_PLL_HVD_PLL_RESET_STATUS_PLL_DRESET_STATUS_MASK 0x00000002
-#define BCHP_CLKGEN_PLL_HVD_PLL_RESET_STATUS_PLL_DRESET_STATUS_SHIFT 1
-
-/* CLKGEN :: PLL_HVD_PLL_RESET_STATUS :: PLL_ARESET_STATUS [00:00] */
-#define BCHP_CLKGEN_PLL_HVD_PLL_RESET_STATUS_PLL_ARESET_STATUS_MASK 0x00000001
-#define BCHP_CLKGEN_PLL_HVD_PLL_RESET_STATUS_PLL_ARESET_STATUS_SHIFT 0
-
-/***************************************************************************
- *PLL_HVD_RDB_MACRO_CTRL - PLL RDB Macro Disable
- ***************************************************************************/
-/* CLKGEN :: PLL_HVD_RDB_MACRO_CTRL :: reserved0 [31:04] */
-#define BCHP_CLKGEN_PLL_HVD_RDB_MACRO_CTRL_reserved0_MASK 0xfffffff0
-#define BCHP_CLKGEN_PLL_HVD_RDB_MACRO_CTRL_reserved0_SHIFT 4
-
-/* CLKGEN :: PLL_HVD_RDB_MACRO_CTRL :: PLL_HVD_OPTIONS_DISABLE_RDB_MACRO [03:03] */
-#define BCHP_CLKGEN_PLL_HVD_RDB_MACRO_CTRL_PLL_HVD_OPTIONS_DISABLE_RDB_MACRO_MASK 0x00000008
-#define BCHP_CLKGEN_PLL_HVD_RDB_MACRO_CTRL_PLL_HVD_OPTIONS_DISABLE_RDB_MACRO_SHIFT 3
-#define BCHP_CLKGEN_PLL_HVD_RDB_MACRO_CTRL_PLL_HVD_OPTIONS_DISABLE_RDB_MACRO_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_HVD_RDB_MACRO_CTRL :: OPTIONS [02:00] */
-#define BCHP_CLKGEN_PLL_HVD_RDB_MACRO_CTRL_OPTIONS_MASK 0x00000007
-#define BCHP_CLKGEN_PLL_HVD_RDB_MACRO_CTRL_OPTIONS_SHIFT 0
-#define BCHP_CLKGEN_PLL_HVD_RDB_MACRO_CTRL_OPTIONS_DEFAULT 0x00000000
-
-/***************************************************************************
- *PLL_LC_PLL_RESET_STATUS - PLL_LC Reset Status
- ***************************************************************************/
-/* CLKGEN :: PLL_LC_PLL_RESET_STATUS :: reserved0 [31:02] */
-#define BCHP_CLKGEN_PLL_LC_PLL_RESET_STATUS_reserved0_MASK 0xfffffffc
-#define BCHP_CLKGEN_PLL_LC_PLL_RESET_STATUS_reserved0_SHIFT 2
-
-/* CLKGEN :: PLL_LC_PLL_RESET_STATUS :: PLL_DRESET_STATUS [01:01] */
-#define BCHP_CLKGEN_PLL_LC_PLL_RESET_STATUS_PLL_DRESET_STATUS_MASK 0x00000002
-#define BCHP_CLKGEN_PLL_LC_PLL_RESET_STATUS_PLL_DRESET_STATUS_SHIFT 1
-
-/* CLKGEN :: PLL_LC_PLL_RESET_STATUS :: PLL_ARESET_STATUS [00:00] */
-#define BCHP_CLKGEN_PLL_LC_PLL_RESET_STATUS_PLL_ARESET_STATUS_MASK 0x00000001
-#define BCHP_CLKGEN_PLL_LC_PLL_RESET_STATUS_PLL_ARESET_STATUS_SHIFT 0
-
-/***************************************************************************
- *PLL_MOCA_PLL_RESET_STATUS - PLL_MOCA Reset Status
- ***************************************************************************/
-/* CLKGEN :: PLL_MOCA_PLL_RESET_STATUS :: reserved0 [31:02] */
-#define BCHP_CLKGEN_PLL_MOCA_PLL_RESET_STATUS_reserved0_MASK 0xfffffffc
-#define BCHP_CLKGEN_PLL_MOCA_PLL_RESET_STATUS_reserved0_SHIFT 2
-
-/* CLKGEN :: PLL_MOCA_PLL_RESET_STATUS :: PLL_DRESET_STATUS [01:01] */
-#define BCHP_CLKGEN_PLL_MOCA_PLL_RESET_STATUS_PLL_DRESET_STATUS_MASK 0x00000002
-#define BCHP_CLKGEN_PLL_MOCA_PLL_RESET_STATUS_PLL_DRESET_STATUS_SHIFT 1
-
-/* CLKGEN :: PLL_MOCA_PLL_RESET_STATUS :: PLL_ARESET_STATUS [00:00] */
-#define BCHP_CLKGEN_PLL_MOCA_PLL_RESET_STATUS_PLL_ARESET_STATUS_MASK 0x00000001
-#define BCHP_CLKGEN_PLL_MOCA_PLL_RESET_STATUS_PLL_ARESET_STATUS_SHIFT 0
-
-/***************************************************************************
- *PLL_MOCA_RDB_MACRO_CTRL - PLL RDB Macro Disable
- ***************************************************************************/
-/* CLKGEN :: PLL_MOCA_RDB_MACRO_CTRL :: reserved0 [31:03] */
-#define BCHP_CLKGEN_PLL_MOCA_RDB_MACRO_CTRL_reserved0_MASK 0xfffffff8
-#define BCHP_CLKGEN_PLL_MOCA_RDB_MACRO_CTRL_reserved0_SHIFT 3
-
-/* CLKGEN :: PLL_MOCA_RDB_MACRO_CTRL :: PLL_MOCA_OPTIONS_DISABLE_RDB_MACRO [02:02] */
-#define BCHP_CLKGEN_PLL_MOCA_RDB_MACRO_CTRL_PLL_MOCA_OPTIONS_DISABLE_RDB_MACRO_MASK 0x00000004
-#define BCHP_CLKGEN_PLL_MOCA_RDB_MACRO_CTRL_PLL_MOCA_OPTIONS_DISABLE_RDB_MACRO_SHIFT 2
-#define BCHP_CLKGEN_PLL_MOCA_RDB_MACRO_CTRL_PLL_MOCA_OPTIONS_DISABLE_RDB_MACRO_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_MOCA_RDB_MACRO_CTRL :: OPTIONS [01:00] */
-#define BCHP_CLKGEN_PLL_MOCA_RDB_MACRO_CTRL_OPTIONS_MASK 0x00000003
-#define BCHP_CLKGEN_PLL_MOCA_RDB_MACRO_CTRL_OPTIONS_SHIFT 0
-#define BCHP_CLKGEN_PLL_MOCA_RDB_MACRO_CTRL_OPTIONS_DEFAULT 0x00000000
-
-/***************************************************************************
- *PLL_NETWORK_PLL_RESET_STATUS - PLL_NETWORK Reset Status
- ***************************************************************************/
-/* CLKGEN :: PLL_NETWORK_PLL_RESET_STATUS :: reserved0 [31:02] */
-#define BCHP_CLKGEN_PLL_NETWORK_PLL_RESET_STATUS_reserved0_MASK 0xfffffffc
-#define BCHP_CLKGEN_PLL_NETWORK_PLL_RESET_STATUS_reserved0_SHIFT 2
-
-/* CLKGEN :: PLL_NETWORK_PLL_RESET_STATUS :: PLL_DRESET_STATUS [01:01] */
-#define BCHP_CLKGEN_PLL_NETWORK_PLL_RESET_STATUS_PLL_DRESET_STATUS_MASK 0x00000002
-#define BCHP_CLKGEN_PLL_NETWORK_PLL_RESET_STATUS_PLL_DRESET_STATUS_SHIFT 1
-
-/* CLKGEN :: PLL_NETWORK_PLL_RESET_STATUS :: PLL_ARESET_STATUS [00:00] */
-#define BCHP_CLKGEN_PLL_NETWORK_PLL_RESET_STATUS_PLL_ARESET_STATUS_MASK 0x00000001
-#define BCHP_CLKGEN_PLL_NETWORK_PLL_RESET_STATUS_PLL_ARESET_STATUS_SHIFT 0
-
-/***************************************************************************
- *PLL_RAAGA_PLL_RESET_STATUS - PLL_RAAGA Reset Status
- ***************************************************************************/
-/* CLKGEN :: PLL_RAAGA_PLL_RESET_STATUS :: reserved0 [31:02] */
-#define BCHP_CLKGEN_PLL_RAAGA_PLL_RESET_STATUS_reserved0_MASK 0xfffffffc
-#define BCHP_CLKGEN_PLL_RAAGA_PLL_RESET_STATUS_reserved0_SHIFT 2
-
-/* CLKGEN :: PLL_RAAGA_PLL_RESET_STATUS :: PLL_DRESET_STATUS [01:01] */
-#define BCHP_CLKGEN_PLL_RAAGA_PLL_RESET_STATUS_PLL_DRESET_STATUS_MASK 0x00000002
-#define BCHP_CLKGEN_PLL_RAAGA_PLL_RESET_STATUS_PLL_DRESET_STATUS_SHIFT 1
-
-/* CLKGEN :: PLL_RAAGA_PLL_RESET_STATUS :: PLL_ARESET_STATUS [00:00] */
-#define BCHP_CLKGEN_PLL_RAAGA_PLL_RESET_STATUS_PLL_ARESET_STATUS_MASK 0x00000001
-#define BCHP_CLKGEN_PLL_RAAGA_PLL_RESET_STATUS_PLL_ARESET_STATUS_SHIFT 0
-
-/***************************************************************************
- *PLL_RAAGA_RDB_MACRO_CTRL - PLL RDB Macro Disable
- ***************************************************************************/
-/* CLKGEN :: PLL_RAAGA_RDB_MACRO_CTRL :: reserved0 [31:04] */
-#define BCHP_CLKGEN_PLL_RAAGA_RDB_MACRO_CTRL_reserved0_MASK 0xfffffff0
-#define BCHP_CLKGEN_PLL_RAAGA_RDB_MACRO_CTRL_reserved0_SHIFT 4
-
-/* CLKGEN :: PLL_RAAGA_RDB_MACRO_CTRL :: PLL_RAAGA_OPTIONS_DISABLE_RDB_MACRO [03:03] */
-#define BCHP_CLKGEN_PLL_RAAGA_RDB_MACRO_CTRL_PLL_RAAGA_OPTIONS_DISABLE_RDB_MACRO_MASK 0x00000008
-#define BCHP_CLKGEN_PLL_RAAGA_RDB_MACRO_CTRL_PLL_RAAGA_OPTIONS_DISABLE_RDB_MACRO_SHIFT 3
-#define BCHP_CLKGEN_PLL_RAAGA_RDB_MACRO_CTRL_PLL_RAAGA_OPTIONS_DISABLE_RDB_MACRO_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_RAAGA_RDB_MACRO_CTRL :: OPTIONS [02:00] */
-#define BCHP_CLKGEN_PLL_RAAGA_RDB_MACRO_CTRL_OPTIONS_MASK 0x00000007
-#define BCHP_CLKGEN_PLL_RAAGA_RDB_MACRO_CTRL_OPTIONS_SHIFT 0
-#define BCHP_CLKGEN_PLL_RAAGA_RDB_MACRO_CTRL_OPTIONS_DEFAULT 0x00000000
-
-/***************************************************************************
- *PLL_SC0_PLL_RESET_STATUS - PLL_SC0 Reset Status
- ***************************************************************************/
-/* CLKGEN :: PLL_SC0_PLL_RESET_STATUS :: reserved0 [31:02] */
-#define BCHP_CLKGEN_PLL_SC0_PLL_RESET_STATUS_reserved0_MASK 0xfffffffc
-#define BCHP_CLKGEN_PLL_SC0_PLL_RESET_STATUS_reserved0_SHIFT 2
-
-/* CLKGEN :: PLL_SC0_PLL_RESET_STATUS :: PLL_DRESET_STATUS [01:01] */
-#define BCHP_CLKGEN_PLL_SC0_PLL_RESET_STATUS_PLL_DRESET_STATUS_MASK 0x00000002
-#define BCHP_CLKGEN_PLL_SC0_PLL_RESET_STATUS_PLL_DRESET_STATUS_SHIFT 1
-
-/* CLKGEN :: PLL_SC0_PLL_RESET_STATUS :: PLL_ARESET_STATUS [00:00] */
-#define BCHP_CLKGEN_PLL_SC0_PLL_RESET_STATUS_PLL_ARESET_STATUS_MASK 0x00000001
-#define BCHP_CLKGEN_PLL_SC0_PLL_RESET_STATUS_PLL_ARESET_STATUS_SHIFT 0
-
-/***************************************************************************
- *PLL_SC0_RDB_MACRO_CTRL - PLL RDB Macro Disable
- ***************************************************************************/
-/* CLKGEN :: PLL_SC0_RDB_MACRO_CTRL :: reserved0 [31:05] */
-#define BCHP_CLKGEN_PLL_SC0_RDB_MACRO_CTRL_reserved0_MASK 0xffffffe0
-#define BCHP_CLKGEN_PLL_SC0_RDB_MACRO_CTRL_reserved0_SHIFT 5
-
-/* CLKGEN :: PLL_SC0_RDB_MACRO_CTRL :: PLL_SC0_OPTIONS_DISABLE_RDB_MACRO [04:04] */
-#define BCHP_CLKGEN_PLL_SC0_RDB_MACRO_CTRL_PLL_SC0_OPTIONS_DISABLE_RDB_MACRO_MASK 0x00000010
-#define BCHP_CLKGEN_PLL_SC0_RDB_MACRO_CTRL_PLL_SC0_OPTIONS_DISABLE_RDB_MACRO_SHIFT 4
-#define BCHP_CLKGEN_PLL_SC0_RDB_MACRO_CTRL_PLL_SC0_OPTIONS_DISABLE_RDB_MACRO_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_SC0_RDB_MACRO_CTRL :: OPTIONS [03:00] */
-#define BCHP_CLKGEN_PLL_SC0_RDB_MACRO_CTRL_OPTIONS_MASK 0x0000000f
-#define BCHP_CLKGEN_PLL_SC0_RDB_MACRO_CTRL_OPTIONS_SHIFT 0
-#define BCHP_CLKGEN_PLL_SC0_RDB_MACRO_CTRL_OPTIONS_DEFAULT 0x00000000
-
-/***************************************************************************
- *PLL_SC1_PLL_RESET_STATUS - PLL_SC1 Reset Status
- ***************************************************************************/
-/* CLKGEN :: PLL_SC1_PLL_RESET_STATUS :: reserved0 [31:02] */
-#define BCHP_CLKGEN_PLL_SC1_PLL_RESET_STATUS_reserved0_MASK 0xfffffffc
-#define BCHP_CLKGEN_PLL_SC1_PLL_RESET_STATUS_reserved0_SHIFT 2
-
-/* CLKGEN :: PLL_SC1_PLL_RESET_STATUS :: PLL_DRESET_STATUS [01:01] */
-#define BCHP_CLKGEN_PLL_SC1_PLL_RESET_STATUS_PLL_DRESET_STATUS_MASK 0x00000002
-#define BCHP_CLKGEN_PLL_SC1_PLL_RESET_STATUS_PLL_DRESET_STATUS_SHIFT 1
-
-/* CLKGEN :: PLL_SC1_PLL_RESET_STATUS :: PLL_ARESET_STATUS [00:00] */
-#define BCHP_CLKGEN_PLL_SC1_PLL_RESET_STATUS_PLL_ARESET_STATUS_MASK 0x00000001
-#define BCHP_CLKGEN_PLL_SC1_PLL_RESET_STATUS_PLL_ARESET_STATUS_SHIFT 0
-
-/***************************************************************************
- *PLL_SC1_RDB_MACRO_CTRL - PLL RDB Macro Disable
- ***************************************************************************/
-/* CLKGEN :: PLL_SC1_RDB_MACRO_CTRL :: reserved0 [31:05] */
-#define BCHP_CLKGEN_PLL_SC1_RDB_MACRO_CTRL_reserved0_MASK 0xffffffe0
-#define BCHP_CLKGEN_PLL_SC1_RDB_MACRO_CTRL_reserved0_SHIFT 5
-
-/* CLKGEN :: PLL_SC1_RDB_MACRO_CTRL :: PLL_SC1_OPTIONS_DISABLE_RDB_MACRO [04:04] */
-#define BCHP_CLKGEN_PLL_SC1_RDB_MACRO_CTRL_PLL_SC1_OPTIONS_DISABLE_RDB_MACRO_MASK 0x00000010
-#define BCHP_CLKGEN_PLL_SC1_RDB_MACRO_CTRL_PLL_SC1_OPTIONS_DISABLE_RDB_MACRO_SHIFT 4
-#define BCHP_CLKGEN_PLL_SC1_RDB_MACRO_CTRL_PLL_SC1_OPTIONS_DISABLE_RDB_MACRO_DEFAULT 0x00000000
-
-/* CLKGEN :: PLL_SC1_RDB_MACRO_CTRL :: OPTIONS [03:00] */
-#define BCHP_CLKGEN_PLL_SC1_RDB_MACRO_CTRL_OPTIONS_MASK 0x0000000f
-#define BCHP_CLKGEN_PLL_SC1_RDB_MACRO_CTRL_OPTIONS_SHIFT 0
-#define BCHP_CLKGEN_PLL_SC1_RDB_MACRO_CTRL_OPTIONS_DEFAULT 0x00000000
-
-/***************************************************************************
- *PLL_VCXO0_PLL_RESET_STATUS - PLL_VCXO0 Reset Status
- ***************************************************************************/
-/* CLKGEN :: PLL_VCXO0_PLL_RESET_STATUS :: reserved0 [31:02] */
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_RESET_STATUS_reserved0_MASK 0xfffffffc
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_RESET_STATUS_reserved0_SHIFT 2
-
-/* CLKGEN :: PLL_VCXO0_PLL_RESET_STATUS :: PLL_DRESET_STATUS [01:01] */
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_RESET_STATUS_PLL_DRESET_STATUS_MASK 0x00000002
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_RESET_STATUS_PLL_DRESET_STATUS_SHIFT 1
-
-/* CLKGEN :: PLL_VCXO0_PLL_RESET_STATUS :: PLL_ARESET_STATUS [00:00] */
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_RESET_STATUS_PLL_ARESET_STATUS_MASK 0x00000001
-#define BCHP_CLKGEN_PLL_VCXO0_PLL_RESET_STATUS_PLL_ARESET_STATUS_SHIFT 0
-
-/***************************************************************************
- *PLL_VCXO1_PLL_RESET_STATUS - PLL_VCXO1 Reset Status
- ***************************************************************************/
-/* CLKGEN :: PLL_VCXO1_PLL_RESET_STATUS :: reserved0 [31:02] */
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_RESET_STATUS_reserved0_MASK 0xfffffffc
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_RESET_STATUS_reserved0_SHIFT 2
-
-/* CLKGEN :: PLL_VCXO1_PLL_RESET_STATUS :: PLL_DRESET_STATUS [01:01] */
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_RESET_STATUS_PLL_DRESET_STATUS_MASK 0x00000002
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_RESET_STATUS_PLL_DRESET_STATUS_SHIFT 1
-
-/* CLKGEN :: PLL_VCXO1_PLL_RESET_STATUS :: PLL_ARESET_STATUS [00:00] */
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_RESET_STATUS_PLL_ARESET_STATUS_MASK 0x00000001
-#define BCHP_CLKGEN_PLL_VCXO1_PLL_RESET_STATUS_PLL_ARESET_STATUS_SHIFT 0
-
-/***************************************************************************
- *PM_CLOCK_Async_ALIVE_SEL - Select clocks that can stay alive during power management standby mode.
- ***************************************************************************/
-/* CLKGEN :: PM_CLOCK_Async_ALIVE_SEL :: reserved0 [31:01] */
-#define BCHP_CLKGEN_PM_CLOCK_Async_ALIVE_SEL_reserved0_MASK 0xfffffffe
-#define BCHP_CLKGEN_PM_CLOCK_Async_ALIVE_SEL_reserved0_SHIFT 1
-
-/* CLKGEN :: PM_CLOCK_Async_ALIVE_SEL :: CLOCK_Async_CG_XPT [00:00] */
-#define BCHP_CLKGEN_PM_CLOCK_Async_ALIVE_SEL_CLOCK_Async_CG_XPT_MASK 0x00000001
-#define BCHP_CLKGEN_PM_CLOCK_Async_ALIVE_SEL_CLOCK_Async_CG_XPT_SHIFT 0
-#define BCHP_CLKGEN_PM_CLOCK_Async_ALIVE_SEL_CLOCK_Async_CG_XPT_DEFAULT 0x00000000
-
-/***************************************************************************
- *PM_PLL_ALIVE_SEL - PLL Alive in Standby Mode
- ***************************************************************************/
-/* CLKGEN :: PM_PLL_ALIVE_SEL :: reserved0 [31:04] */
-#define BCHP_CLKGEN_PM_PLL_ALIVE_SEL_reserved0_MASK 0xfffffff0
-#define BCHP_CLKGEN_PM_PLL_ALIVE_SEL_reserved0_SHIFT 4
-
-/* CLKGEN :: PM_PLL_ALIVE_SEL :: memsys_PLL [03:03] */
-#define BCHP_CLKGEN_PM_PLL_ALIVE_SEL_memsys_PLL_MASK 0x00000008
-#define BCHP_CLKGEN_PM_PLL_ALIVE_SEL_memsys_PLL_SHIFT 3
-#define BCHP_CLKGEN_PM_PLL_ALIVE_SEL_memsys_PLL_DEFAULT 0x00000000
-
-/* CLKGEN :: PM_PLL_ALIVE_SEL :: PLL_XPT [02:02] */
-#define BCHP_CLKGEN_PM_PLL_ALIVE_SEL_PLL_XPT_MASK 0x00000004
-#define BCHP_CLKGEN_PM_PLL_ALIVE_SEL_PLL_XPT_SHIFT 2
-#define BCHP_CLKGEN_PM_PLL_ALIVE_SEL_PLL_XPT_DEFAULT 0x00000000
-
-/* CLKGEN :: PM_PLL_ALIVE_SEL :: PLL_SYS0 [01:01] */
-#define BCHP_CLKGEN_PM_PLL_ALIVE_SEL_PLL_SYS0_MASK 0x00000002
-#define BCHP_CLKGEN_PM_PLL_ALIVE_SEL_PLL_SYS0_SHIFT 1
-#define BCHP_CLKGEN_PM_PLL_ALIVE_SEL_PLL_SYS0_DEFAULT 0x00000000
-
-/* CLKGEN :: PM_PLL_ALIVE_SEL :: PLL_CPU [00:00] */
-#define BCHP_CLKGEN_PM_PLL_ALIVE_SEL_PLL_CPU_MASK 0x00000001
-#define BCHP_CLKGEN_PM_PLL_ALIVE_SEL_PLL_CPU_SHIFT 0
-#define BCHP_CLKGEN_PM_PLL_ALIVE_SEL_PLL_CPU_DEFAULT 0x00000000
-
-/***************************************************************************
- *PM_PLL_LDO_POWERUP - Power management LDO PLL
- ***************************************************************************/
-/* CLKGEN :: PM_PLL_LDO_POWERUP :: reserved0 [31:07] */
-#define BCHP_CLKGEN_PM_PLL_LDO_POWERUP_reserved0_MASK 0xffffff80
-#define BCHP_CLKGEN_PM_PLL_LDO_POWERUP_reserved0_SHIFT 7
-
-/* CLKGEN :: PM_PLL_LDO_POWERUP :: ISO_CLOCK_PLL_VCXO1 [06:06] */
-#define BCHP_CLKGEN_PM_PLL_LDO_POWERUP_ISO_CLOCK_PLL_VCXO1_MASK 0x00000040
-#define BCHP_CLKGEN_PM_PLL_LDO_POWERUP_ISO_CLOCK_PLL_VCXO1_SHIFT 6
-#define BCHP_CLKGEN_PM_PLL_LDO_POWERUP_ISO_CLOCK_PLL_VCXO1_DEFAULT 0x00000000
-
-/* CLKGEN :: PM_PLL_LDO_POWERUP :: ISO_CLOCK_PLL_VCXO0 [05:05] */
-#define BCHP_CLKGEN_PM_PLL_LDO_POWERUP_ISO_CLOCK_PLL_VCXO0_MASK 0x00000020
-#define BCHP_CLKGEN_PM_PLL_LDO_POWERUP_ISO_CLOCK_PLL_VCXO0_SHIFT 5
-#define BCHP_CLKGEN_PM_PLL_LDO_POWERUP_ISO_CLOCK_PLL_VCXO0_DEFAULT 0x00000000
-
-/* CLKGEN :: PM_PLL_LDO_POWERUP :: ISO_CLOCK_PLL_RAAGA [04:04] */
-#define BCHP_CLKGEN_PM_PLL_LDO_POWERUP_ISO_CLOCK_PLL_RAAGA_MASK 0x00000010
-#define BCHP_CLKGEN_PM_PLL_LDO_POWERUP_ISO_CLOCK_PLL_RAAGA_SHIFT 4
-#define BCHP_CLKGEN_PM_PLL_LDO_POWERUP_ISO_CLOCK_PLL_RAAGA_DEFAULT 0x00000000
-
-/* CLKGEN :: PM_PLL_LDO_POWERUP :: ISO_CLOCK_PLL_NETWORK [03:03] */
-#define BCHP_CLKGEN_PM_PLL_LDO_POWERUP_ISO_CLOCK_PLL_NETWORK_MASK 0x00000008
-#define BCHP_CLKGEN_PM_PLL_LDO_POWERUP_ISO_CLOCK_PLL_NETWORK_SHIFT 3
-#define BCHP_CLKGEN_PM_PLL_LDO_POWERUP_ISO_CLOCK_PLL_NETWORK_DEFAULT 0x00000000
-
-/* CLKGEN :: PM_PLL_LDO_POWERUP :: ISO_CLOCK_PLL_MOCA [02:02] */
-#define BCHP_CLKGEN_PM_PLL_LDO_POWERUP_ISO_CLOCK_PLL_MOCA_MASK 0x00000004
-#define BCHP_CLKGEN_PM_PLL_LDO_POWERUP_ISO_CLOCK_PLL_MOCA_SHIFT 2
-#define BCHP_CLKGEN_PM_PLL_LDO_POWERUP_ISO_CLOCK_PLL_MOCA_DEFAULT 0x00000000
-
-/* CLKGEN :: PM_PLL_LDO_POWERUP :: ISO_CLOCK_PLL_LC [01:01] */
-#define BCHP_CLKGEN_PM_PLL_LDO_POWERUP_ISO_CLOCK_PLL_LC_MASK 0x00000002
-#define BCHP_CLKGEN_PM_PLL_LDO_POWERUP_ISO_CLOCK_PLL_LC_SHIFT 1
-#define BCHP_CLKGEN_PM_PLL_LDO_POWERUP_ISO_CLOCK_PLL_LC_DEFAULT 0x00000000
-
-/* CLKGEN :: PM_PLL_LDO_POWERUP :: ISO_CLOCK_PLL_HVD [00:00] */
-#define BCHP_CLKGEN_PM_PLL_LDO_POWERUP_ISO_CLOCK_PLL_HVD_MASK 0x00000001
-#define BCHP_CLKGEN_PM_PLL_LDO_POWERUP_ISO_CLOCK_PLL_HVD_SHIFT 0
-#define BCHP_CLKGEN_PM_PLL_LDO_POWERUP_ISO_CLOCK_PLL_HVD_DEFAULT 0x00000000
-
-/***************************************************************************
- *PROD_OTP_INST_CLOCK_DISABLE - Disable PROD_OTP_INST's clocks
- ***************************************************************************/
-/* CLKGEN :: PROD_OTP_INST_CLOCK_DISABLE :: reserved0 [31:02] */
-#define BCHP_CLKGEN_PROD_OTP_INST_CLOCK_DISABLE_reserved0_MASK 0xfffffffc
-#define BCHP_CLKGEN_PROD_OTP_INST_CLOCK_DISABLE_reserved0_SHIFT 2
-
-/* CLKGEN :: PROD_OTP_INST_CLOCK_DISABLE :: DISABLE_POTP_JTAGOTP_CLOCK [01:01] */
-#define BCHP_CLKGEN_PROD_OTP_INST_CLOCK_DISABLE_DISABLE_POTP_JTAGOTP_CLOCK_MASK 0x00000002
-#define BCHP_CLKGEN_PROD_OTP_INST_CLOCK_DISABLE_DISABLE_POTP_JTAGOTP_CLOCK_SHIFT 1
-#define BCHP_CLKGEN_PROD_OTP_INST_CLOCK_DISABLE_DISABLE_POTP_JTAGOTP_CLOCK_DEFAULT 0x00000000
-
-/* CLKGEN :: PROD_OTP_INST_CLOCK_DISABLE :: DISABLE_POTP_ALWAYSON_CLOCK [00:00] */
-#define BCHP_CLKGEN_PROD_OTP_INST_CLOCK_DISABLE_DISABLE_POTP_ALWAYSON_CLOCK_MASK 0x00000001
-#define BCHP_CLKGEN_PROD_OTP_INST_CLOCK_DISABLE_DISABLE_POTP_ALWAYSON_CLOCK_SHIFT 0
-#define BCHP_CLKGEN_PROD_OTP_INST_CLOCK_DISABLE_DISABLE_POTP_ALWAYSON_CLOCK_DEFAULT 0x00000000
-
-/***************************************************************************
- *PROD_OTP_INST_CLOCK_DISABLE_STATUS - Clock Disable Status
- ***************************************************************************/
-/* CLKGEN :: PROD_OTP_INST_CLOCK_DISABLE_STATUS :: reserved0 [31:02] */
-#define BCHP_CLKGEN_PROD_OTP_INST_CLOCK_DISABLE_STATUS_reserved0_MASK 0xfffffffc
-#define BCHP_CLKGEN_PROD_OTP_INST_CLOCK_DISABLE_STATUS_reserved0_SHIFT 2
-
-/* CLKGEN :: PROD_OTP_INST_CLOCK_DISABLE_STATUS :: DISABLE_POTP_JTAGOTP_CLOCK_STATUS [01:01] */
-#define BCHP_CLKGEN_PROD_OTP_INST_CLOCK_DISABLE_STATUS_DISABLE_POTP_JTAGOTP_CLOCK_STATUS_MASK 0x00000002
-#define BCHP_CLKGEN_PROD_OTP_INST_CLOCK_DISABLE_STATUS_DISABLE_POTP_JTAGOTP_CLOCK_STATUS_SHIFT 1
-
-/* CLKGEN :: PROD_OTP_INST_CLOCK_DISABLE_STATUS :: DISABLE_POTP_ALWAYSON_CLOCK_STATUS [00:00] */
-#define BCHP_CLKGEN_PROD_OTP_INST_CLOCK_DISABLE_STATUS_DISABLE_POTP_ALWAYSON_CLOCK_STATUS_MASK 0x00000001
-#define BCHP_CLKGEN_PROD_OTP_INST_CLOCK_DISABLE_STATUS_DISABLE_POTP_ALWAYSON_CLOCK_STATUS_SHIFT 0
-
-/***************************************************************************
- *PROD_OTP_INST_CLOCK_ENABLE - Prod otp inst clock enable
- ***************************************************************************/
-/* CLKGEN :: PROD_OTP_INST_CLOCK_ENABLE :: reserved0 [31:02] */
-#define BCHP_CLKGEN_PROD_OTP_INST_CLOCK_ENABLE_reserved0_MASK 0xfffffffc
-#define BCHP_CLKGEN_PROD_OTP_INST_CLOCK_ENABLE_reserved0_SHIFT 2
-
-/* CLKGEN :: PROD_OTP_INST_CLOCK_ENABLE :: POTP_GISB_CLOCK_ENABLE [01:01] */
-#define BCHP_CLKGEN_PROD_OTP_INST_CLOCK_ENABLE_POTP_GISB_CLOCK_ENABLE_MASK 0x00000002
-#define BCHP_CLKGEN_PROD_OTP_INST_CLOCK_ENABLE_POTP_GISB_CLOCK_ENABLE_SHIFT 1
-#define BCHP_CLKGEN_PROD_OTP_INST_CLOCK_ENABLE_POTP_GISB_CLOCK_ENABLE_DEFAULT 0x00000001
-
-/* CLKGEN :: PROD_OTP_INST_CLOCK_ENABLE :: POTP_54_CLOCK_ENABLE [00:00] */
-#define BCHP_CLKGEN_PROD_OTP_INST_CLOCK_ENABLE_POTP_54_CLOCK_ENABLE_MASK 0x00000001
-#define BCHP_CLKGEN_PROD_OTP_INST_CLOCK_ENABLE_POTP_54_CLOCK_ENABLE_SHIFT 0
-#define BCHP_CLKGEN_PROD_OTP_INST_CLOCK_ENABLE_POTP_54_CLOCK_ENABLE_DEFAULT 0x00000001
-
-/***************************************************************************
- *PROD_OTP_INST_CLOCK_ENABLE_STATUS - Clock Enable Status
- ***************************************************************************/
-/* CLKGEN :: PROD_OTP_INST_CLOCK_ENABLE_STATUS :: reserved0 [31:02] */
-#define BCHP_CLKGEN_PROD_OTP_INST_CLOCK_ENABLE_STATUS_reserved0_MASK 0xfffffffc
-#define BCHP_CLKGEN_PROD_OTP_INST_CLOCK_ENABLE_STATUS_reserved0_SHIFT 2
-
-/* CLKGEN :: PROD_OTP_INST_CLOCK_ENABLE_STATUS :: POTP_GISB_CLOCK_ENABLE_STATUS [01:01] */
-#define BCHP_CLKGEN_PROD_OTP_INST_CLOCK_ENABLE_STATUS_POTP_GISB_CLOCK_ENABLE_STATUS_MASK 0x00000002
-#define BCHP_CLKGEN_PROD_OTP_INST_CLOCK_ENABLE_STATUS_POTP_GISB_CLOCK_ENABLE_STATUS_SHIFT 1
-
-/* CLKGEN :: PROD_OTP_INST_CLOCK_ENABLE_STATUS :: POTP_54_CLOCK_ENABLE_STATUS [00:00] */
-#define BCHP_CLKGEN_PROD_OTP_INST_CLOCK_ENABLE_STATUS_POTP_54_CLOCK_ENABLE_STATUS_MASK 0x00000001
-#define BCHP_CLKGEN_PROD_OTP_INST_CLOCK_ENABLE_STATUS_POTP_54_CLOCK_ENABLE_STATUS_SHIFT 0
-
-/***************************************************************************
- *RAAGA_DSP_TOP_0_INST_CLOCK_ENABLE - Raaga dsp top 0 inst clock enable
- ***************************************************************************/
-/* CLKGEN :: RAAGA_DSP_TOP_0_INST_CLOCK_ENABLE :: reserved0 [31:05] */
-#define BCHP_CLKGEN_RAAGA_DSP_TOP_0_INST_CLOCK_ENABLE_reserved0_MASK 0xffffffe0
-#define BCHP_CLKGEN_RAAGA_DSP_TOP_0_INST_CLOCK_ENABLE_reserved0_SHIFT 5
-
-/* CLKGEN :: RAAGA_DSP_TOP_0_INST_CLOCK_ENABLE :: RAAGA_SCB_CLOCK_ENABLE [04:04] */
-#define BCHP_CLKGEN_RAAGA_DSP_TOP_0_INST_CLOCK_ENABLE_RAAGA_SCB_CLOCK_ENABLE_MASK 0x00000010
-#define BCHP_CLKGEN_RAAGA_DSP_TOP_0_INST_CLOCK_ENABLE_RAAGA_SCB_CLOCK_ENABLE_SHIFT 4
-#define BCHP_CLKGEN_RAAGA_DSP_TOP_0_INST_CLOCK_ENABLE_RAAGA_SCB_CLOCK_ENABLE_DEFAULT 0x00000001
-
-/* CLKGEN :: RAAGA_DSP_TOP_0_INST_CLOCK_ENABLE :: RAAGA_GISB_CLOCK_ENABLE [03:03] */
-#define BCHP_CLKGEN_RAAGA_DSP_TOP_0_INST_CLOCK_ENABLE_RAAGA_GISB_CLOCK_ENABLE_MASK 0x00000008
-#define BCHP_CLKGEN_RAAGA_DSP_TOP_0_INST_CLOCK_ENABLE_RAAGA_GISB_CLOCK_ENABLE_SHIFT 3
-#define BCHP_CLKGEN_RAAGA_DSP_TOP_0_INST_CLOCK_ENABLE_RAAGA_GISB_CLOCK_ENABLE_DEFAULT 0x00000001
-
-/* CLKGEN :: RAAGA_DSP_TOP_0_INST_CLOCK_ENABLE :: RAAGA_DSP_CLOCK_ENABLE [02:02] */
-#define BCHP_CLKGEN_RAAGA_DSP_TOP_0_INST_CLOCK_ENABLE_RAAGA_DSP_CLOCK_ENABLE_MASK 0x00000004
-#define BCHP_CLKGEN_RAAGA_DSP_TOP_0_INST_CLOCK_ENABLE_RAAGA_DSP_CLOCK_ENABLE_SHIFT 2
-#define BCHP_CLKGEN_RAAGA_DSP_TOP_0_INST_CLOCK_ENABLE_RAAGA_DSP_CLOCK_ENABLE_DEFAULT 0x00000001
-
-/* CLKGEN :: RAAGA_DSP_TOP_0_INST_CLOCK_ENABLE :: RAAGA_54_CLOCK_ENABLE [01:01] */
-#define BCHP_CLKGEN_RAAGA_DSP_TOP_0_INST_CLOCK_ENABLE_RAAGA_54_CLOCK_ENABLE_MASK 0x00000002
-#define BCHP_CLKGEN_RAAGA_DSP_TOP_0_INST_CLOCK_ENABLE_RAAGA_54_CLOCK_ENABLE_SHIFT 1
-#define BCHP_CLKGEN_RAAGA_DSP_TOP_0_INST_CLOCK_ENABLE_RAAGA_54_CLOCK_ENABLE_DEFAULT 0x00000001
-
-/* CLKGEN :: RAAGA_DSP_TOP_0_INST_CLOCK_ENABLE :: RAAGA_108_CLOCK_ENABLE [00:00] */
-#define BCHP_CLKGEN_RAAGA_DSP_TOP_0_INST_CLOCK_ENABLE_RAAGA_108_CLOCK_ENABLE_MASK 0x00000001
-#define BCHP_CLKGEN_RAAGA_DSP_TOP_0_INST_CLOCK_ENABLE_RAAGA_108_CLOCK_ENABLE_SHIFT 0
-#define BCHP_CLKGEN_RAAGA_DSP_TOP_0_INST_CLOCK_ENABLE_RAAGA_108_CLOCK_ENABLE_DEFAULT 0x00000001
-
-/***************************************************************************
- *RAAGA_DSP_TOP_0_INST_CLOCK_ENABLE_STATUS - Clock Enable Status
- ***************************************************************************/
-/* CLKGEN :: RAAGA_DSP_TOP_0_INST_CLOCK_ENABLE_STATUS :: reserved0 [31:05] */
-#define BCHP_CLKGEN_RAAGA_DSP_TOP_0_INST_CLOCK_ENABLE_STATUS_reserved0_MASK 0xffffffe0
-#define BCHP_CLKGEN_RAAGA_DSP_TOP_0_INST_CLOCK_ENABLE_STATUS_reserved0_SHIFT 5
-
-/* CLKGEN :: RAAGA_DSP_TOP_0_INST_CLOCK_ENABLE_STATUS :: RAAGA_SCB_CLOCK_ENABLE_STATUS [04:04] */
-#define BCHP_CLKGEN_RAAGA_DSP_TOP_0_INST_CLOCK_ENABLE_STATUS_RAAGA_SCB_CLOCK_ENABLE_STATUS_MASK 0x00000010
-#define BCHP_CLKGEN_RAAGA_DSP_TOP_0_INST_CLOCK_ENABLE_STATUS_RAAGA_SCB_CLOCK_ENABLE_STATUS_SHIFT 4
-
-/* CLKGEN :: RAAGA_DSP_TOP_0_INST_CLOCK_ENABLE_STATUS :: RAAGA_GISB_CLOCK_ENABLE_STATUS [03:03] */
-#define BCHP_CLKGEN_RAAGA_DSP_TOP_0_INST_CLOCK_ENABLE_STATUS_RAAGA_GISB_CLOCK_ENABLE_STATUS_MASK 0x00000008
-#define BCHP_CLKGEN_RAAGA_DSP_TOP_0_INST_CLOCK_ENABLE_STATUS_RAAGA_GISB_CLOCK_ENABLE_STATUS_SHIFT 3
-
-/* CLKGEN :: RAAGA_DSP_TOP_0_INST_CLOCK_ENABLE_STATUS :: RAAGA_DSP_CLOCK_ENABLE_STATUS [02:02] */
-#define BCHP_CLKGEN_RAAGA_DSP_TOP_0_INST_CLOCK_ENABLE_STATUS_RAAGA_DSP_CLOCK_ENABLE_STATUS_MASK 0x00000004
-#define BCHP_CLKGEN_RAAGA_DSP_TOP_0_INST_CLOCK_ENABLE_STATUS_RAAGA_DSP_CLOCK_ENABLE_STATUS_SHIFT 2
-
-/* CLKGEN :: RAAGA_DSP_TOP_0_INST_CLOCK_ENABLE_STATUS :: RAAGA_54_CLOCK_ENABLE_STATUS [01:01] */
-#define BCHP_CLKGEN_RAAGA_DSP_TOP_0_INST_CLOCK_ENABLE_STATUS_RAAGA_54_CLOCK_ENABLE_STATUS_MASK 0x00000002
-#define BCHP_CLKGEN_RAAGA_DSP_TOP_0_INST_CLOCK_ENABLE_STATUS_RAAGA_54_CLOCK_ENABLE_STATUS_SHIFT 1
-
-/* CLKGEN :: RAAGA_DSP_TOP_0_INST_CLOCK_ENABLE_STATUS :: RAAGA_108_CLOCK_ENABLE_STATUS [00:00] */
-#define BCHP_CLKGEN_RAAGA_DSP_TOP_0_INST_CLOCK_ENABLE_STATUS_RAAGA_108_CLOCK_ENABLE_STATUS_MASK 0x00000001
-#define BCHP_CLKGEN_RAAGA_DSP_TOP_0_INST_CLOCK_ENABLE_STATUS_RAAGA_108_CLOCK_ENABLE_STATUS_SHIFT 0
-
-/***************************************************************************
- *RAAGA_DSP_TOP_0_INST_OBSERVE_CLOCK - Raaga dsp top 0 inst observe clock
- ***************************************************************************/
-/* CLKGEN :: RAAGA_DSP_TOP_0_INST_OBSERVE_CLOCK :: reserved0 [31:02] */
-#define BCHP_CLKGEN_RAAGA_DSP_TOP_0_INST_OBSERVE_CLOCK_reserved0_MASK 0xfffffffc
-#define BCHP_CLKGEN_RAAGA_DSP_TOP_0_INST_OBSERVE_CLOCK_reserved0_SHIFT 2
-
-/* CLKGEN :: RAAGA_DSP_TOP_0_INST_OBSERVE_CLOCK :: RAAGA_ENABLE_OBSERVE_CLOCK [01:01] */
-#define BCHP_CLKGEN_RAAGA_DSP_TOP_0_INST_OBSERVE_CLOCK_RAAGA_ENABLE_OBSERVE_CLOCK_MASK 0x00000002
-#define BCHP_CLKGEN_RAAGA_DSP_TOP_0_INST_OBSERVE_CLOCK_RAAGA_ENABLE_OBSERVE_CLOCK_SHIFT 1
-#define BCHP_CLKGEN_RAAGA_DSP_TOP_0_INST_OBSERVE_CLOCK_RAAGA_ENABLE_OBSERVE_CLOCK_DEFAULT 0x00000000
-
-/* CLKGEN :: RAAGA_DSP_TOP_0_INST_OBSERVE_CLOCK :: RAAGA_ENABLE_DIVIDER_OBSERVE_CLOCK [00:00] */
-#define BCHP_CLKGEN_RAAGA_DSP_TOP_0_INST_OBSERVE_CLOCK_RAAGA_ENABLE_DIVIDER_OBSERVE_CLOCK_MASK 0x00000001
-#define BCHP_CLKGEN_RAAGA_DSP_TOP_0_INST_OBSERVE_CLOCK_RAAGA_ENABLE_DIVIDER_OBSERVE_CLOCK_SHIFT 0
-#define BCHP_CLKGEN_RAAGA_DSP_TOP_0_INST_OBSERVE_CLOCK_RAAGA_ENABLE_DIVIDER_OBSERVE_CLOCK_DEFAULT 0x00000000
-
-/***************************************************************************
- *RFM_TOP_INST_CLOCK_ENABLE - Rfm top inst clock enable
- ***************************************************************************/
-/* CLKGEN :: RFM_TOP_INST_CLOCK_ENABLE :: reserved0 [31:03] */
-#define BCHP_CLKGEN_RFM_TOP_INST_CLOCK_ENABLE_reserved0_MASK 0xfffffff8
-#define BCHP_CLKGEN_RFM_TOP_INST_CLOCK_ENABLE_reserved0_SHIFT 3
-
-/* CLKGEN :: RFM_TOP_INST_CLOCK_ENABLE :: RFM_GISB_CLOCK_ENABLE [02:02] */
-#define BCHP_CLKGEN_RFM_TOP_INST_CLOCK_ENABLE_RFM_GISB_CLOCK_ENABLE_MASK 0x00000004
-#define BCHP_CLKGEN_RFM_TOP_INST_CLOCK_ENABLE_RFM_GISB_CLOCK_ENABLE_SHIFT 2
-#define BCHP_CLKGEN_RFM_TOP_INST_CLOCK_ENABLE_RFM_GISB_CLOCK_ENABLE_DEFAULT 0x00000001
-
-/* CLKGEN :: RFM_TOP_INST_CLOCK_ENABLE :: RFM_54_CLOCK_ENABLE [01:01] */
-#define BCHP_CLKGEN_RFM_TOP_INST_CLOCK_ENABLE_RFM_54_CLOCK_ENABLE_MASK 0x00000002
-#define BCHP_CLKGEN_RFM_TOP_INST_CLOCK_ENABLE_RFM_54_CLOCK_ENABLE_SHIFT 1
-#define BCHP_CLKGEN_RFM_TOP_INST_CLOCK_ENABLE_RFM_54_CLOCK_ENABLE_DEFAULT 0x00000001
-
-/* CLKGEN :: RFM_TOP_INST_CLOCK_ENABLE :: RFM_108_CLOCK_ENABLE [00:00] */
-#define BCHP_CLKGEN_RFM_TOP_INST_CLOCK_ENABLE_RFM_108_CLOCK_ENABLE_MASK 0x00000001
-#define BCHP_CLKGEN_RFM_TOP_INST_CLOCK_ENABLE_RFM_108_CLOCK_ENABLE_SHIFT 0
-#define BCHP_CLKGEN_RFM_TOP_INST_CLOCK_ENABLE_RFM_108_CLOCK_ENABLE_DEFAULT 0x00000001
-
-/***************************************************************************
- *RFM_TOP_INST_CLOCK_ENABLE_STATUS - Clock Enable Status
- ***************************************************************************/
-/* CLKGEN :: RFM_TOP_INST_CLOCK_ENABLE_STATUS :: reserved0 [31:03] */
-#define BCHP_CLKGEN_RFM_TOP_INST_CLOCK_ENABLE_STATUS_reserved0_MASK 0xfffffff8
-#define BCHP_CLKGEN_RFM_TOP_INST_CLOCK_ENABLE_STATUS_reserved0_SHIFT 3
-
-/* CLKGEN :: RFM_TOP_INST_CLOCK_ENABLE_STATUS :: RFM_GISB_CLOCK_ENABLE_STATUS [02:02] */
-#define BCHP_CLKGEN_RFM_TOP_INST_CLOCK_ENABLE_STATUS_RFM_GISB_CLOCK_ENABLE_STATUS_MASK 0x00000004
-#define BCHP_CLKGEN_RFM_TOP_INST_CLOCK_ENABLE_STATUS_RFM_GISB_CLOCK_ENABLE_STATUS_SHIFT 2
-
-/* CLKGEN :: RFM_TOP_INST_CLOCK_ENABLE_STATUS :: RFM_54_CLOCK_ENABLE_STATUS [01:01] */
-#define BCHP_CLKGEN_RFM_TOP_INST_CLOCK_ENABLE_STATUS_RFM_54_CLOCK_ENABLE_STATUS_MASK 0x00000002
-#define BCHP_CLKGEN_RFM_TOP_INST_CLOCK_ENABLE_STATUS_RFM_54_CLOCK_ENABLE_STATUS_SHIFT 1
-
-/* CLKGEN :: RFM_TOP_INST_CLOCK_ENABLE_STATUS :: RFM_108_CLOCK_ENABLE_STATUS [00:00] */
-#define BCHP_CLKGEN_RFM_TOP_INST_CLOCK_ENABLE_STATUS_RFM_108_CLOCK_ENABLE_STATUS_MASK 0x00000001
-#define BCHP_CLKGEN_RFM_TOP_INST_CLOCK_ENABLE_STATUS_RFM_108_CLOCK_ENABLE_STATUS_SHIFT 0
-
-/***************************************************************************
- *RFM_TOP_INST_OBSERVE_CLOCK - Rfm top inst observe clock
- ***************************************************************************/
-/* CLKGEN :: RFM_TOP_INST_OBSERVE_CLOCK :: reserved0 [31:06] */
-#define BCHP_CLKGEN_RFM_TOP_INST_OBSERVE_CLOCK_reserved0_MASK 0xffffffc0
-#define BCHP_CLKGEN_RFM_TOP_INST_OBSERVE_CLOCK_reserved0_SHIFT 6
-
-/* CLKGEN :: RFM_TOP_INST_OBSERVE_CLOCK :: RFM_ENABLE_OBSERVE_CLOCK [05:05] */
-#define BCHP_CLKGEN_RFM_TOP_INST_OBSERVE_CLOCK_RFM_ENABLE_OBSERVE_CLOCK_MASK 0x00000020
-#define BCHP_CLKGEN_RFM_TOP_INST_OBSERVE_CLOCK_RFM_ENABLE_OBSERVE_CLOCK_SHIFT 5
-#define BCHP_CLKGEN_RFM_TOP_INST_OBSERVE_CLOCK_RFM_ENABLE_OBSERVE_CLOCK_DEFAULT 0x00000000
-
-/* CLKGEN :: RFM_TOP_INST_OBSERVE_CLOCK :: RFM_ENABLE_DIVIDER_OBSERVE_CLOCK [04:04] */
-#define BCHP_CLKGEN_RFM_TOP_INST_OBSERVE_CLOCK_RFM_ENABLE_DIVIDER_OBSERVE_CLOCK_MASK 0x00000010
-#define BCHP_CLKGEN_RFM_TOP_INST_OBSERVE_CLOCK_RFM_ENABLE_DIVIDER_OBSERVE_CLOCK_SHIFT 4
-#define BCHP_CLKGEN_RFM_TOP_INST_OBSERVE_CLOCK_RFM_ENABLE_DIVIDER_OBSERVE_CLOCK_DEFAULT 0x00000000
-
-/* CLKGEN :: RFM_TOP_INST_OBSERVE_CLOCK :: RFM_CONTROL_OBSERVE_CLOCK [03:00] */
-#define BCHP_CLKGEN_RFM_TOP_INST_OBSERVE_CLOCK_RFM_CONTROL_OBSERVE_CLOCK_MASK 0x0000000f
-#define BCHP_CLKGEN_RFM_TOP_INST_OBSERVE_CLOCK_RFM_CONTROL_OBSERVE_CLOCK_SHIFT 0
-#define BCHP_CLKGEN_RFM_TOP_INST_OBSERVE_CLOCK_RFM_CONTROL_OBSERVE_CLOCK_DEFAULT 0x00000000
-
-/***************************************************************************
- *SATA3_TOP_INST_CLOCK_DISABLE - Disable SATA3_TOP_INST's clocks
- ***************************************************************************/
-/* CLKGEN :: SATA3_TOP_INST_CLOCK_DISABLE :: reserved0 [31:01] */
-#define BCHP_CLKGEN_SATA3_TOP_INST_CLOCK_DISABLE_reserved0_MASK 0xfffffffe
-#define BCHP_CLKGEN_SATA3_TOP_INST_CLOCK_DISABLE_reserved0_SHIFT 1
-
-/* CLKGEN :: SATA3_TOP_INST_CLOCK_DISABLE :: DISABLE_SATA3_AT_SPEED_SCAN_CLOCK [00:00] */
-#define BCHP_CLKGEN_SATA3_TOP_INST_CLOCK_DISABLE_DISABLE_SATA3_AT_SPEED_SCAN_CLOCK_MASK 0x00000001
-#define BCHP_CLKGEN_SATA3_TOP_INST_CLOCK_DISABLE_DISABLE_SATA3_AT_SPEED_SCAN_CLOCK_SHIFT 0
-#define BCHP_CLKGEN_SATA3_TOP_INST_CLOCK_DISABLE_DISABLE_SATA3_AT_SPEED_SCAN_CLOCK_DEFAULT 0x00000000
-
-/***************************************************************************
- *SATA3_TOP_INST_CLOCK_DISABLE_STATUS - Clock Disable Status
- ***************************************************************************/
-/* CLKGEN :: SATA3_TOP_INST_CLOCK_DISABLE_STATUS :: reserved0 [31:01] */
-#define BCHP_CLKGEN_SATA3_TOP_INST_CLOCK_DISABLE_STATUS_reserved0_MASK 0xfffffffe
-#define BCHP_CLKGEN_SATA3_TOP_INST_CLOCK_DISABLE_STATUS_reserved0_SHIFT 1
-
-/* CLKGEN :: SATA3_TOP_INST_CLOCK_DISABLE_STATUS :: DISABLE_SATA3_AT_SPEED_SCAN_CLOCK_STATUS [00:00] */
-#define BCHP_CLKGEN_SATA3_TOP_INST_CLOCK_DISABLE_STATUS_DISABLE_SATA3_AT_SPEED_SCAN_CLOCK_STATUS_MASK 0x00000001
-#define BCHP_CLKGEN_SATA3_TOP_INST_CLOCK_DISABLE_STATUS_DISABLE_SATA3_AT_SPEED_SCAN_CLOCK_STATUS_SHIFT 0
-
-/***************************************************************************
- *SATA3_TOP_INST_CLOCK_ENABLE - Sata3 top inst clock enable
- ***************************************************************************/
-/* CLKGEN :: SATA3_TOP_INST_CLOCK_ENABLE :: reserved0 [31:03] */
-#define BCHP_CLKGEN_SATA3_TOP_INST_CLOCK_ENABLE_reserved0_MASK 0xfffffff8
-#define BCHP_CLKGEN_SATA3_TOP_INST_CLOCK_ENABLE_reserved0_SHIFT 3
-
-/* CLKGEN :: SATA3_TOP_INST_CLOCK_ENABLE :: SATA3_SCB_CLOCK_ENABLE [02:02] */
-#define BCHP_CLKGEN_SATA3_TOP_INST_CLOCK_ENABLE_SATA3_SCB_CLOCK_ENABLE_MASK 0x00000004
-#define BCHP_CLKGEN_SATA3_TOP_INST_CLOCK_ENABLE_SATA3_SCB_CLOCK_ENABLE_SHIFT 2
-#define BCHP_CLKGEN_SATA3_TOP_INST_CLOCK_ENABLE_SATA3_SCB_CLOCK_ENABLE_DEFAULT 0x00000001
-
-/* CLKGEN :: SATA3_TOP_INST_CLOCK_ENABLE :: SATA3_GISB_CLOCK_ENABLE [01:01] */
-#define BCHP_CLKGEN_SATA3_TOP_INST_CLOCK_ENABLE_SATA3_GISB_CLOCK_ENABLE_MASK 0x00000002
-#define BCHP_CLKGEN_SATA3_TOP_INST_CLOCK_ENABLE_SATA3_GISB_CLOCK_ENABLE_SHIFT 1
-#define BCHP_CLKGEN_SATA3_TOP_INST_CLOCK_ENABLE_SATA3_GISB_CLOCK_ENABLE_DEFAULT 0x00000001
-
-/* CLKGEN :: SATA3_TOP_INST_CLOCK_ENABLE :: SATA3_54_CLOCK_ENABLE [00:00] */
-#define BCHP_CLKGEN_SATA3_TOP_INST_CLOCK_ENABLE_SATA3_54_CLOCK_ENABLE_MASK 0x00000001
-#define BCHP_CLKGEN_SATA3_TOP_INST_CLOCK_ENABLE_SATA3_54_CLOCK_ENABLE_SHIFT 0
-#define BCHP_CLKGEN_SATA3_TOP_INST_CLOCK_ENABLE_SATA3_54_CLOCK_ENABLE_DEFAULT 0x00000001
-
-/***************************************************************************
- *SATA3_TOP_INST_CLOCK_ENABLE_STATUS - Clock Enable Status
- ***************************************************************************/
-/* CLKGEN :: SATA3_TOP_INST_CLOCK_ENABLE_STATUS :: reserved0 [31:03] */
-#define BCHP_CLKGEN_SATA3_TOP_INST_CLOCK_ENABLE_STATUS_reserved0_MASK 0xfffffff8
-#define BCHP_CLKGEN_SATA3_TOP_INST_CLOCK_ENABLE_STATUS_reserved0_SHIFT 3
-
-/* CLKGEN :: SATA3_TOP_INST_CLOCK_ENABLE_STATUS :: SATA3_SCB_CLOCK_ENABLE_STATUS [02:02] */
-#define BCHP_CLKGEN_SATA3_TOP_INST_CLOCK_ENABLE_STATUS_SATA3_SCB_CLOCK_ENABLE_STATUS_MASK 0x00000004
-#define BCHP_CLKGEN_SATA3_TOP_INST_CLOCK_ENABLE_STATUS_SATA3_SCB_CLOCK_ENABLE_STATUS_SHIFT 2
-
-/* CLKGEN :: SATA3_TOP_INST_CLOCK_ENABLE_STATUS :: SATA3_GISB_CLOCK_ENABLE_STATUS [01:01] */
-#define BCHP_CLKGEN_SATA3_TOP_INST_CLOCK_ENABLE_STATUS_SATA3_GISB_CLOCK_ENABLE_STATUS_MASK 0x00000002
-#define BCHP_CLKGEN_SATA3_TOP_INST_CLOCK_ENABLE_STATUS_SATA3_GISB_CLOCK_ENABLE_STATUS_SHIFT 1
-
-/* CLKGEN :: SATA3_TOP_INST_CLOCK_ENABLE_STATUS :: SATA3_54_CLOCK_ENABLE_STATUS [00:00] */
-#define BCHP_CLKGEN_SATA3_TOP_INST_CLOCK_ENABLE_STATUS_SATA3_54_CLOCK_ENABLE_STATUS_MASK 0x00000001
-#define BCHP_CLKGEN_SATA3_TOP_INST_CLOCK_ENABLE_STATUS_SATA3_54_CLOCK_ENABLE_STATUS_SHIFT 0
-
-/***************************************************************************
- *SATA3_TOP_INST_CLOCK_SELECT - Sata3 top inst clock select
- ***************************************************************************/
-/* CLKGEN :: SATA3_TOP_INST_CLOCK_SELECT :: reserved0 [31:03] */
-#define BCHP_CLKGEN_SATA3_TOP_INST_CLOCK_SELECT_reserved0_MASK 0xfffffff8
-#define BCHP_CLKGEN_SATA3_TOP_INST_CLOCK_SELECT_reserved0_SHIFT 3
-
-/* CLKGEN :: SATA3_TOP_INST_CLOCK_SELECT :: SATA3_REF_CLOCK_SELECT [02:00] */
-#define BCHP_CLKGEN_SATA3_TOP_INST_CLOCK_SELECT_SATA3_REF_CLOCK_SELECT_MASK 0x00000007
-#define BCHP_CLKGEN_SATA3_TOP_INST_CLOCK_SELECT_SATA3_REF_CLOCK_SELECT_SHIFT 0
-#define BCHP_CLKGEN_SATA3_TOP_INST_CLOCK_SELECT_SATA3_REF_CLOCK_SELECT_DEFAULT 0x00000000
-
-/***************************************************************************
- *SATA3_TOP_INST_OBSERVE_CLOCK - Sata3 top inst observe clock
- ***************************************************************************/
-/* CLKGEN :: SATA3_TOP_INST_OBSERVE_CLOCK :: reserved0 [31:06] */
-#define BCHP_CLKGEN_SATA3_TOP_INST_OBSERVE_CLOCK_reserved0_MASK 0xffffffc0
-#define BCHP_CLKGEN_SATA3_TOP_INST_OBSERVE_CLOCK_reserved0_SHIFT 6
-
-/* CLKGEN :: SATA3_TOP_INST_OBSERVE_CLOCK :: SATA3_ENABLE_OBSERVE_CLOCK [05:05] */
-#define BCHP_CLKGEN_SATA3_TOP_INST_OBSERVE_CLOCK_SATA3_ENABLE_OBSERVE_CLOCK_MASK 0x00000020
-#define BCHP_CLKGEN_SATA3_TOP_INST_OBSERVE_CLOCK_SATA3_ENABLE_OBSERVE_CLOCK_SHIFT 5
-#define BCHP_CLKGEN_SATA3_TOP_INST_OBSERVE_CLOCK_SATA3_ENABLE_OBSERVE_CLOCK_DEFAULT 0x00000000
-
-/* CLKGEN :: SATA3_TOP_INST_OBSERVE_CLOCK :: SATA3_ENABLE_DIVIDER_OBSERVE_CLOCK [04:04] */
-#define BCHP_CLKGEN_SATA3_TOP_INST_OBSERVE_CLOCK_SATA3_ENABLE_DIVIDER_OBSERVE_CLOCK_MASK 0x00000010
-#define BCHP_CLKGEN_SATA3_TOP_INST_OBSERVE_CLOCK_SATA3_ENABLE_DIVIDER_OBSERVE_CLOCK_SHIFT 4
-#define BCHP_CLKGEN_SATA3_TOP_INST_OBSERVE_CLOCK_SATA3_ENABLE_DIVIDER_OBSERVE_CLOCK_DEFAULT 0x00000000
-
-/* CLKGEN :: SATA3_TOP_INST_OBSERVE_CLOCK :: SATA3_CONTROL_OBSERVE_CLOCK [03:00] */
-#define BCHP_CLKGEN_SATA3_TOP_INST_OBSERVE_CLOCK_SATA3_CONTROL_OBSERVE_CLOCK_MASK 0x0000000f
-#define BCHP_CLKGEN_SATA3_TOP_INST_OBSERVE_CLOCK_SATA3_CONTROL_OBSERVE_CLOCK_SHIFT 0
-#define BCHP_CLKGEN_SATA3_TOP_INST_OBSERVE_CLOCK_SATA3_CONTROL_OBSERVE_CLOCK_DEFAULT 0x00000000
-
-/***************************************************************************
- *SECTOP_INST_OBSERVE_CLOCK - Sectop inst observe clock
- ***************************************************************************/
-/* CLKGEN :: SECTOP_INST_OBSERVE_CLOCK :: reserved0 [31:06] */
-#define BCHP_CLKGEN_SECTOP_INST_OBSERVE_CLOCK_reserved0_MASK 0xffffffc0
-#define BCHP_CLKGEN_SECTOP_INST_OBSERVE_CLOCK_reserved0_SHIFT 6
-
-/* CLKGEN :: SECTOP_INST_OBSERVE_CLOCK :: SECTOP_ENABLE_OBSERVE_CLOCK [05:05] */
-#define BCHP_CLKGEN_SECTOP_INST_OBSERVE_CLOCK_SECTOP_ENABLE_OBSERVE_CLOCK_MASK 0x00000020
-#define BCHP_CLKGEN_SECTOP_INST_OBSERVE_CLOCK_SECTOP_ENABLE_OBSERVE_CLOCK_SHIFT 5
-#define BCHP_CLKGEN_SECTOP_INST_OBSERVE_CLOCK_SECTOP_ENABLE_OBSERVE_CLOCK_DEFAULT 0x00000000
-
-/* CLKGEN :: SECTOP_INST_OBSERVE_CLOCK :: SECTOP_ENABLE_DIVIDER_OBSERVE_CLOCK [04:04] */
-#define BCHP_CLKGEN_SECTOP_INST_OBSERVE_CLOCK_SECTOP_ENABLE_DIVIDER_OBSERVE_CLOCK_MASK 0x00000010
-#define BCHP_CLKGEN_SECTOP_INST_OBSERVE_CLOCK_SECTOP_ENABLE_DIVIDER_OBSERVE_CLOCK_SHIFT 4
-#define BCHP_CLKGEN_SECTOP_INST_OBSERVE_CLOCK_SECTOP_ENABLE_DIVIDER_OBSERVE_CLOCK_DEFAULT 0x00000000
-
-/* CLKGEN :: SECTOP_INST_OBSERVE_CLOCK :: SECTOP_CONTROL_OBSERVE_CLOCK [03:00] */
-#define BCHP_CLKGEN_SECTOP_INST_OBSERVE_CLOCK_SECTOP_CONTROL_OBSERVE_CLOCK_MASK 0x0000000f
-#define BCHP_CLKGEN_SECTOP_INST_OBSERVE_CLOCK_SECTOP_CONTROL_OBSERVE_CLOCK_SHIFT 0
-#define BCHP_CLKGEN_SECTOP_INST_OBSERVE_CLOCK_SECTOP_CONTROL_OBSERVE_CLOCK_DEFAULT 0x00000000
-
-/***************************************************************************
- *SMARTCARD_MUX_SELECT - Mux selects for Smartcard clocks
- ***************************************************************************/
-/* CLKGEN :: SMARTCARD_MUX_SELECT :: reserved0 [31:02] */
-#define BCHP_CLKGEN_SMARTCARD_MUX_SELECT_reserved0_MASK 0xfffffffc
-#define BCHP_CLKGEN_SMARTCARD_MUX_SELECT_reserved0_SHIFT 2
-
-/* CLKGEN :: SMARTCARD_MUX_SELECT :: SC1_CLOCK [01:01] */
-#define BCHP_CLKGEN_SMARTCARD_MUX_SELECT_SC1_CLOCK_MASK 0x00000002
-#define BCHP_CLKGEN_SMARTCARD_MUX_SELECT_SC1_CLOCK_SHIFT 1
-#define BCHP_CLKGEN_SMARTCARD_MUX_SELECT_SC1_CLOCK_DEFAULT 0x00000000
-
-/* CLKGEN :: SMARTCARD_MUX_SELECT :: SC0_CLOCK [00:00] */
-#define BCHP_CLKGEN_SMARTCARD_MUX_SELECT_SC0_CLOCK_MASK 0x00000001
-#define BCHP_CLKGEN_SMARTCARD_MUX_SELECT_SC0_CLOCK_SHIFT 0
-#define BCHP_CLKGEN_SMARTCARD_MUX_SELECT_SC0_CLOCK_DEFAULT 0x00000000
-
-/***************************************************************************
- *SPARE - Spares
- ***************************************************************************/
-/* CLKGEN :: SPARE :: SPARE_RESET_LOW [31:12] */
-#define BCHP_CLKGEN_SPARE_SPARE_RESET_LOW_MASK 0xfffff000
-#define BCHP_CLKGEN_SPARE_SPARE_RESET_LOW_SHIFT 12
-#define BCHP_CLKGEN_SPARE_SPARE_RESET_LOW_DEFAULT 0x00000000
-
-/* CLKGEN :: SPARE :: SPARE_RESET_HIGH [11:00] */
-#define BCHP_CLKGEN_SPARE_SPARE_RESET_HIGH_MASK 0x00000fff
-#define BCHP_CLKGEN_SPARE_SPARE_RESET_HIGH_SHIFT 0
-#define BCHP_CLKGEN_SPARE_SPARE_RESET_HIGH_DEFAULT 0x00000000
-
-/***************************************************************************
- *SYS_CTRL_INST_CLOCK_DISABLE - Disable SYS_CTRL_INST's clocks
- ***************************************************************************/
-/* CLKGEN :: SYS_CTRL_INST_CLOCK_DISABLE :: reserved0 [31:05] */
-#define BCHP_CLKGEN_SYS_CTRL_INST_CLOCK_DISABLE_reserved0_MASK 0xffffffe0
-#define BCHP_CLKGEN_SYS_CTRL_INST_CLOCK_DISABLE_reserved0_SHIFT 5
-
-/* CLKGEN :: SYS_CTRL_INST_CLOCK_DISABLE :: DISABLE_SYSCTRL_UPG_CLOCK [04:04] */
-#define BCHP_CLKGEN_SYS_CTRL_INST_CLOCK_DISABLE_DISABLE_SYSCTRL_UPG_CLOCK_MASK 0x00000010
-#define BCHP_CLKGEN_SYS_CTRL_INST_CLOCK_DISABLE_DISABLE_SYSCTRL_UPG_CLOCK_SHIFT 4
-#define BCHP_CLKGEN_SYS_CTRL_INST_CLOCK_DISABLE_DISABLE_SYSCTRL_UPG_CLOCK_DEFAULT 0x00000000
-
-/* CLKGEN :: SYS_CTRL_INST_CLOCK_DISABLE :: DISABLE_SC1_CLOCK [03:03] */
-#define BCHP_CLKGEN_SYS_CTRL_INST_CLOCK_DISABLE_DISABLE_SC1_CLOCK_MASK 0x00000008
-#define BCHP_CLKGEN_SYS_CTRL_INST_CLOCK_DISABLE_DISABLE_SC1_CLOCK_SHIFT 3
-#define BCHP_CLKGEN_SYS_CTRL_INST_CLOCK_DISABLE_DISABLE_SC1_CLOCK_DEFAULT 0x00000000
-
-/* CLKGEN :: SYS_CTRL_INST_CLOCK_DISABLE :: DISABLE_SC0_CLOCK [02:02] */
-#define BCHP_CLKGEN_SYS_CTRL_INST_CLOCK_DISABLE_DISABLE_SC0_CLOCK_MASK 0x00000004
-#define BCHP_CLKGEN_SYS_CTRL_INST_CLOCK_DISABLE_DISABLE_SC0_CLOCK_SHIFT 2
-#define BCHP_CLKGEN_SYS_CTRL_INST_CLOCK_DISABLE_DISABLE_SC0_CLOCK_DEFAULT 0x00000000
-
-/* CLKGEN :: SYS_CTRL_INST_CLOCK_DISABLE :: DISABLE_AVSTOP_PVTMON_CLOCK [01:01] */
-#define BCHP_CLKGEN_SYS_CTRL_INST_CLOCK_DISABLE_DISABLE_AVSTOP_PVTMON_CLOCK_MASK 0x00000002
-#define BCHP_CLKGEN_SYS_CTRL_INST_CLOCK_DISABLE_DISABLE_AVSTOP_PVTMON_CLOCK_SHIFT 1
-#define BCHP_CLKGEN_SYS_CTRL_INST_CLOCK_DISABLE_DISABLE_AVSTOP_PVTMON_CLOCK_DEFAULT 0x00000000
-
-/* CLKGEN :: SYS_CTRL_INST_CLOCK_DISABLE :: DISABLE_AVSTOP_27_UART_CLOCK [00:00] */
-#define BCHP_CLKGEN_SYS_CTRL_INST_CLOCK_DISABLE_DISABLE_AVSTOP_27_UART_CLOCK_MASK 0x00000001
-#define BCHP_CLKGEN_SYS_CTRL_INST_CLOCK_DISABLE_DISABLE_AVSTOP_27_UART_CLOCK_SHIFT 0
-#define BCHP_CLKGEN_SYS_CTRL_INST_CLOCK_DISABLE_DISABLE_AVSTOP_27_UART_CLOCK_DEFAULT 0x00000000
-
-/***************************************************************************
- *SYS_CTRL_INST_CLOCK_DISABLE_STATUS - Clock Disable Status
- ***************************************************************************/
-/* CLKGEN :: SYS_CTRL_INST_CLOCK_DISABLE_STATUS :: reserved0 [31:05] */
-#define BCHP_CLKGEN_SYS_CTRL_INST_CLOCK_DISABLE_STATUS_reserved0_MASK 0xffffffe0
-#define BCHP_CLKGEN_SYS_CTRL_INST_CLOCK_DISABLE_STATUS_reserved0_SHIFT 5
-
-/* CLKGEN :: SYS_CTRL_INST_CLOCK_DISABLE_STATUS :: DISABLE_SYSCTRL_UPG_CLOCK_STATUS [04:04] */
-#define BCHP_CLKGEN_SYS_CTRL_INST_CLOCK_DISABLE_STATUS_DISABLE_SYSCTRL_UPG_CLOCK_STATUS_MASK 0x00000010
-#define BCHP_CLKGEN_SYS_CTRL_INST_CLOCK_DISABLE_STATUS_DISABLE_SYSCTRL_UPG_CLOCK_STATUS_SHIFT 4
-
-/* CLKGEN :: SYS_CTRL_INST_CLOCK_DISABLE_STATUS :: DISABLE_SC1_CLOCK_STATUS [03:03] */
-#define BCHP_CLKGEN_SYS_CTRL_INST_CLOCK_DISABLE_STATUS_DISABLE_SC1_CLOCK_STATUS_MASK 0x00000008
-#define BCHP_CLKGEN_SYS_CTRL_INST_CLOCK_DISABLE_STATUS_DISABLE_SC1_CLOCK_STATUS_SHIFT 3
-
-/* CLKGEN :: SYS_CTRL_INST_CLOCK_DISABLE_STATUS :: DISABLE_SC0_CLOCK_STATUS [02:02] */
-#define BCHP_CLKGEN_SYS_CTRL_INST_CLOCK_DISABLE_STATUS_DISABLE_SC0_CLOCK_STATUS_MASK 0x00000004
-#define BCHP_CLKGEN_SYS_CTRL_INST_CLOCK_DISABLE_STATUS_DISABLE_SC0_CLOCK_STATUS_SHIFT 2
-
-/* CLKGEN :: SYS_CTRL_INST_CLOCK_DISABLE_STATUS :: DISABLE_AVSTOP_PVTMON_CLOCK_STATUS [01:01] */
-#define BCHP_CLKGEN_SYS_CTRL_INST_CLOCK_DISABLE_STATUS_DISABLE_AVSTOP_PVTMON_CLOCK_STATUS_MASK 0x00000002
-#define BCHP_CLKGEN_SYS_CTRL_INST_CLOCK_DISABLE_STATUS_DISABLE_AVSTOP_PVTMON_CLOCK_STATUS_SHIFT 1
-
-/* CLKGEN :: SYS_CTRL_INST_CLOCK_DISABLE_STATUS :: DISABLE_AVSTOP_27_UART_CLOCK_STATUS [00:00] */
-#define BCHP_CLKGEN_SYS_CTRL_INST_CLOCK_DISABLE_STATUS_DISABLE_AVSTOP_27_UART_CLOCK_STATUS_MASK 0x00000001
-#define BCHP_CLKGEN_SYS_CTRL_INST_CLOCK_DISABLE_STATUS_DISABLE_AVSTOP_27_UART_CLOCK_STATUS_SHIFT 0
-
-/***************************************************************************
- *SYS_CTRL_INST_OBSERVE_CLOCK - Sys ctrl inst observe clock
- ***************************************************************************/
-/* CLKGEN :: SYS_CTRL_INST_OBSERVE_CLOCK :: reserved0 [31:06] */
-#define BCHP_CLKGEN_SYS_CTRL_INST_OBSERVE_CLOCK_reserved0_MASK 0xffffffc0
-#define BCHP_CLKGEN_SYS_CTRL_INST_OBSERVE_CLOCK_reserved0_SHIFT 6
-
-/* CLKGEN :: SYS_CTRL_INST_OBSERVE_CLOCK :: AVS_TOP_ENABLE_OBSERVE_CLOCK [05:05] */
-#define BCHP_CLKGEN_SYS_CTRL_INST_OBSERVE_CLOCK_AVS_TOP_ENABLE_OBSERVE_CLOCK_MASK 0x00000020
-#define BCHP_CLKGEN_SYS_CTRL_INST_OBSERVE_CLOCK_AVS_TOP_ENABLE_OBSERVE_CLOCK_SHIFT 5
-#define BCHP_CLKGEN_SYS_CTRL_INST_OBSERVE_CLOCK_AVS_TOP_ENABLE_OBSERVE_CLOCK_DEFAULT 0x00000000
-
-/* CLKGEN :: SYS_CTRL_INST_OBSERVE_CLOCK :: AVS_TOP_ENABLE_DIVIDER_OBSERVE_CLOCK [04:04] */
-#define BCHP_CLKGEN_SYS_CTRL_INST_OBSERVE_CLOCK_AVS_TOP_ENABLE_DIVIDER_OBSERVE_CLOCK_MASK 0x00000010
-#define BCHP_CLKGEN_SYS_CTRL_INST_OBSERVE_CLOCK_AVS_TOP_ENABLE_DIVIDER_OBSERVE_CLOCK_SHIFT 4
-#define BCHP_CLKGEN_SYS_CTRL_INST_OBSERVE_CLOCK_AVS_TOP_ENABLE_DIVIDER_OBSERVE_CLOCK_DEFAULT 0x00000000
-
-/* CLKGEN :: SYS_CTRL_INST_OBSERVE_CLOCK :: AVS_TOP_CONTROL_OBSERVE_CLOCK [03:00] */
-#define BCHP_CLKGEN_SYS_CTRL_INST_OBSERVE_CLOCK_AVS_TOP_CONTROL_OBSERVE_CLOCK_MASK 0x0000000f
-#define BCHP_CLKGEN_SYS_CTRL_INST_OBSERVE_CLOCK_AVS_TOP_CONTROL_OBSERVE_CLOCK_SHIFT 0
-#define BCHP_CLKGEN_SYS_CTRL_INST_OBSERVE_CLOCK_AVS_TOP_CONTROL_OBSERVE_CLOCK_DEFAULT 0x00000000
-
-/***************************************************************************
- *TESTPORT - Special Testport Controls
- ***************************************************************************/
-/* CLKGEN :: TESTPORT :: reserved0 [31:04] */
-#define BCHP_CLKGEN_TESTPORT_reserved0_MASK 0xfffffff0
-#define BCHP_CLKGEN_TESTPORT_reserved0_SHIFT 4
-
-/* CLKGEN :: TESTPORT :: PLL_TEST_STATUS_SELECT [03:00] */
-#define BCHP_CLKGEN_TESTPORT_PLL_TEST_STATUS_SELECT_MASK 0x0000000f
-#define BCHP_CLKGEN_TESTPORT_PLL_TEST_STATUS_SELECT_SHIFT 0
-#define BCHP_CLKGEN_TESTPORT_PLL_TEST_STATUS_SELECT_DEFAULT 0x00000000
-
-/***************************************************************************
- *USB0_TOP_INST_CLOCK_DISABLE - Disable USB0_TOP_INST's clocks
- ***************************************************************************/
-/* CLKGEN :: USB0_TOP_INST_CLOCK_DISABLE :: reserved0 [31:02] */
-#define BCHP_CLKGEN_USB0_TOP_INST_CLOCK_DISABLE_reserved0_MASK 0xfffffffc
-#define BCHP_CLKGEN_USB0_TOP_INST_CLOCK_DISABLE_reserved0_SHIFT 2
-
-/* CLKGEN :: USB0_TOP_INST_CLOCK_DISABLE :: DISABLE_USB0_FREERUN_CLOCK [01:01] */
-#define BCHP_CLKGEN_USB0_TOP_INST_CLOCK_DISABLE_DISABLE_USB0_FREERUN_CLOCK_MASK 0x00000002
-#define BCHP_CLKGEN_USB0_TOP_INST_CLOCK_DISABLE_DISABLE_USB0_FREERUN_CLOCK_SHIFT 1
-#define BCHP_CLKGEN_USB0_TOP_INST_CLOCK_DISABLE_DISABLE_USB0_FREERUN_CLOCK_DEFAULT 0x00000000
-
-/* CLKGEN :: USB0_TOP_INST_CLOCK_DISABLE :: DISABLE_USB0_54_MDIO_CLOCK [00:00] */
-#define BCHP_CLKGEN_USB0_TOP_INST_CLOCK_DISABLE_DISABLE_USB0_54_MDIO_CLOCK_MASK 0x00000001
-#define BCHP_CLKGEN_USB0_TOP_INST_CLOCK_DISABLE_DISABLE_USB0_54_MDIO_CLOCK_SHIFT 0
-#define BCHP_CLKGEN_USB0_TOP_INST_CLOCK_DISABLE_DISABLE_USB0_54_MDIO_CLOCK_DEFAULT 0x00000000
-
-/***************************************************************************
- *USB0_TOP_INST_CLOCK_DISABLE_STATUS - Clock Disable Status
- ***************************************************************************/
-/* CLKGEN :: USB0_TOP_INST_CLOCK_DISABLE_STATUS :: reserved0 [31:02] */
-#define BCHP_CLKGEN_USB0_TOP_INST_CLOCK_DISABLE_STATUS_reserved0_MASK 0xfffffffc
-#define BCHP_CLKGEN_USB0_TOP_INST_CLOCK_DISABLE_STATUS_reserved0_SHIFT 2
-
-/* CLKGEN :: USB0_TOP_INST_CLOCK_DISABLE_STATUS :: DISABLE_USB0_FREERUN_CLOCK_STATUS [01:01] */
-#define BCHP_CLKGEN_USB0_TOP_INST_CLOCK_DISABLE_STATUS_DISABLE_USB0_FREERUN_CLOCK_STATUS_MASK 0x00000002
-#define BCHP_CLKGEN_USB0_TOP_INST_CLOCK_DISABLE_STATUS_DISABLE_USB0_FREERUN_CLOCK_STATUS_SHIFT 1
-
-/* CLKGEN :: USB0_TOP_INST_CLOCK_DISABLE_STATUS :: DISABLE_USB0_54_MDIO_CLOCK_STATUS [00:00] */
-#define BCHP_CLKGEN_USB0_TOP_INST_CLOCK_DISABLE_STATUS_DISABLE_USB0_54_MDIO_CLOCK_STATUS_MASK 0x00000001
-#define BCHP_CLKGEN_USB0_TOP_INST_CLOCK_DISABLE_STATUS_DISABLE_USB0_54_MDIO_CLOCK_STATUS_SHIFT 0
-
-/***************************************************************************
- *USB0_TOP_INST_CLOCK_ENABLE - Usb0 top inst clock enable
- ***************************************************************************/
-/* CLKGEN :: USB0_TOP_INST_CLOCK_ENABLE :: reserved0 [31:03] */
-#define BCHP_CLKGEN_USB0_TOP_INST_CLOCK_ENABLE_reserved0_MASK 0xfffffff8
-#define BCHP_CLKGEN_USB0_TOP_INST_CLOCK_ENABLE_reserved0_SHIFT 3
-
-/* CLKGEN :: USB0_TOP_INST_CLOCK_ENABLE :: USB0_SCB_CLOCK_ENABLE [02:02] */
-#define BCHP_CLKGEN_USB0_TOP_INST_CLOCK_ENABLE_USB0_SCB_CLOCK_ENABLE_MASK 0x00000004
-#define BCHP_CLKGEN_USB0_TOP_INST_CLOCK_ENABLE_USB0_SCB_CLOCK_ENABLE_SHIFT 2
-#define BCHP_CLKGEN_USB0_TOP_INST_CLOCK_ENABLE_USB0_SCB_CLOCK_ENABLE_DEFAULT 0x00000001
-
-/* CLKGEN :: USB0_TOP_INST_CLOCK_ENABLE :: USB0_GISB_CLOCK_ENABLE [01:01] */
-#define BCHP_CLKGEN_USB0_TOP_INST_CLOCK_ENABLE_USB0_GISB_CLOCK_ENABLE_MASK 0x00000002
-#define BCHP_CLKGEN_USB0_TOP_INST_CLOCK_ENABLE_USB0_GISB_CLOCK_ENABLE_SHIFT 1
-#define BCHP_CLKGEN_USB0_TOP_INST_CLOCK_ENABLE_USB0_GISB_CLOCK_ENABLE_DEFAULT 0x00000001
-
-/* CLKGEN :: USB0_TOP_INST_CLOCK_ENABLE :: USB0_54_CLOCK_ENABLE [00:00] */
-#define BCHP_CLKGEN_USB0_TOP_INST_CLOCK_ENABLE_USB0_54_CLOCK_ENABLE_MASK 0x00000001
-#define BCHP_CLKGEN_USB0_TOP_INST_CLOCK_ENABLE_USB0_54_CLOCK_ENABLE_SHIFT 0
-#define BCHP_CLKGEN_USB0_TOP_INST_CLOCK_ENABLE_USB0_54_CLOCK_ENABLE_DEFAULT 0x00000001
-
-/***************************************************************************
- *USB0_TOP_INST_CLOCK_ENABLE_AHB - Usb0 top inst clock enable ahb
- ***************************************************************************/
-/* CLKGEN :: USB0_TOP_INST_CLOCK_ENABLE_AHB :: reserved0 [31:01] */
-#define BCHP_CLKGEN_USB0_TOP_INST_CLOCK_ENABLE_AHB_reserved0_MASK 0xfffffffe
-#define BCHP_CLKGEN_USB0_TOP_INST_CLOCK_ENABLE_AHB_reserved0_SHIFT 1
-
-/* CLKGEN :: USB0_TOP_INST_CLOCK_ENABLE_AHB :: USB0_108_CLOCK_ENABLE_AHB [00:00] */
-#define BCHP_CLKGEN_USB0_TOP_INST_CLOCK_ENABLE_AHB_USB0_108_CLOCK_ENABLE_AHB_MASK 0x00000001
-#define BCHP_CLKGEN_USB0_TOP_INST_CLOCK_ENABLE_AHB_USB0_108_CLOCK_ENABLE_AHB_SHIFT 0
-#define BCHP_CLKGEN_USB0_TOP_INST_CLOCK_ENABLE_AHB_USB0_108_CLOCK_ENABLE_AHB_DEFAULT 0x00000001
-
-/***************************************************************************
- *USB0_TOP_INST_CLOCK_ENABLE_AHB_STATUS - Clock Enable Status
- ***************************************************************************/
-/* CLKGEN :: USB0_TOP_INST_CLOCK_ENABLE_AHB_STATUS :: reserved0 [31:01] */
-#define BCHP_CLKGEN_USB0_TOP_INST_CLOCK_ENABLE_AHB_STATUS_reserved0_MASK 0xfffffffe
-#define BCHP_CLKGEN_USB0_TOP_INST_CLOCK_ENABLE_AHB_STATUS_reserved0_SHIFT 1
-
-/* CLKGEN :: USB0_TOP_INST_CLOCK_ENABLE_AHB_STATUS :: USB0_108_CLOCK_ENABLE_AHB_STATUS [00:00] */
-#define BCHP_CLKGEN_USB0_TOP_INST_CLOCK_ENABLE_AHB_STATUS_USB0_108_CLOCK_ENABLE_AHB_STATUS_MASK 0x00000001
-#define BCHP_CLKGEN_USB0_TOP_INST_CLOCK_ENABLE_AHB_STATUS_USB0_108_CLOCK_ENABLE_AHB_STATUS_SHIFT 0
-
-/***************************************************************************
- *USB0_TOP_INST_CLOCK_ENABLE_AXI - Usb0 top inst clock enable axi
- ***************************************************************************/
-/* CLKGEN :: USB0_TOP_INST_CLOCK_ENABLE_AXI :: reserved0 [31:01] */
-#define BCHP_CLKGEN_USB0_TOP_INST_CLOCK_ENABLE_AXI_reserved0_MASK 0xfffffffe
-#define BCHP_CLKGEN_USB0_TOP_INST_CLOCK_ENABLE_AXI_reserved0_SHIFT 1
-
-/* CLKGEN :: USB0_TOP_INST_CLOCK_ENABLE_AXI :: USB0_108_CLOCK_ENABLE_AXI [00:00] */
-#define BCHP_CLKGEN_USB0_TOP_INST_CLOCK_ENABLE_AXI_USB0_108_CLOCK_ENABLE_AXI_MASK 0x00000001
-#define BCHP_CLKGEN_USB0_TOP_INST_CLOCK_ENABLE_AXI_USB0_108_CLOCK_ENABLE_AXI_SHIFT 0
-#define BCHP_CLKGEN_USB0_TOP_INST_CLOCK_ENABLE_AXI_USB0_108_CLOCK_ENABLE_AXI_DEFAULT 0x00000001
-
-/***************************************************************************
- *USB0_TOP_INST_CLOCK_ENABLE_AXI_STATUS - Clock Enable Status
- ***************************************************************************/
-/* CLKGEN :: USB0_TOP_INST_CLOCK_ENABLE_AXI_STATUS :: reserved0 [31:01] */
-#define BCHP_CLKGEN_USB0_TOP_INST_CLOCK_ENABLE_AXI_STATUS_reserved0_MASK 0xfffffffe
-#define BCHP_CLKGEN_USB0_TOP_INST_CLOCK_ENABLE_AXI_STATUS_reserved0_SHIFT 1
-
-/* CLKGEN :: USB0_TOP_INST_CLOCK_ENABLE_AXI_STATUS :: USB0_108_CLOCK_ENABLE_AXI_STATUS [00:00] */
-#define BCHP_CLKGEN_USB0_TOP_INST_CLOCK_ENABLE_AXI_STATUS_USB0_108_CLOCK_ENABLE_AXI_STATUS_MASK 0x00000001
-#define BCHP_CLKGEN_USB0_TOP_INST_CLOCK_ENABLE_AXI_STATUS_USB0_108_CLOCK_ENABLE_AXI_STATUS_SHIFT 0
-
-/***************************************************************************
- *USB0_TOP_INST_CLOCK_ENABLE_STATUS - Clock Enable Status
- ***************************************************************************/
-/* CLKGEN :: USB0_TOP_INST_CLOCK_ENABLE_STATUS :: reserved0 [31:03] */
-#define BCHP_CLKGEN_USB0_TOP_INST_CLOCK_ENABLE_STATUS_reserved0_MASK 0xfffffff8
-#define BCHP_CLKGEN_USB0_TOP_INST_CLOCK_ENABLE_STATUS_reserved0_SHIFT 3
-
-/* CLKGEN :: USB0_TOP_INST_CLOCK_ENABLE_STATUS :: USB0_SCB_CLOCK_ENABLE_STATUS [02:02] */
-#define BCHP_CLKGEN_USB0_TOP_INST_CLOCK_ENABLE_STATUS_USB0_SCB_CLOCK_ENABLE_STATUS_MASK 0x00000004
-#define BCHP_CLKGEN_USB0_TOP_INST_CLOCK_ENABLE_STATUS_USB0_SCB_CLOCK_ENABLE_STATUS_SHIFT 2
-
-/* CLKGEN :: USB0_TOP_INST_CLOCK_ENABLE_STATUS :: USB0_GISB_CLOCK_ENABLE_STATUS [01:01] */
-#define BCHP_CLKGEN_USB0_TOP_INST_CLOCK_ENABLE_STATUS_USB0_GISB_CLOCK_ENABLE_STATUS_MASK 0x00000002
-#define BCHP_CLKGEN_USB0_TOP_INST_CLOCK_ENABLE_STATUS_USB0_GISB_CLOCK_ENABLE_STATUS_SHIFT 1
-
-/* CLKGEN :: USB0_TOP_INST_CLOCK_ENABLE_STATUS :: USB0_54_CLOCK_ENABLE_STATUS [00:00] */
-#define BCHP_CLKGEN_USB0_TOP_INST_CLOCK_ENABLE_STATUS_USB0_54_CLOCK_ENABLE_STATUS_MASK 0x00000001
-#define BCHP_CLKGEN_USB0_TOP_INST_CLOCK_ENABLE_STATUS_USB0_54_CLOCK_ENABLE_STATUS_SHIFT 0
-
-/***************************************************************************
- *USB0_TOP_INST_OBSERVE_CLOCK - Usb0 top inst observe clock
- ***************************************************************************/
-/* CLKGEN :: USB0_TOP_INST_OBSERVE_CLOCK :: reserved0 [31:06] */
-#define BCHP_CLKGEN_USB0_TOP_INST_OBSERVE_CLOCK_reserved0_MASK 0xffffffc0
-#define BCHP_CLKGEN_USB0_TOP_INST_OBSERVE_CLOCK_reserved0_SHIFT 6
-
-/* CLKGEN :: USB0_TOP_INST_OBSERVE_CLOCK :: USB0_ENABLE_OBSERVE_CLOCK [05:05] */
-#define BCHP_CLKGEN_USB0_TOP_INST_OBSERVE_CLOCK_USB0_ENABLE_OBSERVE_CLOCK_MASK 0x00000020
-#define BCHP_CLKGEN_USB0_TOP_INST_OBSERVE_CLOCK_USB0_ENABLE_OBSERVE_CLOCK_SHIFT 5
-#define BCHP_CLKGEN_USB0_TOP_INST_OBSERVE_CLOCK_USB0_ENABLE_OBSERVE_CLOCK_DEFAULT 0x00000000
-
-/* CLKGEN :: USB0_TOP_INST_OBSERVE_CLOCK :: USB0_ENABLE_DIVIDER_OBSERVE_CLOCK [04:04] */
-#define BCHP_CLKGEN_USB0_TOP_INST_OBSERVE_CLOCK_USB0_ENABLE_DIVIDER_OBSERVE_CLOCK_MASK 0x00000010
-#define BCHP_CLKGEN_USB0_TOP_INST_OBSERVE_CLOCK_USB0_ENABLE_DIVIDER_OBSERVE_CLOCK_SHIFT 4
-#define BCHP_CLKGEN_USB0_TOP_INST_OBSERVE_CLOCK_USB0_ENABLE_DIVIDER_OBSERVE_CLOCK_DEFAULT 0x00000000
-
-/* CLKGEN :: USB0_TOP_INST_OBSERVE_CLOCK :: USB0_CONTROL_OBSERVE_CLOCK [03:00] */
-#define BCHP_CLKGEN_USB0_TOP_INST_OBSERVE_CLOCK_USB0_CONTROL_OBSERVE_CLOCK_MASK 0x0000000f
-#define BCHP_CLKGEN_USB0_TOP_INST_OBSERVE_CLOCK_USB0_CONTROL_OBSERVE_CLOCK_SHIFT 0
-#define BCHP_CLKGEN_USB0_TOP_INST_OBSERVE_CLOCK_USB0_CONTROL_OBSERVE_CLOCK_DEFAULT 0x00000000
-
-/***************************************************************************
- *USB1_TOP_INST_CLOCK_DISABLE - Disable USB1_TOP_INST's clocks
- ***************************************************************************/
-/* CLKGEN :: USB1_TOP_INST_CLOCK_DISABLE :: reserved0 [31:02] */
-#define BCHP_CLKGEN_USB1_TOP_INST_CLOCK_DISABLE_reserved0_MASK 0xfffffffc
-#define BCHP_CLKGEN_USB1_TOP_INST_CLOCK_DISABLE_reserved0_SHIFT 2
-
-/* CLKGEN :: USB1_TOP_INST_CLOCK_DISABLE :: DISABLE_USB1_FREERUN_CLOCK [01:01] */
-#define BCHP_CLKGEN_USB1_TOP_INST_CLOCK_DISABLE_DISABLE_USB1_FREERUN_CLOCK_MASK 0x00000002
-#define BCHP_CLKGEN_USB1_TOP_INST_CLOCK_DISABLE_DISABLE_USB1_FREERUN_CLOCK_SHIFT 1
-#define BCHP_CLKGEN_USB1_TOP_INST_CLOCK_DISABLE_DISABLE_USB1_FREERUN_CLOCK_DEFAULT 0x00000000
-
-/* CLKGEN :: USB1_TOP_INST_CLOCK_DISABLE :: DISABLE_USB1_54_MDIO_CLOCK [00:00] */
-#define BCHP_CLKGEN_USB1_TOP_INST_CLOCK_DISABLE_DISABLE_USB1_54_MDIO_CLOCK_MASK 0x00000001
-#define BCHP_CLKGEN_USB1_TOP_INST_CLOCK_DISABLE_DISABLE_USB1_54_MDIO_CLOCK_SHIFT 0
-#define BCHP_CLKGEN_USB1_TOP_INST_CLOCK_DISABLE_DISABLE_USB1_54_MDIO_CLOCK_DEFAULT 0x00000000
-
-/***************************************************************************
- *USB1_TOP_INST_CLOCK_DISABLE_STATUS - Clock Disable Status
- ***************************************************************************/
-/* CLKGEN :: USB1_TOP_INST_CLOCK_DISABLE_STATUS :: reserved0 [31:02] */
-#define BCHP_CLKGEN_USB1_TOP_INST_CLOCK_DISABLE_STATUS_reserved0_MASK 0xfffffffc
-#define BCHP_CLKGEN_USB1_TOP_INST_CLOCK_DISABLE_STATUS_reserved0_SHIFT 2
-
-/* CLKGEN :: USB1_TOP_INST_CLOCK_DISABLE_STATUS :: DISABLE_USB1_FREERUN_CLOCK_STATUS [01:01] */
-#define BCHP_CLKGEN_USB1_TOP_INST_CLOCK_DISABLE_STATUS_DISABLE_USB1_FREERUN_CLOCK_STATUS_MASK 0x00000002
-#define BCHP_CLKGEN_USB1_TOP_INST_CLOCK_DISABLE_STATUS_DISABLE_USB1_FREERUN_CLOCK_STATUS_SHIFT 1
-
-/* CLKGEN :: USB1_TOP_INST_CLOCK_DISABLE_STATUS :: DISABLE_USB1_54_MDIO_CLOCK_STATUS [00:00] */
-#define BCHP_CLKGEN_USB1_TOP_INST_CLOCK_DISABLE_STATUS_DISABLE_USB1_54_MDIO_CLOCK_STATUS_MASK 0x00000001
-#define BCHP_CLKGEN_USB1_TOP_INST_CLOCK_DISABLE_STATUS_DISABLE_USB1_54_MDIO_CLOCK_STATUS_SHIFT 0
-
-/***************************************************************************
- *USB1_TOP_INST_CLOCK_ENABLE - Usb1 top inst clock enable
- ***************************************************************************/
-/* CLKGEN :: USB1_TOP_INST_CLOCK_ENABLE :: reserved0 [31:03] */
-#define BCHP_CLKGEN_USB1_TOP_INST_CLOCK_ENABLE_reserved0_MASK 0xfffffff8
-#define BCHP_CLKGEN_USB1_TOP_INST_CLOCK_ENABLE_reserved0_SHIFT 3
-
-/* CLKGEN :: USB1_TOP_INST_CLOCK_ENABLE :: USB1_SCB_CLOCK_ENABLE [02:02] */
-#define BCHP_CLKGEN_USB1_TOP_INST_CLOCK_ENABLE_USB1_SCB_CLOCK_ENABLE_MASK 0x00000004
-#define BCHP_CLKGEN_USB1_TOP_INST_CLOCK_ENABLE_USB1_SCB_CLOCK_ENABLE_SHIFT 2
-#define BCHP_CLKGEN_USB1_TOP_INST_CLOCK_ENABLE_USB1_SCB_CLOCK_ENABLE_DEFAULT 0x00000001
-
-/* CLKGEN :: USB1_TOP_INST_CLOCK_ENABLE :: USB1_GISB_CLOCK_ENABLE [01:01] */
-#define BCHP_CLKGEN_USB1_TOP_INST_CLOCK_ENABLE_USB1_GISB_CLOCK_ENABLE_MASK 0x00000002
-#define BCHP_CLKGEN_USB1_TOP_INST_CLOCK_ENABLE_USB1_GISB_CLOCK_ENABLE_SHIFT 1
-#define BCHP_CLKGEN_USB1_TOP_INST_CLOCK_ENABLE_USB1_GISB_CLOCK_ENABLE_DEFAULT 0x00000001
-
-/* CLKGEN :: USB1_TOP_INST_CLOCK_ENABLE :: USB1_54_CLOCK_ENABLE [00:00] */
-#define BCHP_CLKGEN_USB1_TOP_INST_CLOCK_ENABLE_USB1_54_CLOCK_ENABLE_MASK 0x00000001
-#define BCHP_CLKGEN_USB1_TOP_INST_CLOCK_ENABLE_USB1_54_CLOCK_ENABLE_SHIFT 0
-#define BCHP_CLKGEN_USB1_TOP_INST_CLOCK_ENABLE_USB1_54_CLOCK_ENABLE_DEFAULT 0x00000001
-
-/***************************************************************************
- *USB1_TOP_INST_CLOCK_ENABLE_AHB - Usb1 top inst clock enable ahb
- ***************************************************************************/
-/* CLKGEN :: USB1_TOP_INST_CLOCK_ENABLE_AHB :: reserved0 [31:01] */
-#define BCHP_CLKGEN_USB1_TOP_INST_CLOCK_ENABLE_AHB_reserved0_MASK 0xfffffffe
-#define BCHP_CLKGEN_USB1_TOP_INST_CLOCK_ENABLE_AHB_reserved0_SHIFT 1
-
-/* CLKGEN :: USB1_TOP_INST_CLOCK_ENABLE_AHB :: USB1_108_CLOCK_ENABLE_AHB [00:00] */
-#define BCHP_CLKGEN_USB1_TOP_INST_CLOCK_ENABLE_AHB_USB1_108_CLOCK_ENABLE_AHB_MASK 0x00000001
-#define BCHP_CLKGEN_USB1_TOP_INST_CLOCK_ENABLE_AHB_USB1_108_CLOCK_ENABLE_AHB_SHIFT 0
-#define BCHP_CLKGEN_USB1_TOP_INST_CLOCK_ENABLE_AHB_USB1_108_CLOCK_ENABLE_AHB_DEFAULT 0x00000001
-
-/***************************************************************************
- *USB1_TOP_INST_CLOCK_ENABLE_AHB_STATUS - Clock Enable Status
- ***************************************************************************/
-/* CLKGEN :: USB1_TOP_INST_CLOCK_ENABLE_AHB_STATUS :: reserved0 [31:01] */
-#define BCHP_CLKGEN_USB1_TOP_INST_CLOCK_ENABLE_AHB_STATUS_reserved0_MASK 0xfffffffe
-#define BCHP_CLKGEN_USB1_TOP_INST_CLOCK_ENABLE_AHB_STATUS_reserved0_SHIFT 1
-
-/* CLKGEN :: USB1_TOP_INST_CLOCK_ENABLE_AHB_STATUS :: USB1_108_CLOCK_ENABLE_AHB_STATUS [00:00] */
-#define BCHP_CLKGEN_USB1_TOP_INST_CLOCK_ENABLE_AHB_STATUS_USB1_108_CLOCK_ENABLE_AHB_STATUS_MASK 0x00000001
-#define BCHP_CLKGEN_USB1_TOP_INST_CLOCK_ENABLE_AHB_STATUS_USB1_108_CLOCK_ENABLE_AHB_STATUS_SHIFT 0
-
-/***************************************************************************
- *USB1_TOP_INST_CLOCK_ENABLE_AXI - Usb1 top inst clock enable axi
- ***************************************************************************/
-/* CLKGEN :: USB1_TOP_INST_CLOCK_ENABLE_AXI :: reserved0 [31:01] */
-#define BCHP_CLKGEN_USB1_TOP_INST_CLOCK_ENABLE_AXI_reserved0_MASK 0xfffffffe
-#define BCHP_CLKGEN_USB1_TOP_INST_CLOCK_ENABLE_AXI_reserved0_SHIFT 1
-
-/* CLKGEN :: USB1_TOP_INST_CLOCK_ENABLE_AXI :: USB1_108_CLOCK_ENABLE_AXI [00:00] */
-#define BCHP_CLKGEN_USB1_TOP_INST_CLOCK_ENABLE_AXI_USB1_108_CLOCK_ENABLE_AXI_MASK 0x00000001
-#define BCHP_CLKGEN_USB1_TOP_INST_CLOCK_ENABLE_AXI_USB1_108_CLOCK_ENABLE_AXI_SHIFT 0
-#define BCHP_CLKGEN_USB1_TOP_INST_CLOCK_ENABLE_AXI_USB1_108_CLOCK_ENABLE_AXI_DEFAULT 0x00000001
-
-/***************************************************************************
- *USB1_TOP_INST_CLOCK_ENABLE_AXI_STATUS - Clock Enable Status
- ***************************************************************************/
-/* CLKGEN :: USB1_TOP_INST_CLOCK_ENABLE_AXI_STATUS :: reserved0 [31:01] */
-#define BCHP_CLKGEN_USB1_TOP_INST_CLOCK_ENABLE_AXI_STATUS_reserved0_MASK 0xfffffffe
-#define BCHP_CLKGEN_USB1_TOP_INST_CLOCK_ENABLE_AXI_STATUS_reserved0_SHIFT 1
-
-/* CLKGEN :: USB1_TOP_INST_CLOCK_ENABLE_AXI_STATUS :: USB1_108_CLOCK_ENABLE_AXI_STATUS [00:00] */
-#define BCHP_CLKGEN_USB1_TOP_INST_CLOCK_ENABLE_AXI_STATUS_USB1_108_CLOCK_ENABLE_AXI_STATUS_MASK 0x00000001
-#define BCHP_CLKGEN_USB1_TOP_INST_CLOCK_ENABLE_AXI_STATUS_USB1_108_CLOCK_ENABLE_AXI_STATUS_SHIFT 0
-
-/***************************************************************************
- *USB1_TOP_INST_CLOCK_ENABLE_STATUS - Clock Enable Status
- ***************************************************************************/
-/* CLKGEN :: USB1_TOP_INST_CLOCK_ENABLE_STATUS :: reserved0 [31:03] */
-#define BCHP_CLKGEN_USB1_TOP_INST_CLOCK_ENABLE_STATUS_reserved0_MASK 0xfffffff8
-#define BCHP_CLKGEN_USB1_TOP_INST_CLOCK_ENABLE_STATUS_reserved0_SHIFT 3
-
-/* CLKGEN :: USB1_TOP_INST_CLOCK_ENABLE_STATUS :: USB1_SCB_CLOCK_ENABLE_STATUS [02:02] */
-#define BCHP_CLKGEN_USB1_TOP_INST_CLOCK_ENABLE_STATUS_USB1_SCB_CLOCK_ENABLE_STATUS_MASK 0x00000004
-#define BCHP_CLKGEN_USB1_TOP_INST_CLOCK_ENABLE_STATUS_USB1_SCB_CLOCK_ENABLE_STATUS_SHIFT 2
-
-/* CLKGEN :: USB1_TOP_INST_CLOCK_ENABLE_STATUS :: USB1_GISB_CLOCK_ENABLE_STATUS [01:01] */
-#define BCHP_CLKGEN_USB1_TOP_INST_CLOCK_ENABLE_STATUS_USB1_GISB_CLOCK_ENABLE_STATUS_MASK 0x00000002
-#define BCHP_CLKGEN_USB1_TOP_INST_CLOCK_ENABLE_STATUS_USB1_GISB_CLOCK_ENABLE_STATUS_SHIFT 1
-
-/* CLKGEN :: USB1_TOP_INST_CLOCK_ENABLE_STATUS :: USB1_54_CLOCK_ENABLE_STATUS [00:00] */
-#define BCHP_CLKGEN_USB1_TOP_INST_CLOCK_ENABLE_STATUS_USB1_54_CLOCK_ENABLE_STATUS_MASK 0x00000001
-#define BCHP_CLKGEN_USB1_TOP_INST_CLOCK_ENABLE_STATUS_USB1_54_CLOCK_ENABLE_STATUS_SHIFT 0
-
-/***************************************************************************
- *USB1_TOP_INST_OBSERVE_CLOCK - Usb1 top inst observe clock
- ***************************************************************************/
-/* CLKGEN :: USB1_TOP_INST_OBSERVE_CLOCK :: reserved0 [31:06] */
-#define BCHP_CLKGEN_USB1_TOP_INST_OBSERVE_CLOCK_reserved0_MASK 0xffffffc0
-#define BCHP_CLKGEN_USB1_TOP_INST_OBSERVE_CLOCK_reserved0_SHIFT 6
-
-/* CLKGEN :: USB1_TOP_INST_OBSERVE_CLOCK :: USB1_ENABLE_OBSERVE_CLOCK [05:05] */
-#define BCHP_CLKGEN_USB1_TOP_INST_OBSERVE_CLOCK_USB1_ENABLE_OBSERVE_CLOCK_MASK 0x00000020
-#define BCHP_CLKGEN_USB1_TOP_INST_OBSERVE_CLOCK_USB1_ENABLE_OBSERVE_CLOCK_SHIFT 5
-#define BCHP_CLKGEN_USB1_TOP_INST_OBSERVE_CLOCK_USB1_ENABLE_OBSERVE_CLOCK_DEFAULT 0x00000000
-
-/* CLKGEN :: USB1_TOP_INST_OBSERVE_CLOCK :: USB1_ENABLE_DIVIDER_OBSERVE_CLOCK [04:04] */
-#define BCHP_CLKGEN_USB1_TOP_INST_OBSERVE_CLOCK_USB1_ENABLE_DIVIDER_OBSERVE_CLOCK_MASK 0x00000010
-#define BCHP_CLKGEN_USB1_TOP_INST_OBSERVE_CLOCK_USB1_ENABLE_DIVIDER_OBSERVE_CLOCK_SHIFT 4
-#define BCHP_CLKGEN_USB1_TOP_INST_OBSERVE_CLOCK_USB1_ENABLE_DIVIDER_OBSERVE_CLOCK_DEFAULT 0x00000000
-
-/* CLKGEN :: USB1_TOP_INST_OBSERVE_CLOCK :: USB1_CONTROL_OBSERVE_CLOCK [03:00] */
-#define BCHP_CLKGEN_USB1_TOP_INST_OBSERVE_CLOCK_USB1_CONTROL_OBSERVE_CLOCK_MASK 0x0000000f
-#define BCHP_CLKGEN_USB1_TOP_INST_OBSERVE_CLOCK_USB1_CONTROL_OBSERVE_CLOCK_SHIFT 0
-#define BCHP_CLKGEN_USB1_TOP_INST_OBSERVE_CLOCK_USB1_CONTROL_OBSERVE_CLOCK_DEFAULT 0x00000000
-
-/***************************************************************************
- *V3D_TOP_INST_CLOCK_ENABLE - V3d top inst clock enable
- ***************************************************************************/
-/* CLKGEN :: V3D_TOP_INST_CLOCK_ENABLE :: reserved0 [31:04] */
-#define BCHP_CLKGEN_V3D_TOP_INST_CLOCK_ENABLE_reserved0_MASK 0xfffffff0
-#define BCHP_CLKGEN_V3D_TOP_INST_CLOCK_ENABLE_reserved0_SHIFT 4
-
-/* CLKGEN :: V3D_TOP_INST_CLOCK_ENABLE :: V3D_SCB_CLOCK_ENABLE [03:03] */
-#define BCHP_CLKGEN_V3D_TOP_INST_CLOCK_ENABLE_V3D_SCB_CLOCK_ENABLE_MASK 0x00000008
-#define BCHP_CLKGEN_V3D_TOP_INST_CLOCK_ENABLE_V3D_SCB_CLOCK_ENABLE_SHIFT 3
-#define BCHP_CLKGEN_V3D_TOP_INST_CLOCK_ENABLE_V3D_SCB_CLOCK_ENABLE_DEFAULT 0x00000001
-
-/* CLKGEN :: V3D_TOP_INST_CLOCK_ENABLE :: V3D_GISB_CLOCK_ENABLE [02:02] */
-#define BCHP_CLKGEN_V3D_TOP_INST_CLOCK_ENABLE_V3D_GISB_CLOCK_ENABLE_MASK 0x00000004
-#define BCHP_CLKGEN_V3D_TOP_INST_CLOCK_ENABLE_V3D_GISB_CLOCK_ENABLE_SHIFT 2
-#define BCHP_CLKGEN_V3D_TOP_INST_CLOCK_ENABLE_V3D_GISB_CLOCK_ENABLE_DEFAULT 0x00000001
-
-/* CLKGEN :: V3D_TOP_INST_CLOCK_ENABLE :: V3D_CLOCK_ENABLE [01:01] */
-#define BCHP_CLKGEN_V3D_TOP_INST_CLOCK_ENABLE_V3D_CLOCK_ENABLE_MASK 0x00000002
-#define BCHP_CLKGEN_V3D_TOP_INST_CLOCK_ENABLE_V3D_CLOCK_ENABLE_SHIFT 1
-#define BCHP_CLKGEN_V3D_TOP_INST_CLOCK_ENABLE_V3D_CLOCK_ENABLE_DEFAULT 0x00000001
-
-/* CLKGEN :: V3D_TOP_INST_CLOCK_ENABLE :: V3D_54_CLOCK_ENABLE [00:00] */
-#define BCHP_CLKGEN_V3D_TOP_INST_CLOCK_ENABLE_V3D_54_CLOCK_ENABLE_MASK 0x00000001
-#define BCHP_CLKGEN_V3D_TOP_INST_CLOCK_ENABLE_V3D_54_CLOCK_ENABLE_SHIFT 0
-#define BCHP_CLKGEN_V3D_TOP_INST_CLOCK_ENABLE_V3D_54_CLOCK_ENABLE_DEFAULT 0x00000001
-
-/***************************************************************************
- *V3D_TOP_INST_CLOCK_ENABLE_STATUS - Clock Enable Status
- ***************************************************************************/
-/* CLKGEN :: V3D_TOP_INST_CLOCK_ENABLE_STATUS :: reserved0 [31:04] */
-#define BCHP_CLKGEN_V3D_TOP_INST_CLOCK_ENABLE_STATUS_reserved0_MASK 0xfffffff0
-#define BCHP_CLKGEN_V3D_TOP_INST_CLOCK_ENABLE_STATUS_reserved0_SHIFT 4
-
-/* CLKGEN :: V3D_TOP_INST_CLOCK_ENABLE_STATUS :: V3D_SCB_CLOCK_ENABLE_STATUS [03:03] */
-#define BCHP_CLKGEN_V3D_TOP_INST_CLOCK_ENABLE_STATUS_V3D_SCB_CLOCK_ENABLE_STATUS_MASK 0x00000008
-#define BCHP_CLKGEN_V3D_TOP_INST_CLOCK_ENABLE_STATUS_V3D_SCB_CLOCK_ENABLE_STATUS_SHIFT 3
-
-/* CLKGEN :: V3D_TOP_INST_CLOCK_ENABLE_STATUS :: V3D_GISB_CLOCK_ENABLE_STATUS [02:02] */
-#define BCHP_CLKGEN_V3D_TOP_INST_CLOCK_ENABLE_STATUS_V3D_GISB_CLOCK_ENABLE_STATUS_MASK 0x00000004
-#define BCHP_CLKGEN_V3D_TOP_INST_CLOCK_ENABLE_STATUS_V3D_GISB_CLOCK_ENABLE_STATUS_SHIFT 2
-
-/* CLKGEN :: V3D_TOP_INST_CLOCK_ENABLE_STATUS :: V3D_CLOCK_ENABLE_STATUS [01:01] */
-#define BCHP_CLKGEN_V3D_TOP_INST_CLOCK_ENABLE_STATUS_V3D_CLOCK_ENABLE_STATUS_MASK 0x00000002
-#define BCHP_CLKGEN_V3D_TOP_INST_CLOCK_ENABLE_STATUS_V3D_CLOCK_ENABLE_STATUS_SHIFT 1
-
-/* CLKGEN :: V3D_TOP_INST_CLOCK_ENABLE_STATUS :: V3D_54_CLOCK_ENABLE_STATUS [00:00] */
-#define BCHP_CLKGEN_V3D_TOP_INST_CLOCK_ENABLE_STATUS_V3D_54_CLOCK_ENABLE_STATUS_MASK 0x00000001
-#define BCHP_CLKGEN_V3D_TOP_INST_CLOCK_ENABLE_STATUS_V3D_54_CLOCK_ENABLE_STATUS_SHIFT 0
-
-/***************************************************************************
- *VEC_AIO_TOP_INST_CLOCK_DISABLE - Disable VEC_AIO_TOP_INST's clocks
- ***************************************************************************/
-/* CLKGEN :: VEC_AIO_TOP_INST_CLOCK_DISABLE :: reserved0 [31:02] */
-#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_DISABLE_reserved0_MASK 0xfffffffc
-#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_DISABLE_reserved0_SHIFT 2
-
-/* CLKGEN :: VEC_AIO_TOP_INST_CLOCK_DISABLE :: DISABLE_VEC_ITU656_0_CLOCK [01:01] */
-#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_DISABLE_DISABLE_VEC_ITU656_0_CLOCK_MASK 0x00000002
-#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_DISABLE_DISABLE_VEC_ITU656_0_CLOCK_SHIFT 1
-#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_DISABLE_DISABLE_VEC_ITU656_0_CLOCK_DEFAULT 0x00000000
-
-/* CLKGEN :: VEC_AIO_TOP_INST_CLOCK_DISABLE :: DISABLE_VEC_DACADC_CLOCK [00:00] */
-#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_DISABLE_DISABLE_VEC_DACADC_CLOCK_MASK 0x00000001
-#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_DISABLE_DISABLE_VEC_DACADC_CLOCK_SHIFT 0
-#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_DISABLE_DISABLE_VEC_DACADC_CLOCK_DEFAULT 0x00000000
-
-/***************************************************************************
- *VEC_AIO_TOP_INST_CLOCK_DISABLE_STATUS - Clock Disable Status
- ***************************************************************************/
-/* CLKGEN :: VEC_AIO_TOP_INST_CLOCK_DISABLE_STATUS :: reserved0 [31:02] */
-#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_DISABLE_STATUS_reserved0_MASK 0xfffffffc
-#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_DISABLE_STATUS_reserved0_SHIFT 2
-
-/* CLKGEN :: VEC_AIO_TOP_INST_CLOCK_DISABLE_STATUS :: DISABLE_VEC_ITU656_0_CLOCK_STATUS [01:01] */
-#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_DISABLE_STATUS_DISABLE_VEC_ITU656_0_CLOCK_STATUS_MASK 0x00000002
-#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_DISABLE_STATUS_DISABLE_VEC_ITU656_0_CLOCK_STATUS_SHIFT 1
-
-/* CLKGEN :: VEC_AIO_TOP_INST_CLOCK_DISABLE_STATUS :: DISABLE_VEC_DACADC_CLOCK_STATUS [00:00] */
-#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_DISABLE_STATUS_DISABLE_VEC_DACADC_CLOCK_STATUS_MASK 0x00000001
-#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_DISABLE_STATUS_DISABLE_VEC_DACADC_CLOCK_STATUS_SHIFT 0
-
-/***************************************************************************
- *VEC_AIO_TOP_INST_CLOCK_ENABLE - Vec aio top inst clock enable
- ***************************************************************************/
-/* CLKGEN :: VEC_AIO_TOP_INST_CLOCK_ENABLE :: reserved0 [31:01] */
-#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_reserved0_MASK 0xfffffffe
-#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_reserved0_SHIFT 1
-
-/* CLKGEN :: VEC_AIO_TOP_INST_CLOCK_ENABLE :: VEC_AIO_54_CLOCK_ENABLE [00:00] */
-#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC_AIO_54_CLOCK_ENABLE_MASK 0x00000001
-#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC_AIO_54_CLOCK_ENABLE_SHIFT 0
-#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC_AIO_54_CLOCK_ENABLE_DEFAULT 0x00000001
-
-/***************************************************************************
- *VEC_AIO_TOP_INST_CLOCK_ENABLE_AIO - Vec aio top inst clock enable aio
- ***************************************************************************/
-/* CLKGEN :: VEC_AIO_TOP_INST_CLOCK_ENABLE_AIO :: reserved0 [31:02] */
-#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_AIO_reserved0_MASK 0xfffffffc
-#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_AIO_reserved0_SHIFT 2
-
-/* CLKGEN :: VEC_AIO_TOP_INST_CLOCK_ENABLE_AIO :: AIO_ALTERNATE_SCB_CLOCK_ENABLE_AIO [01:01] */
-#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_AIO_AIO_ALTERNATE_SCB_CLOCK_ENABLE_AIO_MASK 0x00000002
-#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_AIO_AIO_ALTERNATE_SCB_CLOCK_ENABLE_AIO_SHIFT 1
-#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_AIO_AIO_ALTERNATE_SCB_CLOCK_ENABLE_AIO_DEFAULT 0x00000001
-
-/* CLKGEN :: VEC_AIO_TOP_INST_CLOCK_ENABLE_AIO :: AIO_ALTERNATE_108_CLOCK_ENABLE_AIO [00:00] */
-#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_AIO_AIO_ALTERNATE_108_CLOCK_ENABLE_AIO_MASK 0x00000001
-#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_AIO_AIO_ALTERNATE_108_CLOCK_ENABLE_AIO_SHIFT 0
-#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_AIO_AIO_ALTERNATE_108_CLOCK_ENABLE_AIO_DEFAULT 0x00000001
-
-/***************************************************************************
- *VEC_AIO_TOP_INST_CLOCK_ENABLE_AIO_STATUS - Clock Enable Status
- ***************************************************************************/
-/* CLKGEN :: VEC_AIO_TOP_INST_CLOCK_ENABLE_AIO_STATUS :: reserved0 [31:02] */
-#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_AIO_STATUS_reserved0_MASK 0xfffffffc
-#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_AIO_STATUS_reserved0_SHIFT 2
-
-/* CLKGEN :: VEC_AIO_TOP_INST_CLOCK_ENABLE_AIO_STATUS :: AIO_ALTERNATE_SCB_CLOCK_ENABLE_AIO_STATUS [01:01] */
-#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_AIO_STATUS_AIO_ALTERNATE_SCB_CLOCK_ENABLE_AIO_STATUS_MASK 0x00000002
-#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_AIO_STATUS_AIO_ALTERNATE_SCB_CLOCK_ENABLE_AIO_STATUS_SHIFT 1
-
-/* CLKGEN :: VEC_AIO_TOP_INST_CLOCK_ENABLE_AIO_STATUS :: AIO_ALTERNATE_108_CLOCK_ENABLE_AIO_STATUS [00:00] */
-#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_AIO_STATUS_AIO_ALTERNATE_108_CLOCK_ENABLE_AIO_STATUS_MASK 0x00000001
-#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_AIO_STATUS_AIO_ALTERNATE_108_CLOCK_ENABLE_AIO_STATUS_SHIFT 0
-
-/***************************************************************************
- *VEC_AIO_TOP_INST_CLOCK_ENABLE_STATUS - Clock Enable Status
- ***************************************************************************/
-/* CLKGEN :: VEC_AIO_TOP_INST_CLOCK_ENABLE_STATUS :: reserved0 [31:01] */
-#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_STATUS_reserved0_MASK 0xfffffffe
-#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_STATUS_reserved0_SHIFT 1
-
-/* CLKGEN :: VEC_AIO_TOP_INST_CLOCK_ENABLE_STATUS :: VEC_AIO_54_CLOCK_ENABLE_STATUS [00:00] */
-#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_STATUS_VEC_AIO_54_CLOCK_ENABLE_STATUS_MASK 0x00000001
-#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_STATUS_VEC_AIO_54_CLOCK_ENABLE_STATUS_SHIFT 0
-
-/***************************************************************************
- *VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC - Vec aio top inst clock enable vec
- ***************************************************************************/
-/* CLKGEN :: VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC :: reserved0 [31:05] */
-#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC_reserved0_MASK 0xffffffe0
-#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC_reserved0_SHIFT 5
-
-/* CLKGEN :: VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC :: VEC_SCB_CLOCK_ENABLE_VEC [04:04] */
-#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC_VEC_SCB_CLOCK_ENABLE_VEC_MASK 0x00000010
-#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC_VEC_SCB_CLOCK_ENABLE_VEC_SHIFT 4
-#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC_VEC_SCB_CLOCK_ENABLE_VEC_DEFAULT 0x00000001
-
-/* CLKGEN :: VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC :: VEC_GISB_CLOCK_ENABLE_VEC [03:03] */
-#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC_VEC_GISB_CLOCK_ENABLE_VEC_MASK 0x00000008
-#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC_VEC_GISB_CLOCK_ENABLE_VEC_SHIFT 3
-#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC_VEC_GISB_CLOCK_ENABLE_VEC_DEFAULT 0x00000001
-
-/* CLKGEN :: VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC :: VEC_BVB_324_CLOCK_ENABLE_VEC [02:02] */
-#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC_VEC_BVB_324_CLOCK_ENABLE_VEC_MASK 0x00000004
-#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC_VEC_BVB_324_CLOCK_ENABLE_VEC_SHIFT 2
-#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC_VEC_BVB_324_CLOCK_ENABLE_VEC_DEFAULT 0x00000001
-
-/* CLKGEN :: VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC :: VEC_108_CLOCK_ENABLE_VEC [01:01] */
-#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC_VEC_108_CLOCK_ENABLE_VEC_MASK 0x00000002
-#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC_VEC_108_CLOCK_ENABLE_VEC_SHIFT 1
-#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC_VEC_108_CLOCK_ENABLE_VEC_DEFAULT 0x00000001
-
-/* CLKGEN :: VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC :: QDAC_GISB_CLOCK_ENABLE_VEC [00:00] */
-#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC_QDAC_GISB_CLOCK_ENABLE_VEC_MASK 0x00000001
-#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC_QDAC_GISB_CLOCK_ENABLE_VEC_SHIFT 0
-#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC_QDAC_GISB_CLOCK_ENABLE_VEC_DEFAULT 0x00000001
-
-/***************************************************************************
- *VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC_QDAC_INTF - Vec aio top inst clock enable vec qdac intf
- ***************************************************************************/
-/* CLKGEN :: VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC_QDAC_INTF :: reserved0 [31:01] */
-#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC_QDAC_INTF_reserved0_MASK 0xfffffffe
-#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC_QDAC_INTF_reserved0_SHIFT 1
-
-/* CLKGEN :: VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC_QDAC_INTF :: VEC_GISB_CLOCK_ENABLE_VEC_QDAC_INTF [00:00] */
-#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC_QDAC_INTF_VEC_GISB_CLOCK_ENABLE_VEC_QDAC_INTF_MASK 0x00000001
-#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC_QDAC_INTF_VEC_GISB_CLOCK_ENABLE_VEC_QDAC_INTF_SHIFT 0
-#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC_QDAC_INTF_VEC_GISB_CLOCK_ENABLE_VEC_QDAC_INTF_DEFAULT 0x00000001
-
-/***************************************************************************
- *VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC_QDAC_INTF_STATUS - Clock Enable Status
- ***************************************************************************/
-/* CLKGEN :: VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC_QDAC_INTF_STATUS :: reserved0 [31:01] */
-#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC_QDAC_INTF_STATUS_reserved0_MASK 0xfffffffe
-#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC_QDAC_INTF_STATUS_reserved0_SHIFT 1
-
-/* CLKGEN :: VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC_QDAC_INTF_STATUS :: VEC_GISB_CLOCK_ENABLE_VEC_QDAC_INTF_STATUS [00:00] */
-#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC_QDAC_INTF_STATUS_VEC_GISB_CLOCK_ENABLE_VEC_QDAC_INTF_STATUS_MASK 0x00000001
-#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC_QDAC_INTF_STATUS_VEC_GISB_CLOCK_ENABLE_VEC_QDAC_INTF_STATUS_SHIFT 0
-
-/***************************************************************************
- *VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC_STATUS - Clock Enable Status
- ***************************************************************************/
-/* CLKGEN :: VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC_STATUS :: reserved0 [31:05] */
-#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC_STATUS_reserved0_MASK 0xffffffe0
-#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC_STATUS_reserved0_SHIFT 5
-
-/* CLKGEN :: VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC_STATUS :: VEC_SCB_CLOCK_ENABLE_VEC_STATUS [04:04] */
-#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC_STATUS_VEC_SCB_CLOCK_ENABLE_VEC_STATUS_MASK 0x00000010
-#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC_STATUS_VEC_SCB_CLOCK_ENABLE_VEC_STATUS_SHIFT 4
-
-/* CLKGEN :: VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC_STATUS :: VEC_GISB_CLOCK_ENABLE_VEC_STATUS [03:03] */
-#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC_STATUS_VEC_GISB_CLOCK_ENABLE_VEC_STATUS_MASK 0x00000008
-#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC_STATUS_VEC_GISB_CLOCK_ENABLE_VEC_STATUS_SHIFT 3
-
-/* CLKGEN :: VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC_STATUS :: VEC_BVB_324_CLOCK_ENABLE_VEC_STATUS [02:02] */
-#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC_STATUS_VEC_BVB_324_CLOCK_ENABLE_VEC_STATUS_MASK 0x00000004
-#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC_STATUS_VEC_BVB_324_CLOCK_ENABLE_VEC_STATUS_SHIFT 2
-
-/* CLKGEN :: VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC_STATUS :: VEC_108_CLOCK_ENABLE_VEC_STATUS [01:01] */
-#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC_STATUS_VEC_108_CLOCK_ENABLE_VEC_STATUS_MASK 0x00000002
-#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC_STATUS_VEC_108_CLOCK_ENABLE_VEC_STATUS_SHIFT 1
-
-/* CLKGEN :: VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC_STATUS :: QDAC_GISB_CLOCK_ENABLE_VEC_STATUS [00:00] */
-#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC_STATUS_QDAC_GISB_CLOCK_ENABLE_VEC_STATUS_MASK 0x00000001
-#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC_STATUS_QDAC_GISB_CLOCK_ENABLE_VEC_STATUS_SHIFT 0
-
-/***************************************************************************
- *VEC_AIO_TOP_INST_ENABLE - Vec aio top inst enable
- ***************************************************************************/
-/* CLKGEN :: VEC_AIO_TOP_INST_ENABLE :: reserved0 [31:01] */
-#define BCHP_CLKGEN_VEC_AIO_TOP_INST_ENABLE_reserved0_MASK 0xfffffffe
-#define BCHP_CLKGEN_VEC_AIO_TOP_INST_ENABLE_reserved0_SHIFT 1
-
-/* CLKGEN :: VEC_AIO_TOP_INST_ENABLE :: VEC_CLK_648_ENABLE [00:00] */
-#define BCHP_CLKGEN_VEC_AIO_TOP_INST_ENABLE_VEC_CLK_648_ENABLE_MASK 0x00000001
-#define BCHP_CLKGEN_VEC_AIO_TOP_INST_ENABLE_VEC_CLK_648_ENABLE_SHIFT 0
-#define BCHP_CLKGEN_VEC_AIO_TOP_INST_ENABLE_VEC_CLK_648_ENABLE_DEFAULT 0x00000001
-
-/***************************************************************************
- *VEC_AIO_TOP_INST_OBSERVE_CLOCK - Vec aio top inst observe clock
- ***************************************************************************/
-/* CLKGEN :: VEC_AIO_TOP_INST_OBSERVE_CLOCK :: reserved0 [31:12] */
-#define BCHP_CLKGEN_VEC_AIO_TOP_INST_OBSERVE_CLOCK_reserved0_MASK 0xfffff000
-#define BCHP_CLKGEN_VEC_AIO_TOP_INST_OBSERVE_CLOCK_reserved0_SHIFT 12
-
-/* CLKGEN :: VEC_AIO_TOP_INST_OBSERVE_CLOCK :: VEC_ENABLE_OBSERVE_CLOCK [11:11] */
-#define BCHP_CLKGEN_VEC_AIO_TOP_INST_OBSERVE_CLOCK_VEC_ENABLE_OBSERVE_CLOCK_MASK 0x00000800
-#define BCHP_CLKGEN_VEC_AIO_TOP_INST_OBSERVE_CLOCK_VEC_ENABLE_OBSERVE_CLOCK_SHIFT 11
-#define BCHP_CLKGEN_VEC_AIO_TOP_INST_OBSERVE_CLOCK_VEC_ENABLE_OBSERVE_CLOCK_DEFAULT 0x00000000
-
-/* CLKGEN :: VEC_AIO_TOP_INST_OBSERVE_CLOCK :: VEC_ENABLE_DIVIDER_OBSERVE_CLOCK [10:10] */
-#define BCHP_CLKGEN_VEC_AIO_TOP_INST_OBSERVE_CLOCK_VEC_ENABLE_DIVIDER_OBSERVE_CLOCK_MASK 0x00000400
-#define BCHP_CLKGEN_VEC_AIO_TOP_INST_OBSERVE_CLOCK_VEC_ENABLE_DIVIDER_OBSERVE_CLOCK_SHIFT 10
-#define BCHP_CLKGEN_VEC_AIO_TOP_INST_OBSERVE_CLOCK_VEC_ENABLE_DIVIDER_OBSERVE_CLOCK_DEFAULT 0x00000000
-
-/* CLKGEN :: VEC_AIO_TOP_INST_OBSERVE_CLOCK :: VEC_CONTROL_OBSERVE_CLOCK [09:06] */
-#define BCHP_CLKGEN_VEC_AIO_TOP_INST_OBSERVE_CLOCK_VEC_CONTROL_OBSERVE_CLOCK_MASK 0x000003c0
-#define BCHP_CLKGEN_VEC_AIO_TOP_INST_OBSERVE_CLOCK_VEC_CONTROL_OBSERVE_CLOCK_SHIFT 6
-#define BCHP_CLKGEN_VEC_AIO_TOP_INST_OBSERVE_CLOCK_VEC_CONTROL_OBSERVE_CLOCK_DEFAULT 0x00000000
-
-/* CLKGEN :: VEC_AIO_TOP_INST_OBSERVE_CLOCK :: AIO_ENABLE_OBSERVE_CLOCK [05:05] */
-#define BCHP_CLKGEN_VEC_AIO_TOP_INST_OBSERVE_CLOCK_AIO_ENABLE_OBSERVE_CLOCK_MASK 0x00000020
-#define BCHP_CLKGEN_VEC_AIO_TOP_INST_OBSERVE_CLOCK_AIO_ENABLE_OBSERVE_CLOCK_SHIFT 5
-#define BCHP_CLKGEN_VEC_AIO_TOP_INST_OBSERVE_CLOCK_AIO_ENABLE_OBSERVE_CLOCK_DEFAULT 0x00000000
-
-/* CLKGEN :: VEC_AIO_TOP_INST_OBSERVE_CLOCK :: AIO_ENABLE_DIVIDER_OBSERVE_CLOCK [04:04] */
-#define BCHP_CLKGEN_VEC_AIO_TOP_INST_OBSERVE_CLOCK_AIO_ENABLE_DIVIDER_OBSERVE_CLOCK_MASK 0x00000010
-#define BCHP_CLKGEN_VEC_AIO_TOP_INST_OBSERVE_CLOCK_AIO_ENABLE_DIVIDER_OBSERVE_CLOCK_SHIFT 4
-#define BCHP_CLKGEN_VEC_AIO_TOP_INST_OBSERVE_CLOCK_AIO_ENABLE_DIVIDER_OBSERVE_CLOCK_DEFAULT 0x00000000
-
-/* CLKGEN :: VEC_AIO_TOP_INST_OBSERVE_CLOCK :: AIO_CONTROL_OBSERVE_CLOCK [03:00] */
-#define BCHP_CLKGEN_VEC_AIO_TOP_INST_OBSERVE_CLOCK_AIO_CONTROL_OBSERVE_CLOCK_MASK 0x0000000f
-#define BCHP_CLKGEN_VEC_AIO_TOP_INST_OBSERVE_CLOCK_AIO_CONTROL_OBSERVE_CLOCK_SHIFT 0
-#define BCHP_CLKGEN_VEC_AIO_TOP_INST_OBSERVE_CLOCK_AIO_CONTROL_OBSERVE_CLOCK_DEFAULT 0x00000000
-
-/***************************************************************************
- *VICE2_0_INST_CLOCK_ENABLE - Vice2 0 inst clock enable
- ***************************************************************************/
-/* CLKGEN :: VICE2_0_INST_CLOCK_ENABLE :: reserved0 [31:06] */
-#define BCHP_CLKGEN_VICE2_0_INST_CLOCK_ENABLE_reserved0_MASK 0xffffffc0
-#define BCHP_CLKGEN_VICE2_0_INST_CLOCK_ENABLE_reserved0_SHIFT 6
-
-/* CLKGEN :: VICE2_0_INST_CLOCK_ENABLE :: VICE2_0_SCB_CLOCK_ENABLE [05:05] */
-#define BCHP_CLKGEN_VICE2_0_INST_CLOCK_ENABLE_VICE2_0_SCB_CLOCK_ENABLE_MASK 0x00000020
-#define BCHP_CLKGEN_VICE2_0_INST_CLOCK_ENABLE_VICE2_0_SCB_CLOCK_ENABLE_SHIFT 5
-#define BCHP_CLKGEN_VICE2_0_INST_CLOCK_ENABLE_VICE2_0_SCB_CLOCK_ENABLE_DEFAULT 0x00000001
-
-/* CLKGEN :: VICE2_0_INST_CLOCK_ENABLE :: VICE2_0_GISB_CLOCK_ENABLE [04:04] */
-#define BCHP_CLKGEN_VICE2_0_INST_CLOCK_ENABLE_VICE2_0_GISB_CLOCK_ENABLE_MASK 0x00000010
-#define BCHP_CLKGEN_VICE2_0_INST_CLOCK_ENABLE_VICE2_0_GISB_CLOCK_ENABLE_SHIFT 4
-#define BCHP_CLKGEN_VICE2_0_INST_CLOCK_ENABLE_VICE2_0_GISB_CLOCK_ENABLE_DEFAULT 0x00000001
-
-/* CLKGEN :: VICE2_0_INST_CLOCK_ENABLE :: VICE2_0_GISB_ALTERNATE_CLOCK_ENABLE [03:03] */
-#define BCHP_CLKGEN_VICE2_0_INST_CLOCK_ENABLE_VICE2_0_GISB_ALTERNATE_CLOCK_ENABLE_MASK 0x00000008
-#define BCHP_CLKGEN_VICE2_0_INST_CLOCK_ENABLE_VICE2_0_GISB_ALTERNATE_CLOCK_ENABLE_SHIFT 3
-#define BCHP_CLKGEN_VICE2_0_INST_CLOCK_ENABLE_VICE2_0_GISB_ALTERNATE_CLOCK_ENABLE_DEFAULT 0x00000001
-
-/* CLKGEN :: VICE2_0_INST_CLOCK_ENABLE :: VICE2_0_CORE_CLOCK_ENABLE [02:02] */
-#define BCHP_CLKGEN_VICE2_0_INST_CLOCK_ENABLE_VICE2_0_CORE_CLOCK_ENABLE_MASK 0x00000004
-#define BCHP_CLKGEN_VICE2_0_INST_CLOCK_ENABLE_VICE2_0_CORE_CLOCK_ENABLE_SHIFT 2
-#define BCHP_CLKGEN_VICE2_0_INST_CLOCK_ENABLE_VICE2_0_CORE_CLOCK_ENABLE_DEFAULT 0x00000001
-
-/* CLKGEN :: VICE2_0_INST_CLOCK_ENABLE :: VICE2_0_54_CLOCK_ENABLE [01:01] */
-#define BCHP_CLKGEN_VICE2_0_INST_CLOCK_ENABLE_VICE2_0_54_CLOCK_ENABLE_MASK 0x00000002
-#define BCHP_CLKGEN_VICE2_0_INST_CLOCK_ENABLE_VICE2_0_54_CLOCK_ENABLE_SHIFT 1
-#define BCHP_CLKGEN_VICE2_0_INST_CLOCK_ENABLE_VICE2_0_54_CLOCK_ENABLE_DEFAULT 0x00000001
-
-/* CLKGEN :: VICE2_0_INST_CLOCK_ENABLE :: VICE2_0_108_CLOCK_ENABLE [00:00] */
-#define BCHP_CLKGEN_VICE2_0_INST_CLOCK_ENABLE_VICE2_0_108_CLOCK_ENABLE_MASK 0x00000001
-#define BCHP_CLKGEN_VICE2_0_INST_CLOCK_ENABLE_VICE2_0_108_CLOCK_ENABLE_SHIFT 0
-#define BCHP_CLKGEN_VICE2_0_INST_CLOCK_ENABLE_VICE2_0_108_CLOCK_ENABLE_DEFAULT 0x00000001
-
-/***************************************************************************
- *VICE2_0_INST_CLOCK_ENABLE_STATUS - Clock Enable Status
- ***************************************************************************/
-/* CLKGEN :: VICE2_0_INST_CLOCK_ENABLE_STATUS :: reserved0 [31:06] */
-#define BCHP_CLKGEN_VICE2_0_INST_CLOCK_ENABLE_STATUS_reserved0_MASK 0xffffffc0
-#define BCHP_CLKGEN_VICE2_0_INST_CLOCK_ENABLE_STATUS_reserved0_SHIFT 6
-
-/* CLKGEN :: VICE2_0_INST_CLOCK_ENABLE_STATUS :: VICE2_0_SCB_CLOCK_ENABLE_STATUS [05:05] */
-#define BCHP_CLKGEN_VICE2_0_INST_CLOCK_ENABLE_STATUS_VICE2_0_SCB_CLOCK_ENABLE_STATUS_MASK 0x00000020
-#define BCHP_CLKGEN_VICE2_0_INST_CLOCK_ENABLE_STATUS_VICE2_0_SCB_CLOCK_ENABLE_STATUS_SHIFT 5
-
-/* CLKGEN :: VICE2_0_INST_CLOCK_ENABLE_STATUS :: VICE2_0_GISB_CLOCK_ENABLE_STATUS [04:04] */
-#define BCHP_CLKGEN_VICE2_0_INST_CLOCK_ENABLE_STATUS_VICE2_0_GISB_CLOCK_ENABLE_STATUS_MASK 0x00000010
-#define BCHP_CLKGEN_VICE2_0_INST_CLOCK_ENABLE_STATUS_VICE2_0_GISB_CLOCK_ENABLE_STATUS_SHIFT 4
-
-/* CLKGEN :: VICE2_0_INST_CLOCK_ENABLE_STATUS :: VICE2_0_GISB_ALTERNATE_CLOCK_ENABLE_STATUS [03:03] */
-#define BCHP_CLKGEN_VICE2_0_INST_CLOCK_ENABLE_STATUS_VICE2_0_GISB_ALTERNATE_CLOCK_ENABLE_STATUS_MASK 0x00000008
-#define BCHP_CLKGEN_VICE2_0_INST_CLOCK_ENABLE_STATUS_VICE2_0_GISB_ALTERNATE_CLOCK_ENABLE_STATUS_SHIFT 3
-
-/* CLKGEN :: VICE2_0_INST_CLOCK_ENABLE_STATUS :: VICE2_0_CORE_CLOCK_ENABLE_STATUS [02:02] */
-#define BCHP_CLKGEN_VICE2_0_INST_CLOCK_ENABLE_STATUS_VICE2_0_CORE_CLOCK_ENABLE_STATUS_MASK 0x00000004
-#define BCHP_CLKGEN_VICE2_0_INST_CLOCK_ENABLE_STATUS_VICE2_0_CORE_CLOCK_ENABLE_STATUS_SHIFT 2
-
-/* CLKGEN :: VICE2_0_INST_CLOCK_ENABLE_STATUS :: VICE2_0_54_CLOCK_ENABLE_STATUS [01:01] */
-#define BCHP_CLKGEN_VICE2_0_INST_CLOCK_ENABLE_STATUS_VICE2_0_54_CLOCK_ENABLE_STATUS_MASK 0x00000002
-#define BCHP_CLKGEN_VICE2_0_INST_CLOCK_ENABLE_STATUS_VICE2_0_54_CLOCK_ENABLE_STATUS_SHIFT 1
-
-/* CLKGEN :: VICE2_0_INST_CLOCK_ENABLE_STATUS :: VICE2_0_108_CLOCK_ENABLE_STATUS [00:00] */
-#define BCHP_CLKGEN_VICE2_0_INST_CLOCK_ENABLE_STATUS_VICE2_0_108_CLOCK_ENABLE_STATUS_MASK 0x00000001
-#define BCHP_CLKGEN_VICE2_0_INST_CLOCK_ENABLE_STATUS_VICE2_0_108_CLOCK_ENABLE_STATUS_SHIFT 0
-
-/***************************************************************************
- *BSPI_CLOCK_SELECT - spi clock control
- ***************************************************************************/
-/* CLKGEN :: BSPI_CLOCK_SELECT :: reserved0 [31:03] */
-#define BCHP_CLKGEN_BSPI_CLOCK_SELECT_reserved0_MASK 0xfffffff8
-#define BCHP_CLKGEN_BSPI_CLOCK_SELECT_reserved0_SHIFT 3
-
-/* CLKGEN :: BSPI_CLOCK_SELECT :: SPI_CLOCK_FREQ_SEL [02:01] */
-#define BCHP_CLKGEN_BSPI_CLOCK_SELECT_SPI_CLOCK_FREQ_SEL_MASK 0x00000006
-#define BCHP_CLKGEN_BSPI_CLOCK_SELECT_SPI_CLOCK_FREQ_SEL_SHIFT 1
-#define BCHP_CLKGEN_BSPI_CLOCK_SELECT_SPI_CLOCK_FREQ_SEL_DEFAULT 0x00000000
-
-/* CLKGEN :: BSPI_CLOCK_SELECT :: SPI_CLOCK_OVERRIDE_STRAP [00:00] */
-#define BCHP_CLKGEN_BSPI_CLOCK_SELECT_SPI_CLOCK_OVERRIDE_STRAP_MASK 0x00000001
-#define BCHP_CLKGEN_BSPI_CLOCK_SELECT_SPI_CLOCK_OVERRIDE_STRAP_SHIFT 0
-#define BCHP_CLKGEN_BSPI_CLOCK_SELECT_SPI_CLOCK_OVERRIDE_STRAP_DEFAULT 0x00000000
-
-/***************************************************************************
- *USBPHY_REF_CLOCK_BYPASS - bypass USBPHY reference clocks
- ***************************************************************************/
-/* CLKGEN :: USBPHY_REF_CLOCK_BYPASS :: reserved0 [31:03] */
-#define BCHP_CLKGEN_USBPHY_REF_CLOCK_BYPASS_reserved0_MASK 0xfffffff8
-#define BCHP_CLKGEN_USBPHY_REF_CLOCK_BYPASS_reserved0_SHIFT 3
-
-/* CLKGEN :: USBPHY_REF_CLOCK_BYPASS :: BYP_USB1_USB20_60MHZ_REFCLK [02:02] */
-#define BCHP_CLKGEN_USBPHY_REF_CLOCK_BYPASS_BYP_USB1_USB20_60MHZ_REFCLK_MASK 0x00000004
-#define BCHP_CLKGEN_USBPHY_REF_CLOCK_BYPASS_BYP_USB1_USB20_60MHZ_REFCLK_SHIFT 2
-#define BCHP_CLKGEN_USBPHY_REF_CLOCK_BYPASS_BYP_USB1_USB20_60MHZ_REFCLK_DEFAULT 0x00000000
-
-/* CLKGEN :: USBPHY_REF_CLOCK_BYPASS :: BYP_USB0_USB20_60MHZ_REFCLK [01:01] */
-#define BCHP_CLKGEN_USBPHY_REF_CLOCK_BYPASS_BYP_USB0_USB20_60MHZ_REFCLK_MASK 0x00000002
-#define BCHP_CLKGEN_USBPHY_REF_CLOCK_BYPASS_BYP_USB0_USB20_60MHZ_REFCLK_SHIFT 1
-#define BCHP_CLKGEN_USBPHY_REF_CLOCK_BYPASS_BYP_USB0_USB20_60MHZ_REFCLK_DEFAULT 0x00000000
-
-/* CLKGEN :: USBPHY_REF_CLOCK_BYPASS :: BYP_USB0_USB30_50MHZ_REFCLK [00:00] */
-#define BCHP_CLKGEN_USBPHY_REF_CLOCK_BYPASS_BYP_USB0_USB30_50MHZ_REFCLK_MASK 0x00000001
-#define BCHP_CLKGEN_USBPHY_REF_CLOCK_BYPASS_BYP_USB0_USB30_50MHZ_REFCLK_SHIFT 0
-#define BCHP_CLKGEN_USBPHY_REF_CLOCK_BYPASS_BYP_USB0_USB30_50MHZ_REFCLK_DEFAULT 0x00000000
-
-/***************************************************************************
- *EPHY_REF_CLOCK_BYPASS - bypass EPHY reference clocks
- ***************************************************************************/
-/* CLKGEN :: EPHY_REF_CLOCK_BYPASS :: reserved0 [31:02] */
-#define BCHP_CLKGEN_EPHY_REF_CLOCK_BYPASS_reserved0_MASK 0xfffffffc
-#define BCHP_CLKGEN_EPHY_REF_CLOCK_BYPASS_reserved0_SHIFT 2
-
-/* CLKGEN :: EPHY_REF_CLOCK_BYPASS :: EPHY_REF_CLK_SEL [01:01] */
-#define BCHP_CLKGEN_EPHY_REF_CLOCK_BYPASS_EPHY_REF_CLK_SEL_MASK 0x00000002
-#define BCHP_CLKGEN_EPHY_REF_CLOCK_BYPASS_EPHY_REF_CLK_SEL_SHIFT 1
-#define BCHP_CLKGEN_EPHY_REF_CLOCK_BYPASS_EPHY_REF_CLK_SEL_DEFAULT 0x00000000
-
-/* CLKGEN :: EPHY_REF_CLOCK_BYPASS :: BYP_EN_EPHY_REFCLK [00:00] */
-#define BCHP_CLKGEN_EPHY_REF_CLOCK_BYPASS_BYP_EN_EPHY_REFCLK_MASK 0x00000001
-#define BCHP_CLKGEN_EPHY_REF_CLOCK_BYPASS_BYP_EN_EPHY_REFCLK_SHIFT 0
-#define BCHP_CLKGEN_EPHY_REF_CLOCK_BYPASS_BYP_EN_EPHY_REFCLK_DEFAULT 0x00000000
-
-/***************************************************************************
- *PLL_AUDIO0 - Ana pll4 1p8v ts28hpm 6mx 2mr fc x e pllaudio0 inst pll audio0
- ***************************************************************************/
-/* CLKGEN :: PLL_AUDIO0 :: reserved0 [31:01] */
-#define BCHP_CLKGEN_PLL_AUDIO0_reserved0_MASK 0xfffffffe
-#define BCHP_CLKGEN_PLL_AUDIO0_reserved0_SHIFT 1
-
-/* CLKGEN :: PLL_AUDIO0 :: PM_PLL_LDO_POWERUP_PLL_AUDIO0 [00:00] */
-#define BCHP_CLKGEN_PLL_AUDIO0_PM_PLL_LDO_POWERUP_PLL_AUDIO0_MASK 0x00000001
-#define BCHP_CLKGEN_PLL_AUDIO0_PM_PLL_LDO_POWERUP_PLL_AUDIO0_SHIFT 0
-#define BCHP_CLKGEN_PLL_AUDIO0_PM_PLL_LDO_POWERUP_PLL_AUDIO0_DEFAULT 0x00000000
-
-/***************************************************************************
- *PLL_AUDIO1 - Ana pll4 rfmod 1p8v ts28hpm 6mx 2mr np x e pllaudio1 inst pll audio1
- ***************************************************************************/
-/* CLKGEN :: PLL_AUDIO1 :: reserved0 [31:01] */
-#define BCHP_CLKGEN_PLL_AUDIO1_reserved0_MASK 0xfffffffe
-#define BCHP_CLKGEN_PLL_AUDIO1_reserved0_SHIFT 1
-
-/* CLKGEN :: PLL_AUDIO1 :: PM_PLL_LDO_POWERUP_PLL_AUDIO1 [00:00] */
-#define BCHP_CLKGEN_PLL_AUDIO1_PM_PLL_LDO_POWERUP_PLL_AUDIO1_MASK 0x00000001
-#define BCHP_CLKGEN_PLL_AUDIO1_PM_PLL_LDO_POWERUP_PLL_AUDIO1_SHIFT 0
-#define BCHP_CLKGEN_PLL_AUDIO1_PM_PLL_LDO_POWERUP_PLL_AUDIO1_DEFAULT 0x00000000
-
-#endif /* #ifndef BCHP_CLKGEN_H__ */
-
-/* End of File */
diff --git a/include/linux/brcmstb/7439a0/bchp_common.h b/include/linux/brcmstb/7439a0/bchp_common.h
deleted file mode 100644
index d74ae01..0000000
--- a/include/linux/brcmstb/7439a0/bchp_common.h
+++ /dev/null
@@ -1,3483 +0,0 @@
-/***************************************************************************
- * Copyright (c) 1999-2014, Broadcom Corporation
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
- *
- * Module Description:
- * DO NOT EDIT THIS FILE DIRECTLY
- *
- * This module was generated magically with RDB from a source description
- * file. You must edit the source file for changes to be made to this file.
- *
- *
- * Date: Generated on Wed Sep 3 14:30:27 2014
- * Full Compile MD5 Checksum edbc259d5ef948d04693ec04bc4d44b4
- * (minus title and desc)
- * MD5 Checksum de2524c7728bb833dc65ac44b70daaa5
- *
- * Compiled with: RDB Utility combo_header.pl
- * RDB Parser 3.0
- * unknown unknown
- * Perl Interpreter 5.008005
- * Operating System linux
- *
- * Revision History:
- *
- * $brcm_Log: $
- *
- ***************************************************************************/
-
-#ifndef BCHP_COMMON_H__
-#define BCHP_COMMON_H__
-
-/**
- * m = memory, c = core, r = register, f = field, d = data.
- */
-#if !defined(GET_FIELD) && !defined(SET_FIELD)
-#define BRCM_MASK(c,r,f) c##_##r##_##f##_MASK
-#define BRCM_SHIFT(c,r,f) c##_##r##_##f##_SHIFT
-
-#define GET_FIELD(m,c,r,f) \
-((((m) & BRCM_MASK(c,r,f)) >> BRCM_SHIFT(c,r,f)))
-
-#define SET_FIELD(m,c,r,f,d) \
-((m) = (((m) & ~BRCM_MASK(c,r,f)) | ((((d)) << BRCM_SHIFT(c,r,f)) & BRCM_MASK(c,r,f))))
-
-#define SET_TYPE_FIELD(m,c,r,f,d) SET_FIELD(m,c,r,f,c##_##d)
-#define SET_NAME_FIELD(m,c,r,f,d) SET_FIELD(m,c,r,f,c##_##r##_##f##_##d)
-#define SET_VALUE_FIELD(m,c,r,f,d) SET_FIELD(m,c,r,f,d)
-
-#endif /* GET & SET */
-
-/***************************************************************************
- *BCM7439_A0
- ***************************************************************************/
-#define BCHP_PHYSICAL_OFFSET 0xf0000000
-#define BCHP_REGISTER_START 0x00100000 /* HEVD_OL_CPU_REGS_0 is first */
-#define BCHP_REGISTER_END 0x00fffda0 /* MOCA_HOSTMISC is last */
-#define BCHP_REGISTER_SIZE 0x003bff68 /* Number of registers */
-
-/****************************************************************************
- * Core instance register start address.
- ***************************************************************************/
-#define BCHP_HEVD_OL_CPU_REGS_0_REG_START 0x00100000
-#define BCHP_HEVD_OL_CPU_REGS_0_REG_END 0x00100108
-#define BCHP_HEVD_OL_CPU_DMA_0_REG_START 0x00100400
-#define BCHP_HEVD_OL_CPU_DMA_0_REG_END 0x00100440
-#define BCHP_HEVD_OL_CPU_DEBUG_0_REG_START 0x00100800
-#define BCHP_HEVD_OL_CPU_DEBUG_0_REG_END 0x00100ffc
-#define BCHP_HEVD_OL_SINT_0_REG_START 0x00101000
-#define BCHP_HEVD_OL_SINT_0_REG_END 0x00101028
-#define BCHP_HEVD_OL_LDST_0_REG_START 0x00108000
-#define BCHP_HEVD_OL_LDST_0_REG_END 0x0010fffc
-#define BCHP_REG_CABAC2BINS_0_REG_START 0x00110b00
-#define BCHP_REG_CABAC2BINS_0_REG_END 0x00110bfc
-#define BCHP_REG_CABAC2BINS2_0_REG_START 0x00112400
-#define BCHP_REG_CABAC2BINS2_0_REG_END 0x001127fc
-#define BCHP_HEVD_CABAC_0_REG_START 0x00113000
-#define BCHP_HEVD_CABAC_0_REG_END 0x0011307c
-#define BCHP_HEVD_OL_CTL_0_REG_START 0x00114000
-#define BCHP_HEVD_OL_CTL_0_REG_END 0x001151fc
-#define BCHP_DECODE_MAIN_0_REG_START 0x00120100
-#define BCHP_DECODE_MAIN_0_REG_END 0x001201fc
-#define BCHP_DECODE_MCOM_0_REG_START 0x00120300
-#define BCHP_DECODE_MCOM_0_REG_END 0x0012031c
-#define BCHP_DECODE_SPRE_0_REG_START 0x00120320
-#define BCHP_DECODE_SPRE_0_REG_END 0x0012033c
-#define BCHP_DECODE_WPRD_0_REG_START 0x00120340
-#define BCHP_DECODE_WPRD_0_REG_END 0x0012035c
-#define BCHP_DECODE_DQNT_0_REG_START 0x00120400
-#define BCHP_DECODE_DQNT_0_REG_END 0x0012045c
-#define BCHP_DECODE_DQNT_8X8_0_REG_START 0x00120500
-#define BCHP_DECODE_DQNT_8X8_0_REG_END 0x0012057c
-#define BCHP_DECODE_VP8_XFRM_0_REG_START 0x00120600
-#define BCHP_DECODE_VP8_XFRM_0_REG_END 0x0012060c
-#define BCHP_DECODE_VP6_DCP_0_REG_START 0x00120620
-#define BCHP_DECODE_VP6_DCP_0_REG_END 0x0012062c
-#define BCHP_DECODE_XFRM_0_REG_START 0x00120700
-#define BCHP_DECODE_XFRM_0_REG_END 0x0012071c
-#define BCHP_DECODE_DBLK_0_REG_START 0x00120720
-#define BCHP_DECODE_DBLK_0_REG_END 0x0012073c
-#define BCHP_DECODE_MB_0_REG_START 0x00120740
-#define BCHP_DECODE_MB_0_REG_END 0x0012075c
-#define BCHP_DECODE_SINT_0_REG_START 0x00120c00
-#define BCHP_DECODE_SINT_0_REG_END 0x00120dfc
-#define BCHP_DECODE_WPTBL_0_REG_START 0x00123000
-#define BCHP_DECODE_WPTBL_0_REG_END 0x001231fc
-#define BCHP_HEVD_BE_GLOBAL_0_REG_START 0x00124000
-#define BCHP_HEVD_BE_GLOBAL_0_REG_END 0x00124030
-#define BCHP_HEVD_IXFORM_0_REG_START 0x00124100
-#define BCHP_HEVD_IXFORM_0_REG_END 0x001241fc
-#define BCHP_HEVD_MCOMP_0_REG_START 0x00124200
-#define BCHP_HEVD_MCOMP_0_REG_END 0x001242fc
-#define BCHP_HEVD_SPRED_0_REG_START 0x00124300
-#define BCHP_HEVD_SPRED_0_REG_END 0x001243f0
-#define BCHP_HEVD_FILTER_0_REG_START 0x00124400
-#define BCHP_HEVD_FILTER_0_REG_END 0x001244fc
-#define BCHP_HEVD_OUTPUT_0_REG_START 0x00124500
-#define BCHP_HEVD_OUTPUT_0_REG_END 0x001245fc
-#define BCHP_HEVD_MARKER_0_REG_START 0x00124f00
-#define BCHP_HEVD_MARKER_0_REG_END 0x00124f7c
-#define BCHP_HEVD_FE_CTRL_0_REG_START 0x00125000
-#define BCHP_HEVD_FE_CTRL_0_REG_END 0x0012503c
-#define BCHP_HEVD_STRM_IN_0_REG_START 0x00125100
-#define BCHP_HEVD_STRM_IN_0_REG_END 0x00125118
-#define BCHP_HEVD_CMDBUS_XMIT_0_REG_START 0x00125200
-#define BCHP_HEVD_CMDBUS_XMIT_0_REG_END 0x00125230
-#define BCHP_HEVD_VECGEN_0_REG_START 0x00125400
-#define BCHP_HEVD_VECGEN_0_REG_END 0x0012568c
-#define BCHP_DCD_PIPE_CTL_0_REG_START 0x00126000
-#define BCHP_DCD_PIPE_CTL_0_REG_END 0x00126404
-#define BCHP_HEVD_PCACHE_0_REG_START 0x00126800
-#define BCHP_HEVD_PCACHE_0_REG_END 0x00126834
-#define BCHP_HEVD_PFRI_0_REG_START 0x00126a00
-#define BCHP_HEVD_PFRI_0_REG_END 0x00126b58
-#define BCHP_RVC_0_REG_START 0x00126c00
-#define BCHP_RVC_0_REG_END 0x00126c20
-#define BCHP_ILS_REGS_0_REG_START 0x00127000
-#define BCHP_ILS_REGS_0_REG_END 0x001270fc
-#define BCHP_ILS_SCALE_ADDR_0_REG_START 0x00127100
-#define BCHP_ILS_SCALE_ADDR_0_REG_END 0x0012710c
-#define BCHP_ILS_SPSCALE_FILL_0_REG_START 0x00127180
-#define BCHP_ILS_SPSCALE_FILL_0_REG_END 0x00127184
-#define BCHP_ILS_MVSCALE_0_REG_START 0x00127200
-#define BCHP_ILS_MVSCALE_0_REG_END 0x0012738c
-#define BCHP_ILB_REGS_0_REG_START 0x00127400
-#define BCHP_ILB_REGS_0_REG_END 0x00127410
-#define BCHP_BLD_DECODE_MAIN_0_REG_START 0x00128100
-#define BCHP_BLD_DECODE_MAIN_0_REG_END 0x001281fc
-#define BCHP_BLD_DECODE_MCOM_0_REG_START 0x00128300
-#define BCHP_BLD_DECODE_MCOM_0_REG_END 0x0012831c
-#define BCHP_BLD_DECODE_SPRE_0_REG_START 0x00128320
-#define BCHP_BLD_DECODE_SPRE_0_REG_END 0x0012833c
-#define BCHP_BLD_DECODE_DQNT_0_REG_START 0x00128400
-#define BCHP_BLD_DECODE_DQNT_0_REG_END 0x0012845c
-#define BCHP_BLD_DECODE_DQNT_8X8_0_REG_START 0x00128500
-#define BCHP_BLD_DECODE_DQNT_8X8_0_REG_END 0x0012857c
-#define BCHP_BLD_DECODE_XFRM_0_REG_START 0x00128700
-#define BCHP_BLD_DECODE_XFRM_0_REG_END 0x0012871c
-#define BCHP_BLD_DECODE_DBLK_0_REG_START 0x00128720
-#define BCHP_BLD_DECODE_DBLK_0_REG_END 0x0012873c
-#define BCHP_BLD_DECODE_MB_0_REG_START 0x00128740
-#define BCHP_BLD_DECODE_MB_0_REG_END 0x0012875c
-#define BCHP_BLD_DECODE_SINT_0_REG_START 0x00128c00
-#define BCHP_BLD_DECODE_SINT_0_REG_END 0x00128dfc
-#define BCHP_BLD_DECODE_RVC_0_REG_START 0x00128e00
-#define BCHP_BLD_DECODE_RVC_0_REG_END 0x00128efc
-#define BCHP_BLD_BL_CPU_REGS_0_REG_START 0x0012c000
-#define BCHP_BLD_BL_CPU_REGS_0_REG_END 0x0012c108
-#define BCHP_BLD_BL_CPU_DMA_0_REG_START 0x0012c400
-#define BCHP_BLD_BL_CPU_DMA_0_REG_END 0x0012c440
-#define BCHP_BLD_BL_CPU_DEBUG_0_REG_START 0x0012c800
-#define BCHP_BLD_BL_CPU_DEBUG_0_REG_END 0x0012cffc
-#define BCHP_BLD_DECODE_IP_SHIM_0_REG_START 0x0012d000
-#define BCHP_BLD_DECODE_IP_SHIM_0_REG_END 0x0012d090
-#define BCHP_HEVD_IL_CPU_REGS_0_REG_START 0x00130000
-#define BCHP_HEVD_IL_CPU_REGS_0_REG_END 0x00130108
-#define BCHP_HEVD_IL_CPU_DMA_0_REG_START 0x00130400
-#define BCHP_HEVD_IL_CPU_DMA_0_REG_END 0x00130440
-#define BCHP_HEVD_IL_CPU_DEBUG_0_REG_START 0x00130800
-#define BCHP_HEVD_IL_CPU_DEBUG_0_REG_END 0x00130ffc
-#define BCHP_HEVD_IL_SLICE_DMA_0_REG_START 0x00131000
-#define BCHP_HEVD_IL_SLICE_DMA_0_REG_END 0x0013100c
-#define BCHP_HEVD_IL_LDST_0_REG_START 0x00134000
-#define BCHP_HEVD_IL_LDST_0_REG_END 0x00137ffc
-#define BCHP_SHVD_INTR2_0_REG_START 0x00180000
-#define BCHP_SHVD_INTR2_0_REG_END 0x0018002c
-#define BCHP_SHVD_RGR_0_REG_START 0x00180400
-#define BCHP_SHVD_RGR_0_REG_END 0x00180410
-#define BCHP_VICH_0_REG_START 0x001a0000
-#define BCHP_VICH_0_REG_END 0x001a008b
-#define BCHP_SCPU_LOCALRAM_REG_START 0x00300000
-#define BCHP_SCPU_LOCALRAM_REG_END 0x0030fffc
-#define BCHP_SCPU_GLOBALRAM_REG_START 0x00310000
-#define BCHP_SCPU_GLOBALRAM_REG_END 0x003103fc
-#define BCHP_SCPU_MISB_BRIDGE_REG_START 0x00310400
-#define BCHP_SCPU_MISB_BRIDGE_REG_END 0x00310410
-#define BCHP_SCPU_RGR_BRIDGE_REG_START 0x00310420
-#define BCHP_SCPU_RGR_BRIDGE_REG_END 0x00310430
-#define BCHP_SCPU_INTR1_REG_START 0x00310440
-#define BCHP_SCPU_INTR1_REG_END 0x00310458
-#define BCHP_INTERNAL_INTR2_REG_START 0x00310480
-#define BCHP_INTERNAL_INTR2_REG_END 0x003104ac
-#define BCHP_BSP_IPI_INTR2_REG_START 0x003104c0
-#define BCHP_BSP_IPI_INTR2_REG_END 0x003104ec
-#define BCHP_CPU_IPI_INTR2_REG_START 0x00310540
-#define BCHP_CPU_IPI_INTR2_REG_END 0x0031056c
-#define BCHP_SCPU_HOST_INTR2_REG_START 0x00310580
-#define BCHP_SCPU_HOST_INTR2_REG_END 0x003105ac
-#define BCHP_SCPU_TOP_CTRL_REG_START 0x003105c0
-#define BCHP_SCPU_TOP_CTRL_REG_END 0x003105c8
-#define BCHP_SCPU_SEC_TIME_REG_START 0x003105e0
-#define BCHP_SCPU_SEC_TIME_REG_END 0x003105f4
-#define BCHP_SAGE_UART_REG_START 0x00310600
-#define BCHP_SAGE_UART_REG_END 0x0031061c
-#define BCHP_SCPU_PM_REG_START 0x00310980
-#define BCHP_SCPU_PM_REG_END 0x00310988
-#define BCHP_SCPU_TIMER_REG_START 0x00310e80
-#define BCHP_SCPU_TIMER_REG_END 0x00310ebc
-#define BCHP_BSP_CMDBUF_REG_START 0x0032c800
-#define BCHP_BSP_CMDBUF_REG_END 0x0032cffc
-#define BCHP_BSP_GLB_CONTROL_REG_START 0x0032d000
-#define BCHP_BSP_GLB_CONTROL_REG_END 0x0032d0b0
-#define BCHP_BSP_PKL_REG_START 0x0032d300
-#define BCHP_BSP_PKL_REG_END 0x0032d37c
-#define BCHP_BSP_CONTROL_INTR2_REG_START 0x0032d800
-#define BCHP_BSP_CONTROL_INTR2_REG_END 0x0032d82c
-#define BCHP_BSP_VISTA_GENACC_REG_START 0x0032d900
-#define BCHP_BSP_VISTA_GENACC_REG_END 0x0032d9fc
-#define BCHP_BSP_OTP_SCRATCH_REG_START 0x0032e000
-#define BCHP_BSP_OTP_SCRATCH_REG_END 0x0032fffc
-#define BCHP_XPT_SECURITY_REG_START 0x00360000
-#define BCHP_XPT_SECURITY_REG_END 0x0037fffc
-#define BCHP_SECTOP_GRB_REG_START 0x00380000
-#define BCHP_SECTOP_GRB_REG_END 0x0038000c
-#define BCHP_XPT_SECURITY_NS_INTR2_0_REG_START 0x00380080
-#define BCHP_XPT_SECURITY_NS_INTR2_0_REG_END 0x003800ac
-#define BCHP_XPT_SECURITY_NS_INTR2_1_REG_START 0x00380100
-#define BCHP_XPT_SECURITY_NS_INTR2_1_REG_END 0x0038012c
-#define BCHP_XPT_SECURITY_NS_INTR2_2_REG_START 0x00380180
-#define BCHP_XPT_SECURITY_NS_INTR2_2_REG_END 0x003801ac
-#define BCHP_XPT_SECURITY_NS_REG_START 0x00380200
-#define BCHP_XPT_SECURITY_NS_REG_END 0x003802c8
-#define BCHP_S_SCPU_REG_START 0x003a0000
-#define BCHP_S_SCPU_REG_END 0x003b3ffc
-#define BCHP_SUN_GISB_ARB_REG_START 0x00400000
-#define BCHP_SUN_GISB_ARB_REG_END 0x004007fc
-#define BCHP_SUN_GR_REG_START 0x00401000
-#define BCHP_SUN_GR_REG_END 0x0040100c
-#define BCHP_SSP_RG_REG_START 0x00401200
-#define BCHP_SSP_RG_REG_END 0x0040120c
-#define BCHP_SUN_RG_REG_START 0x00401400
-#define BCHP_SUN_RG_REG_END 0x0040140c
-#define BCHP_TPCAP_REG_START 0x00401800
-#define BCHP_TPCAP_REG_END 0x0040189c
-#define BCHP_SUN_L2_REG_START 0x00403000
-#define BCHP_SUN_L2_REG_END 0x00403044
-#define BCHP_SUN_TOP_CTRL_REG_START 0x00404000
-#define BCHP_SUN_TOP_CTRL_REG_END 0x00404518
-#define BCHP_IRB_REG_START 0x00406000
-#define BCHP_IRB_REG_END 0x00406138
-#define BCHP_PM_REG_START 0x00406180
-#define BCHP_PM_REG_END 0x00406188
-#define BCHP_BSCA_REG_START 0x00406200
-#define BCHP_BSCA_REG_END 0x00406254
-#define BCHP_BSCB_REG_START 0x00406280
-#define BCHP_BSCB_REG_END 0x004062d4
-#define BCHP_BSCE_REG_START 0x00406300
-#define BCHP_BSCE_REG_END 0x00406354
-#define BCHP_BSCF_REG_START 0x00406380
-#define BCHP_BSCF_REG_END 0x004063d4
-#define BCHP_PWM_REG_START 0x00406580
-#define BCHP_PWM_REG_END 0x004065a4
-#define BCHP_GIO_REG_START 0x00406700
-#define BCHP_GIO_REG_END 0x0040679c
-#define BCHP_IRQ0_REG_START 0x00406800
-#define BCHP_IRQ0_REG_END 0x00406804
-#define BCHP_IRQ1_REG_START 0x00406808
-#define BCHP_IRQ1_REG_END 0x0040680c
-#define BCHP_TIMER_REG_START 0x00406840
-#define BCHP_TIMER_REG_END 0x0040687c
-#define BCHP_PWMB_REG_START 0x00406880
-#define BCHP_PWMB_REG_END 0x004068a4
-#define BCHP_UARTA_REG_START 0x00406b00
-#define BCHP_UARTA_REG_END 0x00406b1c
-#define BCHP_UARTB_REG_START 0x00406b40
-#define BCHP_UARTB_REG_END 0x00406b5c
-#define BCHP_UARTC_REG_START 0x00406b80
-#define BCHP_UARTC_REG_END 0x00406b9c
-#define BCHP_SCA_REG_START 0x00406c00
-#define BCHP_SCA_REG_END 0x00406cbc
-#define BCHP_SCB_REG_START 0x00406d00
-#define BCHP_SCB_REG_END 0x00406dbc
-#define BCHP_SCIRQ0_REG_START 0x00406e00
-#define BCHP_SCIRQ0_REG_END 0x00406e04
-#define BCHP_SCIRQ1_REG_START 0x00406e40
-#define BCHP_SCIRQ1_REG_END 0x00406e44
-#define BCHP_SCIRQ_SCPU_REG_START 0x00406e80
-#define BCHP_SCIRQ_SCPU_REG_END 0x00406e84
-#define BCHP_MCIF_REG_START 0x00407000
-#define BCHP_MCIF_REG_END 0x00407028
-#define BCHP_MCIF1_REG_START 0x00407040
-#define BCHP_MCIF1_REG_END 0x00407068
-#define BCHP_MCIF_INTR2_REG_START 0x00407080
-#define BCHP_MCIF_INTR2_REG_END 0x004070c4
-#define BCHP_UPG_AUX_INTR2_REG_START 0x00407100
-#define BCHP_UPG_AUX_INTR2_REG_END 0x0040712c
-#define BCHP_UPG_UART_DMA_REG_START 0x00407600
-#define BCHP_UPG_UART_DMA_REG_END 0x00407630
-#define BCHP_AON_CTRL_REG_START 0x00410000
-#define BCHP_AON_CTRL_REG_END 0x004103fc
-#define BCHP_AON_L2_REG_START 0x00410400
-#define BCHP_AON_L2_REG_END 0x0041042c
-#define BCHP_AON_PM_L2_REG_START 0x00410440
-#define BCHP_AON_PM_L2_REG_END 0x0041046c
-#define BCHP_AON_PIN_CTRL_REG_START 0x00410500
-#define BCHP_AON_PIN_CTRL_REG_END 0x00410518
-#define BCHP_AON_HDMI_TX_REG_START 0x00410600
-#define BCHP_AON_HDMI_TX_REG_END 0x00410698
-#define BCHP_AON_HDMI_TX_1_REG_START 0x00410700
-#define BCHP_AON_HDMI_TX_1_REG_END 0x00410798
-#define BCHP_AON_HDMI_RX_REG_START 0x00410800
-#define BCHP_AON_HDMI_RX_REG_END 0x00410900
-#define BCHP_MSPI_REG_START 0x00411000
-#define BCHP_MSPI_REG_END 0x0041117c
-#define BCHP_LDK_REG_START 0x00411180
-#define BCHP_LDK_REG_END 0x004111bc
-#define BCHP_PM_AON_REG_START 0x004111c0
-#define BCHP_PM_AON_REG_END 0x004111c8
-#define BCHP_ICAP_REG_START 0x00411200
-#define BCHP_ICAP_REG_END 0x0041123c
-#define BCHP_KBD1_REG_START 0x00411240
-#define BCHP_KBD1_REG_END 0x0041127c
-#define BCHP_KBD2_REG_START 0x00411280
-#define BCHP_KBD2_REG_END 0x004112bc
-#define BCHP_KBD3_REG_START 0x004112c0
-#define BCHP_KBD3_REG_END 0x004112fc
-#define BCHP_BSCC_REG_START 0x00411300
-#define BCHP_BSCC_REG_END 0x00411354
-#define BCHP_BSCD_REG_START 0x00411380
-#define BCHP_BSCD_REG_END 0x004113d4
-#define BCHP_IRQ0_AON_REG_START 0x00411480
-#define BCHP_IRQ0_AON_REG_END 0x00411484
-#define BCHP_IRQ1_AON_REG_START 0x00411488
-#define BCHP_IRQ1_AON_REG_END 0x0041148c
-#define BCHP_GIO_AON_REG_START 0x004114c0
-#define BCHP_GIO_AON_REG_END 0x004114fc
-#define BCHP_BICAP_REG_START 0x00411500
-#define BCHP_BICAP_REG_END 0x00411538
-#define BCHP_UPG_AUX_AON_INTR2_REG_START 0x00411540
-#define BCHP_UPG_AUX_AON_INTR2_REG_END 0x0041156c
-#define BCHP_WKTMR_REG_START 0x00411580
-#define BCHP_WKTMR_REG_END 0x00411590
-#define BCHP_CNTControlBase_REG_START 0x00414000
-#define BCHP_CNTControlBase_REG_END 0x00414ffc
-#define BCHP_CNTReadBase_REG_START 0x00416000
-#define BCHP_CNTReadBase_REG_END 0x00416ffc
-#define BCHP_SYS_GISB_ARB_SEC_REG_START 0x0041e000
-#define BCHP_SYS_GISB_ARB_SEC_REG_END 0x0041e7fc
-#define BCHP_SYS_TOP_CTRL_SEC_REG_START 0x0041e800
-#define BCHP_SYS_TOP_CTRL_SEC_REG_END 0x0041e804
-#define BCHP_AON_CTRL_SECURE_REG_START 0x0041e900
-#define BCHP_AON_CTRL_SECURE_REG_END 0x0041e97c
-#define BCHP_BOOTSRAM_SECURE_REG_START 0x00420000
-#define BCHP_BOOTSRAM_SECURE_REG_END 0x0042fffc
-#define BCHP_ITCH0_REG_START 0x00430000
-#define BCHP_ITCH0_REG_END 0x00430000
-#define BCHP_HIF_SECURE_CTRL_REG_START 0x00430400
-#define BCHP_HIF_SECURE_CTRL_REG_END 0x00430400
-#define BCHP_HIF_SECURE_BSPI_REG_START 0x00430500
-#define BCHP_HIF_SECURE_BSPI_REG_END 0x00430500
-#define BCHP_HIF_SECURE_LR_SPI_REG_START 0x00430600
-#define BCHP_HIF_SECURE_LR_SPI_REG_END 0x00430600
-#define BCHP_NAND_SECURE_REG_START 0x00430800
-#define BCHP_NAND_SECURE_REG_END 0x00430800
-#define BCHP_HIF_SECURE_INDIRECT_MSPI_PIPE_REG_START 0x00430c00
-#define BCHP_HIF_SECURE_INDIRECT_MSPI_PIPE_REG_END 0x00430c00
-#define BCHP_HIF_CPUBIUARCH_SECURE_REG_START 0x00430e00
-#define BCHP_HIF_CPUBIUARCH_SECURE_REG_END 0x00430ffc
-#define BCHP_HIF_CONTINUATION_SECURE_REG_START 0x00431000
-#define BCHP_HIF_CONTINUATION_SECURE_REG_END 0x00431004
-#define BCHP_ITCH1_REG_START 0x00431200
-#define BCHP_ITCH1_REG_END 0x00431200
-#define BCHP_SDIO_0_HOST_REG_START 0x00440000
-#define BCHP_SDIO_0_HOST_REG_END 0x004400fc
-#define BCHP_SDIO_0_CFG_REG_START 0x00440100
-#define BCHP_SDIO_0_CFG_REG_END 0x004401fc
-#define BCHP_SDIO_1_HOST_REG_START 0x00440200
-#define BCHP_SDIO_1_HOST_REG_END 0x004402fc
-#define BCHP_SDIO_1_CFG_REG_START 0x00440300
-#define BCHP_SDIO_1_CFG_REG_END 0x004403fc
-#define BCHP_SDIO_1_BOOT_REG_START 0x00440400
-#define BCHP_SDIO_1_BOOT_REG_END 0x0044043c
-#define BCHP_EBI_REG_START 0x00440800
-#define BCHP_EBI_REG_END 0x00440bfc
-#define BCHP_HIF_INTR2_REG_START 0x00441000
-#define BCHP_HIF_INTR2_REG_END 0x0044102c
-#define BCHP_IPI0_INTR2_REG_START 0x00441100
-#define BCHP_IPI0_INTR2_REG_END 0x0044112c
-#define BCHP_IPI1_INTR2_REG_START 0x00441200
-#define BCHP_IPI1_INTR2_REG_END 0x0044122c
-#define BCHP_HIF_CPU_INTR1_REG_START 0x00441500
-#define BCHP_HIF_CPU_INTR1_REG_END 0x0044153c
-#define BCHP_PCI_PCIE_INTR1_REG_START 0x00441600
-#define BCHP_PCI_PCIE_INTR1_REG_END 0x0044163c
-#define BCHP_HIF_RGR2_REG_START 0x00441700
-#define BCHP_HIF_RGR2_REG_END 0x00441710
-#define BCHP_HIF_SPI_INTR2_REG_START 0x00441a00
-#define BCHP_HIF_SPI_INTR2_REG_END 0x00441a2c
-#define BCHP_HIF_TOP_CTRL_REG_START 0x00442000
-#define BCHP_HIF_TOP_CTRL_REG_END 0x0044203c
-#define BCHP_WEBHIF_L1_MASK_REG_START 0x00442100
-#define BCHP_WEBHIF_L1_MASK_REG_END 0x0044210c
-#define BCHP_HIF_CPUBIUARCH_REG_START 0x00442200
-#define BCHP_HIF_CPUBIUARCH_REG_END 0x004423fc
-#define BCHP_HIF_CPUBIUCTRL_REG_START 0x00442400
-#define BCHP_HIF_CPUBIUCTRL_REG_END 0x004427fc
-#define BCHP_NAND_REG_START 0x00442800
-#define BCHP_NAND_REG_END 0x00442dfc
-#define BCHP_FLASH_DMA_REG_START 0x00443000
-#define BCHP_FLASH_DMA_REG_END 0x00443028
-#define BCHP_BSPI_REG_START 0x00443200
-#define BCHP_BSPI_REG_END 0x0044324c
-#define BCHP_BSPI_RAF_REG_START 0x00443300
-#define BCHP_BSPI_RAF_REG_END 0x00443320
-#define BCHP_HIF_MSPI_REG_START 0x00443400
-#define BCHP_HIF_MSPI_REG_END 0x00443584
-#define BCHP_HIF_CONTINUATION_SECURE_TM_REG_START 0x00443600
-#define BCHP_HIF_CONTINUATION_SECURE_TM_REG_END 0x00443604
-#define BCHP_BOOTSRAM_TM_REG_START 0x00450000
-#define BCHP_BOOTSRAM_TM_REG_END 0x0045fffc
-#define BCHP_WEBHIF_RGR1_REG_START 0x00460000
-#define BCHP_WEBHIF_RGR1_REG_END 0x00460010
-#define BCHP_WEBHIF_INTR2_REG_START 0x00460100
-#define BCHP_WEBHIF_INTR2_REG_END 0x0046012c
-#define BCHP_WEBHIF_IPI0_INTR2_REG_START 0x00460200
-#define BCHP_WEBHIF_IPI0_INTR2_REG_END 0x0046022c
-#define BCHP_WEBHIF_STB_IPI0_INTR2_REG_START 0x00460400
-#define BCHP_WEBHIF_STB_IPI0_INTR2_REG_END 0x0046042c
-#define BCHP_WEBHIF_CPU_INTR1_REG_START 0x00460600
-#define BCHP_WEBHIF_CPU_INTR1_REG_END 0x0046063c
-#define BCHP_WEBHIF_SCRATCH_REG_START 0x00460800
-#define BCHP_WEBHIF_SCRATCH_REG_END 0x0046081c
-#define BCHP_WEBHIF_TIMER_REG_START 0x00460900
-#define BCHP_WEBHIF_TIMER_REG_END 0x0046093c
-#define BCHP_WEBHIF_TOP_CTRL_REG_START 0x00460a00
-#define BCHP_WEBHIF_TOP_CTRL_REG_END 0x00460a00
-#define BCHP_HIF_CONTINUATION_REG_START 0x00462000
-#define BCHP_HIF_CONTINUATION_REG_END 0x004620fc
-#define BCHP_WEBHIF_CONTINUATION_REG_START 0x00462800
-#define BCHP_WEBHIF_CONTINUATION_REG_END 0x00462804
-#define BCHP_SATA_GRB_REG_START 0x00468000
-#define BCHP_SATA_GRB_REG_END 0x0046800c
-#define BCHP_SATA_TOP_CTRL_REG_START 0x00468040
-#define BCHP_SATA_TOP_CTRL_REG_END 0x00468060
-#define BCHP_SATA3_INTR2_REG_START 0x00468080
-#define BCHP_SATA3_INTR2_REG_END 0x004680ac
-#define BCHP_PORT0_SATA3_PCB_REG_START 0x00468100
-#define BCHP_PORT0_SATA3_PCB_REG_END 0x00468ffc
-#define BCHP_SATA_AHCI_GHC_REG_START 0x0046a000
-#define BCHP_SATA_AHCI_GHC_REG_END 0x0046a028
-#define BCHP_SATA_GLOBAL_RESERVED_REG_START 0x0046a02c
-#define BCHP_SATA_GLOBAL_RESERVED_REG_END 0x0046a09c
-#define BCHP_SATA_PORT0_AHCI_S1_REG_START 0x0046a100
-#define BCHP_SATA_PORT0_AHCI_S1_REG_END 0x0046a11c
-#define BCHP_SATA_PORT0_AHCI_S2_REG_START 0x0046a120
-#define BCHP_SATA_PORT0_AHCI_S2_REG_END 0x0046a134
-#define BCHP_SATA_PORT0_AHCI_S3_REG_START 0x0046a138
-#define BCHP_SATA_PORT0_AHCI_S3_REG_END 0x0046a17c
-#define BCHP_SATA_AHCI_PCICFG_REG_START 0x0046a600
-#define BCHP_SATA_AHCI_PCICFG_REG_END 0x0046a664
-#define BCHP_SATA_PORT0_CTRL_REG_START 0x0046a700
-#define BCHP_SATA_PORT0_CTRL_REG_END 0x0046a730
-#define BCHP_SATA_PORT0_CJPAT_REG_START 0x0046a740
-#define BCHP_SATA_PORT0_CJPAT_REG_END 0x0046a764
-#define BCHP_SATA_LEG_PCICFG_REG_START 0x0046a800
-#define BCHP_SATA_LEG_PCICFG_REG_END 0x0046a880
-#define BCHP_SATA_PORT0_LEG_S1_REG_START 0x0046a900
-#define BCHP_SATA_PORT0_LEG_S1_REG_END 0x0046a934
-#define BCHP_SATA_PORT0_LEG_S2_REG_START 0x0046a940
-#define BCHP_SATA_PORT0_LEG_S2_REG_END 0x0046a954
-#define BCHP_SATA_PORT0_LEG_S3_REG_START 0x0046a958
-#define BCHP_SATA_PORT0_LEG_S3_REG_END 0x0046a998
-#define BCHP_RFM_SYSCLK_REG_START 0x0046c000
-#define BCHP_RFM_SYSCLK_REG_END 0x0046c124
-#define BCHP_RFM_CLK27_REG_START 0x0046c000
-#define BCHP_RFM_CLK27_REG_END 0x0046c470
-#define BCHP_RFM_L2_REG_START 0x0046cc00
-#define BCHP_RFM_L2_REG_END 0x0046cc2c
-#define BCHP_RFM_GRB_REG_START 0x0046d000
-#define BCHP_RFM_GRB_REG_END 0x0046d00c
-#define BCHP_PCIE_0_RC_CFG_TYPE1_REG_START 0x00470000
-#define BCHP_PCIE_0_RC_CFG_TYPE1_REG_END 0x0047003c
-#define BCHP_PCIE_0_RC_CFG_PM_REG_START 0x00470048
-#define BCHP_PCIE_0_RC_CFG_PM_REG_END 0x0047004c
-#define BCHP_PCIE_0_RC_CFG_PCIE_REG_START 0x004700ac
-#define BCHP_PCIE_0_RC_CFG_PCIE_REG_END 0x004700e4
-#define BCHP_PCIE_0_RC_CFG_AER_REG_START 0x00470100
-#define BCHP_PCIE_0_RC_CFG_AER_REG_END 0x00470134
-#define BCHP_PCIE_0_RC_CFG_VC_REG_START 0x00470160
-#define BCHP_PCIE_0_RC_CFG_VC_REG_END 0x00470178
-#define BCHP_PCIE_0_RC_CFG_VENDOR_REG_START 0x00470180
-#define BCHP_PCIE_0_RC_CFG_VENDOR_REG_END 0x004701a4
-#define BCHP_PCIE_0_RC_CFG_PRIV0_REG_START 0x00470404
-#define BCHP_PCIE_0_RC_CFG_PRIV0_REG_END 0x00470418
-#define BCHP_PCIE_0_RC_CFG_PRIV1_REG_START 0x00470428
-#define BCHP_PCIE_0_RC_CFG_PRIV1_REG_END 0x00470630
-#define BCHP_PCIE_0_RC_TL_REG_START 0x00470800
-#define BCHP_PCIE_0_RC_TL_REG_END 0x00470998
-#define BCHP_PCIE_0_RC_DL_REG_START 0x00471000
-#define BCHP_PCIE_0_RC_DL_REG_END 0x00471424
-#define BCHP_PCIE_0_RC_PL_REG_START 0x00471800
-#define BCHP_PCIE_0_RC_PL_REG_END 0x00471e1c
-#define BCHP_PCIE_0_EP_CFG_TYPE0_REG_START 0x00472000
-#define BCHP_PCIE_0_EP_CFG_TYPE0_REG_END 0x0047203c
-#define BCHP_PCIE_0_EP_CFG_PM_REG_START 0x00472048
-#define BCHP_PCIE_0_EP_CFG_PM_REG_END 0x0047204c
-#define BCHP_PCIE_0_EP_CFG_VPD_REG_START 0x00472050
-#define BCHP_PCIE_0_EP_CFG_VPD_REG_END 0x00472054
-#define BCHP_PCIE_0_EP_CFG_MSI_REG_START 0x00472058
-#define BCHP_PCIE_0_EP_CFG_MSI_REG_END 0x00472064
-#define BCHP_PCIE_0_EP_CFG_MSIX_REG_START 0x004720a0
-#define BCHP_PCIE_0_EP_CFG_MSIX_REG_END 0x004720a8
-#define BCHP_PCIE_0_EP_CFG_PCIE_REG_START 0x004720ac
-#define BCHP_PCIE_0_EP_CFG_PCIE_REG_END 0x004720e4
-#define BCHP_PCIE_0_EP_CFG_AER_REG_START 0x00472100
-#define BCHP_PCIE_0_EP_CFG_AER_REG_END 0x00472134
-#define BCHP_PCIE_0_EP_CFG_DEV_REG_START 0x0047213c
-#define BCHP_PCIE_0_EP_CFG_DEV_REG_END 0x00472144
-#define BCHP_PCIE_0_EP_CFG_PB_REG_START 0x00472150
-#define BCHP_PCIE_0_EP_CFG_PB_REG_END 0x0047215c
-#define BCHP_PCIE_0_EP_CFG_VC_REG_START 0x00472160
-#define BCHP_PCIE_0_EP_CFG_VC_REG_END 0x00472178
-#define BCHP_PCIE_0_EP_CFG_VENDOR_REG_START 0x00472180
-#define BCHP_PCIE_0_EP_CFG_VENDOR_REG_END 0x004721a4
-#define BCHP_PCIE_0_EP_CFG_PRIV0_REG_START 0x00472404
-#define BCHP_PCIE_0_EP_CFG_PRIV0_REG_END 0x00472418
-#define BCHP_PCIE_0_EP_CFG_PRIV1_REG_START 0x00472428
-#define BCHP_PCIE_0_EP_CFG_PRIV1_REG_END 0x00472630
-#define BCHP_PCIE_0_EP_TL_REG_START 0x00472800
-#define BCHP_PCIE_0_EP_TL_REG_END 0x00472998
-#define BCHP_PCIE_0_EP_DL_REG_START 0x00473000
-#define BCHP_PCIE_0_EP_DL_REG_END 0x00473424
-#define BCHP_PCIE_0_EP_PL_REG_START 0x00473800
-#define BCHP_PCIE_0_EP_PL_REG_END 0x00473e1c
-#define BCHP_PCIE_0_MISC_REG_START 0x00474000
-#define BCHP_PCIE_0_MISC_REG_END 0x004740c4
-#define BCHP_PCIE_0_MISC_PERST_REG_START 0x00474100
-#define BCHP_PCIE_0_MISC_PERST_REG_END 0x00474104
-#define BCHP_PCIE_0_MISC_HARD_REG_START 0x00474200
-#define BCHP_PCIE_0_MISC_HARD_REG_END 0x00474204
-#define BCHP_PCIE_0_INTR2_REG_START 0x00474300
-#define BCHP_PCIE_0_INTR2_REG_END 0x0047432c
-#define BCHP_PCIE_0_DMA_REG_START 0x00474400
-#define BCHP_PCIE_0_DMA_REG_END 0x0047446c
-#define BCHP_PCIE_0_EXT_CFG_REG_START 0x00478000
-#define BCHP_PCIE_0_EXT_CFG_REG_END 0x00479008
-#define BCHP_PCIE_0_RGR1_REG_START 0x00479200
-#define BCHP_PCIE_0_RGR1_REG_END 0x00479210
-#define BCHP_PCIE_0_RG_REG_START 0x00479300
-#define BCHP_PCIE_0_RG_REG_END 0x0047930c
-#define BCHP_USB_CAPS_REG_START 0x00480000
-#define BCHP_USB_CAPS_REG_END 0x0048002c
-#define BCHP_USB_GR_BRIDGE_REG_START 0x00480100
-#define BCHP_USB_GR_BRIDGE_REG_END 0x0048010c
-#define BCHP_USB_INTR2_REG_START 0x00480180
-#define BCHP_USB_INTR2_REG_END 0x004801ac
-#define BCHP_USB_CTRL_REG_START 0x00480200
-#define BCHP_USB_CTRL_REG_END 0x0048027c
-#define BCHP_USB_EHCI_REG_START 0x00480300
-#define BCHP_USB_EHCI_REG_END 0x004803a4
-#define BCHP_USB_OHCI_REG_START 0x00480400
-#define BCHP_USB_OHCI_REG_END 0x00480454
-#define BCHP_USB_EHCI1_REG_START 0x00480500
-#define BCHP_USB_EHCI1_REG_END 0x004805a4
-#define BCHP_USB_OHCI1_REG_START 0x00480600
-#define BCHP_USB_OHCI1_REG_END 0x00480654
-#define BCHP_USB_XHCI_REG_START 0x00481000
-#define BCHP_USB_XHCI_REG_END 0x004818c4
-#define BCHP_USB_XHCI_EC_REG_START 0x00481940
-#define BCHP_USB_XHCI_EC_REG_END 0x00481fc0
-#define BCHP_USB1_CAPS_REG_START 0x00490000
-#define BCHP_USB1_CAPS_REG_END 0x0049002c
-#define BCHP_USB1_GR_BRIDGE_REG_START 0x00490100
-#define BCHP_USB1_GR_BRIDGE_REG_END 0x0049010c
-#define BCHP_USB1_INTR2_REG_START 0x00490180
-#define BCHP_USB1_INTR2_REG_END 0x004901ac
-#define BCHP_USB1_CTRL_REG_START 0x00490200
-#define BCHP_USB1_CTRL_REG_END 0x0049027c
-#define BCHP_USB1_EHCI_REG_START 0x00490300
-#define BCHP_USB1_EHCI_REG_END 0x004903a4
-#define BCHP_USB1_OHCI_REG_START 0x00490400
-#define BCHP_USB1_OHCI_REG_END 0x00490454
-#define BCHP_USB1_EHCI1_REG_START 0x00490500
-#define BCHP_USB1_EHCI1_REG_END 0x004905a4
-#define BCHP_USB1_OHCI1_REG_START 0x00490600
-#define BCHP_USB1_OHCI1_REG_END 0x00490654
-#define BCHP_AVS_CPU_PROG_MEM_REG_START 0x004c0000
-#define BCHP_AVS_CPU_PROG_MEM_REG_END 0x004c2ffc
-#define BCHP_AVS_CPU_DATA_MEM_REG_START 0x004c4000
-#define BCHP_AVS_CPU_DATA_MEM_REG_END 0x004c4bfc
-#define BCHP_AVS_CPU_CORE_REGS_REG_START 0x004c8000
-#define BCHP_AVS_CPU_CORE_REGS_REG_END 0x004c80fc
-#define BCHP_AVS_CPU_AUX_REGS_REG_START 0x004ca000
-#define BCHP_AVS_CPU_AUX_REGS_REG_END 0x004caa08
-#define BCHP_AVS_UART_REG_START 0x004d0000
-#define BCHP_AVS_UART_REG_END 0x004d0ffc
-#define BCHP_AVS_CPU_L2_REG_START 0x004d1100
-#define BCHP_AVS_CPU_L2_REG_END 0x004d112c
-#define BCHP_AVS_HOST_L2_REG_START 0x004d1200
-#define BCHP_AVS_HOST_L2_REG_END 0x004d122c
-#define BCHP_AVS_CPU_CTRL_REG_START 0x004d1300
-#define BCHP_AVS_CPU_CTRL_REG_END 0x004d1330
-#define BCHP_AVS_BSTI_REG_START 0x004d1400
-#define BCHP_AVS_BSTI_REG_END 0x004d1404
-#define BCHP_AVS_TOP_CTRL_REG_START 0x004d1500
-#define BCHP_AVS_TOP_CTRL_REG_END 0x004d15b8
-#define BCHP_AVS_HW_MNTR_REG_START 0x004d2000
-#define BCHP_AVS_HW_MNTR_REG_END 0x004d20c8
-#define BCHP_AVS_PVT_MNTR_CONFIG_REG_START 0x004d2100
-#define BCHP_AVS_PVT_MNTR_CONFIG_REG_END 0x004d2124
-#define BCHP_AVS_RO_REGISTERS_0_REG_START 0x004d2200
-#define BCHP_AVS_RO_REGISTERS_0_REG_END 0x004d22e0
-#define BCHP_AVS_RO_REGISTERS_1_REG_START 0x004d2800
-#define BCHP_AVS_RO_REGISTERS_1_REG_END 0x004d28dc
-#define BCHP_AVS_ROSC_THRESHOLD_1_REG_START 0x004d2d00
-#define BCHP_AVS_ROSC_THRESHOLD_1_REG_END 0x004d2dfc
-#define BCHP_AVS_ROSC_THRESHOLD_2_REG_START 0x004d2e00
-#define BCHP_AVS_ROSC_THRESHOLD_2_REG_END 0x004d2efc
-#define BCHP_AVS_PMB_S_000_REG_START 0x004d4000
-#define BCHP_AVS_PMB_S_000_REG_END 0x004d4024
-#define BCHP_AVS_PMB_S_001_REG_START 0x004d4040
-#define BCHP_AVS_PMB_S_001_REG_END 0x004d4064
-#define BCHP_AVS_PMB_S_002_REG_START 0x004d4080
-#define BCHP_AVS_PMB_S_002_REG_END 0x004d40a4
-#define BCHP_AVS_PMB_S_003_REG_START 0x004d40c0
-#define BCHP_AVS_PMB_S_003_REG_END 0x004d40e4
-#define BCHP_AVS_PMB_S_004_REG_START 0x004d4100
-#define BCHP_AVS_PMB_S_004_REG_END 0x004d4124
-#define BCHP_AVS_PMB_S_005_REG_START 0x004d4140
-#define BCHP_AVS_PMB_S_005_REG_END 0x004d4164
-#define BCHP_AVS_PMB_S_006_REG_START 0x004d4180
-#define BCHP_AVS_PMB_S_006_REG_END 0x004d41a4
-#define BCHP_AVS_PMB_S_007_REG_START 0x004d41c0
-#define BCHP_AVS_PMB_S_007_REG_END 0x004d41e4
-#define BCHP_AVS_PMB_S_008_REG_START 0x004d4200
-#define BCHP_AVS_PMB_S_008_REG_END 0x004d4224
-#define BCHP_AVS_PMB_S_009_REG_START 0x004d4240
-#define BCHP_AVS_PMB_S_009_REG_END 0x004d4264
-#define BCHP_AVS_PMB_S_010_REG_START 0x004d4280
-#define BCHP_AVS_PMB_S_010_REG_END 0x004d42a4
-#define BCHP_AVS_PMB_S_011_REG_START 0x004d42c0
-#define BCHP_AVS_PMB_S_011_REG_END 0x004d42e4
-#define BCHP_AVS_PMB_S_012_REG_START 0x004d4300
-#define BCHP_AVS_PMB_S_012_REG_END 0x004d4324
-#define BCHP_AVS_PMB_S_013_REG_START 0x004d4340
-#define BCHP_AVS_PMB_S_013_REG_END 0x004d4364
-#define BCHP_AVS_PMB_S_014_REG_START 0x004d4380
-#define BCHP_AVS_PMB_S_014_REG_END 0x004d43a4
-#define BCHP_AVS_PMB_S_015_REG_START 0x004d43c0
-#define BCHP_AVS_PMB_S_015_REG_END 0x004d43e4
-#define BCHP_AVS_PMB_S_016_REG_START 0x004d4400
-#define BCHP_AVS_PMB_S_016_REG_END 0x004d4424
-#define BCHP_AVS_PMB_S_017_REG_START 0x004d4440
-#define BCHP_AVS_PMB_S_017_REG_END 0x004d4464
-#define BCHP_AVS_PMB_S_018_REG_START 0x004d4480
-#define BCHP_AVS_PMB_S_018_REG_END 0x004d44a4
-#define BCHP_AVS_PMB_S_019_REG_START 0x004d44c0
-#define BCHP_AVS_PMB_S_019_REG_END 0x004d44e4
-#define BCHP_AVS_PMB_S_020_REG_START 0x004d4500
-#define BCHP_AVS_PMB_S_020_REG_END 0x004d4524
-#define BCHP_AVS_PMB_S_021_REG_START 0x004d4540
-#define BCHP_AVS_PMB_S_021_REG_END 0x004d4564
-#define BCHP_AVS_PMB_S_022_REG_START 0x004d4580
-#define BCHP_AVS_PMB_S_022_REG_END 0x004d45a4
-#define BCHP_AVS_PMB_S_023_REG_START 0x004d45c0
-#define BCHP_AVS_PMB_S_023_REG_END 0x004d45e4
-#define BCHP_AVS_PMB_REGISTERS_REG_START 0x004d6000
-#define BCHP_AVS_PMB_REGISTERS_REG_END 0x004d6008
-#define BCHP_CLKGEN_REG_START 0x004e0000
-#define BCHP_CLKGEN_REG_END 0x004e05b0
-#define BCHP_VCXO_0_RM_REG_START 0x004e2800
-#define BCHP_VCXO_0_RM_REG_END 0x004e282c
-#define BCHP_VCXO_1_RM_REG_START 0x004e2880
-#define BCHP_VCXO_1_RM_REG_END 0x004e28ac
-#define BCHP_CLKGEN_GR_REG_START 0x004e3000
-#define BCHP_CLKGEN_GR_REG_END 0x004e300c
-#define BCHP_CLKGEN_INTR2_REG_START 0x004e4000
-#define BCHP_CLKGEN_INTR2_REG_END 0x004e4044
-#define BCHP_AVS_RANGE_BLOCKER_REG_START 0x004e5000
-#define BCHP_AVS_RANGE_BLOCKER_REG_END 0x004e5054
-#define BCHP_PROD_OTP_GRB_REG_START 0x004e6000
-#define BCHP_PROD_OTP_GRB_REG_END 0x004e600c
-#define BCHP_JTAG_OTP_REG_START 0x004e6100
-#define BCHP_JTAG_OTP_REG_END 0x004e6138
-#define BCHP_MFD_0_REG_START 0x00600000
-#define BCHP_MFD_0_REG_END 0x006003fc
-#define BCHP_MFD_1_REG_START 0x00600400
-#define BCHP_MFD_1_REG_END 0x006007fc
-#define BCHP_VFD_0_REG_START 0x00602000
-#define BCHP_VFD_0_REG_END 0x006021fc
-#define BCHP_VFD_1_REG_START 0x00602200
-#define BCHP_VFD_1_REG_END 0x006023fc
-#define BCHP_VFD_2_REG_START 0x00602400
-#define BCHP_VFD_2_REG_END 0x006025fc
-#define BCHP_VFD_3_REG_START 0x00602600
-#define BCHP_VFD_3_REG_END 0x006027fc
-#define BCHP_RDC_REG_START 0x00603000
-#define BCHP_RDC_REG_END 0x00603cfc
-#define BCHP_BVNF_INTR2_0_REG_START 0x00604000
-#define BCHP_BVNF_INTR2_0_REG_END 0x0060402c
-#define BCHP_BVNF_INTR2_1_REG_START 0x00604100
-#define BCHP_BVNF_INTR2_1_REG_END 0x0060412c
-#define BCHP_BVNF_INTR2_3_REG_START 0x00604300
-#define BCHP_BVNF_INTR2_3_REG_END 0x0060432c
-#define BCHP_BVNF_INTR2_4_REG_START 0x00604400
-#define BCHP_BVNF_INTR2_4_REG_END 0x0060442c
-#define BCHP_BVNF_INTR2_5_REG_START 0x00604500
-#define BCHP_BVNF_INTR2_5_REG_END 0x0060452c
-#define BCHP_BVNF_INTR2_6_REG_START 0x00604600
-#define BCHP_BVNF_INTR2_6_REG_END 0x0060462c
-#define BCHP_BVNF_INTR2_7_REG_START 0x00604700
-#define BCHP_BVNF_INTR2_7_REG_END 0x0060472c
-#define BCHP_BVNF_INTR2_9_REG_START 0x00604900
-#define BCHP_BVNF_INTR2_9_REG_END 0x0060492c
-#define BCHP_BVNF_INTR2_12_REG_START 0x00604c00
-#define BCHP_BVNF_INTR2_12_REG_END 0x00604c2c
-#define BCHP_BVNF_INTR2_15_REG_START 0x00604f00
-#define BCHP_BVNF_INTR2_15_REG_END 0x00604f2c
-#define BCHP_BVNF_INTR2_16_REG_START 0x00605000
-#define BCHP_BVNF_INTR2_16_REG_END 0x0060502c
-#define BCHP_BVNF_INTR2_17_REG_START 0x00605100
-#define BCHP_BVNF_INTR2_17_REG_END 0x0060512c
-#define BCHP_BVNF_INTR2_18_REG_START 0x00605200
-#define BCHP_BVNF_INTR2_18_REG_END 0x0060522c
-#define BCHP_FMISC_REG_START 0x00606000
-#define BCHP_FMISC_REG_END 0x00606020
-#define BCHP_SCL_0_REG_START 0x00620000
-#define BCHP_SCL_0_REG_END 0x006203fc
-#define BCHP_SCL_1_REG_START 0x00620400
-#define BCHP_SCL_1_REG_END 0x006207fc
-#define BCHP_SCL_2_REG_START 0x00620800
-#define BCHP_SCL_2_REG_END 0x00620bfc
-#define BCHP_SCL_3_REG_START 0x00620c00
-#define BCHP_SCL_3_REG_END 0x00620ffc
-#define BCHP_VNET_F_REG_START 0x00622000
-#define BCHP_VNET_F_REG_END 0x006221fc
-#define BCHP_VNET_B_REG_START 0x00622200
-#define BCHP_VNET_B_REG_END 0x006223fc
-#define BCHP_MMISC_REG_START 0x00622800
-#define BCHP_MMISC_REG_END 0x00622828
-#define BCHP_LBOX_0_REG_START 0x00624000
-#define BCHP_LBOX_0_REG_END 0x00624070
-#define BCHP_LBOX_1_REG_START 0x00624200
-#define BCHP_LBOX_1_REG_END 0x00624270
-#define BCHP_DNR_0_REG_START 0x00626000
-#define BCHP_DNR_0_REG_END 0x006260a4
-#define BCHP_DNR_1_REG_START 0x00626200
-#define BCHP_DNR_1_REG_END 0x006262a4
-#define BCHP_BVNM_INTR2_0_REG_START 0x00627000
-#define BCHP_BVNM_INTR2_0_REG_END 0x0062702c
-#define BCHP_DMISC_REG_START 0x00640000
-#define BCHP_DMISC_REG_END 0x0064001c
-#define BCHP_MVP_TOP_0_REG_START 0x00644000
-#define BCHP_MVP_TOP_0_REG_END 0x0064402c
-#define BCHP_SIOB_0_REG_START 0x00644200
-#define BCHP_SIOB_0_REG_END 0x006442fc
-#define BCHP_HSCL_0_REG_START 0x00644400
-#define BCHP_HSCL_0_REG_END 0x006447fc
-#define BCHP_HD_ANR_MCTF_0_REG_START 0x00645000
-#define BCHP_HD_ANR_MCTF_0_REG_END 0x0064527c
-#define BCHP_HD_ANR_AND_0_REG_START 0x00645800
-#define BCHP_HD_ANR_AND_0_REG_END 0x00645888
-#define BCHP_MDI_TOP_0_REG_START 0x00646000
-#define BCHP_MDI_TOP_0_REG_END 0x006460fc
-#define BCHP_MDI_FCB_0_REG_START 0x00646400
-#define BCHP_MDI_FCB_0_REG_END 0x006467fc
-#define BCHP_MDI_PPB_0_REG_START 0x00646800
-#define BCHP_MDI_PPB_0_REG_END 0x00646bfc
-#define BCHP_MDI_FCN_0_REG_START 0x00646c00
-#define BCHP_MDI_FCN_0_REG_END 0x00646ffc
-#define BCHP_MVP_TOP_1_REG_START 0x00650000
-#define BCHP_MVP_TOP_1_REG_END 0x0065002c
-#define BCHP_SIOB_1_REG_START 0x00650200
-#define BCHP_SIOB_1_REG_END 0x006502fc
-#define BCHP_HSCL_1_REG_START 0x00650400
-#define BCHP_HSCL_1_REG_END 0x006507fc
-#define BCHP_MDI_TOP_1_REG_START 0x00652000
-#define BCHP_MDI_TOP_1_REG_END 0x006520fc
-#define BCHP_MDI_PPB_1_REG_START 0x00652800
-#define BCHP_MDI_PPB_1_REG_END 0x00652bfc
-#define BCHP_MDI_FCN_1_REG_START 0x00652c00
-#define BCHP_MDI_FCN_1_REG_END 0x00652ffc
-#define BCHP_CAP_0_REG_START 0x00680000
-#define BCHP_CAP_0_REG_END 0x0068007c
-#define BCHP_CAP_1_REG_START 0x00680200
-#define BCHP_CAP_1_REG_END 0x0068027c
-#define BCHP_CAP_2_REG_START 0x00680400
-#define BCHP_CAP_2_REG_END 0x0068047c
-#define BCHP_CAP_3_REG_START 0x00680600
-#define BCHP_CAP_3_REG_END 0x0068067c
-#define BCHP_GFD_0_REG_START 0x00681000
-#define BCHP_GFD_0_REG_END 0x0068122c
-#define BCHP_GFD_1_REG_START 0x00681400
-#define BCHP_GFD_1_REG_END 0x0068162c
-#define BCHP_GFD_2_REG_START 0x00681800
-#define BCHP_GFD_2_REG_END 0x00681a2c
-#define BCHP_CMP_0_REG_START 0x00683000
-#define BCHP_CMP_0_REG_END 0x006834b4
-#define BCHP_CMP_1_REG_START 0x00683800
-#define BCHP_CMP_1_REG_END 0x00683cb4
-#define BCHP_CMP_2_REG_START 0x00684000
-#define BCHP_CMP_2_REG_END 0x00684264
-#define BCHP_TNT_CMP_0_V0_REG_START 0x00685800
-#define BCHP_TNT_CMP_0_V0_REG_END 0x006858a4
-#define BCHP_MASK_0_REG_START 0x00685c00
-#define BCHP_MASK_0_REG_END 0x00685c20
-#define BCHP_PEP_CMP_0_V0_REG_START 0x00686000
-#define BCHP_PEP_CMP_0_V0_REG_END 0x00687484
-#define BCHP_TNT_CMP_1_V0_REG_START 0x00687600
-#define BCHP_TNT_CMP_1_V0_REG_END 0x006876a4
-#define BCHP_MASK_1_REG_START 0x00687800
-#define BCHP_MASK_1_REG_END 0x00687820
-#define BCHP_BVNB_INTR2_REG_START 0x00688000
-#define BCHP_BVNB_INTR2_REG_END 0x0068802c
-#define BCHP_BMISC_REG_START 0x00688400
-#define BCHP_BMISC_REG_END 0x0068841c
-#define BCHP_MISC_REG_START 0x006a0000
-#define BCHP_MISC_REG_END 0x006a0094
-#define BCHP_IT_0_REG_START 0x006a1000
-#define BCHP_IT_0_REG_END 0x006a17fc
-#define BCHP_IT_1_REG_START 0x006a2000
-#define BCHP_IT_1_REG_END 0x006a27fc
-#define BCHP_VF_0_REG_START 0x006a3000
-#define BCHP_VF_0_REG_END 0x006a3134
-#define BCHP_SECAM_0_REG_START 0x006a3200
-#define BCHP_SECAM_0_REG_END 0x006a3214
-#define BCHP_SM_0_REG_START 0x006a3280
-#define BCHP_SM_0_REG_END 0x006a32ac
-#define BCHP_SDSRC_0_REG_START 0x006a3300
-#define BCHP_SDSRC_0_REG_END 0x006a330c
-#define BCHP_CSC_0_REG_START 0x006a3380
-#define BCHP_CSC_0_REG_END 0x006a33b0
-#define BCHP_RM_0_REG_START 0x006a3400
-#define BCHP_RM_0_REG_END 0x006a3424
-#define BCHP_RM_1_REG_START 0x006a3440
-#define BCHP_RM_1_REG_END 0x006a3464
-#define BCHP_ANA_DEBUG_0_REG_START 0x006a3500
-#define BCHP_ANA_DEBUG_0_REG_END 0x006a3544
-#define BCHP_DVI_DTG_0_REG_START 0x006a3800
-#define BCHP_DVI_DTG_0_REG_END 0x006a3c88
-#define BCHP_DVI_DTG_RM_0_REG_START 0x006a4000
-#define BCHP_DVI_DTG_RM_0_REG_END 0x006a4024
-#define BCHP_DVI_CSC_0_REG_START 0x006a4100
-#define BCHP_DVI_CSC_0_REG_END 0x006a4130
-#define BCHP_DVI_DVF_0_REG_START 0x006a4200
-#define BCHP_DVI_DVF_0_REG_END 0x006a4218
-#define BCHP_DVI_DEBUG_0_REG_START 0x006a4300
-#define BCHP_DVI_DEBUG_0_REG_END 0x006a4344
-#define BCHP_DVI_DTG_1_REG_START 0x006a4800
-#define BCHP_DVI_DTG_1_REG_END 0x006a4c88
-#define BCHP_DVI_DTG_RM_1_REG_START 0x006a5000
-#define BCHP_DVI_DTG_RM_1_REG_END 0x006a5024
-#define BCHP_DVI_CSC_1_REG_START 0x006a5100
-#define BCHP_DVI_CSC_1_REG_END 0x006a5130
-#define BCHP_DVI_DVF_1_REG_START 0x006a5200
-#define BCHP_DVI_DVF_1_REG_END 0x006a5218
-#define BCHP_DVI_DEBUG_1_REG_START 0x006a5300
-#define BCHP_DVI_DEBUG_1_REG_END 0x006a5344
-#define BCHP_ITU656_DTG_0_REG_START 0x006a5800
-#define BCHP_ITU656_DTG_0_REG_END 0x006a5c88
-#define BCHP_ITU656_CSC_0_REG_START 0x006a5e00
-#define BCHP_ITU656_CSC_0_REG_END 0x006a5e30
-#define BCHP_ITU656_DVF_0_REG_START 0x006a5f00
-#define BCHP_ITU656_DVF_0_REG_END 0x006a5f18
-#define BCHP_ITU656_0_REG_START 0x006a6000
-#define BCHP_ITU656_0_REG_END 0x006a6020
-#define BCHP_VEC_CFG_REG_START 0x006a6400
-#define BCHP_VEC_CFG_REG_END 0x006a652c
-#define BCHP_VIDEO_ENC_INTR2_REG_START 0x006a6800
-#define BCHP_VIDEO_ENC_INTR2_REG_END 0x006a682c
-#define BCHP_VIDEO_ENC_TPG_0_REG_START 0x006a6a00
-#define BCHP_VIDEO_ENC_TPG_0_REG_END 0x006a6b20
-#define BCHP_VIDEO_ENC_STG_0_REG_START 0x006a6c00
-#define BCHP_VIDEO_ENC_STG_0_REG_END 0x006a6c48
-#define BCHP_VIDEO_ENC_STG_1_REG_START 0x006a6d00
-#define BCHP_VIDEO_ENC_STG_1_REG_END 0x006a6d48
-#define BCHP_DSCL_0_REG_START 0x006a7000
-#define BCHP_DSCL_0_REG_END 0x006a73fc
-#define BCHP_VIDEO_ENC_DECIM_0_REG_START 0x006a7800
-#define BCHP_VIDEO_ENC_DECIM_0_REG_END 0x006a7808
-#define BCHP_DVP_TVG_0_REG_START 0x006a7900
-#define BCHP_DVP_TVG_0_REG_END 0x006a7988
-#define BCHP_DVP_TVG_1_REG_START 0x006a7a00
-#define BCHP_DVP_TVG_1_REG_END 0x006a7a88
-#define BCHP_VBI_ENC_REG_START 0x006a8000
-#define BCHP_VBI_ENC_REG_END 0x006a8074
-#define BCHP_CCE_0_REG_START 0x006a8400
-#define BCHP_CCE_0_REG_END 0x006a8458
-#define BCHP_WSE_0_REG_START 0x006a8500
-#define BCHP_WSE_0_REG_END 0x006a8514
-#define BCHP_CGMSAE_0_REG_START 0x006a8600
-#define BCHP_CGMSAE_0_REG_END 0x006a8658
-#define BCHP_TTE_0_REG_START 0x006a8700
-#define BCHP_TTE_0_REG_END 0x006a8728
-#define BCHP_GSE_0_REG_START 0x006a8800
-#define BCHP_GSE_0_REG_END 0x006a8880
-#define BCHP_AMOLE_0_REG_START 0x006a8900
-#define BCHP_AMOLE_0_REG_END 0x006a898c
-#define BCHP_CCE_ANCIL_0_REG_START 0x006a8a00
-#define BCHP_CCE_ANCIL_0_REG_END 0x006a8a54
-#define BCHP_WSE_ANCIL_0_REG_START 0x006a8b00
-#define BCHP_WSE_ANCIL_0_REG_END 0x006a8b0c
-#define BCHP_TTE_ANCIL_0_REG_START 0x006a8c00
-#define BCHP_TTE_ANCIL_0_REG_END 0x006a8c28
-#define BCHP_GSE_ANCIL_0_REG_START 0x006a8d00
-#define BCHP_GSE_ANCIL_0_REG_END 0x006a8d80
-#define BCHP_AMOLE_ANCIL_0_REG_START 0x006a8e00
-#define BCHP_AMOLE_ANCIL_0_REG_END 0x006a8e8c
-#define BCHP_ANCI656_ANCIL_0_REG_START 0x006a8f00
-#define BCHP_ANCI656_ANCIL_0_REG_END 0x006a8f24
-#define BCHP_DVP_HR_REG_START 0x006b0000
-#define BCHP_DVP_HR_REG_END 0x006b03fc
-#define BCHP_DVP_HR_INTR2_REG_START 0x006b0400
-#define BCHP_DVP_HR_INTR2_REG_END 0x006b042c
-#define BCHP_DVP_HR_KEY_RAM_REG_START 0x006b0600
-#define BCHP_DVP_HR_KEY_RAM_REG_END 0x006b0614
-#define BCHP_HDMI_RX_FE_SHARED_REG_START 0x006b0800
-#define BCHP_HDMI_RX_FE_SHARED_REG_END 0x006b090c
-#define BCHP_HDMI_RX_SHARED_REG_START 0x006b0c00
-#define BCHP_HDMI_RX_SHARED_REG_END 0x006b0c24
-#define BCHP_HDMI_RX_FE_0_REG_START 0x006b1000
-#define BCHP_HDMI_RX_FE_0_REG_END 0x006b11fc
-#define BCHP_HDMI_RX_EQ_0_REG_START 0x006b1200
-#define BCHP_HDMI_RX_EQ_0_REG_END 0x006b13fc
-#define BCHP_HDMI_RX_0_REG_START 0x006b2000
-#define BCHP_HDMI_RX_0_REG_END 0x006b27bc
-#define BCHP_HDMI_RX_INTR2_0_REG_START 0x006b27c0
-#define BCHP_HDMI_RX_INTR2_0_REG_END 0x006b27ec
-#define BCHP_HD_DVI_0_REG_START 0x006b4000
-#define BCHP_HD_DVI_0_REG_END 0x006b41fc
-#define BCHP_DVP_HR_TMR_REG_START 0x006b4cc0
-#define BCHP_DVP_HR_TMR_REG_END 0x006b4cfc
-#define BCHP_DVP_HT_REG_START 0x006c0000
-#define BCHP_DVP_HT_REG_END 0x006c011c
-#define BCHP_HDMI_REG_START 0x006c0800
-#define BCHP_HDMI_REG_END 0x006c09ec
-#define BCHP_HDMI_TX_PHY_REG_START 0x006c0a80
-#define BCHP_HDMI_TX_PHY_REG_END 0x006c0aec
-#define BCHP_HDMI_RM_REG_START 0x006c0b00
-#define BCHP_HDMI_RM_REG_END 0x006c0b2c
-#define BCHP_HDMI_TX_INTR2_REG_START 0x006c0b40
-#define BCHP_HDMI_TX_INTR2_REG_END 0x006c0b6c
-#define BCHP_HDMI_RAM_REG_START 0x006c0c00
-#define BCHP_HDMI_RAM_REG_END 0x006c0dfc
-#define BCHP_DVP_HT_1_REG_START 0x006d0000
-#define BCHP_DVP_HT_1_REG_END 0x006d011c
-#define BCHP_HDMI_1_REG_START 0x006d0800
-#define BCHP_HDMI_1_REG_END 0x006d09ec
-#define BCHP_HDMI_TX_PHY_1_REG_START 0x006d0a80
-#define BCHP_HDMI_TX_PHY_1_REG_END 0x006d0aec
-#define BCHP_HDMI_RM_1_REG_START 0x006d0b00
-#define BCHP_HDMI_RM_1_REG_END 0x006d0b2c
-#define BCHP_HDMI_TX_INTR2_1_REG_START 0x006d0b40
-#define BCHP_HDMI_TX_INTR2_1_REG_END 0x006d0b6c
-#define BCHP_HDMI_RAM_1_REG_START 0x006d0c00
-#define BCHP_HDMI_RAM_1_REG_END 0x006d0dfc
-#define BCHP_BVN_RGR_REG_START 0x006e0000
-#define BCHP_BVN_RGR_REG_END 0x006e0010
-#define BCHP_VICE2_CME_0_0_REG_START 0x00700800
-#define BCHP_VICE2_CME_0_0_REG_END 0x007008a0
-#define BCHP_VICE2_FME_0_0_REG_START 0x00700c00
-#define BCHP_VICE2_FME_0_0_REG_END 0x00700c88
-#define BCHP_VICE2_MC_0_0_REG_START 0x00701000
-#define BCHP_VICE2_MC_0_0_REG_END 0x0070108c
-#define BCHP_VICE2_MAU_0_0_REG_START 0x00701400
-#define BCHP_VICE2_MAU_0_0_REG_END 0x00701510
-#define BCHP_VICE2_IMD_0_0_REG_START 0x00701800
-#define BCHP_VICE2_IMD_0_0_REG_END 0x0070187c
-#define BCHP_VICE2_CABAC_0_0_REG_START 0x00701c00
-#define BCHP_VICE2_CABAC_0_0_REG_END 0x00701dec
-#define BCHP_VICE2_HA_0_0_REG_START 0x00702000
-#define BCHP_VICE2_HA_0_0_REG_END 0x0070208c
-#define BCHP_VICE2_SG_0_0_REG_START 0x00702400
-#define BCHP_VICE2_SG_0_0_REG_END 0x007024ac
-#define BCHP_VICE2_DBLK_0_0_REG_START 0x00702800
-#define BCHP_VICE2_DBLK_0_0_REG_END 0x0070288c
-#define BCHP_VICE2_VIP_0_0_REG_START 0x00703000
-#define BCHP_VICE2_VIP_0_0_REG_END 0x00703224
-#define BCHP_VICE2_VIP1_0_0_REG_START 0x00703800
-#define BCHP_VICE2_VIP1_0_0_REG_END 0x00703a24
-#define BCHP_VICE2_XQ_0_0_REG_START 0x00704000
-#define BCHP_VICE2_XQ_0_0_REG_END 0x007054c8
-#define BCHP_VICE2_ARCSS_ESS_ADI_0_0_REG_START 0x00718000
-#define BCHP_VICE2_ARCSS_ESS_ADI_0_0_REG_END 0x007182b4
-#define BCHP_VICE2_ARCSS_ESS_CTRL_0_0_REG_START 0x00720000
-#define BCHP_VICE2_ARCSS_ESS_CTRL_0_0_REG_END 0x007200a4
-#define BCHP_VICE2_ARCSS_ESS_FLAG_INTR2_0_0_REG_START 0x00720400
-#define BCHP_VICE2_ARCSS_ESS_FLAG_INTR2_0_0_REG_END 0x0072042c
-#define BCHP_VICE2_ARCSS_ESS_P1_INTR2_0_0_REG_START 0x00720600
-#define BCHP_VICE2_ARCSS_ESS_P1_INTR2_0_0_REG_END 0x0072062c
-#define BCHP_VICE2_ARCSS_ESS_HOSTIF_0_0_REG_START 0x00722000
-#define BCHP_VICE2_ARCSS_ESS_HOSTIF_0_0_REG_END 0x007233fc
-#define BCHP_VICE2_ARCSS_ESS_DCCM_0_0_REG_START 0x00730000
-#define BCHP_VICE2_ARCSS_ESS_DCCM_0_0_REG_END 0x0073fffc
-#define BCHP_VICE2_ARCSS_ESS_ADI_1_0_REG_START 0x00758000
-#define BCHP_VICE2_ARCSS_ESS_ADI_1_0_REG_END 0x007582a8
-#define BCHP_VICE2_ARCSS_ESS_CTRL_1_0_REG_START 0x00760000
-#define BCHP_VICE2_ARCSS_ESS_CTRL_1_0_REG_END 0x007600a4
-#define BCHP_VICE2_ARCSS_ESS_FLAG_INTR2_1_0_REG_START 0x00760400
-#define BCHP_VICE2_ARCSS_ESS_FLAG_INTR2_1_0_REG_END 0x0076042c
-#define BCHP_VICE2_ARCSS_ESS_P1_INTR2_1_0_REG_START 0x00760600
-#define BCHP_VICE2_ARCSS_ESS_P1_INTR2_1_0_REG_END 0x0076062c
-#define BCHP_VICE2_ARCSS_ESS_HOSTIF_1_0_REG_START 0x00762000
-#define BCHP_VICE2_ARCSS_ESS_HOSTIF_1_0_REG_END 0x007633fc
-#define BCHP_VICE2_ARCSS_ESS_DCCM_1_0_REG_START 0x00770000
-#define BCHP_VICE2_ARCSS_ESS_DCCM_1_0_REG_END 0x0077fffc
-#define BCHP_VICE2_RGR_0_REG_START 0x00780000
-#define BCHP_VICE2_RGR_0_REG_END 0x0078000c
-#define BCHP_VICE2_MISC_0_REG_START 0x00781000
-#define BCHP_VICE2_MISC_0_REG_END 0x00781030
-#define BCHP_VICE2_L2_0_REG_START 0x00781100
-#define BCHP_VICE2_L2_0_REG_END 0x0078112c
-#define BCHP_VICE2_ARCSS_MISC_0_REG_START 0x00782000
-#define BCHP_VICE2_ARCSS_MISC_0_REG_END 0x007820b8
-#define BCHP_VICE2_SEC_CTRL_0_REG_START 0x00800000
-#define BCHP_VICE2_SEC_CTRL_0_REG_END 0x00800080
-#define BCHP_MEMC_GEN_0_REG_START 0x00900000
-#define BCHP_MEMC_GEN_0_REG_END 0x009005fc
-#define BCHP_MEMC_EDIS_0_0_REG_START 0x00900800
-#define BCHP_MEMC_EDIS_0_0_REG_END 0x009008fc
-#define BCHP_MEMC_EDIS_0_1_REG_START 0x00900a00
-#define BCHP_MEMC_EDIS_0_1_REG_END 0x00900afc
-#define BCHP_MEMC_ARC_0_REG_START 0x00900c00
-#define BCHP_MEMC_ARC_0_REG_END 0x00900f74
-#define BCHP_MEMC_ARB_0_REG_START 0x00901000
-#define BCHP_MEMC_ARB_0_REG_END 0x009014a8
-#define BCHP_MEMC_DDR_0_REG_START 0x00902000
-#define BCHP_MEMC_DDR_0_REG_END 0x009027fc
-#define BCHP_MEMC_L2_0_0_REG_START 0x00903000
-#define BCHP_MEMC_L2_0_0_REG_END 0x00903044
-#define BCHP_MEMC_L2_0_1_REG_START 0x00903200
-#define BCHP_MEMC_L2_0_1_REG_END 0x00903244
-#define BCHP_MEMC_L2_0_2_REG_START 0x00903400
-#define BCHP_MEMC_L2_0_2_REG_END 0x00903444
-#define BCHP_MEMC_TRACELOG_0_0_REG_START 0x00903800
-#define BCHP_MEMC_TRACELOG_0_0_REG_END 0x009039fc
-#define BCHP_MEMC_RGRB_0_REG_START 0x00904000
-#define BCHP_MEMC_RGRB_0_REG_END 0x00904010
-#define BCHP_MEMC_MISC_0_REG_START 0x00905000
-#define BCHP_MEMC_MISC_0_REG_END 0x00905010
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_REG_START 0x00906000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_REG_END 0x00906248
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_REG_START 0x00906400
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_REG_END 0x00906514
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_REG_START 0x00906600
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_REG_END 0x00906714
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_REG_START 0x00906800
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_REG_END 0x00906914
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_REG_START 0x00906a00
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_REG_END 0x00906b14
-#define BCHP_DDR34_PHY_ECC_LANE_0_REG_START 0x00906c00
-#define BCHP_DDR34_PHY_ECC_LANE_0_REG_END 0x00906d14
-#define BCHP_SHIMPHY_ADDR_CNTL_0_REG_START 0x00908000
-#define BCHP_SHIMPHY_ADDR_CNTL_0_REG_END 0x009080b4
-#define BCHP_MEMC_SENTINEL_0_0_REG_START 0x00940000
-#define BCHP_MEMC_SENTINEL_0_0_REG_END 0x0097fffc
-#define BCHP_S_MEMC_0_REG_START 0x00980000
-#define BCHP_S_MEMC_0_REG_END 0x00980780
-#define BCHP_XPT_BUS_IF_SUB_MODULE_SOFT_INIT_DONE_INTR2_REG_START 0x00a00000
-#define BCHP_XPT_BUS_IF_SUB_MODULE_SOFT_INIT_DONE_INTR2_REG_END 0x00a0002c
-#define BCHP_XPT_BUS_IF_REG_START 0x00a00080
-#define BCHP_XPT_BUS_IF_REG_END 0x00a000fc
-#define BCHP_XPT_XMEMIF_REG_START 0x00a00100
-#define BCHP_XPT_XMEMIF_REG_END 0x00a001fc
-#define BCHP_XPT_PMU_REG_START 0x00a00200
-#define BCHP_XPT_PMU_REG_END 0x00a00218
-#define BCHP_XPT_GR_REG_START 0x00a00300
-#define BCHP_XPT_GR_REG_END 0x00a0030c
-#define BCHP_XPT_RMX0_IO_REG_START 0x00a00400
-#define BCHP_XPT_RMX0_IO_REG_END 0x00a00420
-#define BCHP_XPT_RMX1_IO_REG_START 0x00a00500
-#define BCHP_XPT_RMX1_IO_REG_END 0x00a00520
-#define BCHP_XPT_WAKEUP_REG_START 0x00a01000
-#define BCHP_XPT_WAKEUP_REG_END 0x00a01fbc
-#define BCHP_XPT_DPCR0_REG_START 0x00a02000
-#define BCHP_XPT_DPCR0_REG_END 0x00a02074
-#define BCHP_XPT_DPCR1_REG_START 0x00a02080
-#define BCHP_XPT_DPCR1_REG_END 0x00a020f4
-#define BCHP_XPT_DPCR2_REG_START 0x00a02100
-#define BCHP_XPT_DPCR2_REG_END 0x00a02174
-#define BCHP_XPT_DPCR3_REG_START 0x00a02180
-#define BCHP_XPT_DPCR3_REG_END 0x00a021f4
-#define BCHP_XPT_DPCR4_REG_START 0x00a02200
-#define BCHP_XPT_DPCR4_REG_END 0x00a02274
-#define BCHP_XPT_DPCR5_REG_START 0x00a02280
-#define BCHP_XPT_DPCR5_REG_END 0x00a022f4
-#define BCHP_XPT_DPCR6_REG_START 0x00a02300
-#define BCHP_XPT_DPCR6_REG_END 0x00a02374
-#define BCHP_XPT_DPCR7_REG_START 0x00a02380
-#define BCHP_XPT_DPCR7_REG_END 0x00a023f4
-#define BCHP_XPT_DPCR8_REG_START 0x00a02400
-#define BCHP_XPT_DPCR8_REG_END 0x00a02474
-#define BCHP_XPT_DPCR9_REG_START 0x00a02480
-#define BCHP_XPT_DPCR9_REG_END 0x00a024f4
-#define BCHP_XPT_DPCR10_REG_START 0x00a02500
-#define BCHP_XPT_DPCR10_REG_END 0x00a02574
-#define BCHP_XPT_DPCR11_REG_START 0x00a02580
-#define BCHP_XPT_DPCR11_REG_END 0x00a025f4
-#define BCHP_XPT_DPCR12_REG_START 0x00a02600
-#define BCHP_XPT_DPCR12_REG_END 0x00a02674
-#define BCHP_XPT_DPCR13_REG_START 0x00a02680
-#define BCHP_XPT_DPCR13_REG_END 0x00a026f4
-#define BCHP_XPT_DPCR_PP_REG_START 0x00a02800
-#define BCHP_XPT_DPCR_PP_REG_END 0x00a02804
-#define BCHP_XPT_PSUB_REG_START 0x00a02a00
-#define BCHP_XPT_PSUB_REG_END 0x00a02b88
-#define BCHP_XPT_MPOD_REG_START 0x00a02c00
-#define BCHP_XPT_MPOD_REG_END 0x00a02c20
-#define BCHP_XPT_RMX0_REG_START 0x00a02d00
-#define BCHP_XPT_RMX0_REG_END 0x00a02d08
-#define BCHP_XPT_RMX1_REG_START 0x00a02e00
-#define BCHP_XPT_RMX1_REG_END 0x00a02e08
-#define BCHP_XPT_RSBUFF_REG_START 0x00a03000
-#define BCHP_XPT_RSBUFF_REG_END 0x00a03e70
-#define BCHP_XPT_XCBUFF_REG_START 0x00a04000
-#define BCHP_XPT_XCBUFF_REG_END 0x00a05ce0
-#define BCHP_XPT_PCROFFSET_REG_START 0x00a08000
-#define BCHP_XPT_PCROFFSET_REG_END 0x00a0aafc
-#define BCHP_XPT_TSIO_CONFIG_REGISTERS_REG_START 0x00a0c000
-#define BCHP_XPT_TSIO_CONFIG_REGISTERS_REG_END 0x00a0ea04
-#define BCHP_XPT_TSIO_CALIB_REGISTERS_REG_START 0x00a0f000
-#define BCHP_XPT_TSIO_CALIB_REGISTERS_REG_END 0x00a0f9fc
-#define BCHP_XPT_TSIO_INTR_L2_REG_START 0x00a0fc00
-#define BCHP_XPT_TSIO_INTR_L2_REG_END 0x00a0fc2c
-#define BCHP_XPT_FULL_PID_PARSER_REG_START 0x00a10000
-#define BCHP_XPT_FULL_PID_PARSER_REG_END 0x00a14050
-#define BCHP_XPT_FE_REG_START 0x00a20000
-#define BCHP_XPT_FE_REG_END 0x00a25ffc
-#define BCHP_XPT_MSG_REG_START 0x00a30000
-#define BCHP_XPT_MSG_REG_END 0x00a3ca14
-#define BCHP_XPT_MSG_BUF_DAT_RDY_CPU_INTR_AGGREGATOR_REG_START 0x00a3fb00
-#define BCHP_XPT_MSG_BUF_DAT_RDY_CPU_INTR_AGGREGATOR_REG_END 0x00a3fb1c
-#define BCHP_XPT_MSG_BUF_OVFL_CPU_INTR_AGGREGATOR_REG_START 0x00a3fb20
-#define BCHP_XPT_MSG_BUF_OVFL_CPU_INTR_AGGREGATOR_REG_END 0x00a3fb3c
-#define BCHP_XPT_MSG_BUF_DAT_RDY_PCI_INTR_AGGREGATOR_REG_START 0x00a3fb40
-#define BCHP_XPT_MSG_BUF_DAT_RDY_PCI_INTR_AGGREGATOR_REG_END 0x00a3fb5c
-#define BCHP_XPT_MSG_BUF_OVFL_PCI_INTR_AGGREGATOR_REG_START 0x00a3fb60
-#define BCHP_XPT_MSG_BUF_OVFL_PCI_INTR_AGGREGATOR_REG_END 0x00a3fb7c
-#define BCHP_XPT_MSG_DAT_ERR_INTR_L2_REG_START 0x00a3fb80
-#define BCHP_XPT_MSG_DAT_ERR_INTR_L2_REG_END 0x00a3fbac
-#define BCHP_XPT_MSG_BUF_DAT_RDY_INTR_00_31_L2_REG_START 0x00a3fc00
-#define BCHP_XPT_MSG_BUF_DAT_RDY_INTR_00_31_L2_REG_END 0x00a3fc2c
-#define BCHP_XPT_MSG_BUF_DAT_RDY_INTR_32_63_L2_REG_START 0x00a3fc40
-#define BCHP_XPT_MSG_BUF_DAT_RDY_INTR_32_63_L2_REG_END 0x00a3fc6c
-#define BCHP_XPT_MSG_BUF_DAT_RDY_INTR_64_95_L2_REG_START 0x00a3fc80
-#define BCHP_XPT_MSG_BUF_DAT_RDY_INTR_64_95_L2_REG_END 0x00a3fcac
-#define BCHP_XPT_MSG_BUF_DAT_RDY_INTR_96_127_L2_REG_START 0x00a3fcc0
-#define BCHP_XPT_MSG_BUF_DAT_RDY_INTR_96_127_L2_REG_END 0x00a3fcec
-#define BCHP_XPT_MSG_BUF_DAT_RDY_INTR_128_159_L2_REG_START 0x00a3fd00
-#define BCHP_XPT_MSG_BUF_DAT_RDY_INTR_128_159_L2_REG_END 0x00a3fd2c
-#define BCHP_XPT_MSG_BUF_DAT_RDY_INTR_160_191_L2_REG_START 0x00a3fd40
-#define BCHP_XPT_MSG_BUF_DAT_RDY_INTR_160_191_L2_REG_END 0x00a3fd6c
-#define BCHP_XPT_MSG_BUF_DAT_RDY_INTR_192_223_L2_REG_START 0x00a3fd80
-#define BCHP_XPT_MSG_BUF_DAT_RDY_INTR_192_223_L2_REG_END 0x00a3fdac
-#define BCHP_XPT_MSG_BUF_DAT_RDY_INTR_224_255_L2_REG_START 0x00a3fdc0
-#define BCHP_XPT_MSG_BUF_DAT_RDY_INTR_224_255_L2_REG_END 0x00a3fdec
-#define BCHP_XPT_MSG_BUF_OVFL_INTR_00_31_L2_REG_START 0x00a3fe00
-#define BCHP_XPT_MSG_BUF_OVFL_INTR_00_31_L2_REG_END 0x00a3fe2c
-#define BCHP_XPT_MSG_BUF_OVFL_INTR_32_63_L2_REG_START 0x00a3fe40
-#define BCHP_XPT_MSG_BUF_OVFL_INTR_32_63_L2_REG_END 0x00a3fe6c
-#define BCHP_XPT_MSG_BUF_OVFL_INTR_64_95_L2_REG_START 0x00a3fe80
-#define BCHP_XPT_MSG_BUF_OVFL_INTR_64_95_L2_REG_END 0x00a3feac
-#define BCHP_XPT_MSG_BUF_OVFL_INTR_96_127_L2_REG_START 0x00a3fec0
-#define BCHP_XPT_MSG_BUF_OVFL_INTR_96_127_L2_REG_END 0x00a3feec
-#define BCHP_XPT_MSG_BUF_OVFL_INTR_128_159_L2_REG_START 0x00a3ff00
-#define BCHP_XPT_MSG_BUF_OVFL_INTR_128_159_L2_REG_END 0x00a3ff2c
-#define BCHP_XPT_MSG_BUF_OVFL_INTR_160_191_L2_REG_START 0x00a3ff40
-#define BCHP_XPT_MSG_BUF_OVFL_INTR_160_191_L2_REG_END 0x00a3ff6c
-#define BCHP_XPT_MSG_BUF_OVFL_INTR_192_223_L2_REG_START 0x00a3ff80
-#define BCHP_XPT_MSG_BUF_OVFL_INTR_192_223_L2_REG_END 0x00a3ffac
-#define BCHP_XPT_MSG_BUF_OVFL_INTR_224_255_L2_REG_START 0x00a3ffc0
-#define BCHP_XPT_MSG_BUF_OVFL_INTR_224_255_L2_REG_END 0x00a3ffec
-#define BCHP_XPT_RAVE_REG_START 0x00a40000
-#define BCHP_XPT_RAVE_REG_END 0x00a4d6f4
-#define BCHP_XPT_RAVE_CPU_INTR_AGGREGATOR_REG_START 0x00a4f000
-#define BCHP_XPT_RAVE_CPU_INTR_AGGREGATOR_REG_END 0x00a4f01c
-#define BCHP_XPT_RAVE_PCI_INTR_AGGREGATOR_REG_START 0x00a4f020
-#define BCHP_XPT_RAVE_PCI_INTR_AGGREGATOR_REG_END 0x00a4f03c
-#define BCHP_XPT_RAVE_MISC_L2_INTR_REG_START 0x00a4f040
-#define BCHP_XPT_RAVE_MISC_L2_INTR_REG_END 0x00a4f06c
-#define BCHP_XPT_RAVE_EMU_ERROR_CX00_31_L2_INTR_REG_START 0x00a4f080
-#define BCHP_XPT_RAVE_EMU_ERROR_CX00_31_L2_INTR_REG_END 0x00a4f0ac
-#define BCHP_XPT_RAVE_EMU_ERROR_CX32_47_L2_INTR_REG_START 0x00a4f0c0
-#define BCHP_XPT_RAVE_EMU_ERROR_CX32_47_L2_INTR_REG_END 0x00a4f0ec
-#define BCHP_XPT_RAVE_PUSI_ERROR_CX00_31_L2_INTR_REG_START 0x00a4f100
-#define BCHP_XPT_RAVE_PUSI_ERROR_CX00_31_L2_INTR_REG_END 0x00a4f12c
-#define BCHP_XPT_RAVE_PUSI_ERROR_CX32_47_L2_INTR_REG_START 0x00a4f140
-#define BCHP_XPT_RAVE_PUSI_ERROR_CX32_47_L2_INTR_REG_END 0x00a4f16c
-#define BCHP_XPT_RAVE_TEI_ERROR_CX00_31_L2_INTR_REG_START 0x00a4f180
-#define BCHP_XPT_RAVE_TEI_ERROR_CX00_31_L2_INTR_REG_END 0x00a4f1ac
-#define BCHP_XPT_RAVE_TEI_ERROR_CX32_47_L2_INTR_REG_START 0x00a4f1c0
-#define BCHP_XPT_RAVE_TEI_ERROR_CX32_47_L2_INTR_REG_END 0x00a4f1ec
-#define BCHP_XPT_RAVE_CC_ERROR_CX00_31_L2_INTR_REG_START 0x00a4f200
-#define BCHP_XPT_RAVE_CC_ERROR_CX00_31_L2_INTR_REG_END 0x00a4f22c
-#define BCHP_XPT_RAVE_CC_ERROR_CX32_47_L2_INTR_REG_START 0x00a4f240
-#define BCHP_XPT_RAVE_CC_ERROR_CX32_47_L2_INTR_REG_END 0x00a4f26c
-#define BCHP_XPT_RAVE_CDB_OVERFLOW_CX00_31_L2_INTR_REG_START 0x00a4f280
-#define BCHP_XPT_RAVE_CDB_OVERFLOW_CX00_31_L2_INTR_REG_END 0x00a4f2ac
-#define BCHP_XPT_RAVE_CDB_OVERFLOW_CX32_47_L2_INTR_REG_START 0x00a4f2c0
-#define BCHP_XPT_RAVE_CDB_OVERFLOW_CX32_47_L2_INTR_REG_END 0x00a4f2ec
-#define BCHP_XPT_RAVE_ITB_OVERFLOW_CX00_31_L2_INTR_REG_START 0x00a4f300
-#define BCHP_XPT_RAVE_ITB_OVERFLOW_CX00_31_L2_INTR_REG_END 0x00a4f32c
-#define BCHP_XPT_RAVE_ITB_OVERFLOW_CX32_47_L2_INTR_REG_START 0x00a4f340
-#define BCHP_XPT_RAVE_ITB_OVERFLOW_CX32_47_L2_INTR_REG_END 0x00a4f36c
-#define BCHP_XPT_RAVE_SPLICE_CX00_31_L2_INTR_REG_START 0x00a4f380
-#define BCHP_XPT_RAVE_SPLICE_CX00_31_L2_INTR_REG_END 0x00a4f3ac
-#define BCHP_XPT_RAVE_SPLICE_CX32_47_L2_INTR_REG_START 0x00a4f3c0
-#define BCHP_XPT_RAVE_SPLICE_CX32_47_L2_INTR_REG_END 0x00a4f3ec
-#define BCHP_XPT_RAVE_LAST_CMD_CX00_31_L2_INTR_REG_START 0x00a4f400
-#define BCHP_XPT_RAVE_LAST_CMD_CX00_31_L2_INTR_REG_END 0x00a4f42c
-#define BCHP_XPT_RAVE_LAST_CMD_CX32_47_L2_INTR_REG_START 0x00a4f440
-#define BCHP_XPT_RAVE_LAST_CMD_CX32_47_L2_INTR_REG_END 0x00a4f46c
-#define BCHP_XPT_RAVE_CDB_LOWER_THRESH_CX00_31_L2_INTR_REG_START 0x00a4f480
-#define BCHP_XPT_RAVE_CDB_LOWER_THRESH_CX00_31_L2_INTR_REG_END 0x00a4f4ac
-#define BCHP_XPT_RAVE_CDB_LOWER_THRESH_CX32_47_L2_INTR_REG_START 0x00a4f4c0
-#define BCHP_XPT_RAVE_CDB_LOWER_THRESH_CX32_47_L2_INTR_REG_END 0x00a4f4ec
-#define BCHP_XPT_RAVE_CDB_UPPER_THRESH_CX00_31_L2_INTR_REG_START 0x00a4f500
-#define BCHP_XPT_RAVE_CDB_UPPER_THRESH_CX00_31_L2_INTR_REG_END 0x00a4f52c
-#define BCHP_XPT_RAVE_CDB_UPPER_THRESH_CX32_47_L2_INTR_REG_START 0x00a4f540
-#define BCHP_XPT_RAVE_CDB_UPPER_THRESH_CX32_47_L2_INTR_REG_END 0x00a4f56c
-#define BCHP_XPT_RAVE_ITB_LOWER_THRESH_CX00_31_L2_INTR_REG_START 0x00a4f580
-#define BCHP_XPT_RAVE_ITB_LOWER_THRESH_CX00_31_L2_INTR_REG_END 0x00a4f5ac
-#define BCHP_XPT_RAVE_ITB_LOWER_THRESH_CX32_47_L2_INTR_REG_START 0x00a4f5c0
-#define BCHP_XPT_RAVE_ITB_LOWER_THRESH_CX32_47_L2_INTR_REG_END 0x00a4f5ec
-#define BCHP_XPT_RAVE_ITB_UPPER_THRESH_CX00_31_L2_INTR_REG_START 0x00a4f600
-#define BCHP_XPT_RAVE_ITB_UPPER_THRESH_CX00_31_L2_INTR_REG_END 0x00a4f62c
-#define BCHP_XPT_RAVE_ITB_UPPER_THRESH_CX32_47_L2_INTR_REG_START 0x00a4f640
-#define BCHP_XPT_RAVE_ITB_UPPER_THRESH_CX32_47_L2_INTR_REG_END 0x00a4f66c
-#define BCHP_XPT_RAVE_CDB_MIN_DEPTH_THRESH_CX00_31_L2_INTR_REG_START 0x00a4f680
-#define BCHP_XPT_RAVE_CDB_MIN_DEPTH_THRESH_CX00_31_L2_INTR_REG_END 0x00a4f6ac
-#define BCHP_XPT_RAVE_CDB_MIN_DEPTH_THRESH_CX32_47_L2_INTR_REG_START 0x00a4f6c0
-#define BCHP_XPT_RAVE_CDB_MIN_DEPTH_THRESH_CX32_47_L2_INTR_REG_END 0x00a4f6ec
-#define BCHP_XPT_RAVE_ITB_MIN_DEPTH_THRESH_CX00_31_L2_INTR_REG_START 0x00a4f700
-#define BCHP_XPT_RAVE_ITB_MIN_DEPTH_THRESH_CX00_31_L2_INTR_REG_END 0x00a4f72c
-#define BCHP_XPT_RAVE_ITB_MIN_DEPTH_THRESH_CX32_47_L2_INTR_REG_START 0x00a4f740
-#define BCHP_XPT_RAVE_ITB_MIN_DEPTH_THRESH_CX32_47_L2_INTR_REG_END 0x00a4f76c
-#define BCHP_XPT_RAVE_TSIO_DMA_END_CX00_31_L2_INTR_REG_START 0x00a4f780
-#define BCHP_XPT_RAVE_TSIO_DMA_END_CX00_31_L2_INTR_REG_END 0x00a4f7ac
-#define BCHP_XPT_RAVE_TSIO_DMA_END_CX32_47_L2_INTR_REG_START 0x00a4f7c0
-#define BCHP_XPT_RAVE_TSIO_DMA_END_CX32_47_L2_INTR_REG_END 0x00a4f7ec
-#define BCHP_XPT_RAVE_FW_GENERIC_1_CX00_31_L2_INTR_REG_START 0x00a4f800
-#define BCHP_XPT_RAVE_FW_GENERIC_1_CX00_31_L2_INTR_REG_END 0x00a4f82c
-#define BCHP_XPT_RAVE_FW_GENERIC_1_CX32_47_L2_INTR_REG_START 0x00a4f840
-#define BCHP_XPT_RAVE_FW_GENERIC_1_CX32_47_L2_INTR_REG_END 0x00a4f86c
-#define BCHP_XPT_RAVE_TO_SCPU_L2_INTR_0_31_REG_START 0x00a4ff80
-#define BCHP_XPT_RAVE_TO_SCPU_L2_INTR_0_31_REG_END 0x00a4ffac
-#define BCHP_XPT_RAVE_TO_SCPU_L2_INTR_32_47_REG_START 0x00a4ffc0
-#define BCHP_XPT_RAVE_TO_SCPU_L2_INTR_32_47_REG_END 0x00a4ffec
-#define BCHP_XPT_MEMDMA_MCPB_CPU_INTR_AGGREGATOR_REG_START 0x00a60000
-#define BCHP_XPT_MEMDMA_MCPB_CPU_INTR_AGGREGATOR_REG_END 0x00a6001c
-#define BCHP_XPT_MEMDMA_MCPB_PCI_INTR_AGGREGATOR_REG_START 0x00a60020
-#define BCHP_XPT_MEMDMA_MCPB_PCI_INTR_AGGREGATOR_REG_END 0x00a6003c
-#define BCHP_XPT_MEMDMA_MCPB_DESC_DONE_INTR_L2_REG_START 0x00a60040
-#define BCHP_XPT_MEMDMA_MCPB_DESC_DONE_INTR_L2_REG_END 0x00a6006c
-#define BCHP_XPT_MEMDMA_MCPB_MISC_FALSE_WAKE_INTR_L2_REG_START 0x00a60080
-#define BCHP_XPT_MEMDMA_MCPB_MISC_FALSE_WAKE_INTR_L2_REG_END 0x00a600ac
-#define BCHP_XPT_MEMDMA_MCPB_MISC_OOS_INTR_L2_REG_START 0x00a600c0
-#define BCHP_XPT_MEMDMA_MCPB_MISC_OOS_INTR_L2_REG_END 0x00a600ec
-#define BCHP_XPT_MEMDMA_MCPB_MISC_TS_PARITY_ERR_INTR_L2_REG_START 0x00a60100
-#define BCHP_XPT_MEMDMA_MCPB_MISC_TS_PARITY_ERR_INTR_L2_REG_END 0x00a6012c
-#define BCHP_XPT_MEMDMA_MCPB_MISC_TEI_INTR_L2_REG_START 0x00a60140
-#define BCHP_XPT_MEMDMA_MCPB_MISC_TEI_INTR_L2_REG_END 0x00a6016c
-#define BCHP_XPT_MEMDMA_MCPB_MISC_ASF_LEN_ERR_INTR_L2_REG_START 0x00a60180
-#define BCHP_XPT_MEMDMA_MCPB_MISC_ASF_LEN_ERR_INTR_L2_REG_END 0x00a601ac
-#define BCHP_XPT_MEMDMA_MCPB_MISC_ASF_FATAL_ERR_INTR_L2_REG_START 0x00a601c0
-#define BCHP_XPT_MEMDMA_MCPB_MISC_ASF_FATAL_ERR_INTR_L2_REG_END 0x00a601ec
-#define BCHP_XPT_MEMDMA_MCPB_MISC_ASF_COMPRESSED_DATA_RECEIVED_INTR_L2_REG_START 0x00a60200
-#define BCHP_XPT_MEMDMA_MCPB_MISC_ASF_COMPRESSED_DATA_RECEIVED_INTR_L2_REG_END 0x00a6022c
-#define BCHP_XPT_MEMDMA_MCPB_MISC_ASF_PROTOCOL_ERR_INTR_L2_REG_START 0x00a60240
-#define BCHP_XPT_MEMDMA_MCPB_MISC_ASF_PROTOCOL_ERR_INTR_L2_REG_END 0x00a6026c
-#define BCHP_XPT_MEMDMA_MCPB_MISC_ASF_PADDING_LEN_ERR_INTR_L2_REG_START 0x00a60280
-#define BCHP_XPT_MEMDMA_MCPB_MISC_ASF_PADDING_LEN_ERR_INTR_L2_REG_END 0x00a602ac
-#define BCHP_XPT_MEMDMA_MCPB_MISC_TS_RANGE_ERR_INTR_L2_REG_START 0x00a602c0
-#define BCHP_XPT_MEMDMA_MCPB_MISC_TS_RANGE_ERR_INTR_L2_REG_END 0x00a602ec
-#define BCHP_XPT_MEMDMA_MCPB_MISC_PES_NEXT_TS_RANGE_ERR_INTR_L2_REG_START 0x00a60300
-#define BCHP_XPT_MEMDMA_MCPB_MISC_PES_NEXT_TS_RANGE_ERR_INTR_L2_REG_END 0x00a6032c
-#define BCHP_XPT_MEMDMA_MCPB_MISC_PAUSE_AT_DESC_READ_INTR_L2_REG_START 0x00a60340
-#define BCHP_XPT_MEMDMA_MCPB_MISC_PAUSE_AT_DESC_READ_INTR_L2_REG_END 0x00a6036c
-#define BCHP_XPT_MEMDMA_MCPB_MISC_PAUSE_AT_DESC_END_INTR_L2_REG_START 0x00a60380
-#define BCHP_XPT_MEMDMA_MCPB_MISC_PAUSE_AT_DESC_END_INTR_L2_REG_END 0x00a603ac
-#define BCHP_XPT_MEMDMA_MCPB_MISC_PAUSE_AFTER_GROUP_PACKETS_INTR_L2_REG_START 0x00a603c0
-#define BCHP_XPT_MEMDMA_MCPB_MISC_PAUSE_AFTER_GROUP_PACKETS_INTR_L2_REG_END 0x00a603ec
-#define BCHP_XPT_MEMDMA_MCPB_MISC_DESC_TAGID_MISMATCH_INTR_L2_REG_START 0x00a60400
-#define BCHP_XPT_MEMDMA_MCPB_MISC_DESC_TAGID_MISMATCH_INTR_L2_REG_END 0x00a6042c
-#define BCHP_XPT_MEMDMA_MCPB_MISC_DATA_TAGID_MISMATCH_INTR_L2_REG_START 0x00a60440
-#define BCHP_XPT_MEMDMA_MCPB_MISC_DATA_TAGID_MISMATCH_INTR_L2_REG_END 0x00a6046c
-#define BCHP_XPT_MEMDMA_MCPB_MISC_CRC_COMPARE_ERROR_INTR_L2_REG_START 0x00a60480
-#define BCHP_XPT_MEMDMA_MCPB_MISC_CRC_COMPARE_ERROR_INTR_L2_REG_END 0x00a604ac
-#define BCHP_XPT_MEMDMA_MCPB_REG_START 0x00a60800
-#define BCHP_XPT_MEMDMA_MCPB_REG_END 0x00a60b80
-#define BCHP_XPT_MEMDMA_MCPB_CH0_REG_START 0x00a60c00
-#define BCHP_XPT_MEMDMA_MCPB_CH0_REG_END 0x00a60d54
-#define BCHP_XPT_MEMDMA_MCPB_CH1_REG_START 0x00a60e00
-#define BCHP_XPT_MEMDMA_MCPB_CH1_REG_END 0x00a60f54
-#define BCHP_XPT_MEMDMA_MCPB_CH2_REG_START 0x00a61000
-#define BCHP_XPT_MEMDMA_MCPB_CH2_REG_END 0x00a61154
-#define BCHP_XPT_MEMDMA_MCPB_CH3_REG_START 0x00a61200
-#define BCHP_XPT_MEMDMA_MCPB_CH3_REG_END 0x00a61354
-#define BCHP_XPT_MEMDMA_MCPB_CH4_REG_START 0x00a61400
-#define BCHP_XPT_MEMDMA_MCPB_CH4_REG_END 0x00a61554
-#define BCHP_XPT_MEMDMA_MCPB_CH5_REG_START 0x00a61600
-#define BCHP_XPT_MEMDMA_MCPB_CH5_REG_END 0x00a61754
-#define BCHP_XPT_MEMDMA_MCPB_CH6_REG_START 0x00a61800
-#define BCHP_XPT_MEMDMA_MCPB_CH6_REG_END 0x00a61954
-#define BCHP_XPT_MEMDMA_MCPB_CH7_REG_START 0x00a61a00
-#define BCHP_XPT_MEMDMA_MCPB_CH7_REG_END 0x00a61b54
-#define BCHP_XPT_MEMDMA_MCPB_CH8_REG_START 0x00a61c00
-#define BCHP_XPT_MEMDMA_MCPB_CH8_REG_END 0x00a61d54
-#define BCHP_XPT_MEMDMA_MCPB_CH9_REG_START 0x00a61e00
-#define BCHP_XPT_MEMDMA_MCPB_CH9_REG_END 0x00a61f54
-#define BCHP_XPT_MEMDMA_MCPB_CH10_REG_START 0x00a62000
-#define BCHP_XPT_MEMDMA_MCPB_CH10_REG_END 0x00a62154
-#define BCHP_XPT_MEMDMA_MCPB_CH11_REG_START 0x00a62200
-#define BCHP_XPT_MEMDMA_MCPB_CH11_REG_END 0x00a62354
-#define BCHP_XPT_MEMDMA_MCPB_CH12_REG_START 0x00a62400
-#define BCHP_XPT_MEMDMA_MCPB_CH12_REG_END 0x00a62554
-#define BCHP_XPT_MEMDMA_MCPB_CH13_REG_START 0x00a62600
-#define BCHP_XPT_MEMDMA_MCPB_CH13_REG_END 0x00a62754
-#define BCHP_XPT_MEMDMA_MCPB_CH14_REG_START 0x00a62800
-#define BCHP_XPT_MEMDMA_MCPB_CH14_REG_END 0x00a62954
-#define BCHP_XPT_MEMDMA_MCPB_CH15_REG_START 0x00a62a00
-#define BCHP_XPT_MEMDMA_MCPB_CH15_REG_END 0x00a62b54
-#define BCHP_XPT_MEMDMA_MCPB_CH16_REG_START 0x00a62c00
-#define BCHP_XPT_MEMDMA_MCPB_CH16_REG_END 0x00a62d54
-#define BCHP_XPT_MEMDMA_MCPB_CH17_REG_START 0x00a62e00
-#define BCHP_XPT_MEMDMA_MCPB_CH17_REG_END 0x00a62f54
-#define BCHP_XPT_MEMDMA_MCPB_CH18_REG_START 0x00a63000
-#define BCHP_XPT_MEMDMA_MCPB_CH18_REG_END 0x00a63154
-#define BCHP_XPT_MEMDMA_MCPB_CH19_REG_START 0x00a63200
-#define BCHP_XPT_MEMDMA_MCPB_CH19_REG_END 0x00a63354
-#define BCHP_XPT_MEMDMA_MCPB_CH20_REG_START 0x00a63400
-#define BCHP_XPT_MEMDMA_MCPB_CH20_REG_END 0x00a63554
-#define BCHP_XPT_MEMDMA_MCPB_CH21_REG_START 0x00a63600
-#define BCHP_XPT_MEMDMA_MCPB_CH21_REG_END 0x00a63754
-#define BCHP_XPT_MEMDMA_MCPB_CH22_REG_START 0x00a63800
-#define BCHP_XPT_MEMDMA_MCPB_CH22_REG_END 0x00a63954
-#define BCHP_XPT_MEMDMA_MCPB_CH23_REG_START 0x00a63a00
-#define BCHP_XPT_MEMDMA_MCPB_CH23_REG_END 0x00a63b54
-#define BCHP_XPT_MEMDMA_MCPB_CH24_REG_START 0x00a63c00
-#define BCHP_XPT_MEMDMA_MCPB_CH24_REG_END 0x00a63d54
-#define BCHP_XPT_MEMDMA_MCPB_CH25_REG_START 0x00a63e00
-#define BCHP_XPT_MEMDMA_MCPB_CH25_REG_END 0x00a63f54
-#define BCHP_XPT_MEMDMA_MCPB_CH26_REG_START 0x00a64000
-#define BCHP_XPT_MEMDMA_MCPB_CH26_REG_END 0x00a64154
-#define BCHP_XPT_MEMDMA_MCPB_CH27_REG_START 0x00a64200
-#define BCHP_XPT_MEMDMA_MCPB_CH27_REG_END 0x00a64354
-#define BCHP_XPT_MEMDMA_MCPB_CH28_REG_START 0x00a64400
-#define BCHP_XPT_MEMDMA_MCPB_CH28_REG_END 0x00a64554
-#define BCHP_XPT_MEMDMA_MCPB_CH29_REG_START 0x00a64600
-#define BCHP_XPT_MEMDMA_MCPB_CH29_REG_END 0x00a64754
-#define BCHP_XPT_MEMDMA_MCPB_CH30_REG_START 0x00a64800
-#define BCHP_XPT_MEMDMA_MCPB_CH30_REG_END 0x00a64954
-#define BCHP_XPT_MEMDMA_MCPB_CH31_REG_START 0x00a64a00
-#define BCHP_XPT_MEMDMA_MCPB_CH31_REG_END 0x00a64b54
-#define BCHP_XPT_WDMA_PCI_INTR_AGGREGATOR_REG_START 0x00a68000
-#define BCHP_XPT_WDMA_PCI_INTR_AGGREGATOR_REG_END 0x00a6801c
-#define BCHP_XPT_WDMA_CPU_INTR_AGGREGATOR_REG_START 0x00a68020
-#define BCHP_XPT_WDMA_CPU_INTR_AGGREGATOR_REG_END 0x00a6803c
-#define BCHP_XPT_WDMA_SCPU_INTR_AGGREGATOR_REG_START 0x00a68040
-#define BCHP_XPT_WDMA_SCPU_INTR_AGGREGATOR_REG_END 0x00a6805c
-#define BCHP_XPT_WDMA_BTP_INTR_L2_REG_START 0x00a68100
-#define BCHP_XPT_WDMA_BTP_INTR_L2_REG_END 0x00a68144
-#define BCHP_XPT_WDMA_OVERFLOW_INTR_L2_REG_START 0x00a68200
-#define BCHP_XPT_WDMA_OVERFLOW_INTR_L2_REG_END 0x00a68244
-#define BCHP_XPT_WDMA_DESC_DONE_INTR_L2_REG_START 0x00a68300
-#define BCHP_XPT_WDMA_DESC_DONE_INTR_L2_REG_END 0x00a68344
-#define BCHP_XPT_WDMA_PM_INTR_L2_REG_START 0x00a68400
-#define BCHP_XPT_WDMA_PM_INTR_L2_REG_END 0x00a68444
-#define BCHP_XPT_WDMA_PM_CONTROL_REG_START 0x00a68500
-#define BCHP_XPT_WDMA_PM_CONTROL_REG_END 0x00a68510
-#define BCHP_XPT_WDMA_PM_RESULTS_REG_START 0x00a68600
-#define BCHP_XPT_WDMA_PM_RESULTS_REG_END 0x00a68658
-#define BCHP_XPT_WDMA_REGS_REG_START 0x00a69000
-#define BCHP_XPT_WDMA_REGS_REG_END 0x00a69068
-#define BCHP_XPT_WDMA_RAMS_REG_START 0x00a6a000
-#define BCHP_XPT_WDMA_RAMS_REG_END 0x00a6bffc
-#define BCHP_XPT_MEMDMA_XMEMIF_REG_START 0x00a6ff00
-#define BCHP_XPT_MEMDMA_XMEMIF_REG_END 0x00a6fffc
-#define BCHP_XPT_MCPB_CPU_INTR_AGGREGATOR_REG_START 0x00a70000
-#define BCHP_XPT_MCPB_CPU_INTR_AGGREGATOR_REG_END 0x00a7001c
-#define BCHP_XPT_MCPB_PCI_INTR_AGGREGATOR_REG_START 0x00a70020
-#define BCHP_XPT_MCPB_PCI_INTR_AGGREGATOR_REG_END 0x00a7003c
-#define BCHP_XPT_MCPB_DESC_DONE_INTR_L2_REG_START 0x00a70040
-#define BCHP_XPT_MCPB_DESC_DONE_INTR_L2_REG_END 0x00a7006c
-#define BCHP_XPT_MCPB_MISC_FALSE_WAKE_INTR_L2_REG_START 0x00a70080
-#define BCHP_XPT_MCPB_MISC_FALSE_WAKE_INTR_L2_REG_END 0x00a700ac
-#define BCHP_XPT_MCPB_MISC_OOS_INTR_L2_REG_START 0x00a700c0
-#define BCHP_XPT_MCPB_MISC_OOS_INTR_L2_REG_END 0x00a700ec
-#define BCHP_XPT_MCPB_MISC_TS_PARITY_ERR_INTR_L2_REG_START 0x00a70100
-#define BCHP_XPT_MCPB_MISC_TS_PARITY_ERR_INTR_L2_REG_END 0x00a7012c
-#define BCHP_XPT_MCPB_MISC_TEI_INTR_L2_REG_START 0x00a70140
-#define BCHP_XPT_MCPB_MISC_TEI_INTR_L2_REG_END 0x00a7016c
-#define BCHP_XPT_MCPB_MISC_ASF_LEN_ERR_INTR_L2_REG_START 0x00a70180
-#define BCHP_XPT_MCPB_MISC_ASF_LEN_ERR_INTR_L2_REG_END 0x00a701ac
-#define BCHP_XPT_MCPB_MISC_ASF_FATAL_ERR_INTR_L2_REG_START 0x00a701c0
-#define BCHP_XPT_MCPB_MISC_ASF_FATAL_ERR_INTR_L2_REG_END 0x00a701ec
-#define BCHP_XPT_MCPB_MISC_ASF_COMPRESSED_DATA_RECEIVED_INTR_L2_REG_START 0x00a70200
-#define BCHP_XPT_MCPB_MISC_ASF_COMPRESSED_DATA_RECEIVED_INTR_L2_REG_END 0x00a7022c
-#define BCHP_XPT_MCPB_MISC_ASF_PROTOCOL_ERR_INTR_L2_REG_START 0x00a70240
-#define BCHP_XPT_MCPB_MISC_ASF_PROTOCOL_ERR_INTR_L2_REG_END 0x00a7026c
-#define BCHP_XPT_MCPB_MISC_ASF_PADDING_LEN_ERR_INTR_L2_REG_START 0x00a70280
-#define BCHP_XPT_MCPB_MISC_ASF_PADDING_LEN_ERR_INTR_L2_REG_END 0x00a702ac
-#define BCHP_XPT_MCPB_MISC_TS_RANGE_ERR_INTR_L2_REG_START 0x00a702c0
-#define BCHP_XPT_MCPB_MISC_TS_RANGE_ERR_INTR_L2_REG_END 0x00a702ec
-#define BCHP_XPT_MCPB_MISC_PES_NEXT_TS_RANGE_ERR_INTR_L2_REG_START 0x00a70300
-#define BCHP_XPT_MCPB_MISC_PES_NEXT_TS_RANGE_ERR_INTR_L2_REG_END 0x00a7032c
-#define BCHP_XPT_MCPB_MISC_PAUSE_AT_DESC_READ_INTR_L2_REG_START 0x00a70340
-#define BCHP_XPT_MCPB_MISC_PAUSE_AT_DESC_READ_INTR_L2_REG_END 0x00a7036c
-#define BCHP_XPT_MCPB_MISC_PAUSE_AT_DESC_END_INTR_L2_REG_START 0x00a70380
-#define BCHP_XPT_MCPB_MISC_PAUSE_AT_DESC_END_INTR_L2_REG_END 0x00a703ac
-#define BCHP_XPT_MCPB_MISC_PAUSE_AFTER_GROUP_PACKETS_INTR_L2_REG_START 0x00a703c0
-#define BCHP_XPT_MCPB_MISC_PAUSE_AFTER_GROUP_PACKETS_INTR_L2_REG_END 0x00a703ec
-#define BCHP_XPT_MCPB_MISC_DESC_TAGID_MISMATCH_INTR_L2_REG_START 0x00a70400
-#define BCHP_XPT_MCPB_MISC_DESC_TAGID_MISMATCH_INTR_L2_REG_END 0x00a7042c
-#define BCHP_XPT_MCPB_MISC_DATA_TAGID_MISMATCH_INTR_L2_REG_START 0x00a70440
-#define BCHP_XPT_MCPB_MISC_DATA_TAGID_MISMATCH_INTR_L2_REG_END 0x00a7046c
-#define BCHP_XPT_MCPB_MISC_CRC_COMPARE_ERROR_INTR_L2_REG_START 0x00a70480
-#define BCHP_XPT_MCPB_MISC_CRC_COMPARE_ERROR_INTR_L2_REG_END 0x00a704ac
-#define BCHP_XPT_MCPB_REG_START 0x00a70800
-#define BCHP_XPT_MCPB_REG_END 0x00a70b80
-#define BCHP_XPT_MCPB_CH0_REG_START 0x00a70c00
-#define BCHP_XPT_MCPB_CH0_REG_END 0x00a70d54
-#define BCHP_XPT_MCPB_CH1_REG_START 0x00a70e00
-#define BCHP_XPT_MCPB_CH1_REG_END 0x00a70f54
-#define BCHP_XPT_MCPB_CH2_REG_START 0x00a71000
-#define BCHP_XPT_MCPB_CH2_REG_END 0x00a71154
-#define BCHP_XPT_MCPB_CH3_REG_START 0x00a71200
-#define BCHP_XPT_MCPB_CH3_REG_END 0x00a71354
-#define BCHP_XPT_MCPB_CH4_REG_START 0x00a71400
-#define BCHP_XPT_MCPB_CH4_REG_END 0x00a71554
-#define BCHP_XPT_MCPB_CH5_REG_START 0x00a71600
-#define BCHP_XPT_MCPB_CH5_REG_END 0x00a71754
-#define BCHP_XPT_MCPB_CH6_REG_START 0x00a71800
-#define BCHP_XPT_MCPB_CH6_REG_END 0x00a71954
-#define BCHP_XPT_MCPB_CH7_REG_START 0x00a71a00
-#define BCHP_XPT_MCPB_CH7_REG_END 0x00a71b54
-#define BCHP_XPT_MCPB_CH8_REG_START 0x00a71c00
-#define BCHP_XPT_MCPB_CH8_REG_END 0x00a71d54
-#define BCHP_XPT_MCPB_CH9_REG_START 0x00a71e00
-#define BCHP_XPT_MCPB_CH9_REG_END 0x00a71f54
-#define BCHP_XPT_MCPB_CH10_REG_START 0x00a72000
-#define BCHP_XPT_MCPB_CH10_REG_END 0x00a72154
-#define BCHP_XPT_MCPB_CH11_REG_START 0x00a72200
-#define BCHP_XPT_MCPB_CH11_REG_END 0x00a72354
-#define BCHP_XPT_MCPB_CH12_REG_START 0x00a72400
-#define BCHP_XPT_MCPB_CH12_REG_END 0x00a72554
-#define BCHP_XPT_MCPB_CH13_REG_START 0x00a72600
-#define BCHP_XPT_MCPB_CH13_REG_END 0x00a72754
-#define BCHP_XPT_MCPB_CH14_REG_START 0x00a72800
-#define BCHP_XPT_MCPB_CH14_REG_END 0x00a72954
-#define BCHP_XPT_MCPB_CH15_REG_START 0x00a72a00
-#define BCHP_XPT_MCPB_CH15_REG_END 0x00a72b54
-#define BCHP_XPT_MCPB_CH16_REG_START 0x00a72c00
-#define BCHP_XPT_MCPB_CH16_REG_END 0x00a72d54
-#define BCHP_XPT_MCPB_CH17_REG_START 0x00a72e00
-#define BCHP_XPT_MCPB_CH17_REG_END 0x00a72f54
-#define BCHP_XPT_MCPB_CH18_REG_START 0x00a73000
-#define BCHP_XPT_MCPB_CH18_REG_END 0x00a73154
-#define BCHP_XPT_MCPB_CH19_REG_START 0x00a73200
-#define BCHP_XPT_MCPB_CH19_REG_END 0x00a73354
-#define BCHP_XPT_MCPB_CH20_REG_START 0x00a73400
-#define BCHP_XPT_MCPB_CH20_REG_END 0x00a73554
-#define BCHP_XPT_MCPB_CH21_REG_START 0x00a73600
-#define BCHP_XPT_MCPB_CH21_REG_END 0x00a73754
-#define BCHP_XPT_MCPB_CH22_REG_START 0x00a73800
-#define BCHP_XPT_MCPB_CH22_REG_END 0x00a73954
-#define BCHP_XPT_MCPB_CH23_REG_START 0x00a73a00
-#define BCHP_XPT_MCPB_CH23_REG_END 0x00a73b54
-#define BCHP_XPT_MCPB_CH24_REG_START 0x00a73c00
-#define BCHP_XPT_MCPB_CH24_REG_END 0x00a73d54
-#define BCHP_XPT_MCPB_CH25_REG_START 0x00a73e00
-#define BCHP_XPT_MCPB_CH25_REG_END 0x00a73f54
-#define BCHP_XPT_MCPB_CH26_REG_START 0x00a74000
-#define BCHP_XPT_MCPB_CH26_REG_END 0x00a74154
-#define BCHP_XPT_MCPB_CH27_REG_START 0x00a74200
-#define BCHP_XPT_MCPB_CH27_REG_END 0x00a74354
-#define BCHP_XPT_MCPB_CH28_REG_START 0x00a74400
-#define BCHP_XPT_MCPB_CH28_REG_END 0x00a74554
-#define BCHP_XPT_MCPB_CH29_REG_START 0x00a74600
-#define BCHP_XPT_MCPB_CH29_REG_END 0x00a74754
-#define BCHP_XPT_MCPB_CH30_REG_START 0x00a74800
-#define BCHP_XPT_MCPB_CH30_REG_END 0x00a74954
-#define BCHP_XPT_MCPB_CH31_REG_START 0x00a74a00
-#define BCHP_XPT_MCPB_CH31_REG_END 0x00a74b54
-#define BCHP_XPT_XPU_REG_START 0x00a78000
-#define BCHP_XPT_XPU_REG_END 0x00a7c7fc
-#define BCHP_XPT_SECURE_BUS_IF_REG_START 0x00a7f000
-#define BCHP_XPT_SECURE_BUS_IF_REG_END 0x00a7f000
-#define BCHP_GENET_0_SYS_REG_START 0x00b60000
-#define BCHP_GENET_0_SYS_REG_END 0x00b6000c
-#define BCHP_GENET_0_GR_BRIDGE_REG_START 0x00b60040
-#define BCHP_GENET_0_GR_BRIDGE_REG_END 0x00b6004c
-#define BCHP_GENET_0_EXT_REG_START 0x00b60080
-#define BCHP_GENET_0_EXT_REG_END 0x00b600a0
-#define BCHP_GENET_0_INTRL2_0_REG_START 0x00b60200
-#define BCHP_GENET_0_INTRL2_0_REG_END 0x00b6022c
-#define BCHP_GENET_0_INTRL2_1_REG_START 0x00b60240
-#define BCHP_GENET_0_INTRL2_1_REG_END 0x00b6026c
-#define BCHP_GENET_0_RBUF_REG_START 0x00b60300
-#define BCHP_GENET_0_RBUF_REG_END 0x00b603b4
-#define BCHP_GENET_0_TBUF_REG_START 0x00b60600
-#define BCHP_GENET_0_TBUF_REG_END 0x00b60628
-#define BCHP_GENET_0_UMAC_REG_START 0x00b60800
-#define BCHP_GENET_0_UMAC_REG_END 0x00b60ed8
-#define BCHP_GENET_0_RDMA_REG_START 0x00b62000
-#define BCHP_GENET_0_RDMA_REG_END 0x00b630d4
-#define BCHP_GENET_0_TDMA_REG_START 0x00b64000
-#define BCHP_GENET_0_TDMA_REG_END 0x00b65084
-#define BCHP_GENET_0_HFB_REG_START 0x00b68000
-#define BCHP_GENET_0_HFB_REG_END 0x00b6fc48
-#define BCHP_GENET_1_SYS_REG_START 0x00b80000
-#define BCHP_GENET_1_SYS_REG_END 0x00b8000c
-#define BCHP_GENET_1_GR_BRIDGE_REG_START 0x00b80040
-#define BCHP_GENET_1_GR_BRIDGE_REG_END 0x00b8004c
-#define BCHP_GENET_1_EXT_REG_START 0x00b80080
-#define BCHP_GENET_1_EXT_REG_END 0x00b800a0
-#define BCHP_GENET_1_INTRL2_0_REG_START 0x00b80200
-#define BCHP_GENET_1_INTRL2_0_REG_END 0x00b8022c
-#define BCHP_GENET_1_INTRL2_1_REG_START 0x00b80240
-#define BCHP_GENET_1_INTRL2_1_REG_END 0x00b8026c
-#define BCHP_GENET_1_RBUF_REG_START 0x00b80300
-#define BCHP_GENET_1_RBUF_REG_END 0x00b803b4
-#define BCHP_GENET_1_TBUF_REG_START 0x00b80600
-#define BCHP_GENET_1_TBUF_REG_END 0x00b80628
-#define BCHP_GENET_1_UMAC_REG_START 0x00b80800
-#define BCHP_GENET_1_UMAC_REG_END 0x00b80ed8
-#define BCHP_GENET_1_RDMA_REG_START 0x00b82000
-#define BCHP_GENET_1_RDMA_REG_END 0x00b830d4
-#define BCHP_GENET_1_TDMA_REG_START 0x00b84000
-#define BCHP_GENET_1_TDMA_REG_END 0x00b85084
-#define BCHP_GENET_1_HFB_REG_START 0x00b88000
-#define BCHP_GENET_1_HFB_REG_END 0x00b8fc48
-#define BCHP_SID_REG_START 0x00bc0100
-#define BCHP_SID_REG_END 0x00bc019c
-#define BCHP_SID_RLE_REG_START 0x00bc0300
-#define BCHP_SID_RLE_REG_END 0x00bc039c
-#define BCHP_SID_DQ_REG_START 0x00bc0400
-#define BCHP_SID_DQ_REG_END 0x00bc04bc
-#define BCHP_SID_STRM_REG_START 0x00bc0800
-#define BCHP_SID_STRM_REG_END 0x00bc087c
-#define BCHP_SID_OUTPUT_REG_START 0x00bc0c00
-#define BCHP_SID_OUTPUT_REG_END 0x00bc0c40
-#define BCHP_SID_ARC_REG_START 0x00bc0f00
-#define BCHP_SID_ARC_REG_END 0x00bc0f3c
-#define BCHP_SID_ARCDMA_REG_START 0x00bc1800
-#define BCHP_SID_ARCDMA_REG_END 0x00bc1840
-#define BCHP_SID_DMARAM_REG_START 0x00bc1a00
-#define BCHP_SID_DMARAM_REG_END 0x00bc1bfc
-#define BCHP_SID_PEEK_BITS_REG_START 0x00bc2b00
-#define BCHP_SID_PEEK_BITS_REG_END 0x00bc2b3c
-#define BCHP_SID_EXTRACT_BITS_REG_START 0x00bc2b40
-#define BCHP_SID_EXTRACT_BITS_REG_END 0x00bc2b7c
-#define BCHP_SID_HUFF_SYMB_REG_START 0x00bc3000
-#define BCHP_SID_HUFF_SYMB_REG_END 0x00bc37fc
-#define BCHP_SID_HUFF_CODE_REG_START 0x00bc3900
-#define BCHP_SID_HUFF_CODE_REG_END 0x00bc39fc
-#define BCHP_SID_SYMB_REG_START 0x00bc3a00
-#define BCHP_SID_SYMB_REG_END 0x00bc3a10
-#define BCHP_SID_SYMB_JPEG_REG_START 0x00bc3a80
-#define BCHP_SID_SYMB_JPEG_REG_END 0x00bc3a8c
-#define BCHP_SID_BIGRAM_REG_START 0x00bc8000
-#define BCHP_SID_BIGRAM_REG_END 0x00bcfffc
-#define BCHP_SID_ARC_DBG_REG_START 0x00bd1000
-#define BCHP_SID_ARC_DBG_REG_END 0x00bd1010
-#define BCHP_SID_ARC_CORE_REG_START 0x00bd5000
-#define BCHP_SID_ARC_CORE_REG_END 0x00bd5014
-#define BCHP_SID_GR_REG_START 0x00be0000
-#define BCHP_SID_GR_REG_END 0x00be000c
-#define BCHP_SID_L2_REG_START 0x00be0100
-#define BCHP_SID_L2_REG_END 0x00be012c
-#define BCHP_SICH_REG_START 0x00be2000
-#define BCHP_SICH_REG_END 0x00be203c
-#define BCHP_M2MC_REG_START 0x00be4000
-#define BCHP_M2MC_REG_END 0x00be47fc
-#define BCHP_M2MC_L2_REG_START 0x00be5000
-#define BCHP_M2MC_L2_REG_END 0x00be502c
-#define BCHP_M2MC_GR_REG_START 0x00be5800
-#define BCHP_M2MC_GR_REG_END 0x00be580c
-#define BCHP_M2MC1_REG_START 0x00be6000
-#define BCHP_M2MC1_REG_END 0x00be67fc
-#define BCHP_M2MC1_L2_REG_START 0x00be7000
-#define BCHP_M2MC1_L2_REG_END 0x00be702c
-#define BCHP_M2MC1_GR_REG_START 0x00be7800
-#define BCHP_M2MC1_GR_REG_END 0x00be780c
-#define BCHP_V3D_CTL_REG_START 0x00bea000
-#define BCHP_V3D_CTL_REG_END 0x00bea040
-#define BCHP_V3D_CLE_REG_START 0x00bea100
-#define BCHP_V3D_CLE_REG_END 0x00bea138
-#define BCHP_V3D_PTB_REG_START 0x00bea300
-#define BCHP_V3D_PTB_REG_END 0x00bea310
-#define BCHP_V3D_QPS_REG_START 0x00bea400
-#define BCHP_V3D_QPS_REG_END 0x00bea43c
-#define BCHP_V3D_VPM_REG_START 0x00bea500
-#define BCHP_V3D_VPM_REG_END 0x00bea504
-#define BCHP_V3D_PCTR_REG_START 0x00bea600
-#define BCHP_V3D_PCTR_REG_END 0x00bea6fc
-#define BCHP_V3D_TOP_GR_BRIDGE_REG_START 0x00bea800
-#define BCHP_V3D_TOP_GR_BRIDGE_REG_END 0x00bea80c
-#define BCHP_V3D_GCA_REG_START 0x00beaa00
-#define BCHP_V3D_GCA_REG_END 0x00beaa58
-#define BCHP_V3D_DBG_REG_START 0x00beae00
-#define BCHP_V3D_DBG_REG_END 0x00beaf20
-#define BCHP_RAAGA_DSP_SEC0_REG_START 0x00bf0000
-#define BCHP_RAAGA_DSP_SEC0_REG_END 0x00bf0000
-#define BCHP_RAAGA_DSP_RGR_REG_START 0x00c00000
-#define BCHP_RAAGA_DSP_RGR_REG_END 0x00c00008
-#define BCHP_RAAGA_DSP_MISC_REG_START 0x00c20000
-#define BCHP_RAAGA_DSP_MISC_REG_END 0x00c2044c
-#define BCHP_RAAGA_DSP_TIMERS_REG_START 0x00c21000
-#define BCHP_RAAGA_DSP_TIMERS_REG_END 0x00c21058
-#define BCHP_RAAGA_DSP_PERI_DBG_CTRL_REG_START 0x00c21080
-#define BCHP_RAAGA_DSP_PERI_DBG_CTRL_REG_END 0x00c2109c
-#define BCHP_RAAGA_DSP_PERI_SW_REG_START 0x00c21100
-#define BCHP_RAAGA_DSP_PERI_SW_REG_END 0x00c21154
-#define BCHP_RAAGA_DSP_DMA_REG_START 0x00c21400
-#define BCHP_RAAGA_DSP_DMA_REG_END 0x00c21664
-#define BCHP_RAAGA_DSP_ESR_SI_REG_START 0x00c22000
-#define BCHP_RAAGA_DSP_ESR_SI_REG_END 0x00c22014
-#define BCHP_RAAGA_DSP_INTH_REG_START 0x00c22200
-#define BCHP_RAAGA_DSP_INTH_REG_END 0x00c2222c
-#define BCHP_RAAGA_DSP_FW_INTH_REG_START 0x00c22400
-#define BCHP_RAAGA_DSP_FW_INTH_REG_END 0x00c2242c
-#define BCHP_RAAGA_DSP_FW_CFG_REG_START 0x00c23000
-#define BCHP_RAAGA_DSP_FW_CFG_REG_END 0x00c2357c
-#define BCHP_RAAGA_DSP_MEM_SUBSYSTEM_REG_START 0x00c30000
-#define BCHP_RAAGA_DSP_MEM_SUBSYSTEM_REG_END 0x00c3bffc
-#define BCHP_AUD_MISC_REG_START 0x00c80000
-#define BCHP_AUD_MISC_REG_END 0x00c80118
-#define BCHP_AUD_INTH_REG_START 0x00c80800
-#define BCHP_AUD_INTH_REG_END 0x00c8082c
-#define BCHP_AUD_FMM_BF_CTRL_REG_START 0x00ca0000
-#define BCHP_AUD_FMM_BF_CTRL_REG_END 0x00ca0d3c
-#define BCHP_AUD_FMM_BF_ESR_REG_START 0x00ca1000
-#define BCHP_AUD_FMM_BF_ESR_REG_END 0x00ca1074
-#define BCHP_AUD_FMM_SRC_CTRL0_REG_START 0x00ca2000
-#define BCHP_AUD_FMM_SRC_CTRL0_REG_END 0x00ca2bfc
-#define BCHP_AUD_FMM_SRC_ESR0_REG_START 0x00ca3000
-#define BCHP_AUD_FMM_SRC_ESR0_REG_END 0x00ca3014
-#define BCHP_AUD_FMM_DP_CTRL0_REG_START 0x00ca4000
-#define BCHP_AUD_FMM_DP_CTRL0_REG_END 0x00ca612c
-#define BCHP_AUD_FMM_DP_ESR0_REG_START 0x00ca7c00
-#define BCHP_AUD_FMM_DP_ESR0_REG_END 0x00ca7c2c
-#define BCHP_AUD_FMM_IOP_OUT_I2S_STEREO_0_REG_START 0x00cb0000
-#define BCHP_AUD_FMM_IOP_OUT_I2S_STEREO_0_REG_END 0x00cb0084
-#define BCHP_AUD_FMM_IOP_OUT_SPDIF_0_REG_START 0x00cb0100
-#define BCHP_AUD_FMM_IOP_OUT_SPDIF_0_REG_END 0x00cb0184
-#define BCHP_AUD_FMM_IOP_OUT_MAI_0_REG_START 0x00cb0200
-#define BCHP_AUD_FMM_IOP_OUT_MAI_0_REG_END 0x00cb0284
-#define BCHP_AUD_FMM_IOP_OUT_MAI_1_REG_START 0x00cb0300
-#define BCHP_AUD_FMM_IOP_OUT_MAI_1_REG_END 0x00cb0384
-#define BCHP_HIFIDAC_CTRL_0_REG_START 0x00cb0800
-#define BCHP_HIFIDAC_CTRL_0_REG_END 0x00cb09fc
-#define BCHP_HIFIDAC_RM_0_REG_START 0x00cb0a00
-#define BCHP_HIFIDAC_RM_0_REG_END 0x00cb0a24
-#define BCHP_HIFIDAC_ESR_0_REG_START 0x00cb0b00
-#define BCHP_HIFIDAC_ESR_0_REG_END 0x00cb0b14
-#define BCHP_AUD_FMM_IOP_OUT_DAC_CTRL_0_REG_START 0x00cb0c00
-#define BCHP_AUD_FMM_IOP_OUT_DAC_CTRL_0_REG_END 0x00cb0c98
-#define BCHP_AUD_FMM_IOP_PLL_0_REG_START 0x00cb0d00
-#define BCHP_AUD_FMM_IOP_PLL_0_REG_END 0x00cb0d88
-#define BCHP_AUD_FMM_IOP_PLL_1_REG_START 0x00cb0e00
-#define BCHP_AUD_FMM_IOP_PLL_1_REG_END 0x00cb0e88
-#define BCHP_AUD_FMM_IOP_NCO_0_REG_START 0x00cb0f00
-#define BCHP_AUD_FMM_IOP_NCO_0_REG_END 0x00cb0f24
-#define BCHP_AUD_FMM_IOP_NCO_1_REG_START 0x00cb1000
-#define BCHP_AUD_FMM_IOP_NCO_1_REG_END 0x00cb1024
-#define BCHP_AUD_FMM_IOP_NCO_2_REG_START 0x00cb1100
-#define BCHP_AUD_FMM_IOP_NCO_2_REG_END 0x00cb1124
-#define BCHP_AUD_FMM_IOP_NCO_3_REG_START 0x00cb1200
-#define BCHP_AUD_FMM_IOP_NCO_3_REG_END 0x00cb1224
-#define BCHP_AUD_FMM_IOP_NCO_4_REG_START 0x00cb1300
-#define BCHP_AUD_FMM_IOP_NCO_4_REG_END 0x00cb1324
-#define BCHP_AUD_FMM_IOP_LOOPBACK_0_REG_START 0x00cb1400
-#define BCHP_AUD_FMM_IOP_LOOPBACK_0_REG_END 0x00cb1524
-#define BCHP_AUD_FMM_IOP_DUMMYSINK_0_REG_START 0x00cb1600
-#define BCHP_AUD_FMM_IOP_DUMMYSINK_0_REG_END 0x00cb1654
-#define BCHP_AUD_FMM_IOP_IN_SPDIF_0_REG_START 0x00cb1800
-#define BCHP_AUD_FMM_IOP_IN_SPDIF_0_REG_END 0x00cb18fc
-#define BCHP_AUD_FMM_IOP_IN_HDMI_0_REG_START 0x00cb2000
-#define BCHP_AUD_FMM_IOP_IN_HDMI_0_REG_END 0x00cb20ac
-#define BCHP_AUD_FMM_IOP_IN_I2S_STEREO_0_REG_START 0x00cb2800
-#define BCHP_AUD_FMM_IOP_IN_I2S_STEREO_0_REG_END 0x00cb2864
-#define BCHP_AUD_FMM_IOP_ATTG_0_REG_START 0x00cb2900
-#define BCHP_AUD_FMM_IOP_ATTG_0_REG_END 0x00cb2964
-#define BCHP_AUD_FMM_IOP_OUT_MS_STRM_CFG_0_REG_START 0x00cb4000
-#define BCHP_AUD_FMM_IOP_OUT_MS_STRM_CFG_0_REG_END 0x00cb41fc
-#define BCHP_AUD_FMM_IOP_OUT_MS_STRM_ESR_0_REG_START 0x00cb4400
-#define BCHP_AUD_FMM_IOP_OUT_MS_STRM_ESR_0_REG_END 0x00cb4414
-#define BCHP_AUD_FMM_IOP_OUT_MS_CTRL_0_REG_START 0x00cb6000
-#define BCHP_AUD_FMM_IOP_OUT_MS_CTRL_0_REG_END 0x00cb7bfc
-#define BCHP_AUD_FMM_IOP_OUT_MS_ESR_0_REG_START 0x00cb7d00
-#define BCHP_AUD_FMM_IOP_OUT_MS_ESR_0_REG_END 0x00cb7d14
-#define BCHP_AUD_FMM_IOP_OUT_MS_STRM_CFG_1_REG_START 0x00cb8000
-#define BCHP_AUD_FMM_IOP_OUT_MS_STRM_CFG_1_REG_END 0x00cb81fc
-#define BCHP_AUD_FMM_IOP_OUT_MS_STRM_ESR_1_REG_START 0x00cb8400
-#define BCHP_AUD_FMM_IOP_OUT_MS_STRM_ESR_1_REG_END 0x00cb8414
-#define BCHP_AUD_FMM_IOP_OUT_MS_CTRL_1_REG_START 0x00cba000
-#define BCHP_AUD_FMM_IOP_OUT_MS_CTRL_1_REG_END 0x00cbbbfc
-#define BCHP_AUD_FMM_IOP_OUT_MS_ESR_1_REG_START 0x00cbbd00
-#define BCHP_AUD_FMM_IOP_OUT_MS_ESR_1_REG_END 0x00cbbd14
-#define BCHP_AUD_FMM_IOP_MISC_REG_START 0x00cbc100
-#define BCHP_AUD_FMM_IOP_MISC_REG_END 0x00cbc154
-#define BCHP_DATA_MEM_REG_START 0x00e00000
-#define BCHP_DATA_MEM_REG_END 0x00e47ffc
-#define BCHP_CNTL_MEM_REG_START 0x00f20000
-#define BCHP_CNTL_MEM_REG_END 0x00f67ffc
-#define BCHP_DMA_AHB_ECL_CMD_SCH0_REG_START 0x00fc0000
-#define BCHP_DMA_AHB_ECL_CMD_SCH0_REG_END 0x00fc0000
-#define BCHP_DMA_AHB_ECL_CMD_SCH1_REG_START 0x00fc0010
-#define BCHP_DMA_AHB_ECL_CMD_SCH1_REG_END 0x00fc0010
-#define BCHP_DMA_AHB_ECL_CMD_SCH2_REG_START 0x00fc0020
-#define BCHP_DMA_AHB_ECL_CMD_SCH2_REG_END 0x00fc0020
-#define BCHP_DMA_AHB_ECL_CMD_SCH3_REG_START 0x00fc0030
-#define BCHP_DMA_AHB_ECL_CMD_SCH3_REG_END 0x00fc0030
-#define BCHP_DMA_AHB_ECL_CMD_SCH4_REG_START 0x00fc0040
-#define BCHP_DMA_AHB_ECL_CMD_SCH4_REG_END 0x00fc0040
-#define BCHP_DMA_AHB_ECL_CMD_SCH5_REG_START 0x00fc0050
-#define BCHP_DMA_AHB_ECL_CMD_SCH5_REG_END 0x00fc0050
-#define BCHP_DMA_AHB_ECL_CMD_SCH6_REG_START 0x00fc0060
-#define BCHP_DMA_AHB_ECL_CMD_SCH6_REG_END 0x00fc0060
-#define BCHP_DMA_AHB_ECL_CMD_SCH7_REG_START 0x00fc0070
-#define BCHP_DMA_AHB_ECL_CMD_SCH7_REG_END 0x00fc0070
-#define BCHP_DMA_AHB_ECL_CMD_SCH8_REG_START 0x00fc0080
-#define BCHP_DMA_AHB_ECL_CMD_SCH8_REG_END 0x00fc0080
-#define BCHP_DMA_AHB_ECL_CMD_SCH9_REG_START 0x00fc0090
-#define BCHP_DMA_AHB_ECL_CMD_SCH9_REG_END 0x00fc0090
-#define BCHP_DMA_AHB_ECL_CMD_SCH10_REG_START 0x00fc00a0
-#define BCHP_DMA_AHB_ECL_CMD_SCH10_REG_END 0x00fc00a0
-#define BCHP_DMA_AHB_ECL_CMD_SCH11_REG_START 0x00fc00b0
-#define BCHP_DMA_AHB_ECL_CMD_SCH11_REG_END 0x00fc00b0
-#define BCHP_DMA_AHB_ECL_CMD_SCH12_REG_START 0x00fc00c0
-#define BCHP_DMA_AHB_ECL_CMD_SCH12_REG_END 0x00fc00c0
-#define BCHP_DMA_AHB_ECL_CMD_SCH13_REG_START 0x00fc00d0
-#define BCHP_DMA_AHB_ECL_CMD_SCH13_REG_END 0x00fc00d0
-#define BCHP_DMA_AHB_ECL_CMD_SCH14_REG_START 0x00fc00e0
-#define BCHP_DMA_AHB_ECL_CMD_SCH14_REG_END 0x00fc00e0
-#define BCHP_DMA_AHB_ECL_CMD_SCH15_REG_START 0x00fc00f0
-#define BCHP_DMA_AHB_ECL_CMD_SCH15_REG_END 0x00fc00f0
-#define BCHP_DMA_AHB_ECL_CMD_SCH16_REG_START 0x00fc0100
-#define BCHP_DMA_AHB_ECL_CMD_SCH16_REG_END 0x00fc0100
-#define BCHP_DMA_AHB_ECL_CMD_SCH17_REG_START 0x00fc0110
-#define BCHP_DMA_AHB_ECL_CMD_SCH17_REG_END 0x00fc0110
-#define BCHP_DMA_AHB_ECL_CMD_SCH18_REG_START 0x00fc0120
-#define BCHP_DMA_AHB_ECL_CMD_SCH18_REG_END 0x00fc0120
-#define BCHP_DMA_AHB_ECL_CMD_SCH19_REG_START 0x00fc0130
-#define BCHP_DMA_AHB_ECL_CMD_SCH19_REG_END 0x00fc0130
-#define BCHP_DMA_AHB_ECL_CMD_RX_REG_START 0x00fc0800
-#define BCHP_DMA_AHB_ECL_CMD_RX_REG_END 0x00fc0800
-#define BCHP_DMA_AHB_CMD_RX_SCH0_REG_START 0x00fc4000
-#define BCHP_DMA_AHB_CMD_RX_SCH0_REG_END 0x00fc4000
-#define BCHP_DMA_AHB_CMD_RX_SCH1_REG_START 0x00fc4010
-#define BCHP_DMA_AHB_CMD_RX_SCH1_REG_END 0x00fc4010
-#define BCHP_DMA_AHB_CMD_RX_SCH2_REG_START 0x00fc4020
-#define BCHP_DMA_AHB_CMD_RX_SCH2_REG_END 0x00fc4020
-#define BCHP_DMA_AHB_CMD_RX_SCH3_REG_START 0x00fc4030
-#define BCHP_DMA_AHB_CMD_RX_SCH3_REG_END 0x00fc4030
-#define BCHP_DMA_AHB_CMD_RX_SCH4_REG_START 0x00fc4040
-#define BCHP_DMA_AHB_CMD_RX_SCH4_REG_END 0x00fc4040
-#define BCHP_DMA_AHB_CMD_RX_SCH5_REG_START 0x00fc4050
-#define BCHP_DMA_AHB_CMD_RX_SCH5_REG_END 0x00fc4050
-#define BCHP_DMA_AHB_CMD_RX_SCH6_REG_START 0x00fc4060
-#define BCHP_DMA_AHB_CMD_RX_SCH6_REG_END 0x00fc4060
-#define BCHP_DMA_AHB_CMD_RX_SCH7_REG_START 0x00fc4070
-#define BCHP_DMA_AHB_CMD_RX_SCH7_REG_END 0x00fc4070
-#define BCHP_DMA_AHB_CMD_RX_SCH8_REG_START 0x00fc4080
-#define BCHP_DMA_AHB_CMD_RX_SCH8_REG_END 0x00fc4080
-#define BCHP_DMA_AHB_CMD_RX_SCH9_REG_START 0x00fc4090
-#define BCHP_DMA_AHB_CMD_RX_SCH9_REG_END 0x00fc4090
-#define BCHP_DMA_AHB_CMD_RX_SCH10_REG_START 0x00fc40a0
-#define BCHP_DMA_AHB_CMD_RX_SCH10_REG_END 0x00fc40a0
-#define BCHP_DMA_AHB_CMD_RX_SCH11_REG_START 0x00fc40b0
-#define BCHP_DMA_AHB_CMD_RX_SCH11_REG_END 0x00fc40b0
-#define BCHP_DMA_AHB_CMD_RX_SCH12_REG_START 0x00fc40c0
-#define BCHP_DMA_AHB_CMD_RX_SCH12_REG_END 0x00fc40c0
-#define BCHP_DMA_AHB_CMD_RX_SCH13_REG_START 0x00fc40d0
-#define BCHP_DMA_AHB_CMD_RX_SCH13_REG_END 0x00fc40d0
-#define BCHP_DMA_AHB_CMD_RX_SCH14_REG_START 0x00fc40e0
-#define BCHP_DMA_AHB_CMD_RX_SCH14_REG_END 0x00fc40e0
-#define BCHP_DMA_AHB_CMD_RX_SCH15_REG_START 0x00fc40f0
-#define BCHP_DMA_AHB_CMD_RX_SCH15_REG_END 0x00fc40f0
-#define BCHP_DMA_AHB_CMD_RX_SCH16_REG_START 0x00fc4100
-#define BCHP_DMA_AHB_CMD_RX_SCH16_REG_END 0x00fc4100
-#define BCHP_DMA_AHB_CMD_RX_SCH17_REG_START 0x00fc4110
-#define BCHP_DMA_AHB_CMD_RX_SCH17_REG_END 0x00fc4110
-#define BCHP_DMA_AHB_CMD_RX_SCH18_REG_START 0x00fc4120
-#define BCHP_DMA_AHB_CMD_RX_SCH18_REG_END 0x00fc4120
-#define BCHP_DMA_AHB_CMD_RX_SCH19_REG_START 0x00fc4130
-#define BCHP_DMA_AHB_CMD_RX_SCH19_REG_END 0x00fc4130
-#define BCHP_DMA_AHB_CMD_RES0_SCH0_REG_START 0x00fc4200
-#define BCHP_DMA_AHB_CMD_RES0_SCH0_REG_END 0x00fc4200
-#define BCHP_DMA_AHB_CMD_RES0_SCH1_REG_START 0x00fc4210
-#define BCHP_DMA_AHB_CMD_RES0_SCH1_REG_END 0x00fc4210
-#define BCHP_DMA_AHB_CMD_RES0_SCH2_REG_START 0x00fc4220
-#define BCHP_DMA_AHB_CMD_RES0_SCH2_REG_END 0x00fc4220
-#define BCHP_DMA_AHB_CMD_RES0_SCH3_REG_START 0x00fc4230
-#define BCHP_DMA_AHB_CMD_RES0_SCH3_REG_END 0x00fc4230
-#define BCHP_DMA_AHB_CMD_RES0_SCH4_REG_START 0x00fc4240
-#define BCHP_DMA_AHB_CMD_RES0_SCH4_REG_END 0x00fc4240
-#define BCHP_DMA_AHB_CMD_RES0_SCH5_REG_START 0x00fc4250
-#define BCHP_DMA_AHB_CMD_RES0_SCH5_REG_END 0x00fc4250
-#define BCHP_DMA_AHB_CMD_RES0_SCH6_REG_START 0x00fc4260
-#define BCHP_DMA_AHB_CMD_RES0_SCH6_REG_END 0x00fc4260
-#define BCHP_DMA_AHB_CMD_RES0_SCH7_REG_START 0x00fc4270
-#define BCHP_DMA_AHB_CMD_RES0_SCH7_REG_END 0x00fc4270
-#define BCHP_DMA_AHB_CMD_TX0_REG_START 0x00fc4800
-#define BCHP_DMA_AHB_CMD_TX0_REG_END 0x00fc4800
-#define BCHP_DMA_AHB_CMD_TX1_REG_START 0x00fc4a00
-#define BCHP_DMA_AHB_CMD_TX1_REG_END 0x00fc4a00
-#define BCHP_DMA_AHB_CMD_CONF0_REG_START 0x00fc4c00
-#define BCHP_DMA_AHB_CMD_CONF0_REG_END 0x00fc4c00
-#define BCHP_MAC_AHB_REG_START 0x00fc5000
-#define BCHP_MAC_AHB_REG_END 0x00fc500c
-#define BCHP_LLM_AHB_REG_START 0x00fc8000
-#define BCHP_LLM_AHB_REG_END 0x00fc805c
-#define BCHP_PHY_REG_START 0x00fe0000
-#define BCHP_PHY_REG_END 0x00fe47fc
-#define BCHP_ECL_REG_START 0x00fe8000
-#define BCHP_ECL_REG_END 0x00fec940
-#define BCHP_DMA_IO2MEM_CH_ECL_TX_Global_REG_START 0x00fed000
-#define BCHP_DMA_IO2MEM_CH_ECL_TX_Global_REG_END 0x00fed014
-#define BCHP_DMA_IO2MEM_SUBCH_ECL_TX_SUBCH0_REG_START 0x00fed040
-#define BCHP_DMA_IO2MEM_SUBCH_ECL_TX_SUBCH0_REG_END 0x00fed06c
-#define BCHP_DMA_IO2MEM_SUBCH_ECL_TX_SUBCH1_REG_START 0x00fed080
-#define BCHP_DMA_IO2MEM_SUBCH_ECL_TX_SUBCH1_REG_END 0x00fed0ac
-#define BCHP_DMA_IO2MEM_SUBCH_ECL_TX_SUBCH2_REG_START 0x00fed0c0
-#define BCHP_DMA_IO2MEM_SUBCH_ECL_TX_SUBCH2_REG_END 0x00fed0ec
-#define BCHP_DMA_IO2MEM_SUBCH_ECL_TX_SUBCH3_REG_START 0x00fed100
-#define BCHP_DMA_IO2MEM_SUBCH_ECL_TX_SUBCH3_REG_END 0x00fed12c
-#define BCHP_DMA_IO2MEM_SUBCH_ECL_TX_SUBCH4_REG_START 0x00fed140
-#define BCHP_DMA_IO2MEM_SUBCH_ECL_TX_SUBCH4_REG_END 0x00fed16c
-#define BCHP_DMA_IO2MEM_SUBCH_ECL_TX_SUBCH5_REG_START 0x00fed180
-#define BCHP_DMA_IO2MEM_SUBCH_ECL_TX_SUBCH5_REG_END 0x00fed1ac
-#define BCHP_DMA_IO2MEM_SUBCH_ECL_TX_SUBCH6_REG_START 0x00fed1c0
-#define BCHP_DMA_IO2MEM_SUBCH_ECL_TX_SUBCH6_REG_END 0x00fed1ec
-#define BCHP_DMA_IO2MEM_SUBCH_ECL_TX_SUBCH7_REG_START 0x00fed200
-#define BCHP_DMA_IO2MEM_SUBCH_ECL_TX_SUBCH7_REG_END 0x00fed22c
-#define BCHP_DMA_IO2MEM_SUBCH_ECL_TX_SUBCH8_REG_START 0x00fed240
-#define BCHP_DMA_IO2MEM_SUBCH_ECL_TX_SUBCH8_REG_END 0x00fed26c
-#define BCHP_DMA_IO2MEM_SUBCH_ECL_TX_SUBCH9_REG_START 0x00fed280
-#define BCHP_DMA_IO2MEM_SUBCH_ECL_TX_SUBCH9_REG_END 0x00fed2ac
-#define BCHP_DMA_IO2MEM_SUBCH_ECL_TX_SUBCH10_REG_START 0x00fed2c0
-#define BCHP_DMA_IO2MEM_SUBCH_ECL_TX_SUBCH10_REG_END 0x00fed2ec
-#define BCHP_DMA_IO2MEM_SUBCH_ECL_TX_SUBCH11_REG_START 0x00fed300
-#define BCHP_DMA_IO2MEM_SUBCH_ECL_TX_SUBCH11_REG_END 0x00fed32c
-#define BCHP_DMA_IO2MEM_SUBCH_ECL_TX_SUBCH12_REG_START 0x00fed340
-#define BCHP_DMA_IO2MEM_SUBCH_ECL_TX_SUBCH12_REG_END 0x00fed36c
-#define BCHP_DMA_IO2MEM_SUBCH_ECL_TX_SUBCH13_REG_START 0x00fed380
-#define BCHP_DMA_IO2MEM_SUBCH_ECL_TX_SUBCH13_REG_END 0x00fed3ac
-#define BCHP_DMA_IO2MEM_SUBCH_ECL_TX_SUBCH14_REG_START 0x00fed3c0
-#define BCHP_DMA_IO2MEM_SUBCH_ECL_TX_SUBCH14_REG_END 0x00fed3ec
-#define BCHP_DMA_IO2MEM_SUBCH_ECL_TX_SUBCH15_REG_START 0x00fed400
-#define BCHP_DMA_IO2MEM_SUBCH_ECL_TX_SUBCH15_REG_END 0x00fed42c
-#define BCHP_DMA_IO2MEM_SUBCH_ECL_TX_SUBCH16_REG_START 0x00fed440
-#define BCHP_DMA_IO2MEM_SUBCH_ECL_TX_SUBCH16_REG_END 0x00fed46c
-#define BCHP_DMA_IO2MEM_SUBCH_ECL_TX_SUBCH17_REG_START 0x00fed480
-#define BCHP_DMA_IO2MEM_SUBCH_ECL_TX_SUBCH17_REG_END 0x00fed4ac
-#define BCHP_DMA_IO2MEM_SUBCH_ECL_TX_SUBCH18_REG_START 0x00fed4c0
-#define BCHP_DMA_IO2MEM_SUBCH_ECL_TX_SUBCH18_REG_END 0x00fed4ec
-#define BCHP_DMA_IO2MEM_SUBCH_ECL_TX_SUBCH19_REG_START 0x00fed500
-#define BCHP_DMA_IO2MEM_SUBCH_ECL_TX_SUBCH19_REG_END 0x00fed52c
-#define BCHP_DMA_MEM2IO_CH_ECL_RX_REG_START 0x00fed800
-#define BCHP_DMA_MEM2IO_CH_ECL_RX_REG_END 0x00fed828
-#define BCHP_GMII_REG_START 0x00fedc00
-#define BCHP_GMII_REG_END 0x00fedc58
-#define BCHP_MAC_APB_REG_START 0x00ff0000
-#define BCHP_MAC_APB_REG_END 0x00ff14fc
-#define BCHP_DMA_IO2MEM_CH_MAC_RX_Global_REG_START 0x00ff4000
-#define BCHP_DMA_IO2MEM_CH_MAC_RX_Global_REG_END 0x00ff4014
-#define BCHP_DMA_IO2MEM_SUBCH_MAC_RX_SUBCH0_REG_START 0x00ff4040
-#define BCHP_DMA_IO2MEM_SUBCH_MAC_RX_SUBCH0_REG_END 0x00ff406c
-#define BCHP_DMA_IO2MEM_SUBCH_MAC_RX_SUBCH1_REG_START 0x00ff4080
-#define BCHP_DMA_IO2MEM_SUBCH_MAC_RX_SUBCH1_REG_END 0x00ff40ac
-#define BCHP_DMA_IO2MEM_SUBCH_MAC_RX_SUBCH2_REG_START 0x00ff40c0
-#define BCHP_DMA_IO2MEM_SUBCH_MAC_RX_SUBCH2_REG_END 0x00ff40ec
-#define BCHP_DMA_IO2MEM_SUBCH_MAC_RX_SUBCH3_REG_START 0x00ff4100
-#define BCHP_DMA_IO2MEM_SUBCH_MAC_RX_SUBCH3_REG_END 0x00ff412c
-#define BCHP_DMA_IO2MEM_SUBCH_MAC_RX_SUBCH4_REG_START 0x00ff4140
-#define BCHP_DMA_IO2MEM_SUBCH_MAC_RX_SUBCH4_REG_END 0x00ff416c
-#define BCHP_DMA_IO2MEM_SUBCH_MAC_RX_SUBCH5_REG_START 0x00ff4180
-#define BCHP_DMA_IO2MEM_SUBCH_MAC_RX_SUBCH5_REG_END 0x00ff41ac
-#define BCHP_DMA_IO2MEM_SUBCH_MAC_RX_SUBCH6_REG_START 0x00ff41c0
-#define BCHP_DMA_IO2MEM_SUBCH_MAC_RX_SUBCH6_REG_END 0x00ff41ec
-#define BCHP_DMA_IO2MEM_SUBCH_MAC_RX_SUBCH7_REG_START 0x00ff4200
-#define BCHP_DMA_IO2MEM_SUBCH_MAC_RX_SUBCH7_REG_END 0x00ff422c
-#define BCHP_DMA_IO2MEM_SUBCH_MAC_RX_SUBCH8_REG_START 0x00ff4240
-#define BCHP_DMA_IO2MEM_SUBCH_MAC_RX_SUBCH8_REG_END 0x00ff426c
-#define BCHP_DMA_IO2MEM_SUBCH_MAC_RX_SUBCH9_REG_START 0x00ff4280
-#define BCHP_DMA_IO2MEM_SUBCH_MAC_RX_SUBCH9_REG_END 0x00ff42ac
-#define BCHP_DMA_IO2MEM_SUBCH_MAC_RX_SUBCH10_REG_START 0x00ff42c0
-#define BCHP_DMA_IO2MEM_SUBCH_MAC_RX_SUBCH10_REG_END 0x00ff42ec
-#define BCHP_DMA_IO2MEM_SUBCH_MAC_RX_SUBCH11_REG_START 0x00ff4300
-#define BCHP_DMA_IO2MEM_SUBCH_MAC_RX_SUBCH11_REG_END 0x00ff432c
-#define BCHP_DMA_IO2MEM_SUBCH_MAC_RX_SUBCH12_REG_START 0x00ff4340
-#define BCHP_DMA_IO2MEM_SUBCH_MAC_RX_SUBCH12_REG_END 0x00ff436c
-#define BCHP_DMA_IO2MEM_SUBCH_MAC_RX_SUBCH13_REG_START 0x00ff4380
-#define BCHP_DMA_IO2MEM_SUBCH_MAC_RX_SUBCH13_REG_END 0x00ff43ac
-#define BCHP_DMA_IO2MEM_SUBCH_MAC_RX_SUBCH14_REG_START 0x00ff43c0
-#define BCHP_DMA_IO2MEM_SUBCH_MAC_RX_SUBCH14_REG_END 0x00ff43ec
-#define BCHP_DMA_IO2MEM_SUBCH_MAC_RX_SUBCH15_REG_START 0x00ff4400
-#define BCHP_DMA_IO2MEM_SUBCH_MAC_RX_SUBCH15_REG_END 0x00ff442c
-#define BCHP_DMA_IO2MEM_SUBCH_MAC_RX_SUBCH16_REG_START 0x00ff4440
-#define BCHP_DMA_IO2MEM_SUBCH_MAC_RX_SUBCH16_REG_END 0x00ff446c
-#define BCHP_DMA_IO2MEM_SUBCH_MAC_RX_SUBCH17_REG_START 0x00ff4480
-#define BCHP_DMA_IO2MEM_SUBCH_MAC_RX_SUBCH17_REG_END 0x00ff44ac
-#define BCHP_DMA_IO2MEM_SUBCH_MAC_RX_SUBCH18_REG_START 0x00ff44c0
-#define BCHP_DMA_IO2MEM_SUBCH_MAC_RX_SUBCH18_REG_END 0x00ff44ec
-#define BCHP_DMA_IO2MEM_SUBCH_MAC_RX_SUBCH19_REG_START 0x00ff4500
-#define BCHP_DMA_IO2MEM_SUBCH_MAC_RX_SUBCH19_REG_END 0x00ff452c
-#define BCHP_DMA_IO2MEM_CH_PHY0_Global_REG_START 0x00ff4800
-#define BCHP_DMA_IO2MEM_CH_PHY0_Global_REG_END 0x00ff4814
-#define BCHP_DMA_IO2MEM_SUBCH_PHY0_SUBCH0_REG_START 0x00ff4840
-#define BCHP_DMA_IO2MEM_SUBCH_PHY0_SUBCH0_REG_END 0x00ff486c
-#define BCHP_DMA_IO2MEM_SUBCH_PHY0_SUBCH1_REG_START 0x00ff4880
-#define BCHP_DMA_IO2MEM_SUBCH_PHY0_SUBCH1_REG_END 0x00ff48ac
-#define BCHP_DMA_IO2MEM_SUBCH_PHY0_SUBCH2_REG_START 0x00ff48c0
-#define BCHP_DMA_IO2MEM_SUBCH_PHY0_SUBCH2_REG_END 0x00ff48ec
-#define BCHP_DMA_IO2MEM_SUBCH_PHY0_SUBCH3_REG_START 0x00ff4900
-#define BCHP_DMA_IO2MEM_SUBCH_PHY0_SUBCH3_REG_END 0x00ff492c
-#define BCHP_DMA_IO2MEM_SUBCH_PHY0_SUBCH4_REG_START 0x00ff4940
-#define BCHP_DMA_IO2MEM_SUBCH_PHY0_SUBCH4_REG_END 0x00ff496c
-#define BCHP_DMA_IO2MEM_SUBCH_PHY0_SUBCH5_REG_START 0x00ff4980
-#define BCHP_DMA_IO2MEM_SUBCH_PHY0_SUBCH5_REG_END 0x00ff49ac
-#define BCHP_DMA_IO2MEM_SUBCH_PHY0_SUBCH6_REG_START 0x00ff49c0
-#define BCHP_DMA_IO2MEM_SUBCH_PHY0_SUBCH6_REG_END 0x00ff49ec
-#define BCHP_DMA_IO2MEM_SUBCH_PHY0_SUBCH7_REG_START 0x00ff4a00
-#define BCHP_DMA_IO2MEM_SUBCH_PHY0_SUBCH7_REG_END 0x00ff4a2c
-#define BCHP_DMA_MEM2IO_CH_MAC_TX0_REG_START 0x00ff6000
-#define BCHP_DMA_MEM2IO_CH_MAC_TX0_REG_END 0x00ff6028
-#define BCHP_DMA_MEM2IO_CH_MAC_TX1_REG_START 0x00ff6400
-#define BCHP_DMA_MEM2IO_CH_MAC_TX1_REG_END 0x00ff6428
-#define BCHP_DMA_MEM2IO_CH_PHY0_CONFIG_REG_START 0x00ff6800
-#define BCHP_DMA_MEM2IO_CH_PHY0_CONFIG_REG_END 0x00ff6828
-#define BCHP_MOCA_INTC_L2_HI_REG_START 0x00ff8000
-#define BCHP_MOCA_INTC_L2_HI_REG_END 0x00ff8584
-#define BCHP_MOCA_INTC_L2_LO_REG_START 0x00ff8800
-#define BCHP_MOCA_INTC_L2_LO_REG_END 0x00ff8d84
-#define BCHP_LLM_APB_REG_START 0x00ffc000
-#define BCHP_LLM_APB_REG_END 0x00ffd00c
-#define BCHP_TRX_REG_START 0x00ffe000
-#define BCHP_TRX_REG_END 0x00ffe1fc
-#define BCHP_MOCA_TIMER_REG_START 0x00ffe400
-#define BCHP_MOCA_TIMER_REG_END 0x00ffe4ec
-#define BCHP_MOCA_GPIO_REG_START 0x00ffe800
-#define BCHP_MOCA_GPIO_REG_END 0x00ffe818
-#define BCHP_EXTRAS_REG_START 0x00ffec00
-#define BCHP_EXTRAS_REG_END 0x00ffed18
-#define BCHP_MOCA_BSC_REG_START 0x00fff000
-#define BCHP_MOCA_BSC_REG_END 0x00fff058
-#define BCHP_MOCA_HOSTM2M_REG_START 0x00fffc00
-#define BCHP_MOCA_HOSTM2M_REG_END 0x00fffc14
-#define BCHP_AHB_M2M_DMA_REG_START 0x00fffc20
-#define BCHP_AHB_M2M_DMA_REG_END 0x00fffc2c
-#define BCHP_MOCA_L2_REG_START 0x00fffc40
-#define BCHP_MOCA_L2_REG_END 0x00fffc6c
-#define BCHP_MOCA_GR_BRIDGE_REG_START 0x00fffc80
-#define BCHP_MOCA_GR_BRIDGE_REG_END 0x00fffc8c
-#define BCHP_MOCA_HOSTMISC_REG_START 0x00fffd00
-#define BCHP_MOCA_HOSTMISC_REG_END 0x00fffd9c
-
-
-/***************************************************************************
- *AUD_FMM_MS_CTRL
- ***************************************************************************/
-/***************************************************************************
- *ABSTRACT_01_MICRO_SEQUENCER_CONTROL - Process to initialize and enable microsequencer
- ***************************************************************************/
-/* AUD_FMM_MS_CTRL :: ABSTRACT_01_MICRO_SEQUENCER_CONTROL :: NULL [31:00] */
-#define BCHP_AUD_FMM_MS_CTRL_ABSTRACT_01_MICRO_SEQUENCER_CONTROL_NULL_MASK 0xffffffff
-#define BCHP_AUD_FMM_MS_CTRL_ABSTRACT_01_MICRO_SEQUENCER_CONTROL_NULL_SHIFT 0
-
-/***************************************************************************
- *ABSTRACT_02_CHANNEL_STATUS - How to control channel status bits
- ***************************************************************************/
-/* AUD_FMM_MS_CTRL :: ABSTRACT_02_CHANNEL_STATUS :: NULL [31:00] */
-#define BCHP_AUD_FMM_MS_CTRL_ABSTRACT_02_CHANNEL_STATUS_NULL_MASK 0xffffffff
-#define BCHP_AUD_FMM_MS_CTRL_ABSTRACT_02_CHANNEL_STATUS_NULL_SHIFT 0
-
-/***************************************************************************
- *AUD_FMM_OP_CTRL
- ***************************************************************************/
-/***************************************************************************
- *ABSTRACT_01_MULTICHANNEL_MAI - Transmitting 6- and 8-channel MAI
- ***************************************************************************/
-/* AUD_FMM_OP_CTRL :: ABSTRACT_01_MULTICHANNEL_MAI :: MORE_INFORMATION [31:00] */
-#define BCHP_AUD_FMM_OP_CTRL_ABSTRACT_01_MULTICHANNEL_MAI_MORE_INFORMATION_MASK 0xffffffff
-#define BCHP_AUD_FMM_OP_CTRL_ABSTRACT_01_MULTICHANNEL_MAI_MORE_INFORMATION_SHIFT 0
-
-/***************************************************************************
- *BVN_MVFD_MFD
- ***************************************************************************/
-/***************************************************************************
- *DRAM_DATA_STRUCTURE - DRAM Data Structure
- ***************************************************************************/
-/* BVN_MVFD_MFD :: DRAM_DATA_STRUCTURE :: DRAM_DATA_STRUCTURE [31:00] */
-#define BCHP_BVN_MVFD_MFD_DRAM_DATA_STRUCTURE_DRAM_DATA_STRUCTURE_MASK 0xffffffff
-#define BCHP_BVN_MVFD_MFD_DRAM_DATA_STRUCTURE_DRAM_DATA_STRUCTURE_SHIFT 0
-
-/***************************************************************************
- *BVN_MVFD_VFD
- ***************************************************************************/
-/***************************************************************************
- *DRAM_DATA_STRUCTURE - DRAM Data Structure
- ***************************************************************************/
-/* BVN_MVFD_VFD :: DRAM_DATA_STRUCTURE :: DRAM_DATA_STRUCTURE [31:00] */
-#define BCHP_BVN_MVFD_VFD_DRAM_DATA_STRUCTURE_DRAM_DATA_STRUCTURE_MASK 0xffffffff
-#define BCHP_BVN_MVFD_VFD_DRAM_DATA_STRUCTURE_DRAM_DATA_STRUCTURE_SHIFT 0
-
-/***************************************************************************
- *GFD
- ***************************************************************************/
-/***************************************************************************
- *DRAM_DATA_STRUCTURE - DRAM Data Structure
- ***************************************************************************/
-/* GFD :: DRAM_DATA_STRUCTURE :: DRAM_DATA_STRUCTURE [31:00] */
-#define BCHP_GFD_DRAM_DATA_STRUCTURE_DRAM_DATA_STRUCTURE_MASK 0xffffffff
-#define BCHP_GFD_DRAM_DATA_STRUCTURE_DRAM_DATA_STRUCTURE_SHIFT 0
-
-/***************************************************************************
- *GFD_1
- ***************************************************************************/
-/***************************************************************************
- *DRAM_DATA_STRUCTURE - DRAM Data Structure
- ***************************************************************************/
-/* GFD_1 :: DRAM_DATA_STRUCTURE :: DRAM_DATA_STRUCTURE [31:00] */
-#define BCHP_GFD_1_DRAM_DATA_STRUCTURE_DRAM_DATA_STRUCTURE_MASK 0xffffffff
-#define BCHP_GFD_1_DRAM_DATA_STRUCTURE_DRAM_DATA_STRUCTURE_SHIFT 0
-
-/***************************************************************************
- *HIFIDAC_CTRL
- ***************************************************************************/
-/***************************************************************************
- *ABSTRACT_01_COMING_OUT_OF_RESET - Process to come out of reset
- ***************************************************************************/
-/* HIFIDAC_CTRL :: ABSTRACT_01_COMING_OUT_OF_RESET :: MORE_INFORMATION [31:00] */
-#define BCHP_HIFIDAC_CTRL_ABSTRACT_01_COMING_OUT_OF_RESET_MORE_INFORMATION_MASK 0xffffffff
-#define BCHP_HIFIDAC_CTRL_ABSTRACT_01_COMING_OUT_OF_RESET_MORE_INFORMATION_SHIFT 0
-
-/***************************************************************************
- *ABSTRACT_02_MUTE_USAGE - Mute usage
- ***************************************************************************/
-/* HIFIDAC_CTRL :: ABSTRACT_02_MUTE_USAGE :: MORE_INFORMATION [31:00] */
-#define BCHP_HIFIDAC_CTRL_ABSTRACT_02_MUTE_USAGE_MORE_INFORMATION_MASK 0xffffffff
-#define BCHP_HIFIDAC_CTRL_ABSTRACT_02_MUTE_USAGE_MORE_INFORMATION_SHIFT 0
-
-/***************************************************************************
- *ABSTRACT_03_SAMPLE_RATE_CHANGE - Process to effect a sample rate change
- ***************************************************************************/
-/* HIFIDAC_CTRL :: ABSTRACT_03_SAMPLE_RATE_CHANGE :: MORE_INFORMATION [31:00] */
-#define BCHP_HIFIDAC_CTRL_ABSTRACT_03_SAMPLE_RATE_CHANGE_MORE_INFORMATION_MASK 0xffffffff
-#define BCHP_HIFIDAC_CTRL_ABSTRACT_03_SAMPLE_RATE_CHANGE_MORE_INFORMATION_SHIFT 0
-
-/***************************************************************************
- *M2MC
- ***************************************************************************/
-/***************************************************************************
- *TYPE_CLUT_COLOR_DATA - color data for color look up table
- ***************************************************************************/
-/* M2MC :: TYPE_CLUT_COLOR_DATA :: ALPHA [31:24] */
-#define BCHP_M2MC_TYPE_CLUT_COLOR_DATA_ALPHA_MASK 0xff000000
-#define BCHP_M2MC_TYPE_CLUT_COLOR_DATA_ALPHA_SHIFT 24
-
-/* M2MC :: TYPE_CLUT_COLOR_DATA :: RED [23:16] */
-#define BCHP_M2MC_TYPE_CLUT_COLOR_DATA_RED_MASK 0x00ff0000
-#define BCHP_M2MC_TYPE_CLUT_COLOR_DATA_RED_SHIFT 16
-
-/* M2MC :: TYPE_CLUT_COLOR_DATA :: GREEN [15:08] */
-#define BCHP_M2MC_TYPE_CLUT_COLOR_DATA_GREEN_MASK 0x0000ff00
-#define BCHP_M2MC_TYPE_CLUT_COLOR_DATA_GREEN_SHIFT 8
-
-/* M2MC :: TYPE_CLUT_COLOR_DATA :: BLUE [07:00] */
-#define BCHP_M2MC_TYPE_CLUT_COLOR_DATA_BLUE_MASK 0x000000ff
-#define BCHP_M2MC_TYPE_CLUT_COLOR_DATA_BLUE_SHIFT 0
-
-/***************************************************************************
- *LIST_PACKET_ABSTRACT - Linked-List Packet Abstract
- ***************************************************************************/
-/* M2MC :: LIST_PACKET_ABSTRACT :: PACKET_FORMAT [31:00] */
-#define BCHP_M2MC_LIST_PACKET_ABSTRACT_PACKET_FORMAT_MASK 0xffffffff
-#define BCHP_M2MC_LIST_PACKET_ABSTRACT_PACKET_FORMAT_SHIFT 0
-
-/***************************************************************************
- *LIST_PACKET_HEADER_0 - Linked-List Packet Header Word 0
- ***************************************************************************/
-/* M2MC :: LIST_PACKET_HEADER_0 :: reserved0 [31:28] */
-#define BCHP_M2MC_LIST_PACKET_HEADER_0_reserved0_MASK 0xf0000000
-#define BCHP_M2MC_LIST_PACKET_HEADER_0_reserved0_SHIFT 28
-
-/* M2MC :: LIST_PACKET_HEADER_0 :: NEXT_PKT_ADDR [27:05] */
-#define BCHP_M2MC_LIST_PACKET_HEADER_0_NEXT_PKT_ADDR_MASK 0x0fffffe0
-#define BCHP_M2MC_LIST_PACKET_HEADER_0_NEXT_PKT_ADDR_SHIFT 5
-
-/* M2MC :: LIST_PACKET_HEADER_0 :: reserved1 [04:01] */
-#define BCHP_M2MC_LIST_PACKET_HEADER_0_reserved1_MASK 0x0000001e
-#define BCHP_M2MC_LIST_PACKET_HEADER_0_reserved1_SHIFT 1
-
-/* M2MC :: LIST_PACKET_HEADER_0 :: LAST_PKT_IND [00:00] */
-#define BCHP_M2MC_LIST_PACKET_HEADER_0_LAST_PKT_IND_MASK 0x00000001
-#define BCHP_M2MC_LIST_PACKET_HEADER_0_LAST_PKT_IND_SHIFT 0
-#define BCHP_M2MC_LIST_PACKET_HEADER_0_LAST_PKT_IND_NextPktValid 0
-#define BCHP_M2MC_LIST_PACKET_HEADER_0_LAST_PKT_IND_NextPktInvalid 1
-
-/***************************************************************************
- *LIST_PACKET_HEADER_1 - Linked-List Packet Header Word 1
- ***************************************************************************/
-/* M2MC :: LIST_PACKET_HEADER_1 :: reserved0 [31:15] */
-#define BCHP_M2MC_LIST_PACKET_HEADER_1_reserved0_MASK 0xffff8000
-#define BCHP_M2MC_LIST_PACKET_HEADER_1_reserved0_SHIFT 15
-
-/* M2MC :: LIST_PACKET_HEADER_1 :: SRC_FEEDER_GRP_CNTRL [14:14] */
-#define BCHP_M2MC_LIST_PACKET_HEADER_1_SRC_FEEDER_GRP_CNTRL_MASK 0x00004000
-#define BCHP_M2MC_LIST_PACKET_HEADER_1_SRC_FEEDER_GRP_CNTRL_SHIFT 14
-#define BCHP_M2MC_LIST_PACKET_HEADER_1_SRC_FEEDER_GRP_CNTRL_GRP_ENABLE 1
-#define BCHP_M2MC_LIST_PACKET_HEADER_1_SRC_FEEDER_GRP_CNTRL_GRP_DISABLE 0
-
-/* M2MC :: LIST_PACKET_HEADER_1 :: DST_FEEDER_GRP_CNTRL [13:13] */
-#define BCHP_M2MC_LIST_PACKET_HEADER_1_DST_FEEDER_GRP_CNTRL_MASK 0x00002000
-#define BCHP_M2MC_LIST_PACKET_HEADER_1_DST_FEEDER_GRP_CNTRL_SHIFT 13
-#define BCHP_M2MC_LIST_PACKET_HEADER_1_DST_FEEDER_GRP_CNTRL_GRP_ENABLE 1
-#define BCHP_M2MC_LIST_PACKET_HEADER_1_DST_FEEDER_GRP_CNTRL_GRP_DISABLE 0
-
-/* M2MC :: LIST_PACKET_HEADER_1 :: OUTPUT_FEEDER_GRP_CNTRL [12:12] */
-#define BCHP_M2MC_LIST_PACKET_HEADER_1_OUTPUT_FEEDER_GRP_CNTRL_MASK 0x00001000
-#define BCHP_M2MC_LIST_PACKET_HEADER_1_OUTPUT_FEEDER_GRP_CNTRL_SHIFT 12
-#define BCHP_M2MC_LIST_PACKET_HEADER_1_OUTPUT_FEEDER_GRP_CNTRL_GRP_ENABLE 1
-#define BCHP_M2MC_LIST_PACKET_HEADER_1_OUTPUT_FEEDER_GRP_CNTRL_GRP_DISABLE 0
-
-/* M2MC :: LIST_PACKET_HEADER_1 :: BLIT_GRP_CNTRL [11:11] */
-#define BCHP_M2MC_LIST_PACKET_HEADER_1_BLIT_GRP_CNTRL_MASK 0x00000800
-#define BCHP_M2MC_LIST_PACKET_HEADER_1_BLIT_GRP_CNTRL_SHIFT 11
-#define BCHP_M2MC_LIST_PACKET_HEADER_1_BLIT_GRP_CNTRL_GRP_ENABLE 1
-#define BCHP_M2MC_LIST_PACKET_HEADER_1_BLIT_GRP_CNTRL_GRP_DISABLE 0
-
-/* M2MC :: LIST_PACKET_HEADER_1 :: SCALE_PARAM_GRP_CNTRL [10:10] */
-#define BCHP_M2MC_LIST_PACKET_HEADER_1_SCALE_PARAM_GRP_CNTRL_MASK 0x00000400
-#define BCHP_M2MC_LIST_PACKET_HEADER_1_SCALE_PARAM_GRP_CNTRL_SHIFT 10
-#define BCHP_M2MC_LIST_PACKET_HEADER_1_SCALE_PARAM_GRP_CNTRL_GRP_ENABLE 1
-#define BCHP_M2MC_LIST_PACKET_HEADER_1_SCALE_PARAM_GRP_CNTRL_GRP_DISABLE 0
-
-/* M2MC :: LIST_PACKET_HEADER_1 :: BLEND_PARAM_GRP_CNTRL [09:09] */
-#define BCHP_M2MC_LIST_PACKET_HEADER_1_BLEND_PARAM_GRP_CNTRL_MASK 0x00000200
-#define BCHP_M2MC_LIST_PACKET_HEADER_1_BLEND_PARAM_GRP_CNTRL_SHIFT 9
-#define BCHP_M2MC_LIST_PACKET_HEADER_1_BLEND_PARAM_GRP_CNTRL_GRP_ENABLE 1
-#define BCHP_M2MC_LIST_PACKET_HEADER_1_BLEND_PARAM_GRP_CNTRL_GRP_DISABLE 0
-
-/* M2MC :: LIST_PACKET_HEADER_1 :: ROP_GRP_CNTRL [08:08] */
-#define BCHP_M2MC_LIST_PACKET_HEADER_1_ROP_GRP_CNTRL_MASK 0x00000100
-#define BCHP_M2MC_LIST_PACKET_HEADER_1_ROP_GRP_CNTRL_SHIFT 8
-#define BCHP_M2MC_LIST_PACKET_HEADER_1_ROP_GRP_CNTRL_GRP_ENABLE 1
-#define BCHP_M2MC_LIST_PACKET_HEADER_1_ROP_GRP_CNTRL_GRP_DISABLE 0
-
-/* M2MC :: LIST_PACKET_HEADER_1 :: SRC_COLOR_KEY_GRP_CNTRL [07:07] */
-#define BCHP_M2MC_LIST_PACKET_HEADER_1_SRC_COLOR_KEY_GRP_CNTRL_MASK 0x00000080
-#define BCHP_M2MC_LIST_PACKET_HEADER_1_SRC_COLOR_KEY_GRP_CNTRL_SHIFT 7
-#define BCHP_M2MC_LIST_PACKET_HEADER_1_SRC_COLOR_KEY_GRP_CNTRL_GRP_ENABLE 1
-#define BCHP_M2MC_LIST_PACKET_HEADER_1_SRC_COLOR_KEY_GRP_CNTRL_GRP_DISABLE 0
-
-/* M2MC :: LIST_PACKET_HEADER_1 :: DST_COLOR_KEY_GRP_CNTRL [06:06] */
-#define BCHP_M2MC_LIST_PACKET_HEADER_1_DST_COLOR_KEY_GRP_CNTRL_MASK 0x00000040
-#define BCHP_M2MC_LIST_PACKET_HEADER_1_DST_COLOR_KEY_GRP_CNTRL_SHIFT 6
-#define BCHP_M2MC_LIST_PACKET_HEADER_1_DST_COLOR_KEY_GRP_CNTRL_GRP_ENABLE 1
-#define BCHP_M2MC_LIST_PACKET_HEADER_1_DST_COLOR_KEY_GRP_CNTRL_GRP_DISABLE 0
-
-/* M2MC :: LIST_PACKET_HEADER_1 :: SCALE_COEF_GRP_CNTRL [05:05] */
-#define BCHP_M2MC_LIST_PACKET_HEADER_1_SCALE_COEF_GRP_CNTRL_MASK 0x00000020
-#define BCHP_M2MC_LIST_PACKET_HEADER_1_SCALE_COEF_GRP_CNTRL_SHIFT 5
-#define BCHP_M2MC_LIST_PACKET_HEADER_1_SCALE_COEF_GRP_CNTRL_GRP_ENABLE 1
-#define BCHP_M2MC_LIST_PACKET_HEADER_1_SCALE_COEF_GRP_CNTRL_GRP_DISABLE 0
-
-/* M2MC :: LIST_PACKET_HEADER_1 :: SRC_COLOR_MATRIX_GRP_CNTRL [04:04] */
-#define BCHP_M2MC_LIST_PACKET_HEADER_1_SRC_COLOR_MATRIX_GRP_CNTRL_MASK 0x00000010
-#define BCHP_M2MC_LIST_PACKET_HEADER_1_SRC_COLOR_MATRIX_GRP_CNTRL_SHIFT 4
-#define BCHP_M2MC_LIST_PACKET_HEADER_1_SRC_COLOR_MATRIX_GRP_CNTRL_GRP_ENABLE 1
-#define BCHP_M2MC_LIST_PACKET_HEADER_1_SRC_COLOR_MATRIX_GRP_CNTRL_GRP_DISABLE 0
-
-/* M2MC :: LIST_PACKET_HEADER_1 :: DST_COLOR_MATRIX_GRP_CNTRL [03:03] */
-#define BCHP_M2MC_LIST_PACKET_HEADER_1_DST_COLOR_MATRIX_GRP_CNTRL_MASK 0x00000008
-#define BCHP_M2MC_LIST_PACKET_HEADER_1_DST_COLOR_MATRIX_GRP_CNTRL_SHIFT 3
-#define BCHP_M2MC_LIST_PACKET_HEADER_1_DST_COLOR_MATRIX_GRP_CNTRL_GRP_ENABLE 1
-#define BCHP_M2MC_LIST_PACKET_HEADER_1_DST_COLOR_MATRIX_GRP_CNTRL_GRP_DISABLE 0
-
-/* M2MC :: LIST_PACKET_HEADER_1 :: OUTPUT_COLOR_MATRIX_GRP_CNTRL [02:02] */
-#define BCHP_M2MC_LIST_PACKET_HEADER_1_OUTPUT_COLOR_MATRIX_GRP_CNTRL_MASK 0x00000004
-#define BCHP_M2MC_LIST_PACKET_HEADER_1_OUTPUT_COLOR_MATRIX_GRP_CNTRL_SHIFT 2
-#define BCHP_M2MC_LIST_PACKET_HEADER_1_OUTPUT_COLOR_MATRIX_GRP_CNTRL_GRP_ENABLE 1
-#define BCHP_M2MC_LIST_PACKET_HEADER_1_OUTPUT_COLOR_MATRIX_GRP_CNTRL_GRP_DISABLE 0
-
-/* M2MC :: LIST_PACKET_HEADER_1 :: SRC_CLUT_GRP_CNTRL [01:01] */
-#define BCHP_M2MC_LIST_PACKET_HEADER_1_SRC_CLUT_GRP_CNTRL_MASK 0x00000002
-#define BCHP_M2MC_LIST_PACKET_HEADER_1_SRC_CLUT_GRP_CNTRL_SHIFT 1
-#define BCHP_M2MC_LIST_PACKET_HEADER_1_SRC_CLUT_GRP_CNTRL_GRP_ENABLE 1
-#define BCHP_M2MC_LIST_PACKET_HEADER_1_SRC_CLUT_GRP_CNTRL_GRP_DISABLE 0
-
-/* M2MC :: LIST_PACKET_HEADER_1 :: DST_CLUT_GRP_CNTRL [00:00] */
-#define BCHP_M2MC_LIST_PACKET_HEADER_1_DST_CLUT_GRP_CNTRL_MASK 0x00000001
-#define BCHP_M2MC_LIST_PACKET_HEADER_1_DST_CLUT_GRP_CNTRL_SHIFT 0
-#define BCHP_M2MC_LIST_PACKET_HEADER_1_DST_CLUT_GRP_CNTRL_GRP_ENABLE 1
-#define BCHP_M2MC_LIST_PACKET_HEADER_1_DST_CLUT_GRP_CNTRL_GRP_DISABLE 0
-
-/***************************************************************************
- *LIST_PKT_00_SRC_FEEDER_N - Linked-List Packet Word N for group SRC_FEEDER
- ***************************************************************************/
-/* M2MC :: LIST_PKT_00_SRC_FEEDER_N :: REGISTER_CONTENTS [31:00] */
-#define BCHP_M2MC_LIST_PKT_00_SRC_FEEDER_N_REGISTER_CONTENTS_MASK 0xffffffff
-#define BCHP_M2MC_LIST_PKT_00_SRC_FEEDER_N_REGISTER_CONTENTS_SHIFT 0
-
-/***************************************************************************
- *LIST_PKT_01_DST_FEEDER_N - Linked-List Packet Word N for group DST_FEEDER
- ***************************************************************************/
-/* M2MC :: LIST_PKT_01_DST_FEEDER_N :: REGISTER_CONTENTS [31:00] */
-#define BCHP_M2MC_LIST_PKT_01_DST_FEEDER_N_REGISTER_CONTENTS_MASK 0xffffffff
-#define BCHP_M2MC_LIST_PKT_01_DST_FEEDER_N_REGISTER_CONTENTS_SHIFT 0
-
-/***************************************************************************
- *LIST_PKT_02_OUTPUT_FEEDER_N - Linked-List Packet Word N for group OUTPUT_FEEDER
- ***************************************************************************/
-/* M2MC :: LIST_PKT_02_OUTPUT_FEEDER_N :: REGISTER_CONTENTS [31:00] */
-#define BCHP_M2MC_LIST_PKT_02_OUTPUT_FEEDER_N_REGISTER_CONTENTS_MASK 0xffffffff
-#define BCHP_M2MC_LIST_PKT_02_OUTPUT_FEEDER_N_REGISTER_CONTENTS_SHIFT 0
-
-/***************************************************************************
- *LIST_PKT_03_BLIT_N - Linked-List Packet Word N for group BLIT
- ***************************************************************************/
-/* M2MC :: LIST_PKT_03_BLIT_N :: REGISTER_CONTENTS [31:00] */
-#define BCHP_M2MC_LIST_PKT_03_BLIT_N_REGISTER_CONTENTS_MASK 0xffffffff
-#define BCHP_M2MC_LIST_PKT_03_BLIT_N_REGISTER_CONTENTS_SHIFT 0
-
-/***************************************************************************
- *LIST_PKT_04_SCALE_PARAM_N - Linked-List Packet Word N for group SCALE_PARAM
- ***************************************************************************/
-/* M2MC :: LIST_PKT_04_SCALE_PARAM_N :: REGISTER_CONTENTS [31:00] */
-#define BCHP_M2MC_LIST_PKT_04_SCALE_PARAM_N_REGISTER_CONTENTS_MASK 0xffffffff
-#define BCHP_M2MC_LIST_PKT_04_SCALE_PARAM_N_REGISTER_CONTENTS_SHIFT 0
-
-/***************************************************************************
- *LIST_PKT_05_BLEND_PARAM_N - Linked-List Packet Word N for group BLEND_PARAM
- ***************************************************************************/
-/* M2MC :: LIST_PKT_05_BLEND_PARAM_N :: REGISTER_CONTENTS [31:00] */
-#define BCHP_M2MC_LIST_PKT_05_BLEND_PARAM_N_REGISTER_CONTENTS_MASK 0xffffffff
-#define BCHP_M2MC_LIST_PKT_05_BLEND_PARAM_N_REGISTER_CONTENTS_SHIFT 0
-
-/***************************************************************************
- *LIST_PKT_06_ROP_N - Linked-List Packet Word N for group ROP
- ***************************************************************************/
-/* M2MC :: LIST_PKT_06_ROP_N :: REGISTER_CONTENTS [31:00] */
-#define BCHP_M2MC_LIST_PKT_06_ROP_N_REGISTER_CONTENTS_MASK 0xffffffff
-#define BCHP_M2MC_LIST_PKT_06_ROP_N_REGISTER_CONTENTS_SHIFT 0
-
-/***************************************************************************
- *LIST_PKT_07_SRC_COLOR_KEY_N - Linked-List Packet Word N for group SRC_COLOR_KEY
- ***************************************************************************/
-/* M2MC :: LIST_PKT_07_SRC_COLOR_KEY_N :: REGISTER_CONTENTS [31:00] */
-#define BCHP_M2MC_LIST_PKT_07_SRC_COLOR_KEY_N_REGISTER_CONTENTS_MASK 0xffffffff
-#define BCHP_M2MC_LIST_PKT_07_SRC_COLOR_KEY_N_REGISTER_CONTENTS_SHIFT 0
-
-/***************************************************************************
- *LIST_PKT_08_DST_COLOR_KEY_N - Linked-List Packet Word N for group DST_COLOR_KEY
- ***************************************************************************/
-/* M2MC :: LIST_PKT_08_DST_COLOR_KEY_N :: REGISTER_CONTENTS [31:00] */
-#define BCHP_M2MC_LIST_PKT_08_DST_COLOR_KEY_N_REGISTER_CONTENTS_MASK 0xffffffff
-#define BCHP_M2MC_LIST_PKT_08_DST_COLOR_KEY_N_REGISTER_CONTENTS_SHIFT 0
-
-/***************************************************************************
- *LIST_PKT_09_SCALE_COEF_N - Linked-List Packet Word N for group SCALE_COEF
- ***************************************************************************/
-/* M2MC :: LIST_PKT_09_SCALE_COEF_N :: REGISTER_CONTENTS [31:00] */
-#define BCHP_M2MC_LIST_PKT_09_SCALE_COEF_N_REGISTER_CONTENTS_MASK 0xffffffff
-#define BCHP_M2MC_LIST_PKT_09_SCALE_COEF_N_REGISTER_CONTENTS_SHIFT 0
-
-/***************************************************************************
- *LIST_PKT_10_SRC_COLOR_MATRIX_N - Linked-List Packet Word N for group SRC_COLOR_MATRIX
- ***************************************************************************/
-/* M2MC :: LIST_PKT_10_SRC_COLOR_MATRIX_N :: REGISTER_CONTENTS [31:00] */
-#define BCHP_M2MC_LIST_PKT_10_SRC_COLOR_MATRIX_N_REGISTER_CONTENTS_MASK 0xffffffff
-#define BCHP_M2MC_LIST_PKT_10_SRC_COLOR_MATRIX_N_REGISTER_CONTENTS_SHIFT 0
-
-/***************************************************************************
- *LIST_PKT_11_SRC_CLUT - Linked-List Packet Word for group SRC_CLUT
- ***************************************************************************/
-/* M2MC :: LIST_PKT_11_SRC_CLUT :: reserved0 [31:29] */
-#define BCHP_M2MC_LIST_PKT_11_SRC_CLUT_reserved0_MASK 0xe0000000
-#define BCHP_M2MC_LIST_PKT_11_SRC_CLUT_reserved0_SHIFT 29
-
-/* M2MC :: LIST_PKT_11_SRC_CLUT :: REGISTER_CONTENTS [28:00] */
-#define BCHP_M2MC_LIST_PKT_11_SRC_CLUT_REGISTER_CONTENTS_MASK 0x1fffffff
-#define BCHP_M2MC_LIST_PKT_11_SRC_CLUT_REGISTER_CONTENTS_SHIFT 0
-
-/***************************************************************************
- *PCIE_DMA
- ***************************************************************************/
-/***************************************************************************
- *DESC_WORD0 - PCIE DMA Descriptor Word 0
- ***************************************************************************/
-/* PCIE_DMA :: DESC_WORD0 :: MEMORY_ADDRESS [31:00] */
-#define BCHP_PCIE_DMA_DESC_WORD0_MEMORY_ADDRESS_MASK 0xffffffff
-#define BCHP_PCIE_DMA_DESC_WORD0_MEMORY_ADDRESS_SHIFT 0
-
-/***************************************************************************
- *DESC_WORD1 - PCIE DMA Descriptor Word 1
- ***************************************************************************/
-/* PCIE_DMA :: DESC_WORD1 :: PCIE_ADDRESS_LO [31:00] */
-#define BCHP_PCIE_DMA_DESC_WORD1_PCIE_ADDRESS_LO_MASK 0xffffffff
-#define BCHP_PCIE_DMA_DESC_WORD1_PCIE_ADDRESS_LO_SHIFT 0
-
-/***************************************************************************
- *DESC_WORD2 - PCIE DMA Descriptor Word 2
- ***************************************************************************/
-/* PCIE_DMA :: DESC_WORD2 :: PCIE_ADDRESS_HI [31:00] */
-#define BCHP_PCIE_DMA_DESC_WORD2_PCIE_ADDRESS_HI_MASK 0xffffffff
-#define BCHP_PCIE_DMA_DESC_WORD2_PCIE_ADDRESS_HI_SHIFT 0
-
-/***************************************************************************
- *DESC_WORD3 - PCIE DMA Descriptor Word 3
- ***************************************************************************/
-/* PCIE_DMA :: DESC_WORD3 :: INTERRUPT_ENABLE [31:31] */
-#define BCHP_PCIE_DMA_DESC_WORD3_INTERRUPT_ENABLE_MASK 0x80000000
-#define BCHP_PCIE_DMA_DESC_WORD3_INTERRUPT_ENABLE_SHIFT 31
-
-/* PCIE_DMA :: DESC_WORD3 :: reserved0 [30:25] */
-#define BCHP_PCIE_DMA_DESC_WORD3_reserved0_MASK 0x7e000000
-#define BCHP_PCIE_DMA_DESC_WORD3_reserved0_SHIFT 25
-
-/* PCIE_DMA :: DESC_WORD3 :: DMA_TRANSFER_SIZE [24:00] */
-#define BCHP_PCIE_DMA_DESC_WORD3_DMA_TRANSFER_SIZE_MASK 0x01ffffff
-#define BCHP_PCIE_DMA_DESC_WORD3_DMA_TRANSFER_SIZE_SHIFT 0
-
-/***************************************************************************
- *DESC_WORD4 - PCIE DMA Descriptor Word 4
- ***************************************************************************/
-/* PCIE_DMA :: DESC_WORD4 :: LAST_RECORD_INDICATOR [31:31] */
-#define BCHP_PCIE_DMA_DESC_WORD4_LAST_RECORD_INDICATOR_MASK 0x80000000
-#define BCHP_PCIE_DMA_DESC_WORD4_LAST_RECORD_INDICATOR_SHIFT 31
-
-/* PCIE_DMA :: DESC_WORD4 :: DMA_DIRECTION [30:30] */
-#define BCHP_PCIE_DMA_DESC_WORD4_DMA_DIRECTION_MASK 0x40000000
-#define BCHP_PCIE_DMA_DESC_WORD4_DMA_DIRECTION_SHIFT 30
-#define BCHP_PCIE_DMA_DESC_WORD4_DMA_DIRECTION_PCIE_TO_MEMORY 1
-#define BCHP_PCIE_DMA_DESC_WORD4_DMA_DIRECTION_MEMORY_TO_PCIE 0
-
-/* PCIE_DMA :: DESC_WORD4 :: reserved0 [29:03] */
-#define BCHP_PCIE_DMA_DESC_WORD4_reserved0_MASK 0x3ffffff8
-#define BCHP_PCIE_DMA_DESC_WORD4_reserved0_SHIFT 3
-
-/* PCIE_DMA :: DESC_WORD4 :: DESC_CONTIGUOUS [02:02] */
-#define BCHP_PCIE_DMA_DESC_WORD4_DESC_CONTIGUOUS_MASK 0x00000004
-#define BCHP_PCIE_DMA_DESC_WORD4_DESC_CONTIGUOUS_SHIFT 2
-
-/* PCIE_DMA :: DESC_WORD4 :: ENDIAN_XLATE_MODE [01:00] */
-#define BCHP_PCIE_DMA_DESC_WORD4_ENDIAN_XLATE_MODE_MASK 0x00000003
-#define BCHP_PCIE_DMA_DESC_WORD4_ENDIAN_XLATE_MODE_SHIFT 0
-#define BCHP_PCIE_DMA_DESC_WORD4_ENDIAN_XLATE_MODE_NO_SWAP 0
-#define BCHP_PCIE_DMA_DESC_WORD4_ENDIAN_XLATE_MODE_SWAP_16_IN_32 1
-#define BCHP_PCIE_DMA_DESC_WORD4_ENDIAN_XLATE_MODE_SWAP_32 2
-#define BCHP_PCIE_DMA_DESC_WORD4_ENDIAN_XLATE_MODE_reserved 3
-
-/***************************************************************************
- *DESC_WORD5 - PCIE DMA Descriptor Word 5
- ***************************************************************************/
-/* PCIE_DMA :: DESC_WORD5 :: NEXT_DESC_ADDRESS_LO [31:05] */
-#define BCHP_PCIE_DMA_DESC_WORD5_NEXT_DESC_ADDRESS_LO_MASK 0xffffffe0
-#define BCHP_PCIE_DMA_DESC_WORD5_NEXT_DESC_ADDRESS_LO_SHIFT 5
-
-/* PCIE_DMA :: DESC_WORD5 :: reserved0 [04:00] */
-#define BCHP_PCIE_DMA_DESC_WORD5_reserved0_MASK 0x0000001f
-#define BCHP_PCIE_DMA_DESC_WORD5_reserved0_SHIFT 0
-
-/***************************************************************************
- *DESC_WORD6 - PCIE DMA Descriptor Word 6
- ***************************************************************************/
-/* PCIE_DMA :: DESC_WORD6 :: NEXT_DESC_ADDRESS_HI [31:00] */
-#define BCHP_PCIE_DMA_DESC_WORD6_NEXT_DESC_ADDRESS_HI_MASK 0xffffffff
-#define BCHP_PCIE_DMA_DESC_WORD6_NEXT_DESC_ADDRESS_HI_SHIFT 0
-
-/***************************************************************************
- *DESC_WORD7 - PCIE DMA Descriptor Word 7
- ***************************************************************************/
-/* PCIE_DMA :: DESC_WORD7 :: reserved0 [31:08] */
-#define BCHP_PCIE_DMA_DESC_WORD7_reserved0_MASK 0xffffff00
-#define BCHP_PCIE_DMA_DESC_WORD7_reserved0_SHIFT 8
-
-/* PCIE_DMA :: DESC_WORD7 :: MEMORY_ADDRESS_HI [07:00] */
-#define BCHP_PCIE_DMA_DESC_WORD7_MEMORY_ADDRESS_HI_MASK 0x000000ff
-#define BCHP_PCIE_DMA_DESC_WORD7_MEMORY_ADDRESS_HI_SHIFT 0
-
-/***************************************************************************
- *RAAGA_REGSET_DSP_CFG
- ***************************************************************************/
-/***************************************************************************
- *AC3_UPS_WORD_00 - AC3 User Parameters Structure Word 0 - DYNRNGSCALEHI
- ***************************************************************************/
-/* RAAGA_REGSET_DSP_CFG :: AC3_UPS_WORD_00 :: DYNRNGSCALEHI [15:00] */
-#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_00_DYNRNGSCALEHI_MASK 0xffff
-#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_00_DYNRNGSCALEHI_SHIFT 0
-#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_00_DYNRNGSCALEHI_No_compression 0
-#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_00_DYNRNGSCALEHI_Full_compression 32767
-
-/***************************************************************************
- *AC3_UPS_WORD_01 - AC3 User Parameters Structure Word 1 - DYNRNGSCALELOW
- ***************************************************************************/
-/* RAAGA_REGSET_DSP_CFG :: AC3_UPS_WORD_01 :: DYNRNGSCALELOW [15:00] */
-#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_01_DYNRNGSCALELOW_MASK 0xffff
-#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_01_DYNRNGSCALELOW_SHIFT 0
-#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_01_DYNRNGSCALELOW_No_compression 0
-#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_01_DYNRNGSCALELOW_Full_compression 32767
-
-/***************************************************************************
- *AC3_UPS_WORD_02 - AC3 User Parameters Structure Word 2 - PCMSCALEFAC
- ***************************************************************************/
-/* RAAGA_REGSET_DSP_CFG :: AC3_UPS_WORD_02 :: PCMSCALEFAC [15:00] */
-#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_02_PCMSCALEFAC_MASK 0xffff
-#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_02_PCMSCALEFAC_SHIFT 0
-#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_02_PCMSCALEFAC_Full_scale 32767
-#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_02_PCMSCALEFAC_Mute 0
-
-/***************************************************************************
- *AC3_UPS_WORD_03 - AC3 User Parameters Structure Word 3 - COMPMODE
- ***************************************************************************/
-/* RAAGA_REGSET_DSP_CFG :: AC3_UPS_WORD_03 :: COMPMODE [15:00] */
-#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_03_COMPMODE_MASK 0xffff
-#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_03_COMPMODE_SHIFT 0
-#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_03_COMPMODE_Comp_custom_a 0
-#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_03_COMPMODE_Comp_custom_d 1
-#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_03_COMPMODE_Comp_line 2
-#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_03_COMPMODE_Comp_rf 3
-
-/***************************************************************************
- *AC3_UPS_WORD_04 - AC3 User Parameters Structure Word 4 - DUALMONOMODE
- ***************************************************************************/
-/* RAAGA_REGSET_DSP_CFG :: AC3_UPS_WORD_04 :: DUALMONOMODE [15:00] */
-#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_04_DUALMONOMODE_MASK 0xffff
-#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_04_DUALMONOMODE_SHIFT 0
-#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_04_DUALMONOMODE_Pass_through 0
-#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_04_DUALMONOMODE_Left_mono 1
-#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_04_DUALMONOMODE_Right_mono 2
-#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_04_DUALMONOMODE_True_mono 3
-
-/***************************************************************************
- *AC3_UPS_WORD_05 - AC3 User Parameters Structure Word 5 - OUTPUTMODE
- ***************************************************************************/
-/* RAAGA_REGSET_DSP_CFG :: AC3_UPS_WORD_05 :: OUTPUTMODE [15:00] */
-#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_05_OUTPUTMODE_MASK 0xffff
-#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_05_OUTPUTMODE_SHIFT 0
-#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_05_OUTPUTMODE_Mode11 0
-#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_05_OUTPUTMODE_Mode10 1
-#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_05_OUTPUTMODE_Mode20 2
-#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_05_OUTPUTMODE_Mode30 3
-#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_05_OUTPUTMODE_Mode21 4
-#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_05_OUTPUTMODE_Mode31 5
-#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_05_OUTPUTMODE_Mode22 6
-#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_05_OUTPUTMODE_Mode32 7
-
-/***************************************************************************
- *AC3_UPS_WORD_06 - AC3 User Parameters Structure Word 6 - OUTLFEON
- ***************************************************************************/
-/* RAAGA_REGSET_DSP_CFG :: AC3_UPS_WORD_06 :: OUTLFEON [15:00] */
-#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_06_OUTLFEON_MASK 0xffff
-#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_06_OUTLFEON_SHIFT 0
-#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_06_OUTLFEON_Off 0
-#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_06_OUTLFEON_On 1
-
-/***************************************************************************
- *AC3_UPS_WORD_07 - AC3 User Parameters Structure Word 7 - KCAPABLEMODE
- ***************************************************************************/
-/* RAAGA_REGSET_DSP_CFG :: AC3_UPS_WORD_07 :: KCAPABLEMODE [15:00] */
-#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_07_KCAPABLEMODE_MASK 0xffff
-#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_07_KCAPABLEMODE_SHIFT 0
-#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_07_KCAPABLEMODE_No_vocal_channels 0
-#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_07_KCAPABLEMODE_Vocal_channel_V1 1
-#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_07_KCAPABLEMODE_Vocal_channel_V2 2
-#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_07_KCAPABLEMODE_Both_vocal_channels 3
-
-/***************************************************************************
- *AC3_UPS_WORD_08 - AC3 User Parameters Structure Word 8 - KARAOKE_PARAMETER_FLAG
- ***************************************************************************/
-/* RAAGA_REGSET_DSP_CFG :: AC3_UPS_WORD_08 :: KARAOKE_PARAMETER_FLAG [15:00] */
-#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_08_KARAOKE_PARAMETER_FLAG_MASK 0xffff
-#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_08_KARAOKE_PARAMETER_FLAG_SHIFT 0
-#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_08_KARAOKE_PARAMETER_FLAG_Off 0
-#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_08_KARAOKE_PARAMETER_FLAG_On 1
-
-/***************************************************************************
- *AC3_UPS_WORD_09 - AC3 User Parameters Structure Word 9 - KARAOKE_V1_LEVEL
- ***************************************************************************/
-/* RAAGA_REGSET_DSP_CFG :: AC3_UPS_WORD_09 :: KARAOKE_V1_LEVEL [15:00] */
-#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_09_KARAOKE_V1_LEVEL_MASK 0xffff
-#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_09_KARAOKE_V1_LEVEL_SHIFT 0
-#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_09_KARAOKE_V1_LEVEL_Full_scale 32767
-#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_09_KARAOKE_V1_LEVEL_Mute 0
-
-/***************************************************************************
- *AC3_UPS_WORD_10 - AC3 User Parameters Structure Word 10 - KARAOKE_V1_PAN
- ***************************************************************************/
-/* RAAGA_REGSET_DSP_CFG :: AC3_UPS_WORD_10 :: KARAOKE_V1_PAN [15:00] */
-#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_10_KARAOKE_V1_PAN_MASK 0xffff
-#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_10_KARAOKE_V1_PAN_SHIFT 0
-#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_10_KARAOKE_V1_PAN_Hard_left 32767
-#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_10_KARAOKE_V1_PAN_Middle 0
-#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_10_KARAOKE_V1_PAN_Hard_right 32768
-
-/***************************************************************************
- *AC3_UPS_WORD_11 - AC3 User Parameters Structure Word 11 - KARAOKE_V2_LEVEL
- ***************************************************************************/
-/* RAAGA_REGSET_DSP_CFG :: AC3_UPS_WORD_11 :: KARAOKE_V2_LEVEL [15:00] */
-#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_11_KARAOKE_V2_LEVEL_MASK 0xffff
-#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_11_KARAOKE_V2_LEVEL_SHIFT 0
-#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_11_KARAOKE_V2_LEVEL_Full_scale 32767
-#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_11_KARAOKE_V2_LEVEL_Mute 0
-
-/***************************************************************************
- *AC3_UPS_WORD_12 - AC3 User Parameters Structure Word 12 - KARAOKE_V2_PAN
- ***************************************************************************/
-/* RAAGA_REGSET_DSP_CFG :: AC3_UPS_WORD_12 :: KARAOKE_V2_PAN [15:00] */
-#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_12_KARAOKE_V2_PAN_MASK 0xffff
-#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_12_KARAOKE_V2_PAN_SHIFT 0
-#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_12_KARAOKE_V2_PAN_Hard_left 32767
-#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_12_KARAOKE_V2_PAN_Middle 0
-#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_12_KARAOKE_V2_PAN_Hard_right 32768
-
-/***************************************************************************
- *AC3_UPS_WORD_13 - AC3 User Parameters Structure Word 13 - KARAOKE_GM_LEVEL
- ***************************************************************************/
-/* RAAGA_REGSET_DSP_CFG :: AC3_UPS_WORD_13 :: KARAOKE_GM_LEVEL [15:00] */
-#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_13_KARAOKE_GM_LEVEL_MASK 0xffff
-#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_13_KARAOKE_GM_LEVEL_SHIFT 0
-#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_13_KARAOKE_GM_LEVEL_Full_scale 32767
-#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_13_KARAOKE_GM_LEVEL_Mute 0
-
-/***************************************************************************
- *AC3_UPS_WORD_14 - AC3 User Parameters Structure Word 14 - KARAOKE_GM_PAN
- ***************************************************************************/
-/* RAAGA_REGSET_DSP_CFG :: AC3_UPS_WORD_14 :: KARAOKE_GM_PAN [15:00] */
-#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_14_KARAOKE_GM_PAN_MASK 0xffff
-#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_14_KARAOKE_GM_PAN_SHIFT 0
-#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_14_KARAOKE_GM_PAN_Hard_left 32767
-#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_14_KARAOKE_GM_PAN_Middle 0
-#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_14_KARAOKE_GM_PAN_Hard_right 32768
-
-/***************************************************************************
- *AC3_UPS_WORD_15 - AC3 User Parameters Structure Word 15 - STEREO_MOD
- ***************************************************************************/
-/* RAAGA_REGSET_DSP_CFG :: AC3_UPS_WORD_15 :: STEREO_MOD [15:00] */
-#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_15_STEREO_MOD_MASK 0xffff
-#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_15_STEREO_MOD_SHIFT 0
-#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_15_STEREO_MOD_Auto 0
-#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_15_STEREO_MOD_LtRt 1
-#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_15_STEREO_MOD_LoRo 2
-
-/***************************************************************************
- *AC3_UPS_WORD_16 - AC3 User Parameters Structure Word 16 - USER_DOWNMIX_FLAG
- ***************************************************************************/
-/* RAAGA_REGSET_DSP_CFG :: AC3_UPS_WORD_16 :: USER_DOWNMIX_FLAG [15:00] */
-#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_16_USER_DOWNMIX_FLAG_MASK 0xffff
-#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_16_USER_DOWNMIX_FLAG_SHIFT 0
-#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_16_USER_DOWNMIX_FLAG_Off 0
-#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_16_USER_DOWNMIX_FLAG_On 1
-
-/***************************************************************************
- *AC3_UPS_WORD_17_TO_52 - AC3 User Parameters Structure Word 17 to 52 - DRAM_USER_DEFINED_DNMX_COEFFS
- ***************************************************************************/
-/* RAAGA_REGSET_DSP_CFG :: AC3_UPS_WORD_17_TO_52 :: DRAM_USER_DEFINED_DNMX_COEFFS [15:00] */
-#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_17_TO_52_DRAM_USER_DEFINED_DNMX_COEFFS_MASK 0xffff
-#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_17_TO_52_DRAM_USER_DEFINED_DNMX_COEFFS_SHIFT 0
-#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_17_TO_52_DRAM_USER_DEFINED_DNMX_COEFFS_Full_scale 32767
-#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_17_TO_52_DRAM_USER_DEFINED_DNMX_COEFFS_Mute 0
-
-/***************************************************************************
- *AC3_UPS_WORD_53 - AC3 User Parameters Structure Word 53 - DUMMY
- ***************************************************************************/
-/* RAAGA_REGSET_DSP_CFG :: AC3_UPS_WORD_53 :: DUMMY [15:00] */
-#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_53_DUMMY_MASK 0xffff
-#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_53_DUMMY_SHIFT 0
-
-/***************************************************************************
- *AC3_PLUS_UPS_WORD_00 - AC3 Plus User Parameters Structure Word 0 - COMPMODE
- ***************************************************************************/
-/* RAAGA_REGSET_DSP_CFG :: AC3_PLUS_UPS_WORD_00 :: COMPMODE [31:00] */
-#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_00_COMPMODE_MASK 0xffffffff
-#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_00_COMPMODE_SHIFT 0
-
-/***************************************************************************
- *AC3_PLUS_UPS_WORD_01 - AC3 Plus User Parameters Structure Word 1 - PCMSCALE
- ***************************************************************************/
-/* RAAGA_REGSET_DSP_CFG :: AC3_PLUS_UPS_WORD_01 :: PCMSCALE [31:00] */
-#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_01_PCMSCALE_MASK 0xffffffff
-#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_01_PCMSCALE_SHIFT 0
-#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_01_PCMSCALE_Full_scale 2147483647
-#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_01_PCMSCALE_Mute 0
-
-/***************************************************************************
- *AC3_PLUS_UPS_WORD_02 - AC3 Plus User Parameters Structure Word 2 - DYNSCALEHIGH
- ***************************************************************************/
-/* RAAGA_REGSET_DSP_CFG :: AC3_PLUS_UPS_WORD_02 :: DYNSCALEHIGH [31:00] */
-#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_02_DYNSCALEHIGH_MASK 0xffffffff
-#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_02_DYNSCALEHIGH_SHIFT 0
-
-/***************************************************************************
- *AC3_PLUS_UPS_WORD_03 - AC3 Plus User Parameters Structure Word 3 - DYNSCALELOW
- ***************************************************************************/
-/* RAAGA_REGSET_DSP_CFG :: AC3_PLUS_UPS_WORD_03 :: DYNSCALELOW [31:00] */
-#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_03_DYNSCALELOW_MASK 0xffffffff
-#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_03_DYNSCALELOW_SHIFT 0
-
-/***************************************************************************
- *AC3_PLUS_UPS_WORD_04 - AC3 Plus User Parameters Structure Word 4 - OUTLFE
- ***************************************************************************/
-/* RAAGA_REGSET_DSP_CFG :: AC3_PLUS_UPS_WORD_04 :: OUTLFE [31:00] */
-#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_04_OUTLFE_MASK 0xffffffff
-#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_04_OUTLFE_SHIFT 0
-
-/***************************************************************************
- *AC3_PLUS_UPS_WORD_05 - AC3 Plus User Parameters Structure Word 5 - OUTMODE
- ***************************************************************************/
-/* RAAGA_REGSET_DSP_CFG :: AC3_PLUS_UPS_WORD_05 :: OUTMODE [31:00] */
-#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_05_OUTMODE_MASK 0xffffffff
-#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_05_OUTMODE_SHIFT 0
-
-/***************************************************************************
- *AC3_PLUS_UPS_WORD_06 - AC3 Plus User Parameters Structure Word 6 - STEREOMODE
- ***************************************************************************/
-/* RAAGA_REGSET_DSP_CFG :: AC3_PLUS_UPS_WORD_06 :: STEREOMODE [31:00] */
-#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_06_STEREOMODE_MASK 0xffffffff
-#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_06_STEREOMODE_SHIFT 0
-
-/***************************************************************************
- *AC3_PLUS_UPS_WORD_07 - AC3 Plus User Parameters Structure Word 7 - DUALMODE
- ***************************************************************************/
-/* RAAGA_REGSET_DSP_CFG :: AC3_PLUS_UPS_WORD_07 :: DUALMODE [31:00] */
-#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_07_DUALMODE_MASK 0xffffffff
-#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_07_DUALMODE_SHIFT 0
-
-/***************************************************************************
- *AC3_PLUS_UPS_WORD_08 - AC3 Plus User Parameters Structure Word 8 - KMODE
- ***************************************************************************/
-/* RAAGA_REGSET_DSP_CFG :: AC3_PLUS_UPS_WORD_08 :: KMODE [31:00] */
-#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_08_KMODE_MASK 0xffffffff
-#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_08_KMODE_SHIFT 0
-#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_08_KMODE_NO_VOCALS 0
-#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_08_KMODE_GBL_VOCAL1 1
-#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_08_KMODE_GBL_VOCAL2 2
-#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_08_KMODE_GBL_BOTH_VOCALS 3
-
-/***************************************************************************
- *AC3_PLUS_UPS_WORD_09 - AC3 Plus User Parameters Structure Word 9 - EXTDNMIX_ENABLED
- ***************************************************************************/
-/* RAAGA_REGSET_DSP_CFG :: AC3_PLUS_UPS_WORD_09 :: EXTDNMIX_ENABLED [31:00] */
-#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_09_EXTDNMIX_ENABLED_MASK 0xffffffff
-#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_09_EXTDNMIX_ENABLED_SHIFT 0
-
-/***************************************************************************
- *AC3_PLUS_UPS_WORD_10_TO_45 - AC3 Plus User Parameters Structure Word 10 to 45 - EXTDNMIXTAB
- ***************************************************************************/
-/* RAAGA_REGSET_DSP_CFG :: AC3_PLUS_UPS_WORD_10_TO_45 :: EXTDNMIXTAB [31:00] */
-#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_10_TO_45_EXTDNMIXTAB_MASK 0xffffffff
-#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_10_TO_45_EXTDNMIXTAB_SHIFT 0
-#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_10_TO_45_EXTDNMIXTAB_Full_scale 2147483647
-#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_10_TO_45_EXTDNMIXTAB_Mute 0
-
-/***************************************************************************
- *AC3_PLUS_UPS_WORD_46 - AC3 Plus User Parameters Structure Word 46 - EXTKARAOKE_ENABLED
- ***************************************************************************/
-/* RAAGA_REGSET_DSP_CFG :: AC3_PLUS_UPS_WORD_46 :: EXTKARAOKE_ENABLED [31:00] */
-#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_46_EXTKARAOKE_ENABLED_MASK 0xffffffff
-#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_46_EXTKARAOKE_ENABLED_SHIFT 0
-
-/***************************************************************************
- *AC3_PLUS_UPS_WORD_47 - AC3 Plus User Parameters Structure Word 47 - EXT_V1_LEVEL
- ***************************************************************************/
-/* RAAGA_REGSET_DSP_CFG :: AC3_PLUS_UPS_WORD_47 :: EXT_V1_LEVEL [31:00] */
-#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_47_EXT_V1_LEVEL_MASK 0xffffffff
-#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_47_EXT_V1_LEVEL_SHIFT 0
-#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_47_EXT_V1_LEVEL_Full_scale 2147483647
-#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_47_EXT_V1_LEVEL_Mute 0
-
-/***************************************************************************
- *AC3_PLUS_UPS_WORD_48 - AC3 Plus User Parameters Structure Word 48 - EXT_V1_PAN
- ***************************************************************************/
-/* RAAGA_REGSET_DSP_CFG :: AC3_PLUS_UPS_WORD_48 :: EXT_V1_PAN [31:00] */
-#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_48_EXT_V1_PAN_MASK 0xffffffff
-#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_48_EXT_V1_PAN_SHIFT 0
-#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_48_EXT_V1_PAN_Hard_left 2147483647
-#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_48_EXT_V1_PAN_Middle 0
-#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_48_EXT_V1_PAN_Hard_right -2147483648
-
-/***************************************************************************
- *AC3_PLUS_UPS_WORD_49 - AC3 Plus User Parameters Structure Word 49 - EXT_V2_LEVEL
- ***************************************************************************/
-/* RAAGA_REGSET_DSP_CFG :: AC3_PLUS_UPS_WORD_49 :: EXT_V2_LEVEL [31:00] */
-#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_49_EXT_V2_LEVEL_MASK 0xffffffff
-#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_49_EXT_V2_LEVEL_SHIFT 0
-#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_49_EXT_V2_LEVEL_Full_scale 2147483647
-#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_49_EXT_V2_LEVEL_Mute 0
-
-/***************************************************************************
- *AC3_PLUS_UPS_WORD_50 - AC3 Plus User Parameters Structure Word 50 - EXT_V2_PAN
- ***************************************************************************/
-/* RAAGA_REGSET_DSP_CFG :: AC3_PLUS_UPS_WORD_50 :: EXT_V2_PAN [31:00] */
-#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_50_EXT_V2_PAN_MASK 0xffffffff
-#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_50_EXT_V2_PAN_SHIFT 0
-#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_50_EXT_V2_PAN_Hard_left 2147483647
-#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_50_EXT_V2_PAN_Middle 0
-#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_50_EXT_V2_PAN_Hard_right -2147483648
-
-/***************************************************************************
- *AC3_PLUS_UPS_WORD_51 - AC3 Plus User Parameters Structure Word 51 - EXT_GM_LEVEL
- ***************************************************************************/
-/* RAAGA_REGSET_DSP_CFG :: AC3_PLUS_UPS_WORD_51 :: EXT_GM_LEVEL [31:00] */
-#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_51_EXT_GM_LEVEL_MASK 0xffffffff
-#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_51_EXT_GM_LEVEL_SHIFT 0
-#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_51_EXT_GM_LEVEL_Full_scale 2147483647
-#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_51_EXT_GM_LEVEL_Mute 0
-
-/***************************************************************************
- *AC3_PLUS_UPS_WORD_52 - AC3 Plus User Parameters Structure Word 52 - EXT_GM_PAN
- ***************************************************************************/
-/* RAAGA_REGSET_DSP_CFG :: AC3_PLUS_UPS_WORD_52 :: EXT_GM_PAN [31:00] */
-#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_52_EXT_GM_PAN_MASK 0xffffffff
-#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_52_EXT_GM_PAN_SHIFT 0
-#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_52_EXT_GM_PAN_Hard_left 2147483647
-#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_52_EXT_GM_PAN_Middle 0
-#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_52_EXT_GM_PAN_Hard_right -2147483648
-
-/***************************************************************************
- *AAC_UPS_WORD_00 - AAC User Parameters Structure Word 0 - XPT_FORMAT
- ***************************************************************************/
-/* RAAGA_REGSET_DSP_CFG :: AAC_UPS_WORD_00 :: XPT_FORMAT [31:00] */
-#define BCHP_RAAGA_REGSET_DSP_CFG_AAC_UPS_WORD_00_XPT_FORMAT_MASK 0xffffffff
-#define BCHP_RAAGA_REGSET_DSP_CFG_AAC_UPS_WORD_00_XPT_FORMAT_SHIFT 0
-
-/***************************************************************************
- *AAC_UPS_WORD_01 - AAC User Parameters Structure Word 1 - DRC_GAIN_CONTROL_COMPRESS
- ***************************************************************************/
-/* RAAGA_REGSET_DSP_CFG :: AAC_UPS_WORD_01 :: DRC_GAIN_CONTROL_COMPRESS [31:00] */
-#define BCHP_RAAGA_REGSET_DSP_CFG_AAC_UPS_WORD_01_DRC_GAIN_CONTROL_COMPRESS_MASK 0xffffffff
-#define BCHP_RAAGA_REGSET_DSP_CFG_AAC_UPS_WORD_01_DRC_GAIN_CONTROL_COMPRESS_SHIFT 0
-
-/***************************************************************************
- *AAC_UPS_WORD_02 - AAC User Parameters Structure Word 2 - DRC_GAIN_CONTROL_BOOST
- ***************************************************************************/
-/* RAAGA_REGSET_DSP_CFG :: AAC_UPS_WORD_02 :: DRC_GAIN_CONTROL_BOOST [31:00] */
-#define BCHP_RAAGA_REGSET_DSP_CFG_AAC_UPS_WORD_02_DRC_GAIN_CONTROL_BOOST_MASK 0xffffffff
-#define BCHP_RAAGA_REGSET_DSP_CFG_AAC_UPS_WORD_02_DRC_GAIN_CONTROL_BOOST_SHIFT 0
-
-/***************************************************************************
- *AAC_UPS_WORD_03 - AAC User Parameters Structure Word 3 - DRC_TARGET_LEVEL
- ***************************************************************************/
-/* RAAGA_REGSET_DSP_CFG :: AAC_UPS_WORD_03 :: DRC_TARGET_LEVEL [31:00] */
-#define BCHP_RAAGA_REGSET_DSP_CFG_AAC_UPS_WORD_03_DRC_TARGET_LEVEL_MASK 0xffffffff
-#define BCHP_RAAGA_REGSET_DSP_CFG_AAC_UPS_WORD_03_DRC_TARGET_LEVEL_SHIFT 0
-
-/***************************************************************************
- *AAC_UPS_WORD_04 - AAC User Parameters Structure Word 4 - DOWNMIX_TYPE
- ***************************************************************************/
-/* RAAGA_REGSET_DSP_CFG :: AAC_UPS_WORD_04 :: DOWNMIX_TYPE [31:00] */
-#define BCHP_RAAGA_REGSET_DSP_CFG_AAC_UPS_WORD_04_DOWNMIX_TYPE_MASK 0xffffffff
-#define BCHP_RAAGA_REGSET_DSP_CFG_AAC_UPS_WORD_04_DOWNMIX_TYPE_SHIFT 0
-
-/***************************************************************************
- *AAC_UPS_WORD_05 - AAC User Parameters Structure Word 5 - OUTMODE
- ***************************************************************************/
-/* RAAGA_REGSET_DSP_CFG :: AAC_UPS_WORD_05 :: OUTMODE [31:00] */
-#define BCHP_RAAGA_REGSET_DSP_CFG_AAC_UPS_WORD_05_OUTMODE_MASK 0xffffffff
-#define BCHP_RAAGA_REGSET_DSP_CFG_AAC_UPS_WORD_05_OUTMODE_SHIFT 0
-#define BCHP_RAAGA_REGSET_DSP_CFG_AAC_UPS_WORD_05_OUTMODE_Stereo 2
-#define BCHP_RAAGA_REGSET_DSP_CFG_AAC_UPS_WORD_05_OUTMODE_Mono 1
-
-/***************************************************************************
- *AAC_UPS_WORD_06 - AAC User Parameters Structure Word 6 - DUALMODE
- ***************************************************************************/
-/* RAAGA_REGSET_DSP_CFG :: AAC_UPS_WORD_06 :: DUALMODE [31:00] */
-#define BCHP_RAAGA_REGSET_DSP_CFG_AAC_UPS_WORD_06_DUALMODE_MASK 0xffffffff
-#define BCHP_RAAGA_REGSET_DSP_CFG_AAC_UPS_WORD_06_DUALMODE_SHIFT 0
-#define BCHP_RAAGA_REGSET_DSP_CFG_AAC_UPS_WORD_06_DUALMODE_Left_mono 0
-#define BCHP_RAAGA_REGSET_DSP_CFG_AAC_UPS_WORD_06_DUALMODE_Right_mono 1
-#define BCHP_RAAGA_REGSET_DSP_CFG_AAC_UPS_WORD_06_DUALMODE_Dual_stereo 2
-#define BCHP_RAAGA_REGSET_DSP_CFG_AAC_UPS_WORD_06_DUALMODE_Dual_mixmono 3
-
-/***************************************************************************
- *DTS_CORE_UPS_WORD_00 - DTS Core User Parameters Structure Word 0 - OUTMODE
- ***************************************************************************/
-/* RAAGA_REGSET_DSP_CFG :: DTS_CORE_UPS_WORD_00 :: OUTMODE [31:00] */
-#define BCHP_RAAGA_REGSET_DSP_CFG_DTS_CORE_UPS_WORD_00_OUTMODE_MASK 0xffffffff
-#define BCHP_RAAGA_REGSET_DSP_CFG_DTS_CORE_UPS_WORD_00_OUTMODE_SHIFT 0
-#define BCHP_RAAGA_REGSET_DSP_CFG_DTS_CORE_UPS_WORD_00_OUTMODE_Stereo 0
-#define BCHP_RAAGA_REGSET_DSP_CFG_DTS_CORE_UPS_WORD_00_OUTMODE_Mono 1
-
-/***************************************************************************
- *DTS_CORE_UPS_WORD_01 - DTS Core User Parameters Structure Word 1 - OUTLFE
- ***************************************************************************/
-/* RAAGA_REGSET_DSP_CFG :: DTS_CORE_UPS_WORD_01 :: OUTLFE [31:00] */
-#define BCHP_RAAGA_REGSET_DSP_CFG_DTS_CORE_UPS_WORD_01_OUTLFE_MASK 0xffffffff
-#define BCHP_RAAGA_REGSET_DSP_CFG_DTS_CORE_UPS_WORD_01_OUTLFE_SHIFT 0
-
-/***************************************************************************
- *DTS_CORE_UPS_WORD_02 - DTS Core User Parameters Structure Word 2 - DUALMODE
- ***************************************************************************/
-/* RAAGA_REGSET_DSP_CFG :: DTS_CORE_UPS_WORD_02 :: DUALMODE [31:00] */
-#define BCHP_RAAGA_REGSET_DSP_CFG_DTS_CORE_UPS_WORD_02_DUALMODE_MASK 0xffffffff
-#define BCHP_RAAGA_REGSET_DSP_CFG_DTS_CORE_UPS_WORD_02_DUALMODE_SHIFT 0
-#define BCHP_RAAGA_REGSET_DSP_CFG_DTS_CORE_UPS_WORD_02_DUALMODE_Dual_stereo 0
-#define BCHP_RAAGA_REGSET_DSP_CFG_DTS_CORE_UPS_WORD_02_DUALMODE_Dual_leftmono 1
-#define BCHP_RAAGA_REGSET_DSP_CFG_DTS_CORE_UPS_WORD_02_DUALMODE_Dual_rghtmono 2
-#define BCHP_RAAGA_REGSET_DSP_CFG_DTS_CORE_UPS_WORD_02_DUALMODE_Dual_mixmono 3
-
-/***************************************************************************
- *DTS_CORE_UPS_WORD_03 - DTS Core User Parameters Structure Word 3 - STEREOMODE
- ***************************************************************************/
-/* RAAGA_REGSET_DSP_CFG :: DTS_CORE_UPS_WORD_03 :: STEREOMODE [31:00] */
-#define BCHP_RAAGA_REGSET_DSP_CFG_DTS_CORE_UPS_WORD_03_STEREOMODE_MASK 0xffffffff
-#define BCHP_RAAGA_REGSET_DSP_CFG_DTS_CORE_UPS_WORD_03_STEREOMODE_SHIFT 0
-#define BCHP_RAAGA_REGSET_DSP_CFG_DTS_CORE_UPS_WORD_03_STEREOMODE_Stereomode_auto 0
-#define BCHP_RAAGA_REGSET_DSP_CFG_DTS_CORE_UPS_WORD_03_STEREOMODE_Stereodmix_LTRT 1
-#define BCHP_RAAGA_REGSET_DSP_CFG_DTS_CORE_UPS_WORD_03_STEREOMODE_Stereodmix_LORO 2
-
-/***************************************************************************
- *DTS_CORE_UPS_WORD_04 - DTS Core User Parameters Structure Word 4 - EXTDNMIX_ENABLED
- ***************************************************************************/
-/* RAAGA_REGSET_DSP_CFG :: DTS_CORE_UPS_WORD_04 :: EXTDNMIX_ENABLED [31:00] */
-#define BCHP_RAAGA_REGSET_DSP_CFG_DTS_CORE_UPS_WORD_04_EXTDNMIX_ENABLED_MASK 0xffffffff
-#define BCHP_RAAGA_REGSET_DSP_CFG_DTS_CORE_UPS_WORD_04_EXTDNMIX_ENABLED_SHIFT 0
-
-/***************************************************************************
- *DTS_CORE_UPS_WORD_05_TO_40 - DTS Core User Parameters Structure Word 5 to 40 - EXTDNMIXTAB
- ***************************************************************************/
-/* RAAGA_REGSET_DSP_CFG :: DTS_CORE_UPS_WORD_05_TO_40 :: EXTDNMIXTAB [31:00] */
-#define BCHP_RAAGA_REGSET_DSP_CFG_DTS_CORE_UPS_WORD_05_TO_40_EXTDNMIXTAB_MASK 0xffffffff
-#define BCHP_RAAGA_REGSET_DSP_CFG_DTS_CORE_UPS_WORD_05_TO_40_EXTDNMIXTAB_SHIFT 0
-#define BCHP_RAAGA_REGSET_DSP_CFG_DTS_CORE_UPS_WORD_05_TO_40_EXTDNMIXTAB_Full_scale 2147483647
-#define BCHP_RAAGA_REGSET_DSP_CFG_DTS_CORE_UPS_WORD_05_TO_40_EXTDNMIXTAB_Mute 0
-
-/***************************************************************************
- *LPCM_UPS_WORD_00 - LPCM User Parameters Structure Word 0 - EXTDNMIX_ENABLED
- ***************************************************************************/
-/* RAAGA_REGSET_DSP_CFG :: LPCM_UPS_WORD_00 :: EXTDNMIX_ENABLED [31:00] */
-#define BCHP_RAAGA_REGSET_DSP_CFG_LPCM_UPS_WORD_00_EXTDNMIX_ENABLED_MASK 0xffffffff
-#define BCHP_RAAGA_REGSET_DSP_CFG_LPCM_UPS_WORD_00_EXTDNMIX_ENABLED_SHIFT 0
-
-/***************************************************************************
- *LPCM_UPS_WORD_01_TO_16 - LPCM User Parameters Structure Word 1 to 16 - EXTDNMIXTAB
- ***************************************************************************/
-/* RAAGA_REGSET_DSP_CFG :: LPCM_UPS_WORD_01_TO_16 :: EXTDNMIXTAB [31:00] */
-#define BCHP_RAAGA_REGSET_DSP_CFG_LPCM_UPS_WORD_01_TO_16_EXTDNMIXTAB_MASK 0xffffffff
-#define BCHP_RAAGA_REGSET_DSP_CFG_LPCM_UPS_WORD_01_TO_16_EXTDNMIXTAB_SHIFT 0
-#define BCHP_RAAGA_REGSET_DSP_CFG_LPCM_UPS_WORD_01_TO_16_EXTDNMIXTAB_Full_scale 2147483647
-#define BCHP_RAAGA_REGSET_DSP_CFG_LPCM_UPS_WORD_01_TO_16_EXTDNMIXTAB_Mute 0
-
-/***************************************************************************
- *MPEG_UPS_WORD_00 - MPEG User Parameters Structure Word 0 - OUTMODE
- ***************************************************************************/
-/* RAAGA_REGSET_DSP_CFG :: MPEG_UPS_WORD_00 :: OUTMODE [31:00] */
-#define BCHP_RAAGA_REGSET_DSP_CFG_MPEG_UPS_WORD_00_OUTMODE_MASK 0xffffffff
-#define BCHP_RAAGA_REGSET_DSP_CFG_MPEG_UPS_WORD_00_OUTMODE_SHIFT 0
-#define BCHP_RAAGA_REGSET_DSP_CFG_MPEG_UPS_WORD_00_OUTMODE_Stereo 0
-#define BCHP_RAAGA_REGSET_DSP_CFG_MPEG_UPS_WORD_00_OUTMODE_Mono 1
-
-/***************************************************************************
- *MPEG_UPS_WORD_01 - MPEG User Parameters Structure Word 1 - DUALMODE
- ***************************************************************************/
-/* RAAGA_REGSET_DSP_CFG :: MPEG_UPS_WORD_01 :: DUALMODE [31:00] */
-#define BCHP_RAAGA_REGSET_DSP_CFG_MPEG_UPS_WORD_01_DUALMODE_MASK 0xffffffff
-#define BCHP_RAAGA_REGSET_DSP_CFG_MPEG_UPS_WORD_01_DUALMODE_SHIFT 0
-#define BCHP_RAAGA_REGSET_DSP_CFG_MPEG_UPS_WORD_01_DUALMODE_Left_mono 0
-#define BCHP_RAAGA_REGSET_DSP_CFG_MPEG_UPS_WORD_01_DUALMODE_Right_mono 1
-#define BCHP_RAAGA_REGSET_DSP_CFG_MPEG_UPS_WORD_01_DUALMODE_Dual_stereo 2
-#define BCHP_RAAGA_REGSET_DSP_CFG_MPEG_UPS_WORD_01_DUALMODE_Dual_mixmono 3
-
-/***************************************************************************
- *RDC
- ***************************************************************************/
-/***************************************************************************
- *RUL - RUL Command.
- ***************************************************************************/
-/* RDC :: RUL :: opcode [31:24] */
-#define BCHP_RDC_RUL_opcode_MASK 0xff000000
-#define BCHP_RDC_RUL_opcode_SHIFT 24
-#define BCHP_RDC_RUL_opcode_NOP 0
-#define BCHP_RDC_RUL_opcode_REG_WRITE_IMM 1
-#define BCHP_RDC_RUL_opcode_REG_WRITE 2
-#define BCHP_RDC_RUL_opcode_REG_READ 3
-#define BCHP_RDC_RUL_opcode_LOAD_IMM 4
-#define BCHP_RDC_RUL_opcode_WINDOW_WRITE 5
-#define BCHP_RDC_RUL_opcode_BLOCK_WRITE 6
-#define BCHP_RDC_RUL_opcode_WINDOW_COPY 7
-#define BCHP_RDC_RUL_opcode_BLOCK_COPY 8
-#define BCHP_RDC_RUL_opcode_WINDOW_TO_BLOCK 9
-#define BCHP_RDC_RUL_opcode_BLOCK_TO_WINDOW 10
-#define BCHP_RDC_RUL_opcode_AND 11
-#define BCHP_RDC_RUL_opcode_AND_IMM 12
-#define BCHP_RDC_RUL_opcode_OR 13
-#define BCHP_RDC_RUL_opcode_OR_IMM 14
-#define BCHP_RDC_RUL_opcode_XOR 15
-#define BCHP_RDC_RUL_opcode_XOR_IMM 16
-#define BCHP_RDC_RUL_opcode_NOT 17
-#define BCHP_RDC_RUL_opcode_ROTATE_RIGHT 18
-#define BCHP_RDC_RUL_opcode_SUM 19
-#define BCHP_RDC_RUL_opcode_SUM_IMM 20
-#define BCHP_RDC_RUL_opcode_COND_SKIP 21
-#define BCHP_RDC_RUL_opcode_SKIP 22
-#define BCHP_RDC_RUL_opcode_EXIT 23
-#define BCHP_RDC_RUL_opcode_WAIT_EOP 24
-#define BCHP_RDC_RUL_opcode_PLACEHOLDER 255
-
-/* RDC :: RUL :: reserved0 [23:23] */
-#define BCHP_RDC_RUL_reserved0_MASK 0x00800000
-#define BCHP_RDC_RUL_reserved0_SHIFT 23
-
-/* union - case rdc_args [22:00] */
-/* RDC :: RUL :: rdc_args :: rotation [22:18] */
-#define BCHP_RDC_RUL_rdc_args_rotation_MASK 0x007c0000
-#define BCHP_RDC_RUL_rdc_args_rotation_SHIFT 18
-
-/* RDC :: RUL :: rdc_args :: src1 [17:12] */
-#define BCHP_RDC_RUL_rdc_args_src1_MASK 0x0003f000
-#define BCHP_RDC_RUL_rdc_args_src1_SHIFT 12
-
-/* RDC :: RUL :: rdc_args :: src2 [11:06] */
-#define BCHP_RDC_RUL_rdc_args_src2_MASK 0x00000fc0
-#define BCHP_RDC_RUL_rdc_args_src2_SHIFT 6
-
-/* RDC :: RUL :: rdc_args :: dest [05:00] */
-#define BCHP_RDC_RUL_rdc_args_dest_MASK 0x0000003f
-#define BCHP_RDC_RUL_rdc_args_dest_SHIFT 0
-
-/* union - case reg_args [22:00] */
-/* RDC :: RUL :: reg_args :: rotation [22:18] */
-#define BCHP_RDC_RUL_reg_args_rotation_MASK 0x007c0000
-#define BCHP_RDC_RUL_reg_args_rotation_SHIFT 18
-
-/* RDC :: RUL :: reg_args :: src1 [17:12] */
-#define BCHP_RDC_RUL_reg_args_src1_MASK 0x0003f000
-#define BCHP_RDC_RUL_reg_args_src1_SHIFT 12
-
-/* RDC :: RUL :: reg_args :: count [11:00] */
-#define BCHP_RDC_RUL_reg_args_count_MASK 0x00000fff
-#define BCHP_RDC_RUL_reg_args_count_SHIFT 0
-
-/* union - case eop_args [22:00] */
-/* RDC :: RUL :: eop_args :: reserved0 [22:08] */
-#define BCHP_RDC_RUL_eop_args_reserved0_MASK 0x007fff00
-#define BCHP_RDC_RUL_eop_args_reserved0_SHIFT 8
-
-/* RDC :: RUL :: eop_args :: eop [07:00] */
-#define BCHP_RDC_RUL_eop_args_eop_MASK 0x000000ff
-#define BCHP_RDC_RUL_eop_args_eop_SHIFT 0
-
-/***************************************************************************
- *EOP_ID_256 - EOP_ID
- ***************************************************************************/
-/* RDC :: EOP_ID_256 :: eop_id [255:00] */
-#define BCHP_RDC_EOP_ID_256_eop_id_MASK 0x00000000000000000000000000000000000000000000000000000000ffffffff
-#define BCHP_RDC_EOP_ID_256_eop_id_SHIFT 0
-#define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_scl_0 0
-#define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_scl_1 1
-#define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_scl_2 2
-#define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_scl_3 3
-#define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_scl_4 4
-#define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_scl_5 5
-#define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_scl_6 6
-#define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_scl_7 7
-#define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_mvp_0 8
-#define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_mvp_1 9
-#define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_mvp_2 10
-#define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_mvp_3 11
-#define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_mvp_4 12
-#define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_mvp_5 13
-#define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_mvp_6 14
-#define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_mvp_7 15
-#define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_dnr_0 16
-#define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_dnr_1 17
-#define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_dnr_2 18
-#define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_dnr_3 19
-#define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_dnr_4 20
-#define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_dnr_5 21
-#define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_dnr_6 22
-#define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_dnr_7 23
-#define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_lbox_0 24
-#define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_lbox_1 25
-#define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_lbox_2 26
-#define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_lbox_3 27
-#define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_lbox_4 28
-#define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_lbox_5 29
-#define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_lbox_6 30
-#define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_pfa_0 31
-#define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_null_0 32
-#define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_null_1 33
-#define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_null_2 34
-#define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_null_3 35
-#define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_null_4 36
-#define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_null_5 37
-#define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_null_6 38
-#define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_null_7 39
-#define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_nvp_0 40
-#define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_s3dh_0 41
-#define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_v0_be 42
-#define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_reserved_0 43
-#define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_reserved_1 44
-#define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_reserved_2 45
-#define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_reserved_3 46
-#define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_reserved_4 47
-#define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_fch_0 48
-#define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_fch_1 49
-#define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_fch_2 50
-#define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_fch_3 51
-#define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_fch_4 52
-#define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_fch_5 53
-#define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_fch_6 54
-#define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_fch_7 55
-#define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_fch_8 56
-#define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_fch_9 57
-#define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_fch_10 58
-#define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_fch_11 59
-#define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_fch_12 60
-#define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_fch_13 61
-#define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_tntd_0 62
-#define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_hscl_0 63
-#define BCHP_RDC_EOP_ID_256_eop_id_mfd_0 64
-#define BCHP_RDC_EOP_ID_256_eop_id_mfd_1 65
-#define BCHP_RDC_EOP_ID_256_eop_id_mfd_2 66
-#define BCHP_RDC_EOP_ID_256_eop_id_mfd_3 67
-#define BCHP_RDC_EOP_ID_256_eop_id_mfd_4 68
-#define BCHP_RDC_EOP_ID_256_eop_id_mfd_5 69
-#define BCHP_RDC_EOP_ID_256_eop_id_mfd_6 70
-#define BCHP_RDC_EOP_ID_256_eop_id_mfd_7 71
-#define BCHP_RDC_EOP_ID_256_eop_id_vfd_0 72
-#define BCHP_RDC_EOP_ID_256_eop_id_vfd_1 73
-#define BCHP_RDC_EOP_ID_256_eop_id_vfd_2 74
-#define BCHP_RDC_EOP_ID_256_eop_id_vfd_3 75
-#define BCHP_RDC_EOP_ID_256_eop_id_vfd_4 76
-#define BCHP_RDC_EOP_ID_256_eop_id_vfd_5 77
-#define BCHP_RDC_EOP_ID_256_eop_id_vfd_6 78
-#define BCHP_RDC_EOP_ID_256_eop_id_vfd_7 79
-#define BCHP_RDC_EOP_ID_256_eop_id_cap_0 80
-#define BCHP_RDC_EOP_ID_256_eop_id_cap_1 81
-#define BCHP_RDC_EOP_ID_256_eop_id_cap_2 82
-#define BCHP_RDC_EOP_ID_256_eop_id_cap_3 83
-#define BCHP_RDC_EOP_ID_256_eop_id_cap_4 84
-#define BCHP_RDC_EOP_ID_256_eop_id_cap_5 85
-#define BCHP_RDC_EOP_ID_256_eop_id_cap_6 86
-#define BCHP_RDC_EOP_ID_256_eop_id_cap_7 87
-#define BCHP_RDC_EOP_ID_256_eop_id_gfd_0 88
-#define BCHP_RDC_EOP_ID_256_eop_id_gfd_1 89
-#define BCHP_RDC_EOP_ID_256_eop_id_gfd_2 90
-#define BCHP_RDC_EOP_ID_256_eop_id_gfd_3 91
-#define BCHP_RDC_EOP_ID_256_eop_id_gfd_4 92
-#define BCHP_RDC_EOP_ID_256_eop_id_gfd_5 93
-#define BCHP_RDC_EOP_ID_256_eop_id_gfd_6 94
-#define BCHP_RDC_EOP_ID_256_eop_id_gfd_7 95
-#define BCHP_RDC_EOP_ID_256_eop_id_scl_0 96
-#define BCHP_RDC_EOP_ID_256_eop_id_scl_1 97
-#define BCHP_RDC_EOP_ID_256_eop_id_scl_2 98
-#define BCHP_RDC_EOP_ID_256_eop_id_scl_3 99
-#define BCHP_RDC_EOP_ID_256_eop_id_scl_4 100
-#define BCHP_RDC_EOP_ID_256_eop_id_scl_5 101
-#define BCHP_RDC_EOP_ID_256_eop_id_scl_6 102
-#define BCHP_RDC_EOP_ID_256_eop_id_scl_7 103
-#define BCHP_RDC_EOP_ID_256_eop_id_hscl_0 104
-#define BCHP_RDC_EOP_ID_256_eop_id_hscl_1 105
-#define BCHP_RDC_EOP_ID_256_eop_id_hscl_2 106
-#define BCHP_RDC_EOP_ID_256_eop_id_hscl_3 107
-#define BCHP_RDC_EOP_ID_256_eop_id_hscl_4 108
-#define BCHP_RDC_EOP_ID_256_eop_id_hscl_5 109
-#define BCHP_RDC_EOP_ID_256_eop_id_hscl_6 110
-#define BCHP_RDC_EOP_ID_256_eop_id_hscl_7 111
-#define BCHP_RDC_EOP_ID_256_eop_id_mvp_0 112
-#define BCHP_RDC_EOP_ID_256_eop_id_mvp_1 113
-#define BCHP_RDC_EOP_ID_256_eop_id_mvp_2 114
-#define BCHP_RDC_EOP_ID_256_eop_id_mvp_3 115
-#define BCHP_RDC_EOP_ID_256_eop_id_mvp_4 116
-#define BCHP_RDC_EOP_ID_256_eop_id_mvp_5 117
-#define BCHP_RDC_EOP_ID_256_eop_id_mvp_6 118
-#define BCHP_RDC_EOP_ID_256_eop_id_mvp_7 119
-#define BCHP_RDC_EOP_ID_256_eop_id_dnr_0 120
-#define BCHP_RDC_EOP_ID_256_eop_id_dnr_1 121
-#define BCHP_RDC_EOP_ID_256_eop_id_dnr_2 122
-#define BCHP_RDC_EOP_ID_256_eop_id_dnr_3 123
-#define BCHP_RDC_EOP_ID_256_eop_id_dnr_4 124
-#define BCHP_RDC_EOP_ID_256_eop_id_dnr_5 125
-#define BCHP_RDC_EOP_ID_256_eop_id_dnr_6 126
-#define BCHP_RDC_EOP_ID_256_eop_id_dnr_7 127
-#define BCHP_RDC_EOP_ID_256_eop_id_cmp_0 128
-#define BCHP_RDC_EOP_ID_256_eop_id_cmp_1 129
-#define BCHP_RDC_EOP_ID_256_eop_id_cmp_2 130
-#define BCHP_RDC_EOP_ID_256_eop_id_cmp_3 131
-#define BCHP_RDC_EOP_ID_256_eop_id_cmp_4 132
-#define BCHP_RDC_EOP_ID_256_eop_id_cmp_5 133
-#define BCHP_RDC_EOP_ID_256_eop_id_cmp_6 134
-#define BCHP_RDC_EOP_ID_256_eop_id_cmp_7 135
-#define BCHP_RDC_EOP_ID_256_eop_id_hd_dvi_0 136
-#define BCHP_RDC_EOP_ID_256_eop_id_hd_dvi_1 137
-#define BCHP_RDC_EOP_ID_256_eop_id_hd_dvi_2 138
-#define BCHP_RDC_EOP_ID_256_eop_id_hd_dvi_3 139
-#define BCHP_RDC_EOP_ID_256_eop_id_hd_dvi_4 140
-#define BCHP_RDC_EOP_ID_256_eop_id_hd_dvi_5 141
-#define BCHP_RDC_EOP_ID_256_eop_id_hd_dvi_6 142
-#define BCHP_RDC_EOP_ID_256_eop_id_tpg_0 143
-#define BCHP_RDC_EOP_ID_256_eop_id_vec_0 144
-#define BCHP_RDC_EOP_ID_256_eop_id_vec_1 145
-#define BCHP_RDC_EOP_ID_256_eop_id_vec_2 146
-#define BCHP_RDC_EOP_ID_256_eop_id_vec_3 147
-#define BCHP_RDC_EOP_ID_256_eop_id_vec_4 148
-#define BCHP_RDC_EOP_ID_256_eop_id_vec_5 149
-#define BCHP_RDC_EOP_ID_256_eop_id_vec_6 150
-#define BCHP_RDC_EOP_ID_256_eop_id_vec_7 151
-#define BCHP_RDC_EOP_ID_256_eop_id_lbox_0 152
-#define BCHP_RDC_EOP_ID_256_eop_id_lbox_1 153
-#define BCHP_RDC_EOP_ID_256_eop_id_lbox_2 154
-#define BCHP_RDC_EOP_ID_256_eop_id_lbox_3 155
-#define BCHP_RDC_EOP_ID_256_eop_id_lbox_4 156
-#define BCHP_RDC_EOP_ID_256_eop_id_lbox_5 157
-#define BCHP_RDC_EOP_ID_256_eop_id_lbox_6 158
-#define BCHP_RDC_EOP_ID_256_eop_id_pfa_0 159
-#define BCHP_RDC_EOP_ID_256_eop_id_crc_0 160
-#define BCHP_RDC_EOP_ID_256_eop_id_crc_1 161
-#define BCHP_RDC_EOP_ID_256_eop_id_crc_2 162
-#define BCHP_RDC_EOP_ID_256_eop_id_crc_3 163
-#define BCHP_RDC_EOP_ID_256_eop_id_hist_0 164
-#define BCHP_RDC_EOP_ID_256_eop_id_hist_1 165
-#define BCHP_RDC_EOP_ID_256_eop_id_psm_0 166
-#define BCHP_RDC_EOP_ID_256_eop_id_plm_0 167
-#define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_cap_0 168
-#define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_cap_1 169
-#define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_cap_2 170
-#define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_cap_3 171
-#define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_cap_4 172
-#define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_cap_5 173
-#define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_cap_6 174
-#define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_cap_7 175
-#define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_crc_0 176
-#define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_crc_1 177
-#define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_crc_2 178
-#define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_crc_3 179
-#define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_hist_0 180
-#define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_hist_1 181
-#define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_psm_0 182
-#define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_plm_0 183
-#define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_cmp_0_v0 184
-#define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_cmp_1_v0 185
-#define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_cmp_2_v0 186
-#define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_cmp_3_v0 187
-#define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_cmp_4_v0 188
-#define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_cmp_5_v0 189
-#define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_cmp_6_v0 190
-#define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_cmp_7_v0 191
-#define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_cmp_0_v1 192
-#define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_cmp_1_v1 193
-#define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_cmp_2_v1 194
-#define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_cmp_3_v1 195
-#define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_cmp_4_v1 196
-#define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_cmp_5_v1 197
-#define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_cmp_6_v1 198
-#define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_cmp_7_v1 199
-#define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_null_0 200
-#define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_null_1 201
-#define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_null_2 202
-#define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_null_3 203
-#define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_null_4 204
-#define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_null_5 205
-#define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_null_6 206
-#define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_null_7 207
-#define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_b3dc_0 208
-#define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_frc_0 209
-#define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_reserved_0 210
-#define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_reserved_1 211
-#define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_reserved_2 212
-#define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_reserved_3 213
-#define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_reserved_4 214
-#define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_reserved_5 215
-#define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_loopback_0 216
-#define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_loopback_1 217
-#define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_loopback_2 218
-#define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_loopback_3 219
-#define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_loopback_4 220
-#define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_loopback_5 221
-#define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_loopback_6 222
-#define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_loopback_7 223
-#define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_loopback_8 224
-#define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_loopback_9 225
-#define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_loopback_10 226
-#define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_loopback_11 227
-#define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_loopback_12 228
-#define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_loopback_13 229
-#define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_reserved_8 230
-#define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_reserved_9 231
-#define BCHP_RDC_EOP_ID_256_eop_id_nvp_0 232
-#define BCHP_RDC_EOP_ID_256_eop_id_s3dh_0 233
-#define BCHP_RDC_EOP_ID_256_eop_id_v0_be 234
-#define BCHP_RDC_EOP_ID_256_eop_id_reserved_0 235
-#define BCHP_RDC_EOP_ID_256_eop_id_reserved_1 236
-#define BCHP_RDC_EOP_ID_256_eop_id_reserved_2 237
-#define BCHP_RDC_EOP_ID_256_eop_id_reserved_3 238
-#define BCHP_RDC_EOP_ID_256_eop_id_reserved_4 239
-#define BCHP_RDC_EOP_ID_256_eop_id_b3dc_0 240
-#define BCHP_RDC_EOP_ID_256_eop_id_frc_0 241
-#define BCHP_RDC_EOP_ID_256_eop_id_pdpf_0 242
-#define BCHP_RDC_EOP_ID_256_eop_id_pdpb_0 243
-#define BCHP_RDC_EOP_ID_256_eop_id_reserved_5 244
-#define BCHP_RDC_EOP_ID_256_eop_id_reserved_6 245
-#define BCHP_RDC_EOP_ID_256_eop_id_reserved_7 246
-#define BCHP_RDC_EOP_ID_256_eop_id_reserved_8 247
-#define BCHP_RDC_EOP_ID_256_eop_id_tntd_0 248
-#define BCHP_RDC_EOP_ID_256_eop_id_reserved_10 249
-#define BCHP_RDC_EOP_ID_256_eop_id_reserved_11 250
-#define BCHP_RDC_EOP_ID_256_eop_id_reserved_12 251
-#define BCHP_RDC_EOP_ID_256_eop_id_reserved_13 252
-#define BCHP_RDC_EOP_ID_256_eop_id_reserved_14 253
-#define BCHP_RDC_EOP_ID_256_eop_id_reserved_15 254
-#define BCHP_RDC_EOP_ID_256_eop_id_reserved_16 255
-
-/***************************************************************************
- *SPDIF_RCVR_CTRL
- ***************************************************************************/
-/***************************************************************************
- *ABSTRACT_INTERRUPT_HANDLING - Interrupt Handling
- ***************************************************************************/
-/* SPDIF_RCVR_CTRL :: ABSTRACT_INTERRUPT_HANDLING :: MORE_INFORMATION [31:00] */
-#define BCHP_SPDIF_RCVR_CTRL_ABSTRACT_INTERRUPT_HANDLING_MORE_INFORMATION_MASK 0xffffffff
-#define BCHP_SPDIF_RCVR_CTRL_ABSTRACT_INTERRUPT_HANDLING_MORE_INFORMATION_SHIFT 0
-
-/***************************************************************************
- *VICE2_REGSET_MISC
- ***************************************************************************/
-/***************************************************************************
- *DCCM - registers interface address offset in DCCM.
- ***************************************************************************/
-/* VICE2_REGSET_MISC :: DCCM :: INTERFACE [31:16] */
-#define BCHP_VICE2_REGSET_MISC_DCCM_INTERFACE_MASK 0xffff0000
-#define BCHP_VICE2_REGSET_MISC_DCCM_INTERFACE_SHIFT 16
-#define BCHP_VICE2_REGSET_MISC_DCCM_INTERFACE_HOST2VICE_OFFSET 0
-#define BCHP_VICE2_REGSET_MISC_DCCM_INTERFACE_VICE2HOST_OFFSET 4
-#define BCHP_VICE2_REGSET_MISC_DCCM_INTERFACE_BVN2VICE_OFFSET 8
-#define BCHP_VICE2_REGSET_MISC_DCCM_INTERFACE_MBOX_0_START 16
-#define BCHP_VICE2_REGSET_MISC_DCCM_INTERFACE_MBOX_1_START 40
-
-/* VICE2_REGSET_MISC :: DCCM :: REVISION [15:00] */
-#define BCHP_VICE2_REGSET_MISC_DCCM_REVISION_MASK 0x0000ffff
-#define BCHP_VICE2_REGSET_MISC_DCCM_REVISION_SHIFT 0
-#define BCHP_VICE2_REGSET_MISC_DCCM_REVISION_ID 1
-
-/***************************************************************************
- *MBOX - MBOX registers interface address offset.
- ***************************************************************************/
-/* VICE2_REGSET_MISC :: MBOX :: INTERFACE [31:16] */
-#define BCHP_VICE2_REGSET_MISC_MBOX_INTERFACE_MASK 0xffff0000
-#define BCHP_VICE2_REGSET_MISC_MBOX_INTERFACE_SHIFT 16
-#define BCHP_VICE2_REGSET_MISC_MBOX_INTERFACE_DWORD_00_BVB_PIC_SIZE_OFFSET 0
-#define BCHP_VICE2_REGSET_MISC_MBOX_INTERFACE_DWORD_01_SAMPLE_ASPECT_RATIO_OFFSET 4
-#define BCHP_VICE2_REGSET_MISC_MBOX_INTERFACE_DWORD_02_PIC_INFO_OFFSET 8
-#define BCHP_VICE2_REGSET_MISC_MBOX_INTERFACE_DWORD_03_ORIGINAL_PTS_OFFSET 12
-#define BCHP_VICE2_REGSET_MISC_MBOX_INTERFACE_DWORD_04_STG_PICTURE_ID_OFFSET 16
-#define BCHP_VICE2_REGSET_MISC_MBOX_INTERFACE_DWORD_05_BARDATA_INFO_OFFSET 20
-#define BCHP_VICE2_REGSET_MISC_MBOX_INTERFACE_SIZE 6
-
-/* VICE2_REGSET_MISC :: MBOX :: MAJORREVISION [15:08] */
-#define BCHP_VICE2_REGSET_MISC_MBOX_MAJORREVISION_MASK 0x0000ff00
-#define BCHP_VICE2_REGSET_MISC_MBOX_MAJORREVISION_SHIFT 8
-#define BCHP_VICE2_REGSET_MISC_MBOX_MAJORREVISION_ID 1
-
-/* VICE2_REGSET_MISC :: MBOX :: MINORREVISION [07:00] */
-#define BCHP_VICE2_REGSET_MISC_MBOX_MINORREVISION_MASK 0x000000ff
-#define BCHP_VICE2_REGSET_MISC_MBOX_MINORREVISION_SHIFT 0
-#define BCHP_VICE2_REGSET_MISC_MBOX_MINORREVISION_ID 0
-
-/***************************************************************************
- *DWORD_00_BVB_PIC_SIZE - BVB Picture Size
- ***************************************************************************/
-/* VICE2_REGSET_MISC :: DWORD_00_BVB_PIC_SIZE :: H_SIZE [31:16] */
-#define BCHP_VICE2_REGSET_MISC_DWORD_00_BVB_PIC_SIZE_H_SIZE_MASK 0xffff0000
-#define BCHP_VICE2_REGSET_MISC_DWORD_00_BVB_PIC_SIZE_H_SIZE_SHIFT 16
-
-/* VICE2_REGSET_MISC :: DWORD_00_BVB_PIC_SIZE :: V_SIZE [15:00] */
-#define BCHP_VICE2_REGSET_MISC_DWORD_00_BVB_PIC_SIZE_V_SIZE_MASK 0x0000ffff
-#define BCHP_VICE2_REGSET_MISC_DWORD_00_BVB_PIC_SIZE_V_SIZE_SHIFT 0
-
-/***************************************************************************
- *DWORD_01_SAMPLE_ASPECT_RATIO - Sample Aspect Ratio
- ***************************************************************************/
-/* VICE2_REGSET_MISC :: DWORD_01_SAMPLE_ASPECT_RATIO :: H_SIZE [31:16] */
-#define BCHP_VICE2_REGSET_MISC_DWORD_01_SAMPLE_ASPECT_RATIO_H_SIZE_MASK 0xffff0000
-#define BCHP_VICE2_REGSET_MISC_DWORD_01_SAMPLE_ASPECT_RATIO_H_SIZE_SHIFT 16
-
-/* VICE2_REGSET_MISC :: DWORD_01_SAMPLE_ASPECT_RATIO :: V_SIZE [15:00] */
-#define BCHP_VICE2_REGSET_MISC_DWORD_01_SAMPLE_ASPECT_RATIO_V_SIZE_MASK 0x0000ffff
-#define BCHP_VICE2_REGSET_MISC_DWORD_01_SAMPLE_ASPECT_RATIO_V_SIZE_SHIFT 0
-
-/***************************************************************************
- *DWORD_02_PIC_INFO - Picture Information
- ***************************************************************************/
-/* VICE2_REGSET_MISC :: DWORD_02_PIC_INFO :: FRAME_RATE [31:16] */
-#define BCHP_VICE2_REGSET_MISC_DWORD_02_PIC_INFO_FRAME_RATE_MASK 0xffff0000
-#define BCHP_VICE2_REGSET_MISC_DWORD_02_PIC_INFO_FRAME_RATE_SHIFT 16
-
-/* VICE2_REGSET_MISC :: DWORD_02_PIC_INFO :: SRC_PIC_TYPE [15:12] */
-#define BCHP_VICE2_REGSET_MISC_DWORD_02_PIC_INFO_SRC_PIC_TYPE_MASK 0x0000f000
-#define BCHP_VICE2_REGSET_MISC_DWORD_02_PIC_INFO_SRC_PIC_TYPE_SHIFT 12
-#define BCHP_VICE2_REGSET_MISC_DWORD_02_PIC_INFO_SRC_PIC_TYPE_UNKNOWN 0
-#define BCHP_VICE2_REGSET_MISC_DWORD_02_PIC_INFO_SRC_PIC_TYPE_I 1
-#define BCHP_VICE2_REGSET_MISC_DWORD_02_PIC_INFO_SRC_PIC_TYPE_P 2
-#define BCHP_VICE2_REGSET_MISC_DWORD_02_PIC_INFO_SRC_PIC_TYPE_B 3
-
-/* VICE2_REGSET_MISC :: DWORD_02_PIC_INFO :: POLARITY [11:10] */
-#define BCHP_VICE2_REGSET_MISC_DWORD_02_PIC_INFO_POLARITY_MASK 0x00000c00
-#define BCHP_VICE2_REGSET_MISC_DWORD_02_PIC_INFO_POLARITY_SHIFT 10
-#define BCHP_VICE2_REGSET_MISC_DWORD_02_PIC_INFO_POLARITY_TOP 0
-#define BCHP_VICE2_REGSET_MISC_DWORD_02_PIC_INFO_POLARITY_BOT 1
-#define BCHP_VICE2_REGSET_MISC_DWORD_02_PIC_INFO_POLARITY_FRAME 2
-
-/* VICE2_REGSET_MISC :: DWORD_02_PIC_INFO :: REPEAT [09:09] */
-#define BCHP_VICE2_REGSET_MISC_DWORD_02_PIC_INFO_REPEAT_MASK 0x00000200
-#define BCHP_VICE2_REGSET_MISC_DWORD_02_PIC_INFO_REPEAT_SHIFT 9
-#define BCHP_VICE2_REGSET_MISC_DWORD_02_PIC_INFO_REPEAT_DISABLE 0
-#define BCHP_VICE2_REGSET_MISC_DWORD_02_PIC_INFO_REPEAT_ENABLE 1
-
-/* VICE2_REGSET_MISC :: DWORD_02_PIC_INFO :: IGNORE [08:08] */
-#define BCHP_VICE2_REGSET_MISC_DWORD_02_PIC_INFO_IGNORE_MASK 0x00000100
-#define BCHP_VICE2_REGSET_MISC_DWORD_02_PIC_INFO_IGNORE_SHIFT 8
-#define BCHP_VICE2_REGSET_MISC_DWORD_02_PIC_INFO_IGNORE_DISABLE 0
-#define BCHP_VICE2_REGSET_MISC_DWORD_02_PIC_INFO_IGNORE_ENABLE 1
-
-/* VICE2_REGSET_MISC :: DWORD_02_PIC_INFO :: LAST [07:07] */
-#define BCHP_VICE2_REGSET_MISC_DWORD_02_PIC_INFO_LAST_MASK 0x00000080
-#define BCHP_VICE2_REGSET_MISC_DWORD_02_PIC_INFO_LAST_SHIFT 7
-#define BCHP_VICE2_REGSET_MISC_DWORD_02_PIC_INFO_LAST_FALSE 0
-#define BCHP_VICE2_REGSET_MISC_DWORD_02_PIC_INFO_LAST_TRUE 1
-
-/* VICE2_REGSET_MISC :: DWORD_02_PIC_INFO :: CHANNELCHANGE [06:06] */
-#define BCHP_VICE2_REGSET_MISC_DWORD_02_PIC_INFO_CHANNELCHANGE_MASK 0x00000040
-#define BCHP_VICE2_REGSET_MISC_DWORD_02_PIC_INFO_CHANNELCHANGE_SHIFT 6
-#define BCHP_VICE2_REGSET_MISC_DWORD_02_PIC_INFO_CHANNELCHANGE_FALSE 0
-#define BCHP_VICE2_REGSET_MISC_DWORD_02_PIC_INFO_CHANNELCHANGE_TRUE 1
-
-/* VICE2_REGSET_MISC :: DWORD_02_PIC_INFO :: reserved0 [05:05] */
-#define BCHP_VICE2_REGSET_MISC_DWORD_02_PIC_INFO_reserved0_MASK 0x00000020
-#define BCHP_VICE2_REGSET_MISC_DWORD_02_PIC_INFO_reserved0_SHIFT 5
-
-/* VICE2_REGSET_MISC :: DWORD_02_PIC_INFO :: ACTIVEFORMATDATA [04:04] */
-#define BCHP_VICE2_REGSET_MISC_DWORD_02_PIC_INFO_ACTIVEFORMATDATA_MASK 0x00000010
-#define BCHP_VICE2_REGSET_MISC_DWORD_02_PIC_INFO_ACTIVEFORMATDATA_SHIFT 4
-#define BCHP_VICE2_REGSET_MISC_DWORD_02_PIC_INFO_ACTIVEFORMATDATA_FALSE 0
-#define BCHP_VICE2_REGSET_MISC_DWORD_02_PIC_INFO_ACTIVEFORMATDATA_TRUE 1
-
-/* VICE2_REGSET_MISC :: DWORD_02_PIC_INFO :: ACTIVEFORMATDATAMODE [03:00] */
-#define BCHP_VICE2_REGSET_MISC_DWORD_02_PIC_INFO_ACTIVEFORMATDATAMODE_MASK 0x0000000f
-#define BCHP_VICE2_REGSET_MISC_DWORD_02_PIC_INFO_ACTIVEFORMATDATAMODE_SHIFT 0
-
-/***************************************************************************
- *DWORD_03_ORIGINAL_PTS - Source PTS Value
- ***************************************************************************/
-/* VICE2_REGSET_MISC :: DWORD_03_ORIGINAL_PTS :: VAL [31:00] */
-#define BCHP_VICE2_REGSET_MISC_DWORD_03_ORIGINAL_PTS_VAL_MASK 0xffffffff
-#define BCHP_VICE2_REGSET_MISC_DWORD_03_ORIGINAL_PTS_VAL_SHIFT 0
-
-/***************************************************************************
- *DWORD_04_STG_PICTURE_ID - STG Picture ID
- ***************************************************************************/
-/* VICE2_REGSET_MISC :: DWORD_04_STG_PICTURE_ID :: VAL [31:00] */
-#define BCHP_VICE2_REGSET_MISC_DWORD_04_STG_PICTURE_ID_VAL_MASK 0xffffffff
-#define BCHP_VICE2_REGSET_MISC_DWORD_04_STG_PICTURE_ID_VAL_SHIFT 0
-
-/***************************************************************************
- *DWORD_05_BARDATA_INFO - bar data Information
- ***************************************************************************/
-/* VICE2_REGSET_MISC :: DWORD_05_BARDATA_INFO :: reserved0 [31:30] */
-#define BCHP_VICE2_REGSET_MISC_DWORD_05_BARDATA_INFO_reserved0_MASK 0xc0000000
-#define BCHP_VICE2_REGSET_MISC_DWORD_05_BARDATA_INFO_reserved0_SHIFT 30
-
-/* VICE2_REGSET_MISC :: DWORD_05_BARDATA_INFO :: TOPLEFTBARVALUE [29:16] */
-#define BCHP_VICE2_REGSET_MISC_DWORD_05_BARDATA_INFO_TOPLEFTBARVALUE_MASK 0x3fff0000
-#define BCHP_VICE2_REGSET_MISC_DWORD_05_BARDATA_INFO_TOPLEFTBARVALUE_SHIFT 16
-
-/* VICE2_REGSET_MISC :: DWORD_05_BARDATA_INFO :: BARDATATYPE [15:14] */
-#define BCHP_VICE2_REGSET_MISC_DWORD_05_BARDATA_INFO_BARDATATYPE_MASK 0x0000c000
-#define BCHP_VICE2_REGSET_MISC_DWORD_05_BARDATA_INFO_BARDATATYPE_SHIFT 14
-#define BCHP_VICE2_REGSET_MISC_DWORD_05_BARDATA_INFO_BARDATATYPE_invalidBarData 0
-#define BCHP_VICE2_REGSET_MISC_DWORD_05_BARDATA_INFO_BARDATATYPE_TopBottom 1
-#define BCHP_VICE2_REGSET_MISC_DWORD_05_BARDATA_INFO_BARDATATYPE_LeftRight 2
-#define BCHP_VICE2_REGSET_MISC_DWORD_05_BARDATA_INFO_BARDATATYPE_reserved 3
-
-/* VICE2_REGSET_MISC :: DWORD_05_BARDATA_INFO :: BOTRIGHTBARVALUE [13:00] */
-#define BCHP_VICE2_REGSET_MISC_DWORD_05_BARDATA_INFO_BOTRIGHTBARVALUE_MASK 0x00003fff
-#define BCHP_VICE2_REGSET_MISC_DWORD_05_BARDATA_INFO_BOTRIGHTBARVALUE_SHIFT 0
-
-/***************************************************************************
- *XPT_RAVE
- ***************************************************************************/
-/***************************************************************************
- *NOTEA_CONTEXT_SETUP_EXAMPLES - Context Setup Examples
- ***************************************************************************/
-/* XPT_RAVE :: NOTEA_CONTEXT_SETUP_EXAMPLES :: CONTEXT_EXAMPLES [31:00] */
-#define BCHP_XPT_RAVE_NOTEA_CONTEXT_SETUP_EXAMPLES_CONTEXT_EXAMPLES_MASK 0xffffffff
-#define BCHP_XPT_RAVE_NOTEA_CONTEXT_SETUP_EXAMPLES_CONTEXT_EXAMPLES_SHIFT 0
-
-/***************************************************************************
- *NOTEB_STREAM_TYPE_SETUP - Stream Type Setup
- ***************************************************************************/
-/* XPT_RAVE :: NOTEB_STREAM_TYPE_SETUP :: STREAM_TYPE_SETUP [31:00] */
-#define BCHP_XPT_RAVE_NOTEB_STREAM_TYPE_SETUP_STREAM_TYPE_SETUP_MASK 0xffffffff
-#define BCHP_XPT_RAVE_NOTEB_STREAM_TYPE_SETUP_STREAM_TYPE_SETUP_SHIFT 0
-
-/***************************************************************************
- *NOTEC_PES_LAYER_SELECTION - PES Layer Selection
- ***************************************************************************/
-/* XPT_RAVE :: NOTEC_PES_LAYER_SELECTION :: PES_LAYER_SELECTION [31:00] */
-#define BCHP_XPT_RAVE_NOTEC_PES_LAYER_SELECTION_PES_LAYER_SELECTION_MASK 0xffffffff
-#define BCHP_XPT_RAVE_NOTEC_PES_LAYER_SELECTION_PES_LAYER_SELECTION_SHIFT 0
-
-/***************************************************************************
- *NOTED_ES_FORMAT_SELECTION_GENERAL - ES Format Selection - general
- ***************************************************************************/
-/* XPT_RAVE :: NOTED_ES_FORMAT_SELECTION_GENERAL :: GENERAL_ES_FORMAT_SELECTION [31:00] */
-#define BCHP_XPT_RAVE_NOTED_ES_FORMAT_SELECTION_GENERAL_GENERAL_ES_FORMAT_SELECTION_MASK 0xffffffff
-#define BCHP_XPT_RAVE_NOTED_ES_FORMAT_SELECTION_GENERAL_GENERAL_ES_FORMAT_SELECTION_SHIFT 0
-
-/***************************************************************************
- *NOTEE_MPEG2_VIDEO_ES_SETUP - ES Setup - MPEG2 Video
- ***************************************************************************/
-/* XPT_RAVE :: NOTEE_MPEG2_VIDEO_ES_SETUP :: MPEG2_VIDEO_ES_FORMAT [31:00] */
-#define BCHP_XPT_RAVE_NOTEE_MPEG2_VIDEO_ES_SETUP_MPEG2_VIDEO_ES_FORMAT_MASK 0xffffffff
-#define BCHP_XPT_RAVE_NOTEE_MPEG2_VIDEO_ES_SETUP_MPEG2_VIDEO_ES_FORMAT_SHIFT 0
-
-/***************************************************************************
- *NOTEF_AVC_VC1_VIDEO_ES_SETUP - ES Setup - AVC and VC1 Video
- ***************************************************************************/
-/* XPT_RAVE :: NOTEF_AVC_VC1_VIDEO_ES_SETUP :: AVC_VC1_VIDEO_ES_FORMAT [31:00] */
-#define BCHP_XPT_RAVE_NOTEF_AVC_VC1_VIDEO_ES_SETUP_AVC_VC1_VIDEO_ES_FORMAT_MASK 0xffffffff
-#define BCHP_XPT_RAVE_NOTEF_AVC_VC1_VIDEO_ES_SETUP_AVC_VC1_VIDEO_ES_FORMAT_SHIFT 0
-
-/***************************************************************************
- *NOTEG_MPEG_AUDIO_ES_SETUP - ES Setup - MPEG Audio
- ***************************************************************************/
-/* XPT_RAVE :: NOTEG_MPEG_AUDIO_ES_SETUP :: AUDIO_MPEG_ES_FORMAT [31:00] */
-#define BCHP_XPT_RAVE_NOTEG_MPEG_AUDIO_ES_SETUP_AUDIO_MPEG_ES_FORMAT_MASK 0xffffffff
-#define BCHP_XPT_RAVE_NOTEG_MPEG_AUDIO_ES_SETUP_AUDIO_MPEG_ES_FORMAT_SHIFT 0
-
-/***************************************************************************
- *NOTEH_AAC_AUDIO_ES_SETUP - ES Setup - AAC Audio
- ***************************************************************************/
-/* XPT_RAVE :: NOTEH_AAC_AUDIO_ES_SETUP :: AUDIO_AAC_ES_FORMAT [31:00] */
-#define BCHP_XPT_RAVE_NOTEH_AAC_AUDIO_ES_SETUP_AUDIO_AAC_ES_FORMAT_MASK 0xffffffff
-#define BCHP_XPT_RAVE_NOTEH_AAC_AUDIO_ES_SETUP_AUDIO_AAC_ES_FORMAT_SHIFT 0
-
-/***************************************************************************
- *NOTEH_AC3_AUDIO_ES_SETUP - ES Setup - AC3 Audio
- ***************************************************************************/
-/* XPT_RAVE :: NOTEH_AC3_AUDIO_ES_SETUP :: AUDIO_AC3_ES_FORMAT [31:00] */
-#define BCHP_XPT_RAVE_NOTEH_AC3_AUDIO_ES_SETUP_AUDIO_AC3_ES_FORMAT_MASK 0xffffffff
-#define BCHP_XPT_RAVE_NOTEH_AC3_AUDIO_ES_SETUP_AUDIO_AC3_ES_FORMAT_SHIFT 0
-
-/***************************************************************************
- *NOTEJ_ENHANCED_AC3_AUDIO_ES_SETUP - ES Setup - AC3 Audio
- ***************************************************************************/
-/* XPT_RAVE :: NOTEJ_ENHANCED_AC3_AUDIO_ES_SETUP :: AUDIO_ENHANCED_AC3_ES_FORMAT [31:00] */
-#define BCHP_XPT_RAVE_NOTEJ_ENHANCED_AC3_AUDIO_ES_SETUP_AUDIO_ENHANCED_AC3_ES_FORMAT_MASK 0xffffffff
-#define BCHP_XPT_RAVE_NOTEJ_ENHANCED_AC3_AUDIO_ES_SETUP_AUDIO_ENHANCED_AC3_ES_FORMAT_SHIFT 0
-
-/***************************************************************************
- *NOTEK_AAC_HE_AUDIO_ES_SETUP - ES Setup - AAC HE Audio
- ***************************************************************************/
-/* XPT_RAVE :: NOTEK_AAC_HE_AUDIO_ES_SETUP :: AUDIO_AAC_HE_ES_FORMAT [31:00] */
-#define BCHP_XPT_RAVE_NOTEK_AAC_HE_AUDIO_ES_SETUP_AUDIO_AAC_HE_ES_FORMAT_MASK 0xffffffff
-#define BCHP_XPT_RAVE_NOTEK_AAC_HE_AUDIO_ES_SETUP_AUDIO_AAC_HE_ES_FORMAT_SHIFT 0
-
-#endif /* #ifndef BCHP_COMMON_H__ */
-
-/* End of File */
diff --git a/include/linux/brcmstb/7439a0/bchp_ddr34_phy_byte_lane_0_0.h b/include/linux/brcmstb/7439a0/bchp_ddr34_phy_byte_lane_0_0.h
deleted file mode 100644
index 5199ecc..0000000
--- a/include/linux/brcmstb/7439a0/bchp_ddr34_phy_byte_lane_0_0.h
+++ /dev/null
@@ -1,2099 +0,0 @@
-/***************************************************************************
- * Copyright (c) 1999-2013, Broadcom Corporation
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
- *
- * Module Description:
- * DO NOT EDIT THIS FILE DIRECTLY
- *
- * This module was generated magically with RDB from a source description
- * file. You must edit the source file for changes to be made to this file.
- *
- *
- * Date: Generated on Tue Apr 16 03:26:50 2013
- * MD5 Checksum d41d8cd98f00b204e9800998ecf8427e
- *
- * Compiled with: RDB Utility combo_header.pl
- * RDB Parser 3.0
- * unknown unknown
- * Perl Interpreter 5.008008
- * Operating System linux
- *
- * Revision History:
- *
- * $brcm_Log: $
- *
- ***************************************************************************/
-
-#ifndef BCHP_DDR34_PHY_BYTE_LANE_0_0_H__
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_H__
-
-/***************************************************************************
- *DDR34_PHY_BYTE_LANE_0_0 - 0 DDR34 DDR34 Byte Lane #0 control registers
- ***************************************************************************/
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQS_P 0x00906400 /* Write channel DQS-P VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQS_N 0x00906404 /* Write channel DQS-N VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ0 0x00906408 /* Write channel DQ0 VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ1 0x0090640c /* Write channel DQ1 VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ2 0x00906410 /* Write channel DQ2 VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ3 0x00906414 /* Write channel DQ3 VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ4 0x00906418 /* Write channel DQ4 VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ5 0x0090641c /* Write channel DQ5 VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ6 0x00906420 /* Write channel DQ6 VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ7 0x00906424 /* Write channel DQ7 VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DM 0x00906428 /* Write channel DM VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_EDC 0x0090642c /* Write channel EDC VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQSP 0x00906430 /* Read channel DQSP VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQSN 0x00906434 /* Read channel DQSP VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ0P 0x00906438 /* Read channel DQ0-P VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ0N 0x0090643c /* Read channel DQ0-N VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ1P 0x00906440 /* Read channel DQ1-P VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ1N 0x00906444 /* Read channel DQ1-N VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ2P 0x00906448 /* Read channel DQ2-P VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ2N 0x0090644c /* Read channel DQ2-N VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ3P 0x00906450 /* Read channel DQ3-P VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ3N 0x00906454 /* Read channel DQ3-N VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ4P 0x00906458 /* Read channel DQ4-P VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ4N 0x0090645c /* Read channel DQ4-N VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ5P 0x00906460 /* Read channel DQ5-P VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ5N 0x00906464 /* Read channel DQ5-N VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ6P 0x00906468 /* Read channel DQ6-P VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ6N 0x0090646c /* Read channel DQ6-N VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ7P 0x00906470 /* Read channel DQ7-P VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ7N 0x00906474 /* Read channel DQ7-N VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DMP 0x00906478 /* Read channel DM-P VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DMN 0x0090647c /* Read channel DM-N VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_EDCP 0x00906480 /* Read channel EDC-P VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_EDCN 0x00906484 /* Read channel EDC-N VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_EN_CS0 0x00906488 /* Read channel CS_N[0] read enable VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_EN_CS1 0x0090648c /* Read channel CS_N[1] read enable VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CLK_CONTROL 0x00906490 /* DDR interface signal Write Leveling CLK VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_LDE_CONTROL 0x00906494 /* DDR interface signal Write Leveling Capture Enable VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_RD_EN_DLY_CYC 0x009064a0 /* Read enable bit-clock cycle delay control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_WR_CHAN_DLY_CYC 0x009064a4 /* Write leveling bit-clock cycle delay control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_READ_CONTROL 0x009064b0 /* Read channel datapath control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_READ_FIFO_ADDR 0x009064b4 /* Read fifo addresss pointer register */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_READ_FIFO_DATA 0x009064b8 /* Read fifo data register */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_READ_FIFO_DM_DBI 0x009064bc /* Read fifo dm/dbi register */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_READ_FIFO_STATUS 0x009064c0 /* Read fifo status register */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_READ_FIFO_CLEAR 0x009064c4 /* Read fifo status clear register */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_IDLE_PAD_CONTROL 0x009064c8 /* Idle mode SSTL pad control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_DRIVE_PAD_CTL 0x009064cc /* SSTL pad drive characteristics control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_RD_EN_DRIVE_PAD_CTL 0x009064d0 /* SSTL read enable pad drive characteristics control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_STATIC_PAD_CTL 0x009064d4 /* pad rx and tx characteristics control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_WR_PREAMBLE_MODE 0x009064d8 /* Write cycle preamble control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_ODT_CONTROL 0x009064e0 /* Read channel ODT control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_DPD_CONTROL 0x009064f0 /* GDDR5M EDC digital phase detector control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_DPD_STATUS 0x009064f4 /* GDDR5M EDC digital phase detector status register */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_DPD_OUT_CONTROL 0x009064f8 /* GDDR5M EDC digital phase detector output signal control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_DPD_OUT_STATUS 0x009064fc /* GDDR5M EDC digital phase detector output signal status register */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_DPD_OUT_STATUS_CLEAR 0x00906500 /* GDDR5M EDC digital phase detector output signal status clear register */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_CRC_CONTROL 0x00906504 /* GDDR5M EDC signal path CRC control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_CRC_STATUS 0x00906508 /* GDDR5M EDC signal path CRC status register */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_CRC_COUNT 0x0090650c /* GDDR5M EDC signal path CRC counter register */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_CRC_STATUS_CLEAR 0x00906510 /* GDDR5M EDC signal path CRC counter register */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_BL_SPARE_REG 0x00906514 /* Byte-Lane Spare register */
-
-/***************************************************************************
- *VDL_CONTROL_WR_DQS_P - Write channel DQS-P VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_WR_DQS_P :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQS_P_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQS_P_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQS_P_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_WR_DQS_P :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQS_P_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQS_P_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_WR_DQS_P :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQS_P_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQS_P_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQS_P_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_WR_DQS_P :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQS_P_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQS_P_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_WR_DQS_P :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQS_P_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQS_P_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQS_P_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_WR_DQS_P :: reserved2 [11:09] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQS_P_reserved2_MASK 0x00000e00
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQS_P_reserved2_SHIFT 9
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_WR_DQS_P :: VDL_STEP [08:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQS_P_VDL_STEP_MASK 0x000001ff
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQS_P_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQS_P_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_WR_DQS_N - Write channel DQS-N VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_WR_DQS_N :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQS_N_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQS_N_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQS_N_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_WR_DQS_N :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQS_N_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQS_N_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_WR_DQS_N :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQS_N_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQS_N_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQS_N_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_WR_DQS_N :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQS_N_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQS_N_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_WR_DQS_N :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQS_N_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQS_N_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQS_N_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_WR_DQS_N :: reserved2 [11:09] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQS_N_reserved2_MASK 0x00000e00
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQS_N_reserved2_SHIFT 9
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_WR_DQS_N :: VDL_STEP [08:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQS_N_VDL_STEP_MASK 0x000001ff
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQS_N_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQS_N_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_WR_DQ0 - Write channel DQ0 VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_WR_DQ0 :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ0_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ0_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ0_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_WR_DQ0 :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ0_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ0_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_WR_DQ0 :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ0_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ0_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ0_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_WR_DQ0 :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ0_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ0_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_WR_DQ0 :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ0_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ0_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ0_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_WR_DQ0 :: reserved2 [11:09] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ0_reserved2_MASK 0x00000e00
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ0_reserved2_SHIFT 9
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_WR_DQ0 :: VDL_STEP [08:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ0_VDL_STEP_MASK 0x000001ff
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ0_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ0_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_WR_DQ1 - Write channel DQ1 VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_WR_DQ1 :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ1_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ1_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ1_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_WR_DQ1 :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ1_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ1_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_WR_DQ1 :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ1_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ1_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ1_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_WR_DQ1 :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ1_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ1_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_WR_DQ1 :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ1_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ1_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ1_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_WR_DQ1 :: reserved2 [11:09] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ1_reserved2_MASK 0x00000e00
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ1_reserved2_SHIFT 9
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_WR_DQ1 :: VDL_STEP [08:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ1_VDL_STEP_MASK 0x000001ff
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ1_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ1_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_WR_DQ2 - Write channel DQ2 VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_WR_DQ2 :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ2_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ2_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ2_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_WR_DQ2 :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ2_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ2_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_WR_DQ2 :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ2_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ2_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ2_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_WR_DQ2 :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ2_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ2_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_WR_DQ2 :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ2_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ2_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ2_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_WR_DQ2 :: reserved2 [11:09] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ2_reserved2_MASK 0x00000e00
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ2_reserved2_SHIFT 9
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_WR_DQ2 :: VDL_STEP [08:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ2_VDL_STEP_MASK 0x000001ff
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ2_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ2_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_WR_DQ3 - Write channel DQ3 VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_WR_DQ3 :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ3_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ3_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ3_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_WR_DQ3 :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ3_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ3_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_WR_DQ3 :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ3_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ3_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ3_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_WR_DQ3 :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ3_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ3_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_WR_DQ3 :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ3_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ3_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ3_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_WR_DQ3 :: reserved2 [11:09] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ3_reserved2_MASK 0x00000e00
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ3_reserved2_SHIFT 9
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_WR_DQ3 :: VDL_STEP [08:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ3_VDL_STEP_MASK 0x000001ff
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ3_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ3_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_WR_DQ4 - Write channel DQ4 VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_WR_DQ4 :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ4_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ4_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ4_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_WR_DQ4 :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ4_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ4_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_WR_DQ4 :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ4_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ4_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ4_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_WR_DQ4 :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ4_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ4_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_WR_DQ4 :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ4_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ4_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ4_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_WR_DQ4 :: reserved2 [11:09] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ4_reserved2_MASK 0x00000e00
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ4_reserved2_SHIFT 9
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_WR_DQ4 :: VDL_STEP [08:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ4_VDL_STEP_MASK 0x000001ff
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ4_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ4_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_WR_DQ5 - Write channel DQ5 VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_WR_DQ5 :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ5_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ5_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ5_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_WR_DQ5 :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ5_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ5_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_WR_DQ5 :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ5_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ5_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ5_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_WR_DQ5 :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ5_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ5_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_WR_DQ5 :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ5_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ5_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ5_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_WR_DQ5 :: reserved2 [11:09] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ5_reserved2_MASK 0x00000e00
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ5_reserved2_SHIFT 9
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_WR_DQ5 :: VDL_STEP [08:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ5_VDL_STEP_MASK 0x000001ff
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ5_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ5_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_WR_DQ6 - Write channel DQ6 VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_WR_DQ6 :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ6_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ6_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ6_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_WR_DQ6 :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ6_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ6_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_WR_DQ6 :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ6_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ6_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ6_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_WR_DQ6 :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ6_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ6_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_WR_DQ6 :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ6_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ6_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ6_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_WR_DQ6 :: reserved2 [11:09] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ6_reserved2_MASK 0x00000e00
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ6_reserved2_SHIFT 9
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_WR_DQ6 :: VDL_STEP [08:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ6_VDL_STEP_MASK 0x000001ff
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ6_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ6_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_WR_DQ7 - Write channel DQ7 VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_WR_DQ7 :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ7_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ7_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ7_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_WR_DQ7 :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ7_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ7_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_WR_DQ7 :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ7_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ7_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ7_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_WR_DQ7 :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ7_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ7_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_WR_DQ7 :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ7_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ7_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ7_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_WR_DQ7 :: reserved2 [11:09] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ7_reserved2_MASK 0x00000e00
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ7_reserved2_SHIFT 9
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_WR_DQ7 :: VDL_STEP [08:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ7_VDL_STEP_MASK 0x000001ff
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ7_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ7_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_WR_DM - Write channel DM VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_WR_DM :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DM_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DM_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DM_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_WR_DM :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DM_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DM_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_WR_DM :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DM_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DM_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DM_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_WR_DM :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DM_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DM_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_WR_DM :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DM_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DM_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DM_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_WR_DM :: reserved2 [11:09] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DM_reserved2_MASK 0x00000e00
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DM_reserved2_SHIFT 9
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_WR_DM :: VDL_STEP [08:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DM_VDL_STEP_MASK 0x000001ff
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DM_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DM_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_WR_EDC - Write channel EDC VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_WR_EDC :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_EDC_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_EDC_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_EDC_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_WR_EDC :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_EDC_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_EDC_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_WR_EDC :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_EDC_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_EDC_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_EDC_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_WR_EDC :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_EDC_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_EDC_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_WR_EDC :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_EDC_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_EDC_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_EDC_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_WR_EDC :: reserved2 [11:09] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_EDC_reserved2_MASK 0x00000e00
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_EDC_reserved2_SHIFT 9
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_WR_EDC :: VDL_STEP [08:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_EDC_VDL_STEP_MASK 0x000001ff
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_EDC_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_EDC_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_RD_DQSP - Read channel DQSP VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQSP :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQSP_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQSP_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQSP_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQSP :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQSP_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQSP_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQSP :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQSP_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQSP_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQSP_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQSP :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQSP_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQSP_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQSP :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQSP_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQSP_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQSP_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQSP :: reserved2 [11:08] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQSP_reserved2_MASK 0x00000f00
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQSP_reserved2_SHIFT 8
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQSP :: VDL_STEP [07:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQSP_VDL_STEP_MASK 0x000000ff
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQSP_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQSP_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_RD_DQSN - Read channel DQSP VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQSN :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQSN_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQSN_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQSN_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQSN :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQSN_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQSN_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQSN :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQSN_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQSN_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQSN_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQSN :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQSN_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQSN_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQSN :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQSN_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQSN_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQSN_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQSN :: reserved2 [11:08] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQSN_reserved2_MASK 0x00000f00
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQSN_reserved2_SHIFT 8
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQSN :: VDL_STEP [07:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQSN_VDL_STEP_MASK 0x000000ff
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQSN_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQSN_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_RD_DQ0P - Read channel DQ0-P VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQ0P :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ0P_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ0P_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ0P_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQ0P :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ0P_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ0P_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQ0P :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ0P_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ0P_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ0P_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQ0P :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ0P_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ0P_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQ0P :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ0P_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ0P_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ0P_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQ0P :: reserved2 [11:08] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ0P_reserved2_MASK 0x00000f00
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ0P_reserved2_SHIFT 8
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQ0P :: VDL_STEP [07:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ0P_VDL_STEP_MASK 0x000000ff
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ0P_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ0P_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_RD_DQ0N - Read channel DQ0-N VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQ0N :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ0N_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ0N_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ0N_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQ0N :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ0N_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ0N_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQ0N :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ0N_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ0N_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ0N_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQ0N :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ0N_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ0N_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQ0N :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ0N_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ0N_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ0N_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQ0N :: reserved2 [11:08] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ0N_reserved2_MASK 0x00000f00
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ0N_reserved2_SHIFT 8
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQ0N :: VDL_STEP [07:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ0N_VDL_STEP_MASK 0x000000ff
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ0N_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ0N_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_RD_DQ1P - Read channel DQ1-P VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQ1P :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ1P_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ1P_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ1P_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQ1P :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ1P_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ1P_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQ1P :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ1P_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ1P_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ1P_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQ1P :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ1P_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ1P_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQ1P :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ1P_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ1P_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ1P_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQ1P :: reserved2 [11:08] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ1P_reserved2_MASK 0x00000f00
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ1P_reserved2_SHIFT 8
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQ1P :: VDL_STEP [07:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ1P_VDL_STEP_MASK 0x000000ff
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ1P_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ1P_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_RD_DQ1N - Read channel DQ1-N VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQ1N :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ1N_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ1N_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ1N_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQ1N :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ1N_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ1N_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQ1N :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ1N_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ1N_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ1N_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQ1N :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ1N_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ1N_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQ1N :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ1N_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ1N_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ1N_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQ1N :: reserved2 [11:08] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ1N_reserved2_MASK 0x00000f00
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ1N_reserved2_SHIFT 8
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQ1N :: VDL_STEP [07:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ1N_VDL_STEP_MASK 0x000000ff
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ1N_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ1N_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_RD_DQ2P - Read channel DQ2-P VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQ2P :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ2P_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ2P_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ2P_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQ2P :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ2P_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ2P_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQ2P :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ2P_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ2P_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ2P_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQ2P :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ2P_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ2P_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQ2P :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ2P_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ2P_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ2P_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQ2P :: reserved2 [11:08] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ2P_reserved2_MASK 0x00000f00
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ2P_reserved2_SHIFT 8
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQ2P :: VDL_STEP [07:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ2P_VDL_STEP_MASK 0x000000ff
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ2P_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ2P_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_RD_DQ2N - Read channel DQ2-N VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQ2N :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ2N_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ2N_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ2N_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQ2N :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ2N_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ2N_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQ2N :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ2N_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ2N_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ2N_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQ2N :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ2N_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ2N_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQ2N :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ2N_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ2N_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ2N_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQ2N :: reserved2 [11:08] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ2N_reserved2_MASK 0x00000f00
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ2N_reserved2_SHIFT 8
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQ2N :: VDL_STEP [07:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ2N_VDL_STEP_MASK 0x000000ff
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ2N_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ2N_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_RD_DQ3P - Read channel DQ3-P VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQ3P :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ3P_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ3P_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ3P_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQ3P :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ3P_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ3P_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQ3P :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ3P_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ3P_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ3P_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQ3P :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ3P_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ3P_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQ3P :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ3P_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ3P_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ3P_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQ3P :: reserved2 [11:08] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ3P_reserved2_MASK 0x00000f00
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ3P_reserved2_SHIFT 8
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQ3P :: VDL_STEP [07:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ3P_VDL_STEP_MASK 0x000000ff
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ3P_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ3P_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_RD_DQ3N - Read channel DQ3-N VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQ3N :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ3N_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ3N_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ3N_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQ3N :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ3N_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ3N_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQ3N :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ3N_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ3N_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ3N_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQ3N :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ3N_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ3N_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQ3N :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ3N_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ3N_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ3N_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQ3N :: reserved2 [11:08] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ3N_reserved2_MASK 0x00000f00
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ3N_reserved2_SHIFT 8
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQ3N :: VDL_STEP [07:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ3N_VDL_STEP_MASK 0x000000ff
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ3N_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ3N_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_RD_DQ4P - Read channel DQ4-P VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQ4P :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ4P_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ4P_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ4P_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQ4P :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ4P_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ4P_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQ4P :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ4P_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ4P_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ4P_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQ4P :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ4P_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ4P_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQ4P :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ4P_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ4P_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ4P_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQ4P :: reserved2 [11:08] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ4P_reserved2_MASK 0x00000f00
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ4P_reserved2_SHIFT 8
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQ4P :: VDL_STEP [07:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ4P_VDL_STEP_MASK 0x000000ff
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ4P_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ4P_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_RD_DQ4N - Read channel DQ4-N VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQ4N :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ4N_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ4N_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ4N_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQ4N :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ4N_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ4N_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQ4N :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ4N_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ4N_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ4N_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQ4N :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ4N_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ4N_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQ4N :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ4N_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ4N_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ4N_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQ4N :: reserved2 [11:08] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ4N_reserved2_MASK 0x00000f00
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ4N_reserved2_SHIFT 8
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQ4N :: VDL_STEP [07:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ4N_VDL_STEP_MASK 0x000000ff
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ4N_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ4N_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_RD_DQ5P - Read channel DQ5-P VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQ5P :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ5P_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ5P_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ5P_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQ5P :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ5P_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ5P_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQ5P :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ5P_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ5P_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ5P_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQ5P :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ5P_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ5P_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQ5P :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ5P_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ5P_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ5P_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQ5P :: reserved2 [11:08] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ5P_reserved2_MASK 0x00000f00
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ5P_reserved2_SHIFT 8
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQ5P :: VDL_STEP [07:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ5P_VDL_STEP_MASK 0x000000ff
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ5P_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ5P_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_RD_DQ5N - Read channel DQ5-N VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQ5N :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ5N_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ5N_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ5N_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQ5N :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ5N_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ5N_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQ5N :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ5N_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ5N_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ5N_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQ5N :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ5N_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ5N_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQ5N :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ5N_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ5N_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ5N_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQ5N :: reserved2 [11:08] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ5N_reserved2_MASK 0x00000f00
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ5N_reserved2_SHIFT 8
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQ5N :: VDL_STEP [07:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ5N_VDL_STEP_MASK 0x000000ff
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ5N_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ5N_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_RD_DQ6P - Read channel DQ6-P VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQ6P :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ6P_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ6P_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ6P_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQ6P :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ6P_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ6P_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQ6P :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ6P_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ6P_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ6P_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQ6P :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ6P_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ6P_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQ6P :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ6P_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ6P_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ6P_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQ6P :: reserved2 [11:08] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ6P_reserved2_MASK 0x00000f00
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ6P_reserved2_SHIFT 8
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQ6P :: VDL_STEP [07:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ6P_VDL_STEP_MASK 0x000000ff
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ6P_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ6P_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_RD_DQ6N - Read channel DQ6-N VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQ6N :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ6N_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ6N_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ6N_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQ6N :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ6N_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ6N_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQ6N :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ6N_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ6N_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ6N_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQ6N :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ6N_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ6N_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQ6N :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ6N_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ6N_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ6N_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQ6N :: reserved2 [11:08] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ6N_reserved2_MASK 0x00000f00
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ6N_reserved2_SHIFT 8
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQ6N :: VDL_STEP [07:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ6N_VDL_STEP_MASK 0x000000ff
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ6N_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ6N_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_RD_DQ7P - Read channel DQ7-P VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQ7P :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ7P_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ7P_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ7P_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQ7P :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ7P_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ7P_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQ7P :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ7P_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ7P_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ7P_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQ7P :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ7P_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ7P_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQ7P :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ7P_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ7P_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ7P_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQ7P :: reserved2 [11:08] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ7P_reserved2_MASK 0x00000f00
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ7P_reserved2_SHIFT 8
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQ7P :: VDL_STEP [07:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ7P_VDL_STEP_MASK 0x000000ff
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ7P_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ7P_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_RD_DQ7N - Read channel DQ7-N VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQ7N :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ7N_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ7N_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ7N_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQ7N :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ7N_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ7N_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQ7N :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ7N_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ7N_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ7N_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQ7N :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ7N_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ7N_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQ7N :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ7N_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ7N_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ7N_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQ7N :: reserved2 [11:08] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ7N_reserved2_MASK 0x00000f00
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ7N_reserved2_SHIFT 8
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQ7N :: VDL_STEP [07:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ7N_VDL_STEP_MASK 0x000000ff
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ7N_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ7N_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_RD_DMP - Read channel DM-P VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DMP :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DMP_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DMP_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DMP_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DMP :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DMP_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DMP_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DMP :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DMP_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DMP_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DMP_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DMP :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DMP_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DMP_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DMP :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DMP_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DMP_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DMP_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DMP :: reserved2 [11:08] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DMP_reserved2_MASK 0x00000f00
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DMP_reserved2_SHIFT 8
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DMP :: VDL_STEP [07:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DMP_VDL_STEP_MASK 0x000000ff
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DMP_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DMP_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_RD_DMN - Read channel DM-N VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DMN :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DMN_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DMN_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DMN_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DMN :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DMN_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DMN_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DMN :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DMN_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DMN_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DMN_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DMN :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DMN_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DMN_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DMN :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DMN_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DMN_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DMN_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DMN :: reserved2 [11:08] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DMN_reserved2_MASK 0x00000f00
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DMN_reserved2_SHIFT 8
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DMN :: VDL_STEP [07:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DMN_VDL_STEP_MASK 0x000000ff
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DMN_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DMN_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_RD_EDCP - Read channel EDC-P VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_EDCP :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_EDCP_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_EDCP_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_EDCP_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_EDCP :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_EDCP_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_EDCP_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_EDCP :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_EDCP_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_EDCP_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_EDCP_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_EDCP :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_EDCP_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_EDCP_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_EDCP :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_EDCP_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_EDCP_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_EDCP_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_EDCP :: reserved2 [11:08] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_EDCP_reserved2_MASK 0x00000f00
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_EDCP_reserved2_SHIFT 8
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_EDCP :: VDL_STEP [07:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_EDCP_VDL_STEP_MASK 0x000000ff
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_EDCP_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_EDCP_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_RD_EDCN - Read channel EDC-N VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_EDCN :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_EDCN_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_EDCN_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_EDCN_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_EDCN :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_EDCN_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_EDCN_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_EDCN :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_EDCN_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_EDCN_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_EDCN_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_EDCN :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_EDCN_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_EDCN_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_EDCN :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_EDCN_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_EDCN_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_EDCN_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_EDCN :: reserved2 [11:08] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_EDCN_reserved2_MASK 0x00000f00
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_EDCN_reserved2_SHIFT 8
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_EDCN :: VDL_STEP [07:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_EDCN_VDL_STEP_MASK 0x000000ff
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_EDCN_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_EDCN_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_RD_EN_CS0 - Read channel CS_N[0] read enable VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_EN_CS0 :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_EN_CS0_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_EN_CS0_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_EN_CS0_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_EN_CS0 :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_EN_CS0_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_EN_CS0_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_EN_CS0 :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_EN_CS0_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_EN_CS0_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_EN_CS0_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_EN_CS0 :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_EN_CS0_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_EN_CS0_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_EN_CS0 :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_EN_CS0_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_EN_CS0_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_EN_CS0_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_EN_CS0 :: reserved2 [11:08] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_EN_CS0_reserved2_MASK 0x00000f00
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_EN_CS0_reserved2_SHIFT 8
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_EN_CS0 :: VDL_STEP [07:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_EN_CS0_VDL_STEP_MASK 0x000000ff
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_EN_CS0_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_EN_CS0_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_RD_EN_CS1 - Read channel CS_N[1] read enable VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_EN_CS1 :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_EN_CS1_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_EN_CS1_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_EN_CS1_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_EN_CS1 :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_EN_CS1_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_EN_CS1_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_EN_CS1 :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_EN_CS1_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_EN_CS1_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_EN_CS1_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_EN_CS1 :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_EN_CS1_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_EN_CS1_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_EN_CS1 :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_EN_CS1_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_EN_CS1_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_EN_CS1_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_EN_CS1 :: reserved2 [11:08] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_EN_CS1_reserved2_MASK 0x00000f00
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_EN_CS1_reserved2_SHIFT 8
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_EN_CS1 :: VDL_STEP [07:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_EN_CS1_VDL_STEP_MASK 0x000000ff
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_EN_CS1_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_EN_CS1_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CLK_CONTROL - DDR interface signal Write Leveling CLK VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CLK_CONTROL :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CLK_CONTROL_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CLK_CONTROL_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CLK_CONTROL_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CLK_CONTROL :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CLK_CONTROL_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CLK_CONTROL_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CLK_CONTROL :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CLK_CONTROL_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CLK_CONTROL_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CLK_CONTROL_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CLK_CONTROL :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CLK_CONTROL_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CLK_CONTROL_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CLK_CONTROL :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CLK_CONTROL_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CLK_CONTROL_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CLK_CONTROL_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CLK_CONTROL :: reserved2 [11:09] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CLK_CONTROL_reserved2_MASK 0x00000e00
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CLK_CONTROL_reserved2_SHIFT 9
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CLK_CONTROL :: VDL_STEP [08:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CLK_CONTROL_VDL_STEP_MASK 0x000001ff
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CLK_CONTROL_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CLK_CONTROL_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_LDE_CONTROL - DDR interface signal Write Leveling Capture Enable VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_LDE_CONTROL :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_LDE_CONTROL_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_LDE_CONTROL_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_LDE_CONTROL_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_LDE_CONTROL :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_LDE_CONTROL_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_LDE_CONTROL_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_LDE_CONTROL :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_LDE_CONTROL_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_LDE_CONTROL_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_LDE_CONTROL_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_LDE_CONTROL :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_LDE_CONTROL_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_LDE_CONTROL_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_LDE_CONTROL :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_LDE_CONTROL_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_LDE_CONTROL_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_LDE_CONTROL_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_LDE_CONTROL :: reserved2 [11:09] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_LDE_CONTROL_reserved2_MASK 0x00000e00
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_LDE_CONTROL_reserved2_SHIFT 9
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_LDE_CONTROL :: VDL_STEP [08:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_LDE_CONTROL_VDL_STEP_MASK 0x000001ff
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_LDE_CONTROL_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_LDE_CONTROL_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *RD_EN_DLY_CYC - Read enable bit-clock cycle delay control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_0_0 :: RD_EN_DLY_CYC :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_RD_EN_DLY_CYC_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_RD_EN_DLY_CYC_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_RD_EN_DLY_CYC_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: RD_EN_DLY_CYC :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_RD_EN_DLY_CYC_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_RD_EN_DLY_CYC_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: RD_EN_DLY_CYC :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_RD_EN_DLY_CYC_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_RD_EN_DLY_CYC_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_RD_EN_DLY_CYC_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: RD_EN_DLY_CYC :: reserved1 [15:08] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_RD_EN_DLY_CYC_reserved1_MASK 0x0000ff00
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_RD_EN_DLY_CYC_reserved1_SHIFT 8
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: RD_EN_DLY_CYC :: CS1_CYCLES [07:04] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_RD_EN_DLY_CYC_CS1_CYCLES_MASK 0x000000f0
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_RD_EN_DLY_CYC_CS1_CYCLES_SHIFT 4
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_RD_EN_DLY_CYC_CS1_CYCLES_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: RD_EN_DLY_CYC :: CS0_CYCLES [03:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_RD_EN_DLY_CYC_CS0_CYCLES_MASK 0x0000000f
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_RD_EN_DLY_CYC_CS0_CYCLES_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_RD_EN_DLY_CYC_CS0_CYCLES_DEFAULT 0x00000000
-
-/***************************************************************************
- *WR_CHAN_DLY_CYC - Write leveling bit-clock cycle delay control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_0_0 :: WR_CHAN_DLY_CYC :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_WR_CHAN_DLY_CYC_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_WR_CHAN_DLY_CYC_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_WR_CHAN_DLY_CYC_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: WR_CHAN_DLY_CYC :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_WR_CHAN_DLY_CYC_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_WR_CHAN_DLY_CYC_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: WR_CHAN_DLY_CYC :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_WR_CHAN_DLY_CYC_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_WR_CHAN_DLY_CYC_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_WR_CHAN_DLY_CYC_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: WR_CHAN_DLY_CYC :: reserved1 [15:03] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_WR_CHAN_DLY_CYC_reserved1_MASK 0x0000fff8
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_WR_CHAN_DLY_CYC_reserved1_SHIFT 3
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: WR_CHAN_DLY_CYC :: CYCLES [02:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_WR_CHAN_DLY_CYC_CYCLES_MASK 0x00000007
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_WR_CHAN_DLY_CYC_CYCLES_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_WR_CHAN_DLY_CYC_CYCLES_DEFAULT 0x00000000
-
-/***************************************************************************
- *READ_CONTROL - Read channel datapath control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_0_0 :: READ_CONTROL :: reserved0 [31:05] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_READ_CONTROL_reserved0_MASK 0xffffffe0
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_READ_CONTROL_reserved0_SHIFT 5
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: READ_CONTROL :: MODE [04:04] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_READ_CONTROL_MODE_MASK 0x00000010
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_READ_CONTROL_MODE_SHIFT 4
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_READ_CONTROL_MODE_DEFAULT 0x00000001
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: READ_CONTROL :: reserved1 [03:03] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_READ_CONTROL_reserved1_MASK 0x00000008
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_READ_CONTROL_reserved1_SHIFT 3
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: READ_CONTROL :: RD_DATA_DLY [02:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_READ_CONTROL_RD_DATA_DLY_MASK 0x00000007
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_READ_CONTROL_RD_DATA_DLY_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_READ_CONTROL_RD_DATA_DLY_DEFAULT 0x00000007
-
-/***************************************************************************
- *READ_FIFO_ADDR - Read fifo addresss pointer register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_0_0 :: READ_FIFO_ADDR :: reserved0 [31:03] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_READ_FIFO_ADDR_reserved0_MASK 0xfffffff8
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_READ_FIFO_ADDR_reserved0_SHIFT 3
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: READ_FIFO_ADDR :: ADDR [02:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_READ_FIFO_ADDR_ADDR_MASK 0x00000007
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_READ_FIFO_ADDR_ADDR_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_READ_FIFO_ADDR_ADDR_DEFAULT 0x00000000
-
-/***************************************************************************
- *READ_FIFO_DATA - Read fifo data register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_0_0 :: READ_FIFO_DATA :: DATA [31:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_READ_FIFO_DATA_DATA_MASK 0xffffffff
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_READ_FIFO_DATA_DATA_SHIFT 0
-
-/***************************************************************************
- *READ_FIFO_DM_DBI - Read fifo dm/dbi register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_0_0 :: READ_FIFO_DM_DBI :: reserved0 [31:04] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_READ_FIFO_DM_DBI_reserved0_MASK 0xfffffff0
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_READ_FIFO_DM_DBI_reserved0_SHIFT 4
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: READ_FIFO_DM_DBI :: DM_DBI [03:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_READ_FIFO_DM_DBI_DM_DBI_MASK 0x0000000f
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_READ_FIFO_DM_DBI_DM_DBI_SHIFT 0
-
-/***************************************************************************
- *READ_FIFO_STATUS - Read fifo status register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_0_0 :: READ_FIFO_STATUS :: reserved0 [31:02] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_READ_FIFO_STATUS_reserved0_MASK 0xfffffffc
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_READ_FIFO_STATUS_reserved0_SHIFT 2
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: READ_FIFO_STATUS :: OVERFLOW [01:01] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_READ_FIFO_STATUS_OVERFLOW_MASK 0x00000002
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_READ_FIFO_STATUS_OVERFLOW_SHIFT 1
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_READ_FIFO_STATUS_OVERFLOW_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: READ_FIFO_STATUS :: UNDERFLOW [00:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_READ_FIFO_STATUS_UNDERFLOW_MASK 0x00000001
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_READ_FIFO_STATUS_UNDERFLOW_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_READ_FIFO_STATUS_UNDERFLOW_DEFAULT 0x00000000
-
-/***************************************************************************
- *READ_FIFO_CLEAR - Read fifo status clear register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_0_0 :: READ_FIFO_CLEAR :: reserved0 [31:01] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_READ_FIFO_CLEAR_reserved0_MASK 0xfffffffe
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_READ_FIFO_CLEAR_reserved0_SHIFT 1
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: READ_FIFO_CLEAR :: CLEAR [00:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_READ_FIFO_CLEAR_CLEAR_MASK 0x00000001
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_READ_FIFO_CLEAR_CLEAR_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_READ_FIFO_CLEAR_CLEAR_DEFAULT 0x00000000
-
-/***************************************************************************
- *IDLE_PAD_CONTROL - Idle mode SSTL pad control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_0_0 :: IDLE_PAD_CONTROL :: IDLE [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_IDLE_PAD_CONTROL_IDLE_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_IDLE_PAD_CONTROL_IDLE_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_IDLE_PAD_CONTROL_IDLE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: IDLE_PAD_CONTROL :: reserved0 [30:20] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_IDLE_PAD_CONTROL_reserved0_MASK 0x7ff00000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_IDLE_PAD_CONTROL_reserved0_SHIFT 20
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: IDLE_PAD_CONTROL :: AUTO_DQ_RXENB_MODE [19:18] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_IDLE_PAD_CONTROL_AUTO_DQ_RXENB_MODE_MASK 0x000c0000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_IDLE_PAD_CONTROL_AUTO_DQ_RXENB_MODE_SHIFT 18
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_IDLE_PAD_CONTROL_AUTO_DQ_RXENB_MODE_DEFAULT 0x00000001
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: IDLE_PAD_CONTROL :: AUTO_DQ_IDDQ_MODE [17:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_IDLE_PAD_CONTROL_AUTO_DQ_IDDQ_MODE_MASK 0x00030000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_IDLE_PAD_CONTROL_AUTO_DQ_IDDQ_MODE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_IDLE_PAD_CONTROL_AUTO_DQ_IDDQ_MODE_DEFAULT 0x00000001
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: IDLE_PAD_CONTROL :: reserved_for_padding1 [15:15] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_IDLE_PAD_CONTROL_reserved_for_padding1_MASK 0x00008000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_IDLE_PAD_CONTROL_reserved_for_padding1_SHIFT 15
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: IDLE_PAD_CONTROL :: IO_IDLE_ENABLE [14:04] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_IDLE_PAD_CONTROL_IO_IDLE_ENABLE_MASK 0x00007ff0
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_IDLE_PAD_CONTROL_IO_IDLE_ENABLE_SHIFT 4
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_IDLE_PAD_CONTROL_IO_IDLE_ENABLE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: IDLE_PAD_CONTROL :: RXENB [03:03] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_IDLE_PAD_CONTROL_RXENB_MASK 0x00000008
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_IDLE_PAD_CONTROL_RXENB_SHIFT 3
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_IDLE_PAD_CONTROL_RXENB_DEFAULT 0x00000001
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: IDLE_PAD_CONTROL :: IDDQ [02:02] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_IDLE_PAD_CONTROL_IDDQ_MASK 0x00000004
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_IDLE_PAD_CONTROL_IDDQ_SHIFT 2
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_IDLE_PAD_CONTROL_IDDQ_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: IDLE_PAD_CONTROL :: DOUT_N [01:01] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_IDLE_PAD_CONTROL_DOUT_N_MASK 0x00000002
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_IDLE_PAD_CONTROL_DOUT_N_SHIFT 1
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: IDLE_PAD_CONTROL :: DOUT_P [00:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_IDLE_PAD_CONTROL_DOUT_P_MASK 0x00000001
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_IDLE_PAD_CONTROL_DOUT_P_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_IDLE_PAD_CONTROL_DOUT_P_DEFAULT 0x00000000
-
-/***************************************************************************
- *DRIVE_PAD_CTL - SSTL pad drive characteristics control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_0_0 :: DRIVE_PAD_CTL :: reserved0 [31:30] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_DRIVE_PAD_CTL_reserved0_MASK 0xc0000000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_DRIVE_PAD_CTL_reserved0_SHIFT 30
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: DRIVE_PAD_CTL :: BL_PD_IDLE_STRENGTH [29:25] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_DRIVE_PAD_CTL_BL_PD_IDLE_STRENGTH_MASK 0x3e000000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_DRIVE_PAD_CTL_BL_PD_IDLE_STRENGTH_SHIFT 25
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_DRIVE_PAD_CTL_BL_PD_IDLE_STRENGTH_DEFAULT 0x0000001f
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: DRIVE_PAD_CTL :: BL_ND_IDLE_STRENGTH [24:20] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_DRIVE_PAD_CTL_BL_ND_IDLE_STRENGTH_MASK 0x01f00000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_DRIVE_PAD_CTL_BL_ND_IDLE_STRENGTH_SHIFT 20
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_DRIVE_PAD_CTL_BL_ND_IDLE_STRENGTH_DEFAULT 0x0000001f
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: DRIVE_PAD_CTL :: BL_PD_TERM_STRENGTH [19:15] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_DRIVE_PAD_CTL_BL_PD_TERM_STRENGTH_MASK 0x000f8000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_DRIVE_PAD_CTL_BL_PD_TERM_STRENGTH_SHIFT 15
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_DRIVE_PAD_CTL_BL_PD_TERM_STRENGTH_DEFAULT 0x00000008
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: DRIVE_PAD_CTL :: BL_ND_TERM_STRENGTH [14:10] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_DRIVE_PAD_CTL_BL_ND_TERM_STRENGTH_MASK 0x00007c00
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_DRIVE_PAD_CTL_BL_ND_TERM_STRENGTH_SHIFT 10
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_DRIVE_PAD_CTL_BL_ND_TERM_STRENGTH_DEFAULT 0x00000008
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: DRIVE_PAD_CTL :: BL_PD_STRENGTH [09:05] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_DRIVE_PAD_CTL_BL_PD_STRENGTH_MASK 0x000003e0
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_DRIVE_PAD_CTL_BL_PD_STRENGTH_SHIFT 5
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_DRIVE_PAD_CTL_BL_PD_STRENGTH_DEFAULT 0x0000001f
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: DRIVE_PAD_CTL :: BL_ND_STRENGTH [04:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_DRIVE_PAD_CTL_BL_ND_STRENGTH_MASK 0x0000001f
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_DRIVE_PAD_CTL_BL_ND_STRENGTH_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_DRIVE_PAD_CTL_BL_ND_STRENGTH_DEFAULT 0x0000001f
-
-/***************************************************************************
- *RD_EN_DRIVE_PAD_CTL - SSTL read enable pad drive characteristics control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_0_0 :: RD_EN_DRIVE_PAD_CTL :: reserved0 [31:20] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_RD_EN_DRIVE_PAD_CTL_reserved0_MASK 0xfff00000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_RD_EN_DRIVE_PAD_CTL_reserved0_SHIFT 20
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: RD_EN_DRIVE_PAD_CTL :: EDC_RD_EN_PD_STRENGTH [19:15] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_RD_EN_DRIVE_PAD_CTL_EDC_RD_EN_PD_STRENGTH_MASK 0x000f8000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_RD_EN_DRIVE_PAD_CTL_EDC_RD_EN_PD_STRENGTH_SHIFT 15
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_RD_EN_DRIVE_PAD_CTL_EDC_RD_EN_PD_STRENGTH_DEFAULT 0x0000001f
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: RD_EN_DRIVE_PAD_CTL :: EDC_RD_EN_ND_STRENGTH [14:10] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_RD_EN_DRIVE_PAD_CTL_EDC_RD_EN_ND_STRENGTH_MASK 0x00007c00
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_RD_EN_DRIVE_PAD_CTL_EDC_RD_EN_ND_STRENGTH_SHIFT 10
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_RD_EN_DRIVE_PAD_CTL_EDC_RD_EN_ND_STRENGTH_DEFAULT 0x0000001f
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: RD_EN_DRIVE_PAD_CTL :: BL_RD_EN_PD_STRENGTH [09:05] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_RD_EN_DRIVE_PAD_CTL_BL_RD_EN_PD_STRENGTH_MASK 0x000003e0
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_RD_EN_DRIVE_PAD_CTL_BL_RD_EN_PD_STRENGTH_SHIFT 5
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_RD_EN_DRIVE_PAD_CTL_BL_RD_EN_PD_STRENGTH_DEFAULT 0x0000001f
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: RD_EN_DRIVE_PAD_CTL :: BL_RD_EN_ND_STRENGTH [04:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_RD_EN_DRIVE_PAD_CTL_BL_RD_EN_ND_STRENGTH_MASK 0x0000001f
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_RD_EN_DRIVE_PAD_CTL_BL_RD_EN_ND_STRENGTH_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_RD_EN_DRIVE_PAD_CTL_BL_RD_EN_ND_STRENGTH_DEFAULT 0x0000001f
-
-/***************************************************************************
- *STATIC_PAD_CTL - pad rx and tx characteristics control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_0_0 :: STATIC_PAD_CTL :: reserved0 [31:21] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_STATIC_PAD_CTL_reserved0_MASK 0xffe00000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_STATIC_PAD_CTL_reserved0_SHIFT 21
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: STATIC_PAD_CTL :: DQS_MODE [20:20] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_STATIC_PAD_CTL_DQS_MODE_MASK 0x00100000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_STATIC_PAD_CTL_DQS_MODE_SHIFT 20
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_STATIC_PAD_CTL_DQS_MODE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: STATIC_PAD_CTL :: reserved1 [19:18] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_STATIC_PAD_CTL_reserved1_MASK 0x000c0000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_STATIC_PAD_CTL_reserved1_SHIFT 18
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: STATIC_PAD_CTL :: EDC_MODE [17:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_STATIC_PAD_CTL_EDC_MODE_MASK 0x00030000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_STATIC_PAD_CTL_EDC_MODE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_STATIC_PAD_CTL_EDC_MODE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: STATIC_PAD_CTL :: reserved2 [15:15] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_STATIC_PAD_CTL_reserved2_MASK 0x00008000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_STATIC_PAD_CTL_reserved2_SHIFT 15
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: STATIC_PAD_CTL :: WDBI_ENABLE [14:14] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_STATIC_PAD_CTL_WDBI_ENABLE_MASK 0x00004000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_STATIC_PAD_CTL_WDBI_ENABLE_SHIFT 14
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_STATIC_PAD_CTL_WDBI_ENABLE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: STATIC_PAD_CTL :: RDBI_ENABLE [13:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_STATIC_PAD_CTL_RDBI_ENABLE_MASK 0x00002000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_STATIC_PAD_CTL_RDBI_ENABLE_SHIFT 13
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_STATIC_PAD_CTL_RDBI_ENABLE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: STATIC_PAD_CTL :: DM_MODE [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_STATIC_PAD_CTL_DM_MODE_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_STATIC_PAD_CTL_DM_MODE_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_STATIC_PAD_CTL_DM_MODE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: STATIC_PAD_CTL :: reserved3 [11:11] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_STATIC_PAD_CTL_reserved3_MASK 0x00000800
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_STATIC_PAD_CTL_reserved3_SHIFT 11
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: STATIC_PAD_CTL :: DQS_TX_PAUSE [10:10] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_STATIC_PAD_CTL_DQS_TX_PAUSE_MASK 0x00000400
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_STATIC_PAD_CTL_DQS_TX_PAUSE_SHIFT 10
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_STATIC_PAD_CTL_DQS_TX_PAUSE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: STATIC_PAD_CTL :: DQS_TX_DIS [09:09] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_STATIC_PAD_CTL_DQS_TX_DIS_MASK 0x00000200
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_STATIC_PAD_CTL_DQS_TX_DIS_SHIFT 9
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_STATIC_PAD_CTL_DQS_TX_DIS_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: STATIC_PAD_CTL :: reserved4 [08:08] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_STATIC_PAD_CTL_reserved4_MASK 0x00000100
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_STATIC_PAD_CTL_reserved4_SHIFT 8
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: STATIC_PAD_CTL :: TX_MODE [07:04] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_STATIC_PAD_CTL_TX_MODE_MASK 0x000000f0
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_STATIC_PAD_CTL_TX_MODE_SHIFT 4
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_STATIC_PAD_CTL_TX_MODE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: STATIC_PAD_CTL :: reserved5 [03:03] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_STATIC_PAD_CTL_reserved5_MASK 0x00000008
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_STATIC_PAD_CTL_reserved5_SHIFT 3
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: STATIC_PAD_CTL :: RX_MODE [02:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_STATIC_PAD_CTL_RX_MODE_MASK 0x00000007
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_STATIC_PAD_CTL_RX_MODE_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_STATIC_PAD_CTL_RX_MODE_DEFAULT 0x00000000
-
-/***************************************************************************
- *WR_PREAMBLE_MODE - Write cycle preamble control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_0_0 :: WR_PREAMBLE_MODE :: reserved0 [31:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_WR_PREAMBLE_MODE_reserved0_MASK 0xffff0000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_WR_PREAMBLE_MODE_reserved0_SHIFT 16
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: WR_PREAMBLE_MODE :: DQ_POSTAM_BITS [15:14] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_WR_PREAMBLE_MODE_DQ_POSTAM_BITS_MASK 0x0000c000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_WR_PREAMBLE_MODE_DQ_POSTAM_BITS_SHIFT 14
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_WR_PREAMBLE_MODE_DQ_POSTAM_BITS_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: WR_PREAMBLE_MODE :: DQ_PREAM_BITS [13:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_WR_PREAMBLE_MODE_DQ_PREAM_BITS_MASK 0x00003000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_WR_PREAMBLE_MODE_DQ_PREAM_BITS_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_WR_PREAMBLE_MODE_DQ_PREAM_BITS_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: WR_PREAMBLE_MODE :: DQS [11:08] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_WR_PREAMBLE_MODE_DQS_MASK 0x00000f00
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_WR_PREAMBLE_MODE_DQS_SHIFT 8
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_WR_PREAMBLE_MODE_DQS_DEFAULT 0x0000000e
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: WR_PREAMBLE_MODE :: reserved1 [07:05] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_WR_PREAMBLE_MODE_reserved1_MASK 0x000000e0
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_WR_PREAMBLE_MODE_reserved1_SHIFT 5
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: WR_PREAMBLE_MODE :: DQS_POSTAM_BITS [04:03] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_WR_PREAMBLE_MODE_DQS_POSTAM_BITS_MASK 0x00000018
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_WR_PREAMBLE_MODE_DQS_POSTAM_BITS_SHIFT 3
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_WR_PREAMBLE_MODE_DQS_POSTAM_BITS_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: WR_PREAMBLE_MODE :: DQS_PREAM_BITS [02:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_WR_PREAMBLE_MODE_DQS_PREAM_BITS_MASK 0x00000007
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_WR_PREAMBLE_MODE_DQS_PREAM_BITS_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_WR_PREAMBLE_MODE_DQS_PREAM_BITS_DEFAULT 0x00000002
-
-/***************************************************************************
- *ODT_CONTROL - Read channel ODT control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_0_0 :: ODT_CONTROL :: reserved_for_padding0 [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_ODT_CONTROL_reserved_for_padding0_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_ODT_CONTROL_reserved_for_padding0_SHIFT 31
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: ODT_CONTROL :: reserved1 [30:10] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_ODT_CONTROL_reserved1_MASK 0x7ffffc00
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_ODT_CONTROL_reserved1_SHIFT 10
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: ODT_CONTROL :: ODT_ENABLE [09:09] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_ODT_CONTROL_ODT_ENABLE_MASK 0x00000200
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_ODT_CONTROL_ODT_ENABLE_SHIFT 9
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_ODT_CONTROL_ODT_ENABLE_DEFAULT 0x00000001
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: ODT_CONTROL :: ODT_DELAY [08:06] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_ODT_CONTROL_ODT_DELAY_MASK 0x000001c0
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_ODT_CONTROL_ODT_DELAY_SHIFT 6
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_ODT_CONTROL_ODT_DELAY_DEFAULT 0x00000001
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: ODT_CONTROL :: ODT_POST_LENGTH [05:03] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_ODT_CONTROL_ODT_POST_LENGTH_MASK 0x00000038
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_ODT_CONTROL_ODT_POST_LENGTH_SHIFT 3
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_ODT_CONTROL_ODT_POST_LENGTH_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: ODT_CONTROL :: ODT_PRE_LENGTH [02:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_ODT_CONTROL_ODT_PRE_LENGTH_MASK 0x00000007
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_ODT_CONTROL_ODT_PRE_LENGTH_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_ODT_CONTROL_ODT_PRE_LENGTH_DEFAULT 0x00000003
-
-/***************************************************************************
- *EDC_DPD_CONTROL - GDDR5M EDC digital phase detector control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_0_0 :: EDC_DPD_CONTROL :: reserved0 [31:06] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_DPD_CONTROL_reserved0_MASK 0xffffffc0
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_DPD_CONTROL_reserved0_SHIFT 6
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: EDC_DPD_CONTROL :: DQS_PHASE_OVERRIDE_VALUE [05:05] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_DPD_CONTROL_DQS_PHASE_OVERRIDE_VALUE_MASK 0x00000020
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_DPD_CONTROL_DQS_PHASE_OVERRIDE_VALUE_SHIFT 5
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_DPD_CONTROL_DQS_PHASE_OVERRIDE_VALUE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: EDC_DPD_CONTROL :: DQS_PHASE_OVERRIDE_ENABLE [04:04] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_DPD_CONTROL_DQS_PHASE_OVERRIDE_ENABLE_MASK 0x00000010
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_DPD_CONTROL_DQS_PHASE_OVERRIDE_ENABLE_SHIFT 4
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_DPD_CONTROL_DQS_PHASE_OVERRIDE_ENABLE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: EDC_DPD_CONTROL :: SET_ADJ_EN [03:03] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_DPD_CONTROL_SET_ADJ_EN_MASK 0x00000008
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_DPD_CONTROL_SET_ADJ_EN_SHIFT 3
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_DPD_CONTROL_SET_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: EDC_DPD_CONTROL :: UPDATE [02:02] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_DPD_CONTROL_UPDATE_MASK 0x00000004
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_DPD_CONTROL_UPDATE_SHIFT 2
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_DPD_CONTROL_UPDATE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: EDC_DPD_CONTROL :: MONITOR [01:01] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_DPD_CONTROL_MONITOR_MASK 0x00000002
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_DPD_CONTROL_MONITOR_SHIFT 1
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_DPD_CONTROL_MONITOR_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: EDC_DPD_CONTROL :: INIT [00:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_DPD_CONTROL_INIT_MASK 0x00000001
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_DPD_CONTROL_INIT_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_DPD_CONTROL_INIT_DEFAULT 0x00000000
-
-/***************************************************************************
- *EDC_DPD_STATUS - GDDR5M EDC digital phase detector status register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_0_0 :: EDC_DPD_STATUS :: reserved0 [31:25] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_DPD_STATUS_reserved0_MASK 0xfe000000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_DPD_STATUS_reserved0_SHIFT 25
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: EDC_DPD_STATUS :: CURRENT_DQS_PHASE [24:24] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_DPD_STATUS_CURRENT_DQS_PHASE_MASK 0x01000000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_DPD_STATUS_CURRENT_DQS_PHASE_SHIFT 24
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_DPD_STATUS_CURRENT_DQS_PHASE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: EDC_DPD_STATUS :: CURRENT_VDL_SETTING [23:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_DPD_STATUS_CURRENT_VDL_SETTING_MASK 0x00ff0000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_DPD_STATUS_CURRENT_VDL_SETTING_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_DPD_STATUS_CURRENT_VDL_SETTING_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: EDC_DPD_STATUS :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_DPD_STATUS_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_DPD_STATUS_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: EDC_DPD_STATUS :: INIT_DQS_PHASE [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_DPD_STATUS_INIT_DQS_PHASE_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_DPD_STATUS_INIT_DQS_PHASE_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_DPD_STATUS_INIT_DQS_PHASE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: EDC_DPD_STATUS :: INIT_VDL_SETTING [11:04] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_DPD_STATUS_INIT_VDL_SETTING_MASK 0x00000ff0
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_DPD_STATUS_INIT_VDL_SETTING_SHIFT 4
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_DPD_STATUS_INIT_VDL_SETTING_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: EDC_DPD_STATUS :: EDGE_ERROR [03:03] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_DPD_STATUS_EDGE_ERROR_MASK 0x00000008
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_DPD_STATUS_EDGE_ERROR_SHIFT 3
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_DPD_STATUS_EDGE_ERROR_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: EDC_DPD_STATUS :: MONITOR_BUSY [02:02] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_DPD_STATUS_MONITOR_BUSY_MASK 0x00000004
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_DPD_STATUS_MONITOR_BUSY_SHIFT 2
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_DPD_STATUS_MONITOR_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: EDC_DPD_STATUS :: INIT_BUSY [01:01] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_DPD_STATUS_INIT_BUSY_MASK 0x00000002
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_DPD_STATUS_INIT_BUSY_SHIFT 1
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_DPD_STATUS_INIT_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: EDC_DPD_STATUS :: INIT_DONE [00:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_DPD_STATUS_INIT_DONE_MASK 0x00000001
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_DPD_STATUS_INIT_DONE_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_DPD_STATUS_INIT_DONE_DEFAULT 0x00000000
-
-/***************************************************************************
- *EDC_DPD_OUT_CONTROL - GDDR5M EDC digital phase detector output signal control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_0_0 :: EDC_DPD_OUT_CONTROL :: reserved0 [31:20] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_DPD_OUT_CONTROL_reserved0_MASK 0xfff00000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_DPD_OUT_CONTROL_reserved0_SHIFT 20
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: EDC_DPD_OUT_CONTROL :: LOWER_LIMIT [19:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_DPD_OUT_CONTROL_LOWER_LIMIT_MASK 0x000ff000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_DPD_OUT_CONTROL_LOWER_LIMIT_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_DPD_OUT_CONTROL_LOWER_LIMIT_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: EDC_DPD_OUT_CONTROL :: UPPER_LIMIT [11:04] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_DPD_OUT_CONTROL_UPPER_LIMIT_MASK 0x00000ff0
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_DPD_OUT_CONTROL_UPPER_LIMIT_SHIFT 4
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_DPD_OUT_CONTROL_UPPER_LIMIT_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: EDC_DPD_OUT_CONTROL :: reserved1 [03:01] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_DPD_OUT_CONTROL_reserved1_MASK 0x0000000e
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_DPD_OUT_CONTROL_reserved1_SHIFT 1
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: EDC_DPD_OUT_CONTROL :: ENABLE [00:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_DPD_OUT_CONTROL_ENABLE_MASK 0x00000001
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_DPD_OUT_CONTROL_ENABLE_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_DPD_OUT_CONTROL_ENABLE_DEFAULT 0x00000000
-
-/***************************************************************************
- *EDC_DPD_OUT_STATUS - GDDR5M EDC digital phase detector output signal status register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_0_0 :: EDC_DPD_OUT_STATUS :: reserved0 [31:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_DPD_OUT_STATUS_reserved0_MASK 0xfffff000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_DPD_OUT_STATUS_reserved0_SHIFT 12
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: EDC_DPD_OUT_STATUS :: VDL_SETTING [11:04] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_DPD_OUT_STATUS_VDL_SETTING_MASK 0x00000ff0
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_DPD_OUT_STATUS_VDL_SETTING_SHIFT 4
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_DPD_OUT_STATUS_VDL_SETTING_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: EDC_DPD_OUT_STATUS :: reserved1 [03:01] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_DPD_OUT_STATUS_reserved1_MASK 0x0000000e
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_DPD_OUT_STATUS_reserved1_SHIFT 1
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: EDC_DPD_OUT_STATUS :: VALID [00:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_DPD_OUT_STATUS_VALID_MASK 0x00000001
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_DPD_OUT_STATUS_VALID_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_DPD_OUT_STATUS_VALID_DEFAULT 0x00000000
-
-/***************************************************************************
- *EDC_DPD_OUT_STATUS_CLEAR - GDDR5M EDC digital phase detector output signal status clear register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_0_0 :: EDC_DPD_OUT_STATUS_CLEAR :: reserved0 [31:01] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_DPD_OUT_STATUS_CLEAR_reserved0_MASK 0xfffffffe
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_DPD_OUT_STATUS_CLEAR_reserved0_SHIFT 1
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: EDC_DPD_OUT_STATUS_CLEAR :: CLEAR [00:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_DPD_OUT_STATUS_CLEAR_CLEAR_MASK 0x00000001
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_DPD_OUT_STATUS_CLEAR_CLEAR_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_DPD_OUT_STATUS_CLEAR_CLEAR_DEFAULT 0x00000000
-
-/***************************************************************************
- *EDC_CRC_CONTROL - GDDR5M EDC signal path CRC control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_0_0 :: EDC_CRC_CONTROL :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_CRC_CONTROL_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_CRC_CONTROL_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_CRC_CONTROL_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: EDC_CRC_CONTROL :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_CRC_CONTROL_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_CRC_CONTROL_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: EDC_CRC_CONTROL :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_CRC_CONTROL_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_CRC_CONTROL_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_CRC_CONTROL_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: EDC_CRC_CONTROL :: reserved1 [15:11] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_CRC_CONTROL_reserved1_MASK 0x0000f800
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_CRC_CONTROL_reserved1_SHIFT 11
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: EDC_CRC_CONTROL :: CRCWL [10:08] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_CRC_CONTROL_CRCWL_MASK 0x00000700
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_CRC_CONTROL_CRCWL_SHIFT 8
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_CRC_CONTROL_CRCWL_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: EDC_CRC_CONTROL :: reserved2 [07:06] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_CRC_CONTROL_reserved2_MASK 0x000000c0
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_CRC_CONTROL_reserved2_SHIFT 6
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: EDC_CRC_CONTROL :: CRCRL [05:04] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_CRC_CONTROL_CRCRL_MASK 0x00000030
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_CRC_CONTROL_CRCRL_SHIFT 4
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_CRC_CONTROL_CRCRL_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: EDC_CRC_CONTROL :: reserved3 [03:03] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_CRC_CONTROL_reserved3_MASK 0x00000008
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_CRC_CONTROL_reserved3_SHIFT 3
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: EDC_CRC_CONTROL :: COUNT_MODE [02:02] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_CRC_CONTROL_COUNT_MODE_MASK 0x00000004
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_CRC_CONTROL_COUNT_MODE_SHIFT 2
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_CRC_CONTROL_COUNT_MODE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: EDC_CRC_CONTROL :: ENABLE_WR [01:01] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_CRC_CONTROL_ENABLE_WR_MASK 0x00000002
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_CRC_CONTROL_ENABLE_WR_SHIFT 1
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_CRC_CONTROL_ENABLE_WR_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: EDC_CRC_CONTROL :: ENABLE_RD [00:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_CRC_CONTROL_ENABLE_RD_MASK 0x00000001
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_CRC_CONTROL_ENABLE_RD_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_CRC_CONTROL_ENABLE_RD_DEFAULT 0x00000000
-
-/***************************************************************************
- *EDC_CRC_STATUS - GDDR5M EDC signal path CRC status register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_0_0 :: EDC_CRC_STATUS :: reserved0 [31:04] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_CRC_STATUS_reserved0_MASK 0xfffffff0
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_CRC_STATUS_reserved0_SHIFT 4
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: EDC_CRC_STATUS :: WR_FAIL [03:03] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_CRC_STATUS_WR_FAIL_MASK 0x00000008
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_CRC_STATUS_WR_FAIL_SHIFT 3
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_CRC_STATUS_WR_FAIL_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: EDC_CRC_STATUS :: WR_PASS [02:02] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_CRC_STATUS_WR_PASS_MASK 0x00000004
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_CRC_STATUS_WR_PASS_SHIFT 2
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_CRC_STATUS_WR_PASS_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: EDC_CRC_STATUS :: RD_FAIL [01:01] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_CRC_STATUS_RD_FAIL_MASK 0x00000002
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_CRC_STATUS_RD_FAIL_SHIFT 1
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_CRC_STATUS_RD_FAIL_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: EDC_CRC_STATUS :: RD_PASS [00:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_CRC_STATUS_RD_PASS_MASK 0x00000001
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_CRC_STATUS_RD_PASS_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_CRC_STATUS_RD_PASS_DEFAULT 0x00000000
-
-/***************************************************************************
- *EDC_CRC_COUNT - GDDR5M EDC signal path CRC counter register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_0_0 :: EDC_CRC_COUNT :: reserved0 [31:28] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_CRC_COUNT_reserved0_MASK 0xf0000000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_CRC_COUNT_reserved0_SHIFT 28
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: EDC_CRC_COUNT :: WR_COUNT [27:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_CRC_COUNT_WR_COUNT_MASK 0x0fff0000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_CRC_COUNT_WR_COUNT_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_CRC_COUNT_WR_COUNT_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: EDC_CRC_COUNT :: reserved1 [15:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_CRC_COUNT_reserved1_MASK 0x0000f000
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_CRC_COUNT_reserved1_SHIFT 12
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: EDC_CRC_COUNT :: RD_COUNT [11:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_CRC_COUNT_RD_COUNT_MASK 0x00000fff
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_CRC_COUNT_RD_COUNT_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_CRC_COUNT_RD_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *EDC_CRC_STATUS_CLEAR - GDDR5M EDC signal path CRC counter register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_0_0 :: EDC_CRC_STATUS_CLEAR :: reserved0 [31:01] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_CRC_STATUS_CLEAR_reserved0_MASK 0xfffffffe
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_CRC_STATUS_CLEAR_reserved0_SHIFT 1
-
-/* DDR34_PHY_BYTE_LANE_0_0 :: EDC_CRC_STATUS_CLEAR :: CLEAR [00:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_CRC_STATUS_CLEAR_CLEAR_MASK 0x00000001
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_CRC_STATUS_CLEAR_CLEAR_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_CRC_STATUS_CLEAR_CLEAR_DEFAULT 0x00000000
-
-/***************************************************************************
- *BL_SPARE_REG - Byte-Lane Spare register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_0_0 :: BL_SPARE_REG :: reserved_for_eco0 [31:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_BL_SPARE_REG_reserved_for_eco0_MASK 0xffffffff
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_BL_SPARE_REG_reserved_for_eco0_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_0_0_BL_SPARE_REG_reserved_for_eco0_DEFAULT 0x00000000
-
-#endif /* #ifndef BCHP_DDR34_PHY_BYTE_LANE_0_0_H__ */
-
-/* End of File */
diff --git a/include/linux/brcmstb/7439a0/bchp_ddr34_phy_byte_lane_1_0.h b/include/linux/brcmstb/7439a0/bchp_ddr34_phy_byte_lane_1_0.h
deleted file mode 100644
index 433045f..0000000
--- a/include/linux/brcmstb/7439a0/bchp_ddr34_phy_byte_lane_1_0.h
+++ /dev/null
@@ -1,2099 +0,0 @@
-/***************************************************************************
- * Copyright (c) 1999-2013, Broadcom Corporation
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
- *
- * Module Description:
- * DO NOT EDIT THIS FILE DIRECTLY
- *
- * This module was generated magically with RDB from a source description
- * file. You must edit the source file for changes to be made to this file.
- *
- *
- * Date: Generated on Tue Apr 16 03:26:52 2013
- * MD5 Checksum d41d8cd98f00b204e9800998ecf8427e
- *
- * Compiled with: RDB Utility combo_header.pl
- * RDB Parser 3.0
- * unknown unknown
- * Perl Interpreter 5.008008
- * Operating System linux
- *
- * Revision History:
- *
- * $brcm_Log: $
- *
- ***************************************************************************/
-
-#ifndef BCHP_DDR34_PHY_BYTE_LANE_1_0_H__
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_H__
-
-/***************************************************************************
- *DDR34_PHY_BYTE_LANE_1_0 - 0 DDR34 DDR34 Byte Lane #1 control registers
- ***************************************************************************/
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQS_P 0x00906600 /* Write channel DQS-P VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQS_N 0x00906604 /* Write channel DQS-N VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ0 0x00906608 /* Write channel DQ0 VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ1 0x0090660c /* Write channel DQ1 VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ2 0x00906610 /* Write channel DQ2 VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ3 0x00906614 /* Write channel DQ3 VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ4 0x00906618 /* Write channel DQ4 VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ5 0x0090661c /* Write channel DQ5 VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ6 0x00906620 /* Write channel DQ6 VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ7 0x00906624 /* Write channel DQ7 VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DM 0x00906628 /* Write channel DM VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_EDC 0x0090662c /* Write channel EDC VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQSP 0x00906630 /* Read channel DQSP VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQSN 0x00906634 /* Read channel DQSP VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ0P 0x00906638 /* Read channel DQ0-P VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ0N 0x0090663c /* Read channel DQ0-N VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ1P 0x00906640 /* Read channel DQ1-P VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ1N 0x00906644 /* Read channel DQ1-N VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ2P 0x00906648 /* Read channel DQ2-P VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ2N 0x0090664c /* Read channel DQ2-N VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ3P 0x00906650 /* Read channel DQ3-P VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ3N 0x00906654 /* Read channel DQ3-N VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ4P 0x00906658 /* Read channel DQ4-P VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ4N 0x0090665c /* Read channel DQ4-N VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ5P 0x00906660 /* Read channel DQ5-P VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ5N 0x00906664 /* Read channel DQ5-N VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ6P 0x00906668 /* Read channel DQ6-P VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ6N 0x0090666c /* Read channel DQ6-N VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ7P 0x00906670 /* Read channel DQ7-P VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ7N 0x00906674 /* Read channel DQ7-N VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DMP 0x00906678 /* Read channel DM-P VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DMN 0x0090667c /* Read channel DM-N VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_EDCP 0x00906680 /* Read channel EDC-P VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_EDCN 0x00906684 /* Read channel EDC-N VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_EN_CS0 0x00906688 /* Read channel CS_N[0] read enable VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_EN_CS1 0x0090668c /* Read channel CS_N[1] read enable VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CLK_CONTROL 0x00906690 /* DDR interface signal Write Leveling CLK VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_LDE_CONTROL 0x00906694 /* DDR interface signal Write Leveling Capture Enable VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_RD_EN_DLY_CYC 0x009066a0 /* Read enable bit-clock cycle delay control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_WR_CHAN_DLY_CYC 0x009066a4 /* Write leveling bit-clock cycle delay control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_READ_CONTROL 0x009066b0 /* Read channel datapath control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_READ_FIFO_ADDR 0x009066b4 /* Read fifo addresss pointer register */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_READ_FIFO_DATA 0x009066b8 /* Read fifo data register */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_READ_FIFO_DM_DBI 0x009066bc /* Read fifo dm/dbi register */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_READ_FIFO_STATUS 0x009066c0 /* Read fifo status register */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_READ_FIFO_CLEAR 0x009066c4 /* Read fifo status clear register */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_IDLE_PAD_CONTROL 0x009066c8 /* Idle mode SSTL pad control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_DRIVE_PAD_CTL 0x009066cc /* SSTL pad drive characteristics control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_RD_EN_DRIVE_PAD_CTL 0x009066d0 /* SSTL read enable pad drive characteristics control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_STATIC_PAD_CTL 0x009066d4 /* pad rx and tx characteristics control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_WR_PREAMBLE_MODE 0x009066d8 /* Write cycle preamble control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_ODT_CONTROL 0x009066e0 /* Read channel ODT control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_DPD_CONTROL 0x009066f0 /* GDDR5M EDC digital phase detector control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_DPD_STATUS 0x009066f4 /* GDDR5M EDC digital phase detector status register */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_DPD_OUT_CONTROL 0x009066f8 /* GDDR5M EDC digital phase detector output signal control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_DPD_OUT_STATUS 0x009066fc /* GDDR5M EDC digital phase detector output signal status register */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_DPD_OUT_STATUS_CLEAR 0x00906700 /* GDDR5M EDC digital phase detector output signal status clear register */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_CRC_CONTROL 0x00906704 /* GDDR5M EDC signal path CRC control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_CRC_STATUS 0x00906708 /* GDDR5M EDC signal path CRC status register */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_CRC_COUNT 0x0090670c /* GDDR5M EDC signal path CRC counter register */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_CRC_STATUS_CLEAR 0x00906710 /* GDDR5M EDC signal path CRC counter register */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_BL_SPARE_REG 0x00906714 /* Byte-Lane Spare register */
-
-/***************************************************************************
- *VDL_CONTROL_WR_DQS_P - Write channel DQS-P VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_WR_DQS_P :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQS_P_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQS_P_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQS_P_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_WR_DQS_P :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQS_P_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQS_P_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_WR_DQS_P :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQS_P_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQS_P_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQS_P_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_WR_DQS_P :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQS_P_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQS_P_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_WR_DQS_P :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQS_P_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQS_P_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQS_P_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_WR_DQS_P :: reserved2 [11:09] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQS_P_reserved2_MASK 0x00000e00
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQS_P_reserved2_SHIFT 9
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_WR_DQS_P :: VDL_STEP [08:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQS_P_VDL_STEP_MASK 0x000001ff
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQS_P_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQS_P_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_WR_DQS_N - Write channel DQS-N VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_WR_DQS_N :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQS_N_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQS_N_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQS_N_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_WR_DQS_N :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQS_N_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQS_N_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_WR_DQS_N :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQS_N_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQS_N_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQS_N_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_WR_DQS_N :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQS_N_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQS_N_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_WR_DQS_N :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQS_N_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQS_N_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQS_N_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_WR_DQS_N :: reserved2 [11:09] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQS_N_reserved2_MASK 0x00000e00
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQS_N_reserved2_SHIFT 9
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_WR_DQS_N :: VDL_STEP [08:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQS_N_VDL_STEP_MASK 0x000001ff
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQS_N_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQS_N_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_WR_DQ0 - Write channel DQ0 VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_WR_DQ0 :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ0_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ0_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ0_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_WR_DQ0 :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ0_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ0_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_WR_DQ0 :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ0_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ0_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ0_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_WR_DQ0 :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ0_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ0_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_WR_DQ0 :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ0_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ0_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ0_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_WR_DQ0 :: reserved2 [11:09] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ0_reserved2_MASK 0x00000e00
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ0_reserved2_SHIFT 9
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_WR_DQ0 :: VDL_STEP [08:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ0_VDL_STEP_MASK 0x000001ff
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ0_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ0_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_WR_DQ1 - Write channel DQ1 VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_WR_DQ1 :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ1_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ1_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ1_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_WR_DQ1 :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ1_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ1_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_WR_DQ1 :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ1_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ1_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ1_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_WR_DQ1 :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ1_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ1_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_WR_DQ1 :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ1_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ1_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ1_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_WR_DQ1 :: reserved2 [11:09] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ1_reserved2_MASK 0x00000e00
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ1_reserved2_SHIFT 9
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_WR_DQ1 :: VDL_STEP [08:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ1_VDL_STEP_MASK 0x000001ff
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ1_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ1_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_WR_DQ2 - Write channel DQ2 VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_WR_DQ2 :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ2_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ2_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ2_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_WR_DQ2 :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ2_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ2_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_WR_DQ2 :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ2_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ2_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ2_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_WR_DQ2 :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ2_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ2_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_WR_DQ2 :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ2_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ2_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ2_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_WR_DQ2 :: reserved2 [11:09] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ2_reserved2_MASK 0x00000e00
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ2_reserved2_SHIFT 9
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_WR_DQ2 :: VDL_STEP [08:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ2_VDL_STEP_MASK 0x000001ff
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ2_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ2_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_WR_DQ3 - Write channel DQ3 VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_WR_DQ3 :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ3_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ3_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ3_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_WR_DQ3 :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ3_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ3_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_WR_DQ3 :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ3_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ3_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ3_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_WR_DQ3 :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ3_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ3_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_WR_DQ3 :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ3_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ3_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ3_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_WR_DQ3 :: reserved2 [11:09] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ3_reserved2_MASK 0x00000e00
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ3_reserved2_SHIFT 9
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_WR_DQ3 :: VDL_STEP [08:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ3_VDL_STEP_MASK 0x000001ff
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ3_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ3_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_WR_DQ4 - Write channel DQ4 VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_WR_DQ4 :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ4_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ4_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ4_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_WR_DQ4 :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ4_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ4_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_WR_DQ4 :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ4_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ4_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ4_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_WR_DQ4 :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ4_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ4_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_WR_DQ4 :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ4_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ4_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ4_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_WR_DQ4 :: reserved2 [11:09] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ4_reserved2_MASK 0x00000e00
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ4_reserved2_SHIFT 9
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_WR_DQ4 :: VDL_STEP [08:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ4_VDL_STEP_MASK 0x000001ff
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ4_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ4_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_WR_DQ5 - Write channel DQ5 VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_WR_DQ5 :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ5_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ5_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ5_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_WR_DQ5 :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ5_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ5_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_WR_DQ5 :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ5_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ5_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ5_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_WR_DQ5 :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ5_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ5_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_WR_DQ5 :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ5_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ5_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ5_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_WR_DQ5 :: reserved2 [11:09] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ5_reserved2_MASK 0x00000e00
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ5_reserved2_SHIFT 9
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_WR_DQ5 :: VDL_STEP [08:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ5_VDL_STEP_MASK 0x000001ff
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ5_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ5_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_WR_DQ6 - Write channel DQ6 VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_WR_DQ6 :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ6_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ6_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ6_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_WR_DQ6 :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ6_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ6_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_WR_DQ6 :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ6_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ6_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ6_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_WR_DQ6 :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ6_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ6_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_WR_DQ6 :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ6_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ6_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ6_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_WR_DQ6 :: reserved2 [11:09] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ6_reserved2_MASK 0x00000e00
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ6_reserved2_SHIFT 9
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_WR_DQ6 :: VDL_STEP [08:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ6_VDL_STEP_MASK 0x000001ff
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ6_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ6_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_WR_DQ7 - Write channel DQ7 VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_WR_DQ7 :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ7_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ7_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ7_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_WR_DQ7 :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ7_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ7_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_WR_DQ7 :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ7_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ7_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ7_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_WR_DQ7 :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ7_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ7_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_WR_DQ7 :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ7_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ7_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ7_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_WR_DQ7 :: reserved2 [11:09] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ7_reserved2_MASK 0x00000e00
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ7_reserved2_SHIFT 9
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_WR_DQ7 :: VDL_STEP [08:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ7_VDL_STEP_MASK 0x000001ff
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ7_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ7_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_WR_DM - Write channel DM VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_WR_DM :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DM_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DM_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DM_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_WR_DM :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DM_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DM_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_WR_DM :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DM_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DM_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DM_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_WR_DM :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DM_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DM_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_WR_DM :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DM_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DM_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DM_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_WR_DM :: reserved2 [11:09] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DM_reserved2_MASK 0x00000e00
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DM_reserved2_SHIFT 9
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_WR_DM :: VDL_STEP [08:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DM_VDL_STEP_MASK 0x000001ff
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DM_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DM_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_WR_EDC - Write channel EDC VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_WR_EDC :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_EDC_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_EDC_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_EDC_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_WR_EDC :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_EDC_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_EDC_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_WR_EDC :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_EDC_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_EDC_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_EDC_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_WR_EDC :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_EDC_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_EDC_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_WR_EDC :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_EDC_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_EDC_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_EDC_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_WR_EDC :: reserved2 [11:09] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_EDC_reserved2_MASK 0x00000e00
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_EDC_reserved2_SHIFT 9
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_WR_EDC :: VDL_STEP [08:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_EDC_VDL_STEP_MASK 0x000001ff
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_EDC_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_EDC_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_RD_DQSP - Read channel DQSP VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_DQSP :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQSP_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQSP_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQSP_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_DQSP :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQSP_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQSP_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_DQSP :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQSP_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQSP_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQSP_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_DQSP :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQSP_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQSP_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_DQSP :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQSP_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQSP_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQSP_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_DQSP :: reserved2 [11:08] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQSP_reserved2_MASK 0x00000f00
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQSP_reserved2_SHIFT 8
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_DQSP :: VDL_STEP [07:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQSP_VDL_STEP_MASK 0x000000ff
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQSP_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQSP_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_RD_DQSN - Read channel DQSP VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_DQSN :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQSN_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQSN_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQSN_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_DQSN :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQSN_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQSN_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_DQSN :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQSN_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQSN_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQSN_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_DQSN :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQSN_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQSN_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_DQSN :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQSN_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQSN_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQSN_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_DQSN :: reserved2 [11:08] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQSN_reserved2_MASK 0x00000f00
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQSN_reserved2_SHIFT 8
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_DQSN :: VDL_STEP [07:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQSN_VDL_STEP_MASK 0x000000ff
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQSN_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQSN_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_RD_DQ0P - Read channel DQ0-P VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_DQ0P :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ0P_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ0P_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ0P_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_DQ0P :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ0P_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ0P_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_DQ0P :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ0P_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ0P_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ0P_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_DQ0P :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ0P_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ0P_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_DQ0P :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ0P_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ0P_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ0P_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_DQ0P :: reserved2 [11:08] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ0P_reserved2_MASK 0x00000f00
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ0P_reserved2_SHIFT 8
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_DQ0P :: VDL_STEP [07:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ0P_VDL_STEP_MASK 0x000000ff
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ0P_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ0P_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_RD_DQ0N - Read channel DQ0-N VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_DQ0N :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ0N_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ0N_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ0N_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_DQ0N :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ0N_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ0N_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_DQ0N :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ0N_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ0N_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ0N_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_DQ0N :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ0N_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ0N_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_DQ0N :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ0N_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ0N_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ0N_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_DQ0N :: reserved2 [11:08] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ0N_reserved2_MASK 0x00000f00
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ0N_reserved2_SHIFT 8
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_DQ0N :: VDL_STEP [07:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ0N_VDL_STEP_MASK 0x000000ff
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ0N_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ0N_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_RD_DQ1P - Read channel DQ1-P VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_DQ1P :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ1P_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ1P_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ1P_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_DQ1P :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ1P_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ1P_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_DQ1P :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ1P_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ1P_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ1P_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_DQ1P :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ1P_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ1P_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_DQ1P :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ1P_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ1P_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ1P_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_DQ1P :: reserved2 [11:08] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ1P_reserved2_MASK 0x00000f00
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ1P_reserved2_SHIFT 8
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_DQ1P :: VDL_STEP [07:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ1P_VDL_STEP_MASK 0x000000ff
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ1P_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ1P_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_RD_DQ1N - Read channel DQ1-N VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_DQ1N :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ1N_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ1N_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ1N_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_DQ1N :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ1N_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ1N_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_DQ1N :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ1N_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ1N_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ1N_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_DQ1N :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ1N_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ1N_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_DQ1N :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ1N_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ1N_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ1N_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_DQ1N :: reserved2 [11:08] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ1N_reserved2_MASK 0x00000f00
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ1N_reserved2_SHIFT 8
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_DQ1N :: VDL_STEP [07:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ1N_VDL_STEP_MASK 0x000000ff
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ1N_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ1N_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_RD_DQ2P - Read channel DQ2-P VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_DQ2P :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ2P_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ2P_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ2P_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_DQ2P :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ2P_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ2P_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_DQ2P :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ2P_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ2P_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ2P_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_DQ2P :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ2P_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ2P_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_DQ2P :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ2P_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ2P_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ2P_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_DQ2P :: reserved2 [11:08] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ2P_reserved2_MASK 0x00000f00
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ2P_reserved2_SHIFT 8
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_DQ2P :: VDL_STEP [07:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ2P_VDL_STEP_MASK 0x000000ff
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ2P_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ2P_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_RD_DQ2N - Read channel DQ2-N VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_DQ2N :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ2N_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ2N_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ2N_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_DQ2N :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ2N_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ2N_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_DQ2N :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ2N_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ2N_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ2N_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_DQ2N :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ2N_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ2N_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_DQ2N :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ2N_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ2N_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ2N_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_DQ2N :: reserved2 [11:08] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ2N_reserved2_MASK 0x00000f00
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ2N_reserved2_SHIFT 8
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_DQ2N :: VDL_STEP [07:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ2N_VDL_STEP_MASK 0x000000ff
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ2N_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ2N_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_RD_DQ3P - Read channel DQ3-P VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_DQ3P :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ3P_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ3P_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ3P_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_DQ3P :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ3P_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ3P_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_DQ3P :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ3P_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ3P_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ3P_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_DQ3P :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ3P_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ3P_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_DQ3P :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ3P_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ3P_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ3P_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_DQ3P :: reserved2 [11:08] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ3P_reserved2_MASK 0x00000f00
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ3P_reserved2_SHIFT 8
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_DQ3P :: VDL_STEP [07:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ3P_VDL_STEP_MASK 0x000000ff
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ3P_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ3P_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_RD_DQ3N - Read channel DQ3-N VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_DQ3N :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ3N_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ3N_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ3N_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_DQ3N :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ3N_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ3N_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_DQ3N :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ3N_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ3N_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ3N_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_DQ3N :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ3N_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ3N_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_DQ3N :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ3N_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ3N_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ3N_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_DQ3N :: reserved2 [11:08] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ3N_reserved2_MASK 0x00000f00
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ3N_reserved2_SHIFT 8
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_DQ3N :: VDL_STEP [07:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ3N_VDL_STEP_MASK 0x000000ff
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ3N_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ3N_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_RD_DQ4P - Read channel DQ4-P VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_DQ4P :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ4P_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ4P_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ4P_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_DQ4P :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ4P_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ4P_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_DQ4P :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ4P_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ4P_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ4P_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_DQ4P :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ4P_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ4P_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_DQ4P :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ4P_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ4P_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ4P_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_DQ4P :: reserved2 [11:08] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ4P_reserved2_MASK 0x00000f00
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ4P_reserved2_SHIFT 8
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_DQ4P :: VDL_STEP [07:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ4P_VDL_STEP_MASK 0x000000ff
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ4P_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ4P_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_RD_DQ4N - Read channel DQ4-N VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_DQ4N :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ4N_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ4N_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ4N_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_DQ4N :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ4N_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ4N_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_DQ4N :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ4N_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ4N_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ4N_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_DQ4N :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ4N_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ4N_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_DQ4N :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ4N_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ4N_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ4N_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_DQ4N :: reserved2 [11:08] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ4N_reserved2_MASK 0x00000f00
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ4N_reserved2_SHIFT 8
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_DQ4N :: VDL_STEP [07:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ4N_VDL_STEP_MASK 0x000000ff
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ4N_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ4N_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_RD_DQ5P - Read channel DQ5-P VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_DQ5P :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ5P_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ5P_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ5P_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_DQ5P :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ5P_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ5P_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_DQ5P :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ5P_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ5P_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ5P_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_DQ5P :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ5P_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ5P_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_DQ5P :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ5P_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ5P_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ5P_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_DQ5P :: reserved2 [11:08] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ5P_reserved2_MASK 0x00000f00
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ5P_reserved2_SHIFT 8
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_DQ5P :: VDL_STEP [07:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ5P_VDL_STEP_MASK 0x000000ff
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ5P_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ5P_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_RD_DQ5N - Read channel DQ5-N VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_DQ5N :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ5N_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ5N_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ5N_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_DQ5N :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ5N_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ5N_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_DQ5N :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ5N_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ5N_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ5N_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_DQ5N :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ5N_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ5N_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_DQ5N :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ5N_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ5N_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ5N_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_DQ5N :: reserved2 [11:08] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ5N_reserved2_MASK 0x00000f00
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ5N_reserved2_SHIFT 8
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_DQ5N :: VDL_STEP [07:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ5N_VDL_STEP_MASK 0x000000ff
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ5N_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ5N_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_RD_DQ6P - Read channel DQ6-P VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_DQ6P :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ6P_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ6P_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ6P_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_DQ6P :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ6P_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ6P_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_DQ6P :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ6P_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ6P_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ6P_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_DQ6P :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ6P_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ6P_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_DQ6P :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ6P_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ6P_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ6P_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_DQ6P :: reserved2 [11:08] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ6P_reserved2_MASK 0x00000f00
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ6P_reserved2_SHIFT 8
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_DQ6P :: VDL_STEP [07:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ6P_VDL_STEP_MASK 0x000000ff
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ6P_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ6P_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_RD_DQ6N - Read channel DQ6-N VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_DQ6N :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ6N_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ6N_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ6N_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_DQ6N :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ6N_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ6N_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_DQ6N :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ6N_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ6N_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ6N_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_DQ6N :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ6N_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ6N_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_DQ6N :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ6N_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ6N_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ6N_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_DQ6N :: reserved2 [11:08] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ6N_reserved2_MASK 0x00000f00
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ6N_reserved2_SHIFT 8
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_DQ6N :: VDL_STEP [07:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ6N_VDL_STEP_MASK 0x000000ff
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ6N_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ6N_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_RD_DQ7P - Read channel DQ7-P VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_DQ7P :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ7P_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ7P_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ7P_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_DQ7P :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ7P_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ7P_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_DQ7P :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ7P_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ7P_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ7P_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_DQ7P :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ7P_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ7P_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_DQ7P :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ7P_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ7P_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ7P_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_DQ7P :: reserved2 [11:08] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ7P_reserved2_MASK 0x00000f00
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ7P_reserved2_SHIFT 8
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_DQ7P :: VDL_STEP [07:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ7P_VDL_STEP_MASK 0x000000ff
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ7P_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ7P_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_RD_DQ7N - Read channel DQ7-N VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_DQ7N :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ7N_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ7N_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ7N_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_DQ7N :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ7N_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ7N_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_DQ7N :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ7N_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ7N_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ7N_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_DQ7N :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ7N_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ7N_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_DQ7N :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ7N_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ7N_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ7N_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_DQ7N :: reserved2 [11:08] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ7N_reserved2_MASK 0x00000f00
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ7N_reserved2_SHIFT 8
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_DQ7N :: VDL_STEP [07:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ7N_VDL_STEP_MASK 0x000000ff
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ7N_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ7N_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_RD_DMP - Read channel DM-P VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_DMP :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DMP_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DMP_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DMP_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_DMP :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DMP_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DMP_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_DMP :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DMP_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DMP_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DMP_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_DMP :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DMP_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DMP_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_DMP :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DMP_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DMP_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DMP_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_DMP :: reserved2 [11:08] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DMP_reserved2_MASK 0x00000f00
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DMP_reserved2_SHIFT 8
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_DMP :: VDL_STEP [07:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DMP_VDL_STEP_MASK 0x000000ff
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DMP_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DMP_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_RD_DMN - Read channel DM-N VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_DMN :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DMN_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DMN_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DMN_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_DMN :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DMN_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DMN_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_DMN :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DMN_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DMN_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DMN_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_DMN :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DMN_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DMN_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_DMN :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DMN_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DMN_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DMN_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_DMN :: reserved2 [11:08] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DMN_reserved2_MASK 0x00000f00
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DMN_reserved2_SHIFT 8
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_DMN :: VDL_STEP [07:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DMN_VDL_STEP_MASK 0x000000ff
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DMN_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DMN_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_RD_EDCP - Read channel EDC-P VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_EDCP :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_EDCP_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_EDCP_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_EDCP_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_EDCP :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_EDCP_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_EDCP_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_EDCP :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_EDCP_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_EDCP_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_EDCP_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_EDCP :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_EDCP_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_EDCP_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_EDCP :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_EDCP_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_EDCP_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_EDCP_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_EDCP :: reserved2 [11:08] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_EDCP_reserved2_MASK 0x00000f00
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_EDCP_reserved2_SHIFT 8
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_EDCP :: VDL_STEP [07:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_EDCP_VDL_STEP_MASK 0x000000ff
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_EDCP_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_EDCP_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_RD_EDCN - Read channel EDC-N VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_EDCN :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_EDCN_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_EDCN_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_EDCN_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_EDCN :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_EDCN_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_EDCN_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_EDCN :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_EDCN_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_EDCN_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_EDCN_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_EDCN :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_EDCN_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_EDCN_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_EDCN :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_EDCN_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_EDCN_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_EDCN_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_EDCN :: reserved2 [11:08] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_EDCN_reserved2_MASK 0x00000f00
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_EDCN_reserved2_SHIFT 8
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_EDCN :: VDL_STEP [07:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_EDCN_VDL_STEP_MASK 0x000000ff
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_EDCN_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_EDCN_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_RD_EN_CS0 - Read channel CS_N[0] read enable VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_EN_CS0 :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_EN_CS0_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_EN_CS0_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_EN_CS0_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_EN_CS0 :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_EN_CS0_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_EN_CS0_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_EN_CS0 :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_EN_CS0_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_EN_CS0_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_EN_CS0_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_EN_CS0 :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_EN_CS0_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_EN_CS0_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_EN_CS0 :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_EN_CS0_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_EN_CS0_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_EN_CS0_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_EN_CS0 :: reserved2 [11:08] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_EN_CS0_reserved2_MASK 0x00000f00
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_EN_CS0_reserved2_SHIFT 8
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_EN_CS0 :: VDL_STEP [07:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_EN_CS0_VDL_STEP_MASK 0x000000ff
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_EN_CS0_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_EN_CS0_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_RD_EN_CS1 - Read channel CS_N[1] read enable VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_EN_CS1 :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_EN_CS1_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_EN_CS1_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_EN_CS1_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_EN_CS1 :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_EN_CS1_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_EN_CS1_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_EN_CS1 :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_EN_CS1_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_EN_CS1_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_EN_CS1_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_EN_CS1 :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_EN_CS1_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_EN_CS1_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_EN_CS1 :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_EN_CS1_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_EN_CS1_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_EN_CS1_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_EN_CS1 :: reserved2 [11:08] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_EN_CS1_reserved2_MASK 0x00000f00
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_EN_CS1_reserved2_SHIFT 8
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_EN_CS1 :: VDL_STEP [07:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_EN_CS1_VDL_STEP_MASK 0x000000ff
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_EN_CS1_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_EN_CS1_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CLK_CONTROL - DDR interface signal Write Leveling CLK VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CLK_CONTROL :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CLK_CONTROL_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CLK_CONTROL_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CLK_CONTROL_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CLK_CONTROL :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CLK_CONTROL_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CLK_CONTROL_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CLK_CONTROL :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CLK_CONTROL_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CLK_CONTROL_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CLK_CONTROL_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CLK_CONTROL :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CLK_CONTROL_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CLK_CONTROL_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CLK_CONTROL :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CLK_CONTROL_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CLK_CONTROL_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CLK_CONTROL_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CLK_CONTROL :: reserved2 [11:09] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CLK_CONTROL_reserved2_MASK 0x00000e00
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CLK_CONTROL_reserved2_SHIFT 9
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CLK_CONTROL :: VDL_STEP [08:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CLK_CONTROL_VDL_STEP_MASK 0x000001ff
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CLK_CONTROL_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CLK_CONTROL_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_LDE_CONTROL - DDR interface signal Write Leveling Capture Enable VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_LDE_CONTROL :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_LDE_CONTROL_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_LDE_CONTROL_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_LDE_CONTROL_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_LDE_CONTROL :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_LDE_CONTROL_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_LDE_CONTROL_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_LDE_CONTROL :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_LDE_CONTROL_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_LDE_CONTROL_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_LDE_CONTROL_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_LDE_CONTROL :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_LDE_CONTROL_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_LDE_CONTROL_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_LDE_CONTROL :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_LDE_CONTROL_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_LDE_CONTROL_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_LDE_CONTROL_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_LDE_CONTROL :: reserved2 [11:09] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_LDE_CONTROL_reserved2_MASK 0x00000e00
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_LDE_CONTROL_reserved2_SHIFT 9
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_LDE_CONTROL :: VDL_STEP [08:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_LDE_CONTROL_VDL_STEP_MASK 0x000001ff
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_LDE_CONTROL_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_LDE_CONTROL_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *RD_EN_DLY_CYC - Read enable bit-clock cycle delay control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_1_0 :: RD_EN_DLY_CYC :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_RD_EN_DLY_CYC_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_RD_EN_DLY_CYC_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_RD_EN_DLY_CYC_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: RD_EN_DLY_CYC :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_RD_EN_DLY_CYC_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_RD_EN_DLY_CYC_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: RD_EN_DLY_CYC :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_RD_EN_DLY_CYC_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_RD_EN_DLY_CYC_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_RD_EN_DLY_CYC_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: RD_EN_DLY_CYC :: reserved1 [15:08] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_RD_EN_DLY_CYC_reserved1_MASK 0x0000ff00
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_RD_EN_DLY_CYC_reserved1_SHIFT 8
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: RD_EN_DLY_CYC :: CS1_CYCLES [07:04] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_RD_EN_DLY_CYC_CS1_CYCLES_MASK 0x000000f0
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_RD_EN_DLY_CYC_CS1_CYCLES_SHIFT 4
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_RD_EN_DLY_CYC_CS1_CYCLES_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: RD_EN_DLY_CYC :: CS0_CYCLES [03:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_RD_EN_DLY_CYC_CS0_CYCLES_MASK 0x0000000f
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_RD_EN_DLY_CYC_CS0_CYCLES_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_RD_EN_DLY_CYC_CS0_CYCLES_DEFAULT 0x00000000
-
-/***************************************************************************
- *WR_CHAN_DLY_CYC - Write leveling bit-clock cycle delay control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_1_0 :: WR_CHAN_DLY_CYC :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_WR_CHAN_DLY_CYC_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_WR_CHAN_DLY_CYC_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_WR_CHAN_DLY_CYC_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: WR_CHAN_DLY_CYC :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_WR_CHAN_DLY_CYC_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_WR_CHAN_DLY_CYC_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: WR_CHAN_DLY_CYC :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_WR_CHAN_DLY_CYC_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_WR_CHAN_DLY_CYC_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_WR_CHAN_DLY_CYC_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: WR_CHAN_DLY_CYC :: reserved1 [15:03] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_WR_CHAN_DLY_CYC_reserved1_MASK 0x0000fff8
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_WR_CHAN_DLY_CYC_reserved1_SHIFT 3
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: WR_CHAN_DLY_CYC :: CYCLES [02:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_WR_CHAN_DLY_CYC_CYCLES_MASK 0x00000007
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_WR_CHAN_DLY_CYC_CYCLES_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_WR_CHAN_DLY_CYC_CYCLES_DEFAULT 0x00000000
-
-/***************************************************************************
- *READ_CONTROL - Read channel datapath control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_1_0 :: READ_CONTROL :: reserved0 [31:05] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_READ_CONTROL_reserved0_MASK 0xffffffe0
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_READ_CONTROL_reserved0_SHIFT 5
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: READ_CONTROL :: MODE [04:04] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_READ_CONTROL_MODE_MASK 0x00000010
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_READ_CONTROL_MODE_SHIFT 4
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_READ_CONTROL_MODE_DEFAULT 0x00000001
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: READ_CONTROL :: reserved1 [03:03] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_READ_CONTROL_reserved1_MASK 0x00000008
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_READ_CONTROL_reserved1_SHIFT 3
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: READ_CONTROL :: RD_DATA_DLY [02:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_READ_CONTROL_RD_DATA_DLY_MASK 0x00000007
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_READ_CONTROL_RD_DATA_DLY_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_READ_CONTROL_RD_DATA_DLY_DEFAULT 0x00000007
-
-/***************************************************************************
- *READ_FIFO_ADDR - Read fifo addresss pointer register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_1_0 :: READ_FIFO_ADDR :: reserved0 [31:03] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_READ_FIFO_ADDR_reserved0_MASK 0xfffffff8
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_READ_FIFO_ADDR_reserved0_SHIFT 3
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: READ_FIFO_ADDR :: ADDR [02:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_READ_FIFO_ADDR_ADDR_MASK 0x00000007
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_READ_FIFO_ADDR_ADDR_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_READ_FIFO_ADDR_ADDR_DEFAULT 0x00000000
-
-/***************************************************************************
- *READ_FIFO_DATA - Read fifo data register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_1_0 :: READ_FIFO_DATA :: DATA [31:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_READ_FIFO_DATA_DATA_MASK 0xffffffff
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_READ_FIFO_DATA_DATA_SHIFT 0
-
-/***************************************************************************
- *READ_FIFO_DM_DBI - Read fifo dm/dbi register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_1_0 :: READ_FIFO_DM_DBI :: reserved0 [31:04] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_READ_FIFO_DM_DBI_reserved0_MASK 0xfffffff0
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_READ_FIFO_DM_DBI_reserved0_SHIFT 4
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: READ_FIFO_DM_DBI :: DM_DBI [03:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_READ_FIFO_DM_DBI_DM_DBI_MASK 0x0000000f
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_READ_FIFO_DM_DBI_DM_DBI_SHIFT 0
-
-/***************************************************************************
- *READ_FIFO_STATUS - Read fifo status register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_1_0 :: READ_FIFO_STATUS :: reserved0 [31:02] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_READ_FIFO_STATUS_reserved0_MASK 0xfffffffc
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_READ_FIFO_STATUS_reserved0_SHIFT 2
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: READ_FIFO_STATUS :: OVERFLOW [01:01] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_READ_FIFO_STATUS_OVERFLOW_MASK 0x00000002
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_READ_FIFO_STATUS_OVERFLOW_SHIFT 1
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_READ_FIFO_STATUS_OVERFLOW_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: READ_FIFO_STATUS :: UNDERFLOW [00:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_READ_FIFO_STATUS_UNDERFLOW_MASK 0x00000001
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_READ_FIFO_STATUS_UNDERFLOW_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_READ_FIFO_STATUS_UNDERFLOW_DEFAULT 0x00000000
-
-/***************************************************************************
- *READ_FIFO_CLEAR - Read fifo status clear register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_1_0 :: READ_FIFO_CLEAR :: reserved0 [31:01] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_READ_FIFO_CLEAR_reserved0_MASK 0xfffffffe
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_READ_FIFO_CLEAR_reserved0_SHIFT 1
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: READ_FIFO_CLEAR :: CLEAR [00:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_READ_FIFO_CLEAR_CLEAR_MASK 0x00000001
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_READ_FIFO_CLEAR_CLEAR_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_READ_FIFO_CLEAR_CLEAR_DEFAULT 0x00000000
-
-/***************************************************************************
- *IDLE_PAD_CONTROL - Idle mode SSTL pad control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_1_0 :: IDLE_PAD_CONTROL :: IDLE [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_IDLE_PAD_CONTROL_IDLE_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_IDLE_PAD_CONTROL_IDLE_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_IDLE_PAD_CONTROL_IDLE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: IDLE_PAD_CONTROL :: reserved0 [30:20] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_IDLE_PAD_CONTROL_reserved0_MASK 0x7ff00000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_IDLE_PAD_CONTROL_reserved0_SHIFT 20
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: IDLE_PAD_CONTROL :: AUTO_DQ_RXENB_MODE [19:18] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_IDLE_PAD_CONTROL_AUTO_DQ_RXENB_MODE_MASK 0x000c0000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_IDLE_PAD_CONTROL_AUTO_DQ_RXENB_MODE_SHIFT 18
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_IDLE_PAD_CONTROL_AUTO_DQ_RXENB_MODE_DEFAULT 0x00000001
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: IDLE_PAD_CONTROL :: AUTO_DQ_IDDQ_MODE [17:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_IDLE_PAD_CONTROL_AUTO_DQ_IDDQ_MODE_MASK 0x00030000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_IDLE_PAD_CONTROL_AUTO_DQ_IDDQ_MODE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_IDLE_PAD_CONTROL_AUTO_DQ_IDDQ_MODE_DEFAULT 0x00000001
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: IDLE_PAD_CONTROL :: reserved_for_padding1 [15:15] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_IDLE_PAD_CONTROL_reserved_for_padding1_MASK 0x00008000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_IDLE_PAD_CONTROL_reserved_for_padding1_SHIFT 15
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: IDLE_PAD_CONTROL :: IO_IDLE_ENABLE [14:04] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_IDLE_PAD_CONTROL_IO_IDLE_ENABLE_MASK 0x00007ff0
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_IDLE_PAD_CONTROL_IO_IDLE_ENABLE_SHIFT 4
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_IDLE_PAD_CONTROL_IO_IDLE_ENABLE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: IDLE_PAD_CONTROL :: RXENB [03:03] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_IDLE_PAD_CONTROL_RXENB_MASK 0x00000008
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_IDLE_PAD_CONTROL_RXENB_SHIFT 3
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_IDLE_PAD_CONTROL_RXENB_DEFAULT 0x00000001
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: IDLE_PAD_CONTROL :: IDDQ [02:02] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_IDLE_PAD_CONTROL_IDDQ_MASK 0x00000004
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_IDLE_PAD_CONTROL_IDDQ_SHIFT 2
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_IDLE_PAD_CONTROL_IDDQ_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: IDLE_PAD_CONTROL :: DOUT_N [01:01] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_IDLE_PAD_CONTROL_DOUT_N_MASK 0x00000002
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_IDLE_PAD_CONTROL_DOUT_N_SHIFT 1
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: IDLE_PAD_CONTROL :: DOUT_P [00:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_IDLE_PAD_CONTROL_DOUT_P_MASK 0x00000001
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_IDLE_PAD_CONTROL_DOUT_P_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_IDLE_PAD_CONTROL_DOUT_P_DEFAULT 0x00000000
-
-/***************************************************************************
- *DRIVE_PAD_CTL - SSTL pad drive characteristics control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_1_0 :: DRIVE_PAD_CTL :: reserved0 [31:30] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_DRIVE_PAD_CTL_reserved0_MASK 0xc0000000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_DRIVE_PAD_CTL_reserved0_SHIFT 30
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: DRIVE_PAD_CTL :: BL_PD_IDLE_STRENGTH [29:25] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_DRIVE_PAD_CTL_BL_PD_IDLE_STRENGTH_MASK 0x3e000000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_DRIVE_PAD_CTL_BL_PD_IDLE_STRENGTH_SHIFT 25
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_DRIVE_PAD_CTL_BL_PD_IDLE_STRENGTH_DEFAULT 0x0000001f
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: DRIVE_PAD_CTL :: BL_ND_IDLE_STRENGTH [24:20] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_DRIVE_PAD_CTL_BL_ND_IDLE_STRENGTH_MASK 0x01f00000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_DRIVE_PAD_CTL_BL_ND_IDLE_STRENGTH_SHIFT 20
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_DRIVE_PAD_CTL_BL_ND_IDLE_STRENGTH_DEFAULT 0x0000001f
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: DRIVE_PAD_CTL :: BL_PD_TERM_STRENGTH [19:15] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_DRIVE_PAD_CTL_BL_PD_TERM_STRENGTH_MASK 0x000f8000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_DRIVE_PAD_CTL_BL_PD_TERM_STRENGTH_SHIFT 15
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_DRIVE_PAD_CTL_BL_PD_TERM_STRENGTH_DEFAULT 0x00000008
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: DRIVE_PAD_CTL :: BL_ND_TERM_STRENGTH [14:10] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_DRIVE_PAD_CTL_BL_ND_TERM_STRENGTH_MASK 0x00007c00
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_DRIVE_PAD_CTL_BL_ND_TERM_STRENGTH_SHIFT 10
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_DRIVE_PAD_CTL_BL_ND_TERM_STRENGTH_DEFAULT 0x00000008
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: DRIVE_PAD_CTL :: BL_PD_STRENGTH [09:05] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_DRIVE_PAD_CTL_BL_PD_STRENGTH_MASK 0x000003e0
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_DRIVE_PAD_CTL_BL_PD_STRENGTH_SHIFT 5
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_DRIVE_PAD_CTL_BL_PD_STRENGTH_DEFAULT 0x0000001f
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: DRIVE_PAD_CTL :: BL_ND_STRENGTH [04:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_DRIVE_PAD_CTL_BL_ND_STRENGTH_MASK 0x0000001f
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_DRIVE_PAD_CTL_BL_ND_STRENGTH_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_DRIVE_PAD_CTL_BL_ND_STRENGTH_DEFAULT 0x0000001f
-
-/***************************************************************************
- *RD_EN_DRIVE_PAD_CTL - SSTL read enable pad drive characteristics control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_1_0 :: RD_EN_DRIVE_PAD_CTL :: reserved0 [31:20] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_RD_EN_DRIVE_PAD_CTL_reserved0_MASK 0xfff00000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_RD_EN_DRIVE_PAD_CTL_reserved0_SHIFT 20
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: RD_EN_DRIVE_PAD_CTL :: EDC_RD_EN_PD_STRENGTH [19:15] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_RD_EN_DRIVE_PAD_CTL_EDC_RD_EN_PD_STRENGTH_MASK 0x000f8000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_RD_EN_DRIVE_PAD_CTL_EDC_RD_EN_PD_STRENGTH_SHIFT 15
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_RD_EN_DRIVE_PAD_CTL_EDC_RD_EN_PD_STRENGTH_DEFAULT 0x0000001f
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: RD_EN_DRIVE_PAD_CTL :: EDC_RD_EN_ND_STRENGTH [14:10] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_RD_EN_DRIVE_PAD_CTL_EDC_RD_EN_ND_STRENGTH_MASK 0x00007c00
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_RD_EN_DRIVE_PAD_CTL_EDC_RD_EN_ND_STRENGTH_SHIFT 10
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_RD_EN_DRIVE_PAD_CTL_EDC_RD_EN_ND_STRENGTH_DEFAULT 0x0000001f
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: RD_EN_DRIVE_PAD_CTL :: BL_RD_EN_PD_STRENGTH [09:05] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_RD_EN_DRIVE_PAD_CTL_BL_RD_EN_PD_STRENGTH_MASK 0x000003e0
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_RD_EN_DRIVE_PAD_CTL_BL_RD_EN_PD_STRENGTH_SHIFT 5
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_RD_EN_DRIVE_PAD_CTL_BL_RD_EN_PD_STRENGTH_DEFAULT 0x0000001f
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: RD_EN_DRIVE_PAD_CTL :: BL_RD_EN_ND_STRENGTH [04:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_RD_EN_DRIVE_PAD_CTL_BL_RD_EN_ND_STRENGTH_MASK 0x0000001f
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_RD_EN_DRIVE_PAD_CTL_BL_RD_EN_ND_STRENGTH_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_RD_EN_DRIVE_PAD_CTL_BL_RD_EN_ND_STRENGTH_DEFAULT 0x0000001f
-
-/***************************************************************************
- *STATIC_PAD_CTL - pad rx and tx characteristics control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_1_0 :: STATIC_PAD_CTL :: reserved0 [31:21] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_STATIC_PAD_CTL_reserved0_MASK 0xffe00000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_STATIC_PAD_CTL_reserved0_SHIFT 21
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: STATIC_PAD_CTL :: DQS_MODE [20:20] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_STATIC_PAD_CTL_DQS_MODE_MASK 0x00100000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_STATIC_PAD_CTL_DQS_MODE_SHIFT 20
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_STATIC_PAD_CTL_DQS_MODE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: STATIC_PAD_CTL :: reserved1 [19:18] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_STATIC_PAD_CTL_reserved1_MASK 0x000c0000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_STATIC_PAD_CTL_reserved1_SHIFT 18
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: STATIC_PAD_CTL :: EDC_MODE [17:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_STATIC_PAD_CTL_EDC_MODE_MASK 0x00030000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_STATIC_PAD_CTL_EDC_MODE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_STATIC_PAD_CTL_EDC_MODE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: STATIC_PAD_CTL :: reserved2 [15:15] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_STATIC_PAD_CTL_reserved2_MASK 0x00008000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_STATIC_PAD_CTL_reserved2_SHIFT 15
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: STATIC_PAD_CTL :: WDBI_ENABLE [14:14] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_STATIC_PAD_CTL_WDBI_ENABLE_MASK 0x00004000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_STATIC_PAD_CTL_WDBI_ENABLE_SHIFT 14
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_STATIC_PAD_CTL_WDBI_ENABLE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: STATIC_PAD_CTL :: RDBI_ENABLE [13:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_STATIC_PAD_CTL_RDBI_ENABLE_MASK 0x00002000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_STATIC_PAD_CTL_RDBI_ENABLE_SHIFT 13
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_STATIC_PAD_CTL_RDBI_ENABLE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: STATIC_PAD_CTL :: DM_MODE [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_STATIC_PAD_CTL_DM_MODE_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_STATIC_PAD_CTL_DM_MODE_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_STATIC_PAD_CTL_DM_MODE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: STATIC_PAD_CTL :: reserved3 [11:11] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_STATIC_PAD_CTL_reserved3_MASK 0x00000800
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_STATIC_PAD_CTL_reserved3_SHIFT 11
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: STATIC_PAD_CTL :: DQS_TX_PAUSE [10:10] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_STATIC_PAD_CTL_DQS_TX_PAUSE_MASK 0x00000400
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_STATIC_PAD_CTL_DQS_TX_PAUSE_SHIFT 10
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_STATIC_PAD_CTL_DQS_TX_PAUSE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: STATIC_PAD_CTL :: DQS_TX_DIS [09:09] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_STATIC_PAD_CTL_DQS_TX_DIS_MASK 0x00000200
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_STATIC_PAD_CTL_DQS_TX_DIS_SHIFT 9
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_STATIC_PAD_CTL_DQS_TX_DIS_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: STATIC_PAD_CTL :: reserved4 [08:08] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_STATIC_PAD_CTL_reserved4_MASK 0x00000100
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_STATIC_PAD_CTL_reserved4_SHIFT 8
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: STATIC_PAD_CTL :: TX_MODE [07:04] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_STATIC_PAD_CTL_TX_MODE_MASK 0x000000f0
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_STATIC_PAD_CTL_TX_MODE_SHIFT 4
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_STATIC_PAD_CTL_TX_MODE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: STATIC_PAD_CTL :: reserved5 [03:03] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_STATIC_PAD_CTL_reserved5_MASK 0x00000008
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_STATIC_PAD_CTL_reserved5_SHIFT 3
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: STATIC_PAD_CTL :: RX_MODE [02:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_STATIC_PAD_CTL_RX_MODE_MASK 0x00000007
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_STATIC_PAD_CTL_RX_MODE_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_STATIC_PAD_CTL_RX_MODE_DEFAULT 0x00000000
-
-/***************************************************************************
- *WR_PREAMBLE_MODE - Write cycle preamble control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_1_0 :: WR_PREAMBLE_MODE :: reserved0 [31:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_WR_PREAMBLE_MODE_reserved0_MASK 0xffff0000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_WR_PREAMBLE_MODE_reserved0_SHIFT 16
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: WR_PREAMBLE_MODE :: DQ_POSTAM_BITS [15:14] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_WR_PREAMBLE_MODE_DQ_POSTAM_BITS_MASK 0x0000c000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_WR_PREAMBLE_MODE_DQ_POSTAM_BITS_SHIFT 14
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_WR_PREAMBLE_MODE_DQ_POSTAM_BITS_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: WR_PREAMBLE_MODE :: DQ_PREAM_BITS [13:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_WR_PREAMBLE_MODE_DQ_PREAM_BITS_MASK 0x00003000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_WR_PREAMBLE_MODE_DQ_PREAM_BITS_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_WR_PREAMBLE_MODE_DQ_PREAM_BITS_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: WR_PREAMBLE_MODE :: DQS [11:08] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_WR_PREAMBLE_MODE_DQS_MASK 0x00000f00
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_WR_PREAMBLE_MODE_DQS_SHIFT 8
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_WR_PREAMBLE_MODE_DQS_DEFAULT 0x0000000e
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: WR_PREAMBLE_MODE :: reserved1 [07:05] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_WR_PREAMBLE_MODE_reserved1_MASK 0x000000e0
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_WR_PREAMBLE_MODE_reserved1_SHIFT 5
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: WR_PREAMBLE_MODE :: DQS_POSTAM_BITS [04:03] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_WR_PREAMBLE_MODE_DQS_POSTAM_BITS_MASK 0x00000018
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_WR_PREAMBLE_MODE_DQS_POSTAM_BITS_SHIFT 3
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_WR_PREAMBLE_MODE_DQS_POSTAM_BITS_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: WR_PREAMBLE_MODE :: DQS_PREAM_BITS [02:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_WR_PREAMBLE_MODE_DQS_PREAM_BITS_MASK 0x00000007
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_WR_PREAMBLE_MODE_DQS_PREAM_BITS_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_WR_PREAMBLE_MODE_DQS_PREAM_BITS_DEFAULT 0x00000002
-
-/***************************************************************************
- *ODT_CONTROL - Read channel ODT control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_1_0 :: ODT_CONTROL :: reserved_for_padding0 [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_ODT_CONTROL_reserved_for_padding0_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_ODT_CONTROL_reserved_for_padding0_SHIFT 31
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: ODT_CONTROL :: reserved1 [30:10] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_ODT_CONTROL_reserved1_MASK 0x7ffffc00
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_ODT_CONTROL_reserved1_SHIFT 10
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: ODT_CONTROL :: ODT_ENABLE [09:09] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_ODT_CONTROL_ODT_ENABLE_MASK 0x00000200
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_ODT_CONTROL_ODT_ENABLE_SHIFT 9
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_ODT_CONTROL_ODT_ENABLE_DEFAULT 0x00000001
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: ODT_CONTROL :: ODT_DELAY [08:06] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_ODT_CONTROL_ODT_DELAY_MASK 0x000001c0
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_ODT_CONTROL_ODT_DELAY_SHIFT 6
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_ODT_CONTROL_ODT_DELAY_DEFAULT 0x00000001
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: ODT_CONTROL :: ODT_POST_LENGTH [05:03] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_ODT_CONTROL_ODT_POST_LENGTH_MASK 0x00000038
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_ODT_CONTROL_ODT_POST_LENGTH_SHIFT 3
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_ODT_CONTROL_ODT_POST_LENGTH_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: ODT_CONTROL :: ODT_PRE_LENGTH [02:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_ODT_CONTROL_ODT_PRE_LENGTH_MASK 0x00000007
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_ODT_CONTROL_ODT_PRE_LENGTH_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_ODT_CONTROL_ODT_PRE_LENGTH_DEFAULT 0x00000003
-
-/***************************************************************************
- *EDC_DPD_CONTROL - GDDR5M EDC digital phase detector control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_1_0 :: EDC_DPD_CONTROL :: reserved0 [31:06] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_DPD_CONTROL_reserved0_MASK 0xffffffc0
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_DPD_CONTROL_reserved0_SHIFT 6
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: EDC_DPD_CONTROL :: DQS_PHASE_OVERRIDE_VALUE [05:05] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_DPD_CONTROL_DQS_PHASE_OVERRIDE_VALUE_MASK 0x00000020
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_DPD_CONTROL_DQS_PHASE_OVERRIDE_VALUE_SHIFT 5
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_DPD_CONTROL_DQS_PHASE_OVERRIDE_VALUE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: EDC_DPD_CONTROL :: DQS_PHASE_OVERRIDE_ENABLE [04:04] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_DPD_CONTROL_DQS_PHASE_OVERRIDE_ENABLE_MASK 0x00000010
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_DPD_CONTROL_DQS_PHASE_OVERRIDE_ENABLE_SHIFT 4
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_DPD_CONTROL_DQS_PHASE_OVERRIDE_ENABLE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: EDC_DPD_CONTROL :: SET_ADJ_EN [03:03] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_DPD_CONTROL_SET_ADJ_EN_MASK 0x00000008
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_DPD_CONTROL_SET_ADJ_EN_SHIFT 3
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_DPD_CONTROL_SET_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: EDC_DPD_CONTROL :: UPDATE [02:02] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_DPD_CONTROL_UPDATE_MASK 0x00000004
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_DPD_CONTROL_UPDATE_SHIFT 2
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_DPD_CONTROL_UPDATE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: EDC_DPD_CONTROL :: MONITOR [01:01] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_DPD_CONTROL_MONITOR_MASK 0x00000002
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_DPD_CONTROL_MONITOR_SHIFT 1
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_DPD_CONTROL_MONITOR_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: EDC_DPD_CONTROL :: INIT [00:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_DPD_CONTROL_INIT_MASK 0x00000001
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_DPD_CONTROL_INIT_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_DPD_CONTROL_INIT_DEFAULT 0x00000000
-
-/***************************************************************************
- *EDC_DPD_STATUS - GDDR5M EDC digital phase detector status register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_1_0 :: EDC_DPD_STATUS :: reserved0 [31:25] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_DPD_STATUS_reserved0_MASK 0xfe000000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_DPD_STATUS_reserved0_SHIFT 25
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: EDC_DPD_STATUS :: CURRENT_DQS_PHASE [24:24] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_DPD_STATUS_CURRENT_DQS_PHASE_MASK 0x01000000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_DPD_STATUS_CURRENT_DQS_PHASE_SHIFT 24
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_DPD_STATUS_CURRENT_DQS_PHASE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: EDC_DPD_STATUS :: CURRENT_VDL_SETTING [23:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_DPD_STATUS_CURRENT_VDL_SETTING_MASK 0x00ff0000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_DPD_STATUS_CURRENT_VDL_SETTING_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_DPD_STATUS_CURRENT_VDL_SETTING_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: EDC_DPD_STATUS :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_DPD_STATUS_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_DPD_STATUS_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: EDC_DPD_STATUS :: INIT_DQS_PHASE [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_DPD_STATUS_INIT_DQS_PHASE_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_DPD_STATUS_INIT_DQS_PHASE_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_DPD_STATUS_INIT_DQS_PHASE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: EDC_DPD_STATUS :: INIT_VDL_SETTING [11:04] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_DPD_STATUS_INIT_VDL_SETTING_MASK 0x00000ff0
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_DPD_STATUS_INIT_VDL_SETTING_SHIFT 4
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_DPD_STATUS_INIT_VDL_SETTING_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: EDC_DPD_STATUS :: EDGE_ERROR [03:03] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_DPD_STATUS_EDGE_ERROR_MASK 0x00000008
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_DPD_STATUS_EDGE_ERROR_SHIFT 3
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_DPD_STATUS_EDGE_ERROR_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: EDC_DPD_STATUS :: MONITOR_BUSY [02:02] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_DPD_STATUS_MONITOR_BUSY_MASK 0x00000004
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_DPD_STATUS_MONITOR_BUSY_SHIFT 2
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_DPD_STATUS_MONITOR_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: EDC_DPD_STATUS :: INIT_BUSY [01:01] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_DPD_STATUS_INIT_BUSY_MASK 0x00000002
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_DPD_STATUS_INIT_BUSY_SHIFT 1
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_DPD_STATUS_INIT_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: EDC_DPD_STATUS :: INIT_DONE [00:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_DPD_STATUS_INIT_DONE_MASK 0x00000001
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_DPD_STATUS_INIT_DONE_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_DPD_STATUS_INIT_DONE_DEFAULT 0x00000000
-
-/***************************************************************************
- *EDC_DPD_OUT_CONTROL - GDDR5M EDC digital phase detector output signal control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_1_0 :: EDC_DPD_OUT_CONTROL :: reserved0 [31:20] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_DPD_OUT_CONTROL_reserved0_MASK 0xfff00000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_DPD_OUT_CONTROL_reserved0_SHIFT 20
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: EDC_DPD_OUT_CONTROL :: LOWER_LIMIT [19:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_DPD_OUT_CONTROL_LOWER_LIMIT_MASK 0x000ff000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_DPD_OUT_CONTROL_LOWER_LIMIT_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_DPD_OUT_CONTROL_LOWER_LIMIT_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: EDC_DPD_OUT_CONTROL :: UPPER_LIMIT [11:04] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_DPD_OUT_CONTROL_UPPER_LIMIT_MASK 0x00000ff0
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_DPD_OUT_CONTROL_UPPER_LIMIT_SHIFT 4
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_DPD_OUT_CONTROL_UPPER_LIMIT_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: EDC_DPD_OUT_CONTROL :: reserved1 [03:01] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_DPD_OUT_CONTROL_reserved1_MASK 0x0000000e
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_DPD_OUT_CONTROL_reserved1_SHIFT 1
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: EDC_DPD_OUT_CONTROL :: ENABLE [00:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_DPD_OUT_CONTROL_ENABLE_MASK 0x00000001
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_DPD_OUT_CONTROL_ENABLE_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_DPD_OUT_CONTROL_ENABLE_DEFAULT 0x00000000
-
-/***************************************************************************
- *EDC_DPD_OUT_STATUS - GDDR5M EDC digital phase detector output signal status register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_1_0 :: EDC_DPD_OUT_STATUS :: reserved0 [31:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_DPD_OUT_STATUS_reserved0_MASK 0xfffff000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_DPD_OUT_STATUS_reserved0_SHIFT 12
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: EDC_DPD_OUT_STATUS :: VDL_SETTING [11:04] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_DPD_OUT_STATUS_VDL_SETTING_MASK 0x00000ff0
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_DPD_OUT_STATUS_VDL_SETTING_SHIFT 4
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_DPD_OUT_STATUS_VDL_SETTING_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: EDC_DPD_OUT_STATUS :: reserved1 [03:01] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_DPD_OUT_STATUS_reserved1_MASK 0x0000000e
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_DPD_OUT_STATUS_reserved1_SHIFT 1
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: EDC_DPD_OUT_STATUS :: VALID [00:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_DPD_OUT_STATUS_VALID_MASK 0x00000001
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_DPD_OUT_STATUS_VALID_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_DPD_OUT_STATUS_VALID_DEFAULT 0x00000000
-
-/***************************************************************************
- *EDC_DPD_OUT_STATUS_CLEAR - GDDR5M EDC digital phase detector output signal status clear register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_1_0 :: EDC_DPD_OUT_STATUS_CLEAR :: reserved0 [31:01] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_DPD_OUT_STATUS_CLEAR_reserved0_MASK 0xfffffffe
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_DPD_OUT_STATUS_CLEAR_reserved0_SHIFT 1
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: EDC_DPD_OUT_STATUS_CLEAR :: CLEAR [00:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_DPD_OUT_STATUS_CLEAR_CLEAR_MASK 0x00000001
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_DPD_OUT_STATUS_CLEAR_CLEAR_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_DPD_OUT_STATUS_CLEAR_CLEAR_DEFAULT 0x00000000
-
-/***************************************************************************
- *EDC_CRC_CONTROL - GDDR5M EDC signal path CRC control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_1_0 :: EDC_CRC_CONTROL :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_CRC_CONTROL_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_CRC_CONTROL_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_CRC_CONTROL_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: EDC_CRC_CONTROL :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_CRC_CONTROL_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_CRC_CONTROL_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: EDC_CRC_CONTROL :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_CRC_CONTROL_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_CRC_CONTROL_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_CRC_CONTROL_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: EDC_CRC_CONTROL :: reserved1 [15:11] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_CRC_CONTROL_reserved1_MASK 0x0000f800
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_CRC_CONTROL_reserved1_SHIFT 11
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: EDC_CRC_CONTROL :: CRCWL [10:08] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_CRC_CONTROL_CRCWL_MASK 0x00000700
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_CRC_CONTROL_CRCWL_SHIFT 8
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_CRC_CONTROL_CRCWL_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: EDC_CRC_CONTROL :: reserved2 [07:06] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_CRC_CONTROL_reserved2_MASK 0x000000c0
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_CRC_CONTROL_reserved2_SHIFT 6
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: EDC_CRC_CONTROL :: CRCRL [05:04] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_CRC_CONTROL_CRCRL_MASK 0x00000030
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_CRC_CONTROL_CRCRL_SHIFT 4
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_CRC_CONTROL_CRCRL_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: EDC_CRC_CONTROL :: reserved3 [03:03] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_CRC_CONTROL_reserved3_MASK 0x00000008
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_CRC_CONTROL_reserved3_SHIFT 3
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: EDC_CRC_CONTROL :: COUNT_MODE [02:02] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_CRC_CONTROL_COUNT_MODE_MASK 0x00000004
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_CRC_CONTROL_COUNT_MODE_SHIFT 2
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_CRC_CONTROL_COUNT_MODE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: EDC_CRC_CONTROL :: ENABLE_WR [01:01] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_CRC_CONTROL_ENABLE_WR_MASK 0x00000002
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_CRC_CONTROL_ENABLE_WR_SHIFT 1
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_CRC_CONTROL_ENABLE_WR_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: EDC_CRC_CONTROL :: ENABLE_RD [00:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_CRC_CONTROL_ENABLE_RD_MASK 0x00000001
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_CRC_CONTROL_ENABLE_RD_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_CRC_CONTROL_ENABLE_RD_DEFAULT 0x00000000
-
-/***************************************************************************
- *EDC_CRC_STATUS - GDDR5M EDC signal path CRC status register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_1_0 :: EDC_CRC_STATUS :: reserved0 [31:04] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_CRC_STATUS_reserved0_MASK 0xfffffff0
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_CRC_STATUS_reserved0_SHIFT 4
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: EDC_CRC_STATUS :: WR_FAIL [03:03] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_CRC_STATUS_WR_FAIL_MASK 0x00000008
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_CRC_STATUS_WR_FAIL_SHIFT 3
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_CRC_STATUS_WR_FAIL_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: EDC_CRC_STATUS :: WR_PASS [02:02] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_CRC_STATUS_WR_PASS_MASK 0x00000004
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_CRC_STATUS_WR_PASS_SHIFT 2
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_CRC_STATUS_WR_PASS_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: EDC_CRC_STATUS :: RD_FAIL [01:01] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_CRC_STATUS_RD_FAIL_MASK 0x00000002
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_CRC_STATUS_RD_FAIL_SHIFT 1
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_CRC_STATUS_RD_FAIL_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: EDC_CRC_STATUS :: RD_PASS [00:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_CRC_STATUS_RD_PASS_MASK 0x00000001
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_CRC_STATUS_RD_PASS_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_CRC_STATUS_RD_PASS_DEFAULT 0x00000000
-
-/***************************************************************************
- *EDC_CRC_COUNT - GDDR5M EDC signal path CRC counter register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_1_0 :: EDC_CRC_COUNT :: reserved0 [31:28] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_CRC_COUNT_reserved0_MASK 0xf0000000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_CRC_COUNT_reserved0_SHIFT 28
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: EDC_CRC_COUNT :: WR_COUNT [27:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_CRC_COUNT_WR_COUNT_MASK 0x0fff0000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_CRC_COUNT_WR_COUNT_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_CRC_COUNT_WR_COUNT_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: EDC_CRC_COUNT :: reserved1 [15:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_CRC_COUNT_reserved1_MASK 0x0000f000
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_CRC_COUNT_reserved1_SHIFT 12
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: EDC_CRC_COUNT :: RD_COUNT [11:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_CRC_COUNT_RD_COUNT_MASK 0x00000fff
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_CRC_COUNT_RD_COUNT_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_CRC_COUNT_RD_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *EDC_CRC_STATUS_CLEAR - GDDR5M EDC signal path CRC counter register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_1_0 :: EDC_CRC_STATUS_CLEAR :: reserved0 [31:01] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_CRC_STATUS_CLEAR_reserved0_MASK 0xfffffffe
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_CRC_STATUS_CLEAR_reserved0_SHIFT 1
-
-/* DDR34_PHY_BYTE_LANE_1_0 :: EDC_CRC_STATUS_CLEAR :: CLEAR [00:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_CRC_STATUS_CLEAR_CLEAR_MASK 0x00000001
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_CRC_STATUS_CLEAR_CLEAR_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_CRC_STATUS_CLEAR_CLEAR_DEFAULT 0x00000000
-
-/***************************************************************************
- *BL_SPARE_REG - Byte-Lane Spare register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_1_0 :: BL_SPARE_REG :: reserved_for_eco0 [31:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_BL_SPARE_REG_reserved_for_eco0_MASK 0xffffffff
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_BL_SPARE_REG_reserved_for_eco0_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_1_0_BL_SPARE_REG_reserved_for_eco0_DEFAULT 0x00000000
-
-#endif /* #ifndef BCHP_DDR34_PHY_BYTE_LANE_1_0_H__ */
-
-/* End of File */
diff --git a/include/linux/brcmstb/7439a0/bchp_ddr34_phy_byte_lane_2_0.h b/include/linux/brcmstb/7439a0/bchp_ddr34_phy_byte_lane_2_0.h
deleted file mode 100644
index 257f573..0000000
--- a/include/linux/brcmstb/7439a0/bchp_ddr34_phy_byte_lane_2_0.h
+++ /dev/null
@@ -1,2099 +0,0 @@
-/***************************************************************************
- * Copyright (c) 1999-2013, Broadcom Corporation
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
- *
- * Module Description:
- * DO NOT EDIT THIS FILE DIRECTLY
- *
- * This module was generated magically with RDB from a source description
- * file. You must edit the source file for changes to be made to this file.
- *
- *
- * Date: Generated on Tue Apr 16 03:26:52 2013
- * MD5 Checksum d41d8cd98f00b204e9800998ecf8427e
- *
- * Compiled with: RDB Utility combo_header.pl
- * RDB Parser 3.0
- * unknown unknown
- * Perl Interpreter 5.008008
- * Operating System linux
- *
- * Revision History:
- *
- * $brcm_Log: $
- *
- ***************************************************************************/
-
-#ifndef BCHP_DDR34_PHY_BYTE_LANE_2_0_H__
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_H__
-
-/***************************************************************************
- *DDR34_PHY_BYTE_LANE_2_0 - 0 DDR34 DDR34 Byte Lane #2 control registers
- ***************************************************************************/
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQS_P 0x00906800 /* Write channel DQS-P VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQS_N 0x00906804 /* Write channel DQS-N VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ0 0x00906808 /* Write channel DQ0 VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ1 0x0090680c /* Write channel DQ1 VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ2 0x00906810 /* Write channel DQ2 VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ3 0x00906814 /* Write channel DQ3 VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ4 0x00906818 /* Write channel DQ4 VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ5 0x0090681c /* Write channel DQ5 VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ6 0x00906820 /* Write channel DQ6 VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ7 0x00906824 /* Write channel DQ7 VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DM 0x00906828 /* Write channel DM VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_EDC 0x0090682c /* Write channel EDC VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQSP 0x00906830 /* Read channel DQSP VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQSN 0x00906834 /* Read channel DQSP VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ0P 0x00906838 /* Read channel DQ0-P VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ0N 0x0090683c /* Read channel DQ0-N VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ1P 0x00906840 /* Read channel DQ1-P VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ1N 0x00906844 /* Read channel DQ1-N VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ2P 0x00906848 /* Read channel DQ2-P VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ2N 0x0090684c /* Read channel DQ2-N VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ3P 0x00906850 /* Read channel DQ3-P VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ3N 0x00906854 /* Read channel DQ3-N VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ4P 0x00906858 /* Read channel DQ4-P VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ4N 0x0090685c /* Read channel DQ4-N VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ5P 0x00906860 /* Read channel DQ5-P VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ5N 0x00906864 /* Read channel DQ5-N VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ6P 0x00906868 /* Read channel DQ6-P VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ6N 0x0090686c /* Read channel DQ6-N VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ7P 0x00906870 /* Read channel DQ7-P VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ7N 0x00906874 /* Read channel DQ7-N VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DMP 0x00906878 /* Read channel DM-P VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DMN 0x0090687c /* Read channel DM-N VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_EDCP 0x00906880 /* Read channel EDC-P VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_EDCN 0x00906884 /* Read channel EDC-N VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_EN_CS0 0x00906888 /* Read channel CS_N[0] read enable VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_EN_CS1 0x0090688c /* Read channel CS_N[1] read enable VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CLK_CONTROL 0x00906890 /* DDR interface signal Write Leveling CLK VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_LDE_CONTROL 0x00906894 /* DDR interface signal Write Leveling Capture Enable VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_RD_EN_DLY_CYC 0x009068a0 /* Read enable bit-clock cycle delay control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_WR_CHAN_DLY_CYC 0x009068a4 /* Write leveling bit-clock cycle delay control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_READ_CONTROL 0x009068b0 /* Read channel datapath control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_READ_FIFO_ADDR 0x009068b4 /* Read fifo addresss pointer register */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_READ_FIFO_DATA 0x009068b8 /* Read fifo data register */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_READ_FIFO_DM_DBI 0x009068bc /* Read fifo dm/dbi register */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_READ_FIFO_STATUS 0x009068c0 /* Read fifo status register */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_READ_FIFO_CLEAR 0x009068c4 /* Read fifo status clear register */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_IDLE_PAD_CONTROL 0x009068c8 /* Idle mode SSTL pad control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_DRIVE_PAD_CTL 0x009068cc /* SSTL pad drive characteristics control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_RD_EN_DRIVE_PAD_CTL 0x009068d0 /* SSTL read enable pad drive characteristics control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_STATIC_PAD_CTL 0x009068d4 /* pad rx and tx characteristics control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_WR_PREAMBLE_MODE 0x009068d8 /* Write cycle preamble control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_ODT_CONTROL 0x009068e0 /* Read channel ODT control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_DPD_CONTROL 0x009068f0 /* GDDR5M EDC digital phase detector control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_DPD_STATUS 0x009068f4 /* GDDR5M EDC digital phase detector status register */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_DPD_OUT_CONTROL 0x009068f8 /* GDDR5M EDC digital phase detector output signal control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_DPD_OUT_STATUS 0x009068fc /* GDDR5M EDC digital phase detector output signal status register */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_DPD_OUT_STATUS_CLEAR 0x00906900 /* GDDR5M EDC digital phase detector output signal status clear register */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_CRC_CONTROL 0x00906904 /* GDDR5M EDC signal path CRC control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_CRC_STATUS 0x00906908 /* GDDR5M EDC signal path CRC status register */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_CRC_COUNT 0x0090690c /* GDDR5M EDC signal path CRC counter register */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_CRC_STATUS_CLEAR 0x00906910 /* GDDR5M EDC signal path CRC counter register */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_BL_SPARE_REG 0x00906914 /* Byte-Lane Spare register */
-
-/***************************************************************************
- *VDL_CONTROL_WR_DQS_P - Write channel DQS-P VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_WR_DQS_P :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQS_P_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQS_P_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQS_P_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_WR_DQS_P :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQS_P_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQS_P_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_WR_DQS_P :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQS_P_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQS_P_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQS_P_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_WR_DQS_P :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQS_P_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQS_P_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_WR_DQS_P :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQS_P_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQS_P_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQS_P_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_WR_DQS_P :: reserved2 [11:09] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQS_P_reserved2_MASK 0x00000e00
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQS_P_reserved2_SHIFT 9
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_WR_DQS_P :: VDL_STEP [08:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQS_P_VDL_STEP_MASK 0x000001ff
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQS_P_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQS_P_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_WR_DQS_N - Write channel DQS-N VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_WR_DQS_N :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQS_N_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQS_N_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQS_N_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_WR_DQS_N :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQS_N_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQS_N_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_WR_DQS_N :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQS_N_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQS_N_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQS_N_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_WR_DQS_N :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQS_N_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQS_N_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_WR_DQS_N :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQS_N_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQS_N_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQS_N_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_WR_DQS_N :: reserved2 [11:09] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQS_N_reserved2_MASK 0x00000e00
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQS_N_reserved2_SHIFT 9
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_WR_DQS_N :: VDL_STEP [08:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQS_N_VDL_STEP_MASK 0x000001ff
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQS_N_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQS_N_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_WR_DQ0 - Write channel DQ0 VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_WR_DQ0 :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ0_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ0_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ0_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_WR_DQ0 :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ0_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ0_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_WR_DQ0 :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ0_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ0_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ0_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_WR_DQ0 :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ0_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ0_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_WR_DQ0 :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ0_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ0_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ0_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_WR_DQ0 :: reserved2 [11:09] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ0_reserved2_MASK 0x00000e00
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ0_reserved2_SHIFT 9
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_WR_DQ0 :: VDL_STEP [08:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ0_VDL_STEP_MASK 0x000001ff
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ0_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ0_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_WR_DQ1 - Write channel DQ1 VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_WR_DQ1 :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ1_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ1_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ1_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_WR_DQ1 :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ1_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ1_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_WR_DQ1 :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ1_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ1_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ1_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_WR_DQ1 :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ1_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ1_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_WR_DQ1 :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ1_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ1_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ1_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_WR_DQ1 :: reserved2 [11:09] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ1_reserved2_MASK 0x00000e00
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ1_reserved2_SHIFT 9
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_WR_DQ1 :: VDL_STEP [08:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ1_VDL_STEP_MASK 0x000001ff
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ1_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ1_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_WR_DQ2 - Write channel DQ2 VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_WR_DQ2 :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ2_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ2_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ2_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_WR_DQ2 :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ2_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ2_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_WR_DQ2 :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ2_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ2_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ2_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_WR_DQ2 :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ2_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ2_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_WR_DQ2 :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ2_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ2_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ2_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_WR_DQ2 :: reserved2 [11:09] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ2_reserved2_MASK 0x00000e00
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ2_reserved2_SHIFT 9
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_WR_DQ2 :: VDL_STEP [08:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ2_VDL_STEP_MASK 0x000001ff
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ2_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ2_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_WR_DQ3 - Write channel DQ3 VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_WR_DQ3 :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ3_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ3_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ3_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_WR_DQ3 :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ3_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ3_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_WR_DQ3 :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ3_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ3_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ3_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_WR_DQ3 :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ3_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ3_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_WR_DQ3 :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ3_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ3_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ3_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_WR_DQ3 :: reserved2 [11:09] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ3_reserved2_MASK 0x00000e00
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ3_reserved2_SHIFT 9
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_WR_DQ3 :: VDL_STEP [08:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ3_VDL_STEP_MASK 0x000001ff
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ3_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ3_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_WR_DQ4 - Write channel DQ4 VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_WR_DQ4 :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ4_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ4_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ4_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_WR_DQ4 :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ4_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ4_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_WR_DQ4 :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ4_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ4_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ4_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_WR_DQ4 :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ4_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ4_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_WR_DQ4 :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ4_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ4_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ4_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_WR_DQ4 :: reserved2 [11:09] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ4_reserved2_MASK 0x00000e00
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ4_reserved2_SHIFT 9
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_WR_DQ4 :: VDL_STEP [08:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ4_VDL_STEP_MASK 0x000001ff
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ4_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ4_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_WR_DQ5 - Write channel DQ5 VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_WR_DQ5 :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ5_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ5_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ5_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_WR_DQ5 :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ5_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ5_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_WR_DQ5 :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ5_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ5_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ5_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_WR_DQ5 :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ5_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ5_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_WR_DQ5 :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ5_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ5_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ5_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_WR_DQ5 :: reserved2 [11:09] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ5_reserved2_MASK 0x00000e00
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ5_reserved2_SHIFT 9
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_WR_DQ5 :: VDL_STEP [08:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ5_VDL_STEP_MASK 0x000001ff
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ5_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ5_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_WR_DQ6 - Write channel DQ6 VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_WR_DQ6 :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ6_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ6_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ6_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_WR_DQ6 :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ6_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ6_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_WR_DQ6 :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ6_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ6_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ6_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_WR_DQ6 :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ6_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ6_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_WR_DQ6 :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ6_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ6_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ6_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_WR_DQ6 :: reserved2 [11:09] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ6_reserved2_MASK 0x00000e00
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ6_reserved2_SHIFT 9
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_WR_DQ6 :: VDL_STEP [08:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ6_VDL_STEP_MASK 0x000001ff
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ6_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ6_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_WR_DQ7 - Write channel DQ7 VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_WR_DQ7 :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ7_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ7_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ7_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_WR_DQ7 :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ7_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ7_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_WR_DQ7 :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ7_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ7_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ7_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_WR_DQ7 :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ7_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ7_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_WR_DQ7 :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ7_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ7_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ7_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_WR_DQ7 :: reserved2 [11:09] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ7_reserved2_MASK 0x00000e00
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ7_reserved2_SHIFT 9
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_WR_DQ7 :: VDL_STEP [08:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ7_VDL_STEP_MASK 0x000001ff
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ7_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ7_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_WR_DM - Write channel DM VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_WR_DM :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DM_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DM_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DM_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_WR_DM :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DM_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DM_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_WR_DM :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DM_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DM_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DM_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_WR_DM :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DM_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DM_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_WR_DM :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DM_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DM_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DM_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_WR_DM :: reserved2 [11:09] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DM_reserved2_MASK 0x00000e00
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DM_reserved2_SHIFT 9
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_WR_DM :: VDL_STEP [08:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DM_VDL_STEP_MASK 0x000001ff
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DM_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DM_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_WR_EDC - Write channel EDC VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_WR_EDC :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_EDC_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_EDC_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_EDC_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_WR_EDC :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_EDC_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_EDC_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_WR_EDC :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_EDC_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_EDC_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_EDC_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_WR_EDC :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_EDC_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_EDC_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_WR_EDC :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_EDC_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_EDC_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_EDC_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_WR_EDC :: reserved2 [11:09] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_EDC_reserved2_MASK 0x00000e00
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_EDC_reserved2_SHIFT 9
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_WR_EDC :: VDL_STEP [08:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_EDC_VDL_STEP_MASK 0x000001ff
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_EDC_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_EDC_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_RD_DQSP - Read channel DQSP VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQSP :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQSP_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQSP_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQSP_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQSP :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQSP_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQSP_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQSP :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQSP_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQSP_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQSP_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQSP :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQSP_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQSP_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQSP :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQSP_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQSP_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQSP_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQSP :: reserved2 [11:08] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQSP_reserved2_MASK 0x00000f00
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQSP_reserved2_SHIFT 8
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQSP :: VDL_STEP [07:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQSP_VDL_STEP_MASK 0x000000ff
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQSP_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQSP_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_RD_DQSN - Read channel DQSP VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQSN :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQSN_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQSN_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQSN_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQSN :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQSN_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQSN_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQSN :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQSN_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQSN_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQSN_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQSN :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQSN_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQSN_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQSN :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQSN_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQSN_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQSN_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQSN :: reserved2 [11:08] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQSN_reserved2_MASK 0x00000f00
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQSN_reserved2_SHIFT 8
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQSN :: VDL_STEP [07:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQSN_VDL_STEP_MASK 0x000000ff
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQSN_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQSN_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_RD_DQ0P - Read channel DQ0-P VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQ0P :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ0P_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ0P_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ0P_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQ0P :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ0P_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ0P_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQ0P :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ0P_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ0P_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ0P_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQ0P :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ0P_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ0P_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQ0P :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ0P_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ0P_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ0P_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQ0P :: reserved2 [11:08] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ0P_reserved2_MASK 0x00000f00
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ0P_reserved2_SHIFT 8
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQ0P :: VDL_STEP [07:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ0P_VDL_STEP_MASK 0x000000ff
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ0P_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ0P_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_RD_DQ0N - Read channel DQ0-N VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQ0N :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ0N_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ0N_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ0N_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQ0N :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ0N_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ0N_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQ0N :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ0N_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ0N_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ0N_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQ0N :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ0N_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ0N_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQ0N :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ0N_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ0N_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ0N_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQ0N :: reserved2 [11:08] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ0N_reserved2_MASK 0x00000f00
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ0N_reserved2_SHIFT 8
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQ0N :: VDL_STEP [07:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ0N_VDL_STEP_MASK 0x000000ff
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ0N_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ0N_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_RD_DQ1P - Read channel DQ1-P VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQ1P :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ1P_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ1P_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ1P_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQ1P :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ1P_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ1P_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQ1P :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ1P_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ1P_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ1P_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQ1P :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ1P_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ1P_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQ1P :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ1P_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ1P_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ1P_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQ1P :: reserved2 [11:08] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ1P_reserved2_MASK 0x00000f00
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ1P_reserved2_SHIFT 8
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQ1P :: VDL_STEP [07:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ1P_VDL_STEP_MASK 0x000000ff
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ1P_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ1P_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_RD_DQ1N - Read channel DQ1-N VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQ1N :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ1N_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ1N_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ1N_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQ1N :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ1N_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ1N_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQ1N :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ1N_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ1N_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ1N_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQ1N :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ1N_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ1N_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQ1N :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ1N_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ1N_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ1N_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQ1N :: reserved2 [11:08] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ1N_reserved2_MASK 0x00000f00
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ1N_reserved2_SHIFT 8
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQ1N :: VDL_STEP [07:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ1N_VDL_STEP_MASK 0x000000ff
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ1N_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ1N_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_RD_DQ2P - Read channel DQ2-P VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQ2P :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ2P_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ2P_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ2P_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQ2P :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ2P_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ2P_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQ2P :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ2P_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ2P_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ2P_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQ2P :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ2P_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ2P_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQ2P :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ2P_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ2P_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ2P_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQ2P :: reserved2 [11:08] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ2P_reserved2_MASK 0x00000f00
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ2P_reserved2_SHIFT 8
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQ2P :: VDL_STEP [07:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ2P_VDL_STEP_MASK 0x000000ff
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ2P_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ2P_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_RD_DQ2N - Read channel DQ2-N VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQ2N :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ2N_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ2N_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ2N_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQ2N :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ2N_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ2N_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQ2N :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ2N_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ2N_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ2N_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQ2N :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ2N_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ2N_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQ2N :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ2N_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ2N_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ2N_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQ2N :: reserved2 [11:08] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ2N_reserved2_MASK 0x00000f00
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ2N_reserved2_SHIFT 8
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQ2N :: VDL_STEP [07:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ2N_VDL_STEP_MASK 0x000000ff
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ2N_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ2N_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_RD_DQ3P - Read channel DQ3-P VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQ3P :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ3P_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ3P_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ3P_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQ3P :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ3P_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ3P_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQ3P :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ3P_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ3P_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ3P_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQ3P :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ3P_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ3P_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQ3P :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ3P_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ3P_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ3P_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQ3P :: reserved2 [11:08] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ3P_reserved2_MASK 0x00000f00
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ3P_reserved2_SHIFT 8
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQ3P :: VDL_STEP [07:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ3P_VDL_STEP_MASK 0x000000ff
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ3P_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ3P_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_RD_DQ3N - Read channel DQ3-N VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQ3N :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ3N_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ3N_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ3N_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQ3N :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ3N_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ3N_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQ3N :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ3N_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ3N_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ3N_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQ3N :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ3N_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ3N_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQ3N :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ3N_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ3N_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ3N_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQ3N :: reserved2 [11:08] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ3N_reserved2_MASK 0x00000f00
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ3N_reserved2_SHIFT 8
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQ3N :: VDL_STEP [07:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ3N_VDL_STEP_MASK 0x000000ff
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ3N_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ3N_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_RD_DQ4P - Read channel DQ4-P VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQ4P :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ4P_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ4P_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ4P_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQ4P :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ4P_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ4P_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQ4P :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ4P_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ4P_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ4P_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQ4P :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ4P_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ4P_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQ4P :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ4P_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ4P_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ4P_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQ4P :: reserved2 [11:08] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ4P_reserved2_MASK 0x00000f00
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ4P_reserved2_SHIFT 8
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQ4P :: VDL_STEP [07:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ4P_VDL_STEP_MASK 0x000000ff
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ4P_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ4P_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_RD_DQ4N - Read channel DQ4-N VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQ4N :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ4N_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ4N_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ4N_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQ4N :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ4N_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ4N_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQ4N :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ4N_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ4N_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ4N_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQ4N :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ4N_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ4N_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQ4N :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ4N_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ4N_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ4N_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQ4N :: reserved2 [11:08] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ4N_reserved2_MASK 0x00000f00
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ4N_reserved2_SHIFT 8
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQ4N :: VDL_STEP [07:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ4N_VDL_STEP_MASK 0x000000ff
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ4N_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ4N_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_RD_DQ5P - Read channel DQ5-P VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQ5P :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ5P_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ5P_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ5P_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQ5P :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ5P_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ5P_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQ5P :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ5P_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ5P_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ5P_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQ5P :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ5P_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ5P_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQ5P :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ5P_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ5P_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ5P_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQ5P :: reserved2 [11:08] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ5P_reserved2_MASK 0x00000f00
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ5P_reserved2_SHIFT 8
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQ5P :: VDL_STEP [07:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ5P_VDL_STEP_MASK 0x000000ff
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ5P_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ5P_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_RD_DQ5N - Read channel DQ5-N VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQ5N :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ5N_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ5N_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ5N_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQ5N :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ5N_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ5N_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQ5N :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ5N_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ5N_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ5N_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQ5N :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ5N_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ5N_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQ5N :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ5N_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ5N_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ5N_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQ5N :: reserved2 [11:08] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ5N_reserved2_MASK 0x00000f00
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ5N_reserved2_SHIFT 8
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQ5N :: VDL_STEP [07:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ5N_VDL_STEP_MASK 0x000000ff
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ5N_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ5N_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_RD_DQ6P - Read channel DQ6-P VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQ6P :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ6P_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ6P_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ6P_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQ6P :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ6P_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ6P_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQ6P :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ6P_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ6P_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ6P_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQ6P :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ6P_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ6P_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQ6P :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ6P_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ6P_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ6P_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQ6P :: reserved2 [11:08] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ6P_reserved2_MASK 0x00000f00
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ6P_reserved2_SHIFT 8
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQ6P :: VDL_STEP [07:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ6P_VDL_STEP_MASK 0x000000ff
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ6P_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ6P_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_RD_DQ6N - Read channel DQ6-N VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQ6N :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ6N_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ6N_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ6N_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQ6N :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ6N_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ6N_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQ6N :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ6N_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ6N_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ6N_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQ6N :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ6N_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ6N_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQ6N :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ6N_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ6N_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ6N_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQ6N :: reserved2 [11:08] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ6N_reserved2_MASK 0x00000f00
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ6N_reserved2_SHIFT 8
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQ6N :: VDL_STEP [07:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ6N_VDL_STEP_MASK 0x000000ff
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ6N_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ6N_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_RD_DQ7P - Read channel DQ7-P VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQ7P :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ7P_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ7P_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ7P_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQ7P :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ7P_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ7P_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQ7P :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ7P_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ7P_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ7P_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQ7P :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ7P_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ7P_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQ7P :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ7P_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ7P_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ7P_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQ7P :: reserved2 [11:08] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ7P_reserved2_MASK 0x00000f00
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ7P_reserved2_SHIFT 8
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQ7P :: VDL_STEP [07:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ7P_VDL_STEP_MASK 0x000000ff
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ7P_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ7P_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_RD_DQ7N - Read channel DQ7-N VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQ7N :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ7N_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ7N_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ7N_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQ7N :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ7N_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ7N_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQ7N :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ7N_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ7N_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ7N_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQ7N :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ7N_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ7N_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQ7N :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ7N_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ7N_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ7N_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQ7N :: reserved2 [11:08] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ7N_reserved2_MASK 0x00000f00
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ7N_reserved2_SHIFT 8
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQ7N :: VDL_STEP [07:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ7N_VDL_STEP_MASK 0x000000ff
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ7N_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ7N_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_RD_DMP - Read channel DM-P VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DMP :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DMP_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DMP_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DMP_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DMP :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DMP_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DMP_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DMP :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DMP_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DMP_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DMP_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DMP :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DMP_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DMP_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DMP :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DMP_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DMP_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DMP_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DMP :: reserved2 [11:08] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DMP_reserved2_MASK 0x00000f00
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DMP_reserved2_SHIFT 8
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DMP :: VDL_STEP [07:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DMP_VDL_STEP_MASK 0x000000ff
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DMP_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DMP_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_RD_DMN - Read channel DM-N VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DMN :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DMN_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DMN_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DMN_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DMN :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DMN_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DMN_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DMN :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DMN_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DMN_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DMN_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DMN :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DMN_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DMN_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DMN :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DMN_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DMN_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DMN_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DMN :: reserved2 [11:08] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DMN_reserved2_MASK 0x00000f00
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DMN_reserved2_SHIFT 8
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DMN :: VDL_STEP [07:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DMN_VDL_STEP_MASK 0x000000ff
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DMN_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DMN_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_RD_EDCP - Read channel EDC-P VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_EDCP :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_EDCP_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_EDCP_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_EDCP_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_EDCP :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_EDCP_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_EDCP_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_EDCP :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_EDCP_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_EDCP_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_EDCP_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_EDCP :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_EDCP_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_EDCP_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_EDCP :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_EDCP_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_EDCP_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_EDCP_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_EDCP :: reserved2 [11:08] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_EDCP_reserved2_MASK 0x00000f00
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_EDCP_reserved2_SHIFT 8
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_EDCP :: VDL_STEP [07:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_EDCP_VDL_STEP_MASK 0x000000ff
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_EDCP_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_EDCP_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_RD_EDCN - Read channel EDC-N VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_EDCN :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_EDCN_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_EDCN_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_EDCN_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_EDCN :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_EDCN_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_EDCN_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_EDCN :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_EDCN_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_EDCN_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_EDCN_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_EDCN :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_EDCN_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_EDCN_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_EDCN :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_EDCN_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_EDCN_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_EDCN_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_EDCN :: reserved2 [11:08] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_EDCN_reserved2_MASK 0x00000f00
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_EDCN_reserved2_SHIFT 8
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_EDCN :: VDL_STEP [07:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_EDCN_VDL_STEP_MASK 0x000000ff
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_EDCN_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_EDCN_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_RD_EN_CS0 - Read channel CS_N[0] read enable VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_EN_CS0 :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_EN_CS0_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_EN_CS0_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_EN_CS0_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_EN_CS0 :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_EN_CS0_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_EN_CS0_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_EN_CS0 :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_EN_CS0_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_EN_CS0_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_EN_CS0_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_EN_CS0 :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_EN_CS0_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_EN_CS0_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_EN_CS0 :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_EN_CS0_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_EN_CS0_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_EN_CS0_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_EN_CS0 :: reserved2 [11:08] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_EN_CS0_reserved2_MASK 0x00000f00
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_EN_CS0_reserved2_SHIFT 8
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_EN_CS0 :: VDL_STEP [07:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_EN_CS0_VDL_STEP_MASK 0x000000ff
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_EN_CS0_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_EN_CS0_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_RD_EN_CS1 - Read channel CS_N[1] read enable VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_EN_CS1 :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_EN_CS1_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_EN_CS1_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_EN_CS1_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_EN_CS1 :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_EN_CS1_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_EN_CS1_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_EN_CS1 :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_EN_CS1_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_EN_CS1_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_EN_CS1_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_EN_CS1 :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_EN_CS1_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_EN_CS1_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_EN_CS1 :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_EN_CS1_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_EN_CS1_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_EN_CS1_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_EN_CS1 :: reserved2 [11:08] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_EN_CS1_reserved2_MASK 0x00000f00
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_EN_CS1_reserved2_SHIFT 8
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_EN_CS1 :: VDL_STEP [07:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_EN_CS1_VDL_STEP_MASK 0x000000ff
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_EN_CS1_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_EN_CS1_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CLK_CONTROL - DDR interface signal Write Leveling CLK VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CLK_CONTROL :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CLK_CONTROL_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CLK_CONTROL_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CLK_CONTROL_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CLK_CONTROL :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CLK_CONTROL_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CLK_CONTROL_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CLK_CONTROL :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CLK_CONTROL_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CLK_CONTROL_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CLK_CONTROL_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CLK_CONTROL :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CLK_CONTROL_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CLK_CONTROL_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CLK_CONTROL :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CLK_CONTROL_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CLK_CONTROL_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CLK_CONTROL_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CLK_CONTROL :: reserved2 [11:09] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CLK_CONTROL_reserved2_MASK 0x00000e00
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CLK_CONTROL_reserved2_SHIFT 9
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CLK_CONTROL :: VDL_STEP [08:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CLK_CONTROL_VDL_STEP_MASK 0x000001ff
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CLK_CONTROL_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CLK_CONTROL_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_LDE_CONTROL - DDR interface signal Write Leveling Capture Enable VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_LDE_CONTROL :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_LDE_CONTROL_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_LDE_CONTROL_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_LDE_CONTROL_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_LDE_CONTROL :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_LDE_CONTROL_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_LDE_CONTROL_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_LDE_CONTROL :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_LDE_CONTROL_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_LDE_CONTROL_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_LDE_CONTROL_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_LDE_CONTROL :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_LDE_CONTROL_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_LDE_CONTROL_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_LDE_CONTROL :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_LDE_CONTROL_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_LDE_CONTROL_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_LDE_CONTROL_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_LDE_CONTROL :: reserved2 [11:09] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_LDE_CONTROL_reserved2_MASK 0x00000e00
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_LDE_CONTROL_reserved2_SHIFT 9
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_LDE_CONTROL :: VDL_STEP [08:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_LDE_CONTROL_VDL_STEP_MASK 0x000001ff
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_LDE_CONTROL_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_LDE_CONTROL_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *RD_EN_DLY_CYC - Read enable bit-clock cycle delay control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_2_0 :: RD_EN_DLY_CYC :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_RD_EN_DLY_CYC_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_RD_EN_DLY_CYC_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_RD_EN_DLY_CYC_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: RD_EN_DLY_CYC :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_RD_EN_DLY_CYC_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_RD_EN_DLY_CYC_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: RD_EN_DLY_CYC :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_RD_EN_DLY_CYC_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_RD_EN_DLY_CYC_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_RD_EN_DLY_CYC_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: RD_EN_DLY_CYC :: reserved1 [15:08] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_RD_EN_DLY_CYC_reserved1_MASK 0x0000ff00
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_RD_EN_DLY_CYC_reserved1_SHIFT 8
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: RD_EN_DLY_CYC :: CS1_CYCLES [07:04] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_RD_EN_DLY_CYC_CS1_CYCLES_MASK 0x000000f0
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_RD_EN_DLY_CYC_CS1_CYCLES_SHIFT 4
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_RD_EN_DLY_CYC_CS1_CYCLES_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: RD_EN_DLY_CYC :: CS0_CYCLES [03:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_RD_EN_DLY_CYC_CS0_CYCLES_MASK 0x0000000f
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_RD_EN_DLY_CYC_CS0_CYCLES_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_RD_EN_DLY_CYC_CS0_CYCLES_DEFAULT 0x00000000
-
-/***************************************************************************
- *WR_CHAN_DLY_CYC - Write leveling bit-clock cycle delay control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_2_0 :: WR_CHAN_DLY_CYC :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_WR_CHAN_DLY_CYC_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_WR_CHAN_DLY_CYC_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_WR_CHAN_DLY_CYC_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: WR_CHAN_DLY_CYC :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_WR_CHAN_DLY_CYC_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_WR_CHAN_DLY_CYC_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: WR_CHAN_DLY_CYC :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_WR_CHAN_DLY_CYC_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_WR_CHAN_DLY_CYC_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_WR_CHAN_DLY_CYC_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: WR_CHAN_DLY_CYC :: reserved1 [15:03] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_WR_CHAN_DLY_CYC_reserved1_MASK 0x0000fff8
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_WR_CHAN_DLY_CYC_reserved1_SHIFT 3
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: WR_CHAN_DLY_CYC :: CYCLES [02:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_WR_CHAN_DLY_CYC_CYCLES_MASK 0x00000007
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_WR_CHAN_DLY_CYC_CYCLES_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_WR_CHAN_DLY_CYC_CYCLES_DEFAULT 0x00000000
-
-/***************************************************************************
- *READ_CONTROL - Read channel datapath control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_2_0 :: READ_CONTROL :: reserved0 [31:05] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_READ_CONTROL_reserved0_MASK 0xffffffe0
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_READ_CONTROL_reserved0_SHIFT 5
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: READ_CONTROL :: MODE [04:04] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_READ_CONTROL_MODE_MASK 0x00000010
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_READ_CONTROL_MODE_SHIFT 4
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_READ_CONTROL_MODE_DEFAULT 0x00000001
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: READ_CONTROL :: reserved1 [03:03] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_READ_CONTROL_reserved1_MASK 0x00000008
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_READ_CONTROL_reserved1_SHIFT 3
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: READ_CONTROL :: RD_DATA_DLY [02:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_READ_CONTROL_RD_DATA_DLY_MASK 0x00000007
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_READ_CONTROL_RD_DATA_DLY_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_READ_CONTROL_RD_DATA_DLY_DEFAULT 0x00000007
-
-/***************************************************************************
- *READ_FIFO_ADDR - Read fifo addresss pointer register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_2_0 :: READ_FIFO_ADDR :: reserved0 [31:03] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_READ_FIFO_ADDR_reserved0_MASK 0xfffffff8
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_READ_FIFO_ADDR_reserved0_SHIFT 3
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: READ_FIFO_ADDR :: ADDR [02:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_READ_FIFO_ADDR_ADDR_MASK 0x00000007
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_READ_FIFO_ADDR_ADDR_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_READ_FIFO_ADDR_ADDR_DEFAULT 0x00000000
-
-/***************************************************************************
- *READ_FIFO_DATA - Read fifo data register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_2_0 :: READ_FIFO_DATA :: DATA [31:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_READ_FIFO_DATA_DATA_MASK 0xffffffff
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_READ_FIFO_DATA_DATA_SHIFT 0
-
-/***************************************************************************
- *READ_FIFO_DM_DBI - Read fifo dm/dbi register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_2_0 :: READ_FIFO_DM_DBI :: reserved0 [31:04] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_READ_FIFO_DM_DBI_reserved0_MASK 0xfffffff0
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_READ_FIFO_DM_DBI_reserved0_SHIFT 4
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: READ_FIFO_DM_DBI :: DM_DBI [03:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_READ_FIFO_DM_DBI_DM_DBI_MASK 0x0000000f
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_READ_FIFO_DM_DBI_DM_DBI_SHIFT 0
-
-/***************************************************************************
- *READ_FIFO_STATUS - Read fifo status register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_2_0 :: READ_FIFO_STATUS :: reserved0 [31:02] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_READ_FIFO_STATUS_reserved0_MASK 0xfffffffc
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_READ_FIFO_STATUS_reserved0_SHIFT 2
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: READ_FIFO_STATUS :: OVERFLOW [01:01] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_READ_FIFO_STATUS_OVERFLOW_MASK 0x00000002
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_READ_FIFO_STATUS_OVERFLOW_SHIFT 1
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_READ_FIFO_STATUS_OVERFLOW_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: READ_FIFO_STATUS :: UNDERFLOW [00:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_READ_FIFO_STATUS_UNDERFLOW_MASK 0x00000001
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_READ_FIFO_STATUS_UNDERFLOW_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_READ_FIFO_STATUS_UNDERFLOW_DEFAULT 0x00000000
-
-/***************************************************************************
- *READ_FIFO_CLEAR - Read fifo status clear register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_2_0 :: READ_FIFO_CLEAR :: reserved0 [31:01] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_READ_FIFO_CLEAR_reserved0_MASK 0xfffffffe
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_READ_FIFO_CLEAR_reserved0_SHIFT 1
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: READ_FIFO_CLEAR :: CLEAR [00:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_READ_FIFO_CLEAR_CLEAR_MASK 0x00000001
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_READ_FIFO_CLEAR_CLEAR_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_READ_FIFO_CLEAR_CLEAR_DEFAULT 0x00000000
-
-/***************************************************************************
- *IDLE_PAD_CONTROL - Idle mode SSTL pad control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_2_0 :: IDLE_PAD_CONTROL :: IDLE [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_IDLE_PAD_CONTROL_IDLE_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_IDLE_PAD_CONTROL_IDLE_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_IDLE_PAD_CONTROL_IDLE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: IDLE_PAD_CONTROL :: reserved0 [30:20] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_IDLE_PAD_CONTROL_reserved0_MASK 0x7ff00000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_IDLE_PAD_CONTROL_reserved0_SHIFT 20
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: IDLE_PAD_CONTROL :: AUTO_DQ_RXENB_MODE [19:18] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_IDLE_PAD_CONTROL_AUTO_DQ_RXENB_MODE_MASK 0x000c0000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_IDLE_PAD_CONTROL_AUTO_DQ_RXENB_MODE_SHIFT 18
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_IDLE_PAD_CONTROL_AUTO_DQ_RXENB_MODE_DEFAULT 0x00000001
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: IDLE_PAD_CONTROL :: AUTO_DQ_IDDQ_MODE [17:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_IDLE_PAD_CONTROL_AUTO_DQ_IDDQ_MODE_MASK 0x00030000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_IDLE_PAD_CONTROL_AUTO_DQ_IDDQ_MODE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_IDLE_PAD_CONTROL_AUTO_DQ_IDDQ_MODE_DEFAULT 0x00000001
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: IDLE_PAD_CONTROL :: reserved_for_padding1 [15:15] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_IDLE_PAD_CONTROL_reserved_for_padding1_MASK 0x00008000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_IDLE_PAD_CONTROL_reserved_for_padding1_SHIFT 15
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: IDLE_PAD_CONTROL :: IO_IDLE_ENABLE [14:04] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_IDLE_PAD_CONTROL_IO_IDLE_ENABLE_MASK 0x00007ff0
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_IDLE_PAD_CONTROL_IO_IDLE_ENABLE_SHIFT 4
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_IDLE_PAD_CONTROL_IO_IDLE_ENABLE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: IDLE_PAD_CONTROL :: RXENB [03:03] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_IDLE_PAD_CONTROL_RXENB_MASK 0x00000008
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_IDLE_PAD_CONTROL_RXENB_SHIFT 3
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_IDLE_PAD_CONTROL_RXENB_DEFAULT 0x00000001
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: IDLE_PAD_CONTROL :: IDDQ [02:02] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_IDLE_PAD_CONTROL_IDDQ_MASK 0x00000004
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_IDLE_PAD_CONTROL_IDDQ_SHIFT 2
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_IDLE_PAD_CONTROL_IDDQ_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: IDLE_PAD_CONTROL :: DOUT_N [01:01] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_IDLE_PAD_CONTROL_DOUT_N_MASK 0x00000002
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_IDLE_PAD_CONTROL_DOUT_N_SHIFT 1
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: IDLE_PAD_CONTROL :: DOUT_P [00:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_IDLE_PAD_CONTROL_DOUT_P_MASK 0x00000001
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_IDLE_PAD_CONTROL_DOUT_P_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_IDLE_PAD_CONTROL_DOUT_P_DEFAULT 0x00000000
-
-/***************************************************************************
- *DRIVE_PAD_CTL - SSTL pad drive characteristics control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_2_0 :: DRIVE_PAD_CTL :: reserved0 [31:30] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_DRIVE_PAD_CTL_reserved0_MASK 0xc0000000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_DRIVE_PAD_CTL_reserved0_SHIFT 30
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: DRIVE_PAD_CTL :: BL_PD_IDLE_STRENGTH [29:25] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_DRIVE_PAD_CTL_BL_PD_IDLE_STRENGTH_MASK 0x3e000000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_DRIVE_PAD_CTL_BL_PD_IDLE_STRENGTH_SHIFT 25
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_DRIVE_PAD_CTL_BL_PD_IDLE_STRENGTH_DEFAULT 0x0000001f
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: DRIVE_PAD_CTL :: BL_ND_IDLE_STRENGTH [24:20] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_DRIVE_PAD_CTL_BL_ND_IDLE_STRENGTH_MASK 0x01f00000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_DRIVE_PAD_CTL_BL_ND_IDLE_STRENGTH_SHIFT 20
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_DRIVE_PAD_CTL_BL_ND_IDLE_STRENGTH_DEFAULT 0x0000001f
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: DRIVE_PAD_CTL :: BL_PD_TERM_STRENGTH [19:15] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_DRIVE_PAD_CTL_BL_PD_TERM_STRENGTH_MASK 0x000f8000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_DRIVE_PAD_CTL_BL_PD_TERM_STRENGTH_SHIFT 15
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_DRIVE_PAD_CTL_BL_PD_TERM_STRENGTH_DEFAULT 0x00000008
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: DRIVE_PAD_CTL :: BL_ND_TERM_STRENGTH [14:10] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_DRIVE_PAD_CTL_BL_ND_TERM_STRENGTH_MASK 0x00007c00
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_DRIVE_PAD_CTL_BL_ND_TERM_STRENGTH_SHIFT 10
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_DRIVE_PAD_CTL_BL_ND_TERM_STRENGTH_DEFAULT 0x00000008
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: DRIVE_PAD_CTL :: BL_PD_STRENGTH [09:05] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_DRIVE_PAD_CTL_BL_PD_STRENGTH_MASK 0x000003e0
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_DRIVE_PAD_CTL_BL_PD_STRENGTH_SHIFT 5
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_DRIVE_PAD_CTL_BL_PD_STRENGTH_DEFAULT 0x0000001f
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: DRIVE_PAD_CTL :: BL_ND_STRENGTH [04:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_DRIVE_PAD_CTL_BL_ND_STRENGTH_MASK 0x0000001f
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_DRIVE_PAD_CTL_BL_ND_STRENGTH_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_DRIVE_PAD_CTL_BL_ND_STRENGTH_DEFAULT 0x0000001f
-
-/***************************************************************************
- *RD_EN_DRIVE_PAD_CTL - SSTL read enable pad drive characteristics control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_2_0 :: RD_EN_DRIVE_PAD_CTL :: reserved0 [31:20] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_RD_EN_DRIVE_PAD_CTL_reserved0_MASK 0xfff00000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_RD_EN_DRIVE_PAD_CTL_reserved0_SHIFT 20
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: RD_EN_DRIVE_PAD_CTL :: EDC_RD_EN_PD_STRENGTH [19:15] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_RD_EN_DRIVE_PAD_CTL_EDC_RD_EN_PD_STRENGTH_MASK 0x000f8000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_RD_EN_DRIVE_PAD_CTL_EDC_RD_EN_PD_STRENGTH_SHIFT 15
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_RD_EN_DRIVE_PAD_CTL_EDC_RD_EN_PD_STRENGTH_DEFAULT 0x0000001f
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: RD_EN_DRIVE_PAD_CTL :: EDC_RD_EN_ND_STRENGTH [14:10] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_RD_EN_DRIVE_PAD_CTL_EDC_RD_EN_ND_STRENGTH_MASK 0x00007c00
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_RD_EN_DRIVE_PAD_CTL_EDC_RD_EN_ND_STRENGTH_SHIFT 10
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_RD_EN_DRIVE_PAD_CTL_EDC_RD_EN_ND_STRENGTH_DEFAULT 0x0000001f
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: RD_EN_DRIVE_PAD_CTL :: BL_RD_EN_PD_STRENGTH [09:05] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_RD_EN_DRIVE_PAD_CTL_BL_RD_EN_PD_STRENGTH_MASK 0x000003e0
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_RD_EN_DRIVE_PAD_CTL_BL_RD_EN_PD_STRENGTH_SHIFT 5
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_RD_EN_DRIVE_PAD_CTL_BL_RD_EN_PD_STRENGTH_DEFAULT 0x0000001f
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: RD_EN_DRIVE_PAD_CTL :: BL_RD_EN_ND_STRENGTH [04:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_RD_EN_DRIVE_PAD_CTL_BL_RD_EN_ND_STRENGTH_MASK 0x0000001f
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_RD_EN_DRIVE_PAD_CTL_BL_RD_EN_ND_STRENGTH_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_RD_EN_DRIVE_PAD_CTL_BL_RD_EN_ND_STRENGTH_DEFAULT 0x0000001f
-
-/***************************************************************************
- *STATIC_PAD_CTL - pad rx and tx characteristics control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_2_0 :: STATIC_PAD_CTL :: reserved0 [31:21] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_STATIC_PAD_CTL_reserved0_MASK 0xffe00000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_STATIC_PAD_CTL_reserved0_SHIFT 21
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: STATIC_PAD_CTL :: DQS_MODE [20:20] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_STATIC_PAD_CTL_DQS_MODE_MASK 0x00100000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_STATIC_PAD_CTL_DQS_MODE_SHIFT 20
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_STATIC_PAD_CTL_DQS_MODE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: STATIC_PAD_CTL :: reserved1 [19:18] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_STATIC_PAD_CTL_reserved1_MASK 0x000c0000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_STATIC_PAD_CTL_reserved1_SHIFT 18
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: STATIC_PAD_CTL :: EDC_MODE [17:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_STATIC_PAD_CTL_EDC_MODE_MASK 0x00030000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_STATIC_PAD_CTL_EDC_MODE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_STATIC_PAD_CTL_EDC_MODE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: STATIC_PAD_CTL :: reserved2 [15:15] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_STATIC_PAD_CTL_reserved2_MASK 0x00008000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_STATIC_PAD_CTL_reserved2_SHIFT 15
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: STATIC_PAD_CTL :: WDBI_ENABLE [14:14] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_STATIC_PAD_CTL_WDBI_ENABLE_MASK 0x00004000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_STATIC_PAD_CTL_WDBI_ENABLE_SHIFT 14
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_STATIC_PAD_CTL_WDBI_ENABLE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: STATIC_PAD_CTL :: RDBI_ENABLE [13:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_STATIC_PAD_CTL_RDBI_ENABLE_MASK 0x00002000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_STATIC_PAD_CTL_RDBI_ENABLE_SHIFT 13
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_STATIC_PAD_CTL_RDBI_ENABLE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: STATIC_PAD_CTL :: DM_MODE [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_STATIC_PAD_CTL_DM_MODE_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_STATIC_PAD_CTL_DM_MODE_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_STATIC_PAD_CTL_DM_MODE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: STATIC_PAD_CTL :: reserved3 [11:11] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_STATIC_PAD_CTL_reserved3_MASK 0x00000800
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_STATIC_PAD_CTL_reserved3_SHIFT 11
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: STATIC_PAD_CTL :: DQS_TX_PAUSE [10:10] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_STATIC_PAD_CTL_DQS_TX_PAUSE_MASK 0x00000400
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_STATIC_PAD_CTL_DQS_TX_PAUSE_SHIFT 10
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_STATIC_PAD_CTL_DQS_TX_PAUSE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: STATIC_PAD_CTL :: DQS_TX_DIS [09:09] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_STATIC_PAD_CTL_DQS_TX_DIS_MASK 0x00000200
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_STATIC_PAD_CTL_DQS_TX_DIS_SHIFT 9
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_STATIC_PAD_CTL_DQS_TX_DIS_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: STATIC_PAD_CTL :: reserved4 [08:08] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_STATIC_PAD_CTL_reserved4_MASK 0x00000100
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_STATIC_PAD_CTL_reserved4_SHIFT 8
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: STATIC_PAD_CTL :: TX_MODE [07:04] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_STATIC_PAD_CTL_TX_MODE_MASK 0x000000f0
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_STATIC_PAD_CTL_TX_MODE_SHIFT 4
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_STATIC_PAD_CTL_TX_MODE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: STATIC_PAD_CTL :: reserved5 [03:03] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_STATIC_PAD_CTL_reserved5_MASK 0x00000008
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_STATIC_PAD_CTL_reserved5_SHIFT 3
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: STATIC_PAD_CTL :: RX_MODE [02:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_STATIC_PAD_CTL_RX_MODE_MASK 0x00000007
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_STATIC_PAD_CTL_RX_MODE_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_STATIC_PAD_CTL_RX_MODE_DEFAULT 0x00000000
-
-/***************************************************************************
- *WR_PREAMBLE_MODE - Write cycle preamble control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_2_0 :: WR_PREAMBLE_MODE :: reserved0 [31:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_WR_PREAMBLE_MODE_reserved0_MASK 0xffff0000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_WR_PREAMBLE_MODE_reserved0_SHIFT 16
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: WR_PREAMBLE_MODE :: DQ_POSTAM_BITS [15:14] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_WR_PREAMBLE_MODE_DQ_POSTAM_BITS_MASK 0x0000c000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_WR_PREAMBLE_MODE_DQ_POSTAM_BITS_SHIFT 14
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_WR_PREAMBLE_MODE_DQ_POSTAM_BITS_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: WR_PREAMBLE_MODE :: DQ_PREAM_BITS [13:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_WR_PREAMBLE_MODE_DQ_PREAM_BITS_MASK 0x00003000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_WR_PREAMBLE_MODE_DQ_PREAM_BITS_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_WR_PREAMBLE_MODE_DQ_PREAM_BITS_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: WR_PREAMBLE_MODE :: DQS [11:08] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_WR_PREAMBLE_MODE_DQS_MASK 0x00000f00
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_WR_PREAMBLE_MODE_DQS_SHIFT 8
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_WR_PREAMBLE_MODE_DQS_DEFAULT 0x0000000e
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: WR_PREAMBLE_MODE :: reserved1 [07:05] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_WR_PREAMBLE_MODE_reserved1_MASK 0x000000e0
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_WR_PREAMBLE_MODE_reserved1_SHIFT 5
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: WR_PREAMBLE_MODE :: DQS_POSTAM_BITS [04:03] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_WR_PREAMBLE_MODE_DQS_POSTAM_BITS_MASK 0x00000018
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_WR_PREAMBLE_MODE_DQS_POSTAM_BITS_SHIFT 3
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_WR_PREAMBLE_MODE_DQS_POSTAM_BITS_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: WR_PREAMBLE_MODE :: DQS_PREAM_BITS [02:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_WR_PREAMBLE_MODE_DQS_PREAM_BITS_MASK 0x00000007
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_WR_PREAMBLE_MODE_DQS_PREAM_BITS_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_WR_PREAMBLE_MODE_DQS_PREAM_BITS_DEFAULT 0x00000002
-
-/***************************************************************************
- *ODT_CONTROL - Read channel ODT control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_2_0 :: ODT_CONTROL :: reserved_for_padding0 [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_ODT_CONTROL_reserved_for_padding0_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_ODT_CONTROL_reserved_for_padding0_SHIFT 31
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: ODT_CONTROL :: reserved1 [30:10] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_ODT_CONTROL_reserved1_MASK 0x7ffffc00
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_ODT_CONTROL_reserved1_SHIFT 10
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: ODT_CONTROL :: ODT_ENABLE [09:09] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_ODT_CONTROL_ODT_ENABLE_MASK 0x00000200
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_ODT_CONTROL_ODT_ENABLE_SHIFT 9
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_ODT_CONTROL_ODT_ENABLE_DEFAULT 0x00000001
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: ODT_CONTROL :: ODT_DELAY [08:06] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_ODT_CONTROL_ODT_DELAY_MASK 0x000001c0
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_ODT_CONTROL_ODT_DELAY_SHIFT 6
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_ODT_CONTROL_ODT_DELAY_DEFAULT 0x00000001
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: ODT_CONTROL :: ODT_POST_LENGTH [05:03] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_ODT_CONTROL_ODT_POST_LENGTH_MASK 0x00000038
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_ODT_CONTROL_ODT_POST_LENGTH_SHIFT 3
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_ODT_CONTROL_ODT_POST_LENGTH_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: ODT_CONTROL :: ODT_PRE_LENGTH [02:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_ODT_CONTROL_ODT_PRE_LENGTH_MASK 0x00000007
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_ODT_CONTROL_ODT_PRE_LENGTH_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_ODT_CONTROL_ODT_PRE_LENGTH_DEFAULT 0x00000003
-
-/***************************************************************************
- *EDC_DPD_CONTROL - GDDR5M EDC digital phase detector control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_2_0 :: EDC_DPD_CONTROL :: reserved0 [31:06] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_DPD_CONTROL_reserved0_MASK 0xffffffc0
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_DPD_CONTROL_reserved0_SHIFT 6
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: EDC_DPD_CONTROL :: DQS_PHASE_OVERRIDE_VALUE [05:05] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_DPD_CONTROL_DQS_PHASE_OVERRIDE_VALUE_MASK 0x00000020
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_DPD_CONTROL_DQS_PHASE_OVERRIDE_VALUE_SHIFT 5
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_DPD_CONTROL_DQS_PHASE_OVERRIDE_VALUE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: EDC_DPD_CONTROL :: DQS_PHASE_OVERRIDE_ENABLE [04:04] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_DPD_CONTROL_DQS_PHASE_OVERRIDE_ENABLE_MASK 0x00000010
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_DPD_CONTROL_DQS_PHASE_OVERRIDE_ENABLE_SHIFT 4
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_DPD_CONTROL_DQS_PHASE_OVERRIDE_ENABLE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: EDC_DPD_CONTROL :: SET_ADJ_EN [03:03] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_DPD_CONTROL_SET_ADJ_EN_MASK 0x00000008
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_DPD_CONTROL_SET_ADJ_EN_SHIFT 3
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_DPD_CONTROL_SET_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: EDC_DPD_CONTROL :: UPDATE [02:02] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_DPD_CONTROL_UPDATE_MASK 0x00000004
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_DPD_CONTROL_UPDATE_SHIFT 2
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_DPD_CONTROL_UPDATE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: EDC_DPD_CONTROL :: MONITOR [01:01] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_DPD_CONTROL_MONITOR_MASK 0x00000002
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_DPD_CONTROL_MONITOR_SHIFT 1
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_DPD_CONTROL_MONITOR_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: EDC_DPD_CONTROL :: INIT [00:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_DPD_CONTROL_INIT_MASK 0x00000001
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_DPD_CONTROL_INIT_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_DPD_CONTROL_INIT_DEFAULT 0x00000000
-
-/***************************************************************************
- *EDC_DPD_STATUS - GDDR5M EDC digital phase detector status register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_2_0 :: EDC_DPD_STATUS :: reserved0 [31:25] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_DPD_STATUS_reserved0_MASK 0xfe000000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_DPD_STATUS_reserved0_SHIFT 25
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: EDC_DPD_STATUS :: CURRENT_DQS_PHASE [24:24] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_DPD_STATUS_CURRENT_DQS_PHASE_MASK 0x01000000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_DPD_STATUS_CURRENT_DQS_PHASE_SHIFT 24
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_DPD_STATUS_CURRENT_DQS_PHASE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: EDC_DPD_STATUS :: CURRENT_VDL_SETTING [23:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_DPD_STATUS_CURRENT_VDL_SETTING_MASK 0x00ff0000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_DPD_STATUS_CURRENT_VDL_SETTING_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_DPD_STATUS_CURRENT_VDL_SETTING_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: EDC_DPD_STATUS :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_DPD_STATUS_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_DPD_STATUS_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: EDC_DPD_STATUS :: INIT_DQS_PHASE [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_DPD_STATUS_INIT_DQS_PHASE_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_DPD_STATUS_INIT_DQS_PHASE_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_DPD_STATUS_INIT_DQS_PHASE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: EDC_DPD_STATUS :: INIT_VDL_SETTING [11:04] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_DPD_STATUS_INIT_VDL_SETTING_MASK 0x00000ff0
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_DPD_STATUS_INIT_VDL_SETTING_SHIFT 4
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_DPD_STATUS_INIT_VDL_SETTING_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: EDC_DPD_STATUS :: EDGE_ERROR [03:03] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_DPD_STATUS_EDGE_ERROR_MASK 0x00000008
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_DPD_STATUS_EDGE_ERROR_SHIFT 3
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_DPD_STATUS_EDGE_ERROR_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: EDC_DPD_STATUS :: MONITOR_BUSY [02:02] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_DPD_STATUS_MONITOR_BUSY_MASK 0x00000004
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_DPD_STATUS_MONITOR_BUSY_SHIFT 2
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_DPD_STATUS_MONITOR_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: EDC_DPD_STATUS :: INIT_BUSY [01:01] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_DPD_STATUS_INIT_BUSY_MASK 0x00000002
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_DPD_STATUS_INIT_BUSY_SHIFT 1
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_DPD_STATUS_INIT_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: EDC_DPD_STATUS :: INIT_DONE [00:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_DPD_STATUS_INIT_DONE_MASK 0x00000001
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_DPD_STATUS_INIT_DONE_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_DPD_STATUS_INIT_DONE_DEFAULT 0x00000000
-
-/***************************************************************************
- *EDC_DPD_OUT_CONTROL - GDDR5M EDC digital phase detector output signal control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_2_0 :: EDC_DPD_OUT_CONTROL :: reserved0 [31:20] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_DPD_OUT_CONTROL_reserved0_MASK 0xfff00000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_DPD_OUT_CONTROL_reserved0_SHIFT 20
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: EDC_DPD_OUT_CONTROL :: LOWER_LIMIT [19:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_DPD_OUT_CONTROL_LOWER_LIMIT_MASK 0x000ff000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_DPD_OUT_CONTROL_LOWER_LIMIT_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_DPD_OUT_CONTROL_LOWER_LIMIT_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: EDC_DPD_OUT_CONTROL :: UPPER_LIMIT [11:04] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_DPD_OUT_CONTROL_UPPER_LIMIT_MASK 0x00000ff0
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_DPD_OUT_CONTROL_UPPER_LIMIT_SHIFT 4
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_DPD_OUT_CONTROL_UPPER_LIMIT_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: EDC_DPD_OUT_CONTROL :: reserved1 [03:01] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_DPD_OUT_CONTROL_reserved1_MASK 0x0000000e
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_DPD_OUT_CONTROL_reserved1_SHIFT 1
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: EDC_DPD_OUT_CONTROL :: ENABLE [00:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_DPD_OUT_CONTROL_ENABLE_MASK 0x00000001
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_DPD_OUT_CONTROL_ENABLE_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_DPD_OUT_CONTROL_ENABLE_DEFAULT 0x00000000
-
-/***************************************************************************
- *EDC_DPD_OUT_STATUS - GDDR5M EDC digital phase detector output signal status register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_2_0 :: EDC_DPD_OUT_STATUS :: reserved0 [31:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_DPD_OUT_STATUS_reserved0_MASK 0xfffff000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_DPD_OUT_STATUS_reserved0_SHIFT 12
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: EDC_DPD_OUT_STATUS :: VDL_SETTING [11:04] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_DPD_OUT_STATUS_VDL_SETTING_MASK 0x00000ff0
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_DPD_OUT_STATUS_VDL_SETTING_SHIFT 4
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_DPD_OUT_STATUS_VDL_SETTING_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: EDC_DPD_OUT_STATUS :: reserved1 [03:01] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_DPD_OUT_STATUS_reserved1_MASK 0x0000000e
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_DPD_OUT_STATUS_reserved1_SHIFT 1
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: EDC_DPD_OUT_STATUS :: VALID [00:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_DPD_OUT_STATUS_VALID_MASK 0x00000001
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_DPD_OUT_STATUS_VALID_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_DPD_OUT_STATUS_VALID_DEFAULT 0x00000000
-
-/***************************************************************************
- *EDC_DPD_OUT_STATUS_CLEAR - GDDR5M EDC digital phase detector output signal status clear register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_2_0 :: EDC_DPD_OUT_STATUS_CLEAR :: reserved0 [31:01] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_DPD_OUT_STATUS_CLEAR_reserved0_MASK 0xfffffffe
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_DPD_OUT_STATUS_CLEAR_reserved0_SHIFT 1
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: EDC_DPD_OUT_STATUS_CLEAR :: CLEAR [00:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_DPD_OUT_STATUS_CLEAR_CLEAR_MASK 0x00000001
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_DPD_OUT_STATUS_CLEAR_CLEAR_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_DPD_OUT_STATUS_CLEAR_CLEAR_DEFAULT 0x00000000
-
-/***************************************************************************
- *EDC_CRC_CONTROL - GDDR5M EDC signal path CRC control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_2_0 :: EDC_CRC_CONTROL :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_CRC_CONTROL_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_CRC_CONTROL_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_CRC_CONTROL_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: EDC_CRC_CONTROL :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_CRC_CONTROL_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_CRC_CONTROL_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: EDC_CRC_CONTROL :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_CRC_CONTROL_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_CRC_CONTROL_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_CRC_CONTROL_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: EDC_CRC_CONTROL :: reserved1 [15:11] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_CRC_CONTROL_reserved1_MASK 0x0000f800
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_CRC_CONTROL_reserved1_SHIFT 11
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: EDC_CRC_CONTROL :: CRCWL [10:08] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_CRC_CONTROL_CRCWL_MASK 0x00000700
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_CRC_CONTROL_CRCWL_SHIFT 8
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_CRC_CONTROL_CRCWL_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: EDC_CRC_CONTROL :: reserved2 [07:06] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_CRC_CONTROL_reserved2_MASK 0x000000c0
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_CRC_CONTROL_reserved2_SHIFT 6
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: EDC_CRC_CONTROL :: CRCRL [05:04] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_CRC_CONTROL_CRCRL_MASK 0x00000030
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_CRC_CONTROL_CRCRL_SHIFT 4
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_CRC_CONTROL_CRCRL_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: EDC_CRC_CONTROL :: reserved3 [03:03] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_CRC_CONTROL_reserved3_MASK 0x00000008
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_CRC_CONTROL_reserved3_SHIFT 3
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: EDC_CRC_CONTROL :: COUNT_MODE [02:02] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_CRC_CONTROL_COUNT_MODE_MASK 0x00000004
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_CRC_CONTROL_COUNT_MODE_SHIFT 2
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_CRC_CONTROL_COUNT_MODE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: EDC_CRC_CONTROL :: ENABLE_WR [01:01] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_CRC_CONTROL_ENABLE_WR_MASK 0x00000002
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_CRC_CONTROL_ENABLE_WR_SHIFT 1
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_CRC_CONTROL_ENABLE_WR_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: EDC_CRC_CONTROL :: ENABLE_RD [00:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_CRC_CONTROL_ENABLE_RD_MASK 0x00000001
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_CRC_CONTROL_ENABLE_RD_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_CRC_CONTROL_ENABLE_RD_DEFAULT 0x00000000
-
-/***************************************************************************
- *EDC_CRC_STATUS - GDDR5M EDC signal path CRC status register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_2_0 :: EDC_CRC_STATUS :: reserved0 [31:04] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_CRC_STATUS_reserved0_MASK 0xfffffff0
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_CRC_STATUS_reserved0_SHIFT 4
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: EDC_CRC_STATUS :: WR_FAIL [03:03] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_CRC_STATUS_WR_FAIL_MASK 0x00000008
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_CRC_STATUS_WR_FAIL_SHIFT 3
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_CRC_STATUS_WR_FAIL_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: EDC_CRC_STATUS :: WR_PASS [02:02] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_CRC_STATUS_WR_PASS_MASK 0x00000004
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_CRC_STATUS_WR_PASS_SHIFT 2
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_CRC_STATUS_WR_PASS_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: EDC_CRC_STATUS :: RD_FAIL [01:01] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_CRC_STATUS_RD_FAIL_MASK 0x00000002
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_CRC_STATUS_RD_FAIL_SHIFT 1
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_CRC_STATUS_RD_FAIL_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: EDC_CRC_STATUS :: RD_PASS [00:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_CRC_STATUS_RD_PASS_MASK 0x00000001
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_CRC_STATUS_RD_PASS_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_CRC_STATUS_RD_PASS_DEFAULT 0x00000000
-
-/***************************************************************************
- *EDC_CRC_COUNT - GDDR5M EDC signal path CRC counter register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_2_0 :: EDC_CRC_COUNT :: reserved0 [31:28] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_CRC_COUNT_reserved0_MASK 0xf0000000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_CRC_COUNT_reserved0_SHIFT 28
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: EDC_CRC_COUNT :: WR_COUNT [27:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_CRC_COUNT_WR_COUNT_MASK 0x0fff0000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_CRC_COUNT_WR_COUNT_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_CRC_COUNT_WR_COUNT_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: EDC_CRC_COUNT :: reserved1 [15:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_CRC_COUNT_reserved1_MASK 0x0000f000
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_CRC_COUNT_reserved1_SHIFT 12
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: EDC_CRC_COUNT :: RD_COUNT [11:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_CRC_COUNT_RD_COUNT_MASK 0x00000fff
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_CRC_COUNT_RD_COUNT_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_CRC_COUNT_RD_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *EDC_CRC_STATUS_CLEAR - GDDR5M EDC signal path CRC counter register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_2_0 :: EDC_CRC_STATUS_CLEAR :: reserved0 [31:01] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_CRC_STATUS_CLEAR_reserved0_MASK 0xfffffffe
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_CRC_STATUS_CLEAR_reserved0_SHIFT 1
-
-/* DDR34_PHY_BYTE_LANE_2_0 :: EDC_CRC_STATUS_CLEAR :: CLEAR [00:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_CRC_STATUS_CLEAR_CLEAR_MASK 0x00000001
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_CRC_STATUS_CLEAR_CLEAR_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_CRC_STATUS_CLEAR_CLEAR_DEFAULT 0x00000000
-
-/***************************************************************************
- *BL_SPARE_REG - Byte-Lane Spare register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_2_0 :: BL_SPARE_REG :: reserved_for_eco0 [31:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_BL_SPARE_REG_reserved_for_eco0_MASK 0xffffffff
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_BL_SPARE_REG_reserved_for_eco0_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_2_0_BL_SPARE_REG_reserved_for_eco0_DEFAULT 0x00000000
-
-#endif /* #ifndef BCHP_DDR34_PHY_BYTE_LANE_2_0_H__ */
-
-/* End of File */
diff --git a/include/linux/brcmstb/7439a0/bchp_ddr34_phy_byte_lane_3_0.h b/include/linux/brcmstb/7439a0/bchp_ddr34_phy_byte_lane_3_0.h
deleted file mode 100644
index ec43204..0000000
--- a/include/linux/brcmstb/7439a0/bchp_ddr34_phy_byte_lane_3_0.h
+++ /dev/null
@@ -1,2099 +0,0 @@
-/***************************************************************************
- * Copyright (c) 1999-2013, Broadcom Corporation
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
- *
- * Module Description:
- * DO NOT EDIT THIS FILE DIRECTLY
- *
- * This module was generated magically with RDB from a source description
- * file. You must edit the source file for changes to be made to this file.
- *
- *
- * Date: Generated on Tue Apr 16 03:26:51 2013
- * MD5 Checksum d41d8cd98f00b204e9800998ecf8427e
- *
- * Compiled with: RDB Utility combo_header.pl
- * RDB Parser 3.0
- * unknown unknown
- * Perl Interpreter 5.008008
- * Operating System linux
- *
- * Revision History:
- *
- * $brcm_Log: $
- *
- ***************************************************************************/
-
-#ifndef BCHP_DDR34_PHY_BYTE_LANE_3_0_H__
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_H__
-
-/***************************************************************************
- *DDR34_PHY_BYTE_LANE_3_0 - 0 DDR34 DDR34 Byte Lane #3 control registers
- ***************************************************************************/
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQS_P 0x00906a00 /* Write channel DQS-P VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQS_N 0x00906a04 /* Write channel DQS-N VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ0 0x00906a08 /* Write channel DQ0 VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ1 0x00906a0c /* Write channel DQ1 VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ2 0x00906a10 /* Write channel DQ2 VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ3 0x00906a14 /* Write channel DQ3 VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ4 0x00906a18 /* Write channel DQ4 VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ5 0x00906a1c /* Write channel DQ5 VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ6 0x00906a20 /* Write channel DQ6 VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ7 0x00906a24 /* Write channel DQ7 VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DM 0x00906a28 /* Write channel DM VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_EDC 0x00906a2c /* Write channel EDC VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQSP 0x00906a30 /* Read channel DQSP VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQSN 0x00906a34 /* Read channel DQSP VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ0P 0x00906a38 /* Read channel DQ0-P VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ0N 0x00906a3c /* Read channel DQ0-N VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ1P 0x00906a40 /* Read channel DQ1-P VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ1N 0x00906a44 /* Read channel DQ1-N VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ2P 0x00906a48 /* Read channel DQ2-P VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ2N 0x00906a4c /* Read channel DQ2-N VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ3P 0x00906a50 /* Read channel DQ3-P VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ3N 0x00906a54 /* Read channel DQ3-N VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ4P 0x00906a58 /* Read channel DQ4-P VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ4N 0x00906a5c /* Read channel DQ4-N VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ5P 0x00906a60 /* Read channel DQ5-P VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ5N 0x00906a64 /* Read channel DQ5-N VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ6P 0x00906a68 /* Read channel DQ6-P VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ6N 0x00906a6c /* Read channel DQ6-N VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ7P 0x00906a70 /* Read channel DQ7-P VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ7N 0x00906a74 /* Read channel DQ7-N VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DMP 0x00906a78 /* Read channel DM-P VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DMN 0x00906a7c /* Read channel DM-N VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_EDCP 0x00906a80 /* Read channel EDC-P VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_EDCN 0x00906a84 /* Read channel EDC-N VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_EN_CS0 0x00906a88 /* Read channel CS_N[0] read enable VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_EN_CS1 0x00906a8c /* Read channel CS_N[1] read enable VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CLK_CONTROL 0x00906a90 /* DDR interface signal Write Leveling CLK VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_LDE_CONTROL 0x00906a94 /* DDR interface signal Write Leveling Capture Enable VDL control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_RD_EN_DLY_CYC 0x00906aa0 /* Read enable bit-clock cycle delay control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_WR_CHAN_DLY_CYC 0x00906aa4 /* Write leveling bit-clock cycle delay control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_READ_CONTROL 0x00906ab0 /* Read channel datapath control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_READ_FIFO_ADDR 0x00906ab4 /* Read fifo addresss pointer register */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_READ_FIFO_DATA 0x00906ab8 /* Read fifo data register */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_READ_FIFO_DM_DBI 0x00906abc /* Read fifo dm/dbi register */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_READ_FIFO_STATUS 0x00906ac0 /* Read fifo status register */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_READ_FIFO_CLEAR 0x00906ac4 /* Read fifo status clear register */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_IDLE_PAD_CONTROL 0x00906ac8 /* Idle mode SSTL pad control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_DRIVE_PAD_CTL 0x00906acc /* SSTL pad drive characteristics control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_RD_EN_DRIVE_PAD_CTL 0x00906ad0 /* SSTL read enable pad drive characteristics control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_STATIC_PAD_CTL 0x00906ad4 /* pad rx and tx characteristics control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_WR_PREAMBLE_MODE 0x00906ad8 /* Write cycle preamble control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_ODT_CONTROL 0x00906ae0 /* Read channel ODT control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_DPD_CONTROL 0x00906af0 /* GDDR5M EDC digital phase detector control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_DPD_STATUS 0x00906af4 /* GDDR5M EDC digital phase detector status register */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_DPD_OUT_CONTROL 0x00906af8 /* GDDR5M EDC digital phase detector output signal control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_DPD_OUT_STATUS 0x00906afc /* GDDR5M EDC digital phase detector output signal status register */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_DPD_OUT_STATUS_CLEAR 0x00906b00 /* GDDR5M EDC digital phase detector output signal status clear register */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_CRC_CONTROL 0x00906b04 /* GDDR5M EDC signal path CRC control register */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_CRC_STATUS 0x00906b08 /* GDDR5M EDC signal path CRC status register */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_CRC_COUNT 0x00906b0c /* GDDR5M EDC signal path CRC counter register */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_CRC_STATUS_CLEAR 0x00906b10 /* GDDR5M EDC signal path CRC counter register */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_BL_SPARE_REG 0x00906b14 /* Byte-Lane Spare register */
-
-/***************************************************************************
- *VDL_CONTROL_WR_DQS_P - Write channel DQS-P VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_WR_DQS_P :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQS_P_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQS_P_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQS_P_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_WR_DQS_P :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQS_P_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQS_P_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_WR_DQS_P :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQS_P_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQS_P_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQS_P_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_WR_DQS_P :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQS_P_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQS_P_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_WR_DQS_P :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQS_P_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQS_P_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQS_P_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_WR_DQS_P :: reserved2 [11:09] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQS_P_reserved2_MASK 0x00000e00
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQS_P_reserved2_SHIFT 9
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_WR_DQS_P :: VDL_STEP [08:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQS_P_VDL_STEP_MASK 0x000001ff
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQS_P_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQS_P_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_WR_DQS_N - Write channel DQS-N VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_WR_DQS_N :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQS_N_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQS_N_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQS_N_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_WR_DQS_N :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQS_N_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQS_N_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_WR_DQS_N :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQS_N_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQS_N_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQS_N_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_WR_DQS_N :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQS_N_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQS_N_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_WR_DQS_N :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQS_N_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQS_N_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQS_N_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_WR_DQS_N :: reserved2 [11:09] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQS_N_reserved2_MASK 0x00000e00
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQS_N_reserved2_SHIFT 9
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_WR_DQS_N :: VDL_STEP [08:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQS_N_VDL_STEP_MASK 0x000001ff
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQS_N_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQS_N_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_WR_DQ0 - Write channel DQ0 VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_WR_DQ0 :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ0_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ0_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ0_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_WR_DQ0 :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ0_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ0_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_WR_DQ0 :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ0_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ0_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ0_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_WR_DQ0 :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ0_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ0_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_WR_DQ0 :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ0_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ0_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ0_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_WR_DQ0 :: reserved2 [11:09] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ0_reserved2_MASK 0x00000e00
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ0_reserved2_SHIFT 9
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_WR_DQ0 :: VDL_STEP [08:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ0_VDL_STEP_MASK 0x000001ff
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ0_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ0_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_WR_DQ1 - Write channel DQ1 VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_WR_DQ1 :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ1_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ1_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ1_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_WR_DQ1 :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ1_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ1_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_WR_DQ1 :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ1_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ1_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ1_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_WR_DQ1 :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ1_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ1_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_WR_DQ1 :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ1_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ1_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ1_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_WR_DQ1 :: reserved2 [11:09] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ1_reserved2_MASK 0x00000e00
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ1_reserved2_SHIFT 9
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_WR_DQ1 :: VDL_STEP [08:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ1_VDL_STEP_MASK 0x000001ff
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ1_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ1_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_WR_DQ2 - Write channel DQ2 VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_WR_DQ2 :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ2_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ2_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ2_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_WR_DQ2 :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ2_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ2_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_WR_DQ2 :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ2_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ2_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ2_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_WR_DQ2 :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ2_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ2_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_WR_DQ2 :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ2_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ2_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ2_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_WR_DQ2 :: reserved2 [11:09] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ2_reserved2_MASK 0x00000e00
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ2_reserved2_SHIFT 9
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_WR_DQ2 :: VDL_STEP [08:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ2_VDL_STEP_MASK 0x000001ff
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ2_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ2_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_WR_DQ3 - Write channel DQ3 VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_WR_DQ3 :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ3_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ3_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ3_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_WR_DQ3 :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ3_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ3_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_WR_DQ3 :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ3_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ3_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ3_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_WR_DQ3 :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ3_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ3_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_WR_DQ3 :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ3_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ3_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ3_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_WR_DQ3 :: reserved2 [11:09] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ3_reserved2_MASK 0x00000e00
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ3_reserved2_SHIFT 9
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_WR_DQ3 :: VDL_STEP [08:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ3_VDL_STEP_MASK 0x000001ff
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ3_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ3_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_WR_DQ4 - Write channel DQ4 VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_WR_DQ4 :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ4_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ4_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ4_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_WR_DQ4 :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ4_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ4_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_WR_DQ4 :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ4_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ4_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ4_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_WR_DQ4 :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ4_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ4_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_WR_DQ4 :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ4_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ4_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ4_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_WR_DQ4 :: reserved2 [11:09] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ4_reserved2_MASK 0x00000e00
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ4_reserved2_SHIFT 9
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_WR_DQ4 :: VDL_STEP [08:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ4_VDL_STEP_MASK 0x000001ff
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ4_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ4_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_WR_DQ5 - Write channel DQ5 VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_WR_DQ5 :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ5_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ5_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ5_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_WR_DQ5 :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ5_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ5_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_WR_DQ5 :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ5_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ5_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ5_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_WR_DQ5 :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ5_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ5_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_WR_DQ5 :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ5_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ5_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ5_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_WR_DQ5 :: reserved2 [11:09] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ5_reserved2_MASK 0x00000e00
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ5_reserved2_SHIFT 9
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_WR_DQ5 :: VDL_STEP [08:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ5_VDL_STEP_MASK 0x000001ff
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ5_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ5_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_WR_DQ6 - Write channel DQ6 VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_WR_DQ6 :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ6_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ6_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ6_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_WR_DQ6 :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ6_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ6_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_WR_DQ6 :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ6_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ6_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ6_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_WR_DQ6 :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ6_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ6_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_WR_DQ6 :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ6_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ6_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ6_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_WR_DQ6 :: reserved2 [11:09] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ6_reserved2_MASK 0x00000e00
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ6_reserved2_SHIFT 9
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_WR_DQ6 :: VDL_STEP [08:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ6_VDL_STEP_MASK 0x000001ff
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ6_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ6_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_WR_DQ7 - Write channel DQ7 VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_WR_DQ7 :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ7_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ7_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ7_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_WR_DQ7 :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ7_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ7_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_WR_DQ7 :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ7_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ7_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ7_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_WR_DQ7 :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ7_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ7_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_WR_DQ7 :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ7_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ7_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ7_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_WR_DQ7 :: reserved2 [11:09] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ7_reserved2_MASK 0x00000e00
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ7_reserved2_SHIFT 9
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_WR_DQ7 :: VDL_STEP [08:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ7_VDL_STEP_MASK 0x000001ff
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ7_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ7_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_WR_DM - Write channel DM VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_WR_DM :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DM_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DM_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DM_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_WR_DM :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DM_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DM_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_WR_DM :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DM_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DM_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DM_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_WR_DM :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DM_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DM_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_WR_DM :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DM_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DM_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DM_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_WR_DM :: reserved2 [11:09] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DM_reserved2_MASK 0x00000e00
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DM_reserved2_SHIFT 9
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_WR_DM :: VDL_STEP [08:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DM_VDL_STEP_MASK 0x000001ff
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DM_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DM_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_WR_EDC - Write channel EDC VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_WR_EDC :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_EDC_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_EDC_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_EDC_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_WR_EDC :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_EDC_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_EDC_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_WR_EDC :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_EDC_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_EDC_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_EDC_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_WR_EDC :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_EDC_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_EDC_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_WR_EDC :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_EDC_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_EDC_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_EDC_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_WR_EDC :: reserved2 [11:09] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_EDC_reserved2_MASK 0x00000e00
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_EDC_reserved2_SHIFT 9
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_WR_EDC :: VDL_STEP [08:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_EDC_VDL_STEP_MASK 0x000001ff
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_EDC_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_EDC_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_RD_DQSP - Read channel DQSP VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_DQSP :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQSP_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQSP_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQSP_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_DQSP :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQSP_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQSP_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_DQSP :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQSP_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQSP_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQSP_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_DQSP :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQSP_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQSP_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_DQSP :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQSP_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQSP_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQSP_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_DQSP :: reserved2 [11:08] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQSP_reserved2_MASK 0x00000f00
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQSP_reserved2_SHIFT 8
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_DQSP :: VDL_STEP [07:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQSP_VDL_STEP_MASK 0x000000ff
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQSP_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQSP_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_RD_DQSN - Read channel DQSP VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_DQSN :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQSN_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQSN_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQSN_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_DQSN :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQSN_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQSN_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_DQSN :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQSN_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQSN_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQSN_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_DQSN :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQSN_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQSN_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_DQSN :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQSN_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQSN_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQSN_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_DQSN :: reserved2 [11:08] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQSN_reserved2_MASK 0x00000f00
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQSN_reserved2_SHIFT 8
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_DQSN :: VDL_STEP [07:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQSN_VDL_STEP_MASK 0x000000ff
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQSN_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQSN_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_RD_DQ0P - Read channel DQ0-P VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_DQ0P :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ0P_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ0P_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ0P_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_DQ0P :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ0P_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ0P_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_DQ0P :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ0P_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ0P_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ0P_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_DQ0P :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ0P_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ0P_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_DQ0P :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ0P_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ0P_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ0P_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_DQ0P :: reserved2 [11:08] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ0P_reserved2_MASK 0x00000f00
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ0P_reserved2_SHIFT 8
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_DQ0P :: VDL_STEP [07:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ0P_VDL_STEP_MASK 0x000000ff
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ0P_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ0P_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_RD_DQ0N - Read channel DQ0-N VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_DQ0N :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ0N_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ0N_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ0N_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_DQ0N :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ0N_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ0N_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_DQ0N :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ0N_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ0N_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ0N_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_DQ0N :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ0N_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ0N_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_DQ0N :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ0N_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ0N_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ0N_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_DQ0N :: reserved2 [11:08] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ0N_reserved2_MASK 0x00000f00
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ0N_reserved2_SHIFT 8
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_DQ0N :: VDL_STEP [07:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ0N_VDL_STEP_MASK 0x000000ff
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ0N_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ0N_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_RD_DQ1P - Read channel DQ1-P VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_DQ1P :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ1P_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ1P_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ1P_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_DQ1P :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ1P_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ1P_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_DQ1P :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ1P_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ1P_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ1P_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_DQ1P :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ1P_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ1P_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_DQ1P :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ1P_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ1P_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ1P_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_DQ1P :: reserved2 [11:08] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ1P_reserved2_MASK 0x00000f00
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ1P_reserved2_SHIFT 8
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_DQ1P :: VDL_STEP [07:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ1P_VDL_STEP_MASK 0x000000ff
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ1P_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ1P_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_RD_DQ1N - Read channel DQ1-N VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_DQ1N :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ1N_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ1N_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ1N_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_DQ1N :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ1N_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ1N_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_DQ1N :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ1N_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ1N_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ1N_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_DQ1N :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ1N_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ1N_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_DQ1N :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ1N_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ1N_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ1N_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_DQ1N :: reserved2 [11:08] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ1N_reserved2_MASK 0x00000f00
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ1N_reserved2_SHIFT 8
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_DQ1N :: VDL_STEP [07:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ1N_VDL_STEP_MASK 0x000000ff
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ1N_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ1N_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_RD_DQ2P - Read channel DQ2-P VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_DQ2P :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ2P_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ2P_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ2P_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_DQ2P :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ2P_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ2P_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_DQ2P :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ2P_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ2P_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ2P_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_DQ2P :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ2P_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ2P_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_DQ2P :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ2P_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ2P_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ2P_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_DQ2P :: reserved2 [11:08] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ2P_reserved2_MASK 0x00000f00
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ2P_reserved2_SHIFT 8
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_DQ2P :: VDL_STEP [07:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ2P_VDL_STEP_MASK 0x000000ff
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ2P_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ2P_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_RD_DQ2N - Read channel DQ2-N VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_DQ2N :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ2N_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ2N_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ2N_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_DQ2N :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ2N_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ2N_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_DQ2N :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ2N_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ2N_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ2N_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_DQ2N :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ2N_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ2N_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_DQ2N :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ2N_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ2N_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ2N_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_DQ2N :: reserved2 [11:08] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ2N_reserved2_MASK 0x00000f00
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ2N_reserved2_SHIFT 8
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_DQ2N :: VDL_STEP [07:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ2N_VDL_STEP_MASK 0x000000ff
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ2N_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ2N_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_RD_DQ3P - Read channel DQ3-P VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_DQ3P :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ3P_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ3P_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ3P_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_DQ3P :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ3P_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ3P_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_DQ3P :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ3P_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ3P_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ3P_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_DQ3P :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ3P_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ3P_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_DQ3P :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ3P_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ3P_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ3P_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_DQ3P :: reserved2 [11:08] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ3P_reserved2_MASK 0x00000f00
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ3P_reserved2_SHIFT 8
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_DQ3P :: VDL_STEP [07:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ3P_VDL_STEP_MASK 0x000000ff
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ3P_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ3P_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_RD_DQ3N - Read channel DQ3-N VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_DQ3N :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ3N_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ3N_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ3N_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_DQ3N :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ3N_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ3N_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_DQ3N :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ3N_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ3N_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ3N_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_DQ3N :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ3N_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ3N_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_DQ3N :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ3N_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ3N_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ3N_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_DQ3N :: reserved2 [11:08] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ3N_reserved2_MASK 0x00000f00
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ3N_reserved2_SHIFT 8
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_DQ3N :: VDL_STEP [07:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ3N_VDL_STEP_MASK 0x000000ff
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ3N_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ3N_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_RD_DQ4P - Read channel DQ4-P VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_DQ4P :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ4P_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ4P_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ4P_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_DQ4P :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ4P_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ4P_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_DQ4P :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ4P_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ4P_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ4P_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_DQ4P :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ4P_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ4P_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_DQ4P :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ4P_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ4P_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ4P_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_DQ4P :: reserved2 [11:08] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ4P_reserved2_MASK 0x00000f00
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ4P_reserved2_SHIFT 8
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_DQ4P :: VDL_STEP [07:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ4P_VDL_STEP_MASK 0x000000ff
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ4P_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ4P_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_RD_DQ4N - Read channel DQ4-N VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_DQ4N :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ4N_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ4N_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ4N_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_DQ4N :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ4N_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ4N_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_DQ4N :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ4N_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ4N_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ4N_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_DQ4N :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ4N_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ4N_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_DQ4N :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ4N_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ4N_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ4N_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_DQ4N :: reserved2 [11:08] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ4N_reserved2_MASK 0x00000f00
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ4N_reserved2_SHIFT 8
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_DQ4N :: VDL_STEP [07:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ4N_VDL_STEP_MASK 0x000000ff
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ4N_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ4N_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_RD_DQ5P - Read channel DQ5-P VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_DQ5P :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ5P_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ5P_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ5P_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_DQ5P :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ5P_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ5P_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_DQ5P :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ5P_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ5P_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ5P_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_DQ5P :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ5P_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ5P_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_DQ5P :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ5P_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ5P_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ5P_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_DQ5P :: reserved2 [11:08] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ5P_reserved2_MASK 0x00000f00
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ5P_reserved2_SHIFT 8
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_DQ5P :: VDL_STEP [07:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ5P_VDL_STEP_MASK 0x000000ff
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ5P_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ5P_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_RD_DQ5N - Read channel DQ5-N VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_DQ5N :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ5N_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ5N_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ5N_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_DQ5N :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ5N_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ5N_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_DQ5N :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ5N_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ5N_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ5N_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_DQ5N :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ5N_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ5N_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_DQ5N :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ5N_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ5N_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ5N_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_DQ5N :: reserved2 [11:08] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ5N_reserved2_MASK 0x00000f00
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ5N_reserved2_SHIFT 8
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_DQ5N :: VDL_STEP [07:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ5N_VDL_STEP_MASK 0x000000ff
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ5N_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ5N_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_RD_DQ6P - Read channel DQ6-P VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_DQ6P :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ6P_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ6P_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ6P_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_DQ6P :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ6P_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ6P_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_DQ6P :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ6P_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ6P_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ6P_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_DQ6P :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ6P_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ6P_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_DQ6P :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ6P_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ6P_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ6P_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_DQ6P :: reserved2 [11:08] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ6P_reserved2_MASK 0x00000f00
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ6P_reserved2_SHIFT 8
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_DQ6P :: VDL_STEP [07:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ6P_VDL_STEP_MASK 0x000000ff
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ6P_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ6P_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_RD_DQ6N - Read channel DQ6-N VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_DQ6N :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ6N_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ6N_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ6N_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_DQ6N :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ6N_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ6N_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_DQ6N :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ6N_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ6N_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ6N_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_DQ6N :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ6N_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ6N_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_DQ6N :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ6N_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ6N_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ6N_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_DQ6N :: reserved2 [11:08] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ6N_reserved2_MASK 0x00000f00
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ6N_reserved2_SHIFT 8
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_DQ6N :: VDL_STEP [07:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ6N_VDL_STEP_MASK 0x000000ff
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ6N_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ6N_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_RD_DQ7P - Read channel DQ7-P VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_DQ7P :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ7P_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ7P_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ7P_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_DQ7P :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ7P_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ7P_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_DQ7P :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ7P_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ7P_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ7P_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_DQ7P :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ7P_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ7P_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_DQ7P :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ7P_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ7P_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ7P_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_DQ7P :: reserved2 [11:08] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ7P_reserved2_MASK 0x00000f00
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ7P_reserved2_SHIFT 8
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_DQ7P :: VDL_STEP [07:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ7P_VDL_STEP_MASK 0x000000ff
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ7P_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ7P_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_RD_DQ7N - Read channel DQ7-N VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_DQ7N :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ7N_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ7N_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ7N_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_DQ7N :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ7N_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ7N_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_DQ7N :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ7N_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ7N_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ7N_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_DQ7N :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ7N_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ7N_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_DQ7N :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ7N_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ7N_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ7N_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_DQ7N :: reserved2 [11:08] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ7N_reserved2_MASK 0x00000f00
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ7N_reserved2_SHIFT 8
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_DQ7N :: VDL_STEP [07:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ7N_VDL_STEP_MASK 0x000000ff
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ7N_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ7N_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_RD_DMP - Read channel DM-P VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_DMP :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DMP_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DMP_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DMP_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_DMP :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DMP_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DMP_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_DMP :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DMP_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DMP_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DMP_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_DMP :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DMP_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DMP_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_DMP :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DMP_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DMP_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DMP_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_DMP :: reserved2 [11:08] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DMP_reserved2_MASK 0x00000f00
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DMP_reserved2_SHIFT 8
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_DMP :: VDL_STEP [07:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DMP_VDL_STEP_MASK 0x000000ff
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DMP_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DMP_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_RD_DMN - Read channel DM-N VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_DMN :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DMN_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DMN_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DMN_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_DMN :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DMN_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DMN_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_DMN :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DMN_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DMN_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DMN_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_DMN :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DMN_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DMN_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_DMN :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DMN_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DMN_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DMN_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_DMN :: reserved2 [11:08] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DMN_reserved2_MASK 0x00000f00
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DMN_reserved2_SHIFT 8
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_DMN :: VDL_STEP [07:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DMN_VDL_STEP_MASK 0x000000ff
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DMN_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DMN_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_RD_EDCP - Read channel EDC-P VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_EDCP :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_EDCP_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_EDCP_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_EDCP_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_EDCP :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_EDCP_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_EDCP_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_EDCP :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_EDCP_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_EDCP_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_EDCP_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_EDCP :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_EDCP_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_EDCP_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_EDCP :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_EDCP_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_EDCP_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_EDCP_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_EDCP :: reserved2 [11:08] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_EDCP_reserved2_MASK 0x00000f00
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_EDCP_reserved2_SHIFT 8
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_EDCP :: VDL_STEP [07:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_EDCP_VDL_STEP_MASK 0x000000ff
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_EDCP_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_EDCP_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_RD_EDCN - Read channel EDC-N VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_EDCN :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_EDCN_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_EDCN_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_EDCN_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_EDCN :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_EDCN_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_EDCN_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_EDCN :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_EDCN_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_EDCN_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_EDCN_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_EDCN :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_EDCN_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_EDCN_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_EDCN :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_EDCN_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_EDCN_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_EDCN_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_EDCN :: reserved2 [11:08] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_EDCN_reserved2_MASK 0x00000f00
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_EDCN_reserved2_SHIFT 8
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_EDCN :: VDL_STEP [07:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_EDCN_VDL_STEP_MASK 0x000000ff
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_EDCN_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_EDCN_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_RD_EN_CS0 - Read channel CS_N[0] read enable VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_EN_CS0 :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_EN_CS0_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_EN_CS0_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_EN_CS0_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_EN_CS0 :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_EN_CS0_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_EN_CS0_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_EN_CS0 :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_EN_CS0_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_EN_CS0_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_EN_CS0_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_EN_CS0 :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_EN_CS0_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_EN_CS0_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_EN_CS0 :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_EN_CS0_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_EN_CS0_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_EN_CS0_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_EN_CS0 :: reserved2 [11:08] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_EN_CS0_reserved2_MASK 0x00000f00
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_EN_CS0_reserved2_SHIFT 8
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_EN_CS0 :: VDL_STEP [07:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_EN_CS0_VDL_STEP_MASK 0x000000ff
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_EN_CS0_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_EN_CS0_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_RD_EN_CS1 - Read channel CS_N[1] read enable VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_EN_CS1 :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_EN_CS1_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_EN_CS1_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_EN_CS1_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_EN_CS1 :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_EN_CS1_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_EN_CS1_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_EN_CS1 :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_EN_CS1_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_EN_CS1_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_EN_CS1_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_EN_CS1 :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_EN_CS1_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_EN_CS1_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_EN_CS1 :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_EN_CS1_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_EN_CS1_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_EN_CS1_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_EN_CS1 :: reserved2 [11:08] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_EN_CS1_reserved2_MASK 0x00000f00
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_EN_CS1_reserved2_SHIFT 8
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_EN_CS1 :: VDL_STEP [07:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_EN_CS1_VDL_STEP_MASK 0x000000ff
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_EN_CS1_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_EN_CS1_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CLK_CONTROL - DDR interface signal Write Leveling CLK VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CLK_CONTROL :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CLK_CONTROL_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CLK_CONTROL_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CLK_CONTROL_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CLK_CONTROL :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CLK_CONTROL_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CLK_CONTROL_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CLK_CONTROL :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CLK_CONTROL_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CLK_CONTROL_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CLK_CONTROL_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CLK_CONTROL :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CLK_CONTROL_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CLK_CONTROL_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CLK_CONTROL :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CLK_CONTROL_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CLK_CONTROL_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CLK_CONTROL_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CLK_CONTROL :: reserved2 [11:09] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CLK_CONTROL_reserved2_MASK 0x00000e00
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CLK_CONTROL_reserved2_SHIFT 9
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CLK_CONTROL :: VDL_STEP [08:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CLK_CONTROL_VDL_STEP_MASK 0x000001ff
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CLK_CONTROL_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CLK_CONTROL_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_LDE_CONTROL - DDR interface signal Write Leveling Capture Enable VDL control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_LDE_CONTROL :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_LDE_CONTROL_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_LDE_CONTROL_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_LDE_CONTROL_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_LDE_CONTROL :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_LDE_CONTROL_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_LDE_CONTROL_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_LDE_CONTROL :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_LDE_CONTROL_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_LDE_CONTROL_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_LDE_CONTROL_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_LDE_CONTROL :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_LDE_CONTROL_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_LDE_CONTROL_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_LDE_CONTROL :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_LDE_CONTROL_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_LDE_CONTROL_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_LDE_CONTROL_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_LDE_CONTROL :: reserved2 [11:09] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_LDE_CONTROL_reserved2_MASK 0x00000e00
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_LDE_CONTROL_reserved2_SHIFT 9
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_LDE_CONTROL :: VDL_STEP [08:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_LDE_CONTROL_VDL_STEP_MASK 0x000001ff
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_LDE_CONTROL_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_LDE_CONTROL_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *RD_EN_DLY_CYC - Read enable bit-clock cycle delay control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_3_0 :: RD_EN_DLY_CYC :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_RD_EN_DLY_CYC_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_RD_EN_DLY_CYC_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_RD_EN_DLY_CYC_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: RD_EN_DLY_CYC :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_RD_EN_DLY_CYC_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_RD_EN_DLY_CYC_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: RD_EN_DLY_CYC :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_RD_EN_DLY_CYC_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_RD_EN_DLY_CYC_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_RD_EN_DLY_CYC_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: RD_EN_DLY_CYC :: reserved1 [15:08] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_RD_EN_DLY_CYC_reserved1_MASK 0x0000ff00
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_RD_EN_DLY_CYC_reserved1_SHIFT 8
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: RD_EN_DLY_CYC :: CS1_CYCLES [07:04] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_RD_EN_DLY_CYC_CS1_CYCLES_MASK 0x000000f0
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_RD_EN_DLY_CYC_CS1_CYCLES_SHIFT 4
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_RD_EN_DLY_CYC_CS1_CYCLES_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: RD_EN_DLY_CYC :: CS0_CYCLES [03:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_RD_EN_DLY_CYC_CS0_CYCLES_MASK 0x0000000f
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_RD_EN_DLY_CYC_CS0_CYCLES_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_RD_EN_DLY_CYC_CS0_CYCLES_DEFAULT 0x00000000
-
-/***************************************************************************
- *WR_CHAN_DLY_CYC - Write leveling bit-clock cycle delay control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_3_0 :: WR_CHAN_DLY_CYC :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_WR_CHAN_DLY_CYC_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_WR_CHAN_DLY_CYC_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_WR_CHAN_DLY_CYC_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: WR_CHAN_DLY_CYC :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_WR_CHAN_DLY_CYC_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_WR_CHAN_DLY_CYC_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: WR_CHAN_DLY_CYC :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_WR_CHAN_DLY_CYC_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_WR_CHAN_DLY_CYC_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_WR_CHAN_DLY_CYC_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: WR_CHAN_DLY_CYC :: reserved1 [15:03] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_WR_CHAN_DLY_CYC_reserved1_MASK 0x0000fff8
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_WR_CHAN_DLY_CYC_reserved1_SHIFT 3
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: WR_CHAN_DLY_CYC :: CYCLES [02:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_WR_CHAN_DLY_CYC_CYCLES_MASK 0x00000007
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_WR_CHAN_DLY_CYC_CYCLES_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_WR_CHAN_DLY_CYC_CYCLES_DEFAULT 0x00000000
-
-/***************************************************************************
- *READ_CONTROL - Read channel datapath control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_3_0 :: READ_CONTROL :: reserved0 [31:05] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_READ_CONTROL_reserved0_MASK 0xffffffe0
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_READ_CONTROL_reserved0_SHIFT 5
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: READ_CONTROL :: MODE [04:04] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_READ_CONTROL_MODE_MASK 0x00000010
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_READ_CONTROL_MODE_SHIFT 4
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_READ_CONTROL_MODE_DEFAULT 0x00000001
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: READ_CONTROL :: reserved1 [03:03] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_READ_CONTROL_reserved1_MASK 0x00000008
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_READ_CONTROL_reserved1_SHIFT 3
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: READ_CONTROL :: RD_DATA_DLY [02:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_READ_CONTROL_RD_DATA_DLY_MASK 0x00000007
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_READ_CONTROL_RD_DATA_DLY_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_READ_CONTROL_RD_DATA_DLY_DEFAULT 0x00000007
-
-/***************************************************************************
- *READ_FIFO_ADDR - Read fifo addresss pointer register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_3_0 :: READ_FIFO_ADDR :: reserved0 [31:03] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_READ_FIFO_ADDR_reserved0_MASK 0xfffffff8
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_READ_FIFO_ADDR_reserved0_SHIFT 3
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: READ_FIFO_ADDR :: ADDR [02:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_READ_FIFO_ADDR_ADDR_MASK 0x00000007
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_READ_FIFO_ADDR_ADDR_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_READ_FIFO_ADDR_ADDR_DEFAULT 0x00000000
-
-/***************************************************************************
- *READ_FIFO_DATA - Read fifo data register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_3_0 :: READ_FIFO_DATA :: DATA [31:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_READ_FIFO_DATA_DATA_MASK 0xffffffff
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_READ_FIFO_DATA_DATA_SHIFT 0
-
-/***************************************************************************
- *READ_FIFO_DM_DBI - Read fifo dm/dbi register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_3_0 :: READ_FIFO_DM_DBI :: reserved0 [31:04] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_READ_FIFO_DM_DBI_reserved0_MASK 0xfffffff0
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_READ_FIFO_DM_DBI_reserved0_SHIFT 4
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: READ_FIFO_DM_DBI :: DM_DBI [03:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_READ_FIFO_DM_DBI_DM_DBI_MASK 0x0000000f
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_READ_FIFO_DM_DBI_DM_DBI_SHIFT 0
-
-/***************************************************************************
- *READ_FIFO_STATUS - Read fifo status register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_3_0 :: READ_FIFO_STATUS :: reserved0 [31:02] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_READ_FIFO_STATUS_reserved0_MASK 0xfffffffc
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_READ_FIFO_STATUS_reserved0_SHIFT 2
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: READ_FIFO_STATUS :: OVERFLOW [01:01] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_READ_FIFO_STATUS_OVERFLOW_MASK 0x00000002
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_READ_FIFO_STATUS_OVERFLOW_SHIFT 1
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_READ_FIFO_STATUS_OVERFLOW_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: READ_FIFO_STATUS :: UNDERFLOW [00:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_READ_FIFO_STATUS_UNDERFLOW_MASK 0x00000001
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_READ_FIFO_STATUS_UNDERFLOW_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_READ_FIFO_STATUS_UNDERFLOW_DEFAULT 0x00000000
-
-/***************************************************************************
- *READ_FIFO_CLEAR - Read fifo status clear register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_3_0 :: READ_FIFO_CLEAR :: reserved0 [31:01] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_READ_FIFO_CLEAR_reserved0_MASK 0xfffffffe
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_READ_FIFO_CLEAR_reserved0_SHIFT 1
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: READ_FIFO_CLEAR :: CLEAR [00:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_READ_FIFO_CLEAR_CLEAR_MASK 0x00000001
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_READ_FIFO_CLEAR_CLEAR_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_READ_FIFO_CLEAR_CLEAR_DEFAULT 0x00000000
-
-/***************************************************************************
- *IDLE_PAD_CONTROL - Idle mode SSTL pad control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_3_0 :: IDLE_PAD_CONTROL :: IDLE [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_IDLE_PAD_CONTROL_IDLE_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_IDLE_PAD_CONTROL_IDLE_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_IDLE_PAD_CONTROL_IDLE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: IDLE_PAD_CONTROL :: reserved0 [30:20] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_IDLE_PAD_CONTROL_reserved0_MASK 0x7ff00000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_IDLE_PAD_CONTROL_reserved0_SHIFT 20
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: IDLE_PAD_CONTROL :: AUTO_DQ_RXENB_MODE [19:18] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_IDLE_PAD_CONTROL_AUTO_DQ_RXENB_MODE_MASK 0x000c0000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_IDLE_PAD_CONTROL_AUTO_DQ_RXENB_MODE_SHIFT 18
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_IDLE_PAD_CONTROL_AUTO_DQ_RXENB_MODE_DEFAULT 0x00000001
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: IDLE_PAD_CONTROL :: AUTO_DQ_IDDQ_MODE [17:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_IDLE_PAD_CONTROL_AUTO_DQ_IDDQ_MODE_MASK 0x00030000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_IDLE_PAD_CONTROL_AUTO_DQ_IDDQ_MODE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_IDLE_PAD_CONTROL_AUTO_DQ_IDDQ_MODE_DEFAULT 0x00000001
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: IDLE_PAD_CONTROL :: reserved_for_padding1 [15:15] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_IDLE_PAD_CONTROL_reserved_for_padding1_MASK 0x00008000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_IDLE_PAD_CONTROL_reserved_for_padding1_SHIFT 15
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: IDLE_PAD_CONTROL :: IO_IDLE_ENABLE [14:04] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_IDLE_PAD_CONTROL_IO_IDLE_ENABLE_MASK 0x00007ff0
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_IDLE_PAD_CONTROL_IO_IDLE_ENABLE_SHIFT 4
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_IDLE_PAD_CONTROL_IO_IDLE_ENABLE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: IDLE_PAD_CONTROL :: RXENB [03:03] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_IDLE_PAD_CONTROL_RXENB_MASK 0x00000008
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_IDLE_PAD_CONTROL_RXENB_SHIFT 3
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_IDLE_PAD_CONTROL_RXENB_DEFAULT 0x00000001
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: IDLE_PAD_CONTROL :: IDDQ [02:02] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_IDLE_PAD_CONTROL_IDDQ_MASK 0x00000004
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_IDLE_PAD_CONTROL_IDDQ_SHIFT 2
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_IDLE_PAD_CONTROL_IDDQ_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: IDLE_PAD_CONTROL :: DOUT_N [01:01] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_IDLE_PAD_CONTROL_DOUT_N_MASK 0x00000002
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_IDLE_PAD_CONTROL_DOUT_N_SHIFT 1
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: IDLE_PAD_CONTROL :: DOUT_P [00:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_IDLE_PAD_CONTROL_DOUT_P_MASK 0x00000001
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_IDLE_PAD_CONTROL_DOUT_P_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_IDLE_PAD_CONTROL_DOUT_P_DEFAULT 0x00000000
-
-/***************************************************************************
- *DRIVE_PAD_CTL - SSTL pad drive characteristics control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_3_0 :: DRIVE_PAD_CTL :: reserved0 [31:30] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_DRIVE_PAD_CTL_reserved0_MASK 0xc0000000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_DRIVE_PAD_CTL_reserved0_SHIFT 30
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: DRIVE_PAD_CTL :: BL_PD_IDLE_STRENGTH [29:25] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_DRIVE_PAD_CTL_BL_PD_IDLE_STRENGTH_MASK 0x3e000000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_DRIVE_PAD_CTL_BL_PD_IDLE_STRENGTH_SHIFT 25
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_DRIVE_PAD_CTL_BL_PD_IDLE_STRENGTH_DEFAULT 0x0000001f
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: DRIVE_PAD_CTL :: BL_ND_IDLE_STRENGTH [24:20] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_DRIVE_PAD_CTL_BL_ND_IDLE_STRENGTH_MASK 0x01f00000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_DRIVE_PAD_CTL_BL_ND_IDLE_STRENGTH_SHIFT 20
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_DRIVE_PAD_CTL_BL_ND_IDLE_STRENGTH_DEFAULT 0x0000001f
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: DRIVE_PAD_CTL :: BL_PD_TERM_STRENGTH [19:15] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_DRIVE_PAD_CTL_BL_PD_TERM_STRENGTH_MASK 0x000f8000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_DRIVE_PAD_CTL_BL_PD_TERM_STRENGTH_SHIFT 15
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_DRIVE_PAD_CTL_BL_PD_TERM_STRENGTH_DEFAULT 0x00000008
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: DRIVE_PAD_CTL :: BL_ND_TERM_STRENGTH [14:10] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_DRIVE_PAD_CTL_BL_ND_TERM_STRENGTH_MASK 0x00007c00
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_DRIVE_PAD_CTL_BL_ND_TERM_STRENGTH_SHIFT 10
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_DRIVE_PAD_CTL_BL_ND_TERM_STRENGTH_DEFAULT 0x00000008
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: DRIVE_PAD_CTL :: BL_PD_STRENGTH [09:05] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_DRIVE_PAD_CTL_BL_PD_STRENGTH_MASK 0x000003e0
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_DRIVE_PAD_CTL_BL_PD_STRENGTH_SHIFT 5
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_DRIVE_PAD_CTL_BL_PD_STRENGTH_DEFAULT 0x0000001f
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: DRIVE_PAD_CTL :: BL_ND_STRENGTH [04:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_DRIVE_PAD_CTL_BL_ND_STRENGTH_MASK 0x0000001f
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_DRIVE_PAD_CTL_BL_ND_STRENGTH_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_DRIVE_PAD_CTL_BL_ND_STRENGTH_DEFAULT 0x0000001f
-
-/***************************************************************************
- *RD_EN_DRIVE_PAD_CTL - SSTL read enable pad drive characteristics control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_3_0 :: RD_EN_DRIVE_PAD_CTL :: reserved0 [31:20] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_RD_EN_DRIVE_PAD_CTL_reserved0_MASK 0xfff00000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_RD_EN_DRIVE_PAD_CTL_reserved0_SHIFT 20
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: RD_EN_DRIVE_PAD_CTL :: EDC_RD_EN_PD_STRENGTH [19:15] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_RD_EN_DRIVE_PAD_CTL_EDC_RD_EN_PD_STRENGTH_MASK 0x000f8000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_RD_EN_DRIVE_PAD_CTL_EDC_RD_EN_PD_STRENGTH_SHIFT 15
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_RD_EN_DRIVE_PAD_CTL_EDC_RD_EN_PD_STRENGTH_DEFAULT 0x0000001f
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: RD_EN_DRIVE_PAD_CTL :: EDC_RD_EN_ND_STRENGTH [14:10] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_RD_EN_DRIVE_PAD_CTL_EDC_RD_EN_ND_STRENGTH_MASK 0x00007c00
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_RD_EN_DRIVE_PAD_CTL_EDC_RD_EN_ND_STRENGTH_SHIFT 10
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_RD_EN_DRIVE_PAD_CTL_EDC_RD_EN_ND_STRENGTH_DEFAULT 0x0000001f
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: RD_EN_DRIVE_PAD_CTL :: BL_RD_EN_PD_STRENGTH [09:05] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_RD_EN_DRIVE_PAD_CTL_BL_RD_EN_PD_STRENGTH_MASK 0x000003e0
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_RD_EN_DRIVE_PAD_CTL_BL_RD_EN_PD_STRENGTH_SHIFT 5
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_RD_EN_DRIVE_PAD_CTL_BL_RD_EN_PD_STRENGTH_DEFAULT 0x0000001f
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: RD_EN_DRIVE_PAD_CTL :: BL_RD_EN_ND_STRENGTH [04:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_RD_EN_DRIVE_PAD_CTL_BL_RD_EN_ND_STRENGTH_MASK 0x0000001f
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_RD_EN_DRIVE_PAD_CTL_BL_RD_EN_ND_STRENGTH_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_RD_EN_DRIVE_PAD_CTL_BL_RD_EN_ND_STRENGTH_DEFAULT 0x0000001f
-
-/***************************************************************************
- *STATIC_PAD_CTL - pad rx and tx characteristics control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_3_0 :: STATIC_PAD_CTL :: reserved0 [31:21] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_STATIC_PAD_CTL_reserved0_MASK 0xffe00000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_STATIC_PAD_CTL_reserved0_SHIFT 21
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: STATIC_PAD_CTL :: DQS_MODE [20:20] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_STATIC_PAD_CTL_DQS_MODE_MASK 0x00100000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_STATIC_PAD_CTL_DQS_MODE_SHIFT 20
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_STATIC_PAD_CTL_DQS_MODE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: STATIC_PAD_CTL :: reserved1 [19:18] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_STATIC_PAD_CTL_reserved1_MASK 0x000c0000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_STATIC_PAD_CTL_reserved1_SHIFT 18
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: STATIC_PAD_CTL :: EDC_MODE [17:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_STATIC_PAD_CTL_EDC_MODE_MASK 0x00030000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_STATIC_PAD_CTL_EDC_MODE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_STATIC_PAD_CTL_EDC_MODE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: STATIC_PAD_CTL :: reserved2 [15:15] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_STATIC_PAD_CTL_reserved2_MASK 0x00008000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_STATIC_PAD_CTL_reserved2_SHIFT 15
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: STATIC_PAD_CTL :: WDBI_ENABLE [14:14] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_STATIC_PAD_CTL_WDBI_ENABLE_MASK 0x00004000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_STATIC_PAD_CTL_WDBI_ENABLE_SHIFT 14
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_STATIC_PAD_CTL_WDBI_ENABLE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: STATIC_PAD_CTL :: RDBI_ENABLE [13:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_STATIC_PAD_CTL_RDBI_ENABLE_MASK 0x00002000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_STATIC_PAD_CTL_RDBI_ENABLE_SHIFT 13
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_STATIC_PAD_CTL_RDBI_ENABLE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: STATIC_PAD_CTL :: DM_MODE [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_STATIC_PAD_CTL_DM_MODE_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_STATIC_PAD_CTL_DM_MODE_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_STATIC_PAD_CTL_DM_MODE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: STATIC_PAD_CTL :: reserved3 [11:11] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_STATIC_PAD_CTL_reserved3_MASK 0x00000800
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_STATIC_PAD_CTL_reserved3_SHIFT 11
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: STATIC_PAD_CTL :: DQS_TX_PAUSE [10:10] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_STATIC_PAD_CTL_DQS_TX_PAUSE_MASK 0x00000400
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_STATIC_PAD_CTL_DQS_TX_PAUSE_SHIFT 10
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_STATIC_PAD_CTL_DQS_TX_PAUSE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: STATIC_PAD_CTL :: DQS_TX_DIS [09:09] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_STATIC_PAD_CTL_DQS_TX_DIS_MASK 0x00000200
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_STATIC_PAD_CTL_DQS_TX_DIS_SHIFT 9
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_STATIC_PAD_CTL_DQS_TX_DIS_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: STATIC_PAD_CTL :: reserved4 [08:08] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_STATIC_PAD_CTL_reserved4_MASK 0x00000100
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_STATIC_PAD_CTL_reserved4_SHIFT 8
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: STATIC_PAD_CTL :: TX_MODE [07:04] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_STATIC_PAD_CTL_TX_MODE_MASK 0x000000f0
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_STATIC_PAD_CTL_TX_MODE_SHIFT 4
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_STATIC_PAD_CTL_TX_MODE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: STATIC_PAD_CTL :: reserved5 [03:03] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_STATIC_PAD_CTL_reserved5_MASK 0x00000008
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_STATIC_PAD_CTL_reserved5_SHIFT 3
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: STATIC_PAD_CTL :: RX_MODE [02:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_STATIC_PAD_CTL_RX_MODE_MASK 0x00000007
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_STATIC_PAD_CTL_RX_MODE_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_STATIC_PAD_CTL_RX_MODE_DEFAULT 0x00000000
-
-/***************************************************************************
- *WR_PREAMBLE_MODE - Write cycle preamble control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_3_0 :: WR_PREAMBLE_MODE :: reserved0 [31:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_WR_PREAMBLE_MODE_reserved0_MASK 0xffff0000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_WR_PREAMBLE_MODE_reserved0_SHIFT 16
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: WR_PREAMBLE_MODE :: DQ_POSTAM_BITS [15:14] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_WR_PREAMBLE_MODE_DQ_POSTAM_BITS_MASK 0x0000c000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_WR_PREAMBLE_MODE_DQ_POSTAM_BITS_SHIFT 14
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_WR_PREAMBLE_MODE_DQ_POSTAM_BITS_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: WR_PREAMBLE_MODE :: DQ_PREAM_BITS [13:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_WR_PREAMBLE_MODE_DQ_PREAM_BITS_MASK 0x00003000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_WR_PREAMBLE_MODE_DQ_PREAM_BITS_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_WR_PREAMBLE_MODE_DQ_PREAM_BITS_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: WR_PREAMBLE_MODE :: DQS [11:08] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_WR_PREAMBLE_MODE_DQS_MASK 0x00000f00
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_WR_PREAMBLE_MODE_DQS_SHIFT 8
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_WR_PREAMBLE_MODE_DQS_DEFAULT 0x0000000e
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: WR_PREAMBLE_MODE :: reserved1 [07:05] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_WR_PREAMBLE_MODE_reserved1_MASK 0x000000e0
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_WR_PREAMBLE_MODE_reserved1_SHIFT 5
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: WR_PREAMBLE_MODE :: DQS_POSTAM_BITS [04:03] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_WR_PREAMBLE_MODE_DQS_POSTAM_BITS_MASK 0x00000018
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_WR_PREAMBLE_MODE_DQS_POSTAM_BITS_SHIFT 3
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_WR_PREAMBLE_MODE_DQS_POSTAM_BITS_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: WR_PREAMBLE_MODE :: DQS_PREAM_BITS [02:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_WR_PREAMBLE_MODE_DQS_PREAM_BITS_MASK 0x00000007
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_WR_PREAMBLE_MODE_DQS_PREAM_BITS_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_WR_PREAMBLE_MODE_DQS_PREAM_BITS_DEFAULT 0x00000002
-
-/***************************************************************************
- *ODT_CONTROL - Read channel ODT control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_3_0 :: ODT_CONTROL :: reserved_for_padding0 [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_ODT_CONTROL_reserved_for_padding0_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_ODT_CONTROL_reserved_for_padding0_SHIFT 31
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: ODT_CONTROL :: reserved1 [30:10] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_ODT_CONTROL_reserved1_MASK 0x7ffffc00
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_ODT_CONTROL_reserved1_SHIFT 10
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: ODT_CONTROL :: ODT_ENABLE [09:09] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_ODT_CONTROL_ODT_ENABLE_MASK 0x00000200
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_ODT_CONTROL_ODT_ENABLE_SHIFT 9
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_ODT_CONTROL_ODT_ENABLE_DEFAULT 0x00000001
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: ODT_CONTROL :: ODT_DELAY [08:06] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_ODT_CONTROL_ODT_DELAY_MASK 0x000001c0
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_ODT_CONTROL_ODT_DELAY_SHIFT 6
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_ODT_CONTROL_ODT_DELAY_DEFAULT 0x00000001
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: ODT_CONTROL :: ODT_POST_LENGTH [05:03] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_ODT_CONTROL_ODT_POST_LENGTH_MASK 0x00000038
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_ODT_CONTROL_ODT_POST_LENGTH_SHIFT 3
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_ODT_CONTROL_ODT_POST_LENGTH_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: ODT_CONTROL :: ODT_PRE_LENGTH [02:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_ODT_CONTROL_ODT_PRE_LENGTH_MASK 0x00000007
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_ODT_CONTROL_ODT_PRE_LENGTH_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_ODT_CONTROL_ODT_PRE_LENGTH_DEFAULT 0x00000003
-
-/***************************************************************************
- *EDC_DPD_CONTROL - GDDR5M EDC digital phase detector control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_3_0 :: EDC_DPD_CONTROL :: reserved0 [31:06] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_DPD_CONTROL_reserved0_MASK 0xffffffc0
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_DPD_CONTROL_reserved0_SHIFT 6
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: EDC_DPD_CONTROL :: DQS_PHASE_OVERRIDE_VALUE [05:05] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_DPD_CONTROL_DQS_PHASE_OVERRIDE_VALUE_MASK 0x00000020
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_DPD_CONTROL_DQS_PHASE_OVERRIDE_VALUE_SHIFT 5
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_DPD_CONTROL_DQS_PHASE_OVERRIDE_VALUE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: EDC_DPD_CONTROL :: DQS_PHASE_OVERRIDE_ENABLE [04:04] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_DPD_CONTROL_DQS_PHASE_OVERRIDE_ENABLE_MASK 0x00000010
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_DPD_CONTROL_DQS_PHASE_OVERRIDE_ENABLE_SHIFT 4
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_DPD_CONTROL_DQS_PHASE_OVERRIDE_ENABLE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: EDC_DPD_CONTROL :: SET_ADJ_EN [03:03] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_DPD_CONTROL_SET_ADJ_EN_MASK 0x00000008
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_DPD_CONTROL_SET_ADJ_EN_SHIFT 3
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_DPD_CONTROL_SET_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: EDC_DPD_CONTROL :: UPDATE [02:02] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_DPD_CONTROL_UPDATE_MASK 0x00000004
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_DPD_CONTROL_UPDATE_SHIFT 2
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_DPD_CONTROL_UPDATE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: EDC_DPD_CONTROL :: MONITOR [01:01] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_DPD_CONTROL_MONITOR_MASK 0x00000002
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_DPD_CONTROL_MONITOR_SHIFT 1
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_DPD_CONTROL_MONITOR_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: EDC_DPD_CONTROL :: INIT [00:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_DPD_CONTROL_INIT_MASK 0x00000001
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_DPD_CONTROL_INIT_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_DPD_CONTROL_INIT_DEFAULT 0x00000000
-
-/***************************************************************************
- *EDC_DPD_STATUS - GDDR5M EDC digital phase detector status register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_3_0 :: EDC_DPD_STATUS :: reserved0 [31:25] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_DPD_STATUS_reserved0_MASK 0xfe000000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_DPD_STATUS_reserved0_SHIFT 25
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: EDC_DPD_STATUS :: CURRENT_DQS_PHASE [24:24] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_DPD_STATUS_CURRENT_DQS_PHASE_MASK 0x01000000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_DPD_STATUS_CURRENT_DQS_PHASE_SHIFT 24
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_DPD_STATUS_CURRENT_DQS_PHASE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: EDC_DPD_STATUS :: CURRENT_VDL_SETTING [23:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_DPD_STATUS_CURRENT_VDL_SETTING_MASK 0x00ff0000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_DPD_STATUS_CURRENT_VDL_SETTING_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_DPD_STATUS_CURRENT_VDL_SETTING_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: EDC_DPD_STATUS :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_DPD_STATUS_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_DPD_STATUS_reserved1_SHIFT 13
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: EDC_DPD_STATUS :: INIT_DQS_PHASE [12:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_DPD_STATUS_INIT_DQS_PHASE_MASK 0x00001000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_DPD_STATUS_INIT_DQS_PHASE_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_DPD_STATUS_INIT_DQS_PHASE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: EDC_DPD_STATUS :: INIT_VDL_SETTING [11:04] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_DPD_STATUS_INIT_VDL_SETTING_MASK 0x00000ff0
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_DPD_STATUS_INIT_VDL_SETTING_SHIFT 4
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_DPD_STATUS_INIT_VDL_SETTING_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: EDC_DPD_STATUS :: EDGE_ERROR [03:03] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_DPD_STATUS_EDGE_ERROR_MASK 0x00000008
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_DPD_STATUS_EDGE_ERROR_SHIFT 3
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_DPD_STATUS_EDGE_ERROR_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: EDC_DPD_STATUS :: MONITOR_BUSY [02:02] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_DPD_STATUS_MONITOR_BUSY_MASK 0x00000004
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_DPD_STATUS_MONITOR_BUSY_SHIFT 2
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_DPD_STATUS_MONITOR_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: EDC_DPD_STATUS :: INIT_BUSY [01:01] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_DPD_STATUS_INIT_BUSY_MASK 0x00000002
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_DPD_STATUS_INIT_BUSY_SHIFT 1
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_DPD_STATUS_INIT_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: EDC_DPD_STATUS :: INIT_DONE [00:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_DPD_STATUS_INIT_DONE_MASK 0x00000001
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_DPD_STATUS_INIT_DONE_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_DPD_STATUS_INIT_DONE_DEFAULT 0x00000000
-
-/***************************************************************************
- *EDC_DPD_OUT_CONTROL - GDDR5M EDC digital phase detector output signal control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_3_0 :: EDC_DPD_OUT_CONTROL :: reserved0 [31:20] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_DPD_OUT_CONTROL_reserved0_MASK 0xfff00000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_DPD_OUT_CONTROL_reserved0_SHIFT 20
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: EDC_DPD_OUT_CONTROL :: LOWER_LIMIT [19:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_DPD_OUT_CONTROL_LOWER_LIMIT_MASK 0x000ff000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_DPD_OUT_CONTROL_LOWER_LIMIT_SHIFT 12
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_DPD_OUT_CONTROL_LOWER_LIMIT_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: EDC_DPD_OUT_CONTROL :: UPPER_LIMIT [11:04] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_DPD_OUT_CONTROL_UPPER_LIMIT_MASK 0x00000ff0
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_DPD_OUT_CONTROL_UPPER_LIMIT_SHIFT 4
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_DPD_OUT_CONTROL_UPPER_LIMIT_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: EDC_DPD_OUT_CONTROL :: reserved1 [03:01] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_DPD_OUT_CONTROL_reserved1_MASK 0x0000000e
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_DPD_OUT_CONTROL_reserved1_SHIFT 1
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: EDC_DPD_OUT_CONTROL :: ENABLE [00:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_DPD_OUT_CONTROL_ENABLE_MASK 0x00000001
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_DPD_OUT_CONTROL_ENABLE_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_DPD_OUT_CONTROL_ENABLE_DEFAULT 0x00000000
-
-/***************************************************************************
- *EDC_DPD_OUT_STATUS - GDDR5M EDC digital phase detector output signal status register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_3_0 :: EDC_DPD_OUT_STATUS :: reserved0 [31:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_DPD_OUT_STATUS_reserved0_MASK 0xfffff000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_DPD_OUT_STATUS_reserved0_SHIFT 12
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: EDC_DPD_OUT_STATUS :: VDL_SETTING [11:04] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_DPD_OUT_STATUS_VDL_SETTING_MASK 0x00000ff0
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_DPD_OUT_STATUS_VDL_SETTING_SHIFT 4
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_DPD_OUT_STATUS_VDL_SETTING_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: EDC_DPD_OUT_STATUS :: reserved1 [03:01] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_DPD_OUT_STATUS_reserved1_MASK 0x0000000e
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_DPD_OUT_STATUS_reserved1_SHIFT 1
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: EDC_DPD_OUT_STATUS :: VALID [00:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_DPD_OUT_STATUS_VALID_MASK 0x00000001
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_DPD_OUT_STATUS_VALID_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_DPD_OUT_STATUS_VALID_DEFAULT 0x00000000
-
-/***************************************************************************
- *EDC_DPD_OUT_STATUS_CLEAR - GDDR5M EDC digital phase detector output signal status clear register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_3_0 :: EDC_DPD_OUT_STATUS_CLEAR :: reserved0 [31:01] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_DPD_OUT_STATUS_CLEAR_reserved0_MASK 0xfffffffe
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_DPD_OUT_STATUS_CLEAR_reserved0_SHIFT 1
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: EDC_DPD_OUT_STATUS_CLEAR :: CLEAR [00:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_DPD_OUT_STATUS_CLEAR_CLEAR_MASK 0x00000001
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_DPD_OUT_STATUS_CLEAR_CLEAR_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_DPD_OUT_STATUS_CLEAR_CLEAR_DEFAULT 0x00000000
-
-/***************************************************************************
- *EDC_CRC_CONTROL - GDDR5M EDC signal path CRC control register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_3_0 :: EDC_CRC_CONTROL :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_CRC_CONTROL_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_CRC_CONTROL_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_CRC_CONTROL_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: EDC_CRC_CONTROL :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_CRC_CONTROL_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_CRC_CONTROL_reserved0_SHIFT 17
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: EDC_CRC_CONTROL :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_CRC_CONTROL_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_CRC_CONTROL_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_CRC_CONTROL_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: EDC_CRC_CONTROL :: reserved1 [15:11] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_CRC_CONTROL_reserved1_MASK 0x0000f800
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_CRC_CONTROL_reserved1_SHIFT 11
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: EDC_CRC_CONTROL :: CRCWL [10:08] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_CRC_CONTROL_CRCWL_MASK 0x00000700
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_CRC_CONTROL_CRCWL_SHIFT 8
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_CRC_CONTROL_CRCWL_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: EDC_CRC_CONTROL :: reserved2 [07:06] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_CRC_CONTROL_reserved2_MASK 0x000000c0
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_CRC_CONTROL_reserved2_SHIFT 6
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: EDC_CRC_CONTROL :: CRCRL [05:04] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_CRC_CONTROL_CRCRL_MASK 0x00000030
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_CRC_CONTROL_CRCRL_SHIFT 4
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_CRC_CONTROL_CRCRL_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: EDC_CRC_CONTROL :: reserved3 [03:03] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_CRC_CONTROL_reserved3_MASK 0x00000008
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_CRC_CONTROL_reserved3_SHIFT 3
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: EDC_CRC_CONTROL :: COUNT_MODE [02:02] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_CRC_CONTROL_COUNT_MODE_MASK 0x00000004
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_CRC_CONTROL_COUNT_MODE_SHIFT 2
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_CRC_CONTROL_COUNT_MODE_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: EDC_CRC_CONTROL :: ENABLE_WR [01:01] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_CRC_CONTROL_ENABLE_WR_MASK 0x00000002
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_CRC_CONTROL_ENABLE_WR_SHIFT 1
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_CRC_CONTROL_ENABLE_WR_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: EDC_CRC_CONTROL :: ENABLE_RD [00:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_CRC_CONTROL_ENABLE_RD_MASK 0x00000001
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_CRC_CONTROL_ENABLE_RD_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_CRC_CONTROL_ENABLE_RD_DEFAULT 0x00000000
-
-/***************************************************************************
- *EDC_CRC_STATUS - GDDR5M EDC signal path CRC status register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_3_0 :: EDC_CRC_STATUS :: reserved0 [31:04] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_CRC_STATUS_reserved0_MASK 0xfffffff0
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_CRC_STATUS_reserved0_SHIFT 4
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: EDC_CRC_STATUS :: WR_FAIL [03:03] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_CRC_STATUS_WR_FAIL_MASK 0x00000008
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_CRC_STATUS_WR_FAIL_SHIFT 3
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_CRC_STATUS_WR_FAIL_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: EDC_CRC_STATUS :: WR_PASS [02:02] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_CRC_STATUS_WR_PASS_MASK 0x00000004
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_CRC_STATUS_WR_PASS_SHIFT 2
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_CRC_STATUS_WR_PASS_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: EDC_CRC_STATUS :: RD_FAIL [01:01] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_CRC_STATUS_RD_FAIL_MASK 0x00000002
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_CRC_STATUS_RD_FAIL_SHIFT 1
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_CRC_STATUS_RD_FAIL_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: EDC_CRC_STATUS :: RD_PASS [00:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_CRC_STATUS_RD_PASS_MASK 0x00000001
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_CRC_STATUS_RD_PASS_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_CRC_STATUS_RD_PASS_DEFAULT 0x00000000
-
-/***************************************************************************
- *EDC_CRC_COUNT - GDDR5M EDC signal path CRC counter register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_3_0 :: EDC_CRC_COUNT :: reserved0 [31:28] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_CRC_COUNT_reserved0_MASK 0xf0000000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_CRC_COUNT_reserved0_SHIFT 28
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: EDC_CRC_COUNT :: WR_COUNT [27:16] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_CRC_COUNT_WR_COUNT_MASK 0x0fff0000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_CRC_COUNT_WR_COUNT_SHIFT 16
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_CRC_COUNT_WR_COUNT_DEFAULT 0x00000000
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: EDC_CRC_COUNT :: reserved1 [15:12] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_CRC_COUNT_reserved1_MASK 0x0000f000
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_CRC_COUNT_reserved1_SHIFT 12
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: EDC_CRC_COUNT :: RD_COUNT [11:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_CRC_COUNT_RD_COUNT_MASK 0x00000fff
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_CRC_COUNT_RD_COUNT_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_CRC_COUNT_RD_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *EDC_CRC_STATUS_CLEAR - GDDR5M EDC signal path CRC counter register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_3_0 :: EDC_CRC_STATUS_CLEAR :: reserved0 [31:01] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_CRC_STATUS_CLEAR_reserved0_MASK 0xfffffffe
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_CRC_STATUS_CLEAR_reserved0_SHIFT 1
-
-/* DDR34_PHY_BYTE_LANE_3_0 :: EDC_CRC_STATUS_CLEAR :: CLEAR [00:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_CRC_STATUS_CLEAR_CLEAR_MASK 0x00000001
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_CRC_STATUS_CLEAR_CLEAR_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_CRC_STATUS_CLEAR_CLEAR_DEFAULT 0x00000000
-
-/***************************************************************************
- *BL_SPARE_REG - Byte-Lane Spare register
- ***************************************************************************/
-/* DDR34_PHY_BYTE_LANE_3_0 :: BL_SPARE_REG :: reserved_for_eco0 [31:00] */
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_BL_SPARE_REG_reserved_for_eco0_MASK 0xffffffff
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_BL_SPARE_REG_reserved_for_eco0_SHIFT 0
-#define BCHP_DDR34_PHY_BYTE_LANE_3_0_BL_SPARE_REG_reserved_for_eco0_DEFAULT 0x00000000
-
-#endif /* #ifndef BCHP_DDR34_PHY_BYTE_LANE_3_0_H__ */
-
-/* End of File */
diff --git a/include/linux/brcmstb/7439a0/bchp_ddr34_phy_control_regs_0.h b/include/linux/brcmstb/7439a0/bchp_ddr34_phy_control_regs_0.h
deleted file mode 100644
index 59176bd..0000000
--- a/include/linux/brcmstb/7439a0/bchp_ddr34_phy_control_regs_0.h
+++ /dev/null
@@ -1,4232 +0,0 @@
-/***************************************************************************
- * Copyright (c) 1999-2013, Broadcom Corporation
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
- *
- * Module Description:
- * DO NOT EDIT THIS FILE DIRECTLY
- *
- * This module was generated magically with RDB from a source description
- * file. You must edit the source file for changes to be made to this file.
- *
- *
- * Date: Generated on Tue Apr 16 03:26:50 2013
- * MD5 Checksum d41d8cd98f00b204e9800998ecf8427e
- *
- * Compiled with: RDB Utility combo_header.pl
- * RDB Parser 3.0
- * unknown unknown
- * Perl Interpreter 5.008008
- * Operating System linux
- *
- * Revision History:
- *
- * $brcm_Log: $
- *
- ***************************************************************************/
-
-#ifndef BCHP_DDR34_PHY_CONTROL_REGS_0_H__
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_H__
-
-/***************************************************************************
- *DDR34_PHY_CONTROL_REGS_0 - 0 DDR34 DDR34 Address/Comand control registers
- ***************************************************************************/
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_REVISION 0x00906000 /* Address & Control revision register */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_STATUS 0x00906004 /* PHY PLL status register */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_CONFIG 0x00906008 /* PHY PLL configuration register */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_CONTROL1 0x0090600c /* PHY PLL control register */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_CONTROL2 0x00906010 /* PHY PLL control register */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_CONTROL3 0x00906014 /* PHY PLL control register */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_DIVIDERS 0x00906018 /* PHY PLL integer divider register */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_FRAC_DIVIDER 0x0090601c /* PHY PLL fractional divider register */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_SS_CONTROL 0x00906020 /* PHY PLL spread spectrum control register */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_SS_LIMIT 0x00906024 /* PHY PLL spread spectrum limit register */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_AUX_CONTROL 0x00906028 /* Aux Control register */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL 0x0090602c /* Idle mode pad control register */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_IDLE_PAD_ENABLE0 0x00906030 /* Idle mode pad enable register */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_IDLE_PAD_ENABLE1 0x00906034 /* Idle mode pad enable register */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL 0x00906038 /* PVT Compensation control register */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_STATIC_PAD_CTL 0x0090603c /* pad rx and tx characteristics control register */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_DRAM_CONFIG 0x00906040 /* DRAM configuration register */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_DRAM_TIMING1 0x00906044 /* DRAM timing register #1 */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_DRAM_TIMING2 0x00906048 /* DRAM timing register #2 */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_DRAM_TIMING3 0x0090604c /* DRAM timing register #3 */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_DRAM_TIMING4 0x00906050 /* DRAM timing register #4 */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CALIBRATE 0x00906060 /* PHY VDL calibration control register */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS1 0x00906064 /* PHY VDL calibration status register #1 */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS2 0x00906068 /* PHY VDL calibration status register #2 */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_MONITOR_CONTROL 0x0090606c /* PHY VDL delay monitoring control register */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_MONITOR_REF 0x00906070 /* PHY VDL delay monitoring reference register */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_MONITOR_STATUS 0x00906074 /* PHY VDL delay monitoring status register */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_MONITOR_OVERRIDE 0x00906078 /* PHY VDL delay monitoring override register */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_MONITOR_OUT_CONTROL 0x0090607c /* PHY VDL delay monitoring output control register */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_MONITOR_OUT_STATUS 0x00906080 /* PHY VDL delay monitoring output status register */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_MONITOR_OUT_STATUS_CLEAR 0x00906084 /* PHY VDL delay monitoring output status clear register */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD00 0x00906090 /* DDR interface signal AD[00] VDL control register */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD01 0x00906094 /* DDR interface signal AD[01] VDL control register */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD02 0x00906098 /* DDR interface signal AD[02] VDL control register */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD03 0x0090609c /* DDR interface signal AD[03] VDL control register */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD04 0x009060a0 /* DDR interface signal AD[04] VDL control register */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD05 0x009060a4 /* DDR interface signal AD[05] VDL control register */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD06 0x009060a8 /* DDR interface signal AD[06] VDL control register */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD07 0x009060ac /* DDR interface signal AD[07] VDL control register */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD08 0x009060b0 /* DDR interface signal AD[08] VDL control register */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD09 0x009060b4 /* DDR interface signal AD[09] VDL control register */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD10 0x009060b8 /* DDR interface signal AD[10] VDL control register */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD11 0x009060bc /* DDR interface signal AD[11] VDL control register */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD12 0x009060c0 /* DDR interface signal AD[12] VDL control register */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD13 0x009060c4 /* DDR interface signal AD[13] VDL control register */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD14 0x009060c8 /* DDR interface signal AD[14] VDL control register */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD15 0x009060cc /* DDR interface signal AD[15] VDL control register */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_BA0 0x009060d0 /* DDR interface signal BA[0] VDL control register */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_BA1 0x009060d4 /* DDR interface signal BA[1] VDL control register */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_BA2 0x009060d8 /* DDR interface signal BA[2] VDL control register */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AUX0 0x009060dc /* DDR interface signal AUX[0] VDL control register */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AUX1 0x009060e0 /* DDR interface signal AUX[1] VDL control register */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AUX2 0x009060e4 /* DDR interface signal AUX[2] VDL control register */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_CS0 0x009060e8 /* DDR interface signal CS0 VDL control register */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_CS1 0x009060ec /* DDR interface signal CS1 VDL control register */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_PAR 0x009060f0 /* DDR interface signal PAR VDL control register */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_RAS_N 0x009060f4 /* DDR interface signal RAS_N VDL control register */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_CAS_N 0x009060f8 /* DDR interface signal CAS_N VDL control register */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_CKE 0x009060fc /* DDR interface signal CKE0 VDL control register */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_RST_N 0x00906100 /* DDR interface signal RST_N VDL control register */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_ODT 0x00906104 /* DDR interface signal ODT0 VDL control register */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_WE_N 0x00906108 /* DDR interface signal WE_N VDL control register */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_DDR_CK_P 0x0090610c /* DDR interface signal DDR_CK-P VDL control register */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_DDR_CK_N 0x00906110 /* DDR interface signal DDR_CK-N VDL control register */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CLK_CONTROL 0x00906114 /* DDR interface signal Write Leveling CLK VDL control register */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_LDE_CONTROL 0x00906118 /* DDR interface signal Write Leveling Capture Enable VDL control register */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_REFRESH 0x00906130 /* Refresh engine controller */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_UPDATE_VDL 0x00906134 /* Update VDL control register */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_UPDATE_VDL_SNOOP1 0x00906138 /* Update VDL snoop control register #1 */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_UPDATE_VDL_SNOOP2 0x0090613c /* Update VDL snoop control register #2 */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_REG1 0x00906140 /* DRAM Command Register #1 */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_AUX_REG1 0x00906144 /* DRAM AUX_N Command Register #1 */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_REG2 0x00906148 /* DRAM Command Register #2 */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_AUX_REG2 0x0090614c /* DRAM AUX_N Command Register #2 */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_REG3 0x00906150 /* DRAM Command Register #3 */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_AUX_REG3 0x00906154 /* DRAM AUX_N Command Register #3 */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_REG4 0x00906158 /* DRAM Command Register #4 */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_AUX_REG4 0x0090615c /* DRAM AUX_N Command Register #4 */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_REG_TIMER 0x00906160 /* DRAM Command Timer Register */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_MODE_REG0 0x00906164 /* DDR3/DDR4/GDDR5 Mode Register 0 and LPDDR Mode Register 1 */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_MODE_REG1 0x00906168 /* DDR3/DDR4/GDDR5 Mode Register 1 and LPDDR Mode Register 2 */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_MODE_REG2 0x0090616c /* DDR3/DDR4/GDDR5 Mode Register 2 and LPDDR Mode Register 3 */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_MODE_REG3 0x00906170 /* DDR3/DDR4/GDDR5 Mode Register 3 and LPDDR Mode Register 9 */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_MODE_REG4 0x00906174 /* DDR4/GDDR5 Mode Register 4 and LPDDR Mode Register 10 */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_MODE_REG5 0x00906178 /* DDR4/GDDR5 Mode Register 5 and LPDDR Mode Register 16 */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_MODE_REG6 0x0090617c /* DDR4/GDDR5 Mode Register 6 and LPDDR Mode Register 17 */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_MODE_REG7 0x00906180 /* DDR4/GDDR5 Mode Register 7 and LPDDR Mode Register 41 */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_MODE_REG8 0x00906184 /* GDDR5 Mode Register 8 and LPDDR Mode Register 42 */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_MODE_REG15 0x00906188 /* GDDR5 Mode Register 15 and LPDDR Mode Register 48 */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_MODE_REG63 0x0090618c /* LPDDR Mode Register 63 */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_ALERT_CLEAR 0x00906190 /* DDR4 Alert status clear register */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_ALERT_STATUS 0x00906194 /* DDR4 Alert status register */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_CA_PARITY 0x00906198 /* DDR4 CA parity control register */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_CA_PLAYBACK_CONTROL 0x0090619c /* GDDR5 CA playback control register */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_CA_PLAYBACK_STATUS0 0x009061a0 /* LPDDR3 and GDDR5 CA playback status register0 (for BL0 and BL1) */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_CA_PLAYBACK_STATUS1 0x009061a4 /* LPDDR3 and GDDR5 CA playback status register1 (for BL2 and BL3) */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_WRITE_LEVELING_CONTROL 0x009061ac /* Write leveling control register */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_WRITE_LEVELING_STATUS 0x009061b0 /* Write leveling status register */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_READ_ENABLE_CONTROL 0x009061b4 /* Read enable test cycle control register */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_READ_ENABLE_STATUS 0x009061b8 /* Read enable test cycle status register */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_TRAFFIC_GEN_LFSR_SEED 0x009061c0 /* Traffic generator seed register */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_TRAFFIC_GEN_ADDRESS1 0x009061c4 /* Traffic generator address register #1 */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_TRAFFIC_GEN_ADDRESS2 0x009061c8 /* Traffic generator address register #2 */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_TRAFFIC_GEN_CONTROL 0x009061cc /* Traffic generator control register */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_TRAFFIC_GEN_DATA_CONTROL 0x009061d0 /* Traffic generator data control register */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_TRAFFIC_GEN_DQ_MASK 0x009061d4 /* Traffic generator DQ mask register */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_TRAFFIC_GEN_ECC_DQ_MASK 0x009061d8 /* Traffic generator ECC DQ mask register */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_TRAFFIC_GEN_STATUS 0x009061dc /* Traffic generator status register */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_TRAFFIC_GEN_DQ_STATUS 0x009061e0 /* Traffic generator DQ status register */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_TRAFFIC_GEN_ECC_STATUS 0x009061e4 /* Traffic generator ECC DQ status register */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_TRAFFIC_GEN_ERR_CNT_CONTROL 0x009061e8 /* Traffic generator error count control register */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_TRAFFIC_GEN_ERR_CNT_STATUS 0x009061ec /* Traffic generator error count status register */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONTROL 0x009061f0 /* Virtual VTT Control and Status register */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VIRTUAL_VTT_STATUS 0x009061f4 /* Virtual VTT Control and Status register */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONNECTIONS 0x009061f8 /* Virtual VTT Connections register */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VIRTUAL_VTT_OVERRIDE 0x009061fc /* Virtual VTT Override register */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL 0x00906200 /* VREF DAC Control register */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PHYBIST_CNTRL 0x00906204 /* PhyBist Control Register */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PHYBIST_SEED 0x00906208 /* PhyBist Seed Register */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PHYBIST_STATUS 0x0090620c /* PhyBist General Status Register */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PHYBIST_CTL_STATUS 0x00906210 /* PhyBist Per-Bit Control Pad Status Register */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PHYBIST_BL0_STATUS 0x00906214 /* PhyBist Byte Lane #0 Status Register */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PHYBIST_BL1_STATUS 0x00906218 /* PhyBist Byte Lane #1 Status Register */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PHYBIST_BL2_STATUS 0x0090621c /* PhyBist Byte Lane #2 Status Register */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PHYBIST_BL3_STATUS 0x00906220 /* PhyBist Byte Lane #3 Status Register */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PHYBIST_BL4_STATUS 0x00906224 /* PhyBist Byte Lane #4 (ECC) Status Register */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_STANDBY_CONTROL 0x00906230 /* Standby Control register */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_DEBUG_FREEZE_ENABLE 0x00906234 /* Freeze-on-error enable register */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_DEBUG_MUX_CONTROL 0x00906238 /* Debug Mux Control register */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_DFI_CNTRL 0x0090623c /* DFI Interface Ownership Control register */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_WRITE_ODT_CNTRL 0x00906240 /* Write ODT Control register */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_ABI_PAR_CNTRL 0x00906244 /* ABI and PAR Control register */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_ZQ_CAL 0x00906248 /* ZQ Calibration Control register */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_AC_SPARE_REG 0x0090611c /* Address and Control Spare register */
-
-/***************************************************************************
- *REVISION - Address & Control revision register
- ***************************************************************************/
-/* DDR34_PHY_CONTROL_REGS_0 :: REVISION :: reserved0 [31:25] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_REVISION_reserved0_MASK 0xfe000000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_REVISION_reserved0_SHIFT 25
-
-/* DDR34_PHY_CONTROL_REGS_0 :: REVISION :: PERFORMANCE [24:23] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_REVISION_PERFORMANCE_MASK 0x01800000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_REVISION_PERFORMANCE_SHIFT 23
-
-/* DDR34_PHY_CONTROL_REGS_0 :: REVISION :: TECHNOLOGY [22:20] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_REVISION_TECHNOLOGY_MASK 0x00700000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_REVISION_TECHNOLOGY_SHIFT 20
-
-/* DDR34_PHY_CONTROL_REGS_0 :: REVISION :: WB [19:19] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_REVISION_WB_MASK 0x00080000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_REVISION_WB_SHIFT 19
-
-/* DDR34_PHY_CONTROL_REGS_0 :: REVISION :: BITS [18:16] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_REVISION_BITS_MASK 0x00070000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_REVISION_BITS_SHIFT 16
-
-/* DDR34_PHY_CONTROL_REGS_0 :: REVISION :: MAJOR [15:08] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_REVISION_MAJOR_MASK 0x0000ff00
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_REVISION_MAJOR_SHIFT 8
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_REVISION_MAJOR_DEFAULT 0x000000e1
-
-/* DDR34_PHY_CONTROL_REGS_0 :: REVISION :: MINOR [07:00] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_REVISION_MINOR_MASK 0x000000ff
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_REVISION_MINOR_SHIFT 0
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_REVISION_MINOR_DEFAULT 0x00000001
-
-/***************************************************************************
- *PLL_STATUS - PHY PLL status register
- ***************************************************************************/
-/* DDR34_PHY_CONTROL_REGS_0 :: PLL_STATUS :: reserved0 [31:21] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_STATUS_reserved0_MASK 0xffe00000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_STATUS_reserved0_SHIFT 21
-
-/* DDR34_PHY_CONTROL_REGS_0 :: PLL_STATUS :: reserved_for_eco1 [20:17] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_STATUS_reserved_for_eco1_MASK 0x001e0000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_STATUS_reserved_for_eco1_SHIFT 17
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_STATUS_reserved_for_eco1_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: PLL_STATUS :: LOCK_LOST [16:16] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_STATUS_LOCK_LOST_MASK 0x00010000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_STATUS_LOCK_LOST_SHIFT 16
-
-/* DDR34_PHY_CONTROL_REGS_0 :: PLL_STATUS :: CLOCKING_8X [15:15] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_STATUS_CLOCKING_8X_MASK 0x00008000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_STATUS_CLOCKING_8X_SHIFT 15
-
-/* DDR34_PHY_CONTROL_REGS_0 :: PLL_STATUS :: CLOCKING_4X [14:14] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_STATUS_CLOCKING_4X_MASK 0x00004000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_STATUS_CLOCKING_4X_SHIFT 14
-
-/* DDR34_PHY_CONTROL_REGS_0 :: PLL_STATUS :: CLOCKING_2X [13:13] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_STATUS_CLOCKING_2X_MASK 0x00002000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_STATUS_CLOCKING_2X_SHIFT 13
-
-/* DDR34_PHY_CONTROL_REGS_0 :: PLL_STATUS :: STATUS [12:01] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_STATUS_STATUS_MASK 0x00001ffe
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_STATUS_STATUS_SHIFT 1
-
-/* DDR34_PHY_CONTROL_REGS_0 :: PLL_STATUS :: LOCK [00:00] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_STATUS_LOCK_MASK 0x00000001
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_STATUS_LOCK_SHIFT 0
-
-/***************************************************************************
- *PLL_CONFIG - PHY PLL configuration register
- ***************************************************************************/
-/* DDR34_PHY_CONTROL_REGS_0 :: PLL_CONFIG :: reserved0 [31:28] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_CONFIG_reserved0_MASK 0xf0000000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_CONFIG_reserved0_SHIFT 28
-
-/* DDR34_PHY_CONTROL_REGS_0 :: PLL_CONFIG :: reserved_for_eco1 [27:27] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_CONFIG_reserved_for_eco1_MASK 0x08000000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_CONFIG_reserved_for_eco1_SHIFT 27
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_CONFIG_reserved_for_eco1_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: PLL_CONFIG :: CK_LDO_REF_CTRL [26:25] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_CONFIG_CK_LDO_REF_CTRL_MASK 0x06000000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_CONFIG_CK_LDO_REF_CTRL_SHIFT 25
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_CONFIG_CK_LDO_REF_CTRL_DEFAULT 0x00000001
-
-/* DDR34_PHY_CONTROL_REGS_0 :: PLL_CONFIG :: CK_LDO_BIAS [24:23] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_CONFIG_CK_LDO_BIAS_MASK 0x01800000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_CONFIG_CK_LDO_BIAS_SHIFT 23
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_CONFIG_CK_LDO_BIAS_DEFAULT 0x00000003
-
-/* DDR34_PHY_CONTROL_REGS_0 :: PLL_CONFIG :: PLL_LDO_REF_SEL [22:22] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_CONFIG_PLL_LDO_REF_SEL_MASK 0x00400000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_CONFIG_PLL_LDO_REF_SEL_SHIFT 22
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_CONFIG_PLL_LDO_REF_SEL_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: PLL_CONFIG :: PLL_LDO_REF_CTRL [21:20] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_CONFIG_PLL_LDO_REF_CTRL_MASK 0x00300000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_CONFIG_PLL_LDO_REF_CTRL_SHIFT 20
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_CONFIG_PLL_LDO_REF_CTRL_DEFAULT 0x00000001
-
-/* DDR34_PHY_CONTROL_REGS_0 :: PLL_CONFIG :: PLL_LDO_BIAS [19:18] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_CONFIG_PLL_LDO_BIAS_MASK 0x000c0000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_CONFIG_PLL_LDO_BIAS_SHIFT 18
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_CONFIG_PLL_LDO_BIAS_DEFAULT 0x00000003
-
-/* DDR34_PHY_CONTROL_REGS_0 :: PLL_CONFIG :: HOLD [17:17] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_CONFIG_HOLD_MASK 0x00020000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_CONFIG_HOLD_SHIFT 17
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_CONFIG_HOLD_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: PLL_CONFIG :: ENABLE [16:16] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_CONFIG_ENABLE_MASK 0x00010000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_CONFIG_ENABLE_SHIFT 16
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_CONFIG_ENABLE_DEFAULT 0x00000001
-
-/* DDR34_PHY_CONTROL_REGS_0 :: PLL_CONFIG :: reserved2 [15:14] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_CONFIG_reserved2_MASK 0x0000c000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_CONFIG_reserved2_SHIFT 14
-
-/* DDR34_PHY_CONTROL_REGS_0 :: PLL_CONFIG :: FB_OFFSET [13:08] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_CONFIG_FB_OFFSET_MASK 0x00003f00
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_CONFIG_FB_OFFSET_SHIFT 8
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_CONFIG_FB_OFFSET_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: PLL_CONFIG :: reserved3 [07:05] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_CONFIG_reserved3_MASK 0x000000e0
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_CONFIG_reserved3_SHIFT 5
-
-/* DDR34_PHY_CONTROL_REGS_0 :: PLL_CONFIG :: RESET_POST_DIV [04:04] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_CONFIG_RESET_POST_DIV_MASK 0x00000010
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_CONFIG_RESET_POST_DIV_SHIFT 4
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_CONFIG_RESET_POST_DIV_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: PLL_CONFIG :: reserved4 [03:02] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_CONFIG_reserved4_MASK 0x0000000c
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_CONFIG_reserved4_SHIFT 2
-
-/* DDR34_PHY_CONTROL_REGS_0 :: PLL_CONFIG :: RESET [01:01] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_CONFIG_RESET_MASK 0x00000002
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_CONFIG_RESET_SHIFT 1
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_CONFIG_RESET_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: PLL_CONFIG :: PWRDN [00:00] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_CONFIG_PWRDN_MASK 0x00000001
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_CONFIG_PWRDN_SHIFT 0
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_CONFIG_PWRDN_DEFAULT 0x00000000
-
-/***************************************************************************
- *PLL_CONTROL1 - PHY PLL control register
- ***************************************************************************/
-/* DDR34_PHY_CONTROL_REGS_0 :: PLL_CONTROL1 :: reserved0 [31:10] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_CONTROL1_reserved0_MASK 0xfffffc00
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_CONTROL1_reserved0_SHIFT 10
-
-/* DDR34_PHY_CONTROL_REGS_0 :: PLL_CONTROL1 :: I_KP [09:06] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_CONTROL1_I_KP_MASK 0x000003c0
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_CONTROL1_I_KP_SHIFT 6
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_CONTROL1_I_KP_DEFAULT 0x00000005
-
-/* DDR34_PHY_CONTROL_REGS_0 :: PLL_CONTROL1 :: I_KI [05:03] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_CONTROL1_I_KI_MASK 0x00000038
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_CONTROL1_I_KI_SHIFT 3
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_CONTROL1_I_KI_DEFAULT 0x00000002
-
-/* DDR34_PHY_CONTROL_REGS_0 :: PLL_CONTROL1 :: I_KA [02:00] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_CONTROL1_I_KA_MASK 0x00000007
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_CONTROL1_I_KA_SHIFT 0
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_CONTROL1_I_KA_DEFAULT 0x00000000
-
-/***************************************************************************
- *PLL_CONTROL2 - PHY PLL control register
- ***************************************************************************/
-/* DDR34_PHY_CONTROL_REGS_0 :: PLL_CONTROL2 :: VCO_RANGE [31:30] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_CONTROL2_VCO_RANGE_MASK 0xc0000000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_CONTROL2_VCO_RANGE_SHIFT 30
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_CONTROL2_VCO_RANGE_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: PLL_CONTROL2 :: UNUSED2 [29:29] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_CONTROL2_UNUSED2_MASK 0x20000000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_CONTROL2_UNUSED2_SHIFT 29
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_CONTROL2_UNUSED2_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: PLL_CONTROL2 :: NDIV_RELOCK [28:28] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_CONTROL2_NDIV_RELOCK_MASK 0x10000000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_CONTROL2_NDIV_RELOCK_SHIFT 28
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_CONTROL2_NDIV_RELOCK_DEFAULT 0x00000001
-
-/* DDR34_PHY_CONTROL_REGS_0 :: PLL_CONTROL2 :: FAST_LOCK [27:27] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_CONTROL2_FAST_LOCK_MASK 0x08000000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_CONTROL2_FAST_LOCK_SHIFT 27
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_CONTROL2_FAST_LOCK_DEFAULT 0x00000001
-
-/* DDR34_PHY_CONTROL_REGS_0 :: PLL_CONTROL2 :: VCO_FB_DIV2 [26:26] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_CONTROL2_VCO_FB_DIV2_MASK 0x04000000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_CONTROL2_VCO_FB_DIV2_SHIFT 26
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_CONTROL2_VCO_FB_DIV2_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: PLL_CONTROL2 :: POST_CTRL_RESETB [25:24] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_CONTROL2_POST_CTRL_RESETB_MASK 0x03000000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_CONTROL2_POST_CTRL_RESETB_SHIFT 24
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_CONTROL2_POST_CTRL_RESETB_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: PLL_CONTROL2 :: PWM_RATE [23:22] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_CONTROL2_PWM_RATE_MASK 0x00c00000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_CONTROL2_PWM_RATE_SHIFT 22
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_CONTROL2_PWM_RATE_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: PLL_CONTROL2 :: STAT_MODE [21:20] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_CONTROL2_STAT_MODE_MASK 0x00300000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_CONTROL2_STAT_MODE_SHIFT 20
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_CONTROL2_STAT_MODE_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: PLL_CONTROL2 :: UNUSED1 [19:18] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_CONTROL2_UNUSED1_MASK 0x000c0000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_CONTROL2_UNUSED1_SHIFT 18
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_CONTROL2_UNUSED1_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: PLL_CONTROL2 :: STAT_UPDATE [17:17] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_CONTROL2_STAT_UPDATE_MASK 0x00020000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_CONTROL2_STAT_UPDATE_SHIFT 17
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_CONTROL2_STAT_UPDATE_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: PLL_CONTROL2 :: STAT_SELECT [16:14] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_CONTROL2_STAT_SELECT_MASK 0x0001c000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_CONTROL2_STAT_SELECT_SHIFT 14
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_CONTROL2_STAT_SELECT_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: PLL_CONTROL2 :: STAT_RESET [13:13] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_CONTROL2_STAT_RESET_MASK 0x00002000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_CONTROL2_STAT_RESET_SHIFT 13
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_CONTROL2_STAT_RESET_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: PLL_CONTROL2 :: DCO_CTRL_BYPASS_ENABLE [12:12] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_CONTROL2_DCO_CTRL_BYPASS_ENABLE_MASK 0x00001000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_CONTROL2_DCO_CTRL_BYPASS_ENABLE_SHIFT 12
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_CONTROL2_DCO_CTRL_BYPASS_ENABLE_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: PLL_CONTROL2 :: DCO_CTRL_BYPASS [11:00] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_CONTROL2_DCO_CTRL_BYPASS_MASK 0x00000fff
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_CONTROL2_DCO_CTRL_BYPASS_SHIFT 0
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_CONTROL2_DCO_CTRL_BYPASS_DEFAULT 0x00000000
-
-/***************************************************************************
- *PLL_CONTROL3 - PHY PLL control register
- ***************************************************************************/
-/* DDR34_PHY_CONTROL_REGS_0 :: PLL_CONTROL3 :: PLL_CONTROL [31:00] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_CONTROL3_PLL_CONTROL_MASK 0xffffffff
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_CONTROL3_PLL_CONTROL_SHIFT 0
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_CONTROL3_PLL_CONTROL_DEFAULT 0x00000000
-
-/***************************************************************************
- *PLL_DIVIDERS - PHY PLL integer divider register
- ***************************************************************************/
-/* DDR34_PHY_CONTROL_REGS_0 :: PLL_DIVIDERS :: reserved0 [31:28] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_DIVIDERS_reserved0_MASK 0xf0000000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_DIVIDERS_reserved0_SHIFT 28
-
-/* DDR34_PHY_CONTROL_REGS_0 :: PLL_DIVIDERS :: MDIV [27:20] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_DIVIDERS_MDIV_MASK 0x0ff00000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_DIVIDERS_MDIV_SHIFT 20
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_DIVIDERS_MDIV_DEFAULT 0x00000001
-
-/* DDR34_PHY_CONTROL_REGS_0 :: PLL_DIVIDERS :: reserved1 [19:16] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_DIVIDERS_reserved1_MASK 0x000f0000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_DIVIDERS_reserved1_SHIFT 16
-
-/* DDR34_PHY_CONTROL_REGS_0 :: PLL_DIVIDERS :: PDIV [15:12] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_DIVIDERS_PDIV_MASK 0x0000f000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_DIVIDERS_PDIV_SHIFT 12
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_DIVIDERS_PDIV_DEFAULT 0x00000001
-
-/* DDR34_PHY_CONTROL_REGS_0 :: PLL_DIVIDERS :: reserved2 [11:10] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_DIVIDERS_reserved2_MASK 0x00000c00
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_DIVIDERS_reserved2_SHIFT 10
-
-/* DDR34_PHY_CONTROL_REGS_0 :: PLL_DIVIDERS :: NDIV_INT [09:00] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_DIVIDERS_NDIV_INT_MASK 0x000003ff
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_DIVIDERS_NDIV_INT_SHIFT 0
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_DIVIDERS_NDIV_INT_DEFAULT 0x00000010
-
-/***************************************************************************
- *PLL_FRAC_DIVIDER - PHY PLL fractional divider register
- ***************************************************************************/
-/* DDR34_PHY_CONTROL_REGS_0 :: PLL_FRAC_DIVIDER :: reserved0 [31:20] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_FRAC_DIVIDER_reserved0_MASK 0xfff00000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_FRAC_DIVIDER_reserved0_SHIFT 20
-
-/* DDR34_PHY_CONTROL_REGS_0 :: PLL_FRAC_DIVIDER :: NDIV_FRAC [19:00] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_FRAC_DIVIDER_NDIV_FRAC_MASK 0x000fffff
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_FRAC_DIVIDER_NDIV_FRAC_SHIFT 0
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_FRAC_DIVIDER_NDIV_FRAC_DEFAULT 0x00000000
-
-/***************************************************************************
- *PLL_SS_CONTROL - PHY PLL spread spectrum control register
- ***************************************************************************/
-/* DDR34_PHY_CONTROL_REGS_0 :: PLL_SS_CONTROL :: reserved0 [31:20] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_SS_CONTROL_reserved0_MASK 0xfff00000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_SS_CONTROL_reserved0_SHIFT 20
-
-/* DDR34_PHY_CONTROL_REGS_0 :: PLL_SS_CONTROL :: SSC_STEP [19:04] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_SS_CONTROL_SSC_STEP_MASK 0x000ffff0
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_SS_CONTROL_SSC_STEP_SHIFT 4
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_SS_CONTROL_SSC_STEP_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: PLL_SS_CONTROL :: reserved1 [03:01] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_SS_CONTROL_reserved1_MASK 0x0000000e
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_SS_CONTROL_reserved1_SHIFT 1
-
-/* DDR34_PHY_CONTROL_REGS_0 :: PLL_SS_CONTROL :: SSC_MODE [00:00] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_SS_CONTROL_SSC_MODE_MASK 0x00000001
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_SS_CONTROL_SSC_MODE_SHIFT 0
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_SS_CONTROL_SSC_MODE_DEFAULT 0x00000000
-
-/***************************************************************************
- *PLL_SS_LIMIT - PHY PLL spread spectrum limit register
- ***************************************************************************/
-/* DDR34_PHY_CONTROL_REGS_0 :: PLL_SS_LIMIT :: reserved0 [31:26] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_SS_LIMIT_reserved0_MASK 0xfc000000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_SS_LIMIT_reserved0_SHIFT 26
-
-/* DDR34_PHY_CONTROL_REGS_0 :: PLL_SS_LIMIT :: SSC_LIMIT [25:04] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_SS_LIMIT_SSC_LIMIT_MASK 0x03fffff0
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_SS_LIMIT_SSC_LIMIT_SHIFT 4
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_SS_LIMIT_SSC_LIMIT_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: PLL_SS_LIMIT :: reserved1 [03:00] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_SS_LIMIT_reserved1_MASK 0x0000000f
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_SS_LIMIT_reserved1_SHIFT 0
-
-/***************************************************************************
- *AUX_CONTROL - Aux Control register
- ***************************************************************************/
-/* DDR34_PHY_CONTROL_REGS_0 :: AUX_CONTROL :: reserved0 [31:21] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_AUX_CONTROL_reserved0_MASK 0xffe00000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_AUX_CONTROL_reserved0_SHIFT 21
-
-/* DDR34_PHY_CONTROL_REGS_0 :: AUX_CONTROL :: IS_ODT [20:16] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_AUX_CONTROL_IS_ODT_MASK 0x001f0000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_AUX_CONTROL_IS_ODT_SHIFT 16
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_AUX_CONTROL_IS_ODT_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: AUX_CONTROL :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_AUX_CONTROL_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_AUX_CONTROL_reserved1_SHIFT 13
-
-/* DDR34_PHY_CONTROL_REGS_0 :: AUX_CONTROL :: IS_CS [12:08] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_AUX_CONTROL_IS_CS_MASK 0x00001f00
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_AUX_CONTROL_IS_CS_SHIFT 8
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_AUX_CONTROL_IS_CS_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: AUX_CONTROL :: reserved2 [07:05] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_AUX_CONTROL_reserved2_MASK 0x000000e0
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_AUX_CONTROL_reserved2_SHIFT 5
-
-/* DDR34_PHY_CONTROL_REGS_0 :: AUX_CONTROL :: IS_AD [04:00] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_AUX_CONTROL_IS_AD_MASK 0x0000001f
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_AUX_CONTROL_IS_AD_SHIFT 0
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_AUX_CONTROL_IS_AD_DEFAULT 0x00000000
-
-/***************************************************************************
- *IDLE_PAD_CONTROL - Idle mode pad control register
- ***************************************************************************/
-/* DDR34_PHY_CONTROL_REGS_0 :: IDLE_PAD_CONTROL :: IDLE [31:31] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_IDLE_MASK 0x80000000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_IDLE_SHIFT 31
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_IDLE_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: IDLE_PAD_CONTROL :: DIB_MODE [30:30] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_DIB_MODE_MASK 0x40000000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_DIB_MODE_SHIFT 30
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_DIB_MODE_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: IDLE_PAD_CONTROL :: reserved0 [29:08] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_reserved0_MASK 0x3fffff00
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_reserved0_SHIFT 8
-
-/* DDR34_PHY_CONTROL_REGS_0 :: IDLE_PAD_CONTROL :: reserved_for_eco1 [07:04] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_reserved_for_eco1_MASK 0x000000f0
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_reserved_for_eco1_SHIFT 4
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_reserved_for_eco1_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: IDLE_PAD_CONTROL :: RXENB [03:03] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_RXENB_MASK 0x00000008
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_RXENB_SHIFT 3
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_RXENB_DEFAULT 0x00000001
-
-/* DDR34_PHY_CONTROL_REGS_0 :: IDLE_PAD_CONTROL :: IDDQ [02:02] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_IDDQ_MASK 0x00000004
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_IDDQ_SHIFT 2
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_IDDQ_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: IDLE_PAD_CONTROL :: DOUT_N [01:01] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_DOUT_N_MASK 0x00000002
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_DOUT_N_SHIFT 1
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_DOUT_N_DEFAULT 0x00000001
-
-/* DDR34_PHY_CONTROL_REGS_0 :: IDLE_PAD_CONTROL :: DOUT_P [00:00] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_DOUT_P_MASK 0x00000001
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_DOUT_P_SHIFT 0
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_DOUT_P_DEFAULT 0x00000000
-
-/***************************************************************************
- *IDLE_PAD_ENABLE0 - Idle mode pad enable register
- ***************************************************************************/
-/* DDR34_PHY_CONTROL_REGS_0 :: IDLE_PAD_ENABLE0 :: reserved0 [31:15] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_IDLE_PAD_ENABLE0_reserved0_MASK 0xffff8000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_IDLE_PAD_ENABLE0_reserved0_SHIFT 15
-
-/* DDR34_PHY_CONTROL_REGS_0 :: IDLE_PAD_ENABLE0 :: reserved_for_eco1 [14:11] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_IDLE_PAD_ENABLE0_reserved_for_eco1_MASK 0x00007800
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_IDLE_PAD_ENABLE0_reserved_for_eco1_SHIFT 11
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_IDLE_PAD_ENABLE0_reserved_for_eco1_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: IDLE_PAD_ENABLE0 :: IO_IDLE_ENABLE [10:00] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_IDLE_PAD_ENABLE0_IO_IDLE_ENABLE_MASK 0x000007ff
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_IDLE_PAD_ENABLE0_IO_IDLE_ENABLE_SHIFT 0
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_IDLE_PAD_ENABLE0_IO_IDLE_ENABLE_DEFAULT 0x00000000
-
-/***************************************************************************
- *IDLE_PAD_ENABLE1 - Idle mode pad enable register
- ***************************************************************************/
-/* DDR34_PHY_CONTROL_REGS_0 :: IDLE_PAD_ENABLE1 :: reserved0 [31:22] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_IDLE_PAD_ENABLE1_reserved0_MASK 0xffc00000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_IDLE_PAD_ENABLE1_reserved0_SHIFT 22
-
-/* DDR34_PHY_CONTROL_REGS_0 :: IDLE_PAD_ENABLE1 :: IO_IDLE_ENABLE [21:00] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_IDLE_PAD_ENABLE1_IO_IDLE_ENABLE_MASK 0x003fffff
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_IDLE_PAD_ENABLE1_IO_IDLE_ENABLE_SHIFT 0
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_IDLE_PAD_ENABLE1_IO_IDLE_ENABLE_DEFAULT 0x00000000
-
-/***************************************************************************
- *DRIVE_PAD_CTL - PVT Compensation control register
- ***************************************************************************/
-/* DDR34_PHY_CONTROL_REGS_0 :: DRIVE_PAD_CTL :: reserved_for_padding0 [31:30] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_reserved_for_padding0_MASK 0xc0000000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_reserved_for_padding0_SHIFT 30
-
-/* DDR34_PHY_CONTROL_REGS_0 :: DRIVE_PAD_CTL :: ADDR_CTL_PD_IDLE_STRENGTH [29:25] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_ADDR_CTL_PD_IDLE_STRENGTH_MASK 0x3e000000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_ADDR_CTL_PD_IDLE_STRENGTH_SHIFT 25
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_ADDR_CTL_PD_IDLE_STRENGTH_DEFAULT 0x0000001f
-
-/* DDR34_PHY_CONTROL_REGS_0 :: DRIVE_PAD_CTL :: ADDR_CTL_ND_IDLE_STRENGTH [24:20] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_ADDR_CTL_ND_IDLE_STRENGTH_MASK 0x01f00000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_ADDR_CTL_ND_IDLE_STRENGTH_SHIFT 20
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_ADDR_CTL_ND_IDLE_STRENGTH_DEFAULT 0x0000001f
-
-/* DDR34_PHY_CONTROL_REGS_0 :: DRIVE_PAD_CTL :: ADDR_CTL_PD_TERM_STRENGTH [19:15] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_ADDR_CTL_PD_TERM_STRENGTH_MASK 0x000f8000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_ADDR_CTL_PD_TERM_STRENGTH_SHIFT 15
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_ADDR_CTL_PD_TERM_STRENGTH_DEFAULT 0x00000008
-
-/* DDR34_PHY_CONTROL_REGS_0 :: DRIVE_PAD_CTL :: ADDR_CTL_ND_TERM_STRENGTH [14:10] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_ADDR_CTL_ND_TERM_STRENGTH_MASK 0x00007c00
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_ADDR_CTL_ND_TERM_STRENGTH_SHIFT 10
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_ADDR_CTL_ND_TERM_STRENGTH_DEFAULT 0x00000008
-
-/* DDR34_PHY_CONTROL_REGS_0 :: DRIVE_PAD_CTL :: ADDR_CTL_PD_STRENGTH [09:05] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_ADDR_CTL_PD_STRENGTH_MASK 0x000003e0
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_ADDR_CTL_PD_STRENGTH_SHIFT 5
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_ADDR_CTL_PD_STRENGTH_DEFAULT 0x0000001f
-
-/* DDR34_PHY_CONTROL_REGS_0 :: DRIVE_PAD_CTL :: ADDR_CTL_ND_STRENGTH [04:00] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_ADDR_CTL_ND_STRENGTH_MASK 0x0000001f
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_ADDR_CTL_ND_STRENGTH_SHIFT 0
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_ADDR_CTL_ND_STRENGTH_DEFAULT 0x0000001f
-
-/***************************************************************************
- *STATIC_PAD_CTL - pad rx and tx characteristics control register
- ***************************************************************************/
-/* DDR34_PHY_CONTROL_REGS_0 :: STATIC_PAD_CTL :: reserved0 [31:28] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_STATIC_PAD_CTL_reserved0_MASK 0xf0000000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_STATIC_PAD_CTL_reserved0_SHIFT 28
-
-/* DDR34_PHY_CONTROL_REGS_0 :: STATIC_PAD_CTL :: AUTO_OEB [27:27] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_STATIC_PAD_CTL_AUTO_OEB_MASK 0x08000000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_STATIC_PAD_CTL_AUTO_OEB_SHIFT 27
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_STATIC_PAD_CTL_AUTO_OEB_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: STATIC_PAD_CTL :: IDDQ_GDDR5 [26:26] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_STATIC_PAD_CTL_IDDQ_GDDR5_MASK 0x04000000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_STATIC_PAD_CTL_IDDQ_GDDR5_SHIFT 26
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_STATIC_PAD_CTL_IDDQ_GDDR5_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: STATIC_PAD_CTL :: IDDQ_LPDDR [25:25] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_STATIC_PAD_CTL_IDDQ_LPDDR_MASK 0x02000000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_STATIC_PAD_CTL_IDDQ_LPDDR_SHIFT 25
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_STATIC_PAD_CTL_IDDQ_LPDDR_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: STATIC_PAD_CTL :: IDDQ_CLK1 [24:24] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_STATIC_PAD_CTL_IDDQ_CLK1_MASK 0x01000000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_STATIC_PAD_CTL_IDDQ_CLK1_SHIFT 24
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_STATIC_PAD_CTL_IDDQ_CLK1_DEFAULT 0x00000001
-
-/* DDR34_PHY_CONTROL_REGS_0 :: STATIC_PAD_CTL :: IDDQ_CLK0 [23:23] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_STATIC_PAD_CTL_IDDQ_CLK0_MASK 0x00800000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_STATIC_PAD_CTL_IDDQ_CLK0_SHIFT 23
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_STATIC_PAD_CTL_IDDQ_CLK0_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: STATIC_PAD_CTL :: IDDQ_ODT [22:22] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_STATIC_PAD_CTL_IDDQ_ODT_MASK 0x00400000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_STATIC_PAD_CTL_IDDQ_ODT_SHIFT 22
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_STATIC_PAD_CTL_IDDQ_ODT_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: STATIC_PAD_CTL :: IDDQ_PAR [21:21] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_STATIC_PAD_CTL_IDDQ_PAR_MASK 0x00200000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_STATIC_PAD_CTL_IDDQ_PAR_SHIFT 21
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_STATIC_PAD_CTL_IDDQ_PAR_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: STATIC_PAD_CTL :: IDDQ_BA [20:20] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_STATIC_PAD_CTL_IDDQ_BA_MASK 0x00100000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_STATIC_PAD_CTL_IDDQ_BA_SHIFT 20
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_STATIC_PAD_CTL_IDDQ_BA_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: STATIC_PAD_CTL :: IDDQ_AUX2 [19:19] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_STATIC_PAD_CTL_IDDQ_AUX2_MASK 0x00080000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_STATIC_PAD_CTL_IDDQ_AUX2_SHIFT 19
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_STATIC_PAD_CTL_IDDQ_AUX2_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: STATIC_PAD_CTL :: IDDQ_AUX1 [18:18] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_STATIC_PAD_CTL_IDDQ_AUX1_MASK 0x00040000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_STATIC_PAD_CTL_IDDQ_AUX1_SHIFT 18
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_STATIC_PAD_CTL_IDDQ_AUX1_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: STATIC_PAD_CTL :: IDDQ_AUX0 [17:17] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_STATIC_PAD_CTL_IDDQ_AUX0_MASK 0x00020000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_STATIC_PAD_CTL_IDDQ_AUX0_SHIFT 17
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_STATIC_PAD_CTL_IDDQ_AUX0_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: STATIC_PAD_CTL :: IDDQ_CS1 [16:16] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_STATIC_PAD_CTL_IDDQ_CS1_MASK 0x00010000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_STATIC_PAD_CTL_IDDQ_CS1_SHIFT 16
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_STATIC_PAD_CTL_IDDQ_CS1_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: STATIC_PAD_CTL :: IDDQ_A15 [15:15] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_STATIC_PAD_CTL_IDDQ_A15_MASK 0x00008000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_STATIC_PAD_CTL_IDDQ_A15_SHIFT 15
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_STATIC_PAD_CTL_IDDQ_A15_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: STATIC_PAD_CTL :: IDDQ_A14 [14:14] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_STATIC_PAD_CTL_IDDQ_A14_MASK 0x00004000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_STATIC_PAD_CTL_IDDQ_A14_SHIFT 14
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_STATIC_PAD_CTL_IDDQ_A14_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: STATIC_PAD_CTL :: IDDQ_A13 [13:13] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_STATIC_PAD_CTL_IDDQ_A13_MASK 0x00002000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_STATIC_PAD_CTL_IDDQ_A13_SHIFT 13
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_STATIC_PAD_CTL_IDDQ_A13_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: STATIC_PAD_CTL :: IDDQ_A12 [12:12] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_STATIC_PAD_CTL_IDDQ_A12_MASK 0x00001000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_STATIC_PAD_CTL_IDDQ_A12_SHIFT 12
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_STATIC_PAD_CTL_IDDQ_A12_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: STATIC_PAD_CTL :: IDDQ_A11 [11:11] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_STATIC_PAD_CTL_IDDQ_A11_MASK 0x00000800
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_STATIC_PAD_CTL_IDDQ_A11_SHIFT 11
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_STATIC_PAD_CTL_IDDQ_A11_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: STATIC_PAD_CTL :: IDDQ_A10 [10:10] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_STATIC_PAD_CTL_IDDQ_A10_MASK 0x00000400
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_STATIC_PAD_CTL_IDDQ_A10_SHIFT 10
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_STATIC_PAD_CTL_IDDQ_A10_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: STATIC_PAD_CTL :: IDDQ_A09 [09:09] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_STATIC_PAD_CTL_IDDQ_A09_MASK 0x00000200
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_STATIC_PAD_CTL_IDDQ_A09_SHIFT 9
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_STATIC_PAD_CTL_IDDQ_A09_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: STATIC_PAD_CTL :: reserved1 [08:08] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_STATIC_PAD_CTL_reserved1_MASK 0x00000100
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_STATIC_PAD_CTL_reserved1_SHIFT 8
-
-/* DDR34_PHY_CONTROL_REGS_0 :: STATIC_PAD_CTL :: TX_MODE [07:04] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_STATIC_PAD_CTL_TX_MODE_MASK 0x000000f0
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_STATIC_PAD_CTL_TX_MODE_SHIFT 4
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_STATIC_PAD_CTL_TX_MODE_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: STATIC_PAD_CTL :: reserved2 [03:03] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_STATIC_PAD_CTL_reserved2_MASK 0x00000008
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_STATIC_PAD_CTL_reserved2_SHIFT 3
-
-/* DDR34_PHY_CONTROL_REGS_0 :: STATIC_PAD_CTL :: RX_MODE [02:00] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_STATIC_PAD_CTL_RX_MODE_MASK 0x00000007
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_STATIC_PAD_CTL_RX_MODE_SHIFT 0
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_STATIC_PAD_CTL_RX_MODE_DEFAULT 0x00000000
-
-/***************************************************************************
- *DRAM_CONFIG - DRAM configuration register
- ***************************************************************************/
-/* DDR34_PHY_CONTROL_REGS_0 :: DRAM_CONFIG :: INIT_MODE [31:31] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_DRAM_CONFIG_INIT_MODE_MASK 0x80000000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_DRAM_CONFIG_INIT_MODE_SHIFT 31
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_DRAM_CONFIG_INIT_MODE_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: DRAM_CONFIG :: reserved0 [30:28] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_DRAM_CONFIG_reserved0_MASK 0x70000000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_DRAM_CONFIG_reserved0_SHIFT 28
-
-/* DDR34_PHY_CONTROL_REGS_0 :: DRAM_CONFIG :: ECC_ENABLED [27:27] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_DRAM_CONFIG_ECC_ENABLED_MASK 0x08000000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_DRAM_CONFIG_ECC_ENABLED_SHIFT 27
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_DRAM_CONFIG_ECC_ENABLED_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: DRAM_CONFIG :: SPLIT_DQ_BUS [26:26] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_DRAM_CONFIG_SPLIT_DQ_BUS_MASK 0x04000000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_DRAM_CONFIG_SPLIT_DQ_BUS_SHIFT 26
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_DRAM_CONFIG_SPLIT_DQ_BUS_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: DRAM_CONFIG :: BUS16 [25:25] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_DRAM_CONFIG_BUS16_MASK 0x02000000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_DRAM_CONFIG_BUS16_SHIFT 25
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_DRAM_CONFIG_BUS16_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: DRAM_CONFIG :: BUS8 [24:24] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_DRAM_CONFIG_BUS8_MASK 0x01000000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_DRAM_CONFIG_BUS8_SHIFT 24
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_DRAM_CONFIG_BUS8_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: DRAM_CONFIG :: reserved1 [23:16] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_DRAM_CONFIG_reserved1_MASK 0x00ff0000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_DRAM_CONFIG_reserved1_SHIFT 16
-
-/* DDR34_PHY_CONTROL_REGS_0 :: DRAM_CONFIG :: EDC_MODE [15:15] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_DRAM_CONFIG_EDC_MODE_MASK 0x00008000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_DRAM_CONFIG_EDC_MODE_SHIFT 15
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_DRAM_CONFIG_EDC_MODE_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: DRAM_CONFIG :: RDQS_MODE [14:14] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_DRAM_CONFIG_RDQS_MODE_MASK 0x00004000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_DRAM_CONFIG_RDQS_MODE_SHIFT 14
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_DRAM_CONFIG_RDQS_MODE_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: DRAM_CONFIG :: GROUP_BITS [13:12] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_DRAM_CONFIG_GROUP_BITS_MASK 0x00003000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_DRAM_CONFIG_GROUP_BITS_SHIFT 12
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_DRAM_CONFIG_GROUP_BITS_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: DRAM_CONFIG :: BANK_BITS [11:10] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_DRAM_CONFIG_BANK_BITS_MASK 0x00000c00
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_DRAM_CONFIG_BANK_BITS_SHIFT 10
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_DRAM_CONFIG_BANK_BITS_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: DRAM_CONFIG :: COL_BITS [09:08] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_DRAM_CONFIG_COL_BITS_MASK 0x00000300
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_DRAM_CONFIG_COL_BITS_SHIFT 8
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_DRAM_CONFIG_COL_BITS_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: DRAM_CONFIG :: ROW_BITS [07:04] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_DRAM_CONFIG_ROW_BITS_MASK 0x000000f0
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_DRAM_CONFIG_ROW_BITS_SHIFT 4
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_DRAM_CONFIG_ROW_BITS_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: DRAM_CONFIG :: DRAM_TYPE [03:00] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_DRAM_CONFIG_DRAM_TYPE_MASK 0x0000000f
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_DRAM_CONFIG_DRAM_TYPE_SHIFT 0
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_DRAM_CONFIG_DRAM_TYPE_DEFAULT 0x00000000
-
-/***************************************************************************
- *DRAM_TIMING1 - DRAM timing register #1
- ***************************************************************************/
-/* DDR34_PHY_CONTROL_REGS_0 :: DRAM_TIMING1 :: TRAS [31:24] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_DRAM_TIMING1_TRAS_MASK 0xff000000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_DRAM_TIMING1_TRAS_SHIFT 24
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_DRAM_TIMING1_TRAS_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: DRAM_TIMING1 :: TRRD [23:16] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_DRAM_TIMING1_TRRD_MASK 0x00ff0000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_DRAM_TIMING1_TRRD_SHIFT 16
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_DRAM_TIMING1_TRRD_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: DRAM_TIMING1 :: TRP [15:08] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_DRAM_TIMING1_TRP_MASK 0x0000ff00
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_DRAM_TIMING1_TRP_SHIFT 8
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_DRAM_TIMING1_TRP_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: DRAM_TIMING1 :: TRCD [07:00] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_DRAM_TIMING1_TRCD_MASK 0x000000ff
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_DRAM_TIMING1_TRCD_SHIFT 0
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_DRAM_TIMING1_TRCD_DEFAULT 0x00000000
-
-/***************************************************************************
- *DRAM_TIMING2 - DRAM timing register #2
- ***************************************************************************/
-/* DDR34_PHY_CONTROL_REGS_0 :: DRAM_TIMING2 :: TRTP [31:24] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_DRAM_TIMING2_TRTP_MASK 0xff000000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_DRAM_TIMING2_TRTP_SHIFT 24
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_DRAM_TIMING2_TRTP_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: DRAM_TIMING2 :: TWR [23:16] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_DRAM_TIMING2_TWR_MASK 0x00ff0000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_DRAM_TIMING2_TWR_SHIFT 16
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_DRAM_TIMING2_TWR_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: DRAM_TIMING2 :: TCWL [15:08] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_DRAM_TIMING2_TCWL_MASK 0x0000ff00
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_DRAM_TIMING2_TCWL_SHIFT 8
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_DRAM_TIMING2_TCWL_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: DRAM_TIMING2 :: TCAS [07:00] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_DRAM_TIMING2_TCAS_MASK 0x000000ff
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_DRAM_TIMING2_TCAS_SHIFT 0
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_DRAM_TIMING2_TCAS_DEFAULT 0x00000000
-
-/***************************************************************************
- *DRAM_TIMING3 - DRAM timing register #3
- ***************************************************************************/
-/* DDR34_PHY_CONTROL_REGS_0 :: DRAM_TIMING3 :: reserved0 [31:24] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_DRAM_TIMING3_reserved0_MASK 0xff000000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_DRAM_TIMING3_reserved0_SHIFT 24
-
-/* DDR34_PHY_CONTROL_REGS_0 :: DRAM_TIMING3 :: TCAL [23:20] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_DRAM_TIMING3_TCAL_MASK 0x00f00000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_DRAM_TIMING3_TCAL_SHIFT 20
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_DRAM_TIMING3_TCAL_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: DRAM_TIMING3 :: TRTW [19:16] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_DRAM_TIMING3_TRTW_MASK 0x000f0000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_DRAM_TIMING3_TRTW_SHIFT 16
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_DRAM_TIMING3_TRTW_DEFAULT 0x00000004
-
-/* DDR34_PHY_CONTROL_REGS_0 :: DRAM_TIMING3 :: TWTR [15:12] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_DRAM_TIMING3_TWTR_MASK 0x0000f000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_DRAM_TIMING3_TWTR_SHIFT 12
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_DRAM_TIMING3_TWTR_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: DRAM_TIMING3 :: TRFC [11:00] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_DRAM_TIMING3_TRFC_MASK 0x00000fff
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_DRAM_TIMING3_TRFC_SHIFT 0
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_DRAM_TIMING3_TRFC_DEFAULT 0x00000000
-
-/***************************************************************************
- *DRAM_TIMING4 - DRAM timing register #4
- ***************************************************************************/
-/* DDR34_PHY_CONTROL_REGS_0 :: DRAM_TIMING4 :: temp [31:00] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_DRAM_TIMING4_temp_MASK 0xffffffff
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_DRAM_TIMING4_temp_SHIFT 0
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_DRAM_TIMING4_temp_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CALIBRATE - PHY VDL calibration control register
- ***************************************************************************/
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CALIBRATE :: reserved0 [31:10] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CALIBRATE_reserved0_MASK 0xfffffc00
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CALIBRATE_reserved0_SHIFT 10
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CALIBRATE :: reserved_for_eco1 [09:06] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CALIBRATE_reserved_for_eco1_MASK 0x000003c0
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CALIBRATE_reserved_for_eco1_SHIFT 6
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CALIBRATE_reserved_for_eco1_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CALIBRATE :: HALF_STEPS [05:05] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CALIBRATE_HALF_STEPS_MASK 0x00000020
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CALIBRATE_HALF_STEPS_SHIFT 5
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CALIBRATE_HALF_STEPS_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CALIBRATE :: UPDATE_FAST [04:04] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CALIBRATE_UPDATE_FAST_MASK 0x00000010
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CALIBRATE_UPDATE_FAST_SHIFT 4
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CALIBRATE_UPDATE_FAST_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CALIBRATE :: UPDATE_REGS [03:03] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CALIBRATE_UPDATE_REGS_MASK 0x00000008
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CALIBRATE_UPDATE_REGS_SHIFT 3
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CALIBRATE_UPDATE_REGS_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CALIBRATE :: CALIB_FTM2 [02:02] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CALIBRATE_CALIB_FTM2_MASK 0x00000004
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CALIBRATE_CALIB_FTM2_SHIFT 2
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CALIBRATE_CALIB_FTM2_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CALIBRATE :: CALIB_PHYBIST [01:01] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CALIBRATE_CALIB_PHYBIST_MASK 0x00000002
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CALIBRATE_CALIB_PHYBIST_SHIFT 1
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CALIBRATE_CALIB_PHYBIST_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CALIBRATE :: CALIB_ONCE [00:00] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CALIBRATE_CALIB_ONCE_MASK 0x00000001
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CALIBRATE_CALIB_ONCE_SHIFT 0
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CALIBRATE_CALIB_ONCE_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CALIB_STATUS1 - PHY VDL calibration status register #1
- ***************************************************************************/
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CALIB_STATUS1 :: reserved0 [31:18] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS1_reserved0_MASK 0xfffc0000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS1_reserved0_SHIFT 18
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CALIB_STATUS1 :: CALIB_TOTAL_STEPS [17:08] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS1_CALIB_TOTAL_STEPS_MASK 0x0003ff00
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS1_CALIB_TOTAL_STEPS_SHIFT 8
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS1_CALIB_TOTAL_STEPS_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CALIB_STATUS1 :: reserved1 [07:06] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS1_reserved1_MASK 0x000000c0
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS1_reserved1_SHIFT 6
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CALIB_STATUS1 :: CALIB_BUS_ERROR [05:05] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS1_CALIB_BUS_ERROR_MASK 0x00000020
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS1_CALIB_BUS_ERROR_SHIFT 5
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS1_CALIB_BUS_ERROR_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CALIB_STATUS1 :: CALIB_REGS_DONE [04:04] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS1_CALIB_REGS_DONE_MASK 0x00000010
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS1_CALIB_REGS_DONE_SHIFT 4
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS1_CALIB_REGS_DONE_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CALIB_STATUS1 :: CALIB_LOCK_6B [03:03] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS1_CALIB_LOCK_6B_MASK 0x00000008
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS1_CALIB_LOCK_6B_SHIFT 3
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS1_CALIB_LOCK_6B_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CALIB_STATUS1 :: CALIB_LOCK_4B [02:02] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS1_CALIB_LOCK_4B_MASK 0x00000004
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS1_CALIB_LOCK_4B_SHIFT 2
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS1_CALIB_LOCK_4B_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CALIB_STATUS1 :: CALIB_LOCK_2B [01:01] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS1_CALIB_LOCK_2B_MASK 0x00000002
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS1_CALIB_LOCK_2B_SHIFT 1
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS1_CALIB_LOCK_2B_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CALIB_STATUS1 :: CALIB_IDLE [00:00] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS1_CALIB_IDLE_MASK 0x00000001
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS1_CALIB_IDLE_SHIFT 0
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS1_CALIB_IDLE_DEFAULT 0x00000001
-
-/***************************************************************************
- *VDL_CALIB_STATUS2 - PHY VDL calibration status register #2
- ***************************************************************************/
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CALIB_STATUS2 :: reserved0 [31:22] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS2_reserved0_MASK 0xffc00000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS2_reserved0_SHIFT 22
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CALIB_STATUS2 :: CALIB_4B_STEPS [21:12] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS2_CALIB_4B_STEPS_MASK 0x003ff000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS2_CALIB_4B_STEPS_SHIFT 12
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS2_CALIB_4B_STEPS_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CALIB_STATUS2 :: reserved1 [11:10] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS2_reserved1_MASK 0x00000c00
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS2_reserved1_SHIFT 10
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CALIB_STATUS2 :: CALIB_2B_STEPS [09:00] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS2_CALIB_2B_STEPS_MASK 0x000003ff
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS2_CALIB_2B_STEPS_SHIFT 0
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS2_CALIB_2B_STEPS_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_MONITOR_CONTROL - PHY VDL delay monitoring control register
- ***************************************************************************/
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_MONITOR_CONTROL :: reserved0 [31:22] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_MONITOR_CONTROL_reserved0_MASK 0xffc00000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_MONITOR_CONTROL_reserved0_SHIFT 22
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_MONITOR_CONTROL :: INTERVAL [21:08] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_MONITOR_CONTROL_INTERVAL_MASK 0x003fff00
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_MONITOR_CONTROL_INTERVAL_SHIFT 8
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_MONITOR_CONTROL_INTERVAL_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_MONITOR_CONTROL :: reserved1 [07:04] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_MONITOR_CONTROL_reserved1_MASK 0x000000f0
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_MONITOR_CONTROL_reserved1_SHIFT 4
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_MONITOR_CONTROL :: UPDATE [03:03] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_MONITOR_CONTROL_UPDATE_MASK 0x00000008
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_MONITOR_CONTROL_UPDATE_SHIFT 3
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_MONITOR_CONTROL_UPDATE_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_MONITOR_CONTROL :: FORCE [02:02] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_MONITOR_CONTROL_FORCE_MASK 0x00000004
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_MONITOR_CONTROL_FORCE_SHIFT 2
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_MONITOR_CONTROL_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_MONITOR_CONTROL :: DATA_RATE [01:01] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_MONITOR_CONTROL_DATA_RATE_MASK 0x00000002
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_MONITOR_CONTROL_DATA_RATE_SHIFT 1
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_MONITOR_CONTROL_DATA_RATE_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_MONITOR_CONTROL :: ENABLE [00:00] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_MONITOR_CONTROL_ENABLE_MASK 0x00000001
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_MONITOR_CONTROL_ENABLE_SHIFT 0
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_MONITOR_CONTROL_ENABLE_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_MONITOR_REF - PHY VDL delay monitoring reference register
- ***************************************************************************/
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_MONITOR_REF :: reserved0 [31:22] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_MONITOR_REF_reserved0_MASK 0xffc00000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_MONITOR_REF_reserved0_SHIFT 22
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_MONITOR_REF :: MONITOR_4B_STEPS [21:12] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_MONITOR_REF_MONITOR_4B_STEPS_MASK 0x003ff000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_MONITOR_REF_MONITOR_4B_STEPS_SHIFT 12
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_MONITOR_REF_MONITOR_4B_STEPS_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_MONITOR_REF :: reserved1 [11:10] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_MONITOR_REF_reserved1_MASK 0x00000c00
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_MONITOR_REF_reserved1_SHIFT 10
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_MONITOR_REF :: MONITOR_2B_STEPS [09:00] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_MONITOR_REF_MONITOR_2B_STEPS_MASK 0x000003ff
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_MONITOR_REF_MONITOR_2B_STEPS_SHIFT 0
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_MONITOR_REF_MONITOR_2B_STEPS_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_MONITOR_STATUS - PHY VDL delay monitoring status register
- ***************************************************************************/
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_MONITOR_STATUS :: reserved0 [31:29] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_MONITOR_STATUS_reserved0_MASK 0xe0000000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_MONITOR_STATUS_reserved0_SHIFT 29
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_MONITOR_STATUS :: MONITOR_BUS_ERROR [28:28] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_MONITOR_STATUS_MONITOR_BUS_ERROR_MASK 0x10000000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_MONITOR_STATUS_MONITOR_BUS_ERROR_SHIFT 28
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_MONITOR_STATUS_MONITOR_BUS_ERROR_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_MONITOR_STATUS :: reserved1 [27:25] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_MONITOR_STATUS_reserved1_MASK 0x0e000000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_MONITOR_STATUS_reserved1_SHIFT 25
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_MONITOR_STATUS :: MONITOR_ADJ [24:20] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_MONITOR_STATUS_MONITOR_ADJ_MASK 0x01f00000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_MONITOR_STATUS_MONITOR_ADJ_SHIFT 20
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_MONITOR_STATUS_MONITOR_ADJ_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_MONITOR_STATUS :: MONITOR_CHANGE [19:12] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_MONITOR_STATUS_MONITOR_CHANGE_MASK 0x000ff000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_MONITOR_STATUS_MONITOR_CHANGE_SHIFT 12
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_MONITOR_STATUS_MONITOR_CHANGE_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_MONITOR_STATUS :: reserved2 [11:10] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_MONITOR_STATUS_reserved2_MASK 0x00000c00
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_MONITOR_STATUS_reserved2_SHIFT 10
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_MONITOR_STATUS :: MONITOR_TOTAL [09:00] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_MONITOR_STATUS_MONITOR_TOTAL_MASK 0x000003ff
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_MONITOR_STATUS_MONITOR_TOTAL_SHIFT 0
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_MONITOR_STATUS_MONITOR_TOTAL_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_MONITOR_OVERRIDE - PHY VDL delay monitoring override register
- ***************************************************************************/
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_MONITOR_OVERRIDE :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_MONITOR_OVERRIDE_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_MONITOR_OVERRIDE_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_MONITOR_OVERRIDE_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_MONITOR_OVERRIDE :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_MONITOR_OVERRIDE_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_MONITOR_OVERRIDE_reserved0_SHIFT 17
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_MONITOR_OVERRIDE :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_MONITOR_OVERRIDE_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_MONITOR_OVERRIDE_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_MONITOR_OVERRIDE_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_MONITOR_OVERRIDE :: reserved1 [15:09] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_MONITOR_OVERRIDE_reserved1_MASK 0x0000fe00
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_MONITOR_OVERRIDE_reserved1_SHIFT 9
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_MONITOR_OVERRIDE :: ADJ [08:04] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_MONITOR_OVERRIDE_ADJ_MASK 0x000001f0
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_MONITOR_OVERRIDE_ADJ_SHIFT 4
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_MONITOR_OVERRIDE_ADJ_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_MONITOR_OVERRIDE :: reserved2 [03:01] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_MONITOR_OVERRIDE_reserved2_MASK 0x0000000e
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_MONITOR_OVERRIDE_reserved2_SHIFT 1
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_MONITOR_OVERRIDE :: ENABLE [00:00] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_MONITOR_OVERRIDE_ENABLE_MASK 0x00000001
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_MONITOR_OVERRIDE_ENABLE_SHIFT 0
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_MONITOR_OVERRIDE_ENABLE_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_MONITOR_OUT_CONTROL - PHY VDL delay monitoring output control register
- ***************************************************************************/
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_MONITOR_OUT_CONTROL :: reserved0 [31:20] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_MONITOR_OUT_CONTROL_reserved0_MASK 0xfff00000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_MONITOR_OUT_CONTROL_reserved0_SHIFT 20
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_MONITOR_OUT_CONTROL :: LOWER_LIMIT [19:12] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_MONITOR_OUT_CONTROL_LOWER_LIMIT_MASK 0x000ff000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_MONITOR_OUT_CONTROL_LOWER_LIMIT_SHIFT 12
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_MONITOR_OUT_CONTROL_LOWER_LIMIT_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_MONITOR_OUT_CONTROL :: UPPER_LIMIT [11:04] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_MONITOR_OUT_CONTROL_UPPER_LIMIT_MASK 0x00000ff0
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_MONITOR_OUT_CONTROL_UPPER_LIMIT_SHIFT 4
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_MONITOR_OUT_CONTROL_UPPER_LIMIT_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_MONITOR_OUT_CONTROL :: reserved1 [03:01] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_MONITOR_OUT_CONTROL_reserved1_MASK 0x0000000e
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_MONITOR_OUT_CONTROL_reserved1_SHIFT 1
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_MONITOR_OUT_CONTROL :: ENABLE [00:00] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_MONITOR_OUT_CONTROL_ENABLE_MASK 0x00000001
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_MONITOR_OUT_CONTROL_ENABLE_SHIFT 0
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_MONITOR_OUT_CONTROL_ENABLE_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_MONITOR_OUT_STATUS - PHY VDL delay monitoring output status register
- ***************************************************************************/
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_MONITOR_OUT_STATUS :: reserved0 [31:24] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_MONITOR_OUT_STATUS_reserved0_MASK 0xff000000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_MONITOR_OUT_STATUS_reserved0_SHIFT 24
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_MONITOR_OUT_STATUS :: MONITOR_CHANGE [23:16] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_MONITOR_OUT_STATUS_MONITOR_CHANGE_MASK 0x00ff0000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_MONITOR_OUT_STATUS_MONITOR_CHANGE_SHIFT 16
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_MONITOR_OUT_STATUS_MONITOR_CHANGE_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_MONITOR_OUT_STATUS :: reserved1 [15:14] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_MONITOR_OUT_STATUS_reserved1_MASK 0x0000c000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_MONITOR_OUT_STATUS_reserved1_SHIFT 14
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_MONITOR_OUT_STATUS :: MONITOR_TOTAL [13:04] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_MONITOR_OUT_STATUS_MONITOR_TOTAL_MASK 0x00003ff0
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_MONITOR_OUT_STATUS_MONITOR_TOTAL_SHIFT 4
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_MONITOR_OUT_STATUS_MONITOR_TOTAL_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_MONITOR_OUT_STATUS :: reserved2 [03:01] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_MONITOR_OUT_STATUS_reserved2_MASK 0x0000000e
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_MONITOR_OUT_STATUS_reserved2_SHIFT 1
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_MONITOR_OUT_STATUS :: VALID [00:00] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_MONITOR_OUT_STATUS_VALID_MASK 0x00000001
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_MONITOR_OUT_STATUS_VALID_SHIFT 0
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_MONITOR_OUT_STATUS_VALID_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_MONITOR_OUT_STATUS_CLEAR - PHY VDL delay monitoring output status clear register
- ***************************************************************************/
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_MONITOR_OUT_STATUS_CLEAR :: reserved0 [31:01] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_MONITOR_OUT_STATUS_CLEAR_reserved0_MASK 0xfffffffe
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_MONITOR_OUT_STATUS_CLEAR_reserved0_SHIFT 1
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_MONITOR_OUT_STATUS_CLEAR :: CLEAR [00:00] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_MONITOR_OUT_STATUS_CLEAR_CLEAR_MASK 0x00000001
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_MONITOR_OUT_STATUS_CLEAR_CLEAR_SHIFT 0
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_MONITOR_OUT_STATUS_CLEAR_CLEAR_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_AD00 - DDR interface signal AD[00] VDL control register
- ***************************************************************************/
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_AD00 :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD00_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD00_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD00_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_AD00 :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD00_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD00_reserved0_SHIFT 17
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_AD00 :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD00_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD00_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD00_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_AD00 :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD00_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD00_reserved1_SHIFT 13
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_AD00 :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD00_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD00_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD00_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_AD00 :: reserved2 [11:09] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD00_reserved2_MASK 0x00000e00
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD00_reserved2_SHIFT 9
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_AD00 :: VDL_STEP [08:00] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD00_VDL_STEP_MASK 0x000001ff
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD00_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD00_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_AD01 - DDR interface signal AD[01] VDL control register
- ***************************************************************************/
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_AD01 :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD01_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD01_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD01_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_AD01 :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD01_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD01_reserved0_SHIFT 17
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_AD01 :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD01_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD01_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD01_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_AD01 :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD01_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD01_reserved1_SHIFT 13
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_AD01 :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD01_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD01_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD01_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_AD01 :: reserved2 [11:09] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD01_reserved2_MASK 0x00000e00
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD01_reserved2_SHIFT 9
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_AD01 :: VDL_STEP [08:00] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD01_VDL_STEP_MASK 0x000001ff
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD01_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD01_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_AD02 - DDR interface signal AD[02] VDL control register
- ***************************************************************************/
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_AD02 :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD02_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD02_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD02_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_AD02 :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD02_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD02_reserved0_SHIFT 17
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_AD02 :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD02_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD02_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD02_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_AD02 :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD02_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD02_reserved1_SHIFT 13
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_AD02 :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD02_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD02_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD02_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_AD02 :: reserved2 [11:09] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD02_reserved2_MASK 0x00000e00
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD02_reserved2_SHIFT 9
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_AD02 :: VDL_STEP [08:00] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD02_VDL_STEP_MASK 0x000001ff
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD02_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD02_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_AD03 - DDR interface signal AD[03] VDL control register
- ***************************************************************************/
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_AD03 :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD03_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD03_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD03_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_AD03 :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD03_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD03_reserved0_SHIFT 17
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_AD03 :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD03_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD03_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD03_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_AD03 :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD03_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD03_reserved1_SHIFT 13
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_AD03 :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD03_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD03_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD03_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_AD03 :: reserved2 [11:09] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD03_reserved2_MASK 0x00000e00
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD03_reserved2_SHIFT 9
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_AD03 :: VDL_STEP [08:00] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD03_VDL_STEP_MASK 0x000001ff
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD03_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD03_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_AD04 - DDR interface signal AD[04] VDL control register
- ***************************************************************************/
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_AD04 :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD04_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD04_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD04_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_AD04 :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD04_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD04_reserved0_SHIFT 17
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_AD04 :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD04_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD04_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD04_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_AD04 :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD04_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD04_reserved1_SHIFT 13
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_AD04 :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD04_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD04_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD04_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_AD04 :: reserved2 [11:09] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD04_reserved2_MASK 0x00000e00
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD04_reserved2_SHIFT 9
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_AD04 :: VDL_STEP [08:00] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD04_VDL_STEP_MASK 0x000001ff
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD04_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD04_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_AD05 - DDR interface signal AD[05] VDL control register
- ***************************************************************************/
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_AD05 :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD05_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD05_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD05_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_AD05 :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD05_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD05_reserved0_SHIFT 17
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_AD05 :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD05_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD05_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD05_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_AD05 :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD05_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD05_reserved1_SHIFT 13
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_AD05 :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD05_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD05_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD05_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_AD05 :: reserved2 [11:09] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD05_reserved2_MASK 0x00000e00
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD05_reserved2_SHIFT 9
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_AD05 :: VDL_STEP [08:00] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD05_VDL_STEP_MASK 0x000001ff
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD05_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD05_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_AD06 - DDR interface signal AD[06] VDL control register
- ***************************************************************************/
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_AD06 :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD06_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD06_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD06_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_AD06 :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD06_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD06_reserved0_SHIFT 17
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_AD06 :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD06_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD06_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD06_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_AD06 :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD06_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD06_reserved1_SHIFT 13
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_AD06 :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD06_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD06_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD06_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_AD06 :: reserved2 [11:09] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD06_reserved2_MASK 0x00000e00
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD06_reserved2_SHIFT 9
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_AD06 :: VDL_STEP [08:00] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD06_VDL_STEP_MASK 0x000001ff
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD06_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD06_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_AD07 - DDR interface signal AD[07] VDL control register
- ***************************************************************************/
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_AD07 :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD07_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD07_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD07_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_AD07 :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD07_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD07_reserved0_SHIFT 17
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_AD07 :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD07_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD07_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD07_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_AD07 :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD07_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD07_reserved1_SHIFT 13
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_AD07 :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD07_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD07_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD07_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_AD07 :: reserved2 [11:09] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD07_reserved2_MASK 0x00000e00
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD07_reserved2_SHIFT 9
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_AD07 :: VDL_STEP [08:00] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD07_VDL_STEP_MASK 0x000001ff
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD07_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD07_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_AD08 - DDR interface signal AD[08] VDL control register
- ***************************************************************************/
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_AD08 :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD08_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD08_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD08_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_AD08 :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD08_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD08_reserved0_SHIFT 17
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_AD08 :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD08_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD08_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD08_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_AD08 :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD08_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD08_reserved1_SHIFT 13
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_AD08 :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD08_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD08_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD08_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_AD08 :: reserved2 [11:09] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD08_reserved2_MASK 0x00000e00
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD08_reserved2_SHIFT 9
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_AD08 :: VDL_STEP [08:00] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD08_VDL_STEP_MASK 0x000001ff
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD08_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD08_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_AD09 - DDR interface signal AD[09] VDL control register
- ***************************************************************************/
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_AD09 :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD09_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD09_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD09_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_AD09 :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD09_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD09_reserved0_SHIFT 17
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_AD09 :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD09_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD09_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD09_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_AD09 :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD09_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD09_reserved1_SHIFT 13
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_AD09 :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD09_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD09_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD09_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_AD09 :: reserved2 [11:09] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD09_reserved2_MASK 0x00000e00
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD09_reserved2_SHIFT 9
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_AD09 :: VDL_STEP [08:00] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD09_VDL_STEP_MASK 0x000001ff
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD09_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD09_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_AD10 - DDR interface signal AD[10] VDL control register
- ***************************************************************************/
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_AD10 :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD10_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD10_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD10_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_AD10 :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD10_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD10_reserved0_SHIFT 17
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_AD10 :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD10_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD10_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD10_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_AD10 :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD10_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD10_reserved1_SHIFT 13
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_AD10 :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD10_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD10_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD10_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_AD10 :: reserved2 [11:09] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD10_reserved2_MASK 0x00000e00
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD10_reserved2_SHIFT 9
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_AD10 :: VDL_STEP [08:00] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD10_VDL_STEP_MASK 0x000001ff
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD10_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD10_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_AD11 - DDR interface signal AD[11] VDL control register
- ***************************************************************************/
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_AD11 :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD11_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD11_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD11_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_AD11 :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD11_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD11_reserved0_SHIFT 17
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_AD11 :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD11_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD11_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD11_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_AD11 :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD11_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD11_reserved1_SHIFT 13
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_AD11 :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD11_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD11_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD11_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_AD11 :: reserved2 [11:09] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD11_reserved2_MASK 0x00000e00
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD11_reserved2_SHIFT 9
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_AD11 :: VDL_STEP [08:00] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD11_VDL_STEP_MASK 0x000001ff
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD11_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD11_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_AD12 - DDR interface signal AD[12] VDL control register
- ***************************************************************************/
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_AD12 :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD12_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD12_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD12_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_AD12 :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD12_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD12_reserved0_SHIFT 17
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_AD12 :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD12_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD12_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD12_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_AD12 :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD12_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD12_reserved1_SHIFT 13
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_AD12 :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD12_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD12_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD12_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_AD12 :: reserved2 [11:09] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD12_reserved2_MASK 0x00000e00
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD12_reserved2_SHIFT 9
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_AD12 :: VDL_STEP [08:00] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD12_VDL_STEP_MASK 0x000001ff
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD12_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD12_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_AD13 - DDR interface signal AD[13] VDL control register
- ***************************************************************************/
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_AD13 :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD13_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD13_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD13_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_AD13 :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD13_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD13_reserved0_SHIFT 17
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_AD13 :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD13_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD13_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD13_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_AD13 :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD13_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD13_reserved1_SHIFT 13
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_AD13 :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD13_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD13_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD13_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_AD13 :: reserved2 [11:09] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD13_reserved2_MASK 0x00000e00
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD13_reserved2_SHIFT 9
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_AD13 :: VDL_STEP [08:00] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD13_VDL_STEP_MASK 0x000001ff
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD13_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD13_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_AD14 - DDR interface signal AD[14] VDL control register
- ***************************************************************************/
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_AD14 :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD14_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD14_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD14_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_AD14 :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD14_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD14_reserved0_SHIFT 17
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_AD14 :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD14_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD14_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD14_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_AD14 :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD14_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD14_reserved1_SHIFT 13
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_AD14 :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD14_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD14_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD14_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_AD14 :: reserved2 [11:09] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD14_reserved2_MASK 0x00000e00
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD14_reserved2_SHIFT 9
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_AD14 :: VDL_STEP [08:00] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD14_VDL_STEP_MASK 0x000001ff
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD14_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD14_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_AD15 - DDR interface signal AD[15] VDL control register
- ***************************************************************************/
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_AD15 :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD15_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD15_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD15_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_AD15 :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD15_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD15_reserved0_SHIFT 17
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_AD15 :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD15_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD15_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD15_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_AD15 :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD15_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD15_reserved1_SHIFT 13
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_AD15 :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD15_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD15_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD15_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_AD15 :: reserved2 [11:09] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD15_reserved2_MASK 0x00000e00
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD15_reserved2_SHIFT 9
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_AD15 :: VDL_STEP [08:00] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD15_VDL_STEP_MASK 0x000001ff
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD15_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD15_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_BA0 - DDR interface signal BA[0] VDL control register
- ***************************************************************************/
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_BA0 :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_BA0_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_BA0_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_BA0_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_BA0 :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_BA0_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_BA0_reserved0_SHIFT 17
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_BA0 :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_BA0_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_BA0_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_BA0_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_BA0 :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_BA0_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_BA0_reserved1_SHIFT 13
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_BA0 :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_BA0_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_BA0_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_BA0_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_BA0 :: reserved2 [11:09] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_BA0_reserved2_MASK 0x00000e00
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_BA0_reserved2_SHIFT 9
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_BA0 :: VDL_STEP [08:00] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_BA0_VDL_STEP_MASK 0x000001ff
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_BA0_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_BA0_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_BA1 - DDR interface signal BA[1] VDL control register
- ***************************************************************************/
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_BA1 :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_BA1_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_BA1_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_BA1_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_BA1 :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_BA1_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_BA1_reserved0_SHIFT 17
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_BA1 :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_BA1_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_BA1_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_BA1_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_BA1 :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_BA1_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_BA1_reserved1_SHIFT 13
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_BA1 :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_BA1_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_BA1_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_BA1_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_BA1 :: reserved2 [11:09] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_BA1_reserved2_MASK 0x00000e00
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_BA1_reserved2_SHIFT 9
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_BA1 :: VDL_STEP [08:00] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_BA1_VDL_STEP_MASK 0x000001ff
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_BA1_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_BA1_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_BA2 - DDR interface signal BA[2] VDL control register
- ***************************************************************************/
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_BA2 :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_BA2_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_BA2_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_BA2_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_BA2 :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_BA2_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_BA2_reserved0_SHIFT 17
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_BA2 :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_BA2_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_BA2_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_BA2_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_BA2 :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_BA2_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_BA2_reserved1_SHIFT 13
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_BA2 :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_BA2_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_BA2_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_BA2_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_BA2 :: reserved2 [11:09] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_BA2_reserved2_MASK 0x00000e00
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_BA2_reserved2_SHIFT 9
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_BA2 :: VDL_STEP [08:00] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_BA2_VDL_STEP_MASK 0x000001ff
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_BA2_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_BA2_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_AUX0 - DDR interface signal AUX[0] VDL control register
- ***************************************************************************/
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_AUX0 :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AUX0_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AUX0_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AUX0_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_AUX0 :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AUX0_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AUX0_reserved0_SHIFT 17
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_AUX0 :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AUX0_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AUX0_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AUX0_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_AUX0 :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AUX0_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AUX0_reserved1_SHIFT 13
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_AUX0 :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AUX0_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AUX0_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AUX0_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_AUX0 :: reserved2 [11:09] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AUX0_reserved2_MASK 0x00000e00
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AUX0_reserved2_SHIFT 9
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_AUX0 :: VDL_STEP [08:00] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AUX0_VDL_STEP_MASK 0x000001ff
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AUX0_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AUX0_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_AUX1 - DDR interface signal AUX[1] VDL control register
- ***************************************************************************/
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_AUX1 :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AUX1_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AUX1_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AUX1_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_AUX1 :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AUX1_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AUX1_reserved0_SHIFT 17
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_AUX1 :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AUX1_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AUX1_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AUX1_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_AUX1 :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AUX1_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AUX1_reserved1_SHIFT 13
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_AUX1 :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AUX1_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AUX1_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AUX1_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_AUX1 :: reserved2 [11:09] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AUX1_reserved2_MASK 0x00000e00
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AUX1_reserved2_SHIFT 9
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_AUX1 :: VDL_STEP [08:00] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AUX1_VDL_STEP_MASK 0x000001ff
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AUX1_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AUX1_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_AUX2 - DDR interface signal AUX[2] VDL control register
- ***************************************************************************/
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_AUX2 :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AUX2_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AUX2_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AUX2_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_AUX2 :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AUX2_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AUX2_reserved0_SHIFT 17
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_AUX2 :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AUX2_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AUX2_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AUX2_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_AUX2 :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AUX2_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AUX2_reserved1_SHIFT 13
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_AUX2 :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AUX2_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AUX2_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AUX2_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_AUX2 :: reserved2 [11:09] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AUX2_reserved2_MASK 0x00000e00
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AUX2_reserved2_SHIFT 9
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_AUX2 :: VDL_STEP [08:00] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AUX2_VDL_STEP_MASK 0x000001ff
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AUX2_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AUX2_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_CS0 - DDR interface signal CS0 VDL control register
- ***************************************************************************/
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_CS0 :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_CS0_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_CS0_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_CS0_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_CS0 :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_CS0_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_CS0_reserved0_SHIFT 17
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_CS0 :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_CS0_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_CS0_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_CS0_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_CS0 :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_CS0_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_CS0_reserved1_SHIFT 13
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_CS0 :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_CS0_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_CS0_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_CS0_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_CS0 :: reserved2 [11:09] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_CS0_reserved2_MASK 0x00000e00
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_CS0_reserved2_SHIFT 9
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_CS0 :: VDL_STEP [08:00] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_CS0_VDL_STEP_MASK 0x000001ff
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_CS0_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_CS0_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_CS1 - DDR interface signal CS1 VDL control register
- ***************************************************************************/
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_CS1 :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_CS1_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_CS1_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_CS1_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_CS1 :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_CS1_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_CS1_reserved0_SHIFT 17
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_CS1 :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_CS1_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_CS1_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_CS1_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_CS1 :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_CS1_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_CS1_reserved1_SHIFT 13
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_CS1 :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_CS1_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_CS1_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_CS1_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_CS1 :: reserved2 [11:09] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_CS1_reserved2_MASK 0x00000e00
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_CS1_reserved2_SHIFT 9
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_CS1 :: VDL_STEP [08:00] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_CS1_VDL_STEP_MASK 0x000001ff
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_CS1_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_CS1_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_PAR - DDR interface signal PAR VDL control register
- ***************************************************************************/
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_PAR :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_PAR_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_PAR_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_PAR_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_PAR :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_PAR_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_PAR_reserved0_SHIFT 17
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_PAR :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_PAR_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_PAR_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_PAR_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_PAR :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_PAR_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_PAR_reserved1_SHIFT 13
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_PAR :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_PAR_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_PAR_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_PAR_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_PAR :: reserved2 [11:09] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_PAR_reserved2_MASK 0x00000e00
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_PAR_reserved2_SHIFT 9
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_PAR :: VDL_STEP [08:00] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_PAR_VDL_STEP_MASK 0x000001ff
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_PAR_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_PAR_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_RAS_N - DDR interface signal RAS_N VDL control register
- ***************************************************************************/
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_RAS_N :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_RAS_N_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_RAS_N_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_RAS_N_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_RAS_N :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_RAS_N_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_RAS_N_reserved0_SHIFT 17
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_RAS_N :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_RAS_N_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_RAS_N_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_RAS_N_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_RAS_N :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_RAS_N_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_RAS_N_reserved1_SHIFT 13
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_RAS_N :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_RAS_N_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_RAS_N_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_RAS_N_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_RAS_N :: reserved2 [11:09] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_RAS_N_reserved2_MASK 0x00000e00
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_RAS_N_reserved2_SHIFT 9
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_RAS_N :: VDL_STEP [08:00] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_RAS_N_VDL_STEP_MASK 0x000001ff
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_RAS_N_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_RAS_N_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_CAS_N - DDR interface signal CAS_N VDL control register
- ***************************************************************************/
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_CAS_N :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_CAS_N_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_CAS_N_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_CAS_N_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_CAS_N :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_CAS_N_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_CAS_N_reserved0_SHIFT 17
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_CAS_N :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_CAS_N_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_CAS_N_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_CAS_N_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_CAS_N :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_CAS_N_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_CAS_N_reserved1_SHIFT 13
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_CAS_N :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_CAS_N_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_CAS_N_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_CAS_N_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_CAS_N :: reserved2 [11:09] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_CAS_N_reserved2_MASK 0x00000e00
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_CAS_N_reserved2_SHIFT 9
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_CAS_N :: VDL_STEP [08:00] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_CAS_N_VDL_STEP_MASK 0x000001ff
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_CAS_N_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_CAS_N_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_CKE - DDR interface signal CKE0 VDL control register
- ***************************************************************************/
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_CKE :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_CKE_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_CKE_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_CKE_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_CKE :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_CKE_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_CKE_reserved0_SHIFT 17
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_CKE :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_CKE_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_CKE_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_CKE_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_CKE :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_CKE_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_CKE_reserved1_SHIFT 13
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_CKE :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_CKE_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_CKE_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_CKE_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_CKE :: reserved2 [11:09] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_CKE_reserved2_MASK 0x00000e00
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_CKE_reserved2_SHIFT 9
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_CKE :: VDL_STEP [08:00] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_CKE_VDL_STEP_MASK 0x000001ff
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_CKE_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_CKE_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_RST_N - DDR interface signal RST_N VDL control register
- ***************************************************************************/
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_RST_N :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_RST_N_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_RST_N_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_RST_N_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_RST_N :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_RST_N_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_RST_N_reserved0_SHIFT 17
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_RST_N :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_RST_N_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_RST_N_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_RST_N_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_RST_N :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_RST_N_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_RST_N_reserved1_SHIFT 13
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_RST_N :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_RST_N_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_RST_N_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_RST_N_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_RST_N :: reserved2 [11:09] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_RST_N_reserved2_MASK 0x00000e00
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_RST_N_reserved2_SHIFT 9
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_RST_N :: VDL_STEP [08:00] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_RST_N_VDL_STEP_MASK 0x000001ff
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_RST_N_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_RST_N_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_ODT - DDR interface signal ODT0 VDL control register
- ***************************************************************************/
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_ODT :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_ODT_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_ODT_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_ODT_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_ODT :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_ODT_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_ODT_reserved0_SHIFT 17
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_ODT :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_ODT_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_ODT_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_ODT_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_ODT :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_ODT_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_ODT_reserved1_SHIFT 13
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_ODT :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_ODT_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_ODT_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_ODT_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_ODT :: reserved2 [11:09] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_ODT_reserved2_MASK 0x00000e00
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_ODT_reserved2_SHIFT 9
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_ODT :: VDL_STEP [08:00] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_ODT_VDL_STEP_MASK 0x000001ff
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_ODT_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_ODT_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_WE_N - DDR interface signal WE_N VDL control register
- ***************************************************************************/
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_WE_N :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_WE_N_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_WE_N_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_WE_N_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_WE_N :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_WE_N_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_WE_N_reserved0_SHIFT 17
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_WE_N :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_WE_N_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_WE_N_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_WE_N_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_WE_N :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_WE_N_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_WE_N_reserved1_SHIFT 13
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_WE_N :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_WE_N_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_WE_N_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_WE_N_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_WE_N :: reserved2 [11:09] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_WE_N_reserved2_MASK 0x00000e00
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_WE_N_reserved2_SHIFT 9
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_WE_N :: VDL_STEP [08:00] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_WE_N_VDL_STEP_MASK 0x000001ff
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_WE_N_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_WE_N_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_DDR_CK_P - DDR interface signal DDR_CK-P VDL control register
- ***************************************************************************/
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_DDR_CK_P :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_DDR_CK_P_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_DDR_CK_P_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_DDR_CK_P_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_DDR_CK_P :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_DDR_CK_P_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_DDR_CK_P_reserved0_SHIFT 17
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_DDR_CK_P :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_DDR_CK_P_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_DDR_CK_P_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_DDR_CK_P_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_DDR_CK_P :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_DDR_CK_P_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_DDR_CK_P_reserved1_SHIFT 13
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_DDR_CK_P :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_DDR_CK_P_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_DDR_CK_P_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_DDR_CK_P_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_DDR_CK_P :: reserved2 [11:09] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_DDR_CK_P_reserved2_MASK 0x00000e00
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_DDR_CK_P_reserved2_SHIFT 9
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_DDR_CK_P :: VDL_STEP [08:00] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_DDR_CK_P_VDL_STEP_MASK 0x000001ff
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_DDR_CK_P_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_DDR_CK_P_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_DDR_CK_N - DDR interface signal DDR_CK-N VDL control register
- ***************************************************************************/
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_DDR_CK_N :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_DDR_CK_N_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_DDR_CK_N_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_DDR_CK_N_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_DDR_CK_N :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_DDR_CK_N_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_DDR_CK_N_reserved0_SHIFT 17
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_DDR_CK_N :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_DDR_CK_N_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_DDR_CK_N_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_DDR_CK_N_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_DDR_CK_N :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_DDR_CK_N_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_DDR_CK_N_reserved1_SHIFT 13
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_DDR_CK_N :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_DDR_CK_N_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_DDR_CK_N_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_DDR_CK_N_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_DDR_CK_N :: reserved2 [11:09] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_DDR_CK_N_reserved2_MASK 0x00000e00
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_DDR_CK_N_reserved2_SHIFT 9
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_DDR_CK_N :: VDL_STEP [08:00] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_DDR_CK_N_VDL_STEP_MASK 0x000001ff
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_DDR_CK_N_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_DDR_CK_N_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CLK_CONTROL - DDR interface signal Write Leveling CLK VDL control register
- ***************************************************************************/
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CLK_CONTROL :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CLK_CONTROL_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CLK_CONTROL_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CLK_CONTROL_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CLK_CONTROL :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CLK_CONTROL_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CLK_CONTROL_reserved0_SHIFT 17
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CLK_CONTROL :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CLK_CONTROL_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CLK_CONTROL_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CLK_CONTROL_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CLK_CONTROL :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CLK_CONTROL_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CLK_CONTROL_reserved1_SHIFT 13
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CLK_CONTROL :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CLK_CONTROL_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CLK_CONTROL_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CLK_CONTROL_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CLK_CONTROL :: reserved2 [11:09] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CLK_CONTROL_reserved2_MASK 0x00000e00
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CLK_CONTROL_reserved2_SHIFT 9
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CLK_CONTROL :: VDL_STEP [08:00] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CLK_CONTROL_VDL_STEP_MASK 0x000001ff
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CLK_CONTROL_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CLK_CONTROL_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_LDE_CONTROL - DDR interface signal Write Leveling Capture Enable VDL control register
- ***************************************************************************/
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_LDE_CONTROL :: BUSY [31:31] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_LDE_CONTROL_BUSY_MASK 0x80000000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_LDE_CONTROL_BUSY_SHIFT 31
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_LDE_CONTROL_BUSY_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_LDE_CONTROL :: reserved0 [30:17] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_LDE_CONTROL_reserved0_MASK 0x7ffe0000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_LDE_CONTROL_reserved0_SHIFT 17
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_LDE_CONTROL :: FORCE [16:16] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_LDE_CONTROL_FORCE_MASK 0x00010000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_LDE_CONTROL_FORCE_SHIFT 16
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_LDE_CONTROL_FORCE_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_LDE_CONTROL :: reserved1 [15:13] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_LDE_CONTROL_reserved1_MASK 0x0000e000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_LDE_CONTROL_reserved1_SHIFT 13
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_LDE_CONTROL :: ADJ_EN [12:12] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_LDE_CONTROL_ADJ_EN_MASK 0x00001000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_LDE_CONTROL_ADJ_EN_SHIFT 12
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_LDE_CONTROL_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_LDE_CONTROL :: reserved2 [11:09] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_LDE_CONTROL_reserved2_MASK 0x00000e00
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_LDE_CONTROL_reserved2_SHIFT 9
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VDL_LDE_CONTROL :: VDL_STEP [08:00] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_LDE_CONTROL_VDL_STEP_MASK 0x000001ff
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_LDE_CONTROL_VDL_STEP_SHIFT 0
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_LDE_CONTROL_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *REFRESH - Refresh engine controller
- ***************************************************************************/
-/* DDR34_PHY_CONTROL_REGS_0 :: REFRESH :: reserved0 [31:17] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_REFRESH_reserved0_MASK 0xfffe0000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_REFRESH_reserved0_SHIFT 17
-
-/* DDR34_PHY_CONTROL_REGS_0 :: REFRESH :: ENABLE [16:16] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_REFRESH_ENABLE_MASK 0x00010000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_REFRESH_ENABLE_SHIFT 16
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_REFRESH_ENABLE_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: REFRESH :: PERIOD [15:00] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_REFRESH_PERIOD_MASK 0x0000ffff
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_REFRESH_PERIOD_SHIFT 0
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_REFRESH_PERIOD_DEFAULT 0x00000000
-
-/***************************************************************************
- *UPDATE_VDL - Update VDL control register
- ***************************************************************************/
-/* DDR34_PHY_CONTROL_REGS_0 :: UPDATE_VDL :: reserved0 [31:06] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_UPDATE_VDL_reserved0_MASK 0xffffffc0
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_UPDATE_VDL_reserved0_SHIFT 6
-
-/* DDR34_PHY_CONTROL_REGS_0 :: UPDATE_VDL :: MODE [05:04] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_UPDATE_VDL_MODE_MASK 0x00000030
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_UPDATE_VDL_MODE_SHIFT 4
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_UPDATE_VDL_MODE_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: UPDATE_VDL :: reserved1 [03:02] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_UPDATE_VDL_reserved1_MASK 0x0000000c
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_UPDATE_VDL_reserved1_SHIFT 2
-
-/* DDR34_PHY_CONTROL_REGS_0 :: UPDATE_VDL :: DISABLE_INPUT [01:01] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_UPDATE_VDL_DISABLE_INPUT_MASK 0x00000002
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_UPDATE_VDL_DISABLE_INPUT_SHIFT 1
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_UPDATE_VDL_DISABLE_INPUT_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: UPDATE_VDL :: ENABLE [00:00] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_UPDATE_VDL_ENABLE_MASK 0x00000001
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_UPDATE_VDL_ENABLE_SHIFT 0
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_UPDATE_VDL_ENABLE_DEFAULT 0x00000000
-
-/***************************************************************************
- *UPDATE_VDL_SNOOP1 - Update VDL snoop control register #1
- ***************************************************************************/
-/* DDR34_PHY_CONTROL_REGS_0 :: UPDATE_VDL_SNOOP1 :: reserved0 [31:30] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_UPDATE_VDL_SNOOP1_reserved0_MASK 0xc0000000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_UPDATE_VDL_SNOOP1_reserved0_SHIFT 30
-
-/* DDR34_PHY_CONTROL_REGS_0 :: UPDATE_VDL_SNOOP1 :: MODE [29:28] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_UPDATE_VDL_SNOOP1_MODE_MASK 0x30000000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_UPDATE_VDL_SNOOP1_MODE_SHIFT 28
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_UPDATE_VDL_SNOOP1_MODE_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: UPDATE_VDL_SNOOP1 :: reserved1 [27:27] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_UPDATE_VDL_SNOOP1_reserved1_MASK 0x08000000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_UPDATE_VDL_SNOOP1_reserved1_SHIFT 27
-
-/* DDR34_PHY_CONTROL_REGS_0 :: UPDATE_VDL_SNOOP1 :: MASK [26:16] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_UPDATE_VDL_SNOOP1_MASK_MASK 0x07ff0000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_UPDATE_VDL_SNOOP1_MASK_SHIFT 16
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_UPDATE_VDL_SNOOP1_MASK_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: UPDATE_VDL_SNOOP1 :: reserved2 [15:15] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_UPDATE_VDL_SNOOP1_reserved2_MASK 0x00008000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_UPDATE_VDL_SNOOP1_reserved2_SHIFT 15
-
-/* DDR34_PHY_CONTROL_REGS_0 :: UPDATE_VDL_SNOOP1 :: CMD [14:04] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_UPDATE_VDL_SNOOP1_CMD_MASK 0x00007ff0
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_UPDATE_VDL_SNOOP1_CMD_SHIFT 4
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_UPDATE_VDL_SNOOP1_CMD_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: UPDATE_VDL_SNOOP1 :: reserved3 [03:01] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_UPDATE_VDL_SNOOP1_reserved3_MASK 0x0000000e
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_UPDATE_VDL_SNOOP1_reserved3_SHIFT 1
-
-/* DDR34_PHY_CONTROL_REGS_0 :: UPDATE_VDL_SNOOP1 :: ENABLE [00:00] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_UPDATE_VDL_SNOOP1_ENABLE_MASK 0x00000001
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_UPDATE_VDL_SNOOP1_ENABLE_SHIFT 0
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_UPDATE_VDL_SNOOP1_ENABLE_DEFAULT 0x00000000
-
-/***************************************************************************
- *UPDATE_VDL_SNOOP2 - Update VDL snoop control register #2
- ***************************************************************************/
-/* DDR34_PHY_CONTROL_REGS_0 :: UPDATE_VDL_SNOOP2 :: reserved0 [31:30] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_UPDATE_VDL_SNOOP2_reserved0_MASK 0xc0000000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_UPDATE_VDL_SNOOP2_reserved0_SHIFT 30
-
-/* DDR34_PHY_CONTROL_REGS_0 :: UPDATE_VDL_SNOOP2 :: MODE [29:28] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_UPDATE_VDL_SNOOP2_MODE_MASK 0x30000000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_UPDATE_VDL_SNOOP2_MODE_SHIFT 28
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_UPDATE_VDL_SNOOP2_MODE_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: UPDATE_VDL_SNOOP2 :: reserved1 [27:27] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_UPDATE_VDL_SNOOP2_reserved1_MASK 0x08000000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_UPDATE_VDL_SNOOP2_reserved1_SHIFT 27
-
-/* DDR34_PHY_CONTROL_REGS_0 :: UPDATE_VDL_SNOOP2 :: MASK [26:16] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_UPDATE_VDL_SNOOP2_MASK_MASK 0x07ff0000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_UPDATE_VDL_SNOOP2_MASK_SHIFT 16
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_UPDATE_VDL_SNOOP2_MASK_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: UPDATE_VDL_SNOOP2 :: reserved2 [15:15] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_UPDATE_VDL_SNOOP2_reserved2_MASK 0x00008000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_UPDATE_VDL_SNOOP2_reserved2_SHIFT 15
-
-/* DDR34_PHY_CONTROL_REGS_0 :: UPDATE_VDL_SNOOP2 :: CMD [14:04] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_UPDATE_VDL_SNOOP2_CMD_MASK 0x00007ff0
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_UPDATE_VDL_SNOOP2_CMD_SHIFT 4
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_UPDATE_VDL_SNOOP2_CMD_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: UPDATE_VDL_SNOOP2 :: reserved3 [03:01] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_UPDATE_VDL_SNOOP2_reserved3_MASK 0x0000000e
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_UPDATE_VDL_SNOOP2_reserved3_SHIFT 1
-
-/* DDR34_PHY_CONTROL_REGS_0 :: UPDATE_VDL_SNOOP2 :: ENABLE [00:00] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_UPDATE_VDL_SNOOP2_ENABLE_MASK 0x00000001
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_UPDATE_VDL_SNOOP2_ENABLE_SHIFT 0
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_UPDATE_VDL_SNOOP2_ENABLE_DEFAULT 0x00000000
-
-/***************************************************************************
- *COMMAND_REG1 - DRAM Command Register #1
- ***************************************************************************/
-/* DDR34_PHY_CONTROL_REGS_0 :: COMMAND_REG1 :: MCP [31:31] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_REG1_MCP_MASK 0x80000000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_REG1_MCP_SHIFT 31
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_REG1_MCP_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: COMMAND_REG1 :: CS [30:29] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_REG1_CS_MASK 0x60000000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_REG1_CS_SHIFT 29
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_REG1_CS_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: COMMAND_REG1 :: AUX [28:24] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_REG1_AUX_MASK 0x1f000000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_REG1_AUX_SHIFT 24
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_REG1_AUX_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: COMMAND_REG1 :: ACT [23:23] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_REG1_ACT_MASK 0x00800000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_REG1_ACT_SHIFT 23
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_REG1_ACT_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: COMMAND_REG1 :: WE [22:22] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_REG1_WE_MASK 0x00400000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_REG1_WE_SHIFT 22
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_REG1_WE_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: COMMAND_REG1 :: CAS [21:21] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_REG1_CAS_MASK 0x00200000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_REG1_CAS_SHIFT 21
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_REG1_CAS_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: COMMAND_REG1 :: RAS [20:20] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_REG1_RAS_MASK 0x00100000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_REG1_RAS_SHIFT 20
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_REG1_RAS_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: COMMAND_REG1 :: BA [19:16] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_REG1_BA_MASK 0x000f0000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_REG1_BA_SHIFT 16
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_REG1_BA_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: COMMAND_REG1 :: AD [15:00] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_REG1_AD_MASK 0x0000ffff
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_REG1_AD_SHIFT 0
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_REG1_AD_DEFAULT 0x00000000
-
-/***************************************************************************
- *COMMAND_AUX_REG1 - DRAM AUX_N Command Register #1
- ***************************************************************************/
-/* DDR34_PHY_CONTROL_REGS_0 :: COMMAND_AUX_REG1 :: reserved0 [31:05] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_AUX_REG1_reserved0_MASK 0xffffffe0
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_AUX_REG1_reserved0_SHIFT 5
-
-/* DDR34_PHY_CONTROL_REGS_0 :: COMMAND_AUX_REG1 :: AUX [04:00] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_AUX_REG1_AUX_MASK 0x0000001f
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_AUX_REG1_AUX_SHIFT 0
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_AUX_REG1_AUX_DEFAULT 0x00000000
-
-/***************************************************************************
- *COMMAND_REG2 - DRAM Command Register #2
- ***************************************************************************/
-/* DDR34_PHY_CONTROL_REGS_0 :: COMMAND_REG2 :: MCP [31:31] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_REG2_MCP_MASK 0x80000000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_REG2_MCP_SHIFT 31
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_REG2_MCP_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: COMMAND_REG2 :: CS [30:29] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_REG2_CS_MASK 0x60000000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_REG2_CS_SHIFT 29
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_REG2_CS_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: COMMAND_REG2 :: AUX [28:24] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_REG2_AUX_MASK 0x1f000000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_REG2_AUX_SHIFT 24
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_REG2_AUX_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: COMMAND_REG2 :: ACT [23:23] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_REG2_ACT_MASK 0x00800000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_REG2_ACT_SHIFT 23
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_REG2_ACT_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: COMMAND_REG2 :: WE [22:22] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_REG2_WE_MASK 0x00400000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_REG2_WE_SHIFT 22
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_REG2_WE_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: COMMAND_REG2 :: CAS [21:21] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_REG2_CAS_MASK 0x00200000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_REG2_CAS_SHIFT 21
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_REG2_CAS_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: COMMAND_REG2 :: RAS [20:20] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_REG2_RAS_MASK 0x00100000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_REG2_RAS_SHIFT 20
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_REG2_RAS_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: COMMAND_REG2 :: BA [19:16] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_REG2_BA_MASK 0x000f0000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_REG2_BA_SHIFT 16
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_REG2_BA_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: COMMAND_REG2 :: AD [15:00] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_REG2_AD_MASK 0x0000ffff
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_REG2_AD_SHIFT 0
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_REG2_AD_DEFAULT 0x00000000
-
-/***************************************************************************
- *COMMAND_AUX_REG2 - DRAM AUX_N Command Register #2
- ***************************************************************************/
-/* DDR34_PHY_CONTROL_REGS_0 :: COMMAND_AUX_REG2 :: reserved0 [31:05] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_AUX_REG2_reserved0_MASK 0xffffffe0
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_AUX_REG2_reserved0_SHIFT 5
-
-/* DDR34_PHY_CONTROL_REGS_0 :: COMMAND_AUX_REG2 :: AUX [04:00] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_AUX_REG2_AUX_MASK 0x0000001f
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_AUX_REG2_AUX_SHIFT 0
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_AUX_REG2_AUX_DEFAULT 0x00000000
-
-/***************************************************************************
- *COMMAND_REG3 - DRAM Command Register #3
- ***************************************************************************/
-/* DDR34_PHY_CONTROL_REGS_0 :: COMMAND_REG3 :: MCP [31:31] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_REG3_MCP_MASK 0x80000000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_REG3_MCP_SHIFT 31
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_REG3_MCP_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: COMMAND_REG3 :: CS [30:29] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_REG3_CS_MASK 0x60000000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_REG3_CS_SHIFT 29
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_REG3_CS_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: COMMAND_REG3 :: AUX [28:24] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_REG3_AUX_MASK 0x1f000000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_REG3_AUX_SHIFT 24
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_REG3_AUX_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: COMMAND_REG3 :: ACT [23:23] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_REG3_ACT_MASK 0x00800000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_REG3_ACT_SHIFT 23
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_REG3_ACT_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: COMMAND_REG3 :: WE [22:22] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_REG3_WE_MASK 0x00400000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_REG3_WE_SHIFT 22
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_REG3_WE_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: COMMAND_REG3 :: CAS [21:21] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_REG3_CAS_MASK 0x00200000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_REG3_CAS_SHIFT 21
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_REG3_CAS_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: COMMAND_REG3 :: RAS [20:20] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_REG3_RAS_MASK 0x00100000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_REG3_RAS_SHIFT 20
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_REG3_RAS_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: COMMAND_REG3 :: BA [19:16] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_REG3_BA_MASK 0x000f0000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_REG3_BA_SHIFT 16
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_REG3_BA_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: COMMAND_REG3 :: AD [15:00] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_REG3_AD_MASK 0x0000ffff
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_REG3_AD_SHIFT 0
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_REG3_AD_DEFAULT 0x00000000
-
-/***************************************************************************
- *COMMAND_AUX_REG3 - DRAM AUX_N Command Register #3
- ***************************************************************************/
-/* DDR34_PHY_CONTROL_REGS_0 :: COMMAND_AUX_REG3 :: reserved0 [31:05] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_AUX_REG3_reserved0_MASK 0xffffffe0
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_AUX_REG3_reserved0_SHIFT 5
-
-/* DDR34_PHY_CONTROL_REGS_0 :: COMMAND_AUX_REG3 :: AUX [04:00] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_AUX_REG3_AUX_MASK 0x0000001f
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_AUX_REG3_AUX_SHIFT 0
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_AUX_REG3_AUX_DEFAULT 0x00000000
-
-/***************************************************************************
- *COMMAND_REG4 - DRAM Command Register #4
- ***************************************************************************/
-/* DDR34_PHY_CONTROL_REGS_0 :: COMMAND_REG4 :: MCP [31:31] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_REG4_MCP_MASK 0x80000000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_REG4_MCP_SHIFT 31
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_REG4_MCP_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: COMMAND_REG4 :: CS [30:29] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_REG4_CS_MASK 0x60000000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_REG4_CS_SHIFT 29
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_REG4_CS_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: COMMAND_REG4 :: AUX [28:24] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_REG4_AUX_MASK 0x1f000000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_REG4_AUX_SHIFT 24
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_REG4_AUX_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: COMMAND_REG4 :: ACT [23:23] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_REG4_ACT_MASK 0x00800000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_REG4_ACT_SHIFT 23
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_REG4_ACT_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: COMMAND_REG4 :: WE [22:22] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_REG4_WE_MASK 0x00400000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_REG4_WE_SHIFT 22
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_REG4_WE_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: COMMAND_REG4 :: CAS [21:21] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_REG4_CAS_MASK 0x00200000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_REG4_CAS_SHIFT 21
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_REG4_CAS_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: COMMAND_REG4 :: RAS [20:20] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_REG4_RAS_MASK 0x00100000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_REG4_RAS_SHIFT 20
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_REG4_RAS_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: COMMAND_REG4 :: BA [19:16] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_REG4_BA_MASK 0x000f0000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_REG4_BA_SHIFT 16
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_REG4_BA_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: COMMAND_REG4 :: AD [15:00] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_REG4_AD_MASK 0x0000ffff
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_REG4_AD_SHIFT 0
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_REG4_AD_DEFAULT 0x00000000
-
-/***************************************************************************
- *COMMAND_AUX_REG4 - DRAM AUX_N Command Register #4
- ***************************************************************************/
-/* DDR34_PHY_CONTROL_REGS_0 :: COMMAND_AUX_REG4 :: reserved0 [31:05] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_AUX_REG4_reserved0_MASK 0xffffffe0
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_AUX_REG4_reserved0_SHIFT 5
-
-/* DDR34_PHY_CONTROL_REGS_0 :: COMMAND_AUX_REG4 :: AUX [04:00] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_AUX_REG4_AUX_MASK 0x0000001f
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_AUX_REG4_AUX_SHIFT 0
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_AUX_REG4_AUX_DEFAULT 0x00000000
-
-/***************************************************************************
- *COMMAND_REG_TIMER - DRAM Command Timer Register
- ***************************************************************************/
-/* DDR34_PHY_CONTROL_REGS_0 :: COMMAND_REG_TIMER :: reserved0 [31:16] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_REG_TIMER_reserved0_MASK 0xffff0000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_REG_TIMER_reserved0_SHIFT 16
-
-/* DDR34_PHY_CONTROL_REGS_0 :: COMMAND_REG_TIMER :: INIT_VAL [15:08] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_REG_TIMER_INIT_VAL_MASK 0x0000ff00
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_REG_TIMER_INIT_VAL_SHIFT 8
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_REG_TIMER_INIT_VAL_DEFAULT 0x0000000f
-
-/* DDR34_PHY_CONTROL_REGS_0 :: COMMAND_REG_TIMER :: COUNT [07:00] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_REG_TIMER_COUNT_MASK 0x000000ff
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_REG_TIMER_COUNT_SHIFT 0
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_REG_TIMER_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *MODE_REG0 - DDR3/DDR4/GDDR5 Mode Register 0 and LPDDR Mode Register 1
- ***************************************************************************/
-/* DDR34_PHY_CONTROL_REGS_0 :: MODE_REG0 :: reserved0 [31:21] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_MODE_REG0_reserved0_MASK 0xffe00000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_MODE_REG0_reserved0_SHIFT 21
-
-/* DDR34_PHY_CONTROL_REGS_0 :: MODE_REG0 :: reserved_for_eco1 [20:17] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_MODE_REG0_reserved_for_eco1_MASK 0x001e0000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_MODE_REG0_reserved_for_eco1_SHIFT 17
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_MODE_REG0_reserved_for_eco1_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: MODE_REG0 :: VALID [16:16] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_MODE_REG0_VALID_MASK 0x00010000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_MODE_REG0_VALID_SHIFT 16
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_MODE_REG0_VALID_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: MODE_REG0 :: AD [15:00] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_MODE_REG0_AD_MASK 0x0000ffff
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_MODE_REG0_AD_SHIFT 0
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_MODE_REG0_AD_DEFAULT 0x00000000
-
-/***************************************************************************
- *MODE_REG1 - DDR3/DDR4/GDDR5 Mode Register 1 and LPDDR Mode Register 2
- ***************************************************************************/
-/* DDR34_PHY_CONTROL_REGS_0 :: MODE_REG1 :: reserved0 [31:21] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_MODE_REG1_reserved0_MASK 0xffe00000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_MODE_REG1_reserved0_SHIFT 21
-
-/* DDR34_PHY_CONTROL_REGS_0 :: MODE_REG1 :: reserved_for_eco1 [20:17] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_MODE_REG1_reserved_for_eco1_MASK 0x001e0000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_MODE_REG1_reserved_for_eco1_SHIFT 17
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_MODE_REG1_reserved_for_eco1_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: MODE_REG1 :: VALID [16:16] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_MODE_REG1_VALID_MASK 0x00010000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_MODE_REG1_VALID_SHIFT 16
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_MODE_REG1_VALID_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: MODE_REG1 :: AD [15:00] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_MODE_REG1_AD_MASK 0x0000ffff
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_MODE_REG1_AD_SHIFT 0
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_MODE_REG1_AD_DEFAULT 0x00000000
-
-/***************************************************************************
- *MODE_REG2 - DDR3/DDR4/GDDR5 Mode Register 2 and LPDDR Mode Register 3
- ***************************************************************************/
-/* DDR34_PHY_CONTROL_REGS_0 :: MODE_REG2 :: reserved0 [31:21] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_MODE_REG2_reserved0_MASK 0xffe00000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_MODE_REG2_reserved0_SHIFT 21
-
-/* DDR34_PHY_CONTROL_REGS_0 :: MODE_REG2 :: reserved_for_eco1 [20:17] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_MODE_REG2_reserved_for_eco1_MASK 0x001e0000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_MODE_REG2_reserved_for_eco1_SHIFT 17
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_MODE_REG2_reserved_for_eco1_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: MODE_REG2 :: VALID [16:16] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_MODE_REG2_VALID_MASK 0x00010000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_MODE_REG2_VALID_SHIFT 16
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_MODE_REG2_VALID_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: MODE_REG2 :: AD [15:00] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_MODE_REG2_AD_MASK 0x0000ffff
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_MODE_REG2_AD_SHIFT 0
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_MODE_REG2_AD_DEFAULT 0x00000000
-
-/***************************************************************************
- *MODE_REG3 - DDR3/DDR4/GDDR5 Mode Register 3 and LPDDR Mode Register 9
- ***************************************************************************/
-/* DDR34_PHY_CONTROL_REGS_0 :: MODE_REG3 :: reserved0 [31:21] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_MODE_REG3_reserved0_MASK 0xffe00000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_MODE_REG3_reserved0_SHIFT 21
-
-/* DDR34_PHY_CONTROL_REGS_0 :: MODE_REG3 :: reserved_for_eco1 [20:17] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_MODE_REG3_reserved_for_eco1_MASK 0x001e0000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_MODE_REG3_reserved_for_eco1_SHIFT 17
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_MODE_REG3_reserved_for_eco1_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: MODE_REG3 :: VALID [16:16] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_MODE_REG3_VALID_MASK 0x00010000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_MODE_REG3_VALID_SHIFT 16
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_MODE_REG3_VALID_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: MODE_REG3 :: AD [15:00] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_MODE_REG3_AD_MASK 0x0000ffff
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_MODE_REG3_AD_SHIFT 0
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_MODE_REG3_AD_DEFAULT 0x00000000
-
-/***************************************************************************
- *MODE_REG4 - DDR4/GDDR5 Mode Register 4 and LPDDR Mode Register 10
- ***************************************************************************/
-/* DDR34_PHY_CONTROL_REGS_0 :: MODE_REG4 :: reserved0 [31:21] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_MODE_REG4_reserved0_MASK 0xffe00000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_MODE_REG4_reserved0_SHIFT 21
-
-/* DDR34_PHY_CONTROL_REGS_0 :: MODE_REG4 :: reserved_for_eco1 [20:17] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_MODE_REG4_reserved_for_eco1_MASK 0x001e0000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_MODE_REG4_reserved_for_eco1_SHIFT 17
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_MODE_REG4_reserved_for_eco1_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: MODE_REG4 :: VALID [16:16] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_MODE_REG4_VALID_MASK 0x00010000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_MODE_REG4_VALID_SHIFT 16
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_MODE_REG4_VALID_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: MODE_REG4 :: AD [15:00] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_MODE_REG4_AD_MASK 0x0000ffff
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_MODE_REG4_AD_SHIFT 0
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_MODE_REG4_AD_DEFAULT 0x00000000
-
-/***************************************************************************
- *MODE_REG5 - DDR4/GDDR5 Mode Register 5 and LPDDR Mode Register 16
- ***************************************************************************/
-/* DDR34_PHY_CONTROL_REGS_0 :: MODE_REG5 :: reserved0 [31:21] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_MODE_REG5_reserved0_MASK 0xffe00000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_MODE_REG5_reserved0_SHIFT 21
-
-/* DDR34_PHY_CONTROL_REGS_0 :: MODE_REG5 :: reserved_for_eco1 [20:17] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_MODE_REG5_reserved_for_eco1_MASK 0x001e0000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_MODE_REG5_reserved_for_eco1_SHIFT 17
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_MODE_REG5_reserved_for_eco1_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: MODE_REG5 :: VALID [16:16] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_MODE_REG5_VALID_MASK 0x00010000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_MODE_REG5_VALID_SHIFT 16
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_MODE_REG5_VALID_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: MODE_REG5 :: AD [15:00] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_MODE_REG5_AD_MASK 0x0000ffff
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_MODE_REG5_AD_SHIFT 0
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_MODE_REG5_AD_DEFAULT 0x00000000
-
-/***************************************************************************
- *MODE_REG6 - DDR4/GDDR5 Mode Register 6 and LPDDR Mode Register 17
- ***************************************************************************/
-/* DDR34_PHY_CONTROL_REGS_0 :: MODE_REG6 :: reserved0 [31:21] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_MODE_REG6_reserved0_MASK 0xffe00000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_MODE_REG6_reserved0_SHIFT 21
-
-/* DDR34_PHY_CONTROL_REGS_0 :: MODE_REG6 :: reserved_for_eco1 [20:17] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_MODE_REG6_reserved_for_eco1_MASK 0x001e0000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_MODE_REG6_reserved_for_eco1_SHIFT 17
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_MODE_REG6_reserved_for_eco1_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: MODE_REG6 :: VALID [16:16] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_MODE_REG6_VALID_MASK 0x00010000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_MODE_REG6_VALID_SHIFT 16
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_MODE_REG6_VALID_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: MODE_REG6 :: AD [15:00] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_MODE_REG6_AD_MASK 0x0000ffff
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_MODE_REG6_AD_SHIFT 0
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_MODE_REG6_AD_DEFAULT 0x00000000
-
-/***************************************************************************
- *MODE_REG7 - DDR4/GDDR5 Mode Register 7 and LPDDR Mode Register 41
- ***************************************************************************/
-/* DDR34_PHY_CONTROL_REGS_0 :: MODE_REG7 :: reserved0 [31:21] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_MODE_REG7_reserved0_MASK 0xffe00000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_MODE_REG7_reserved0_SHIFT 21
-
-/* DDR34_PHY_CONTROL_REGS_0 :: MODE_REG7 :: reserved_for_eco1 [20:17] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_MODE_REG7_reserved_for_eco1_MASK 0x001e0000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_MODE_REG7_reserved_for_eco1_SHIFT 17
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_MODE_REG7_reserved_for_eco1_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: MODE_REG7 :: VALID [16:16] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_MODE_REG7_VALID_MASK 0x00010000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_MODE_REG7_VALID_SHIFT 16
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_MODE_REG7_VALID_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: MODE_REG7 :: AD [15:00] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_MODE_REG7_AD_MASK 0x0000ffff
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_MODE_REG7_AD_SHIFT 0
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_MODE_REG7_AD_DEFAULT 0x00000000
-
-/***************************************************************************
- *MODE_REG8 - GDDR5 Mode Register 8 and LPDDR Mode Register 42
- ***************************************************************************/
-/* DDR34_PHY_CONTROL_REGS_0 :: MODE_REG8 :: reserved0 [31:21] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_MODE_REG8_reserved0_MASK 0xffe00000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_MODE_REG8_reserved0_SHIFT 21
-
-/* DDR34_PHY_CONTROL_REGS_0 :: MODE_REG8 :: reserved_for_eco1 [20:17] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_MODE_REG8_reserved_for_eco1_MASK 0x001e0000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_MODE_REG8_reserved_for_eco1_SHIFT 17
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_MODE_REG8_reserved_for_eco1_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: MODE_REG8 :: VALID [16:16] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_MODE_REG8_VALID_MASK 0x00010000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_MODE_REG8_VALID_SHIFT 16
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_MODE_REG8_VALID_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: MODE_REG8 :: AD [15:00] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_MODE_REG8_AD_MASK 0x0000ffff
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_MODE_REG8_AD_SHIFT 0
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_MODE_REG8_AD_DEFAULT 0x00000000
-
-/***************************************************************************
- *MODE_REG15 - GDDR5 Mode Register 15 and LPDDR Mode Register 48
- ***************************************************************************/
-/* DDR34_PHY_CONTROL_REGS_0 :: MODE_REG15 :: reserved0 [31:21] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_MODE_REG15_reserved0_MASK 0xffe00000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_MODE_REG15_reserved0_SHIFT 21
-
-/* DDR34_PHY_CONTROL_REGS_0 :: MODE_REG15 :: reserved_for_eco1 [20:17] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_MODE_REG15_reserved_for_eco1_MASK 0x001e0000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_MODE_REG15_reserved_for_eco1_SHIFT 17
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_MODE_REG15_reserved_for_eco1_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: MODE_REG15 :: VALID [16:16] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_MODE_REG15_VALID_MASK 0x00010000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_MODE_REG15_VALID_SHIFT 16
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_MODE_REG15_VALID_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: MODE_REG15 :: AD [15:00] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_MODE_REG15_AD_MASK 0x0000ffff
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_MODE_REG15_AD_SHIFT 0
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_MODE_REG15_AD_DEFAULT 0x00000000
-
-/***************************************************************************
- *MODE_REG63 - LPDDR Mode Register 63
- ***************************************************************************/
-/* DDR34_PHY_CONTROL_REGS_0 :: MODE_REG63 :: reserved0 [31:21] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_MODE_REG63_reserved0_MASK 0xffe00000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_MODE_REG63_reserved0_SHIFT 21
-
-/* DDR34_PHY_CONTROL_REGS_0 :: MODE_REG63 :: reserved_for_eco1 [20:17] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_MODE_REG63_reserved_for_eco1_MASK 0x001e0000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_MODE_REG63_reserved_for_eco1_SHIFT 17
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_MODE_REG63_reserved_for_eco1_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: MODE_REG63 :: VALID [16:16] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_MODE_REG63_VALID_MASK 0x00010000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_MODE_REG63_VALID_SHIFT 16
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_MODE_REG63_VALID_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: MODE_REG63 :: AD [15:00] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_MODE_REG63_AD_MASK 0x0000ffff
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_MODE_REG63_AD_SHIFT 0
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_MODE_REG63_AD_DEFAULT 0x00000000
-
-/***************************************************************************
- *ALERT_CLEAR - DDR4 Alert status clear register
- ***************************************************************************/
-/* DDR34_PHY_CONTROL_REGS_0 :: ALERT_CLEAR :: reserved0 [31:01] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_ALERT_CLEAR_reserved0_MASK 0xfffffffe
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_ALERT_CLEAR_reserved0_SHIFT 1
-
-/* DDR34_PHY_CONTROL_REGS_0 :: ALERT_CLEAR :: CLEAR [00:00] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_ALERT_CLEAR_CLEAR_MASK 0x00000001
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_ALERT_CLEAR_CLEAR_SHIFT 0
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_ALERT_CLEAR_CLEAR_DEFAULT 0x00000000
-
-/***************************************************************************
- *ALERT_STATUS - DDR4 Alert status register
- ***************************************************************************/
-/* DDR34_PHY_CONTROL_REGS_0 :: ALERT_STATUS :: reserved0 [31:01] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_ALERT_STATUS_reserved0_MASK 0xfffffffe
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_ALERT_STATUS_reserved0_SHIFT 1
-
-/* DDR34_PHY_CONTROL_REGS_0 :: ALERT_STATUS :: STATUS [00:00] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_ALERT_STATUS_STATUS_MASK 0x00000001
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_ALERT_STATUS_STATUS_SHIFT 0
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_ALERT_STATUS_STATUS_DEFAULT 0x00000000
-
-/***************************************************************************
- *CA_PARITY - DDR4 CA parity control register
- ***************************************************************************/
-/* DDR34_PHY_CONTROL_REGS_0 :: CA_PARITY :: reserved0 [31:02] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_CA_PARITY_reserved0_MASK 0xfffffffc
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_CA_PARITY_reserved0_SHIFT 2
-
-/* DDR34_PHY_CONTROL_REGS_0 :: CA_PARITY :: ERROR [01:01] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_CA_PARITY_ERROR_MASK 0x00000002
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_CA_PARITY_ERROR_SHIFT 1
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_CA_PARITY_ERROR_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: CA_PARITY :: ENABLE [00:00] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_CA_PARITY_ENABLE_MASK 0x00000001
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_CA_PARITY_ENABLE_SHIFT 0
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_CA_PARITY_ENABLE_DEFAULT 0x00000000
-
-/***************************************************************************
- *CA_PLAYBACK_CONTROL - GDDR5 CA playback control register
- ***************************************************************************/
-/* DDR34_PHY_CONTROL_REGS_0 :: CA_PLAYBACK_CONTROL :: reserved0 [31:12] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_CA_PLAYBACK_CONTROL_reserved0_MASK 0xfffff000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_CA_PLAYBACK_CONTROL_reserved0_SHIFT 12
-
-/* DDR34_PHY_CONTROL_REGS_0 :: CA_PLAYBACK_CONTROL :: COUNT [11:04] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_CA_PLAYBACK_CONTROL_COUNT_MASK 0x00000ff0
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_CA_PLAYBACK_CONTROL_COUNT_SHIFT 4
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_CA_PLAYBACK_CONTROL_COUNT_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: CA_PLAYBACK_CONTROL :: reserved1 [03:01] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_CA_PLAYBACK_CONTROL_reserved1_MASK 0x0000000e
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_CA_PLAYBACK_CONTROL_reserved1_SHIFT 1
-
-/* DDR34_PHY_CONTROL_REGS_0 :: CA_PLAYBACK_CONTROL :: SAMPLE [00:00] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_CA_PLAYBACK_CONTROL_SAMPLE_MASK 0x00000001
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_CA_PLAYBACK_CONTROL_SAMPLE_SHIFT 0
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_CA_PLAYBACK_CONTROL_SAMPLE_DEFAULT 0x00000000
-
-/***************************************************************************
- *CA_PLAYBACK_STATUS0 - LPDDR3 and GDDR5 CA playback status register0 (for BL0 and BL1)
- ***************************************************************************/
-/* DDR34_PHY_CONTROL_REGS_0 :: CA_PLAYBACK_STATUS0 :: VALID [31:31] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_CA_PLAYBACK_STATUS0_VALID_MASK 0x80000000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_CA_PLAYBACK_STATUS0_VALID_SHIFT 31
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_CA_PLAYBACK_STATUS0_VALID_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: CA_PLAYBACK_STATUS0 :: reserved0 [30:26] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_CA_PLAYBACK_STATUS0_reserved0_MASK 0x7c000000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_CA_PLAYBACK_STATUS0_reserved0_SHIFT 26
-
-/* DDR34_PHY_CONTROL_REGS_0 :: CA_PLAYBACK_STATUS0 :: DATA1 [25:16] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_CA_PLAYBACK_STATUS0_DATA1_MASK 0x03ff0000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_CA_PLAYBACK_STATUS0_DATA1_SHIFT 16
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_CA_PLAYBACK_STATUS0_DATA1_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: CA_PLAYBACK_STATUS0 :: reserved1 [15:10] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_CA_PLAYBACK_STATUS0_reserved1_MASK 0x0000fc00
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_CA_PLAYBACK_STATUS0_reserved1_SHIFT 10
-
-/* DDR34_PHY_CONTROL_REGS_0 :: CA_PLAYBACK_STATUS0 :: DATA0 [09:00] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_CA_PLAYBACK_STATUS0_DATA0_MASK 0x000003ff
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_CA_PLAYBACK_STATUS0_DATA0_SHIFT 0
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_CA_PLAYBACK_STATUS0_DATA0_DEFAULT 0x00000000
-
-/***************************************************************************
- *CA_PLAYBACK_STATUS1 - LPDDR3 and GDDR5 CA playback status register1 (for BL2 and BL3)
- ***************************************************************************/
-/* DDR34_PHY_CONTROL_REGS_0 :: CA_PLAYBACK_STATUS1 :: VALID [31:31] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_CA_PLAYBACK_STATUS1_VALID_MASK 0x80000000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_CA_PLAYBACK_STATUS1_VALID_SHIFT 31
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_CA_PLAYBACK_STATUS1_VALID_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: CA_PLAYBACK_STATUS1 :: reserved0 [30:26] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_CA_PLAYBACK_STATUS1_reserved0_MASK 0x7c000000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_CA_PLAYBACK_STATUS1_reserved0_SHIFT 26
-
-/* DDR34_PHY_CONTROL_REGS_0 :: CA_PLAYBACK_STATUS1 :: DATA1 [25:16] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_CA_PLAYBACK_STATUS1_DATA1_MASK 0x03ff0000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_CA_PLAYBACK_STATUS1_DATA1_SHIFT 16
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_CA_PLAYBACK_STATUS1_DATA1_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: CA_PLAYBACK_STATUS1 :: reserved1 [15:10] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_CA_PLAYBACK_STATUS1_reserved1_MASK 0x0000fc00
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_CA_PLAYBACK_STATUS1_reserved1_SHIFT 10
-
-/* DDR34_PHY_CONTROL_REGS_0 :: CA_PLAYBACK_STATUS1 :: DATA0 [09:00] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_CA_PLAYBACK_STATUS1_DATA0_MASK 0x000003ff
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_CA_PLAYBACK_STATUS1_DATA0_SHIFT 0
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_CA_PLAYBACK_STATUS1_DATA0_DEFAULT 0x00000000
-
-/***************************************************************************
- *WRITE_LEVELING_CONTROL - Write leveling control register
- ***************************************************************************/
-/* DDR34_PHY_CONTROL_REGS_0 :: WRITE_LEVELING_CONTROL :: reserved0 [31:20] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_WRITE_LEVELING_CONTROL_reserved0_MASK 0xfff00000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_WRITE_LEVELING_CONTROL_reserved0_SHIFT 20
-
-/* DDR34_PHY_CONTROL_REGS_0 :: WRITE_LEVELING_CONTROL :: reserved_for_eco1 [19:16] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_WRITE_LEVELING_CONTROL_reserved_for_eco1_MASK 0x000f0000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_WRITE_LEVELING_CONTROL_reserved_for_eco1_SHIFT 16
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_WRITE_LEVELING_CONTROL_reserved_for_eco1_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: WRITE_LEVELING_CONTROL :: COUNT [15:08] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_WRITE_LEVELING_CONTROL_COUNT_MASK 0x0000ff00
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_WRITE_LEVELING_CONTROL_COUNT_SHIFT 8
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_WRITE_LEVELING_CONTROL_COUNT_DEFAULT 0x0000000f
-
-/* DDR34_PHY_CONTROL_REGS_0 :: WRITE_LEVELING_CONTROL :: reserved2 [07:03] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_WRITE_LEVELING_CONTROL_reserved2_MASK 0x000000f8
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_WRITE_LEVELING_CONTROL_reserved2_SHIFT 3
-
-/* DDR34_PHY_CONTROL_REGS_0 :: WRITE_LEVELING_CONTROL :: SAMPLE [02:02] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_WRITE_LEVELING_CONTROL_SAMPLE_MASK 0x00000004
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_WRITE_LEVELING_CONTROL_SAMPLE_SHIFT 2
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_WRITE_LEVELING_CONTROL_SAMPLE_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: WRITE_LEVELING_CONTROL :: CONTINUOUS [01:01] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_WRITE_LEVELING_CONTROL_CONTINUOUS_MASK 0x00000002
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_WRITE_LEVELING_CONTROL_CONTINUOUS_SHIFT 1
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_WRITE_LEVELING_CONTROL_CONTINUOUS_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: WRITE_LEVELING_CONTROL :: ENABLE [00:00] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_WRITE_LEVELING_CONTROL_ENABLE_MASK 0x00000001
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_WRITE_LEVELING_CONTROL_ENABLE_SHIFT 0
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_WRITE_LEVELING_CONTROL_ENABLE_DEFAULT 0x00000000
-
-/***************************************************************************
- *WRITE_LEVELING_STATUS - Write leveling status register
- ***************************************************************************/
-/* DDR34_PHY_CONTROL_REGS_0 :: WRITE_LEVELING_STATUS :: reserved0 [31:14] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_WRITE_LEVELING_STATUS_reserved0_MASK 0xffffc000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_WRITE_LEVELING_STATUS_reserved0_SHIFT 14
-
-/* DDR34_PHY_CONTROL_REGS_0 :: WRITE_LEVELING_STATUS :: EDC [13:09] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_WRITE_LEVELING_STATUS_EDC_MASK 0x00003e00
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_WRITE_LEVELING_STATUS_EDC_SHIFT 9
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_WRITE_LEVELING_STATUS_EDC_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: WRITE_LEVELING_STATUS :: STATUS [08:04] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_WRITE_LEVELING_STATUS_STATUS_MASK 0x000001f0
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_WRITE_LEVELING_STATUS_STATUS_SHIFT 4
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_WRITE_LEVELING_STATUS_STATUS_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: WRITE_LEVELING_STATUS :: reserved1 [03:01] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_WRITE_LEVELING_STATUS_reserved1_MASK 0x0000000e
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_WRITE_LEVELING_STATUS_reserved1_SHIFT 1
-
-/* DDR34_PHY_CONTROL_REGS_0 :: WRITE_LEVELING_STATUS :: VALID [00:00] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_WRITE_LEVELING_STATUS_VALID_MASK 0x00000001
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_WRITE_LEVELING_STATUS_VALID_SHIFT 0
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_WRITE_LEVELING_STATUS_VALID_DEFAULT 0x00000000
-
-/***************************************************************************
- *READ_ENABLE_CONTROL - Read enable test cycle control register
- ***************************************************************************/
-/* DDR34_PHY_CONTROL_REGS_0 :: READ_ENABLE_CONTROL :: reserved0 [31:13] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_READ_ENABLE_CONTROL_reserved0_MASK 0xffffe000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_READ_ENABLE_CONTROL_reserved0_SHIFT 13
-
-/* DDR34_PHY_CONTROL_REGS_0 :: READ_ENABLE_CONTROL :: TEST_CYCLE [12:12] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_READ_ENABLE_CONTROL_TEST_CYCLE_MASK 0x00001000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_READ_ENABLE_CONTROL_TEST_CYCLE_SHIFT 12
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_READ_ENABLE_CONTROL_TEST_CYCLE_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: READ_ENABLE_CONTROL :: SELECT [11:08] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_READ_ENABLE_CONTROL_SELECT_MASK 0x00000f00
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_READ_ENABLE_CONTROL_SELECT_SHIFT 8
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_READ_ENABLE_CONTROL_SELECT_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: READ_ENABLE_CONTROL :: reserved_for_eco1 [07:06] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_READ_ENABLE_CONTROL_reserved_for_eco1_MASK 0x000000c0
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_READ_ENABLE_CONTROL_reserved_for_eco1_SHIFT 6
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_READ_ENABLE_CONTROL_reserved_for_eco1_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: READ_ENABLE_CONTROL :: CS_N [05:04] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_READ_ENABLE_CONTROL_CS_N_MASK 0x00000030
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_READ_ENABLE_CONTROL_CS_N_SHIFT 4
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_READ_ENABLE_CONTROL_CS_N_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: READ_ENABLE_CONTROL :: EDC_DATA [03:03] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_READ_ENABLE_CONTROL_EDC_DATA_MASK 0x00000008
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_READ_ENABLE_CONTROL_EDC_DATA_SHIFT 3
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_READ_ENABLE_CONTROL_EDC_DATA_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: READ_ENABLE_CONTROL :: EDC_PHASE [02:02] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_READ_ENABLE_CONTROL_EDC_PHASE_MASK 0x00000004
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_READ_ENABLE_CONTROL_EDC_PHASE_SHIFT 2
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_READ_ENABLE_CONTROL_EDC_PHASE_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: READ_ENABLE_CONTROL :: DQS [01:01] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_READ_ENABLE_CONTROL_DQS_MASK 0x00000002
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_READ_ENABLE_CONTROL_DQS_SHIFT 1
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_READ_ENABLE_CONTROL_DQS_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: READ_ENABLE_CONTROL :: ENABLE [00:00] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_READ_ENABLE_CONTROL_ENABLE_MASK 0x00000001
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_READ_ENABLE_CONTROL_ENABLE_SHIFT 0
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_READ_ENABLE_CONTROL_ENABLE_DEFAULT 0x00000000
-
-/***************************************************************************
- *READ_ENABLE_STATUS - Read enable test cycle status register
- ***************************************************************************/
-/* DDR34_PHY_CONTROL_REGS_0 :: READ_ENABLE_STATUS :: reserved0 [31:20] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_READ_ENABLE_STATUS_reserved0_MASK 0xfff00000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_READ_ENABLE_STATUS_reserved0_SHIFT 20
-
-/* DDR34_PHY_CONTROL_REGS_0 :: READ_ENABLE_STATUS :: DATA [19:12] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_READ_ENABLE_STATUS_DATA_MASK 0x000ff000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_READ_ENABLE_STATUS_DATA_SHIFT 12
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_READ_ENABLE_STATUS_DATA_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: READ_ENABLE_STATUS :: reserved1 [11:09] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_READ_ENABLE_STATUS_reserved1_MASK 0x00000e00
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_READ_ENABLE_STATUS_reserved1_SHIFT 9
-
-/* DDR34_PHY_CONTROL_REGS_0 :: READ_ENABLE_STATUS :: BL4_STATUS [08:08] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_READ_ENABLE_STATUS_BL4_STATUS_MASK 0x00000100
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_READ_ENABLE_STATUS_BL4_STATUS_SHIFT 8
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_READ_ENABLE_STATUS_BL4_STATUS_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: READ_ENABLE_STATUS :: BL3_STATUS [07:07] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_READ_ENABLE_STATUS_BL3_STATUS_MASK 0x00000080
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_READ_ENABLE_STATUS_BL3_STATUS_SHIFT 7
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_READ_ENABLE_STATUS_BL3_STATUS_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: READ_ENABLE_STATUS :: BL2_STATUS [06:06] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_READ_ENABLE_STATUS_BL2_STATUS_MASK 0x00000040
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_READ_ENABLE_STATUS_BL2_STATUS_SHIFT 6
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_READ_ENABLE_STATUS_BL2_STATUS_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: READ_ENABLE_STATUS :: BL1_STATUS [05:05] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_READ_ENABLE_STATUS_BL1_STATUS_MASK 0x00000020
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_READ_ENABLE_STATUS_BL1_STATUS_SHIFT 5
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_READ_ENABLE_STATUS_BL1_STATUS_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: READ_ENABLE_STATUS :: BL0_STATUS [04:04] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_READ_ENABLE_STATUS_BL0_STATUS_MASK 0x00000010
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_READ_ENABLE_STATUS_BL0_STATUS_SHIFT 4
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_READ_ENABLE_STATUS_BL0_STATUS_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: READ_ENABLE_STATUS :: reserved2 [03:01] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_READ_ENABLE_STATUS_reserved2_MASK 0x0000000e
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_READ_ENABLE_STATUS_reserved2_SHIFT 1
-
-/* DDR34_PHY_CONTROL_REGS_0 :: READ_ENABLE_STATUS :: VALID [00:00] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_READ_ENABLE_STATUS_VALID_MASK 0x00000001
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_READ_ENABLE_STATUS_VALID_SHIFT 0
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_READ_ENABLE_STATUS_VALID_DEFAULT 0x00000000
-
-/***************************************************************************
- *TRAFFIC_GEN_LFSR_SEED - Traffic generator seed register
- ***************************************************************************/
-/* DDR34_PHY_CONTROL_REGS_0 :: TRAFFIC_GEN_LFSR_SEED :: SEED [31:00] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_TRAFFIC_GEN_LFSR_SEED_SEED_MASK 0xffffffff
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_TRAFFIC_GEN_LFSR_SEED_SEED_SHIFT 0
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_TRAFFIC_GEN_LFSR_SEED_SEED_DEFAULT 0xba5eba11
-
-/***************************************************************************
- *TRAFFIC_GEN_ADDRESS1 - Traffic generator address register #1
- ***************************************************************************/
-/* DDR34_PHY_CONTROL_REGS_0 :: TRAFFIC_GEN_ADDRESS1 :: reserved0 [31:20] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_TRAFFIC_GEN_ADDRESS1_reserved0_MASK 0xfff00000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_TRAFFIC_GEN_ADDRESS1_reserved0_SHIFT 20
-
-/* DDR34_PHY_CONTROL_REGS_0 :: TRAFFIC_GEN_ADDRESS1 :: BANK [19:16] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_TRAFFIC_GEN_ADDRESS1_BANK_MASK 0x000f0000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_TRAFFIC_GEN_ADDRESS1_BANK_SHIFT 16
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_TRAFFIC_GEN_ADDRESS1_BANK_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: TRAFFIC_GEN_ADDRESS1 :: ROW [15:00] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_TRAFFIC_GEN_ADDRESS1_ROW_MASK 0x0000ffff
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_TRAFFIC_GEN_ADDRESS1_ROW_SHIFT 0
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_TRAFFIC_GEN_ADDRESS1_ROW_DEFAULT 0x00000000
-
-/***************************************************************************
- *TRAFFIC_GEN_ADDRESS2 - Traffic generator address register #2
- ***************************************************************************/
-/* DDR34_PHY_CONTROL_REGS_0 :: TRAFFIC_GEN_ADDRESS2 :: reserved0 [31:20] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_TRAFFIC_GEN_ADDRESS2_reserved0_MASK 0xfff00000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_TRAFFIC_GEN_ADDRESS2_reserved0_SHIFT 20
-
-/* DDR34_PHY_CONTROL_REGS_0 :: TRAFFIC_GEN_ADDRESS2 :: BANK [19:16] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_TRAFFIC_GEN_ADDRESS2_BANK_MASK 0x000f0000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_TRAFFIC_GEN_ADDRESS2_BANK_SHIFT 16
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_TRAFFIC_GEN_ADDRESS2_BANK_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: TRAFFIC_GEN_ADDRESS2 :: ROW [15:00] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_TRAFFIC_GEN_ADDRESS2_ROW_MASK 0x0000ffff
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_TRAFFIC_GEN_ADDRESS2_ROW_SHIFT 0
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_TRAFFIC_GEN_ADDRESS2_ROW_DEFAULT 0x00000000
-
-/***************************************************************************
- *TRAFFIC_GEN_CONTROL - Traffic generator control register
- ***************************************************************************/
-/* DDR34_PHY_CONTROL_REGS_0 :: TRAFFIC_GEN_CONTROL :: reserved0 [31:17] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_TRAFFIC_GEN_CONTROL_reserved0_MASK 0xfffe0000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_TRAFFIC_GEN_CONTROL_reserved0_SHIFT 17
-
-/* DDR34_PHY_CONTROL_REGS_0 :: TRAFFIC_GEN_CONTROL :: reserved_for_eco1 [16:13] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_TRAFFIC_GEN_CONTROL_reserved_for_eco1_MASK 0x0001e000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_TRAFFIC_GEN_CONTROL_reserved_for_eco1_SHIFT 13
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_TRAFFIC_GEN_CONTROL_reserved_for_eco1_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: TRAFFIC_GEN_CONTROL :: DIAG_WRO [12:12] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_TRAFFIC_GEN_CONTROL_DIAG_WRO_MASK 0x00001000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_TRAFFIC_GEN_CONTROL_DIAG_WRO_SHIFT 12
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_TRAFFIC_GEN_CONTROL_DIAG_WRO_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: TRAFFIC_GEN_CONTROL :: DIAG_WRO_RD [11:11] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_TRAFFIC_GEN_CONTROL_DIAG_WRO_RD_MASK 0x00000800
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_TRAFFIC_GEN_CONTROL_DIAG_WRO_RD_SHIFT 11
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_TRAFFIC_GEN_CONTROL_DIAG_WRO_RD_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: TRAFFIC_GEN_CONTROL :: DIAG_WR_RD [10:10] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_TRAFFIC_GEN_CONTROL_DIAG_WR_RD_MASK 0x00000400
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_TRAFFIC_GEN_CONTROL_DIAG_WR_RD_SHIFT 10
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_TRAFFIC_GEN_CONTROL_DIAG_WR_RD_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: TRAFFIC_GEN_CONTROL :: WR_NOISE [09:09] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_TRAFFIC_GEN_CONTROL_WR_NOISE_MASK 0x00000200
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_TRAFFIC_GEN_CONTROL_WR_NOISE_SHIFT 9
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_TRAFFIC_GEN_CONTROL_WR_NOISE_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: TRAFFIC_GEN_CONTROL :: RD_NOISE [08:08] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_TRAFFIC_GEN_CONTROL_RD_NOISE_MASK 0x00000100
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_TRAFFIC_GEN_CONTROL_RD_NOISE_SHIFT 8
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_TRAFFIC_GEN_CONTROL_RD_NOISE_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: TRAFFIC_GEN_CONTROL :: CLEAR_DRAM [07:07] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_TRAFFIC_GEN_CONTROL_CLEAR_DRAM_MASK 0x00000080
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_TRAFFIC_GEN_CONTROL_CLEAR_DRAM_SHIFT 7
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_TRAFFIC_GEN_CONTROL_CLEAR_DRAM_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: TRAFFIC_GEN_CONTROL :: MASK_DM [06:06] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_TRAFFIC_GEN_CONTROL_MASK_DM_MASK 0x00000040
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_TRAFFIC_GEN_CONTROL_MASK_DM_SHIFT 6
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_TRAFFIC_GEN_CONTROL_MASK_DM_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: TRAFFIC_GEN_CONTROL :: INIT_LFSR [05:05] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_TRAFFIC_GEN_CONTROL_INIT_LFSR_MASK 0x00000020
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_TRAFFIC_GEN_CONTROL_INIT_LFSR_SHIFT 5
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_TRAFFIC_GEN_CONTROL_INIT_LFSR_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: TRAFFIC_GEN_CONTROL :: FIFO [04:04] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_TRAFFIC_GEN_CONTROL_FIFO_MASK 0x00000010
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_TRAFFIC_GEN_CONTROL_FIFO_SHIFT 4
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_TRAFFIC_GEN_CONTROL_FIFO_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: TRAFFIC_GEN_CONTROL :: MPR [03:03] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_TRAFFIC_GEN_CONTROL_MPR_MASK 0x00000008
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_TRAFFIC_GEN_CONTROL_MPR_SHIFT 3
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_TRAFFIC_GEN_CONTROL_MPR_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: TRAFFIC_GEN_CONTROL :: RD_WR [02:02] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_TRAFFIC_GEN_CONTROL_RD_WR_MASK 0x00000004
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_TRAFFIC_GEN_CONTROL_RD_WR_SHIFT 2
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_TRAFFIC_GEN_CONTROL_RD_WR_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: TRAFFIC_GEN_CONTROL :: RD_EN [01:01] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_TRAFFIC_GEN_CONTROL_RD_EN_MASK 0x00000002
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_TRAFFIC_GEN_CONTROL_RD_EN_SHIFT 1
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_TRAFFIC_GEN_CONTROL_RD_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: TRAFFIC_GEN_CONTROL :: ENABLE [00:00] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_TRAFFIC_GEN_CONTROL_ENABLE_MASK 0x00000001
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_TRAFFIC_GEN_CONTROL_ENABLE_SHIFT 0
-
-/***************************************************************************
- *TRAFFIC_GEN_DATA_CONTROL - Traffic generator data control register
- ***************************************************************************/
-/* DDR34_PHY_CONTROL_REGS_0 :: TRAFFIC_GEN_DATA_CONTROL :: reserved0 [31:22] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_TRAFFIC_GEN_DATA_CONTROL_reserved0_MASK 0xffc00000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_TRAFFIC_GEN_DATA_CONTROL_reserved0_SHIFT 22
-
-/* DDR34_PHY_CONTROL_REGS_0 :: TRAFFIC_GEN_DATA_CONTROL :: PATTERN [21:20] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_TRAFFIC_GEN_DATA_CONTROL_PATTERN_MASK 0x00300000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_TRAFFIC_GEN_DATA_CONTROL_PATTERN_SHIFT 20
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_TRAFFIC_GEN_DATA_CONTROL_PATTERN_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: TRAFFIC_GEN_DATA_CONTROL :: LENGTH [19:00] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_TRAFFIC_GEN_DATA_CONTROL_LENGTH_MASK 0x000fffff
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_TRAFFIC_GEN_DATA_CONTROL_LENGTH_SHIFT 0
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_TRAFFIC_GEN_DATA_CONTROL_LENGTH_DEFAULT 0x00000000
-
-/***************************************************************************
- *TRAFFIC_GEN_DQ_MASK - Traffic generator DQ mask register
- ***************************************************************************/
-/* DDR34_PHY_CONTROL_REGS_0 :: TRAFFIC_GEN_DQ_MASK :: MASK [31:00] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_TRAFFIC_GEN_DQ_MASK_MASK_MASK 0xffffffff
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_TRAFFIC_GEN_DQ_MASK_MASK_SHIFT 0
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_TRAFFIC_GEN_DQ_MASK_MASK_DEFAULT 0x00000000
-
-/***************************************************************************
- *TRAFFIC_GEN_ECC_DQ_MASK - Traffic generator ECC DQ mask register
- ***************************************************************************/
-/* DDR34_PHY_CONTROL_REGS_0 :: TRAFFIC_GEN_ECC_DQ_MASK :: reserved0 [31:04] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_TRAFFIC_GEN_ECC_DQ_MASK_reserved0_MASK 0xfffffff0
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_TRAFFIC_GEN_ECC_DQ_MASK_reserved0_SHIFT 4
-
-/* DDR34_PHY_CONTROL_REGS_0 :: TRAFFIC_GEN_ECC_DQ_MASK :: MASK [03:00] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_TRAFFIC_GEN_ECC_DQ_MASK_MASK_MASK 0x0000000f
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_TRAFFIC_GEN_ECC_DQ_MASK_MASK_SHIFT 0
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_TRAFFIC_GEN_ECC_DQ_MASK_MASK_DEFAULT 0x00000000
-
-/***************************************************************************
- *TRAFFIC_GEN_STATUS - Traffic generator status register
- ***************************************************************************/
-/* DDR34_PHY_CONTROL_REGS_0 :: TRAFFIC_GEN_STATUS :: reserved0 [31:01] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_TRAFFIC_GEN_STATUS_reserved0_MASK 0xfffffffe
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_TRAFFIC_GEN_STATUS_reserved0_SHIFT 1
-
-/* DDR34_PHY_CONTROL_REGS_0 :: TRAFFIC_GEN_STATUS :: BUSY [00:00] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_TRAFFIC_GEN_STATUS_BUSY_MASK 0x00000001
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_TRAFFIC_GEN_STATUS_BUSY_SHIFT 0
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_TRAFFIC_GEN_STATUS_BUSY_DEFAULT 0x00000000
-
-/***************************************************************************
- *TRAFFIC_GEN_DQ_STATUS - Traffic generator DQ status register
- ***************************************************************************/
-/* DDR34_PHY_CONTROL_REGS_0 :: TRAFFIC_GEN_DQ_STATUS :: STATUS [31:00] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_TRAFFIC_GEN_DQ_STATUS_STATUS_MASK 0xffffffff
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_TRAFFIC_GEN_DQ_STATUS_STATUS_SHIFT 0
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_TRAFFIC_GEN_DQ_STATUS_STATUS_DEFAULT 0x00000000
-
-/***************************************************************************
- *TRAFFIC_GEN_ECC_STATUS - Traffic generator ECC DQ status register
- ***************************************************************************/
-/* DDR34_PHY_CONTROL_REGS_0 :: TRAFFIC_GEN_ECC_STATUS :: reserved0 [31:04] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_TRAFFIC_GEN_ECC_STATUS_reserved0_MASK 0xfffffff0
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_TRAFFIC_GEN_ECC_STATUS_reserved0_SHIFT 4
-
-/* DDR34_PHY_CONTROL_REGS_0 :: TRAFFIC_GEN_ECC_STATUS :: STATUS [03:00] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_TRAFFIC_GEN_ECC_STATUS_STATUS_MASK 0x0000000f
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_TRAFFIC_GEN_ECC_STATUS_STATUS_SHIFT 0
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_TRAFFIC_GEN_ECC_STATUS_STATUS_DEFAULT 0x00000000
-
-/***************************************************************************
- *TRAFFIC_GEN_ERR_CNT_CONTROL - Traffic generator error count control register
- ***************************************************************************/
-/* DDR34_PHY_CONTROL_REGS_0 :: TRAFFIC_GEN_ERR_CNT_CONTROL :: reserved0 [31:09] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_TRAFFIC_GEN_ERR_CNT_CONTROL_reserved0_MASK 0xfffffe00
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_TRAFFIC_GEN_ERR_CNT_CONTROL_reserved0_SHIFT 9
-
-/* DDR34_PHY_CONTROL_REGS_0 :: TRAFFIC_GEN_ERR_CNT_CONTROL :: DQ_SEL [08:04] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_TRAFFIC_GEN_ERR_CNT_CONTROL_DQ_SEL_MASK 0x000001f0
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_TRAFFIC_GEN_ERR_CNT_CONTROL_DQ_SEL_SHIFT 4
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_TRAFFIC_GEN_ERR_CNT_CONTROL_DQ_SEL_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: TRAFFIC_GEN_ERR_CNT_CONTROL :: reserved1 [03:02] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_TRAFFIC_GEN_ERR_CNT_CONTROL_reserved1_MASK 0x0000000c
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_TRAFFIC_GEN_ERR_CNT_CONTROL_reserved1_SHIFT 2
-
-/* DDR34_PHY_CONTROL_REGS_0 :: TRAFFIC_GEN_ERR_CNT_CONTROL :: CLEAR [01:01] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_TRAFFIC_GEN_ERR_CNT_CONTROL_CLEAR_MASK 0x00000002
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_TRAFFIC_GEN_ERR_CNT_CONTROL_CLEAR_SHIFT 1
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_TRAFFIC_GEN_ERR_CNT_CONTROL_CLEAR_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: TRAFFIC_GEN_ERR_CNT_CONTROL :: ENABLE [00:00] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_TRAFFIC_GEN_ERR_CNT_CONTROL_ENABLE_MASK 0x00000001
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_TRAFFIC_GEN_ERR_CNT_CONTROL_ENABLE_SHIFT 0
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_TRAFFIC_GEN_ERR_CNT_CONTROL_ENABLE_DEFAULT 0x00000000
-
-/***************************************************************************
- *TRAFFIC_GEN_ERR_CNT_STATUS - Traffic generator error count status register
- ***************************************************************************/
-/* DDR34_PHY_CONTROL_REGS_0 :: TRAFFIC_GEN_ERR_CNT_STATUS :: reserved0 [31:16] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_TRAFFIC_GEN_ERR_CNT_STATUS_reserved0_MASK 0xffff0000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_TRAFFIC_GEN_ERR_CNT_STATUS_reserved0_SHIFT 16
-
-/* DDR34_PHY_CONTROL_REGS_0 :: TRAFFIC_GEN_ERR_CNT_STATUS :: COUNT [15:00] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_TRAFFIC_GEN_ERR_CNT_STATUS_COUNT_MASK 0x0000ffff
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_TRAFFIC_GEN_ERR_CNT_STATUS_COUNT_SHIFT 0
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_TRAFFIC_GEN_ERR_CNT_STATUS_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *VIRTUAL_VTT_CONTROL - Virtual VTT Control and Status register
- ***************************************************************************/
-/* DDR34_PHY_CONTROL_REGS_0 :: VIRTUAL_VTT_CONTROL :: reserved0 [31:12] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONTROL_reserved0_MASK 0xfffff000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONTROL_reserved0_SHIFT 12
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VIRTUAL_VTT_CONTROL :: reserved_for_eco1 [11:08] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONTROL_reserved_for_eco1_MASK 0x00000f00
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONTROL_reserved_for_eco1_SHIFT 8
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONTROL_reserved_for_eco1_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VIRTUAL_VTT_CONTROL :: MAX_NOISE [07:07] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONTROL_MAX_NOISE_MASK 0x00000080
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONTROL_MAX_NOISE_SHIFT 7
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONTROL_MAX_NOISE_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VIRTUAL_VTT_CONTROL :: LOW_NOISE [06:06] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONTROL_LOW_NOISE_MASK 0x00000040
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONTROL_LOW_NOISE_SHIFT 6
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONTROL_LOW_NOISE_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VIRTUAL_VTT_CONTROL :: LOW_VTT [05:05] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONTROL_LOW_VTT_MASK 0x00000020
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONTROL_LOW_VTT_SHIFT 5
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONTROL_LOW_VTT_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VIRTUAL_VTT_CONTROL :: HIGH_VTT [04:04] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONTROL_HIGH_VTT_MASK 0x00000010
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONTROL_HIGH_VTT_SHIFT 4
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONTROL_HIGH_VTT_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VIRTUAL_VTT_CONTROL :: ERROR_RESET [03:03] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONTROL_ERROR_RESET_MASK 0x00000008
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONTROL_ERROR_RESET_SHIFT 3
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONTROL_ERROR_RESET_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VIRTUAL_VTT_CONTROL :: ENABLE_CTL_IDLE [02:02] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONTROL_ENABLE_CTL_IDLE_MASK 0x00000004
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONTROL_ENABLE_CTL_IDLE_SHIFT 2
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONTROL_ENABLE_CTL_IDLE_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VIRTUAL_VTT_CONTROL :: ENABLE_CS_IDLE [01:01] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONTROL_ENABLE_CS_IDLE_MASK 0x00000002
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONTROL_ENABLE_CS_IDLE_SHIFT 1
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONTROL_ENABLE_CS_IDLE_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VIRTUAL_VTT_CONTROL :: ENABLE_CKE_IDLE [00:00] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONTROL_ENABLE_CKE_IDLE_MASK 0x00000001
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONTROL_ENABLE_CKE_IDLE_SHIFT 0
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONTROL_ENABLE_CKE_IDLE_DEFAULT 0x00000000
-
-/***************************************************************************
- *VIRTUAL_VTT_STATUS - Virtual VTT Control and Status register
- ***************************************************************************/
-/* DDR34_PHY_CONTROL_REGS_0 :: VIRTUAL_VTT_STATUS :: reserved0 [31:19] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VIRTUAL_VTT_STATUS_reserved0_MASK 0xfff80000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VIRTUAL_VTT_STATUS_reserved0_SHIFT 19
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VIRTUAL_VTT_STATUS :: ERROR [18:03] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VIRTUAL_VTT_STATUS_ERROR_MASK 0x0007fff8
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VIRTUAL_VTT_STATUS_ERROR_SHIFT 3
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VIRTUAL_VTT_STATUS_ERROR_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VIRTUAL_VTT_STATUS :: ERROR_LOW [02:02] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VIRTUAL_VTT_STATUS_ERROR_LOW_MASK 0x00000004
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VIRTUAL_VTT_STATUS_ERROR_LOW_SHIFT 2
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VIRTUAL_VTT_STATUS_ERROR_LOW_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VIRTUAL_VTT_STATUS :: ERROR_HIGH [01:01] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VIRTUAL_VTT_STATUS_ERROR_HIGH_MASK 0x00000002
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VIRTUAL_VTT_STATUS_ERROR_HIGH_SHIFT 1
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VIRTUAL_VTT_STATUS_ERROR_HIGH_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VIRTUAL_VTT_STATUS :: READY [00:00] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VIRTUAL_VTT_STATUS_READY_MASK 0x00000001
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VIRTUAL_VTT_STATUS_READY_SHIFT 0
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VIRTUAL_VTT_STATUS_READY_DEFAULT 0x00000000
-
-/***************************************************************************
- *VIRTUAL_VTT_CONNECTIONS - Virtual VTT Connections register
- ***************************************************************************/
-/* DDR34_PHY_CONTROL_REGS_0 :: VIRTUAL_VTT_CONNECTIONS :: reserved0 [31:31] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONNECTIONS_reserved0_MASK 0x80000000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONNECTIONS_reserved0_SHIFT 31
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VIRTUAL_VTT_CONNECTIONS :: MASK [30:00] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONNECTIONS_MASK_MASK 0x7fffffff
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONNECTIONS_MASK_SHIFT 0
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONNECTIONS_MASK_DEFAULT 0x1fffffff
-
-/***************************************************************************
- *VIRTUAL_VTT_OVERRIDE - Virtual VTT Override register
- ***************************************************************************/
-/* DDR34_PHY_CONTROL_REGS_0 :: VIRTUAL_VTT_OVERRIDE :: reserved0 [31:31] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VIRTUAL_VTT_OVERRIDE_reserved0_MASK 0x80000000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VIRTUAL_VTT_OVERRIDE_reserved0_SHIFT 31
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VIRTUAL_VTT_OVERRIDE :: MASK [30:00] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VIRTUAL_VTT_OVERRIDE_MASK_MASK 0x7fffffff
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VIRTUAL_VTT_OVERRIDE_MASK_SHIFT 0
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VIRTUAL_VTT_OVERRIDE_MASK_DEFAULT 0x0000ffff
-
-/***************************************************************************
- *VREF_DAC_CONTROL - VREF DAC Control register
- ***************************************************************************/
-/* DDR34_PHY_CONTROL_REGS_0 :: VREF_DAC_CONTROL :: reserved0 [31:20] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_reserved0_MASK 0xfff00000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_reserved0_SHIFT 20
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VREF_DAC_CONTROL :: AUX_GT_INT [19:19] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_AUX_GT_INT_MASK 0x00080000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_AUX_GT_INT_SHIFT 19
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_AUX_GT_INT_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VREF_DAC_CONTROL :: TESTOUT_MUX_CTL [18:17] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_TESTOUT_MUX_CTL_MASK 0x00060000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_TESTOUT_MUX_CTL_SHIFT 17
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_TESTOUT_MUX_CTL_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VREF_DAC_CONTROL :: TEST [16:16] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_TEST_MASK 0x00010000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_TEST_SHIFT 16
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_TEST_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VREF_DAC_CONTROL :: PDN3 [15:15] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_PDN3_MASK 0x00008000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_PDN3_SHIFT 15
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_PDN3_DEFAULT 0x00000001
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VREF_DAC_CONTROL :: PDN2 [14:14] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_PDN2_MASK 0x00004000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_PDN2_SHIFT 14
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_PDN2_DEFAULT 0x00000001
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VREF_DAC_CONTROL :: PDN1 [13:13] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_PDN1_MASK 0x00002000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_PDN1_SHIFT 13
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_PDN1_DEFAULT 0x00000001
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VREF_DAC_CONTROL :: PDN0 [12:12] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_PDN0_MASK 0x00001000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_PDN0_SHIFT 12
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_PDN0_DEFAULT 0x00000001
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VREF_DAC_CONTROL :: DAC1 [11:06] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_DAC1_MASK 0x00000fc0
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_DAC1_SHIFT 6
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_DAC1_DEFAULT 0x00000020
-
-/* DDR34_PHY_CONTROL_REGS_0 :: VREF_DAC_CONTROL :: DAC0 [05:00] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_DAC0_MASK 0x0000003f
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_DAC0_SHIFT 0
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_DAC0_DEFAULT 0x00000020
-
-/***************************************************************************
- *PHYBIST_CNTRL - PhyBist Control Register
- ***************************************************************************/
-/* DDR34_PHY_CONTROL_REGS_0 :: PHYBIST_CNTRL :: reserved0 [31:30] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PHYBIST_CNTRL_reserved0_MASK 0xc0000000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PHYBIST_CNTRL_reserved0_SHIFT 30
-
-/* DDR34_PHY_CONTROL_REGS_0 :: PHYBIST_CNTRL :: CLK_PAD_ENB [29:28] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PHYBIST_CNTRL_CLK_PAD_ENB_MASK 0x30000000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PHYBIST_CNTRL_CLK_PAD_ENB_SHIFT 28
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PHYBIST_CNTRL_CLK_PAD_ENB_DEFAULT 0x00000002
-
-/* DDR34_PHY_CONTROL_REGS_0 :: PHYBIST_CNTRL :: reserved1 [27:27] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PHYBIST_CNTRL_reserved1_MASK 0x08000000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PHYBIST_CNTRL_reserved1_SHIFT 27
-
-/* DDR34_PHY_CONTROL_REGS_0 :: PHYBIST_CNTRL :: FORCE_DQ_ERROR_SEL [26:24] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PHYBIST_CNTRL_FORCE_DQ_ERROR_SEL_MASK 0x07000000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PHYBIST_CNTRL_FORCE_DQ_ERROR_SEL_SHIFT 24
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PHYBIST_CNTRL_FORCE_DQ_ERROR_SEL_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: PHYBIST_CNTRL :: reserved_for_eco2 [23:23] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PHYBIST_CNTRL_reserved_for_eco2_MASK 0x00800000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PHYBIST_CNTRL_reserved_for_eco2_SHIFT 23
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PHYBIST_CNTRL_reserved_for_eco2_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: PHYBIST_CNTRL :: FORCE_BL_ERROR_SEL [22:20] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PHYBIST_CNTRL_FORCE_BL_ERROR_SEL_MASK 0x00700000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PHYBIST_CNTRL_FORCE_BL_ERROR_SEL_SHIFT 20
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PHYBIST_CNTRL_FORCE_BL_ERROR_SEL_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: PHYBIST_CNTRL :: reserved_for_eco3 [19:17] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PHYBIST_CNTRL_reserved_for_eco3_MASK 0x000e0000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PHYBIST_CNTRL_reserved_for_eco3_SHIFT 17
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PHYBIST_CNTRL_reserved_for_eco3_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: PHYBIST_CNTRL :: FORCE_CTL_ERROR_SEL [16:12] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PHYBIST_CNTRL_FORCE_CTL_ERROR_SEL_MASK 0x0001f000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PHYBIST_CNTRL_FORCE_CTL_ERROR_SEL_SHIFT 12
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PHYBIST_CNTRL_FORCE_CTL_ERROR_SEL_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: PHYBIST_CNTRL :: reserved4 [11:10] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PHYBIST_CNTRL_reserved4_MASK 0x00000c00
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PHYBIST_CNTRL_reserved4_SHIFT 10
-
-/* DDR34_PHY_CONTROL_REGS_0 :: PHYBIST_CNTRL :: FORCE_DAT_ERROR [09:09] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PHYBIST_CNTRL_FORCE_DAT_ERROR_MASK 0x00000200
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PHYBIST_CNTRL_FORCE_DAT_ERROR_SHIFT 9
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PHYBIST_CNTRL_FORCE_DAT_ERROR_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: PHYBIST_CNTRL :: FORCE_CTL_ERROR [08:08] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PHYBIST_CNTRL_FORCE_CTL_ERROR_MASK 0x00000100
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PHYBIST_CNTRL_FORCE_CTL_ERROR_SHIFT 8
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PHYBIST_CNTRL_FORCE_CTL_ERROR_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: PHYBIST_CNTRL :: SSO [07:06] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PHYBIST_CNTRL_SSO_MASK 0x000000c0
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PHYBIST_CNTRL_SSO_SHIFT 6
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PHYBIST_CNTRL_SSO_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: PHYBIST_CNTRL :: LENGTH [05:04] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PHYBIST_CNTRL_LENGTH_MASK 0x00000030
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PHYBIST_CNTRL_LENGTH_SHIFT 4
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PHYBIST_CNTRL_LENGTH_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: PHYBIST_CNTRL :: MODE [03:01] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PHYBIST_CNTRL_MODE_MASK 0x0000000e
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PHYBIST_CNTRL_MODE_SHIFT 1
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PHYBIST_CNTRL_MODE_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: PHYBIST_CNTRL :: ENABLE [00:00] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PHYBIST_CNTRL_ENABLE_MASK 0x00000001
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PHYBIST_CNTRL_ENABLE_SHIFT 0
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PHYBIST_CNTRL_ENABLE_DEFAULT 0x00000000
-
-/***************************************************************************
- *PHYBIST_SEED - PhyBist Seed Register
- ***************************************************************************/
-/* DDR34_PHY_CONTROL_REGS_0 :: PHYBIST_SEED :: SEED [31:00] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PHYBIST_SEED_SEED_MASK 0xffffffff
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PHYBIST_SEED_SEED_SHIFT 0
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PHYBIST_SEED_SEED_DEFAULT 0xba5eba11
-
-/***************************************************************************
- *PHYBIST_STATUS - PhyBist General Status Register
- ***************************************************************************/
-/* DDR34_PHY_CONTROL_REGS_0 :: PHYBIST_STATUS :: reserved0 [31:04] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PHYBIST_STATUS_reserved0_MASK 0xfffffff0
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PHYBIST_STATUS_reserved0_SHIFT 4
-
-/* DDR34_PHY_CONTROL_REGS_0 :: PHYBIST_STATUS :: DAT_PASS [03:03] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PHYBIST_STATUS_DAT_PASS_MASK 0x00000008
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PHYBIST_STATUS_DAT_PASS_SHIFT 3
-
-/* DDR34_PHY_CONTROL_REGS_0 :: PHYBIST_STATUS :: CTL_PASS [02:02] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PHYBIST_STATUS_CTL_PASS_MASK 0x00000004
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PHYBIST_STATUS_CTL_PASS_SHIFT 2
-
-/* DDR34_PHY_CONTROL_REGS_0 :: PHYBIST_STATUS :: DAT_DONE [01:01] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PHYBIST_STATUS_DAT_DONE_MASK 0x00000002
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PHYBIST_STATUS_DAT_DONE_SHIFT 1
-
-/* DDR34_PHY_CONTROL_REGS_0 :: PHYBIST_STATUS :: CTL_DONE [00:00] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PHYBIST_STATUS_CTL_DONE_MASK 0x00000001
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PHYBIST_STATUS_CTL_DONE_SHIFT 0
-
-/***************************************************************************
- *PHYBIST_CTL_STATUS - PhyBist Per-Bit Control Pad Status Register
- ***************************************************************************/
-/* DDR34_PHY_CONTROL_REGS_0 :: PHYBIST_CTL_STATUS :: reserved0 [31:31] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PHYBIST_CTL_STATUS_reserved0_MASK 0x80000000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PHYBIST_CTL_STATUS_reserved0_SHIFT 31
-
-/* DDR34_PHY_CONTROL_REGS_0 :: PHYBIST_CTL_STATUS :: CTL_ERRORS [30:00] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PHYBIST_CTL_STATUS_CTL_ERRORS_MASK 0x7fffffff
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PHYBIST_CTL_STATUS_CTL_ERRORS_SHIFT 0
-
-/***************************************************************************
- *PHYBIST_BL0_STATUS - PhyBist Byte Lane #0 Status Register
- ***************************************************************************/
-/* DDR34_PHY_CONTROL_REGS_0 :: PHYBIST_BL0_STATUS :: reserved0 [31:10] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PHYBIST_BL0_STATUS_reserved0_MASK 0xfffffc00
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PHYBIST_BL0_STATUS_reserved0_SHIFT 10
-
-/* DDR34_PHY_CONTROL_REGS_0 :: PHYBIST_BL0_STATUS :: EDC [09:09] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PHYBIST_BL0_STATUS_EDC_MASK 0x00000200
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PHYBIST_BL0_STATUS_EDC_SHIFT 9
-
-/* DDR34_PHY_CONTROL_REGS_0 :: PHYBIST_BL0_STATUS :: DM [08:08] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PHYBIST_BL0_STATUS_DM_MASK 0x00000100
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PHYBIST_BL0_STATUS_DM_SHIFT 8
-
-/* DDR34_PHY_CONTROL_REGS_0 :: PHYBIST_BL0_STATUS :: DQ [07:00] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PHYBIST_BL0_STATUS_DQ_MASK 0x000000ff
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PHYBIST_BL0_STATUS_DQ_SHIFT 0
-
-/***************************************************************************
- *PHYBIST_BL1_STATUS - PhyBist Byte Lane #1 Status Register
- ***************************************************************************/
-/* DDR34_PHY_CONTROL_REGS_0 :: PHYBIST_BL1_STATUS :: reserved0 [31:10] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PHYBIST_BL1_STATUS_reserved0_MASK 0xfffffc00
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PHYBIST_BL1_STATUS_reserved0_SHIFT 10
-
-/* DDR34_PHY_CONTROL_REGS_0 :: PHYBIST_BL1_STATUS :: EDC [09:09] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PHYBIST_BL1_STATUS_EDC_MASK 0x00000200
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PHYBIST_BL1_STATUS_EDC_SHIFT 9
-
-/* DDR34_PHY_CONTROL_REGS_0 :: PHYBIST_BL1_STATUS :: DM [08:08] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PHYBIST_BL1_STATUS_DM_MASK 0x00000100
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PHYBIST_BL1_STATUS_DM_SHIFT 8
-
-/* DDR34_PHY_CONTROL_REGS_0 :: PHYBIST_BL1_STATUS :: DQ [07:00] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PHYBIST_BL1_STATUS_DQ_MASK 0x000000ff
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PHYBIST_BL1_STATUS_DQ_SHIFT 0
-
-/***************************************************************************
- *PHYBIST_BL2_STATUS - PhyBist Byte Lane #2 Status Register
- ***************************************************************************/
-/* DDR34_PHY_CONTROL_REGS_0 :: PHYBIST_BL2_STATUS :: reserved0 [31:10] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PHYBIST_BL2_STATUS_reserved0_MASK 0xfffffc00
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PHYBIST_BL2_STATUS_reserved0_SHIFT 10
-
-/* DDR34_PHY_CONTROL_REGS_0 :: PHYBIST_BL2_STATUS :: EDC [09:09] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PHYBIST_BL2_STATUS_EDC_MASK 0x00000200
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PHYBIST_BL2_STATUS_EDC_SHIFT 9
-
-/* DDR34_PHY_CONTROL_REGS_0 :: PHYBIST_BL2_STATUS :: DM [08:08] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PHYBIST_BL2_STATUS_DM_MASK 0x00000100
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PHYBIST_BL2_STATUS_DM_SHIFT 8
-
-/* DDR34_PHY_CONTROL_REGS_0 :: PHYBIST_BL2_STATUS :: DQ [07:00] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PHYBIST_BL2_STATUS_DQ_MASK 0x000000ff
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PHYBIST_BL2_STATUS_DQ_SHIFT 0
-
-/***************************************************************************
- *PHYBIST_BL3_STATUS - PhyBist Byte Lane #3 Status Register
- ***************************************************************************/
-/* DDR34_PHY_CONTROL_REGS_0 :: PHYBIST_BL3_STATUS :: reserved0 [31:10] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PHYBIST_BL3_STATUS_reserved0_MASK 0xfffffc00
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PHYBIST_BL3_STATUS_reserved0_SHIFT 10
-
-/* DDR34_PHY_CONTROL_REGS_0 :: PHYBIST_BL3_STATUS :: EDC [09:09] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PHYBIST_BL3_STATUS_EDC_MASK 0x00000200
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PHYBIST_BL3_STATUS_EDC_SHIFT 9
-
-/* DDR34_PHY_CONTROL_REGS_0 :: PHYBIST_BL3_STATUS :: DM [08:08] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PHYBIST_BL3_STATUS_DM_MASK 0x00000100
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PHYBIST_BL3_STATUS_DM_SHIFT 8
-
-/* DDR34_PHY_CONTROL_REGS_0 :: PHYBIST_BL3_STATUS :: DQ [07:00] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PHYBIST_BL3_STATUS_DQ_MASK 0x000000ff
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PHYBIST_BL3_STATUS_DQ_SHIFT 0
-
-/***************************************************************************
- *PHYBIST_BL4_STATUS - PhyBist Byte Lane #4 (ECC) Status Register
- ***************************************************************************/
-/* DDR34_PHY_CONTROL_REGS_0 :: PHYBIST_BL4_STATUS :: reserved0 [31:10] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PHYBIST_BL4_STATUS_reserved0_MASK 0xfffffc00
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PHYBIST_BL4_STATUS_reserved0_SHIFT 10
-
-/* DDR34_PHY_CONTROL_REGS_0 :: PHYBIST_BL4_STATUS :: EDC [09:09] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PHYBIST_BL4_STATUS_EDC_MASK 0x00000200
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PHYBIST_BL4_STATUS_EDC_SHIFT 9
-
-/* DDR34_PHY_CONTROL_REGS_0 :: PHYBIST_BL4_STATUS :: DM [08:08] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PHYBIST_BL4_STATUS_DM_MASK 0x00000100
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PHYBIST_BL4_STATUS_DM_SHIFT 8
-
-/* DDR34_PHY_CONTROL_REGS_0 :: PHYBIST_BL4_STATUS :: DQ [07:00] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PHYBIST_BL4_STATUS_DQ_MASK 0x000000ff
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_PHYBIST_BL4_STATUS_DQ_SHIFT 0
-
-/***************************************************************************
- *STANDBY_CONTROL - Standby Control register
- ***************************************************************************/
-/* DDR34_PHY_CONTROL_REGS_0 :: STANDBY_CONTROL :: reserved0 [31:23] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_STANDBY_CONTROL_reserved0_MASK 0xff800000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_STANDBY_CONTROL_reserved0_SHIFT 23
-
-/* DDR34_PHY_CONTROL_REGS_0 :: STANDBY_CONTROL :: STANDBY_READY [22:22] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_STANDBY_CONTROL_STANDBY_READY_MASK 0x00400000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_STANDBY_CONTROL_STANDBY_READY_SHIFT 22
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_STANDBY_CONTROL_STANDBY_READY_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: STANDBY_CONTROL :: STANDBY_EXIT_PIN_EN [21:21] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_STANDBY_CONTROL_STANDBY_EXIT_PIN_EN_MASK 0x00200000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_STANDBY_CONTROL_STANDBY_EXIT_PIN_EN_SHIFT 21
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_STANDBY_CONTROL_STANDBY_EXIT_PIN_EN_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: STANDBY_CONTROL :: STANDBY_ACTIVE [20:20] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_STANDBY_CONTROL_STANDBY_ACTIVE_MASK 0x00100000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_STANDBY_CONTROL_STANDBY_ACTIVE_SHIFT 20
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_STANDBY_CONTROL_STANDBY_ACTIVE_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: STANDBY_CONTROL :: ARMED [19:19] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_STANDBY_CONTROL_ARMED_MASK 0x00080000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_STANDBY_CONTROL_ARMED_SHIFT 19
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_STANDBY_CONTROL_ARMED_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: STANDBY_CONTROL :: WARMSTART [18:18] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_STANDBY_CONTROL_WARMSTART_MASK 0x00040000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_STANDBY_CONTROL_WARMSTART_SHIFT 18
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_STANDBY_CONTROL_WARMSTART_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: STANDBY_CONTROL :: PWRDOWN_LDO_BIAS [17:16] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_STANDBY_CONTROL_PWRDOWN_LDO_BIAS_MASK 0x00030000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_STANDBY_CONTROL_PWRDOWN_LDO_BIAS_SHIFT 16
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_STANDBY_CONTROL_PWRDOWN_LDO_BIAS_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: STANDBY_CONTROL :: PWRDOWN_LDO_VOLTS [15:14] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_STANDBY_CONTROL_PWRDOWN_LDO_VOLTS_MASK 0x0000c000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_STANDBY_CONTROL_PWRDOWN_LDO_VOLTS_SHIFT 14
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_STANDBY_CONTROL_PWRDOWN_LDO_VOLTS_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: STANDBY_CONTROL :: PWRDOWN_SKIP_MRS [13:13] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_STANDBY_CONTROL_PWRDOWN_SKIP_MRS_MASK 0x00002000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_STANDBY_CONTROL_PWRDOWN_SKIP_MRS_SHIFT 13
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_STANDBY_CONTROL_PWRDOWN_SKIP_MRS_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: STANDBY_CONTROL :: PWRDOWN_RST_N [12:12] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_STANDBY_CONTROL_PWRDOWN_RST_N_MASK 0x00001000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_STANDBY_CONTROL_PWRDOWN_RST_N_SHIFT 12
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_STANDBY_CONTROL_PWRDOWN_RST_N_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: STANDBY_CONTROL :: PWRDOWN_CKE [11:11] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_STANDBY_CONTROL_PWRDOWN_CKE_MASK 0x00000800
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_STANDBY_CONTROL_PWRDOWN_CKE_SHIFT 11
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_STANDBY_CONTROL_PWRDOWN_CKE_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: STANDBY_CONTROL :: LDO_BIAS [10:09] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_STANDBY_CONTROL_LDO_BIAS_MASK 0x00000600
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_STANDBY_CONTROL_LDO_BIAS_SHIFT 9
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_STANDBY_CONTROL_LDO_BIAS_DEFAULT 0x00000003
-
-/* DDR34_PHY_CONTROL_REGS_0 :: STANDBY_CONTROL :: LDO_VOLTS [08:07] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_STANDBY_CONTROL_LDO_VOLTS_MASK 0x00000180
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_STANDBY_CONTROL_LDO_VOLTS_SHIFT 7
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_STANDBY_CONTROL_LDO_VOLTS_DEFAULT 0x00000001
-
-/* DDR34_PHY_CONTROL_REGS_0 :: STANDBY_CONTROL :: SKIP_MRS [06:06] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_STANDBY_CONTROL_SKIP_MRS_MASK 0x00000040
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_STANDBY_CONTROL_SKIP_MRS_SHIFT 6
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_STANDBY_CONTROL_SKIP_MRS_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: STANDBY_CONTROL :: RST_N [05:05] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_STANDBY_CONTROL_RST_N_MASK 0x00000020
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_STANDBY_CONTROL_RST_N_SHIFT 5
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_STANDBY_CONTROL_RST_N_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: STANDBY_CONTROL :: CKE [04:04] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_STANDBY_CONTROL_CKE_MASK 0x00000010
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_STANDBY_CONTROL_CKE_SHIFT 4
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_STANDBY_CONTROL_CKE_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: STANDBY_CONTROL :: STANDBY [03:00] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_STANDBY_CONTROL_STANDBY_MASK 0x0000000f
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_STANDBY_CONTROL_STANDBY_SHIFT 0
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_STANDBY_CONTROL_STANDBY_DEFAULT 0x00000000
-
-/***************************************************************************
- *DEBUG_FREEZE_ENABLE - Freeze-on-error enable register
- ***************************************************************************/
-/* DDR34_PHY_CONTROL_REGS_0 :: DEBUG_FREEZE_ENABLE :: reserved0 [31:05] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_DEBUG_FREEZE_ENABLE_reserved0_MASK 0xffffffe0
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_DEBUG_FREEZE_ENABLE_reserved0_SHIFT 5
-
-/* DDR34_PHY_CONTROL_REGS_0 :: DEBUG_FREEZE_ENABLE :: WLECC [04:04] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_DEBUG_FREEZE_ENABLE_WLECC_MASK 0x00000010
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_DEBUG_FREEZE_ENABLE_WLECC_SHIFT 4
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_DEBUG_FREEZE_ENABLE_WLECC_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: DEBUG_FREEZE_ENABLE :: WL1_BL1 [03:03] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_DEBUG_FREEZE_ENABLE_WL1_BL1_MASK 0x00000008
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_DEBUG_FREEZE_ENABLE_WL1_BL1_SHIFT 3
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_DEBUG_FREEZE_ENABLE_WL1_BL1_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: DEBUG_FREEZE_ENABLE :: WL1_BL0 [02:02] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_DEBUG_FREEZE_ENABLE_WL1_BL0_MASK 0x00000004
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_DEBUG_FREEZE_ENABLE_WL1_BL0_SHIFT 2
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_DEBUG_FREEZE_ENABLE_WL1_BL0_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: DEBUG_FREEZE_ENABLE :: WL0_BL1 [01:01] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_DEBUG_FREEZE_ENABLE_WL0_BL1_MASK 0x00000002
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_DEBUG_FREEZE_ENABLE_WL0_BL1_SHIFT 1
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_DEBUG_FREEZE_ENABLE_WL0_BL1_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: DEBUG_FREEZE_ENABLE :: WL0_BL0 [00:00] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_DEBUG_FREEZE_ENABLE_WL0_BL0_MASK 0x00000001
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_DEBUG_FREEZE_ENABLE_WL0_BL0_SHIFT 0
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_DEBUG_FREEZE_ENABLE_WL0_BL0_DEFAULT 0x00000000
-
-/***************************************************************************
- *DEBUG_MUX_CONTROL - Debug Mux Control register
- ***************************************************************************/
-/* DDR34_PHY_CONTROL_REGS_0 :: DEBUG_MUX_CONTROL :: reserved0 [31:11] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_DEBUG_MUX_CONTROL_reserved0_MASK 0xfffff800
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_DEBUG_MUX_CONTROL_reserved0_SHIFT 11
-
-/* DDR34_PHY_CONTROL_REGS_0 :: DEBUG_MUX_CONTROL :: BYTE_SEL [10:08] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_DEBUG_MUX_CONTROL_BYTE_SEL_MASK 0x00000700
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_DEBUG_MUX_CONTROL_BYTE_SEL_SHIFT 8
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_DEBUG_MUX_CONTROL_BYTE_SEL_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: DEBUG_MUX_CONTROL :: reserved1 [07:06] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_DEBUG_MUX_CONTROL_reserved1_MASK 0x000000c0
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_DEBUG_MUX_CONTROL_reserved1_SHIFT 6
-
-/* DDR34_PHY_CONTROL_REGS_0 :: DEBUG_MUX_CONTROL :: PHASE_SEL [05:04] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_DEBUG_MUX_CONTROL_PHASE_SEL_MASK 0x00000030
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_DEBUG_MUX_CONTROL_PHASE_SEL_SHIFT 4
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_DEBUG_MUX_CONTROL_PHASE_SEL_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: DEBUG_MUX_CONTROL :: SOURCE_SEL [03:00] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_DEBUG_MUX_CONTROL_SOURCE_SEL_MASK 0x0000000f
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_DEBUG_MUX_CONTROL_SOURCE_SEL_SHIFT 0
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_DEBUG_MUX_CONTROL_SOURCE_SEL_DEFAULT 0x00000000
-
-/***************************************************************************
- *DFI_CNTRL - DFI Interface Ownership Control register
- ***************************************************************************/
-/* DDR34_PHY_CONTROL_REGS_0 :: DFI_CNTRL :: reserved0 [31:07] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_DFI_CNTRL_reserved0_MASK 0xffffff80
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_DFI_CNTRL_reserved0_SHIFT 7
-
-/* DDR34_PHY_CONTROL_REGS_0 :: DFI_CNTRL :: DFI_CS1 [06:06] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_DFI_CNTRL_DFI_CS1_MASK 0x00000040
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_DFI_CNTRL_DFI_CS1_SHIFT 6
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_DFI_CNTRL_DFI_CS1_DEFAULT 0x00000001
-
-/* DDR34_PHY_CONTROL_REGS_0 :: DFI_CNTRL :: DFI_CS0 [05:05] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_DFI_CNTRL_DFI_CS0_MASK 0x00000020
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_DFI_CNTRL_DFI_CS0_SHIFT 5
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_DFI_CNTRL_DFI_CS0_DEFAULT 0x00000001
-
-/* DDR34_PHY_CONTROL_REGS_0 :: DFI_CNTRL :: DFI_RST_N [04:04] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_DFI_CNTRL_DFI_RST_N_MASK 0x00000010
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_DFI_CNTRL_DFI_RST_N_SHIFT 4
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_DFI_CNTRL_DFI_RST_N_DEFAULT 0x00000001
-
-/* DDR34_PHY_CONTROL_REGS_0 :: DFI_CNTRL :: DFI_CKE [03:03] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_DFI_CNTRL_DFI_CKE_MASK 0x00000008
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_DFI_CNTRL_DFI_CKE_SHIFT 3
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_DFI_CNTRL_DFI_CKE_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: DFI_CNTRL :: ACK_ENABLE [02:02] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_DFI_CNTRL_ACK_ENABLE_MASK 0x00000004
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_DFI_CNTRL_ACK_ENABLE_SHIFT 2
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_DFI_CNTRL_ACK_ENABLE_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: DFI_CNTRL :: ACK_STATUS [01:01] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_DFI_CNTRL_ACK_STATUS_MASK 0x00000002
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_DFI_CNTRL_ACK_STATUS_SHIFT 1
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_DFI_CNTRL_ACK_STATUS_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: DFI_CNTRL :: ASSERT_REQ [00:00] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_DFI_CNTRL_ASSERT_REQ_MASK 0x00000001
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_DFI_CNTRL_ASSERT_REQ_SHIFT 0
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_DFI_CNTRL_ASSERT_REQ_DEFAULT 0x00000001
-
-/***************************************************************************
- *WRITE_ODT_CNTRL - Write ODT Control register
- ***************************************************************************/
-/* DDR34_PHY_CONTROL_REGS_0 :: WRITE_ODT_CNTRL :: reserved0 [31:13] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_WRITE_ODT_CNTRL_reserved0_MASK 0xffffe000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_WRITE_ODT_CNTRL_reserved0_SHIFT 13
-
-/* DDR34_PHY_CONTROL_REGS_0 :: WRITE_ODT_CNTRL :: ODT_FORCE_VALUE [12:12] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_WRITE_ODT_CNTRL_ODT_FORCE_VALUE_MASK 0x00001000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_WRITE_ODT_CNTRL_ODT_FORCE_VALUE_SHIFT 12
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_WRITE_ODT_CNTRL_ODT_FORCE_VALUE_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: WRITE_ODT_CNTRL :: ODT_FORCE [11:11] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_WRITE_ODT_CNTRL_ODT_FORCE_MASK 0x00000800
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_WRITE_ODT_CNTRL_ODT_FORCE_SHIFT 11
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_WRITE_ODT_CNTRL_ODT_FORCE_DEFAULT 0x00000001
-
-/* DDR34_PHY_CONTROL_REGS_0 :: WRITE_ODT_CNTRL :: ODT_ENABLE [10:10] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_WRITE_ODT_CNTRL_ODT_ENABLE_MASK 0x00000400
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_WRITE_ODT_CNTRL_ODT_ENABLE_SHIFT 10
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_WRITE_ODT_CNTRL_ODT_ENABLE_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: WRITE_ODT_CNTRL :: ODT_LENGTH [09:06] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_WRITE_ODT_CNTRL_ODT_LENGTH_MASK 0x000003c0
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_WRITE_ODT_CNTRL_ODT_LENGTH_SHIFT 6
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_WRITE_ODT_CNTRL_ODT_LENGTH_DEFAULT 0x00000004
-
-/* DDR34_PHY_CONTROL_REGS_0 :: WRITE_ODT_CNTRL :: ODT_DELAY [05:00] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_WRITE_ODT_CNTRL_ODT_DELAY_MASK 0x0000003f
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_WRITE_ODT_CNTRL_ODT_DELAY_SHIFT 0
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_WRITE_ODT_CNTRL_ODT_DELAY_DEFAULT 0x00000010
-
-/***************************************************************************
- *ABI_PAR_CNTRL - ABI and PAR Control register
- ***************************************************************************/
-/* DDR34_PHY_CONTROL_REGS_0 :: ABI_PAR_CNTRL :: reserved0 [31:04] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_ABI_PAR_CNTRL_reserved0_MASK 0xfffffff0
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_ABI_PAR_CNTRL_reserved0_SHIFT 4
-
-/* DDR34_PHY_CONTROL_REGS_0 :: ABI_PAR_CNTRL :: PAR_INCLUDE_AUX [03:03] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_ABI_PAR_CNTRL_PAR_INCLUDE_AUX_MASK 0x00000008
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_ABI_PAR_CNTRL_PAR_INCLUDE_AUX_SHIFT 3
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_ABI_PAR_CNTRL_PAR_INCLUDE_AUX_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: ABI_PAR_CNTRL :: PAR_ENABLE [02:02] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_ABI_PAR_CNTRL_PAR_ENABLE_MASK 0x00000004
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_ABI_PAR_CNTRL_PAR_ENABLE_SHIFT 2
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_ABI_PAR_CNTRL_PAR_ENABLE_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: ABI_PAR_CNTRL :: ABI_INCLUDE_AUX [01:01] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_ABI_PAR_CNTRL_ABI_INCLUDE_AUX_MASK 0x00000002
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_ABI_PAR_CNTRL_ABI_INCLUDE_AUX_SHIFT 1
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_ABI_PAR_CNTRL_ABI_INCLUDE_AUX_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: ABI_PAR_CNTRL :: ABI_ENABLE [00:00] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_ABI_PAR_CNTRL_ABI_ENABLE_MASK 0x00000001
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_ABI_PAR_CNTRL_ABI_ENABLE_SHIFT 0
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_ABI_PAR_CNTRL_ABI_ENABLE_DEFAULT 0x00000000
-
-/***************************************************************************
- *ZQ_CAL - ZQ Calibration Control register
- ***************************************************************************/
-/* DDR34_PHY_CONTROL_REGS_0 :: ZQ_CAL :: reserved0 [31:20] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_ZQ_CAL_reserved0_MASK 0xfff00000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_ZQ_CAL_reserved0_SHIFT 20
-
-/* DDR34_PHY_CONTROL_REGS_0 :: ZQ_CAL :: ZQ_STATUS [19:19] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_ZQ_CAL_ZQ_STATUS_MASK 0x00080000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_ZQ_CAL_ZQ_STATUS_SHIFT 19
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_ZQ_CAL_ZQ_STATUS_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: ZQ_CAL :: ZQ_RXENB [18:18] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_ZQ_CAL_ZQ_RXENB_MASK 0x00040000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_ZQ_CAL_ZQ_RXENB_SHIFT 18
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_ZQ_CAL_ZQ_RXENB_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: ZQ_CAL :: ZQ_IDDQ [17:17] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_ZQ_CAL_ZQ_IDDQ_MASK 0x00020000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_ZQ_CAL_ZQ_IDDQ_SHIFT 17
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_ZQ_CAL_ZQ_IDDQ_DEFAULT 0x00000001
-
-/* DDR34_PHY_CONTROL_REGS_0 :: ZQ_CAL :: ZQ_DRIVE_N [16:12] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_ZQ_CAL_ZQ_DRIVE_N_MASK 0x0001f000
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_ZQ_CAL_ZQ_DRIVE_N_SHIFT 12
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_ZQ_CAL_ZQ_DRIVE_N_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: ZQ_CAL :: ZQ_DRIVE_P [11:07] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_ZQ_CAL_ZQ_DRIVE_P_MASK 0x00000f80
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_ZQ_CAL_ZQ_DRIVE_P_SHIFT 7
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_ZQ_CAL_ZQ_DRIVE_P_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: ZQ_CAL :: ZQ_TX_MODE [06:03] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_ZQ_CAL_ZQ_TX_MODE_MASK 0x00000078
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_ZQ_CAL_ZQ_TX_MODE_SHIFT 3
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_ZQ_CAL_ZQ_TX_MODE_DEFAULT 0x00000000
-
-/* DDR34_PHY_CONTROL_REGS_0 :: ZQ_CAL :: ZQ_RX_MODE [02:00] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_ZQ_CAL_ZQ_RX_MODE_MASK 0x00000007
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_ZQ_CAL_ZQ_RX_MODE_SHIFT 0
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_ZQ_CAL_ZQ_RX_MODE_DEFAULT 0x00000000
-
-/***************************************************************************
- *AC_SPARE_REG - Address and Control Spare register
- ***************************************************************************/
-/* DDR34_PHY_CONTROL_REGS_0 :: AC_SPARE_REG :: reserved_for_eco0 [31:00] */
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_AC_SPARE_REG_reserved_for_eco0_MASK 0xffffffff
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_AC_SPARE_REG_reserved_for_eco0_SHIFT 0
-#define BCHP_DDR34_PHY_CONTROL_REGS_0_AC_SPARE_REG_reserved_for_eco0_DEFAULT 0x00000000
-
-#endif /* #ifndef BCHP_DDR34_PHY_CONTROL_REGS_0_H__ */
-
-/* End of File */
diff --git a/include/linux/brcmstb/7439a0/bchp_ebi.h b/include/linux/brcmstb/7439a0/bchp_ebi.h
deleted file mode 100644
index 8d28b01..0000000
--- a/include/linux/brcmstb/7439a0/bchp_ebi.h
+++ /dev/null
@@ -1,2005 +0,0 @@
-/***************************************************************************
- * Copyright (c) 1999-2012, Broadcom Corporation
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
- *
- * Module Description:
- * DO NOT EDIT THIS FILE DIRECTLY
- *
- * This module was generated magically with RDB from a source description
- * file. You must edit the source file for changes to be made to this file.
- *
- *
- * Date: Generated on Wed Oct 17 03:11:30 2012
- * MD5 Checksum d41d8cd98f00b204e9800998ecf8427e
- *
- * Compiled with: RDB Utility combo_header.pl
- * RDB Parser 3.0
- * unknown unknown
- * Perl Interpreter 5.008008
- * Operating System linux
- *
- * Revision History:
- *
- * $brcm_Log: $
- *
- ***************************************************************************/
-
-#ifndef BCHP_EBI_H__
-#define BCHP_EBI_H__
-
-/***************************************************************************
- *EBI - EBI Registers
- ***************************************************************************/
-#define BCHP_EBI_CS_BASE_HI_0 0x00440800 /* Upper 8-bit of EBI CS Base 0 Register */
-#define BCHP_EBI_CS_BASE_0 0x00440804 /* Lower 32-bit of EBI CS Base 0 Register */
-#define BCHP_EBI_CS_CONFIG_0 0x00440808 /* EBI CS Config 0 Register */
-#define BCHP_EBI_CS_BASE_HI_1 0x0044080c /* Upper 8-bit of EBI CS Base 1 Register */
-#define BCHP_EBI_CS_BASE_1 0x00440810 /* Lower 32-bit of EBI CS Base 1 Register */
-#define BCHP_EBI_CS_CONFIG_1 0x00440814 /* EBI CS Config 1 Register */
-#define BCHP_EBI_CS_BASE_HI_2 0x00440818 /* Upper 8-bit of EBI CS Base 2 Register */
-#define BCHP_EBI_CS_BASE_2 0x0044081c /* Lower 32-bit of EBI CS Base 2 Register */
-#define BCHP_EBI_CS_CONFIG_2 0x00440820 /* EBI CS Config 2 Register */
-#define BCHP_EBI_CS_BASE_HI_3 0x00440824 /* Upper 8-bit of EBI CS Base 3 Register */
-#define BCHP_EBI_CS_BASE_3 0x00440828 /* Lower 32-bit of EBI CS Base 3 Register */
-#define BCHP_EBI_CS_CONFIG_3 0x0044082c /* EBI CS Config 3 Register */
-#define BCHP_EBI_CS_BASE_HI_4 0x00440830 /* Upper 8-bit of EBI CS Base 4 Register */
-#define BCHP_EBI_CS_BASE_4 0x00440834 /* Lower 32-bit of EBI CS Base 4 Register */
-#define BCHP_EBI_CS_CONFIG_4 0x00440838 /* EBI CS Config 4 Register */
-#define BCHP_EBI_CS_BASE_HI_5 0x0044083c /* Upper 8-bit of EBI CS Base 5 Register */
-#define BCHP_EBI_CS_BASE_5 0x00440840 /* Lower 32-bit of EBI CS Base 5 Register */
-#define BCHP_EBI_CS_CONFIG_5 0x00440844 /* EBI CS Config 5 Register */
-#define BCHP_EBI_CS_BASE_HI_6 0x00440848 /* Upper 8-bit of EBI CS Base 6 Register */
-#define BCHP_EBI_CS_BASE_6 0x0044084c /* Lower 32-bit of EBI CS Base 6 Register */
-#define BCHP_EBI_CS_CONFIG_6 0x00440850 /* EBI CS Config 6 Register */
-#define BCHP_EBI_BURST_CFG_0 0x00440860 /* EBI Synchronous Intel StrataFlash Burst Configure Register */
-#define BCHP_EBI_BURST_CFG_1 0x00440864 /* EBI Synchronous Intel StrataFlash Burst Configure Register */
-#define BCHP_EBI_BURST_CFG_2 0x00440868 /* EBI Synchronous Intel StrataFlash Burst Configure Register */
-#define BCHP_EBI_BURST_CFG_3 0x0044086c /* EBI Synchronous Intel StrataFlash Burst Configure Register */
-#define BCHP_EBI_BURST_CFG_4 0x00440870 /* EBI Synchronous Intel StrataFlash Burst Configure Register */
-#define BCHP_EBI_BURST_CFG_5 0x00440874 /* EBI Synchronous Intel StrataFlash Burst Configure Register */
-#define BCHP_EBI_BURST_CFG_6 0x00440878 /* EBI Synchronous Intel StrataFlash Burst Configure Register */
-#define BCHP_EBI_ECR 0x00440900 /* EBI Configuration Register */
-#define BCHP_EBI_CS_TRISTATE_CFG 0x00440918 /* EBI CS Tristate Configuration Register */
-#define BCHP_EBI_CS_SPI_SELECT 0x00440920 /* SPI CS Select */
-#define BCHP_EBI_ARRAY_ADDRESS 0x004409f0 /* EBI Data Array Address */
-
-/***************************************************************************
- *CS_BASE_HI_0 - Upper 8-bit of EBI CS Base 0 Register
- ***************************************************************************/
-/* EBI :: CS_BASE_HI_0 :: reserved0 [31:08] */
-#define BCHP_EBI_CS_BASE_HI_0_reserved0_MASK 0xffffff00
-#define BCHP_EBI_CS_BASE_HI_0_reserved0_SHIFT 8
-
-/* EBI :: CS_BASE_HI_0 :: base_addr_hi [07:00] */
-#define BCHP_EBI_CS_BASE_HI_0_base_addr_hi_MASK 0x000000ff
-#define BCHP_EBI_CS_BASE_HI_0_base_addr_hi_SHIFT 0
-#define BCHP_EBI_CS_BASE_HI_0_base_addr_hi_DEFAULT 0x00000000
-
-/***************************************************************************
- *CS_BASE_0 - Lower 32-bit of EBI CS Base 0 Register
- ***************************************************************************/
-/* EBI :: CS_BASE_0 :: base_addr [31:13] */
-#define BCHP_EBI_CS_BASE_0_base_addr_MASK 0xffffe000
-#define BCHP_EBI_CS_BASE_0_base_addr_SHIFT 13
-
-/* EBI :: CS_BASE_0 :: reserved0 [12:04] */
-#define BCHP_EBI_CS_BASE_0_reserved0_MASK 0x00001ff0
-#define BCHP_EBI_CS_BASE_0_reserved0_SHIFT 4
-
-/* EBI :: CS_BASE_0 :: size [03:00] */
-#define BCHP_EBI_CS_BASE_0_size_MASK 0x0000000f
-#define BCHP_EBI_CS_BASE_0_size_SHIFT 0
-#define BCHP_EBI_CS_BASE_0_size_SIZE_8KB 0
-#define BCHP_EBI_CS_BASE_0_size_SIZE_16KB 1
-#define BCHP_EBI_CS_BASE_0_size_SIZE_32KB 2
-#define BCHP_EBI_CS_BASE_0_size_SIZE_64KB 3
-#define BCHP_EBI_CS_BASE_0_size_SIZE_128KB 4
-#define BCHP_EBI_CS_BASE_0_size_SIZE_256KB 5
-#define BCHP_EBI_CS_BASE_0_size_SIZE_512KB 6
-#define BCHP_EBI_CS_BASE_0_size_SIZE_1MB 7
-#define BCHP_EBI_CS_BASE_0_size_SIZE_2MB 8
-#define BCHP_EBI_CS_BASE_0_size_SIZE_4MB 9
-#define BCHP_EBI_CS_BASE_0_size_SIZE_8MB 10
-#define BCHP_EBI_CS_BASE_0_size_SIZE_16MB 11
-#define BCHP_EBI_CS_BASE_0_size_SIZE_32MB 12
-#define BCHP_EBI_CS_BASE_0_size_SIZE_64MB 13
-#define BCHP_EBI_CS_BASE_0_size_SIZE_128MB 14
-#define BCHP_EBI_CS_BASE_0_size_SIZE_256MB 15
-
-/***************************************************************************
- *CS_CONFIG_0 - EBI CS Config 0 Register
- ***************************************************************************/
-/* EBI :: CS_CONFIG_0 :: mem_io [31:31] */
-#define BCHP_EBI_CS_CONFIG_0_mem_io_MASK 0x80000000
-#define BCHP_EBI_CS_CONFIG_0_mem_io_SHIFT 31
-#define BCHP_EBI_CS_CONFIG_0_mem_io_DEFAULT 0x00000000
-
-/* EBI :: CS_CONFIG_0 :: ta_wait [30:30] */
-#define BCHP_EBI_CS_CONFIG_0_ta_wait_MASK 0x40000000
-#define BCHP_EBI_CS_CONFIG_0_ta_wait_SHIFT 30
-#define BCHP_EBI_CS_CONFIG_0_ta_wait_DEFAULT 0x00000000
-
-/* EBI :: CS_CONFIG_0 :: wp [29:29] */
-#define BCHP_EBI_CS_CONFIG_0_wp_MASK 0x20000000
-#define BCHP_EBI_CS_CONFIG_0_wp_SHIFT 29
-#define BCHP_EBI_CS_CONFIG_0_wp_DEFAULT 0x00000000
-
-/* EBI :: CS_CONFIG_0 :: wait_count [28:24] */
-#define BCHP_EBI_CS_CONFIG_0_wait_count_MASK 0x1f000000
-#define BCHP_EBI_CS_CONFIG_0_wait_count_SHIFT 24
-#define BCHP_EBI_CS_CONFIG_0_wait_count_DEFAULT 0x00000007
-
-/* EBI :: CS_CONFIG_0 :: t_hold [23:20] */
-#define BCHP_EBI_CS_CONFIG_0_t_hold_MASK 0x00f00000
-#define BCHP_EBI_CS_CONFIG_0_t_hold_SHIFT 20
-#define BCHP_EBI_CS_CONFIG_0_t_hold_DEFAULT 0x00000000
-
-/* EBI :: CS_CONFIG_0 :: t_setup [19:16] */
-#define BCHP_EBI_CS_CONFIG_0_t_setup_MASK 0x000f0000
-#define BCHP_EBI_CS_CONFIG_0_t_setup_SHIFT 16
-#define BCHP_EBI_CS_CONFIG_0_t_setup_DEFAULT 0x00000000
-
-/* EBI :: CS_CONFIG_0 :: cs_hold [15:15] */
-#define BCHP_EBI_CS_CONFIG_0_cs_hold_MASK 0x00008000
-#define BCHP_EBI_CS_CONFIG_0_cs_hold_SHIFT 15
-#define BCHP_EBI_CS_CONFIG_0_cs_hold_DEFAULT 0x00000000
-
-/* EBI :: CS_CONFIG_0 :: split_cs [14:14] */
-#define BCHP_EBI_CS_CONFIG_0_split_cs_MASK 0x00004000
-#define BCHP_EBI_CS_CONFIG_0_split_cs_SHIFT 14
-#define BCHP_EBI_CS_CONFIG_0_split_cs_DEFAULT 0x00000000
-
-/* EBI :: CS_CONFIG_0 :: mask_en [13:13] */
-#define BCHP_EBI_CS_CONFIG_0_mask_en_MASK 0x00002000
-#define BCHP_EBI_CS_CONFIG_0_mask_en_SHIFT 13
-#define BCHP_EBI_CS_CONFIG_0_mask_en_DEFAULT 0x00000000
-
-/* EBI :: CS_CONFIG_0 :: ne_sample [12:12] */
-#define BCHP_EBI_CS_CONFIG_0_ne_sample_MASK 0x00001000
-#define BCHP_EBI_CS_CONFIG_0_ne_sample_SHIFT 12
-#define BCHP_EBI_CS_CONFIG_0_ne_sample_DEFAULT 0x00000000
-
-/* EBI :: CS_CONFIG_0 :: m68k [11:11] */
-#define BCHP_EBI_CS_CONFIG_0_m68k_MASK 0x00000800
-#define BCHP_EBI_CS_CONFIG_0_m68k_SHIFT 11
-#define BCHP_EBI_CS_CONFIG_0_m68k_DEFAULT 0x00000000
-
-/* EBI :: CS_CONFIG_0 :: le [10:10] */
-#define BCHP_EBI_CS_CONFIG_0_le_MASK 0x00000400
-#define BCHP_EBI_CS_CONFIG_0_le_SHIFT 10
-
-/* EBI :: CS_CONFIG_0 :: fast_read [09:09] */
-#define BCHP_EBI_CS_CONFIG_0_fast_read_MASK 0x00000200
-#define BCHP_EBI_CS_CONFIG_0_fast_read_SHIFT 9
-#define BCHP_EBI_CS_CONFIG_0_fast_read_DEFAULT 0x00000000
-#define BCHP_EBI_CS_CONFIG_0_fast_read_Normal 0
-#define BCHP_EBI_CS_CONFIG_0_fast_read_Fast_Read_Enable 1
-
-/* EBI :: CS_CONFIG_0 :: size_sel [08:08] */
-#define BCHP_EBI_CS_CONFIG_0_size_sel_MASK 0x00000100
-#define BCHP_EBI_CS_CONFIG_0_size_sel_SHIFT 8
-#define BCHP_EBI_CS_CONFIG_0_size_sel_DEFAULT 0x00000000
-
-/* EBI :: CS_CONFIG_0 :: sync [07:07] */
-#define BCHP_EBI_CS_CONFIG_0_sync_MASK 0x00000080
-#define BCHP_EBI_CS_CONFIG_0_sync_SHIFT 7
-#define BCHP_EBI_CS_CONFIG_0_sync_DEFAULT 0x00000000
-
-/* EBI :: CS_CONFIG_0 :: polarity [06:06] */
-#define BCHP_EBI_CS_CONFIG_0_polarity_MASK 0x00000040
-#define BCHP_EBI_CS_CONFIG_0_polarity_SHIFT 6
-#define BCHP_EBI_CS_CONFIG_0_polarity_DEFAULT 0x00000000
-
-/* EBI :: CS_CONFIG_0 :: we_ctl [05:05] */
-#define BCHP_EBI_CS_CONFIG_0_we_ctl_MASK 0x00000020
-#define BCHP_EBI_CS_CONFIG_0_we_ctl_SHIFT 5
-#define BCHP_EBI_CS_CONFIG_0_we_ctl_DEFAULT 0x00000000
-
-/* EBI :: CS_CONFIG_0 :: dest_size [04:04] */
-#define BCHP_EBI_CS_CONFIG_0_dest_size_MASK 0x00000010
-#define BCHP_EBI_CS_CONFIG_0_dest_size_SHIFT 4
-
-/* EBI :: CS_CONFIG_0 :: ms_inh [03:03] */
-#define BCHP_EBI_CS_CONFIG_0_ms_inh_MASK 0x00000008
-#define BCHP_EBI_CS_CONFIG_0_ms_inh_SHIFT 3
-#define BCHP_EBI_CS_CONFIG_0_ms_inh_DEFAULT 0x00000000
-
-/* EBI :: CS_CONFIG_0 :: ls_inh [02:02] */
-#define BCHP_EBI_CS_CONFIG_0_ls_inh_MASK 0x00000004
-#define BCHP_EBI_CS_CONFIG_0_ls_inh_SHIFT 2
-#define BCHP_EBI_CS_CONFIG_0_ls_inh_DEFAULT 0x00000000
-
-/* EBI :: CS_CONFIG_0 :: bcachen [01:01] */
-#define BCHP_EBI_CS_CONFIG_0_bcachen_MASK 0x00000002
-#define BCHP_EBI_CS_CONFIG_0_bcachen_SHIFT 1
-#define BCHP_EBI_CS_CONFIG_0_bcachen_DEFAULT 0x00000000
-
-/* EBI :: CS_CONFIG_0 :: enable [00:00] */
-#define BCHP_EBI_CS_CONFIG_0_enable_MASK 0x00000001
-#define BCHP_EBI_CS_CONFIG_0_enable_SHIFT 0
-#define BCHP_EBI_CS_CONFIG_0_enable_DEFAULT 0x00000001
-
-/***************************************************************************
- *CS_BASE_HI_1 - Upper 8-bit of EBI CS Base 1 Register
- ***************************************************************************/
-/* EBI :: CS_BASE_HI_1 :: reserved0 [31:08] */
-#define BCHP_EBI_CS_BASE_HI_1_reserved0_MASK 0xffffff00
-#define BCHP_EBI_CS_BASE_HI_1_reserved0_SHIFT 8
-
-/* EBI :: CS_BASE_HI_1 :: base_addr_hi [07:00] */
-#define BCHP_EBI_CS_BASE_HI_1_base_addr_hi_MASK 0x000000ff
-#define BCHP_EBI_CS_BASE_HI_1_base_addr_hi_SHIFT 0
-#define BCHP_EBI_CS_BASE_HI_1_base_addr_hi_DEFAULT 0x00000000
-
-/***************************************************************************
- *CS_BASE_1 - Lower 32-bit of EBI CS Base 1 Register
- ***************************************************************************/
-/* EBI :: CS_BASE_1 :: base_addr [31:13] */
-#define BCHP_EBI_CS_BASE_1_base_addr_MASK 0xffffe000
-#define BCHP_EBI_CS_BASE_1_base_addr_SHIFT 13
-#define BCHP_EBI_CS_BASE_1_base_addr_DEFAULT 0x00000000
-
-/* EBI :: CS_BASE_1 :: reserved0 [12:04] */
-#define BCHP_EBI_CS_BASE_1_reserved0_MASK 0x00001ff0
-#define BCHP_EBI_CS_BASE_1_reserved0_SHIFT 4
-
-/* EBI :: CS_BASE_1 :: size [03:00] */
-#define BCHP_EBI_CS_BASE_1_size_MASK 0x0000000f
-#define BCHP_EBI_CS_BASE_1_size_SHIFT 0
-#define BCHP_EBI_CS_BASE_1_size_DEFAULT 0x00000000
-#define BCHP_EBI_CS_BASE_1_size_SIZE_8KB 0
-#define BCHP_EBI_CS_BASE_1_size_SIZE_16KB 1
-#define BCHP_EBI_CS_BASE_1_size_SIZE_32KB 2
-#define BCHP_EBI_CS_BASE_1_size_SIZE_64KB 3
-#define BCHP_EBI_CS_BASE_1_size_SIZE_128KB 4
-#define BCHP_EBI_CS_BASE_1_size_SIZE_256KB 5
-#define BCHP_EBI_CS_BASE_1_size_SIZE_512KB 6
-#define BCHP_EBI_CS_BASE_1_size_SIZE_1MB 7
-#define BCHP_EBI_CS_BASE_1_size_SIZE_2MB 8
-#define BCHP_EBI_CS_BASE_1_size_SIZE_4MB 9
-#define BCHP_EBI_CS_BASE_1_size_SIZE_8MB 10
-#define BCHP_EBI_CS_BASE_1_size_SIZE_16MB 11
-#define BCHP_EBI_CS_BASE_1_size_SIZE_32MB 12
-#define BCHP_EBI_CS_BASE_1_size_SIZE_64MB 13
-#define BCHP_EBI_CS_BASE_1_size_SIZE_128MB 14
-#define BCHP_EBI_CS_BASE_1_size_SIZE_256MB 15
-
-/***************************************************************************
- *CS_CONFIG_1 - EBI CS Config 1 Register
- ***************************************************************************/
-/* EBI :: CS_CONFIG_1 :: mem_io [31:31] */
-#define BCHP_EBI_CS_CONFIG_1_mem_io_MASK 0x80000000
-#define BCHP_EBI_CS_CONFIG_1_mem_io_SHIFT 31
-#define BCHP_EBI_CS_CONFIG_1_mem_io_DEFAULT 0x00000000
-
-/* EBI :: CS_CONFIG_1 :: ta_wait [30:30] */
-#define BCHP_EBI_CS_CONFIG_1_ta_wait_MASK 0x40000000
-#define BCHP_EBI_CS_CONFIG_1_ta_wait_SHIFT 30
-#define BCHP_EBI_CS_CONFIG_1_ta_wait_DEFAULT 0x00000000
-
-/* EBI :: CS_CONFIG_1 :: wp [29:29] */
-#define BCHP_EBI_CS_CONFIG_1_wp_MASK 0x20000000
-#define BCHP_EBI_CS_CONFIG_1_wp_SHIFT 29
-#define BCHP_EBI_CS_CONFIG_1_wp_DEFAULT 0x00000000
-
-/* EBI :: CS_CONFIG_1 :: wait_count [28:24] */
-#define BCHP_EBI_CS_CONFIG_1_wait_count_MASK 0x1f000000
-#define BCHP_EBI_CS_CONFIG_1_wait_count_SHIFT 24
-#define BCHP_EBI_CS_CONFIG_1_wait_count_DEFAULT 0x00000007
-
-/* EBI :: CS_CONFIG_1 :: t_hold [23:20] */
-#define BCHP_EBI_CS_CONFIG_1_t_hold_MASK 0x00f00000
-#define BCHP_EBI_CS_CONFIG_1_t_hold_SHIFT 20
-#define BCHP_EBI_CS_CONFIG_1_t_hold_DEFAULT 0x00000000
-
-/* EBI :: CS_CONFIG_1 :: t_setup [19:16] */
-#define BCHP_EBI_CS_CONFIG_1_t_setup_MASK 0x000f0000
-#define BCHP_EBI_CS_CONFIG_1_t_setup_SHIFT 16
-#define BCHP_EBI_CS_CONFIG_1_t_setup_DEFAULT 0x00000000
-
-/* EBI :: CS_CONFIG_1 :: cs_hold [15:15] */
-#define BCHP_EBI_CS_CONFIG_1_cs_hold_MASK 0x00008000
-#define BCHP_EBI_CS_CONFIG_1_cs_hold_SHIFT 15
-#define BCHP_EBI_CS_CONFIG_1_cs_hold_DEFAULT 0x00000000
-
-/* EBI :: CS_CONFIG_1 :: split_cs [14:14] */
-#define BCHP_EBI_CS_CONFIG_1_split_cs_MASK 0x00004000
-#define BCHP_EBI_CS_CONFIG_1_split_cs_SHIFT 14
-#define BCHP_EBI_CS_CONFIG_1_split_cs_DEFAULT 0x00000000
-
-/* EBI :: CS_CONFIG_1 :: mask_en [13:13] */
-#define BCHP_EBI_CS_CONFIG_1_mask_en_MASK 0x00002000
-#define BCHP_EBI_CS_CONFIG_1_mask_en_SHIFT 13
-#define BCHP_EBI_CS_CONFIG_1_mask_en_DEFAULT 0x00000000
-
-/* EBI :: CS_CONFIG_1 :: ne_sample [12:12] */
-#define BCHP_EBI_CS_CONFIG_1_ne_sample_MASK 0x00001000
-#define BCHP_EBI_CS_CONFIG_1_ne_sample_SHIFT 12
-#define BCHP_EBI_CS_CONFIG_1_ne_sample_DEFAULT 0x00000000
-
-/* EBI :: CS_CONFIG_1 :: m68k [11:11] */
-#define BCHP_EBI_CS_CONFIG_1_m68k_MASK 0x00000800
-#define BCHP_EBI_CS_CONFIG_1_m68k_SHIFT 11
-#define BCHP_EBI_CS_CONFIG_1_m68k_DEFAULT 0x00000000
-
-/* EBI :: CS_CONFIG_1 :: le [10:10] */
-#define BCHP_EBI_CS_CONFIG_1_le_MASK 0x00000400
-#define BCHP_EBI_CS_CONFIG_1_le_SHIFT 10
-#define BCHP_EBI_CS_CONFIG_1_le_DEFAULT 0x00000000
-
-/* EBI :: CS_CONFIG_1 :: fast_read [09:09] */
-#define BCHP_EBI_CS_CONFIG_1_fast_read_MASK 0x00000200
-#define BCHP_EBI_CS_CONFIG_1_fast_read_SHIFT 9
-#define BCHP_EBI_CS_CONFIG_1_fast_read_DEFAULT 0x00000000
-#define BCHP_EBI_CS_CONFIG_1_fast_read_Normal 0
-#define BCHP_EBI_CS_CONFIG_1_fast_read_Fast_Read_Enable 1
-
-/* EBI :: CS_CONFIG_1 :: size_sel [08:08] */
-#define BCHP_EBI_CS_CONFIG_1_size_sel_MASK 0x00000100
-#define BCHP_EBI_CS_CONFIG_1_size_sel_SHIFT 8
-#define BCHP_EBI_CS_CONFIG_1_size_sel_DEFAULT 0x00000000
-
-/* EBI :: CS_CONFIG_1 :: sync [07:07] */
-#define BCHP_EBI_CS_CONFIG_1_sync_MASK 0x00000080
-#define BCHP_EBI_CS_CONFIG_1_sync_SHIFT 7
-#define BCHP_EBI_CS_CONFIG_1_sync_DEFAULT 0x00000000
-
-/* EBI :: CS_CONFIG_1 :: polarity [06:06] */
-#define BCHP_EBI_CS_CONFIG_1_polarity_MASK 0x00000040
-#define BCHP_EBI_CS_CONFIG_1_polarity_SHIFT 6
-#define BCHP_EBI_CS_CONFIG_1_polarity_DEFAULT 0x00000000
-
-/* EBI :: CS_CONFIG_1 :: we_ctl [05:05] */
-#define BCHP_EBI_CS_CONFIG_1_we_ctl_MASK 0x00000020
-#define BCHP_EBI_CS_CONFIG_1_we_ctl_SHIFT 5
-#define BCHP_EBI_CS_CONFIG_1_we_ctl_DEFAULT 0x00000000
-
-/* EBI :: CS_CONFIG_1 :: dest_size [04:04] */
-#define BCHP_EBI_CS_CONFIG_1_dest_size_MASK 0x00000010
-#define BCHP_EBI_CS_CONFIG_1_dest_size_SHIFT 4
-#define BCHP_EBI_CS_CONFIG_1_dest_size_DEFAULT 0x00000000
-
-/* EBI :: CS_CONFIG_1 :: ms_inh [03:03] */
-#define BCHP_EBI_CS_CONFIG_1_ms_inh_MASK 0x00000008
-#define BCHP_EBI_CS_CONFIG_1_ms_inh_SHIFT 3
-#define BCHP_EBI_CS_CONFIG_1_ms_inh_DEFAULT 0x00000000
-
-/* EBI :: CS_CONFIG_1 :: ls_inh [02:02] */
-#define BCHP_EBI_CS_CONFIG_1_ls_inh_MASK 0x00000004
-#define BCHP_EBI_CS_CONFIG_1_ls_inh_SHIFT 2
-#define BCHP_EBI_CS_CONFIG_1_ls_inh_DEFAULT 0x00000000
-
-/* EBI :: CS_CONFIG_1 :: bcachen [01:01] */
-#define BCHP_EBI_CS_CONFIG_1_bcachen_MASK 0x00000002
-#define BCHP_EBI_CS_CONFIG_1_bcachen_SHIFT 1
-#define BCHP_EBI_CS_CONFIG_1_bcachen_DEFAULT 0x00000000
-
-/* EBI :: CS_CONFIG_1 :: enable [00:00] */
-#define BCHP_EBI_CS_CONFIG_1_enable_MASK 0x00000001
-#define BCHP_EBI_CS_CONFIG_1_enable_SHIFT 0
-#define BCHP_EBI_CS_CONFIG_1_enable_DEFAULT 0x00000000
-
-/***************************************************************************
- *CS_BASE_HI_2 - Upper 8-bit of EBI CS Base 2 Register
- ***************************************************************************/
-/* EBI :: CS_BASE_HI_2 :: reserved0 [31:08] */
-#define BCHP_EBI_CS_BASE_HI_2_reserved0_MASK 0xffffff00
-#define BCHP_EBI_CS_BASE_HI_2_reserved0_SHIFT 8
-
-/* EBI :: CS_BASE_HI_2 :: base_addr_hi [07:00] */
-#define BCHP_EBI_CS_BASE_HI_2_base_addr_hi_MASK 0x000000ff
-#define BCHP_EBI_CS_BASE_HI_2_base_addr_hi_SHIFT 0
-#define BCHP_EBI_CS_BASE_HI_2_base_addr_hi_DEFAULT 0x00000000
-
-/***************************************************************************
- *CS_BASE_2 - Lower 32-bit of EBI CS Base 2 Register
- ***************************************************************************/
-/* EBI :: CS_BASE_2 :: base_addr [31:13] */
-#define BCHP_EBI_CS_BASE_2_base_addr_MASK 0xffffe000
-#define BCHP_EBI_CS_BASE_2_base_addr_SHIFT 13
-#define BCHP_EBI_CS_BASE_2_base_addr_DEFAULT 0x00000000
-
-/* EBI :: CS_BASE_2 :: reserved0 [12:04] */
-#define BCHP_EBI_CS_BASE_2_reserved0_MASK 0x00001ff0
-#define BCHP_EBI_CS_BASE_2_reserved0_SHIFT 4
-
-/* EBI :: CS_BASE_2 :: size [03:00] */
-#define BCHP_EBI_CS_BASE_2_size_MASK 0x0000000f
-#define BCHP_EBI_CS_BASE_2_size_SHIFT 0
-#define BCHP_EBI_CS_BASE_2_size_DEFAULT 0x00000000
-#define BCHP_EBI_CS_BASE_2_size_SIZE_8KB 0
-#define BCHP_EBI_CS_BASE_2_size_SIZE_16KB 1
-#define BCHP_EBI_CS_BASE_2_size_SIZE_32KB 2
-#define BCHP_EBI_CS_BASE_2_size_SIZE_64KB 3
-#define BCHP_EBI_CS_BASE_2_size_SIZE_128KB 4
-#define BCHP_EBI_CS_BASE_2_size_SIZE_256KB 5
-#define BCHP_EBI_CS_BASE_2_size_SIZE_512KB 6
-#define BCHP_EBI_CS_BASE_2_size_SIZE_1MB 7
-#define BCHP_EBI_CS_BASE_2_size_SIZE_2MB 8
-#define BCHP_EBI_CS_BASE_2_size_SIZE_4MB 9
-#define BCHP_EBI_CS_BASE_2_size_SIZE_8MB 10
-#define BCHP_EBI_CS_BASE_2_size_SIZE_16MB 11
-#define BCHP_EBI_CS_BASE_2_size_SIZE_32MB 12
-#define BCHP_EBI_CS_BASE_2_size_SIZE_64MB 13
-#define BCHP_EBI_CS_BASE_2_size_SIZE_128MB 14
-#define BCHP_EBI_CS_BASE_2_size_SIZE_256MB 15
-
-/***************************************************************************
- *CS_CONFIG_2 - EBI CS Config 2 Register
- ***************************************************************************/
-/* EBI :: CS_CONFIG_2 :: mem_io [31:31] */
-#define BCHP_EBI_CS_CONFIG_2_mem_io_MASK 0x80000000
-#define BCHP_EBI_CS_CONFIG_2_mem_io_SHIFT 31
-#define BCHP_EBI_CS_CONFIG_2_mem_io_DEFAULT 0x00000000
-
-/* EBI :: CS_CONFIG_2 :: ta_wait [30:30] */
-#define BCHP_EBI_CS_CONFIG_2_ta_wait_MASK 0x40000000
-#define BCHP_EBI_CS_CONFIG_2_ta_wait_SHIFT 30
-#define BCHP_EBI_CS_CONFIG_2_ta_wait_DEFAULT 0x00000000
-
-/* EBI :: CS_CONFIG_2 :: wp [29:29] */
-#define BCHP_EBI_CS_CONFIG_2_wp_MASK 0x20000000
-#define BCHP_EBI_CS_CONFIG_2_wp_SHIFT 29
-#define BCHP_EBI_CS_CONFIG_2_wp_DEFAULT 0x00000000
-
-/* EBI :: CS_CONFIG_2 :: wait_count [28:24] */
-#define BCHP_EBI_CS_CONFIG_2_wait_count_MASK 0x1f000000
-#define BCHP_EBI_CS_CONFIG_2_wait_count_SHIFT 24
-#define BCHP_EBI_CS_CONFIG_2_wait_count_DEFAULT 0x00000007
-
-/* EBI :: CS_CONFIG_2 :: t_hold [23:20] */
-#define BCHP_EBI_CS_CONFIG_2_t_hold_MASK 0x00f00000
-#define BCHP_EBI_CS_CONFIG_2_t_hold_SHIFT 20
-#define BCHP_EBI_CS_CONFIG_2_t_hold_DEFAULT 0x00000000
-
-/* EBI :: CS_CONFIG_2 :: t_setup [19:16] */
-#define BCHP_EBI_CS_CONFIG_2_t_setup_MASK 0x000f0000
-#define BCHP_EBI_CS_CONFIG_2_t_setup_SHIFT 16
-#define BCHP_EBI_CS_CONFIG_2_t_setup_DEFAULT 0x00000000
-
-/* EBI :: CS_CONFIG_2 :: cs_hold [15:15] */
-#define BCHP_EBI_CS_CONFIG_2_cs_hold_MASK 0x00008000
-#define BCHP_EBI_CS_CONFIG_2_cs_hold_SHIFT 15
-#define BCHP_EBI_CS_CONFIG_2_cs_hold_DEFAULT 0x00000000
-
-/* EBI :: CS_CONFIG_2 :: split_cs [14:14] */
-#define BCHP_EBI_CS_CONFIG_2_split_cs_MASK 0x00004000
-#define BCHP_EBI_CS_CONFIG_2_split_cs_SHIFT 14
-#define BCHP_EBI_CS_CONFIG_2_split_cs_DEFAULT 0x00000000
-
-/* EBI :: CS_CONFIG_2 :: mask_en [13:13] */
-#define BCHP_EBI_CS_CONFIG_2_mask_en_MASK 0x00002000
-#define BCHP_EBI_CS_CONFIG_2_mask_en_SHIFT 13
-#define BCHP_EBI_CS_CONFIG_2_mask_en_DEFAULT 0x00000000
-
-/* EBI :: CS_CONFIG_2 :: ne_sample [12:12] */
-#define BCHP_EBI_CS_CONFIG_2_ne_sample_MASK 0x00001000
-#define BCHP_EBI_CS_CONFIG_2_ne_sample_SHIFT 12
-#define BCHP_EBI_CS_CONFIG_2_ne_sample_DEFAULT 0x00000000
-
-/* EBI :: CS_CONFIG_2 :: m68k [11:11] */
-#define BCHP_EBI_CS_CONFIG_2_m68k_MASK 0x00000800
-#define BCHP_EBI_CS_CONFIG_2_m68k_SHIFT 11
-#define BCHP_EBI_CS_CONFIG_2_m68k_DEFAULT 0x00000000
-
-/* EBI :: CS_CONFIG_2 :: le [10:10] */
-#define BCHP_EBI_CS_CONFIG_2_le_MASK 0x00000400
-#define BCHP_EBI_CS_CONFIG_2_le_SHIFT 10
-#define BCHP_EBI_CS_CONFIG_2_le_DEFAULT 0x00000000
-
-/* EBI :: CS_CONFIG_2 :: fast_read [09:09] */
-#define BCHP_EBI_CS_CONFIG_2_fast_read_MASK 0x00000200
-#define BCHP_EBI_CS_CONFIG_2_fast_read_SHIFT 9
-#define BCHP_EBI_CS_CONFIG_2_fast_read_DEFAULT 0x00000000
-#define BCHP_EBI_CS_CONFIG_2_fast_read_Normal 0
-#define BCHP_EBI_CS_CONFIG_2_fast_read_Fast_Read_Enable 1
-
-/* EBI :: CS_CONFIG_2 :: size_sel [08:08] */
-#define BCHP_EBI_CS_CONFIG_2_size_sel_MASK 0x00000100
-#define BCHP_EBI_CS_CONFIG_2_size_sel_SHIFT 8
-#define BCHP_EBI_CS_CONFIG_2_size_sel_DEFAULT 0x00000000
-
-/* EBI :: CS_CONFIG_2 :: sync [07:07] */
-#define BCHP_EBI_CS_CONFIG_2_sync_MASK 0x00000080
-#define BCHP_EBI_CS_CONFIG_2_sync_SHIFT 7
-#define BCHP_EBI_CS_CONFIG_2_sync_DEFAULT 0x00000000
-
-/* EBI :: CS_CONFIG_2 :: polarity [06:06] */
-#define BCHP_EBI_CS_CONFIG_2_polarity_MASK 0x00000040
-#define BCHP_EBI_CS_CONFIG_2_polarity_SHIFT 6
-#define BCHP_EBI_CS_CONFIG_2_polarity_DEFAULT 0x00000000
-
-/* EBI :: CS_CONFIG_2 :: we_ctl [05:05] */
-#define BCHP_EBI_CS_CONFIG_2_we_ctl_MASK 0x00000020
-#define BCHP_EBI_CS_CONFIG_2_we_ctl_SHIFT 5
-#define BCHP_EBI_CS_CONFIG_2_we_ctl_DEFAULT 0x00000000
-
-/* EBI :: CS_CONFIG_2 :: dest_size [04:04] */
-#define BCHP_EBI_CS_CONFIG_2_dest_size_MASK 0x00000010
-#define BCHP_EBI_CS_CONFIG_2_dest_size_SHIFT 4
-#define BCHP_EBI_CS_CONFIG_2_dest_size_DEFAULT 0x00000000
-
-/* EBI :: CS_CONFIG_2 :: ms_inh [03:03] */
-#define BCHP_EBI_CS_CONFIG_2_ms_inh_MASK 0x00000008
-#define BCHP_EBI_CS_CONFIG_2_ms_inh_SHIFT 3
-#define BCHP_EBI_CS_CONFIG_2_ms_inh_DEFAULT 0x00000000
-
-/* EBI :: CS_CONFIG_2 :: ls_inh [02:02] */
-#define BCHP_EBI_CS_CONFIG_2_ls_inh_MASK 0x00000004
-#define BCHP_EBI_CS_CONFIG_2_ls_inh_SHIFT 2
-#define BCHP_EBI_CS_CONFIG_2_ls_inh_DEFAULT 0x00000000
-
-/* EBI :: CS_CONFIG_2 :: bcachen [01:01] */
-#define BCHP_EBI_CS_CONFIG_2_bcachen_MASK 0x00000002
-#define BCHP_EBI_CS_CONFIG_2_bcachen_SHIFT 1
-#define BCHP_EBI_CS_CONFIG_2_bcachen_DEFAULT 0x00000000
-
-/* EBI :: CS_CONFIG_2 :: enable [00:00] */
-#define BCHP_EBI_CS_CONFIG_2_enable_MASK 0x00000001
-#define BCHP_EBI_CS_CONFIG_2_enable_SHIFT 0
-#define BCHP_EBI_CS_CONFIG_2_enable_DEFAULT 0x00000000
-
-/***************************************************************************
- *CS_BASE_HI_3 - Upper 8-bit of EBI CS Base 3 Register
- ***************************************************************************/
-/* EBI :: CS_BASE_HI_3 :: reserved0 [31:08] */
-#define BCHP_EBI_CS_BASE_HI_3_reserved0_MASK 0xffffff00
-#define BCHP_EBI_CS_BASE_HI_3_reserved0_SHIFT 8
-
-/* EBI :: CS_BASE_HI_3 :: base_addr_hi [07:00] */
-#define BCHP_EBI_CS_BASE_HI_3_base_addr_hi_MASK 0x000000ff
-#define BCHP_EBI_CS_BASE_HI_3_base_addr_hi_SHIFT 0
-#define BCHP_EBI_CS_BASE_HI_3_base_addr_hi_DEFAULT 0x00000000
-
-/***************************************************************************
- *CS_BASE_3 - Lower 32-bit of EBI CS Base 3 Register
- ***************************************************************************/
-/* EBI :: CS_BASE_3 :: base_addr [31:13] */
-#define BCHP_EBI_CS_BASE_3_base_addr_MASK 0xffffe000
-#define BCHP_EBI_CS_BASE_3_base_addr_SHIFT 13
-#define BCHP_EBI_CS_BASE_3_base_addr_DEFAULT 0x00000000
-
-/* EBI :: CS_BASE_3 :: reserved0 [12:04] */
-#define BCHP_EBI_CS_BASE_3_reserved0_MASK 0x00001ff0
-#define BCHP_EBI_CS_BASE_3_reserved0_SHIFT 4
-
-/* EBI :: CS_BASE_3 :: size [03:00] */
-#define BCHP_EBI_CS_BASE_3_size_MASK 0x0000000f
-#define BCHP_EBI_CS_BASE_3_size_SHIFT 0
-#define BCHP_EBI_CS_BASE_3_size_DEFAULT 0x00000000
-#define BCHP_EBI_CS_BASE_3_size_SIZE_8KB 0
-#define BCHP_EBI_CS_BASE_3_size_SIZE_16KB 1
-#define BCHP_EBI_CS_BASE_3_size_SIZE_32KB 2
-#define BCHP_EBI_CS_BASE_3_size_SIZE_64KB 3
-#define BCHP_EBI_CS_BASE_3_size_SIZE_128KB 4
-#define BCHP_EBI_CS_BASE_3_size_SIZE_256KB 5
-#define BCHP_EBI_CS_BASE_3_size_SIZE_512KB 6
-#define BCHP_EBI_CS_BASE_3_size_SIZE_1MB 7
-#define BCHP_EBI_CS_BASE_3_size_SIZE_2MB 8
-#define BCHP_EBI_CS_BASE_3_size_SIZE_4MB 9
-#define BCHP_EBI_CS_BASE_3_size_SIZE_8MB 10
-#define BCHP_EBI_CS_BASE_3_size_SIZE_16MB 11
-#define BCHP_EBI_CS_BASE_3_size_SIZE_32MB 12
-#define BCHP_EBI_CS_BASE_3_size_SIZE_64MB 13
-#define BCHP_EBI_CS_BASE_3_size_SIZE_128MB 14
-#define BCHP_EBI_CS_BASE_3_size_SIZE_256MB 15
-
-/***************************************************************************
- *CS_CONFIG_3 - EBI CS Config 3 Register
- ***************************************************************************/
-/* EBI :: CS_CONFIG_3 :: mem_io [31:31] */
-#define BCHP_EBI_CS_CONFIG_3_mem_io_MASK 0x80000000
-#define BCHP_EBI_CS_CONFIG_3_mem_io_SHIFT 31
-#define BCHP_EBI_CS_CONFIG_3_mem_io_DEFAULT 0x00000000
-
-/* EBI :: CS_CONFIG_3 :: ta_wait [30:30] */
-#define BCHP_EBI_CS_CONFIG_3_ta_wait_MASK 0x40000000
-#define BCHP_EBI_CS_CONFIG_3_ta_wait_SHIFT 30
-#define BCHP_EBI_CS_CONFIG_3_ta_wait_DEFAULT 0x00000000
-
-/* EBI :: CS_CONFIG_3 :: wp [29:29] */
-#define BCHP_EBI_CS_CONFIG_3_wp_MASK 0x20000000
-#define BCHP_EBI_CS_CONFIG_3_wp_SHIFT 29
-#define BCHP_EBI_CS_CONFIG_3_wp_DEFAULT 0x00000000
-
-/* EBI :: CS_CONFIG_3 :: wait_count [28:24] */
-#define BCHP_EBI_CS_CONFIG_3_wait_count_MASK 0x1f000000
-#define BCHP_EBI_CS_CONFIG_3_wait_count_SHIFT 24
-#define BCHP_EBI_CS_CONFIG_3_wait_count_DEFAULT 0x00000007
-
-/* EBI :: CS_CONFIG_3 :: t_hold [23:20] */
-#define BCHP_EBI_CS_CONFIG_3_t_hold_MASK 0x00f00000
-#define BCHP_EBI_CS_CONFIG_3_t_hold_SHIFT 20
-#define BCHP_EBI_CS_CONFIG_3_t_hold_DEFAULT 0x00000000
-
-/* EBI :: CS_CONFIG_3 :: t_setup [19:16] */
-#define BCHP_EBI_CS_CONFIG_3_t_setup_MASK 0x000f0000
-#define BCHP_EBI_CS_CONFIG_3_t_setup_SHIFT 16
-#define BCHP_EBI_CS_CONFIG_3_t_setup_DEFAULT 0x00000000
-
-/* EBI :: CS_CONFIG_3 :: cs_hold [15:15] */
-#define BCHP_EBI_CS_CONFIG_3_cs_hold_MASK 0x00008000
-#define BCHP_EBI_CS_CONFIG_3_cs_hold_SHIFT 15
-#define BCHP_EBI_CS_CONFIG_3_cs_hold_DEFAULT 0x00000000
-
-/* EBI :: CS_CONFIG_3 :: split_cs [14:14] */
-#define BCHP_EBI_CS_CONFIG_3_split_cs_MASK 0x00004000
-#define BCHP_EBI_CS_CONFIG_3_split_cs_SHIFT 14
-#define BCHP_EBI_CS_CONFIG_3_split_cs_DEFAULT 0x00000000
-
-/* EBI :: CS_CONFIG_3 :: mask_en [13:13] */
-#define BCHP_EBI_CS_CONFIG_3_mask_en_MASK 0x00002000
-#define BCHP_EBI_CS_CONFIG_3_mask_en_SHIFT 13
-#define BCHP_EBI_CS_CONFIG_3_mask_en_DEFAULT 0x00000000
-
-/* EBI :: CS_CONFIG_3 :: ne_sample [12:12] */
-#define BCHP_EBI_CS_CONFIG_3_ne_sample_MASK 0x00001000
-#define BCHP_EBI_CS_CONFIG_3_ne_sample_SHIFT 12
-#define BCHP_EBI_CS_CONFIG_3_ne_sample_DEFAULT 0x00000000
-
-/* EBI :: CS_CONFIG_3 :: m68k [11:11] */
-#define BCHP_EBI_CS_CONFIG_3_m68k_MASK 0x00000800
-#define BCHP_EBI_CS_CONFIG_3_m68k_SHIFT 11
-#define BCHP_EBI_CS_CONFIG_3_m68k_DEFAULT 0x00000000
-
-/* EBI :: CS_CONFIG_3 :: le [10:10] */
-#define BCHP_EBI_CS_CONFIG_3_le_MASK 0x00000400
-#define BCHP_EBI_CS_CONFIG_3_le_SHIFT 10
-#define BCHP_EBI_CS_CONFIG_3_le_DEFAULT 0x00000000
-
-/* EBI :: CS_CONFIG_3 :: fast_read [09:09] */
-#define BCHP_EBI_CS_CONFIG_3_fast_read_MASK 0x00000200
-#define BCHP_EBI_CS_CONFIG_3_fast_read_SHIFT 9
-#define BCHP_EBI_CS_CONFIG_3_fast_read_DEFAULT 0x00000000
-#define BCHP_EBI_CS_CONFIG_3_fast_read_Normal 0
-#define BCHP_EBI_CS_CONFIG_3_fast_read_Fast_Read_Enable 1
-
-/* EBI :: CS_CONFIG_3 :: size_sel [08:08] */
-#define BCHP_EBI_CS_CONFIG_3_size_sel_MASK 0x00000100
-#define BCHP_EBI_CS_CONFIG_3_size_sel_SHIFT 8
-#define BCHP_EBI_CS_CONFIG_3_size_sel_DEFAULT 0x00000000
-
-/* EBI :: CS_CONFIG_3 :: sync [07:07] */
-#define BCHP_EBI_CS_CONFIG_3_sync_MASK 0x00000080
-#define BCHP_EBI_CS_CONFIG_3_sync_SHIFT 7
-#define BCHP_EBI_CS_CONFIG_3_sync_DEFAULT 0x00000000
-
-/* EBI :: CS_CONFIG_3 :: polarity [06:06] */
-#define BCHP_EBI_CS_CONFIG_3_polarity_MASK 0x00000040
-#define BCHP_EBI_CS_CONFIG_3_polarity_SHIFT 6
-#define BCHP_EBI_CS_CONFIG_3_polarity_DEFAULT 0x00000000
-
-/* EBI :: CS_CONFIG_3 :: we_ctl [05:05] */
-#define BCHP_EBI_CS_CONFIG_3_we_ctl_MASK 0x00000020
-#define BCHP_EBI_CS_CONFIG_3_we_ctl_SHIFT 5
-#define BCHP_EBI_CS_CONFIG_3_we_ctl_DEFAULT 0x00000000
-
-/* EBI :: CS_CONFIG_3 :: dest_size [04:04] */
-#define BCHP_EBI_CS_CONFIG_3_dest_size_MASK 0x00000010
-#define BCHP_EBI_CS_CONFIG_3_dest_size_SHIFT 4
-#define BCHP_EBI_CS_CONFIG_3_dest_size_DEFAULT 0x00000000
-
-/* EBI :: CS_CONFIG_3 :: ms_inh [03:03] */
-#define BCHP_EBI_CS_CONFIG_3_ms_inh_MASK 0x00000008
-#define BCHP_EBI_CS_CONFIG_3_ms_inh_SHIFT 3
-#define BCHP_EBI_CS_CONFIG_3_ms_inh_DEFAULT 0x00000000
-
-/* EBI :: CS_CONFIG_3 :: ls_inh [02:02] */
-#define BCHP_EBI_CS_CONFIG_3_ls_inh_MASK 0x00000004
-#define BCHP_EBI_CS_CONFIG_3_ls_inh_SHIFT 2
-#define BCHP_EBI_CS_CONFIG_3_ls_inh_DEFAULT 0x00000000
-
-/* EBI :: CS_CONFIG_3 :: bcachen [01:01] */
-#define BCHP_EBI_CS_CONFIG_3_bcachen_MASK 0x00000002
-#define BCHP_EBI_CS_CONFIG_3_bcachen_SHIFT 1
-#define BCHP_EBI_CS_CONFIG_3_bcachen_DEFAULT 0x00000000
-
-/* EBI :: CS_CONFIG_3 :: enable [00:00] */
-#define BCHP_EBI_CS_CONFIG_3_enable_MASK 0x00000001
-#define BCHP_EBI_CS_CONFIG_3_enable_SHIFT 0
-#define BCHP_EBI_CS_CONFIG_3_enable_DEFAULT 0x00000000
-
-/***************************************************************************
- *CS_BASE_HI_4 - Upper 8-bit of EBI CS Base 4 Register
- ***************************************************************************/
-/* EBI :: CS_BASE_HI_4 :: reserved0 [31:08] */
-#define BCHP_EBI_CS_BASE_HI_4_reserved0_MASK 0xffffff00
-#define BCHP_EBI_CS_BASE_HI_4_reserved0_SHIFT 8
-
-/* EBI :: CS_BASE_HI_4 :: base_addr_hi [07:00] */
-#define BCHP_EBI_CS_BASE_HI_4_base_addr_hi_MASK 0x000000ff
-#define BCHP_EBI_CS_BASE_HI_4_base_addr_hi_SHIFT 0
-#define BCHP_EBI_CS_BASE_HI_4_base_addr_hi_DEFAULT 0x00000000
-
-/***************************************************************************
- *CS_BASE_4 - Lower 32-bit of EBI CS Base 4 Register
- ***************************************************************************/
-/* EBI :: CS_BASE_4 :: base_addr [31:13] */
-#define BCHP_EBI_CS_BASE_4_base_addr_MASK 0xffffe000
-#define BCHP_EBI_CS_BASE_4_base_addr_SHIFT 13
-#define BCHP_EBI_CS_BASE_4_base_addr_DEFAULT 0x00000000
-
-/* EBI :: CS_BASE_4 :: reserved0 [12:04] */
-#define BCHP_EBI_CS_BASE_4_reserved0_MASK 0x00001ff0
-#define BCHP_EBI_CS_BASE_4_reserved0_SHIFT 4
-
-/* EBI :: CS_BASE_4 :: size [03:00] */
-#define BCHP_EBI_CS_BASE_4_size_MASK 0x0000000f
-#define BCHP_EBI_CS_BASE_4_size_SHIFT 0
-#define BCHP_EBI_CS_BASE_4_size_DEFAULT 0x00000000
-#define BCHP_EBI_CS_BASE_4_size_SIZE_8KB 0
-#define BCHP_EBI_CS_BASE_4_size_SIZE_16KB 1
-#define BCHP_EBI_CS_BASE_4_size_SIZE_32KB 2
-#define BCHP_EBI_CS_BASE_4_size_SIZE_64KB 3
-#define BCHP_EBI_CS_BASE_4_size_SIZE_128KB 4
-#define BCHP_EBI_CS_BASE_4_size_SIZE_256KB 5
-#define BCHP_EBI_CS_BASE_4_size_SIZE_512KB 6
-#define BCHP_EBI_CS_BASE_4_size_SIZE_1MB 7
-#define BCHP_EBI_CS_BASE_4_size_SIZE_2MB 8
-#define BCHP_EBI_CS_BASE_4_size_SIZE_4MB 9
-#define BCHP_EBI_CS_BASE_4_size_SIZE_8MB 10
-#define BCHP_EBI_CS_BASE_4_size_SIZE_16MB 11
-#define BCHP_EBI_CS_BASE_4_size_SIZE_32MB 12
-#define BCHP_EBI_CS_BASE_4_size_SIZE_64MB 13
-#define BCHP_EBI_CS_BASE_4_size_SIZE_128MB 14
-#define BCHP_EBI_CS_BASE_4_size_SIZE_256MB 15
-
-/***************************************************************************
- *CS_CONFIG_4 - EBI CS Config 4 Register
- ***************************************************************************/
-/* EBI :: CS_CONFIG_4 :: mem_io [31:31] */
-#define BCHP_EBI_CS_CONFIG_4_mem_io_MASK 0x80000000
-#define BCHP_EBI_CS_CONFIG_4_mem_io_SHIFT 31
-#define BCHP_EBI_CS_CONFIG_4_mem_io_DEFAULT 0x00000000
-
-/* EBI :: CS_CONFIG_4 :: ta_wait [30:30] */
-#define BCHP_EBI_CS_CONFIG_4_ta_wait_MASK 0x40000000
-#define BCHP_EBI_CS_CONFIG_4_ta_wait_SHIFT 30
-#define BCHP_EBI_CS_CONFIG_4_ta_wait_DEFAULT 0x00000000
-
-/* EBI :: CS_CONFIG_4 :: wp [29:29] */
-#define BCHP_EBI_CS_CONFIG_4_wp_MASK 0x20000000
-#define BCHP_EBI_CS_CONFIG_4_wp_SHIFT 29
-#define BCHP_EBI_CS_CONFIG_4_wp_DEFAULT 0x00000000
-
-/* EBI :: CS_CONFIG_4 :: wait_count [28:24] */
-#define BCHP_EBI_CS_CONFIG_4_wait_count_MASK 0x1f000000
-#define BCHP_EBI_CS_CONFIG_4_wait_count_SHIFT 24
-#define BCHP_EBI_CS_CONFIG_4_wait_count_DEFAULT 0x00000007
-
-/* EBI :: CS_CONFIG_4 :: t_hold [23:20] */
-#define BCHP_EBI_CS_CONFIG_4_t_hold_MASK 0x00f00000
-#define BCHP_EBI_CS_CONFIG_4_t_hold_SHIFT 20
-#define BCHP_EBI_CS_CONFIG_4_t_hold_DEFAULT 0x00000000
-
-/* EBI :: CS_CONFIG_4 :: t_setup [19:16] */
-#define BCHP_EBI_CS_CONFIG_4_t_setup_MASK 0x000f0000
-#define BCHP_EBI_CS_CONFIG_4_t_setup_SHIFT 16
-#define BCHP_EBI_CS_CONFIG_4_t_setup_DEFAULT 0x00000000
-
-/* EBI :: CS_CONFIG_4 :: cs_hold [15:15] */
-#define BCHP_EBI_CS_CONFIG_4_cs_hold_MASK 0x00008000
-#define BCHP_EBI_CS_CONFIG_4_cs_hold_SHIFT 15
-#define BCHP_EBI_CS_CONFIG_4_cs_hold_DEFAULT 0x00000000
-
-/* EBI :: CS_CONFIG_4 :: split_cs [14:14] */
-#define BCHP_EBI_CS_CONFIG_4_split_cs_MASK 0x00004000
-#define BCHP_EBI_CS_CONFIG_4_split_cs_SHIFT 14
-#define BCHP_EBI_CS_CONFIG_4_split_cs_DEFAULT 0x00000000
-
-/* EBI :: CS_CONFIG_4 :: mask_en [13:13] */
-#define BCHP_EBI_CS_CONFIG_4_mask_en_MASK 0x00002000
-#define BCHP_EBI_CS_CONFIG_4_mask_en_SHIFT 13
-#define BCHP_EBI_CS_CONFIG_4_mask_en_DEFAULT 0x00000000
-
-/* EBI :: CS_CONFIG_4 :: ne_sample [12:12] */
-#define BCHP_EBI_CS_CONFIG_4_ne_sample_MASK 0x00001000
-#define BCHP_EBI_CS_CONFIG_4_ne_sample_SHIFT 12
-#define BCHP_EBI_CS_CONFIG_4_ne_sample_DEFAULT 0x00000000
-
-/* EBI :: CS_CONFIG_4 :: m68k [11:11] */
-#define BCHP_EBI_CS_CONFIG_4_m68k_MASK 0x00000800
-#define BCHP_EBI_CS_CONFIG_4_m68k_SHIFT 11
-#define BCHP_EBI_CS_CONFIG_4_m68k_DEFAULT 0x00000000
-
-/* EBI :: CS_CONFIG_4 :: le [10:10] */
-#define BCHP_EBI_CS_CONFIG_4_le_MASK 0x00000400
-#define BCHP_EBI_CS_CONFIG_4_le_SHIFT 10
-#define BCHP_EBI_CS_CONFIG_4_le_DEFAULT 0x00000000
-
-/* EBI :: CS_CONFIG_4 :: fast_read [09:09] */
-#define BCHP_EBI_CS_CONFIG_4_fast_read_MASK 0x00000200
-#define BCHP_EBI_CS_CONFIG_4_fast_read_SHIFT 9
-#define BCHP_EBI_CS_CONFIG_4_fast_read_DEFAULT 0x00000000
-#define BCHP_EBI_CS_CONFIG_4_fast_read_Normal 0
-#define BCHP_EBI_CS_CONFIG_4_fast_read_Fast_Read_Enable 1
-
-/* EBI :: CS_CONFIG_4 :: size_sel [08:08] */
-#define BCHP_EBI_CS_CONFIG_4_size_sel_MASK 0x00000100
-#define BCHP_EBI_CS_CONFIG_4_size_sel_SHIFT 8
-#define BCHP_EBI_CS_CONFIG_4_size_sel_DEFAULT 0x00000000
-
-/* EBI :: CS_CONFIG_4 :: sync [07:07] */
-#define BCHP_EBI_CS_CONFIG_4_sync_MASK 0x00000080
-#define BCHP_EBI_CS_CONFIG_4_sync_SHIFT 7
-#define BCHP_EBI_CS_CONFIG_4_sync_DEFAULT 0x00000000
-
-/* EBI :: CS_CONFIG_4 :: polarity [06:06] */
-#define BCHP_EBI_CS_CONFIG_4_polarity_MASK 0x00000040
-#define BCHP_EBI_CS_CONFIG_4_polarity_SHIFT 6
-#define BCHP_EBI_CS_CONFIG_4_polarity_DEFAULT 0x00000000
-
-/* EBI :: CS_CONFIG_4 :: we_ctl [05:05] */
-#define BCHP_EBI_CS_CONFIG_4_we_ctl_MASK 0x00000020
-#define BCHP_EBI_CS_CONFIG_4_we_ctl_SHIFT 5
-#define BCHP_EBI_CS_CONFIG_4_we_ctl_DEFAULT 0x00000000
-
-/* EBI :: CS_CONFIG_4 :: dest_size [04:04] */
-#define BCHP_EBI_CS_CONFIG_4_dest_size_MASK 0x00000010
-#define BCHP_EBI_CS_CONFIG_4_dest_size_SHIFT 4
-#define BCHP_EBI_CS_CONFIG_4_dest_size_DEFAULT 0x00000000
-
-/* EBI :: CS_CONFIG_4 :: ms_inh [03:03] */
-#define BCHP_EBI_CS_CONFIG_4_ms_inh_MASK 0x00000008
-#define BCHP_EBI_CS_CONFIG_4_ms_inh_SHIFT 3
-#define BCHP_EBI_CS_CONFIG_4_ms_inh_DEFAULT 0x00000000
-
-/* EBI :: CS_CONFIG_4 :: ls_inh [02:02] */
-#define BCHP_EBI_CS_CONFIG_4_ls_inh_MASK 0x00000004
-#define BCHP_EBI_CS_CONFIG_4_ls_inh_SHIFT 2
-#define BCHP_EBI_CS_CONFIG_4_ls_inh_DEFAULT 0x00000000
-
-/* EBI :: CS_CONFIG_4 :: bcachen [01:01] */
-#define BCHP_EBI_CS_CONFIG_4_bcachen_MASK 0x00000002
-#define BCHP_EBI_CS_CONFIG_4_bcachen_SHIFT 1
-#define BCHP_EBI_CS_CONFIG_4_bcachen_DEFAULT 0x00000000
-
-/* EBI :: CS_CONFIG_4 :: enable [00:00] */
-#define BCHP_EBI_CS_CONFIG_4_enable_MASK 0x00000001
-#define BCHP_EBI_CS_CONFIG_4_enable_SHIFT 0
-#define BCHP_EBI_CS_CONFIG_4_enable_DEFAULT 0x00000000
-
-/***************************************************************************
- *CS_BASE_HI_5 - Upper 8-bit of EBI CS Base 5 Register
- ***************************************************************************/
-/* EBI :: CS_BASE_HI_5 :: reserved0 [31:08] */
-#define BCHP_EBI_CS_BASE_HI_5_reserved0_MASK 0xffffff00
-#define BCHP_EBI_CS_BASE_HI_5_reserved0_SHIFT 8
-
-/* EBI :: CS_BASE_HI_5 :: base_addr_hi [07:00] */
-#define BCHP_EBI_CS_BASE_HI_5_base_addr_hi_MASK 0x000000ff
-#define BCHP_EBI_CS_BASE_HI_5_base_addr_hi_SHIFT 0
-#define BCHP_EBI_CS_BASE_HI_5_base_addr_hi_DEFAULT 0x00000000
-
-/***************************************************************************
- *CS_BASE_5 - Lower 32-bit of EBI CS Base 5 Register
- ***************************************************************************/
-/* EBI :: CS_BASE_5 :: base_addr [31:13] */
-#define BCHP_EBI_CS_BASE_5_base_addr_MASK 0xffffe000
-#define BCHP_EBI_CS_BASE_5_base_addr_SHIFT 13
-#define BCHP_EBI_CS_BASE_5_base_addr_DEFAULT 0x00000000
-
-/* EBI :: CS_BASE_5 :: reserved0 [12:04] */
-#define BCHP_EBI_CS_BASE_5_reserved0_MASK 0x00001ff0
-#define BCHP_EBI_CS_BASE_5_reserved0_SHIFT 4
-
-/* EBI :: CS_BASE_5 :: size [03:00] */
-#define BCHP_EBI_CS_BASE_5_size_MASK 0x0000000f
-#define BCHP_EBI_CS_BASE_5_size_SHIFT 0
-#define BCHP_EBI_CS_BASE_5_size_DEFAULT 0x00000000
-#define BCHP_EBI_CS_BASE_5_size_SIZE_8KB 0
-#define BCHP_EBI_CS_BASE_5_size_SIZE_16KB 1
-#define BCHP_EBI_CS_BASE_5_size_SIZE_32KB 2
-#define BCHP_EBI_CS_BASE_5_size_SIZE_64KB 3
-#define BCHP_EBI_CS_BASE_5_size_SIZE_128KB 4
-#define BCHP_EBI_CS_BASE_5_size_SIZE_256KB 5
-#define BCHP_EBI_CS_BASE_5_size_SIZE_512KB 6
-#define BCHP_EBI_CS_BASE_5_size_SIZE_1MB 7
-#define BCHP_EBI_CS_BASE_5_size_SIZE_2MB 8
-#define BCHP_EBI_CS_BASE_5_size_SIZE_4MB 9
-#define BCHP_EBI_CS_BASE_5_size_SIZE_8MB 10
-#define BCHP_EBI_CS_BASE_5_size_SIZE_16MB 11
-#define BCHP_EBI_CS_BASE_5_size_SIZE_32MB 12
-#define BCHP_EBI_CS_BASE_5_size_SIZE_64MB 13
-#define BCHP_EBI_CS_BASE_5_size_SIZE_128MB 14
-#define BCHP_EBI_CS_BASE_5_size_SIZE_256MB 15
-
-/***************************************************************************
- *CS_CONFIG_5 - EBI CS Config 5 Register
- ***************************************************************************/
-/* EBI :: CS_CONFIG_5 :: mem_io [31:31] */
-#define BCHP_EBI_CS_CONFIG_5_mem_io_MASK 0x80000000
-#define BCHP_EBI_CS_CONFIG_5_mem_io_SHIFT 31
-#define BCHP_EBI_CS_CONFIG_5_mem_io_DEFAULT 0x00000000
-
-/* EBI :: CS_CONFIG_5 :: ta_wait [30:30] */
-#define BCHP_EBI_CS_CONFIG_5_ta_wait_MASK 0x40000000
-#define BCHP_EBI_CS_CONFIG_5_ta_wait_SHIFT 30
-#define BCHP_EBI_CS_CONFIG_5_ta_wait_DEFAULT 0x00000000
-
-/* EBI :: CS_CONFIG_5 :: wp [29:29] */
-#define BCHP_EBI_CS_CONFIG_5_wp_MASK 0x20000000
-#define BCHP_EBI_CS_CONFIG_5_wp_SHIFT 29
-#define BCHP_EBI_CS_CONFIG_5_wp_DEFAULT 0x00000000
-
-/* EBI :: CS_CONFIG_5 :: wait_count [28:24] */
-#define BCHP_EBI_CS_CONFIG_5_wait_count_MASK 0x1f000000
-#define BCHP_EBI_CS_CONFIG_5_wait_count_SHIFT 24
-#define BCHP_EBI_CS_CONFIG_5_wait_count_DEFAULT 0x00000007
-
-/* EBI :: CS_CONFIG_5 :: t_hold [23:20] */
-#define BCHP_EBI_CS_CONFIG_5_t_hold_MASK 0x00f00000
-#define BCHP_EBI_CS_CONFIG_5_t_hold_SHIFT 20
-#define BCHP_EBI_CS_CONFIG_5_t_hold_DEFAULT 0x00000000
-
-/* EBI :: CS_CONFIG_5 :: t_setup [19:16] */
-#define BCHP_EBI_CS_CONFIG_5_t_setup_MASK 0x000f0000
-#define BCHP_EBI_CS_CONFIG_5_t_setup_SHIFT 16
-#define BCHP_EBI_CS_CONFIG_5_t_setup_DEFAULT 0x00000000
-
-/* EBI :: CS_CONFIG_5 :: cs_hold [15:15] */
-#define BCHP_EBI_CS_CONFIG_5_cs_hold_MASK 0x00008000
-#define BCHP_EBI_CS_CONFIG_5_cs_hold_SHIFT 15
-#define BCHP_EBI_CS_CONFIG_5_cs_hold_DEFAULT 0x00000000
-
-/* EBI :: CS_CONFIG_5 :: split_cs [14:14] */
-#define BCHP_EBI_CS_CONFIG_5_split_cs_MASK 0x00004000
-#define BCHP_EBI_CS_CONFIG_5_split_cs_SHIFT 14
-#define BCHP_EBI_CS_CONFIG_5_split_cs_DEFAULT 0x00000000
-
-/* EBI :: CS_CONFIG_5 :: mask_en [13:13] */
-#define BCHP_EBI_CS_CONFIG_5_mask_en_MASK 0x00002000
-#define BCHP_EBI_CS_CONFIG_5_mask_en_SHIFT 13
-#define BCHP_EBI_CS_CONFIG_5_mask_en_DEFAULT 0x00000000
-
-/* EBI :: CS_CONFIG_5 :: ne_sample [12:12] */
-#define BCHP_EBI_CS_CONFIG_5_ne_sample_MASK 0x00001000
-#define BCHP_EBI_CS_CONFIG_5_ne_sample_SHIFT 12
-#define BCHP_EBI_CS_CONFIG_5_ne_sample_DEFAULT 0x00000000
-
-/* EBI :: CS_CONFIG_5 :: m68k [11:11] */
-#define BCHP_EBI_CS_CONFIG_5_m68k_MASK 0x00000800
-#define BCHP_EBI_CS_CONFIG_5_m68k_SHIFT 11
-#define BCHP_EBI_CS_CONFIG_5_m68k_DEFAULT 0x00000000
-
-/* EBI :: CS_CONFIG_5 :: le [10:10] */
-#define BCHP_EBI_CS_CONFIG_5_le_MASK 0x00000400
-#define BCHP_EBI_CS_CONFIG_5_le_SHIFT 10
-#define BCHP_EBI_CS_CONFIG_5_le_DEFAULT 0x00000000
-
-/* EBI :: CS_CONFIG_5 :: fast_read [09:09] */
-#define BCHP_EBI_CS_CONFIG_5_fast_read_MASK 0x00000200
-#define BCHP_EBI_CS_CONFIG_5_fast_read_SHIFT 9
-#define BCHP_EBI_CS_CONFIG_5_fast_read_DEFAULT 0x00000000
-#define BCHP_EBI_CS_CONFIG_5_fast_read_Normal 0
-#define BCHP_EBI_CS_CONFIG_5_fast_read_Fast_Read_Enable 1
-
-/* EBI :: CS_CONFIG_5 :: size_sel [08:08] */
-#define BCHP_EBI_CS_CONFIG_5_size_sel_MASK 0x00000100
-#define BCHP_EBI_CS_CONFIG_5_size_sel_SHIFT 8
-#define BCHP_EBI_CS_CONFIG_5_size_sel_DEFAULT 0x00000000
-
-/* EBI :: CS_CONFIG_5 :: sync [07:07] */
-#define BCHP_EBI_CS_CONFIG_5_sync_MASK 0x00000080
-#define BCHP_EBI_CS_CONFIG_5_sync_SHIFT 7
-#define BCHP_EBI_CS_CONFIG_5_sync_DEFAULT 0x00000000
-
-/* EBI :: CS_CONFIG_5 :: polarity [06:06] */
-#define BCHP_EBI_CS_CONFIG_5_polarity_MASK 0x00000040
-#define BCHP_EBI_CS_CONFIG_5_polarity_SHIFT 6
-#define BCHP_EBI_CS_CONFIG_5_polarity_DEFAULT 0x00000000
-
-/* EBI :: CS_CONFIG_5 :: we_ctl [05:05] */
-#define BCHP_EBI_CS_CONFIG_5_we_ctl_MASK 0x00000020
-#define BCHP_EBI_CS_CONFIG_5_we_ctl_SHIFT 5
-#define BCHP_EBI_CS_CONFIG_5_we_ctl_DEFAULT 0x00000000
-
-/* EBI :: CS_CONFIG_5 :: dest_size [04:04] */
-#define BCHP_EBI_CS_CONFIG_5_dest_size_MASK 0x00000010
-#define BCHP_EBI_CS_CONFIG_5_dest_size_SHIFT 4
-#define BCHP_EBI_CS_CONFIG_5_dest_size_DEFAULT 0x00000000
-
-/* EBI :: CS_CONFIG_5 :: ms_inh [03:03] */
-#define BCHP_EBI_CS_CONFIG_5_ms_inh_MASK 0x00000008
-#define BCHP_EBI_CS_CONFIG_5_ms_inh_SHIFT 3
-#define BCHP_EBI_CS_CONFIG_5_ms_inh_DEFAULT 0x00000000
-
-/* EBI :: CS_CONFIG_5 :: ls_inh [02:02] */
-#define BCHP_EBI_CS_CONFIG_5_ls_inh_MASK 0x00000004
-#define BCHP_EBI_CS_CONFIG_5_ls_inh_SHIFT 2
-#define BCHP_EBI_CS_CONFIG_5_ls_inh_DEFAULT 0x00000000
-
-/* EBI :: CS_CONFIG_5 :: bcachen [01:01] */
-#define BCHP_EBI_CS_CONFIG_5_bcachen_MASK 0x00000002
-#define BCHP_EBI_CS_CONFIG_5_bcachen_SHIFT 1
-#define BCHP_EBI_CS_CONFIG_5_bcachen_DEFAULT 0x00000000
-
-/* EBI :: CS_CONFIG_5 :: enable [00:00] */
-#define BCHP_EBI_CS_CONFIG_5_enable_MASK 0x00000001
-#define BCHP_EBI_CS_CONFIG_5_enable_SHIFT 0
-#define BCHP_EBI_CS_CONFIG_5_enable_DEFAULT 0x00000000
-
-/***************************************************************************
- *CS_BASE_HI_6 - Upper 8-bit of EBI CS Base 6 Register
- ***************************************************************************/
-/* EBI :: CS_BASE_HI_6 :: reserved0 [31:08] */
-#define BCHP_EBI_CS_BASE_HI_6_reserved0_MASK 0xffffff00
-#define BCHP_EBI_CS_BASE_HI_6_reserved0_SHIFT 8
-
-/* EBI :: CS_BASE_HI_6 :: base_addr_hi [07:00] */
-#define BCHP_EBI_CS_BASE_HI_6_base_addr_hi_MASK 0x000000ff
-#define BCHP_EBI_CS_BASE_HI_6_base_addr_hi_SHIFT 0
-#define BCHP_EBI_CS_BASE_HI_6_base_addr_hi_DEFAULT 0x00000000
-
-/***************************************************************************
- *CS_BASE_6 - Lower 32-bit of EBI CS Base 6 Register
- ***************************************************************************/
-/* EBI :: CS_BASE_6 :: base_addr [31:13] */
-#define BCHP_EBI_CS_BASE_6_base_addr_MASK 0xffffe000
-#define BCHP_EBI_CS_BASE_6_base_addr_SHIFT 13
-#define BCHP_EBI_CS_BASE_6_base_addr_DEFAULT 0x00000000
-
-/* EBI :: CS_BASE_6 :: reserved0 [12:04] */
-#define BCHP_EBI_CS_BASE_6_reserved0_MASK 0x00001ff0
-#define BCHP_EBI_CS_BASE_6_reserved0_SHIFT 4
-
-/* EBI :: CS_BASE_6 :: size [03:00] */
-#define BCHP_EBI_CS_BASE_6_size_MASK 0x0000000f
-#define BCHP_EBI_CS_BASE_6_size_SHIFT 0
-#define BCHP_EBI_CS_BASE_6_size_DEFAULT 0x00000000
-#define BCHP_EBI_CS_BASE_6_size_SIZE_8KB 0
-#define BCHP_EBI_CS_BASE_6_size_SIZE_16KB 1
-#define BCHP_EBI_CS_BASE_6_size_SIZE_32KB 2
-#define BCHP_EBI_CS_BASE_6_size_SIZE_64KB 3
-#define BCHP_EBI_CS_BASE_6_size_SIZE_128KB 4
-#define BCHP_EBI_CS_BASE_6_size_SIZE_256KB 5
-#define BCHP_EBI_CS_BASE_6_size_SIZE_512KB 6
-#define BCHP_EBI_CS_BASE_6_size_SIZE_1MB 7
-#define BCHP_EBI_CS_BASE_6_size_SIZE_2MB 8
-#define BCHP_EBI_CS_BASE_6_size_SIZE_4MB 9
-#define BCHP_EBI_CS_BASE_6_size_SIZE_8MB 10
-#define BCHP_EBI_CS_BASE_6_size_SIZE_16MB 11
-#define BCHP_EBI_CS_BASE_6_size_SIZE_32MB 12
-#define BCHP_EBI_CS_BASE_6_size_SIZE_64MB 13
-#define BCHP_EBI_CS_BASE_6_size_SIZE_128MB 14
-#define BCHP_EBI_CS_BASE_6_size_SIZE_256MB 15
-
-/***************************************************************************
- *CS_CONFIG_6 - EBI CS Config 6 Register
- ***************************************************************************/
-/* EBI :: CS_CONFIG_6 :: mem_io [31:31] */
-#define BCHP_EBI_CS_CONFIG_6_mem_io_MASK 0x80000000
-#define BCHP_EBI_CS_CONFIG_6_mem_io_SHIFT 31
-#define BCHP_EBI_CS_CONFIG_6_mem_io_DEFAULT 0x00000000
-
-/* EBI :: CS_CONFIG_6 :: ta_wait [30:30] */
-#define BCHP_EBI_CS_CONFIG_6_ta_wait_MASK 0x40000000
-#define BCHP_EBI_CS_CONFIG_6_ta_wait_SHIFT 30
-#define BCHP_EBI_CS_CONFIG_6_ta_wait_DEFAULT 0x00000000
-
-/* EBI :: CS_CONFIG_6 :: wp [29:29] */
-#define BCHP_EBI_CS_CONFIG_6_wp_MASK 0x20000000
-#define BCHP_EBI_CS_CONFIG_6_wp_SHIFT 29
-#define BCHP_EBI_CS_CONFIG_6_wp_DEFAULT 0x00000000
-
-/* EBI :: CS_CONFIG_6 :: wait_count [28:24] */
-#define BCHP_EBI_CS_CONFIG_6_wait_count_MASK 0x1f000000
-#define BCHP_EBI_CS_CONFIG_6_wait_count_SHIFT 24
-#define BCHP_EBI_CS_CONFIG_6_wait_count_DEFAULT 0x00000007
-
-/* EBI :: CS_CONFIG_6 :: t_hold [23:20] */
-#define BCHP_EBI_CS_CONFIG_6_t_hold_MASK 0x00f00000
-#define BCHP_EBI_CS_CONFIG_6_t_hold_SHIFT 20
-#define BCHP_EBI_CS_CONFIG_6_t_hold_DEFAULT 0x00000000
-
-/* EBI :: CS_CONFIG_6 :: t_setup [19:16] */
-#define BCHP_EBI_CS_CONFIG_6_t_setup_MASK 0x000f0000
-#define BCHP_EBI_CS_CONFIG_6_t_setup_SHIFT 16
-#define BCHP_EBI_CS_CONFIG_6_t_setup_DEFAULT 0x00000000
-
-/* EBI :: CS_CONFIG_6 :: cs_hold [15:15] */
-#define BCHP_EBI_CS_CONFIG_6_cs_hold_MASK 0x00008000
-#define BCHP_EBI_CS_CONFIG_6_cs_hold_SHIFT 15
-#define BCHP_EBI_CS_CONFIG_6_cs_hold_DEFAULT 0x00000000
-
-/* EBI :: CS_CONFIG_6 :: split_cs [14:14] */
-#define BCHP_EBI_CS_CONFIG_6_split_cs_MASK 0x00004000
-#define BCHP_EBI_CS_CONFIG_6_split_cs_SHIFT 14
-#define BCHP_EBI_CS_CONFIG_6_split_cs_DEFAULT 0x00000000
-
-/* EBI :: CS_CONFIG_6 :: mask_en [13:13] */
-#define BCHP_EBI_CS_CONFIG_6_mask_en_MASK 0x00002000
-#define BCHP_EBI_CS_CONFIG_6_mask_en_SHIFT 13
-#define BCHP_EBI_CS_CONFIG_6_mask_en_DEFAULT 0x00000000
-
-/* EBI :: CS_CONFIG_6 :: ne_sample [12:12] */
-#define BCHP_EBI_CS_CONFIG_6_ne_sample_MASK 0x00001000
-#define BCHP_EBI_CS_CONFIG_6_ne_sample_SHIFT 12
-#define BCHP_EBI_CS_CONFIG_6_ne_sample_DEFAULT 0x00000000
-
-/* EBI :: CS_CONFIG_6 :: m68k [11:11] */
-#define BCHP_EBI_CS_CONFIG_6_m68k_MASK 0x00000800
-#define BCHP_EBI_CS_CONFIG_6_m68k_SHIFT 11
-#define BCHP_EBI_CS_CONFIG_6_m68k_DEFAULT 0x00000000
-
-/* EBI :: CS_CONFIG_6 :: le [10:10] */
-#define BCHP_EBI_CS_CONFIG_6_le_MASK 0x00000400
-#define BCHP_EBI_CS_CONFIG_6_le_SHIFT 10
-#define BCHP_EBI_CS_CONFIG_6_le_DEFAULT 0x00000000
-
-/* EBI :: CS_CONFIG_6 :: fast_read [09:09] */
-#define BCHP_EBI_CS_CONFIG_6_fast_read_MASK 0x00000200
-#define BCHP_EBI_CS_CONFIG_6_fast_read_SHIFT 9
-#define BCHP_EBI_CS_CONFIG_6_fast_read_DEFAULT 0x00000000
-#define BCHP_EBI_CS_CONFIG_6_fast_read_Normal 0
-#define BCHP_EBI_CS_CONFIG_6_fast_read_Fast_Read_Enable 1
-
-/* EBI :: CS_CONFIG_6 :: size_sel [08:08] */
-#define BCHP_EBI_CS_CONFIG_6_size_sel_MASK 0x00000100
-#define BCHP_EBI_CS_CONFIG_6_size_sel_SHIFT 8
-#define BCHP_EBI_CS_CONFIG_6_size_sel_DEFAULT 0x00000000
-
-/* EBI :: CS_CONFIG_6 :: sync [07:07] */
-#define BCHP_EBI_CS_CONFIG_6_sync_MASK 0x00000080
-#define BCHP_EBI_CS_CONFIG_6_sync_SHIFT 7
-#define BCHP_EBI_CS_CONFIG_6_sync_DEFAULT 0x00000000
-
-/* EBI :: CS_CONFIG_6 :: polarity [06:06] */
-#define BCHP_EBI_CS_CONFIG_6_polarity_MASK 0x00000040
-#define BCHP_EBI_CS_CONFIG_6_polarity_SHIFT 6
-#define BCHP_EBI_CS_CONFIG_6_polarity_DEFAULT 0x00000000
-
-/* EBI :: CS_CONFIG_6 :: we_ctl [05:05] */
-#define BCHP_EBI_CS_CONFIG_6_we_ctl_MASK 0x00000020
-#define BCHP_EBI_CS_CONFIG_6_we_ctl_SHIFT 5
-#define BCHP_EBI_CS_CONFIG_6_we_ctl_DEFAULT 0x00000000
-
-/* EBI :: CS_CONFIG_6 :: dest_size [04:04] */
-#define BCHP_EBI_CS_CONFIG_6_dest_size_MASK 0x00000010
-#define BCHP_EBI_CS_CONFIG_6_dest_size_SHIFT 4
-#define BCHP_EBI_CS_CONFIG_6_dest_size_DEFAULT 0x00000000
-
-/* EBI :: CS_CONFIG_6 :: ms_inh [03:03] */
-#define BCHP_EBI_CS_CONFIG_6_ms_inh_MASK 0x00000008
-#define BCHP_EBI_CS_CONFIG_6_ms_inh_SHIFT 3
-#define BCHP_EBI_CS_CONFIG_6_ms_inh_DEFAULT 0x00000000
-
-/* EBI :: CS_CONFIG_6 :: ls_inh [02:02] */
-#define BCHP_EBI_CS_CONFIG_6_ls_inh_MASK 0x00000004
-#define BCHP_EBI_CS_CONFIG_6_ls_inh_SHIFT 2
-#define BCHP_EBI_CS_CONFIG_6_ls_inh_DEFAULT 0x00000000
-
-/* EBI :: CS_CONFIG_6 :: bcachen [01:01] */
-#define BCHP_EBI_CS_CONFIG_6_bcachen_MASK 0x00000002
-#define BCHP_EBI_CS_CONFIG_6_bcachen_SHIFT 1
-#define BCHP_EBI_CS_CONFIG_6_bcachen_DEFAULT 0x00000000
-
-/* EBI :: CS_CONFIG_6 :: enable [00:00] */
-#define BCHP_EBI_CS_CONFIG_6_enable_MASK 0x00000001
-#define BCHP_EBI_CS_CONFIG_6_enable_SHIFT 0
-#define BCHP_EBI_CS_CONFIG_6_enable_DEFAULT 0x00000000
-
-/***************************************************************************
- *BURST_CFG_0 - EBI Synchronous Intel StrataFlash Burst Configure Register
- ***************************************************************************/
-/* EBI :: BURST_CFG_0 :: prefetch_enable [31:31] */
-#define BCHP_EBI_BURST_CFG_0_prefetch_enable_MASK 0x80000000
-#define BCHP_EBI_BURST_CFG_0_prefetch_enable_SHIFT 31
-#define BCHP_EBI_BURST_CFG_0_prefetch_enable_DEFAULT 0x00000000
-
-/* EBI :: BURST_CFG_0 :: page_enable [30:30] */
-#define BCHP_EBI_BURST_CFG_0_page_enable_MASK 0x40000000
-#define BCHP_EBI_BURST_CFG_0_page_enable_SHIFT 30
-#define BCHP_EBI_BURST_CFG_0_page_enable_DEFAULT 0x00000000
-
-/* EBI :: BURST_CFG_0 :: pfetch_abort_enable [29:29] */
-#define BCHP_EBI_BURST_CFG_0_pfetch_abort_enable_MASK 0x20000000
-#define BCHP_EBI_BURST_CFG_0_pfetch_abort_enable_SHIFT 29
-#define BCHP_EBI_BURST_CFG_0_pfetch_abort_enable_DEFAULT 0x00000000
-
-/* EBI :: BURST_CFG_0 :: page_latch_enable [28:28] */
-#define BCHP_EBI_BURST_CFG_0_page_latch_enable_MASK 0x10000000
-#define BCHP_EBI_BURST_CFG_0_page_latch_enable_SHIFT 28
-#define BCHP_EBI_BURST_CFG_0_page_latch_enable_DEFAULT 0x00000000
-
-/* EBI :: BURST_CFG_0 :: pfetch_wrap_enable [27:27] */
-#define BCHP_EBI_BURST_CFG_0_pfetch_wrap_enable_MASK 0x08000000
-#define BCHP_EBI_BURST_CFG_0_pfetch_wrap_enable_SHIFT 27
-#define BCHP_EBI_BURST_CFG_0_pfetch_wrap_enable_DEFAULT 0x00000000
-
-/* EBI :: BURST_CFG_0 :: reserved0 [26:24] */
-#define BCHP_EBI_BURST_CFG_0_reserved0_MASK 0x07000000
-#define BCHP_EBI_BURST_CFG_0_reserved0_SHIFT 24
-
-/* EBI :: BURST_CFG_0 :: prefetch_size [23:22] */
-#define BCHP_EBI_BURST_CFG_0_prefetch_size_MASK 0x00c00000
-#define BCHP_EBI_BURST_CFG_0_prefetch_size_SHIFT 22
-#define BCHP_EBI_BURST_CFG_0_prefetch_size_DEFAULT 0x00000000
-#define BCHP_EBI_BURST_CFG_0_prefetch_size_SIZE_4_BYTES 0
-#define BCHP_EBI_BURST_CFG_0_prefetch_size_SIZE_8_BYTES 1
-#define BCHP_EBI_BURST_CFG_0_prefetch_size_SIZE_16_BYTES 2
-#define BCHP_EBI_BURST_CFG_0_prefetch_size_SIZE_32_BYTES 3
-
-/* EBI :: BURST_CFG_0 :: page_size [21:20] */
-#define BCHP_EBI_BURST_CFG_0_page_size_MASK 0x00300000
-#define BCHP_EBI_BURST_CFG_0_page_size_SHIFT 20
-#define BCHP_EBI_BURST_CFG_0_page_size_DEFAULT 0x00000000
-#define BCHP_EBI_BURST_CFG_0_page_size_SIZE_4_BYTES 0
-#define BCHP_EBI_BURST_CFG_0_page_size_SIZE_8_BYTES 1
-#define BCHP_EBI_BURST_CFG_0_page_size_SIZE_16_BYTES 2
-#define BCHP_EBI_BURST_CFG_0_page_size_SIZE_32_BYTES 3
-
-/* EBI :: BURST_CFG_0 :: page_wait_count [19:16] */
-#define BCHP_EBI_BURST_CFG_0_page_wait_count_MASK 0x000f0000
-#define BCHP_EBI_BURST_CFG_0_page_wait_count_SHIFT 16
-#define BCHP_EBI_BURST_CFG_0_page_wait_count_DEFAULT 0x00000001
-
-/* EBI :: BURST_CFG_0 :: burst_cyc_disable [15:15] */
-#define BCHP_EBI_BURST_CFG_0_burst_cyc_disable_MASK 0x00008000
-#define BCHP_EBI_BURST_CFG_0_burst_cyc_disable_SHIFT 15
-#define BCHP_EBI_BURST_CFG_0_burst_cyc_disable_DEFAULT 0x00000001
-
-/* EBI :: BURST_CFG_0 :: reserved1 [14:08] */
-#define BCHP_EBI_BURST_CFG_0_reserved1_MASK 0x00007f00
-#define BCHP_EBI_BURST_CFG_0_reserved1_SHIFT 8
-
-/* EBI :: BURST_CFG_0 :: burst_latency [07:04] */
-#define BCHP_EBI_BURST_CFG_0_burst_latency_MASK 0x000000f0
-#define BCHP_EBI_BURST_CFG_0_burst_latency_SHIFT 4
-#define BCHP_EBI_BURST_CFG_0_burst_latency_DEFAULT 0x00000000
-
-/* EBI :: BURST_CFG_0 :: reserved2 [03:02] */
-#define BCHP_EBI_BURST_CFG_0_reserved2_MASK 0x0000000c
-#define BCHP_EBI_BURST_CFG_0_reserved2_SHIFT 2
-
-/* EBI :: BURST_CFG_0 :: data_hold [01:01] */
-#define BCHP_EBI_BURST_CFG_0_data_hold_MASK 0x00000002
-#define BCHP_EBI_BURST_CFG_0_data_hold_SHIFT 1
-#define BCHP_EBI_BURST_CFG_0_data_hold_DEFAULT 0x00000000
-
-/* EBI :: BURST_CFG_0 :: burst_16 [00:00] */
-#define BCHP_EBI_BURST_CFG_0_burst_16_MASK 0x00000001
-#define BCHP_EBI_BURST_CFG_0_burst_16_SHIFT 0
-#define BCHP_EBI_BURST_CFG_0_burst_16_DEFAULT 0x00000000
-
-/***************************************************************************
- *BURST_CFG_1 - EBI Synchronous Intel StrataFlash Burst Configure Register
- ***************************************************************************/
-/* EBI :: BURST_CFG_1 :: prefetch_enable [31:31] */
-#define BCHP_EBI_BURST_CFG_1_prefetch_enable_MASK 0x80000000
-#define BCHP_EBI_BURST_CFG_1_prefetch_enable_SHIFT 31
-#define BCHP_EBI_BURST_CFG_1_prefetch_enable_DEFAULT 0x00000000
-
-/* EBI :: BURST_CFG_1 :: page_enable [30:30] */
-#define BCHP_EBI_BURST_CFG_1_page_enable_MASK 0x40000000
-#define BCHP_EBI_BURST_CFG_1_page_enable_SHIFT 30
-#define BCHP_EBI_BURST_CFG_1_page_enable_DEFAULT 0x00000000
-
-/* EBI :: BURST_CFG_1 :: pfetch_abort_enable [29:29] */
-#define BCHP_EBI_BURST_CFG_1_pfetch_abort_enable_MASK 0x20000000
-#define BCHP_EBI_BURST_CFG_1_pfetch_abort_enable_SHIFT 29
-#define BCHP_EBI_BURST_CFG_1_pfetch_abort_enable_DEFAULT 0x00000000
-
-/* EBI :: BURST_CFG_1 :: page_latch_enable [28:28] */
-#define BCHP_EBI_BURST_CFG_1_page_latch_enable_MASK 0x10000000
-#define BCHP_EBI_BURST_CFG_1_page_latch_enable_SHIFT 28
-#define BCHP_EBI_BURST_CFG_1_page_latch_enable_DEFAULT 0x00000000
-
-/* EBI :: BURST_CFG_1 :: pfetch_wrap_enable [27:27] */
-#define BCHP_EBI_BURST_CFG_1_pfetch_wrap_enable_MASK 0x08000000
-#define BCHP_EBI_BURST_CFG_1_pfetch_wrap_enable_SHIFT 27
-#define BCHP_EBI_BURST_CFG_1_pfetch_wrap_enable_DEFAULT 0x00000000
-
-/* EBI :: BURST_CFG_1 :: reserved0 [26:24] */
-#define BCHP_EBI_BURST_CFG_1_reserved0_MASK 0x07000000
-#define BCHP_EBI_BURST_CFG_1_reserved0_SHIFT 24
-
-/* EBI :: BURST_CFG_1 :: prefetch_size [23:22] */
-#define BCHP_EBI_BURST_CFG_1_prefetch_size_MASK 0x00c00000
-#define BCHP_EBI_BURST_CFG_1_prefetch_size_SHIFT 22
-#define BCHP_EBI_BURST_CFG_1_prefetch_size_DEFAULT 0x00000000
-#define BCHP_EBI_BURST_CFG_1_prefetch_size_SIZE_4_BYTES 0
-#define BCHP_EBI_BURST_CFG_1_prefetch_size_SIZE_8_BYTES 1
-#define BCHP_EBI_BURST_CFG_1_prefetch_size_SIZE_16_BYTES 2
-#define BCHP_EBI_BURST_CFG_1_prefetch_size_SIZE_32_BYTES 3
-
-/* EBI :: BURST_CFG_1 :: page_size [21:20] */
-#define BCHP_EBI_BURST_CFG_1_page_size_MASK 0x00300000
-#define BCHP_EBI_BURST_CFG_1_page_size_SHIFT 20
-#define BCHP_EBI_BURST_CFG_1_page_size_DEFAULT 0x00000000
-#define BCHP_EBI_BURST_CFG_1_page_size_SIZE_4_BYTES 0
-#define BCHP_EBI_BURST_CFG_1_page_size_SIZE_8_BYTES 1
-#define BCHP_EBI_BURST_CFG_1_page_size_SIZE_16_BYTES 2
-#define BCHP_EBI_BURST_CFG_1_page_size_SIZE_32_BYTES 3
-
-/* EBI :: BURST_CFG_1 :: page_wait_count [19:16] */
-#define BCHP_EBI_BURST_CFG_1_page_wait_count_MASK 0x000f0000
-#define BCHP_EBI_BURST_CFG_1_page_wait_count_SHIFT 16
-#define BCHP_EBI_BURST_CFG_1_page_wait_count_DEFAULT 0x00000001
-
-/* EBI :: BURST_CFG_1 :: burst_cyc_disable [15:15] */
-#define BCHP_EBI_BURST_CFG_1_burst_cyc_disable_MASK 0x00008000
-#define BCHP_EBI_BURST_CFG_1_burst_cyc_disable_SHIFT 15
-#define BCHP_EBI_BURST_CFG_1_burst_cyc_disable_DEFAULT 0x00000001
-
-/* EBI :: BURST_CFG_1 :: reserved1 [14:08] */
-#define BCHP_EBI_BURST_CFG_1_reserved1_MASK 0x00007f00
-#define BCHP_EBI_BURST_CFG_1_reserved1_SHIFT 8
-
-/* EBI :: BURST_CFG_1 :: burst_latency [07:04] */
-#define BCHP_EBI_BURST_CFG_1_burst_latency_MASK 0x000000f0
-#define BCHP_EBI_BURST_CFG_1_burst_latency_SHIFT 4
-#define BCHP_EBI_BURST_CFG_1_burst_latency_DEFAULT 0x00000000
-
-/* EBI :: BURST_CFG_1 :: reserved2 [03:02] */
-#define BCHP_EBI_BURST_CFG_1_reserved2_MASK 0x0000000c
-#define BCHP_EBI_BURST_CFG_1_reserved2_SHIFT 2
-
-/* EBI :: BURST_CFG_1 :: data_hold [01:01] */
-#define BCHP_EBI_BURST_CFG_1_data_hold_MASK 0x00000002
-#define BCHP_EBI_BURST_CFG_1_data_hold_SHIFT 1
-#define BCHP_EBI_BURST_CFG_1_data_hold_DEFAULT 0x00000000
-
-/* EBI :: BURST_CFG_1 :: burst_16 [00:00] */
-#define BCHP_EBI_BURST_CFG_1_burst_16_MASK 0x00000001
-#define BCHP_EBI_BURST_CFG_1_burst_16_SHIFT 0
-#define BCHP_EBI_BURST_CFG_1_burst_16_DEFAULT 0x00000000
-
-/***************************************************************************
- *BURST_CFG_2 - EBI Synchronous Intel StrataFlash Burst Configure Register
- ***************************************************************************/
-/* EBI :: BURST_CFG_2 :: prefetch_enable [31:31] */
-#define BCHP_EBI_BURST_CFG_2_prefetch_enable_MASK 0x80000000
-#define BCHP_EBI_BURST_CFG_2_prefetch_enable_SHIFT 31
-#define BCHP_EBI_BURST_CFG_2_prefetch_enable_DEFAULT 0x00000000
-
-/* EBI :: BURST_CFG_2 :: page_enable [30:30] */
-#define BCHP_EBI_BURST_CFG_2_page_enable_MASK 0x40000000
-#define BCHP_EBI_BURST_CFG_2_page_enable_SHIFT 30
-#define BCHP_EBI_BURST_CFG_2_page_enable_DEFAULT 0x00000000
-
-/* EBI :: BURST_CFG_2 :: pfetch_abort_enable [29:29] */
-#define BCHP_EBI_BURST_CFG_2_pfetch_abort_enable_MASK 0x20000000
-#define BCHP_EBI_BURST_CFG_2_pfetch_abort_enable_SHIFT 29
-#define BCHP_EBI_BURST_CFG_2_pfetch_abort_enable_DEFAULT 0x00000000
-
-/* EBI :: BURST_CFG_2 :: page_latch_enable [28:28] */
-#define BCHP_EBI_BURST_CFG_2_page_latch_enable_MASK 0x10000000
-#define BCHP_EBI_BURST_CFG_2_page_latch_enable_SHIFT 28
-#define BCHP_EBI_BURST_CFG_2_page_latch_enable_DEFAULT 0x00000000
-
-/* EBI :: BURST_CFG_2 :: pfetch_wrap_enable [27:27] */
-#define BCHP_EBI_BURST_CFG_2_pfetch_wrap_enable_MASK 0x08000000
-#define BCHP_EBI_BURST_CFG_2_pfetch_wrap_enable_SHIFT 27
-#define BCHP_EBI_BURST_CFG_2_pfetch_wrap_enable_DEFAULT 0x00000000
-
-/* EBI :: BURST_CFG_2 :: reserved0 [26:24] */
-#define BCHP_EBI_BURST_CFG_2_reserved0_MASK 0x07000000
-#define BCHP_EBI_BURST_CFG_2_reserved0_SHIFT 24
-
-/* EBI :: BURST_CFG_2 :: prefetch_size [23:22] */
-#define BCHP_EBI_BURST_CFG_2_prefetch_size_MASK 0x00c00000
-#define BCHP_EBI_BURST_CFG_2_prefetch_size_SHIFT 22
-#define BCHP_EBI_BURST_CFG_2_prefetch_size_DEFAULT 0x00000000
-#define BCHP_EBI_BURST_CFG_2_prefetch_size_SIZE_4_BYTES 0
-#define BCHP_EBI_BURST_CFG_2_prefetch_size_SIZE_8_BYTES 1
-#define BCHP_EBI_BURST_CFG_2_prefetch_size_SIZE_16_BYTES 2
-#define BCHP_EBI_BURST_CFG_2_prefetch_size_SIZE_32_BYTES 3
-
-/* EBI :: BURST_CFG_2 :: page_size [21:20] */
-#define BCHP_EBI_BURST_CFG_2_page_size_MASK 0x00300000
-#define BCHP_EBI_BURST_CFG_2_page_size_SHIFT 20
-#define BCHP_EBI_BURST_CFG_2_page_size_DEFAULT 0x00000000
-#define BCHP_EBI_BURST_CFG_2_page_size_SIZE_4_BYTES 0
-#define BCHP_EBI_BURST_CFG_2_page_size_SIZE_8_BYTES 1
-#define BCHP_EBI_BURST_CFG_2_page_size_SIZE_16_BYTES 2
-#define BCHP_EBI_BURST_CFG_2_page_size_SIZE_32_BYTES 3
-
-/* EBI :: BURST_CFG_2 :: page_wait_count [19:16] */
-#define BCHP_EBI_BURST_CFG_2_page_wait_count_MASK 0x000f0000
-#define BCHP_EBI_BURST_CFG_2_page_wait_count_SHIFT 16
-#define BCHP_EBI_BURST_CFG_2_page_wait_count_DEFAULT 0x00000001
-
-/* EBI :: BURST_CFG_2 :: burst_cyc_disable [15:15] */
-#define BCHP_EBI_BURST_CFG_2_burst_cyc_disable_MASK 0x00008000
-#define BCHP_EBI_BURST_CFG_2_burst_cyc_disable_SHIFT 15
-#define BCHP_EBI_BURST_CFG_2_burst_cyc_disable_DEFAULT 0x00000001
-
-/* EBI :: BURST_CFG_2 :: reserved1 [14:08] */
-#define BCHP_EBI_BURST_CFG_2_reserved1_MASK 0x00007f00
-#define BCHP_EBI_BURST_CFG_2_reserved1_SHIFT 8
-
-/* EBI :: BURST_CFG_2 :: burst_latency [07:04] */
-#define BCHP_EBI_BURST_CFG_2_burst_latency_MASK 0x000000f0
-#define BCHP_EBI_BURST_CFG_2_burst_latency_SHIFT 4
-#define BCHP_EBI_BURST_CFG_2_burst_latency_DEFAULT 0x00000000
-
-/* EBI :: BURST_CFG_2 :: reserved2 [03:02] */
-#define BCHP_EBI_BURST_CFG_2_reserved2_MASK 0x0000000c
-#define BCHP_EBI_BURST_CFG_2_reserved2_SHIFT 2
-
-/* EBI :: BURST_CFG_2 :: data_hold [01:01] */
-#define BCHP_EBI_BURST_CFG_2_data_hold_MASK 0x00000002
-#define BCHP_EBI_BURST_CFG_2_data_hold_SHIFT 1
-#define BCHP_EBI_BURST_CFG_2_data_hold_DEFAULT 0x00000000
-
-/* EBI :: BURST_CFG_2 :: burst_16 [00:00] */
-#define BCHP_EBI_BURST_CFG_2_burst_16_MASK 0x00000001
-#define BCHP_EBI_BURST_CFG_2_burst_16_SHIFT 0
-#define BCHP_EBI_BURST_CFG_2_burst_16_DEFAULT 0x00000000
-
-/***************************************************************************
- *BURST_CFG_3 - EBI Synchronous Intel StrataFlash Burst Configure Register
- ***************************************************************************/
-/* EBI :: BURST_CFG_3 :: prefetch_enable [31:31] */
-#define BCHP_EBI_BURST_CFG_3_prefetch_enable_MASK 0x80000000
-#define BCHP_EBI_BURST_CFG_3_prefetch_enable_SHIFT 31
-#define BCHP_EBI_BURST_CFG_3_prefetch_enable_DEFAULT 0x00000000
-
-/* EBI :: BURST_CFG_3 :: page_enable [30:30] */
-#define BCHP_EBI_BURST_CFG_3_page_enable_MASK 0x40000000
-#define BCHP_EBI_BURST_CFG_3_page_enable_SHIFT 30
-#define BCHP_EBI_BURST_CFG_3_page_enable_DEFAULT 0x00000000
-
-/* EBI :: BURST_CFG_3 :: pfetch_abort_enable [29:29] */
-#define BCHP_EBI_BURST_CFG_3_pfetch_abort_enable_MASK 0x20000000
-#define BCHP_EBI_BURST_CFG_3_pfetch_abort_enable_SHIFT 29
-#define BCHP_EBI_BURST_CFG_3_pfetch_abort_enable_DEFAULT 0x00000000
-
-/* EBI :: BURST_CFG_3 :: page_latch_enable [28:28] */
-#define BCHP_EBI_BURST_CFG_3_page_latch_enable_MASK 0x10000000
-#define BCHP_EBI_BURST_CFG_3_page_latch_enable_SHIFT 28
-#define BCHP_EBI_BURST_CFG_3_page_latch_enable_DEFAULT 0x00000000
-
-/* EBI :: BURST_CFG_3 :: pfetch_wrap_enable [27:27] */
-#define BCHP_EBI_BURST_CFG_3_pfetch_wrap_enable_MASK 0x08000000
-#define BCHP_EBI_BURST_CFG_3_pfetch_wrap_enable_SHIFT 27
-#define BCHP_EBI_BURST_CFG_3_pfetch_wrap_enable_DEFAULT 0x00000000
-
-/* EBI :: BURST_CFG_3 :: reserved0 [26:24] */
-#define BCHP_EBI_BURST_CFG_3_reserved0_MASK 0x07000000
-#define BCHP_EBI_BURST_CFG_3_reserved0_SHIFT 24
-
-/* EBI :: BURST_CFG_3 :: prefetch_size [23:22] */
-#define BCHP_EBI_BURST_CFG_3_prefetch_size_MASK 0x00c00000
-#define BCHP_EBI_BURST_CFG_3_prefetch_size_SHIFT 22
-#define BCHP_EBI_BURST_CFG_3_prefetch_size_DEFAULT 0x00000000
-#define BCHP_EBI_BURST_CFG_3_prefetch_size_SIZE_4_BYTES 0
-#define BCHP_EBI_BURST_CFG_3_prefetch_size_SIZE_8_BYTES 1
-#define BCHP_EBI_BURST_CFG_3_prefetch_size_SIZE_16_BYTES 2
-#define BCHP_EBI_BURST_CFG_3_prefetch_size_SIZE_32_BYTES 3
-
-/* EBI :: BURST_CFG_3 :: page_size [21:20] */
-#define BCHP_EBI_BURST_CFG_3_page_size_MASK 0x00300000
-#define BCHP_EBI_BURST_CFG_3_page_size_SHIFT 20
-#define BCHP_EBI_BURST_CFG_3_page_size_DEFAULT 0x00000000
-#define BCHP_EBI_BURST_CFG_3_page_size_SIZE_4_BYTES 0
-#define BCHP_EBI_BURST_CFG_3_page_size_SIZE_8_BYTES 1
-#define BCHP_EBI_BURST_CFG_3_page_size_SIZE_16_BYTES 2
-#define BCHP_EBI_BURST_CFG_3_page_size_SIZE_32_BYTES 3
-
-/* EBI :: BURST_CFG_3 :: page_wait_count [19:16] */
-#define BCHP_EBI_BURST_CFG_3_page_wait_count_MASK 0x000f0000
-#define BCHP_EBI_BURST_CFG_3_page_wait_count_SHIFT 16
-#define BCHP_EBI_BURST_CFG_3_page_wait_count_DEFAULT 0x00000001
-
-/* EBI :: BURST_CFG_3 :: burst_cyc_disable [15:15] */
-#define BCHP_EBI_BURST_CFG_3_burst_cyc_disable_MASK 0x00008000
-#define BCHP_EBI_BURST_CFG_3_burst_cyc_disable_SHIFT 15
-#define BCHP_EBI_BURST_CFG_3_burst_cyc_disable_DEFAULT 0x00000001
-
-/* EBI :: BURST_CFG_3 :: reserved1 [14:08] */
-#define BCHP_EBI_BURST_CFG_3_reserved1_MASK 0x00007f00
-#define BCHP_EBI_BURST_CFG_3_reserved1_SHIFT 8
-
-/* EBI :: BURST_CFG_3 :: burst_latency [07:04] */
-#define BCHP_EBI_BURST_CFG_3_burst_latency_MASK 0x000000f0
-#define BCHP_EBI_BURST_CFG_3_burst_latency_SHIFT 4
-#define BCHP_EBI_BURST_CFG_3_burst_latency_DEFAULT 0x00000000
-
-/* EBI :: BURST_CFG_3 :: reserved2 [03:02] */
-#define BCHP_EBI_BURST_CFG_3_reserved2_MASK 0x0000000c
-#define BCHP_EBI_BURST_CFG_3_reserved2_SHIFT 2
-
-/* EBI :: BURST_CFG_3 :: data_hold [01:01] */
-#define BCHP_EBI_BURST_CFG_3_data_hold_MASK 0x00000002
-#define BCHP_EBI_BURST_CFG_3_data_hold_SHIFT 1
-#define BCHP_EBI_BURST_CFG_3_data_hold_DEFAULT 0x00000000
-
-/* EBI :: BURST_CFG_3 :: burst_16 [00:00] */
-#define BCHP_EBI_BURST_CFG_3_burst_16_MASK 0x00000001
-#define BCHP_EBI_BURST_CFG_3_burst_16_SHIFT 0
-#define BCHP_EBI_BURST_CFG_3_burst_16_DEFAULT 0x00000000
-
-/***************************************************************************
- *BURST_CFG_4 - EBI Synchronous Intel StrataFlash Burst Configure Register
- ***************************************************************************/
-/* EBI :: BURST_CFG_4 :: prefetch_enable [31:31] */
-#define BCHP_EBI_BURST_CFG_4_prefetch_enable_MASK 0x80000000
-#define BCHP_EBI_BURST_CFG_4_prefetch_enable_SHIFT 31
-#define BCHP_EBI_BURST_CFG_4_prefetch_enable_DEFAULT 0x00000000
-
-/* EBI :: BURST_CFG_4 :: page_enable [30:30] */
-#define BCHP_EBI_BURST_CFG_4_page_enable_MASK 0x40000000
-#define BCHP_EBI_BURST_CFG_4_page_enable_SHIFT 30
-#define BCHP_EBI_BURST_CFG_4_page_enable_DEFAULT 0x00000000
-
-/* EBI :: BURST_CFG_4 :: pfetch_abort_enable [29:29] */
-#define BCHP_EBI_BURST_CFG_4_pfetch_abort_enable_MASK 0x20000000
-#define BCHP_EBI_BURST_CFG_4_pfetch_abort_enable_SHIFT 29
-#define BCHP_EBI_BURST_CFG_4_pfetch_abort_enable_DEFAULT 0x00000000
-
-/* EBI :: BURST_CFG_4 :: page_latch_enable [28:28] */
-#define BCHP_EBI_BURST_CFG_4_page_latch_enable_MASK 0x10000000
-#define BCHP_EBI_BURST_CFG_4_page_latch_enable_SHIFT 28
-#define BCHP_EBI_BURST_CFG_4_page_latch_enable_DEFAULT 0x00000000
-
-/* EBI :: BURST_CFG_4 :: pfetch_wrap_enable [27:27] */
-#define BCHP_EBI_BURST_CFG_4_pfetch_wrap_enable_MASK 0x08000000
-#define BCHP_EBI_BURST_CFG_4_pfetch_wrap_enable_SHIFT 27
-#define BCHP_EBI_BURST_CFG_4_pfetch_wrap_enable_DEFAULT 0x00000000
-
-/* EBI :: BURST_CFG_4 :: reserved0 [26:24] */
-#define BCHP_EBI_BURST_CFG_4_reserved0_MASK 0x07000000
-#define BCHP_EBI_BURST_CFG_4_reserved0_SHIFT 24
-
-/* EBI :: BURST_CFG_4 :: prefetch_size [23:22] */
-#define BCHP_EBI_BURST_CFG_4_prefetch_size_MASK 0x00c00000
-#define BCHP_EBI_BURST_CFG_4_prefetch_size_SHIFT 22
-#define BCHP_EBI_BURST_CFG_4_prefetch_size_DEFAULT 0x00000000
-#define BCHP_EBI_BURST_CFG_4_prefetch_size_SIZE_4_BYTES 0
-#define BCHP_EBI_BURST_CFG_4_prefetch_size_SIZE_8_BYTES 1
-#define BCHP_EBI_BURST_CFG_4_prefetch_size_SIZE_16_BYTES 2
-#define BCHP_EBI_BURST_CFG_4_prefetch_size_SIZE_32_BYTES 3
-
-/* EBI :: BURST_CFG_4 :: page_size [21:20] */
-#define BCHP_EBI_BURST_CFG_4_page_size_MASK 0x00300000
-#define BCHP_EBI_BURST_CFG_4_page_size_SHIFT 20
-#define BCHP_EBI_BURST_CFG_4_page_size_DEFAULT 0x00000000
-#define BCHP_EBI_BURST_CFG_4_page_size_SIZE_4_BYTES 0
-#define BCHP_EBI_BURST_CFG_4_page_size_SIZE_8_BYTES 1
-#define BCHP_EBI_BURST_CFG_4_page_size_SIZE_16_BYTES 2
-#define BCHP_EBI_BURST_CFG_4_page_size_SIZE_32_BYTES 3
-
-/* EBI :: BURST_CFG_4 :: page_wait_count [19:16] */
-#define BCHP_EBI_BURST_CFG_4_page_wait_count_MASK 0x000f0000
-#define BCHP_EBI_BURST_CFG_4_page_wait_count_SHIFT 16
-#define BCHP_EBI_BURST_CFG_4_page_wait_count_DEFAULT 0x00000001
-
-/* EBI :: BURST_CFG_4 :: burst_cyc_disable [15:15] */
-#define BCHP_EBI_BURST_CFG_4_burst_cyc_disable_MASK 0x00008000
-#define BCHP_EBI_BURST_CFG_4_burst_cyc_disable_SHIFT 15
-#define BCHP_EBI_BURST_CFG_4_burst_cyc_disable_DEFAULT 0x00000001
-
-/* EBI :: BURST_CFG_4 :: reserved1 [14:08] */
-#define BCHP_EBI_BURST_CFG_4_reserved1_MASK 0x00007f00
-#define BCHP_EBI_BURST_CFG_4_reserved1_SHIFT 8
-
-/* EBI :: BURST_CFG_4 :: burst_latency [07:04] */
-#define BCHP_EBI_BURST_CFG_4_burst_latency_MASK 0x000000f0
-#define BCHP_EBI_BURST_CFG_4_burst_latency_SHIFT 4
-#define BCHP_EBI_BURST_CFG_4_burst_latency_DEFAULT 0x00000000
-
-/* EBI :: BURST_CFG_4 :: reserved2 [03:02] */
-#define BCHP_EBI_BURST_CFG_4_reserved2_MASK 0x0000000c
-#define BCHP_EBI_BURST_CFG_4_reserved2_SHIFT 2
-
-/* EBI :: BURST_CFG_4 :: data_hold [01:01] */
-#define BCHP_EBI_BURST_CFG_4_data_hold_MASK 0x00000002
-#define BCHP_EBI_BURST_CFG_4_data_hold_SHIFT 1
-#define BCHP_EBI_BURST_CFG_4_data_hold_DEFAULT 0x00000000
-
-/* EBI :: BURST_CFG_4 :: burst_16 [00:00] */
-#define BCHP_EBI_BURST_CFG_4_burst_16_MASK 0x00000001
-#define BCHP_EBI_BURST_CFG_4_burst_16_SHIFT 0
-#define BCHP_EBI_BURST_CFG_4_burst_16_DEFAULT 0x00000000
-
-/***************************************************************************
- *BURST_CFG_5 - EBI Synchronous Intel StrataFlash Burst Configure Register
- ***************************************************************************/
-/* EBI :: BURST_CFG_5 :: prefetch_enable [31:31] */
-#define BCHP_EBI_BURST_CFG_5_prefetch_enable_MASK 0x80000000
-#define BCHP_EBI_BURST_CFG_5_prefetch_enable_SHIFT 31
-#define BCHP_EBI_BURST_CFG_5_prefetch_enable_DEFAULT 0x00000000
-
-/* EBI :: BURST_CFG_5 :: page_enable [30:30] */
-#define BCHP_EBI_BURST_CFG_5_page_enable_MASK 0x40000000
-#define BCHP_EBI_BURST_CFG_5_page_enable_SHIFT 30
-#define BCHP_EBI_BURST_CFG_5_page_enable_DEFAULT 0x00000000
-
-/* EBI :: BURST_CFG_5 :: pfetch_abort_enable [29:29] */
-#define BCHP_EBI_BURST_CFG_5_pfetch_abort_enable_MASK 0x20000000
-#define BCHP_EBI_BURST_CFG_5_pfetch_abort_enable_SHIFT 29
-#define BCHP_EBI_BURST_CFG_5_pfetch_abort_enable_DEFAULT 0x00000000
-
-/* EBI :: BURST_CFG_5 :: page_latch_enable [28:28] */
-#define BCHP_EBI_BURST_CFG_5_page_latch_enable_MASK 0x10000000
-#define BCHP_EBI_BURST_CFG_5_page_latch_enable_SHIFT 28
-#define BCHP_EBI_BURST_CFG_5_page_latch_enable_DEFAULT 0x00000000
-
-/* EBI :: BURST_CFG_5 :: pfetch_wrap_enable [27:27] */
-#define BCHP_EBI_BURST_CFG_5_pfetch_wrap_enable_MASK 0x08000000
-#define BCHP_EBI_BURST_CFG_5_pfetch_wrap_enable_SHIFT 27
-#define BCHP_EBI_BURST_CFG_5_pfetch_wrap_enable_DEFAULT 0x00000000
-
-/* EBI :: BURST_CFG_5 :: reserved0 [26:24] */
-#define BCHP_EBI_BURST_CFG_5_reserved0_MASK 0x07000000
-#define BCHP_EBI_BURST_CFG_5_reserved0_SHIFT 24
-
-/* EBI :: BURST_CFG_5 :: prefetch_size [23:22] */
-#define BCHP_EBI_BURST_CFG_5_prefetch_size_MASK 0x00c00000
-#define BCHP_EBI_BURST_CFG_5_prefetch_size_SHIFT 22
-#define BCHP_EBI_BURST_CFG_5_prefetch_size_DEFAULT 0x00000000
-#define BCHP_EBI_BURST_CFG_5_prefetch_size_SIZE_4_BYTES 0
-#define BCHP_EBI_BURST_CFG_5_prefetch_size_SIZE_8_BYTES 1
-#define BCHP_EBI_BURST_CFG_5_prefetch_size_SIZE_16_BYTES 2
-#define BCHP_EBI_BURST_CFG_5_prefetch_size_SIZE_32_BYTES 3
-
-/* EBI :: BURST_CFG_5 :: page_size [21:20] */
-#define BCHP_EBI_BURST_CFG_5_page_size_MASK 0x00300000
-#define BCHP_EBI_BURST_CFG_5_page_size_SHIFT 20
-#define BCHP_EBI_BURST_CFG_5_page_size_DEFAULT 0x00000000
-#define BCHP_EBI_BURST_CFG_5_page_size_SIZE_4_BYTES 0
-#define BCHP_EBI_BURST_CFG_5_page_size_SIZE_8_BYTES 1
-#define BCHP_EBI_BURST_CFG_5_page_size_SIZE_16_BYTES 2
-#define BCHP_EBI_BURST_CFG_5_page_size_SIZE_32_BYTES 3
-
-/* EBI :: BURST_CFG_5 :: page_wait_count [19:16] */
-#define BCHP_EBI_BURST_CFG_5_page_wait_count_MASK 0x000f0000
-#define BCHP_EBI_BURST_CFG_5_page_wait_count_SHIFT 16
-#define BCHP_EBI_BURST_CFG_5_page_wait_count_DEFAULT 0x00000001
-
-/* EBI :: BURST_CFG_5 :: burst_cyc_disable [15:15] */
-#define BCHP_EBI_BURST_CFG_5_burst_cyc_disable_MASK 0x00008000
-#define BCHP_EBI_BURST_CFG_5_burst_cyc_disable_SHIFT 15
-#define BCHP_EBI_BURST_CFG_5_burst_cyc_disable_DEFAULT 0x00000001
-
-/* EBI :: BURST_CFG_5 :: reserved1 [14:08] */
-#define BCHP_EBI_BURST_CFG_5_reserved1_MASK 0x00007f00
-#define BCHP_EBI_BURST_CFG_5_reserved1_SHIFT 8
-
-/* EBI :: BURST_CFG_5 :: burst_latency [07:04] */
-#define BCHP_EBI_BURST_CFG_5_burst_latency_MASK 0x000000f0
-#define BCHP_EBI_BURST_CFG_5_burst_latency_SHIFT 4
-#define BCHP_EBI_BURST_CFG_5_burst_latency_DEFAULT 0x00000000
-
-/* EBI :: BURST_CFG_5 :: reserved2 [03:02] */
-#define BCHP_EBI_BURST_CFG_5_reserved2_MASK 0x0000000c
-#define BCHP_EBI_BURST_CFG_5_reserved2_SHIFT 2
-
-/* EBI :: BURST_CFG_5 :: data_hold [01:01] */
-#define BCHP_EBI_BURST_CFG_5_data_hold_MASK 0x00000002
-#define BCHP_EBI_BURST_CFG_5_data_hold_SHIFT 1
-#define BCHP_EBI_BURST_CFG_5_data_hold_DEFAULT 0x00000000
-
-/* EBI :: BURST_CFG_5 :: burst_16 [00:00] */
-#define BCHP_EBI_BURST_CFG_5_burst_16_MASK 0x00000001
-#define BCHP_EBI_BURST_CFG_5_burst_16_SHIFT 0
-#define BCHP_EBI_BURST_CFG_5_burst_16_DEFAULT 0x00000000
-
-/***************************************************************************
- *BURST_CFG_6 - EBI Synchronous Intel StrataFlash Burst Configure Register
- ***************************************************************************/
-/* EBI :: BURST_CFG_6 :: prefetch_enable [31:31] */
-#define BCHP_EBI_BURST_CFG_6_prefetch_enable_MASK 0x80000000
-#define BCHP_EBI_BURST_CFG_6_prefetch_enable_SHIFT 31
-#define BCHP_EBI_BURST_CFG_6_prefetch_enable_DEFAULT 0x00000000
-
-/* EBI :: BURST_CFG_6 :: page_enable [30:30] */
-#define BCHP_EBI_BURST_CFG_6_page_enable_MASK 0x40000000
-#define BCHP_EBI_BURST_CFG_6_page_enable_SHIFT 30
-#define BCHP_EBI_BURST_CFG_6_page_enable_DEFAULT 0x00000000
-
-/* EBI :: BURST_CFG_6 :: pfetch_abort_enable [29:29] */
-#define BCHP_EBI_BURST_CFG_6_pfetch_abort_enable_MASK 0x20000000
-#define BCHP_EBI_BURST_CFG_6_pfetch_abort_enable_SHIFT 29
-#define BCHP_EBI_BURST_CFG_6_pfetch_abort_enable_DEFAULT 0x00000000
-
-/* EBI :: BURST_CFG_6 :: page_latch_enable [28:28] */
-#define BCHP_EBI_BURST_CFG_6_page_latch_enable_MASK 0x10000000
-#define BCHP_EBI_BURST_CFG_6_page_latch_enable_SHIFT 28
-#define BCHP_EBI_BURST_CFG_6_page_latch_enable_DEFAULT 0x00000000
-
-/* EBI :: BURST_CFG_6 :: pfetch_wrap_enable [27:27] */
-#define BCHP_EBI_BURST_CFG_6_pfetch_wrap_enable_MASK 0x08000000
-#define BCHP_EBI_BURST_CFG_6_pfetch_wrap_enable_SHIFT 27
-#define BCHP_EBI_BURST_CFG_6_pfetch_wrap_enable_DEFAULT 0x00000000
-
-/* EBI :: BURST_CFG_6 :: reserved0 [26:24] */
-#define BCHP_EBI_BURST_CFG_6_reserved0_MASK 0x07000000
-#define BCHP_EBI_BURST_CFG_6_reserved0_SHIFT 24
-
-/* EBI :: BURST_CFG_6 :: prefetch_size [23:22] */
-#define BCHP_EBI_BURST_CFG_6_prefetch_size_MASK 0x00c00000
-#define BCHP_EBI_BURST_CFG_6_prefetch_size_SHIFT 22
-#define BCHP_EBI_BURST_CFG_6_prefetch_size_DEFAULT 0x00000000
-#define BCHP_EBI_BURST_CFG_6_prefetch_size_SIZE_4_BYTES 0
-#define BCHP_EBI_BURST_CFG_6_prefetch_size_SIZE_8_BYTES 1
-#define BCHP_EBI_BURST_CFG_6_prefetch_size_SIZE_16_BYTES 2
-#define BCHP_EBI_BURST_CFG_6_prefetch_size_SIZE_32_BYTES 3
-
-/* EBI :: BURST_CFG_6 :: page_size [21:20] */
-#define BCHP_EBI_BURST_CFG_6_page_size_MASK 0x00300000
-#define BCHP_EBI_BURST_CFG_6_page_size_SHIFT 20
-#define BCHP_EBI_BURST_CFG_6_page_size_DEFAULT 0x00000000
-#define BCHP_EBI_BURST_CFG_6_page_size_SIZE_4_BYTES 0
-#define BCHP_EBI_BURST_CFG_6_page_size_SIZE_8_BYTES 1
-#define BCHP_EBI_BURST_CFG_6_page_size_SIZE_16_BYTES 2
-#define BCHP_EBI_BURST_CFG_6_page_size_SIZE_32_BYTES 3
-
-/* EBI :: BURST_CFG_6 :: page_wait_count [19:16] */
-#define BCHP_EBI_BURST_CFG_6_page_wait_count_MASK 0x000f0000
-#define BCHP_EBI_BURST_CFG_6_page_wait_count_SHIFT 16
-#define BCHP_EBI_BURST_CFG_6_page_wait_count_DEFAULT 0x00000001
-
-/* EBI :: BURST_CFG_6 :: burst_cyc_disable [15:15] */
-#define BCHP_EBI_BURST_CFG_6_burst_cyc_disable_MASK 0x00008000
-#define BCHP_EBI_BURST_CFG_6_burst_cyc_disable_SHIFT 15
-#define BCHP_EBI_BURST_CFG_6_burst_cyc_disable_DEFAULT 0x00000001
-
-/* EBI :: BURST_CFG_6 :: reserved1 [14:08] */
-#define BCHP_EBI_BURST_CFG_6_reserved1_MASK 0x00007f00
-#define BCHP_EBI_BURST_CFG_6_reserved1_SHIFT 8
-
-/* EBI :: BURST_CFG_6 :: burst_latency [07:04] */
-#define BCHP_EBI_BURST_CFG_6_burst_latency_MASK 0x000000f0
-#define BCHP_EBI_BURST_CFG_6_burst_latency_SHIFT 4
-#define BCHP_EBI_BURST_CFG_6_burst_latency_DEFAULT 0x00000000
-
-/* EBI :: BURST_CFG_6 :: reserved2 [03:02] */
-#define BCHP_EBI_BURST_CFG_6_reserved2_MASK 0x0000000c
-#define BCHP_EBI_BURST_CFG_6_reserved2_SHIFT 2
-
-/* EBI :: BURST_CFG_6 :: data_hold [01:01] */
-#define BCHP_EBI_BURST_CFG_6_data_hold_MASK 0x00000002
-#define BCHP_EBI_BURST_CFG_6_data_hold_SHIFT 1
-#define BCHP_EBI_BURST_CFG_6_data_hold_DEFAULT 0x00000000
-
-/* EBI :: BURST_CFG_6 :: burst_16 [00:00] */
-#define BCHP_EBI_BURST_CFG_6_burst_16_MASK 0x00000001
-#define BCHP_EBI_BURST_CFG_6_burst_16_SHIFT 0
-#define BCHP_EBI_BURST_CFG_6_burst_16_DEFAULT 0x00000000
-
-/***************************************************************************
- *ECR - EBI Configuration Register
- ***************************************************************************/
-/* EBI :: ECR :: reserved0 [31:28] */
-#define BCHP_EBI_ECR_reserved0_MASK 0xf0000000
-#define BCHP_EBI_ECR_reserved0_SHIFT 28
-
-/* EBI :: ECR :: Ebi_Byte_Swap [27:27] */
-#define BCHP_EBI_ECR_Ebi_Byte_Swap_MASK 0x08000000
-#define BCHP_EBI_ECR_Ebi_Byte_Swap_SHIFT 27
-#define BCHP_EBI_ECR_Ebi_Byte_Swap_DEFAULT 0x00000000
-#define BCHP_EBI_ECR_Ebi_Byte_Swap_Byte_Swap_For_32_16_and_8_bit_Xfers 0
-#define BCHP_EBI_ECR_Ebi_Byte_Swap_Byte_Swap_For_8_bit_Xfers_Only 1
-
-/* EBI :: ECR :: reserved1 [26:26] */
-#define BCHP_EBI_ECR_reserved1_MASK 0x04000000
-#define BCHP_EBI_ECR_reserved1_SHIFT 26
-
-/* EBI :: ECR :: Flag_32bit_Xfer [25:25] */
-#define BCHP_EBI_ECR_Flag_32bit_Xfer_MASK 0x02000000
-#define BCHP_EBI_ECR_Flag_32bit_Xfer_SHIFT 25
-#define BCHP_EBI_ECR_Flag_32bit_Xfer_DEFAULT 0x00000000
-#define BCHP_EBI_ECR_Flag_32bit_Xfer_Code_32bit_Xfer_as_10 0
-#define BCHP_EBI_ECR_Flag_32bit_Xfer_Code_32bit_Xfer_as_00 1
-
-/* EBI :: ECR :: reserved2 [24:11] */
-#define BCHP_EBI_ECR_reserved2_MASK 0x01fff800
-#define BCHP_EBI_ECR_reserved2_SHIFT 11
-
-/* EBI :: ECR :: timeout_count [10:00] */
-#define BCHP_EBI_ECR_timeout_count_MASK 0x000007ff
-#define BCHP_EBI_ECR_timeout_count_SHIFT 0
-#define BCHP_EBI_ECR_timeout_count_DEFAULT 0x00000400
-
-/***************************************************************************
- *CS_TRISTATE_CFG - EBI CS Tristate Configuration Register
- ***************************************************************************/
-/* EBI :: CS_TRISTATE_CFG :: tristate_ebi_rdb [31:31] */
-#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_rdb_MASK 0x80000000
-#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_rdb_SHIFT 31
-#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_rdb_DEFAULT 0x00000000
-
-/* EBI :: CS_TRISTATE_CFG :: tristate_ebi_dsb [30:30] */
-#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_dsb_MASK 0x40000000
-#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_dsb_SHIFT 30
-#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_dsb_DEFAULT 0x00000000
-
-/* EBI :: CS_TRISTATE_CFG :: tristate_ebi_tsb [29:29] */
-#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_tsb_MASK 0x20000000
-#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_tsb_SHIFT 29
-#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_tsb_DEFAULT 0x00000000
-
-/* EBI :: CS_TRISTATE_CFG :: tristate_ebi_rwb [28:28] */
-#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_rwb_MASK 0x10000000
-#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_rwb_SHIFT 28
-#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_rwb_DEFAULT 0x00000000
-
-/* EBI :: CS_TRISTATE_CFG :: tristate_ebi_we1b [27:27] */
-#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_we1b_MASK 0x08000000
-#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_we1b_SHIFT 27
-#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_we1b_DEFAULT 0x00000000
-
-/* EBI :: CS_TRISTATE_CFG :: tristate_ebi_we0b [26:26] */
-#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_we0b_MASK 0x04000000
-#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_we0b_SHIFT 26
-#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_we0b_DEFAULT 0x00000000
-
-/* EBI :: CS_TRISTATE_CFG :: tristate_ebi_tsize1b [25:25] */
-#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_tsize1b_MASK 0x02000000
-#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_tsize1b_SHIFT 25
-#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_tsize1b_DEFAULT 0x00000000
-
-/* EBI :: CS_TRISTATE_CFG :: tristate_ebi_tsize0b [24:24] */
-#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_tsize0b_MASK 0x01000000
-#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_tsize0b_SHIFT 24
-#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_tsize0b_DEFAULT 0x00000000
-
-/* EBI :: CS_TRISTATE_CFG :: reserved0 [23:07] */
-#define BCHP_EBI_CS_TRISTATE_CFG_reserved0_MASK 0x00ffff80
-#define BCHP_EBI_CS_TRISTATE_CFG_reserved0_SHIFT 7
-
-/* EBI :: CS_TRISTATE_CFG :: tristate_ebi_cs6 [06:06] */
-#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_cs6_MASK 0x00000040
-#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_cs6_SHIFT 6
-#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_cs6_DEFAULT 0x00000000
-
-/* EBI :: CS_TRISTATE_CFG :: tristate_ebi_cs5 [05:05] */
-#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_cs5_MASK 0x00000020
-#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_cs5_SHIFT 5
-#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_cs5_DEFAULT 0x00000000
-
-/* EBI :: CS_TRISTATE_CFG :: tristate_ebi_cs4 [04:04] */
-#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_cs4_MASK 0x00000010
-#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_cs4_SHIFT 4
-#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_cs4_DEFAULT 0x00000000
-
-/* EBI :: CS_TRISTATE_CFG :: tristate_ebi_cs3 [03:03] */
-#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_cs3_MASK 0x00000008
-#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_cs3_SHIFT 3
-#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_cs3_DEFAULT 0x00000000
-
-/* EBI :: CS_TRISTATE_CFG :: tristate_ebi_cs2 [02:02] */
-#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_cs2_MASK 0x00000004
-#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_cs2_SHIFT 2
-#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_cs2_DEFAULT 0x00000000
-
-/* EBI :: CS_TRISTATE_CFG :: tristate_ebi_cs1 [01:01] */
-#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_cs1_MASK 0x00000002
-#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_cs1_SHIFT 1
-#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_cs1_DEFAULT 0x00000000
-
-/* EBI :: CS_TRISTATE_CFG :: tristate_ebi_cs0 [00:00] */
-#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_cs0_MASK 0x00000001
-#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_cs0_SHIFT 0
-#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_cs0_DEFAULT 0x00000000
-
-/***************************************************************************
- *CS_SPI_SELECT - SPI CS Select
- ***************************************************************************/
-/* EBI :: CS_SPI_SELECT :: reserved0 [31:15] */
-#define BCHP_EBI_CS_SPI_SELECT_reserved0_MASK 0xffff8000
-#define BCHP_EBI_CS_SPI_SELECT_reserved0_SHIFT 15
-
-/* EBI :: CS_SPI_SELECT :: EBI_CS_6_USES_SPI [14:14] */
-#define BCHP_EBI_CS_SPI_SELECT_EBI_CS_6_USES_SPI_MASK 0x00004000
-#define BCHP_EBI_CS_SPI_SELECT_EBI_CS_6_USES_SPI_SHIFT 14
-#define BCHP_EBI_CS_SPI_SELECT_EBI_CS_6_USES_SPI_DEFAULT 0x00000000
-
-/* EBI :: CS_SPI_SELECT :: EBI_CS_5_USES_SPI [13:13] */
-#define BCHP_EBI_CS_SPI_SELECT_EBI_CS_5_USES_SPI_MASK 0x00002000
-#define BCHP_EBI_CS_SPI_SELECT_EBI_CS_5_USES_SPI_SHIFT 13
-#define BCHP_EBI_CS_SPI_SELECT_EBI_CS_5_USES_SPI_DEFAULT 0x00000000
-
-/* EBI :: CS_SPI_SELECT :: EBI_CS_4_USES_SPI [12:12] */
-#define BCHP_EBI_CS_SPI_SELECT_EBI_CS_4_USES_SPI_MASK 0x00001000
-#define BCHP_EBI_CS_SPI_SELECT_EBI_CS_4_USES_SPI_SHIFT 12
-#define BCHP_EBI_CS_SPI_SELECT_EBI_CS_4_USES_SPI_DEFAULT 0x00000000
-
-/* EBI :: CS_SPI_SELECT :: EBI_CS_3_USES_SPI [11:11] */
-#define BCHP_EBI_CS_SPI_SELECT_EBI_CS_3_USES_SPI_MASK 0x00000800
-#define BCHP_EBI_CS_SPI_SELECT_EBI_CS_3_USES_SPI_SHIFT 11
-#define BCHP_EBI_CS_SPI_SELECT_EBI_CS_3_USES_SPI_DEFAULT 0x00000000
-
-/* EBI :: CS_SPI_SELECT :: EBI_CS_2_USES_SPI [10:10] */
-#define BCHP_EBI_CS_SPI_SELECT_EBI_CS_2_USES_SPI_MASK 0x00000400
-#define BCHP_EBI_CS_SPI_SELECT_EBI_CS_2_USES_SPI_SHIFT 10
-#define BCHP_EBI_CS_SPI_SELECT_EBI_CS_2_USES_SPI_DEFAULT 0x00000000
-
-/* EBI :: CS_SPI_SELECT :: EBI_CS_1_USES_SPI [09:09] */
-#define BCHP_EBI_CS_SPI_SELECT_EBI_CS_1_USES_SPI_MASK 0x00000200
-#define BCHP_EBI_CS_SPI_SELECT_EBI_CS_1_USES_SPI_SHIFT 9
-#define BCHP_EBI_CS_SPI_SELECT_EBI_CS_1_USES_SPI_DEFAULT 0x00000000
-
-/* EBI :: CS_SPI_SELECT :: EBI_CS_0_USES_SPI [08:08] */
-#define BCHP_EBI_CS_SPI_SELECT_EBI_CS_0_USES_SPI_MASK 0x00000100
-#define BCHP_EBI_CS_SPI_SELECT_EBI_CS_0_USES_SPI_SHIFT 8
-
-/* EBI :: CS_SPI_SELECT :: reserved1 [07:07] */
-#define BCHP_EBI_CS_SPI_SELECT_reserved1_MASK 0x00000080
-#define BCHP_EBI_CS_SPI_SELECT_reserved1_SHIFT 7
-
-/* EBI :: CS_SPI_SELECT :: SPI_EBI_CS_6_SEL [06:06] */
-#define BCHP_EBI_CS_SPI_SELECT_SPI_EBI_CS_6_SEL_MASK 0x00000040
-#define BCHP_EBI_CS_SPI_SELECT_SPI_EBI_CS_6_SEL_SHIFT 6
-#define BCHP_EBI_CS_SPI_SELECT_SPI_EBI_CS_6_SEL_DEFAULT 0x00000000
-
-/* EBI :: CS_SPI_SELECT :: SPI_EBI_CS_5_SEL [05:05] */
-#define BCHP_EBI_CS_SPI_SELECT_SPI_EBI_CS_5_SEL_MASK 0x00000020
-#define BCHP_EBI_CS_SPI_SELECT_SPI_EBI_CS_5_SEL_SHIFT 5
-#define BCHP_EBI_CS_SPI_SELECT_SPI_EBI_CS_5_SEL_DEFAULT 0x00000000
-
-/* EBI :: CS_SPI_SELECT :: SPI_EBI_CS_4_SEL [04:04] */
-#define BCHP_EBI_CS_SPI_SELECT_SPI_EBI_CS_4_SEL_MASK 0x00000010
-#define BCHP_EBI_CS_SPI_SELECT_SPI_EBI_CS_4_SEL_SHIFT 4
-#define BCHP_EBI_CS_SPI_SELECT_SPI_EBI_CS_4_SEL_DEFAULT 0x00000000
-
-/* EBI :: CS_SPI_SELECT :: SPI_EBI_CS_3_SEL [03:03] */
-#define BCHP_EBI_CS_SPI_SELECT_SPI_EBI_CS_3_SEL_MASK 0x00000008
-#define BCHP_EBI_CS_SPI_SELECT_SPI_EBI_CS_3_SEL_SHIFT 3
-#define BCHP_EBI_CS_SPI_SELECT_SPI_EBI_CS_3_SEL_DEFAULT 0x00000000
-
-/* EBI :: CS_SPI_SELECT :: SPI_EBI_CS_2_SEL [02:02] */
-#define BCHP_EBI_CS_SPI_SELECT_SPI_EBI_CS_2_SEL_MASK 0x00000004
-#define BCHP_EBI_CS_SPI_SELECT_SPI_EBI_CS_2_SEL_SHIFT 2
-#define BCHP_EBI_CS_SPI_SELECT_SPI_EBI_CS_2_SEL_DEFAULT 0x00000000
-
-/* EBI :: CS_SPI_SELECT :: SPI_EBI_CS_1_SEL [01:01] */
-#define BCHP_EBI_CS_SPI_SELECT_SPI_EBI_CS_1_SEL_MASK 0x00000002
-#define BCHP_EBI_CS_SPI_SELECT_SPI_EBI_CS_1_SEL_SHIFT 1
-#define BCHP_EBI_CS_SPI_SELECT_SPI_EBI_CS_1_SEL_DEFAULT 0x00000000
-
-/* EBI :: CS_SPI_SELECT :: SPI_EBI_CS_0_SEL [00:00] */
-#define BCHP_EBI_CS_SPI_SELECT_SPI_EBI_CS_0_SEL_MASK 0x00000001
-#define BCHP_EBI_CS_SPI_SELECT_SPI_EBI_CS_0_SEL_SHIFT 0
-
-/***************************************************************************
- *ARRAY_ADDRESS - EBI Data Array Address
- ***************************************************************************/
-/* EBI :: ARRAY_ADDRESS :: ADDRESS [31:09] */
-#define BCHP_EBI_ARRAY_ADDRESS_ADDRESS_MASK 0xfffffe00
-#define BCHP_EBI_ARRAY_ADDRESS_ADDRESS_SHIFT 9
-#define BCHP_EBI_ARRAY_ADDRESS_ADDRESS_DEFAULT 0x00000000
-
-/* EBI :: ARRAY_ADDRESS :: reserved0 [08:03] */
-#define BCHP_EBI_ARRAY_ADDRESS_reserved0_MASK 0x000001f8
-#define BCHP_EBI_ARRAY_ADDRESS_reserved0_SHIFT 3
-
-/* EBI :: ARRAY_ADDRESS :: CS_SEL [02:00] */
-#define BCHP_EBI_ARRAY_ADDRESS_CS_SEL_MASK 0x00000007
-#define BCHP_EBI_ARRAY_ADDRESS_CS_SEL_SHIFT 0
-#define BCHP_EBI_ARRAY_ADDRESS_CS_SEL_DEFAULT 0x00000000
-
-/***************************************************************************
- *DATA_ARRAY%i - EBI Data Array Read/Write Access
- ***************************************************************************/
-#define BCHP_EBI_DATA_ARRAYi_ARRAY_BASE 0x00440a00
-#define BCHP_EBI_DATA_ARRAYi_ARRAY_START 0
-#define BCHP_EBI_DATA_ARRAYi_ARRAY_END 127
-#define BCHP_EBI_DATA_ARRAYi_ARRAY_ELEMENT_SIZE 32
-
-/***************************************************************************
- *DATA_ARRAY%i - EBI Data Array Read/Write Access
- ***************************************************************************/
-/* EBI :: DATA_ARRAYi :: WORD [31:00] */
-#define BCHP_EBI_DATA_ARRAYi_WORD_MASK 0xffffffff
-#define BCHP_EBI_DATA_ARRAYi_WORD_SHIFT 0
-
-
-#endif /* #ifndef BCHP_EBI_H__ */
-
-/* End of File */
diff --git a/include/linux/brcmstb/7439a0/bchp_gio.h b/include/linux/brcmstb/7439a0/bchp_gio.h
deleted file mode 100644
index cbf2abe..0000000
--- a/include/linux/brcmstb/7439a0/bchp_gio.h
+++ /dev/null
@@ -1,472 +0,0 @@
-/***************************************************************************
- * Copyright (c) 1999-2013, Broadcom Corporation
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
- *
- * Module Description:
- * DO NOT EDIT THIS FILE DIRECTLY
- *
- * This module was generated magically with RDB from a source description
- * file. You must edit the source file for changes to be made to this file.
- *
- *
- * Date: Generated on Tue Apr 16 03:26:49 2013
- * MD5 Checksum d41d8cd98f00b204e9800998ecf8427e
- *
- * Compiled with: RDB Utility combo_header.pl
- * RDB Parser 3.0
- * unknown unknown
- * Perl Interpreter 5.008008
- * Operating System linux
- *
- * Revision History:
- *
- * $brcm_Log: $
- *
- ***************************************************************************/
-
-#ifndef BCHP_GIO_H__
-#define BCHP_GIO_H__
-
-/***************************************************************************
- *GIO - GPIO
- ***************************************************************************/
-#define BCHP_GIO_ODEN_LO 0x00406700 /* GENERAL PURPOSE I/O OPEN DRAIN ENABLE FOR GPIO[31:0] */
-#define BCHP_GIO_DATA_LO 0x00406704 /* GENERAL PURPOSE I/O DATA FOR GPIO[31:0] */
-#define BCHP_GIO_IODIR_LO 0x00406708 /* GENERAL PURPOSE I/O DIRECTION FOR GPIO[31:0] */
-#define BCHP_GIO_EC_LO 0x0040670c /* GENERAL PURPOSE I/O EDGE CONFIGURATION FOR GPIO[31:0] */
-#define BCHP_GIO_EI_LO 0x00406710 /* GENERAL PURPOSE I/O EDGE INSENSITIVE FOR GPIO[31:0] */
-#define BCHP_GIO_MASK_LO 0x00406714 /* GENERAL PURPOSE I/O INTERRUPT MASK FOR GPIO[31:0] */
-#define BCHP_GIO_LEVEL_LO 0x00406718 /* GENERAL PURPOSE I/O INTERRUPT TYPE FOR GPIO[31:0] */
-#define BCHP_GIO_STAT_LO 0x0040671c /* GENERAL PURPOSE I/O INTERRUPT STATUS FOR GPIO[31:0] */
-#define BCHP_GIO_ODEN_HI 0x00406720 /* GENERAL PURPOSE I/O OPEN DRAIN ENABLE FOR GPIO[63:32] */
-#define BCHP_GIO_DATA_HI 0x00406724 /* GENERAL PURPOSE I/O DATA FOR GPIO[63:32] */
-#define BCHP_GIO_IODIR_HI 0x00406728 /* GENERAL PURPOSE I/O DIRECTION FOR GPIO[63:32] */
-#define BCHP_GIO_EC_HI 0x0040672c /* GENERAL PURPOSE I/O EDGE CONFIGURATION FOR GPIO[63:32] */
-#define BCHP_GIO_EI_HI 0x00406730 /* GENERAL PURPOSE I/O EDGE INSENSITIVE FOR GPIO[63:32] */
-#define BCHP_GIO_MASK_HI 0x00406734 /* GENERAL PURPOSE I/O INTERRUPT MASK FOR GPIO[63:32] */
-#define BCHP_GIO_LEVEL_HI 0x00406738 /* GENERAL PURPOSE I/O INTERRUPT TYPE FOR GPIO[63:32] */
-#define BCHP_GIO_STAT_HI 0x0040673c /* GENERAL PURPOSE I/O INTERRUPT STATUS FOR GPIO[63:32] */
-#define BCHP_GIO_ODEN_EXT_HI 0x00406740 /* GENERAL PURPOSE I/O OPEN DRAIN ENABLE FOR GPIO[95:64] */
-#define BCHP_GIO_DATA_EXT_HI 0x00406744 /* GENERAL PURPOSE I/O DATA FOR GPIO[95:64] */
-#define BCHP_GIO_IODIR_EXT_HI 0x00406748 /* GENERAL PURPOSE I/O DIRECTION FOR GPIO[95:64] */
-#define BCHP_GIO_EC_EXT_HI 0x0040674c /* GENERAL PURPOSE I/O EDGE CONFIGURATION FOR GPIO[95:64] */
-#define BCHP_GIO_EI_EXT_HI 0x00406750 /* GENERAL PURPOSE I/O EDGE INSENSITIVE FOR GPIO[95:64] */
-#define BCHP_GIO_MASK_EXT_HI 0x00406754 /* GENERAL PURPOSE I/O INTERRUPT MASK FOR GPIO[95:64] */
-#define BCHP_GIO_LEVEL_EXT_HI 0x00406758 /* GENERAL PURPOSE I/O INTERRUPT TYPE FOR GPIO[95:64] */
-#define BCHP_GIO_STAT_EXT_HI 0x0040675c /* GENERAL PURPOSE I/O INTERRUPT STATUS FOR GPIO[95:64] */
-#define BCHP_GIO_ODEN_EXT2 0x00406760 /* GENERAL PURPOSE I/O OPEN DRAIN ENABLE FOR GPIO[111:96] */
-#define BCHP_GIO_DATA_EXT2 0x00406764 /* GENERAL PURPOSE I/O DATA FOR GPIO[111:96] */
-#define BCHP_GIO_IODIR_EXT2 0x00406768 /* GENERAL PURPOSE I/O DIRECTION FOR GPIO[111:96] */
-#define BCHP_GIO_EC_EXT2 0x0040676c /* GENERAL PURPOSE I/O EDGE CONFIGURATION FOR GPIO[111:96] */
-#define BCHP_GIO_EI_EXT2 0x00406770 /* GENERAL PURPOSE I/O EDGE INSENSITIVE FOR GPIO[111:96] */
-#define BCHP_GIO_MASK_EXT2 0x00406774 /* GENERAL PURPOSE I/O INTERRUPT MASK FOR GPIO[111:96] */
-#define BCHP_GIO_LEVEL_EXT2 0x00406778 /* GENERAL PURPOSE I/O INTERRUPT TYPE FOR GPIO[111:96] */
-#define BCHP_GIO_STAT_EXT2 0x0040677c /* GENERAL PURPOSE I/O INTERRUPT STATUS FOR GPIO[111:96] */
-#define BCHP_GIO_ODEN_EXT 0x00406780 /* GENERAL PURPOSE I/O OPEN DRAIN ENABLE FOR AON_SGPIO[3:0] and SGPIO[5:0] */
-#define BCHP_GIO_DATA_EXT 0x00406784 /* GENERAL PURPOSE I/O DATA FOR AON_SGPIO[3:0] and SGPIO[5:0] */
-#define BCHP_GIO_IODIR_EXT 0x00406788 /* GENERAL PURPOSE I/O DIRECTION FOR AON_SGPIO[3:0] and SGPIO[5:0] */
-#define BCHP_GIO_EC_EXT 0x0040678c /* GENERAL PURPOSE I/O EDGE CONFIGURATION FOR AON_SGPIO[3:0] and SGPIO[5:0] */
-#define BCHP_GIO_EI_EXT 0x00406790 /* GENERAL PURPOSE I/O EDGE INSENSITIVE FOR AON_SGPIO[3:0] and SGPIO[5:0] */
-#define BCHP_GIO_MASK_EXT 0x00406794 /* GENERAL PURPOSE I/O INTERRUPT MASK FOR AON_SGPIO[3:0] and SGPIO[5:0] */
-#define BCHP_GIO_LEVEL_EXT 0x00406798 /* GENERAL PURPOSE I/O INTERRUPT TYPE FOR AON_SGPIO[3:0] and SGPIO[5:0] */
-#define BCHP_GIO_STAT_EXT 0x0040679c /* GENERAL PURPOSE I/O INTERRUPT STATUS FOR AON_SGPIO[3:0] and SGPIO[5:0] */
-
-/***************************************************************************
- *ODEN_LO - GENERAL PURPOSE I/O OPEN DRAIN ENABLE FOR GPIO[31:0]
- ***************************************************************************/
-/* GIO :: ODEN_LO :: oden [31:00] */
-#define BCHP_GIO_ODEN_LO_oden_MASK 0xffffffff
-#define BCHP_GIO_ODEN_LO_oden_SHIFT 0
-#define BCHP_GIO_ODEN_LO_oden_DEFAULT 0x00000000
-
-/***************************************************************************
- *DATA_LO - GENERAL PURPOSE I/O DATA FOR GPIO[31:0]
- ***************************************************************************/
-/* GIO :: DATA_LO :: data [31:00] */
-#define BCHP_GIO_DATA_LO_data_MASK 0xffffffff
-#define BCHP_GIO_DATA_LO_data_SHIFT 0
-#define BCHP_GIO_DATA_LO_data_DEFAULT 0x00000000
-
-/***************************************************************************
- *IODIR_LO - GENERAL PURPOSE I/O DIRECTION FOR GPIO[31:0]
- ***************************************************************************/
-/* GIO :: IODIR_LO :: iodir [31:00] */
-#define BCHP_GIO_IODIR_LO_iodir_MASK 0xffffffff
-#define BCHP_GIO_IODIR_LO_iodir_SHIFT 0
-#define BCHP_GIO_IODIR_LO_iodir_DEFAULT 0xffffffff
-
-/***************************************************************************
- *EC_LO - GENERAL PURPOSE I/O EDGE CONFIGURATION FOR GPIO[31:0]
- ***************************************************************************/
-/* GIO :: EC_LO :: edge_config [31:00] */
-#define BCHP_GIO_EC_LO_edge_config_MASK 0xffffffff
-#define BCHP_GIO_EC_LO_edge_config_SHIFT 0
-#define BCHP_GIO_EC_LO_edge_config_DEFAULT 0x00000000
-
-/***************************************************************************
- *EI_LO - GENERAL PURPOSE I/O EDGE INSENSITIVE FOR GPIO[31:0]
- ***************************************************************************/
-/* GIO :: EI_LO :: edge_insensitive [31:00] */
-#define BCHP_GIO_EI_LO_edge_insensitive_MASK 0xffffffff
-#define BCHP_GIO_EI_LO_edge_insensitive_SHIFT 0
-#define BCHP_GIO_EI_LO_edge_insensitive_DEFAULT 0x00000000
-
-/***************************************************************************
- *MASK_LO - GENERAL PURPOSE I/O INTERRUPT MASK FOR GPIO[31:0]
- ***************************************************************************/
-/* GIO :: MASK_LO :: irq_mask [31:00] */
-#define BCHP_GIO_MASK_LO_irq_mask_MASK 0xffffffff
-#define BCHP_GIO_MASK_LO_irq_mask_SHIFT 0
-#define BCHP_GIO_MASK_LO_irq_mask_DEFAULT 0x00000000
-
-/***************************************************************************
- *LEVEL_LO - GENERAL PURPOSE I/O INTERRUPT TYPE FOR GPIO[31:0]
- ***************************************************************************/
-/* GIO :: LEVEL_LO :: level [31:00] */
-#define BCHP_GIO_LEVEL_LO_level_MASK 0xffffffff
-#define BCHP_GIO_LEVEL_LO_level_SHIFT 0
-#define BCHP_GIO_LEVEL_LO_level_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_LO - GENERAL PURPOSE I/O INTERRUPT STATUS FOR GPIO[31:0]
- ***************************************************************************/
-/* GIO :: STAT_LO :: irq_status [31:00] */
-#define BCHP_GIO_STAT_LO_irq_status_MASK 0xffffffff
-#define BCHP_GIO_STAT_LO_irq_status_SHIFT 0
-#define BCHP_GIO_STAT_LO_irq_status_DEFAULT 0x00000000
-
-/***************************************************************************
- *ODEN_HI - GENERAL PURPOSE I/O OPEN DRAIN ENABLE FOR GPIO[63:32]
- ***************************************************************************/
-/* GIO :: ODEN_HI :: oden [31:00] */
-#define BCHP_GIO_ODEN_HI_oden_MASK 0xffffffff
-#define BCHP_GIO_ODEN_HI_oden_SHIFT 0
-#define BCHP_GIO_ODEN_HI_oden_DEFAULT 0x00000000
-
-/***************************************************************************
- *DATA_HI - GENERAL PURPOSE I/O DATA FOR GPIO[63:32]
- ***************************************************************************/
-/* GIO :: DATA_HI :: data [31:00] */
-#define BCHP_GIO_DATA_HI_data_MASK 0xffffffff
-#define BCHP_GIO_DATA_HI_data_SHIFT 0
-#define BCHP_GIO_DATA_HI_data_DEFAULT 0x00000000
-
-/***************************************************************************
- *IODIR_HI - GENERAL PURPOSE I/O DIRECTION FOR GPIO[63:32]
- ***************************************************************************/
-/* GIO :: IODIR_HI :: iodir [31:00] */
-#define BCHP_GIO_IODIR_HI_iodir_MASK 0xffffffff
-#define BCHP_GIO_IODIR_HI_iodir_SHIFT 0
-#define BCHP_GIO_IODIR_HI_iodir_DEFAULT 0xffffffff
-
-/***************************************************************************
- *EC_HI - GENERAL PURPOSE I/O EDGE CONFIGURATION FOR GPIO[63:32]
- ***************************************************************************/
-/* GIO :: EC_HI :: edge_config [31:00] */
-#define BCHP_GIO_EC_HI_edge_config_MASK 0xffffffff
-#define BCHP_GIO_EC_HI_edge_config_SHIFT 0
-#define BCHP_GIO_EC_HI_edge_config_DEFAULT 0x00000000
-
-/***************************************************************************
- *EI_HI - GENERAL PURPOSE I/O EDGE INSENSITIVE FOR GPIO[63:32]
- ***************************************************************************/
-/* GIO :: EI_HI :: edge_insensitive [31:00] */
-#define BCHP_GIO_EI_HI_edge_insensitive_MASK 0xffffffff
-#define BCHP_GIO_EI_HI_edge_insensitive_SHIFT 0
-#define BCHP_GIO_EI_HI_edge_insensitive_DEFAULT 0x00000000
-
-/***************************************************************************
- *MASK_HI - GENERAL PURPOSE I/O INTERRUPT MASK FOR GPIO[63:32]
- ***************************************************************************/
-/* GIO :: MASK_HI :: irq_mask [31:00] */
-#define BCHP_GIO_MASK_HI_irq_mask_MASK 0xffffffff
-#define BCHP_GIO_MASK_HI_irq_mask_SHIFT 0
-#define BCHP_GIO_MASK_HI_irq_mask_DEFAULT 0x00000000
-
-/***************************************************************************
- *LEVEL_HI - GENERAL PURPOSE I/O INTERRUPT TYPE FOR GPIO[63:32]
- ***************************************************************************/
-/* GIO :: LEVEL_HI :: level [31:00] */
-#define BCHP_GIO_LEVEL_HI_level_MASK 0xffffffff
-#define BCHP_GIO_LEVEL_HI_level_SHIFT 0
-#define BCHP_GIO_LEVEL_HI_level_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_HI - GENERAL PURPOSE I/O INTERRUPT STATUS FOR GPIO[63:32]
- ***************************************************************************/
-/* GIO :: STAT_HI :: irq_status [31:00] */
-#define BCHP_GIO_STAT_HI_irq_status_MASK 0xffffffff
-#define BCHP_GIO_STAT_HI_irq_status_SHIFT 0
-#define BCHP_GIO_STAT_HI_irq_status_DEFAULT 0x00000000
-
-/***************************************************************************
- *ODEN_EXT_HI - GENERAL PURPOSE I/O OPEN DRAIN ENABLE FOR GPIO[95:64]
- ***************************************************************************/
-/* GIO :: ODEN_EXT_HI :: oden [31:00] */
-#define BCHP_GIO_ODEN_EXT_HI_oden_MASK 0xffffffff
-#define BCHP_GIO_ODEN_EXT_HI_oden_SHIFT 0
-#define BCHP_GIO_ODEN_EXT_HI_oden_DEFAULT 0x00000000
-
-/***************************************************************************
- *DATA_EXT_HI - GENERAL PURPOSE I/O DATA FOR GPIO[95:64]
- ***************************************************************************/
-/* GIO :: DATA_EXT_HI :: data [31:00] */
-#define BCHP_GIO_DATA_EXT_HI_data_MASK 0xffffffff
-#define BCHP_GIO_DATA_EXT_HI_data_SHIFT 0
-#define BCHP_GIO_DATA_EXT_HI_data_DEFAULT 0x00000000
-
-/***************************************************************************
- *IODIR_EXT_HI - GENERAL PURPOSE I/O DIRECTION FOR GPIO[95:64]
- ***************************************************************************/
-/* GIO :: IODIR_EXT_HI :: iodir [31:00] */
-#define BCHP_GIO_IODIR_EXT_HI_iodir_MASK 0xffffffff
-#define BCHP_GIO_IODIR_EXT_HI_iodir_SHIFT 0
-#define BCHP_GIO_IODIR_EXT_HI_iodir_DEFAULT 0xffffffff
-
-/***************************************************************************
- *EC_EXT_HI - GENERAL PURPOSE I/O EDGE CONFIGURATION FOR GPIO[95:64]
- ***************************************************************************/
-/* GIO :: EC_EXT_HI :: edge_config [31:00] */
-#define BCHP_GIO_EC_EXT_HI_edge_config_MASK 0xffffffff
-#define BCHP_GIO_EC_EXT_HI_edge_config_SHIFT 0
-#define BCHP_GIO_EC_EXT_HI_edge_config_DEFAULT 0x00000000
-
-/***************************************************************************
- *EI_EXT_HI - GENERAL PURPOSE I/O EDGE INSENSITIVE FOR GPIO[95:64]
- ***************************************************************************/
-/* GIO :: EI_EXT_HI :: edge_insensitive [31:00] */
-#define BCHP_GIO_EI_EXT_HI_edge_insensitive_MASK 0xffffffff
-#define BCHP_GIO_EI_EXT_HI_edge_insensitive_SHIFT 0
-#define BCHP_GIO_EI_EXT_HI_edge_insensitive_DEFAULT 0x00000000
-
-/***************************************************************************
- *MASK_EXT_HI - GENERAL PURPOSE I/O INTERRUPT MASK FOR GPIO[95:64]
- ***************************************************************************/
-/* GIO :: MASK_EXT_HI :: irq_mask [31:00] */
-#define BCHP_GIO_MASK_EXT_HI_irq_mask_MASK 0xffffffff
-#define BCHP_GIO_MASK_EXT_HI_irq_mask_SHIFT 0
-#define BCHP_GIO_MASK_EXT_HI_irq_mask_DEFAULT 0x00000000
-
-/***************************************************************************
- *LEVEL_EXT_HI - GENERAL PURPOSE I/O INTERRUPT TYPE FOR GPIO[95:64]
- ***************************************************************************/
-/* GIO :: LEVEL_EXT_HI :: level [31:00] */
-#define BCHP_GIO_LEVEL_EXT_HI_level_MASK 0xffffffff
-#define BCHP_GIO_LEVEL_EXT_HI_level_SHIFT 0
-#define BCHP_GIO_LEVEL_EXT_HI_level_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_EXT_HI - GENERAL PURPOSE I/O INTERRUPT STATUS FOR GPIO[95:64]
- ***************************************************************************/
-/* GIO :: STAT_EXT_HI :: irq_status [31:00] */
-#define BCHP_GIO_STAT_EXT_HI_irq_status_MASK 0xffffffff
-#define BCHP_GIO_STAT_EXT_HI_irq_status_SHIFT 0
-#define BCHP_GIO_STAT_EXT_HI_irq_status_DEFAULT 0x00000000
-
-/***************************************************************************
- *ODEN_EXT2 - GENERAL PURPOSE I/O OPEN DRAIN ENABLE FOR GPIO[111:96]
- ***************************************************************************/
-/* GIO :: ODEN_EXT2 :: reserved0 [31:16] */
-#define BCHP_GIO_ODEN_EXT2_reserved0_MASK 0xffff0000
-#define BCHP_GIO_ODEN_EXT2_reserved0_SHIFT 16
-
-/* GIO :: ODEN_EXT2 :: oden [15:00] */
-#define BCHP_GIO_ODEN_EXT2_oden_MASK 0x0000ffff
-#define BCHP_GIO_ODEN_EXT2_oden_SHIFT 0
-#define BCHP_GIO_ODEN_EXT2_oden_DEFAULT 0x00000000
-
-/***************************************************************************
- *DATA_EXT2 - GENERAL PURPOSE I/O DATA FOR GPIO[111:96]
- ***************************************************************************/
-/* GIO :: DATA_EXT2 :: reserved0 [31:16] */
-#define BCHP_GIO_DATA_EXT2_reserved0_MASK 0xffff0000
-#define BCHP_GIO_DATA_EXT2_reserved0_SHIFT 16
-
-/* GIO :: DATA_EXT2 :: data [15:00] */
-#define BCHP_GIO_DATA_EXT2_data_MASK 0x0000ffff
-#define BCHP_GIO_DATA_EXT2_data_SHIFT 0
-#define BCHP_GIO_DATA_EXT2_data_DEFAULT 0x00000000
-
-/***************************************************************************
- *IODIR_EXT2 - GENERAL PURPOSE I/O DIRECTION FOR GPIO[111:96]
- ***************************************************************************/
-/* GIO :: IODIR_EXT2 :: reserved0 [31:16] */
-#define BCHP_GIO_IODIR_EXT2_reserved0_MASK 0xffff0000
-#define BCHP_GIO_IODIR_EXT2_reserved0_SHIFT 16
-
-/* GIO :: IODIR_EXT2 :: iodir [15:00] */
-#define BCHP_GIO_IODIR_EXT2_iodir_MASK 0x0000ffff
-#define BCHP_GIO_IODIR_EXT2_iodir_SHIFT 0
-#define BCHP_GIO_IODIR_EXT2_iodir_DEFAULT 0x0000ffff
-
-/***************************************************************************
- *EC_EXT2 - GENERAL PURPOSE I/O EDGE CONFIGURATION FOR GPIO[111:96]
- ***************************************************************************/
-/* GIO :: EC_EXT2 :: reserved0 [31:16] */
-#define BCHP_GIO_EC_EXT2_reserved0_MASK 0xffff0000
-#define BCHP_GIO_EC_EXT2_reserved0_SHIFT 16
-
-/* GIO :: EC_EXT2 :: edge_config [15:00] */
-#define BCHP_GIO_EC_EXT2_edge_config_MASK 0x0000ffff
-#define BCHP_GIO_EC_EXT2_edge_config_SHIFT 0
-#define BCHP_GIO_EC_EXT2_edge_config_DEFAULT 0x00000000
-
-/***************************************************************************
- *EI_EXT2 - GENERAL PURPOSE I/O EDGE INSENSITIVE FOR GPIO[111:96]
- ***************************************************************************/
-/* GIO :: EI_EXT2 :: reserved0 [31:16] */
-#define BCHP_GIO_EI_EXT2_reserved0_MASK 0xffff0000
-#define BCHP_GIO_EI_EXT2_reserved0_SHIFT 16
-
-/* GIO :: EI_EXT2 :: edge_insensitive [15:00] */
-#define BCHP_GIO_EI_EXT2_edge_insensitive_MASK 0x0000ffff
-#define BCHP_GIO_EI_EXT2_edge_insensitive_SHIFT 0
-#define BCHP_GIO_EI_EXT2_edge_insensitive_DEFAULT 0x00000000
-
-/***************************************************************************
- *MASK_EXT2 - GENERAL PURPOSE I/O INTERRUPT MASK FOR GPIO[111:96]
- ***************************************************************************/
-/* GIO :: MASK_EXT2 :: reserved0 [31:16] */
-#define BCHP_GIO_MASK_EXT2_reserved0_MASK 0xffff0000
-#define BCHP_GIO_MASK_EXT2_reserved0_SHIFT 16
-
-/* GIO :: MASK_EXT2 :: irq_mask [15:00] */
-#define BCHP_GIO_MASK_EXT2_irq_mask_MASK 0x0000ffff
-#define BCHP_GIO_MASK_EXT2_irq_mask_SHIFT 0
-#define BCHP_GIO_MASK_EXT2_irq_mask_DEFAULT 0x00000000
-
-/***************************************************************************
- *LEVEL_EXT2 - GENERAL PURPOSE I/O INTERRUPT TYPE FOR GPIO[111:96]
- ***************************************************************************/
-/* GIO :: LEVEL_EXT2 :: reserved0 [31:16] */
-#define BCHP_GIO_LEVEL_EXT2_reserved0_MASK 0xffff0000
-#define BCHP_GIO_LEVEL_EXT2_reserved0_SHIFT 16
-
-/* GIO :: LEVEL_EXT2 :: level [15:00] */
-#define BCHP_GIO_LEVEL_EXT2_level_MASK 0x0000ffff
-#define BCHP_GIO_LEVEL_EXT2_level_SHIFT 0
-#define BCHP_GIO_LEVEL_EXT2_level_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_EXT2 - GENERAL PURPOSE I/O INTERRUPT STATUS FOR GPIO[111:96]
- ***************************************************************************/
-/* GIO :: STAT_EXT2 :: reserved0 [31:16] */
-#define BCHP_GIO_STAT_EXT2_reserved0_MASK 0xffff0000
-#define BCHP_GIO_STAT_EXT2_reserved0_SHIFT 16
-
-/* GIO :: STAT_EXT2 :: irq_status [15:00] */
-#define BCHP_GIO_STAT_EXT2_irq_status_MASK 0x0000ffff
-#define BCHP_GIO_STAT_EXT2_irq_status_SHIFT 0
-#define BCHP_GIO_STAT_EXT2_irq_status_DEFAULT 0x00000000
-
-/***************************************************************************
- *ODEN_EXT - GENERAL PURPOSE I/O OPEN DRAIN ENABLE FOR AON_SGPIO[3:0] and SGPIO[5:0]
- ***************************************************************************/
-/* GIO :: ODEN_EXT :: reserved0 [31:10] */
-#define BCHP_GIO_ODEN_EXT_reserved0_MASK 0xfffffc00
-#define BCHP_GIO_ODEN_EXT_reserved0_SHIFT 10
-
-/* GIO :: ODEN_EXT :: oden [09:00] */
-#define BCHP_GIO_ODEN_EXT_oden_MASK 0x000003ff
-#define BCHP_GIO_ODEN_EXT_oden_SHIFT 0
-#define BCHP_GIO_ODEN_EXT_oden_DEFAULT 0x00000000
-
-/***************************************************************************
- *DATA_EXT - GENERAL PURPOSE I/O DATA FOR AON_SGPIO[3:0] and SGPIO[5:0]
- ***************************************************************************/
-/* GIO :: DATA_EXT :: reserved0 [31:10] */
-#define BCHP_GIO_DATA_EXT_reserved0_MASK 0xfffffc00
-#define BCHP_GIO_DATA_EXT_reserved0_SHIFT 10
-
-/* GIO :: DATA_EXT :: data [09:00] */
-#define BCHP_GIO_DATA_EXT_data_MASK 0x000003ff
-#define BCHP_GIO_DATA_EXT_data_SHIFT 0
-#define BCHP_GIO_DATA_EXT_data_DEFAULT 0x00000000
-
-/***************************************************************************
- *IODIR_EXT - GENERAL PURPOSE I/O DIRECTION FOR AON_SGPIO[3:0] and SGPIO[5:0]
- ***************************************************************************/
-/* GIO :: IODIR_EXT :: reserved0 [31:10] */
-#define BCHP_GIO_IODIR_EXT_reserved0_MASK 0xfffffc00
-#define BCHP_GIO_IODIR_EXT_reserved0_SHIFT 10
-
-/* GIO :: IODIR_EXT :: iodir [09:00] */
-#define BCHP_GIO_IODIR_EXT_iodir_MASK 0x000003ff
-#define BCHP_GIO_IODIR_EXT_iodir_SHIFT 0
-#define BCHP_GIO_IODIR_EXT_iodir_DEFAULT 0x000003ff
-
-/***************************************************************************
- *EC_EXT - GENERAL PURPOSE I/O EDGE CONFIGURATION FOR AON_SGPIO[3:0] and SGPIO[5:0]
- ***************************************************************************/
-/* GIO :: EC_EXT :: reserved0 [31:10] */
-#define BCHP_GIO_EC_EXT_reserved0_MASK 0xfffffc00
-#define BCHP_GIO_EC_EXT_reserved0_SHIFT 10
-
-/* GIO :: EC_EXT :: edge_config [09:00] */
-#define BCHP_GIO_EC_EXT_edge_config_MASK 0x000003ff
-#define BCHP_GIO_EC_EXT_edge_config_SHIFT 0
-#define BCHP_GIO_EC_EXT_edge_config_DEFAULT 0x00000000
-
-/***************************************************************************
- *EI_EXT - GENERAL PURPOSE I/O EDGE INSENSITIVE FOR AON_SGPIO[3:0] and SGPIO[5:0]
- ***************************************************************************/
-/* GIO :: EI_EXT :: reserved0 [31:10] */
-#define BCHP_GIO_EI_EXT_reserved0_MASK 0xfffffc00
-#define BCHP_GIO_EI_EXT_reserved0_SHIFT 10
-
-/* GIO :: EI_EXT :: edge_insensitive [09:00] */
-#define BCHP_GIO_EI_EXT_edge_insensitive_MASK 0x000003ff
-#define BCHP_GIO_EI_EXT_edge_insensitive_SHIFT 0
-#define BCHP_GIO_EI_EXT_edge_insensitive_DEFAULT 0x00000000
-
-/***************************************************************************
- *MASK_EXT - GENERAL PURPOSE I/O INTERRUPT MASK FOR AON_SGPIO[3:0] and SGPIO[5:0]
- ***************************************************************************/
-/* GIO :: MASK_EXT :: reserved0 [31:10] */
-#define BCHP_GIO_MASK_EXT_reserved0_MASK 0xfffffc00
-#define BCHP_GIO_MASK_EXT_reserved0_SHIFT 10
-
-/* GIO :: MASK_EXT :: irq_mask [09:00] */
-#define BCHP_GIO_MASK_EXT_irq_mask_MASK 0x000003ff
-#define BCHP_GIO_MASK_EXT_irq_mask_SHIFT 0
-#define BCHP_GIO_MASK_EXT_irq_mask_DEFAULT 0x00000000
-
-/***************************************************************************
- *LEVEL_EXT - GENERAL PURPOSE I/O INTERRUPT TYPE FOR AON_SGPIO[3:0] and SGPIO[5:0]
- ***************************************************************************/
-/* GIO :: LEVEL_EXT :: reserved0 [31:10] */
-#define BCHP_GIO_LEVEL_EXT_reserved0_MASK 0xfffffc00
-#define BCHP_GIO_LEVEL_EXT_reserved0_SHIFT 10
-
-/* GIO :: LEVEL_EXT :: level [09:00] */
-#define BCHP_GIO_LEVEL_EXT_level_MASK 0x000003ff
-#define BCHP_GIO_LEVEL_EXT_level_SHIFT 0
-#define BCHP_GIO_LEVEL_EXT_level_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_EXT - GENERAL PURPOSE I/O INTERRUPT STATUS FOR AON_SGPIO[3:0] and SGPIO[5:0]
- ***************************************************************************/
-/* GIO :: STAT_EXT :: reserved0 [31:10] */
-#define BCHP_GIO_STAT_EXT_reserved0_MASK 0xfffffc00
-#define BCHP_GIO_STAT_EXT_reserved0_SHIFT 10
-
-/* GIO :: STAT_EXT :: irq_status [09:00] */
-#define BCHP_GIO_STAT_EXT_irq_status_MASK 0x000003ff
-#define BCHP_GIO_STAT_EXT_irq_status_SHIFT 0
-#define BCHP_GIO_STAT_EXT_irq_status_DEFAULT 0x00000000
-
-#endif /* #ifndef BCHP_GIO_H__ */
-
-/* End of File */
diff --git a/include/linux/brcmstb/7439a0/bchp_gio_aon.h b/include/linux/brcmstb/7439a0/bchp_gio_aon.h
deleted file mode 100644
index d08d434..0000000
--- a/include/linux/brcmstb/7439a0/bchp_gio_aon.h
+++ /dev/null
@@ -1,256 +0,0 @@
-/***************************************************************************
- * Copyright (c) 1999-2013, Broadcom Corporation
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
- *
- * Module Description:
- * DO NOT EDIT THIS FILE DIRECTLY
- *
- * This module was generated magically with RDB from a source description
- * file. You must edit the source file for changes to be made to this file.
- *
- *
- * Date: Generated on Tue Apr 16 03:26:51 2013
- * MD5 Checksum d41d8cd98f00b204e9800998ecf8427e
- *
- * Compiled with: RDB Utility combo_header.pl
- * RDB Parser 3.0
- * unknown unknown
- * Perl Interpreter 5.008008
- * Operating System linux
- *
- * Revision History:
- *
- * $brcm_Log: $
- *
- ***************************************************************************/
-
-#ifndef BCHP_GIO_AON_H__
-#define BCHP_GIO_AON_H__
-
-/***************************************************************************
- *GIO_AON - GPIO
- ***************************************************************************/
-#define BCHP_GIO_AON_ODEN_LO 0x004114c0 /* GENERAL PURPOSE I/O OPEN DRAIN ENABLE FOR AON_GPIO[20:0] */
-#define BCHP_GIO_AON_DATA_LO 0x004114c4 /* GENERAL PURPOSE I/O DATA FOR AON_GPIO[20:0] */
-#define BCHP_GIO_AON_IODIR_LO 0x004114c8 /* GENERAL PURPOSE I/O DIRECTION FOR AON_GPIO[20:0] */
-#define BCHP_GIO_AON_EC_LO 0x004114cc /* GENERAL PURPOSE I/O EDGE CONFIGURATION FOR AON_GPIO[20:0] */
-#define BCHP_GIO_AON_EI_LO 0x004114d0 /* GENERAL PURPOSE I/O EDGE INSENSITIVE FOR AON_GPIO[20:0] */
-#define BCHP_GIO_AON_MASK_LO 0x004114d4 /* GENERAL PURPOSE I/O INTERRUPT MASK FOR AON_GPIO[20:0] */
-#define BCHP_GIO_AON_LEVEL_LO 0x004114d8 /* GENERAL PURPOSE I/O INTERRUPT TYPE FOR AON_GPIO[20:0] */
-#define BCHP_GIO_AON_STAT_LO 0x004114dc /* GENERAL PURPOSE I/O INTERRUPT STATUS FOR AON_GPIO[20:0] */
-#define BCHP_GIO_AON_ODEN_EXT 0x004114e0 /* GENERAL PURPOSE I/O OPEN DRAIN ENABLE FOR AON_SGPIO[7:4] */
-#define BCHP_GIO_AON_DATA_EXT 0x004114e4 /* GENERAL PURPOSE I/O DATA FOR AON_SGPIO[7:4] */
-#define BCHP_GIO_AON_IODIR_EXT 0x004114e8 /* GENERAL PURPOSE I/O DIRECTION FOR AON_SGPIO[7:4] */
-#define BCHP_GIO_AON_EC_EXT 0x004114ec /* GENERAL PURPOSE I/O EDGE CONFIGURATION FOR AON_SGPIO[7:4] */
-#define BCHP_GIO_AON_EI_EXT 0x004114f0 /* GENERAL PURPOSE I/O EDGE INSENSITIVE FOR AON_SGPIO[7:4] */
-#define BCHP_GIO_AON_MASK_EXT 0x004114f4 /* GENERAL PURPOSE I/O INTERRUPT MASK FOR AON_SGPIO[7:4] */
-#define BCHP_GIO_AON_LEVEL_EXT 0x004114f8 /* GENERAL PURPOSE I/O INTERRUPT TYPE FOR AON_SGPIO[7:4] */
-#define BCHP_GIO_AON_STAT_EXT 0x004114fc /* GENERAL PURPOSE I/O INTERRUPT STATUS FOR AON_SGPIO[7:4] */
-
-/***************************************************************************
- *ODEN_LO - GENERAL PURPOSE I/O OPEN DRAIN ENABLE FOR AON_GPIO[20:0]
- ***************************************************************************/
-/* GIO_AON :: ODEN_LO :: reserved0 [31:21] */
-#define BCHP_GIO_AON_ODEN_LO_reserved0_MASK 0xffe00000
-#define BCHP_GIO_AON_ODEN_LO_reserved0_SHIFT 21
-
-/* GIO_AON :: ODEN_LO :: oden [20:00] */
-#define BCHP_GIO_AON_ODEN_LO_oden_MASK 0x001fffff
-#define BCHP_GIO_AON_ODEN_LO_oden_SHIFT 0
-#define BCHP_GIO_AON_ODEN_LO_oden_DEFAULT 0x00000000
-
-/***************************************************************************
- *DATA_LO - GENERAL PURPOSE I/O DATA FOR AON_GPIO[20:0]
- ***************************************************************************/
-/* GIO_AON :: DATA_LO :: reserved0 [31:21] */
-#define BCHP_GIO_AON_DATA_LO_reserved0_MASK 0xffe00000
-#define BCHP_GIO_AON_DATA_LO_reserved0_SHIFT 21
-
-/* GIO_AON :: DATA_LO :: data [20:00] */
-#define BCHP_GIO_AON_DATA_LO_data_MASK 0x001fffff
-#define BCHP_GIO_AON_DATA_LO_data_SHIFT 0
-#define BCHP_GIO_AON_DATA_LO_data_DEFAULT 0x00000000
-
-/***************************************************************************
- *IODIR_LO - GENERAL PURPOSE I/O DIRECTION FOR AON_GPIO[20:0]
- ***************************************************************************/
-/* GIO_AON :: IODIR_LO :: reserved0 [31:21] */
-#define BCHP_GIO_AON_IODIR_LO_reserved0_MASK 0xffe00000
-#define BCHP_GIO_AON_IODIR_LO_reserved0_SHIFT 21
-
-/* GIO_AON :: IODIR_LO :: iodir [20:00] */
-#define BCHP_GIO_AON_IODIR_LO_iodir_MASK 0x001fffff
-#define BCHP_GIO_AON_IODIR_LO_iodir_SHIFT 0
-#define BCHP_GIO_AON_IODIR_LO_iodir_DEFAULT 0x001fffff
-
-/***************************************************************************
- *EC_LO - GENERAL PURPOSE I/O EDGE CONFIGURATION FOR AON_GPIO[20:0]
- ***************************************************************************/
-/* GIO_AON :: EC_LO :: reserved0 [31:21] */
-#define BCHP_GIO_AON_EC_LO_reserved0_MASK 0xffe00000
-#define BCHP_GIO_AON_EC_LO_reserved0_SHIFT 21
-
-/* GIO_AON :: EC_LO :: edge_config [20:00] */
-#define BCHP_GIO_AON_EC_LO_edge_config_MASK 0x001fffff
-#define BCHP_GIO_AON_EC_LO_edge_config_SHIFT 0
-#define BCHP_GIO_AON_EC_LO_edge_config_DEFAULT 0x00000000
-
-/***************************************************************************
- *EI_LO - GENERAL PURPOSE I/O EDGE INSENSITIVE FOR AON_GPIO[20:0]
- ***************************************************************************/
-/* GIO_AON :: EI_LO :: reserved0 [31:21] */
-#define BCHP_GIO_AON_EI_LO_reserved0_MASK 0xffe00000
-#define BCHP_GIO_AON_EI_LO_reserved0_SHIFT 21
-
-/* GIO_AON :: EI_LO :: edge_insensitive [20:00] */
-#define BCHP_GIO_AON_EI_LO_edge_insensitive_MASK 0x001fffff
-#define BCHP_GIO_AON_EI_LO_edge_insensitive_SHIFT 0
-#define BCHP_GIO_AON_EI_LO_edge_insensitive_DEFAULT 0x00000000
-
-/***************************************************************************
- *MASK_LO - GENERAL PURPOSE I/O INTERRUPT MASK FOR AON_GPIO[20:0]
- ***************************************************************************/
-/* GIO_AON :: MASK_LO :: reserved0 [31:21] */
-#define BCHP_GIO_AON_MASK_LO_reserved0_MASK 0xffe00000
-#define BCHP_GIO_AON_MASK_LO_reserved0_SHIFT 21
-
-/* GIO_AON :: MASK_LO :: irq_mask [20:00] */
-#define BCHP_GIO_AON_MASK_LO_irq_mask_MASK 0x001fffff
-#define BCHP_GIO_AON_MASK_LO_irq_mask_SHIFT 0
-#define BCHP_GIO_AON_MASK_LO_irq_mask_DEFAULT 0x00000000
-
-/***************************************************************************
- *LEVEL_LO - GENERAL PURPOSE I/O INTERRUPT TYPE FOR AON_GPIO[20:0]
- ***************************************************************************/
-/* GIO_AON :: LEVEL_LO :: reserved0 [31:21] */
-#define BCHP_GIO_AON_LEVEL_LO_reserved0_MASK 0xffe00000
-#define BCHP_GIO_AON_LEVEL_LO_reserved0_SHIFT 21
-
-/* GIO_AON :: LEVEL_LO :: level [20:00] */
-#define BCHP_GIO_AON_LEVEL_LO_level_MASK 0x001fffff
-#define BCHP_GIO_AON_LEVEL_LO_level_SHIFT 0
-#define BCHP_GIO_AON_LEVEL_LO_level_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_LO - GENERAL PURPOSE I/O INTERRUPT STATUS FOR AON_GPIO[20:0]
- ***************************************************************************/
-/* GIO_AON :: STAT_LO :: reserved0 [31:21] */
-#define BCHP_GIO_AON_STAT_LO_reserved0_MASK 0xffe00000
-#define BCHP_GIO_AON_STAT_LO_reserved0_SHIFT 21
-
-/* GIO_AON :: STAT_LO :: irq_status [20:00] */
-#define BCHP_GIO_AON_STAT_LO_irq_status_MASK 0x001fffff
-#define BCHP_GIO_AON_STAT_LO_irq_status_SHIFT 0
-#define BCHP_GIO_AON_STAT_LO_irq_status_DEFAULT 0x00000000
-
-/***************************************************************************
- *ODEN_EXT - GENERAL PURPOSE I/O OPEN DRAIN ENABLE FOR AON_SGPIO[7:4]
- ***************************************************************************/
-/* GIO_AON :: ODEN_EXT :: reserved0 [31:04] */
-#define BCHP_GIO_AON_ODEN_EXT_reserved0_MASK 0xfffffff0
-#define BCHP_GIO_AON_ODEN_EXT_reserved0_SHIFT 4
-
-/* GIO_AON :: ODEN_EXT :: oden [03:00] */
-#define BCHP_GIO_AON_ODEN_EXT_oden_MASK 0x0000000f
-#define BCHP_GIO_AON_ODEN_EXT_oden_SHIFT 0
-#define BCHP_GIO_AON_ODEN_EXT_oden_DEFAULT 0x00000000
-
-/***************************************************************************
- *DATA_EXT - GENERAL PURPOSE I/O DATA FOR AON_SGPIO[7:4]
- ***************************************************************************/
-/* GIO_AON :: DATA_EXT :: reserved0 [31:04] */
-#define BCHP_GIO_AON_DATA_EXT_reserved0_MASK 0xfffffff0
-#define BCHP_GIO_AON_DATA_EXT_reserved0_SHIFT 4
-
-/* GIO_AON :: DATA_EXT :: data [03:00] */
-#define BCHP_GIO_AON_DATA_EXT_data_MASK 0x0000000f
-#define BCHP_GIO_AON_DATA_EXT_data_SHIFT 0
-#define BCHP_GIO_AON_DATA_EXT_data_DEFAULT 0x00000000
-
-/***************************************************************************
- *IODIR_EXT - GENERAL PURPOSE I/O DIRECTION FOR AON_SGPIO[7:4]
- ***************************************************************************/
-/* GIO_AON :: IODIR_EXT :: reserved0 [31:04] */
-#define BCHP_GIO_AON_IODIR_EXT_reserved0_MASK 0xfffffff0
-#define BCHP_GIO_AON_IODIR_EXT_reserved0_SHIFT 4
-
-/* GIO_AON :: IODIR_EXT :: iodir [03:00] */
-#define BCHP_GIO_AON_IODIR_EXT_iodir_MASK 0x0000000f
-#define BCHP_GIO_AON_IODIR_EXT_iodir_SHIFT 0
-#define BCHP_GIO_AON_IODIR_EXT_iodir_DEFAULT 0x0000000f
-
-/***************************************************************************
- *EC_EXT - GENERAL PURPOSE I/O EDGE CONFIGURATION FOR AON_SGPIO[7:4]
- ***************************************************************************/
-/* GIO_AON :: EC_EXT :: reserved0 [31:04] */
-#define BCHP_GIO_AON_EC_EXT_reserved0_MASK 0xfffffff0
-#define BCHP_GIO_AON_EC_EXT_reserved0_SHIFT 4
-
-/* GIO_AON :: EC_EXT :: edge_config [03:00] */
-#define BCHP_GIO_AON_EC_EXT_edge_config_MASK 0x0000000f
-#define BCHP_GIO_AON_EC_EXT_edge_config_SHIFT 0
-#define BCHP_GIO_AON_EC_EXT_edge_config_DEFAULT 0x00000000
-
-/***************************************************************************
- *EI_EXT - GENERAL PURPOSE I/O EDGE INSENSITIVE FOR AON_SGPIO[7:4]
- ***************************************************************************/
-/* GIO_AON :: EI_EXT :: reserved0 [31:04] */
-#define BCHP_GIO_AON_EI_EXT_reserved0_MASK 0xfffffff0
-#define BCHP_GIO_AON_EI_EXT_reserved0_SHIFT 4
-
-/* GIO_AON :: EI_EXT :: edge_insensitive [03:00] */
-#define BCHP_GIO_AON_EI_EXT_edge_insensitive_MASK 0x0000000f
-#define BCHP_GIO_AON_EI_EXT_edge_insensitive_SHIFT 0
-#define BCHP_GIO_AON_EI_EXT_edge_insensitive_DEFAULT 0x00000000
-
-/***************************************************************************
- *MASK_EXT - GENERAL PURPOSE I/O INTERRUPT MASK FOR AON_SGPIO[7:4]
- ***************************************************************************/
-/* GIO_AON :: MASK_EXT :: reserved0 [31:04] */
-#define BCHP_GIO_AON_MASK_EXT_reserved0_MASK 0xfffffff0
-#define BCHP_GIO_AON_MASK_EXT_reserved0_SHIFT 4
-
-/* GIO_AON :: MASK_EXT :: irq_mask [03:00] */
-#define BCHP_GIO_AON_MASK_EXT_irq_mask_MASK 0x0000000f
-#define BCHP_GIO_AON_MASK_EXT_irq_mask_SHIFT 0
-#define BCHP_GIO_AON_MASK_EXT_irq_mask_DEFAULT 0x00000000
-
-/***************************************************************************
- *LEVEL_EXT - GENERAL PURPOSE I/O INTERRUPT TYPE FOR AON_SGPIO[7:4]
- ***************************************************************************/
-/* GIO_AON :: LEVEL_EXT :: reserved0 [31:04] */
-#define BCHP_GIO_AON_LEVEL_EXT_reserved0_MASK 0xfffffff0
-#define BCHP_GIO_AON_LEVEL_EXT_reserved0_SHIFT 4
-
-/* GIO_AON :: LEVEL_EXT :: level [03:00] */
-#define BCHP_GIO_AON_LEVEL_EXT_level_MASK 0x0000000f
-#define BCHP_GIO_AON_LEVEL_EXT_level_SHIFT 0
-#define BCHP_GIO_AON_LEVEL_EXT_level_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_EXT - GENERAL PURPOSE I/O INTERRUPT STATUS FOR AON_SGPIO[7:4]
- ***************************************************************************/
-/* GIO_AON :: STAT_EXT :: reserved0 [31:04] */
-#define BCHP_GIO_AON_STAT_EXT_reserved0_MASK 0xfffffff0
-#define BCHP_GIO_AON_STAT_EXT_reserved0_SHIFT 4
-
-/* GIO_AON :: STAT_EXT :: irq_status [03:00] */
-#define BCHP_GIO_AON_STAT_EXT_irq_status_MASK 0x0000000f
-#define BCHP_GIO_AON_STAT_EXT_irq_status_SHIFT 0
-#define BCHP_GIO_AON_STAT_EXT_irq_status_DEFAULT 0x00000000
-
-#endif /* #ifndef BCHP_GIO_AON_H__ */
-
-/* End of File */
diff --git a/include/linux/brcmstb/7439a0/bchp_hif_continuation.h b/include/linux/brcmstb/7439a0/bchp_hif_continuation.h
deleted file mode 100644
index 18ef137..0000000
--- a/include/linux/brcmstb/7439a0/bchp_hif_continuation.h
+++ /dev/null
@@ -1,114 +0,0 @@
-/***************************************************************************
- * Copyright (c) 1999-2013, Broadcom Corporation
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
- *
- * Module Description:
- * DO NOT EDIT THIS FILE DIRECTLY
- *
- * This module was generated magically with RDB from a source description
- * file. You must edit the source file for changes to be made to this file.
- *
- *
- * Date: Generated on Tue Apr 16 03:26:50 2013
- * MD5 Checksum d41d8cd98f00b204e9800998ecf8427e
- *
- * Compiled with: RDB Utility combo_header.pl
- * RDB Parser 3.0
- * unknown unknown
- * Perl Interpreter 5.008008
- * Operating System linux
- *
- * Revision History:
- *
- * $brcm_Log: $
- *
- ***************************************************************************/
-
-#ifndef BCHP_HIF_CONTINUATION_H__
-#define BCHP_HIF_CONTINUATION_H__
-
-/***************************************************************************
- *HIF_CONTINUATION - HIF Boot Continuation Registers
- ***************************************************************************/
-#define BCHP_HIF_CONTINUATION_STB_BOOT_HI_ADDR0 0x00462000 /* Higher 8-bit of HIF's Read-only STB Boot Continuation Address 0 Register */
-#define BCHP_HIF_CONTINUATION_STB_BOOT_ADDR0 0x00462004 /* Lower 32-bit of HIF's Read-only STB Boot Continuation Address 0 Register */
-#define BCHP_HIF_CONTINUATION_STB_BOOT_HI_ADDR1 0x00462008 /* Higher 8-bit of HIF's STB Boot Continuation Address 1 Register */
-#define BCHP_HIF_CONTINUATION_STB_BOOT_ADDR1 0x0046200c /* Lower 32-bit of HIF's STB Boot Continuation Address 1 Register */
-#define BCHP_HIF_CONTINUATION_WEB_BOOT_HI_ADDR0 0x004620f8 /* Higher 8-bit of HIF's WEB Boot Continuation Address 0 Register */
-#define BCHP_HIF_CONTINUATION_WEB_BOOT_ADDR0 0x004620fc /* Lower 32-bit of HIF's WEB Boot Continuation Address 0 Register */
-
-/***************************************************************************
- *STB_BOOT_HI_ADDR0 - Higher 8-bit of HIF's Read-only STB Boot Continuation Address 0 Register
- ***************************************************************************/
-/* HIF_CONTINUATION :: STB_BOOT_HI_ADDR0 :: reserved0 [31:08] */
-#define BCHP_HIF_CONTINUATION_STB_BOOT_HI_ADDR0_reserved0_MASK 0xffffff00
-#define BCHP_HIF_CONTINUATION_STB_BOOT_HI_ADDR0_reserved0_SHIFT 8
-
-/* HIF_CONTINUATION :: STB_BOOT_HI_ADDR0 :: ADDRESS [07:00] */
-#define BCHP_HIF_CONTINUATION_STB_BOOT_HI_ADDR0_ADDRESS_MASK 0x000000ff
-#define BCHP_HIF_CONTINUATION_STB_BOOT_HI_ADDR0_ADDRESS_SHIFT 0
-#define BCHP_HIF_CONTINUATION_STB_BOOT_HI_ADDR0_ADDRESS_DEFAULT 0x00000000
-
-/***************************************************************************
- *STB_BOOT_ADDR0 - Lower 32-bit of HIF's Read-only STB Boot Continuation Address 0 Register
- ***************************************************************************/
-/* HIF_CONTINUATION :: STB_BOOT_ADDR0 :: ADDRESS [31:00] */
-#define BCHP_HIF_CONTINUATION_STB_BOOT_ADDR0_ADDRESS_MASK 0xffffffff
-#define BCHP_HIF_CONTINUATION_STB_BOOT_ADDR0_ADDRESS_SHIFT 0
-#define BCHP_HIF_CONTINUATION_STB_BOOT_ADDR0_ADDRESS_DEFAULT 0xe0000000
-
-/***************************************************************************
- *STB_BOOT_HI_ADDR1 - Higher 8-bit of HIF's STB Boot Continuation Address 1 Register
- ***************************************************************************/
-/* HIF_CONTINUATION :: STB_BOOT_HI_ADDR1 :: reserved0 [31:08] */
-#define BCHP_HIF_CONTINUATION_STB_BOOT_HI_ADDR1_reserved0_MASK 0xffffff00
-#define BCHP_HIF_CONTINUATION_STB_BOOT_HI_ADDR1_reserved0_SHIFT 8
-
-/* HIF_CONTINUATION :: STB_BOOT_HI_ADDR1 :: ADDRESS [07:00] */
-#define BCHP_HIF_CONTINUATION_STB_BOOT_HI_ADDR1_ADDRESS_MASK 0x000000ff
-#define BCHP_HIF_CONTINUATION_STB_BOOT_HI_ADDR1_ADDRESS_SHIFT 0
-#define BCHP_HIF_CONTINUATION_STB_BOOT_HI_ADDR1_ADDRESS_DEFAULT 0x00000000
-
-/***************************************************************************
- *STB_BOOT_ADDR1 - Lower 32-bit of HIF's STB Boot Continuation Address 1 Register
- ***************************************************************************/
-/* HIF_CONTINUATION :: STB_BOOT_ADDR1 :: ADDRESS [31:00] */
-#define BCHP_HIF_CONTINUATION_STB_BOOT_ADDR1_ADDRESS_MASK 0xffffffff
-#define BCHP_HIF_CONTINUATION_STB_BOOT_ADDR1_ADDRESS_SHIFT 0
-#define BCHP_HIF_CONTINUATION_STB_BOOT_ADDR1_ADDRESS_DEFAULT 0xffff0000
-
-/***************************************************************************
- *WEB_BOOT_HI_ADDR0 - Higher 8-bit of HIF's WEB Boot Continuation Address 0 Register
- ***************************************************************************/
-/* HIF_CONTINUATION :: WEB_BOOT_HI_ADDR0 :: reserved0 [31:08] */
-#define BCHP_HIF_CONTINUATION_WEB_BOOT_HI_ADDR0_reserved0_MASK 0xffffff00
-#define BCHP_HIF_CONTINUATION_WEB_BOOT_HI_ADDR0_reserved0_SHIFT 8
-
-/* HIF_CONTINUATION :: WEB_BOOT_HI_ADDR0 :: ADDRESS [07:00] */
-#define BCHP_HIF_CONTINUATION_WEB_BOOT_HI_ADDR0_ADDRESS_MASK 0x000000ff
-#define BCHP_HIF_CONTINUATION_WEB_BOOT_HI_ADDR0_ADDRESS_SHIFT 0
-#define BCHP_HIF_CONTINUATION_WEB_BOOT_HI_ADDR0_ADDRESS_DEFAULT 0x00000000
-
-/***************************************************************************
- *WEB_BOOT_ADDR0 - Lower 32-bit of HIF's WEB Boot Continuation Address 0 Register
- ***************************************************************************/
-/* HIF_CONTINUATION :: WEB_BOOT_ADDR0 :: ADDRESS [31:00] */
-#define BCHP_HIF_CONTINUATION_WEB_BOOT_ADDR0_ADDRESS_MASK 0xffffffff
-#define BCHP_HIF_CONTINUATION_WEB_BOOT_ADDR0_ADDRESS_SHIFT 0
-#define BCHP_HIF_CONTINUATION_WEB_BOOT_ADDR0_ADDRESS_DEFAULT 0xffff0000
-
-#endif /* #ifndef BCHP_HIF_CONTINUATION_H__ */
-
-/* End of File */
diff --git a/include/linux/brcmstb/7439a0/bchp_hif_cpubiuctrl.h b/include/linux/brcmstb/7439a0/bchp_hif_cpubiuctrl.h
deleted file mode 100644
index 5fe945a..0000000
--- a/include/linux/brcmstb/7439a0/bchp_hif_cpubiuctrl.h
+++ /dev/null
@@ -1,3311 +0,0 @@
-/***************************************************************************
- * Copyright (c) 1999-2013, Broadcom Corporation
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
- *
- * Module Description:
- * DO NOT EDIT THIS FILE DIRECTLY
- *
- * This module was generated magically with RDB from a source description
- * file. You must edit the source file for changes to be made to this file.
- *
- *
- * Date: Generated on Tue Apr 16 03:26:50 2013
- * MD5 Checksum d41d8cd98f00b204e9800998ecf8427e
- *
- * Compiled with: RDB Utility combo_header.pl
- * RDB Parser 3.0
- * unknown unknown
- * Perl Interpreter 5.008008
- * Operating System linux
- *
- * Revision History:
- *
- * $brcm_Log: $
- *
- ***************************************************************************/
-
-#ifndef BCHP_HIF_CPUBIUCTRL_H__
-#define BCHP_HIF_CPUBIUCTRL_H__
-
-/***************************************************************************
- *HIF_CPUBIUCTRL - CPU BIU Control registers
- ***************************************************************************/
-#define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_ULIMT0 0x00442400 /* CPU Address Range0 Upper Limit Mapping Register */
-#define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_LLIMT0 0x00442404 /* CPU Address Range0 Lower Limit Mapping Register */
-#define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_ULIMT1 0x00442408 /* CPU Address Range1 Upper Limit Mapping Register */
-#define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_LLIMT1 0x0044240c /* CPU Address Range1 Lower Limit Mapping Register */
-#define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_ULIMT2 0x00442410 /* CPU Address Range2 Upper Limit Mapping Register */
-#define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_LLIMT2 0x00442414 /* CPU Address Range2 Lower Limit Mapping Register */
-#define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_ULIMT3 0x00442418 /* CPU Address Range3 Upper Limit Mapping Register */
-#define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_LLIMT3 0x0044241c /* CPU Address Range3 Lower Limit Mapping Register */
-#define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_ULIMT4 0x00442420 /* CPU Address Range4 Upper Limit Mapping Register */
-#define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_LLIMT4 0x00442424 /* CPU Address Range4 Lower Limit Mapping Register */
-#define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_ULIMT5 0x00442428 /* CPU Address Range5 Upper Limit Mapping Register */
-#define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_LLIMT5 0x0044242c /* CPU Address Range5 Lower Limit Mapping Register */
-#define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_ULIMT6 0x00442430 /* CPU Address Range6 Upper Limit Mapping Register */
-#define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_LLIMT6 0x00442434 /* CPU Address Range6 Lower Limit Mapping Register */
-#define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_ULIMT7 0x00442438 /* CPU Address Range7 Upper Limit Mapping Register */
-#define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_LLIMT7 0x0044243c /* CPU Address Range7 Lower Limit Mapping Register */
-#define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_ULIMT8 0x00442440 /* CPU Address Range8 Upper Limit Mapping Register */
-#define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_LLIMT8 0x00442444 /* CPU Address Range8 Lower Limit Mapping Register */
-#define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_ULIMT9 0x00442448 /* CPU Address Range9 Upper Limit Mapping Register */
-#define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_LLIMT9 0x0044244c /* CPU Address Range9 Lower Limit Mapping Register */
-#define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_ULIMT10 0x00442450 /* CPU Address Range10 Upper Limit Mapping Register */
-#define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_LLIMT10 0x00442454 /* CPU Address Range10 Lower Limit Mapping Register */
-#define BCHP_HIF_CPUBIUCTRL_SECURE_RESET_HNDSHAKE_REG 0x00442458 /* CPU Secure Soft Reset Handshake Register */
-#define BCHP_HIF_CPUBIUCTRL_SECURE_SOFT_RESET_REG 0x0044245c /* CPU Secure Soft Reset Register */
-#define BCHP_HIF_CPUBIUCTRL_CPU_ACCESS_RIGHT_VIOL_ADDR0 0x00442460 /* STB CPU Access Rights Violation Address0 Register */
-#define BCHP_HIF_CPUBIUCTRL_CPU_ACCESS_RIGHT_VIOL_UPPER_ADDR0 0x00442464 /* STB CPU Access Rights Violation Upper Address0 Register */
-#define BCHP_HIF_CPUBIUCTRL_CPU_ACCESS_RIGHT_VIOL_DETAIL_ADDR0 0x00442468 /* STB CPU Access Rights Violation Transaction Detail0 Register */
-#define BCHP_HIF_CPUBIUCTRL_CPU_ACCESS_RIGHT_VIOL_ADDR1 0x0044246c /* WEB CPU Access Rights Violation Address1 Register */
-#define BCHP_HIF_CPUBIUCTRL_CPU_ACCESS_RIGHT_VIOL_UPPER_ADDR1 0x00442470 /* WEB CPU Access Rights Violation Upper Address1 Register */
-#define BCHP_HIF_CPUBIUCTRL_CPU_ACCESS_RIGHT_VIOL_DETAIL_ADDR1 0x00442474 /* WEB CPU Access Rights Violation Transaction Detail1 Register */
-#define BCHP_HIF_CPUBIUCTRL_RAC_CONFIG0_REG 0x00442478 /* Read Ahead Cache Configuration0 Register */
-#define BCHP_HIF_CPUBIUCTRL_RAC_CONFIG1_REG 0x0044247c /* Read Ahead Cache Configuration1 Register */
-#define BCHP_HIF_CPUBIUCTRL_RAC_FLUSH_REG 0x00442480 /* Read Ahead Cache Flush Register */
-#define BCHP_HIF_CPUBIUCTRL_CPU_POWER_CONFIG_REG 0x00442484 /* CPU Power Configuration Register */
-#define BCHP_HIF_CPUBIUCTRL_CPU0_PWR_ZONE_CNTRL_REG 0x00442488 /* CPU0 Power Zone Control Register */
-#define BCHP_HIF_CPUBIUCTRL_CPU1_PWR_ZONE_CNTRL_REG 0x0044248c /* CPU1 Power Zone Control Register */
-#define BCHP_HIF_CPUBIUCTRL_CPU2_PWR_ZONE_CNTRL_REG 0x00442490 /* CPU2 Power Zone Control Register */
-#define BCHP_HIF_CPUBIUCTRL_CPU3_PWR_ZONE_CNTRL_REG 0x00442494 /* CPU3 Power Zone Control Register */
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_PWR_ZONE_CNTRL_REG 0x00442498 /* L2 and BIU Power Zone Control Register */
-#define BCHP_HIF_CPUBIUCTRL_CPU0_PWR_ZONE_CONFIG1_REG 0x0044249c /* CPU0 Power Zone Config1 Registers */
-#define BCHP_HIF_CPUBIUCTRL_CPU0_PWR_ZONE_CONFIG2_REG 0x004424a0 /* CPU0 Power Zone Config2 Registers */
-#define BCHP_HIF_CPUBIUCTRL_CPU1_PWR_ZONE_CONFIG1_REG 0x004424a4 /* CPU1 Power Zone Config1 Registers */
-#define BCHP_HIF_CPUBIUCTRL_CPU1_PWR_ZONE_CONFIG2_REG 0x004424a8 /* CPU1 Power Zone Config2 Registers */
-#define BCHP_HIF_CPUBIUCTRL_CPU2_PWR_ZONE_CONFIG1_REG 0x004424ac /* CPU2 Power Zone Config1 Registers */
-#define BCHP_HIF_CPUBIUCTRL_CPU2_PWR_ZONE_CONFIG2_REG 0x004424b0 /* CPU2 Power Zone Config2 Registers */
-#define BCHP_HIF_CPUBIUCTRL_CPU3_PWR_ZONE_CONFIG1_REG 0x004424b4 /* CPU3 Power Zone Config1 Registers */
-#define BCHP_HIF_CPUBIUCTRL_CPU3_PWR_ZONE_CONFIG2_REG 0x004424b8 /* CPU3 Power Zone Config2 Registers */
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_PWR_ZONE_CONFIG1_REG 0x004424bc /* L2/BIU Power Zone Config1 Registers */
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_PWR_ZONE_CONFIG2_REG 0x004424c0 /* L2/BIU Power Zone Config2 Registers */
-#define BCHP_HIF_CPUBIUCTRL_CPU0_PWR_FREQ_SCALAR_CTRL_REG 0x004424c4 /* CPU0 BPCM Frequency Scalar Control Register */
-#define BCHP_HIF_CPUBIUCTRL_CPU1_PWR_FREQ_SCALAR_CTRL_REG 0x004424c8 /* CPU1 BPCM Frequency Scalar Control Register */
-#define BCHP_HIF_CPUBIUCTRL_CPU2_PWR_FREQ_SCALAR_CTRL_REG 0x004424cc /* CPU2 BPCM Frequency Scalar Control Register */
-#define BCHP_HIF_CPUBIUCTRL_CPU3_PWR_FREQ_SCALAR_CTRL_REG 0x004424d0 /* CPU3 BPCM Frequency Scalar Control Register */
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_PWR_FREQ_SCALAR_CTRL_REG 0x004424d4 /* L2/BIU BPCM Frequency Scalar Control Register */
-#define BCHP_HIF_CPUBIUCTRL_CPU0_BPCM_ID 0x004424d8 /* CPU0 BPCM ID Register */
-#define BCHP_HIF_CPUBIUCTRL_CPU0_BPCM_CAPABILITY 0x004424dc /* CPU0 BPCM Capability Register */
-#define BCHP_HIF_CPUBIUCTRL_CPU0_BPCM_CONTROL 0x004424e0 /* CPU0 BPCM Control Register */
-#define BCHP_HIF_CPUBIUCTRL_CPU0_BPCM_STATUS 0x004424e4 /* CPU0 BPCM Status Register */
-#define BCHP_HIF_CPUBIUCTRL_CPU0_AVS_ROSC_CONTROL 0x004424e8 /* CPU0 Ring Oscillator Control Register */
-#define BCHP_HIF_CPUBIUCTRL_CPU0_AVS_ROSC_THRESHOLD 0x004424ec /* CPU0 Event Counter Threshold Register */
-#define BCHP_HIF_CPUBIUCTRL_CPU0_AVS_ROSC_COUNT 0x004424f0 /* CPU0 Event Counter Count Register */
-#define BCHP_HIF_CPUBIUCTRL_CPU0_AVS_PWD_CONTROL 0x004424f4 /* CPU0 PWD control Register */
-#define BCHP_HIF_CPUBIUCTRL_CPU1_BPCM_ID 0x004424f8 /* CPU1 BPCM ID Register */
-#define BCHP_HIF_CPUBIUCTRL_CPU1_BPCM_CAPABILITY 0x004424fc /* CPU1 BPCM Capability Register */
-#define BCHP_HIF_CPUBIUCTRL_CPU1_BPCM_CONTROL 0x00442500 /* CPU1 BPCM Control Register */
-#define BCHP_HIF_CPUBIUCTRL_CPU1_BPCM_STATUS 0x00442504 /* CPU1 BPCM Status Register */
-#define BCHP_HIF_CPUBIUCTRL_CPU1_AVS_ROSC_CONTROL 0x00442508 /* CPU1 Ring Oscillator Control Register */
-#define BCHP_HIF_CPUBIUCTRL_CPU1_AVS_ROSC_THRESHOLD 0x0044250c /* CPU1 Event Counter Threshold Register */
-#define BCHP_HIF_CPUBIUCTRL_CPU1_AVS_ROSC_COUNT 0x00442510 /* CPU1 Event Counter Count Register */
-#define BCHP_HIF_CPUBIUCTRL_CPU1_AVS_PWD_CONTROL 0x00442514 /* CPU1 PWD control Register */
-#define BCHP_HIF_CPUBIUCTRL_CPU2_BPCM_ID 0x00442518 /* CPU2 BPCM ID Register */
-#define BCHP_HIF_CPUBIUCTRL_CPU2_BPCM_CAPABILITY 0x0044251c /* CPU2 BPCM Capability Register */
-#define BCHP_HIF_CPUBIUCTRL_CPU2_BPCM_CONTROL 0x00442520 /* CPU2 BPCM Control Register */
-#define BCHP_HIF_CPUBIUCTRL_CPU2_BPCM_STATUS 0x00442524 /* CPU2 BPCM Status Register */
-#define BCHP_HIF_CPUBIUCTRL_CPU2_AVS_ROSC_CONTROL 0x00442528 /* CPU2 Ring Oscillator Control Register */
-#define BCHP_HIF_CPUBIUCTRL_CPU2_AVS_ROSC_THRESHOLD 0x0044252c /* CPU2 Event Counter Threshold Register */
-#define BCHP_HIF_CPUBIUCTRL_CPU2_AVS_ROSC_COUNT 0x00442530 /* CPU2 Event Counter Count Register */
-#define BCHP_HIF_CPUBIUCTRL_CPU2_AVS_PWD_CONTROL 0x00442534 /* CPU2 PWD control Register */
-#define BCHP_HIF_CPUBIUCTRL_CPU3_BPCM_ID 0x00442538 /* CPU3 BPCM ID Register */
-#define BCHP_HIF_CPUBIUCTRL_CPU3_BPCM_CAPABILITY 0x0044253c /* CPU3 BPCM Capability Register */
-#define BCHP_HIF_CPUBIUCTRL_CPU3_BPCM_CONTROL 0x00442540 /* CPU3 BPCM Control Register */
-#define BCHP_HIF_CPUBIUCTRL_CPU3_BPCM_STATUS 0x00442544 /* CPU3 BPCM Status Register */
-#define BCHP_HIF_CPUBIUCTRL_CPU3_AVS_ROSC_CONTROL 0x00442548 /* CPU3 Ring Oscillator Control Register */
-#define BCHP_HIF_CPUBIUCTRL_CPU3_AVS_ROSC_THRESHOLD 0x0044254c /* CPU3 Event Counter Threshold Register */
-#define BCHP_HIF_CPUBIUCTRL_CPU3_AVS_ROSC_COUNT 0x00442550 /* CPU3 Event Counter Count Register */
-#define BCHP_HIF_CPUBIUCTRL_CPU3_AVS_PWD_CONTROL 0x00442554 /* CPU3 PWD control Register */
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_BPCM_ID 0x00442558 /* L2BIU BPCM ID Register */
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_BPCM_CAPABILITY 0x0044255c /* L2BIU BPCM Capability Register */
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_BPCM_CONTROL 0x00442560 /* L2BIU BPCM Control Register */
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_BPCM_STATUS 0x00442564 /* L2BIU BPCM Status Register */
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_AVS_ROSC_CONTROL 0x00442568 /* L2BIU Ring Oscillator Control Register */
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_AVS_ROSC_THRESHOLD 0x0044256c /* L2BIU Event Counter Threshold Register */
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_AVS_ROSC_COUNT 0x00442570 /* L2BIU Event Counter Count Register */
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_AVS_PWD_CONTROL 0x00442574 /* L2BIU PWD control Register */
-#define BCHP_HIF_CPUBIUCTRL_CPU_RESET_CONFIG_REG 0x00442578 /* CPU Reset Configuration Register */
-#define BCHP_HIF_CPUBIUCTRL_CPU_CLOCK_CONFIG_REG 0x0044257c /* CPU Clock Configuration Register */
-#define BCHP_HIF_CPUBIUCTRL_CPU_MISC_CONFIG_REG 0x00442580 /* CPU Miscellaneous Configuration Register */
-#define BCHP_HIF_CPUBIUCTRL_CPU_CREDIT_REG 0x00442584 /* CPU Request Credit Register */
-#define BCHP_HIF_CPUBIUCTRL_CPU_THERM_THROTTLE_TEMP_REG 0x00442588 /* CPU Thermal Throttling IRQ Config Register */
-#define BCHP_HIF_CPUBIUCTRL_CPU_THERM_THROTTLE_IRQ_CONFIG_REG 0x0044258c /* CPU Thermal Throttling IRQ Config Register */
-#define BCHP_HIF_CPUBIUCTRL_CPU_THERM_IRQ_HIGH_REG 0x00442590 /* CPU Thermal Throttling IRQ High Register */
-#define BCHP_HIF_CPUBIUCTRL_CPU_THERM_IRQ_LOW_REG 0x00442594 /* CPU Thermal Throttling IRQ Low Register */
-#define BCHP_HIF_CPUBIUCTRL_CPU_THERM_MISC_THRESHOLD_REG 0x00442598 /* CPU Thermal Throttling Misc Threshold Register */
-#define BCHP_HIF_CPUBIUCTRL_CPU_THERM_IRQ_MISC_REG 0x0044259c /* CPU Thermal Throttling Misc IRQ Register */
-#define BCHP_HIF_CPUBIUCTRL_CPU_DEFEATURE_REG 0x004425a0 /* CPU Defeature Register */
-#define BCHP_HIF_CPUBIUCTRL_CPU_DEFEATURE_KEY_REG 0x004425a4 /* CPU Defeature Key Register */
-#define BCHP_HIF_CPUBIUCTRL_CPU_DEBUGROMADDR_REG 0x004425a8 /* CPU Debug ROM Address Register */
-#define BCHP_HIF_CPUBIUCTRL_CPU_DEBUGSELFADDR_REG 0x004425ac /* CPU Debug SELF Address Register */
-#define BCHP_HIF_CPUBIUCTRL_CPU_DEBUG_TRACECTRL_REG 0x004425b0 /* CPU Debug Trace Control Registeer */
-#define BCHP_HIF_CPUBIUCTRL_CPU_AXICONFIG_REG 0x004425b4 /* CPU AXI Config Register */
-#define BCHP_HIF_CPUBIUCTRL_CPU_REVISION_REG 0x004425b8 /* CPU Revision Register */
-#define BCHP_HIF_CPUBIUCTRL_CPU_SCRATCH_REG 0x004427fc /* Scratch Register */
-
-/***************************************************************************
- *CPU_BUS_RANGE_ULIMT0 - CPU Address Range0 Upper Limit Mapping Register
- ***************************************************************************/
-/* HIF_CPUBIUCTRL :: CPU_BUS_RANGE_ULIMT0 :: ULIMIT [31:04] */
-#define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_ULIMT0_ULIMIT_MASK 0xfffffff0
-#define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_ULIMT0_ULIMIT_SHIFT 4
-#define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_ULIMT0_ULIMIT_DEFAULT 0x000fffff
-
-/* HIF_CPUBIUCTRL :: CPU_BUS_RANGE_ULIMT0 :: BUSNUM [03:00] */
-#define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_ULIMT0_BUSNUM_MASK 0x0000000f
-#define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_ULIMT0_BUSNUM_SHIFT 0
-#define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_ULIMT0_BUSNUM_DEFAULT 0x00000002
-
-/***************************************************************************
- *CPU_BUS_RANGE_LLIMT0 - CPU Address Range0 Lower Limit Mapping Register
- ***************************************************************************/
-/* HIF_CPUBIUCTRL :: CPU_BUS_RANGE_LLIMT0 :: LLIMIT [31:04] */
-#define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_LLIMT0_LLIMIT_MASK 0xfffffff0
-#define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_LLIMT0_LLIMIT_SHIFT 4
-#define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_LLIMT0_LLIMIT_DEFAULT 0x000ffe00
-
-/* HIF_CPUBIUCTRL :: CPU_BUS_RANGE_LLIMT0 :: reserved0 [03:01] */
-#define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_LLIMT0_reserved0_MASK 0x0000000e
-#define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_LLIMT0_reserved0_SHIFT 1
-
-/* HIF_CPUBIUCTRL :: CPU_BUS_RANGE_LLIMT0 :: UBUSCDBIT [00:00] */
-#define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_LLIMT0_UBUSCDBIT_MASK 0x00000001
-#define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_LLIMT0_UBUSCDBIT_SHIFT 0
-#define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_LLIMT0_UBUSCDBIT_DEFAULT 0x00000000
-
-/***************************************************************************
- *CPU_BUS_RANGE_ULIMT1 - CPU Address Range1 Upper Limit Mapping Register
- ***************************************************************************/
-/* HIF_CPUBIUCTRL :: CPU_BUS_RANGE_ULIMT1 :: ULIMIT [31:04] */
-#define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_ULIMT1_ULIMIT_MASK 0xfffffff0
-#define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_ULIMT1_ULIMIT_SHIFT 4
-#define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_ULIMT1_ULIMIT_DEFAULT 0x000f1fff
-
-/* HIF_CPUBIUCTRL :: CPU_BUS_RANGE_ULIMT1 :: BUSNUM [03:00] */
-#define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_ULIMT1_BUSNUM_MASK 0x0000000f
-#define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_ULIMT1_BUSNUM_SHIFT 0
-#define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_ULIMT1_BUSNUM_DEFAULT 0x00000002
-
-/***************************************************************************
- *CPU_BUS_RANGE_LLIMT1 - CPU Address Range1 Lower Limit Mapping Register
- ***************************************************************************/
-/* HIF_CPUBIUCTRL :: CPU_BUS_RANGE_LLIMT1 :: LLIMIT [31:04] */
-#define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_LLIMT1_LLIMIT_MASK 0xfffffff0
-#define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_LLIMT1_LLIMIT_SHIFT 4
-#define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_LLIMT1_LLIMIT_DEFAULT 0x000c0000
-
-/* HIF_CPUBIUCTRL :: CPU_BUS_RANGE_LLIMT1 :: reserved0 [03:01] */
-#define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_LLIMT1_reserved0_MASK 0x0000000e
-#define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_LLIMT1_reserved0_SHIFT 1
-
-/* HIF_CPUBIUCTRL :: CPU_BUS_RANGE_LLIMT1 :: UBUSCDBIT [00:00] */
-#define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_LLIMT1_UBUSCDBIT_MASK 0x00000001
-#define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_LLIMT1_UBUSCDBIT_SHIFT 0
-#define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_LLIMT1_UBUSCDBIT_DEFAULT 0x00000000
-
-/***************************************************************************
- *CPU_BUS_RANGE_ULIMT2 - CPU Address Range2 Upper Limit Mapping Register
- ***************************************************************************/
-/* HIF_CPUBIUCTRL :: CPU_BUS_RANGE_ULIMT2 :: ULIMIT [31:04] */
-#define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_ULIMT2_ULIMIT_MASK 0xfffffff0
-#define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_ULIMT2_ULIMIT_SHIFT 4
-#define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_ULIMT2_ULIMIT_DEFAULT 0x00bfffff
-
-/* HIF_CPUBIUCTRL :: CPU_BUS_RANGE_ULIMT2 :: BUSNUM [03:00] */
-#define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_ULIMT2_BUSNUM_MASK 0x0000000f
-#define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_ULIMT2_BUSNUM_SHIFT 0
-#define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_ULIMT2_BUSNUM_DEFAULT 0x00000002
-
-/***************************************************************************
- *CPU_BUS_RANGE_LLIMT2 - CPU Address Range2 Lower Limit Mapping Register
- ***************************************************************************/
-/* HIF_CPUBIUCTRL :: CPU_BUS_RANGE_LLIMT2 :: LLIMIT [31:04] */
-#define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_LLIMT2_LLIMIT_MASK 0xfffffff0
-#define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_LLIMT2_LLIMIT_SHIFT 4
-#define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_LLIMT2_LLIMIT_DEFAULT 0x00600000
-
-/* HIF_CPUBIUCTRL :: CPU_BUS_RANGE_LLIMT2 :: reserved0 [03:01] */
-#define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_LLIMT2_reserved0_MASK 0x0000000e
-#define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_LLIMT2_reserved0_SHIFT 1
-
-/* HIF_CPUBIUCTRL :: CPU_BUS_RANGE_LLIMT2 :: UBUSCDBIT [00:00] */
-#define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_LLIMT2_UBUSCDBIT_MASK 0x00000001
-#define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_LLIMT2_UBUSCDBIT_SHIFT 0
-#define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_LLIMT2_UBUSCDBIT_DEFAULT 0x00000000
-
-/***************************************************************************
- *CPU_BUS_RANGE_ULIMT3 - CPU Address Range3 Upper Limit Mapping Register
- ***************************************************************************/
-/* HIF_CPUBIUCTRL :: CPU_BUS_RANGE_ULIMT3 :: ULIMIT [31:04] */
-#define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_ULIMT3_ULIMIT_MASK 0xfffffff0
-#define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_ULIMT3_ULIMIT_SHIFT 4
-#define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_ULIMT3_ULIMIT_DEFAULT 0x0003ffff
-
-/* HIF_CPUBIUCTRL :: CPU_BUS_RANGE_ULIMT3 :: BUSNUM [03:00] */
-#define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_ULIMT3_BUSNUM_MASK 0x0000000f
-#define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_ULIMT3_BUSNUM_SHIFT 0
-#define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_ULIMT3_BUSNUM_DEFAULT 0x00000004
-
-/***************************************************************************
- *CPU_BUS_RANGE_LLIMT3 - CPU Address Range3 Lower Limit Mapping Register
- ***************************************************************************/
-/* HIF_CPUBIUCTRL :: CPU_BUS_RANGE_LLIMT3 :: LLIMIT [31:04] */
-#define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_LLIMT3_LLIMIT_MASK 0xfffffff0
-#define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_LLIMT3_LLIMIT_SHIFT 4
-#define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_LLIMT3_LLIMIT_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: CPU_BUS_RANGE_LLIMT3 :: reserved0 [03:01] */
-#define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_LLIMT3_reserved0_MASK 0x0000000e
-#define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_LLIMT3_reserved0_SHIFT 1
-
-/* HIF_CPUBIUCTRL :: CPU_BUS_RANGE_LLIMT3 :: UBUSCDBIT [00:00] */
-#define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_LLIMT3_UBUSCDBIT_MASK 0x00000001
-#define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_LLIMT3_UBUSCDBIT_SHIFT 0
-#define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_LLIMT3_UBUSCDBIT_DEFAULT 0x00000000
-
-/***************************************************************************
- *CPU_BUS_RANGE_ULIMT4 - CPU Address Range4 Upper Limit Mapping Register
- ***************************************************************************/
-/* HIF_CPUBIUCTRL :: CPU_BUS_RANGE_ULIMT4 :: ULIMIT [31:04] */
-#define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_ULIMT4_ULIMIT_MASK 0xfffffff0
-#define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_ULIMT4_ULIMIT_SHIFT 4
-#define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_ULIMT4_ULIMIT_DEFAULT 0x001bffff
-
-/* HIF_CPUBIUCTRL :: CPU_BUS_RANGE_ULIMT4 :: BUSNUM [03:00] */
-#define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_ULIMT4_BUSNUM_MASK 0x0000000f
-#define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_ULIMT4_BUSNUM_SHIFT 0
-#define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_ULIMT4_BUSNUM_DEFAULT 0x00000004
-
-/***************************************************************************
- *CPU_BUS_RANGE_LLIMT4 - CPU Address Range4 Lower Limit Mapping Register
- ***************************************************************************/
-/* HIF_CPUBIUCTRL :: CPU_BUS_RANGE_LLIMT4 :: LLIMIT [31:04] */
-#define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_LLIMT4_LLIMIT_MASK 0xfffffff0
-#define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_LLIMT4_LLIMIT_SHIFT 4
-#define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_LLIMT4_LLIMIT_DEFAULT 0x00100000
-
-/* HIF_CPUBIUCTRL :: CPU_BUS_RANGE_LLIMT4 :: reserved0 [03:01] */
-#define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_LLIMT4_reserved0_MASK 0x0000000e
-#define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_LLIMT4_reserved0_SHIFT 1
-
-/* HIF_CPUBIUCTRL :: CPU_BUS_RANGE_LLIMT4 :: UBUSCDBIT [00:00] */
-#define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_LLIMT4_UBUSCDBIT_MASK 0x00000001
-#define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_LLIMT4_UBUSCDBIT_SHIFT 0
-#define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_LLIMT4_UBUSCDBIT_DEFAULT 0x00000000
-
-/***************************************************************************
- *CPU_BUS_RANGE_ULIMT5 - CPU Address Range5 Upper Limit Mapping Register
- ***************************************************************************/
-/* HIF_CPUBIUCTRL :: CPU_BUS_RANGE_ULIMT5 :: ULIMIT [31:04] */
-#define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_ULIMT5_ULIMIT_MASK 0xfffffff0
-#define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_ULIMT5_ULIMIT_SHIFT 4
-#define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_ULIMT5_ULIMIT_DEFAULT 0x0007ffff
-
-/* HIF_CPUBIUCTRL :: CPU_BUS_RANGE_ULIMT5 :: BUSNUM [03:00] */
-#define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_ULIMT5_BUSNUM_MASK 0x0000000f
-#define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_ULIMT5_BUSNUM_SHIFT 0
-#define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_ULIMT5_BUSNUM_DEFAULT 0x00000005
-
-/***************************************************************************
- *CPU_BUS_RANGE_LLIMT5 - CPU Address Range5 Lower Limit Mapping Register
- ***************************************************************************/
-/* HIF_CPUBIUCTRL :: CPU_BUS_RANGE_LLIMT5 :: LLIMIT [31:04] */
-#define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_LLIMT5_LLIMIT_MASK 0xfffffff0
-#define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_LLIMT5_LLIMIT_SHIFT 4
-#define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_LLIMT5_LLIMIT_DEFAULT 0x00040000
-
-/* HIF_CPUBIUCTRL :: CPU_BUS_RANGE_LLIMT5 :: reserved0 [03:01] */
-#define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_LLIMT5_reserved0_MASK 0x0000000e
-#define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_LLIMT5_reserved0_SHIFT 1
-
-/* HIF_CPUBIUCTRL :: CPU_BUS_RANGE_LLIMT5 :: UBUSCDBIT [00:00] */
-#define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_LLIMT5_UBUSCDBIT_MASK 0x00000001
-#define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_LLIMT5_UBUSCDBIT_SHIFT 0
-#define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_LLIMT5_UBUSCDBIT_DEFAULT 0x00000000
-
-/***************************************************************************
- *CPU_BUS_RANGE_ULIMT6 - CPU Address Range6 Upper Limit Mapping Register
- ***************************************************************************/
-/* HIF_CPUBIUCTRL :: CPU_BUS_RANGE_ULIMT6 :: ULIMIT [31:04] */
-#define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_ULIMT6_ULIMIT_MASK 0xfffffff0
-#define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_ULIMT6_ULIMIT_SHIFT 4
-#define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_ULIMT6_ULIMIT_DEFAULT 0x003bffff
-
-/* HIF_CPUBIUCTRL :: CPU_BUS_RANGE_ULIMT6 :: BUSNUM [03:00] */
-#define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_ULIMT6_BUSNUM_MASK 0x0000000f
-#define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_ULIMT6_BUSNUM_SHIFT 0
-#define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_ULIMT6_BUSNUM_DEFAULT 0x00000005
-
-/***************************************************************************
- *CPU_BUS_RANGE_LLIMT6 - CPU Address Range6 Lower Limit Mapping Register
- ***************************************************************************/
-/* HIF_CPUBIUCTRL :: CPU_BUS_RANGE_LLIMT6 :: LLIMIT [31:04] */
-#define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_LLIMT6_LLIMIT_MASK 0xfffffff0
-#define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_LLIMT6_LLIMIT_SHIFT 4
-#define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_LLIMT6_LLIMIT_DEFAULT 0x00300000
-
-/* HIF_CPUBIUCTRL :: CPU_BUS_RANGE_LLIMT6 :: reserved0 [03:01] */
-#define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_LLIMT6_reserved0_MASK 0x0000000e
-#define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_LLIMT6_reserved0_SHIFT 1
-
-/* HIF_CPUBIUCTRL :: CPU_BUS_RANGE_LLIMT6 :: UBUSCDBIT [00:00] */
-#define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_LLIMT6_UBUSCDBIT_MASK 0x00000001
-#define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_LLIMT6_UBUSCDBIT_SHIFT 0
-#define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_LLIMT6_UBUSCDBIT_DEFAULT 0x00000000
-
-/***************************************************************************
- *CPU_BUS_RANGE_ULIMT7 - CPU Address Range7 Upper Limit Mapping Register
- ***************************************************************************/
-/* HIF_CPUBIUCTRL :: CPU_BUS_RANGE_ULIMT7 :: ULIMIT [31:04] */
-#define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_ULIMT7_ULIMIT_MASK 0xfffffff0
-#define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_ULIMT7_ULIMIT_SHIFT 4
-#define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_ULIMT7_ULIMIT_DEFAULT 0x000bffff
-
-/* HIF_CPUBIUCTRL :: CPU_BUS_RANGE_ULIMT7 :: BUSNUM [03:00] */
-#define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_ULIMT7_BUSNUM_MASK 0x0000000f
-#define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_ULIMT7_BUSNUM_SHIFT 0
-#define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_ULIMT7_BUSNUM_DEFAULT 0x00000006
-
-/***************************************************************************
- *CPU_BUS_RANGE_LLIMT7 - CPU Address Range7 Lower Limit Mapping Register
- ***************************************************************************/
-/* HIF_CPUBIUCTRL :: CPU_BUS_RANGE_LLIMT7 :: LLIMIT [31:04] */
-#define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_LLIMT7_LLIMIT_MASK 0xfffffff0
-#define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_LLIMT7_LLIMIT_SHIFT 4
-#define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_LLIMT7_LLIMIT_DEFAULT 0x00080000
-
-/* HIF_CPUBIUCTRL :: CPU_BUS_RANGE_LLIMT7 :: reserved0 [03:01] */
-#define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_LLIMT7_reserved0_MASK 0x0000000e
-#define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_LLIMT7_reserved0_SHIFT 1
-
-/* HIF_CPUBIUCTRL :: CPU_BUS_RANGE_LLIMT7 :: UBUSCDBIT [00:00] */
-#define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_LLIMT7_UBUSCDBIT_MASK 0x00000001
-#define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_LLIMT7_UBUSCDBIT_SHIFT 0
-#define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_LLIMT7_UBUSCDBIT_DEFAULT 0x00000000
-
-/***************************************************************************
- *CPU_BUS_RANGE_ULIMT8 - CPU Address Range8 Upper Limit Mapping Register
- ***************************************************************************/
-/* HIF_CPUBIUCTRL :: CPU_BUS_RANGE_ULIMT8 :: ULIMIT [31:04] */
-#define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_ULIMT8_ULIMIT_MASK 0xfffffff0
-#define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_ULIMT8_ULIMIT_SHIFT 4
-#define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_ULIMT8_ULIMIT_DEFAULT 0x00cbffff
-
-/* HIF_CPUBIUCTRL :: CPU_BUS_RANGE_ULIMT8 :: BUSNUM [03:00] */
-#define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_ULIMT8_BUSNUM_MASK 0x0000000f
-#define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_ULIMT8_BUSNUM_SHIFT 0
-#define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_ULIMT8_BUSNUM_DEFAULT 0x00000006
-
-/***************************************************************************
- *CPU_BUS_RANGE_LLIMT8 - CPU Address Range8 Lower Limit Mapping Register
- ***************************************************************************/
-/* HIF_CPUBIUCTRL :: CPU_BUS_RANGE_LLIMT8 :: LLIMIT [31:04] */
-#define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_LLIMT8_LLIMIT_MASK 0xfffffff0
-#define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_LLIMT8_LLIMIT_SHIFT 4
-#define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_LLIMT8_LLIMIT_DEFAULT 0x00c00000
-
-/* HIF_CPUBIUCTRL :: CPU_BUS_RANGE_LLIMT8 :: reserved0 [03:01] */
-#define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_LLIMT8_reserved0_MASK 0x0000000e
-#define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_LLIMT8_reserved0_SHIFT 1
-
-/* HIF_CPUBIUCTRL :: CPU_BUS_RANGE_LLIMT8 :: UBUSCDBIT [00:00] */
-#define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_LLIMT8_UBUSCDBIT_MASK 0x00000001
-#define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_LLIMT8_UBUSCDBIT_SHIFT 0
-#define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_LLIMT8_UBUSCDBIT_DEFAULT 0x00000000
-
-/***************************************************************************
- *CPU_BUS_RANGE_ULIMT9 - CPU Address Range9 Upper Limit Mapping Register
- ***************************************************************************/
-/* HIF_CPUBIUCTRL :: CPU_BUS_RANGE_ULIMT9 :: ULIMIT [31:04] */
-#define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_ULIMT9_ULIMIT_MASK 0xfffffff0
-#define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_ULIMT9_ULIMIT_SHIFT 4
-#define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_ULIMT9_ULIMIT_DEFAULT 0x00dfffff
-
-/* HIF_CPUBIUCTRL :: CPU_BUS_RANGE_ULIMT9 :: BUSNUM [03:00] */
-#define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_ULIMT9_BUSNUM_MASK 0x0000000f
-#define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_ULIMT9_BUSNUM_SHIFT 0
-#define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_ULIMT9_BUSNUM_DEFAULT 0x00000000
-
-/***************************************************************************
- *CPU_BUS_RANGE_LLIMT9 - CPU Address Range9 Lower Limit Mapping Register
- ***************************************************************************/
-/* HIF_CPUBIUCTRL :: CPU_BUS_RANGE_LLIMT9 :: LLIMIT [31:04] */
-#define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_LLIMT9_LLIMIT_MASK 0xfffffff0
-#define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_LLIMT9_LLIMIT_SHIFT 4
-#define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_LLIMT9_LLIMIT_DEFAULT 0x00d00000
-
-/* HIF_CPUBIUCTRL :: CPU_BUS_RANGE_LLIMT9 :: reserved0 [03:01] */
-#define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_LLIMT9_reserved0_MASK 0x0000000e
-#define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_LLIMT9_reserved0_SHIFT 1
-
-/* HIF_CPUBIUCTRL :: CPU_BUS_RANGE_LLIMT9 :: UBUSCDBIT [00:00] */
-#define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_LLIMT9_UBUSCDBIT_MASK 0x00000001
-#define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_LLIMT9_UBUSCDBIT_SHIFT 0
-#define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_LLIMT9_UBUSCDBIT_DEFAULT 0x00000000
-
-/***************************************************************************
- *CPU_BUS_RANGE_ULIMT10 - CPU Address Range10 Upper Limit Mapping Register
- ***************************************************************************/
-/* HIF_CPUBIUCTRL :: CPU_BUS_RANGE_ULIMT10 :: ULIMIT [31:04] */
-#define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_ULIMT10_ULIMIT_MASK 0xfffffff0
-#define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_ULIMT10_ULIMIT_SHIFT 4
-#define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_ULIMT10_ULIMIT_DEFAULT 0x00efffff
-
-/* HIF_CPUBIUCTRL :: CPU_BUS_RANGE_ULIMT10 :: BUSNUM [03:00] */
-#define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_ULIMT10_BUSNUM_MASK 0x0000000f
-#define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_ULIMT10_BUSNUM_SHIFT 0
-#define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_ULIMT10_BUSNUM_DEFAULT 0x00000000
-
-/***************************************************************************
- *CPU_BUS_RANGE_LLIMT10 - CPU Address Range10 Lower Limit Mapping Register
- ***************************************************************************/
-/* HIF_CPUBIUCTRL :: CPU_BUS_RANGE_LLIMT10 :: LLIMIT [31:04] */
-#define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_LLIMT10_LLIMIT_MASK 0xfffffff0
-#define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_LLIMT10_LLIMIT_SHIFT 4
-#define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_LLIMT10_LLIMIT_DEFAULT 0x00e00000
-
-/* HIF_CPUBIUCTRL :: CPU_BUS_RANGE_LLIMT10 :: reserved0 [03:01] */
-#define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_LLIMT10_reserved0_MASK 0x0000000e
-#define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_LLIMT10_reserved0_SHIFT 1
-
-/* HIF_CPUBIUCTRL :: CPU_BUS_RANGE_LLIMT10 :: UBUSCDBIT [00:00] */
-#define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_LLIMT10_UBUSCDBIT_MASK 0x00000001
-#define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_LLIMT10_UBUSCDBIT_SHIFT 0
-#define BCHP_HIF_CPUBIUCTRL_CPU_BUS_RANGE_LLIMT10_UBUSCDBIT_DEFAULT 0x00000000
-
-/***************************************************************************
- *SECURE_RESET_HNDSHAKE_REG - CPU Secure Soft Reset Handshake Register
- ***************************************************************************/
-/* HIF_CPUBIUCTRL :: SECURE_RESET_HNDSHAKE_REG :: START [31:31] */
-#define BCHP_HIF_CPUBIUCTRL_SECURE_RESET_HNDSHAKE_REG_START_MASK 0x80000000
-#define BCHP_HIF_CPUBIUCTRL_SECURE_RESET_HNDSHAKE_REG_START_SHIFT 31
-#define BCHP_HIF_CPUBIUCTRL_SECURE_RESET_HNDSHAKE_REG_START_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: SECURE_RESET_HNDSHAKE_REG :: SW_DONE [30:30] */
-#define BCHP_HIF_CPUBIUCTRL_SECURE_RESET_HNDSHAKE_REG_SW_DONE_MASK 0x40000000
-#define BCHP_HIF_CPUBIUCTRL_SECURE_RESET_HNDSHAKE_REG_SW_DONE_SHIFT 30
-#define BCHP_HIF_CPUBIUCTRL_SECURE_RESET_HNDSHAKE_REG_SW_DONE_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: SECURE_RESET_HNDSHAKE_REG :: HW_DONE [29:29] */
-#define BCHP_HIF_CPUBIUCTRL_SECURE_RESET_HNDSHAKE_REG_HW_DONE_MASK 0x20000000
-#define BCHP_HIF_CPUBIUCTRL_SECURE_RESET_HNDSHAKE_REG_HW_DONE_SHIFT 29
-
-/* HIF_CPUBIUCTRL :: SECURE_RESET_HNDSHAKE_REG :: reserved0 [28:00] */
-#define BCHP_HIF_CPUBIUCTRL_SECURE_RESET_HNDSHAKE_REG_reserved0_MASK 0x1fffffff
-#define BCHP_HIF_CPUBIUCTRL_SECURE_RESET_HNDSHAKE_REG_reserved0_SHIFT 0
-
-/***************************************************************************
- *SECURE_SOFT_RESET_REG - CPU Secure Soft Reset Register
- ***************************************************************************/
-/* HIF_CPUBIUCTRL :: SECURE_SOFT_RESET_REG :: WEBCORES_SOFT_RESET [31:31] */
-#define BCHP_HIF_CPUBIUCTRL_SECURE_SOFT_RESET_REG_WEBCORES_SOFT_RESET_MASK 0x80000000
-#define BCHP_HIF_CPUBIUCTRL_SECURE_SOFT_RESET_REG_WEBCORES_SOFT_RESET_SHIFT 31
-#define BCHP_HIF_CPUBIUCTRL_SECURE_SOFT_RESET_REG_WEBCORES_SOFT_RESET_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: SECURE_SOFT_RESET_REG :: reserved0 [30:00] */
-#define BCHP_HIF_CPUBIUCTRL_SECURE_SOFT_RESET_REG_reserved0_MASK 0x7fffffff
-#define BCHP_HIF_CPUBIUCTRL_SECURE_SOFT_RESET_REG_reserved0_SHIFT 0
-
-/***************************************************************************
- *CPU_ACCESS_RIGHT_VIOL_ADDR0 - STB CPU Access Rights Violation Address0 Register
- ***************************************************************************/
-/* HIF_CPUBIUCTRL :: CPU_ACCESS_RIGHT_VIOL_ADDR0 :: VIOL_ADDR [31:00] */
-#define BCHP_HIF_CPUBIUCTRL_CPU_ACCESS_RIGHT_VIOL_ADDR0_VIOL_ADDR_MASK 0xffffffff
-#define BCHP_HIF_CPUBIUCTRL_CPU_ACCESS_RIGHT_VIOL_ADDR0_VIOL_ADDR_SHIFT 0
-#define BCHP_HIF_CPUBIUCTRL_CPU_ACCESS_RIGHT_VIOL_ADDR0_VIOL_ADDR_DEFAULT 0x00000000
-
-/***************************************************************************
- *CPU_ACCESS_RIGHT_VIOL_UPPER_ADDR0 - STB CPU Access Rights Violation Upper Address0 Register
- ***************************************************************************/
-/* HIF_CPUBIUCTRL :: CPU_ACCESS_RIGHT_VIOL_UPPER_ADDR0 :: reserved0 [31:08] */
-#define BCHP_HIF_CPUBIUCTRL_CPU_ACCESS_RIGHT_VIOL_UPPER_ADDR0_reserved0_MASK 0xffffff00
-#define BCHP_HIF_CPUBIUCTRL_CPU_ACCESS_RIGHT_VIOL_UPPER_ADDR0_reserved0_SHIFT 8
-
-/* HIF_CPUBIUCTRL :: CPU_ACCESS_RIGHT_VIOL_UPPER_ADDR0 :: VIOL_UPPER_ADDR [07:00] */
-#define BCHP_HIF_CPUBIUCTRL_CPU_ACCESS_RIGHT_VIOL_UPPER_ADDR0_VIOL_UPPER_ADDR_MASK 0x000000ff
-#define BCHP_HIF_CPUBIUCTRL_CPU_ACCESS_RIGHT_VIOL_UPPER_ADDR0_VIOL_UPPER_ADDR_SHIFT 0
-#define BCHP_HIF_CPUBIUCTRL_CPU_ACCESS_RIGHT_VIOL_UPPER_ADDR0_VIOL_UPPER_ADDR_DEFAULT 0x00000000
-
-/***************************************************************************
- *CPU_ACCESS_RIGHT_VIOL_DETAIL_ADDR0 - STB CPU Access Rights Violation Transaction Detail0 Register
- ***************************************************************************/
-/* HIF_CPUBIUCTRL :: CPU_ACCESS_RIGHT_VIOL_DETAIL_ADDR0 :: ERROR_VLD [31:31] */
-#define BCHP_HIF_CPUBIUCTRL_CPU_ACCESS_RIGHT_VIOL_DETAIL_ADDR0_ERROR_VLD_MASK 0x80000000
-#define BCHP_HIF_CPUBIUCTRL_CPU_ACCESS_RIGHT_VIOL_DETAIL_ADDR0_ERROR_VLD_SHIFT 31
-
-/* HIF_CPUBIUCTRL :: CPU_ACCESS_RIGHT_VIOL_DETAIL_ADDR0 :: reserved0 [30:30] */
-#define BCHP_HIF_CPUBIUCTRL_CPU_ACCESS_RIGHT_VIOL_DETAIL_ADDR0_reserved0_MASK 0x40000000
-#define BCHP_HIF_CPUBIUCTRL_CPU_ACCESS_RIGHT_VIOL_DETAIL_ADDR0_reserved0_SHIFT 30
-
-/* HIF_CPUBIUCTRL :: CPU_ACCESS_RIGHT_VIOL_DETAIL_ADDR0 :: CLUSTER_ID [29:26] */
-#define BCHP_HIF_CPUBIUCTRL_CPU_ACCESS_RIGHT_VIOL_DETAIL_ADDR0_CLUSTER_ID_MASK 0x3c000000
-#define BCHP_HIF_CPUBIUCTRL_CPU_ACCESS_RIGHT_VIOL_DETAIL_ADDR0_CLUSTER_ID_SHIFT 26
-
-/* HIF_CPUBIUCTRL :: CPU_ACCESS_RIGHT_VIOL_DETAIL_ADDR0 :: PROCESSOR_ID [25:24] */
-#define BCHP_HIF_CPUBIUCTRL_CPU_ACCESS_RIGHT_VIOL_DETAIL_ADDR0_PROCESSOR_ID_MASK 0x03000000
-#define BCHP_HIF_CPUBIUCTRL_CPU_ACCESS_RIGHT_VIOL_DETAIL_ADDR0_PROCESSOR_ID_SHIFT 24
-
-/* HIF_CPUBIUCTRL :: CPU_ACCESS_RIGHT_VIOL_DETAIL_ADDR0 :: reserved1 [23:23] */
-#define BCHP_HIF_CPUBIUCTRL_CPU_ACCESS_RIGHT_VIOL_DETAIL_ADDR0_reserved1_MASK 0x00800000
-#define BCHP_HIF_CPUBIUCTRL_CPU_ACCESS_RIGHT_VIOL_DETAIL_ADDR0_reserved1_SHIFT 23
-
-/* HIF_CPUBIUCTRL :: CPU_ACCESS_RIGHT_VIOL_DETAIL_ADDR0 :: INSTRUCTION_ACCESS [22:22] */
-#define BCHP_HIF_CPUBIUCTRL_CPU_ACCESS_RIGHT_VIOL_DETAIL_ADDR0_INSTRUCTION_ACCESS_MASK 0x00400000
-#define BCHP_HIF_CPUBIUCTRL_CPU_ACCESS_RIGHT_VIOL_DETAIL_ADDR0_INSTRUCTION_ACCESS_SHIFT 22
-
-/* HIF_CPUBIUCTRL :: CPU_ACCESS_RIGHT_VIOL_DETAIL_ADDR0 :: reserved2 [21:16] */
-#define BCHP_HIF_CPUBIUCTRL_CPU_ACCESS_RIGHT_VIOL_DETAIL_ADDR0_reserved2_MASK 0x003f0000
-#define BCHP_HIF_CPUBIUCTRL_CPU_ACCESS_RIGHT_VIOL_DETAIL_ADDR0_reserved2_SHIFT 16
-
-/* HIF_CPUBIUCTRL :: CPU_ACCESS_RIGHT_VIOL_DETAIL_ADDR0 :: REQUEST_SIZE [15:12] */
-#define BCHP_HIF_CPUBIUCTRL_CPU_ACCESS_RIGHT_VIOL_DETAIL_ADDR0_REQUEST_SIZE_MASK 0x0000f000
-#define BCHP_HIF_CPUBIUCTRL_CPU_ACCESS_RIGHT_VIOL_DETAIL_ADDR0_REQUEST_SIZE_SHIFT 12
-
-/* HIF_CPUBIUCTRL :: CPU_ACCESS_RIGHT_VIOL_DETAIL_ADDR0 :: UPPER_VIOL_ADDR [11:04] */
-#define BCHP_HIF_CPUBIUCTRL_CPU_ACCESS_RIGHT_VIOL_DETAIL_ADDR0_UPPER_VIOL_ADDR_MASK 0x00000ff0
-#define BCHP_HIF_CPUBIUCTRL_CPU_ACCESS_RIGHT_VIOL_DETAIL_ADDR0_UPPER_VIOL_ADDR_SHIFT 4
-#define BCHP_HIF_CPUBIUCTRL_CPU_ACCESS_RIGHT_VIOL_DETAIL_ADDR0_UPPER_VIOL_ADDR_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: CPU_ACCESS_RIGHT_VIOL_DETAIL_ADDR0 :: REQUEST_TYPE [03:00] */
-#define BCHP_HIF_CPUBIUCTRL_CPU_ACCESS_RIGHT_VIOL_DETAIL_ADDR0_REQUEST_TYPE_MASK 0x0000000f
-#define BCHP_HIF_CPUBIUCTRL_CPU_ACCESS_RIGHT_VIOL_DETAIL_ADDR0_REQUEST_TYPE_SHIFT 0
-
-/***************************************************************************
- *CPU_ACCESS_RIGHT_VIOL_ADDR1 - WEB CPU Access Rights Violation Address1 Register
- ***************************************************************************/
-/* HIF_CPUBIUCTRL :: CPU_ACCESS_RIGHT_VIOL_ADDR1 :: VIOL_ADDR [31:00] */
-#define BCHP_HIF_CPUBIUCTRL_CPU_ACCESS_RIGHT_VIOL_ADDR1_VIOL_ADDR_MASK 0xffffffff
-#define BCHP_HIF_CPUBIUCTRL_CPU_ACCESS_RIGHT_VIOL_ADDR1_VIOL_ADDR_SHIFT 0
-#define BCHP_HIF_CPUBIUCTRL_CPU_ACCESS_RIGHT_VIOL_ADDR1_VIOL_ADDR_DEFAULT 0x00000000
-
-/***************************************************************************
- *CPU_ACCESS_RIGHT_VIOL_UPPER_ADDR1 - WEB CPU Access Rights Violation Upper Address1 Register
- ***************************************************************************/
-/* HIF_CPUBIUCTRL :: CPU_ACCESS_RIGHT_VIOL_UPPER_ADDR1 :: reserved0 [31:08] */
-#define BCHP_HIF_CPUBIUCTRL_CPU_ACCESS_RIGHT_VIOL_UPPER_ADDR1_reserved0_MASK 0xffffff00
-#define BCHP_HIF_CPUBIUCTRL_CPU_ACCESS_RIGHT_VIOL_UPPER_ADDR1_reserved0_SHIFT 8
-
-/* HIF_CPUBIUCTRL :: CPU_ACCESS_RIGHT_VIOL_UPPER_ADDR1 :: VIOL_UPPER_ADDR [07:00] */
-#define BCHP_HIF_CPUBIUCTRL_CPU_ACCESS_RIGHT_VIOL_UPPER_ADDR1_VIOL_UPPER_ADDR_MASK 0x000000ff
-#define BCHP_HIF_CPUBIUCTRL_CPU_ACCESS_RIGHT_VIOL_UPPER_ADDR1_VIOL_UPPER_ADDR_SHIFT 0
-#define BCHP_HIF_CPUBIUCTRL_CPU_ACCESS_RIGHT_VIOL_UPPER_ADDR1_VIOL_UPPER_ADDR_DEFAULT 0x00000000
-
-/***************************************************************************
- *CPU_ACCESS_RIGHT_VIOL_DETAIL_ADDR1 - WEB CPU Access Rights Violation Transaction Detail1 Register
- ***************************************************************************/
-/* HIF_CPUBIUCTRL :: CPU_ACCESS_RIGHT_VIOL_DETAIL_ADDR1 :: ERROR_VLD [31:31] */
-#define BCHP_HIF_CPUBIUCTRL_CPU_ACCESS_RIGHT_VIOL_DETAIL_ADDR1_ERROR_VLD_MASK 0x80000000
-#define BCHP_HIF_CPUBIUCTRL_CPU_ACCESS_RIGHT_VIOL_DETAIL_ADDR1_ERROR_VLD_SHIFT 31
-
-/* HIF_CPUBIUCTRL :: CPU_ACCESS_RIGHT_VIOL_DETAIL_ADDR1 :: reserved0 [30:30] */
-#define BCHP_HIF_CPUBIUCTRL_CPU_ACCESS_RIGHT_VIOL_DETAIL_ADDR1_reserved0_MASK 0x40000000
-#define BCHP_HIF_CPUBIUCTRL_CPU_ACCESS_RIGHT_VIOL_DETAIL_ADDR1_reserved0_SHIFT 30
-
-/* HIF_CPUBIUCTRL :: CPU_ACCESS_RIGHT_VIOL_DETAIL_ADDR1 :: CLUSTER_ID [29:26] */
-#define BCHP_HIF_CPUBIUCTRL_CPU_ACCESS_RIGHT_VIOL_DETAIL_ADDR1_CLUSTER_ID_MASK 0x3c000000
-#define BCHP_HIF_CPUBIUCTRL_CPU_ACCESS_RIGHT_VIOL_DETAIL_ADDR1_CLUSTER_ID_SHIFT 26
-
-/* HIF_CPUBIUCTRL :: CPU_ACCESS_RIGHT_VIOL_DETAIL_ADDR1 :: PROCESSOR_ID [25:24] */
-#define BCHP_HIF_CPUBIUCTRL_CPU_ACCESS_RIGHT_VIOL_DETAIL_ADDR1_PROCESSOR_ID_MASK 0x03000000
-#define BCHP_HIF_CPUBIUCTRL_CPU_ACCESS_RIGHT_VIOL_DETAIL_ADDR1_PROCESSOR_ID_SHIFT 24
-
-/* HIF_CPUBIUCTRL :: CPU_ACCESS_RIGHT_VIOL_DETAIL_ADDR1 :: reserved1 [23:23] */
-#define BCHP_HIF_CPUBIUCTRL_CPU_ACCESS_RIGHT_VIOL_DETAIL_ADDR1_reserved1_MASK 0x00800000
-#define BCHP_HIF_CPUBIUCTRL_CPU_ACCESS_RIGHT_VIOL_DETAIL_ADDR1_reserved1_SHIFT 23
-
-/* HIF_CPUBIUCTRL :: CPU_ACCESS_RIGHT_VIOL_DETAIL_ADDR1 :: INSTRUCTION_ACCESS [22:22] */
-#define BCHP_HIF_CPUBIUCTRL_CPU_ACCESS_RIGHT_VIOL_DETAIL_ADDR1_INSTRUCTION_ACCESS_MASK 0x00400000
-#define BCHP_HIF_CPUBIUCTRL_CPU_ACCESS_RIGHT_VIOL_DETAIL_ADDR1_INSTRUCTION_ACCESS_SHIFT 22
-
-/* HIF_CPUBIUCTRL :: CPU_ACCESS_RIGHT_VIOL_DETAIL_ADDR1 :: reserved2 [21:16] */
-#define BCHP_HIF_CPUBIUCTRL_CPU_ACCESS_RIGHT_VIOL_DETAIL_ADDR1_reserved2_MASK 0x003f0000
-#define BCHP_HIF_CPUBIUCTRL_CPU_ACCESS_RIGHT_VIOL_DETAIL_ADDR1_reserved2_SHIFT 16
-
-/* HIF_CPUBIUCTRL :: CPU_ACCESS_RIGHT_VIOL_DETAIL_ADDR1 :: REQUEST_SIZE [15:12] */
-#define BCHP_HIF_CPUBIUCTRL_CPU_ACCESS_RIGHT_VIOL_DETAIL_ADDR1_REQUEST_SIZE_MASK 0x0000f000
-#define BCHP_HIF_CPUBIUCTRL_CPU_ACCESS_RIGHT_VIOL_DETAIL_ADDR1_REQUEST_SIZE_SHIFT 12
-
-/* HIF_CPUBIUCTRL :: CPU_ACCESS_RIGHT_VIOL_DETAIL_ADDR1 :: UPPER_VIOL_ADDR [11:04] */
-#define BCHP_HIF_CPUBIUCTRL_CPU_ACCESS_RIGHT_VIOL_DETAIL_ADDR1_UPPER_VIOL_ADDR_MASK 0x00000ff0
-#define BCHP_HIF_CPUBIUCTRL_CPU_ACCESS_RIGHT_VIOL_DETAIL_ADDR1_UPPER_VIOL_ADDR_SHIFT 4
-#define BCHP_HIF_CPUBIUCTRL_CPU_ACCESS_RIGHT_VIOL_DETAIL_ADDR1_UPPER_VIOL_ADDR_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: CPU_ACCESS_RIGHT_VIOL_DETAIL_ADDR1 :: REQUEST_TYPE [03:00] */
-#define BCHP_HIF_CPUBIUCTRL_CPU_ACCESS_RIGHT_VIOL_DETAIL_ADDR1_REQUEST_TYPE_MASK 0x0000000f
-#define BCHP_HIF_CPUBIUCTRL_CPU_ACCESS_RIGHT_VIOL_DETAIL_ADDR1_REQUEST_TYPE_SHIFT 0
-
-/***************************************************************************
- *RAC_CONFIG0_REG - Read Ahead Cache Configuration0 Register
- ***************************************************************************/
-/* HIF_CPUBIUCTRL :: RAC_CONFIG0_REG :: RACENDATA3 [31:30] */
-#define BCHP_HIF_CPUBIUCTRL_RAC_CONFIG0_REG_RACENDATA3_MASK 0xc0000000
-#define BCHP_HIF_CPUBIUCTRL_RAC_CONFIG0_REG_RACENDATA3_SHIFT 30
-#define BCHP_HIF_CPUBIUCTRL_RAC_CONFIG0_REG_RACENDATA3_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: RAC_CONFIG0_REG :: RACPREFDATA3 [29:28] */
-#define BCHP_HIF_CPUBIUCTRL_RAC_CONFIG0_REG_RACPREFDATA3_MASK 0x30000000
-#define BCHP_HIF_CPUBIUCTRL_RAC_CONFIG0_REG_RACPREFDATA3_SHIFT 28
-#define BCHP_HIF_CPUBIUCTRL_RAC_CONFIG0_REG_RACPREFDATA3_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: RAC_CONFIG0_REG :: RACENINST3 [27:26] */
-#define BCHP_HIF_CPUBIUCTRL_RAC_CONFIG0_REG_RACENINST3_MASK 0x0c000000
-#define BCHP_HIF_CPUBIUCTRL_RAC_CONFIG0_REG_RACENINST3_SHIFT 26
-#define BCHP_HIF_CPUBIUCTRL_RAC_CONFIG0_REG_RACENINST3_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: RAC_CONFIG0_REG :: RACPREFINST3 [25:24] */
-#define BCHP_HIF_CPUBIUCTRL_RAC_CONFIG0_REG_RACPREFINST3_MASK 0x03000000
-#define BCHP_HIF_CPUBIUCTRL_RAC_CONFIG0_REG_RACPREFINST3_SHIFT 24
-#define BCHP_HIF_CPUBIUCTRL_RAC_CONFIG0_REG_RACPREFINST3_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: RAC_CONFIG0_REG :: RACENDATA2 [23:22] */
-#define BCHP_HIF_CPUBIUCTRL_RAC_CONFIG0_REG_RACENDATA2_MASK 0x00c00000
-#define BCHP_HIF_CPUBIUCTRL_RAC_CONFIG0_REG_RACENDATA2_SHIFT 22
-#define BCHP_HIF_CPUBIUCTRL_RAC_CONFIG0_REG_RACENDATA2_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: RAC_CONFIG0_REG :: RACPREFDATA2 [21:20] */
-#define BCHP_HIF_CPUBIUCTRL_RAC_CONFIG0_REG_RACPREFDATA2_MASK 0x00300000
-#define BCHP_HIF_CPUBIUCTRL_RAC_CONFIG0_REG_RACPREFDATA2_SHIFT 20
-#define BCHP_HIF_CPUBIUCTRL_RAC_CONFIG0_REG_RACPREFDATA2_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: RAC_CONFIG0_REG :: RACENINST2 [19:18] */
-#define BCHP_HIF_CPUBIUCTRL_RAC_CONFIG0_REG_RACENINST2_MASK 0x000c0000
-#define BCHP_HIF_CPUBIUCTRL_RAC_CONFIG0_REG_RACENINST2_SHIFT 18
-#define BCHP_HIF_CPUBIUCTRL_RAC_CONFIG0_REG_RACENINST2_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: RAC_CONFIG0_REG :: RACPREFINST2 [17:16] */
-#define BCHP_HIF_CPUBIUCTRL_RAC_CONFIG0_REG_RACPREFINST2_MASK 0x00030000
-#define BCHP_HIF_CPUBIUCTRL_RAC_CONFIG0_REG_RACPREFINST2_SHIFT 16
-#define BCHP_HIF_CPUBIUCTRL_RAC_CONFIG0_REG_RACPREFINST2_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: RAC_CONFIG0_REG :: RACENDATA1 [15:14] */
-#define BCHP_HIF_CPUBIUCTRL_RAC_CONFIG0_REG_RACENDATA1_MASK 0x0000c000
-#define BCHP_HIF_CPUBIUCTRL_RAC_CONFIG0_REG_RACENDATA1_SHIFT 14
-#define BCHP_HIF_CPUBIUCTRL_RAC_CONFIG0_REG_RACENDATA1_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: RAC_CONFIG0_REG :: RACPREFDATA1 [13:12] */
-#define BCHP_HIF_CPUBIUCTRL_RAC_CONFIG0_REG_RACPREFDATA1_MASK 0x00003000
-#define BCHP_HIF_CPUBIUCTRL_RAC_CONFIG0_REG_RACPREFDATA1_SHIFT 12
-#define BCHP_HIF_CPUBIUCTRL_RAC_CONFIG0_REG_RACPREFDATA1_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: RAC_CONFIG0_REG :: RACENINST1 [11:10] */
-#define BCHP_HIF_CPUBIUCTRL_RAC_CONFIG0_REG_RACENINST1_MASK 0x00000c00
-#define BCHP_HIF_CPUBIUCTRL_RAC_CONFIG0_REG_RACENINST1_SHIFT 10
-#define BCHP_HIF_CPUBIUCTRL_RAC_CONFIG0_REG_RACENINST1_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: RAC_CONFIG0_REG :: RACPREFINST1 [09:08] */
-#define BCHP_HIF_CPUBIUCTRL_RAC_CONFIG0_REG_RACPREFINST1_MASK 0x00000300
-#define BCHP_HIF_CPUBIUCTRL_RAC_CONFIG0_REG_RACPREFINST1_SHIFT 8
-#define BCHP_HIF_CPUBIUCTRL_RAC_CONFIG0_REG_RACPREFINST1_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: RAC_CONFIG0_REG :: RACENDATA0 [07:06] */
-#define BCHP_HIF_CPUBIUCTRL_RAC_CONFIG0_REG_RACENDATA0_MASK 0x000000c0
-#define BCHP_HIF_CPUBIUCTRL_RAC_CONFIG0_REG_RACENDATA0_SHIFT 6
-#define BCHP_HIF_CPUBIUCTRL_RAC_CONFIG0_REG_RACENDATA0_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: RAC_CONFIG0_REG :: RACPREFDATA0 [05:04] */
-#define BCHP_HIF_CPUBIUCTRL_RAC_CONFIG0_REG_RACPREFDATA0_MASK 0x00000030
-#define BCHP_HIF_CPUBIUCTRL_RAC_CONFIG0_REG_RACPREFDATA0_SHIFT 4
-#define BCHP_HIF_CPUBIUCTRL_RAC_CONFIG0_REG_RACPREFDATA0_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: RAC_CONFIG0_REG :: RACENINST0 [03:02] */
-#define BCHP_HIF_CPUBIUCTRL_RAC_CONFIG0_REG_RACENINST0_MASK 0x0000000c
-#define BCHP_HIF_CPUBIUCTRL_RAC_CONFIG0_REG_RACENINST0_SHIFT 2
-#define BCHP_HIF_CPUBIUCTRL_RAC_CONFIG0_REG_RACENINST0_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: RAC_CONFIG0_REG :: RACPREFINST0 [01:00] */
-#define BCHP_HIF_CPUBIUCTRL_RAC_CONFIG0_REG_RACPREFINST0_MASK 0x00000003
-#define BCHP_HIF_CPUBIUCTRL_RAC_CONFIG0_REG_RACPREFINST0_SHIFT 0
-#define BCHP_HIF_CPUBIUCTRL_RAC_CONFIG0_REG_RACPREFINST0_DEFAULT 0x00000000
-
-/***************************************************************************
- *RAC_CONFIG1_REG - Read Ahead Cache Configuration1 Register
- ***************************************************************************/
-/* HIF_CPUBIUCTRL :: RAC_CONFIG1_REG :: reserved0 [31:09] */
-#define BCHP_HIF_CPUBIUCTRL_RAC_CONFIG1_REG_reserved0_MASK 0xfffffe00
-#define BCHP_HIF_CPUBIUCTRL_RAC_CONFIG1_REG_reserved0_SHIFT 9
-
-/* HIF_CPUBIUCTRL :: RAC_CONFIG1_REG :: RAC_TAG_ERROR_EN [08:08] */
-#define BCHP_HIF_CPUBIUCTRL_RAC_CONFIG1_REG_RAC_TAG_ERROR_EN_MASK 0x00000100
-#define BCHP_HIF_CPUBIUCTRL_RAC_CONFIG1_REG_RAC_TAG_ERROR_EN_SHIFT 8
-#define BCHP_HIF_CPUBIUCTRL_RAC_CONFIG1_REG_RAC_TAG_ERROR_EN_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: RAC_CONFIG1_REG :: RAC_TBD_CTRL7to6 [07:06] */
-#define BCHP_HIF_CPUBIUCTRL_RAC_CONFIG1_REG_RAC_TBD_CTRL7to6_MASK 0x000000c0
-#define BCHP_HIF_CPUBIUCTRL_RAC_CONFIG1_REG_RAC_TBD_CTRL7to6_SHIFT 6
-#define BCHP_HIF_CPUBIUCTRL_RAC_CONFIG1_REG_RAC_TBD_CTRL7to6_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: RAC_CONFIG1_REG :: RAC_FIFO_CTRL [05:04] */
-#define BCHP_HIF_CPUBIUCTRL_RAC_CONFIG1_REG_RAC_FIFO_CTRL_MASK 0x00000030
-#define BCHP_HIF_CPUBIUCTRL_RAC_CONFIG1_REG_RAC_FIFO_CTRL_SHIFT 4
-#define BCHP_HIF_CPUBIUCTRL_RAC_CONFIG1_REG_RAC_FIFO_CTRL_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: RAC_CONFIG1_REG :: RAC_TBD_CTRL3to1 [03:01] */
-#define BCHP_HIF_CPUBIUCTRL_RAC_CONFIG1_REG_RAC_TBD_CTRL3to1_MASK 0x0000000e
-#define BCHP_HIF_CPUBIUCTRL_RAC_CONFIG1_REG_RAC_TBD_CTRL3to1_SHIFT 1
-#define BCHP_HIF_CPUBIUCTRL_RAC_CONFIG1_REG_RAC_TBD_CTRL3to1_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: RAC_CONFIG1_REG :: UBUS_RAC_EN [00:00] */
-#define BCHP_HIF_CPUBIUCTRL_RAC_CONFIG1_REG_UBUS_RAC_EN_MASK 0x00000001
-#define BCHP_HIF_CPUBIUCTRL_RAC_CONFIG1_REG_UBUS_RAC_EN_SHIFT 0
-#define BCHP_HIF_CPUBIUCTRL_RAC_CONFIG1_REG_UBUS_RAC_EN_DEFAULT 0x00000000
-
-/***************************************************************************
- *RAC_FLUSH_REG - Read Ahead Cache Flush Register
- ***************************************************************************/
-/* HIF_CPUBIUCTRL :: RAC_FLUSH_REG :: reserved0 [31:01] */
-#define BCHP_HIF_CPUBIUCTRL_RAC_FLUSH_REG_reserved0_MASK 0xfffffffe
-#define BCHP_HIF_CPUBIUCTRL_RAC_FLUSH_REG_reserved0_SHIFT 1
-
-/* HIF_CPUBIUCTRL :: RAC_FLUSH_REG :: FLUSH_RAC [00:00] */
-#define BCHP_HIF_CPUBIUCTRL_RAC_FLUSH_REG_FLUSH_RAC_MASK 0x00000001
-#define BCHP_HIF_CPUBIUCTRL_RAC_FLUSH_REG_FLUSH_RAC_SHIFT 0
-#define BCHP_HIF_CPUBIUCTRL_RAC_FLUSH_REG_FLUSH_RAC_DEFAULT 0x00000000
-
-/***************************************************************************
- *CPU_POWER_CONFIG_REG - CPU Power Configuration Register
- ***************************************************************************/
-/* HIF_CPUBIUCTRL :: CPU_POWER_CONFIG_REG :: reserved0 [31:08] */
-#define BCHP_HIF_CPUBIUCTRL_CPU_POWER_CONFIG_REG_reserved0_MASK 0xffffff00
-#define BCHP_HIF_CPUBIUCTRL_CPU_POWER_CONFIG_REG_reserved0_SHIFT 8
-
-/* HIF_CPUBIUCTRL :: CPU_POWER_CONFIG_REG :: CPU3_BPCM_INIT_ON [07:07] */
-#define BCHP_HIF_CPUBIUCTRL_CPU_POWER_CONFIG_REG_CPU3_BPCM_INIT_ON_MASK 0x00000080
-#define BCHP_HIF_CPUBIUCTRL_CPU_POWER_CONFIG_REG_CPU3_BPCM_INIT_ON_SHIFT 7
-#define BCHP_HIF_CPUBIUCTRL_CPU_POWER_CONFIG_REG_CPU3_BPCM_INIT_ON_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: CPU_POWER_CONFIG_REG :: CPU2_BPCM_INIT_ON [06:06] */
-#define BCHP_HIF_CPUBIUCTRL_CPU_POWER_CONFIG_REG_CPU2_BPCM_INIT_ON_MASK 0x00000040
-#define BCHP_HIF_CPUBIUCTRL_CPU_POWER_CONFIG_REG_CPU2_BPCM_INIT_ON_SHIFT 6
-#define BCHP_HIF_CPUBIUCTRL_CPU_POWER_CONFIG_REG_CPU2_BPCM_INIT_ON_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: CPU_POWER_CONFIG_REG :: CPU1_BPCM_INIT_ON [05:05] */
-#define BCHP_HIF_CPUBIUCTRL_CPU_POWER_CONFIG_REG_CPU1_BPCM_INIT_ON_MASK 0x00000020
-#define BCHP_HIF_CPUBIUCTRL_CPU_POWER_CONFIG_REG_CPU1_BPCM_INIT_ON_SHIFT 5
-#define BCHP_HIF_CPUBIUCTRL_CPU_POWER_CONFIG_REG_CPU1_BPCM_INIT_ON_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: CPU_POWER_CONFIG_REG :: CPU0_BPCM_INIT_ON [04:04] */
-#define BCHP_HIF_CPUBIUCTRL_CPU_POWER_CONFIG_REG_CPU0_BPCM_INIT_ON_MASK 0x00000010
-#define BCHP_HIF_CPUBIUCTRL_CPU_POWER_CONFIG_REG_CPU0_BPCM_INIT_ON_SHIFT 4
-#define BCHP_HIF_CPUBIUCTRL_CPU_POWER_CONFIG_REG_CPU0_BPCM_INIT_ON_DEFAULT 0x00000001
-
-/* HIF_CPUBIUCTRL :: CPU_POWER_CONFIG_REG :: CPU3_BPCM_DIS [03:03] */
-#define BCHP_HIF_CPUBIUCTRL_CPU_POWER_CONFIG_REG_CPU3_BPCM_DIS_MASK 0x00000008
-#define BCHP_HIF_CPUBIUCTRL_CPU_POWER_CONFIG_REG_CPU3_BPCM_DIS_SHIFT 3
-#define BCHP_HIF_CPUBIUCTRL_CPU_POWER_CONFIG_REG_CPU3_BPCM_DIS_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: CPU_POWER_CONFIG_REG :: CPU2_BPCM_DIS [02:02] */
-#define BCHP_HIF_CPUBIUCTRL_CPU_POWER_CONFIG_REG_CPU2_BPCM_DIS_MASK 0x00000004
-#define BCHP_HIF_CPUBIUCTRL_CPU_POWER_CONFIG_REG_CPU2_BPCM_DIS_SHIFT 2
-#define BCHP_HIF_CPUBIUCTRL_CPU_POWER_CONFIG_REG_CPU2_BPCM_DIS_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: CPU_POWER_CONFIG_REG :: CPU1_BPCM_DIS [01:01] */
-#define BCHP_HIF_CPUBIUCTRL_CPU_POWER_CONFIG_REG_CPU1_BPCM_DIS_MASK 0x00000002
-#define BCHP_HIF_CPUBIUCTRL_CPU_POWER_CONFIG_REG_CPU1_BPCM_DIS_SHIFT 1
-#define BCHP_HIF_CPUBIUCTRL_CPU_POWER_CONFIG_REG_CPU1_BPCM_DIS_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: CPU_POWER_CONFIG_REG :: CPU0_BPCM_DIS [00:00] */
-#define BCHP_HIF_CPUBIUCTRL_CPU_POWER_CONFIG_REG_CPU0_BPCM_DIS_MASK 0x00000001
-#define BCHP_HIF_CPUBIUCTRL_CPU_POWER_CONFIG_REG_CPU0_BPCM_DIS_SHIFT 0
-#define BCHP_HIF_CPUBIUCTRL_CPU_POWER_CONFIG_REG_CPU0_BPCM_DIS_DEFAULT 0x00000000
-
-/***************************************************************************
- *CPU0_PWR_ZONE_CNTRL_REG - CPU0 Power Zone Control Register
- ***************************************************************************/
-/* HIF_CPUBIUCTRL :: CPU0_PWR_ZONE_CNTRL_REG :: ZONE_RESET_STATE [31:31] */
-#define BCHP_HIF_CPUBIUCTRL_CPU0_PWR_ZONE_CNTRL_REG_ZONE_RESET_STATE_MASK 0x80000000
-#define BCHP_HIF_CPUBIUCTRL_CPU0_PWR_ZONE_CNTRL_REG_ZONE_RESET_STATE_SHIFT 31
-
-/* HIF_CPUBIUCTRL :: CPU0_PWR_ZONE_CNTRL_REG :: ZONE_ISO_STATE [30:30] */
-#define BCHP_HIF_CPUBIUCTRL_CPU0_PWR_ZONE_CNTRL_REG_ZONE_ISO_STATE_MASK 0x40000000
-#define BCHP_HIF_CPUBIUCTRL_CPU0_PWR_ZONE_CNTRL_REG_ZONE_ISO_STATE_SHIFT 30
-
-/* HIF_CPUBIUCTRL :: CPU0_PWR_ZONE_CNTRL_REG :: ZONE_MEM_PWR_STATE [29:29] */
-#define BCHP_HIF_CPUBIUCTRL_CPU0_PWR_ZONE_CNTRL_REG_ZONE_MEM_PWR_STATE_MASK 0x20000000
-#define BCHP_HIF_CPUBIUCTRL_CPU0_PWR_ZONE_CNTRL_REG_ZONE_MEM_PWR_STATE_SHIFT 29
-
-/* HIF_CPUBIUCTRL :: CPU0_PWR_ZONE_CNTRL_REG :: ZONE_DPG_PWR_STATE [28:28] */
-#define BCHP_HIF_CPUBIUCTRL_CPU0_PWR_ZONE_CNTRL_REG_ZONE_DPG_PWR_STATE_MASK 0x10000000
-#define BCHP_HIF_CPUBIUCTRL_CPU0_PWR_ZONE_CNTRL_REG_ZONE_DPG_PWR_STATE_SHIFT 28
-
-/* HIF_CPUBIUCTRL :: CPU0_PWR_ZONE_CNTRL_REG :: ZONE_POWER_GOOD [27:27] */
-#define BCHP_HIF_CPUBIUCTRL_CPU0_PWR_ZONE_CNTRL_REG_ZONE_POWER_GOOD_MASK 0x08000000
-#define BCHP_HIF_CPUBIUCTRL_CPU0_PWR_ZONE_CNTRL_REG_ZONE_POWER_GOOD_SHIFT 27
-
-/* HIF_CPUBIUCTRL :: CPU0_PWR_ZONE_CNTRL_REG :: ZONE_PWR_ON_STATE [26:26] */
-#define BCHP_HIF_CPUBIUCTRL_CPU0_PWR_ZONE_CNTRL_REG_ZONE_PWR_ON_STATE_MASK 0x04000000
-#define BCHP_HIF_CPUBIUCTRL_CPU0_PWR_ZONE_CNTRL_REG_ZONE_PWR_ON_STATE_SHIFT 26
-
-/* HIF_CPUBIUCTRL :: CPU0_PWR_ZONE_CNTRL_REG :: ZONE_PWR_OFF_STATE [25:25] */
-#define BCHP_HIF_CPUBIUCTRL_CPU0_PWR_ZONE_CNTRL_REG_ZONE_PWR_OFF_STATE_MASK 0x02000000
-#define BCHP_HIF_CPUBIUCTRL_CPU0_PWR_ZONE_CNTRL_REG_ZONE_PWR_OFF_STATE_SHIFT 25
-
-/* HIF_CPUBIUCTRL :: CPU0_PWR_ZONE_CNTRL_REG :: FREQ_SCALAR_DYNAMIC_SEL [24:24] */
-#define BCHP_HIF_CPUBIUCTRL_CPU0_PWR_ZONE_CNTRL_REG_FREQ_SCALAR_DYNAMIC_SEL_MASK 0x01000000
-#define BCHP_HIF_CPUBIUCTRL_CPU0_PWR_ZONE_CNTRL_REG_FREQ_SCALAR_DYNAMIC_SEL_SHIFT 24
-
-/* HIF_CPUBIUCTRL :: CPU0_PWR_ZONE_CNTRL_REG :: ZONE_PWR_CNTL_STATE [23:19] */
-#define BCHP_HIF_CPUBIUCTRL_CPU0_PWR_ZONE_CNTRL_REG_ZONE_PWR_CNTL_STATE_MASK 0x00f80000
-#define BCHP_HIF_CPUBIUCTRL_CPU0_PWR_ZONE_CNTRL_REG_ZONE_PWR_CNTL_STATE_SHIFT 19
-
-/* HIF_CPUBIUCTRL :: CPU0_PWR_ZONE_CNTRL_REG :: reserved0 [18:14] */
-#define BCHP_HIF_CPUBIUCTRL_CPU0_PWR_ZONE_CNTRL_REG_reserved0_MASK 0x0007c000
-#define BCHP_HIF_CPUBIUCTRL_CPU0_PWR_ZONE_CNTRL_REG_reserved0_SHIFT 14
-
-/* HIF_CPUBIUCTRL :: CPU0_PWR_ZONE_CNTRL_REG :: ZONE_MEM_STBY [13:13] */
-#define BCHP_HIF_CPUBIUCTRL_CPU0_PWR_ZONE_CNTRL_REG_ZONE_MEM_STBY_MASK 0x00002000
-#define BCHP_HIF_CPUBIUCTRL_CPU0_PWR_ZONE_CNTRL_REG_ZONE_MEM_STBY_SHIFT 13
-
-/* HIF_CPUBIUCTRL :: CPU0_PWR_ZONE_CNTRL_REG :: ZONE_BLK_RST_ASSERT [12:12] */
-#define BCHP_HIF_CPUBIUCTRL_CPU0_PWR_ZONE_CNTRL_REG_ZONE_BLK_RST_ASSERT_MASK 0x00001000
-#define BCHP_HIF_CPUBIUCTRL_CPU0_PWR_ZONE_CNTRL_REG_ZONE_BLK_RST_ASSERT_SHIFT 12
-#define BCHP_HIF_CPUBIUCTRL_CPU0_PWR_ZONE_CNTRL_REG_ZONE_BLK_RST_ASSERT_DEFAULT 0x00000001
-
-/* HIF_CPUBIUCTRL :: CPU0_PWR_ZONE_CNTRL_REG :: ZONE_MEM_PWR_CNTL_EN [11:11] */
-#define BCHP_HIF_CPUBIUCTRL_CPU0_PWR_ZONE_CNTRL_REG_ZONE_MEM_PWR_CNTL_EN_MASK 0x00000800
-#define BCHP_HIF_CPUBIUCTRL_CPU0_PWR_ZONE_CNTRL_REG_ZONE_MEM_PWR_CNTL_EN_SHIFT 11
-#define BCHP_HIF_CPUBIUCTRL_CPU0_PWR_ZONE_CNTRL_REG_ZONE_MEM_PWR_CNTL_EN_DEFAULT 0x00000001
-
-/* HIF_CPUBIUCTRL :: CPU0_PWR_ZONE_CNTRL_REG :: ZONE_PWR_UP_REQ [10:10] */
-#define BCHP_HIF_CPUBIUCTRL_CPU0_PWR_ZONE_CNTRL_REG_ZONE_PWR_UP_REQ_MASK 0x00000400
-#define BCHP_HIF_CPUBIUCTRL_CPU0_PWR_ZONE_CNTRL_REG_ZONE_PWR_UP_REQ_SHIFT 10
-#define BCHP_HIF_CPUBIUCTRL_CPU0_PWR_ZONE_CNTRL_REG_ZONE_PWR_UP_REQ_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: CPU0_PWR_ZONE_CNTRL_REG :: ZONE_PWR_DN_REQ [09:09] */
-#define BCHP_HIF_CPUBIUCTRL_CPU0_PWR_ZONE_CNTRL_REG_ZONE_PWR_DN_REQ_MASK 0x00000200
-#define BCHP_HIF_CPUBIUCTRL_CPU0_PWR_ZONE_CNTRL_REG_ZONE_PWR_DN_REQ_SHIFT 9
-#define BCHP_HIF_CPUBIUCTRL_CPU0_PWR_ZONE_CNTRL_REG_ZONE_PWR_DN_REQ_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: CPU0_PWR_ZONE_CNTRL_REG :: ZONE_DPG_CNTL_EN [08:08] */
-#define BCHP_HIF_CPUBIUCTRL_CPU0_PWR_ZONE_CNTRL_REG_ZONE_DPG_CNTL_EN_MASK 0x00000100
-#define BCHP_HIF_CPUBIUCTRL_CPU0_PWR_ZONE_CNTRL_REG_ZONE_DPG_CNTL_EN_SHIFT 8
-#define BCHP_HIF_CPUBIUCTRL_CPU0_PWR_ZONE_CNTRL_REG_ZONE_DPG_CNTL_EN_DEFAULT 0x00000001
-
-/* HIF_CPUBIUCTRL :: CPU0_PWR_ZONE_CNTRL_REG :: ZONE_MANUAL_CONTROL [07:07] */
-#define BCHP_HIF_CPUBIUCTRL_CPU0_PWR_ZONE_CNTRL_REG_ZONE_MANUAL_CONTROL_MASK 0x00000080
-#define BCHP_HIF_CPUBIUCTRL_CPU0_PWR_ZONE_CNTRL_REG_ZONE_MANUAL_CONTROL_SHIFT 7
-#define BCHP_HIF_CPUBIUCTRL_CPU0_PWR_ZONE_CNTRL_REG_ZONE_MANUAL_CONTROL_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: CPU0_PWR_ZONE_CNTRL_REG :: ZONE_MAN_ISO_CNTL [06:06] */
-#define BCHP_HIF_CPUBIUCTRL_CPU0_PWR_ZONE_CNTRL_REG_ZONE_MAN_ISO_CNTL_MASK 0x00000040
-#define BCHP_HIF_CPUBIUCTRL_CPU0_PWR_ZONE_CNTRL_REG_ZONE_MAN_ISO_CNTL_SHIFT 6
-#define BCHP_HIF_CPUBIUCTRL_CPU0_PWR_ZONE_CNTRL_REG_ZONE_MAN_ISO_CNTL_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: CPU0_PWR_ZONE_CNTRL_REG :: reserved1 [05:05] */
-#define BCHP_HIF_CPUBIUCTRL_CPU0_PWR_ZONE_CNTRL_REG_reserved1_MASK 0x00000020
-#define BCHP_HIF_CPUBIUCTRL_CPU0_PWR_ZONE_CNTRL_REG_reserved1_SHIFT 5
-
-/* HIF_CPUBIUCTRL :: CPU0_PWR_ZONE_CNTRL_REG :: ZONE_MAN_MEM_PWR [04:04] */
-#define BCHP_HIF_CPUBIUCTRL_CPU0_PWR_ZONE_CNTRL_REG_ZONE_MAN_MEM_PWR_MASK 0x00000010
-#define BCHP_HIF_CPUBIUCTRL_CPU0_PWR_ZONE_CNTRL_REG_ZONE_MAN_MEM_PWR_SHIFT 4
-#define BCHP_HIF_CPUBIUCTRL_CPU0_PWR_ZONE_CNTRL_REG_ZONE_MAN_MEM_PWR_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: CPU0_PWR_ZONE_CNTRL_REG :: ZONE_DPG_CAPABLE [03:03] */
-#define BCHP_HIF_CPUBIUCTRL_CPU0_PWR_ZONE_CNTRL_REG_ZONE_DPG_CAPABLE_MASK 0x00000008
-#define BCHP_HIF_CPUBIUCTRL_CPU0_PWR_ZONE_CNTRL_REG_ZONE_DPG_CAPABLE_SHIFT 3
-
-/* HIF_CPUBIUCTRL :: CPU0_PWR_ZONE_CNTRL_REG :: ZONE_FREQ_SCALE_USED [02:02] */
-#define BCHP_HIF_CPUBIUCTRL_CPU0_PWR_ZONE_CNTRL_REG_ZONE_FREQ_SCALE_USED_MASK 0x00000004
-#define BCHP_HIF_CPUBIUCTRL_CPU0_PWR_ZONE_CNTRL_REG_ZONE_FREQ_SCALE_USED_SHIFT 2
-
-/* HIF_CPUBIUCTRL :: CPU0_PWR_ZONE_CNTRL_REG :: ZONE_MAN_RESET_CNTL [01:01] */
-#define BCHP_HIF_CPUBIUCTRL_CPU0_PWR_ZONE_CNTRL_REG_ZONE_MAN_RESET_CNTL_MASK 0x00000002
-#define BCHP_HIF_CPUBIUCTRL_CPU0_PWR_ZONE_CNTRL_REG_ZONE_MAN_RESET_CNTL_SHIFT 1
-#define BCHP_HIF_CPUBIUCTRL_CPU0_PWR_ZONE_CNTRL_REG_ZONE_MAN_RESET_CNTL_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: CPU0_PWR_ZONE_CNTRL_REG :: ZONE_MAN_CLKEN [00:00] */
-#define BCHP_HIF_CPUBIUCTRL_CPU0_PWR_ZONE_CNTRL_REG_ZONE_MAN_CLKEN_MASK 0x00000001
-#define BCHP_HIF_CPUBIUCTRL_CPU0_PWR_ZONE_CNTRL_REG_ZONE_MAN_CLKEN_SHIFT 0
-#define BCHP_HIF_CPUBIUCTRL_CPU0_PWR_ZONE_CNTRL_REG_ZONE_MAN_CLKEN_DEFAULT 0x00000000
-
-/***************************************************************************
- *CPU1_PWR_ZONE_CNTRL_REG - CPU1 Power Zone Control Register
- ***************************************************************************/
-/* HIF_CPUBIUCTRL :: CPU1_PWR_ZONE_CNTRL_REG :: ZONE_RESET_STATE [31:31] */
-#define BCHP_HIF_CPUBIUCTRL_CPU1_PWR_ZONE_CNTRL_REG_ZONE_RESET_STATE_MASK 0x80000000
-#define BCHP_HIF_CPUBIUCTRL_CPU1_PWR_ZONE_CNTRL_REG_ZONE_RESET_STATE_SHIFT 31
-
-/* HIF_CPUBIUCTRL :: CPU1_PWR_ZONE_CNTRL_REG :: ZONE_ISO_STATE [30:30] */
-#define BCHP_HIF_CPUBIUCTRL_CPU1_PWR_ZONE_CNTRL_REG_ZONE_ISO_STATE_MASK 0x40000000
-#define BCHP_HIF_CPUBIUCTRL_CPU1_PWR_ZONE_CNTRL_REG_ZONE_ISO_STATE_SHIFT 30
-
-/* HIF_CPUBIUCTRL :: CPU1_PWR_ZONE_CNTRL_REG :: ZONE_MEM_PWR_STATE [29:29] */
-#define BCHP_HIF_CPUBIUCTRL_CPU1_PWR_ZONE_CNTRL_REG_ZONE_MEM_PWR_STATE_MASK 0x20000000
-#define BCHP_HIF_CPUBIUCTRL_CPU1_PWR_ZONE_CNTRL_REG_ZONE_MEM_PWR_STATE_SHIFT 29
-
-/* HIF_CPUBIUCTRL :: CPU1_PWR_ZONE_CNTRL_REG :: ZONE_DPG_PWR_STATE [28:28] */
-#define BCHP_HIF_CPUBIUCTRL_CPU1_PWR_ZONE_CNTRL_REG_ZONE_DPG_PWR_STATE_MASK 0x10000000
-#define BCHP_HIF_CPUBIUCTRL_CPU1_PWR_ZONE_CNTRL_REG_ZONE_DPG_PWR_STATE_SHIFT 28
-
-/* HIF_CPUBIUCTRL :: CPU1_PWR_ZONE_CNTRL_REG :: ZONE_POWER_GOOD [27:27] */
-#define BCHP_HIF_CPUBIUCTRL_CPU1_PWR_ZONE_CNTRL_REG_ZONE_POWER_GOOD_MASK 0x08000000
-#define BCHP_HIF_CPUBIUCTRL_CPU1_PWR_ZONE_CNTRL_REG_ZONE_POWER_GOOD_SHIFT 27
-
-/* HIF_CPUBIUCTRL :: CPU1_PWR_ZONE_CNTRL_REG :: ZONE_PWR_ON_STATE [26:26] */
-#define BCHP_HIF_CPUBIUCTRL_CPU1_PWR_ZONE_CNTRL_REG_ZONE_PWR_ON_STATE_MASK 0x04000000
-#define BCHP_HIF_CPUBIUCTRL_CPU1_PWR_ZONE_CNTRL_REG_ZONE_PWR_ON_STATE_SHIFT 26
-
-/* HIF_CPUBIUCTRL :: CPU1_PWR_ZONE_CNTRL_REG :: ZONE_PWR_OFF_STATE [25:25] */
-#define BCHP_HIF_CPUBIUCTRL_CPU1_PWR_ZONE_CNTRL_REG_ZONE_PWR_OFF_STATE_MASK 0x02000000
-#define BCHP_HIF_CPUBIUCTRL_CPU1_PWR_ZONE_CNTRL_REG_ZONE_PWR_OFF_STATE_SHIFT 25
-
-/* HIF_CPUBIUCTRL :: CPU1_PWR_ZONE_CNTRL_REG :: FREQ_SCALAR_DYNAMIC_SEL [24:24] */
-#define BCHP_HIF_CPUBIUCTRL_CPU1_PWR_ZONE_CNTRL_REG_FREQ_SCALAR_DYNAMIC_SEL_MASK 0x01000000
-#define BCHP_HIF_CPUBIUCTRL_CPU1_PWR_ZONE_CNTRL_REG_FREQ_SCALAR_DYNAMIC_SEL_SHIFT 24
-
-/* HIF_CPUBIUCTRL :: CPU1_PWR_ZONE_CNTRL_REG :: ZONE_PWR_CNTL_STATE [23:19] */
-#define BCHP_HIF_CPUBIUCTRL_CPU1_PWR_ZONE_CNTRL_REG_ZONE_PWR_CNTL_STATE_MASK 0x00f80000
-#define BCHP_HIF_CPUBIUCTRL_CPU1_PWR_ZONE_CNTRL_REG_ZONE_PWR_CNTL_STATE_SHIFT 19
-
-/* HIF_CPUBIUCTRL :: CPU1_PWR_ZONE_CNTRL_REG :: reserved0 [18:14] */
-#define BCHP_HIF_CPUBIUCTRL_CPU1_PWR_ZONE_CNTRL_REG_reserved0_MASK 0x0007c000
-#define BCHP_HIF_CPUBIUCTRL_CPU1_PWR_ZONE_CNTRL_REG_reserved0_SHIFT 14
-
-/* HIF_CPUBIUCTRL :: CPU1_PWR_ZONE_CNTRL_REG :: ZONE_MEM_STBY [13:13] */
-#define BCHP_HIF_CPUBIUCTRL_CPU1_PWR_ZONE_CNTRL_REG_ZONE_MEM_STBY_MASK 0x00002000
-#define BCHP_HIF_CPUBIUCTRL_CPU1_PWR_ZONE_CNTRL_REG_ZONE_MEM_STBY_SHIFT 13
-
-/* HIF_CPUBIUCTRL :: CPU1_PWR_ZONE_CNTRL_REG :: ZONE_BLK_RST_ASSERT [12:12] */
-#define BCHP_HIF_CPUBIUCTRL_CPU1_PWR_ZONE_CNTRL_REG_ZONE_BLK_RST_ASSERT_MASK 0x00001000
-#define BCHP_HIF_CPUBIUCTRL_CPU1_PWR_ZONE_CNTRL_REG_ZONE_BLK_RST_ASSERT_SHIFT 12
-#define BCHP_HIF_CPUBIUCTRL_CPU1_PWR_ZONE_CNTRL_REG_ZONE_BLK_RST_ASSERT_DEFAULT 0x00000001
-
-/* HIF_CPUBIUCTRL :: CPU1_PWR_ZONE_CNTRL_REG :: ZONE_MEM_PWR_CNTL_EN [11:11] */
-#define BCHP_HIF_CPUBIUCTRL_CPU1_PWR_ZONE_CNTRL_REG_ZONE_MEM_PWR_CNTL_EN_MASK 0x00000800
-#define BCHP_HIF_CPUBIUCTRL_CPU1_PWR_ZONE_CNTRL_REG_ZONE_MEM_PWR_CNTL_EN_SHIFT 11
-#define BCHP_HIF_CPUBIUCTRL_CPU1_PWR_ZONE_CNTRL_REG_ZONE_MEM_PWR_CNTL_EN_DEFAULT 0x00000001
-
-/* HIF_CPUBIUCTRL :: CPU1_PWR_ZONE_CNTRL_REG :: ZONE_PWR_UP_REQ [10:10] */
-#define BCHP_HIF_CPUBIUCTRL_CPU1_PWR_ZONE_CNTRL_REG_ZONE_PWR_UP_REQ_MASK 0x00000400
-#define BCHP_HIF_CPUBIUCTRL_CPU1_PWR_ZONE_CNTRL_REG_ZONE_PWR_UP_REQ_SHIFT 10
-#define BCHP_HIF_CPUBIUCTRL_CPU1_PWR_ZONE_CNTRL_REG_ZONE_PWR_UP_REQ_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: CPU1_PWR_ZONE_CNTRL_REG :: ZONE_PWR_DN_REQ [09:09] */
-#define BCHP_HIF_CPUBIUCTRL_CPU1_PWR_ZONE_CNTRL_REG_ZONE_PWR_DN_REQ_MASK 0x00000200
-#define BCHP_HIF_CPUBIUCTRL_CPU1_PWR_ZONE_CNTRL_REG_ZONE_PWR_DN_REQ_SHIFT 9
-#define BCHP_HIF_CPUBIUCTRL_CPU1_PWR_ZONE_CNTRL_REG_ZONE_PWR_DN_REQ_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: CPU1_PWR_ZONE_CNTRL_REG :: ZONE_DPG_CNTL_EN [08:08] */
-#define BCHP_HIF_CPUBIUCTRL_CPU1_PWR_ZONE_CNTRL_REG_ZONE_DPG_CNTL_EN_MASK 0x00000100
-#define BCHP_HIF_CPUBIUCTRL_CPU1_PWR_ZONE_CNTRL_REG_ZONE_DPG_CNTL_EN_SHIFT 8
-#define BCHP_HIF_CPUBIUCTRL_CPU1_PWR_ZONE_CNTRL_REG_ZONE_DPG_CNTL_EN_DEFAULT 0x00000001
-
-/* HIF_CPUBIUCTRL :: CPU1_PWR_ZONE_CNTRL_REG :: ZONE_MANUAL_CONTROL [07:07] */
-#define BCHP_HIF_CPUBIUCTRL_CPU1_PWR_ZONE_CNTRL_REG_ZONE_MANUAL_CONTROL_MASK 0x00000080
-#define BCHP_HIF_CPUBIUCTRL_CPU1_PWR_ZONE_CNTRL_REG_ZONE_MANUAL_CONTROL_SHIFT 7
-#define BCHP_HIF_CPUBIUCTRL_CPU1_PWR_ZONE_CNTRL_REG_ZONE_MANUAL_CONTROL_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: CPU1_PWR_ZONE_CNTRL_REG :: ZONE_MAN_ISO_CNTL [06:06] */
-#define BCHP_HIF_CPUBIUCTRL_CPU1_PWR_ZONE_CNTRL_REG_ZONE_MAN_ISO_CNTL_MASK 0x00000040
-#define BCHP_HIF_CPUBIUCTRL_CPU1_PWR_ZONE_CNTRL_REG_ZONE_MAN_ISO_CNTL_SHIFT 6
-#define BCHP_HIF_CPUBIUCTRL_CPU1_PWR_ZONE_CNTRL_REG_ZONE_MAN_ISO_CNTL_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: CPU1_PWR_ZONE_CNTRL_REG :: reserved1 [05:05] */
-#define BCHP_HIF_CPUBIUCTRL_CPU1_PWR_ZONE_CNTRL_REG_reserved1_MASK 0x00000020
-#define BCHP_HIF_CPUBIUCTRL_CPU1_PWR_ZONE_CNTRL_REG_reserved1_SHIFT 5
-
-/* HIF_CPUBIUCTRL :: CPU1_PWR_ZONE_CNTRL_REG :: ZONE_MAN_MEM_PWR [04:04] */
-#define BCHP_HIF_CPUBIUCTRL_CPU1_PWR_ZONE_CNTRL_REG_ZONE_MAN_MEM_PWR_MASK 0x00000010
-#define BCHP_HIF_CPUBIUCTRL_CPU1_PWR_ZONE_CNTRL_REG_ZONE_MAN_MEM_PWR_SHIFT 4
-#define BCHP_HIF_CPUBIUCTRL_CPU1_PWR_ZONE_CNTRL_REG_ZONE_MAN_MEM_PWR_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: CPU1_PWR_ZONE_CNTRL_REG :: ZONE_DPG_CAPABLE [03:03] */
-#define BCHP_HIF_CPUBIUCTRL_CPU1_PWR_ZONE_CNTRL_REG_ZONE_DPG_CAPABLE_MASK 0x00000008
-#define BCHP_HIF_CPUBIUCTRL_CPU1_PWR_ZONE_CNTRL_REG_ZONE_DPG_CAPABLE_SHIFT 3
-
-/* HIF_CPUBIUCTRL :: CPU1_PWR_ZONE_CNTRL_REG :: ZONE_FREQ_SCALE_USED [02:02] */
-#define BCHP_HIF_CPUBIUCTRL_CPU1_PWR_ZONE_CNTRL_REG_ZONE_FREQ_SCALE_USED_MASK 0x00000004
-#define BCHP_HIF_CPUBIUCTRL_CPU1_PWR_ZONE_CNTRL_REG_ZONE_FREQ_SCALE_USED_SHIFT 2
-
-/* HIF_CPUBIUCTRL :: CPU1_PWR_ZONE_CNTRL_REG :: ZONE_MAN_RESET_CNTL [01:01] */
-#define BCHP_HIF_CPUBIUCTRL_CPU1_PWR_ZONE_CNTRL_REG_ZONE_MAN_RESET_CNTL_MASK 0x00000002
-#define BCHP_HIF_CPUBIUCTRL_CPU1_PWR_ZONE_CNTRL_REG_ZONE_MAN_RESET_CNTL_SHIFT 1
-#define BCHP_HIF_CPUBIUCTRL_CPU1_PWR_ZONE_CNTRL_REG_ZONE_MAN_RESET_CNTL_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: CPU1_PWR_ZONE_CNTRL_REG :: ZONE_MAN_CLKEN [00:00] */
-#define BCHP_HIF_CPUBIUCTRL_CPU1_PWR_ZONE_CNTRL_REG_ZONE_MAN_CLKEN_MASK 0x00000001
-#define BCHP_HIF_CPUBIUCTRL_CPU1_PWR_ZONE_CNTRL_REG_ZONE_MAN_CLKEN_SHIFT 0
-#define BCHP_HIF_CPUBIUCTRL_CPU1_PWR_ZONE_CNTRL_REG_ZONE_MAN_CLKEN_DEFAULT 0x00000000
-
-/***************************************************************************
- *CPU2_PWR_ZONE_CNTRL_REG - CPU2 Power Zone Control Register
- ***************************************************************************/
-/* HIF_CPUBIUCTRL :: CPU2_PWR_ZONE_CNTRL_REG :: ZONE_RESET_STATE [31:31] */
-#define BCHP_HIF_CPUBIUCTRL_CPU2_PWR_ZONE_CNTRL_REG_ZONE_RESET_STATE_MASK 0x80000000
-#define BCHP_HIF_CPUBIUCTRL_CPU2_PWR_ZONE_CNTRL_REG_ZONE_RESET_STATE_SHIFT 31
-
-/* HIF_CPUBIUCTRL :: CPU2_PWR_ZONE_CNTRL_REG :: ZONE_ISO_STATE [30:30] */
-#define BCHP_HIF_CPUBIUCTRL_CPU2_PWR_ZONE_CNTRL_REG_ZONE_ISO_STATE_MASK 0x40000000
-#define BCHP_HIF_CPUBIUCTRL_CPU2_PWR_ZONE_CNTRL_REG_ZONE_ISO_STATE_SHIFT 30
-
-/* HIF_CPUBIUCTRL :: CPU2_PWR_ZONE_CNTRL_REG :: ZONE_MEM_PWR_STATE [29:29] */
-#define BCHP_HIF_CPUBIUCTRL_CPU2_PWR_ZONE_CNTRL_REG_ZONE_MEM_PWR_STATE_MASK 0x20000000
-#define BCHP_HIF_CPUBIUCTRL_CPU2_PWR_ZONE_CNTRL_REG_ZONE_MEM_PWR_STATE_SHIFT 29
-
-/* HIF_CPUBIUCTRL :: CPU2_PWR_ZONE_CNTRL_REG :: ZONE_DPG_PWR_STATE [28:28] */
-#define BCHP_HIF_CPUBIUCTRL_CPU2_PWR_ZONE_CNTRL_REG_ZONE_DPG_PWR_STATE_MASK 0x10000000
-#define BCHP_HIF_CPUBIUCTRL_CPU2_PWR_ZONE_CNTRL_REG_ZONE_DPG_PWR_STATE_SHIFT 28
-
-/* HIF_CPUBIUCTRL :: CPU2_PWR_ZONE_CNTRL_REG :: ZONE_POWER_GOOD [27:27] */
-#define BCHP_HIF_CPUBIUCTRL_CPU2_PWR_ZONE_CNTRL_REG_ZONE_POWER_GOOD_MASK 0x08000000
-#define BCHP_HIF_CPUBIUCTRL_CPU2_PWR_ZONE_CNTRL_REG_ZONE_POWER_GOOD_SHIFT 27
-
-/* HIF_CPUBIUCTRL :: CPU2_PWR_ZONE_CNTRL_REG :: ZONE_PWR_ON_STATE [26:26] */
-#define BCHP_HIF_CPUBIUCTRL_CPU2_PWR_ZONE_CNTRL_REG_ZONE_PWR_ON_STATE_MASK 0x04000000
-#define BCHP_HIF_CPUBIUCTRL_CPU2_PWR_ZONE_CNTRL_REG_ZONE_PWR_ON_STATE_SHIFT 26
-
-/* HIF_CPUBIUCTRL :: CPU2_PWR_ZONE_CNTRL_REG :: ZONE_PWR_OFF_STATE [25:25] */
-#define BCHP_HIF_CPUBIUCTRL_CPU2_PWR_ZONE_CNTRL_REG_ZONE_PWR_OFF_STATE_MASK 0x02000000
-#define BCHP_HIF_CPUBIUCTRL_CPU2_PWR_ZONE_CNTRL_REG_ZONE_PWR_OFF_STATE_SHIFT 25
-
-/* HIF_CPUBIUCTRL :: CPU2_PWR_ZONE_CNTRL_REG :: FREQ_SCALAR_DYNAMIC_SEL [24:24] */
-#define BCHP_HIF_CPUBIUCTRL_CPU2_PWR_ZONE_CNTRL_REG_FREQ_SCALAR_DYNAMIC_SEL_MASK 0x01000000
-#define BCHP_HIF_CPUBIUCTRL_CPU2_PWR_ZONE_CNTRL_REG_FREQ_SCALAR_DYNAMIC_SEL_SHIFT 24
-
-/* HIF_CPUBIUCTRL :: CPU2_PWR_ZONE_CNTRL_REG :: ZONE_PWR_CNTL_STATE [23:19] */
-#define BCHP_HIF_CPUBIUCTRL_CPU2_PWR_ZONE_CNTRL_REG_ZONE_PWR_CNTL_STATE_MASK 0x00f80000
-#define BCHP_HIF_CPUBIUCTRL_CPU2_PWR_ZONE_CNTRL_REG_ZONE_PWR_CNTL_STATE_SHIFT 19
-
-/* HIF_CPUBIUCTRL :: CPU2_PWR_ZONE_CNTRL_REG :: reserved0 [18:14] */
-#define BCHP_HIF_CPUBIUCTRL_CPU2_PWR_ZONE_CNTRL_REG_reserved0_MASK 0x0007c000
-#define BCHP_HIF_CPUBIUCTRL_CPU2_PWR_ZONE_CNTRL_REG_reserved0_SHIFT 14
-
-/* HIF_CPUBIUCTRL :: CPU2_PWR_ZONE_CNTRL_REG :: ZONE_MEM_STBY [13:13] */
-#define BCHP_HIF_CPUBIUCTRL_CPU2_PWR_ZONE_CNTRL_REG_ZONE_MEM_STBY_MASK 0x00002000
-#define BCHP_HIF_CPUBIUCTRL_CPU2_PWR_ZONE_CNTRL_REG_ZONE_MEM_STBY_SHIFT 13
-
-/* HIF_CPUBIUCTRL :: CPU2_PWR_ZONE_CNTRL_REG :: ZONE_BLK_RST_ASSERT [12:12] */
-#define BCHP_HIF_CPUBIUCTRL_CPU2_PWR_ZONE_CNTRL_REG_ZONE_BLK_RST_ASSERT_MASK 0x00001000
-#define BCHP_HIF_CPUBIUCTRL_CPU2_PWR_ZONE_CNTRL_REG_ZONE_BLK_RST_ASSERT_SHIFT 12
-#define BCHP_HIF_CPUBIUCTRL_CPU2_PWR_ZONE_CNTRL_REG_ZONE_BLK_RST_ASSERT_DEFAULT 0x00000001
-
-/* HIF_CPUBIUCTRL :: CPU2_PWR_ZONE_CNTRL_REG :: ZONE_MEM_PWR_CNTL_EN [11:11] */
-#define BCHP_HIF_CPUBIUCTRL_CPU2_PWR_ZONE_CNTRL_REG_ZONE_MEM_PWR_CNTL_EN_MASK 0x00000800
-#define BCHP_HIF_CPUBIUCTRL_CPU2_PWR_ZONE_CNTRL_REG_ZONE_MEM_PWR_CNTL_EN_SHIFT 11
-#define BCHP_HIF_CPUBIUCTRL_CPU2_PWR_ZONE_CNTRL_REG_ZONE_MEM_PWR_CNTL_EN_DEFAULT 0x00000001
-
-/* HIF_CPUBIUCTRL :: CPU2_PWR_ZONE_CNTRL_REG :: ZONE_PWR_UP_REQ [10:10] */
-#define BCHP_HIF_CPUBIUCTRL_CPU2_PWR_ZONE_CNTRL_REG_ZONE_PWR_UP_REQ_MASK 0x00000400
-#define BCHP_HIF_CPUBIUCTRL_CPU2_PWR_ZONE_CNTRL_REG_ZONE_PWR_UP_REQ_SHIFT 10
-#define BCHP_HIF_CPUBIUCTRL_CPU2_PWR_ZONE_CNTRL_REG_ZONE_PWR_UP_REQ_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: CPU2_PWR_ZONE_CNTRL_REG :: ZONE_PWR_DN_REQ [09:09] */
-#define BCHP_HIF_CPUBIUCTRL_CPU2_PWR_ZONE_CNTRL_REG_ZONE_PWR_DN_REQ_MASK 0x00000200
-#define BCHP_HIF_CPUBIUCTRL_CPU2_PWR_ZONE_CNTRL_REG_ZONE_PWR_DN_REQ_SHIFT 9
-#define BCHP_HIF_CPUBIUCTRL_CPU2_PWR_ZONE_CNTRL_REG_ZONE_PWR_DN_REQ_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: CPU2_PWR_ZONE_CNTRL_REG :: ZONE_DPG_CNTL_EN [08:08] */
-#define BCHP_HIF_CPUBIUCTRL_CPU2_PWR_ZONE_CNTRL_REG_ZONE_DPG_CNTL_EN_MASK 0x00000100
-#define BCHP_HIF_CPUBIUCTRL_CPU2_PWR_ZONE_CNTRL_REG_ZONE_DPG_CNTL_EN_SHIFT 8
-#define BCHP_HIF_CPUBIUCTRL_CPU2_PWR_ZONE_CNTRL_REG_ZONE_DPG_CNTL_EN_DEFAULT 0x00000001
-
-/* HIF_CPUBIUCTRL :: CPU2_PWR_ZONE_CNTRL_REG :: ZONE_MANUAL_CONTROL [07:07] */
-#define BCHP_HIF_CPUBIUCTRL_CPU2_PWR_ZONE_CNTRL_REG_ZONE_MANUAL_CONTROL_MASK 0x00000080
-#define BCHP_HIF_CPUBIUCTRL_CPU2_PWR_ZONE_CNTRL_REG_ZONE_MANUAL_CONTROL_SHIFT 7
-#define BCHP_HIF_CPUBIUCTRL_CPU2_PWR_ZONE_CNTRL_REG_ZONE_MANUAL_CONTROL_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: CPU2_PWR_ZONE_CNTRL_REG :: ZONE_MAN_ISO_CNTL [06:06] */
-#define BCHP_HIF_CPUBIUCTRL_CPU2_PWR_ZONE_CNTRL_REG_ZONE_MAN_ISO_CNTL_MASK 0x00000040
-#define BCHP_HIF_CPUBIUCTRL_CPU2_PWR_ZONE_CNTRL_REG_ZONE_MAN_ISO_CNTL_SHIFT 6
-#define BCHP_HIF_CPUBIUCTRL_CPU2_PWR_ZONE_CNTRL_REG_ZONE_MAN_ISO_CNTL_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: CPU2_PWR_ZONE_CNTRL_REG :: reserved1 [05:05] */
-#define BCHP_HIF_CPUBIUCTRL_CPU2_PWR_ZONE_CNTRL_REG_reserved1_MASK 0x00000020
-#define BCHP_HIF_CPUBIUCTRL_CPU2_PWR_ZONE_CNTRL_REG_reserved1_SHIFT 5
-
-/* HIF_CPUBIUCTRL :: CPU2_PWR_ZONE_CNTRL_REG :: ZONE_MAN_MEM_PWR [04:04] */
-#define BCHP_HIF_CPUBIUCTRL_CPU2_PWR_ZONE_CNTRL_REG_ZONE_MAN_MEM_PWR_MASK 0x00000010
-#define BCHP_HIF_CPUBIUCTRL_CPU2_PWR_ZONE_CNTRL_REG_ZONE_MAN_MEM_PWR_SHIFT 4
-#define BCHP_HIF_CPUBIUCTRL_CPU2_PWR_ZONE_CNTRL_REG_ZONE_MAN_MEM_PWR_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: CPU2_PWR_ZONE_CNTRL_REG :: ZONE_DPG_CAPABLE [03:03] */
-#define BCHP_HIF_CPUBIUCTRL_CPU2_PWR_ZONE_CNTRL_REG_ZONE_DPG_CAPABLE_MASK 0x00000008
-#define BCHP_HIF_CPUBIUCTRL_CPU2_PWR_ZONE_CNTRL_REG_ZONE_DPG_CAPABLE_SHIFT 3
-
-/* HIF_CPUBIUCTRL :: CPU2_PWR_ZONE_CNTRL_REG :: ZONE_FREQ_SCALE_USED [02:02] */
-#define BCHP_HIF_CPUBIUCTRL_CPU2_PWR_ZONE_CNTRL_REG_ZONE_FREQ_SCALE_USED_MASK 0x00000004
-#define BCHP_HIF_CPUBIUCTRL_CPU2_PWR_ZONE_CNTRL_REG_ZONE_FREQ_SCALE_USED_SHIFT 2
-
-/* HIF_CPUBIUCTRL :: CPU2_PWR_ZONE_CNTRL_REG :: ZONE_MAN_RESET_CNTL [01:01] */
-#define BCHP_HIF_CPUBIUCTRL_CPU2_PWR_ZONE_CNTRL_REG_ZONE_MAN_RESET_CNTL_MASK 0x00000002
-#define BCHP_HIF_CPUBIUCTRL_CPU2_PWR_ZONE_CNTRL_REG_ZONE_MAN_RESET_CNTL_SHIFT 1
-#define BCHP_HIF_CPUBIUCTRL_CPU2_PWR_ZONE_CNTRL_REG_ZONE_MAN_RESET_CNTL_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: CPU2_PWR_ZONE_CNTRL_REG :: ZONE_MAN_CLKEN [00:00] */
-#define BCHP_HIF_CPUBIUCTRL_CPU2_PWR_ZONE_CNTRL_REG_ZONE_MAN_CLKEN_MASK 0x00000001
-#define BCHP_HIF_CPUBIUCTRL_CPU2_PWR_ZONE_CNTRL_REG_ZONE_MAN_CLKEN_SHIFT 0
-#define BCHP_HIF_CPUBIUCTRL_CPU2_PWR_ZONE_CNTRL_REG_ZONE_MAN_CLKEN_DEFAULT 0x00000000
-
-/***************************************************************************
- *CPU3_PWR_ZONE_CNTRL_REG - CPU3 Power Zone Control Register
- ***************************************************************************/
-/* HIF_CPUBIUCTRL :: CPU3_PWR_ZONE_CNTRL_REG :: ZONE_RESET_STATE [31:31] */
-#define BCHP_HIF_CPUBIUCTRL_CPU3_PWR_ZONE_CNTRL_REG_ZONE_RESET_STATE_MASK 0x80000000
-#define BCHP_HIF_CPUBIUCTRL_CPU3_PWR_ZONE_CNTRL_REG_ZONE_RESET_STATE_SHIFT 31
-
-/* HIF_CPUBIUCTRL :: CPU3_PWR_ZONE_CNTRL_REG :: ZONE_ISO_STATE [30:30] */
-#define BCHP_HIF_CPUBIUCTRL_CPU3_PWR_ZONE_CNTRL_REG_ZONE_ISO_STATE_MASK 0x40000000
-#define BCHP_HIF_CPUBIUCTRL_CPU3_PWR_ZONE_CNTRL_REG_ZONE_ISO_STATE_SHIFT 30
-
-/* HIF_CPUBIUCTRL :: CPU3_PWR_ZONE_CNTRL_REG :: ZONE_MEM_PWR_STATE [29:29] */
-#define BCHP_HIF_CPUBIUCTRL_CPU3_PWR_ZONE_CNTRL_REG_ZONE_MEM_PWR_STATE_MASK 0x20000000
-#define BCHP_HIF_CPUBIUCTRL_CPU3_PWR_ZONE_CNTRL_REG_ZONE_MEM_PWR_STATE_SHIFT 29
-
-/* HIF_CPUBIUCTRL :: CPU3_PWR_ZONE_CNTRL_REG :: ZONE_DPG_PWR_STATE [28:28] */
-#define BCHP_HIF_CPUBIUCTRL_CPU3_PWR_ZONE_CNTRL_REG_ZONE_DPG_PWR_STATE_MASK 0x10000000
-#define BCHP_HIF_CPUBIUCTRL_CPU3_PWR_ZONE_CNTRL_REG_ZONE_DPG_PWR_STATE_SHIFT 28
-
-/* HIF_CPUBIUCTRL :: CPU3_PWR_ZONE_CNTRL_REG :: ZONE_POWER_GOOD [27:27] */
-#define BCHP_HIF_CPUBIUCTRL_CPU3_PWR_ZONE_CNTRL_REG_ZONE_POWER_GOOD_MASK 0x08000000
-#define BCHP_HIF_CPUBIUCTRL_CPU3_PWR_ZONE_CNTRL_REG_ZONE_POWER_GOOD_SHIFT 27
-
-/* HIF_CPUBIUCTRL :: CPU3_PWR_ZONE_CNTRL_REG :: ZONE_PWR_ON_STATE [26:26] */
-#define BCHP_HIF_CPUBIUCTRL_CPU3_PWR_ZONE_CNTRL_REG_ZONE_PWR_ON_STATE_MASK 0x04000000
-#define BCHP_HIF_CPUBIUCTRL_CPU3_PWR_ZONE_CNTRL_REG_ZONE_PWR_ON_STATE_SHIFT 26
-
-/* HIF_CPUBIUCTRL :: CPU3_PWR_ZONE_CNTRL_REG :: ZONE_PWR_OFF_STATE [25:25] */
-#define BCHP_HIF_CPUBIUCTRL_CPU3_PWR_ZONE_CNTRL_REG_ZONE_PWR_OFF_STATE_MASK 0x02000000
-#define BCHP_HIF_CPUBIUCTRL_CPU3_PWR_ZONE_CNTRL_REG_ZONE_PWR_OFF_STATE_SHIFT 25
-
-/* HIF_CPUBIUCTRL :: CPU3_PWR_ZONE_CNTRL_REG :: FREQ_SCALAR_DYNAMIC_SEL [24:24] */
-#define BCHP_HIF_CPUBIUCTRL_CPU3_PWR_ZONE_CNTRL_REG_FREQ_SCALAR_DYNAMIC_SEL_MASK 0x01000000
-#define BCHP_HIF_CPUBIUCTRL_CPU3_PWR_ZONE_CNTRL_REG_FREQ_SCALAR_DYNAMIC_SEL_SHIFT 24
-
-/* HIF_CPUBIUCTRL :: CPU3_PWR_ZONE_CNTRL_REG :: ZONE_PWR_CNTL_STATE [23:19] */
-#define BCHP_HIF_CPUBIUCTRL_CPU3_PWR_ZONE_CNTRL_REG_ZONE_PWR_CNTL_STATE_MASK 0x00f80000
-#define BCHP_HIF_CPUBIUCTRL_CPU3_PWR_ZONE_CNTRL_REG_ZONE_PWR_CNTL_STATE_SHIFT 19
-
-/* HIF_CPUBIUCTRL :: CPU3_PWR_ZONE_CNTRL_REG :: reserved0 [18:14] */
-#define BCHP_HIF_CPUBIUCTRL_CPU3_PWR_ZONE_CNTRL_REG_reserved0_MASK 0x0007c000
-#define BCHP_HIF_CPUBIUCTRL_CPU3_PWR_ZONE_CNTRL_REG_reserved0_SHIFT 14
-
-/* HIF_CPUBIUCTRL :: CPU3_PWR_ZONE_CNTRL_REG :: ZONE_MEM_STBY [13:13] */
-#define BCHP_HIF_CPUBIUCTRL_CPU3_PWR_ZONE_CNTRL_REG_ZONE_MEM_STBY_MASK 0x00002000
-#define BCHP_HIF_CPUBIUCTRL_CPU3_PWR_ZONE_CNTRL_REG_ZONE_MEM_STBY_SHIFT 13
-
-/* HIF_CPUBIUCTRL :: CPU3_PWR_ZONE_CNTRL_REG :: ZONE_BLK_RST_ASSERT [12:12] */
-#define BCHP_HIF_CPUBIUCTRL_CPU3_PWR_ZONE_CNTRL_REG_ZONE_BLK_RST_ASSERT_MASK 0x00001000
-#define BCHP_HIF_CPUBIUCTRL_CPU3_PWR_ZONE_CNTRL_REG_ZONE_BLK_RST_ASSERT_SHIFT 12
-#define BCHP_HIF_CPUBIUCTRL_CPU3_PWR_ZONE_CNTRL_REG_ZONE_BLK_RST_ASSERT_DEFAULT 0x00000001
-
-/* HIF_CPUBIUCTRL :: CPU3_PWR_ZONE_CNTRL_REG :: ZONE_MEM_PWR_CNTL_EN [11:11] */
-#define BCHP_HIF_CPUBIUCTRL_CPU3_PWR_ZONE_CNTRL_REG_ZONE_MEM_PWR_CNTL_EN_MASK 0x00000800
-#define BCHP_HIF_CPUBIUCTRL_CPU3_PWR_ZONE_CNTRL_REG_ZONE_MEM_PWR_CNTL_EN_SHIFT 11
-#define BCHP_HIF_CPUBIUCTRL_CPU3_PWR_ZONE_CNTRL_REG_ZONE_MEM_PWR_CNTL_EN_DEFAULT 0x00000001
-
-/* HIF_CPUBIUCTRL :: CPU3_PWR_ZONE_CNTRL_REG :: ZONE_PWR_UP_REQ [10:10] */
-#define BCHP_HIF_CPUBIUCTRL_CPU3_PWR_ZONE_CNTRL_REG_ZONE_PWR_UP_REQ_MASK 0x00000400
-#define BCHP_HIF_CPUBIUCTRL_CPU3_PWR_ZONE_CNTRL_REG_ZONE_PWR_UP_REQ_SHIFT 10
-#define BCHP_HIF_CPUBIUCTRL_CPU3_PWR_ZONE_CNTRL_REG_ZONE_PWR_UP_REQ_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: CPU3_PWR_ZONE_CNTRL_REG :: ZONE_PWR_DN_REQ [09:09] */
-#define BCHP_HIF_CPUBIUCTRL_CPU3_PWR_ZONE_CNTRL_REG_ZONE_PWR_DN_REQ_MASK 0x00000200
-#define BCHP_HIF_CPUBIUCTRL_CPU3_PWR_ZONE_CNTRL_REG_ZONE_PWR_DN_REQ_SHIFT 9
-#define BCHP_HIF_CPUBIUCTRL_CPU3_PWR_ZONE_CNTRL_REG_ZONE_PWR_DN_REQ_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: CPU3_PWR_ZONE_CNTRL_REG :: ZONE_DPG_CNTL_EN [08:08] */
-#define BCHP_HIF_CPUBIUCTRL_CPU3_PWR_ZONE_CNTRL_REG_ZONE_DPG_CNTL_EN_MASK 0x00000100
-#define BCHP_HIF_CPUBIUCTRL_CPU3_PWR_ZONE_CNTRL_REG_ZONE_DPG_CNTL_EN_SHIFT 8
-#define BCHP_HIF_CPUBIUCTRL_CPU3_PWR_ZONE_CNTRL_REG_ZONE_DPG_CNTL_EN_DEFAULT 0x00000001
-
-/* HIF_CPUBIUCTRL :: CPU3_PWR_ZONE_CNTRL_REG :: ZONE_MANUAL_CONTROL [07:07] */
-#define BCHP_HIF_CPUBIUCTRL_CPU3_PWR_ZONE_CNTRL_REG_ZONE_MANUAL_CONTROL_MASK 0x00000080
-#define BCHP_HIF_CPUBIUCTRL_CPU3_PWR_ZONE_CNTRL_REG_ZONE_MANUAL_CONTROL_SHIFT 7
-#define BCHP_HIF_CPUBIUCTRL_CPU3_PWR_ZONE_CNTRL_REG_ZONE_MANUAL_CONTROL_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: CPU3_PWR_ZONE_CNTRL_REG :: ZONE_MAN_ISO_CNTL [06:06] */
-#define BCHP_HIF_CPUBIUCTRL_CPU3_PWR_ZONE_CNTRL_REG_ZONE_MAN_ISO_CNTL_MASK 0x00000040
-#define BCHP_HIF_CPUBIUCTRL_CPU3_PWR_ZONE_CNTRL_REG_ZONE_MAN_ISO_CNTL_SHIFT 6
-#define BCHP_HIF_CPUBIUCTRL_CPU3_PWR_ZONE_CNTRL_REG_ZONE_MAN_ISO_CNTL_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: CPU3_PWR_ZONE_CNTRL_REG :: reserved1 [05:05] */
-#define BCHP_HIF_CPUBIUCTRL_CPU3_PWR_ZONE_CNTRL_REG_reserved1_MASK 0x00000020
-#define BCHP_HIF_CPUBIUCTRL_CPU3_PWR_ZONE_CNTRL_REG_reserved1_SHIFT 5
-
-/* HIF_CPUBIUCTRL :: CPU3_PWR_ZONE_CNTRL_REG :: ZONE_MAN_MEM_PWR [04:04] */
-#define BCHP_HIF_CPUBIUCTRL_CPU3_PWR_ZONE_CNTRL_REG_ZONE_MAN_MEM_PWR_MASK 0x00000010
-#define BCHP_HIF_CPUBIUCTRL_CPU3_PWR_ZONE_CNTRL_REG_ZONE_MAN_MEM_PWR_SHIFT 4
-#define BCHP_HIF_CPUBIUCTRL_CPU3_PWR_ZONE_CNTRL_REG_ZONE_MAN_MEM_PWR_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: CPU3_PWR_ZONE_CNTRL_REG :: ZONE_DPG_CAPABLE [03:03] */
-#define BCHP_HIF_CPUBIUCTRL_CPU3_PWR_ZONE_CNTRL_REG_ZONE_DPG_CAPABLE_MASK 0x00000008
-#define BCHP_HIF_CPUBIUCTRL_CPU3_PWR_ZONE_CNTRL_REG_ZONE_DPG_CAPABLE_SHIFT 3
-
-/* HIF_CPUBIUCTRL :: CPU3_PWR_ZONE_CNTRL_REG :: ZONE_FREQ_SCALE_USED [02:02] */
-#define BCHP_HIF_CPUBIUCTRL_CPU3_PWR_ZONE_CNTRL_REG_ZONE_FREQ_SCALE_USED_MASK 0x00000004
-#define BCHP_HIF_CPUBIUCTRL_CPU3_PWR_ZONE_CNTRL_REG_ZONE_FREQ_SCALE_USED_SHIFT 2
-
-/* HIF_CPUBIUCTRL :: CPU3_PWR_ZONE_CNTRL_REG :: ZONE_MAN_RESET_CNTL [01:01] */
-#define BCHP_HIF_CPUBIUCTRL_CPU3_PWR_ZONE_CNTRL_REG_ZONE_MAN_RESET_CNTL_MASK 0x00000002
-#define BCHP_HIF_CPUBIUCTRL_CPU3_PWR_ZONE_CNTRL_REG_ZONE_MAN_RESET_CNTL_SHIFT 1
-#define BCHP_HIF_CPUBIUCTRL_CPU3_PWR_ZONE_CNTRL_REG_ZONE_MAN_RESET_CNTL_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: CPU3_PWR_ZONE_CNTRL_REG :: ZONE_MAN_CLKEN [00:00] */
-#define BCHP_HIF_CPUBIUCTRL_CPU3_PWR_ZONE_CNTRL_REG_ZONE_MAN_CLKEN_MASK 0x00000001
-#define BCHP_HIF_CPUBIUCTRL_CPU3_PWR_ZONE_CNTRL_REG_ZONE_MAN_CLKEN_SHIFT 0
-#define BCHP_HIF_CPUBIUCTRL_CPU3_PWR_ZONE_CNTRL_REG_ZONE_MAN_CLKEN_DEFAULT 0x00000000
-
-/***************************************************************************
- *L2BIU_PWR_ZONE_CNTRL_REG - L2 and BIU Power Zone Control Register
- ***************************************************************************/
-/* HIF_CPUBIUCTRL :: L2BIU_PWR_ZONE_CNTRL_REG :: ZONE_RESET_STATE [31:31] */
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_PWR_ZONE_CNTRL_REG_ZONE_RESET_STATE_MASK 0x80000000
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_PWR_ZONE_CNTRL_REG_ZONE_RESET_STATE_SHIFT 31
-
-/* HIF_CPUBIUCTRL :: L2BIU_PWR_ZONE_CNTRL_REG :: ZONE_ISO_STATE [30:30] */
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_PWR_ZONE_CNTRL_REG_ZONE_ISO_STATE_MASK 0x40000000
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_PWR_ZONE_CNTRL_REG_ZONE_ISO_STATE_SHIFT 30
-
-/* HIF_CPUBIUCTRL :: L2BIU_PWR_ZONE_CNTRL_REG :: ZONE_MEM_PWR_STATE [29:29] */
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_PWR_ZONE_CNTRL_REG_ZONE_MEM_PWR_STATE_MASK 0x20000000
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_PWR_ZONE_CNTRL_REG_ZONE_MEM_PWR_STATE_SHIFT 29
-
-/* HIF_CPUBIUCTRL :: L2BIU_PWR_ZONE_CNTRL_REG :: ZONE_DPG_PWR_STATE [28:28] */
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_PWR_ZONE_CNTRL_REG_ZONE_DPG_PWR_STATE_MASK 0x10000000
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_PWR_ZONE_CNTRL_REG_ZONE_DPG_PWR_STATE_SHIFT 28
-
-/* HIF_CPUBIUCTRL :: L2BIU_PWR_ZONE_CNTRL_REG :: ZONE_POWER_GOOD [27:27] */
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_PWR_ZONE_CNTRL_REG_ZONE_POWER_GOOD_MASK 0x08000000
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_PWR_ZONE_CNTRL_REG_ZONE_POWER_GOOD_SHIFT 27
-
-/* HIF_CPUBIUCTRL :: L2BIU_PWR_ZONE_CNTRL_REG :: ZONE_PWR_ON_STATE [26:26] */
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_PWR_ZONE_CNTRL_REG_ZONE_PWR_ON_STATE_MASK 0x04000000
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_PWR_ZONE_CNTRL_REG_ZONE_PWR_ON_STATE_SHIFT 26
-
-/* HIF_CPUBIUCTRL :: L2BIU_PWR_ZONE_CNTRL_REG :: ZONE_PWR_OFF_STATE [25:25] */
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_PWR_ZONE_CNTRL_REG_ZONE_PWR_OFF_STATE_MASK 0x02000000
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_PWR_ZONE_CNTRL_REG_ZONE_PWR_OFF_STATE_SHIFT 25
-
-/* HIF_CPUBIUCTRL :: L2BIU_PWR_ZONE_CNTRL_REG :: FREQ_SCALAR_DYNAMIC_SEL [24:24] */
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_PWR_ZONE_CNTRL_REG_FREQ_SCALAR_DYNAMIC_SEL_MASK 0x01000000
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_PWR_ZONE_CNTRL_REG_FREQ_SCALAR_DYNAMIC_SEL_SHIFT 24
-
-/* HIF_CPUBIUCTRL :: L2BIU_PWR_ZONE_CNTRL_REG :: ZONE_PWR_CNTL_STATE [23:19] */
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_PWR_ZONE_CNTRL_REG_ZONE_PWR_CNTL_STATE_MASK 0x00f80000
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_PWR_ZONE_CNTRL_REG_ZONE_PWR_CNTL_STATE_SHIFT 19
-
-/* HIF_CPUBIUCTRL :: L2BIU_PWR_ZONE_CNTRL_REG :: reserved0 [18:14] */
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_PWR_ZONE_CNTRL_REG_reserved0_MASK 0x0007c000
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_PWR_ZONE_CNTRL_REG_reserved0_SHIFT 14
-
-/* HIF_CPUBIUCTRL :: L2BIU_PWR_ZONE_CNTRL_REG :: ZONE_MEM_STBY [13:13] */
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_PWR_ZONE_CNTRL_REG_ZONE_MEM_STBY_MASK 0x00002000
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_PWR_ZONE_CNTRL_REG_ZONE_MEM_STBY_SHIFT 13
-
-/* HIF_CPUBIUCTRL :: L2BIU_PWR_ZONE_CNTRL_REG :: ZONE_BLK_RST_ASSERT [12:12] */
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_PWR_ZONE_CNTRL_REG_ZONE_BLK_RST_ASSERT_MASK 0x00001000
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_PWR_ZONE_CNTRL_REG_ZONE_BLK_RST_ASSERT_SHIFT 12
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_PWR_ZONE_CNTRL_REG_ZONE_BLK_RST_ASSERT_DEFAULT 0x00000001
-
-/* HIF_CPUBIUCTRL :: L2BIU_PWR_ZONE_CNTRL_REG :: ZONE_MEM_PWR_CNTL_EN [11:11] */
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_PWR_ZONE_CNTRL_REG_ZONE_MEM_PWR_CNTL_EN_MASK 0x00000800
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_PWR_ZONE_CNTRL_REG_ZONE_MEM_PWR_CNTL_EN_SHIFT 11
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_PWR_ZONE_CNTRL_REG_ZONE_MEM_PWR_CNTL_EN_DEFAULT 0x00000001
-
-/* HIF_CPUBIUCTRL :: L2BIU_PWR_ZONE_CNTRL_REG :: ZONE_PWR_UP_REQ [10:10] */
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_PWR_ZONE_CNTRL_REG_ZONE_PWR_UP_REQ_MASK 0x00000400
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_PWR_ZONE_CNTRL_REG_ZONE_PWR_UP_REQ_SHIFT 10
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_PWR_ZONE_CNTRL_REG_ZONE_PWR_UP_REQ_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: L2BIU_PWR_ZONE_CNTRL_REG :: ZONE_PWR_DN_REQ [09:09] */
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_PWR_ZONE_CNTRL_REG_ZONE_PWR_DN_REQ_MASK 0x00000200
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_PWR_ZONE_CNTRL_REG_ZONE_PWR_DN_REQ_SHIFT 9
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_PWR_ZONE_CNTRL_REG_ZONE_PWR_DN_REQ_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: L2BIU_PWR_ZONE_CNTRL_REG :: ZONE_DPG_CNTL_EN [08:08] */
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_PWR_ZONE_CNTRL_REG_ZONE_DPG_CNTL_EN_MASK 0x00000100
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_PWR_ZONE_CNTRL_REG_ZONE_DPG_CNTL_EN_SHIFT 8
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_PWR_ZONE_CNTRL_REG_ZONE_DPG_CNTL_EN_DEFAULT 0x00000001
-
-/* HIF_CPUBIUCTRL :: L2BIU_PWR_ZONE_CNTRL_REG :: ZONE_MANUAL_CONTROL [07:07] */
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_PWR_ZONE_CNTRL_REG_ZONE_MANUAL_CONTROL_MASK 0x00000080
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_PWR_ZONE_CNTRL_REG_ZONE_MANUAL_CONTROL_SHIFT 7
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_PWR_ZONE_CNTRL_REG_ZONE_MANUAL_CONTROL_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: L2BIU_PWR_ZONE_CNTRL_REG :: ZONE_MAN_ISO_CNTL [06:06] */
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_PWR_ZONE_CNTRL_REG_ZONE_MAN_ISO_CNTL_MASK 0x00000040
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_PWR_ZONE_CNTRL_REG_ZONE_MAN_ISO_CNTL_SHIFT 6
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_PWR_ZONE_CNTRL_REG_ZONE_MAN_ISO_CNTL_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: L2BIU_PWR_ZONE_CNTRL_REG :: reserved1 [05:05] */
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_PWR_ZONE_CNTRL_REG_reserved1_MASK 0x00000020
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_PWR_ZONE_CNTRL_REG_reserved1_SHIFT 5
-
-/* HIF_CPUBIUCTRL :: L2BIU_PWR_ZONE_CNTRL_REG :: ZONE_MAN_MEM_PWR [04:04] */
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_PWR_ZONE_CNTRL_REG_ZONE_MAN_MEM_PWR_MASK 0x00000010
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_PWR_ZONE_CNTRL_REG_ZONE_MAN_MEM_PWR_SHIFT 4
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_PWR_ZONE_CNTRL_REG_ZONE_MAN_MEM_PWR_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: L2BIU_PWR_ZONE_CNTRL_REG :: ZONE_DPG_CAPABLE [03:03] */
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_PWR_ZONE_CNTRL_REG_ZONE_DPG_CAPABLE_MASK 0x00000008
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_PWR_ZONE_CNTRL_REG_ZONE_DPG_CAPABLE_SHIFT 3
-
-/* HIF_CPUBIUCTRL :: L2BIU_PWR_ZONE_CNTRL_REG :: ZONE_FREQ_SCALE_USED [02:02] */
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_PWR_ZONE_CNTRL_REG_ZONE_FREQ_SCALE_USED_MASK 0x00000004
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_PWR_ZONE_CNTRL_REG_ZONE_FREQ_SCALE_USED_SHIFT 2
-
-/* HIF_CPUBIUCTRL :: L2BIU_PWR_ZONE_CNTRL_REG :: ZONE_MAN_RESET_CNTL [01:01] */
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_PWR_ZONE_CNTRL_REG_ZONE_MAN_RESET_CNTL_MASK 0x00000002
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_PWR_ZONE_CNTRL_REG_ZONE_MAN_RESET_CNTL_SHIFT 1
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_PWR_ZONE_CNTRL_REG_ZONE_MAN_RESET_CNTL_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: L2BIU_PWR_ZONE_CNTRL_REG :: ZONE_MAN_CLKEN [00:00] */
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_PWR_ZONE_CNTRL_REG_ZONE_MAN_CLKEN_MASK 0x00000001
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_PWR_ZONE_CNTRL_REG_ZONE_MAN_CLKEN_SHIFT 0
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_PWR_ZONE_CNTRL_REG_ZONE_MAN_CLKEN_DEFAULT 0x00000000
-
-/***************************************************************************
- *CPU0_PWR_ZONE_CONFIG1_REG - CPU0 Power Zone Config1 Registers
- ***************************************************************************/
-/* HIF_CPUBIUCTRL :: CPU0_PWR_ZONE_CONFIG1_REG :: RST_OFF_DLY [31:28] */
-#define BCHP_HIF_CPUBIUCTRL_CPU0_PWR_ZONE_CONFIG1_REG_RST_OFF_DLY_MASK 0xf0000000
-#define BCHP_HIF_CPUBIUCTRL_CPU0_PWR_ZONE_CONFIG1_REG_RST_OFF_DLY_SHIFT 28
-#define BCHP_HIF_CPUBIUCTRL_CPU0_PWR_ZONE_CONFIG1_REG_RST_OFF_DLY_DEFAULT 0x00000004
-
-/* HIF_CPUBIUCTRL :: CPU0_PWR_ZONE_CONFIG1_REG :: RST_ON_DLY [27:24] */
-#define BCHP_HIF_CPUBIUCTRL_CPU0_PWR_ZONE_CONFIG1_REG_RST_ON_DLY_MASK 0x0f000000
-#define BCHP_HIF_CPUBIUCTRL_CPU0_PWR_ZONE_CONFIG1_REG_RST_ON_DLY_SHIFT 24
-#define BCHP_HIF_CPUBIUCTRL_CPU0_PWR_ZONE_CONFIG1_REG_RST_ON_DLY_DEFAULT 0x00000004
-
-/* HIF_CPUBIUCTRL :: CPU0_PWR_ZONE_CONFIG1_REG :: CLK_OFF_DLY [23:20] */
-#define BCHP_HIF_CPUBIUCTRL_CPU0_PWR_ZONE_CONFIG1_REG_CLK_OFF_DLY_MASK 0x00f00000
-#define BCHP_HIF_CPUBIUCTRL_CPU0_PWR_ZONE_CONFIG1_REG_CLK_OFF_DLY_SHIFT 20
-#define BCHP_HIF_CPUBIUCTRL_CPU0_PWR_ZONE_CONFIG1_REG_CLK_OFF_DLY_DEFAULT 0x00000004
-
-/* HIF_CPUBIUCTRL :: CPU0_PWR_ZONE_CONFIG1_REG :: CLK_ON_DLY [19:16] */
-#define BCHP_HIF_CPUBIUCTRL_CPU0_PWR_ZONE_CONFIG1_REG_CLK_ON_DLY_MASK 0x000f0000
-#define BCHP_HIF_CPUBIUCTRL_CPU0_PWR_ZONE_CONFIG1_REG_CLK_ON_DLY_SHIFT 16
-#define BCHP_HIF_CPUBIUCTRL_CPU0_PWR_ZONE_CONFIG1_REG_CLK_ON_DLY_DEFAULT 0x00000004
-
-/* HIF_CPUBIUCTRL :: CPU0_PWR_ZONE_CONFIG1_REG :: ISO_OFF_DLY [15:12] */
-#define BCHP_HIF_CPUBIUCTRL_CPU0_PWR_ZONE_CONFIG1_REG_ISO_OFF_DLY_MASK 0x0000f000
-#define BCHP_HIF_CPUBIUCTRL_CPU0_PWR_ZONE_CONFIG1_REG_ISO_OFF_DLY_SHIFT 12
-#define BCHP_HIF_CPUBIUCTRL_CPU0_PWR_ZONE_CONFIG1_REG_ISO_OFF_DLY_DEFAULT 0x00000004
-
-/* HIF_CPUBIUCTRL :: CPU0_PWR_ZONE_CONFIG1_REG :: ISO_ON_DLY [11:08] */
-#define BCHP_HIF_CPUBIUCTRL_CPU0_PWR_ZONE_CONFIG1_REG_ISO_ON_DLY_MASK 0x00000f00
-#define BCHP_HIF_CPUBIUCTRL_CPU0_PWR_ZONE_CONFIG1_REG_ISO_ON_DLY_SHIFT 8
-#define BCHP_HIF_CPUBIUCTRL_CPU0_PWR_ZONE_CONFIG1_REG_ISO_ON_DLY_DEFAULT 0x00000004
-
-/* HIF_CPUBIUCTRL :: CPU0_PWR_ZONE_CONFIG1_REG :: reserved0 [07:05] */
-#define BCHP_HIF_CPUBIUCTRL_CPU0_PWR_ZONE_CONFIG1_REG_reserved0_MASK 0x000000e0
-#define BCHP_HIF_CPUBIUCTRL_CPU0_PWR_ZONE_CONFIG1_REG_reserved0_SHIFT 5
-
-/* HIF_CPUBIUCTRL :: CPU0_PWR_ZONE_CONFIG1_REG :: PWROK_TRESH [04:03] */
-#define BCHP_HIF_CPUBIUCTRL_CPU0_PWR_ZONE_CONFIG1_REG_PWROK_TRESH_MASK 0x00000018
-#define BCHP_HIF_CPUBIUCTRL_CPU0_PWR_ZONE_CONFIG1_REG_PWROK_TRESH_SHIFT 3
-#define BCHP_HIF_CPUBIUCTRL_CPU0_PWR_ZONE_CONFIG1_REG_PWROK_TRESH_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: CPU0_PWR_ZONE_CONFIG1_REG :: PWROK_DELAY_SEL [02:00] */
-#define BCHP_HIF_CPUBIUCTRL_CPU0_PWR_ZONE_CONFIG1_REG_PWROK_DELAY_SEL_MASK 0x00000007
-#define BCHP_HIF_CPUBIUCTRL_CPU0_PWR_ZONE_CONFIG1_REG_PWROK_DELAY_SEL_SHIFT 0
-#define BCHP_HIF_CPUBIUCTRL_CPU0_PWR_ZONE_CONFIG1_REG_PWROK_DELAY_SEL_DEFAULT 0x00000000
-
-/***************************************************************************
- *CPU0_PWR_ZONE_CONFIG2_REG - CPU0 Power Zone Config2 Registers
- ***************************************************************************/
-/* HIF_CPUBIUCTRL :: CPU0_PWR_ZONE_CONFIG2_REG :: MEM_OFF_DLY [31:28] */
-#define BCHP_HIF_CPUBIUCTRL_CPU0_PWR_ZONE_CONFIG2_REG_MEM_OFF_DLY_MASK 0xf0000000
-#define BCHP_HIF_CPUBIUCTRL_CPU0_PWR_ZONE_CONFIG2_REG_MEM_OFF_DLY_SHIFT 28
-#define BCHP_HIF_CPUBIUCTRL_CPU0_PWR_ZONE_CONFIG2_REG_MEM_OFF_DLY_DEFAULT 0x00000004
-
-/* HIF_CPUBIUCTRL :: CPU0_PWR_ZONE_CONFIG2_REG :: MEM_ON_DLY [27:24] */
-#define BCHP_HIF_CPUBIUCTRL_CPU0_PWR_ZONE_CONFIG2_REG_MEM_ON_DLY_MASK 0x0f000000
-#define BCHP_HIF_CPUBIUCTRL_CPU0_PWR_ZONE_CONFIG2_REG_MEM_ON_DLY_SHIFT 24
-#define BCHP_HIF_CPUBIUCTRL_CPU0_PWR_ZONE_CONFIG2_REG_MEM_ON_DLY_DEFAULT 0x00000004
-
-/* HIF_CPUBIUCTRL :: CPU0_PWR_ZONE_CONFIG2_REG :: DPG_OFF_DLY [23:20] */
-#define BCHP_HIF_CPUBIUCTRL_CPU0_PWR_ZONE_CONFIG2_REG_DPG_OFF_DLY_MASK 0x00f00000
-#define BCHP_HIF_CPUBIUCTRL_CPU0_PWR_ZONE_CONFIG2_REG_DPG_OFF_DLY_SHIFT 20
-#define BCHP_HIF_CPUBIUCTRL_CPU0_PWR_ZONE_CONFIG2_REG_DPG_OFF_DLY_DEFAULT 0x00000004
-
-/* HIF_CPUBIUCTRL :: CPU0_PWR_ZONE_CONFIG2_REG :: DPG1_ON_DLY [19:16] */
-#define BCHP_HIF_CPUBIUCTRL_CPU0_PWR_ZONE_CONFIG2_REG_DPG1_ON_DLY_MASK 0x000f0000
-#define BCHP_HIF_CPUBIUCTRL_CPU0_PWR_ZONE_CONFIG2_REG_DPG1_ON_DLY_SHIFT 16
-#define BCHP_HIF_CPUBIUCTRL_CPU0_PWR_ZONE_CONFIG2_REG_DPG1_ON_DLY_DEFAULT 0x00000003
-
-/* HIF_CPUBIUCTRL :: CPU0_PWR_ZONE_CONFIG2_REG :: DPGN_ON_DLY [15:12] */
-#define BCHP_HIF_CPUBIUCTRL_CPU0_PWR_ZONE_CONFIG2_REG_DPGN_ON_DLY_MASK 0x0000f000
-#define BCHP_HIF_CPUBIUCTRL_CPU0_PWR_ZONE_CONFIG2_REG_DPGN_ON_DLY_SHIFT 12
-#define BCHP_HIF_CPUBIUCTRL_CPU0_PWR_ZONE_CONFIG2_REG_DPGN_ON_DLY_DEFAULT 0x00000001
-
-/* HIF_CPUBIUCTRL :: CPU0_PWR_ZONE_CONFIG2_REG :: reserved0 [11:06] */
-#define BCHP_HIF_CPUBIUCTRL_CPU0_PWR_ZONE_CONFIG2_REG_reserved0_MASK 0x00000fc0
-#define BCHP_HIF_CPUBIUCTRL_CPU0_PWR_ZONE_CONFIG2_REG_reserved0_SHIFT 6
-
-/* HIF_CPUBIUCTRL :: CPU0_PWR_ZONE_CONFIG2_REG :: SLEW_PRESCALE_SEL [05:03] */
-#define BCHP_HIF_CPUBIUCTRL_CPU0_PWR_ZONE_CONFIG2_REG_SLEW_PRESCALE_SEL_MASK 0x00000038
-#define BCHP_HIF_CPUBIUCTRL_CPU0_PWR_ZONE_CONFIG2_REG_SLEW_PRESCALE_SEL_SHIFT 3
-#define BCHP_HIF_CPUBIUCTRL_CPU0_PWR_ZONE_CONFIG2_REG_SLEW_PRESCALE_SEL_DEFAULT 0x00000002
-
-/* HIF_CPUBIUCTRL :: CPU0_PWR_ZONE_CONFIG2_REG :: DELAY_PRESCALE_SEL [02:00] */
-#define BCHP_HIF_CPUBIUCTRL_CPU0_PWR_ZONE_CONFIG2_REG_DELAY_PRESCALE_SEL_MASK 0x00000007
-#define BCHP_HIF_CPUBIUCTRL_CPU0_PWR_ZONE_CONFIG2_REG_DELAY_PRESCALE_SEL_SHIFT 0
-#define BCHP_HIF_CPUBIUCTRL_CPU0_PWR_ZONE_CONFIG2_REG_DELAY_PRESCALE_SEL_DEFAULT 0x00000002
-
-/***************************************************************************
- *CPU1_PWR_ZONE_CONFIG1_REG - CPU1 Power Zone Config1 Registers
- ***************************************************************************/
-/* HIF_CPUBIUCTRL :: CPU1_PWR_ZONE_CONFIG1_REG :: RST_OFF_DLY [31:28] */
-#define BCHP_HIF_CPUBIUCTRL_CPU1_PWR_ZONE_CONFIG1_REG_RST_OFF_DLY_MASK 0xf0000000
-#define BCHP_HIF_CPUBIUCTRL_CPU1_PWR_ZONE_CONFIG1_REG_RST_OFF_DLY_SHIFT 28
-#define BCHP_HIF_CPUBIUCTRL_CPU1_PWR_ZONE_CONFIG1_REG_RST_OFF_DLY_DEFAULT 0x00000004
-
-/* HIF_CPUBIUCTRL :: CPU1_PWR_ZONE_CONFIG1_REG :: RST_ON_DLY [27:24] */
-#define BCHP_HIF_CPUBIUCTRL_CPU1_PWR_ZONE_CONFIG1_REG_RST_ON_DLY_MASK 0x0f000000
-#define BCHP_HIF_CPUBIUCTRL_CPU1_PWR_ZONE_CONFIG1_REG_RST_ON_DLY_SHIFT 24
-#define BCHP_HIF_CPUBIUCTRL_CPU1_PWR_ZONE_CONFIG1_REG_RST_ON_DLY_DEFAULT 0x00000004
-
-/* HIF_CPUBIUCTRL :: CPU1_PWR_ZONE_CONFIG1_REG :: CLK_OFF_DLY [23:20] */
-#define BCHP_HIF_CPUBIUCTRL_CPU1_PWR_ZONE_CONFIG1_REG_CLK_OFF_DLY_MASK 0x00f00000
-#define BCHP_HIF_CPUBIUCTRL_CPU1_PWR_ZONE_CONFIG1_REG_CLK_OFF_DLY_SHIFT 20
-#define BCHP_HIF_CPUBIUCTRL_CPU1_PWR_ZONE_CONFIG1_REG_CLK_OFF_DLY_DEFAULT 0x00000004
-
-/* HIF_CPUBIUCTRL :: CPU1_PWR_ZONE_CONFIG1_REG :: CLK_ON_DLY [19:16] */
-#define BCHP_HIF_CPUBIUCTRL_CPU1_PWR_ZONE_CONFIG1_REG_CLK_ON_DLY_MASK 0x000f0000
-#define BCHP_HIF_CPUBIUCTRL_CPU1_PWR_ZONE_CONFIG1_REG_CLK_ON_DLY_SHIFT 16
-#define BCHP_HIF_CPUBIUCTRL_CPU1_PWR_ZONE_CONFIG1_REG_CLK_ON_DLY_DEFAULT 0x00000004
-
-/* HIF_CPUBIUCTRL :: CPU1_PWR_ZONE_CONFIG1_REG :: ISO_OFF_DLY [15:12] */
-#define BCHP_HIF_CPUBIUCTRL_CPU1_PWR_ZONE_CONFIG1_REG_ISO_OFF_DLY_MASK 0x0000f000
-#define BCHP_HIF_CPUBIUCTRL_CPU1_PWR_ZONE_CONFIG1_REG_ISO_OFF_DLY_SHIFT 12
-#define BCHP_HIF_CPUBIUCTRL_CPU1_PWR_ZONE_CONFIG1_REG_ISO_OFF_DLY_DEFAULT 0x00000004
-
-/* HIF_CPUBIUCTRL :: CPU1_PWR_ZONE_CONFIG1_REG :: ISO_ON_DLY [11:08] */
-#define BCHP_HIF_CPUBIUCTRL_CPU1_PWR_ZONE_CONFIG1_REG_ISO_ON_DLY_MASK 0x00000f00
-#define BCHP_HIF_CPUBIUCTRL_CPU1_PWR_ZONE_CONFIG1_REG_ISO_ON_DLY_SHIFT 8
-#define BCHP_HIF_CPUBIUCTRL_CPU1_PWR_ZONE_CONFIG1_REG_ISO_ON_DLY_DEFAULT 0x00000004
-
-/* HIF_CPUBIUCTRL :: CPU1_PWR_ZONE_CONFIG1_REG :: reserved0 [07:05] */
-#define BCHP_HIF_CPUBIUCTRL_CPU1_PWR_ZONE_CONFIG1_REG_reserved0_MASK 0x000000e0
-#define BCHP_HIF_CPUBIUCTRL_CPU1_PWR_ZONE_CONFIG1_REG_reserved0_SHIFT 5
-
-/* HIF_CPUBIUCTRL :: CPU1_PWR_ZONE_CONFIG1_REG :: PWROK_TRESH [04:03] */
-#define BCHP_HIF_CPUBIUCTRL_CPU1_PWR_ZONE_CONFIG1_REG_PWROK_TRESH_MASK 0x00000018
-#define BCHP_HIF_CPUBIUCTRL_CPU1_PWR_ZONE_CONFIG1_REG_PWROK_TRESH_SHIFT 3
-#define BCHP_HIF_CPUBIUCTRL_CPU1_PWR_ZONE_CONFIG1_REG_PWROK_TRESH_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: CPU1_PWR_ZONE_CONFIG1_REG :: PWROK_DELAY_SEL [02:00] */
-#define BCHP_HIF_CPUBIUCTRL_CPU1_PWR_ZONE_CONFIG1_REG_PWROK_DELAY_SEL_MASK 0x00000007
-#define BCHP_HIF_CPUBIUCTRL_CPU1_PWR_ZONE_CONFIG1_REG_PWROK_DELAY_SEL_SHIFT 0
-#define BCHP_HIF_CPUBIUCTRL_CPU1_PWR_ZONE_CONFIG1_REG_PWROK_DELAY_SEL_DEFAULT 0x00000000
-
-/***************************************************************************
- *CPU1_PWR_ZONE_CONFIG2_REG - CPU1 Power Zone Config2 Registers
- ***************************************************************************/
-/* HIF_CPUBIUCTRL :: CPU1_PWR_ZONE_CONFIG2_REG :: MEM_OFF_DLY [31:28] */
-#define BCHP_HIF_CPUBIUCTRL_CPU1_PWR_ZONE_CONFIG2_REG_MEM_OFF_DLY_MASK 0xf0000000
-#define BCHP_HIF_CPUBIUCTRL_CPU1_PWR_ZONE_CONFIG2_REG_MEM_OFF_DLY_SHIFT 28
-#define BCHP_HIF_CPUBIUCTRL_CPU1_PWR_ZONE_CONFIG2_REG_MEM_OFF_DLY_DEFAULT 0x00000004
-
-/* HIF_CPUBIUCTRL :: CPU1_PWR_ZONE_CONFIG2_REG :: MEM_ON_DLY [27:24] */
-#define BCHP_HIF_CPUBIUCTRL_CPU1_PWR_ZONE_CONFIG2_REG_MEM_ON_DLY_MASK 0x0f000000
-#define BCHP_HIF_CPUBIUCTRL_CPU1_PWR_ZONE_CONFIG2_REG_MEM_ON_DLY_SHIFT 24
-#define BCHP_HIF_CPUBIUCTRL_CPU1_PWR_ZONE_CONFIG2_REG_MEM_ON_DLY_DEFAULT 0x00000004
-
-/* HIF_CPUBIUCTRL :: CPU1_PWR_ZONE_CONFIG2_REG :: DPG_OFF_DLY [23:20] */
-#define BCHP_HIF_CPUBIUCTRL_CPU1_PWR_ZONE_CONFIG2_REG_DPG_OFF_DLY_MASK 0x00f00000
-#define BCHP_HIF_CPUBIUCTRL_CPU1_PWR_ZONE_CONFIG2_REG_DPG_OFF_DLY_SHIFT 20
-#define BCHP_HIF_CPUBIUCTRL_CPU1_PWR_ZONE_CONFIG2_REG_DPG_OFF_DLY_DEFAULT 0x00000004
-
-/* HIF_CPUBIUCTRL :: CPU1_PWR_ZONE_CONFIG2_REG :: DPG1_ON_DLY [19:16] */
-#define BCHP_HIF_CPUBIUCTRL_CPU1_PWR_ZONE_CONFIG2_REG_DPG1_ON_DLY_MASK 0x000f0000
-#define BCHP_HIF_CPUBIUCTRL_CPU1_PWR_ZONE_CONFIG2_REG_DPG1_ON_DLY_SHIFT 16
-#define BCHP_HIF_CPUBIUCTRL_CPU1_PWR_ZONE_CONFIG2_REG_DPG1_ON_DLY_DEFAULT 0x00000003
-
-/* HIF_CPUBIUCTRL :: CPU1_PWR_ZONE_CONFIG2_REG :: DPGN_ON_DLY [15:12] */
-#define BCHP_HIF_CPUBIUCTRL_CPU1_PWR_ZONE_CONFIG2_REG_DPGN_ON_DLY_MASK 0x0000f000
-#define BCHP_HIF_CPUBIUCTRL_CPU1_PWR_ZONE_CONFIG2_REG_DPGN_ON_DLY_SHIFT 12
-#define BCHP_HIF_CPUBIUCTRL_CPU1_PWR_ZONE_CONFIG2_REG_DPGN_ON_DLY_DEFAULT 0x00000001
-
-/* HIF_CPUBIUCTRL :: CPU1_PWR_ZONE_CONFIG2_REG :: reserved0 [11:06] */
-#define BCHP_HIF_CPUBIUCTRL_CPU1_PWR_ZONE_CONFIG2_REG_reserved0_MASK 0x00000fc0
-#define BCHP_HIF_CPUBIUCTRL_CPU1_PWR_ZONE_CONFIG2_REG_reserved0_SHIFT 6
-
-/* HIF_CPUBIUCTRL :: CPU1_PWR_ZONE_CONFIG2_REG :: SLEW_PRESCALE_SEL [05:03] */
-#define BCHP_HIF_CPUBIUCTRL_CPU1_PWR_ZONE_CONFIG2_REG_SLEW_PRESCALE_SEL_MASK 0x00000038
-#define BCHP_HIF_CPUBIUCTRL_CPU1_PWR_ZONE_CONFIG2_REG_SLEW_PRESCALE_SEL_SHIFT 3
-#define BCHP_HIF_CPUBIUCTRL_CPU1_PWR_ZONE_CONFIG2_REG_SLEW_PRESCALE_SEL_DEFAULT 0x00000002
-
-/* HIF_CPUBIUCTRL :: CPU1_PWR_ZONE_CONFIG2_REG :: DELAY_PRESCALE_SEL [02:00] */
-#define BCHP_HIF_CPUBIUCTRL_CPU1_PWR_ZONE_CONFIG2_REG_DELAY_PRESCALE_SEL_MASK 0x00000007
-#define BCHP_HIF_CPUBIUCTRL_CPU1_PWR_ZONE_CONFIG2_REG_DELAY_PRESCALE_SEL_SHIFT 0
-#define BCHP_HIF_CPUBIUCTRL_CPU1_PWR_ZONE_CONFIG2_REG_DELAY_PRESCALE_SEL_DEFAULT 0x00000002
-
-/***************************************************************************
- *CPU2_PWR_ZONE_CONFIG1_REG - CPU2 Power Zone Config1 Registers
- ***************************************************************************/
-/* HIF_CPUBIUCTRL :: CPU2_PWR_ZONE_CONFIG1_REG :: RST_OFF_DLY [31:28] */
-#define BCHP_HIF_CPUBIUCTRL_CPU2_PWR_ZONE_CONFIG1_REG_RST_OFF_DLY_MASK 0xf0000000
-#define BCHP_HIF_CPUBIUCTRL_CPU2_PWR_ZONE_CONFIG1_REG_RST_OFF_DLY_SHIFT 28
-#define BCHP_HIF_CPUBIUCTRL_CPU2_PWR_ZONE_CONFIG1_REG_RST_OFF_DLY_DEFAULT 0x00000004
-
-/* HIF_CPUBIUCTRL :: CPU2_PWR_ZONE_CONFIG1_REG :: RST_ON_DLY [27:24] */
-#define BCHP_HIF_CPUBIUCTRL_CPU2_PWR_ZONE_CONFIG1_REG_RST_ON_DLY_MASK 0x0f000000
-#define BCHP_HIF_CPUBIUCTRL_CPU2_PWR_ZONE_CONFIG1_REG_RST_ON_DLY_SHIFT 24
-#define BCHP_HIF_CPUBIUCTRL_CPU2_PWR_ZONE_CONFIG1_REG_RST_ON_DLY_DEFAULT 0x00000004
-
-/* HIF_CPUBIUCTRL :: CPU2_PWR_ZONE_CONFIG1_REG :: CLK_OFF_DLY [23:20] */
-#define BCHP_HIF_CPUBIUCTRL_CPU2_PWR_ZONE_CONFIG1_REG_CLK_OFF_DLY_MASK 0x00f00000
-#define BCHP_HIF_CPUBIUCTRL_CPU2_PWR_ZONE_CONFIG1_REG_CLK_OFF_DLY_SHIFT 20
-#define BCHP_HIF_CPUBIUCTRL_CPU2_PWR_ZONE_CONFIG1_REG_CLK_OFF_DLY_DEFAULT 0x00000004
-
-/* HIF_CPUBIUCTRL :: CPU2_PWR_ZONE_CONFIG1_REG :: CLK_ON_DLY [19:16] */
-#define BCHP_HIF_CPUBIUCTRL_CPU2_PWR_ZONE_CONFIG1_REG_CLK_ON_DLY_MASK 0x000f0000
-#define BCHP_HIF_CPUBIUCTRL_CPU2_PWR_ZONE_CONFIG1_REG_CLK_ON_DLY_SHIFT 16
-#define BCHP_HIF_CPUBIUCTRL_CPU2_PWR_ZONE_CONFIG1_REG_CLK_ON_DLY_DEFAULT 0x00000004
-
-/* HIF_CPUBIUCTRL :: CPU2_PWR_ZONE_CONFIG1_REG :: ISO_OFF_DLY [15:12] */
-#define BCHP_HIF_CPUBIUCTRL_CPU2_PWR_ZONE_CONFIG1_REG_ISO_OFF_DLY_MASK 0x0000f000
-#define BCHP_HIF_CPUBIUCTRL_CPU2_PWR_ZONE_CONFIG1_REG_ISO_OFF_DLY_SHIFT 12
-#define BCHP_HIF_CPUBIUCTRL_CPU2_PWR_ZONE_CONFIG1_REG_ISO_OFF_DLY_DEFAULT 0x00000004
-
-/* HIF_CPUBIUCTRL :: CPU2_PWR_ZONE_CONFIG1_REG :: ISO_ON_DLY [11:08] */
-#define BCHP_HIF_CPUBIUCTRL_CPU2_PWR_ZONE_CONFIG1_REG_ISO_ON_DLY_MASK 0x00000f00
-#define BCHP_HIF_CPUBIUCTRL_CPU2_PWR_ZONE_CONFIG1_REG_ISO_ON_DLY_SHIFT 8
-#define BCHP_HIF_CPUBIUCTRL_CPU2_PWR_ZONE_CONFIG1_REG_ISO_ON_DLY_DEFAULT 0x00000004
-
-/* HIF_CPUBIUCTRL :: CPU2_PWR_ZONE_CONFIG1_REG :: reserved0 [07:05] */
-#define BCHP_HIF_CPUBIUCTRL_CPU2_PWR_ZONE_CONFIG1_REG_reserved0_MASK 0x000000e0
-#define BCHP_HIF_CPUBIUCTRL_CPU2_PWR_ZONE_CONFIG1_REG_reserved0_SHIFT 5
-
-/* HIF_CPUBIUCTRL :: CPU2_PWR_ZONE_CONFIG1_REG :: PWROK_TRESH [04:03] */
-#define BCHP_HIF_CPUBIUCTRL_CPU2_PWR_ZONE_CONFIG1_REG_PWROK_TRESH_MASK 0x00000018
-#define BCHP_HIF_CPUBIUCTRL_CPU2_PWR_ZONE_CONFIG1_REG_PWROK_TRESH_SHIFT 3
-#define BCHP_HIF_CPUBIUCTRL_CPU2_PWR_ZONE_CONFIG1_REG_PWROK_TRESH_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: CPU2_PWR_ZONE_CONFIG1_REG :: PWROK_DELAY_SEL [02:00] */
-#define BCHP_HIF_CPUBIUCTRL_CPU2_PWR_ZONE_CONFIG1_REG_PWROK_DELAY_SEL_MASK 0x00000007
-#define BCHP_HIF_CPUBIUCTRL_CPU2_PWR_ZONE_CONFIG1_REG_PWROK_DELAY_SEL_SHIFT 0
-#define BCHP_HIF_CPUBIUCTRL_CPU2_PWR_ZONE_CONFIG1_REG_PWROK_DELAY_SEL_DEFAULT 0x00000000
-
-/***************************************************************************
- *CPU2_PWR_ZONE_CONFIG2_REG - CPU2 Power Zone Config2 Registers
- ***************************************************************************/
-/* HIF_CPUBIUCTRL :: CPU2_PWR_ZONE_CONFIG2_REG :: MEM_OFF_DLY [31:28] */
-#define BCHP_HIF_CPUBIUCTRL_CPU2_PWR_ZONE_CONFIG2_REG_MEM_OFF_DLY_MASK 0xf0000000
-#define BCHP_HIF_CPUBIUCTRL_CPU2_PWR_ZONE_CONFIG2_REG_MEM_OFF_DLY_SHIFT 28
-#define BCHP_HIF_CPUBIUCTRL_CPU2_PWR_ZONE_CONFIG2_REG_MEM_OFF_DLY_DEFAULT 0x00000004
-
-/* HIF_CPUBIUCTRL :: CPU2_PWR_ZONE_CONFIG2_REG :: MEM_ON_DLY [27:24] */
-#define BCHP_HIF_CPUBIUCTRL_CPU2_PWR_ZONE_CONFIG2_REG_MEM_ON_DLY_MASK 0x0f000000
-#define BCHP_HIF_CPUBIUCTRL_CPU2_PWR_ZONE_CONFIG2_REG_MEM_ON_DLY_SHIFT 24
-#define BCHP_HIF_CPUBIUCTRL_CPU2_PWR_ZONE_CONFIG2_REG_MEM_ON_DLY_DEFAULT 0x00000004
-
-/* HIF_CPUBIUCTRL :: CPU2_PWR_ZONE_CONFIG2_REG :: DPG_OFF_DLY [23:20] */
-#define BCHP_HIF_CPUBIUCTRL_CPU2_PWR_ZONE_CONFIG2_REG_DPG_OFF_DLY_MASK 0x00f00000
-#define BCHP_HIF_CPUBIUCTRL_CPU2_PWR_ZONE_CONFIG2_REG_DPG_OFF_DLY_SHIFT 20
-#define BCHP_HIF_CPUBIUCTRL_CPU2_PWR_ZONE_CONFIG2_REG_DPG_OFF_DLY_DEFAULT 0x00000004
-
-/* HIF_CPUBIUCTRL :: CPU2_PWR_ZONE_CONFIG2_REG :: DPG1_ON_DLY [19:16] */
-#define BCHP_HIF_CPUBIUCTRL_CPU2_PWR_ZONE_CONFIG2_REG_DPG1_ON_DLY_MASK 0x000f0000
-#define BCHP_HIF_CPUBIUCTRL_CPU2_PWR_ZONE_CONFIG2_REG_DPG1_ON_DLY_SHIFT 16
-#define BCHP_HIF_CPUBIUCTRL_CPU2_PWR_ZONE_CONFIG2_REG_DPG1_ON_DLY_DEFAULT 0x00000003
-
-/* HIF_CPUBIUCTRL :: CPU2_PWR_ZONE_CONFIG2_REG :: DPGN_ON_DLY [15:12] */
-#define BCHP_HIF_CPUBIUCTRL_CPU2_PWR_ZONE_CONFIG2_REG_DPGN_ON_DLY_MASK 0x0000f000
-#define BCHP_HIF_CPUBIUCTRL_CPU2_PWR_ZONE_CONFIG2_REG_DPGN_ON_DLY_SHIFT 12
-#define BCHP_HIF_CPUBIUCTRL_CPU2_PWR_ZONE_CONFIG2_REG_DPGN_ON_DLY_DEFAULT 0x00000001
-
-/* HIF_CPUBIUCTRL :: CPU2_PWR_ZONE_CONFIG2_REG :: reserved0 [11:06] */
-#define BCHP_HIF_CPUBIUCTRL_CPU2_PWR_ZONE_CONFIG2_REG_reserved0_MASK 0x00000fc0
-#define BCHP_HIF_CPUBIUCTRL_CPU2_PWR_ZONE_CONFIG2_REG_reserved0_SHIFT 6
-
-/* HIF_CPUBIUCTRL :: CPU2_PWR_ZONE_CONFIG2_REG :: SLEW_PRESCALE_SEL [05:03] */
-#define BCHP_HIF_CPUBIUCTRL_CPU2_PWR_ZONE_CONFIG2_REG_SLEW_PRESCALE_SEL_MASK 0x00000038
-#define BCHP_HIF_CPUBIUCTRL_CPU2_PWR_ZONE_CONFIG2_REG_SLEW_PRESCALE_SEL_SHIFT 3
-#define BCHP_HIF_CPUBIUCTRL_CPU2_PWR_ZONE_CONFIG2_REG_SLEW_PRESCALE_SEL_DEFAULT 0x00000002
-
-/* HIF_CPUBIUCTRL :: CPU2_PWR_ZONE_CONFIG2_REG :: DELAY_PRESCALE_SEL [02:00] */
-#define BCHP_HIF_CPUBIUCTRL_CPU2_PWR_ZONE_CONFIG2_REG_DELAY_PRESCALE_SEL_MASK 0x00000007
-#define BCHP_HIF_CPUBIUCTRL_CPU2_PWR_ZONE_CONFIG2_REG_DELAY_PRESCALE_SEL_SHIFT 0
-#define BCHP_HIF_CPUBIUCTRL_CPU2_PWR_ZONE_CONFIG2_REG_DELAY_PRESCALE_SEL_DEFAULT 0x00000002
-
-/***************************************************************************
- *CPU3_PWR_ZONE_CONFIG1_REG - CPU3 Power Zone Config1 Registers
- ***************************************************************************/
-/* HIF_CPUBIUCTRL :: CPU3_PWR_ZONE_CONFIG1_REG :: RST_OFF_DLY [31:28] */
-#define BCHP_HIF_CPUBIUCTRL_CPU3_PWR_ZONE_CONFIG1_REG_RST_OFF_DLY_MASK 0xf0000000
-#define BCHP_HIF_CPUBIUCTRL_CPU3_PWR_ZONE_CONFIG1_REG_RST_OFF_DLY_SHIFT 28
-#define BCHP_HIF_CPUBIUCTRL_CPU3_PWR_ZONE_CONFIG1_REG_RST_OFF_DLY_DEFAULT 0x00000004
-
-/* HIF_CPUBIUCTRL :: CPU3_PWR_ZONE_CONFIG1_REG :: RST_ON_DLY [27:24] */
-#define BCHP_HIF_CPUBIUCTRL_CPU3_PWR_ZONE_CONFIG1_REG_RST_ON_DLY_MASK 0x0f000000
-#define BCHP_HIF_CPUBIUCTRL_CPU3_PWR_ZONE_CONFIG1_REG_RST_ON_DLY_SHIFT 24
-#define BCHP_HIF_CPUBIUCTRL_CPU3_PWR_ZONE_CONFIG1_REG_RST_ON_DLY_DEFAULT 0x00000004
-
-/* HIF_CPUBIUCTRL :: CPU3_PWR_ZONE_CONFIG1_REG :: CLK_OFF_DLY [23:20] */
-#define BCHP_HIF_CPUBIUCTRL_CPU3_PWR_ZONE_CONFIG1_REG_CLK_OFF_DLY_MASK 0x00f00000
-#define BCHP_HIF_CPUBIUCTRL_CPU3_PWR_ZONE_CONFIG1_REG_CLK_OFF_DLY_SHIFT 20
-#define BCHP_HIF_CPUBIUCTRL_CPU3_PWR_ZONE_CONFIG1_REG_CLK_OFF_DLY_DEFAULT 0x00000004
-
-/* HIF_CPUBIUCTRL :: CPU3_PWR_ZONE_CONFIG1_REG :: CLK_ON_DLY [19:16] */
-#define BCHP_HIF_CPUBIUCTRL_CPU3_PWR_ZONE_CONFIG1_REG_CLK_ON_DLY_MASK 0x000f0000
-#define BCHP_HIF_CPUBIUCTRL_CPU3_PWR_ZONE_CONFIG1_REG_CLK_ON_DLY_SHIFT 16
-#define BCHP_HIF_CPUBIUCTRL_CPU3_PWR_ZONE_CONFIG1_REG_CLK_ON_DLY_DEFAULT 0x00000004
-
-/* HIF_CPUBIUCTRL :: CPU3_PWR_ZONE_CONFIG1_REG :: ISO_OFF_DLY [15:12] */
-#define BCHP_HIF_CPUBIUCTRL_CPU3_PWR_ZONE_CONFIG1_REG_ISO_OFF_DLY_MASK 0x0000f000
-#define BCHP_HIF_CPUBIUCTRL_CPU3_PWR_ZONE_CONFIG1_REG_ISO_OFF_DLY_SHIFT 12
-#define BCHP_HIF_CPUBIUCTRL_CPU3_PWR_ZONE_CONFIG1_REG_ISO_OFF_DLY_DEFAULT 0x00000004
-
-/* HIF_CPUBIUCTRL :: CPU3_PWR_ZONE_CONFIG1_REG :: ISO_ON_DLY [11:08] */
-#define BCHP_HIF_CPUBIUCTRL_CPU3_PWR_ZONE_CONFIG1_REG_ISO_ON_DLY_MASK 0x00000f00
-#define BCHP_HIF_CPUBIUCTRL_CPU3_PWR_ZONE_CONFIG1_REG_ISO_ON_DLY_SHIFT 8
-#define BCHP_HIF_CPUBIUCTRL_CPU3_PWR_ZONE_CONFIG1_REG_ISO_ON_DLY_DEFAULT 0x00000004
-
-/* HIF_CPUBIUCTRL :: CPU3_PWR_ZONE_CONFIG1_REG :: reserved0 [07:05] */
-#define BCHP_HIF_CPUBIUCTRL_CPU3_PWR_ZONE_CONFIG1_REG_reserved0_MASK 0x000000e0
-#define BCHP_HIF_CPUBIUCTRL_CPU3_PWR_ZONE_CONFIG1_REG_reserved0_SHIFT 5
-
-/* HIF_CPUBIUCTRL :: CPU3_PWR_ZONE_CONFIG1_REG :: PWROK_TRESH [04:03] */
-#define BCHP_HIF_CPUBIUCTRL_CPU3_PWR_ZONE_CONFIG1_REG_PWROK_TRESH_MASK 0x00000018
-#define BCHP_HIF_CPUBIUCTRL_CPU3_PWR_ZONE_CONFIG1_REG_PWROK_TRESH_SHIFT 3
-#define BCHP_HIF_CPUBIUCTRL_CPU3_PWR_ZONE_CONFIG1_REG_PWROK_TRESH_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: CPU3_PWR_ZONE_CONFIG1_REG :: PWROK_DELAY_SEL [02:00] */
-#define BCHP_HIF_CPUBIUCTRL_CPU3_PWR_ZONE_CONFIG1_REG_PWROK_DELAY_SEL_MASK 0x00000007
-#define BCHP_HIF_CPUBIUCTRL_CPU3_PWR_ZONE_CONFIG1_REG_PWROK_DELAY_SEL_SHIFT 0
-#define BCHP_HIF_CPUBIUCTRL_CPU3_PWR_ZONE_CONFIG1_REG_PWROK_DELAY_SEL_DEFAULT 0x00000000
-
-/***************************************************************************
- *CPU3_PWR_ZONE_CONFIG2_REG - CPU3 Power Zone Config2 Registers
- ***************************************************************************/
-/* HIF_CPUBIUCTRL :: CPU3_PWR_ZONE_CONFIG2_REG :: MEM_OFF_DLY [31:28] */
-#define BCHP_HIF_CPUBIUCTRL_CPU3_PWR_ZONE_CONFIG2_REG_MEM_OFF_DLY_MASK 0xf0000000
-#define BCHP_HIF_CPUBIUCTRL_CPU3_PWR_ZONE_CONFIG2_REG_MEM_OFF_DLY_SHIFT 28
-#define BCHP_HIF_CPUBIUCTRL_CPU3_PWR_ZONE_CONFIG2_REG_MEM_OFF_DLY_DEFAULT 0x00000004
-
-/* HIF_CPUBIUCTRL :: CPU3_PWR_ZONE_CONFIG2_REG :: MEM_ON_DLY [27:24] */
-#define BCHP_HIF_CPUBIUCTRL_CPU3_PWR_ZONE_CONFIG2_REG_MEM_ON_DLY_MASK 0x0f000000
-#define BCHP_HIF_CPUBIUCTRL_CPU3_PWR_ZONE_CONFIG2_REG_MEM_ON_DLY_SHIFT 24
-#define BCHP_HIF_CPUBIUCTRL_CPU3_PWR_ZONE_CONFIG2_REG_MEM_ON_DLY_DEFAULT 0x00000004
-
-/* HIF_CPUBIUCTRL :: CPU3_PWR_ZONE_CONFIG2_REG :: DPG_OFF_DLY [23:20] */
-#define BCHP_HIF_CPUBIUCTRL_CPU3_PWR_ZONE_CONFIG2_REG_DPG_OFF_DLY_MASK 0x00f00000
-#define BCHP_HIF_CPUBIUCTRL_CPU3_PWR_ZONE_CONFIG2_REG_DPG_OFF_DLY_SHIFT 20
-#define BCHP_HIF_CPUBIUCTRL_CPU3_PWR_ZONE_CONFIG2_REG_DPG_OFF_DLY_DEFAULT 0x00000004
-
-/* HIF_CPUBIUCTRL :: CPU3_PWR_ZONE_CONFIG2_REG :: DPG1_ON_DLY [19:16] */
-#define BCHP_HIF_CPUBIUCTRL_CPU3_PWR_ZONE_CONFIG2_REG_DPG1_ON_DLY_MASK 0x000f0000
-#define BCHP_HIF_CPUBIUCTRL_CPU3_PWR_ZONE_CONFIG2_REG_DPG1_ON_DLY_SHIFT 16
-#define BCHP_HIF_CPUBIUCTRL_CPU3_PWR_ZONE_CONFIG2_REG_DPG1_ON_DLY_DEFAULT 0x00000003
-
-/* HIF_CPUBIUCTRL :: CPU3_PWR_ZONE_CONFIG2_REG :: DPGN_ON_DLY [15:12] */
-#define BCHP_HIF_CPUBIUCTRL_CPU3_PWR_ZONE_CONFIG2_REG_DPGN_ON_DLY_MASK 0x0000f000
-#define BCHP_HIF_CPUBIUCTRL_CPU3_PWR_ZONE_CONFIG2_REG_DPGN_ON_DLY_SHIFT 12
-#define BCHP_HIF_CPUBIUCTRL_CPU3_PWR_ZONE_CONFIG2_REG_DPGN_ON_DLY_DEFAULT 0x00000001
-
-/* HIF_CPUBIUCTRL :: CPU3_PWR_ZONE_CONFIG2_REG :: reserved0 [11:06] */
-#define BCHP_HIF_CPUBIUCTRL_CPU3_PWR_ZONE_CONFIG2_REG_reserved0_MASK 0x00000fc0
-#define BCHP_HIF_CPUBIUCTRL_CPU3_PWR_ZONE_CONFIG2_REG_reserved0_SHIFT 6
-
-/* HIF_CPUBIUCTRL :: CPU3_PWR_ZONE_CONFIG2_REG :: SLEW_PRESCALE_SEL [05:03] */
-#define BCHP_HIF_CPUBIUCTRL_CPU3_PWR_ZONE_CONFIG2_REG_SLEW_PRESCALE_SEL_MASK 0x00000038
-#define BCHP_HIF_CPUBIUCTRL_CPU3_PWR_ZONE_CONFIG2_REG_SLEW_PRESCALE_SEL_SHIFT 3
-#define BCHP_HIF_CPUBIUCTRL_CPU3_PWR_ZONE_CONFIG2_REG_SLEW_PRESCALE_SEL_DEFAULT 0x00000002
-
-/* HIF_CPUBIUCTRL :: CPU3_PWR_ZONE_CONFIG2_REG :: DELAY_PRESCALE_SEL [02:00] */
-#define BCHP_HIF_CPUBIUCTRL_CPU3_PWR_ZONE_CONFIG2_REG_DELAY_PRESCALE_SEL_MASK 0x00000007
-#define BCHP_HIF_CPUBIUCTRL_CPU3_PWR_ZONE_CONFIG2_REG_DELAY_PRESCALE_SEL_SHIFT 0
-#define BCHP_HIF_CPUBIUCTRL_CPU3_PWR_ZONE_CONFIG2_REG_DELAY_PRESCALE_SEL_DEFAULT 0x00000002
-
-/***************************************************************************
- *L2BIU_PWR_ZONE_CONFIG1_REG - L2/BIU Power Zone Config1 Registers
- ***************************************************************************/
-/* HIF_CPUBIUCTRL :: L2BIU_PWR_ZONE_CONFIG1_REG :: RST_OFF_DLY [31:28] */
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_PWR_ZONE_CONFIG1_REG_RST_OFF_DLY_MASK 0xf0000000
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_PWR_ZONE_CONFIG1_REG_RST_OFF_DLY_SHIFT 28
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_PWR_ZONE_CONFIG1_REG_RST_OFF_DLY_DEFAULT 0x00000004
-
-/* HIF_CPUBIUCTRL :: L2BIU_PWR_ZONE_CONFIG1_REG :: RST_ON_DLY [27:24] */
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_PWR_ZONE_CONFIG1_REG_RST_ON_DLY_MASK 0x0f000000
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_PWR_ZONE_CONFIG1_REG_RST_ON_DLY_SHIFT 24
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_PWR_ZONE_CONFIG1_REG_RST_ON_DLY_DEFAULT 0x00000004
-
-/* HIF_CPUBIUCTRL :: L2BIU_PWR_ZONE_CONFIG1_REG :: CLK_OFF_DLY [23:20] */
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_PWR_ZONE_CONFIG1_REG_CLK_OFF_DLY_MASK 0x00f00000
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_PWR_ZONE_CONFIG1_REG_CLK_OFF_DLY_SHIFT 20
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_PWR_ZONE_CONFIG1_REG_CLK_OFF_DLY_DEFAULT 0x00000004
-
-/* HIF_CPUBIUCTRL :: L2BIU_PWR_ZONE_CONFIG1_REG :: CLK_ON_DLY [19:16] */
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_PWR_ZONE_CONFIG1_REG_CLK_ON_DLY_MASK 0x000f0000
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_PWR_ZONE_CONFIG1_REG_CLK_ON_DLY_SHIFT 16
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_PWR_ZONE_CONFIG1_REG_CLK_ON_DLY_DEFAULT 0x00000004
-
-/* HIF_CPUBIUCTRL :: L2BIU_PWR_ZONE_CONFIG1_REG :: ISO_OFF_DLY [15:12] */
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_PWR_ZONE_CONFIG1_REG_ISO_OFF_DLY_MASK 0x0000f000
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_PWR_ZONE_CONFIG1_REG_ISO_OFF_DLY_SHIFT 12
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_PWR_ZONE_CONFIG1_REG_ISO_OFF_DLY_DEFAULT 0x00000004
-
-/* HIF_CPUBIUCTRL :: L2BIU_PWR_ZONE_CONFIG1_REG :: ISO_ON_DLY [11:08] */
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_PWR_ZONE_CONFIG1_REG_ISO_ON_DLY_MASK 0x00000f00
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_PWR_ZONE_CONFIG1_REG_ISO_ON_DLY_SHIFT 8
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_PWR_ZONE_CONFIG1_REG_ISO_ON_DLY_DEFAULT 0x00000004
-
-/* HIF_CPUBIUCTRL :: L2BIU_PWR_ZONE_CONFIG1_REG :: reserved0 [07:05] */
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_PWR_ZONE_CONFIG1_REG_reserved0_MASK 0x000000e0
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_PWR_ZONE_CONFIG1_REG_reserved0_SHIFT 5
-
-/* HIF_CPUBIUCTRL :: L2BIU_PWR_ZONE_CONFIG1_REG :: PWROK_TRESH [04:03] */
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_PWR_ZONE_CONFIG1_REG_PWROK_TRESH_MASK 0x00000018
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_PWR_ZONE_CONFIG1_REG_PWROK_TRESH_SHIFT 3
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_PWR_ZONE_CONFIG1_REG_PWROK_TRESH_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: L2BIU_PWR_ZONE_CONFIG1_REG :: PWROK_DELAY_SEL [02:00] */
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_PWR_ZONE_CONFIG1_REG_PWROK_DELAY_SEL_MASK 0x00000007
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_PWR_ZONE_CONFIG1_REG_PWROK_DELAY_SEL_SHIFT 0
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_PWR_ZONE_CONFIG1_REG_PWROK_DELAY_SEL_DEFAULT 0x00000000
-
-/***************************************************************************
- *L2BIU_PWR_ZONE_CONFIG2_REG - L2/BIU Power Zone Config2 Registers
- ***************************************************************************/
-/* HIF_CPUBIUCTRL :: L2BIU_PWR_ZONE_CONFIG2_REG :: MEM_OFF_DLY [31:28] */
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_PWR_ZONE_CONFIG2_REG_MEM_OFF_DLY_MASK 0xf0000000
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_PWR_ZONE_CONFIG2_REG_MEM_OFF_DLY_SHIFT 28
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_PWR_ZONE_CONFIG2_REG_MEM_OFF_DLY_DEFAULT 0x00000004
-
-/* HIF_CPUBIUCTRL :: L2BIU_PWR_ZONE_CONFIG2_REG :: MEM_ON_DLY [27:24] */
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_PWR_ZONE_CONFIG2_REG_MEM_ON_DLY_MASK 0x0f000000
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_PWR_ZONE_CONFIG2_REG_MEM_ON_DLY_SHIFT 24
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_PWR_ZONE_CONFIG2_REG_MEM_ON_DLY_DEFAULT 0x00000004
-
-/* HIF_CPUBIUCTRL :: L2BIU_PWR_ZONE_CONFIG2_REG :: DPG_OFF_DLY [23:20] */
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_PWR_ZONE_CONFIG2_REG_DPG_OFF_DLY_MASK 0x00f00000
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_PWR_ZONE_CONFIG2_REG_DPG_OFF_DLY_SHIFT 20
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_PWR_ZONE_CONFIG2_REG_DPG_OFF_DLY_DEFAULT 0x00000004
-
-/* HIF_CPUBIUCTRL :: L2BIU_PWR_ZONE_CONFIG2_REG :: DPG1_ON_DLY [19:16] */
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_PWR_ZONE_CONFIG2_REG_DPG1_ON_DLY_MASK 0x000f0000
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_PWR_ZONE_CONFIG2_REG_DPG1_ON_DLY_SHIFT 16
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_PWR_ZONE_CONFIG2_REG_DPG1_ON_DLY_DEFAULT 0x00000003
-
-/* HIF_CPUBIUCTRL :: L2BIU_PWR_ZONE_CONFIG2_REG :: DPGN_ON_DLY [15:12] */
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_PWR_ZONE_CONFIG2_REG_DPGN_ON_DLY_MASK 0x0000f000
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_PWR_ZONE_CONFIG2_REG_DPGN_ON_DLY_SHIFT 12
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_PWR_ZONE_CONFIG2_REG_DPGN_ON_DLY_DEFAULT 0x00000001
-
-/* HIF_CPUBIUCTRL :: L2BIU_PWR_ZONE_CONFIG2_REG :: reserved0 [11:06] */
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_PWR_ZONE_CONFIG2_REG_reserved0_MASK 0x00000fc0
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_PWR_ZONE_CONFIG2_REG_reserved0_SHIFT 6
-
-/* HIF_CPUBIUCTRL :: L2BIU_PWR_ZONE_CONFIG2_REG :: SLEW_PRESCALE_SEL [05:03] */
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_PWR_ZONE_CONFIG2_REG_SLEW_PRESCALE_SEL_MASK 0x00000038
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_PWR_ZONE_CONFIG2_REG_SLEW_PRESCALE_SEL_SHIFT 3
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_PWR_ZONE_CONFIG2_REG_SLEW_PRESCALE_SEL_DEFAULT 0x00000002
-
-/* HIF_CPUBIUCTRL :: L2BIU_PWR_ZONE_CONFIG2_REG :: DELAY_PRESCALE_SEL [02:00] */
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_PWR_ZONE_CONFIG2_REG_DELAY_PRESCALE_SEL_MASK 0x00000007
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_PWR_ZONE_CONFIG2_REG_DELAY_PRESCALE_SEL_SHIFT 0
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_PWR_ZONE_CONFIG2_REG_DELAY_PRESCALE_SEL_DEFAULT 0x00000002
-
-/***************************************************************************
- *CPU0_PWR_FREQ_SCALAR_CTRL_REG - CPU0 BPCM Frequency Scalar Control Register
- ***************************************************************************/
-/* HIF_CPUBIUCTRL :: CPU0_PWR_FREQ_SCALAR_CTRL_REG :: reserved0 [31:10] */
-#define BCHP_HIF_CPUBIUCTRL_CPU0_PWR_FREQ_SCALAR_CTRL_REG_reserved0_MASK 0xfffffc00
-#define BCHP_HIF_CPUBIUCTRL_CPU0_PWR_FREQ_SCALAR_CTRL_REG_reserved0_SHIFT 10
-
-/* HIF_CPUBIUCTRL :: CPU0_PWR_FREQ_SCALAR_CTRL_REG :: HIGH_GEAR_DIV [09:07] */
-#define BCHP_HIF_CPUBIUCTRL_CPU0_PWR_FREQ_SCALAR_CTRL_REG_HIGH_GEAR_DIV_MASK 0x00000380
-#define BCHP_HIF_CPUBIUCTRL_CPU0_PWR_FREQ_SCALAR_CTRL_REG_HIGH_GEAR_DIV_SHIFT 7
-#define BCHP_HIF_CPUBIUCTRL_CPU0_PWR_FREQ_SCALAR_CTRL_REG_HIGH_GEAR_DIV_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: CPU0_PWR_FREQ_SCALAR_CTRL_REG :: LOW_GEAR_DIV [06:04] */
-#define BCHP_HIF_CPUBIUCTRL_CPU0_PWR_FREQ_SCALAR_CTRL_REG_LOW_GEAR_DIV_MASK 0x00000070
-#define BCHP_HIF_CPUBIUCTRL_CPU0_PWR_FREQ_SCALAR_CTRL_REG_LOW_GEAR_DIV_SHIFT 4
-#define BCHP_HIF_CPUBIUCTRL_CPU0_PWR_FREQ_SCALAR_CTRL_REG_LOW_GEAR_DIV_DEFAULT 0x00000001
-
-/* HIF_CPUBIUCTRL :: CPU0_PWR_FREQ_SCALAR_CTRL_REG :: reserved1 [03:03] */
-#define BCHP_HIF_CPUBIUCTRL_CPU0_PWR_FREQ_SCALAR_CTRL_REG_reserved1_MASK 0x00000008
-#define BCHP_HIF_CPUBIUCTRL_CPU0_PWR_FREQ_SCALAR_CTRL_REG_reserved1_SHIFT 3
-
-/* HIF_CPUBIUCTRL :: CPU0_PWR_FREQ_SCALAR_CTRL_REG :: USE_DYN_GEAR_SEL [02:02] */
-#define BCHP_HIF_CPUBIUCTRL_CPU0_PWR_FREQ_SCALAR_CTRL_REG_USE_DYN_GEAR_SEL_MASK 0x00000004
-#define BCHP_HIF_CPUBIUCTRL_CPU0_PWR_FREQ_SCALAR_CTRL_REG_USE_DYN_GEAR_SEL_SHIFT 2
-#define BCHP_HIF_CPUBIUCTRL_CPU0_PWR_FREQ_SCALAR_CTRL_REG_USE_DYN_GEAR_SEL_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: CPU0_PWR_FREQ_SCALAR_CTRL_REG :: GEAR_SELECT [01:01] */
-#define BCHP_HIF_CPUBIUCTRL_CPU0_PWR_FREQ_SCALAR_CTRL_REG_GEAR_SELECT_MASK 0x00000002
-#define BCHP_HIF_CPUBIUCTRL_CPU0_PWR_FREQ_SCALAR_CTRL_REG_GEAR_SELECT_SHIFT 1
-#define BCHP_HIF_CPUBIUCTRL_CPU0_PWR_FREQ_SCALAR_CTRL_REG_GEAR_SELECT_DEFAULT 0x00000001
-
-/* HIF_CPUBIUCTRL :: CPU0_PWR_FREQ_SCALAR_CTRL_REG :: FS_BYPASS_EN [00:00] */
-#define BCHP_HIF_CPUBIUCTRL_CPU0_PWR_FREQ_SCALAR_CTRL_REG_FS_BYPASS_EN_MASK 0x00000001
-#define BCHP_HIF_CPUBIUCTRL_CPU0_PWR_FREQ_SCALAR_CTRL_REG_FS_BYPASS_EN_SHIFT 0
-#define BCHP_HIF_CPUBIUCTRL_CPU0_PWR_FREQ_SCALAR_CTRL_REG_FS_BYPASS_EN_DEFAULT 0x00000000
-
-/***************************************************************************
- *CPU1_PWR_FREQ_SCALAR_CTRL_REG - CPU1 BPCM Frequency Scalar Control Register
- ***************************************************************************/
-/* HIF_CPUBIUCTRL :: CPU1_PWR_FREQ_SCALAR_CTRL_REG :: reserved0 [31:10] */
-#define BCHP_HIF_CPUBIUCTRL_CPU1_PWR_FREQ_SCALAR_CTRL_REG_reserved0_MASK 0xfffffc00
-#define BCHP_HIF_CPUBIUCTRL_CPU1_PWR_FREQ_SCALAR_CTRL_REG_reserved0_SHIFT 10
-
-/* HIF_CPUBIUCTRL :: CPU1_PWR_FREQ_SCALAR_CTRL_REG :: HIGH_GEAR_DIV [09:07] */
-#define BCHP_HIF_CPUBIUCTRL_CPU1_PWR_FREQ_SCALAR_CTRL_REG_HIGH_GEAR_DIV_MASK 0x00000380
-#define BCHP_HIF_CPUBIUCTRL_CPU1_PWR_FREQ_SCALAR_CTRL_REG_HIGH_GEAR_DIV_SHIFT 7
-#define BCHP_HIF_CPUBIUCTRL_CPU1_PWR_FREQ_SCALAR_CTRL_REG_HIGH_GEAR_DIV_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: CPU1_PWR_FREQ_SCALAR_CTRL_REG :: LOW_GEAR_DIV [06:04] */
-#define BCHP_HIF_CPUBIUCTRL_CPU1_PWR_FREQ_SCALAR_CTRL_REG_LOW_GEAR_DIV_MASK 0x00000070
-#define BCHP_HIF_CPUBIUCTRL_CPU1_PWR_FREQ_SCALAR_CTRL_REG_LOW_GEAR_DIV_SHIFT 4
-#define BCHP_HIF_CPUBIUCTRL_CPU1_PWR_FREQ_SCALAR_CTRL_REG_LOW_GEAR_DIV_DEFAULT 0x00000001
-
-/* HIF_CPUBIUCTRL :: CPU1_PWR_FREQ_SCALAR_CTRL_REG :: reserved1 [03:03] */
-#define BCHP_HIF_CPUBIUCTRL_CPU1_PWR_FREQ_SCALAR_CTRL_REG_reserved1_MASK 0x00000008
-#define BCHP_HIF_CPUBIUCTRL_CPU1_PWR_FREQ_SCALAR_CTRL_REG_reserved1_SHIFT 3
-
-/* HIF_CPUBIUCTRL :: CPU1_PWR_FREQ_SCALAR_CTRL_REG :: USE_DYN_GEAR_SEL [02:02] */
-#define BCHP_HIF_CPUBIUCTRL_CPU1_PWR_FREQ_SCALAR_CTRL_REG_USE_DYN_GEAR_SEL_MASK 0x00000004
-#define BCHP_HIF_CPUBIUCTRL_CPU1_PWR_FREQ_SCALAR_CTRL_REG_USE_DYN_GEAR_SEL_SHIFT 2
-#define BCHP_HIF_CPUBIUCTRL_CPU1_PWR_FREQ_SCALAR_CTRL_REG_USE_DYN_GEAR_SEL_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: CPU1_PWR_FREQ_SCALAR_CTRL_REG :: GEAR_SELECT [01:01] */
-#define BCHP_HIF_CPUBIUCTRL_CPU1_PWR_FREQ_SCALAR_CTRL_REG_GEAR_SELECT_MASK 0x00000002
-#define BCHP_HIF_CPUBIUCTRL_CPU1_PWR_FREQ_SCALAR_CTRL_REG_GEAR_SELECT_SHIFT 1
-#define BCHP_HIF_CPUBIUCTRL_CPU1_PWR_FREQ_SCALAR_CTRL_REG_GEAR_SELECT_DEFAULT 0x00000001
-
-/* HIF_CPUBIUCTRL :: CPU1_PWR_FREQ_SCALAR_CTRL_REG :: FS_BYPASS_EN [00:00] */
-#define BCHP_HIF_CPUBIUCTRL_CPU1_PWR_FREQ_SCALAR_CTRL_REG_FS_BYPASS_EN_MASK 0x00000001
-#define BCHP_HIF_CPUBIUCTRL_CPU1_PWR_FREQ_SCALAR_CTRL_REG_FS_BYPASS_EN_SHIFT 0
-#define BCHP_HIF_CPUBIUCTRL_CPU1_PWR_FREQ_SCALAR_CTRL_REG_FS_BYPASS_EN_DEFAULT 0x00000000
-
-/***************************************************************************
- *CPU2_PWR_FREQ_SCALAR_CTRL_REG - CPU2 BPCM Frequency Scalar Control Register
- ***************************************************************************/
-/* HIF_CPUBIUCTRL :: CPU2_PWR_FREQ_SCALAR_CTRL_REG :: reserved0 [31:10] */
-#define BCHP_HIF_CPUBIUCTRL_CPU2_PWR_FREQ_SCALAR_CTRL_REG_reserved0_MASK 0xfffffc00
-#define BCHP_HIF_CPUBIUCTRL_CPU2_PWR_FREQ_SCALAR_CTRL_REG_reserved0_SHIFT 10
-
-/* HIF_CPUBIUCTRL :: CPU2_PWR_FREQ_SCALAR_CTRL_REG :: HIGH_GEAR_DIV [09:07] */
-#define BCHP_HIF_CPUBIUCTRL_CPU2_PWR_FREQ_SCALAR_CTRL_REG_HIGH_GEAR_DIV_MASK 0x00000380
-#define BCHP_HIF_CPUBIUCTRL_CPU2_PWR_FREQ_SCALAR_CTRL_REG_HIGH_GEAR_DIV_SHIFT 7
-#define BCHP_HIF_CPUBIUCTRL_CPU2_PWR_FREQ_SCALAR_CTRL_REG_HIGH_GEAR_DIV_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: CPU2_PWR_FREQ_SCALAR_CTRL_REG :: LOW_GEAR_DIV [06:04] */
-#define BCHP_HIF_CPUBIUCTRL_CPU2_PWR_FREQ_SCALAR_CTRL_REG_LOW_GEAR_DIV_MASK 0x00000070
-#define BCHP_HIF_CPUBIUCTRL_CPU2_PWR_FREQ_SCALAR_CTRL_REG_LOW_GEAR_DIV_SHIFT 4
-#define BCHP_HIF_CPUBIUCTRL_CPU2_PWR_FREQ_SCALAR_CTRL_REG_LOW_GEAR_DIV_DEFAULT 0x00000001
-
-/* HIF_CPUBIUCTRL :: CPU2_PWR_FREQ_SCALAR_CTRL_REG :: reserved1 [03:03] */
-#define BCHP_HIF_CPUBIUCTRL_CPU2_PWR_FREQ_SCALAR_CTRL_REG_reserved1_MASK 0x00000008
-#define BCHP_HIF_CPUBIUCTRL_CPU2_PWR_FREQ_SCALAR_CTRL_REG_reserved1_SHIFT 3
-
-/* HIF_CPUBIUCTRL :: CPU2_PWR_FREQ_SCALAR_CTRL_REG :: USE_DYN_GEAR_SEL [02:02] */
-#define BCHP_HIF_CPUBIUCTRL_CPU2_PWR_FREQ_SCALAR_CTRL_REG_USE_DYN_GEAR_SEL_MASK 0x00000004
-#define BCHP_HIF_CPUBIUCTRL_CPU2_PWR_FREQ_SCALAR_CTRL_REG_USE_DYN_GEAR_SEL_SHIFT 2
-#define BCHP_HIF_CPUBIUCTRL_CPU2_PWR_FREQ_SCALAR_CTRL_REG_USE_DYN_GEAR_SEL_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: CPU2_PWR_FREQ_SCALAR_CTRL_REG :: GEAR_SELECT [01:01] */
-#define BCHP_HIF_CPUBIUCTRL_CPU2_PWR_FREQ_SCALAR_CTRL_REG_GEAR_SELECT_MASK 0x00000002
-#define BCHP_HIF_CPUBIUCTRL_CPU2_PWR_FREQ_SCALAR_CTRL_REG_GEAR_SELECT_SHIFT 1
-#define BCHP_HIF_CPUBIUCTRL_CPU2_PWR_FREQ_SCALAR_CTRL_REG_GEAR_SELECT_DEFAULT 0x00000001
-
-/* HIF_CPUBIUCTRL :: CPU2_PWR_FREQ_SCALAR_CTRL_REG :: FS_BYPASS_EN [00:00] */
-#define BCHP_HIF_CPUBIUCTRL_CPU2_PWR_FREQ_SCALAR_CTRL_REG_FS_BYPASS_EN_MASK 0x00000001
-#define BCHP_HIF_CPUBIUCTRL_CPU2_PWR_FREQ_SCALAR_CTRL_REG_FS_BYPASS_EN_SHIFT 0
-#define BCHP_HIF_CPUBIUCTRL_CPU2_PWR_FREQ_SCALAR_CTRL_REG_FS_BYPASS_EN_DEFAULT 0x00000000
-
-/***************************************************************************
- *CPU3_PWR_FREQ_SCALAR_CTRL_REG - CPU3 BPCM Frequency Scalar Control Register
- ***************************************************************************/
-/* HIF_CPUBIUCTRL :: CPU3_PWR_FREQ_SCALAR_CTRL_REG :: reserved0 [31:10] */
-#define BCHP_HIF_CPUBIUCTRL_CPU3_PWR_FREQ_SCALAR_CTRL_REG_reserved0_MASK 0xfffffc00
-#define BCHP_HIF_CPUBIUCTRL_CPU3_PWR_FREQ_SCALAR_CTRL_REG_reserved0_SHIFT 10
-
-/* HIF_CPUBIUCTRL :: CPU3_PWR_FREQ_SCALAR_CTRL_REG :: HIGH_GEAR_DIV [09:07] */
-#define BCHP_HIF_CPUBIUCTRL_CPU3_PWR_FREQ_SCALAR_CTRL_REG_HIGH_GEAR_DIV_MASK 0x00000380
-#define BCHP_HIF_CPUBIUCTRL_CPU3_PWR_FREQ_SCALAR_CTRL_REG_HIGH_GEAR_DIV_SHIFT 7
-#define BCHP_HIF_CPUBIUCTRL_CPU3_PWR_FREQ_SCALAR_CTRL_REG_HIGH_GEAR_DIV_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: CPU3_PWR_FREQ_SCALAR_CTRL_REG :: LOW_GEAR_DIV [06:04] */
-#define BCHP_HIF_CPUBIUCTRL_CPU3_PWR_FREQ_SCALAR_CTRL_REG_LOW_GEAR_DIV_MASK 0x00000070
-#define BCHP_HIF_CPUBIUCTRL_CPU3_PWR_FREQ_SCALAR_CTRL_REG_LOW_GEAR_DIV_SHIFT 4
-#define BCHP_HIF_CPUBIUCTRL_CPU3_PWR_FREQ_SCALAR_CTRL_REG_LOW_GEAR_DIV_DEFAULT 0x00000001
-
-/* HIF_CPUBIUCTRL :: CPU3_PWR_FREQ_SCALAR_CTRL_REG :: reserved1 [03:03] */
-#define BCHP_HIF_CPUBIUCTRL_CPU3_PWR_FREQ_SCALAR_CTRL_REG_reserved1_MASK 0x00000008
-#define BCHP_HIF_CPUBIUCTRL_CPU3_PWR_FREQ_SCALAR_CTRL_REG_reserved1_SHIFT 3
-
-/* HIF_CPUBIUCTRL :: CPU3_PWR_FREQ_SCALAR_CTRL_REG :: USE_DYN_GEAR_SEL [02:02] */
-#define BCHP_HIF_CPUBIUCTRL_CPU3_PWR_FREQ_SCALAR_CTRL_REG_USE_DYN_GEAR_SEL_MASK 0x00000004
-#define BCHP_HIF_CPUBIUCTRL_CPU3_PWR_FREQ_SCALAR_CTRL_REG_USE_DYN_GEAR_SEL_SHIFT 2
-#define BCHP_HIF_CPUBIUCTRL_CPU3_PWR_FREQ_SCALAR_CTRL_REG_USE_DYN_GEAR_SEL_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: CPU3_PWR_FREQ_SCALAR_CTRL_REG :: GEAR_SELECT [01:01] */
-#define BCHP_HIF_CPUBIUCTRL_CPU3_PWR_FREQ_SCALAR_CTRL_REG_GEAR_SELECT_MASK 0x00000002
-#define BCHP_HIF_CPUBIUCTRL_CPU3_PWR_FREQ_SCALAR_CTRL_REG_GEAR_SELECT_SHIFT 1
-#define BCHP_HIF_CPUBIUCTRL_CPU3_PWR_FREQ_SCALAR_CTRL_REG_GEAR_SELECT_DEFAULT 0x00000001
-
-/* HIF_CPUBIUCTRL :: CPU3_PWR_FREQ_SCALAR_CTRL_REG :: FS_BYPASS_EN [00:00] */
-#define BCHP_HIF_CPUBIUCTRL_CPU3_PWR_FREQ_SCALAR_CTRL_REG_FS_BYPASS_EN_MASK 0x00000001
-#define BCHP_HIF_CPUBIUCTRL_CPU3_PWR_FREQ_SCALAR_CTRL_REG_FS_BYPASS_EN_SHIFT 0
-#define BCHP_HIF_CPUBIUCTRL_CPU3_PWR_FREQ_SCALAR_CTRL_REG_FS_BYPASS_EN_DEFAULT 0x00000000
-
-/***************************************************************************
- *L2BIU_PWR_FREQ_SCALAR_CTRL_REG - L2/BIU BPCM Frequency Scalar Control Register
- ***************************************************************************/
-/* HIF_CPUBIUCTRL :: L2BIU_PWR_FREQ_SCALAR_CTRL_REG :: reserved0 [31:10] */
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_PWR_FREQ_SCALAR_CTRL_REG_reserved0_MASK 0xfffffc00
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_PWR_FREQ_SCALAR_CTRL_REG_reserved0_SHIFT 10
-
-/* HIF_CPUBIUCTRL :: L2BIU_PWR_FREQ_SCALAR_CTRL_REG :: HIGH_GEAR_DIV [09:07] */
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_PWR_FREQ_SCALAR_CTRL_REG_HIGH_GEAR_DIV_MASK 0x00000380
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_PWR_FREQ_SCALAR_CTRL_REG_HIGH_GEAR_DIV_SHIFT 7
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_PWR_FREQ_SCALAR_CTRL_REG_HIGH_GEAR_DIV_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: L2BIU_PWR_FREQ_SCALAR_CTRL_REG :: LOW_GEAR_DIV [06:04] */
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_PWR_FREQ_SCALAR_CTRL_REG_LOW_GEAR_DIV_MASK 0x00000070
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_PWR_FREQ_SCALAR_CTRL_REG_LOW_GEAR_DIV_SHIFT 4
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_PWR_FREQ_SCALAR_CTRL_REG_LOW_GEAR_DIV_DEFAULT 0x00000001
-
-/* HIF_CPUBIUCTRL :: L2BIU_PWR_FREQ_SCALAR_CTRL_REG :: reserved1 [03:03] */
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_PWR_FREQ_SCALAR_CTRL_REG_reserved1_MASK 0x00000008
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_PWR_FREQ_SCALAR_CTRL_REG_reserved1_SHIFT 3
-
-/* HIF_CPUBIUCTRL :: L2BIU_PWR_FREQ_SCALAR_CTRL_REG :: USE_DYN_GEAR_SEL [02:02] */
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_PWR_FREQ_SCALAR_CTRL_REG_USE_DYN_GEAR_SEL_MASK 0x00000004
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_PWR_FREQ_SCALAR_CTRL_REG_USE_DYN_GEAR_SEL_SHIFT 2
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_PWR_FREQ_SCALAR_CTRL_REG_USE_DYN_GEAR_SEL_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: L2BIU_PWR_FREQ_SCALAR_CTRL_REG :: GEAR_SELECT [01:01] */
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_PWR_FREQ_SCALAR_CTRL_REG_GEAR_SELECT_MASK 0x00000002
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_PWR_FREQ_SCALAR_CTRL_REG_GEAR_SELECT_SHIFT 1
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_PWR_FREQ_SCALAR_CTRL_REG_GEAR_SELECT_DEFAULT 0x00000001
-
-/* HIF_CPUBIUCTRL :: L2BIU_PWR_FREQ_SCALAR_CTRL_REG :: FS_BYPASS_EN [00:00] */
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_PWR_FREQ_SCALAR_CTRL_REG_FS_BYPASS_EN_MASK 0x00000001
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_PWR_FREQ_SCALAR_CTRL_REG_FS_BYPASS_EN_SHIFT 0
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_PWR_FREQ_SCALAR_CTRL_REG_FS_BYPASS_EN_DEFAULT 0x00000000
-
-/***************************************************************************
- *CPU0_BPCM_ID - CPU0 BPCM ID Register
- ***************************************************************************/
-/* HIF_CPUBIUCTRL :: CPU0_BPCM_ID :: SW_strap [31:16] */
-#define BCHP_HIF_CPUBIUCTRL_CPU0_BPCM_ID_SW_strap_MASK 0xffff0000
-#define BCHP_HIF_CPUBIUCTRL_CPU0_BPCM_ID_SW_strap_SHIFT 16
-
-/* HIF_CPUBIUCTRL :: CPU0_BPCM_ID :: HW_revision [15:08] */
-#define BCHP_HIF_CPUBIUCTRL_CPU0_BPCM_ID_HW_revision_MASK 0x0000ff00
-#define BCHP_HIF_CPUBIUCTRL_CPU0_BPCM_ID_HW_revision_SHIFT 8
-
-/* HIF_CPUBIUCTRL :: CPU0_BPCM_ID :: PMB_ADDR [07:00] */
-#define BCHP_HIF_CPUBIUCTRL_CPU0_BPCM_ID_PMB_ADDR_MASK 0x000000ff
-#define BCHP_HIF_CPUBIUCTRL_CPU0_BPCM_ID_PMB_ADDR_SHIFT 0
-
-/***************************************************************************
- *CPU0_BPCM_CAPABILITY - CPU0 BPCM Capability Register
- ***************************************************************************/
-/* HIF_CPUBIUCTRL :: CPU0_BPCM_CAPABILITY :: reserved0 [31:08] */
-#define BCHP_HIF_CPUBIUCTRL_CPU0_BPCM_CAPABILITY_reserved0_MASK 0xffffff00
-#define BCHP_HIF_CPUBIUCTRL_CPU0_BPCM_CAPABILITY_reserved0_SHIFT 8
-
-/* HIF_CPUBIUCTRL :: CPU0_BPCM_CAPABILITY :: Number_of_zones [07:00] */
-#define BCHP_HIF_CPUBIUCTRL_CPU0_BPCM_CAPABILITY_Number_of_zones_MASK 0x000000ff
-#define BCHP_HIF_CPUBIUCTRL_CPU0_BPCM_CAPABILITY_Number_of_zones_SHIFT 0
-
-/***************************************************************************
- *CPU0_BPCM_CONTROL - CPU0 BPCM Control Register
- ***************************************************************************/
-/* HIF_CPUBIUCTRL :: CPU0_BPCM_CONTROL :: TbdField [31:00] */
-#define BCHP_HIF_CPUBIUCTRL_CPU0_BPCM_CONTROL_TbdField_MASK 0xffffffff
-#define BCHP_HIF_CPUBIUCTRL_CPU0_BPCM_CONTROL_TbdField_SHIFT 0
-
-/***************************************************************************
- *CPU0_BPCM_STATUS - CPU0 BPCM Status Register
- ***************************************************************************/
-/* HIF_CPUBIUCTRL :: CPU0_BPCM_STATUS :: reserved0 [31:01] */
-#define BCHP_HIF_CPUBIUCTRL_CPU0_BPCM_STATUS_reserved0_MASK 0xfffffffe
-#define BCHP_HIF_CPUBIUCTRL_CPU0_BPCM_STATUS_reserved0_SHIFT 1
-
-/* HIF_CPUBIUCTRL :: CPU0_BPCM_STATUS :: PWD_Alert [00:00] */
-#define BCHP_HIF_CPUBIUCTRL_CPU0_BPCM_STATUS_PWD_Alert_MASK 0x00000001
-#define BCHP_HIF_CPUBIUCTRL_CPU0_BPCM_STATUS_PWD_Alert_SHIFT 0
-
-/***************************************************************************
- *CPU0_AVS_ROSC_CONTROL - CPU0 Ring Oscillator Control Register
- ***************************************************************************/
-/* HIF_CPUBIUCTRL :: CPU0_AVS_ROSC_CONTROL :: Test_interval [31:16] */
-#define BCHP_HIF_CPUBIUCTRL_CPU0_AVS_ROSC_CONTROL_Test_interval_MASK 0xffff0000
-#define BCHP_HIF_CPUBIUCTRL_CPU0_AVS_ROSC_CONTROL_Test_interval_SHIFT 16
-#define BCHP_HIF_CPUBIUCTRL_CPU0_AVS_ROSC_CONTROL_Test_interval_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: CPU0_AVS_ROSC_CONTROL :: ALERT_H [15:15] */
-#define BCHP_HIF_CPUBIUCTRL_CPU0_AVS_ROSC_CONTROL_ALERT_H_MASK 0x00008000
-#define BCHP_HIF_CPUBIUCTRL_CPU0_AVS_ROSC_CONTROL_ALERT_H_SHIFT 15
-#define BCHP_HIF_CPUBIUCTRL_CPU0_AVS_ROSC_CONTROL_ALERT_H_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: CPU0_AVS_ROSC_CONTROL :: VALID_H [14:14] */
-#define BCHP_HIF_CPUBIUCTRL_CPU0_AVS_ROSC_CONTROL_VALID_H_MASK 0x00004000
-#define BCHP_HIF_CPUBIUCTRL_CPU0_AVS_ROSC_CONTROL_VALID_H_SHIFT 14
-#define BCHP_HIF_CPUBIUCTRL_CPU0_AVS_ROSC_CONTROL_VALID_H_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: CPU0_AVS_ROSC_CONTROL :: ALERT_S [13:13] */
-#define BCHP_HIF_CPUBIUCTRL_CPU0_AVS_ROSC_CONTROL_ALERT_S_MASK 0x00002000
-#define BCHP_HIF_CPUBIUCTRL_CPU0_AVS_ROSC_CONTROL_ALERT_S_SHIFT 13
-#define BCHP_HIF_CPUBIUCTRL_CPU0_AVS_ROSC_CONTROL_ALERT_S_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: CPU0_AVS_ROSC_CONTROL :: VALID_S [12:12] */
-#define BCHP_HIF_CPUBIUCTRL_CPU0_AVS_ROSC_CONTROL_VALID_S_MASK 0x00001000
-#define BCHP_HIF_CPUBIUCTRL_CPU0_AVS_ROSC_CONTROL_VALID_S_SHIFT 12
-#define BCHP_HIF_CPUBIUCTRL_CPU0_AVS_ROSC_CONTROL_VALID_S_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: CPU0_AVS_ROSC_CONTROL :: reserved0 [11:08] */
-#define BCHP_HIF_CPUBIUCTRL_CPU0_AVS_ROSC_CONTROL_reserved0_MASK 0x00000f00
-#define BCHP_HIF_CPUBIUCTRL_CPU0_AVS_ROSC_CONTROL_reserved0_SHIFT 8
-
-/* HIF_CPUBIUCTRL :: CPU0_AVS_ROSC_CONTROL :: CONTINUOUS_H [07:07] */
-#define BCHP_HIF_CPUBIUCTRL_CPU0_AVS_ROSC_CONTROL_CONTINUOUS_H_MASK 0x00000080
-#define BCHP_HIF_CPUBIUCTRL_CPU0_AVS_ROSC_CONTROL_CONTINUOUS_H_SHIFT 7
-#define BCHP_HIF_CPUBIUCTRL_CPU0_AVS_ROSC_CONTROL_CONTINUOUS_H_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: CPU0_AVS_ROSC_CONTROL :: CONTINUOUS_S [06:06] */
-#define BCHP_HIF_CPUBIUCTRL_CPU0_AVS_ROSC_CONTROL_CONTINUOUS_S_MASK 0x00000040
-#define BCHP_HIF_CPUBIUCTRL_CPU0_AVS_ROSC_CONTROL_CONTINUOUS_S_SHIFT 6
-#define BCHP_HIF_CPUBIUCTRL_CPU0_AVS_ROSC_CONTROL_CONTINUOUS_S_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: CPU0_AVS_ROSC_CONTROL :: THRSH_EN_H [05:05] */
-#define BCHP_HIF_CPUBIUCTRL_CPU0_AVS_ROSC_CONTROL_THRSH_EN_H_MASK 0x00000020
-#define BCHP_HIF_CPUBIUCTRL_CPU0_AVS_ROSC_CONTROL_THRSH_EN_H_SHIFT 5
-#define BCHP_HIF_CPUBIUCTRL_CPU0_AVS_ROSC_CONTROL_THRSH_EN_H_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: CPU0_AVS_ROSC_CONTROL :: THRSH_EN_S [04:04] */
-#define BCHP_HIF_CPUBIUCTRL_CPU0_AVS_ROSC_CONTROL_THRSH_EN_S_MASK 0x00000010
-#define BCHP_HIF_CPUBIUCTRL_CPU0_AVS_ROSC_CONTROL_THRSH_EN_S_SHIFT 4
-#define BCHP_HIF_CPUBIUCTRL_CPU0_AVS_ROSC_CONTROL_THRSH_EN_S_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: CPU0_AVS_ROSC_CONTROL :: ECTR_EN_H [03:03] */
-#define BCHP_HIF_CPUBIUCTRL_CPU0_AVS_ROSC_CONTROL_ECTR_EN_H_MASK 0x00000008
-#define BCHP_HIF_CPUBIUCTRL_CPU0_AVS_ROSC_CONTROL_ECTR_EN_H_SHIFT 3
-#define BCHP_HIF_CPUBIUCTRL_CPU0_AVS_ROSC_CONTROL_ECTR_EN_H_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: CPU0_AVS_ROSC_CONTROL :: ECTR_EN_S [02:02] */
-#define BCHP_HIF_CPUBIUCTRL_CPU0_AVS_ROSC_CONTROL_ECTR_EN_S_MASK 0x00000004
-#define BCHP_HIF_CPUBIUCTRL_CPU0_AVS_ROSC_CONTROL_ECTR_EN_S_SHIFT 2
-#define BCHP_HIF_CPUBIUCTRL_CPU0_AVS_ROSC_CONTROL_ECTR_EN_S_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: CPU0_AVS_ROSC_CONTROL :: RO_EN_H [01:01] */
-#define BCHP_HIF_CPUBIUCTRL_CPU0_AVS_ROSC_CONTROL_RO_EN_H_MASK 0x00000002
-#define BCHP_HIF_CPUBIUCTRL_CPU0_AVS_ROSC_CONTROL_RO_EN_H_SHIFT 1
-#define BCHP_HIF_CPUBIUCTRL_CPU0_AVS_ROSC_CONTROL_RO_EN_H_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: CPU0_AVS_ROSC_CONTROL :: RO_EN_S [00:00] */
-#define BCHP_HIF_CPUBIUCTRL_CPU0_AVS_ROSC_CONTROL_RO_EN_S_MASK 0x00000001
-#define BCHP_HIF_CPUBIUCTRL_CPU0_AVS_ROSC_CONTROL_RO_EN_S_SHIFT 0
-#define BCHP_HIF_CPUBIUCTRL_CPU0_AVS_ROSC_CONTROL_RO_EN_S_DEFAULT 0x00000000
-
-/***************************************************************************
- *CPU0_AVS_ROSC_THRESHOLD - CPU0 Event Counter Threshold Register
- ***************************************************************************/
-/* HIF_CPUBIUCTRL :: CPU0_AVS_ROSC_THRESHOLD :: THRESH_HI [31:16] */
-#define BCHP_HIF_CPUBIUCTRL_CPU0_AVS_ROSC_THRESHOLD_THRESH_HI_MASK 0xffff0000
-#define BCHP_HIF_CPUBIUCTRL_CPU0_AVS_ROSC_THRESHOLD_THRESH_HI_SHIFT 16
-#define BCHP_HIF_CPUBIUCTRL_CPU0_AVS_ROSC_THRESHOLD_THRESH_HI_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: CPU0_AVS_ROSC_THRESHOLD :: THRESH_LO [15:00] */
-#define BCHP_HIF_CPUBIUCTRL_CPU0_AVS_ROSC_THRESHOLD_THRESH_LO_MASK 0x0000ffff
-#define BCHP_HIF_CPUBIUCTRL_CPU0_AVS_ROSC_THRESHOLD_THRESH_LO_SHIFT 0
-#define BCHP_HIF_CPUBIUCTRL_CPU0_AVS_ROSC_THRESHOLD_THRESH_LO_DEFAULT 0x00000000
-
-/***************************************************************************
- *CPU0_AVS_ROSC_COUNT - CPU0 Event Counter Count Register
- ***************************************************************************/
-/* HIF_CPUBIUCTRL :: CPU0_AVS_ROSC_COUNT :: COUNT_H [31:16] */
-#define BCHP_HIF_CPUBIUCTRL_CPU0_AVS_ROSC_COUNT_COUNT_H_MASK 0xffff0000
-#define BCHP_HIF_CPUBIUCTRL_CPU0_AVS_ROSC_COUNT_COUNT_H_SHIFT 16
-#define BCHP_HIF_CPUBIUCTRL_CPU0_AVS_ROSC_COUNT_COUNT_H_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: CPU0_AVS_ROSC_COUNT :: COUNT_S [15:00] */
-#define BCHP_HIF_CPUBIUCTRL_CPU0_AVS_ROSC_COUNT_COUNT_S_MASK 0x0000ffff
-#define BCHP_HIF_CPUBIUCTRL_CPU0_AVS_ROSC_COUNT_COUNT_S_SHIFT 0
-#define BCHP_HIF_CPUBIUCTRL_CPU0_AVS_ROSC_COUNT_COUNT_S_DEFAULT 0x00000000
-
-/***************************************************************************
- *CPU0_AVS_PWD_CONTROL - CPU0 PWD control Register
- ***************************************************************************/
-/* HIF_CPUBIUCTRL :: CPU0_AVS_PWD_CONTROL :: reserved0 [31:30] */
-#define BCHP_HIF_CPUBIUCTRL_CPU0_AVS_PWD_CONTROL_reserved0_MASK 0xc0000000
-#define BCHP_HIF_CPUBIUCTRL_CPU0_AVS_PWD_CONTROL_reserved0_SHIFT 30
-
-/* HIF_CPUBIUCTRL :: CPU0_AVS_PWD_CONTROL :: CLRCFG [29:27] */
-#define BCHP_HIF_CPUBIUCTRL_CPU0_AVS_PWD_CONTROL_CLRCFG_MASK 0x38000000
-#define BCHP_HIF_CPUBIUCTRL_CPU0_AVS_PWD_CONTROL_CLRCFG_SHIFT 27
-#define BCHP_HIF_CPUBIUCTRL_CPU0_AVS_PWD_CONTROL_CLRCFG_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: CPU0_AVS_PWD_CONTROL :: RSEL [26:24] */
-#define BCHP_HIF_CPUBIUCTRL_CPU0_AVS_PWD_CONTROL_RSEL_MASK 0x07000000
-#define BCHP_HIF_CPUBIUCTRL_CPU0_AVS_PWD_CONTROL_RSEL_SHIFT 24
-#define BCHP_HIF_CPUBIUCTRL_CPU0_AVS_PWD_CONTROL_RSEL_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: CPU0_AVS_PWD_CONTROL :: CGFG [23:16] */
-#define BCHP_HIF_CPUBIUCTRL_CPU0_AVS_PWD_CONTROL_CGFG_MASK 0x00ff0000
-#define BCHP_HIF_CPUBIUCTRL_CPU0_AVS_PWD_CONTROL_CGFG_SHIFT 16
-#define BCHP_HIF_CPUBIUCTRL_CPU0_AVS_PWD_CONTROL_CGFG_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: CPU0_AVS_PWD_CONTROL :: ALERT [15:15] */
-#define BCHP_HIF_CPUBIUCTRL_CPU0_AVS_PWD_CONTROL_ALERT_MASK 0x00008000
-#define BCHP_HIF_CPUBIUCTRL_CPU0_AVS_PWD_CONTROL_ALERT_SHIFT 15
-#define BCHP_HIF_CPUBIUCTRL_CPU0_AVS_PWD_CONTROL_ALERT_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: CPU0_AVS_PWD_CONTROL :: reserved1 [14:09] */
-#define BCHP_HIF_CPUBIUCTRL_CPU0_AVS_PWD_CONTROL_reserved1_MASK 0x00007e00
-#define BCHP_HIF_CPUBIUCTRL_CPU0_AVS_PWD_CONTROL_reserved1_SHIFT 9
-
-/* HIF_CPUBIUCTRL :: CPU0_AVS_PWD_CONTROL :: PWD_TM_EN [08:08] */
-#define BCHP_HIF_CPUBIUCTRL_CPU0_AVS_PWD_CONTROL_PWD_TM_EN_MASK 0x00000100
-#define BCHP_HIF_CPUBIUCTRL_CPU0_AVS_PWD_CONTROL_PWD_TM_EN_SHIFT 8
-#define BCHP_HIF_CPUBIUCTRL_CPU0_AVS_PWD_CONTROL_PWD_TM_EN_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: CPU0_AVS_PWD_CONTROL :: START [07:02] */
-#define BCHP_HIF_CPUBIUCTRL_CPU0_AVS_PWD_CONTROL_START_MASK 0x000000fc
-#define BCHP_HIF_CPUBIUCTRL_CPU0_AVS_PWD_CONTROL_START_SHIFT 2
-#define BCHP_HIF_CPUBIUCTRL_CPU0_AVS_PWD_CONTROL_START_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: CPU0_AVS_PWD_CONTROL :: PWD_ALERT_SEL [01:01] */
-#define BCHP_HIF_CPUBIUCTRL_CPU0_AVS_PWD_CONTROL_PWD_ALERT_SEL_MASK 0x00000002
-#define BCHP_HIF_CPUBIUCTRL_CPU0_AVS_PWD_CONTROL_PWD_ALERT_SEL_SHIFT 1
-#define BCHP_HIF_CPUBIUCTRL_CPU0_AVS_PWD_CONTROL_PWD_ALERT_SEL_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: CPU0_AVS_PWD_CONTROL :: PWD_EN [00:00] */
-#define BCHP_HIF_CPUBIUCTRL_CPU0_AVS_PWD_CONTROL_PWD_EN_MASK 0x00000001
-#define BCHP_HIF_CPUBIUCTRL_CPU0_AVS_PWD_CONTROL_PWD_EN_SHIFT 0
-#define BCHP_HIF_CPUBIUCTRL_CPU0_AVS_PWD_CONTROL_PWD_EN_DEFAULT 0x00000000
-
-/***************************************************************************
- *CPU1_BPCM_ID - CPU1 BPCM ID Register
- ***************************************************************************/
-/* HIF_CPUBIUCTRL :: CPU1_BPCM_ID :: SW_strap [31:16] */
-#define BCHP_HIF_CPUBIUCTRL_CPU1_BPCM_ID_SW_strap_MASK 0xffff0000
-#define BCHP_HIF_CPUBIUCTRL_CPU1_BPCM_ID_SW_strap_SHIFT 16
-
-/* HIF_CPUBIUCTRL :: CPU1_BPCM_ID :: HW_revision [15:08] */
-#define BCHP_HIF_CPUBIUCTRL_CPU1_BPCM_ID_HW_revision_MASK 0x0000ff00
-#define BCHP_HIF_CPUBIUCTRL_CPU1_BPCM_ID_HW_revision_SHIFT 8
-
-/* HIF_CPUBIUCTRL :: CPU1_BPCM_ID :: PMB_ADDR [07:00] */
-#define BCHP_HIF_CPUBIUCTRL_CPU1_BPCM_ID_PMB_ADDR_MASK 0x000000ff
-#define BCHP_HIF_CPUBIUCTRL_CPU1_BPCM_ID_PMB_ADDR_SHIFT 0
-
-/***************************************************************************
- *CPU1_BPCM_CAPABILITY - CPU1 BPCM Capability Register
- ***************************************************************************/
-/* HIF_CPUBIUCTRL :: CPU1_BPCM_CAPABILITY :: reserved0 [31:08] */
-#define BCHP_HIF_CPUBIUCTRL_CPU1_BPCM_CAPABILITY_reserved0_MASK 0xffffff00
-#define BCHP_HIF_CPUBIUCTRL_CPU1_BPCM_CAPABILITY_reserved0_SHIFT 8
-
-/* HIF_CPUBIUCTRL :: CPU1_BPCM_CAPABILITY :: Number_of_zones [07:00] */
-#define BCHP_HIF_CPUBIUCTRL_CPU1_BPCM_CAPABILITY_Number_of_zones_MASK 0x000000ff
-#define BCHP_HIF_CPUBIUCTRL_CPU1_BPCM_CAPABILITY_Number_of_zones_SHIFT 0
-
-/***************************************************************************
- *CPU1_BPCM_CONTROL - CPU1 BPCM Control Register
- ***************************************************************************/
-/* HIF_CPUBIUCTRL :: CPU1_BPCM_CONTROL :: TbdField [31:00] */
-#define BCHP_HIF_CPUBIUCTRL_CPU1_BPCM_CONTROL_TbdField_MASK 0xffffffff
-#define BCHP_HIF_CPUBIUCTRL_CPU1_BPCM_CONTROL_TbdField_SHIFT 0
-
-/***************************************************************************
- *CPU1_BPCM_STATUS - CPU1 BPCM Status Register
- ***************************************************************************/
-/* HIF_CPUBIUCTRL :: CPU1_BPCM_STATUS :: reserved0 [31:01] */
-#define BCHP_HIF_CPUBIUCTRL_CPU1_BPCM_STATUS_reserved0_MASK 0xfffffffe
-#define BCHP_HIF_CPUBIUCTRL_CPU1_BPCM_STATUS_reserved0_SHIFT 1
-
-/* HIF_CPUBIUCTRL :: CPU1_BPCM_STATUS :: PWD_Alert [00:00] */
-#define BCHP_HIF_CPUBIUCTRL_CPU1_BPCM_STATUS_PWD_Alert_MASK 0x00000001
-#define BCHP_HIF_CPUBIUCTRL_CPU1_BPCM_STATUS_PWD_Alert_SHIFT 0
-
-/***************************************************************************
- *CPU1_AVS_ROSC_CONTROL - CPU1 Ring Oscillator Control Register
- ***************************************************************************/
-/* HIF_CPUBIUCTRL :: CPU1_AVS_ROSC_CONTROL :: Test_interval [31:16] */
-#define BCHP_HIF_CPUBIUCTRL_CPU1_AVS_ROSC_CONTROL_Test_interval_MASK 0xffff0000
-#define BCHP_HIF_CPUBIUCTRL_CPU1_AVS_ROSC_CONTROL_Test_interval_SHIFT 16
-#define BCHP_HIF_CPUBIUCTRL_CPU1_AVS_ROSC_CONTROL_Test_interval_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: CPU1_AVS_ROSC_CONTROL :: ALERT_H [15:15] */
-#define BCHP_HIF_CPUBIUCTRL_CPU1_AVS_ROSC_CONTROL_ALERT_H_MASK 0x00008000
-#define BCHP_HIF_CPUBIUCTRL_CPU1_AVS_ROSC_CONTROL_ALERT_H_SHIFT 15
-#define BCHP_HIF_CPUBIUCTRL_CPU1_AVS_ROSC_CONTROL_ALERT_H_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: CPU1_AVS_ROSC_CONTROL :: VALID_H [14:14] */
-#define BCHP_HIF_CPUBIUCTRL_CPU1_AVS_ROSC_CONTROL_VALID_H_MASK 0x00004000
-#define BCHP_HIF_CPUBIUCTRL_CPU1_AVS_ROSC_CONTROL_VALID_H_SHIFT 14
-#define BCHP_HIF_CPUBIUCTRL_CPU1_AVS_ROSC_CONTROL_VALID_H_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: CPU1_AVS_ROSC_CONTROL :: ALERT_S [13:13] */
-#define BCHP_HIF_CPUBIUCTRL_CPU1_AVS_ROSC_CONTROL_ALERT_S_MASK 0x00002000
-#define BCHP_HIF_CPUBIUCTRL_CPU1_AVS_ROSC_CONTROL_ALERT_S_SHIFT 13
-#define BCHP_HIF_CPUBIUCTRL_CPU1_AVS_ROSC_CONTROL_ALERT_S_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: CPU1_AVS_ROSC_CONTROL :: VALID_S [12:12] */
-#define BCHP_HIF_CPUBIUCTRL_CPU1_AVS_ROSC_CONTROL_VALID_S_MASK 0x00001000
-#define BCHP_HIF_CPUBIUCTRL_CPU1_AVS_ROSC_CONTROL_VALID_S_SHIFT 12
-#define BCHP_HIF_CPUBIUCTRL_CPU1_AVS_ROSC_CONTROL_VALID_S_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: CPU1_AVS_ROSC_CONTROL :: reserved0 [11:08] */
-#define BCHP_HIF_CPUBIUCTRL_CPU1_AVS_ROSC_CONTROL_reserved0_MASK 0x00000f00
-#define BCHP_HIF_CPUBIUCTRL_CPU1_AVS_ROSC_CONTROL_reserved0_SHIFT 8
-
-/* HIF_CPUBIUCTRL :: CPU1_AVS_ROSC_CONTROL :: CONTINUOUS_H [07:07] */
-#define BCHP_HIF_CPUBIUCTRL_CPU1_AVS_ROSC_CONTROL_CONTINUOUS_H_MASK 0x00000080
-#define BCHP_HIF_CPUBIUCTRL_CPU1_AVS_ROSC_CONTROL_CONTINUOUS_H_SHIFT 7
-#define BCHP_HIF_CPUBIUCTRL_CPU1_AVS_ROSC_CONTROL_CONTINUOUS_H_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: CPU1_AVS_ROSC_CONTROL :: CONTINUOUS_S [06:06] */
-#define BCHP_HIF_CPUBIUCTRL_CPU1_AVS_ROSC_CONTROL_CONTINUOUS_S_MASK 0x00000040
-#define BCHP_HIF_CPUBIUCTRL_CPU1_AVS_ROSC_CONTROL_CONTINUOUS_S_SHIFT 6
-#define BCHP_HIF_CPUBIUCTRL_CPU1_AVS_ROSC_CONTROL_CONTINUOUS_S_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: CPU1_AVS_ROSC_CONTROL :: THRSH_EN_H [05:05] */
-#define BCHP_HIF_CPUBIUCTRL_CPU1_AVS_ROSC_CONTROL_THRSH_EN_H_MASK 0x00000020
-#define BCHP_HIF_CPUBIUCTRL_CPU1_AVS_ROSC_CONTROL_THRSH_EN_H_SHIFT 5
-#define BCHP_HIF_CPUBIUCTRL_CPU1_AVS_ROSC_CONTROL_THRSH_EN_H_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: CPU1_AVS_ROSC_CONTROL :: THRSH_EN_S [04:04] */
-#define BCHP_HIF_CPUBIUCTRL_CPU1_AVS_ROSC_CONTROL_THRSH_EN_S_MASK 0x00000010
-#define BCHP_HIF_CPUBIUCTRL_CPU1_AVS_ROSC_CONTROL_THRSH_EN_S_SHIFT 4
-#define BCHP_HIF_CPUBIUCTRL_CPU1_AVS_ROSC_CONTROL_THRSH_EN_S_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: CPU1_AVS_ROSC_CONTROL :: ECTR_EN_H [03:03] */
-#define BCHP_HIF_CPUBIUCTRL_CPU1_AVS_ROSC_CONTROL_ECTR_EN_H_MASK 0x00000008
-#define BCHP_HIF_CPUBIUCTRL_CPU1_AVS_ROSC_CONTROL_ECTR_EN_H_SHIFT 3
-#define BCHP_HIF_CPUBIUCTRL_CPU1_AVS_ROSC_CONTROL_ECTR_EN_H_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: CPU1_AVS_ROSC_CONTROL :: ECTR_EN_S [02:02] */
-#define BCHP_HIF_CPUBIUCTRL_CPU1_AVS_ROSC_CONTROL_ECTR_EN_S_MASK 0x00000004
-#define BCHP_HIF_CPUBIUCTRL_CPU1_AVS_ROSC_CONTROL_ECTR_EN_S_SHIFT 2
-#define BCHP_HIF_CPUBIUCTRL_CPU1_AVS_ROSC_CONTROL_ECTR_EN_S_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: CPU1_AVS_ROSC_CONTROL :: RO_EN_H [01:01] */
-#define BCHP_HIF_CPUBIUCTRL_CPU1_AVS_ROSC_CONTROL_RO_EN_H_MASK 0x00000002
-#define BCHP_HIF_CPUBIUCTRL_CPU1_AVS_ROSC_CONTROL_RO_EN_H_SHIFT 1
-#define BCHP_HIF_CPUBIUCTRL_CPU1_AVS_ROSC_CONTROL_RO_EN_H_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: CPU1_AVS_ROSC_CONTROL :: RO_EN_S [00:00] */
-#define BCHP_HIF_CPUBIUCTRL_CPU1_AVS_ROSC_CONTROL_RO_EN_S_MASK 0x00000001
-#define BCHP_HIF_CPUBIUCTRL_CPU1_AVS_ROSC_CONTROL_RO_EN_S_SHIFT 0
-#define BCHP_HIF_CPUBIUCTRL_CPU1_AVS_ROSC_CONTROL_RO_EN_S_DEFAULT 0x00000000
-
-/***************************************************************************
- *CPU1_AVS_ROSC_THRESHOLD - CPU1 Event Counter Threshold Register
- ***************************************************************************/
-/* HIF_CPUBIUCTRL :: CPU1_AVS_ROSC_THRESHOLD :: THRESH_HI [31:16] */
-#define BCHP_HIF_CPUBIUCTRL_CPU1_AVS_ROSC_THRESHOLD_THRESH_HI_MASK 0xffff0000
-#define BCHP_HIF_CPUBIUCTRL_CPU1_AVS_ROSC_THRESHOLD_THRESH_HI_SHIFT 16
-#define BCHP_HIF_CPUBIUCTRL_CPU1_AVS_ROSC_THRESHOLD_THRESH_HI_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: CPU1_AVS_ROSC_THRESHOLD :: THRESH_LO [15:00] */
-#define BCHP_HIF_CPUBIUCTRL_CPU1_AVS_ROSC_THRESHOLD_THRESH_LO_MASK 0x0000ffff
-#define BCHP_HIF_CPUBIUCTRL_CPU1_AVS_ROSC_THRESHOLD_THRESH_LO_SHIFT 0
-#define BCHP_HIF_CPUBIUCTRL_CPU1_AVS_ROSC_THRESHOLD_THRESH_LO_DEFAULT 0x00000000
-
-/***************************************************************************
- *CPU1_AVS_ROSC_COUNT - CPU1 Event Counter Count Register
- ***************************************************************************/
-/* HIF_CPUBIUCTRL :: CPU1_AVS_ROSC_COUNT :: COUNT_H [31:16] */
-#define BCHP_HIF_CPUBIUCTRL_CPU1_AVS_ROSC_COUNT_COUNT_H_MASK 0xffff0000
-#define BCHP_HIF_CPUBIUCTRL_CPU1_AVS_ROSC_COUNT_COUNT_H_SHIFT 16
-#define BCHP_HIF_CPUBIUCTRL_CPU1_AVS_ROSC_COUNT_COUNT_H_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: CPU1_AVS_ROSC_COUNT :: COUNT_S [15:00] */
-#define BCHP_HIF_CPUBIUCTRL_CPU1_AVS_ROSC_COUNT_COUNT_S_MASK 0x0000ffff
-#define BCHP_HIF_CPUBIUCTRL_CPU1_AVS_ROSC_COUNT_COUNT_S_SHIFT 0
-#define BCHP_HIF_CPUBIUCTRL_CPU1_AVS_ROSC_COUNT_COUNT_S_DEFAULT 0x00000000
-
-/***************************************************************************
- *CPU1_AVS_PWD_CONTROL - CPU1 PWD control Register
- ***************************************************************************/
-/* HIF_CPUBIUCTRL :: CPU1_AVS_PWD_CONTROL :: reserved0 [31:30] */
-#define BCHP_HIF_CPUBIUCTRL_CPU1_AVS_PWD_CONTROL_reserved0_MASK 0xc0000000
-#define BCHP_HIF_CPUBIUCTRL_CPU1_AVS_PWD_CONTROL_reserved0_SHIFT 30
-
-/* HIF_CPUBIUCTRL :: CPU1_AVS_PWD_CONTROL :: CLRCFG [29:27] */
-#define BCHP_HIF_CPUBIUCTRL_CPU1_AVS_PWD_CONTROL_CLRCFG_MASK 0x38000000
-#define BCHP_HIF_CPUBIUCTRL_CPU1_AVS_PWD_CONTROL_CLRCFG_SHIFT 27
-#define BCHP_HIF_CPUBIUCTRL_CPU1_AVS_PWD_CONTROL_CLRCFG_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: CPU1_AVS_PWD_CONTROL :: RSEL [26:24] */
-#define BCHP_HIF_CPUBIUCTRL_CPU1_AVS_PWD_CONTROL_RSEL_MASK 0x07000000
-#define BCHP_HIF_CPUBIUCTRL_CPU1_AVS_PWD_CONTROL_RSEL_SHIFT 24
-#define BCHP_HIF_CPUBIUCTRL_CPU1_AVS_PWD_CONTROL_RSEL_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: CPU1_AVS_PWD_CONTROL :: CGFG [23:16] */
-#define BCHP_HIF_CPUBIUCTRL_CPU1_AVS_PWD_CONTROL_CGFG_MASK 0x00ff0000
-#define BCHP_HIF_CPUBIUCTRL_CPU1_AVS_PWD_CONTROL_CGFG_SHIFT 16
-#define BCHP_HIF_CPUBIUCTRL_CPU1_AVS_PWD_CONTROL_CGFG_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: CPU1_AVS_PWD_CONTROL :: ALERT [15:15] */
-#define BCHP_HIF_CPUBIUCTRL_CPU1_AVS_PWD_CONTROL_ALERT_MASK 0x00008000
-#define BCHP_HIF_CPUBIUCTRL_CPU1_AVS_PWD_CONTROL_ALERT_SHIFT 15
-#define BCHP_HIF_CPUBIUCTRL_CPU1_AVS_PWD_CONTROL_ALERT_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: CPU1_AVS_PWD_CONTROL :: reserved1 [14:09] */
-#define BCHP_HIF_CPUBIUCTRL_CPU1_AVS_PWD_CONTROL_reserved1_MASK 0x00007e00
-#define BCHP_HIF_CPUBIUCTRL_CPU1_AVS_PWD_CONTROL_reserved1_SHIFT 9
-
-/* HIF_CPUBIUCTRL :: CPU1_AVS_PWD_CONTROL :: PWD_TM_EN [08:08] */
-#define BCHP_HIF_CPUBIUCTRL_CPU1_AVS_PWD_CONTROL_PWD_TM_EN_MASK 0x00000100
-#define BCHP_HIF_CPUBIUCTRL_CPU1_AVS_PWD_CONTROL_PWD_TM_EN_SHIFT 8
-#define BCHP_HIF_CPUBIUCTRL_CPU1_AVS_PWD_CONTROL_PWD_TM_EN_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: CPU1_AVS_PWD_CONTROL :: START [07:02] */
-#define BCHP_HIF_CPUBIUCTRL_CPU1_AVS_PWD_CONTROL_START_MASK 0x000000fc
-#define BCHP_HIF_CPUBIUCTRL_CPU1_AVS_PWD_CONTROL_START_SHIFT 2
-#define BCHP_HIF_CPUBIUCTRL_CPU1_AVS_PWD_CONTROL_START_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: CPU1_AVS_PWD_CONTROL :: PWD_ALERT_SEL [01:01] */
-#define BCHP_HIF_CPUBIUCTRL_CPU1_AVS_PWD_CONTROL_PWD_ALERT_SEL_MASK 0x00000002
-#define BCHP_HIF_CPUBIUCTRL_CPU1_AVS_PWD_CONTROL_PWD_ALERT_SEL_SHIFT 1
-#define BCHP_HIF_CPUBIUCTRL_CPU1_AVS_PWD_CONTROL_PWD_ALERT_SEL_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: CPU1_AVS_PWD_CONTROL :: PWD_EN [00:00] */
-#define BCHP_HIF_CPUBIUCTRL_CPU1_AVS_PWD_CONTROL_PWD_EN_MASK 0x00000001
-#define BCHP_HIF_CPUBIUCTRL_CPU1_AVS_PWD_CONTROL_PWD_EN_SHIFT 0
-#define BCHP_HIF_CPUBIUCTRL_CPU1_AVS_PWD_CONTROL_PWD_EN_DEFAULT 0x00000000
-
-/***************************************************************************
- *CPU2_BPCM_ID - CPU2 BPCM ID Register
- ***************************************************************************/
-/* HIF_CPUBIUCTRL :: CPU2_BPCM_ID :: SW_strap [31:16] */
-#define BCHP_HIF_CPUBIUCTRL_CPU2_BPCM_ID_SW_strap_MASK 0xffff0000
-#define BCHP_HIF_CPUBIUCTRL_CPU2_BPCM_ID_SW_strap_SHIFT 16
-
-/* HIF_CPUBIUCTRL :: CPU2_BPCM_ID :: HW_revision [15:08] */
-#define BCHP_HIF_CPUBIUCTRL_CPU2_BPCM_ID_HW_revision_MASK 0x0000ff00
-#define BCHP_HIF_CPUBIUCTRL_CPU2_BPCM_ID_HW_revision_SHIFT 8
-
-/* HIF_CPUBIUCTRL :: CPU2_BPCM_ID :: PMB_ADDR [07:00] */
-#define BCHP_HIF_CPUBIUCTRL_CPU2_BPCM_ID_PMB_ADDR_MASK 0x000000ff
-#define BCHP_HIF_CPUBIUCTRL_CPU2_BPCM_ID_PMB_ADDR_SHIFT 0
-
-/***************************************************************************
- *CPU2_BPCM_CAPABILITY - CPU2 BPCM Capability Register
- ***************************************************************************/
-/* HIF_CPUBIUCTRL :: CPU2_BPCM_CAPABILITY :: reserved0 [31:08] */
-#define BCHP_HIF_CPUBIUCTRL_CPU2_BPCM_CAPABILITY_reserved0_MASK 0xffffff00
-#define BCHP_HIF_CPUBIUCTRL_CPU2_BPCM_CAPABILITY_reserved0_SHIFT 8
-
-/* HIF_CPUBIUCTRL :: CPU2_BPCM_CAPABILITY :: Number_of_zones [07:00] */
-#define BCHP_HIF_CPUBIUCTRL_CPU2_BPCM_CAPABILITY_Number_of_zones_MASK 0x000000ff
-#define BCHP_HIF_CPUBIUCTRL_CPU2_BPCM_CAPABILITY_Number_of_zones_SHIFT 0
-
-/***************************************************************************
- *CPU2_BPCM_CONTROL - CPU2 BPCM Control Register
- ***************************************************************************/
-/* HIF_CPUBIUCTRL :: CPU2_BPCM_CONTROL :: TbdField [31:00] */
-#define BCHP_HIF_CPUBIUCTRL_CPU2_BPCM_CONTROL_TbdField_MASK 0xffffffff
-#define BCHP_HIF_CPUBIUCTRL_CPU2_BPCM_CONTROL_TbdField_SHIFT 0
-
-/***************************************************************************
- *CPU2_BPCM_STATUS - CPU2 BPCM Status Register
- ***************************************************************************/
-/* HIF_CPUBIUCTRL :: CPU2_BPCM_STATUS :: reserved0 [31:01] */
-#define BCHP_HIF_CPUBIUCTRL_CPU2_BPCM_STATUS_reserved0_MASK 0xfffffffe
-#define BCHP_HIF_CPUBIUCTRL_CPU2_BPCM_STATUS_reserved0_SHIFT 1
-
-/* HIF_CPUBIUCTRL :: CPU2_BPCM_STATUS :: PWD_Alert [00:00] */
-#define BCHP_HIF_CPUBIUCTRL_CPU2_BPCM_STATUS_PWD_Alert_MASK 0x00000001
-#define BCHP_HIF_CPUBIUCTRL_CPU2_BPCM_STATUS_PWD_Alert_SHIFT 0
-
-/***************************************************************************
- *CPU2_AVS_ROSC_CONTROL - CPU2 Ring Oscillator Control Register
- ***************************************************************************/
-/* HIF_CPUBIUCTRL :: CPU2_AVS_ROSC_CONTROL :: Test_interval [31:16] */
-#define BCHP_HIF_CPUBIUCTRL_CPU2_AVS_ROSC_CONTROL_Test_interval_MASK 0xffff0000
-#define BCHP_HIF_CPUBIUCTRL_CPU2_AVS_ROSC_CONTROL_Test_interval_SHIFT 16
-#define BCHP_HIF_CPUBIUCTRL_CPU2_AVS_ROSC_CONTROL_Test_interval_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: CPU2_AVS_ROSC_CONTROL :: ALERT_H [15:15] */
-#define BCHP_HIF_CPUBIUCTRL_CPU2_AVS_ROSC_CONTROL_ALERT_H_MASK 0x00008000
-#define BCHP_HIF_CPUBIUCTRL_CPU2_AVS_ROSC_CONTROL_ALERT_H_SHIFT 15
-#define BCHP_HIF_CPUBIUCTRL_CPU2_AVS_ROSC_CONTROL_ALERT_H_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: CPU2_AVS_ROSC_CONTROL :: VALID_H [14:14] */
-#define BCHP_HIF_CPUBIUCTRL_CPU2_AVS_ROSC_CONTROL_VALID_H_MASK 0x00004000
-#define BCHP_HIF_CPUBIUCTRL_CPU2_AVS_ROSC_CONTROL_VALID_H_SHIFT 14
-#define BCHP_HIF_CPUBIUCTRL_CPU2_AVS_ROSC_CONTROL_VALID_H_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: CPU2_AVS_ROSC_CONTROL :: ALERT_S [13:13] */
-#define BCHP_HIF_CPUBIUCTRL_CPU2_AVS_ROSC_CONTROL_ALERT_S_MASK 0x00002000
-#define BCHP_HIF_CPUBIUCTRL_CPU2_AVS_ROSC_CONTROL_ALERT_S_SHIFT 13
-#define BCHP_HIF_CPUBIUCTRL_CPU2_AVS_ROSC_CONTROL_ALERT_S_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: CPU2_AVS_ROSC_CONTROL :: VALID_S [12:12] */
-#define BCHP_HIF_CPUBIUCTRL_CPU2_AVS_ROSC_CONTROL_VALID_S_MASK 0x00001000
-#define BCHP_HIF_CPUBIUCTRL_CPU2_AVS_ROSC_CONTROL_VALID_S_SHIFT 12
-#define BCHP_HIF_CPUBIUCTRL_CPU2_AVS_ROSC_CONTROL_VALID_S_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: CPU2_AVS_ROSC_CONTROL :: reserved0 [11:08] */
-#define BCHP_HIF_CPUBIUCTRL_CPU2_AVS_ROSC_CONTROL_reserved0_MASK 0x00000f00
-#define BCHP_HIF_CPUBIUCTRL_CPU2_AVS_ROSC_CONTROL_reserved0_SHIFT 8
-
-/* HIF_CPUBIUCTRL :: CPU2_AVS_ROSC_CONTROL :: CONTINUOUS_H [07:07] */
-#define BCHP_HIF_CPUBIUCTRL_CPU2_AVS_ROSC_CONTROL_CONTINUOUS_H_MASK 0x00000080
-#define BCHP_HIF_CPUBIUCTRL_CPU2_AVS_ROSC_CONTROL_CONTINUOUS_H_SHIFT 7
-#define BCHP_HIF_CPUBIUCTRL_CPU2_AVS_ROSC_CONTROL_CONTINUOUS_H_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: CPU2_AVS_ROSC_CONTROL :: CONTINUOUS_S [06:06] */
-#define BCHP_HIF_CPUBIUCTRL_CPU2_AVS_ROSC_CONTROL_CONTINUOUS_S_MASK 0x00000040
-#define BCHP_HIF_CPUBIUCTRL_CPU2_AVS_ROSC_CONTROL_CONTINUOUS_S_SHIFT 6
-#define BCHP_HIF_CPUBIUCTRL_CPU2_AVS_ROSC_CONTROL_CONTINUOUS_S_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: CPU2_AVS_ROSC_CONTROL :: THRSH_EN_H [05:05] */
-#define BCHP_HIF_CPUBIUCTRL_CPU2_AVS_ROSC_CONTROL_THRSH_EN_H_MASK 0x00000020
-#define BCHP_HIF_CPUBIUCTRL_CPU2_AVS_ROSC_CONTROL_THRSH_EN_H_SHIFT 5
-#define BCHP_HIF_CPUBIUCTRL_CPU2_AVS_ROSC_CONTROL_THRSH_EN_H_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: CPU2_AVS_ROSC_CONTROL :: THRSH_EN_S [04:04] */
-#define BCHP_HIF_CPUBIUCTRL_CPU2_AVS_ROSC_CONTROL_THRSH_EN_S_MASK 0x00000010
-#define BCHP_HIF_CPUBIUCTRL_CPU2_AVS_ROSC_CONTROL_THRSH_EN_S_SHIFT 4
-#define BCHP_HIF_CPUBIUCTRL_CPU2_AVS_ROSC_CONTROL_THRSH_EN_S_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: CPU2_AVS_ROSC_CONTROL :: ECTR_EN_H [03:03] */
-#define BCHP_HIF_CPUBIUCTRL_CPU2_AVS_ROSC_CONTROL_ECTR_EN_H_MASK 0x00000008
-#define BCHP_HIF_CPUBIUCTRL_CPU2_AVS_ROSC_CONTROL_ECTR_EN_H_SHIFT 3
-#define BCHP_HIF_CPUBIUCTRL_CPU2_AVS_ROSC_CONTROL_ECTR_EN_H_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: CPU2_AVS_ROSC_CONTROL :: ECTR_EN_S [02:02] */
-#define BCHP_HIF_CPUBIUCTRL_CPU2_AVS_ROSC_CONTROL_ECTR_EN_S_MASK 0x00000004
-#define BCHP_HIF_CPUBIUCTRL_CPU2_AVS_ROSC_CONTROL_ECTR_EN_S_SHIFT 2
-#define BCHP_HIF_CPUBIUCTRL_CPU2_AVS_ROSC_CONTROL_ECTR_EN_S_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: CPU2_AVS_ROSC_CONTROL :: RO_EN_H [01:01] */
-#define BCHP_HIF_CPUBIUCTRL_CPU2_AVS_ROSC_CONTROL_RO_EN_H_MASK 0x00000002
-#define BCHP_HIF_CPUBIUCTRL_CPU2_AVS_ROSC_CONTROL_RO_EN_H_SHIFT 1
-#define BCHP_HIF_CPUBIUCTRL_CPU2_AVS_ROSC_CONTROL_RO_EN_H_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: CPU2_AVS_ROSC_CONTROL :: RO_EN_S [00:00] */
-#define BCHP_HIF_CPUBIUCTRL_CPU2_AVS_ROSC_CONTROL_RO_EN_S_MASK 0x00000001
-#define BCHP_HIF_CPUBIUCTRL_CPU2_AVS_ROSC_CONTROL_RO_EN_S_SHIFT 0
-#define BCHP_HIF_CPUBIUCTRL_CPU2_AVS_ROSC_CONTROL_RO_EN_S_DEFAULT 0x00000000
-
-/***************************************************************************
- *CPU2_AVS_ROSC_THRESHOLD - CPU2 Event Counter Threshold Register
- ***************************************************************************/
-/* HIF_CPUBIUCTRL :: CPU2_AVS_ROSC_THRESHOLD :: THRESH_HI [31:16] */
-#define BCHP_HIF_CPUBIUCTRL_CPU2_AVS_ROSC_THRESHOLD_THRESH_HI_MASK 0xffff0000
-#define BCHP_HIF_CPUBIUCTRL_CPU2_AVS_ROSC_THRESHOLD_THRESH_HI_SHIFT 16
-#define BCHP_HIF_CPUBIUCTRL_CPU2_AVS_ROSC_THRESHOLD_THRESH_HI_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: CPU2_AVS_ROSC_THRESHOLD :: THRESH_LO [15:00] */
-#define BCHP_HIF_CPUBIUCTRL_CPU2_AVS_ROSC_THRESHOLD_THRESH_LO_MASK 0x0000ffff
-#define BCHP_HIF_CPUBIUCTRL_CPU2_AVS_ROSC_THRESHOLD_THRESH_LO_SHIFT 0
-#define BCHP_HIF_CPUBIUCTRL_CPU2_AVS_ROSC_THRESHOLD_THRESH_LO_DEFAULT 0x00000000
-
-/***************************************************************************
- *CPU2_AVS_ROSC_COUNT - CPU2 Event Counter Count Register
- ***************************************************************************/
-/* HIF_CPUBIUCTRL :: CPU2_AVS_ROSC_COUNT :: COUNT_H [31:16] */
-#define BCHP_HIF_CPUBIUCTRL_CPU2_AVS_ROSC_COUNT_COUNT_H_MASK 0xffff0000
-#define BCHP_HIF_CPUBIUCTRL_CPU2_AVS_ROSC_COUNT_COUNT_H_SHIFT 16
-#define BCHP_HIF_CPUBIUCTRL_CPU2_AVS_ROSC_COUNT_COUNT_H_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: CPU2_AVS_ROSC_COUNT :: COUNT_S [15:00] */
-#define BCHP_HIF_CPUBIUCTRL_CPU2_AVS_ROSC_COUNT_COUNT_S_MASK 0x0000ffff
-#define BCHP_HIF_CPUBIUCTRL_CPU2_AVS_ROSC_COUNT_COUNT_S_SHIFT 0
-#define BCHP_HIF_CPUBIUCTRL_CPU2_AVS_ROSC_COUNT_COUNT_S_DEFAULT 0x00000000
-
-/***************************************************************************
- *CPU2_AVS_PWD_CONTROL - CPU2 PWD control Register
- ***************************************************************************/
-/* HIF_CPUBIUCTRL :: CPU2_AVS_PWD_CONTROL :: reserved0 [31:30] */
-#define BCHP_HIF_CPUBIUCTRL_CPU2_AVS_PWD_CONTROL_reserved0_MASK 0xc0000000
-#define BCHP_HIF_CPUBIUCTRL_CPU2_AVS_PWD_CONTROL_reserved0_SHIFT 30
-
-/* HIF_CPUBIUCTRL :: CPU2_AVS_PWD_CONTROL :: CLRCFG [29:27] */
-#define BCHP_HIF_CPUBIUCTRL_CPU2_AVS_PWD_CONTROL_CLRCFG_MASK 0x38000000
-#define BCHP_HIF_CPUBIUCTRL_CPU2_AVS_PWD_CONTROL_CLRCFG_SHIFT 27
-#define BCHP_HIF_CPUBIUCTRL_CPU2_AVS_PWD_CONTROL_CLRCFG_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: CPU2_AVS_PWD_CONTROL :: RSEL [26:24] */
-#define BCHP_HIF_CPUBIUCTRL_CPU2_AVS_PWD_CONTROL_RSEL_MASK 0x07000000
-#define BCHP_HIF_CPUBIUCTRL_CPU2_AVS_PWD_CONTROL_RSEL_SHIFT 24
-#define BCHP_HIF_CPUBIUCTRL_CPU2_AVS_PWD_CONTROL_RSEL_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: CPU2_AVS_PWD_CONTROL :: CGFG [23:16] */
-#define BCHP_HIF_CPUBIUCTRL_CPU2_AVS_PWD_CONTROL_CGFG_MASK 0x00ff0000
-#define BCHP_HIF_CPUBIUCTRL_CPU2_AVS_PWD_CONTROL_CGFG_SHIFT 16
-#define BCHP_HIF_CPUBIUCTRL_CPU2_AVS_PWD_CONTROL_CGFG_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: CPU2_AVS_PWD_CONTROL :: ALERT [15:15] */
-#define BCHP_HIF_CPUBIUCTRL_CPU2_AVS_PWD_CONTROL_ALERT_MASK 0x00008000
-#define BCHP_HIF_CPUBIUCTRL_CPU2_AVS_PWD_CONTROL_ALERT_SHIFT 15
-#define BCHP_HIF_CPUBIUCTRL_CPU2_AVS_PWD_CONTROL_ALERT_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: CPU2_AVS_PWD_CONTROL :: reserved1 [14:09] */
-#define BCHP_HIF_CPUBIUCTRL_CPU2_AVS_PWD_CONTROL_reserved1_MASK 0x00007e00
-#define BCHP_HIF_CPUBIUCTRL_CPU2_AVS_PWD_CONTROL_reserved1_SHIFT 9
-
-/* HIF_CPUBIUCTRL :: CPU2_AVS_PWD_CONTROL :: PWD_TM_EN [08:08] */
-#define BCHP_HIF_CPUBIUCTRL_CPU2_AVS_PWD_CONTROL_PWD_TM_EN_MASK 0x00000100
-#define BCHP_HIF_CPUBIUCTRL_CPU2_AVS_PWD_CONTROL_PWD_TM_EN_SHIFT 8
-#define BCHP_HIF_CPUBIUCTRL_CPU2_AVS_PWD_CONTROL_PWD_TM_EN_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: CPU2_AVS_PWD_CONTROL :: START [07:02] */
-#define BCHP_HIF_CPUBIUCTRL_CPU2_AVS_PWD_CONTROL_START_MASK 0x000000fc
-#define BCHP_HIF_CPUBIUCTRL_CPU2_AVS_PWD_CONTROL_START_SHIFT 2
-#define BCHP_HIF_CPUBIUCTRL_CPU2_AVS_PWD_CONTROL_START_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: CPU2_AVS_PWD_CONTROL :: PWD_ALERT_SEL [01:01] */
-#define BCHP_HIF_CPUBIUCTRL_CPU2_AVS_PWD_CONTROL_PWD_ALERT_SEL_MASK 0x00000002
-#define BCHP_HIF_CPUBIUCTRL_CPU2_AVS_PWD_CONTROL_PWD_ALERT_SEL_SHIFT 1
-#define BCHP_HIF_CPUBIUCTRL_CPU2_AVS_PWD_CONTROL_PWD_ALERT_SEL_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: CPU2_AVS_PWD_CONTROL :: PWD_EN [00:00] */
-#define BCHP_HIF_CPUBIUCTRL_CPU2_AVS_PWD_CONTROL_PWD_EN_MASK 0x00000001
-#define BCHP_HIF_CPUBIUCTRL_CPU2_AVS_PWD_CONTROL_PWD_EN_SHIFT 0
-#define BCHP_HIF_CPUBIUCTRL_CPU2_AVS_PWD_CONTROL_PWD_EN_DEFAULT 0x00000000
-
-/***************************************************************************
- *CPU3_BPCM_ID - CPU3 BPCM ID Register
- ***************************************************************************/
-/* HIF_CPUBIUCTRL :: CPU3_BPCM_ID :: SW_strap [31:16] */
-#define BCHP_HIF_CPUBIUCTRL_CPU3_BPCM_ID_SW_strap_MASK 0xffff0000
-#define BCHP_HIF_CPUBIUCTRL_CPU3_BPCM_ID_SW_strap_SHIFT 16
-
-/* HIF_CPUBIUCTRL :: CPU3_BPCM_ID :: HW_revision [15:08] */
-#define BCHP_HIF_CPUBIUCTRL_CPU3_BPCM_ID_HW_revision_MASK 0x0000ff00
-#define BCHP_HIF_CPUBIUCTRL_CPU3_BPCM_ID_HW_revision_SHIFT 8
-
-/* HIF_CPUBIUCTRL :: CPU3_BPCM_ID :: PMB_ADDR [07:00] */
-#define BCHP_HIF_CPUBIUCTRL_CPU3_BPCM_ID_PMB_ADDR_MASK 0x000000ff
-#define BCHP_HIF_CPUBIUCTRL_CPU3_BPCM_ID_PMB_ADDR_SHIFT 0
-
-/***************************************************************************
- *CPU3_BPCM_CAPABILITY - CPU3 BPCM Capability Register
- ***************************************************************************/
-/* HIF_CPUBIUCTRL :: CPU3_BPCM_CAPABILITY :: reserved0 [31:08] */
-#define BCHP_HIF_CPUBIUCTRL_CPU3_BPCM_CAPABILITY_reserved0_MASK 0xffffff00
-#define BCHP_HIF_CPUBIUCTRL_CPU3_BPCM_CAPABILITY_reserved0_SHIFT 8
-
-/* HIF_CPUBIUCTRL :: CPU3_BPCM_CAPABILITY :: Number_of_zones [07:00] */
-#define BCHP_HIF_CPUBIUCTRL_CPU3_BPCM_CAPABILITY_Number_of_zones_MASK 0x000000ff
-#define BCHP_HIF_CPUBIUCTRL_CPU3_BPCM_CAPABILITY_Number_of_zones_SHIFT 0
-
-/***************************************************************************
- *CPU3_BPCM_CONTROL - CPU3 BPCM Control Register
- ***************************************************************************/
-/* HIF_CPUBIUCTRL :: CPU3_BPCM_CONTROL :: TbdField [31:00] */
-#define BCHP_HIF_CPUBIUCTRL_CPU3_BPCM_CONTROL_TbdField_MASK 0xffffffff
-#define BCHP_HIF_CPUBIUCTRL_CPU3_BPCM_CONTROL_TbdField_SHIFT 0
-
-/***************************************************************************
- *CPU3_BPCM_STATUS - CPU3 BPCM Status Register
- ***************************************************************************/
-/* HIF_CPUBIUCTRL :: CPU3_BPCM_STATUS :: reserved0 [31:01] */
-#define BCHP_HIF_CPUBIUCTRL_CPU3_BPCM_STATUS_reserved0_MASK 0xfffffffe
-#define BCHP_HIF_CPUBIUCTRL_CPU3_BPCM_STATUS_reserved0_SHIFT 1
-
-/* HIF_CPUBIUCTRL :: CPU3_BPCM_STATUS :: PWD_Alert [00:00] */
-#define BCHP_HIF_CPUBIUCTRL_CPU3_BPCM_STATUS_PWD_Alert_MASK 0x00000001
-#define BCHP_HIF_CPUBIUCTRL_CPU3_BPCM_STATUS_PWD_Alert_SHIFT 0
-
-/***************************************************************************
- *CPU3_AVS_ROSC_CONTROL - CPU3 Ring Oscillator Control Register
- ***************************************************************************/
-/* HIF_CPUBIUCTRL :: CPU3_AVS_ROSC_CONTROL :: Test_interval [31:16] */
-#define BCHP_HIF_CPUBIUCTRL_CPU3_AVS_ROSC_CONTROL_Test_interval_MASK 0xffff0000
-#define BCHP_HIF_CPUBIUCTRL_CPU3_AVS_ROSC_CONTROL_Test_interval_SHIFT 16
-#define BCHP_HIF_CPUBIUCTRL_CPU3_AVS_ROSC_CONTROL_Test_interval_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: CPU3_AVS_ROSC_CONTROL :: ALERT_H [15:15] */
-#define BCHP_HIF_CPUBIUCTRL_CPU3_AVS_ROSC_CONTROL_ALERT_H_MASK 0x00008000
-#define BCHP_HIF_CPUBIUCTRL_CPU3_AVS_ROSC_CONTROL_ALERT_H_SHIFT 15
-#define BCHP_HIF_CPUBIUCTRL_CPU3_AVS_ROSC_CONTROL_ALERT_H_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: CPU3_AVS_ROSC_CONTROL :: VALID_H [14:14] */
-#define BCHP_HIF_CPUBIUCTRL_CPU3_AVS_ROSC_CONTROL_VALID_H_MASK 0x00004000
-#define BCHP_HIF_CPUBIUCTRL_CPU3_AVS_ROSC_CONTROL_VALID_H_SHIFT 14
-#define BCHP_HIF_CPUBIUCTRL_CPU3_AVS_ROSC_CONTROL_VALID_H_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: CPU3_AVS_ROSC_CONTROL :: ALERT_S [13:13] */
-#define BCHP_HIF_CPUBIUCTRL_CPU3_AVS_ROSC_CONTROL_ALERT_S_MASK 0x00002000
-#define BCHP_HIF_CPUBIUCTRL_CPU3_AVS_ROSC_CONTROL_ALERT_S_SHIFT 13
-#define BCHP_HIF_CPUBIUCTRL_CPU3_AVS_ROSC_CONTROL_ALERT_S_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: CPU3_AVS_ROSC_CONTROL :: VALID_S [12:12] */
-#define BCHP_HIF_CPUBIUCTRL_CPU3_AVS_ROSC_CONTROL_VALID_S_MASK 0x00001000
-#define BCHP_HIF_CPUBIUCTRL_CPU3_AVS_ROSC_CONTROL_VALID_S_SHIFT 12
-#define BCHP_HIF_CPUBIUCTRL_CPU3_AVS_ROSC_CONTROL_VALID_S_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: CPU3_AVS_ROSC_CONTROL :: reserved0 [11:08] */
-#define BCHP_HIF_CPUBIUCTRL_CPU3_AVS_ROSC_CONTROL_reserved0_MASK 0x00000f00
-#define BCHP_HIF_CPUBIUCTRL_CPU3_AVS_ROSC_CONTROL_reserved0_SHIFT 8
-
-/* HIF_CPUBIUCTRL :: CPU3_AVS_ROSC_CONTROL :: CONTINUOUS_H [07:07] */
-#define BCHP_HIF_CPUBIUCTRL_CPU3_AVS_ROSC_CONTROL_CONTINUOUS_H_MASK 0x00000080
-#define BCHP_HIF_CPUBIUCTRL_CPU3_AVS_ROSC_CONTROL_CONTINUOUS_H_SHIFT 7
-#define BCHP_HIF_CPUBIUCTRL_CPU3_AVS_ROSC_CONTROL_CONTINUOUS_H_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: CPU3_AVS_ROSC_CONTROL :: CONTINUOUS_S [06:06] */
-#define BCHP_HIF_CPUBIUCTRL_CPU3_AVS_ROSC_CONTROL_CONTINUOUS_S_MASK 0x00000040
-#define BCHP_HIF_CPUBIUCTRL_CPU3_AVS_ROSC_CONTROL_CONTINUOUS_S_SHIFT 6
-#define BCHP_HIF_CPUBIUCTRL_CPU3_AVS_ROSC_CONTROL_CONTINUOUS_S_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: CPU3_AVS_ROSC_CONTROL :: THRSH_EN_H [05:05] */
-#define BCHP_HIF_CPUBIUCTRL_CPU3_AVS_ROSC_CONTROL_THRSH_EN_H_MASK 0x00000020
-#define BCHP_HIF_CPUBIUCTRL_CPU3_AVS_ROSC_CONTROL_THRSH_EN_H_SHIFT 5
-#define BCHP_HIF_CPUBIUCTRL_CPU3_AVS_ROSC_CONTROL_THRSH_EN_H_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: CPU3_AVS_ROSC_CONTROL :: THRSH_EN_S [04:04] */
-#define BCHP_HIF_CPUBIUCTRL_CPU3_AVS_ROSC_CONTROL_THRSH_EN_S_MASK 0x00000010
-#define BCHP_HIF_CPUBIUCTRL_CPU3_AVS_ROSC_CONTROL_THRSH_EN_S_SHIFT 4
-#define BCHP_HIF_CPUBIUCTRL_CPU3_AVS_ROSC_CONTROL_THRSH_EN_S_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: CPU3_AVS_ROSC_CONTROL :: ECTR_EN_H [03:03] */
-#define BCHP_HIF_CPUBIUCTRL_CPU3_AVS_ROSC_CONTROL_ECTR_EN_H_MASK 0x00000008
-#define BCHP_HIF_CPUBIUCTRL_CPU3_AVS_ROSC_CONTROL_ECTR_EN_H_SHIFT 3
-#define BCHP_HIF_CPUBIUCTRL_CPU3_AVS_ROSC_CONTROL_ECTR_EN_H_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: CPU3_AVS_ROSC_CONTROL :: ECTR_EN_S [02:02] */
-#define BCHP_HIF_CPUBIUCTRL_CPU3_AVS_ROSC_CONTROL_ECTR_EN_S_MASK 0x00000004
-#define BCHP_HIF_CPUBIUCTRL_CPU3_AVS_ROSC_CONTROL_ECTR_EN_S_SHIFT 2
-#define BCHP_HIF_CPUBIUCTRL_CPU3_AVS_ROSC_CONTROL_ECTR_EN_S_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: CPU3_AVS_ROSC_CONTROL :: RO_EN_H [01:01] */
-#define BCHP_HIF_CPUBIUCTRL_CPU3_AVS_ROSC_CONTROL_RO_EN_H_MASK 0x00000002
-#define BCHP_HIF_CPUBIUCTRL_CPU3_AVS_ROSC_CONTROL_RO_EN_H_SHIFT 1
-#define BCHP_HIF_CPUBIUCTRL_CPU3_AVS_ROSC_CONTROL_RO_EN_H_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: CPU3_AVS_ROSC_CONTROL :: RO_EN_S [00:00] */
-#define BCHP_HIF_CPUBIUCTRL_CPU3_AVS_ROSC_CONTROL_RO_EN_S_MASK 0x00000001
-#define BCHP_HIF_CPUBIUCTRL_CPU3_AVS_ROSC_CONTROL_RO_EN_S_SHIFT 0
-#define BCHP_HIF_CPUBIUCTRL_CPU3_AVS_ROSC_CONTROL_RO_EN_S_DEFAULT 0x00000000
-
-/***************************************************************************
- *CPU3_AVS_ROSC_THRESHOLD - CPU3 Event Counter Threshold Register
- ***************************************************************************/
-/* HIF_CPUBIUCTRL :: CPU3_AVS_ROSC_THRESHOLD :: THRESH_HI [31:16] */
-#define BCHP_HIF_CPUBIUCTRL_CPU3_AVS_ROSC_THRESHOLD_THRESH_HI_MASK 0xffff0000
-#define BCHP_HIF_CPUBIUCTRL_CPU3_AVS_ROSC_THRESHOLD_THRESH_HI_SHIFT 16
-#define BCHP_HIF_CPUBIUCTRL_CPU3_AVS_ROSC_THRESHOLD_THRESH_HI_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: CPU3_AVS_ROSC_THRESHOLD :: THRESH_LO [15:00] */
-#define BCHP_HIF_CPUBIUCTRL_CPU3_AVS_ROSC_THRESHOLD_THRESH_LO_MASK 0x0000ffff
-#define BCHP_HIF_CPUBIUCTRL_CPU3_AVS_ROSC_THRESHOLD_THRESH_LO_SHIFT 0
-#define BCHP_HIF_CPUBIUCTRL_CPU3_AVS_ROSC_THRESHOLD_THRESH_LO_DEFAULT 0x00000000
-
-/***************************************************************************
- *CPU3_AVS_ROSC_COUNT - CPU3 Event Counter Count Register
- ***************************************************************************/
-/* HIF_CPUBIUCTRL :: CPU3_AVS_ROSC_COUNT :: COUNT_H [31:16] */
-#define BCHP_HIF_CPUBIUCTRL_CPU3_AVS_ROSC_COUNT_COUNT_H_MASK 0xffff0000
-#define BCHP_HIF_CPUBIUCTRL_CPU3_AVS_ROSC_COUNT_COUNT_H_SHIFT 16
-#define BCHP_HIF_CPUBIUCTRL_CPU3_AVS_ROSC_COUNT_COUNT_H_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: CPU3_AVS_ROSC_COUNT :: COUNT_S [15:00] */
-#define BCHP_HIF_CPUBIUCTRL_CPU3_AVS_ROSC_COUNT_COUNT_S_MASK 0x0000ffff
-#define BCHP_HIF_CPUBIUCTRL_CPU3_AVS_ROSC_COUNT_COUNT_S_SHIFT 0
-#define BCHP_HIF_CPUBIUCTRL_CPU3_AVS_ROSC_COUNT_COUNT_S_DEFAULT 0x00000000
-
-/***************************************************************************
- *CPU3_AVS_PWD_CONTROL - CPU3 PWD control Register
- ***************************************************************************/
-/* HIF_CPUBIUCTRL :: CPU3_AVS_PWD_CONTROL :: reserved0 [31:30] */
-#define BCHP_HIF_CPUBIUCTRL_CPU3_AVS_PWD_CONTROL_reserved0_MASK 0xc0000000
-#define BCHP_HIF_CPUBIUCTRL_CPU3_AVS_PWD_CONTROL_reserved0_SHIFT 30
-
-/* HIF_CPUBIUCTRL :: CPU3_AVS_PWD_CONTROL :: CLRCFG [29:27] */
-#define BCHP_HIF_CPUBIUCTRL_CPU3_AVS_PWD_CONTROL_CLRCFG_MASK 0x38000000
-#define BCHP_HIF_CPUBIUCTRL_CPU3_AVS_PWD_CONTROL_CLRCFG_SHIFT 27
-#define BCHP_HIF_CPUBIUCTRL_CPU3_AVS_PWD_CONTROL_CLRCFG_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: CPU3_AVS_PWD_CONTROL :: RSEL [26:24] */
-#define BCHP_HIF_CPUBIUCTRL_CPU3_AVS_PWD_CONTROL_RSEL_MASK 0x07000000
-#define BCHP_HIF_CPUBIUCTRL_CPU3_AVS_PWD_CONTROL_RSEL_SHIFT 24
-#define BCHP_HIF_CPUBIUCTRL_CPU3_AVS_PWD_CONTROL_RSEL_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: CPU3_AVS_PWD_CONTROL :: CGFG [23:16] */
-#define BCHP_HIF_CPUBIUCTRL_CPU3_AVS_PWD_CONTROL_CGFG_MASK 0x00ff0000
-#define BCHP_HIF_CPUBIUCTRL_CPU3_AVS_PWD_CONTROL_CGFG_SHIFT 16
-#define BCHP_HIF_CPUBIUCTRL_CPU3_AVS_PWD_CONTROL_CGFG_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: CPU3_AVS_PWD_CONTROL :: ALERT [15:15] */
-#define BCHP_HIF_CPUBIUCTRL_CPU3_AVS_PWD_CONTROL_ALERT_MASK 0x00008000
-#define BCHP_HIF_CPUBIUCTRL_CPU3_AVS_PWD_CONTROL_ALERT_SHIFT 15
-#define BCHP_HIF_CPUBIUCTRL_CPU3_AVS_PWD_CONTROL_ALERT_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: CPU3_AVS_PWD_CONTROL :: reserved1 [14:09] */
-#define BCHP_HIF_CPUBIUCTRL_CPU3_AVS_PWD_CONTROL_reserved1_MASK 0x00007e00
-#define BCHP_HIF_CPUBIUCTRL_CPU3_AVS_PWD_CONTROL_reserved1_SHIFT 9
-
-/* HIF_CPUBIUCTRL :: CPU3_AVS_PWD_CONTROL :: PWD_TM_EN [08:08] */
-#define BCHP_HIF_CPUBIUCTRL_CPU3_AVS_PWD_CONTROL_PWD_TM_EN_MASK 0x00000100
-#define BCHP_HIF_CPUBIUCTRL_CPU3_AVS_PWD_CONTROL_PWD_TM_EN_SHIFT 8
-#define BCHP_HIF_CPUBIUCTRL_CPU3_AVS_PWD_CONTROL_PWD_TM_EN_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: CPU3_AVS_PWD_CONTROL :: START [07:02] */
-#define BCHP_HIF_CPUBIUCTRL_CPU3_AVS_PWD_CONTROL_START_MASK 0x000000fc
-#define BCHP_HIF_CPUBIUCTRL_CPU3_AVS_PWD_CONTROL_START_SHIFT 2
-#define BCHP_HIF_CPUBIUCTRL_CPU3_AVS_PWD_CONTROL_START_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: CPU3_AVS_PWD_CONTROL :: PWD_ALERT_SEL [01:01] */
-#define BCHP_HIF_CPUBIUCTRL_CPU3_AVS_PWD_CONTROL_PWD_ALERT_SEL_MASK 0x00000002
-#define BCHP_HIF_CPUBIUCTRL_CPU3_AVS_PWD_CONTROL_PWD_ALERT_SEL_SHIFT 1
-#define BCHP_HIF_CPUBIUCTRL_CPU3_AVS_PWD_CONTROL_PWD_ALERT_SEL_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: CPU3_AVS_PWD_CONTROL :: PWD_EN [00:00] */
-#define BCHP_HIF_CPUBIUCTRL_CPU3_AVS_PWD_CONTROL_PWD_EN_MASK 0x00000001
-#define BCHP_HIF_CPUBIUCTRL_CPU3_AVS_PWD_CONTROL_PWD_EN_SHIFT 0
-#define BCHP_HIF_CPUBIUCTRL_CPU3_AVS_PWD_CONTROL_PWD_EN_DEFAULT 0x00000000
-
-/***************************************************************************
- *L2BIU_BPCM_ID - L2BIU BPCM ID Register
- ***************************************************************************/
-/* HIF_CPUBIUCTRL :: L2BIU_BPCM_ID :: SW_strap [31:16] */
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_BPCM_ID_SW_strap_MASK 0xffff0000
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_BPCM_ID_SW_strap_SHIFT 16
-
-/* HIF_CPUBIUCTRL :: L2BIU_BPCM_ID :: HW_revision [15:08] */
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_BPCM_ID_HW_revision_MASK 0x0000ff00
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_BPCM_ID_HW_revision_SHIFT 8
-
-/* HIF_CPUBIUCTRL :: L2BIU_BPCM_ID :: PMB_ADDR [07:00] */
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_BPCM_ID_PMB_ADDR_MASK 0x000000ff
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_BPCM_ID_PMB_ADDR_SHIFT 0
-
-/***************************************************************************
- *L2BIU_BPCM_CAPABILITY - L2BIU BPCM Capability Register
- ***************************************************************************/
-/* HIF_CPUBIUCTRL :: L2BIU_BPCM_CAPABILITY :: reserved0 [31:08] */
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_BPCM_CAPABILITY_reserved0_MASK 0xffffff00
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_BPCM_CAPABILITY_reserved0_SHIFT 8
-
-/* HIF_CPUBIUCTRL :: L2BIU_BPCM_CAPABILITY :: Number_of_zones [07:00] */
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_BPCM_CAPABILITY_Number_of_zones_MASK 0x000000ff
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_BPCM_CAPABILITY_Number_of_zones_SHIFT 0
-
-/***************************************************************************
- *L2BIU_BPCM_CONTROL - L2BIU BPCM Control Register
- ***************************************************************************/
-/* HIF_CPUBIUCTRL :: L2BIU_BPCM_CONTROL :: TbdField [31:00] */
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_BPCM_CONTROL_TbdField_MASK 0xffffffff
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_BPCM_CONTROL_TbdField_SHIFT 0
-
-/***************************************************************************
- *L2BIU_BPCM_STATUS - L2BIU BPCM Status Register
- ***************************************************************************/
-/* HIF_CPUBIUCTRL :: L2BIU_BPCM_STATUS :: reserved0 [31:01] */
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_BPCM_STATUS_reserved0_MASK 0xfffffffe
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_BPCM_STATUS_reserved0_SHIFT 1
-
-/* HIF_CPUBIUCTRL :: L2BIU_BPCM_STATUS :: PWD_Alert [00:00] */
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_BPCM_STATUS_PWD_Alert_MASK 0x00000001
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_BPCM_STATUS_PWD_Alert_SHIFT 0
-
-/***************************************************************************
- *L2BIU_AVS_ROSC_CONTROL - L2BIU Ring Oscillator Control Register
- ***************************************************************************/
-/* HIF_CPUBIUCTRL :: L2BIU_AVS_ROSC_CONTROL :: Test_interval [31:16] */
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_AVS_ROSC_CONTROL_Test_interval_MASK 0xffff0000
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_AVS_ROSC_CONTROL_Test_interval_SHIFT 16
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_AVS_ROSC_CONTROL_Test_interval_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: L2BIU_AVS_ROSC_CONTROL :: ALERT_H [15:15] */
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_AVS_ROSC_CONTROL_ALERT_H_MASK 0x00008000
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_AVS_ROSC_CONTROL_ALERT_H_SHIFT 15
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_AVS_ROSC_CONTROL_ALERT_H_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: L2BIU_AVS_ROSC_CONTROL :: VALID_H [14:14] */
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_AVS_ROSC_CONTROL_VALID_H_MASK 0x00004000
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_AVS_ROSC_CONTROL_VALID_H_SHIFT 14
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_AVS_ROSC_CONTROL_VALID_H_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: L2BIU_AVS_ROSC_CONTROL :: ALERT_S [13:13] */
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_AVS_ROSC_CONTROL_ALERT_S_MASK 0x00002000
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_AVS_ROSC_CONTROL_ALERT_S_SHIFT 13
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_AVS_ROSC_CONTROL_ALERT_S_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: L2BIU_AVS_ROSC_CONTROL :: VALID_S [12:12] */
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_AVS_ROSC_CONTROL_VALID_S_MASK 0x00001000
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_AVS_ROSC_CONTROL_VALID_S_SHIFT 12
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_AVS_ROSC_CONTROL_VALID_S_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: L2BIU_AVS_ROSC_CONTROL :: reserved0 [11:08] */
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_AVS_ROSC_CONTROL_reserved0_MASK 0x00000f00
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_AVS_ROSC_CONTROL_reserved0_SHIFT 8
-
-/* HIF_CPUBIUCTRL :: L2BIU_AVS_ROSC_CONTROL :: CONTINUOUS_H [07:07] */
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_AVS_ROSC_CONTROL_CONTINUOUS_H_MASK 0x00000080
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_AVS_ROSC_CONTROL_CONTINUOUS_H_SHIFT 7
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_AVS_ROSC_CONTROL_CONTINUOUS_H_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: L2BIU_AVS_ROSC_CONTROL :: CONTINUOUS_S [06:06] */
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_AVS_ROSC_CONTROL_CONTINUOUS_S_MASK 0x00000040
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_AVS_ROSC_CONTROL_CONTINUOUS_S_SHIFT 6
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_AVS_ROSC_CONTROL_CONTINUOUS_S_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: L2BIU_AVS_ROSC_CONTROL :: THRSH_EN_H [05:05] */
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_AVS_ROSC_CONTROL_THRSH_EN_H_MASK 0x00000020
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_AVS_ROSC_CONTROL_THRSH_EN_H_SHIFT 5
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_AVS_ROSC_CONTROL_THRSH_EN_H_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: L2BIU_AVS_ROSC_CONTROL :: THRSH_EN_S [04:04] */
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_AVS_ROSC_CONTROL_THRSH_EN_S_MASK 0x00000010
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_AVS_ROSC_CONTROL_THRSH_EN_S_SHIFT 4
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_AVS_ROSC_CONTROL_THRSH_EN_S_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: L2BIU_AVS_ROSC_CONTROL :: ECTR_EN_H [03:03] */
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_AVS_ROSC_CONTROL_ECTR_EN_H_MASK 0x00000008
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_AVS_ROSC_CONTROL_ECTR_EN_H_SHIFT 3
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_AVS_ROSC_CONTROL_ECTR_EN_H_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: L2BIU_AVS_ROSC_CONTROL :: ECTR_EN_S [02:02] */
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_AVS_ROSC_CONTROL_ECTR_EN_S_MASK 0x00000004
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_AVS_ROSC_CONTROL_ECTR_EN_S_SHIFT 2
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_AVS_ROSC_CONTROL_ECTR_EN_S_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: L2BIU_AVS_ROSC_CONTROL :: RO_EN_H [01:01] */
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_AVS_ROSC_CONTROL_RO_EN_H_MASK 0x00000002
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_AVS_ROSC_CONTROL_RO_EN_H_SHIFT 1
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_AVS_ROSC_CONTROL_RO_EN_H_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: L2BIU_AVS_ROSC_CONTROL :: RO_EN_S [00:00] */
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_AVS_ROSC_CONTROL_RO_EN_S_MASK 0x00000001
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_AVS_ROSC_CONTROL_RO_EN_S_SHIFT 0
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_AVS_ROSC_CONTROL_RO_EN_S_DEFAULT 0x00000000
-
-/***************************************************************************
- *L2BIU_AVS_ROSC_THRESHOLD - L2BIU Event Counter Threshold Register
- ***************************************************************************/
-/* HIF_CPUBIUCTRL :: L2BIU_AVS_ROSC_THRESHOLD :: THRESH_HI [31:16] */
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_AVS_ROSC_THRESHOLD_THRESH_HI_MASK 0xffff0000
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_AVS_ROSC_THRESHOLD_THRESH_HI_SHIFT 16
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_AVS_ROSC_THRESHOLD_THRESH_HI_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: L2BIU_AVS_ROSC_THRESHOLD :: THRESH_LO [15:00] */
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_AVS_ROSC_THRESHOLD_THRESH_LO_MASK 0x0000ffff
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_AVS_ROSC_THRESHOLD_THRESH_LO_SHIFT 0
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_AVS_ROSC_THRESHOLD_THRESH_LO_DEFAULT 0x00000000
-
-/***************************************************************************
- *L2BIU_AVS_ROSC_COUNT - L2BIU Event Counter Count Register
- ***************************************************************************/
-/* HIF_CPUBIUCTRL :: L2BIU_AVS_ROSC_COUNT :: COUNT_H [31:16] */
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_AVS_ROSC_COUNT_COUNT_H_MASK 0xffff0000
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_AVS_ROSC_COUNT_COUNT_H_SHIFT 16
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_AVS_ROSC_COUNT_COUNT_H_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: L2BIU_AVS_ROSC_COUNT :: COUNT_S [15:00] */
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_AVS_ROSC_COUNT_COUNT_S_MASK 0x0000ffff
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_AVS_ROSC_COUNT_COUNT_S_SHIFT 0
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_AVS_ROSC_COUNT_COUNT_S_DEFAULT 0x00000000
-
-/***************************************************************************
- *L2BIU_AVS_PWD_CONTROL - L2BIU PWD control Register
- ***************************************************************************/
-/* HIF_CPUBIUCTRL :: L2BIU_AVS_PWD_CONTROL :: reserved0 [31:30] */
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_AVS_PWD_CONTROL_reserved0_MASK 0xc0000000
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_AVS_PWD_CONTROL_reserved0_SHIFT 30
-
-/* HIF_CPUBIUCTRL :: L2BIU_AVS_PWD_CONTROL :: CLRCFG [29:27] */
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_AVS_PWD_CONTROL_CLRCFG_MASK 0x38000000
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_AVS_PWD_CONTROL_CLRCFG_SHIFT 27
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_AVS_PWD_CONTROL_CLRCFG_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: L2BIU_AVS_PWD_CONTROL :: RSEL [26:24] */
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_AVS_PWD_CONTROL_RSEL_MASK 0x07000000
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_AVS_PWD_CONTROL_RSEL_SHIFT 24
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_AVS_PWD_CONTROL_RSEL_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: L2BIU_AVS_PWD_CONTROL :: CGFG [23:16] */
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_AVS_PWD_CONTROL_CGFG_MASK 0x00ff0000
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_AVS_PWD_CONTROL_CGFG_SHIFT 16
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_AVS_PWD_CONTROL_CGFG_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: L2BIU_AVS_PWD_CONTROL :: ALERT [15:15] */
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_AVS_PWD_CONTROL_ALERT_MASK 0x00008000
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_AVS_PWD_CONTROL_ALERT_SHIFT 15
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_AVS_PWD_CONTROL_ALERT_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: L2BIU_AVS_PWD_CONTROL :: reserved1 [14:09] */
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_AVS_PWD_CONTROL_reserved1_MASK 0x00007e00
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_AVS_PWD_CONTROL_reserved1_SHIFT 9
-
-/* HIF_CPUBIUCTRL :: L2BIU_AVS_PWD_CONTROL :: PWD_TM_EN [08:08] */
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_AVS_PWD_CONTROL_PWD_TM_EN_MASK 0x00000100
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_AVS_PWD_CONTROL_PWD_TM_EN_SHIFT 8
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_AVS_PWD_CONTROL_PWD_TM_EN_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: L2BIU_AVS_PWD_CONTROL :: START [07:02] */
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_AVS_PWD_CONTROL_START_MASK 0x000000fc
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_AVS_PWD_CONTROL_START_SHIFT 2
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_AVS_PWD_CONTROL_START_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: L2BIU_AVS_PWD_CONTROL :: PWD_ALERT_SEL [01:01] */
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_AVS_PWD_CONTROL_PWD_ALERT_SEL_MASK 0x00000002
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_AVS_PWD_CONTROL_PWD_ALERT_SEL_SHIFT 1
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_AVS_PWD_CONTROL_PWD_ALERT_SEL_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: L2BIU_AVS_PWD_CONTROL :: PWD_EN [00:00] */
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_AVS_PWD_CONTROL_PWD_EN_MASK 0x00000001
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_AVS_PWD_CONTROL_PWD_EN_SHIFT 0
-#define BCHP_HIF_CPUBIUCTRL_L2BIU_AVS_PWD_CONTROL_PWD_EN_DEFAULT 0x00000000
-
-/***************************************************************************
- *CPU_RESET_CONFIG_REG - CPU Reset Configuration Register
- ***************************************************************************/
-/* HIF_CPUBIUCTRL :: CPU_RESET_CONFIG_REG :: reserved0 [31:04] */
-#define BCHP_HIF_CPUBIUCTRL_CPU_RESET_CONFIG_REG_reserved0_MASK 0xfffffff0
-#define BCHP_HIF_CPUBIUCTRL_CPU_RESET_CONFIG_REG_reserved0_SHIFT 4
-
-/* HIF_CPUBIUCTRL :: CPU_RESET_CONFIG_REG :: CPU3_RESET [03:03] */
-#define BCHP_HIF_CPUBIUCTRL_CPU_RESET_CONFIG_REG_CPU3_RESET_MASK 0x00000008
-#define BCHP_HIF_CPUBIUCTRL_CPU_RESET_CONFIG_REG_CPU3_RESET_SHIFT 3
-#define BCHP_HIF_CPUBIUCTRL_CPU_RESET_CONFIG_REG_CPU3_RESET_DEFAULT 0x00000001
-
-/* HIF_CPUBIUCTRL :: CPU_RESET_CONFIG_REG :: CPU2_RESET [02:02] */
-#define BCHP_HIF_CPUBIUCTRL_CPU_RESET_CONFIG_REG_CPU2_RESET_MASK 0x00000004
-#define BCHP_HIF_CPUBIUCTRL_CPU_RESET_CONFIG_REG_CPU2_RESET_SHIFT 2
-#define BCHP_HIF_CPUBIUCTRL_CPU_RESET_CONFIG_REG_CPU2_RESET_DEFAULT 0x00000001
-
-/* HIF_CPUBIUCTRL :: CPU_RESET_CONFIG_REG :: CPU1_RESET [01:01] */
-#define BCHP_HIF_CPUBIUCTRL_CPU_RESET_CONFIG_REG_CPU1_RESET_MASK 0x00000002
-#define BCHP_HIF_CPUBIUCTRL_CPU_RESET_CONFIG_REG_CPU1_RESET_SHIFT 1
-#define BCHP_HIF_CPUBIUCTRL_CPU_RESET_CONFIG_REG_CPU1_RESET_DEFAULT 0x00000001
-
-/* HIF_CPUBIUCTRL :: CPU_RESET_CONFIG_REG :: CPU0_RESET [00:00] */
-#define BCHP_HIF_CPUBIUCTRL_CPU_RESET_CONFIG_REG_CPU0_RESET_MASK 0x00000001
-#define BCHP_HIF_CPUBIUCTRL_CPU_RESET_CONFIG_REG_CPU0_RESET_SHIFT 0
-#define BCHP_HIF_CPUBIUCTRL_CPU_RESET_CONFIG_REG_CPU0_RESET_DEFAULT 0x00000000
-
-/***************************************************************************
- *CPU_CLOCK_CONFIG_REG - CPU Clock Configuration Register
- ***************************************************************************/
-/* HIF_CPUBIUCTRL :: CPU_CLOCK_CONFIG_REG :: reserved0 [31:12] */
-#define BCHP_HIF_CPUBIUCTRL_CPU_CLOCK_CONFIG_REG_reserved0_MASK 0xfffff000
-#define BCHP_HIF_CPUBIUCTRL_CPU_CLOCK_CONFIG_REG_reserved0_SHIFT 12
-
-/* HIF_CPUBIUCTRL :: CPU_CLOCK_CONFIG_REG :: GIC_CLK_RATIO [11:08] */
-#define BCHP_HIF_CPUBIUCTRL_CPU_CLOCK_CONFIG_REG_GIC_CLK_RATIO_MASK 0x00000f00
-#define BCHP_HIF_CPUBIUCTRL_CPU_CLOCK_CONFIG_REG_GIC_CLK_RATIO_SHIFT 8
-#define BCHP_HIF_CPUBIUCTRL_CPU_CLOCK_CONFIG_REG_GIC_CLK_RATIO_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: CPU_CLOCK_CONFIG_REG :: reserved1 [07:06] */
-#define BCHP_HIF_CPUBIUCTRL_CPU_CLOCK_CONFIG_REG_reserved1_MASK 0x000000c0
-#define BCHP_HIF_CPUBIUCTRL_CPU_CLOCK_CONFIG_REG_reserved1_SHIFT 6
-
-/* HIF_CPUBIUCTRL :: CPU_CLOCK_CONFIG_REG :: UBUS_CLK_EN [05:05] */
-#define BCHP_HIF_CPUBIUCTRL_CPU_CLOCK_CONFIG_REG_UBUS_CLK_EN_MASK 0x00000020
-#define BCHP_HIF_CPUBIUCTRL_CPU_CLOCK_CONFIG_REG_UBUS_CLK_EN_SHIFT 5
-#define BCHP_HIF_CPUBIUCTRL_CPU_CLOCK_CONFIG_REG_UBUS_CLK_EN_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: CPU_CLOCK_CONFIG_REG :: SAFE_CLK_MODE [04:04] */
-#define BCHP_HIF_CPUBIUCTRL_CPU_CLOCK_CONFIG_REG_SAFE_CLK_MODE_MASK 0x00000010
-#define BCHP_HIF_CPUBIUCTRL_CPU_CLOCK_CONFIG_REG_SAFE_CLK_MODE_SHIFT 4
-#define BCHP_HIF_CPUBIUCTRL_CPU_CLOCK_CONFIG_REG_SAFE_CLK_MODE_DEFAULT 0x00000001
-
-/* HIF_CPUBIUCTRL :: CPU_CLOCK_CONFIG_REG :: CLK_RATIO [03:00] */
-#define BCHP_HIF_CPUBIUCTRL_CPU_CLOCK_CONFIG_REG_CLK_RATIO_MASK 0x0000000f
-#define BCHP_HIF_CPUBIUCTRL_CPU_CLOCK_CONFIG_REG_CLK_RATIO_SHIFT 0
-#define BCHP_HIF_CPUBIUCTRL_CPU_CLOCK_CONFIG_REG_CLK_RATIO_DEFAULT 0x00000001
-
-/***************************************************************************
- *CPU_MISC_CONFIG_REG - CPU Miscellaneous Configuration Register
- ***************************************************************************/
-/* HIF_CPUBIUCTRL :: CPU_MISC_CONFIG_REG :: MiscCommands [31:08] */
-#define BCHP_HIF_CPUBIUCTRL_CPU_MISC_CONFIG_REG_MiscCommands_MASK 0xffffff00
-#define BCHP_HIF_CPUBIUCTRL_CPU_MISC_CONFIG_REG_MiscCommands_SHIFT 8
-#define BCHP_HIF_CPUBIUCTRL_CPU_MISC_CONFIG_REG_MiscCommands_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: CPU_MISC_CONFIG_REG :: ENABLE_PMUIRQ [07:04] */
-#define BCHP_HIF_CPUBIUCTRL_CPU_MISC_CONFIG_REG_ENABLE_PMUIRQ_MASK 0x000000f0
-#define BCHP_HIF_CPUBIUCTRL_CPU_MISC_CONFIG_REG_ENABLE_PMUIRQ_SHIFT 4
-#define BCHP_HIF_CPUBIUCTRL_CPU_MISC_CONFIG_REG_ENABLE_PMUIRQ_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: CPU_MISC_CONFIG_REG :: VINITHI [03:00] */
-#define BCHP_HIF_CPUBIUCTRL_CPU_MISC_CONFIG_REG_VINITHI_MASK 0x0000000f
-#define BCHP_HIF_CPUBIUCTRL_CPU_MISC_CONFIG_REG_VINITHI_SHIFT 0
-#define BCHP_HIF_CPUBIUCTRL_CPU_MISC_CONFIG_REG_VINITHI_DEFAULT 0x0000000f
-
-/***************************************************************************
- *CPU_CREDIT_REG - CPU Request Credit Register
- ***************************************************************************/
-/* HIF_CPUBIUCTRL :: CPU_CREDIT_REG :: reserved0 [31:24] */
-#define BCHP_HIF_CPUBIUCTRL_CPU_CREDIT_REG_reserved0_MASK 0xff000000
-#define BCHP_HIF_CPUBIUCTRL_CPU_CREDIT_REG_reserved0_SHIFT 24
-
-/* HIF_CPUBIUCTRL :: CPU_CREDIT_REG :: MCP2_WRITE_CRED [23:20] */
-#define BCHP_HIF_CPUBIUCTRL_CPU_CREDIT_REG_MCP2_WRITE_CRED_MASK 0x00f00000
-#define BCHP_HIF_CPUBIUCTRL_CPU_CREDIT_REG_MCP2_WRITE_CRED_SHIFT 20
-#define BCHP_HIF_CPUBIUCTRL_CPU_CREDIT_REG_MCP2_WRITE_CRED_DEFAULT 0x00000004
-
-/* HIF_CPUBIUCTRL :: CPU_CREDIT_REG :: MCP2_READ_CRED [19:16] */
-#define BCHP_HIF_CPUBIUCTRL_CPU_CREDIT_REG_MCP2_READ_CRED_MASK 0x000f0000
-#define BCHP_HIF_CPUBIUCTRL_CPU_CREDIT_REG_MCP2_READ_CRED_SHIFT 16
-#define BCHP_HIF_CPUBIUCTRL_CPU_CREDIT_REG_MCP2_READ_CRED_DEFAULT 0x00000004
-
-/* HIF_CPUBIUCTRL :: CPU_CREDIT_REG :: MCP1_WRITE_CRED [15:12] */
-#define BCHP_HIF_CPUBIUCTRL_CPU_CREDIT_REG_MCP1_WRITE_CRED_MASK 0x0000f000
-#define BCHP_HIF_CPUBIUCTRL_CPU_CREDIT_REG_MCP1_WRITE_CRED_SHIFT 12
-#define BCHP_HIF_CPUBIUCTRL_CPU_CREDIT_REG_MCP1_WRITE_CRED_DEFAULT 0x00000004
-
-/* HIF_CPUBIUCTRL :: CPU_CREDIT_REG :: MCP1_READ_CRED [11:08] */
-#define BCHP_HIF_CPUBIUCTRL_CPU_CREDIT_REG_MCP1_READ_CRED_MASK 0x00000f00
-#define BCHP_HIF_CPUBIUCTRL_CPU_CREDIT_REG_MCP1_READ_CRED_SHIFT 8
-#define BCHP_HIF_CPUBIUCTRL_CPU_CREDIT_REG_MCP1_READ_CRED_DEFAULT 0x00000004
-
-/* HIF_CPUBIUCTRL :: CPU_CREDIT_REG :: MCP0_WRITE_CRED [07:04] */
-#define BCHP_HIF_CPUBIUCTRL_CPU_CREDIT_REG_MCP0_WRITE_CRED_MASK 0x000000f0
-#define BCHP_HIF_CPUBIUCTRL_CPU_CREDIT_REG_MCP0_WRITE_CRED_SHIFT 4
-#define BCHP_HIF_CPUBIUCTRL_CPU_CREDIT_REG_MCP0_WRITE_CRED_DEFAULT 0x00000004
-
-/* HIF_CPUBIUCTRL :: CPU_CREDIT_REG :: MCP0_READ_CRED [03:00] */
-#define BCHP_HIF_CPUBIUCTRL_CPU_CREDIT_REG_MCP0_READ_CRED_MASK 0x0000000f
-#define BCHP_HIF_CPUBIUCTRL_CPU_CREDIT_REG_MCP0_READ_CRED_SHIFT 0
-#define BCHP_HIF_CPUBIUCTRL_CPU_CREDIT_REG_MCP0_READ_CRED_DEFAULT 0x00000004
-
-/***************************************************************************
- *CPU_THERM_THROTTLE_TEMP_REG - CPU Thermal Throttling IRQ Config Register
- ***************************************************************************/
-/* HIF_CPUBIUCTRL :: CPU_THERM_THROTTLE_TEMP_REG :: Valid [31:31] */
-#define BCHP_HIF_CPUBIUCTRL_CPU_THERM_THROTTLE_TEMP_REG_Valid_MASK 0x80000000
-#define BCHP_HIF_CPUBIUCTRL_CPU_THERM_THROTTLE_TEMP_REG_Valid_SHIFT 31
-#define BCHP_HIF_CPUBIUCTRL_CPU_THERM_THROTTLE_TEMP_REG_Valid_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: CPU_THERM_THROTTLE_TEMP_REG :: reserved0 [30:10] */
-#define BCHP_HIF_CPUBIUCTRL_CPU_THERM_THROTTLE_TEMP_REG_reserved0_MASK 0x7ffffc00
-#define BCHP_HIF_CPUBIUCTRL_CPU_THERM_THROTTLE_TEMP_REG_reserved0_SHIFT 10
-
-/* HIF_CPUBIUCTRL :: CPU_THERM_THROTTLE_TEMP_REG :: Temp [09:00] */
-#define BCHP_HIF_CPUBIUCTRL_CPU_THERM_THROTTLE_TEMP_REG_Temp_MASK 0x000003ff
-#define BCHP_HIF_CPUBIUCTRL_CPU_THERM_THROTTLE_TEMP_REG_Temp_SHIFT 0
-#define BCHP_HIF_CPUBIUCTRL_CPU_THERM_THROTTLE_TEMP_REG_Temp_DEFAULT 0x00000000
-
-/***************************************************************************
- *CPU_THERM_THROTTLE_IRQ_CONFIG_REG - CPU Thermal Throttling IRQ Config Register
- ***************************************************************************/
-/* HIF_CPUBIUCTRL :: CPU_THERM_THROTTLE_IRQ_CONFIG_REG :: reserved0 [31:27] */
-#define BCHP_HIF_CPUBIUCTRL_CPU_THERM_THROTTLE_IRQ_CONFIG_REG_reserved0_MASK 0xf8000000
-#define BCHP_HIF_CPUBIUCTRL_CPU_THERM_THROTTLE_IRQ_CONFIG_REG_reserved0_SHIFT 27
-
-/* HIF_CPUBIUCTRL :: CPU_THERM_THROTTLE_IRQ_CONFIG_REG :: ThermCtl [26:24] */
-#define BCHP_HIF_CPUBIUCTRL_CPU_THERM_THROTTLE_IRQ_CONFIG_REG_ThermCtl_MASK 0x07000000
-#define BCHP_HIF_CPUBIUCTRL_CPU_THERM_THROTTLE_IRQ_CONFIG_REG_ThermCtl_SHIFT 24
-#define BCHP_HIF_CPUBIUCTRL_CPU_THERM_THROTTLE_IRQ_CONFIG_REG_ThermCtl_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: CPU_THERM_THROTTLE_IRQ_CONFIG_REG :: Irq_Enable_Low [23:23] */
-#define BCHP_HIF_CPUBIUCTRL_CPU_THERM_THROTTLE_IRQ_CONFIG_REG_Irq_Enable_Low_MASK 0x00800000
-#define BCHP_HIF_CPUBIUCTRL_CPU_THERM_THROTTLE_IRQ_CONFIG_REG_Irq_Enable_Low_SHIFT 23
-#define BCHP_HIF_CPUBIUCTRL_CPU_THERM_THROTTLE_IRQ_CONFIG_REG_Irq_Enable_Low_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: CPU_THERM_THROTTLE_IRQ_CONFIG_REG :: Irq_Enable_High [22:22] */
-#define BCHP_HIF_CPUBIUCTRL_CPU_THERM_THROTTLE_IRQ_CONFIG_REG_Irq_Enable_High_MASK 0x00400000
-#define BCHP_HIF_CPUBIUCTRL_CPU_THERM_THROTTLE_IRQ_CONFIG_REG_Irq_Enable_High_SHIFT 22
-#define BCHP_HIF_CPUBIUCTRL_CPU_THERM_THROTTLE_IRQ_CONFIG_REG_Irq_Enable_High_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: CPU_THERM_THROTTLE_IRQ_CONFIG_REG :: Temp_Threshold_Low [21:12] */
-#define BCHP_HIF_CPUBIUCTRL_CPU_THERM_THROTTLE_IRQ_CONFIG_REG_Temp_Threshold_Low_MASK 0x003ff000
-#define BCHP_HIF_CPUBIUCTRL_CPU_THERM_THROTTLE_IRQ_CONFIG_REG_Temp_Threshold_Low_SHIFT 12
-#define BCHP_HIF_CPUBIUCTRL_CPU_THERM_THROTTLE_IRQ_CONFIG_REG_Temp_Threshold_Low_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: CPU_THERM_THROTTLE_IRQ_CONFIG_REG :: reserved1 [11:10] */
-#define BCHP_HIF_CPUBIUCTRL_CPU_THERM_THROTTLE_IRQ_CONFIG_REG_reserved1_MASK 0x00000c00
-#define BCHP_HIF_CPUBIUCTRL_CPU_THERM_THROTTLE_IRQ_CONFIG_REG_reserved1_SHIFT 10
-
-/* HIF_CPUBIUCTRL :: CPU_THERM_THROTTLE_IRQ_CONFIG_REG :: Temp_Threshold_High [09:00] */
-#define BCHP_HIF_CPUBIUCTRL_CPU_THERM_THROTTLE_IRQ_CONFIG_REG_Temp_Threshold_High_MASK 0x000003ff
-#define BCHP_HIF_CPUBIUCTRL_CPU_THERM_THROTTLE_IRQ_CONFIG_REG_Temp_Threshold_High_SHIFT 0
-#define BCHP_HIF_CPUBIUCTRL_CPU_THERM_THROTTLE_IRQ_CONFIG_REG_Temp_Threshold_High_DEFAULT 0x00000000
-
-/***************************************************************************
- *CPU_THERM_IRQ_HIGH_REG - CPU Thermal Throttling IRQ High Register
- ***************************************************************************/
-/* HIF_CPUBIUCTRL :: CPU_THERM_IRQ_HIGH_REG :: reserved0 [31:01] */
-#define BCHP_HIF_CPUBIUCTRL_CPU_THERM_IRQ_HIGH_REG_reserved0_MASK 0xfffffffe
-#define BCHP_HIF_CPUBIUCTRL_CPU_THERM_IRQ_HIGH_REG_reserved0_SHIFT 1
-
-/* HIF_CPUBIUCTRL :: CPU_THERM_IRQ_HIGH_REG :: Therm_Irq_High [00:00] */
-#define BCHP_HIF_CPUBIUCTRL_CPU_THERM_IRQ_HIGH_REG_Therm_Irq_High_MASK 0x00000001
-#define BCHP_HIF_CPUBIUCTRL_CPU_THERM_IRQ_HIGH_REG_Therm_Irq_High_SHIFT 0
-#define BCHP_HIF_CPUBIUCTRL_CPU_THERM_IRQ_HIGH_REG_Therm_Irq_High_DEFAULT 0x00000000
-
-/***************************************************************************
- *CPU_THERM_IRQ_LOW_REG - CPU Thermal Throttling IRQ Low Register
- ***************************************************************************/
-/* HIF_CPUBIUCTRL :: CPU_THERM_IRQ_LOW_REG :: reserved0 [31:01] */
-#define BCHP_HIF_CPUBIUCTRL_CPU_THERM_IRQ_LOW_REG_reserved0_MASK 0xfffffffe
-#define BCHP_HIF_CPUBIUCTRL_CPU_THERM_IRQ_LOW_REG_reserved0_SHIFT 1
-
-/* HIF_CPUBIUCTRL :: CPU_THERM_IRQ_LOW_REG :: Therm_Irq_Low [00:00] */
-#define BCHP_HIF_CPUBIUCTRL_CPU_THERM_IRQ_LOW_REG_Therm_Irq_Low_MASK 0x00000001
-#define BCHP_HIF_CPUBIUCTRL_CPU_THERM_IRQ_LOW_REG_Therm_Irq_Low_SHIFT 0
-#define BCHP_HIF_CPUBIUCTRL_CPU_THERM_IRQ_LOW_REG_Therm_Irq_Low_DEFAULT 0x00000000
-
-/***************************************************************************
- *CPU_THERM_MISC_THRESHOLD_REG - CPU Thermal Throttling Misc Threshold Register
- ***************************************************************************/
-/* HIF_CPUBIUCTRL :: CPU_THERM_MISC_THRESHOLD_REG :: reserved0 [31:23] */
-#define BCHP_HIF_CPUBIUCTRL_CPU_THERM_MISC_THRESHOLD_REG_reserved0_MASK 0xff800000
-#define BCHP_HIF_CPUBIUCTRL_CPU_THERM_MISC_THRESHOLD_REG_reserved0_SHIFT 23
-
-/* HIF_CPUBIUCTRL :: CPU_THERM_MISC_THRESHOLD_REG :: Misc_Irq_Enable [22:22] */
-#define BCHP_HIF_CPUBIUCTRL_CPU_THERM_MISC_THRESHOLD_REG_Misc_Irq_Enable_MASK 0x00400000
-#define BCHP_HIF_CPUBIUCTRL_CPU_THERM_MISC_THRESHOLD_REG_Misc_Irq_Enable_SHIFT 22
-#define BCHP_HIF_CPUBIUCTRL_CPU_THERM_MISC_THRESHOLD_REG_Misc_Irq_Enable_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: CPU_THERM_MISC_THRESHOLD_REG :: Temp_Threshold_Low [21:12] */
-#define BCHP_HIF_CPUBIUCTRL_CPU_THERM_MISC_THRESHOLD_REG_Temp_Threshold_Low_MASK 0x003ff000
-#define BCHP_HIF_CPUBIUCTRL_CPU_THERM_MISC_THRESHOLD_REG_Temp_Threshold_Low_SHIFT 12
-#define BCHP_HIF_CPUBIUCTRL_CPU_THERM_MISC_THRESHOLD_REG_Temp_Threshold_Low_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: CPU_THERM_MISC_THRESHOLD_REG :: reserved1 [11:10] */
-#define BCHP_HIF_CPUBIUCTRL_CPU_THERM_MISC_THRESHOLD_REG_reserved1_MASK 0x00000c00
-#define BCHP_HIF_CPUBIUCTRL_CPU_THERM_MISC_THRESHOLD_REG_reserved1_SHIFT 10
-
-/* HIF_CPUBIUCTRL :: CPU_THERM_MISC_THRESHOLD_REG :: Temp_Threshold_High [09:00] */
-#define BCHP_HIF_CPUBIUCTRL_CPU_THERM_MISC_THRESHOLD_REG_Temp_Threshold_High_MASK 0x000003ff
-#define BCHP_HIF_CPUBIUCTRL_CPU_THERM_MISC_THRESHOLD_REG_Temp_Threshold_High_SHIFT 0
-#define BCHP_HIF_CPUBIUCTRL_CPU_THERM_MISC_THRESHOLD_REG_Temp_Threshold_High_DEFAULT 0x00000000
-
-/***************************************************************************
- *CPU_THERM_IRQ_MISC_REG - CPU Thermal Throttling Misc IRQ Register
- ***************************************************************************/
-/* HIF_CPUBIUCTRL :: CPU_THERM_IRQ_MISC_REG :: reserved0 [31:01] */
-#define BCHP_HIF_CPUBIUCTRL_CPU_THERM_IRQ_MISC_REG_reserved0_MASK 0xfffffffe
-#define BCHP_HIF_CPUBIUCTRL_CPU_THERM_IRQ_MISC_REG_reserved0_SHIFT 1
-
-/* HIF_CPUBIUCTRL :: CPU_THERM_IRQ_MISC_REG :: Therm_Irq_Misc [00:00] */
-#define BCHP_HIF_CPUBIUCTRL_CPU_THERM_IRQ_MISC_REG_Therm_Irq_Misc_MASK 0x00000001
-#define BCHP_HIF_CPUBIUCTRL_CPU_THERM_IRQ_MISC_REG_Therm_Irq_Misc_SHIFT 0
-
-/***************************************************************************
- *CPU_DEFEATURE_REG - CPU Defeature Register
- ***************************************************************************/
-/* HIF_CPUBIUCTRL :: CPU_DEFEATURE_REG :: TBD_field [31:08] */
-#define BCHP_HIF_CPUBIUCTRL_CPU_DEFEATURE_REG_TBD_field_MASK 0xffffff00
-#define BCHP_HIF_CPUBIUCTRL_CPU_DEFEATURE_REG_TBD_field_SHIFT 8
-#define BCHP_HIF_CPUBIUCTRL_CPU_DEFEATURE_REG_TBD_field_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: CPU_DEFEATURE_REG :: RAC_DEBUG [07:04] */
-#define BCHP_HIF_CPUBIUCTRL_CPU_DEFEATURE_REG_RAC_DEBUG_MASK 0x000000f0
-#define BCHP_HIF_CPUBIUCTRL_CPU_DEFEATURE_REG_RAC_DEBUG_SHIFT 4
-#define BCHP_HIF_CPUBIUCTRL_CPU_DEFEATURE_REG_RAC_DEBUG_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: CPU_DEFEATURE_REG :: RAC_DEFEATURE [03:00] */
-#define BCHP_HIF_CPUBIUCTRL_CPU_DEFEATURE_REG_RAC_DEFEATURE_MASK 0x0000000f
-#define BCHP_HIF_CPUBIUCTRL_CPU_DEFEATURE_REG_RAC_DEFEATURE_SHIFT 0
-#define BCHP_HIF_CPUBIUCTRL_CPU_DEFEATURE_REG_RAC_DEFEATURE_DEFAULT 0x00000000
-
-/***************************************************************************
- *CPU_DEFEATURE_KEY_REG - CPU Defeature Key Register
- ***************************************************************************/
-/* HIF_CPUBIUCTRL :: CPU_DEFEATURE_KEY_REG :: KEY [31:00] */
-#define BCHP_HIF_CPUBIUCTRL_CPU_DEFEATURE_KEY_REG_KEY_MASK 0xffffffff
-#define BCHP_HIF_CPUBIUCTRL_CPU_DEFEATURE_KEY_REG_KEY_SHIFT 0
-#define BCHP_HIF_CPUBIUCTRL_CPU_DEFEATURE_KEY_REG_KEY_DEFAULT 0x00000000
-
-/***************************************************************************
- *CPU_DEBUGROMADDR_REG - CPU Debug ROM Address Register
- ***************************************************************************/
-/* HIF_CPUBIUCTRL :: CPU_DEBUGROMADDR_REG :: DBGROMADDR [31:04] */
-#define BCHP_HIF_CPUBIUCTRL_CPU_DEBUGROMADDR_REG_DBGROMADDR_MASK 0xfffffff0
-#define BCHP_HIF_CPUBIUCTRL_CPU_DEBUGROMADDR_REG_DBGROMADDR_SHIFT 4
-#define BCHP_HIF_CPUBIUCTRL_CPU_DEBUGROMADDR_REG_DBGROMADDR_DEFAULT 0x01200000
-
-/* HIF_CPUBIUCTRL :: CPU_DEBUGROMADDR_REG :: reserved0 [03:01] */
-#define BCHP_HIF_CPUBIUCTRL_CPU_DEBUGROMADDR_REG_reserved0_MASK 0x0000000e
-#define BCHP_HIF_CPUBIUCTRL_CPU_DEBUGROMADDR_REG_reserved0_SHIFT 1
-
-/* HIF_CPUBIUCTRL :: CPU_DEBUGROMADDR_REG :: DBGROMADDRV [00:00] */
-#define BCHP_HIF_CPUBIUCTRL_CPU_DEBUGROMADDR_REG_DBGROMADDRV_MASK 0x00000001
-#define BCHP_HIF_CPUBIUCTRL_CPU_DEBUGROMADDR_REG_DBGROMADDRV_SHIFT 0
-#define BCHP_HIF_CPUBIUCTRL_CPU_DEBUGROMADDR_REG_DBGROMADDRV_DEFAULT 0x00000000
-
-/***************************************************************************
- *CPU_DEBUGSELFADDR_REG - CPU Debug SELF Address Register
- ***************************************************************************/
-/* HIF_CPUBIUCTRL :: CPU_DEBUGSELFADDR_REG :: DBGSELFADDR [31:11] */
-#define BCHP_HIF_CPUBIUCTRL_CPU_DEBUGSELFADDR_REG_DBGSELFADDR_MASK 0xfffff800
-#define BCHP_HIF_CPUBIUCTRL_CPU_DEBUGSELFADDR_REG_DBGSELFADDR_SHIFT 11
-#define BCHP_HIF_CPUBIUCTRL_CPU_DEBUGSELFADDR_REG_DBGSELFADDR_DEFAULT 0x00000001
-
-/* HIF_CPUBIUCTRL :: CPU_DEBUGSELFADDR_REG :: reserved0 [10:01] */
-#define BCHP_HIF_CPUBIUCTRL_CPU_DEBUGSELFADDR_REG_reserved0_MASK 0x000007fe
-#define BCHP_HIF_CPUBIUCTRL_CPU_DEBUGSELFADDR_REG_reserved0_SHIFT 1
-
-/* HIF_CPUBIUCTRL :: CPU_DEBUGSELFADDR_REG :: DBGSELFADDRV [00:00] */
-#define BCHP_HIF_CPUBIUCTRL_CPU_DEBUGSELFADDR_REG_DBGSELFADDRV_MASK 0x00000001
-#define BCHP_HIF_CPUBIUCTRL_CPU_DEBUGSELFADDR_REG_DBGSELFADDRV_SHIFT 0
-#define BCHP_HIF_CPUBIUCTRL_CPU_DEBUGSELFADDR_REG_DBGSELFADDRV_DEFAULT 0x00000000
-
-/***************************************************************************
- *CPU_DEBUG_TRACECTRL_REG - CPU Debug Trace Control Registeer
- ***************************************************************************/
-/* HIF_CPUBIUCTRL :: CPU_DEBUG_TRACECTRL_REG :: reserved0 [31:05] */
-#define BCHP_HIF_CPUBIUCTRL_CPU_DEBUG_TRACECTRL_REG_reserved0_MASK 0xffffffe0
-#define BCHP_HIF_CPUBIUCTRL_CPU_DEBUG_TRACECTRL_REG_reserved0_SHIFT 5
-
-/* HIF_CPUBIUCTRL :: CPU_DEBUG_TRACECTRL_REG :: TPMAXDATASIZE [04:00] */
-#define BCHP_HIF_CPUBIUCTRL_CPU_DEBUG_TRACECTRL_REG_TPMAXDATASIZE_MASK 0x0000001f
-#define BCHP_HIF_CPUBIUCTRL_CPU_DEBUG_TRACECTRL_REG_TPMAXDATASIZE_SHIFT 0
-#define BCHP_HIF_CPUBIUCTRL_CPU_DEBUG_TRACECTRL_REG_TPMAXDATASIZE_DEFAULT 0x00000003
-
-/***************************************************************************
- *CPU_AXICONFIG_REG - CPU AXI Config Register
- ***************************************************************************/
-/* HIF_CPUBIUCTRL :: CPU_AXICONFIG_REG :: reserved0 [31:04] */
-#define BCHP_HIF_CPUBIUCTRL_CPU_AXICONFIG_REG_reserved0_MASK 0xfffffff0
-#define BCHP_HIF_CPUBIUCTRL_CPU_AXICONFIG_REG_reserved0_SHIFT 4
-
-/* HIF_CPUBIUCTRL :: CPU_AXICONFIG_REG :: BROADCASTINNER [03:03] */
-#define BCHP_HIF_CPUBIUCTRL_CPU_AXICONFIG_REG_BROADCASTINNER_MASK 0x00000008
-#define BCHP_HIF_CPUBIUCTRL_CPU_AXICONFIG_REG_BROADCASTINNER_SHIFT 3
-#define BCHP_HIF_CPUBIUCTRL_CPU_AXICONFIG_REG_BROADCASTINNER_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: CPU_AXICONFIG_REG :: BROADCASTOUTER [02:02] */
-#define BCHP_HIF_CPUBIUCTRL_CPU_AXICONFIG_REG_BROADCASTOUTER_MASK 0x00000004
-#define BCHP_HIF_CPUBIUCTRL_CPU_AXICONFIG_REG_BROADCASTOUTER_SHIFT 2
-#define BCHP_HIF_CPUBIUCTRL_CPU_AXICONFIG_REG_BROADCASTOUTER_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: CPU_AXICONFIG_REG :: BROADCASTCACHEMAINT [01:01] */
-#define BCHP_HIF_CPUBIUCTRL_CPU_AXICONFIG_REG_BROADCASTCACHEMAINT_MASK 0x00000002
-#define BCHP_HIF_CPUBIUCTRL_CPU_AXICONFIG_REG_BROADCASTCACHEMAINT_SHIFT 1
-#define BCHP_HIF_CPUBIUCTRL_CPU_AXICONFIG_REG_BROADCASTCACHEMAINT_DEFAULT 0x00000001
-
-/* HIF_CPUBIUCTRL :: CPU_AXICONFIG_REG :: SYSBARDISABLE [00:00] */
-#define BCHP_HIF_CPUBIUCTRL_CPU_AXICONFIG_REG_SYSBARDISABLE_MASK 0x00000001
-#define BCHP_HIF_CPUBIUCTRL_CPU_AXICONFIG_REG_SYSBARDISABLE_SHIFT 0
-#define BCHP_HIF_CPUBIUCTRL_CPU_AXICONFIG_REG_SYSBARDISABLE_DEFAULT 0x00000000
-
-/***************************************************************************
- *CPU_REVISION_REG - CPU Revision Register
- ***************************************************************************/
-/* HIF_CPUBIUCTRL :: CPU_REVISION_REG :: reserved0 [31:08] */
-#define BCHP_HIF_CPUBIUCTRL_CPU_REVISION_REG_reserved0_MASK 0xffffff00
-#define BCHP_HIF_CPUBIUCTRL_CPU_REVISION_REG_reserved0_SHIFT 8
-
-/* HIF_CPUBIUCTRL :: CPU_REVISION_REG :: MAJOR_REV [07:04] */
-#define BCHP_HIF_CPUBIUCTRL_CPU_REVISION_REG_MAJOR_REV_MASK 0x000000f0
-#define BCHP_HIF_CPUBIUCTRL_CPU_REVISION_REG_MAJOR_REV_SHIFT 4
-#define BCHP_HIF_CPUBIUCTRL_CPU_REVISION_REG_MAJOR_REV_DEFAULT 0x00000000
-
-/* HIF_CPUBIUCTRL :: CPU_REVISION_REG :: MINOR_REV [03:00] */
-#define BCHP_HIF_CPUBIUCTRL_CPU_REVISION_REG_MINOR_REV_MASK 0x0000000f
-#define BCHP_HIF_CPUBIUCTRL_CPU_REVISION_REG_MINOR_REV_SHIFT 0
-#define BCHP_HIF_CPUBIUCTRL_CPU_REVISION_REG_MINOR_REV_DEFAULT 0x00000001
-
-/***************************************************************************
- *CPU_SCRATCH_REG - Scratch Register
- ***************************************************************************/
-/* HIF_CPUBIUCTRL :: CPU_SCRATCH_REG :: scratch [31:00] */
-#define BCHP_HIF_CPUBIUCTRL_CPU_SCRATCH_REG_scratch_MASK 0xffffffff
-#define BCHP_HIF_CPUBIUCTRL_CPU_SCRATCH_REG_scratch_SHIFT 0
-#define BCHP_HIF_CPUBIUCTRL_CPU_SCRATCH_REG_scratch_DEFAULT 0x00000000
-
-#endif /* #ifndef BCHP_HIF_CPUBIUCTRL_H__ */
-
-/* End of File */
diff --git a/include/linux/brcmstb/7439a0/bchp_hif_intr2.h b/include/linux/brcmstb/7439a0/bchp_hif_intr2.h
deleted file mode 100644
index 8ad856e..0000000
--- a/include/linux/brcmstb/7439a0/bchp_hif_intr2.h
+++ /dev/null
@@ -1,1536 +0,0 @@
-/***************************************************************************
- * Copyright (c) 1999-2012, Broadcom Corporation
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
- *
- * Module Description:
- * DO NOT EDIT THIS FILE DIRECTLY
- *
- * This module was generated magically with RDB from a source description
- * file. You must edit the source file for changes to be made to this file.
- *
- *
- * Date: Generated on Wed Oct 17 03:11:32 2012
- * MD5 Checksum d41d8cd98f00b204e9800998ecf8427e
- *
- * Compiled with: RDB Utility combo_header.pl
- * RDB Parser 3.0
- * unknown unknown
- * Perl Interpreter 5.008008
- * Operating System linux
- *
- * Revision History:
- *
- * $brcm_Log: $
- *
- ***************************************************************************/
-
-#ifndef BCHP_HIF_INTR2_H__
-#define BCHP_HIF_INTR2_H__
-
-/***************************************************************************
- *HIF_INTR2 - HIF Level 2 Interrupt Controller Registers
- ***************************************************************************/
-#define BCHP_HIF_INTR2_CPU_STATUS 0x00441000 /* CPU interrupt Status Register */
-#define BCHP_HIF_INTR2_CPU_SET 0x00441004 /* CPU interrupt Set Register */
-#define BCHP_HIF_INTR2_CPU_CLEAR 0x00441008 /* CPU interrupt Clear Register */
-#define BCHP_HIF_INTR2_CPU_MASK_STATUS 0x0044100c /* CPU interrupt Mask Status Register */
-#define BCHP_HIF_INTR2_CPU_MASK_SET 0x00441010 /* CPU interrupt Mask Set Register */
-#define BCHP_HIF_INTR2_CPU_MASK_CLEAR 0x00441014 /* CPU interrupt Mask Clear Register */
-#define BCHP_HIF_INTR2_PCI_STATUS 0x00441018 /* PCI interrupt Status Register */
-#define BCHP_HIF_INTR2_PCI_SET 0x0044101c /* PCI interrupt Set Register */
-#define BCHP_HIF_INTR2_PCI_CLEAR 0x00441020 /* PCI interrupt Clear Register */
-#define BCHP_HIF_INTR2_PCI_MASK_STATUS 0x00441024 /* PCI interrupt Mask Status Register */
-#define BCHP_HIF_INTR2_PCI_MASK_SET 0x00441028 /* PCI interrupt Mask Set Register */
-#define BCHP_HIF_INTR2_PCI_MASK_CLEAR 0x0044102c /* PCI interrupt Mask Clear Register */
-
-/***************************************************************************
- *CPU_STATUS - CPU interrupt Status Register
- ***************************************************************************/
-/* HIF_INTR2 :: CPU_STATUS :: PCIE_LINKDOWN_INTR [31:31] */
-#define BCHP_HIF_INTR2_CPU_STATUS_PCIE_LINKDOWN_INTR_MASK 0x80000000
-#define BCHP_HIF_INTR2_CPU_STATUS_PCIE_LINKDOWN_INTR_SHIFT 31
-#define BCHP_HIF_INTR2_CPU_STATUS_PCIE_LINKDOWN_INTR_DEFAULT 0x00000000
-
-/* HIF_INTR2 :: CPU_STATUS :: PCIE_LINKUP_INTR [30:30] */
-#define BCHP_HIF_INTR2_CPU_STATUS_PCIE_LINKUP_INTR_MASK 0x40000000
-#define BCHP_HIF_INTR2_CPU_STATUS_PCIE_LINKUP_INTR_SHIFT 30
-#define BCHP_HIF_INTR2_CPU_STATUS_PCIE_LINKUP_INTR_DEFAULT 0x00000000
-
-/* HIF_INTR2 :: CPU_STATUS :: reserved0 [29:28] */
-#define BCHP_HIF_INTR2_CPU_STATUS_reserved0_MASK 0x30000000
-#define BCHP_HIF_INTR2_CPU_STATUS_reserved0_SHIFT 28
-
-/* HIF_INTR2 :: CPU_STATUS :: NAND_CORR_INTR [27:27] */
-#define BCHP_HIF_INTR2_CPU_STATUS_NAND_CORR_INTR_MASK 0x08000000
-#define BCHP_HIF_INTR2_CPU_STATUS_NAND_CORR_INTR_SHIFT 27
-#define BCHP_HIF_INTR2_CPU_STATUS_NAND_CORR_INTR_DEFAULT 0x00000000
-
-/* HIF_INTR2 :: CPU_STATUS :: NAND_UNC_INTR [26:26] */
-#define BCHP_HIF_INTR2_CPU_STATUS_NAND_UNC_INTR_MASK 0x04000000
-#define BCHP_HIF_INTR2_CPU_STATUS_NAND_UNC_INTR_SHIFT 26
-#define BCHP_HIF_INTR2_CPU_STATUS_NAND_UNC_INTR_DEFAULT 0x00000000
-
-/* HIF_INTR2 :: CPU_STATUS :: NAND_RBPIN_INTR [25:25] */
-#define BCHP_HIF_INTR2_CPU_STATUS_NAND_RBPIN_INTR_MASK 0x02000000
-#define BCHP_HIF_INTR2_CPU_STATUS_NAND_RBPIN_INTR_SHIFT 25
-#define BCHP_HIF_INTR2_CPU_STATUS_NAND_RBPIN_INTR_DEFAULT 0x00000000
-
-/* HIF_INTR2 :: CPU_STATUS :: NAND_CTLRDY_INTR [24:24] */
-#define BCHP_HIF_INTR2_CPU_STATUS_NAND_CTLRDY_INTR_MASK 0x01000000
-#define BCHP_HIF_INTR2_CPU_STATUS_NAND_CTLRDY_INTR_SHIFT 24
-#define BCHP_HIF_INTR2_CPU_STATUS_NAND_CTLRDY_INTR_DEFAULT 0x00000000
-
-/* HIF_INTR2 :: CPU_STATUS :: NAND_PGMPG_INTR [23:23] */
-#define BCHP_HIF_INTR2_CPU_STATUS_NAND_PGMPG_INTR_MASK 0x00800000
-#define BCHP_HIF_INTR2_CPU_STATUS_NAND_PGMPG_INTR_SHIFT 23
-#define BCHP_HIF_INTR2_CPU_STATUS_NAND_PGMPG_INTR_DEFAULT 0x00000000
-
-/* HIF_INTR2 :: CPU_STATUS :: NAND_CPYBK_INTR [22:22] */
-#define BCHP_HIF_INTR2_CPU_STATUS_NAND_CPYBK_INTR_MASK 0x00400000
-#define BCHP_HIF_INTR2_CPU_STATUS_NAND_CPYBK_INTR_SHIFT 22
-#define BCHP_HIF_INTR2_CPU_STATUS_NAND_CPYBK_INTR_DEFAULT 0x00000000
-
-/* HIF_INTR2 :: CPU_STATUS :: NAND_BLKERA_INTR [21:21] */
-#define BCHP_HIF_INTR2_CPU_STATUS_NAND_BLKERA_INTR_MASK 0x00200000
-#define BCHP_HIF_INTR2_CPU_STATUS_NAND_BLKERA_INTR_SHIFT 21
-#define BCHP_HIF_INTR2_CPU_STATUS_NAND_BLKERA_INTR_DEFAULT 0x00000000
-
-/* HIF_INTR2 :: CPU_STATUS :: NAND_NP_READ_INTR [20:20] */
-#define BCHP_HIF_INTR2_CPU_STATUS_NAND_NP_READ_INTR_MASK 0x00100000
-#define BCHP_HIF_INTR2_CPU_STATUS_NAND_NP_READ_INTR_SHIFT 20
-#define BCHP_HIF_INTR2_CPU_STATUS_NAND_NP_READ_INTR_DEFAULT 0x00000000
-
-/* HIF_INTR2 :: CPU_STATUS :: reserved1 [19:18] */
-#define BCHP_HIF_INTR2_CPU_STATUS_reserved1_MASK 0x000c0000
-#define BCHP_HIF_INTR2_CPU_STATUS_reserved1_SHIFT 18
-
-/* HIF_INTR2 :: CPU_STATUS :: EBI_TIMEOUT_INTR [17:17] */
-#define BCHP_HIF_INTR2_CPU_STATUS_EBI_TIMEOUT_INTR_MASK 0x00020000
-#define BCHP_HIF_INTR2_CPU_STATUS_EBI_TIMEOUT_INTR_SHIFT 17
-#define BCHP_HIF_INTR2_CPU_STATUS_EBI_TIMEOUT_INTR_DEFAULT 0x00000000
-
-/* HIF_INTR2 :: CPU_STATUS :: EBI_TEA_INTR [16:16] */
-#define BCHP_HIF_INTR2_CPU_STATUS_EBI_TEA_INTR_MASK 0x00010000
-#define BCHP_HIF_INTR2_CPU_STATUS_EBI_TEA_INTR_SHIFT 16
-#define BCHP_HIF_INTR2_CPU_STATUS_EBI_TEA_INTR_DEFAULT 0x00000000
-
-/* HIF_INTR2 :: CPU_STATUS :: ITCH0_RD_INTR [15:15] */
-#define BCHP_HIF_INTR2_CPU_STATUS_ITCH0_RD_INTR_MASK 0x00008000
-#define BCHP_HIF_INTR2_CPU_STATUS_ITCH0_RD_INTR_SHIFT 15
-#define BCHP_HIF_INTR2_CPU_STATUS_ITCH0_RD_INTR_DEFAULT 0x00000000
-
-/* HIF_INTR2 :: CPU_STATUS :: reserved2 [14:14] */
-#define BCHP_HIF_INTR2_CPU_STATUS_reserved2_MASK 0x00004000
-#define BCHP_HIF_INTR2_CPU_STATUS_reserved2_SHIFT 14
-
-/* HIF_INTR2 :: CPU_STATUS :: PCIE_RG_BRIDGE_INTR [13:13] */
-#define BCHP_HIF_INTR2_CPU_STATUS_PCIE_RG_BRIDGE_INTR_MASK 0x00002000
-#define BCHP_HIF_INTR2_CPU_STATUS_PCIE_RG_BRIDGE_INTR_SHIFT 13
-#define BCHP_HIF_INTR2_CPU_STATUS_PCIE_RG_BRIDGE_INTR_DEFAULT 0x00000000
-
-/* HIF_INTR2 :: CPU_STATUS :: PCIE_RGR_BRIDGE_INTR [12:12] */
-#define BCHP_HIF_INTR2_CPU_STATUS_PCIE_RGR_BRIDGE_INTR_MASK 0x00001000
-#define BCHP_HIF_INTR2_CPU_STATUS_PCIE_RGR_BRIDGE_INTR_SHIFT 12
-#define BCHP_HIF_INTR2_CPU_STATUS_PCIE_RGR_BRIDGE_INTR_DEFAULT 0x00000000
-
-/* HIF_INTR2 :: CPU_STATUS :: reserved3 [11:06] */
-#define BCHP_HIF_INTR2_CPU_STATUS_reserved3_MASK 0x00000fc0
-#define BCHP_HIF_INTR2_CPU_STATUS_reserved3_SHIFT 6
-
-/* HIF_INTR2 :: CPU_STATUS :: FLASH_DMA_ERR_INTR [05:05] */
-#define BCHP_HIF_INTR2_CPU_STATUS_FLASH_DMA_ERR_INTR_MASK 0x00000020
-#define BCHP_HIF_INTR2_CPU_STATUS_FLASH_DMA_ERR_INTR_SHIFT 5
-#define BCHP_HIF_INTR2_CPU_STATUS_FLASH_DMA_ERR_INTR_DEFAULT 0x00000000
-
-/* HIF_INTR2 :: CPU_STATUS :: FLASH_DMA_DONE_INTR [04:04] */
-#define BCHP_HIF_INTR2_CPU_STATUS_FLASH_DMA_DONE_INTR_MASK 0x00000010
-#define BCHP_HIF_INTR2_CPU_STATUS_FLASH_DMA_DONE_INTR_SHIFT 4
-#define BCHP_HIF_INTR2_CPU_STATUS_FLASH_DMA_DONE_INTR_DEFAULT 0x00000000
-
-/* HIF_INTR2 :: CPU_STATUS :: WEBHIF_WD_TIMEOUT_INTR [03:03] */
-#define BCHP_HIF_INTR2_CPU_STATUS_WEBHIF_WD_TIMEOUT_INTR_MASK 0x00000008
-#define BCHP_HIF_INTR2_CPU_STATUS_WEBHIF_WD_TIMEOUT_INTR_SHIFT 3
-#define BCHP_HIF_INTR2_CPU_STATUS_WEBHIF_WD_TIMEOUT_INTR_DEFAULT 0x00000000
-
-/* HIF_INTR2 :: CPU_STATUS :: reserved4 [02:02] */
-#define BCHP_HIF_INTR2_CPU_STATUS_reserved4_MASK 0x00000004
-#define BCHP_HIF_INTR2_CPU_STATUS_reserved4_SHIFT 2
-
-/* HIF_INTR2 :: CPU_STATUS :: ITCH1_RD_INTR [01:01] */
-#define BCHP_HIF_INTR2_CPU_STATUS_ITCH1_RD_INTR_MASK 0x00000002
-#define BCHP_HIF_INTR2_CPU_STATUS_ITCH1_RD_INTR_SHIFT 1
-#define BCHP_HIF_INTR2_CPU_STATUS_ITCH1_RD_INTR_DEFAULT 0x00000000
-
-/* HIF_INTR2 :: CPU_STATUS :: HIF_RGR2_BRIDGE_INTR [00:00] */
-#define BCHP_HIF_INTR2_CPU_STATUS_HIF_RGR2_BRIDGE_INTR_MASK 0x00000001
-#define BCHP_HIF_INTR2_CPU_STATUS_HIF_RGR2_BRIDGE_INTR_SHIFT 0
-#define BCHP_HIF_INTR2_CPU_STATUS_HIF_RGR2_BRIDGE_INTR_DEFAULT 0x00000000
-
-/***************************************************************************
- *CPU_SET - CPU interrupt Set Register
- ***************************************************************************/
-/* HIF_INTR2 :: CPU_SET :: PCIE_LINKDOWN_INTR [31:31] */
-#define BCHP_HIF_INTR2_CPU_SET_PCIE_LINKDOWN_INTR_MASK 0x80000000
-#define BCHP_HIF_INTR2_CPU_SET_PCIE_LINKDOWN_INTR_SHIFT 31
-#define BCHP_HIF_INTR2_CPU_SET_PCIE_LINKDOWN_INTR_DEFAULT 0x00000000
-
-/* HIF_INTR2 :: CPU_SET :: PCIE_LINKUP_INTR [30:30] */
-#define BCHP_HIF_INTR2_CPU_SET_PCIE_LINKUP_INTR_MASK 0x40000000
-#define BCHP_HIF_INTR2_CPU_SET_PCIE_LINKUP_INTR_SHIFT 30
-#define BCHP_HIF_INTR2_CPU_SET_PCIE_LINKUP_INTR_DEFAULT 0x00000000
-
-/* HIF_INTR2 :: CPU_SET :: reserved0 [29:28] */
-#define BCHP_HIF_INTR2_CPU_SET_reserved0_MASK 0x30000000
-#define BCHP_HIF_INTR2_CPU_SET_reserved0_SHIFT 28
-
-/* HIF_INTR2 :: CPU_SET :: NAND_CORR_INTR [27:27] */
-#define BCHP_HIF_INTR2_CPU_SET_NAND_CORR_INTR_MASK 0x08000000
-#define BCHP_HIF_INTR2_CPU_SET_NAND_CORR_INTR_SHIFT 27
-#define BCHP_HIF_INTR2_CPU_SET_NAND_CORR_INTR_DEFAULT 0x00000000
-
-/* HIF_INTR2 :: CPU_SET :: NAND_UNC_INTR [26:26] */
-#define BCHP_HIF_INTR2_CPU_SET_NAND_UNC_INTR_MASK 0x04000000
-#define BCHP_HIF_INTR2_CPU_SET_NAND_UNC_INTR_SHIFT 26
-#define BCHP_HIF_INTR2_CPU_SET_NAND_UNC_INTR_DEFAULT 0x00000000
-
-/* HIF_INTR2 :: CPU_SET :: NAND_RBPIN_INTR [25:25] */
-#define BCHP_HIF_INTR2_CPU_SET_NAND_RBPIN_INTR_MASK 0x02000000
-#define BCHP_HIF_INTR2_CPU_SET_NAND_RBPIN_INTR_SHIFT 25
-#define BCHP_HIF_INTR2_CPU_SET_NAND_RBPIN_INTR_DEFAULT 0x00000000
-
-/* HIF_INTR2 :: CPU_SET :: NAND_CTLRDY_INTR [24:24] */
-#define BCHP_HIF_INTR2_CPU_SET_NAND_CTLRDY_INTR_MASK 0x01000000
-#define BCHP_HIF_INTR2_CPU_SET_NAND_CTLRDY_INTR_SHIFT 24
-#define BCHP_HIF_INTR2_CPU_SET_NAND_CTLRDY_INTR_DEFAULT 0x00000000
-
-/* HIF_INTR2 :: CPU_SET :: NAND_PGMPG_INTR [23:23] */
-#define BCHP_HIF_INTR2_CPU_SET_NAND_PGMPG_INTR_MASK 0x00800000
-#define BCHP_HIF_INTR2_CPU_SET_NAND_PGMPG_INTR_SHIFT 23
-#define BCHP_HIF_INTR2_CPU_SET_NAND_PGMPG_INTR_DEFAULT 0x00000000
-
-/* HIF_INTR2 :: CPU_SET :: NAND_CPYBK_INTR [22:22] */
-#define BCHP_HIF_INTR2_CPU_SET_NAND_CPYBK_INTR_MASK 0x00400000
-#define BCHP_HIF_INTR2_CPU_SET_NAND_CPYBK_INTR_SHIFT 22
-#define BCHP_HIF_INTR2_CPU_SET_NAND_CPYBK_INTR_DEFAULT 0x00000000
-
-/* HIF_INTR2 :: CPU_SET :: NAND_BLKERA_INTR [21:21] */
-#define BCHP_HIF_INTR2_CPU_SET_NAND_BLKERA_INTR_MASK 0x00200000
-#define BCHP_HIF_INTR2_CPU_SET_NAND_BLKERA_INTR_SHIFT 21
-#define BCHP_HIF_INTR2_CPU_SET_NAND_BLKERA_INTR_DEFAULT 0x00000000
-
-/* HIF_INTR2 :: CPU_SET :: NAND_NP_READ_INTR [20:20] */
-#define BCHP_HIF_INTR2_CPU_SET_NAND_NP_READ_INTR_MASK 0x00100000
-#define BCHP_HIF_INTR2_CPU_SET_NAND_NP_READ_INTR_SHIFT 20
-#define BCHP_HIF_INTR2_CPU_SET_NAND_NP_READ_INTR_DEFAULT 0x00000000
-
-/* HIF_INTR2 :: CPU_SET :: reserved1 [19:18] */
-#define BCHP_HIF_INTR2_CPU_SET_reserved1_MASK 0x000c0000
-#define BCHP_HIF_INTR2_CPU_SET_reserved1_SHIFT 18
-
-/* HIF_INTR2 :: CPU_SET :: EBI_TIMEOUT_INTR [17:17] */
-#define BCHP_HIF_INTR2_CPU_SET_EBI_TIMEOUT_INTR_MASK 0x00020000
-#define BCHP_HIF_INTR2_CPU_SET_EBI_TIMEOUT_INTR_SHIFT 17
-#define BCHP_HIF_INTR2_CPU_SET_EBI_TIMEOUT_INTR_DEFAULT 0x00000000
-
-/* HIF_INTR2 :: CPU_SET :: EBI_TEA_INTR [16:16] */
-#define BCHP_HIF_INTR2_CPU_SET_EBI_TEA_INTR_MASK 0x00010000
-#define BCHP_HIF_INTR2_CPU_SET_EBI_TEA_INTR_SHIFT 16
-#define BCHP_HIF_INTR2_CPU_SET_EBI_TEA_INTR_DEFAULT 0x00000000
-
-/* HIF_INTR2 :: CPU_SET :: ITCH0_RD_INTR [15:15] */
-#define BCHP_HIF_INTR2_CPU_SET_ITCH0_RD_INTR_MASK 0x00008000
-#define BCHP_HIF_INTR2_CPU_SET_ITCH0_RD_INTR_SHIFT 15
-#define BCHP_HIF_INTR2_CPU_SET_ITCH0_RD_INTR_DEFAULT 0x00000000
-
-/* HIF_INTR2 :: CPU_SET :: reserved2 [14:14] */
-#define BCHP_HIF_INTR2_CPU_SET_reserved2_MASK 0x00004000
-#define BCHP_HIF_INTR2_CPU_SET_reserved2_SHIFT 14
-
-/* HIF_INTR2 :: CPU_SET :: PCIE_RG_BRIDGE_INTR [13:13] */
-#define BCHP_HIF_INTR2_CPU_SET_PCIE_RG_BRIDGE_INTR_MASK 0x00002000
-#define BCHP_HIF_INTR2_CPU_SET_PCIE_RG_BRIDGE_INTR_SHIFT 13
-#define BCHP_HIF_INTR2_CPU_SET_PCIE_RG_BRIDGE_INTR_DEFAULT 0x00000000
-
-/* HIF_INTR2 :: CPU_SET :: PCIE_RGR_BRIDGE_INTR [12:12] */
-#define BCHP_HIF_INTR2_CPU_SET_PCIE_RGR_BRIDGE_INTR_MASK 0x00001000
-#define BCHP_HIF_INTR2_CPU_SET_PCIE_RGR_BRIDGE_INTR_SHIFT 12
-#define BCHP_HIF_INTR2_CPU_SET_PCIE_RGR_BRIDGE_INTR_DEFAULT 0x00000000
-
-/* HIF_INTR2 :: CPU_SET :: reserved3 [11:06] */
-#define BCHP_HIF_INTR2_CPU_SET_reserved3_MASK 0x00000fc0
-#define BCHP_HIF_INTR2_CPU_SET_reserved3_SHIFT 6
-
-/* HIF_INTR2 :: CPU_SET :: FLASH_DMA_ERR_INTR [05:05] */
-#define BCHP_HIF_INTR2_CPU_SET_FLASH_DMA_ERR_INTR_MASK 0x00000020
-#define BCHP_HIF_INTR2_CPU_SET_FLASH_DMA_ERR_INTR_SHIFT 5
-#define BCHP_HIF_INTR2_CPU_SET_FLASH_DMA_ERR_INTR_DEFAULT 0x00000000
-
-/* HIF_INTR2 :: CPU_SET :: FLASH_DMA_DONE_INTR [04:04] */
-#define BCHP_HIF_INTR2_CPU_SET_FLASH_DMA_DONE_INTR_MASK 0x00000010
-#define BCHP_HIF_INTR2_CPU_SET_FLASH_DMA_DONE_INTR_SHIFT 4
-#define BCHP_HIF_INTR2_CPU_SET_FLASH_DMA_DONE_INTR_DEFAULT 0x00000000
-
-/* HIF_INTR2 :: CPU_SET :: WEBHIF_WD_TIMEOUT_INTR [03:03] */
-#define BCHP_HIF_INTR2_CPU_SET_WEBHIF_WD_TIMEOUT_INTR_MASK 0x00000008
-#define BCHP_HIF_INTR2_CPU_SET_WEBHIF_WD_TIMEOUT_INTR_SHIFT 3
-#define BCHP_HIF_INTR2_CPU_SET_WEBHIF_WD_TIMEOUT_INTR_DEFAULT 0x00000000
-
-/* HIF_INTR2 :: CPU_SET :: reserved4 [02:02] */
-#define BCHP_HIF_INTR2_CPU_SET_reserved4_MASK 0x00000004
-#define BCHP_HIF_INTR2_CPU_SET_reserved4_SHIFT 2
-
-/* HIF_INTR2 :: CPU_SET :: ITCH1_RD_INTR [01:01] */
-#define BCHP_HIF_INTR2_CPU_SET_ITCH1_RD_INTR_MASK 0x00000002
-#define BCHP_HIF_INTR2_CPU_SET_ITCH1_RD_INTR_SHIFT 1
-#define BCHP_HIF_INTR2_CPU_SET_ITCH1_RD_INTR_DEFAULT 0x00000000
-
-/* HIF_INTR2 :: CPU_SET :: HIF_RGR2_BRIDGE_INTR [00:00] */
-#define BCHP_HIF_INTR2_CPU_SET_HIF_RGR2_BRIDGE_INTR_MASK 0x00000001
-#define BCHP_HIF_INTR2_CPU_SET_HIF_RGR2_BRIDGE_INTR_SHIFT 0
-#define BCHP_HIF_INTR2_CPU_SET_HIF_RGR2_BRIDGE_INTR_DEFAULT 0x00000000
-
-/***************************************************************************
- *CPU_CLEAR - CPU interrupt Clear Register
- ***************************************************************************/
-/* HIF_INTR2 :: CPU_CLEAR :: PCIE_LINKDOWN_INTR [31:31] */
-#define BCHP_HIF_INTR2_CPU_CLEAR_PCIE_LINKDOWN_INTR_MASK 0x80000000
-#define BCHP_HIF_INTR2_CPU_CLEAR_PCIE_LINKDOWN_INTR_SHIFT 31
-#define BCHP_HIF_INTR2_CPU_CLEAR_PCIE_LINKDOWN_INTR_DEFAULT 0x00000000
-
-/* HIF_INTR2 :: CPU_CLEAR :: PCIE_LINKUP_INTR [30:30] */
-#define BCHP_HIF_INTR2_CPU_CLEAR_PCIE_LINKUP_INTR_MASK 0x40000000
-#define BCHP_HIF_INTR2_CPU_CLEAR_PCIE_LINKUP_INTR_SHIFT 30
-#define BCHP_HIF_INTR2_CPU_CLEAR_PCIE_LINKUP_INTR_DEFAULT 0x00000000
-
-/* HIF_INTR2 :: CPU_CLEAR :: reserved0 [29:28] */
-#define BCHP_HIF_INTR2_CPU_CLEAR_reserved0_MASK 0x30000000
-#define BCHP_HIF_INTR2_CPU_CLEAR_reserved0_SHIFT 28
-
-/* HIF_INTR2 :: CPU_CLEAR :: NAND_CORR_INTR [27:27] */
-#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_CORR_INTR_MASK 0x08000000
-#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_CORR_INTR_SHIFT 27
-#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_CORR_INTR_DEFAULT 0x00000000
-
-/* HIF_INTR2 :: CPU_CLEAR :: NAND_UNC_INTR [26:26] */
-#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_UNC_INTR_MASK 0x04000000
-#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_UNC_INTR_SHIFT 26
-#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_UNC_INTR_DEFAULT 0x00000000
-
-/* HIF_INTR2 :: CPU_CLEAR :: NAND_RBPIN_INTR [25:25] */
-#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_RBPIN_INTR_MASK 0x02000000
-#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_RBPIN_INTR_SHIFT 25
-#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_RBPIN_INTR_DEFAULT 0x00000000
-
-/* HIF_INTR2 :: CPU_CLEAR :: NAND_CTLRDY_INTR [24:24] */
-#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_CTLRDY_INTR_MASK 0x01000000
-#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_CTLRDY_INTR_SHIFT 24
-#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_CTLRDY_INTR_DEFAULT 0x00000000
-
-/* HIF_INTR2 :: CPU_CLEAR :: NAND_PGMPG_INTR [23:23] */
-#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_PGMPG_INTR_MASK 0x00800000
-#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_PGMPG_INTR_SHIFT 23
-#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_PGMPG_INTR_DEFAULT 0x00000000
-
-/* HIF_INTR2 :: CPU_CLEAR :: NAND_CPYBK_INTR [22:22] */
-#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_CPYBK_INTR_MASK 0x00400000
-#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_CPYBK_INTR_SHIFT 22
-#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_CPYBK_INTR_DEFAULT 0x00000000
-
-/* HIF_INTR2 :: CPU_CLEAR :: NAND_BLKERA_INTR [21:21] */
-#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_BLKERA_INTR_MASK 0x00200000
-#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_BLKERA_INTR_SHIFT 21
-#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_BLKERA_INTR_DEFAULT 0x00000000
-
-/* HIF_INTR2 :: CPU_CLEAR :: NAND_NP_READ_INTR [20:20] */
-#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_NP_READ_INTR_MASK 0x00100000
-#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_NP_READ_INTR_SHIFT 20
-#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_NP_READ_INTR_DEFAULT 0x00000000
-
-/* HIF_INTR2 :: CPU_CLEAR :: reserved1 [19:18] */
-#define BCHP_HIF_INTR2_CPU_CLEAR_reserved1_MASK 0x000c0000
-#define BCHP_HIF_INTR2_CPU_CLEAR_reserved1_SHIFT 18
-
-/* HIF_INTR2 :: CPU_CLEAR :: EBI_TIMEOUT_INTR [17:17] */
-#define BCHP_HIF_INTR2_CPU_CLEAR_EBI_TIMEOUT_INTR_MASK 0x00020000
-#define BCHP_HIF_INTR2_CPU_CLEAR_EBI_TIMEOUT_INTR_SHIFT 17
-#define BCHP_HIF_INTR2_CPU_CLEAR_EBI_TIMEOUT_INTR_DEFAULT 0x00000000
-
-/* HIF_INTR2 :: CPU_CLEAR :: EBI_TEA_INTR [16:16] */
-#define BCHP_HIF_INTR2_CPU_CLEAR_EBI_TEA_INTR_MASK 0x00010000
-#define BCHP_HIF_INTR2_CPU_CLEAR_EBI_TEA_INTR_SHIFT 16
-#define BCHP_HIF_INTR2_CPU_CLEAR_EBI_TEA_INTR_DEFAULT 0x00000000
-
-/* HIF_INTR2 :: CPU_CLEAR :: ITCH0_RD_INTR [15:15] */
-#define BCHP_HIF_INTR2_CPU_CLEAR_ITCH0_RD_INTR_MASK 0x00008000
-#define BCHP_HIF_INTR2_CPU_CLEAR_ITCH0_RD_INTR_SHIFT 15
-#define BCHP_HIF_INTR2_CPU_CLEAR_ITCH0_RD_INTR_DEFAULT 0x00000000
-
-/* HIF_INTR2 :: CPU_CLEAR :: reserved2 [14:14] */
-#define BCHP_HIF_INTR2_CPU_CLEAR_reserved2_MASK 0x00004000
-#define BCHP_HIF_INTR2_CPU_CLEAR_reserved2_SHIFT 14
-
-/* HIF_INTR2 :: CPU_CLEAR :: PCIE_RG_BRIDGE_INTR [13:13] */
-#define BCHP_HIF_INTR2_CPU_CLEAR_PCIE_RG_BRIDGE_INTR_MASK 0x00002000
-#define BCHP_HIF_INTR2_CPU_CLEAR_PCIE_RG_BRIDGE_INTR_SHIFT 13
-#define BCHP_HIF_INTR2_CPU_CLEAR_PCIE_RG_BRIDGE_INTR_DEFAULT 0x00000000
-
-/* HIF_INTR2 :: CPU_CLEAR :: PCIE_RGR_BRIDGE_INTR [12:12] */
-#define BCHP_HIF_INTR2_CPU_CLEAR_PCIE_RGR_BRIDGE_INTR_MASK 0x00001000
-#define BCHP_HIF_INTR2_CPU_CLEAR_PCIE_RGR_BRIDGE_INTR_SHIFT 12
-#define BCHP_HIF_INTR2_CPU_CLEAR_PCIE_RGR_BRIDGE_INTR_DEFAULT 0x00000000
-
-/* HIF_INTR2 :: CPU_CLEAR :: reserved3 [11:06] */
-#define BCHP_HIF_INTR2_CPU_CLEAR_reserved3_MASK 0x00000fc0
-#define BCHP_HIF_INTR2_CPU_CLEAR_reserved3_SHIFT 6
-
-/* HIF_INTR2 :: CPU_CLEAR :: FLASH_DMA_ERR_INTR [05:05] */
-#define BCHP_HIF_INTR2_CPU_CLEAR_FLASH_DMA_ERR_INTR_MASK 0x00000020
-#define BCHP_HIF_INTR2_CPU_CLEAR_FLASH_DMA_ERR_INTR_SHIFT 5
-#define BCHP_HIF_INTR2_CPU_CLEAR_FLASH_DMA_ERR_INTR_DEFAULT 0x00000000
-
-/* HIF_INTR2 :: CPU_CLEAR :: FLASH_DMA_DONE_INTR [04:04] */
-#define BCHP_HIF_INTR2_CPU_CLEAR_FLASH_DMA_DONE_INTR_MASK 0x00000010
-#define BCHP_HIF_INTR2_CPU_CLEAR_FLASH_DMA_DONE_INTR_SHIFT 4
-#define BCHP_HIF_INTR2_CPU_CLEAR_FLASH_DMA_DONE_INTR_DEFAULT 0x00000000
-
-/* HIF_INTR2 :: CPU_CLEAR :: WEBHIF_WD_TIMEOUT_INTR [03:03] */
-#define BCHP_HIF_INTR2_CPU_CLEAR_WEBHIF_WD_TIMEOUT_INTR_MASK 0x00000008
-#define BCHP_HIF_INTR2_CPU_CLEAR_WEBHIF_WD_TIMEOUT_INTR_SHIFT 3
-#define BCHP_HIF_INTR2_CPU_CLEAR_WEBHIF_WD_TIMEOUT_INTR_DEFAULT 0x00000000
-
-/* HIF_INTR2 :: CPU_CLEAR :: reserved4 [02:02] */
-#define BCHP_HIF_INTR2_CPU_CLEAR_reserved4_MASK 0x00000004
-#define BCHP_HIF_INTR2_CPU_CLEAR_reserved4_SHIFT 2
-
-/* HIF_INTR2 :: CPU_CLEAR :: ITCH1_RD_INTR [01:01] */
-#define BCHP_HIF_INTR2_CPU_CLEAR_ITCH1_RD_INTR_MASK 0x00000002
-#define BCHP_HIF_INTR2_CPU_CLEAR_ITCH1_RD_INTR_SHIFT 1
-#define BCHP_HIF_INTR2_CPU_CLEAR_ITCH1_RD_INTR_DEFAULT 0x00000000
-
-/* HIF_INTR2 :: CPU_CLEAR :: HIF_RGR2_BRIDGE_INTR [00:00] */
-#define BCHP_HIF_INTR2_CPU_CLEAR_HIF_RGR2_BRIDGE_INTR_MASK 0x00000001
-#define BCHP_HIF_INTR2_CPU_CLEAR_HIF_RGR2_BRIDGE_INTR_SHIFT 0
-#define BCHP_HIF_INTR2_CPU_CLEAR_HIF_RGR2_BRIDGE_INTR_DEFAULT 0x00000000
-
-/***************************************************************************
- *CPU_MASK_STATUS - CPU interrupt Mask Status Register
- ***************************************************************************/
-/* HIF_INTR2 :: CPU_MASK_STATUS :: PCIE_LINKDOWN_INTR [31:31] */
-#define BCHP_HIF_INTR2_CPU_MASK_STATUS_PCIE_LINKDOWN_INTR_MASK 0x80000000
-#define BCHP_HIF_INTR2_CPU_MASK_STATUS_PCIE_LINKDOWN_INTR_SHIFT 31
-#define BCHP_HIF_INTR2_CPU_MASK_STATUS_PCIE_LINKDOWN_INTR_DEFAULT 0x00000000
-
-/* HIF_INTR2 :: CPU_MASK_STATUS :: PCIE_LINKUP_INTR [30:30] */
-#define BCHP_HIF_INTR2_CPU_MASK_STATUS_PCIE_LINKUP_INTR_MASK 0x40000000
-#define BCHP_HIF_INTR2_CPU_MASK_STATUS_PCIE_LINKUP_INTR_SHIFT 30
-#define BCHP_HIF_INTR2_CPU_MASK_STATUS_PCIE_LINKUP_INTR_DEFAULT 0x00000000
-
-/* HIF_INTR2 :: CPU_MASK_STATUS :: reserved0 [29:28] */
-#define BCHP_HIF_INTR2_CPU_MASK_STATUS_reserved0_MASK 0x30000000
-#define BCHP_HIF_INTR2_CPU_MASK_STATUS_reserved0_SHIFT 28
-
-/* HIF_INTR2 :: CPU_MASK_STATUS :: NAND_CORR_INTR [27:27] */
-#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_CORR_INTR_MASK 0x08000000
-#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_CORR_INTR_SHIFT 27
-#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_CORR_INTR_DEFAULT 0x00000001
-
-/* HIF_INTR2 :: CPU_MASK_STATUS :: NAND_UNC_INTR [26:26] */
-#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_UNC_INTR_MASK 0x04000000
-#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_UNC_INTR_SHIFT 26
-#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_UNC_INTR_DEFAULT 0x00000001
-
-/* HIF_INTR2 :: CPU_MASK_STATUS :: NAND_RBPIN_INTR [25:25] */
-#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_RBPIN_INTR_MASK 0x02000000
-#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_RBPIN_INTR_SHIFT 25
-#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_RBPIN_INTR_DEFAULT 0x00000001
-
-/* HIF_INTR2 :: CPU_MASK_STATUS :: NAND_CTLRDY_INTR [24:24] */
-#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_CTLRDY_INTR_MASK 0x01000000
-#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_CTLRDY_INTR_SHIFT 24
-#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_CTLRDY_INTR_DEFAULT 0x00000001
-
-/* HIF_INTR2 :: CPU_MASK_STATUS :: NAND_PGMPG_INTR [23:23] */
-#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_PGMPG_INTR_MASK 0x00800000
-#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_PGMPG_INTR_SHIFT 23
-#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_PGMPG_INTR_DEFAULT 0x00000001
-
-/* HIF_INTR2 :: CPU_MASK_STATUS :: NAND_CPYBK_INTR [22:22] */
-#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_CPYBK_INTR_MASK 0x00400000
-#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_CPYBK_INTR_SHIFT 22
-#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_CPYBK_INTR_DEFAULT 0x00000001
-
-/* HIF_INTR2 :: CPU_MASK_STATUS :: NAND_BLKERA_INTR [21:21] */
-#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_BLKERA_INTR_MASK 0x00200000
-#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_BLKERA_INTR_SHIFT 21
-#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_BLKERA_INTR_DEFAULT 0x00000001
-
-/* HIF_INTR2 :: CPU_MASK_STATUS :: NAND_NP_READ_INTR [20:20] */
-#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_NP_READ_INTR_MASK 0x00100000
-#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_NP_READ_INTR_SHIFT 20
-#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_NP_READ_INTR_DEFAULT 0x00000001
-
-/* HIF_INTR2 :: CPU_MASK_STATUS :: reserved1 [19:18] */
-#define BCHP_HIF_INTR2_CPU_MASK_STATUS_reserved1_MASK 0x000c0000
-#define BCHP_HIF_INTR2_CPU_MASK_STATUS_reserved1_SHIFT 18
-
-/* HIF_INTR2 :: CPU_MASK_STATUS :: EBI_TIMEOUT_INTR [17:17] */
-#define BCHP_HIF_INTR2_CPU_MASK_STATUS_EBI_TIMEOUT_INTR_MASK 0x00020000
-#define BCHP_HIF_INTR2_CPU_MASK_STATUS_EBI_TIMEOUT_INTR_SHIFT 17
-#define BCHP_HIF_INTR2_CPU_MASK_STATUS_EBI_TIMEOUT_INTR_DEFAULT 0x00000001
-
-/* HIF_INTR2 :: CPU_MASK_STATUS :: EBI_TEA_INTR [16:16] */
-#define BCHP_HIF_INTR2_CPU_MASK_STATUS_EBI_TEA_INTR_MASK 0x00010000
-#define BCHP_HIF_INTR2_CPU_MASK_STATUS_EBI_TEA_INTR_SHIFT 16
-#define BCHP_HIF_INTR2_CPU_MASK_STATUS_EBI_TEA_INTR_DEFAULT 0x00000001
-
-/* HIF_INTR2 :: CPU_MASK_STATUS :: ITCH0_RD_INTR [15:15] */
-#define BCHP_HIF_INTR2_CPU_MASK_STATUS_ITCH0_RD_INTR_MASK 0x00008000
-#define BCHP_HIF_INTR2_CPU_MASK_STATUS_ITCH0_RD_INTR_SHIFT 15
-#define BCHP_HIF_INTR2_CPU_MASK_STATUS_ITCH0_RD_INTR_DEFAULT 0x00000001
-
-/* HIF_INTR2 :: CPU_MASK_STATUS :: reserved2 [14:14] */
-#define BCHP_HIF_INTR2_CPU_MASK_STATUS_reserved2_MASK 0x00004000
-#define BCHP_HIF_INTR2_CPU_MASK_STATUS_reserved2_SHIFT 14
-
-/* HIF_INTR2 :: CPU_MASK_STATUS :: PCIE_RG_BRIDGE_INTR [13:13] */
-#define BCHP_HIF_INTR2_CPU_MASK_STATUS_PCIE_RG_BRIDGE_INTR_MASK 0x00002000
-#define BCHP_HIF_INTR2_CPU_MASK_STATUS_PCIE_RG_BRIDGE_INTR_SHIFT 13
-#define BCHP_HIF_INTR2_CPU_MASK_STATUS_PCIE_RG_BRIDGE_INTR_DEFAULT 0x00000001
-
-/* HIF_INTR2 :: CPU_MASK_STATUS :: PCIE_RGR_BRIDGE_INTR [12:12] */
-#define BCHP_HIF_INTR2_CPU_MASK_STATUS_PCIE_RGR_BRIDGE_INTR_MASK 0x00001000
-#define BCHP_HIF_INTR2_CPU_MASK_STATUS_PCIE_RGR_BRIDGE_INTR_SHIFT 12
-#define BCHP_HIF_INTR2_CPU_MASK_STATUS_PCIE_RGR_BRIDGE_INTR_DEFAULT 0x00000001
-
-/* HIF_INTR2 :: CPU_MASK_STATUS :: reserved3 [11:06] */
-#define BCHP_HIF_INTR2_CPU_MASK_STATUS_reserved3_MASK 0x00000fc0
-#define BCHP_HIF_INTR2_CPU_MASK_STATUS_reserved3_SHIFT 6
-
-/* HIF_INTR2 :: CPU_MASK_STATUS :: FLASH_DMA_ERR_INTR [05:05] */
-#define BCHP_HIF_INTR2_CPU_MASK_STATUS_FLASH_DMA_ERR_INTR_MASK 0x00000020
-#define BCHP_HIF_INTR2_CPU_MASK_STATUS_FLASH_DMA_ERR_INTR_SHIFT 5
-#define BCHP_HIF_INTR2_CPU_MASK_STATUS_FLASH_DMA_ERR_INTR_DEFAULT 0x00000000
-
-/* HIF_INTR2 :: CPU_MASK_STATUS :: FLASH_DMA_DONE_INTR [04:04] */
-#define BCHP_HIF_INTR2_CPU_MASK_STATUS_FLASH_DMA_DONE_INTR_MASK 0x00000010
-#define BCHP_HIF_INTR2_CPU_MASK_STATUS_FLASH_DMA_DONE_INTR_SHIFT 4
-#define BCHP_HIF_INTR2_CPU_MASK_STATUS_FLASH_DMA_DONE_INTR_DEFAULT 0x00000000
-
-/* HIF_INTR2 :: CPU_MASK_STATUS :: WEBHIF_WD_TIMEOUT_INTR [03:03] */
-#define BCHP_HIF_INTR2_CPU_MASK_STATUS_WEBHIF_WD_TIMEOUT_INTR_MASK 0x00000008
-#define BCHP_HIF_INTR2_CPU_MASK_STATUS_WEBHIF_WD_TIMEOUT_INTR_SHIFT 3
-#define BCHP_HIF_INTR2_CPU_MASK_STATUS_WEBHIF_WD_TIMEOUT_INTR_DEFAULT 0x00000000
-
-/* HIF_INTR2 :: CPU_MASK_STATUS :: reserved4 [02:02] */
-#define BCHP_HIF_INTR2_CPU_MASK_STATUS_reserved4_MASK 0x00000004
-#define BCHP_HIF_INTR2_CPU_MASK_STATUS_reserved4_SHIFT 2
-
-/* HIF_INTR2 :: CPU_MASK_STATUS :: ITCH1_RD_INTR [01:01] */
-#define BCHP_HIF_INTR2_CPU_MASK_STATUS_ITCH1_RD_INTR_MASK 0x00000002
-#define BCHP_HIF_INTR2_CPU_MASK_STATUS_ITCH1_RD_INTR_SHIFT 1
-#define BCHP_HIF_INTR2_CPU_MASK_STATUS_ITCH1_RD_INTR_DEFAULT 0x00000001
-
-/* HIF_INTR2 :: CPU_MASK_STATUS :: HIF_RGR2_BRIDGE_INTR [00:00] */
-#define BCHP_HIF_INTR2_CPU_MASK_STATUS_HIF_RGR2_BRIDGE_INTR_MASK 0x00000001
-#define BCHP_HIF_INTR2_CPU_MASK_STATUS_HIF_RGR2_BRIDGE_INTR_SHIFT 0
-#define BCHP_HIF_INTR2_CPU_MASK_STATUS_HIF_RGR2_BRIDGE_INTR_DEFAULT 0x00000001
-
-/***************************************************************************
- *CPU_MASK_SET - CPU interrupt Mask Set Register
- ***************************************************************************/
-/* HIF_INTR2 :: CPU_MASK_SET :: PCIE_LINKDOWN_INTR [31:31] */
-#define BCHP_HIF_INTR2_CPU_MASK_SET_PCIE_LINKDOWN_INTR_MASK 0x80000000
-#define BCHP_HIF_INTR2_CPU_MASK_SET_PCIE_LINKDOWN_INTR_SHIFT 31
-#define BCHP_HIF_INTR2_CPU_MASK_SET_PCIE_LINKDOWN_INTR_DEFAULT 0x00000000
-
-/* HIF_INTR2 :: CPU_MASK_SET :: PCIE_LINKUP_INTR [30:30] */
-#define BCHP_HIF_INTR2_CPU_MASK_SET_PCIE_LINKUP_INTR_MASK 0x40000000
-#define BCHP_HIF_INTR2_CPU_MASK_SET_PCIE_LINKUP_INTR_SHIFT 30
-#define BCHP_HIF_INTR2_CPU_MASK_SET_PCIE_LINKUP_INTR_DEFAULT 0x00000000
-
-/* HIF_INTR2 :: CPU_MASK_SET :: reserved0 [29:28] */
-#define BCHP_HIF_INTR2_CPU_MASK_SET_reserved0_MASK 0x30000000
-#define BCHP_HIF_INTR2_CPU_MASK_SET_reserved0_SHIFT 28
-
-/* HIF_INTR2 :: CPU_MASK_SET :: NAND_CORR_INTR [27:27] */
-#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_CORR_INTR_MASK 0x08000000
-#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_CORR_INTR_SHIFT 27
-#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_CORR_INTR_DEFAULT 0x00000001
-
-/* HIF_INTR2 :: CPU_MASK_SET :: NAND_UNC_INTR [26:26] */
-#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_UNC_INTR_MASK 0x04000000
-#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_UNC_INTR_SHIFT 26
-#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_UNC_INTR_DEFAULT 0x00000001
-
-/* HIF_INTR2 :: CPU_MASK_SET :: NAND_RBPIN_INTR [25:25] */
-#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_RBPIN_INTR_MASK 0x02000000
-#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_RBPIN_INTR_SHIFT 25
-#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_RBPIN_INTR_DEFAULT 0x00000001
-
-/* HIF_INTR2 :: CPU_MASK_SET :: NAND_CTLRDY_INTR [24:24] */
-#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_CTLRDY_INTR_MASK 0x01000000
-#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_CTLRDY_INTR_SHIFT 24
-#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_CTLRDY_INTR_DEFAULT 0x00000001
-
-/* HIF_INTR2 :: CPU_MASK_SET :: NAND_PGMPG_INTR [23:23] */
-#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_PGMPG_INTR_MASK 0x00800000
-#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_PGMPG_INTR_SHIFT 23
-#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_PGMPG_INTR_DEFAULT 0x00000001
-
-/* HIF_INTR2 :: CPU_MASK_SET :: NAND_CPYBK_INTR [22:22] */
-#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_CPYBK_INTR_MASK 0x00400000
-#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_CPYBK_INTR_SHIFT 22
-#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_CPYBK_INTR_DEFAULT 0x00000001
-
-/* HIF_INTR2 :: CPU_MASK_SET :: NAND_BLKERA_INTR [21:21] */
-#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_BLKERA_INTR_MASK 0x00200000
-#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_BLKERA_INTR_SHIFT 21
-#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_BLKERA_INTR_DEFAULT 0x00000001
-
-/* HIF_INTR2 :: CPU_MASK_SET :: NAND_NP_READ_INTR [20:20] */
-#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_NP_READ_INTR_MASK 0x00100000
-#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_NP_READ_INTR_SHIFT 20
-#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_NP_READ_INTR_DEFAULT 0x00000001
-
-/* HIF_INTR2 :: CPU_MASK_SET :: reserved1 [19:18] */
-#define BCHP_HIF_INTR2_CPU_MASK_SET_reserved1_MASK 0x000c0000
-#define BCHP_HIF_INTR2_CPU_MASK_SET_reserved1_SHIFT 18
-
-/* HIF_INTR2 :: CPU_MASK_SET :: EBI_TIMEOUT_INTR [17:17] */
-#define BCHP_HIF_INTR2_CPU_MASK_SET_EBI_TIMEOUT_INTR_MASK 0x00020000
-#define BCHP_HIF_INTR2_CPU_MASK_SET_EBI_TIMEOUT_INTR_SHIFT 17
-#define BCHP_HIF_INTR2_CPU_MASK_SET_EBI_TIMEOUT_INTR_DEFAULT 0x00000001
-
-/* HIF_INTR2 :: CPU_MASK_SET :: EBI_TEA_INTR [16:16] */
-#define BCHP_HIF_INTR2_CPU_MASK_SET_EBI_TEA_INTR_MASK 0x00010000
-#define BCHP_HIF_INTR2_CPU_MASK_SET_EBI_TEA_INTR_SHIFT 16
-#define BCHP_HIF_INTR2_CPU_MASK_SET_EBI_TEA_INTR_DEFAULT 0x00000001
-
-/* HIF_INTR2 :: CPU_MASK_SET :: ITCH0_RD_INTR [15:15] */
-#define BCHP_HIF_INTR2_CPU_MASK_SET_ITCH0_RD_INTR_MASK 0x00008000
-#define BCHP_HIF_INTR2_CPU_MASK_SET_ITCH0_RD_INTR_SHIFT 15
-#define BCHP_HIF_INTR2_CPU_MASK_SET_ITCH0_RD_INTR_DEFAULT 0x00000001
-
-/* HIF_INTR2 :: CPU_MASK_SET :: reserved2 [14:14] */
-#define BCHP_HIF_INTR2_CPU_MASK_SET_reserved2_MASK 0x00004000
-#define BCHP_HIF_INTR2_CPU_MASK_SET_reserved2_SHIFT 14
-
-/* HIF_INTR2 :: CPU_MASK_SET :: PCIE_RG_BRIDGE_INTR [13:13] */
-#define BCHP_HIF_INTR2_CPU_MASK_SET_PCIE_RG_BRIDGE_INTR_MASK 0x00002000
-#define BCHP_HIF_INTR2_CPU_MASK_SET_PCIE_RG_BRIDGE_INTR_SHIFT 13
-#define BCHP_HIF_INTR2_CPU_MASK_SET_PCIE_RG_BRIDGE_INTR_DEFAULT 0x00000001
-
-/* HIF_INTR2 :: CPU_MASK_SET :: PCIE_RGR_BRIDGE_INTR [12:12] */
-#define BCHP_HIF_INTR2_CPU_MASK_SET_PCIE_RGR_BRIDGE_INTR_MASK 0x00001000
-#define BCHP_HIF_INTR2_CPU_MASK_SET_PCIE_RGR_BRIDGE_INTR_SHIFT 12
-#define BCHP_HIF_INTR2_CPU_MASK_SET_PCIE_RGR_BRIDGE_INTR_DEFAULT 0x00000001
-
-/* HIF_INTR2 :: CPU_MASK_SET :: reserved3 [11:06] */
-#define BCHP_HIF_INTR2_CPU_MASK_SET_reserved3_MASK 0x00000fc0
-#define BCHP_HIF_INTR2_CPU_MASK_SET_reserved3_SHIFT 6
-
-/* HIF_INTR2 :: CPU_MASK_SET :: FLASH_DMA_ERR_INTR [05:05] */
-#define BCHP_HIF_INTR2_CPU_MASK_SET_FLASH_DMA_ERR_INTR_MASK 0x00000020
-#define BCHP_HIF_INTR2_CPU_MASK_SET_FLASH_DMA_ERR_INTR_SHIFT 5
-#define BCHP_HIF_INTR2_CPU_MASK_SET_FLASH_DMA_ERR_INTR_DEFAULT 0x00000000
-
-/* HIF_INTR2 :: CPU_MASK_SET :: FLASH_DMA_DONE_INTR [04:04] */
-#define BCHP_HIF_INTR2_CPU_MASK_SET_FLASH_DMA_DONE_INTR_MASK 0x00000010
-#define BCHP_HIF_INTR2_CPU_MASK_SET_FLASH_DMA_DONE_INTR_SHIFT 4
-#define BCHP_HIF_INTR2_CPU_MASK_SET_FLASH_DMA_DONE_INTR_DEFAULT 0x00000000
-
-/* HIF_INTR2 :: CPU_MASK_SET :: WEBHIF_WD_TIMEOUT_INTR [03:03] */
-#define BCHP_HIF_INTR2_CPU_MASK_SET_WEBHIF_WD_TIMEOUT_INTR_MASK 0x00000008
-#define BCHP_HIF_INTR2_CPU_MASK_SET_WEBHIF_WD_TIMEOUT_INTR_SHIFT 3
-#define BCHP_HIF_INTR2_CPU_MASK_SET_WEBHIF_WD_TIMEOUT_INTR_DEFAULT 0x00000000
-
-/* HIF_INTR2 :: CPU_MASK_SET :: reserved4 [02:02] */
-#define BCHP_HIF_INTR2_CPU_MASK_SET_reserved4_MASK 0x00000004
-#define BCHP_HIF_INTR2_CPU_MASK_SET_reserved4_SHIFT 2
-
-/* HIF_INTR2 :: CPU_MASK_SET :: ITCH1_RD_INTR [01:01] */
-#define BCHP_HIF_INTR2_CPU_MASK_SET_ITCH1_RD_INTR_MASK 0x00000002
-#define BCHP_HIF_INTR2_CPU_MASK_SET_ITCH1_RD_INTR_SHIFT 1
-#define BCHP_HIF_INTR2_CPU_MASK_SET_ITCH1_RD_INTR_DEFAULT 0x00000001
-
-/* HIF_INTR2 :: CPU_MASK_SET :: HIF_RGR2_BRIDGE_INTR [00:00] */
-#define BCHP_HIF_INTR2_CPU_MASK_SET_HIF_RGR2_BRIDGE_INTR_MASK 0x00000001
-#define BCHP_HIF_INTR2_CPU_MASK_SET_HIF_RGR2_BRIDGE_INTR_SHIFT 0
-#define BCHP_HIF_INTR2_CPU_MASK_SET_HIF_RGR2_BRIDGE_INTR_DEFAULT 0x00000001
-
-/***************************************************************************
- *CPU_MASK_CLEAR - CPU interrupt Mask Clear Register
- ***************************************************************************/
-/* HIF_INTR2 :: CPU_MASK_CLEAR :: PCIE_LINKDOWN_INTR [31:31] */
-#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_PCIE_LINKDOWN_INTR_MASK 0x80000000
-#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_PCIE_LINKDOWN_INTR_SHIFT 31
-#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_PCIE_LINKDOWN_INTR_DEFAULT 0x00000000
-
-/* HIF_INTR2 :: CPU_MASK_CLEAR :: PCIE_LINKUP_INTR [30:30] */
-#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_PCIE_LINKUP_INTR_MASK 0x40000000
-#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_PCIE_LINKUP_INTR_SHIFT 30
-#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_PCIE_LINKUP_INTR_DEFAULT 0x00000000
-
-/* HIF_INTR2 :: CPU_MASK_CLEAR :: reserved0 [29:28] */
-#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_reserved0_MASK 0x30000000
-#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_reserved0_SHIFT 28
-
-/* HIF_INTR2 :: CPU_MASK_CLEAR :: NAND_CORR_INTR [27:27] */
-#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_CORR_INTR_MASK 0x08000000
-#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_CORR_INTR_SHIFT 27
-#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_CORR_INTR_DEFAULT 0x00000001
-
-/* HIF_INTR2 :: CPU_MASK_CLEAR :: NAND_UNC_INTR [26:26] */
-#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_UNC_INTR_MASK 0x04000000
-#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_UNC_INTR_SHIFT 26
-#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_UNC_INTR_DEFAULT 0x00000001
-
-/* HIF_INTR2 :: CPU_MASK_CLEAR :: NAND_RBPIN_INTR [25:25] */
-#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_RBPIN_INTR_MASK 0x02000000
-#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_RBPIN_INTR_SHIFT 25
-#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_RBPIN_INTR_DEFAULT 0x00000001
-
-/* HIF_INTR2 :: CPU_MASK_CLEAR :: NAND_CTLRDY_INTR [24:24] */
-#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_CTLRDY_INTR_MASK 0x01000000
-#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_CTLRDY_INTR_SHIFT 24
-#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_CTLRDY_INTR_DEFAULT 0x00000001
-
-/* HIF_INTR2 :: CPU_MASK_CLEAR :: NAND_PGMPG_INTR [23:23] */
-#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_PGMPG_INTR_MASK 0x00800000
-#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_PGMPG_INTR_SHIFT 23
-#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_PGMPG_INTR_DEFAULT 0x00000001
-
-/* HIF_INTR2 :: CPU_MASK_CLEAR :: NAND_CPYBK_INTR [22:22] */
-#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_CPYBK_INTR_MASK 0x00400000
-#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_CPYBK_INTR_SHIFT 22
-#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_CPYBK_INTR_DEFAULT 0x00000001
-
-/* HIF_INTR2 :: CPU_MASK_CLEAR :: NAND_BLKERA_INTR [21:21] */
-#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_BLKERA_INTR_MASK 0x00200000
-#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_BLKERA_INTR_SHIFT 21
-#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_BLKERA_INTR_DEFAULT 0x00000001
-
-/* HIF_INTR2 :: CPU_MASK_CLEAR :: NAND_NP_READ_INTR [20:20] */
-#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_NP_READ_INTR_MASK 0x00100000
-#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_NP_READ_INTR_SHIFT 20
-#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_NP_READ_INTR_DEFAULT 0x00000001
-
-/* HIF_INTR2 :: CPU_MASK_CLEAR :: reserved1 [19:18] */
-#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_reserved1_MASK 0x000c0000
-#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_reserved1_SHIFT 18
-
-/* HIF_INTR2 :: CPU_MASK_CLEAR :: EBI_TIMEOUT_INTR [17:17] */
-#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_EBI_TIMEOUT_INTR_MASK 0x00020000
-#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_EBI_TIMEOUT_INTR_SHIFT 17
-#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_EBI_TIMEOUT_INTR_DEFAULT 0x00000001
-
-/* HIF_INTR2 :: CPU_MASK_CLEAR :: EBI_TEA_INTR [16:16] */
-#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_EBI_TEA_INTR_MASK 0x00010000
-#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_EBI_TEA_INTR_SHIFT 16
-#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_EBI_TEA_INTR_DEFAULT 0x00000001
-
-/* HIF_INTR2 :: CPU_MASK_CLEAR :: ITCH0_RD_INTR [15:15] */
-#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_ITCH0_RD_INTR_MASK 0x00008000
-#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_ITCH0_RD_INTR_SHIFT 15
-#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_ITCH0_RD_INTR_DEFAULT 0x00000001
-
-/* HIF_INTR2 :: CPU_MASK_CLEAR :: reserved2 [14:14] */
-#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_reserved2_MASK 0x00004000
-#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_reserved2_SHIFT 14
-
-/* HIF_INTR2 :: CPU_MASK_CLEAR :: PCIE_RG_BRIDGE_INTR [13:13] */
-#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_PCIE_RG_BRIDGE_INTR_MASK 0x00002000
-#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_PCIE_RG_BRIDGE_INTR_SHIFT 13
-#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_PCIE_RG_BRIDGE_INTR_DEFAULT 0x00000001
-
-/* HIF_INTR2 :: CPU_MASK_CLEAR :: PCIE_RGR_BRIDGE_INTR [12:12] */
-#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_PCIE_RGR_BRIDGE_INTR_MASK 0x00001000
-#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_PCIE_RGR_BRIDGE_INTR_SHIFT 12
-#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_PCIE_RGR_BRIDGE_INTR_DEFAULT 0x00000001
-
-/* HIF_INTR2 :: CPU_MASK_CLEAR :: reserved3 [11:06] */
-#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_reserved3_MASK 0x00000fc0
-#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_reserved3_SHIFT 6
-
-/* HIF_INTR2 :: CPU_MASK_CLEAR :: FLASH_DMA_ERR_INTR [05:05] */
-#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_FLASH_DMA_ERR_INTR_MASK 0x00000020
-#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_FLASH_DMA_ERR_INTR_SHIFT 5
-#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_FLASH_DMA_ERR_INTR_DEFAULT 0x00000000
-
-/* HIF_INTR2 :: CPU_MASK_CLEAR :: FLASH_DMA_DONE_INTR [04:04] */
-#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_FLASH_DMA_DONE_INTR_MASK 0x00000010
-#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_FLASH_DMA_DONE_INTR_SHIFT 4
-#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_FLASH_DMA_DONE_INTR_DEFAULT 0x00000000
-
-/* HIF_INTR2 :: CPU_MASK_CLEAR :: WEBHIF_WD_TIMEOUT_INTR [03:03] */
-#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_WEBHIF_WD_TIMEOUT_INTR_MASK 0x00000008
-#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_WEBHIF_WD_TIMEOUT_INTR_SHIFT 3
-#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_WEBHIF_WD_TIMEOUT_INTR_DEFAULT 0x00000000
-
-/* HIF_INTR2 :: CPU_MASK_CLEAR :: reserved4 [02:02] */
-#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_reserved4_MASK 0x00000004
-#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_reserved4_SHIFT 2
-
-/* HIF_INTR2 :: CPU_MASK_CLEAR :: ITCH1_RD_INTR [01:01] */
-#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_ITCH1_RD_INTR_MASK 0x00000002
-#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_ITCH1_RD_INTR_SHIFT 1
-#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_ITCH1_RD_INTR_DEFAULT 0x00000001
-
-/* HIF_INTR2 :: CPU_MASK_CLEAR :: HIF_RGR2_BRIDGE_INTR [00:00] */
-#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_HIF_RGR2_BRIDGE_INTR_MASK 0x00000001
-#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_HIF_RGR2_BRIDGE_INTR_SHIFT 0
-#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_HIF_RGR2_BRIDGE_INTR_DEFAULT 0x00000001
-
-/***************************************************************************
- *PCI_STATUS - PCI interrupt Status Register
- ***************************************************************************/
-/* HIF_INTR2 :: PCI_STATUS :: PCIE_LINKDOWN_INTR [31:31] */
-#define BCHP_HIF_INTR2_PCI_STATUS_PCIE_LINKDOWN_INTR_MASK 0x80000000
-#define BCHP_HIF_INTR2_PCI_STATUS_PCIE_LINKDOWN_INTR_SHIFT 31
-#define BCHP_HIF_INTR2_PCI_STATUS_PCIE_LINKDOWN_INTR_DEFAULT 0x00000000
-
-/* HIF_INTR2 :: PCI_STATUS :: PCIE_LINKUP_INTR [30:30] */
-#define BCHP_HIF_INTR2_PCI_STATUS_PCIE_LINKUP_INTR_MASK 0x40000000
-#define BCHP_HIF_INTR2_PCI_STATUS_PCIE_LINKUP_INTR_SHIFT 30
-#define BCHP_HIF_INTR2_PCI_STATUS_PCIE_LINKUP_INTR_DEFAULT 0x00000000
-
-/* HIF_INTR2 :: PCI_STATUS :: reserved0 [29:28] */
-#define BCHP_HIF_INTR2_PCI_STATUS_reserved0_MASK 0x30000000
-#define BCHP_HIF_INTR2_PCI_STATUS_reserved0_SHIFT 28
-
-/* HIF_INTR2 :: PCI_STATUS :: NAND_CORR_INTR [27:27] */
-#define BCHP_HIF_INTR2_PCI_STATUS_NAND_CORR_INTR_MASK 0x08000000
-#define BCHP_HIF_INTR2_PCI_STATUS_NAND_CORR_INTR_SHIFT 27
-#define BCHP_HIF_INTR2_PCI_STATUS_NAND_CORR_INTR_DEFAULT 0x00000000
-
-/* HIF_INTR2 :: PCI_STATUS :: NAND_UNC_INTR [26:26] */
-#define BCHP_HIF_INTR2_PCI_STATUS_NAND_UNC_INTR_MASK 0x04000000
-#define BCHP_HIF_INTR2_PCI_STATUS_NAND_UNC_INTR_SHIFT 26
-#define BCHP_HIF_INTR2_PCI_STATUS_NAND_UNC_INTR_DEFAULT 0x00000000
-
-/* HIF_INTR2 :: PCI_STATUS :: NAND_RBPIN_INTR [25:25] */
-#define BCHP_HIF_INTR2_PCI_STATUS_NAND_RBPIN_INTR_MASK 0x02000000
-#define BCHP_HIF_INTR2_PCI_STATUS_NAND_RBPIN_INTR_SHIFT 25
-#define BCHP_HIF_INTR2_PCI_STATUS_NAND_RBPIN_INTR_DEFAULT 0x00000000
-
-/* HIF_INTR2 :: PCI_STATUS :: NAND_CTLRDY_INTR [24:24] */
-#define BCHP_HIF_INTR2_PCI_STATUS_NAND_CTLRDY_INTR_MASK 0x01000000
-#define BCHP_HIF_INTR2_PCI_STATUS_NAND_CTLRDY_INTR_SHIFT 24
-#define BCHP_HIF_INTR2_PCI_STATUS_NAND_CTLRDY_INTR_DEFAULT 0x00000000
-
-/* HIF_INTR2 :: PCI_STATUS :: NAND_PGMPG_INTR [23:23] */
-#define BCHP_HIF_INTR2_PCI_STATUS_NAND_PGMPG_INTR_MASK 0x00800000
-#define BCHP_HIF_INTR2_PCI_STATUS_NAND_PGMPG_INTR_SHIFT 23
-#define BCHP_HIF_INTR2_PCI_STATUS_NAND_PGMPG_INTR_DEFAULT 0x00000000
-
-/* HIF_INTR2 :: PCI_STATUS :: NAND_CPYBK_INTR [22:22] */
-#define BCHP_HIF_INTR2_PCI_STATUS_NAND_CPYBK_INTR_MASK 0x00400000
-#define BCHP_HIF_INTR2_PCI_STATUS_NAND_CPYBK_INTR_SHIFT 22
-#define BCHP_HIF_INTR2_PCI_STATUS_NAND_CPYBK_INTR_DEFAULT 0x00000000
-
-/* HIF_INTR2 :: PCI_STATUS :: NAND_BLKERA_INTR [21:21] */
-#define BCHP_HIF_INTR2_PCI_STATUS_NAND_BLKERA_INTR_MASK 0x00200000
-#define BCHP_HIF_INTR2_PCI_STATUS_NAND_BLKERA_INTR_SHIFT 21
-#define BCHP_HIF_INTR2_PCI_STATUS_NAND_BLKERA_INTR_DEFAULT 0x00000000
-
-/* HIF_INTR2 :: PCI_STATUS :: NAND_NP_READ_INTR [20:20] */
-#define BCHP_HIF_INTR2_PCI_STATUS_NAND_NP_READ_INTR_MASK 0x00100000
-#define BCHP_HIF_INTR2_PCI_STATUS_NAND_NP_READ_INTR_SHIFT 20
-#define BCHP_HIF_INTR2_PCI_STATUS_NAND_NP_READ_INTR_DEFAULT 0x00000000
-
-/* HIF_INTR2 :: PCI_STATUS :: reserved1 [19:18] */
-#define BCHP_HIF_INTR2_PCI_STATUS_reserved1_MASK 0x000c0000
-#define BCHP_HIF_INTR2_PCI_STATUS_reserved1_SHIFT 18
-
-/* HIF_INTR2 :: PCI_STATUS :: EBI_TIMEOUT_INTR [17:17] */
-#define BCHP_HIF_INTR2_PCI_STATUS_EBI_TIMEOUT_INTR_MASK 0x00020000
-#define BCHP_HIF_INTR2_PCI_STATUS_EBI_TIMEOUT_INTR_SHIFT 17
-#define BCHP_HIF_INTR2_PCI_STATUS_EBI_TIMEOUT_INTR_DEFAULT 0x00000000
-
-/* HIF_INTR2 :: PCI_STATUS :: EBI_TEA_INTR [16:16] */
-#define BCHP_HIF_INTR2_PCI_STATUS_EBI_TEA_INTR_MASK 0x00010000
-#define BCHP_HIF_INTR2_PCI_STATUS_EBI_TEA_INTR_SHIFT 16
-#define BCHP_HIF_INTR2_PCI_STATUS_EBI_TEA_INTR_DEFAULT 0x00000000
-
-/* HIF_INTR2 :: PCI_STATUS :: ITCH0_RD_INTR [15:15] */
-#define BCHP_HIF_INTR2_PCI_STATUS_ITCH0_RD_INTR_MASK 0x00008000
-#define BCHP_HIF_INTR2_PCI_STATUS_ITCH0_RD_INTR_SHIFT 15
-#define BCHP_HIF_INTR2_PCI_STATUS_ITCH0_RD_INTR_DEFAULT 0x00000000
-
-/* HIF_INTR2 :: PCI_STATUS :: reserved2 [14:14] */
-#define BCHP_HIF_INTR2_PCI_STATUS_reserved2_MASK 0x00004000
-#define BCHP_HIF_INTR2_PCI_STATUS_reserved2_SHIFT 14
-
-/* HIF_INTR2 :: PCI_STATUS :: PCIE_RG_BRIDGE_INTR [13:13] */
-#define BCHP_HIF_INTR2_PCI_STATUS_PCIE_RG_BRIDGE_INTR_MASK 0x00002000
-#define BCHP_HIF_INTR2_PCI_STATUS_PCIE_RG_BRIDGE_INTR_SHIFT 13
-#define BCHP_HIF_INTR2_PCI_STATUS_PCIE_RG_BRIDGE_INTR_DEFAULT 0x00000000
-
-/* HIF_INTR2 :: PCI_STATUS :: PCIE_RGR_BRIDGE_INTR [12:12] */
-#define BCHP_HIF_INTR2_PCI_STATUS_PCIE_RGR_BRIDGE_INTR_MASK 0x00001000
-#define BCHP_HIF_INTR2_PCI_STATUS_PCIE_RGR_BRIDGE_INTR_SHIFT 12
-#define BCHP_HIF_INTR2_PCI_STATUS_PCIE_RGR_BRIDGE_INTR_DEFAULT 0x00000000
-
-/* HIF_INTR2 :: PCI_STATUS :: reserved3 [11:06] */
-#define BCHP_HIF_INTR2_PCI_STATUS_reserved3_MASK 0x00000fc0
-#define BCHP_HIF_INTR2_PCI_STATUS_reserved3_SHIFT 6
-
-/* HIF_INTR2 :: PCI_STATUS :: FLASH_DMA_ERR_INTR [05:05] */
-#define BCHP_HIF_INTR2_PCI_STATUS_FLASH_DMA_ERR_INTR_MASK 0x00000020
-#define BCHP_HIF_INTR2_PCI_STATUS_FLASH_DMA_ERR_INTR_SHIFT 5
-#define BCHP_HIF_INTR2_PCI_STATUS_FLASH_DMA_ERR_INTR_DEFAULT 0x00000000
-
-/* HIF_INTR2 :: PCI_STATUS :: FLASH_DMA_DONE_INTR [04:04] */
-#define BCHP_HIF_INTR2_PCI_STATUS_FLASH_DMA_DONE_INTR_MASK 0x00000010
-#define BCHP_HIF_INTR2_PCI_STATUS_FLASH_DMA_DONE_INTR_SHIFT 4
-#define BCHP_HIF_INTR2_PCI_STATUS_FLASH_DMA_DONE_INTR_DEFAULT 0x00000000
-
-/* HIF_INTR2 :: PCI_STATUS :: WEBHIF_WD_TIMEOUT_INTR [03:03] */
-#define BCHP_HIF_INTR2_PCI_STATUS_WEBHIF_WD_TIMEOUT_INTR_MASK 0x00000008
-#define BCHP_HIF_INTR2_PCI_STATUS_WEBHIF_WD_TIMEOUT_INTR_SHIFT 3
-#define BCHP_HIF_INTR2_PCI_STATUS_WEBHIF_WD_TIMEOUT_INTR_DEFAULT 0x00000000
-
-/* HIF_INTR2 :: PCI_STATUS :: reserved4 [02:02] */
-#define BCHP_HIF_INTR2_PCI_STATUS_reserved4_MASK 0x00000004
-#define BCHP_HIF_INTR2_PCI_STATUS_reserved4_SHIFT 2
-
-/* HIF_INTR2 :: PCI_STATUS :: ITCH1_RD_INTR [01:01] */
-#define BCHP_HIF_INTR2_PCI_STATUS_ITCH1_RD_INTR_MASK 0x00000002
-#define BCHP_HIF_INTR2_PCI_STATUS_ITCH1_RD_INTR_SHIFT 1
-#define BCHP_HIF_INTR2_PCI_STATUS_ITCH1_RD_INTR_DEFAULT 0x00000000
-
-/* HIF_INTR2 :: PCI_STATUS :: HIF_RGR2_BRIDGE_INTR [00:00] */
-#define BCHP_HIF_INTR2_PCI_STATUS_HIF_RGR2_BRIDGE_INTR_MASK 0x00000001
-#define BCHP_HIF_INTR2_PCI_STATUS_HIF_RGR2_BRIDGE_INTR_SHIFT 0
-#define BCHP_HIF_INTR2_PCI_STATUS_HIF_RGR2_BRIDGE_INTR_DEFAULT 0x00000000
-
-/***************************************************************************
- *PCI_SET - PCI interrupt Set Register
- ***************************************************************************/
-/* HIF_INTR2 :: PCI_SET :: PCIE_LINKDOWN_INTR [31:31] */
-#define BCHP_HIF_INTR2_PCI_SET_PCIE_LINKDOWN_INTR_MASK 0x80000000
-#define BCHP_HIF_INTR2_PCI_SET_PCIE_LINKDOWN_INTR_SHIFT 31
-#define BCHP_HIF_INTR2_PCI_SET_PCIE_LINKDOWN_INTR_DEFAULT 0x00000000
-
-/* HIF_INTR2 :: PCI_SET :: PCIE_LINKUP_INTR [30:30] */
-#define BCHP_HIF_INTR2_PCI_SET_PCIE_LINKUP_INTR_MASK 0x40000000
-#define BCHP_HIF_INTR2_PCI_SET_PCIE_LINKUP_INTR_SHIFT 30
-#define BCHP_HIF_INTR2_PCI_SET_PCIE_LINKUP_INTR_DEFAULT 0x00000000
-
-/* HIF_INTR2 :: PCI_SET :: reserved0 [29:28] */
-#define BCHP_HIF_INTR2_PCI_SET_reserved0_MASK 0x30000000
-#define BCHP_HIF_INTR2_PCI_SET_reserved0_SHIFT 28
-
-/* HIF_INTR2 :: PCI_SET :: NAND_CORR_INTR [27:27] */
-#define BCHP_HIF_INTR2_PCI_SET_NAND_CORR_INTR_MASK 0x08000000
-#define BCHP_HIF_INTR2_PCI_SET_NAND_CORR_INTR_SHIFT 27
-#define BCHP_HIF_INTR2_PCI_SET_NAND_CORR_INTR_DEFAULT 0x00000000
-
-/* HIF_INTR2 :: PCI_SET :: NAND_UNC_INTR [26:26] */
-#define BCHP_HIF_INTR2_PCI_SET_NAND_UNC_INTR_MASK 0x04000000
-#define BCHP_HIF_INTR2_PCI_SET_NAND_UNC_INTR_SHIFT 26
-#define BCHP_HIF_INTR2_PCI_SET_NAND_UNC_INTR_DEFAULT 0x00000000
-
-/* HIF_INTR2 :: PCI_SET :: NAND_RBPIN_INTR [25:25] */
-#define BCHP_HIF_INTR2_PCI_SET_NAND_RBPIN_INTR_MASK 0x02000000
-#define BCHP_HIF_INTR2_PCI_SET_NAND_RBPIN_INTR_SHIFT 25
-#define BCHP_HIF_INTR2_PCI_SET_NAND_RBPIN_INTR_DEFAULT 0x00000000
-
-/* HIF_INTR2 :: PCI_SET :: NAND_CTLRDY_INTR [24:24] */
-#define BCHP_HIF_INTR2_PCI_SET_NAND_CTLRDY_INTR_MASK 0x01000000
-#define BCHP_HIF_INTR2_PCI_SET_NAND_CTLRDY_INTR_SHIFT 24
-#define BCHP_HIF_INTR2_PCI_SET_NAND_CTLRDY_INTR_DEFAULT 0x00000000
-
-/* HIF_INTR2 :: PCI_SET :: NAND_PGMPG_INTR [23:23] */
-#define BCHP_HIF_INTR2_PCI_SET_NAND_PGMPG_INTR_MASK 0x00800000
-#define BCHP_HIF_INTR2_PCI_SET_NAND_PGMPG_INTR_SHIFT 23
-#define BCHP_HIF_INTR2_PCI_SET_NAND_PGMPG_INTR_DEFAULT 0x00000000
-
-/* HIF_INTR2 :: PCI_SET :: NAND_CPYBK_INTR [22:22] */
-#define BCHP_HIF_INTR2_PCI_SET_NAND_CPYBK_INTR_MASK 0x00400000
-#define BCHP_HIF_INTR2_PCI_SET_NAND_CPYBK_INTR_SHIFT 22
-#define BCHP_HIF_INTR2_PCI_SET_NAND_CPYBK_INTR_DEFAULT 0x00000000
-
-/* HIF_INTR2 :: PCI_SET :: NAND_BLKERA_INTR [21:21] */
-#define BCHP_HIF_INTR2_PCI_SET_NAND_BLKERA_INTR_MASK 0x00200000
-#define BCHP_HIF_INTR2_PCI_SET_NAND_BLKERA_INTR_SHIFT 21
-#define BCHP_HIF_INTR2_PCI_SET_NAND_BLKERA_INTR_DEFAULT 0x00000000
-
-/* HIF_INTR2 :: PCI_SET :: NAND_NP_READ_INTR [20:20] */
-#define BCHP_HIF_INTR2_PCI_SET_NAND_NP_READ_INTR_MASK 0x00100000
-#define BCHP_HIF_INTR2_PCI_SET_NAND_NP_READ_INTR_SHIFT 20
-#define BCHP_HIF_INTR2_PCI_SET_NAND_NP_READ_INTR_DEFAULT 0x00000000
-
-/* HIF_INTR2 :: PCI_SET :: reserved1 [19:18] */
-#define BCHP_HIF_INTR2_PCI_SET_reserved1_MASK 0x000c0000
-#define BCHP_HIF_INTR2_PCI_SET_reserved1_SHIFT 18
-
-/* HIF_INTR2 :: PCI_SET :: EBI_TIMEOUT_INTR [17:17] */
-#define BCHP_HIF_INTR2_PCI_SET_EBI_TIMEOUT_INTR_MASK 0x00020000
-#define BCHP_HIF_INTR2_PCI_SET_EBI_TIMEOUT_INTR_SHIFT 17
-#define BCHP_HIF_INTR2_PCI_SET_EBI_TIMEOUT_INTR_DEFAULT 0x00000000
-
-/* HIF_INTR2 :: PCI_SET :: EBI_TEA_INTR [16:16] */
-#define BCHP_HIF_INTR2_PCI_SET_EBI_TEA_INTR_MASK 0x00010000
-#define BCHP_HIF_INTR2_PCI_SET_EBI_TEA_INTR_SHIFT 16
-#define BCHP_HIF_INTR2_PCI_SET_EBI_TEA_INTR_DEFAULT 0x00000000
-
-/* HIF_INTR2 :: PCI_SET :: ITCH0_RD_INTR [15:15] */
-#define BCHP_HIF_INTR2_PCI_SET_ITCH0_RD_INTR_MASK 0x00008000
-#define BCHP_HIF_INTR2_PCI_SET_ITCH0_RD_INTR_SHIFT 15
-#define BCHP_HIF_INTR2_PCI_SET_ITCH0_RD_INTR_DEFAULT 0x00000000
-
-/* HIF_INTR2 :: PCI_SET :: reserved2 [14:14] */
-#define BCHP_HIF_INTR2_PCI_SET_reserved2_MASK 0x00004000
-#define BCHP_HIF_INTR2_PCI_SET_reserved2_SHIFT 14
-
-/* HIF_INTR2 :: PCI_SET :: PCIE_RG_BRIDGE_INTR [13:13] */
-#define BCHP_HIF_INTR2_PCI_SET_PCIE_RG_BRIDGE_INTR_MASK 0x00002000
-#define BCHP_HIF_INTR2_PCI_SET_PCIE_RG_BRIDGE_INTR_SHIFT 13
-#define BCHP_HIF_INTR2_PCI_SET_PCIE_RG_BRIDGE_INTR_DEFAULT 0x00000000
-
-/* HIF_INTR2 :: PCI_SET :: PCIE_RGR_BRIDGE_INTR [12:12] */
-#define BCHP_HIF_INTR2_PCI_SET_PCIE_RGR_BRIDGE_INTR_MASK 0x00001000
-#define BCHP_HIF_INTR2_PCI_SET_PCIE_RGR_BRIDGE_INTR_SHIFT 12
-#define BCHP_HIF_INTR2_PCI_SET_PCIE_RGR_BRIDGE_INTR_DEFAULT 0x00000000
-
-/* HIF_INTR2 :: PCI_SET :: reserved3 [11:06] */
-#define BCHP_HIF_INTR2_PCI_SET_reserved3_MASK 0x00000fc0
-#define BCHP_HIF_INTR2_PCI_SET_reserved3_SHIFT 6
-
-/* HIF_INTR2 :: PCI_SET :: FLASH_DMA_ERR_INTR [05:05] */
-#define BCHP_HIF_INTR2_PCI_SET_FLASH_DMA_ERR_INTR_MASK 0x00000020
-#define BCHP_HIF_INTR2_PCI_SET_FLASH_DMA_ERR_INTR_SHIFT 5
-#define BCHP_HIF_INTR2_PCI_SET_FLASH_DMA_ERR_INTR_DEFAULT 0x00000000
-
-/* HIF_INTR2 :: PCI_SET :: FLASH_DMA_DONE_INTR [04:04] */
-#define BCHP_HIF_INTR2_PCI_SET_FLASH_DMA_DONE_INTR_MASK 0x00000010
-#define BCHP_HIF_INTR2_PCI_SET_FLASH_DMA_DONE_INTR_SHIFT 4
-#define BCHP_HIF_INTR2_PCI_SET_FLASH_DMA_DONE_INTR_DEFAULT 0x00000000
-
-/* HIF_INTR2 :: PCI_SET :: WEBHIF_WD_TIMEOUT_INTR [03:03] */
-#define BCHP_HIF_INTR2_PCI_SET_WEBHIF_WD_TIMEOUT_INTR_MASK 0x00000008
-#define BCHP_HIF_INTR2_PCI_SET_WEBHIF_WD_TIMEOUT_INTR_SHIFT 3
-#define BCHP_HIF_INTR2_PCI_SET_WEBHIF_WD_TIMEOUT_INTR_DEFAULT 0x00000000
-
-/* HIF_INTR2 :: PCI_SET :: reserved4 [02:02] */
-#define BCHP_HIF_INTR2_PCI_SET_reserved4_MASK 0x00000004
-#define BCHP_HIF_INTR2_PCI_SET_reserved4_SHIFT 2
-
-/* HIF_INTR2 :: PCI_SET :: ITCH1_RD_INTR [01:01] */
-#define BCHP_HIF_INTR2_PCI_SET_ITCH1_RD_INTR_MASK 0x00000002
-#define BCHP_HIF_INTR2_PCI_SET_ITCH1_RD_INTR_SHIFT 1
-#define BCHP_HIF_INTR2_PCI_SET_ITCH1_RD_INTR_DEFAULT 0x00000000
-
-/* HIF_INTR2 :: PCI_SET :: HIF_RGR2_BRIDGE_INTR [00:00] */
-#define BCHP_HIF_INTR2_PCI_SET_HIF_RGR2_BRIDGE_INTR_MASK 0x00000001
-#define BCHP_HIF_INTR2_PCI_SET_HIF_RGR2_BRIDGE_INTR_SHIFT 0
-#define BCHP_HIF_INTR2_PCI_SET_HIF_RGR2_BRIDGE_INTR_DEFAULT 0x00000000
-
-/***************************************************************************
- *PCI_CLEAR - PCI interrupt Clear Register
- ***************************************************************************/
-/* HIF_INTR2 :: PCI_CLEAR :: PCIE_LINKDOWN_INTR [31:31] */
-#define BCHP_HIF_INTR2_PCI_CLEAR_PCIE_LINKDOWN_INTR_MASK 0x80000000
-#define BCHP_HIF_INTR2_PCI_CLEAR_PCIE_LINKDOWN_INTR_SHIFT 31
-#define BCHP_HIF_INTR2_PCI_CLEAR_PCIE_LINKDOWN_INTR_DEFAULT 0x00000000
-
-/* HIF_INTR2 :: PCI_CLEAR :: PCIE_LINKUP_INTR [30:30] */
-#define BCHP_HIF_INTR2_PCI_CLEAR_PCIE_LINKUP_INTR_MASK 0x40000000
-#define BCHP_HIF_INTR2_PCI_CLEAR_PCIE_LINKUP_INTR_SHIFT 30
-#define BCHP_HIF_INTR2_PCI_CLEAR_PCIE_LINKUP_INTR_DEFAULT 0x00000000
-
-/* HIF_INTR2 :: PCI_CLEAR :: reserved0 [29:28] */
-#define BCHP_HIF_INTR2_PCI_CLEAR_reserved0_MASK 0x30000000
-#define BCHP_HIF_INTR2_PCI_CLEAR_reserved0_SHIFT 28
-
-/* HIF_INTR2 :: PCI_CLEAR :: NAND_CORR_INTR [27:27] */
-#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_CORR_INTR_MASK 0x08000000
-#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_CORR_INTR_SHIFT 27
-#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_CORR_INTR_DEFAULT 0x00000000
-
-/* HIF_INTR2 :: PCI_CLEAR :: NAND_UNC_INTR [26:26] */
-#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_UNC_INTR_MASK 0x04000000
-#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_UNC_INTR_SHIFT 26
-#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_UNC_INTR_DEFAULT 0x00000000
-
-/* HIF_INTR2 :: PCI_CLEAR :: NAND_RBPIN_INTR [25:25] */
-#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_RBPIN_INTR_MASK 0x02000000
-#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_RBPIN_INTR_SHIFT 25
-#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_RBPIN_INTR_DEFAULT 0x00000000
-
-/* HIF_INTR2 :: PCI_CLEAR :: NAND_CTLRDY_INTR [24:24] */
-#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_CTLRDY_INTR_MASK 0x01000000
-#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_CTLRDY_INTR_SHIFT 24
-#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_CTLRDY_INTR_DEFAULT 0x00000000
-
-/* HIF_INTR2 :: PCI_CLEAR :: NAND_PGMPG_INTR [23:23] */
-#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_PGMPG_INTR_MASK 0x00800000
-#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_PGMPG_INTR_SHIFT 23
-#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_PGMPG_INTR_DEFAULT 0x00000000
-
-/* HIF_INTR2 :: PCI_CLEAR :: NAND_CPYBK_INTR [22:22] */
-#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_CPYBK_INTR_MASK 0x00400000
-#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_CPYBK_INTR_SHIFT 22
-#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_CPYBK_INTR_DEFAULT 0x00000000
-
-/* HIF_INTR2 :: PCI_CLEAR :: NAND_BLKERA_INTR [21:21] */
-#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_BLKERA_INTR_MASK 0x00200000
-#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_BLKERA_INTR_SHIFT 21
-#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_BLKERA_INTR_DEFAULT 0x00000000
-
-/* HIF_INTR2 :: PCI_CLEAR :: NAND_NP_READ_INTR [20:20] */
-#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_NP_READ_INTR_MASK 0x00100000
-#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_NP_READ_INTR_SHIFT 20
-#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_NP_READ_INTR_DEFAULT 0x00000000
-
-/* HIF_INTR2 :: PCI_CLEAR :: reserved1 [19:18] */
-#define BCHP_HIF_INTR2_PCI_CLEAR_reserved1_MASK 0x000c0000
-#define BCHP_HIF_INTR2_PCI_CLEAR_reserved1_SHIFT 18
-
-/* HIF_INTR2 :: PCI_CLEAR :: EBI_TIMEOUT_INTR [17:17] */
-#define BCHP_HIF_INTR2_PCI_CLEAR_EBI_TIMEOUT_INTR_MASK 0x00020000
-#define BCHP_HIF_INTR2_PCI_CLEAR_EBI_TIMEOUT_INTR_SHIFT 17
-#define BCHP_HIF_INTR2_PCI_CLEAR_EBI_TIMEOUT_INTR_DEFAULT 0x00000000
-
-/* HIF_INTR2 :: PCI_CLEAR :: EBI_TEA_INTR [16:16] */
-#define BCHP_HIF_INTR2_PCI_CLEAR_EBI_TEA_INTR_MASK 0x00010000
-#define BCHP_HIF_INTR2_PCI_CLEAR_EBI_TEA_INTR_SHIFT 16
-#define BCHP_HIF_INTR2_PCI_CLEAR_EBI_TEA_INTR_DEFAULT 0x00000000
-
-/* HIF_INTR2 :: PCI_CLEAR :: ITCH0_RD_INTR [15:15] */
-#define BCHP_HIF_INTR2_PCI_CLEAR_ITCH0_RD_INTR_MASK 0x00008000
-#define BCHP_HIF_INTR2_PCI_CLEAR_ITCH0_RD_INTR_SHIFT 15
-#define BCHP_HIF_INTR2_PCI_CLEAR_ITCH0_RD_INTR_DEFAULT 0x00000000
-
-/* HIF_INTR2 :: PCI_CLEAR :: reserved2 [14:14] */
-#define BCHP_HIF_INTR2_PCI_CLEAR_reserved2_MASK 0x00004000
-#define BCHP_HIF_INTR2_PCI_CLEAR_reserved2_SHIFT 14
-
-/* HIF_INTR2 :: PCI_CLEAR :: PCIE_RG_BRIDGE_INTR [13:13] */
-#define BCHP_HIF_INTR2_PCI_CLEAR_PCIE_RG_BRIDGE_INTR_MASK 0x00002000
-#define BCHP_HIF_INTR2_PCI_CLEAR_PCIE_RG_BRIDGE_INTR_SHIFT 13
-#define BCHP_HIF_INTR2_PCI_CLEAR_PCIE_RG_BRIDGE_INTR_DEFAULT 0x00000000
-
-/* HIF_INTR2 :: PCI_CLEAR :: PCIE_RGR_BRIDGE_INTR [12:12] */
-#define BCHP_HIF_INTR2_PCI_CLEAR_PCIE_RGR_BRIDGE_INTR_MASK 0x00001000
-#define BCHP_HIF_INTR2_PCI_CLEAR_PCIE_RGR_BRIDGE_INTR_SHIFT 12
-#define BCHP_HIF_INTR2_PCI_CLEAR_PCIE_RGR_BRIDGE_INTR_DEFAULT 0x00000000
-
-/* HIF_INTR2 :: PCI_CLEAR :: reserved3 [11:06] */
-#define BCHP_HIF_INTR2_PCI_CLEAR_reserved3_MASK 0x00000fc0
-#define BCHP_HIF_INTR2_PCI_CLEAR_reserved3_SHIFT 6
-
-/* HIF_INTR2 :: PCI_CLEAR :: FLASH_DMA_ERR_INTR [05:05] */
-#define BCHP_HIF_INTR2_PCI_CLEAR_FLASH_DMA_ERR_INTR_MASK 0x00000020
-#define BCHP_HIF_INTR2_PCI_CLEAR_FLASH_DMA_ERR_INTR_SHIFT 5
-#define BCHP_HIF_INTR2_PCI_CLEAR_FLASH_DMA_ERR_INTR_DEFAULT 0x00000000
-
-/* HIF_INTR2 :: PCI_CLEAR :: FLASH_DMA_DONE_INTR [04:04] */
-#define BCHP_HIF_INTR2_PCI_CLEAR_FLASH_DMA_DONE_INTR_MASK 0x00000010
-#define BCHP_HIF_INTR2_PCI_CLEAR_FLASH_DMA_DONE_INTR_SHIFT 4
-#define BCHP_HIF_INTR2_PCI_CLEAR_FLASH_DMA_DONE_INTR_DEFAULT 0x00000000
-
-/* HIF_INTR2 :: PCI_CLEAR :: WEBHIF_WD_TIMEOUT_INTR [03:03] */
-#define BCHP_HIF_INTR2_PCI_CLEAR_WEBHIF_WD_TIMEOUT_INTR_MASK 0x00000008
-#define BCHP_HIF_INTR2_PCI_CLEAR_WEBHIF_WD_TIMEOUT_INTR_SHIFT 3
-#define BCHP_HIF_INTR2_PCI_CLEAR_WEBHIF_WD_TIMEOUT_INTR_DEFAULT 0x00000000
-
-/* HIF_INTR2 :: PCI_CLEAR :: reserved4 [02:02] */
-#define BCHP_HIF_INTR2_PCI_CLEAR_reserved4_MASK 0x00000004
-#define BCHP_HIF_INTR2_PCI_CLEAR_reserved4_SHIFT 2
-
-/* HIF_INTR2 :: PCI_CLEAR :: ITCH1_RD_INTR [01:01] */
-#define BCHP_HIF_INTR2_PCI_CLEAR_ITCH1_RD_INTR_MASK 0x00000002
-#define BCHP_HIF_INTR2_PCI_CLEAR_ITCH1_RD_INTR_SHIFT 1
-#define BCHP_HIF_INTR2_PCI_CLEAR_ITCH1_RD_INTR_DEFAULT 0x00000000
-
-/* HIF_INTR2 :: PCI_CLEAR :: HIF_RGR2_BRIDGE_INTR [00:00] */
-#define BCHP_HIF_INTR2_PCI_CLEAR_HIF_RGR2_BRIDGE_INTR_MASK 0x00000001
-#define BCHP_HIF_INTR2_PCI_CLEAR_HIF_RGR2_BRIDGE_INTR_SHIFT 0
-#define BCHP_HIF_INTR2_PCI_CLEAR_HIF_RGR2_BRIDGE_INTR_DEFAULT 0x00000000
-
-/***************************************************************************
- *PCI_MASK_STATUS - PCI interrupt Mask Status Register
- ***************************************************************************/
-/* HIF_INTR2 :: PCI_MASK_STATUS :: PCIE_LINKDOWN_INTR [31:31] */
-#define BCHP_HIF_INTR2_PCI_MASK_STATUS_PCIE_LINKDOWN_INTR_MASK 0x80000000
-#define BCHP_HIF_INTR2_PCI_MASK_STATUS_PCIE_LINKDOWN_INTR_SHIFT 31
-#define BCHP_HIF_INTR2_PCI_MASK_STATUS_PCIE_LINKDOWN_INTR_DEFAULT 0x00000000
-
-/* HIF_INTR2 :: PCI_MASK_STATUS :: PCIE_LINKUP_INTR [30:30] */
-#define BCHP_HIF_INTR2_PCI_MASK_STATUS_PCIE_LINKUP_INTR_MASK 0x40000000
-#define BCHP_HIF_INTR2_PCI_MASK_STATUS_PCIE_LINKUP_INTR_SHIFT 30
-#define BCHP_HIF_INTR2_PCI_MASK_STATUS_PCIE_LINKUP_INTR_DEFAULT 0x00000000
-
-/* HIF_INTR2 :: PCI_MASK_STATUS :: reserved0 [29:28] */
-#define BCHP_HIF_INTR2_PCI_MASK_STATUS_reserved0_MASK 0x30000000
-#define BCHP_HIF_INTR2_PCI_MASK_STATUS_reserved0_SHIFT 28
-
-/* HIF_INTR2 :: PCI_MASK_STATUS :: NAND_CORR_INTR [27:27] */
-#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_CORR_INTR_MASK 0x08000000
-#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_CORR_INTR_SHIFT 27
-#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_CORR_INTR_DEFAULT 0x00000001
-
-/* HIF_INTR2 :: PCI_MASK_STATUS :: NAND_UNC_INTR [26:26] */
-#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_UNC_INTR_MASK 0x04000000
-#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_UNC_INTR_SHIFT 26
-#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_UNC_INTR_DEFAULT 0x00000001
-
-/* HIF_INTR2 :: PCI_MASK_STATUS :: NAND_RBPIN_INTR [25:25] */
-#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_RBPIN_INTR_MASK 0x02000000
-#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_RBPIN_INTR_SHIFT 25
-#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_RBPIN_INTR_DEFAULT 0x00000001
-
-/* HIF_INTR2 :: PCI_MASK_STATUS :: NAND_CTLRDY_INTR [24:24] */
-#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_CTLRDY_INTR_MASK 0x01000000
-#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_CTLRDY_INTR_SHIFT 24
-#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_CTLRDY_INTR_DEFAULT 0x00000001
-
-/* HIF_INTR2 :: PCI_MASK_STATUS :: NAND_PGMPG_INTR [23:23] */
-#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_PGMPG_INTR_MASK 0x00800000
-#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_PGMPG_INTR_SHIFT 23
-#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_PGMPG_INTR_DEFAULT 0x00000001
-
-/* HIF_INTR2 :: PCI_MASK_STATUS :: NAND_CPYBK_INTR [22:22] */
-#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_CPYBK_INTR_MASK 0x00400000
-#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_CPYBK_INTR_SHIFT 22
-#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_CPYBK_INTR_DEFAULT 0x00000001
-
-/* HIF_INTR2 :: PCI_MASK_STATUS :: NAND_BLKERA_INTR [21:21] */
-#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_BLKERA_INTR_MASK 0x00200000
-#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_BLKERA_INTR_SHIFT 21
-#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_BLKERA_INTR_DEFAULT 0x00000001
-
-/* HIF_INTR2 :: PCI_MASK_STATUS :: NAND_NP_READ_INTR [20:20] */
-#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_NP_READ_INTR_MASK 0x00100000
-#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_NP_READ_INTR_SHIFT 20
-#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_NP_READ_INTR_DEFAULT 0x00000001
-
-/* HIF_INTR2 :: PCI_MASK_STATUS :: reserved1 [19:18] */
-#define BCHP_HIF_INTR2_PCI_MASK_STATUS_reserved1_MASK 0x000c0000
-#define BCHP_HIF_INTR2_PCI_MASK_STATUS_reserved1_SHIFT 18
-
-/* HIF_INTR2 :: PCI_MASK_STATUS :: EBI_TIMEOUT_INTR [17:17] */
-#define BCHP_HIF_INTR2_PCI_MASK_STATUS_EBI_TIMEOUT_INTR_MASK 0x00020000
-#define BCHP_HIF_INTR2_PCI_MASK_STATUS_EBI_TIMEOUT_INTR_SHIFT 17
-#define BCHP_HIF_INTR2_PCI_MASK_STATUS_EBI_TIMEOUT_INTR_DEFAULT 0x00000001
-
-/* HIF_INTR2 :: PCI_MASK_STATUS :: EBI_TEA_INTR [16:16] */
-#define BCHP_HIF_INTR2_PCI_MASK_STATUS_EBI_TEA_INTR_MASK 0x00010000
-#define BCHP_HIF_INTR2_PCI_MASK_STATUS_EBI_TEA_INTR_SHIFT 16
-#define BCHP_HIF_INTR2_PCI_MASK_STATUS_EBI_TEA_INTR_DEFAULT 0x00000001
-
-/* HIF_INTR2 :: PCI_MASK_STATUS :: ITCH0_RD_INTR [15:15] */
-#define BCHP_HIF_INTR2_PCI_MASK_STATUS_ITCH0_RD_INTR_MASK 0x00008000
-#define BCHP_HIF_INTR2_PCI_MASK_STATUS_ITCH0_RD_INTR_SHIFT 15
-#define BCHP_HIF_INTR2_PCI_MASK_STATUS_ITCH0_RD_INTR_DEFAULT 0x00000001
-
-/* HIF_INTR2 :: PCI_MASK_STATUS :: reserved2 [14:14] */
-#define BCHP_HIF_INTR2_PCI_MASK_STATUS_reserved2_MASK 0x00004000
-#define BCHP_HIF_INTR2_PCI_MASK_STATUS_reserved2_SHIFT 14
-
-/* HIF_INTR2 :: PCI_MASK_STATUS :: PCIE_RG_BRIDGE_INTR [13:13] */
-#define BCHP_HIF_INTR2_PCI_MASK_STATUS_PCIE_RG_BRIDGE_INTR_MASK 0x00002000
-#define BCHP_HIF_INTR2_PCI_MASK_STATUS_PCIE_RG_BRIDGE_INTR_SHIFT 13
-#define BCHP_HIF_INTR2_PCI_MASK_STATUS_PCIE_RG_BRIDGE_INTR_DEFAULT 0x00000001
-
-/* HIF_INTR2 :: PCI_MASK_STATUS :: PCIE_RGR_BRIDGE_INTR [12:12] */
-#define BCHP_HIF_INTR2_PCI_MASK_STATUS_PCIE_RGR_BRIDGE_INTR_MASK 0x00001000
-#define BCHP_HIF_INTR2_PCI_MASK_STATUS_PCIE_RGR_BRIDGE_INTR_SHIFT 12
-#define BCHP_HIF_INTR2_PCI_MASK_STATUS_PCIE_RGR_BRIDGE_INTR_DEFAULT 0x00000001
-
-/* HIF_INTR2 :: PCI_MASK_STATUS :: reserved3 [11:06] */
-#define BCHP_HIF_INTR2_PCI_MASK_STATUS_reserved3_MASK 0x00000fc0
-#define BCHP_HIF_INTR2_PCI_MASK_STATUS_reserved3_SHIFT 6
-
-/* HIF_INTR2 :: PCI_MASK_STATUS :: FLASH_DMA_ERR_INTR [05:05] */
-#define BCHP_HIF_INTR2_PCI_MASK_STATUS_FLASH_DMA_ERR_INTR_MASK 0x00000020
-#define BCHP_HIF_INTR2_PCI_MASK_STATUS_FLASH_DMA_ERR_INTR_SHIFT 5
-#define BCHP_HIF_INTR2_PCI_MASK_STATUS_FLASH_DMA_ERR_INTR_DEFAULT 0x00000000
-
-/* HIF_INTR2 :: PCI_MASK_STATUS :: FLASH_DMA_DONE_INTR [04:04] */
-#define BCHP_HIF_INTR2_PCI_MASK_STATUS_FLASH_DMA_DONE_INTR_MASK 0x00000010
-#define BCHP_HIF_INTR2_PCI_MASK_STATUS_FLASH_DMA_DONE_INTR_SHIFT 4
-#define BCHP_HIF_INTR2_PCI_MASK_STATUS_FLASH_DMA_DONE_INTR_DEFAULT 0x00000000
-
-/* HIF_INTR2 :: PCI_MASK_STATUS :: WEBHIF_WD_TIMEOUT_INTR [03:03] */
-#define BCHP_HIF_INTR2_PCI_MASK_STATUS_WEBHIF_WD_TIMEOUT_INTR_MASK 0x00000008
-#define BCHP_HIF_INTR2_PCI_MASK_STATUS_WEBHIF_WD_TIMEOUT_INTR_SHIFT 3
-#define BCHP_HIF_INTR2_PCI_MASK_STATUS_WEBHIF_WD_TIMEOUT_INTR_DEFAULT 0x00000000
-
-/* HIF_INTR2 :: PCI_MASK_STATUS :: reserved4 [02:02] */
-#define BCHP_HIF_INTR2_PCI_MASK_STATUS_reserved4_MASK 0x00000004
-#define BCHP_HIF_INTR2_PCI_MASK_STATUS_reserved4_SHIFT 2
-
-/* HIF_INTR2 :: PCI_MASK_STATUS :: ITCH1_RD_INTR [01:01] */
-#define BCHP_HIF_INTR2_PCI_MASK_STATUS_ITCH1_RD_INTR_MASK 0x00000002
-#define BCHP_HIF_INTR2_PCI_MASK_STATUS_ITCH1_RD_INTR_SHIFT 1
-#define BCHP_HIF_INTR2_PCI_MASK_STATUS_ITCH1_RD_INTR_DEFAULT 0x00000001
-
-/* HIF_INTR2 :: PCI_MASK_STATUS :: HIF_RGR2_BRIDGE_INTR [00:00] */
-#define BCHP_HIF_INTR2_PCI_MASK_STATUS_HIF_RGR2_BRIDGE_INTR_MASK 0x00000001
-#define BCHP_HIF_INTR2_PCI_MASK_STATUS_HIF_RGR2_BRIDGE_INTR_SHIFT 0
-#define BCHP_HIF_INTR2_PCI_MASK_STATUS_HIF_RGR2_BRIDGE_INTR_DEFAULT 0x00000001
-
-/***************************************************************************
- *PCI_MASK_SET - PCI interrupt Mask Set Register
- ***************************************************************************/
-/* HIF_INTR2 :: PCI_MASK_SET :: PCIE_LINKDOWN_INTR [31:31] */
-#define BCHP_HIF_INTR2_PCI_MASK_SET_PCIE_LINKDOWN_INTR_MASK 0x80000000
-#define BCHP_HIF_INTR2_PCI_MASK_SET_PCIE_LINKDOWN_INTR_SHIFT 31
-#define BCHP_HIF_INTR2_PCI_MASK_SET_PCIE_LINKDOWN_INTR_DEFAULT 0x00000000
-
-/* HIF_INTR2 :: PCI_MASK_SET :: PCIE_LINKUP_INTR [30:30] */
-#define BCHP_HIF_INTR2_PCI_MASK_SET_PCIE_LINKUP_INTR_MASK 0x40000000
-#define BCHP_HIF_INTR2_PCI_MASK_SET_PCIE_LINKUP_INTR_SHIFT 30
-#define BCHP_HIF_INTR2_PCI_MASK_SET_PCIE_LINKUP_INTR_DEFAULT 0x00000000
-
-/* HIF_INTR2 :: PCI_MASK_SET :: reserved0 [29:28] */
-#define BCHP_HIF_INTR2_PCI_MASK_SET_reserved0_MASK 0x30000000
-#define BCHP_HIF_INTR2_PCI_MASK_SET_reserved0_SHIFT 28
-
-/* HIF_INTR2 :: PCI_MASK_SET :: NAND_CORR_INTR [27:27] */
-#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_CORR_INTR_MASK 0x08000000
-#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_CORR_INTR_SHIFT 27
-#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_CORR_INTR_DEFAULT 0x00000001
-
-/* HIF_INTR2 :: PCI_MASK_SET :: NAND_UNC_INTR [26:26] */
-#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_UNC_INTR_MASK 0x04000000
-#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_UNC_INTR_SHIFT 26
-#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_UNC_INTR_DEFAULT 0x00000001
-
-/* HIF_INTR2 :: PCI_MASK_SET :: NAND_RBPIN_INTR [25:25] */
-#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_RBPIN_INTR_MASK 0x02000000
-#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_RBPIN_INTR_SHIFT 25
-#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_RBPIN_INTR_DEFAULT 0x00000001
-
-/* HIF_INTR2 :: PCI_MASK_SET :: NAND_CTLRDY_INTR [24:24] */
-#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_CTLRDY_INTR_MASK 0x01000000
-#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_CTLRDY_INTR_SHIFT 24
-#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_CTLRDY_INTR_DEFAULT 0x00000001
-
-/* HIF_INTR2 :: PCI_MASK_SET :: NAND_PGMPG_INTR [23:23] */
-#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_PGMPG_INTR_MASK 0x00800000
-#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_PGMPG_INTR_SHIFT 23
-#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_PGMPG_INTR_DEFAULT 0x00000001
-
-/* HIF_INTR2 :: PCI_MASK_SET :: NAND_CPYBK_INTR [22:22] */
-#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_CPYBK_INTR_MASK 0x00400000
-#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_CPYBK_INTR_SHIFT 22
-#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_CPYBK_INTR_DEFAULT 0x00000001
-
-/* HIF_INTR2 :: PCI_MASK_SET :: NAND_BLKERA_INTR [21:21] */
-#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_BLKERA_INTR_MASK 0x00200000
-#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_BLKERA_INTR_SHIFT 21
-#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_BLKERA_INTR_DEFAULT 0x00000001
-
-/* HIF_INTR2 :: PCI_MASK_SET :: NAND_NP_READ_INTR [20:20] */
-#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_NP_READ_INTR_MASK 0x00100000
-#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_NP_READ_INTR_SHIFT 20
-#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_NP_READ_INTR_DEFAULT 0x00000001
-
-/* HIF_INTR2 :: PCI_MASK_SET :: reserved1 [19:18] */
-#define BCHP_HIF_INTR2_PCI_MASK_SET_reserved1_MASK 0x000c0000
-#define BCHP_HIF_INTR2_PCI_MASK_SET_reserved1_SHIFT 18
-
-/* HIF_INTR2 :: PCI_MASK_SET :: EBI_TIMEOUT_INTR [17:17] */
-#define BCHP_HIF_INTR2_PCI_MASK_SET_EBI_TIMEOUT_INTR_MASK 0x00020000
-#define BCHP_HIF_INTR2_PCI_MASK_SET_EBI_TIMEOUT_INTR_SHIFT 17
-#define BCHP_HIF_INTR2_PCI_MASK_SET_EBI_TIMEOUT_INTR_DEFAULT 0x00000001
-
-/* HIF_INTR2 :: PCI_MASK_SET :: EBI_TEA_INTR [16:16] */
-#define BCHP_HIF_INTR2_PCI_MASK_SET_EBI_TEA_INTR_MASK 0x00010000
-#define BCHP_HIF_INTR2_PCI_MASK_SET_EBI_TEA_INTR_SHIFT 16
-#define BCHP_HIF_INTR2_PCI_MASK_SET_EBI_TEA_INTR_DEFAULT 0x00000001
-
-/* HIF_INTR2 :: PCI_MASK_SET :: ITCH0_RD_INTR [15:15] */
-#define BCHP_HIF_INTR2_PCI_MASK_SET_ITCH0_RD_INTR_MASK 0x00008000
-#define BCHP_HIF_INTR2_PCI_MASK_SET_ITCH0_RD_INTR_SHIFT 15
-#define BCHP_HIF_INTR2_PCI_MASK_SET_ITCH0_RD_INTR_DEFAULT 0x00000001
-
-/* HIF_INTR2 :: PCI_MASK_SET :: reserved2 [14:14] */
-#define BCHP_HIF_INTR2_PCI_MASK_SET_reserved2_MASK 0x00004000
-#define BCHP_HIF_INTR2_PCI_MASK_SET_reserved2_SHIFT 14
-
-/* HIF_INTR2 :: PCI_MASK_SET :: PCIE_RG_BRIDGE_INTR [13:13] */
-#define BCHP_HIF_INTR2_PCI_MASK_SET_PCIE_RG_BRIDGE_INTR_MASK 0x00002000
-#define BCHP_HIF_INTR2_PCI_MASK_SET_PCIE_RG_BRIDGE_INTR_SHIFT 13
-#define BCHP_HIF_INTR2_PCI_MASK_SET_PCIE_RG_BRIDGE_INTR_DEFAULT 0x00000001
-
-/* HIF_INTR2 :: PCI_MASK_SET :: PCIE_RGR_BRIDGE_INTR [12:12] */
-#define BCHP_HIF_INTR2_PCI_MASK_SET_PCIE_RGR_BRIDGE_INTR_MASK 0x00001000
-#define BCHP_HIF_INTR2_PCI_MASK_SET_PCIE_RGR_BRIDGE_INTR_SHIFT 12
-#define BCHP_HIF_INTR2_PCI_MASK_SET_PCIE_RGR_BRIDGE_INTR_DEFAULT 0x00000001
-
-/* HIF_INTR2 :: PCI_MASK_SET :: reserved3 [11:06] */
-#define BCHP_HIF_INTR2_PCI_MASK_SET_reserved3_MASK 0x00000fc0
-#define BCHP_HIF_INTR2_PCI_MASK_SET_reserved3_SHIFT 6
-
-/* HIF_INTR2 :: PCI_MASK_SET :: FLASH_DMA_ERR_INTR [05:05] */
-#define BCHP_HIF_INTR2_PCI_MASK_SET_FLASH_DMA_ERR_INTR_MASK 0x00000020
-#define BCHP_HIF_INTR2_PCI_MASK_SET_FLASH_DMA_ERR_INTR_SHIFT 5
-#define BCHP_HIF_INTR2_PCI_MASK_SET_FLASH_DMA_ERR_INTR_DEFAULT 0x00000000
-
-/* HIF_INTR2 :: PCI_MASK_SET :: FLASH_DMA_DONE_INTR [04:04] */
-#define BCHP_HIF_INTR2_PCI_MASK_SET_FLASH_DMA_DONE_INTR_MASK 0x00000010
-#define BCHP_HIF_INTR2_PCI_MASK_SET_FLASH_DMA_DONE_INTR_SHIFT 4
-#define BCHP_HIF_INTR2_PCI_MASK_SET_FLASH_DMA_DONE_INTR_DEFAULT 0x00000000
-
-/* HIF_INTR2 :: PCI_MASK_SET :: WEBHIF_WD_TIMEOUT_INTR [03:03] */
-#define BCHP_HIF_INTR2_PCI_MASK_SET_WEBHIF_WD_TIMEOUT_INTR_MASK 0x00000008
-#define BCHP_HIF_INTR2_PCI_MASK_SET_WEBHIF_WD_TIMEOUT_INTR_SHIFT 3
-#define BCHP_HIF_INTR2_PCI_MASK_SET_WEBHIF_WD_TIMEOUT_INTR_DEFAULT 0x00000000
-
-/* HIF_INTR2 :: PCI_MASK_SET :: reserved4 [02:02] */
-#define BCHP_HIF_INTR2_PCI_MASK_SET_reserved4_MASK 0x00000004
-#define BCHP_HIF_INTR2_PCI_MASK_SET_reserved4_SHIFT 2
-
-/* HIF_INTR2 :: PCI_MASK_SET :: ITCH1_RD_INTR [01:01] */
-#define BCHP_HIF_INTR2_PCI_MASK_SET_ITCH1_RD_INTR_MASK 0x00000002
-#define BCHP_HIF_INTR2_PCI_MASK_SET_ITCH1_RD_INTR_SHIFT 1
-#define BCHP_HIF_INTR2_PCI_MASK_SET_ITCH1_RD_INTR_DEFAULT 0x00000001
-
-/* HIF_INTR2 :: PCI_MASK_SET :: HIF_RGR2_BRIDGE_INTR [00:00] */
-#define BCHP_HIF_INTR2_PCI_MASK_SET_HIF_RGR2_BRIDGE_INTR_MASK 0x00000001
-#define BCHP_HIF_INTR2_PCI_MASK_SET_HIF_RGR2_BRIDGE_INTR_SHIFT 0
-#define BCHP_HIF_INTR2_PCI_MASK_SET_HIF_RGR2_BRIDGE_INTR_DEFAULT 0x00000001
-
-/***************************************************************************
- *PCI_MASK_CLEAR - PCI interrupt Mask Clear Register
- ***************************************************************************/
-/* HIF_INTR2 :: PCI_MASK_CLEAR :: PCIE_LINKDOWN_INTR [31:31] */
-#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_PCIE_LINKDOWN_INTR_MASK 0x80000000
-#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_PCIE_LINKDOWN_INTR_SHIFT 31
-#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_PCIE_LINKDOWN_INTR_DEFAULT 0x00000000
-
-/* HIF_INTR2 :: PCI_MASK_CLEAR :: PCIE_LINKUP_INTR [30:30] */
-#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_PCIE_LINKUP_INTR_MASK 0x40000000
-#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_PCIE_LINKUP_INTR_SHIFT 30
-#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_PCIE_LINKUP_INTR_DEFAULT 0x00000000
-
-/* HIF_INTR2 :: PCI_MASK_CLEAR :: reserved0 [29:28] */
-#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_reserved0_MASK 0x30000000
-#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_reserved0_SHIFT 28
-
-/* HIF_INTR2 :: PCI_MASK_CLEAR :: NAND_CORR_INTR [27:27] */
-#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_CORR_INTR_MASK 0x08000000
-#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_CORR_INTR_SHIFT 27
-#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_CORR_INTR_DEFAULT 0x00000001
-
-/* HIF_INTR2 :: PCI_MASK_CLEAR :: NAND_UNC_INTR [26:26] */
-#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_UNC_INTR_MASK 0x04000000
-#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_UNC_INTR_SHIFT 26
-#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_UNC_INTR_DEFAULT 0x00000001
-
-/* HIF_INTR2 :: PCI_MASK_CLEAR :: NAND_RBPIN_INTR [25:25] */
-#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_RBPIN_INTR_MASK 0x02000000
-#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_RBPIN_INTR_SHIFT 25
-#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_RBPIN_INTR_DEFAULT 0x00000001
-
-/* HIF_INTR2 :: PCI_MASK_CLEAR :: NAND_CTLRDY_INTR [24:24] */
-#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_CTLRDY_INTR_MASK 0x01000000
-#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_CTLRDY_INTR_SHIFT 24
-#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_CTLRDY_INTR_DEFAULT 0x00000001
-
-/* HIF_INTR2 :: PCI_MASK_CLEAR :: NAND_PGMPG_INTR [23:23] */
-#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_PGMPG_INTR_MASK 0x00800000
-#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_PGMPG_INTR_SHIFT 23
-#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_PGMPG_INTR_DEFAULT 0x00000001
-
-/* HIF_INTR2 :: PCI_MASK_CLEAR :: NAND_CPYBK_INTR [22:22] */
-#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_CPYBK_INTR_MASK 0x00400000
-#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_CPYBK_INTR_SHIFT 22
-#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_CPYBK_INTR_DEFAULT 0x00000001
-
-/* HIF_INTR2 :: PCI_MASK_CLEAR :: NAND_BLKERA_INTR [21:21] */
-#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_BLKERA_INTR_MASK 0x00200000
-#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_BLKERA_INTR_SHIFT 21
-#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_BLKERA_INTR_DEFAULT 0x00000001
-
-/* HIF_INTR2 :: PCI_MASK_CLEAR :: NAND_NP_READ_INTR [20:20] */
-#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_NP_READ_INTR_MASK 0x00100000
-#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_NP_READ_INTR_SHIFT 20
-#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_NP_READ_INTR_DEFAULT 0x00000001
-
-/* HIF_INTR2 :: PCI_MASK_CLEAR :: reserved1 [19:18] */
-#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_reserved1_MASK 0x000c0000
-#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_reserved1_SHIFT 18
-
-/* HIF_INTR2 :: PCI_MASK_CLEAR :: EBI_TIMEOUT_INTR [17:17] */
-#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_EBI_TIMEOUT_INTR_MASK 0x00020000
-#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_EBI_TIMEOUT_INTR_SHIFT 17
-#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_EBI_TIMEOUT_INTR_DEFAULT 0x00000001
-
-/* HIF_INTR2 :: PCI_MASK_CLEAR :: EBI_TEA_INTR [16:16] */
-#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_EBI_TEA_INTR_MASK 0x00010000
-#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_EBI_TEA_INTR_SHIFT 16
-#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_EBI_TEA_INTR_DEFAULT 0x00000001
-
-/* HIF_INTR2 :: PCI_MASK_CLEAR :: ITCH0_RD_INTR [15:15] */
-#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_ITCH0_RD_INTR_MASK 0x00008000
-#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_ITCH0_RD_INTR_SHIFT 15
-#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_ITCH0_RD_INTR_DEFAULT 0x00000001
-
-/* HIF_INTR2 :: PCI_MASK_CLEAR :: reserved2 [14:14] */
-#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_reserved2_MASK 0x00004000
-#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_reserved2_SHIFT 14
-
-/* HIF_INTR2 :: PCI_MASK_CLEAR :: PCIE_RG_BRIDGE_INTR [13:13] */
-#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_PCIE_RG_BRIDGE_INTR_MASK 0x00002000
-#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_PCIE_RG_BRIDGE_INTR_SHIFT 13
-#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_PCIE_RG_BRIDGE_INTR_DEFAULT 0x00000001
-
-/* HIF_INTR2 :: PCI_MASK_CLEAR :: PCIE_RGR_BRIDGE_INTR [12:12] */
-#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_PCIE_RGR_BRIDGE_INTR_MASK 0x00001000
-#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_PCIE_RGR_BRIDGE_INTR_SHIFT 12
-#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_PCIE_RGR_BRIDGE_INTR_DEFAULT 0x00000001
-
-/* HIF_INTR2 :: PCI_MASK_CLEAR :: reserved3 [11:06] */
-#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_reserved3_MASK 0x00000fc0
-#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_reserved3_SHIFT 6
-
-/* HIF_INTR2 :: PCI_MASK_CLEAR :: FLASH_DMA_ERR_INTR [05:05] */
-#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_FLASH_DMA_ERR_INTR_MASK 0x00000020
-#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_FLASH_DMA_ERR_INTR_SHIFT 5
-#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_FLASH_DMA_ERR_INTR_DEFAULT 0x00000000
-
-/* HIF_INTR2 :: PCI_MASK_CLEAR :: FLASH_DMA_DONE_INTR [04:04] */
-#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_FLASH_DMA_DONE_INTR_MASK 0x00000010
-#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_FLASH_DMA_DONE_INTR_SHIFT 4
-#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_FLASH_DMA_DONE_INTR_DEFAULT 0x00000000
-
-/* HIF_INTR2 :: PCI_MASK_CLEAR :: WEBHIF_WD_TIMEOUT_INTR [03:03] */
-#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_WEBHIF_WD_TIMEOUT_INTR_MASK 0x00000008
-#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_WEBHIF_WD_TIMEOUT_INTR_SHIFT 3
-#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_WEBHIF_WD_TIMEOUT_INTR_DEFAULT 0x00000000
-
-/* HIF_INTR2 :: PCI_MASK_CLEAR :: reserved4 [02:02] */
-#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_reserved4_MASK 0x00000004
-#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_reserved4_SHIFT 2
-
-/* HIF_INTR2 :: PCI_MASK_CLEAR :: ITCH1_RD_INTR [01:01] */
-#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_ITCH1_RD_INTR_MASK 0x00000002
-#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_ITCH1_RD_INTR_SHIFT 1
-#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_ITCH1_RD_INTR_DEFAULT 0x00000001
-
-/* HIF_INTR2 :: PCI_MASK_CLEAR :: HIF_RGR2_BRIDGE_INTR [00:00] */
-#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_HIF_RGR2_BRIDGE_INTR_MASK 0x00000001
-#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_HIF_RGR2_BRIDGE_INTR_SHIFT 0
-#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_HIF_RGR2_BRIDGE_INTR_DEFAULT 0x00000001
-
-#endif /* #ifndef BCHP_HIF_INTR2_H__ */
-
-/* End of File */
diff --git a/include/linux/brcmstb/7439a0/bchp_hif_mspi.h b/include/linux/brcmstb/7439a0/bchp_hif_mspi.h
deleted file mode 100644
index e537c46..0000000
--- a/include/linux/brcmstb/7439a0/bchp_hif_mspi.h
+++ /dev/null
@@ -1,1289 +0,0 @@
-/***************************************************************************
- * Copyright (c) 1999-2012, Broadcom Corporation
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
- *
- * Module Description:
- * DO NOT EDIT THIS FILE DIRECTLY
- *
- * This module was generated magically with RDB from a source description
- * file. You must edit the source file for changes to be made to this file.
- *
- *
- * Date: Generated on Wed Oct 17 03:11:31 2012
- * MD5 Checksum d41d8cd98f00b204e9800998ecf8427e
- *
- * Compiled with: RDB Utility combo_header.pl
- * RDB Parser 3.0
- * unknown unknown
- * Perl Interpreter 5.008008
- * Operating System linux
- *
- * Revision History:
- *
- * $brcm_Log: $
- *
- ***************************************************************************/
-
-#ifndef BCHP_HIF_MSPI_H__
-#define BCHP_HIF_MSPI_H__
-
-/***************************************************************************
- *HIF_MSPI - Public MSPI Registers
- ***************************************************************************/
-#define BCHP_HIF_MSPI_SPCR0_LSB 0x00443400 /* SPCR0_LSB REGISTER */
-#define BCHP_HIF_MSPI_SPCR0_MSB 0x00443404 /* SPCR0_MSB Register */
-#define BCHP_HIF_MSPI_SPCR1_LSB 0x00443408 /* SPCR1_LSB REGISTER */
-#define BCHP_HIF_MSPI_SPCR1_MSB 0x0044340c /* SPCR1_MSB REGISTER */
-#define BCHP_HIF_MSPI_NEWQP 0x00443410 /* NEWQP REGISTER */
-#define BCHP_HIF_MSPI_ENDQP 0x00443414 /* ENDQP REGISTER */
-#define BCHP_HIF_MSPI_SPCR2 0x00443418 /* SPCR2 REGISTER */
-#define BCHP_HIF_MSPI_MSPI_STATUS 0x00443420 /* MSPI STATUS REGISTER */
-#define BCHP_HIF_MSPI_CPTQP 0x00443424 /* CPTQP REGISTER */
-#define BCHP_HIF_MSPI_SPCR3 0x00443428 /* SPCR3 REGISTER */
-#define BCHP_HIF_MSPI_REVISION 0x0044342c /* REVISION ID REGISTER */
-#define BCHP_HIF_MSPI_TXRAM00 0x00443440 /* Most significant byte of TXRAM[0] (queue pointer = 0) */
-#define BCHP_HIF_MSPI_TXRAM01 0x00443444 /* Least significant byte of TXRAM[0] (queue pointer = 0) */
-#define BCHP_HIF_MSPI_TXRAM02 0x00443448 /* Most significant byte of TXRAM[1] (queue pointer = 1) */
-#define BCHP_HIF_MSPI_TXRAM03 0x0044344c /* Least significant byte of TXRAM[1] (queue pointer = 1) */
-#define BCHP_HIF_MSPI_TXRAM04 0x00443450 /* Most significant byte of TXRAM[2] (queue pointer = 2) */
-#define BCHP_HIF_MSPI_TXRAM05 0x00443454 /* Least significant byte of TXRAM[2] (queue pointer = 2) */
-#define BCHP_HIF_MSPI_TXRAM06 0x00443458 /* Most significant byte of TXRAM[3] (queue pointer = 3) */
-#define BCHP_HIF_MSPI_TXRAM07 0x0044345c /* Least significant byte of TXRAM[3] (queue pointer = 3) */
-#define BCHP_HIF_MSPI_TXRAM08 0x00443460 /* Most significant byte of TXRAM[4] (queue pointer = 4) */
-#define BCHP_HIF_MSPI_TXRAM09 0x00443464 /* Least significant byte of TXRAM[4] (queue pointer = 4) */
-#define BCHP_HIF_MSPI_TXRAM10 0x00443468 /* Most significant byte of TXRAM[5] (queue pointer = 5) */
-#define BCHP_HIF_MSPI_TXRAM11 0x0044346c /* Least significant byte of TXRAM[5] (queue pointer = 5) */
-#define BCHP_HIF_MSPI_TXRAM12 0x00443470 /* Most significant byte of TXRAM[6] (queue pointer = 6) */
-#define BCHP_HIF_MSPI_TXRAM13 0x00443474 /* Least significant byte of TXRAM[6] (queue pointer = 6) */
-#define BCHP_HIF_MSPI_TXRAM14 0x00443478 /* Most significant byte of TXRAM[7] (queue pointer = 7) */
-#define BCHP_HIF_MSPI_TXRAM15 0x0044347c /* Least significant byte of TXRAM[7] (queue pointer = 7) */
-#define BCHP_HIF_MSPI_TXRAM16 0x00443480 /* Most significant byte of TXRAM[8] (queue pointer = 8) */
-#define BCHP_HIF_MSPI_TXRAM17 0x00443484 /* Least significant byte of TXRAM[8] (queue pointer = 8) */
-#define BCHP_HIF_MSPI_TXRAM18 0x00443488 /* Most significant byte of TXRAM[9] (queue pointer = 9) */
-#define BCHP_HIF_MSPI_TXRAM19 0x0044348c /* Least significant byte of TXRAM[9] (queue pointer = 9) */
-#define BCHP_HIF_MSPI_TXRAM20 0x00443490 /* Most significant byte of TXRAM[10] (queue pointer = 10) */
-#define BCHP_HIF_MSPI_TXRAM21 0x00443494 /* Least significant byte of TXRAM[10] (queue pointer = 10) */
-#define BCHP_HIF_MSPI_TXRAM22 0x00443498 /* Most significant byte of TXRAM[11] (queue pointer = 11) */
-#define BCHP_HIF_MSPI_TXRAM23 0x0044349c /* Least significant byte of TXRAM[11] (queue pointer = 11) */
-#define BCHP_HIF_MSPI_TXRAM24 0x004434a0 /* Most significant byte of TXRAM[12] (queue pointer = 12) */
-#define BCHP_HIF_MSPI_TXRAM25 0x004434a4 /* Least significant byte of TXRAM[12] (queue pointer = 12) */
-#define BCHP_HIF_MSPI_TXRAM26 0x004434a8 /* Most significant byte of TXRAM[13] (queue pointer = 13) */
-#define BCHP_HIF_MSPI_TXRAM27 0x004434ac /* Least significant byte of TXRAM[13] (queue pointer = 13) */
-#define BCHP_HIF_MSPI_TXRAM28 0x004434b0 /* Most significant byte of TXRAM[14] (queue pointer = 14) */
-#define BCHP_HIF_MSPI_TXRAM29 0x004434b4 /* Least significant byte of TXRAM[14] (queue pointer = 14) */
-#define BCHP_HIF_MSPI_TXRAM30 0x004434b8 /* Most significant byte of TXRAM[15] (queue pointer = 15) */
-#define BCHP_HIF_MSPI_TXRAM31 0x004434bc /* Least significant byte of TXRAM[15] (queue pointer = 15) */
-#define BCHP_HIF_MSPI_RXRAM00 0x004434c0 /* Most significant byte of RXRAM[0] (queue pointer = 0) */
-#define BCHP_HIF_MSPI_RXRAM01 0x004434c4 /* Least significant byte of RXRAM[0] (queue pointer = 0) */
-#define BCHP_HIF_MSPI_RXRAM02 0x004434c8 /* Most significant byte of RXRAM[1] (queue pointer = 1) */
-#define BCHP_HIF_MSPI_RXRAM03 0x004434cc /* Least significant byte of RXRAM[1] (queue pointer = 1) */
-#define BCHP_HIF_MSPI_RXRAM04 0x004434d0 /* Most significant byte of RXRAM[2] (queue pointer = 2) */
-#define BCHP_HIF_MSPI_RXRAM05 0x004434d4 /* Least significant byte of RXRAM[2] (queue pointer = 2) */
-#define BCHP_HIF_MSPI_RXRAM06 0x004434d8 /* Most significant byte of RXRAM[3] (queue pointer = 3) */
-#define BCHP_HIF_MSPI_RXRAM07 0x004434dc /* Least significant byte of RXRAM[3] (queue pointer = 3) */
-#define BCHP_HIF_MSPI_RXRAM08 0x004434e0 /* Most significant byte of RXRAM[4] (queue pointer = 4) */
-#define BCHP_HIF_MSPI_RXRAM09 0x004434e4 /* Least significant byte of RXRAM[4] (queue pointer = 4) */
-#define BCHP_HIF_MSPI_RXRAM10 0x004434e8 /* Most significant byte of RXRAM[5] (queue pointer = 5) */
-#define BCHP_HIF_MSPI_RXRAM11 0x004434ec /* Least significant byte of RXRAM[5] (queue pointer = 5) */
-#define BCHP_HIF_MSPI_RXRAM12 0x004434f0 /* Most significant byte of RXRAM[6] (queue pointer = 6) */
-#define BCHP_HIF_MSPI_RXRAM13 0x004434f4 /* Least significant byte of RXRAM[6] (queue pointer = 6) */
-#define BCHP_HIF_MSPI_RXRAM14 0x004434f8 /* Most significant byte of RXRAM[7] (queue pointer = 7) */
-#define BCHP_HIF_MSPI_RXRAM15 0x004434fc /* Least significant byte of RXRAM[7] (queue pointer = 7) */
-#define BCHP_HIF_MSPI_RXRAM16 0x00443500 /* Most significant byte of RXRAM[8] (queue pointer = 8) */
-#define BCHP_HIF_MSPI_RXRAM17 0x00443504 /* Least significant byte of RXRAM[8] (queue pointer = 8) */
-#define BCHP_HIF_MSPI_RXRAM18 0x00443508 /* Most significant byte of RXRAM[9] (queue pointer = 9) */
-#define BCHP_HIF_MSPI_RXRAM19 0x0044350c /* Least significant byte of RXRAM[9] (queue pointer = 9) */
-#define BCHP_HIF_MSPI_RXRAM20 0x00443510 /* Most significant byte of RXRAM[10] (queue pointer = 10) */
-#define BCHP_HIF_MSPI_RXRAM21 0x00443514 /* Least significant byte of RXRAM[10] (queue pointer = 10) */
-#define BCHP_HIF_MSPI_RXRAM22 0x00443518 /* Most significant byte of RXRAM[11] (queue pointer = 11) */
-#define BCHP_HIF_MSPI_RXRAM23 0x0044351c /* Least significant byte of RXRAM[11] (queue pointer = 11) */
-#define BCHP_HIF_MSPI_RXRAM24 0x00443520 /* Most significant byte of RXRAM[12] (queue pointer = 12) */
-#define BCHP_HIF_MSPI_RXRAM25 0x00443524 /* Least significant byte of RXRAM[12] (queue pointer = 12) */
-#define BCHP_HIF_MSPI_RXRAM26 0x00443528 /* Most significant byte of RXRAM[13] (queue pointer = 13) */
-#define BCHP_HIF_MSPI_RXRAM27 0x0044352c /* Least significant byte of RXRAM[13] (queue pointer = 13) */
-#define BCHP_HIF_MSPI_RXRAM28 0x00443530 /* Most significant byte of RXRAM[14] (queue pointer = 14) */
-#define BCHP_HIF_MSPI_RXRAM29 0x00443534 /* Least significant byte of RXRAM[14] (queue pointer = 14) */
-#define BCHP_HIF_MSPI_RXRAM30 0x00443538 /* Most significant byte of RXRAM[15] (queue pointer = 15) */
-#define BCHP_HIF_MSPI_RXRAM31 0x0044353c /* Least significant byte of RXRAM[15] (queue pointer = 15) */
-#define BCHP_HIF_MSPI_CDRAM00 0x00443540 /* 8-bit command (queue pointer = 0) */
-#define BCHP_HIF_MSPI_CDRAM01 0x00443544 /* 8-bit command (queue pointer = 1) */
-#define BCHP_HIF_MSPI_CDRAM02 0x00443548 /* 8-bit command (queue pointer = 2) */
-#define BCHP_HIF_MSPI_CDRAM03 0x0044354c /* 8-bit command (queue pointer = 3) */
-#define BCHP_HIF_MSPI_CDRAM04 0x00443550 /* 8-bit command (queue pointer = 4) */
-#define BCHP_HIF_MSPI_CDRAM05 0x00443554 /* 8-bit command (queue pointer = 5) */
-#define BCHP_HIF_MSPI_CDRAM06 0x00443558 /* 8-bit command (queue pointer = 6) */
-#define BCHP_HIF_MSPI_CDRAM07 0x0044355c /* 8-bit command (queue pointer = 7) */
-#define BCHP_HIF_MSPI_CDRAM08 0x00443560 /* 8-bit command (queue pointer = 8) */
-#define BCHP_HIF_MSPI_CDRAM09 0x00443564 /* 8-bit command (queue pointer = 9) */
-#define BCHP_HIF_MSPI_CDRAM10 0x00443568 /* 8-bit command (queue pointer = a) */
-#define BCHP_HIF_MSPI_CDRAM11 0x0044356c /* 8-bit command (queue pointer = b) */
-#define BCHP_HIF_MSPI_CDRAM12 0x00443570 /* 8-bit command (queue pointer = c) */
-#define BCHP_HIF_MSPI_CDRAM13 0x00443574 /* 8-bit command (queue pointer = d) */
-#define BCHP_HIF_MSPI_CDRAM14 0x00443578 /* 8-bit command (queue pointer = e) */
-#define BCHP_HIF_MSPI_CDRAM15 0x0044357c /* 8-bit command (queue pointer = f) */
-#define BCHP_HIF_MSPI_WRITE_LOCK 0x00443580 /* Control bit to lock group of write commands */
-#define BCHP_HIF_MSPI_DISABLE_FLUSH_GEN 0x00443584 /* Debug bit to mask the generation of flush signals from Mspi */
-
-/***************************************************************************
- *SPCR0_LSB - SPCR0_LSB REGISTER
- ***************************************************************************/
-/* HIF_MSPI :: SPCR0_LSB :: reserved0 [31:08] */
-#define BCHP_HIF_MSPI_SPCR0_LSB_reserved0_MASK 0xffffff00
-#define BCHP_HIF_MSPI_SPCR0_LSB_reserved0_SHIFT 8
-
-/* HIF_MSPI :: SPCR0_LSB :: SPBR [07:00] */
-#define BCHP_HIF_MSPI_SPCR0_LSB_SPBR_MASK 0x000000ff
-#define BCHP_HIF_MSPI_SPCR0_LSB_SPBR_SHIFT 0
-#define BCHP_HIF_MSPI_SPCR0_LSB_SPBR_DEFAULT 0x00000000
-
-/***************************************************************************
- *SPCR0_MSB - SPCR0_MSB Register
- ***************************************************************************/
-/* HIF_MSPI :: SPCR0_MSB :: reserved0 [31:09] */
-#define BCHP_HIF_MSPI_SPCR0_MSB_reserved0_MASK 0xfffffe00
-#define BCHP_HIF_MSPI_SPCR0_MSB_reserved0_SHIFT 9
-
-/* HIF_MSPI :: SPCR0_MSB :: StartTransDelay [08:08] */
-#define BCHP_HIF_MSPI_SPCR0_MSB_StartTransDelay_MASK 0x00000100
-#define BCHP_HIF_MSPI_SPCR0_MSB_StartTransDelay_SHIFT 8
-#define BCHP_HIF_MSPI_SPCR0_MSB_StartTransDelay_DEFAULT 0x00000000
-
-/* union - case data_reg_8 [07:02] */
-/* HIF_MSPI :: SPCR0_MSB :: data_reg_8 :: reserved0 [07:06] */
-#define BCHP_HIF_MSPI_SPCR0_MSB_data_reg_8_reserved0_MASK 0x000000c0
-#define BCHP_HIF_MSPI_SPCR0_MSB_data_reg_8_reserved0_SHIFT 6
-
-/* HIF_MSPI :: SPCR0_MSB :: data_reg_8 :: BITS [05:02] */
-#define BCHP_HIF_MSPI_SPCR0_MSB_data_reg_8_BITS_MASK 0x0000003c
-#define BCHP_HIF_MSPI_SPCR0_MSB_data_reg_8_BITS_SHIFT 2
-#define BCHP_HIF_MSPI_SPCR0_MSB_data_reg_8_BITS_DEFAULT 0x00000000
-
-/* union - case data_reg_32 [07:02] */
-/* HIF_MSPI :: SPCR0_MSB :: data_reg_32 :: BITS [07:02] */
-#define BCHP_HIF_MSPI_SPCR0_MSB_data_reg_32_BITS_MASK 0x000000fc
-#define BCHP_HIF_MSPI_SPCR0_MSB_data_reg_32_BITS_SHIFT 2
-#define BCHP_HIF_MSPI_SPCR0_MSB_data_reg_32_BITS_DEFAULT 0x00000000
-
-/* HIF_MSPI :: SPCR0_MSB :: CPOL [01:01] */
-#define BCHP_HIF_MSPI_SPCR0_MSB_CPOL_MASK 0x00000002
-#define BCHP_HIF_MSPI_SPCR0_MSB_CPOL_SHIFT 1
-#define BCHP_HIF_MSPI_SPCR0_MSB_CPOL_DEFAULT 0x00000000
-
-/* HIF_MSPI :: SPCR0_MSB :: CPHA [00:00] */
-#define BCHP_HIF_MSPI_SPCR0_MSB_CPHA_MASK 0x00000001
-#define BCHP_HIF_MSPI_SPCR0_MSB_CPHA_SHIFT 0
-#define BCHP_HIF_MSPI_SPCR0_MSB_CPHA_DEFAULT 0x00000000
-
-/***************************************************************************
- *SPCR1_LSB - SPCR1_LSB REGISTER
- ***************************************************************************/
-/* HIF_MSPI :: SPCR1_LSB :: reserved0 [31:08] */
-#define BCHP_HIF_MSPI_SPCR1_LSB_reserved0_MASK 0xffffff00
-#define BCHP_HIF_MSPI_SPCR1_LSB_reserved0_SHIFT 8
-
-/* HIF_MSPI :: SPCR1_LSB :: DTL [07:00] */
-#define BCHP_HIF_MSPI_SPCR1_LSB_DTL_MASK 0x000000ff
-#define BCHP_HIF_MSPI_SPCR1_LSB_DTL_SHIFT 0
-#define BCHP_HIF_MSPI_SPCR1_LSB_DTL_DEFAULT 0x00000000
-
-/***************************************************************************
- *SPCR1_MSB - SPCR1_MSB REGISTER
- ***************************************************************************/
-/* HIF_MSPI :: SPCR1_MSB :: reserved0 [31:08] */
-#define BCHP_HIF_MSPI_SPCR1_MSB_reserved0_MASK 0xffffff00
-#define BCHP_HIF_MSPI_SPCR1_MSB_reserved0_SHIFT 8
-
-/* HIF_MSPI :: SPCR1_MSB :: RDSCLK [07:00] */
-#define BCHP_HIF_MSPI_SPCR1_MSB_RDSCLK_MASK 0x000000ff
-#define BCHP_HIF_MSPI_SPCR1_MSB_RDSCLK_SHIFT 0
-#define BCHP_HIF_MSPI_SPCR1_MSB_RDSCLK_DEFAULT 0x00000000
-
-/***************************************************************************
- *NEWQP - NEWQP REGISTER
- ***************************************************************************/
-/* HIF_MSPI :: NEWQP :: reserved0 [31:04] */
-#define BCHP_HIF_MSPI_NEWQP_reserved0_MASK 0xfffffff0
-#define BCHP_HIF_MSPI_NEWQP_reserved0_SHIFT 4
-
-/* HIF_MSPI :: NEWQP :: newqp [03:00] */
-#define BCHP_HIF_MSPI_NEWQP_newqp_MASK 0x0000000f
-#define BCHP_HIF_MSPI_NEWQP_newqp_SHIFT 0
-#define BCHP_HIF_MSPI_NEWQP_newqp_DEFAULT 0x00000000
-
-/***************************************************************************
- *ENDQP - ENDQP REGISTER
- ***************************************************************************/
-/* HIF_MSPI :: ENDQP :: reserved0 [31:04] */
-#define BCHP_HIF_MSPI_ENDQP_reserved0_MASK 0xfffffff0
-#define BCHP_HIF_MSPI_ENDQP_reserved0_SHIFT 4
-
-/* HIF_MSPI :: ENDQP :: endqp [03:00] */
-#define BCHP_HIF_MSPI_ENDQP_endqp_MASK 0x0000000f
-#define BCHP_HIF_MSPI_ENDQP_endqp_SHIFT 0
-#define BCHP_HIF_MSPI_ENDQP_endqp_DEFAULT 0x00000000
-
-/***************************************************************************
- *SPCR2 - SPCR2 REGISTER
- ***************************************************************************/
-/* HIF_MSPI :: SPCR2 :: reserved0 [31:08] */
-#define BCHP_HIF_MSPI_SPCR2_reserved0_MASK 0xffffff00
-#define BCHP_HIF_MSPI_SPCR2_reserved0_SHIFT 8
-
-/* HIF_MSPI :: SPCR2 :: cont_after_cmd [07:07] */
-#define BCHP_HIF_MSPI_SPCR2_cont_after_cmd_MASK 0x00000080
-#define BCHP_HIF_MSPI_SPCR2_cont_after_cmd_SHIFT 7
-#define BCHP_HIF_MSPI_SPCR2_cont_after_cmd_DEFAULT 0x00000000
-
-/* HIF_MSPI :: SPCR2 :: spe [06:06] */
-#define BCHP_HIF_MSPI_SPCR2_spe_MASK 0x00000040
-#define BCHP_HIF_MSPI_SPCR2_spe_SHIFT 6
-#define BCHP_HIF_MSPI_SPCR2_spe_DEFAULT 0x00000000
-
-/* HIF_MSPI :: SPCR2 :: spifie [05:05] */
-#define BCHP_HIF_MSPI_SPCR2_spifie_MASK 0x00000020
-#define BCHP_HIF_MSPI_SPCR2_spifie_SHIFT 5
-#define BCHP_HIF_MSPI_SPCR2_spifie_DEFAULT 0x00000000
-
-/* HIF_MSPI :: SPCR2 :: wren [04:04] */
-#define BCHP_HIF_MSPI_SPCR2_wren_MASK 0x00000010
-#define BCHP_HIF_MSPI_SPCR2_wren_SHIFT 4
-#define BCHP_HIF_MSPI_SPCR2_wren_DEFAULT 0x00000000
-
-/* HIF_MSPI :: SPCR2 :: wrt0 [03:03] */
-#define BCHP_HIF_MSPI_SPCR2_wrt0_MASK 0x00000008
-#define BCHP_HIF_MSPI_SPCR2_wrt0_SHIFT 3
-#define BCHP_HIF_MSPI_SPCR2_wrt0_DEFAULT 0x00000000
-
-/* HIF_MSPI :: SPCR2 :: loopq [02:02] */
-#define BCHP_HIF_MSPI_SPCR2_loopq_MASK 0x00000004
-#define BCHP_HIF_MSPI_SPCR2_loopq_SHIFT 2
-#define BCHP_HIF_MSPI_SPCR2_loopq_DEFAULT 0x00000000
-
-/* HIF_MSPI :: SPCR2 :: hie [01:01] */
-#define BCHP_HIF_MSPI_SPCR2_hie_MASK 0x00000002
-#define BCHP_HIF_MSPI_SPCR2_hie_SHIFT 1
-#define BCHP_HIF_MSPI_SPCR2_hie_DEFAULT 0x00000000
-
-/* HIF_MSPI :: SPCR2 :: halt [00:00] */
-#define BCHP_HIF_MSPI_SPCR2_halt_MASK 0x00000001
-#define BCHP_HIF_MSPI_SPCR2_halt_SHIFT 0
-#define BCHP_HIF_MSPI_SPCR2_halt_DEFAULT 0x00000000
-
-/***************************************************************************
- *MSPI_STATUS - MSPI STATUS REGISTER
- ***************************************************************************/
-/* HIF_MSPI :: MSPI_STATUS :: reserved0 [31:02] */
-#define BCHP_HIF_MSPI_MSPI_STATUS_reserved0_MASK 0xfffffffc
-#define BCHP_HIF_MSPI_MSPI_STATUS_reserved0_SHIFT 2
-
-/* HIF_MSPI :: MSPI_STATUS :: HALTA [01:01] */
-#define BCHP_HIF_MSPI_MSPI_STATUS_HALTA_MASK 0x00000002
-#define BCHP_HIF_MSPI_MSPI_STATUS_HALTA_SHIFT 1
-#define BCHP_HIF_MSPI_MSPI_STATUS_HALTA_DEFAULT 0x00000000
-
-/* HIF_MSPI :: MSPI_STATUS :: SPIF [00:00] */
-#define BCHP_HIF_MSPI_MSPI_STATUS_SPIF_MASK 0x00000001
-#define BCHP_HIF_MSPI_MSPI_STATUS_SPIF_SHIFT 0
-#define BCHP_HIF_MSPI_MSPI_STATUS_SPIF_DEFAULT 0x00000000
-
-/***************************************************************************
- *CPTQP - CPTQP REGISTER
- ***************************************************************************/
-/* HIF_MSPI :: CPTQP :: reserved0 [31:04] */
-#define BCHP_HIF_MSPI_CPTQP_reserved0_MASK 0xfffffff0
-#define BCHP_HIF_MSPI_CPTQP_reserved0_SHIFT 4
-
-/* HIF_MSPI :: CPTQP :: cptqp [03:00] */
-#define BCHP_HIF_MSPI_CPTQP_cptqp_MASK 0x0000000f
-#define BCHP_HIF_MSPI_CPTQP_cptqp_SHIFT 0
-#define BCHP_HIF_MSPI_CPTQP_cptqp_DEFAULT 0x00000000
-
-/***************************************************************************
- *SPCR3 - SPCR3 REGISTER
- ***************************************************************************/
-/* HIF_MSPI :: SPCR3 :: reserved0 [31:10] */
-#define BCHP_HIF_MSPI_SPCR3_reserved0_MASK 0xfffffc00
-#define BCHP_HIF_MSPI_SPCR3_reserved0_SHIFT 10
-
-/* HIF_MSPI :: SPCR3 :: cpharx [09:09] */
-#define BCHP_HIF_MSPI_SPCR3_cpharx_MASK 0x00000200
-#define BCHP_HIF_MSPI_SPCR3_cpharx_SHIFT 9
-#define BCHP_HIF_MSPI_SPCR3_cpharx_DEFAULT 0x00000000
-
-/* HIF_MSPI :: SPCR3 :: data_reg_size [08:08] */
-#define BCHP_HIF_MSPI_SPCR3_data_reg_size_MASK 0x00000100
-#define BCHP_HIF_MSPI_SPCR3_data_reg_size_SHIFT 8
-#define BCHP_HIF_MSPI_SPCR3_data_reg_size_DEFAULT 0x00000000
-
-/* HIF_MSPI :: SPCR3 :: hdouttype [07:07] */
-#define BCHP_HIF_MSPI_SPCR3_hdouttype_MASK 0x00000080
-#define BCHP_HIF_MSPI_SPCR3_hdouttype_SHIFT 7
-#define BCHP_HIF_MSPI_SPCR3_hdouttype_DEFAULT 0x00000000
-
-/* HIF_MSPI :: SPCR3 :: halfduplex [06:06] */
-#define BCHP_HIF_MSPI_SPCR3_halfduplex_MASK 0x00000040
-#define BCHP_HIF_MSPI_SPCR3_halfduplex_SHIFT 6
-#define BCHP_HIF_MSPI_SPCR3_halfduplex_DEFAULT 0x00000000
-
-/* HIF_MSPI :: SPCR3 :: txramdam [05:04] */
-#define BCHP_HIF_MSPI_SPCR3_txramdam_MASK 0x00000030
-#define BCHP_HIF_MSPI_SPCR3_txramdam_SHIFT 4
-#define BCHP_HIF_MSPI_SPCR3_txramdam_DEFAULT 0x00000000
-#define BCHP_HIF_MSPI_SPCR3_txramdam_DAM_8B 0
-#define BCHP_HIF_MSPI_SPCR3_txramdam_DAM_16B 1
-#define BCHP_HIF_MSPI_SPCR3_txramdam_DAM_32B 2
-
-/* HIF_MSPI :: SPCR3 :: rxramdam [03:02] */
-#define BCHP_HIF_MSPI_SPCR3_rxramdam_MASK 0x0000000c
-#define BCHP_HIF_MSPI_SPCR3_rxramdam_SHIFT 2
-#define BCHP_HIF_MSPI_SPCR3_rxramdam_DEFAULT 0x00000000
-#define BCHP_HIF_MSPI_SPCR3_rxramdam_DAM_8B 0
-#define BCHP_HIF_MSPI_SPCR3_rxramdam_DAM_16B 1
-#define BCHP_HIF_MSPI_SPCR3_rxramdam_DAM_32B 2
-
-/* HIF_MSPI :: SPCR3 :: fastdt [01:01] */
-#define BCHP_HIF_MSPI_SPCR3_fastdt_MASK 0x00000002
-#define BCHP_HIF_MSPI_SPCR3_fastdt_SHIFT 1
-#define BCHP_HIF_MSPI_SPCR3_fastdt_DEFAULT 0x00000000
-
-/* HIF_MSPI :: SPCR3 :: fastbr [00:00] */
-#define BCHP_HIF_MSPI_SPCR3_fastbr_MASK 0x00000001
-#define BCHP_HIF_MSPI_SPCR3_fastbr_SHIFT 0
-#define BCHP_HIF_MSPI_SPCR3_fastbr_DEFAULT 0x00000000
-
-/***************************************************************************
- *REVISION - REVISION ID REGISTER
- ***************************************************************************/
-/* HIF_MSPI :: REVISION :: reserved0 [31:08] */
-#define BCHP_HIF_MSPI_REVISION_reserved0_MASK 0xffffff00
-#define BCHP_HIF_MSPI_REVISION_reserved0_SHIFT 8
-
-/* HIF_MSPI :: REVISION :: major [07:04] */
-#define BCHP_HIF_MSPI_REVISION_major_MASK 0x000000f0
-#define BCHP_HIF_MSPI_REVISION_major_SHIFT 4
-#define BCHP_HIF_MSPI_REVISION_major_DEFAULT 0x00000001
-
-/* HIF_MSPI :: REVISION :: minor [03:00] */
-#define BCHP_HIF_MSPI_REVISION_minor_MASK 0x0000000f
-#define BCHP_HIF_MSPI_REVISION_minor_SHIFT 0
-#define BCHP_HIF_MSPI_REVISION_minor_DEFAULT 0x00000005
-
-/***************************************************************************
- *TXRAM00 - Most significant byte of TXRAM[0] (queue pointer = 0)
- ***************************************************************************/
-/* HIF_MSPI :: TXRAM00 :: reserved0 [31:08] */
-#define BCHP_HIF_MSPI_TXRAM00_reserved0_MASK 0xffffff00
-#define BCHP_HIF_MSPI_TXRAM00_reserved0_SHIFT 8
-
-/* HIF_MSPI :: TXRAM00 :: txram [07:00] */
-#define BCHP_HIF_MSPI_TXRAM00_txram_MASK 0x000000ff
-#define BCHP_HIF_MSPI_TXRAM00_txram_SHIFT 0
-
-/***************************************************************************
- *TXRAM01 - Least significant byte of TXRAM[0] (queue pointer = 0)
- ***************************************************************************/
-/* HIF_MSPI :: TXRAM01 :: reserved0 [31:08] */
-#define BCHP_HIF_MSPI_TXRAM01_reserved0_MASK 0xffffff00
-#define BCHP_HIF_MSPI_TXRAM01_reserved0_SHIFT 8
-
-/* HIF_MSPI :: TXRAM01 :: txram [07:00] */
-#define BCHP_HIF_MSPI_TXRAM01_txram_MASK 0x000000ff
-#define BCHP_HIF_MSPI_TXRAM01_txram_SHIFT 0
-
-/***************************************************************************
- *TXRAM02 - Most significant byte of TXRAM[1] (queue pointer = 1)
- ***************************************************************************/
-/* HIF_MSPI :: TXRAM02 :: reserved0 [31:08] */
-#define BCHP_HIF_MSPI_TXRAM02_reserved0_MASK 0xffffff00
-#define BCHP_HIF_MSPI_TXRAM02_reserved0_SHIFT 8
-
-/* HIF_MSPI :: TXRAM02 :: txram [07:00] */
-#define BCHP_HIF_MSPI_TXRAM02_txram_MASK 0x000000ff
-#define BCHP_HIF_MSPI_TXRAM02_txram_SHIFT 0
-
-/***************************************************************************
- *TXRAM03 - Least significant byte of TXRAM[1] (queue pointer = 1)
- ***************************************************************************/
-/* HIF_MSPI :: TXRAM03 :: reserved0 [31:08] */
-#define BCHP_HIF_MSPI_TXRAM03_reserved0_MASK 0xffffff00
-#define BCHP_HIF_MSPI_TXRAM03_reserved0_SHIFT 8
-
-/* HIF_MSPI :: TXRAM03 :: txram [07:00] */
-#define BCHP_HIF_MSPI_TXRAM03_txram_MASK 0x000000ff
-#define BCHP_HIF_MSPI_TXRAM03_txram_SHIFT 0
-
-/***************************************************************************
- *TXRAM04 - Most significant byte of TXRAM[2] (queue pointer = 2)
- ***************************************************************************/
-/* HIF_MSPI :: TXRAM04 :: reserved0 [31:08] */
-#define BCHP_HIF_MSPI_TXRAM04_reserved0_MASK 0xffffff00
-#define BCHP_HIF_MSPI_TXRAM04_reserved0_SHIFT 8
-
-/* HIF_MSPI :: TXRAM04 :: txram [07:00] */
-#define BCHP_HIF_MSPI_TXRAM04_txram_MASK 0x000000ff
-#define BCHP_HIF_MSPI_TXRAM04_txram_SHIFT 0
-
-/***************************************************************************
- *TXRAM05 - Least significant byte of TXRAM[2] (queue pointer = 2)
- ***************************************************************************/
-/* HIF_MSPI :: TXRAM05 :: reserved0 [31:08] */
-#define BCHP_HIF_MSPI_TXRAM05_reserved0_MASK 0xffffff00
-#define BCHP_HIF_MSPI_TXRAM05_reserved0_SHIFT 8
-
-/* HIF_MSPI :: TXRAM05 :: txram [07:00] */
-#define BCHP_HIF_MSPI_TXRAM05_txram_MASK 0x000000ff
-#define BCHP_HIF_MSPI_TXRAM05_txram_SHIFT 0
-
-/***************************************************************************
- *TXRAM06 - Most significant byte of TXRAM[3] (queue pointer = 3)
- ***************************************************************************/
-/* HIF_MSPI :: TXRAM06 :: reserved0 [31:08] */
-#define BCHP_HIF_MSPI_TXRAM06_reserved0_MASK 0xffffff00
-#define BCHP_HIF_MSPI_TXRAM06_reserved0_SHIFT 8
-
-/* HIF_MSPI :: TXRAM06 :: txram [07:00] */
-#define BCHP_HIF_MSPI_TXRAM06_txram_MASK 0x000000ff
-#define BCHP_HIF_MSPI_TXRAM06_txram_SHIFT 0
-
-/***************************************************************************
- *TXRAM07 - Least significant byte of TXRAM[3] (queue pointer = 3)
- ***************************************************************************/
-/* HIF_MSPI :: TXRAM07 :: reserved0 [31:08] */
-#define BCHP_HIF_MSPI_TXRAM07_reserved0_MASK 0xffffff00
-#define BCHP_HIF_MSPI_TXRAM07_reserved0_SHIFT 8
-
-/* HIF_MSPI :: TXRAM07 :: txram [07:00] */
-#define BCHP_HIF_MSPI_TXRAM07_txram_MASK 0x000000ff
-#define BCHP_HIF_MSPI_TXRAM07_txram_SHIFT 0
-
-/***************************************************************************
- *TXRAM08 - Most significant byte of TXRAM[4] (queue pointer = 4)
- ***************************************************************************/
-/* HIF_MSPI :: TXRAM08 :: reserved0 [31:08] */
-#define BCHP_HIF_MSPI_TXRAM08_reserved0_MASK 0xffffff00
-#define BCHP_HIF_MSPI_TXRAM08_reserved0_SHIFT 8
-
-/* HIF_MSPI :: TXRAM08 :: txram [07:00] */
-#define BCHP_HIF_MSPI_TXRAM08_txram_MASK 0x000000ff
-#define BCHP_HIF_MSPI_TXRAM08_txram_SHIFT 0
-
-/***************************************************************************
- *TXRAM09 - Least significant byte of TXRAM[4] (queue pointer = 4)
- ***************************************************************************/
-/* HIF_MSPI :: TXRAM09 :: reserved0 [31:08] */
-#define BCHP_HIF_MSPI_TXRAM09_reserved0_MASK 0xffffff00
-#define BCHP_HIF_MSPI_TXRAM09_reserved0_SHIFT 8
-
-/* HIF_MSPI :: TXRAM09 :: txram [07:00] */
-#define BCHP_HIF_MSPI_TXRAM09_txram_MASK 0x000000ff
-#define BCHP_HIF_MSPI_TXRAM09_txram_SHIFT 0
-
-/***************************************************************************
- *TXRAM10 - Most significant byte of TXRAM[5] (queue pointer = 5)
- ***************************************************************************/
-/* HIF_MSPI :: TXRAM10 :: reserved0 [31:08] */
-#define BCHP_HIF_MSPI_TXRAM10_reserved0_MASK 0xffffff00
-#define BCHP_HIF_MSPI_TXRAM10_reserved0_SHIFT 8
-
-/* HIF_MSPI :: TXRAM10 :: txram [07:00] */
-#define BCHP_HIF_MSPI_TXRAM10_txram_MASK 0x000000ff
-#define BCHP_HIF_MSPI_TXRAM10_txram_SHIFT 0
-
-/***************************************************************************
- *TXRAM11 - Least significant byte of TXRAM[5] (queue pointer = 5)
- ***************************************************************************/
-/* HIF_MSPI :: TXRAM11 :: reserved0 [31:08] */
-#define BCHP_HIF_MSPI_TXRAM11_reserved0_MASK 0xffffff00
-#define BCHP_HIF_MSPI_TXRAM11_reserved0_SHIFT 8
-
-/* HIF_MSPI :: TXRAM11 :: txram [07:00] */
-#define BCHP_HIF_MSPI_TXRAM11_txram_MASK 0x000000ff
-#define BCHP_HIF_MSPI_TXRAM11_txram_SHIFT 0
-
-/***************************************************************************
- *TXRAM12 - Most significant byte of TXRAM[6] (queue pointer = 6)
- ***************************************************************************/
-/* HIF_MSPI :: TXRAM12 :: reserved0 [31:08] */
-#define BCHP_HIF_MSPI_TXRAM12_reserved0_MASK 0xffffff00
-#define BCHP_HIF_MSPI_TXRAM12_reserved0_SHIFT 8
-
-/* HIF_MSPI :: TXRAM12 :: txram [07:00] */
-#define BCHP_HIF_MSPI_TXRAM12_txram_MASK 0x000000ff
-#define BCHP_HIF_MSPI_TXRAM12_txram_SHIFT 0
-
-/***************************************************************************
- *TXRAM13 - Least significant byte of TXRAM[6] (queue pointer = 6)
- ***************************************************************************/
-/* HIF_MSPI :: TXRAM13 :: reserved0 [31:08] */
-#define BCHP_HIF_MSPI_TXRAM13_reserved0_MASK 0xffffff00
-#define BCHP_HIF_MSPI_TXRAM13_reserved0_SHIFT 8
-
-/* HIF_MSPI :: TXRAM13 :: txram [07:00] */
-#define BCHP_HIF_MSPI_TXRAM13_txram_MASK 0x000000ff
-#define BCHP_HIF_MSPI_TXRAM13_txram_SHIFT 0
-
-/***************************************************************************
- *TXRAM14 - Most significant byte of TXRAM[7] (queue pointer = 7)
- ***************************************************************************/
-/* HIF_MSPI :: TXRAM14 :: reserved0 [31:08] */
-#define BCHP_HIF_MSPI_TXRAM14_reserved0_MASK 0xffffff00
-#define BCHP_HIF_MSPI_TXRAM14_reserved0_SHIFT 8
-
-/* HIF_MSPI :: TXRAM14 :: txram [07:00] */
-#define BCHP_HIF_MSPI_TXRAM14_txram_MASK 0x000000ff
-#define BCHP_HIF_MSPI_TXRAM14_txram_SHIFT 0
-
-/***************************************************************************
- *TXRAM15 - Least significant byte of TXRAM[7] (queue pointer = 7)
- ***************************************************************************/
-/* HIF_MSPI :: TXRAM15 :: reserved0 [31:08] */
-#define BCHP_HIF_MSPI_TXRAM15_reserved0_MASK 0xffffff00
-#define BCHP_HIF_MSPI_TXRAM15_reserved0_SHIFT 8
-
-/* HIF_MSPI :: TXRAM15 :: txram [07:00] */
-#define BCHP_HIF_MSPI_TXRAM15_txram_MASK 0x000000ff
-#define BCHP_HIF_MSPI_TXRAM15_txram_SHIFT 0
-
-/***************************************************************************
- *TXRAM16 - Most significant byte of TXRAM[8] (queue pointer = 8)
- ***************************************************************************/
-/* HIF_MSPI :: TXRAM16 :: reserved0 [31:08] */
-#define BCHP_HIF_MSPI_TXRAM16_reserved0_MASK 0xffffff00
-#define BCHP_HIF_MSPI_TXRAM16_reserved0_SHIFT 8
-
-/* HIF_MSPI :: TXRAM16 :: txram [07:00] */
-#define BCHP_HIF_MSPI_TXRAM16_txram_MASK 0x000000ff
-#define BCHP_HIF_MSPI_TXRAM16_txram_SHIFT 0
-
-/***************************************************************************
- *TXRAM17 - Least significant byte of TXRAM[8] (queue pointer = 8)
- ***************************************************************************/
-/* HIF_MSPI :: TXRAM17 :: reserved0 [31:08] */
-#define BCHP_HIF_MSPI_TXRAM17_reserved0_MASK 0xffffff00
-#define BCHP_HIF_MSPI_TXRAM17_reserved0_SHIFT 8
-
-/* HIF_MSPI :: TXRAM17 :: txram [07:00] */
-#define BCHP_HIF_MSPI_TXRAM17_txram_MASK 0x000000ff
-#define BCHP_HIF_MSPI_TXRAM17_txram_SHIFT 0
-
-/***************************************************************************
- *TXRAM18 - Most significant byte of TXRAM[9] (queue pointer = 9)
- ***************************************************************************/
-/* HIF_MSPI :: TXRAM18 :: reserved0 [31:08] */
-#define BCHP_HIF_MSPI_TXRAM18_reserved0_MASK 0xffffff00
-#define BCHP_HIF_MSPI_TXRAM18_reserved0_SHIFT 8
-
-/* HIF_MSPI :: TXRAM18 :: txram [07:00] */
-#define BCHP_HIF_MSPI_TXRAM18_txram_MASK 0x000000ff
-#define BCHP_HIF_MSPI_TXRAM18_txram_SHIFT 0
-
-/***************************************************************************
- *TXRAM19 - Least significant byte of TXRAM[9] (queue pointer = 9)
- ***************************************************************************/
-/* HIF_MSPI :: TXRAM19 :: reserved0 [31:08] */
-#define BCHP_HIF_MSPI_TXRAM19_reserved0_MASK 0xffffff00
-#define BCHP_HIF_MSPI_TXRAM19_reserved0_SHIFT 8
-
-/* HIF_MSPI :: TXRAM19 :: txram [07:00] */
-#define BCHP_HIF_MSPI_TXRAM19_txram_MASK 0x000000ff
-#define BCHP_HIF_MSPI_TXRAM19_txram_SHIFT 0
-
-/***************************************************************************
- *TXRAM20 - Most significant byte of TXRAM[10] (queue pointer = 10)
- ***************************************************************************/
-/* HIF_MSPI :: TXRAM20 :: reserved0 [31:08] */
-#define BCHP_HIF_MSPI_TXRAM20_reserved0_MASK 0xffffff00
-#define BCHP_HIF_MSPI_TXRAM20_reserved0_SHIFT 8
-
-/* HIF_MSPI :: TXRAM20 :: txram [07:00] */
-#define BCHP_HIF_MSPI_TXRAM20_txram_MASK 0x000000ff
-#define BCHP_HIF_MSPI_TXRAM20_txram_SHIFT 0
-
-/***************************************************************************
- *TXRAM21 - Least significant byte of TXRAM[10] (queue pointer = 10)
- ***************************************************************************/
-/* HIF_MSPI :: TXRAM21 :: reserved0 [31:08] */
-#define BCHP_HIF_MSPI_TXRAM21_reserved0_MASK 0xffffff00
-#define BCHP_HIF_MSPI_TXRAM21_reserved0_SHIFT 8
-
-/* HIF_MSPI :: TXRAM21 :: txram [07:00] */
-#define BCHP_HIF_MSPI_TXRAM21_txram_MASK 0x000000ff
-#define BCHP_HIF_MSPI_TXRAM21_txram_SHIFT 0
-
-/***************************************************************************
- *TXRAM22 - Most significant byte of TXRAM[11] (queue pointer = 11)
- ***************************************************************************/
-/* HIF_MSPI :: TXRAM22 :: reserved0 [31:08] */
-#define BCHP_HIF_MSPI_TXRAM22_reserved0_MASK 0xffffff00
-#define BCHP_HIF_MSPI_TXRAM22_reserved0_SHIFT 8
-
-/* HIF_MSPI :: TXRAM22 :: txram [07:00] */
-#define BCHP_HIF_MSPI_TXRAM22_txram_MASK 0x000000ff
-#define BCHP_HIF_MSPI_TXRAM22_txram_SHIFT 0
-
-/***************************************************************************
- *TXRAM23 - Least significant byte of TXRAM[11] (queue pointer = 11)
- ***************************************************************************/
-/* HIF_MSPI :: TXRAM23 :: reserved0 [31:08] */
-#define BCHP_HIF_MSPI_TXRAM23_reserved0_MASK 0xffffff00
-#define BCHP_HIF_MSPI_TXRAM23_reserved0_SHIFT 8
-
-/* HIF_MSPI :: TXRAM23 :: txram [07:00] */
-#define BCHP_HIF_MSPI_TXRAM23_txram_MASK 0x000000ff
-#define BCHP_HIF_MSPI_TXRAM23_txram_SHIFT 0
-
-/***************************************************************************
- *TXRAM24 - Most significant byte of TXRAM[12] (queue pointer = 12)
- ***************************************************************************/
-/* HIF_MSPI :: TXRAM24 :: reserved0 [31:08] */
-#define BCHP_HIF_MSPI_TXRAM24_reserved0_MASK 0xffffff00
-#define BCHP_HIF_MSPI_TXRAM24_reserved0_SHIFT 8
-
-/* HIF_MSPI :: TXRAM24 :: txram [07:00] */
-#define BCHP_HIF_MSPI_TXRAM24_txram_MASK 0x000000ff
-#define BCHP_HIF_MSPI_TXRAM24_txram_SHIFT 0
-
-/***************************************************************************
- *TXRAM25 - Least significant byte of TXRAM[12] (queue pointer = 12)
- ***************************************************************************/
-/* HIF_MSPI :: TXRAM25 :: reserved0 [31:08] */
-#define BCHP_HIF_MSPI_TXRAM25_reserved0_MASK 0xffffff00
-#define BCHP_HIF_MSPI_TXRAM25_reserved0_SHIFT 8
-
-/* HIF_MSPI :: TXRAM25 :: txram [07:00] */
-#define BCHP_HIF_MSPI_TXRAM25_txram_MASK 0x000000ff
-#define BCHP_HIF_MSPI_TXRAM25_txram_SHIFT 0
-
-/***************************************************************************
- *TXRAM26 - Most significant byte of TXRAM[13] (queue pointer = 13)
- ***************************************************************************/
-/* HIF_MSPI :: TXRAM26 :: reserved0 [31:08] */
-#define BCHP_HIF_MSPI_TXRAM26_reserved0_MASK 0xffffff00
-#define BCHP_HIF_MSPI_TXRAM26_reserved0_SHIFT 8
-
-/* HIF_MSPI :: TXRAM26 :: txram [07:00] */
-#define BCHP_HIF_MSPI_TXRAM26_txram_MASK 0x000000ff
-#define BCHP_HIF_MSPI_TXRAM26_txram_SHIFT 0
-
-/***************************************************************************
- *TXRAM27 - Least significant byte of TXRAM[13] (queue pointer = 13)
- ***************************************************************************/
-/* HIF_MSPI :: TXRAM27 :: reserved0 [31:08] */
-#define BCHP_HIF_MSPI_TXRAM27_reserved0_MASK 0xffffff00
-#define BCHP_HIF_MSPI_TXRAM27_reserved0_SHIFT 8
-
-/* HIF_MSPI :: TXRAM27 :: txram [07:00] */
-#define BCHP_HIF_MSPI_TXRAM27_txram_MASK 0x000000ff
-#define BCHP_HIF_MSPI_TXRAM27_txram_SHIFT 0
-
-/***************************************************************************
- *TXRAM28 - Most significant byte of TXRAM[14] (queue pointer = 14)
- ***************************************************************************/
-/* HIF_MSPI :: TXRAM28 :: reserved0 [31:08] */
-#define BCHP_HIF_MSPI_TXRAM28_reserved0_MASK 0xffffff00
-#define BCHP_HIF_MSPI_TXRAM28_reserved0_SHIFT 8
-
-/* HIF_MSPI :: TXRAM28 :: txram [07:00] */
-#define BCHP_HIF_MSPI_TXRAM28_txram_MASK 0x000000ff
-#define BCHP_HIF_MSPI_TXRAM28_txram_SHIFT 0
-
-/***************************************************************************
- *TXRAM29 - Least significant byte of TXRAM[14] (queue pointer = 14)
- ***************************************************************************/
-/* HIF_MSPI :: TXRAM29 :: reserved0 [31:08] */
-#define BCHP_HIF_MSPI_TXRAM29_reserved0_MASK 0xffffff00
-#define BCHP_HIF_MSPI_TXRAM29_reserved0_SHIFT 8
-
-/* HIF_MSPI :: TXRAM29 :: txram [07:00] */
-#define BCHP_HIF_MSPI_TXRAM29_txram_MASK 0x000000ff
-#define BCHP_HIF_MSPI_TXRAM29_txram_SHIFT 0
-
-/***************************************************************************
- *TXRAM30 - Most significant byte of TXRAM[15] (queue pointer = 15)
- ***************************************************************************/
-/* HIF_MSPI :: TXRAM30 :: reserved0 [31:08] */
-#define BCHP_HIF_MSPI_TXRAM30_reserved0_MASK 0xffffff00
-#define BCHP_HIF_MSPI_TXRAM30_reserved0_SHIFT 8
-
-/* HIF_MSPI :: TXRAM30 :: txram [07:00] */
-#define BCHP_HIF_MSPI_TXRAM30_txram_MASK 0x000000ff
-#define BCHP_HIF_MSPI_TXRAM30_txram_SHIFT 0
-
-/***************************************************************************
- *TXRAM31 - Least significant byte of TXRAM[15] (queue pointer = 15)
- ***************************************************************************/
-/* HIF_MSPI :: TXRAM31 :: reserved0 [31:08] */
-#define BCHP_HIF_MSPI_TXRAM31_reserved0_MASK 0xffffff00
-#define BCHP_HIF_MSPI_TXRAM31_reserved0_SHIFT 8
-
-/* HIF_MSPI :: TXRAM31 :: txram [07:00] */
-#define BCHP_HIF_MSPI_TXRAM31_txram_MASK 0x000000ff
-#define BCHP_HIF_MSPI_TXRAM31_txram_SHIFT 0
-
-/***************************************************************************
- *RXRAM00 - Most significant byte of RXRAM[0] (queue pointer = 0)
- ***************************************************************************/
-/* HIF_MSPI :: RXRAM00 :: reserved0 [31:08] */
-#define BCHP_HIF_MSPI_RXRAM00_reserved0_MASK 0xffffff00
-#define BCHP_HIF_MSPI_RXRAM00_reserved0_SHIFT 8
-
-/* HIF_MSPI :: RXRAM00 :: rxram [07:00] */
-#define BCHP_HIF_MSPI_RXRAM00_rxram_MASK 0x000000ff
-#define BCHP_HIF_MSPI_RXRAM00_rxram_SHIFT 0
-
-/***************************************************************************
- *RXRAM01 - Least significant byte of RXRAM[0] (queue pointer = 0)
- ***************************************************************************/
-/* HIF_MSPI :: RXRAM01 :: reserved0 [31:08] */
-#define BCHP_HIF_MSPI_RXRAM01_reserved0_MASK 0xffffff00
-#define BCHP_HIF_MSPI_RXRAM01_reserved0_SHIFT 8
-
-/* HIF_MSPI :: RXRAM01 :: rxram [07:00] */
-#define BCHP_HIF_MSPI_RXRAM01_rxram_MASK 0x000000ff
-#define BCHP_HIF_MSPI_RXRAM01_rxram_SHIFT 0
-
-/***************************************************************************
- *RXRAM02 - Most significant byte of RXRAM[1] (queue pointer = 1)
- ***************************************************************************/
-/* HIF_MSPI :: RXRAM02 :: reserved0 [31:08] */
-#define BCHP_HIF_MSPI_RXRAM02_reserved0_MASK 0xffffff00
-#define BCHP_HIF_MSPI_RXRAM02_reserved0_SHIFT 8
-
-/* HIF_MSPI :: RXRAM02 :: rxram [07:00] */
-#define BCHP_HIF_MSPI_RXRAM02_rxram_MASK 0x000000ff
-#define BCHP_HIF_MSPI_RXRAM02_rxram_SHIFT 0
-
-/***************************************************************************
- *RXRAM03 - Least significant byte of RXRAM[1] (queue pointer = 1)
- ***************************************************************************/
-/* HIF_MSPI :: RXRAM03 :: reserved0 [31:08] */
-#define BCHP_HIF_MSPI_RXRAM03_reserved0_MASK 0xffffff00
-#define BCHP_HIF_MSPI_RXRAM03_reserved0_SHIFT 8
-
-/* HIF_MSPI :: RXRAM03 :: rxram [07:00] */
-#define BCHP_HIF_MSPI_RXRAM03_rxram_MASK 0x000000ff
-#define BCHP_HIF_MSPI_RXRAM03_rxram_SHIFT 0
-
-/***************************************************************************
- *RXRAM04 - Most significant byte of RXRAM[2] (queue pointer = 2)
- ***************************************************************************/
-/* HIF_MSPI :: RXRAM04 :: reserved0 [31:08] */
-#define BCHP_HIF_MSPI_RXRAM04_reserved0_MASK 0xffffff00
-#define BCHP_HIF_MSPI_RXRAM04_reserved0_SHIFT 8
-
-/* HIF_MSPI :: RXRAM04 :: rxram [07:00] */
-#define BCHP_HIF_MSPI_RXRAM04_rxram_MASK 0x000000ff
-#define BCHP_HIF_MSPI_RXRAM04_rxram_SHIFT 0
-
-/***************************************************************************
- *RXRAM05 - Least significant byte of RXRAM[2] (queue pointer = 2)
- ***************************************************************************/
-/* HIF_MSPI :: RXRAM05 :: reserved0 [31:08] */
-#define BCHP_HIF_MSPI_RXRAM05_reserved0_MASK 0xffffff00
-#define BCHP_HIF_MSPI_RXRAM05_reserved0_SHIFT 8
-
-/* HIF_MSPI :: RXRAM05 :: rxram [07:00] */
-#define BCHP_HIF_MSPI_RXRAM05_rxram_MASK 0x000000ff
-#define BCHP_HIF_MSPI_RXRAM05_rxram_SHIFT 0
-
-/***************************************************************************
- *RXRAM06 - Most significant byte of RXRAM[3] (queue pointer = 3)
- ***************************************************************************/
-/* HIF_MSPI :: RXRAM06 :: reserved0 [31:08] */
-#define BCHP_HIF_MSPI_RXRAM06_reserved0_MASK 0xffffff00
-#define BCHP_HIF_MSPI_RXRAM06_reserved0_SHIFT 8
-
-/* HIF_MSPI :: RXRAM06 :: rxram [07:00] */
-#define BCHP_HIF_MSPI_RXRAM06_rxram_MASK 0x000000ff
-#define BCHP_HIF_MSPI_RXRAM06_rxram_SHIFT 0
-
-/***************************************************************************
- *RXRAM07 - Least significant byte of RXRAM[3] (queue pointer = 3)
- ***************************************************************************/
-/* HIF_MSPI :: RXRAM07 :: reserved0 [31:08] */
-#define BCHP_HIF_MSPI_RXRAM07_reserved0_MASK 0xffffff00
-#define BCHP_HIF_MSPI_RXRAM07_reserved0_SHIFT 8
-
-/* HIF_MSPI :: RXRAM07 :: rxram [07:00] */
-#define BCHP_HIF_MSPI_RXRAM07_rxram_MASK 0x000000ff
-#define BCHP_HIF_MSPI_RXRAM07_rxram_SHIFT 0
-
-/***************************************************************************
- *RXRAM08 - Most significant byte of RXRAM[4] (queue pointer = 4)
- ***************************************************************************/
-/* HIF_MSPI :: RXRAM08 :: reserved0 [31:08] */
-#define BCHP_HIF_MSPI_RXRAM08_reserved0_MASK 0xffffff00
-#define BCHP_HIF_MSPI_RXRAM08_reserved0_SHIFT 8
-
-/* HIF_MSPI :: RXRAM08 :: rxram [07:00] */
-#define BCHP_HIF_MSPI_RXRAM08_rxram_MASK 0x000000ff
-#define BCHP_HIF_MSPI_RXRAM08_rxram_SHIFT 0
-
-/***************************************************************************
- *RXRAM09 - Least significant byte of RXRAM[4] (queue pointer = 4)
- ***************************************************************************/
-/* HIF_MSPI :: RXRAM09 :: reserved0 [31:08] */
-#define BCHP_HIF_MSPI_RXRAM09_reserved0_MASK 0xffffff00
-#define BCHP_HIF_MSPI_RXRAM09_reserved0_SHIFT 8
-
-/* HIF_MSPI :: RXRAM09 :: rxram [07:00] */
-#define BCHP_HIF_MSPI_RXRAM09_rxram_MASK 0x000000ff
-#define BCHP_HIF_MSPI_RXRAM09_rxram_SHIFT 0
-
-/***************************************************************************
- *RXRAM10 - Most significant byte of RXRAM[5] (queue pointer = 5)
- ***************************************************************************/
-/* HIF_MSPI :: RXRAM10 :: reserved0 [31:08] */
-#define BCHP_HIF_MSPI_RXRAM10_reserved0_MASK 0xffffff00
-#define BCHP_HIF_MSPI_RXRAM10_reserved0_SHIFT 8
-
-/* HIF_MSPI :: RXRAM10 :: rxram [07:00] */
-#define BCHP_HIF_MSPI_RXRAM10_rxram_MASK 0x000000ff
-#define BCHP_HIF_MSPI_RXRAM10_rxram_SHIFT 0
-
-/***************************************************************************
- *RXRAM11 - Least significant byte of RXRAM[5] (queue pointer = 5)
- ***************************************************************************/
-/* HIF_MSPI :: RXRAM11 :: reserved0 [31:08] */
-#define BCHP_HIF_MSPI_RXRAM11_reserved0_MASK 0xffffff00
-#define BCHP_HIF_MSPI_RXRAM11_reserved0_SHIFT 8
-
-/* HIF_MSPI :: RXRAM11 :: rxram [07:00] */
-#define BCHP_HIF_MSPI_RXRAM11_rxram_MASK 0x000000ff
-#define BCHP_HIF_MSPI_RXRAM11_rxram_SHIFT 0
-
-/***************************************************************************
- *RXRAM12 - Most significant byte of RXRAM[6] (queue pointer = 6)
- ***************************************************************************/
-/* HIF_MSPI :: RXRAM12 :: reserved0 [31:08] */
-#define BCHP_HIF_MSPI_RXRAM12_reserved0_MASK 0xffffff00
-#define BCHP_HIF_MSPI_RXRAM12_reserved0_SHIFT 8
-
-/* HIF_MSPI :: RXRAM12 :: rxram [07:00] */
-#define BCHP_HIF_MSPI_RXRAM12_rxram_MASK 0x000000ff
-#define BCHP_HIF_MSPI_RXRAM12_rxram_SHIFT 0
-
-/***************************************************************************
- *RXRAM13 - Least significant byte of RXRAM[6] (queue pointer = 6)
- ***************************************************************************/
-/* HIF_MSPI :: RXRAM13 :: reserved0 [31:08] */
-#define BCHP_HIF_MSPI_RXRAM13_reserved0_MASK 0xffffff00
-#define BCHP_HIF_MSPI_RXRAM13_reserved0_SHIFT 8
-
-/* HIF_MSPI :: RXRAM13 :: rxram [07:00] */
-#define BCHP_HIF_MSPI_RXRAM13_rxram_MASK 0x000000ff
-#define BCHP_HIF_MSPI_RXRAM13_rxram_SHIFT 0
-
-/***************************************************************************
- *RXRAM14 - Most significant byte of RXRAM[7] (queue pointer = 7)
- ***************************************************************************/
-/* HIF_MSPI :: RXRAM14 :: reserved0 [31:08] */
-#define BCHP_HIF_MSPI_RXRAM14_reserved0_MASK 0xffffff00
-#define BCHP_HIF_MSPI_RXRAM14_reserved0_SHIFT 8
-
-/* HIF_MSPI :: RXRAM14 :: rxram [07:00] */
-#define BCHP_HIF_MSPI_RXRAM14_rxram_MASK 0x000000ff
-#define BCHP_HIF_MSPI_RXRAM14_rxram_SHIFT 0
-
-/***************************************************************************
- *RXRAM15 - Least significant byte of RXRAM[7] (queue pointer = 7)
- ***************************************************************************/
-/* HIF_MSPI :: RXRAM15 :: reserved0 [31:08] */
-#define BCHP_HIF_MSPI_RXRAM15_reserved0_MASK 0xffffff00
-#define BCHP_HIF_MSPI_RXRAM15_reserved0_SHIFT 8
-
-/* HIF_MSPI :: RXRAM15 :: rxram [07:00] */
-#define BCHP_HIF_MSPI_RXRAM15_rxram_MASK 0x000000ff
-#define BCHP_HIF_MSPI_RXRAM15_rxram_SHIFT 0
-
-/***************************************************************************
- *RXRAM16 - Most significant byte of RXRAM[8] (queue pointer = 8)
- ***************************************************************************/
-/* HIF_MSPI :: RXRAM16 :: reserved0 [31:08] */
-#define BCHP_HIF_MSPI_RXRAM16_reserved0_MASK 0xffffff00
-#define BCHP_HIF_MSPI_RXRAM16_reserved0_SHIFT 8
-
-/* HIF_MSPI :: RXRAM16 :: rxram [07:00] */
-#define BCHP_HIF_MSPI_RXRAM16_rxram_MASK 0x000000ff
-#define BCHP_HIF_MSPI_RXRAM16_rxram_SHIFT 0
-
-/***************************************************************************
- *RXRAM17 - Least significant byte of RXRAM[8] (queue pointer = 8)
- ***************************************************************************/
-/* HIF_MSPI :: RXRAM17 :: reserved0 [31:08] */
-#define BCHP_HIF_MSPI_RXRAM17_reserved0_MASK 0xffffff00
-#define BCHP_HIF_MSPI_RXRAM17_reserved0_SHIFT 8
-
-/* HIF_MSPI :: RXRAM17 :: rxram [07:00] */
-#define BCHP_HIF_MSPI_RXRAM17_rxram_MASK 0x000000ff
-#define BCHP_HIF_MSPI_RXRAM17_rxram_SHIFT 0
-
-/***************************************************************************
- *RXRAM18 - Most significant byte of RXRAM[9] (queue pointer = 9)
- ***************************************************************************/
-/* HIF_MSPI :: RXRAM18 :: reserved0 [31:08] */
-#define BCHP_HIF_MSPI_RXRAM18_reserved0_MASK 0xffffff00
-#define BCHP_HIF_MSPI_RXRAM18_reserved0_SHIFT 8
-
-/* HIF_MSPI :: RXRAM18 :: rxram [07:00] */
-#define BCHP_HIF_MSPI_RXRAM18_rxram_MASK 0x000000ff
-#define BCHP_HIF_MSPI_RXRAM18_rxram_SHIFT 0
-
-/***************************************************************************
- *RXRAM19 - Least significant byte of RXRAM[9] (queue pointer = 9)
- ***************************************************************************/
-/* HIF_MSPI :: RXRAM19 :: reserved0 [31:08] */
-#define BCHP_HIF_MSPI_RXRAM19_reserved0_MASK 0xffffff00
-#define BCHP_HIF_MSPI_RXRAM19_reserved0_SHIFT 8
-
-/* HIF_MSPI :: RXRAM19 :: rxram [07:00] */
-#define BCHP_HIF_MSPI_RXRAM19_rxram_MASK 0x000000ff
-#define BCHP_HIF_MSPI_RXRAM19_rxram_SHIFT 0
-
-/***************************************************************************
- *RXRAM20 - Most significant byte of RXRAM[10] (queue pointer = 10)
- ***************************************************************************/
-/* HIF_MSPI :: RXRAM20 :: reserved0 [31:08] */
-#define BCHP_HIF_MSPI_RXRAM20_reserved0_MASK 0xffffff00
-#define BCHP_HIF_MSPI_RXRAM20_reserved0_SHIFT 8
-
-/* HIF_MSPI :: RXRAM20 :: rxram [07:00] */
-#define BCHP_HIF_MSPI_RXRAM20_rxram_MASK 0x000000ff
-#define BCHP_HIF_MSPI_RXRAM20_rxram_SHIFT 0
-
-/***************************************************************************
- *RXRAM21 - Least significant byte of RXRAM[10] (queue pointer = 10)
- ***************************************************************************/
-/* HIF_MSPI :: RXRAM21 :: reserved0 [31:08] */
-#define BCHP_HIF_MSPI_RXRAM21_reserved0_MASK 0xffffff00
-#define BCHP_HIF_MSPI_RXRAM21_reserved0_SHIFT 8
-
-/* HIF_MSPI :: RXRAM21 :: rxram [07:00] */
-#define BCHP_HIF_MSPI_RXRAM21_rxram_MASK 0x000000ff
-#define BCHP_HIF_MSPI_RXRAM21_rxram_SHIFT 0
-
-/***************************************************************************
- *RXRAM22 - Most significant byte of RXRAM[11] (queue pointer = 11)
- ***************************************************************************/
-/* HIF_MSPI :: RXRAM22 :: reserved0 [31:08] */
-#define BCHP_HIF_MSPI_RXRAM22_reserved0_MASK 0xffffff00
-#define BCHP_HIF_MSPI_RXRAM22_reserved0_SHIFT 8
-
-/* HIF_MSPI :: RXRAM22 :: rxram [07:00] */
-#define BCHP_HIF_MSPI_RXRAM22_rxram_MASK 0x000000ff
-#define BCHP_HIF_MSPI_RXRAM22_rxram_SHIFT 0
-
-/***************************************************************************
- *RXRAM23 - Least significant byte of RXRAM[11] (queue pointer = 11)
- ***************************************************************************/
-/* HIF_MSPI :: RXRAM23 :: reserved0 [31:08] */
-#define BCHP_HIF_MSPI_RXRAM23_reserved0_MASK 0xffffff00
-#define BCHP_HIF_MSPI_RXRAM23_reserved0_SHIFT 8
-
-/* HIF_MSPI :: RXRAM23 :: rxram [07:00] */
-#define BCHP_HIF_MSPI_RXRAM23_rxram_MASK 0x000000ff
-#define BCHP_HIF_MSPI_RXRAM23_rxram_SHIFT 0
-
-/***************************************************************************
- *RXRAM24 - Most significant byte of RXRAM[12] (queue pointer = 12)
- ***************************************************************************/
-/* HIF_MSPI :: RXRAM24 :: reserved0 [31:08] */
-#define BCHP_HIF_MSPI_RXRAM24_reserved0_MASK 0xffffff00
-#define BCHP_HIF_MSPI_RXRAM24_reserved0_SHIFT 8
-
-/* HIF_MSPI :: RXRAM24 :: rxram [07:00] */
-#define BCHP_HIF_MSPI_RXRAM24_rxram_MASK 0x000000ff
-#define BCHP_HIF_MSPI_RXRAM24_rxram_SHIFT 0
-
-/***************************************************************************
- *RXRAM25 - Least significant byte of RXRAM[12] (queue pointer = 12)
- ***************************************************************************/
-/* HIF_MSPI :: RXRAM25 :: reserved0 [31:08] */
-#define BCHP_HIF_MSPI_RXRAM25_reserved0_MASK 0xffffff00
-#define BCHP_HIF_MSPI_RXRAM25_reserved0_SHIFT 8
-
-/* HIF_MSPI :: RXRAM25 :: rxram [07:00] */
-#define BCHP_HIF_MSPI_RXRAM25_rxram_MASK 0x000000ff
-#define BCHP_HIF_MSPI_RXRAM25_rxram_SHIFT 0
-
-/***************************************************************************
- *RXRAM26 - Most significant byte of RXRAM[13] (queue pointer = 13)
- ***************************************************************************/
-/* HIF_MSPI :: RXRAM26 :: reserved0 [31:08] */
-#define BCHP_HIF_MSPI_RXRAM26_reserved0_MASK 0xffffff00
-#define BCHP_HIF_MSPI_RXRAM26_reserved0_SHIFT 8
-
-/* HIF_MSPI :: RXRAM26 :: rxram [07:00] */
-#define BCHP_HIF_MSPI_RXRAM26_rxram_MASK 0x000000ff
-#define BCHP_HIF_MSPI_RXRAM26_rxram_SHIFT 0
-
-/***************************************************************************
- *RXRAM27 - Least significant byte of RXRAM[13] (queue pointer = 13)
- ***************************************************************************/
-/* HIF_MSPI :: RXRAM27 :: reserved0 [31:08] */
-#define BCHP_HIF_MSPI_RXRAM27_reserved0_MASK 0xffffff00
-#define BCHP_HIF_MSPI_RXRAM27_reserved0_SHIFT 8
-
-/* HIF_MSPI :: RXRAM27 :: rxram [07:00] */
-#define BCHP_HIF_MSPI_RXRAM27_rxram_MASK 0x000000ff
-#define BCHP_HIF_MSPI_RXRAM27_rxram_SHIFT 0
-
-/***************************************************************************
- *RXRAM28 - Most significant byte of RXRAM[14] (queue pointer = 14)
- ***************************************************************************/
-/* HIF_MSPI :: RXRAM28 :: reserved0 [31:08] */
-#define BCHP_HIF_MSPI_RXRAM28_reserved0_MASK 0xffffff00
-#define BCHP_HIF_MSPI_RXRAM28_reserved0_SHIFT 8
-
-/* HIF_MSPI :: RXRAM28 :: rxram [07:00] */
-#define BCHP_HIF_MSPI_RXRAM28_rxram_MASK 0x000000ff
-#define BCHP_HIF_MSPI_RXRAM28_rxram_SHIFT 0
-
-/***************************************************************************
- *RXRAM29 - Least significant byte of RXRAM[14] (queue pointer = 14)
- ***************************************************************************/
-/* HIF_MSPI :: RXRAM29 :: reserved0 [31:08] */
-#define BCHP_HIF_MSPI_RXRAM29_reserved0_MASK 0xffffff00
-#define BCHP_HIF_MSPI_RXRAM29_reserved0_SHIFT 8
-
-/* HIF_MSPI :: RXRAM29 :: rxram [07:00] */
-#define BCHP_HIF_MSPI_RXRAM29_rxram_MASK 0x000000ff
-#define BCHP_HIF_MSPI_RXRAM29_rxram_SHIFT 0
-
-/***************************************************************************
- *RXRAM30 - Most significant byte of RXRAM[15] (queue pointer = 15)
- ***************************************************************************/
-/* HIF_MSPI :: RXRAM30 :: reserved0 [31:08] */
-#define BCHP_HIF_MSPI_RXRAM30_reserved0_MASK 0xffffff00
-#define BCHP_HIF_MSPI_RXRAM30_reserved0_SHIFT 8
-
-/* HIF_MSPI :: RXRAM30 :: rxram [07:00] */
-#define BCHP_HIF_MSPI_RXRAM30_rxram_MASK 0x000000ff
-#define BCHP_HIF_MSPI_RXRAM30_rxram_SHIFT 0
-
-/***************************************************************************
- *RXRAM31 - Least significant byte of RXRAM[15] (queue pointer = 15)
- ***************************************************************************/
-/* HIF_MSPI :: RXRAM31 :: reserved0 [31:08] */
-#define BCHP_HIF_MSPI_RXRAM31_reserved0_MASK 0xffffff00
-#define BCHP_HIF_MSPI_RXRAM31_reserved0_SHIFT 8
-
-/* HIF_MSPI :: RXRAM31 :: rxram [07:00] */
-#define BCHP_HIF_MSPI_RXRAM31_rxram_MASK 0x000000ff
-#define BCHP_HIF_MSPI_RXRAM31_rxram_SHIFT 0
-
-/***************************************************************************
- *CDRAM00 - 8-bit command (queue pointer = 0)
- ***************************************************************************/
-/* HIF_MSPI :: CDRAM00 :: reserved0 [31:09] */
-#define BCHP_HIF_MSPI_CDRAM00_reserved0_MASK 0xfffffe00
-#define BCHP_HIF_MSPI_CDRAM00_reserved0_SHIFT 9
-
-/* HIF_MSPI :: CDRAM00 :: cdram [08:00] */
-#define BCHP_HIF_MSPI_CDRAM00_cdram_MASK 0x000001ff
-#define BCHP_HIF_MSPI_CDRAM00_cdram_SHIFT 0
-
-/***************************************************************************
- *CDRAM01 - 8-bit command (queue pointer = 1)
- ***************************************************************************/
-/* HIF_MSPI :: CDRAM01 :: reserved0 [31:09] */
-#define BCHP_HIF_MSPI_CDRAM01_reserved0_MASK 0xfffffe00
-#define BCHP_HIF_MSPI_CDRAM01_reserved0_SHIFT 9
-
-/* HIF_MSPI :: CDRAM01 :: cdram [08:00] */
-#define BCHP_HIF_MSPI_CDRAM01_cdram_MASK 0x000001ff
-#define BCHP_HIF_MSPI_CDRAM01_cdram_SHIFT 0
-
-/***************************************************************************
- *CDRAM02 - 8-bit command (queue pointer = 2)
- ***************************************************************************/
-/* HIF_MSPI :: CDRAM02 :: reserved0 [31:09] */
-#define BCHP_HIF_MSPI_CDRAM02_reserved0_MASK 0xfffffe00
-#define BCHP_HIF_MSPI_CDRAM02_reserved0_SHIFT 9
-
-/* HIF_MSPI :: CDRAM02 :: cdram [08:00] */
-#define BCHP_HIF_MSPI_CDRAM02_cdram_MASK 0x000001ff
-#define BCHP_HIF_MSPI_CDRAM02_cdram_SHIFT 0
-
-/***************************************************************************
- *CDRAM03 - 8-bit command (queue pointer = 3)
- ***************************************************************************/
-/* HIF_MSPI :: CDRAM03 :: reserved0 [31:09] */
-#define BCHP_HIF_MSPI_CDRAM03_reserved0_MASK 0xfffffe00
-#define BCHP_HIF_MSPI_CDRAM03_reserved0_SHIFT 9
-
-/* HIF_MSPI :: CDRAM03 :: cdram [08:00] */
-#define BCHP_HIF_MSPI_CDRAM03_cdram_MASK 0x000001ff
-#define BCHP_HIF_MSPI_CDRAM03_cdram_SHIFT 0
-
-/***************************************************************************
- *CDRAM04 - 8-bit command (queue pointer = 4)
- ***************************************************************************/
-/* HIF_MSPI :: CDRAM04 :: reserved0 [31:09] */
-#define BCHP_HIF_MSPI_CDRAM04_reserved0_MASK 0xfffffe00
-#define BCHP_HIF_MSPI_CDRAM04_reserved0_SHIFT 9
-
-/* HIF_MSPI :: CDRAM04 :: cdram [08:00] */
-#define BCHP_HIF_MSPI_CDRAM04_cdram_MASK 0x000001ff
-#define BCHP_HIF_MSPI_CDRAM04_cdram_SHIFT 0
-
-/***************************************************************************
- *CDRAM05 - 8-bit command (queue pointer = 5)
- ***************************************************************************/
-/* HIF_MSPI :: CDRAM05 :: reserved0 [31:09] */
-#define BCHP_HIF_MSPI_CDRAM05_reserved0_MASK 0xfffffe00
-#define BCHP_HIF_MSPI_CDRAM05_reserved0_SHIFT 9
-
-/* HIF_MSPI :: CDRAM05 :: cdram [08:00] */
-#define BCHP_HIF_MSPI_CDRAM05_cdram_MASK 0x000001ff
-#define BCHP_HIF_MSPI_CDRAM05_cdram_SHIFT 0
-
-/***************************************************************************
- *CDRAM06 - 8-bit command (queue pointer = 6)
- ***************************************************************************/
-/* HIF_MSPI :: CDRAM06 :: reserved0 [31:09] */
-#define BCHP_HIF_MSPI_CDRAM06_reserved0_MASK 0xfffffe00
-#define BCHP_HIF_MSPI_CDRAM06_reserved0_SHIFT 9
-
-/* HIF_MSPI :: CDRAM06 :: cdram [08:00] */
-#define BCHP_HIF_MSPI_CDRAM06_cdram_MASK 0x000001ff
-#define BCHP_HIF_MSPI_CDRAM06_cdram_SHIFT 0
-
-/***************************************************************************
- *CDRAM07 - 8-bit command (queue pointer = 7)
- ***************************************************************************/
-/* HIF_MSPI :: CDRAM07 :: reserved0 [31:09] */
-#define BCHP_HIF_MSPI_CDRAM07_reserved0_MASK 0xfffffe00
-#define BCHP_HIF_MSPI_CDRAM07_reserved0_SHIFT 9
-
-/* HIF_MSPI :: CDRAM07 :: cdram [08:00] */
-#define BCHP_HIF_MSPI_CDRAM07_cdram_MASK 0x000001ff
-#define BCHP_HIF_MSPI_CDRAM07_cdram_SHIFT 0
-
-/***************************************************************************
- *CDRAM08 - 8-bit command (queue pointer = 8)
- ***************************************************************************/
-/* HIF_MSPI :: CDRAM08 :: reserved0 [31:09] */
-#define BCHP_HIF_MSPI_CDRAM08_reserved0_MASK 0xfffffe00
-#define BCHP_HIF_MSPI_CDRAM08_reserved0_SHIFT 9
-
-/* HIF_MSPI :: CDRAM08 :: cdram [08:00] */
-#define BCHP_HIF_MSPI_CDRAM08_cdram_MASK 0x000001ff
-#define BCHP_HIF_MSPI_CDRAM08_cdram_SHIFT 0
-
-/***************************************************************************
- *CDRAM09 - 8-bit command (queue pointer = 9)
- ***************************************************************************/
-/* HIF_MSPI :: CDRAM09 :: reserved0 [31:09] */
-#define BCHP_HIF_MSPI_CDRAM09_reserved0_MASK 0xfffffe00
-#define BCHP_HIF_MSPI_CDRAM09_reserved0_SHIFT 9
-
-/* HIF_MSPI :: CDRAM09 :: cdram [08:00] */
-#define BCHP_HIF_MSPI_CDRAM09_cdram_MASK 0x000001ff
-#define BCHP_HIF_MSPI_CDRAM09_cdram_SHIFT 0
-
-/***************************************************************************
- *CDRAM10 - 8-bit command (queue pointer = a)
- ***************************************************************************/
-/* HIF_MSPI :: CDRAM10 :: reserved0 [31:09] */
-#define BCHP_HIF_MSPI_CDRAM10_reserved0_MASK 0xfffffe00
-#define BCHP_HIF_MSPI_CDRAM10_reserved0_SHIFT 9
-
-/* HIF_MSPI :: CDRAM10 :: cdram [08:00] */
-#define BCHP_HIF_MSPI_CDRAM10_cdram_MASK 0x000001ff
-#define BCHP_HIF_MSPI_CDRAM10_cdram_SHIFT 0
-
-/***************************************************************************
- *CDRAM11 - 8-bit command (queue pointer = b)
- ***************************************************************************/
-/* HIF_MSPI :: CDRAM11 :: reserved0 [31:09] */
-#define BCHP_HIF_MSPI_CDRAM11_reserved0_MASK 0xfffffe00
-#define BCHP_HIF_MSPI_CDRAM11_reserved0_SHIFT 9
-
-/* HIF_MSPI :: CDRAM11 :: cdram [08:00] */
-#define BCHP_HIF_MSPI_CDRAM11_cdram_MASK 0x000001ff
-#define BCHP_HIF_MSPI_CDRAM11_cdram_SHIFT 0
-
-/***************************************************************************
- *CDRAM12 - 8-bit command (queue pointer = c)
- ***************************************************************************/
-/* HIF_MSPI :: CDRAM12 :: reserved0 [31:09] */
-#define BCHP_HIF_MSPI_CDRAM12_reserved0_MASK 0xfffffe00
-#define BCHP_HIF_MSPI_CDRAM12_reserved0_SHIFT 9
-
-/* HIF_MSPI :: CDRAM12 :: cdram [08:00] */
-#define BCHP_HIF_MSPI_CDRAM12_cdram_MASK 0x000001ff
-#define BCHP_HIF_MSPI_CDRAM12_cdram_SHIFT 0
-
-/***************************************************************************
- *CDRAM13 - 8-bit command (queue pointer = d)
- ***************************************************************************/
-/* HIF_MSPI :: CDRAM13 :: reserved0 [31:09] */
-#define BCHP_HIF_MSPI_CDRAM13_reserved0_MASK 0xfffffe00
-#define BCHP_HIF_MSPI_CDRAM13_reserved0_SHIFT 9
-
-/* HIF_MSPI :: CDRAM13 :: cdram [08:00] */
-#define BCHP_HIF_MSPI_CDRAM13_cdram_MASK 0x000001ff
-#define BCHP_HIF_MSPI_CDRAM13_cdram_SHIFT 0
-
-/***************************************************************************
- *CDRAM14 - 8-bit command (queue pointer = e)
- ***************************************************************************/
-/* HIF_MSPI :: CDRAM14 :: reserved0 [31:09] */
-#define BCHP_HIF_MSPI_CDRAM14_reserved0_MASK 0xfffffe00
-#define BCHP_HIF_MSPI_CDRAM14_reserved0_SHIFT 9
-
-/* HIF_MSPI :: CDRAM14 :: cdram [08:00] */
-#define BCHP_HIF_MSPI_CDRAM14_cdram_MASK 0x000001ff
-#define BCHP_HIF_MSPI_CDRAM14_cdram_SHIFT 0
-
-/***************************************************************************
- *CDRAM15 - 8-bit command (queue pointer = f)
- ***************************************************************************/
-/* HIF_MSPI :: CDRAM15 :: reserved0 [31:09] */
-#define BCHP_HIF_MSPI_CDRAM15_reserved0_MASK 0xfffffe00
-#define BCHP_HIF_MSPI_CDRAM15_reserved0_SHIFT 9
-
-/* HIF_MSPI :: CDRAM15 :: cdram [08:00] */
-#define BCHP_HIF_MSPI_CDRAM15_cdram_MASK 0x000001ff
-#define BCHP_HIF_MSPI_CDRAM15_cdram_SHIFT 0
-
-/***************************************************************************
- *WRITE_LOCK - Control bit to lock group of write commands
- ***************************************************************************/
-/* HIF_MSPI :: WRITE_LOCK :: reserved0 [31:01] */
-#define BCHP_HIF_MSPI_WRITE_LOCK_reserved0_MASK 0xfffffffe
-#define BCHP_HIF_MSPI_WRITE_LOCK_reserved0_SHIFT 1
-
-/* HIF_MSPI :: WRITE_LOCK :: WriteLock [00:00] */
-#define BCHP_HIF_MSPI_WRITE_LOCK_WriteLock_MASK 0x00000001
-#define BCHP_HIF_MSPI_WRITE_LOCK_WriteLock_SHIFT 0
-#define BCHP_HIF_MSPI_WRITE_LOCK_WriteLock_DEFAULT 0x00000000
-
-/***************************************************************************
- *DISABLE_FLUSH_GEN - Debug bit to mask the generation of flush signals from Mspi
- ***************************************************************************/
-/* HIF_MSPI :: DISABLE_FLUSH_GEN :: reserved0 [31:01] */
-#define BCHP_HIF_MSPI_DISABLE_FLUSH_GEN_reserved0_MASK 0xfffffffe
-#define BCHP_HIF_MSPI_DISABLE_FLUSH_GEN_reserved0_SHIFT 1
-
-/* HIF_MSPI :: DISABLE_FLUSH_GEN :: DisableFlushGen [00:00] */
-#define BCHP_HIF_MSPI_DISABLE_FLUSH_GEN_DisableFlushGen_MASK 0x00000001
-#define BCHP_HIF_MSPI_DISABLE_FLUSH_GEN_DisableFlushGen_SHIFT 0
-#define BCHP_HIF_MSPI_DISABLE_FLUSH_GEN_DisableFlushGen_DEFAULT 0x00000000
-
-#endif /* #ifndef BCHP_HIF_MSPI_H__ */
-
-/* End of File */
diff --git a/include/linux/brcmstb/7439a0/bchp_hif_spi_intr2.h b/include/linux/brcmstb/7439a0/bchp_hif_spi_intr2.h
deleted file mode 100644
index d027ca6..0000000
--- a/include/linux/brcmstb/7439a0/bchp_hif_spi_intr2.h
+++ /dev/null
@@ -1,564 +0,0 @@
-/***************************************************************************
- * Copyright (c) 1999-2012, Broadcom Corporation
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
- *
- * Module Description:
- * DO NOT EDIT THIS FILE DIRECTLY
- *
- * This module was generated magically with RDB from a source description
- * file. You must edit the source file for changes to be made to this file.
- *
- *
- * Date: Generated on Wed Oct 17 03:11:30 2012
- * MD5 Checksum d41d8cd98f00b204e9800998ecf8427e
- *
- * Compiled with: RDB Utility combo_header.pl
- * RDB Parser 3.0
- * unknown unknown
- * Perl Interpreter 5.008008
- * Operating System linux
- *
- * Revision History:
- *
- * $brcm_Log: $
- *
- ***************************************************************************/
-
-#ifndef BCHP_HIF_SPI_INTR2_H__
-#define BCHP_HIF_SPI_INTR2_H__
-
-/***************************************************************************
- *HIF_SPI_INTR2 - HIF Level 2 Interrupt Controller Registers for SPI
- ***************************************************************************/
-#define BCHP_HIF_SPI_INTR2_CPU_STATUS 0x00441a00 /* CPU interrupt Status Register */
-#define BCHP_HIF_SPI_INTR2_CPU_SET 0x00441a04 /* CPU interrupt Set Register */
-#define BCHP_HIF_SPI_INTR2_CPU_CLEAR 0x00441a08 /* CPU interrupt Clear Register */
-#define BCHP_HIF_SPI_INTR2_CPU_MASK_STATUS 0x00441a0c /* CPU interrupt Mask Status Register */
-#define BCHP_HIF_SPI_INTR2_CPU_MASK_SET 0x00441a10 /* CPU interrupt Mask Set Register */
-#define BCHP_HIF_SPI_INTR2_CPU_MASK_CLEAR 0x00441a14 /* CPU interrupt Mask Clear Register */
-#define BCHP_HIF_SPI_INTR2_PCI_STATUS 0x00441a18 /* PCI interrupt Status Register */
-#define BCHP_HIF_SPI_INTR2_PCI_SET 0x00441a1c /* PCI interrupt Set Register */
-#define BCHP_HIF_SPI_INTR2_PCI_CLEAR 0x00441a20 /* PCI interrupt Clear Register */
-#define BCHP_HIF_SPI_INTR2_PCI_MASK_STATUS 0x00441a24 /* PCI interrupt Mask Status Register */
-#define BCHP_HIF_SPI_INTR2_PCI_MASK_SET 0x00441a28 /* PCI interrupt Mask Set Register */
-#define BCHP_HIF_SPI_INTR2_PCI_MASK_CLEAR 0x00441a2c /* PCI interrupt Mask Clear Register */
-
-/***************************************************************************
- *CPU_STATUS - CPU interrupt Status Register
- ***************************************************************************/
-/* HIF_SPI_INTR2 :: CPU_STATUS :: reserved0 [31:07] */
-#define BCHP_HIF_SPI_INTR2_CPU_STATUS_reserved0_MASK 0xffffff80
-#define BCHP_HIF_SPI_INTR2_CPU_STATUS_reserved0_SHIFT 7
-
-/* HIF_SPI_INTR2 :: CPU_STATUS :: MSPI_HALTED [06:06] */
-#define BCHP_HIF_SPI_INTR2_CPU_STATUS_MSPI_HALTED_MASK 0x00000040
-#define BCHP_HIF_SPI_INTR2_CPU_STATUS_MSPI_HALTED_SHIFT 6
-#define BCHP_HIF_SPI_INTR2_CPU_STATUS_MSPI_HALTED_DEFAULT 0x00000000
-
-/* HIF_SPI_INTR2 :: CPU_STATUS :: MSPI_DONE [05:05] */
-#define BCHP_HIF_SPI_INTR2_CPU_STATUS_MSPI_DONE_MASK 0x00000020
-#define BCHP_HIF_SPI_INTR2_CPU_STATUS_MSPI_DONE_SHIFT 5
-#define BCHP_HIF_SPI_INTR2_CPU_STATUS_MSPI_DONE_DEFAULT 0x00000000
-
-/* HIF_SPI_INTR2 :: CPU_STATUS :: SPI_LR_OVERREAD [04:04] */
-#define BCHP_HIF_SPI_INTR2_CPU_STATUS_SPI_LR_OVERREAD_MASK 0x00000010
-#define BCHP_HIF_SPI_INTR2_CPU_STATUS_SPI_LR_OVERREAD_SHIFT 4
-#define BCHP_HIF_SPI_INTR2_CPU_STATUS_SPI_LR_OVERREAD_DEFAULT 0x00000000
-
-/* HIF_SPI_INTR2 :: CPU_STATUS :: SPI_LR_SESSION_DONE [03:03] */
-#define BCHP_HIF_SPI_INTR2_CPU_STATUS_SPI_LR_SESSION_DONE_MASK 0x00000008
-#define BCHP_HIF_SPI_INTR2_CPU_STATUS_SPI_LR_SESSION_DONE_SHIFT 3
-#define BCHP_HIF_SPI_INTR2_CPU_STATUS_SPI_LR_SESSION_DONE_DEFAULT 0x00000000
-
-/* HIF_SPI_INTR2 :: CPU_STATUS :: SPI_LR_IMPATIENT [02:02] */
-#define BCHP_HIF_SPI_INTR2_CPU_STATUS_SPI_LR_IMPATIENT_MASK 0x00000004
-#define BCHP_HIF_SPI_INTR2_CPU_STATUS_SPI_LR_IMPATIENT_SHIFT 2
-#define BCHP_HIF_SPI_INTR2_CPU_STATUS_SPI_LR_IMPATIENT_DEFAULT 0x00000000
-
-/* HIF_SPI_INTR2 :: CPU_STATUS :: SPI_LR_SESSION_ABORTED [01:01] */
-#define BCHP_HIF_SPI_INTR2_CPU_STATUS_SPI_LR_SESSION_ABORTED_MASK 0x00000002
-#define BCHP_HIF_SPI_INTR2_CPU_STATUS_SPI_LR_SESSION_ABORTED_SHIFT 1
-#define BCHP_HIF_SPI_INTR2_CPU_STATUS_SPI_LR_SESSION_ABORTED_DEFAULT 0x00000000
-
-/* HIF_SPI_INTR2 :: CPU_STATUS :: SPI_LR_FULLNESS_REACHED [00:00] */
-#define BCHP_HIF_SPI_INTR2_CPU_STATUS_SPI_LR_FULLNESS_REACHED_MASK 0x00000001
-#define BCHP_HIF_SPI_INTR2_CPU_STATUS_SPI_LR_FULLNESS_REACHED_SHIFT 0
-#define BCHP_HIF_SPI_INTR2_CPU_STATUS_SPI_LR_FULLNESS_REACHED_DEFAULT 0x00000000
-
-/***************************************************************************
- *CPU_SET - CPU interrupt Set Register
- ***************************************************************************/
-/* HIF_SPI_INTR2 :: CPU_SET :: reserved0 [31:07] */
-#define BCHP_HIF_SPI_INTR2_CPU_SET_reserved0_MASK 0xffffff80
-#define BCHP_HIF_SPI_INTR2_CPU_SET_reserved0_SHIFT 7
-
-/* HIF_SPI_INTR2 :: CPU_SET :: MSPI_HALTED [06:06] */
-#define BCHP_HIF_SPI_INTR2_CPU_SET_MSPI_HALTED_MASK 0x00000040
-#define BCHP_HIF_SPI_INTR2_CPU_SET_MSPI_HALTED_SHIFT 6
-#define BCHP_HIF_SPI_INTR2_CPU_SET_MSPI_HALTED_DEFAULT 0x00000000
-
-/* HIF_SPI_INTR2 :: CPU_SET :: MSPI_DONE [05:05] */
-#define BCHP_HIF_SPI_INTR2_CPU_SET_MSPI_DONE_MASK 0x00000020
-#define BCHP_HIF_SPI_INTR2_CPU_SET_MSPI_DONE_SHIFT 5
-#define BCHP_HIF_SPI_INTR2_CPU_SET_MSPI_DONE_DEFAULT 0x00000000
-
-/* HIF_SPI_INTR2 :: CPU_SET :: SPI_LR_OVERREAD [04:04] */
-#define BCHP_HIF_SPI_INTR2_CPU_SET_SPI_LR_OVERREAD_MASK 0x00000010
-#define BCHP_HIF_SPI_INTR2_CPU_SET_SPI_LR_OVERREAD_SHIFT 4
-#define BCHP_HIF_SPI_INTR2_CPU_SET_SPI_LR_OVERREAD_DEFAULT 0x00000000
-
-/* HIF_SPI_INTR2 :: CPU_SET :: SPI_LR_SESSION_DONE [03:03] */
-#define BCHP_HIF_SPI_INTR2_CPU_SET_SPI_LR_SESSION_DONE_MASK 0x00000008
-#define BCHP_HIF_SPI_INTR2_CPU_SET_SPI_LR_SESSION_DONE_SHIFT 3
-#define BCHP_HIF_SPI_INTR2_CPU_SET_SPI_LR_SESSION_DONE_DEFAULT 0x00000000
-
-/* HIF_SPI_INTR2 :: CPU_SET :: SPI_LR_IMPATIENT [02:02] */
-#define BCHP_HIF_SPI_INTR2_CPU_SET_SPI_LR_IMPATIENT_MASK 0x00000004
-#define BCHP_HIF_SPI_INTR2_CPU_SET_SPI_LR_IMPATIENT_SHIFT 2
-#define BCHP_HIF_SPI_INTR2_CPU_SET_SPI_LR_IMPATIENT_DEFAULT 0x00000000
-
-/* HIF_SPI_INTR2 :: CPU_SET :: SPI_LR_SESSION_ABORTED [01:01] */
-#define BCHP_HIF_SPI_INTR2_CPU_SET_SPI_LR_SESSION_ABORTED_MASK 0x00000002
-#define BCHP_HIF_SPI_INTR2_CPU_SET_SPI_LR_SESSION_ABORTED_SHIFT 1
-#define BCHP_HIF_SPI_INTR2_CPU_SET_SPI_LR_SESSION_ABORTED_DEFAULT 0x00000000
-
-/* HIF_SPI_INTR2 :: CPU_SET :: SPI_LR_FULLNESS_REACHED [00:00] */
-#define BCHP_HIF_SPI_INTR2_CPU_SET_SPI_LR_FULLNESS_REACHED_MASK 0x00000001
-#define BCHP_HIF_SPI_INTR2_CPU_SET_SPI_LR_FULLNESS_REACHED_SHIFT 0
-#define BCHP_HIF_SPI_INTR2_CPU_SET_SPI_LR_FULLNESS_REACHED_DEFAULT 0x00000000
-
-/***************************************************************************
- *CPU_CLEAR - CPU interrupt Clear Register
- ***************************************************************************/
-/* HIF_SPI_INTR2 :: CPU_CLEAR :: reserved0 [31:07] */
-#define BCHP_HIF_SPI_INTR2_CPU_CLEAR_reserved0_MASK 0xffffff80
-#define BCHP_HIF_SPI_INTR2_CPU_CLEAR_reserved0_SHIFT 7
-
-/* HIF_SPI_INTR2 :: CPU_CLEAR :: MSPI_HALTED [06:06] */
-#define BCHP_HIF_SPI_INTR2_CPU_CLEAR_MSPI_HALTED_MASK 0x00000040
-#define BCHP_HIF_SPI_INTR2_CPU_CLEAR_MSPI_HALTED_SHIFT 6
-#define BCHP_HIF_SPI_INTR2_CPU_CLEAR_MSPI_HALTED_DEFAULT 0x00000000
-
-/* HIF_SPI_INTR2 :: CPU_CLEAR :: MSPI_DONE [05:05] */
-#define BCHP_HIF_SPI_INTR2_CPU_CLEAR_MSPI_DONE_MASK 0x00000020
-#define BCHP_HIF_SPI_INTR2_CPU_CLEAR_MSPI_DONE_SHIFT 5
-#define BCHP_HIF_SPI_INTR2_CPU_CLEAR_MSPI_DONE_DEFAULT 0x00000000
-
-/* HIF_SPI_INTR2 :: CPU_CLEAR :: SPI_LR_OVERREAD [04:04] */
-#define BCHP_HIF_SPI_INTR2_CPU_CLEAR_SPI_LR_OVERREAD_MASK 0x00000010
-#define BCHP_HIF_SPI_INTR2_CPU_CLEAR_SPI_LR_OVERREAD_SHIFT 4
-#define BCHP_HIF_SPI_INTR2_CPU_CLEAR_SPI_LR_OVERREAD_DEFAULT 0x00000000
-
-/* HIF_SPI_INTR2 :: CPU_CLEAR :: SPI_LR_SESSION_DONE [03:03] */
-#define BCHP_HIF_SPI_INTR2_CPU_CLEAR_SPI_LR_SESSION_DONE_MASK 0x00000008
-#define BCHP_HIF_SPI_INTR2_CPU_CLEAR_SPI_LR_SESSION_DONE_SHIFT 3
-#define BCHP_HIF_SPI_INTR2_CPU_CLEAR_SPI_LR_SESSION_DONE_DEFAULT 0x00000000
-
-/* HIF_SPI_INTR2 :: CPU_CLEAR :: SPI_LR_IMPATIENT [02:02] */
-#define BCHP_HIF_SPI_INTR2_CPU_CLEAR_SPI_LR_IMPATIENT_MASK 0x00000004
-#define BCHP_HIF_SPI_INTR2_CPU_CLEAR_SPI_LR_IMPATIENT_SHIFT 2
-#define BCHP_HIF_SPI_INTR2_CPU_CLEAR_SPI_LR_IMPATIENT_DEFAULT 0x00000000
-
-/* HIF_SPI_INTR2 :: CPU_CLEAR :: SPI_LR_SESSION_ABORTED [01:01] */
-#define BCHP_HIF_SPI_INTR2_CPU_CLEAR_SPI_LR_SESSION_ABORTED_MASK 0x00000002
-#define BCHP_HIF_SPI_INTR2_CPU_CLEAR_SPI_LR_SESSION_ABORTED_SHIFT 1
-#define BCHP_HIF_SPI_INTR2_CPU_CLEAR_SPI_LR_SESSION_ABORTED_DEFAULT 0x00000000
-
-/* HIF_SPI_INTR2 :: CPU_CLEAR :: SPI_LR_FULLNESS_REACHED [00:00] */
-#define BCHP_HIF_SPI_INTR2_CPU_CLEAR_SPI_LR_FULLNESS_REACHED_MASK 0x00000001
-#define BCHP_HIF_SPI_INTR2_CPU_CLEAR_SPI_LR_FULLNESS_REACHED_SHIFT 0
-#define BCHP_HIF_SPI_INTR2_CPU_CLEAR_SPI_LR_FULLNESS_REACHED_DEFAULT 0x00000000
-
-/***************************************************************************
- *CPU_MASK_STATUS - CPU interrupt Mask Status Register
- ***************************************************************************/
-/* HIF_SPI_INTR2 :: CPU_MASK_STATUS :: reserved0 [31:07] */
-#define BCHP_HIF_SPI_INTR2_CPU_MASK_STATUS_reserved0_MASK 0xffffff80
-#define BCHP_HIF_SPI_INTR2_CPU_MASK_STATUS_reserved0_SHIFT 7
-
-/* HIF_SPI_INTR2 :: CPU_MASK_STATUS :: MSPI_HALTED [06:06] */
-#define BCHP_HIF_SPI_INTR2_CPU_MASK_STATUS_MSPI_HALTED_MASK 0x00000040
-#define BCHP_HIF_SPI_INTR2_CPU_MASK_STATUS_MSPI_HALTED_SHIFT 6
-#define BCHP_HIF_SPI_INTR2_CPU_MASK_STATUS_MSPI_HALTED_DEFAULT 0x00000000
-
-/* HIF_SPI_INTR2 :: CPU_MASK_STATUS :: MSPI_DONE [05:05] */
-#define BCHP_HIF_SPI_INTR2_CPU_MASK_STATUS_MSPI_DONE_MASK 0x00000020
-#define BCHP_HIF_SPI_INTR2_CPU_MASK_STATUS_MSPI_DONE_SHIFT 5
-#define BCHP_HIF_SPI_INTR2_CPU_MASK_STATUS_MSPI_DONE_DEFAULT 0x00000000
-
-/* HIF_SPI_INTR2 :: CPU_MASK_STATUS :: SPI_LR_OVERREAD [04:04] */
-#define BCHP_HIF_SPI_INTR2_CPU_MASK_STATUS_SPI_LR_OVERREAD_MASK 0x00000010
-#define BCHP_HIF_SPI_INTR2_CPU_MASK_STATUS_SPI_LR_OVERREAD_SHIFT 4
-#define BCHP_HIF_SPI_INTR2_CPU_MASK_STATUS_SPI_LR_OVERREAD_DEFAULT 0x00000000
-
-/* HIF_SPI_INTR2 :: CPU_MASK_STATUS :: SPI_LR_SESSION_DONE [03:03] */
-#define BCHP_HIF_SPI_INTR2_CPU_MASK_STATUS_SPI_LR_SESSION_DONE_MASK 0x00000008
-#define BCHP_HIF_SPI_INTR2_CPU_MASK_STATUS_SPI_LR_SESSION_DONE_SHIFT 3
-#define BCHP_HIF_SPI_INTR2_CPU_MASK_STATUS_SPI_LR_SESSION_DONE_DEFAULT 0x00000000
-
-/* HIF_SPI_INTR2 :: CPU_MASK_STATUS :: SPI_LR_IMPATIENT [02:02] */
-#define BCHP_HIF_SPI_INTR2_CPU_MASK_STATUS_SPI_LR_IMPATIENT_MASK 0x00000004
-#define BCHP_HIF_SPI_INTR2_CPU_MASK_STATUS_SPI_LR_IMPATIENT_SHIFT 2
-#define BCHP_HIF_SPI_INTR2_CPU_MASK_STATUS_SPI_LR_IMPATIENT_DEFAULT 0x00000000
-
-/* HIF_SPI_INTR2 :: CPU_MASK_STATUS :: SPI_LR_SESSION_ABORTED [01:01] */
-#define BCHP_HIF_SPI_INTR2_CPU_MASK_STATUS_SPI_LR_SESSION_ABORTED_MASK 0x00000002
-#define BCHP_HIF_SPI_INTR2_CPU_MASK_STATUS_SPI_LR_SESSION_ABORTED_SHIFT 1
-#define BCHP_HIF_SPI_INTR2_CPU_MASK_STATUS_SPI_LR_SESSION_ABORTED_DEFAULT 0x00000000
-
-/* HIF_SPI_INTR2 :: CPU_MASK_STATUS :: SPI_LR_FULLNESS_REACHED [00:00] */
-#define BCHP_HIF_SPI_INTR2_CPU_MASK_STATUS_SPI_LR_FULLNESS_REACHED_MASK 0x00000001
-#define BCHP_HIF_SPI_INTR2_CPU_MASK_STATUS_SPI_LR_FULLNESS_REACHED_SHIFT 0
-#define BCHP_HIF_SPI_INTR2_CPU_MASK_STATUS_SPI_LR_FULLNESS_REACHED_DEFAULT 0x00000000
-
-/***************************************************************************
- *CPU_MASK_SET - CPU interrupt Mask Set Register
- ***************************************************************************/
-/* HIF_SPI_INTR2 :: CPU_MASK_SET :: reserved0 [31:07] */
-#define BCHP_HIF_SPI_INTR2_CPU_MASK_SET_reserved0_MASK 0xffffff80
-#define BCHP_HIF_SPI_INTR2_CPU_MASK_SET_reserved0_SHIFT 7
-
-/* HIF_SPI_INTR2 :: CPU_MASK_SET :: MSPI_HALTED [06:06] */
-#define BCHP_HIF_SPI_INTR2_CPU_MASK_SET_MSPI_HALTED_MASK 0x00000040
-#define BCHP_HIF_SPI_INTR2_CPU_MASK_SET_MSPI_HALTED_SHIFT 6
-#define BCHP_HIF_SPI_INTR2_CPU_MASK_SET_MSPI_HALTED_DEFAULT 0x00000000
-
-/* HIF_SPI_INTR2 :: CPU_MASK_SET :: MSPI_DONE [05:05] */
-#define BCHP_HIF_SPI_INTR2_CPU_MASK_SET_MSPI_DONE_MASK 0x00000020
-#define BCHP_HIF_SPI_INTR2_CPU_MASK_SET_MSPI_DONE_SHIFT 5
-#define BCHP_HIF_SPI_INTR2_CPU_MASK_SET_MSPI_DONE_DEFAULT 0x00000000
-
-/* HIF_SPI_INTR2 :: CPU_MASK_SET :: SPI_LR_OVERREAD [04:04] */
-#define BCHP_HIF_SPI_INTR2_CPU_MASK_SET_SPI_LR_OVERREAD_MASK 0x00000010
-#define BCHP_HIF_SPI_INTR2_CPU_MASK_SET_SPI_LR_OVERREAD_SHIFT 4
-#define BCHP_HIF_SPI_INTR2_CPU_MASK_SET_SPI_LR_OVERREAD_DEFAULT 0x00000000
-
-/* HIF_SPI_INTR2 :: CPU_MASK_SET :: SPI_LR_SESSION_DONE [03:03] */
-#define BCHP_HIF_SPI_INTR2_CPU_MASK_SET_SPI_LR_SESSION_DONE_MASK 0x00000008
-#define BCHP_HIF_SPI_INTR2_CPU_MASK_SET_SPI_LR_SESSION_DONE_SHIFT 3
-#define BCHP_HIF_SPI_INTR2_CPU_MASK_SET_SPI_LR_SESSION_DONE_DEFAULT 0x00000000
-
-/* HIF_SPI_INTR2 :: CPU_MASK_SET :: SPI_LR_IMPATIENT [02:02] */
-#define BCHP_HIF_SPI_INTR2_CPU_MASK_SET_SPI_LR_IMPATIENT_MASK 0x00000004
-#define BCHP_HIF_SPI_INTR2_CPU_MASK_SET_SPI_LR_IMPATIENT_SHIFT 2
-#define BCHP_HIF_SPI_INTR2_CPU_MASK_SET_SPI_LR_IMPATIENT_DEFAULT 0x00000000
-
-/* HIF_SPI_INTR2 :: CPU_MASK_SET :: SPI_LR_SESSION_ABORTED [01:01] */
-#define BCHP_HIF_SPI_INTR2_CPU_MASK_SET_SPI_LR_SESSION_ABORTED_MASK 0x00000002
-#define BCHP_HIF_SPI_INTR2_CPU_MASK_SET_SPI_LR_SESSION_ABORTED_SHIFT 1
-#define BCHP_HIF_SPI_INTR2_CPU_MASK_SET_SPI_LR_SESSION_ABORTED_DEFAULT 0x00000000
-
-/* HIF_SPI_INTR2 :: CPU_MASK_SET :: SPI_LR_FULLNESS_REACHED [00:00] */
-#define BCHP_HIF_SPI_INTR2_CPU_MASK_SET_SPI_LR_FULLNESS_REACHED_MASK 0x00000001
-#define BCHP_HIF_SPI_INTR2_CPU_MASK_SET_SPI_LR_FULLNESS_REACHED_SHIFT 0
-#define BCHP_HIF_SPI_INTR2_CPU_MASK_SET_SPI_LR_FULLNESS_REACHED_DEFAULT 0x00000000
-
-/***************************************************************************
- *CPU_MASK_CLEAR - CPU interrupt Mask Clear Register
- ***************************************************************************/
-/* HIF_SPI_INTR2 :: CPU_MASK_CLEAR :: reserved0 [31:07] */
-#define BCHP_HIF_SPI_INTR2_CPU_MASK_CLEAR_reserved0_MASK 0xffffff80
-#define BCHP_HIF_SPI_INTR2_CPU_MASK_CLEAR_reserved0_SHIFT 7
-
-/* HIF_SPI_INTR2 :: CPU_MASK_CLEAR :: MSPI_HALTED [06:06] */
-#define BCHP_HIF_SPI_INTR2_CPU_MASK_CLEAR_MSPI_HALTED_MASK 0x00000040
-#define BCHP_HIF_SPI_INTR2_CPU_MASK_CLEAR_MSPI_HALTED_SHIFT 6
-#define BCHP_HIF_SPI_INTR2_CPU_MASK_CLEAR_MSPI_HALTED_DEFAULT 0x00000000
-
-/* HIF_SPI_INTR2 :: CPU_MASK_CLEAR :: MSPI_DONE [05:05] */
-#define BCHP_HIF_SPI_INTR2_CPU_MASK_CLEAR_MSPI_DONE_MASK 0x00000020
-#define BCHP_HIF_SPI_INTR2_CPU_MASK_CLEAR_MSPI_DONE_SHIFT 5
-#define BCHP_HIF_SPI_INTR2_CPU_MASK_CLEAR_MSPI_DONE_DEFAULT 0x00000000
-
-/* HIF_SPI_INTR2 :: CPU_MASK_CLEAR :: SPI_LR_OVERREAD [04:04] */
-#define BCHP_HIF_SPI_INTR2_CPU_MASK_CLEAR_SPI_LR_OVERREAD_MASK 0x00000010
-#define BCHP_HIF_SPI_INTR2_CPU_MASK_CLEAR_SPI_LR_OVERREAD_SHIFT 4
-#define BCHP_HIF_SPI_INTR2_CPU_MASK_CLEAR_SPI_LR_OVERREAD_DEFAULT 0x00000000
-
-/* HIF_SPI_INTR2 :: CPU_MASK_CLEAR :: SPI_LR_SESSION_DONE [03:03] */
-#define BCHP_HIF_SPI_INTR2_CPU_MASK_CLEAR_SPI_LR_SESSION_DONE_MASK 0x00000008
-#define BCHP_HIF_SPI_INTR2_CPU_MASK_CLEAR_SPI_LR_SESSION_DONE_SHIFT 3
-#define BCHP_HIF_SPI_INTR2_CPU_MASK_CLEAR_SPI_LR_SESSION_DONE_DEFAULT 0x00000000
-
-/* HIF_SPI_INTR2 :: CPU_MASK_CLEAR :: SPI_LR_IMPATIENT [02:02] */
-#define BCHP_HIF_SPI_INTR2_CPU_MASK_CLEAR_SPI_LR_IMPATIENT_MASK 0x00000004
-#define BCHP_HIF_SPI_INTR2_CPU_MASK_CLEAR_SPI_LR_IMPATIENT_SHIFT 2
-#define BCHP_HIF_SPI_INTR2_CPU_MASK_CLEAR_SPI_LR_IMPATIENT_DEFAULT 0x00000000
-
-/* HIF_SPI_INTR2 :: CPU_MASK_CLEAR :: SPI_LR_SESSION_ABORTED [01:01] */
-#define BCHP_HIF_SPI_INTR2_CPU_MASK_CLEAR_SPI_LR_SESSION_ABORTED_MASK 0x00000002
-#define BCHP_HIF_SPI_INTR2_CPU_MASK_CLEAR_SPI_LR_SESSION_ABORTED_SHIFT 1
-#define BCHP_HIF_SPI_INTR2_CPU_MASK_CLEAR_SPI_LR_SESSION_ABORTED_DEFAULT 0x00000000
-
-/* HIF_SPI_INTR2 :: CPU_MASK_CLEAR :: SPI_LR_FULLNESS_REACHED [00:00] */
-#define BCHP_HIF_SPI_INTR2_CPU_MASK_CLEAR_SPI_LR_FULLNESS_REACHED_MASK 0x00000001
-#define BCHP_HIF_SPI_INTR2_CPU_MASK_CLEAR_SPI_LR_FULLNESS_REACHED_SHIFT 0
-#define BCHP_HIF_SPI_INTR2_CPU_MASK_CLEAR_SPI_LR_FULLNESS_REACHED_DEFAULT 0x00000000
-
-/***************************************************************************
- *PCI_STATUS - PCI interrupt Status Register
- ***************************************************************************/
-/* HIF_SPI_INTR2 :: PCI_STATUS :: reserved0 [31:07] */
-#define BCHP_HIF_SPI_INTR2_PCI_STATUS_reserved0_MASK 0xffffff80
-#define BCHP_HIF_SPI_INTR2_PCI_STATUS_reserved0_SHIFT 7
-
-/* HIF_SPI_INTR2 :: PCI_STATUS :: MSPI_HALTED [06:06] */
-#define BCHP_HIF_SPI_INTR2_PCI_STATUS_MSPI_HALTED_MASK 0x00000040
-#define BCHP_HIF_SPI_INTR2_PCI_STATUS_MSPI_HALTED_SHIFT 6
-#define BCHP_HIF_SPI_INTR2_PCI_STATUS_MSPI_HALTED_DEFAULT 0x00000000
-
-/* HIF_SPI_INTR2 :: PCI_STATUS :: MSPI_DONE [05:05] */
-#define BCHP_HIF_SPI_INTR2_PCI_STATUS_MSPI_DONE_MASK 0x00000020
-#define BCHP_HIF_SPI_INTR2_PCI_STATUS_MSPI_DONE_SHIFT 5
-#define BCHP_HIF_SPI_INTR2_PCI_STATUS_MSPI_DONE_DEFAULT 0x00000000
-
-/* HIF_SPI_INTR2 :: PCI_STATUS :: SPI_LR_OVERREAD [04:04] */
-#define BCHP_HIF_SPI_INTR2_PCI_STATUS_SPI_LR_OVERREAD_MASK 0x00000010
-#define BCHP_HIF_SPI_INTR2_PCI_STATUS_SPI_LR_OVERREAD_SHIFT 4
-#define BCHP_HIF_SPI_INTR2_PCI_STATUS_SPI_LR_OVERREAD_DEFAULT 0x00000000
-
-/* HIF_SPI_INTR2 :: PCI_STATUS :: SPI_LR_SESSION_DONE [03:03] */
-#define BCHP_HIF_SPI_INTR2_PCI_STATUS_SPI_LR_SESSION_DONE_MASK 0x00000008
-#define BCHP_HIF_SPI_INTR2_PCI_STATUS_SPI_LR_SESSION_DONE_SHIFT 3
-#define BCHP_HIF_SPI_INTR2_PCI_STATUS_SPI_LR_SESSION_DONE_DEFAULT 0x00000000
-
-/* HIF_SPI_INTR2 :: PCI_STATUS :: SPI_LR_IMPATIENT [02:02] */
-#define BCHP_HIF_SPI_INTR2_PCI_STATUS_SPI_LR_IMPATIENT_MASK 0x00000004
-#define BCHP_HIF_SPI_INTR2_PCI_STATUS_SPI_LR_IMPATIENT_SHIFT 2
-#define BCHP_HIF_SPI_INTR2_PCI_STATUS_SPI_LR_IMPATIENT_DEFAULT 0x00000000
-
-/* HIF_SPI_INTR2 :: PCI_STATUS :: SPI_LR_SESSION_ABORTED [01:01] */
-#define BCHP_HIF_SPI_INTR2_PCI_STATUS_SPI_LR_SESSION_ABORTED_MASK 0x00000002
-#define BCHP_HIF_SPI_INTR2_PCI_STATUS_SPI_LR_SESSION_ABORTED_SHIFT 1
-#define BCHP_HIF_SPI_INTR2_PCI_STATUS_SPI_LR_SESSION_ABORTED_DEFAULT 0x00000000
-
-/* HIF_SPI_INTR2 :: PCI_STATUS :: SPI_LR_FULLNESS_REACHED [00:00] */
-#define BCHP_HIF_SPI_INTR2_PCI_STATUS_SPI_LR_FULLNESS_REACHED_MASK 0x00000001
-#define BCHP_HIF_SPI_INTR2_PCI_STATUS_SPI_LR_FULLNESS_REACHED_SHIFT 0
-#define BCHP_HIF_SPI_INTR2_PCI_STATUS_SPI_LR_FULLNESS_REACHED_DEFAULT 0x00000000
-
-/***************************************************************************
- *PCI_SET - PCI interrupt Set Register
- ***************************************************************************/
-/* HIF_SPI_INTR2 :: PCI_SET :: reserved0 [31:07] */
-#define BCHP_HIF_SPI_INTR2_PCI_SET_reserved0_MASK 0xffffff80
-#define BCHP_HIF_SPI_INTR2_PCI_SET_reserved0_SHIFT 7
-
-/* HIF_SPI_INTR2 :: PCI_SET :: MSPI_HALTED [06:06] */
-#define BCHP_HIF_SPI_INTR2_PCI_SET_MSPI_HALTED_MASK 0x00000040
-#define BCHP_HIF_SPI_INTR2_PCI_SET_MSPI_HALTED_SHIFT 6
-#define BCHP_HIF_SPI_INTR2_PCI_SET_MSPI_HALTED_DEFAULT 0x00000000
-
-/* HIF_SPI_INTR2 :: PCI_SET :: MSPI_DONE [05:05] */
-#define BCHP_HIF_SPI_INTR2_PCI_SET_MSPI_DONE_MASK 0x00000020
-#define BCHP_HIF_SPI_INTR2_PCI_SET_MSPI_DONE_SHIFT 5
-#define BCHP_HIF_SPI_INTR2_PCI_SET_MSPI_DONE_DEFAULT 0x00000000
-
-/* HIF_SPI_INTR2 :: PCI_SET :: SPI_LR_OVERREAD [04:04] */
-#define BCHP_HIF_SPI_INTR2_PCI_SET_SPI_LR_OVERREAD_MASK 0x00000010
-#define BCHP_HIF_SPI_INTR2_PCI_SET_SPI_LR_OVERREAD_SHIFT 4
-#define BCHP_HIF_SPI_INTR2_PCI_SET_SPI_LR_OVERREAD_DEFAULT 0x00000000
-
-/* HIF_SPI_INTR2 :: PCI_SET :: SPI_LR_SESSION_DONE [03:03] */
-#define BCHP_HIF_SPI_INTR2_PCI_SET_SPI_LR_SESSION_DONE_MASK 0x00000008
-#define BCHP_HIF_SPI_INTR2_PCI_SET_SPI_LR_SESSION_DONE_SHIFT 3
-#define BCHP_HIF_SPI_INTR2_PCI_SET_SPI_LR_SESSION_DONE_DEFAULT 0x00000000
-
-/* HIF_SPI_INTR2 :: PCI_SET :: SPI_LR_IMPATIENT [02:02] */
-#define BCHP_HIF_SPI_INTR2_PCI_SET_SPI_LR_IMPATIENT_MASK 0x00000004
-#define BCHP_HIF_SPI_INTR2_PCI_SET_SPI_LR_IMPATIENT_SHIFT 2
-#define BCHP_HIF_SPI_INTR2_PCI_SET_SPI_LR_IMPATIENT_DEFAULT 0x00000000
-
-/* HIF_SPI_INTR2 :: PCI_SET :: SPI_LR_SESSION_ABORTED [01:01] */
-#define BCHP_HIF_SPI_INTR2_PCI_SET_SPI_LR_SESSION_ABORTED_MASK 0x00000002
-#define BCHP_HIF_SPI_INTR2_PCI_SET_SPI_LR_SESSION_ABORTED_SHIFT 1
-#define BCHP_HIF_SPI_INTR2_PCI_SET_SPI_LR_SESSION_ABORTED_DEFAULT 0x00000000
-
-/* HIF_SPI_INTR2 :: PCI_SET :: SPI_LR_FULLNESS_REACHED [00:00] */
-#define BCHP_HIF_SPI_INTR2_PCI_SET_SPI_LR_FULLNESS_REACHED_MASK 0x00000001
-#define BCHP_HIF_SPI_INTR2_PCI_SET_SPI_LR_FULLNESS_REACHED_SHIFT 0
-#define BCHP_HIF_SPI_INTR2_PCI_SET_SPI_LR_FULLNESS_REACHED_DEFAULT 0x00000000
-
-/***************************************************************************
- *PCI_CLEAR - PCI interrupt Clear Register
- ***************************************************************************/
-/* HIF_SPI_INTR2 :: PCI_CLEAR :: reserved0 [31:07] */
-#define BCHP_HIF_SPI_INTR2_PCI_CLEAR_reserved0_MASK 0xffffff80
-#define BCHP_HIF_SPI_INTR2_PCI_CLEAR_reserved0_SHIFT 7
-
-/* HIF_SPI_INTR2 :: PCI_CLEAR :: MSPI_HALTED [06:06] */
-#define BCHP_HIF_SPI_INTR2_PCI_CLEAR_MSPI_HALTED_MASK 0x00000040
-#define BCHP_HIF_SPI_INTR2_PCI_CLEAR_MSPI_HALTED_SHIFT 6
-#define BCHP_HIF_SPI_INTR2_PCI_CLEAR_MSPI_HALTED_DEFAULT 0x00000000
-
-/* HIF_SPI_INTR2 :: PCI_CLEAR :: MSPI_DONE [05:05] */
-#define BCHP_HIF_SPI_INTR2_PCI_CLEAR_MSPI_DONE_MASK 0x00000020
-#define BCHP_HIF_SPI_INTR2_PCI_CLEAR_MSPI_DONE_SHIFT 5
-#define BCHP_HIF_SPI_INTR2_PCI_CLEAR_MSPI_DONE_DEFAULT 0x00000000
-
-/* HIF_SPI_INTR2 :: PCI_CLEAR :: SPI_LR_OVERREAD [04:04] */
-#define BCHP_HIF_SPI_INTR2_PCI_CLEAR_SPI_LR_OVERREAD_MASK 0x00000010
-#define BCHP_HIF_SPI_INTR2_PCI_CLEAR_SPI_LR_OVERREAD_SHIFT 4
-#define BCHP_HIF_SPI_INTR2_PCI_CLEAR_SPI_LR_OVERREAD_DEFAULT 0x00000000
-
-/* HIF_SPI_INTR2 :: PCI_CLEAR :: SPI_LR_SESSION_DONE [03:03] */
-#define BCHP_HIF_SPI_INTR2_PCI_CLEAR_SPI_LR_SESSION_DONE_MASK 0x00000008
-#define BCHP_HIF_SPI_INTR2_PCI_CLEAR_SPI_LR_SESSION_DONE_SHIFT 3
-#define BCHP_HIF_SPI_INTR2_PCI_CLEAR_SPI_LR_SESSION_DONE_DEFAULT 0x00000000
-
-/* HIF_SPI_INTR2 :: PCI_CLEAR :: SPI_LR_IMPATIENT [02:02] */
-#define BCHP_HIF_SPI_INTR2_PCI_CLEAR_SPI_LR_IMPATIENT_MASK 0x00000004
-#define BCHP_HIF_SPI_INTR2_PCI_CLEAR_SPI_LR_IMPATIENT_SHIFT 2
-#define BCHP_HIF_SPI_INTR2_PCI_CLEAR_SPI_LR_IMPATIENT_DEFAULT 0x00000000
-
-/* HIF_SPI_INTR2 :: PCI_CLEAR :: SPI_LR_SESSION_ABORTED [01:01] */
-#define BCHP_HIF_SPI_INTR2_PCI_CLEAR_SPI_LR_SESSION_ABORTED_MASK 0x00000002
-#define BCHP_HIF_SPI_INTR2_PCI_CLEAR_SPI_LR_SESSION_ABORTED_SHIFT 1
-#define BCHP_HIF_SPI_INTR2_PCI_CLEAR_SPI_LR_SESSION_ABORTED_DEFAULT 0x00000000
-
-/* HIF_SPI_INTR2 :: PCI_CLEAR :: SPI_LR_FULLNESS_REACHED [00:00] */
-#define BCHP_HIF_SPI_INTR2_PCI_CLEAR_SPI_LR_FULLNESS_REACHED_MASK 0x00000001
-#define BCHP_HIF_SPI_INTR2_PCI_CLEAR_SPI_LR_FULLNESS_REACHED_SHIFT 0
-#define BCHP_HIF_SPI_INTR2_PCI_CLEAR_SPI_LR_FULLNESS_REACHED_DEFAULT 0x00000000
-
-/***************************************************************************
- *PCI_MASK_STATUS - PCI interrupt Mask Status Register
- ***************************************************************************/
-/* HIF_SPI_INTR2 :: PCI_MASK_STATUS :: reserved0 [31:07] */
-#define BCHP_HIF_SPI_INTR2_PCI_MASK_STATUS_reserved0_MASK 0xffffff80
-#define BCHP_HIF_SPI_INTR2_PCI_MASK_STATUS_reserved0_SHIFT 7
-
-/* HIF_SPI_INTR2 :: PCI_MASK_STATUS :: MSPI_HALTED [06:06] */
-#define BCHP_HIF_SPI_INTR2_PCI_MASK_STATUS_MSPI_HALTED_MASK 0x00000040
-#define BCHP_HIF_SPI_INTR2_PCI_MASK_STATUS_MSPI_HALTED_SHIFT 6
-#define BCHP_HIF_SPI_INTR2_PCI_MASK_STATUS_MSPI_HALTED_DEFAULT 0x00000000
-
-/* HIF_SPI_INTR2 :: PCI_MASK_STATUS :: MSPI_DONE [05:05] */
-#define BCHP_HIF_SPI_INTR2_PCI_MASK_STATUS_MSPI_DONE_MASK 0x00000020
-#define BCHP_HIF_SPI_INTR2_PCI_MASK_STATUS_MSPI_DONE_SHIFT 5
-#define BCHP_HIF_SPI_INTR2_PCI_MASK_STATUS_MSPI_DONE_DEFAULT 0x00000000
-
-/* HIF_SPI_INTR2 :: PCI_MASK_STATUS :: SPI_LR_OVERREAD [04:04] */
-#define BCHP_HIF_SPI_INTR2_PCI_MASK_STATUS_SPI_LR_OVERREAD_MASK 0x00000010
-#define BCHP_HIF_SPI_INTR2_PCI_MASK_STATUS_SPI_LR_OVERREAD_SHIFT 4
-#define BCHP_HIF_SPI_INTR2_PCI_MASK_STATUS_SPI_LR_OVERREAD_DEFAULT 0x00000000
-
-/* HIF_SPI_INTR2 :: PCI_MASK_STATUS :: SPI_LR_SESSION_DONE [03:03] */
-#define BCHP_HIF_SPI_INTR2_PCI_MASK_STATUS_SPI_LR_SESSION_DONE_MASK 0x00000008
-#define BCHP_HIF_SPI_INTR2_PCI_MASK_STATUS_SPI_LR_SESSION_DONE_SHIFT 3
-#define BCHP_HIF_SPI_INTR2_PCI_MASK_STATUS_SPI_LR_SESSION_DONE_DEFAULT 0x00000000
-
-/* HIF_SPI_INTR2 :: PCI_MASK_STATUS :: SPI_LR_IMPATIENT [02:02] */
-#define BCHP_HIF_SPI_INTR2_PCI_MASK_STATUS_SPI_LR_IMPATIENT_MASK 0x00000004
-#define BCHP_HIF_SPI_INTR2_PCI_MASK_STATUS_SPI_LR_IMPATIENT_SHIFT 2
-#define BCHP_HIF_SPI_INTR2_PCI_MASK_STATUS_SPI_LR_IMPATIENT_DEFAULT 0x00000000
-
-/* HIF_SPI_INTR2 :: PCI_MASK_STATUS :: SPI_LR_SESSION_ABORTED [01:01] */
-#define BCHP_HIF_SPI_INTR2_PCI_MASK_STATUS_SPI_LR_SESSION_ABORTED_MASK 0x00000002
-#define BCHP_HIF_SPI_INTR2_PCI_MASK_STATUS_SPI_LR_SESSION_ABORTED_SHIFT 1
-#define BCHP_HIF_SPI_INTR2_PCI_MASK_STATUS_SPI_LR_SESSION_ABORTED_DEFAULT 0x00000000
-
-/* HIF_SPI_INTR2 :: PCI_MASK_STATUS :: SPI_LR_FULLNESS_REACHED [00:00] */
-#define BCHP_HIF_SPI_INTR2_PCI_MASK_STATUS_SPI_LR_FULLNESS_REACHED_MASK 0x00000001
-#define BCHP_HIF_SPI_INTR2_PCI_MASK_STATUS_SPI_LR_FULLNESS_REACHED_SHIFT 0
-#define BCHP_HIF_SPI_INTR2_PCI_MASK_STATUS_SPI_LR_FULLNESS_REACHED_DEFAULT 0x00000000
-
-/***************************************************************************
- *PCI_MASK_SET - PCI interrupt Mask Set Register
- ***************************************************************************/
-/* HIF_SPI_INTR2 :: PCI_MASK_SET :: reserved0 [31:07] */
-#define BCHP_HIF_SPI_INTR2_PCI_MASK_SET_reserved0_MASK 0xffffff80
-#define BCHP_HIF_SPI_INTR2_PCI_MASK_SET_reserved0_SHIFT 7
-
-/* HIF_SPI_INTR2 :: PCI_MASK_SET :: MSPI_HALTED [06:06] */
-#define BCHP_HIF_SPI_INTR2_PCI_MASK_SET_MSPI_HALTED_MASK 0x00000040
-#define BCHP_HIF_SPI_INTR2_PCI_MASK_SET_MSPI_HALTED_SHIFT 6
-#define BCHP_HIF_SPI_INTR2_PCI_MASK_SET_MSPI_HALTED_DEFAULT 0x00000000
-
-/* HIF_SPI_INTR2 :: PCI_MASK_SET :: MSPI_DONE [05:05] */
-#define BCHP_HIF_SPI_INTR2_PCI_MASK_SET_MSPI_DONE_MASK 0x00000020
-#define BCHP_HIF_SPI_INTR2_PCI_MASK_SET_MSPI_DONE_SHIFT 5
-#define BCHP_HIF_SPI_INTR2_PCI_MASK_SET_MSPI_DONE_DEFAULT 0x00000000
-
-/* HIF_SPI_INTR2 :: PCI_MASK_SET :: SPI_LR_OVERREAD [04:04] */
-#define BCHP_HIF_SPI_INTR2_PCI_MASK_SET_SPI_LR_OVERREAD_MASK 0x00000010
-#define BCHP_HIF_SPI_INTR2_PCI_MASK_SET_SPI_LR_OVERREAD_SHIFT 4
-#define BCHP_HIF_SPI_INTR2_PCI_MASK_SET_SPI_LR_OVERREAD_DEFAULT 0x00000000
-
-/* HIF_SPI_INTR2 :: PCI_MASK_SET :: SPI_LR_SESSION_DONE [03:03] */
-#define BCHP_HIF_SPI_INTR2_PCI_MASK_SET_SPI_LR_SESSION_DONE_MASK 0x00000008
-#define BCHP_HIF_SPI_INTR2_PCI_MASK_SET_SPI_LR_SESSION_DONE_SHIFT 3
-#define BCHP_HIF_SPI_INTR2_PCI_MASK_SET_SPI_LR_SESSION_DONE_DEFAULT 0x00000000
-
-/* HIF_SPI_INTR2 :: PCI_MASK_SET :: SPI_LR_IMPATIENT [02:02] */
-#define BCHP_HIF_SPI_INTR2_PCI_MASK_SET_SPI_LR_IMPATIENT_MASK 0x00000004
-#define BCHP_HIF_SPI_INTR2_PCI_MASK_SET_SPI_LR_IMPATIENT_SHIFT 2
-#define BCHP_HIF_SPI_INTR2_PCI_MASK_SET_SPI_LR_IMPATIENT_DEFAULT 0x00000000
-
-/* HIF_SPI_INTR2 :: PCI_MASK_SET :: SPI_LR_SESSION_ABORTED [01:01] */
-#define BCHP_HIF_SPI_INTR2_PCI_MASK_SET_SPI_LR_SESSION_ABORTED_MASK 0x00000002
-#define BCHP_HIF_SPI_INTR2_PCI_MASK_SET_SPI_LR_SESSION_ABORTED_SHIFT 1
-#define BCHP_HIF_SPI_INTR2_PCI_MASK_SET_SPI_LR_SESSION_ABORTED_DEFAULT 0x00000000
-
-/* HIF_SPI_INTR2 :: PCI_MASK_SET :: SPI_LR_FULLNESS_REACHED [00:00] */
-#define BCHP_HIF_SPI_INTR2_PCI_MASK_SET_SPI_LR_FULLNESS_REACHED_MASK 0x00000001
-#define BCHP_HIF_SPI_INTR2_PCI_MASK_SET_SPI_LR_FULLNESS_REACHED_SHIFT 0
-#define BCHP_HIF_SPI_INTR2_PCI_MASK_SET_SPI_LR_FULLNESS_REACHED_DEFAULT 0x00000000
-
-/***************************************************************************
- *PCI_MASK_CLEAR - PCI interrupt Mask Clear Register
- ***************************************************************************/
-/* HIF_SPI_INTR2 :: PCI_MASK_CLEAR :: reserved0 [31:07] */
-#define BCHP_HIF_SPI_INTR2_PCI_MASK_CLEAR_reserved0_MASK 0xffffff80
-#define BCHP_HIF_SPI_INTR2_PCI_MASK_CLEAR_reserved0_SHIFT 7
-
-/* HIF_SPI_INTR2 :: PCI_MASK_CLEAR :: MSPI_HALTED [06:06] */
-#define BCHP_HIF_SPI_INTR2_PCI_MASK_CLEAR_MSPI_HALTED_MASK 0x00000040
-#define BCHP_HIF_SPI_INTR2_PCI_MASK_CLEAR_MSPI_HALTED_SHIFT 6
-#define BCHP_HIF_SPI_INTR2_PCI_MASK_CLEAR_MSPI_HALTED_DEFAULT 0x00000000
-
-/* HIF_SPI_INTR2 :: PCI_MASK_CLEAR :: MSPI_DONE [05:05] */
-#define BCHP_HIF_SPI_INTR2_PCI_MASK_CLEAR_MSPI_DONE_MASK 0x00000020
-#define BCHP_HIF_SPI_INTR2_PCI_MASK_CLEAR_MSPI_DONE_SHIFT 5
-#define BCHP_HIF_SPI_INTR2_PCI_MASK_CLEAR_MSPI_DONE_DEFAULT 0x00000000
-
-/* HIF_SPI_INTR2 :: PCI_MASK_CLEAR :: SPI_LR_OVERREAD [04:04] */
-#define BCHP_HIF_SPI_INTR2_PCI_MASK_CLEAR_SPI_LR_OVERREAD_MASK 0x00000010
-#define BCHP_HIF_SPI_INTR2_PCI_MASK_CLEAR_SPI_LR_OVERREAD_SHIFT 4
-#define BCHP_HIF_SPI_INTR2_PCI_MASK_CLEAR_SPI_LR_OVERREAD_DEFAULT 0x00000000
-
-/* HIF_SPI_INTR2 :: PCI_MASK_CLEAR :: SPI_LR_SESSION_DONE [03:03] */
-#define BCHP_HIF_SPI_INTR2_PCI_MASK_CLEAR_SPI_LR_SESSION_DONE_MASK 0x00000008
-#define BCHP_HIF_SPI_INTR2_PCI_MASK_CLEAR_SPI_LR_SESSION_DONE_SHIFT 3
-#define BCHP_HIF_SPI_INTR2_PCI_MASK_CLEAR_SPI_LR_SESSION_DONE_DEFAULT 0x00000000
-
-/* HIF_SPI_INTR2 :: PCI_MASK_CLEAR :: SPI_LR_IMPATIENT [02:02] */
-#define BCHP_HIF_SPI_INTR2_PCI_MASK_CLEAR_SPI_LR_IMPATIENT_MASK 0x00000004
-#define BCHP_HIF_SPI_INTR2_PCI_MASK_CLEAR_SPI_LR_IMPATIENT_SHIFT 2
-#define BCHP_HIF_SPI_INTR2_PCI_MASK_CLEAR_SPI_LR_IMPATIENT_DEFAULT 0x00000000
-
-/* HIF_SPI_INTR2 :: PCI_MASK_CLEAR :: SPI_LR_SESSION_ABORTED [01:01] */
-#define BCHP_HIF_SPI_INTR2_PCI_MASK_CLEAR_SPI_LR_SESSION_ABORTED_MASK 0x00000002
-#define BCHP_HIF_SPI_INTR2_PCI_MASK_CLEAR_SPI_LR_SESSION_ABORTED_SHIFT 1
-#define BCHP_HIF_SPI_INTR2_PCI_MASK_CLEAR_SPI_LR_SESSION_ABORTED_DEFAULT 0x00000000
-
-/* HIF_SPI_INTR2 :: PCI_MASK_CLEAR :: SPI_LR_FULLNESS_REACHED [00:00] */
-#define BCHP_HIF_SPI_INTR2_PCI_MASK_CLEAR_SPI_LR_FULLNESS_REACHED_MASK 0x00000001
-#define BCHP_HIF_SPI_INTR2_PCI_MASK_CLEAR_SPI_LR_FULLNESS_REACHED_SHIFT 0
-#define BCHP_HIF_SPI_INTR2_PCI_MASK_CLEAR_SPI_LR_FULLNESS_REACHED_DEFAULT 0x00000000
-
-#endif /* #ifndef BCHP_HIF_SPI_INTR2_H__ */
-
-/* End of File */
diff --git a/include/linux/brcmstb/7439a0/bchp_hif_top_ctrl.h b/include/linux/brcmstb/7439a0/bchp_hif_top_ctrl.h
deleted file mode 100644
index a8dda04..0000000
--- a/include/linux/brcmstb/7439a0/bchp_hif_top_ctrl.h
+++ /dev/null
@@ -1,589 +0,0 @@
-/***************************************************************************
- * Copyright (c) 1999-2013, Broadcom Corporation
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
- *
- * Module Description:
- * DO NOT EDIT THIS FILE DIRECTLY
- *
- * This module was generated magically with RDB from a source description
- * file. You must edit the source file for changes to be made to this file.
- *
- *
- * Date: Generated on Tue Apr 16 03:26:50 2013
- * MD5 Checksum d41d8cd98f00b204e9800998ecf8427e
- *
- * Compiled with: RDB Utility combo_header.pl
- * RDB Parser 3.0
- * unknown unknown
- * Perl Interpreter 5.008008
- * Operating System linux
- *
- * Revision History:
- *
- * $brcm_Log: $
- *
- ***************************************************************************/
-
-#ifndef BCHP_HIF_TOP_CTRL_H__
-#define BCHP_HIF_TOP_CTRL_H__
-
-/***************************************************************************
- *HIF_TOP_CTRL - HIF Top Control Registers
- ***************************************************************************/
-#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL 0x00442000 /* External IRQ Active Level Control Register */
-#define BCHP_HIF_TOP_CTRL_SPI_DBG_SEL 0x00442004 /* SPI test port select register */
-#define BCHP_HIF_TOP_CTRL_PM_CTRL0 0x0044200c /* HIF Power Management Control0 Register */
-#define BCHP_HIF_TOP_CTRL_PM_CTRL1 0x00442010 /* HIF Power Management Control1 Register */
-#define BCHP_HIF_TOP_CTRL_PM_CTRL2 0x00442014 /* HIF Power Management Control Register:used to control SDIO_0 (CARD) */
-#define BCHP_HIF_TOP_CTRL_PM_CTRL3 0x00442018 /* HIF Power Management Control Register:used to control SDIO_1 (EMMC) */
-#define BCHP_HIF_TOP_CTRL_FLASH_TYPE 0x0044201c /* HIF Decoded Flash Type */
-#define BCHP_HIF_TOP_CTRL_CPU_MODE_CTRL 0x00442030 /* CPU MODE Control register (PUBLIC) */
-#define BCHP_HIF_TOP_CTRL_CPU_MODE_STATUS 0x00442034 /* CPU MODE Control status register (PUBLIC) */
-#define BCHP_HIF_TOP_CTRL_SCRATCH 0x0044203c /* HIF Scratch Register */
-
-/***************************************************************************
- *EXT_IRQ_LEVEL - External IRQ Active Level Control Register
- ***************************************************************************/
-/* HIF_TOP_CTRL :: EXT_IRQ_LEVEL :: reserved0 [31:06] */
-#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_reserved0_MASK 0xffffffc0
-#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_reserved0_SHIFT 6
-
-/* HIF_TOP_CTRL :: EXT_IRQ_LEVEL :: ext_irq_5_level [05:05] */
-#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_5_level_MASK 0x00000020
-#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_5_level_SHIFT 5
-#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_5_level_DEFAULT 0x00000000
-#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_5_level_LOW 0
-#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_5_level_HIGH 1
-
-/* HIF_TOP_CTRL :: EXT_IRQ_LEVEL :: ext_irq_4_level [04:04] */
-#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_4_level_MASK 0x00000010
-#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_4_level_SHIFT 4
-#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_4_level_DEFAULT 0x00000000
-#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_4_level_LOW 0
-#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_4_level_HIGH 1
-
-/* HIF_TOP_CTRL :: EXT_IRQ_LEVEL :: ext_irq_3_level [03:03] */
-#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_3_level_MASK 0x00000008
-#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_3_level_SHIFT 3
-#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_3_level_DEFAULT 0x00000000
-#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_3_level_LOW 0
-#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_3_level_HIGH 1
-
-/* HIF_TOP_CTRL :: EXT_IRQ_LEVEL :: ext_irq_2_level [02:02] */
-#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_2_level_MASK 0x00000004
-#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_2_level_SHIFT 2
-#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_2_level_DEFAULT 0x00000000
-#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_2_level_LOW 0
-#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_2_level_HIGH 1
-
-/* HIF_TOP_CTRL :: EXT_IRQ_LEVEL :: ext_irq_1_level [01:01] */
-#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_1_level_MASK 0x00000002
-#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_1_level_SHIFT 1
-#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_1_level_DEFAULT 0x00000000
-#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_1_level_LOW 0
-#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_1_level_HIGH 1
-
-/* HIF_TOP_CTRL :: EXT_IRQ_LEVEL :: ext_irq_0_level [00:00] */
-#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_0_level_MASK 0x00000001
-#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_0_level_SHIFT 0
-#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_0_level_DEFAULT 0x00000000
-#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_0_level_LOW 0
-#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_0_level_HIGH 1
-
-/***************************************************************************
- *SPI_DBG_SEL - SPI test port select register
- ***************************************************************************/
-/* HIF_TOP_CTRL :: SPI_DBG_SEL :: reserved0 [31:03] */
-#define BCHP_HIF_TOP_CTRL_SPI_DBG_SEL_reserved0_MASK 0xfffffff8
-#define BCHP_HIF_TOP_CTRL_SPI_DBG_SEL_reserved0_SHIFT 3
-
-/* HIF_TOP_CTRL :: SPI_DBG_SEL :: DISABLE_MSPI_FLUSH [02:02] */
-#define BCHP_HIF_TOP_CTRL_SPI_DBG_SEL_DISABLE_MSPI_FLUSH_MASK 0x00000004
-#define BCHP_HIF_TOP_CTRL_SPI_DBG_SEL_DISABLE_MSPI_FLUSH_SHIFT 2
-#define BCHP_HIF_TOP_CTRL_SPI_DBG_SEL_DISABLE_MSPI_FLUSH_DEFAULT 0x00000000
-
-/* HIF_TOP_CTRL :: SPI_DBG_SEL :: SPI_RBUS_TIMER_EN [01:01] */
-#define BCHP_HIF_TOP_CTRL_SPI_DBG_SEL_SPI_RBUS_TIMER_EN_MASK 0x00000002
-#define BCHP_HIF_TOP_CTRL_SPI_DBG_SEL_SPI_RBUS_TIMER_EN_SHIFT 1
-#define BCHP_HIF_TOP_CTRL_SPI_DBG_SEL_SPI_RBUS_TIMER_EN_DEFAULT 0x00000000
-
-/* HIF_TOP_CTRL :: SPI_DBG_SEL :: reserved1 [00:00] */
-#define BCHP_HIF_TOP_CTRL_SPI_DBG_SEL_reserved1_MASK 0x00000001
-#define BCHP_HIF_TOP_CTRL_SPI_DBG_SEL_reserved1_SHIFT 0
-
-/***************************************************************************
- *PM_CTRL0 - HIF Power Management Control0 Register
- ***************************************************************************/
-/* HIF_TOP_CTRL :: PM_CTRL0 :: EBI_PM_IN_DRIVE_INACTIVE [31:30] */
-#define BCHP_HIF_TOP_CTRL_PM_CTRL0_EBI_PM_IN_DRIVE_INACTIVE_MASK 0xc0000000
-#define BCHP_HIF_TOP_CTRL_PM_CTRL0_EBI_PM_IN_DRIVE_INACTIVE_SHIFT 30
-#define BCHP_HIF_TOP_CTRL_PM_CTRL0_EBI_PM_IN_DRIVE_INACTIVE_DEFAULT 0x00000000
-#define BCHP_HIF_TOP_CTRL_PM_CTRL0_EBI_PM_IN_DRIVE_INACTIVE_FUNCTIONAL 0
-#define BCHP_HIF_TOP_CTRL_PM_CTRL0_EBI_PM_IN_DRIVE_INACTIVE_Low 1
-#define BCHP_HIF_TOP_CTRL_PM_CTRL0_EBI_PM_IN_DRIVE_INACTIVE_HIGH 2
-
-/* HIF_TOP_CTRL :: PM_CTRL0 :: NAND_DATA_PM_IN_DRIVE_INACTIVE [29:28] */
-#define BCHP_HIF_TOP_CTRL_PM_CTRL0_NAND_DATA_PM_IN_DRIVE_INACTIVE_MASK 0x30000000
-#define BCHP_HIF_TOP_CTRL_PM_CTRL0_NAND_DATA_PM_IN_DRIVE_INACTIVE_SHIFT 28
-#define BCHP_HIF_TOP_CTRL_PM_CTRL0_NAND_DATA_PM_IN_DRIVE_INACTIVE_DEFAULT 0x00000000
-#define BCHP_HIF_TOP_CTRL_PM_CTRL0_NAND_DATA_PM_IN_DRIVE_INACTIVE_FUNCTIONAL 0
-#define BCHP_HIF_TOP_CTRL_PM_CTRL0_NAND_DATA_PM_IN_DRIVE_INACTIVE_Low 1
-#define BCHP_HIF_TOP_CTRL_PM_CTRL0_NAND_DATA_PM_IN_DRIVE_INACTIVE_HIGH 2
-
-/* HIF_TOP_CTRL :: PM_CTRL0 :: NAND_CTRL_PM_IN_DRIVE_INACTIVE [27:26] */
-#define BCHP_HIF_TOP_CTRL_PM_CTRL0_NAND_CTRL_PM_IN_DRIVE_INACTIVE_MASK 0x0c000000
-#define BCHP_HIF_TOP_CTRL_PM_CTRL0_NAND_CTRL_PM_IN_DRIVE_INACTIVE_SHIFT 26
-#define BCHP_HIF_TOP_CTRL_PM_CTRL0_NAND_CTRL_PM_IN_DRIVE_INACTIVE_DEFAULT 0x00000000
-#define BCHP_HIF_TOP_CTRL_PM_CTRL0_NAND_CTRL_PM_IN_DRIVE_INACTIVE_FUNCTIONAL 0
-#define BCHP_HIF_TOP_CTRL_PM_CTRL0_NAND_CTRL_PM_IN_DRIVE_INACTIVE_NOT_USED 1
-#define BCHP_HIF_TOP_CTRL_PM_CTRL0_NAND_CTRL_PM_IN_DRIVE_INACTIVE_HIGH 2
-
-/* HIF_TOP_CTRL :: PM_CTRL0 :: EBI_DATA_PM_OUT_CTRL [25:24] */
-#define BCHP_HIF_TOP_CTRL_PM_CTRL0_EBI_DATA_PM_OUT_CTRL_MASK 0x03000000
-#define BCHP_HIF_TOP_CTRL_PM_CTRL0_EBI_DATA_PM_OUT_CTRL_SHIFT 24
-#define BCHP_HIF_TOP_CTRL_PM_CTRL0_EBI_DATA_PM_OUT_CTRL_DEFAULT 0x00000000
-#define BCHP_HIF_TOP_CTRL_PM_CTRL0_EBI_DATA_PM_OUT_CTRL_FUNCTIONAL 0
-#define BCHP_HIF_TOP_CTRL_PM_CTRL0_EBI_DATA_PM_OUT_CTRL_LOW 1
-#define BCHP_HIF_TOP_CTRL_PM_CTRL0_EBI_DATA_PM_OUT_CTRL_HIGH 2
-#define BCHP_HIF_TOP_CTRL_PM_CTRL0_EBI_DATA_PM_OUT_CTRL_Tristate 3
-
-/* HIF_TOP_CTRL :: PM_CTRL0 :: EBI_ADDR_PM_OUT_CTRL [23:22] */
-#define BCHP_HIF_TOP_CTRL_PM_CTRL0_EBI_ADDR_PM_OUT_CTRL_MASK 0x00c00000
-#define BCHP_HIF_TOP_CTRL_PM_CTRL0_EBI_ADDR_PM_OUT_CTRL_SHIFT 22
-#define BCHP_HIF_TOP_CTRL_PM_CTRL0_EBI_ADDR_PM_OUT_CTRL_DEFAULT 0x00000000
-#define BCHP_HIF_TOP_CTRL_PM_CTRL0_EBI_ADDR_PM_OUT_CTRL_FUNCTIONAL 0
-#define BCHP_HIF_TOP_CTRL_PM_CTRL0_EBI_ADDR_PM_OUT_CTRL_LOW 1
-#define BCHP_HIF_TOP_CTRL_PM_CTRL0_EBI_ADDR_PM_OUT_CTRL_HIGH 2
-#define BCHP_HIF_TOP_CTRL_PM_CTRL0_EBI_ADDR_PM_OUT_CTRL_Tristate 3
-
-/* HIF_TOP_CTRL :: PM_CTRL0 :: EBI_CTRL_PM_OUT_CTRL [21:20] */
-#define BCHP_HIF_TOP_CTRL_PM_CTRL0_EBI_CTRL_PM_OUT_CTRL_MASK 0x00300000
-#define BCHP_HIF_TOP_CTRL_PM_CTRL0_EBI_CTRL_PM_OUT_CTRL_SHIFT 20
-#define BCHP_HIF_TOP_CTRL_PM_CTRL0_EBI_CTRL_PM_OUT_CTRL_DEFAULT 0x00000000
-#define BCHP_HIF_TOP_CTRL_PM_CTRL0_EBI_CTRL_PM_OUT_CTRL_FUNCTIONAL 0
-#define BCHP_HIF_TOP_CTRL_PM_CTRL0_EBI_CTRL_PM_OUT_CTRL_LOW 1
-#define BCHP_HIF_TOP_CTRL_PM_CTRL0_EBI_CTRL_PM_OUT_CTRL_HIGH 2
-#define BCHP_HIF_TOP_CTRL_PM_CTRL0_EBI_CTRL_PM_OUT_CTRL_Tristate 3
-
-/* HIF_TOP_CTRL :: PM_CTRL0 :: NAND_DATA_PM_OUT_CTRL [19:18] */
-#define BCHP_HIF_TOP_CTRL_PM_CTRL0_NAND_DATA_PM_OUT_CTRL_MASK 0x000c0000
-#define BCHP_HIF_TOP_CTRL_PM_CTRL0_NAND_DATA_PM_OUT_CTRL_SHIFT 18
-#define BCHP_HIF_TOP_CTRL_PM_CTRL0_NAND_DATA_PM_OUT_CTRL_DEFAULT 0x00000000
-#define BCHP_HIF_TOP_CTRL_PM_CTRL0_NAND_DATA_PM_OUT_CTRL_FUNCTIONAL 0
-#define BCHP_HIF_TOP_CTRL_PM_CTRL0_NAND_DATA_PM_OUT_CTRL_LOW 1
-#define BCHP_HIF_TOP_CTRL_PM_CTRL0_NAND_DATA_PM_OUT_CTRL_HIGH 2
-#define BCHP_HIF_TOP_CTRL_PM_CTRL0_NAND_DATA_PM_OUT_CTRL_Tristate 3
-
-/* HIF_TOP_CTRL :: PM_CTRL0 :: NAND_CTRL_PM_OUT_CTRL [17:16] */
-#define BCHP_HIF_TOP_CTRL_PM_CTRL0_NAND_CTRL_PM_OUT_CTRL_MASK 0x00030000
-#define BCHP_HIF_TOP_CTRL_PM_CTRL0_NAND_CTRL_PM_OUT_CTRL_SHIFT 16
-#define BCHP_HIF_TOP_CTRL_PM_CTRL0_NAND_CTRL_PM_OUT_CTRL_DEFAULT 0x00000000
-#define BCHP_HIF_TOP_CTRL_PM_CTRL0_NAND_CTRL_PM_OUT_CTRL_FUNCTIONAL 0
-#define BCHP_HIF_TOP_CTRL_PM_CTRL0_NAND_CTRL_PM_OUT_CTRL_LOW 1
-#define BCHP_HIF_TOP_CTRL_PM_CTRL0_NAND_CTRL_PM_OUT_CTRL_HIGH 2
-#define BCHP_HIF_TOP_CTRL_PM_CTRL0_NAND_CTRL_PM_OUT_CTRL_Tristate 3
-
-/* HIF_TOP_CTRL :: PM_CTRL0 :: PM_OUT_CTRL_CS7 [15:14] */
-#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS7_MASK 0x0000c000
-#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS7_SHIFT 14
-#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS7_DEFAULT 0x00000000
-#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS7_FUNCTIONAL 0
-#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS7_LOW 1
-#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS7_HIGH 2
-#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS7_Tristate 3
-
-/* HIF_TOP_CTRL :: PM_CTRL0 :: PM_OUT_CTRL_CS6 [13:12] */
-#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS6_MASK 0x00003000
-#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS6_SHIFT 12
-#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS6_DEFAULT 0x00000000
-#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS6_FUNCTIONAL 0
-#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS6_LOW 1
-#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS6_HIGH 2
-#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS6_Tristate 3
-
-/* HIF_TOP_CTRL :: PM_CTRL0 :: PM_OUT_CTRL_CS5 [11:10] */
-#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS5_MASK 0x00000c00
-#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS5_SHIFT 10
-#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS5_DEFAULT 0x00000000
-#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS5_FUNCTIONAL 0
-#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS5_LOW 1
-#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS5_HIGH 2
-#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS5_Tristate 3
-
-/* HIF_TOP_CTRL :: PM_CTRL0 :: PM_OUT_CTRL_CS4 [09:08] */
-#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS4_MASK 0x00000300
-#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS4_SHIFT 8
-#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS4_DEFAULT 0x00000000
-#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS4_FUNCTIONAL 0
-#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS4_LOW 1
-#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS4_HIGH 2
-#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS4_Tristate 3
-
-/* HIF_TOP_CTRL :: PM_CTRL0 :: PM_OUT_CTRL_CS3 [07:06] */
-#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS3_MASK 0x000000c0
-#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS3_SHIFT 6
-#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS3_DEFAULT 0x00000000
-#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS3_FUNCTIONAL 0
-#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS3_LOW 1
-#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS3_HIGH 2
-#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS3_Tristate 3
-
-/* HIF_TOP_CTRL :: PM_CTRL0 :: PM_OUT_CTRL_CS2 [05:04] */
-#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS2_MASK 0x00000030
-#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS2_SHIFT 4
-#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS2_DEFAULT 0x00000000
-#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS2_FUNCTIONAL 0
-#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS2_LOW 1
-#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS2_HIGH 2
-#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS2_Tristate 3
-
-/* HIF_TOP_CTRL :: PM_CTRL0 :: PM_OUT_CTRL_CS1 [03:02] */
-#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS1_MASK 0x0000000c
-#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS1_SHIFT 2
-#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS1_DEFAULT 0x00000000
-#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS1_FUNCTIONAL 0
-#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS1_LOW 1
-#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS1_HIGH 2
-#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS1_Tristate 3
-
-/* HIF_TOP_CTRL :: PM_CTRL0 :: PM_OUT_CTRL_CS0 [01:00] */
-#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS0_MASK 0x00000003
-#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS0_SHIFT 0
-#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS0_DEFAULT 0x00000000
-#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS0_FUNCTIONAL 0
-#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS0_LOW 1
-#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS0_HIGH 2
-#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS0_Tristate 3
-
-/***************************************************************************
- *PM_CTRL1 - HIF Power Management Control1 Register
- ***************************************************************************/
-/* HIF_TOP_CTRL :: PM_CTRL1 :: reserved0 [31:12] */
-#define BCHP_HIF_TOP_CTRL_PM_CTRL1_reserved0_MASK 0xfffff000
-#define BCHP_HIF_TOP_CTRL_PM_CTRL1_reserved0_SHIFT 12
-
-/* HIF_TOP_CTRL :: PM_CTRL1 :: SPI_PM_IN_DRIVE_INACTIVE [11:10] */
-#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_PM_IN_DRIVE_INACTIVE_MASK 0x00000c00
-#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_PM_IN_DRIVE_INACTIVE_SHIFT 10
-#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_PM_IN_DRIVE_INACTIVE_DEFAULT 0x00000000
-#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_PM_IN_DRIVE_INACTIVE_FUNCTIONAL 0
-#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_PM_IN_DRIVE_INACTIVE_Low 1
-#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_PM_IN_DRIVE_INACTIVE_HIGH 2
-
-/* HIF_TOP_CTRL :: PM_CTRL1 :: SPI_WPB_PM_OUT_CTRL [09:08] */
-#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_WPB_PM_OUT_CTRL_MASK 0x00000300
-#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_WPB_PM_OUT_CTRL_SHIFT 8
-#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_WPB_PM_OUT_CTRL_DEFAULT 0x00000000
-#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_WPB_PM_OUT_CTRL_FUNCTIONAL 0
-#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_WPB_PM_OUT_CTRL_LOW 1
-#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_WPB_PM_OUT_CTRL_HIGH 2
-#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_WPB_PM_OUT_CTRL_Tristate 3
-
-/* HIF_TOP_CTRL :: PM_CTRL1 :: SPI_HOLDB_PM_OUT_CTRL [07:06] */
-#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_HOLDB_PM_OUT_CTRL_MASK 0x000000c0
-#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_HOLDB_PM_OUT_CTRL_SHIFT 6
-#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_HOLDB_PM_OUT_CTRL_DEFAULT 0x00000000
-#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_HOLDB_PM_OUT_CTRL_FUNCTIONAL 0
-#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_HOLDB_PM_OUT_CTRL_LOW 1
-#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_HOLDB_PM_OUT_CTRL_HIGH 2
-#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_HOLDB_PM_OUT_CTRL_Tristate 3
-
-/* HIF_TOP_CTRL :: PM_CTRL1 :: SPI_MISO_PM_OUT_CTRL [05:04] */
-#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_MISO_PM_OUT_CTRL_MASK 0x00000030
-#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_MISO_PM_OUT_CTRL_SHIFT 4
-#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_MISO_PM_OUT_CTRL_DEFAULT 0x00000000
-#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_MISO_PM_OUT_CTRL_FUNCTIONAL 0
-#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_MISO_PM_OUT_CTRL_LOW 1
-#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_MISO_PM_OUT_CTRL_HIGH 2
-#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_MISO_PM_OUT_CTRL_Tristate 3
-
-/* HIF_TOP_CTRL :: PM_CTRL1 :: SPI_MOSI_PM_OUT_CTRL [03:02] */
-#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_MOSI_PM_OUT_CTRL_MASK 0x0000000c
-#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_MOSI_PM_OUT_CTRL_SHIFT 2
-#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_MOSI_PM_OUT_CTRL_DEFAULT 0x00000000
-#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_MOSI_PM_OUT_CTRL_FUNCTIONAL 0
-#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_MOSI_PM_OUT_CTRL_LOW 1
-#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_MOSI_PM_OUT_CTRL_HIGH 2
-#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_MOSI_PM_OUT_CTRL_Tristate 3
-
-/* HIF_TOP_CTRL :: PM_CTRL1 :: SPI_CLK_PM_OUT_CTRL [01:00] */
-#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_CLK_PM_OUT_CTRL_MASK 0x00000003
-#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_CLK_PM_OUT_CTRL_SHIFT 0
-#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_CLK_PM_OUT_CTRL_DEFAULT 0x00000000
-#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_CLK_PM_OUT_CTRL_FUNCTIONAL 0
-#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_CLK_PM_OUT_CTRL_LOW 1
-#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_CLK_PM_OUT_CTRL_HIGH 2
-#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_CLK_PM_OUT_CTRL_Tristate 3
-
-/***************************************************************************
- *PM_CTRL2 - HIF Power Management Control Register:used to control SDIO_0 (CARD)
- ***************************************************************************/
-/* HIF_TOP_CTRL :: PM_CTRL2 :: reserved0 [31:24] */
-#define BCHP_HIF_TOP_CTRL_PM_CTRL2_reserved0_MASK 0xff000000
-#define BCHP_HIF_TOP_CTRL_PM_CTRL2_reserved0_SHIFT 24
-
-/* HIF_TOP_CTRL :: PM_CTRL2 :: SDIO_CARD_DETECT_PM_IN_DRIVE_INACTIVE [23:22] */
-#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_CARD_DETECT_PM_IN_DRIVE_INACTIVE_MASK 0x00c00000
-#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_CARD_DETECT_PM_IN_DRIVE_INACTIVE_SHIFT 22
-#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_CARD_DETECT_PM_IN_DRIVE_INACTIVE_DEFAULT 0x00000000
-#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_CARD_DETECT_PM_IN_DRIVE_INACTIVE_FUNCTIONAL 0
-#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_CARD_DETECT_PM_IN_DRIVE_INACTIVE_Low 1
-#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_CARD_DETECT_PM_IN_DRIVE_INACTIVE_HIGH 2
-
-/* HIF_TOP_CTRL :: PM_CTRL2 :: SDIO_WRITE_PROTECT_PM_IN_DRIVE_INACTIVE [21:20] */
-#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_WRITE_PROTECT_PM_IN_DRIVE_INACTIVE_MASK 0x00300000
-#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_WRITE_PROTECT_PM_IN_DRIVE_INACTIVE_SHIFT 20
-#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_WRITE_PROTECT_PM_IN_DRIVE_INACTIVE_DEFAULT 0x00000000
-#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_WRITE_PROTECT_PM_IN_DRIVE_INACTIVE_FUNCTIONAL 0
-#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_WRITE_PROTECT_PM_IN_DRIVE_INACTIVE_Low 1
-#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_WRITE_PROTECT_PM_IN_DRIVE_INACTIVE_HIGH 2
-
-/* HIF_TOP_CTRL :: PM_CTRL2 :: SDIO_DATA_PM_IN_DRIVE_INACTIVE [19:18] */
-#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_DATA_PM_IN_DRIVE_INACTIVE_MASK 0x000c0000
-#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_DATA_PM_IN_DRIVE_INACTIVE_SHIFT 18
-#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_DATA_PM_IN_DRIVE_INACTIVE_DEFAULT 0x00000000
-#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_DATA_PM_IN_DRIVE_INACTIVE_FUNCTIONAL 0
-#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_DATA_PM_IN_DRIVE_INACTIVE_Low 1
-#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_DATA_PM_IN_DRIVE_INACTIVE_HIGH 2
-
-/* HIF_TOP_CTRL :: PM_CTRL2 :: SDIO_CMD_PM_IN_DRIVE_INACTIVE [17:16] */
-#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_CMD_PM_IN_DRIVE_INACTIVE_MASK 0x00030000
-#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_CMD_PM_IN_DRIVE_INACTIVE_SHIFT 16
-#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_CMD_PM_IN_DRIVE_INACTIVE_DEFAULT 0x00000000
-#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_CMD_PM_IN_DRIVE_INACTIVE_FUNCTIONAL 0
-#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_CMD_PM_IN_DRIVE_INACTIVE_Low 1
-#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_CMD_PM_IN_DRIVE_INACTIVE_HIGH 2
-
-/* HIF_TOP_CTRL :: PM_CTRL2 :: reserved1 [15:12] */
-#define BCHP_HIF_TOP_CTRL_PM_CTRL2_reserved1_MASK 0x0000f000
-#define BCHP_HIF_TOP_CTRL_PM_CTRL2_reserved1_SHIFT 12
-
-/* HIF_TOP_CTRL :: PM_CTRL2 :: SDIO_VOLTAGE_PM_OUT_CTRL [11:10] */
-#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_VOLTAGE_PM_OUT_CTRL_MASK 0x00000c00
-#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_VOLTAGE_PM_OUT_CTRL_SHIFT 10
-#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_VOLTAGE_PM_OUT_CTRL_DEFAULT 0x00000000
-#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_VOLTAGE_PM_OUT_CTRL_FUNCTIONAL 0
-#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_VOLTAGE_PM_OUT_CTRL_LOW 1
-#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_VOLTAGE_PM_OUT_CTRL_HIGH 2
-#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_VOLTAGE_PM_OUT_CTRL_Tristate 3
-
-/* HIF_TOP_CTRL :: PM_CTRL2 :: SDIO_POWER_PM_OUT_CTRL [09:08] */
-#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_POWER_PM_OUT_CTRL_MASK 0x00000300
-#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_POWER_PM_OUT_CTRL_SHIFT 8
-#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_POWER_PM_OUT_CTRL_DEFAULT 0x00000000
-#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_POWER_PM_OUT_CTRL_FUNCTIONAL 0
-#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_POWER_PM_OUT_CTRL_LOW 1
-#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_POWER_PM_OUT_CTRL_HIGH 2
-#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_POWER_PM_OUT_CTRL_Tristate 3
-
-/* HIF_TOP_CTRL :: PM_CTRL2 :: SDIO_LED_PM_OUT_CTRL [07:06] */
-#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_LED_PM_OUT_CTRL_MASK 0x000000c0
-#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_LED_PM_OUT_CTRL_SHIFT 6
-#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_LED_PM_OUT_CTRL_DEFAULT 0x00000000
-#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_LED_PM_OUT_CTRL_FUNCTIONAL 0
-#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_LED_PM_OUT_CTRL_LOW 1
-#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_LED_PM_OUT_CTRL_HIGH 2
-#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_LED_PM_OUT_CTRL_Tristate 3
-
-/* HIF_TOP_CTRL :: PM_CTRL2 :: SDIO_DATA_PM_OUT_CTRL [05:04] */
-#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_DATA_PM_OUT_CTRL_MASK 0x00000030
-#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_DATA_PM_OUT_CTRL_SHIFT 4
-#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_DATA_PM_OUT_CTRL_DEFAULT 0x00000000
-#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_DATA_PM_OUT_CTRL_FUNCTIONAL 0
-#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_DATA_PM_OUT_CTRL_LOW 1
-#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_DATA_PM_OUT_CTRL_HIGH 2
-#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_DATA_PM_OUT_CTRL_Tristate 3
-
-/* HIF_TOP_CTRL :: PM_CTRL2 :: SDIO_CMD_PM_OUT_CTRL [03:02] */
-#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_CMD_PM_OUT_CTRL_MASK 0x0000000c
-#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_CMD_PM_OUT_CTRL_SHIFT 2
-#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_CMD_PM_OUT_CTRL_DEFAULT 0x00000000
-#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_CMD_PM_OUT_CTRL_FUNCTIONAL 0
-#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_CMD_PM_OUT_CTRL_LOW 1
-#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_CMD_PM_OUT_CTRL_HIGH 2
-#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_CMD_PM_OUT_CTRL_Tristate 3
-
-/* HIF_TOP_CTRL :: PM_CTRL2 :: SDIO_CLK_PM_OUT_CTRL [01:00] */
-#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_CLK_PM_OUT_CTRL_MASK 0x00000003
-#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_CLK_PM_OUT_CTRL_SHIFT 0
-#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_CLK_PM_OUT_CTRL_DEFAULT 0x00000000
-#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_CLK_PM_OUT_CTRL_FUNCTIONAL 0
-#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_CLK_PM_OUT_CTRL_LOW 1
-#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_CLK_PM_OUT_CTRL_HIGH 2
-#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_CLK_PM_OUT_CTRL_Tristate 3
-
-/***************************************************************************
- *PM_CTRL3 - HIF Power Management Control Register:used to control SDIO_1 (EMMC)
- ***************************************************************************/
-/* HIF_TOP_CTRL :: PM_CTRL3 :: reserved0 [31:24] */
-#define BCHP_HIF_TOP_CTRL_PM_CTRL3_reserved0_MASK 0xff000000
-#define BCHP_HIF_TOP_CTRL_PM_CTRL3_reserved0_SHIFT 24
-
-/* HIF_TOP_CTRL :: PM_CTRL3 :: SDIO_CARD_DETECT_PM_IN_DRIVE_INACTIVE [23:22] */
-#define BCHP_HIF_TOP_CTRL_PM_CTRL3_SDIO_CARD_DETECT_PM_IN_DRIVE_INACTIVE_MASK 0x00c00000
-#define BCHP_HIF_TOP_CTRL_PM_CTRL3_SDIO_CARD_DETECT_PM_IN_DRIVE_INACTIVE_SHIFT 22
-#define BCHP_HIF_TOP_CTRL_PM_CTRL3_SDIO_CARD_DETECT_PM_IN_DRIVE_INACTIVE_DEFAULT 0x00000000
-#define BCHP_HIF_TOP_CTRL_PM_CTRL3_SDIO_CARD_DETECT_PM_IN_DRIVE_INACTIVE_FUNCTIONAL 0
-#define BCHP_HIF_TOP_CTRL_PM_CTRL3_SDIO_CARD_DETECT_PM_IN_DRIVE_INACTIVE_Low 1
-#define BCHP_HIF_TOP_CTRL_PM_CTRL3_SDIO_CARD_DETECT_PM_IN_DRIVE_INACTIVE_HIGH 2
-
-/* HIF_TOP_CTRL :: PM_CTRL3 :: SDIO_WRITE_PROTECT_PM_IN_DRIVE_INACTIVE [21:20] */
-#define BCHP_HIF_TOP_CTRL_PM_CTRL3_SDIO_WRITE_PROTECT_PM_IN_DRIVE_INACTIVE_MASK 0x00300000
-#define BCHP_HIF_TOP_CTRL_PM_CTRL3_SDIO_WRITE_PROTECT_PM_IN_DRIVE_INACTIVE_SHIFT 20
-#define BCHP_HIF_TOP_CTRL_PM_CTRL3_SDIO_WRITE_PROTECT_PM_IN_DRIVE_INACTIVE_DEFAULT 0x00000000
-#define BCHP_HIF_TOP_CTRL_PM_CTRL3_SDIO_WRITE_PROTECT_PM_IN_DRIVE_INACTIVE_FUNCTIONAL 0
-#define BCHP_HIF_TOP_CTRL_PM_CTRL3_SDIO_WRITE_PROTECT_PM_IN_DRIVE_INACTIVE_Low 1
-#define BCHP_HIF_TOP_CTRL_PM_CTRL3_SDIO_WRITE_PROTECT_PM_IN_DRIVE_INACTIVE_HIGH 2
-
-/* HIF_TOP_CTRL :: PM_CTRL3 :: SDIO_DATA_PM_IN_DRIVE_INACTIVE [19:18] */
-#define BCHP_HIF_TOP_CTRL_PM_CTRL3_SDIO_DATA_PM_IN_DRIVE_INACTIVE_MASK 0x000c0000
-#define BCHP_HIF_TOP_CTRL_PM_CTRL3_SDIO_DATA_PM_IN_DRIVE_INACTIVE_SHIFT 18
-#define BCHP_HIF_TOP_CTRL_PM_CTRL3_SDIO_DATA_PM_IN_DRIVE_INACTIVE_DEFAULT 0x00000000
-#define BCHP_HIF_TOP_CTRL_PM_CTRL3_SDIO_DATA_PM_IN_DRIVE_INACTIVE_FUNCTIONAL 0
-#define BCHP_HIF_TOP_CTRL_PM_CTRL3_SDIO_DATA_PM_IN_DRIVE_INACTIVE_Low 1
-#define BCHP_HIF_TOP_CTRL_PM_CTRL3_SDIO_DATA_PM_IN_DRIVE_INACTIVE_HIGH 2
-
-/* HIF_TOP_CTRL :: PM_CTRL3 :: SDIO_CMD_PM_IN_DRIVE_INACTIVE [17:16] */
-#define BCHP_HIF_TOP_CTRL_PM_CTRL3_SDIO_CMD_PM_IN_DRIVE_INACTIVE_MASK 0x00030000
-#define BCHP_HIF_TOP_CTRL_PM_CTRL3_SDIO_CMD_PM_IN_DRIVE_INACTIVE_SHIFT 16
-#define BCHP_HIF_TOP_CTRL_PM_CTRL3_SDIO_CMD_PM_IN_DRIVE_INACTIVE_DEFAULT 0x00000000
-#define BCHP_HIF_TOP_CTRL_PM_CTRL3_SDIO_CMD_PM_IN_DRIVE_INACTIVE_FUNCTIONAL 0
-#define BCHP_HIF_TOP_CTRL_PM_CTRL3_SDIO_CMD_PM_IN_DRIVE_INACTIVE_Low 1
-#define BCHP_HIF_TOP_CTRL_PM_CTRL3_SDIO_CMD_PM_IN_DRIVE_INACTIVE_HIGH 2
-
-/* HIF_TOP_CTRL :: PM_CTRL3 :: reserved1 [15:12] */
-#define BCHP_HIF_TOP_CTRL_PM_CTRL3_reserved1_MASK 0x0000f000
-#define BCHP_HIF_TOP_CTRL_PM_CTRL3_reserved1_SHIFT 12
-
-/* HIF_TOP_CTRL :: PM_CTRL3 :: SDIO_VOLTAGE_PM_OUT_CTRL [11:10] */
-#define BCHP_HIF_TOP_CTRL_PM_CTRL3_SDIO_VOLTAGE_PM_OUT_CTRL_MASK 0x00000c00
-#define BCHP_HIF_TOP_CTRL_PM_CTRL3_SDIO_VOLTAGE_PM_OUT_CTRL_SHIFT 10
-#define BCHP_HIF_TOP_CTRL_PM_CTRL3_SDIO_VOLTAGE_PM_OUT_CTRL_DEFAULT 0x00000000
-#define BCHP_HIF_TOP_CTRL_PM_CTRL3_SDIO_VOLTAGE_PM_OUT_CTRL_FUNCTIONAL 0
-#define BCHP_HIF_TOP_CTRL_PM_CTRL3_SDIO_VOLTAGE_PM_OUT_CTRL_LOW 1
-#define BCHP_HIF_TOP_CTRL_PM_CTRL3_SDIO_VOLTAGE_PM_OUT_CTRL_HIGH 2
-#define BCHP_HIF_TOP_CTRL_PM_CTRL3_SDIO_VOLTAGE_PM_OUT_CTRL_Tristate 3
-
-/* HIF_TOP_CTRL :: PM_CTRL3 :: SDIO_POWER_PM_OUT_CTRL [09:08] */
-#define BCHP_HIF_TOP_CTRL_PM_CTRL3_SDIO_POWER_PM_OUT_CTRL_MASK 0x00000300
-#define BCHP_HIF_TOP_CTRL_PM_CTRL3_SDIO_POWER_PM_OUT_CTRL_SHIFT 8
-#define BCHP_HIF_TOP_CTRL_PM_CTRL3_SDIO_POWER_PM_OUT_CTRL_DEFAULT 0x00000000
-#define BCHP_HIF_TOP_CTRL_PM_CTRL3_SDIO_POWER_PM_OUT_CTRL_FUNCTIONAL 0
-#define BCHP_HIF_TOP_CTRL_PM_CTRL3_SDIO_POWER_PM_OUT_CTRL_LOW 1
-#define BCHP_HIF_TOP_CTRL_PM_CTRL3_SDIO_POWER_PM_OUT_CTRL_HIGH 2
-#define BCHP_HIF_TOP_CTRL_PM_CTRL3_SDIO_POWER_PM_OUT_CTRL_Tristate 3
-
-/* HIF_TOP_CTRL :: PM_CTRL3 :: SDIO_LED_PM_OUT_CTRL [07:06] */
-#define BCHP_HIF_TOP_CTRL_PM_CTRL3_SDIO_LED_PM_OUT_CTRL_MASK 0x000000c0
-#define BCHP_HIF_TOP_CTRL_PM_CTRL3_SDIO_LED_PM_OUT_CTRL_SHIFT 6
-#define BCHP_HIF_TOP_CTRL_PM_CTRL3_SDIO_LED_PM_OUT_CTRL_DEFAULT 0x00000000
-#define BCHP_HIF_TOP_CTRL_PM_CTRL3_SDIO_LED_PM_OUT_CTRL_FUNCTIONAL 0
-#define BCHP_HIF_TOP_CTRL_PM_CTRL3_SDIO_LED_PM_OUT_CTRL_LOW 1
-#define BCHP_HIF_TOP_CTRL_PM_CTRL3_SDIO_LED_PM_OUT_CTRL_HIGH 2
-#define BCHP_HIF_TOP_CTRL_PM_CTRL3_SDIO_LED_PM_OUT_CTRL_Tristate 3
-
-/* HIF_TOP_CTRL :: PM_CTRL3 :: SDIO_DATA_PM_OUT_CTRL [05:04] */
-#define BCHP_HIF_TOP_CTRL_PM_CTRL3_SDIO_DATA_PM_OUT_CTRL_MASK 0x00000030
-#define BCHP_HIF_TOP_CTRL_PM_CTRL3_SDIO_DATA_PM_OUT_CTRL_SHIFT 4
-#define BCHP_HIF_TOP_CTRL_PM_CTRL3_SDIO_DATA_PM_OUT_CTRL_DEFAULT 0x00000000
-#define BCHP_HIF_TOP_CTRL_PM_CTRL3_SDIO_DATA_PM_OUT_CTRL_FUNCTIONAL 0
-#define BCHP_HIF_TOP_CTRL_PM_CTRL3_SDIO_DATA_PM_OUT_CTRL_LOW 1
-#define BCHP_HIF_TOP_CTRL_PM_CTRL3_SDIO_DATA_PM_OUT_CTRL_HIGH 2
-#define BCHP_HIF_TOP_CTRL_PM_CTRL3_SDIO_DATA_PM_OUT_CTRL_Tristate 3
-
-/* HIF_TOP_CTRL :: PM_CTRL3 :: SDIO_CMD_PM_OUT_CTRL [03:02] */
-#define BCHP_HIF_TOP_CTRL_PM_CTRL3_SDIO_CMD_PM_OUT_CTRL_MASK 0x0000000c
-#define BCHP_HIF_TOP_CTRL_PM_CTRL3_SDIO_CMD_PM_OUT_CTRL_SHIFT 2
-#define BCHP_HIF_TOP_CTRL_PM_CTRL3_SDIO_CMD_PM_OUT_CTRL_DEFAULT 0x00000000
-#define BCHP_HIF_TOP_CTRL_PM_CTRL3_SDIO_CMD_PM_OUT_CTRL_FUNCTIONAL 0
-#define BCHP_HIF_TOP_CTRL_PM_CTRL3_SDIO_CMD_PM_OUT_CTRL_LOW 1
-#define BCHP_HIF_TOP_CTRL_PM_CTRL3_SDIO_CMD_PM_OUT_CTRL_HIGH 2
-#define BCHP_HIF_TOP_CTRL_PM_CTRL3_SDIO_CMD_PM_OUT_CTRL_Tristate 3
-
-/* HIF_TOP_CTRL :: PM_CTRL3 :: SDIO_CLK_PM_OUT_CTRL [01:00] */
-#define BCHP_HIF_TOP_CTRL_PM_CTRL3_SDIO_CLK_PM_OUT_CTRL_MASK 0x00000003
-#define BCHP_HIF_TOP_CTRL_PM_CTRL3_SDIO_CLK_PM_OUT_CTRL_SHIFT 0
-#define BCHP_HIF_TOP_CTRL_PM_CTRL3_SDIO_CLK_PM_OUT_CTRL_DEFAULT 0x00000000
-#define BCHP_HIF_TOP_CTRL_PM_CTRL3_SDIO_CLK_PM_OUT_CTRL_FUNCTIONAL 0
-#define BCHP_HIF_TOP_CTRL_PM_CTRL3_SDIO_CLK_PM_OUT_CTRL_LOW 1
-#define BCHP_HIF_TOP_CTRL_PM_CTRL3_SDIO_CLK_PM_OUT_CTRL_HIGH 2
-#define BCHP_HIF_TOP_CTRL_PM_CTRL3_SDIO_CLK_PM_OUT_CTRL_Tristate 3
-
-/***************************************************************************
- *FLASH_TYPE - HIF Decoded Flash Type
- ***************************************************************************/
-/* HIF_TOP_CTRL :: FLASH_TYPE :: reserved0 [31:03] */
-#define BCHP_HIF_TOP_CTRL_FLASH_TYPE_reserved0_MASK 0xfffffff8
-#define BCHP_HIF_TOP_CTRL_FLASH_TYPE_reserved0_SHIFT 3
-
-/* HIF_TOP_CTRL :: FLASH_TYPE :: InvalidStrap [02:02] */
-#define BCHP_HIF_TOP_CTRL_FLASH_TYPE_InvalidStrap_MASK 0x00000004
-#define BCHP_HIF_TOP_CTRL_FLASH_TYPE_InvalidStrap_SHIFT 2
-#define BCHP_HIF_TOP_CTRL_FLASH_TYPE_InvalidStrap_DEFAULT 0x00000000
-
-/* HIF_TOP_CTRL :: FLASH_TYPE :: FLASH_TYPE [01:00] */
-#define BCHP_HIF_TOP_CTRL_FLASH_TYPE_FLASH_TYPE_MASK 0x00000003
-#define BCHP_HIF_TOP_CTRL_FLASH_TYPE_FLASH_TYPE_SHIFT 0
-#define BCHP_HIF_TOP_CTRL_FLASH_TYPE_FLASH_TYPE_ParallelNOR 0
-#define BCHP_HIF_TOP_CTRL_FLASH_TYPE_FLASH_TYPE_Nand 1
-#define BCHP_HIF_TOP_CTRL_FLASH_TYPE_FLASH_TYPE_SerialNOR 2
-#define BCHP_HIF_TOP_CTRL_FLASH_TYPE_FLASH_TYPE_eMMC 3
-
-/***************************************************************************
- *CPU_MODE_CTRL - CPU MODE Control register (PUBLIC)
- ***************************************************************************/
-/* HIF_TOP_CTRL :: CPU_MODE_CTRL :: reserved0 [31:02] */
-#define BCHP_HIF_TOP_CTRL_CPU_MODE_CTRL_reserved0_MASK 0xfffffffc
-#define BCHP_HIF_TOP_CTRL_CPU_MODE_CTRL_reserved0_SHIFT 2
-
-/* HIF_TOP_CTRL :: CPU_MODE_CTRL :: CPU_MODE [01:00] */
-#define BCHP_HIF_TOP_CTRL_CPU_MODE_CTRL_CPU_MODE_MASK 0x00000003
-#define BCHP_HIF_TOP_CTRL_CPU_MODE_CTRL_CPU_MODE_SHIFT 0
-#define BCHP_HIF_TOP_CTRL_CPU_MODE_CTRL_CPU_MODE_DEFAULT 0x00000000
-#define BCHP_HIF_TOP_CTRL_CPU_MODE_CTRL_CPU_MODE_FullSMP 0
-#define BCHP_HIF_TOP_CTRL_CPU_MODE_CTRL_CPU_MODE_Sandbox_1_1 1
-#define BCHP_HIF_TOP_CTRL_CPU_MODE_CTRL_CPU_MODE_Sandbox_1_1_reserved2 2
-#define BCHP_HIF_TOP_CTRL_CPU_MODE_CTRL_CPU_MODE_Sandbox_1_1_reserved3 3
-
-/***************************************************************************
- *CPU_MODE_STATUS - CPU MODE Control status register (PUBLIC)
- ***************************************************************************/
-/* HIF_TOP_CTRL :: CPU_MODE_STATUS :: reserved0 [31:08] */
-#define BCHP_HIF_TOP_CTRL_CPU_MODE_STATUS_reserved0_MASK 0xffffff00
-#define BCHP_HIF_TOP_CTRL_CPU_MODE_STATUS_reserved0_SHIFT 8
-
-/* HIF_TOP_CTRL :: CPU_MODE_STATUS :: SPARE_STATUS [07:05] */
-#define BCHP_HIF_TOP_CTRL_CPU_MODE_STATUS_SPARE_STATUS_MASK 0x000000e0
-#define BCHP_HIF_TOP_CTRL_CPU_MODE_STATUS_SPARE_STATUS_SHIFT 5
-
-/* HIF_TOP_CTRL :: CPU_MODE_STATUS :: CPU_MODE_STATUS [04:03] */
-#define BCHP_HIF_TOP_CTRL_CPU_MODE_STATUS_CPU_MODE_STATUS_MASK 0x00000018
-#define BCHP_HIF_TOP_CTRL_CPU_MODE_STATUS_CPU_MODE_STATUS_SHIFT 3
-
-/* HIF_TOP_CTRL :: CPU_MODE_STATUS :: CPU_MODE_OTP [02:00] */
-#define BCHP_HIF_TOP_CTRL_CPU_MODE_STATUS_CPU_MODE_OTP_MASK 0x00000007
-#define BCHP_HIF_TOP_CTRL_CPU_MODE_STATUS_CPU_MODE_OTP_SHIFT 0
-
-/***************************************************************************
- *SCRATCH - HIF Scratch Register
- ***************************************************************************/
-/* HIF_TOP_CTRL :: SCRATCH :: SCRATCH_BITS [31:00] */
-#define BCHP_HIF_TOP_CTRL_SCRATCH_SCRATCH_BITS_MASK 0xffffffff
-#define BCHP_HIF_TOP_CTRL_SCRATCH_SCRATCH_BITS_SHIFT 0
-#define BCHP_HIF_TOP_CTRL_SCRATCH_SCRATCH_BITS_DEFAULT 0x00000000
-
-#endif /* #ifndef BCHP_HIF_TOP_CTRL_H__ */
-
-/* End of File */
diff --git a/include/linux/brcmstb/7439a0/bchp_irq0.h b/include/linux/brcmstb/7439a0/bchp_irq0.h
deleted file mode 100644
index d411e51..0000000
--- a/include/linux/brcmstb/7439a0/bchp_irq0.h
+++ /dev/null
@@ -1,184 +0,0 @@
-/***************************************************************************
- * Copyright (c) 1999-2013, Broadcom Corporation
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
- *
- * Module Description:
- * DO NOT EDIT THIS FILE DIRECTLY
- *
- * This module was generated magically with RDB from a source description
- * file. You must edit the source file for changes to be made to this file.
- *
- *
- * Date: Generated on Tue Apr 16 03:26:51 2013
- * MD5 Checksum d41d8cd98f00b204e9800998ecf8427e
- *
- * Compiled with: RDB Utility combo_header.pl
- * RDB Parser 3.0
- * unknown unknown
- * Perl Interpreter 5.008008
- * Operating System linux
- *
- * Revision History:
- *
- * $brcm_Log: $
- *
- ***************************************************************************/
-
-#ifndef BCHP_IRQ0_H__
-#define BCHP_IRQ0_H__
-
-/***************************************************************************
- *IRQ0 - Level 2 CPU Interrupt Enable/Status
- ***************************************************************************/
-#define BCHP_IRQ0_IRQEN 0x00406800 /* Interrupt Enable */
-#define BCHP_IRQ0_IRQSTAT 0x00406804 /* Interrupt Status */
-
-/***************************************************************************
- *IRQEN - Interrupt Enable
- ***************************************************************************/
-/* IRQ0 :: IRQEN :: reserved0 [31:12] */
-#define BCHP_IRQ0_IRQEN_reserved0_MASK 0xfffff000
-#define BCHP_IRQ0_IRQEN_reserved0_SHIFT 12
-
-/* IRQ0 :: IRQEN :: irb_irqen [11:11] */
-#define BCHP_IRQ0_IRQEN_irb_irqen_MASK 0x00000800
-#define BCHP_IRQ0_IRQEN_irb_irqen_SHIFT 11
-#define BCHP_IRQ0_IRQEN_irb_irqen_DEFAULT 0x00000000
-
-/* IRQ0 :: IRQEN :: gio_irqen [10:10] */
-#define BCHP_IRQ0_IRQEN_gio_irqen_MASK 0x00000400
-#define BCHP_IRQ0_IRQEN_gio_irqen_SHIFT 10
-#define BCHP_IRQ0_IRQEN_gio_irqen_DEFAULT 0x00000000
-
-/* IRQ0 :: IRQEN :: iicf_irqen [09:09] */
-#define BCHP_IRQ0_IRQEN_iicf_irqen_MASK 0x00000200
-#define BCHP_IRQ0_IRQEN_iicf_irqen_SHIFT 9
-#define BCHP_IRQ0_IRQEN_iicf_irqen_DEFAULT 0x00000000
-
-/* IRQ0 :: IRQEN :: iice_irqen [08:08] */
-#define BCHP_IRQ0_IRQEN_iice_irqen_MASK 0x00000100
-#define BCHP_IRQ0_IRQEN_iice_irqen_SHIFT 8
-#define BCHP_IRQ0_IRQEN_iice_irqen_DEFAULT 0x00000000
-
-/* IRQ0 :: IRQEN :: iicb_irqen [07:07] */
-#define BCHP_IRQ0_IRQEN_iicb_irqen_MASK 0x00000080
-#define BCHP_IRQ0_IRQEN_iicb_irqen_SHIFT 7
-#define BCHP_IRQ0_IRQEN_iicb_irqen_DEFAULT 0x00000000
-
-/* IRQ0 :: IRQEN :: iica_irqen [06:06] */
-#define BCHP_IRQ0_IRQEN_iica_irqen_MASK 0x00000040
-#define BCHP_IRQ0_IRQEN_iica_irqen_SHIFT 6
-#define BCHP_IRQ0_IRQEN_iica_irqen_DEFAULT 0x00000000
-
-/* IRQ0 :: IRQEN :: uc_irqen [05:05] */
-#define BCHP_IRQ0_IRQEN_uc_irqen_MASK 0x00000020
-#define BCHP_IRQ0_IRQEN_uc_irqen_SHIFT 5
-#define BCHP_IRQ0_IRQEN_uc_irqen_DEFAULT 0x00000000
-
-/* IRQ0 :: IRQEN :: ub_irqen [04:04] */
-#define BCHP_IRQ0_IRQEN_ub_irqen_MASK 0x00000010
-#define BCHP_IRQ0_IRQEN_ub_irqen_SHIFT 4
-#define BCHP_IRQ0_IRQEN_ub_irqen_DEFAULT 0x00000000
-
-/* IRQ0 :: IRQEN :: ua_irqen [03:03] */
-#define BCHP_IRQ0_IRQEN_ua_irqen_MASK 0x00000008
-#define BCHP_IRQ0_IRQEN_ua_irqen_SHIFT 3
-#define BCHP_IRQ0_IRQEN_ua_irqen_DEFAULT 0x00000000
-
-/* IRQ0 :: IRQEN :: uartc_irqen [02:02] */
-#define BCHP_IRQ0_IRQEN_uartc_irqen_MASK 0x00000004
-#define BCHP_IRQ0_IRQEN_uartc_irqen_SHIFT 2
-#define BCHP_IRQ0_IRQEN_uartc_irqen_DEFAULT 0x00000000
-
-/* IRQ0 :: IRQEN :: uartb_irqen [01:01] */
-#define BCHP_IRQ0_IRQEN_uartb_irqen_MASK 0x00000002
-#define BCHP_IRQ0_IRQEN_uartb_irqen_SHIFT 1
-#define BCHP_IRQ0_IRQEN_uartb_irqen_DEFAULT 0x00000000
-
-/* IRQ0 :: IRQEN :: uarta_irqen [00:00] */
-#define BCHP_IRQ0_IRQEN_uarta_irqen_MASK 0x00000001
-#define BCHP_IRQ0_IRQEN_uarta_irqen_SHIFT 0
-#define BCHP_IRQ0_IRQEN_uarta_irqen_DEFAULT 0x00000000
-
-/***************************************************************************
- *IRQSTAT - Interrupt Status
- ***************************************************************************/
-/* IRQ0 :: IRQSTAT :: reserved0 [31:12] */
-#define BCHP_IRQ0_IRQSTAT_reserved0_MASK 0xfffff000
-#define BCHP_IRQ0_IRQSTAT_reserved0_SHIFT 12
-
-/* IRQ0 :: IRQSTAT :: irbirq [11:11] */
-#define BCHP_IRQ0_IRQSTAT_irbirq_MASK 0x00000800
-#define BCHP_IRQ0_IRQSTAT_irbirq_SHIFT 11
-#define BCHP_IRQ0_IRQSTAT_irbirq_DEFAULT 0x00000000
-
-/* IRQ0 :: IRQSTAT :: gioirq [10:10] */
-#define BCHP_IRQ0_IRQSTAT_gioirq_MASK 0x00000400
-#define BCHP_IRQ0_IRQSTAT_gioirq_SHIFT 10
-#define BCHP_IRQ0_IRQSTAT_gioirq_DEFAULT 0x00000000
-
-/* IRQ0 :: IRQSTAT :: iicfirq [09:09] */
-#define BCHP_IRQ0_IRQSTAT_iicfirq_MASK 0x00000200
-#define BCHP_IRQ0_IRQSTAT_iicfirq_SHIFT 9
-#define BCHP_IRQ0_IRQSTAT_iicfirq_DEFAULT 0x00000000
-
-/* IRQ0 :: IRQSTAT :: iiceirq [08:08] */
-#define BCHP_IRQ0_IRQSTAT_iiceirq_MASK 0x00000100
-#define BCHP_IRQ0_IRQSTAT_iiceirq_SHIFT 8
-#define BCHP_IRQ0_IRQSTAT_iiceirq_DEFAULT 0x00000000
-
-/* IRQ0 :: IRQSTAT :: iicbirq [07:07] */
-#define BCHP_IRQ0_IRQSTAT_iicbirq_MASK 0x00000080
-#define BCHP_IRQ0_IRQSTAT_iicbirq_SHIFT 7
-#define BCHP_IRQ0_IRQSTAT_iicbirq_DEFAULT 0x00000000
-
-/* IRQ0 :: IRQSTAT :: iicairq [06:06] */
-#define BCHP_IRQ0_IRQSTAT_iicairq_MASK 0x00000040
-#define BCHP_IRQ0_IRQSTAT_iicairq_SHIFT 6
-#define BCHP_IRQ0_IRQSTAT_iicairq_DEFAULT 0x00000000
-
-/* IRQ0 :: IRQSTAT :: ucirq [05:05] */
-#define BCHP_IRQ0_IRQSTAT_ucirq_MASK 0x00000020
-#define BCHP_IRQ0_IRQSTAT_ucirq_SHIFT 5
-#define BCHP_IRQ0_IRQSTAT_ucirq_DEFAULT 0x00000000
-
-/* IRQ0 :: IRQSTAT :: ubirq [04:04] */
-#define BCHP_IRQ0_IRQSTAT_ubirq_MASK 0x00000010
-#define BCHP_IRQ0_IRQSTAT_ubirq_SHIFT 4
-#define BCHP_IRQ0_IRQSTAT_ubirq_DEFAULT 0x00000000
-
-/* IRQ0 :: IRQSTAT :: uairq [03:03] */
-#define BCHP_IRQ0_IRQSTAT_uairq_MASK 0x00000008
-#define BCHP_IRQ0_IRQSTAT_uairq_SHIFT 3
-#define BCHP_IRQ0_IRQSTAT_uairq_DEFAULT 0x00000000
-
-/* IRQ0 :: IRQSTAT :: uartc_irq [02:02] */
-#define BCHP_IRQ0_IRQSTAT_uartc_irq_MASK 0x00000004
-#define BCHP_IRQ0_IRQSTAT_uartc_irq_SHIFT 2
-#define BCHP_IRQ0_IRQSTAT_uartc_irq_DEFAULT 0x00000000
-
-/* IRQ0 :: IRQSTAT :: uartb_irq [01:01] */
-#define BCHP_IRQ0_IRQSTAT_uartb_irq_MASK 0x00000002
-#define BCHP_IRQ0_IRQSTAT_uartb_irq_SHIFT 1
-#define BCHP_IRQ0_IRQSTAT_uartb_irq_DEFAULT 0x00000000
-
-/* IRQ0 :: IRQSTAT :: uarta_irq [00:00] */
-#define BCHP_IRQ0_IRQSTAT_uarta_irq_MASK 0x00000001
-#define BCHP_IRQ0_IRQSTAT_uarta_irq_SHIFT 0
-#define BCHP_IRQ0_IRQSTAT_uarta_irq_DEFAULT 0x00000000
-
-#endif /* #ifndef BCHP_IRQ0_H__ */
-
-/* End of File */
diff --git a/include/linux/brcmstb/7439a0/bchp_irq1.h b/include/linux/brcmstb/7439a0/bchp_irq1.h
deleted file mode 100644
index 1b1cd19..0000000
--- a/include/linux/brcmstb/7439a0/bchp_irq1.h
+++ /dev/null
@@ -1,184 +0,0 @@
-/***************************************************************************
- * Copyright (c) 1999-2013, Broadcom Corporation
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
- *
- * Module Description:
- * DO NOT EDIT THIS FILE DIRECTLY
- *
- * This module was generated magically with RDB from a source description
- * file. You must edit the source file for changes to be made to this file.
- *
- *
- * Date: Generated on Tue Apr 16 03:26:50 2013
- * MD5 Checksum d41d8cd98f00b204e9800998ecf8427e
- *
- * Compiled with: RDB Utility combo_header.pl
- * RDB Parser 3.0
- * unknown unknown
- * Perl Interpreter 5.008008
- * Operating System linux
- *
- * Revision History:
- *
- * $brcm_Log: $
- *
- ***************************************************************************/
-
-#ifndef BCHP_IRQ1_H__
-#define BCHP_IRQ1_H__
-
-/***************************************************************************
- *IRQ1 - Level 2 PCI Interrupt Enable/Status
- ***************************************************************************/
-#define BCHP_IRQ1_IRQEN 0x00406808 /* Interrupt Enable */
-#define BCHP_IRQ1_IRQSTAT 0x0040680c /* Interrupt Status */
-
-/***************************************************************************
- *IRQEN - Interrupt Enable
- ***************************************************************************/
-/* IRQ1 :: IRQEN :: reserved0 [31:12] */
-#define BCHP_IRQ1_IRQEN_reserved0_MASK 0xfffff000
-#define BCHP_IRQ1_IRQEN_reserved0_SHIFT 12
-
-/* IRQ1 :: IRQEN :: irb_irqen [11:11] */
-#define BCHP_IRQ1_IRQEN_irb_irqen_MASK 0x00000800
-#define BCHP_IRQ1_IRQEN_irb_irqen_SHIFT 11
-#define BCHP_IRQ1_IRQEN_irb_irqen_DEFAULT 0x00000000
-
-/* IRQ1 :: IRQEN :: gio_irqen [10:10] */
-#define BCHP_IRQ1_IRQEN_gio_irqen_MASK 0x00000400
-#define BCHP_IRQ1_IRQEN_gio_irqen_SHIFT 10
-#define BCHP_IRQ1_IRQEN_gio_irqen_DEFAULT 0x00000000
-
-/* IRQ1 :: IRQEN :: iicf_irqen [09:09] */
-#define BCHP_IRQ1_IRQEN_iicf_irqen_MASK 0x00000200
-#define BCHP_IRQ1_IRQEN_iicf_irqen_SHIFT 9
-#define BCHP_IRQ1_IRQEN_iicf_irqen_DEFAULT 0x00000000
-
-/* IRQ1 :: IRQEN :: iice_irqen [08:08] */
-#define BCHP_IRQ1_IRQEN_iice_irqen_MASK 0x00000100
-#define BCHP_IRQ1_IRQEN_iice_irqen_SHIFT 8
-#define BCHP_IRQ1_IRQEN_iice_irqen_DEFAULT 0x00000000
-
-/* IRQ1 :: IRQEN :: iicb_irqen [07:07] */
-#define BCHP_IRQ1_IRQEN_iicb_irqen_MASK 0x00000080
-#define BCHP_IRQ1_IRQEN_iicb_irqen_SHIFT 7
-#define BCHP_IRQ1_IRQEN_iicb_irqen_DEFAULT 0x00000000
-
-/* IRQ1 :: IRQEN :: iica_irqen [06:06] */
-#define BCHP_IRQ1_IRQEN_iica_irqen_MASK 0x00000040
-#define BCHP_IRQ1_IRQEN_iica_irqen_SHIFT 6
-#define BCHP_IRQ1_IRQEN_iica_irqen_DEFAULT 0x00000000
-
-/* IRQ1 :: IRQEN :: uc_irqen [05:05] */
-#define BCHP_IRQ1_IRQEN_uc_irqen_MASK 0x00000020
-#define BCHP_IRQ1_IRQEN_uc_irqen_SHIFT 5
-#define BCHP_IRQ1_IRQEN_uc_irqen_DEFAULT 0x00000000
-
-/* IRQ1 :: IRQEN :: ub_irqen [04:04] */
-#define BCHP_IRQ1_IRQEN_ub_irqen_MASK 0x00000010
-#define BCHP_IRQ1_IRQEN_ub_irqen_SHIFT 4
-#define BCHP_IRQ1_IRQEN_ub_irqen_DEFAULT 0x00000000
-
-/* IRQ1 :: IRQEN :: ua_irqen [03:03] */
-#define BCHP_IRQ1_IRQEN_ua_irqen_MASK 0x00000008
-#define BCHP_IRQ1_IRQEN_ua_irqen_SHIFT 3
-#define BCHP_IRQ1_IRQEN_ua_irqen_DEFAULT 0x00000000
-
-/* IRQ1 :: IRQEN :: uartc_irqen [02:02] */
-#define BCHP_IRQ1_IRQEN_uartc_irqen_MASK 0x00000004
-#define BCHP_IRQ1_IRQEN_uartc_irqen_SHIFT 2
-#define BCHP_IRQ1_IRQEN_uartc_irqen_DEFAULT 0x00000000
-
-/* IRQ1 :: IRQEN :: uartb_irqen [01:01] */
-#define BCHP_IRQ1_IRQEN_uartb_irqen_MASK 0x00000002
-#define BCHP_IRQ1_IRQEN_uartb_irqen_SHIFT 1
-#define BCHP_IRQ1_IRQEN_uartb_irqen_DEFAULT 0x00000000
-
-/* IRQ1 :: IRQEN :: uarta_irqen [00:00] */
-#define BCHP_IRQ1_IRQEN_uarta_irqen_MASK 0x00000001
-#define BCHP_IRQ1_IRQEN_uarta_irqen_SHIFT 0
-#define BCHP_IRQ1_IRQEN_uarta_irqen_DEFAULT 0x00000000
-
-/***************************************************************************
- *IRQSTAT - Interrupt Status
- ***************************************************************************/
-/* IRQ1 :: IRQSTAT :: reserved0 [31:12] */
-#define BCHP_IRQ1_IRQSTAT_reserved0_MASK 0xfffff000
-#define BCHP_IRQ1_IRQSTAT_reserved0_SHIFT 12
-
-/* IRQ1 :: IRQSTAT :: irbirq [11:11] */
-#define BCHP_IRQ1_IRQSTAT_irbirq_MASK 0x00000800
-#define BCHP_IRQ1_IRQSTAT_irbirq_SHIFT 11
-#define BCHP_IRQ1_IRQSTAT_irbirq_DEFAULT 0x00000000
-
-/* IRQ1 :: IRQSTAT :: gioirq [10:10] */
-#define BCHP_IRQ1_IRQSTAT_gioirq_MASK 0x00000400
-#define BCHP_IRQ1_IRQSTAT_gioirq_SHIFT 10
-#define BCHP_IRQ1_IRQSTAT_gioirq_DEFAULT 0x00000000
-
-/* IRQ1 :: IRQSTAT :: iicfirq [09:09] */
-#define BCHP_IRQ1_IRQSTAT_iicfirq_MASK 0x00000200
-#define BCHP_IRQ1_IRQSTAT_iicfirq_SHIFT 9
-#define BCHP_IRQ1_IRQSTAT_iicfirq_DEFAULT 0x00000000
-
-/* IRQ1 :: IRQSTAT :: iiceirq [08:08] */
-#define BCHP_IRQ1_IRQSTAT_iiceirq_MASK 0x00000100
-#define BCHP_IRQ1_IRQSTAT_iiceirq_SHIFT 8
-#define BCHP_IRQ1_IRQSTAT_iiceirq_DEFAULT 0x00000000
-
-/* IRQ1 :: IRQSTAT :: iicbirq [07:07] */
-#define BCHP_IRQ1_IRQSTAT_iicbirq_MASK 0x00000080
-#define BCHP_IRQ1_IRQSTAT_iicbirq_SHIFT 7
-#define BCHP_IRQ1_IRQSTAT_iicbirq_DEFAULT 0x00000000
-
-/* IRQ1 :: IRQSTAT :: iicairq [06:06] */
-#define BCHP_IRQ1_IRQSTAT_iicairq_MASK 0x00000040
-#define BCHP_IRQ1_IRQSTAT_iicairq_SHIFT 6
-#define BCHP_IRQ1_IRQSTAT_iicairq_DEFAULT 0x00000000
-
-/* IRQ1 :: IRQSTAT :: ucirq [05:05] */
-#define BCHP_IRQ1_IRQSTAT_ucirq_MASK 0x00000020
-#define BCHP_IRQ1_IRQSTAT_ucirq_SHIFT 5
-#define BCHP_IRQ1_IRQSTAT_ucirq_DEFAULT 0x00000000
-
-/* IRQ1 :: IRQSTAT :: ubirq [04:04] */
-#define BCHP_IRQ1_IRQSTAT_ubirq_MASK 0x00000010
-#define BCHP_IRQ1_IRQSTAT_ubirq_SHIFT 4
-#define BCHP_IRQ1_IRQSTAT_ubirq_DEFAULT 0x00000000
-
-/* IRQ1 :: IRQSTAT :: uairq [03:03] */
-#define BCHP_IRQ1_IRQSTAT_uairq_MASK 0x00000008
-#define BCHP_IRQ1_IRQSTAT_uairq_SHIFT 3
-#define BCHP_IRQ1_IRQSTAT_uairq_DEFAULT 0x00000000
-
-/* IRQ1 :: IRQSTAT :: uartc_irq [02:02] */
-#define BCHP_IRQ1_IRQSTAT_uartc_irq_MASK 0x00000004
-#define BCHP_IRQ1_IRQSTAT_uartc_irq_SHIFT 2
-#define BCHP_IRQ1_IRQSTAT_uartc_irq_DEFAULT 0x00000000
-
-/* IRQ1 :: IRQSTAT :: uartb_irq [01:01] */
-#define BCHP_IRQ1_IRQSTAT_uartb_irq_MASK 0x00000002
-#define BCHP_IRQ1_IRQSTAT_uartb_irq_SHIFT 1
-#define BCHP_IRQ1_IRQSTAT_uartb_irq_DEFAULT 0x00000000
-
-/* IRQ1 :: IRQSTAT :: uarta_irq [00:00] */
-#define BCHP_IRQ1_IRQSTAT_uarta_irq_MASK 0x00000001
-#define BCHP_IRQ1_IRQSTAT_uarta_irq_SHIFT 0
-#define BCHP_IRQ1_IRQSTAT_uarta_irq_DEFAULT 0x00000000
-
-#endif /* #ifndef BCHP_IRQ1_H__ */
-
-/* End of File */
diff --git a/include/linux/brcmstb/7439a0/bchp_memc_ddr_0.h b/include/linux/brcmstb/7439a0/bchp_memc_ddr_0.h
deleted file mode 100644
index 974415a..0000000
--- a/include/linux/brcmstb/7439a0/bchp_memc_ddr_0.h
+++ /dev/null
@@ -1,4762 +0,0 @@
-/***************************************************************************
- * Copyright (c) 1999-2013, Broadcom Corporation
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
- *
- * Module Description:
- * DO NOT EDIT THIS FILE DIRECTLY
- *
- * This module was generated magically with RDB from a source description
- * file. You must edit the source file for changes to be made to this file.
- *
- *
- * Date: Generated on Tue Apr 16 03:26:50 2013
- * MD5 Checksum d41d8cd98f00b204e9800998ecf8427e
- *
- * Compiled with: RDB Utility combo_header.pl
- * RDB Parser 3.0
- * unknown unknown
- * Perl Interpreter 5.008008
- * Operating System linux
- *
- * Revision History:
- *
- * $brcm_Log: $
- *
- ***************************************************************************/
-
-#ifndef BCHP_MEMC_DDR_0_H__
-#define BCHP_MEMC_DDR_0_H__
-
-/***************************************************************************
- *MEMC_DDR_0 - 0 Sequencer DRAM Param and Control Registers
- ***************************************************************************/
-#define BCHP_MEMC_DDR_0_CNTRLR_CONFIG 0x00902000 /* Memory Controller Configuration Register */
-#define BCHP_MEMC_DDR_0_CNTRLR_CONFIG_STATUS 0x00902004 /* Memory Controller Configuration Status Register */
-#define BCHP_MEMC_DDR_0_DRAM_INIT_CNTRL 0x00902008 /* Dram initialization control */
-#define BCHP_MEMC_DDR_0_DRAM_INIT_STATUS 0x0090200c /* Dram initialization status */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_0 0x00902010 /* Dram Mode Register 0 */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_1 0x00902014 /* Dram Mode Register 1 */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_2 0x00902018 /* Dram Mode Register 2 */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_3 0x0090201c /* Dram Mode Register 3 */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_4 0x00902020 /* Dram Mode Register 4 */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_5 0x00902024 /* Dram Mode Register 5 */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_6 0x00902028 /* Dram Mode Register 6 */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_7 0x0090202c /* Dram Mode Register 7 */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_8 0x00902030 /* Dram Mode Register 8 */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_15 0x00902034 /* Dram Mode Register 15 */
-#define BCHP_MEMC_DDR_0_PPD_CONFIG 0x00902038 /* Precharge power down mode configuration register */
-#define BCHP_MEMC_DDR_0_SRPD_CONFIG 0x0090203c /* Self-refresh power down mode configuration register */
-#define BCHP_MEMC_DDR_0_SSPD_CMD 0x00902040 /* Software standby power down mode */
-#define BCHP_MEMC_DDR_0_POWER_DOWN_STATUS 0x00902044 /* Power down status */
-#define BCHP_MEMC_DDR_0_WARM_BOOT 0x00902048 /* Warm boot control registers */
-#define BCHP_MEMC_DDR_0_DRAM_TIMING_0 0x0090204c /* DDR-SDRAM Timing Register 0 */
-#define BCHP_MEMC_DDR_0_DRAM_TIMING_1 0x00902050 /* DDR-SDRAM Timing Register 1 */
-#define BCHP_MEMC_DDR_0_DRAM_TIMING_2 0x00902054 /* Read to Write & write to read timing register */
-#define BCHP_MEMC_DDR_0_DRAM_TIMING_3 0x00902058 /* DDR-SDRAM Timing Register 3 */
-#define BCHP_MEMC_DDR_0_DRAM_TIMING_4 0x0090205c /* DDR-SDRAM Timing Register 4 */
-#define BCHP_MEMC_DDR_0_DRAM_TIMING_5 0x00902060 /* DDR-SDRAM Timing Register 5 */
-#define BCHP_MEMC_DDR_0_MIN_DQ_IDLE_CONTROL 0x00902064 /* Minimum DQ Idle Time Control */
-#define BCHP_MEMC_DDR_0_PHY_OP_ACCESS_PENALTY 0x00902068 /* PHY Operational Access Penalty Count. */
-#define BCHP_MEMC_DDR_0_CNTRLR_SM_TIMEOUT 0x0090206c /* Memory Controller , state machine timeout register. */
-#define BCHP_MEMC_DDR_0_BANK_STATUS 0x00902070 /* Memory Controller, Bank Status Register */
-#define BCHP_MEMC_DDR_0_TESTER_LATENCY 0x00902074 /* Memory Controller, Tester Latency Register. */
-#define BCHP_MEMC_DDR_0_SEQ_RING_BUF_DEPTH 0x00902078 /* Sequencer Ring Buffer programmable depth. */
-#define BCHP_MEMC_DDR_0_SEQ_WRDATA_ERR_INFO 0x0090207c /* Sequencer write data error info */
-#define BCHP_MEMC_DDR_0_SEQ_WRDATA_TRANSID_MISMATCH_INFO 0x00902080 /* Sequencer transaction ID mismatch error info */
-#define BCHP_MEMC_DDR_0_SEQ_CLEAR_VIOLATIONS 0x00902084 /* Sequencer Violation Info register clear. */
-#define BCHP_MEMC_DDR_0_STAT_CONTROL 0x00902088 /* Statistics Control register */
-#define BCHP_MEMC_DDR_0_STAT_TIMER 0x0090208c /* Statistics Timer */
-#define BCHP_MEMC_DDR_0_STAT_IDLE_NOP 0x00902090 /* DRAM Idle_NOP Cycle Count Register. */
-#define BCHP_MEMC_DDR_0_STAT_MAX_IDLE_NOP 0x00902094 /* Maximum DRAM idle_NOP cycle count register. */
-#define BCHP_MEMC_DDR_0_STAT_MIN_IDLE_NOP 0x00902098 /* Minimum DRAM idle_NOP cycle count register. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_ALL 0x0090209c /* CAS Count Register. */
-#define BCHP_MEMC_DDR_0_STAT_MAX_CAS_ALL 0x009020a0 /* Maximum DRAM CAS cycle count register. */
-#define BCHP_MEMC_DDR_0_STAT_MIN_CAS_ALL 0x009020a4 /* Minimum DRAM CAS cycle count register. */
-#define BCHP_MEMC_DDR_0_STAT_PENALTY_ALL 0x009020a8 /* DRAM Penalty Cycle Count register. */
-#define BCHP_MEMC_DDR_0_STAT_PENALTY_GDDRWM 0x009020ac /* GDDR Write Mask Penalty Cycle Count register. */
-#define BCHP_MEMC_DDR_0_STAT_MAX_TRANS_CYCLES_ALL 0x009020b0 /* Maximum number of transactions cycles (CAS+Penalty_ALL). */
-#define BCHP_MEMC_DDR_0_STAT_MIN_TRANS_CYCLES_ALL 0x009020b4 /* Minimum number of transactions cycles (CAS+Penalty_ALL). */
-#define BCHP_MEMC_DDR_0_STAT_TRANS_READ_ALL 0x009020b8 /* Number of overall system memory read transactions. */
-#define BCHP_MEMC_DDR_0_STAT_TRANS_WRITE_ALL 0x009020bc /* Number of overall system memory write transactions. */
-#define BCHP_MEMC_DDR_0_STAT_MAX_TRANS_ALL 0x009020c0 /* Maximum Number of Overall System memory transactions. */
-#define BCHP_MEMC_DDR_0_STAT_MIN_TRANS_ALL 0x009020c4 /* Minimum Number of Overall System memory transactions. */
-#define BCHP_MEMC_DDR_0_STAT_CLIENT_SERVICE_CAS 0x009020c8 /* Service CAS Cycle Count register. */
-#define BCHP_MEMC_DDR_0_STAT_MAX_CLIENT_SERVICE_CAS 0x009020cc /* Maximum service CAS cycle count register. */
-#define BCHP_MEMC_DDR_0_STAT_MIN_CLIENT_SERVICE_CAS 0x009020d0 /* Minimum service CAS cycle count register. */
-#define BCHP_MEMC_DDR_0_STAT_CLIENT_SERVICE_INTR_PENALTY 0x009020d4 /* Service Intra DRAM Penalty Cycle Count register. */
-#define BCHP_MEMC_DDR_0_STAT_CLIENT_SERVICE_POST_PENALTY 0x009020d8 /* Service Post DRAM Penalty Cycle Count register. */
-#define BCHP_MEMC_DDR_0_STAT_CLIENT_SERVICE_GDDRWM_PENALTY 0x009020dc /* Service GDDR Write Mask Penalty Cycle Count register. */
-#define BCHP_MEMC_DDR_0_STAT_MAX_CLIENT_SERVICE_CYCLES 0x009020e0 /* Maximum service cycle count register. */
-#define BCHP_MEMC_DDR_0_STAT_MIN_CLIENT_SERVICE_CYCLES 0x009020e4 /* Minimum service cycle count register. */
-#define BCHP_MEMC_DDR_0_STAT_CLIENT_SERVICE_TRANS_READ 0x009020e8 /* Service Read Transaction Count register. */
-#define BCHP_MEMC_DDR_0_STAT_CLIENT_SERVICE_TRANS_WRITE 0x009020ec /* Service Write Transaction Count register. */
-#define BCHP_MEMC_DDR_0_STAT_MAX_CLIENT_SERVICE_TRANS 0x009020f0 /* Maximum service Transaction count register. */
-#define BCHP_MEMC_DDR_0_STAT_MIN_CLIENT_SERVICE_TRANS 0x009020f4 /* Minimum service cycle Transaction register. */
-#define BCHP_MEMC_DDR_0_STAT_CLIENT_SERVICE_LATENCY 0x009020f8 /* Service Latency Count register. */
-#define BCHP_MEMC_DDR_0_STAT_MAX_CLIENT_SERVICE_LATENCY 0x009020fc /* Maximum Service Latency count register. */
-#define BCHP_MEMC_DDR_0_STAT_MIN_CLIENT_SERVICE_LATENCY 0x00902100 /* Minimum Service Latency count register. */
-#define BCHP_MEMC_DDR_0_STAT_CLIENT_ABS_MAX_SERVICE_LATENCY 0x00902104 /* Absolute Minimum Service Latency count register. */
-#define BCHP_MEMC_DDR_0_STAT_CLIENT_ABS_MIN_SERVICE_LATENCY 0x00902108 /* Absolute Maximum Service Latency count register. */
-#define BCHP_MEMC_DDR_0_STAT_REFRESH 0x0090210c /* Total number of refreshes issued. */
-#define BCHP_MEMC_DDR_0_STAT_MIN_DQ_IDLE_WRITE 0x00902110 /* Min DQ Idle Write event counter */
-#define BCHP_MEMC_DDR_0_STAT_MIN_DQ_IDLE_READ 0x00902114 /* Min DQ Idle Read event counter */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_0 0x00902400 /* CAS or consumption cycle count register for client 0. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_1 0x00902404 /* CAS or consumption cycle count register for client 1. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_2 0x00902408 /* CAS or consumption cycle count register for client 2. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_3 0x0090240c /* CAS or consumption cycle count register for client 3. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_4 0x00902410 /* CAS or consumption cycle count register for client 4. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_5 0x00902414 /* CAS or consumption cycle count register for client 5. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_6 0x00902418 /* CAS or consumption cycle count register for client 6. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_7 0x0090241c /* CAS or consumption cycle count register for client 7. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_8 0x00902420 /* CAS or consumption cycle count register for client 8. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_9 0x00902424 /* CAS or consumption cycle count register for client 9. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_10 0x00902428 /* CAS or consumption cycle count register for client 10. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_11 0x0090242c /* CAS or consumption cycle count register for client 11. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_12 0x00902430 /* CAS or consumption cycle count register for client 12. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_13 0x00902434 /* CAS or consumption cycle count register for client 13. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_14 0x00902438 /* CAS or consumption cycle count register for client 14. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_15 0x0090243c /* CAS or consumption cycle count register for client 15. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_16 0x00902440 /* CAS or consumption cycle count register for client 16. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_17 0x00902444 /* CAS or consumption cycle count register for client 17. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_18 0x00902448 /* CAS or consumption cycle count register for client 18. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_19 0x0090244c /* CAS or consumption cycle count register for client 19. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_20 0x00902450 /* CAS or consumption cycle count register for client 20. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_21 0x00902454 /* CAS or consumption cycle count register for client 21. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_22 0x00902458 /* CAS or consumption cycle count register for client 22. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_23 0x0090245c /* CAS or consumption cycle count register for client 23. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_24 0x00902460 /* CAS or consumption cycle count register for client 24. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_25 0x00902464 /* CAS or consumption cycle count register for client 25. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_26 0x00902468 /* CAS or consumption cycle count register for client 26. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_27 0x0090246c /* CAS or consumption cycle count register for client 27. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_28 0x00902470 /* CAS or consumption cycle count register for client 28. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_29 0x00902474 /* CAS or consumption cycle count register for client 29. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_30 0x00902478 /* CAS or consumption cycle count register for client 30. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_31 0x0090247c /* CAS or consumption cycle count register for client 31. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_32 0x00902480 /* CAS or consumption cycle count register for client 32. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_33 0x00902484 /* CAS or consumption cycle count register for client 33. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_34 0x00902488 /* CAS or consumption cycle count register for client 34. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_35 0x0090248c /* CAS or consumption cycle count register for client 35. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_36 0x00902490 /* CAS or consumption cycle count register for client 36. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_37 0x00902494 /* CAS or consumption cycle count register for client 37. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_38 0x00902498 /* CAS or consumption cycle count register for client 38. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_39 0x0090249c /* CAS or consumption cycle count register for client 39. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_40 0x009024a0 /* CAS or consumption cycle count register for client 40. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_41 0x009024a4 /* CAS or consumption cycle count register for client 41. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_42 0x009024a8 /* CAS or consumption cycle count register for client 42. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_43 0x009024ac /* CAS or consumption cycle count register for client 43. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_44 0x009024b0 /* CAS or consumption cycle count register for client 44. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_45 0x009024b4 /* CAS or consumption cycle count register for client 45. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_46 0x009024b8 /* CAS or consumption cycle count register for client 46. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_47 0x009024bc /* CAS or consumption cycle count register for client 47. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_48 0x009024c0 /* CAS or consumption cycle count register for client 48. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_49 0x009024c4 /* CAS or consumption cycle count register for client 49. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_50 0x009024c8 /* CAS or consumption cycle count register for client 50. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_51 0x009024cc /* CAS or consumption cycle count register for client 51. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_52 0x009024d0 /* CAS or consumption cycle count register for client 52. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_53 0x009024d4 /* CAS or consumption cycle count register for client 53. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_54 0x009024d8 /* CAS or consumption cycle count register for client 54. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_55 0x009024dc /* CAS or consumption cycle count register for client 55. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_56 0x009024e0 /* CAS or consumption cycle count register for client 56. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_57 0x009024e4 /* CAS or consumption cycle count register for client 57. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_58 0x009024e8 /* CAS or consumption cycle count register for client 58. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_59 0x009024ec /* CAS or consumption cycle count register for client 59. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_60 0x009024f0 /* CAS or consumption cycle count register for client 60. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_61 0x009024f4 /* CAS or consumption cycle count register for client 61. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_62 0x009024f8 /* CAS or consumption cycle count register for client 62. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_63 0x009024fc /* CAS or consumption cycle count register for client 63. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_64 0x00902500 /* CAS or consumption cycle count register for client 64. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_65 0x00902504 /* CAS or consumption cycle count register for client 65. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_66 0x00902508 /* CAS or consumption cycle count register for client 66. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_67 0x0090250c /* CAS or consumption cycle count register for client 67. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_68 0x00902510 /* CAS or consumption cycle count register for client 68. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_69 0x00902514 /* CAS or consumption cycle count register for client 69. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_70 0x00902518 /* CAS or consumption cycle count register for client 70. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_71 0x0090251c /* CAS or consumption cycle count register for client 71. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_72 0x00902520 /* CAS or consumption cycle count register for client 72. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_73 0x00902524 /* CAS or consumption cycle count register for client 73. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_74 0x00902528 /* CAS or consumption cycle count register for client 74. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_75 0x0090252c /* CAS or consumption cycle count register for client 75. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_76 0x00902530 /* CAS or consumption cycle count register for client 76. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_77 0x00902534 /* CAS or consumption cycle count register for client 77. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_78 0x00902538 /* CAS or consumption cycle count register for client 78. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_79 0x0090253c /* CAS or consumption cycle count register for client 79. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_80 0x00902540 /* CAS or consumption cycle count register for client 80. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_81 0x00902544 /* CAS or consumption cycle count register for client 81. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_82 0x00902548 /* CAS or consumption cycle count register for client 82. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_83 0x0090254c /* CAS or consumption cycle count register for client 83. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_84 0x00902550 /* CAS or consumption cycle count register for client 84. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_85 0x00902554 /* CAS or consumption cycle count register for client 85. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_86 0x00902558 /* CAS or consumption cycle count register for client 86. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_87 0x0090255c /* CAS or consumption cycle count register for client 87. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_88 0x00902560 /* CAS or consumption cycle count register for client 88. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_89 0x00902564 /* CAS or consumption cycle count register for client 89. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_90 0x00902568 /* CAS or consumption cycle count register for client 90. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_91 0x0090256c /* CAS or consumption cycle count register for client 91. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_92 0x00902570 /* CAS or consumption cycle count register for client 92. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_93 0x00902574 /* CAS or consumption cycle count register for client 93. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_94 0x00902578 /* CAS or consumption cycle count register for client 94. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_95 0x0090257c /* CAS or consumption cycle count register for client 95. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_96 0x00902580 /* CAS or consumption cycle count register for client 96. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_97 0x00902584 /* CAS or consumption cycle count register for client 97. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_98 0x00902588 /* CAS or consumption cycle count register for client 98. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_99 0x0090258c /* CAS or consumption cycle count register for client 99. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_100 0x00902590 /* CAS or consumption cycle count register for client 100. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_101 0x00902594 /* CAS or consumption cycle count register for client 101. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_102 0x00902598 /* CAS or consumption cycle count register for client 102. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_103 0x0090259c /* CAS or consumption cycle count register for client 103. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_104 0x009025a0 /* CAS or consumption cycle count register for client 104. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_105 0x009025a4 /* CAS or consumption cycle count register for client 105. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_106 0x009025a8 /* CAS or consumption cycle count register for client 106. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_107 0x009025ac /* CAS or consumption cycle count register for client 107. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_108 0x009025b0 /* CAS or consumption cycle count register for client 108. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_109 0x009025b4 /* CAS or consumption cycle count register for client 109. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_110 0x009025b8 /* CAS or consumption cycle count register for client 110. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_111 0x009025bc /* CAS or consumption cycle count register for client 111. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_112 0x009025c0 /* CAS or consumption cycle count register for client 112. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_113 0x009025c4 /* CAS or consumption cycle count register for client 113. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_114 0x009025c8 /* CAS or consumption cycle count register for client 114. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_115 0x009025cc /* CAS or consumption cycle count register for client 115. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_116 0x009025d0 /* CAS or consumption cycle count register for client 116. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_117 0x009025d4 /* CAS or consumption cycle count register for client 117. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_118 0x009025d8 /* CAS or consumption cycle count register for client 118. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_119 0x009025dc /* CAS or consumption cycle count register for client 119. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_120 0x009025e0 /* CAS or consumption cycle count register for client 120. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_121 0x009025e4 /* CAS or consumption cycle count register for client 121. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_122 0x009025e8 /* CAS or consumption cycle count register for client 122. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_123 0x009025ec /* CAS or consumption cycle count register for client 123. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_124 0x009025f0 /* CAS or consumption cycle count register for client 124. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_125 0x009025f4 /* CAS or consumption cycle count register for client 125. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_126 0x009025f8 /* CAS or consumption cycle count register for client 126. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_127 0x009025fc /* CAS or consumption cycle count register for client 127. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_128 0x00902600 /* CAS or consumption cycle count register for client 128. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_129 0x00902604 /* CAS or consumption cycle count register for client 129. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_130 0x00902608 /* CAS or consumption cycle count register for client 130. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_131 0x0090260c /* CAS or consumption cycle count register for client 131. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_132 0x00902610 /* CAS or consumption cycle count register for client 132. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_133 0x00902614 /* CAS or consumption cycle count register for client 133. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_134 0x00902618 /* CAS or consumption cycle count register for client 134. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_135 0x0090261c /* CAS or consumption cycle count register for client 135. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_136 0x00902620 /* CAS or consumption cycle count register for client 136. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_137 0x00902624 /* CAS or consumption cycle count register for client 137. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_138 0x00902628 /* CAS or consumption cycle count register for client 138. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_139 0x0090262c /* CAS or consumption cycle count register for client 139. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_140 0x00902630 /* CAS or consumption cycle count register for client 140. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_141 0x00902634 /* CAS or consumption cycle count register for client 141. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_142 0x00902638 /* CAS or consumption cycle count register for client 142. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_143 0x0090263c /* CAS or consumption cycle count register for client 143. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_144 0x00902640 /* CAS or consumption cycle count register for client 144. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_145 0x00902644 /* CAS or consumption cycle count register for client 145. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_146 0x00902648 /* CAS or consumption cycle count register for client 146. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_147 0x0090264c /* CAS or consumption cycle count register for client 147. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_148 0x00902650 /* CAS or consumption cycle count register for client 148. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_149 0x00902654 /* CAS or consumption cycle count register for client 149. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_150 0x00902658 /* CAS or consumption cycle count register for client 150. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_151 0x0090265c /* CAS or consumption cycle count register for client 151. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_152 0x00902660 /* CAS or consumption cycle count register for client 152. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_153 0x00902664 /* CAS or consumption cycle count register for client 153. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_154 0x00902668 /* CAS or consumption cycle count register for client 154. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_155 0x0090266c /* CAS or consumption cycle count register for client 155. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_156 0x00902670 /* CAS or consumption cycle count register for client 156. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_157 0x00902674 /* CAS or consumption cycle count register for client 157. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_158 0x00902678 /* CAS or consumption cycle count register for client 158. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_159 0x0090267c /* CAS or consumption cycle count register for client 159. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_160 0x00902680 /* CAS or consumption cycle count register for client 160. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_161 0x00902684 /* CAS or consumption cycle count register for client 161. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_162 0x00902688 /* CAS or consumption cycle count register for client 162. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_163 0x0090268c /* CAS or consumption cycle count register for client 163. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_164 0x00902690 /* CAS or consumption cycle count register for client 164. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_165 0x00902694 /* CAS or consumption cycle count register for client 165. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_166 0x00902698 /* CAS or consumption cycle count register for client 166. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_167 0x0090269c /* CAS or consumption cycle count register for client 167. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_168 0x009026a0 /* CAS or consumption cycle count register for client 168. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_169 0x009026a4 /* CAS or consumption cycle count register for client 169. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_170 0x009026a8 /* CAS or consumption cycle count register for client 170. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_171 0x009026ac /* CAS or consumption cycle count register for client 171. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_172 0x009026b0 /* CAS or consumption cycle count register for client 172. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_173 0x009026b4 /* CAS or consumption cycle count register for client 173. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_174 0x009026b8 /* CAS or consumption cycle count register for client 174. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_175 0x009026bc /* CAS or consumption cycle count register for client 175. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_176 0x009026c0 /* CAS or consumption cycle count register for client 176. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_177 0x009026c4 /* CAS or consumption cycle count register for client 177. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_178 0x009026c8 /* CAS or consumption cycle count register for client 178. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_179 0x009026cc /* CAS or consumption cycle count register for client 179. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_180 0x009026d0 /* CAS or consumption cycle count register for client 180. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_181 0x009026d4 /* CAS or consumption cycle count register for client 181. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_182 0x009026d8 /* CAS or consumption cycle count register for client 182. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_183 0x009026dc /* CAS or consumption cycle count register for client 183. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_184 0x009026e0 /* CAS or consumption cycle count register for client 184. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_185 0x009026e4 /* CAS or consumption cycle count register for client 185. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_186 0x009026e8 /* CAS or consumption cycle count register for client 186. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_187 0x009026ec /* CAS or consumption cycle count register for client 187. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_188 0x009026f0 /* CAS or consumption cycle count register for client 188. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_189 0x009026f4 /* CAS or consumption cycle count register for client 189. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_190 0x009026f8 /* CAS or consumption cycle count register for client 190. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_191 0x009026fc /* CAS or consumption cycle count register for client 191. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_192 0x00902700 /* CAS or consumption cycle count register for client 192. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_193 0x00902704 /* CAS or consumption cycle count register for client 193. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_194 0x00902708 /* CAS or consumption cycle count register for client 194. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_195 0x0090270c /* CAS or consumption cycle count register for client 195. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_196 0x00902710 /* CAS or consumption cycle count register for client 196. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_197 0x00902714 /* CAS or consumption cycle count register for client 197. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_198 0x00902718 /* CAS or consumption cycle count register for client 198. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_199 0x0090271c /* CAS or consumption cycle count register for client 199. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_200 0x00902720 /* CAS or consumption cycle count register for client 200. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_201 0x00902724 /* CAS or consumption cycle count register for client 201. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_202 0x00902728 /* CAS or consumption cycle count register for client 202. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_203 0x0090272c /* CAS or consumption cycle count register for client 203. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_204 0x00902730 /* CAS or consumption cycle count register for client 204. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_205 0x00902734 /* CAS or consumption cycle count register for client 205. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_206 0x00902738 /* CAS or consumption cycle count register for client 206. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_207 0x0090273c /* CAS or consumption cycle count register for client 207. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_208 0x00902740 /* CAS or consumption cycle count register for client 208. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_209 0x00902744 /* CAS or consumption cycle count register for client 209. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_210 0x00902748 /* CAS or consumption cycle count register for client 210. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_211 0x0090274c /* CAS or consumption cycle count register for client 211. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_212 0x00902750 /* CAS or consumption cycle count register for client 212. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_213 0x00902754 /* CAS or consumption cycle count register for client 213. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_214 0x00902758 /* CAS or consumption cycle count register for client 214. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_215 0x0090275c /* CAS or consumption cycle count register for client 215. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_216 0x00902760 /* CAS or consumption cycle count register for client 216. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_217 0x00902764 /* CAS or consumption cycle count register for client 217. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_218 0x00902768 /* CAS or consumption cycle count register for client 218. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_219 0x0090276c /* CAS or consumption cycle count register for client 219. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_220 0x00902770 /* CAS or consumption cycle count register for client 220. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_221 0x00902774 /* CAS or consumption cycle count register for client 221. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_222 0x00902778 /* CAS or consumption cycle count register for client 222. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_223 0x0090277c /* CAS or consumption cycle count register for client 223. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_224 0x00902780 /* CAS or consumption cycle count register for client 224. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_225 0x00902784 /* CAS or consumption cycle count register for client 225. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_226 0x00902788 /* CAS or consumption cycle count register for client 226. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_227 0x0090278c /* CAS or consumption cycle count register for client 227. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_228 0x00902790 /* CAS or consumption cycle count register for client 228. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_229 0x00902794 /* CAS or consumption cycle count register for client 229. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_230 0x00902798 /* CAS or consumption cycle count register for client 230. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_231 0x0090279c /* CAS or consumption cycle count register for client 231. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_232 0x009027a0 /* CAS or consumption cycle count register for client 232. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_233 0x009027a4 /* CAS or consumption cycle count register for client 233. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_234 0x009027a8 /* CAS or consumption cycle count register for client 234. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_235 0x009027ac /* CAS or consumption cycle count register for client 235. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_236 0x009027b0 /* CAS or consumption cycle count register for client 236. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_237 0x009027b4 /* CAS or consumption cycle count register for client 237. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_238 0x009027b8 /* CAS or consumption cycle count register for client 238. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_239 0x009027bc /* CAS or consumption cycle count register for client 239. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_240 0x009027c0 /* CAS or consumption cycle count register for client 240. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_241 0x009027c4 /* CAS or consumption cycle count register for client 241. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_242 0x009027c8 /* CAS or consumption cycle count register for client 242. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_243 0x009027cc /* CAS or consumption cycle count register for client 243. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_244 0x009027d0 /* CAS or consumption cycle count register for client 244. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_245 0x009027d4 /* CAS or consumption cycle count register for client 245. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_246 0x009027d8 /* CAS or consumption cycle count register for client 246. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_247 0x009027dc /* CAS or consumption cycle count register for client 247. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_248 0x009027e0 /* CAS or consumption cycle count register for client 248. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_249 0x009027e4 /* CAS or consumption cycle count register for client 249. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_250 0x009027e8 /* CAS or consumption cycle count register for client 250. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_251 0x009027ec /* CAS or consumption cycle count register for client 251. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_252 0x009027f0 /* CAS or consumption cycle count register for client 252. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_253 0x009027f4 /* CAS or consumption cycle count register for client 253. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_254 0x009027f8 /* CAS or consumption cycle count register for client 254. */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_255 0x009027fc /* CAS or consumption cycle count register for client 255. */
-
-/***************************************************************************
- *CNTRLR_CONFIG - Memory Controller Configuration Register
- ***************************************************************************/
-/* MEMC_DDR_0 :: CNTRLR_CONFIG :: reserved0 [31:15] */
-#define BCHP_MEMC_DDR_0_CNTRLR_CONFIG_reserved0_MASK 0xffff8000
-#define BCHP_MEMC_DDR_0_CNTRLR_CONFIG_reserved0_SHIFT 15
-
-/* MEMC_DDR_0 :: CNTRLR_CONFIG :: GROUPAGE_ENABLE [14:14] */
-#define BCHP_MEMC_DDR_0_CNTRLR_CONFIG_GROUPAGE_ENABLE_MASK 0x00004000
-#define BCHP_MEMC_DDR_0_CNTRLR_CONFIG_GROUPAGE_ENABLE_SHIFT 14
-#define BCHP_MEMC_DDR_0_CNTRLR_CONFIG_GROUPAGE_ENABLE_DEFAULT 0x00000000
-
-/* MEMC_DDR_0 :: CNTRLR_CONFIG :: MODIFY_RASTER_ADDR [13:13] */
-#define BCHP_MEMC_DDR_0_CNTRLR_CONFIG_MODIFY_RASTER_ADDR_MASK 0x00002000
-#define BCHP_MEMC_DDR_0_CNTRLR_CONFIG_MODIFY_RASTER_ADDR_SHIFT 13
-#define BCHP_MEMC_DDR_0_CNTRLR_CONFIG_MODIFY_RASTER_ADDR_DEFAULT 0x00000001
-
-/* MEMC_DDR_0 :: CNTRLR_CONFIG :: DRAM_COMMANDS_2T [12:12] */
-#define BCHP_MEMC_DDR_0_CNTRLR_CONFIG_DRAM_COMMANDS_2T_MASK 0x00001000
-#define BCHP_MEMC_DDR_0_CNTRLR_CONFIG_DRAM_COMMANDS_2T_SHIFT 12
-#define BCHP_MEMC_DDR_0_CNTRLR_CONFIG_DRAM_COMMANDS_2T_DEFAULT 0x00000000
-
-/* MEMC_DDR_0 :: CNTRLR_CONFIG :: DRAM_TOTAL_WIDTH [11:10] */
-#define BCHP_MEMC_DDR_0_CNTRLR_CONFIG_DRAM_TOTAL_WIDTH_MASK 0x00000c00
-#define BCHP_MEMC_DDR_0_CNTRLR_CONFIG_DRAM_TOTAL_WIDTH_SHIFT 10
-#define BCHP_MEMC_DDR_0_CNTRLR_CONFIG_DRAM_TOTAL_WIDTH_DEFAULT 0x00000002
-#define BCHP_MEMC_DDR_0_CNTRLR_CONFIG_DRAM_TOTAL_WIDTH_reserved_x8 0
-#define BCHP_MEMC_DDR_0_CNTRLR_CONFIG_DRAM_TOTAL_WIDTH_x16 1
-#define BCHP_MEMC_DDR_0_CNTRLR_CONFIG_DRAM_TOTAL_WIDTH_x32 2
-#define BCHP_MEMC_DDR_0_CNTRLR_CONFIG_DRAM_TOTAL_WIDTH_reserved_x64 3
-
-/* MEMC_DDR_0 :: CNTRLR_CONFIG :: DRAM_DEVICE_WIDTH [09:08] */
-#define BCHP_MEMC_DDR_0_CNTRLR_CONFIG_DRAM_DEVICE_WIDTH_MASK 0x00000300
-#define BCHP_MEMC_DDR_0_CNTRLR_CONFIG_DRAM_DEVICE_WIDTH_SHIFT 8
-#define BCHP_MEMC_DDR_0_CNTRLR_CONFIG_DRAM_DEVICE_WIDTH_DEFAULT 0x00000001
-#define BCHP_MEMC_DDR_0_CNTRLR_CONFIG_DRAM_DEVICE_WIDTH_x8 0
-#define BCHP_MEMC_DDR_0_CNTRLR_CONFIG_DRAM_DEVICE_WIDTH_x16 1
-#define BCHP_MEMC_DDR_0_CNTRLR_CONFIG_DRAM_DEVICE_WIDTH_reserved_2 2
-#define BCHP_MEMC_DDR_0_CNTRLR_CONFIG_DRAM_DEVICE_WIDTH_reserved_3 3
-
-/* MEMC_DDR_0 :: CNTRLR_CONFIG :: DRAM_DEVICE_SIZE [07:04] */
-#define BCHP_MEMC_DDR_0_CNTRLR_CONFIG_DRAM_DEVICE_SIZE_MASK 0x000000f0
-#define BCHP_MEMC_DDR_0_CNTRLR_CONFIG_DRAM_DEVICE_SIZE_SHIFT 4
-#define BCHP_MEMC_DDR_0_CNTRLR_CONFIG_DRAM_DEVICE_SIZE_DEFAULT 0x00000003
-#define BCHP_MEMC_DDR_0_CNTRLR_CONFIG_DRAM_DEVICE_SIZE_reserved_256_Mb 0
-#define BCHP_MEMC_DDR_0_CNTRLR_CONFIG_DRAM_DEVICE_SIZE_512_Mb 1
-#define BCHP_MEMC_DDR_0_CNTRLR_CONFIG_DRAM_DEVICE_SIZE_1_Gb 2
-#define BCHP_MEMC_DDR_0_CNTRLR_CONFIG_DRAM_DEVICE_SIZE_2_Gb 3
-#define BCHP_MEMC_DDR_0_CNTRLR_CONFIG_DRAM_DEVICE_SIZE_4_Gb 4
-#define BCHP_MEMC_DDR_0_CNTRLR_CONFIG_DRAM_DEVICE_SIZE_8_Gb 5
-#define BCHP_MEMC_DDR_0_CNTRLR_CONFIG_DRAM_DEVICE_SIZE_16_Gb 6
-#define BCHP_MEMC_DDR_0_CNTRLR_CONFIG_DRAM_DEVICE_SIZE_reserved_7 7
-#define BCHP_MEMC_DDR_0_CNTRLR_CONFIG_DRAM_DEVICE_SIZE_reserved_8 8
-#define BCHP_MEMC_DDR_0_CNTRLR_CONFIG_DRAM_DEVICE_SIZE_reserved_9 9
-#define BCHP_MEMC_DDR_0_CNTRLR_CONFIG_DRAM_DEVICE_SIZE_reserved_10 10
-#define BCHP_MEMC_DDR_0_CNTRLR_CONFIG_DRAM_DEVICE_SIZE_reserved_11 11
-#define BCHP_MEMC_DDR_0_CNTRLR_CONFIG_DRAM_DEVICE_SIZE_reserved_12 12
-#define BCHP_MEMC_DDR_0_CNTRLR_CONFIG_DRAM_DEVICE_SIZE_reserved_13 13
-#define BCHP_MEMC_DDR_0_CNTRLR_CONFIG_DRAM_DEVICE_SIZE_reserved_14 14
-#define BCHP_MEMC_DDR_0_CNTRLR_CONFIG_DRAM_DEVICE_SIZE_reserved_15 15
-
-/* MEMC_DDR_0 :: CNTRLR_CONFIG :: DRAM_DEVICE_TYPE [03:00] */
-#define BCHP_MEMC_DDR_0_CNTRLR_CONFIG_DRAM_DEVICE_TYPE_MASK 0x0000000f
-#define BCHP_MEMC_DDR_0_CNTRLR_CONFIG_DRAM_DEVICE_TYPE_SHIFT 0
-#define BCHP_MEMC_DDR_0_CNTRLR_CONFIG_DRAM_DEVICE_TYPE_DEFAULT 0x00000001
-#define BCHP_MEMC_DDR_0_CNTRLR_CONFIG_DRAM_DEVICE_TYPE_reserved_DDR2 0
-#define BCHP_MEMC_DDR_0_CNTRLR_CONFIG_DRAM_DEVICE_TYPE_DDR3 1
-#define BCHP_MEMC_DDR_0_CNTRLR_CONFIG_DRAM_DEVICE_TYPE_DDR4 2
-#define BCHP_MEMC_DDR_0_CNTRLR_CONFIG_DRAM_DEVICE_TYPE_GDDR5M 3
-#define BCHP_MEMC_DDR_0_CNTRLR_CONFIG_DRAM_DEVICE_TYPE_GDDR5 4
-#define BCHP_MEMC_DDR_0_CNTRLR_CONFIG_DRAM_DEVICE_TYPE_reserved_5 5
-#define BCHP_MEMC_DDR_0_CNTRLR_CONFIG_DRAM_DEVICE_TYPE_reserved_6 6
-#define BCHP_MEMC_DDR_0_CNTRLR_CONFIG_DRAM_DEVICE_TYPE_reserved_7 7
-#define BCHP_MEMC_DDR_0_CNTRLR_CONFIG_DRAM_DEVICE_TYPE_reserved_8 8
-#define BCHP_MEMC_DDR_0_CNTRLR_CONFIG_DRAM_DEVICE_TYPE_reserved_9 9
-#define BCHP_MEMC_DDR_0_CNTRLR_CONFIG_DRAM_DEVICE_TYPE_reserved_10 10
-#define BCHP_MEMC_DDR_0_CNTRLR_CONFIG_DRAM_DEVICE_TYPE_reserved_11 11
-#define BCHP_MEMC_DDR_0_CNTRLR_CONFIG_DRAM_DEVICE_TYPE_reserved_12 12
-#define BCHP_MEMC_DDR_0_CNTRLR_CONFIG_DRAM_DEVICE_TYPE_reserved_13 13
-#define BCHP_MEMC_DDR_0_CNTRLR_CONFIG_DRAM_DEVICE_TYPE_reserved_14 14
-#define BCHP_MEMC_DDR_0_CNTRLR_CONFIG_DRAM_DEVICE_TYPE_reserved_15 15
-
-/***************************************************************************
- *CNTRLR_CONFIG_STATUS - Memory Controller Configuration Status Register
- ***************************************************************************/
-/* MEMC_DDR_0 :: CNTRLR_CONFIG_STATUS :: reserved0 [31:15] */
-#define BCHP_MEMC_DDR_0_CNTRLR_CONFIG_STATUS_reserved0_MASK 0xffff8000
-#define BCHP_MEMC_DDR_0_CNTRLR_CONFIG_STATUS_reserved0_SHIFT 15
-
-/* MEMC_DDR_0 :: CNTRLR_CONFIG_STATUS :: GROUPAGE_ENABLE [14:14] */
-#define BCHP_MEMC_DDR_0_CNTRLR_CONFIG_STATUS_GROUPAGE_ENABLE_MASK 0x00004000
-#define BCHP_MEMC_DDR_0_CNTRLR_CONFIG_STATUS_GROUPAGE_ENABLE_SHIFT 14
-#define BCHP_MEMC_DDR_0_CNTRLR_CONFIG_STATUS_GROUPAGE_ENABLE_DEFAULT 0x00000000
-
-/* MEMC_DDR_0 :: CNTRLR_CONFIG_STATUS :: MODIFY_RASTER_ADDR [13:13] */
-#define BCHP_MEMC_DDR_0_CNTRLR_CONFIG_STATUS_MODIFY_RASTER_ADDR_MASK 0x00002000
-#define BCHP_MEMC_DDR_0_CNTRLR_CONFIG_STATUS_MODIFY_RASTER_ADDR_SHIFT 13
-#define BCHP_MEMC_DDR_0_CNTRLR_CONFIG_STATUS_MODIFY_RASTER_ADDR_DEFAULT 0x00000001
-
-/* MEMC_DDR_0 :: CNTRLR_CONFIG_STATUS :: DRAM_COMMANDS_2T [12:12] */
-#define BCHP_MEMC_DDR_0_CNTRLR_CONFIG_STATUS_DRAM_COMMANDS_2T_MASK 0x00001000
-#define BCHP_MEMC_DDR_0_CNTRLR_CONFIG_STATUS_DRAM_COMMANDS_2T_SHIFT 12
-#define BCHP_MEMC_DDR_0_CNTRLR_CONFIG_STATUS_DRAM_COMMANDS_2T_DEFAULT 0x00000000
-
-/* MEMC_DDR_0 :: CNTRLR_CONFIG_STATUS :: DRAM_TOTAL_WIDTH [11:10] */
-#define BCHP_MEMC_DDR_0_CNTRLR_CONFIG_STATUS_DRAM_TOTAL_WIDTH_MASK 0x00000c00
-#define BCHP_MEMC_DDR_0_CNTRLR_CONFIG_STATUS_DRAM_TOTAL_WIDTH_SHIFT 10
-#define BCHP_MEMC_DDR_0_CNTRLR_CONFIG_STATUS_DRAM_TOTAL_WIDTH_DEFAULT 0x00000002
-#define BCHP_MEMC_DDR_0_CNTRLR_CONFIG_STATUS_DRAM_TOTAL_WIDTH_reserved_x8 0
-#define BCHP_MEMC_DDR_0_CNTRLR_CONFIG_STATUS_DRAM_TOTAL_WIDTH_x16 1
-#define BCHP_MEMC_DDR_0_CNTRLR_CONFIG_STATUS_DRAM_TOTAL_WIDTH_x32 2
-#define BCHP_MEMC_DDR_0_CNTRLR_CONFIG_STATUS_DRAM_TOTAL_WIDTH_reserved_x64 3
-
-/* MEMC_DDR_0 :: CNTRLR_CONFIG_STATUS :: DRAM_DEVICE_WIDTH [09:08] */
-#define BCHP_MEMC_DDR_0_CNTRLR_CONFIG_STATUS_DRAM_DEVICE_WIDTH_MASK 0x00000300
-#define BCHP_MEMC_DDR_0_CNTRLR_CONFIG_STATUS_DRAM_DEVICE_WIDTH_SHIFT 8
-#define BCHP_MEMC_DDR_0_CNTRLR_CONFIG_STATUS_DRAM_DEVICE_WIDTH_DEFAULT 0x00000001
-#define BCHP_MEMC_DDR_0_CNTRLR_CONFIG_STATUS_DRAM_DEVICE_WIDTH_x8 0
-#define BCHP_MEMC_DDR_0_CNTRLR_CONFIG_STATUS_DRAM_DEVICE_WIDTH_x16 1
-#define BCHP_MEMC_DDR_0_CNTRLR_CONFIG_STATUS_DRAM_DEVICE_WIDTH_reserved_2 2
-#define BCHP_MEMC_DDR_0_CNTRLR_CONFIG_STATUS_DRAM_DEVICE_WIDTH_reserved_3 3
-
-/* MEMC_DDR_0 :: CNTRLR_CONFIG_STATUS :: DRAM_DEVICE_SIZE [07:04] */
-#define BCHP_MEMC_DDR_0_CNTRLR_CONFIG_STATUS_DRAM_DEVICE_SIZE_MASK 0x000000f0
-#define BCHP_MEMC_DDR_0_CNTRLR_CONFIG_STATUS_DRAM_DEVICE_SIZE_SHIFT 4
-#define BCHP_MEMC_DDR_0_CNTRLR_CONFIG_STATUS_DRAM_DEVICE_SIZE_DEFAULT 0x00000003
-#define BCHP_MEMC_DDR_0_CNTRLR_CONFIG_STATUS_DRAM_DEVICE_SIZE_reserved_256_Mb 0
-#define BCHP_MEMC_DDR_0_CNTRLR_CONFIG_STATUS_DRAM_DEVICE_SIZE_512_Mb 1
-#define BCHP_MEMC_DDR_0_CNTRLR_CONFIG_STATUS_DRAM_DEVICE_SIZE_1_Gb 2
-#define BCHP_MEMC_DDR_0_CNTRLR_CONFIG_STATUS_DRAM_DEVICE_SIZE_2_Gb 3
-#define BCHP_MEMC_DDR_0_CNTRLR_CONFIG_STATUS_DRAM_DEVICE_SIZE_4_Gb 4
-#define BCHP_MEMC_DDR_0_CNTRLR_CONFIG_STATUS_DRAM_DEVICE_SIZE_8_Gb 5
-#define BCHP_MEMC_DDR_0_CNTRLR_CONFIG_STATUS_DRAM_DEVICE_SIZE_16_Gb 6
-#define BCHP_MEMC_DDR_0_CNTRLR_CONFIG_STATUS_DRAM_DEVICE_SIZE_reserved_7 7
-#define BCHP_MEMC_DDR_0_CNTRLR_CONFIG_STATUS_DRAM_DEVICE_SIZE_reserved_8 8
-#define BCHP_MEMC_DDR_0_CNTRLR_CONFIG_STATUS_DRAM_DEVICE_SIZE_reserved_9 9
-#define BCHP_MEMC_DDR_0_CNTRLR_CONFIG_STATUS_DRAM_DEVICE_SIZE_reserved_10 10
-#define BCHP_MEMC_DDR_0_CNTRLR_CONFIG_STATUS_DRAM_DEVICE_SIZE_reserved_11 11
-#define BCHP_MEMC_DDR_0_CNTRLR_CONFIG_STATUS_DRAM_DEVICE_SIZE_reserved_12 12
-#define BCHP_MEMC_DDR_0_CNTRLR_CONFIG_STATUS_DRAM_DEVICE_SIZE_reserved_13 13
-#define BCHP_MEMC_DDR_0_CNTRLR_CONFIG_STATUS_DRAM_DEVICE_SIZE_reserved_14 14
-#define BCHP_MEMC_DDR_0_CNTRLR_CONFIG_STATUS_DRAM_DEVICE_SIZE_reserved_15 15
-
-/* MEMC_DDR_0 :: CNTRLR_CONFIG_STATUS :: DRAM_DEVICE_TYPE [03:00] */
-#define BCHP_MEMC_DDR_0_CNTRLR_CONFIG_STATUS_DRAM_DEVICE_TYPE_MASK 0x0000000f
-#define BCHP_MEMC_DDR_0_CNTRLR_CONFIG_STATUS_DRAM_DEVICE_TYPE_SHIFT 0
-#define BCHP_MEMC_DDR_0_CNTRLR_CONFIG_STATUS_DRAM_DEVICE_TYPE_DEFAULT 0x00000001
-#define BCHP_MEMC_DDR_0_CNTRLR_CONFIG_STATUS_DRAM_DEVICE_TYPE_reserved_DDR2 0
-#define BCHP_MEMC_DDR_0_CNTRLR_CONFIG_STATUS_DRAM_DEVICE_TYPE_DDR3 1
-#define BCHP_MEMC_DDR_0_CNTRLR_CONFIG_STATUS_DRAM_DEVICE_TYPE_DDR4 2
-#define BCHP_MEMC_DDR_0_CNTRLR_CONFIG_STATUS_DRAM_DEVICE_TYPE_GDDR5M 3
-#define BCHP_MEMC_DDR_0_CNTRLR_CONFIG_STATUS_DRAM_DEVICE_TYPE_GDDR5 4
-#define BCHP_MEMC_DDR_0_CNTRLR_CONFIG_STATUS_DRAM_DEVICE_TYPE_reserved_5 5
-#define BCHP_MEMC_DDR_0_CNTRLR_CONFIG_STATUS_DRAM_DEVICE_TYPE_reserved_6 6
-#define BCHP_MEMC_DDR_0_CNTRLR_CONFIG_STATUS_DRAM_DEVICE_TYPE_reserved_7 7
-#define BCHP_MEMC_DDR_0_CNTRLR_CONFIG_STATUS_DRAM_DEVICE_TYPE_reserved_8 8
-#define BCHP_MEMC_DDR_0_CNTRLR_CONFIG_STATUS_DRAM_DEVICE_TYPE_reserved_9 9
-#define BCHP_MEMC_DDR_0_CNTRLR_CONFIG_STATUS_DRAM_DEVICE_TYPE_reserved_10 10
-#define BCHP_MEMC_DDR_0_CNTRLR_CONFIG_STATUS_DRAM_DEVICE_TYPE_reserved_11 11
-#define BCHP_MEMC_DDR_0_CNTRLR_CONFIG_STATUS_DRAM_DEVICE_TYPE_reserved_12 12
-#define BCHP_MEMC_DDR_0_CNTRLR_CONFIG_STATUS_DRAM_DEVICE_TYPE_reserved_13 13
-#define BCHP_MEMC_DDR_0_CNTRLR_CONFIG_STATUS_DRAM_DEVICE_TYPE_reserved_14 14
-#define BCHP_MEMC_DDR_0_CNTRLR_CONFIG_STATUS_DRAM_DEVICE_TYPE_reserved_15 15
-
-/***************************************************************************
- *DRAM_INIT_CNTRL - Dram initialization control
- ***************************************************************************/
-/* MEMC_DDR_0 :: DRAM_INIT_CNTRL :: reserved0 [31:06] */
-#define BCHP_MEMC_DDR_0_DRAM_INIT_CNTRL_reserved0_MASK 0xffffffc0
-#define BCHP_MEMC_DDR_0_DRAM_INIT_CNTRL_reserved0_SHIFT 6
-
-/* MEMC_DDR_0 :: DRAM_INIT_CNTRL :: IGNORE_PHY_REQUEST_AT_RESET [05:05] */
-#define BCHP_MEMC_DDR_0_DRAM_INIT_CNTRL_IGNORE_PHY_REQUEST_AT_RESET_MASK 0x00000020
-#define BCHP_MEMC_DDR_0_DRAM_INIT_CNTRL_IGNORE_PHY_REQUEST_AT_RESET_SHIFT 5
-#define BCHP_MEMC_DDR_0_DRAM_INIT_CNTRL_IGNORE_PHY_REQUEST_AT_RESET_DEFAULT 0x00000000
-
-/* MEMC_DDR_0 :: DRAM_INIT_CNTRL :: ENTER_PHY_OP_STATE [04:04] */
-#define BCHP_MEMC_DDR_0_DRAM_INIT_CNTRL_ENTER_PHY_OP_STATE_MASK 0x00000010
-#define BCHP_MEMC_DDR_0_DRAM_INIT_CNTRL_ENTER_PHY_OP_STATE_SHIFT 4
-#define BCHP_MEMC_DDR_0_DRAM_INIT_CNTRL_ENTER_PHY_OP_STATE_DEFAULT 0x00000000
-
-/* MEMC_DDR_0 :: DRAM_INIT_CNTRL :: ENABLE_AUTO_PHY_OP_ACCESS [03:03] */
-#define BCHP_MEMC_DDR_0_DRAM_INIT_CNTRL_ENABLE_AUTO_PHY_OP_ACCESS_MASK 0x00000008
-#define BCHP_MEMC_DDR_0_DRAM_INIT_CNTRL_ENABLE_AUTO_PHY_OP_ACCESS_SHIFT 3
-#define BCHP_MEMC_DDR_0_DRAM_INIT_CNTRL_ENABLE_AUTO_PHY_OP_ACCESS_DEFAULT 0x00000000
-
-/* MEMC_DDR_0 :: DRAM_INIT_CNTRL :: OVERRIDE_PHY_INIT_COMPLETE [02:02] */
-#define BCHP_MEMC_DDR_0_DRAM_INIT_CNTRL_OVERRIDE_PHY_INIT_COMPLETE_MASK 0x00000004
-#define BCHP_MEMC_DDR_0_DRAM_INIT_CNTRL_OVERRIDE_PHY_INIT_COMPLETE_SHIFT 2
-#define BCHP_MEMC_DDR_0_DRAM_INIT_CNTRL_OVERRIDE_PHY_INIT_COMPLETE_DEFAULT 0x00000000
-
-/* MEMC_DDR_0 :: DRAM_INIT_CNTRL :: OVERRIDE_PHY_DFI_GRANT [01:01] */
-#define BCHP_MEMC_DDR_0_DRAM_INIT_CNTRL_OVERRIDE_PHY_DFI_GRANT_MASK 0x00000002
-#define BCHP_MEMC_DDR_0_DRAM_INIT_CNTRL_OVERRIDE_PHY_DFI_GRANT_SHIFT 1
-#define BCHP_MEMC_DDR_0_DRAM_INIT_CNTRL_OVERRIDE_PHY_DFI_GRANT_DEFAULT 0x00000000
-
-/* MEMC_DDR_0 :: DRAM_INIT_CNTRL :: PHY_DFI_GRANT_VALUE [00:00] */
-#define BCHP_MEMC_DDR_0_DRAM_INIT_CNTRL_PHY_DFI_GRANT_VALUE_MASK 0x00000001
-#define BCHP_MEMC_DDR_0_DRAM_INIT_CNTRL_PHY_DFI_GRANT_VALUE_SHIFT 0
-#define BCHP_MEMC_DDR_0_DRAM_INIT_CNTRL_PHY_DFI_GRANT_VALUE_DEFAULT 0x00000000
-
-/***************************************************************************
- *DRAM_INIT_STATUS - Dram initialization status
- ***************************************************************************/
-/* MEMC_DDR_0 :: DRAM_INIT_STATUS :: reserved0 [31:02] */
-#define BCHP_MEMC_DDR_0_DRAM_INIT_STATUS_reserved0_MASK 0xfffffffc
-#define BCHP_MEMC_DDR_0_DRAM_INIT_STATUS_reserved0_SHIFT 2
-
-/* MEMC_DDR_0 :: DRAM_INIT_STATUS :: PHY_DFI_REQUEST_VALUE [01:01] */
-#define BCHP_MEMC_DDR_0_DRAM_INIT_STATUS_PHY_DFI_REQUEST_VALUE_MASK 0x00000002
-#define BCHP_MEMC_DDR_0_DRAM_INIT_STATUS_PHY_DFI_REQUEST_VALUE_SHIFT 1
-#define BCHP_MEMC_DDR_0_DRAM_INIT_STATUS_PHY_DFI_REQUEST_VALUE_DEFAULT 0x00000000
-
-/* MEMC_DDR_0 :: DRAM_INIT_STATUS :: INIT_DONE [00:00] */
-#define BCHP_MEMC_DDR_0_DRAM_INIT_STATUS_INIT_DONE_MASK 0x00000001
-#define BCHP_MEMC_DDR_0_DRAM_INIT_STATUS_INIT_DONE_SHIFT 0
-#define BCHP_MEMC_DDR_0_DRAM_INIT_STATUS_INIT_DONE_DEFAULT 0x00000000
-
-/***************************************************************************
- *DRAM_MODE_0 - Dram Mode Register 0
- ***************************************************************************/
-/* MEMC_DDR_0 :: DRAM_MODE_0 :: reserved0 [31:16] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_0_reserved0_MASK 0xffff0000
-#define BCHP_MEMC_DDR_0_DRAM_MODE_0_reserved0_SHIFT 16
-
-/* MEMC_DDR_0 :: DRAM_MODE_0 :: unused_0 [15:13] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_0_unused_0_MASK 0x0000e000
-#define BCHP_MEMC_DDR_0_DRAM_MODE_0_unused_0_SHIFT 13
-#define BCHP_MEMC_DDR_0_DRAM_MODE_0_unused_0_DEFAULT 0x00000000
-
-/* union - case DDR3 [12:00] */
-/* MEMC_DDR_0 :: DRAM_MODE_0 :: DDR3 :: DLL_CNTRL_PPD [12:12] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR3_DLL_CNTRL_PPD_MASK 0x00001000
-#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR3_DLL_CNTRL_PPD_SHIFT 12
-#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR3_DLL_CNTRL_PPD_DEFAULT 0x00000000
-
-/* MEMC_DDR_0 :: DRAM_MODE_0 :: DDR3 :: WR [11:09] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR3_WR_MASK 0x00000e00
-#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR3_WR_SHIFT 9
-#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR3_WR_DEFAULT 0x00000004
-
-/* MEMC_DDR_0 :: DRAM_MODE_0 :: DDR3 :: DLL_RST [08:08] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR3_DLL_RST_MASK 0x00000100
-#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR3_DLL_RST_SHIFT 8
-#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR3_DLL_RST_DEFAULT 0x00000000
-
-/* MEMC_DDR_0 :: DRAM_MODE_0 :: DDR3 :: TEST_MODE [07:07] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR3_TEST_MODE_MASK 0x00000080
-#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR3_TEST_MODE_SHIFT 7
-#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR3_TEST_MODE_DEFAULT 0x00000000
-
-/* MEMC_DDR_0 :: DRAM_MODE_0 :: DDR3 :: CL_3_1 [06:04] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR3_CL_3_1_MASK 0x00000070
-#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR3_CL_3_1_SHIFT 4
-#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR3_CL_3_1_DEFAULT 0x00000004
-
-/* MEMC_DDR_0 :: DRAM_MODE_0 :: DDR3 :: RBT [03:03] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR3_RBT_MASK 0x00000008
-#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR3_RBT_SHIFT 3
-#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR3_RBT_DEFAULT 0x00000000
-
-/* MEMC_DDR_0 :: DRAM_MODE_0 :: DDR3 :: CL_0 [02:02] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR3_CL_0_MASK 0x00000004
-#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR3_CL_0_SHIFT 2
-#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR3_CL_0_DEFAULT 0x00000000
-
-/* MEMC_DDR_0 :: DRAM_MODE_0 :: DDR3 :: BL [01:00] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR3_BL_MASK 0x00000003
-#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR3_BL_SHIFT 0
-#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR3_BL_DEFAULT 0x00000000
-
-/* union - case DDR4 [12:00] */
-/* MEMC_DDR_0 :: DRAM_MODE_0 :: DDR4 :: unused_1 [12:12] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR4_unused_1_MASK 0x00001000
-#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR4_unused_1_SHIFT 12
-#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR4_unused_1_DEFAULT 0x00000000
-
-/* MEMC_DDR_0 :: DRAM_MODE_0 :: DDR4 :: WR [11:09] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR4_WR_MASK 0x00000e00
-#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR4_WR_SHIFT 9
-#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR4_WR_DEFAULT 0x00000004
-
-/* MEMC_DDR_0 :: DRAM_MODE_0 :: DDR4 :: DLL_RST [08:08] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR4_DLL_RST_MASK 0x00000100
-#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR4_DLL_RST_SHIFT 8
-#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR4_DLL_RST_DEFAULT 0x00000000
-
-/* MEMC_DDR_0 :: DRAM_MODE_0 :: DDR4 :: TEST_MODE [07:07] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR4_TEST_MODE_MASK 0x00000080
-#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR4_TEST_MODE_SHIFT 7
-#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR4_TEST_MODE_DEFAULT 0x00000000
-
-/* MEMC_DDR_0 :: DRAM_MODE_0 :: DDR4 :: CL_3_1 [06:04] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR4_CL_3_1_MASK 0x00000070
-#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR4_CL_3_1_SHIFT 4
-#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR4_CL_3_1_DEFAULT 0x00000004
-
-/* MEMC_DDR_0 :: DRAM_MODE_0 :: DDR4 :: BT [03:03] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR4_BT_MASK 0x00000008
-#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR4_BT_SHIFT 3
-#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR4_BT_DEFAULT 0x00000000
-
-/* MEMC_DDR_0 :: DRAM_MODE_0 :: DDR4 :: CL_0 [02:02] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR4_CL_0_MASK 0x00000004
-#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR4_CL_0_SHIFT 2
-#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR4_CL_0_DEFAULT 0x00000000
-
-/* MEMC_DDR_0 :: DRAM_MODE_0 :: DDR4 :: BL [01:00] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR4_BL_MASK 0x00000003
-#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR4_BL_SHIFT 0
-#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR4_BL_DEFAULT 0x00000000
-
-/* union - case GDDR5M [12:00] */
-/* MEMC_DDR_0 :: DRAM_MODE_0 :: GDDR5M :: unused_1 [12:12] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_0_GDDR5M_unused_1_MASK 0x00001000
-#define BCHP_MEMC_DDR_0_DRAM_MODE_0_GDDR5M_unused_1_SHIFT 12
-#define BCHP_MEMC_DDR_0_DRAM_MODE_0_GDDR5M_unused_1_DEFAULT 0x00000000
-
-/* MEMC_DDR_0 :: DRAM_MODE_0 :: GDDR5M :: WR [11:08] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_0_GDDR5M_WR_MASK 0x00000f00
-#define BCHP_MEMC_DDR_0_DRAM_MODE_0_GDDR5M_WR_SHIFT 8
-#define BCHP_MEMC_DDR_0_DRAM_MODE_0_GDDR5M_WR_DEFAULT 0x00000008
-
-/* MEMC_DDR_0 :: DRAM_MODE_0 :: GDDR5M :: TEST_MODE [07:07] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_0_GDDR5M_TEST_MODE_MASK 0x00000080
-#define BCHP_MEMC_DDR_0_DRAM_MODE_0_GDDR5M_TEST_MODE_SHIFT 7
-#define BCHP_MEMC_DDR_0_DRAM_MODE_0_GDDR5M_TEST_MODE_DEFAULT 0x00000000
-
-/* MEMC_DDR_0 :: DRAM_MODE_0 :: GDDR5M :: CL [06:03] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_0_GDDR5M_CL_MASK 0x00000078
-#define BCHP_MEMC_DDR_0_DRAM_MODE_0_GDDR5M_CL_SHIFT 3
-#define BCHP_MEMC_DDR_0_DRAM_MODE_0_GDDR5M_CL_DEFAULT 0x00000009
-
-/* MEMC_DDR_0 :: DRAM_MODE_0 :: GDDR5M :: WL [02:00] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_0_GDDR5M_WL_MASK 0x00000007
-#define BCHP_MEMC_DDR_0_DRAM_MODE_0_GDDR5M_WL_SHIFT 0
-#define BCHP_MEMC_DDR_0_DRAM_MODE_0_GDDR5M_WL_DEFAULT 0x00000004
-
-/* union - case GDDR5 [12:00] */
-/* MEMC_DDR_0 :: DRAM_MODE_0 :: GDDR5 :: unused_1 [12:12] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_0_GDDR5_unused_1_MASK 0x00001000
-#define BCHP_MEMC_DDR_0_DRAM_MODE_0_GDDR5_unused_1_SHIFT 12
-#define BCHP_MEMC_DDR_0_DRAM_MODE_0_GDDR5_unused_1_DEFAULT 0x00000000
-
-/* MEMC_DDR_0 :: DRAM_MODE_0 :: GDDR5 :: WR [11:08] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_0_GDDR5_WR_MASK 0x00000f00
-#define BCHP_MEMC_DDR_0_DRAM_MODE_0_GDDR5_WR_SHIFT 8
-#define BCHP_MEMC_DDR_0_DRAM_MODE_0_GDDR5_WR_DEFAULT 0x00000008
-
-/* MEMC_DDR_0 :: DRAM_MODE_0 :: GDDR5 :: TEST_MODE [07:07] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_0_GDDR5_TEST_MODE_MASK 0x00000080
-#define BCHP_MEMC_DDR_0_DRAM_MODE_0_GDDR5_TEST_MODE_SHIFT 7
-#define BCHP_MEMC_DDR_0_DRAM_MODE_0_GDDR5_TEST_MODE_DEFAULT 0x00000000
-
-/* MEMC_DDR_0 :: DRAM_MODE_0 :: GDDR5 :: CL [06:03] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_0_GDDR5_CL_MASK 0x00000078
-#define BCHP_MEMC_DDR_0_DRAM_MODE_0_GDDR5_CL_SHIFT 3
-#define BCHP_MEMC_DDR_0_DRAM_MODE_0_GDDR5_CL_DEFAULT 0x00000009
-
-/* MEMC_DDR_0 :: DRAM_MODE_0 :: GDDR5 :: WL [02:00] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_0_GDDR5_WL_MASK 0x00000007
-#define BCHP_MEMC_DDR_0_DRAM_MODE_0_GDDR5_WL_SHIFT 0
-#define BCHP_MEMC_DDR_0_DRAM_MODE_0_GDDR5_WL_DEFAULT 0x00000004
-
-/***************************************************************************
- *DRAM_MODE_1 - Dram Mode Register 1
- ***************************************************************************/
-/* MEMC_DDR_0 :: DRAM_MODE_1 :: reserved0 [31:16] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_1_reserved0_MASK 0xffff0000
-#define BCHP_MEMC_DDR_0_DRAM_MODE_1_reserved0_SHIFT 16
-
-/* MEMC_DDR_0 :: DRAM_MODE_1 :: unused_0 [15:13] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_1_unused_0_MASK 0x0000e000
-#define BCHP_MEMC_DDR_0_DRAM_MODE_1_unused_0_SHIFT 13
-#define BCHP_MEMC_DDR_0_DRAM_MODE_1_unused_0_DEFAULT 0x00000000
-
-/* union - case DDR3 [12:00] */
-/* MEMC_DDR_0 :: DRAM_MODE_1 :: DDR3 :: Q_OFF [12:12] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_Q_OFF_MASK 0x00001000
-#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_Q_OFF_SHIFT 12
-#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_Q_OFF_DEFAULT 0x00000000
-#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_Q_OFF_ENABLE 0
-#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_Q_OFF_DISABLE 1
-
-/* MEMC_DDR_0 :: DRAM_MODE_1 :: DDR3 :: TDQS [11:11] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_TDQS_MASK 0x00000800
-#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_TDQS_SHIFT 11
-#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_TDQS_DEFAULT 0x00000000
-#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_TDQS_ENABLE 1
-#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_TDQS_DISABLE 0
-
-/* MEMC_DDR_0 :: DRAM_MODE_1 :: DDR3 :: unused_1 [10:10] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_unused_1_MASK 0x00000400
-#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_unused_1_SHIFT 10
-#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_unused_1_DEFAULT 0x00000000
-
-/* MEMC_DDR_0 :: DRAM_MODE_1 :: DDR3 :: ODT_CNTRL_2 [09:09] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_ODT_CNTRL_2_MASK 0x00000200
-#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_ODT_CNTRL_2_SHIFT 9
-#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_ODT_CNTRL_2_DEFAULT 0x00000000
-
-/* MEMC_DDR_0 :: DRAM_MODE_1 :: DDR3 :: unused_2 [08:08] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_unused_2_MASK 0x00000100
-#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_unused_2_SHIFT 8
-#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_unused_2_DEFAULT 0x00000000
-
-/* MEMC_DDR_0 :: DRAM_MODE_1 :: DDR3 :: WR_LEVEL [07:07] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_WR_LEVEL_MASK 0x00000080
-#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_WR_LEVEL_SHIFT 7
-#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_WR_LEVEL_DEFAULT 0x00000000
-#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_WR_LEVEL_ENABLE 1
-#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_WR_LEVEL_DISABLE 0
-
-/* MEMC_DDR_0 :: DRAM_MODE_1 :: DDR3 :: ODT_CNTRL_1 [06:06] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_ODT_CNTRL_1_MASK 0x00000040
-#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_ODT_CNTRL_1_SHIFT 6
-#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_ODT_CNTRL_1_DEFAULT 0x00000000
-
-/* MEMC_DDR_0 :: DRAM_MODE_1 :: DDR3 :: DRIVER_IMP_CNTRL_1 [05:05] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_DRIVER_IMP_CNTRL_1_MASK 0x00000020
-#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_DRIVER_IMP_CNTRL_1_SHIFT 5
-#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_DRIVER_IMP_CNTRL_1_DEFAULT 0x00000000
-
-/* MEMC_DDR_0 :: DRAM_MODE_1 :: DDR3 :: AL [04:03] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_AL_MASK 0x00000018
-#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_AL_SHIFT 3
-#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_AL_DEFAULT 0x00000001
-
-/* MEMC_DDR_0 :: DRAM_MODE_1 :: DDR3 :: ODT_CNTRL_0 [02:02] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_ODT_CNTRL_0_MASK 0x00000004
-#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_ODT_CNTRL_0_SHIFT 2
-#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_ODT_CNTRL_0_DEFAULT 0x00000001
-
-/* MEMC_DDR_0 :: DRAM_MODE_1 :: DDR3 :: DRIVER_IMP_CNTRL_0 [01:01] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_DRIVER_IMP_CNTRL_0_MASK 0x00000002
-#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_DRIVER_IMP_CNTRL_0_SHIFT 1
-#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_DRIVER_IMP_CNTRL_0_DEFAULT 0x00000000
-
-/* MEMC_DDR_0 :: DRAM_MODE_1 :: DDR3 :: DLL_EN [00:00] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_DLL_EN_MASK 0x00000001
-#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_DLL_EN_SHIFT 0
-#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_DLL_EN_DEFAULT 0x00000000
-#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_DLL_EN_ENABLE 0
-#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_DLL_EN_DISABLE 1
-
-/* union - case DDR4 [12:00] */
-/* MEMC_DDR_0 :: DRAM_MODE_1 :: DDR4 :: Q_OFF [12:12] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR4_Q_OFF_MASK 0x00001000
-#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR4_Q_OFF_SHIFT 12
-#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR4_Q_OFF_DEFAULT 0x00000000
-#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR4_Q_OFF_ENABLE 0
-#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR4_Q_OFF_DISABLE 1
-
-/* MEMC_DDR_0 :: DRAM_MODE_1 :: DDR4 :: TDQS [11:11] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR4_TDQS_MASK 0x00000800
-#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR4_TDQS_SHIFT 11
-#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR4_TDQS_DEFAULT 0x00000000
-#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR4_TDQS_ENABLE 1
-#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR4_TDQS_DISABLE 0
-
-/* MEMC_DDR_0 :: DRAM_MODE_1 :: DDR4 :: unused_1 [10:10] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR4_unused_1_MASK 0x00000400
-#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR4_unused_1_SHIFT 10
-#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR4_unused_1_DEFAULT 0x00000000
-
-/* MEMC_DDR_0 :: DRAM_MODE_1 :: DDR4 :: ODT_CNTRL_2 [09:09] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR4_ODT_CNTRL_2_MASK 0x00000200
-#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR4_ODT_CNTRL_2_SHIFT 9
-#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR4_ODT_CNTRL_2_DEFAULT 0x00000000
-
-/* MEMC_DDR_0 :: DRAM_MODE_1 :: DDR4 :: unused_2 [08:08] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR4_unused_2_MASK 0x00000100
-#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR4_unused_2_SHIFT 8
-#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR4_unused_2_DEFAULT 0x00000000
-
-/* MEMC_DDR_0 :: DRAM_MODE_1 :: DDR4 :: WR_LEVEL [07:07] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR4_WR_LEVEL_MASK 0x00000080
-#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR4_WR_LEVEL_SHIFT 7
-#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR4_WR_LEVEL_DEFAULT 0x00000000
-#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR4_WR_LEVEL_ENABLE 1
-#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR4_WR_LEVEL_DISABLE 0
-
-/* MEMC_DDR_0 :: DRAM_MODE_1 :: DDR4 :: ODT_CNTRL_1 [06:06] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR4_ODT_CNTRL_1_MASK 0x00000040
-#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR4_ODT_CNTRL_1_SHIFT 6
-#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR4_ODT_CNTRL_1_DEFAULT 0x00000000
-
-/* MEMC_DDR_0 :: DRAM_MODE_1 :: DDR4 :: DRIVER_IMP_CNTRL_1 [05:05] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR4_DRIVER_IMP_CNTRL_1_MASK 0x00000020
-#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR4_DRIVER_IMP_CNTRL_1_SHIFT 5
-#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR4_DRIVER_IMP_CNTRL_1_DEFAULT 0x00000000
-
-/* MEMC_DDR_0 :: DRAM_MODE_1 :: DDR4 :: AL [04:03] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR4_AL_MASK 0x00000018
-#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR4_AL_SHIFT 3
-#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR4_AL_DEFAULT 0x00000001
-
-/* MEMC_DDR_0 :: DRAM_MODE_1 :: DDR4 :: ODT_CNTRL_0 [02:02] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR4_ODT_CNTRL_0_MASK 0x00000004
-#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR4_ODT_CNTRL_0_SHIFT 2
-#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR4_ODT_CNTRL_0_DEFAULT 0x00000001
-
-/* MEMC_DDR_0 :: DRAM_MODE_1 :: DDR4 :: DRIVER_IMP_CNTRL_0 [01:01] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR4_DRIVER_IMP_CNTRL_0_MASK 0x00000002
-#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR4_DRIVER_IMP_CNTRL_0_SHIFT 1
-#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR4_DRIVER_IMP_CNTRL_0_DEFAULT 0x00000000
-
-/* MEMC_DDR_0 :: DRAM_MODE_1 :: DDR4 :: DLL_EN [00:00] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR4_DLL_EN_MASK 0x00000001
-#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR4_DLL_EN_SHIFT 0
-#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR4_DLL_EN_DEFAULT 0x00000000
-#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR4_DLL_EN_ENABLE 0
-#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR4_DLL_EN_DISABLE 1
-
-/* union - case GDDR5M [12:00] */
-/* MEMC_DDR_0 :: DRAM_MODE_1 :: GDDR5M :: unused_1 [12:11] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_1_GDDR5M_unused_1_MASK 0x00001800
-#define BCHP_MEMC_DDR_0_DRAM_MODE_1_GDDR5M_unused_1_SHIFT 11
-#define BCHP_MEMC_DDR_0_DRAM_MODE_1_GDDR5M_unused_1_DEFAULT 0x00000000
-
-/* MEMC_DDR_0 :: DRAM_MODE_1 :: GDDR5M :: ABI [10:10] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_1_GDDR5M_ABI_MASK 0x00000400
-#define BCHP_MEMC_DDR_0_DRAM_MODE_1_GDDR5M_ABI_SHIFT 10
-#define BCHP_MEMC_DDR_0_DRAM_MODE_1_GDDR5M_ABI_DEFAULT 0x00000000
-#define BCHP_MEMC_DDR_0_DRAM_MODE_1_GDDR5M_ABI_ENABLE 0
-#define BCHP_MEMC_DDR_0_DRAM_MODE_1_GDDR5M_ABI_DISABLE 1
-
-/* MEMC_DDR_0 :: DRAM_MODE_1 :: GDDR5M :: WDBI [09:09] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_1_GDDR5M_WDBI_MASK 0x00000200
-#define BCHP_MEMC_DDR_0_DRAM_MODE_1_GDDR5M_WDBI_SHIFT 9
-#define BCHP_MEMC_DDR_0_DRAM_MODE_1_GDDR5M_WDBI_DEFAULT 0x00000000
-#define BCHP_MEMC_DDR_0_DRAM_MODE_1_GDDR5M_WDBI_ENABLE 0
-#define BCHP_MEMC_DDR_0_DRAM_MODE_1_GDDR5M_WDBI_DISABLE 1
-
-/* MEMC_DDR_0 :: DRAM_MODE_1 :: GDDR5M :: RDBI [08:08] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_1_GDDR5M_RDBI_MASK 0x00000100
-#define BCHP_MEMC_DDR_0_DRAM_MODE_1_GDDR5M_RDBI_SHIFT 8
-#define BCHP_MEMC_DDR_0_DRAM_MODE_1_GDDR5M_RDBI_DEFAULT 0x00000000
-#define BCHP_MEMC_DDR_0_DRAM_MODE_1_GDDR5M_RDBI_ENABLE 0
-#define BCHP_MEMC_DDR_0_DRAM_MODE_1_GDDR5M_RDBI_DISABLE 1
-
-/* MEMC_DDR_0 :: DRAM_MODE_1 :: GDDR5M :: unused_2 [07:07] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_1_GDDR5M_unused_2_MASK 0x00000080
-#define BCHP_MEMC_DDR_0_DRAM_MODE_1_GDDR5M_unused_2_SHIFT 7
-#define BCHP_MEMC_DDR_0_DRAM_MODE_1_GDDR5M_unused_2_DEFAULT 0x00000000
-
-/* MEMC_DDR_0 :: DRAM_MODE_1 :: GDDR5M :: CAL_UPD [06:06] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_1_GDDR5M_CAL_UPD_MASK 0x00000040
-#define BCHP_MEMC_DDR_0_DRAM_MODE_1_GDDR5M_CAL_UPD_SHIFT 6
-#define BCHP_MEMC_DDR_0_DRAM_MODE_1_GDDR5M_CAL_UPD_DEFAULT 0x00000000
-#define BCHP_MEMC_DDR_0_DRAM_MODE_1_GDDR5M_CAL_UPD_ENABLE 0
-#define BCHP_MEMC_DDR_0_DRAM_MODE_1_GDDR5M_CAL_UPD_DISABLE 1
-
-/* MEMC_DDR_0 :: DRAM_MODE_1 :: GDDR5M :: ADDR_CMD_TERM [05:04] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_1_GDDR5M_ADDR_CMD_TERM_MASK 0x00000030
-#define BCHP_MEMC_DDR_0_DRAM_MODE_1_GDDR5M_ADDR_CMD_TERM_SHIFT 4
-#define BCHP_MEMC_DDR_0_DRAM_MODE_1_GDDR5M_ADDR_CMD_TERM_DEFAULT 0x00000000
-
-/* MEMC_DDR_0 :: DRAM_MODE_1 :: GDDR5M :: DATA_TERM [03:02] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_1_GDDR5M_DATA_TERM_MASK 0x0000000c
-#define BCHP_MEMC_DDR_0_DRAM_MODE_1_GDDR5M_DATA_TERM_SHIFT 2
-#define BCHP_MEMC_DDR_0_DRAM_MODE_1_GDDR5M_DATA_TERM_DEFAULT 0x00000000
-
-/* MEMC_DDR_0 :: DRAM_MODE_1 :: GDDR5M :: DRIVER_STRENGTH [01:00] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_1_GDDR5M_DRIVER_STRENGTH_MASK 0x00000003
-#define BCHP_MEMC_DDR_0_DRAM_MODE_1_GDDR5M_DRIVER_STRENGTH_SHIFT 0
-#define BCHP_MEMC_DDR_0_DRAM_MODE_1_GDDR5M_DRIVER_STRENGTH_DEFAULT 0x00000000
-
-/* union - case GDDR5 [12:00] */
-/* MEMC_DDR_0 :: DRAM_MODE_1 :: GDDR5 :: unused_1 [12:12] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_1_GDDR5_unused_1_MASK 0x00001000
-#define BCHP_MEMC_DDR_0_DRAM_MODE_1_GDDR5_unused_1_SHIFT 12
-#define BCHP_MEMC_DDR_0_DRAM_MODE_1_GDDR5_unused_1_DEFAULT 0x00000000
-
-/* MEMC_DDR_0 :: DRAM_MODE_1 :: GDDR5 :: PLL_DLL_RST [11:11] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_1_GDDR5_PLL_DLL_RST_MASK 0x00000800
-#define BCHP_MEMC_DDR_0_DRAM_MODE_1_GDDR5_PLL_DLL_RST_SHIFT 11
-#define BCHP_MEMC_DDR_0_DRAM_MODE_1_GDDR5_PLL_DLL_RST_DEFAULT 0x00000000
-
-/* MEMC_DDR_0 :: DRAM_MODE_1 :: GDDR5 :: ABI [10:10] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_1_GDDR5_ABI_MASK 0x00000400
-#define BCHP_MEMC_DDR_0_DRAM_MODE_1_GDDR5_ABI_SHIFT 10
-#define BCHP_MEMC_DDR_0_DRAM_MODE_1_GDDR5_ABI_DEFAULT 0x00000000
-#define BCHP_MEMC_DDR_0_DRAM_MODE_1_GDDR5_ABI_ENABLE 0
-#define BCHP_MEMC_DDR_0_DRAM_MODE_1_GDDR5_ABI_DISABLE 1
-
-/* MEMC_DDR_0 :: DRAM_MODE_1 :: GDDR5 :: WDBI [09:09] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_1_GDDR5_WDBI_MASK 0x00000200
-#define BCHP_MEMC_DDR_0_DRAM_MODE_1_GDDR5_WDBI_SHIFT 9
-#define BCHP_MEMC_DDR_0_DRAM_MODE_1_GDDR5_WDBI_DEFAULT 0x00000000
-#define BCHP_MEMC_DDR_0_DRAM_MODE_1_GDDR5_WDBI_ENABLE 0
-#define BCHP_MEMC_DDR_0_DRAM_MODE_1_GDDR5_WDBI_DISABLE 1
-
-/* MEMC_DDR_0 :: DRAM_MODE_1 :: GDDR5 :: RDBI [08:08] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_1_GDDR5_RDBI_MASK 0x00000100
-#define BCHP_MEMC_DDR_0_DRAM_MODE_1_GDDR5_RDBI_SHIFT 8
-#define BCHP_MEMC_DDR_0_DRAM_MODE_1_GDDR5_RDBI_DEFAULT 0x00000000
-#define BCHP_MEMC_DDR_0_DRAM_MODE_1_GDDR5_RDBI_ENABLE 0
-#define BCHP_MEMC_DDR_0_DRAM_MODE_1_GDDR5_RDBI_DISABLE 1
-
-/* MEMC_DDR_0 :: DRAM_MODE_1 :: GDDR5 :: PLL_DLL [07:07] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_1_GDDR5_PLL_DLL_MASK 0x00000080
-#define BCHP_MEMC_DDR_0_DRAM_MODE_1_GDDR5_PLL_DLL_SHIFT 7
-#define BCHP_MEMC_DDR_0_DRAM_MODE_1_GDDR5_PLL_DLL_DEFAULT 0x00000000
-
-/* MEMC_DDR_0 :: DRAM_MODE_1 :: GDDR5 :: CAL_UPD [06:06] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_1_GDDR5_CAL_UPD_MASK 0x00000040
-#define BCHP_MEMC_DDR_0_DRAM_MODE_1_GDDR5_CAL_UPD_SHIFT 6
-#define BCHP_MEMC_DDR_0_DRAM_MODE_1_GDDR5_CAL_UPD_DEFAULT 0x00000000
-#define BCHP_MEMC_DDR_0_DRAM_MODE_1_GDDR5_CAL_UPD_ENABLE 0
-#define BCHP_MEMC_DDR_0_DRAM_MODE_1_GDDR5_CAL_UPD_DISABLE 1
-
-/* MEMC_DDR_0 :: DRAM_MODE_1 :: GDDR5 :: ADDR_CMD_TERM [05:04] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_1_GDDR5_ADDR_CMD_TERM_MASK 0x00000030
-#define BCHP_MEMC_DDR_0_DRAM_MODE_1_GDDR5_ADDR_CMD_TERM_SHIFT 4
-#define BCHP_MEMC_DDR_0_DRAM_MODE_1_GDDR5_ADDR_CMD_TERM_DEFAULT 0x00000000
-
-/* MEMC_DDR_0 :: DRAM_MODE_1 :: GDDR5 :: DATA_TERM [03:02] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_1_GDDR5_DATA_TERM_MASK 0x0000000c
-#define BCHP_MEMC_DDR_0_DRAM_MODE_1_GDDR5_DATA_TERM_SHIFT 2
-#define BCHP_MEMC_DDR_0_DRAM_MODE_1_GDDR5_DATA_TERM_DEFAULT 0x00000000
-
-/* MEMC_DDR_0 :: DRAM_MODE_1 :: GDDR5 :: DRIVER_STRENGTH [01:00] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_1_GDDR5_DRIVER_STRENGTH_MASK 0x00000003
-#define BCHP_MEMC_DDR_0_DRAM_MODE_1_GDDR5_DRIVER_STRENGTH_SHIFT 0
-#define BCHP_MEMC_DDR_0_DRAM_MODE_1_GDDR5_DRIVER_STRENGTH_DEFAULT 0x00000000
-
-/***************************************************************************
- *DRAM_MODE_2 - Dram Mode Register 2
- ***************************************************************************/
-/* MEMC_DDR_0 :: DRAM_MODE_2 :: reserved0 [31:16] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_2_reserved0_MASK 0xffff0000
-#define BCHP_MEMC_DDR_0_DRAM_MODE_2_reserved0_SHIFT 16
-
-/* MEMC_DDR_0 :: DRAM_MODE_2 :: unused_0 [15:13] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_2_unused_0_MASK 0x0000e000
-#define BCHP_MEMC_DDR_0_DRAM_MODE_2_unused_0_SHIFT 13
-#define BCHP_MEMC_DDR_0_DRAM_MODE_2_unused_0_DEFAULT 0x00000000
-
-/* union - case DDR3 [12:00] */
-/* MEMC_DDR_0 :: DRAM_MODE_2 :: DDR3 :: unused_1 [12:11] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR3_unused_1_MASK 0x00001800
-#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR3_unused_1_SHIFT 11
-#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR3_unused_1_DEFAULT 0x00000000
-
-/* MEMC_DDR_0 :: DRAM_MODE_2 :: DDR3 :: WR_ODT [10:09] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR3_WR_ODT_MASK 0x00000600
-#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR3_WR_ODT_SHIFT 9
-#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR3_WR_ODT_DEFAULT 0x00000001
-
-/* MEMC_DDR_0 :: DRAM_MODE_2 :: DDR3 :: unused_2 [08:08] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR3_unused_2_MASK 0x00000100
-#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR3_unused_2_SHIFT 8
-#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR3_unused_2_DEFAULT 0x00000000
-
-/* MEMC_DDR_0 :: DRAM_MODE_2 :: DDR3 :: SRF_TR [07:07] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR3_SRF_TR_MASK 0x00000080
-#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR3_SRF_TR_SHIFT 7
-#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR3_SRF_TR_DEFAULT 0x00000000
-
-/* MEMC_DDR_0 :: DRAM_MODE_2 :: DDR3 :: AUTO_SR [06:06] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR3_AUTO_SR_MASK 0x00000040
-#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR3_AUTO_SR_SHIFT 6
-#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR3_AUTO_SR_DEFAULT 0x00000001
-
-/* MEMC_DDR_0 :: DRAM_MODE_2 :: DDR3 :: WCL [05:03] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR3_WCL_MASK 0x00000038
-#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR3_WCL_SHIFT 3
-#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR3_WCL_DEFAULT 0x00000001
-
-/* MEMC_DDR_0 :: DRAM_MODE_2 :: DDR3 :: PASR [02:00] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR3_PASR_MASK 0x00000007
-#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR3_PASR_SHIFT 0
-#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR3_PASR_DEFAULT 0x00000000
-
-/* union - case DDR4 [12:00] */
-/* MEMC_DDR_0 :: DRAM_MODE_2 :: DDR4 :: WR_DATA_CRC [12:12] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR4_WR_DATA_CRC_MASK 0x00001000
-#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR4_WR_DATA_CRC_SHIFT 12
-#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR4_WR_DATA_CRC_DEFAULT 0x00000000
-#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR4_WR_DATA_CRC_ENABLE 1
-#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR4_WR_DATA_CRC_DISABLE 0
-
-/* MEMC_DDR_0 :: DRAM_MODE_2 :: DDR4 :: RD_DATA_CRC [11:11] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR4_RD_DATA_CRC_MASK 0x00000800
-#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR4_RD_DATA_CRC_SHIFT 11
-#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR4_RD_DATA_CRC_DEFAULT 0x00000000
-#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR4_RD_DATA_CRC_ENABLE 1
-#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR4_RD_DATA_CRC_DISABLE 0
-
-/* MEMC_DDR_0 :: DRAM_MODE_2 :: DDR4 :: RTT_WR [10:09] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR4_RTT_WR_MASK 0x00000600
-#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR4_RTT_WR_SHIFT 9
-#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR4_RTT_WR_DEFAULT 0x00000001
-
-/* MEMC_DDR_0 :: DRAM_MODE_2 :: DDR4 :: unused_1 [08:08] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR4_unused_1_MASK 0x00000100
-#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR4_unused_1_SHIFT 8
-#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR4_unused_1_DEFAULT 0x00000000
-
-/* MEMC_DDR_0 :: DRAM_MODE_2 :: DDR4 :: LPASR [07:06] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR4_LPASR_MASK 0x000000c0
-#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR4_LPASR_SHIFT 6
-#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR4_LPASR_DEFAULT 0x00000000
-
-/* MEMC_DDR_0 :: DRAM_MODE_2 :: DDR4 :: CWL [05:03] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR4_CWL_MASK 0x00000038
-#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR4_CWL_SHIFT 3
-#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR4_CWL_DEFAULT 0x00000001
-
-/* MEMC_DDR_0 :: DRAM_MODE_2 :: DDR4 :: PASR [02:00] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR4_PASR_MASK 0x00000007
-#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR4_PASR_SHIFT 0
-#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR4_PASR_DEFAULT 0x00000000
-
-/* union - case GDDR5M [12:00] */
-/* MEMC_DDR_0 :: DRAM_MODE_2 :: GDDR5M :: unused_1 [12:12] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_2_GDDR5M_unused_1_MASK 0x00001000
-#define BCHP_MEMC_DDR_0_DRAM_MODE_2_GDDR5M_unused_1_SHIFT 12
-#define BCHP_MEMC_DDR_0_DRAM_MODE_2_GDDR5M_unused_1_DEFAULT 0x00000000
-
-/* MEMC_DDR_0 :: DRAM_MODE_2 :: GDDR5M :: ADDR_CMD_TERM_OFFSET [11:09] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_2_GDDR5M_ADDR_CMD_TERM_OFFSET_MASK 0x00000e00
-#define BCHP_MEMC_DDR_0_DRAM_MODE_2_GDDR5M_ADDR_CMD_TERM_OFFSET_SHIFT 9
-#define BCHP_MEMC_DDR_0_DRAM_MODE_2_GDDR5M_ADDR_CMD_TERM_OFFSET_DEFAULT 0x00000000
-
-/* MEMC_DDR_0 :: DRAM_MODE_2 :: GDDR5M :: DATA_WCK_TERM_OFFSET [08:06] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_2_GDDR5M_DATA_WCK_TERM_OFFSET_MASK 0x000001c0
-#define BCHP_MEMC_DDR_0_DRAM_MODE_2_GDDR5M_DATA_WCK_TERM_OFFSET_SHIFT 6
-#define BCHP_MEMC_DDR_0_DRAM_MODE_2_GDDR5M_DATA_WCK_TERM_OFFSET_DEFAULT 0x00000000
-
-/* MEMC_DDR_0 :: DRAM_MODE_2 :: GDDR5M :: OCD_PUP_DRIVER_OFFSET [05:03] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_2_GDDR5M_OCD_PUP_DRIVER_OFFSET_MASK 0x00000038
-#define BCHP_MEMC_DDR_0_DRAM_MODE_2_GDDR5M_OCD_PUP_DRIVER_OFFSET_SHIFT 3
-#define BCHP_MEMC_DDR_0_DRAM_MODE_2_GDDR5M_OCD_PUP_DRIVER_OFFSET_DEFAULT 0x00000000
-
-/* MEMC_DDR_0 :: DRAM_MODE_2 :: GDDR5M :: OCD_PDN_DRIVER_OFFSET [02:00] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_2_GDDR5M_OCD_PDN_DRIVER_OFFSET_MASK 0x00000007
-#define BCHP_MEMC_DDR_0_DRAM_MODE_2_GDDR5M_OCD_PDN_DRIVER_OFFSET_SHIFT 0
-#define BCHP_MEMC_DDR_0_DRAM_MODE_2_GDDR5M_OCD_PDN_DRIVER_OFFSET_DEFAULT 0x00000000
-
-/* union - case GDDR5 [12:00] */
-/* MEMC_DDR_0 :: DRAM_MODE_2 :: GDDR5 :: unused_1 [12:12] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_2_GDDR5_unused_1_MASK 0x00001000
-#define BCHP_MEMC_DDR_0_DRAM_MODE_2_GDDR5_unused_1_SHIFT 12
-#define BCHP_MEMC_DDR_0_DRAM_MODE_2_GDDR5_unused_1_DEFAULT 0x00000000
-
-/* MEMC_DDR_0 :: DRAM_MODE_2 :: GDDR5 :: ADDR_CMD_TERM_OFFSET [11:09] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_2_GDDR5_ADDR_CMD_TERM_OFFSET_MASK 0x00000e00
-#define BCHP_MEMC_DDR_0_DRAM_MODE_2_GDDR5_ADDR_CMD_TERM_OFFSET_SHIFT 9
-#define BCHP_MEMC_DDR_0_DRAM_MODE_2_GDDR5_ADDR_CMD_TERM_OFFSET_DEFAULT 0x00000000
-
-/* MEMC_DDR_0 :: DRAM_MODE_2 :: GDDR5 :: DATA_WCK_TERM_OFFSET [08:06] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_2_GDDR5_DATA_WCK_TERM_OFFSET_MASK 0x000001c0
-#define BCHP_MEMC_DDR_0_DRAM_MODE_2_GDDR5_DATA_WCK_TERM_OFFSET_SHIFT 6
-#define BCHP_MEMC_DDR_0_DRAM_MODE_2_GDDR5_DATA_WCK_TERM_OFFSET_DEFAULT 0x00000000
-
-/* MEMC_DDR_0 :: DRAM_MODE_2 :: GDDR5 :: OCD_PUP_DRIVER_OFFSET [05:03] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_2_GDDR5_OCD_PUP_DRIVER_OFFSET_MASK 0x00000038
-#define BCHP_MEMC_DDR_0_DRAM_MODE_2_GDDR5_OCD_PUP_DRIVER_OFFSET_SHIFT 3
-#define BCHP_MEMC_DDR_0_DRAM_MODE_2_GDDR5_OCD_PUP_DRIVER_OFFSET_DEFAULT 0x00000000
-
-/* MEMC_DDR_0 :: DRAM_MODE_2 :: GDDR5 :: OCD_PDN_DRIVER_OFFSET [02:00] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_2_GDDR5_OCD_PDN_DRIVER_OFFSET_MASK 0x00000007
-#define BCHP_MEMC_DDR_0_DRAM_MODE_2_GDDR5_OCD_PDN_DRIVER_OFFSET_SHIFT 0
-#define BCHP_MEMC_DDR_0_DRAM_MODE_2_GDDR5_OCD_PDN_DRIVER_OFFSET_DEFAULT 0x00000000
-
-/***************************************************************************
- *DRAM_MODE_3 - Dram Mode Register 3
- ***************************************************************************/
-/* MEMC_DDR_0 :: DRAM_MODE_3 :: reserved0 [31:16] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_3_reserved0_MASK 0xffff0000
-#define BCHP_MEMC_DDR_0_DRAM_MODE_3_reserved0_SHIFT 16
-
-/* MEMC_DDR_0 :: DRAM_MODE_3 :: unused_0 [15:13] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_3_unused_0_MASK 0x0000e000
-#define BCHP_MEMC_DDR_0_DRAM_MODE_3_unused_0_SHIFT 13
-#define BCHP_MEMC_DDR_0_DRAM_MODE_3_unused_0_DEFAULT 0x00000000
-
-/* union - case DDR3 [12:00] */
-/* MEMC_DDR_0 :: DRAM_MODE_3 :: DDR3 :: unused_1 [12:03] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_3_DDR3_unused_1_MASK 0x00001ff8
-#define BCHP_MEMC_DDR_0_DRAM_MODE_3_DDR3_unused_1_SHIFT 3
-#define BCHP_MEMC_DDR_0_DRAM_MODE_3_DDR3_unused_1_DEFAULT 0x00000000
-
-/* MEMC_DDR_0 :: DRAM_MODE_3 :: DDR3 :: MPR [02:02] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_3_DDR3_MPR_MASK 0x00000004
-#define BCHP_MEMC_DDR_0_DRAM_MODE_3_DDR3_MPR_SHIFT 2
-#define BCHP_MEMC_DDR_0_DRAM_MODE_3_DDR3_MPR_DEFAULT 0x00000000
-
-/* MEMC_DDR_0 :: DRAM_MODE_3 :: DDR3 :: MPR_LOC [01:00] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_3_DDR3_MPR_LOC_MASK 0x00000003
-#define BCHP_MEMC_DDR_0_DRAM_MODE_3_DDR3_MPR_LOC_SHIFT 0
-#define BCHP_MEMC_DDR_0_DRAM_MODE_3_DDR3_MPR_LOC_DEFAULT 0x00000000
-
-/* union - case DDR4 [12:00] */
-/* MEMC_DDR_0 :: DRAM_MODE_3 :: DDR4 :: MPR_READ_FORMAT [12:11] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_3_DDR4_MPR_READ_FORMAT_MASK 0x00001800
-#define BCHP_MEMC_DDR_0_DRAM_MODE_3_DDR4_MPR_READ_FORMAT_SHIFT 11
-#define BCHP_MEMC_DDR_0_DRAM_MODE_3_DDR4_MPR_READ_FORMAT_DEFAULT 0x00000000
-
-/* MEMC_DDR_0 :: DRAM_MODE_3 :: DDR4 :: unused_1 [10:09] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_3_DDR4_unused_1_MASK 0x00000600
-#define BCHP_MEMC_DDR_0_DRAM_MODE_3_DDR4_unused_1_SHIFT 9
-#define BCHP_MEMC_DDR_0_DRAM_MODE_3_DDR4_unused_1_DEFAULT 0x00000000
-
-/* MEMC_DDR_0 :: DRAM_MODE_3 :: DDR4 :: FGR [08:06] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_3_DDR4_FGR_MASK 0x000001c0
-#define BCHP_MEMC_DDR_0_DRAM_MODE_3_DDR4_FGR_SHIFT 6
-#define BCHP_MEMC_DDR_0_DRAM_MODE_3_DDR4_FGR_DEFAULT 0x00000000
-
-/* MEMC_DDR_0 :: DRAM_MODE_3 :: DDR4 :: MRS_READOUT [05:05] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_3_DDR4_MRS_READOUT_MASK 0x00000020
-#define BCHP_MEMC_DDR_0_DRAM_MODE_3_DDR4_MRS_READOUT_SHIFT 5
-#define BCHP_MEMC_DDR_0_DRAM_MODE_3_DDR4_MRS_READOUT_DEFAULT 0x00000000
-#define BCHP_MEMC_DDR_0_DRAM_MODE_3_DDR4_MRS_READOUT_ENABLE 1
-#define BCHP_MEMC_DDR_0_DRAM_MODE_3_DDR4_MRS_READOUT_DISABLE 0
-
-/* MEMC_DDR_0 :: DRAM_MODE_3 :: DDR4 :: PER_DRAM_ADDR [04:04] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_3_DDR4_PER_DRAM_ADDR_MASK 0x00000010
-#define BCHP_MEMC_DDR_0_DRAM_MODE_3_DDR4_PER_DRAM_ADDR_SHIFT 4
-#define BCHP_MEMC_DDR_0_DRAM_MODE_3_DDR4_PER_DRAM_ADDR_DEFAULT 0x00000000
-#define BCHP_MEMC_DDR_0_DRAM_MODE_3_DDR4_PER_DRAM_ADDR_ENABLE 1
-#define BCHP_MEMC_DDR_0_DRAM_MODE_3_DDR4_PER_DRAM_ADDR_DISABLE 0
-
-/* MEMC_DDR_0 :: DRAM_MODE_3 :: DDR4 :: GEARDOWN [03:03] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_3_DDR4_GEARDOWN_MASK 0x00000008
-#define BCHP_MEMC_DDR_0_DRAM_MODE_3_DDR4_GEARDOWN_SHIFT 3
-#define BCHP_MEMC_DDR_0_DRAM_MODE_3_DDR4_GEARDOWN_DEFAULT 0x00000000
-
-/* MEMC_DDR_0 :: DRAM_MODE_3 :: DDR4 :: MPR [02:02] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_3_DDR4_MPR_MASK 0x00000004
-#define BCHP_MEMC_DDR_0_DRAM_MODE_3_DDR4_MPR_SHIFT 2
-#define BCHP_MEMC_DDR_0_DRAM_MODE_3_DDR4_MPR_DEFAULT 0x00000000
-
-/* MEMC_DDR_0 :: DRAM_MODE_3 :: DDR4 :: MPR_PAGE [01:00] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_3_DDR4_MPR_PAGE_MASK 0x00000003
-#define BCHP_MEMC_DDR_0_DRAM_MODE_3_DDR4_MPR_PAGE_SHIFT 0
-#define BCHP_MEMC_DDR_0_DRAM_MODE_3_DDR4_MPR_PAGE_DEFAULT 0x00000000
-
-/* union - case GDDR5M [12:00] */
-/* MEMC_DDR_0 :: DRAM_MODE_3 :: GDDR5M :: unused_1 [12:12] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_3_GDDR5M_unused_1_MASK 0x00001000
-#define BCHP_MEMC_DDR_0_DRAM_MODE_3_GDDR5M_unused_1_SHIFT 12
-#define BCHP_MEMC_DDR_0_DRAM_MODE_3_GDDR5M_unused_1_DEFAULT 0x00000000
-
-/* MEMC_DDR_0 :: DRAM_MODE_3 :: GDDR5M :: BANK_GROUPS [11:10] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_3_GDDR5M_BANK_GROUPS_MASK 0x00000c00
-#define BCHP_MEMC_DDR_0_DRAM_MODE_3_GDDR5M_BANK_GROUPS_SHIFT 10
-#define BCHP_MEMC_DDR_0_DRAM_MODE_3_GDDR5M_BANK_GROUPS_DEFAULT 0x00000000
-
-/* MEMC_DDR_0 :: DRAM_MODE_3 :: GDDR5M :: WCK_TERM [09:08] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_3_GDDR5M_WCK_TERM_MASK 0x00000300
-#define BCHP_MEMC_DDR_0_DRAM_MODE_3_GDDR5M_WCK_TERM_SHIFT 8
-#define BCHP_MEMC_DDR_0_DRAM_MODE_3_GDDR5M_WCK_TERM_DEFAULT 0x00000000
-
-/* MEMC_DDR_0 :: DRAM_MODE_3 :: GDDR5M :: DRAM_INFO [07:06] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_3_GDDR5M_DRAM_INFO_MASK 0x000000c0
-#define BCHP_MEMC_DDR_0_DRAM_MODE_3_GDDR5M_DRAM_INFO_SHIFT 6
-#define BCHP_MEMC_DDR_0_DRAM_MODE_3_GDDR5M_DRAM_INFO_DEFAULT 0x00000000
-
-/* MEMC_DDR_0 :: DRAM_MODE_3 :: GDDR5M :: RDQS_MODE [05:05] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_3_GDDR5M_RDQS_MODE_MASK 0x00000020
-#define BCHP_MEMC_DDR_0_DRAM_MODE_3_GDDR5M_RDQS_MODE_SHIFT 5
-#define BCHP_MEMC_DDR_0_DRAM_MODE_3_GDDR5M_RDQS_MODE_DEFAULT 0x00000000
-#define BCHP_MEMC_DDR_0_DRAM_MODE_3_GDDR5M_RDQS_MODE_ENABLE 1
-#define BCHP_MEMC_DDR_0_DRAM_MODE_3_GDDR5M_RDQS_MODE_DISABLE 0
-
-/* MEMC_DDR_0 :: DRAM_MODE_3 :: GDDR5M :: WCK2CK_TRAIN [04:04] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_3_GDDR5M_WCK2CK_TRAIN_MASK 0x00000010
-#define BCHP_MEMC_DDR_0_DRAM_MODE_3_GDDR5M_WCK2CK_TRAIN_SHIFT 4
-#define BCHP_MEMC_DDR_0_DRAM_MODE_3_GDDR5M_WCK2CK_TRAIN_DEFAULT 0x00000000
-#define BCHP_MEMC_DDR_0_DRAM_MODE_3_GDDR5M_WCK2CK_TRAIN_ENABLE 1
-#define BCHP_MEMC_DDR_0_DRAM_MODE_3_GDDR5M_WCK2CK_TRAIN_DISABLE 0
-
-/* MEMC_DDR_0 :: DRAM_MODE_3 :: GDDR5M :: WCK23_INVERT [03:03] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_3_GDDR5M_WCK23_INVERT_MASK 0x00000008
-#define BCHP_MEMC_DDR_0_DRAM_MODE_3_GDDR5M_WCK23_INVERT_SHIFT 3
-#define BCHP_MEMC_DDR_0_DRAM_MODE_3_GDDR5M_WCK23_INVERT_DEFAULT 0x00000000
-#define BCHP_MEMC_DDR_0_DRAM_MODE_3_GDDR5M_WCK23_INVERT_ENABLE 1
-#define BCHP_MEMC_DDR_0_DRAM_MODE_3_GDDR5M_WCK23_INVERT_DISABLE 0
-
-/* MEMC_DDR_0 :: DRAM_MODE_3 :: GDDR5M :: WCK01_INVERT [02:02] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_3_GDDR5M_WCK01_INVERT_MASK 0x00000004
-#define BCHP_MEMC_DDR_0_DRAM_MODE_3_GDDR5M_WCK01_INVERT_SHIFT 2
-#define BCHP_MEMC_DDR_0_DRAM_MODE_3_GDDR5M_WCK01_INVERT_DEFAULT 0x00000000
-#define BCHP_MEMC_DDR_0_DRAM_MODE_3_GDDR5M_WCK01_INVERT_ENABLE 1
-#define BCHP_MEMC_DDR_0_DRAM_MODE_3_GDDR5M_WCK01_INVERT_DISABLE 0
-
-/* MEMC_DDR_0 :: DRAM_MODE_3 :: GDDR5M :: SELF_REFRESH [01:00] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_3_GDDR5M_SELF_REFRESH_MASK 0x00000003
-#define BCHP_MEMC_DDR_0_DRAM_MODE_3_GDDR5M_SELF_REFRESH_SHIFT 0
-#define BCHP_MEMC_DDR_0_DRAM_MODE_3_GDDR5M_SELF_REFRESH_DEFAULT 0x00000000
-
-/* union - case GDDR5 [12:00] */
-/* MEMC_DDR_0 :: DRAM_MODE_3 :: GDDR5 :: unused_1 [12:12] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_3_GDDR5_unused_1_MASK 0x00001000
-#define BCHP_MEMC_DDR_0_DRAM_MODE_3_GDDR5_unused_1_SHIFT 12
-#define BCHP_MEMC_DDR_0_DRAM_MODE_3_GDDR5_unused_1_DEFAULT 0x00000000
-
-/* MEMC_DDR_0 :: DRAM_MODE_3 :: GDDR5 :: BANK_GROUPS [11:10] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_3_GDDR5_BANK_GROUPS_MASK 0x00000c00
-#define BCHP_MEMC_DDR_0_DRAM_MODE_3_GDDR5_BANK_GROUPS_SHIFT 10
-#define BCHP_MEMC_DDR_0_DRAM_MODE_3_GDDR5_BANK_GROUPS_DEFAULT 0x00000000
-
-/* MEMC_DDR_0 :: DRAM_MODE_3 :: GDDR5 :: WCK_TERM [09:08] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_3_GDDR5_WCK_TERM_MASK 0x00000300
-#define BCHP_MEMC_DDR_0_DRAM_MODE_3_GDDR5_WCK_TERM_SHIFT 8
-#define BCHP_MEMC_DDR_0_DRAM_MODE_3_GDDR5_WCK_TERM_DEFAULT 0x00000000
-
-/* MEMC_DDR_0 :: DRAM_MODE_3 :: GDDR5 :: DRAM_INFO [07:06] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_3_GDDR5_DRAM_INFO_MASK 0x000000c0
-#define BCHP_MEMC_DDR_0_DRAM_MODE_3_GDDR5_DRAM_INFO_SHIFT 6
-#define BCHP_MEMC_DDR_0_DRAM_MODE_3_GDDR5_DRAM_INFO_DEFAULT 0x00000000
-
-/* MEMC_DDR_0 :: DRAM_MODE_3 :: GDDR5 :: RDQS_MODE [05:05] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_3_GDDR5_RDQS_MODE_MASK 0x00000020
-#define BCHP_MEMC_DDR_0_DRAM_MODE_3_GDDR5_RDQS_MODE_SHIFT 5
-#define BCHP_MEMC_DDR_0_DRAM_MODE_3_GDDR5_RDQS_MODE_DEFAULT 0x00000000
-#define BCHP_MEMC_DDR_0_DRAM_MODE_3_GDDR5_RDQS_MODE_ENABLE 1
-#define BCHP_MEMC_DDR_0_DRAM_MODE_3_GDDR5_RDQS_MODE_DISABLE 0
-
-/* MEMC_DDR_0 :: DRAM_MODE_3 :: GDDR5 :: WCK2CK_TRAIN [04:04] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_3_GDDR5_WCK2CK_TRAIN_MASK 0x00000010
-#define BCHP_MEMC_DDR_0_DRAM_MODE_3_GDDR5_WCK2CK_TRAIN_SHIFT 4
-#define BCHP_MEMC_DDR_0_DRAM_MODE_3_GDDR5_WCK2CK_TRAIN_DEFAULT 0x00000000
-#define BCHP_MEMC_DDR_0_DRAM_MODE_3_GDDR5_WCK2CK_TRAIN_ENABLE 1
-#define BCHP_MEMC_DDR_0_DRAM_MODE_3_GDDR5_WCK2CK_TRAIN_DISABLE 0
-
-/* MEMC_DDR_0 :: DRAM_MODE_3 :: GDDR5 :: WCK23_INVERT [03:03] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_3_GDDR5_WCK23_INVERT_MASK 0x00000008
-#define BCHP_MEMC_DDR_0_DRAM_MODE_3_GDDR5_WCK23_INVERT_SHIFT 3
-#define BCHP_MEMC_DDR_0_DRAM_MODE_3_GDDR5_WCK23_INVERT_DEFAULT 0x00000000
-#define BCHP_MEMC_DDR_0_DRAM_MODE_3_GDDR5_WCK23_INVERT_ENABLE 1
-#define BCHP_MEMC_DDR_0_DRAM_MODE_3_GDDR5_WCK23_INVERT_DISABLE 0
-
-/* MEMC_DDR_0 :: DRAM_MODE_3 :: GDDR5 :: WCK01_INVERT [02:02] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_3_GDDR5_WCK01_INVERT_MASK 0x00000004
-#define BCHP_MEMC_DDR_0_DRAM_MODE_3_GDDR5_WCK01_INVERT_SHIFT 2
-#define BCHP_MEMC_DDR_0_DRAM_MODE_3_GDDR5_WCK01_INVERT_DEFAULT 0x00000000
-#define BCHP_MEMC_DDR_0_DRAM_MODE_3_GDDR5_WCK01_INVERT_ENABLE 1
-#define BCHP_MEMC_DDR_0_DRAM_MODE_3_GDDR5_WCK01_INVERT_DISABLE 0
-
-/* MEMC_DDR_0 :: DRAM_MODE_3 :: GDDR5 :: SELF_REFRESH [01:00] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_3_GDDR5_SELF_REFRESH_MASK 0x00000003
-#define BCHP_MEMC_DDR_0_DRAM_MODE_3_GDDR5_SELF_REFRESH_SHIFT 0
-#define BCHP_MEMC_DDR_0_DRAM_MODE_3_GDDR5_SELF_REFRESH_DEFAULT 0x00000000
-
-/* union - case Others [12:00] */
-/* MEMC_DDR_0 :: DRAM_MODE_3 :: Others :: unused_1 [12:00] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_3_Others_unused_1_MASK 0x00001fff
-#define BCHP_MEMC_DDR_0_DRAM_MODE_3_Others_unused_1_SHIFT 0
-#define BCHP_MEMC_DDR_0_DRAM_MODE_3_Others_unused_1_DEFAULT 0x00000000
-
-/***************************************************************************
- *DRAM_MODE_4 - Dram Mode Register 4
- ***************************************************************************/
-/* MEMC_DDR_0 :: DRAM_MODE_4 :: reserved0 [31:16] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_4_reserved0_MASK 0xffff0000
-#define BCHP_MEMC_DDR_0_DRAM_MODE_4_reserved0_SHIFT 16
-
-/* MEMC_DDR_0 :: DRAM_MODE_4 :: unused_0 [15:13] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_4_unused_0_MASK 0x0000e000
-#define BCHP_MEMC_DDR_0_DRAM_MODE_4_unused_0_SHIFT 13
-#define BCHP_MEMC_DDR_0_DRAM_MODE_4_unused_0_DEFAULT 0x00000000
-
-/* union - case DDR4 [12:00] */
-/* MEMC_DDR_0 :: DRAM_MODE_4 :: DDR4 :: WR_PREAMBLE [12:12] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_4_DDR4_WR_PREAMBLE_MASK 0x00001000
-#define BCHP_MEMC_DDR_0_DRAM_MODE_4_DDR4_WR_PREAMBLE_SHIFT 12
-#define BCHP_MEMC_DDR_0_DRAM_MODE_4_DDR4_WR_PREAMBLE_DEFAULT 0x00000000
-
-/* MEMC_DDR_0 :: DRAM_MODE_4 :: DDR4 :: RD_PREAMBLE [11:11] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_4_DDR4_RD_PREAMBLE_MASK 0x00000800
-#define BCHP_MEMC_DDR_0_DRAM_MODE_4_DDR4_RD_PREAMBLE_SHIFT 11
-#define BCHP_MEMC_DDR_0_DRAM_MODE_4_DDR4_RD_PREAMBLE_DEFAULT 0x00000000
-
-/* MEMC_DDR_0 :: DRAM_MODE_4 :: DDR4 :: RD_PREAMBLE_TRAINING [10:10] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_4_DDR4_RD_PREAMBLE_TRAINING_MASK 0x00000400
-#define BCHP_MEMC_DDR_0_DRAM_MODE_4_DDR4_RD_PREAMBLE_TRAINING_SHIFT 10
-#define BCHP_MEMC_DDR_0_DRAM_MODE_4_DDR4_RD_PREAMBLE_TRAINING_DEFAULT 0x00000000
-#define BCHP_MEMC_DDR_0_DRAM_MODE_4_DDR4_RD_PREAMBLE_TRAINING_ENABLE 1
-#define BCHP_MEMC_DDR_0_DRAM_MODE_4_DDR4_RD_PREAMBLE_TRAINING_DISABLE 0
-
-/* MEMC_DDR_0 :: DRAM_MODE_4 :: DDR4 :: SELF_REFRESH_ABORT [09:09] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_4_DDR4_SELF_REFRESH_ABORT_MASK 0x00000200
-#define BCHP_MEMC_DDR_0_DRAM_MODE_4_DDR4_SELF_REFRESH_ABORT_SHIFT 9
-#define BCHP_MEMC_DDR_0_DRAM_MODE_4_DDR4_SELF_REFRESH_ABORT_DEFAULT 0x00000000
-#define BCHP_MEMC_DDR_0_DRAM_MODE_4_DDR4_SELF_REFRESH_ABORT_ENABLE 1
-#define BCHP_MEMC_DDR_0_DRAM_MODE_4_DDR4_SELF_REFRESH_ABORT_DISABLE 0
-
-/* MEMC_DDR_0 :: DRAM_MODE_4 :: DDR4 :: CMD_ADDR_LATENCY [08:06] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_4_DDR4_CMD_ADDR_LATENCY_MASK 0x000001c0
-#define BCHP_MEMC_DDR_0_DRAM_MODE_4_DDR4_CMD_ADDR_LATENCY_SHIFT 6
-#define BCHP_MEMC_DDR_0_DRAM_MODE_4_DDR4_CMD_ADDR_LATENCY_DEFAULT 0x00000000
-
-/* MEMC_DDR_0 :: DRAM_MODE_4 :: DDR4 :: CMD_ADDR_PARITY [05:05] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_4_DDR4_CMD_ADDR_PARITY_MASK 0x00000020
-#define BCHP_MEMC_DDR_0_DRAM_MODE_4_DDR4_CMD_ADDR_PARITY_SHIFT 5
-#define BCHP_MEMC_DDR_0_DRAM_MODE_4_DDR4_CMD_ADDR_PARITY_DEFAULT 0x00000000
-#define BCHP_MEMC_DDR_0_DRAM_MODE_4_DDR4_CMD_ADDR_PARITY_ENABLE 1
-#define BCHP_MEMC_DDR_0_DRAM_MODE_4_DDR4_CMD_ADDR_PARITY_DISABLE 0
-
-/* MEMC_DDR_0 :: DRAM_MODE_4 :: DDR4 :: VREF_MONITOR [04:04] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_4_DDR4_VREF_MONITOR_MASK 0x00000010
-#define BCHP_MEMC_DDR_0_DRAM_MODE_4_DDR4_VREF_MONITOR_SHIFT 4
-#define BCHP_MEMC_DDR_0_DRAM_MODE_4_DDR4_VREF_MONITOR_DEFAULT 0x00000000
-#define BCHP_MEMC_DDR_0_DRAM_MODE_4_DDR4_VREF_MONITOR_ENABLE 1
-#define BCHP_MEMC_DDR_0_DRAM_MODE_4_DDR4_VREF_MONITOR_DISABLE 0
-
-/* MEMC_DDR_0 :: DRAM_MODE_4 :: DDR4 :: TEMP_CONTROLLED_REFRESH [03:03] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_4_DDR4_TEMP_CONTROLLED_REFRESH_MASK 0x00000008
-#define BCHP_MEMC_DDR_0_DRAM_MODE_4_DDR4_TEMP_CONTROLLED_REFRESH_SHIFT 3
-#define BCHP_MEMC_DDR_0_DRAM_MODE_4_DDR4_TEMP_CONTROLLED_REFRESH_DEFAULT 0x00000000
-#define BCHP_MEMC_DDR_0_DRAM_MODE_4_DDR4_TEMP_CONTROLLED_REFRESH_ENABLE 1
-#define BCHP_MEMC_DDR_0_DRAM_MODE_4_DDR4_TEMP_CONTROLLED_REFRESH_DISABLE 0
-
-/* MEMC_DDR_0 :: DRAM_MODE_4 :: DDR4 :: TEMP_CONTROLLED_REFRESH_RANGE [02:02] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_4_DDR4_TEMP_CONTROLLED_REFRESH_RANGE_MASK 0x00000004
-#define BCHP_MEMC_DDR_0_DRAM_MODE_4_DDR4_TEMP_CONTROLLED_REFRESH_RANGE_SHIFT 2
-#define BCHP_MEMC_DDR_0_DRAM_MODE_4_DDR4_TEMP_CONTROLLED_REFRESH_RANGE_DEFAULT 0x00000000
-
-/* MEMC_DDR_0 :: DRAM_MODE_4 :: DDR4 :: MAXIMUM_POWER_SAVINGS [01:01] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_4_DDR4_MAXIMUM_POWER_SAVINGS_MASK 0x00000002
-#define BCHP_MEMC_DDR_0_DRAM_MODE_4_DDR4_MAXIMUM_POWER_SAVINGS_SHIFT 1
-#define BCHP_MEMC_DDR_0_DRAM_MODE_4_DDR4_MAXIMUM_POWER_SAVINGS_DEFAULT 0x00000000
-#define BCHP_MEMC_DDR_0_DRAM_MODE_4_DDR4_MAXIMUM_POWER_SAVINGS_ENABLE 1
-#define BCHP_MEMC_DDR_0_DRAM_MODE_4_DDR4_MAXIMUM_POWER_SAVINGS_DISABLE 0
-
-/* MEMC_DDR_0 :: DRAM_MODE_4 :: DDR4 :: unused_1 [00:00] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_4_DDR4_unused_1_MASK 0x00000001
-#define BCHP_MEMC_DDR_0_DRAM_MODE_4_DDR4_unused_1_SHIFT 0
-#define BCHP_MEMC_DDR_0_DRAM_MODE_4_DDR4_unused_1_DEFAULT 0x00000000
-
-/* union - case GDDR5M [12:00] */
-/* MEMC_DDR_0 :: DRAM_MODE_4 :: GDDR5M :: unused_1 [12:12] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_4_GDDR5M_unused_1_MASK 0x00001000
-#define BCHP_MEMC_DDR_0_DRAM_MODE_4_GDDR5M_unused_1_SHIFT 12
-#define BCHP_MEMC_DDR_0_DRAM_MODE_4_GDDR5M_unused_1_DEFAULT 0x00000000
-
-/* MEMC_DDR_0 :: DRAM_MODE_4 :: GDDR5M :: EDC_HOLD_INVERT [11:11] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_4_GDDR5M_EDC_HOLD_INVERT_MASK 0x00000800
-#define BCHP_MEMC_DDR_0_DRAM_MODE_4_GDDR5M_EDC_HOLD_INVERT_SHIFT 11
-#define BCHP_MEMC_DDR_0_DRAM_MODE_4_GDDR5M_EDC_HOLD_INVERT_DEFAULT 0x00000000
-
-/* MEMC_DDR_0 :: DRAM_MODE_4 :: GDDR5M :: WR_CRC [10:10] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_4_GDDR5M_WR_CRC_MASK 0x00000400
-#define BCHP_MEMC_DDR_0_DRAM_MODE_4_GDDR5M_WR_CRC_SHIFT 10
-#define BCHP_MEMC_DDR_0_DRAM_MODE_4_GDDR5M_WR_CRC_DEFAULT 0x00000001
-#define BCHP_MEMC_DDR_0_DRAM_MODE_4_GDDR5M_WR_CRC_ENABLE 0
-#define BCHP_MEMC_DDR_0_DRAM_MODE_4_GDDR5M_WR_CRC_DISABLE 1
-
-/* MEMC_DDR_0 :: DRAM_MODE_4 :: GDDR5M :: RD_CRC [09:09] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_4_GDDR5M_RD_CRC_MASK 0x00000200
-#define BCHP_MEMC_DDR_0_DRAM_MODE_4_GDDR5M_RD_CRC_SHIFT 9
-#define BCHP_MEMC_DDR_0_DRAM_MODE_4_GDDR5M_RD_CRC_DEFAULT 0x00000001
-#define BCHP_MEMC_DDR_0_DRAM_MODE_4_GDDR5M_RD_CRC_ENABLE 0
-#define BCHP_MEMC_DDR_0_DRAM_MODE_4_GDDR5M_RD_CRC_DISABLE 1
-
-/* MEMC_DDR_0 :: DRAM_MODE_4 :: GDDR5M :: CRC_RD_LATENCY [08:07] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_4_GDDR5M_CRC_RD_LATENCY_MASK 0x00000180
-#define BCHP_MEMC_DDR_0_DRAM_MODE_4_GDDR5M_CRC_RD_LATENCY_SHIFT 7
-#define BCHP_MEMC_DDR_0_DRAM_MODE_4_GDDR5M_CRC_RD_LATENCY_DEFAULT 0x00000000
-
-/* MEMC_DDR_0 :: DRAM_MODE_4 :: GDDR5M :: CRC_WR_LATENCY [06:04] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_4_GDDR5M_CRC_WR_LATENCY_MASK 0x00000070
-#define BCHP_MEMC_DDR_0_DRAM_MODE_4_GDDR5M_CRC_WR_LATENCY_SHIFT 4
-#define BCHP_MEMC_DDR_0_DRAM_MODE_4_GDDR5M_CRC_WR_LATENCY_DEFAULT 0x00000000
-
-/* MEMC_DDR_0 :: DRAM_MODE_4 :: GDDR5M :: EDC_HOLD_PATTERN [03:00] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_4_GDDR5M_EDC_HOLD_PATTERN_MASK 0x0000000f
-#define BCHP_MEMC_DDR_0_DRAM_MODE_4_GDDR5M_EDC_HOLD_PATTERN_SHIFT 0
-#define BCHP_MEMC_DDR_0_DRAM_MODE_4_GDDR5M_EDC_HOLD_PATTERN_DEFAULT 0x00000000
-
-/* union - case GDDR5 [12:00] */
-/* MEMC_DDR_0 :: DRAM_MODE_4 :: GDDR5 :: unused_1 [12:12] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_4_GDDR5_unused_1_MASK 0x00001000
-#define BCHP_MEMC_DDR_0_DRAM_MODE_4_GDDR5_unused_1_SHIFT 12
-#define BCHP_MEMC_DDR_0_DRAM_MODE_4_GDDR5_unused_1_DEFAULT 0x00000000
-
-/* MEMC_DDR_0 :: DRAM_MODE_4 :: GDDR5 :: EDC_HOLD_INVERT [11:11] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_4_GDDR5_EDC_HOLD_INVERT_MASK 0x00000800
-#define BCHP_MEMC_DDR_0_DRAM_MODE_4_GDDR5_EDC_HOLD_INVERT_SHIFT 11
-#define BCHP_MEMC_DDR_0_DRAM_MODE_4_GDDR5_EDC_HOLD_INVERT_DEFAULT 0x00000000
-
-/* MEMC_DDR_0 :: DRAM_MODE_4 :: GDDR5 :: WR_CRC [10:10] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_4_GDDR5_WR_CRC_MASK 0x00000400
-#define BCHP_MEMC_DDR_0_DRAM_MODE_4_GDDR5_WR_CRC_SHIFT 10
-#define BCHP_MEMC_DDR_0_DRAM_MODE_4_GDDR5_WR_CRC_DEFAULT 0x00000001
-#define BCHP_MEMC_DDR_0_DRAM_MODE_4_GDDR5_WR_CRC_ENABLE 0
-#define BCHP_MEMC_DDR_0_DRAM_MODE_4_GDDR5_WR_CRC_DISABLE 1
-
-/* MEMC_DDR_0 :: DRAM_MODE_4 :: GDDR5 :: RD_CRC [09:09] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_4_GDDR5_RD_CRC_MASK 0x00000200
-#define BCHP_MEMC_DDR_0_DRAM_MODE_4_GDDR5_RD_CRC_SHIFT 9
-#define BCHP_MEMC_DDR_0_DRAM_MODE_4_GDDR5_RD_CRC_DEFAULT 0x00000001
-#define BCHP_MEMC_DDR_0_DRAM_MODE_4_GDDR5_RD_CRC_ENABLE 0
-#define BCHP_MEMC_DDR_0_DRAM_MODE_4_GDDR5_RD_CRC_DISABLE 1
-
-/* MEMC_DDR_0 :: DRAM_MODE_4 :: GDDR5 :: CRC_RD_LATENCY [08:07] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_4_GDDR5_CRC_RD_LATENCY_MASK 0x00000180
-#define BCHP_MEMC_DDR_0_DRAM_MODE_4_GDDR5_CRC_RD_LATENCY_SHIFT 7
-#define BCHP_MEMC_DDR_0_DRAM_MODE_4_GDDR5_CRC_RD_LATENCY_DEFAULT 0x00000000
-
-/* MEMC_DDR_0 :: DRAM_MODE_4 :: GDDR5 :: CRC_WR_LATENCY [06:04] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_4_GDDR5_CRC_WR_LATENCY_MASK 0x00000070
-#define BCHP_MEMC_DDR_0_DRAM_MODE_4_GDDR5_CRC_WR_LATENCY_SHIFT 4
-#define BCHP_MEMC_DDR_0_DRAM_MODE_4_GDDR5_CRC_WR_LATENCY_DEFAULT 0x00000000
-
-/* MEMC_DDR_0 :: DRAM_MODE_4 :: GDDR5 :: EDC_HOLD_PATTERN [03:00] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_4_GDDR5_EDC_HOLD_PATTERN_MASK 0x0000000f
-#define BCHP_MEMC_DDR_0_DRAM_MODE_4_GDDR5_EDC_HOLD_PATTERN_SHIFT 0
-#define BCHP_MEMC_DDR_0_DRAM_MODE_4_GDDR5_EDC_HOLD_PATTERN_DEFAULT 0x00000000
-
-/* union - case Others [12:00] */
-/* MEMC_DDR_0 :: DRAM_MODE_4 :: Others :: unused_1 [12:00] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_4_Others_unused_1_MASK 0x00001fff
-#define BCHP_MEMC_DDR_0_DRAM_MODE_4_Others_unused_1_SHIFT 0
-#define BCHP_MEMC_DDR_0_DRAM_MODE_4_Others_unused_1_DEFAULT 0x00000000
-
-/***************************************************************************
- *DRAM_MODE_5 - Dram Mode Register 5
- ***************************************************************************/
-/* MEMC_DDR_0 :: DRAM_MODE_5 :: reserved0 [31:16] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_5_reserved0_MASK 0xffff0000
-#define BCHP_MEMC_DDR_0_DRAM_MODE_5_reserved0_SHIFT 16
-
-/* MEMC_DDR_0 :: DRAM_MODE_5 :: unused_0 [15:13] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_5_unused_0_MASK 0x0000e000
-#define BCHP_MEMC_DDR_0_DRAM_MODE_5_unused_0_SHIFT 13
-#define BCHP_MEMC_DDR_0_DRAM_MODE_5_unused_0_DEFAULT 0x00000000
-
-/* union - case DDR4 [12:00] */
-/* MEMC_DDR_0 :: DRAM_MODE_5 :: DDR4 :: RD_DBI [12:12] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_5_DDR4_RD_DBI_MASK 0x00001000
-#define BCHP_MEMC_DDR_0_DRAM_MODE_5_DDR4_RD_DBI_SHIFT 12
-#define BCHP_MEMC_DDR_0_DRAM_MODE_5_DDR4_RD_DBI_DEFAULT 0x00000000
-#define BCHP_MEMC_DDR_0_DRAM_MODE_5_DDR4_RD_DBI_ENABLE 1
-#define BCHP_MEMC_DDR_0_DRAM_MODE_5_DDR4_RD_DBI_DISABLE 0
-
-/* MEMC_DDR_0 :: DRAM_MODE_5 :: DDR4 :: WR_DBI [11:11] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_5_DDR4_WR_DBI_MASK 0x00000800
-#define BCHP_MEMC_DDR_0_DRAM_MODE_5_DDR4_WR_DBI_SHIFT 11
-#define BCHP_MEMC_DDR_0_DRAM_MODE_5_DDR4_WR_DBI_DEFAULT 0x00000000
-#define BCHP_MEMC_DDR_0_DRAM_MODE_5_DDR4_WR_DBI_ENABLE 1
-#define BCHP_MEMC_DDR_0_DRAM_MODE_5_DDR4_WR_DBI_DISABLE 0
-
-/* MEMC_DDR_0 :: DRAM_MODE_5 :: DDR4 :: DM [10:10] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_5_DDR4_DM_MASK 0x00000400
-#define BCHP_MEMC_DDR_0_DRAM_MODE_5_DDR4_DM_SHIFT 10
-#define BCHP_MEMC_DDR_0_DRAM_MODE_5_DDR4_DM_DEFAULT 0x00000000
-#define BCHP_MEMC_DDR_0_DRAM_MODE_5_DDR4_DM_ENABLE 1
-#define BCHP_MEMC_DDR_0_DRAM_MODE_5_DDR4_DM_DISABLE 0
-
-/* MEMC_DDR_0 :: DRAM_MODE_5 :: DDR4 :: unused_1 [09:09] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_5_DDR4_unused_1_MASK 0x00000200
-#define BCHP_MEMC_DDR_0_DRAM_MODE_5_DDR4_unused_1_SHIFT 9
-#define BCHP_MEMC_DDR_0_DRAM_MODE_5_DDR4_unused_1_DEFAULT 0x00000000
-
-/* MEMC_DDR_0 :: DRAM_MODE_5 :: DDR4 :: RTT_PARK [08:06] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_5_DDR4_RTT_PARK_MASK 0x000001c0
-#define BCHP_MEMC_DDR_0_DRAM_MODE_5_DDR4_RTT_PARK_SHIFT 6
-#define BCHP_MEMC_DDR_0_DRAM_MODE_5_DDR4_RTT_PARK_DEFAULT 0x00000000
-
-/* MEMC_DDR_0 :: DRAM_MODE_5 :: DDR4 :: unused_2 [05:05] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_5_DDR4_unused_2_MASK 0x00000020
-#define BCHP_MEMC_DDR_0_DRAM_MODE_5_DDR4_unused_2_SHIFT 5
-#define BCHP_MEMC_DDR_0_DRAM_MODE_5_DDR4_unused_2_DEFAULT 0x00000000
-
-/* MEMC_DDR_0 :: DRAM_MODE_5 :: DDR4 :: CMD_ADDR_PARITY_ERROR [04:04] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_5_DDR4_CMD_ADDR_PARITY_ERROR_MASK 0x00000010
-#define BCHP_MEMC_DDR_0_DRAM_MODE_5_DDR4_CMD_ADDR_PARITY_ERROR_SHIFT 4
-#define BCHP_MEMC_DDR_0_DRAM_MODE_5_DDR4_CMD_ADDR_PARITY_ERROR_DEFAULT 0x00000000
-
-/* MEMC_DDR_0 :: DRAM_MODE_5 :: DDR4 :: CRC_ERROR [03:03] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_5_DDR4_CRC_ERROR_MASK 0x00000008
-#define BCHP_MEMC_DDR_0_DRAM_MODE_5_DDR4_CRC_ERROR_SHIFT 3
-#define BCHP_MEMC_DDR_0_DRAM_MODE_5_DDR4_CRC_ERROR_DEFAULT 0x00000000
-
-/* MEMC_DDR_0 :: DRAM_MODE_5 :: DDR4 :: CMD_ADDR_PARITY_LATENCY [02:00] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_5_DDR4_CMD_ADDR_PARITY_LATENCY_MASK 0x00000007
-#define BCHP_MEMC_DDR_0_DRAM_MODE_5_DDR4_CMD_ADDR_PARITY_LATENCY_SHIFT 0
-#define BCHP_MEMC_DDR_0_DRAM_MODE_5_DDR4_CMD_ADDR_PARITY_LATENCY_DEFAULT 0x00000000
-
-/* union - case GDDR5M [12:00] */
-/* MEMC_DDR_0 :: DRAM_MODE_5 :: GDDR5M :: unused_1 [12:12] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_5_GDDR5M_unused_1_MASK 0x00001000
-#define BCHP_MEMC_DDR_0_DRAM_MODE_5_GDDR5M_unused_1_SHIFT 12
-#define BCHP_MEMC_DDR_0_DRAM_MODE_5_GDDR5M_unused_1_DEFAULT 0x00000000
-
-/* MEMC_DDR_0 :: DRAM_MODE_5 :: GDDR5M :: RAS [11:06] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_5_GDDR5M_RAS_MASK 0x00000fc0
-#define BCHP_MEMC_DDR_0_DRAM_MODE_5_GDDR5M_RAS_SHIFT 6
-#define BCHP_MEMC_DDR_0_DRAM_MODE_5_GDDR5M_RAS_DEFAULT 0x00000000
-
-/* MEMC_DDR_0 :: DRAM_MODE_5 :: GDDR5M :: unused_2 [05:03] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_5_GDDR5M_unused_2_MASK 0x00000038
-#define BCHP_MEMC_DDR_0_DRAM_MODE_5_GDDR5M_unused_2_SHIFT 3
-#define BCHP_MEMC_DDR_0_DRAM_MODE_5_GDDR5M_unused_2_DEFAULT 0x00000000
-
-/* MEMC_DDR_0 :: DRAM_MODE_5 :: GDDR5M :: LP3 [02:02] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_5_GDDR5M_LP3_MASK 0x00000004
-#define BCHP_MEMC_DDR_0_DRAM_MODE_5_GDDR5M_LP3_SHIFT 2
-#define BCHP_MEMC_DDR_0_DRAM_MODE_5_GDDR5M_LP3_DEFAULT 0x00000000
-#define BCHP_MEMC_DDR_0_DRAM_MODE_5_GDDR5M_LP3_ENABLE 1
-#define BCHP_MEMC_DDR_0_DRAM_MODE_5_GDDR5M_LP3_DISABLE 0
-
-/* MEMC_DDR_0 :: DRAM_MODE_5 :: GDDR5M :: LP2 [01:01] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_5_GDDR5M_LP2_MASK 0x00000002
-#define BCHP_MEMC_DDR_0_DRAM_MODE_5_GDDR5M_LP2_SHIFT 1
-#define BCHP_MEMC_DDR_0_DRAM_MODE_5_GDDR5M_LP2_DEFAULT 0x00000000
-#define BCHP_MEMC_DDR_0_DRAM_MODE_5_GDDR5M_LP2_ENABLE 1
-#define BCHP_MEMC_DDR_0_DRAM_MODE_5_GDDR5M_LP2_DISABLE 0
-
-/* MEMC_DDR_0 :: DRAM_MODE_5 :: GDDR5M :: LP1 [00:00] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_5_GDDR5M_LP1_MASK 0x00000001
-#define BCHP_MEMC_DDR_0_DRAM_MODE_5_GDDR5M_LP1_SHIFT 0
-#define BCHP_MEMC_DDR_0_DRAM_MODE_5_GDDR5M_LP1_DEFAULT 0x00000000
-#define BCHP_MEMC_DDR_0_DRAM_MODE_5_GDDR5M_LP1_ENABLE 1
-#define BCHP_MEMC_DDR_0_DRAM_MODE_5_GDDR5M_LP1_DISABLE 0
-
-/* union - case GDDR5 [12:00] */
-/* MEMC_DDR_0 :: DRAM_MODE_5 :: GDDR5 :: unused_1 [12:12] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_5_GDDR5_unused_1_MASK 0x00001000
-#define BCHP_MEMC_DDR_0_DRAM_MODE_5_GDDR5_unused_1_SHIFT 12
-#define BCHP_MEMC_DDR_0_DRAM_MODE_5_GDDR5_unused_1_DEFAULT 0x00000000
-
-/* MEMC_DDR_0 :: DRAM_MODE_5 :: GDDR5 :: RAS [11:06] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_5_GDDR5_RAS_MASK 0x00000fc0
-#define BCHP_MEMC_DDR_0_DRAM_MODE_5_GDDR5_RAS_SHIFT 6
-#define BCHP_MEMC_DDR_0_DRAM_MODE_5_GDDR5_RAS_DEFAULT 0x00000000
-
-/* MEMC_DDR_0 :: DRAM_MODE_5 :: GDDR5 :: PLL_DLL_BANDWIDTH [05:03] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_5_GDDR5_PLL_DLL_BANDWIDTH_MASK 0x00000038
-#define BCHP_MEMC_DDR_0_DRAM_MODE_5_GDDR5_PLL_DLL_BANDWIDTH_SHIFT 3
-#define BCHP_MEMC_DDR_0_DRAM_MODE_5_GDDR5_PLL_DLL_BANDWIDTH_DEFAULT 0x00000000
-
-/* MEMC_DDR_0 :: DRAM_MODE_5 :: GDDR5 :: LP3 [02:02] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_5_GDDR5_LP3_MASK 0x00000004
-#define BCHP_MEMC_DDR_0_DRAM_MODE_5_GDDR5_LP3_SHIFT 2
-#define BCHP_MEMC_DDR_0_DRAM_MODE_5_GDDR5_LP3_DEFAULT 0x00000000
-#define BCHP_MEMC_DDR_0_DRAM_MODE_5_GDDR5_LP3_ENABLE 1
-#define BCHP_MEMC_DDR_0_DRAM_MODE_5_GDDR5_LP3_DISABLE 0
-
-/* MEMC_DDR_0 :: DRAM_MODE_5 :: GDDR5 :: LP2 [01:01] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_5_GDDR5_LP2_MASK 0x00000002
-#define BCHP_MEMC_DDR_0_DRAM_MODE_5_GDDR5_LP2_SHIFT 1
-#define BCHP_MEMC_DDR_0_DRAM_MODE_5_GDDR5_LP2_DEFAULT 0x00000000
-#define BCHP_MEMC_DDR_0_DRAM_MODE_5_GDDR5_LP2_ENABLE 1
-#define BCHP_MEMC_DDR_0_DRAM_MODE_5_GDDR5_LP2_DISABLE 0
-
-/* MEMC_DDR_0 :: DRAM_MODE_5 :: GDDR5 :: LP1 [00:00] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_5_GDDR5_LP1_MASK 0x00000001
-#define BCHP_MEMC_DDR_0_DRAM_MODE_5_GDDR5_LP1_SHIFT 0
-#define BCHP_MEMC_DDR_0_DRAM_MODE_5_GDDR5_LP1_DEFAULT 0x00000000
-#define BCHP_MEMC_DDR_0_DRAM_MODE_5_GDDR5_LP1_ENABLE 1
-#define BCHP_MEMC_DDR_0_DRAM_MODE_5_GDDR5_LP1_DISABLE 0
-
-/* union - case Others [12:00] */
-/* MEMC_DDR_0 :: DRAM_MODE_5 :: Others :: unused_1 [12:00] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_5_Others_unused_1_MASK 0x00001fff
-#define BCHP_MEMC_DDR_0_DRAM_MODE_5_Others_unused_1_SHIFT 0
-#define BCHP_MEMC_DDR_0_DRAM_MODE_5_Others_unused_1_DEFAULT 0x00000000
-
-/***************************************************************************
- *DRAM_MODE_6 - Dram Mode Register 6
- ***************************************************************************/
-/* MEMC_DDR_0 :: DRAM_MODE_6 :: reserved0 [31:16] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_6_reserved0_MASK 0xffff0000
-#define BCHP_MEMC_DDR_0_DRAM_MODE_6_reserved0_SHIFT 16
-
-/* MEMC_DDR_0 :: DRAM_MODE_6 :: unused_0 [15:13] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_6_unused_0_MASK 0x0000e000
-#define BCHP_MEMC_DDR_0_DRAM_MODE_6_unused_0_SHIFT 13
-#define BCHP_MEMC_DDR_0_DRAM_MODE_6_unused_0_DEFAULT 0x00000000
-
-/* union - case DDR4 [12:00] */
-/* MEMC_DDR_0 :: DRAM_MODE_6 :: DDR4 :: unused_1 [12:07] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_6_DDR4_unused_1_MASK 0x00001f80
-#define BCHP_MEMC_DDR_0_DRAM_MODE_6_DDR4_unused_1_SHIFT 7
-#define BCHP_MEMC_DDR_0_DRAM_MODE_6_DDR4_unused_1_DEFAULT 0x00000000
-
-/* MEMC_DDR_0 :: DRAM_MODE_6 :: DDR4 :: VREF_TRAINING_RANGE [06:06] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_6_DDR4_VREF_TRAINING_RANGE_MASK 0x00000040
-#define BCHP_MEMC_DDR_0_DRAM_MODE_6_DDR4_VREF_TRAINING_RANGE_SHIFT 6
-#define BCHP_MEMC_DDR_0_DRAM_MODE_6_DDR4_VREF_TRAINING_RANGE_DEFAULT 0x00000000
-
-/* MEMC_DDR_0 :: DRAM_MODE_6 :: DDR4 :: VREF_TRAINING [05:00] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_6_DDR4_VREF_TRAINING_MASK 0x0000003f
-#define BCHP_MEMC_DDR_0_DRAM_MODE_6_DDR4_VREF_TRAINING_SHIFT 0
-#define BCHP_MEMC_DDR_0_DRAM_MODE_6_DDR4_VREF_TRAINING_DEFAULT 0x00000000
-
-/* union - case GDDR5M [12:00] */
-/* MEMC_DDR_0 :: DRAM_MODE_6 :: GDDR5M :: unused_1 [12:12] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_6_GDDR5M_unused_1_MASK 0x00001000
-#define BCHP_MEMC_DDR_0_DRAM_MODE_6_GDDR5M_unused_1_SHIFT 12
-#define BCHP_MEMC_DDR_0_DRAM_MODE_6_GDDR5M_unused_1_DEFAULT 0x00000000
-
-/* MEMC_DDR_0 :: DRAM_MODE_6 :: GDDR5M :: VREFD_OFFSET_01 [11:08] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_6_GDDR5M_VREFD_OFFSET_01_MASK 0x00000f00
-#define BCHP_MEMC_DDR_0_DRAM_MODE_6_GDDR5M_VREFD_OFFSET_01_SHIFT 8
-#define BCHP_MEMC_DDR_0_DRAM_MODE_6_GDDR5M_VREFD_OFFSET_01_DEFAULT 0x00000000
-
-/* MEMC_DDR_0 :: DRAM_MODE_6 :: GDDR5M :: VREFD_OFFSET_23 [07:04] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_6_GDDR5M_VREFD_OFFSET_23_MASK 0x000000f0
-#define BCHP_MEMC_DDR_0_DRAM_MODE_6_GDDR5M_VREFD_OFFSET_23_SHIFT 4
-#define BCHP_MEMC_DDR_0_DRAM_MODE_6_GDDR5M_VREFD_OFFSET_23_DEFAULT 0x00000000
-
-/* MEMC_DDR_0 :: DRAM_MODE_6 :: GDDR5M :: unused_2 [03:01] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_6_GDDR5M_unused_2_MASK 0x0000000e
-#define BCHP_MEMC_DDR_0_DRAM_MODE_6_GDDR5M_unused_2_SHIFT 1
-#define BCHP_MEMC_DDR_0_DRAM_MODE_6_GDDR5M_unused_2_DEFAULT 0x00000000
-
-/* MEMC_DDR_0 :: DRAM_MODE_6 :: GDDR5M :: WCK2CK_ALIGN [00:00] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_6_GDDR5M_WCK2CK_ALIGN_MASK 0x00000001
-#define BCHP_MEMC_DDR_0_DRAM_MODE_6_GDDR5M_WCK2CK_ALIGN_SHIFT 0
-#define BCHP_MEMC_DDR_0_DRAM_MODE_6_GDDR5M_WCK2CK_ALIGN_DEFAULT 0x00000000
-
-/* union - case GDDR5 [12:00] */
-/* MEMC_DDR_0 :: DRAM_MODE_6 :: GDDR5 :: unused_1 [12:12] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_6_GDDR5_unused_1_MASK 0x00001000
-#define BCHP_MEMC_DDR_0_DRAM_MODE_6_GDDR5_unused_1_SHIFT 12
-#define BCHP_MEMC_DDR_0_DRAM_MODE_6_GDDR5_unused_1_DEFAULT 0x00000000
-
-/* MEMC_DDR_0 :: DRAM_MODE_6 :: GDDR5 :: VREFD_OFFSET_01 [11:08] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_6_GDDR5_VREFD_OFFSET_01_MASK 0x00000f00
-#define BCHP_MEMC_DDR_0_DRAM_MODE_6_GDDR5_VREFD_OFFSET_01_SHIFT 8
-#define BCHP_MEMC_DDR_0_DRAM_MODE_6_GDDR5_VREFD_OFFSET_01_DEFAULT 0x00000000
-
-/* MEMC_DDR_0 :: DRAM_MODE_6 :: GDDR5 :: VREFD_OFFSET_23 [07:04] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_6_GDDR5_VREFD_OFFSET_23_MASK 0x000000f0
-#define BCHP_MEMC_DDR_0_DRAM_MODE_6_GDDR5_VREFD_OFFSET_23_SHIFT 4
-#define BCHP_MEMC_DDR_0_DRAM_MODE_6_GDDR5_VREFD_OFFSET_23_DEFAULT 0x00000000
-
-/* MEMC_DDR_0 :: DRAM_MODE_6 :: GDDR5 :: VREFD [03:03] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_6_GDDR5_VREFD_MASK 0x00000008
-#define BCHP_MEMC_DDR_0_DRAM_MODE_6_GDDR5_VREFD_SHIFT 3
-#define BCHP_MEMC_DDR_0_DRAM_MODE_6_GDDR5_VREFD_DEFAULT 0x00000000
-
-/* MEMC_DDR_0 :: DRAM_MODE_6 :: GDDR5 :: AUTO_VREFD [02:02] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_6_GDDR5_AUTO_VREFD_MASK 0x00000004
-#define BCHP_MEMC_DDR_0_DRAM_MODE_6_GDDR5_AUTO_VREFD_SHIFT 2
-#define BCHP_MEMC_DDR_0_DRAM_MODE_6_GDDR5_AUTO_VREFD_DEFAULT 0x00000000
-
-/* MEMC_DDR_0 :: DRAM_MODE_6 :: GDDR5 :: VREFD_MERGE [01:01] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_6_GDDR5_VREFD_MERGE_MASK 0x00000002
-#define BCHP_MEMC_DDR_0_DRAM_MODE_6_GDDR5_VREFD_MERGE_SHIFT 1
-#define BCHP_MEMC_DDR_0_DRAM_MODE_6_GDDR5_VREFD_MERGE_DEFAULT 0x00000000
-
-/* MEMC_DDR_0 :: DRAM_MODE_6 :: GDDR5 :: WCK2CK_ALIGN [00:00] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_6_GDDR5_WCK2CK_ALIGN_MASK 0x00000001
-#define BCHP_MEMC_DDR_0_DRAM_MODE_6_GDDR5_WCK2CK_ALIGN_SHIFT 0
-#define BCHP_MEMC_DDR_0_DRAM_MODE_6_GDDR5_WCK2CK_ALIGN_DEFAULT 0x00000000
-
-/* union - case Others [12:00] */
-/* MEMC_DDR_0 :: DRAM_MODE_6 :: Others :: unused_1 [12:00] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_6_Others_unused_1_MASK 0x00001fff
-#define BCHP_MEMC_DDR_0_DRAM_MODE_6_Others_unused_1_SHIFT 0
-#define BCHP_MEMC_DDR_0_DRAM_MODE_6_Others_unused_1_DEFAULT 0x00000000
-
-/***************************************************************************
- *DRAM_MODE_7 - Dram Mode Register 7
- ***************************************************************************/
-/* MEMC_DDR_0 :: DRAM_MODE_7 :: reserved0 [31:16] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_7_reserved0_MASK 0xffff0000
-#define BCHP_MEMC_DDR_0_DRAM_MODE_7_reserved0_SHIFT 16
-
-/* MEMC_DDR_0 :: DRAM_MODE_7 :: unused_0 [15:13] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_7_unused_0_MASK 0x0000e000
-#define BCHP_MEMC_DDR_0_DRAM_MODE_7_unused_0_SHIFT 13
-#define BCHP_MEMC_DDR_0_DRAM_MODE_7_unused_0_DEFAULT 0x00000000
-
-/* union - case GDDR5M [12:00] */
-/* MEMC_DDR_0 :: DRAM_MODE_7 :: GDDR5M :: unused_1 [12:12] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_7_GDDR5M_unused_1_MASK 0x00001000
-#define BCHP_MEMC_DDR_0_DRAM_MODE_7_GDDR5M_unused_1_SHIFT 12
-#define BCHP_MEMC_DDR_0_DRAM_MODE_7_GDDR5M_unused_1_DEFAULT 0x00000000
-
-/* MEMC_DDR_0 :: DRAM_MODE_7 :: GDDR5M :: DDC [11:10] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_7_GDDR5M_DDC_MASK 0x00000c00
-#define BCHP_MEMC_DDR_0_DRAM_MODE_7_GDDR5M_DDC_SHIFT 10
-#define BCHP_MEMC_DDR_0_DRAM_MODE_7_GDDR5M_DDC_DEFAULT 0x00000000
-
-/* MEMC_DDR_0 :: DRAM_MODE_7 :: GDDR5M :: VDD_RANGE [09:08] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_7_GDDR5M_VDD_RANGE_MASK 0x00000300
-#define BCHP_MEMC_DDR_0_DRAM_MODE_7_GDDR5M_VDD_RANGE_SHIFT 8
-#define BCHP_MEMC_DDR_0_DRAM_MODE_7_GDDR5M_VDD_RANGE_DEFAULT 0x00000000
-
-/* MEMC_DDR_0 :: DRAM_MODE_7 :: GDDR5M :: HALF_VREFD [07:07] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_7_GDDR5M_HALF_VREFD_MASK 0x00000080
-#define BCHP_MEMC_DDR_0_DRAM_MODE_7_GDDR5M_HALF_VREFD_SHIFT 7
-#define BCHP_MEMC_DDR_0_DRAM_MODE_7_GDDR5M_HALF_VREFD_DEFAULT 0x00000000
-
-/* MEMC_DDR_0 :: DRAM_MODE_7 :: GDDR5M :: TEMP_SENSE [06:06] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_7_GDDR5M_TEMP_SENSE_MASK 0x00000040
-#define BCHP_MEMC_DDR_0_DRAM_MODE_7_GDDR5M_TEMP_SENSE_SHIFT 6
-#define BCHP_MEMC_DDR_0_DRAM_MODE_7_GDDR5M_TEMP_SENSE_DEFAULT 0x00000000
-#define BCHP_MEMC_DDR_0_DRAM_MODE_7_GDDR5M_TEMP_SENSE_ENABLE 1
-#define BCHP_MEMC_DDR_0_DRAM_MODE_7_GDDR5M_TEMP_SENSE_DISABLE 0
-
-/* MEMC_DDR_0 :: DRAM_MODE_7 :: GDDR5M :: DQ_PREAMBLE [05:05] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_7_GDDR5M_DQ_PREAMBLE_MASK 0x00000020
-#define BCHP_MEMC_DDR_0_DRAM_MODE_7_GDDR5M_DQ_PREAMBLE_SHIFT 5
-#define BCHP_MEMC_DDR_0_DRAM_MODE_7_GDDR5M_DQ_PREAMBLE_DEFAULT 0x00000000
-#define BCHP_MEMC_DDR_0_DRAM_MODE_7_GDDR5M_DQ_PREAMBLE_ENABLE 1
-#define BCHP_MEMC_DDR_0_DRAM_MODE_7_GDDR5M_DQ_PREAMBLE_DISABLE 0
-
-/* MEMC_DDR_0 :: DRAM_MODE_7 :: GDDR5M :: WCK2CK_AUTO_SYNC [04:04] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_7_GDDR5M_WCK2CK_AUTO_SYNC_MASK 0x00000010
-#define BCHP_MEMC_DDR_0_DRAM_MODE_7_GDDR5M_WCK2CK_AUTO_SYNC_SHIFT 4
-#define BCHP_MEMC_DDR_0_DRAM_MODE_7_GDDR5M_WCK2CK_AUTO_SYNC_DEFAULT 0x00000000
-#define BCHP_MEMC_DDR_0_DRAM_MODE_7_GDDR5M_WCK2CK_AUTO_SYNC_ENABLE 1
-#define BCHP_MEMC_DDR_0_DRAM_MODE_7_GDDR5M_WCK2CK_AUTO_SYNC_DISABLE 0
-
-/* MEMC_DDR_0 :: DRAM_MODE_7 :: GDDR5M :: LOW_FREQ [03:03] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_7_GDDR5M_LOW_FREQ_MASK 0x00000008
-#define BCHP_MEMC_DDR_0_DRAM_MODE_7_GDDR5M_LOW_FREQ_SHIFT 3
-#define BCHP_MEMC_DDR_0_DRAM_MODE_7_GDDR5M_LOW_FREQ_DEFAULT 0x00000000
-#define BCHP_MEMC_DDR_0_DRAM_MODE_7_GDDR5M_LOW_FREQ_ENABLE 1
-#define BCHP_MEMC_DDR_0_DRAM_MODE_7_GDDR5M_LOW_FREQ_DISABLE 0
-
-/* MEMC_DDR_0 :: DRAM_MODE_7 :: GDDR5M :: unused_2 [02:00] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_7_GDDR5M_unused_2_MASK 0x00000007
-#define BCHP_MEMC_DDR_0_DRAM_MODE_7_GDDR5M_unused_2_SHIFT 0
-#define BCHP_MEMC_DDR_0_DRAM_MODE_7_GDDR5M_unused_2_DEFAULT 0x00000000
-
-/* union - case GDDR5 [12:00] */
-/* MEMC_DDR_0 :: DRAM_MODE_7 :: GDDR5 :: unused_1 [12:12] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_7_GDDR5_unused_1_MASK 0x00001000
-#define BCHP_MEMC_DDR_0_DRAM_MODE_7_GDDR5_unused_1_SHIFT 12
-#define BCHP_MEMC_DDR_0_DRAM_MODE_7_GDDR5_unused_1_DEFAULT 0x00000000
-
-/* MEMC_DDR_0 :: DRAM_MODE_7 :: GDDR5 :: DDC [11:10] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_7_GDDR5_DDC_MASK 0x00000c00
-#define BCHP_MEMC_DDR_0_DRAM_MODE_7_GDDR5_DDC_SHIFT 10
-#define BCHP_MEMC_DDR_0_DRAM_MODE_7_GDDR5_DDC_DEFAULT 0x00000000
-
-/* MEMC_DDR_0 :: DRAM_MODE_7 :: GDDR5 :: VDD_RANGE [09:08] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_7_GDDR5_VDD_RANGE_MASK 0x00000300
-#define BCHP_MEMC_DDR_0_DRAM_MODE_7_GDDR5_VDD_RANGE_SHIFT 8
-#define BCHP_MEMC_DDR_0_DRAM_MODE_7_GDDR5_VDD_RANGE_DEFAULT 0x00000000
-
-/* MEMC_DDR_0 :: DRAM_MODE_7 :: GDDR5 :: HALF_VREFD [07:07] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_7_GDDR5_HALF_VREFD_MASK 0x00000080
-#define BCHP_MEMC_DDR_0_DRAM_MODE_7_GDDR5_HALF_VREFD_SHIFT 7
-#define BCHP_MEMC_DDR_0_DRAM_MODE_7_GDDR5_HALF_VREFD_DEFAULT 0x00000000
-
-/* MEMC_DDR_0 :: DRAM_MODE_7 :: GDDR5 :: TEMP_SENSE [06:06] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_7_GDDR5_TEMP_SENSE_MASK 0x00000040
-#define BCHP_MEMC_DDR_0_DRAM_MODE_7_GDDR5_TEMP_SENSE_SHIFT 6
-#define BCHP_MEMC_DDR_0_DRAM_MODE_7_GDDR5_TEMP_SENSE_DEFAULT 0x00000000
-#define BCHP_MEMC_DDR_0_DRAM_MODE_7_GDDR5_TEMP_SENSE_ENABLE 1
-#define BCHP_MEMC_DDR_0_DRAM_MODE_7_GDDR5_TEMP_SENSE_DISABLE 0
-
-/* MEMC_DDR_0 :: DRAM_MODE_7 :: GDDR5 :: DQ_PREAMBLE [05:05] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_7_GDDR5_DQ_PREAMBLE_MASK 0x00000020
-#define BCHP_MEMC_DDR_0_DRAM_MODE_7_GDDR5_DQ_PREAMBLE_SHIFT 5
-#define BCHP_MEMC_DDR_0_DRAM_MODE_7_GDDR5_DQ_PREAMBLE_DEFAULT 0x00000000
-#define BCHP_MEMC_DDR_0_DRAM_MODE_7_GDDR5_DQ_PREAMBLE_ENABLE 1
-#define BCHP_MEMC_DDR_0_DRAM_MODE_7_GDDR5_DQ_PREAMBLE_DISABLE 0
-
-/* MEMC_DDR_0 :: DRAM_MODE_7 :: GDDR5 :: WCK2CK_AUTO_SYNC [04:04] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_7_GDDR5_WCK2CK_AUTO_SYNC_MASK 0x00000010
-#define BCHP_MEMC_DDR_0_DRAM_MODE_7_GDDR5_WCK2CK_AUTO_SYNC_SHIFT 4
-#define BCHP_MEMC_DDR_0_DRAM_MODE_7_GDDR5_WCK2CK_AUTO_SYNC_DEFAULT 0x00000000
-#define BCHP_MEMC_DDR_0_DRAM_MODE_7_GDDR5_WCK2CK_AUTO_SYNC_ENABLE 1
-#define BCHP_MEMC_DDR_0_DRAM_MODE_7_GDDR5_WCK2CK_AUTO_SYNC_DISABLE 0
-
-/* MEMC_DDR_0 :: DRAM_MODE_7 :: GDDR5 :: LOW_FREQ [03:03] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_7_GDDR5_LOW_FREQ_MASK 0x00000008
-#define BCHP_MEMC_DDR_0_DRAM_MODE_7_GDDR5_LOW_FREQ_SHIFT 3
-#define BCHP_MEMC_DDR_0_DRAM_MODE_7_GDDR5_LOW_FREQ_DEFAULT 0x00000000
-#define BCHP_MEMC_DDR_0_DRAM_MODE_7_GDDR5_LOW_FREQ_ENABLE 1
-#define BCHP_MEMC_DDR_0_DRAM_MODE_7_GDDR5_LOW_FREQ_DISABLE 0
-
-/* MEMC_DDR_0 :: DRAM_MODE_7 :: GDDR5 :: PLL_DELAY_COMP [02:02] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_7_GDDR5_PLL_DELAY_COMP_MASK 0x00000004
-#define BCHP_MEMC_DDR_0_DRAM_MODE_7_GDDR5_PLL_DELAY_COMP_SHIFT 2
-#define BCHP_MEMC_DDR_0_DRAM_MODE_7_GDDR5_PLL_DELAY_COMP_DEFAULT 0x00000000
-#define BCHP_MEMC_DDR_0_DRAM_MODE_7_GDDR5_PLL_DELAY_COMP_ENABLE 1
-#define BCHP_MEMC_DDR_0_DRAM_MODE_7_GDDR5_PLL_DELAY_COMP_DISABLE 0
-
-/* MEMC_DDR_0 :: DRAM_MODE_7 :: GDDR5 :: PLL_FAST_LOCK [01:01] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_7_GDDR5_PLL_FAST_LOCK_MASK 0x00000002
-#define BCHP_MEMC_DDR_0_DRAM_MODE_7_GDDR5_PLL_FAST_LOCK_SHIFT 1
-#define BCHP_MEMC_DDR_0_DRAM_MODE_7_GDDR5_PLL_FAST_LOCK_DEFAULT 0x00000000
-#define BCHP_MEMC_DDR_0_DRAM_MODE_7_GDDR5_PLL_FAST_LOCK_ENABLE 1
-#define BCHP_MEMC_DDR_0_DRAM_MODE_7_GDDR5_PLL_FAST_LOCK_DISABLE 0
-
-/* MEMC_DDR_0 :: DRAM_MODE_7 :: GDDR5 :: PLL_STANDBY [00:00] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_7_GDDR5_PLL_STANDBY_MASK 0x00000001
-#define BCHP_MEMC_DDR_0_DRAM_MODE_7_GDDR5_PLL_STANDBY_SHIFT 0
-#define BCHP_MEMC_DDR_0_DRAM_MODE_7_GDDR5_PLL_STANDBY_DEFAULT 0x00000000
-#define BCHP_MEMC_DDR_0_DRAM_MODE_7_GDDR5_PLL_STANDBY_ENABLE 1
-#define BCHP_MEMC_DDR_0_DRAM_MODE_7_GDDR5_PLL_STANDBY_DISABLE 0
-
-/* union - case Others [12:00] */
-/* MEMC_DDR_0 :: DRAM_MODE_7 :: Others :: unused_1 [12:00] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_7_Others_unused_1_MASK 0x00001fff
-#define BCHP_MEMC_DDR_0_DRAM_MODE_7_Others_unused_1_SHIFT 0
-#define BCHP_MEMC_DDR_0_DRAM_MODE_7_Others_unused_1_DEFAULT 0x00000000
-
-/***************************************************************************
- *DRAM_MODE_8 - Dram Mode Register 8
- ***************************************************************************/
-/* MEMC_DDR_0 :: DRAM_MODE_8 :: reserved0 [31:16] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_8_reserved0_MASK 0xffff0000
-#define BCHP_MEMC_DDR_0_DRAM_MODE_8_reserved0_SHIFT 16
-
-/* MEMC_DDR_0 :: DRAM_MODE_8 :: unused_0 [15:13] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_8_unused_0_MASK 0x0000e000
-#define BCHP_MEMC_DDR_0_DRAM_MODE_8_unused_0_SHIFT 13
-#define BCHP_MEMC_DDR_0_DRAM_MODE_8_unused_0_DEFAULT 0x00000000
-
-/* union - case GDDR5 [12:00] */
-/* MEMC_DDR_0 :: DRAM_MODE_8 :: GDDR5 :: unused_1 [12:02] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_8_GDDR5_unused_1_MASK 0x00001ffc
-#define BCHP_MEMC_DDR_0_DRAM_MODE_8_GDDR5_unused_1_SHIFT 2
-#define BCHP_MEMC_DDR_0_DRAM_MODE_8_GDDR5_unused_1_DEFAULT 0x00000000
-
-/* MEMC_DDR_0 :: DRAM_MODE_8 :: GDDR5 :: WR_EHF [01:01] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_8_GDDR5_WR_EHF_MASK 0x00000002
-#define BCHP_MEMC_DDR_0_DRAM_MODE_8_GDDR5_WR_EHF_SHIFT 1
-#define BCHP_MEMC_DDR_0_DRAM_MODE_8_GDDR5_WR_EHF_DEFAULT 0x00000000
-
-/* MEMC_DDR_0 :: DRAM_MODE_8 :: GDDR5 :: CL_EHF [00:00] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_8_GDDR5_CL_EHF_MASK 0x00000001
-#define BCHP_MEMC_DDR_0_DRAM_MODE_8_GDDR5_CL_EHF_SHIFT 0
-#define BCHP_MEMC_DDR_0_DRAM_MODE_8_GDDR5_CL_EHF_DEFAULT 0x00000000
-
-/* union - case Others [12:00] */
-/* MEMC_DDR_0 :: DRAM_MODE_8 :: Others :: unused_1 [12:00] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_8_Others_unused_1_MASK 0x00001fff
-#define BCHP_MEMC_DDR_0_DRAM_MODE_8_Others_unused_1_SHIFT 0
-#define BCHP_MEMC_DDR_0_DRAM_MODE_8_Others_unused_1_DEFAULT 0x00000000
-
-/***************************************************************************
- *DRAM_MODE_15 - Dram Mode Register 15
- ***************************************************************************/
-/* MEMC_DDR_0 :: DRAM_MODE_15 :: reserved0 [31:16] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_15_reserved0_MASK 0xffff0000
-#define BCHP_MEMC_DDR_0_DRAM_MODE_15_reserved0_SHIFT 16
-
-/* MEMC_DDR_0 :: DRAM_MODE_15 :: unused_0 [15:13] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_15_unused_0_MASK 0x0000e000
-#define BCHP_MEMC_DDR_0_DRAM_MODE_15_unused_0_SHIFT 13
-#define BCHP_MEMC_DDR_0_DRAM_MODE_15_unused_0_DEFAULT 0x00000000
-
-/* union - case GDDR5M [12:00] */
-/* MEMC_DDR_0 :: DRAM_MODE_15 :: GDDR5M :: unused_1 [12:12] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_15_GDDR5M_unused_1_MASK 0x00001000
-#define BCHP_MEMC_DDR_0_DRAM_MODE_15_GDDR5M_unused_1_SHIFT 12
-#define BCHP_MEMC_DDR_0_DRAM_MODE_15_GDDR5M_unused_1_DEFAULT 0x00000000
-
-/* MEMC_DDR_0 :: DRAM_MODE_15 :: GDDR5M :: ADDR_TRAINING [11:10] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_15_GDDR5M_ADDR_TRAINING_MASK 0x00000c00
-#define BCHP_MEMC_DDR_0_DRAM_MODE_15_GDDR5M_ADDR_TRAINING_SHIFT 10
-#define BCHP_MEMC_DDR_0_DRAM_MODE_15_GDDR5M_ADDR_TRAINING_DEFAULT 0x00000000
-
-/* MEMC_DDR_0 :: DRAM_MODE_15 :: GDDR5M :: MRE_MF1 [09:09] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_15_GDDR5M_MRE_MF1_MASK 0x00000200
-#define BCHP_MEMC_DDR_0_DRAM_MODE_15_GDDR5M_MRE_MF1_SHIFT 9
-#define BCHP_MEMC_DDR_0_DRAM_MODE_15_GDDR5M_MRE_MF1_DEFAULT 0x00000000
-#define BCHP_MEMC_DDR_0_DRAM_MODE_15_GDDR5M_MRE_MF1_ENABLE 0
-#define BCHP_MEMC_DDR_0_DRAM_MODE_15_GDDR5M_MRE_MF1_DISABLE 1
-
-/* MEMC_DDR_0 :: DRAM_MODE_15 :: GDDR5M :: MRE_MF2 [08:08] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_15_GDDR5M_MRE_MF2_MASK 0x00000100
-#define BCHP_MEMC_DDR_0_DRAM_MODE_15_GDDR5M_MRE_MF2_SHIFT 8
-#define BCHP_MEMC_DDR_0_DRAM_MODE_15_GDDR5M_MRE_MF2_DEFAULT 0x00000000
-#define BCHP_MEMC_DDR_0_DRAM_MODE_15_GDDR5M_MRE_MF2_ENABLE 0
-#define BCHP_MEMC_DDR_0_DRAM_MODE_15_GDDR5M_MRE_MF2_DISABLE 1
-
-/* MEMC_DDR_0 :: DRAM_MODE_15 :: GDDR5M :: unused_2 [07:00] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_15_GDDR5M_unused_2_MASK 0x000000ff
-#define BCHP_MEMC_DDR_0_DRAM_MODE_15_GDDR5M_unused_2_SHIFT 0
-#define BCHP_MEMC_DDR_0_DRAM_MODE_15_GDDR5M_unused_2_DEFAULT 0x00000000
-
-/* union - case GDDR5 [12:00] */
-/* MEMC_DDR_0 :: DRAM_MODE_15 :: GDDR5 :: unused_1 [12:11] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_15_GDDR5_unused_1_MASK 0x00001800
-#define BCHP_MEMC_DDR_0_DRAM_MODE_15_GDDR5_unused_1_SHIFT 11
-#define BCHP_MEMC_DDR_0_DRAM_MODE_15_GDDR5_unused_1_DEFAULT 0x00000000
-
-/* MEMC_DDR_0 :: DRAM_MODE_15 :: GDDR5 :: ADDR_TRAINING [10:10] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_15_GDDR5_ADDR_TRAINING_MASK 0x00000400
-#define BCHP_MEMC_DDR_0_DRAM_MODE_15_GDDR5_ADDR_TRAINING_SHIFT 10
-#define BCHP_MEMC_DDR_0_DRAM_MODE_15_GDDR5_ADDR_TRAINING_DEFAULT 0x00000000
-#define BCHP_MEMC_DDR_0_DRAM_MODE_15_GDDR5_ADDR_TRAINING_ENABLE 1
-#define BCHP_MEMC_DDR_0_DRAM_MODE_15_GDDR5_ADDR_TRAINING_DISABLE 0
-
-/* MEMC_DDR_0 :: DRAM_MODE_15 :: GDDR5 :: MRE_MF1 [09:09] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_15_GDDR5_MRE_MF1_MASK 0x00000200
-#define BCHP_MEMC_DDR_0_DRAM_MODE_15_GDDR5_MRE_MF1_SHIFT 9
-#define BCHP_MEMC_DDR_0_DRAM_MODE_15_GDDR5_MRE_MF1_DEFAULT 0x00000000
-#define BCHP_MEMC_DDR_0_DRAM_MODE_15_GDDR5_MRE_MF1_ENABLE 0
-#define BCHP_MEMC_DDR_0_DRAM_MODE_15_GDDR5_MRE_MF1_DISABLE 1
-
-/* MEMC_DDR_0 :: DRAM_MODE_15 :: GDDR5 :: MRE_MF2 [08:08] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_15_GDDR5_MRE_MF2_MASK 0x00000100
-#define BCHP_MEMC_DDR_0_DRAM_MODE_15_GDDR5_MRE_MF2_SHIFT 8
-#define BCHP_MEMC_DDR_0_DRAM_MODE_15_GDDR5_MRE_MF2_DEFAULT 0x00000000
-#define BCHP_MEMC_DDR_0_DRAM_MODE_15_GDDR5_MRE_MF2_ENABLE 0
-#define BCHP_MEMC_DDR_0_DRAM_MODE_15_GDDR5_MRE_MF2_DISABLE 1
-
-/* MEMC_DDR_0 :: DRAM_MODE_15 :: GDDR5 :: unused_2 [07:00] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_15_GDDR5_unused_2_MASK 0x000000ff
-#define BCHP_MEMC_DDR_0_DRAM_MODE_15_GDDR5_unused_2_SHIFT 0
-#define BCHP_MEMC_DDR_0_DRAM_MODE_15_GDDR5_unused_2_DEFAULT 0x00000000
-
-/* union - case Others [12:00] */
-/* MEMC_DDR_0 :: DRAM_MODE_15 :: Others :: unused_1 [12:00] */
-#define BCHP_MEMC_DDR_0_DRAM_MODE_15_Others_unused_1_MASK 0x00001fff
-#define BCHP_MEMC_DDR_0_DRAM_MODE_15_Others_unused_1_SHIFT 0
-#define BCHP_MEMC_DDR_0_DRAM_MODE_15_Others_unused_1_DEFAULT 0x00000000
-
-/***************************************************************************
- *PPD_CONFIG - Precharge power down mode configuration register
- ***************************************************************************/
-/* MEMC_DDR_0 :: PPD_CONFIG :: reserved0 [31:15] */
-#define BCHP_MEMC_DDR_0_PPD_CONFIG_reserved0_MASK 0xffff8000
-#define BCHP_MEMC_DDR_0_PPD_CONFIG_reserved0_SHIFT 15
-
-/* MEMC_DDR_0 :: PPD_CONFIG :: FORCE_PPD_EXIT [14:14] */
-#define BCHP_MEMC_DDR_0_PPD_CONFIG_FORCE_PPD_EXIT_MASK 0x00004000
-#define BCHP_MEMC_DDR_0_PPD_CONFIG_FORCE_PPD_EXIT_SHIFT 14
-#define BCHP_MEMC_DDR_0_PPD_CONFIG_FORCE_PPD_EXIT_DEFAULT 0x00000000
-
-/* MEMC_DDR_0 :: PPD_CONFIG :: PPD_FORCE [13:13] */
-#define BCHP_MEMC_DDR_0_PPD_CONFIG_PPD_FORCE_MASK 0x00002000
-#define BCHP_MEMC_DDR_0_PPD_CONFIG_PPD_FORCE_SHIFT 13
-#define BCHP_MEMC_DDR_0_PPD_CONFIG_PPD_FORCE_DEFAULT 0x00000000
-
-/* MEMC_DDR_0 :: PPD_CONFIG :: PPD_EN [12:12] */
-#define BCHP_MEMC_DDR_0_PPD_CONFIG_PPD_EN_MASK 0x00001000
-#define BCHP_MEMC_DDR_0_PPD_CONFIG_PPD_EN_SHIFT 12
-#define BCHP_MEMC_DDR_0_PPD_CONFIG_PPD_EN_DEFAULT 0x00000000
-
-/* MEMC_DDR_0 :: PPD_CONFIG :: INACT_COUNT [11:00] */
-#define BCHP_MEMC_DDR_0_PPD_CONFIG_INACT_COUNT_MASK 0x00000fff
-#define BCHP_MEMC_DDR_0_PPD_CONFIG_INACT_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_PPD_CONFIG_INACT_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *SRPD_CONFIG - Self-refresh power down mode configuration register
- ***************************************************************************/
-/* MEMC_DDR_0 :: SRPD_CONFIG :: reserved0 [31:18] */
-#define BCHP_MEMC_DDR_0_SRPD_CONFIG_reserved0_MASK 0xfffc0000
-#define BCHP_MEMC_DDR_0_SRPD_CONFIG_reserved0_SHIFT 18
-
-/* MEMC_DDR_0 :: SRPD_CONFIG :: FORCE_SRPD_EXIT [17:17] */
-#define BCHP_MEMC_DDR_0_SRPD_CONFIG_FORCE_SRPD_EXIT_MASK 0x00020000
-#define BCHP_MEMC_DDR_0_SRPD_CONFIG_FORCE_SRPD_EXIT_SHIFT 17
-#define BCHP_MEMC_DDR_0_SRPD_CONFIG_FORCE_SRPD_EXIT_DEFAULT 0x00000000
-
-/* MEMC_DDR_0 :: SRPD_CONFIG :: SRPD_EN [16:16] */
-#define BCHP_MEMC_DDR_0_SRPD_CONFIG_SRPD_EN_MASK 0x00010000
-#define BCHP_MEMC_DDR_0_SRPD_CONFIG_SRPD_EN_SHIFT 16
-#define BCHP_MEMC_DDR_0_SRPD_CONFIG_SRPD_EN_DEFAULT 0x00000000
-
-/* MEMC_DDR_0 :: SRPD_CONFIG :: INACT_COUNT [15:00] */
-#define BCHP_MEMC_DDR_0_SRPD_CONFIG_INACT_COUNT_MASK 0x0000ffff
-#define BCHP_MEMC_DDR_0_SRPD_CONFIG_INACT_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_SRPD_CONFIG_INACT_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *SSPD_CMD - Software standby power down mode
- ***************************************************************************/
-/* MEMC_DDR_0 :: SSPD_CMD :: reserved0 [31:01] */
-#define BCHP_MEMC_DDR_0_SSPD_CMD_reserved0_MASK 0xfffffffe
-#define BCHP_MEMC_DDR_0_SSPD_CMD_reserved0_SHIFT 1
-
-/* MEMC_DDR_0 :: SSPD_CMD :: SSPD [00:00] */
-#define BCHP_MEMC_DDR_0_SSPD_CMD_SSPD_MASK 0x00000001
-#define BCHP_MEMC_DDR_0_SSPD_CMD_SSPD_SHIFT 0
-#define BCHP_MEMC_DDR_0_SSPD_CMD_SSPD_DEFAULT 0x00000000
-
-/***************************************************************************
- *POWER_DOWN_STATUS - Power down status
- ***************************************************************************/
-/* MEMC_DDR_0 :: POWER_DOWN_STATUS :: reserved0 [31:03] */
-#define BCHP_MEMC_DDR_0_POWER_DOWN_STATUS_reserved0_MASK 0xfffffff8
-#define BCHP_MEMC_DDR_0_POWER_DOWN_STATUS_reserved0_SHIFT 3
-
-/* MEMC_DDR_0 :: POWER_DOWN_STATUS :: SSPD [02:02] */
-#define BCHP_MEMC_DDR_0_POWER_DOWN_STATUS_SSPD_MASK 0x00000004
-#define BCHP_MEMC_DDR_0_POWER_DOWN_STATUS_SSPD_SHIFT 2
-#define BCHP_MEMC_DDR_0_POWER_DOWN_STATUS_SSPD_DEFAULT 0x00000000
-
-/* MEMC_DDR_0 :: POWER_DOWN_STATUS :: SRPD [01:01] */
-#define BCHP_MEMC_DDR_0_POWER_DOWN_STATUS_SRPD_MASK 0x00000002
-#define BCHP_MEMC_DDR_0_POWER_DOWN_STATUS_SRPD_SHIFT 1
-#define BCHP_MEMC_DDR_0_POWER_DOWN_STATUS_SRPD_DEFAULT 0x00000000
-
-/* MEMC_DDR_0 :: POWER_DOWN_STATUS :: PPD [00:00] */
-#define BCHP_MEMC_DDR_0_POWER_DOWN_STATUS_PPD_MASK 0x00000001
-#define BCHP_MEMC_DDR_0_POWER_DOWN_STATUS_PPD_SHIFT 0
-#define BCHP_MEMC_DDR_0_POWER_DOWN_STATUS_PPD_DEFAULT 0x00000000
-
-/***************************************************************************
- *WARM_BOOT - Warm boot control registers
- ***************************************************************************/
-/* MEMC_DDR_0 :: WARM_BOOT :: reserved0 [31:01] */
-#define BCHP_MEMC_DDR_0_WARM_BOOT_reserved0_MASK 0xfffffffe
-#define BCHP_MEMC_DDR_0_WARM_BOOT_reserved0_SHIFT 1
-
-/* MEMC_DDR_0 :: WARM_BOOT :: WARM_BOOT [00:00] */
-#define BCHP_MEMC_DDR_0_WARM_BOOT_WARM_BOOT_MASK 0x00000001
-#define BCHP_MEMC_DDR_0_WARM_BOOT_WARM_BOOT_SHIFT 0
-#define BCHP_MEMC_DDR_0_WARM_BOOT_WARM_BOOT_DEFAULT 0x00000000
-
-/***************************************************************************
- *DRAM_TIMING_0 - DDR-SDRAM Timing Register 0
- ***************************************************************************/
-/* MEMC_DDR_0 :: DRAM_TIMING_0 :: TRRD_NOP [31:24] */
-#define BCHP_MEMC_DDR_0_DRAM_TIMING_0_TRRD_NOP_MASK 0xff000000
-#define BCHP_MEMC_DDR_0_DRAM_TIMING_0_TRRD_NOP_SHIFT 24
-#define BCHP_MEMC_DDR_0_DRAM_TIMING_0_TRRD_NOP_DEFAULT 0x00000006
-
-/* MEMC_DDR_0 :: DRAM_TIMING_0 :: TRCD_NOP [23:16] */
-#define BCHP_MEMC_DDR_0_DRAM_TIMING_0_TRCD_NOP_MASK 0x00ff0000
-#define BCHP_MEMC_DDR_0_DRAM_TIMING_0_TRCD_NOP_SHIFT 16
-#define BCHP_MEMC_DDR_0_DRAM_TIMING_0_TRCD_NOP_DEFAULT 0x00000008
-
-/* MEMC_DDR_0 :: DRAM_TIMING_0 :: TRP_NOP [15:08] */
-#define BCHP_MEMC_DDR_0_DRAM_TIMING_0_TRP_NOP_MASK 0x0000ff00
-#define BCHP_MEMC_DDR_0_DRAM_TIMING_0_TRP_NOP_SHIFT 8
-#define BCHP_MEMC_DDR_0_DRAM_TIMING_0_TRP_NOP_DEFAULT 0x00000008
-
-/* MEMC_DDR_0 :: DRAM_TIMING_0 :: TRAS_NOP [07:00] */
-#define BCHP_MEMC_DDR_0_DRAM_TIMING_0_TRAS_NOP_MASK 0x000000ff
-#define BCHP_MEMC_DDR_0_DRAM_TIMING_0_TRAS_NOP_SHIFT 0
-#define BCHP_MEMC_DDR_0_DRAM_TIMING_0_TRAS_NOP_DEFAULT 0x00000014
-
-/***************************************************************************
- *DRAM_TIMING_1 - DDR-SDRAM Timing Register 1
- ***************************************************************************/
-/* MEMC_DDR_0 :: DRAM_TIMING_1 :: reserved0 [31:28] */
-#define BCHP_MEMC_DDR_0_DRAM_TIMING_1_reserved0_MASK 0xf0000000
-#define BCHP_MEMC_DDR_0_DRAM_TIMING_1_reserved0_SHIFT 28
-
-/* MEMC_DDR_0 :: DRAM_TIMING_1 :: T32AW_NOP [27:16] */
-#define BCHP_MEMC_DDR_0_DRAM_TIMING_1_T32AW_NOP_MASK 0x0fff0000
-#define BCHP_MEMC_DDR_0_DRAM_TIMING_1_T32AW_NOP_SHIFT 16
-#define BCHP_MEMC_DDR_0_DRAM_TIMING_1_T32AW_NOP_DEFAULT 0x00000020
-
-/* MEMC_DDR_0 :: DRAM_TIMING_1 :: TFAW_NOP [15:08] */
-#define BCHP_MEMC_DDR_0_DRAM_TIMING_1_TFAW_NOP_MASK 0x0000ff00
-#define BCHP_MEMC_DDR_0_DRAM_TIMING_1_TFAW_NOP_SHIFT 8
-#define BCHP_MEMC_DDR_0_DRAM_TIMING_1_TFAW_NOP_DEFAULT 0x0000001b
-
-/* MEMC_DDR_0 :: DRAM_TIMING_1 :: TRTP_NOP [07:00] */
-#define BCHP_MEMC_DDR_0_DRAM_TIMING_1_TRTP_NOP_MASK 0x000000ff
-#define BCHP_MEMC_DDR_0_DRAM_TIMING_1_TRTP_NOP_SHIFT 0
-#define BCHP_MEMC_DDR_0_DRAM_TIMING_1_TRTP_NOP_DEFAULT 0x00000004
-
-/***************************************************************************
- *DRAM_TIMING_2 - Read to Write & write to read timing register
- ***************************************************************************/
-/* MEMC_DDR_0 :: DRAM_TIMING_2 :: TRRDL_NOP [31:24] */
-#define BCHP_MEMC_DDR_0_DRAM_TIMING_2_TRRDL_NOP_MASK 0xff000000
-#define BCHP_MEMC_DDR_0_DRAM_TIMING_2_TRRDL_NOP_SHIFT 24
-#define BCHP_MEMC_DDR_0_DRAM_TIMING_2_TRRDL_NOP_DEFAULT 0x00000006
-
-/* MEMC_DDR_0 :: DRAM_TIMING_2 :: WR2RDL_NOP [23:16] */
-#define BCHP_MEMC_DDR_0_DRAM_TIMING_2_WR2RDL_NOP_MASK 0x00ff0000
-#define BCHP_MEMC_DDR_0_DRAM_TIMING_2_WR2RDL_NOP_SHIFT 16
-#define BCHP_MEMC_DDR_0_DRAM_TIMING_2_WR2RDL_NOP_DEFAULT 0x0000000e
-
-/* MEMC_DDR_0 :: DRAM_TIMING_2 :: WR2RD_NOP [15:08] */
-#define BCHP_MEMC_DDR_0_DRAM_TIMING_2_WR2RD_NOP_MASK 0x0000ff00
-#define BCHP_MEMC_DDR_0_DRAM_TIMING_2_WR2RD_NOP_SHIFT 8
-#define BCHP_MEMC_DDR_0_DRAM_TIMING_2_WR2RD_NOP_DEFAULT 0x0000000e
-
-/* MEMC_DDR_0 :: DRAM_TIMING_2 :: RD2WR_NOP [07:00] */
-#define BCHP_MEMC_DDR_0_DRAM_TIMING_2_RD2WR_NOP_MASK 0x000000ff
-#define BCHP_MEMC_DDR_0_DRAM_TIMING_2_RD2WR_NOP_SHIFT 0
-#define BCHP_MEMC_DDR_0_DRAM_TIMING_2_RD2WR_NOP_DEFAULT 0x00000009
-
-/***************************************************************************
- *DRAM_TIMING_3 - DDR-SDRAM Timing Register 3
- ***************************************************************************/
-/* MEMC_DDR_0 :: DRAM_TIMING_3 :: reserved0 [31:24] */
-#define BCHP_MEMC_DDR_0_DRAM_TIMING_3_reserved0_MASK 0xff000000
-#define BCHP_MEMC_DDR_0_DRAM_TIMING_3_reserved0_SHIFT 24
-
-/* MEMC_DDR_0 :: DRAM_TIMING_3 :: CKENB_CKE_DELAY [23:19] */
-#define BCHP_MEMC_DDR_0_DRAM_TIMING_3_CKENB_CKE_DELAY_MASK 0x00f80000
-#define BCHP_MEMC_DDR_0_DRAM_TIMING_3_CKENB_CKE_DELAY_SHIFT 19
-#define BCHP_MEMC_DDR_0_DRAM_TIMING_3_CKENB_CKE_DELAY_DEFAULT 0x0000000c
-
-/* MEMC_DDR_0 :: DRAM_TIMING_3 :: POWERUP_CKE_DELAY [18:10] */
-#define BCHP_MEMC_DDR_0_DRAM_TIMING_3_POWERUP_CKE_DELAY_MASK 0x0007fc00
-#define BCHP_MEMC_DDR_0_DRAM_TIMING_3_POWERUP_CKE_DELAY_SHIFT 10
-#define BCHP_MEMC_DDR_0_DRAM_TIMING_3_POWERUP_CKE_DELAY_DEFAULT 0x0000005e
-
-/* MEMC_DDR_0 :: DRAM_TIMING_3 :: DLL_LOCK_DELAY [09:00] */
-#define BCHP_MEMC_DDR_0_DRAM_TIMING_3_DLL_LOCK_DELAY_MASK 0x000003ff
-#define BCHP_MEMC_DDR_0_DRAM_TIMING_3_DLL_LOCK_DELAY_SHIFT 0
-#define BCHP_MEMC_DDR_0_DRAM_TIMING_3_DLL_LOCK_DELAY_DEFAULT 0x00000200
-
-/***************************************************************************
- *DRAM_TIMING_4 - DDR-SDRAM Timing Register 4
- ***************************************************************************/
-/* MEMC_DDR_0 :: DRAM_TIMING_4 :: reserved0 [31:29] */
-#define BCHP_MEMC_DDR_0_DRAM_TIMING_4_reserved0_MASK 0xe0000000
-#define BCHP_MEMC_DDR_0_DRAM_TIMING_4_reserved0_SHIFT 29
-
-/* MEMC_DDR_0 :: DRAM_TIMING_4 :: PRECHARGE_ALL_DELAY [28:24] */
-#define BCHP_MEMC_DDR_0_DRAM_TIMING_4_PRECHARGE_ALL_DELAY_MASK 0x1f000000
-#define BCHP_MEMC_DDR_0_DRAM_TIMING_4_PRECHARGE_ALL_DELAY_SHIFT 24
-#define BCHP_MEMC_DDR_0_DRAM_TIMING_4_PRECHARGE_ALL_DELAY_DEFAULT 0x00000008
-
-/* MEMC_DDR_0 :: DRAM_TIMING_4 :: LOAD_MODE_DELAY [23:19] */
-#define BCHP_MEMC_DDR_0_DRAM_TIMING_4_LOAD_MODE_DELAY_MASK 0x00f80000
-#define BCHP_MEMC_DDR_0_DRAM_TIMING_4_LOAD_MODE_DELAY_SHIFT 19
-#define BCHP_MEMC_DDR_0_DRAM_TIMING_4_LOAD_MODE_DELAY_DEFAULT 0x0000000c
-
-/* MEMC_DDR_0 :: DRAM_TIMING_4 :: REFRESH_DELAY [18:10] */
-#define BCHP_MEMC_DDR_0_DRAM_TIMING_4_REFRESH_DELAY_MASK 0x0007fc00
-#define BCHP_MEMC_DDR_0_DRAM_TIMING_4_REFRESH_DELAY_SHIFT 10
-#define BCHP_MEMC_DDR_0_DRAM_TIMING_4_REFRESH_DELAY_DEFAULT 0x00000058
-
-/* MEMC_DDR_0 :: DRAM_TIMING_4 :: ZQCALIB_DELAY [09:00] */
-#define BCHP_MEMC_DDR_0_DRAM_TIMING_4_ZQCALIB_DELAY_MASK 0x000003ff
-#define BCHP_MEMC_DDR_0_DRAM_TIMING_4_ZQCALIB_DELAY_SHIFT 0
-#define BCHP_MEMC_DDR_0_DRAM_TIMING_4_ZQCALIB_DELAY_DEFAULT 0x00000200
-
-/***************************************************************************
- *DRAM_TIMING_5 - DDR-SDRAM Timing Register 5
- ***************************************************************************/
-/* MEMC_DDR_0 :: DRAM_TIMING_5 :: reserved0 [31:29] */
-#define BCHP_MEMC_DDR_0_DRAM_TIMING_5_reserved0_MASK 0xe0000000
-#define BCHP_MEMC_DDR_0_DRAM_TIMING_5_reserved0_SHIFT 29
-
-/* MEMC_DDR_0 :: DRAM_TIMING_5 :: CKE_ASSETION_DELAY [28:19] */
-#define BCHP_MEMC_DDR_0_DRAM_TIMING_5_CKE_ASSETION_DELAY_MASK 0x1ff80000
-#define BCHP_MEMC_DDR_0_DRAM_TIMING_5_CKE_ASSETION_DELAY_SHIFT 19
-#define BCHP_MEMC_DDR_0_DRAM_TIMING_5_CKE_ASSETION_DELAY_DEFAULT 0x00000105
-
-/* MEMC_DDR_0 :: DRAM_TIMING_5 :: CKE_MIN_WIDTH [18:15] */
-#define BCHP_MEMC_DDR_0_DRAM_TIMING_5_CKE_MIN_WIDTH_MASK 0x00078000
-#define BCHP_MEMC_DDR_0_DRAM_TIMING_5_CKE_MIN_WIDTH_SHIFT 15
-#define BCHP_MEMC_DDR_0_DRAM_TIMING_5_CKE_MIN_WIDTH_DEFAULT 0x00000003
-
-/* MEMC_DDR_0 :: DRAM_TIMING_5 :: PWDN_EXIT_DELAY [14:10] */
-#define BCHP_MEMC_DDR_0_DRAM_TIMING_5_PWDN_EXIT_DELAY_MASK 0x00007c00
-#define BCHP_MEMC_DDR_0_DRAM_TIMING_5_PWDN_EXIT_DELAY_SHIFT 10
-#define BCHP_MEMC_DDR_0_DRAM_TIMING_5_PWDN_EXIT_DELAY_DEFAULT 0x0000000d
-
-/* MEMC_DDR_0 :: DRAM_TIMING_5 :: SELFREF_EXIT_DELAY [09:00] */
-#define BCHP_MEMC_DDR_0_DRAM_TIMING_5_SELFREF_EXIT_DELAY_MASK 0x000003ff
-#define BCHP_MEMC_DDR_0_DRAM_TIMING_5_SELFREF_EXIT_DELAY_SHIFT 0
-#define BCHP_MEMC_DDR_0_DRAM_TIMING_5_SELFREF_EXIT_DELAY_DEFAULT 0x00000200
-
-/***************************************************************************
- *MIN_DQ_IDLE_CONTROL - Minimum DQ Idle Time Control
- ***************************************************************************/
-/* MEMC_DDR_0 :: MIN_DQ_IDLE_CONTROL :: reserved0 [31:23] */
-#define BCHP_MEMC_DDR_0_MIN_DQ_IDLE_CONTROL_reserved0_MASK 0xff800000
-#define BCHP_MEMC_DDR_0_MIN_DQ_IDLE_CONTROL_reserved0_SHIFT 23
-
-/* MEMC_DDR_0 :: MIN_DQ_IDLE_CONTROL :: WriteDelay [22:20] */
-#define BCHP_MEMC_DDR_0_MIN_DQ_IDLE_CONTROL_WriteDelay_MASK 0x00700000
-#define BCHP_MEMC_DDR_0_MIN_DQ_IDLE_CONTROL_WriteDelay_SHIFT 20
-#define BCHP_MEMC_DDR_0_MIN_DQ_IDLE_CONTROL_WriteDelay_DEFAULT 0x00000000
-
-/* MEMC_DDR_0 :: MIN_DQ_IDLE_CONTROL :: reserved1 [19:18] */
-#define BCHP_MEMC_DDR_0_MIN_DQ_IDLE_CONTROL_reserved1_MASK 0x000c0000
-#define BCHP_MEMC_DDR_0_MIN_DQ_IDLE_CONTROL_reserved1_SHIFT 18
-
-/* MEMC_DDR_0 :: MIN_DQ_IDLE_CONTROL :: WriteForceIdle [17:17] */
-#define BCHP_MEMC_DDR_0_MIN_DQ_IDLE_CONTROL_WriteForceIdle_MASK 0x00020000
-#define BCHP_MEMC_DDR_0_MIN_DQ_IDLE_CONTROL_WriteForceIdle_SHIFT 17
-#define BCHP_MEMC_DDR_0_MIN_DQ_IDLE_CONTROL_WriteForceIdle_DEFAULT 0x00000000
-
-/* MEMC_DDR_0 :: MIN_DQ_IDLE_CONTROL :: WriteEnable [16:16] */
-#define BCHP_MEMC_DDR_0_MIN_DQ_IDLE_CONTROL_WriteEnable_MASK 0x00010000
-#define BCHP_MEMC_DDR_0_MIN_DQ_IDLE_CONTROL_WriteEnable_SHIFT 16
-#define BCHP_MEMC_DDR_0_MIN_DQ_IDLE_CONTROL_WriteEnable_DEFAULT 0x00000000
-
-/* MEMC_DDR_0 :: MIN_DQ_IDLE_CONTROL :: reserved2 [15:07] */
-#define BCHP_MEMC_DDR_0_MIN_DQ_IDLE_CONTROL_reserved2_MASK 0x0000ff80
-#define BCHP_MEMC_DDR_0_MIN_DQ_IDLE_CONTROL_reserved2_SHIFT 7
-
-/* MEMC_DDR_0 :: MIN_DQ_IDLE_CONTROL :: ReadDelay [06:04] */
-#define BCHP_MEMC_DDR_0_MIN_DQ_IDLE_CONTROL_ReadDelay_MASK 0x00000070
-#define BCHP_MEMC_DDR_0_MIN_DQ_IDLE_CONTROL_ReadDelay_SHIFT 4
-#define BCHP_MEMC_DDR_0_MIN_DQ_IDLE_CONTROL_ReadDelay_DEFAULT 0x00000000
-
-/* MEMC_DDR_0 :: MIN_DQ_IDLE_CONTROL :: reserved3 [03:02] */
-#define BCHP_MEMC_DDR_0_MIN_DQ_IDLE_CONTROL_reserved3_MASK 0x0000000c
-#define BCHP_MEMC_DDR_0_MIN_DQ_IDLE_CONTROL_reserved3_SHIFT 2
-
-/* MEMC_DDR_0 :: MIN_DQ_IDLE_CONTROL :: ReadForceIdle [01:01] */
-#define BCHP_MEMC_DDR_0_MIN_DQ_IDLE_CONTROL_ReadForceIdle_MASK 0x00000002
-#define BCHP_MEMC_DDR_0_MIN_DQ_IDLE_CONTROL_ReadForceIdle_SHIFT 1
-#define BCHP_MEMC_DDR_0_MIN_DQ_IDLE_CONTROL_ReadForceIdle_DEFAULT 0x00000000
-
-/* MEMC_DDR_0 :: MIN_DQ_IDLE_CONTROL :: ReadEnable [00:00] */
-#define BCHP_MEMC_DDR_0_MIN_DQ_IDLE_CONTROL_ReadEnable_MASK 0x00000001
-#define BCHP_MEMC_DDR_0_MIN_DQ_IDLE_CONTROL_ReadEnable_SHIFT 0
-#define BCHP_MEMC_DDR_0_MIN_DQ_IDLE_CONTROL_ReadEnable_DEFAULT 0x00000000
-
-/***************************************************************************
- *PHY_OP_ACCESS_PENALTY - PHY Operational Access Penalty Count.
- ***************************************************************************/
-/* MEMC_DDR_0 :: PHY_OP_ACCESS_PENALTY :: PHY_OP_ACCESS_WAIT_PENALTY [31:00] */
-#define BCHP_MEMC_DDR_0_PHY_OP_ACCESS_PENALTY_PHY_OP_ACCESS_WAIT_PENALTY_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_PHY_OP_ACCESS_PENALTY_PHY_OP_ACCESS_WAIT_PENALTY_SHIFT 0
-#define BCHP_MEMC_DDR_0_PHY_OP_ACCESS_PENALTY_PHY_OP_ACCESS_WAIT_PENALTY_DEFAULT 0x00000004
-
-/***************************************************************************
- *CNTRLR_SM_TIMEOUT - Memory Controller , state machine timeout register.
- ***************************************************************************/
-/* MEMC_DDR_0 :: CNTRLR_SM_TIMEOUT :: reserved0 [31:17] */
-#define BCHP_MEMC_DDR_0_CNTRLR_SM_TIMEOUT_reserved0_MASK 0xfffe0000
-#define BCHP_MEMC_DDR_0_CNTRLR_SM_TIMEOUT_reserved0_SHIFT 17
-
-/* MEMC_DDR_0 :: CNTRLR_SM_TIMEOUT :: ENABLE [16:16] */
-#define BCHP_MEMC_DDR_0_CNTRLR_SM_TIMEOUT_ENABLE_MASK 0x00010000
-#define BCHP_MEMC_DDR_0_CNTRLR_SM_TIMEOUT_ENABLE_SHIFT 16
-#define BCHP_MEMC_DDR_0_CNTRLR_SM_TIMEOUT_ENABLE_DEFAULT 0x00000000
-
-/* MEMC_DDR_0 :: CNTRLR_SM_TIMEOUT :: COUNT [15:00] */
-#define BCHP_MEMC_DDR_0_CNTRLR_SM_TIMEOUT_COUNT_MASK 0x0000ffff
-#define BCHP_MEMC_DDR_0_CNTRLR_SM_TIMEOUT_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_CNTRLR_SM_TIMEOUT_COUNT_DEFAULT 0x0000ffff
-
-/***************************************************************************
- *BANK_STATUS - Memory Controller, Bank Status Register
- ***************************************************************************/
-/* MEMC_DDR_0 :: BANK_STATUS :: reserved0 [31:16] */
-#define BCHP_MEMC_DDR_0_BANK_STATUS_reserved0_MASK 0xffff0000
-#define BCHP_MEMC_DDR_0_BANK_STATUS_reserved0_SHIFT 16
-
-/* MEMC_DDR_0 :: BANK_STATUS :: BANK_STATUS [15:00] */
-#define BCHP_MEMC_DDR_0_BANK_STATUS_BANK_STATUS_MASK 0x0000ffff
-#define BCHP_MEMC_DDR_0_BANK_STATUS_BANK_STATUS_SHIFT 0
-#define BCHP_MEMC_DDR_0_BANK_STATUS_BANK_STATUS_DEFAULT 0x0000ffff
-
-/***************************************************************************
- *TESTER_LATENCY - Memory Controller, Tester Latency Register.
- ***************************************************************************/
-/* MEMC_DDR_0 :: TESTER_LATENCY :: reserved0 [31:08] */
-#define BCHP_MEMC_DDR_0_TESTER_LATENCY_reserved0_MASK 0xffffff00
-#define BCHP_MEMC_DDR_0_TESTER_LATENCY_reserved0_SHIFT 8
-
-/* MEMC_DDR_0 :: TESTER_LATENCY :: TLATENCY_SEL [07:00] */
-#define BCHP_MEMC_DDR_0_TESTER_LATENCY_TLATENCY_SEL_MASK 0x000000ff
-#define BCHP_MEMC_DDR_0_TESTER_LATENCY_TLATENCY_SEL_SHIFT 0
-#define BCHP_MEMC_DDR_0_TESTER_LATENCY_TLATENCY_SEL_DEFAULT 0x00000000
-
-/***************************************************************************
- *SEQ_RING_BUF_DEPTH - Sequencer Ring Buffer programmable depth.
- ***************************************************************************/
-/* MEMC_DDR_0 :: SEQ_RING_BUF_DEPTH :: reserved0 [31:05] */
-#define BCHP_MEMC_DDR_0_SEQ_RING_BUF_DEPTH_reserved0_MASK 0xffffffe0
-#define BCHP_MEMC_DDR_0_SEQ_RING_BUF_DEPTH_reserved0_SHIFT 5
-
-/* MEMC_DDR_0 :: SEQ_RING_BUF_DEPTH :: RING_BUF_DEPTH [04:00] */
-#define BCHP_MEMC_DDR_0_SEQ_RING_BUF_DEPTH_RING_BUF_DEPTH_MASK 0x0000001f
-#define BCHP_MEMC_DDR_0_SEQ_RING_BUF_DEPTH_RING_BUF_DEPTH_SHIFT 0
-#define BCHP_MEMC_DDR_0_SEQ_RING_BUF_DEPTH_RING_BUF_DEPTH_DEFAULT 0x00000011
-
-/***************************************************************************
- *SEQ_WRDATA_ERR_INFO - Sequencer write data error info
- ***************************************************************************/
-/* MEMC_DDR_0 :: SEQ_WRDATA_ERR_INFO :: reserved0 [31:21] */
-#define BCHP_MEMC_DDR_0_SEQ_WRDATA_ERR_INFO_reserved0_MASK 0xffe00000
-#define BCHP_MEMC_DDR_0_SEQ_WRDATA_ERR_INFO_reserved0_SHIFT 21
-
-/* MEMC_DDR_0 :: SEQ_WRDATA_ERR_INFO :: INTF_ID [20:16] */
-#define BCHP_MEMC_DDR_0_SEQ_WRDATA_ERR_INFO_INTF_ID_MASK 0x001f0000
-#define BCHP_MEMC_DDR_0_SEQ_WRDATA_ERR_INFO_INTF_ID_SHIFT 16
-#define BCHP_MEMC_DDR_0_SEQ_WRDATA_ERR_INFO_INTF_ID_DEFAULT 0x00000000
-
-/* MEMC_DDR_0 :: SEQ_WRDATA_ERR_INFO :: reserved1 [15:08] */
-#define BCHP_MEMC_DDR_0_SEQ_WRDATA_ERR_INFO_reserved1_MASK 0x0000ff00
-#define BCHP_MEMC_DDR_0_SEQ_WRDATA_ERR_INFO_reserved1_SHIFT 8
-
-/* MEMC_DDR_0 :: SEQ_WRDATA_ERR_INFO :: INTF_TRANSACTION_ID [07:00] */
-#define BCHP_MEMC_DDR_0_SEQ_WRDATA_ERR_INFO_INTF_TRANSACTION_ID_MASK 0x000000ff
-#define BCHP_MEMC_DDR_0_SEQ_WRDATA_ERR_INFO_INTF_TRANSACTION_ID_SHIFT 0
-#define BCHP_MEMC_DDR_0_SEQ_WRDATA_ERR_INFO_INTF_TRANSACTION_ID_DEFAULT 0x00000000
-
-/***************************************************************************
- *SEQ_WRDATA_TRANSID_MISMATCH_INFO - Sequencer transaction ID mismatch error info
- ***************************************************************************/
-/* MEMC_DDR_0 :: SEQ_WRDATA_TRANSID_MISMATCH_INFO :: reserved0 [31:28] */
-#define BCHP_MEMC_DDR_0_SEQ_WRDATA_TRANSID_MISMATCH_INFO_reserved0_MASK 0xf0000000
-#define BCHP_MEMC_DDR_0_SEQ_WRDATA_TRANSID_MISMATCH_INFO_reserved0_SHIFT 28
-
-/* MEMC_DDR_0 :: SEQ_WRDATA_TRANSID_MISMATCH_INFO :: INTF_TYPE [27:24] */
-#define BCHP_MEMC_DDR_0_SEQ_WRDATA_TRANSID_MISMATCH_INFO_INTF_TYPE_MASK 0x0f000000
-#define BCHP_MEMC_DDR_0_SEQ_WRDATA_TRANSID_MISMATCH_INFO_INTF_TYPE_SHIFT 24
-#define BCHP_MEMC_DDR_0_SEQ_WRDATA_TRANSID_MISMATCH_INFO_INTF_TYPE_DEFAULT 0x00000000
-
-/* MEMC_DDR_0 :: SEQ_WRDATA_TRANSID_MISMATCH_INFO :: reserved1 [23:21] */
-#define BCHP_MEMC_DDR_0_SEQ_WRDATA_TRANSID_MISMATCH_INFO_reserved1_MASK 0x00e00000
-#define BCHP_MEMC_DDR_0_SEQ_WRDATA_TRANSID_MISMATCH_INFO_reserved1_SHIFT 21
-
-/* MEMC_DDR_0 :: SEQ_WRDATA_TRANSID_MISMATCH_INFO :: INTF_ID [20:16] */
-#define BCHP_MEMC_DDR_0_SEQ_WRDATA_TRANSID_MISMATCH_INFO_INTF_ID_MASK 0x001f0000
-#define BCHP_MEMC_DDR_0_SEQ_WRDATA_TRANSID_MISMATCH_INFO_INTF_ID_SHIFT 16
-#define BCHP_MEMC_DDR_0_SEQ_WRDATA_TRANSID_MISMATCH_INFO_INTF_ID_DEFAULT 0x00000000
-
-/* MEMC_DDR_0 :: SEQ_WRDATA_TRANSID_MISMATCH_INFO :: CMD_TRANS_ID [15:08] */
-#define BCHP_MEMC_DDR_0_SEQ_WRDATA_TRANSID_MISMATCH_INFO_CMD_TRANS_ID_MASK 0x0000ff00
-#define BCHP_MEMC_DDR_0_SEQ_WRDATA_TRANSID_MISMATCH_INFO_CMD_TRANS_ID_SHIFT 8
-#define BCHP_MEMC_DDR_0_SEQ_WRDATA_TRANSID_MISMATCH_INFO_CMD_TRANS_ID_DEFAULT 0x00000000
-
-/* MEMC_DDR_0 :: SEQ_WRDATA_TRANSID_MISMATCH_INFO :: WRDATA_TRANS_ID [07:00] */
-#define BCHP_MEMC_DDR_0_SEQ_WRDATA_TRANSID_MISMATCH_INFO_WRDATA_TRANS_ID_MASK 0x000000ff
-#define BCHP_MEMC_DDR_0_SEQ_WRDATA_TRANSID_MISMATCH_INFO_WRDATA_TRANS_ID_SHIFT 0
-#define BCHP_MEMC_DDR_0_SEQ_WRDATA_TRANSID_MISMATCH_INFO_WRDATA_TRANS_ID_DEFAULT 0x00000000
-
-/***************************************************************************
- *SEQ_CLEAR_VIOLATIONS - Sequencer Violation Info register clear.
- ***************************************************************************/
-/* MEMC_DDR_0 :: SEQ_CLEAR_VIOLATIONS :: reserved0 [31:01] */
-#define BCHP_MEMC_DDR_0_SEQ_CLEAR_VIOLATIONS_reserved0_MASK 0xfffffffe
-#define BCHP_MEMC_DDR_0_SEQ_CLEAR_VIOLATIONS_reserved0_SHIFT 1
-
-/* MEMC_DDR_0 :: SEQ_CLEAR_VIOLATIONS :: SEQ_CLEAR_VIOL [00:00] */
-#define BCHP_MEMC_DDR_0_SEQ_CLEAR_VIOLATIONS_SEQ_CLEAR_VIOL_MASK 0x00000001
-#define BCHP_MEMC_DDR_0_SEQ_CLEAR_VIOLATIONS_SEQ_CLEAR_VIOL_SHIFT 0
-#define BCHP_MEMC_DDR_0_SEQ_CLEAR_VIOLATIONS_SEQ_CLEAR_VIOL_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CONTROL - Statistics Control register
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CONTROL :: reserved0 [31:11] */
-#define BCHP_MEMC_DDR_0_STAT_CONTROL_reserved0_MASK 0xfffff800
-#define BCHP_MEMC_DDR_0_STAT_CONTROL_reserved0_SHIFT 11
-
-/* MEMC_DDR_0 :: STAT_CONTROL :: PER_CLIENT_MODE [10:10] */
-#define BCHP_MEMC_DDR_0_STAT_CONTROL_PER_CLIENT_MODE_MASK 0x00000400
-#define BCHP_MEMC_DDR_0_STAT_CONTROL_PER_CLIENT_MODE_SHIFT 10
-#define BCHP_MEMC_DDR_0_STAT_CONTROL_PER_CLIENT_MODE_DEFAULT 0x00000000
-
-/* MEMC_DDR_0 :: STAT_CONTROL :: COUNTER_MODE [09:09] */
-#define BCHP_MEMC_DDR_0_STAT_CONTROL_COUNTER_MODE_MASK 0x00000200
-#define BCHP_MEMC_DDR_0_STAT_CONTROL_COUNTER_MODE_SHIFT 9
-#define BCHP_MEMC_DDR_0_STAT_CONTROL_COUNTER_MODE_DEFAULT 0x00000000
-#define BCHP_MEMC_DDR_0_STAT_CONTROL_COUNTER_MODE_MAX_MIN_FUNCT 1
-#define BCHP_MEMC_DDR_0_STAT_CONTROL_COUNTER_MODE_NORMAL 0
-
-/* MEMC_DDR_0 :: STAT_CONTROL :: STAT_ENABLE [08:08] */
-#define BCHP_MEMC_DDR_0_STAT_CONTROL_STAT_ENABLE_MASK 0x00000100
-#define BCHP_MEMC_DDR_0_STAT_CONTROL_STAT_ENABLE_SHIFT 8
-#define BCHP_MEMC_DDR_0_STAT_CONTROL_STAT_ENABLE_DEFAULT 0x00000000
-#define BCHP_MEMC_DDR_0_STAT_CONTROL_STAT_ENABLE_ENABLE 1
-#define BCHP_MEMC_DDR_0_STAT_CONTROL_STAT_ENABLE_DISABLE 0
-
-/* MEMC_DDR_0 :: STAT_CONTROL :: CLIENT_ID [07:00] */
-#define BCHP_MEMC_DDR_0_STAT_CONTROL_CLIENT_ID_MASK 0x000000ff
-#define BCHP_MEMC_DDR_0_STAT_CONTROL_CLIENT_ID_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CONTROL_CLIENT_ID_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_TIMER - Statistics Timer
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_TIMER :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_TIMER_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_TIMER_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_TIMER_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_IDLE_NOP - DRAM Idle_NOP Cycle Count Register.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_IDLE_NOP :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_IDLE_NOP_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_IDLE_NOP_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_IDLE_NOP_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_MAX_IDLE_NOP - Maximum DRAM idle_NOP cycle count register.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_MAX_IDLE_NOP :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_MAX_IDLE_NOP_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_MAX_IDLE_NOP_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_MAX_IDLE_NOP_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_MIN_IDLE_NOP - Minimum DRAM idle_NOP cycle count register.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_MIN_IDLE_NOP :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_MIN_IDLE_NOP_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_MIN_IDLE_NOP_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_MIN_IDLE_NOP_COUNT_DEFAULT 0xffffffff
-
-/***************************************************************************
- *STAT_CAS_ALL - CAS Count Register.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_ALL :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_ALL_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_ALL_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_ALL_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_MAX_CAS_ALL - Maximum DRAM CAS cycle count register.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_MAX_CAS_ALL :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_MAX_CAS_ALL_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_MAX_CAS_ALL_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_MAX_CAS_ALL_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_MIN_CAS_ALL - Minimum DRAM CAS cycle count register.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_MIN_CAS_ALL :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_MIN_CAS_ALL_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_MIN_CAS_ALL_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_MIN_CAS_ALL_COUNT_DEFAULT 0xffffffff
-
-/***************************************************************************
- *STAT_PENALTY_ALL - DRAM Penalty Cycle Count register.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_PENALTY_ALL :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_PENALTY_ALL_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_PENALTY_ALL_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_PENALTY_ALL_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_PENALTY_GDDRWM - GDDR Write Mask Penalty Cycle Count register.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_PENALTY_GDDRWM :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_PENALTY_GDDRWM_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_PENALTY_GDDRWM_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_PENALTY_GDDRWM_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_MAX_TRANS_CYCLES_ALL - Maximum number of transactions cycles (CAS+Penalty_ALL).
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_MAX_TRANS_CYCLES_ALL :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_MAX_TRANS_CYCLES_ALL_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_MAX_TRANS_CYCLES_ALL_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_MAX_TRANS_CYCLES_ALL_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_MIN_TRANS_CYCLES_ALL - Minimum number of transactions cycles (CAS+Penalty_ALL).
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_MIN_TRANS_CYCLES_ALL :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_MIN_TRANS_CYCLES_ALL_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_MIN_TRANS_CYCLES_ALL_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_MIN_TRANS_CYCLES_ALL_COUNT_DEFAULT 0xffffffff
-
-/***************************************************************************
- *STAT_TRANS_READ_ALL - Number of overall system memory read transactions.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_TRANS_READ_ALL :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_TRANS_READ_ALL_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_TRANS_READ_ALL_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_TRANS_READ_ALL_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_TRANS_WRITE_ALL - Number of overall system memory write transactions.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_TRANS_WRITE_ALL :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_TRANS_WRITE_ALL_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_TRANS_WRITE_ALL_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_TRANS_WRITE_ALL_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_MAX_TRANS_ALL - Maximum Number of Overall System memory transactions.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_MAX_TRANS_ALL :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_MAX_TRANS_ALL_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_MAX_TRANS_ALL_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_MAX_TRANS_ALL_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_MIN_TRANS_ALL - Minimum Number of Overall System memory transactions.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_MIN_TRANS_ALL :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_MIN_TRANS_ALL_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_MIN_TRANS_ALL_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_MIN_TRANS_ALL_COUNT_DEFAULT 0xffffffff
-
-/***************************************************************************
- *STAT_CLIENT_SERVICE_CAS - Service CAS Cycle Count register.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CLIENT_SERVICE_CAS :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CLIENT_SERVICE_CAS_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CLIENT_SERVICE_CAS_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CLIENT_SERVICE_CAS_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_MAX_CLIENT_SERVICE_CAS - Maximum service CAS cycle count register.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_MAX_CLIENT_SERVICE_CAS :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_MAX_CLIENT_SERVICE_CAS_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_MAX_CLIENT_SERVICE_CAS_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_MAX_CLIENT_SERVICE_CAS_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_MIN_CLIENT_SERVICE_CAS - Minimum service CAS cycle count register.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_MIN_CLIENT_SERVICE_CAS :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_MIN_CLIENT_SERVICE_CAS_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_MIN_CLIENT_SERVICE_CAS_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_MIN_CLIENT_SERVICE_CAS_COUNT_DEFAULT 0xffffffff
-
-/***************************************************************************
- *STAT_CLIENT_SERVICE_INTR_PENALTY - Service Intra DRAM Penalty Cycle Count register.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CLIENT_SERVICE_INTR_PENALTY :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CLIENT_SERVICE_INTR_PENALTY_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CLIENT_SERVICE_INTR_PENALTY_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CLIENT_SERVICE_INTR_PENALTY_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CLIENT_SERVICE_POST_PENALTY - Service Post DRAM Penalty Cycle Count register.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CLIENT_SERVICE_POST_PENALTY :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CLIENT_SERVICE_POST_PENALTY_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CLIENT_SERVICE_POST_PENALTY_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CLIENT_SERVICE_POST_PENALTY_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CLIENT_SERVICE_GDDRWM_PENALTY - Service GDDR Write Mask Penalty Cycle Count register.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CLIENT_SERVICE_GDDRWM_PENALTY :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CLIENT_SERVICE_GDDRWM_PENALTY_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CLIENT_SERVICE_GDDRWM_PENALTY_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CLIENT_SERVICE_GDDRWM_PENALTY_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_MAX_CLIENT_SERVICE_CYCLES - Maximum service cycle count register.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_MAX_CLIENT_SERVICE_CYCLES :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_MAX_CLIENT_SERVICE_CYCLES_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_MAX_CLIENT_SERVICE_CYCLES_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_MAX_CLIENT_SERVICE_CYCLES_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_MIN_CLIENT_SERVICE_CYCLES - Minimum service cycle count register.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_MIN_CLIENT_SERVICE_CYCLES :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_MIN_CLIENT_SERVICE_CYCLES_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_MIN_CLIENT_SERVICE_CYCLES_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_MIN_CLIENT_SERVICE_CYCLES_COUNT_DEFAULT 0xffffffff
-
-/***************************************************************************
- *STAT_CLIENT_SERVICE_TRANS_READ - Service Read Transaction Count register.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CLIENT_SERVICE_TRANS_READ :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CLIENT_SERVICE_TRANS_READ_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CLIENT_SERVICE_TRANS_READ_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CLIENT_SERVICE_TRANS_READ_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CLIENT_SERVICE_TRANS_WRITE - Service Write Transaction Count register.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CLIENT_SERVICE_TRANS_WRITE :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CLIENT_SERVICE_TRANS_WRITE_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CLIENT_SERVICE_TRANS_WRITE_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CLIENT_SERVICE_TRANS_WRITE_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_MAX_CLIENT_SERVICE_TRANS - Maximum service Transaction count register.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_MAX_CLIENT_SERVICE_TRANS :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_MAX_CLIENT_SERVICE_TRANS_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_MAX_CLIENT_SERVICE_TRANS_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_MAX_CLIENT_SERVICE_TRANS_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_MIN_CLIENT_SERVICE_TRANS - Minimum service cycle Transaction register.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_MIN_CLIENT_SERVICE_TRANS :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_MIN_CLIENT_SERVICE_TRANS_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_MIN_CLIENT_SERVICE_TRANS_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_MIN_CLIENT_SERVICE_TRANS_COUNT_DEFAULT 0xffffffff
-
-/***************************************************************************
- *STAT_CLIENT_SERVICE_LATENCY - Service Latency Count register.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CLIENT_SERVICE_LATENCY :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CLIENT_SERVICE_LATENCY_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CLIENT_SERVICE_LATENCY_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CLIENT_SERVICE_LATENCY_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_MAX_CLIENT_SERVICE_LATENCY - Maximum Service Latency count register.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_MAX_CLIENT_SERVICE_LATENCY :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_MAX_CLIENT_SERVICE_LATENCY_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_MAX_CLIENT_SERVICE_LATENCY_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_MAX_CLIENT_SERVICE_LATENCY_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_MIN_CLIENT_SERVICE_LATENCY - Minimum Service Latency count register.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_MIN_CLIENT_SERVICE_LATENCY :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_MIN_CLIENT_SERVICE_LATENCY_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_MIN_CLIENT_SERVICE_LATENCY_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_MIN_CLIENT_SERVICE_LATENCY_COUNT_DEFAULT 0xffffffff
-
-/***************************************************************************
- *STAT_CLIENT_ABS_MAX_SERVICE_LATENCY - Absolute Minimum Service Latency count register.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CLIENT_ABS_MAX_SERVICE_LATENCY :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CLIENT_ABS_MAX_SERVICE_LATENCY_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CLIENT_ABS_MAX_SERVICE_LATENCY_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CLIENT_ABS_MAX_SERVICE_LATENCY_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CLIENT_ABS_MIN_SERVICE_LATENCY - Absolute Maximum Service Latency count register.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CLIENT_ABS_MIN_SERVICE_LATENCY :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CLIENT_ABS_MIN_SERVICE_LATENCY_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CLIENT_ABS_MIN_SERVICE_LATENCY_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CLIENT_ABS_MIN_SERVICE_LATENCY_COUNT_DEFAULT 0xffffffff
-
-/***************************************************************************
- *STAT_REFRESH - Total number of refreshes issued.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_REFRESH :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_REFRESH_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_REFRESH_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_REFRESH_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_MIN_DQ_IDLE_WRITE - Min DQ Idle Write event counter
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_MIN_DQ_IDLE_WRITE :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_MIN_DQ_IDLE_WRITE_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_MIN_DQ_IDLE_WRITE_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_MIN_DQ_IDLE_WRITE_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_MIN_DQ_IDLE_READ - Min DQ Idle Read event counter
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_MIN_DQ_IDLE_READ :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_MIN_DQ_IDLE_READ_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_MIN_DQ_IDLE_READ_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_MIN_DQ_IDLE_READ_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_0 - CAS or consumption cycle count register for client 0.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_0 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_0_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_0_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_0_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_1 - CAS or consumption cycle count register for client 1.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_1 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_1_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_1_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_1_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_2 - CAS or consumption cycle count register for client 2.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_2 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_2_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_2_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_2_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_3 - CAS or consumption cycle count register for client 3.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_3 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_3_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_3_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_3_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_4 - CAS or consumption cycle count register for client 4.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_4 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_4_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_4_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_4_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_5 - CAS or consumption cycle count register for client 5.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_5 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_5_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_5_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_5_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_6 - CAS or consumption cycle count register for client 6.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_6 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_6_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_6_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_6_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_7 - CAS or consumption cycle count register for client 7.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_7 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_7_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_7_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_7_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_8 - CAS or consumption cycle count register for client 8.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_8 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_8_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_8_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_8_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_9 - CAS or consumption cycle count register for client 9.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_9 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_9_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_9_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_9_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_10 - CAS or consumption cycle count register for client 10.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_10 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_10_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_10_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_10_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_11 - CAS or consumption cycle count register for client 11.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_11 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_11_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_11_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_11_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_12 - CAS or consumption cycle count register for client 12.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_12 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_12_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_12_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_12_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_13 - CAS or consumption cycle count register for client 13.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_13 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_13_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_13_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_13_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_14 - CAS or consumption cycle count register for client 14.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_14 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_14_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_14_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_14_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_15 - CAS or consumption cycle count register for client 15.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_15 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_15_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_15_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_15_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_16 - CAS or consumption cycle count register for client 16.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_16 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_16_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_16_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_16_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_17 - CAS or consumption cycle count register for client 17.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_17 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_17_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_17_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_17_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_18 - CAS or consumption cycle count register for client 18.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_18 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_18_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_18_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_18_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_19 - CAS or consumption cycle count register for client 19.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_19 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_19_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_19_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_19_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_20 - CAS or consumption cycle count register for client 20.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_20 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_20_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_20_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_20_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_21 - CAS or consumption cycle count register for client 21.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_21 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_21_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_21_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_21_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_22 - CAS or consumption cycle count register for client 22.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_22 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_22_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_22_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_22_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_23 - CAS or consumption cycle count register for client 23.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_23 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_23_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_23_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_23_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_24 - CAS or consumption cycle count register for client 24.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_24 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_24_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_24_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_24_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_25 - CAS or consumption cycle count register for client 25.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_25 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_25_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_25_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_25_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_26 - CAS or consumption cycle count register for client 26.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_26 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_26_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_26_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_26_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_27 - CAS or consumption cycle count register for client 27.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_27 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_27_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_27_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_27_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_28 - CAS or consumption cycle count register for client 28.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_28 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_28_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_28_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_28_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_29 - CAS or consumption cycle count register for client 29.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_29 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_29_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_29_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_29_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_30 - CAS or consumption cycle count register for client 30.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_30 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_30_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_30_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_30_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_31 - CAS or consumption cycle count register for client 31.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_31 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_31_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_31_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_31_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_32 - CAS or consumption cycle count register for client 32.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_32 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_32_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_32_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_32_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_33 - CAS or consumption cycle count register for client 33.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_33 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_33_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_33_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_33_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_34 - CAS or consumption cycle count register for client 34.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_34 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_34_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_34_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_34_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_35 - CAS or consumption cycle count register for client 35.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_35 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_35_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_35_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_35_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_36 - CAS or consumption cycle count register for client 36.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_36 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_36_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_36_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_36_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_37 - CAS or consumption cycle count register for client 37.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_37 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_37_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_37_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_37_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_38 - CAS or consumption cycle count register for client 38.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_38 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_38_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_38_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_38_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_39 - CAS or consumption cycle count register for client 39.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_39 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_39_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_39_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_39_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_40 - CAS or consumption cycle count register for client 40.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_40 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_40_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_40_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_40_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_41 - CAS or consumption cycle count register for client 41.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_41 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_41_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_41_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_41_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_42 - CAS or consumption cycle count register for client 42.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_42 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_42_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_42_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_42_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_43 - CAS or consumption cycle count register for client 43.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_43 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_43_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_43_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_43_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_44 - CAS or consumption cycle count register for client 44.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_44 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_44_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_44_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_44_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_45 - CAS or consumption cycle count register for client 45.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_45 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_45_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_45_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_45_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_46 - CAS or consumption cycle count register for client 46.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_46 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_46_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_46_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_46_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_47 - CAS or consumption cycle count register for client 47.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_47 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_47_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_47_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_47_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_48 - CAS or consumption cycle count register for client 48.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_48 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_48_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_48_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_48_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_49 - CAS or consumption cycle count register for client 49.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_49 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_49_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_49_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_49_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_50 - CAS or consumption cycle count register for client 50.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_50 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_50_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_50_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_50_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_51 - CAS or consumption cycle count register for client 51.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_51 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_51_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_51_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_51_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_52 - CAS or consumption cycle count register for client 52.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_52 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_52_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_52_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_52_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_53 - CAS or consumption cycle count register for client 53.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_53 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_53_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_53_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_53_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_54 - CAS or consumption cycle count register for client 54.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_54 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_54_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_54_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_54_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_55 - CAS or consumption cycle count register for client 55.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_55 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_55_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_55_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_55_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_56 - CAS or consumption cycle count register for client 56.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_56 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_56_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_56_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_56_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_57 - CAS or consumption cycle count register for client 57.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_57 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_57_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_57_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_57_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_58 - CAS or consumption cycle count register for client 58.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_58 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_58_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_58_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_58_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_59 - CAS or consumption cycle count register for client 59.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_59 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_59_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_59_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_59_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_60 - CAS or consumption cycle count register for client 60.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_60 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_60_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_60_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_60_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_61 - CAS or consumption cycle count register for client 61.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_61 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_61_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_61_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_61_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_62 - CAS or consumption cycle count register for client 62.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_62 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_62_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_62_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_62_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_63 - CAS or consumption cycle count register for client 63.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_63 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_63_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_63_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_63_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_64 - CAS or consumption cycle count register for client 64.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_64 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_64_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_64_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_64_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_65 - CAS or consumption cycle count register for client 65.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_65 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_65_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_65_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_65_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_66 - CAS or consumption cycle count register for client 66.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_66 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_66_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_66_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_66_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_67 - CAS or consumption cycle count register for client 67.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_67 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_67_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_67_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_67_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_68 - CAS or consumption cycle count register for client 68.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_68 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_68_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_68_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_68_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_69 - CAS or consumption cycle count register for client 69.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_69 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_69_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_69_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_69_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_70 - CAS or consumption cycle count register for client 70.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_70 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_70_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_70_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_70_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_71 - CAS or consumption cycle count register for client 71.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_71 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_71_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_71_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_71_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_72 - CAS or consumption cycle count register for client 72.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_72 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_72_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_72_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_72_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_73 - CAS or consumption cycle count register for client 73.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_73 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_73_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_73_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_73_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_74 - CAS or consumption cycle count register for client 74.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_74 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_74_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_74_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_74_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_75 - CAS or consumption cycle count register for client 75.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_75 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_75_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_75_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_75_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_76 - CAS or consumption cycle count register for client 76.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_76 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_76_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_76_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_76_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_77 - CAS or consumption cycle count register for client 77.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_77 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_77_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_77_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_77_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_78 - CAS or consumption cycle count register for client 78.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_78 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_78_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_78_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_78_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_79 - CAS or consumption cycle count register for client 79.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_79 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_79_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_79_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_79_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_80 - CAS or consumption cycle count register for client 80.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_80 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_80_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_80_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_80_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_81 - CAS or consumption cycle count register for client 81.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_81 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_81_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_81_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_81_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_82 - CAS or consumption cycle count register for client 82.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_82 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_82_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_82_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_82_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_83 - CAS or consumption cycle count register for client 83.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_83 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_83_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_83_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_83_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_84 - CAS or consumption cycle count register for client 84.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_84 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_84_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_84_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_84_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_85 - CAS or consumption cycle count register for client 85.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_85 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_85_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_85_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_85_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_86 - CAS or consumption cycle count register for client 86.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_86 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_86_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_86_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_86_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_87 - CAS or consumption cycle count register for client 87.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_87 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_87_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_87_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_87_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_88 - CAS or consumption cycle count register for client 88.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_88 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_88_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_88_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_88_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_89 - CAS or consumption cycle count register for client 89.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_89 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_89_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_89_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_89_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_90 - CAS or consumption cycle count register for client 90.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_90 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_90_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_90_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_90_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_91 - CAS or consumption cycle count register for client 91.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_91 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_91_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_91_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_91_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_92 - CAS or consumption cycle count register for client 92.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_92 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_92_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_92_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_92_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_93 - CAS or consumption cycle count register for client 93.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_93 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_93_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_93_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_93_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_94 - CAS or consumption cycle count register for client 94.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_94 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_94_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_94_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_94_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_95 - CAS or consumption cycle count register for client 95.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_95 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_95_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_95_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_95_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_96 - CAS or consumption cycle count register for client 96.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_96 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_96_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_96_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_96_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_97 - CAS or consumption cycle count register for client 97.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_97 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_97_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_97_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_97_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_98 - CAS or consumption cycle count register for client 98.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_98 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_98_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_98_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_98_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_99 - CAS or consumption cycle count register for client 99.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_99 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_99_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_99_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_99_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_100 - CAS or consumption cycle count register for client 100.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_100 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_100_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_100_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_100_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_101 - CAS or consumption cycle count register for client 101.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_101 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_101_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_101_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_101_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_102 - CAS or consumption cycle count register for client 102.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_102 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_102_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_102_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_102_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_103 - CAS or consumption cycle count register for client 103.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_103 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_103_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_103_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_103_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_104 - CAS or consumption cycle count register for client 104.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_104 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_104_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_104_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_104_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_105 - CAS or consumption cycle count register for client 105.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_105 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_105_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_105_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_105_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_106 - CAS or consumption cycle count register for client 106.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_106 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_106_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_106_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_106_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_107 - CAS or consumption cycle count register for client 107.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_107 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_107_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_107_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_107_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_108 - CAS or consumption cycle count register for client 108.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_108 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_108_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_108_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_108_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_109 - CAS or consumption cycle count register for client 109.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_109 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_109_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_109_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_109_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_110 - CAS or consumption cycle count register for client 110.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_110 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_110_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_110_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_110_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_111 - CAS or consumption cycle count register for client 111.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_111 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_111_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_111_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_111_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_112 - CAS or consumption cycle count register for client 112.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_112 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_112_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_112_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_112_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_113 - CAS or consumption cycle count register for client 113.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_113 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_113_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_113_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_113_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_114 - CAS or consumption cycle count register for client 114.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_114 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_114_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_114_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_114_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_115 - CAS or consumption cycle count register for client 115.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_115 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_115_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_115_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_115_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_116 - CAS or consumption cycle count register for client 116.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_116 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_116_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_116_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_116_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_117 - CAS or consumption cycle count register for client 117.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_117 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_117_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_117_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_117_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_118 - CAS or consumption cycle count register for client 118.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_118 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_118_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_118_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_118_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_119 - CAS or consumption cycle count register for client 119.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_119 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_119_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_119_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_119_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_120 - CAS or consumption cycle count register for client 120.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_120 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_120_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_120_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_120_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_121 - CAS or consumption cycle count register for client 121.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_121 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_121_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_121_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_121_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_122 - CAS or consumption cycle count register for client 122.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_122 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_122_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_122_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_122_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_123 - CAS or consumption cycle count register for client 123.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_123 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_123_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_123_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_123_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_124 - CAS or consumption cycle count register for client 124.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_124 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_124_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_124_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_124_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_125 - CAS or consumption cycle count register for client 125.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_125 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_125_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_125_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_125_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_126 - CAS or consumption cycle count register for client 126.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_126 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_126_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_126_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_126_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_127 - CAS or consumption cycle count register for client 127.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_127 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_127_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_127_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_127_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_128 - CAS or consumption cycle count register for client 128.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_128 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_128_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_128_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_128_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_129 - CAS or consumption cycle count register for client 129.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_129 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_129_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_129_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_129_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_130 - CAS or consumption cycle count register for client 130.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_130 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_130_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_130_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_130_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_131 - CAS or consumption cycle count register for client 131.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_131 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_131_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_131_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_131_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_132 - CAS or consumption cycle count register for client 132.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_132 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_132_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_132_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_132_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_133 - CAS or consumption cycle count register for client 133.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_133 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_133_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_133_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_133_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_134 - CAS or consumption cycle count register for client 134.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_134 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_134_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_134_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_134_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_135 - CAS or consumption cycle count register for client 135.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_135 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_135_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_135_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_135_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_136 - CAS or consumption cycle count register for client 136.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_136 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_136_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_136_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_136_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_137 - CAS or consumption cycle count register for client 137.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_137 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_137_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_137_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_137_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_138 - CAS or consumption cycle count register for client 138.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_138 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_138_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_138_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_138_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_139 - CAS or consumption cycle count register for client 139.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_139 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_139_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_139_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_139_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_140 - CAS or consumption cycle count register for client 140.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_140 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_140_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_140_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_140_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_141 - CAS or consumption cycle count register for client 141.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_141 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_141_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_141_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_141_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_142 - CAS or consumption cycle count register for client 142.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_142 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_142_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_142_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_142_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_143 - CAS or consumption cycle count register for client 143.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_143 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_143_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_143_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_143_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_144 - CAS or consumption cycle count register for client 144.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_144 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_144_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_144_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_144_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_145 - CAS or consumption cycle count register for client 145.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_145 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_145_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_145_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_145_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_146 - CAS or consumption cycle count register for client 146.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_146 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_146_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_146_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_146_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_147 - CAS or consumption cycle count register for client 147.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_147 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_147_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_147_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_147_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_148 - CAS or consumption cycle count register for client 148.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_148 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_148_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_148_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_148_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_149 - CAS or consumption cycle count register for client 149.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_149 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_149_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_149_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_149_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_150 - CAS or consumption cycle count register for client 150.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_150 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_150_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_150_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_150_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_151 - CAS or consumption cycle count register for client 151.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_151 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_151_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_151_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_151_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_152 - CAS or consumption cycle count register for client 152.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_152 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_152_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_152_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_152_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_153 - CAS or consumption cycle count register for client 153.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_153 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_153_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_153_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_153_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_154 - CAS or consumption cycle count register for client 154.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_154 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_154_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_154_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_154_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_155 - CAS or consumption cycle count register for client 155.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_155 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_155_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_155_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_155_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_156 - CAS or consumption cycle count register for client 156.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_156 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_156_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_156_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_156_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_157 - CAS or consumption cycle count register for client 157.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_157 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_157_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_157_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_157_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_158 - CAS or consumption cycle count register for client 158.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_158 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_158_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_158_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_158_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_159 - CAS or consumption cycle count register for client 159.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_159 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_159_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_159_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_159_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_160 - CAS or consumption cycle count register for client 160.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_160 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_160_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_160_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_160_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_161 - CAS or consumption cycle count register for client 161.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_161 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_161_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_161_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_161_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_162 - CAS or consumption cycle count register for client 162.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_162 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_162_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_162_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_162_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_163 - CAS or consumption cycle count register for client 163.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_163 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_163_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_163_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_163_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_164 - CAS or consumption cycle count register for client 164.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_164 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_164_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_164_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_164_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_165 - CAS or consumption cycle count register for client 165.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_165 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_165_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_165_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_165_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_166 - CAS or consumption cycle count register for client 166.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_166 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_166_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_166_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_166_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_167 - CAS or consumption cycle count register for client 167.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_167 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_167_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_167_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_167_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_168 - CAS or consumption cycle count register for client 168.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_168 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_168_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_168_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_168_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_169 - CAS or consumption cycle count register for client 169.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_169 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_169_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_169_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_169_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_170 - CAS or consumption cycle count register for client 170.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_170 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_170_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_170_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_170_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_171 - CAS or consumption cycle count register for client 171.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_171 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_171_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_171_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_171_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_172 - CAS or consumption cycle count register for client 172.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_172 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_172_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_172_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_172_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_173 - CAS or consumption cycle count register for client 173.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_173 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_173_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_173_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_173_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_174 - CAS or consumption cycle count register for client 174.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_174 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_174_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_174_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_174_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_175 - CAS or consumption cycle count register for client 175.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_175 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_175_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_175_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_175_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_176 - CAS or consumption cycle count register for client 176.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_176 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_176_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_176_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_176_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_177 - CAS or consumption cycle count register for client 177.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_177 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_177_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_177_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_177_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_178 - CAS or consumption cycle count register for client 178.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_178 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_178_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_178_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_178_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_179 - CAS or consumption cycle count register for client 179.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_179 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_179_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_179_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_179_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_180 - CAS or consumption cycle count register for client 180.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_180 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_180_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_180_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_180_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_181 - CAS or consumption cycle count register for client 181.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_181 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_181_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_181_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_181_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_182 - CAS or consumption cycle count register for client 182.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_182 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_182_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_182_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_182_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_183 - CAS or consumption cycle count register for client 183.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_183 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_183_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_183_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_183_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_184 - CAS or consumption cycle count register for client 184.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_184 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_184_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_184_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_184_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_185 - CAS or consumption cycle count register for client 185.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_185 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_185_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_185_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_185_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_186 - CAS or consumption cycle count register for client 186.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_186 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_186_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_186_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_186_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_187 - CAS or consumption cycle count register for client 187.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_187 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_187_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_187_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_187_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_188 - CAS or consumption cycle count register for client 188.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_188 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_188_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_188_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_188_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_189 - CAS or consumption cycle count register for client 189.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_189 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_189_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_189_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_189_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_190 - CAS or consumption cycle count register for client 190.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_190 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_190_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_190_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_190_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_191 - CAS or consumption cycle count register for client 191.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_191 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_191_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_191_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_191_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_192 - CAS or consumption cycle count register for client 192.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_192 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_192_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_192_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_192_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_193 - CAS or consumption cycle count register for client 193.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_193 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_193_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_193_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_193_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_194 - CAS or consumption cycle count register for client 194.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_194 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_194_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_194_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_194_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_195 - CAS or consumption cycle count register for client 195.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_195 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_195_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_195_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_195_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_196 - CAS or consumption cycle count register for client 196.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_196 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_196_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_196_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_196_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_197 - CAS or consumption cycle count register for client 197.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_197 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_197_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_197_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_197_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_198 - CAS or consumption cycle count register for client 198.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_198 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_198_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_198_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_198_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_199 - CAS or consumption cycle count register for client 199.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_199 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_199_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_199_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_199_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_200 - CAS or consumption cycle count register for client 200.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_200 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_200_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_200_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_200_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_201 - CAS or consumption cycle count register for client 201.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_201 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_201_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_201_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_201_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_202 - CAS or consumption cycle count register for client 202.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_202 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_202_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_202_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_202_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_203 - CAS or consumption cycle count register for client 203.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_203 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_203_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_203_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_203_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_204 - CAS or consumption cycle count register for client 204.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_204 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_204_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_204_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_204_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_205 - CAS or consumption cycle count register for client 205.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_205 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_205_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_205_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_205_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_206 - CAS or consumption cycle count register for client 206.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_206 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_206_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_206_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_206_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_207 - CAS or consumption cycle count register for client 207.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_207 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_207_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_207_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_207_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_208 - CAS or consumption cycle count register for client 208.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_208 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_208_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_208_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_208_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_209 - CAS or consumption cycle count register for client 209.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_209 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_209_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_209_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_209_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_210 - CAS or consumption cycle count register for client 210.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_210 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_210_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_210_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_210_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_211 - CAS or consumption cycle count register for client 211.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_211 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_211_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_211_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_211_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_212 - CAS or consumption cycle count register for client 212.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_212 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_212_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_212_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_212_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_213 - CAS or consumption cycle count register for client 213.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_213 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_213_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_213_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_213_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_214 - CAS or consumption cycle count register for client 214.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_214 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_214_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_214_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_214_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_215 - CAS or consumption cycle count register for client 215.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_215 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_215_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_215_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_215_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_216 - CAS or consumption cycle count register for client 216.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_216 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_216_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_216_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_216_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_217 - CAS or consumption cycle count register for client 217.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_217 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_217_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_217_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_217_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_218 - CAS or consumption cycle count register for client 218.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_218 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_218_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_218_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_218_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_219 - CAS or consumption cycle count register for client 219.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_219 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_219_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_219_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_219_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_220 - CAS or consumption cycle count register for client 220.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_220 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_220_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_220_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_220_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_221 - CAS or consumption cycle count register for client 221.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_221 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_221_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_221_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_221_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_222 - CAS or consumption cycle count register for client 222.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_222 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_222_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_222_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_222_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_223 - CAS or consumption cycle count register for client 223.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_223 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_223_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_223_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_223_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_224 - CAS or consumption cycle count register for client 224.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_224 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_224_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_224_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_224_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_225 - CAS or consumption cycle count register for client 225.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_225 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_225_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_225_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_225_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_226 - CAS or consumption cycle count register for client 226.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_226 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_226_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_226_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_226_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_227 - CAS or consumption cycle count register for client 227.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_227 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_227_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_227_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_227_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_228 - CAS or consumption cycle count register for client 228.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_228 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_228_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_228_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_228_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_229 - CAS or consumption cycle count register for client 229.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_229 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_229_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_229_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_229_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_230 - CAS or consumption cycle count register for client 230.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_230 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_230_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_230_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_230_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_231 - CAS or consumption cycle count register for client 231.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_231 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_231_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_231_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_231_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_232 - CAS or consumption cycle count register for client 232.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_232 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_232_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_232_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_232_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_233 - CAS or consumption cycle count register for client 233.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_233 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_233_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_233_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_233_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_234 - CAS or consumption cycle count register for client 234.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_234 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_234_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_234_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_234_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_235 - CAS or consumption cycle count register for client 235.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_235 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_235_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_235_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_235_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_236 - CAS or consumption cycle count register for client 236.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_236 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_236_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_236_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_236_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_237 - CAS or consumption cycle count register for client 237.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_237 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_237_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_237_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_237_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_238 - CAS or consumption cycle count register for client 238.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_238 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_238_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_238_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_238_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_239 - CAS or consumption cycle count register for client 239.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_239 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_239_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_239_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_239_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_240 - CAS or consumption cycle count register for client 240.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_240 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_240_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_240_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_240_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_241 - CAS or consumption cycle count register for client 241.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_241 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_241_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_241_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_241_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_242 - CAS or consumption cycle count register for client 242.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_242 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_242_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_242_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_242_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_243 - CAS or consumption cycle count register for client 243.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_243 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_243_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_243_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_243_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_244 - CAS or consumption cycle count register for client 244.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_244 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_244_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_244_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_244_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_245 - CAS or consumption cycle count register for client 245.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_245 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_245_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_245_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_245_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_246 - CAS or consumption cycle count register for client 246.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_246 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_246_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_246_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_246_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_247 - CAS or consumption cycle count register for client 247.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_247 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_247_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_247_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_247_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_248 - CAS or consumption cycle count register for client 248.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_248 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_248_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_248_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_248_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_249 - CAS or consumption cycle count register for client 249.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_249 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_249_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_249_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_249_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_250 - CAS or consumption cycle count register for client 250.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_250 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_250_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_250_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_250_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_251 - CAS or consumption cycle count register for client 251.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_251 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_251_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_251_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_251_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_252 - CAS or consumption cycle count register for client 252.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_252 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_252_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_252_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_252_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_253 - CAS or consumption cycle count register for client 253.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_253 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_253_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_253_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_253_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_254 - CAS or consumption cycle count register for client 254.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_254 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_254_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_254_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_254_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *STAT_CAS_CLIENT_255 - CAS or consumption cycle count register for client 255.
- ***************************************************************************/
-/* MEMC_DDR_0 :: STAT_CAS_CLIENT_255 :: COUNT [31:00] */
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_255_COUNT_MASK 0xffffffff
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_255_COUNT_SHIFT 0
-#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_255_COUNT_DEFAULT 0x00000000
-
-#endif /* #ifndef BCHP_MEMC_DDR_0_H__ */
-
-/* End of File */
diff --git a/include/linux/brcmstb/7439a0/bchp_moca_hostmisc.h b/include/linux/brcmstb/7439a0/bchp_moca_hostmisc.h
deleted file mode 100644
index 3e5a892..0000000
--- a/include/linux/brcmstb/7439a0/bchp_moca_hostmisc.h
+++ /dev/null
@@ -1,511 +0,0 @@
-/***************************************************************************
- * Copyright (c) 1999-2012, Broadcom Corporation
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
- *
- * Module Description:
- * DO NOT EDIT THIS FILE DIRECTLY
- *
- * This module was generated magically with RDB from a source description
- * file. You must edit the source file for changes to be made to this file.
- *
- *
- * Date: Generated on Wed Oct 17 03:11:32 2012
- * MD5 Checksum d41d8cd98f00b204e9800998ecf8427e
- *
- * Compiled with: RDB Utility combo_header.pl
- * RDB Parser 3.0
- * unknown unknown
- * Perl Interpreter 5.008008
- * Operating System linux
- *
- * Revision History:
- *
- * $brcm_Log: $
- *
- ***************************************************************************/
-
-#ifndef BCHP_MOCA_HOSTMISC_H__
-#define BCHP_MOCA_HOSTMISC_H__
-
-/***************************************************************************
- *MOCA_HOSTMISC - MOCA_HOSTMISC registers
- ***************************************************************************/
-#define BCHP_MOCA_HOSTMISC_MISC_CTRL 0x00fffd00 /* Moca Software Reset */
-#define BCHP_MOCA_HOSTMISC_SCRATCH 0x00fffd04 /* Moca Scratch Register */
-#define BCHP_MOCA_HOSTMISC_VERSION 0x00fffd08 /* MoCA version register */
-#define BCHP_MOCA_HOSTMISC_H2M_INT_TRIG 0x00fffd0c /* Host-to-MoCA Interrupt Trigger */
-#define BCHP_MOCA_HOSTMISC_WAKEUP 0x00fffd10 /* Host-to-MoCA Wakeup Interrupt */
-#define BCHP_MOCA_HOSTMISC_SUBSYS_CFG 0x00fffd14 /* Moca Subsystem configuration */
-#define BCHP_MOCA_HOSTMISC_H2M_MMP_OUTBOX_0 0x00fffd18 /* Host to MoCA MMP outbox registes , register set index 0. */
-#define BCHP_MOCA_HOSTMISC_H2M_MMP_OUTBOX_1 0x00fffd1c /* Host to MoCA MMP outbox registes , register set index 1. */
-#define BCHP_MOCA_HOSTMISC_H2M_MMP_OUTBOX_2 0x00fffd20 /* Host to MoCA MMP outbox registes , register set index 2. */
-#define BCHP_MOCA_HOSTMISC_H2M_MMP_OUTBOX_3 0x00fffd24 /* Host to MoCA MMP outbox registes , register set index 3. */
-#define BCHP_MOCA_HOSTMISC_H2M_MMP_OUTBOX_4 0x00fffd28 /* Host to MoCA MMP outbox registes , register set index 4. */
-#define BCHP_MOCA_HOSTMISC_H2M_MMP_OUTBOX_5 0x00fffd2c /* Host to MoCA MMP outbox registes , register set index 5. */
-#define BCHP_MOCA_HOSTMISC_H2M_MMP_OUTBOX_6 0x00fffd30 /* Host to MoCA MMP outbox registes , register set index 6. */
-#define BCHP_MOCA_HOSTMISC_H2M_MMP_OUTBOX_7 0x00fffd34 /* Host to MoCA MMP outbox registes , register set index 7. */
-#define BCHP_MOCA_HOSTMISC_H2M_MMP_OUTBOX_8 0x00fffd38 /* Host to MoCA MMP outbox registes , register set index 8. */
-#define BCHP_MOCA_HOSTMISC_H2M_MMP_OUTBOX_9 0x00fffd3c /* Host to MoCA MMP outbox registes , register set index 9. */
-#define BCHP_MOCA_HOSTMISC_H2M_MMP_OUTBOX_10 0x00fffd40 /* Host to MoCA MMP outbox registes , register set index 10. */
-#define BCHP_MOCA_HOSTMISC_H2M_MMP_OUTBOX_11 0x00fffd44 /* Host to MoCA MMP outbox registes , register set index 11. */
-#define BCHP_MOCA_HOSTMISC_H2M_MMP_OUTBOX_12 0x00fffd48 /* Host to MoCA MMP outbox registes , register set index 12. */
-#define BCHP_MOCA_HOSTMISC_H2M_MMP_OUTBOX_13 0x00fffd4c /* Host to MoCA MMP outbox registes , register set index 13. */
-#define BCHP_MOCA_HOSTMISC_H2M_MMP_OUTBOX_14 0x00fffd50 /* Host to MoCA MMP outbox registes , register set index 14. */
-#define BCHP_MOCA_HOSTMISC_H2M_MMP_OUTBOX_15 0x00fffd54 /* Host to MoCA MMP outbox registes , register set index 15. */
-#define BCHP_MOCA_HOSTMISC_M2H_MMP_INBOX_0 0x00fffd58 /* MoCA to Host MMP inbox registers , register set index 0. */
-#define BCHP_MOCA_HOSTMISC_M2H_MMP_INBOX_1 0x00fffd5c /* MoCA to Host MMP inbox registers , register set index 1. */
-#define BCHP_MOCA_HOSTMISC_M2H_MMP_INBOX_2 0x00fffd60 /* MoCA to Host MMP inbox registers , register set index 2. */
-#define BCHP_MOCA_HOSTMISC_M2H_MMP_INBOX_3 0x00fffd64 /* MoCA to Host MMP inbox registers , register set index 3. */
-#define BCHP_MOCA_HOSTMISC_M2H_MMP_INBOX_4 0x00fffd68 /* MoCA to Host MMP inbox registers , register set index 4. */
-#define BCHP_MOCA_HOSTMISC_M2H_MMP_INBOX_5 0x00fffd6c /* MoCA to Host MMP inbox registers , register set index 5. */
-#define BCHP_MOCA_HOSTMISC_M2H_MMP_INBOX_6 0x00fffd70 /* MoCA to Host MMP inbox registers , register set index 6. */
-#define BCHP_MOCA_HOSTMISC_M2H_MMP_INBOX_7 0x00fffd74 /* MoCA to Host MMP inbox registers , register set index 7. */
-#define BCHP_MOCA_HOSTMISC_M2H_MMP_INBOX_8 0x00fffd78 /* MoCA to Host MMP inbox registers , register set index 8. */
-#define BCHP_MOCA_HOSTMISC_M2H_MMP_INBOX_9 0x00fffd7c /* MoCA to Host MMP inbox registers , register set index 9. */
-#define BCHP_MOCA_HOSTMISC_M2H_MMP_INBOX_10 0x00fffd80 /* MoCA to Host MMP inbox registers , register set index 10. */
-#define BCHP_MOCA_HOSTMISC_M2H_MMP_INBOX_11 0x00fffd84 /* MoCA to Host MMP inbox registers , register set index 11. */
-#define BCHP_MOCA_HOSTMISC_M2H_MMP_INBOX_12 0x00fffd88 /* MoCA to Host MMP inbox registers , register set index 12. */
-#define BCHP_MOCA_HOSTMISC_M2H_MMP_INBOX_13 0x00fffd8c /* MoCA to Host MMP inbox registers , register set index 13. */
-#define BCHP_MOCA_HOSTMISC_M2H_MMP_INBOX_14 0x00fffd90 /* MoCA to Host MMP inbox registers , register set index 14. */
-#define BCHP_MOCA_HOSTMISC_M2H_MMP_INBOX_15 0x00fffd94 /* MoCA to Host MMP inbox registers , register set index 15. */
-#define BCHP_MOCA_HOSTMISC_DMPG_CHAINS_STATUS 0x00fffd98 /* "MoCA dynamic memory power gating chain power up (bit per chain),Active when moca_dmpg_gisb_en is high,0: Chain is on,1: Chain is off" */
-#define BCHP_MOCA_HOSTMISC_DMPG_CHAINS_PWR_UP 0x00fffd9c /* "MoCA dynamic memory power gating chain status (bit per chain),0: Power down chain,1: Power up chain" */
-
-/***************************************************************************
- *MISC_CTRL - Moca Software Reset
- ***************************************************************************/
-/* MOCA_HOSTMISC :: MISC_CTRL :: spare_ctrl [31:17] */
-#define BCHP_MOCA_HOSTMISC_MISC_CTRL_spare_ctrl_MASK 0xfffe0000
-#define BCHP_MOCA_HOSTMISC_MISC_CTRL_spare_ctrl_SHIFT 17
-#define BCHP_MOCA_HOSTMISC_MISC_CTRL_spare_ctrl_DEFAULT 0x00007fff
-
-/* MOCA_HOSTMISC :: MISC_CTRL :: moca_dmpg_sel [16:16] */
-#define BCHP_MOCA_HOSTMISC_MISC_CTRL_moca_dmpg_sel_MASK 0x00010000
-#define BCHP_MOCA_HOSTMISC_MISC_CTRL_moca_dmpg_sel_SHIFT 16
-#define BCHP_MOCA_HOSTMISC_MISC_CTRL_moca_dmpg_sel_DEFAULT 0x00000000
-
-/* MOCA_HOSTMISC :: MISC_CTRL :: moca_dmpg_en [15:15] */
-#define BCHP_MOCA_HOSTMISC_MISC_CTRL_moca_dmpg_en_MASK 0x00008000
-#define BCHP_MOCA_HOSTMISC_MISC_CTRL_moca_dmpg_en_SHIFT 15
-#define BCHP_MOCA_HOSTMISC_MISC_CTRL_moca_dmpg_en_DEFAULT 0x00000001
-
-/* MOCA_HOSTMISC :: MISC_CTRL :: spare_status [14:10] */
-#define BCHP_MOCA_HOSTMISC_MISC_CTRL_spare_status_MASK 0x00007c00
-#define BCHP_MOCA_HOSTMISC_MISC_CTRL_spare_status_SHIFT 10
-#define BCHP_MOCA_HOSTMISC_MISC_CTRL_spare_status_DEFAULT 0x0000001f
-
-/* MOCA_HOSTMISC :: MISC_CTRL :: moca_phy1_disable_clk [09:09] */
-#define BCHP_MOCA_HOSTMISC_MISC_CTRL_moca_phy1_disable_clk_MASK 0x00000200
-#define BCHP_MOCA_HOSTMISC_MISC_CTRL_moca_phy1_disable_clk_SHIFT 9
-#define BCHP_MOCA_HOSTMISC_MISC_CTRL_moca_phy1_disable_clk_DEFAULT 0x00000000
-
-/* MOCA_HOSTMISC :: MISC_CTRL :: moca_phy0_disable_clk [08:08] */
-#define BCHP_MOCA_HOSTMISC_MISC_CTRL_moca_phy0_disable_clk_MASK 0x00000100
-#define BCHP_MOCA_HOSTMISC_MISC_CTRL_moca_phy0_disable_clk_SHIFT 8
-#define BCHP_MOCA_HOSTMISC_MISC_CTRL_moca_phy0_disable_clk_DEFAULT 0x00000000
-
-/* MOCA_HOSTMISC :: MISC_CTRL :: moca_disable_clocks [07:07] */
-#define BCHP_MOCA_HOSTMISC_MISC_CTRL_moca_disable_clocks_MASK 0x00000080
-#define BCHP_MOCA_HOSTMISC_MISC_CTRL_moca_disable_clocks_SHIFT 7
-#define BCHP_MOCA_HOSTMISC_MISC_CTRL_moca_disable_clocks_DEFAULT 0x00000000
-
-/* MOCA_HOSTMISC :: MISC_CTRL :: spare_reset [06:06] */
-#define BCHP_MOCA_HOSTMISC_MISC_CTRL_spare_reset_MASK 0x00000040
-#define BCHP_MOCA_HOSTMISC_MISC_CTRL_spare_reset_SHIFT 6
-#define BCHP_MOCA_HOSTMISC_MISC_CTRL_spare_reset_DEFAULT 0x00000001
-
-/* MOCA_HOSTMISC :: MISC_CTRL :: moca_phy1_reset [05:05] */
-#define BCHP_MOCA_HOSTMISC_MISC_CTRL_moca_phy1_reset_MASK 0x00000020
-#define BCHP_MOCA_HOSTMISC_MISC_CTRL_moca_phy1_reset_SHIFT 5
-#define BCHP_MOCA_HOSTMISC_MISC_CTRL_moca_phy1_reset_DEFAULT 0x00000000
-
-/* MOCA_HOSTMISC :: MISC_CTRL :: moca_phy0_reset [04:04] */
-#define BCHP_MOCA_HOSTMISC_MISC_CTRL_moca_phy0_reset_MASK 0x00000010
-#define BCHP_MOCA_HOSTMISC_MISC_CTRL_moca_phy0_reset_SHIFT 4
-#define BCHP_MOCA_HOSTMISC_MISC_CTRL_moca_phy0_reset_DEFAULT 0x00000000
-
-/* MOCA_HOSTMISC :: MISC_CTRL :: moca_gmii_sw_init [03:03] */
-#define BCHP_MOCA_HOSTMISC_MISC_CTRL_moca_gmii_sw_init_MASK 0x00000008
-#define BCHP_MOCA_HOSTMISC_MISC_CTRL_moca_gmii_sw_init_SHIFT 3
-#define BCHP_MOCA_HOSTMISC_MISC_CTRL_moca_gmii_sw_init_DEFAULT 0x00000000
-
-/* MOCA_HOSTMISC :: MISC_CTRL :: moca_cpu_l_reset [02:02] */
-#define BCHP_MOCA_HOSTMISC_MISC_CTRL_moca_cpu_l_reset_MASK 0x00000004
-#define BCHP_MOCA_HOSTMISC_MISC_CTRL_moca_cpu_l_reset_SHIFT 2
-#define BCHP_MOCA_HOSTMISC_MISC_CTRL_moca_cpu_l_reset_DEFAULT 0x00000001
-
-/* MOCA_HOSTMISC :: MISC_CTRL :: moca_sys_reset [01:01] */
-#define BCHP_MOCA_HOSTMISC_MISC_CTRL_moca_sys_reset_MASK 0x00000002
-#define BCHP_MOCA_HOSTMISC_MISC_CTRL_moca_sys_reset_SHIFT 1
-#define BCHP_MOCA_HOSTMISC_MISC_CTRL_moca_sys_reset_DEFAULT 0x00000001
-
-/* MOCA_HOSTMISC :: MISC_CTRL :: moca_cpu_h_reset [00:00] */
-#define BCHP_MOCA_HOSTMISC_MISC_CTRL_moca_cpu_h_reset_MASK 0x00000001
-#define BCHP_MOCA_HOSTMISC_MISC_CTRL_moca_cpu_h_reset_SHIFT 0
-#define BCHP_MOCA_HOSTMISC_MISC_CTRL_moca_cpu_h_reset_DEFAULT 0x00000001
-
-/***************************************************************************
- *SCRATCH - Moca Scratch Register
- ***************************************************************************/
-/* MOCA_HOSTMISC :: SCRATCH :: value [31:00] */
-#define BCHP_MOCA_HOSTMISC_SCRATCH_value_MASK 0xffffffff
-#define BCHP_MOCA_HOSTMISC_SCRATCH_value_SHIFT 0
-#define BCHP_MOCA_HOSTMISC_SCRATCH_value_DEFAULT 0x00000000
-
-/***************************************************************************
- *VERSION - MoCA version register
- ***************************************************************************/
-/* MOCA_HOSTMISC :: VERSION :: moca_id [31:16] */
-#define BCHP_MOCA_HOSTMISC_VERSION_moca_id_MASK 0xffff0000
-#define BCHP_MOCA_HOSTMISC_VERSION_moca_id_SHIFT 16
-#define BCHP_MOCA_HOSTMISC_VERSION_moca_id_DEFAULT 0x00006622
-
-/* MOCA_HOSTMISC :: VERSION :: moca_spec_ver [15:12] */
-#define BCHP_MOCA_HOSTMISC_VERSION_moca_spec_ver_MASK 0x0000f000
-#define BCHP_MOCA_HOSTMISC_VERSION_moca_spec_ver_SHIFT 12
-#define BCHP_MOCA_HOSTMISC_VERSION_moca_spec_ver_DEFAULT 0x00000003
-
-/* MOCA_HOSTMISC :: VERSION :: core_version [11:08] */
-#define BCHP_MOCA_HOSTMISC_VERSION_core_version_MASK 0x00000f00
-#define BCHP_MOCA_HOSTMISC_VERSION_core_version_SHIFT 8
-#define BCHP_MOCA_HOSTMISC_VERSION_core_version_DEFAULT 0x00000000
-
-/* MOCA_HOSTMISC :: VERSION :: core_revision [07:04] */
-#define BCHP_MOCA_HOSTMISC_VERSION_core_revision_MASK 0x000000f0
-#define BCHP_MOCA_HOSTMISC_VERSION_core_revision_SHIFT 4
-#define BCHP_MOCA_HOSTMISC_VERSION_core_revision_DEFAULT 0x00000000
-
-/* MOCA_HOSTMISC :: VERSION :: core_mask [03:00] */
-#define BCHP_MOCA_HOSTMISC_VERSION_core_mask_MASK 0x0000000f
-#define BCHP_MOCA_HOSTMISC_VERSION_core_mask_SHIFT 0
-#define BCHP_MOCA_HOSTMISC_VERSION_core_mask_DEFAULT 0x00000000
-
-/***************************************************************************
- *H2M_INT_TRIG - Host-to-MoCA Interrupt Trigger
- ***************************************************************************/
-/* MOCA_HOSTMISC :: H2M_INT_TRIG :: reserved0 [31:08] */
-#define BCHP_MOCA_HOSTMISC_H2M_INT_TRIG_reserved0_MASK 0xffffff00
-#define BCHP_MOCA_HOSTMISC_H2M_INT_TRIG_reserved0_SHIFT 8
-
-/* MOCA_HOSTMISC :: H2M_INT_TRIG :: INT_TRIG [07:00] */
-#define BCHP_MOCA_HOSTMISC_H2M_INT_TRIG_INT_TRIG_MASK 0x000000ff
-#define BCHP_MOCA_HOSTMISC_H2M_INT_TRIG_INT_TRIG_SHIFT 0
-#define BCHP_MOCA_HOSTMISC_H2M_INT_TRIG_INT_TRIG_DEFAULT 0x00000000
-
-/***************************************************************************
- *WAKEUP - Host-to-MoCA Wakeup Interrupt
- ***************************************************************************/
-/* MOCA_HOSTMISC :: WAKEUP :: reserved0 [31:02] */
-#define BCHP_MOCA_HOSTMISC_WAKEUP_reserved0_MASK 0xfffffffc
-#define BCHP_MOCA_HOSTMISC_WAKEUP_reserved0_SHIFT 2
-
-/* MOCA_HOSTMISC :: WAKEUP :: cpu_l_wakeup_int [01:01] */
-#define BCHP_MOCA_HOSTMISC_WAKEUP_cpu_l_wakeup_int_MASK 0x00000002
-#define BCHP_MOCA_HOSTMISC_WAKEUP_cpu_l_wakeup_int_SHIFT 1
-#define BCHP_MOCA_HOSTMISC_WAKEUP_cpu_l_wakeup_int_DEFAULT 0x00000000
-
-/* MOCA_HOSTMISC :: WAKEUP :: cpu_h_wakeup_int [00:00] */
-#define BCHP_MOCA_HOSTMISC_WAKEUP_cpu_h_wakeup_int_MASK 0x00000001
-#define BCHP_MOCA_HOSTMISC_WAKEUP_cpu_h_wakeup_int_SHIFT 0
-#define BCHP_MOCA_HOSTMISC_WAKEUP_cpu_h_wakeup_int_DEFAULT 0x00000000
-
-/***************************************************************************
- *SUBSYS_CFG - Moca Subsystem configuration
- ***************************************************************************/
-/* MOCA_HOSTMISC :: SUBSYS_CFG :: spare_cfg [31:01] */
-#define BCHP_MOCA_HOSTMISC_SUBSYS_CFG_spare_cfg_MASK 0xfffffffe
-#define BCHP_MOCA_HOSTMISC_SUBSYS_CFG_spare_cfg_SHIFT 1
-#define BCHP_MOCA_HOSTMISC_SUBSYS_CFG_spare_cfg_DEFAULT 0x00000000
-
-/* MOCA_HOSTMISC :: SUBSYS_CFG :: moca_arb_rr_sel [00:00] */
-#define BCHP_MOCA_HOSTMISC_SUBSYS_CFG_moca_arb_rr_sel_MASK 0x00000001
-#define BCHP_MOCA_HOSTMISC_SUBSYS_CFG_moca_arb_rr_sel_SHIFT 0
-#define BCHP_MOCA_HOSTMISC_SUBSYS_CFG_moca_arb_rr_sel_DEFAULT 0x00000001
-
-/***************************************************************************
- *H2M_MMP_OUTBOX_0 - Host to MoCA MMP outbox registes , register set index 0.
- ***************************************************************************/
-/* MOCA_HOSTMISC :: H2M_MMP_OUTBOX_0 :: m2h_mmp_outbox [31:00] */
-#define BCHP_MOCA_HOSTMISC_H2M_MMP_OUTBOX_0_m2h_mmp_outbox_MASK 0xffffffff
-#define BCHP_MOCA_HOSTMISC_H2M_MMP_OUTBOX_0_m2h_mmp_outbox_SHIFT 0
-#define BCHP_MOCA_HOSTMISC_H2M_MMP_OUTBOX_0_m2h_mmp_outbox_DEFAULT 0x00000000
-
-/***************************************************************************
- *H2M_MMP_OUTBOX_1 - Host to MoCA MMP outbox registes , register set index 1.
- ***************************************************************************/
-/* MOCA_HOSTMISC :: H2M_MMP_OUTBOX_1 :: m2h_mmp_outbox [31:00] */
-#define BCHP_MOCA_HOSTMISC_H2M_MMP_OUTBOX_1_m2h_mmp_outbox_MASK 0xffffffff
-#define BCHP_MOCA_HOSTMISC_H2M_MMP_OUTBOX_1_m2h_mmp_outbox_SHIFT 0
-#define BCHP_MOCA_HOSTMISC_H2M_MMP_OUTBOX_1_m2h_mmp_outbox_DEFAULT 0x00000000
-
-/***************************************************************************
- *H2M_MMP_OUTBOX_2 - Host to MoCA MMP outbox registes , register set index 2.
- ***************************************************************************/
-/* MOCA_HOSTMISC :: H2M_MMP_OUTBOX_2 :: m2h_mmp_outbox [31:00] */
-#define BCHP_MOCA_HOSTMISC_H2M_MMP_OUTBOX_2_m2h_mmp_outbox_MASK 0xffffffff
-#define BCHP_MOCA_HOSTMISC_H2M_MMP_OUTBOX_2_m2h_mmp_outbox_SHIFT 0
-#define BCHP_MOCA_HOSTMISC_H2M_MMP_OUTBOX_2_m2h_mmp_outbox_DEFAULT 0x00000000
-
-/***************************************************************************
- *H2M_MMP_OUTBOX_3 - Host to MoCA MMP outbox registes , register set index 3.
- ***************************************************************************/
-/* MOCA_HOSTMISC :: H2M_MMP_OUTBOX_3 :: m2h_mmp_outbox [31:00] */
-#define BCHP_MOCA_HOSTMISC_H2M_MMP_OUTBOX_3_m2h_mmp_outbox_MASK 0xffffffff
-#define BCHP_MOCA_HOSTMISC_H2M_MMP_OUTBOX_3_m2h_mmp_outbox_SHIFT 0
-#define BCHP_MOCA_HOSTMISC_H2M_MMP_OUTBOX_3_m2h_mmp_outbox_DEFAULT 0x00000000
-
-/***************************************************************************
- *H2M_MMP_OUTBOX_4 - Host to MoCA MMP outbox registes , register set index 4.
- ***************************************************************************/
-/* MOCA_HOSTMISC :: H2M_MMP_OUTBOX_4 :: m2h_mmp_outbox [31:00] */
-#define BCHP_MOCA_HOSTMISC_H2M_MMP_OUTBOX_4_m2h_mmp_outbox_MASK 0xffffffff
-#define BCHP_MOCA_HOSTMISC_H2M_MMP_OUTBOX_4_m2h_mmp_outbox_SHIFT 0
-#define BCHP_MOCA_HOSTMISC_H2M_MMP_OUTBOX_4_m2h_mmp_outbox_DEFAULT 0x00000000
-
-/***************************************************************************
- *H2M_MMP_OUTBOX_5 - Host to MoCA MMP outbox registes , register set index 5.
- ***************************************************************************/
-/* MOCA_HOSTMISC :: H2M_MMP_OUTBOX_5 :: m2h_mmp_outbox [31:00] */
-#define BCHP_MOCA_HOSTMISC_H2M_MMP_OUTBOX_5_m2h_mmp_outbox_MASK 0xffffffff
-#define BCHP_MOCA_HOSTMISC_H2M_MMP_OUTBOX_5_m2h_mmp_outbox_SHIFT 0
-#define BCHP_MOCA_HOSTMISC_H2M_MMP_OUTBOX_5_m2h_mmp_outbox_DEFAULT 0x00000000
-
-/***************************************************************************
- *H2M_MMP_OUTBOX_6 - Host to MoCA MMP outbox registes , register set index 6.
- ***************************************************************************/
-/* MOCA_HOSTMISC :: H2M_MMP_OUTBOX_6 :: m2h_mmp_outbox [31:00] */
-#define BCHP_MOCA_HOSTMISC_H2M_MMP_OUTBOX_6_m2h_mmp_outbox_MASK 0xffffffff
-#define BCHP_MOCA_HOSTMISC_H2M_MMP_OUTBOX_6_m2h_mmp_outbox_SHIFT 0
-#define BCHP_MOCA_HOSTMISC_H2M_MMP_OUTBOX_6_m2h_mmp_outbox_DEFAULT 0x00000000
-
-/***************************************************************************
- *H2M_MMP_OUTBOX_7 - Host to MoCA MMP outbox registes , register set index 7.
- ***************************************************************************/
-/* MOCA_HOSTMISC :: H2M_MMP_OUTBOX_7 :: m2h_mmp_outbox [31:00] */
-#define BCHP_MOCA_HOSTMISC_H2M_MMP_OUTBOX_7_m2h_mmp_outbox_MASK 0xffffffff
-#define BCHP_MOCA_HOSTMISC_H2M_MMP_OUTBOX_7_m2h_mmp_outbox_SHIFT 0
-#define BCHP_MOCA_HOSTMISC_H2M_MMP_OUTBOX_7_m2h_mmp_outbox_DEFAULT 0x00000000
-
-/***************************************************************************
- *H2M_MMP_OUTBOX_8 - Host to MoCA MMP outbox registes , register set index 8.
- ***************************************************************************/
-/* MOCA_HOSTMISC :: H2M_MMP_OUTBOX_8 :: m2h_mmp_outbox [31:00] */
-#define BCHP_MOCA_HOSTMISC_H2M_MMP_OUTBOX_8_m2h_mmp_outbox_MASK 0xffffffff
-#define BCHP_MOCA_HOSTMISC_H2M_MMP_OUTBOX_8_m2h_mmp_outbox_SHIFT 0
-#define BCHP_MOCA_HOSTMISC_H2M_MMP_OUTBOX_8_m2h_mmp_outbox_DEFAULT 0x00000000
-
-/***************************************************************************
- *H2M_MMP_OUTBOX_9 - Host to MoCA MMP outbox registes , register set index 9.
- ***************************************************************************/
-/* MOCA_HOSTMISC :: H2M_MMP_OUTBOX_9 :: m2h_mmp_outbox [31:00] */
-#define BCHP_MOCA_HOSTMISC_H2M_MMP_OUTBOX_9_m2h_mmp_outbox_MASK 0xffffffff
-#define BCHP_MOCA_HOSTMISC_H2M_MMP_OUTBOX_9_m2h_mmp_outbox_SHIFT 0
-#define BCHP_MOCA_HOSTMISC_H2M_MMP_OUTBOX_9_m2h_mmp_outbox_DEFAULT 0x00000000
-
-/***************************************************************************
- *H2M_MMP_OUTBOX_10 - Host to MoCA MMP outbox registes , register set index 10.
- ***************************************************************************/
-/* MOCA_HOSTMISC :: H2M_MMP_OUTBOX_10 :: m2h_mmp_outbox [31:00] */
-#define BCHP_MOCA_HOSTMISC_H2M_MMP_OUTBOX_10_m2h_mmp_outbox_MASK 0xffffffff
-#define BCHP_MOCA_HOSTMISC_H2M_MMP_OUTBOX_10_m2h_mmp_outbox_SHIFT 0
-#define BCHP_MOCA_HOSTMISC_H2M_MMP_OUTBOX_10_m2h_mmp_outbox_DEFAULT 0x00000000
-
-/***************************************************************************
- *H2M_MMP_OUTBOX_11 - Host to MoCA MMP outbox registes , register set index 11.
- ***************************************************************************/
-/* MOCA_HOSTMISC :: H2M_MMP_OUTBOX_11 :: m2h_mmp_outbox [31:00] */
-#define BCHP_MOCA_HOSTMISC_H2M_MMP_OUTBOX_11_m2h_mmp_outbox_MASK 0xffffffff
-#define BCHP_MOCA_HOSTMISC_H2M_MMP_OUTBOX_11_m2h_mmp_outbox_SHIFT 0
-#define BCHP_MOCA_HOSTMISC_H2M_MMP_OUTBOX_11_m2h_mmp_outbox_DEFAULT 0x00000000
-
-/***************************************************************************
- *H2M_MMP_OUTBOX_12 - Host to MoCA MMP outbox registes , register set index 12.
- ***************************************************************************/
-/* MOCA_HOSTMISC :: H2M_MMP_OUTBOX_12 :: m2h_mmp_outbox [31:00] */
-#define BCHP_MOCA_HOSTMISC_H2M_MMP_OUTBOX_12_m2h_mmp_outbox_MASK 0xffffffff
-#define BCHP_MOCA_HOSTMISC_H2M_MMP_OUTBOX_12_m2h_mmp_outbox_SHIFT 0
-#define BCHP_MOCA_HOSTMISC_H2M_MMP_OUTBOX_12_m2h_mmp_outbox_DEFAULT 0x00000000
-
-/***************************************************************************
- *H2M_MMP_OUTBOX_13 - Host to MoCA MMP outbox registes , register set index 13.
- ***************************************************************************/
-/* MOCA_HOSTMISC :: H2M_MMP_OUTBOX_13 :: m2h_mmp_outbox [31:00] */
-#define BCHP_MOCA_HOSTMISC_H2M_MMP_OUTBOX_13_m2h_mmp_outbox_MASK 0xffffffff
-#define BCHP_MOCA_HOSTMISC_H2M_MMP_OUTBOX_13_m2h_mmp_outbox_SHIFT 0
-#define BCHP_MOCA_HOSTMISC_H2M_MMP_OUTBOX_13_m2h_mmp_outbox_DEFAULT 0x00000000
-
-/***************************************************************************
- *H2M_MMP_OUTBOX_14 - Host to MoCA MMP outbox registes , register set index 14.
- ***************************************************************************/
-/* MOCA_HOSTMISC :: H2M_MMP_OUTBOX_14 :: m2h_mmp_outbox [31:00] */
-#define BCHP_MOCA_HOSTMISC_H2M_MMP_OUTBOX_14_m2h_mmp_outbox_MASK 0xffffffff
-#define BCHP_MOCA_HOSTMISC_H2M_MMP_OUTBOX_14_m2h_mmp_outbox_SHIFT 0
-#define BCHP_MOCA_HOSTMISC_H2M_MMP_OUTBOX_14_m2h_mmp_outbox_DEFAULT 0x00000000
-
-/***************************************************************************
- *H2M_MMP_OUTBOX_15 - Host to MoCA MMP outbox registes , register set index 15.
- ***************************************************************************/
-/* MOCA_HOSTMISC :: H2M_MMP_OUTBOX_15 :: m2h_mmp_outbox [31:00] */
-#define BCHP_MOCA_HOSTMISC_H2M_MMP_OUTBOX_15_m2h_mmp_outbox_MASK 0xffffffff
-#define BCHP_MOCA_HOSTMISC_H2M_MMP_OUTBOX_15_m2h_mmp_outbox_SHIFT 0
-#define BCHP_MOCA_HOSTMISC_H2M_MMP_OUTBOX_15_m2h_mmp_outbox_DEFAULT 0x00000000
-
-/***************************************************************************
- *M2H_MMP_INBOX_0 - MoCA to Host MMP inbox registers , register set index 0.
- ***************************************************************************/
-/* MOCA_HOSTMISC :: M2H_MMP_INBOX_0 :: h2m_mmp_inbox [31:00] */
-#define BCHP_MOCA_HOSTMISC_M2H_MMP_INBOX_0_h2m_mmp_inbox_MASK 0xffffffff
-#define BCHP_MOCA_HOSTMISC_M2H_MMP_INBOX_0_h2m_mmp_inbox_SHIFT 0
-#define BCHP_MOCA_HOSTMISC_M2H_MMP_INBOX_0_h2m_mmp_inbox_DEFAULT 0x00000000
-
-/***************************************************************************
- *M2H_MMP_INBOX_1 - MoCA to Host MMP inbox registers , register set index 1.
- ***************************************************************************/
-/* MOCA_HOSTMISC :: M2H_MMP_INBOX_1 :: h2m_mmp_inbox [31:00] */
-#define BCHP_MOCA_HOSTMISC_M2H_MMP_INBOX_1_h2m_mmp_inbox_MASK 0xffffffff
-#define BCHP_MOCA_HOSTMISC_M2H_MMP_INBOX_1_h2m_mmp_inbox_SHIFT 0
-#define BCHP_MOCA_HOSTMISC_M2H_MMP_INBOX_1_h2m_mmp_inbox_DEFAULT 0x00000000
-
-/***************************************************************************
- *M2H_MMP_INBOX_2 - MoCA to Host MMP inbox registers , register set index 2.
- ***************************************************************************/
-/* MOCA_HOSTMISC :: M2H_MMP_INBOX_2 :: h2m_mmp_inbox [31:00] */
-#define BCHP_MOCA_HOSTMISC_M2H_MMP_INBOX_2_h2m_mmp_inbox_MASK 0xffffffff
-#define BCHP_MOCA_HOSTMISC_M2H_MMP_INBOX_2_h2m_mmp_inbox_SHIFT 0
-#define BCHP_MOCA_HOSTMISC_M2H_MMP_INBOX_2_h2m_mmp_inbox_DEFAULT 0x00000000
-
-/***************************************************************************
- *M2H_MMP_INBOX_3 - MoCA to Host MMP inbox registers , register set index 3.
- ***************************************************************************/
-/* MOCA_HOSTMISC :: M2H_MMP_INBOX_3 :: h2m_mmp_inbox [31:00] */
-#define BCHP_MOCA_HOSTMISC_M2H_MMP_INBOX_3_h2m_mmp_inbox_MASK 0xffffffff
-#define BCHP_MOCA_HOSTMISC_M2H_MMP_INBOX_3_h2m_mmp_inbox_SHIFT 0
-#define BCHP_MOCA_HOSTMISC_M2H_MMP_INBOX_3_h2m_mmp_inbox_DEFAULT 0x00000000
-
-/***************************************************************************
- *M2H_MMP_INBOX_4 - MoCA to Host MMP inbox registers , register set index 4.
- ***************************************************************************/
-/* MOCA_HOSTMISC :: M2H_MMP_INBOX_4 :: h2m_mmp_inbox [31:00] */
-#define BCHP_MOCA_HOSTMISC_M2H_MMP_INBOX_4_h2m_mmp_inbox_MASK 0xffffffff
-#define BCHP_MOCA_HOSTMISC_M2H_MMP_INBOX_4_h2m_mmp_inbox_SHIFT 0
-#define BCHP_MOCA_HOSTMISC_M2H_MMP_INBOX_4_h2m_mmp_inbox_DEFAULT 0x00000000
-
-/***************************************************************************
- *M2H_MMP_INBOX_5 - MoCA to Host MMP inbox registers , register set index 5.
- ***************************************************************************/
-/* MOCA_HOSTMISC :: M2H_MMP_INBOX_5 :: h2m_mmp_inbox [31:00] */
-#define BCHP_MOCA_HOSTMISC_M2H_MMP_INBOX_5_h2m_mmp_inbox_MASK 0xffffffff
-#define BCHP_MOCA_HOSTMISC_M2H_MMP_INBOX_5_h2m_mmp_inbox_SHIFT 0
-#define BCHP_MOCA_HOSTMISC_M2H_MMP_INBOX_5_h2m_mmp_inbox_DEFAULT 0x00000000
-
-/***************************************************************************
- *M2H_MMP_INBOX_6 - MoCA to Host MMP inbox registers , register set index 6.
- ***************************************************************************/
-/* MOCA_HOSTMISC :: M2H_MMP_INBOX_6 :: h2m_mmp_inbox [31:00] */
-#define BCHP_MOCA_HOSTMISC_M2H_MMP_INBOX_6_h2m_mmp_inbox_MASK 0xffffffff
-#define BCHP_MOCA_HOSTMISC_M2H_MMP_INBOX_6_h2m_mmp_inbox_SHIFT 0
-#define BCHP_MOCA_HOSTMISC_M2H_MMP_INBOX_6_h2m_mmp_inbox_DEFAULT 0x00000000
-
-/***************************************************************************
- *M2H_MMP_INBOX_7 - MoCA to Host MMP inbox registers , register set index 7.
- ***************************************************************************/
-/* MOCA_HOSTMISC :: M2H_MMP_INBOX_7 :: h2m_mmp_inbox [31:00] */
-#define BCHP_MOCA_HOSTMISC_M2H_MMP_INBOX_7_h2m_mmp_inbox_MASK 0xffffffff
-#define BCHP_MOCA_HOSTMISC_M2H_MMP_INBOX_7_h2m_mmp_inbox_SHIFT 0
-#define BCHP_MOCA_HOSTMISC_M2H_MMP_INBOX_7_h2m_mmp_inbox_DEFAULT 0x00000000
-
-/***************************************************************************
- *M2H_MMP_INBOX_8 - MoCA to Host MMP inbox registers , register set index 8.
- ***************************************************************************/
-/* MOCA_HOSTMISC :: M2H_MMP_INBOX_8 :: h2m_mmp_inbox [31:00] */
-#define BCHP_MOCA_HOSTMISC_M2H_MMP_INBOX_8_h2m_mmp_inbox_MASK 0xffffffff
-#define BCHP_MOCA_HOSTMISC_M2H_MMP_INBOX_8_h2m_mmp_inbox_SHIFT 0
-#define BCHP_MOCA_HOSTMISC_M2H_MMP_INBOX_8_h2m_mmp_inbox_DEFAULT 0x00000000
-
-/***************************************************************************
- *M2H_MMP_INBOX_9 - MoCA to Host MMP inbox registers , register set index 9.
- ***************************************************************************/
-/* MOCA_HOSTMISC :: M2H_MMP_INBOX_9 :: h2m_mmp_inbox [31:00] */
-#define BCHP_MOCA_HOSTMISC_M2H_MMP_INBOX_9_h2m_mmp_inbox_MASK 0xffffffff
-#define BCHP_MOCA_HOSTMISC_M2H_MMP_INBOX_9_h2m_mmp_inbox_SHIFT 0
-#define BCHP_MOCA_HOSTMISC_M2H_MMP_INBOX_9_h2m_mmp_inbox_DEFAULT 0x00000000
-
-/***************************************************************************
- *M2H_MMP_INBOX_10 - MoCA to Host MMP inbox registers , register set index 10.
- ***************************************************************************/
-/* MOCA_HOSTMISC :: M2H_MMP_INBOX_10 :: h2m_mmp_inbox [31:00] */
-#define BCHP_MOCA_HOSTMISC_M2H_MMP_INBOX_10_h2m_mmp_inbox_MASK 0xffffffff
-#define BCHP_MOCA_HOSTMISC_M2H_MMP_INBOX_10_h2m_mmp_inbox_SHIFT 0
-#define BCHP_MOCA_HOSTMISC_M2H_MMP_INBOX_10_h2m_mmp_inbox_DEFAULT 0x00000000
-
-/***************************************************************************
- *M2H_MMP_INBOX_11 - MoCA to Host MMP inbox registers , register set index 11.
- ***************************************************************************/
-/* MOCA_HOSTMISC :: M2H_MMP_INBOX_11 :: h2m_mmp_inbox [31:00] */
-#define BCHP_MOCA_HOSTMISC_M2H_MMP_INBOX_11_h2m_mmp_inbox_MASK 0xffffffff
-#define BCHP_MOCA_HOSTMISC_M2H_MMP_INBOX_11_h2m_mmp_inbox_SHIFT 0
-#define BCHP_MOCA_HOSTMISC_M2H_MMP_INBOX_11_h2m_mmp_inbox_DEFAULT 0x00000000
-
-/***************************************************************************
- *M2H_MMP_INBOX_12 - MoCA to Host MMP inbox registers , register set index 12.
- ***************************************************************************/
-/* MOCA_HOSTMISC :: M2H_MMP_INBOX_12 :: h2m_mmp_inbox [31:00] */
-#define BCHP_MOCA_HOSTMISC_M2H_MMP_INBOX_12_h2m_mmp_inbox_MASK 0xffffffff
-#define BCHP_MOCA_HOSTMISC_M2H_MMP_INBOX_12_h2m_mmp_inbox_SHIFT 0
-#define BCHP_MOCA_HOSTMISC_M2H_MMP_INBOX_12_h2m_mmp_inbox_DEFAULT 0x00000000
-
-/***************************************************************************
- *M2H_MMP_INBOX_13 - MoCA to Host MMP inbox registers , register set index 13.
- ***************************************************************************/
-/* MOCA_HOSTMISC :: M2H_MMP_INBOX_13 :: h2m_mmp_inbox [31:00] */
-#define BCHP_MOCA_HOSTMISC_M2H_MMP_INBOX_13_h2m_mmp_inbox_MASK 0xffffffff
-#define BCHP_MOCA_HOSTMISC_M2H_MMP_INBOX_13_h2m_mmp_inbox_SHIFT 0
-#define BCHP_MOCA_HOSTMISC_M2H_MMP_INBOX_13_h2m_mmp_inbox_DEFAULT 0x00000000
-
-/***************************************************************************
- *M2H_MMP_INBOX_14 - MoCA to Host MMP inbox registers , register set index 14.
- ***************************************************************************/
-/* MOCA_HOSTMISC :: M2H_MMP_INBOX_14 :: h2m_mmp_inbox [31:00] */
-#define BCHP_MOCA_HOSTMISC_M2H_MMP_INBOX_14_h2m_mmp_inbox_MASK 0xffffffff
-#define BCHP_MOCA_HOSTMISC_M2H_MMP_INBOX_14_h2m_mmp_inbox_SHIFT 0
-#define BCHP_MOCA_HOSTMISC_M2H_MMP_INBOX_14_h2m_mmp_inbox_DEFAULT 0x00000000
-
-/***************************************************************************
- *M2H_MMP_INBOX_15 - MoCA to Host MMP inbox registers , register set index 15.
- ***************************************************************************/
-/* MOCA_HOSTMISC :: M2H_MMP_INBOX_15 :: h2m_mmp_inbox [31:00] */
-#define BCHP_MOCA_HOSTMISC_M2H_MMP_INBOX_15_h2m_mmp_inbox_MASK 0xffffffff
-#define BCHP_MOCA_HOSTMISC_M2H_MMP_INBOX_15_h2m_mmp_inbox_SHIFT 0
-#define BCHP_MOCA_HOSTMISC_M2H_MMP_INBOX_15_h2m_mmp_inbox_DEFAULT 0x00000000
-
-/***************************************************************************
- *DMPG_CHAINS_STATUS - "MoCA dynamic memory power gating chain power up (bit per chain),Active when moca_dmpg_gisb_en is high,0: Chain is on,1: Chain is off"
- ***************************************************************************/
-/* MOCA_HOSTMISC :: DMPG_CHAINS_STATUS :: dmpg_pda_out_status [31:00] */
-#define BCHP_MOCA_HOSTMISC_DMPG_CHAINS_STATUS_dmpg_pda_out_status_MASK 0xffffffff
-#define BCHP_MOCA_HOSTMISC_DMPG_CHAINS_STATUS_dmpg_pda_out_status_SHIFT 0
-#define BCHP_MOCA_HOSTMISC_DMPG_CHAINS_STATUS_dmpg_pda_out_status_DEFAULT 0x00000000
-
-/***************************************************************************
- *DMPG_CHAINS_PWR_UP - "MoCA dynamic memory power gating chain status (bit per chain),0: Power down chain,1: Power up chain"
- ***************************************************************************/
-/* MOCA_HOSTMISC :: DMPG_CHAINS_PWR_UP :: dmpg_pwr_up [31:00] */
-#define BCHP_MOCA_HOSTMISC_DMPG_CHAINS_PWR_UP_dmpg_pwr_up_MASK 0xffffffff
-#define BCHP_MOCA_HOSTMISC_DMPG_CHAINS_PWR_UP_dmpg_pwr_up_SHIFT 0
-#define BCHP_MOCA_HOSTMISC_DMPG_CHAINS_PWR_UP_dmpg_pwr_up_DEFAULT 0xffffffff
-
-#endif /* #ifndef BCHP_MOCA_HOSTMISC_H__ */
-
-/* End of File */
diff --git a/include/linux/brcmstb/7439a0/bchp_nand.h b/include/linux/brcmstb/7439a0/bchp_nand.h
deleted file mode 100644
index 357284f..0000000
--- a/include/linux/brcmstb/7439a0/bchp_nand.h
+++ /dev/null
@@ -1,3594 +0,0 @@
-/***************************************************************************
- * Copyright (c) 1999-2012, Broadcom Corporation
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
- *
- * Module Description:
- * DO NOT EDIT THIS FILE DIRECTLY
- *
- * This module was generated magically with RDB from a source description
- * file. You must edit the source file for changes to be made to this file.
- *
- *
- * Date: Generated on Wed Oct 17 03:11:31 2012
- * MD5 Checksum d41d8cd98f00b204e9800998ecf8427e
- *
- * Compiled with: RDB Utility combo_header.pl
- * RDB Parser 3.0
- * unknown unknown
- * Perl Interpreter 5.008008
- * Operating System linux
- *
- * Revision History:
- *
- * $brcm_Log: $
- *
- ***************************************************************************/
-
-#ifndef BCHP_NAND_H__
-#define BCHP_NAND_H__
-
-/***************************************************************************
- *NAND - Nand Flash Control Registers
- ***************************************************************************/
-#define BCHP_NAND_REVISION 0x00442800 /* NAND Revision */
-#define BCHP_NAND_CMD_START 0x00442804 /* Nand Flash Command Start */
-#define BCHP_NAND_CMD_EXT_ADDRESS 0x00442808 /* Nand Flash Command Extended Address */
-#define BCHP_NAND_CMD_ADDRESS 0x0044280c /* Nand Flash Command Address */
-#define BCHP_NAND_CMD_END_ADDRESS 0x00442810 /* Nand Flash Command End Address */
-#define BCHP_NAND_INTFC_STATUS 0x00442814 /* Nand Flash Interface Status */
-#define BCHP_NAND_CS_NAND_SELECT 0x00442818 /* Nand Flash EBI CS Select */
-#define BCHP_NAND_CS_NAND_XOR 0x0044281c /* Nand Flash EBI CS XOR masking on CPU address Control */
-#define BCHP_NAND_LL_OP 0x00442820 /* Nand Flash Low Level Operation */
-#define BCHP_NAND_MPLANE_BASE_EXT_ADDRESS 0x00442824 /* Nand Flash Multiplane base address */
-#define BCHP_NAND_MPLANE_BASE_ADDRESS 0x00442828 /* Nand Flash Multiplane base address */
-#define BCHP_NAND_ACC_CONTROL_CS0 0x00442850 /* Nand Flash Access Control */
-#define BCHP_NAND_CONFIG_CS0 0x00442854 /* Nand Flash Config */
-#define BCHP_NAND_TIMING_1_CS0 0x00442858 /* Nand Flash Timing Parameters 1 */
-#define BCHP_NAND_TIMING_2_CS0 0x0044285c /* Nand Flash Timing Parameters 2 */
-#define BCHP_NAND_ACC_CONTROL_CS1 0x00442860 /* Nand Flash Access Control */
-#define BCHP_NAND_CONFIG_CS1 0x00442864 /* Nand Flash Config */
-#define BCHP_NAND_TIMING_1_CS1 0x00442868 /* Nand Flash Timing Parameters 1 */
-#define BCHP_NAND_TIMING_2_CS1 0x0044286c /* Nand Flash Timing Parameters 2 */
-#define BCHP_NAND_ACC_CONTROL_CS2 0x00442870 /* Nand Flash Access Control */
-#define BCHP_NAND_CONFIG_CS2 0x00442874 /* Nand Flash Config */
-#define BCHP_NAND_TIMING_1_CS2 0x00442878 /* Nand Flash Timing Parameters 1 */
-#define BCHP_NAND_TIMING_2_CS2 0x0044287c /* Nand Flash Timing Parameters 2 */
-#define BCHP_NAND_ACC_CONTROL_CS3 0x00442880 /* Nand Flash Access Control */
-#define BCHP_NAND_CONFIG_CS3 0x00442884 /* Nand Flash Config */
-#define BCHP_NAND_TIMING_1_CS3 0x00442888 /* Nand Flash Timing Parameters 1 */
-#define BCHP_NAND_TIMING_2_CS3 0x0044288c /* Nand Flash Timing Parameters 2 */
-#define BCHP_NAND_ACC_CONTROL_CS4 0x00442890 /* Nand Flash Access Control */
-#define BCHP_NAND_CONFIG_CS4 0x00442894 /* Nand Flash Config */
-#define BCHP_NAND_TIMING_1_CS4 0x00442898 /* Nand Flash Timing Parameters 1 */
-#define BCHP_NAND_TIMING_2_CS4 0x0044289c /* Nand Flash Timing Parameters 2 */
-#define BCHP_NAND_ACC_CONTROL_CS5 0x004428a0 /* Nand Flash Access Control */
-#define BCHP_NAND_CONFIG_CS5 0x004428a4 /* Nand Flash Config */
-#define BCHP_NAND_TIMING_1_CS5 0x004428a8 /* Nand Flash Timing Parameters 1 */
-#define BCHP_NAND_TIMING_2_CS5 0x004428ac /* Nand Flash Timing Parameters 2 */
-#define BCHP_NAND_ACC_CONTROL_CS6 0x004428b0 /* Nand Flash Access Control */
-#define BCHP_NAND_CONFIG_CS6 0x004428b4 /* Nand Flash Config */
-#define BCHP_NAND_TIMING_1_CS6 0x004428b8 /* Nand Flash Timing Parameters 1 */
-#define BCHP_NAND_TIMING_2_CS6 0x004428bc /* Nand Flash Timing Parameters 2 */
-#define BCHP_NAND_CORR_STAT_THRESHOLD 0x004428c0 /* Correctable Error Reporting Threshold */
-#define BCHP_NAND_CORR_STAT_THRESHOLD_EXT 0x004428c4 /* Correctable Error Reporting Threshold */
-#define BCHP_NAND_BLK_WR_PROTECT 0x004428c8 /* Block Write Protect Enable and Size for EBI_CS0b */
-#define BCHP_NAND_MULTIPLANE_OPCODES_1 0x004428cc /* Nand Flash Multiplane Customerized Opcodes */
-#define BCHP_NAND_MULTIPLANE_OPCODES_2 0x004428d0 /* Nand Flash Multiplane Customerized Opcodes */
-#define BCHP_NAND_MULTIPLANE_CTRL 0x004428d4 /* Nand Flash Multiplane Control */
-#define BCHP_NAND_UNCORR_ERROR_COUNT 0x004428fc /* Read Uncorrectable Event Count */
-#define BCHP_NAND_CORR_ERROR_COUNT 0x00442900 /* Read Error Count */
-#define BCHP_NAND_READ_ERROR_COUNT 0x00442904 /* Read Error Count */
-#define BCHP_NAND_BLOCK_LOCK_STATUS 0x00442908 /* Nand Flash Block Lock Status */
-#define BCHP_NAND_ECC_CORR_EXT_ADDR 0x0044290c /* ECC Correctable Error Extended Address */
-#define BCHP_NAND_ECC_CORR_ADDR 0x00442910 /* ECC Correctable Error Address */
-#define BCHP_NAND_ECC_UNC_EXT_ADDR 0x00442914 /* ECC Uncorrectable Error Extended Address */
-#define BCHP_NAND_ECC_UNC_ADDR 0x00442918 /* ECC Uncorrectable Error Address */
-#define BCHP_NAND_FLASH_READ_EXT_ADDR 0x0044291c /* Flash Read Data Extended Address */
-#define BCHP_NAND_FLASH_READ_ADDR 0x00442920 /* Flash Read Data Address */
-#define BCHP_NAND_PROGRAM_PAGE_EXT_ADDR 0x00442924 /* Page Program Extended Address */
-#define BCHP_NAND_PROGRAM_PAGE_ADDR 0x00442928 /* Page Program Address */
-#define BCHP_NAND_COPY_BACK_EXT_ADDR 0x0044292c /* Copy Back Extended Address */
-#define BCHP_NAND_COPY_BACK_ADDR 0x00442930 /* Copy Back Address */
-#define BCHP_NAND_BLOCK_ERASE_EXT_ADDR 0x00442934 /* Block Erase Extended Address */
-#define BCHP_NAND_BLOCK_ERASE_ADDR 0x00442938 /* Block Erase Address */
-#define BCHP_NAND_INV_READ_EXT_ADDR 0x0044293c /* Flash Invalid Data Extended Address */
-#define BCHP_NAND_INV_READ_ADDR 0x00442940 /* Flash Invalid Data Address */
-#define BCHP_NAND_INIT_STATUS 0x00442944 /* Initialization status */
-#define BCHP_NAND_ONFI_STATUS 0x00442948 /* ONFI Status */
-#define BCHP_NAND_ONFI_DEBUG_DATA 0x0044294c /* ONFI Debug Data */
-#define BCHP_NAND_SEMAPHORE 0x00442950 /* Semaphore */
-#define BCHP_NAND_FLASH_DEVICE_ID 0x00442994 /* Nand Flash Device ID */
-#define BCHP_NAND_FLASH_DEVICE_ID_EXT 0x00442998 /* Nand Flash Extended Device ID */
-#define BCHP_NAND_LL_RDDATA 0x0044299c /* Nand Flash Low Level Read Data */
-#define BCHP_NAND_SPARE_AREA_READ_OFS_0 0x00442a00 /* Nand Flash Spare Area Read Bytes 0-3 */
-#define BCHP_NAND_SPARE_AREA_READ_OFS_4 0x00442a04 /* Nand Flash Spare Area Read Bytes 4-7 */
-#define BCHP_NAND_SPARE_AREA_READ_OFS_8 0x00442a08 /* Nand Flash Spare Area Read Bytes 8-11 */
-#define BCHP_NAND_SPARE_AREA_READ_OFS_C 0x00442a0c /* Nand Flash Spare Area Read Bytes 12-15 */
-#define BCHP_NAND_SPARE_AREA_READ_OFS_10 0x00442a10 /* Nand Flash Spare Area Read Bytes 16-19 */
-#define BCHP_NAND_SPARE_AREA_READ_OFS_14 0x00442a14 /* Nand Flash Spare Area Read Bytes 20-23 */
-#define BCHP_NAND_SPARE_AREA_READ_OFS_18 0x00442a18 /* Nand Flash Spare Area Read Bytes 24-27 */
-#define BCHP_NAND_SPARE_AREA_READ_OFS_1C 0x00442a1c /* Nand Flash Spare Area Read Bytes 28-31 */
-#define BCHP_NAND_SPARE_AREA_READ_OFS_20 0x00442a20 /* Nand Flash Spare Area Read Bytes 32-35 */
-#define BCHP_NAND_SPARE_AREA_READ_OFS_24 0x00442a24 /* Nand Flash Spare Area Read Bytes 36-39 */
-#define BCHP_NAND_SPARE_AREA_READ_OFS_28 0x00442a28 /* Nand Flash Spare Area Read Bytes 40-43 */
-#define BCHP_NAND_SPARE_AREA_READ_OFS_2C 0x00442a2c /* Nand Flash Spare Area Read Bytes 44-47 */
-#define BCHP_NAND_SPARE_AREA_READ_OFS_30 0x00442a30 /* Nand Flash Spare Area Read Bytes 48-51 */
-#define BCHP_NAND_SPARE_AREA_READ_OFS_34 0x00442a34 /* Nand Flash Spare Area Read Bytes 52-55 */
-#define BCHP_NAND_SPARE_AREA_READ_OFS_38 0x00442a38 /* Nand Flash Spare Area Read Bytes 56-59 */
-#define BCHP_NAND_SPARE_AREA_READ_OFS_3C 0x00442a3c /* Nand Flash Spare Area Read Bytes 60-63 */
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_0 0x00442a80 /* Nand Flash Spare Area Write Bytes 0-3 */
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_4 0x00442a84 /* Nand Flash Spare Area Write Bytes 4-7 */
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_8 0x00442a88 /* Nand Flash Spare Area Write Bytes 8-11 */
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_C 0x00442a8c /* Nand Flash Spare Area Write Bytes 12-15 */
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_10 0x00442a90 /* Nand Flash Spare Area Write Bytes 16-19 */
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_14 0x00442a94 /* Nand Flash Spare Area Write Bytes 20-23 */
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_18 0x00442a98 /* Nand Flash Spare Area Write Bytes 24-27 */
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_1C 0x00442a9c /* Nand Flash Spare Area Write Bytes 28-31 */
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_20 0x00442aa0 /* Nand Flash Spare Area Write Bytes 32-35 */
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_24 0x00442aa4 /* Nand Flash Spare Area Write Bytes 36-39 */
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_28 0x00442aa8 /* Nand Flash Spare Area Write Bytes 40-43 */
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_2C 0x00442aac /* Nand Flash Spare Area Write Bytes 44-47 */
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_30 0x00442ab0 /* Nand Flash Spare Area Write Bytes 48-51 */
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_34 0x00442ab4 /* Nand Flash Spare Area Write Bytes 52-55 */
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_38 0x00442ab8 /* Nand Flash Spare Area Write Bytes 56-59 */
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_3C 0x00442abc /* Nand Flash Spare Area Write Bytes 60-63 */
-#define BCHP_NAND_DDR_TIMING 0x00442ac0 /* Nand Flash DDR TIMING */
-#define BCHP_NAND_DDR_NCDL_CALIB_CTL 0x00442ac4 /* Nand Flash Calibration Control for Master DLL */
-#define BCHP_NAND_DDR_NCDL_CALIB_PERIOD 0x00442ac8 /* Nand Flash Calibration Period */
-#define BCHP_NAND_DDR_NCDL_CALIB_STAT 0x00442acc /* Nand Flash Calibration Status for Master DLL */
-#define BCHP_NAND_DDR_NCDL_MODE 0x00442ad0 /* Nand Flash NCDL mode for Slave DLLs */
-#define BCHP_NAND_DDR_NCDL_OFFSET 0x00442ad4 /* Nand Flash NCDL offset for Slave DLLs */
-#define BCHP_NAND_DDR_PHY_CTL 0x00442ad8 /* Nand Flash DDR PHY CONTROL */
-#define BCHP_NAND_DDR_PHY_BIST_CTL 0x00442adc /* Nand Flash DDR PHY BIST CONTROL */
-#define BCHP_NAND_DDR_PHY_BIST_STAT 0x00442ae0 /* Nand Flash DDR PHY BIST STATUS */
-#define BCHP_NAND_DDR_DIAG_STAT0 0x00442ae4 /* Nand Flash DDR DIAG STATUS0 */
-#define BCHP_NAND_DDR_DIAG_STAT1 0x00442ae8 /* Nand Flash DDR DIAG STATUS1 */
-
-/***************************************************************************
- *REVISION - NAND Revision
- ***************************************************************************/
-/* NAND :: REVISION :: 8KB_PAGE_SUPPORT [31:31] */
-#define BCHP_NAND_REVISION_8KB_PAGE_SUPPORT_MASK 0x80000000
-#define BCHP_NAND_REVISION_8KB_PAGE_SUPPORT_SHIFT 31
-#define BCHP_NAND_REVISION_8KB_PAGE_SUPPORT_DEFAULT 0x00000001
-
-/* NAND :: REVISION :: reserved0 [30:16] */
-#define BCHP_NAND_REVISION_reserved0_MASK 0x7fff0000
-#define BCHP_NAND_REVISION_reserved0_SHIFT 16
-
-/* NAND :: REVISION :: MAJOR [15:08] */
-#define BCHP_NAND_REVISION_MAJOR_MASK 0x0000ff00
-#define BCHP_NAND_REVISION_MAJOR_SHIFT 8
-#define BCHP_NAND_REVISION_MAJOR_DEFAULT 0x00000007
-
-/* NAND :: REVISION :: MINOR [07:00] */
-#define BCHP_NAND_REVISION_MINOR_MASK 0x000000ff
-#define BCHP_NAND_REVISION_MINOR_SHIFT 0
-#define BCHP_NAND_REVISION_MINOR_DEFAULT 0x00000000
-
-/***************************************************************************
- *CMD_START - Nand Flash Command Start
- ***************************************************************************/
-/* NAND :: CMD_START :: reserved0 [31:05] */
-#define BCHP_NAND_CMD_START_reserved0_MASK 0xffffffe0
-#define BCHP_NAND_CMD_START_reserved0_SHIFT 5
-
-/* NAND :: CMD_START :: OPCODE [04:00] */
-#define BCHP_NAND_CMD_START_OPCODE_MASK 0x0000001f
-#define BCHP_NAND_CMD_START_OPCODE_SHIFT 0
-#define BCHP_NAND_CMD_START_OPCODE_DEFAULT 0x00000000
-#define BCHP_NAND_CMD_START_OPCODE_NULL 0
-#define BCHP_NAND_CMD_START_OPCODE_PAGE_READ 1
-#define BCHP_NAND_CMD_START_OPCODE_SPARE_AREA_READ 2
-#define BCHP_NAND_CMD_START_OPCODE_STATUS_READ 3
-#define BCHP_NAND_CMD_START_OPCODE_PROGRAM_PAGE 4
-#define BCHP_NAND_CMD_START_OPCODE_PROGRAM_SPARE_AREA 5
-#define BCHP_NAND_CMD_START_OPCODE_COPY_BACK 6
-#define BCHP_NAND_CMD_START_OPCODE_DEVICE_ID_READ 7
-#define BCHP_NAND_CMD_START_OPCODE_BLOCK_ERASE 8
-#define BCHP_NAND_CMD_START_OPCODE_FLASH_RESET 9
-#define BCHP_NAND_CMD_START_OPCODE_BLOCKS_LOCK 10
-#define BCHP_NAND_CMD_START_OPCODE_BLOCKS_LOCK_DOWN 11
-#define BCHP_NAND_CMD_START_OPCODE_BLOCKS_UNLOCK 12
-#define BCHP_NAND_CMD_START_OPCODE_READ_BLOCKS_LOCK_STATUS 13
-#define BCHP_NAND_CMD_START_OPCODE_PARAMETER_READ 14
-#define BCHP_NAND_CMD_START_OPCODE_PARAMETER_CHANGE_COL 15
-#define BCHP_NAND_CMD_START_OPCODE_LOW_LEVEL_OP 16
-#define BCHP_NAND_CMD_START_OPCODE_PAGE_READ_MULTI 17
-#define BCHP_NAND_CMD_START_OPCODE_STATUS_READ_MULTI 18
-#define BCHP_NAND_CMD_START_OPCODE_PROGRAM_PAGE_MULTI 19
-#define BCHP_NAND_CMD_START_OPCODE_BLOCK_ERASE_MULTI 21
-
-/***************************************************************************
- *CMD_EXT_ADDRESS - Nand Flash Command Extended Address
- ***************************************************************************/
-/* NAND :: CMD_EXT_ADDRESS :: reserved0 [31:19] */
-#define BCHP_NAND_CMD_EXT_ADDRESS_reserved0_MASK 0xfff80000
-#define BCHP_NAND_CMD_EXT_ADDRESS_reserved0_SHIFT 19
-
-/* NAND :: CMD_EXT_ADDRESS :: CS_SEL [18:16] */
-#define BCHP_NAND_CMD_EXT_ADDRESS_CS_SEL_MASK 0x00070000
-#define BCHP_NAND_CMD_EXT_ADDRESS_CS_SEL_SHIFT 16
-#define BCHP_NAND_CMD_EXT_ADDRESS_CS_SEL_DEFAULT 0x00000000
-
-/* NAND :: CMD_EXT_ADDRESS :: EXT_ADDRESS [15:00] */
-#define BCHP_NAND_CMD_EXT_ADDRESS_EXT_ADDRESS_MASK 0x0000ffff
-#define BCHP_NAND_CMD_EXT_ADDRESS_EXT_ADDRESS_SHIFT 0
-#define BCHP_NAND_CMD_EXT_ADDRESS_EXT_ADDRESS_DEFAULT 0x00000000
-
-/***************************************************************************
- *CMD_ADDRESS - Nand Flash Command Address
- ***************************************************************************/
-/* NAND :: CMD_ADDRESS :: ADDRESS [31:00] */
-#define BCHP_NAND_CMD_ADDRESS_ADDRESS_MASK 0xffffffff
-#define BCHP_NAND_CMD_ADDRESS_ADDRESS_SHIFT 0
-#define BCHP_NAND_CMD_ADDRESS_ADDRESS_DEFAULT 0x00000000
-
-/***************************************************************************
- *CMD_END_ADDRESS - Nand Flash Command End Address
- ***************************************************************************/
-/* NAND :: CMD_END_ADDRESS :: ADDRESS [31:00] */
-#define BCHP_NAND_CMD_END_ADDRESS_ADDRESS_MASK 0xffffffff
-#define BCHP_NAND_CMD_END_ADDRESS_ADDRESS_SHIFT 0
-#define BCHP_NAND_CMD_END_ADDRESS_ADDRESS_DEFAULT 0x00000000
-
-/***************************************************************************
- *INTFC_STATUS - Nand Flash Interface Status
- ***************************************************************************/
-/* NAND :: INTFC_STATUS :: CTLR_READY [31:31] */
-#define BCHP_NAND_INTFC_STATUS_CTLR_READY_MASK 0x80000000
-#define BCHP_NAND_INTFC_STATUS_CTLR_READY_SHIFT 31
-
-/* NAND :: INTFC_STATUS :: FLASH_READY [30:30] */
-#define BCHP_NAND_INTFC_STATUS_FLASH_READY_MASK 0x40000000
-#define BCHP_NAND_INTFC_STATUS_FLASH_READY_SHIFT 30
-
-/* NAND :: INTFC_STATUS :: CACHE_VALID [29:29] */
-#define BCHP_NAND_INTFC_STATUS_CACHE_VALID_MASK 0x20000000
-#define BCHP_NAND_INTFC_STATUS_CACHE_VALID_SHIFT 29
-
-/* NAND :: INTFC_STATUS :: SPARE_AREA_VALID [28:28] */
-#define BCHP_NAND_INTFC_STATUS_SPARE_AREA_VALID_MASK 0x10000000
-#define BCHP_NAND_INTFC_STATUS_SPARE_AREA_VALID_SHIFT 28
-
-/* NAND :: INTFC_STATUS :: ERASED [27:27] */
-#define BCHP_NAND_INTFC_STATUS_ERASED_MASK 0x08000000
-#define BCHP_NAND_INTFC_STATUS_ERASED_SHIFT 27
-
-/* NAND :: INTFC_STATUS :: PLANE_READY [26:26] */
-#define BCHP_NAND_INTFC_STATUS_PLANE_READY_MASK 0x04000000
-#define BCHP_NAND_INTFC_STATUS_PLANE_READY_SHIFT 26
-
-/* NAND :: INTFC_STATUS :: reserved0 [25:08] */
-#define BCHP_NAND_INTFC_STATUS_reserved0_MASK 0x03ffff00
-#define BCHP_NAND_INTFC_STATUS_reserved0_SHIFT 8
-
-/* NAND :: INTFC_STATUS :: FLASH_STATUS [07:00] */
-#define BCHP_NAND_INTFC_STATUS_FLASH_STATUS_MASK 0x000000ff
-#define BCHP_NAND_INTFC_STATUS_FLASH_STATUS_SHIFT 0
-#define BCHP_NAND_INTFC_STATUS_FLASH_STATUS_DEFAULT 0x00000000
-
-/***************************************************************************
- *CS_NAND_SELECT - Nand Flash EBI CS Select
- ***************************************************************************/
-/* NAND :: CS_NAND_SELECT :: CS_LOCK [31:31] */
-#define BCHP_NAND_CS_NAND_SELECT_CS_LOCK_MASK 0x80000000
-#define BCHP_NAND_CS_NAND_SELECT_CS_LOCK_SHIFT 31
-#define BCHP_NAND_CS_NAND_SELECT_CS_LOCK_DEFAULT 0x00000000
-
-/* NAND :: CS_NAND_SELECT :: AUTO_DEVICE_ID_CONFIG [30:30] */
-#define BCHP_NAND_CS_NAND_SELECT_AUTO_DEVICE_ID_CONFIG_MASK 0x40000000
-#define BCHP_NAND_CS_NAND_SELECT_AUTO_DEVICE_ID_CONFIG_SHIFT 30
-
-/* NAND :: CS_NAND_SELECT :: NAND_WP [29:29] */
-#define BCHP_NAND_CS_NAND_SELECT_NAND_WP_MASK 0x20000000
-#define BCHP_NAND_CS_NAND_SELECT_NAND_WP_SHIFT 29
-#define BCHP_NAND_CS_NAND_SELECT_NAND_WP_DEFAULT 0x00000001
-
-/* NAND :: CS_NAND_SELECT :: WR_PROTECT_BLK0 [28:28] */
-#define BCHP_NAND_CS_NAND_SELECT_WR_PROTECT_BLK0_MASK 0x10000000
-#define BCHP_NAND_CS_NAND_SELECT_WR_PROTECT_BLK0_SHIFT 28
-#define BCHP_NAND_CS_NAND_SELECT_WR_PROTECT_BLK0_DEFAULT 0x00000000
-
-/* NAND :: CS_NAND_SELECT :: reserved0 [27:16] */
-#define BCHP_NAND_CS_NAND_SELECT_reserved0_MASK 0x0fff0000
-#define BCHP_NAND_CS_NAND_SELECT_reserved0_SHIFT 16
-
-/* NAND :: CS_NAND_SELECT :: EBI_CS_7_USES_NAND [15:15] */
-#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_7_USES_NAND_MASK 0x00008000
-#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_7_USES_NAND_SHIFT 15
-#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_7_USES_NAND_DEFAULT 0x00000000
-
-/* NAND :: CS_NAND_SELECT :: EBI_CS_6_USES_NAND [14:14] */
-#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_6_USES_NAND_MASK 0x00004000
-#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_6_USES_NAND_SHIFT 14
-#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_6_USES_NAND_DEFAULT 0x00000000
-
-/* NAND :: CS_NAND_SELECT :: EBI_CS_5_USES_NAND [13:13] */
-#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_5_USES_NAND_MASK 0x00002000
-#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_5_USES_NAND_SHIFT 13
-#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_5_USES_NAND_DEFAULT 0x00000000
-
-/* NAND :: CS_NAND_SELECT :: EBI_CS_4_USES_NAND [12:12] */
-#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_4_USES_NAND_MASK 0x00001000
-#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_4_USES_NAND_SHIFT 12
-#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_4_USES_NAND_DEFAULT 0x00000000
-
-/* NAND :: CS_NAND_SELECT :: EBI_CS_3_USES_NAND [11:11] */
-#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_3_USES_NAND_MASK 0x00000800
-#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_3_USES_NAND_SHIFT 11
-#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_3_USES_NAND_DEFAULT 0x00000000
-
-/* NAND :: CS_NAND_SELECT :: EBI_CS_2_USES_NAND [10:10] */
-#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_2_USES_NAND_MASK 0x00000400
-#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_2_USES_NAND_SHIFT 10
-#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_2_USES_NAND_DEFAULT 0x00000000
-
-/* NAND :: CS_NAND_SELECT :: EBI_CS_1_USES_NAND [09:09] */
-#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_1_USES_NAND_MASK 0x00000200
-#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_1_USES_NAND_SHIFT 9
-#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_1_USES_NAND_DEFAULT 0x00000000
-
-/* NAND :: CS_NAND_SELECT :: EBI_CS_0_USES_NAND [08:08] */
-#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_0_USES_NAND_MASK 0x00000100
-#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_0_USES_NAND_SHIFT 8
-
-/* NAND :: CS_NAND_SELECT :: EBI_CS_7_SEL [07:07] */
-#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_7_SEL_MASK 0x00000080
-#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_7_SEL_SHIFT 7
-#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_7_SEL_DEFAULT 0x00000000
-
-/* NAND :: CS_NAND_SELECT :: EBI_CS_6_SEL [06:06] */
-#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_6_SEL_MASK 0x00000040
-#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_6_SEL_SHIFT 6
-#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_6_SEL_DEFAULT 0x00000000
-
-/* NAND :: CS_NAND_SELECT :: EBI_CS_5_SEL [05:05] */
-#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_5_SEL_MASK 0x00000020
-#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_5_SEL_SHIFT 5
-#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_5_SEL_DEFAULT 0x00000000
-
-/* NAND :: CS_NAND_SELECT :: EBI_CS_4_SEL [04:04] */
-#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_4_SEL_MASK 0x00000010
-#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_4_SEL_SHIFT 4
-#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_4_SEL_DEFAULT 0x00000000
-
-/* NAND :: CS_NAND_SELECT :: EBI_CS_3_SEL [03:03] */
-#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_3_SEL_MASK 0x00000008
-#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_3_SEL_SHIFT 3
-#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_3_SEL_DEFAULT 0x00000000
-
-/* NAND :: CS_NAND_SELECT :: EBI_CS_2_SEL [02:02] */
-#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_2_SEL_MASK 0x00000004
-#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_2_SEL_SHIFT 2
-#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_2_SEL_DEFAULT 0x00000000
-
-/* NAND :: CS_NAND_SELECT :: EBI_CS_1_SEL [01:01] */
-#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_1_SEL_MASK 0x00000002
-#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_1_SEL_SHIFT 1
-#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_1_SEL_DEFAULT 0x00000000
-
-/* NAND :: CS_NAND_SELECT :: EBI_CS_0_SEL [00:00] */
-#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_0_SEL_MASK 0x00000001
-#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_0_SEL_SHIFT 0
-
-/***************************************************************************
- *CS_NAND_XOR - Nand Flash EBI CS XOR masking on CPU address Control
- ***************************************************************************/
-/* NAND :: CS_NAND_XOR :: ONLY_BLOCK_0_XOR [31:31] */
-#define BCHP_NAND_CS_NAND_XOR_ONLY_BLOCK_0_XOR_MASK 0x80000000
-#define BCHP_NAND_CS_NAND_XOR_ONLY_BLOCK_0_XOR_SHIFT 31
-#define BCHP_NAND_CS_NAND_XOR_ONLY_BLOCK_0_XOR_DEFAULT 0x00000000
-
-/* NAND :: CS_NAND_XOR :: reserved0 [30:08] */
-#define BCHP_NAND_CS_NAND_XOR_reserved0_MASK 0x7fffff00
-#define BCHP_NAND_CS_NAND_XOR_reserved0_SHIFT 8
-
-/* NAND :: CS_NAND_XOR :: EBI_CS_7_ADDR_XOR [07:07] */
-#define BCHP_NAND_CS_NAND_XOR_EBI_CS_7_ADDR_XOR_MASK 0x00000080
-#define BCHP_NAND_CS_NAND_XOR_EBI_CS_7_ADDR_XOR_SHIFT 7
-#define BCHP_NAND_CS_NAND_XOR_EBI_CS_7_ADDR_XOR_DEFAULT 0x00000000
-
-/* NAND :: CS_NAND_XOR :: EBI_CS_6_ADDR_XOR [06:06] */
-#define BCHP_NAND_CS_NAND_XOR_EBI_CS_6_ADDR_XOR_MASK 0x00000040
-#define BCHP_NAND_CS_NAND_XOR_EBI_CS_6_ADDR_XOR_SHIFT 6
-#define BCHP_NAND_CS_NAND_XOR_EBI_CS_6_ADDR_XOR_DEFAULT 0x00000000
-
-/* NAND :: CS_NAND_XOR :: EBI_CS_5_ADDR_XOR [05:05] */
-#define BCHP_NAND_CS_NAND_XOR_EBI_CS_5_ADDR_XOR_MASK 0x00000020
-#define BCHP_NAND_CS_NAND_XOR_EBI_CS_5_ADDR_XOR_SHIFT 5
-#define BCHP_NAND_CS_NAND_XOR_EBI_CS_5_ADDR_XOR_DEFAULT 0x00000000
-
-/* NAND :: CS_NAND_XOR :: EBI_CS_4_ADDR_XOR [04:04] */
-#define BCHP_NAND_CS_NAND_XOR_EBI_CS_4_ADDR_XOR_MASK 0x00000010
-#define BCHP_NAND_CS_NAND_XOR_EBI_CS_4_ADDR_XOR_SHIFT 4
-#define BCHP_NAND_CS_NAND_XOR_EBI_CS_4_ADDR_XOR_DEFAULT 0x00000000
-
-/* NAND :: CS_NAND_XOR :: EBI_CS_3_ADDR_XOR [03:03] */
-#define BCHP_NAND_CS_NAND_XOR_EBI_CS_3_ADDR_XOR_MASK 0x00000008
-#define BCHP_NAND_CS_NAND_XOR_EBI_CS_3_ADDR_XOR_SHIFT 3
-#define BCHP_NAND_CS_NAND_XOR_EBI_CS_3_ADDR_XOR_DEFAULT 0x00000000
-
-/* NAND :: CS_NAND_XOR :: EBI_CS_2_ADDR_XOR [02:02] */
-#define BCHP_NAND_CS_NAND_XOR_EBI_CS_2_ADDR_XOR_MASK 0x00000004
-#define BCHP_NAND_CS_NAND_XOR_EBI_CS_2_ADDR_XOR_SHIFT 2
-#define BCHP_NAND_CS_NAND_XOR_EBI_CS_2_ADDR_XOR_DEFAULT 0x00000000
-
-/* NAND :: CS_NAND_XOR :: EBI_CS_1_ADDR_XOR [01:01] */
-#define BCHP_NAND_CS_NAND_XOR_EBI_CS_1_ADDR_XOR_MASK 0x00000002
-#define BCHP_NAND_CS_NAND_XOR_EBI_CS_1_ADDR_XOR_SHIFT 1
-#define BCHP_NAND_CS_NAND_XOR_EBI_CS_1_ADDR_XOR_DEFAULT 0x00000000
-
-/* NAND :: CS_NAND_XOR :: EBI_CS_0_ADDR_XOR [00:00] */
-#define BCHP_NAND_CS_NAND_XOR_EBI_CS_0_ADDR_XOR_MASK 0x00000001
-#define BCHP_NAND_CS_NAND_XOR_EBI_CS_0_ADDR_XOR_SHIFT 0
-
-/***************************************************************************
- *LL_OP - Nand Flash Low Level Operation
- ***************************************************************************/
-/* NAND :: LL_OP :: RETURN_IDLE [31:31] */
-#define BCHP_NAND_LL_OP_RETURN_IDLE_MASK 0x80000000
-#define BCHP_NAND_LL_OP_RETURN_IDLE_SHIFT 31
-#define BCHP_NAND_LL_OP_RETURN_IDLE_DEFAULT 0x00000000
-
-/* NAND :: LL_OP :: reserved0 [30:20] */
-#define BCHP_NAND_LL_OP_reserved0_MASK 0x7ff00000
-#define BCHP_NAND_LL_OP_reserved0_SHIFT 20
-
-/* NAND :: LL_OP :: CLE [19:19] */
-#define BCHP_NAND_LL_OP_CLE_MASK 0x00080000
-#define BCHP_NAND_LL_OP_CLE_SHIFT 19
-#define BCHP_NAND_LL_OP_CLE_DEFAULT 0x00000000
-
-/* NAND :: LL_OP :: ALE [18:18] */
-#define BCHP_NAND_LL_OP_ALE_MASK 0x00040000
-#define BCHP_NAND_LL_OP_ALE_SHIFT 18
-#define BCHP_NAND_LL_OP_ALE_DEFAULT 0x00000000
-
-/* NAND :: LL_OP :: WE [17:17] */
-#define BCHP_NAND_LL_OP_WE_MASK 0x00020000
-#define BCHP_NAND_LL_OP_WE_SHIFT 17
-#define BCHP_NAND_LL_OP_WE_DEFAULT 0x00000000
-
-/* NAND :: LL_OP :: RE [16:16] */
-#define BCHP_NAND_LL_OP_RE_MASK 0x00010000
-#define BCHP_NAND_LL_OP_RE_SHIFT 16
-#define BCHP_NAND_LL_OP_RE_DEFAULT 0x00000000
-
-/* NAND :: LL_OP :: DATA [15:00] */
-#define BCHP_NAND_LL_OP_DATA_MASK 0x0000ffff
-#define BCHP_NAND_LL_OP_DATA_SHIFT 0
-#define BCHP_NAND_LL_OP_DATA_DEFAULT 0x00000000
-
-/***************************************************************************
- *MPLANE_BASE_EXT_ADDRESS - Nand Flash Multiplane base address
- ***************************************************************************/
-/* NAND :: MPLANE_BASE_EXT_ADDRESS :: reserved0 [31:16] */
-#define BCHP_NAND_MPLANE_BASE_EXT_ADDRESS_reserved0_MASK 0xffff0000
-#define BCHP_NAND_MPLANE_BASE_EXT_ADDRESS_reserved0_SHIFT 16
-
-/* NAND :: MPLANE_BASE_EXT_ADDRESS :: EXT_ADDRESS [15:00] */
-#define BCHP_NAND_MPLANE_BASE_EXT_ADDRESS_EXT_ADDRESS_MASK 0x0000ffff
-#define BCHP_NAND_MPLANE_BASE_EXT_ADDRESS_EXT_ADDRESS_SHIFT 0
-#define BCHP_NAND_MPLANE_BASE_EXT_ADDRESS_EXT_ADDRESS_DEFAULT 0x00000000
-
-/***************************************************************************
- *MPLANE_BASE_ADDRESS - Nand Flash Multiplane base address
- ***************************************************************************/
-/* NAND :: MPLANE_BASE_ADDRESS :: ADDRESS [31:00] */
-#define BCHP_NAND_MPLANE_BASE_ADDRESS_ADDRESS_MASK 0xffffffff
-#define BCHP_NAND_MPLANE_BASE_ADDRESS_ADDRESS_SHIFT 0
-#define BCHP_NAND_MPLANE_BASE_ADDRESS_ADDRESS_DEFAULT 0x00000000
-
-/***************************************************************************
- *ACC_CONTROL_CS0 - Nand Flash Access Control
- ***************************************************************************/
-/* NAND :: ACC_CONTROL_CS0 :: RD_ECC_EN [31:31] */
-#define BCHP_NAND_ACC_CONTROL_CS0_RD_ECC_EN_MASK 0x80000000
-#define BCHP_NAND_ACC_CONTROL_CS0_RD_ECC_EN_SHIFT 31
-#define BCHP_NAND_ACC_CONTROL_CS0_RD_ECC_EN_DEFAULT 0x00000001
-
-/* NAND :: ACC_CONTROL_CS0 :: WR_ECC_EN [30:30] */
-#define BCHP_NAND_ACC_CONTROL_CS0_WR_ECC_EN_MASK 0x40000000
-#define BCHP_NAND_ACC_CONTROL_CS0_WR_ECC_EN_SHIFT 30
-#define BCHP_NAND_ACC_CONTROL_CS0_WR_ECC_EN_DEFAULT 0x00000001
-
-/* NAND :: ACC_CONTROL_CS0 :: CE_CARE [29:29] */
-#define BCHP_NAND_ACC_CONTROL_CS0_CE_CARE_MASK 0x20000000
-#define BCHP_NAND_ACC_CONTROL_CS0_CE_CARE_SHIFT 29
-#define BCHP_NAND_ACC_CONTROL_CS0_CE_CARE_DEFAULT 0x00000000
-
-/* NAND :: ACC_CONTROL_CS0 :: reserved0 [28:28] */
-#define BCHP_NAND_ACC_CONTROL_CS0_reserved0_MASK 0x10000000
-#define BCHP_NAND_ACC_CONTROL_CS0_reserved0_SHIFT 28
-
-/* NAND :: ACC_CONTROL_CS0 :: RD_ERASED_ECC_EN [27:27] */
-#define BCHP_NAND_ACC_CONTROL_CS0_RD_ERASED_ECC_EN_MASK 0x08000000
-#define BCHP_NAND_ACC_CONTROL_CS0_RD_ERASED_ECC_EN_SHIFT 27
-#define BCHP_NAND_ACC_CONTROL_CS0_RD_ERASED_ECC_EN_DEFAULT 0x00000000
-
-/* NAND :: ACC_CONTROL_CS0 :: PARTIAL_PAGE_EN [26:26] */
-#define BCHP_NAND_ACC_CONTROL_CS0_PARTIAL_PAGE_EN_MASK 0x04000000
-#define BCHP_NAND_ACC_CONTROL_CS0_PARTIAL_PAGE_EN_SHIFT 26
-#define BCHP_NAND_ACC_CONTROL_CS0_PARTIAL_PAGE_EN_DEFAULT 0x00000000
-
-/* NAND :: ACC_CONTROL_CS0 :: WR_PREEMPT_EN [25:25] */
-#define BCHP_NAND_ACC_CONTROL_CS0_WR_PREEMPT_EN_MASK 0x02000000
-#define BCHP_NAND_ACC_CONTROL_CS0_WR_PREEMPT_EN_SHIFT 25
-#define BCHP_NAND_ACC_CONTROL_CS0_WR_PREEMPT_EN_DEFAULT 0x00000001
-
-/* NAND :: ACC_CONTROL_CS0 :: PAGE_HIT_EN [24:24] */
-#define BCHP_NAND_ACC_CONTROL_CS0_PAGE_HIT_EN_MASK 0x01000000
-#define BCHP_NAND_ACC_CONTROL_CS0_PAGE_HIT_EN_SHIFT 24
-#define BCHP_NAND_ACC_CONTROL_CS0_PAGE_HIT_EN_DEFAULT 0x00000001
-
-/* NAND :: ACC_CONTROL_CS0 :: PREFETCH_EN [23:23] */
-#define BCHP_NAND_ACC_CONTROL_CS0_PREFETCH_EN_MASK 0x00800000
-#define BCHP_NAND_ACC_CONTROL_CS0_PREFETCH_EN_SHIFT 23
-#define BCHP_NAND_ACC_CONTROL_CS0_PREFETCH_EN_DEFAULT 0x00000000
-
-/* NAND :: ACC_CONTROL_CS0 :: CACHE_MODE_EN [22:22] */
-#define BCHP_NAND_ACC_CONTROL_CS0_CACHE_MODE_EN_MASK 0x00400000
-#define BCHP_NAND_ACC_CONTROL_CS0_CACHE_MODE_EN_SHIFT 22
-#define BCHP_NAND_ACC_CONTROL_CS0_CACHE_MODE_EN_DEFAULT 0x00000000
-
-/* NAND :: ACC_CONTROL_CS0 :: reserved1 [21:21] */
-#define BCHP_NAND_ACC_CONTROL_CS0_reserved1_MASK 0x00200000
-#define BCHP_NAND_ACC_CONTROL_CS0_reserved1_SHIFT 21
-
-/* NAND :: ACC_CONTROL_CS0 :: ECC_LEVEL [20:16] */
-#define BCHP_NAND_ACC_CONTROL_CS0_ECC_LEVEL_MASK 0x001f0000
-#define BCHP_NAND_ACC_CONTROL_CS0_ECC_LEVEL_SHIFT 16
-#define BCHP_NAND_ACC_CONTROL_CS0_ECC_LEVEL_DEFAULT 0x0000000f
-
-/* NAND :: ACC_CONTROL_CS0 :: reserved2 [15:08] */
-#define BCHP_NAND_ACC_CONTROL_CS0_reserved2_MASK 0x0000ff00
-#define BCHP_NAND_ACC_CONTROL_CS0_reserved2_SHIFT 8
-
-/* NAND :: ACC_CONTROL_CS0 :: SECTOR_SIZE_1K [07:07] */
-#define BCHP_NAND_ACC_CONTROL_CS0_SECTOR_SIZE_1K_MASK 0x00000080
-#define BCHP_NAND_ACC_CONTROL_CS0_SECTOR_SIZE_1K_SHIFT 7
-#define BCHP_NAND_ACC_CONTROL_CS0_SECTOR_SIZE_1K_DEFAULT 0x00000000
-
-/* NAND :: ACC_CONTROL_CS0 :: SPARE_AREA_SIZE [06:00] */
-#define BCHP_NAND_ACC_CONTROL_CS0_SPARE_AREA_SIZE_MASK 0x0000007f
-#define BCHP_NAND_ACC_CONTROL_CS0_SPARE_AREA_SIZE_SHIFT 0
-#define BCHP_NAND_ACC_CONTROL_CS0_SPARE_AREA_SIZE_DEFAULT 0x00000010
-
-/***************************************************************************
- *CONFIG_CS0 - Nand Flash Config
- ***************************************************************************/
-/* NAND :: CONFIG_CS0 :: CONFIG_LOCK [31:31] */
-#define BCHP_NAND_CONFIG_CS0_CONFIG_LOCK_MASK 0x80000000
-#define BCHP_NAND_CONFIG_CS0_CONFIG_LOCK_SHIFT 31
-#define BCHP_NAND_CONFIG_CS0_CONFIG_LOCK_DEFAULT 0x00000000
-
-/* NAND :: CONFIG_CS0 :: BLOCK_SIZE [30:28] */
-#define BCHP_NAND_CONFIG_CS0_BLOCK_SIZE_MASK 0x70000000
-#define BCHP_NAND_CONFIG_CS0_BLOCK_SIZE_SHIFT 28
-#define BCHP_NAND_CONFIG_CS0_BLOCK_SIZE_BK_SIZE_2048KB 6
-#define BCHP_NAND_CONFIG_CS0_BLOCK_SIZE_BK_SIZE_1024KB 5
-#define BCHP_NAND_CONFIG_CS0_BLOCK_SIZE_BK_SIZE_512KB 4
-#define BCHP_NAND_CONFIG_CS0_BLOCK_SIZE_BK_SIZE_256KB 3
-#define BCHP_NAND_CONFIG_CS0_BLOCK_SIZE_BK_SIZE_128KB 2
-#define BCHP_NAND_CONFIG_CS0_BLOCK_SIZE_BK_SIZE_16KB 1
-#define BCHP_NAND_CONFIG_CS0_BLOCK_SIZE_BK_SIZE_8KB 0
-
-/* NAND :: CONFIG_CS0 :: DEVICE_SIZE [27:24] */
-#define BCHP_NAND_CONFIG_CS0_DEVICE_SIZE_MASK 0x0f000000
-#define BCHP_NAND_CONFIG_CS0_DEVICE_SIZE_SHIFT 24
-#define BCHP_NAND_CONFIG_CS0_DEVICE_SIZE_DVC_SIZE_4MB 0
-#define BCHP_NAND_CONFIG_CS0_DEVICE_SIZE_DVC_SIZE_8MB 1
-#define BCHP_NAND_CONFIG_CS0_DEVICE_SIZE_DVC_SIZE_16MB 2
-#define BCHP_NAND_CONFIG_CS0_DEVICE_SIZE_DVC_SIZE_32MB 3
-#define BCHP_NAND_CONFIG_CS0_DEVICE_SIZE_DVC_SIZE_64MB 4
-#define BCHP_NAND_CONFIG_CS0_DEVICE_SIZE_DVC_SIZE_128MB 5
-#define BCHP_NAND_CONFIG_CS0_DEVICE_SIZE_DVC_SIZE_256MB 6
-#define BCHP_NAND_CONFIG_CS0_DEVICE_SIZE_DVC_SIZE_512MB 7
-#define BCHP_NAND_CONFIG_CS0_DEVICE_SIZE_DVC_SIZE_1GB 8
-#define BCHP_NAND_CONFIG_CS0_DEVICE_SIZE_DVC_SIZE_2GB 9
-#define BCHP_NAND_CONFIG_CS0_DEVICE_SIZE_DVC_SIZE_4GB 10
-#define BCHP_NAND_CONFIG_CS0_DEVICE_SIZE_DVC_SIZE_8GB 11
-#define BCHP_NAND_CONFIG_CS0_DEVICE_SIZE_DVC_SIZE_16GB 12
-#define BCHP_NAND_CONFIG_CS0_DEVICE_SIZE_DVC_SIZE_32GB 13
-#define BCHP_NAND_CONFIG_CS0_DEVICE_SIZE_DVC_SIZE_64GB 14
-#define BCHP_NAND_CONFIG_CS0_DEVICE_SIZE_DVC_SIZE_128GB 15
-
-/* NAND :: CONFIG_CS0 :: DEVICE_WIDTH [23:23] */
-#define BCHP_NAND_CONFIG_CS0_DEVICE_WIDTH_MASK 0x00800000
-#define BCHP_NAND_CONFIG_CS0_DEVICE_WIDTH_SHIFT 23
-#define BCHP_NAND_CONFIG_CS0_DEVICE_WIDTH_DVC_WIDTH_8 0
-#define BCHP_NAND_CONFIG_CS0_DEVICE_WIDTH_DVC_WIDTH_16 1
-
-/* NAND :: CONFIG_CS0 :: reserved0 [22:22] */
-#define BCHP_NAND_CONFIG_CS0_reserved0_MASK 0x00400000
-#define BCHP_NAND_CONFIG_CS0_reserved0_SHIFT 22
-
-/* NAND :: CONFIG_CS0 :: PAGE_SIZE [21:20] */
-#define BCHP_NAND_CONFIG_CS0_PAGE_SIZE_MASK 0x00300000
-#define BCHP_NAND_CONFIG_CS0_PAGE_SIZE_SHIFT 20
-#define BCHP_NAND_CONFIG_CS0_PAGE_SIZE_PG_SIZE_512 0
-#define BCHP_NAND_CONFIG_CS0_PAGE_SIZE_PG_SIZE_2KB 1
-#define BCHP_NAND_CONFIG_CS0_PAGE_SIZE_PG_SIZE_4KB 2
-#define BCHP_NAND_CONFIG_CS0_PAGE_SIZE_PG_SIZE_8KB 3
-
-/* NAND :: CONFIG_CS0 :: reserved1 [19:19] */
-#define BCHP_NAND_CONFIG_CS0_reserved1_MASK 0x00080000
-#define BCHP_NAND_CONFIG_CS0_reserved1_SHIFT 19
-
-/* NAND :: CONFIG_CS0 :: FUL_ADR_BYTES [18:16] */
-#define BCHP_NAND_CONFIG_CS0_FUL_ADR_BYTES_MASK 0x00070000
-#define BCHP_NAND_CONFIG_CS0_FUL_ADR_BYTES_SHIFT 16
-
-/* NAND :: CONFIG_CS0 :: reserved2 [15:15] */
-#define BCHP_NAND_CONFIG_CS0_reserved2_MASK 0x00008000
-#define BCHP_NAND_CONFIG_CS0_reserved2_SHIFT 15
-
-/* NAND :: CONFIG_CS0 :: COL_ADR_BYTES [14:12] */
-#define BCHP_NAND_CONFIG_CS0_COL_ADR_BYTES_MASK 0x00007000
-#define BCHP_NAND_CONFIG_CS0_COL_ADR_BYTES_SHIFT 12
-
-/* NAND :: CONFIG_CS0 :: reserved3 [11:11] */
-#define BCHP_NAND_CONFIG_CS0_reserved3_MASK 0x00000800
-#define BCHP_NAND_CONFIG_CS0_reserved3_SHIFT 11
-
-/* NAND :: CONFIG_CS0 :: BLK_ADR_BYTES [10:08] */
-#define BCHP_NAND_CONFIG_CS0_BLK_ADR_BYTES_MASK 0x00000700
-#define BCHP_NAND_CONFIG_CS0_BLK_ADR_BYTES_SHIFT 8
-
-/* NAND :: CONFIG_CS0 :: reserved4 [07:00] */
-#define BCHP_NAND_CONFIG_CS0_reserved4_MASK 0x000000ff
-#define BCHP_NAND_CONFIG_CS0_reserved4_SHIFT 0
-
-/***************************************************************************
- *TIMING_1_CS0 - Nand Flash Timing Parameters 1
- ***************************************************************************/
-/* NAND :: TIMING_1_CS0 :: tWP [31:28] */
-#define BCHP_NAND_TIMING_1_CS0_tWP_MASK 0xf0000000
-#define BCHP_NAND_TIMING_1_CS0_tWP_SHIFT 28
-#define BCHP_NAND_TIMING_1_CS0_tWP_DEFAULT 0x00000006
-
-/* NAND :: TIMING_1_CS0 :: tWH [27:24] */
-#define BCHP_NAND_TIMING_1_CS0_tWH_MASK 0x0f000000
-#define BCHP_NAND_TIMING_1_CS0_tWH_SHIFT 24
-#define BCHP_NAND_TIMING_1_CS0_tWH_DEFAULT 0x00000005
-
-/* NAND :: TIMING_1_CS0 :: tRP [23:20] */
-#define BCHP_NAND_TIMING_1_CS0_tRP_MASK 0x00f00000
-#define BCHP_NAND_TIMING_1_CS0_tRP_SHIFT 20
-#define BCHP_NAND_TIMING_1_CS0_tRP_DEFAULT 0x00000007
-
-/* NAND :: TIMING_1_CS0 :: tREH [19:16] */
-#define BCHP_NAND_TIMING_1_CS0_tREH_MASK 0x000f0000
-#define BCHP_NAND_TIMING_1_CS0_tREH_SHIFT 16
-#define BCHP_NAND_TIMING_1_CS0_tREH_DEFAULT 0x00000004
-
-/* NAND :: TIMING_1_CS0 :: tCS [15:12] */
-#define BCHP_NAND_TIMING_1_CS0_tCS_MASK 0x0000f000
-#define BCHP_NAND_TIMING_1_CS0_tCS_SHIFT 12
-#define BCHP_NAND_TIMING_1_CS0_tCS_DEFAULT 0x00000008
-
-/* NAND :: TIMING_1_CS0 :: tCLH [11:08] */
-#define BCHP_NAND_TIMING_1_CS0_tCLH_MASK 0x00000f00
-#define BCHP_NAND_TIMING_1_CS0_tCLH_SHIFT 8
-#define BCHP_NAND_TIMING_1_CS0_tCLH_DEFAULT 0x00000004
-
-/* NAND :: TIMING_1_CS0 :: tALH [07:04] */
-#define BCHP_NAND_TIMING_1_CS0_tALH_MASK 0x000000f0
-#define BCHP_NAND_TIMING_1_CS0_tALH_SHIFT 4
-#define BCHP_NAND_TIMING_1_CS0_tALH_DEFAULT 0x00000005
-
-/* NAND :: TIMING_1_CS0 :: tADL [03:00] */
-#define BCHP_NAND_TIMING_1_CS0_tADL_MASK 0x0000000f
-#define BCHP_NAND_TIMING_1_CS0_tADL_SHIFT 0
-#define BCHP_NAND_TIMING_1_CS0_tADL_DEFAULT 0x0000000b
-
-/***************************************************************************
- *TIMING_2_CS0 - Nand Flash Timing Parameters 2
- ***************************************************************************/
-/* NAND :: TIMING_2_CS0 :: CLK_SELECT [31:31] */
-#define BCHP_NAND_TIMING_2_CS0_CLK_SELECT_MASK 0x80000000
-#define BCHP_NAND_TIMING_2_CS0_CLK_SELECT_SHIFT 31
-#define BCHP_NAND_TIMING_2_CS0_CLK_SELECT_DEFAULT 0x00000000
-#define BCHP_NAND_TIMING_2_CS0_CLK_SELECT_CLK_108 0
-#define BCHP_NAND_TIMING_2_CS0_CLK_SELECT_CLK_216 1
-
-/* NAND :: TIMING_2_CS0 :: reserved0 [30:13] */
-#define BCHP_NAND_TIMING_2_CS0_reserved0_MASK 0x7fffe000
-#define BCHP_NAND_TIMING_2_CS0_reserved0_SHIFT 13
-
-/* NAND :: TIMING_2_CS0 :: tWB [12:09] */
-#define BCHP_NAND_TIMING_2_CS0_tWB_MASK 0x00001e00
-#define BCHP_NAND_TIMING_2_CS0_tWB_SHIFT 9
-#define BCHP_NAND_TIMING_2_CS0_tWB_DEFAULT 0x0000000f
-
-/* NAND :: TIMING_2_CS0 :: tWHR [08:04] */
-#define BCHP_NAND_TIMING_2_CS0_tWHR_MASK 0x000001f0
-#define BCHP_NAND_TIMING_2_CS0_tWHR_SHIFT 4
-#define BCHP_NAND_TIMING_2_CS0_tWHR_DEFAULT 0x00000009
-
-/* NAND :: TIMING_2_CS0 :: tREAD [03:00] */
-#define BCHP_NAND_TIMING_2_CS0_tREAD_MASK 0x0000000f
-#define BCHP_NAND_TIMING_2_CS0_tREAD_SHIFT 0
-#define BCHP_NAND_TIMING_2_CS0_tREAD_DEFAULT 0x00000006
-
-/***************************************************************************
- *ACC_CONTROL_CS1 - Nand Flash Access Control
- ***************************************************************************/
-/* NAND :: ACC_CONTROL_CS1 :: RD_ECC_EN [31:31] */
-#define BCHP_NAND_ACC_CONTROL_CS1_RD_ECC_EN_MASK 0x80000000
-#define BCHP_NAND_ACC_CONTROL_CS1_RD_ECC_EN_SHIFT 31
-#define BCHP_NAND_ACC_CONTROL_CS1_RD_ECC_EN_DEFAULT 0x00000001
-
-/* NAND :: ACC_CONTROL_CS1 :: WR_ECC_EN [30:30] */
-#define BCHP_NAND_ACC_CONTROL_CS1_WR_ECC_EN_MASK 0x40000000
-#define BCHP_NAND_ACC_CONTROL_CS1_WR_ECC_EN_SHIFT 30
-#define BCHP_NAND_ACC_CONTROL_CS1_WR_ECC_EN_DEFAULT 0x00000001
-
-/* NAND :: ACC_CONTROL_CS1 :: CE_CARE [29:29] */
-#define BCHP_NAND_ACC_CONTROL_CS1_CE_CARE_MASK 0x20000000
-#define BCHP_NAND_ACC_CONTROL_CS1_CE_CARE_SHIFT 29
-#define BCHP_NAND_ACC_CONTROL_CS1_CE_CARE_DEFAULT 0x00000000
-
-/* NAND :: ACC_CONTROL_CS1 :: reserved0 [28:28] */
-#define BCHP_NAND_ACC_CONTROL_CS1_reserved0_MASK 0x10000000
-#define BCHP_NAND_ACC_CONTROL_CS1_reserved0_SHIFT 28
-
-/* NAND :: ACC_CONTROL_CS1 :: RD_ERASED_ECC_EN [27:27] */
-#define BCHP_NAND_ACC_CONTROL_CS1_RD_ERASED_ECC_EN_MASK 0x08000000
-#define BCHP_NAND_ACC_CONTROL_CS1_RD_ERASED_ECC_EN_SHIFT 27
-#define BCHP_NAND_ACC_CONTROL_CS1_RD_ERASED_ECC_EN_DEFAULT 0x00000000
-
-/* NAND :: ACC_CONTROL_CS1 :: PARTIAL_PAGE_EN [26:26] */
-#define BCHP_NAND_ACC_CONTROL_CS1_PARTIAL_PAGE_EN_MASK 0x04000000
-#define BCHP_NAND_ACC_CONTROL_CS1_PARTIAL_PAGE_EN_SHIFT 26
-#define BCHP_NAND_ACC_CONTROL_CS1_PARTIAL_PAGE_EN_DEFAULT 0x00000000
-
-/* NAND :: ACC_CONTROL_CS1 :: WR_PREEMPT_EN [25:25] */
-#define BCHP_NAND_ACC_CONTROL_CS1_WR_PREEMPT_EN_MASK 0x02000000
-#define BCHP_NAND_ACC_CONTROL_CS1_WR_PREEMPT_EN_SHIFT 25
-#define BCHP_NAND_ACC_CONTROL_CS1_WR_PREEMPT_EN_DEFAULT 0x00000001
-
-/* NAND :: ACC_CONTROL_CS1 :: PAGE_HIT_EN [24:24] */
-#define BCHP_NAND_ACC_CONTROL_CS1_PAGE_HIT_EN_MASK 0x01000000
-#define BCHP_NAND_ACC_CONTROL_CS1_PAGE_HIT_EN_SHIFT 24
-#define BCHP_NAND_ACC_CONTROL_CS1_PAGE_HIT_EN_DEFAULT 0x00000001
-
-/* NAND :: ACC_CONTROL_CS1 :: PREFETCH_EN [23:23] */
-#define BCHP_NAND_ACC_CONTROL_CS1_PREFETCH_EN_MASK 0x00800000
-#define BCHP_NAND_ACC_CONTROL_CS1_PREFETCH_EN_SHIFT 23
-#define BCHP_NAND_ACC_CONTROL_CS1_PREFETCH_EN_DEFAULT 0x00000000
-
-/* NAND :: ACC_CONTROL_CS1 :: CACHE_MODE_EN [22:22] */
-#define BCHP_NAND_ACC_CONTROL_CS1_CACHE_MODE_EN_MASK 0x00400000
-#define BCHP_NAND_ACC_CONTROL_CS1_CACHE_MODE_EN_SHIFT 22
-#define BCHP_NAND_ACC_CONTROL_CS1_CACHE_MODE_EN_DEFAULT 0x00000000
-
-/* NAND :: ACC_CONTROL_CS1 :: reserved1 [21:21] */
-#define BCHP_NAND_ACC_CONTROL_CS1_reserved1_MASK 0x00200000
-#define BCHP_NAND_ACC_CONTROL_CS1_reserved1_SHIFT 21
-
-/* NAND :: ACC_CONTROL_CS1 :: ECC_LEVEL [20:16] */
-#define BCHP_NAND_ACC_CONTROL_CS1_ECC_LEVEL_MASK 0x001f0000
-#define BCHP_NAND_ACC_CONTROL_CS1_ECC_LEVEL_SHIFT 16
-#define BCHP_NAND_ACC_CONTROL_CS1_ECC_LEVEL_DEFAULT 0x0000000f
-
-/* NAND :: ACC_CONTROL_CS1 :: reserved2 [15:08] */
-#define BCHP_NAND_ACC_CONTROL_CS1_reserved2_MASK 0x0000ff00
-#define BCHP_NAND_ACC_CONTROL_CS1_reserved2_SHIFT 8
-
-/* NAND :: ACC_CONTROL_CS1 :: SECTOR_SIZE_1K [07:07] */
-#define BCHP_NAND_ACC_CONTROL_CS1_SECTOR_SIZE_1K_MASK 0x00000080
-#define BCHP_NAND_ACC_CONTROL_CS1_SECTOR_SIZE_1K_SHIFT 7
-#define BCHP_NAND_ACC_CONTROL_CS1_SECTOR_SIZE_1K_DEFAULT 0x00000000
-
-/* NAND :: ACC_CONTROL_CS1 :: SPARE_AREA_SIZE [06:00] */
-#define BCHP_NAND_ACC_CONTROL_CS1_SPARE_AREA_SIZE_MASK 0x0000007f
-#define BCHP_NAND_ACC_CONTROL_CS1_SPARE_AREA_SIZE_SHIFT 0
-#define BCHP_NAND_ACC_CONTROL_CS1_SPARE_AREA_SIZE_DEFAULT 0x00000010
-
-/***************************************************************************
- *CONFIG_CS1 - Nand Flash Config
- ***************************************************************************/
-/* NAND :: CONFIG_CS1 :: CONFIG_LOCK [31:31] */
-#define BCHP_NAND_CONFIG_CS1_CONFIG_LOCK_MASK 0x80000000
-#define BCHP_NAND_CONFIG_CS1_CONFIG_LOCK_SHIFT 31
-#define BCHP_NAND_CONFIG_CS1_CONFIG_LOCK_DEFAULT 0x00000000
-
-/* NAND :: CONFIG_CS1 :: BLOCK_SIZE [30:28] */
-#define BCHP_NAND_CONFIG_CS1_BLOCK_SIZE_MASK 0x70000000
-#define BCHP_NAND_CONFIG_CS1_BLOCK_SIZE_SHIFT 28
-#define BCHP_NAND_CONFIG_CS1_BLOCK_SIZE_BK_SIZE_2048KB 6
-#define BCHP_NAND_CONFIG_CS1_BLOCK_SIZE_BK_SIZE_1024KB 5
-#define BCHP_NAND_CONFIG_CS1_BLOCK_SIZE_BK_SIZE_512KB 4
-#define BCHP_NAND_CONFIG_CS1_BLOCK_SIZE_BK_SIZE_256KB 3
-#define BCHP_NAND_CONFIG_CS1_BLOCK_SIZE_BK_SIZE_128KB 2
-#define BCHP_NAND_CONFIG_CS1_BLOCK_SIZE_BK_SIZE_16KB 1
-#define BCHP_NAND_CONFIG_CS1_BLOCK_SIZE_BK_SIZE_8KB 0
-
-/* NAND :: CONFIG_CS1 :: DEVICE_SIZE [27:24] */
-#define BCHP_NAND_CONFIG_CS1_DEVICE_SIZE_MASK 0x0f000000
-#define BCHP_NAND_CONFIG_CS1_DEVICE_SIZE_SHIFT 24
-#define BCHP_NAND_CONFIG_CS1_DEVICE_SIZE_DVC_SIZE_4MB 0
-#define BCHP_NAND_CONFIG_CS1_DEVICE_SIZE_DVC_SIZE_8MB 1
-#define BCHP_NAND_CONFIG_CS1_DEVICE_SIZE_DVC_SIZE_16MB 2
-#define BCHP_NAND_CONFIG_CS1_DEVICE_SIZE_DVC_SIZE_32MB 3
-#define BCHP_NAND_CONFIG_CS1_DEVICE_SIZE_DVC_SIZE_64MB 4
-#define BCHP_NAND_CONFIG_CS1_DEVICE_SIZE_DVC_SIZE_128MB 5
-#define BCHP_NAND_CONFIG_CS1_DEVICE_SIZE_DVC_SIZE_256MB 6
-#define BCHP_NAND_CONFIG_CS1_DEVICE_SIZE_DVC_SIZE_512MB 7
-#define BCHP_NAND_CONFIG_CS1_DEVICE_SIZE_DVC_SIZE_1GB 8
-#define BCHP_NAND_CONFIG_CS1_DEVICE_SIZE_DVC_SIZE_2GB 9
-#define BCHP_NAND_CONFIG_CS1_DEVICE_SIZE_DVC_SIZE_4GB 10
-#define BCHP_NAND_CONFIG_CS1_DEVICE_SIZE_DVC_SIZE_8GB 11
-#define BCHP_NAND_CONFIG_CS1_DEVICE_SIZE_DVC_SIZE_16GB 12
-#define BCHP_NAND_CONFIG_CS1_DEVICE_SIZE_DVC_SIZE_32GB 13
-#define BCHP_NAND_CONFIG_CS1_DEVICE_SIZE_DVC_SIZE_64GB 14
-#define BCHP_NAND_CONFIG_CS1_DEVICE_SIZE_DVC_SIZE_128GB 15
-
-/* NAND :: CONFIG_CS1 :: DEVICE_WIDTH [23:23] */
-#define BCHP_NAND_CONFIG_CS1_DEVICE_WIDTH_MASK 0x00800000
-#define BCHP_NAND_CONFIG_CS1_DEVICE_WIDTH_SHIFT 23
-#define BCHP_NAND_CONFIG_CS1_DEVICE_WIDTH_DVC_WIDTH_8 0
-#define BCHP_NAND_CONFIG_CS1_DEVICE_WIDTH_DVC_WIDTH_16 1
-
-/* NAND :: CONFIG_CS1 :: reserved0 [22:22] */
-#define BCHP_NAND_CONFIG_CS1_reserved0_MASK 0x00400000
-#define BCHP_NAND_CONFIG_CS1_reserved0_SHIFT 22
-
-/* NAND :: CONFIG_CS1 :: PAGE_SIZE [21:20] */
-#define BCHP_NAND_CONFIG_CS1_PAGE_SIZE_MASK 0x00300000
-#define BCHP_NAND_CONFIG_CS1_PAGE_SIZE_SHIFT 20
-#define BCHP_NAND_CONFIG_CS1_PAGE_SIZE_PG_SIZE_512 0
-#define BCHP_NAND_CONFIG_CS1_PAGE_SIZE_PG_SIZE_2KB 1
-#define BCHP_NAND_CONFIG_CS1_PAGE_SIZE_PG_SIZE_4KB 2
-#define BCHP_NAND_CONFIG_CS1_PAGE_SIZE_PG_SIZE_8KB 3
-
-/* NAND :: CONFIG_CS1 :: reserved1 [19:19] */
-#define BCHP_NAND_CONFIG_CS1_reserved1_MASK 0x00080000
-#define BCHP_NAND_CONFIG_CS1_reserved1_SHIFT 19
-
-/* NAND :: CONFIG_CS1 :: FUL_ADR_BYTES [18:16] */
-#define BCHP_NAND_CONFIG_CS1_FUL_ADR_BYTES_MASK 0x00070000
-#define BCHP_NAND_CONFIG_CS1_FUL_ADR_BYTES_SHIFT 16
-
-/* NAND :: CONFIG_CS1 :: reserved2 [15:15] */
-#define BCHP_NAND_CONFIG_CS1_reserved2_MASK 0x00008000
-#define BCHP_NAND_CONFIG_CS1_reserved2_SHIFT 15
-
-/* NAND :: CONFIG_CS1 :: COL_ADR_BYTES [14:12] */
-#define BCHP_NAND_CONFIG_CS1_COL_ADR_BYTES_MASK 0x00007000
-#define BCHP_NAND_CONFIG_CS1_COL_ADR_BYTES_SHIFT 12
-
-/* NAND :: CONFIG_CS1 :: reserved3 [11:11] */
-#define BCHP_NAND_CONFIG_CS1_reserved3_MASK 0x00000800
-#define BCHP_NAND_CONFIG_CS1_reserved3_SHIFT 11
-
-/* NAND :: CONFIG_CS1 :: BLK_ADR_BYTES [10:08] */
-#define BCHP_NAND_CONFIG_CS1_BLK_ADR_BYTES_MASK 0x00000700
-#define BCHP_NAND_CONFIG_CS1_BLK_ADR_BYTES_SHIFT 8
-
-/* NAND :: CONFIG_CS1 :: reserved4 [07:00] */
-#define BCHP_NAND_CONFIG_CS1_reserved4_MASK 0x000000ff
-#define BCHP_NAND_CONFIG_CS1_reserved4_SHIFT 0
-
-/***************************************************************************
- *TIMING_1_CS1 - Nand Flash Timing Parameters 1
- ***************************************************************************/
-/* NAND :: TIMING_1_CS1 :: tWP [31:28] */
-#define BCHP_NAND_TIMING_1_CS1_tWP_MASK 0xf0000000
-#define BCHP_NAND_TIMING_1_CS1_tWP_SHIFT 28
-#define BCHP_NAND_TIMING_1_CS1_tWP_DEFAULT 0x00000006
-
-/* NAND :: TIMING_1_CS1 :: tWH [27:24] */
-#define BCHP_NAND_TIMING_1_CS1_tWH_MASK 0x0f000000
-#define BCHP_NAND_TIMING_1_CS1_tWH_SHIFT 24
-#define BCHP_NAND_TIMING_1_CS1_tWH_DEFAULT 0x00000005
-
-/* NAND :: TIMING_1_CS1 :: tRP [23:20] */
-#define BCHP_NAND_TIMING_1_CS1_tRP_MASK 0x00f00000
-#define BCHP_NAND_TIMING_1_CS1_tRP_SHIFT 20
-#define BCHP_NAND_TIMING_1_CS1_tRP_DEFAULT 0x00000007
-
-/* NAND :: TIMING_1_CS1 :: tREH [19:16] */
-#define BCHP_NAND_TIMING_1_CS1_tREH_MASK 0x000f0000
-#define BCHP_NAND_TIMING_1_CS1_tREH_SHIFT 16
-#define BCHP_NAND_TIMING_1_CS1_tREH_DEFAULT 0x00000004
-
-/* NAND :: TIMING_1_CS1 :: tCS [15:12] */
-#define BCHP_NAND_TIMING_1_CS1_tCS_MASK 0x0000f000
-#define BCHP_NAND_TIMING_1_CS1_tCS_SHIFT 12
-#define BCHP_NAND_TIMING_1_CS1_tCS_DEFAULT 0x00000008
-
-/* NAND :: TIMING_1_CS1 :: tCLH [11:08] */
-#define BCHP_NAND_TIMING_1_CS1_tCLH_MASK 0x00000f00
-#define BCHP_NAND_TIMING_1_CS1_tCLH_SHIFT 8
-#define BCHP_NAND_TIMING_1_CS1_tCLH_DEFAULT 0x00000004
-
-/* NAND :: TIMING_1_CS1 :: tALH [07:04] */
-#define BCHP_NAND_TIMING_1_CS1_tALH_MASK 0x000000f0
-#define BCHP_NAND_TIMING_1_CS1_tALH_SHIFT 4
-#define BCHP_NAND_TIMING_1_CS1_tALH_DEFAULT 0x00000005
-
-/* NAND :: TIMING_1_CS1 :: tADL [03:00] */
-#define BCHP_NAND_TIMING_1_CS1_tADL_MASK 0x0000000f
-#define BCHP_NAND_TIMING_1_CS1_tADL_SHIFT 0
-#define BCHP_NAND_TIMING_1_CS1_tADL_DEFAULT 0x0000000b
-
-/***************************************************************************
- *TIMING_2_CS1 - Nand Flash Timing Parameters 2
- ***************************************************************************/
-/* NAND :: TIMING_2_CS1 :: CLK_SELECT [31:31] */
-#define BCHP_NAND_TIMING_2_CS1_CLK_SELECT_MASK 0x80000000
-#define BCHP_NAND_TIMING_2_CS1_CLK_SELECT_SHIFT 31
-#define BCHP_NAND_TIMING_2_CS1_CLK_SELECT_DEFAULT 0x00000000
-#define BCHP_NAND_TIMING_2_CS1_CLK_SELECT_CLK_108 0
-#define BCHP_NAND_TIMING_2_CS1_CLK_SELECT_CLK_216 1
-
-/* NAND :: TIMING_2_CS1 :: reserved0 [30:13] */
-#define BCHP_NAND_TIMING_2_CS1_reserved0_MASK 0x7fffe000
-#define BCHP_NAND_TIMING_2_CS1_reserved0_SHIFT 13
-
-/* NAND :: TIMING_2_CS1 :: tWB [12:09] */
-#define BCHP_NAND_TIMING_2_CS1_tWB_MASK 0x00001e00
-#define BCHP_NAND_TIMING_2_CS1_tWB_SHIFT 9
-#define BCHP_NAND_TIMING_2_CS1_tWB_DEFAULT 0x0000000f
-
-/* NAND :: TIMING_2_CS1 :: tWHR [08:04] */
-#define BCHP_NAND_TIMING_2_CS1_tWHR_MASK 0x000001f0
-#define BCHP_NAND_TIMING_2_CS1_tWHR_SHIFT 4
-#define BCHP_NAND_TIMING_2_CS1_tWHR_DEFAULT 0x00000009
-
-/* NAND :: TIMING_2_CS1 :: tREAD [03:00] */
-#define BCHP_NAND_TIMING_2_CS1_tREAD_MASK 0x0000000f
-#define BCHP_NAND_TIMING_2_CS1_tREAD_SHIFT 0
-#define BCHP_NAND_TIMING_2_CS1_tREAD_DEFAULT 0x00000006
-
-/***************************************************************************
- *ACC_CONTROL_CS2 - Nand Flash Access Control
- ***************************************************************************/
-/* NAND :: ACC_CONTROL_CS2 :: RD_ECC_EN [31:31] */
-#define BCHP_NAND_ACC_CONTROL_CS2_RD_ECC_EN_MASK 0x80000000
-#define BCHP_NAND_ACC_CONTROL_CS2_RD_ECC_EN_SHIFT 31
-#define BCHP_NAND_ACC_CONTROL_CS2_RD_ECC_EN_DEFAULT 0x00000001
-
-/* NAND :: ACC_CONTROL_CS2 :: WR_ECC_EN [30:30] */
-#define BCHP_NAND_ACC_CONTROL_CS2_WR_ECC_EN_MASK 0x40000000
-#define BCHP_NAND_ACC_CONTROL_CS2_WR_ECC_EN_SHIFT 30
-#define BCHP_NAND_ACC_CONTROL_CS2_WR_ECC_EN_DEFAULT 0x00000001
-
-/* NAND :: ACC_CONTROL_CS2 :: CE_CARE [29:29] */
-#define BCHP_NAND_ACC_CONTROL_CS2_CE_CARE_MASK 0x20000000
-#define BCHP_NAND_ACC_CONTROL_CS2_CE_CARE_SHIFT 29
-#define BCHP_NAND_ACC_CONTROL_CS2_CE_CARE_DEFAULT 0x00000000
-
-/* NAND :: ACC_CONTROL_CS2 :: reserved0 [28:28] */
-#define BCHP_NAND_ACC_CONTROL_CS2_reserved0_MASK 0x10000000
-#define BCHP_NAND_ACC_CONTROL_CS2_reserved0_SHIFT 28
-
-/* NAND :: ACC_CONTROL_CS2 :: RD_ERASED_ECC_EN [27:27] */
-#define BCHP_NAND_ACC_CONTROL_CS2_RD_ERASED_ECC_EN_MASK 0x08000000
-#define BCHP_NAND_ACC_CONTROL_CS2_RD_ERASED_ECC_EN_SHIFT 27
-#define BCHP_NAND_ACC_CONTROL_CS2_RD_ERASED_ECC_EN_DEFAULT 0x00000000
-
-/* NAND :: ACC_CONTROL_CS2 :: PARTIAL_PAGE_EN [26:26] */
-#define BCHP_NAND_ACC_CONTROL_CS2_PARTIAL_PAGE_EN_MASK 0x04000000
-#define BCHP_NAND_ACC_CONTROL_CS2_PARTIAL_PAGE_EN_SHIFT 26
-#define BCHP_NAND_ACC_CONTROL_CS2_PARTIAL_PAGE_EN_DEFAULT 0x00000000
-
-/* NAND :: ACC_CONTROL_CS2 :: WR_PREEMPT_EN [25:25] */
-#define BCHP_NAND_ACC_CONTROL_CS2_WR_PREEMPT_EN_MASK 0x02000000
-#define BCHP_NAND_ACC_CONTROL_CS2_WR_PREEMPT_EN_SHIFT 25
-#define BCHP_NAND_ACC_CONTROL_CS2_WR_PREEMPT_EN_DEFAULT 0x00000001
-
-/* NAND :: ACC_CONTROL_CS2 :: PAGE_HIT_EN [24:24] */
-#define BCHP_NAND_ACC_CONTROL_CS2_PAGE_HIT_EN_MASK 0x01000000
-#define BCHP_NAND_ACC_CONTROL_CS2_PAGE_HIT_EN_SHIFT 24
-#define BCHP_NAND_ACC_CONTROL_CS2_PAGE_HIT_EN_DEFAULT 0x00000001
-
-/* NAND :: ACC_CONTROL_CS2 :: PREFETCH_EN [23:23] */
-#define BCHP_NAND_ACC_CONTROL_CS2_PREFETCH_EN_MASK 0x00800000
-#define BCHP_NAND_ACC_CONTROL_CS2_PREFETCH_EN_SHIFT 23
-#define BCHP_NAND_ACC_CONTROL_CS2_PREFETCH_EN_DEFAULT 0x00000000
-
-/* NAND :: ACC_CONTROL_CS2 :: CACHE_MODE_EN [22:22] */
-#define BCHP_NAND_ACC_CONTROL_CS2_CACHE_MODE_EN_MASK 0x00400000
-#define BCHP_NAND_ACC_CONTROL_CS2_CACHE_MODE_EN_SHIFT 22
-#define BCHP_NAND_ACC_CONTROL_CS2_CACHE_MODE_EN_DEFAULT 0x00000000
-
-/* NAND :: ACC_CONTROL_CS2 :: reserved1 [21:21] */
-#define BCHP_NAND_ACC_CONTROL_CS2_reserved1_MASK 0x00200000
-#define BCHP_NAND_ACC_CONTROL_CS2_reserved1_SHIFT 21
-
-/* NAND :: ACC_CONTROL_CS2 :: ECC_LEVEL [20:16] */
-#define BCHP_NAND_ACC_CONTROL_CS2_ECC_LEVEL_MASK 0x001f0000
-#define BCHP_NAND_ACC_CONTROL_CS2_ECC_LEVEL_SHIFT 16
-#define BCHP_NAND_ACC_CONTROL_CS2_ECC_LEVEL_DEFAULT 0x0000000f
-
-/* NAND :: ACC_CONTROL_CS2 :: reserved2 [15:08] */
-#define BCHP_NAND_ACC_CONTROL_CS2_reserved2_MASK 0x0000ff00
-#define BCHP_NAND_ACC_CONTROL_CS2_reserved2_SHIFT 8
-
-/* NAND :: ACC_CONTROL_CS2 :: SECTOR_SIZE_1K [07:07] */
-#define BCHP_NAND_ACC_CONTROL_CS2_SECTOR_SIZE_1K_MASK 0x00000080
-#define BCHP_NAND_ACC_CONTROL_CS2_SECTOR_SIZE_1K_SHIFT 7
-#define BCHP_NAND_ACC_CONTROL_CS2_SECTOR_SIZE_1K_DEFAULT 0x00000000
-
-/* NAND :: ACC_CONTROL_CS2 :: SPARE_AREA_SIZE [06:00] */
-#define BCHP_NAND_ACC_CONTROL_CS2_SPARE_AREA_SIZE_MASK 0x0000007f
-#define BCHP_NAND_ACC_CONTROL_CS2_SPARE_AREA_SIZE_SHIFT 0
-#define BCHP_NAND_ACC_CONTROL_CS2_SPARE_AREA_SIZE_DEFAULT 0x00000010
-
-/***************************************************************************
- *CONFIG_CS2 - Nand Flash Config
- ***************************************************************************/
-/* NAND :: CONFIG_CS2 :: CONFIG_LOCK [31:31] */
-#define BCHP_NAND_CONFIG_CS2_CONFIG_LOCK_MASK 0x80000000
-#define BCHP_NAND_CONFIG_CS2_CONFIG_LOCK_SHIFT 31
-#define BCHP_NAND_CONFIG_CS2_CONFIG_LOCK_DEFAULT 0x00000000
-
-/* NAND :: CONFIG_CS2 :: BLOCK_SIZE [30:28] */
-#define BCHP_NAND_CONFIG_CS2_BLOCK_SIZE_MASK 0x70000000
-#define BCHP_NAND_CONFIG_CS2_BLOCK_SIZE_SHIFT 28
-#define BCHP_NAND_CONFIG_CS2_BLOCK_SIZE_BK_SIZE_2048KB 6
-#define BCHP_NAND_CONFIG_CS2_BLOCK_SIZE_BK_SIZE_1024KB 5
-#define BCHP_NAND_CONFIG_CS2_BLOCK_SIZE_BK_SIZE_512KB 4
-#define BCHP_NAND_CONFIG_CS2_BLOCK_SIZE_BK_SIZE_256KB 3
-#define BCHP_NAND_CONFIG_CS2_BLOCK_SIZE_BK_SIZE_128KB 2
-#define BCHP_NAND_CONFIG_CS2_BLOCK_SIZE_BK_SIZE_16KB 1
-#define BCHP_NAND_CONFIG_CS2_BLOCK_SIZE_BK_SIZE_8KB 0
-
-/* NAND :: CONFIG_CS2 :: DEVICE_SIZE [27:24] */
-#define BCHP_NAND_CONFIG_CS2_DEVICE_SIZE_MASK 0x0f000000
-#define BCHP_NAND_CONFIG_CS2_DEVICE_SIZE_SHIFT 24
-#define BCHP_NAND_CONFIG_CS2_DEVICE_SIZE_DVC_SIZE_4MB 0
-#define BCHP_NAND_CONFIG_CS2_DEVICE_SIZE_DVC_SIZE_8MB 1
-#define BCHP_NAND_CONFIG_CS2_DEVICE_SIZE_DVC_SIZE_16MB 2
-#define BCHP_NAND_CONFIG_CS2_DEVICE_SIZE_DVC_SIZE_32MB 3
-#define BCHP_NAND_CONFIG_CS2_DEVICE_SIZE_DVC_SIZE_64MB 4
-#define BCHP_NAND_CONFIG_CS2_DEVICE_SIZE_DVC_SIZE_128MB 5
-#define BCHP_NAND_CONFIG_CS2_DEVICE_SIZE_DVC_SIZE_256MB 6
-#define BCHP_NAND_CONFIG_CS2_DEVICE_SIZE_DVC_SIZE_512MB 7
-#define BCHP_NAND_CONFIG_CS2_DEVICE_SIZE_DVC_SIZE_1GB 8
-#define BCHP_NAND_CONFIG_CS2_DEVICE_SIZE_DVC_SIZE_2GB 9
-#define BCHP_NAND_CONFIG_CS2_DEVICE_SIZE_DVC_SIZE_4GB 10
-#define BCHP_NAND_CONFIG_CS2_DEVICE_SIZE_DVC_SIZE_8GB 11
-#define BCHP_NAND_CONFIG_CS2_DEVICE_SIZE_DVC_SIZE_16GB 12
-#define BCHP_NAND_CONFIG_CS2_DEVICE_SIZE_DVC_SIZE_32GB 13
-#define BCHP_NAND_CONFIG_CS2_DEVICE_SIZE_DVC_SIZE_64GB 14
-#define BCHP_NAND_CONFIG_CS2_DEVICE_SIZE_DVC_SIZE_128GB 15
-
-/* NAND :: CONFIG_CS2 :: DEVICE_WIDTH [23:23] */
-#define BCHP_NAND_CONFIG_CS2_DEVICE_WIDTH_MASK 0x00800000
-#define BCHP_NAND_CONFIG_CS2_DEVICE_WIDTH_SHIFT 23
-#define BCHP_NAND_CONFIG_CS2_DEVICE_WIDTH_DVC_WIDTH_8 0
-#define BCHP_NAND_CONFIG_CS2_DEVICE_WIDTH_DVC_WIDTH_16 1
-
-/* NAND :: CONFIG_CS2 :: reserved0 [22:22] */
-#define BCHP_NAND_CONFIG_CS2_reserved0_MASK 0x00400000
-#define BCHP_NAND_CONFIG_CS2_reserved0_SHIFT 22
-
-/* NAND :: CONFIG_CS2 :: PAGE_SIZE [21:20] */
-#define BCHP_NAND_CONFIG_CS2_PAGE_SIZE_MASK 0x00300000
-#define BCHP_NAND_CONFIG_CS2_PAGE_SIZE_SHIFT 20
-#define BCHP_NAND_CONFIG_CS2_PAGE_SIZE_PG_SIZE_512 0
-#define BCHP_NAND_CONFIG_CS2_PAGE_SIZE_PG_SIZE_2KB 1
-#define BCHP_NAND_CONFIG_CS2_PAGE_SIZE_PG_SIZE_4KB 2
-#define BCHP_NAND_CONFIG_CS2_PAGE_SIZE_PG_SIZE_8KB 3
-
-/* NAND :: CONFIG_CS2 :: reserved1 [19:19] */
-#define BCHP_NAND_CONFIG_CS2_reserved1_MASK 0x00080000
-#define BCHP_NAND_CONFIG_CS2_reserved1_SHIFT 19
-
-/* NAND :: CONFIG_CS2 :: FUL_ADR_BYTES [18:16] */
-#define BCHP_NAND_CONFIG_CS2_FUL_ADR_BYTES_MASK 0x00070000
-#define BCHP_NAND_CONFIG_CS2_FUL_ADR_BYTES_SHIFT 16
-
-/* NAND :: CONFIG_CS2 :: reserved2 [15:15] */
-#define BCHP_NAND_CONFIG_CS2_reserved2_MASK 0x00008000
-#define BCHP_NAND_CONFIG_CS2_reserved2_SHIFT 15
-
-/* NAND :: CONFIG_CS2 :: COL_ADR_BYTES [14:12] */
-#define BCHP_NAND_CONFIG_CS2_COL_ADR_BYTES_MASK 0x00007000
-#define BCHP_NAND_CONFIG_CS2_COL_ADR_BYTES_SHIFT 12
-
-/* NAND :: CONFIG_CS2 :: reserved3 [11:11] */
-#define BCHP_NAND_CONFIG_CS2_reserved3_MASK 0x00000800
-#define BCHP_NAND_CONFIG_CS2_reserved3_SHIFT 11
-
-/* NAND :: CONFIG_CS2 :: BLK_ADR_BYTES [10:08] */
-#define BCHP_NAND_CONFIG_CS2_BLK_ADR_BYTES_MASK 0x00000700
-#define BCHP_NAND_CONFIG_CS2_BLK_ADR_BYTES_SHIFT 8
-
-/* NAND :: CONFIG_CS2 :: reserved4 [07:00] */
-#define BCHP_NAND_CONFIG_CS2_reserved4_MASK 0x000000ff
-#define BCHP_NAND_CONFIG_CS2_reserved4_SHIFT 0
-
-/***************************************************************************
- *TIMING_1_CS2 - Nand Flash Timing Parameters 1
- ***************************************************************************/
-/* NAND :: TIMING_1_CS2 :: tWP [31:28] */
-#define BCHP_NAND_TIMING_1_CS2_tWP_MASK 0xf0000000
-#define BCHP_NAND_TIMING_1_CS2_tWP_SHIFT 28
-#define BCHP_NAND_TIMING_1_CS2_tWP_DEFAULT 0x00000006
-
-/* NAND :: TIMING_1_CS2 :: tWH [27:24] */
-#define BCHP_NAND_TIMING_1_CS2_tWH_MASK 0x0f000000
-#define BCHP_NAND_TIMING_1_CS2_tWH_SHIFT 24
-#define BCHP_NAND_TIMING_1_CS2_tWH_DEFAULT 0x00000005
-
-/* NAND :: TIMING_1_CS2 :: tRP [23:20] */
-#define BCHP_NAND_TIMING_1_CS2_tRP_MASK 0x00f00000
-#define BCHP_NAND_TIMING_1_CS2_tRP_SHIFT 20
-#define BCHP_NAND_TIMING_1_CS2_tRP_DEFAULT 0x00000007
-
-/* NAND :: TIMING_1_CS2 :: tREH [19:16] */
-#define BCHP_NAND_TIMING_1_CS2_tREH_MASK 0x000f0000
-#define BCHP_NAND_TIMING_1_CS2_tREH_SHIFT 16
-#define BCHP_NAND_TIMING_1_CS2_tREH_DEFAULT 0x00000004
-
-/* NAND :: TIMING_1_CS2 :: tCS [15:12] */
-#define BCHP_NAND_TIMING_1_CS2_tCS_MASK 0x0000f000
-#define BCHP_NAND_TIMING_1_CS2_tCS_SHIFT 12
-#define BCHP_NAND_TIMING_1_CS2_tCS_DEFAULT 0x00000008
-
-/* NAND :: TIMING_1_CS2 :: tCLH [11:08] */
-#define BCHP_NAND_TIMING_1_CS2_tCLH_MASK 0x00000f00
-#define BCHP_NAND_TIMING_1_CS2_tCLH_SHIFT 8
-#define BCHP_NAND_TIMING_1_CS2_tCLH_DEFAULT 0x00000004
-
-/* NAND :: TIMING_1_CS2 :: tALH [07:04] */
-#define BCHP_NAND_TIMING_1_CS2_tALH_MASK 0x000000f0
-#define BCHP_NAND_TIMING_1_CS2_tALH_SHIFT 4
-#define BCHP_NAND_TIMING_1_CS2_tALH_DEFAULT 0x00000005
-
-/* NAND :: TIMING_1_CS2 :: tADL [03:00] */
-#define BCHP_NAND_TIMING_1_CS2_tADL_MASK 0x0000000f
-#define BCHP_NAND_TIMING_1_CS2_tADL_SHIFT 0
-#define BCHP_NAND_TIMING_1_CS2_tADL_DEFAULT 0x0000000b
-
-/***************************************************************************
- *TIMING_2_CS2 - Nand Flash Timing Parameters 2
- ***************************************************************************/
-/* NAND :: TIMING_2_CS2 :: CLK_SELECT [31:31] */
-#define BCHP_NAND_TIMING_2_CS2_CLK_SELECT_MASK 0x80000000
-#define BCHP_NAND_TIMING_2_CS2_CLK_SELECT_SHIFT 31
-#define BCHP_NAND_TIMING_2_CS2_CLK_SELECT_DEFAULT 0x00000000
-#define BCHP_NAND_TIMING_2_CS2_CLK_SELECT_CLK_108 0
-#define BCHP_NAND_TIMING_2_CS2_CLK_SELECT_CLK_216 1
-
-/* NAND :: TIMING_2_CS2 :: reserved0 [30:13] */
-#define BCHP_NAND_TIMING_2_CS2_reserved0_MASK 0x7fffe000
-#define BCHP_NAND_TIMING_2_CS2_reserved0_SHIFT 13
-
-/* NAND :: TIMING_2_CS2 :: tWB [12:09] */
-#define BCHP_NAND_TIMING_2_CS2_tWB_MASK 0x00001e00
-#define BCHP_NAND_TIMING_2_CS2_tWB_SHIFT 9
-#define BCHP_NAND_TIMING_2_CS2_tWB_DEFAULT 0x0000000f
-
-/* NAND :: TIMING_2_CS2 :: tWHR [08:04] */
-#define BCHP_NAND_TIMING_2_CS2_tWHR_MASK 0x000001f0
-#define BCHP_NAND_TIMING_2_CS2_tWHR_SHIFT 4
-#define BCHP_NAND_TIMING_2_CS2_tWHR_DEFAULT 0x00000009
-
-/* NAND :: TIMING_2_CS2 :: tREAD [03:00] */
-#define BCHP_NAND_TIMING_2_CS2_tREAD_MASK 0x0000000f
-#define BCHP_NAND_TIMING_2_CS2_tREAD_SHIFT 0
-#define BCHP_NAND_TIMING_2_CS2_tREAD_DEFAULT 0x00000006
-
-/***************************************************************************
- *ACC_CONTROL_CS3 - Nand Flash Access Control
- ***************************************************************************/
-/* NAND :: ACC_CONTROL_CS3 :: RD_ECC_EN [31:31] */
-#define BCHP_NAND_ACC_CONTROL_CS3_RD_ECC_EN_MASK 0x80000000
-#define BCHP_NAND_ACC_CONTROL_CS3_RD_ECC_EN_SHIFT 31
-#define BCHP_NAND_ACC_CONTROL_CS3_RD_ECC_EN_DEFAULT 0x00000001
-
-/* NAND :: ACC_CONTROL_CS3 :: WR_ECC_EN [30:30] */
-#define BCHP_NAND_ACC_CONTROL_CS3_WR_ECC_EN_MASK 0x40000000
-#define BCHP_NAND_ACC_CONTROL_CS3_WR_ECC_EN_SHIFT 30
-#define BCHP_NAND_ACC_CONTROL_CS3_WR_ECC_EN_DEFAULT 0x00000001
-
-/* NAND :: ACC_CONTROL_CS3 :: CE_CARE [29:29] */
-#define BCHP_NAND_ACC_CONTROL_CS3_CE_CARE_MASK 0x20000000
-#define BCHP_NAND_ACC_CONTROL_CS3_CE_CARE_SHIFT 29
-#define BCHP_NAND_ACC_CONTROL_CS3_CE_CARE_DEFAULT 0x00000000
-
-/* NAND :: ACC_CONTROL_CS3 :: reserved0 [28:28] */
-#define BCHP_NAND_ACC_CONTROL_CS3_reserved0_MASK 0x10000000
-#define BCHP_NAND_ACC_CONTROL_CS3_reserved0_SHIFT 28
-
-/* NAND :: ACC_CONTROL_CS3 :: RD_ERASED_ECC_EN [27:27] */
-#define BCHP_NAND_ACC_CONTROL_CS3_RD_ERASED_ECC_EN_MASK 0x08000000
-#define BCHP_NAND_ACC_CONTROL_CS3_RD_ERASED_ECC_EN_SHIFT 27
-#define BCHP_NAND_ACC_CONTROL_CS3_RD_ERASED_ECC_EN_DEFAULT 0x00000000
-
-/* NAND :: ACC_CONTROL_CS3 :: PARTIAL_PAGE_EN [26:26] */
-#define BCHP_NAND_ACC_CONTROL_CS3_PARTIAL_PAGE_EN_MASK 0x04000000
-#define BCHP_NAND_ACC_CONTROL_CS3_PARTIAL_PAGE_EN_SHIFT 26
-#define BCHP_NAND_ACC_CONTROL_CS3_PARTIAL_PAGE_EN_DEFAULT 0x00000000
-
-/* NAND :: ACC_CONTROL_CS3 :: WR_PREEMPT_EN [25:25] */
-#define BCHP_NAND_ACC_CONTROL_CS3_WR_PREEMPT_EN_MASK 0x02000000
-#define BCHP_NAND_ACC_CONTROL_CS3_WR_PREEMPT_EN_SHIFT 25
-#define BCHP_NAND_ACC_CONTROL_CS3_WR_PREEMPT_EN_DEFAULT 0x00000001
-
-/* NAND :: ACC_CONTROL_CS3 :: PAGE_HIT_EN [24:24] */
-#define BCHP_NAND_ACC_CONTROL_CS3_PAGE_HIT_EN_MASK 0x01000000
-#define BCHP_NAND_ACC_CONTROL_CS3_PAGE_HIT_EN_SHIFT 24
-#define BCHP_NAND_ACC_CONTROL_CS3_PAGE_HIT_EN_DEFAULT 0x00000001
-
-/* NAND :: ACC_CONTROL_CS3 :: PREFETCH_EN [23:23] */
-#define BCHP_NAND_ACC_CONTROL_CS3_PREFETCH_EN_MASK 0x00800000
-#define BCHP_NAND_ACC_CONTROL_CS3_PREFETCH_EN_SHIFT 23
-#define BCHP_NAND_ACC_CONTROL_CS3_PREFETCH_EN_DEFAULT 0x00000000
-
-/* NAND :: ACC_CONTROL_CS3 :: CACHE_MODE_EN [22:22] */
-#define BCHP_NAND_ACC_CONTROL_CS3_CACHE_MODE_EN_MASK 0x00400000
-#define BCHP_NAND_ACC_CONTROL_CS3_CACHE_MODE_EN_SHIFT 22
-#define BCHP_NAND_ACC_CONTROL_CS3_CACHE_MODE_EN_DEFAULT 0x00000000
-
-/* NAND :: ACC_CONTROL_CS3 :: reserved1 [21:21] */
-#define BCHP_NAND_ACC_CONTROL_CS3_reserved1_MASK 0x00200000
-#define BCHP_NAND_ACC_CONTROL_CS3_reserved1_SHIFT 21
-
-/* NAND :: ACC_CONTROL_CS3 :: ECC_LEVEL [20:16] */
-#define BCHP_NAND_ACC_CONTROL_CS3_ECC_LEVEL_MASK 0x001f0000
-#define BCHP_NAND_ACC_CONTROL_CS3_ECC_LEVEL_SHIFT 16
-#define BCHP_NAND_ACC_CONTROL_CS3_ECC_LEVEL_DEFAULT 0x0000000f
-
-/* NAND :: ACC_CONTROL_CS3 :: reserved2 [15:08] */
-#define BCHP_NAND_ACC_CONTROL_CS3_reserved2_MASK 0x0000ff00
-#define BCHP_NAND_ACC_CONTROL_CS3_reserved2_SHIFT 8
-
-/* NAND :: ACC_CONTROL_CS3 :: SECTOR_SIZE_1K [07:07] */
-#define BCHP_NAND_ACC_CONTROL_CS3_SECTOR_SIZE_1K_MASK 0x00000080
-#define BCHP_NAND_ACC_CONTROL_CS3_SECTOR_SIZE_1K_SHIFT 7
-#define BCHP_NAND_ACC_CONTROL_CS3_SECTOR_SIZE_1K_DEFAULT 0x00000000
-
-/* NAND :: ACC_CONTROL_CS3 :: SPARE_AREA_SIZE [06:00] */
-#define BCHP_NAND_ACC_CONTROL_CS3_SPARE_AREA_SIZE_MASK 0x0000007f
-#define BCHP_NAND_ACC_CONTROL_CS3_SPARE_AREA_SIZE_SHIFT 0
-#define BCHP_NAND_ACC_CONTROL_CS3_SPARE_AREA_SIZE_DEFAULT 0x00000010
-
-/***************************************************************************
- *CONFIG_CS3 - Nand Flash Config
- ***************************************************************************/
-/* NAND :: CONFIG_CS3 :: CONFIG_LOCK [31:31] */
-#define BCHP_NAND_CONFIG_CS3_CONFIG_LOCK_MASK 0x80000000
-#define BCHP_NAND_CONFIG_CS3_CONFIG_LOCK_SHIFT 31
-#define BCHP_NAND_CONFIG_CS3_CONFIG_LOCK_DEFAULT 0x00000000
-
-/* NAND :: CONFIG_CS3 :: BLOCK_SIZE [30:28] */
-#define BCHP_NAND_CONFIG_CS3_BLOCK_SIZE_MASK 0x70000000
-#define BCHP_NAND_CONFIG_CS3_BLOCK_SIZE_SHIFT 28
-#define BCHP_NAND_CONFIG_CS3_BLOCK_SIZE_BK_SIZE_2048KB 6
-#define BCHP_NAND_CONFIG_CS3_BLOCK_SIZE_BK_SIZE_1024KB 5
-#define BCHP_NAND_CONFIG_CS3_BLOCK_SIZE_BK_SIZE_512KB 4
-#define BCHP_NAND_CONFIG_CS3_BLOCK_SIZE_BK_SIZE_256KB 3
-#define BCHP_NAND_CONFIG_CS3_BLOCK_SIZE_BK_SIZE_128KB 2
-#define BCHP_NAND_CONFIG_CS3_BLOCK_SIZE_BK_SIZE_16KB 1
-#define BCHP_NAND_CONFIG_CS3_BLOCK_SIZE_BK_SIZE_8KB 0
-
-/* NAND :: CONFIG_CS3 :: DEVICE_SIZE [27:24] */
-#define BCHP_NAND_CONFIG_CS3_DEVICE_SIZE_MASK 0x0f000000
-#define BCHP_NAND_CONFIG_CS3_DEVICE_SIZE_SHIFT 24
-#define BCHP_NAND_CONFIG_CS3_DEVICE_SIZE_DVC_SIZE_4MB 0
-#define BCHP_NAND_CONFIG_CS3_DEVICE_SIZE_DVC_SIZE_8MB 1
-#define BCHP_NAND_CONFIG_CS3_DEVICE_SIZE_DVC_SIZE_16MB 2
-#define BCHP_NAND_CONFIG_CS3_DEVICE_SIZE_DVC_SIZE_32MB 3
-#define BCHP_NAND_CONFIG_CS3_DEVICE_SIZE_DVC_SIZE_64MB 4
-#define BCHP_NAND_CONFIG_CS3_DEVICE_SIZE_DVC_SIZE_128MB 5
-#define BCHP_NAND_CONFIG_CS3_DEVICE_SIZE_DVC_SIZE_256MB 6
-#define BCHP_NAND_CONFIG_CS3_DEVICE_SIZE_DVC_SIZE_512MB 7
-#define BCHP_NAND_CONFIG_CS3_DEVICE_SIZE_DVC_SIZE_1GB 8
-#define BCHP_NAND_CONFIG_CS3_DEVICE_SIZE_DVC_SIZE_2GB 9
-#define BCHP_NAND_CONFIG_CS3_DEVICE_SIZE_DVC_SIZE_4GB 10
-#define BCHP_NAND_CONFIG_CS3_DEVICE_SIZE_DVC_SIZE_8GB 11
-#define BCHP_NAND_CONFIG_CS3_DEVICE_SIZE_DVC_SIZE_16GB 12
-#define BCHP_NAND_CONFIG_CS3_DEVICE_SIZE_DVC_SIZE_32GB 13
-#define BCHP_NAND_CONFIG_CS3_DEVICE_SIZE_DVC_SIZE_64GB 14
-#define BCHP_NAND_CONFIG_CS3_DEVICE_SIZE_DVC_SIZE_128GB 15
-
-/* NAND :: CONFIG_CS3 :: DEVICE_WIDTH [23:23] */
-#define BCHP_NAND_CONFIG_CS3_DEVICE_WIDTH_MASK 0x00800000
-#define BCHP_NAND_CONFIG_CS3_DEVICE_WIDTH_SHIFT 23
-#define BCHP_NAND_CONFIG_CS3_DEVICE_WIDTH_DVC_WIDTH_8 0
-#define BCHP_NAND_CONFIG_CS3_DEVICE_WIDTH_DVC_WIDTH_16 1
-
-/* NAND :: CONFIG_CS3 :: reserved0 [22:22] */
-#define BCHP_NAND_CONFIG_CS3_reserved0_MASK 0x00400000
-#define BCHP_NAND_CONFIG_CS3_reserved0_SHIFT 22
-
-/* NAND :: CONFIG_CS3 :: PAGE_SIZE [21:20] */
-#define BCHP_NAND_CONFIG_CS3_PAGE_SIZE_MASK 0x00300000
-#define BCHP_NAND_CONFIG_CS3_PAGE_SIZE_SHIFT 20
-#define BCHP_NAND_CONFIG_CS3_PAGE_SIZE_PG_SIZE_512 0
-#define BCHP_NAND_CONFIG_CS3_PAGE_SIZE_PG_SIZE_2KB 1
-#define BCHP_NAND_CONFIG_CS3_PAGE_SIZE_PG_SIZE_4KB 2
-#define BCHP_NAND_CONFIG_CS3_PAGE_SIZE_PG_SIZE_8KB 3
-
-/* NAND :: CONFIG_CS3 :: reserved1 [19:19] */
-#define BCHP_NAND_CONFIG_CS3_reserved1_MASK 0x00080000
-#define BCHP_NAND_CONFIG_CS3_reserved1_SHIFT 19
-
-/* NAND :: CONFIG_CS3 :: FUL_ADR_BYTES [18:16] */
-#define BCHP_NAND_CONFIG_CS3_FUL_ADR_BYTES_MASK 0x00070000
-#define BCHP_NAND_CONFIG_CS3_FUL_ADR_BYTES_SHIFT 16
-
-/* NAND :: CONFIG_CS3 :: reserved2 [15:15] */
-#define BCHP_NAND_CONFIG_CS3_reserved2_MASK 0x00008000
-#define BCHP_NAND_CONFIG_CS3_reserved2_SHIFT 15
-
-/* NAND :: CONFIG_CS3 :: COL_ADR_BYTES [14:12] */
-#define BCHP_NAND_CONFIG_CS3_COL_ADR_BYTES_MASK 0x00007000
-#define BCHP_NAND_CONFIG_CS3_COL_ADR_BYTES_SHIFT 12
-
-/* NAND :: CONFIG_CS3 :: reserved3 [11:11] */
-#define BCHP_NAND_CONFIG_CS3_reserved3_MASK 0x00000800
-#define BCHP_NAND_CONFIG_CS3_reserved3_SHIFT 11
-
-/* NAND :: CONFIG_CS3 :: BLK_ADR_BYTES [10:08] */
-#define BCHP_NAND_CONFIG_CS3_BLK_ADR_BYTES_MASK 0x00000700
-#define BCHP_NAND_CONFIG_CS3_BLK_ADR_BYTES_SHIFT 8
-
-/* NAND :: CONFIG_CS3 :: reserved4 [07:00] */
-#define BCHP_NAND_CONFIG_CS3_reserved4_MASK 0x000000ff
-#define BCHP_NAND_CONFIG_CS3_reserved4_SHIFT 0
-
-/***************************************************************************
- *TIMING_1_CS3 - Nand Flash Timing Parameters 1
- ***************************************************************************/
-/* NAND :: TIMING_1_CS3 :: tWP [31:28] */
-#define BCHP_NAND_TIMING_1_CS3_tWP_MASK 0xf0000000
-#define BCHP_NAND_TIMING_1_CS3_tWP_SHIFT 28
-#define BCHP_NAND_TIMING_1_CS3_tWP_DEFAULT 0x00000006
-
-/* NAND :: TIMING_1_CS3 :: tWH [27:24] */
-#define BCHP_NAND_TIMING_1_CS3_tWH_MASK 0x0f000000
-#define BCHP_NAND_TIMING_1_CS3_tWH_SHIFT 24
-#define BCHP_NAND_TIMING_1_CS3_tWH_DEFAULT 0x00000005
-
-/* NAND :: TIMING_1_CS3 :: tRP [23:20] */
-#define BCHP_NAND_TIMING_1_CS3_tRP_MASK 0x00f00000
-#define BCHP_NAND_TIMING_1_CS3_tRP_SHIFT 20
-#define BCHP_NAND_TIMING_1_CS3_tRP_DEFAULT 0x00000007
-
-/* NAND :: TIMING_1_CS3 :: tREH [19:16] */
-#define BCHP_NAND_TIMING_1_CS3_tREH_MASK 0x000f0000
-#define BCHP_NAND_TIMING_1_CS3_tREH_SHIFT 16
-#define BCHP_NAND_TIMING_1_CS3_tREH_DEFAULT 0x00000004
-
-/* NAND :: TIMING_1_CS3 :: tCS [15:12] */
-#define BCHP_NAND_TIMING_1_CS3_tCS_MASK 0x0000f000
-#define BCHP_NAND_TIMING_1_CS3_tCS_SHIFT 12
-#define BCHP_NAND_TIMING_1_CS3_tCS_DEFAULT 0x00000008
-
-/* NAND :: TIMING_1_CS3 :: tCLH [11:08] */
-#define BCHP_NAND_TIMING_1_CS3_tCLH_MASK 0x00000f00
-#define BCHP_NAND_TIMING_1_CS3_tCLH_SHIFT 8
-#define BCHP_NAND_TIMING_1_CS3_tCLH_DEFAULT 0x00000004
-
-/* NAND :: TIMING_1_CS3 :: tALH [07:04] */
-#define BCHP_NAND_TIMING_1_CS3_tALH_MASK 0x000000f0
-#define BCHP_NAND_TIMING_1_CS3_tALH_SHIFT 4
-#define BCHP_NAND_TIMING_1_CS3_tALH_DEFAULT 0x00000005
-
-/* NAND :: TIMING_1_CS3 :: tADL [03:00] */
-#define BCHP_NAND_TIMING_1_CS3_tADL_MASK 0x0000000f
-#define BCHP_NAND_TIMING_1_CS3_tADL_SHIFT 0
-#define BCHP_NAND_TIMING_1_CS3_tADL_DEFAULT 0x0000000b
-
-/***************************************************************************
- *TIMING_2_CS3 - Nand Flash Timing Parameters 2
- ***************************************************************************/
-/* NAND :: TIMING_2_CS3 :: CLK_SELECT [31:31] */
-#define BCHP_NAND_TIMING_2_CS3_CLK_SELECT_MASK 0x80000000
-#define BCHP_NAND_TIMING_2_CS3_CLK_SELECT_SHIFT 31
-#define BCHP_NAND_TIMING_2_CS3_CLK_SELECT_DEFAULT 0x00000000
-#define BCHP_NAND_TIMING_2_CS3_CLK_SELECT_CLK_108 0
-#define BCHP_NAND_TIMING_2_CS3_CLK_SELECT_CLK_216 1
-
-/* NAND :: TIMING_2_CS3 :: reserved0 [30:13] */
-#define BCHP_NAND_TIMING_2_CS3_reserved0_MASK 0x7fffe000
-#define BCHP_NAND_TIMING_2_CS3_reserved0_SHIFT 13
-
-/* NAND :: TIMING_2_CS3 :: tWB [12:09] */
-#define BCHP_NAND_TIMING_2_CS3_tWB_MASK 0x00001e00
-#define BCHP_NAND_TIMING_2_CS3_tWB_SHIFT 9
-#define BCHP_NAND_TIMING_2_CS3_tWB_DEFAULT 0x0000000f
-
-/* NAND :: TIMING_2_CS3 :: tWHR [08:04] */
-#define BCHP_NAND_TIMING_2_CS3_tWHR_MASK 0x000001f0
-#define BCHP_NAND_TIMING_2_CS3_tWHR_SHIFT 4
-#define BCHP_NAND_TIMING_2_CS3_tWHR_DEFAULT 0x00000009
-
-/* NAND :: TIMING_2_CS3 :: tREAD [03:00] */
-#define BCHP_NAND_TIMING_2_CS3_tREAD_MASK 0x0000000f
-#define BCHP_NAND_TIMING_2_CS3_tREAD_SHIFT 0
-#define BCHP_NAND_TIMING_2_CS3_tREAD_DEFAULT 0x00000006
-
-/***************************************************************************
- *ACC_CONTROL_CS4 - Nand Flash Access Control
- ***************************************************************************/
-/* NAND :: ACC_CONTROL_CS4 :: RD_ECC_EN [31:31] */
-#define BCHP_NAND_ACC_CONTROL_CS4_RD_ECC_EN_MASK 0x80000000
-#define BCHP_NAND_ACC_CONTROL_CS4_RD_ECC_EN_SHIFT 31
-#define BCHP_NAND_ACC_CONTROL_CS4_RD_ECC_EN_DEFAULT 0x00000001
-
-/* NAND :: ACC_CONTROL_CS4 :: WR_ECC_EN [30:30] */
-#define BCHP_NAND_ACC_CONTROL_CS4_WR_ECC_EN_MASK 0x40000000
-#define BCHP_NAND_ACC_CONTROL_CS4_WR_ECC_EN_SHIFT 30
-#define BCHP_NAND_ACC_CONTROL_CS4_WR_ECC_EN_DEFAULT 0x00000001
-
-/* NAND :: ACC_CONTROL_CS4 :: CE_CARE [29:29] */
-#define BCHP_NAND_ACC_CONTROL_CS4_CE_CARE_MASK 0x20000000
-#define BCHP_NAND_ACC_CONTROL_CS4_CE_CARE_SHIFT 29
-#define BCHP_NAND_ACC_CONTROL_CS4_CE_CARE_DEFAULT 0x00000000
-
-/* NAND :: ACC_CONTROL_CS4 :: reserved0 [28:28] */
-#define BCHP_NAND_ACC_CONTROL_CS4_reserved0_MASK 0x10000000
-#define BCHP_NAND_ACC_CONTROL_CS4_reserved0_SHIFT 28
-
-/* NAND :: ACC_CONTROL_CS4 :: RD_ERASED_ECC_EN [27:27] */
-#define BCHP_NAND_ACC_CONTROL_CS4_RD_ERASED_ECC_EN_MASK 0x08000000
-#define BCHP_NAND_ACC_CONTROL_CS4_RD_ERASED_ECC_EN_SHIFT 27
-#define BCHP_NAND_ACC_CONTROL_CS4_RD_ERASED_ECC_EN_DEFAULT 0x00000000
-
-/* NAND :: ACC_CONTROL_CS4 :: PARTIAL_PAGE_EN [26:26] */
-#define BCHP_NAND_ACC_CONTROL_CS4_PARTIAL_PAGE_EN_MASK 0x04000000
-#define BCHP_NAND_ACC_CONTROL_CS4_PARTIAL_PAGE_EN_SHIFT 26
-#define BCHP_NAND_ACC_CONTROL_CS4_PARTIAL_PAGE_EN_DEFAULT 0x00000000
-
-/* NAND :: ACC_CONTROL_CS4 :: WR_PREEMPT_EN [25:25] */
-#define BCHP_NAND_ACC_CONTROL_CS4_WR_PREEMPT_EN_MASK 0x02000000
-#define BCHP_NAND_ACC_CONTROL_CS4_WR_PREEMPT_EN_SHIFT 25
-#define BCHP_NAND_ACC_CONTROL_CS4_WR_PREEMPT_EN_DEFAULT 0x00000001
-
-/* NAND :: ACC_CONTROL_CS4 :: PAGE_HIT_EN [24:24] */
-#define BCHP_NAND_ACC_CONTROL_CS4_PAGE_HIT_EN_MASK 0x01000000
-#define BCHP_NAND_ACC_CONTROL_CS4_PAGE_HIT_EN_SHIFT 24
-#define BCHP_NAND_ACC_CONTROL_CS4_PAGE_HIT_EN_DEFAULT 0x00000001
-
-/* NAND :: ACC_CONTROL_CS4 :: PREFETCH_EN [23:23] */
-#define BCHP_NAND_ACC_CONTROL_CS4_PREFETCH_EN_MASK 0x00800000
-#define BCHP_NAND_ACC_CONTROL_CS4_PREFETCH_EN_SHIFT 23
-#define BCHP_NAND_ACC_CONTROL_CS4_PREFETCH_EN_DEFAULT 0x00000000
-
-/* NAND :: ACC_CONTROL_CS4 :: CACHE_MODE_EN [22:22] */
-#define BCHP_NAND_ACC_CONTROL_CS4_CACHE_MODE_EN_MASK 0x00400000
-#define BCHP_NAND_ACC_CONTROL_CS4_CACHE_MODE_EN_SHIFT 22
-#define BCHP_NAND_ACC_CONTROL_CS4_CACHE_MODE_EN_DEFAULT 0x00000000
-
-/* NAND :: ACC_CONTROL_CS4 :: reserved1 [21:21] */
-#define BCHP_NAND_ACC_CONTROL_CS4_reserved1_MASK 0x00200000
-#define BCHP_NAND_ACC_CONTROL_CS4_reserved1_SHIFT 21
-
-/* NAND :: ACC_CONTROL_CS4 :: ECC_LEVEL [20:16] */
-#define BCHP_NAND_ACC_CONTROL_CS4_ECC_LEVEL_MASK 0x001f0000
-#define BCHP_NAND_ACC_CONTROL_CS4_ECC_LEVEL_SHIFT 16
-#define BCHP_NAND_ACC_CONTROL_CS4_ECC_LEVEL_DEFAULT 0x0000000f
-
-/* NAND :: ACC_CONTROL_CS4 :: reserved2 [15:08] */
-#define BCHP_NAND_ACC_CONTROL_CS4_reserved2_MASK 0x0000ff00
-#define BCHP_NAND_ACC_CONTROL_CS4_reserved2_SHIFT 8
-
-/* NAND :: ACC_CONTROL_CS4 :: SECTOR_SIZE_1K [07:07] */
-#define BCHP_NAND_ACC_CONTROL_CS4_SECTOR_SIZE_1K_MASK 0x00000080
-#define BCHP_NAND_ACC_CONTROL_CS4_SECTOR_SIZE_1K_SHIFT 7
-#define BCHP_NAND_ACC_CONTROL_CS4_SECTOR_SIZE_1K_DEFAULT 0x00000000
-
-/* NAND :: ACC_CONTROL_CS4 :: SPARE_AREA_SIZE [06:00] */
-#define BCHP_NAND_ACC_CONTROL_CS4_SPARE_AREA_SIZE_MASK 0x0000007f
-#define BCHP_NAND_ACC_CONTROL_CS4_SPARE_AREA_SIZE_SHIFT 0
-#define BCHP_NAND_ACC_CONTROL_CS4_SPARE_AREA_SIZE_DEFAULT 0x00000010
-
-/***************************************************************************
- *CONFIG_CS4 - Nand Flash Config
- ***************************************************************************/
-/* NAND :: CONFIG_CS4 :: CONFIG_LOCK [31:31] */
-#define BCHP_NAND_CONFIG_CS4_CONFIG_LOCK_MASK 0x80000000
-#define BCHP_NAND_CONFIG_CS4_CONFIG_LOCK_SHIFT 31
-#define BCHP_NAND_CONFIG_CS4_CONFIG_LOCK_DEFAULT 0x00000000
-
-/* NAND :: CONFIG_CS4 :: BLOCK_SIZE [30:28] */
-#define BCHP_NAND_CONFIG_CS4_BLOCK_SIZE_MASK 0x70000000
-#define BCHP_NAND_CONFIG_CS4_BLOCK_SIZE_SHIFT 28
-#define BCHP_NAND_CONFIG_CS4_BLOCK_SIZE_BK_SIZE_2048KB 6
-#define BCHP_NAND_CONFIG_CS4_BLOCK_SIZE_BK_SIZE_1024KB 5
-#define BCHP_NAND_CONFIG_CS4_BLOCK_SIZE_BK_SIZE_512KB 4
-#define BCHP_NAND_CONFIG_CS4_BLOCK_SIZE_BK_SIZE_256KB 3
-#define BCHP_NAND_CONFIG_CS4_BLOCK_SIZE_BK_SIZE_128KB 2
-#define BCHP_NAND_CONFIG_CS4_BLOCK_SIZE_BK_SIZE_16KB 1
-#define BCHP_NAND_CONFIG_CS4_BLOCK_SIZE_BK_SIZE_8KB 0
-
-/* NAND :: CONFIG_CS4 :: DEVICE_SIZE [27:24] */
-#define BCHP_NAND_CONFIG_CS4_DEVICE_SIZE_MASK 0x0f000000
-#define BCHP_NAND_CONFIG_CS4_DEVICE_SIZE_SHIFT 24
-#define BCHP_NAND_CONFIG_CS4_DEVICE_SIZE_DVC_SIZE_4MB 0
-#define BCHP_NAND_CONFIG_CS4_DEVICE_SIZE_DVC_SIZE_8MB 1
-#define BCHP_NAND_CONFIG_CS4_DEVICE_SIZE_DVC_SIZE_16MB 2
-#define BCHP_NAND_CONFIG_CS4_DEVICE_SIZE_DVC_SIZE_32MB 3
-#define BCHP_NAND_CONFIG_CS4_DEVICE_SIZE_DVC_SIZE_64MB 4
-#define BCHP_NAND_CONFIG_CS4_DEVICE_SIZE_DVC_SIZE_128MB 5
-#define BCHP_NAND_CONFIG_CS4_DEVICE_SIZE_DVC_SIZE_256MB 6
-#define BCHP_NAND_CONFIG_CS4_DEVICE_SIZE_DVC_SIZE_512MB 7
-#define BCHP_NAND_CONFIG_CS4_DEVICE_SIZE_DVC_SIZE_1GB 8
-#define BCHP_NAND_CONFIG_CS4_DEVICE_SIZE_DVC_SIZE_2GB 9
-#define BCHP_NAND_CONFIG_CS4_DEVICE_SIZE_DVC_SIZE_4GB 10
-#define BCHP_NAND_CONFIG_CS4_DEVICE_SIZE_DVC_SIZE_8GB 11
-#define BCHP_NAND_CONFIG_CS4_DEVICE_SIZE_DVC_SIZE_16GB 12
-#define BCHP_NAND_CONFIG_CS4_DEVICE_SIZE_DVC_SIZE_32GB 13
-#define BCHP_NAND_CONFIG_CS4_DEVICE_SIZE_DVC_SIZE_64GB 14
-#define BCHP_NAND_CONFIG_CS4_DEVICE_SIZE_DVC_SIZE_128GB 15
-
-/* NAND :: CONFIG_CS4 :: DEVICE_WIDTH [23:23] */
-#define BCHP_NAND_CONFIG_CS4_DEVICE_WIDTH_MASK 0x00800000
-#define BCHP_NAND_CONFIG_CS4_DEVICE_WIDTH_SHIFT 23
-#define BCHP_NAND_CONFIG_CS4_DEVICE_WIDTH_DVC_WIDTH_8 0
-#define BCHP_NAND_CONFIG_CS4_DEVICE_WIDTH_DVC_WIDTH_16 1
-
-/* NAND :: CONFIG_CS4 :: reserved0 [22:22] */
-#define BCHP_NAND_CONFIG_CS4_reserved0_MASK 0x00400000
-#define BCHP_NAND_CONFIG_CS4_reserved0_SHIFT 22
-
-/* NAND :: CONFIG_CS4 :: PAGE_SIZE [21:20] */
-#define BCHP_NAND_CONFIG_CS4_PAGE_SIZE_MASK 0x00300000
-#define BCHP_NAND_CONFIG_CS4_PAGE_SIZE_SHIFT 20
-#define BCHP_NAND_CONFIG_CS4_PAGE_SIZE_PG_SIZE_512 0
-#define BCHP_NAND_CONFIG_CS4_PAGE_SIZE_PG_SIZE_2KB 1
-#define BCHP_NAND_CONFIG_CS4_PAGE_SIZE_PG_SIZE_4KB 2
-#define BCHP_NAND_CONFIG_CS4_PAGE_SIZE_PG_SIZE_8KB 3
-
-/* NAND :: CONFIG_CS4 :: reserved1 [19:19] */
-#define BCHP_NAND_CONFIG_CS4_reserved1_MASK 0x00080000
-#define BCHP_NAND_CONFIG_CS4_reserved1_SHIFT 19
-
-/* NAND :: CONFIG_CS4 :: FUL_ADR_BYTES [18:16] */
-#define BCHP_NAND_CONFIG_CS4_FUL_ADR_BYTES_MASK 0x00070000
-#define BCHP_NAND_CONFIG_CS4_FUL_ADR_BYTES_SHIFT 16
-
-/* NAND :: CONFIG_CS4 :: reserved2 [15:15] */
-#define BCHP_NAND_CONFIG_CS4_reserved2_MASK 0x00008000
-#define BCHP_NAND_CONFIG_CS4_reserved2_SHIFT 15
-
-/* NAND :: CONFIG_CS4 :: COL_ADR_BYTES [14:12] */
-#define BCHP_NAND_CONFIG_CS4_COL_ADR_BYTES_MASK 0x00007000
-#define BCHP_NAND_CONFIG_CS4_COL_ADR_BYTES_SHIFT 12
-
-/* NAND :: CONFIG_CS4 :: reserved3 [11:11] */
-#define BCHP_NAND_CONFIG_CS4_reserved3_MASK 0x00000800
-#define BCHP_NAND_CONFIG_CS4_reserved3_SHIFT 11
-
-/* NAND :: CONFIG_CS4 :: BLK_ADR_BYTES [10:08] */
-#define BCHP_NAND_CONFIG_CS4_BLK_ADR_BYTES_MASK 0x00000700
-#define BCHP_NAND_CONFIG_CS4_BLK_ADR_BYTES_SHIFT 8
-
-/* NAND :: CONFIG_CS4 :: reserved4 [07:00] */
-#define BCHP_NAND_CONFIG_CS4_reserved4_MASK 0x000000ff
-#define BCHP_NAND_CONFIG_CS4_reserved4_SHIFT 0
-
-/***************************************************************************
- *TIMING_1_CS4 - Nand Flash Timing Parameters 1
- ***************************************************************************/
-/* NAND :: TIMING_1_CS4 :: tWP [31:28] */
-#define BCHP_NAND_TIMING_1_CS4_tWP_MASK 0xf0000000
-#define BCHP_NAND_TIMING_1_CS4_tWP_SHIFT 28
-#define BCHP_NAND_TIMING_1_CS4_tWP_DEFAULT 0x00000006
-
-/* NAND :: TIMING_1_CS4 :: tWH [27:24] */
-#define BCHP_NAND_TIMING_1_CS4_tWH_MASK 0x0f000000
-#define BCHP_NAND_TIMING_1_CS4_tWH_SHIFT 24
-#define BCHP_NAND_TIMING_1_CS4_tWH_DEFAULT 0x00000005
-
-/* NAND :: TIMING_1_CS4 :: tRP [23:20] */
-#define BCHP_NAND_TIMING_1_CS4_tRP_MASK 0x00f00000
-#define BCHP_NAND_TIMING_1_CS4_tRP_SHIFT 20
-#define BCHP_NAND_TIMING_1_CS4_tRP_DEFAULT 0x00000007
-
-/* NAND :: TIMING_1_CS4 :: tREH [19:16] */
-#define BCHP_NAND_TIMING_1_CS4_tREH_MASK 0x000f0000
-#define BCHP_NAND_TIMING_1_CS4_tREH_SHIFT 16
-#define BCHP_NAND_TIMING_1_CS4_tREH_DEFAULT 0x00000004
-
-/* NAND :: TIMING_1_CS4 :: tCS [15:12] */
-#define BCHP_NAND_TIMING_1_CS4_tCS_MASK 0x0000f000
-#define BCHP_NAND_TIMING_1_CS4_tCS_SHIFT 12
-#define BCHP_NAND_TIMING_1_CS4_tCS_DEFAULT 0x00000008
-
-/* NAND :: TIMING_1_CS4 :: tCLH [11:08] */
-#define BCHP_NAND_TIMING_1_CS4_tCLH_MASK 0x00000f00
-#define BCHP_NAND_TIMING_1_CS4_tCLH_SHIFT 8
-#define BCHP_NAND_TIMING_1_CS4_tCLH_DEFAULT 0x00000004
-
-/* NAND :: TIMING_1_CS4 :: tALH [07:04] */
-#define BCHP_NAND_TIMING_1_CS4_tALH_MASK 0x000000f0
-#define BCHP_NAND_TIMING_1_CS4_tALH_SHIFT 4
-#define BCHP_NAND_TIMING_1_CS4_tALH_DEFAULT 0x00000005
-
-/* NAND :: TIMING_1_CS4 :: tADL [03:00] */
-#define BCHP_NAND_TIMING_1_CS4_tADL_MASK 0x0000000f
-#define BCHP_NAND_TIMING_1_CS4_tADL_SHIFT 0
-#define BCHP_NAND_TIMING_1_CS4_tADL_DEFAULT 0x0000000b
-
-/***************************************************************************
- *TIMING_2_CS4 - Nand Flash Timing Parameters 2
- ***************************************************************************/
-/* NAND :: TIMING_2_CS4 :: CLK_SELECT [31:31] */
-#define BCHP_NAND_TIMING_2_CS4_CLK_SELECT_MASK 0x80000000
-#define BCHP_NAND_TIMING_2_CS4_CLK_SELECT_SHIFT 31
-#define BCHP_NAND_TIMING_2_CS4_CLK_SELECT_DEFAULT 0x00000000
-#define BCHP_NAND_TIMING_2_CS4_CLK_SELECT_CLK_108 0
-#define BCHP_NAND_TIMING_2_CS4_CLK_SELECT_CLK_216 1
-
-/* NAND :: TIMING_2_CS4 :: reserved0 [30:13] */
-#define BCHP_NAND_TIMING_2_CS4_reserved0_MASK 0x7fffe000
-#define BCHP_NAND_TIMING_2_CS4_reserved0_SHIFT 13
-
-/* NAND :: TIMING_2_CS4 :: tWB [12:09] */
-#define BCHP_NAND_TIMING_2_CS4_tWB_MASK 0x00001e00
-#define BCHP_NAND_TIMING_2_CS4_tWB_SHIFT 9
-#define BCHP_NAND_TIMING_2_CS4_tWB_DEFAULT 0x0000000f
-
-/* NAND :: TIMING_2_CS4 :: tWHR [08:04] */
-#define BCHP_NAND_TIMING_2_CS4_tWHR_MASK 0x000001f0
-#define BCHP_NAND_TIMING_2_CS4_tWHR_SHIFT 4
-#define BCHP_NAND_TIMING_2_CS4_tWHR_DEFAULT 0x00000009
-
-/* NAND :: TIMING_2_CS4 :: tREAD [03:00] */
-#define BCHP_NAND_TIMING_2_CS4_tREAD_MASK 0x0000000f
-#define BCHP_NAND_TIMING_2_CS4_tREAD_SHIFT 0
-#define BCHP_NAND_TIMING_2_CS4_tREAD_DEFAULT 0x00000006
-
-/***************************************************************************
- *ACC_CONTROL_CS5 - Nand Flash Access Control
- ***************************************************************************/
-/* NAND :: ACC_CONTROL_CS5 :: RD_ECC_EN [31:31] */
-#define BCHP_NAND_ACC_CONTROL_CS5_RD_ECC_EN_MASK 0x80000000
-#define BCHP_NAND_ACC_CONTROL_CS5_RD_ECC_EN_SHIFT 31
-#define BCHP_NAND_ACC_CONTROL_CS5_RD_ECC_EN_DEFAULT 0x00000001
-
-/* NAND :: ACC_CONTROL_CS5 :: WR_ECC_EN [30:30] */
-#define BCHP_NAND_ACC_CONTROL_CS5_WR_ECC_EN_MASK 0x40000000
-#define BCHP_NAND_ACC_CONTROL_CS5_WR_ECC_EN_SHIFT 30
-#define BCHP_NAND_ACC_CONTROL_CS5_WR_ECC_EN_DEFAULT 0x00000001
-
-/* NAND :: ACC_CONTROL_CS5 :: CE_CARE [29:29] */
-#define BCHP_NAND_ACC_CONTROL_CS5_CE_CARE_MASK 0x20000000
-#define BCHP_NAND_ACC_CONTROL_CS5_CE_CARE_SHIFT 29
-#define BCHP_NAND_ACC_CONTROL_CS5_CE_CARE_DEFAULT 0x00000000
-
-/* NAND :: ACC_CONTROL_CS5 :: reserved0 [28:28] */
-#define BCHP_NAND_ACC_CONTROL_CS5_reserved0_MASK 0x10000000
-#define BCHP_NAND_ACC_CONTROL_CS5_reserved0_SHIFT 28
-
-/* NAND :: ACC_CONTROL_CS5 :: RD_ERASED_ECC_EN [27:27] */
-#define BCHP_NAND_ACC_CONTROL_CS5_RD_ERASED_ECC_EN_MASK 0x08000000
-#define BCHP_NAND_ACC_CONTROL_CS5_RD_ERASED_ECC_EN_SHIFT 27
-#define BCHP_NAND_ACC_CONTROL_CS5_RD_ERASED_ECC_EN_DEFAULT 0x00000000
-
-/* NAND :: ACC_CONTROL_CS5 :: PARTIAL_PAGE_EN [26:26] */
-#define BCHP_NAND_ACC_CONTROL_CS5_PARTIAL_PAGE_EN_MASK 0x04000000
-#define BCHP_NAND_ACC_CONTROL_CS5_PARTIAL_PAGE_EN_SHIFT 26
-#define BCHP_NAND_ACC_CONTROL_CS5_PARTIAL_PAGE_EN_DEFAULT 0x00000000
-
-/* NAND :: ACC_CONTROL_CS5 :: WR_PREEMPT_EN [25:25] */
-#define BCHP_NAND_ACC_CONTROL_CS5_WR_PREEMPT_EN_MASK 0x02000000
-#define BCHP_NAND_ACC_CONTROL_CS5_WR_PREEMPT_EN_SHIFT 25
-#define BCHP_NAND_ACC_CONTROL_CS5_WR_PREEMPT_EN_DEFAULT 0x00000001
-
-/* NAND :: ACC_CONTROL_CS5 :: PAGE_HIT_EN [24:24] */
-#define BCHP_NAND_ACC_CONTROL_CS5_PAGE_HIT_EN_MASK 0x01000000
-#define BCHP_NAND_ACC_CONTROL_CS5_PAGE_HIT_EN_SHIFT 24
-#define BCHP_NAND_ACC_CONTROL_CS5_PAGE_HIT_EN_DEFAULT 0x00000001
-
-/* NAND :: ACC_CONTROL_CS5 :: PREFETCH_EN [23:23] */
-#define BCHP_NAND_ACC_CONTROL_CS5_PREFETCH_EN_MASK 0x00800000
-#define BCHP_NAND_ACC_CONTROL_CS5_PREFETCH_EN_SHIFT 23
-#define BCHP_NAND_ACC_CONTROL_CS5_PREFETCH_EN_DEFAULT 0x00000000
-
-/* NAND :: ACC_CONTROL_CS5 :: CACHE_MODE_EN [22:22] */
-#define BCHP_NAND_ACC_CONTROL_CS5_CACHE_MODE_EN_MASK 0x00400000
-#define BCHP_NAND_ACC_CONTROL_CS5_CACHE_MODE_EN_SHIFT 22
-#define BCHP_NAND_ACC_CONTROL_CS5_CACHE_MODE_EN_DEFAULT 0x00000000
-
-/* NAND :: ACC_CONTROL_CS5 :: reserved1 [21:21] */
-#define BCHP_NAND_ACC_CONTROL_CS5_reserved1_MASK 0x00200000
-#define BCHP_NAND_ACC_CONTROL_CS5_reserved1_SHIFT 21
-
-/* NAND :: ACC_CONTROL_CS5 :: ECC_LEVEL [20:16] */
-#define BCHP_NAND_ACC_CONTROL_CS5_ECC_LEVEL_MASK 0x001f0000
-#define BCHP_NAND_ACC_CONTROL_CS5_ECC_LEVEL_SHIFT 16
-#define BCHP_NAND_ACC_CONTROL_CS5_ECC_LEVEL_DEFAULT 0x0000000f
-
-/* NAND :: ACC_CONTROL_CS5 :: reserved2 [15:08] */
-#define BCHP_NAND_ACC_CONTROL_CS5_reserved2_MASK 0x0000ff00
-#define BCHP_NAND_ACC_CONTROL_CS5_reserved2_SHIFT 8
-
-/* NAND :: ACC_CONTROL_CS5 :: SECTOR_SIZE_1K [07:07] */
-#define BCHP_NAND_ACC_CONTROL_CS5_SECTOR_SIZE_1K_MASK 0x00000080
-#define BCHP_NAND_ACC_CONTROL_CS5_SECTOR_SIZE_1K_SHIFT 7
-#define BCHP_NAND_ACC_CONTROL_CS5_SECTOR_SIZE_1K_DEFAULT 0x00000000
-
-/* NAND :: ACC_CONTROL_CS5 :: SPARE_AREA_SIZE [06:00] */
-#define BCHP_NAND_ACC_CONTROL_CS5_SPARE_AREA_SIZE_MASK 0x0000007f
-#define BCHP_NAND_ACC_CONTROL_CS5_SPARE_AREA_SIZE_SHIFT 0
-#define BCHP_NAND_ACC_CONTROL_CS5_SPARE_AREA_SIZE_DEFAULT 0x00000010
-
-/***************************************************************************
- *CONFIG_CS5 - Nand Flash Config
- ***************************************************************************/
-/* NAND :: CONFIG_CS5 :: CONFIG_LOCK [31:31] */
-#define BCHP_NAND_CONFIG_CS5_CONFIG_LOCK_MASK 0x80000000
-#define BCHP_NAND_CONFIG_CS5_CONFIG_LOCK_SHIFT 31
-#define BCHP_NAND_CONFIG_CS5_CONFIG_LOCK_DEFAULT 0x00000000
-
-/* NAND :: CONFIG_CS5 :: BLOCK_SIZE [30:28] */
-#define BCHP_NAND_CONFIG_CS5_BLOCK_SIZE_MASK 0x70000000
-#define BCHP_NAND_CONFIG_CS5_BLOCK_SIZE_SHIFT 28
-#define BCHP_NAND_CONFIG_CS5_BLOCK_SIZE_BK_SIZE_2048KB 6
-#define BCHP_NAND_CONFIG_CS5_BLOCK_SIZE_BK_SIZE_1024KB 5
-#define BCHP_NAND_CONFIG_CS5_BLOCK_SIZE_BK_SIZE_512KB 4
-#define BCHP_NAND_CONFIG_CS5_BLOCK_SIZE_BK_SIZE_256KB 3
-#define BCHP_NAND_CONFIG_CS5_BLOCK_SIZE_BK_SIZE_128KB 2
-#define BCHP_NAND_CONFIG_CS5_BLOCK_SIZE_BK_SIZE_16KB 1
-#define BCHP_NAND_CONFIG_CS5_BLOCK_SIZE_BK_SIZE_8KB 0
-
-/* NAND :: CONFIG_CS5 :: DEVICE_SIZE [27:24] */
-#define BCHP_NAND_CONFIG_CS5_DEVICE_SIZE_MASK 0x0f000000
-#define BCHP_NAND_CONFIG_CS5_DEVICE_SIZE_SHIFT 24
-#define BCHP_NAND_CONFIG_CS5_DEVICE_SIZE_DVC_SIZE_4MB 0
-#define BCHP_NAND_CONFIG_CS5_DEVICE_SIZE_DVC_SIZE_8MB 1
-#define BCHP_NAND_CONFIG_CS5_DEVICE_SIZE_DVC_SIZE_16MB 2
-#define BCHP_NAND_CONFIG_CS5_DEVICE_SIZE_DVC_SIZE_32MB 3
-#define BCHP_NAND_CONFIG_CS5_DEVICE_SIZE_DVC_SIZE_64MB 4
-#define BCHP_NAND_CONFIG_CS5_DEVICE_SIZE_DVC_SIZE_128MB 5
-#define BCHP_NAND_CONFIG_CS5_DEVICE_SIZE_DVC_SIZE_256MB 6
-#define BCHP_NAND_CONFIG_CS5_DEVICE_SIZE_DVC_SIZE_512MB 7
-#define BCHP_NAND_CONFIG_CS5_DEVICE_SIZE_DVC_SIZE_1GB 8
-#define BCHP_NAND_CONFIG_CS5_DEVICE_SIZE_DVC_SIZE_2GB 9
-#define BCHP_NAND_CONFIG_CS5_DEVICE_SIZE_DVC_SIZE_4GB 10
-#define BCHP_NAND_CONFIG_CS5_DEVICE_SIZE_DVC_SIZE_8GB 11
-#define BCHP_NAND_CONFIG_CS5_DEVICE_SIZE_DVC_SIZE_16GB 12
-#define BCHP_NAND_CONFIG_CS5_DEVICE_SIZE_DVC_SIZE_32GB 13
-#define BCHP_NAND_CONFIG_CS5_DEVICE_SIZE_DVC_SIZE_64GB 14
-#define BCHP_NAND_CONFIG_CS5_DEVICE_SIZE_DVC_SIZE_128GB 15
-
-/* NAND :: CONFIG_CS5 :: DEVICE_WIDTH [23:23] */
-#define BCHP_NAND_CONFIG_CS5_DEVICE_WIDTH_MASK 0x00800000
-#define BCHP_NAND_CONFIG_CS5_DEVICE_WIDTH_SHIFT 23
-#define BCHP_NAND_CONFIG_CS5_DEVICE_WIDTH_DVC_WIDTH_8 0
-#define BCHP_NAND_CONFIG_CS5_DEVICE_WIDTH_DVC_WIDTH_16 1
-
-/* NAND :: CONFIG_CS5 :: reserved0 [22:22] */
-#define BCHP_NAND_CONFIG_CS5_reserved0_MASK 0x00400000
-#define BCHP_NAND_CONFIG_CS5_reserved0_SHIFT 22
-
-/* NAND :: CONFIG_CS5 :: PAGE_SIZE [21:20] */
-#define BCHP_NAND_CONFIG_CS5_PAGE_SIZE_MASK 0x00300000
-#define BCHP_NAND_CONFIG_CS5_PAGE_SIZE_SHIFT 20
-#define BCHP_NAND_CONFIG_CS5_PAGE_SIZE_PG_SIZE_512 0
-#define BCHP_NAND_CONFIG_CS5_PAGE_SIZE_PG_SIZE_2KB 1
-#define BCHP_NAND_CONFIG_CS5_PAGE_SIZE_PG_SIZE_4KB 2
-#define BCHP_NAND_CONFIG_CS5_PAGE_SIZE_PG_SIZE_8KB 3
-
-/* NAND :: CONFIG_CS5 :: reserved1 [19:19] */
-#define BCHP_NAND_CONFIG_CS5_reserved1_MASK 0x00080000
-#define BCHP_NAND_CONFIG_CS5_reserved1_SHIFT 19
-
-/* NAND :: CONFIG_CS5 :: FUL_ADR_BYTES [18:16] */
-#define BCHP_NAND_CONFIG_CS5_FUL_ADR_BYTES_MASK 0x00070000
-#define BCHP_NAND_CONFIG_CS5_FUL_ADR_BYTES_SHIFT 16
-
-/* NAND :: CONFIG_CS5 :: reserved2 [15:15] */
-#define BCHP_NAND_CONFIG_CS5_reserved2_MASK 0x00008000
-#define BCHP_NAND_CONFIG_CS5_reserved2_SHIFT 15
-
-/* NAND :: CONFIG_CS5 :: COL_ADR_BYTES [14:12] */
-#define BCHP_NAND_CONFIG_CS5_COL_ADR_BYTES_MASK 0x00007000
-#define BCHP_NAND_CONFIG_CS5_COL_ADR_BYTES_SHIFT 12
-
-/* NAND :: CONFIG_CS5 :: reserved3 [11:11] */
-#define BCHP_NAND_CONFIG_CS5_reserved3_MASK 0x00000800
-#define BCHP_NAND_CONFIG_CS5_reserved3_SHIFT 11
-
-/* NAND :: CONFIG_CS5 :: BLK_ADR_BYTES [10:08] */
-#define BCHP_NAND_CONFIG_CS5_BLK_ADR_BYTES_MASK 0x00000700
-#define BCHP_NAND_CONFIG_CS5_BLK_ADR_BYTES_SHIFT 8
-
-/* NAND :: CONFIG_CS5 :: reserved4 [07:00] */
-#define BCHP_NAND_CONFIG_CS5_reserved4_MASK 0x000000ff
-#define BCHP_NAND_CONFIG_CS5_reserved4_SHIFT 0
-
-/***************************************************************************
- *TIMING_1_CS5 - Nand Flash Timing Parameters 1
- ***************************************************************************/
-/* NAND :: TIMING_1_CS5 :: tWP [31:28] */
-#define BCHP_NAND_TIMING_1_CS5_tWP_MASK 0xf0000000
-#define BCHP_NAND_TIMING_1_CS5_tWP_SHIFT 28
-#define BCHP_NAND_TIMING_1_CS5_tWP_DEFAULT 0x00000006
-
-/* NAND :: TIMING_1_CS5 :: tWH [27:24] */
-#define BCHP_NAND_TIMING_1_CS5_tWH_MASK 0x0f000000
-#define BCHP_NAND_TIMING_1_CS5_tWH_SHIFT 24
-#define BCHP_NAND_TIMING_1_CS5_tWH_DEFAULT 0x00000005
-
-/* NAND :: TIMING_1_CS5 :: tRP [23:20] */
-#define BCHP_NAND_TIMING_1_CS5_tRP_MASK 0x00f00000
-#define BCHP_NAND_TIMING_1_CS5_tRP_SHIFT 20
-#define BCHP_NAND_TIMING_1_CS5_tRP_DEFAULT 0x00000007
-
-/* NAND :: TIMING_1_CS5 :: tREH [19:16] */
-#define BCHP_NAND_TIMING_1_CS5_tREH_MASK 0x000f0000
-#define BCHP_NAND_TIMING_1_CS5_tREH_SHIFT 16
-#define BCHP_NAND_TIMING_1_CS5_tREH_DEFAULT 0x00000004
-
-/* NAND :: TIMING_1_CS5 :: tCS [15:12] */
-#define BCHP_NAND_TIMING_1_CS5_tCS_MASK 0x0000f000
-#define BCHP_NAND_TIMING_1_CS5_tCS_SHIFT 12
-#define BCHP_NAND_TIMING_1_CS5_tCS_DEFAULT 0x00000008
-
-/* NAND :: TIMING_1_CS5 :: tCLH [11:08] */
-#define BCHP_NAND_TIMING_1_CS5_tCLH_MASK 0x00000f00
-#define BCHP_NAND_TIMING_1_CS5_tCLH_SHIFT 8
-#define BCHP_NAND_TIMING_1_CS5_tCLH_DEFAULT 0x00000004
-
-/* NAND :: TIMING_1_CS5 :: tALH [07:04] */
-#define BCHP_NAND_TIMING_1_CS5_tALH_MASK 0x000000f0
-#define BCHP_NAND_TIMING_1_CS5_tALH_SHIFT 4
-#define BCHP_NAND_TIMING_1_CS5_tALH_DEFAULT 0x00000005
-
-/* NAND :: TIMING_1_CS5 :: tADL [03:00] */
-#define BCHP_NAND_TIMING_1_CS5_tADL_MASK 0x0000000f
-#define BCHP_NAND_TIMING_1_CS5_tADL_SHIFT 0
-#define BCHP_NAND_TIMING_1_CS5_tADL_DEFAULT 0x0000000b
-
-/***************************************************************************
- *TIMING_2_CS5 - Nand Flash Timing Parameters 2
- ***************************************************************************/
-/* NAND :: TIMING_2_CS5 :: CLK_SELECT [31:31] */
-#define BCHP_NAND_TIMING_2_CS5_CLK_SELECT_MASK 0x80000000
-#define BCHP_NAND_TIMING_2_CS5_CLK_SELECT_SHIFT 31
-#define BCHP_NAND_TIMING_2_CS5_CLK_SELECT_DEFAULT 0x00000000
-#define BCHP_NAND_TIMING_2_CS5_CLK_SELECT_CLK_108 0
-#define BCHP_NAND_TIMING_2_CS5_CLK_SELECT_CLK_216 1
-
-/* NAND :: TIMING_2_CS5 :: reserved0 [30:13] */
-#define BCHP_NAND_TIMING_2_CS5_reserved0_MASK 0x7fffe000
-#define BCHP_NAND_TIMING_2_CS5_reserved0_SHIFT 13
-
-/* NAND :: TIMING_2_CS5 :: tWB [12:09] */
-#define BCHP_NAND_TIMING_2_CS5_tWB_MASK 0x00001e00
-#define BCHP_NAND_TIMING_2_CS5_tWB_SHIFT 9
-#define BCHP_NAND_TIMING_2_CS5_tWB_DEFAULT 0x0000000f
-
-/* NAND :: TIMING_2_CS5 :: tWHR [08:04] */
-#define BCHP_NAND_TIMING_2_CS5_tWHR_MASK 0x000001f0
-#define BCHP_NAND_TIMING_2_CS5_tWHR_SHIFT 4
-#define BCHP_NAND_TIMING_2_CS5_tWHR_DEFAULT 0x00000009
-
-/* NAND :: TIMING_2_CS5 :: tREAD [03:00] */
-#define BCHP_NAND_TIMING_2_CS5_tREAD_MASK 0x0000000f
-#define BCHP_NAND_TIMING_2_CS5_tREAD_SHIFT 0
-#define BCHP_NAND_TIMING_2_CS5_tREAD_DEFAULT 0x00000006
-
-/***************************************************************************
- *ACC_CONTROL_CS6 - Nand Flash Access Control
- ***************************************************************************/
-/* NAND :: ACC_CONTROL_CS6 :: RD_ECC_EN [31:31] */
-#define BCHP_NAND_ACC_CONTROL_CS6_RD_ECC_EN_MASK 0x80000000
-#define BCHP_NAND_ACC_CONTROL_CS6_RD_ECC_EN_SHIFT 31
-#define BCHP_NAND_ACC_CONTROL_CS6_RD_ECC_EN_DEFAULT 0x00000001
-
-/* NAND :: ACC_CONTROL_CS6 :: WR_ECC_EN [30:30] */
-#define BCHP_NAND_ACC_CONTROL_CS6_WR_ECC_EN_MASK 0x40000000
-#define BCHP_NAND_ACC_CONTROL_CS6_WR_ECC_EN_SHIFT 30
-#define BCHP_NAND_ACC_CONTROL_CS6_WR_ECC_EN_DEFAULT 0x00000001
-
-/* NAND :: ACC_CONTROL_CS6 :: CE_CARE [29:29] */
-#define BCHP_NAND_ACC_CONTROL_CS6_CE_CARE_MASK 0x20000000
-#define BCHP_NAND_ACC_CONTROL_CS6_CE_CARE_SHIFT 29
-#define BCHP_NAND_ACC_CONTROL_CS6_CE_CARE_DEFAULT 0x00000000
-
-/* NAND :: ACC_CONTROL_CS6 :: reserved0 [28:28] */
-#define BCHP_NAND_ACC_CONTROL_CS6_reserved0_MASK 0x10000000
-#define BCHP_NAND_ACC_CONTROL_CS6_reserved0_SHIFT 28
-
-/* NAND :: ACC_CONTROL_CS6 :: RD_ERASED_ECC_EN [27:27] */
-#define BCHP_NAND_ACC_CONTROL_CS6_RD_ERASED_ECC_EN_MASK 0x08000000
-#define BCHP_NAND_ACC_CONTROL_CS6_RD_ERASED_ECC_EN_SHIFT 27
-#define BCHP_NAND_ACC_CONTROL_CS6_RD_ERASED_ECC_EN_DEFAULT 0x00000000
-
-/* NAND :: ACC_CONTROL_CS6 :: PARTIAL_PAGE_EN [26:26] */
-#define BCHP_NAND_ACC_CONTROL_CS6_PARTIAL_PAGE_EN_MASK 0x04000000
-#define BCHP_NAND_ACC_CONTROL_CS6_PARTIAL_PAGE_EN_SHIFT 26
-#define BCHP_NAND_ACC_CONTROL_CS6_PARTIAL_PAGE_EN_DEFAULT 0x00000000
-
-/* NAND :: ACC_CONTROL_CS6 :: WR_PREEMPT_EN [25:25] */
-#define BCHP_NAND_ACC_CONTROL_CS6_WR_PREEMPT_EN_MASK 0x02000000
-#define BCHP_NAND_ACC_CONTROL_CS6_WR_PREEMPT_EN_SHIFT 25
-#define BCHP_NAND_ACC_CONTROL_CS6_WR_PREEMPT_EN_DEFAULT 0x00000001
-
-/* NAND :: ACC_CONTROL_CS6 :: PAGE_HIT_EN [24:24] */
-#define BCHP_NAND_ACC_CONTROL_CS6_PAGE_HIT_EN_MASK 0x01000000
-#define BCHP_NAND_ACC_CONTROL_CS6_PAGE_HIT_EN_SHIFT 24
-#define BCHP_NAND_ACC_CONTROL_CS6_PAGE_HIT_EN_DEFAULT 0x00000001
-
-/* NAND :: ACC_CONTROL_CS6 :: PREFETCH_EN [23:23] */
-#define BCHP_NAND_ACC_CONTROL_CS6_PREFETCH_EN_MASK 0x00800000
-#define BCHP_NAND_ACC_CONTROL_CS6_PREFETCH_EN_SHIFT 23
-#define BCHP_NAND_ACC_CONTROL_CS6_PREFETCH_EN_DEFAULT 0x00000000
-
-/* NAND :: ACC_CONTROL_CS6 :: CACHE_MODE_EN [22:22] */
-#define BCHP_NAND_ACC_CONTROL_CS6_CACHE_MODE_EN_MASK 0x00400000
-#define BCHP_NAND_ACC_CONTROL_CS6_CACHE_MODE_EN_SHIFT 22
-#define BCHP_NAND_ACC_CONTROL_CS6_CACHE_MODE_EN_DEFAULT 0x00000000
-
-/* NAND :: ACC_CONTROL_CS6 :: reserved1 [21:21] */
-#define BCHP_NAND_ACC_CONTROL_CS6_reserved1_MASK 0x00200000
-#define BCHP_NAND_ACC_CONTROL_CS6_reserved1_SHIFT 21
-
-/* NAND :: ACC_CONTROL_CS6 :: ECC_LEVEL [20:16] */
-#define BCHP_NAND_ACC_CONTROL_CS6_ECC_LEVEL_MASK 0x001f0000
-#define BCHP_NAND_ACC_CONTROL_CS6_ECC_LEVEL_SHIFT 16
-#define BCHP_NAND_ACC_CONTROL_CS6_ECC_LEVEL_DEFAULT 0x0000000f
-
-/* NAND :: ACC_CONTROL_CS6 :: reserved2 [15:08] */
-#define BCHP_NAND_ACC_CONTROL_CS6_reserved2_MASK 0x0000ff00
-#define BCHP_NAND_ACC_CONTROL_CS6_reserved2_SHIFT 8
-
-/* NAND :: ACC_CONTROL_CS6 :: SECTOR_SIZE_1K [07:07] */
-#define BCHP_NAND_ACC_CONTROL_CS6_SECTOR_SIZE_1K_MASK 0x00000080
-#define BCHP_NAND_ACC_CONTROL_CS6_SECTOR_SIZE_1K_SHIFT 7
-#define BCHP_NAND_ACC_CONTROL_CS6_SECTOR_SIZE_1K_DEFAULT 0x00000000
-
-/* NAND :: ACC_CONTROL_CS6 :: SPARE_AREA_SIZE [06:00] */
-#define BCHP_NAND_ACC_CONTROL_CS6_SPARE_AREA_SIZE_MASK 0x0000007f
-#define BCHP_NAND_ACC_CONTROL_CS6_SPARE_AREA_SIZE_SHIFT 0
-#define BCHP_NAND_ACC_CONTROL_CS6_SPARE_AREA_SIZE_DEFAULT 0x00000010
-
-/***************************************************************************
- *CONFIG_CS6 - Nand Flash Config
- ***************************************************************************/
-/* NAND :: CONFIG_CS6 :: CONFIG_LOCK [31:31] */
-#define BCHP_NAND_CONFIG_CS6_CONFIG_LOCK_MASK 0x80000000
-#define BCHP_NAND_CONFIG_CS6_CONFIG_LOCK_SHIFT 31
-#define BCHP_NAND_CONFIG_CS6_CONFIG_LOCK_DEFAULT 0x00000000
-
-/* NAND :: CONFIG_CS6 :: BLOCK_SIZE [30:28] */
-#define BCHP_NAND_CONFIG_CS6_BLOCK_SIZE_MASK 0x70000000
-#define BCHP_NAND_CONFIG_CS6_BLOCK_SIZE_SHIFT 28
-#define BCHP_NAND_CONFIG_CS6_BLOCK_SIZE_BK_SIZE_2048KB 6
-#define BCHP_NAND_CONFIG_CS6_BLOCK_SIZE_BK_SIZE_1024KB 5
-#define BCHP_NAND_CONFIG_CS6_BLOCK_SIZE_BK_SIZE_512KB 4
-#define BCHP_NAND_CONFIG_CS6_BLOCK_SIZE_BK_SIZE_256KB 3
-#define BCHP_NAND_CONFIG_CS6_BLOCK_SIZE_BK_SIZE_128KB 2
-#define BCHP_NAND_CONFIG_CS6_BLOCK_SIZE_BK_SIZE_16KB 1
-#define BCHP_NAND_CONFIG_CS6_BLOCK_SIZE_BK_SIZE_8KB 0
-
-/* NAND :: CONFIG_CS6 :: DEVICE_SIZE [27:24] */
-#define BCHP_NAND_CONFIG_CS6_DEVICE_SIZE_MASK 0x0f000000
-#define BCHP_NAND_CONFIG_CS6_DEVICE_SIZE_SHIFT 24
-#define BCHP_NAND_CONFIG_CS6_DEVICE_SIZE_DVC_SIZE_4MB 0
-#define BCHP_NAND_CONFIG_CS6_DEVICE_SIZE_DVC_SIZE_8MB 1
-#define BCHP_NAND_CONFIG_CS6_DEVICE_SIZE_DVC_SIZE_16MB 2
-#define BCHP_NAND_CONFIG_CS6_DEVICE_SIZE_DVC_SIZE_32MB 3
-#define BCHP_NAND_CONFIG_CS6_DEVICE_SIZE_DVC_SIZE_64MB 4
-#define BCHP_NAND_CONFIG_CS6_DEVICE_SIZE_DVC_SIZE_128MB 5
-#define BCHP_NAND_CONFIG_CS6_DEVICE_SIZE_DVC_SIZE_256MB 6
-#define BCHP_NAND_CONFIG_CS6_DEVICE_SIZE_DVC_SIZE_512MB 7
-#define BCHP_NAND_CONFIG_CS6_DEVICE_SIZE_DVC_SIZE_1GB 8
-#define BCHP_NAND_CONFIG_CS6_DEVICE_SIZE_DVC_SIZE_2GB 9
-#define BCHP_NAND_CONFIG_CS6_DEVICE_SIZE_DVC_SIZE_4GB 10
-#define BCHP_NAND_CONFIG_CS6_DEVICE_SIZE_DVC_SIZE_8GB 11
-#define BCHP_NAND_CONFIG_CS6_DEVICE_SIZE_DVC_SIZE_16GB 12
-#define BCHP_NAND_CONFIG_CS6_DEVICE_SIZE_DVC_SIZE_32GB 13
-#define BCHP_NAND_CONFIG_CS6_DEVICE_SIZE_DVC_SIZE_64GB 14
-#define BCHP_NAND_CONFIG_CS6_DEVICE_SIZE_DVC_SIZE_128GB 15
-
-/* NAND :: CONFIG_CS6 :: DEVICE_WIDTH [23:23] */
-#define BCHP_NAND_CONFIG_CS6_DEVICE_WIDTH_MASK 0x00800000
-#define BCHP_NAND_CONFIG_CS6_DEVICE_WIDTH_SHIFT 23
-#define BCHP_NAND_CONFIG_CS6_DEVICE_WIDTH_DVC_WIDTH_8 0
-#define BCHP_NAND_CONFIG_CS6_DEVICE_WIDTH_DVC_WIDTH_16 1
-
-/* NAND :: CONFIG_CS6 :: reserved0 [22:22] */
-#define BCHP_NAND_CONFIG_CS6_reserved0_MASK 0x00400000
-#define BCHP_NAND_CONFIG_CS6_reserved0_SHIFT 22
-
-/* NAND :: CONFIG_CS6 :: PAGE_SIZE [21:20] */
-#define BCHP_NAND_CONFIG_CS6_PAGE_SIZE_MASK 0x00300000
-#define BCHP_NAND_CONFIG_CS6_PAGE_SIZE_SHIFT 20
-#define BCHP_NAND_CONFIG_CS6_PAGE_SIZE_PG_SIZE_512 0
-#define BCHP_NAND_CONFIG_CS6_PAGE_SIZE_PG_SIZE_2KB 1
-#define BCHP_NAND_CONFIG_CS6_PAGE_SIZE_PG_SIZE_4KB 2
-#define BCHP_NAND_CONFIG_CS6_PAGE_SIZE_PG_SIZE_8KB 3
-
-/* NAND :: CONFIG_CS6 :: reserved1 [19:19] */
-#define BCHP_NAND_CONFIG_CS6_reserved1_MASK 0x00080000
-#define BCHP_NAND_CONFIG_CS6_reserved1_SHIFT 19
-
-/* NAND :: CONFIG_CS6 :: FUL_ADR_BYTES [18:16] */
-#define BCHP_NAND_CONFIG_CS6_FUL_ADR_BYTES_MASK 0x00070000
-#define BCHP_NAND_CONFIG_CS6_FUL_ADR_BYTES_SHIFT 16
-
-/* NAND :: CONFIG_CS6 :: reserved2 [15:15] */
-#define BCHP_NAND_CONFIG_CS6_reserved2_MASK 0x00008000
-#define BCHP_NAND_CONFIG_CS6_reserved2_SHIFT 15
-
-/* NAND :: CONFIG_CS6 :: COL_ADR_BYTES [14:12] */
-#define BCHP_NAND_CONFIG_CS6_COL_ADR_BYTES_MASK 0x00007000
-#define BCHP_NAND_CONFIG_CS6_COL_ADR_BYTES_SHIFT 12
-
-/* NAND :: CONFIG_CS6 :: reserved3 [11:11] */
-#define BCHP_NAND_CONFIG_CS6_reserved3_MASK 0x00000800
-#define BCHP_NAND_CONFIG_CS6_reserved3_SHIFT 11
-
-/* NAND :: CONFIG_CS6 :: BLK_ADR_BYTES [10:08] */
-#define BCHP_NAND_CONFIG_CS6_BLK_ADR_BYTES_MASK 0x00000700
-#define BCHP_NAND_CONFIG_CS6_BLK_ADR_BYTES_SHIFT 8
-
-/* NAND :: CONFIG_CS6 :: reserved4 [07:00] */
-#define BCHP_NAND_CONFIG_CS6_reserved4_MASK 0x000000ff
-#define BCHP_NAND_CONFIG_CS6_reserved4_SHIFT 0
-
-/***************************************************************************
- *TIMING_1_CS6 - Nand Flash Timing Parameters 1
- ***************************************************************************/
-/* NAND :: TIMING_1_CS6 :: tWP [31:28] */
-#define BCHP_NAND_TIMING_1_CS6_tWP_MASK 0xf0000000
-#define BCHP_NAND_TIMING_1_CS6_tWP_SHIFT 28
-#define BCHP_NAND_TIMING_1_CS6_tWP_DEFAULT 0x00000006
-
-/* NAND :: TIMING_1_CS6 :: tWH [27:24] */
-#define BCHP_NAND_TIMING_1_CS6_tWH_MASK 0x0f000000
-#define BCHP_NAND_TIMING_1_CS6_tWH_SHIFT 24
-#define BCHP_NAND_TIMING_1_CS6_tWH_DEFAULT 0x00000005
-
-/* NAND :: TIMING_1_CS6 :: tRP [23:20] */
-#define BCHP_NAND_TIMING_1_CS6_tRP_MASK 0x00f00000
-#define BCHP_NAND_TIMING_1_CS6_tRP_SHIFT 20
-#define BCHP_NAND_TIMING_1_CS6_tRP_DEFAULT 0x00000007
-
-/* NAND :: TIMING_1_CS6 :: tREH [19:16] */
-#define BCHP_NAND_TIMING_1_CS6_tREH_MASK 0x000f0000
-#define BCHP_NAND_TIMING_1_CS6_tREH_SHIFT 16
-#define BCHP_NAND_TIMING_1_CS6_tREH_DEFAULT 0x00000004
-
-/* NAND :: TIMING_1_CS6 :: tCS [15:12] */
-#define BCHP_NAND_TIMING_1_CS6_tCS_MASK 0x0000f000
-#define BCHP_NAND_TIMING_1_CS6_tCS_SHIFT 12
-#define BCHP_NAND_TIMING_1_CS6_tCS_DEFAULT 0x00000008
-
-/* NAND :: TIMING_1_CS6 :: tCLH [11:08] */
-#define BCHP_NAND_TIMING_1_CS6_tCLH_MASK 0x00000f00
-#define BCHP_NAND_TIMING_1_CS6_tCLH_SHIFT 8
-#define BCHP_NAND_TIMING_1_CS6_tCLH_DEFAULT 0x00000004
-
-/* NAND :: TIMING_1_CS6 :: tALH [07:04] */
-#define BCHP_NAND_TIMING_1_CS6_tALH_MASK 0x000000f0
-#define BCHP_NAND_TIMING_1_CS6_tALH_SHIFT 4
-#define BCHP_NAND_TIMING_1_CS6_tALH_DEFAULT 0x00000005
-
-/* NAND :: TIMING_1_CS6 :: tADL [03:00] */
-#define BCHP_NAND_TIMING_1_CS6_tADL_MASK 0x0000000f
-#define BCHP_NAND_TIMING_1_CS6_tADL_SHIFT 0
-#define BCHP_NAND_TIMING_1_CS6_tADL_DEFAULT 0x0000000b
-
-/***************************************************************************
- *TIMING_2_CS6 - Nand Flash Timing Parameters 2
- ***************************************************************************/
-/* NAND :: TIMING_2_CS6 :: CLK_SELECT [31:31] */
-#define BCHP_NAND_TIMING_2_CS6_CLK_SELECT_MASK 0x80000000
-#define BCHP_NAND_TIMING_2_CS6_CLK_SELECT_SHIFT 31
-#define BCHP_NAND_TIMING_2_CS6_CLK_SELECT_DEFAULT 0x00000000
-#define BCHP_NAND_TIMING_2_CS6_CLK_SELECT_CLK_108 0
-#define BCHP_NAND_TIMING_2_CS6_CLK_SELECT_CLK_216 1
-
-/* NAND :: TIMING_2_CS6 :: reserved0 [30:13] */
-#define BCHP_NAND_TIMING_2_CS6_reserved0_MASK 0x7fffe000
-#define BCHP_NAND_TIMING_2_CS6_reserved0_SHIFT 13
-
-/* NAND :: TIMING_2_CS6 :: tWB [12:09] */
-#define BCHP_NAND_TIMING_2_CS6_tWB_MASK 0x00001e00
-#define BCHP_NAND_TIMING_2_CS6_tWB_SHIFT 9
-#define BCHP_NAND_TIMING_2_CS6_tWB_DEFAULT 0x0000000f
-
-/* NAND :: TIMING_2_CS6 :: tWHR [08:04] */
-#define BCHP_NAND_TIMING_2_CS6_tWHR_MASK 0x000001f0
-#define BCHP_NAND_TIMING_2_CS6_tWHR_SHIFT 4
-#define BCHP_NAND_TIMING_2_CS6_tWHR_DEFAULT 0x00000009
-
-/* NAND :: TIMING_2_CS6 :: tREAD [03:00] */
-#define BCHP_NAND_TIMING_2_CS6_tREAD_MASK 0x0000000f
-#define BCHP_NAND_TIMING_2_CS6_tREAD_SHIFT 0
-#define BCHP_NAND_TIMING_2_CS6_tREAD_DEFAULT 0x00000006
-
-/***************************************************************************
- *CORR_STAT_THRESHOLD - Correctable Error Reporting Threshold
- ***************************************************************************/
-/* NAND :: CORR_STAT_THRESHOLD :: reserved0 [31:30] */
-#define BCHP_NAND_CORR_STAT_THRESHOLD_reserved0_MASK 0xc0000000
-#define BCHP_NAND_CORR_STAT_THRESHOLD_reserved0_SHIFT 30
-
-/* NAND :: CORR_STAT_THRESHOLD :: CORR_STAT_THRESHOLD_CS4 [29:24] */
-#define BCHP_NAND_CORR_STAT_THRESHOLD_CORR_STAT_THRESHOLD_CS4_MASK 0x3f000000
-#define BCHP_NAND_CORR_STAT_THRESHOLD_CORR_STAT_THRESHOLD_CS4_SHIFT 24
-#define BCHP_NAND_CORR_STAT_THRESHOLD_CORR_STAT_THRESHOLD_CS4_DEFAULT 0x00000001
-
-/* NAND :: CORR_STAT_THRESHOLD :: CORR_STAT_THRESHOLD_CS3 [23:18] */
-#define BCHP_NAND_CORR_STAT_THRESHOLD_CORR_STAT_THRESHOLD_CS3_MASK 0x00fc0000
-#define BCHP_NAND_CORR_STAT_THRESHOLD_CORR_STAT_THRESHOLD_CS3_SHIFT 18
-#define BCHP_NAND_CORR_STAT_THRESHOLD_CORR_STAT_THRESHOLD_CS3_DEFAULT 0x00000001
-
-/* NAND :: CORR_STAT_THRESHOLD :: CORR_STAT_THRESHOLD_CS2 [17:12] */
-#define BCHP_NAND_CORR_STAT_THRESHOLD_CORR_STAT_THRESHOLD_CS2_MASK 0x0003f000
-#define BCHP_NAND_CORR_STAT_THRESHOLD_CORR_STAT_THRESHOLD_CS2_SHIFT 12
-#define BCHP_NAND_CORR_STAT_THRESHOLD_CORR_STAT_THRESHOLD_CS2_DEFAULT 0x00000001
-
-/* NAND :: CORR_STAT_THRESHOLD :: CORR_STAT_THRESHOLD_CS1 [11:06] */
-#define BCHP_NAND_CORR_STAT_THRESHOLD_CORR_STAT_THRESHOLD_CS1_MASK 0x00000fc0
-#define BCHP_NAND_CORR_STAT_THRESHOLD_CORR_STAT_THRESHOLD_CS1_SHIFT 6
-#define BCHP_NAND_CORR_STAT_THRESHOLD_CORR_STAT_THRESHOLD_CS1_DEFAULT 0x00000001
-
-/* NAND :: CORR_STAT_THRESHOLD :: CORR_STAT_THRESHOLD_CS0 [05:00] */
-#define BCHP_NAND_CORR_STAT_THRESHOLD_CORR_STAT_THRESHOLD_CS0_MASK 0x0000003f
-#define BCHP_NAND_CORR_STAT_THRESHOLD_CORR_STAT_THRESHOLD_CS0_SHIFT 0
-#define BCHP_NAND_CORR_STAT_THRESHOLD_CORR_STAT_THRESHOLD_CS0_DEFAULT 0x00000001
-
-/***************************************************************************
- *CORR_STAT_THRESHOLD_EXT - Correctable Error Reporting Threshold
- ***************************************************************************/
-/* NAND :: CORR_STAT_THRESHOLD_EXT :: reserved0 [31:12] */
-#define BCHP_NAND_CORR_STAT_THRESHOLD_EXT_reserved0_MASK 0xfffff000
-#define BCHP_NAND_CORR_STAT_THRESHOLD_EXT_reserved0_SHIFT 12
-
-/* NAND :: CORR_STAT_THRESHOLD_EXT :: CORR_STAT_THRESHOLD_CS6 [11:06] */
-#define BCHP_NAND_CORR_STAT_THRESHOLD_EXT_CORR_STAT_THRESHOLD_CS6_MASK 0x00000fc0
-#define BCHP_NAND_CORR_STAT_THRESHOLD_EXT_CORR_STAT_THRESHOLD_CS6_SHIFT 6
-#define BCHP_NAND_CORR_STAT_THRESHOLD_EXT_CORR_STAT_THRESHOLD_CS6_DEFAULT 0x00000001
-
-/* NAND :: CORR_STAT_THRESHOLD_EXT :: CORR_STAT_THRESHOLD_CS5 [05:00] */
-#define BCHP_NAND_CORR_STAT_THRESHOLD_EXT_CORR_STAT_THRESHOLD_CS5_MASK 0x0000003f
-#define BCHP_NAND_CORR_STAT_THRESHOLD_EXT_CORR_STAT_THRESHOLD_CS5_SHIFT 0
-#define BCHP_NAND_CORR_STAT_THRESHOLD_EXT_CORR_STAT_THRESHOLD_CS5_DEFAULT 0x00000001
-
-/***************************************************************************
- *BLK_WR_PROTECT - Block Write Protect Enable and Size for EBI_CS0b
- ***************************************************************************/
-/* NAND :: BLK_WR_PROTECT :: BLK_END_ADDR [31:00] */
-#define BCHP_NAND_BLK_WR_PROTECT_BLK_END_ADDR_MASK 0xffffffff
-#define BCHP_NAND_BLK_WR_PROTECT_BLK_END_ADDR_SHIFT 0
-#define BCHP_NAND_BLK_WR_PROTECT_BLK_END_ADDR_DEFAULT 0x00000000
-
-/***************************************************************************
- *MULTIPLANE_OPCODES_1 - Nand Flash Multiplane Customerized Opcodes
- ***************************************************************************/
-/* NAND :: MULTIPLANE_OPCODES_1 :: ERASE_CYC2_OPCODE [31:24] */
-#define BCHP_NAND_MULTIPLANE_OPCODES_1_ERASE_CYC2_OPCODE_MASK 0xff000000
-#define BCHP_NAND_MULTIPLANE_OPCODES_1_ERASE_CYC2_OPCODE_SHIFT 24
-#define BCHP_NAND_MULTIPLANE_OPCODES_1_ERASE_CYC2_OPCODE_DEFAULT 0x000000d1
-
-/* NAND :: MULTIPLANE_OPCODES_1 :: READ_STATUS_OPCODE [23:16] */
-#define BCHP_NAND_MULTIPLANE_OPCODES_1_READ_STATUS_OPCODE_MASK 0x00ff0000
-#define BCHP_NAND_MULTIPLANE_OPCODES_1_READ_STATUS_OPCODE_SHIFT 16
-#define BCHP_NAND_MULTIPLANE_OPCODES_1_READ_STATUS_OPCODE_DEFAULT 0x00000070
-
-/* NAND :: MULTIPLANE_OPCODES_1 :: PROG_ODD_PLANE_OPCODE [15:08] */
-#define BCHP_NAND_MULTIPLANE_OPCODES_1_PROG_ODD_PLANE_OPCODE_MASK 0x0000ff00
-#define BCHP_NAND_MULTIPLANE_OPCODES_1_PROG_ODD_PLANE_OPCODE_SHIFT 8
-#define BCHP_NAND_MULTIPLANE_OPCODES_1_PROG_ODD_PLANE_OPCODE_DEFAULT 0x00000080
-
-/* NAND :: MULTIPLANE_OPCODES_1 :: PROG_TR_OPCODE [07:00] */
-#define BCHP_NAND_MULTIPLANE_OPCODES_1_PROG_TR_OPCODE_MASK 0x000000ff
-#define BCHP_NAND_MULTIPLANE_OPCODES_1_PROG_TR_OPCODE_SHIFT 0
-#define BCHP_NAND_MULTIPLANE_OPCODES_1_PROG_TR_OPCODE_DEFAULT 0x00000010
-
-/***************************************************************************
- *MULTIPLANE_OPCODES_2 - Nand Flash Multiplane Customerized Opcodes
- ***************************************************************************/
-/* NAND :: MULTIPLANE_OPCODES_2 :: PROG_CACHE_TR_OPCODE [31:24] */
-#define BCHP_NAND_MULTIPLANE_OPCODES_2_PROG_CACHE_TR_OPCODE_MASK 0xff000000
-#define BCHP_NAND_MULTIPLANE_OPCODES_2_PROG_CACHE_TR_OPCODE_SHIFT 24
-#define BCHP_NAND_MULTIPLANE_OPCODES_2_PROG_CACHE_TR_OPCODE_DEFAULT 0x00000015
-
-/* NAND :: MULTIPLANE_OPCODES_2 :: TWO_PLANE_READ_STATUS_OPCODE [23:16] */
-#define BCHP_NAND_MULTIPLANE_OPCODES_2_TWO_PLANE_READ_STATUS_OPCODE_MASK 0x00ff0000
-#define BCHP_NAND_MULTIPLANE_OPCODES_2_TWO_PLANE_READ_STATUS_OPCODE_SHIFT 16
-#define BCHP_NAND_MULTIPLANE_OPCODES_2_TWO_PLANE_READ_STATUS_OPCODE_DEFAULT 0x00000078
-
-/* NAND :: MULTIPLANE_OPCODES_2 :: READ_OPCODE [15:08] */
-#define BCHP_NAND_MULTIPLANE_OPCODES_2_READ_OPCODE_MASK 0x0000ff00
-#define BCHP_NAND_MULTIPLANE_OPCODES_2_READ_OPCODE_SHIFT 8
-#define BCHP_NAND_MULTIPLANE_OPCODES_2_READ_OPCODE_DEFAULT 0x00000000
-
-/* NAND :: MULTIPLANE_OPCODES_2 :: READ_RAND_OPCODE [07:00] */
-#define BCHP_NAND_MULTIPLANE_OPCODES_2_READ_RAND_OPCODE_MASK 0x000000ff
-#define BCHP_NAND_MULTIPLANE_OPCODES_2_READ_RAND_OPCODE_SHIFT 0
-#define BCHP_NAND_MULTIPLANE_OPCODES_2_READ_RAND_OPCODE_DEFAULT 0x00000000
-
-/***************************************************************************
- *MULTIPLANE_CTRL - Nand Flash Multiplane Control
- ***************************************************************************/
-/* NAND :: MULTIPLANE_CTRL :: ERASE_CYC2_OP_ENABLE [31:31] */
-#define BCHP_NAND_MULTIPLANE_CTRL_ERASE_CYC2_OP_ENABLE_MASK 0x80000000
-#define BCHP_NAND_MULTIPLANE_CTRL_ERASE_CYC2_OP_ENABLE_SHIFT 31
-#define BCHP_NAND_MULTIPLANE_CTRL_ERASE_CYC2_OP_ENABLE_DEFAULT 0x00000000
-
-/* NAND :: MULTIPLANE_CTRL :: READ_ADR_SIZE [30:30] */
-#define BCHP_NAND_MULTIPLANE_CTRL_READ_ADR_SIZE_MASK 0x40000000
-#define BCHP_NAND_MULTIPLANE_CTRL_READ_ADR_SIZE_SHIFT 30
-#define BCHP_NAND_MULTIPLANE_CTRL_READ_ADR_SIZE_DEFAULT 0x00000000
-
-/* NAND :: MULTIPLANE_CTRL :: READ_CYC_ADR_FLAG [29:29] */
-#define BCHP_NAND_MULTIPLANE_CTRL_READ_CYC_ADR_FLAG_MASK 0x20000000
-#define BCHP_NAND_MULTIPLANE_CTRL_READ_CYC_ADR_FLAG_SHIFT 29
-#define BCHP_NAND_MULTIPLANE_CTRL_READ_CYC_ADR_FLAG_DEFAULT 0x00000000
-
-/* NAND :: MULTIPLANE_CTRL :: READ_NEXT_PAGE_FLAG [28:28] */
-#define BCHP_NAND_MULTIPLANE_CTRL_READ_NEXT_PAGE_FLAG_MASK 0x10000000
-#define BCHP_NAND_MULTIPLANE_CTRL_READ_NEXT_PAGE_FLAG_SHIFT 28
-#define BCHP_NAND_MULTIPLANE_CTRL_READ_NEXT_PAGE_FLAG_DEFAULT 0x00000000
-
-/* NAND :: MULTIPLANE_CTRL :: reserved0 [27:00] */
-#define BCHP_NAND_MULTIPLANE_CTRL_reserved0_MASK 0x0fffffff
-#define BCHP_NAND_MULTIPLANE_CTRL_reserved0_SHIFT 0
-
-/***************************************************************************
- *UNCORR_ERROR_COUNT - Read Uncorrectable Event Count
- ***************************************************************************/
-/* NAND :: UNCORR_ERROR_COUNT :: UNCORR_ERROR_COUNT [31:00] */
-#define BCHP_NAND_UNCORR_ERROR_COUNT_UNCORR_ERROR_COUNT_MASK 0xffffffff
-#define BCHP_NAND_UNCORR_ERROR_COUNT_UNCORR_ERROR_COUNT_SHIFT 0
-#define BCHP_NAND_UNCORR_ERROR_COUNT_UNCORR_ERROR_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *CORR_ERROR_COUNT - Read Error Count
- ***************************************************************************/
-/* NAND :: CORR_ERROR_COUNT :: CORR_ERROR_COUNT [31:00] */
-#define BCHP_NAND_CORR_ERROR_COUNT_CORR_ERROR_COUNT_MASK 0xffffffff
-#define BCHP_NAND_CORR_ERROR_COUNT_CORR_ERROR_COUNT_SHIFT 0
-#define BCHP_NAND_CORR_ERROR_COUNT_CORR_ERROR_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *READ_ERROR_COUNT - Read Error Count
- ***************************************************************************/
-/* NAND :: READ_ERROR_COUNT :: READ_ERROR_COUNT [31:00] */
-#define BCHP_NAND_READ_ERROR_COUNT_READ_ERROR_COUNT_MASK 0xffffffff
-#define BCHP_NAND_READ_ERROR_COUNT_READ_ERROR_COUNT_SHIFT 0
-#define BCHP_NAND_READ_ERROR_COUNT_READ_ERROR_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *BLOCK_LOCK_STATUS - Nand Flash Block Lock Status
- ***************************************************************************/
-/* NAND :: BLOCK_LOCK_STATUS :: reserved0 [31:08] */
-#define BCHP_NAND_BLOCK_LOCK_STATUS_reserved0_MASK 0xffffff00
-#define BCHP_NAND_BLOCK_LOCK_STATUS_reserved0_SHIFT 8
-
-/* NAND :: BLOCK_LOCK_STATUS :: STATUS [07:00] */
-#define BCHP_NAND_BLOCK_LOCK_STATUS_STATUS_MASK 0x000000ff
-#define BCHP_NAND_BLOCK_LOCK_STATUS_STATUS_SHIFT 0
-#define BCHP_NAND_BLOCK_LOCK_STATUS_STATUS_DEFAULT 0x00000000
-
-/***************************************************************************
- *ECC_CORR_EXT_ADDR - ECC Correctable Error Extended Address
- ***************************************************************************/
-/* NAND :: ECC_CORR_EXT_ADDR :: reserved0 [31:19] */
-#define BCHP_NAND_ECC_CORR_EXT_ADDR_reserved0_MASK 0xfff80000
-#define BCHP_NAND_ECC_CORR_EXT_ADDR_reserved0_SHIFT 19
-
-/* NAND :: ECC_CORR_EXT_ADDR :: CS_SEL [18:16] */
-#define BCHP_NAND_ECC_CORR_EXT_ADDR_CS_SEL_MASK 0x00070000
-#define BCHP_NAND_ECC_CORR_EXT_ADDR_CS_SEL_SHIFT 16
-#define BCHP_NAND_ECC_CORR_EXT_ADDR_CS_SEL_DEFAULT 0x00000000
-
-/* NAND :: ECC_CORR_EXT_ADDR :: EXT_ADDRESS [15:00] */
-#define BCHP_NAND_ECC_CORR_EXT_ADDR_EXT_ADDRESS_MASK 0x0000ffff
-#define BCHP_NAND_ECC_CORR_EXT_ADDR_EXT_ADDRESS_SHIFT 0
-#define BCHP_NAND_ECC_CORR_EXT_ADDR_EXT_ADDRESS_DEFAULT 0x00000000
-
-/***************************************************************************
- *ECC_CORR_ADDR - ECC Correctable Error Address
- ***************************************************************************/
-/* NAND :: ECC_CORR_ADDR :: ADDRESS [31:00] */
-#define BCHP_NAND_ECC_CORR_ADDR_ADDRESS_MASK 0xffffffff
-#define BCHP_NAND_ECC_CORR_ADDR_ADDRESS_SHIFT 0
-#define BCHP_NAND_ECC_CORR_ADDR_ADDRESS_DEFAULT 0x00000000
-
-/***************************************************************************
- *ECC_UNC_EXT_ADDR - ECC Uncorrectable Error Extended Address
- ***************************************************************************/
-/* NAND :: ECC_UNC_EXT_ADDR :: reserved0 [31:19] */
-#define BCHP_NAND_ECC_UNC_EXT_ADDR_reserved0_MASK 0xfff80000
-#define BCHP_NAND_ECC_UNC_EXT_ADDR_reserved0_SHIFT 19
-
-/* NAND :: ECC_UNC_EXT_ADDR :: CS_SEL [18:16] */
-#define BCHP_NAND_ECC_UNC_EXT_ADDR_CS_SEL_MASK 0x00070000
-#define BCHP_NAND_ECC_UNC_EXT_ADDR_CS_SEL_SHIFT 16
-#define BCHP_NAND_ECC_UNC_EXT_ADDR_CS_SEL_DEFAULT 0x00000000
-
-/* NAND :: ECC_UNC_EXT_ADDR :: EXT_ADDRESS [15:00] */
-#define BCHP_NAND_ECC_UNC_EXT_ADDR_EXT_ADDRESS_MASK 0x0000ffff
-#define BCHP_NAND_ECC_UNC_EXT_ADDR_EXT_ADDRESS_SHIFT 0
-#define BCHP_NAND_ECC_UNC_EXT_ADDR_EXT_ADDRESS_DEFAULT 0x00000000
-
-/***************************************************************************
- *ECC_UNC_ADDR - ECC Uncorrectable Error Address
- ***************************************************************************/
-/* NAND :: ECC_UNC_ADDR :: ADDRESS [31:00] */
-#define BCHP_NAND_ECC_UNC_ADDR_ADDRESS_MASK 0xffffffff
-#define BCHP_NAND_ECC_UNC_ADDR_ADDRESS_SHIFT 0
-#define BCHP_NAND_ECC_UNC_ADDR_ADDRESS_DEFAULT 0x00000000
-
-/***************************************************************************
- *FLASH_READ_EXT_ADDR - Flash Read Data Extended Address
- ***************************************************************************/
-/* NAND :: FLASH_READ_EXT_ADDR :: reserved0 [31:19] */
-#define BCHP_NAND_FLASH_READ_EXT_ADDR_reserved0_MASK 0xfff80000
-#define BCHP_NAND_FLASH_READ_EXT_ADDR_reserved0_SHIFT 19
-
-/* NAND :: FLASH_READ_EXT_ADDR :: CS_SEL [18:16] */
-#define BCHP_NAND_FLASH_READ_EXT_ADDR_CS_SEL_MASK 0x00070000
-#define BCHP_NAND_FLASH_READ_EXT_ADDR_CS_SEL_SHIFT 16
-#define BCHP_NAND_FLASH_READ_EXT_ADDR_CS_SEL_DEFAULT 0x00000000
-
-/* NAND :: FLASH_READ_EXT_ADDR :: EXT_ADDRESS [15:00] */
-#define BCHP_NAND_FLASH_READ_EXT_ADDR_EXT_ADDRESS_MASK 0x0000ffff
-#define BCHP_NAND_FLASH_READ_EXT_ADDR_EXT_ADDRESS_SHIFT 0
-#define BCHP_NAND_FLASH_READ_EXT_ADDR_EXT_ADDRESS_DEFAULT 0x00000000
-
-/***************************************************************************
- *FLASH_READ_ADDR - Flash Read Data Address
- ***************************************************************************/
-/* NAND :: FLASH_READ_ADDR :: ADDRESS [31:00] */
-#define BCHP_NAND_FLASH_READ_ADDR_ADDRESS_MASK 0xffffffff
-#define BCHP_NAND_FLASH_READ_ADDR_ADDRESS_SHIFT 0
-#define BCHP_NAND_FLASH_READ_ADDR_ADDRESS_DEFAULT 0x00000000
-
-/***************************************************************************
- *PROGRAM_PAGE_EXT_ADDR - Page Program Extended Address
- ***************************************************************************/
-/* NAND :: PROGRAM_PAGE_EXT_ADDR :: reserved0 [31:19] */
-#define BCHP_NAND_PROGRAM_PAGE_EXT_ADDR_reserved0_MASK 0xfff80000
-#define BCHP_NAND_PROGRAM_PAGE_EXT_ADDR_reserved0_SHIFT 19
-
-/* NAND :: PROGRAM_PAGE_EXT_ADDR :: CS_SEL [18:16] */
-#define BCHP_NAND_PROGRAM_PAGE_EXT_ADDR_CS_SEL_MASK 0x00070000
-#define BCHP_NAND_PROGRAM_PAGE_EXT_ADDR_CS_SEL_SHIFT 16
-#define BCHP_NAND_PROGRAM_PAGE_EXT_ADDR_CS_SEL_DEFAULT 0x00000000
-
-/* NAND :: PROGRAM_PAGE_EXT_ADDR :: EXT_ADDRESS [15:00] */
-#define BCHP_NAND_PROGRAM_PAGE_EXT_ADDR_EXT_ADDRESS_MASK 0x0000ffff
-#define BCHP_NAND_PROGRAM_PAGE_EXT_ADDR_EXT_ADDRESS_SHIFT 0
-#define BCHP_NAND_PROGRAM_PAGE_EXT_ADDR_EXT_ADDRESS_DEFAULT 0x00000000
-
-/***************************************************************************
- *PROGRAM_PAGE_ADDR - Page Program Address
- ***************************************************************************/
-/* NAND :: PROGRAM_PAGE_ADDR :: ADDRESS [31:00] */
-#define BCHP_NAND_PROGRAM_PAGE_ADDR_ADDRESS_MASK 0xffffffff
-#define BCHP_NAND_PROGRAM_PAGE_ADDR_ADDRESS_SHIFT 0
-#define BCHP_NAND_PROGRAM_PAGE_ADDR_ADDRESS_DEFAULT 0x00000000
-
-/***************************************************************************
- *COPY_BACK_EXT_ADDR - Copy Back Extended Address
- ***************************************************************************/
-/* NAND :: COPY_BACK_EXT_ADDR :: reserved0 [31:19] */
-#define BCHP_NAND_COPY_BACK_EXT_ADDR_reserved0_MASK 0xfff80000
-#define BCHP_NAND_COPY_BACK_EXT_ADDR_reserved0_SHIFT 19
-
-/* NAND :: COPY_BACK_EXT_ADDR :: CS_SEL [18:16] */
-#define BCHP_NAND_COPY_BACK_EXT_ADDR_CS_SEL_MASK 0x00070000
-#define BCHP_NAND_COPY_BACK_EXT_ADDR_CS_SEL_SHIFT 16
-#define BCHP_NAND_COPY_BACK_EXT_ADDR_CS_SEL_DEFAULT 0x00000000
-
-/* NAND :: COPY_BACK_EXT_ADDR :: EXT_ADDRESS [15:00] */
-#define BCHP_NAND_COPY_BACK_EXT_ADDR_EXT_ADDRESS_MASK 0x0000ffff
-#define BCHP_NAND_COPY_BACK_EXT_ADDR_EXT_ADDRESS_SHIFT 0
-#define BCHP_NAND_COPY_BACK_EXT_ADDR_EXT_ADDRESS_DEFAULT 0x00000000
-
-/***************************************************************************
- *COPY_BACK_ADDR - Copy Back Address
- ***************************************************************************/
-/* NAND :: COPY_BACK_ADDR :: ADDRESS [31:00] */
-#define BCHP_NAND_COPY_BACK_ADDR_ADDRESS_MASK 0xffffffff
-#define BCHP_NAND_COPY_BACK_ADDR_ADDRESS_SHIFT 0
-#define BCHP_NAND_COPY_BACK_ADDR_ADDRESS_DEFAULT 0x00000000
-
-/***************************************************************************
- *BLOCK_ERASE_EXT_ADDR - Block Erase Extended Address
- ***************************************************************************/
-/* NAND :: BLOCK_ERASE_EXT_ADDR :: reserved0 [31:19] */
-#define BCHP_NAND_BLOCK_ERASE_EXT_ADDR_reserved0_MASK 0xfff80000
-#define BCHP_NAND_BLOCK_ERASE_EXT_ADDR_reserved0_SHIFT 19
-
-/* NAND :: BLOCK_ERASE_EXT_ADDR :: CS_SEL [18:16] */
-#define BCHP_NAND_BLOCK_ERASE_EXT_ADDR_CS_SEL_MASK 0x00070000
-#define BCHP_NAND_BLOCK_ERASE_EXT_ADDR_CS_SEL_SHIFT 16
-#define BCHP_NAND_BLOCK_ERASE_EXT_ADDR_CS_SEL_DEFAULT 0x00000000
-
-/* NAND :: BLOCK_ERASE_EXT_ADDR :: EXT_ADDRESS [15:00] */
-#define BCHP_NAND_BLOCK_ERASE_EXT_ADDR_EXT_ADDRESS_MASK 0x0000ffff
-#define BCHP_NAND_BLOCK_ERASE_EXT_ADDR_EXT_ADDRESS_SHIFT 0
-#define BCHP_NAND_BLOCK_ERASE_EXT_ADDR_EXT_ADDRESS_DEFAULT 0x00000000
-
-/***************************************************************************
- *BLOCK_ERASE_ADDR - Block Erase Address
- ***************************************************************************/
-/* NAND :: BLOCK_ERASE_ADDR :: ADDRESS [31:00] */
-#define BCHP_NAND_BLOCK_ERASE_ADDR_ADDRESS_MASK 0xffffffff
-#define BCHP_NAND_BLOCK_ERASE_ADDR_ADDRESS_SHIFT 0
-#define BCHP_NAND_BLOCK_ERASE_ADDR_ADDRESS_DEFAULT 0x00000000
-
-/***************************************************************************
- *INV_READ_EXT_ADDR - Flash Invalid Data Extended Address
- ***************************************************************************/
-/* NAND :: INV_READ_EXT_ADDR :: reserved0 [31:19] */
-#define BCHP_NAND_INV_READ_EXT_ADDR_reserved0_MASK 0xfff80000
-#define BCHP_NAND_INV_READ_EXT_ADDR_reserved0_SHIFT 19
-
-/* NAND :: INV_READ_EXT_ADDR :: CS_SEL [18:16] */
-#define BCHP_NAND_INV_READ_EXT_ADDR_CS_SEL_MASK 0x00070000
-#define BCHP_NAND_INV_READ_EXT_ADDR_CS_SEL_SHIFT 16
-#define BCHP_NAND_INV_READ_EXT_ADDR_CS_SEL_DEFAULT 0x00000000
-
-/* NAND :: INV_READ_EXT_ADDR :: EXT_ADDRESS [15:00] */
-#define BCHP_NAND_INV_READ_EXT_ADDR_EXT_ADDRESS_MASK 0x0000ffff
-#define BCHP_NAND_INV_READ_EXT_ADDR_EXT_ADDRESS_SHIFT 0
-#define BCHP_NAND_INV_READ_EXT_ADDR_EXT_ADDRESS_DEFAULT 0x00000000
-
-/***************************************************************************
- *INV_READ_ADDR - Flash Invalid Data Address
- ***************************************************************************/
-/* NAND :: INV_READ_ADDR :: ADDRESS [31:00] */
-#define BCHP_NAND_INV_READ_ADDR_ADDRESS_MASK 0xffffffff
-#define BCHP_NAND_INV_READ_ADDR_ADDRESS_SHIFT 0
-#define BCHP_NAND_INV_READ_ADDR_ADDRESS_DEFAULT 0x00000000
-
-/***************************************************************************
- *INIT_STATUS - Initialization status
- ***************************************************************************/
-/* NAND :: INIT_STATUS :: ONFI_INIT_DONE [31:31] */
-#define BCHP_NAND_INIT_STATUS_ONFI_INIT_DONE_MASK 0x80000000
-#define BCHP_NAND_INIT_STATUS_ONFI_INIT_DONE_SHIFT 31
-
-/* NAND :: INIT_STATUS :: DEVICE_ID_INIT_DONE [30:30] */
-#define BCHP_NAND_INIT_STATUS_DEVICE_ID_INIT_DONE_MASK 0x40000000
-#define BCHP_NAND_INIT_STATUS_DEVICE_ID_INIT_DONE_SHIFT 30
-
-/* NAND :: INIT_STATUS :: INIT_SUCCESS [29:29] */
-#define BCHP_NAND_INIT_STATUS_INIT_SUCCESS_MASK 0x20000000
-#define BCHP_NAND_INIT_STATUS_INIT_SUCCESS_SHIFT 29
-
-/* NAND :: INIT_STATUS :: INIT_FAIL [28:28] */
-#define BCHP_NAND_INIT_STATUS_INIT_FAIL_MASK 0x10000000
-#define BCHP_NAND_INIT_STATUS_INIT_FAIL_SHIFT 28
-
-/* NAND :: INIT_STATUS :: INIT_BLANK [27:27] */
-#define BCHP_NAND_INIT_STATUS_INIT_BLANK_MASK 0x08000000
-#define BCHP_NAND_INIT_STATUS_INIT_BLANK_SHIFT 27
-
-/* NAND :: INIT_STATUS :: INIT_TIMEOUT [26:26] */
-#define BCHP_NAND_INIT_STATUS_INIT_TIMEOUT_MASK 0x04000000
-#define BCHP_NAND_INIT_STATUS_INIT_TIMEOUT_SHIFT 26
-
-/* NAND :: INIT_STATUS :: INIT_UNC_ERROR [25:25] */
-#define BCHP_NAND_INIT_STATUS_INIT_UNC_ERROR_MASK 0x02000000
-#define BCHP_NAND_INIT_STATUS_INIT_UNC_ERROR_SHIFT 25
-
-/* NAND :: INIT_STATUS :: INIT_CORR_ERROR [24:24] */
-#define BCHP_NAND_INIT_STATUS_INIT_CORR_ERROR_MASK 0x01000000
-#define BCHP_NAND_INIT_STATUS_INIT_CORR_ERROR_SHIFT 24
-
-/* NAND :: INIT_STATUS :: PARAMETER_READY [23:23] */
-#define BCHP_NAND_INIT_STATUS_PARAMETER_READY_MASK 0x00800000
-#define BCHP_NAND_INIT_STATUS_PARAMETER_READY_SHIFT 23
-
-/* NAND :: INIT_STATUS :: AUTHENTICATION_FAIL [22:22] */
-#define BCHP_NAND_INIT_STATUS_AUTHENTICATION_FAIL_MASK 0x00400000
-#define BCHP_NAND_INIT_STATUS_AUTHENTICATION_FAIL_SHIFT 22
-
-/* NAND :: INIT_STATUS :: reserved0 [21:00] */
-#define BCHP_NAND_INIT_STATUS_reserved0_MASK 0x003fffff
-#define BCHP_NAND_INIT_STATUS_reserved0_SHIFT 0
-
-/***************************************************************************
- *ONFI_STATUS - ONFI Status
- ***************************************************************************/
-/* NAND :: ONFI_STATUS :: ONFI_DEBUG_SEL [31:28] */
-#define BCHP_NAND_ONFI_STATUS_ONFI_DEBUG_SEL_MASK 0xf0000000
-#define BCHP_NAND_ONFI_STATUS_ONFI_DEBUG_SEL_SHIFT 28
-#define BCHP_NAND_ONFI_STATUS_ONFI_DEBUG_SEL_DEFAULT 0x00000000
-
-/* NAND :: ONFI_STATUS :: ONFI_detected [27:27] */
-#define BCHP_NAND_ONFI_STATUS_ONFI_detected_MASK 0x08000000
-#define BCHP_NAND_ONFI_STATUS_ONFI_detected_SHIFT 27
-
-/* NAND :: ONFI_STATUS :: reserved0 [26:06] */
-#define BCHP_NAND_ONFI_STATUS_reserved0_MASK 0x07ffffc0
-#define BCHP_NAND_ONFI_STATUS_reserved0_SHIFT 6
-
-/* NAND :: ONFI_STATUS :: ONFI_BAD_IDENT_PG2 [05:05] */
-#define BCHP_NAND_ONFI_STATUS_ONFI_BAD_IDENT_PG2_MASK 0x00000020
-#define BCHP_NAND_ONFI_STATUS_ONFI_BAD_IDENT_PG2_SHIFT 5
-
-/* NAND :: ONFI_STATUS :: ONFI_BAD_IDENT_PG1 [04:04] */
-#define BCHP_NAND_ONFI_STATUS_ONFI_BAD_IDENT_PG1_MASK 0x00000010
-#define BCHP_NAND_ONFI_STATUS_ONFI_BAD_IDENT_PG1_SHIFT 4
-
-/* NAND :: ONFI_STATUS :: ONFI_BAD_IDENT_PG0 [03:03] */
-#define BCHP_NAND_ONFI_STATUS_ONFI_BAD_IDENT_PG0_MASK 0x00000008
-#define BCHP_NAND_ONFI_STATUS_ONFI_BAD_IDENT_PG0_SHIFT 3
-
-/* NAND :: ONFI_STATUS :: ONFI_CRC_ERROR_PG2 [02:02] */
-#define BCHP_NAND_ONFI_STATUS_ONFI_CRC_ERROR_PG2_MASK 0x00000004
-#define BCHP_NAND_ONFI_STATUS_ONFI_CRC_ERROR_PG2_SHIFT 2
-
-/* NAND :: ONFI_STATUS :: ONFI_CRC_ERROR_PG1 [01:01] */
-#define BCHP_NAND_ONFI_STATUS_ONFI_CRC_ERROR_PG1_MASK 0x00000002
-#define BCHP_NAND_ONFI_STATUS_ONFI_CRC_ERROR_PG1_SHIFT 1
-
-/* NAND :: ONFI_STATUS :: ONFI_CRC_ERROR_PG0 [00:00] */
-#define BCHP_NAND_ONFI_STATUS_ONFI_CRC_ERROR_PG0_MASK 0x00000001
-#define BCHP_NAND_ONFI_STATUS_ONFI_CRC_ERROR_PG0_SHIFT 0
-
-/***************************************************************************
- *ONFI_DEBUG_DATA - ONFI Debug Data
- ***************************************************************************/
-/* NAND :: ONFI_DEBUG_DATA :: ONFI_DEBUG_DATA [31:00] */
-#define BCHP_NAND_ONFI_DEBUG_DATA_ONFI_DEBUG_DATA_MASK 0xffffffff
-#define BCHP_NAND_ONFI_DEBUG_DATA_ONFI_DEBUG_DATA_SHIFT 0
-
-/***************************************************************************
- *SEMAPHORE - Semaphore
- ***************************************************************************/
-/* NAND :: SEMAPHORE :: reserved0 [31:08] */
-#define BCHP_NAND_SEMAPHORE_reserved0_MASK 0xffffff00
-#define BCHP_NAND_SEMAPHORE_reserved0_SHIFT 8
-
-/* NAND :: SEMAPHORE :: semaphore_ctrl [07:00] */
-#define BCHP_NAND_SEMAPHORE_semaphore_ctrl_MASK 0x000000ff
-#define BCHP_NAND_SEMAPHORE_semaphore_ctrl_SHIFT 0
-#define BCHP_NAND_SEMAPHORE_semaphore_ctrl_DEFAULT 0x00000000
-
-/***************************************************************************
- *FLASH_DEVICE_ID - Nand Flash Device ID
- ***************************************************************************/
-/* NAND :: FLASH_DEVICE_ID :: BYTE_0 [31:24] */
-#define BCHP_NAND_FLASH_DEVICE_ID_BYTE_0_MASK 0xff000000
-#define BCHP_NAND_FLASH_DEVICE_ID_BYTE_0_SHIFT 24
-
-/* NAND :: FLASH_DEVICE_ID :: BYTE_1 [23:16] */
-#define BCHP_NAND_FLASH_DEVICE_ID_BYTE_1_MASK 0x00ff0000
-#define BCHP_NAND_FLASH_DEVICE_ID_BYTE_1_SHIFT 16
-
-/* NAND :: FLASH_DEVICE_ID :: BYTE_2 [15:08] */
-#define BCHP_NAND_FLASH_DEVICE_ID_BYTE_2_MASK 0x0000ff00
-#define BCHP_NAND_FLASH_DEVICE_ID_BYTE_2_SHIFT 8
-
-/* NAND :: FLASH_DEVICE_ID :: BYTE_3 [07:00] */
-#define BCHP_NAND_FLASH_DEVICE_ID_BYTE_3_MASK 0x000000ff
-#define BCHP_NAND_FLASH_DEVICE_ID_BYTE_3_SHIFT 0
-
-/***************************************************************************
- *FLASH_DEVICE_ID_EXT - Nand Flash Extended Device ID
- ***************************************************************************/
-/* NAND :: FLASH_DEVICE_ID_EXT :: BYTE_4 [31:24] */
-#define BCHP_NAND_FLASH_DEVICE_ID_EXT_BYTE_4_MASK 0xff000000
-#define BCHP_NAND_FLASH_DEVICE_ID_EXT_BYTE_4_SHIFT 24
-
-/* NAND :: FLASH_DEVICE_ID_EXT :: BYTE_5 [23:16] */
-#define BCHP_NAND_FLASH_DEVICE_ID_EXT_BYTE_5_MASK 0x00ff0000
-#define BCHP_NAND_FLASH_DEVICE_ID_EXT_BYTE_5_SHIFT 16
-
-/* NAND :: FLASH_DEVICE_ID_EXT :: BYTE_6 [15:08] */
-#define BCHP_NAND_FLASH_DEVICE_ID_EXT_BYTE_6_MASK 0x0000ff00
-#define BCHP_NAND_FLASH_DEVICE_ID_EXT_BYTE_6_SHIFT 8
-
-/* NAND :: FLASH_DEVICE_ID_EXT :: BYTE_7 [07:00] */
-#define BCHP_NAND_FLASH_DEVICE_ID_EXT_BYTE_7_MASK 0x000000ff
-#define BCHP_NAND_FLASH_DEVICE_ID_EXT_BYTE_7_SHIFT 0
-
-/***************************************************************************
- *LL_RDDATA - Nand Flash Low Level Read Data
- ***************************************************************************/
-/* NAND :: LL_RDDATA :: reserved0 [31:16] */
-#define BCHP_NAND_LL_RDDATA_reserved0_MASK 0xffff0000
-#define BCHP_NAND_LL_RDDATA_reserved0_SHIFT 16
-
-/* NAND :: LL_RDDATA :: DATA [15:00] */
-#define BCHP_NAND_LL_RDDATA_DATA_MASK 0x0000ffff
-#define BCHP_NAND_LL_RDDATA_DATA_SHIFT 0
-#define BCHP_NAND_LL_RDDATA_DATA_DEFAULT 0x00000000
-
-/***************************************************************************
- *SPARE_AREA_READ_OFS_0 - Nand Flash Spare Area Read Bytes 0-3
- ***************************************************************************/
-/* NAND :: SPARE_AREA_READ_OFS_0 :: BYTE_OFS_0 [31:24] */
-#define BCHP_NAND_SPARE_AREA_READ_OFS_0_BYTE_OFS_0_MASK 0xff000000
-#define BCHP_NAND_SPARE_AREA_READ_OFS_0_BYTE_OFS_0_SHIFT 24
-#define BCHP_NAND_SPARE_AREA_READ_OFS_0_BYTE_OFS_0_DEFAULT 0x000000ff
-
-/* NAND :: SPARE_AREA_READ_OFS_0 :: BYTE_OFS_1 [23:16] */
-#define BCHP_NAND_SPARE_AREA_READ_OFS_0_BYTE_OFS_1_MASK 0x00ff0000
-#define BCHP_NAND_SPARE_AREA_READ_OFS_0_BYTE_OFS_1_SHIFT 16
-#define BCHP_NAND_SPARE_AREA_READ_OFS_0_BYTE_OFS_1_DEFAULT 0x000000ff
-
-/* NAND :: SPARE_AREA_READ_OFS_0 :: BYTE_OFS_2 [15:08] */
-#define BCHP_NAND_SPARE_AREA_READ_OFS_0_BYTE_OFS_2_MASK 0x0000ff00
-#define BCHP_NAND_SPARE_AREA_READ_OFS_0_BYTE_OFS_2_SHIFT 8
-#define BCHP_NAND_SPARE_AREA_READ_OFS_0_BYTE_OFS_2_DEFAULT 0x000000ff
-
-/* NAND :: SPARE_AREA_READ_OFS_0 :: BYTE_OFS_3 [07:00] */
-#define BCHP_NAND_SPARE_AREA_READ_OFS_0_BYTE_OFS_3_MASK 0x000000ff
-#define BCHP_NAND_SPARE_AREA_READ_OFS_0_BYTE_OFS_3_SHIFT 0
-#define BCHP_NAND_SPARE_AREA_READ_OFS_0_BYTE_OFS_3_DEFAULT 0x000000ff
-
-/***************************************************************************
- *SPARE_AREA_READ_OFS_4 - Nand Flash Spare Area Read Bytes 4-7
- ***************************************************************************/
-/* NAND :: SPARE_AREA_READ_OFS_4 :: BYTE_OFS_4 [31:24] */
-#define BCHP_NAND_SPARE_AREA_READ_OFS_4_BYTE_OFS_4_MASK 0xff000000
-#define BCHP_NAND_SPARE_AREA_READ_OFS_4_BYTE_OFS_4_SHIFT 24
-#define BCHP_NAND_SPARE_AREA_READ_OFS_4_BYTE_OFS_4_DEFAULT 0x000000ff
-
-/* NAND :: SPARE_AREA_READ_OFS_4 :: BYTE_OFS_5 [23:16] */
-#define BCHP_NAND_SPARE_AREA_READ_OFS_4_BYTE_OFS_5_MASK 0x00ff0000
-#define BCHP_NAND_SPARE_AREA_READ_OFS_4_BYTE_OFS_5_SHIFT 16
-#define BCHP_NAND_SPARE_AREA_READ_OFS_4_BYTE_OFS_5_DEFAULT 0x000000ff
-
-/* NAND :: SPARE_AREA_READ_OFS_4 :: BYTE_OFS_6 [15:08] */
-#define BCHP_NAND_SPARE_AREA_READ_OFS_4_BYTE_OFS_6_MASK 0x0000ff00
-#define BCHP_NAND_SPARE_AREA_READ_OFS_4_BYTE_OFS_6_SHIFT 8
-#define BCHP_NAND_SPARE_AREA_READ_OFS_4_BYTE_OFS_6_DEFAULT 0x000000ff
-
-/* NAND :: SPARE_AREA_READ_OFS_4 :: BYTE_OFS_7 [07:00] */
-#define BCHP_NAND_SPARE_AREA_READ_OFS_4_BYTE_OFS_7_MASK 0x000000ff
-#define BCHP_NAND_SPARE_AREA_READ_OFS_4_BYTE_OFS_7_SHIFT 0
-#define BCHP_NAND_SPARE_AREA_READ_OFS_4_BYTE_OFS_7_DEFAULT 0x000000ff
-
-/***************************************************************************
- *SPARE_AREA_READ_OFS_8 - Nand Flash Spare Area Read Bytes 8-11
- ***************************************************************************/
-/* NAND :: SPARE_AREA_READ_OFS_8 :: BYTE_OFS_8 [31:24] */
-#define BCHP_NAND_SPARE_AREA_READ_OFS_8_BYTE_OFS_8_MASK 0xff000000
-#define BCHP_NAND_SPARE_AREA_READ_OFS_8_BYTE_OFS_8_SHIFT 24
-#define BCHP_NAND_SPARE_AREA_READ_OFS_8_BYTE_OFS_8_DEFAULT 0x000000ff
-
-/* NAND :: SPARE_AREA_READ_OFS_8 :: BYTE_OFS_9 [23:16] */
-#define BCHP_NAND_SPARE_AREA_READ_OFS_8_BYTE_OFS_9_MASK 0x00ff0000
-#define BCHP_NAND_SPARE_AREA_READ_OFS_8_BYTE_OFS_9_SHIFT 16
-#define BCHP_NAND_SPARE_AREA_READ_OFS_8_BYTE_OFS_9_DEFAULT 0x000000ff
-
-/* NAND :: SPARE_AREA_READ_OFS_8 :: BYTE_OFS_10 [15:08] */
-#define BCHP_NAND_SPARE_AREA_READ_OFS_8_BYTE_OFS_10_MASK 0x0000ff00
-#define BCHP_NAND_SPARE_AREA_READ_OFS_8_BYTE_OFS_10_SHIFT 8
-#define BCHP_NAND_SPARE_AREA_READ_OFS_8_BYTE_OFS_10_DEFAULT 0x000000ff
-
-/* NAND :: SPARE_AREA_READ_OFS_8 :: BYTE_OFS_11 [07:00] */
-#define BCHP_NAND_SPARE_AREA_READ_OFS_8_BYTE_OFS_11_MASK 0x000000ff
-#define BCHP_NAND_SPARE_AREA_READ_OFS_8_BYTE_OFS_11_SHIFT 0
-#define BCHP_NAND_SPARE_AREA_READ_OFS_8_BYTE_OFS_11_DEFAULT 0x000000ff
-
-/***************************************************************************
- *SPARE_AREA_READ_OFS_C - Nand Flash Spare Area Read Bytes 12-15
- ***************************************************************************/
-/* NAND :: SPARE_AREA_READ_OFS_C :: BYTE_OFS_12 [31:24] */
-#define BCHP_NAND_SPARE_AREA_READ_OFS_C_BYTE_OFS_12_MASK 0xff000000
-#define BCHP_NAND_SPARE_AREA_READ_OFS_C_BYTE_OFS_12_SHIFT 24
-#define BCHP_NAND_SPARE_AREA_READ_OFS_C_BYTE_OFS_12_DEFAULT 0x000000ff
-
-/* NAND :: SPARE_AREA_READ_OFS_C :: BYTE_OFS_13 [23:16] */
-#define BCHP_NAND_SPARE_AREA_READ_OFS_C_BYTE_OFS_13_MASK 0x00ff0000
-#define BCHP_NAND_SPARE_AREA_READ_OFS_C_BYTE_OFS_13_SHIFT 16
-#define BCHP_NAND_SPARE_AREA_READ_OFS_C_BYTE_OFS_13_DEFAULT 0x000000ff
-
-/* NAND :: SPARE_AREA_READ_OFS_C :: BYTE_OFS_14 [15:08] */
-#define BCHP_NAND_SPARE_AREA_READ_OFS_C_BYTE_OFS_14_MASK 0x0000ff00
-#define BCHP_NAND_SPARE_AREA_READ_OFS_C_BYTE_OFS_14_SHIFT 8
-#define BCHP_NAND_SPARE_AREA_READ_OFS_C_BYTE_OFS_14_DEFAULT 0x000000ff
-
-/* NAND :: SPARE_AREA_READ_OFS_C :: BYTE_OFS_15 [07:00] */
-#define BCHP_NAND_SPARE_AREA_READ_OFS_C_BYTE_OFS_15_MASK 0x000000ff
-#define BCHP_NAND_SPARE_AREA_READ_OFS_C_BYTE_OFS_15_SHIFT 0
-#define BCHP_NAND_SPARE_AREA_READ_OFS_C_BYTE_OFS_15_DEFAULT 0x000000ff
-
-/***************************************************************************
- *SPARE_AREA_READ_OFS_10 - Nand Flash Spare Area Read Bytes 16-19
- ***************************************************************************/
-/* NAND :: SPARE_AREA_READ_OFS_10 :: BYTE_OFS_16 [31:24] */
-#define BCHP_NAND_SPARE_AREA_READ_OFS_10_BYTE_OFS_16_MASK 0xff000000
-#define BCHP_NAND_SPARE_AREA_READ_OFS_10_BYTE_OFS_16_SHIFT 24
-#define BCHP_NAND_SPARE_AREA_READ_OFS_10_BYTE_OFS_16_DEFAULT 0x000000ff
-
-/* NAND :: SPARE_AREA_READ_OFS_10 :: BYTE_OFS_17 [23:16] */
-#define BCHP_NAND_SPARE_AREA_READ_OFS_10_BYTE_OFS_17_MASK 0x00ff0000
-#define BCHP_NAND_SPARE_AREA_READ_OFS_10_BYTE_OFS_17_SHIFT 16
-#define BCHP_NAND_SPARE_AREA_READ_OFS_10_BYTE_OFS_17_DEFAULT 0x000000ff
-
-/* NAND :: SPARE_AREA_READ_OFS_10 :: BYTE_OFS_18 [15:08] */
-#define BCHP_NAND_SPARE_AREA_READ_OFS_10_BYTE_OFS_18_MASK 0x0000ff00
-#define BCHP_NAND_SPARE_AREA_READ_OFS_10_BYTE_OFS_18_SHIFT 8
-#define BCHP_NAND_SPARE_AREA_READ_OFS_10_BYTE_OFS_18_DEFAULT 0x000000ff
-
-/* NAND :: SPARE_AREA_READ_OFS_10 :: BYTE_OFS_19 [07:00] */
-#define BCHP_NAND_SPARE_AREA_READ_OFS_10_BYTE_OFS_19_MASK 0x000000ff
-#define BCHP_NAND_SPARE_AREA_READ_OFS_10_BYTE_OFS_19_SHIFT 0
-#define BCHP_NAND_SPARE_AREA_READ_OFS_10_BYTE_OFS_19_DEFAULT 0x000000ff
-
-/***************************************************************************
- *SPARE_AREA_READ_OFS_14 - Nand Flash Spare Area Read Bytes 20-23
- ***************************************************************************/
-/* NAND :: SPARE_AREA_READ_OFS_14 :: BYTE_OFS_20 [31:24] */
-#define BCHP_NAND_SPARE_AREA_READ_OFS_14_BYTE_OFS_20_MASK 0xff000000
-#define BCHP_NAND_SPARE_AREA_READ_OFS_14_BYTE_OFS_20_SHIFT 24
-#define BCHP_NAND_SPARE_AREA_READ_OFS_14_BYTE_OFS_20_DEFAULT 0x000000ff
-
-/* NAND :: SPARE_AREA_READ_OFS_14 :: BYTE_OFS_21 [23:16] */
-#define BCHP_NAND_SPARE_AREA_READ_OFS_14_BYTE_OFS_21_MASK 0x00ff0000
-#define BCHP_NAND_SPARE_AREA_READ_OFS_14_BYTE_OFS_21_SHIFT 16
-#define BCHP_NAND_SPARE_AREA_READ_OFS_14_BYTE_OFS_21_DEFAULT 0x000000ff
-
-/* NAND :: SPARE_AREA_READ_OFS_14 :: BYTE_OFS_22 [15:08] */
-#define BCHP_NAND_SPARE_AREA_READ_OFS_14_BYTE_OFS_22_MASK 0x0000ff00
-#define BCHP_NAND_SPARE_AREA_READ_OFS_14_BYTE_OFS_22_SHIFT 8
-#define BCHP_NAND_SPARE_AREA_READ_OFS_14_BYTE_OFS_22_DEFAULT 0x000000ff
-
-/* NAND :: SPARE_AREA_READ_OFS_14 :: BYTE_OFS_23 [07:00] */
-#define BCHP_NAND_SPARE_AREA_READ_OFS_14_BYTE_OFS_23_MASK 0x000000ff
-#define BCHP_NAND_SPARE_AREA_READ_OFS_14_BYTE_OFS_23_SHIFT 0
-#define BCHP_NAND_SPARE_AREA_READ_OFS_14_BYTE_OFS_23_DEFAULT 0x000000ff
-
-/***************************************************************************
- *SPARE_AREA_READ_OFS_18 - Nand Flash Spare Area Read Bytes 24-27
- ***************************************************************************/
-/* NAND :: SPARE_AREA_READ_OFS_18 :: BYTE_OFS_24 [31:24] */
-#define BCHP_NAND_SPARE_AREA_READ_OFS_18_BYTE_OFS_24_MASK 0xff000000
-#define BCHP_NAND_SPARE_AREA_READ_OFS_18_BYTE_OFS_24_SHIFT 24
-#define BCHP_NAND_SPARE_AREA_READ_OFS_18_BYTE_OFS_24_DEFAULT 0x000000ff
-
-/* NAND :: SPARE_AREA_READ_OFS_18 :: BYTE_OFS_25 [23:16] */
-#define BCHP_NAND_SPARE_AREA_READ_OFS_18_BYTE_OFS_25_MASK 0x00ff0000
-#define BCHP_NAND_SPARE_AREA_READ_OFS_18_BYTE_OFS_25_SHIFT 16
-#define BCHP_NAND_SPARE_AREA_READ_OFS_18_BYTE_OFS_25_DEFAULT 0x000000ff
-
-/* NAND :: SPARE_AREA_READ_OFS_18 :: BYTE_OFS_26 [15:08] */
-#define BCHP_NAND_SPARE_AREA_READ_OFS_18_BYTE_OFS_26_MASK 0x0000ff00
-#define BCHP_NAND_SPARE_AREA_READ_OFS_18_BYTE_OFS_26_SHIFT 8
-#define BCHP_NAND_SPARE_AREA_READ_OFS_18_BYTE_OFS_26_DEFAULT 0x000000ff
-
-/* NAND :: SPARE_AREA_READ_OFS_18 :: BYTE_OFS_27 [07:00] */
-#define BCHP_NAND_SPARE_AREA_READ_OFS_18_BYTE_OFS_27_MASK 0x000000ff
-#define BCHP_NAND_SPARE_AREA_READ_OFS_18_BYTE_OFS_27_SHIFT 0
-#define BCHP_NAND_SPARE_AREA_READ_OFS_18_BYTE_OFS_27_DEFAULT 0x000000ff
-
-/***************************************************************************
- *SPARE_AREA_READ_OFS_1C - Nand Flash Spare Area Read Bytes 28-31
- ***************************************************************************/
-/* NAND :: SPARE_AREA_READ_OFS_1C :: BYTE_OFS_28 [31:24] */
-#define BCHP_NAND_SPARE_AREA_READ_OFS_1C_BYTE_OFS_28_MASK 0xff000000
-#define BCHP_NAND_SPARE_AREA_READ_OFS_1C_BYTE_OFS_28_SHIFT 24
-#define BCHP_NAND_SPARE_AREA_READ_OFS_1C_BYTE_OFS_28_DEFAULT 0x000000ff
-
-/* NAND :: SPARE_AREA_READ_OFS_1C :: BYTE_OFS_29 [23:16] */
-#define BCHP_NAND_SPARE_AREA_READ_OFS_1C_BYTE_OFS_29_MASK 0x00ff0000
-#define BCHP_NAND_SPARE_AREA_READ_OFS_1C_BYTE_OFS_29_SHIFT 16
-#define BCHP_NAND_SPARE_AREA_READ_OFS_1C_BYTE_OFS_29_DEFAULT 0x000000ff
-
-/* NAND :: SPARE_AREA_READ_OFS_1C :: BYTE_OFS_30 [15:08] */
-#define BCHP_NAND_SPARE_AREA_READ_OFS_1C_BYTE_OFS_30_MASK 0x0000ff00
-#define BCHP_NAND_SPARE_AREA_READ_OFS_1C_BYTE_OFS_30_SHIFT 8
-#define BCHP_NAND_SPARE_AREA_READ_OFS_1C_BYTE_OFS_30_DEFAULT 0x000000ff
-
-/* NAND :: SPARE_AREA_READ_OFS_1C :: BYTE_OFS_31 [07:00] */
-#define BCHP_NAND_SPARE_AREA_READ_OFS_1C_BYTE_OFS_31_MASK 0x000000ff
-#define BCHP_NAND_SPARE_AREA_READ_OFS_1C_BYTE_OFS_31_SHIFT 0
-#define BCHP_NAND_SPARE_AREA_READ_OFS_1C_BYTE_OFS_31_DEFAULT 0x000000ff
-
-/***************************************************************************
- *SPARE_AREA_READ_OFS_20 - Nand Flash Spare Area Read Bytes 32-35
- ***************************************************************************/
-/* NAND :: SPARE_AREA_READ_OFS_20 :: BYTE_OFS_32 [31:24] */
-#define BCHP_NAND_SPARE_AREA_READ_OFS_20_BYTE_OFS_32_MASK 0xff000000
-#define BCHP_NAND_SPARE_AREA_READ_OFS_20_BYTE_OFS_32_SHIFT 24
-#define BCHP_NAND_SPARE_AREA_READ_OFS_20_BYTE_OFS_32_DEFAULT 0x000000ff
-
-/* NAND :: SPARE_AREA_READ_OFS_20 :: BYTE_OFS_33 [23:16] */
-#define BCHP_NAND_SPARE_AREA_READ_OFS_20_BYTE_OFS_33_MASK 0x00ff0000
-#define BCHP_NAND_SPARE_AREA_READ_OFS_20_BYTE_OFS_33_SHIFT 16
-#define BCHP_NAND_SPARE_AREA_READ_OFS_20_BYTE_OFS_33_DEFAULT 0x000000ff
-
-/* NAND :: SPARE_AREA_READ_OFS_20 :: BYTE_OFS_34 [15:08] */
-#define BCHP_NAND_SPARE_AREA_READ_OFS_20_BYTE_OFS_34_MASK 0x0000ff00
-#define BCHP_NAND_SPARE_AREA_READ_OFS_20_BYTE_OFS_34_SHIFT 8
-#define BCHP_NAND_SPARE_AREA_READ_OFS_20_BYTE_OFS_34_DEFAULT 0x000000ff
-
-/* NAND :: SPARE_AREA_READ_OFS_20 :: BYTE_OFS_35 [07:00] */
-#define BCHP_NAND_SPARE_AREA_READ_OFS_20_BYTE_OFS_35_MASK 0x000000ff
-#define BCHP_NAND_SPARE_AREA_READ_OFS_20_BYTE_OFS_35_SHIFT 0
-#define BCHP_NAND_SPARE_AREA_READ_OFS_20_BYTE_OFS_35_DEFAULT 0x000000ff
-
-/***************************************************************************
- *SPARE_AREA_READ_OFS_24 - Nand Flash Spare Area Read Bytes 36-39
- ***************************************************************************/
-/* NAND :: SPARE_AREA_READ_OFS_24 :: BYTE_OFS_36 [31:24] */
-#define BCHP_NAND_SPARE_AREA_READ_OFS_24_BYTE_OFS_36_MASK 0xff000000
-#define BCHP_NAND_SPARE_AREA_READ_OFS_24_BYTE_OFS_36_SHIFT 24
-#define BCHP_NAND_SPARE_AREA_READ_OFS_24_BYTE_OFS_36_DEFAULT 0x000000ff
-
-/* NAND :: SPARE_AREA_READ_OFS_24 :: BYTE_OFS_37 [23:16] */
-#define BCHP_NAND_SPARE_AREA_READ_OFS_24_BYTE_OFS_37_MASK 0x00ff0000
-#define BCHP_NAND_SPARE_AREA_READ_OFS_24_BYTE_OFS_37_SHIFT 16
-#define BCHP_NAND_SPARE_AREA_READ_OFS_24_BYTE_OFS_37_DEFAULT 0x000000ff
-
-/* NAND :: SPARE_AREA_READ_OFS_24 :: BYTE_OFS_38 [15:08] */
-#define BCHP_NAND_SPARE_AREA_READ_OFS_24_BYTE_OFS_38_MASK 0x0000ff00
-#define BCHP_NAND_SPARE_AREA_READ_OFS_24_BYTE_OFS_38_SHIFT 8
-#define BCHP_NAND_SPARE_AREA_READ_OFS_24_BYTE_OFS_38_DEFAULT 0x000000ff
-
-/* NAND :: SPARE_AREA_READ_OFS_24 :: BYTE_OFS_39 [07:00] */
-#define BCHP_NAND_SPARE_AREA_READ_OFS_24_BYTE_OFS_39_MASK 0x000000ff
-#define BCHP_NAND_SPARE_AREA_READ_OFS_24_BYTE_OFS_39_SHIFT 0
-#define BCHP_NAND_SPARE_AREA_READ_OFS_24_BYTE_OFS_39_DEFAULT 0x000000ff
-
-/***************************************************************************
- *SPARE_AREA_READ_OFS_28 - Nand Flash Spare Area Read Bytes 40-43
- ***************************************************************************/
-/* NAND :: SPARE_AREA_READ_OFS_28 :: BYTE_OFS_40 [31:24] */
-#define BCHP_NAND_SPARE_AREA_READ_OFS_28_BYTE_OFS_40_MASK 0xff000000
-#define BCHP_NAND_SPARE_AREA_READ_OFS_28_BYTE_OFS_40_SHIFT 24
-#define BCHP_NAND_SPARE_AREA_READ_OFS_28_BYTE_OFS_40_DEFAULT 0x000000ff
-
-/* NAND :: SPARE_AREA_READ_OFS_28 :: BYTE_OFS_41 [23:16] */
-#define BCHP_NAND_SPARE_AREA_READ_OFS_28_BYTE_OFS_41_MASK 0x00ff0000
-#define BCHP_NAND_SPARE_AREA_READ_OFS_28_BYTE_OFS_41_SHIFT 16
-#define BCHP_NAND_SPARE_AREA_READ_OFS_28_BYTE_OFS_41_DEFAULT 0x000000ff
-
-/* NAND :: SPARE_AREA_READ_OFS_28 :: BYTE_OFS_42 [15:08] */
-#define BCHP_NAND_SPARE_AREA_READ_OFS_28_BYTE_OFS_42_MASK 0x0000ff00
-#define BCHP_NAND_SPARE_AREA_READ_OFS_28_BYTE_OFS_42_SHIFT 8
-#define BCHP_NAND_SPARE_AREA_READ_OFS_28_BYTE_OFS_42_DEFAULT 0x000000ff
-
-/* NAND :: SPARE_AREA_READ_OFS_28 :: BYTE_OFS_43 [07:00] */
-#define BCHP_NAND_SPARE_AREA_READ_OFS_28_BYTE_OFS_43_MASK 0x000000ff
-#define BCHP_NAND_SPARE_AREA_READ_OFS_28_BYTE_OFS_43_SHIFT 0
-#define BCHP_NAND_SPARE_AREA_READ_OFS_28_BYTE_OFS_43_DEFAULT 0x000000ff
-
-/***************************************************************************
- *SPARE_AREA_READ_OFS_2C - Nand Flash Spare Area Read Bytes 44-47
- ***************************************************************************/
-/* NAND :: SPARE_AREA_READ_OFS_2C :: BYTE_OFS_44 [31:24] */
-#define BCHP_NAND_SPARE_AREA_READ_OFS_2C_BYTE_OFS_44_MASK 0xff000000
-#define BCHP_NAND_SPARE_AREA_READ_OFS_2C_BYTE_OFS_44_SHIFT 24
-#define BCHP_NAND_SPARE_AREA_READ_OFS_2C_BYTE_OFS_44_DEFAULT 0x000000ff
-
-/* NAND :: SPARE_AREA_READ_OFS_2C :: BYTE_OFS_45 [23:16] */
-#define BCHP_NAND_SPARE_AREA_READ_OFS_2C_BYTE_OFS_45_MASK 0x00ff0000
-#define BCHP_NAND_SPARE_AREA_READ_OFS_2C_BYTE_OFS_45_SHIFT 16
-#define BCHP_NAND_SPARE_AREA_READ_OFS_2C_BYTE_OFS_45_DEFAULT 0x000000ff
-
-/* NAND :: SPARE_AREA_READ_OFS_2C :: BYTE_OFS_46 [15:08] */
-#define BCHP_NAND_SPARE_AREA_READ_OFS_2C_BYTE_OFS_46_MASK 0x0000ff00
-#define BCHP_NAND_SPARE_AREA_READ_OFS_2C_BYTE_OFS_46_SHIFT 8
-#define BCHP_NAND_SPARE_AREA_READ_OFS_2C_BYTE_OFS_46_DEFAULT 0x000000ff
-
-/* NAND :: SPARE_AREA_READ_OFS_2C :: BYTE_OFS_47 [07:00] */
-#define BCHP_NAND_SPARE_AREA_READ_OFS_2C_BYTE_OFS_47_MASK 0x000000ff
-#define BCHP_NAND_SPARE_AREA_READ_OFS_2C_BYTE_OFS_47_SHIFT 0
-#define BCHP_NAND_SPARE_AREA_READ_OFS_2C_BYTE_OFS_47_DEFAULT 0x000000ff
-
-/***************************************************************************
- *SPARE_AREA_READ_OFS_30 - Nand Flash Spare Area Read Bytes 48-51
- ***************************************************************************/
-/* NAND :: SPARE_AREA_READ_OFS_30 :: BYTE_OFS_48 [31:24] */
-#define BCHP_NAND_SPARE_AREA_READ_OFS_30_BYTE_OFS_48_MASK 0xff000000
-#define BCHP_NAND_SPARE_AREA_READ_OFS_30_BYTE_OFS_48_SHIFT 24
-#define BCHP_NAND_SPARE_AREA_READ_OFS_30_BYTE_OFS_48_DEFAULT 0x000000ff
-
-/* NAND :: SPARE_AREA_READ_OFS_30 :: BYTE_OFS_49 [23:16] */
-#define BCHP_NAND_SPARE_AREA_READ_OFS_30_BYTE_OFS_49_MASK 0x00ff0000
-#define BCHP_NAND_SPARE_AREA_READ_OFS_30_BYTE_OFS_49_SHIFT 16
-#define BCHP_NAND_SPARE_AREA_READ_OFS_30_BYTE_OFS_49_DEFAULT 0x000000ff
-
-/* NAND :: SPARE_AREA_READ_OFS_30 :: BYTE_OFS_50 [15:08] */
-#define BCHP_NAND_SPARE_AREA_READ_OFS_30_BYTE_OFS_50_MASK 0x0000ff00
-#define BCHP_NAND_SPARE_AREA_READ_OFS_30_BYTE_OFS_50_SHIFT 8
-#define BCHP_NAND_SPARE_AREA_READ_OFS_30_BYTE_OFS_50_DEFAULT 0x000000ff
-
-/* NAND :: SPARE_AREA_READ_OFS_30 :: BYTE_OFS_51 [07:00] */
-#define BCHP_NAND_SPARE_AREA_READ_OFS_30_BYTE_OFS_51_MASK 0x000000ff
-#define BCHP_NAND_SPARE_AREA_READ_OFS_30_BYTE_OFS_51_SHIFT 0
-#define BCHP_NAND_SPARE_AREA_READ_OFS_30_BYTE_OFS_51_DEFAULT 0x000000ff
-
-/***************************************************************************
- *SPARE_AREA_READ_OFS_34 - Nand Flash Spare Area Read Bytes 52-55
- ***************************************************************************/
-/* NAND :: SPARE_AREA_READ_OFS_34 :: BYTE_OFS_52 [31:24] */
-#define BCHP_NAND_SPARE_AREA_READ_OFS_34_BYTE_OFS_52_MASK 0xff000000
-#define BCHP_NAND_SPARE_AREA_READ_OFS_34_BYTE_OFS_52_SHIFT 24
-#define BCHP_NAND_SPARE_AREA_READ_OFS_34_BYTE_OFS_52_DEFAULT 0x000000ff
-
-/* NAND :: SPARE_AREA_READ_OFS_34 :: BYTE_OFS_53 [23:16] */
-#define BCHP_NAND_SPARE_AREA_READ_OFS_34_BYTE_OFS_53_MASK 0x00ff0000
-#define BCHP_NAND_SPARE_AREA_READ_OFS_34_BYTE_OFS_53_SHIFT 16
-#define BCHP_NAND_SPARE_AREA_READ_OFS_34_BYTE_OFS_53_DEFAULT 0x000000ff
-
-/* NAND :: SPARE_AREA_READ_OFS_34 :: BYTE_OFS_54 [15:08] */
-#define BCHP_NAND_SPARE_AREA_READ_OFS_34_BYTE_OFS_54_MASK 0x0000ff00
-#define BCHP_NAND_SPARE_AREA_READ_OFS_34_BYTE_OFS_54_SHIFT 8
-#define BCHP_NAND_SPARE_AREA_READ_OFS_34_BYTE_OFS_54_DEFAULT 0x000000ff
-
-/* NAND :: SPARE_AREA_READ_OFS_34 :: BYTE_OFS_55 [07:00] */
-#define BCHP_NAND_SPARE_AREA_READ_OFS_34_BYTE_OFS_55_MASK 0x000000ff
-#define BCHP_NAND_SPARE_AREA_READ_OFS_34_BYTE_OFS_55_SHIFT 0
-#define BCHP_NAND_SPARE_AREA_READ_OFS_34_BYTE_OFS_55_DEFAULT 0x000000ff
-
-/***************************************************************************
- *SPARE_AREA_READ_OFS_38 - Nand Flash Spare Area Read Bytes 56-59
- ***************************************************************************/
-/* NAND :: SPARE_AREA_READ_OFS_38 :: BYTE_OFS_56 [31:24] */
-#define BCHP_NAND_SPARE_AREA_READ_OFS_38_BYTE_OFS_56_MASK 0xff000000
-#define BCHP_NAND_SPARE_AREA_READ_OFS_38_BYTE_OFS_56_SHIFT 24
-#define BCHP_NAND_SPARE_AREA_READ_OFS_38_BYTE_OFS_56_DEFAULT 0x000000ff
-
-/* NAND :: SPARE_AREA_READ_OFS_38 :: BYTE_OFS_57 [23:16] */
-#define BCHP_NAND_SPARE_AREA_READ_OFS_38_BYTE_OFS_57_MASK 0x00ff0000
-#define BCHP_NAND_SPARE_AREA_READ_OFS_38_BYTE_OFS_57_SHIFT 16
-#define BCHP_NAND_SPARE_AREA_READ_OFS_38_BYTE_OFS_57_DEFAULT 0x000000ff
-
-/* NAND :: SPARE_AREA_READ_OFS_38 :: BYTE_OFS_58 [15:08] */
-#define BCHP_NAND_SPARE_AREA_READ_OFS_38_BYTE_OFS_58_MASK 0x0000ff00
-#define BCHP_NAND_SPARE_AREA_READ_OFS_38_BYTE_OFS_58_SHIFT 8
-#define BCHP_NAND_SPARE_AREA_READ_OFS_38_BYTE_OFS_58_DEFAULT 0x000000ff
-
-/* NAND :: SPARE_AREA_READ_OFS_38 :: BYTE_OFS_59 [07:00] */
-#define BCHP_NAND_SPARE_AREA_READ_OFS_38_BYTE_OFS_59_MASK 0x000000ff
-#define BCHP_NAND_SPARE_AREA_READ_OFS_38_BYTE_OFS_59_SHIFT 0
-#define BCHP_NAND_SPARE_AREA_READ_OFS_38_BYTE_OFS_59_DEFAULT 0x000000ff
-
-/***************************************************************************
- *SPARE_AREA_READ_OFS_3C - Nand Flash Spare Area Read Bytes 60-63
- ***************************************************************************/
-/* NAND :: SPARE_AREA_READ_OFS_3C :: BYTE_OFS_60 [31:24] */
-#define BCHP_NAND_SPARE_AREA_READ_OFS_3C_BYTE_OFS_60_MASK 0xff000000
-#define BCHP_NAND_SPARE_AREA_READ_OFS_3C_BYTE_OFS_60_SHIFT 24
-#define BCHP_NAND_SPARE_AREA_READ_OFS_3C_BYTE_OFS_60_DEFAULT 0x000000ff
-
-/* NAND :: SPARE_AREA_READ_OFS_3C :: BYTE_OFS_61 [23:16] */
-#define BCHP_NAND_SPARE_AREA_READ_OFS_3C_BYTE_OFS_61_MASK 0x00ff0000
-#define BCHP_NAND_SPARE_AREA_READ_OFS_3C_BYTE_OFS_61_SHIFT 16
-#define BCHP_NAND_SPARE_AREA_READ_OFS_3C_BYTE_OFS_61_DEFAULT 0x000000ff
-
-/* NAND :: SPARE_AREA_READ_OFS_3C :: BYTE_OFS_62 [15:08] */
-#define BCHP_NAND_SPARE_AREA_READ_OFS_3C_BYTE_OFS_62_MASK 0x0000ff00
-#define BCHP_NAND_SPARE_AREA_READ_OFS_3C_BYTE_OFS_62_SHIFT 8
-#define BCHP_NAND_SPARE_AREA_READ_OFS_3C_BYTE_OFS_62_DEFAULT 0x000000ff
-
-/* NAND :: SPARE_AREA_READ_OFS_3C :: BYTE_OFS_63 [07:00] */
-#define BCHP_NAND_SPARE_AREA_READ_OFS_3C_BYTE_OFS_63_MASK 0x000000ff
-#define BCHP_NAND_SPARE_AREA_READ_OFS_3C_BYTE_OFS_63_SHIFT 0
-#define BCHP_NAND_SPARE_AREA_READ_OFS_3C_BYTE_OFS_63_DEFAULT 0x000000ff
-
-/***************************************************************************
- *SPARE_AREA_WRITE_OFS_0 - Nand Flash Spare Area Write Bytes 0-3
- ***************************************************************************/
-/* NAND :: SPARE_AREA_WRITE_OFS_0 :: BYTE_OFS_0 [31:24] */
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_0_BYTE_OFS_0_MASK 0xff000000
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_0_BYTE_OFS_0_SHIFT 24
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_0_BYTE_OFS_0_DEFAULT 0x000000ff
-
-/* NAND :: SPARE_AREA_WRITE_OFS_0 :: BYTE_OFS_1 [23:16] */
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_0_BYTE_OFS_1_MASK 0x00ff0000
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_0_BYTE_OFS_1_SHIFT 16
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_0_BYTE_OFS_1_DEFAULT 0x000000ff
-
-/* NAND :: SPARE_AREA_WRITE_OFS_0 :: BYTE_OFS_2 [15:08] */
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_0_BYTE_OFS_2_MASK 0x0000ff00
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_0_BYTE_OFS_2_SHIFT 8
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_0_BYTE_OFS_2_DEFAULT 0x000000ff
-
-/* NAND :: SPARE_AREA_WRITE_OFS_0 :: BYTE_OFS_3 [07:00] */
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_0_BYTE_OFS_3_MASK 0x000000ff
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_0_BYTE_OFS_3_SHIFT 0
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_0_BYTE_OFS_3_DEFAULT 0x000000ff
-
-/***************************************************************************
- *SPARE_AREA_WRITE_OFS_4 - Nand Flash Spare Area Write Bytes 4-7
- ***************************************************************************/
-/* NAND :: SPARE_AREA_WRITE_OFS_4 :: BYTE_OFS_4 [31:24] */
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_4_BYTE_OFS_4_MASK 0xff000000
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_4_BYTE_OFS_4_SHIFT 24
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_4_BYTE_OFS_4_DEFAULT 0x000000ff
-
-/* NAND :: SPARE_AREA_WRITE_OFS_4 :: BYTE_OFS_5 [23:16] */
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_4_BYTE_OFS_5_MASK 0x00ff0000
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_4_BYTE_OFS_5_SHIFT 16
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_4_BYTE_OFS_5_DEFAULT 0x000000ff
-
-/* NAND :: SPARE_AREA_WRITE_OFS_4 :: BYTE_OFS_6 [15:08] */
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_4_BYTE_OFS_6_MASK 0x0000ff00
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_4_BYTE_OFS_6_SHIFT 8
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_4_BYTE_OFS_6_DEFAULT 0x000000ff
-
-/* NAND :: SPARE_AREA_WRITE_OFS_4 :: BYTE_OFS_7 [07:00] */
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_4_BYTE_OFS_7_MASK 0x000000ff
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_4_BYTE_OFS_7_SHIFT 0
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_4_BYTE_OFS_7_DEFAULT 0x000000ff
-
-/***************************************************************************
- *SPARE_AREA_WRITE_OFS_8 - Nand Flash Spare Area Write Bytes 8-11
- ***************************************************************************/
-/* NAND :: SPARE_AREA_WRITE_OFS_8 :: BYTE_OFS_8 [31:24] */
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_8_BYTE_OFS_8_MASK 0xff000000
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_8_BYTE_OFS_8_SHIFT 24
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_8_BYTE_OFS_8_DEFAULT 0x000000ff
-
-/* NAND :: SPARE_AREA_WRITE_OFS_8 :: BYTE_OFS_9 [23:16] */
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_8_BYTE_OFS_9_MASK 0x00ff0000
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_8_BYTE_OFS_9_SHIFT 16
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_8_BYTE_OFS_9_DEFAULT 0x000000ff
-
-/* NAND :: SPARE_AREA_WRITE_OFS_8 :: BYTE_OFS_10 [15:08] */
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_8_BYTE_OFS_10_MASK 0x0000ff00
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_8_BYTE_OFS_10_SHIFT 8
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_8_BYTE_OFS_10_DEFAULT 0x000000ff
-
-/* NAND :: SPARE_AREA_WRITE_OFS_8 :: BYTE_OFS_11 [07:00] */
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_8_BYTE_OFS_11_MASK 0x000000ff
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_8_BYTE_OFS_11_SHIFT 0
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_8_BYTE_OFS_11_DEFAULT 0x000000ff
-
-/***************************************************************************
- *SPARE_AREA_WRITE_OFS_C - Nand Flash Spare Area Write Bytes 12-15
- ***************************************************************************/
-/* NAND :: SPARE_AREA_WRITE_OFS_C :: BYTE_OFS_12 [31:24] */
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_C_BYTE_OFS_12_MASK 0xff000000
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_C_BYTE_OFS_12_SHIFT 24
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_C_BYTE_OFS_12_DEFAULT 0x000000ff
-
-/* NAND :: SPARE_AREA_WRITE_OFS_C :: BYTE_OFS_13 [23:16] */
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_C_BYTE_OFS_13_MASK 0x00ff0000
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_C_BYTE_OFS_13_SHIFT 16
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_C_BYTE_OFS_13_DEFAULT 0x000000ff
-
-/* NAND :: SPARE_AREA_WRITE_OFS_C :: BYTE_OFS_14 [15:08] */
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_C_BYTE_OFS_14_MASK 0x0000ff00
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_C_BYTE_OFS_14_SHIFT 8
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_C_BYTE_OFS_14_DEFAULT 0x000000ff
-
-/* NAND :: SPARE_AREA_WRITE_OFS_C :: BYTE_OFS_15 [07:00] */
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_C_BYTE_OFS_15_MASK 0x000000ff
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_C_BYTE_OFS_15_SHIFT 0
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_C_BYTE_OFS_15_DEFAULT 0x000000ff
-
-/***************************************************************************
- *SPARE_AREA_WRITE_OFS_10 - Nand Flash Spare Area Write Bytes 16-19
- ***************************************************************************/
-/* NAND :: SPARE_AREA_WRITE_OFS_10 :: BYTE_OFS_16 [31:24] */
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_10_BYTE_OFS_16_MASK 0xff000000
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_10_BYTE_OFS_16_SHIFT 24
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_10_BYTE_OFS_16_DEFAULT 0x000000ff
-
-/* NAND :: SPARE_AREA_WRITE_OFS_10 :: BYTE_OFS_17 [23:16] */
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_10_BYTE_OFS_17_MASK 0x00ff0000
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_10_BYTE_OFS_17_SHIFT 16
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_10_BYTE_OFS_17_DEFAULT 0x000000ff
-
-/* NAND :: SPARE_AREA_WRITE_OFS_10 :: BYTE_OFS_18 [15:08] */
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_10_BYTE_OFS_18_MASK 0x0000ff00
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_10_BYTE_OFS_18_SHIFT 8
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_10_BYTE_OFS_18_DEFAULT 0x000000ff
-
-/* NAND :: SPARE_AREA_WRITE_OFS_10 :: BYTE_OFS_19 [07:00] */
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_10_BYTE_OFS_19_MASK 0x000000ff
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_10_BYTE_OFS_19_SHIFT 0
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_10_BYTE_OFS_19_DEFAULT 0x000000ff
-
-/***************************************************************************
- *SPARE_AREA_WRITE_OFS_14 - Nand Flash Spare Area Write Bytes 20-23
- ***************************************************************************/
-/* NAND :: SPARE_AREA_WRITE_OFS_14 :: BYTE_OFS_20 [31:24] */
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_14_BYTE_OFS_20_MASK 0xff000000
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_14_BYTE_OFS_20_SHIFT 24
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_14_BYTE_OFS_20_DEFAULT 0x000000ff
-
-/* NAND :: SPARE_AREA_WRITE_OFS_14 :: BYTE_OFS_21 [23:16] */
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_14_BYTE_OFS_21_MASK 0x00ff0000
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_14_BYTE_OFS_21_SHIFT 16
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_14_BYTE_OFS_21_DEFAULT 0x000000ff
-
-/* NAND :: SPARE_AREA_WRITE_OFS_14 :: BYTE_OFS_22 [15:08] */
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_14_BYTE_OFS_22_MASK 0x0000ff00
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_14_BYTE_OFS_22_SHIFT 8
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_14_BYTE_OFS_22_DEFAULT 0x000000ff
-
-/* NAND :: SPARE_AREA_WRITE_OFS_14 :: BYTE_OFS_23 [07:00] */
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_14_BYTE_OFS_23_MASK 0x000000ff
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_14_BYTE_OFS_23_SHIFT 0
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_14_BYTE_OFS_23_DEFAULT 0x000000ff
-
-/***************************************************************************
- *SPARE_AREA_WRITE_OFS_18 - Nand Flash Spare Area Write Bytes 24-27
- ***************************************************************************/
-/* NAND :: SPARE_AREA_WRITE_OFS_18 :: BYTE_OFS_24 [31:24] */
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_18_BYTE_OFS_24_MASK 0xff000000
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_18_BYTE_OFS_24_SHIFT 24
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_18_BYTE_OFS_24_DEFAULT 0x000000ff
-
-/* NAND :: SPARE_AREA_WRITE_OFS_18 :: BYTE_OFS_25 [23:16] */
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_18_BYTE_OFS_25_MASK 0x00ff0000
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_18_BYTE_OFS_25_SHIFT 16
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_18_BYTE_OFS_25_DEFAULT 0x000000ff
-
-/* NAND :: SPARE_AREA_WRITE_OFS_18 :: BYTE_OFS_26 [15:08] */
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_18_BYTE_OFS_26_MASK 0x0000ff00
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_18_BYTE_OFS_26_SHIFT 8
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_18_BYTE_OFS_26_DEFAULT 0x000000ff
-
-/* NAND :: SPARE_AREA_WRITE_OFS_18 :: BYTE_OFS_27 [07:00] */
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_18_BYTE_OFS_27_MASK 0x000000ff
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_18_BYTE_OFS_27_SHIFT 0
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_18_BYTE_OFS_27_DEFAULT 0x000000ff
-
-/***************************************************************************
- *SPARE_AREA_WRITE_OFS_1C - Nand Flash Spare Area Write Bytes 28-31
- ***************************************************************************/
-/* NAND :: SPARE_AREA_WRITE_OFS_1C :: BYTE_OFS_28 [31:24] */
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_1C_BYTE_OFS_28_MASK 0xff000000
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_1C_BYTE_OFS_28_SHIFT 24
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_1C_BYTE_OFS_28_DEFAULT 0x000000ff
-
-/* NAND :: SPARE_AREA_WRITE_OFS_1C :: BYTE_OFS_29 [23:16] */
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_1C_BYTE_OFS_29_MASK 0x00ff0000
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_1C_BYTE_OFS_29_SHIFT 16
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_1C_BYTE_OFS_29_DEFAULT 0x000000ff
-
-/* NAND :: SPARE_AREA_WRITE_OFS_1C :: BYTE_OFS_30 [15:08] */
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_1C_BYTE_OFS_30_MASK 0x0000ff00
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_1C_BYTE_OFS_30_SHIFT 8
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_1C_BYTE_OFS_30_DEFAULT 0x000000ff
-
-/* NAND :: SPARE_AREA_WRITE_OFS_1C :: BYTE_OFS_31 [07:00] */
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_1C_BYTE_OFS_31_MASK 0x000000ff
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_1C_BYTE_OFS_31_SHIFT 0
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_1C_BYTE_OFS_31_DEFAULT 0x000000ff
-
-/***************************************************************************
- *SPARE_AREA_WRITE_OFS_20 - Nand Flash Spare Area Write Bytes 32-35
- ***************************************************************************/
-/* NAND :: SPARE_AREA_WRITE_OFS_20 :: BYTE_OFS_32 [31:24] */
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_20_BYTE_OFS_32_MASK 0xff000000
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_20_BYTE_OFS_32_SHIFT 24
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_20_BYTE_OFS_32_DEFAULT 0x000000ff
-
-/* NAND :: SPARE_AREA_WRITE_OFS_20 :: BYTE_OFS_33 [23:16] */
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_20_BYTE_OFS_33_MASK 0x00ff0000
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_20_BYTE_OFS_33_SHIFT 16
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_20_BYTE_OFS_33_DEFAULT 0x000000ff
-
-/* NAND :: SPARE_AREA_WRITE_OFS_20 :: BYTE_OFS_34 [15:08] */
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_20_BYTE_OFS_34_MASK 0x0000ff00
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_20_BYTE_OFS_34_SHIFT 8
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_20_BYTE_OFS_34_DEFAULT 0x000000ff
-
-/* NAND :: SPARE_AREA_WRITE_OFS_20 :: BYTE_OFS_35 [07:00] */
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_20_BYTE_OFS_35_MASK 0x000000ff
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_20_BYTE_OFS_35_SHIFT 0
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_20_BYTE_OFS_35_DEFAULT 0x000000ff
-
-/***************************************************************************
- *SPARE_AREA_WRITE_OFS_24 - Nand Flash Spare Area Write Bytes 36-39
- ***************************************************************************/
-/* NAND :: SPARE_AREA_WRITE_OFS_24 :: BYTE_OFS_36 [31:24] */
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_24_BYTE_OFS_36_MASK 0xff000000
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_24_BYTE_OFS_36_SHIFT 24
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_24_BYTE_OFS_36_DEFAULT 0x000000ff
-
-/* NAND :: SPARE_AREA_WRITE_OFS_24 :: BYTE_OFS_37 [23:16] */
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_24_BYTE_OFS_37_MASK 0x00ff0000
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_24_BYTE_OFS_37_SHIFT 16
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_24_BYTE_OFS_37_DEFAULT 0x000000ff
-
-/* NAND :: SPARE_AREA_WRITE_OFS_24 :: BYTE_OFS_38 [15:08] */
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_24_BYTE_OFS_38_MASK 0x0000ff00
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_24_BYTE_OFS_38_SHIFT 8
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_24_BYTE_OFS_38_DEFAULT 0x000000ff
-
-/* NAND :: SPARE_AREA_WRITE_OFS_24 :: BYTE_OFS_39 [07:00] */
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_24_BYTE_OFS_39_MASK 0x000000ff
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_24_BYTE_OFS_39_SHIFT 0
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_24_BYTE_OFS_39_DEFAULT 0x000000ff
-
-/***************************************************************************
- *SPARE_AREA_WRITE_OFS_28 - Nand Flash Spare Area Write Bytes 40-43
- ***************************************************************************/
-/* NAND :: SPARE_AREA_WRITE_OFS_28 :: BYTE_OFS_40 [31:24] */
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_28_BYTE_OFS_40_MASK 0xff000000
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_28_BYTE_OFS_40_SHIFT 24
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_28_BYTE_OFS_40_DEFAULT 0x000000ff
-
-/* NAND :: SPARE_AREA_WRITE_OFS_28 :: BYTE_OFS_41 [23:16] */
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_28_BYTE_OFS_41_MASK 0x00ff0000
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_28_BYTE_OFS_41_SHIFT 16
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_28_BYTE_OFS_41_DEFAULT 0x000000ff
-
-/* NAND :: SPARE_AREA_WRITE_OFS_28 :: BYTE_OFS_42 [15:08] */
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_28_BYTE_OFS_42_MASK 0x0000ff00
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_28_BYTE_OFS_42_SHIFT 8
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_28_BYTE_OFS_42_DEFAULT 0x000000ff
-
-/* NAND :: SPARE_AREA_WRITE_OFS_28 :: BYTE_OFS_43 [07:00] */
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_28_BYTE_OFS_43_MASK 0x000000ff
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_28_BYTE_OFS_43_SHIFT 0
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_28_BYTE_OFS_43_DEFAULT 0x000000ff
-
-/***************************************************************************
- *SPARE_AREA_WRITE_OFS_2C - Nand Flash Spare Area Write Bytes 44-47
- ***************************************************************************/
-/* NAND :: SPARE_AREA_WRITE_OFS_2C :: BYTE_OFS_44 [31:24] */
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_2C_BYTE_OFS_44_MASK 0xff000000
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_2C_BYTE_OFS_44_SHIFT 24
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_2C_BYTE_OFS_44_DEFAULT 0x000000ff
-
-/* NAND :: SPARE_AREA_WRITE_OFS_2C :: BYTE_OFS_45 [23:16] */
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_2C_BYTE_OFS_45_MASK 0x00ff0000
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_2C_BYTE_OFS_45_SHIFT 16
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_2C_BYTE_OFS_45_DEFAULT 0x000000ff
-
-/* NAND :: SPARE_AREA_WRITE_OFS_2C :: BYTE_OFS_46 [15:08] */
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_2C_BYTE_OFS_46_MASK 0x0000ff00
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_2C_BYTE_OFS_46_SHIFT 8
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_2C_BYTE_OFS_46_DEFAULT 0x000000ff
-
-/* NAND :: SPARE_AREA_WRITE_OFS_2C :: BYTE_OFS_47 [07:00] */
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_2C_BYTE_OFS_47_MASK 0x000000ff
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_2C_BYTE_OFS_47_SHIFT 0
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_2C_BYTE_OFS_47_DEFAULT 0x000000ff
-
-/***************************************************************************
- *SPARE_AREA_WRITE_OFS_30 - Nand Flash Spare Area Write Bytes 48-51
- ***************************************************************************/
-/* NAND :: SPARE_AREA_WRITE_OFS_30 :: BYTE_OFS_48 [31:24] */
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_30_BYTE_OFS_48_MASK 0xff000000
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_30_BYTE_OFS_48_SHIFT 24
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_30_BYTE_OFS_48_DEFAULT 0x000000ff
-
-/* NAND :: SPARE_AREA_WRITE_OFS_30 :: BYTE_OFS_49 [23:16] */
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_30_BYTE_OFS_49_MASK 0x00ff0000
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_30_BYTE_OFS_49_SHIFT 16
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_30_BYTE_OFS_49_DEFAULT 0x000000ff
-
-/* NAND :: SPARE_AREA_WRITE_OFS_30 :: BYTE_OFS_50 [15:08] */
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_30_BYTE_OFS_50_MASK 0x0000ff00
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_30_BYTE_OFS_50_SHIFT 8
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_30_BYTE_OFS_50_DEFAULT 0x000000ff
-
-/* NAND :: SPARE_AREA_WRITE_OFS_30 :: BYTE_OFS_51 [07:00] */
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_30_BYTE_OFS_51_MASK 0x000000ff
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_30_BYTE_OFS_51_SHIFT 0
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_30_BYTE_OFS_51_DEFAULT 0x000000ff
-
-/***************************************************************************
- *SPARE_AREA_WRITE_OFS_34 - Nand Flash Spare Area Write Bytes 52-55
- ***************************************************************************/
-/* NAND :: SPARE_AREA_WRITE_OFS_34 :: BYTE_OFS_52 [31:24] */
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_34_BYTE_OFS_52_MASK 0xff000000
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_34_BYTE_OFS_52_SHIFT 24
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_34_BYTE_OFS_52_DEFAULT 0x000000ff
-
-/* NAND :: SPARE_AREA_WRITE_OFS_34 :: BYTE_OFS_53 [23:16] */
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_34_BYTE_OFS_53_MASK 0x00ff0000
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_34_BYTE_OFS_53_SHIFT 16
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_34_BYTE_OFS_53_DEFAULT 0x000000ff
-
-/* NAND :: SPARE_AREA_WRITE_OFS_34 :: BYTE_OFS_54 [15:08] */
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_34_BYTE_OFS_54_MASK 0x0000ff00
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_34_BYTE_OFS_54_SHIFT 8
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_34_BYTE_OFS_54_DEFAULT 0x000000ff
-
-/* NAND :: SPARE_AREA_WRITE_OFS_34 :: BYTE_OFS_55 [07:00] */
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_34_BYTE_OFS_55_MASK 0x000000ff
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_34_BYTE_OFS_55_SHIFT 0
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_34_BYTE_OFS_55_DEFAULT 0x000000ff
-
-/***************************************************************************
- *SPARE_AREA_WRITE_OFS_38 - Nand Flash Spare Area Write Bytes 56-59
- ***************************************************************************/
-/* NAND :: SPARE_AREA_WRITE_OFS_38 :: BYTE_OFS_56 [31:24] */
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_38_BYTE_OFS_56_MASK 0xff000000
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_38_BYTE_OFS_56_SHIFT 24
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_38_BYTE_OFS_56_DEFAULT 0x000000ff
-
-/* NAND :: SPARE_AREA_WRITE_OFS_38 :: BYTE_OFS_57 [23:16] */
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_38_BYTE_OFS_57_MASK 0x00ff0000
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_38_BYTE_OFS_57_SHIFT 16
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_38_BYTE_OFS_57_DEFAULT 0x000000ff
-
-/* NAND :: SPARE_AREA_WRITE_OFS_38 :: BYTE_OFS_58 [15:08] */
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_38_BYTE_OFS_58_MASK 0x0000ff00
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_38_BYTE_OFS_58_SHIFT 8
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_38_BYTE_OFS_58_DEFAULT 0x000000ff
-
-/* NAND :: SPARE_AREA_WRITE_OFS_38 :: BYTE_OFS_59 [07:00] */
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_38_BYTE_OFS_59_MASK 0x000000ff
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_38_BYTE_OFS_59_SHIFT 0
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_38_BYTE_OFS_59_DEFAULT 0x000000ff
-
-/***************************************************************************
- *SPARE_AREA_WRITE_OFS_3C - Nand Flash Spare Area Write Bytes 60-63
- ***************************************************************************/
-/* NAND :: SPARE_AREA_WRITE_OFS_3C :: BYTE_OFS_60 [31:24] */
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_3C_BYTE_OFS_60_MASK 0xff000000
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_3C_BYTE_OFS_60_SHIFT 24
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_3C_BYTE_OFS_60_DEFAULT 0x000000ff
-
-/* NAND :: SPARE_AREA_WRITE_OFS_3C :: BYTE_OFS_61 [23:16] */
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_3C_BYTE_OFS_61_MASK 0x00ff0000
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_3C_BYTE_OFS_61_SHIFT 16
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_3C_BYTE_OFS_61_DEFAULT 0x000000ff
-
-/* NAND :: SPARE_AREA_WRITE_OFS_3C :: BYTE_OFS_62 [15:08] */
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_3C_BYTE_OFS_62_MASK 0x0000ff00
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_3C_BYTE_OFS_62_SHIFT 8
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_3C_BYTE_OFS_62_DEFAULT 0x000000ff
-
-/* NAND :: SPARE_AREA_WRITE_OFS_3C :: BYTE_OFS_63 [07:00] */
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_3C_BYTE_OFS_63_MASK 0x000000ff
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_3C_BYTE_OFS_63_SHIFT 0
-#define BCHP_NAND_SPARE_AREA_WRITE_OFS_3C_BYTE_OFS_63_DEFAULT 0x000000ff
-
-/***************************************************************************
- *DDR_TIMING - Nand Flash DDR TIMING
- ***************************************************************************/
-/* NAND :: DDR_TIMING :: reserved0 [31:24] */
-#define BCHP_NAND_DDR_TIMING_reserved0_MASK 0xff000000
-#define BCHP_NAND_DDR_TIMING_reserved0_SHIFT 24
-
-/* NAND :: DDR_TIMING :: tCAD [23:20] */
-#define BCHP_NAND_DDR_TIMING_tCAD_MASK 0x00f00000
-#define BCHP_NAND_DDR_TIMING_tCAD_SHIFT 20
-#define BCHP_NAND_DDR_TIMING_tCAD_DEFAULT 0x00000004
-
-/* NAND :: DDR_TIMING :: reserved1 [19:17] */
-#define BCHP_NAND_DDR_TIMING_reserved1_MASK 0x000e0000
-#define BCHP_NAND_DDR_TIMING_reserved1_SHIFT 17
-
-/* NAND :: DDR_TIMING :: tWHR [16:12] */
-#define BCHP_NAND_DDR_TIMING_tWHR_MASK 0x0001f000
-#define BCHP_NAND_DDR_TIMING_tWHR_SHIFT 12
-#define BCHP_NAND_DDR_TIMING_tWHR_DEFAULT 0x00000014
-
-/* NAND :: DDR_TIMING :: tCS [11:08] */
-#define BCHP_NAND_DDR_TIMING_tCS_MASK 0x00000f00
-#define BCHP_NAND_DDR_TIMING_tCS_SHIFT 8
-#define BCHP_NAND_DDR_TIMING_tCS_DEFAULT 0x00000002
-
-/* NAND :: DDR_TIMING :: tWB [07:04] */
-#define BCHP_NAND_DDR_TIMING_tWB_MASK 0x000000f0
-#define BCHP_NAND_DDR_TIMING_tWB_SHIFT 4
-#define BCHP_NAND_DDR_TIMING_tWB_DEFAULT 0x0000000f
-
-/* NAND :: DDR_TIMING :: tADL [03:00] */
-#define BCHP_NAND_DDR_TIMING_tADL_MASK 0x0000000f
-#define BCHP_NAND_DDR_TIMING_tADL_SHIFT 0
-#define BCHP_NAND_DDR_TIMING_tADL_DEFAULT 0x00000007
-
-/***************************************************************************
- *DDR_NCDL_CALIB_CTL - Nand Flash Calibration Control for Master DLL
- ***************************************************************************/
-/* NAND :: DDR_NCDL_CALIB_CTL :: reserved0 [31:04] */
-#define BCHP_NAND_DDR_NCDL_CALIB_CTL_reserved0_MASK 0xfffffff0
-#define BCHP_NAND_DDR_NCDL_CALIB_CTL_reserved0_SHIFT 4
-
-/* NAND :: DDR_NCDL_CALIB_CTL :: CALIB_PERIODIC [03:03] */
-#define BCHP_NAND_DDR_NCDL_CALIB_CTL_CALIB_PERIODIC_MASK 0x00000008
-#define BCHP_NAND_DDR_NCDL_CALIB_CTL_CALIB_PERIODIC_SHIFT 3
-#define BCHP_NAND_DDR_NCDL_CALIB_CTL_CALIB_PERIODIC_DEFAULT 0x00000000
-
-/* NAND :: DDR_NCDL_CALIB_CTL :: CALIB_ALWAYS [02:02] */
-#define BCHP_NAND_DDR_NCDL_CALIB_CTL_CALIB_ALWAYS_MASK 0x00000004
-#define BCHP_NAND_DDR_NCDL_CALIB_CTL_CALIB_ALWAYS_SHIFT 2
-#define BCHP_NAND_DDR_NCDL_CALIB_CTL_CALIB_ALWAYS_DEFAULT 0x00000000
-
-/* NAND :: DDR_NCDL_CALIB_CTL :: CALIB_ONCE [01:01] */
-#define BCHP_NAND_DDR_NCDL_CALIB_CTL_CALIB_ONCE_MASK 0x00000002
-#define BCHP_NAND_DDR_NCDL_CALIB_CTL_CALIB_ONCE_SHIFT 1
-#define BCHP_NAND_DDR_NCDL_CALIB_CTL_CALIB_ONCE_DEFAULT 0x00000000
-
-/* NAND :: DDR_NCDL_CALIB_CTL :: CALIB_EN [00:00] */
-#define BCHP_NAND_DDR_NCDL_CALIB_CTL_CALIB_EN_MASK 0x00000001
-#define BCHP_NAND_DDR_NCDL_CALIB_CTL_CALIB_EN_SHIFT 0
-#define BCHP_NAND_DDR_NCDL_CALIB_CTL_CALIB_EN_DEFAULT 0x00000000
-
-/***************************************************************************
- *DDR_NCDL_CALIB_PERIOD - Nand Flash Calibration Period
- ***************************************************************************/
-/* NAND :: DDR_NCDL_CALIB_PERIOD :: reserved0 [31:20] */
-#define BCHP_NAND_DDR_NCDL_CALIB_PERIOD_reserved0_MASK 0xfff00000
-#define BCHP_NAND_DDR_NCDL_CALIB_PERIOD_reserved0_SHIFT 20
-
-/* NAND :: DDR_NCDL_CALIB_PERIOD :: CALIB_PERIOD [19:00] */
-#define BCHP_NAND_DDR_NCDL_CALIB_PERIOD_CALIB_PERIOD_MASK 0x000fffff
-#define BCHP_NAND_DDR_NCDL_CALIB_PERIOD_CALIB_PERIOD_SHIFT 0
-#define BCHP_NAND_DDR_NCDL_CALIB_PERIOD_CALIB_PERIOD_DEFAULT 0x00000000
-
-/***************************************************************************
- *DDR_NCDL_CALIB_STAT - Nand Flash Calibration Status for Master DLL
- ***************************************************************************/
-/* NAND :: DDR_NCDL_CALIB_STAT :: reserved0 [31:16] */
-#define BCHP_NAND_DDR_NCDL_CALIB_STAT_reserved0_MASK 0xffff0000
-#define BCHP_NAND_DDR_NCDL_CALIB_STAT_reserved0_SHIFT 16
-
-/* NAND :: DDR_NCDL_CALIB_STAT :: NCDL_PHASE [15:08] */
-#define BCHP_NAND_DDR_NCDL_CALIB_STAT_NCDL_PHASE_MASK 0x0000ff00
-#define BCHP_NAND_DDR_NCDL_CALIB_STAT_NCDL_PHASE_SHIFT 8
-#define BCHP_NAND_DDR_NCDL_CALIB_STAT_NCDL_PHASE_DEFAULT 0x00000000
-
-/* NAND :: DDR_NCDL_CALIB_STAT :: reserved1 [07:01] */
-#define BCHP_NAND_DDR_NCDL_CALIB_STAT_reserved1_MASK 0x000000fe
-#define BCHP_NAND_DDR_NCDL_CALIB_STAT_reserved1_SHIFT 1
-
-/* NAND :: DDR_NCDL_CALIB_STAT :: CALIB_LOCK [00:00] */
-#define BCHP_NAND_DDR_NCDL_CALIB_STAT_CALIB_LOCK_MASK 0x00000001
-#define BCHP_NAND_DDR_NCDL_CALIB_STAT_CALIB_LOCK_SHIFT 0
-#define BCHP_NAND_DDR_NCDL_CALIB_STAT_CALIB_LOCK_DEFAULT 0x00000000
-
-/***************************************************************************
- *DDR_NCDL_MODE - Nand Flash NCDL mode for Slave DLLs
- ***************************************************************************/
-/* NAND :: DDR_NCDL_MODE :: reserved0 [31:05] */
-#define BCHP_NAND_DDR_NCDL_MODE_reserved0_MASK 0xffffffe0
-#define BCHP_NAND_DDR_NCDL_MODE_reserved0_SHIFT 5
-
-/* NAND :: DDR_NCDL_MODE :: RDNCDL [04:04] */
-#define BCHP_NAND_DDR_NCDL_MODE_RDNCDL_MASK 0x00000010
-#define BCHP_NAND_DDR_NCDL_MODE_RDNCDL_SHIFT 4
-#define BCHP_NAND_DDR_NCDL_MODE_RDNCDL_DEFAULT 0x00000000
-
-/* NAND :: DDR_NCDL_MODE :: reserved1 [03:01] */
-#define BCHP_NAND_DDR_NCDL_MODE_reserved1_MASK 0x0000000e
-#define BCHP_NAND_DDR_NCDL_MODE_reserved1_SHIFT 1
-
-/* NAND :: DDR_NCDL_MODE :: WRNCDL [00:00] */
-#define BCHP_NAND_DDR_NCDL_MODE_WRNCDL_MASK 0x00000001
-#define BCHP_NAND_DDR_NCDL_MODE_WRNCDL_SHIFT 0
-#define BCHP_NAND_DDR_NCDL_MODE_WRNCDL_DEFAULT 0x00000000
-
-/***************************************************************************
- *DDR_NCDL_OFFSET - Nand Flash NCDL offset for Slave DLLs
- ***************************************************************************/
-/* NAND :: DDR_NCDL_OFFSET :: reserved0 [31:25] */
-#define BCHP_NAND_DDR_NCDL_OFFSET_reserved0_MASK 0xfe000000
-#define BCHP_NAND_DDR_NCDL_OFFSET_reserved0_SHIFT 25
-
-/* NAND :: DDR_NCDL_OFFSET :: RDNCDL_OFF [24:16] */
-#define BCHP_NAND_DDR_NCDL_OFFSET_RDNCDL_OFF_MASK 0x01ff0000
-#define BCHP_NAND_DDR_NCDL_OFFSET_RDNCDL_OFF_SHIFT 16
-#define BCHP_NAND_DDR_NCDL_OFFSET_RDNCDL_OFF_DEFAULT 0x00000000
-
-/* NAND :: DDR_NCDL_OFFSET :: reserved1 [15:09] */
-#define BCHP_NAND_DDR_NCDL_OFFSET_reserved1_MASK 0x0000fe00
-#define BCHP_NAND_DDR_NCDL_OFFSET_reserved1_SHIFT 9
-
-/* NAND :: DDR_NCDL_OFFSET :: WRNCDL_OFF [08:00] */
-#define BCHP_NAND_DDR_NCDL_OFFSET_WRNCDL_OFF_MASK 0x000001ff
-#define BCHP_NAND_DDR_NCDL_OFFSET_WRNCDL_OFF_SHIFT 0
-#define BCHP_NAND_DDR_NCDL_OFFSET_WRNCDL_OFF_DEFAULT 0x00000000
-
-/***************************************************************************
- *DDR_PHY_CTL - Nand Flash DDR PHY CONTROL
- ***************************************************************************/
-/* NAND :: DDR_PHY_CTL :: reserved0 [31:02] */
-#define BCHP_NAND_DDR_PHY_CTL_reserved0_MASK 0xfffffffc
-#define BCHP_NAND_DDR_PHY_CTL_reserved0_SHIFT 2
-
-/* NAND :: DDR_PHY_CTL :: DDR_MODE [01:01] */
-#define BCHP_NAND_DDR_PHY_CTL_DDR_MODE_MASK 0x00000002
-#define BCHP_NAND_DDR_PHY_CTL_DDR_MODE_SHIFT 1
-#define BCHP_NAND_DDR_PHY_CTL_DDR_MODE_DEFAULT 0x00000000
-
-/* NAND :: DDR_PHY_CTL :: reserved1 [00:00] */
-#define BCHP_NAND_DDR_PHY_CTL_reserved1_MASK 0x00000001
-#define BCHP_NAND_DDR_PHY_CTL_reserved1_SHIFT 0
-
-/***************************************************************************
- *DDR_PHY_BIST_CTL - Nand Flash DDR PHY BIST CONTROL
- ***************************************************************************/
-/* NAND :: DDR_PHY_BIST_CTL :: reserved0 [31:05] */
-#define BCHP_NAND_DDR_PHY_BIST_CTL_reserved0_MASK 0xffffffe0
-#define BCHP_NAND_DDR_PHY_BIST_CTL_reserved0_SHIFT 5
-
-/* NAND :: DDR_PHY_BIST_CTL :: BIST_CLR [04:04] */
-#define BCHP_NAND_DDR_PHY_BIST_CTL_BIST_CLR_MASK 0x00000010
-#define BCHP_NAND_DDR_PHY_BIST_CTL_BIST_CLR_SHIFT 4
-#define BCHP_NAND_DDR_PHY_BIST_CTL_BIST_CLR_DEFAULT 0x00000000
-
-/* NAND :: DDR_PHY_BIST_CTL :: reserved1 [03:01] */
-#define BCHP_NAND_DDR_PHY_BIST_CTL_reserved1_MASK 0x0000000e
-#define BCHP_NAND_DDR_PHY_BIST_CTL_reserved1_SHIFT 1
-
-/* NAND :: DDR_PHY_BIST_CTL :: BIST_START [00:00] */
-#define BCHP_NAND_DDR_PHY_BIST_CTL_BIST_START_MASK 0x00000001
-#define BCHP_NAND_DDR_PHY_BIST_CTL_BIST_START_SHIFT 0
-#define BCHP_NAND_DDR_PHY_BIST_CTL_BIST_START_DEFAULT 0x00000000
-
-/***************************************************************************
- *DDR_PHY_BIST_STAT - Nand Flash DDR PHY BIST STATUS
- ***************************************************************************/
-/* NAND :: DDR_PHY_BIST_STAT :: reserved0 [31:07] */
-#define BCHP_NAND_DDR_PHY_BIST_STAT_reserved0_MASK 0xffffff80
-#define BCHP_NAND_DDR_PHY_BIST_STAT_reserved0_SHIFT 7
-
-/* NAND :: DDR_PHY_BIST_STAT :: W1_DATA_RDPH_ERR [06:06] */
-#define BCHP_NAND_DDR_PHY_BIST_STAT_W1_DATA_RDPH_ERR_MASK 0x00000040
-#define BCHP_NAND_DDR_PHY_BIST_STAT_W1_DATA_RDPH_ERR_SHIFT 6
-
-/* NAND :: DDR_PHY_BIST_STAT :: W0_DATA_RDPH_ERR [05:05] */
-#define BCHP_NAND_DDR_PHY_BIST_STAT_W0_DATA_RDPH_ERR_MASK 0x00000020
-#define BCHP_NAND_DDR_PHY_BIST_STAT_W0_DATA_RDPH_ERR_SHIFT 5
-
-/* NAND :: DDR_PHY_BIST_STAT :: W1_DATA_WRPH_ERR [04:04] */
-#define BCHP_NAND_DDR_PHY_BIST_STAT_W1_DATA_WRPH_ERR_MASK 0x00000010
-#define BCHP_NAND_DDR_PHY_BIST_STAT_W1_DATA_WRPH_ERR_SHIFT 4
-
-/* NAND :: DDR_PHY_BIST_STAT :: W0_DATA_WRPH_ERR [03:03] */
-#define BCHP_NAND_DDR_PHY_BIST_STAT_W0_DATA_WRPH_ERR_MASK 0x00000008
-#define BCHP_NAND_DDR_PHY_BIST_STAT_W0_DATA_WRPH_ERR_SHIFT 3
-
-/* NAND :: DDR_PHY_BIST_STAT :: W1_ADDR_ERR [02:02] */
-#define BCHP_NAND_DDR_PHY_BIST_STAT_W1_ADDR_ERR_MASK 0x00000004
-#define BCHP_NAND_DDR_PHY_BIST_STAT_W1_ADDR_ERR_SHIFT 2
-
-/* NAND :: DDR_PHY_BIST_STAT :: W0_ADDR_ERR [01:01] */
-#define BCHP_NAND_DDR_PHY_BIST_STAT_W0_ADDR_ERR_MASK 0x00000002
-#define BCHP_NAND_DDR_PHY_BIST_STAT_W0_ADDR_ERR_SHIFT 1
-
-/* NAND :: DDR_PHY_BIST_STAT :: BIST_DONE [00:00] */
-#define BCHP_NAND_DDR_PHY_BIST_STAT_BIST_DONE_MASK 0x00000001
-#define BCHP_NAND_DDR_PHY_BIST_STAT_BIST_DONE_SHIFT 0
-
-/***************************************************************************
- *DDR_DIAG_STAT0 - Nand Flash DDR DIAG STATUS0
- ***************************************************************************/
-/* NAND :: DDR_DIAG_STAT0 :: DIAG_STATUS [31:00] */
-#define BCHP_NAND_DDR_DIAG_STAT0_DIAG_STATUS_MASK 0xffffffff
-#define BCHP_NAND_DDR_DIAG_STAT0_DIAG_STATUS_SHIFT 0
-
-/***************************************************************************
- *DDR_DIAG_STAT1 - Nand Flash DDR DIAG STATUS1
- ***************************************************************************/
-/* NAND :: DDR_DIAG_STAT1 :: DIAG_STATUS [31:00] */
-#define BCHP_NAND_DDR_DIAG_STAT1_DIAG_STATUS_MASK 0xffffffff
-#define BCHP_NAND_DDR_DIAG_STAT1_DIAG_STATUS_SHIFT 0
-
-/***************************************************************************
- *FLASH_CACHE%i - Flash Cache Buffer Read Access
- ***************************************************************************/
-#define BCHP_NAND_FLASH_CACHEi_ARRAY_BASE 0x00442c00
-#define BCHP_NAND_FLASH_CACHEi_ARRAY_START 0
-#define BCHP_NAND_FLASH_CACHEi_ARRAY_END 127
-#define BCHP_NAND_FLASH_CACHEi_ARRAY_ELEMENT_SIZE 32
-
-/***************************************************************************
- *FLASH_CACHE%i - Flash Cache Buffer Read Access
- ***************************************************************************/
-/* NAND :: FLASH_CACHEi :: WORD [31:00] */
-#define BCHP_NAND_FLASH_CACHEi_WORD_MASK 0xffffffff
-#define BCHP_NAND_FLASH_CACHEi_WORD_SHIFT 0
-
-
-#endif /* #ifndef BCHP_NAND_H__ */
-
-/* End of File */
diff --git a/include/linux/brcmstb/7439a0/bchp_pcie_0_dma.h b/include/linux/brcmstb/7439a0/bchp_pcie_0_dma.h
deleted file mode 100644
index 14772bf..0000000
--- a/include/linux/brcmstb/7439a0/bchp_pcie_0_dma.h
+++ /dev/null
@@ -1,735 +0,0 @@
-/***************************************************************************
- * Copyright (c) 1999-2013, Broadcom Corporation
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
- *
- * Module Description:
- * DO NOT EDIT THIS FILE DIRECTLY
- *
- * This module was generated magically with RDB from a source description
- * file. You must edit the source file for changes to be made to this file.
- *
- *
- * Date: Generated on Tue Apr 16 03:26:51 2013
- * MD5 Checksum d41d8cd98f00b204e9800998ecf8427e
- *
- * Compiled with: RDB Utility combo_header.pl
- * RDB Parser 3.0
- * unknown unknown
- * Perl Interpreter 5.008008
- * Operating System linux
- *
- * Revision History:
- *
- * $brcm_Log: $
- *
- ***************************************************************************/
-
-#ifndef BCHP_PCIE_0_DMA_H__
-#define BCHP_PCIE_0_DMA_H__
-
-/***************************************************************************
- *PCIE_0_DMA - PCI-E DMA Registers
- ***************************************************************************/
-#define BCHP_PCIE_0_DMA_TX_FIRST_DESC_L_ADDR_LIST0 0x00474400 /* Tx Descriptor List0 First Descriptor lower Address */
-#define BCHP_PCIE_0_DMA_TX_FIRST_DESC_U_ADDR_LIST0 0x00474404 /* Tx Descriptor List0 First Descriptor Upper Address */
-#define BCHP_PCIE_0_DMA_TX_FIRST_DESC_L_ADDR_LIST1 0x00474408 /* Tx Descriptor List1 First Descriptor Lower Address */
-#define BCHP_PCIE_0_DMA_TX_FIRST_DESC_U_ADDR_LIST1 0x0047440c /* Tx Descriptor List1 First Descriptor Upper Address */
-#define BCHP_PCIE_0_DMA_TX_SW_DESC_LIST_CTRL_STS 0x00474410 /* Tx Software Descriptor List Control and Status */
-#define BCHP_PCIE_0_DMA_TX_WAKE_CTRL 0x00474414 /* Tx Wake Control */
-#define BCHP_PCIE_0_DMA_TX_ERROR_STATUS 0x00474418 /* Tx Engine Error Status */
-#define BCHP_PCIE_0_DMA_TX_LIST0_CUR_DESC_L_ADDR 0x0047441c /* Tx List0 Current Descriptor Lower Address */
-#define BCHP_PCIE_0_DMA_TX_LIST0_CUR_DESC_U_ADDR 0x00474420 /* Tx List0 Current Descriptor Upper Address */
-#define BCHP_PCIE_0_DMA_TX_LIST0_CUR_BYTE_CNT 0x00474424 /* Tx List0 Current Descriptor Byte Count */
-#define BCHP_PCIE_0_DMA_TX_LIST1_CUR_DESC_L_ADDR 0x00474428 /* Tx List1 Current Descriptor Lower Address */
-#define BCHP_PCIE_0_DMA_TX_LIST1_CUR_DESC_U_ADDR 0x0047442c /* Tx List1 Current Descriptor Upper Address */
-#define BCHP_PCIE_0_DMA_TX_LIST1_CUR_BYTE_CNT 0x00474430 /* Tx List1 Current Descriptor Byte Count */
-#define BCHP_PCIE_0_DMA_RX_FIRST_DESC_L_ADDR_LIST0 0x00474434 /* Rx Descriptor List0 First Descriptor Lower Address */
-#define BCHP_PCIE_0_DMA_RX_FIRST_DESC_U_ADDR_LIST0 0x00474438 /* Rx Descriptor List0 First Descriptor Upper Address */
-#define BCHP_PCIE_0_DMA_RX_FIRST_DESC_L_ADDR_LIST1 0x0047443c /* Rx Descriptor List1 First Descriptor Lower Address */
-#define BCHP_PCIE_0_DMA_RX_FIRST_DESC_U_ADDR_LIST1 0x00474440 /* Rx Descriptor List1 First Descriptor Upper Address */
-#define BCHP_PCIE_0_DMA_RX_SW_DESC_LIST_CTRL_STS 0x00474444 /* Rx Software Descriptor List Control and Status */
-#define BCHP_PCIE_0_DMA_RX_WAKE_CTRL 0x00474448 /* Rx DMA Wake Control */
-#define BCHP_PCIE_0_DMA_RX_ERROR_STATUS 0x0047444c /* Rx Engine Error Status */
-#define BCHP_PCIE_0_DMA_RX_LIST0_CUR_DESC_L_ADDR 0x00474450 /* Rx List0 Current Descriptor Lower Address */
-#define BCHP_PCIE_0_DMA_RX_LIST0_CUR_DESC_U_ADDR 0x00474454 /* Rx List0 Current Descriptor Upper Address */
-#define BCHP_PCIE_0_DMA_RX_LIST0_CUR_BYTE_CNT 0x00474458 /* Rx List0 Current Descriptor Byte Count */
-#define BCHP_PCIE_0_DMA_RX_LIST1_CUR_DESC_L_ADDR 0x0047445c /* Rx List1 Current Descriptor Lower address */
-#define BCHP_PCIE_0_DMA_RX_LIST1_CUR_DESC_U_ADDR 0x00474460 /* Rx List1 Current Descriptor Upper address */
-#define BCHP_PCIE_0_DMA_RX_LIST1_CUR_BYTE_CNT 0x00474464 /* Rx List1 Current Descriptor Byte Count */
-#define BCHP_PCIE_0_DMA_DMA_DEBUG_OPTIONS_REG 0x00474468 /* DMA Debug Options Register */
-#define BCHP_PCIE_0_DMA_READ_CHANNEL_ERROR_STATUS 0x0047446c /* Read Channel Error Status */
-
-/***************************************************************************
- *TX_FIRST_DESC_L_ADDR_LIST0 - Tx Descriptor List0 First Descriptor lower Address
- ***************************************************************************/
-/* PCIE_0_DMA :: TX_FIRST_DESC_L_ADDR_LIST0 :: DESC_ADDR [31:05] */
-#define BCHP_PCIE_0_DMA_TX_FIRST_DESC_L_ADDR_LIST0_DESC_ADDR_MASK 0xffffffe0
-#define BCHP_PCIE_0_DMA_TX_FIRST_DESC_L_ADDR_LIST0_DESC_ADDR_SHIFT 5
-#define BCHP_PCIE_0_DMA_TX_FIRST_DESC_L_ADDR_LIST0_DESC_ADDR_DEFAULT 0x00000000
-
-/* PCIE_0_DMA :: TX_FIRST_DESC_L_ADDR_LIST0 :: reserved0 [04:01] */
-#define BCHP_PCIE_0_DMA_TX_FIRST_DESC_L_ADDR_LIST0_reserved0_MASK 0x0000001e
-#define BCHP_PCIE_0_DMA_TX_FIRST_DESC_L_ADDR_LIST0_reserved0_SHIFT 1
-
-/* PCIE_0_DMA :: TX_FIRST_DESC_L_ADDR_LIST0 :: TX_DESC_LIST0_VALID [00:00] */
-#define BCHP_PCIE_0_DMA_TX_FIRST_DESC_L_ADDR_LIST0_TX_DESC_LIST0_VALID_MASK 0x00000001
-#define BCHP_PCIE_0_DMA_TX_FIRST_DESC_L_ADDR_LIST0_TX_DESC_LIST0_VALID_SHIFT 0
-#define BCHP_PCIE_0_DMA_TX_FIRST_DESC_L_ADDR_LIST0_TX_DESC_LIST0_VALID_DEFAULT 0x00000000
-
-/***************************************************************************
- *TX_FIRST_DESC_U_ADDR_LIST0 - Tx Descriptor List0 First Descriptor Upper Address
- ***************************************************************************/
-/* PCIE_0_DMA :: TX_FIRST_DESC_U_ADDR_LIST0 :: DESC_ADDR [31:00] */
-#define BCHP_PCIE_0_DMA_TX_FIRST_DESC_U_ADDR_LIST0_DESC_ADDR_MASK 0xffffffff
-#define BCHP_PCIE_0_DMA_TX_FIRST_DESC_U_ADDR_LIST0_DESC_ADDR_SHIFT 0
-#define BCHP_PCIE_0_DMA_TX_FIRST_DESC_U_ADDR_LIST0_DESC_ADDR_DEFAULT 0x00000000
-
-/***************************************************************************
- *TX_FIRST_DESC_L_ADDR_LIST1 - Tx Descriptor List1 First Descriptor Lower Address
- ***************************************************************************/
-/* PCIE_0_DMA :: TX_FIRST_DESC_L_ADDR_LIST1 :: DESC_ADDR [31:05] */
-#define BCHP_PCIE_0_DMA_TX_FIRST_DESC_L_ADDR_LIST1_DESC_ADDR_MASK 0xffffffe0
-#define BCHP_PCIE_0_DMA_TX_FIRST_DESC_L_ADDR_LIST1_DESC_ADDR_SHIFT 5
-#define BCHP_PCIE_0_DMA_TX_FIRST_DESC_L_ADDR_LIST1_DESC_ADDR_DEFAULT 0x00000000
-
-/* PCIE_0_DMA :: TX_FIRST_DESC_L_ADDR_LIST1 :: reserved0 [04:01] */
-#define BCHP_PCIE_0_DMA_TX_FIRST_DESC_L_ADDR_LIST1_reserved0_MASK 0x0000001e
-#define BCHP_PCIE_0_DMA_TX_FIRST_DESC_L_ADDR_LIST1_reserved0_SHIFT 1
-
-/* PCIE_0_DMA :: TX_FIRST_DESC_L_ADDR_LIST1 :: TX_DESC_LIST1_VALID [00:00] */
-#define BCHP_PCIE_0_DMA_TX_FIRST_DESC_L_ADDR_LIST1_TX_DESC_LIST1_VALID_MASK 0x00000001
-#define BCHP_PCIE_0_DMA_TX_FIRST_DESC_L_ADDR_LIST1_TX_DESC_LIST1_VALID_SHIFT 0
-#define BCHP_PCIE_0_DMA_TX_FIRST_DESC_L_ADDR_LIST1_TX_DESC_LIST1_VALID_DEFAULT 0x00000000
-
-/***************************************************************************
- *TX_FIRST_DESC_U_ADDR_LIST1 - Tx Descriptor List1 First Descriptor Upper Address
- ***************************************************************************/
-/* PCIE_0_DMA :: TX_FIRST_DESC_U_ADDR_LIST1 :: DESC_ADDR [31:00] */
-#define BCHP_PCIE_0_DMA_TX_FIRST_DESC_U_ADDR_LIST1_DESC_ADDR_MASK 0xffffffff
-#define BCHP_PCIE_0_DMA_TX_FIRST_DESC_U_ADDR_LIST1_DESC_ADDR_SHIFT 0
-#define BCHP_PCIE_0_DMA_TX_FIRST_DESC_U_ADDR_LIST1_DESC_ADDR_DEFAULT 0x00000000
-
-/***************************************************************************
- *TX_SW_DESC_LIST_CTRL_STS - Tx Software Descriptor List Control and Status
- ***************************************************************************/
-/* PCIE_0_DMA :: TX_SW_DESC_LIST_CTRL_STS :: reserved0 [31:20] */
-#define BCHP_PCIE_0_DMA_TX_SW_DESC_LIST_CTRL_STS_reserved0_MASK 0xfff00000
-#define BCHP_PCIE_0_DMA_TX_SW_DESC_LIST_CTRL_STS_reserved0_SHIFT 20
-
-/* PCIE_0_DMA :: TX_SW_DESC_LIST_CTRL_STS :: BURST_SIZE_OVERRIDE [19:19] */
-#define BCHP_PCIE_0_DMA_TX_SW_DESC_LIST_CTRL_STS_BURST_SIZE_OVERRIDE_MASK 0x00080000
-#define BCHP_PCIE_0_DMA_TX_SW_DESC_LIST_CTRL_STS_BURST_SIZE_OVERRIDE_SHIFT 19
-#define BCHP_PCIE_0_DMA_TX_SW_DESC_LIST_CTRL_STS_BURST_SIZE_OVERRIDE_DEFAULT 0x00000000
-
-/* PCIE_0_DMA :: TX_SW_DESC_LIST_CTRL_STS :: BURST_SIZE_OVERRIDE_VALUE [18:16] */
-#define BCHP_PCIE_0_DMA_TX_SW_DESC_LIST_CTRL_STS_BURST_SIZE_OVERRIDE_VALUE_MASK 0x00070000
-#define BCHP_PCIE_0_DMA_TX_SW_DESC_LIST_CTRL_STS_BURST_SIZE_OVERRIDE_VALUE_SHIFT 16
-#define BCHP_PCIE_0_DMA_TX_SW_DESC_LIST_CTRL_STS_BURST_SIZE_OVERRIDE_VALUE_DEFAULT 0x00000000
-
-/* PCIE_0_DMA :: TX_SW_DESC_LIST_CTRL_STS :: reserved1 [15:14] */
-#define BCHP_PCIE_0_DMA_TX_SW_DESC_LIST_CTRL_STS_reserved1_MASK 0x0000c000
-#define BCHP_PCIE_0_DMA_TX_SW_DESC_LIST_CTRL_STS_reserved1_SHIFT 14
-
-/* PCIE_0_DMA :: TX_SW_DESC_LIST_CTRL_STS :: DESC_ENDIAN_MODE [13:12] */
-#define BCHP_PCIE_0_DMA_TX_SW_DESC_LIST_CTRL_STS_DESC_ENDIAN_MODE_MASK 0x00003000
-#define BCHP_PCIE_0_DMA_TX_SW_DESC_LIST_CTRL_STS_DESC_ENDIAN_MODE_SHIFT 12
-#define BCHP_PCIE_0_DMA_TX_SW_DESC_LIST_CTRL_STS_DESC_ENDIAN_MODE_DEFAULT 0x00000000
-
-/* PCIE_0_DMA :: TX_SW_DESC_LIST_CTRL_STS :: reserved2 [11:10] */
-#define BCHP_PCIE_0_DMA_TX_SW_DESC_LIST_CTRL_STS_reserved2_MASK 0x00000c00
-#define BCHP_PCIE_0_DMA_TX_SW_DESC_LIST_CTRL_STS_reserved2_SHIFT 10
-
-/* PCIE_0_DMA :: TX_SW_DESC_LIST_CTRL_STS :: LOCAL_DESC [09:09] */
-#define BCHP_PCIE_0_DMA_TX_SW_DESC_LIST_CTRL_STS_LOCAL_DESC_MASK 0x00000200
-#define BCHP_PCIE_0_DMA_TX_SW_DESC_LIST_CTRL_STS_LOCAL_DESC_SHIFT 9
-#define BCHP_PCIE_0_DMA_TX_SW_DESC_LIST_CTRL_STS_LOCAL_DESC_DEFAULT 0x00000000
-
-/* PCIE_0_DMA :: TX_SW_DESC_LIST_CTRL_STS :: DMA_MODE [08:08] */
-#define BCHP_PCIE_0_DMA_TX_SW_DESC_LIST_CTRL_STS_DMA_MODE_MASK 0x00000100
-#define BCHP_PCIE_0_DMA_TX_SW_DESC_LIST_CTRL_STS_DMA_MODE_SHIFT 8
-#define BCHP_PCIE_0_DMA_TX_SW_DESC_LIST_CTRL_STS_DMA_MODE_DEFAULT 0x00000000
-
-/* PCIE_0_DMA :: TX_SW_DESC_LIST_CTRL_STS :: reserved3 [07:06] */
-#define BCHP_PCIE_0_DMA_TX_SW_DESC_LIST_CTRL_STS_reserved3_MASK 0x000000c0
-#define BCHP_PCIE_0_DMA_TX_SW_DESC_LIST_CTRL_STS_reserved3_SHIFT 6
-
-/* PCIE_0_DMA :: TX_SW_DESC_LIST_CTRL_STS :: DMA_STATUS [05:04] */
-#define BCHP_PCIE_0_DMA_TX_SW_DESC_LIST_CTRL_STS_DMA_STATUS_MASK 0x00000030
-#define BCHP_PCIE_0_DMA_TX_SW_DESC_LIST_CTRL_STS_DMA_STATUS_SHIFT 4
-#define BCHP_PCIE_0_DMA_TX_SW_DESC_LIST_CTRL_STS_DMA_STATUS_DEFAULT 0x00000000
-
-/* PCIE_0_DMA :: TX_SW_DESC_LIST_CTRL_STS :: DMA_DATA_SERV_PTR [03:03] */
-#define BCHP_PCIE_0_DMA_TX_SW_DESC_LIST_CTRL_STS_DMA_DATA_SERV_PTR_MASK 0x00000008
-#define BCHP_PCIE_0_DMA_TX_SW_DESC_LIST_CTRL_STS_DMA_DATA_SERV_PTR_SHIFT 3
-#define BCHP_PCIE_0_DMA_TX_SW_DESC_LIST_CTRL_STS_DMA_DATA_SERV_PTR_DEFAULT 0x00000000
-
-/* PCIE_0_DMA :: TX_SW_DESC_LIST_CTRL_STS :: DESC_SERV_PTR [02:02] */
-#define BCHP_PCIE_0_DMA_TX_SW_DESC_LIST_CTRL_STS_DESC_SERV_PTR_MASK 0x00000004
-#define BCHP_PCIE_0_DMA_TX_SW_DESC_LIST_CTRL_STS_DESC_SERV_PTR_SHIFT 2
-#define BCHP_PCIE_0_DMA_TX_SW_DESC_LIST_CTRL_STS_DESC_SERV_PTR_DEFAULT 0x00000000
-
-/* PCIE_0_DMA :: TX_SW_DESC_LIST_CTRL_STS :: reserved4 [01:01] */
-#define BCHP_PCIE_0_DMA_TX_SW_DESC_LIST_CTRL_STS_reserved4_MASK 0x00000002
-#define BCHP_PCIE_0_DMA_TX_SW_DESC_LIST_CTRL_STS_reserved4_SHIFT 1
-
-/* PCIE_0_DMA :: TX_SW_DESC_LIST_CTRL_STS :: TX_DMA_RUN_STOP [00:00] */
-#define BCHP_PCIE_0_DMA_TX_SW_DESC_LIST_CTRL_STS_TX_DMA_RUN_STOP_MASK 0x00000001
-#define BCHP_PCIE_0_DMA_TX_SW_DESC_LIST_CTRL_STS_TX_DMA_RUN_STOP_SHIFT 0
-#define BCHP_PCIE_0_DMA_TX_SW_DESC_LIST_CTRL_STS_TX_DMA_RUN_STOP_DEFAULT 0x00000000
-
-/***************************************************************************
- *TX_WAKE_CTRL - Tx Wake Control
- ***************************************************************************/
-/* PCIE_0_DMA :: TX_WAKE_CTRL :: reserved0 [31:02] */
-#define BCHP_PCIE_0_DMA_TX_WAKE_CTRL_reserved0_MASK 0xfffffffc
-#define BCHP_PCIE_0_DMA_TX_WAKE_CTRL_reserved0_SHIFT 2
-
-/* PCIE_0_DMA :: TX_WAKE_CTRL :: WAKE_MODE [01:01] */
-#define BCHP_PCIE_0_DMA_TX_WAKE_CTRL_WAKE_MODE_MASK 0x00000002
-#define BCHP_PCIE_0_DMA_TX_WAKE_CTRL_WAKE_MODE_SHIFT 1
-#define BCHP_PCIE_0_DMA_TX_WAKE_CTRL_WAKE_MODE_DEFAULT 0x00000000
-
-/* PCIE_0_DMA :: TX_WAKE_CTRL :: WAKE [00:00] */
-#define BCHP_PCIE_0_DMA_TX_WAKE_CTRL_WAKE_MASK 0x00000001
-#define BCHP_PCIE_0_DMA_TX_WAKE_CTRL_WAKE_SHIFT 0
-#define BCHP_PCIE_0_DMA_TX_WAKE_CTRL_WAKE_DEFAULT 0x00000000
-
-/***************************************************************************
- *TX_ERROR_STATUS - Tx Engine Error Status
- ***************************************************************************/
-/* PCIE_0_DMA :: TX_ERROR_STATUS :: reserved0 [31:10] */
-#define BCHP_PCIE_0_DMA_TX_ERROR_STATUS_reserved0_MASK 0xfffffc00
-#define BCHP_PCIE_0_DMA_TX_ERROR_STATUS_reserved0_SHIFT 10
-
-/* PCIE_0_DMA :: TX_ERROR_STATUS :: TX_L1_DESC_TX_ABORT_ERRORS [09:09] */
-#define BCHP_PCIE_0_DMA_TX_ERROR_STATUS_TX_L1_DESC_TX_ABORT_ERRORS_MASK 0x00000200
-#define BCHP_PCIE_0_DMA_TX_ERROR_STATUS_TX_L1_DESC_TX_ABORT_ERRORS_SHIFT 9
-#define BCHP_PCIE_0_DMA_TX_ERROR_STATUS_TX_L1_DESC_TX_ABORT_ERRORS_DEFAULT 0x00000000
-
-/* PCIE_0_DMA :: TX_ERROR_STATUS :: reserved1 [08:08] */
-#define BCHP_PCIE_0_DMA_TX_ERROR_STATUS_reserved1_MASK 0x00000100
-#define BCHP_PCIE_0_DMA_TX_ERROR_STATUS_reserved1_SHIFT 8
-
-/* PCIE_0_DMA :: TX_ERROR_STATUS :: TX_L0_DESC_TX_ABORT_ERRORS [07:07] */
-#define BCHP_PCIE_0_DMA_TX_ERROR_STATUS_TX_L0_DESC_TX_ABORT_ERRORS_MASK 0x00000080
-#define BCHP_PCIE_0_DMA_TX_ERROR_STATUS_TX_L0_DESC_TX_ABORT_ERRORS_SHIFT 7
-#define BCHP_PCIE_0_DMA_TX_ERROR_STATUS_TX_L0_DESC_TX_ABORT_ERRORS_DEFAULT 0x00000000
-
-/* PCIE_0_DMA :: TX_ERROR_STATUS :: reserved2 [06:06] */
-#define BCHP_PCIE_0_DMA_TX_ERROR_STATUS_reserved2_MASK 0x00000040
-#define BCHP_PCIE_0_DMA_TX_ERROR_STATUS_reserved2_SHIFT 6
-
-/* PCIE_0_DMA :: TX_ERROR_STATUS :: TX_L1_DATA_TX_ABORT_ERRORS [05:05] */
-#define BCHP_PCIE_0_DMA_TX_ERROR_STATUS_TX_L1_DATA_TX_ABORT_ERRORS_MASK 0x00000020
-#define BCHP_PCIE_0_DMA_TX_ERROR_STATUS_TX_L1_DATA_TX_ABORT_ERRORS_SHIFT 5
-#define BCHP_PCIE_0_DMA_TX_ERROR_STATUS_TX_L1_DATA_TX_ABORT_ERRORS_DEFAULT 0x00000000
-
-/* PCIE_0_DMA :: TX_ERROR_STATUS :: TX_L1_REPIN_ERRORS [04:04] */
-#define BCHP_PCIE_0_DMA_TX_ERROR_STATUS_TX_L1_REPIN_ERRORS_MASK 0x00000010
-#define BCHP_PCIE_0_DMA_TX_ERROR_STATUS_TX_L1_REPIN_ERRORS_SHIFT 4
-#define BCHP_PCIE_0_DMA_TX_ERROR_STATUS_TX_L1_REPIN_ERRORS_DEFAULT 0x00000000
-
-/* PCIE_0_DMA :: TX_ERROR_STATUS :: reserved3 [03:03] */
-#define BCHP_PCIE_0_DMA_TX_ERROR_STATUS_reserved3_MASK 0x00000008
-#define BCHP_PCIE_0_DMA_TX_ERROR_STATUS_reserved3_SHIFT 3
-
-/* PCIE_0_DMA :: TX_ERROR_STATUS :: TX_L0_DATA_TX_ABORT_ERRORS [02:02] */
-#define BCHP_PCIE_0_DMA_TX_ERROR_STATUS_TX_L0_DATA_TX_ABORT_ERRORS_MASK 0x00000004
-#define BCHP_PCIE_0_DMA_TX_ERROR_STATUS_TX_L0_DATA_TX_ABORT_ERRORS_SHIFT 2
-#define BCHP_PCIE_0_DMA_TX_ERROR_STATUS_TX_L0_DATA_TX_ABORT_ERRORS_DEFAULT 0x00000000
-
-/* PCIE_0_DMA :: TX_ERROR_STATUS :: TX_L0_REPIN_ERRORS [01:01] */
-#define BCHP_PCIE_0_DMA_TX_ERROR_STATUS_TX_L0_REPIN_ERRORS_MASK 0x00000002
-#define BCHP_PCIE_0_DMA_TX_ERROR_STATUS_TX_L0_REPIN_ERRORS_SHIFT 1
-#define BCHP_PCIE_0_DMA_TX_ERROR_STATUS_TX_L0_REPIN_ERRORS_DEFAULT 0x00000000
-
-/* PCIE_0_DMA :: TX_ERROR_STATUS :: reserved4 [00:00] */
-#define BCHP_PCIE_0_DMA_TX_ERROR_STATUS_reserved4_MASK 0x00000001
-#define BCHP_PCIE_0_DMA_TX_ERROR_STATUS_reserved4_SHIFT 0
-
-/***************************************************************************
- *TX_LIST0_CUR_DESC_L_ADDR - Tx List0 Current Descriptor Lower Address
- ***************************************************************************/
-/* PCIE_0_DMA :: TX_LIST0_CUR_DESC_L_ADDR :: TX_L0_CUR_DESC_L_ADDR [31:05] */
-#define BCHP_PCIE_0_DMA_TX_LIST0_CUR_DESC_L_ADDR_TX_L0_CUR_DESC_L_ADDR_MASK 0xffffffe0
-#define BCHP_PCIE_0_DMA_TX_LIST0_CUR_DESC_L_ADDR_TX_L0_CUR_DESC_L_ADDR_SHIFT 5
-#define BCHP_PCIE_0_DMA_TX_LIST0_CUR_DESC_L_ADDR_TX_L0_CUR_DESC_L_ADDR_DEFAULT 0x00000000
-
-/* PCIE_0_DMA :: TX_LIST0_CUR_DESC_L_ADDR :: reserved0 [04:04] */
-#define BCHP_PCIE_0_DMA_TX_LIST0_CUR_DESC_L_ADDR_reserved0_MASK 0x00000010
-#define BCHP_PCIE_0_DMA_TX_LIST0_CUR_DESC_L_ADDR_reserved0_SHIFT 4
-
-/* PCIE_0_DMA :: TX_LIST0_CUR_DESC_L_ADDR :: TX_L0_CUR_LIST [03:03] */
-#define BCHP_PCIE_0_DMA_TX_LIST0_CUR_DESC_L_ADDR_TX_L0_CUR_LIST_MASK 0x00000008
-#define BCHP_PCIE_0_DMA_TX_LIST0_CUR_DESC_L_ADDR_TX_L0_CUR_LIST_SHIFT 3
-#define BCHP_PCIE_0_DMA_TX_LIST0_CUR_DESC_L_ADDR_TX_L0_CUR_LIST_DEFAULT 0x00000000
-
-/* PCIE_0_DMA :: TX_LIST0_CUR_DESC_L_ADDR :: TX_L0_CUR_IN_PROGRESS [02:02] */
-#define BCHP_PCIE_0_DMA_TX_LIST0_CUR_DESC_L_ADDR_TX_L0_CUR_IN_PROGRESS_MASK 0x00000004
-#define BCHP_PCIE_0_DMA_TX_LIST0_CUR_DESC_L_ADDR_TX_L0_CUR_IN_PROGRESS_SHIFT 2
-#define BCHP_PCIE_0_DMA_TX_LIST0_CUR_DESC_L_ADDR_TX_L0_CUR_IN_PROGRESS_DEFAULT 0x00000000
-
-/* PCIE_0_DMA :: TX_LIST0_CUR_DESC_L_ADDR :: TX_L0_CUR_STATUS [01:00] */
-#define BCHP_PCIE_0_DMA_TX_LIST0_CUR_DESC_L_ADDR_TX_L0_CUR_STATUS_MASK 0x00000003
-#define BCHP_PCIE_0_DMA_TX_LIST0_CUR_DESC_L_ADDR_TX_L0_CUR_STATUS_SHIFT 0
-#define BCHP_PCIE_0_DMA_TX_LIST0_CUR_DESC_L_ADDR_TX_L0_CUR_STATUS_DEFAULT 0x00000000
-
-/***************************************************************************
- *TX_LIST0_CUR_DESC_U_ADDR - Tx List0 Current Descriptor Upper Address
- ***************************************************************************/
-/* PCIE_0_DMA :: TX_LIST0_CUR_DESC_U_ADDR :: TX_L0_CUR_DESC_U_ADDR [31:00] */
-#define BCHP_PCIE_0_DMA_TX_LIST0_CUR_DESC_U_ADDR_TX_L0_CUR_DESC_U_ADDR_MASK 0xffffffff
-#define BCHP_PCIE_0_DMA_TX_LIST0_CUR_DESC_U_ADDR_TX_L0_CUR_DESC_U_ADDR_SHIFT 0
-#define BCHP_PCIE_0_DMA_TX_LIST0_CUR_DESC_U_ADDR_TX_L0_CUR_DESC_U_ADDR_DEFAULT 0x00000000
-
-/***************************************************************************
- *TX_LIST0_CUR_BYTE_CNT - Tx List0 Current Descriptor Byte Count
- ***************************************************************************/
-/* PCIE_0_DMA :: TX_LIST0_CUR_BYTE_CNT :: TX_L0_CUR_BYTE_CNT [31:00] */
-#define BCHP_PCIE_0_DMA_TX_LIST0_CUR_BYTE_CNT_TX_L0_CUR_BYTE_CNT_MASK 0xffffffff
-#define BCHP_PCIE_0_DMA_TX_LIST0_CUR_BYTE_CNT_TX_L0_CUR_BYTE_CNT_SHIFT 0
-#define BCHP_PCIE_0_DMA_TX_LIST0_CUR_BYTE_CNT_TX_L0_CUR_BYTE_CNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *TX_LIST1_CUR_DESC_L_ADDR - Tx List1 Current Descriptor Lower Address
- ***************************************************************************/
-/* PCIE_0_DMA :: TX_LIST1_CUR_DESC_L_ADDR :: TX_L1_CUR_DESC_L_ADDR [31:05] */
-#define BCHP_PCIE_0_DMA_TX_LIST1_CUR_DESC_L_ADDR_TX_L1_CUR_DESC_L_ADDR_MASK 0xffffffe0
-#define BCHP_PCIE_0_DMA_TX_LIST1_CUR_DESC_L_ADDR_TX_L1_CUR_DESC_L_ADDR_SHIFT 5
-#define BCHP_PCIE_0_DMA_TX_LIST1_CUR_DESC_L_ADDR_TX_L1_CUR_DESC_L_ADDR_DEFAULT 0x00000000
-
-/* PCIE_0_DMA :: TX_LIST1_CUR_DESC_L_ADDR :: reserved0 [04:04] */
-#define BCHP_PCIE_0_DMA_TX_LIST1_CUR_DESC_L_ADDR_reserved0_MASK 0x00000010
-#define BCHP_PCIE_0_DMA_TX_LIST1_CUR_DESC_L_ADDR_reserved0_SHIFT 4
-
-/* PCIE_0_DMA :: TX_LIST1_CUR_DESC_L_ADDR :: TX_L1_CUR_LIST [03:03] */
-#define BCHP_PCIE_0_DMA_TX_LIST1_CUR_DESC_L_ADDR_TX_L1_CUR_LIST_MASK 0x00000008
-#define BCHP_PCIE_0_DMA_TX_LIST1_CUR_DESC_L_ADDR_TX_L1_CUR_LIST_SHIFT 3
-#define BCHP_PCIE_0_DMA_TX_LIST1_CUR_DESC_L_ADDR_TX_L1_CUR_LIST_DEFAULT 0x00000000
-
-/* PCIE_0_DMA :: TX_LIST1_CUR_DESC_L_ADDR :: TX_L1_CUR_IN_PROGRESS [02:02] */
-#define BCHP_PCIE_0_DMA_TX_LIST1_CUR_DESC_L_ADDR_TX_L1_CUR_IN_PROGRESS_MASK 0x00000004
-#define BCHP_PCIE_0_DMA_TX_LIST1_CUR_DESC_L_ADDR_TX_L1_CUR_IN_PROGRESS_SHIFT 2
-#define BCHP_PCIE_0_DMA_TX_LIST1_CUR_DESC_L_ADDR_TX_L1_CUR_IN_PROGRESS_DEFAULT 0x00000000
-
-/* PCIE_0_DMA :: TX_LIST1_CUR_DESC_L_ADDR :: TX_L1_CUR_STATUS [01:00] */
-#define BCHP_PCIE_0_DMA_TX_LIST1_CUR_DESC_L_ADDR_TX_L1_CUR_STATUS_MASK 0x00000003
-#define BCHP_PCIE_0_DMA_TX_LIST1_CUR_DESC_L_ADDR_TX_L1_CUR_STATUS_SHIFT 0
-#define BCHP_PCIE_0_DMA_TX_LIST1_CUR_DESC_L_ADDR_TX_L1_CUR_STATUS_DEFAULT 0x00000000
-
-/***************************************************************************
- *TX_LIST1_CUR_DESC_U_ADDR - Tx List1 Current Descriptor Upper Address
- ***************************************************************************/
-/* PCIE_0_DMA :: TX_LIST1_CUR_DESC_U_ADDR :: TX_L1_CUR_DESC_U_ADDR [31:00] */
-#define BCHP_PCIE_0_DMA_TX_LIST1_CUR_DESC_U_ADDR_TX_L1_CUR_DESC_U_ADDR_MASK 0xffffffff
-#define BCHP_PCIE_0_DMA_TX_LIST1_CUR_DESC_U_ADDR_TX_L1_CUR_DESC_U_ADDR_SHIFT 0
-#define BCHP_PCIE_0_DMA_TX_LIST1_CUR_DESC_U_ADDR_TX_L1_CUR_DESC_U_ADDR_DEFAULT 0x00000000
-
-/***************************************************************************
- *TX_LIST1_CUR_BYTE_CNT - Tx List1 Current Descriptor Byte Count
- ***************************************************************************/
-/* PCIE_0_DMA :: TX_LIST1_CUR_BYTE_CNT :: TX_L1_CUR_BYTE_CNT [31:00] */
-#define BCHP_PCIE_0_DMA_TX_LIST1_CUR_BYTE_CNT_TX_L1_CUR_BYTE_CNT_MASK 0xffffffff
-#define BCHP_PCIE_0_DMA_TX_LIST1_CUR_BYTE_CNT_TX_L1_CUR_BYTE_CNT_SHIFT 0
-#define BCHP_PCIE_0_DMA_TX_LIST1_CUR_BYTE_CNT_TX_L1_CUR_BYTE_CNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *RX_FIRST_DESC_L_ADDR_LIST0 - Rx Descriptor List0 First Descriptor Lower Address
- ***************************************************************************/
-/* PCIE_0_DMA :: RX_FIRST_DESC_L_ADDR_LIST0 :: DESC_ADDR [31:05] */
-#define BCHP_PCIE_0_DMA_RX_FIRST_DESC_L_ADDR_LIST0_DESC_ADDR_MASK 0xffffffe0
-#define BCHP_PCIE_0_DMA_RX_FIRST_DESC_L_ADDR_LIST0_DESC_ADDR_SHIFT 5
-#define BCHP_PCIE_0_DMA_RX_FIRST_DESC_L_ADDR_LIST0_DESC_ADDR_DEFAULT 0x00000000
-
-/* PCIE_0_DMA :: RX_FIRST_DESC_L_ADDR_LIST0 :: reserved0 [04:01] */
-#define BCHP_PCIE_0_DMA_RX_FIRST_DESC_L_ADDR_LIST0_reserved0_MASK 0x0000001e
-#define BCHP_PCIE_0_DMA_RX_FIRST_DESC_L_ADDR_LIST0_reserved0_SHIFT 1
-
-/* PCIE_0_DMA :: RX_FIRST_DESC_L_ADDR_LIST0 :: RX_DESC_LIST0_VALID [00:00] */
-#define BCHP_PCIE_0_DMA_RX_FIRST_DESC_L_ADDR_LIST0_RX_DESC_LIST0_VALID_MASK 0x00000001
-#define BCHP_PCIE_0_DMA_RX_FIRST_DESC_L_ADDR_LIST0_RX_DESC_LIST0_VALID_SHIFT 0
-#define BCHP_PCIE_0_DMA_RX_FIRST_DESC_L_ADDR_LIST0_RX_DESC_LIST0_VALID_DEFAULT 0x00000000
-
-/***************************************************************************
- *RX_FIRST_DESC_U_ADDR_LIST0 - Rx Descriptor List0 First Descriptor Upper Address
- ***************************************************************************/
-/* PCIE_0_DMA :: RX_FIRST_DESC_U_ADDR_LIST0 :: DESC_ADDR [31:00] */
-#define BCHP_PCIE_0_DMA_RX_FIRST_DESC_U_ADDR_LIST0_DESC_ADDR_MASK 0xffffffff
-#define BCHP_PCIE_0_DMA_RX_FIRST_DESC_U_ADDR_LIST0_DESC_ADDR_SHIFT 0
-#define BCHP_PCIE_0_DMA_RX_FIRST_DESC_U_ADDR_LIST0_DESC_ADDR_DEFAULT 0x00000000
-
-/***************************************************************************
- *RX_FIRST_DESC_L_ADDR_LIST1 - Rx Descriptor List1 First Descriptor Lower Address
- ***************************************************************************/
-/* PCIE_0_DMA :: RX_FIRST_DESC_L_ADDR_LIST1 :: DESC_ADDR [31:05] */
-#define BCHP_PCIE_0_DMA_RX_FIRST_DESC_L_ADDR_LIST1_DESC_ADDR_MASK 0xffffffe0
-#define BCHP_PCIE_0_DMA_RX_FIRST_DESC_L_ADDR_LIST1_DESC_ADDR_SHIFT 5
-#define BCHP_PCIE_0_DMA_RX_FIRST_DESC_L_ADDR_LIST1_DESC_ADDR_DEFAULT 0x00000000
-
-/* PCIE_0_DMA :: RX_FIRST_DESC_L_ADDR_LIST1 :: reserved0 [04:01] */
-#define BCHP_PCIE_0_DMA_RX_FIRST_DESC_L_ADDR_LIST1_reserved0_MASK 0x0000001e
-#define BCHP_PCIE_0_DMA_RX_FIRST_DESC_L_ADDR_LIST1_reserved0_SHIFT 1
-
-/* PCIE_0_DMA :: RX_FIRST_DESC_L_ADDR_LIST1 :: RX_DESC_LIST1_VALID [00:00] */
-#define BCHP_PCIE_0_DMA_RX_FIRST_DESC_L_ADDR_LIST1_RX_DESC_LIST1_VALID_MASK 0x00000001
-#define BCHP_PCIE_0_DMA_RX_FIRST_DESC_L_ADDR_LIST1_RX_DESC_LIST1_VALID_SHIFT 0
-#define BCHP_PCIE_0_DMA_RX_FIRST_DESC_L_ADDR_LIST1_RX_DESC_LIST1_VALID_DEFAULT 0x00000000
-
-/***************************************************************************
- *RX_FIRST_DESC_U_ADDR_LIST1 - Rx Descriptor List1 First Descriptor Upper Address
- ***************************************************************************/
-/* PCIE_0_DMA :: RX_FIRST_DESC_U_ADDR_LIST1 :: DESC_ADDR [31:00] */
-#define BCHP_PCIE_0_DMA_RX_FIRST_DESC_U_ADDR_LIST1_DESC_ADDR_MASK 0xffffffff
-#define BCHP_PCIE_0_DMA_RX_FIRST_DESC_U_ADDR_LIST1_DESC_ADDR_SHIFT 0
-#define BCHP_PCIE_0_DMA_RX_FIRST_DESC_U_ADDR_LIST1_DESC_ADDR_DEFAULT 0x00000000
-
-/***************************************************************************
- *RX_SW_DESC_LIST_CTRL_STS - Rx Software Descriptor List Control and Status
- ***************************************************************************/
-/* PCIE_0_DMA :: RX_SW_DESC_LIST_CTRL_STS :: reserved0 [31:20] */
-#define BCHP_PCIE_0_DMA_RX_SW_DESC_LIST_CTRL_STS_reserved0_MASK 0xfff00000
-#define BCHP_PCIE_0_DMA_RX_SW_DESC_LIST_CTRL_STS_reserved0_SHIFT 20
-
-/* PCIE_0_DMA :: RX_SW_DESC_LIST_CTRL_STS :: BURST_SIZE_OVERRIDE [19:19] */
-#define BCHP_PCIE_0_DMA_RX_SW_DESC_LIST_CTRL_STS_BURST_SIZE_OVERRIDE_MASK 0x00080000
-#define BCHP_PCIE_0_DMA_RX_SW_DESC_LIST_CTRL_STS_BURST_SIZE_OVERRIDE_SHIFT 19
-#define BCHP_PCIE_0_DMA_RX_SW_DESC_LIST_CTRL_STS_BURST_SIZE_OVERRIDE_DEFAULT 0x00000000
-
-/* PCIE_0_DMA :: RX_SW_DESC_LIST_CTRL_STS :: BURST_SIZE_OVERRIDE_VALUE [18:16] */
-#define BCHP_PCIE_0_DMA_RX_SW_DESC_LIST_CTRL_STS_BURST_SIZE_OVERRIDE_VALUE_MASK 0x00070000
-#define BCHP_PCIE_0_DMA_RX_SW_DESC_LIST_CTRL_STS_BURST_SIZE_OVERRIDE_VALUE_SHIFT 16
-#define BCHP_PCIE_0_DMA_RX_SW_DESC_LIST_CTRL_STS_BURST_SIZE_OVERRIDE_VALUE_DEFAULT 0x00000000
-
-/* PCIE_0_DMA :: RX_SW_DESC_LIST_CTRL_STS :: reserved1 [15:14] */
-#define BCHP_PCIE_0_DMA_RX_SW_DESC_LIST_CTRL_STS_reserved1_MASK 0x0000c000
-#define BCHP_PCIE_0_DMA_RX_SW_DESC_LIST_CTRL_STS_reserved1_SHIFT 14
-
-/* PCIE_0_DMA :: RX_SW_DESC_LIST_CTRL_STS :: DESC_ENDIAN_MODE [13:12] */
-#define BCHP_PCIE_0_DMA_RX_SW_DESC_LIST_CTRL_STS_DESC_ENDIAN_MODE_MASK 0x00003000
-#define BCHP_PCIE_0_DMA_RX_SW_DESC_LIST_CTRL_STS_DESC_ENDIAN_MODE_SHIFT 12
-#define BCHP_PCIE_0_DMA_RX_SW_DESC_LIST_CTRL_STS_DESC_ENDIAN_MODE_DEFAULT 0x00000000
-
-/* PCIE_0_DMA :: RX_SW_DESC_LIST_CTRL_STS :: reserved2 [11:10] */
-#define BCHP_PCIE_0_DMA_RX_SW_DESC_LIST_CTRL_STS_reserved2_MASK 0x00000c00
-#define BCHP_PCIE_0_DMA_RX_SW_DESC_LIST_CTRL_STS_reserved2_SHIFT 10
-
-/* PCIE_0_DMA :: RX_SW_DESC_LIST_CTRL_STS :: LOCAL_DESC [09:09] */
-#define BCHP_PCIE_0_DMA_RX_SW_DESC_LIST_CTRL_STS_LOCAL_DESC_MASK 0x00000200
-#define BCHP_PCIE_0_DMA_RX_SW_DESC_LIST_CTRL_STS_LOCAL_DESC_SHIFT 9
-#define BCHP_PCIE_0_DMA_RX_SW_DESC_LIST_CTRL_STS_LOCAL_DESC_DEFAULT 0x00000000
-
-/* PCIE_0_DMA :: RX_SW_DESC_LIST_CTRL_STS :: DMA_MODE [08:08] */
-#define BCHP_PCIE_0_DMA_RX_SW_DESC_LIST_CTRL_STS_DMA_MODE_MASK 0x00000100
-#define BCHP_PCIE_0_DMA_RX_SW_DESC_LIST_CTRL_STS_DMA_MODE_SHIFT 8
-#define BCHP_PCIE_0_DMA_RX_SW_DESC_LIST_CTRL_STS_DMA_MODE_DEFAULT 0x00000000
-
-/* PCIE_0_DMA :: RX_SW_DESC_LIST_CTRL_STS :: reserved3 [07:06] */
-#define BCHP_PCIE_0_DMA_RX_SW_DESC_LIST_CTRL_STS_reserved3_MASK 0x000000c0
-#define BCHP_PCIE_0_DMA_RX_SW_DESC_LIST_CTRL_STS_reserved3_SHIFT 6
-
-/* PCIE_0_DMA :: RX_SW_DESC_LIST_CTRL_STS :: DMA_STATUS [05:04] */
-#define BCHP_PCIE_0_DMA_RX_SW_DESC_LIST_CTRL_STS_DMA_STATUS_MASK 0x00000030
-#define BCHP_PCIE_0_DMA_RX_SW_DESC_LIST_CTRL_STS_DMA_STATUS_SHIFT 4
-#define BCHP_PCIE_0_DMA_RX_SW_DESC_LIST_CTRL_STS_DMA_STATUS_DEFAULT 0x00000000
-
-/* PCIE_0_DMA :: RX_SW_DESC_LIST_CTRL_STS :: DMA_DATA_SERV_PTR [03:03] */
-#define BCHP_PCIE_0_DMA_RX_SW_DESC_LIST_CTRL_STS_DMA_DATA_SERV_PTR_MASK 0x00000008
-#define BCHP_PCIE_0_DMA_RX_SW_DESC_LIST_CTRL_STS_DMA_DATA_SERV_PTR_SHIFT 3
-#define BCHP_PCIE_0_DMA_RX_SW_DESC_LIST_CTRL_STS_DMA_DATA_SERV_PTR_DEFAULT 0x00000000
-
-/* PCIE_0_DMA :: RX_SW_DESC_LIST_CTRL_STS :: DESC_SERV_PTR [02:02] */
-#define BCHP_PCIE_0_DMA_RX_SW_DESC_LIST_CTRL_STS_DESC_SERV_PTR_MASK 0x00000004
-#define BCHP_PCIE_0_DMA_RX_SW_DESC_LIST_CTRL_STS_DESC_SERV_PTR_SHIFT 2
-#define BCHP_PCIE_0_DMA_RX_SW_DESC_LIST_CTRL_STS_DESC_SERV_PTR_DEFAULT 0x00000000
-
-/* PCIE_0_DMA :: RX_SW_DESC_LIST_CTRL_STS :: reserved4 [01:01] */
-#define BCHP_PCIE_0_DMA_RX_SW_DESC_LIST_CTRL_STS_reserved4_MASK 0x00000002
-#define BCHP_PCIE_0_DMA_RX_SW_DESC_LIST_CTRL_STS_reserved4_SHIFT 1
-
-/* PCIE_0_DMA :: RX_SW_DESC_LIST_CTRL_STS :: RX_DMA_RUN_STOP [00:00] */
-#define BCHP_PCIE_0_DMA_RX_SW_DESC_LIST_CTRL_STS_RX_DMA_RUN_STOP_MASK 0x00000001
-#define BCHP_PCIE_0_DMA_RX_SW_DESC_LIST_CTRL_STS_RX_DMA_RUN_STOP_SHIFT 0
-#define BCHP_PCIE_0_DMA_RX_SW_DESC_LIST_CTRL_STS_RX_DMA_RUN_STOP_DEFAULT 0x00000000
-
-/***************************************************************************
- *RX_WAKE_CTRL - Rx DMA Wake Control
- ***************************************************************************/
-/* PCIE_0_DMA :: RX_WAKE_CTRL :: reserved0 [31:02] */
-#define BCHP_PCIE_0_DMA_RX_WAKE_CTRL_reserved0_MASK 0xfffffffc
-#define BCHP_PCIE_0_DMA_RX_WAKE_CTRL_reserved0_SHIFT 2
-
-/* PCIE_0_DMA :: RX_WAKE_CTRL :: WAKE_MODE [01:01] */
-#define BCHP_PCIE_0_DMA_RX_WAKE_CTRL_WAKE_MODE_MASK 0x00000002
-#define BCHP_PCIE_0_DMA_RX_WAKE_CTRL_WAKE_MODE_SHIFT 1
-#define BCHP_PCIE_0_DMA_RX_WAKE_CTRL_WAKE_MODE_DEFAULT 0x00000000
-
-/* PCIE_0_DMA :: RX_WAKE_CTRL :: WAKE [00:00] */
-#define BCHP_PCIE_0_DMA_RX_WAKE_CTRL_WAKE_MASK 0x00000001
-#define BCHP_PCIE_0_DMA_RX_WAKE_CTRL_WAKE_SHIFT 0
-#define BCHP_PCIE_0_DMA_RX_WAKE_CTRL_WAKE_DEFAULT 0x00000000
-
-/***************************************************************************
- *RX_ERROR_STATUS - Rx Engine Error Status
- ***************************************************************************/
-/* PCIE_0_DMA :: RX_ERROR_STATUS :: reserved0 [31:10] */
-#define BCHP_PCIE_0_DMA_RX_ERROR_STATUS_reserved0_MASK 0xfffffc00
-#define BCHP_PCIE_0_DMA_RX_ERROR_STATUS_reserved0_SHIFT 10
-
-/* PCIE_0_DMA :: RX_ERROR_STATUS :: RX_L1_DESC_TX_ABORT_ERRORS [09:09] */
-#define BCHP_PCIE_0_DMA_RX_ERROR_STATUS_RX_L1_DESC_TX_ABORT_ERRORS_MASK 0x00000200
-#define BCHP_PCIE_0_DMA_RX_ERROR_STATUS_RX_L1_DESC_TX_ABORT_ERRORS_SHIFT 9
-#define BCHP_PCIE_0_DMA_RX_ERROR_STATUS_RX_L1_DESC_TX_ABORT_ERRORS_DEFAULT 0x00000000
-
-/* PCIE_0_DMA :: RX_ERROR_STATUS :: reserved1 [08:08] */
-#define BCHP_PCIE_0_DMA_RX_ERROR_STATUS_reserved1_MASK 0x00000100
-#define BCHP_PCIE_0_DMA_RX_ERROR_STATUS_reserved1_SHIFT 8
-
-/* PCIE_0_DMA :: RX_ERROR_STATUS :: RX_L0_DESC_TX_ABORT_ERRORS [07:07] */
-#define BCHP_PCIE_0_DMA_RX_ERROR_STATUS_RX_L0_DESC_TX_ABORT_ERRORS_MASK 0x00000080
-#define BCHP_PCIE_0_DMA_RX_ERROR_STATUS_RX_L0_DESC_TX_ABORT_ERRORS_SHIFT 7
-#define BCHP_PCIE_0_DMA_RX_ERROR_STATUS_RX_L0_DESC_TX_ABORT_ERRORS_DEFAULT 0x00000000
-
-/* PCIE_0_DMA :: RX_ERROR_STATUS :: reserved2 [06:06] */
-#define BCHP_PCIE_0_DMA_RX_ERROR_STATUS_reserved2_MASK 0x00000040
-#define BCHP_PCIE_0_DMA_RX_ERROR_STATUS_reserved2_SHIFT 6
-
-/* PCIE_0_DMA :: RX_ERROR_STATUS :: RX_L1_DATA_TX_ABORT_ERRORS [05:05] */
-#define BCHP_PCIE_0_DMA_RX_ERROR_STATUS_RX_L1_DATA_TX_ABORT_ERRORS_MASK 0x00000020
-#define BCHP_PCIE_0_DMA_RX_ERROR_STATUS_RX_L1_DATA_TX_ABORT_ERRORS_SHIFT 5
-#define BCHP_PCIE_0_DMA_RX_ERROR_STATUS_RX_L1_DATA_TX_ABORT_ERRORS_DEFAULT 0x00000000
-
-/* PCIE_0_DMA :: RX_ERROR_STATUS :: reserved3 [04:03] */
-#define BCHP_PCIE_0_DMA_RX_ERROR_STATUS_reserved3_MASK 0x00000018
-#define BCHP_PCIE_0_DMA_RX_ERROR_STATUS_reserved3_SHIFT 3
-
-/* PCIE_0_DMA :: RX_ERROR_STATUS :: RX_L0_DATA_TX_ABORT_ERRORS [02:02] */
-#define BCHP_PCIE_0_DMA_RX_ERROR_STATUS_RX_L0_DATA_TX_ABORT_ERRORS_MASK 0x00000004
-#define BCHP_PCIE_0_DMA_RX_ERROR_STATUS_RX_L0_DATA_TX_ABORT_ERRORS_SHIFT 2
-#define BCHP_PCIE_0_DMA_RX_ERROR_STATUS_RX_L0_DATA_TX_ABORT_ERRORS_DEFAULT 0x00000000
-
-/* PCIE_0_DMA :: RX_ERROR_STATUS :: reserved4 [01:00] */
-#define BCHP_PCIE_0_DMA_RX_ERROR_STATUS_reserved4_MASK 0x00000003
-#define BCHP_PCIE_0_DMA_RX_ERROR_STATUS_reserved4_SHIFT 0
-
-/***************************************************************************
- *RX_LIST0_CUR_DESC_L_ADDR - Rx List0 Current Descriptor Lower Address
- ***************************************************************************/
-/* PCIE_0_DMA :: RX_LIST0_CUR_DESC_L_ADDR :: RX_L0_CUR_DESC_L_ADDR [31:05] */
-#define BCHP_PCIE_0_DMA_RX_LIST0_CUR_DESC_L_ADDR_RX_L0_CUR_DESC_L_ADDR_MASK 0xffffffe0
-#define BCHP_PCIE_0_DMA_RX_LIST0_CUR_DESC_L_ADDR_RX_L0_CUR_DESC_L_ADDR_SHIFT 5
-#define BCHP_PCIE_0_DMA_RX_LIST0_CUR_DESC_L_ADDR_RX_L0_CUR_DESC_L_ADDR_DEFAULT 0x00000000
-
-/* PCIE_0_DMA :: RX_LIST0_CUR_DESC_L_ADDR :: reserved0 [04:04] */
-#define BCHP_PCIE_0_DMA_RX_LIST0_CUR_DESC_L_ADDR_reserved0_MASK 0x00000010
-#define BCHP_PCIE_0_DMA_RX_LIST0_CUR_DESC_L_ADDR_reserved0_SHIFT 4
-
-/* PCIE_0_DMA :: RX_LIST0_CUR_DESC_L_ADDR :: RX_L0_CUR_LIST [03:03] */
-#define BCHP_PCIE_0_DMA_RX_LIST0_CUR_DESC_L_ADDR_RX_L0_CUR_LIST_MASK 0x00000008
-#define BCHP_PCIE_0_DMA_RX_LIST0_CUR_DESC_L_ADDR_RX_L0_CUR_LIST_SHIFT 3
-#define BCHP_PCIE_0_DMA_RX_LIST0_CUR_DESC_L_ADDR_RX_L0_CUR_LIST_DEFAULT 0x00000000
-
-/* PCIE_0_DMA :: RX_LIST0_CUR_DESC_L_ADDR :: RX_L0_CUR_IN_PROGRESS [02:02] */
-#define BCHP_PCIE_0_DMA_RX_LIST0_CUR_DESC_L_ADDR_RX_L0_CUR_IN_PROGRESS_MASK 0x00000004
-#define BCHP_PCIE_0_DMA_RX_LIST0_CUR_DESC_L_ADDR_RX_L0_CUR_IN_PROGRESS_SHIFT 2
-#define BCHP_PCIE_0_DMA_RX_LIST0_CUR_DESC_L_ADDR_RX_L0_CUR_IN_PROGRESS_DEFAULT 0x00000000
-
-/* PCIE_0_DMA :: RX_LIST0_CUR_DESC_L_ADDR :: RX_L0_CUR_STATUS [01:00] */
-#define BCHP_PCIE_0_DMA_RX_LIST0_CUR_DESC_L_ADDR_RX_L0_CUR_STATUS_MASK 0x00000003
-#define BCHP_PCIE_0_DMA_RX_LIST0_CUR_DESC_L_ADDR_RX_L0_CUR_STATUS_SHIFT 0
-#define BCHP_PCIE_0_DMA_RX_LIST0_CUR_DESC_L_ADDR_RX_L0_CUR_STATUS_DEFAULT 0x00000000
-
-/***************************************************************************
- *RX_LIST0_CUR_DESC_U_ADDR - Rx List0 Current Descriptor Upper Address
- ***************************************************************************/
-/* PCIE_0_DMA :: RX_LIST0_CUR_DESC_U_ADDR :: RX_L0_CUR_DESC_U_ADDR [31:00] */
-#define BCHP_PCIE_0_DMA_RX_LIST0_CUR_DESC_U_ADDR_RX_L0_CUR_DESC_U_ADDR_MASK 0xffffffff
-#define BCHP_PCIE_0_DMA_RX_LIST0_CUR_DESC_U_ADDR_RX_L0_CUR_DESC_U_ADDR_SHIFT 0
-#define BCHP_PCIE_0_DMA_RX_LIST0_CUR_DESC_U_ADDR_RX_L0_CUR_DESC_U_ADDR_DEFAULT 0x00000000
-
-/***************************************************************************
- *RX_LIST0_CUR_BYTE_CNT - Rx List0 Current Descriptor Byte Count
- ***************************************************************************/
-/* PCIE_0_DMA :: RX_LIST0_CUR_BYTE_CNT :: RX_L0_CUR_BYTE_CNT [31:00] */
-#define BCHP_PCIE_0_DMA_RX_LIST0_CUR_BYTE_CNT_RX_L0_CUR_BYTE_CNT_MASK 0xffffffff
-#define BCHP_PCIE_0_DMA_RX_LIST0_CUR_BYTE_CNT_RX_L0_CUR_BYTE_CNT_SHIFT 0
-#define BCHP_PCIE_0_DMA_RX_LIST0_CUR_BYTE_CNT_RX_L0_CUR_BYTE_CNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *RX_LIST1_CUR_DESC_L_ADDR - Rx List1 Current Descriptor Lower address
- ***************************************************************************/
-/* PCIE_0_DMA :: RX_LIST1_CUR_DESC_L_ADDR :: RX_L1_CUR_DESC_L_ADDR [31:05] */
-#define BCHP_PCIE_0_DMA_RX_LIST1_CUR_DESC_L_ADDR_RX_L1_CUR_DESC_L_ADDR_MASK 0xffffffe0
-#define BCHP_PCIE_0_DMA_RX_LIST1_CUR_DESC_L_ADDR_RX_L1_CUR_DESC_L_ADDR_SHIFT 5
-#define BCHP_PCIE_0_DMA_RX_LIST1_CUR_DESC_L_ADDR_RX_L1_CUR_DESC_L_ADDR_DEFAULT 0x00000000
-
-/* PCIE_0_DMA :: RX_LIST1_CUR_DESC_L_ADDR :: reserved0 [04:04] */
-#define BCHP_PCIE_0_DMA_RX_LIST1_CUR_DESC_L_ADDR_reserved0_MASK 0x00000010
-#define BCHP_PCIE_0_DMA_RX_LIST1_CUR_DESC_L_ADDR_reserved0_SHIFT 4
-
-/* PCIE_0_DMA :: RX_LIST1_CUR_DESC_L_ADDR :: RX_L1_CUR_LIST [03:03] */
-#define BCHP_PCIE_0_DMA_RX_LIST1_CUR_DESC_L_ADDR_RX_L1_CUR_LIST_MASK 0x00000008
-#define BCHP_PCIE_0_DMA_RX_LIST1_CUR_DESC_L_ADDR_RX_L1_CUR_LIST_SHIFT 3
-#define BCHP_PCIE_0_DMA_RX_LIST1_CUR_DESC_L_ADDR_RX_L1_CUR_LIST_DEFAULT 0x00000000
-
-/* PCIE_0_DMA :: RX_LIST1_CUR_DESC_L_ADDR :: RX_L1_CUR_IN_PROGRESS [02:02] */
-#define BCHP_PCIE_0_DMA_RX_LIST1_CUR_DESC_L_ADDR_RX_L1_CUR_IN_PROGRESS_MASK 0x00000004
-#define BCHP_PCIE_0_DMA_RX_LIST1_CUR_DESC_L_ADDR_RX_L1_CUR_IN_PROGRESS_SHIFT 2
-#define BCHP_PCIE_0_DMA_RX_LIST1_CUR_DESC_L_ADDR_RX_L1_CUR_IN_PROGRESS_DEFAULT 0x00000000
-
-/* PCIE_0_DMA :: RX_LIST1_CUR_DESC_L_ADDR :: RX_L1_CUR_STATUS [01:00] */
-#define BCHP_PCIE_0_DMA_RX_LIST1_CUR_DESC_L_ADDR_RX_L1_CUR_STATUS_MASK 0x00000003
-#define BCHP_PCIE_0_DMA_RX_LIST1_CUR_DESC_L_ADDR_RX_L1_CUR_STATUS_SHIFT 0
-#define BCHP_PCIE_0_DMA_RX_LIST1_CUR_DESC_L_ADDR_RX_L1_CUR_STATUS_DEFAULT 0x00000000
-
-/***************************************************************************
- *RX_LIST1_CUR_DESC_U_ADDR - Rx List1 Current Descriptor Upper address
- ***************************************************************************/
-/* PCIE_0_DMA :: RX_LIST1_CUR_DESC_U_ADDR :: RX_L1_CUR_DESC_U_ADDR [31:00] */
-#define BCHP_PCIE_0_DMA_RX_LIST1_CUR_DESC_U_ADDR_RX_L1_CUR_DESC_U_ADDR_MASK 0xffffffff
-#define BCHP_PCIE_0_DMA_RX_LIST1_CUR_DESC_U_ADDR_RX_L1_CUR_DESC_U_ADDR_SHIFT 0
-#define BCHP_PCIE_0_DMA_RX_LIST1_CUR_DESC_U_ADDR_RX_L1_CUR_DESC_U_ADDR_DEFAULT 0x00000000
-
-/***************************************************************************
- *RX_LIST1_CUR_BYTE_CNT - Rx List1 Current Descriptor Byte Count
- ***************************************************************************/
-/* PCIE_0_DMA :: RX_LIST1_CUR_BYTE_CNT :: RX_L1_CUR_BYTE_CNT [31:00] */
-#define BCHP_PCIE_0_DMA_RX_LIST1_CUR_BYTE_CNT_RX_L1_CUR_BYTE_CNT_MASK 0xffffffff
-#define BCHP_PCIE_0_DMA_RX_LIST1_CUR_BYTE_CNT_RX_L1_CUR_BYTE_CNT_SHIFT 0
-#define BCHP_PCIE_0_DMA_RX_LIST1_CUR_BYTE_CNT_RX_L1_CUR_BYTE_CNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *DMA_DEBUG_OPTIONS_REG - DMA Debug Options Register
- ***************************************************************************/
-/* PCIE_0_DMA :: DMA_DEBUG_OPTIONS_REG :: DMA_DEBUG_TX_DMA_SOFT_RST [31:31] */
-#define BCHP_PCIE_0_DMA_DMA_DEBUG_OPTIONS_REG_DMA_DEBUG_TX_DMA_SOFT_RST_MASK 0x80000000
-#define BCHP_PCIE_0_DMA_DMA_DEBUG_OPTIONS_REG_DMA_DEBUG_TX_DMA_SOFT_RST_SHIFT 31
-#define BCHP_PCIE_0_DMA_DMA_DEBUG_OPTIONS_REG_DMA_DEBUG_TX_DMA_SOFT_RST_DEFAULT 0x00000000
-
-/* PCIE_0_DMA :: DMA_DEBUG_OPTIONS_REG :: DMA_DEBUG_RX_DMA_SOFT_RST [30:30] */
-#define BCHP_PCIE_0_DMA_DMA_DEBUG_OPTIONS_REG_DMA_DEBUG_RX_DMA_SOFT_RST_MASK 0x40000000
-#define BCHP_PCIE_0_DMA_DMA_DEBUG_OPTIONS_REG_DMA_DEBUG_RX_DMA_SOFT_RST_SHIFT 30
-#define BCHP_PCIE_0_DMA_DMA_DEBUG_OPTIONS_REG_DMA_DEBUG_RX_DMA_SOFT_RST_DEFAULT 0x00000000
-
-/* PCIE_0_DMA :: DMA_DEBUG_OPTIONS_REG :: DMA_DEBUG_TX_DMA_RD_Q_SOFT_RST [29:29] */
-#define BCHP_PCIE_0_DMA_DMA_DEBUG_OPTIONS_REG_DMA_DEBUG_TX_DMA_RD_Q_SOFT_RST_MASK 0x20000000
-#define BCHP_PCIE_0_DMA_DMA_DEBUG_OPTIONS_REG_DMA_DEBUG_TX_DMA_RD_Q_SOFT_RST_SHIFT 29
-#define BCHP_PCIE_0_DMA_DMA_DEBUG_OPTIONS_REG_DMA_DEBUG_TX_DMA_RD_Q_SOFT_RST_DEFAULT 0x00000000
-
-/* PCIE_0_DMA :: DMA_DEBUG_OPTIONS_REG :: DMA_DEBUG_RX_DMA_WR_Q_SOFT_RST [28:28] */
-#define BCHP_PCIE_0_DMA_DMA_DEBUG_OPTIONS_REG_DMA_DEBUG_RX_DMA_WR_Q_SOFT_RST_MASK 0x10000000
-#define BCHP_PCIE_0_DMA_DMA_DEBUG_OPTIONS_REG_DMA_DEBUG_RX_DMA_WR_Q_SOFT_RST_SHIFT 28
-#define BCHP_PCIE_0_DMA_DMA_DEBUG_OPTIONS_REG_DMA_DEBUG_RX_DMA_WR_Q_SOFT_RST_DEFAULT 0x00000000
-
-/* PCIE_0_DMA :: DMA_DEBUG_OPTIONS_REG :: RSVD_DMA_DEBUG_0 [27:10] */
-#define BCHP_PCIE_0_DMA_DMA_DEBUG_OPTIONS_REG_RSVD_DMA_DEBUG_0_MASK 0x0ffffc00
-#define BCHP_PCIE_0_DMA_DMA_DEBUG_OPTIONS_REG_RSVD_DMA_DEBUG_0_SHIFT 10
-#define BCHP_PCIE_0_DMA_DMA_DEBUG_OPTIONS_REG_RSVD_DMA_DEBUG_0_DEFAULT 0x00000000
-
-/* PCIE_0_DMA :: DMA_DEBUG_OPTIONS_REG :: DMA_DEBUG_SPQ_SNAP_PW_DIS [09:09] */
-#define BCHP_PCIE_0_DMA_DMA_DEBUG_OPTIONS_REG_DMA_DEBUG_SPQ_SNAP_PW_DIS_MASK 0x00000200
-#define BCHP_PCIE_0_DMA_DMA_DEBUG_OPTIONS_REG_DMA_DEBUG_SPQ_SNAP_PW_DIS_SHIFT 9
-#define BCHP_PCIE_0_DMA_DMA_DEBUG_OPTIONS_REG_DMA_DEBUG_SPQ_SNAP_PW_DIS_DEFAULT 0x00000000
-
-/* PCIE_0_DMA :: DMA_DEBUG_OPTIONS_REG :: DMA_DEBUG_OUTCP_Q_RO [08:08] */
-#define BCHP_PCIE_0_DMA_DMA_DEBUG_OPTIONS_REG_DMA_DEBUG_OUTCP_Q_RO_MASK 0x00000100
-#define BCHP_PCIE_0_DMA_DMA_DEBUG_OPTIONS_REG_DMA_DEBUG_OUTCP_Q_RO_SHIFT 8
-#define BCHP_PCIE_0_DMA_DMA_DEBUG_OPTIONS_REG_DMA_DEBUG_OUTCP_Q_RO_DEFAULT 0x00000000
-
-/* PCIE_0_DMA :: DMA_DEBUG_OPTIONS_REG :: DMA_DEBUG_NO_TX_DESC [07:07] */
-#define BCHP_PCIE_0_DMA_DMA_DEBUG_OPTIONS_REG_DMA_DEBUG_NO_TX_DESC_MASK 0x00000080
-#define BCHP_PCIE_0_DMA_DMA_DEBUG_OPTIONS_REG_DMA_DEBUG_NO_TX_DESC_SHIFT 7
-#define BCHP_PCIE_0_DMA_DMA_DEBUG_OPTIONS_REG_DMA_DEBUG_NO_TX_DESC_DEFAULT 0x00000000
-
-/* PCIE_0_DMA :: DMA_DEBUG_OPTIONS_REG :: DMA_DEBUG_NO_RX_DESC [06:06] */
-#define BCHP_PCIE_0_DMA_DMA_DEBUG_OPTIONS_REG_DMA_DEBUG_NO_RX_DESC_MASK 0x00000040
-#define BCHP_PCIE_0_DMA_DMA_DEBUG_OPTIONS_REG_DMA_DEBUG_NO_RX_DESC_SHIFT 6
-#define BCHP_PCIE_0_DMA_DMA_DEBUG_OPTIONS_REG_DMA_DEBUG_NO_RX_DESC_DEFAULT 0x00000000
-
-/* PCIE_0_DMA :: DMA_DEBUG_OPTIONS_REG :: DMA_DEBUG_SEL_RX_CNT [05:05] */
-#define BCHP_PCIE_0_DMA_DMA_DEBUG_OPTIONS_REG_DMA_DEBUG_SEL_RX_CNT_MASK 0x00000020
-#define BCHP_PCIE_0_DMA_DMA_DEBUG_OPTIONS_REG_DMA_DEBUG_SEL_RX_CNT_SHIFT 5
-#define BCHP_PCIE_0_DMA_DMA_DEBUG_OPTIONS_REG_DMA_DEBUG_SEL_RX_CNT_DEFAULT 0x00000000
-
-/* PCIE_0_DMA :: DMA_DEBUG_OPTIONS_REG :: DMA_DEBUG_EN_RX_DMA_XFER_CNT [04:04] */
-#define BCHP_PCIE_0_DMA_DMA_DEBUG_OPTIONS_REG_DMA_DEBUG_EN_RX_DMA_XFER_CNT_MASK 0x00000010
-#define BCHP_PCIE_0_DMA_DMA_DEBUG_OPTIONS_REG_DMA_DEBUG_EN_RX_DMA_XFER_CNT_SHIFT 4
-#define BCHP_PCIE_0_DMA_DMA_DEBUG_OPTIONS_REG_DMA_DEBUG_EN_RX_DMA_XFER_CNT_DEFAULT 0x00000000
-
-/* PCIE_0_DMA :: DMA_DEBUG_OPTIONS_REG :: DMA_DEBUG_SEL_TX_CNT [03:03] */
-#define BCHP_PCIE_0_DMA_DMA_DEBUG_OPTIONS_REG_DMA_DEBUG_SEL_TX_CNT_MASK 0x00000008
-#define BCHP_PCIE_0_DMA_DMA_DEBUG_OPTIONS_REG_DMA_DEBUG_SEL_TX_CNT_SHIFT 3
-#define BCHP_PCIE_0_DMA_DMA_DEBUG_OPTIONS_REG_DMA_DEBUG_SEL_TX_CNT_DEFAULT 0x00000000
-
-/* PCIE_0_DMA :: DMA_DEBUG_OPTIONS_REG :: DMA_DEBUG_SINGLE_RD_Q [02:02] */
-#define BCHP_PCIE_0_DMA_DMA_DEBUG_OPTIONS_REG_DMA_DEBUG_SINGLE_RD_Q_MASK 0x00000004
-#define BCHP_PCIE_0_DMA_DMA_DEBUG_OPTIONS_REG_DMA_DEBUG_SINGLE_RD_Q_SHIFT 2
-#define BCHP_PCIE_0_DMA_DMA_DEBUG_OPTIONS_REG_DMA_DEBUG_SINGLE_RD_Q_DEFAULT 0x00000000
-
-/* PCIE_0_DMA :: DMA_DEBUG_OPTIONS_REG :: DMA_DEBUG_SINGLE_WR_Q [01:01] */
-#define BCHP_PCIE_0_DMA_DMA_DEBUG_OPTIONS_REG_DMA_DEBUG_SINGLE_WR_Q_MASK 0x00000002
-#define BCHP_PCIE_0_DMA_DMA_DEBUG_OPTIONS_REG_DMA_DEBUG_SINGLE_WR_Q_SHIFT 1
-#define BCHP_PCIE_0_DMA_DMA_DEBUG_OPTIONS_REG_DMA_DEBUG_SINGLE_WR_Q_DEFAULT 0x00000000
-
-/* PCIE_0_DMA :: DMA_DEBUG_OPTIONS_REG :: DMA_DEBUG_RD_Q_RO [00:00] */
-#define BCHP_PCIE_0_DMA_DMA_DEBUG_OPTIONS_REG_DMA_DEBUG_RD_Q_RO_MASK 0x00000001
-#define BCHP_PCIE_0_DMA_DMA_DEBUG_OPTIONS_REG_DMA_DEBUG_RD_Q_RO_SHIFT 0
-#define BCHP_PCIE_0_DMA_DMA_DEBUG_OPTIONS_REG_DMA_DEBUG_RD_Q_RO_DEFAULT 0x00000000
-
-/***************************************************************************
- *READ_CHANNEL_ERROR_STATUS - Read Channel Error Status
- ***************************************************************************/
-/* PCIE_0_DMA :: READ_CHANNEL_ERROR_STATUS :: TX_ERR_STS_CHAN_7 [31:28] */
-#define BCHP_PCIE_0_DMA_READ_CHANNEL_ERROR_STATUS_TX_ERR_STS_CHAN_7_MASK 0xf0000000
-#define BCHP_PCIE_0_DMA_READ_CHANNEL_ERROR_STATUS_TX_ERR_STS_CHAN_7_SHIFT 28
-#define BCHP_PCIE_0_DMA_READ_CHANNEL_ERROR_STATUS_TX_ERR_STS_CHAN_7_DEFAULT 0x00000000
-
-/* PCIE_0_DMA :: READ_CHANNEL_ERROR_STATUS :: TX_ERR_STS_CHAN_6 [27:24] */
-#define BCHP_PCIE_0_DMA_READ_CHANNEL_ERROR_STATUS_TX_ERR_STS_CHAN_6_MASK 0x0f000000
-#define BCHP_PCIE_0_DMA_READ_CHANNEL_ERROR_STATUS_TX_ERR_STS_CHAN_6_SHIFT 24
-#define BCHP_PCIE_0_DMA_READ_CHANNEL_ERROR_STATUS_TX_ERR_STS_CHAN_6_DEFAULT 0x00000000
-
-/* PCIE_0_DMA :: READ_CHANNEL_ERROR_STATUS :: TX_ERR_STS_CHAN_5 [23:20] */
-#define BCHP_PCIE_0_DMA_READ_CHANNEL_ERROR_STATUS_TX_ERR_STS_CHAN_5_MASK 0x00f00000
-#define BCHP_PCIE_0_DMA_READ_CHANNEL_ERROR_STATUS_TX_ERR_STS_CHAN_5_SHIFT 20
-#define BCHP_PCIE_0_DMA_READ_CHANNEL_ERROR_STATUS_TX_ERR_STS_CHAN_5_DEFAULT 0x00000000
-
-/* PCIE_0_DMA :: READ_CHANNEL_ERROR_STATUS :: TX_ERR_STS_CHAN_4 [19:16] */
-#define BCHP_PCIE_0_DMA_READ_CHANNEL_ERROR_STATUS_TX_ERR_STS_CHAN_4_MASK 0x000f0000
-#define BCHP_PCIE_0_DMA_READ_CHANNEL_ERROR_STATUS_TX_ERR_STS_CHAN_4_SHIFT 16
-#define BCHP_PCIE_0_DMA_READ_CHANNEL_ERROR_STATUS_TX_ERR_STS_CHAN_4_DEFAULT 0x00000000
-
-/* PCIE_0_DMA :: READ_CHANNEL_ERROR_STATUS :: TX_ERR_STS_CHAN_3 [15:12] */
-#define BCHP_PCIE_0_DMA_READ_CHANNEL_ERROR_STATUS_TX_ERR_STS_CHAN_3_MASK 0x0000f000
-#define BCHP_PCIE_0_DMA_READ_CHANNEL_ERROR_STATUS_TX_ERR_STS_CHAN_3_SHIFT 12
-#define BCHP_PCIE_0_DMA_READ_CHANNEL_ERROR_STATUS_TX_ERR_STS_CHAN_3_DEFAULT 0x00000000
-
-/* PCIE_0_DMA :: READ_CHANNEL_ERROR_STATUS :: TX_ERR_STS_CHAN_2 [11:08] */
-#define BCHP_PCIE_0_DMA_READ_CHANNEL_ERROR_STATUS_TX_ERR_STS_CHAN_2_MASK 0x00000f00
-#define BCHP_PCIE_0_DMA_READ_CHANNEL_ERROR_STATUS_TX_ERR_STS_CHAN_2_SHIFT 8
-#define BCHP_PCIE_0_DMA_READ_CHANNEL_ERROR_STATUS_TX_ERR_STS_CHAN_2_DEFAULT 0x00000000
-
-/* PCIE_0_DMA :: READ_CHANNEL_ERROR_STATUS :: TX_ERR_STS_CHAN_1 [07:04] */
-#define BCHP_PCIE_0_DMA_READ_CHANNEL_ERROR_STATUS_TX_ERR_STS_CHAN_1_MASK 0x000000f0
-#define BCHP_PCIE_0_DMA_READ_CHANNEL_ERROR_STATUS_TX_ERR_STS_CHAN_1_SHIFT 4
-#define BCHP_PCIE_0_DMA_READ_CHANNEL_ERROR_STATUS_TX_ERR_STS_CHAN_1_DEFAULT 0x00000000
-
-/* PCIE_0_DMA :: READ_CHANNEL_ERROR_STATUS :: TX_ERR_STS_CHAN_0 [03:00] */
-#define BCHP_PCIE_0_DMA_READ_CHANNEL_ERROR_STATUS_TX_ERR_STS_CHAN_0_MASK 0x0000000f
-#define BCHP_PCIE_0_DMA_READ_CHANNEL_ERROR_STATUS_TX_ERR_STS_CHAN_0_SHIFT 0
-#define BCHP_PCIE_0_DMA_READ_CHANNEL_ERROR_STATUS_TX_ERR_STS_CHAN_0_DEFAULT 0x00000000
-
-#endif /* #ifndef BCHP_PCIE_0_DMA_H__ */
-
-/* End of File */
diff --git a/include/linux/brcmstb/7439a0/bchp_pcie_0_ext_cfg.h b/include/linux/brcmstb/7439a0/bchp_pcie_0_ext_cfg.h
deleted file mode 100644
index 88e98a4..0000000
--- a/include/linux/brcmstb/7439a0/bchp_pcie_0_ext_cfg.h
+++ /dev/null
@@ -1,116 +0,0 @@
-/***************************************************************************
- * Copyright (c) 1999-2013, Broadcom Corporation
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
- *
- * Module Description:
- * DO NOT EDIT THIS FILE DIRECTLY
- *
- * This module was generated magically with RDB from a source description
- * file. You must edit the source file for changes to be made to this file.
- *
- *
- * Date: Generated on Tue Apr 16 03:26:52 2013
- * MD5 Checksum d41d8cd98f00b204e9800998ecf8427e
- *
- * Compiled with: RDB Utility combo_header.pl
- * RDB Parser 3.0
- * unknown unknown
- * Perl Interpreter 5.008008
- * Operating System linux
- *
- * Revision History:
- *
- * $brcm_Log: $
- *
- ***************************************************************************/
-
-#ifndef BCHP_PCIE_0_EXT_CFG_H__
-#define BCHP_PCIE_0_EXT_CFG_H__
-
-/***************************************************************************
- *PCIE_0_EXT_CFG - PCIE EXTERNAL CFG Registers
- ***************************************************************************/
-#define BCHP_PCIE_0_EXT_CFG_PCIE_EXT_CFG_DATA_0 0x00478000 /* PCIe External Configuration Space Data[0] */
-#define BCHP_PCIE_0_EXT_CFG_PCIE_EXT_CFG_DATA_1023 0x00478ffc /* PCIe External Configuration Space Data[1023] */
-#define BCHP_PCIE_0_EXT_CFG_PCIE_EXT_CFG_INDEX 0x00479000 /* PCIE External Configuration Access Index */
-#define BCHP_PCIE_0_EXT_CFG_PCIE_EXT_CFG_DATA 0x00479004 /* PCIE External Configuration Access Data */
-#define BCHP_PCIE_0_EXT_CFG_SCRATCH 0x00479008 /* Scratch Register */
-
-/***************************************************************************
- *PCIE_EXT_CFG_DATA_0 - PCIe External Configuration Space Data[0]
- ***************************************************************************/
-/* PCIE_0_EXT_CFG :: PCIE_EXT_CFG_DATA_0 :: DATA [31:00] */
-#define BCHP_PCIE_0_EXT_CFG_PCIE_EXT_CFG_DATA_0_DATA_MASK 0xffffffff
-#define BCHP_PCIE_0_EXT_CFG_PCIE_EXT_CFG_DATA_0_DATA_SHIFT 0
-
-/***************************************************************************
- *PCIE_EXT_CFG_DATA_1023 - PCIe External Configuration Space Data[1023]
- ***************************************************************************/
-/* PCIE_0_EXT_CFG :: PCIE_EXT_CFG_DATA_1023 :: DATA [31:00] */
-#define BCHP_PCIE_0_EXT_CFG_PCIE_EXT_CFG_DATA_1023_DATA_MASK 0xffffffff
-#define BCHP_PCIE_0_EXT_CFG_PCIE_EXT_CFG_DATA_1023_DATA_SHIFT 0
-
-/***************************************************************************
- *PCIE_EXT_CFG_INDEX - PCIE External Configuration Access Index
- ***************************************************************************/
-/* PCIE_0_EXT_CFG :: PCIE_EXT_CFG_INDEX :: UNUSED_1 [31:28] */
-#define BCHP_PCIE_0_EXT_CFG_PCIE_EXT_CFG_INDEX_UNUSED_1_MASK 0xf0000000
-#define BCHP_PCIE_0_EXT_CFG_PCIE_EXT_CFG_INDEX_UNUSED_1_SHIFT 28
-#define BCHP_PCIE_0_EXT_CFG_PCIE_EXT_CFG_INDEX_UNUSED_1_DEFAULT 0x00000000
-
-/* PCIE_0_EXT_CFG :: PCIE_EXT_CFG_INDEX :: BUS_NUM [27:20] */
-#define BCHP_PCIE_0_EXT_CFG_PCIE_EXT_CFG_INDEX_BUS_NUM_MASK 0x0ff00000
-#define BCHP_PCIE_0_EXT_CFG_PCIE_EXT_CFG_INDEX_BUS_NUM_SHIFT 20
-#define BCHP_PCIE_0_EXT_CFG_PCIE_EXT_CFG_INDEX_BUS_NUM_DEFAULT 0x00000000
-
-/* PCIE_0_EXT_CFG :: PCIE_EXT_CFG_INDEX :: DEV_NUM [19:15] */
-#define BCHP_PCIE_0_EXT_CFG_PCIE_EXT_CFG_INDEX_DEV_NUM_MASK 0x000f8000
-#define BCHP_PCIE_0_EXT_CFG_PCIE_EXT_CFG_INDEX_DEV_NUM_SHIFT 15
-#define BCHP_PCIE_0_EXT_CFG_PCIE_EXT_CFG_INDEX_DEV_NUM_DEFAULT 0x00000000
-
-/* PCIE_0_EXT_CFG :: PCIE_EXT_CFG_INDEX :: FUNC_NUM [14:12] */
-#define BCHP_PCIE_0_EXT_CFG_PCIE_EXT_CFG_INDEX_FUNC_NUM_MASK 0x00007000
-#define BCHP_PCIE_0_EXT_CFG_PCIE_EXT_CFG_INDEX_FUNC_NUM_SHIFT 12
-#define BCHP_PCIE_0_EXT_CFG_PCIE_EXT_CFG_INDEX_FUNC_NUM_DEFAULT 0x00000000
-
-/* PCIE_0_EXT_CFG :: PCIE_EXT_CFG_INDEX :: REG_NUM [11:02] */
-#define BCHP_PCIE_0_EXT_CFG_PCIE_EXT_CFG_INDEX_REG_NUM_MASK 0x00000ffc
-#define BCHP_PCIE_0_EXT_CFG_PCIE_EXT_CFG_INDEX_REG_NUM_SHIFT 2
-#define BCHP_PCIE_0_EXT_CFG_PCIE_EXT_CFG_INDEX_REG_NUM_DEFAULT 0x00000000
-
-/* PCIE_0_EXT_CFG :: PCIE_EXT_CFG_INDEX :: UNUSED_0 [01:00] */
-#define BCHP_PCIE_0_EXT_CFG_PCIE_EXT_CFG_INDEX_UNUSED_0_MASK 0x00000003
-#define BCHP_PCIE_0_EXT_CFG_PCIE_EXT_CFG_INDEX_UNUSED_0_SHIFT 0
-#define BCHP_PCIE_0_EXT_CFG_PCIE_EXT_CFG_INDEX_UNUSED_0_DEFAULT 0x00000000
-
-/***************************************************************************
- *PCIE_EXT_CFG_DATA - PCIE External Configuration Access Data
- ***************************************************************************/
-/* PCIE_0_EXT_CFG :: PCIE_EXT_CFG_DATA :: DATA [31:00] */
-#define BCHP_PCIE_0_EXT_CFG_PCIE_EXT_CFG_DATA_DATA_MASK 0xffffffff
-#define BCHP_PCIE_0_EXT_CFG_PCIE_EXT_CFG_DATA_DATA_SHIFT 0
-#define BCHP_PCIE_0_EXT_CFG_PCIE_EXT_CFG_DATA_DATA_DEFAULT 0x00000000
-
-/***************************************************************************
- *SCRATCH - Scratch Register
- ***************************************************************************/
-/* PCIE_0_EXT_CFG :: SCRATCH :: DATA [31:00] */
-#define BCHP_PCIE_0_EXT_CFG_SCRATCH_DATA_MASK 0xffffffff
-#define BCHP_PCIE_0_EXT_CFG_SCRATCH_DATA_SHIFT 0
-#define BCHP_PCIE_0_EXT_CFG_SCRATCH_DATA_DEFAULT 0x00000000
-
-#endif /* #ifndef BCHP_PCIE_0_EXT_CFG_H__ */
-
-/* End of File */
diff --git a/include/linux/brcmstb/7439a0/bchp_pcie_0_intr2.h b/include/linux/brcmstb/7439a0/bchp_pcie_0_intr2.h
deleted file mode 100644
index 977cb95..0000000
--- a/include/linux/brcmstb/7439a0/bchp_pcie_0_intr2.h
+++ /dev/null
@@ -1,2016 +0,0 @@
-/***************************************************************************
- * Copyright (c) 1999-2013, Broadcom Corporation
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
- *
- * Module Description:
- * DO NOT EDIT THIS FILE DIRECTLY
- *
- * This module was generated magically with RDB from a source description
- * file. You must edit the source file for changes to be made to this file.
- *
- *
- * Date: Generated on Tue Apr 16 03:26:49 2013
- * MD5 Checksum d41d8cd98f00b204e9800998ecf8427e
- *
- * Compiled with: RDB Utility combo_header.pl
- * RDB Parser 3.0
- * unknown unknown
- * Perl Interpreter 5.008008
- * Operating System linux
- *
- * Revision History:
- *
- * $brcm_Log: $
- *
- ***************************************************************************/
-
-#ifndef BCHP_PCIE_0_INTR2_H__
-#define BCHP_PCIE_0_INTR2_H__
-
-/***************************************************************************
- *PCIE_0_INTR2 - PCI-E L2 Interrupt Controller Registers
- ***************************************************************************/
-#define BCHP_PCIE_0_INTR2_CPU_STATUS 0x00474300 /* CPU interrupt Status Register */
-#define BCHP_PCIE_0_INTR2_CPU_SET 0x00474304 /* CPU interrupt Set Register */
-#define BCHP_PCIE_0_INTR2_CPU_CLEAR 0x00474308 /* CPU interrupt Clear Register */
-#define BCHP_PCIE_0_INTR2_CPU_MASK_STATUS 0x0047430c /* CPU interrupt Mask Status Register */
-#define BCHP_PCIE_0_INTR2_CPU_MASK_SET 0x00474310 /* CPU interrupt Mask Set Register */
-#define BCHP_PCIE_0_INTR2_CPU_MASK_CLEAR 0x00474314 /* CPU interrupt Mask Clear Register */
-#define BCHP_PCIE_0_INTR2_PCI_STATUS 0x00474318 /* PCI interrupt Status Register */
-#define BCHP_PCIE_0_INTR2_PCI_SET 0x0047431c /* PCI interrupt Set Register */
-#define BCHP_PCIE_0_INTR2_PCI_CLEAR 0x00474320 /* PCI interrupt Clear Register */
-#define BCHP_PCIE_0_INTR2_PCI_MASK_STATUS 0x00474324 /* PCI interrupt Mask Status Register */
-#define BCHP_PCIE_0_INTR2_PCI_MASK_SET 0x00474328 /* PCI interrupt Mask Set Register */
-#define BCHP_PCIE_0_INTR2_PCI_MASK_CLEAR 0x0047432c /* PCI interrupt Mask Clear Register */
-
-/***************************************************************************
- *CPU_STATUS - CPU interrupt Status Register
- ***************************************************************************/
-/* PCIE_0_INTR2 :: CPU_STATUS :: MSI_INTR07 [31:31] */
-#define BCHP_PCIE_0_INTR2_CPU_STATUS_MSI_INTR07_MASK 0x80000000
-#define BCHP_PCIE_0_INTR2_CPU_STATUS_MSI_INTR07_SHIFT 31
-#define BCHP_PCIE_0_INTR2_CPU_STATUS_MSI_INTR07_DEFAULT 0x00000000
-
-/* PCIE_0_INTR2 :: CPU_STATUS :: MSI_INTR06 [30:30] */
-#define BCHP_PCIE_0_INTR2_CPU_STATUS_MSI_INTR06_MASK 0x40000000
-#define BCHP_PCIE_0_INTR2_CPU_STATUS_MSI_INTR06_SHIFT 30
-#define BCHP_PCIE_0_INTR2_CPU_STATUS_MSI_INTR06_DEFAULT 0x00000000
-
-/* PCIE_0_INTR2 :: CPU_STATUS :: MSI_INTR05 [29:29] */
-#define BCHP_PCIE_0_INTR2_CPU_STATUS_MSI_INTR05_MASK 0x20000000
-#define BCHP_PCIE_0_INTR2_CPU_STATUS_MSI_INTR05_SHIFT 29
-#define BCHP_PCIE_0_INTR2_CPU_STATUS_MSI_INTR05_DEFAULT 0x00000000
-
-/* PCIE_0_INTR2 :: CPU_STATUS :: MSI_INTR04 [28:28] */
-#define BCHP_PCIE_0_INTR2_CPU_STATUS_MSI_INTR04_MASK 0x10000000
-#define BCHP_PCIE_0_INTR2_CPU_STATUS_MSI_INTR04_SHIFT 28
-#define BCHP_PCIE_0_INTR2_CPU_STATUS_MSI_INTR04_DEFAULT 0x00000000
-
-/* PCIE_0_INTR2 :: CPU_STATUS :: MSI_INTR03 [27:27] */
-#define BCHP_PCIE_0_INTR2_CPU_STATUS_MSI_INTR03_MASK 0x08000000
-#define BCHP_PCIE_0_INTR2_CPU_STATUS_MSI_INTR03_SHIFT 27
-#define BCHP_PCIE_0_INTR2_CPU_STATUS_MSI_INTR03_DEFAULT 0x00000000
-
-/* PCIE_0_INTR2 :: CPU_STATUS :: MSI_INTR02 [26:26] */
-#define BCHP_PCIE_0_INTR2_CPU_STATUS_MSI_INTR02_MASK 0x04000000
-#define BCHP_PCIE_0_INTR2_CPU_STATUS_MSI_INTR02_SHIFT 26
-#define BCHP_PCIE_0_INTR2_CPU_STATUS_MSI_INTR02_DEFAULT 0x00000000
-
-/* PCIE_0_INTR2 :: CPU_STATUS :: MSI_INTR01 [25:25] */
-#define BCHP_PCIE_0_INTR2_CPU_STATUS_MSI_INTR01_MASK 0x02000000
-#define BCHP_PCIE_0_INTR2_CPU_STATUS_MSI_INTR01_SHIFT 25
-#define BCHP_PCIE_0_INTR2_CPU_STATUS_MSI_INTR01_DEFAULT 0x00000000
-
-/* PCIE_0_INTR2 :: CPU_STATUS :: MSI_INTR00 [24:24] */
-#define BCHP_PCIE_0_INTR2_CPU_STATUS_MSI_INTR00_MASK 0x01000000
-#define BCHP_PCIE_0_INTR2_CPU_STATUS_MSI_INTR00_SHIFT 24
-#define BCHP_PCIE_0_INTR2_CPU_STATUS_MSI_INTR00_DEFAULT 0x00000000
-
-/* PCIE_0_INTR2 :: CPU_STATUS :: UNASSIGNED_23 [23:23] */
-#define BCHP_PCIE_0_INTR2_CPU_STATUS_UNASSIGNED_23_MASK 0x00800000
-#define BCHP_PCIE_0_INTR2_CPU_STATUS_UNASSIGNED_23_SHIFT 23
-#define BCHP_PCIE_0_INTR2_CPU_STATUS_UNASSIGNED_23_DEFAULT 0x00000000
-
-/* PCIE_0_INTR2 :: CPU_STATUS :: UNASSIGNED_22 [22:22] */
-#define BCHP_PCIE_0_INTR2_CPU_STATUS_UNASSIGNED_22_MASK 0x00400000
-#define BCHP_PCIE_0_INTR2_CPU_STATUS_UNASSIGNED_22_SHIFT 22
-#define BCHP_PCIE_0_INTR2_CPU_STATUS_UNASSIGNED_22_DEFAULT 0x00000000
-
-/* PCIE_0_INTR2 :: CPU_STATUS :: UNASSIGNED_21 [21:21] */
-#define BCHP_PCIE_0_INTR2_CPU_STATUS_UNASSIGNED_21_MASK 0x00200000
-#define BCHP_PCIE_0_INTR2_CPU_STATUS_UNASSIGNED_21_SHIFT 21
-#define BCHP_PCIE_0_INTR2_CPU_STATUS_UNASSIGNED_21_DEFAULT 0x00000000
-
-/* PCIE_0_INTR2 :: CPU_STATUS :: UNASSIGNED_20 [20:20] */
-#define BCHP_PCIE_0_INTR2_CPU_STATUS_UNASSIGNED_20_MASK 0x00100000
-#define BCHP_PCIE_0_INTR2_CPU_STATUS_UNASSIGNED_20_SHIFT 20
-#define BCHP_PCIE_0_INTR2_CPU_STATUS_UNASSIGNED_20_DEFAULT 0x00000000
-
-/* PCIE_0_INTR2 :: CPU_STATUS :: MAILBOX_3 [19:19] */
-#define BCHP_PCIE_0_INTR2_CPU_STATUS_MAILBOX_3_MASK 0x00080000
-#define BCHP_PCIE_0_INTR2_CPU_STATUS_MAILBOX_3_SHIFT 19
-#define BCHP_PCIE_0_INTR2_CPU_STATUS_MAILBOX_3_DEFAULT 0x00000000
-
-/* PCIE_0_INTR2 :: CPU_STATUS :: MAILBOX_2 [18:18] */
-#define BCHP_PCIE_0_INTR2_CPU_STATUS_MAILBOX_2_MASK 0x00040000
-#define BCHP_PCIE_0_INTR2_CPU_STATUS_MAILBOX_2_SHIFT 18
-#define BCHP_PCIE_0_INTR2_CPU_STATUS_MAILBOX_2_DEFAULT 0x00000000
-
-/* PCIE_0_INTR2 :: CPU_STATUS :: MAILBOX_1 [17:17] */
-#define BCHP_PCIE_0_INTR2_CPU_STATUS_MAILBOX_1_MASK 0x00020000
-#define BCHP_PCIE_0_INTR2_CPU_STATUS_MAILBOX_1_SHIFT 17
-#define BCHP_PCIE_0_INTR2_CPU_STATUS_MAILBOX_1_DEFAULT 0x00000000
-
-/* PCIE_0_INTR2 :: CPU_STATUS :: MAILBOX_0 [16:16] */
-#define BCHP_PCIE_0_INTR2_CPU_STATUS_MAILBOX_0_MASK 0x00010000
-#define BCHP_PCIE_0_INTR2_CPU_STATUS_MAILBOX_0_SHIFT 16
-#define BCHP_PCIE_0_INTR2_CPU_STATUS_MAILBOX_0_DEFAULT 0x00000000
-
-/* PCIE_0_INTR2 :: CPU_STATUS :: PCIE_MSTR_FWD_ERR [15:15] */
-#define BCHP_PCIE_0_INTR2_CPU_STATUS_PCIE_MSTR_FWD_ERR_MASK 0x00008000
-#define BCHP_PCIE_0_INTR2_CPU_STATUS_PCIE_MSTR_FWD_ERR_SHIFT 15
-#define BCHP_PCIE_0_INTR2_CPU_STATUS_PCIE_MSTR_FWD_ERR_DEFAULT 0x00000000
-
-/* PCIE_0_INTR2 :: CPU_STATUS :: PCIE_MSTR_RETRY_TIMEOUT [14:14] */
-#define BCHP_PCIE_0_INTR2_CPU_STATUS_PCIE_MSTR_RETRY_TIMEOUT_MASK 0x00004000
-#define BCHP_PCIE_0_INTR2_CPU_STATUS_PCIE_MSTR_RETRY_TIMEOUT_SHIFT 14
-#define BCHP_PCIE_0_INTR2_CPU_STATUS_PCIE_MSTR_RETRY_TIMEOUT_DEFAULT 0x00000000
-
-/* PCIE_0_INTR2 :: CPU_STATUS :: PCIE_MSTR_CA_ATTN [13:13] */
-#define BCHP_PCIE_0_INTR2_CPU_STATUS_PCIE_MSTR_CA_ATTN_MASK 0x00002000
-#define BCHP_PCIE_0_INTR2_CPU_STATUS_PCIE_MSTR_CA_ATTN_SHIFT 13
-#define BCHP_PCIE_0_INTR2_CPU_STATUS_PCIE_MSTR_CA_ATTN_DEFAULT 0x00000000
-
-/* PCIE_0_INTR2 :: CPU_STATUS :: PCIE_MSTR_UR_ATTN [12:12] */
-#define BCHP_PCIE_0_INTR2_CPU_STATUS_PCIE_MSTR_UR_ATTN_MASK 0x00001000
-#define BCHP_PCIE_0_INTR2_CPU_STATUS_PCIE_MSTR_UR_ATTN_SHIFT 12
-#define BCHP_PCIE_0_INTR2_CPU_STATUS_PCIE_MSTR_UR_ATTN_DEFAULT 0x00000000
-
-/* PCIE_0_INTR2 :: CPU_STATUS :: UNASSIGNED_11 [11:11] */
-#define BCHP_PCIE_0_INTR2_CPU_STATUS_UNASSIGNED_11_MASK 0x00000800
-#define BCHP_PCIE_0_INTR2_CPU_STATUS_UNASSIGNED_11_SHIFT 11
-#define BCHP_PCIE_0_INTR2_CPU_STATUS_UNASSIGNED_11_DEFAULT 0x00000000
-
-/* PCIE_0_INTR2 :: CPU_STATUS :: UNASSIGNED_10 [10:10] */
-#define BCHP_PCIE_0_INTR2_CPU_STATUS_UNASSIGNED_10_MASK 0x00000400
-#define BCHP_PCIE_0_INTR2_CPU_STATUS_UNASSIGNED_10_SHIFT 10
-#define BCHP_PCIE_0_INTR2_CPU_STATUS_UNASSIGNED_10_DEFAULT 0x00000000
-
-/* PCIE_0_INTR2 :: CPU_STATUS :: PCIE_TGT_BAD_ACCESS [09:09] */
-#define BCHP_PCIE_0_INTR2_CPU_STATUS_PCIE_TGT_BAD_ACCESS_MASK 0x00000200
-#define BCHP_PCIE_0_INTR2_CPU_STATUS_PCIE_TGT_BAD_ACCESS_SHIFT 9
-#define BCHP_PCIE_0_INTR2_CPU_STATUS_PCIE_TGT_BAD_ACCESS_DEFAULT 0x00000000
-
-/* PCIE_0_INTR2 :: CPU_STATUS :: PCIE_TGT_BAD_ADDRESS [08:08] */
-#define BCHP_PCIE_0_INTR2_CPU_STATUS_PCIE_TGT_BAD_ADDRESS_MASK 0x00000100
-#define BCHP_PCIE_0_INTR2_CPU_STATUS_PCIE_TGT_BAD_ADDRESS_SHIFT 8
-#define BCHP_PCIE_0_INTR2_CPU_STATUS_PCIE_TGT_BAD_ADDRESS_DEFAULT 0x00000000
-
-/* PCIE_0_INTR2 :: CPU_STATUS :: L1_RX_DMA_ERR_INTR [07:07] */
-#define BCHP_PCIE_0_INTR2_CPU_STATUS_L1_RX_DMA_ERR_INTR_MASK 0x00000080
-#define BCHP_PCIE_0_INTR2_CPU_STATUS_L1_RX_DMA_ERR_INTR_SHIFT 7
-#define BCHP_PCIE_0_INTR2_CPU_STATUS_L1_RX_DMA_ERR_INTR_DEFAULT 0x00000000
-
-/* PCIE_0_INTR2 :: CPU_STATUS :: L1_RX_DMA_DONE_INTR [06:06] */
-#define BCHP_PCIE_0_INTR2_CPU_STATUS_L1_RX_DMA_DONE_INTR_MASK 0x00000040
-#define BCHP_PCIE_0_INTR2_CPU_STATUS_L1_RX_DMA_DONE_INTR_SHIFT 6
-#define BCHP_PCIE_0_INTR2_CPU_STATUS_L1_RX_DMA_DONE_INTR_DEFAULT 0x00000000
-
-/* PCIE_0_INTR2 :: CPU_STATUS :: L1_TX_DMA_ERR_INTR [05:05] */
-#define BCHP_PCIE_0_INTR2_CPU_STATUS_L1_TX_DMA_ERR_INTR_MASK 0x00000020
-#define BCHP_PCIE_0_INTR2_CPU_STATUS_L1_TX_DMA_ERR_INTR_SHIFT 5
-#define BCHP_PCIE_0_INTR2_CPU_STATUS_L1_TX_DMA_ERR_INTR_DEFAULT 0x00000000
-
-/* PCIE_0_INTR2 :: CPU_STATUS :: L1_TX_DMA_DONE_INTR [04:04] */
-#define BCHP_PCIE_0_INTR2_CPU_STATUS_L1_TX_DMA_DONE_INTR_MASK 0x00000010
-#define BCHP_PCIE_0_INTR2_CPU_STATUS_L1_TX_DMA_DONE_INTR_SHIFT 4
-#define BCHP_PCIE_0_INTR2_CPU_STATUS_L1_TX_DMA_DONE_INTR_DEFAULT 0x00000000
-
-/* PCIE_0_INTR2 :: CPU_STATUS :: L0_RX_DMA_ERR_INTR [03:03] */
-#define BCHP_PCIE_0_INTR2_CPU_STATUS_L0_RX_DMA_ERR_INTR_MASK 0x00000008
-#define BCHP_PCIE_0_INTR2_CPU_STATUS_L0_RX_DMA_ERR_INTR_SHIFT 3
-#define BCHP_PCIE_0_INTR2_CPU_STATUS_L0_RX_DMA_ERR_INTR_DEFAULT 0x00000000
-
-/* PCIE_0_INTR2 :: CPU_STATUS :: L0_RX_DMA_DONE_INTR [02:02] */
-#define BCHP_PCIE_0_INTR2_CPU_STATUS_L0_RX_DMA_DONE_INTR_MASK 0x00000004
-#define BCHP_PCIE_0_INTR2_CPU_STATUS_L0_RX_DMA_DONE_INTR_SHIFT 2
-#define BCHP_PCIE_0_INTR2_CPU_STATUS_L0_RX_DMA_DONE_INTR_DEFAULT 0x00000000
-
-/* PCIE_0_INTR2 :: CPU_STATUS :: L0_TX_DMA_ERR_INTR [01:01] */
-#define BCHP_PCIE_0_INTR2_CPU_STATUS_L0_TX_DMA_ERR_INTR_MASK 0x00000002
-#define BCHP_PCIE_0_INTR2_CPU_STATUS_L0_TX_DMA_ERR_INTR_SHIFT 1
-#define BCHP_PCIE_0_INTR2_CPU_STATUS_L0_TX_DMA_ERR_INTR_DEFAULT 0x00000000
-
-/* PCIE_0_INTR2 :: CPU_STATUS :: L0_TX_DMA_DONE_INTR [00:00] */
-#define BCHP_PCIE_0_INTR2_CPU_STATUS_L0_TX_DMA_DONE_INTR_MASK 0x00000001
-#define BCHP_PCIE_0_INTR2_CPU_STATUS_L0_TX_DMA_DONE_INTR_SHIFT 0
-#define BCHP_PCIE_0_INTR2_CPU_STATUS_L0_TX_DMA_DONE_INTR_DEFAULT 0x00000000
-
-/***************************************************************************
- *CPU_SET - CPU interrupt Set Register
- ***************************************************************************/
-/* PCIE_0_INTR2 :: CPU_SET :: MSI_INTR07 [31:31] */
-#define BCHP_PCIE_0_INTR2_CPU_SET_MSI_INTR07_MASK 0x80000000
-#define BCHP_PCIE_0_INTR2_CPU_SET_MSI_INTR07_SHIFT 31
-#define BCHP_PCIE_0_INTR2_CPU_SET_MSI_INTR07_DEFAULT 0x00000000
-
-/* PCIE_0_INTR2 :: CPU_SET :: MSI_INTR06 [30:30] */
-#define BCHP_PCIE_0_INTR2_CPU_SET_MSI_INTR06_MASK 0x40000000
-#define BCHP_PCIE_0_INTR2_CPU_SET_MSI_INTR06_SHIFT 30
-#define BCHP_PCIE_0_INTR2_CPU_SET_MSI_INTR06_DEFAULT 0x00000000
-
-/* PCIE_0_INTR2 :: CPU_SET :: MSI_INTR05 [29:29] */
-#define BCHP_PCIE_0_INTR2_CPU_SET_MSI_INTR05_MASK 0x20000000
-#define BCHP_PCIE_0_INTR2_CPU_SET_MSI_INTR05_SHIFT 29
-#define BCHP_PCIE_0_INTR2_CPU_SET_MSI_INTR05_DEFAULT 0x00000000
-
-/* PCIE_0_INTR2 :: CPU_SET :: MSI_INTR04 [28:28] */
-#define BCHP_PCIE_0_INTR2_CPU_SET_MSI_INTR04_MASK 0x10000000
-#define BCHP_PCIE_0_INTR2_CPU_SET_MSI_INTR04_SHIFT 28
-#define BCHP_PCIE_0_INTR2_CPU_SET_MSI_INTR04_DEFAULT 0x00000000
-
-/* PCIE_0_INTR2 :: CPU_SET :: MSI_INTR03 [27:27] */
-#define BCHP_PCIE_0_INTR2_CPU_SET_MSI_INTR03_MASK 0x08000000
-#define BCHP_PCIE_0_INTR2_CPU_SET_MSI_INTR03_SHIFT 27
-#define BCHP_PCIE_0_INTR2_CPU_SET_MSI_INTR03_DEFAULT 0x00000000
-
-/* PCIE_0_INTR2 :: CPU_SET :: MSI_INTR02 [26:26] */
-#define BCHP_PCIE_0_INTR2_CPU_SET_MSI_INTR02_MASK 0x04000000
-#define BCHP_PCIE_0_INTR2_CPU_SET_MSI_INTR02_SHIFT 26
-#define BCHP_PCIE_0_INTR2_CPU_SET_MSI_INTR02_DEFAULT 0x00000000
-
-/* PCIE_0_INTR2 :: CPU_SET :: MSI_INTR01 [25:25] */
-#define BCHP_PCIE_0_INTR2_CPU_SET_MSI_INTR01_MASK 0x02000000
-#define BCHP_PCIE_0_INTR2_CPU_SET_MSI_INTR01_SHIFT 25
-#define BCHP_PCIE_0_INTR2_CPU_SET_MSI_INTR01_DEFAULT 0x00000000
-
-/* PCIE_0_INTR2 :: CPU_SET :: MSI_INTR00 [24:24] */
-#define BCHP_PCIE_0_INTR2_CPU_SET_MSI_INTR00_MASK 0x01000000
-#define BCHP_PCIE_0_INTR2_CPU_SET_MSI_INTR00_SHIFT 24
-#define BCHP_PCIE_0_INTR2_CPU_SET_MSI_INTR00_DEFAULT 0x00000000
-
-/* PCIE_0_INTR2 :: CPU_SET :: UNASSIGNED_23 [23:23] */
-#define BCHP_PCIE_0_INTR2_CPU_SET_UNASSIGNED_23_MASK 0x00800000
-#define BCHP_PCIE_0_INTR2_CPU_SET_UNASSIGNED_23_SHIFT 23
-#define BCHP_PCIE_0_INTR2_CPU_SET_UNASSIGNED_23_DEFAULT 0x00000000
-
-/* PCIE_0_INTR2 :: CPU_SET :: UNASSIGNED_22 [22:22] */
-#define BCHP_PCIE_0_INTR2_CPU_SET_UNASSIGNED_22_MASK 0x00400000
-#define BCHP_PCIE_0_INTR2_CPU_SET_UNASSIGNED_22_SHIFT 22
-#define BCHP_PCIE_0_INTR2_CPU_SET_UNASSIGNED_22_DEFAULT 0x00000000
-
-/* PCIE_0_INTR2 :: CPU_SET :: UNASSIGNED_21 [21:21] */
-#define BCHP_PCIE_0_INTR2_CPU_SET_UNASSIGNED_21_MASK 0x00200000
-#define BCHP_PCIE_0_INTR2_CPU_SET_UNASSIGNED_21_SHIFT 21
-#define BCHP_PCIE_0_INTR2_CPU_SET_UNASSIGNED_21_DEFAULT 0x00000000
-
-/* PCIE_0_INTR2 :: CPU_SET :: UNASSIGNED_20 [20:20] */
-#define BCHP_PCIE_0_INTR2_CPU_SET_UNASSIGNED_20_MASK 0x00100000
-#define BCHP_PCIE_0_INTR2_CPU_SET_UNASSIGNED_20_SHIFT 20
-#define BCHP_PCIE_0_INTR2_CPU_SET_UNASSIGNED_20_DEFAULT 0x00000000
-
-/* PCIE_0_INTR2 :: CPU_SET :: MAILBOX_3 [19:19] */
-#define BCHP_PCIE_0_INTR2_CPU_SET_MAILBOX_3_MASK 0x00080000
-#define BCHP_PCIE_0_INTR2_CPU_SET_MAILBOX_3_SHIFT 19
-#define BCHP_PCIE_0_INTR2_CPU_SET_MAILBOX_3_DEFAULT 0x00000000
-
-/* PCIE_0_INTR2 :: CPU_SET :: MAILBOX_2 [18:18] */
-#define BCHP_PCIE_0_INTR2_CPU_SET_MAILBOX_2_MASK 0x00040000
-#define BCHP_PCIE_0_INTR2_CPU_SET_MAILBOX_2_SHIFT 18
-#define BCHP_PCIE_0_INTR2_CPU_SET_MAILBOX_2_DEFAULT 0x00000000
-
-/* PCIE_0_INTR2 :: CPU_SET :: MAILBOX_1 [17:17] */
-#define BCHP_PCIE_0_INTR2_CPU_SET_MAILBOX_1_MASK 0x00020000
-#define BCHP_PCIE_0_INTR2_CPU_SET_MAILBOX_1_SHIFT 17
-#define BCHP_PCIE_0_INTR2_CPU_SET_MAILBOX_1_DEFAULT 0x00000000
-
-/* PCIE_0_INTR2 :: CPU_SET :: MAILBOX_0 [16:16] */
-#define BCHP_PCIE_0_INTR2_CPU_SET_MAILBOX_0_MASK 0x00010000
-#define BCHP_PCIE_0_INTR2_CPU_SET_MAILBOX_0_SHIFT 16
-#define BCHP_PCIE_0_INTR2_CPU_SET_MAILBOX_0_DEFAULT 0x00000000
-
-/* PCIE_0_INTR2 :: CPU_SET :: PCIE_MSTR_FWD_ERR [15:15] */
-#define BCHP_PCIE_0_INTR2_CPU_SET_PCIE_MSTR_FWD_ERR_MASK 0x00008000
-#define BCHP_PCIE_0_INTR2_CPU_SET_PCIE_MSTR_FWD_ERR_SHIFT 15
-#define BCHP_PCIE_0_INTR2_CPU_SET_PCIE_MSTR_FWD_ERR_DEFAULT 0x00000000
-
-/* PCIE_0_INTR2 :: CPU_SET :: PCIE_MSTR_RETRY_TIMEOUT [14:14] */
-#define BCHP_PCIE_0_INTR2_CPU_SET_PCIE_MSTR_RETRY_TIMEOUT_MASK 0x00004000
-#define BCHP_PCIE_0_INTR2_CPU_SET_PCIE_MSTR_RETRY_TIMEOUT_SHIFT 14
-#define BCHP_PCIE_0_INTR2_CPU_SET_PCIE_MSTR_RETRY_TIMEOUT_DEFAULT 0x00000000
-
-/* PCIE_0_INTR2 :: CPU_SET :: PCIE_MSTR_CA_ATTN [13:13] */
-#define BCHP_PCIE_0_INTR2_CPU_SET_PCIE_MSTR_CA_ATTN_MASK 0x00002000
-#define BCHP_PCIE_0_INTR2_CPU_SET_PCIE_MSTR_CA_ATTN_SHIFT 13
-#define BCHP_PCIE_0_INTR2_CPU_SET_PCIE_MSTR_CA_ATTN_DEFAULT 0x00000000
-
-/* PCIE_0_INTR2 :: CPU_SET :: PCIE_MSTR_UR_ATTN [12:12] */
-#define BCHP_PCIE_0_INTR2_CPU_SET_PCIE_MSTR_UR_ATTN_MASK 0x00001000
-#define BCHP_PCIE_0_INTR2_CPU_SET_PCIE_MSTR_UR_ATTN_SHIFT 12
-#define BCHP_PCIE_0_INTR2_CPU_SET_PCIE_MSTR_UR_ATTN_DEFAULT 0x00000000
-
-/* PCIE_0_INTR2 :: CPU_SET :: UNASSIGNED_11 [11:11] */
-#define BCHP_PCIE_0_INTR2_CPU_SET_UNASSIGNED_11_MASK 0x00000800
-#define BCHP_PCIE_0_INTR2_CPU_SET_UNASSIGNED_11_SHIFT 11
-#define BCHP_PCIE_0_INTR2_CPU_SET_UNASSIGNED_11_DEFAULT 0x00000000
-
-/* PCIE_0_INTR2 :: CPU_SET :: UNASSIGNED_10 [10:10] */
-#define BCHP_PCIE_0_INTR2_CPU_SET_UNASSIGNED_10_MASK 0x00000400
-#define BCHP_PCIE_0_INTR2_CPU_SET_UNASSIGNED_10_SHIFT 10
-#define BCHP_PCIE_0_INTR2_CPU_SET_UNASSIGNED_10_DEFAULT 0x00000000
-
-/* PCIE_0_INTR2 :: CPU_SET :: PCIE_TGT_BAD_ACCESS [09:09] */
-#define BCHP_PCIE_0_INTR2_CPU_SET_PCIE_TGT_BAD_ACCESS_MASK 0x00000200
-#define BCHP_PCIE_0_INTR2_CPU_SET_PCIE_TGT_BAD_ACCESS_SHIFT 9
-#define BCHP_PCIE_0_INTR2_CPU_SET_PCIE_TGT_BAD_ACCESS_DEFAULT 0x00000000
-
-/* PCIE_0_INTR2 :: CPU_SET :: PCIE_TGT_BAD_ADDRESS [08:08] */
-#define BCHP_PCIE_0_INTR2_CPU_SET_PCIE_TGT_BAD_ADDRESS_MASK 0x00000100
-#define BCHP_PCIE_0_INTR2_CPU_SET_PCIE_TGT_BAD_ADDRESS_SHIFT 8
-#define BCHP_PCIE_0_INTR2_CPU_SET_PCIE_TGT_BAD_ADDRESS_DEFAULT 0x00000000
-
-/* PCIE_0_INTR2 :: CPU_SET :: L1_RX_DMA_ERR_INTR [07:07] */
-#define BCHP_PCIE_0_INTR2_CPU_SET_L1_RX_DMA_ERR_INTR_MASK 0x00000080
-#define BCHP_PCIE_0_INTR2_CPU_SET_L1_RX_DMA_ERR_INTR_SHIFT 7
-#define BCHP_PCIE_0_INTR2_CPU_SET_L1_RX_DMA_ERR_INTR_DEFAULT 0x00000000
-
-/* PCIE_0_INTR2 :: CPU_SET :: L1_RX_DMA_DONE_INTR [06:06] */
-#define BCHP_PCIE_0_INTR2_CPU_SET_L1_RX_DMA_DONE_INTR_MASK 0x00000040
-#define BCHP_PCIE_0_INTR2_CPU_SET_L1_RX_DMA_DONE_INTR_SHIFT 6
-#define BCHP_PCIE_0_INTR2_CPU_SET_L1_RX_DMA_DONE_INTR_DEFAULT 0x00000000
-
-/* PCIE_0_INTR2 :: CPU_SET :: L1_TX_DMA_ERR_INTR [05:05] */
-#define BCHP_PCIE_0_INTR2_CPU_SET_L1_TX_DMA_ERR_INTR_MASK 0x00000020
-#define BCHP_PCIE_0_INTR2_CPU_SET_L1_TX_DMA_ERR_INTR_SHIFT 5
-#define BCHP_PCIE_0_INTR2_CPU_SET_L1_TX_DMA_ERR_INTR_DEFAULT 0x00000000
-
-/* PCIE_0_INTR2 :: CPU_SET :: L1_TX_DMA_DONE_INTR [04:04] */
-#define BCHP_PCIE_0_INTR2_CPU_SET_L1_TX_DMA_DONE_INTR_MASK 0x00000010
-#define BCHP_PCIE_0_INTR2_CPU_SET_L1_TX_DMA_DONE_INTR_SHIFT 4
-#define BCHP_PCIE_0_INTR2_CPU_SET_L1_TX_DMA_DONE_INTR_DEFAULT 0x00000000
-
-/* PCIE_0_INTR2 :: CPU_SET :: L0_RX_DMA_ERR_INTR [03:03] */
-#define BCHP_PCIE_0_INTR2_CPU_SET_L0_RX_DMA_ERR_INTR_MASK 0x00000008
-#define BCHP_PCIE_0_INTR2_CPU_SET_L0_RX_DMA_ERR_INTR_SHIFT 3
-#define BCHP_PCIE_0_INTR2_CPU_SET_L0_RX_DMA_ERR_INTR_DEFAULT 0x00000000
-
-/* PCIE_0_INTR2 :: CPU_SET :: L0_RX_DMA_DONE_INTR [02:02] */
-#define BCHP_PCIE_0_INTR2_CPU_SET_L0_RX_DMA_DONE_INTR_MASK 0x00000004
-#define BCHP_PCIE_0_INTR2_CPU_SET_L0_RX_DMA_DONE_INTR_SHIFT 2
-#define BCHP_PCIE_0_INTR2_CPU_SET_L0_RX_DMA_DONE_INTR_DEFAULT 0x00000000
-
-/* PCIE_0_INTR2 :: CPU_SET :: L0_TX_DMA_ERR_INTR [01:01] */
-#define BCHP_PCIE_0_INTR2_CPU_SET_L0_TX_DMA_ERR_INTR_MASK 0x00000002
-#define BCHP_PCIE_0_INTR2_CPU_SET_L0_TX_DMA_ERR_INTR_SHIFT 1
-#define BCHP_PCIE_0_INTR2_CPU_SET_L0_TX_DMA_ERR_INTR_DEFAULT 0x00000000
-
-/* PCIE_0_INTR2 :: CPU_SET :: L0_TX_DMA_DONE_INTR [00:00] */
-#define BCHP_PCIE_0_INTR2_CPU_SET_L0_TX_DMA_DONE_INTR_MASK 0x00000001
-#define BCHP_PCIE_0_INTR2_CPU_SET_L0_TX_DMA_DONE_INTR_SHIFT 0
-#define BCHP_PCIE_0_INTR2_CPU_SET_L0_TX_DMA_DONE_INTR_DEFAULT 0x00000000
-
-/***************************************************************************
- *CPU_CLEAR - CPU interrupt Clear Register
- ***************************************************************************/
-/* PCIE_0_INTR2 :: CPU_CLEAR :: MSI_INTR07 [31:31] */
-#define BCHP_PCIE_0_INTR2_CPU_CLEAR_MSI_INTR07_MASK 0x80000000
-#define BCHP_PCIE_0_INTR2_CPU_CLEAR_MSI_INTR07_SHIFT 31
-#define BCHP_PCIE_0_INTR2_CPU_CLEAR_MSI_INTR07_DEFAULT 0x00000000
-
-/* PCIE_0_INTR2 :: CPU_CLEAR :: MSI_INTR06 [30:30] */
-#define BCHP_PCIE_0_INTR2_CPU_CLEAR_MSI_INTR06_MASK 0x40000000
-#define BCHP_PCIE_0_INTR2_CPU_CLEAR_MSI_INTR06_SHIFT 30
-#define BCHP_PCIE_0_INTR2_CPU_CLEAR_MSI_INTR06_DEFAULT 0x00000000
-
-/* PCIE_0_INTR2 :: CPU_CLEAR :: MSI_INTR05 [29:29] */
-#define BCHP_PCIE_0_INTR2_CPU_CLEAR_MSI_INTR05_MASK 0x20000000
-#define BCHP_PCIE_0_INTR2_CPU_CLEAR_MSI_INTR05_SHIFT 29
-#define BCHP_PCIE_0_INTR2_CPU_CLEAR_MSI_INTR05_DEFAULT 0x00000000
-
-/* PCIE_0_INTR2 :: CPU_CLEAR :: MSI_INTR04 [28:28] */
-#define BCHP_PCIE_0_INTR2_CPU_CLEAR_MSI_INTR04_MASK 0x10000000
-#define BCHP_PCIE_0_INTR2_CPU_CLEAR_MSI_INTR04_SHIFT 28
-#define BCHP_PCIE_0_INTR2_CPU_CLEAR_MSI_INTR04_DEFAULT 0x00000000
-
-/* PCIE_0_INTR2 :: CPU_CLEAR :: MSI_INTR03 [27:27] */
-#define BCHP_PCIE_0_INTR2_CPU_CLEAR_MSI_INTR03_MASK 0x08000000
-#define BCHP_PCIE_0_INTR2_CPU_CLEAR_MSI_INTR03_SHIFT 27
-#define BCHP_PCIE_0_INTR2_CPU_CLEAR_MSI_INTR03_DEFAULT 0x00000000
-
-/* PCIE_0_INTR2 :: CPU_CLEAR :: MSI_INTR02 [26:26] */
-#define BCHP_PCIE_0_INTR2_CPU_CLEAR_MSI_INTR02_MASK 0x04000000
-#define BCHP_PCIE_0_INTR2_CPU_CLEAR_MSI_INTR02_SHIFT 26
-#define BCHP_PCIE_0_INTR2_CPU_CLEAR_MSI_INTR02_DEFAULT 0x00000000
-
-/* PCIE_0_INTR2 :: CPU_CLEAR :: MSI_INTR01 [25:25] */
-#define BCHP_PCIE_0_INTR2_CPU_CLEAR_MSI_INTR01_MASK 0x02000000
-#define BCHP_PCIE_0_INTR2_CPU_CLEAR_MSI_INTR01_SHIFT 25
-#define BCHP_PCIE_0_INTR2_CPU_CLEAR_MSI_INTR01_DEFAULT 0x00000000
-
-/* PCIE_0_INTR2 :: CPU_CLEAR :: MSI_INTR00 [24:24] */
-#define BCHP_PCIE_0_INTR2_CPU_CLEAR_MSI_INTR00_MASK 0x01000000
-#define BCHP_PCIE_0_INTR2_CPU_CLEAR_MSI_INTR00_SHIFT 24
-#define BCHP_PCIE_0_INTR2_CPU_CLEAR_MSI_INTR00_DEFAULT 0x00000000
-
-/* PCIE_0_INTR2 :: CPU_CLEAR :: UNASSIGNED_23 [23:23] */
-#define BCHP_PCIE_0_INTR2_CPU_CLEAR_UNASSIGNED_23_MASK 0x00800000
-#define BCHP_PCIE_0_INTR2_CPU_CLEAR_UNASSIGNED_23_SHIFT 23
-#define BCHP_PCIE_0_INTR2_CPU_CLEAR_UNASSIGNED_23_DEFAULT 0x00000000
-
-/* PCIE_0_INTR2 :: CPU_CLEAR :: UNASSIGNED_22 [22:22] */
-#define BCHP_PCIE_0_INTR2_CPU_CLEAR_UNASSIGNED_22_MASK 0x00400000
-#define BCHP_PCIE_0_INTR2_CPU_CLEAR_UNASSIGNED_22_SHIFT 22
-#define BCHP_PCIE_0_INTR2_CPU_CLEAR_UNASSIGNED_22_DEFAULT 0x00000000
-
-/* PCIE_0_INTR2 :: CPU_CLEAR :: UNASSIGNED_21 [21:21] */
-#define BCHP_PCIE_0_INTR2_CPU_CLEAR_UNASSIGNED_21_MASK 0x00200000
-#define BCHP_PCIE_0_INTR2_CPU_CLEAR_UNASSIGNED_21_SHIFT 21
-#define BCHP_PCIE_0_INTR2_CPU_CLEAR_UNASSIGNED_21_DEFAULT 0x00000000
-
-/* PCIE_0_INTR2 :: CPU_CLEAR :: UNASSIGNED_20 [20:20] */
-#define BCHP_PCIE_0_INTR2_CPU_CLEAR_UNASSIGNED_20_MASK 0x00100000
-#define BCHP_PCIE_0_INTR2_CPU_CLEAR_UNASSIGNED_20_SHIFT 20
-#define BCHP_PCIE_0_INTR2_CPU_CLEAR_UNASSIGNED_20_DEFAULT 0x00000000
-
-/* PCIE_0_INTR2 :: CPU_CLEAR :: MAILBOX_3 [19:19] */
-#define BCHP_PCIE_0_INTR2_CPU_CLEAR_MAILBOX_3_MASK 0x00080000
-#define BCHP_PCIE_0_INTR2_CPU_CLEAR_MAILBOX_3_SHIFT 19
-#define BCHP_PCIE_0_INTR2_CPU_CLEAR_MAILBOX_3_DEFAULT 0x00000000
-
-/* PCIE_0_INTR2 :: CPU_CLEAR :: MAILBOX_2 [18:18] */
-#define BCHP_PCIE_0_INTR2_CPU_CLEAR_MAILBOX_2_MASK 0x00040000
-#define BCHP_PCIE_0_INTR2_CPU_CLEAR_MAILBOX_2_SHIFT 18
-#define BCHP_PCIE_0_INTR2_CPU_CLEAR_MAILBOX_2_DEFAULT 0x00000000
-
-/* PCIE_0_INTR2 :: CPU_CLEAR :: MAILBOX_1 [17:17] */
-#define BCHP_PCIE_0_INTR2_CPU_CLEAR_MAILBOX_1_MASK 0x00020000
-#define BCHP_PCIE_0_INTR2_CPU_CLEAR_MAILBOX_1_SHIFT 17
-#define BCHP_PCIE_0_INTR2_CPU_CLEAR_MAILBOX_1_DEFAULT 0x00000000
-
-/* PCIE_0_INTR2 :: CPU_CLEAR :: MAILBOX_0 [16:16] */
-#define BCHP_PCIE_0_INTR2_CPU_CLEAR_MAILBOX_0_MASK 0x00010000
-#define BCHP_PCIE_0_INTR2_CPU_CLEAR_MAILBOX_0_SHIFT 16
-#define BCHP_PCIE_0_INTR2_CPU_CLEAR_MAILBOX_0_DEFAULT 0x00000000
-
-/* PCIE_0_INTR2 :: CPU_CLEAR :: PCIE_MSTR_FWD_ERR [15:15] */
-#define BCHP_PCIE_0_INTR2_CPU_CLEAR_PCIE_MSTR_FWD_ERR_MASK 0x00008000
-#define BCHP_PCIE_0_INTR2_CPU_CLEAR_PCIE_MSTR_FWD_ERR_SHIFT 15
-#define BCHP_PCIE_0_INTR2_CPU_CLEAR_PCIE_MSTR_FWD_ERR_DEFAULT 0x00000000
-
-/* PCIE_0_INTR2 :: CPU_CLEAR :: PCIE_MSTR_RETRY_TIMEOUT [14:14] */
-#define BCHP_PCIE_0_INTR2_CPU_CLEAR_PCIE_MSTR_RETRY_TIMEOUT_MASK 0x00004000
-#define BCHP_PCIE_0_INTR2_CPU_CLEAR_PCIE_MSTR_RETRY_TIMEOUT_SHIFT 14
-#define BCHP_PCIE_0_INTR2_CPU_CLEAR_PCIE_MSTR_RETRY_TIMEOUT_DEFAULT 0x00000000
-
-/* PCIE_0_INTR2 :: CPU_CLEAR :: PCIE_MSTR_CA_ATTN [13:13] */
-#define BCHP_PCIE_0_INTR2_CPU_CLEAR_PCIE_MSTR_CA_ATTN_MASK 0x00002000
-#define BCHP_PCIE_0_INTR2_CPU_CLEAR_PCIE_MSTR_CA_ATTN_SHIFT 13
-#define BCHP_PCIE_0_INTR2_CPU_CLEAR_PCIE_MSTR_CA_ATTN_DEFAULT 0x00000000
-
-/* PCIE_0_INTR2 :: CPU_CLEAR :: PCIE_MSTR_UR_ATTN [12:12] */
-#define BCHP_PCIE_0_INTR2_CPU_CLEAR_PCIE_MSTR_UR_ATTN_MASK 0x00001000
-#define BCHP_PCIE_0_INTR2_CPU_CLEAR_PCIE_MSTR_UR_ATTN_SHIFT 12
-#define BCHP_PCIE_0_INTR2_CPU_CLEAR_PCIE_MSTR_UR_ATTN_DEFAULT 0x00000000
-
-/* PCIE_0_INTR2 :: CPU_CLEAR :: UNASSIGNED_11 [11:11] */
-#define BCHP_PCIE_0_INTR2_CPU_CLEAR_UNASSIGNED_11_MASK 0x00000800
-#define BCHP_PCIE_0_INTR2_CPU_CLEAR_UNASSIGNED_11_SHIFT 11
-#define BCHP_PCIE_0_INTR2_CPU_CLEAR_UNASSIGNED_11_DEFAULT 0x00000000
-
-/* PCIE_0_INTR2 :: CPU_CLEAR :: UNASSIGNED_10 [10:10] */
-#define BCHP_PCIE_0_INTR2_CPU_CLEAR_UNASSIGNED_10_MASK 0x00000400
-#define BCHP_PCIE_0_INTR2_CPU_CLEAR_UNASSIGNED_10_SHIFT 10
-#define BCHP_PCIE_0_INTR2_CPU_CLEAR_UNASSIGNED_10_DEFAULT 0x00000000
-
-/* PCIE_0_INTR2 :: CPU_CLEAR :: PCIE_TGT_BAD_ACCESS [09:09] */
-#define BCHP_PCIE_0_INTR2_CPU_CLEAR_PCIE_TGT_BAD_ACCESS_MASK 0x00000200
-#define BCHP_PCIE_0_INTR2_CPU_CLEAR_PCIE_TGT_BAD_ACCESS_SHIFT 9
-#define BCHP_PCIE_0_INTR2_CPU_CLEAR_PCIE_TGT_BAD_ACCESS_DEFAULT 0x00000000
-
-/* PCIE_0_INTR2 :: CPU_CLEAR :: PCIE_TGT_BAD_ADDRESS [08:08] */
-#define BCHP_PCIE_0_INTR2_CPU_CLEAR_PCIE_TGT_BAD_ADDRESS_MASK 0x00000100
-#define BCHP_PCIE_0_INTR2_CPU_CLEAR_PCIE_TGT_BAD_ADDRESS_SHIFT 8
-#define BCHP_PCIE_0_INTR2_CPU_CLEAR_PCIE_TGT_BAD_ADDRESS_DEFAULT 0x00000000
-
-/* PCIE_0_INTR2 :: CPU_CLEAR :: L1_RX_DMA_ERR_INTR [07:07] */
-#define BCHP_PCIE_0_INTR2_CPU_CLEAR_L1_RX_DMA_ERR_INTR_MASK 0x00000080
-#define BCHP_PCIE_0_INTR2_CPU_CLEAR_L1_RX_DMA_ERR_INTR_SHIFT 7
-#define BCHP_PCIE_0_INTR2_CPU_CLEAR_L1_RX_DMA_ERR_INTR_DEFAULT 0x00000000
-
-/* PCIE_0_INTR2 :: CPU_CLEAR :: L1_RX_DMA_DONE_INTR [06:06] */
-#define BCHP_PCIE_0_INTR2_CPU_CLEAR_L1_RX_DMA_DONE_INTR_MASK 0x00000040
-#define BCHP_PCIE_0_INTR2_CPU_CLEAR_L1_RX_DMA_DONE_INTR_SHIFT 6
-#define BCHP_PCIE_0_INTR2_CPU_CLEAR_L1_RX_DMA_DONE_INTR_DEFAULT 0x00000000
-
-/* PCIE_0_INTR2 :: CPU_CLEAR :: L1_TX_DMA_ERR_INTR [05:05] */
-#define BCHP_PCIE_0_INTR2_CPU_CLEAR_L1_TX_DMA_ERR_INTR_MASK 0x00000020
-#define BCHP_PCIE_0_INTR2_CPU_CLEAR_L1_TX_DMA_ERR_INTR_SHIFT 5
-#define BCHP_PCIE_0_INTR2_CPU_CLEAR_L1_TX_DMA_ERR_INTR_DEFAULT 0x00000000
-
-/* PCIE_0_INTR2 :: CPU_CLEAR :: L1_TX_DMA_DONE_INTR [04:04] */
-#define BCHP_PCIE_0_INTR2_CPU_CLEAR_L1_TX_DMA_DONE_INTR_MASK 0x00000010
-#define BCHP_PCIE_0_INTR2_CPU_CLEAR_L1_TX_DMA_DONE_INTR_SHIFT 4
-#define BCHP_PCIE_0_INTR2_CPU_CLEAR_L1_TX_DMA_DONE_INTR_DEFAULT 0x00000000
-
-/* PCIE_0_INTR2 :: CPU_CLEAR :: L0_RX_DMA_ERR_INTR [03:03] */
-#define BCHP_PCIE_0_INTR2_CPU_CLEAR_L0_RX_DMA_ERR_INTR_MASK 0x00000008
-#define BCHP_PCIE_0_INTR2_CPU_CLEAR_L0_RX_DMA_ERR_INTR_SHIFT 3
-#define BCHP_PCIE_0_INTR2_CPU_CLEAR_L0_RX_DMA_ERR_INTR_DEFAULT 0x00000000
-
-/* PCIE_0_INTR2 :: CPU_CLEAR :: L0_RX_DMA_DONE_INTR [02:02] */
-#define BCHP_PCIE_0_INTR2_CPU_CLEAR_L0_RX_DMA_DONE_INTR_MASK 0x00000004
-#define BCHP_PCIE_0_INTR2_CPU_CLEAR_L0_RX_DMA_DONE_INTR_SHIFT 2
-#define BCHP_PCIE_0_INTR2_CPU_CLEAR_L0_RX_DMA_DONE_INTR_DEFAULT 0x00000000
-
-/* PCIE_0_INTR2 :: CPU_CLEAR :: L0_TX_DMA_ERR_INTR [01:01] */
-#define BCHP_PCIE_0_INTR2_CPU_CLEAR_L0_TX_DMA_ERR_INTR_MASK 0x00000002
-#define BCHP_PCIE_0_INTR2_CPU_CLEAR_L0_TX_DMA_ERR_INTR_SHIFT 1
-#define BCHP_PCIE_0_INTR2_CPU_CLEAR_L0_TX_DMA_ERR_INTR_DEFAULT 0x00000000
-
-/* PCIE_0_INTR2 :: CPU_CLEAR :: L0_TX_DMA_DONE_INTR [00:00] */
-#define BCHP_PCIE_0_INTR2_CPU_CLEAR_L0_TX_DMA_DONE_INTR_MASK 0x00000001
-#define BCHP_PCIE_0_INTR2_CPU_CLEAR_L0_TX_DMA_DONE_INTR_SHIFT 0
-#define BCHP_PCIE_0_INTR2_CPU_CLEAR_L0_TX_DMA_DONE_INTR_DEFAULT 0x00000000
-
-/***************************************************************************
- *CPU_MASK_STATUS - CPU interrupt Mask Status Register
- ***************************************************************************/
-/* PCIE_0_INTR2 :: CPU_MASK_STATUS :: MSI_INTR07 [31:31] */
-#define BCHP_PCIE_0_INTR2_CPU_MASK_STATUS_MSI_INTR07_MASK 0x80000000
-#define BCHP_PCIE_0_INTR2_CPU_MASK_STATUS_MSI_INTR07_SHIFT 31
-#define BCHP_PCIE_0_INTR2_CPU_MASK_STATUS_MSI_INTR07_DEFAULT 0x00000001
-
-/* PCIE_0_INTR2 :: CPU_MASK_STATUS :: MSI_INTR06 [30:30] */
-#define BCHP_PCIE_0_INTR2_CPU_MASK_STATUS_MSI_INTR06_MASK 0x40000000
-#define BCHP_PCIE_0_INTR2_CPU_MASK_STATUS_MSI_INTR06_SHIFT 30
-#define BCHP_PCIE_0_INTR2_CPU_MASK_STATUS_MSI_INTR06_DEFAULT 0x00000001
-
-/* PCIE_0_INTR2 :: CPU_MASK_STATUS :: MSI_INTR05 [29:29] */
-#define BCHP_PCIE_0_INTR2_CPU_MASK_STATUS_MSI_INTR05_MASK 0x20000000
-#define BCHP_PCIE_0_INTR2_CPU_MASK_STATUS_MSI_INTR05_SHIFT 29
-#define BCHP_PCIE_0_INTR2_CPU_MASK_STATUS_MSI_INTR05_DEFAULT 0x00000001
-
-/* PCIE_0_INTR2 :: CPU_MASK_STATUS :: MSI_INTR04 [28:28] */
-#define BCHP_PCIE_0_INTR2_CPU_MASK_STATUS_MSI_INTR04_MASK 0x10000000
-#define BCHP_PCIE_0_INTR2_CPU_MASK_STATUS_MSI_INTR04_SHIFT 28
-#define BCHP_PCIE_0_INTR2_CPU_MASK_STATUS_MSI_INTR04_DEFAULT 0x00000001
-
-/* PCIE_0_INTR2 :: CPU_MASK_STATUS :: MSI_INTR03 [27:27] */
-#define BCHP_PCIE_0_INTR2_CPU_MASK_STATUS_MSI_INTR03_MASK 0x08000000
-#define BCHP_PCIE_0_INTR2_CPU_MASK_STATUS_MSI_INTR03_SHIFT 27
-#define BCHP_PCIE_0_INTR2_CPU_MASK_STATUS_MSI_INTR03_DEFAULT 0x00000001
-
-/* PCIE_0_INTR2 :: CPU_MASK_STATUS :: MSI_INTR02 [26:26] */
-#define BCHP_PCIE_0_INTR2_CPU_MASK_STATUS_MSI_INTR02_MASK 0x04000000
-#define BCHP_PCIE_0_INTR2_CPU_MASK_STATUS_MSI_INTR02_SHIFT 26
-#define BCHP_PCIE_0_INTR2_CPU_MASK_STATUS_MSI_INTR02_DEFAULT 0x00000001
-
-/* PCIE_0_INTR2 :: CPU_MASK_STATUS :: MSI_INTR01 [25:25] */
-#define BCHP_PCIE_0_INTR2_CPU_MASK_STATUS_MSI_INTR01_MASK 0x02000000
-#define BCHP_PCIE_0_INTR2_CPU_MASK_STATUS_MSI_INTR01_SHIFT 25
-#define BCHP_PCIE_0_INTR2_CPU_MASK_STATUS_MSI_INTR01_DEFAULT 0x00000001
-
-/* PCIE_0_INTR2 :: CPU_MASK_STATUS :: MSI_INTR00 [24:24] */
-#define BCHP_PCIE_0_INTR2_CPU_MASK_STATUS_MSI_INTR00_MASK 0x01000000
-#define BCHP_PCIE_0_INTR2_CPU_MASK_STATUS_MSI_INTR00_SHIFT 24
-#define BCHP_PCIE_0_INTR2_CPU_MASK_STATUS_MSI_INTR00_DEFAULT 0x00000001
-
-/* PCIE_0_INTR2 :: CPU_MASK_STATUS :: UNASSIGNED_23 [23:23] */
-#define BCHP_PCIE_0_INTR2_CPU_MASK_STATUS_UNASSIGNED_23_MASK 0x00800000
-#define BCHP_PCIE_0_INTR2_CPU_MASK_STATUS_UNASSIGNED_23_SHIFT 23
-#define BCHP_PCIE_0_INTR2_CPU_MASK_STATUS_UNASSIGNED_23_DEFAULT 0x00000001
-
-/* PCIE_0_INTR2 :: CPU_MASK_STATUS :: UNASSIGNED_22 [22:22] */
-#define BCHP_PCIE_0_INTR2_CPU_MASK_STATUS_UNASSIGNED_22_MASK 0x00400000
-#define BCHP_PCIE_0_INTR2_CPU_MASK_STATUS_UNASSIGNED_22_SHIFT 22
-#define BCHP_PCIE_0_INTR2_CPU_MASK_STATUS_UNASSIGNED_22_DEFAULT 0x00000001
-
-/* PCIE_0_INTR2 :: CPU_MASK_STATUS :: UNASSIGNED_21 [21:21] */
-#define BCHP_PCIE_0_INTR2_CPU_MASK_STATUS_UNASSIGNED_21_MASK 0x00200000
-#define BCHP_PCIE_0_INTR2_CPU_MASK_STATUS_UNASSIGNED_21_SHIFT 21
-#define BCHP_PCIE_0_INTR2_CPU_MASK_STATUS_UNASSIGNED_21_DEFAULT 0x00000001
-
-/* PCIE_0_INTR2 :: CPU_MASK_STATUS :: UNASSIGNED_20 [20:20] */
-#define BCHP_PCIE_0_INTR2_CPU_MASK_STATUS_UNASSIGNED_20_MASK 0x00100000
-#define BCHP_PCIE_0_INTR2_CPU_MASK_STATUS_UNASSIGNED_20_SHIFT 20
-#define BCHP_PCIE_0_INTR2_CPU_MASK_STATUS_UNASSIGNED_20_DEFAULT 0x00000001
-
-/* PCIE_0_INTR2 :: CPU_MASK_STATUS :: MAILBOX_3 [19:19] */
-#define BCHP_PCIE_0_INTR2_CPU_MASK_STATUS_MAILBOX_3_MASK 0x00080000
-#define BCHP_PCIE_0_INTR2_CPU_MASK_STATUS_MAILBOX_3_SHIFT 19
-#define BCHP_PCIE_0_INTR2_CPU_MASK_STATUS_MAILBOX_3_DEFAULT 0x00000001
-
-/* PCIE_0_INTR2 :: CPU_MASK_STATUS :: MAILBOX_2 [18:18] */
-#define BCHP_PCIE_0_INTR2_CPU_MASK_STATUS_MAILBOX_2_MASK 0x00040000
-#define BCHP_PCIE_0_INTR2_CPU_MASK_STATUS_MAILBOX_2_SHIFT 18
-#define BCHP_PCIE_0_INTR2_CPU_MASK_STATUS_MAILBOX_2_DEFAULT 0x00000001
-
-/* PCIE_0_INTR2 :: CPU_MASK_STATUS :: MAILBOX_1 [17:17] */
-#define BCHP_PCIE_0_INTR2_CPU_MASK_STATUS_MAILBOX_1_MASK 0x00020000
-#define BCHP_PCIE_0_INTR2_CPU_MASK_STATUS_MAILBOX_1_SHIFT 17
-#define BCHP_PCIE_0_INTR2_CPU_MASK_STATUS_MAILBOX_1_DEFAULT 0x00000001
-
-/* PCIE_0_INTR2 :: CPU_MASK_STATUS :: MAILBOX_0 [16:16] */
-#define BCHP_PCIE_0_INTR2_CPU_MASK_STATUS_MAILBOX_0_MASK 0x00010000
-#define BCHP_PCIE_0_INTR2_CPU_MASK_STATUS_MAILBOX_0_SHIFT 16
-#define BCHP_PCIE_0_INTR2_CPU_MASK_STATUS_MAILBOX_0_DEFAULT 0x00000001
-
-/* PCIE_0_INTR2 :: CPU_MASK_STATUS :: PCIE_MSTR_FWD_ERR [15:15] */
-#define BCHP_PCIE_0_INTR2_CPU_MASK_STATUS_PCIE_MSTR_FWD_ERR_MASK 0x00008000
-#define BCHP_PCIE_0_INTR2_CPU_MASK_STATUS_PCIE_MSTR_FWD_ERR_SHIFT 15
-#define BCHP_PCIE_0_INTR2_CPU_MASK_STATUS_PCIE_MSTR_FWD_ERR_DEFAULT 0x00000001
-
-/* PCIE_0_INTR2 :: CPU_MASK_STATUS :: PCIE_MSTR_RETRY_TIMEOUT [14:14] */
-#define BCHP_PCIE_0_INTR2_CPU_MASK_STATUS_PCIE_MSTR_RETRY_TIMEOUT_MASK 0x00004000
-#define BCHP_PCIE_0_INTR2_CPU_MASK_STATUS_PCIE_MSTR_RETRY_TIMEOUT_SHIFT 14
-#define BCHP_PCIE_0_INTR2_CPU_MASK_STATUS_PCIE_MSTR_RETRY_TIMEOUT_DEFAULT 0x00000001
-
-/* PCIE_0_INTR2 :: CPU_MASK_STATUS :: PCIE_MSTR_CA_ATTN [13:13] */
-#define BCHP_PCIE_0_INTR2_CPU_MASK_STATUS_PCIE_MSTR_CA_ATTN_MASK 0x00002000
-#define BCHP_PCIE_0_INTR2_CPU_MASK_STATUS_PCIE_MSTR_CA_ATTN_SHIFT 13
-#define BCHP_PCIE_0_INTR2_CPU_MASK_STATUS_PCIE_MSTR_CA_ATTN_DEFAULT 0x00000001
-
-/* PCIE_0_INTR2 :: CPU_MASK_STATUS :: PCIE_MSTR_UR_ATTN [12:12] */
-#define BCHP_PCIE_0_INTR2_CPU_MASK_STATUS_PCIE_MSTR_UR_ATTN_MASK 0x00001000
-#define BCHP_PCIE_0_INTR2_CPU_MASK_STATUS_PCIE_MSTR_UR_ATTN_SHIFT 12
-#define BCHP_PCIE_0_INTR2_CPU_MASK_STATUS_PCIE_MSTR_UR_ATTN_DEFAULT 0x00000001
-
-/* PCIE_0_INTR2 :: CPU_MASK_STATUS :: UNASSIGNED_11 [11:11] */
-#define BCHP_PCIE_0_INTR2_CPU_MASK_STATUS_UNASSIGNED_11_MASK 0x00000800
-#define BCHP_PCIE_0_INTR2_CPU_MASK_STATUS_UNASSIGNED_11_SHIFT 11
-#define BCHP_PCIE_0_INTR2_CPU_MASK_STATUS_UNASSIGNED_11_DEFAULT 0x00000001
-
-/* PCIE_0_INTR2 :: CPU_MASK_STATUS :: UNASSIGNED_10 [10:10] */
-#define BCHP_PCIE_0_INTR2_CPU_MASK_STATUS_UNASSIGNED_10_MASK 0x00000400
-#define BCHP_PCIE_0_INTR2_CPU_MASK_STATUS_UNASSIGNED_10_SHIFT 10
-#define BCHP_PCIE_0_INTR2_CPU_MASK_STATUS_UNASSIGNED_10_DEFAULT 0x00000001
-
-/* PCIE_0_INTR2 :: CPU_MASK_STATUS :: PCIE_TGT_BAD_ACCESS [09:09] */
-#define BCHP_PCIE_0_INTR2_CPU_MASK_STATUS_PCIE_TGT_BAD_ACCESS_MASK 0x00000200
-#define BCHP_PCIE_0_INTR2_CPU_MASK_STATUS_PCIE_TGT_BAD_ACCESS_SHIFT 9
-#define BCHP_PCIE_0_INTR2_CPU_MASK_STATUS_PCIE_TGT_BAD_ACCESS_DEFAULT 0x00000001
-
-/* PCIE_0_INTR2 :: CPU_MASK_STATUS :: PCIE_TGT_BAD_ADDRESS [08:08] */
-#define BCHP_PCIE_0_INTR2_CPU_MASK_STATUS_PCIE_TGT_BAD_ADDRESS_MASK 0x00000100
-#define BCHP_PCIE_0_INTR2_CPU_MASK_STATUS_PCIE_TGT_BAD_ADDRESS_SHIFT 8
-#define BCHP_PCIE_0_INTR2_CPU_MASK_STATUS_PCIE_TGT_BAD_ADDRESS_DEFAULT 0x00000001
-
-/* PCIE_0_INTR2 :: CPU_MASK_STATUS :: L1_RX_DMA_ERR_INTR [07:07] */
-#define BCHP_PCIE_0_INTR2_CPU_MASK_STATUS_L1_RX_DMA_ERR_INTR_MASK 0x00000080
-#define BCHP_PCIE_0_INTR2_CPU_MASK_STATUS_L1_RX_DMA_ERR_INTR_SHIFT 7
-#define BCHP_PCIE_0_INTR2_CPU_MASK_STATUS_L1_RX_DMA_ERR_INTR_DEFAULT 0x00000001
-
-/* PCIE_0_INTR2 :: CPU_MASK_STATUS :: L1_RX_DMA_DONE_INTR [06:06] */
-#define BCHP_PCIE_0_INTR2_CPU_MASK_STATUS_L1_RX_DMA_DONE_INTR_MASK 0x00000040
-#define BCHP_PCIE_0_INTR2_CPU_MASK_STATUS_L1_RX_DMA_DONE_INTR_SHIFT 6
-#define BCHP_PCIE_0_INTR2_CPU_MASK_STATUS_L1_RX_DMA_DONE_INTR_DEFAULT 0x00000001
-
-/* PCIE_0_INTR2 :: CPU_MASK_STATUS :: L1_TX_DMA_ERR_INTR [05:05] */
-#define BCHP_PCIE_0_INTR2_CPU_MASK_STATUS_L1_TX_DMA_ERR_INTR_MASK 0x00000020
-#define BCHP_PCIE_0_INTR2_CPU_MASK_STATUS_L1_TX_DMA_ERR_INTR_SHIFT 5
-#define BCHP_PCIE_0_INTR2_CPU_MASK_STATUS_L1_TX_DMA_ERR_INTR_DEFAULT 0x00000001
-
-/* PCIE_0_INTR2 :: CPU_MASK_STATUS :: L1_TX_DMA_DONE_INTR [04:04] */
-#define BCHP_PCIE_0_INTR2_CPU_MASK_STATUS_L1_TX_DMA_DONE_INTR_MASK 0x00000010
-#define BCHP_PCIE_0_INTR2_CPU_MASK_STATUS_L1_TX_DMA_DONE_INTR_SHIFT 4
-#define BCHP_PCIE_0_INTR2_CPU_MASK_STATUS_L1_TX_DMA_DONE_INTR_DEFAULT 0x00000001
-
-/* PCIE_0_INTR2 :: CPU_MASK_STATUS :: L0_RX_DMA_ERR_INTR [03:03] */
-#define BCHP_PCIE_0_INTR2_CPU_MASK_STATUS_L0_RX_DMA_ERR_INTR_MASK 0x00000008
-#define BCHP_PCIE_0_INTR2_CPU_MASK_STATUS_L0_RX_DMA_ERR_INTR_SHIFT 3
-#define BCHP_PCIE_0_INTR2_CPU_MASK_STATUS_L0_RX_DMA_ERR_INTR_DEFAULT 0x00000001
-
-/* PCIE_0_INTR2 :: CPU_MASK_STATUS :: L0_RX_DMA_DONE_INTR [02:02] */
-#define BCHP_PCIE_0_INTR2_CPU_MASK_STATUS_L0_RX_DMA_DONE_INTR_MASK 0x00000004
-#define BCHP_PCIE_0_INTR2_CPU_MASK_STATUS_L0_RX_DMA_DONE_INTR_SHIFT 2
-#define BCHP_PCIE_0_INTR2_CPU_MASK_STATUS_L0_RX_DMA_DONE_INTR_DEFAULT 0x00000001
-
-/* PCIE_0_INTR2 :: CPU_MASK_STATUS :: L0_TX_DMA_ERR_INTR [01:01] */
-#define BCHP_PCIE_0_INTR2_CPU_MASK_STATUS_L0_TX_DMA_ERR_INTR_MASK 0x00000002
-#define BCHP_PCIE_0_INTR2_CPU_MASK_STATUS_L0_TX_DMA_ERR_INTR_SHIFT 1
-#define BCHP_PCIE_0_INTR2_CPU_MASK_STATUS_L0_TX_DMA_ERR_INTR_DEFAULT 0x00000001
-
-/* PCIE_0_INTR2 :: CPU_MASK_STATUS :: L0_TX_DMA_DONE_INTR [00:00] */
-#define BCHP_PCIE_0_INTR2_CPU_MASK_STATUS_L0_TX_DMA_DONE_INTR_MASK 0x00000001
-#define BCHP_PCIE_0_INTR2_CPU_MASK_STATUS_L0_TX_DMA_DONE_INTR_SHIFT 0
-#define BCHP_PCIE_0_INTR2_CPU_MASK_STATUS_L0_TX_DMA_DONE_INTR_DEFAULT 0x00000001
-
-/***************************************************************************
- *CPU_MASK_SET - CPU interrupt Mask Set Register
- ***************************************************************************/
-/* PCIE_0_INTR2 :: CPU_MASK_SET :: MSI_INTR07 [31:31] */
-#define BCHP_PCIE_0_INTR2_CPU_MASK_SET_MSI_INTR07_MASK 0x80000000
-#define BCHP_PCIE_0_INTR2_CPU_MASK_SET_MSI_INTR07_SHIFT 31
-#define BCHP_PCIE_0_INTR2_CPU_MASK_SET_MSI_INTR07_DEFAULT 0x00000001
-
-/* PCIE_0_INTR2 :: CPU_MASK_SET :: MSI_INTR06 [30:30] */
-#define BCHP_PCIE_0_INTR2_CPU_MASK_SET_MSI_INTR06_MASK 0x40000000
-#define BCHP_PCIE_0_INTR2_CPU_MASK_SET_MSI_INTR06_SHIFT 30
-#define BCHP_PCIE_0_INTR2_CPU_MASK_SET_MSI_INTR06_DEFAULT 0x00000001
-
-/* PCIE_0_INTR2 :: CPU_MASK_SET :: MSI_INTR05 [29:29] */
-#define BCHP_PCIE_0_INTR2_CPU_MASK_SET_MSI_INTR05_MASK 0x20000000
-#define BCHP_PCIE_0_INTR2_CPU_MASK_SET_MSI_INTR05_SHIFT 29
-#define BCHP_PCIE_0_INTR2_CPU_MASK_SET_MSI_INTR05_DEFAULT 0x00000001
-
-/* PCIE_0_INTR2 :: CPU_MASK_SET :: MSI_INTR04 [28:28] */
-#define BCHP_PCIE_0_INTR2_CPU_MASK_SET_MSI_INTR04_MASK 0x10000000
-#define BCHP_PCIE_0_INTR2_CPU_MASK_SET_MSI_INTR04_SHIFT 28
-#define BCHP_PCIE_0_INTR2_CPU_MASK_SET_MSI_INTR04_DEFAULT 0x00000001
-
-/* PCIE_0_INTR2 :: CPU_MASK_SET :: MSI_INTR03 [27:27] */
-#define BCHP_PCIE_0_INTR2_CPU_MASK_SET_MSI_INTR03_MASK 0x08000000
-#define BCHP_PCIE_0_INTR2_CPU_MASK_SET_MSI_INTR03_SHIFT 27
-#define BCHP_PCIE_0_INTR2_CPU_MASK_SET_MSI_INTR03_DEFAULT 0x00000001
-
-/* PCIE_0_INTR2 :: CPU_MASK_SET :: MSI_INTR02 [26:26] */
-#define BCHP_PCIE_0_INTR2_CPU_MASK_SET_MSI_INTR02_MASK 0x04000000
-#define BCHP_PCIE_0_INTR2_CPU_MASK_SET_MSI_INTR02_SHIFT 26
-#define BCHP_PCIE_0_INTR2_CPU_MASK_SET_MSI_INTR02_DEFAULT 0x00000001
-
-/* PCIE_0_INTR2 :: CPU_MASK_SET :: MSI_INTR01 [25:25] */
-#define BCHP_PCIE_0_INTR2_CPU_MASK_SET_MSI_INTR01_MASK 0x02000000
-#define BCHP_PCIE_0_INTR2_CPU_MASK_SET_MSI_INTR01_SHIFT 25
-#define BCHP_PCIE_0_INTR2_CPU_MASK_SET_MSI_INTR01_DEFAULT 0x00000001
-
-/* PCIE_0_INTR2 :: CPU_MASK_SET :: MSI_INTR00 [24:24] */
-#define BCHP_PCIE_0_INTR2_CPU_MASK_SET_MSI_INTR00_MASK 0x01000000
-#define BCHP_PCIE_0_INTR2_CPU_MASK_SET_MSI_INTR00_SHIFT 24
-#define BCHP_PCIE_0_INTR2_CPU_MASK_SET_MSI_INTR00_DEFAULT 0x00000001
-
-/* PCIE_0_INTR2 :: CPU_MASK_SET :: UNASSIGNED_23 [23:23] */
-#define BCHP_PCIE_0_INTR2_CPU_MASK_SET_UNASSIGNED_23_MASK 0x00800000
-#define BCHP_PCIE_0_INTR2_CPU_MASK_SET_UNASSIGNED_23_SHIFT 23
-#define BCHP_PCIE_0_INTR2_CPU_MASK_SET_UNASSIGNED_23_DEFAULT 0x00000001
-
-/* PCIE_0_INTR2 :: CPU_MASK_SET :: UNASSIGNED_22 [22:22] */
-#define BCHP_PCIE_0_INTR2_CPU_MASK_SET_UNASSIGNED_22_MASK 0x00400000
-#define BCHP_PCIE_0_INTR2_CPU_MASK_SET_UNASSIGNED_22_SHIFT 22
-#define BCHP_PCIE_0_INTR2_CPU_MASK_SET_UNASSIGNED_22_DEFAULT 0x00000001
-
-/* PCIE_0_INTR2 :: CPU_MASK_SET :: UNASSIGNED_21 [21:21] */
-#define BCHP_PCIE_0_INTR2_CPU_MASK_SET_UNASSIGNED_21_MASK 0x00200000
-#define BCHP_PCIE_0_INTR2_CPU_MASK_SET_UNASSIGNED_21_SHIFT 21
-#define BCHP_PCIE_0_INTR2_CPU_MASK_SET_UNASSIGNED_21_DEFAULT 0x00000001
-
-/* PCIE_0_INTR2 :: CPU_MASK_SET :: UNASSIGNED_20 [20:20] */
-#define BCHP_PCIE_0_INTR2_CPU_MASK_SET_UNASSIGNED_20_MASK 0x00100000
-#define BCHP_PCIE_0_INTR2_CPU_MASK_SET_UNASSIGNED_20_SHIFT 20
-#define BCHP_PCIE_0_INTR2_CPU_MASK_SET_UNASSIGNED_20_DEFAULT 0x00000001
-
-/* PCIE_0_INTR2 :: CPU_MASK_SET :: MAILBOX_3 [19:19] */
-#define BCHP_PCIE_0_INTR2_CPU_MASK_SET_MAILBOX_3_MASK 0x00080000
-#define BCHP_PCIE_0_INTR2_CPU_MASK_SET_MAILBOX_3_SHIFT 19
-#define BCHP_PCIE_0_INTR2_CPU_MASK_SET_MAILBOX_3_DEFAULT 0x00000001
-
-/* PCIE_0_INTR2 :: CPU_MASK_SET :: MAILBOX_2 [18:18] */
-#define BCHP_PCIE_0_INTR2_CPU_MASK_SET_MAILBOX_2_MASK 0x00040000
-#define BCHP_PCIE_0_INTR2_CPU_MASK_SET_MAILBOX_2_SHIFT 18
-#define BCHP_PCIE_0_INTR2_CPU_MASK_SET_MAILBOX_2_DEFAULT 0x00000001
-
-/* PCIE_0_INTR2 :: CPU_MASK_SET :: MAILBOX_1 [17:17] */
-#define BCHP_PCIE_0_INTR2_CPU_MASK_SET_MAILBOX_1_MASK 0x00020000
-#define BCHP_PCIE_0_INTR2_CPU_MASK_SET_MAILBOX_1_SHIFT 17
-#define BCHP_PCIE_0_INTR2_CPU_MASK_SET_MAILBOX_1_DEFAULT 0x00000001
-
-/* PCIE_0_INTR2 :: CPU_MASK_SET :: MAILBOX_0 [16:16] */
-#define BCHP_PCIE_0_INTR2_CPU_MASK_SET_MAILBOX_0_MASK 0x00010000
-#define BCHP_PCIE_0_INTR2_CPU_MASK_SET_MAILBOX_0_SHIFT 16
-#define BCHP_PCIE_0_INTR2_CPU_MASK_SET_MAILBOX_0_DEFAULT 0x00000001
-
-/* PCIE_0_INTR2 :: CPU_MASK_SET :: PCIE_MSTR_FWD_ERR [15:15] */
-#define BCHP_PCIE_0_INTR2_CPU_MASK_SET_PCIE_MSTR_FWD_ERR_MASK 0x00008000
-#define BCHP_PCIE_0_INTR2_CPU_MASK_SET_PCIE_MSTR_FWD_ERR_SHIFT 15
-#define BCHP_PCIE_0_INTR2_CPU_MASK_SET_PCIE_MSTR_FWD_ERR_DEFAULT 0x00000001
-
-/* PCIE_0_INTR2 :: CPU_MASK_SET :: PCIE_MSTR_RETRY_TIMEOUT [14:14] */
-#define BCHP_PCIE_0_INTR2_CPU_MASK_SET_PCIE_MSTR_RETRY_TIMEOUT_MASK 0x00004000
-#define BCHP_PCIE_0_INTR2_CPU_MASK_SET_PCIE_MSTR_RETRY_TIMEOUT_SHIFT 14
-#define BCHP_PCIE_0_INTR2_CPU_MASK_SET_PCIE_MSTR_RETRY_TIMEOUT_DEFAULT 0x00000001
-
-/* PCIE_0_INTR2 :: CPU_MASK_SET :: PCIE_MSTR_CA_ATTN [13:13] */
-#define BCHP_PCIE_0_INTR2_CPU_MASK_SET_PCIE_MSTR_CA_ATTN_MASK 0x00002000
-#define BCHP_PCIE_0_INTR2_CPU_MASK_SET_PCIE_MSTR_CA_ATTN_SHIFT 13
-#define BCHP_PCIE_0_INTR2_CPU_MASK_SET_PCIE_MSTR_CA_ATTN_DEFAULT 0x00000001
-
-/* PCIE_0_INTR2 :: CPU_MASK_SET :: PCIE_MSTR_UR_ATTN [12:12] */
-#define BCHP_PCIE_0_INTR2_CPU_MASK_SET_PCIE_MSTR_UR_ATTN_MASK 0x00001000
-#define BCHP_PCIE_0_INTR2_CPU_MASK_SET_PCIE_MSTR_UR_ATTN_SHIFT 12
-#define BCHP_PCIE_0_INTR2_CPU_MASK_SET_PCIE_MSTR_UR_ATTN_DEFAULT 0x00000001
-
-/* PCIE_0_INTR2 :: CPU_MASK_SET :: UNASSIGNED_11 [11:11] */
-#define BCHP_PCIE_0_INTR2_CPU_MASK_SET_UNASSIGNED_11_MASK 0x00000800
-#define BCHP_PCIE_0_INTR2_CPU_MASK_SET_UNASSIGNED_11_SHIFT 11
-#define BCHP_PCIE_0_INTR2_CPU_MASK_SET_UNASSIGNED_11_DEFAULT 0x00000001
-
-/* PCIE_0_INTR2 :: CPU_MASK_SET :: UNASSIGNED_10 [10:10] */
-#define BCHP_PCIE_0_INTR2_CPU_MASK_SET_UNASSIGNED_10_MASK 0x00000400
-#define BCHP_PCIE_0_INTR2_CPU_MASK_SET_UNASSIGNED_10_SHIFT 10
-#define BCHP_PCIE_0_INTR2_CPU_MASK_SET_UNASSIGNED_10_DEFAULT 0x00000001
-
-/* PCIE_0_INTR2 :: CPU_MASK_SET :: PCIE_TGT_BAD_ACCESS [09:09] */
-#define BCHP_PCIE_0_INTR2_CPU_MASK_SET_PCIE_TGT_BAD_ACCESS_MASK 0x00000200
-#define BCHP_PCIE_0_INTR2_CPU_MASK_SET_PCIE_TGT_BAD_ACCESS_SHIFT 9
-#define BCHP_PCIE_0_INTR2_CPU_MASK_SET_PCIE_TGT_BAD_ACCESS_DEFAULT 0x00000001
-
-/* PCIE_0_INTR2 :: CPU_MASK_SET :: PCIE_TGT_BAD_ADDRESS [08:08] */
-#define BCHP_PCIE_0_INTR2_CPU_MASK_SET_PCIE_TGT_BAD_ADDRESS_MASK 0x00000100
-#define BCHP_PCIE_0_INTR2_CPU_MASK_SET_PCIE_TGT_BAD_ADDRESS_SHIFT 8
-#define BCHP_PCIE_0_INTR2_CPU_MASK_SET_PCIE_TGT_BAD_ADDRESS_DEFAULT 0x00000001
-
-/* PCIE_0_INTR2 :: CPU_MASK_SET :: L1_RX_DMA_ERR_INTR [07:07] */
-#define BCHP_PCIE_0_INTR2_CPU_MASK_SET_L1_RX_DMA_ERR_INTR_MASK 0x00000080
-#define BCHP_PCIE_0_INTR2_CPU_MASK_SET_L1_RX_DMA_ERR_INTR_SHIFT 7
-#define BCHP_PCIE_0_INTR2_CPU_MASK_SET_L1_RX_DMA_ERR_INTR_DEFAULT 0x00000001
-
-/* PCIE_0_INTR2 :: CPU_MASK_SET :: L1_RX_DMA_DONE_INTR [06:06] */
-#define BCHP_PCIE_0_INTR2_CPU_MASK_SET_L1_RX_DMA_DONE_INTR_MASK 0x00000040
-#define BCHP_PCIE_0_INTR2_CPU_MASK_SET_L1_RX_DMA_DONE_INTR_SHIFT 6
-#define BCHP_PCIE_0_INTR2_CPU_MASK_SET_L1_RX_DMA_DONE_INTR_DEFAULT 0x00000001
-
-/* PCIE_0_INTR2 :: CPU_MASK_SET :: L1_TX_DMA_ERR_INTR [05:05] */
-#define BCHP_PCIE_0_INTR2_CPU_MASK_SET_L1_TX_DMA_ERR_INTR_MASK 0x00000020
-#define BCHP_PCIE_0_INTR2_CPU_MASK_SET_L1_TX_DMA_ERR_INTR_SHIFT 5
-#define BCHP_PCIE_0_INTR2_CPU_MASK_SET_L1_TX_DMA_ERR_INTR_DEFAULT 0x00000001
-
-/* PCIE_0_INTR2 :: CPU_MASK_SET :: L1_TX_DMA_DONE_INTR [04:04] */
-#define BCHP_PCIE_0_INTR2_CPU_MASK_SET_L1_TX_DMA_DONE_INTR_MASK 0x00000010
-#define BCHP_PCIE_0_INTR2_CPU_MASK_SET_L1_TX_DMA_DONE_INTR_SHIFT 4
-#define BCHP_PCIE_0_INTR2_CPU_MASK_SET_L1_TX_DMA_DONE_INTR_DEFAULT 0x00000001
-
-/* PCIE_0_INTR2 :: CPU_MASK_SET :: L0_RX_DMA_ERR_INTR [03:03] */
-#define BCHP_PCIE_0_INTR2_CPU_MASK_SET_L0_RX_DMA_ERR_INTR_MASK 0x00000008
-#define BCHP_PCIE_0_INTR2_CPU_MASK_SET_L0_RX_DMA_ERR_INTR_SHIFT 3
-#define BCHP_PCIE_0_INTR2_CPU_MASK_SET_L0_RX_DMA_ERR_INTR_DEFAULT 0x00000001
-
-/* PCIE_0_INTR2 :: CPU_MASK_SET :: L0_RX_DMA_DONE_INTR [02:02] */
-#define BCHP_PCIE_0_INTR2_CPU_MASK_SET_L0_RX_DMA_DONE_INTR_MASK 0x00000004
-#define BCHP_PCIE_0_INTR2_CPU_MASK_SET_L0_RX_DMA_DONE_INTR_SHIFT 2
-#define BCHP_PCIE_0_INTR2_CPU_MASK_SET_L0_RX_DMA_DONE_INTR_DEFAULT 0x00000001
-
-/* PCIE_0_INTR2 :: CPU_MASK_SET :: L0_TX_DMA_ERR_INTR [01:01] */
-#define BCHP_PCIE_0_INTR2_CPU_MASK_SET_L0_TX_DMA_ERR_INTR_MASK 0x00000002
-#define BCHP_PCIE_0_INTR2_CPU_MASK_SET_L0_TX_DMA_ERR_INTR_SHIFT 1
-#define BCHP_PCIE_0_INTR2_CPU_MASK_SET_L0_TX_DMA_ERR_INTR_DEFAULT 0x00000001
-
-/* PCIE_0_INTR2 :: CPU_MASK_SET :: L0_TX_DMA_DONE_INTR [00:00] */
-#define BCHP_PCIE_0_INTR2_CPU_MASK_SET_L0_TX_DMA_DONE_INTR_MASK 0x00000001
-#define BCHP_PCIE_0_INTR2_CPU_MASK_SET_L0_TX_DMA_DONE_INTR_SHIFT 0
-#define BCHP_PCIE_0_INTR2_CPU_MASK_SET_L0_TX_DMA_DONE_INTR_DEFAULT 0x00000001
-
-/***************************************************************************
- *CPU_MASK_CLEAR - CPU interrupt Mask Clear Register
- ***************************************************************************/
-/* PCIE_0_INTR2 :: CPU_MASK_CLEAR :: MSI_INTR07 [31:31] */
-#define BCHP_PCIE_0_INTR2_CPU_MASK_CLEAR_MSI_INTR07_MASK 0x80000000
-#define BCHP_PCIE_0_INTR2_CPU_MASK_CLEAR_MSI_INTR07_SHIFT 31
-#define BCHP_PCIE_0_INTR2_CPU_MASK_CLEAR_MSI_INTR07_DEFAULT 0x00000001
-
-/* PCIE_0_INTR2 :: CPU_MASK_CLEAR :: MSI_INTR06 [30:30] */
-#define BCHP_PCIE_0_INTR2_CPU_MASK_CLEAR_MSI_INTR06_MASK 0x40000000
-#define BCHP_PCIE_0_INTR2_CPU_MASK_CLEAR_MSI_INTR06_SHIFT 30
-#define BCHP_PCIE_0_INTR2_CPU_MASK_CLEAR_MSI_INTR06_DEFAULT 0x00000001
-
-/* PCIE_0_INTR2 :: CPU_MASK_CLEAR :: MSI_INTR05 [29:29] */
-#define BCHP_PCIE_0_INTR2_CPU_MASK_CLEAR_MSI_INTR05_MASK 0x20000000
-#define BCHP_PCIE_0_INTR2_CPU_MASK_CLEAR_MSI_INTR05_SHIFT 29
-#define BCHP_PCIE_0_INTR2_CPU_MASK_CLEAR_MSI_INTR05_DEFAULT 0x00000001
-
-/* PCIE_0_INTR2 :: CPU_MASK_CLEAR :: MSI_INTR04 [28:28] */
-#define BCHP_PCIE_0_INTR2_CPU_MASK_CLEAR_MSI_INTR04_MASK 0x10000000
-#define BCHP_PCIE_0_INTR2_CPU_MASK_CLEAR_MSI_INTR04_SHIFT 28
-#define BCHP_PCIE_0_INTR2_CPU_MASK_CLEAR_MSI_INTR04_DEFAULT 0x00000001
-
-/* PCIE_0_INTR2 :: CPU_MASK_CLEAR :: MSI_INTR03 [27:27] */
-#define BCHP_PCIE_0_INTR2_CPU_MASK_CLEAR_MSI_INTR03_MASK 0x08000000
-#define BCHP_PCIE_0_INTR2_CPU_MASK_CLEAR_MSI_INTR03_SHIFT 27
-#define BCHP_PCIE_0_INTR2_CPU_MASK_CLEAR_MSI_INTR03_DEFAULT 0x00000001
-
-/* PCIE_0_INTR2 :: CPU_MASK_CLEAR :: MSI_INTR02 [26:26] */
-#define BCHP_PCIE_0_INTR2_CPU_MASK_CLEAR_MSI_INTR02_MASK 0x04000000
-#define BCHP_PCIE_0_INTR2_CPU_MASK_CLEAR_MSI_INTR02_SHIFT 26
-#define BCHP_PCIE_0_INTR2_CPU_MASK_CLEAR_MSI_INTR02_DEFAULT 0x00000001
-
-/* PCIE_0_INTR2 :: CPU_MASK_CLEAR :: MSI_INTR01 [25:25] */
-#define BCHP_PCIE_0_INTR2_CPU_MASK_CLEAR_MSI_INTR01_MASK 0x02000000
-#define BCHP_PCIE_0_INTR2_CPU_MASK_CLEAR_MSI_INTR01_SHIFT 25
-#define BCHP_PCIE_0_INTR2_CPU_MASK_CLEAR_MSI_INTR01_DEFAULT 0x00000001
-
-/* PCIE_0_INTR2 :: CPU_MASK_CLEAR :: MSI_INTR00 [24:24] */
-#define BCHP_PCIE_0_INTR2_CPU_MASK_CLEAR_MSI_INTR00_MASK 0x01000000
-#define BCHP_PCIE_0_INTR2_CPU_MASK_CLEAR_MSI_INTR00_SHIFT 24
-#define BCHP_PCIE_0_INTR2_CPU_MASK_CLEAR_MSI_INTR00_DEFAULT 0x00000001
-
-/* PCIE_0_INTR2 :: CPU_MASK_CLEAR :: UNASSIGNED_23 [23:23] */
-#define BCHP_PCIE_0_INTR2_CPU_MASK_CLEAR_UNASSIGNED_23_MASK 0x00800000
-#define BCHP_PCIE_0_INTR2_CPU_MASK_CLEAR_UNASSIGNED_23_SHIFT 23
-#define BCHP_PCIE_0_INTR2_CPU_MASK_CLEAR_UNASSIGNED_23_DEFAULT 0x00000001
-
-/* PCIE_0_INTR2 :: CPU_MASK_CLEAR :: UNASSIGNED_22 [22:22] */
-#define BCHP_PCIE_0_INTR2_CPU_MASK_CLEAR_UNASSIGNED_22_MASK 0x00400000
-#define BCHP_PCIE_0_INTR2_CPU_MASK_CLEAR_UNASSIGNED_22_SHIFT 22
-#define BCHP_PCIE_0_INTR2_CPU_MASK_CLEAR_UNASSIGNED_22_DEFAULT 0x00000001
-
-/* PCIE_0_INTR2 :: CPU_MASK_CLEAR :: UNASSIGNED_21 [21:21] */
-#define BCHP_PCIE_0_INTR2_CPU_MASK_CLEAR_UNASSIGNED_21_MASK 0x00200000
-#define BCHP_PCIE_0_INTR2_CPU_MASK_CLEAR_UNASSIGNED_21_SHIFT 21
-#define BCHP_PCIE_0_INTR2_CPU_MASK_CLEAR_UNASSIGNED_21_DEFAULT 0x00000001
-
-/* PCIE_0_INTR2 :: CPU_MASK_CLEAR :: UNASSIGNED_20 [20:20] */
-#define BCHP_PCIE_0_INTR2_CPU_MASK_CLEAR_UNASSIGNED_20_MASK 0x00100000
-#define BCHP_PCIE_0_INTR2_CPU_MASK_CLEAR_UNASSIGNED_20_SHIFT 20
-#define BCHP_PCIE_0_INTR2_CPU_MASK_CLEAR_UNASSIGNED_20_DEFAULT 0x00000001
-
-/* PCIE_0_INTR2 :: CPU_MASK_CLEAR :: MAILBOX_3 [19:19] */
-#define BCHP_PCIE_0_INTR2_CPU_MASK_CLEAR_MAILBOX_3_MASK 0x00080000
-#define BCHP_PCIE_0_INTR2_CPU_MASK_CLEAR_MAILBOX_3_SHIFT 19
-#define BCHP_PCIE_0_INTR2_CPU_MASK_CLEAR_MAILBOX_3_DEFAULT 0x00000001
-
-/* PCIE_0_INTR2 :: CPU_MASK_CLEAR :: MAILBOX_2 [18:18] */
-#define BCHP_PCIE_0_INTR2_CPU_MASK_CLEAR_MAILBOX_2_MASK 0x00040000
-#define BCHP_PCIE_0_INTR2_CPU_MASK_CLEAR_MAILBOX_2_SHIFT 18
-#define BCHP_PCIE_0_INTR2_CPU_MASK_CLEAR_MAILBOX_2_DEFAULT 0x00000001
-
-/* PCIE_0_INTR2 :: CPU_MASK_CLEAR :: MAILBOX_1 [17:17] */
-#define BCHP_PCIE_0_INTR2_CPU_MASK_CLEAR_MAILBOX_1_MASK 0x00020000
-#define BCHP_PCIE_0_INTR2_CPU_MASK_CLEAR_MAILBOX_1_SHIFT 17
-#define BCHP_PCIE_0_INTR2_CPU_MASK_CLEAR_MAILBOX_1_DEFAULT 0x00000001
-
-/* PCIE_0_INTR2 :: CPU_MASK_CLEAR :: MAILBOX_0 [16:16] */
-#define BCHP_PCIE_0_INTR2_CPU_MASK_CLEAR_MAILBOX_0_MASK 0x00010000
-#define BCHP_PCIE_0_INTR2_CPU_MASK_CLEAR_MAILBOX_0_SHIFT 16
-#define BCHP_PCIE_0_INTR2_CPU_MASK_CLEAR_MAILBOX_0_DEFAULT 0x00000001
-
-/* PCIE_0_INTR2 :: CPU_MASK_CLEAR :: PCIE_MSTR_FWD_ERR [15:15] */
-#define BCHP_PCIE_0_INTR2_CPU_MASK_CLEAR_PCIE_MSTR_FWD_ERR_MASK 0x00008000
-#define BCHP_PCIE_0_INTR2_CPU_MASK_CLEAR_PCIE_MSTR_FWD_ERR_SHIFT 15
-#define BCHP_PCIE_0_INTR2_CPU_MASK_CLEAR_PCIE_MSTR_FWD_ERR_DEFAULT 0x00000001
-
-/* PCIE_0_INTR2 :: CPU_MASK_CLEAR :: PCIE_MSTR_RETRY_TIMEOUT [14:14] */
-#define BCHP_PCIE_0_INTR2_CPU_MASK_CLEAR_PCIE_MSTR_RETRY_TIMEOUT_MASK 0x00004000
-#define BCHP_PCIE_0_INTR2_CPU_MASK_CLEAR_PCIE_MSTR_RETRY_TIMEOUT_SHIFT 14
-#define BCHP_PCIE_0_INTR2_CPU_MASK_CLEAR_PCIE_MSTR_RETRY_TIMEOUT_DEFAULT 0x00000001
-
-/* PCIE_0_INTR2 :: CPU_MASK_CLEAR :: PCIE_MSTR_CA_ATTN [13:13] */
-#define BCHP_PCIE_0_INTR2_CPU_MASK_CLEAR_PCIE_MSTR_CA_ATTN_MASK 0x00002000
-#define BCHP_PCIE_0_INTR2_CPU_MASK_CLEAR_PCIE_MSTR_CA_ATTN_SHIFT 13
-#define BCHP_PCIE_0_INTR2_CPU_MASK_CLEAR_PCIE_MSTR_CA_ATTN_DEFAULT 0x00000001
-
-/* PCIE_0_INTR2 :: CPU_MASK_CLEAR :: PCIE_MSTR_UR_ATTN [12:12] */
-#define BCHP_PCIE_0_INTR2_CPU_MASK_CLEAR_PCIE_MSTR_UR_ATTN_MASK 0x00001000
-#define BCHP_PCIE_0_INTR2_CPU_MASK_CLEAR_PCIE_MSTR_UR_ATTN_SHIFT 12
-#define BCHP_PCIE_0_INTR2_CPU_MASK_CLEAR_PCIE_MSTR_UR_ATTN_DEFAULT 0x00000001
-
-/* PCIE_0_INTR2 :: CPU_MASK_CLEAR :: UNASSIGNED_11 [11:11] */
-#define BCHP_PCIE_0_INTR2_CPU_MASK_CLEAR_UNASSIGNED_11_MASK 0x00000800
-#define BCHP_PCIE_0_INTR2_CPU_MASK_CLEAR_UNASSIGNED_11_SHIFT 11
-#define BCHP_PCIE_0_INTR2_CPU_MASK_CLEAR_UNASSIGNED_11_DEFAULT 0x00000001
-
-/* PCIE_0_INTR2 :: CPU_MASK_CLEAR :: UNASSIGNED_10 [10:10] */
-#define BCHP_PCIE_0_INTR2_CPU_MASK_CLEAR_UNASSIGNED_10_MASK 0x00000400
-#define BCHP_PCIE_0_INTR2_CPU_MASK_CLEAR_UNASSIGNED_10_SHIFT 10
-#define BCHP_PCIE_0_INTR2_CPU_MASK_CLEAR_UNASSIGNED_10_DEFAULT 0x00000001
-
-/* PCIE_0_INTR2 :: CPU_MASK_CLEAR :: PCIE_TGT_BAD_ACCESS [09:09] */
-#define BCHP_PCIE_0_INTR2_CPU_MASK_CLEAR_PCIE_TGT_BAD_ACCESS_MASK 0x00000200
-#define BCHP_PCIE_0_INTR2_CPU_MASK_CLEAR_PCIE_TGT_BAD_ACCESS_SHIFT 9
-#define BCHP_PCIE_0_INTR2_CPU_MASK_CLEAR_PCIE_TGT_BAD_ACCESS_DEFAULT 0x00000001
-
-/* PCIE_0_INTR2 :: CPU_MASK_CLEAR :: PCIE_TGT_BAD_ADDRESS [08:08] */
-#define BCHP_PCIE_0_INTR2_CPU_MASK_CLEAR_PCIE_TGT_BAD_ADDRESS_MASK 0x00000100
-#define BCHP_PCIE_0_INTR2_CPU_MASK_CLEAR_PCIE_TGT_BAD_ADDRESS_SHIFT 8
-#define BCHP_PCIE_0_INTR2_CPU_MASK_CLEAR_PCIE_TGT_BAD_ADDRESS_DEFAULT 0x00000001
-
-/* PCIE_0_INTR2 :: CPU_MASK_CLEAR :: L1_RX_DMA_ERR_INTR [07:07] */
-#define BCHP_PCIE_0_INTR2_CPU_MASK_CLEAR_L1_RX_DMA_ERR_INTR_MASK 0x00000080
-#define BCHP_PCIE_0_INTR2_CPU_MASK_CLEAR_L1_RX_DMA_ERR_INTR_SHIFT 7
-#define BCHP_PCIE_0_INTR2_CPU_MASK_CLEAR_L1_RX_DMA_ERR_INTR_DEFAULT 0x00000001
-
-/* PCIE_0_INTR2 :: CPU_MASK_CLEAR :: L1_RX_DMA_DONE_INTR [06:06] */
-#define BCHP_PCIE_0_INTR2_CPU_MASK_CLEAR_L1_RX_DMA_DONE_INTR_MASK 0x00000040
-#define BCHP_PCIE_0_INTR2_CPU_MASK_CLEAR_L1_RX_DMA_DONE_INTR_SHIFT 6
-#define BCHP_PCIE_0_INTR2_CPU_MASK_CLEAR_L1_RX_DMA_DONE_INTR_DEFAULT 0x00000001
-
-/* PCIE_0_INTR2 :: CPU_MASK_CLEAR :: L1_TX_DMA_ERR_INTR [05:05] */
-#define BCHP_PCIE_0_INTR2_CPU_MASK_CLEAR_L1_TX_DMA_ERR_INTR_MASK 0x00000020
-#define BCHP_PCIE_0_INTR2_CPU_MASK_CLEAR_L1_TX_DMA_ERR_INTR_SHIFT 5
-#define BCHP_PCIE_0_INTR2_CPU_MASK_CLEAR_L1_TX_DMA_ERR_INTR_DEFAULT 0x00000001
-
-/* PCIE_0_INTR2 :: CPU_MASK_CLEAR :: L1_TX_DMA_DONE_INTR [04:04] */
-#define BCHP_PCIE_0_INTR2_CPU_MASK_CLEAR_L1_TX_DMA_DONE_INTR_MASK 0x00000010
-#define BCHP_PCIE_0_INTR2_CPU_MASK_CLEAR_L1_TX_DMA_DONE_INTR_SHIFT 4
-#define BCHP_PCIE_0_INTR2_CPU_MASK_CLEAR_L1_TX_DMA_DONE_INTR_DEFAULT 0x00000001
-
-/* PCIE_0_INTR2 :: CPU_MASK_CLEAR :: L0_RX_DMA_ERR_INTR [03:03] */
-#define BCHP_PCIE_0_INTR2_CPU_MASK_CLEAR_L0_RX_DMA_ERR_INTR_MASK 0x00000008
-#define BCHP_PCIE_0_INTR2_CPU_MASK_CLEAR_L0_RX_DMA_ERR_INTR_SHIFT 3
-#define BCHP_PCIE_0_INTR2_CPU_MASK_CLEAR_L0_RX_DMA_ERR_INTR_DEFAULT 0x00000001
-
-/* PCIE_0_INTR2 :: CPU_MASK_CLEAR :: L0_RX_DMA_DONE_INTR [02:02] */
-#define BCHP_PCIE_0_INTR2_CPU_MASK_CLEAR_L0_RX_DMA_DONE_INTR_MASK 0x00000004
-#define BCHP_PCIE_0_INTR2_CPU_MASK_CLEAR_L0_RX_DMA_DONE_INTR_SHIFT 2
-#define BCHP_PCIE_0_INTR2_CPU_MASK_CLEAR_L0_RX_DMA_DONE_INTR_DEFAULT 0x00000001
-
-/* PCIE_0_INTR2 :: CPU_MASK_CLEAR :: L0_TX_DMA_ERR_INTR [01:01] */
-#define BCHP_PCIE_0_INTR2_CPU_MASK_CLEAR_L0_TX_DMA_ERR_INTR_MASK 0x00000002
-#define BCHP_PCIE_0_INTR2_CPU_MASK_CLEAR_L0_TX_DMA_ERR_INTR_SHIFT 1
-#define BCHP_PCIE_0_INTR2_CPU_MASK_CLEAR_L0_TX_DMA_ERR_INTR_DEFAULT 0x00000001
-
-/* PCIE_0_INTR2 :: CPU_MASK_CLEAR :: L0_TX_DMA_DONE_INTR [00:00] */
-#define BCHP_PCIE_0_INTR2_CPU_MASK_CLEAR_L0_TX_DMA_DONE_INTR_MASK 0x00000001
-#define BCHP_PCIE_0_INTR2_CPU_MASK_CLEAR_L0_TX_DMA_DONE_INTR_SHIFT 0
-#define BCHP_PCIE_0_INTR2_CPU_MASK_CLEAR_L0_TX_DMA_DONE_INTR_DEFAULT 0x00000001
-
-/***************************************************************************
- *PCI_STATUS - PCI interrupt Status Register
- ***************************************************************************/
-/* PCIE_0_INTR2 :: PCI_STATUS :: MSI_INTR07 [31:31] */
-#define BCHP_PCIE_0_INTR2_PCI_STATUS_MSI_INTR07_MASK 0x80000000
-#define BCHP_PCIE_0_INTR2_PCI_STATUS_MSI_INTR07_SHIFT 31
-#define BCHP_PCIE_0_INTR2_PCI_STATUS_MSI_INTR07_DEFAULT 0x00000000
-
-/* PCIE_0_INTR2 :: PCI_STATUS :: MSI_INTR06 [30:30] */
-#define BCHP_PCIE_0_INTR2_PCI_STATUS_MSI_INTR06_MASK 0x40000000
-#define BCHP_PCIE_0_INTR2_PCI_STATUS_MSI_INTR06_SHIFT 30
-#define BCHP_PCIE_0_INTR2_PCI_STATUS_MSI_INTR06_DEFAULT 0x00000000
-
-/* PCIE_0_INTR2 :: PCI_STATUS :: MSI_INTR05 [29:29] */
-#define BCHP_PCIE_0_INTR2_PCI_STATUS_MSI_INTR05_MASK 0x20000000
-#define BCHP_PCIE_0_INTR2_PCI_STATUS_MSI_INTR05_SHIFT 29
-#define BCHP_PCIE_0_INTR2_PCI_STATUS_MSI_INTR05_DEFAULT 0x00000000
-
-/* PCIE_0_INTR2 :: PCI_STATUS :: MSI_INTR04 [28:28] */
-#define BCHP_PCIE_0_INTR2_PCI_STATUS_MSI_INTR04_MASK 0x10000000
-#define BCHP_PCIE_0_INTR2_PCI_STATUS_MSI_INTR04_SHIFT 28
-#define BCHP_PCIE_0_INTR2_PCI_STATUS_MSI_INTR04_DEFAULT 0x00000000
-
-/* PCIE_0_INTR2 :: PCI_STATUS :: MSI_INTR03 [27:27] */
-#define BCHP_PCIE_0_INTR2_PCI_STATUS_MSI_INTR03_MASK 0x08000000
-#define BCHP_PCIE_0_INTR2_PCI_STATUS_MSI_INTR03_SHIFT 27
-#define BCHP_PCIE_0_INTR2_PCI_STATUS_MSI_INTR03_DEFAULT 0x00000000
-
-/* PCIE_0_INTR2 :: PCI_STATUS :: MSI_INTR02 [26:26] */
-#define BCHP_PCIE_0_INTR2_PCI_STATUS_MSI_INTR02_MASK 0x04000000
-#define BCHP_PCIE_0_INTR2_PCI_STATUS_MSI_INTR02_SHIFT 26
-#define BCHP_PCIE_0_INTR2_PCI_STATUS_MSI_INTR02_DEFAULT 0x00000000
-
-/* PCIE_0_INTR2 :: PCI_STATUS :: MSI_INTR01 [25:25] */
-#define BCHP_PCIE_0_INTR2_PCI_STATUS_MSI_INTR01_MASK 0x02000000
-#define BCHP_PCIE_0_INTR2_PCI_STATUS_MSI_INTR01_SHIFT 25
-#define BCHP_PCIE_0_INTR2_PCI_STATUS_MSI_INTR01_DEFAULT 0x00000000
-
-/* PCIE_0_INTR2 :: PCI_STATUS :: MSI_INTR00 [24:24] */
-#define BCHP_PCIE_0_INTR2_PCI_STATUS_MSI_INTR00_MASK 0x01000000
-#define BCHP_PCIE_0_INTR2_PCI_STATUS_MSI_INTR00_SHIFT 24
-#define BCHP_PCIE_0_INTR2_PCI_STATUS_MSI_INTR00_DEFAULT 0x00000000
-
-/* PCIE_0_INTR2 :: PCI_STATUS :: UNASSIGNED_23 [23:23] */
-#define BCHP_PCIE_0_INTR2_PCI_STATUS_UNASSIGNED_23_MASK 0x00800000
-#define BCHP_PCIE_0_INTR2_PCI_STATUS_UNASSIGNED_23_SHIFT 23
-#define BCHP_PCIE_0_INTR2_PCI_STATUS_UNASSIGNED_23_DEFAULT 0x00000000
-
-/* PCIE_0_INTR2 :: PCI_STATUS :: UNASSIGNED_22 [22:22] */
-#define BCHP_PCIE_0_INTR2_PCI_STATUS_UNASSIGNED_22_MASK 0x00400000
-#define BCHP_PCIE_0_INTR2_PCI_STATUS_UNASSIGNED_22_SHIFT 22
-#define BCHP_PCIE_0_INTR2_PCI_STATUS_UNASSIGNED_22_DEFAULT 0x00000000
-
-/* PCIE_0_INTR2 :: PCI_STATUS :: UNASSIGNED_21 [21:21] */
-#define BCHP_PCIE_0_INTR2_PCI_STATUS_UNASSIGNED_21_MASK 0x00200000
-#define BCHP_PCIE_0_INTR2_PCI_STATUS_UNASSIGNED_21_SHIFT 21
-#define BCHP_PCIE_0_INTR2_PCI_STATUS_UNASSIGNED_21_DEFAULT 0x00000000
-
-/* PCIE_0_INTR2 :: PCI_STATUS :: UNASSIGNED_20 [20:20] */
-#define BCHP_PCIE_0_INTR2_PCI_STATUS_UNASSIGNED_20_MASK 0x00100000
-#define BCHP_PCIE_0_INTR2_PCI_STATUS_UNASSIGNED_20_SHIFT 20
-#define BCHP_PCIE_0_INTR2_PCI_STATUS_UNASSIGNED_20_DEFAULT 0x00000000
-
-/* PCIE_0_INTR2 :: PCI_STATUS :: MAILBOX_3 [19:19] */
-#define BCHP_PCIE_0_INTR2_PCI_STATUS_MAILBOX_3_MASK 0x00080000
-#define BCHP_PCIE_0_INTR2_PCI_STATUS_MAILBOX_3_SHIFT 19
-#define BCHP_PCIE_0_INTR2_PCI_STATUS_MAILBOX_3_DEFAULT 0x00000000
-
-/* PCIE_0_INTR2 :: PCI_STATUS :: MAILBOX_2 [18:18] */
-#define BCHP_PCIE_0_INTR2_PCI_STATUS_MAILBOX_2_MASK 0x00040000
-#define BCHP_PCIE_0_INTR2_PCI_STATUS_MAILBOX_2_SHIFT 18
-#define BCHP_PCIE_0_INTR2_PCI_STATUS_MAILBOX_2_DEFAULT 0x00000000
-
-/* PCIE_0_INTR2 :: PCI_STATUS :: MAILBOX_1 [17:17] */
-#define BCHP_PCIE_0_INTR2_PCI_STATUS_MAILBOX_1_MASK 0x00020000
-#define BCHP_PCIE_0_INTR2_PCI_STATUS_MAILBOX_1_SHIFT 17
-#define BCHP_PCIE_0_INTR2_PCI_STATUS_MAILBOX_1_DEFAULT 0x00000000
-
-/* PCIE_0_INTR2 :: PCI_STATUS :: MAILBOX_0 [16:16] */
-#define BCHP_PCIE_0_INTR2_PCI_STATUS_MAILBOX_0_MASK 0x00010000
-#define BCHP_PCIE_0_INTR2_PCI_STATUS_MAILBOX_0_SHIFT 16
-#define BCHP_PCIE_0_INTR2_PCI_STATUS_MAILBOX_0_DEFAULT 0x00000000
-
-/* PCIE_0_INTR2 :: PCI_STATUS :: PCIE_MSTR_FWD_ERR [15:15] */
-#define BCHP_PCIE_0_INTR2_PCI_STATUS_PCIE_MSTR_FWD_ERR_MASK 0x00008000
-#define BCHP_PCIE_0_INTR2_PCI_STATUS_PCIE_MSTR_FWD_ERR_SHIFT 15
-#define BCHP_PCIE_0_INTR2_PCI_STATUS_PCIE_MSTR_FWD_ERR_DEFAULT 0x00000000
-
-/* PCIE_0_INTR2 :: PCI_STATUS :: PCIE_MSTR_RETRY_TIMEOUT [14:14] */
-#define BCHP_PCIE_0_INTR2_PCI_STATUS_PCIE_MSTR_RETRY_TIMEOUT_MASK 0x00004000
-#define BCHP_PCIE_0_INTR2_PCI_STATUS_PCIE_MSTR_RETRY_TIMEOUT_SHIFT 14
-#define BCHP_PCIE_0_INTR2_PCI_STATUS_PCIE_MSTR_RETRY_TIMEOUT_DEFAULT 0x00000000
-
-/* PCIE_0_INTR2 :: PCI_STATUS :: PCIE_MSTR_CA_ATTN [13:13] */
-#define BCHP_PCIE_0_INTR2_PCI_STATUS_PCIE_MSTR_CA_ATTN_MASK 0x00002000
-#define BCHP_PCIE_0_INTR2_PCI_STATUS_PCIE_MSTR_CA_ATTN_SHIFT 13
-#define BCHP_PCIE_0_INTR2_PCI_STATUS_PCIE_MSTR_CA_ATTN_DEFAULT 0x00000000
-
-/* PCIE_0_INTR2 :: PCI_STATUS :: PCIE_MSTR_UR_ATTN [12:12] */
-#define BCHP_PCIE_0_INTR2_PCI_STATUS_PCIE_MSTR_UR_ATTN_MASK 0x00001000
-#define BCHP_PCIE_0_INTR2_PCI_STATUS_PCIE_MSTR_UR_ATTN_SHIFT 12
-#define BCHP_PCIE_0_INTR2_PCI_STATUS_PCIE_MSTR_UR_ATTN_DEFAULT 0x00000000
-
-/* PCIE_0_INTR2 :: PCI_STATUS :: UNASSIGNED_11 [11:11] */
-#define BCHP_PCIE_0_INTR2_PCI_STATUS_UNASSIGNED_11_MASK 0x00000800
-#define BCHP_PCIE_0_INTR2_PCI_STATUS_UNASSIGNED_11_SHIFT 11
-#define BCHP_PCIE_0_INTR2_PCI_STATUS_UNASSIGNED_11_DEFAULT 0x00000000
-
-/* PCIE_0_INTR2 :: PCI_STATUS :: UNASSIGNED_10 [10:10] */
-#define BCHP_PCIE_0_INTR2_PCI_STATUS_UNASSIGNED_10_MASK 0x00000400
-#define BCHP_PCIE_0_INTR2_PCI_STATUS_UNASSIGNED_10_SHIFT 10
-#define BCHP_PCIE_0_INTR2_PCI_STATUS_UNASSIGNED_10_DEFAULT 0x00000000
-
-/* PCIE_0_INTR2 :: PCI_STATUS :: PCIE_TGT_BAD_ACCESS [09:09] */
-#define BCHP_PCIE_0_INTR2_PCI_STATUS_PCIE_TGT_BAD_ACCESS_MASK 0x00000200
-#define BCHP_PCIE_0_INTR2_PCI_STATUS_PCIE_TGT_BAD_ACCESS_SHIFT 9
-#define BCHP_PCIE_0_INTR2_PCI_STATUS_PCIE_TGT_BAD_ACCESS_DEFAULT 0x00000000
-
-/* PCIE_0_INTR2 :: PCI_STATUS :: PCIE_TGT_BAD_ADDRESS [08:08] */
-#define BCHP_PCIE_0_INTR2_PCI_STATUS_PCIE_TGT_BAD_ADDRESS_MASK 0x00000100
-#define BCHP_PCIE_0_INTR2_PCI_STATUS_PCIE_TGT_BAD_ADDRESS_SHIFT 8
-#define BCHP_PCIE_0_INTR2_PCI_STATUS_PCIE_TGT_BAD_ADDRESS_DEFAULT 0x00000000
-
-/* PCIE_0_INTR2 :: PCI_STATUS :: L1_RX_DMA_ERR_INTR [07:07] */
-#define BCHP_PCIE_0_INTR2_PCI_STATUS_L1_RX_DMA_ERR_INTR_MASK 0x00000080
-#define BCHP_PCIE_0_INTR2_PCI_STATUS_L1_RX_DMA_ERR_INTR_SHIFT 7
-#define BCHP_PCIE_0_INTR2_PCI_STATUS_L1_RX_DMA_ERR_INTR_DEFAULT 0x00000000
-
-/* PCIE_0_INTR2 :: PCI_STATUS :: L1_RX_DMA_DONE_INTR [06:06] */
-#define BCHP_PCIE_0_INTR2_PCI_STATUS_L1_RX_DMA_DONE_INTR_MASK 0x00000040
-#define BCHP_PCIE_0_INTR2_PCI_STATUS_L1_RX_DMA_DONE_INTR_SHIFT 6
-#define BCHP_PCIE_0_INTR2_PCI_STATUS_L1_RX_DMA_DONE_INTR_DEFAULT 0x00000000
-
-/* PCIE_0_INTR2 :: PCI_STATUS :: L1_TX_DMA_ERR_INTR [05:05] */
-#define BCHP_PCIE_0_INTR2_PCI_STATUS_L1_TX_DMA_ERR_INTR_MASK 0x00000020
-#define BCHP_PCIE_0_INTR2_PCI_STATUS_L1_TX_DMA_ERR_INTR_SHIFT 5
-#define BCHP_PCIE_0_INTR2_PCI_STATUS_L1_TX_DMA_ERR_INTR_DEFAULT 0x00000000
-
-/* PCIE_0_INTR2 :: PCI_STATUS :: L1_TX_DMA_DONE_INTR [04:04] */
-#define BCHP_PCIE_0_INTR2_PCI_STATUS_L1_TX_DMA_DONE_INTR_MASK 0x00000010
-#define BCHP_PCIE_0_INTR2_PCI_STATUS_L1_TX_DMA_DONE_INTR_SHIFT 4
-#define BCHP_PCIE_0_INTR2_PCI_STATUS_L1_TX_DMA_DONE_INTR_DEFAULT 0x00000000
-
-/* PCIE_0_INTR2 :: PCI_STATUS :: L0_RX_DMA_ERR_INTR [03:03] */
-#define BCHP_PCIE_0_INTR2_PCI_STATUS_L0_RX_DMA_ERR_INTR_MASK 0x00000008
-#define BCHP_PCIE_0_INTR2_PCI_STATUS_L0_RX_DMA_ERR_INTR_SHIFT 3
-#define BCHP_PCIE_0_INTR2_PCI_STATUS_L0_RX_DMA_ERR_INTR_DEFAULT 0x00000000
-
-/* PCIE_0_INTR2 :: PCI_STATUS :: L0_RX_DMA_DONE_INTR [02:02] */
-#define BCHP_PCIE_0_INTR2_PCI_STATUS_L0_RX_DMA_DONE_INTR_MASK 0x00000004
-#define BCHP_PCIE_0_INTR2_PCI_STATUS_L0_RX_DMA_DONE_INTR_SHIFT 2
-#define BCHP_PCIE_0_INTR2_PCI_STATUS_L0_RX_DMA_DONE_INTR_DEFAULT 0x00000000
-
-/* PCIE_0_INTR2 :: PCI_STATUS :: L0_TX_DMA_ERR_INTR [01:01] */
-#define BCHP_PCIE_0_INTR2_PCI_STATUS_L0_TX_DMA_ERR_INTR_MASK 0x00000002
-#define BCHP_PCIE_0_INTR2_PCI_STATUS_L0_TX_DMA_ERR_INTR_SHIFT 1
-#define BCHP_PCIE_0_INTR2_PCI_STATUS_L0_TX_DMA_ERR_INTR_DEFAULT 0x00000000
-
-/* PCIE_0_INTR2 :: PCI_STATUS :: L0_TX_DMA_DONE_INTR [00:00] */
-#define BCHP_PCIE_0_INTR2_PCI_STATUS_L0_TX_DMA_DONE_INTR_MASK 0x00000001
-#define BCHP_PCIE_0_INTR2_PCI_STATUS_L0_TX_DMA_DONE_INTR_SHIFT 0
-#define BCHP_PCIE_0_INTR2_PCI_STATUS_L0_TX_DMA_DONE_INTR_DEFAULT 0x00000000
-
-/***************************************************************************
- *PCI_SET - PCI interrupt Set Register
- ***************************************************************************/
-/* PCIE_0_INTR2 :: PCI_SET :: MSI_INTR07 [31:31] */
-#define BCHP_PCIE_0_INTR2_PCI_SET_MSI_INTR07_MASK 0x80000000
-#define BCHP_PCIE_0_INTR2_PCI_SET_MSI_INTR07_SHIFT 31
-#define BCHP_PCIE_0_INTR2_PCI_SET_MSI_INTR07_DEFAULT 0x00000000
-
-/* PCIE_0_INTR2 :: PCI_SET :: MSI_INTR06 [30:30] */
-#define BCHP_PCIE_0_INTR2_PCI_SET_MSI_INTR06_MASK 0x40000000
-#define BCHP_PCIE_0_INTR2_PCI_SET_MSI_INTR06_SHIFT 30
-#define BCHP_PCIE_0_INTR2_PCI_SET_MSI_INTR06_DEFAULT 0x00000000
-
-/* PCIE_0_INTR2 :: PCI_SET :: MSI_INTR05 [29:29] */
-#define BCHP_PCIE_0_INTR2_PCI_SET_MSI_INTR05_MASK 0x20000000
-#define BCHP_PCIE_0_INTR2_PCI_SET_MSI_INTR05_SHIFT 29
-#define BCHP_PCIE_0_INTR2_PCI_SET_MSI_INTR05_DEFAULT 0x00000000
-
-/* PCIE_0_INTR2 :: PCI_SET :: MSI_INTR04 [28:28] */
-#define BCHP_PCIE_0_INTR2_PCI_SET_MSI_INTR04_MASK 0x10000000
-#define BCHP_PCIE_0_INTR2_PCI_SET_MSI_INTR04_SHIFT 28
-#define BCHP_PCIE_0_INTR2_PCI_SET_MSI_INTR04_DEFAULT 0x00000000
-
-/* PCIE_0_INTR2 :: PCI_SET :: MSI_INTR03 [27:27] */
-#define BCHP_PCIE_0_INTR2_PCI_SET_MSI_INTR03_MASK 0x08000000
-#define BCHP_PCIE_0_INTR2_PCI_SET_MSI_INTR03_SHIFT 27
-#define BCHP_PCIE_0_INTR2_PCI_SET_MSI_INTR03_DEFAULT 0x00000000
-
-/* PCIE_0_INTR2 :: PCI_SET :: MSI_INTR02 [26:26] */
-#define BCHP_PCIE_0_INTR2_PCI_SET_MSI_INTR02_MASK 0x04000000
-#define BCHP_PCIE_0_INTR2_PCI_SET_MSI_INTR02_SHIFT 26
-#define BCHP_PCIE_0_INTR2_PCI_SET_MSI_INTR02_DEFAULT 0x00000000
-
-/* PCIE_0_INTR2 :: PCI_SET :: MSI_INTR01 [25:25] */
-#define BCHP_PCIE_0_INTR2_PCI_SET_MSI_INTR01_MASK 0x02000000
-#define BCHP_PCIE_0_INTR2_PCI_SET_MSI_INTR01_SHIFT 25
-#define BCHP_PCIE_0_INTR2_PCI_SET_MSI_INTR01_DEFAULT 0x00000000
-
-/* PCIE_0_INTR2 :: PCI_SET :: MSI_INTR00 [24:24] */
-#define BCHP_PCIE_0_INTR2_PCI_SET_MSI_INTR00_MASK 0x01000000
-#define BCHP_PCIE_0_INTR2_PCI_SET_MSI_INTR00_SHIFT 24
-#define BCHP_PCIE_0_INTR2_PCI_SET_MSI_INTR00_DEFAULT 0x00000000
-
-/* PCIE_0_INTR2 :: PCI_SET :: UNASSIGNED_23 [23:23] */
-#define BCHP_PCIE_0_INTR2_PCI_SET_UNASSIGNED_23_MASK 0x00800000
-#define BCHP_PCIE_0_INTR2_PCI_SET_UNASSIGNED_23_SHIFT 23
-#define BCHP_PCIE_0_INTR2_PCI_SET_UNASSIGNED_23_DEFAULT 0x00000000
-
-/* PCIE_0_INTR2 :: PCI_SET :: UNASSIGNED_22 [22:22] */
-#define BCHP_PCIE_0_INTR2_PCI_SET_UNASSIGNED_22_MASK 0x00400000
-#define BCHP_PCIE_0_INTR2_PCI_SET_UNASSIGNED_22_SHIFT 22
-#define BCHP_PCIE_0_INTR2_PCI_SET_UNASSIGNED_22_DEFAULT 0x00000000
-
-/* PCIE_0_INTR2 :: PCI_SET :: UNASSIGNED_21 [21:21] */
-#define BCHP_PCIE_0_INTR2_PCI_SET_UNASSIGNED_21_MASK 0x00200000
-#define BCHP_PCIE_0_INTR2_PCI_SET_UNASSIGNED_21_SHIFT 21
-#define BCHP_PCIE_0_INTR2_PCI_SET_UNASSIGNED_21_DEFAULT 0x00000000
-
-/* PCIE_0_INTR2 :: PCI_SET :: UNASSIGNED_20 [20:20] */
-#define BCHP_PCIE_0_INTR2_PCI_SET_UNASSIGNED_20_MASK 0x00100000
-#define BCHP_PCIE_0_INTR2_PCI_SET_UNASSIGNED_20_SHIFT 20
-#define BCHP_PCIE_0_INTR2_PCI_SET_UNASSIGNED_20_DEFAULT 0x00000000
-
-/* PCIE_0_INTR2 :: PCI_SET :: MAILBOX_3 [19:19] */
-#define BCHP_PCIE_0_INTR2_PCI_SET_MAILBOX_3_MASK 0x00080000
-#define BCHP_PCIE_0_INTR2_PCI_SET_MAILBOX_3_SHIFT 19
-#define BCHP_PCIE_0_INTR2_PCI_SET_MAILBOX_3_DEFAULT 0x00000000
-
-/* PCIE_0_INTR2 :: PCI_SET :: MAILBOX_2 [18:18] */
-#define BCHP_PCIE_0_INTR2_PCI_SET_MAILBOX_2_MASK 0x00040000
-#define BCHP_PCIE_0_INTR2_PCI_SET_MAILBOX_2_SHIFT 18
-#define BCHP_PCIE_0_INTR2_PCI_SET_MAILBOX_2_DEFAULT 0x00000000
-
-/* PCIE_0_INTR2 :: PCI_SET :: MAILBOX_1 [17:17] */
-#define BCHP_PCIE_0_INTR2_PCI_SET_MAILBOX_1_MASK 0x00020000
-#define BCHP_PCIE_0_INTR2_PCI_SET_MAILBOX_1_SHIFT 17
-#define BCHP_PCIE_0_INTR2_PCI_SET_MAILBOX_1_DEFAULT 0x00000000
-
-/* PCIE_0_INTR2 :: PCI_SET :: MAILBOX_0 [16:16] */
-#define BCHP_PCIE_0_INTR2_PCI_SET_MAILBOX_0_MASK 0x00010000
-#define BCHP_PCIE_0_INTR2_PCI_SET_MAILBOX_0_SHIFT 16
-#define BCHP_PCIE_0_INTR2_PCI_SET_MAILBOX_0_DEFAULT 0x00000000
-
-/* PCIE_0_INTR2 :: PCI_SET :: PCIE_MSTR_FWD_ERR [15:15] */
-#define BCHP_PCIE_0_INTR2_PCI_SET_PCIE_MSTR_FWD_ERR_MASK 0x00008000
-#define BCHP_PCIE_0_INTR2_PCI_SET_PCIE_MSTR_FWD_ERR_SHIFT 15
-#define BCHP_PCIE_0_INTR2_PCI_SET_PCIE_MSTR_FWD_ERR_DEFAULT 0x00000000
-
-/* PCIE_0_INTR2 :: PCI_SET :: PCIE_MSTR_RETRY_TIMEOUT [14:14] */
-#define BCHP_PCIE_0_INTR2_PCI_SET_PCIE_MSTR_RETRY_TIMEOUT_MASK 0x00004000
-#define BCHP_PCIE_0_INTR2_PCI_SET_PCIE_MSTR_RETRY_TIMEOUT_SHIFT 14
-#define BCHP_PCIE_0_INTR2_PCI_SET_PCIE_MSTR_RETRY_TIMEOUT_DEFAULT 0x00000000
-
-/* PCIE_0_INTR2 :: PCI_SET :: PCIE_MSTR_CA_ATTN [13:13] */
-#define BCHP_PCIE_0_INTR2_PCI_SET_PCIE_MSTR_CA_ATTN_MASK 0x00002000
-#define BCHP_PCIE_0_INTR2_PCI_SET_PCIE_MSTR_CA_ATTN_SHIFT 13
-#define BCHP_PCIE_0_INTR2_PCI_SET_PCIE_MSTR_CA_ATTN_DEFAULT 0x00000000
-
-/* PCIE_0_INTR2 :: PCI_SET :: PCIE_MSTR_UR_ATTN [12:12] */
-#define BCHP_PCIE_0_INTR2_PCI_SET_PCIE_MSTR_UR_ATTN_MASK 0x00001000
-#define BCHP_PCIE_0_INTR2_PCI_SET_PCIE_MSTR_UR_ATTN_SHIFT 12
-#define BCHP_PCIE_0_INTR2_PCI_SET_PCIE_MSTR_UR_ATTN_DEFAULT 0x00000000
-
-/* PCIE_0_INTR2 :: PCI_SET :: UNASSIGNED_11 [11:11] */
-#define BCHP_PCIE_0_INTR2_PCI_SET_UNASSIGNED_11_MASK 0x00000800
-#define BCHP_PCIE_0_INTR2_PCI_SET_UNASSIGNED_11_SHIFT 11
-#define BCHP_PCIE_0_INTR2_PCI_SET_UNASSIGNED_11_DEFAULT 0x00000000
-
-/* PCIE_0_INTR2 :: PCI_SET :: UNASSIGNED_10 [10:10] */
-#define BCHP_PCIE_0_INTR2_PCI_SET_UNASSIGNED_10_MASK 0x00000400
-#define BCHP_PCIE_0_INTR2_PCI_SET_UNASSIGNED_10_SHIFT 10
-#define BCHP_PCIE_0_INTR2_PCI_SET_UNASSIGNED_10_DEFAULT 0x00000000
-
-/* PCIE_0_INTR2 :: PCI_SET :: PCIE_TGT_BAD_ACCESS [09:09] */
-#define BCHP_PCIE_0_INTR2_PCI_SET_PCIE_TGT_BAD_ACCESS_MASK 0x00000200
-#define BCHP_PCIE_0_INTR2_PCI_SET_PCIE_TGT_BAD_ACCESS_SHIFT 9
-#define BCHP_PCIE_0_INTR2_PCI_SET_PCIE_TGT_BAD_ACCESS_DEFAULT 0x00000000
-
-/* PCIE_0_INTR2 :: PCI_SET :: PCIE_TGT_BAD_ADDRESS [08:08] */
-#define BCHP_PCIE_0_INTR2_PCI_SET_PCIE_TGT_BAD_ADDRESS_MASK 0x00000100
-#define BCHP_PCIE_0_INTR2_PCI_SET_PCIE_TGT_BAD_ADDRESS_SHIFT 8
-#define BCHP_PCIE_0_INTR2_PCI_SET_PCIE_TGT_BAD_ADDRESS_DEFAULT 0x00000000
-
-/* PCIE_0_INTR2 :: PCI_SET :: L1_RX_DMA_ERR_INTR [07:07] */
-#define BCHP_PCIE_0_INTR2_PCI_SET_L1_RX_DMA_ERR_INTR_MASK 0x00000080
-#define BCHP_PCIE_0_INTR2_PCI_SET_L1_RX_DMA_ERR_INTR_SHIFT 7
-#define BCHP_PCIE_0_INTR2_PCI_SET_L1_RX_DMA_ERR_INTR_DEFAULT 0x00000000
-
-/* PCIE_0_INTR2 :: PCI_SET :: L1_RX_DMA_DONE_INTR [06:06] */
-#define BCHP_PCIE_0_INTR2_PCI_SET_L1_RX_DMA_DONE_INTR_MASK 0x00000040
-#define BCHP_PCIE_0_INTR2_PCI_SET_L1_RX_DMA_DONE_INTR_SHIFT 6
-#define BCHP_PCIE_0_INTR2_PCI_SET_L1_RX_DMA_DONE_INTR_DEFAULT 0x00000000
-
-/* PCIE_0_INTR2 :: PCI_SET :: L1_TX_DMA_ERR_INTR [05:05] */
-#define BCHP_PCIE_0_INTR2_PCI_SET_L1_TX_DMA_ERR_INTR_MASK 0x00000020
-#define BCHP_PCIE_0_INTR2_PCI_SET_L1_TX_DMA_ERR_INTR_SHIFT 5
-#define BCHP_PCIE_0_INTR2_PCI_SET_L1_TX_DMA_ERR_INTR_DEFAULT 0x00000000
-
-/* PCIE_0_INTR2 :: PCI_SET :: L1_TX_DMA_DONE_INTR [04:04] */
-#define BCHP_PCIE_0_INTR2_PCI_SET_L1_TX_DMA_DONE_INTR_MASK 0x00000010
-#define BCHP_PCIE_0_INTR2_PCI_SET_L1_TX_DMA_DONE_INTR_SHIFT 4
-#define BCHP_PCIE_0_INTR2_PCI_SET_L1_TX_DMA_DONE_INTR_DEFAULT 0x00000000
-
-/* PCIE_0_INTR2 :: PCI_SET :: L0_RX_DMA_ERR_INTR [03:03] */
-#define BCHP_PCIE_0_INTR2_PCI_SET_L0_RX_DMA_ERR_INTR_MASK 0x00000008
-#define BCHP_PCIE_0_INTR2_PCI_SET_L0_RX_DMA_ERR_INTR_SHIFT 3
-#define BCHP_PCIE_0_INTR2_PCI_SET_L0_RX_DMA_ERR_INTR_DEFAULT 0x00000000
-
-/* PCIE_0_INTR2 :: PCI_SET :: L0_RX_DMA_DONE_INTR [02:02] */
-#define BCHP_PCIE_0_INTR2_PCI_SET_L0_RX_DMA_DONE_INTR_MASK 0x00000004
-#define BCHP_PCIE_0_INTR2_PCI_SET_L0_RX_DMA_DONE_INTR_SHIFT 2
-#define BCHP_PCIE_0_INTR2_PCI_SET_L0_RX_DMA_DONE_INTR_DEFAULT 0x00000000
-
-/* PCIE_0_INTR2 :: PCI_SET :: L0_TX_DMA_ERR_INTR [01:01] */
-#define BCHP_PCIE_0_INTR2_PCI_SET_L0_TX_DMA_ERR_INTR_MASK 0x00000002
-#define BCHP_PCIE_0_INTR2_PCI_SET_L0_TX_DMA_ERR_INTR_SHIFT 1
-#define BCHP_PCIE_0_INTR2_PCI_SET_L0_TX_DMA_ERR_INTR_DEFAULT 0x00000000
-
-/* PCIE_0_INTR2 :: PCI_SET :: L0_TX_DMA_DONE_INTR [00:00] */
-#define BCHP_PCIE_0_INTR2_PCI_SET_L0_TX_DMA_DONE_INTR_MASK 0x00000001
-#define BCHP_PCIE_0_INTR2_PCI_SET_L0_TX_DMA_DONE_INTR_SHIFT 0
-#define BCHP_PCIE_0_INTR2_PCI_SET_L0_TX_DMA_DONE_INTR_DEFAULT 0x00000000
-
-/***************************************************************************
- *PCI_CLEAR - PCI interrupt Clear Register
- ***************************************************************************/
-/* PCIE_0_INTR2 :: PCI_CLEAR :: MSI_INTR07 [31:31] */
-#define BCHP_PCIE_0_INTR2_PCI_CLEAR_MSI_INTR07_MASK 0x80000000
-#define BCHP_PCIE_0_INTR2_PCI_CLEAR_MSI_INTR07_SHIFT 31
-#define BCHP_PCIE_0_INTR2_PCI_CLEAR_MSI_INTR07_DEFAULT 0x00000000
-
-/* PCIE_0_INTR2 :: PCI_CLEAR :: MSI_INTR06 [30:30] */
-#define BCHP_PCIE_0_INTR2_PCI_CLEAR_MSI_INTR06_MASK 0x40000000
-#define BCHP_PCIE_0_INTR2_PCI_CLEAR_MSI_INTR06_SHIFT 30
-#define BCHP_PCIE_0_INTR2_PCI_CLEAR_MSI_INTR06_DEFAULT 0x00000000
-
-/* PCIE_0_INTR2 :: PCI_CLEAR :: MSI_INTR05 [29:29] */
-#define BCHP_PCIE_0_INTR2_PCI_CLEAR_MSI_INTR05_MASK 0x20000000
-#define BCHP_PCIE_0_INTR2_PCI_CLEAR_MSI_INTR05_SHIFT 29
-#define BCHP_PCIE_0_INTR2_PCI_CLEAR_MSI_INTR05_DEFAULT 0x00000000
-
-/* PCIE_0_INTR2 :: PCI_CLEAR :: MSI_INTR04 [28:28] */
-#define BCHP_PCIE_0_INTR2_PCI_CLEAR_MSI_INTR04_MASK 0x10000000
-#define BCHP_PCIE_0_INTR2_PCI_CLEAR_MSI_INTR04_SHIFT 28
-#define BCHP_PCIE_0_INTR2_PCI_CLEAR_MSI_INTR04_DEFAULT 0x00000000
-
-/* PCIE_0_INTR2 :: PCI_CLEAR :: MSI_INTR03 [27:27] */
-#define BCHP_PCIE_0_INTR2_PCI_CLEAR_MSI_INTR03_MASK 0x08000000
-#define BCHP_PCIE_0_INTR2_PCI_CLEAR_MSI_INTR03_SHIFT 27
-#define BCHP_PCIE_0_INTR2_PCI_CLEAR_MSI_INTR03_DEFAULT 0x00000000
-
-/* PCIE_0_INTR2 :: PCI_CLEAR :: MSI_INTR02 [26:26] */
-#define BCHP_PCIE_0_INTR2_PCI_CLEAR_MSI_INTR02_MASK 0x04000000
-#define BCHP_PCIE_0_INTR2_PCI_CLEAR_MSI_INTR02_SHIFT 26
-#define BCHP_PCIE_0_INTR2_PCI_CLEAR_MSI_INTR02_DEFAULT 0x00000000
-
-/* PCIE_0_INTR2 :: PCI_CLEAR :: MSI_INTR01 [25:25] */
-#define BCHP_PCIE_0_INTR2_PCI_CLEAR_MSI_INTR01_MASK 0x02000000
-#define BCHP_PCIE_0_INTR2_PCI_CLEAR_MSI_INTR01_SHIFT 25
-#define BCHP_PCIE_0_INTR2_PCI_CLEAR_MSI_INTR01_DEFAULT 0x00000000
-
-/* PCIE_0_INTR2 :: PCI_CLEAR :: MSI_INTR00 [24:24] */
-#define BCHP_PCIE_0_INTR2_PCI_CLEAR_MSI_INTR00_MASK 0x01000000
-#define BCHP_PCIE_0_INTR2_PCI_CLEAR_MSI_INTR00_SHIFT 24
-#define BCHP_PCIE_0_INTR2_PCI_CLEAR_MSI_INTR00_DEFAULT 0x00000000
-
-/* PCIE_0_INTR2 :: PCI_CLEAR :: UNASSIGNED_23 [23:23] */
-#define BCHP_PCIE_0_INTR2_PCI_CLEAR_UNASSIGNED_23_MASK 0x00800000
-#define BCHP_PCIE_0_INTR2_PCI_CLEAR_UNASSIGNED_23_SHIFT 23
-#define BCHP_PCIE_0_INTR2_PCI_CLEAR_UNASSIGNED_23_DEFAULT 0x00000000
-
-/* PCIE_0_INTR2 :: PCI_CLEAR :: UNASSIGNED_22 [22:22] */
-#define BCHP_PCIE_0_INTR2_PCI_CLEAR_UNASSIGNED_22_MASK 0x00400000
-#define BCHP_PCIE_0_INTR2_PCI_CLEAR_UNASSIGNED_22_SHIFT 22
-#define BCHP_PCIE_0_INTR2_PCI_CLEAR_UNASSIGNED_22_DEFAULT 0x00000000
-
-/* PCIE_0_INTR2 :: PCI_CLEAR :: UNASSIGNED_21 [21:21] */
-#define BCHP_PCIE_0_INTR2_PCI_CLEAR_UNASSIGNED_21_MASK 0x00200000
-#define BCHP_PCIE_0_INTR2_PCI_CLEAR_UNASSIGNED_21_SHIFT 21
-#define BCHP_PCIE_0_INTR2_PCI_CLEAR_UNASSIGNED_21_DEFAULT 0x00000000
-
-/* PCIE_0_INTR2 :: PCI_CLEAR :: UNASSIGNED_20 [20:20] */
-#define BCHP_PCIE_0_INTR2_PCI_CLEAR_UNASSIGNED_20_MASK 0x00100000
-#define BCHP_PCIE_0_INTR2_PCI_CLEAR_UNASSIGNED_20_SHIFT 20
-#define BCHP_PCIE_0_INTR2_PCI_CLEAR_UNASSIGNED_20_DEFAULT 0x00000000
-
-/* PCIE_0_INTR2 :: PCI_CLEAR :: MAILBOX_3 [19:19] */
-#define BCHP_PCIE_0_INTR2_PCI_CLEAR_MAILBOX_3_MASK 0x00080000
-#define BCHP_PCIE_0_INTR2_PCI_CLEAR_MAILBOX_3_SHIFT 19
-#define BCHP_PCIE_0_INTR2_PCI_CLEAR_MAILBOX_3_DEFAULT 0x00000000
-
-/* PCIE_0_INTR2 :: PCI_CLEAR :: MAILBOX_2 [18:18] */
-#define BCHP_PCIE_0_INTR2_PCI_CLEAR_MAILBOX_2_MASK 0x00040000
-#define BCHP_PCIE_0_INTR2_PCI_CLEAR_MAILBOX_2_SHIFT 18
-#define BCHP_PCIE_0_INTR2_PCI_CLEAR_MAILBOX_2_DEFAULT 0x00000000
-
-/* PCIE_0_INTR2 :: PCI_CLEAR :: MAILBOX_1 [17:17] */
-#define BCHP_PCIE_0_INTR2_PCI_CLEAR_MAILBOX_1_MASK 0x00020000
-#define BCHP_PCIE_0_INTR2_PCI_CLEAR_MAILBOX_1_SHIFT 17
-#define BCHP_PCIE_0_INTR2_PCI_CLEAR_MAILBOX_1_DEFAULT 0x00000000
-
-/* PCIE_0_INTR2 :: PCI_CLEAR :: MAILBOX_0 [16:16] */
-#define BCHP_PCIE_0_INTR2_PCI_CLEAR_MAILBOX_0_MASK 0x00010000
-#define BCHP_PCIE_0_INTR2_PCI_CLEAR_MAILBOX_0_SHIFT 16
-#define BCHP_PCIE_0_INTR2_PCI_CLEAR_MAILBOX_0_DEFAULT 0x00000000
-
-/* PCIE_0_INTR2 :: PCI_CLEAR :: PCIE_MSTR_FWD_ERR [15:15] */
-#define BCHP_PCIE_0_INTR2_PCI_CLEAR_PCIE_MSTR_FWD_ERR_MASK 0x00008000
-#define BCHP_PCIE_0_INTR2_PCI_CLEAR_PCIE_MSTR_FWD_ERR_SHIFT 15
-#define BCHP_PCIE_0_INTR2_PCI_CLEAR_PCIE_MSTR_FWD_ERR_DEFAULT 0x00000000
-
-/* PCIE_0_INTR2 :: PCI_CLEAR :: PCIE_MSTR_RETRY_TIMEOUT [14:14] */
-#define BCHP_PCIE_0_INTR2_PCI_CLEAR_PCIE_MSTR_RETRY_TIMEOUT_MASK 0x00004000
-#define BCHP_PCIE_0_INTR2_PCI_CLEAR_PCIE_MSTR_RETRY_TIMEOUT_SHIFT 14
-#define BCHP_PCIE_0_INTR2_PCI_CLEAR_PCIE_MSTR_RETRY_TIMEOUT_DEFAULT 0x00000000
-
-/* PCIE_0_INTR2 :: PCI_CLEAR :: PCIE_MSTR_CA_ATTN [13:13] */
-#define BCHP_PCIE_0_INTR2_PCI_CLEAR_PCIE_MSTR_CA_ATTN_MASK 0x00002000
-#define BCHP_PCIE_0_INTR2_PCI_CLEAR_PCIE_MSTR_CA_ATTN_SHIFT 13
-#define BCHP_PCIE_0_INTR2_PCI_CLEAR_PCIE_MSTR_CA_ATTN_DEFAULT 0x00000000
-
-/* PCIE_0_INTR2 :: PCI_CLEAR :: PCIE_MSTR_UR_ATTN [12:12] */
-#define BCHP_PCIE_0_INTR2_PCI_CLEAR_PCIE_MSTR_UR_ATTN_MASK 0x00001000
-#define BCHP_PCIE_0_INTR2_PCI_CLEAR_PCIE_MSTR_UR_ATTN_SHIFT 12
-#define BCHP_PCIE_0_INTR2_PCI_CLEAR_PCIE_MSTR_UR_ATTN_DEFAULT 0x00000000
-
-/* PCIE_0_INTR2 :: PCI_CLEAR :: UNASSIGNED_11 [11:11] */
-#define BCHP_PCIE_0_INTR2_PCI_CLEAR_UNASSIGNED_11_MASK 0x00000800
-#define BCHP_PCIE_0_INTR2_PCI_CLEAR_UNASSIGNED_11_SHIFT 11
-#define BCHP_PCIE_0_INTR2_PCI_CLEAR_UNASSIGNED_11_DEFAULT 0x00000000
-
-/* PCIE_0_INTR2 :: PCI_CLEAR :: UNASSIGNED_10 [10:10] */
-#define BCHP_PCIE_0_INTR2_PCI_CLEAR_UNASSIGNED_10_MASK 0x00000400
-#define BCHP_PCIE_0_INTR2_PCI_CLEAR_UNASSIGNED_10_SHIFT 10
-#define BCHP_PCIE_0_INTR2_PCI_CLEAR_UNASSIGNED_10_DEFAULT 0x00000000
-
-/* PCIE_0_INTR2 :: PCI_CLEAR :: PCIE_TGT_BAD_ACCESS [09:09] */
-#define BCHP_PCIE_0_INTR2_PCI_CLEAR_PCIE_TGT_BAD_ACCESS_MASK 0x00000200
-#define BCHP_PCIE_0_INTR2_PCI_CLEAR_PCIE_TGT_BAD_ACCESS_SHIFT 9
-#define BCHP_PCIE_0_INTR2_PCI_CLEAR_PCIE_TGT_BAD_ACCESS_DEFAULT 0x00000000
-
-/* PCIE_0_INTR2 :: PCI_CLEAR :: PCIE_TGT_BAD_ADDRESS [08:08] */
-#define BCHP_PCIE_0_INTR2_PCI_CLEAR_PCIE_TGT_BAD_ADDRESS_MASK 0x00000100
-#define BCHP_PCIE_0_INTR2_PCI_CLEAR_PCIE_TGT_BAD_ADDRESS_SHIFT 8
-#define BCHP_PCIE_0_INTR2_PCI_CLEAR_PCIE_TGT_BAD_ADDRESS_DEFAULT 0x00000000
-
-/* PCIE_0_INTR2 :: PCI_CLEAR :: L1_RX_DMA_ERR_INTR [07:07] */
-#define BCHP_PCIE_0_INTR2_PCI_CLEAR_L1_RX_DMA_ERR_INTR_MASK 0x00000080
-#define BCHP_PCIE_0_INTR2_PCI_CLEAR_L1_RX_DMA_ERR_INTR_SHIFT 7
-#define BCHP_PCIE_0_INTR2_PCI_CLEAR_L1_RX_DMA_ERR_INTR_DEFAULT 0x00000000
-
-/* PCIE_0_INTR2 :: PCI_CLEAR :: L1_RX_DMA_DONE_INTR [06:06] */
-#define BCHP_PCIE_0_INTR2_PCI_CLEAR_L1_RX_DMA_DONE_INTR_MASK 0x00000040
-#define BCHP_PCIE_0_INTR2_PCI_CLEAR_L1_RX_DMA_DONE_INTR_SHIFT 6
-#define BCHP_PCIE_0_INTR2_PCI_CLEAR_L1_RX_DMA_DONE_INTR_DEFAULT 0x00000000
-
-/* PCIE_0_INTR2 :: PCI_CLEAR :: L1_TX_DMA_ERR_INTR [05:05] */
-#define BCHP_PCIE_0_INTR2_PCI_CLEAR_L1_TX_DMA_ERR_INTR_MASK 0x00000020
-#define BCHP_PCIE_0_INTR2_PCI_CLEAR_L1_TX_DMA_ERR_INTR_SHIFT 5
-#define BCHP_PCIE_0_INTR2_PCI_CLEAR_L1_TX_DMA_ERR_INTR_DEFAULT 0x00000000
-
-/* PCIE_0_INTR2 :: PCI_CLEAR :: L1_TX_DMA_DONE_INTR [04:04] */
-#define BCHP_PCIE_0_INTR2_PCI_CLEAR_L1_TX_DMA_DONE_INTR_MASK 0x00000010
-#define BCHP_PCIE_0_INTR2_PCI_CLEAR_L1_TX_DMA_DONE_INTR_SHIFT 4
-#define BCHP_PCIE_0_INTR2_PCI_CLEAR_L1_TX_DMA_DONE_INTR_DEFAULT 0x00000000
-
-/* PCIE_0_INTR2 :: PCI_CLEAR :: L0_RX_DMA_ERR_INTR [03:03] */
-#define BCHP_PCIE_0_INTR2_PCI_CLEAR_L0_RX_DMA_ERR_INTR_MASK 0x00000008
-#define BCHP_PCIE_0_INTR2_PCI_CLEAR_L0_RX_DMA_ERR_INTR_SHIFT 3
-#define BCHP_PCIE_0_INTR2_PCI_CLEAR_L0_RX_DMA_ERR_INTR_DEFAULT 0x00000000
-
-/* PCIE_0_INTR2 :: PCI_CLEAR :: L0_RX_DMA_DONE_INTR [02:02] */
-#define BCHP_PCIE_0_INTR2_PCI_CLEAR_L0_RX_DMA_DONE_INTR_MASK 0x00000004
-#define BCHP_PCIE_0_INTR2_PCI_CLEAR_L0_RX_DMA_DONE_INTR_SHIFT 2
-#define BCHP_PCIE_0_INTR2_PCI_CLEAR_L0_RX_DMA_DONE_INTR_DEFAULT 0x00000000
-
-/* PCIE_0_INTR2 :: PCI_CLEAR :: L0_TX_DMA_ERR_INTR [01:01] */
-#define BCHP_PCIE_0_INTR2_PCI_CLEAR_L0_TX_DMA_ERR_INTR_MASK 0x00000002
-#define BCHP_PCIE_0_INTR2_PCI_CLEAR_L0_TX_DMA_ERR_INTR_SHIFT 1
-#define BCHP_PCIE_0_INTR2_PCI_CLEAR_L0_TX_DMA_ERR_INTR_DEFAULT 0x00000000
-
-/* PCIE_0_INTR2 :: PCI_CLEAR :: L0_TX_DMA_DONE_INTR [00:00] */
-#define BCHP_PCIE_0_INTR2_PCI_CLEAR_L0_TX_DMA_DONE_INTR_MASK 0x00000001
-#define BCHP_PCIE_0_INTR2_PCI_CLEAR_L0_TX_DMA_DONE_INTR_SHIFT 0
-#define BCHP_PCIE_0_INTR2_PCI_CLEAR_L0_TX_DMA_DONE_INTR_DEFAULT 0x00000000
-
-/***************************************************************************
- *PCI_MASK_STATUS - PCI interrupt Mask Status Register
- ***************************************************************************/
-/* PCIE_0_INTR2 :: PCI_MASK_STATUS :: MSI_INTR07 [31:31] */
-#define BCHP_PCIE_0_INTR2_PCI_MASK_STATUS_MSI_INTR07_MASK 0x80000000
-#define BCHP_PCIE_0_INTR2_PCI_MASK_STATUS_MSI_INTR07_SHIFT 31
-#define BCHP_PCIE_0_INTR2_PCI_MASK_STATUS_MSI_INTR07_DEFAULT 0x00000001
-
-/* PCIE_0_INTR2 :: PCI_MASK_STATUS :: MSI_INTR06 [30:30] */
-#define BCHP_PCIE_0_INTR2_PCI_MASK_STATUS_MSI_INTR06_MASK 0x40000000
-#define BCHP_PCIE_0_INTR2_PCI_MASK_STATUS_MSI_INTR06_SHIFT 30
-#define BCHP_PCIE_0_INTR2_PCI_MASK_STATUS_MSI_INTR06_DEFAULT 0x00000001
-
-/* PCIE_0_INTR2 :: PCI_MASK_STATUS :: MSI_INTR05 [29:29] */
-#define BCHP_PCIE_0_INTR2_PCI_MASK_STATUS_MSI_INTR05_MASK 0x20000000
-#define BCHP_PCIE_0_INTR2_PCI_MASK_STATUS_MSI_INTR05_SHIFT 29
-#define BCHP_PCIE_0_INTR2_PCI_MASK_STATUS_MSI_INTR05_DEFAULT 0x00000001
-
-/* PCIE_0_INTR2 :: PCI_MASK_STATUS :: MSI_INTR04 [28:28] */
-#define BCHP_PCIE_0_INTR2_PCI_MASK_STATUS_MSI_INTR04_MASK 0x10000000
-#define BCHP_PCIE_0_INTR2_PCI_MASK_STATUS_MSI_INTR04_SHIFT 28
-#define BCHP_PCIE_0_INTR2_PCI_MASK_STATUS_MSI_INTR04_DEFAULT 0x00000001
-
-/* PCIE_0_INTR2 :: PCI_MASK_STATUS :: MSI_INTR03 [27:27] */
-#define BCHP_PCIE_0_INTR2_PCI_MASK_STATUS_MSI_INTR03_MASK 0x08000000
-#define BCHP_PCIE_0_INTR2_PCI_MASK_STATUS_MSI_INTR03_SHIFT 27
-#define BCHP_PCIE_0_INTR2_PCI_MASK_STATUS_MSI_INTR03_DEFAULT 0x00000001
-
-/* PCIE_0_INTR2 :: PCI_MASK_STATUS :: MSI_INTR02 [26:26] */
-#define BCHP_PCIE_0_INTR2_PCI_MASK_STATUS_MSI_INTR02_MASK 0x04000000
-#define BCHP_PCIE_0_INTR2_PCI_MASK_STATUS_MSI_INTR02_SHIFT 26
-#define BCHP_PCIE_0_INTR2_PCI_MASK_STATUS_MSI_INTR02_DEFAULT 0x00000001
-
-/* PCIE_0_INTR2 :: PCI_MASK_STATUS :: MSI_INTR01 [25:25] */
-#define BCHP_PCIE_0_INTR2_PCI_MASK_STATUS_MSI_INTR01_MASK 0x02000000
-#define BCHP_PCIE_0_INTR2_PCI_MASK_STATUS_MSI_INTR01_SHIFT 25
-#define BCHP_PCIE_0_INTR2_PCI_MASK_STATUS_MSI_INTR01_DEFAULT 0x00000001
-
-/* PCIE_0_INTR2 :: PCI_MASK_STATUS :: MSI_INTR00 [24:24] */
-#define BCHP_PCIE_0_INTR2_PCI_MASK_STATUS_MSI_INTR00_MASK 0x01000000
-#define BCHP_PCIE_0_INTR2_PCI_MASK_STATUS_MSI_INTR00_SHIFT 24
-#define BCHP_PCIE_0_INTR2_PCI_MASK_STATUS_MSI_INTR00_DEFAULT 0x00000001
-
-/* PCIE_0_INTR2 :: PCI_MASK_STATUS :: UNASSIGNED_23 [23:23] */
-#define BCHP_PCIE_0_INTR2_PCI_MASK_STATUS_UNASSIGNED_23_MASK 0x00800000
-#define BCHP_PCIE_0_INTR2_PCI_MASK_STATUS_UNASSIGNED_23_SHIFT 23
-#define BCHP_PCIE_0_INTR2_PCI_MASK_STATUS_UNASSIGNED_23_DEFAULT 0x00000001
-
-/* PCIE_0_INTR2 :: PCI_MASK_STATUS :: UNASSIGNED_22 [22:22] */
-#define BCHP_PCIE_0_INTR2_PCI_MASK_STATUS_UNASSIGNED_22_MASK 0x00400000
-#define BCHP_PCIE_0_INTR2_PCI_MASK_STATUS_UNASSIGNED_22_SHIFT 22
-#define BCHP_PCIE_0_INTR2_PCI_MASK_STATUS_UNASSIGNED_22_DEFAULT 0x00000001
-
-/* PCIE_0_INTR2 :: PCI_MASK_STATUS :: UNASSIGNED_21 [21:21] */
-#define BCHP_PCIE_0_INTR2_PCI_MASK_STATUS_UNASSIGNED_21_MASK 0x00200000
-#define BCHP_PCIE_0_INTR2_PCI_MASK_STATUS_UNASSIGNED_21_SHIFT 21
-#define BCHP_PCIE_0_INTR2_PCI_MASK_STATUS_UNASSIGNED_21_DEFAULT 0x00000001
-
-/* PCIE_0_INTR2 :: PCI_MASK_STATUS :: UNASSIGNED_20 [20:20] */
-#define BCHP_PCIE_0_INTR2_PCI_MASK_STATUS_UNASSIGNED_20_MASK 0x00100000
-#define BCHP_PCIE_0_INTR2_PCI_MASK_STATUS_UNASSIGNED_20_SHIFT 20
-#define BCHP_PCIE_0_INTR2_PCI_MASK_STATUS_UNASSIGNED_20_DEFAULT 0x00000001
-
-/* PCIE_0_INTR2 :: PCI_MASK_STATUS :: MAILBOX_3 [19:19] */
-#define BCHP_PCIE_0_INTR2_PCI_MASK_STATUS_MAILBOX_3_MASK 0x00080000
-#define BCHP_PCIE_0_INTR2_PCI_MASK_STATUS_MAILBOX_3_SHIFT 19
-#define BCHP_PCIE_0_INTR2_PCI_MASK_STATUS_MAILBOX_3_DEFAULT 0x00000001
-
-/* PCIE_0_INTR2 :: PCI_MASK_STATUS :: MAILBOX_2 [18:18] */
-#define BCHP_PCIE_0_INTR2_PCI_MASK_STATUS_MAILBOX_2_MASK 0x00040000
-#define BCHP_PCIE_0_INTR2_PCI_MASK_STATUS_MAILBOX_2_SHIFT 18
-#define BCHP_PCIE_0_INTR2_PCI_MASK_STATUS_MAILBOX_2_DEFAULT 0x00000001
-
-/* PCIE_0_INTR2 :: PCI_MASK_STATUS :: MAILBOX_1 [17:17] */
-#define BCHP_PCIE_0_INTR2_PCI_MASK_STATUS_MAILBOX_1_MASK 0x00020000
-#define BCHP_PCIE_0_INTR2_PCI_MASK_STATUS_MAILBOX_1_SHIFT 17
-#define BCHP_PCIE_0_INTR2_PCI_MASK_STATUS_MAILBOX_1_DEFAULT 0x00000001
-
-/* PCIE_0_INTR2 :: PCI_MASK_STATUS :: MAILBOX_0 [16:16] */
-#define BCHP_PCIE_0_INTR2_PCI_MASK_STATUS_MAILBOX_0_MASK 0x00010000
-#define BCHP_PCIE_0_INTR2_PCI_MASK_STATUS_MAILBOX_0_SHIFT 16
-#define BCHP_PCIE_0_INTR2_PCI_MASK_STATUS_MAILBOX_0_DEFAULT 0x00000001
-
-/* PCIE_0_INTR2 :: PCI_MASK_STATUS :: PCIE_MSTR_FWD_ERR [15:15] */
-#define BCHP_PCIE_0_INTR2_PCI_MASK_STATUS_PCIE_MSTR_FWD_ERR_MASK 0x00008000
-#define BCHP_PCIE_0_INTR2_PCI_MASK_STATUS_PCIE_MSTR_FWD_ERR_SHIFT 15
-#define BCHP_PCIE_0_INTR2_PCI_MASK_STATUS_PCIE_MSTR_FWD_ERR_DEFAULT 0x00000001
-
-/* PCIE_0_INTR2 :: PCI_MASK_STATUS :: PCIE_MSTR_RETRY_TIMEOUT [14:14] */
-#define BCHP_PCIE_0_INTR2_PCI_MASK_STATUS_PCIE_MSTR_RETRY_TIMEOUT_MASK 0x00004000
-#define BCHP_PCIE_0_INTR2_PCI_MASK_STATUS_PCIE_MSTR_RETRY_TIMEOUT_SHIFT 14
-#define BCHP_PCIE_0_INTR2_PCI_MASK_STATUS_PCIE_MSTR_RETRY_TIMEOUT_DEFAULT 0x00000001
-
-/* PCIE_0_INTR2 :: PCI_MASK_STATUS :: PCIE_MSTR_CA_ATTN [13:13] */
-#define BCHP_PCIE_0_INTR2_PCI_MASK_STATUS_PCIE_MSTR_CA_ATTN_MASK 0x00002000
-#define BCHP_PCIE_0_INTR2_PCI_MASK_STATUS_PCIE_MSTR_CA_ATTN_SHIFT 13
-#define BCHP_PCIE_0_INTR2_PCI_MASK_STATUS_PCIE_MSTR_CA_ATTN_DEFAULT 0x00000001
-
-/* PCIE_0_INTR2 :: PCI_MASK_STATUS :: PCIE_MSTR_UR_ATTN [12:12] */
-#define BCHP_PCIE_0_INTR2_PCI_MASK_STATUS_PCIE_MSTR_UR_ATTN_MASK 0x00001000
-#define BCHP_PCIE_0_INTR2_PCI_MASK_STATUS_PCIE_MSTR_UR_ATTN_SHIFT 12
-#define BCHP_PCIE_0_INTR2_PCI_MASK_STATUS_PCIE_MSTR_UR_ATTN_DEFAULT 0x00000001
-
-/* PCIE_0_INTR2 :: PCI_MASK_STATUS :: UNASSIGNED_11 [11:11] */
-#define BCHP_PCIE_0_INTR2_PCI_MASK_STATUS_UNASSIGNED_11_MASK 0x00000800
-#define BCHP_PCIE_0_INTR2_PCI_MASK_STATUS_UNASSIGNED_11_SHIFT 11
-#define BCHP_PCIE_0_INTR2_PCI_MASK_STATUS_UNASSIGNED_11_DEFAULT 0x00000001
-
-/* PCIE_0_INTR2 :: PCI_MASK_STATUS :: UNASSIGNED_10 [10:10] */
-#define BCHP_PCIE_0_INTR2_PCI_MASK_STATUS_UNASSIGNED_10_MASK 0x00000400
-#define BCHP_PCIE_0_INTR2_PCI_MASK_STATUS_UNASSIGNED_10_SHIFT 10
-#define BCHP_PCIE_0_INTR2_PCI_MASK_STATUS_UNASSIGNED_10_DEFAULT 0x00000001
-
-/* PCIE_0_INTR2 :: PCI_MASK_STATUS :: PCIE_TGT_BAD_ACCESS [09:09] */
-#define BCHP_PCIE_0_INTR2_PCI_MASK_STATUS_PCIE_TGT_BAD_ACCESS_MASK 0x00000200
-#define BCHP_PCIE_0_INTR2_PCI_MASK_STATUS_PCIE_TGT_BAD_ACCESS_SHIFT 9
-#define BCHP_PCIE_0_INTR2_PCI_MASK_STATUS_PCIE_TGT_BAD_ACCESS_DEFAULT 0x00000001
-
-/* PCIE_0_INTR2 :: PCI_MASK_STATUS :: PCIE_TGT_BAD_ADDRESS [08:08] */
-#define BCHP_PCIE_0_INTR2_PCI_MASK_STATUS_PCIE_TGT_BAD_ADDRESS_MASK 0x00000100
-#define BCHP_PCIE_0_INTR2_PCI_MASK_STATUS_PCIE_TGT_BAD_ADDRESS_SHIFT 8
-#define BCHP_PCIE_0_INTR2_PCI_MASK_STATUS_PCIE_TGT_BAD_ADDRESS_DEFAULT 0x00000001
-
-/* PCIE_0_INTR2 :: PCI_MASK_STATUS :: L1_RX_DMA_ERR_INTR [07:07] */
-#define BCHP_PCIE_0_INTR2_PCI_MASK_STATUS_L1_RX_DMA_ERR_INTR_MASK 0x00000080
-#define BCHP_PCIE_0_INTR2_PCI_MASK_STATUS_L1_RX_DMA_ERR_INTR_SHIFT 7
-#define BCHP_PCIE_0_INTR2_PCI_MASK_STATUS_L1_RX_DMA_ERR_INTR_DEFAULT 0x00000001
-
-/* PCIE_0_INTR2 :: PCI_MASK_STATUS :: L1_RX_DMA_DONE_INTR [06:06] */
-#define BCHP_PCIE_0_INTR2_PCI_MASK_STATUS_L1_RX_DMA_DONE_INTR_MASK 0x00000040
-#define BCHP_PCIE_0_INTR2_PCI_MASK_STATUS_L1_RX_DMA_DONE_INTR_SHIFT 6
-#define BCHP_PCIE_0_INTR2_PCI_MASK_STATUS_L1_RX_DMA_DONE_INTR_DEFAULT 0x00000001
-
-/* PCIE_0_INTR2 :: PCI_MASK_STATUS :: L1_TX_DMA_ERR_INTR [05:05] */
-#define BCHP_PCIE_0_INTR2_PCI_MASK_STATUS_L1_TX_DMA_ERR_INTR_MASK 0x00000020
-#define BCHP_PCIE_0_INTR2_PCI_MASK_STATUS_L1_TX_DMA_ERR_INTR_SHIFT 5
-#define BCHP_PCIE_0_INTR2_PCI_MASK_STATUS_L1_TX_DMA_ERR_INTR_DEFAULT 0x00000001
-
-/* PCIE_0_INTR2 :: PCI_MASK_STATUS :: L1_TX_DMA_DONE_INTR [04:04] */
-#define BCHP_PCIE_0_INTR2_PCI_MASK_STATUS_L1_TX_DMA_DONE_INTR_MASK 0x00000010
-#define BCHP_PCIE_0_INTR2_PCI_MASK_STATUS_L1_TX_DMA_DONE_INTR_SHIFT 4
-#define BCHP_PCIE_0_INTR2_PCI_MASK_STATUS_L1_TX_DMA_DONE_INTR_DEFAULT 0x00000001
-
-/* PCIE_0_INTR2 :: PCI_MASK_STATUS :: L0_RX_DMA_ERR_INTR [03:03] */
-#define BCHP_PCIE_0_INTR2_PCI_MASK_STATUS_L0_RX_DMA_ERR_INTR_MASK 0x00000008
-#define BCHP_PCIE_0_INTR2_PCI_MASK_STATUS_L0_RX_DMA_ERR_INTR_SHIFT 3
-#define BCHP_PCIE_0_INTR2_PCI_MASK_STATUS_L0_RX_DMA_ERR_INTR_DEFAULT 0x00000001
-
-/* PCIE_0_INTR2 :: PCI_MASK_STATUS :: L0_RX_DMA_DONE_INTR [02:02] */
-#define BCHP_PCIE_0_INTR2_PCI_MASK_STATUS_L0_RX_DMA_DONE_INTR_MASK 0x00000004
-#define BCHP_PCIE_0_INTR2_PCI_MASK_STATUS_L0_RX_DMA_DONE_INTR_SHIFT 2
-#define BCHP_PCIE_0_INTR2_PCI_MASK_STATUS_L0_RX_DMA_DONE_INTR_DEFAULT 0x00000001
-
-/* PCIE_0_INTR2 :: PCI_MASK_STATUS :: L0_TX_DMA_ERR_INTR [01:01] */
-#define BCHP_PCIE_0_INTR2_PCI_MASK_STATUS_L0_TX_DMA_ERR_INTR_MASK 0x00000002
-#define BCHP_PCIE_0_INTR2_PCI_MASK_STATUS_L0_TX_DMA_ERR_INTR_SHIFT 1
-#define BCHP_PCIE_0_INTR2_PCI_MASK_STATUS_L0_TX_DMA_ERR_INTR_DEFAULT 0x00000001
-
-/* PCIE_0_INTR2 :: PCI_MASK_STATUS :: L0_TX_DMA_DONE_INTR [00:00] */
-#define BCHP_PCIE_0_INTR2_PCI_MASK_STATUS_L0_TX_DMA_DONE_INTR_MASK 0x00000001
-#define BCHP_PCIE_0_INTR2_PCI_MASK_STATUS_L0_TX_DMA_DONE_INTR_SHIFT 0
-#define BCHP_PCIE_0_INTR2_PCI_MASK_STATUS_L0_TX_DMA_DONE_INTR_DEFAULT 0x00000001
-
-/***************************************************************************
- *PCI_MASK_SET - PCI interrupt Mask Set Register
- ***************************************************************************/
-/* PCIE_0_INTR2 :: PCI_MASK_SET :: MSI_INTR07 [31:31] */
-#define BCHP_PCIE_0_INTR2_PCI_MASK_SET_MSI_INTR07_MASK 0x80000000
-#define BCHP_PCIE_0_INTR2_PCI_MASK_SET_MSI_INTR07_SHIFT 31
-#define BCHP_PCIE_0_INTR2_PCI_MASK_SET_MSI_INTR07_DEFAULT 0x00000001
-
-/* PCIE_0_INTR2 :: PCI_MASK_SET :: MSI_INTR06 [30:30] */
-#define BCHP_PCIE_0_INTR2_PCI_MASK_SET_MSI_INTR06_MASK 0x40000000
-#define BCHP_PCIE_0_INTR2_PCI_MASK_SET_MSI_INTR06_SHIFT 30
-#define BCHP_PCIE_0_INTR2_PCI_MASK_SET_MSI_INTR06_DEFAULT 0x00000001
-
-/* PCIE_0_INTR2 :: PCI_MASK_SET :: MSI_INTR05 [29:29] */
-#define BCHP_PCIE_0_INTR2_PCI_MASK_SET_MSI_INTR05_MASK 0x20000000
-#define BCHP_PCIE_0_INTR2_PCI_MASK_SET_MSI_INTR05_SHIFT 29
-#define BCHP_PCIE_0_INTR2_PCI_MASK_SET_MSI_INTR05_DEFAULT 0x00000001
-
-/* PCIE_0_INTR2 :: PCI_MASK_SET :: MSI_INTR04 [28:28] */
-#define BCHP_PCIE_0_INTR2_PCI_MASK_SET_MSI_INTR04_MASK 0x10000000
-#define BCHP_PCIE_0_INTR2_PCI_MASK_SET_MSI_INTR04_SHIFT 28
-#define BCHP_PCIE_0_INTR2_PCI_MASK_SET_MSI_INTR04_DEFAULT 0x00000001
-
-/* PCIE_0_INTR2 :: PCI_MASK_SET :: MSI_INTR03 [27:27] */
-#define BCHP_PCIE_0_INTR2_PCI_MASK_SET_MSI_INTR03_MASK 0x08000000
-#define BCHP_PCIE_0_INTR2_PCI_MASK_SET_MSI_INTR03_SHIFT 27
-#define BCHP_PCIE_0_INTR2_PCI_MASK_SET_MSI_INTR03_DEFAULT 0x00000001
-
-/* PCIE_0_INTR2 :: PCI_MASK_SET :: MSI_INTR02 [26:26] */
-#define BCHP_PCIE_0_INTR2_PCI_MASK_SET_MSI_INTR02_MASK 0x04000000
-#define BCHP_PCIE_0_INTR2_PCI_MASK_SET_MSI_INTR02_SHIFT 26
-#define BCHP_PCIE_0_INTR2_PCI_MASK_SET_MSI_INTR02_DEFAULT 0x00000001
-
-/* PCIE_0_INTR2 :: PCI_MASK_SET :: MSI_INTR01 [25:25] */
-#define BCHP_PCIE_0_INTR2_PCI_MASK_SET_MSI_INTR01_MASK 0x02000000
-#define BCHP_PCIE_0_INTR2_PCI_MASK_SET_MSI_INTR01_SHIFT 25
-#define BCHP_PCIE_0_INTR2_PCI_MASK_SET_MSI_INTR01_DEFAULT 0x00000001
-
-/* PCIE_0_INTR2 :: PCI_MASK_SET :: MSI_INTR00 [24:24] */
-#define BCHP_PCIE_0_INTR2_PCI_MASK_SET_MSI_INTR00_MASK 0x01000000
-#define BCHP_PCIE_0_INTR2_PCI_MASK_SET_MSI_INTR00_SHIFT 24
-#define BCHP_PCIE_0_INTR2_PCI_MASK_SET_MSI_INTR00_DEFAULT 0x00000001
-
-/* PCIE_0_INTR2 :: PCI_MASK_SET :: UNASSIGNED_23 [23:23] */
-#define BCHP_PCIE_0_INTR2_PCI_MASK_SET_UNASSIGNED_23_MASK 0x00800000
-#define BCHP_PCIE_0_INTR2_PCI_MASK_SET_UNASSIGNED_23_SHIFT 23
-#define BCHP_PCIE_0_INTR2_PCI_MASK_SET_UNASSIGNED_23_DEFAULT 0x00000001
-
-/* PCIE_0_INTR2 :: PCI_MASK_SET :: UNASSIGNED_22 [22:22] */
-#define BCHP_PCIE_0_INTR2_PCI_MASK_SET_UNASSIGNED_22_MASK 0x00400000
-#define BCHP_PCIE_0_INTR2_PCI_MASK_SET_UNASSIGNED_22_SHIFT 22
-#define BCHP_PCIE_0_INTR2_PCI_MASK_SET_UNASSIGNED_22_DEFAULT 0x00000001
-
-/* PCIE_0_INTR2 :: PCI_MASK_SET :: UNASSIGNED_21 [21:21] */
-#define BCHP_PCIE_0_INTR2_PCI_MASK_SET_UNASSIGNED_21_MASK 0x00200000
-#define BCHP_PCIE_0_INTR2_PCI_MASK_SET_UNASSIGNED_21_SHIFT 21
-#define BCHP_PCIE_0_INTR2_PCI_MASK_SET_UNASSIGNED_21_DEFAULT 0x00000001
-
-/* PCIE_0_INTR2 :: PCI_MASK_SET :: UNASSIGNED_20 [20:20] */
-#define BCHP_PCIE_0_INTR2_PCI_MASK_SET_UNASSIGNED_20_MASK 0x00100000
-#define BCHP_PCIE_0_INTR2_PCI_MASK_SET_UNASSIGNED_20_SHIFT 20
-#define BCHP_PCIE_0_INTR2_PCI_MASK_SET_UNASSIGNED_20_DEFAULT 0x00000001
-
-/* PCIE_0_INTR2 :: PCI_MASK_SET :: MAILBOX_3 [19:19] */
-#define BCHP_PCIE_0_INTR2_PCI_MASK_SET_MAILBOX_3_MASK 0x00080000
-#define BCHP_PCIE_0_INTR2_PCI_MASK_SET_MAILBOX_3_SHIFT 19
-#define BCHP_PCIE_0_INTR2_PCI_MASK_SET_MAILBOX_3_DEFAULT 0x00000001
-
-/* PCIE_0_INTR2 :: PCI_MASK_SET :: MAILBOX_2 [18:18] */
-#define BCHP_PCIE_0_INTR2_PCI_MASK_SET_MAILBOX_2_MASK 0x00040000
-#define BCHP_PCIE_0_INTR2_PCI_MASK_SET_MAILBOX_2_SHIFT 18
-#define BCHP_PCIE_0_INTR2_PCI_MASK_SET_MAILBOX_2_DEFAULT 0x00000001
-
-/* PCIE_0_INTR2 :: PCI_MASK_SET :: MAILBOX_1 [17:17] */
-#define BCHP_PCIE_0_INTR2_PCI_MASK_SET_MAILBOX_1_MASK 0x00020000
-#define BCHP_PCIE_0_INTR2_PCI_MASK_SET_MAILBOX_1_SHIFT 17
-#define BCHP_PCIE_0_INTR2_PCI_MASK_SET_MAILBOX_1_DEFAULT 0x00000001
-
-/* PCIE_0_INTR2 :: PCI_MASK_SET :: MAILBOX_0 [16:16] */
-#define BCHP_PCIE_0_INTR2_PCI_MASK_SET_MAILBOX_0_MASK 0x00010000
-#define BCHP_PCIE_0_INTR2_PCI_MASK_SET_MAILBOX_0_SHIFT 16
-#define BCHP_PCIE_0_INTR2_PCI_MASK_SET_MAILBOX_0_DEFAULT 0x00000001
-
-/* PCIE_0_INTR2 :: PCI_MASK_SET :: PCIE_MSTR_FWD_ERR [15:15] */
-#define BCHP_PCIE_0_INTR2_PCI_MASK_SET_PCIE_MSTR_FWD_ERR_MASK 0x00008000
-#define BCHP_PCIE_0_INTR2_PCI_MASK_SET_PCIE_MSTR_FWD_ERR_SHIFT 15
-#define BCHP_PCIE_0_INTR2_PCI_MASK_SET_PCIE_MSTR_FWD_ERR_DEFAULT 0x00000001
-
-/* PCIE_0_INTR2 :: PCI_MASK_SET :: PCIE_MSTR_RETRY_TIMEOUT [14:14] */
-#define BCHP_PCIE_0_INTR2_PCI_MASK_SET_PCIE_MSTR_RETRY_TIMEOUT_MASK 0x00004000
-#define BCHP_PCIE_0_INTR2_PCI_MASK_SET_PCIE_MSTR_RETRY_TIMEOUT_SHIFT 14
-#define BCHP_PCIE_0_INTR2_PCI_MASK_SET_PCIE_MSTR_RETRY_TIMEOUT_DEFAULT 0x00000001
-
-/* PCIE_0_INTR2 :: PCI_MASK_SET :: PCIE_MSTR_CA_ATTN [13:13] */
-#define BCHP_PCIE_0_INTR2_PCI_MASK_SET_PCIE_MSTR_CA_ATTN_MASK 0x00002000
-#define BCHP_PCIE_0_INTR2_PCI_MASK_SET_PCIE_MSTR_CA_ATTN_SHIFT 13
-#define BCHP_PCIE_0_INTR2_PCI_MASK_SET_PCIE_MSTR_CA_ATTN_DEFAULT 0x00000001
-
-/* PCIE_0_INTR2 :: PCI_MASK_SET :: PCIE_MSTR_UR_ATTN [12:12] */
-#define BCHP_PCIE_0_INTR2_PCI_MASK_SET_PCIE_MSTR_UR_ATTN_MASK 0x00001000
-#define BCHP_PCIE_0_INTR2_PCI_MASK_SET_PCIE_MSTR_UR_ATTN_SHIFT 12
-#define BCHP_PCIE_0_INTR2_PCI_MASK_SET_PCIE_MSTR_UR_ATTN_DEFAULT 0x00000001
-
-/* PCIE_0_INTR2 :: PCI_MASK_SET :: UNASSIGNED_11 [11:11] */
-#define BCHP_PCIE_0_INTR2_PCI_MASK_SET_UNASSIGNED_11_MASK 0x00000800
-#define BCHP_PCIE_0_INTR2_PCI_MASK_SET_UNASSIGNED_11_SHIFT 11
-#define BCHP_PCIE_0_INTR2_PCI_MASK_SET_UNASSIGNED_11_DEFAULT 0x00000001
-
-/* PCIE_0_INTR2 :: PCI_MASK_SET :: UNASSIGNED_10 [10:10] */
-#define BCHP_PCIE_0_INTR2_PCI_MASK_SET_UNASSIGNED_10_MASK 0x00000400
-#define BCHP_PCIE_0_INTR2_PCI_MASK_SET_UNASSIGNED_10_SHIFT 10
-#define BCHP_PCIE_0_INTR2_PCI_MASK_SET_UNASSIGNED_10_DEFAULT 0x00000001
-
-/* PCIE_0_INTR2 :: PCI_MASK_SET :: PCIE_TGT_BAD_ACCESS [09:09] */
-#define BCHP_PCIE_0_INTR2_PCI_MASK_SET_PCIE_TGT_BAD_ACCESS_MASK 0x00000200
-#define BCHP_PCIE_0_INTR2_PCI_MASK_SET_PCIE_TGT_BAD_ACCESS_SHIFT 9
-#define BCHP_PCIE_0_INTR2_PCI_MASK_SET_PCIE_TGT_BAD_ACCESS_DEFAULT 0x00000001
-
-/* PCIE_0_INTR2 :: PCI_MASK_SET :: PCIE_TGT_BAD_ADDRESS [08:08] */
-#define BCHP_PCIE_0_INTR2_PCI_MASK_SET_PCIE_TGT_BAD_ADDRESS_MASK 0x00000100
-#define BCHP_PCIE_0_INTR2_PCI_MASK_SET_PCIE_TGT_BAD_ADDRESS_SHIFT 8
-#define BCHP_PCIE_0_INTR2_PCI_MASK_SET_PCIE_TGT_BAD_ADDRESS_DEFAULT 0x00000001
-
-/* PCIE_0_INTR2 :: PCI_MASK_SET :: L1_RX_DMA_ERR_INTR [07:07] */
-#define BCHP_PCIE_0_INTR2_PCI_MASK_SET_L1_RX_DMA_ERR_INTR_MASK 0x00000080
-#define BCHP_PCIE_0_INTR2_PCI_MASK_SET_L1_RX_DMA_ERR_INTR_SHIFT 7
-#define BCHP_PCIE_0_INTR2_PCI_MASK_SET_L1_RX_DMA_ERR_INTR_DEFAULT 0x00000001
-
-/* PCIE_0_INTR2 :: PCI_MASK_SET :: L1_RX_DMA_DONE_INTR [06:06] */
-#define BCHP_PCIE_0_INTR2_PCI_MASK_SET_L1_RX_DMA_DONE_INTR_MASK 0x00000040
-#define BCHP_PCIE_0_INTR2_PCI_MASK_SET_L1_RX_DMA_DONE_INTR_SHIFT 6
-#define BCHP_PCIE_0_INTR2_PCI_MASK_SET_L1_RX_DMA_DONE_INTR_DEFAULT 0x00000001
-
-/* PCIE_0_INTR2 :: PCI_MASK_SET :: L1_TX_DMA_ERR_INTR [05:05] */
-#define BCHP_PCIE_0_INTR2_PCI_MASK_SET_L1_TX_DMA_ERR_INTR_MASK 0x00000020
-#define BCHP_PCIE_0_INTR2_PCI_MASK_SET_L1_TX_DMA_ERR_INTR_SHIFT 5
-#define BCHP_PCIE_0_INTR2_PCI_MASK_SET_L1_TX_DMA_ERR_INTR_DEFAULT 0x00000001
-
-/* PCIE_0_INTR2 :: PCI_MASK_SET :: L1_TX_DMA_DONE_INTR [04:04] */
-#define BCHP_PCIE_0_INTR2_PCI_MASK_SET_L1_TX_DMA_DONE_INTR_MASK 0x00000010
-#define BCHP_PCIE_0_INTR2_PCI_MASK_SET_L1_TX_DMA_DONE_INTR_SHIFT 4
-#define BCHP_PCIE_0_INTR2_PCI_MASK_SET_L1_TX_DMA_DONE_INTR_DEFAULT 0x00000001
-
-/* PCIE_0_INTR2 :: PCI_MASK_SET :: L0_RX_DMA_ERR_INTR [03:03] */
-#define BCHP_PCIE_0_INTR2_PCI_MASK_SET_L0_RX_DMA_ERR_INTR_MASK 0x00000008
-#define BCHP_PCIE_0_INTR2_PCI_MASK_SET_L0_RX_DMA_ERR_INTR_SHIFT 3
-#define BCHP_PCIE_0_INTR2_PCI_MASK_SET_L0_RX_DMA_ERR_INTR_DEFAULT 0x00000001
-
-/* PCIE_0_INTR2 :: PCI_MASK_SET :: L0_RX_DMA_DONE_INTR [02:02] */
-#define BCHP_PCIE_0_INTR2_PCI_MASK_SET_L0_RX_DMA_DONE_INTR_MASK 0x00000004
-#define BCHP_PCIE_0_INTR2_PCI_MASK_SET_L0_RX_DMA_DONE_INTR_SHIFT 2
-#define BCHP_PCIE_0_INTR2_PCI_MASK_SET_L0_RX_DMA_DONE_INTR_DEFAULT 0x00000001
-
-/* PCIE_0_INTR2 :: PCI_MASK_SET :: L0_TX_DMA_ERR_INTR [01:01] */
-#define BCHP_PCIE_0_INTR2_PCI_MASK_SET_L0_TX_DMA_ERR_INTR_MASK 0x00000002
-#define BCHP_PCIE_0_INTR2_PCI_MASK_SET_L0_TX_DMA_ERR_INTR_SHIFT 1
-#define BCHP_PCIE_0_INTR2_PCI_MASK_SET_L0_TX_DMA_ERR_INTR_DEFAULT 0x00000001
-
-/* PCIE_0_INTR2 :: PCI_MASK_SET :: L0_TX_DMA_DONE_INTR [00:00] */
-#define BCHP_PCIE_0_INTR2_PCI_MASK_SET_L0_TX_DMA_DONE_INTR_MASK 0x00000001
-#define BCHP_PCIE_0_INTR2_PCI_MASK_SET_L0_TX_DMA_DONE_INTR_SHIFT 0
-#define BCHP_PCIE_0_INTR2_PCI_MASK_SET_L0_TX_DMA_DONE_INTR_DEFAULT 0x00000001
-
-/***************************************************************************
- *PCI_MASK_CLEAR - PCI interrupt Mask Clear Register
- ***************************************************************************/
-/* PCIE_0_INTR2 :: PCI_MASK_CLEAR :: MSI_INTR07 [31:31] */
-#define BCHP_PCIE_0_INTR2_PCI_MASK_CLEAR_MSI_INTR07_MASK 0x80000000
-#define BCHP_PCIE_0_INTR2_PCI_MASK_CLEAR_MSI_INTR07_SHIFT 31
-#define BCHP_PCIE_0_INTR2_PCI_MASK_CLEAR_MSI_INTR07_DEFAULT 0x00000001
-
-/* PCIE_0_INTR2 :: PCI_MASK_CLEAR :: MSI_INTR06 [30:30] */
-#define BCHP_PCIE_0_INTR2_PCI_MASK_CLEAR_MSI_INTR06_MASK 0x40000000
-#define BCHP_PCIE_0_INTR2_PCI_MASK_CLEAR_MSI_INTR06_SHIFT 30
-#define BCHP_PCIE_0_INTR2_PCI_MASK_CLEAR_MSI_INTR06_DEFAULT 0x00000001
-
-/* PCIE_0_INTR2 :: PCI_MASK_CLEAR :: MSI_INTR05 [29:29] */
-#define BCHP_PCIE_0_INTR2_PCI_MASK_CLEAR_MSI_INTR05_MASK 0x20000000
-#define BCHP_PCIE_0_INTR2_PCI_MASK_CLEAR_MSI_INTR05_SHIFT 29
-#define BCHP_PCIE_0_INTR2_PCI_MASK_CLEAR_MSI_INTR05_DEFAULT 0x00000001
-
-/* PCIE_0_INTR2 :: PCI_MASK_CLEAR :: MSI_INTR04 [28:28] */
-#define BCHP_PCIE_0_INTR2_PCI_MASK_CLEAR_MSI_INTR04_MASK 0x10000000
-#define BCHP_PCIE_0_INTR2_PCI_MASK_CLEAR_MSI_INTR04_SHIFT 28
-#define BCHP_PCIE_0_INTR2_PCI_MASK_CLEAR_MSI_INTR04_DEFAULT 0x00000001
-
-/* PCIE_0_INTR2 :: PCI_MASK_CLEAR :: MSI_INTR03 [27:27] */
-#define BCHP_PCIE_0_INTR2_PCI_MASK_CLEAR_MSI_INTR03_MASK 0x08000000
-#define BCHP_PCIE_0_INTR2_PCI_MASK_CLEAR_MSI_INTR03_SHIFT 27
-#define BCHP_PCIE_0_INTR2_PCI_MASK_CLEAR_MSI_INTR03_DEFAULT 0x00000001
-
-/* PCIE_0_INTR2 :: PCI_MASK_CLEAR :: MSI_INTR02 [26:26] */
-#define BCHP_PCIE_0_INTR2_PCI_MASK_CLEAR_MSI_INTR02_MASK 0x04000000
-#define BCHP_PCIE_0_INTR2_PCI_MASK_CLEAR_MSI_INTR02_SHIFT 26
-#define BCHP_PCIE_0_INTR2_PCI_MASK_CLEAR_MSI_INTR02_DEFAULT 0x00000001
-
-/* PCIE_0_INTR2 :: PCI_MASK_CLEAR :: MSI_INTR01 [25:25] */
-#define BCHP_PCIE_0_INTR2_PCI_MASK_CLEAR_MSI_INTR01_MASK 0x02000000
-#define BCHP_PCIE_0_INTR2_PCI_MASK_CLEAR_MSI_INTR01_SHIFT 25
-#define BCHP_PCIE_0_INTR2_PCI_MASK_CLEAR_MSI_INTR01_DEFAULT 0x00000001
-
-/* PCIE_0_INTR2 :: PCI_MASK_CLEAR :: MSI_INTR00 [24:24] */
-#define BCHP_PCIE_0_INTR2_PCI_MASK_CLEAR_MSI_INTR00_MASK 0x01000000
-#define BCHP_PCIE_0_INTR2_PCI_MASK_CLEAR_MSI_INTR00_SHIFT 24
-#define BCHP_PCIE_0_INTR2_PCI_MASK_CLEAR_MSI_INTR00_DEFAULT 0x00000001
-
-/* PCIE_0_INTR2 :: PCI_MASK_CLEAR :: UNASSIGNED_23 [23:23] */
-#define BCHP_PCIE_0_INTR2_PCI_MASK_CLEAR_UNASSIGNED_23_MASK 0x00800000
-#define BCHP_PCIE_0_INTR2_PCI_MASK_CLEAR_UNASSIGNED_23_SHIFT 23
-#define BCHP_PCIE_0_INTR2_PCI_MASK_CLEAR_UNASSIGNED_23_DEFAULT 0x00000001
-
-/* PCIE_0_INTR2 :: PCI_MASK_CLEAR :: UNASSIGNED_22 [22:22] */
-#define BCHP_PCIE_0_INTR2_PCI_MASK_CLEAR_UNASSIGNED_22_MASK 0x00400000
-#define BCHP_PCIE_0_INTR2_PCI_MASK_CLEAR_UNASSIGNED_22_SHIFT 22
-#define BCHP_PCIE_0_INTR2_PCI_MASK_CLEAR_UNASSIGNED_22_DEFAULT 0x00000001
-
-/* PCIE_0_INTR2 :: PCI_MASK_CLEAR :: UNASSIGNED_21 [21:21] */
-#define BCHP_PCIE_0_INTR2_PCI_MASK_CLEAR_UNASSIGNED_21_MASK 0x00200000
-#define BCHP_PCIE_0_INTR2_PCI_MASK_CLEAR_UNASSIGNED_21_SHIFT 21
-#define BCHP_PCIE_0_INTR2_PCI_MASK_CLEAR_UNASSIGNED_21_DEFAULT 0x00000001
-
-/* PCIE_0_INTR2 :: PCI_MASK_CLEAR :: UNASSIGNED_20 [20:20] */
-#define BCHP_PCIE_0_INTR2_PCI_MASK_CLEAR_UNASSIGNED_20_MASK 0x00100000
-#define BCHP_PCIE_0_INTR2_PCI_MASK_CLEAR_UNASSIGNED_20_SHIFT 20
-#define BCHP_PCIE_0_INTR2_PCI_MASK_CLEAR_UNASSIGNED_20_DEFAULT 0x00000001
-
-/* PCIE_0_INTR2 :: PCI_MASK_CLEAR :: MAILBOX_3 [19:19] */
-#define BCHP_PCIE_0_INTR2_PCI_MASK_CLEAR_MAILBOX_3_MASK 0x00080000
-#define BCHP_PCIE_0_INTR2_PCI_MASK_CLEAR_MAILBOX_3_SHIFT 19
-#define BCHP_PCIE_0_INTR2_PCI_MASK_CLEAR_MAILBOX_3_DEFAULT 0x00000001
-
-/* PCIE_0_INTR2 :: PCI_MASK_CLEAR :: MAILBOX_2 [18:18] */
-#define BCHP_PCIE_0_INTR2_PCI_MASK_CLEAR_MAILBOX_2_MASK 0x00040000
-#define BCHP_PCIE_0_INTR2_PCI_MASK_CLEAR_MAILBOX_2_SHIFT 18
-#define BCHP_PCIE_0_INTR2_PCI_MASK_CLEAR_MAILBOX_2_DEFAULT 0x00000001
-
-/* PCIE_0_INTR2 :: PCI_MASK_CLEAR :: MAILBOX_1 [17:17] */
-#define BCHP_PCIE_0_INTR2_PCI_MASK_CLEAR_MAILBOX_1_MASK 0x00020000
-#define BCHP_PCIE_0_INTR2_PCI_MASK_CLEAR_MAILBOX_1_SHIFT 17
-#define BCHP_PCIE_0_INTR2_PCI_MASK_CLEAR_MAILBOX_1_DEFAULT 0x00000001
-
-/* PCIE_0_INTR2 :: PCI_MASK_CLEAR :: MAILBOX_0 [16:16] */
-#define BCHP_PCIE_0_INTR2_PCI_MASK_CLEAR_MAILBOX_0_MASK 0x00010000
-#define BCHP_PCIE_0_INTR2_PCI_MASK_CLEAR_MAILBOX_0_SHIFT 16
-#define BCHP_PCIE_0_INTR2_PCI_MASK_CLEAR_MAILBOX_0_DEFAULT 0x00000001
-
-/* PCIE_0_INTR2 :: PCI_MASK_CLEAR :: PCIE_MSTR_FWD_ERR [15:15] */
-#define BCHP_PCIE_0_INTR2_PCI_MASK_CLEAR_PCIE_MSTR_FWD_ERR_MASK 0x00008000
-#define BCHP_PCIE_0_INTR2_PCI_MASK_CLEAR_PCIE_MSTR_FWD_ERR_SHIFT 15
-#define BCHP_PCIE_0_INTR2_PCI_MASK_CLEAR_PCIE_MSTR_FWD_ERR_DEFAULT 0x00000001
-
-/* PCIE_0_INTR2 :: PCI_MASK_CLEAR :: PCIE_MSTR_RETRY_TIMEOUT [14:14] */
-#define BCHP_PCIE_0_INTR2_PCI_MASK_CLEAR_PCIE_MSTR_RETRY_TIMEOUT_MASK 0x00004000
-#define BCHP_PCIE_0_INTR2_PCI_MASK_CLEAR_PCIE_MSTR_RETRY_TIMEOUT_SHIFT 14
-#define BCHP_PCIE_0_INTR2_PCI_MASK_CLEAR_PCIE_MSTR_RETRY_TIMEOUT_DEFAULT 0x00000001
-
-/* PCIE_0_INTR2 :: PCI_MASK_CLEAR :: PCIE_MSTR_CA_ATTN [13:13] */
-#define BCHP_PCIE_0_INTR2_PCI_MASK_CLEAR_PCIE_MSTR_CA_ATTN_MASK 0x00002000
-#define BCHP_PCIE_0_INTR2_PCI_MASK_CLEAR_PCIE_MSTR_CA_ATTN_SHIFT 13
-#define BCHP_PCIE_0_INTR2_PCI_MASK_CLEAR_PCIE_MSTR_CA_ATTN_DEFAULT 0x00000001
-
-/* PCIE_0_INTR2 :: PCI_MASK_CLEAR :: PCIE_MSTR_UR_ATTN [12:12] */
-#define BCHP_PCIE_0_INTR2_PCI_MASK_CLEAR_PCIE_MSTR_UR_ATTN_MASK 0x00001000
-#define BCHP_PCIE_0_INTR2_PCI_MASK_CLEAR_PCIE_MSTR_UR_ATTN_SHIFT 12
-#define BCHP_PCIE_0_INTR2_PCI_MASK_CLEAR_PCIE_MSTR_UR_ATTN_DEFAULT 0x00000001
-
-/* PCIE_0_INTR2 :: PCI_MASK_CLEAR :: UNASSIGNED_11 [11:11] */
-#define BCHP_PCIE_0_INTR2_PCI_MASK_CLEAR_UNASSIGNED_11_MASK 0x00000800
-#define BCHP_PCIE_0_INTR2_PCI_MASK_CLEAR_UNASSIGNED_11_SHIFT 11
-#define BCHP_PCIE_0_INTR2_PCI_MASK_CLEAR_UNASSIGNED_11_DEFAULT 0x00000001
-
-/* PCIE_0_INTR2 :: PCI_MASK_CLEAR :: UNASSIGNED_10 [10:10] */
-#define BCHP_PCIE_0_INTR2_PCI_MASK_CLEAR_UNASSIGNED_10_MASK 0x00000400
-#define BCHP_PCIE_0_INTR2_PCI_MASK_CLEAR_UNASSIGNED_10_SHIFT 10
-#define BCHP_PCIE_0_INTR2_PCI_MASK_CLEAR_UNASSIGNED_10_DEFAULT 0x00000001
-
-/* PCIE_0_INTR2 :: PCI_MASK_CLEAR :: PCIE_TGT_BAD_ACCESS [09:09] */
-#define BCHP_PCIE_0_INTR2_PCI_MASK_CLEAR_PCIE_TGT_BAD_ACCESS_MASK 0x00000200
-#define BCHP_PCIE_0_INTR2_PCI_MASK_CLEAR_PCIE_TGT_BAD_ACCESS_SHIFT 9
-#define BCHP_PCIE_0_INTR2_PCI_MASK_CLEAR_PCIE_TGT_BAD_ACCESS_DEFAULT 0x00000001
-
-/* PCIE_0_INTR2 :: PCI_MASK_CLEAR :: PCIE_TGT_BAD_ADDRESS [08:08] */
-#define BCHP_PCIE_0_INTR2_PCI_MASK_CLEAR_PCIE_TGT_BAD_ADDRESS_MASK 0x00000100
-#define BCHP_PCIE_0_INTR2_PCI_MASK_CLEAR_PCIE_TGT_BAD_ADDRESS_SHIFT 8
-#define BCHP_PCIE_0_INTR2_PCI_MASK_CLEAR_PCIE_TGT_BAD_ADDRESS_DEFAULT 0x00000001
-
-/* PCIE_0_INTR2 :: PCI_MASK_CLEAR :: L1_RX_DMA_ERR_INTR [07:07] */
-#define BCHP_PCIE_0_INTR2_PCI_MASK_CLEAR_L1_RX_DMA_ERR_INTR_MASK 0x00000080
-#define BCHP_PCIE_0_INTR2_PCI_MASK_CLEAR_L1_RX_DMA_ERR_INTR_SHIFT 7
-#define BCHP_PCIE_0_INTR2_PCI_MASK_CLEAR_L1_RX_DMA_ERR_INTR_DEFAULT 0x00000001
-
-/* PCIE_0_INTR2 :: PCI_MASK_CLEAR :: L1_RX_DMA_DONE_INTR [06:06] */
-#define BCHP_PCIE_0_INTR2_PCI_MASK_CLEAR_L1_RX_DMA_DONE_INTR_MASK 0x00000040
-#define BCHP_PCIE_0_INTR2_PCI_MASK_CLEAR_L1_RX_DMA_DONE_INTR_SHIFT 6
-#define BCHP_PCIE_0_INTR2_PCI_MASK_CLEAR_L1_RX_DMA_DONE_INTR_DEFAULT 0x00000001
-
-/* PCIE_0_INTR2 :: PCI_MASK_CLEAR :: L1_TX_DMA_ERR_INTR [05:05] */
-#define BCHP_PCIE_0_INTR2_PCI_MASK_CLEAR_L1_TX_DMA_ERR_INTR_MASK 0x00000020
-#define BCHP_PCIE_0_INTR2_PCI_MASK_CLEAR_L1_TX_DMA_ERR_INTR_SHIFT 5
-#define BCHP_PCIE_0_INTR2_PCI_MASK_CLEAR_L1_TX_DMA_ERR_INTR_DEFAULT 0x00000001
-
-/* PCIE_0_INTR2 :: PCI_MASK_CLEAR :: L1_TX_DMA_DONE_INTR [04:04] */
-#define BCHP_PCIE_0_INTR2_PCI_MASK_CLEAR_L1_TX_DMA_DONE_INTR_MASK 0x00000010
-#define BCHP_PCIE_0_INTR2_PCI_MASK_CLEAR_L1_TX_DMA_DONE_INTR_SHIFT 4
-#define BCHP_PCIE_0_INTR2_PCI_MASK_CLEAR_L1_TX_DMA_DONE_INTR_DEFAULT 0x00000001
-
-/* PCIE_0_INTR2 :: PCI_MASK_CLEAR :: L0_RX_DMA_ERR_INTR [03:03] */
-#define BCHP_PCIE_0_INTR2_PCI_MASK_CLEAR_L0_RX_DMA_ERR_INTR_MASK 0x00000008
-#define BCHP_PCIE_0_INTR2_PCI_MASK_CLEAR_L0_RX_DMA_ERR_INTR_SHIFT 3
-#define BCHP_PCIE_0_INTR2_PCI_MASK_CLEAR_L0_RX_DMA_ERR_INTR_DEFAULT 0x00000001
-
-/* PCIE_0_INTR2 :: PCI_MASK_CLEAR :: L0_RX_DMA_DONE_INTR [02:02] */
-#define BCHP_PCIE_0_INTR2_PCI_MASK_CLEAR_L0_RX_DMA_DONE_INTR_MASK 0x00000004
-#define BCHP_PCIE_0_INTR2_PCI_MASK_CLEAR_L0_RX_DMA_DONE_INTR_SHIFT 2
-#define BCHP_PCIE_0_INTR2_PCI_MASK_CLEAR_L0_RX_DMA_DONE_INTR_DEFAULT 0x00000001
-
-/* PCIE_0_INTR2 :: PCI_MASK_CLEAR :: L0_TX_DMA_ERR_INTR [01:01] */
-#define BCHP_PCIE_0_INTR2_PCI_MASK_CLEAR_L0_TX_DMA_ERR_INTR_MASK 0x00000002
-#define BCHP_PCIE_0_INTR2_PCI_MASK_CLEAR_L0_TX_DMA_ERR_INTR_SHIFT 1
-#define BCHP_PCIE_0_INTR2_PCI_MASK_CLEAR_L0_TX_DMA_ERR_INTR_DEFAULT 0x00000001
-
-/* PCIE_0_INTR2 :: PCI_MASK_CLEAR :: L0_TX_DMA_DONE_INTR [00:00] */
-#define BCHP_PCIE_0_INTR2_PCI_MASK_CLEAR_L0_TX_DMA_DONE_INTR_MASK 0x00000001
-#define BCHP_PCIE_0_INTR2_PCI_MASK_CLEAR_L0_TX_DMA_DONE_INTR_SHIFT 0
-#define BCHP_PCIE_0_INTR2_PCI_MASK_CLEAR_L0_TX_DMA_DONE_INTR_DEFAULT 0x00000001
-
-#endif /* #ifndef BCHP_PCIE_0_INTR2_H__ */
-
-/* End of File */
diff --git a/include/linux/brcmstb/7439a0/bchp_pcie_0_misc.h b/include/linux/brcmstb/7439a0/bchp_pcie_0_misc.h
deleted file mode 100644
index 2489853..0000000
--- a/include/linux/brcmstb/7439a0/bchp_pcie_0_misc.h
+++ /dev/null
@@ -1,969 +0,0 @@
-/***************************************************************************
- * Copyright (c) 1999-2013, Broadcom Corporation
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
- *
- * Module Description:
- * DO NOT EDIT THIS FILE DIRECTLY
- *
- * This module was generated magically with RDB from a source description
- * file. You must edit the source file for changes to be made to this file.
- *
- *
- * Date: Generated on Tue Apr 16 03:26:52 2013
- * MD5 Checksum d41d8cd98f00b204e9800998ecf8427e
- *
- * Compiled with: RDB Utility combo_header.pl
- * RDB Parser 3.0
- * unknown unknown
- * Perl Interpreter 5.008008
- * Operating System linux
- *
- * Revision History:
- *
- * $brcm_Log: $
- *
- ***************************************************************************/
-
-#ifndef BCHP_PCIE_0_MISC_H__
-#define BCHP_PCIE_0_MISC_H__
-
-/***************************************************************************
- *PCIE_0_MISC - PCI-E Miscellaneous Registers
- ***************************************************************************/
-#define BCHP_PCIE_0_MISC_RESET_CTRL 0x00474000 /* Reset Control Register */
-#define BCHP_PCIE_0_MISC_ECO_CTRL_CORE 0x00474004 /* ECO Core Reset Control Register */
-#define BCHP_PCIE_0_MISC_MISC_CTRL 0x00474008 /* MISC Control Register */
-#define BCHP_PCIE_0_MISC_CPU_2_PCIE_MEM_WIN0_LO 0x0047400c /* CPU to PCIe Memory Window 0 Low */
-#define BCHP_PCIE_0_MISC_CPU_2_PCIE_MEM_WIN0_HI 0x00474010 /* CPU to PCIe Memory Window 0 High */
-#define BCHP_PCIE_0_MISC_CPU_2_PCIE_MEM_WIN1_LO 0x00474014 /* CPU to PCIe Memory Window 1 Low */
-#define BCHP_PCIE_0_MISC_CPU_2_PCIE_MEM_WIN1_HI 0x00474018 /* CPU to PCIe Memory Window 1 High */
-#define BCHP_PCIE_0_MISC_CPU_2_PCIE_MEM_WIN2_LO 0x0047401c /* CPU to PCIe Memory Window 2 Low */
-#define BCHP_PCIE_0_MISC_CPU_2_PCIE_MEM_WIN2_HI 0x00474020 /* CPU to PCIe Memory Window 2 High */
-#define BCHP_PCIE_0_MISC_CPU_2_PCIE_MEM_WIN3_LO 0x00474024 /* CPU to PCIe Memory Window 3 Low */
-#define BCHP_PCIE_0_MISC_CPU_2_PCIE_MEM_WIN3_HI 0x00474028 /* CPU to PCIe Memory Window 3 High */
-#define BCHP_PCIE_0_MISC_RC_BAR1_CONFIG_LO 0x0047402c /* RC BAR1 Configuration Low Register */
-#define BCHP_PCIE_0_MISC_RC_BAR1_CONFIG_HI 0x00474030 /* RC BAR1 Configuration High Register */
-#define BCHP_PCIE_0_MISC_RC_BAR2_CONFIG_LO 0x00474034 /* RC BAR2 Configuration Low Register */
-#define BCHP_PCIE_0_MISC_RC_BAR2_CONFIG_HI 0x00474038 /* RC BAR2 Configuration High Register */
-#define BCHP_PCIE_0_MISC_RC_BAR3_CONFIG_LO 0x0047403c /* RC BAR3 Configuration Low Register */
-#define BCHP_PCIE_0_MISC_RC_BAR3_CONFIG_HI 0x00474040 /* RC BAR3 Configuration High Register */
-#define BCHP_PCIE_0_MISC_MSI_BAR_CONFIG_LO 0x00474044 /* Message Signaled Interrupt Base Address Low Register */
-#define BCHP_PCIE_0_MISC_MSI_BAR_CONFIG_HI 0x00474048 /* Message Signaled Interrupt Base Address High Register */
-#define BCHP_PCIE_0_MISC_MSI_DATA_CONFIG 0x0047404c /* Message Signaled Interrupt Data Configuration Register */
-#define BCHP_PCIE_0_MISC_RC_BAD_ADDRESS_LO 0x00474050 /* RC Bad Address Register Low */
-#define BCHP_PCIE_0_MISC_RC_BAD_ADDRESS_HI 0x00474054 /* RC Bad Address Register High */
-#define BCHP_PCIE_0_MISC_RC_BAD_DATA 0x00474058 /* RC Bad Data Register */
-#define BCHP_PCIE_0_MISC_RC_CONFIG_RETRY_TIMEOUT 0x0047405c /* RC Configuration Retry Timeout Register */
-#define BCHP_PCIE_0_MISC_EOI_CTRL 0x00474060 /* End of Interrupt Control Register */
-#define BCHP_PCIE_0_MISC_PCIE_CTRL 0x00474064 /* PCIe Control */
-#define BCHP_PCIE_0_MISC_PCIE_STATUS 0x00474068 /* PCIe Status */
-#define BCHP_PCIE_0_MISC_REVISION 0x0047406c /* PCIe Revision */
-#define BCHP_PCIE_0_MISC_CPU_2_PCIE_MEM_WIN0_BASE_LIMIT 0x00474070 /* CPU to PCIe Memory Window 0 base/limit */
-#define BCHP_PCIE_0_MISC_CPU_2_PCIE_MEM_WIN1_BASE_LIMIT 0x00474074 /* CPU to PCIe Memory Window 1 base/limit */
-#define BCHP_PCIE_0_MISC_CPU_2_PCIE_MEM_WIN2_BASE_LIMIT 0x00474078 /* CPU to PCIe Memory Window 2 base/limit */
-#define BCHP_PCIE_0_MISC_CPU_2_PCIE_MEM_WIN3_BASE_LIMIT 0x0047407c /* CPU to PCIe Memory Window 3 base/limit */
-#define BCHP_PCIE_0_MISC_CPU_2_PCIE_MEM_WIN0_BASE_HI 0x00474080 /* CPU to PCIe Memory Window 0 base high */
-#define BCHP_PCIE_0_MISC_CPU_2_PCIE_MEM_WIN0_LIMIT_HI 0x00474084 /* CPU to PCIe Memory Window 0 limit high */
-#define BCHP_PCIE_0_MISC_CPU_2_PCIE_MEM_WIN1_BASE_HI 0x00474088 /* CPU to PCIe Memory Window 1 base high */
-#define BCHP_PCIE_0_MISC_CPU_2_PCIE_MEM_WIN1_LIMIT_HI 0x0047408c /* CPU to PCIe Memory Window 1 limit high */
-#define BCHP_PCIE_0_MISC_CPU_2_PCIE_MEM_WIN2_BASE_HI 0x00474090 /* CPU to PCIe Memory Window 2 base high */
-#define BCHP_PCIE_0_MISC_CPU_2_PCIE_MEM_WIN2_LIMIT_HI 0x00474094 /* CPU to PCIe Memory Window 2 limit high */
-#define BCHP_PCIE_0_MISC_CPU_2_PCIE_MEM_WIN3_BASE_HI 0x00474098 /* CPU to PCIe Memory Window 3 base high */
-#define BCHP_PCIE_0_MISC_CPU_2_PCIE_MEM_WIN3_LIMIT_HI 0x0047409c /* CPU to PCIe Memory Window 3 limit high */
-#define BCHP_PCIE_0_MISC_MISC_CTRL_1 0x004740a0 /* MISC Control Register 1 */
-#define BCHP_PCIE_0_MISC_UBUS_CTRL 0x004740a4 /* UBUS Control */
-#define BCHP_PCIE_0_MISC_UBUS_TIMEOUT 0x004740a8 /* UBUS Timeout */
-#define BCHP_PCIE_0_MISC_UBUS_BAR1_CONFIG_REMAP 0x004740ac /* UBUS BAR1 System Bus Address Remap Register */
-#define BCHP_PCIE_0_MISC_UBUS_BAR1_CONFIG_REMAP_HI 0x004740b0 /* UBUS BAR2 System Bus Address Remap Register High */
-#define BCHP_PCIE_0_MISC_UBUS_BAR2_CONFIG_REMAP 0x004740b4 /* UBUS BAR2 System Bus Address Remap Register */
-#define BCHP_PCIE_0_MISC_UBUS_BAR2_CONFIG_REMAP_HI 0x004740b8 /* UBUS BAR2 System Bus Address Remap Register High */
-#define BCHP_PCIE_0_MISC_UBUS_BAR3_CONFIG_REMAP 0x004740bc /* UBUS BAR3 System Bus Address Remap Register */
-#define BCHP_PCIE_0_MISC_UBUS_BAR3_CONFIG_REMAP_HI 0x004740c0 /* UBUS BAR3 System Bus Address Remap Register High */
-#define BCHP_PCIE_0_MISC_UBUS_STATUS 0x004740c4 /* UBUS Status */
-
-/***************************************************************************
- *RESET_CTRL - Reset Control Register
- ***************************************************************************/
-/* PCIE_0_MISC :: RESET_CTRL :: reserved0 [31:01] */
-#define BCHP_PCIE_0_MISC_RESET_CTRL_reserved0_MASK 0xfffffffe
-#define BCHP_PCIE_0_MISC_RESET_CTRL_reserved0_SHIFT 1
-
-/* PCIE_0_MISC :: RESET_CTRL :: CORE_RESET [00:00] */
-#define BCHP_PCIE_0_MISC_RESET_CTRL_CORE_RESET_MASK 0x00000001
-#define BCHP_PCIE_0_MISC_RESET_CTRL_CORE_RESET_SHIFT 0
-#define BCHP_PCIE_0_MISC_RESET_CTRL_CORE_RESET_DEFAULT 0x00000000
-
-/***************************************************************************
- *ECO_CTRL_CORE - ECO Core Reset Control Register
- ***************************************************************************/
-/* PCIE_0_MISC :: ECO_CTRL_CORE :: reserved0 [31:16] */
-#define BCHP_PCIE_0_MISC_ECO_CTRL_CORE_reserved0_MASK 0xffff0000
-#define BCHP_PCIE_0_MISC_ECO_CTRL_CORE_reserved0_SHIFT 16
-
-/* PCIE_0_MISC :: ECO_CTRL_CORE :: ECO_CORE_RST_N [15:00] */
-#define BCHP_PCIE_0_MISC_ECO_CTRL_CORE_ECO_CORE_RST_N_MASK 0x0000ffff
-#define BCHP_PCIE_0_MISC_ECO_CTRL_CORE_ECO_CORE_RST_N_SHIFT 0
-#define BCHP_PCIE_0_MISC_ECO_CTRL_CORE_ECO_CORE_RST_N_DEFAULT 0x00000000
-
-/***************************************************************************
- *MISC_CTRL - MISC Control Register
- ***************************************************************************/
-/* PCIE_0_MISC :: MISC_CTRL :: SCB0_SIZE [31:27] */
-#define BCHP_PCIE_0_MISC_MISC_CTRL_SCB0_SIZE_MASK 0xf8000000
-#define BCHP_PCIE_0_MISC_MISC_CTRL_SCB0_SIZE_SHIFT 27
-#define BCHP_PCIE_0_MISC_MISC_CTRL_SCB0_SIZE_DEFAULT 0x00000000
-
-/* PCIE_0_MISC :: MISC_CTRL :: SCB1_SIZE [26:22] */
-#define BCHP_PCIE_0_MISC_MISC_CTRL_SCB1_SIZE_MASK 0x07c00000
-#define BCHP_PCIE_0_MISC_MISC_CTRL_SCB1_SIZE_SHIFT 22
-#define BCHP_PCIE_0_MISC_MISC_CTRL_SCB1_SIZE_DEFAULT 0x00000000
-
-/* PCIE_0_MISC :: MISC_CTRL :: MAX_BURST_SIZE [21:20] */
-#define BCHP_PCIE_0_MISC_MISC_CTRL_MAX_BURST_SIZE_MASK 0x00300000
-#define BCHP_PCIE_0_MISC_MISC_CTRL_MAX_BURST_SIZE_SHIFT 20
-#define BCHP_PCIE_0_MISC_MISC_CTRL_MAX_BURST_SIZE_DEFAULT 0x00000000
-
-/* PCIE_0_MISC :: MISC_CTRL :: BURST_ALIGN [19:19] */
-#define BCHP_PCIE_0_MISC_MISC_CTRL_BURST_ALIGN_MASK 0x00080000
-#define BCHP_PCIE_0_MISC_MISC_CTRL_BURST_ALIGN_SHIFT 19
-#define BCHP_PCIE_0_MISC_MISC_CTRL_BURST_ALIGN_DEFAULT 0x00000000
-
-/* PCIE_0_MISC :: MISC_CTRL :: TBD_OPTION_18 [18:18] */
-#define BCHP_PCIE_0_MISC_MISC_CTRL_TBD_OPTION_18_MASK 0x00040000
-#define BCHP_PCIE_0_MISC_MISC_CTRL_TBD_OPTION_18_SHIFT 18
-#define BCHP_PCIE_0_MISC_MISC_CTRL_TBD_OPTION_18_DEFAULT 0x00000000
-
-/* PCIE_0_MISC :: MISC_CTRL :: CSR_CFG_MODE [17:17] */
-#define BCHP_PCIE_0_MISC_MISC_CTRL_CSR_CFG_MODE_MASK 0x00020000
-#define BCHP_PCIE_0_MISC_MISC_CTRL_CSR_CFG_MODE_SHIFT 17
-#define BCHP_PCIE_0_MISC_MISC_CTRL_CSR_CFG_MODE_DEFAULT 0x00000000
-
-/* PCIE_0_MISC :: MISC_CTRL :: CSR_CFG_RETRY_EN [16:16] */
-#define BCHP_PCIE_0_MISC_MISC_CTRL_CSR_CFG_RETRY_EN_MASK 0x00010000
-#define BCHP_PCIE_0_MISC_MISC_CTRL_CSR_CFG_RETRY_EN_SHIFT 16
-#define BCHP_PCIE_0_MISC_MISC_CTRL_CSR_CFG_RETRY_EN_DEFAULT 0x00000000
-
-/* PCIE_0_MISC :: MISC_CTRL :: TBD_OPTION_15 [15:15] */
-#define BCHP_PCIE_0_MISC_MISC_CTRL_TBD_OPTION_15_MASK 0x00008000
-#define BCHP_PCIE_0_MISC_MISC_CTRL_TBD_OPTION_15_SHIFT 15
-#define BCHP_PCIE_0_MISC_MISC_CTRL_TBD_OPTION_15_DEFAULT 0x00000000
-
-/* PCIE_0_MISC :: MISC_CTRL :: TBD_OPTION_14 [14:14] */
-#define BCHP_PCIE_0_MISC_MISC_CTRL_TBD_OPTION_14_MASK 0x00004000
-#define BCHP_PCIE_0_MISC_MISC_CTRL_TBD_OPTION_14_SHIFT 14
-#define BCHP_PCIE_0_MISC_MISC_CTRL_TBD_OPTION_14_DEFAULT 0x00000000
-
-/* PCIE_0_MISC :: MISC_CTRL :: CFG_READ_UR_MODE [13:13] */
-#define BCHP_PCIE_0_MISC_MISC_CTRL_CFG_READ_UR_MODE_MASK 0x00002000
-#define BCHP_PCIE_0_MISC_MISC_CTRL_CFG_READ_UR_MODE_SHIFT 13
-#define BCHP_PCIE_0_MISC_MISC_CTRL_CFG_READ_UR_MODE_DEFAULT 0x00000000
-
-/* PCIE_0_MISC :: MISC_CTRL :: SCB_ACCESS_EN [12:12] */
-#define BCHP_PCIE_0_MISC_MISC_CTRL_SCB_ACCESS_EN_MASK 0x00001000
-#define BCHP_PCIE_0_MISC_MISC_CTRL_SCB_ACCESS_EN_SHIFT 12
-#define BCHP_PCIE_0_MISC_MISC_CTRL_SCB_ACCESS_EN_DEFAULT 0x00000000
-
-/* PCIE_0_MISC :: MISC_CTRL :: PCIE_IN_WR_COMBINE [11:11] */
-#define BCHP_PCIE_0_MISC_MISC_CTRL_PCIE_IN_WR_COMBINE_MASK 0x00000800
-#define BCHP_PCIE_0_MISC_MISC_CTRL_PCIE_IN_WR_COMBINE_SHIFT 11
-#define BCHP_PCIE_0_MISC_MISC_CTRL_PCIE_IN_WR_COMBINE_DEFAULT 0x00000000
-
-/* PCIE_0_MISC :: MISC_CTRL :: PCIE_RCB_MPS_MODE [10:10] */
-#define BCHP_PCIE_0_MISC_MISC_CTRL_PCIE_RCB_MPS_MODE_MASK 0x00000400
-#define BCHP_PCIE_0_MISC_MISC_CTRL_PCIE_RCB_MPS_MODE_SHIFT 10
-#define BCHP_PCIE_0_MISC_MISC_CTRL_PCIE_RCB_MPS_MODE_DEFAULT 0x00000000
-
-/* PCIE_0_MISC :: MISC_CTRL :: DESC_PRIORITY_EN [09:09] */
-#define BCHP_PCIE_0_MISC_MISC_CTRL_DESC_PRIORITY_EN_MASK 0x00000200
-#define BCHP_PCIE_0_MISC_MISC_CTRL_DESC_PRIORITY_EN_SHIFT 9
-#define BCHP_PCIE_0_MISC_MISC_CTRL_DESC_PRIORITY_EN_DEFAULT 0x00000000
-
-/* PCIE_0_MISC :: MISC_CTRL :: READ_PRIORITY_EN [08:08] */
-#define BCHP_PCIE_0_MISC_MISC_CTRL_READ_PRIORITY_EN_MASK 0x00000100
-#define BCHP_PCIE_0_MISC_MISC_CTRL_READ_PRIORITY_EN_SHIFT 8
-#define BCHP_PCIE_0_MISC_MISC_CTRL_READ_PRIORITY_EN_DEFAULT 0x00000000
-
-/* PCIE_0_MISC :: MISC_CTRL :: PCIE_RCB_64B_MODE [07:07] */
-#define BCHP_PCIE_0_MISC_MISC_CTRL_PCIE_RCB_64B_MODE_MASK 0x00000080
-#define BCHP_PCIE_0_MISC_MISC_CTRL_PCIE_RCB_64B_MODE_SHIFT 7
-#define BCHP_PCIE_0_MISC_MISC_CTRL_PCIE_RCB_64B_MODE_DEFAULT 0x00000000
-
-/* PCIE_0_MISC :: MISC_CTRL :: PCIE_OUT_CPL_RO [06:06] */
-#define BCHP_PCIE_0_MISC_MISC_CTRL_PCIE_OUT_CPL_RO_MASK 0x00000040
-#define BCHP_PCIE_0_MISC_MISC_CTRL_PCIE_OUT_CPL_RO_SHIFT 6
-#define BCHP_PCIE_0_MISC_MISC_CTRL_PCIE_OUT_CPL_RO_DEFAULT 0x00000000
-
-/* PCIE_0_MISC :: MISC_CTRL :: PCIE_IN_CPL_RO [05:05] */
-#define BCHP_PCIE_0_MISC_MISC_CTRL_PCIE_IN_CPL_RO_MASK 0x00000020
-#define BCHP_PCIE_0_MISC_MISC_CTRL_PCIE_IN_CPL_RO_SHIFT 5
-#define BCHP_PCIE_0_MISC_MISC_CTRL_PCIE_IN_CPL_RO_DEFAULT 0x00000000
-
-/* PCIE_0_MISC :: MISC_CTRL :: SCB2_SIZE [04:00] */
-#define BCHP_PCIE_0_MISC_MISC_CTRL_SCB2_SIZE_MASK 0x0000001f
-#define BCHP_PCIE_0_MISC_MISC_CTRL_SCB2_SIZE_SHIFT 0
-#define BCHP_PCIE_0_MISC_MISC_CTRL_SCB2_SIZE_DEFAULT 0x00000000
-
-/***************************************************************************
- *CPU_2_PCIE_MEM_WIN0_LO - CPU to PCIe Memory Window 0 Low
- ***************************************************************************/
-/* PCIE_0_MISC :: CPU_2_PCIE_MEM_WIN0_LO :: BASE_ADDR [31:20] */
-#define BCHP_PCIE_0_MISC_CPU_2_PCIE_MEM_WIN0_LO_BASE_ADDR_MASK 0xfff00000
-#define BCHP_PCIE_0_MISC_CPU_2_PCIE_MEM_WIN0_LO_BASE_ADDR_SHIFT 20
-#define BCHP_PCIE_0_MISC_CPU_2_PCIE_MEM_WIN0_LO_BASE_ADDR_DEFAULT 0x00000000
-
-/* PCIE_0_MISC :: CPU_2_PCIE_MEM_WIN0_LO :: reserved0 [19:02] */
-#define BCHP_PCIE_0_MISC_CPU_2_PCIE_MEM_WIN0_LO_reserved0_MASK 0x000ffffc
-#define BCHP_PCIE_0_MISC_CPU_2_PCIE_MEM_WIN0_LO_reserved0_SHIFT 2
-
-/* PCIE_0_MISC :: CPU_2_PCIE_MEM_WIN0_LO :: ENDIAN_MODE [01:00] */
-#define BCHP_PCIE_0_MISC_CPU_2_PCIE_MEM_WIN0_LO_ENDIAN_MODE_MASK 0x00000003
-#define BCHP_PCIE_0_MISC_CPU_2_PCIE_MEM_WIN0_LO_ENDIAN_MODE_SHIFT 0
-#define BCHP_PCIE_0_MISC_CPU_2_PCIE_MEM_WIN0_LO_ENDIAN_MODE_DEFAULT 0x00000000
-
-/***************************************************************************
- *CPU_2_PCIE_MEM_WIN0_HI - CPU to PCIe Memory Window 0 High
- ***************************************************************************/
-/* PCIE_0_MISC :: CPU_2_PCIE_MEM_WIN0_HI :: BASE_ADDR [31:00] */
-#define BCHP_PCIE_0_MISC_CPU_2_PCIE_MEM_WIN0_HI_BASE_ADDR_MASK 0xffffffff
-#define BCHP_PCIE_0_MISC_CPU_2_PCIE_MEM_WIN0_HI_BASE_ADDR_SHIFT 0
-#define BCHP_PCIE_0_MISC_CPU_2_PCIE_MEM_WIN0_HI_BASE_ADDR_DEFAULT 0x00000000
-
-/***************************************************************************
- *CPU_2_PCIE_MEM_WIN1_LO - CPU to PCIe Memory Window 1 Low
- ***************************************************************************/
-/* PCIE_0_MISC :: CPU_2_PCIE_MEM_WIN1_LO :: BASE_ADDR [31:20] */
-#define BCHP_PCIE_0_MISC_CPU_2_PCIE_MEM_WIN1_LO_BASE_ADDR_MASK 0xfff00000
-#define BCHP_PCIE_0_MISC_CPU_2_PCIE_MEM_WIN1_LO_BASE_ADDR_SHIFT 20
-#define BCHP_PCIE_0_MISC_CPU_2_PCIE_MEM_WIN1_LO_BASE_ADDR_DEFAULT 0x00000000
-
-/* PCIE_0_MISC :: CPU_2_PCIE_MEM_WIN1_LO :: reserved0 [19:02] */
-#define BCHP_PCIE_0_MISC_CPU_2_PCIE_MEM_WIN1_LO_reserved0_MASK 0x000ffffc
-#define BCHP_PCIE_0_MISC_CPU_2_PCIE_MEM_WIN1_LO_reserved0_SHIFT 2
-
-/* PCIE_0_MISC :: CPU_2_PCIE_MEM_WIN1_LO :: ENDIAN_MODE [01:00] */
-#define BCHP_PCIE_0_MISC_CPU_2_PCIE_MEM_WIN1_LO_ENDIAN_MODE_MASK 0x00000003
-#define BCHP_PCIE_0_MISC_CPU_2_PCIE_MEM_WIN1_LO_ENDIAN_MODE_SHIFT 0
-#define BCHP_PCIE_0_MISC_CPU_2_PCIE_MEM_WIN1_LO_ENDIAN_MODE_DEFAULT 0x00000000
-
-/***************************************************************************
- *CPU_2_PCIE_MEM_WIN1_HI - CPU to PCIe Memory Window 1 High
- ***************************************************************************/
-/* PCIE_0_MISC :: CPU_2_PCIE_MEM_WIN1_HI :: BASE_ADDR [31:00] */
-#define BCHP_PCIE_0_MISC_CPU_2_PCIE_MEM_WIN1_HI_BASE_ADDR_MASK 0xffffffff
-#define BCHP_PCIE_0_MISC_CPU_2_PCIE_MEM_WIN1_HI_BASE_ADDR_SHIFT 0
-#define BCHP_PCIE_0_MISC_CPU_2_PCIE_MEM_WIN1_HI_BASE_ADDR_DEFAULT 0x00000000
-
-/***************************************************************************
- *CPU_2_PCIE_MEM_WIN2_LO - CPU to PCIe Memory Window 2 Low
- ***************************************************************************/
-/* PCIE_0_MISC :: CPU_2_PCIE_MEM_WIN2_LO :: BASE_ADDR [31:20] */
-#define BCHP_PCIE_0_MISC_CPU_2_PCIE_MEM_WIN2_LO_BASE_ADDR_MASK 0xfff00000
-#define BCHP_PCIE_0_MISC_CPU_2_PCIE_MEM_WIN2_LO_BASE_ADDR_SHIFT 20
-#define BCHP_PCIE_0_MISC_CPU_2_PCIE_MEM_WIN2_LO_BASE_ADDR_DEFAULT 0x00000000
-
-/* PCIE_0_MISC :: CPU_2_PCIE_MEM_WIN2_LO :: reserved0 [19:02] */
-#define BCHP_PCIE_0_MISC_CPU_2_PCIE_MEM_WIN2_LO_reserved0_MASK 0x000ffffc
-#define BCHP_PCIE_0_MISC_CPU_2_PCIE_MEM_WIN2_LO_reserved0_SHIFT 2
-
-/* PCIE_0_MISC :: CPU_2_PCIE_MEM_WIN2_LO :: ENDIAN_MODE [01:00] */
-#define BCHP_PCIE_0_MISC_CPU_2_PCIE_MEM_WIN2_LO_ENDIAN_MODE_MASK 0x00000003
-#define BCHP_PCIE_0_MISC_CPU_2_PCIE_MEM_WIN2_LO_ENDIAN_MODE_SHIFT 0
-#define BCHP_PCIE_0_MISC_CPU_2_PCIE_MEM_WIN2_LO_ENDIAN_MODE_DEFAULT 0x00000000
-
-/***************************************************************************
- *CPU_2_PCIE_MEM_WIN2_HI - CPU to PCIe Memory Window 2 High
- ***************************************************************************/
-/* PCIE_0_MISC :: CPU_2_PCIE_MEM_WIN2_HI :: BASE_ADDR [31:00] */
-#define BCHP_PCIE_0_MISC_CPU_2_PCIE_MEM_WIN2_HI_BASE_ADDR_MASK 0xffffffff
-#define BCHP_PCIE_0_MISC_CPU_2_PCIE_MEM_WIN2_HI_BASE_ADDR_SHIFT 0
-#define BCHP_PCIE_0_MISC_CPU_2_PCIE_MEM_WIN2_HI_BASE_ADDR_DEFAULT 0x00000000
-
-/***************************************************************************
- *CPU_2_PCIE_MEM_WIN3_LO - CPU to PCIe Memory Window 3 Low
- ***************************************************************************/
-/* PCIE_0_MISC :: CPU_2_PCIE_MEM_WIN3_LO :: BASE_ADDR [31:20] */
-#define BCHP_PCIE_0_MISC_CPU_2_PCIE_MEM_WIN3_LO_BASE_ADDR_MASK 0xfff00000
-#define BCHP_PCIE_0_MISC_CPU_2_PCIE_MEM_WIN3_LO_BASE_ADDR_SHIFT 20
-#define BCHP_PCIE_0_MISC_CPU_2_PCIE_MEM_WIN3_LO_BASE_ADDR_DEFAULT 0x00000000
-
-/* PCIE_0_MISC :: CPU_2_PCIE_MEM_WIN3_LO :: reserved0 [19:02] */
-#define BCHP_PCIE_0_MISC_CPU_2_PCIE_MEM_WIN3_LO_reserved0_MASK 0x000ffffc
-#define BCHP_PCIE_0_MISC_CPU_2_PCIE_MEM_WIN3_LO_reserved0_SHIFT 2
-
-/* PCIE_0_MISC :: CPU_2_PCIE_MEM_WIN3_LO :: ENDIAN_MODE [01:00] */
-#define BCHP_PCIE_0_MISC_CPU_2_PCIE_MEM_WIN3_LO_ENDIAN_MODE_MASK 0x00000003
-#define BCHP_PCIE_0_MISC_CPU_2_PCIE_MEM_WIN3_LO_ENDIAN_MODE_SHIFT 0
-#define BCHP_PCIE_0_MISC_CPU_2_PCIE_MEM_WIN3_LO_ENDIAN_MODE_DEFAULT 0x00000000
-
-/***************************************************************************
- *CPU_2_PCIE_MEM_WIN3_HI - CPU to PCIe Memory Window 3 High
- ***************************************************************************/
-/* PCIE_0_MISC :: CPU_2_PCIE_MEM_WIN3_HI :: BASE_ADDR [31:00] */
-#define BCHP_PCIE_0_MISC_CPU_2_PCIE_MEM_WIN3_HI_BASE_ADDR_MASK 0xffffffff
-#define BCHP_PCIE_0_MISC_CPU_2_PCIE_MEM_WIN3_HI_BASE_ADDR_SHIFT 0
-#define BCHP_PCIE_0_MISC_CPU_2_PCIE_MEM_WIN3_HI_BASE_ADDR_DEFAULT 0x00000000
-
-/***************************************************************************
- *RC_BAR1_CONFIG_LO - RC BAR1 Configuration Low Register
- ***************************************************************************/
-/* PCIE_0_MISC :: RC_BAR1_CONFIG_LO :: MATCH_ADDRESS [31:12] */
-#define BCHP_PCIE_0_MISC_RC_BAR1_CONFIG_LO_MATCH_ADDRESS_MASK 0xfffff000
-#define BCHP_PCIE_0_MISC_RC_BAR1_CONFIG_LO_MATCH_ADDRESS_SHIFT 12
-#define BCHP_PCIE_0_MISC_RC_BAR1_CONFIG_LO_MATCH_ADDRESS_DEFAULT 0x00000000
-
-/* PCIE_0_MISC :: RC_BAR1_CONFIG_LO :: reserved0 [11:05] */
-#define BCHP_PCIE_0_MISC_RC_BAR1_CONFIG_LO_reserved0_MASK 0x00000fe0
-#define BCHP_PCIE_0_MISC_RC_BAR1_CONFIG_LO_reserved0_SHIFT 5
-
-/* PCIE_0_MISC :: RC_BAR1_CONFIG_LO :: SIZE [04:00] */
-#define BCHP_PCIE_0_MISC_RC_BAR1_CONFIG_LO_SIZE_MASK 0x0000001f
-#define BCHP_PCIE_0_MISC_RC_BAR1_CONFIG_LO_SIZE_SHIFT 0
-#define BCHP_PCIE_0_MISC_RC_BAR1_CONFIG_LO_SIZE_DEFAULT 0x00000000
-
-/***************************************************************************
- *RC_BAR1_CONFIG_HI - RC BAR1 Configuration High Register
- ***************************************************************************/
-/* PCIE_0_MISC :: RC_BAR1_CONFIG_HI :: MATCH_ADDRESS [31:00] */
-#define BCHP_PCIE_0_MISC_RC_BAR1_CONFIG_HI_MATCH_ADDRESS_MASK 0xffffffff
-#define BCHP_PCIE_0_MISC_RC_BAR1_CONFIG_HI_MATCH_ADDRESS_SHIFT 0
-#define BCHP_PCIE_0_MISC_RC_BAR1_CONFIG_HI_MATCH_ADDRESS_DEFAULT 0x00000000
-
-/***************************************************************************
- *RC_BAR2_CONFIG_LO - RC BAR2 Configuration Low Register
- ***************************************************************************/
-/* PCIE_0_MISC :: RC_BAR2_CONFIG_LO :: MATCH_ADDRESS [31:12] */
-#define BCHP_PCIE_0_MISC_RC_BAR2_CONFIG_LO_MATCH_ADDRESS_MASK 0xfffff000
-#define BCHP_PCIE_0_MISC_RC_BAR2_CONFIG_LO_MATCH_ADDRESS_SHIFT 12
-#define BCHP_PCIE_0_MISC_RC_BAR2_CONFIG_LO_MATCH_ADDRESS_DEFAULT 0x00000000
-
-/* PCIE_0_MISC :: RC_BAR2_CONFIG_LO :: reserved0 [11:05] */
-#define BCHP_PCIE_0_MISC_RC_BAR2_CONFIG_LO_reserved0_MASK 0x00000fe0
-#define BCHP_PCIE_0_MISC_RC_BAR2_CONFIG_LO_reserved0_SHIFT 5
-
-/* PCIE_0_MISC :: RC_BAR2_CONFIG_LO :: SIZE [04:00] */
-#define BCHP_PCIE_0_MISC_RC_BAR2_CONFIG_LO_SIZE_MASK 0x0000001f
-#define BCHP_PCIE_0_MISC_RC_BAR2_CONFIG_LO_SIZE_SHIFT 0
-#define BCHP_PCIE_0_MISC_RC_BAR2_CONFIG_LO_SIZE_DEFAULT 0x00000000
-
-/***************************************************************************
- *RC_BAR2_CONFIG_HI - RC BAR2 Configuration High Register
- ***************************************************************************/
-/* PCIE_0_MISC :: RC_BAR2_CONFIG_HI :: MATCH_ADDRESS [31:00] */
-#define BCHP_PCIE_0_MISC_RC_BAR2_CONFIG_HI_MATCH_ADDRESS_MASK 0xffffffff
-#define BCHP_PCIE_0_MISC_RC_BAR2_CONFIG_HI_MATCH_ADDRESS_SHIFT 0
-#define BCHP_PCIE_0_MISC_RC_BAR2_CONFIG_HI_MATCH_ADDRESS_DEFAULT 0x00000000
-
-/***************************************************************************
- *RC_BAR3_CONFIG_LO - RC BAR3 Configuration Low Register
- ***************************************************************************/
-/* PCIE_0_MISC :: RC_BAR3_CONFIG_LO :: MATCH_ADDRESS [31:12] */
-#define BCHP_PCIE_0_MISC_RC_BAR3_CONFIG_LO_MATCH_ADDRESS_MASK 0xfffff000
-#define BCHP_PCIE_0_MISC_RC_BAR3_CONFIG_LO_MATCH_ADDRESS_SHIFT 12
-#define BCHP_PCIE_0_MISC_RC_BAR3_CONFIG_LO_MATCH_ADDRESS_DEFAULT 0x00000000
-
-/* PCIE_0_MISC :: RC_BAR3_CONFIG_LO :: reserved0 [11:05] */
-#define BCHP_PCIE_0_MISC_RC_BAR3_CONFIG_LO_reserved0_MASK 0x00000fe0
-#define BCHP_PCIE_0_MISC_RC_BAR3_CONFIG_LO_reserved0_SHIFT 5
-
-/* PCIE_0_MISC :: RC_BAR3_CONFIG_LO :: SIZE [04:00] */
-#define BCHP_PCIE_0_MISC_RC_BAR3_CONFIG_LO_SIZE_MASK 0x0000001f
-#define BCHP_PCIE_0_MISC_RC_BAR3_CONFIG_LO_SIZE_SHIFT 0
-#define BCHP_PCIE_0_MISC_RC_BAR3_CONFIG_LO_SIZE_DEFAULT 0x00000000
-
-/***************************************************************************
- *RC_BAR3_CONFIG_HI - RC BAR3 Configuration High Register
- ***************************************************************************/
-/* PCIE_0_MISC :: RC_BAR3_CONFIG_HI :: MATCH_ADDRESS [31:00] */
-#define BCHP_PCIE_0_MISC_RC_BAR3_CONFIG_HI_MATCH_ADDRESS_MASK 0xffffffff
-#define BCHP_PCIE_0_MISC_RC_BAR3_CONFIG_HI_MATCH_ADDRESS_SHIFT 0
-#define BCHP_PCIE_0_MISC_RC_BAR3_CONFIG_HI_MATCH_ADDRESS_DEFAULT 0x00000000
-
-/***************************************************************************
- *MSI_BAR_CONFIG_LO - Message Signaled Interrupt Base Address Low Register
- ***************************************************************************/
-/* PCIE_0_MISC :: MSI_BAR_CONFIG_LO :: MATCH_ADDRESS [31:02] */
-#define BCHP_PCIE_0_MISC_MSI_BAR_CONFIG_LO_MATCH_ADDRESS_MASK 0xfffffffc
-#define BCHP_PCIE_0_MISC_MSI_BAR_CONFIG_LO_MATCH_ADDRESS_SHIFT 2
-#define BCHP_PCIE_0_MISC_MSI_BAR_CONFIG_LO_MATCH_ADDRESS_DEFAULT 0x00000000
-
-/* PCIE_0_MISC :: MSI_BAR_CONFIG_LO :: reserved0 [01:01] */
-#define BCHP_PCIE_0_MISC_MSI_BAR_CONFIG_LO_reserved0_MASK 0x00000002
-#define BCHP_PCIE_0_MISC_MSI_BAR_CONFIG_LO_reserved0_SHIFT 1
-
-/* PCIE_0_MISC :: MSI_BAR_CONFIG_LO :: ENABLE [00:00] */
-#define BCHP_PCIE_0_MISC_MSI_BAR_CONFIG_LO_ENABLE_MASK 0x00000001
-#define BCHP_PCIE_0_MISC_MSI_BAR_CONFIG_LO_ENABLE_SHIFT 0
-#define BCHP_PCIE_0_MISC_MSI_BAR_CONFIG_LO_ENABLE_DEFAULT 0x00000000
-
-/***************************************************************************
- *MSI_BAR_CONFIG_HI - Message Signaled Interrupt Base Address High Register
- ***************************************************************************/
-/* PCIE_0_MISC :: MSI_BAR_CONFIG_HI :: MATCH_ADDRESS [31:00] */
-#define BCHP_PCIE_0_MISC_MSI_BAR_CONFIG_HI_MATCH_ADDRESS_MASK 0xffffffff
-#define BCHP_PCIE_0_MISC_MSI_BAR_CONFIG_HI_MATCH_ADDRESS_SHIFT 0
-#define BCHP_PCIE_0_MISC_MSI_BAR_CONFIG_HI_MATCH_ADDRESS_DEFAULT 0x00000000
-
-/***************************************************************************
- *MSI_DATA_CONFIG - Message Signaled Interrupt Data Configuration Register
- ***************************************************************************/
-/* PCIE_0_MISC :: MSI_DATA_CONFIG :: MASK [31:16] */
-#define BCHP_PCIE_0_MISC_MSI_DATA_CONFIG_MASK_MASK 0xffff0000
-#define BCHP_PCIE_0_MISC_MSI_DATA_CONFIG_MASK_SHIFT 16
-#define BCHP_PCIE_0_MISC_MSI_DATA_CONFIG_MASK_DEFAULT 0x00000000
-
-/* PCIE_0_MISC :: MSI_DATA_CONFIG :: DATA [15:00] */
-#define BCHP_PCIE_0_MISC_MSI_DATA_CONFIG_DATA_MASK 0x0000ffff
-#define BCHP_PCIE_0_MISC_MSI_DATA_CONFIG_DATA_SHIFT 0
-#define BCHP_PCIE_0_MISC_MSI_DATA_CONFIG_DATA_DEFAULT 0x00000000
-
-/***************************************************************************
- *RC_BAD_ADDRESS_LO - RC Bad Address Register Low
- ***************************************************************************/
-/* PCIE_0_MISC :: RC_BAD_ADDRESS_LO :: ADDRESS [31:02] */
-#define BCHP_PCIE_0_MISC_RC_BAD_ADDRESS_LO_ADDRESS_MASK 0xfffffffc
-#define BCHP_PCIE_0_MISC_RC_BAD_ADDRESS_LO_ADDRESS_SHIFT 2
-#define BCHP_PCIE_0_MISC_RC_BAD_ADDRESS_LO_ADDRESS_DEFAULT 0x00000000
-
-/* PCIE_0_MISC :: RC_BAD_ADDRESS_LO :: reserved0 [01:01] */
-#define BCHP_PCIE_0_MISC_RC_BAD_ADDRESS_LO_reserved0_MASK 0x00000002
-#define BCHP_PCIE_0_MISC_RC_BAD_ADDRESS_LO_reserved0_SHIFT 1
-
-/* PCIE_0_MISC :: RC_BAD_ADDRESS_LO :: VALID [00:00] */
-#define BCHP_PCIE_0_MISC_RC_BAD_ADDRESS_LO_VALID_MASK 0x00000001
-#define BCHP_PCIE_0_MISC_RC_BAD_ADDRESS_LO_VALID_SHIFT 0
-#define BCHP_PCIE_0_MISC_RC_BAD_ADDRESS_LO_VALID_DEFAULT 0x00000000
-
-/***************************************************************************
- *RC_BAD_ADDRESS_HI - RC Bad Address Register High
- ***************************************************************************/
-/* PCIE_0_MISC :: RC_BAD_ADDRESS_HI :: ADDRESS [31:00] */
-#define BCHP_PCIE_0_MISC_RC_BAD_ADDRESS_HI_ADDRESS_MASK 0xffffffff
-#define BCHP_PCIE_0_MISC_RC_BAD_ADDRESS_HI_ADDRESS_SHIFT 0
-#define BCHP_PCIE_0_MISC_RC_BAD_ADDRESS_HI_ADDRESS_DEFAULT 0x00000000
-
-/***************************************************************************
- *RC_BAD_DATA - RC Bad Data Register
- ***************************************************************************/
-/* PCIE_0_MISC :: RC_BAD_DATA :: DATA [31:00] */
-#define BCHP_PCIE_0_MISC_RC_BAD_DATA_DATA_MASK 0xffffffff
-#define BCHP_PCIE_0_MISC_RC_BAD_DATA_DATA_SHIFT 0
-#define BCHP_PCIE_0_MISC_RC_BAD_DATA_DATA_DEFAULT 0x00000000
-
-/***************************************************************************
- *RC_CONFIG_RETRY_TIMEOUT - RC Configuration Retry Timeout Register
- ***************************************************************************/
-/* PCIE_0_MISC :: RC_CONFIG_RETRY_TIMEOUT :: TIMER_VALUE [31:00] */
-#define BCHP_PCIE_0_MISC_RC_CONFIG_RETRY_TIMEOUT_TIMER_VALUE_MASK 0xffffffff
-#define BCHP_PCIE_0_MISC_RC_CONFIG_RETRY_TIMEOUT_TIMER_VALUE_SHIFT 0
-#define BCHP_PCIE_0_MISC_RC_CONFIG_RETRY_TIMEOUT_TIMER_VALUE_DEFAULT 0x00000000
-
-/***************************************************************************
- *EOI_CTRL - End of Interrupt Control Register
- ***************************************************************************/
-/* PCIE_0_MISC :: EOI_CTRL :: reserved0 [31:01] */
-#define BCHP_PCIE_0_MISC_EOI_CTRL_reserved0_MASK 0xfffffffe
-#define BCHP_PCIE_0_MISC_EOI_CTRL_reserved0_SHIFT 1
-
-/* PCIE_0_MISC :: EOI_CTRL :: EOI [00:00] */
-#define BCHP_PCIE_0_MISC_EOI_CTRL_EOI_MASK 0x00000001
-#define BCHP_PCIE_0_MISC_EOI_CTRL_EOI_SHIFT 0
-#define BCHP_PCIE_0_MISC_EOI_CTRL_EOI_DEFAULT 0x00000000
-
-/***************************************************************************
- *PCIE_CTRL - PCIe Control
- ***************************************************************************/
-/* PCIE_0_MISC :: PCIE_CTRL :: reserved0 [31:02] */
-#define BCHP_PCIE_0_MISC_PCIE_CTRL_reserved0_MASK 0xfffffffc
-#define BCHP_PCIE_0_MISC_PCIE_CTRL_reserved0_SHIFT 2
-
-/* PCIE_0_MISC :: PCIE_CTRL :: PCIE_PME_REQUEST [01:01] */
-#define BCHP_PCIE_0_MISC_PCIE_CTRL_PCIE_PME_REQUEST_MASK 0x00000002
-#define BCHP_PCIE_0_MISC_PCIE_CTRL_PCIE_PME_REQUEST_SHIFT 1
-#define BCHP_PCIE_0_MISC_PCIE_CTRL_PCIE_PME_REQUEST_DEFAULT 0x00000000
-
-/* PCIE_0_MISC :: PCIE_CTRL :: PCIE_L23_REQUEST [00:00] */
-#define BCHP_PCIE_0_MISC_PCIE_CTRL_PCIE_L23_REQUEST_MASK 0x00000001
-#define BCHP_PCIE_0_MISC_PCIE_CTRL_PCIE_L23_REQUEST_SHIFT 0
-#define BCHP_PCIE_0_MISC_PCIE_CTRL_PCIE_L23_REQUEST_DEFAULT 0x00000000
-
-/***************************************************************************
- *PCIE_STATUS - PCIe Status
- ***************************************************************************/
-/* PCIE_0_MISC :: PCIE_STATUS :: reserved0 [31:13] */
-#define BCHP_PCIE_0_MISC_PCIE_STATUS_reserved0_MASK 0xffffe000
-#define BCHP_PCIE_0_MISC_PCIE_STATUS_reserved0_SHIFT 13
-
-/* PCIE_0_MISC :: PCIE_STATUS :: PCIE_SSC_STATUS [12:12] */
-#define BCHP_PCIE_0_MISC_PCIE_STATUS_PCIE_SSC_STATUS_MASK 0x00001000
-#define BCHP_PCIE_0_MISC_PCIE_STATUS_PCIE_SSC_STATUS_SHIFT 12
-#define BCHP_PCIE_0_MISC_PCIE_STATUS_PCIE_SSC_STATUS_DEFAULT 0x00000000
-
-/* PCIE_0_MISC :: PCIE_STATUS :: PCIE_PM_STATE [11:10] */
-#define BCHP_PCIE_0_MISC_PCIE_STATUS_PCIE_PM_STATE_MASK 0x00000c00
-#define BCHP_PCIE_0_MISC_PCIE_STATUS_PCIE_PM_STATE_SHIFT 10
-#define BCHP_PCIE_0_MISC_PCIE_STATUS_PCIE_PM_STATE_DEFAULT 0x00000000
-
-/* PCIE_0_MISC :: PCIE_STATUS :: PCIE_WAKE [09:09] */
-#define BCHP_PCIE_0_MISC_PCIE_STATUS_PCIE_WAKE_MASK 0x00000200
-#define BCHP_PCIE_0_MISC_PCIE_STATUS_PCIE_WAKE_SHIFT 9
-#define BCHP_PCIE_0_MISC_PCIE_STATUS_PCIE_WAKE_DEFAULT 0x00000000
-
-/* PCIE_0_MISC :: PCIE_STATUS :: PCIE_PME_EVENT [08:08] */
-#define BCHP_PCIE_0_MISC_PCIE_STATUS_PCIE_PME_EVENT_MASK 0x00000100
-#define BCHP_PCIE_0_MISC_PCIE_STATUS_PCIE_PME_EVENT_SHIFT 8
-#define BCHP_PCIE_0_MISC_PCIE_STATUS_PCIE_PME_EVENT_DEFAULT 0x00000000
-
-/* PCIE_0_MISC :: PCIE_STATUS :: PCIE_PORT [07:07] */
-#define BCHP_PCIE_0_MISC_PCIE_STATUS_PCIE_PORT_MASK 0x00000080
-#define BCHP_PCIE_0_MISC_PCIE_STATUS_PCIE_PORT_SHIFT 7
-
-/* PCIE_0_MISC :: PCIE_STATUS :: PCIE_LINK_IN_L23 [06:06] */
-#define BCHP_PCIE_0_MISC_PCIE_STATUS_PCIE_LINK_IN_L23_MASK 0x00000040
-#define BCHP_PCIE_0_MISC_PCIE_STATUS_PCIE_LINK_IN_L23_SHIFT 6
-#define BCHP_PCIE_0_MISC_PCIE_STATUS_PCIE_LINK_IN_L23_DEFAULT 0x00000000
-
-/* PCIE_0_MISC :: PCIE_STATUS :: PCIE_DL_ACTIVE [05:05] */
-#define BCHP_PCIE_0_MISC_PCIE_STATUS_PCIE_DL_ACTIVE_MASK 0x00000020
-#define BCHP_PCIE_0_MISC_PCIE_STATUS_PCIE_DL_ACTIVE_SHIFT 5
-#define BCHP_PCIE_0_MISC_PCIE_STATUS_PCIE_DL_ACTIVE_DEFAULT 0x00000000
-
-/* PCIE_0_MISC :: PCIE_STATUS :: PCIE_PHYLINKUP [04:04] */
-#define BCHP_PCIE_0_MISC_PCIE_STATUS_PCIE_PHYLINKUP_MASK 0x00000010
-#define BCHP_PCIE_0_MISC_PCIE_STATUS_PCIE_PHYLINKUP_SHIFT 4
-#define BCHP_PCIE_0_MISC_PCIE_STATUS_PCIE_PHYLINKUP_DEFAULT 0x00000000
-
-/* PCIE_0_MISC :: PCIE_STATUS :: PCIE_ERR_STATUS [03:00] */
-#define BCHP_PCIE_0_MISC_PCIE_STATUS_PCIE_ERR_STATUS_MASK 0x0000000f
-#define BCHP_PCIE_0_MISC_PCIE_STATUS_PCIE_ERR_STATUS_SHIFT 0
-#define BCHP_PCIE_0_MISC_PCIE_STATUS_PCIE_ERR_STATUS_DEFAULT 0x00000000
-
-/***************************************************************************
- *REVISION - PCIe Revision
- ***************************************************************************/
-/* PCIE_0_MISC :: REVISION :: reserved0 [31:16] */
-#define BCHP_PCIE_0_MISC_REVISION_reserved0_MASK 0xffff0000
-#define BCHP_PCIE_0_MISC_REVISION_reserved0_SHIFT 16
-
-/* PCIE_0_MISC :: REVISION :: MAJOR [15:08] */
-#define BCHP_PCIE_0_MISC_REVISION_MAJOR_MASK 0x0000ff00
-#define BCHP_PCIE_0_MISC_REVISION_MAJOR_SHIFT 8
-#define BCHP_PCIE_0_MISC_REVISION_MAJOR_DEFAULT 0x00000003
-
-/* PCIE_0_MISC :: REVISION :: MINOR [07:00] */
-#define BCHP_PCIE_0_MISC_REVISION_MINOR_MASK 0x000000ff
-#define BCHP_PCIE_0_MISC_REVISION_MINOR_SHIFT 0
-#define BCHP_PCIE_0_MISC_REVISION_MINOR_DEFAULT 0x00000001
-
-/***************************************************************************
- *CPU_2_PCIE_MEM_WIN0_BASE_LIMIT - CPU to PCIe Memory Window 0 base/limit
- ***************************************************************************/
-/* PCIE_0_MISC :: CPU_2_PCIE_MEM_WIN0_BASE_LIMIT :: LIMIT [31:20] */
-#define BCHP_PCIE_0_MISC_CPU_2_PCIE_MEM_WIN0_BASE_LIMIT_LIMIT_MASK 0xfff00000
-#define BCHP_PCIE_0_MISC_CPU_2_PCIE_MEM_WIN0_BASE_LIMIT_LIMIT_SHIFT 20
-#define BCHP_PCIE_0_MISC_CPU_2_PCIE_MEM_WIN0_BASE_LIMIT_LIMIT_DEFAULT 0x00000000
-
-/* PCIE_0_MISC :: CPU_2_PCIE_MEM_WIN0_BASE_LIMIT :: reserved0 [19:16] */
-#define BCHP_PCIE_0_MISC_CPU_2_PCIE_MEM_WIN0_BASE_LIMIT_reserved0_MASK 0x000f0000
-#define BCHP_PCIE_0_MISC_CPU_2_PCIE_MEM_WIN0_BASE_LIMIT_reserved0_SHIFT 16
-
-/* PCIE_0_MISC :: CPU_2_PCIE_MEM_WIN0_BASE_LIMIT :: BASE [15:04] */
-#define BCHP_PCIE_0_MISC_CPU_2_PCIE_MEM_WIN0_BASE_LIMIT_BASE_MASK 0x0000fff0
-#define BCHP_PCIE_0_MISC_CPU_2_PCIE_MEM_WIN0_BASE_LIMIT_BASE_SHIFT 4
-#define BCHP_PCIE_0_MISC_CPU_2_PCIE_MEM_WIN0_BASE_LIMIT_BASE_DEFAULT 0x00000001
-
-/* PCIE_0_MISC :: CPU_2_PCIE_MEM_WIN0_BASE_LIMIT :: reserved1 [03:00] */
-#define BCHP_PCIE_0_MISC_CPU_2_PCIE_MEM_WIN0_BASE_LIMIT_reserved1_MASK 0x0000000f
-#define BCHP_PCIE_0_MISC_CPU_2_PCIE_MEM_WIN0_BASE_LIMIT_reserved1_SHIFT 0
-
-/***************************************************************************
- *CPU_2_PCIE_MEM_WIN1_BASE_LIMIT - CPU to PCIe Memory Window 1 base/limit
- ***************************************************************************/
-/* PCIE_0_MISC :: CPU_2_PCIE_MEM_WIN1_BASE_LIMIT :: LIMIT [31:20] */
-#define BCHP_PCIE_0_MISC_CPU_2_PCIE_MEM_WIN1_BASE_LIMIT_LIMIT_MASK 0xfff00000
-#define BCHP_PCIE_0_MISC_CPU_2_PCIE_MEM_WIN1_BASE_LIMIT_LIMIT_SHIFT 20
-#define BCHP_PCIE_0_MISC_CPU_2_PCIE_MEM_WIN1_BASE_LIMIT_LIMIT_DEFAULT 0x00000000
-
-/* PCIE_0_MISC :: CPU_2_PCIE_MEM_WIN1_BASE_LIMIT :: reserved0 [19:16] */
-#define BCHP_PCIE_0_MISC_CPU_2_PCIE_MEM_WIN1_BASE_LIMIT_reserved0_MASK 0x000f0000
-#define BCHP_PCIE_0_MISC_CPU_2_PCIE_MEM_WIN1_BASE_LIMIT_reserved0_SHIFT 16
-
-/* PCIE_0_MISC :: CPU_2_PCIE_MEM_WIN1_BASE_LIMIT :: BASE [15:04] */
-#define BCHP_PCIE_0_MISC_CPU_2_PCIE_MEM_WIN1_BASE_LIMIT_BASE_MASK 0x0000fff0
-#define BCHP_PCIE_0_MISC_CPU_2_PCIE_MEM_WIN1_BASE_LIMIT_BASE_SHIFT 4
-#define BCHP_PCIE_0_MISC_CPU_2_PCIE_MEM_WIN1_BASE_LIMIT_BASE_DEFAULT 0x00000001
-
-/* PCIE_0_MISC :: CPU_2_PCIE_MEM_WIN1_BASE_LIMIT :: reserved1 [03:00] */
-#define BCHP_PCIE_0_MISC_CPU_2_PCIE_MEM_WIN1_BASE_LIMIT_reserved1_MASK 0x0000000f
-#define BCHP_PCIE_0_MISC_CPU_2_PCIE_MEM_WIN1_BASE_LIMIT_reserved1_SHIFT 0
-
-/***************************************************************************
- *CPU_2_PCIE_MEM_WIN2_BASE_LIMIT - CPU to PCIe Memory Window 2 base/limit
- ***************************************************************************/
-/* PCIE_0_MISC :: CPU_2_PCIE_MEM_WIN2_BASE_LIMIT :: LIMIT [31:20] */
-#define BCHP_PCIE_0_MISC_CPU_2_PCIE_MEM_WIN2_BASE_LIMIT_LIMIT_MASK 0xfff00000
-#define BCHP_PCIE_0_MISC_CPU_2_PCIE_MEM_WIN2_BASE_LIMIT_LIMIT_SHIFT 20
-#define BCHP_PCIE_0_MISC_CPU_2_PCIE_MEM_WIN2_BASE_LIMIT_LIMIT_DEFAULT 0x00000000
-
-/* PCIE_0_MISC :: CPU_2_PCIE_MEM_WIN2_BASE_LIMIT :: reserved0 [19:16] */
-#define BCHP_PCIE_0_MISC_CPU_2_PCIE_MEM_WIN2_BASE_LIMIT_reserved0_MASK 0x000f0000
-#define BCHP_PCIE_0_MISC_CPU_2_PCIE_MEM_WIN2_BASE_LIMIT_reserved0_SHIFT 16
-
-/* PCIE_0_MISC :: CPU_2_PCIE_MEM_WIN2_BASE_LIMIT :: BASE [15:04] */
-#define BCHP_PCIE_0_MISC_CPU_2_PCIE_MEM_WIN2_BASE_LIMIT_BASE_MASK 0x0000fff0
-#define BCHP_PCIE_0_MISC_CPU_2_PCIE_MEM_WIN2_BASE_LIMIT_BASE_SHIFT 4
-#define BCHP_PCIE_0_MISC_CPU_2_PCIE_MEM_WIN2_BASE_LIMIT_BASE_DEFAULT 0x00000001
-
-/* PCIE_0_MISC :: CPU_2_PCIE_MEM_WIN2_BASE_LIMIT :: reserved1 [03:00] */
-#define BCHP_PCIE_0_MISC_CPU_2_PCIE_MEM_WIN2_BASE_LIMIT_reserved1_MASK 0x0000000f
-#define BCHP_PCIE_0_MISC_CPU_2_PCIE_MEM_WIN2_BASE_LIMIT_reserved1_SHIFT 0
-
-/***************************************************************************
- *CPU_2_PCIE_MEM_WIN3_BASE_LIMIT - CPU to PCIe Memory Window 3 base/limit
- ***************************************************************************/
-/* PCIE_0_MISC :: CPU_2_PCIE_MEM_WIN3_BASE_LIMIT :: LIMIT [31:20] */
-#define BCHP_PCIE_0_MISC_CPU_2_PCIE_MEM_WIN3_BASE_LIMIT_LIMIT_MASK 0xfff00000
-#define BCHP_PCIE_0_MISC_CPU_2_PCIE_MEM_WIN3_BASE_LIMIT_LIMIT_SHIFT 20
-#define BCHP_PCIE_0_MISC_CPU_2_PCIE_MEM_WIN3_BASE_LIMIT_LIMIT_DEFAULT 0x00000000
-
-/* PCIE_0_MISC :: CPU_2_PCIE_MEM_WIN3_BASE_LIMIT :: reserved0 [19:16] */
-#define BCHP_PCIE_0_MISC_CPU_2_PCIE_MEM_WIN3_BASE_LIMIT_reserved0_MASK 0x000f0000
-#define BCHP_PCIE_0_MISC_CPU_2_PCIE_MEM_WIN3_BASE_LIMIT_reserved0_SHIFT 16
-
-/* PCIE_0_MISC :: CPU_2_PCIE_MEM_WIN3_BASE_LIMIT :: BASE [15:04] */
-#define BCHP_PCIE_0_MISC_CPU_2_PCIE_MEM_WIN3_BASE_LIMIT_BASE_MASK 0x0000fff0
-#define BCHP_PCIE_0_MISC_CPU_2_PCIE_MEM_WIN3_BASE_LIMIT_BASE_SHIFT 4
-#define BCHP_PCIE_0_MISC_CPU_2_PCIE_MEM_WIN3_BASE_LIMIT_BASE_DEFAULT 0x00000001
-
-/* PCIE_0_MISC :: CPU_2_PCIE_MEM_WIN3_BASE_LIMIT :: reserved1 [03:00] */
-#define BCHP_PCIE_0_MISC_CPU_2_PCIE_MEM_WIN3_BASE_LIMIT_reserved1_MASK 0x0000000f
-#define BCHP_PCIE_0_MISC_CPU_2_PCIE_MEM_WIN3_BASE_LIMIT_reserved1_SHIFT 0
-
-/***************************************************************************
- *CPU_2_PCIE_MEM_WIN0_BASE_HI - CPU to PCIe Memory Window 0 base high
- ***************************************************************************/
-/* PCIE_0_MISC :: CPU_2_PCIE_MEM_WIN0_BASE_HI :: reserved0 [31:08] */
-#define BCHP_PCIE_0_MISC_CPU_2_PCIE_MEM_WIN0_BASE_HI_reserved0_MASK 0xffffff00
-#define BCHP_PCIE_0_MISC_CPU_2_PCIE_MEM_WIN0_BASE_HI_reserved0_SHIFT 8
-
-/* PCIE_0_MISC :: CPU_2_PCIE_MEM_WIN0_BASE_HI :: BASE [07:00] */
-#define BCHP_PCIE_0_MISC_CPU_2_PCIE_MEM_WIN0_BASE_HI_BASE_MASK 0x000000ff
-#define BCHP_PCIE_0_MISC_CPU_2_PCIE_MEM_WIN0_BASE_HI_BASE_SHIFT 0
-#define BCHP_PCIE_0_MISC_CPU_2_PCIE_MEM_WIN0_BASE_HI_BASE_DEFAULT 0x00000000
-
-/***************************************************************************
- *CPU_2_PCIE_MEM_WIN0_LIMIT_HI - CPU to PCIe Memory Window 0 limit high
- ***************************************************************************/
-/* PCIE_0_MISC :: CPU_2_PCIE_MEM_WIN0_LIMIT_HI :: reserved0 [31:08] */
-#define BCHP_PCIE_0_MISC_CPU_2_PCIE_MEM_WIN0_LIMIT_HI_reserved0_MASK 0xffffff00
-#define BCHP_PCIE_0_MISC_CPU_2_PCIE_MEM_WIN0_LIMIT_HI_reserved0_SHIFT 8
-
-/* PCIE_0_MISC :: CPU_2_PCIE_MEM_WIN0_LIMIT_HI :: LIMIT [07:00] */
-#define BCHP_PCIE_0_MISC_CPU_2_PCIE_MEM_WIN0_LIMIT_HI_LIMIT_MASK 0x000000ff
-#define BCHP_PCIE_0_MISC_CPU_2_PCIE_MEM_WIN0_LIMIT_HI_LIMIT_SHIFT 0
-#define BCHP_PCIE_0_MISC_CPU_2_PCIE_MEM_WIN0_LIMIT_HI_LIMIT_DEFAULT 0x00000000
-
-/***************************************************************************
- *CPU_2_PCIE_MEM_WIN1_BASE_HI - CPU to PCIe Memory Window 1 base high
- ***************************************************************************/
-/* PCIE_0_MISC :: CPU_2_PCIE_MEM_WIN1_BASE_HI :: reserved0 [31:08] */
-#define BCHP_PCIE_0_MISC_CPU_2_PCIE_MEM_WIN1_BASE_HI_reserved0_MASK 0xffffff00
-#define BCHP_PCIE_0_MISC_CPU_2_PCIE_MEM_WIN1_BASE_HI_reserved0_SHIFT 8
-
-/* PCIE_0_MISC :: CPU_2_PCIE_MEM_WIN1_BASE_HI :: BASE [07:00] */
-#define BCHP_PCIE_0_MISC_CPU_2_PCIE_MEM_WIN1_BASE_HI_BASE_MASK 0x000000ff
-#define BCHP_PCIE_0_MISC_CPU_2_PCIE_MEM_WIN1_BASE_HI_BASE_SHIFT 0
-#define BCHP_PCIE_0_MISC_CPU_2_PCIE_MEM_WIN1_BASE_HI_BASE_DEFAULT 0x00000000
-
-/***************************************************************************
- *CPU_2_PCIE_MEM_WIN1_LIMIT_HI - CPU to PCIe Memory Window 1 limit high
- ***************************************************************************/
-/* PCIE_0_MISC :: CPU_2_PCIE_MEM_WIN1_LIMIT_HI :: reserved0 [31:08] */
-#define BCHP_PCIE_0_MISC_CPU_2_PCIE_MEM_WIN1_LIMIT_HI_reserved0_MASK 0xffffff00
-#define BCHP_PCIE_0_MISC_CPU_2_PCIE_MEM_WIN1_LIMIT_HI_reserved0_SHIFT 8
-
-/* PCIE_0_MISC :: CPU_2_PCIE_MEM_WIN1_LIMIT_HI :: LIMIT [07:00] */
-#define BCHP_PCIE_0_MISC_CPU_2_PCIE_MEM_WIN1_LIMIT_HI_LIMIT_MASK 0x000000ff
-#define BCHP_PCIE_0_MISC_CPU_2_PCIE_MEM_WIN1_LIMIT_HI_LIMIT_SHIFT 0
-#define BCHP_PCIE_0_MISC_CPU_2_PCIE_MEM_WIN1_LIMIT_HI_LIMIT_DEFAULT 0x00000000
-
-/***************************************************************************
- *CPU_2_PCIE_MEM_WIN2_BASE_HI - CPU to PCIe Memory Window 2 base high
- ***************************************************************************/
-/* PCIE_0_MISC :: CPU_2_PCIE_MEM_WIN2_BASE_HI :: reserved0 [31:08] */
-#define BCHP_PCIE_0_MISC_CPU_2_PCIE_MEM_WIN2_BASE_HI_reserved0_MASK 0xffffff00
-#define BCHP_PCIE_0_MISC_CPU_2_PCIE_MEM_WIN2_BASE_HI_reserved0_SHIFT 8
-
-/* PCIE_0_MISC :: CPU_2_PCIE_MEM_WIN2_BASE_HI :: BASE [07:00] */
-#define BCHP_PCIE_0_MISC_CPU_2_PCIE_MEM_WIN2_BASE_HI_BASE_MASK 0x000000ff
-#define BCHP_PCIE_0_MISC_CPU_2_PCIE_MEM_WIN2_BASE_HI_BASE_SHIFT 0
-#define BCHP_PCIE_0_MISC_CPU_2_PCIE_MEM_WIN2_BASE_HI_BASE_DEFAULT 0x00000000
-
-/***************************************************************************
- *CPU_2_PCIE_MEM_WIN2_LIMIT_HI - CPU to PCIe Memory Window 2 limit high
- ***************************************************************************/
-/* PCIE_0_MISC :: CPU_2_PCIE_MEM_WIN2_LIMIT_HI :: reserved0 [31:08] */
-#define BCHP_PCIE_0_MISC_CPU_2_PCIE_MEM_WIN2_LIMIT_HI_reserved0_MASK 0xffffff00
-#define BCHP_PCIE_0_MISC_CPU_2_PCIE_MEM_WIN2_LIMIT_HI_reserved0_SHIFT 8
-
-/* PCIE_0_MISC :: CPU_2_PCIE_MEM_WIN2_LIMIT_HI :: LIMIT [07:00] */
-#define BCHP_PCIE_0_MISC_CPU_2_PCIE_MEM_WIN2_LIMIT_HI_LIMIT_MASK 0x000000ff
-#define BCHP_PCIE_0_MISC_CPU_2_PCIE_MEM_WIN2_LIMIT_HI_LIMIT_SHIFT 0
-#define BCHP_PCIE_0_MISC_CPU_2_PCIE_MEM_WIN2_LIMIT_HI_LIMIT_DEFAULT 0x00000000
-
-/***************************************************************************
- *CPU_2_PCIE_MEM_WIN3_BASE_HI - CPU to PCIe Memory Window 3 base high
- ***************************************************************************/
-/* PCIE_0_MISC :: CPU_2_PCIE_MEM_WIN3_BASE_HI :: reserved0 [31:08] */
-#define BCHP_PCIE_0_MISC_CPU_2_PCIE_MEM_WIN3_BASE_HI_reserved0_MASK 0xffffff00
-#define BCHP_PCIE_0_MISC_CPU_2_PCIE_MEM_WIN3_BASE_HI_reserved0_SHIFT 8
-
-/* PCIE_0_MISC :: CPU_2_PCIE_MEM_WIN3_BASE_HI :: BASE [07:00] */
-#define BCHP_PCIE_0_MISC_CPU_2_PCIE_MEM_WIN3_BASE_HI_BASE_MASK 0x000000ff
-#define BCHP_PCIE_0_MISC_CPU_2_PCIE_MEM_WIN3_BASE_HI_BASE_SHIFT 0
-#define BCHP_PCIE_0_MISC_CPU_2_PCIE_MEM_WIN3_BASE_HI_BASE_DEFAULT 0x00000000
-
-/***************************************************************************
- *CPU_2_PCIE_MEM_WIN3_LIMIT_HI - CPU to PCIe Memory Window 3 limit high
- ***************************************************************************/
-/* PCIE_0_MISC :: CPU_2_PCIE_MEM_WIN3_LIMIT_HI :: reserved0 [31:08] */
-#define BCHP_PCIE_0_MISC_CPU_2_PCIE_MEM_WIN3_LIMIT_HI_reserved0_MASK 0xffffff00
-#define BCHP_PCIE_0_MISC_CPU_2_PCIE_MEM_WIN3_LIMIT_HI_reserved0_SHIFT 8
-
-/* PCIE_0_MISC :: CPU_2_PCIE_MEM_WIN3_LIMIT_HI :: LIMIT [07:00] */
-#define BCHP_PCIE_0_MISC_CPU_2_PCIE_MEM_WIN3_LIMIT_HI_LIMIT_MASK 0x000000ff
-#define BCHP_PCIE_0_MISC_CPU_2_PCIE_MEM_WIN3_LIMIT_HI_LIMIT_SHIFT 0
-#define BCHP_PCIE_0_MISC_CPU_2_PCIE_MEM_WIN3_LIMIT_HI_LIMIT_DEFAULT 0x00000000
-
-/***************************************************************************
- *MISC_CTRL_1 - MISC Control Register 1
- ***************************************************************************/
-/* PCIE_0_MISC :: MISC_CTRL_1 :: reserved0 [31:16] */
-#define BCHP_PCIE_0_MISC_MISC_CTRL_1_reserved0_MASK 0xffff0000
-#define BCHP_PCIE_0_MISC_MISC_CTRL_1_reserved0_SHIFT 16
-
-/* PCIE_0_MISC :: MISC_CTRL_1 :: TBD_OPTION_15_5 [15:05] */
-#define BCHP_PCIE_0_MISC_MISC_CTRL_1_TBD_OPTION_15_5_MASK 0x0000ffe0
-#define BCHP_PCIE_0_MISC_MISC_CTRL_1_TBD_OPTION_15_5_SHIFT 5
-#define BCHP_PCIE_0_MISC_MISC_CTRL_1_TBD_OPTION_15_5_DEFAULT 0x00000000
-
-/* PCIE_0_MISC :: MISC_CTRL_1 :: RELAXED_ORDERING [04:04] */
-#define BCHP_PCIE_0_MISC_MISC_CTRL_1_RELAXED_ORDERING_MASK 0x00000010
-#define BCHP_PCIE_0_MISC_MISC_CTRL_1_RELAXED_ORDERING_SHIFT 4
-#define BCHP_PCIE_0_MISC_MISC_CTRL_1_RELAXED_ORDERING_DEFAULT 0x00000000
-
-/* PCIE_0_MISC :: MISC_CTRL_1 :: NO_SNOOP [03:03] */
-#define BCHP_PCIE_0_MISC_MISC_CTRL_1_NO_SNOOP_MASK 0x00000008
-#define BCHP_PCIE_0_MISC_MISC_CTRL_1_NO_SNOOP_SHIFT 3
-#define BCHP_PCIE_0_MISC_MISC_CTRL_1_NO_SNOOP_DEFAULT 0x00000000
-
-/* PCIE_0_MISC :: MISC_CTRL_1 :: TRAFFIC_CLASS [02:00] */
-#define BCHP_PCIE_0_MISC_MISC_CTRL_1_TRAFFIC_CLASS_MASK 0x00000007
-#define BCHP_PCIE_0_MISC_MISC_CTRL_1_TRAFFIC_CLASS_SHIFT 0
-#define BCHP_PCIE_0_MISC_MISC_CTRL_1_TRAFFIC_CLASS_DEFAULT 0x00000000
-
-/***************************************************************************
- *UBUS_CTRL - UBUS Control
- ***************************************************************************/
-/* PCIE_0_MISC :: UBUS_CTRL :: TBD_OPTION_31_19 [31:19] */
-#define BCHP_PCIE_0_MISC_UBUS_CTRL_TBD_OPTION_31_19_MASK 0xfff80000
-#define BCHP_PCIE_0_MISC_UBUS_CTRL_TBD_OPTION_31_19_SHIFT 19
-#define BCHP_PCIE_0_MISC_UBUS_CTRL_TBD_OPTION_31_19_DEFAULT 0x00000000
-
-/* PCIE_0_MISC :: UBUS_CTRL :: REQOUT_PRIORITY [18:18] */
-#define BCHP_PCIE_0_MISC_UBUS_CTRL_REQOUT_PRIORITY_MASK 0x00040000
-#define BCHP_PCIE_0_MISC_UBUS_CTRL_REQOUT_PRIORITY_SHIFT 18
-#define BCHP_PCIE_0_MISC_UBUS_CTRL_REQOUT_PRIORITY_DEFAULT 0x00000000
-
-/* PCIE_0_MISC :: UBUS_CTRL :: REPOUT_PRIORITY [17:17] */
-#define BCHP_PCIE_0_MISC_UBUS_CTRL_REPOUT_PRIORITY_MASK 0x00020000
-#define BCHP_PCIE_0_MISC_UBUS_CTRL_REPOUT_PRIORITY_SHIFT 17
-#define BCHP_PCIE_0_MISC_UBUS_CTRL_REPOUT_PRIORITY_DEFAULT 0x00000000
-
-/* PCIE_0_MISC :: UBUS_CTRL :: UBUS_DMA_WR_WITH_REPLY [16:15] */
-#define BCHP_PCIE_0_MISC_UBUS_CTRL_UBUS_DMA_WR_WITH_REPLY_MASK 0x00018000
-#define BCHP_PCIE_0_MISC_UBUS_CTRL_UBUS_DMA_WR_WITH_REPLY_SHIFT 15
-#define BCHP_PCIE_0_MISC_UBUS_CTRL_UBUS_DMA_WR_WITH_REPLY_DEFAULT 0x00000000
-
-/* PCIE_0_MISC :: UBUS_CTRL :: UBUS_WR_WITH_REPLY [14:14] */
-#define BCHP_PCIE_0_MISC_UBUS_CTRL_UBUS_WR_WITH_REPLY_MASK 0x00004000
-#define BCHP_PCIE_0_MISC_UBUS_CTRL_UBUS_WR_WITH_REPLY_SHIFT 14
-#define BCHP_PCIE_0_MISC_UBUS_CTRL_UBUS_WR_WITH_REPLY_DEFAULT 0x00000000
-
-/* PCIE_0_MISC :: UBUS_CTRL :: UBUS_PCIE_REPLY_ERR_DIS [13:13] */
-#define BCHP_PCIE_0_MISC_UBUS_CTRL_UBUS_PCIE_REPLY_ERR_DIS_MASK 0x00002000
-#define BCHP_PCIE_0_MISC_UBUS_CTRL_UBUS_PCIE_REPLY_ERR_DIS_SHIFT 13
-#define BCHP_PCIE_0_MISC_UBUS_CTRL_UBUS_PCIE_REPLY_ERR_DIS_DEFAULT 0x00000000
-
-/* PCIE_0_MISC :: UBUS_CTRL :: UBUS_REG_ACCESS_RO [12:12] */
-#define BCHP_PCIE_0_MISC_UBUS_CTRL_UBUS_REG_ACCESS_RO_MASK 0x00001000
-#define BCHP_PCIE_0_MISC_UBUS_CTRL_UBUS_REG_ACCESS_RO_SHIFT 12
-#define BCHP_PCIE_0_MISC_UBUS_CTRL_UBUS_REG_ACCESS_RO_DEFAULT 0x00000000
-
-/* PCIE_0_MISC :: UBUS_CTRL :: TBD_OPTION_11_0 [11:00] */
-#define BCHP_PCIE_0_MISC_UBUS_CTRL_TBD_OPTION_11_0_MASK 0x00000fff
-#define BCHP_PCIE_0_MISC_UBUS_CTRL_TBD_OPTION_11_0_SHIFT 0
-#define BCHP_PCIE_0_MISC_UBUS_CTRL_TBD_OPTION_11_0_DEFAULT 0x00000000
-
-/***************************************************************************
- *UBUS_TIMEOUT - UBUS Timeout
- ***************************************************************************/
-/* PCIE_0_MISC :: UBUS_TIMEOUT :: TIMER_VALUE [31:00] */
-#define BCHP_PCIE_0_MISC_UBUS_TIMEOUT_TIMER_VALUE_MASK 0xffffffff
-#define BCHP_PCIE_0_MISC_UBUS_TIMEOUT_TIMER_VALUE_SHIFT 0
-#define BCHP_PCIE_0_MISC_UBUS_TIMEOUT_TIMER_VALUE_DEFAULT 0x00080000
-
-/***************************************************************************
- *UBUS_BAR1_CONFIG_REMAP - UBUS BAR1 System Bus Address Remap Register
- ***************************************************************************/
-/* PCIE_0_MISC :: UBUS_BAR1_CONFIG_REMAP :: OFFSET [31:12] */
-#define BCHP_PCIE_0_MISC_UBUS_BAR1_CONFIG_REMAP_OFFSET_MASK 0xfffff000
-#define BCHP_PCIE_0_MISC_UBUS_BAR1_CONFIG_REMAP_OFFSET_SHIFT 12
-#define BCHP_PCIE_0_MISC_UBUS_BAR1_CONFIG_REMAP_OFFSET_DEFAULT 0x00000000
-
-/* PCIE_0_MISC :: UBUS_BAR1_CONFIG_REMAP :: reserved0 [11:04] */
-#define BCHP_PCIE_0_MISC_UBUS_BAR1_CONFIG_REMAP_reserved0_MASK 0x00000ff0
-#define BCHP_PCIE_0_MISC_UBUS_BAR1_CONFIG_REMAP_reserved0_SHIFT 4
-
-/* PCIE_0_MISC :: UBUS_BAR1_CONFIG_REMAP :: UNUSED_3_2 [03:02] */
-#define BCHP_PCIE_0_MISC_UBUS_BAR1_CONFIG_REMAP_UNUSED_3_2_MASK 0x0000000c
-#define BCHP_PCIE_0_MISC_UBUS_BAR1_CONFIG_REMAP_UNUSED_3_2_SHIFT 2
-#define BCHP_PCIE_0_MISC_UBUS_BAR1_CONFIG_REMAP_UNUSED_3_2_DEFAULT 0x00000000
-
-/* PCIE_0_MISC :: UBUS_BAR1_CONFIG_REMAP :: WR_COMBINE [01:01] */
-#define BCHP_PCIE_0_MISC_UBUS_BAR1_CONFIG_REMAP_WR_COMBINE_MASK 0x00000002
-#define BCHP_PCIE_0_MISC_UBUS_BAR1_CONFIG_REMAP_WR_COMBINE_SHIFT 1
-#define BCHP_PCIE_0_MISC_UBUS_BAR1_CONFIG_REMAP_WR_COMBINE_DEFAULT 0x00000000
-
-/* PCIE_0_MISC :: UBUS_BAR1_CONFIG_REMAP :: ACCESS_EN [00:00] */
-#define BCHP_PCIE_0_MISC_UBUS_BAR1_CONFIG_REMAP_ACCESS_EN_MASK 0x00000001
-#define BCHP_PCIE_0_MISC_UBUS_BAR1_CONFIG_REMAP_ACCESS_EN_SHIFT 0
-#define BCHP_PCIE_0_MISC_UBUS_BAR1_CONFIG_REMAP_ACCESS_EN_DEFAULT 0x00000000
-
-/***************************************************************************
- *UBUS_BAR1_CONFIG_REMAP_HI - UBUS BAR2 System Bus Address Remap Register High
- ***************************************************************************/
-/* PCIE_0_MISC :: UBUS_BAR1_CONFIG_REMAP_HI :: reserved0 [31:08] */
-#define BCHP_PCIE_0_MISC_UBUS_BAR1_CONFIG_REMAP_HI_reserved0_MASK 0xffffff00
-#define BCHP_PCIE_0_MISC_UBUS_BAR1_CONFIG_REMAP_HI_reserved0_SHIFT 8
-
-/* PCIE_0_MISC :: UBUS_BAR1_CONFIG_REMAP_HI :: OFFSET [07:00] */
-#define BCHP_PCIE_0_MISC_UBUS_BAR1_CONFIG_REMAP_HI_OFFSET_MASK 0x000000ff
-#define BCHP_PCIE_0_MISC_UBUS_BAR1_CONFIG_REMAP_HI_OFFSET_SHIFT 0
-#define BCHP_PCIE_0_MISC_UBUS_BAR1_CONFIG_REMAP_HI_OFFSET_DEFAULT 0x00000000
-
-/***************************************************************************
- *UBUS_BAR2_CONFIG_REMAP - UBUS BAR2 System Bus Address Remap Register
- ***************************************************************************/
-/* PCIE_0_MISC :: UBUS_BAR2_CONFIG_REMAP :: OFFSET [31:12] */
-#define BCHP_PCIE_0_MISC_UBUS_BAR2_CONFIG_REMAP_OFFSET_MASK 0xfffff000
-#define BCHP_PCIE_0_MISC_UBUS_BAR2_CONFIG_REMAP_OFFSET_SHIFT 12
-#define BCHP_PCIE_0_MISC_UBUS_BAR2_CONFIG_REMAP_OFFSET_DEFAULT 0x00000000
-
-/* PCIE_0_MISC :: UBUS_BAR2_CONFIG_REMAP :: reserved0 [11:04] */
-#define BCHP_PCIE_0_MISC_UBUS_BAR2_CONFIG_REMAP_reserved0_MASK 0x00000ff0
-#define BCHP_PCIE_0_MISC_UBUS_BAR2_CONFIG_REMAP_reserved0_SHIFT 4
-
-/* PCIE_0_MISC :: UBUS_BAR2_CONFIG_REMAP :: UNUSED_3_2 [03:02] */
-#define BCHP_PCIE_0_MISC_UBUS_BAR2_CONFIG_REMAP_UNUSED_3_2_MASK 0x0000000c
-#define BCHP_PCIE_0_MISC_UBUS_BAR2_CONFIG_REMAP_UNUSED_3_2_SHIFT 2
-#define BCHP_PCIE_0_MISC_UBUS_BAR2_CONFIG_REMAP_UNUSED_3_2_DEFAULT 0x00000000
-
-/* PCIE_0_MISC :: UBUS_BAR2_CONFIG_REMAP :: WR_COMBINE [01:01] */
-#define BCHP_PCIE_0_MISC_UBUS_BAR2_CONFIG_REMAP_WR_COMBINE_MASK 0x00000002
-#define BCHP_PCIE_0_MISC_UBUS_BAR2_CONFIG_REMAP_WR_COMBINE_SHIFT 1
-#define BCHP_PCIE_0_MISC_UBUS_BAR2_CONFIG_REMAP_WR_COMBINE_DEFAULT 0x00000000
-
-/* PCIE_0_MISC :: UBUS_BAR2_CONFIG_REMAP :: ACCESS_EN [00:00] */
-#define BCHP_PCIE_0_MISC_UBUS_BAR2_CONFIG_REMAP_ACCESS_EN_MASK 0x00000001
-#define BCHP_PCIE_0_MISC_UBUS_BAR2_CONFIG_REMAP_ACCESS_EN_SHIFT 0
-#define BCHP_PCIE_0_MISC_UBUS_BAR2_CONFIG_REMAP_ACCESS_EN_DEFAULT 0x00000000
-
-/***************************************************************************
- *UBUS_BAR2_CONFIG_REMAP_HI - UBUS BAR2 System Bus Address Remap Register High
- ***************************************************************************/
-/* PCIE_0_MISC :: UBUS_BAR2_CONFIG_REMAP_HI :: reserved0 [31:08] */
-#define BCHP_PCIE_0_MISC_UBUS_BAR2_CONFIG_REMAP_HI_reserved0_MASK 0xffffff00
-#define BCHP_PCIE_0_MISC_UBUS_BAR2_CONFIG_REMAP_HI_reserved0_SHIFT 8
-
-/* PCIE_0_MISC :: UBUS_BAR2_CONFIG_REMAP_HI :: OFFSET [07:00] */
-#define BCHP_PCIE_0_MISC_UBUS_BAR2_CONFIG_REMAP_HI_OFFSET_MASK 0x000000ff
-#define BCHP_PCIE_0_MISC_UBUS_BAR2_CONFIG_REMAP_HI_OFFSET_SHIFT 0
-#define BCHP_PCIE_0_MISC_UBUS_BAR2_CONFIG_REMAP_HI_OFFSET_DEFAULT 0x00000000
-
-/***************************************************************************
- *UBUS_BAR3_CONFIG_REMAP - UBUS BAR3 System Bus Address Remap Register
- ***************************************************************************/
-/* PCIE_0_MISC :: UBUS_BAR3_CONFIG_REMAP :: OFFSET [31:12] */
-#define BCHP_PCIE_0_MISC_UBUS_BAR3_CONFIG_REMAP_OFFSET_MASK 0xfffff000
-#define BCHP_PCIE_0_MISC_UBUS_BAR3_CONFIG_REMAP_OFFSET_SHIFT 12
-#define BCHP_PCIE_0_MISC_UBUS_BAR3_CONFIG_REMAP_OFFSET_DEFAULT 0x00000000
-
-/* PCIE_0_MISC :: UBUS_BAR3_CONFIG_REMAP :: reserved0 [11:04] */
-#define BCHP_PCIE_0_MISC_UBUS_BAR3_CONFIG_REMAP_reserved0_MASK 0x00000ff0
-#define BCHP_PCIE_0_MISC_UBUS_BAR3_CONFIG_REMAP_reserved0_SHIFT 4
-
-/* PCIE_0_MISC :: UBUS_BAR3_CONFIG_REMAP :: UNUSED_3_2 [03:02] */
-#define BCHP_PCIE_0_MISC_UBUS_BAR3_CONFIG_REMAP_UNUSED_3_2_MASK 0x0000000c
-#define BCHP_PCIE_0_MISC_UBUS_BAR3_CONFIG_REMAP_UNUSED_3_2_SHIFT 2
-#define BCHP_PCIE_0_MISC_UBUS_BAR3_CONFIG_REMAP_UNUSED_3_2_DEFAULT 0x00000000
-
-/* PCIE_0_MISC :: UBUS_BAR3_CONFIG_REMAP :: WR_COMBINE [01:01] */
-#define BCHP_PCIE_0_MISC_UBUS_BAR3_CONFIG_REMAP_WR_COMBINE_MASK 0x00000002
-#define BCHP_PCIE_0_MISC_UBUS_BAR3_CONFIG_REMAP_WR_COMBINE_SHIFT 1
-#define BCHP_PCIE_0_MISC_UBUS_BAR3_CONFIG_REMAP_WR_COMBINE_DEFAULT 0x00000000
-
-/* PCIE_0_MISC :: UBUS_BAR3_CONFIG_REMAP :: ACCESS_EN [00:00] */
-#define BCHP_PCIE_0_MISC_UBUS_BAR3_CONFIG_REMAP_ACCESS_EN_MASK 0x00000001
-#define BCHP_PCIE_0_MISC_UBUS_BAR3_CONFIG_REMAP_ACCESS_EN_SHIFT 0
-#define BCHP_PCIE_0_MISC_UBUS_BAR3_CONFIG_REMAP_ACCESS_EN_DEFAULT 0x00000000
-
-/***************************************************************************
- *UBUS_BAR3_CONFIG_REMAP_HI - UBUS BAR3 System Bus Address Remap Register High
- ***************************************************************************/
-/* PCIE_0_MISC :: UBUS_BAR3_CONFIG_REMAP_HI :: reserved0 [31:08] */
-#define BCHP_PCIE_0_MISC_UBUS_BAR3_CONFIG_REMAP_HI_reserved0_MASK 0xffffff00
-#define BCHP_PCIE_0_MISC_UBUS_BAR3_CONFIG_REMAP_HI_reserved0_SHIFT 8
-
-/* PCIE_0_MISC :: UBUS_BAR3_CONFIG_REMAP_HI :: OFFSET [07:00] */
-#define BCHP_PCIE_0_MISC_UBUS_BAR3_CONFIG_REMAP_HI_OFFSET_MASK 0x000000ff
-#define BCHP_PCIE_0_MISC_UBUS_BAR3_CONFIG_REMAP_HI_OFFSET_SHIFT 0
-#define BCHP_PCIE_0_MISC_UBUS_BAR3_CONFIG_REMAP_HI_OFFSET_DEFAULT 0x00000000
-
-/***************************************************************************
- *UBUS_STATUS - UBUS Status
- ***************************************************************************/
-/* PCIE_0_MISC :: UBUS_STATUS :: SLAVE_REPOUT_HSPACE [31:24] */
-#define BCHP_PCIE_0_MISC_UBUS_STATUS_SLAVE_REPOUT_HSPACE_MASK 0xff000000
-#define BCHP_PCIE_0_MISC_UBUS_STATUS_SLAVE_REPOUT_HSPACE_SHIFT 24
-#define BCHP_PCIE_0_MISC_UBUS_STATUS_SLAVE_REPOUT_HSPACE_DEFAULT 0x00000000
-
-/* PCIE_0_MISC :: UBUS_STATUS :: SLAVE_REPOUT_DSPACE [23:16] */
-#define BCHP_PCIE_0_MISC_UBUS_STATUS_SLAVE_REPOUT_DSPACE_MASK 0x00ff0000
-#define BCHP_PCIE_0_MISC_UBUS_STATUS_SLAVE_REPOUT_DSPACE_SHIFT 16
-#define BCHP_PCIE_0_MISC_UBUS_STATUS_SLAVE_REPOUT_DSPACE_DEFAULT 0x00000000
-
-/* PCIE_0_MISC :: UBUS_STATUS :: MASTER_REQOUT_HSPACE [15:08] */
-#define BCHP_PCIE_0_MISC_UBUS_STATUS_MASTER_REQOUT_HSPACE_MASK 0x0000ff00
-#define BCHP_PCIE_0_MISC_UBUS_STATUS_MASTER_REQOUT_HSPACE_SHIFT 8
-#define BCHP_PCIE_0_MISC_UBUS_STATUS_MASTER_REQOUT_HSPACE_DEFAULT 0x00000000
-
-/* PCIE_0_MISC :: UBUS_STATUS :: MASTER_REQOUT_DSPACE [07:00] */
-#define BCHP_PCIE_0_MISC_UBUS_STATUS_MASTER_REQOUT_DSPACE_MASK 0x000000ff
-#define BCHP_PCIE_0_MISC_UBUS_STATUS_MASTER_REQOUT_DSPACE_SHIFT 0
-#define BCHP_PCIE_0_MISC_UBUS_STATUS_MASTER_REQOUT_DSPACE_DEFAULT 0x00000000
-
-#endif /* #ifndef BCHP_PCIE_0_MISC_H__ */
-
-/* End of File */
diff --git a/include/linux/brcmstb/7439a0/bchp_pcie_0_misc_perst.h b/include/linux/brcmstb/7439a0/bchp_pcie_0_misc_perst.h
deleted file mode 100644
index 7eadf74..0000000
--- a/include/linux/brcmstb/7439a0/bchp_pcie_0_misc_perst.h
+++ /dev/null
@@ -1,85 +0,0 @@
-/***************************************************************************
- * Copyright (c) 1999-2013, Broadcom Corporation
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
- *
- * Module Description:
- * DO NOT EDIT THIS FILE DIRECTLY
- *
- * This module was generated magically with RDB from a source description
- * file. You must edit the source file for changes to be made to this file.
- *
- *
- * Date: Generated on Tue Apr 16 03:26:50 2013
- * MD5 Checksum d41d8cd98f00b204e9800998ecf8427e
- *
- * Compiled with: RDB Utility combo_header.pl
- * RDB Parser 3.0
- * unknown unknown
- * Perl Interpreter 5.008008
- * Operating System linux
- *
- * Revision History:
- *
- * $brcm_Log: $
- *
- ***************************************************************************/
-
-#ifndef BCHP_PCIE_0_MISC_PERST_H__
-#define BCHP_PCIE_0_MISC_PERST_H__
-
-/***************************************************************************
- *PCIE_0_MISC_PERST - PCI-E Miscellaneous Registers (Fundamental reset)
- ***************************************************************************/
-#define BCHP_PCIE_0_MISC_PERST_ECO_CTRL_PERST 0x00474100 /* ECO PCIE Reset Control Register */
-#define BCHP_PCIE_0_MISC_PERST_CCE_STATUS 0x00474104 /* Config Copy Engine Status */
-
-/***************************************************************************
- *ECO_CTRL_PERST - ECO PCIE Reset Control Register
- ***************************************************************************/
-/* PCIE_0_MISC_PERST :: ECO_CTRL_PERST :: reserved0 [31:16] */
-#define BCHP_PCIE_0_MISC_PERST_ECO_CTRL_PERST_reserved0_MASK 0xffff0000
-#define BCHP_PCIE_0_MISC_PERST_ECO_CTRL_PERST_reserved0_SHIFT 16
-
-/* PCIE_0_MISC_PERST :: ECO_CTRL_PERST :: ECO_PERST_N [15:00] */
-#define BCHP_PCIE_0_MISC_PERST_ECO_CTRL_PERST_ECO_PERST_N_MASK 0x0000ffff
-#define BCHP_PCIE_0_MISC_PERST_ECO_CTRL_PERST_ECO_PERST_N_SHIFT 0
-#define BCHP_PCIE_0_MISC_PERST_ECO_CTRL_PERST_ECO_PERST_N_DEFAULT 0x00000000
-
-/***************************************************************************
- *CCE_STATUS - Config Copy Engine Status
- ***************************************************************************/
-/* PCIE_0_MISC_PERST :: CCE_STATUS :: CCE_DONE [31:31] */
-#define BCHP_PCIE_0_MISC_PERST_CCE_STATUS_CCE_DONE_MASK 0x80000000
-#define BCHP_PCIE_0_MISC_PERST_CCE_STATUS_CCE_DONE_SHIFT 31
-
-/* PCIE_0_MISC_PERST :: CCE_STATUS :: reserved0 [30:03] */
-#define BCHP_PCIE_0_MISC_PERST_CCE_STATUS_reserved0_MASK 0x7ffffff8
-#define BCHP_PCIE_0_MISC_PERST_CCE_STATUS_reserved0_SHIFT 3
-
-/* PCIE_0_MISC_PERST :: CCE_STATUS :: CCE_BAD_GISB_ACCESS [02:02] */
-#define BCHP_PCIE_0_MISC_PERST_CCE_STATUS_CCE_BAD_GISB_ACCESS_MASK 0x00000004
-#define BCHP_PCIE_0_MISC_PERST_CCE_STATUS_CCE_BAD_GISB_ACCESS_SHIFT 2
-
-/* PCIE_0_MISC_PERST :: CCE_STATUS :: CCE_BAD_I2C_ACCESS [01:01] */
-#define BCHP_PCIE_0_MISC_PERST_CCE_STATUS_CCE_BAD_I2C_ACCESS_MASK 0x00000002
-#define BCHP_PCIE_0_MISC_PERST_CCE_STATUS_CCE_BAD_I2C_ACCESS_SHIFT 1
-
-/* PCIE_0_MISC_PERST :: CCE_STATUS :: CCE_BAD_SECTION_ID [00:00] */
-#define BCHP_PCIE_0_MISC_PERST_CCE_STATUS_CCE_BAD_SECTION_ID_MASK 0x00000001
-#define BCHP_PCIE_0_MISC_PERST_CCE_STATUS_CCE_BAD_SECTION_ID_SHIFT 0
-
-#endif /* #ifndef BCHP_PCIE_0_MISC_PERST_H__ */
-
-/* End of File */
diff --git a/include/linux/brcmstb/7439a0/bchp_pcie_0_rc_cfg_pcie.h b/include/linux/brcmstb/7439a0/bchp_pcie_0_rc_cfg_pcie.h
deleted file mode 100644
index 5360fcc..0000000
--- a/include/linux/brcmstb/7439a0/bchp_pcie_0_rc_cfg_pcie.h
+++ /dev/null
@@ -1,644 +0,0 @@
-/***************************************************************************
- * Copyright (c) 1999-2013, Broadcom Corporation
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
- *
- * Module Description:
- * DO NOT EDIT THIS FILE DIRECTLY
- *
- * This module was generated magically with RDB from a source description
- * file. You must edit the source file for changes to be made to this file.
- *
- *
- * Date: Generated on Tue Apr 16 03:26:51 2013
- * MD5 Checksum d41d8cd98f00b204e9800998ecf8427e
- *
- * Compiled with: RDB Utility combo_header.pl
- * RDB Parser 3.0
- * unknown unknown
- * Perl Interpreter 5.008008
- * Operating System linux
- *
- * Revision History:
- *
- * $brcm_Log: $
- *
- ***************************************************************************/
-
-#ifndef BCHP_PCIE_0_RC_CFG_PCIE_H__
-#define BCHP_PCIE_0_RC_CFG_PCIE_H__
-
-/***************************************************************************
- *PCIE_0_RC_CFG_PCIE
- ***************************************************************************/
-#define BCHP_PCIE_0_RC_CFG_PCIE_PCIE_CAPABILITY 0x004700ac /* pcie_capability */
-#define BCHP_PCIE_0_RC_CFG_PCIE_DEVICE_CAPABILITY 0x004700b0 /* device_capability */
-#define BCHP_PCIE_0_RC_CFG_PCIE_DEVICE_STATUS_CONTROL 0x004700b4 /* device_status_control */
-#define BCHP_PCIE_0_RC_CFG_PCIE_LINK_CAPABILITY 0x004700b8 /* link_capability */
-#define BCHP_PCIE_0_RC_CFG_PCIE_LINK_STATUS_CONTROL 0x004700bc /* link_status_control */
-#define BCHP_PCIE_0_RC_CFG_PCIE_SLOT_CAPABILITY 0x004700c0 /* slot_capability */
-#define BCHP_PCIE_0_RC_CFG_PCIE_SLOT_CONTROL_STATUS 0x004700c4 /* slot_control_status */
-#define BCHP_PCIE_0_RC_CFG_PCIE_ROOT_CAP_CONTROL 0x004700c8 /* root_cap_control */
-#define BCHP_PCIE_0_RC_CFG_PCIE_ROOT_STATUS 0x004700cc /* root_status */
-#define BCHP_PCIE_0_RC_CFG_PCIE_DEVICE_CAPABILITY_2 0x004700d0 /* device_capability_2 */
-#define BCHP_PCIE_0_RC_CFG_PCIE_DEVICE_STATUS_CONTROL_2 0x004700d4 /* device_status_control_2 */
-#define BCHP_PCIE_0_RC_CFG_PCIE_LINK_CAPABILITY_2 0x004700d8 /* link_capability_2 */
-#define BCHP_PCIE_0_RC_CFG_PCIE_LINK_STATUS_CONTROL_2 0x004700dc /* link_status_control_2 */
-#define BCHP_PCIE_0_RC_CFG_PCIE_SLOT_CAPABILITY_2 0x004700e0 /* slot_capability_2 */
-#define BCHP_PCIE_0_RC_CFG_PCIE_SLOT_STATUS_CONTROL_2 0x004700e4 /* slot_status_control_2 */
-
-/***************************************************************************
- *PCIE_CAPABILITY - pcie_capability
- ***************************************************************************/
-/* PCIE_0_RC_CFG_PCIE :: PCIE_CAPABILITY :: RESERVED0 [31:30] */
-#define BCHP_PCIE_0_RC_CFG_PCIE_PCIE_CAPABILITY_RESERVED0_MASK 0xc0000000
-#define BCHP_PCIE_0_RC_CFG_PCIE_PCIE_CAPABILITY_RESERVED0_SHIFT 30
-
-/* PCIE_0_RC_CFG_PCIE :: PCIE_CAPABILITY :: MSG_NUM [29:25] */
-#define BCHP_PCIE_0_RC_CFG_PCIE_PCIE_CAPABILITY_MSG_NUM_MASK 0x3e000000
-#define BCHP_PCIE_0_RC_CFG_PCIE_PCIE_CAPABILITY_MSG_NUM_SHIFT 25
-#define BCHP_PCIE_0_RC_CFG_PCIE_PCIE_CAPABILITY_MSG_NUM_DEFAULT 0x00000000
-
-/* PCIE_0_RC_CFG_PCIE :: PCIE_CAPABILITY :: SLOT_IMPLEMENTED [24:24] */
-#define BCHP_PCIE_0_RC_CFG_PCIE_PCIE_CAPABILITY_SLOT_IMPLEMENTED_MASK 0x01000000
-#define BCHP_PCIE_0_RC_CFG_PCIE_PCIE_CAPABILITY_SLOT_IMPLEMENTED_SHIFT 24
-#define BCHP_PCIE_0_RC_CFG_PCIE_PCIE_CAPABILITY_SLOT_IMPLEMENTED_DEFAULT 0x00000000
-
-/* PCIE_0_RC_CFG_PCIE :: PCIE_CAPABILITY :: TYPE [23:20] */
-#define BCHP_PCIE_0_RC_CFG_PCIE_PCIE_CAPABILITY_TYPE_MASK 0x00f00000
-#define BCHP_PCIE_0_RC_CFG_PCIE_PCIE_CAPABILITY_TYPE_SHIFT 20
-#define BCHP_PCIE_0_RC_CFG_PCIE_PCIE_CAPABILITY_TYPE_DEFAULT 0x00000004
-
-/* PCIE_0_RC_CFG_PCIE :: PCIE_CAPABILITY :: VER [19:16] */
-#define BCHP_PCIE_0_RC_CFG_PCIE_PCIE_CAPABILITY_VER_MASK 0x000f0000
-#define BCHP_PCIE_0_RC_CFG_PCIE_PCIE_CAPABILITY_VER_SHIFT 16
-#define BCHP_PCIE_0_RC_CFG_PCIE_PCIE_CAPABILITY_VER_DEFAULT 0x00000002
-
-/* PCIE_0_RC_CFG_PCIE :: PCIE_CAPABILITY :: PCIE_NEXT_CAP_PTR [15:08] */
-#define BCHP_PCIE_0_RC_CFG_PCIE_PCIE_CAPABILITY_PCIE_NEXT_CAP_PTR_MASK 0x0000ff00
-#define BCHP_PCIE_0_RC_CFG_PCIE_PCIE_CAPABILITY_PCIE_NEXT_CAP_PTR_SHIFT 8
-#define BCHP_PCIE_0_RC_CFG_PCIE_PCIE_CAPABILITY_PCIE_NEXT_CAP_PTR_DEFAULT 0x00000000
-
-/* PCIE_0_RC_CFG_PCIE :: PCIE_CAPABILITY :: PCIE_CAP_ID [07:00] */
-#define BCHP_PCIE_0_RC_CFG_PCIE_PCIE_CAPABILITY_PCIE_CAP_ID_MASK 0x000000ff
-#define BCHP_PCIE_0_RC_CFG_PCIE_PCIE_CAPABILITY_PCIE_CAP_ID_SHIFT 0
-#define BCHP_PCIE_0_RC_CFG_PCIE_PCIE_CAPABILITY_PCIE_CAP_ID_DEFAULT 0x00000010
-
-/***************************************************************************
- *DEVICE_CAPABILITY - device_capability
- ***************************************************************************/
-/* PCIE_0_RC_CFG_PCIE :: DEVICE_CAPABILITY :: RESERVED3 [31:28] */
-#define BCHP_PCIE_0_RC_CFG_PCIE_DEVICE_CAPABILITY_RESERVED3_MASK 0xf0000000
-#define BCHP_PCIE_0_RC_CFG_PCIE_DEVICE_CAPABILITY_RESERVED3_SHIFT 28
-
-/* PCIE_0_RC_CFG_PCIE :: DEVICE_CAPABILITY :: CAPTURED_SLOT_PWR_SCALE [27:26] */
-#define BCHP_PCIE_0_RC_CFG_PCIE_DEVICE_CAPABILITY_CAPTURED_SLOT_PWR_SCALE_MASK 0x0c000000
-#define BCHP_PCIE_0_RC_CFG_PCIE_DEVICE_CAPABILITY_CAPTURED_SLOT_PWR_SCALE_SHIFT 26
-#define BCHP_PCIE_0_RC_CFG_PCIE_DEVICE_CAPABILITY_CAPTURED_SLOT_PWR_SCALE_DEFAULT 0x00000000
-
-/* PCIE_0_RC_CFG_PCIE :: DEVICE_CAPABILITY :: CAPTURED_SLOT_PWR_VAL [25:18] */
-#define BCHP_PCIE_0_RC_CFG_PCIE_DEVICE_CAPABILITY_CAPTURED_SLOT_PWR_VAL_MASK 0x03fc0000
-#define BCHP_PCIE_0_RC_CFG_PCIE_DEVICE_CAPABILITY_CAPTURED_SLOT_PWR_VAL_SHIFT 18
-#define BCHP_PCIE_0_RC_CFG_PCIE_DEVICE_CAPABILITY_CAPTURED_SLOT_PWR_VAL_DEFAULT 0x00000000
-
-/* PCIE_0_RC_CFG_PCIE :: DEVICE_CAPABILITY :: RESERVED2 [17:16] */
-#define BCHP_PCIE_0_RC_CFG_PCIE_DEVICE_CAPABILITY_RESERVED2_MASK 0x00030000
-#define BCHP_PCIE_0_RC_CFG_PCIE_DEVICE_CAPABILITY_RESERVED2_SHIFT 16
-
-/* PCIE_0_RC_CFG_PCIE :: DEVICE_CAPABILITY :: ROLE_BASED_ERR_RPT [15:15] */
-#define BCHP_PCIE_0_RC_CFG_PCIE_DEVICE_CAPABILITY_ROLE_BASED_ERR_RPT_MASK 0x00008000
-#define BCHP_PCIE_0_RC_CFG_PCIE_DEVICE_CAPABILITY_ROLE_BASED_ERR_RPT_SHIFT 15
-#define BCHP_PCIE_0_RC_CFG_PCIE_DEVICE_CAPABILITY_ROLE_BASED_ERR_RPT_DEFAULT 0x00000001
-
-/* PCIE_0_RC_CFG_PCIE :: DEVICE_CAPABILITY :: RESERVED1 [14:12] */
-#define BCHP_PCIE_0_RC_CFG_PCIE_DEVICE_CAPABILITY_RESERVED1_MASK 0x00007000
-#define BCHP_PCIE_0_RC_CFG_PCIE_DEVICE_CAPABILITY_RESERVED1_SHIFT 12
-
-/* PCIE_0_RC_CFG_PCIE :: DEVICE_CAPABILITY :: L1_ACCEPTABLE_LATENCY [11:09] */
-#define BCHP_PCIE_0_RC_CFG_PCIE_DEVICE_CAPABILITY_L1_ACCEPTABLE_LATENCY_MASK 0x00000e00
-#define BCHP_PCIE_0_RC_CFG_PCIE_DEVICE_CAPABILITY_L1_ACCEPTABLE_LATENCY_SHIFT 9
-#define BCHP_PCIE_0_RC_CFG_PCIE_DEVICE_CAPABILITY_L1_ACCEPTABLE_LATENCY_DEFAULT 0x00000000
-
-/* PCIE_0_RC_CFG_PCIE :: DEVICE_CAPABILITY :: L0S_ACCEPTABLE_LATENCY [08:06] */
-#define BCHP_PCIE_0_RC_CFG_PCIE_DEVICE_CAPABILITY_L0S_ACCEPTABLE_LATENCY_MASK 0x000001c0
-#define BCHP_PCIE_0_RC_CFG_PCIE_DEVICE_CAPABILITY_L0S_ACCEPTABLE_LATENCY_SHIFT 6
-#define BCHP_PCIE_0_RC_CFG_PCIE_DEVICE_CAPABILITY_L0S_ACCEPTABLE_LATENCY_DEFAULT 0x00000000
-
-/* PCIE_0_RC_CFG_PCIE :: DEVICE_CAPABILITY :: EXTENDED_TAG_SUPPORT [05:05] */
-#define BCHP_PCIE_0_RC_CFG_PCIE_DEVICE_CAPABILITY_EXTENDED_TAG_SUPPORT_MASK 0x00000020
-#define BCHP_PCIE_0_RC_CFG_PCIE_DEVICE_CAPABILITY_EXTENDED_TAG_SUPPORT_SHIFT 5
-#define BCHP_PCIE_0_RC_CFG_PCIE_DEVICE_CAPABILITY_EXTENDED_TAG_SUPPORT_DEFAULT 0x00000000
-
-/* PCIE_0_RC_CFG_PCIE :: DEVICE_CAPABILITY :: RESERVED0 [04:03] */
-#define BCHP_PCIE_0_RC_CFG_PCIE_DEVICE_CAPABILITY_RESERVED0_MASK 0x00000018
-#define BCHP_PCIE_0_RC_CFG_PCIE_DEVICE_CAPABILITY_RESERVED0_SHIFT 3
-
-/* PCIE_0_RC_CFG_PCIE :: DEVICE_CAPABILITY :: MAX_PL_SIZE_SUPPORTED [02:00] */
-#define BCHP_PCIE_0_RC_CFG_PCIE_DEVICE_CAPABILITY_MAX_PL_SIZE_SUPPORTED_MASK 0x00000007
-#define BCHP_PCIE_0_RC_CFG_PCIE_DEVICE_CAPABILITY_MAX_PL_SIZE_SUPPORTED_SHIFT 0
-#define BCHP_PCIE_0_RC_CFG_PCIE_DEVICE_CAPABILITY_MAX_PL_SIZE_SUPPORTED_DEFAULT 0x00000002
-
-/***************************************************************************
- *DEVICE_STATUS_CONTROL - device_status_control
- ***************************************************************************/
-/* PCIE_0_RC_CFG_PCIE :: DEVICE_STATUS_CONTROL :: RESERVED2 [31:22] */
-#define BCHP_PCIE_0_RC_CFG_PCIE_DEVICE_STATUS_CONTROL_RESERVED2_MASK 0xffc00000
-#define BCHP_PCIE_0_RC_CFG_PCIE_DEVICE_STATUS_CONTROL_RESERVED2_SHIFT 22
-
-/* PCIE_0_RC_CFG_PCIE :: DEVICE_STATUS_CONTROL :: NP_TRANSACTION_PEND [21:21] */
-#define BCHP_PCIE_0_RC_CFG_PCIE_DEVICE_STATUS_CONTROL_NP_TRANSACTION_PEND_MASK 0x00200000
-#define BCHP_PCIE_0_RC_CFG_PCIE_DEVICE_STATUS_CONTROL_NP_TRANSACTION_PEND_SHIFT 21
-#define BCHP_PCIE_0_RC_CFG_PCIE_DEVICE_STATUS_CONTROL_NP_TRANSACTION_PEND_DEFAULT 0x00000000
-
-/* PCIE_0_RC_CFG_PCIE :: DEVICE_STATUS_CONTROL :: AUX_PWR_DET [20:20] */
-#define BCHP_PCIE_0_RC_CFG_PCIE_DEVICE_STATUS_CONTROL_AUX_PWR_DET_MASK 0x00100000
-#define BCHP_PCIE_0_RC_CFG_PCIE_DEVICE_STATUS_CONTROL_AUX_PWR_DET_SHIFT 20
-#define BCHP_PCIE_0_RC_CFG_PCIE_DEVICE_STATUS_CONTROL_AUX_PWR_DET_DEFAULT 0x00000001
-
-/* PCIE_0_RC_CFG_PCIE :: DEVICE_STATUS_CONTROL :: UNSUP_REQ_DET [19:19] */
-#define BCHP_PCIE_0_RC_CFG_PCIE_DEVICE_STATUS_CONTROL_UNSUP_REQ_DET_MASK 0x00080000
-#define BCHP_PCIE_0_RC_CFG_PCIE_DEVICE_STATUS_CONTROL_UNSUP_REQ_DET_SHIFT 19
-#define BCHP_PCIE_0_RC_CFG_PCIE_DEVICE_STATUS_CONTROL_UNSUP_REQ_DET_DEFAULT 0x00000000
-
-/* PCIE_0_RC_CFG_PCIE :: DEVICE_STATUS_CONTROL :: FATAL_ERR_DET [18:18] */
-#define BCHP_PCIE_0_RC_CFG_PCIE_DEVICE_STATUS_CONTROL_FATAL_ERR_DET_MASK 0x00040000
-#define BCHP_PCIE_0_RC_CFG_PCIE_DEVICE_STATUS_CONTROL_FATAL_ERR_DET_SHIFT 18
-#define BCHP_PCIE_0_RC_CFG_PCIE_DEVICE_STATUS_CONTROL_FATAL_ERR_DET_DEFAULT 0x00000000
-
-/* PCIE_0_RC_CFG_PCIE :: DEVICE_STATUS_CONTROL :: NON_FATAL_ERR_DET [17:17] */
-#define BCHP_PCIE_0_RC_CFG_PCIE_DEVICE_STATUS_CONTROL_NON_FATAL_ERR_DET_MASK 0x00020000
-#define BCHP_PCIE_0_RC_CFG_PCIE_DEVICE_STATUS_CONTROL_NON_FATAL_ERR_DET_SHIFT 17
-#define BCHP_PCIE_0_RC_CFG_PCIE_DEVICE_STATUS_CONTROL_NON_FATAL_ERR_DET_DEFAULT 0x00000000
-
-/* PCIE_0_RC_CFG_PCIE :: DEVICE_STATUS_CONTROL :: CORR_ERR_DET [16:16] */
-#define BCHP_PCIE_0_RC_CFG_PCIE_DEVICE_STATUS_CONTROL_CORR_ERR_DET_MASK 0x00010000
-#define BCHP_PCIE_0_RC_CFG_PCIE_DEVICE_STATUS_CONTROL_CORR_ERR_DET_SHIFT 16
-#define BCHP_PCIE_0_RC_CFG_PCIE_DEVICE_STATUS_CONTROL_CORR_ERR_DET_DEFAULT 0x00000000
-
-/* PCIE_0_RC_CFG_PCIE :: DEVICE_STATUS_CONTROL :: RESERVED1 [15:15] */
-#define BCHP_PCIE_0_RC_CFG_PCIE_DEVICE_STATUS_CONTROL_RESERVED1_MASK 0x00008000
-#define BCHP_PCIE_0_RC_CFG_PCIE_DEVICE_STATUS_CONTROL_RESERVED1_SHIFT 15
-
-/* PCIE_0_RC_CFG_PCIE :: DEVICE_STATUS_CONTROL :: MAX_READ_REQ_SIZ [14:12] */
-#define BCHP_PCIE_0_RC_CFG_PCIE_DEVICE_STATUS_CONTROL_MAX_READ_REQ_SIZ_MASK 0x00007000
-#define BCHP_PCIE_0_RC_CFG_PCIE_DEVICE_STATUS_CONTROL_MAX_READ_REQ_SIZ_SHIFT 12
-#define BCHP_PCIE_0_RC_CFG_PCIE_DEVICE_STATUS_CONTROL_MAX_READ_REQ_SIZ_DEFAULT 0x00000002
-
-/* PCIE_0_RC_CFG_PCIE :: DEVICE_STATUS_CONTROL :: NO_SNOOP_ENABLE [11:11] */
-#define BCHP_PCIE_0_RC_CFG_PCIE_DEVICE_STATUS_CONTROL_NO_SNOOP_ENABLE_MASK 0x00000800
-#define BCHP_PCIE_0_RC_CFG_PCIE_DEVICE_STATUS_CONTROL_NO_SNOOP_ENABLE_SHIFT 11
-#define BCHP_PCIE_0_RC_CFG_PCIE_DEVICE_STATUS_CONTROL_NO_SNOOP_ENABLE_DEFAULT 0x00000001
-
-/* PCIE_0_RC_CFG_PCIE :: DEVICE_STATUS_CONTROL :: AUX_PWR_PM_ENA [10:10] */
-#define BCHP_PCIE_0_RC_CFG_PCIE_DEVICE_STATUS_CONTROL_AUX_PWR_PM_ENA_MASK 0x00000400
-#define BCHP_PCIE_0_RC_CFG_PCIE_DEVICE_STATUS_CONTROL_AUX_PWR_PM_ENA_SHIFT 10
-#define BCHP_PCIE_0_RC_CFG_PCIE_DEVICE_STATUS_CONTROL_AUX_PWR_PM_ENA_DEFAULT 0x00000001
-
-/* PCIE_0_RC_CFG_PCIE :: DEVICE_STATUS_CONTROL :: RESERVED0 [09:09] */
-#define BCHP_PCIE_0_RC_CFG_PCIE_DEVICE_STATUS_CONTROL_RESERVED0_MASK 0x00000200
-#define BCHP_PCIE_0_RC_CFG_PCIE_DEVICE_STATUS_CONTROL_RESERVED0_SHIFT 9
-
-/* PCIE_0_RC_CFG_PCIE :: DEVICE_STATUS_CONTROL :: EXTENDED_TAG_EN [08:08] */
-#define BCHP_PCIE_0_RC_CFG_PCIE_DEVICE_STATUS_CONTROL_EXTENDED_TAG_EN_MASK 0x00000100
-#define BCHP_PCIE_0_RC_CFG_PCIE_DEVICE_STATUS_CONTROL_EXTENDED_TAG_EN_SHIFT 8
-#define BCHP_PCIE_0_RC_CFG_PCIE_DEVICE_STATUS_CONTROL_EXTENDED_TAG_EN_DEFAULT 0x00000000
-
-/* PCIE_0_RC_CFG_PCIE :: DEVICE_STATUS_CONTROL :: MAX_PAYLOAD_SIZE [07:05] */
-#define BCHP_PCIE_0_RC_CFG_PCIE_DEVICE_STATUS_CONTROL_MAX_PAYLOAD_SIZE_MASK 0x000000e0
-#define BCHP_PCIE_0_RC_CFG_PCIE_DEVICE_STATUS_CONTROL_MAX_PAYLOAD_SIZE_SHIFT 5
-#define BCHP_PCIE_0_RC_CFG_PCIE_DEVICE_STATUS_CONTROL_MAX_PAYLOAD_SIZE_DEFAULT 0x00000000
-
-/* PCIE_0_RC_CFG_PCIE :: DEVICE_STATUS_CONTROL :: RELAX_ORDERING_ENABLE [04:04] */
-#define BCHP_PCIE_0_RC_CFG_PCIE_DEVICE_STATUS_CONTROL_RELAX_ORDERING_ENABLE_MASK 0x00000010
-#define BCHP_PCIE_0_RC_CFG_PCIE_DEVICE_STATUS_CONTROL_RELAX_ORDERING_ENABLE_SHIFT 4
-#define BCHP_PCIE_0_RC_CFG_PCIE_DEVICE_STATUS_CONTROL_RELAX_ORDERING_ENABLE_DEFAULT 0x00000001
-
-/* PCIE_0_RC_CFG_PCIE :: DEVICE_STATUS_CONTROL :: U_REQ_REPORT_EN [03:03] */
-#define BCHP_PCIE_0_RC_CFG_PCIE_DEVICE_STATUS_CONTROL_U_REQ_REPORT_EN_MASK 0x00000008
-#define BCHP_PCIE_0_RC_CFG_PCIE_DEVICE_STATUS_CONTROL_U_REQ_REPORT_EN_SHIFT 3
-#define BCHP_PCIE_0_RC_CFG_PCIE_DEVICE_STATUS_CONTROL_U_REQ_REPORT_EN_DEFAULT 0x00000000
-
-/* PCIE_0_RC_CFG_PCIE :: DEVICE_STATUS_CONTROL :: FATAL_ERR_REPORT_EN [02:02] */
-#define BCHP_PCIE_0_RC_CFG_PCIE_DEVICE_STATUS_CONTROL_FATAL_ERR_REPORT_EN_MASK 0x00000004
-#define BCHP_PCIE_0_RC_CFG_PCIE_DEVICE_STATUS_CONTROL_FATAL_ERR_REPORT_EN_SHIFT 2
-#define BCHP_PCIE_0_RC_CFG_PCIE_DEVICE_STATUS_CONTROL_FATAL_ERR_REPORT_EN_DEFAULT 0x00000000
-
-/* PCIE_0_RC_CFG_PCIE :: DEVICE_STATUS_CONTROL :: NFATAL_ERR_REPORT_EN [01:01] */
-#define BCHP_PCIE_0_RC_CFG_PCIE_DEVICE_STATUS_CONTROL_NFATAL_ERR_REPORT_EN_MASK 0x00000002
-#define BCHP_PCIE_0_RC_CFG_PCIE_DEVICE_STATUS_CONTROL_NFATAL_ERR_REPORT_EN_SHIFT 1
-#define BCHP_PCIE_0_RC_CFG_PCIE_DEVICE_STATUS_CONTROL_NFATAL_ERR_REPORT_EN_DEFAULT 0x00000000
-
-/* PCIE_0_RC_CFG_PCIE :: DEVICE_STATUS_CONTROL :: CORR_ERR_REPORT_EN [00:00] */
-#define BCHP_PCIE_0_RC_CFG_PCIE_DEVICE_STATUS_CONTROL_CORR_ERR_REPORT_EN_MASK 0x00000001
-#define BCHP_PCIE_0_RC_CFG_PCIE_DEVICE_STATUS_CONTROL_CORR_ERR_REPORT_EN_SHIFT 0
-#define BCHP_PCIE_0_RC_CFG_PCIE_DEVICE_STATUS_CONTROL_CORR_ERR_REPORT_EN_DEFAULT 0x00000000
-
-/***************************************************************************
- *LINK_CAPABILITY - link_capability
- ***************************************************************************/
-/* PCIE_0_RC_CFG_PCIE :: LINK_CAPABILITY :: PORT_NUMBER [31:24] */
-#define BCHP_PCIE_0_RC_CFG_PCIE_LINK_CAPABILITY_PORT_NUMBER_MASK 0xff000000
-#define BCHP_PCIE_0_RC_CFG_PCIE_LINK_CAPABILITY_PORT_NUMBER_SHIFT 24
-#define BCHP_PCIE_0_RC_CFG_PCIE_LINK_CAPABILITY_PORT_NUMBER_DEFAULT 0x00000000
-
-/* PCIE_0_RC_CFG_PCIE :: LINK_CAPABILITY :: RESERVED0 [23:23] */
-#define BCHP_PCIE_0_RC_CFG_PCIE_LINK_CAPABILITY_RESERVED0_MASK 0x00800000
-#define BCHP_PCIE_0_RC_CFG_PCIE_LINK_CAPABILITY_RESERVED0_SHIFT 23
-
-/* PCIE_0_RC_CFG_PCIE :: LINK_CAPABILITY :: ASPM_OPTIONALITY [22:22] */
-#define BCHP_PCIE_0_RC_CFG_PCIE_LINK_CAPABILITY_ASPM_OPTIONALITY_MASK 0x00400000
-#define BCHP_PCIE_0_RC_CFG_PCIE_LINK_CAPABILITY_ASPM_OPTIONALITY_SHIFT 22
-#define BCHP_PCIE_0_RC_CFG_PCIE_LINK_CAPABILITY_ASPM_OPTIONALITY_DEFAULT 0x00000001
-
-/* PCIE_0_RC_CFG_PCIE :: LINK_CAPABILITY :: LINK_BW_NOTIFY [21:21] */
-#define BCHP_PCIE_0_RC_CFG_PCIE_LINK_CAPABILITY_LINK_BW_NOTIFY_MASK 0x00200000
-#define BCHP_PCIE_0_RC_CFG_PCIE_LINK_CAPABILITY_LINK_BW_NOTIFY_SHIFT 21
-#define BCHP_PCIE_0_RC_CFG_PCIE_LINK_CAPABILITY_LINK_BW_NOTIFY_DEFAULT 0x00000000
-
-/* PCIE_0_RC_CFG_PCIE :: LINK_CAPABILITY :: DL_ACTIVE_REP [20:20] */
-#define BCHP_PCIE_0_RC_CFG_PCIE_LINK_CAPABILITY_DL_ACTIVE_REP_MASK 0x00100000
-#define BCHP_PCIE_0_RC_CFG_PCIE_LINK_CAPABILITY_DL_ACTIVE_REP_SHIFT 20
-#define BCHP_PCIE_0_RC_CFG_PCIE_LINK_CAPABILITY_DL_ACTIVE_REP_DEFAULT 0x00000000
-
-/* PCIE_0_RC_CFG_PCIE :: LINK_CAPABILITY :: SUR_DWN_ERR_REP [19:19] */
-#define BCHP_PCIE_0_RC_CFG_PCIE_LINK_CAPABILITY_SUR_DWN_ERR_REP_MASK 0x00080000
-#define BCHP_PCIE_0_RC_CFG_PCIE_LINK_CAPABILITY_SUR_DWN_ERR_REP_SHIFT 19
-#define BCHP_PCIE_0_RC_CFG_PCIE_LINK_CAPABILITY_SUR_DWN_ERR_REP_DEFAULT 0x00000000
-
-/* PCIE_0_RC_CFG_PCIE :: LINK_CAPABILITY :: CLK_PWR_MGMT [18:18] */
-#define BCHP_PCIE_0_RC_CFG_PCIE_LINK_CAPABILITY_CLK_PWR_MGMT_MASK 0x00040000
-#define BCHP_PCIE_0_RC_CFG_PCIE_LINK_CAPABILITY_CLK_PWR_MGMT_SHIFT 18
-#define BCHP_PCIE_0_RC_CFG_PCIE_LINK_CAPABILITY_CLK_PWR_MGMT_DEFAULT 0x00000001
-
-/* PCIE_0_RC_CFG_PCIE :: LINK_CAPABILITY :: L1_EXIT_LAT [17:15] */
-#define BCHP_PCIE_0_RC_CFG_PCIE_LINK_CAPABILITY_L1_EXIT_LAT_MASK 0x00038000
-#define BCHP_PCIE_0_RC_CFG_PCIE_LINK_CAPABILITY_L1_EXIT_LAT_SHIFT 15
-#define BCHP_PCIE_0_RC_CFG_PCIE_LINK_CAPABILITY_L1_EXIT_LAT_DEFAULT 0x00000002
-
-/* PCIE_0_RC_CFG_PCIE :: LINK_CAPABILITY :: L0S_EXIT_LAT [14:12] */
-#define BCHP_PCIE_0_RC_CFG_PCIE_LINK_CAPABILITY_L0S_EXIT_LAT_MASK 0x00007000
-#define BCHP_PCIE_0_RC_CFG_PCIE_LINK_CAPABILITY_L0S_EXIT_LAT_SHIFT 12
-#define BCHP_PCIE_0_RC_CFG_PCIE_LINK_CAPABILITY_L0S_EXIT_LAT_DEFAULT 0x00000005
-
-/* PCIE_0_RC_CFG_PCIE :: LINK_CAPABILITY :: ASPM_SUPT [11:10] */
-#define BCHP_PCIE_0_RC_CFG_PCIE_LINK_CAPABILITY_ASPM_SUPT_MASK 0x00000c00
-#define BCHP_PCIE_0_RC_CFG_PCIE_LINK_CAPABILITY_ASPM_SUPT_SHIFT 10
-#define BCHP_PCIE_0_RC_CFG_PCIE_LINK_CAPABILITY_ASPM_SUPT_DEFAULT 0x00000003
-
-/* PCIE_0_RC_CFG_PCIE :: LINK_CAPABILITY :: MAX_LINK_WIDTH [09:04] */
-#define BCHP_PCIE_0_RC_CFG_PCIE_LINK_CAPABILITY_MAX_LINK_WIDTH_MASK 0x000003f0
-#define BCHP_PCIE_0_RC_CFG_PCIE_LINK_CAPABILITY_MAX_LINK_WIDTH_SHIFT 4
-#define BCHP_PCIE_0_RC_CFG_PCIE_LINK_CAPABILITY_MAX_LINK_WIDTH_DEFAULT 0x00000001
-
-/* PCIE_0_RC_CFG_PCIE :: LINK_CAPABILITY :: MAX_LINK_SPEED [03:00] */
-#define BCHP_PCIE_0_RC_CFG_PCIE_LINK_CAPABILITY_MAX_LINK_SPEED_MASK 0x0000000f
-#define BCHP_PCIE_0_RC_CFG_PCIE_LINK_CAPABILITY_MAX_LINK_SPEED_SHIFT 0
-#define BCHP_PCIE_0_RC_CFG_PCIE_LINK_CAPABILITY_MAX_LINK_SPEED_DEFAULT 0x00000002
-
-/***************************************************************************
- *LINK_STATUS_CONTROL - link_status_control
- ***************************************************************************/
-/* PCIE_0_RC_CFG_PCIE :: LINK_STATUS_CONTROL :: RESERVED3 [31:30] */
-#define BCHP_PCIE_0_RC_CFG_PCIE_LINK_STATUS_CONTROL_RESERVED3_MASK 0xc0000000
-#define BCHP_PCIE_0_RC_CFG_PCIE_LINK_STATUS_CONTROL_RESERVED3_SHIFT 30
-
-/* PCIE_0_RC_CFG_PCIE :: LINK_STATUS_CONTROL :: DL_ACTIVE [29:29] */
-#define BCHP_PCIE_0_RC_CFG_PCIE_LINK_STATUS_CONTROL_DL_ACTIVE_MASK 0x20000000
-#define BCHP_PCIE_0_RC_CFG_PCIE_LINK_STATUS_CONTROL_DL_ACTIVE_SHIFT 29
-#define BCHP_PCIE_0_RC_CFG_PCIE_LINK_STATUS_CONTROL_DL_ACTIVE_DEFAULT 0x00000000
-
-/* PCIE_0_RC_CFG_PCIE :: LINK_STATUS_CONTROL :: SLOT_CLK_CONFIG [28:28] */
-#define BCHP_PCIE_0_RC_CFG_PCIE_LINK_STATUS_CONTROL_SLOT_CLK_CONFIG_MASK 0x10000000
-#define BCHP_PCIE_0_RC_CFG_PCIE_LINK_STATUS_CONTROL_SLOT_CLK_CONFIG_SHIFT 28
-#define BCHP_PCIE_0_RC_CFG_PCIE_LINK_STATUS_CONTROL_SLOT_CLK_CONFIG_DEFAULT 0x00000001
-
-/* PCIE_0_RC_CFG_PCIE :: LINK_STATUS_CONTROL :: LINK_TRAINING [27:27] */
-#define BCHP_PCIE_0_RC_CFG_PCIE_LINK_STATUS_CONTROL_LINK_TRAINING_MASK 0x08000000
-#define BCHP_PCIE_0_RC_CFG_PCIE_LINK_STATUS_CONTROL_LINK_TRAINING_SHIFT 27
-#define BCHP_PCIE_0_RC_CFG_PCIE_LINK_STATUS_CONTROL_LINK_TRAINING_DEFAULT 0x00000000
-
-/* PCIE_0_RC_CFG_PCIE :: LINK_STATUS_CONTROL :: RESERVED2 [26:26] */
-#define BCHP_PCIE_0_RC_CFG_PCIE_LINK_STATUS_CONTROL_RESERVED2_MASK 0x04000000
-#define BCHP_PCIE_0_RC_CFG_PCIE_LINK_STATUS_CONTROL_RESERVED2_SHIFT 26
-
-/* PCIE_0_RC_CFG_PCIE :: LINK_STATUS_CONTROL :: NEG_LINK_WIDTH [25:20] */
-#define BCHP_PCIE_0_RC_CFG_PCIE_LINK_STATUS_CONTROL_NEG_LINK_WIDTH_MASK 0x03f00000
-#define BCHP_PCIE_0_RC_CFG_PCIE_LINK_STATUS_CONTROL_NEG_LINK_WIDTH_SHIFT 20
-#define BCHP_PCIE_0_RC_CFG_PCIE_LINK_STATUS_CONTROL_NEG_LINK_WIDTH_DEFAULT 0x00000000
-
-/* PCIE_0_RC_CFG_PCIE :: LINK_STATUS_CONTROL :: NEG_LINK_SPEED [19:16] */
-#define BCHP_PCIE_0_RC_CFG_PCIE_LINK_STATUS_CONTROL_NEG_LINK_SPEED_MASK 0x000f0000
-#define BCHP_PCIE_0_RC_CFG_PCIE_LINK_STATUS_CONTROL_NEG_LINK_SPEED_SHIFT 16
-#define BCHP_PCIE_0_RC_CFG_PCIE_LINK_STATUS_CONTROL_NEG_LINK_SPEED_DEFAULT 0x00000000
-
-/* PCIE_0_RC_CFG_PCIE :: LINK_STATUS_CONTROL :: RESERVED1 [15:12] */
-#define BCHP_PCIE_0_RC_CFG_PCIE_LINK_STATUS_CONTROL_RESERVED1_MASK 0x0000f000
-#define BCHP_PCIE_0_RC_CFG_PCIE_LINK_STATUS_CONTROL_RESERVED1_SHIFT 12
-
-/* PCIE_0_RC_CFG_PCIE :: LINK_STATUS_CONTROL :: LINK_BW_INT_EN [11:11] */
-#define BCHP_PCIE_0_RC_CFG_PCIE_LINK_STATUS_CONTROL_LINK_BW_INT_EN_MASK 0x00000800
-#define BCHP_PCIE_0_RC_CFG_PCIE_LINK_STATUS_CONTROL_LINK_BW_INT_EN_SHIFT 11
-#define BCHP_PCIE_0_RC_CFG_PCIE_LINK_STATUS_CONTROL_LINK_BW_INT_EN_DEFAULT 0x00000000
-
-/* PCIE_0_RC_CFG_PCIE :: LINK_STATUS_CONTROL :: LINK_BW_MGMT_INT_EN [10:10] */
-#define BCHP_PCIE_0_RC_CFG_PCIE_LINK_STATUS_CONTROL_LINK_BW_MGMT_INT_EN_MASK 0x00000400
-#define BCHP_PCIE_0_RC_CFG_PCIE_LINK_STATUS_CONTROL_LINK_BW_MGMT_INT_EN_SHIFT 10
-#define BCHP_PCIE_0_RC_CFG_PCIE_LINK_STATUS_CONTROL_LINK_BW_MGMT_INT_EN_DEFAULT 0x00000000
-
-/* PCIE_0_RC_CFG_PCIE :: LINK_STATUS_CONTROL :: HW_AUTO_WIDTH_DIS [09:09] */
-#define BCHP_PCIE_0_RC_CFG_PCIE_LINK_STATUS_CONTROL_HW_AUTO_WIDTH_DIS_MASK 0x00000200
-#define BCHP_PCIE_0_RC_CFG_PCIE_LINK_STATUS_CONTROL_HW_AUTO_WIDTH_DIS_SHIFT 9
-#define BCHP_PCIE_0_RC_CFG_PCIE_LINK_STATUS_CONTROL_HW_AUTO_WIDTH_DIS_DEFAULT 0x00000000
-
-/* PCIE_0_RC_CFG_PCIE :: LINK_STATUS_CONTROL :: EN_CLK_PW_MGMT [08:08] */
-#define BCHP_PCIE_0_RC_CFG_PCIE_LINK_STATUS_CONTROL_EN_CLK_PW_MGMT_MASK 0x00000100
-#define BCHP_PCIE_0_RC_CFG_PCIE_LINK_STATUS_CONTROL_EN_CLK_PW_MGMT_SHIFT 8
-#define BCHP_PCIE_0_RC_CFG_PCIE_LINK_STATUS_CONTROL_EN_CLK_PW_MGMT_DEFAULT 0x00000000
-
-/* PCIE_0_RC_CFG_PCIE :: LINK_STATUS_CONTROL :: LINK_CR_EXT_SYNC [07:07] */
-#define BCHP_PCIE_0_RC_CFG_PCIE_LINK_STATUS_CONTROL_LINK_CR_EXT_SYNC_MASK 0x00000080
-#define BCHP_PCIE_0_RC_CFG_PCIE_LINK_STATUS_CONTROL_LINK_CR_EXT_SYNC_SHIFT 7
-#define BCHP_PCIE_0_RC_CFG_PCIE_LINK_STATUS_CONTROL_LINK_CR_EXT_SYNC_DEFAULT 0x00000000
-
-/* PCIE_0_RC_CFG_PCIE :: LINK_STATUS_CONTROL :: LINK_CR_COMMON_CLK [06:06] */
-#define BCHP_PCIE_0_RC_CFG_PCIE_LINK_STATUS_CONTROL_LINK_CR_COMMON_CLK_MASK 0x00000040
-#define BCHP_PCIE_0_RC_CFG_PCIE_LINK_STATUS_CONTROL_LINK_CR_COMMON_CLK_SHIFT 6
-#define BCHP_PCIE_0_RC_CFG_PCIE_LINK_STATUS_CONTROL_LINK_CR_COMMON_CLK_DEFAULT 0x00000000
-
-/* PCIE_0_RC_CFG_PCIE :: LINK_STATUS_CONTROL :: CFG_PSM_RETRAIN_LINK [05:05] */
-#define BCHP_PCIE_0_RC_CFG_PCIE_LINK_STATUS_CONTROL_CFG_PSM_RETRAIN_LINK_MASK 0x00000020
-#define BCHP_PCIE_0_RC_CFG_PCIE_LINK_STATUS_CONTROL_CFG_PSM_RETRAIN_LINK_SHIFT 5
-#define BCHP_PCIE_0_RC_CFG_PCIE_LINK_STATUS_CONTROL_CFG_PSM_RETRAIN_LINK_DEFAULT 0x00000000
-
-/* PCIE_0_RC_CFG_PCIE :: LINK_STATUS_CONTROL :: CFG_PSM_LINK_DISABLE [04:04] */
-#define BCHP_PCIE_0_RC_CFG_PCIE_LINK_STATUS_CONTROL_CFG_PSM_LINK_DISABLE_MASK 0x00000010
-#define BCHP_PCIE_0_RC_CFG_PCIE_LINK_STATUS_CONTROL_CFG_PSM_LINK_DISABLE_SHIFT 4
-#define BCHP_PCIE_0_RC_CFG_PCIE_LINK_STATUS_CONTROL_CFG_PSM_LINK_DISABLE_DEFAULT 0x00000000
-
-/* PCIE_0_RC_CFG_PCIE :: LINK_STATUS_CONTROL :: RCB [03:03] */
-#define BCHP_PCIE_0_RC_CFG_PCIE_LINK_STATUS_CONTROL_RCB_MASK 0x00000008
-#define BCHP_PCIE_0_RC_CFG_PCIE_LINK_STATUS_CONTROL_RCB_SHIFT 3
-#define BCHP_PCIE_0_RC_CFG_PCIE_LINK_STATUS_CONTROL_RCB_DEFAULT 0x00000000
-
-/* PCIE_0_RC_CFG_PCIE :: LINK_STATUS_CONTROL :: RESERVED0 [02:02] */
-#define BCHP_PCIE_0_RC_CFG_PCIE_LINK_STATUS_CONTROL_RESERVED0_MASK 0x00000004
-#define BCHP_PCIE_0_RC_CFG_PCIE_LINK_STATUS_CONTROL_RESERVED0_SHIFT 2
-
-/* PCIE_0_RC_CFG_PCIE :: LINK_STATUS_CONTROL :: ASPM_CTRL [01:00] */
-#define BCHP_PCIE_0_RC_CFG_PCIE_LINK_STATUS_CONTROL_ASPM_CTRL_MASK 0x00000003
-#define BCHP_PCIE_0_RC_CFG_PCIE_LINK_STATUS_CONTROL_ASPM_CTRL_SHIFT 0
-#define BCHP_PCIE_0_RC_CFG_PCIE_LINK_STATUS_CONTROL_ASPM_CTRL_DEFAULT 0x00000000
-
-/***************************************************************************
- *SLOT_CAPABILITY - slot_capability
- ***************************************************************************/
-/* PCIE_0_RC_CFG_PCIE :: SLOT_CAPABILITY :: PHYSICAL_SLOT_NUMBER [31:19] */
-#define BCHP_PCIE_0_RC_CFG_PCIE_SLOT_CAPABILITY_PHYSICAL_SLOT_NUMBER_MASK 0xfff80000
-#define BCHP_PCIE_0_RC_CFG_PCIE_SLOT_CAPABILITY_PHYSICAL_SLOT_NUMBER_SHIFT 19
-#define BCHP_PCIE_0_RC_CFG_PCIE_SLOT_CAPABILITY_PHYSICAL_SLOT_NUMBER_DEFAULT 0x00000000
-
-/* PCIE_0_RC_CFG_PCIE :: SLOT_CAPABILITY :: UNUSED [18:17] */
-#define BCHP_PCIE_0_RC_CFG_PCIE_SLOT_CAPABILITY_UNUSED_MASK 0x00060000
-#define BCHP_PCIE_0_RC_CFG_PCIE_SLOT_CAPABILITY_UNUSED_SHIFT 17
-#define BCHP_PCIE_0_RC_CFG_PCIE_SLOT_CAPABILITY_UNUSED_DEFAULT 0x00000000
-
-/* PCIE_0_RC_CFG_PCIE :: SLOT_CAPABILITY :: SLOT_POWER_LIMIT_SCALE [16:15] */
-#define BCHP_PCIE_0_RC_CFG_PCIE_SLOT_CAPABILITY_SLOT_POWER_LIMIT_SCALE_MASK 0x00018000
-#define BCHP_PCIE_0_RC_CFG_PCIE_SLOT_CAPABILITY_SLOT_POWER_LIMIT_SCALE_SHIFT 15
-#define BCHP_PCIE_0_RC_CFG_PCIE_SLOT_CAPABILITY_SLOT_POWER_LIMIT_SCALE_DEFAULT 0x00000000
-
-/* PCIE_0_RC_CFG_PCIE :: SLOT_CAPABILITY :: SLOT_POWER_LIMIT_VALUE [14:07] */
-#define BCHP_PCIE_0_RC_CFG_PCIE_SLOT_CAPABILITY_SLOT_POWER_LIMIT_VALUE_MASK 0x00007f80
-#define BCHP_PCIE_0_RC_CFG_PCIE_SLOT_CAPABILITY_SLOT_POWER_LIMIT_VALUE_SHIFT 7
-#define BCHP_PCIE_0_RC_CFG_PCIE_SLOT_CAPABILITY_SLOT_POWER_LIMIT_VALUE_DEFAULT 0x00000000
-
-/* PCIE_0_RC_CFG_PCIE :: SLOT_CAPABILITY :: UNUSED_2 [06:00] */
-#define BCHP_PCIE_0_RC_CFG_PCIE_SLOT_CAPABILITY_UNUSED_2_MASK 0x0000007f
-#define BCHP_PCIE_0_RC_CFG_PCIE_SLOT_CAPABILITY_UNUSED_2_SHIFT 0
-#define BCHP_PCIE_0_RC_CFG_PCIE_SLOT_CAPABILITY_UNUSED_2_DEFAULT 0x00000000
-
-/***************************************************************************
- *SLOT_CONTROL_STATUS - slot_control_status
- ***************************************************************************/
-/* PCIE_0_RC_CFG_PCIE :: SLOT_CONTROL_STATUS :: SLOT_STATUS [31:23] */
-#define BCHP_PCIE_0_RC_CFG_PCIE_SLOT_CONTROL_STATUS_SLOT_STATUS_MASK 0xff800000
-#define BCHP_PCIE_0_RC_CFG_PCIE_SLOT_CONTROL_STATUS_SLOT_STATUS_SHIFT 23
-#define BCHP_PCIE_0_RC_CFG_PCIE_SLOT_CONTROL_STATUS_SLOT_STATUS_DEFAULT 0x00000000
-
-/* PCIE_0_RC_CFG_PCIE :: SLOT_CONTROL_STATUS :: PRESENCE_DETECT [22:22] */
-#define BCHP_PCIE_0_RC_CFG_PCIE_SLOT_CONTROL_STATUS_PRESENCE_DETECT_MASK 0x00400000
-#define BCHP_PCIE_0_RC_CFG_PCIE_SLOT_CONTROL_STATUS_PRESENCE_DETECT_SHIFT 22
-#define BCHP_PCIE_0_RC_CFG_PCIE_SLOT_CONTROL_STATUS_PRESENCE_DETECT_DEFAULT 0x00000001
-
-/* PCIE_0_RC_CFG_PCIE :: SLOT_CONTROL_STATUS :: UNUSED_1 [21:16] */
-#define BCHP_PCIE_0_RC_CFG_PCIE_SLOT_CONTROL_STATUS_UNUSED_1_MASK 0x003f0000
-#define BCHP_PCIE_0_RC_CFG_PCIE_SLOT_CONTROL_STATUS_UNUSED_1_SHIFT 16
-#define BCHP_PCIE_0_RC_CFG_PCIE_SLOT_CONTROL_STATUS_UNUSED_1_DEFAULT 0x00000000
-
-/* PCIE_0_RC_CFG_PCIE :: SLOT_CONTROL_STATUS :: SLOT_CONTROL [15:00] */
-#define BCHP_PCIE_0_RC_CFG_PCIE_SLOT_CONTROL_STATUS_SLOT_CONTROL_MASK 0x0000ffff
-#define BCHP_PCIE_0_RC_CFG_PCIE_SLOT_CONTROL_STATUS_SLOT_CONTROL_SHIFT 0
-#define BCHP_PCIE_0_RC_CFG_PCIE_SLOT_CONTROL_STATUS_SLOT_CONTROL_DEFAULT 0x00000000
-
-/***************************************************************************
- *ROOT_CAP_CONTROL - root_cap_control
- ***************************************************************************/
-/* PCIE_0_RC_CFG_PCIE :: ROOT_CAP_CONTROL :: RESERVED1 [31:17] */
-#define BCHP_PCIE_0_RC_CFG_PCIE_ROOT_CAP_CONTROL_RESERVED1_MASK 0xfffe0000
-#define BCHP_PCIE_0_RC_CFG_PCIE_ROOT_CAP_CONTROL_RESERVED1_SHIFT 17
-
-/* PCIE_0_RC_CFG_PCIE :: ROOT_CAP_CONTROL :: RC_CRS_VISIBILITY [16:16] */
-#define BCHP_PCIE_0_RC_CFG_PCIE_ROOT_CAP_CONTROL_RC_CRS_VISIBILITY_MASK 0x00010000
-#define BCHP_PCIE_0_RC_CFG_PCIE_ROOT_CAP_CONTROL_RC_CRS_VISIBILITY_SHIFT 16
-#define BCHP_PCIE_0_RC_CFG_PCIE_ROOT_CAP_CONTROL_RC_CRS_VISIBILITY_DEFAULT 0x00000001
-
-/* PCIE_0_RC_CFG_PCIE :: ROOT_CAP_CONTROL :: RESERVED0 [15:05] */
-#define BCHP_PCIE_0_RC_CFG_PCIE_ROOT_CAP_CONTROL_RESERVED0_MASK 0x0000ffe0
-#define BCHP_PCIE_0_RC_CFG_PCIE_ROOT_CAP_CONTROL_RESERVED0_SHIFT 5
-
-/* PCIE_0_RC_CFG_PCIE :: ROOT_CAP_CONTROL :: RC_CRS_EN [04:04] */
-#define BCHP_PCIE_0_RC_CFG_PCIE_ROOT_CAP_CONTROL_RC_CRS_EN_MASK 0x00000010
-#define BCHP_PCIE_0_RC_CFG_PCIE_ROOT_CAP_CONTROL_RC_CRS_EN_SHIFT 4
-#define BCHP_PCIE_0_RC_CFG_PCIE_ROOT_CAP_CONTROL_RC_CRS_EN_DEFAULT 0x00000000
-
-/* PCIE_0_RC_CFG_PCIE :: ROOT_CAP_CONTROL :: RC_PME_INT_EN [03:03] */
-#define BCHP_PCIE_0_RC_CFG_PCIE_ROOT_CAP_CONTROL_RC_PME_INT_EN_MASK 0x00000008
-#define BCHP_PCIE_0_RC_CFG_PCIE_ROOT_CAP_CONTROL_RC_PME_INT_EN_SHIFT 3
-#define BCHP_PCIE_0_RC_CFG_PCIE_ROOT_CAP_CONTROL_RC_PME_INT_EN_DEFAULT 0x00000000
-
-/* PCIE_0_RC_CFG_PCIE :: ROOT_CAP_CONTROL :: RC_FATAL_SERR_EN [02:02] */
-#define BCHP_PCIE_0_RC_CFG_PCIE_ROOT_CAP_CONTROL_RC_FATAL_SERR_EN_MASK 0x00000004
-#define BCHP_PCIE_0_RC_CFG_PCIE_ROOT_CAP_CONTROL_RC_FATAL_SERR_EN_SHIFT 2
-#define BCHP_PCIE_0_RC_CFG_PCIE_ROOT_CAP_CONTROL_RC_FATAL_SERR_EN_DEFAULT 0x00000000
-
-/* PCIE_0_RC_CFG_PCIE :: ROOT_CAP_CONTROL :: RC_NONFATAL_SERR_EN [01:01] */
-#define BCHP_PCIE_0_RC_CFG_PCIE_ROOT_CAP_CONTROL_RC_NONFATAL_SERR_EN_MASK 0x00000002
-#define BCHP_PCIE_0_RC_CFG_PCIE_ROOT_CAP_CONTROL_RC_NONFATAL_SERR_EN_SHIFT 1
-#define BCHP_PCIE_0_RC_CFG_PCIE_ROOT_CAP_CONTROL_RC_NONFATAL_SERR_EN_DEFAULT 0x00000000
-
-/* PCIE_0_RC_CFG_PCIE :: ROOT_CAP_CONTROL :: RC_CORR_SERR_EN [00:00] */
-#define BCHP_PCIE_0_RC_CFG_PCIE_ROOT_CAP_CONTROL_RC_CORR_SERR_EN_MASK 0x00000001
-#define BCHP_PCIE_0_RC_CFG_PCIE_ROOT_CAP_CONTROL_RC_CORR_SERR_EN_SHIFT 0
-#define BCHP_PCIE_0_RC_CFG_PCIE_ROOT_CAP_CONTROL_RC_CORR_SERR_EN_DEFAULT 0x00000000
-
-/***************************************************************************
- *ROOT_STATUS - root_status
- ***************************************************************************/
-/* PCIE_0_RC_CFG_PCIE :: ROOT_STATUS :: RESERVED0 [31:18] */
-#define BCHP_PCIE_0_RC_CFG_PCIE_ROOT_STATUS_RESERVED0_MASK 0xfffc0000
-#define BCHP_PCIE_0_RC_CFG_PCIE_ROOT_STATUS_RESERVED0_SHIFT 18
-
-/* PCIE_0_RC_CFG_PCIE :: ROOT_STATUS :: RC_PME_PENDING [17:17] */
-#define BCHP_PCIE_0_RC_CFG_PCIE_ROOT_STATUS_RC_PME_PENDING_MASK 0x00020000
-#define BCHP_PCIE_0_RC_CFG_PCIE_ROOT_STATUS_RC_PME_PENDING_SHIFT 17
-#define BCHP_PCIE_0_RC_CFG_PCIE_ROOT_STATUS_RC_PME_PENDING_DEFAULT 0x00000000
-
-/* PCIE_0_RC_CFG_PCIE :: ROOT_STATUS :: RC_PME_STATUS [16:16] */
-#define BCHP_PCIE_0_RC_CFG_PCIE_ROOT_STATUS_RC_PME_STATUS_MASK 0x00010000
-#define BCHP_PCIE_0_RC_CFG_PCIE_ROOT_STATUS_RC_PME_STATUS_SHIFT 16
-#define BCHP_PCIE_0_RC_CFG_PCIE_ROOT_STATUS_RC_PME_STATUS_DEFAULT 0x00000000
-
-/* PCIE_0_RC_CFG_PCIE :: ROOT_STATUS :: RC_PME_REQ_ID [15:00] */
-#define BCHP_PCIE_0_RC_CFG_PCIE_ROOT_STATUS_RC_PME_REQ_ID_MASK 0x0000ffff
-#define BCHP_PCIE_0_RC_CFG_PCIE_ROOT_STATUS_RC_PME_REQ_ID_SHIFT 0
-#define BCHP_PCIE_0_RC_CFG_PCIE_ROOT_STATUS_RC_PME_REQ_ID_DEFAULT 0x00000000
-
-/***************************************************************************
- *DEVICE_CAPABILITY_2 - device_capability_2
- ***************************************************************************/
-/* PCIE_0_RC_CFG_PCIE :: DEVICE_CAPABILITY_2 :: RESERVED0 [31:05] */
-#define BCHP_PCIE_0_RC_CFG_PCIE_DEVICE_CAPABILITY_2_RESERVED0_MASK 0xffffffe0
-#define BCHP_PCIE_0_RC_CFG_PCIE_DEVICE_CAPABILITY_2_RESERVED0_SHIFT 5
-
-/* PCIE_0_RC_CFG_PCIE :: DEVICE_CAPABILITY_2 :: CMPL_TIMEOUT_DISABL_SUPPORTED [04:04] */
-#define BCHP_PCIE_0_RC_CFG_PCIE_DEVICE_CAPABILITY_2_CMPL_TIMEOUT_DISABL_SUPPORTED_MASK 0x00000010
-#define BCHP_PCIE_0_RC_CFG_PCIE_DEVICE_CAPABILITY_2_CMPL_TIMEOUT_DISABL_SUPPORTED_SHIFT 4
-#define BCHP_PCIE_0_RC_CFG_PCIE_DEVICE_CAPABILITY_2_CMPL_TIMEOUT_DISABL_SUPPORTED_DEFAULT 0x00000001
-
-/* PCIE_0_RC_CFG_PCIE :: DEVICE_CAPABILITY_2 :: CMPL_TIMEOUT_RANGES_SUPPORTED [03:00] */
-#define BCHP_PCIE_0_RC_CFG_PCIE_DEVICE_CAPABILITY_2_CMPL_TIMEOUT_RANGES_SUPPORTED_MASK 0x0000000f
-#define BCHP_PCIE_0_RC_CFG_PCIE_DEVICE_CAPABILITY_2_CMPL_TIMEOUT_RANGES_SUPPORTED_SHIFT 0
-#define BCHP_PCIE_0_RC_CFG_PCIE_DEVICE_CAPABILITY_2_CMPL_TIMEOUT_RANGES_SUPPORTED_DEFAULT 0x0000000f
-
-/***************************************************************************
- *DEVICE_STATUS_CONTROL_2 - device_status_control_2
- ***************************************************************************/
-/* PCIE_0_RC_CFG_PCIE :: DEVICE_STATUS_CONTROL_2 :: DEVICE_STATUS_2 [31:16] */
-#define BCHP_PCIE_0_RC_CFG_PCIE_DEVICE_STATUS_CONTROL_2_DEVICE_STATUS_2_MASK 0xffff0000
-#define BCHP_PCIE_0_RC_CFG_PCIE_DEVICE_STATUS_CONTROL_2_DEVICE_STATUS_2_SHIFT 16
-#define BCHP_PCIE_0_RC_CFG_PCIE_DEVICE_STATUS_CONTROL_2_DEVICE_STATUS_2_DEFAULT 0x00000000
-
-/* PCIE_0_RC_CFG_PCIE :: DEVICE_STATUS_CONTROL_2 :: RESERVED0 [15:05] */
-#define BCHP_PCIE_0_RC_CFG_PCIE_DEVICE_STATUS_CONTROL_2_RESERVED0_MASK 0x0000ffe0
-#define BCHP_PCIE_0_RC_CFG_PCIE_DEVICE_STATUS_CONTROL_2_RESERVED0_SHIFT 5
-
-/* PCIE_0_RC_CFG_PCIE :: DEVICE_STATUS_CONTROL_2 :: CMPL_TIMEOUT_DISABLE [04:04] */
-#define BCHP_PCIE_0_RC_CFG_PCIE_DEVICE_STATUS_CONTROL_2_CMPL_TIMEOUT_DISABLE_MASK 0x00000010
-#define BCHP_PCIE_0_RC_CFG_PCIE_DEVICE_STATUS_CONTROL_2_CMPL_TIMEOUT_DISABLE_SHIFT 4
-#define BCHP_PCIE_0_RC_CFG_PCIE_DEVICE_STATUS_CONTROL_2_CMPL_TIMEOUT_DISABLE_DEFAULT 0x00000000
-
-/* PCIE_0_RC_CFG_PCIE :: DEVICE_STATUS_CONTROL_2 :: CMPL_TIMEOUT_VALUE [03:00] */
-#define BCHP_PCIE_0_RC_CFG_PCIE_DEVICE_STATUS_CONTROL_2_CMPL_TIMEOUT_VALUE_MASK 0x0000000f
-#define BCHP_PCIE_0_RC_CFG_PCIE_DEVICE_STATUS_CONTROL_2_CMPL_TIMEOUT_VALUE_SHIFT 0
-#define BCHP_PCIE_0_RC_CFG_PCIE_DEVICE_STATUS_CONTROL_2_CMPL_TIMEOUT_VALUE_DEFAULT 0x00000000
-
-/***************************************************************************
- *LINK_CAPABILITY_2 - link_capability_2
- ***************************************************************************/
-/* PCIE_0_RC_CFG_PCIE :: LINK_CAPABILITY_2 :: LINK_CAPABILITY_2 [31:00] */
-#define BCHP_PCIE_0_RC_CFG_PCIE_LINK_CAPABILITY_2_LINK_CAPABILITY_2_MASK 0xffffffff
-#define BCHP_PCIE_0_RC_CFG_PCIE_LINK_CAPABILITY_2_LINK_CAPABILITY_2_SHIFT 0
-#define BCHP_PCIE_0_RC_CFG_PCIE_LINK_CAPABILITY_2_LINK_CAPABILITY_2_DEFAULT 0x00000000
-
-/***************************************************************************
- *LINK_STATUS_CONTROL_2 - link_status_control_2
- ***************************************************************************/
-/* PCIE_0_RC_CFG_PCIE :: LINK_STATUS_CONTROL_2 :: LINK_STATUS_2 [31:17] */
-#define BCHP_PCIE_0_RC_CFG_PCIE_LINK_STATUS_CONTROL_2_LINK_STATUS_2_MASK 0xfffe0000
-#define BCHP_PCIE_0_RC_CFG_PCIE_LINK_STATUS_CONTROL_2_LINK_STATUS_2_SHIFT 17
-#define BCHP_PCIE_0_RC_CFG_PCIE_LINK_STATUS_CONTROL_2_LINK_STATUS_2_DEFAULT 0x00000000
-
-/* PCIE_0_RC_CFG_PCIE :: LINK_STATUS_CONTROL_2 :: CURR_DEEMPH_LEVEL [16:16] */
-#define BCHP_PCIE_0_RC_CFG_PCIE_LINK_STATUS_CONTROL_2_CURR_DEEMPH_LEVEL_MASK 0x00010000
-#define BCHP_PCIE_0_RC_CFG_PCIE_LINK_STATUS_CONTROL_2_CURR_DEEMPH_LEVEL_SHIFT 16
-#define BCHP_PCIE_0_RC_CFG_PCIE_LINK_STATUS_CONTROL_2_CURR_DEEMPH_LEVEL_DEFAULT 0x00000000
-
-/* PCIE_0_RC_CFG_PCIE :: LINK_STATUS_CONTROL_2 :: RESERVED0 [15:13] */
-#define BCHP_PCIE_0_RC_CFG_PCIE_LINK_STATUS_CONTROL_2_RESERVED0_MASK 0x0000e000
-#define BCHP_PCIE_0_RC_CFG_PCIE_LINK_STATUS_CONTROL_2_RESERVED0_SHIFT 13
-
-/* PCIE_0_RC_CFG_PCIE :: LINK_STATUS_CONTROL_2 :: CFG_COMPLIANCE_DEEMPH [12:12] */
-#define BCHP_PCIE_0_RC_CFG_PCIE_LINK_STATUS_CONTROL_2_CFG_COMPLIANCE_DEEMPH_MASK 0x00001000
-#define BCHP_PCIE_0_RC_CFG_PCIE_LINK_STATUS_CONTROL_2_CFG_COMPLIANCE_DEEMPH_SHIFT 12
-#define BCHP_PCIE_0_RC_CFG_PCIE_LINK_STATUS_CONTROL_2_CFG_COMPLIANCE_DEEMPH_DEFAULT 0x00000000
-
-/* PCIE_0_RC_CFG_PCIE :: LINK_STATUS_CONTROL_2 :: CFG_COMPLIANCE_SOS [11:11] */
-#define BCHP_PCIE_0_RC_CFG_PCIE_LINK_STATUS_CONTROL_2_CFG_COMPLIANCE_SOS_MASK 0x00000800
-#define BCHP_PCIE_0_RC_CFG_PCIE_LINK_STATUS_CONTROL_2_CFG_COMPLIANCE_SOS_SHIFT 11
-#define BCHP_PCIE_0_RC_CFG_PCIE_LINK_STATUS_CONTROL_2_CFG_COMPLIANCE_SOS_DEFAULT 0x00000000
-
-/* PCIE_0_RC_CFG_PCIE :: LINK_STATUS_CONTROL_2 :: CFG_ENTER_MOD_COMPLIANCE [10:10] */
-#define BCHP_PCIE_0_RC_CFG_PCIE_LINK_STATUS_CONTROL_2_CFG_ENTER_MOD_COMPLIANCE_MASK 0x00000400
-#define BCHP_PCIE_0_RC_CFG_PCIE_LINK_STATUS_CONTROL_2_CFG_ENTER_MOD_COMPLIANCE_SHIFT 10
-#define BCHP_PCIE_0_RC_CFG_PCIE_LINK_STATUS_CONTROL_2_CFG_ENTER_MOD_COMPLIANCE_DEFAULT 0x00000000
-
-/* PCIE_0_RC_CFG_PCIE :: LINK_STATUS_CONTROL_2 :: CFG_TX_MARGIN [09:07] */
-#define BCHP_PCIE_0_RC_CFG_PCIE_LINK_STATUS_CONTROL_2_CFG_TX_MARGIN_MASK 0x00000380
-#define BCHP_PCIE_0_RC_CFG_PCIE_LINK_STATUS_CONTROL_2_CFG_TX_MARGIN_SHIFT 7
-#define BCHP_PCIE_0_RC_CFG_PCIE_LINK_STATUS_CONTROL_2_CFG_TX_MARGIN_DEFAULT 0x00000000
-
-/* PCIE_0_RC_CFG_PCIE :: LINK_STATUS_CONTROL_2 :: SEL_DEEMPHASIS [06:06] */
-#define BCHP_PCIE_0_RC_CFG_PCIE_LINK_STATUS_CONTROL_2_SEL_DEEMPHASIS_MASK 0x00000040
-#define BCHP_PCIE_0_RC_CFG_PCIE_LINK_STATUS_CONTROL_2_SEL_DEEMPHASIS_SHIFT 6
-#define BCHP_PCIE_0_RC_CFG_PCIE_LINK_STATUS_CONTROL_2_SEL_DEEMPHASIS_DEFAULT 0x00000000
-
-/* PCIE_0_RC_CFG_PCIE :: LINK_STATUS_CONTROL_2 :: HW_AUTO_SPEED_DISABLE [05:05] */
-#define BCHP_PCIE_0_RC_CFG_PCIE_LINK_STATUS_CONTROL_2_HW_AUTO_SPEED_DISABLE_MASK 0x00000020
-#define BCHP_PCIE_0_RC_CFG_PCIE_LINK_STATUS_CONTROL_2_HW_AUTO_SPEED_DISABLE_SHIFT 5
-#define BCHP_PCIE_0_RC_CFG_PCIE_LINK_STATUS_CONTROL_2_HW_AUTO_SPEED_DISABLE_DEFAULT 0x00000000
-
-/* PCIE_0_RC_CFG_PCIE :: LINK_STATUS_CONTROL_2 :: ENTER_COMPLIANCE [04:04] */
-#define BCHP_PCIE_0_RC_CFG_PCIE_LINK_STATUS_CONTROL_2_ENTER_COMPLIANCE_MASK 0x00000010
-#define BCHP_PCIE_0_RC_CFG_PCIE_LINK_STATUS_CONTROL_2_ENTER_COMPLIANCE_SHIFT 4
-#define BCHP_PCIE_0_RC_CFG_PCIE_LINK_STATUS_CONTROL_2_ENTER_COMPLIANCE_DEFAULT 0x00000000
-
-/* PCIE_0_RC_CFG_PCIE :: LINK_STATUS_CONTROL_2 :: TARGET_LINK_SPEED [03:00] */
-#define BCHP_PCIE_0_RC_CFG_PCIE_LINK_STATUS_CONTROL_2_TARGET_LINK_SPEED_MASK 0x0000000f
-#define BCHP_PCIE_0_RC_CFG_PCIE_LINK_STATUS_CONTROL_2_TARGET_LINK_SPEED_SHIFT 0
-#define BCHP_PCIE_0_RC_CFG_PCIE_LINK_STATUS_CONTROL_2_TARGET_LINK_SPEED_DEFAULT 0x00000001
-
-/***************************************************************************
- *SLOT_CAPABILITY_2 - slot_capability_2
- ***************************************************************************/
-/* PCIE_0_RC_CFG_PCIE :: SLOT_CAPABILITY_2 :: SLOT_CAPABILITY_2 [31:00] */
-#define BCHP_PCIE_0_RC_CFG_PCIE_SLOT_CAPABILITY_2_SLOT_CAPABILITY_2_MASK 0xffffffff
-#define BCHP_PCIE_0_RC_CFG_PCIE_SLOT_CAPABILITY_2_SLOT_CAPABILITY_2_SHIFT 0
-#define BCHP_PCIE_0_RC_CFG_PCIE_SLOT_CAPABILITY_2_SLOT_CAPABILITY_2_DEFAULT 0x00000000
-
-/***************************************************************************
- *SLOT_STATUS_CONTROL_2 - slot_status_control_2
- ***************************************************************************/
-/* PCIE_0_RC_CFG_PCIE :: SLOT_STATUS_CONTROL_2 :: SLOT_STATUS_2 [31:16] */
-#define BCHP_PCIE_0_RC_CFG_PCIE_SLOT_STATUS_CONTROL_2_SLOT_STATUS_2_MASK 0xffff0000
-#define BCHP_PCIE_0_RC_CFG_PCIE_SLOT_STATUS_CONTROL_2_SLOT_STATUS_2_SHIFT 16
-#define BCHP_PCIE_0_RC_CFG_PCIE_SLOT_STATUS_CONTROL_2_SLOT_STATUS_2_DEFAULT 0x00000000
-
-/* PCIE_0_RC_CFG_PCIE :: SLOT_STATUS_CONTROL_2 :: SLOT_CONTROL_2 [15:00] */
-#define BCHP_PCIE_0_RC_CFG_PCIE_SLOT_STATUS_CONTROL_2_SLOT_CONTROL_2_MASK 0x0000ffff
-#define BCHP_PCIE_0_RC_CFG_PCIE_SLOT_STATUS_CONTROL_2_SLOT_CONTROL_2_SHIFT 0
-#define BCHP_PCIE_0_RC_CFG_PCIE_SLOT_STATUS_CONTROL_2_SLOT_CONTROL_2_DEFAULT 0x00000000
-
-#endif /* #ifndef BCHP_PCIE_0_RC_CFG_PCIE_H__ */
-
-/* End of File */
diff --git a/include/linux/brcmstb/7439a0/bchp_pcie_0_rc_cfg_type1.h b/include/linux/brcmstb/7439a0/bchp_pcie_0_rc_cfg_type1.h
deleted file mode 100644
index af7c2de..0000000
--- a/include/linux/brcmstb/7439a0/bchp_pcie_0_rc_cfg_type1.h
+++ /dev/null
@@ -1,526 +0,0 @@
-/***************************************************************************
- * Copyright (c) 1999-2013, Broadcom Corporation
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
- *
- * Module Description:
- * DO NOT EDIT THIS FILE DIRECTLY
- *
- * This module was generated magically with RDB from a source description
- * file. You must edit the source file for changes to be made to this file.
- *
- *
- * Date: Generated on Tue Apr 16 03:26:51 2013
- * MD5 Checksum d41d8cd98f00b204e9800998ecf8427e
- *
- * Compiled with: RDB Utility combo_header.pl
- * RDB Parser 3.0
- * unknown unknown
- * Perl Interpreter 5.008008
- * Operating System linux
- *
- * Revision History:
- *
- * $brcm_Log: $
- *
- ***************************************************************************/
-
-#ifndef BCHP_PCIE_0_RC_CFG_TYPE1_H__
-#define BCHP_PCIE_0_RC_CFG_TYPE1_H__
-
-/***************************************************************************
- *PCIE_0_RC_CFG_TYPE1
- ***************************************************************************/
-#define BCHP_PCIE_0_RC_CFG_TYPE1_DEVICE_VENDOR_ID 0x00470000 /* device_vendor_id */
-#define BCHP_PCIE_0_RC_CFG_TYPE1_STATUS_COMMAND 0x00470004 /* status_command */
-#define BCHP_PCIE_0_RC_CFG_TYPE1_REV_ID_CLASS_CODE 0x00470008 /* rev_id_class_code */
-#define BCHP_PCIE_0_RC_CFG_TYPE1_HEADERTYPE_LAT_CACHELINESIZE 0x0047000c /* headertype_lat_cachelinesize */
-#define BCHP_PCIE_0_RC_CFG_TYPE1_BAR_1 0x00470010 /* bar_1 */
-#define BCHP_PCIE_0_RC_CFG_TYPE1_BAR_2 0x00470014 /* bar_2 */
-#define BCHP_PCIE_0_RC_CFG_TYPE1_PRI_SEC_BUS_NO 0x00470018 /* pri_sec_bus_no */
-#define BCHP_PCIE_0_RC_CFG_TYPE1_SEC_STATUS_IO_BASE_LIMIT 0x0047001c /* sec_status_io_base_limit */
-#define BCHP_PCIE_0_RC_CFG_TYPE1_RC_MEM_BASE_LIMIT 0x00470020 /* rc_mem_base_limit */
-#define BCHP_PCIE_0_RC_CFG_TYPE1_RC_PREF_BASE_LIMIT 0x00470024 /* rc_pref_base_limit */
-#define BCHP_PCIE_0_RC_CFG_TYPE1_RC_PREF_BASE_HI 0x00470028 /* rc_pref_base_hi */
-#define BCHP_PCIE_0_RC_CFG_TYPE1_RC_PREF_LIM_HI 0x0047002c /* rc_pref_lim_hi */
-#define BCHP_PCIE_0_RC_CFG_TYPE1_RC_IO_BASE_LIMIT 0x00470030 /* rc_io_base_limit */
-#define BCHP_PCIE_0_RC_CFG_TYPE1_CAP_POINTER 0x00470034 /* cap_pointer */
-#define BCHP_PCIE_0_RC_CFG_TYPE1_EXP_ROM_BAR 0x00470038 /* exp_rom_bar */
-#define BCHP_PCIE_0_RC_CFG_TYPE1_BRIDGE_CONTROL 0x0047003c /* bridge_control */
-
-/***************************************************************************
- *DEVICE_VENDOR_ID - device_vendor_id
- ***************************************************************************/
-/* PCIE_0_RC_CFG_TYPE1 :: DEVICE_VENDOR_ID :: DEVICE_ID [31:16] */
-#define BCHP_PCIE_0_RC_CFG_TYPE1_DEVICE_VENDOR_ID_DEVICE_ID_MASK 0xffff0000
-#define BCHP_PCIE_0_RC_CFG_TYPE1_DEVICE_VENDOR_ID_DEVICE_ID_SHIFT 16
-
-/* PCIE_0_RC_CFG_TYPE1 :: DEVICE_VENDOR_ID :: VENDOR_ID [15:00] */
-#define BCHP_PCIE_0_RC_CFG_TYPE1_DEVICE_VENDOR_ID_VENDOR_ID_MASK 0x0000ffff
-#define BCHP_PCIE_0_RC_CFG_TYPE1_DEVICE_VENDOR_ID_VENDOR_ID_SHIFT 0
-#define BCHP_PCIE_0_RC_CFG_TYPE1_DEVICE_VENDOR_ID_VENDOR_ID_DEFAULT 0x000014e4
-
-/***************************************************************************
- *STATUS_COMMAND - status_command
- ***************************************************************************/
-/* PCIE_0_RC_CFG_TYPE1 :: STATUS_COMMAND :: PAR_ERR [31:31] */
-#define BCHP_PCIE_0_RC_CFG_TYPE1_STATUS_COMMAND_PAR_ERR_MASK 0x80000000
-#define BCHP_PCIE_0_RC_CFG_TYPE1_STATUS_COMMAND_PAR_ERR_SHIFT 31
-#define BCHP_PCIE_0_RC_CFG_TYPE1_STATUS_COMMAND_PAR_ERR_DEFAULT 0x00000000
-
-/* PCIE_0_RC_CFG_TYPE1 :: STATUS_COMMAND :: SIG_SERR [30:30] */
-#define BCHP_PCIE_0_RC_CFG_TYPE1_STATUS_COMMAND_SIG_SERR_MASK 0x40000000
-#define BCHP_PCIE_0_RC_CFG_TYPE1_STATUS_COMMAND_SIG_SERR_SHIFT 30
-#define BCHP_PCIE_0_RC_CFG_TYPE1_STATUS_COMMAND_SIG_SERR_DEFAULT 0x00000000
-
-/* PCIE_0_RC_CFG_TYPE1 :: STATUS_COMMAND :: RCV_MSTR_ABT [29:29] */
-#define BCHP_PCIE_0_RC_CFG_TYPE1_STATUS_COMMAND_RCV_MSTR_ABT_MASK 0x20000000
-#define BCHP_PCIE_0_RC_CFG_TYPE1_STATUS_COMMAND_RCV_MSTR_ABT_SHIFT 29
-#define BCHP_PCIE_0_RC_CFG_TYPE1_STATUS_COMMAND_RCV_MSTR_ABT_DEFAULT 0x00000000
-
-/* PCIE_0_RC_CFG_TYPE1 :: STATUS_COMMAND :: RCV_TGT_ABT [28:28] */
-#define BCHP_PCIE_0_RC_CFG_TYPE1_STATUS_COMMAND_RCV_TGT_ABT_MASK 0x10000000
-#define BCHP_PCIE_0_RC_CFG_TYPE1_STATUS_COMMAND_RCV_TGT_ABT_SHIFT 28
-#define BCHP_PCIE_0_RC_CFG_TYPE1_STATUS_COMMAND_RCV_TGT_ABT_DEFAULT 0x00000000
-
-/* PCIE_0_RC_CFG_TYPE1 :: STATUS_COMMAND :: SIG_TGT_ABT [27:27] */
-#define BCHP_PCIE_0_RC_CFG_TYPE1_STATUS_COMMAND_SIG_TGT_ABT_MASK 0x08000000
-#define BCHP_PCIE_0_RC_CFG_TYPE1_STATUS_COMMAND_SIG_TGT_ABT_SHIFT 27
-#define BCHP_PCIE_0_RC_CFG_TYPE1_STATUS_COMMAND_SIG_TGT_ABT_DEFAULT 0x00000000
-
-/* PCIE_0_RC_CFG_TYPE1 :: STATUS_COMMAND :: DEVSEL_TIMING [26:25] */
-#define BCHP_PCIE_0_RC_CFG_TYPE1_STATUS_COMMAND_DEVSEL_TIMING_MASK 0x06000000
-#define BCHP_PCIE_0_RC_CFG_TYPE1_STATUS_COMMAND_DEVSEL_TIMING_SHIFT 25
-#define BCHP_PCIE_0_RC_CFG_TYPE1_STATUS_COMMAND_DEVSEL_TIMING_DEFAULT 0x00000000
-
-/* PCIE_0_RC_CFG_TYPE1 :: STATUS_COMMAND :: MSTR_PERR [24:24] */
-#define BCHP_PCIE_0_RC_CFG_TYPE1_STATUS_COMMAND_MSTR_PERR_MASK 0x01000000
-#define BCHP_PCIE_0_RC_CFG_TYPE1_STATUS_COMMAND_MSTR_PERR_SHIFT 24
-#define BCHP_PCIE_0_RC_CFG_TYPE1_STATUS_COMMAND_MSTR_PERR_DEFAULT 0x00000000
-
-/* PCIE_0_RC_CFG_TYPE1 :: STATUS_COMMAND :: FAST_B2B_CAP [23:23] */
-#define BCHP_PCIE_0_RC_CFG_TYPE1_STATUS_COMMAND_FAST_B2B_CAP_MASK 0x00800000
-#define BCHP_PCIE_0_RC_CFG_TYPE1_STATUS_COMMAND_FAST_B2B_CAP_SHIFT 23
-#define BCHP_PCIE_0_RC_CFG_TYPE1_STATUS_COMMAND_FAST_B2B_CAP_DEFAULT 0x00000000
-
-/* PCIE_0_RC_CFG_TYPE1 :: STATUS_COMMAND :: RESERVED1 [22:22] */
-#define BCHP_PCIE_0_RC_CFG_TYPE1_STATUS_COMMAND_RESERVED1_MASK 0x00400000
-#define BCHP_PCIE_0_RC_CFG_TYPE1_STATUS_COMMAND_RESERVED1_SHIFT 22
-#define BCHP_PCIE_0_RC_CFG_TYPE1_STATUS_COMMAND_RESERVED1_DEFAULT 0x00000000
-
-/* PCIE_0_RC_CFG_TYPE1 :: STATUS_COMMAND :: CAP_66MHZ [21:21] */
-#define BCHP_PCIE_0_RC_CFG_TYPE1_STATUS_COMMAND_CAP_66MHZ_MASK 0x00200000
-#define BCHP_PCIE_0_RC_CFG_TYPE1_STATUS_COMMAND_CAP_66MHZ_SHIFT 21
-#define BCHP_PCIE_0_RC_CFG_TYPE1_STATUS_COMMAND_CAP_66MHZ_DEFAULT 0x00000000
-
-/* PCIE_0_RC_CFG_TYPE1 :: STATUS_COMMAND :: CAP_LIST [20:20] */
-#define BCHP_PCIE_0_RC_CFG_TYPE1_STATUS_COMMAND_CAP_LIST_MASK 0x00100000
-#define BCHP_PCIE_0_RC_CFG_TYPE1_STATUS_COMMAND_CAP_LIST_SHIFT 20
-#define BCHP_PCIE_0_RC_CFG_TYPE1_STATUS_COMMAND_CAP_LIST_DEFAULT 0x00000001
-
-/* PCIE_0_RC_CFG_TYPE1 :: STATUS_COMMAND :: INT_STATUS [19:19] */
-#define BCHP_PCIE_0_RC_CFG_TYPE1_STATUS_COMMAND_INT_STATUS_MASK 0x00080000
-#define BCHP_PCIE_0_RC_CFG_TYPE1_STATUS_COMMAND_INT_STATUS_SHIFT 19
-#define BCHP_PCIE_0_RC_CFG_TYPE1_STATUS_COMMAND_INT_STATUS_DEFAULT 0x00000000
-
-/* PCIE_0_RC_CFG_TYPE1 :: STATUS_COMMAND :: RESERVED2 [18:16] */
-#define BCHP_PCIE_0_RC_CFG_TYPE1_STATUS_COMMAND_RESERVED2_MASK 0x00070000
-#define BCHP_PCIE_0_RC_CFG_TYPE1_STATUS_COMMAND_RESERVED2_SHIFT 16
-#define BCHP_PCIE_0_RC_CFG_TYPE1_STATUS_COMMAND_RESERVED2_DEFAULT 0x00000000
-
-/* PCIE_0_RC_CFG_TYPE1 :: STATUS_COMMAND :: RESERVED [15:11] */
-#define BCHP_PCIE_0_RC_CFG_TYPE1_STATUS_COMMAND_RESERVED_MASK 0x0000f800
-#define BCHP_PCIE_0_RC_CFG_TYPE1_STATUS_COMMAND_RESERVED_SHIFT 11
-#define BCHP_PCIE_0_RC_CFG_TYPE1_STATUS_COMMAND_RESERVED_DEFAULT 0x00000000
-
-/* PCIE_0_RC_CFG_TYPE1 :: STATUS_COMMAND :: INT_DISABLE [10:10] */
-#define BCHP_PCIE_0_RC_CFG_TYPE1_STATUS_COMMAND_INT_DISABLE_MASK 0x00000400
-#define BCHP_PCIE_0_RC_CFG_TYPE1_STATUS_COMMAND_INT_DISABLE_SHIFT 10
-#define BCHP_PCIE_0_RC_CFG_TYPE1_STATUS_COMMAND_INT_DISABLE_DEFAULT 0x00000000
-
-/* PCIE_0_RC_CFG_TYPE1 :: STATUS_COMMAND :: FAST_B2B [09:09] */
-#define BCHP_PCIE_0_RC_CFG_TYPE1_STATUS_COMMAND_FAST_B2B_MASK 0x00000200
-#define BCHP_PCIE_0_RC_CFG_TYPE1_STATUS_COMMAND_FAST_B2B_SHIFT 9
-#define BCHP_PCIE_0_RC_CFG_TYPE1_STATUS_COMMAND_FAST_B2B_DEFAULT 0x00000000
-
-/* PCIE_0_RC_CFG_TYPE1 :: STATUS_COMMAND :: SERR_ENA [08:08] */
-#define BCHP_PCIE_0_RC_CFG_TYPE1_STATUS_COMMAND_SERR_ENA_MASK 0x00000100
-#define BCHP_PCIE_0_RC_CFG_TYPE1_STATUS_COMMAND_SERR_ENA_SHIFT 8
-#define BCHP_PCIE_0_RC_CFG_TYPE1_STATUS_COMMAND_SERR_ENA_DEFAULT 0x00000000
-
-/* PCIE_0_RC_CFG_TYPE1 :: STATUS_COMMAND :: STEPPING [07:07] */
-#define BCHP_PCIE_0_RC_CFG_TYPE1_STATUS_COMMAND_STEPPING_MASK 0x00000080
-#define BCHP_PCIE_0_RC_CFG_TYPE1_STATUS_COMMAND_STEPPING_SHIFT 7
-#define BCHP_PCIE_0_RC_CFG_TYPE1_STATUS_COMMAND_STEPPING_DEFAULT 0x00000000
-
-/* PCIE_0_RC_CFG_TYPE1 :: STATUS_COMMAND :: PERR_ENA [06:06] */
-#define BCHP_PCIE_0_RC_CFG_TYPE1_STATUS_COMMAND_PERR_ENA_MASK 0x00000040
-#define BCHP_PCIE_0_RC_CFG_TYPE1_STATUS_COMMAND_PERR_ENA_SHIFT 6
-#define BCHP_PCIE_0_RC_CFG_TYPE1_STATUS_COMMAND_PERR_ENA_DEFAULT 0x00000000
-
-/* PCIE_0_RC_CFG_TYPE1 :: STATUS_COMMAND :: VGA_SNOOP [05:05] */
-#define BCHP_PCIE_0_RC_CFG_TYPE1_STATUS_COMMAND_VGA_SNOOP_MASK 0x00000020
-#define BCHP_PCIE_0_RC_CFG_TYPE1_STATUS_COMMAND_VGA_SNOOP_SHIFT 5
-#define BCHP_PCIE_0_RC_CFG_TYPE1_STATUS_COMMAND_VGA_SNOOP_DEFAULT 0x00000000
-
-/* PCIE_0_RC_CFG_TYPE1 :: STATUS_COMMAND :: MWI_CYCLES [04:04] */
-#define BCHP_PCIE_0_RC_CFG_TYPE1_STATUS_COMMAND_MWI_CYCLES_MASK 0x00000010
-#define BCHP_PCIE_0_RC_CFG_TYPE1_STATUS_COMMAND_MWI_CYCLES_SHIFT 4
-#define BCHP_PCIE_0_RC_CFG_TYPE1_STATUS_COMMAND_MWI_CYCLES_DEFAULT 0x00000000
-
-/* PCIE_0_RC_CFG_TYPE1 :: STATUS_COMMAND :: SPECIAL_CYCLES [03:03] */
-#define BCHP_PCIE_0_RC_CFG_TYPE1_STATUS_COMMAND_SPECIAL_CYCLES_MASK 0x00000008
-#define BCHP_PCIE_0_RC_CFG_TYPE1_STATUS_COMMAND_SPECIAL_CYCLES_SHIFT 3
-#define BCHP_PCIE_0_RC_CFG_TYPE1_STATUS_COMMAND_SPECIAL_CYCLES_DEFAULT 0x00000000
-
-/* PCIE_0_RC_CFG_TYPE1 :: STATUS_COMMAND :: BUS_MASTER [02:02] */
-#define BCHP_PCIE_0_RC_CFG_TYPE1_STATUS_COMMAND_BUS_MASTER_MASK 0x00000004
-#define BCHP_PCIE_0_RC_CFG_TYPE1_STATUS_COMMAND_BUS_MASTER_SHIFT 2
-#define BCHP_PCIE_0_RC_CFG_TYPE1_STATUS_COMMAND_BUS_MASTER_DEFAULT 0x00000000
-
-/* PCIE_0_RC_CFG_TYPE1 :: STATUS_COMMAND :: MEM_SPACE [01:01] */
-#define BCHP_PCIE_0_RC_CFG_TYPE1_STATUS_COMMAND_MEM_SPACE_MASK 0x00000002
-#define BCHP_PCIE_0_RC_CFG_TYPE1_STATUS_COMMAND_MEM_SPACE_SHIFT 1
-#define BCHP_PCIE_0_RC_CFG_TYPE1_STATUS_COMMAND_MEM_SPACE_DEFAULT 0x00000000
-
-/* PCIE_0_RC_CFG_TYPE1 :: STATUS_COMMAND :: IO_SPACE [00:00] */
-#define BCHP_PCIE_0_RC_CFG_TYPE1_STATUS_COMMAND_IO_SPACE_MASK 0x00000001
-#define BCHP_PCIE_0_RC_CFG_TYPE1_STATUS_COMMAND_IO_SPACE_SHIFT 0
-#define BCHP_PCIE_0_RC_CFG_TYPE1_STATUS_COMMAND_IO_SPACE_DEFAULT 0x00000000
-
-/***************************************************************************
- *REV_ID_CLASS_CODE - rev_id_class_code
- ***************************************************************************/
-/* PCIE_0_RC_CFG_TYPE1 :: REV_ID_CLASS_CODE :: CLASS_CODE [31:08] */
-#define BCHP_PCIE_0_RC_CFG_TYPE1_REV_ID_CLASS_CODE_CLASS_CODE_MASK 0xffffff00
-#define BCHP_PCIE_0_RC_CFG_TYPE1_REV_ID_CLASS_CODE_CLASS_CODE_SHIFT 8
-#define BCHP_PCIE_0_RC_CFG_TYPE1_REV_ID_CLASS_CODE_CLASS_CODE_DEFAULT 0x00020000
-
-/* PCIE_0_RC_CFG_TYPE1 :: REV_ID_CLASS_CODE :: REV_ID [07:00] */
-#define BCHP_PCIE_0_RC_CFG_TYPE1_REV_ID_CLASS_CODE_REV_ID_MASK 0x000000ff
-#define BCHP_PCIE_0_RC_CFG_TYPE1_REV_ID_CLASS_CODE_REV_ID_SHIFT 0
-
-/***************************************************************************
- *HEADERTYPE_LAT_CACHELINESIZE - headertype_lat_cachelinesize
- ***************************************************************************/
-/* PCIE_0_RC_CFG_TYPE1 :: HEADERTYPE_LAT_CACHELINESIZE :: BIST [31:24] */
-#define BCHP_PCIE_0_RC_CFG_TYPE1_HEADERTYPE_LAT_CACHELINESIZE_BIST_MASK 0xff000000
-#define BCHP_PCIE_0_RC_CFG_TYPE1_HEADERTYPE_LAT_CACHELINESIZE_BIST_SHIFT 24
-#define BCHP_PCIE_0_RC_CFG_TYPE1_HEADERTYPE_LAT_CACHELINESIZE_BIST_DEFAULT 0x00000000
-
-/* PCIE_0_RC_CFG_TYPE1 :: HEADERTYPE_LAT_CACHELINESIZE :: HEADER_TYPE [23:16] */
-#define BCHP_PCIE_0_RC_CFG_TYPE1_HEADERTYPE_LAT_CACHELINESIZE_HEADER_TYPE_MASK 0x00ff0000
-#define BCHP_PCIE_0_RC_CFG_TYPE1_HEADERTYPE_LAT_CACHELINESIZE_HEADER_TYPE_SHIFT 16
-#define BCHP_PCIE_0_RC_CFG_TYPE1_HEADERTYPE_LAT_CACHELINESIZE_HEADER_TYPE_DEFAULT 0x00000001
-
-/* PCIE_0_RC_CFG_TYPE1 :: HEADERTYPE_LAT_CACHELINESIZE :: LATENCY_TIMER [15:08] */
-#define BCHP_PCIE_0_RC_CFG_TYPE1_HEADERTYPE_LAT_CACHELINESIZE_LATENCY_TIMER_MASK 0x0000ff00
-#define BCHP_PCIE_0_RC_CFG_TYPE1_HEADERTYPE_LAT_CACHELINESIZE_LATENCY_TIMER_SHIFT 8
-#define BCHP_PCIE_0_RC_CFG_TYPE1_HEADERTYPE_LAT_CACHELINESIZE_LATENCY_TIMER_DEFAULT 0x00000000
-
-/* PCIE_0_RC_CFG_TYPE1 :: HEADERTYPE_LAT_CACHELINESIZE :: CACHE_LINE_SIZE [07:00] */
-#define BCHP_PCIE_0_RC_CFG_TYPE1_HEADERTYPE_LAT_CACHELINESIZE_CACHE_LINE_SIZE_MASK 0x000000ff
-#define BCHP_PCIE_0_RC_CFG_TYPE1_HEADERTYPE_LAT_CACHELINESIZE_CACHE_LINE_SIZE_SHIFT 0
-#define BCHP_PCIE_0_RC_CFG_TYPE1_HEADERTYPE_LAT_CACHELINESIZE_CACHE_LINE_SIZE_DEFAULT 0x00000000
-
-/***************************************************************************
- *BAR_1 - bar_1
- ***************************************************************************/
-/* PCIE_0_RC_CFG_TYPE1 :: BAR_1 :: ADDRESS [31:04] */
-#define BCHP_PCIE_0_RC_CFG_TYPE1_BAR_1_ADDRESS_MASK 0xfffffff0
-#define BCHP_PCIE_0_RC_CFG_TYPE1_BAR_1_ADDRESS_SHIFT 4
-#define BCHP_PCIE_0_RC_CFG_TYPE1_BAR_1_ADDRESS_DEFAULT 0x00000000
-
-/* PCIE_0_RC_CFG_TYPE1 :: BAR_1 :: PREFETCH [03:03] */
-#define BCHP_PCIE_0_RC_CFG_TYPE1_BAR_1_PREFETCH_MASK 0x00000008
-#define BCHP_PCIE_0_RC_CFG_TYPE1_BAR_1_PREFETCH_SHIFT 3
-#define BCHP_PCIE_0_RC_CFG_TYPE1_BAR_1_PREFETCH_DEFAULT 0x00000001
-
-/* PCIE_0_RC_CFG_TYPE1 :: BAR_1 :: SPACE_TYPE [02:01] */
-#define BCHP_PCIE_0_RC_CFG_TYPE1_BAR_1_SPACE_TYPE_MASK 0x00000006
-#define BCHP_PCIE_0_RC_CFG_TYPE1_BAR_1_SPACE_TYPE_SHIFT 1
-#define BCHP_PCIE_0_RC_CFG_TYPE1_BAR_1_SPACE_TYPE_DEFAULT 0x00000002
-
-/* PCIE_0_RC_CFG_TYPE1 :: BAR_1 :: MEM_SPACE [00:00] */
-#define BCHP_PCIE_0_RC_CFG_TYPE1_BAR_1_MEM_SPACE_MASK 0x00000001
-#define BCHP_PCIE_0_RC_CFG_TYPE1_BAR_1_MEM_SPACE_SHIFT 0
-#define BCHP_PCIE_0_RC_CFG_TYPE1_BAR_1_MEM_SPACE_DEFAULT 0x00000000
-
-/***************************************************************************
- *BAR_2 - bar_2
- ***************************************************************************/
-/* PCIE_0_RC_CFG_TYPE1 :: BAR_2 :: ADDR [31:00] */
-#define BCHP_PCIE_0_RC_CFG_TYPE1_BAR_2_ADDR_MASK 0xffffffff
-#define BCHP_PCIE_0_RC_CFG_TYPE1_BAR_2_ADDR_SHIFT 0
-#define BCHP_PCIE_0_RC_CFG_TYPE1_BAR_2_ADDR_DEFAULT 0x00000000
-
-/***************************************************************************
- *PRI_SEC_BUS_NO - pri_sec_bus_no
- ***************************************************************************/
-/* PCIE_0_RC_CFG_TYPE1 :: PRI_SEC_BUS_NO :: SEC_LATENCY_TIMER [31:24] */
-#define BCHP_PCIE_0_RC_CFG_TYPE1_PRI_SEC_BUS_NO_SEC_LATENCY_TIMER_MASK 0xff000000
-#define BCHP_PCIE_0_RC_CFG_TYPE1_PRI_SEC_BUS_NO_SEC_LATENCY_TIMER_SHIFT 24
-#define BCHP_PCIE_0_RC_CFG_TYPE1_PRI_SEC_BUS_NO_SEC_LATENCY_TIMER_DEFAULT 0x00000000
-
-/* PCIE_0_RC_CFG_TYPE1 :: PRI_SEC_BUS_NO :: SUB_BUS_NO [23:16] */
-#define BCHP_PCIE_0_RC_CFG_TYPE1_PRI_SEC_BUS_NO_SUB_BUS_NO_MASK 0x00ff0000
-#define BCHP_PCIE_0_RC_CFG_TYPE1_PRI_SEC_BUS_NO_SUB_BUS_NO_SHIFT 16
-#define BCHP_PCIE_0_RC_CFG_TYPE1_PRI_SEC_BUS_NO_SUB_BUS_NO_DEFAULT 0x00000000
-
-/* PCIE_0_RC_CFG_TYPE1 :: PRI_SEC_BUS_NO :: SEC_BUS_NO [15:08] */
-#define BCHP_PCIE_0_RC_CFG_TYPE1_PRI_SEC_BUS_NO_SEC_BUS_NO_MASK 0x0000ff00
-#define BCHP_PCIE_0_RC_CFG_TYPE1_PRI_SEC_BUS_NO_SEC_BUS_NO_SHIFT 8
-#define BCHP_PCIE_0_RC_CFG_TYPE1_PRI_SEC_BUS_NO_SEC_BUS_NO_DEFAULT 0x00000000
-
-/* PCIE_0_RC_CFG_TYPE1 :: PRI_SEC_BUS_NO :: PRI_BUS_NO [07:00] */
-#define BCHP_PCIE_0_RC_CFG_TYPE1_PRI_SEC_BUS_NO_PRI_BUS_NO_MASK 0x000000ff
-#define BCHP_PCIE_0_RC_CFG_TYPE1_PRI_SEC_BUS_NO_PRI_BUS_NO_SHIFT 0
-#define BCHP_PCIE_0_RC_CFG_TYPE1_PRI_SEC_BUS_NO_PRI_BUS_NO_DEFAULT 0x00000000
-
-/***************************************************************************
- *SEC_STATUS_IO_BASE_LIMIT - sec_status_io_base_limit
- ***************************************************************************/
-/* PCIE_0_RC_CFG_TYPE1 :: SEC_STATUS_IO_BASE_LIMIT :: SEC_DETECTED_PARITY_ERROR [31:31] */
-#define BCHP_PCIE_0_RC_CFG_TYPE1_SEC_STATUS_IO_BASE_LIMIT_SEC_DETECTED_PARITY_ERROR_MASK 0x80000000
-#define BCHP_PCIE_0_RC_CFG_TYPE1_SEC_STATUS_IO_BASE_LIMIT_SEC_DETECTED_PARITY_ERROR_SHIFT 31
-#define BCHP_PCIE_0_RC_CFG_TYPE1_SEC_STATUS_IO_BASE_LIMIT_SEC_DETECTED_PARITY_ERROR_DEFAULT 0x00000000
-
-/* PCIE_0_RC_CFG_TYPE1 :: SEC_STATUS_IO_BASE_LIMIT :: SEC_RECEIVED_SYSTEM_ERROR [30:30] */
-#define BCHP_PCIE_0_RC_CFG_TYPE1_SEC_STATUS_IO_BASE_LIMIT_SEC_RECEIVED_SYSTEM_ERROR_MASK 0x40000000
-#define BCHP_PCIE_0_RC_CFG_TYPE1_SEC_STATUS_IO_BASE_LIMIT_SEC_RECEIVED_SYSTEM_ERROR_SHIFT 30
-#define BCHP_PCIE_0_RC_CFG_TYPE1_SEC_STATUS_IO_BASE_LIMIT_SEC_RECEIVED_SYSTEM_ERROR_DEFAULT 0x00000000
-
-/* PCIE_0_RC_CFG_TYPE1 :: SEC_STATUS_IO_BASE_LIMIT :: SEC_RECEIVED_MASTER_ABORT [29:29] */
-#define BCHP_PCIE_0_RC_CFG_TYPE1_SEC_STATUS_IO_BASE_LIMIT_SEC_RECEIVED_MASTER_ABORT_MASK 0x20000000
-#define BCHP_PCIE_0_RC_CFG_TYPE1_SEC_STATUS_IO_BASE_LIMIT_SEC_RECEIVED_MASTER_ABORT_SHIFT 29
-#define BCHP_PCIE_0_RC_CFG_TYPE1_SEC_STATUS_IO_BASE_LIMIT_SEC_RECEIVED_MASTER_ABORT_DEFAULT 0x00000000
-
-/* PCIE_0_RC_CFG_TYPE1 :: SEC_STATUS_IO_BASE_LIMIT :: SEC_RECEIVED_TARGET_ABORT [28:28] */
-#define BCHP_PCIE_0_RC_CFG_TYPE1_SEC_STATUS_IO_BASE_LIMIT_SEC_RECEIVED_TARGET_ABORT_MASK 0x10000000
-#define BCHP_PCIE_0_RC_CFG_TYPE1_SEC_STATUS_IO_BASE_LIMIT_SEC_RECEIVED_TARGET_ABORT_SHIFT 28
-#define BCHP_PCIE_0_RC_CFG_TYPE1_SEC_STATUS_IO_BASE_LIMIT_SEC_RECEIVED_TARGET_ABORT_DEFAULT 0x00000000
-
-/* PCIE_0_RC_CFG_TYPE1 :: SEC_STATUS_IO_BASE_LIMIT :: SEC_SIGNALED_TARGET_ABORT [27:27] */
-#define BCHP_PCIE_0_RC_CFG_TYPE1_SEC_STATUS_IO_BASE_LIMIT_SEC_SIGNALED_TARGET_ABORT_MASK 0x08000000
-#define BCHP_PCIE_0_RC_CFG_TYPE1_SEC_STATUS_IO_BASE_LIMIT_SEC_SIGNALED_TARGET_ABORT_SHIFT 27
-#define BCHP_PCIE_0_RC_CFG_TYPE1_SEC_STATUS_IO_BASE_LIMIT_SEC_SIGNALED_TARGET_ABORT_DEFAULT 0x00000000
-
-/* PCIE_0_RC_CFG_TYPE1 :: SEC_STATUS_IO_BASE_LIMIT :: DEVICE_TIMING [26:25] */
-#define BCHP_PCIE_0_RC_CFG_TYPE1_SEC_STATUS_IO_BASE_LIMIT_DEVICE_TIMING_MASK 0x06000000
-#define BCHP_PCIE_0_RC_CFG_TYPE1_SEC_STATUS_IO_BASE_LIMIT_DEVICE_TIMING_SHIFT 25
-#define BCHP_PCIE_0_RC_CFG_TYPE1_SEC_STATUS_IO_BASE_LIMIT_DEVICE_TIMING_DEFAULT 0x00000000
-
-/* PCIE_0_RC_CFG_TYPE1 :: SEC_STATUS_IO_BASE_LIMIT :: SEC_MASTER_DATA_PARITY_ERROR [24:24] */
-#define BCHP_PCIE_0_RC_CFG_TYPE1_SEC_STATUS_IO_BASE_LIMIT_SEC_MASTER_DATA_PARITY_ERROR_MASK 0x01000000
-#define BCHP_PCIE_0_RC_CFG_TYPE1_SEC_STATUS_IO_BASE_LIMIT_SEC_MASTER_DATA_PARITY_ERROR_SHIFT 24
-#define BCHP_PCIE_0_RC_CFG_TYPE1_SEC_STATUS_IO_BASE_LIMIT_SEC_MASTER_DATA_PARITY_ERROR_DEFAULT 0x00000000
-
-/* PCIE_0_RC_CFG_TYPE1 :: SEC_STATUS_IO_BASE_LIMIT :: FAST_B2B [23:23] */
-#define BCHP_PCIE_0_RC_CFG_TYPE1_SEC_STATUS_IO_BASE_LIMIT_FAST_B2B_MASK 0x00800000
-#define BCHP_PCIE_0_RC_CFG_TYPE1_SEC_STATUS_IO_BASE_LIMIT_FAST_B2B_SHIFT 23
-#define BCHP_PCIE_0_RC_CFG_TYPE1_SEC_STATUS_IO_BASE_LIMIT_FAST_B2B_DEFAULT 0x00000000
-
-/* PCIE_0_RC_CFG_TYPE1 :: SEC_STATUS_IO_BASE_LIMIT :: RESERVED3 [22:22] */
-#define BCHP_PCIE_0_RC_CFG_TYPE1_SEC_STATUS_IO_BASE_LIMIT_RESERVED3_MASK 0x00400000
-#define BCHP_PCIE_0_RC_CFG_TYPE1_SEC_STATUS_IO_BASE_LIMIT_RESERVED3_SHIFT 22
-#define BCHP_PCIE_0_RC_CFG_TYPE1_SEC_STATUS_IO_BASE_LIMIT_RESERVED3_DEFAULT 0x00000000
-
-/* PCIE_0_RC_CFG_TYPE1 :: SEC_STATUS_IO_BASE_LIMIT :: CAP_66_MHZ [21:21] */
-#define BCHP_PCIE_0_RC_CFG_TYPE1_SEC_STATUS_IO_BASE_LIMIT_CAP_66_MHZ_MASK 0x00200000
-#define BCHP_PCIE_0_RC_CFG_TYPE1_SEC_STATUS_IO_BASE_LIMIT_CAP_66_MHZ_SHIFT 21
-#define BCHP_PCIE_0_RC_CFG_TYPE1_SEC_STATUS_IO_BASE_LIMIT_CAP_66_MHZ_DEFAULT 0x00000000
-
-/* PCIE_0_RC_CFG_TYPE1 :: SEC_STATUS_IO_BASE_LIMIT :: RESERVED4 [20:16] */
-#define BCHP_PCIE_0_RC_CFG_TYPE1_SEC_STATUS_IO_BASE_LIMIT_RESERVED4_MASK 0x001f0000
-#define BCHP_PCIE_0_RC_CFG_TYPE1_SEC_STATUS_IO_BASE_LIMIT_RESERVED4_SHIFT 16
-#define BCHP_PCIE_0_RC_CFG_TYPE1_SEC_STATUS_IO_BASE_LIMIT_RESERVED4_DEFAULT 0x00000000
-
-/* PCIE_0_RC_CFG_TYPE1 :: SEC_STATUS_IO_BASE_LIMIT :: IO_LIMIT [15:08] */
-#define BCHP_PCIE_0_RC_CFG_TYPE1_SEC_STATUS_IO_BASE_LIMIT_IO_LIMIT_MASK 0x0000ff00
-#define BCHP_PCIE_0_RC_CFG_TYPE1_SEC_STATUS_IO_BASE_LIMIT_IO_LIMIT_SHIFT 8
-#define BCHP_PCIE_0_RC_CFG_TYPE1_SEC_STATUS_IO_BASE_LIMIT_IO_LIMIT_DEFAULT 0x00000000
-
-/* PCIE_0_RC_CFG_TYPE1 :: SEC_STATUS_IO_BASE_LIMIT :: IO_BASE [07:00] */
-#define BCHP_PCIE_0_RC_CFG_TYPE1_SEC_STATUS_IO_BASE_LIMIT_IO_BASE_MASK 0x000000ff
-#define BCHP_PCIE_0_RC_CFG_TYPE1_SEC_STATUS_IO_BASE_LIMIT_IO_BASE_SHIFT 0
-#define BCHP_PCIE_0_RC_CFG_TYPE1_SEC_STATUS_IO_BASE_LIMIT_IO_BASE_DEFAULT 0x00000000
-
-/***************************************************************************
- *RC_MEM_BASE_LIMIT - rc_mem_base_limit
- ***************************************************************************/
-/* PCIE_0_RC_CFG_TYPE1 :: RC_MEM_BASE_LIMIT :: RC_MEM_LIMIT [31:20] */
-#define BCHP_PCIE_0_RC_CFG_TYPE1_RC_MEM_BASE_LIMIT_RC_MEM_LIMIT_MASK 0xfff00000
-#define BCHP_PCIE_0_RC_CFG_TYPE1_RC_MEM_BASE_LIMIT_RC_MEM_LIMIT_SHIFT 20
-#define BCHP_PCIE_0_RC_CFG_TYPE1_RC_MEM_BASE_LIMIT_RC_MEM_LIMIT_DEFAULT 0x00000000
-
-/* PCIE_0_RC_CFG_TYPE1 :: RC_MEM_BASE_LIMIT :: RC_MEM_LIMIT_3TO0 [19:16] */
-#define BCHP_PCIE_0_RC_CFG_TYPE1_RC_MEM_BASE_LIMIT_RC_MEM_LIMIT_3TO0_MASK 0x000f0000
-#define BCHP_PCIE_0_RC_CFG_TYPE1_RC_MEM_BASE_LIMIT_RC_MEM_LIMIT_3TO0_SHIFT 16
-#define BCHP_PCIE_0_RC_CFG_TYPE1_RC_MEM_BASE_LIMIT_RC_MEM_LIMIT_3TO0_DEFAULT 0x00000000
-
-/* PCIE_0_RC_CFG_TYPE1 :: RC_MEM_BASE_LIMIT :: RC_MEM_BASE [15:04] */
-#define BCHP_PCIE_0_RC_CFG_TYPE1_RC_MEM_BASE_LIMIT_RC_MEM_BASE_MASK 0x0000fff0
-#define BCHP_PCIE_0_RC_CFG_TYPE1_RC_MEM_BASE_LIMIT_RC_MEM_BASE_SHIFT 4
-#define BCHP_PCIE_0_RC_CFG_TYPE1_RC_MEM_BASE_LIMIT_RC_MEM_BASE_DEFAULT 0x00000000
-
-/* PCIE_0_RC_CFG_TYPE1 :: RC_MEM_BASE_LIMIT :: RC_MEM_BASE_3TO0 [03:00] */
-#define BCHP_PCIE_0_RC_CFG_TYPE1_RC_MEM_BASE_LIMIT_RC_MEM_BASE_3TO0_MASK 0x0000000f
-#define BCHP_PCIE_0_RC_CFG_TYPE1_RC_MEM_BASE_LIMIT_RC_MEM_BASE_3TO0_SHIFT 0
-#define BCHP_PCIE_0_RC_CFG_TYPE1_RC_MEM_BASE_LIMIT_RC_MEM_BASE_3TO0_DEFAULT 0x00000000
-
-/***************************************************************************
- *RC_PREF_BASE_LIMIT - rc_pref_base_limit
- ***************************************************************************/
-/* PCIE_0_RC_CFG_TYPE1 :: RC_PREF_BASE_LIMIT :: RC_PREF_LIM [31:20] */
-#define BCHP_PCIE_0_RC_CFG_TYPE1_RC_PREF_BASE_LIMIT_RC_PREF_LIM_MASK 0xfff00000
-#define BCHP_PCIE_0_RC_CFG_TYPE1_RC_PREF_BASE_LIMIT_RC_PREF_LIM_SHIFT 20
-#define BCHP_PCIE_0_RC_CFG_TYPE1_RC_PREF_BASE_LIMIT_RC_PREF_LIM_DEFAULT 0x00000000
-
-/* PCIE_0_RC_CFG_TYPE1 :: RC_PREF_BASE_LIMIT :: RC_PREF_LIMIT_3TO0 [19:16] */
-#define BCHP_PCIE_0_RC_CFG_TYPE1_RC_PREF_BASE_LIMIT_RC_PREF_LIMIT_3TO0_MASK 0x000f0000
-#define BCHP_PCIE_0_RC_CFG_TYPE1_RC_PREF_BASE_LIMIT_RC_PREF_LIMIT_3TO0_SHIFT 16
-#define BCHP_PCIE_0_RC_CFG_TYPE1_RC_PREF_BASE_LIMIT_RC_PREF_LIMIT_3TO0_DEFAULT 0x00000001
-
-/* PCIE_0_RC_CFG_TYPE1 :: RC_PREF_BASE_LIMIT :: RC_PREF_BASE [15:04] */
-#define BCHP_PCIE_0_RC_CFG_TYPE1_RC_PREF_BASE_LIMIT_RC_PREF_BASE_MASK 0x0000fff0
-#define BCHP_PCIE_0_RC_CFG_TYPE1_RC_PREF_BASE_LIMIT_RC_PREF_BASE_SHIFT 4
-#define BCHP_PCIE_0_RC_CFG_TYPE1_RC_PREF_BASE_LIMIT_RC_PREF_BASE_DEFAULT 0x00000000
-
-/* PCIE_0_RC_CFG_TYPE1 :: RC_PREF_BASE_LIMIT :: RC_PREF_BASE_3TO0 [03:00] */
-#define BCHP_PCIE_0_RC_CFG_TYPE1_RC_PREF_BASE_LIMIT_RC_PREF_BASE_3TO0_MASK 0x0000000f
-#define BCHP_PCIE_0_RC_CFG_TYPE1_RC_PREF_BASE_LIMIT_RC_PREF_BASE_3TO0_SHIFT 0
-#define BCHP_PCIE_0_RC_CFG_TYPE1_RC_PREF_BASE_LIMIT_RC_PREF_BASE_3TO0_DEFAULT 0x00000001
-
-/***************************************************************************
- *RC_PREF_BASE_HI - rc_pref_base_hi
- ***************************************************************************/
-/* PCIE_0_RC_CFG_TYPE1 :: RC_PREF_BASE_HI :: RC_PREF_BASE_HI [31:00] */
-#define BCHP_PCIE_0_RC_CFG_TYPE1_RC_PREF_BASE_HI_RC_PREF_BASE_HI_MASK 0xffffffff
-#define BCHP_PCIE_0_RC_CFG_TYPE1_RC_PREF_BASE_HI_RC_PREF_BASE_HI_SHIFT 0
-#define BCHP_PCIE_0_RC_CFG_TYPE1_RC_PREF_BASE_HI_RC_PREF_BASE_HI_DEFAULT 0x00000000
-
-/***************************************************************************
- *RC_PREF_LIM_HI - rc_pref_lim_hi
- ***************************************************************************/
-/* PCIE_0_RC_CFG_TYPE1 :: RC_PREF_LIM_HI :: RC_PREF_BASE_HI [31:00] */
-#define BCHP_PCIE_0_RC_CFG_TYPE1_RC_PREF_LIM_HI_RC_PREF_BASE_HI_MASK 0xffffffff
-#define BCHP_PCIE_0_RC_CFG_TYPE1_RC_PREF_LIM_HI_RC_PREF_BASE_HI_SHIFT 0
-#define BCHP_PCIE_0_RC_CFG_TYPE1_RC_PREF_LIM_HI_RC_PREF_BASE_HI_DEFAULT 0x00000000
-
-/***************************************************************************
- *RC_IO_BASE_LIMIT - rc_io_base_limit
- ***************************************************************************/
-/* PCIE_0_RC_CFG_TYPE1 :: RC_IO_BASE_LIMIT :: RC_IO_LIM_HI [31:16] */
-#define BCHP_PCIE_0_RC_CFG_TYPE1_RC_IO_BASE_LIMIT_RC_IO_LIM_HI_MASK 0xffff0000
-#define BCHP_PCIE_0_RC_CFG_TYPE1_RC_IO_BASE_LIMIT_RC_IO_LIM_HI_SHIFT 16
-#define BCHP_PCIE_0_RC_CFG_TYPE1_RC_IO_BASE_LIMIT_RC_IO_LIM_HI_DEFAULT 0x00000000
-
-/* PCIE_0_RC_CFG_TYPE1 :: RC_IO_BASE_LIMIT :: RC_IO_BASE_HI [15:00] */
-#define BCHP_PCIE_0_RC_CFG_TYPE1_RC_IO_BASE_LIMIT_RC_IO_BASE_HI_MASK 0x0000ffff
-#define BCHP_PCIE_0_RC_CFG_TYPE1_RC_IO_BASE_LIMIT_RC_IO_BASE_HI_SHIFT 0
-#define BCHP_PCIE_0_RC_CFG_TYPE1_RC_IO_BASE_LIMIT_RC_IO_BASE_HI_DEFAULT 0x00000000
-
-/***************************************************************************
- *CAP_POINTER - cap_pointer
- ***************************************************************************/
-/* PCIE_0_RC_CFG_TYPE1 :: CAP_POINTER :: RESERVED0 [31:08] */
-#define BCHP_PCIE_0_RC_CFG_TYPE1_CAP_POINTER_RESERVED0_MASK 0xffffff00
-#define BCHP_PCIE_0_RC_CFG_TYPE1_CAP_POINTER_RESERVED0_SHIFT 8
-
-/* PCIE_0_RC_CFG_TYPE1 :: CAP_POINTER :: CAP_POINTER [07:00] */
-#define BCHP_PCIE_0_RC_CFG_TYPE1_CAP_POINTER_CAP_POINTER_MASK 0x000000ff
-#define BCHP_PCIE_0_RC_CFG_TYPE1_CAP_POINTER_CAP_POINTER_SHIFT 0
-#define BCHP_PCIE_0_RC_CFG_TYPE1_CAP_POINTER_CAP_POINTER_DEFAULT 0x00000048
-
-/***************************************************************************
- *EXP_ROM_BAR - exp_rom_bar
- ***************************************************************************/
-/* PCIE_0_RC_CFG_TYPE1 :: EXP_ROM_BAR :: RESERVED0 [31:08] */
-#define BCHP_PCIE_0_RC_CFG_TYPE1_EXP_ROM_BAR_RESERVED0_MASK 0xffffff00
-#define BCHP_PCIE_0_RC_CFG_TYPE1_EXP_ROM_BAR_RESERVED0_SHIFT 8
-
-/* PCIE_0_RC_CFG_TYPE1 :: EXP_ROM_BAR :: EXP_ROM_BAR [07:00] */
-#define BCHP_PCIE_0_RC_CFG_TYPE1_EXP_ROM_BAR_EXP_ROM_BAR_MASK 0x000000ff
-#define BCHP_PCIE_0_RC_CFG_TYPE1_EXP_ROM_BAR_EXP_ROM_BAR_SHIFT 0
-#define BCHP_PCIE_0_RC_CFG_TYPE1_EXP_ROM_BAR_EXP_ROM_BAR_DEFAULT 0x00000000
-
-/***************************************************************************
- *BRIDGE_CONTROL - bridge_control
- ***************************************************************************/
-/* PCIE_0_RC_CFG_TYPE1 :: BRIDGE_CONTROL :: RESERVED1 [31:28] */
-#define BCHP_PCIE_0_RC_CFG_TYPE1_BRIDGE_CONTROL_RESERVED1_MASK 0xf0000000
-#define BCHP_PCIE_0_RC_CFG_TYPE1_BRIDGE_CONTROL_RESERVED1_SHIFT 28
-
-/* PCIE_0_RC_CFG_TYPE1 :: BRIDGE_CONTROL :: DISCARD_TIMER_SERR_EN [27:27] */
-#define BCHP_PCIE_0_RC_CFG_TYPE1_BRIDGE_CONTROL_DISCARD_TIMER_SERR_EN_MASK 0x08000000
-#define BCHP_PCIE_0_RC_CFG_TYPE1_BRIDGE_CONTROL_DISCARD_TIMER_SERR_EN_SHIFT 27
-#define BCHP_PCIE_0_RC_CFG_TYPE1_BRIDGE_CONTROL_DISCARD_TIMER_SERR_EN_DEFAULT 0x00000000
-
-/* PCIE_0_RC_CFG_TYPE1 :: BRIDGE_CONTROL :: DISCARD_TIMER_STATUS [26:26] */
-#define BCHP_PCIE_0_RC_CFG_TYPE1_BRIDGE_CONTROL_DISCARD_TIMER_STATUS_MASK 0x04000000
-#define BCHP_PCIE_0_RC_CFG_TYPE1_BRIDGE_CONTROL_DISCARD_TIMER_STATUS_SHIFT 26
-#define BCHP_PCIE_0_RC_CFG_TYPE1_BRIDGE_CONTROL_DISCARD_TIMER_STATUS_DEFAULT 0x00000000
-
-/* PCIE_0_RC_CFG_TYPE1 :: BRIDGE_CONTROL :: SEC_DISCARD_TIMER [25:25] */
-#define BCHP_PCIE_0_RC_CFG_TYPE1_BRIDGE_CONTROL_SEC_DISCARD_TIMER_MASK 0x02000000
-#define BCHP_PCIE_0_RC_CFG_TYPE1_BRIDGE_CONTROL_SEC_DISCARD_TIMER_SHIFT 25
-#define BCHP_PCIE_0_RC_CFG_TYPE1_BRIDGE_CONTROL_SEC_DISCARD_TIMER_DEFAULT 0x00000000
-
-/* PCIE_0_RC_CFG_TYPE1 :: BRIDGE_CONTROL :: PRIM_DISCARD_TIMER [24:24] */
-#define BCHP_PCIE_0_RC_CFG_TYPE1_BRIDGE_CONTROL_PRIM_DISCARD_TIMER_MASK 0x01000000
-#define BCHP_PCIE_0_RC_CFG_TYPE1_BRIDGE_CONTROL_PRIM_DISCARD_TIMER_SHIFT 24
-#define BCHP_PCIE_0_RC_CFG_TYPE1_BRIDGE_CONTROL_PRIM_DISCARD_TIMER_DEFAULT 0x00000000
-
-/* PCIE_0_RC_CFG_TYPE1 :: BRIDGE_CONTROL :: FAST_B2B_EN [23:23] */
-#define BCHP_PCIE_0_RC_CFG_TYPE1_BRIDGE_CONTROL_FAST_B2B_EN_MASK 0x00800000
-#define BCHP_PCIE_0_RC_CFG_TYPE1_BRIDGE_CONTROL_FAST_B2B_EN_SHIFT 23
-#define BCHP_PCIE_0_RC_CFG_TYPE1_BRIDGE_CONTROL_FAST_B2B_EN_DEFAULT 0x00000000
-
-/* PCIE_0_RC_CFG_TYPE1 :: BRIDGE_CONTROL :: SEC_BUS_RESET [22:22] */
-#define BCHP_PCIE_0_RC_CFG_TYPE1_BRIDGE_CONTROL_SEC_BUS_RESET_MASK 0x00400000
-#define BCHP_PCIE_0_RC_CFG_TYPE1_BRIDGE_CONTROL_SEC_BUS_RESET_SHIFT 22
-#define BCHP_PCIE_0_RC_CFG_TYPE1_BRIDGE_CONTROL_SEC_BUS_RESET_DEFAULT 0x00000000
-
-/* PCIE_0_RC_CFG_TYPE1 :: BRIDGE_CONTROL :: MASTER_ABORT_MODE [21:21] */
-#define BCHP_PCIE_0_RC_CFG_TYPE1_BRIDGE_CONTROL_MASTER_ABORT_MODE_MASK 0x00200000
-#define BCHP_PCIE_0_RC_CFG_TYPE1_BRIDGE_CONTROL_MASTER_ABORT_MODE_SHIFT 21
-#define BCHP_PCIE_0_RC_CFG_TYPE1_BRIDGE_CONTROL_MASTER_ABORT_MODE_DEFAULT 0x00000000
-
-/* PCIE_0_RC_CFG_TYPE1 :: BRIDGE_CONTROL :: RESERVED0 [20:18] */
-#define BCHP_PCIE_0_RC_CFG_TYPE1_BRIDGE_CONTROL_RESERVED0_MASK 0x001c0000
-#define BCHP_PCIE_0_RC_CFG_TYPE1_BRIDGE_CONTROL_RESERVED0_SHIFT 18
-
-/* PCIE_0_RC_CFG_TYPE1 :: BRIDGE_CONTROL :: SEC_SERR_EN [17:17] */
-#define BCHP_PCIE_0_RC_CFG_TYPE1_BRIDGE_CONTROL_SEC_SERR_EN_MASK 0x00020000
-#define BCHP_PCIE_0_RC_CFG_TYPE1_BRIDGE_CONTROL_SEC_SERR_EN_SHIFT 17
-#define BCHP_PCIE_0_RC_CFG_TYPE1_BRIDGE_CONTROL_SEC_SERR_EN_DEFAULT 0x00000000
-
-/* PCIE_0_RC_CFG_TYPE1 :: BRIDGE_CONTROL :: SEC_PERR_RESP_EN [16:16] */
-#define BCHP_PCIE_0_RC_CFG_TYPE1_BRIDGE_CONTROL_SEC_PERR_RESP_EN_MASK 0x00010000
-#define BCHP_PCIE_0_RC_CFG_TYPE1_BRIDGE_CONTROL_SEC_PERR_RESP_EN_SHIFT 16
-#define BCHP_PCIE_0_RC_CFG_TYPE1_BRIDGE_CONTROL_SEC_PERR_RESP_EN_DEFAULT 0x00000000
-
-/* PCIE_0_RC_CFG_TYPE1 :: BRIDGE_CONTROL :: INT_PIN [15:08] */
-#define BCHP_PCIE_0_RC_CFG_TYPE1_BRIDGE_CONTROL_INT_PIN_MASK 0x0000ff00
-#define BCHP_PCIE_0_RC_CFG_TYPE1_BRIDGE_CONTROL_INT_PIN_SHIFT 8
-#define BCHP_PCIE_0_RC_CFG_TYPE1_BRIDGE_CONTROL_INT_PIN_DEFAULT 0x00000001
-
-/* PCIE_0_RC_CFG_TYPE1 :: BRIDGE_CONTROL :: INT_LINE [07:00] */
-#define BCHP_PCIE_0_RC_CFG_TYPE1_BRIDGE_CONTROL_INT_LINE_MASK 0x000000ff
-#define BCHP_PCIE_0_RC_CFG_TYPE1_BRIDGE_CONTROL_INT_LINE_SHIFT 0
-#define BCHP_PCIE_0_RC_CFG_TYPE1_BRIDGE_CONTROL_INT_LINE_DEFAULT 0x00000000
-
-#endif /* #ifndef BCHP_PCIE_0_RC_CFG_TYPE1_H__ */
-
-/* End of File */
diff --git a/include/linux/brcmstb/7439a0/bchp_pcie_0_rc_cfg_vendor.h b/include/linux/brcmstb/7439a0/bchp_pcie_0_rc_cfg_vendor.h
deleted file mode 100644
index 18986db..0000000
--- a/include/linux/brcmstb/7439a0/bchp_pcie_0_rc_cfg_vendor.h
+++ /dev/null
@@ -1,173 +0,0 @@
-/***************************************************************************
- * Copyright (c) 1999-2013, Broadcom Corporation
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
- *
- * Module Description:
- * DO NOT EDIT THIS FILE DIRECTLY
- *
- * This module was generated magically with RDB from a source description
- * file. You must edit the source file for changes to be made to this file.
- *
- *
- * Date: Generated on Tue Apr 16 03:26:50 2013
- * MD5 Checksum d41d8cd98f00b204e9800998ecf8427e
- *
- * Compiled with: RDB Utility combo_header.pl
- * RDB Parser 3.0
- * unknown unknown
- * Perl Interpreter 5.008008
- * Operating System linux
- *
- * Revision History:
- *
- * $brcm_Log: $
- *
- ***************************************************************************/
-
-#ifndef BCHP_PCIE_0_RC_CFG_VENDOR_H__
-#define BCHP_PCIE_0_RC_CFG_VENDOR_H__
-
-/***************************************************************************
- *PCIE_0_RC_CFG_VENDOR
- ***************************************************************************/
-#define BCHP_PCIE_0_RC_CFG_VENDOR_VENDOR_CAP 0x00470180 /* vendor_cap */
-#define BCHP_PCIE_0_RC_CFG_VENDOR_VENDOR_SPECIFIC_HEADER 0x00470184 /* vendor_specific_header */
-#define BCHP_PCIE_0_RC_CFG_VENDOR_VENDOR_SPECIFIC_REG1 0x00470188 /* Vendor Specific User Register 1 */
-#define BCHP_PCIE_0_RC_CFG_VENDOR_VENDOR_SPECIFIC_REG2 0x0047018c /* Vendor Specific User Register 2 */
-#define BCHP_PCIE_0_RC_CFG_VENDOR_VENDOR_SPECIFIC_REG3 0x00470190 /* Vendor Specific User Register 3 */
-#define BCHP_PCIE_0_RC_CFG_VENDOR_VENDOR_SPECIFIC_REG4 0x00470194 /* Vendor Specific User Register 4 */
-#define BCHP_PCIE_0_RC_CFG_VENDOR_VENDOR_SPECIFIC_REG5 0x00470198 /* Vendor Specific User Register 5 */
-#define BCHP_PCIE_0_RC_CFG_VENDOR_VENDOR_SPECIFIC_REG6 0x0047019c /* Vendor Specific User Register 6 */
-#define BCHP_PCIE_0_RC_CFG_VENDOR_VENDOR_SPECIFIC_REG7 0x004701a0 /* Vendor Specific User Register 7 */
-#define BCHP_PCIE_0_RC_CFG_VENDOR_VENDOR_SPECIFIC_REG8 0x004701a4 /* Vendor Specific User Register 8 */
-
-/***************************************************************************
- *VENDOR_CAP - vendor_cap
- ***************************************************************************/
-/* PCIE_0_RC_CFG_VENDOR :: VENDOR_CAP :: NEXT [31:20] */
-#define BCHP_PCIE_0_RC_CFG_VENDOR_VENDOR_CAP_NEXT_MASK 0xfff00000
-#define BCHP_PCIE_0_RC_CFG_VENDOR_VENDOR_CAP_NEXT_SHIFT 20
-#define BCHP_PCIE_0_RC_CFG_VENDOR_VENDOR_CAP_NEXT_DEFAULT 0x00000000
-
-/* PCIE_0_RC_CFG_VENDOR :: VENDOR_CAP :: CAP_VER [19:16] */
-#define BCHP_PCIE_0_RC_CFG_VENDOR_VENDOR_CAP_CAP_VER_MASK 0x000f0000
-#define BCHP_PCIE_0_RC_CFG_VENDOR_VENDOR_CAP_CAP_VER_SHIFT 16
-#define BCHP_PCIE_0_RC_CFG_VENDOR_VENDOR_CAP_CAP_VER_DEFAULT 0x00000001
-
-/* PCIE_0_RC_CFG_VENDOR :: VENDOR_CAP :: VENDOR_SPEC_CAP_ID [15:00] */
-#define BCHP_PCIE_0_RC_CFG_VENDOR_VENDOR_CAP_VENDOR_SPEC_CAP_ID_MASK 0x0000ffff
-#define BCHP_PCIE_0_RC_CFG_VENDOR_VENDOR_CAP_VENDOR_SPEC_CAP_ID_SHIFT 0
-#define BCHP_PCIE_0_RC_CFG_VENDOR_VENDOR_CAP_VENDOR_SPEC_CAP_ID_DEFAULT 0x0000000b
-
-/***************************************************************************
- *VENDOR_SPECIFIC_HEADER - vendor_specific_header
- ***************************************************************************/
-/* PCIE_0_RC_CFG_VENDOR :: VENDOR_SPECIFIC_HEADER :: VSEC_LENGTH [31:20] */
-#define BCHP_PCIE_0_RC_CFG_VENDOR_VENDOR_SPECIFIC_HEADER_VSEC_LENGTH_MASK 0xfff00000
-#define BCHP_PCIE_0_RC_CFG_VENDOR_VENDOR_SPECIFIC_HEADER_VSEC_LENGTH_SHIFT 20
-#define BCHP_PCIE_0_RC_CFG_VENDOR_VENDOR_SPECIFIC_HEADER_VSEC_LENGTH_DEFAULT 0x00000028
-
-/* PCIE_0_RC_CFG_VENDOR :: VENDOR_SPECIFIC_HEADER :: VSEC_REV [19:16] */
-#define BCHP_PCIE_0_RC_CFG_VENDOR_VENDOR_SPECIFIC_HEADER_VSEC_REV_MASK 0x000f0000
-#define BCHP_PCIE_0_RC_CFG_VENDOR_VENDOR_SPECIFIC_HEADER_VSEC_REV_SHIFT 16
-#define BCHP_PCIE_0_RC_CFG_VENDOR_VENDOR_SPECIFIC_HEADER_VSEC_REV_DEFAULT 0x00000000
-
-/* PCIE_0_RC_CFG_VENDOR :: VENDOR_SPECIFIC_HEADER :: VSEC_ID [15:00] */
-#define BCHP_PCIE_0_RC_CFG_VENDOR_VENDOR_SPECIFIC_HEADER_VSEC_ID_MASK 0x0000ffff
-#define BCHP_PCIE_0_RC_CFG_VENDOR_VENDOR_SPECIFIC_HEADER_VSEC_ID_SHIFT 0
-#define BCHP_PCIE_0_RC_CFG_VENDOR_VENDOR_SPECIFIC_HEADER_VSEC_ID_DEFAULT 0x00000000
-
-/***************************************************************************
- *VENDOR_SPECIFIC_REG1 - Vendor Specific User Register 1
- ***************************************************************************/
-/* PCIE_0_RC_CFG_VENDOR :: VENDOR_SPECIFIC_REG1 :: Undefined [31:06] */
-#define BCHP_PCIE_0_RC_CFG_VENDOR_VENDOR_SPECIFIC_REG1_Undefined_MASK 0xffffffc0
-#define BCHP_PCIE_0_RC_CFG_VENDOR_VENDOR_SPECIFIC_REG1_Undefined_SHIFT 6
-#define BCHP_PCIE_0_RC_CFG_VENDOR_VENDOR_SPECIFIC_REG1_Undefined_DEFAULT 0x00000000
-
-/* PCIE_0_RC_CFG_VENDOR :: VENDOR_SPECIFIC_REG1 :: ENDIAN_MODE_BAR3 [05:04] */
-#define BCHP_PCIE_0_RC_CFG_VENDOR_VENDOR_SPECIFIC_REG1_ENDIAN_MODE_BAR3_MASK 0x00000030
-#define BCHP_PCIE_0_RC_CFG_VENDOR_VENDOR_SPECIFIC_REG1_ENDIAN_MODE_BAR3_SHIFT 4
-#define BCHP_PCIE_0_RC_CFG_VENDOR_VENDOR_SPECIFIC_REG1_ENDIAN_MODE_BAR3_DEFAULT 0x00000000
-
-/* PCIE_0_RC_CFG_VENDOR :: VENDOR_SPECIFIC_REG1 :: ENDIAN_MODE_BAR2 [03:02] */
-#define BCHP_PCIE_0_RC_CFG_VENDOR_VENDOR_SPECIFIC_REG1_ENDIAN_MODE_BAR2_MASK 0x0000000c
-#define BCHP_PCIE_0_RC_CFG_VENDOR_VENDOR_SPECIFIC_REG1_ENDIAN_MODE_BAR2_SHIFT 2
-#define BCHP_PCIE_0_RC_CFG_VENDOR_VENDOR_SPECIFIC_REG1_ENDIAN_MODE_BAR2_DEFAULT 0x00000000
-
-/* PCIE_0_RC_CFG_VENDOR :: VENDOR_SPECIFIC_REG1 :: ENDIAN_MODE_BAR1 [01:00] */
-#define BCHP_PCIE_0_RC_CFG_VENDOR_VENDOR_SPECIFIC_REG1_ENDIAN_MODE_BAR1_MASK 0x00000003
-#define BCHP_PCIE_0_RC_CFG_VENDOR_VENDOR_SPECIFIC_REG1_ENDIAN_MODE_BAR1_SHIFT 0
-#define BCHP_PCIE_0_RC_CFG_VENDOR_VENDOR_SPECIFIC_REG1_ENDIAN_MODE_BAR1_DEFAULT 0x00000000
-
-/***************************************************************************
- *VENDOR_SPECIFIC_REG2 - Vendor Specific User Register 2
- ***************************************************************************/
-/* PCIE_0_RC_CFG_VENDOR :: VENDOR_SPECIFIC_REG2 :: Undefined [31:00] */
-#define BCHP_PCIE_0_RC_CFG_VENDOR_VENDOR_SPECIFIC_REG2_Undefined_MASK 0xffffffff
-#define BCHP_PCIE_0_RC_CFG_VENDOR_VENDOR_SPECIFIC_REG2_Undefined_SHIFT 0
-#define BCHP_PCIE_0_RC_CFG_VENDOR_VENDOR_SPECIFIC_REG2_Undefined_DEFAULT 0x00000000
-
-/***************************************************************************
- *VENDOR_SPECIFIC_REG3 - Vendor Specific User Register 3
- ***************************************************************************/
-/* PCIE_0_RC_CFG_VENDOR :: VENDOR_SPECIFIC_REG3 :: Undefined [31:00] */
-#define BCHP_PCIE_0_RC_CFG_VENDOR_VENDOR_SPECIFIC_REG3_Undefined_MASK 0xffffffff
-#define BCHP_PCIE_0_RC_CFG_VENDOR_VENDOR_SPECIFIC_REG3_Undefined_SHIFT 0
-#define BCHP_PCIE_0_RC_CFG_VENDOR_VENDOR_SPECIFIC_REG3_Undefined_DEFAULT 0x00000000
-
-/***************************************************************************
- *VENDOR_SPECIFIC_REG4 - Vendor Specific User Register 4
- ***************************************************************************/
-/* PCIE_0_RC_CFG_VENDOR :: VENDOR_SPECIFIC_REG4 :: Undefined [31:00] */
-#define BCHP_PCIE_0_RC_CFG_VENDOR_VENDOR_SPECIFIC_REG4_Undefined_MASK 0xffffffff
-#define BCHP_PCIE_0_RC_CFG_VENDOR_VENDOR_SPECIFIC_REG4_Undefined_SHIFT 0
-#define BCHP_PCIE_0_RC_CFG_VENDOR_VENDOR_SPECIFIC_REG4_Undefined_DEFAULT 0x00000000
-
-/***************************************************************************
- *VENDOR_SPECIFIC_REG5 - Vendor Specific User Register 5
- ***************************************************************************/
-/* PCIE_0_RC_CFG_VENDOR :: VENDOR_SPECIFIC_REG5 :: Undefined [31:00] */
-#define BCHP_PCIE_0_RC_CFG_VENDOR_VENDOR_SPECIFIC_REG5_Undefined_MASK 0xffffffff
-#define BCHP_PCIE_0_RC_CFG_VENDOR_VENDOR_SPECIFIC_REG5_Undefined_SHIFT 0
-#define BCHP_PCIE_0_RC_CFG_VENDOR_VENDOR_SPECIFIC_REG5_Undefined_DEFAULT 0x00000000
-
-/***************************************************************************
- *VENDOR_SPECIFIC_REG6 - Vendor Specific User Register 6
- ***************************************************************************/
-/* PCIE_0_RC_CFG_VENDOR :: VENDOR_SPECIFIC_REG6 :: Undefined [31:00] */
-#define BCHP_PCIE_0_RC_CFG_VENDOR_VENDOR_SPECIFIC_REG6_Undefined_MASK 0xffffffff
-#define BCHP_PCIE_0_RC_CFG_VENDOR_VENDOR_SPECIFIC_REG6_Undefined_SHIFT 0
-#define BCHP_PCIE_0_RC_CFG_VENDOR_VENDOR_SPECIFIC_REG6_Undefined_DEFAULT 0x00000000
-
-/***************************************************************************
- *VENDOR_SPECIFIC_REG7 - Vendor Specific User Register 7
- ***************************************************************************/
-/* PCIE_0_RC_CFG_VENDOR :: VENDOR_SPECIFIC_REG7 :: Undefined [31:00] */
-#define BCHP_PCIE_0_RC_CFG_VENDOR_VENDOR_SPECIFIC_REG7_Undefined_MASK 0xffffffff
-#define BCHP_PCIE_0_RC_CFG_VENDOR_VENDOR_SPECIFIC_REG7_Undefined_SHIFT 0
-#define BCHP_PCIE_0_RC_CFG_VENDOR_VENDOR_SPECIFIC_REG7_Undefined_DEFAULT 0x00000000
-
-/***************************************************************************
- *VENDOR_SPECIFIC_REG8 - Vendor Specific User Register 8
- ***************************************************************************/
-/* PCIE_0_RC_CFG_VENDOR :: VENDOR_SPECIFIC_REG8 :: Undefined [31:00] */
-#define BCHP_PCIE_0_RC_CFG_VENDOR_VENDOR_SPECIFIC_REG8_Undefined_MASK 0xffffffff
-#define BCHP_PCIE_0_RC_CFG_VENDOR_VENDOR_SPECIFIC_REG8_Undefined_SHIFT 0
-#define BCHP_PCIE_0_RC_CFG_VENDOR_VENDOR_SPECIFIC_REG8_Undefined_DEFAULT 0x00000000
-
-#endif /* #ifndef BCHP_PCIE_0_RC_CFG_VENDOR_H__ */
-
-/* End of File */
diff --git a/include/linux/brcmstb/7439a0/bchp_pcie_0_rgr1.h b/include/linux/brcmstb/7439a0/bchp_pcie_0_rgr1.h
deleted file mode 100644
index 59b3e9c..0000000
--- a/include/linux/brcmstb/7439a0/bchp_pcie_0_rgr1.h
+++ /dev/null
@@ -1,134 +0,0 @@
-/***************************************************************************
- * Copyright (c) 1999-2013, Broadcom Corporation
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
- *
- * Module Description:
- * DO NOT EDIT THIS FILE DIRECTLY
- *
- * This module was generated magically with RDB from a source description
- * file. You must edit the source file for changes to be made to this file.
- *
- *
- * Date: Generated on Tue Apr 16 03:26:51 2013
- * MD5 Checksum d41d8cd98f00b204e9800998ecf8427e
- *
- * Compiled with: RDB Utility combo_header.pl
- * RDB Parser 3.0
- * unknown unknown
- * Perl Interpreter 5.008008
- * Operating System linux
- *
- * Revision History:
- *
- * $brcm_Log: $
- *
- ***************************************************************************/
-
-#ifndef BCHP_PCIE_0_RGR1_H__
-#define BCHP_PCIE_0_RGR1_H__
-
-/***************************************************************************
- *PCIE_0_RGR1 - PCIe RBUS-GISB-RBUS Bridge Registers
- ***************************************************************************/
-#define BCHP_PCIE_0_RGR1_REVISION 0x00479200 /* RGR Bridge Revision */
-#define BCHP_PCIE_0_RGR1_CTRL 0x00479204 /* RGR Bridge Control Register */
-#define BCHP_PCIE_0_RGR1_RBUS_TIMER 0x00479208 /* RGR Bridge RBUS Timer Register */
-#define BCHP_PCIE_0_RGR1_SW_INIT_0 0x0047920c /* RGR Bridge Software Reset 0 Register */
-#define BCHP_PCIE_0_RGR1_SW_INIT_1 0x00479210 /* RGR Bridge Software Reset 1 Register */
-
-/***************************************************************************
- *REVISION - RGR Bridge Revision
- ***************************************************************************/
-/* PCIE_0_RGR1 :: REVISION :: reserved0 [31:16] */
-#define BCHP_PCIE_0_RGR1_REVISION_reserved0_MASK 0xffff0000
-#define BCHP_PCIE_0_RGR1_REVISION_reserved0_SHIFT 16
-
-/* PCIE_0_RGR1 :: REVISION :: MAJOR [15:08] */
-#define BCHP_PCIE_0_RGR1_REVISION_MAJOR_MASK 0x0000ff00
-#define BCHP_PCIE_0_RGR1_REVISION_MAJOR_SHIFT 8
-#define BCHP_PCIE_0_RGR1_REVISION_MAJOR_DEFAULT 0x00000002
-
-/* PCIE_0_RGR1 :: REVISION :: MINOR [07:00] */
-#define BCHP_PCIE_0_RGR1_REVISION_MINOR_MASK 0x000000ff
-#define BCHP_PCIE_0_RGR1_REVISION_MINOR_SHIFT 0
-#define BCHP_PCIE_0_RGR1_REVISION_MINOR_DEFAULT 0x00000000
-
-/***************************************************************************
- *CTRL - RGR Bridge Control Register
- ***************************************************************************/
-/* PCIE_0_RGR1 :: CTRL :: reserved0 [31:02] */
-#define BCHP_PCIE_0_RGR1_CTRL_reserved0_MASK 0xfffffffc
-#define BCHP_PCIE_0_RGR1_CTRL_reserved0_SHIFT 2
-
-/* PCIE_0_RGR1 :: CTRL :: rbus_error_intr [01:01] */
-#define BCHP_PCIE_0_RGR1_CTRL_rbus_error_intr_MASK 0x00000002
-#define BCHP_PCIE_0_RGR1_CTRL_rbus_error_intr_SHIFT 1
-#define BCHP_PCIE_0_RGR1_CTRL_rbus_error_intr_DEFAULT 0x00000000
-#define BCHP_PCIE_0_RGR1_CTRL_rbus_error_intr_INTR_DISABLE 0
-#define BCHP_PCIE_0_RGR1_CTRL_rbus_error_intr_INTR_ENABLE 1
-
-/* PCIE_0_RGR1 :: CTRL :: gisb_error_intr [00:00] */
-#define BCHP_PCIE_0_RGR1_CTRL_gisb_error_intr_MASK 0x00000001
-#define BCHP_PCIE_0_RGR1_CTRL_gisb_error_intr_SHIFT 0
-#define BCHP_PCIE_0_RGR1_CTRL_gisb_error_intr_DEFAULT 0x00000000
-#define BCHP_PCIE_0_RGR1_CTRL_gisb_error_intr_INTR_DISABLE 0
-#define BCHP_PCIE_0_RGR1_CTRL_gisb_error_intr_INTR_ENABLE 1
-
-/***************************************************************************
- *RBUS_TIMER - RGR Bridge RBUS Timer Register
- ***************************************************************************/
-/* PCIE_0_RGR1 :: RBUS_TIMER :: timer_value [31:00] */
-#define BCHP_PCIE_0_RGR1_RBUS_TIMER_timer_value_MASK 0xffffffff
-#define BCHP_PCIE_0_RGR1_RBUS_TIMER_timer_value_SHIFT 0
-#define BCHP_PCIE_0_RGR1_RBUS_TIMER_timer_value_DEFAULT 0x0e297d00
-
-/***************************************************************************
- *SW_INIT_0 - RGR Bridge Software Reset 0 Register
- ***************************************************************************/
-/* PCIE_0_RGR1 :: SW_INIT_0 :: reserved0 [31:01] */
-#define BCHP_PCIE_0_RGR1_SW_INIT_0_reserved0_MASK 0xfffffffe
-#define BCHP_PCIE_0_RGR1_SW_INIT_0_reserved0_SHIFT 1
-
-/* PCIE_0_RGR1 :: SW_INIT_0 :: SPARE_SW_INIT [00:00] */
-#define BCHP_PCIE_0_RGR1_SW_INIT_0_SPARE_SW_INIT_MASK 0x00000001
-#define BCHP_PCIE_0_RGR1_SW_INIT_0_SPARE_SW_INIT_SHIFT 0
-#define BCHP_PCIE_0_RGR1_SW_INIT_0_SPARE_SW_INIT_DEFAULT 0x00000000
-#define BCHP_PCIE_0_RGR1_SW_INIT_0_SPARE_SW_INIT_DEASSERT 0
-#define BCHP_PCIE_0_RGR1_SW_INIT_0_SPARE_SW_INIT_ASSERT 1
-
-/***************************************************************************
- *SW_INIT_1 - RGR Bridge Software Reset 1 Register
- ***************************************************************************/
-/* PCIE_0_RGR1 :: SW_INIT_1 :: reserved0 [31:02] */
-#define BCHP_PCIE_0_RGR1_SW_INIT_1_reserved0_MASK 0xfffffffc
-#define BCHP_PCIE_0_RGR1_SW_INIT_1_reserved0_SHIFT 2
-
-/* PCIE_0_RGR1 :: SW_INIT_1 :: PCIE_BRIDGE_SW_INIT [01:01] */
-#define BCHP_PCIE_0_RGR1_SW_INIT_1_PCIE_BRIDGE_SW_INIT_MASK 0x00000002
-#define BCHP_PCIE_0_RGR1_SW_INIT_1_PCIE_BRIDGE_SW_INIT_SHIFT 1
-#define BCHP_PCIE_0_RGR1_SW_INIT_1_PCIE_BRIDGE_SW_INIT_DEFAULT 0x00000001
-#define BCHP_PCIE_0_RGR1_SW_INIT_1_PCIE_BRIDGE_SW_INIT_DEASSERT 0
-#define BCHP_PCIE_0_RGR1_SW_INIT_1_PCIE_BRIDGE_SW_INIT_ASSERT 1
-
-/* PCIE_0_RGR1 :: SW_INIT_1 :: PCIE_SW_PERST [00:00] */
-#define BCHP_PCIE_0_RGR1_SW_INIT_1_PCIE_SW_PERST_MASK 0x00000001
-#define BCHP_PCIE_0_RGR1_SW_INIT_1_PCIE_SW_PERST_SHIFT 0
-#define BCHP_PCIE_0_RGR1_SW_INIT_1_PCIE_SW_PERST_DEFAULT 0x00000001
-#define BCHP_PCIE_0_RGR1_SW_INIT_1_PCIE_SW_PERST_DEASSERT 0
-#define BCHP_PCIE_0_RGR1_SW_INIT_1_PCIE_SW_PERST_ASSERT 1
-
-#endif /* #ifndef BCHP_PCIE_0_RGR1_H__ */
-
-/* End of File */
diff --git a/include/linux/brcmstb/7439a0/bchp_shimphy_addr_cntl_0.h b/include/linux/brcmstb/7439a0/bchp_shimphy_addr_cntl_0.h
deleted file mode 100644
index cf46b41..0000000
--- a/include/linux/brcmstb/7439a0/bchp_shimphy_addr_cntl_0.h
+++ /dev/null
@@ -1,556 +0,0 @@
-/***************************************************************************
- * Copyright (c) 1999-2013, Broadcom Corporation
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
- *
- * Module Description:
- * DO NOT EDIT THIS FILE DIRECTLY
- *
- * This module was generated magically with RDB from a source description
- * file. You must edit the source file for changes to be made to this file.
- *
- *
- * Date: Generated on Tue Apr 16 03:26:50 2013
- * MD5 Checksum d41d8cd98f00b204e9800998ecf8427e
- *
- * Compiled with: RDB Utility combo_header.pl
- * RDB Parser 3.0
- * unknown unknown
- * Perl Interpreter 5.008008
- * Operating System linux
- *
- * Revision History:
- *
- * $brcm_Log: $
- *
- ***************************************************************************/
-
-#ifndef BCHP_SHIMPHY_ADDR_CNTL_0_H__
-#define BCHP_SHIMPHY_ADDR_CNTL_0_H__
-
-/***************************************************************************
- *SHIMPHY_ADDR_CNTL_0 - 0 DDR SHIMPHY Control Registers
- ***************************************************************************/
-#define BCHP_SHIMPHY_ADDR_CNTL_0_CONFIG 0x00908000 /* SHIMPHY Config register */
-#define BCHP_SHIMPHY_ADDR_CNTL_0_SHIMPHY_REV_ID 0x00908004 /* SHIMPHY Revision ID Register. */
-#define BCHP_SHIMPHY_ADDR_CNTL_0_RESET 0x00908008 /* DDR soft reset register */
-#define BCHP_SHIMPHY_ADDR_CNTL_0_DFI_CONTROL 0x00908038 /* DFI Interface Control Register */
-#define BCHP_SHIMPHY_ADDR_CNTL_0_DFI_STATUS 0x0090803c /* DFI Interface Status Register */
-#define BCHP_SHIMPHY_ADDR_CNTL_0_PHY_LPM_STAT 0x00908040 /* PHY Power Control Status Register */
-#define BCHP_SHIMPHY_ADDR_CNTL_0_IDLE_POWER_SAVING 0x00908048 /* DDR PHY Idle power saving Control register */
-#define BCHP_SHIMPHY_ADDR_CNTL_0_PHY_STANDBY_EXIT 0x0090804c /* DDR PHY standby exit register */
-#define BCHP_SHIMPHY_ADDR_CNTL_0_ANALOG_BYPASS_CNTRL 0x0090806c /* Analog macro register bypass control */
-#define BCHP_SHIMPHY_ADDR_CNTL_0_DDR_PLL_EXT_CLKSEL 0x00908070 /* DDR PLL external clock select register */
-#define BCHP_SHIMPHY_ADDR_CNTL_0_TEST_MODE_CNTRL_REG 0x00908074 /* SHIMPHY testport control register */
-#define BCHP_SHIMPHY_ADDR_CNTL_0_DISABLE_CHIP_BYPASS_PLL 0x0090807c /* DDR bypass pll mode disable register. */
-#define BCHP_SHIMPHY_ADDR_CNTL_0_VECTOR_MODE_CLK_SEL 0x00908088 /* DDR VECTOR PLL bypass mode clock select */
-#define BCHP_SHIMPHY_ADDR_CNTL_0_DDR_PAD_CNTRL 0x0090808c /* DDR Pad control register */
-#define BCHP_SHIMPHY_ADDR_CNTL_0_CLK_GATE 0x00908098 /* CLK_667_ENABLE Register */
-#define BCHP_SHIMPHY_ADDR_CNTL_0_SHIMPHY_STATUS 0x0090809c /* SHIMPHY Status Register */
-#define BCHP_SHIMPHY_ADDR_CNTL_0_CMD_DATA_FIFO 0x00908028 /* Command and Data FIFO Status Register */
-#define BCHP_SHIMPHY_ADDR_CNTL_0_RD_DATAPATH 0x0090802c /* Read Datapath Status Register */
-#define BCHP_SHIMPHY_ADDR_CNTL_0_FLAG_BUS 0x00908030 /* TP_OUT bus value Register */
-#define BCHP_SHIMPHY_ADDR_CNTL_0_MISC 0x00908034 /* Miscellaneous Register */
-#define BCHP_SHIMPHY_ADDR_CNTL_0_SPARE0_RW 0x009080a4 /* Spare register */
-#define BCHP_SHIMPHY_ADDR_CNTL_0_SPARE1_RW 0x009080a8 /* Spare register */
-#define BCHP_SHIMPHY_ADDR_CNTL_0_SPARE0_RO 0x009080ac /* Spare register */
-#define BCHP_SHIMPHY_ADDR_CNTL_0_SPARE1_RO 0x009080b0 /* Spare register */
-#define BCHP_SHIMPHY_ADDR_CNTL_0_DDR3_RESET_CNTRL 0x009080b4 /* FORCE_DDR3_RESET Deassert Register */
-
-/***************************************************************************
- *CONFIG - SHIMPHY Config register
- ***************************************************************************/
-/* SHIMPHY_ADDR_CNTL_0 :: CONFIG :: DFI_CLK_DISABLE [31:31] */
-#define BCHP_SHIMPHY_ADDR_CNTL_0_CONFIG_DFI_CLK_DISABLE_MASK 0x80000000
-#define BCHP_SHIMPHY_ADDR_CNTL_0_CONFIG_DFI_CLK_DISABLE_SHIFT 31
-#define BCHP_SHIMPHY_ADDR_CNTL_0_CONFIG_DFI_CLK_DISABLE_DEFAULT 0x00000000
-
-/* SHIMPHY_ADDR_CNTL_0 :: CONFIG :: DRAM_NOP_OR_DSEL_CMD [30:30] */
-#define BCHP_SHIMPHY_ADDR_CNTL_0_CONFIG_DRAM_NOP_OR_DSEL_CMD_MASK 0x40000000
-#define BCHP_SHIMPHY_ADDR_CNTL_0_CONFIG_DRAM_NOP_OR_DSEL_CMD_SHIFT 30
-#define BCHP_SHIMPHY_ADDR_CNTL_0_CONFIG_DRAM_NOP_OR_DSEL_CMD_DEFAULT 0x00000000
-
-/* SHIMPHY_ADDR_CNTL_0 :: CONFIG :: LAST_RD_STRETCH [29:29] */
-#define BCHP_SHIMPHY_ADDR_CNTL_0_CONFIG_LAST_RD_STRETCH_MASK 0x20000000
-#define BCHP_SHIMPHY_ADDR_CNTL_0_CONFIG_LAST_RD_STRETCH_SHIFT 29
-#define BCHP_SHIMPHY_ADDR_CNTL_0_CONFIG_LAST_RD_STRETCH_DEFAULT 0x00000000
-
-/* SHIMPHY_ADDR_CNTL_0 :: CONFIG :: reserved0 [28:24] */
-#define BCHP_SHIMPHY_ADDR_CNTL_0_CONFIG_reserved0_MASK 0x1f000000
-#define BCHP_SHIMPHY_ADDR_CNTL_0_CONFIG_reserved0_SHIFT 24
-
-/* SHIMPHY_ADDR_CNTL_0 :: CONFIG :: LAST_READ_LATENCY [23:16] */
-#define BCHP_SHIMPHY_ADDR_CNTL_0_CONFIG_LAST_READ_LATENCY_MASK 0x00ff0000
-#define BCHP_SHIMPHY_ADDR_CNTL_0_CONFIG_LAST_READ_LATENCY_SHIFT 16
-#define BCHP_SHIMPHY_ADDR_CNTL_0_CONFIG_LAST_READ_LATENCY_DEFAULT 0x0000000b
-
-/* SHIMPHY_ADDR_CNTL_0 :: CONFIG :: READ_LATENCY [15:08] */
-#define BCHP_SHIMPHY_ADDR_CNTL_0_CONFIG_READ_LATENCY_MASK 0x0000ff00
-#define BCHP_SHIMPHY_ADDR_CNTL_0_CONFIG_READ_LATENCY_SHIFT 8
-#define BCHP_SHIMPHY_ADDR_CNTL_0_CONFIG_READ_LATENCY_DEFAULT 0x00000007
-
-/* SHIMPHY_ADDR_CNTL_0 :: CONFIG :: reserved1 [07:06] */
-#define BCHP_SHIMPHY_ADDR_CNTL_0_CONFIG_reserved1_MASK 0x000000c0
-#define BCHP_SHIMPHY_ADDR_CNTL_0_CONFIG_reserved1_SHIFT 6
-
-/* SHIMPHY_ADDR_CNTL_0 :: CONFIG :: WRITE_LATENCY [05:00] */
-#define BCHP_SHIMPHY_ADDR_CNTL_0_CONFIG_WRITE_LATENCY_MASK 0x0000003f
-#define BCHP_SHIMPHY_ADDR_CNTL_0_CONFIG_WRITE_LATENCY_SHIFT 0
-#define BCHP_SHIMPHY_ADDR_CNTL_0_CONFIG_WRITE_LATENCY_DEFAULT 0x0000000e
-
-/***************************************************************************
- *SHIMPHY_REV_ID - SHIMPHY Revision ID Register.
- ***************************************************************************/
-/* SHIMPHY_ADDR_CNTL_0 :: SHIMPHY_REV_ID :: reserved0 [31:16] */
-#define BCHP_SHIMPHY_ADDR_CNTL_0_SHIMPHY_REV_ID_reserved0_MASK 0xffff0000
-#define BCHP_SHIMPHY_ADDR_CNTL_0_SHIMPHY_REV_ID_reserved0_SHIFT 16
-
-/* SHIMPHY_ADDR_CNTL_0 :: SHIMPHY_REV_ID :: MAJOR_ID [15:08] */
-#define BCHP_SHIMPHY_ADDR_CNTL_0_SHIMPHY_REV_ID_MAJOR_ID_MASK 0x0000ff00
-#define BCHP_SHIMPHY_ADDR_CNTL_0_SHIMPHY_REV_ID_MAJOR_ID_SHIFT 8
-#define BCHP_SHIMPHY_ADDR_CNTL_0_SHIMPHY_REV_ID_MAJOR_ID_DEFAULT 0x00000001
-
-/* SHIMPHY_ADDR_CNTL_0 :: SHIMPHY_REV_ID :: MINOR_ID [07:00] */
-#define BCHP_SHIMPHY_ADDR_CNTL_0_SHIMPHY_REV_ID_MINOR_ID_MASK 0x000000ff
-#define BCHP_SHIMPHY_ADDR_CNTL_0_SHIMPHY_REV_ID_MINOR_ID_SHIFT 0
-#define BCHP_SHIMPHY_ADDR_CNTL_0_SHIMPHY_REV_ID_MINOR_ID_DEFAULT 0x00000000
-
-/***************************************************************************
- *RESET - DDR soft reset register
- ***************************************************************************/
-/* SHIMPHY_ADDR_CNTL_0 :: RESET :: reserved0 [31:03] */
-#define BCHP_SHIMPHY_ADDR_CNTL_0_RESET_reserved0_MASK 0xfffffff8
-#define BCHP_SHIMPHY_ADDR_CNTL_0_RESET_reserved0_SHIFT 3
-
-/* SHIMPHY_ADDR_CNTL_0 :: RESET :: DATAPATH_216_RESET [02:02] */
-#define BCHP_SHIMPHY_ADDR_CNTL_0_RESET_DATAPATH_216_RESET_MASK 0x00000004
-#define BCHP_SHIMPHY_ADDR_CNTL_0_RESET_DATAPATH_216_RESET_SHIFT 2
-#define BCHP_SHIMPHY_ADDR_CNTL_0_RESET_DATAPATH_216_RESET_DEFAULT 0x00000000
-
-/* SHIMPHY_ADDR_CNTL_0 :: RESET :: DATAPATH_DDR_RESET [01:01] */
-#define BCHP_SHIMPHY_ADDR_CNTL_0_RESET_DATAPATH_DDR_RESET_MASK 0x00000002
-#define BCHP_SHIMPHY_ADDR_CNTL_0_RESET_DATAPATH_DDR_RESET_SHIFT 1
-#define BCHP_SHIMPHY_ADDR_CNTL_0_RESET_DATAPATH_DDR_RESET_DEFAULT 0x00000000
-
-/* SHIMPHY_ADDR_CNTL_0 :: RESET :: PHY_PWRUP_RSB [00:00] */
-#define BCHP_SHIMPHY_ADDR_CNTL_0_RESET_PHY_PWRUP_RSB_MASK 0x00000001
-#define BCHP_SHIMPHY_ADDR_CNTL_0_RESET_PHY_PWRUP_RSB_SHIFT 0
-#define BCHP_SHIMPHY_ADDR_CNTL_0_RESET_PHY_PWRUP_RSB_DEFAULT 0x00000000
-
-/***************************************************************************
- *DFI_CONTROL - DFI Interface Control Register
- ***************************************************************************/
-/* SHIMPHY_ADDR_CNTL_0 :: DFI_CONTROL :: reserved0 [31:13] */
-#define BCHP_SHIMPHY_ADDR_CNTL_0_DFI_CONTROL_reserved0_MASK 0xffffe000
-#define BCHP_SHIMPHY_ADDR_CNTL_0_DFI_CONTROL_reserved0_SHIFT 13
-
-/* SHIMPHY_ADDR_CNTL_0 :: DFI_CONTROL :: PHY_PLL_PWRDWN [12:12] */
-#define BCHP_SHIMPHY_ADDR_CNTL_0_DFI_CONTROL_PHY_PLL_PWRDWN_MASK 0x00001000
-#define BCHP_SHIMPHY_ADDR_CNTL_0_DFI_CONTROL_PHY_PLL_PWRDWN_SHIFT 12
-#define BCHP_SHIMPHY_ADDR_CNTL_0_DFI_CONTROL_PHY_PLL_PWRDWN_DEFAULT 0x00000000
-
-/* SHIMPHY_ADDR_CNTL_0 :: DFI_CONTROL :: reserved1 [11:10] */
-#define BCHP_SHIMPHY_ADDR_CNTL_0_DFI_CONTROL_reserved1_MASK 0x00000c00
-#define BCHP_SHIMPHY_ADDR_CNTL_0_DFI_CONTROL_reserved1_SHIFT 10
-
-/* SHIMPHY_ADDR_CNTL_0 :: DFI_CONTROL :: TM2_MUX_SEL [09:09] */
-#define BCHP_SHIMPHY_ADDR_CNTL_0_DFI_CONTROL_TM2_MUX_SEL_MASK 0x00000200
-#define BCHP_SHIMPHY_ADDR_CNTL_0_DFI_CONTROL_TM2_MUX_SEL_SHIFT 9
-#define BCHP_SHIMPHY_ADDR_CNTL_0_DFI_CONTROL_TM2_MUX_SEL_DEFAULT 0x00000000
-
-/* SHIMPHY_ADDR_CNTL_0 :: DFI_CONTROL :: PHY_PLL_HOLD_CH [08:08] */
-#define BCHP_SHIMPHY_ADDR_CNTL_0_DFI_CONTROL_PHY_PLL_HOLD_CH_MASK 0x00000100
-#define BCHP_SHIMPHY_ADDR_CNTL_0_DFI_CONTROL_PHY_PLL_HOLD_CH_SHIFT 8
-#define BCHP_SHIMPHY_ADDR_CNTL_0_DFI_CONTROL_PHY_PLL_HOLD_CH_DEFAULT 0x00000000
-
-/* SHIMPHY_ADDR_CNTL_0 :: DFI_CONTROL :: reserved2 [07:01] */
-#define BCHP_SHIMPHY_ADDR_CNTL_0_DFI_CONTROL_reserved2_MASK 0x000000fe
-#define BCHP_SHIMPHY_ADDR_CNTL_0_DFI_CONTROL_reserved2_SHIFT 1
-
-/* SHIMPHY_ADDR_CNTL_0 :: DFI_CONTROL :: LATCH_FIRST_ERROR [00:00] */
-#define BCHP_SHIMPHY_ADDR_CNTL_0_DFI_CONTROL_LATCH_FIRST_ERROR_MASK 0x00000001
-#define BCHP_SHIMPHY_ADDR_CNTL_0_DFI_CONTROL_LATCH_FIRST_ERROR_SHIFT 0
-#define BCHP_SHIMPHY_ADDR_CNTL_0_DFI_CONTROL_LATCH_FIRST_ERROR_DEFAULT 0x00000001
-
-/***************************************************************************
- *DFI_STATUS - DFI Interface Status Register
- ***************************************************************************/
-/* SHIMPHY_ADDR_CNTL_0 :: DFI_STATUS :: reserved0 [31:18] */
-#define BCHP_SHIMPHY_ADDR_CNTL_0_DFI_STATUS_reserved0_MASK 0xfffc0000
-#define BCHP_SHIMPHY_ADDR_CNTL_0_DFI_STATUS_reserved0_SHIFT 18
-
-/* SHIMPHY_ADDR_CNTL_0 :: DFI_STATUS :: PHY_EDC_MONITOR_STATUS [17:17] */
-#define BCHP_SHIMPHY_ADDR_CNTL_0_DFI_STATUS_PHY_EDC_MONITOR_STATUS_MASK 0x00020000
-#define BCHP_SHIMPHY_ADDR_CNTL_0_DFI_STATUS_PHY_EDC_MONITOR_STATUS_SHIFT 17
-#define BCHP_SHIMPHY_ADDR_CNTL_0_DFI_STATUS_PHY_EDC_MONITOR_STATUS_DEFAULT 0x00000000
-
-/* SHIMPHY_ADDR_CNTL_0 :: DFI_STATUS :: PHY_VDL_MONITOR_STATUS [16:16] */
-#define BCHP_SHIMPHY_ADDR_CNTL_0_DFI_STATUS_PHY_VDL_MONITOR_STATUS_MASK 0x00010000
-#define BCHP_SHIMPHY_ADDR_CNTL_0_DFI_STATUS_PHY_VDL_MONITOR_STATUS_SHIFT 16
-#define BCHP_SHIMPHY_ADDR_CNTL_0_DFI_STATUS_PHY_VDL_MONITOR_STATUS_DEFAULT 0x00000000
-
-/* SHIMPHY_ADDR_CNTL_0 :: DFI_STATUS :: reserved1 [15:09] */
-#define BCHP_SHIMPHY_ADDR_CNTL_0_DFI_STATUS_reserved1_MASK 0x0000fe00
-#define BCHP_SHIMPHY_ADDR_CNTL_0_DFI_STATUS_reserved1_SHIFT 9
-
-/* SHIMPHY_ADDR_CNTL_0 :: DFI_STATUS :: ERROR_VALID [08:08] */
-#define BCHP_SHIMPHY_ADDR_CNTL_0_DFI_STATUS_ERROR_VALID_MASK 0x00000100
-#define BCHP_SHIMPHY_ADDR_CNTL_0_DFI_STATUS_ERROR_VALID_SHIFT 8
-#define BCHP_SHIMPHY_ADDR_CNTL_0_DFI_STATUS_ERROR_VALID_DEFAULT 0x00000000
-
-/* SHIMPHY_ADDR_CNTL_0 :: DFI_STATUS :: reserved2 [07:04] */
-#define BCHP_SHIMPHY_ADDR_CNTL_0_DFI_STATUS_reserved2_MASK 0x000000f0
-#define BCHP_SHIMPHY_ADDR_CNTL_0_DFI_STATUS_reserved2_SHIFT 4
-
-/* SHIMPHY_ADDR_CNTL_0 :: DFI_STATUS :: ERROR_INFO [03:00] */
-#define BCHP_SHIMPHY_ADDR_CNTL_0_DFI_STATUS_ERROR_INFO_MASK 0x0000000f
-#define BCHP_SHIMPHY_ADDR_CNTL_0_DFI_STATUS_ERROR_INFO_SHIFT 0
-#define BCHP_SHIMPHY_ADDR_CNTL_0_DFI_STATUS_ERROR_INFO_DEFAULT 0x00000000
-
-/***************************************************************************
- *PHY_LPM_STAT - PHY Power Control Status Register
- ***************************************************************************/
-/* SHIMPHY_ADDR_CNTL_0 :: PHY_LPM_STAT :: reserved0 [31:10] */
-#define BCHP_SHIMPHY_ADDR_CNTL_0_PHY_LPM_STAT_reserved0_MASK 0xfffffc00
-#define BCHP_SHIMPHY_ADDR_CNTL_0_PHY_LPM_STAT_reserved0_SHIFT 10
-
-/* SHIMPHY_ADDR_CNTL_0 :: PHY_LPM_STAT :: PHY_RBUS_IS_IDLE [09:09] */
-#define BCHP_SHIMPHY_ADDR_CNTL_0_PHY_LPM_STAT_PHY_RBUS_IS_IDLE_MASK 0x00000200
-#define BCHP_SHIMPHY_ADDR_CNTL_0_PHY_LPM_STAT_PHY_RBUS_IS_IDLE_SHIFT 9
-#define BCHP_SHIMPHY_ADDR_CNTL_0_PHY_LPM_STAT_PHY_RBUS_IS_IDLE_DEFAULT 0x00000000
-
-/* SHIMPHY_ADDR_CNTL_0 :: PHY_LPM_STAT :: PHY_IS_IDLE [08:08] */
-#define BCHP_SHIMPHY_ADDR_CNTL_0_PHY_LPM_STAT_PHY_IS_IDLE_MASK 0x00000100
-#define BCHP_SHIMPHY_ADDR_CNTL_0_PHY_LPM_STAT_PHY_IS_IDLE_SHIFT 8
-#define BCHP_SHIMPHY_ADDR_CNTL_0_PHY_LPM_STAT_PHY_IS_IDLE_DEFAULT 0x00000000
-
-/* SHIMPHY_ADDR_CNTL_0 :: PHY_LPM_STAT :: reserved1 [07:00] */
-#define BCHP_SHIMPHY_ADDR_CNTL_0_PHY_LPM_STAT_reserved1_MASK 0x000000ff
-#define BCHP_SHIMPHY_ADDR_CNTL_0_PHY_LPM_STAT_reserved1_SHIFT 0
-
-/***************************************************************************
- *IDLE_POWER_SAVING - DDR PHY Idle power saving Control register
- ***************************************************************************/
-/* SHIMPHY_ADDR_CNTL_0 :: IDLE_POWER_SAVING :: reserved0 [31:06] */
-#define BCHP_SHIMPHY_ADDR_CNTL_0_IDLE_POWER_SAVING_reserved0_MASK 0xffffffc0
-#define BCHP_SHIMPHY_ADDR_CNTL_0_IDLE_POWER_SAVING_reserved0_SHIFT 6
-
-/* SHIMPHY_ADDR_CNTL_0 :: IDLE_POWER_SAVING :: PhyAddrCntl [05:04] */
-#define BCHP_SHIMPHY_ADDR_CNTL_0_IDLE_POWER_SAVING_PhyAddrCntl_MASK 0x00000030
-#define BCHP_SHIMPHY_ADDR_CNTL_0_IDLE_POWER_SAVING_PhyAddrCntl_SHIFT 4
-#define BCHP_SHIMPHY_ADDR_CNTL_0_IDLE_POWER_SAVING_PhyAddrCntl_DEFAULT 0x00000000
-
-/* SHIMPHY_ADDR_CNTL_0 :: IDLE_POWER_SAVING :: ByteLane3 [03:03] */
-#define BCHP_SHIMPHY_ADDR_CNTL_0_IDLE_POWER_SAVING_ByteLane3_MASK 0x00000008
-#define BCHP_SHIMPHY_ADDR_CNTL_0_IDLE_POWER_SAVING_ByteLane3_SHIFT 3
-#define BCHP_SHIMPHY_ADDR_CNTL_0_IDLE_POWER_SAVING_ByteLane3_DEFAULT 0x00000000
-
-/* SHIMPHY_ADDR_CNTL_0 :: IDLE_POWER_SAVING :: ByteLane2 [02:02] */
-#define BCHP_SHIMPHY_ADDR_CNTL_0_IDLE_POWER_SAVING_ByteLane2_MASK 0x00000004
-#define BCHP_SHIMPHY_ADDR_CNTL_0_IDLE_POWER_SAVING_ByteLane2_SHIFT 2
-#define BCHP_SHIMPHY_ADDR_CNTL_0_IDLE_POWER_SAVING_ByteLane2_DEFAULT 0x00000000
-
-/* SHIMPHY_ADDR_CNTL_0 :: IDLE_POWER_SAVING :: ByteLane1 [01:01] */
-#define BCHP_SHIMPHY_ADDR_CNTL_0_IDLE_POWER_SAVING_ByteLane1_MASK 0x00000002
-#define BCHP_SHIMPHY_ADDR_CNTL_0_IDLE_POWER_SAVING_ByteLane1_SHIFT 1
-#define BCHP_SHIMPHY_ADDR_CNTL_0_IDLE_POWER_SAVING_ByteLane1_DEFAULT 0x00000000
-
-/* SHIMPHY_ADDR_CNTL_0 :: IDLE_POWER_SAVING :: ByteLane0 [00:00] */
-#define BCHP_SHIMPHY_ADDR_CNTL_0_IDLE_POWER_SAVING_ByteLane0_MASK 0x00000001
-#define BCHP_SHIMPHY_ADDR_CNTL_0_IDLE_POWER_SAVING_ByteLane0_SHIFT 0
-#define BCHP_SHIMPHY_ADDR_CNTL_0_IDLE_POWER_SAVING_ByteLane0_DEFAULT 0x00000000
-
-/***************************************************************************
- *PHY_STANDBY_EXIT - DDR PHY standby exit register
- ***************************************************************************/
-/* SHIMPHY_ADDR_CNTL_0 :: PHY_STANDBY_EXIT :: reserved0 [31:01] */
-#define BCHP_SHIMPHY_ADDR_CNTL_0_PHY_STANDBY_EXIT_reserved0_MASK 0xfffffffe
-#define BCHP_SHIMPHY_ADDR_CNTL_0_PHY_STANDBY_EXIT_reserved0_SHIFT 1
-
-/* SHIMPHY_ADDR_CNTL_0 :: PHY_STANDBY_EXIT :: ENABLE [00:00] */
-#define BCHP_SHIMPHY_ADDR_CNTL_0_PHY_STANDBY_EXIT_ENABLE_MASK 0x00000001
-#define BCHP_SHIMPHY_ADDR_CNTL_0_PHY_STANDBY_EXIT_ENABLE_SHIFT 0
-#define BCHP_SHIMPHY_ADDR_CNTL_0_PHY_STANDBY_EXIT_ENABLE_DEFAULT 0x00000001
-
-/***************************************************************************
- *ANALOG_BYPASS_CNTRL - Analog macro register bypass control
- ***************************************************************************/
-/* SHIMPHY_ADDR_CNTL_0 :: ANALOG_BYPASS_CNTRL :: reserved0 [31:01] */
-#define BCHP_SHIMPHY_ADDR_CNTL_0_ANALOG_BYPASS_CNTRL_reserved0_MASK 0xfffffffe
-#define BCHP_SHIMPHY_ADDR_CNTL_0_ANALOG_BYPASS_CNTRL_reserved0_SHIFT 1
-
-/* SHIMPHY_ADDR_CNTL_0 :: ANALOG_BYPASS_CNTRL :: BYPASS_PLL [00:00] */
-#define BCHP_SHIMPHY_ADDR_CNTL_0_ANALOG_BYPASS_CNTRL_BYPASS_PLL_MASK 0x00000001
-#define BCHP_SHIMPHY_ADDR_CNTL_0_ANALOG_BYPASS_CNTRL_BYPASS_PLL_SHIFT 0
-#define BCHP_SHIMPHY_ADDR_CNTL_0_ANALOG_BYPASS_CNTRL_BYPASS_PLL_DEFAULT 0x00000000
-
-/***************************************************************************
- *DDR_PLL_EXT_CLKSEL - DDR PLL external clock select register
- ***************************************************************************/
-/* SHIMPHY_ADDR_CNTL_0 :: DDR_PLL_EXT_CLKSEL :: reserved0 [31:01] */
-#define BCHP_SHIMPHY_ADDR_CNTL_0_DDR_PLL_EXT_CLKSEL_reserved0_MASK 0xfffffffe
-#define BCHP_SHIMPHY_ADDR_CNTL_0_DDR_PLL_EXT_CLKSEL_reserved0_SHIFT 1
-
-/* SHIMPHY_ADDR_CNTL_0 :: DDR_PLL_EXT_CLKSEL :: EXT_CLK_SEL [00:00] */
-#define BCHP_SHIMPHY_ADDR_CNTL_0_DDR_PLL_EXT_CLKSEL_EXT_CLK_SEL_MASK 0x00000001
-#define BCHP_SHIMPHY_ADDR_CNTL_0_DDR_PLL_EXT_CLKSEL_EXT_CLK_SEL_SHIFT 0
-#define BCHP_SHIMPHY_ADDR_CNTL_0_DDR_PLL_EXT_CLKSEL_EXT_CLK_SEL_DEFAULT 0x00000000
-
-/***************************************************************************
- *TEST_MODE_CNTRL_REG - SHIMPHY testport control register
- ***************************************************************************/
-/* SHIMPHY_ADDR_CNTL_0 :: TEST_MODE_CNTRL_REG :: reserved_for_eco0 [31:00] */
-#define BCHP_SHIMPHY_ADDR_CNTL_0_TEST_MODE_CNTRL_REG_reserved_for_eco0_MASK 0xffffffff
-#define BCHP_SHIMPHY_ADDR_CNTL_0_TEST_MODE_CNTRL_REG_reserved_for_eco0_SHIFT 0
-#define BCHP_SHIMPHY_ADDR_CNTL_0_TEST_MODE_CNTRL_REG_reserved_for_eco0_DEFAULT 0x00000000
-
-/***************************************************************************
- *DISABLE_CHIP_BYPASS_PLL - DDR bypass pll mode disable register.
- ***************************************************************************/
-/* SHIMPHY_ADDR_CNTL_0 :: DISABLE_CHIP_BYPASS_PLL :: reserved0 [31:01] */
-#define BCHP_SHIMPHY_ADDR_CNTL_0_DISABLE_CHIP_BYPASS_PLL_reserved0_MASK 0xfffffffe
-#define BCHP_SHIMPHY_ADDR_CNTL_0_DISABLE_CHIP_BYPASS_PLL_reserved0_SHIFT 1
-
-/* SHIMPHY_ADDR_CNTL_0 :: DISABLE_CHIP_BYPASS_PLL :: DISABLE_BYPASS_PLL [00:00] */
-#define BCHP_SHIMPHY_ADDR_CNTL_0_DISABLE_CHIP_BYPASS_PLL_DISABLE_BYPASS_PLL_MASK 0x00000001
-#define BCHP_SHIMPHY_ADDR_CNTL_0_DISABLE_CHIP_BYPASS_PLL_DISABLE_BYPASS_PLL_SHIFT 0
-#define BCHP_SHIMPHY_ADDR_CNTL_0_DISABLE_CHIP_BYPASS_PLL_DISABLE_BYPASS_PLL_DEFAULT 0x00000000
-
-/***************************************************************************
- *VECTOR_MODE_CLK_SEL - DDR VECTOR PLL bypass mode clock select
- ***************************************************************************/
-/* SHIMPHY_ADDR_CNTL_0 :: VECTOR_MODE_CLK_SEL :: reserved0 [31:01] */
-#define BCHP_SHIMPHY_ADDR_CNTL_0_VECTOR_MODE_CLK_SEL_reserved0_MASK 0xfffffffe
-#define BCHP_SHIMPHY_ADDR_CNTL_0_VECTOR_MODE_CLK_SEL_reserved0_SHIFT 1
-
-/* SHIMPHY_ADDR_CNTL_0 :: VECTOR_MODE_CLK_SEL :: SEL [00:00] */
-#define BCHP_SHIMPHY_ADDR_CNTL_0_VECTOR_MODE_CLK_SEL_SEL_MASK 0x00000001
-#define BCHP_SHIMPHY_ADDR_CNTL_0_VECTOR_MODE_CLK_SEL_SEL_SHIFT 0
-#define BCHP_SHIMPHY_ADDR_CNTL_0_VECTOR_MODE_CLK_SEL_SEL_DEFAULT 0x00000000
-
-/***************************************************************************
- *DDR_PAD_CNTRL - DDR Pad control register
- ***************************************************************************/
-/* SHIMPHY_ADDR_CNTL_0 :: DDR_PAD_CNTRL :: reserved0 [31:07] */
-#define BCHP_SHIMPHY_ADDR_CNTL_0_DDR_PAD_CNTRL_reserved0_MASK 0xffffff80
-#define BCHP_SHIMPHY_ADDR_CNTL_0_DDR_PAD_CNTRL_reserved0_SHIFT 7
-
-/* SHIMPHY_ADDR_CNTL_0 :: DDR_PAD_CNTRL :: IDDQ_MODE_ON_SELFREF [06:06] */
-#define BCHP_SHIMPHY_ADDR_CNTL_0_DDR_PAD_CNTRL_IDDQ_MODE_ON_SELFREF_MASK 0x00000040
-#define BCHP_SHIMPHY_ADDR_CNTL_0_DDR_PAD_CNTRL_IDDQ_MODE_ON_SELFREF_SHIFT 6
-#define BCHP_SHIMPHY_ADDR_CNTL_0_DDR_PAD_CNTRL_IDDQ_MODE_ON_SELFREF_DEFAULT 0x00000000
-
-/* SHIMPHY_ADDR_CNTL_0 :: DDR_PAD_CNTRL :: PHY_IDLE_ENABLE [05:05] */
-#define BCHP_SHIMPHY_ADDR_CNTL_0_DDR_PAD_CNTRL_PHY_IDLE_ENABLE_MASK 0x00000020
-#define BCHP_SHIMPHY_ADDR_CNTL_0_DDR_PAD_CNTRL_PHY_IDLE_ENABLE_SHIFT 5
-#define BCHP_SHIMPHY_ADDR_CNTL_0_DDR_PAD_CNTRL_PHY_IDLE_ENABLE_DEFAULT 0x00000000
-
-/* SHIMPHY_ADDR_CNTL_0 :: DDR_PAD_CNTRL :: HIZ_ON_SELFREF [04:04] */
-#define BCHP_SHIMPHY_ADDR_CNTL_0_DDR_PAD_CNTRL_HIZ_ON_SELFREF_MASK 0x00000010
-#define BCHP_SHIMPHY_ADDR_CNTL_0_DDR_PAD_CNTRL_HIZ_ON_SELFREF_SHIFT 4
-#define BCHP_SHIMPHY_ADDR_CNTL_0_DDR_PAD_CNTRL_HIZ_ON_SELFREF_DEFAULT 0x00000000
-
-/* SHIMPHY_ADDR_CNTL_0 :: DDR_PAD_CNTRL :: CNTRL [03:00] */
-#define BCHP_SHIMPHY_ADDR_CNTL_0_DDR_PAD_CNTRL_CNTRL_MASK 0x0000000f
-#define BCHP_SHIMPHY_ADDR_CNTL_0_DDR_PAD_CNTRL_CNTRL_SHIFT 0
-#define BCHP_SHIMPHY_ADDR_CNTL_0_DDR_PAD_CNTRL_CNTRL_DEFAULT 0x00000000
-
-/***************************************************************************
- *CLK_GATE - CLK_667_ENABLE Register
- ***************************************************************************/
-/* SHIMPHY_ADDR_CNTL_0 :: CLK_GATE :: UNUSED [31:01] */
-#define BCHP_SHIMPHY_ADDR_CNTL_0_CLK_GATE_UNUSED_MASK 0xfffffffe
-#define BCHP_SHIMPHY_ADDR_CNTL_0_CLK_GATE_UNUSED_SHIFT 1
-#define BCHP_SHIMPHY_ADDR_CNTL_0_CLK_GATE_UNUSED_DEFAULT 0x00000000
-
-/* SHIMPHY_ADDR_CNTL_0 :: CLK_GATE :: CLK_667_ENABLE [00:00] */
-#define BCHP_SHIMPHY_ADDR_CNTL_0_CLK_GATE_CLK_667_ENABLE_MASK 0x00000001
-#define BCHP_SHIMPHY_ADDR_CNTL_0_CLK_GATE_CLK_667_ENABLE_SHIFT 0
-#define BCHP_SHIMPHY_ADDR_CNTL_0_CLK_GATE_CLK_667_ENABLE_DEFAULT 0x00000000
-
-/***************************************************************************
- *SHIMPHY_STATUS - SHIMPHY Status Register
- ***************************************************************************/
-/* SHIMPHY_ADDR_CNTL_0 :: SHIMPHY_STATUS :: reserved0 [31:01] */
-#define BCHP_SHIMPHY_ADDR_CNTL_0_SHIMPHY_STATUS_reserved0_MASK 0xfffffffe
-#define BCHP_SHIMPHY_ADDR_CNTL_0_SHIMPHY_STATUS_reserved0_SHIFT 1
-
-/* SHIMPHY_ADDR_CNTL_0 :: SHIMPHY_STATUS :: READY [00:00] */
-#define BCHP_SHIMPHY_ADDR_CNTL_0_SHIMPHY_STATUS_READY_MASK 0x00000001
-#define BCHP_SHIMPHY_ADDR_CNTL_0_SHIMPHY_STATUS_READY_SHIFT 0
-#define BCHP_SHIMPHY_ADDR_CNTL_0_SHIMPHY_STATUS_READY_DEFAULT 0x00000000
-
-/***************************************************************************
- *CMD_DATA_FIFO - Command and Data FIFO Status Register
- ***************************************************************************/
-/* SHIMPHY_ADDR_CNTL_0 :: CMD_DATA_FIFO :: reserved0 [31:26] */
-#define BCHP_SHIMPHY_ADDR_CNTL_0_CMD_DATA_FIFO_reserved0_MASK 0xfc000000
-#define BCHP_SHIMPHY_ADDR_CNTL_0_CMD_DATA_FIFO_reserved0_SHIFT 26
-
-/* SHIMPHY_ADDR_CNTL_0 :: CMD_DATA_FIFO :: FIFO_FULL [25:25] */
-#define BCHP_SHIMPHY_ADDR_CNTL_0_CMD_DATA_FIFO_FIFO_FULL_MASK 0x02000000
-#define BCHP_SHIMPHY_ADDR_CNTL_0_CMD_DATA_FIFO_FIFO_FULL_SHIFT 25
-
-/* SHIMPHY_ADDR_CNTL_0 :: CMD_DATA_FIFO :: FIFO_EMPTY [24:24] */
-#define BCHP_SHIMPHY_ADDR_CNTL_0_CMD_DATA_FIFO_FIFO_EMPTY_MASK 0x01000000
-#define BCHP_SHIMPHY_ADDR_CNTL_0_CMD_DATA_FIFO_FIFO_EMPTY_SHIFT 24
-
-/* SHIMPHY_ADDR_CNTL_0 :: CMD_DATA_FIFO :: reserved1 [23:10] */
-#define BCHP_SHIMPHY_ADDR_CNTL_0_CMD_DATA_FIFO_reserved1_MASK 0x00fffc00
-#define BCHP_SHIMPHY_ADDR_CNTL_0_CMD_DATA_FIFO_reserved1_SHIFT 10
-
-/* SHIMPHY_ADDR_CNTL_0 :: CMD_DATA_FIFO :: WR_PNTR [09:05] */
-#define BCHP_SHIMPHY_ADDR_CNTL_0_CMD_DATA_FIFO_WR_PNTR_MASK 0x000003e0
-#define BCHP_SHIMPHY_ADDR_CNTL_0_CMD_DATA_FIFO_WR_PNTR_SHIFT 5
-
-/* SHIMPHY_ADDR_CNTL_0 :: CMD_DATA_FIFO :: RD_PNTR [04:00] */
-#define BCHP_SHIMPHY_ADDR_CNTL_0_CMD_DATA_FIFO_RD_PNTR_MASK 0x0000001f
-#define BCHP_SHIMPHY_ADDR_CNTL_0_CMD_DATA_FIFO_RD_PNTR_SHIFT 0
-
-/***************************************************************************
- *RD_DATAPATH - Read Datapath Status Register
- ***************************************************************************/
-/* SHIMPHY_ADDR_CNTL_0 :: RD_DATAPATH :: reserved0 [31:10] */
-#define BCHP_SHIMPHY_ADDR_CNTL_0_RD_DATAPATH_reserved0_MASK 0xfffffc00
-#define BCHP_SHIMPHY_ADDR_CNTL_0_RD_DATAPATH_reserved0_SHIFT 10
-
-/* SHIMPHY_ADDR_CNTL_0 :: RD_DATAPATH :: WR_PNTR [09:05] */
-#define BCHP_SHIMPHY_ADDR_CNTL_0_RD_DATAPATH_WR_PNTR_MASK 0x000003e0
-#define BCHP_SHIMPHY_ADDR_CNTL_0_RD_DATAPATH_WR_PNTR_SHIFT 5
-
-/* SHIMPHY_ADDR_CNTL_0 :: RD_DATAPATH :: RD_PNTR [04:00] */
-#define BCHP_SHIMPHY_ADDR_CNTL_0_RD_DATAPATH_RD_PNTR_MASK 0x0000001f
-#define BCHP_SHIMPHY_ADDR_CNTL_0_RD_DATAPATH_RD_PNTR_SHIFT 0
-
-/***************************************************************************
- *FLAG_BUS - TP_OUT bus value Register
- ***************************************************************************/
-/* SHIMPHY_ADDR_CNTL_0 :: FLAG_BUS :: FLAG_BUS [31:00] */
-#define BCHP_SHIMPHY_ADDR_CNTL_0_FLAG_BUS_FLAG_BUS_MASK 0xffffffff
-#define BCHP_SHIMPHY_ADDR_CNTL_0_FLAG_BUS_FLAG_BUS_SHIFT 0
-
-/***************************************************************************
- *MISC - Miscellaneous Register
- ***************************************************************************/
-/* SHIMPHY_ADDR_CNTL_0 :: MISC :: reserved0 [31:20] */
-#define BCHP_SHIMPHY_ADDR_CNTL_0_MISC_reserved0_MASK 0xfff00000
-#define BCHP_SHIMPHY_ADDR_CNTL_0_MISC_reserved0_SHIFT 20
-
-/* SHIMPHY_ADDR_CNTL_0 :: MISC :: ASYNC_FIFO_AF_THRESHOLD [19:15] */
-#define BCHP_SHIMPHY_ADDR_CNTL_0_MISC_ASYNC_FIFO_AF_THRESHOLD_MASK 0x000f8000
-#define BCHP_SHIMPHY_ADDR_CNTL_0_MISC_ASYNC_FIFO_AF_THRESHOLD_SHIFT 15
-#define BCHP_SHIMPHY_ADDR_CNTL_0_MISC_ASYNC_FIFO_AF_THRESHOLD_DEFAULT 0x0000000a
-
-/* SHIMPHY_ADDR_CNTL_0 :: MISC :: reserved_for_eco1 [14:12] */
-#define BCHP_SHIMPHY_ADDR_CNTL_0_MISC_reserved_for_eco1_MASK 0x00007000
-#define BCHP_SHIMPHY_ADDR_CNTL_0_MISC_reserved_for_eco1_SHIFT 12
-#define BCHP_SHIMPHY_ADDR_CNTL_0_MISC_reserved_for_eco1_DEFAULT 0x00000000
-
-/* SHIMPHY_ADDR_CNTL_0 :: MISC :: DFI_ERROR_STATUS_CLR [11:11] */
-#define BCHP_SHIMPHY_ADDR_CNTL_0_MISC_DFI_ERROR_STATUS_CLR_MASK 0x00000800
-#define BCHP_SHIMPHY_ADDR_CNTL_0_MISC_DFI_ERROR_STATUS_CLR_SHIFT 11
-#define BCHP_SHIMPHY_ADDR_CNTL_0_MISC_DFI_ERROR_STATUS_CLR_DEFAULT 0x00000000
-
-/* SHIMPHY_ADDR_CNTL_0 :: MISC :: EDC_MONTIOR_STATUS_CLR [10:10] */
-#define BCHP_SHIMPHY_ADDR_CNTL_0_MISC_EDC_MONTIOR_STATUS_CLR_MASK 0x00000400
-#define BCHP_SHIMPHY_ADDR_CNTL_0_MISC_EDC_MONTIOR_STATUS_CLR_SHIFT 10
-#define BCHP_SHIMPHY_ADDR_CNTL_0_MISC_EDC_MONTIOR_STATUS_CLR_DEFAULT 0x00000000
-
-/* SHIMPHY_ADDR_CNTL_0 :: MISC :: VDL_MONITOR_STATUS_CLR [09:09] */
-#define BCHP_SHIMPHY_ADDR_CNTL_0_MISC_VDL_MONITOR_STATUS_CLR_MASK 0x00000200
-#define BCHP_SHIMPHY_ADDR_CNTL_0_MISC_VDL_MONITOR_STATUS_CLR_SHIFT 9
-#define BCHP_SHIMPHY_ADDR_CNTL_0_MISC_VDL_MONITOR_STATUS_CLR_DEFAULT 0x00000000
-
-/* SHIMPHY_ADDR_CNTL_0 :: MISC :: FUNC1 [08:08] */
-#define BCHP_SHIMPHY_ADDR_CNTL_0_MISC_FUNC1_MASK 0x00000100
-#define BCHP_SHIMPHY_ADDR_CNTL_0_MISC_FUNC1_SHIFT 8
-#define BCHP_SHIMPHY_ADDR_CNTL_0_MISC_FUNC1_DEFAULT 0x00000000
-
-/* SHIMPHY_ADDR_CNTL_0 :: MISC :: FUNC0 [07:07] */
-#define BCHP_SHIMPHY_ADDR_CNTL_0_MISC_FUNC0_MASK 0x00000080
-#define BCHP_SHIMPHY_ADDR_CNTL_0_MISC_FUNC0_SHIFT 7
-#define BCHP_SHIMPHY_ADDR_CNTL_0_MISC_FUNC0_DEFAULT 0x00000000
-
-/* SHIMPHY_ADDR_CNTL_0 :: MISC :: C2IO_INIT_RDY_OVR [06:06] */
-#define BCHP_SHIMPHY_ADDR_CNTL_0_MISC_C2IO_INIT_RDY_OVR_MASK 0x00000040
-#define BCHP_SHIMPHY_ADDR_CNTL_0_MISC_C2IO_INIT_RDY_OVR_SHIFT 6
-#define BCHP_SHIMPHY_ADDR_CNTL_0_MISC_C2IO_INIT_RDY_OVR_DEFAULT 0x00000000
-
-/* SHIMPHY_ADDR_CNTL_0 :: MISC :: RD_FIFO_HOLD_CLR [05:05] */
-#define BCHP_SHIMPHY_ADDR_CNTL_0_MISC_RD_FIFO_HOLD_CLR_MASK 0x00000020
-#define BCHP_SHIMPHY_ADDR_CNTL_0_MISC_RD_FIFO_HOLD_CLR_SHIFT 5
-#define BCHP_SHIMPHY_ADDR_CNTL_0_MISC_RD_FIFO_HOLD_CLR_DEFAULT 0x00000000
-
-/* SHIMPHY_ADDR_CNTL_0 :: MISC :: CMD_FIFO_HOLD_CLR [04:04] */
-#define BCHP_SHIMPHY_ADDR_CNTL_0_MISC_CMD_FIFO_HOLD_CLR_MASK 0x00000010
-#define BCHP_SHIMPHY_ADDR_CNTL_0_MISC_CMD_FIFO_HOLD_CLR_SHIFT 4
-#define BCHP_SHIMPHY_ADDR_CNTL_0_MISC_CMD_FIFO_HOLD_CLR_DEFAULT 0x00000000
-
-/* SHIMPHY_ADDR_CNTL_0 :: MISC :: reserved2 [03:01] */
-#define BCHP_SHIMPHY_ADDR_CNTL_0_MISC_reserved2_MASK 0x0000000e
-#define BCHP_SHIMPHY_ADDR_CNTL_0_MISC_reserved2_SHIFT 1
-
-/* SHIMPHY_ADDR_CNTL_0 :: MISC :: DATA_OVERRUN_CLR [00:00] */
-#define BCHP_SHIMPHY_ADDR_CNTL_0_MISC_DATA_OVERRUN_CLR_MASK 0x00000001
-#define BCHP_SHIMPHY_ADDR_CNTL_0_MISC_DATA_OVERRUN_CLR_SHIFT 0
-#define BCHP_SHIMPHY_ADDR_CNTL_0_MISC_DATA_OVERRUN_CLR_DEFAULT 0x00000000
-
-/***************************************************************************
- *SPARE0_RW - Spare register
- ***************************************************************************/
-/* SHIMPHY_ADDR_CNTL_0 :: SPARE0_RW :: reserved_for_eco0 [31:00] */
-#define BCHP_SHIMPHY_ADDR_CNTL_0_SPARE0_RW_reserved_for_eco0_MASK 0xffffffff
-#define BCHP_SHIMPHY_ADDR_CNTL_0_SPARE0_RW_reserved_for_eco0_SHIFT 0
-#define BCHP_SHIMPHY_ADDR_CNTL_0_SPARE0_RW_reserved_for_eco0_DEFAULT 0x00000000
-
-/***************************************************************************
- *SPARE1_RW - Spare register
- ***************************************************************************/
-/* SHIMPHY_ADDR_CNTL_0 :: SPARE1_RW :: reserved_for_eco0 [31:00] */
-#define BCHP_SHIMPHY_ADDR_CNTL_0_SPARE1_RW_reserved_for_eco0_MASK 0xffffffff
-#define BCHP_SHIMPHY_ADDR_CNTL_0_SPARE1_RW_reserved_for_eco0_SHIFT 0
-#define BCHP_SHIMPHY_ADDR_CNTL_0_SPARE1_RW_reserved_for_eco0_DEFAULT 0x00000000
-
-/***************************************************************************
- *SPARE0_RO - Spare register
- ***************************************************************************/
-/* SHIMPHY_ADDR_CNTL_0 :: SPARE0_RO :: reserved_for_eco0 [31:00] */
-#define BCHP_SHIMPHY_ADDR_CNTL_0_SPARE0_RO_reserved_for_eco0_MASK 0xffffffff
-#define BCHP_SHIMPHY_ADDR_CNTL_0_SPARE0_RO_reserved_for_eco0_SHIFT 0
-#define BCHP_SHIMPHY_ADDR_CNTL_0_SPARE0_RO_reserved_for_eco0_DEFAULT 0x00000000
-
-/***************************************************************************
- *SPARE1_RO - Spare register
- ***************************************************************************/
-/* SHIMPHY_ADDR_CNTL_0 :: SPARE1_RO :: reserved_for_eco0 [31:00] */
-#define BCHP_SHIMPHY_ADDR_CNTL_0_SPARE1_RO_reserved_for_eco0_MASK 0xffffffff
-#define BCHP_SHIMPHY_ADDR_CNTL_0_SPARE1_RO_reserved_for_eco0_SHIFT 0
-#define BCHP_SHIMPHY_ADDR_CNTL_0_SPARE1_RO_reserved_for_eco0_DEFAULT 0x00000000
-
-/***************************************************************************
- *DDR3_RESET_CNTRL - FORCE_DDR3_RESET Deassert Register
- ***************************************************************************/
-/* SHIMPHY_ADDR_CNTL_0 :: DDR3_RESET_CNTRL :: UNUSED [31:01] */
-#define BCHP_SHIMPHY_ADDR_CNTL_0_DDR3_RESET_CNTRL_UNUSED_MASK 0xfffffffe
-#define BCHP_SHIMPHY_ADDR_CNTL_0_DDR3_RESET_CNTRL_UNUSED_SHIFT 1
-#define BCHP_SHIMPHY_ADDR_CNTL_0_DDR3_RESET_CNTRL_UNUSED_DEFAULT 0x00000000
-
-/* SHIMPHY_ADDR_CNTL_0 :: DDR3_RESET_CNTRL :: FORCE_DDR3_RESET [00:00] */
-#define BCHP_SHIMPHY_ADDR_CNTL_0_DDR3_RESET_CNTRL_FORCE_DDR3_RESET_MASK 0x00000001
-#define BCHP_SHIMPHY_ADDR_CNTL_0_DDR3_RESET_CNTRL_FORCE_DDR3_RESET_SHIFT 0
-#define BCHP_SHIMPHY_ADDR_CNTL_0_DDR3_RESET_CNTRL_FORCE_DDR3_RESET_DEFAULT 0x00000001
-
-#endif /* #ifndef BCHP_SHIMPHY_ADDR_CNTL_0_H__ */
-
-/* End of File */
diff --git a/include/linux/brcmstb/7439a0/bchp_sun_top_ctrl.h b/include/linux/brcmstb/7439a0/bchp_sun_top_ctrl.h
deleted file mode 100644
index cf6895b..0000000
--- a/include/linux/brcmstb/7439a0/bchp_sun_top_ctrl.h
+++ /dev/null
@@ -1,7278 +0,0 @@
-/***************************************************************************
- * Copyright (c) 1999-2014, Broadcom Corporation
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
- *
- * Module Description:
- * DO NOT EDIT THIS FILE DIRECTLY
- *
- * This module was generated magically with RDB from a source description
- * file. You must edit the source file for changes to be made to this file.
- *
- *
- * Date: Generated on Wed Sep 3 14:30:57 2014
- * Full Compile MD5 Checksum edbc259d5ef948d04693ec04bc4d44b4
- * (minus title and desc)
- * MD5 Checksum de2524c7728bb833dc65ac44b70daaa5
- *
- * Compiled with: RDB Utility combo_header.pl
- * RDB Parser 3.0
- * unknown unknown
- * Perl Interpreter 5.008005
- * Operating System linux
- *
- * Revision History:
- *
- * $brcm_Log: $
- *
- ***************************************************************************/
-
-#ifndef BCHP_SUN_TOP_CTRL_H__
-#define BCHP_SUN_TOP_CTRL_H__
-
-/***************************************************************************
- *SUN_TOP_CTRL - Top Control registers
- ***************************************************************************/
-#define BCHP_SUN_TOP_CTRL_CHIP_FAMILY_ID 0x00404000 /* Chip family ID */
-#define BCHP_SUN_TOP_CTRL_PRODUCT_ID 0x00404004 /* Product Revision ID */
-#define BCHP_SUN_TOP_CTRL_BSP_FEATURE_TABLE_ADDR 0x00404008 /* BSP feature table address */
-#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0 0x0040401c /* Strapping values */
-#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_1 0x00404020 /* Strapping values */
-#define BCHP_SUN_TOP_CTRL_BOND_STATUS 0x00404024 /* Bond option value register */
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0 0x00404028 /* OTP option test register */
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1 0x0040402c /* OTP option test register */
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0 0x00404030 /* OTP option status register */
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1 0x00404034 /* OTP option status register */
-#define BCHP_SUN_TOP_CTRL_SEMAPHORE_0 0x00404038 /* Semaphore channel 0 */
-#define BCHP_SUN_TOP_CTRL_SEMAPHORE_1 0x0040403c /* Semaphore channel 1 */
-#define BCHP_SUN_TOP_CTRL_SEMAPHORE_2 0x00404040 /* Semaphore channel 2 */
-#define BCHP_SUN_TOP_CTRL_SEMAPHORE_3 0x00404044 /* Semaphore channel 3 */
-#define BCHP_SUN_TOP_CTRL_SEMAPHORE_4 0x00404048 /* Semaphore channel 4 */
-#define BCHP_SUN_TOP_CTRL_SEMAPHORE_5 0x0040404c /* Semaphore channel 5 */
-#define BCHP_SUN_TOP_CTRL_SEMAPHORE_6 0x00404050 /* Semaphore channel 6 */
-#define BCHP_SUN_TOP_CTRL_SEMAPHORE_7 0x00404054 /* Semaphore channel 7 */
-#define BCHP_SUN_TOP_CTRL_SEMAPHORE_8 0x00404058 /* Semaphore channel 8 */
-#define BCHP_SUN_TOP_CTRL_SEMAPHORE_9 0x0040405c /* Semaphore channel 9 */
-#define BCHP_SUN_TOP_CTRL_SEMAPHORE_10 0x00404060 /* Semaphore channel 10 */
-#define BCHP_SUN_TOP_CTRL_SEMAPHORE_11 0x00404064 /* Semaphore channel 11 */
-#define BCHP_SUN_TOP_CTRL_SEMAPHORE_12 0x00404068 /* Semaphore channel 12 */
-#define BCHP_SUN_TOP_CTRL_SEMAPHORE_13 0x0040406c /* Semaphore channel 13 */
-#define BCHP_SUN_TOP_CTRL_SEMAPHORE_14 0x00404070 /* Semaphore channel 14 */
-#define BCHP_SUN_TOP_CTRL_SEMAPHORE_15 0x00404074 /* Semaphore channel 15 */
-#define BCHP_SUN_TOP_CTRL_GEN_WATCHDOG_0 0x00404078 /* General watchdog timer 0 */
-#define BCHP_SUN_TOP_CTRL_GEN_WATCHDOG_1 0x0040407c /* General watchdog timer 1 */
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0 0x00404080 /* General control register 0 */
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1 0x00404084 /* General control register 1 */
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_2 0x00404088 /* General control register 2 */
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_3 0x0040408c /* General control register 3 */
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_4 0x00404090 /* General control register 4 */
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_5 0x00404094 /* General control register 5 */
-#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0 0x00404098 /* General status register 0 */
-#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_1 0x0040409c /* General status register 1 */
-#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_2 0x004040a0 /* General status register 2 */
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0 0x004040a4 /* General control register without scan 0 */
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1 0x004040a8 /* General control register without scan 1 */
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2 0x004040ac /* General control register without scan 2 */
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3 0x004040b0 /* General control register without scan 3 */
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_4 0x004040b4 /* General control register without scan 4 */
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5 0x004040b8 /* General control register without scan 5 */
-#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_3 0x004040bc /* General status register 3 */
-#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_4 0x004040c0 /* General status register 4 */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0 0x00404100 /* Pinmux control register 0 */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1 0x00404104 /* Pinmux control register 1 */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2 0x00404108 /* Pinmux control register 2 */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3 0x0040410c /* Pinmux control register 3 */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4 0x00404110 /* Pinmux control register 4 */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5 0x00404114 /* Pinmux control register 5 */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6 0x00404118 /* Pinmux control register 6 */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7 0x0040411c /* Pinmux control register 7 */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8 0x00404120 /* Pinmux control register 8 */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9 0x00404124 /* Pinmux control register 9 */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10 0x00404128 /* Pinmux control register 10 */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11 0x0040412c /* Pinmux control register 11 */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12 0x00404130 /* Pinmux control register 12 */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13 0x00404134 /* Pinmux control register 13 */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14 0x00404138 /* Pinmux control register 14 */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15 0x0040413c /* Pinmux control register 15 */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16 0x00404140 /* Pinmux control register 16 */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17 0x00404144 /* Pinmux control register 17 */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0 0x00404148 /* Pad pull-up/pull-down control register 0 */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1 0x0040414c /* Pad pull-up/pull-down control register 1 */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2 0x00404150 /* Pad pull-up/pull-down control register 2 */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3 0x00404154 /* Pad pull-up/pull-down control register 3 */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4 0x00404158 /* Pad pull-up/pull-down control register 4 */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5 0x0040415c /* Pad pull-up/pull-down control register 5 */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6 0x00404160 /* Pad pull-up/pull-down control register 6 */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7 0x00404164 /* Pad pull-up/pull-down control register 7 */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8 0x00404168 /* Pad pull-up/pull-down control register 8 */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9 0x0040416c /* Pad pull-up/pull-down control register 9 */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10 0x00404170 /* Pad pull-up/pull-down control register 10 */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11 0x00404174 /* Pad pull-up/pull-down control register 11 */
-#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0 0x00404178 /* Bypass clock unselect register 0 */
-#define BCHP_SUN_TOP_CTRL_RESET_CTRL 0x00404300 /* Reset control */
-#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE 0x00404304 /* Reset source enable */
-#define BCHP_SUN_TOP_CTRL_SW_MASTER_RESET 0x00404308 /* Software master reset */
-#define BCHP_SUN_TOP_CTRL_HW_RESET_EXTENSION 0x0040430c /* Hardware reset extension */
-#define BCHP_SUN_TOP_CTRL_RESET_MONITOR 0x00404310 /* Reset Monitor */
-#define BCHP_SUN_TOP_CTRL_RESET_HISTORY 0x00404314 /* Reset history */
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET 0x00404318 /* Software init 0 set */
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR 0x0040431c /* Software init 0 clear */
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS 0x00404320 /* Software init 0 status */
-#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR 0x00404324 /* Security software init 0 monitor */
-#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR 0x00404328 /* Test configuration software init 0 monitor */
-#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR 0x0040432c /* Final software init 0 monitor */
-#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET 0x00404330 /* Software init 1 set */
-#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR 0x00404334 /* Software init 1 clear */
-#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS 0x00404338 /* Software init 1 status */
-#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR 0x0040433c /* Security software init 1 monitor */
-#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR 0x00404340 /* Test configuration software init 1 monitor */
-#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR 0x00404344 /* Final software init 1 monitor */
-#define BCHP_SUN_TOP_CTRL_SW_INIT_ONE_SHOT_TRIGGER 0x00404348 /* Software init one-shot trigger */
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_WIDTH 0x0040434c /* One-shot 0 width */
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK 0x00404350 /* One-shot 0 mask for software init 0 */
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK 0x00404354 /* One-shot 0 mask for software init 1 */
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_WIDTH 0x00404358 /* One-shot 1 width */
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK 0x0040435c /* One-shot 1 mask for software init 0 */
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK 0x00404360 /* One-shot 1 mask for software init 1 */
-#define BCHP_SUN_TOP_CTRL_UNCLEARED_SCRATCH 0x00404364 /* Scratch register */
-#define BCHP_SUN_TOP_CTRL_SPARE_CTRL 0x00404368 /* Spare control bits reserved for future use */
-#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL 0x00404380 /* Test port control */
-#define BCHP_SUN_TOP_CTRL_TEST_PORT_OUT_PEEK 0x00404384 /* Testport peek register */
-#define BCHP_SUN_TOP_CTRL_TEST_PORT_OUT_POKE 0x00404388 /* Testport poke register */
-#define BCHP_SUN_TOP_CTRL_TEST_PORT_IN_PEEK 0x0040438c /* Testport peek register */
-#define BCHP_SUN_TOP_CTRL_TEST_PORT_IN_POKE 0x00404390 /* Testport poke register */
-#define BCHP_SUN_TOP_CTRL_EJTAG_INPUT_EN 0x00404394 /* EJTAG input bus enables */
-#define BCHP_SUN_TOP_CTRL_EJTAG_OUTPUT_SEL 0x00404398 /* EJTAG output select */
-#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL 0x004043a0 /* VTRAP Control */
-#define BCHP_SUN_TOP_CTRL_VTRAP_STATUS 0x004043a4 /* VTRAP Status */
-#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0 0x004043a8 /* UART Router select 0 */
-#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1 0x004043ac /* UART Router select 1 */
-#define BCHP_SUN_TOP_CTRL_SSP_CONFIG 0x00404400 /* Serial Slave Port configuration register */
-#define BCHP_SUN_TOP_CTRL_SERS_REV 0x00404420 /* SERS Revision Register */
-#define BCHP_SUN_TOP_CTRL_SERS_CFG 0x00404424 /* SERS Configuration Register */
-#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL 0x00404514 /* Block select for RO testmode */
-#define BCHP_SUN_TOP_CTRL_TEST_CONFIGURATION 0x00404518 /* Test configuration */
-
-/***************************************************************************
- *CHIP_FAMILY_ID - Chip family ID
- ***************************************************************************/
-/* SUN_TOP_CTRL :: CHIP_FAMILY_ID :: chip_family_id [31:00] */
-#define BCHP_SUN_TOP_CTRL_CHIP_FAMILY_ID_chip_family_id_MASK 0xffffffff
-#define BCHP_SUN_TOP_CTRL_CHIP_FAMILY_ID_chip_family_id_SHIFT 0
-#define BCHP_SUN_TOP_CTRL_CHIP_FAMILY_ID_chip_family_id_DEFAULT 0x74390000
-
-/***************************************************************************
- *PRODUCT_ID - Product Revision ID
- ***************************************************************************/
-/* SUN_TOP_CTRL :: PRODUCT_ID :: product_id [31:00] */
-#define BCHP_SUN_TOP_CTRL_PRODUCT_ID_product_id_MASK 0xffffffff
-#define BCHP_SUN_TOP_CTRL_PRODUCT_ID_product_id_SHIFT 0
-#define BCHP_SUN_TOP_CTRL_PRODUCT_ID_product_id_DEFAULT 0x74390000
-
-/***************************************************************************
- *BSP_FEATURE_TABLE_ADDR - BSP feature table address
- ***************************************************************************/
-/* SUN_TOP_CTRL :: BSP_FEATURE_TABLE_ADDR :: bsp_feature_table_addr [31:00] */
-#define BCHP_SUN_TOP_CTRL_BSP_FEATURE_TABLE_ADDR_bsp_feature_table_addr_MASK 0xffffffff
-#define BCHP_SUN_TOP_CTRL_BSP_FEATURE_TABLE_ADDR_bsp_feature_table_addr_SHIFT 0
-#define BCHP_SUN_TOP_CTRL_BSP_FEATURE_TABLE_ADDR_bsp_feature_table_addr_DEFAULT 0x00000000
-
-/***************************************************************************
- *STRAP_VALUE_0 - Strapping values
- ***************************************************************************/
-/* SUN_TOP_CTRL :: STRAP_VALUE_0 :: reserved0 [31:09] */
-#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0_reserved0_MASK 0xfffffe00
-#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0_reserved0_SHIFT 9
-
-/* SUN_TOP_CTRL :: STRAP_VALUE_0 :: strap_system_big_endian [08:08] */
-#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0_strap_system_big_endian_MASK 0x00000100
-#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0_strap_system_big_endian_SHIFT 8
-#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0_strap_system_big_endian_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: STRAP_VALUE_0 :: strap_boot_shape [07:03] */
-#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0_strap_boot_shape_MASK 0x000000f8
-#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0_strap_boot_shape_SHIFT 3
-#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0_strap_boot_shape_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: STRAP_VALUE_0 :: strap_rc_ep [02:02] */
-#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0_strap_rc_ep_MASK 0x00000004
-#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0_strap_rc_ep_SHIFT 2
-#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0_strap_rc_ep_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: STRAP_VALUE_0 :: strap_reset_outb_def_val [01:01] */
-#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0_strap_reset_outb_def_val_MASK 0x00000002
-#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0_strap_reset_outb_def_val_SHIFT 1
-#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0_strap_reset_outb_def_val_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: STRAP_VALUE_0 :: strap_rsvd_1 [00:00] */
-#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0_strap_rsvd_1_MASK 0x00000001
-#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0_strap_rsvd_1_SHIFT 0
-#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0_strap_rsvd_1_DEFAULT 0x00000000
-
-/***************************************************************************
- *STRAP_VALUE_1 - Strapping values
- ***************************************************************************/
-/* SUN_TOP_CTRL :: STRAP_VALUE_1 :: reserved0 [31:06] */
-#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_1_reserved0_MASK 0xffffffc0
-#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_1_reserved0_SHIFT 6
-
-/* SUN_TOP_CTRL :: STRAP_VALUE_1 :: strap_hipass_xtal [05:05] */
-#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_1_strap_hipass_xtal_MASK 0x00000020
-#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_1_strap_hipass_xtal_SHIFT 5
-#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_1_strap_hipass_xtal_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: STRAP_VALUE_1 :: strap_xcore_bias [04:01] */
-#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_1_strap_xcore_bias_MASK 0x0000001e
-#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_1_strap_xcore_bias_SHIFT 1
-#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_1_strap_xcore_bias_DEFAULT 0x00000004
-
-/* SUN_TOP_CTRL :: STRAP_VALUE_1 :: strap_rsvd_0 [00:00] */
-#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_1_strap_rsvd_0_MASK 0x00000001
-#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_1_strap_rsvd_0_SHIFT 0
-#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_1_strap_rsvd_0_DEFAULT 0x00000000
-
-/***************************************************************************
- *BOND_STATUS - Bond option value register
- ***************************************************************************/
-/* SUN_TOP_CTRL :: BOND_STATUS :: reserved0 [31:01] */
-#define BCHP_SUN_TOP_CTRL_BOND_STATUS_reserved0_MASK 0xfffffffe
-#define BCHP_SUN_TOP_CTRL_BOND_STATUS_reserved0_SHIFT 1
-
-/* SUN_TOP_CTRL :: BOND_STATUS :: bond_reserved [00:00] */
-#define BCHP_SUN_TOP_CTRL_BOND_STATUS_bond_reserved_MASK 0x00000001
-#define BCHP_SUN_TOP_CTRL_BOND_STATUS_bond_reserved_SHIFT 0
-
-/***************************************************************************
- *OTP_OPTION_TEST_0 - OTP option test register
- ***************************************************************************/
-/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_pcie0_disable [31:31] */
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_pcie0_disable_MASK 0x80000000
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_pcie0_disable_SHIFT 31
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_pcie0_disable_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_moca_disable [30:30] */
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_moca_disable_MASK 0x40000000
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_moca_disable_SHIFT 30
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_moca_disable_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_av_output_disable [29:29] */
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_av_output_disable_MASK 0x20000000
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_av_output_disable_SHIFT 29
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_av_output_disable_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_vc4_disable [28:28] */
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_vc4_disable_MASK 0x10000000
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_vc4_disable_SHIFT 28
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_vc4_disable_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_4kx2k_disable [27:27] */
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_4kx2k_disable_MASK 0x08000000
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_4kx2k_disable_SHIFT 27
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_4kx2k_disable_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_sata_disable [26:26] */
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_sata_disable_MASK 0x04000000
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_sata_disable_SHIFT 26
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_sata_disable_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_macrovision_disable [25:25] */
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_macrovision_disable_MASK 0x02000000
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_macrovision_disable_SHIFT 25
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_macrovision_disable_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_hdcp_disable [24:24] */
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_hdcp_disable_MASK 0x01000000
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_hdcp_disable_SHIFT 24
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_hdcp_disable_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_hdmi_pass_thru_disable [23:23] */
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_hdmi_pass_thru_disable_MASK 0x00800000
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_hdmi_pass_thru_disable_SHIFT 23
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_hdmi_pass_thru_disable_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_hdmi_rx_disable [22:22] */
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_hdmi_rx_disable_MASK 0x00400000
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_hdmi_rx_disable_SHIFT 22
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_hdmi_rx_disable_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_rv9_disable [21:21] */
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_rv9_disable_MASK 0x00200000
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_rv9_disable_SHIFT 21
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_rv9_disable_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: reserved0 [20:13] */
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_reserved0_MASK 0x001fe000
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_reserved0_SHIFT 13
-
-/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_hvd0_disable [12:12] */
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_hvd0_disable_MASK 0x00001000
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_hvd0_disable_SHIFT 12
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_hvd0_disable_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: reserved1 [11:11] */
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_reserved1_MASK 0x00000800
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_reserved1_SHIFT 11
-
-/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_vice2_0_disable [10:10] */
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_vice2_0_disable_MASK 0x00000400
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_vice2_0_disable_SHIFT 10
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_vice2_0_disable_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_avs_disable [09:09] */
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_avs_disable_MASK 0x00000200
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_avs_disable_SHIFT 9
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_avs_disable_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_audio_spdif_disable [08:08] */
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_audio_spdif_disable_MASK 0x00000100
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_audio_spdif_disable_SHIFT 8
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_audio_spdif_disable_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_en_testport [07:07] */
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_en_testport_MASK 0x00000080
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_en_testport_SHIFT 7
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_en_testport_DEFAULT 0x00000001
-
-/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_en_cr [06:05] */
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_en_cr_MASK 0x00000060
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_en_cr_SHIFT 5
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_en_cr_DEFAULT 0x00000003
-
-/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_rave_verify_enable [04:04] */
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_rave_verify_enable_MASK 0x00000010
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_rave_verify_enable_SHIFT 4
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_rave_verify_enable_DEFAULT 0x00000001
-
-/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_bsp_spares [03:00] */
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_bsp_spares_MASK 0x0000000f
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_bsp_spares_SHIFT 0
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_bsp_spares_DEFAULT 0x00000000
-
-/***************************************************************************
- *OTP_OPTION_TEST_1 - OTP option test register
- ***************************************************************************/
-/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_24 [31:31] */
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_24_MASK 0x80000000
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_24_SHIFT 31
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_24_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_23 [30:30] */
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_23_MASK 0x40000000
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_23_SHIFT 30
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_23_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_22 [29:29] */
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_22_MASK 0x20000000
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_22_SHIFT 29
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_22_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_21 [28:28] */
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_21_MASK 0x10000000
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_21_SHIFT 28
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_21_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_20 [27:27] */
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_20_MASK 0x08000000
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_20_SHIFT 27
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_20_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_19 [26:26] */
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_19_MASK 0x04000000
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_19_SHIFT 26
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_19_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_18 [25:25] */
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_18_MASK 0x02000000
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_18_SHIFT 25
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_18_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_17 [24:24] */
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_17_MASK 0x01000000
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_17_SHIFT 24
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_17_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_16 [23:23] */
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_16_MASK 0x00800000
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_16_SHIFT 23
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_16_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_15 [22:22] */
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_15_MASK 0x00400000
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_15_SHIFT 22
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_15_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_14 [21:21] */
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_14_MASK 0x00200000
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_14_SHIFT 21
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_14_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_13 [20:20] */
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_13_MASK 0x00100000
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_13_SHIFT 20
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_13_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_12 [19:19] */
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_12_MASK 0x00080000
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_12_SHIFT 19
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_12_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_11 [18:18] */
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_11_MASK 0x00040000
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_11_SHIFT 18
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_11_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_10 [17:17] */
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_10_MASK 0x00020000
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_10_SHIFT 17
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_10_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_9 [16:16] */
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_9_MASK 0x00010000
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_9_SHIFT 16
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_9_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_8 [15:15] */
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_8_MASK 0x00008000
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_8_SHIFT 15
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_8_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_7 [14:14] */
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_7_MASK 0x00004000
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_7_SHIFT 14
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_7_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_6 [13:13] */
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_6_MASK 0x00002000
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_6_SHIFT 13
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_6_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_5 [12:12] */
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_5_MASK 0x00001000
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_5_SHIFT 12
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_5_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_4 [11:11] */
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_4_MASK 0x00000800
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_4_SHIFT 11
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_4_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_3 [10:10] */
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_3_MASK 0x00000400
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_3_SHIFT 10
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_3_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_2 [09:09] */
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_2_MASK 0x00000200
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_2_SHIFT 9
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_2_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_1 [08:08] */
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_1_MASK 0x00000100
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_1_SHIFT 8
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_1_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_0 [07:07] */
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_0_MASK 0x00000080
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_0_SHIFT 7
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_0_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_usb1_disable [06:06] */
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_usb1_disable_MASK 0x00000040
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_usb1_disable_SHIFT 6
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_usb1_disable_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_usb0_disable [05:05] */
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_usb0_disable_MASK 0x00000020
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_usb0_disable_SHIFT 5
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_usb0_disable_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_usb2_disable [04:04] */
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_usb2_disable_MASK 0x00000010
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_usb2_disable_SHIFT 4
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_usb2_disable_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_usb3_disable [03:03] */
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_usb3_disable_MASK 0x00000008
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_usb3_disable_SHIFT 3
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_usb3_disable_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_moca2_disable [02:02] */
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_moca2_disable_MASK 0x00000004
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_moca2_disable_SHIFT 2
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_moca2_disable_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_rfm_disable [01:01] */
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_rfm_disable_MASK 0x00000002
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_rfm_disable_SHIFT 1
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_rfm_disable_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_hdmi_tx1_disable [00:00] */
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_hdmi_tx1_disable_MASK 0x00000001
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_hdmi_tx1_disable_SHIFT 0
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_hdmi_tx1_disable_DEFAULT 0x00000000
-
-/***************************************************************************
- *OTP_OPTION_STATUS_0 - OTP option status register
- ***************************************************************************/
-/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_pcie0_disable [31:31] */
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_pcie0_disable_MASK 0x80000000
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_pcie0_disable_SHIFT 31
-
-/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_moca_disable [30:30] */
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_moca_disable_MASK 0x40000000
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_moca_disable_SHIFT 30
-
-/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_av_output_disable [29:29] */
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_av_output_disable_MASK 0x20000000
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_av_output_disable_SHIFT 29
-
-/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_vc4_disable [28:28] */
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_vc4_disable_MASK 0x10000000
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_vc4_disable_SHIFT 28
-
-/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_4kx2k_disable [27:27] */
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_4kx2k_disable_MASK 0x08000000
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_4kx2k_disable_SHIFT 27
-
-/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_sata_disable [26:26] */
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_sata_disable_MASK 0x04000000
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_sata_disable_SHIFT 26
-
-/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_macrovision_disable [25:25] */
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_macrovision_disable_MASK 0x02000000
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_macrovision_disable_SHIFT 25
-
-/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_hdcp_disable [24:24] */
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_hdcp_disable_MASK 0x01000000
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_hdcp_disable_SHIFT 24
-
-/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_hdmi_pass_thru_disable [23:23] */
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_hdmi_pass_thru_disable_MASK 0x00800000
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_hdmi_pass_thru_disable_SHIFT 23
-
-/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_hdmi_rx_disable [22:22] */
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_hdmi_rx_disable_MASK 0x00400000
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_hdmi_rx_disable_SHIFT 22
-
-/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_rv9_disable [21:21] */
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_rv9_disable_MASK 0x00200000
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_rv9_disable_SHIFT 21
-
-/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: reserved0 [20:13] */
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_reserved0_MASK 0x001fe000
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_reserved0_SHIFT 13
-
-/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_hvd0_disable [12:12] */
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_hvd0_disable_MASK 0x00001000
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_hvd0_disable_SHIFT 12
-
-/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: reserved1 [11:11] */
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_reserved1_MASK 0x00000800
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_reserved1_SHIFT 11
-
-/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_vice2_0_disable [10:10] */
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_vice2_0_disable_MASK 0x00000400
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_vice2_0_disable_SHIFT 10
-
-/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_avs_disable [09:09] */
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_avs_disable_MASK 0x00000200
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_avs_disable_SHIFT 9
-
-/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_audio_spdif_disable [08:08] */
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_audio_spdif_disable_MASK 0x00000100
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_audio_spdif_disable_SHIFT 8
-
-/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_en_testport [07:07] */
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_en_testport_MASK 0x00000080
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_en_testport_SHIFT 7
-
-/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_en_cr [06:05] */
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_en_cr_MASK 0x00000060
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_en_cr_SHIFT 5
-
-/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_rave_verify_enable [04:04] */
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_rave_verify_enable_MASK 0x00000010
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_rave_verify_enable_SHIFT 4
-
-/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_bsp_spares [03:00] */
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_bsp_spares_MASK 0x0000000f
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_bsp_spares_SHIFT 0
-
-/***************************************************************************
- *OTP_OPTION_STATUS_1 - OTP option status register
- ***************************************************************************/
-/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_24 [31:31] */
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_24_MASK 0x80000000
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_24_SHIFT 31
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_24_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_23 [30:30] */
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_23_MASK 0x40000000
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_23_SHIFT 30
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_23_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_22 [29:29] */
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_22_MASK 0x20000000
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_22_SHIFT 29
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_22_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_21 [28:28] */
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_21_MASK 0x10000000
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_21_SHIFT 28
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_21_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_20 [27:27] */
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_20_MASK 0x08000000
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_20_SHIFT 27
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_20_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_19 [26:26] */
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_19_MASK 0x04000000
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_19_SHIFT 26
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_19_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_18 [25:25] */
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_18_MASK 0x02000000
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_18_SHIFT 25
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_18_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_17 [24:24] */
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_17_MASK 0x01000000
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_17_SHIFT 24
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_17_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_16 [23:23] */
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_16_MASK 0x00800000
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_16_SHIFT 23
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_16_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_15 [22:22] */
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_15_MASK 0x00400000
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_15_SHIFT 22
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_15_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_14 [21:21] */
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_14_MASK 0x00200000
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_14_SHIFT 21
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_14_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_13 [20:20] */
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_13_MASK 0x00100000
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_13_SHIFT 20
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_13_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_12 [19:19] */
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_12_MASK 0x00080000
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_12_SHIFT 19
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_12_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_11 [18:18] */
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_11_MASK 0x00040000
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_11_SHIFT 18
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_11_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_10 [17:17] */
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_10_MASK 0x00020000
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_10_SHIFT 17
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_10_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_9 [16:16] */
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_9_MASK 0x00010000
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_9_SHIFT 16
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_9_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_8 [15:15] */
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_8_MASK 0x00008000
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_8_SHIFT 15
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_8_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_7 [14:14] */
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_7_MASK 0x00004000
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_7_SHIFT 14
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_7_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_6 [13:13] */
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_6_MASK 0x00002000
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_6_SHIFT 13
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_6_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_5 [12:12] */
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_5_MASK 0x00001000
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_5_SHIFT 12
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_5_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_4 [11:11] */
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_4_MASK 0x00000800
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_4_SHIFT 11
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_4_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_3 [10:10] */
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_3_MASK 0x00000400
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_3_SHIFT 10
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_3_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_2 [09:09] */
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_2_MASK 0x00000200
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_2_SHIFT 9
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_2_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_1 [08:08] */
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_1_MASK 0x00000100
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_1_SHIFT 8
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_1_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_0 [07:07] */
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_0_MASK 0x00000080
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_0_SHIFT 7
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_0_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_usb1_disable [06:06] */
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_usb1_disable_MASK 0x00000040
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_usb1_disable_SHIFT 6
-
-/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_usb0_disable [05:05] */
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_usb0_disable_MASK 0x00000020
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_usb0_disable_SHIFT 5
-
-/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_usb2_disable [04:04] */
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_usb2_disable_MASK 0x00000010
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_usb2_disable_SHIFT 4
-
-/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_usb3_disable [03:03] */
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_usb3_disable_MASK 0x00000008
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_usb3_disable_SHIFT 3
-
-/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_moca2_disable [02:02] */
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_moca2_disable_MASK 0x00000004
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_moca2_disable_SHIFT 2
-
-/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_rfm_disable [01:01] */
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_rfm_disable_MASK 0x00000002
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_rfm_disable_SHIFT 1
-
-/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_hdmi_tx1_disable [00:00] */
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_hdmi_tx1_disable_MASK 0x00000001
-#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_hdmi_tx1_disable_SHIFT 0
-
-/***************************************************************************
- *SEMAPHORE_0 - Semaphore channel 0
- ***************************************************************************/
-/* SUN_TOP_CTRL :: SEMAPHORE_0 :: reserved0 [31:08] */
-#define BCHP_SUN_TOP_CTRL_SEMAPHORE_0_reserved0_MASK 0xffffff00
-#define BCHP_SUN_TOP_CTRL_SEMAPHORE_0_reserved0_SHIFT 8
-
-/* SUN_TOP_CTRL :: SEMAPHORE_0 :: semaphore_ctrl [07:00] */
-#define BCHP_SUN_TOP_CTRL_SEMAPHORE_0_semaphore_ctrl_MASK 0x000000ff
-#define BCHP_SUN_TOP_CTRL_SEMAPHORE_0_semaphore_ctrl_SHIFT 0
-#define BCHP_SUN_TOP_CTRL_SEMAPHORE_0_semaphore_ctrl_DEFAULT 0x00000000
-
-/***************************************************************************
- *SEMAPHORE_1 - Semaphore channel 1
- ***************************************************************************/
-/* SUN_TOP_CTRL :: SEMAPHORE_1 :: reserved0 [31:08] */
-#define BCHP_SUN_TOP_CTRL_SEMAPHORE_1_reserved0_MASK 0xffffff00
-#define BCHP_SUN_TOP_CTRL_SEMAPHORE_1_reserved0_SHIFT 8
-
-/* SUN_TOP_CTRL :: SEMAPHORE_1 :: semaphore_ctrl [07:00] */
-#define BCHP_SUN_TOP_CTRL_SEMAPHORE_1_semaphore_ctrl_MASK 0x000000ff
-#define BCHP_SUN_TOP_CTRL_SEMAPHORE_1_semaphore_ctrl_SHIFT 0
-#define BCHP_SUN_TOP_CTRL_SEMAPHORE_1_semaphore_ctrl_DEFAULT 0x00000000
-
-/***************************************************************************
- *SEMAPHORE_2 - Semaphore channel 2
- ***************************************************************************/
-/* SUN_TOP_CTRL :: SEMAPHORE_2 :: reserved0 [31:08] */
-#define BCHP_SUN_TOP_CTRL_SEMAPHORE_2_reserved0_MASK 0xffffff00
-#define BCHP_SUN_TOP_CTRL_SEMAPHORE_2_reserved0_SHIFT 8
-
-/* SUN_TOP_CTRL :: SEMAPHORE_2 :: semaphore_ctrl [07:00] */
-#define BCHP_SUN_TOP_CTRL_SEMAPHORE_2_semaphore_ctrl_MASK 0x000000ff
-#define BCHP_SUN_TOP_CTRL_SEMAPHORE_2_semaphore_ctrl_SHIFT 0
-#define BCHP_SUN_TOP_CTRL_SEMAPHORE_2_semaphore_ctrl_DEFAULT 0x00000000
-
-/***************************************************************************
- *SEMAPHORE_3 - Semaphore channel 3
- ***************************************************************************/
-/* SUN_TOP_CTRL :: SEMAPHORE_3 :: reserved0 [31:08] */
-#define BCHP_SUN_TOP_CTRL_SEMAPHORE_3_reserved0_MASK 0xffffff00
-#define BCHP_SUN_TOP_CTRL_SEMAPHORE_3_reserved0_SHIFT 8
-
-/* SUN_TOP_CTRL :: SEMAPHORE_3 :: semaphore_ctrl [07:00] */
-#define BCHP_SUN_TOP_CTRL_SEMAPHORE_3_semaphore_ctrl_MASK 0x000000ff
-#define BCHP_SUN_TOP_CTRL_SEMAPHORE_3_semaphore_ctrl_SHIFT 0
-#define BCHP_SUN_TOP_CTRL_SEMAPHORE_3_semaphore_ctrl_DEFAULT 0x00000000
-
-/***************************************************************************
- *SEMAPHORE_4 - Semaphore channel 4
- ***************************************************************************/
-/* SUN_TOP_CTRL :: SEMAPHORE_4 :: reserved0 [31:08] */
-#define BCHP_SUN_TOP_CTRL_SEMAPHORE_4_reserved0_MASK 0xffffff00
-#define BCHP_SUN_TOP_CTRL_SEMAPHORE_4_reserved0_SHIFT 8
-
-/* SUN_TOP_CTRL :: SEMAPHORE_4 :: semaphore_ctrl [07:00] */
-#define BCHP_SUN_TOP_CTRL_SEMAPHORE_4_semaphore_ctrl_MASK 0x000000ff
-#define BCHP_SUN_TOP_CTRL_SEMAPHORE_4_semaphore_ctrl_SHIFT 0
-#define BCHP_SUN_TOP_CTRL_SEMAPHORE_4_semaphore_ctrl_DEFAULT 0x00000000
-
-/***************************************************************************
- *SEMAPHORE_5 - Semaphore channel 5
- ***************************************************************************/
-/* SUN_TOP_CTRL :: SEMAPHORE_5 :: reserved0 [31:08] */
-#define BCHP_SUN_TOP_CTRL_SEMAPHORE_5_reserved0_MASK 0xffffff00
-#define BCHP_SUN_TOP_CTRL_SEMAPHORE_5_reserved0_SHIFT 8
-
-/* SUN_TOP_CTRL :: SEMAPHORE_5 :: semaphore_ctrl [07:00] */
-#define BCHP_SUN_TOP_CTRL_SEMAPHORE_5_semaphore_ctrl_MASK 0x000000ff
-#define BCHP_SUN_TOP_CTRL_SEMAPHORE_5_semaphore_ctrl_SHIFT 0
-#define BCHP_SUN_TOP_CTRL_SEMAPHORE_5_semaphore_ctrl_DEFAULT 0x00000000
-
-/***************************************************************************
- *SEMAPHORE_6 - Semaphore channel 6
- ***************************************************************************/
-/* SUN_TOP_CTRL :: SEMAPHORE_6 :: reserved0 [31:08] */
-#define BCHP_SUN_TOP_CTRL_SEMAPHORE_6_reserved0_MASK 0xffffff00
-#define BCHP_SUN_TOP_CTRL_SEMAPHORE_6_reserved0_SHIFT 8
-
-/* SUN_TOP_CTRL :: SEMAPHORE_6 :: semaphore_ctrl [07:00] */
-#define BCHP_SUN_TOP_CTRL_SEMAPHORE_6_semaphore_ctrl_MASK 0x000000ff
-#define BCHP_SUN_TOP_CTRL_SEMAPHORE_6_semaphore_ctrl_SHIFT 0
-#define BCHP_SUN_TOP_CTRL_SEMAPHORE_6_semaphore_ctrl_DEFAULT 0x00000000
-
-/***************************************************************************
- *SEMAPHORE_7 - Semaphore channel 7
- ***************************************************************************/
-/* SUN_TOP_CTRL :: SEMAPHORE_7 :: reserved0 [31:08] */
-#define BCHP_SUN_TOP_CTRL_SEMAPHORE_7_reserved0_MASK 0xffffff00
-#define BCHP_SUN_TOP_CTRL_SEMAPHORE_7_reserved0_SHIFT 8
-
-/* SUN_TOP_CTRL :: SEMAPHORE_7 :: semaphore_ctrl [07:00] */
-#define BCHP_SUN_TOP_CTRL_SEMAPHORE_7_semaphore_ctrl_MASK 0x000000ff
-#define BCHP_SUN_TOP_CTRL_SEMAPHORE_7_semaphore_ctrl_SHIFT 0
-#define BCHP_SUN_TOP_CTRL_SEMAPHORE_7_semaphore_ctrl_DEFAULT 0x00000000
-
-/***************************************************************************
- *SEMAPHORE_8 - Semaphore channel 8
- ***************************************************************************/
-/* SUN_TOP_CTRL :: SEMAPHORE_8 :: reserved0 [31:08] */
-#define BCHP_SUN_TOP_CTRL_SEMAPHORE_8_reserved0_MASK 0xffffff00
-#define BCHP_SUN_TOP_CTRL_SEMAPHORE_8_reserved0_SHIFT 8
-
-/* SUN_TOP_CTRL :: SEMAPHORE_8 :: semaphore_ctrl [07:00] */
-#define BCHP_SUN_TOP_CTRL_SEMAPHORE_8_semaphore_ctrl_MASK 0x000000ff
-#define BCHP_SUN_TOP_CTRL_SEMAPHORE_8_semaphore_ctrl_SHIFT 0
-#define BCHP_SUN_TOP_CTRL_SEMAPHORE_8_semaphore_ctrl_DEFAULT 0x00000000
-
-/***************************************************************************
- *SEMAPHORE_9 - Semaphore channel 9
- ***************************************************************************/
-/* SUN_TOP_CTRL :: SEMAPHORE_9 :: reserved0 [31:08] */
-#define BCHP_SUN_TOP_CTRL_SEMAPHORE_9_reserved0_MASK 0xffffff00
-#define BCHP_SUN_TOP_CTRL_SEMAPHORE_9_reserved0_SHIFT 8
-
-/* SUN_TOP_CTRL :: SEMAPHORE_9 :: semaphore_ctrl [07:00] */
-#define BCHP_SUN_TOP_CTRL_SEMAPHORE_9_semaphore_ctrl_MASK 0x000000ff
-#define BCHP_SUN_TOP_CTRL_SEMAPHORE_9_semaphore_ctrl_SHIFT 0
-#define BCHP_SUN_TOP_CTRL_SEMAPHORE_9_semaphore_ctrl_DEFAULT 0x00000000
-
-/***************************************************************************
- *SEMAPHORE_10 - Semaphore channel 10
- ***************************************************************************/
-/* SUN_TOP_CTRL :: SEMAPHORE_10 :: reserved0 [31:08] */
-#define BCHP_SUN_TOP_CTRL_SEMAPHORE_10_reserved0_MASK 0xffffff00
-#define BCHP_SUN_TOP_CTRL_SEMAPHORE_10_reserved0_SHIFT 8
-
-/* SUN_TOP_CTRL :: SEMAPHORE_10 :: semaphore_ctrl [07:00] */
-#define BCHP_SUN_TOP_CTRL_SEMAPHORE_10_semaphore_ctrl_MASK 0x000000ff
-#define BCHP_SUN_TOP_CTRL_SEMAPHORE_10_semaphore_ctrl_SHIFT 0
-#define BCHP_SUN_TOP_CTRL_SEMAPHORE_10_semaphore_ctrl_DEFAULT 0x00000000
-
-/***************************************************************************
- *SEMAPHORE_11 - Semaphore channel 11
- ***************************************************************************/
-/* SUN_TOP_CTRL :: SEMAPHORE_11 :: reserved0 [31:08] */
-#define BCHP_SUN_TOP_CTRL_SEMAPHORE_11_reserved0_MASK 0xffffff00
-#define BCHP_SUN_TOP_CTRL_SEMAPHORE_11_reserved0_SHIFT 8
-
-/* SUN_TOP_CTRL :: SEMAPHORE_11 :: semaphore_ctrl [07:00] */
-#define BCHP_SUN_TOP_CTRL_SEMAPHORE_11_semaphore_ctrl_MASK 0x000000ff
-#define BCHP_SUN_TOP_CTRL_SEMAPHORE_11_semaphore_ctrl_SHIFT 0
-#define BCHP_SUN_TOP_CTRL_SEMAPHORE_11_semaphore_ctrl_DEFAULT 0x00000000
-
-/***************************************************************************
- *SEMAPHORE_12 - Semaphore channel 12
- ***************************************************************************/
-/* SUN_TOP_CTRL :: SEMAPHORE_12 :: reserved0 [31:08] */
-#define BCHP_SUN_TOP_CTRL_SEMAPHORE_12_reserved0_MASK 0xffffff00
-#define BCHP_SUN_TOP_CTRL_SEMAPHORE_12_reserved0_SHIFT 8
-
-/* SUN_TOP_CTRL :: SEMAPHORE_12 :: semaphore_ctrl [07:00] */
-#define BCHP_SUN_TOP_CTRL_SEMAPHORE_12_semaphore_ctrl_MASK 0x000000ff
-#define BCHP_SUN_TOP_CTRL_SEMAPHORE_12_semaphore_ctrl_SHIFT 0
-#define BCHP_SUN_TOP_CTRL_SEMAPHORE_12_semaphore_ctrl_DEFAULT 0x00000000
-
-/***************************************************************************
- *SEMAPHORE_13 - Semaphore channel 13
- ***************************************************************************/
-/* SUN_TOP_CTRL :: SEMAPHORE_13 :: reserved0 [31:08] */
-#define BCHP_SUN_TOP_CTRL_SEMAPHORE_13_reserved0_MASK 0xffffff00
-#define BCHP_SUN_TOP_CTRL_SEMAPHORE_13_reserved0_SHIFT 8
-
-/* SUN_TOP_CTRL :: SEMAPHORE_13 :: semaphore_ctrl [07:00] */
-#define BCHP_SUN_TOP_CTRL_SEMAPHORE_13_semaphore_ctrl_MASK 0x000000ff
-#define BCHP_SUN_TOP_CTRL_SEMAPHORE_13_semaphore_ctrl_SHIFT 0
-#define BCHP_SUN_TOP_CTRL_SEMAPHORE_13_semaphore_ctrl_DEFAULT 0x00000000
-
-/***************************************************************************
- *SEMAPHORE_14 - Semaphore channel 14
- ***************************************************************************/
-/* SUN_TOP_CTRL :: SEMAPHORE_14 :: reserved0 [31:08] */
-#define BCHP_SUN_TOP_CTRL_SEMAPHORE_14_reserved0_MASK 0xffffff00
-#define BCHP_SUN_TOP_CTRL_SEMAPHORE_14_reserved0_SHIFT 8
-
-/* SUN_TOP_CTRL :: SEMAPHORE_14 :: semaphore_ctrl [07:00] */
-#define BCHP_SUN_TOP_CTRL_SEMAPHORE_14_semaphore_ctrl_MASK 0x000000ff
-#define BCHP_SUN_TOP_CTRL_SEMAPHORE_14_semaphore_ctrl_SHIFT 0
-#define BCHP_SUN_TOP_CTRL_SEMAPHORE_14_semaphore_ctrl_DEFAULT 0x00000000
-
-/***************************************************************************
- *SEMAPHORE_15 - Semaphore channel 15
- ***************************************************************************/
-/* SUN_TOP_CTRL :: SEMAPHORE_15 :: reserved0 [31:08] */
-#define BCHP_SUN_TOP_CTRL_SEMAPHORE_15_reserved0_MASK 0xffffff00
-#define BCHP_SUN_TOP_CTRL_SEMAPHORE_15_reserved0_SHIFT 8
-
-/* SUN_TOP_CTRL :: SEMAPHORE_15 :: semaphore_ctrl [07:00] */
-#define BCHP_SUN_TOP_CTRL_SEMAPHORE_15_semaphore_ctrl_MASK 0x000000ff
-#define BCHP_SUN_TOP_CTRL_SEMAPHORE_15_semaphore_ctrl_SHIFT 0
-#define BCHP_SUN_TOP_CTRL_SEMAPHORE_15_semaphore_ctrl_DEFAULT 0x00000000
-
-/***************************************************************************
- *GEN_WATCHDOG_0 - General watchdog timer 0
- ***************************************************************************/
-/* SUN_TOP_CTRL :: GEN_WATCHDOG_0 :: watchdog_timeout_value [31:00] */
-#define BCHP_SUN_TOP_CTRL_GEN_WATCHDOG_0_watchdog_timeout_value_MASK 0xffffffff
-#define BCHP_SUN_TOP_CTRL_GEN_WATCHDOG_0_watchdog_timeout_value_SHIFT 0
-#define BCHP_SUN_TOP_CTRL_GEN_WATCHDOG_0_watchdog_timeout_value_DEFAULT 0x00000000
-
-/***************************************************************************
- *GEN_WATCHDOG_1 - General watchdog timer 1
- ***************************************************************************/
-/* SUN_TOP_CTRL :: GEN_WATCHDOG_1 :: watchdog_timeout_value [31:00] */
-#define BCHP_SUN_TOP_CTRL_GEN_WATCHDOG_1_watchdog_timeout_value_MASK 0xffffffff
-#define BCHP_SUN_TOP_CTRL_GEN_WATCHDOG_1_watchdog_timeout_value_SHIFT 0
-#define BCHP_SUN_TOP_CTRL_GEN_WATCHDOG_1_watchdog_timeout_value_DEFAULT 0x00000000
-
-/***************************************************************************
- *GENERAL_CTRL_0 - General control register 0
- ***************************************************************************/
-/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_31 [31:31] */
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_31_MASK 0x80000000
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_31_SHIFT 31
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_31_DEFAULT 0x00000001
-
-/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_30 [30:30] */
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_30_MASK 0x40000000
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_30_SHIFT 30
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_30_DEFAULT 0x00000001
-
-/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_29 [29:29] */
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_29_MASK 0x20000000
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_29_SHIFT 29
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_29_DEFAULT 0x00000001
-
-/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_28 [28:28] */
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_28_MASK 0x10000000
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_28_SHIFT 28
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_28_DEFAULT 0x00000001
-
-/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_27 [27:27] */
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_27_MASK 0x08000000
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_27_SHIFT 27
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_27_DEFAULT 0x00000001
-
-/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_26 [26:26] */
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_26_MASK 0x04000000
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_26_SHIFT 26
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_26_DEFAULT 0x00000001
-
-/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_25 [25:25] */
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_25_MASK 0x02000000
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_25_SHIFT 25
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_25_DEFAULT 0x00000001
-
-/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_24 [24:24] */
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_24_MASK 0x01000000
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_24_SHIFT 24
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_24_DEFAULT 0x00000001
-
-/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_23 [23:23] */
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_23_MASK 0x00800000
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_23_SHIFT 23
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_23_DEFAULT 0x00000001
-
-/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_22 [22:22] */
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_22_MASK 0x00400000
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_22_SHIFT 22
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_22_DEFAULT 0x00000001
-
-/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_21 [21:21] */
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_21_MASK 0x00200000
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_21_SHIFT 21
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_21_DEFAULT 0x00000001
-
-/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_20 [20:20] */
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_20_MASK 0x00100000
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_20_SHIFT 20
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_20_DEFAULT 0x00000001
-
-/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_19 [19:19] */
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_19_MASK 0x00080000
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_19_SHIFT 19
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_19_DEFAULT 0x00000001
-
-/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_18 [18:18] */
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_18_MASK 0x00040000
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_18_SHIFT 18
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_18_DEFAULT 0x00000001
-
-/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_17 [17:17] */
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_17_MASK 0x00020000
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_17_SHIFT 17
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_17_DEFAULT 0x00000001
-
-/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_16 [16:16] */
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_16_MASK 0x00010000
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_16_SHIFT 16
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_16_DEFAULT 0x00000001
-
-/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_15 [15:15] */
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_15_MASK 0x00008000
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_15_SHIFT 15
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_15_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_14 [14:14] */
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_14_MASK 0x00004000
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_14_SHIFT 14
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_14_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_13 [13:13] */
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_13_MASK 0x00002000
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_13_SHIFT 13
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_13_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_12 [12:12] */
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_12_MASK 0x00001000
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_12_SHIFT 12
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_12_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_11 [11:11] */
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_11_MASK 0x00000800
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_11_SHIFT 11
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_11_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_10 [10:10] */
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_10_MASK 0x00000400
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_10_SHIFT 10
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_10_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_9 [09:09] */
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_9_MASK 0x00000200
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_9_SHIFT 9
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_9_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_8 [08:08] */
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_8_MASK 0x00000100
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_8_SHIFT 8
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_8_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_7 [07:07] */
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_7_MASK 0x00000080
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_7_SHIFT 7
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_7_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: ana_detect_sdio_1_pd [06:06] */
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_ana_detect_sdio_1_pd_MASK 0x00000040
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_ana_detect_sdio_1_pd_SHIFT 6
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_ana_detect_sdio_1_pd_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: ana_detect_sdio_0_pd [05:05] */
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_ana_detect_sdio_0_pd_MASK 0x00000020
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_ana_detect_sdio_0_pd_SHIFT 5
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_ana_detect_sdio_0_pd_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: sdio_1_pad_modehv_override [04:04] */
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_sdio_1_pad_modehv_override_MASK 0x00000010
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_sdio_1_pad_modehv_override_SHIFT 4
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_sdio_1_pad_modehv_override_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: sdio_0_pad_modehv_override [03:03] */
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_sdio_0_pad_modehv_override_MASK 0x00000008
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_sdio_0_pad_modehv_override_SHIFT 3
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_sdio_0_pad_modehv_override_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: sdio1_pin_sel [02:01] */
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_sdio1_pin_sel_MASK 0x00000006
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_sdio1_pin_sel_SHIFT 1
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_sdio1_pin_sel_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: rgmii_swap [00:00] */
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_rgmii_swap_MASK 0x00000001
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_rgmii_swap_SHIFT 0
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_rgmii_swap_DEFAULT 0x00000000
-
-/***************************************************************************
- *GENERAL_CTRL_1 - General control register 1
- ***************************************************************************/
-/* SUN_TOP_CTRL :: GENERAL_CTRL_1 :: reserved0 [31:02] */
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_reserved0_MASK 0xfffffffc
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_reserved0_SHIFT 2
-
-/* SUN_TOP_CTRL :: GENERAL_CTRL_1 :: general_ctrl1_1 [01:01] */
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_1_MASK 0x00000002
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_1_SHIFT 1
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_1_DEFAULT 0x00000001
-
-/* SUN_TOP_CTRL :: GENERAL_CTRL_1 :: general_ctrl1_0 [00:00] */
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_0_MASK 0x00000001
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_0_SHIFT 0
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_0_DEFAULT 0x00000000
-
-/***************************************************************************
- *GENERAL_CTRL_2 - General control register 2
- ***************************************************************************/
-/* SUN_TOP_CTRL :: GENERAL_CTRL_2 :: reserved0 [31:02] */
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_2_reserved0_MASK 0xfffffffc
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_2_reserved0_SHIFT 2
-
-/* SUN_TOP_CTRL :: GENERAL_CTRL_2 :: general_ctrl2_1 [01:01] */
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_2_general_ctrl2_1_MASK 0x00000002
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_2_general_ctrl2_1_SHIFT 1
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_2_general_ctrl2_1_DEFAULT 0x00000001
-
-/* SUN_TOP_CTRL :: GENERAL_CTRL_2 :: general_ctrl2_0 [00:00] */
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_2_general_ctrl2_0_MASK 0x00000001
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_2_general_ctrl2_0_SHIFT 0
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_2_general_ctrl2_0_DEFAULT 0x00000000
-
-/***************************************************************************
- *GENERAL_CTRL_3 - General control register 3
- ***************************************************************************/
-/* SUN_TOP_CTRL :: GENERAL_CTRL_3 :: reserved0 [31:02] */
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_3_reserved0_MASK 0xfffffffc
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_3_reserved0_SHIFT 2
-
-/* SUN_TOP_CTRL :: GENERAL_CTRL_3 :: general_ctrl3_1 [01:01] */
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_3_general_ctrl3_1_MASK 0x00000002
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_3_general_ctrl3_1_SHIFT 1
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_3_general_ctrl3_1_DEFAULT 0x00000001
-
-/* SUN_TOP_CTRL :: GENERAL_CTRL_3 :: general_ctrl3_0 [00:00] */
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_3_general_ctrl3_0_MASK 0x00000001
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_3_general_ctrl3_0_SHIFT 0
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_3_general_ctrl3_0_DEFAULT 0x00000000
-
-/***************************************************************************
- *GENERAL_CTRL_4 - General control register 4
- ***************************************************************************/
-/* SUN_TOP_CTRL :: GENERAL_CTRL_4 :: reserved0 [31:02] */
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_4_reserved0_MASK 0xfffffffc
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_4_reserved0_SHIFT 2
-
-/* SUN_TOP_CTRL :: GENERAL_CTRL_4 :: general_ctrl4_1 [01:01] */
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_4_general_ctrl4_1_MASK 0x00000002
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_4_general_ctrl4_1_SHIFT 1
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_4_general_ctrl4_1_DEFAULT 0x00000001
-
-/* SUN_TOP_CTRL :: GENERAL_CTRL_4 :: general_ctrl4_0 [00:00] */
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_4_general_ctrl4_0_MASK 0x00000001
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_4_general_ctrl4_0_SHIFT 0
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_4_general_ctrl4_0_DEFAULT 0x00000000
-
-/***************************************************************************
- *GENERAL_CTRL_5 - General control register 5
- ***************************************************************************/
-/* SUN_TOP_CTRL :: GENERAL_CTRL_5 :: reserved0 [31:02] */
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_5_reserved0_MASK 0xfffffffc
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_5_reserved0_SHIFT 2
-
-/* SUN_TOP_CTRL :: GENERAL_CTRL_5 :: general_ctrl5_1 [01:01] */
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_5_general_ctrl5_1_MASK 0x00000002
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_5_general_ctrl5_1_SHIFT 1
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_5_general_ctrl5_1_DEFAULT 0x00000001
-
-/* SUN_TOP_CTRL :: GENERAL_CTRL_5 :: general_ctrl5_0 [00:00] */
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_5_general_ctrl5_0_MASK 0x00000001
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_5_general_ctrl5_0_SHIFT 0
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_5_general_ctrl5_0_DEFAULT 0x00000000
-
-/***************************************************************************
- *GENERAL_STATUS_0 - General status register 0
- ***************************************************************************/
-/* SUN_TOP_CTRL :: GENERAL_STATUS_0 :: reserved0 [31:08] */
-#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0_reserved0_MASK 0xffffff00
-#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0_reserved0_SHIFT 8
-
-/* SUN_TOP_CTRL :: GENERAL_STATUS_0 :: general_status0_7 [07:07] */
-#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0_general_status0_7_MASK 0x00000080
-#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0_general_status0_7_SHIFT 7
-
-/* SUN_TOP_CTRL :: GENERAL_STATUS_0 :: general_status0_6 [06:06] */
-#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0_general_status0_6_MASK 0x00000040
-#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0_general_status0_6_SHIFT 6
-
-/* SUN_TOP_CTRL :: GENERAL_STATUS_0 :: general_status0_5 [05:05] */
-#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0_general_status0_5_MASK 0x00000020
-#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0_general_status0_5_SHIFT 5
-
-/* SUN_TOP_CTRL :: GENERAL_STATUS_0 :: general_status0_4 [04:04] */
-#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0_general_status0_4_MASK 0x00000010
-#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0_general_status0_4_SHIFT 4
-
-/* SUN_TOP_CTRL :: GENERAL_STATUS_0 :: general_status0_3 [03:03] */
-#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0_general_status0_3_MASK 0x00000008
-#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0_general_status0_3_SHIFT 3
-
-/* SUN_TOP_CTRL :: GENERAL_STATUS_0 :: general_status0_2 [02:02] */
-#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0_general_status0_2_MASK 0x00000004
-#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0_general_status0_2_SHIFT 2
-
-/* SUN_TOP_CTRL :: GENERAL_STATUS_0 :: ebi_pad_config [01:01] */
-#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0_ebi_pad_config_MASK 0x00000002
-#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0_ebi_pad_config_SHIFT 1
-
-/* SUN_TOP_CTRL :: GENERAL_STATUS_0 :: hif_strap_invalid [00:00] */
-#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0_hif_strap_invalid_MASK 0x00000001
-#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0_hif_strap_invalid_SHIFT 0
-
-/***************************************************************************
- *GENERAL_STATUS_1 - General status register 1
- ***************************************************************************/
-/* SUN_TOP_CTRL :: GENERAL_STATUS_1 :: reserved0 [31:02] */
-#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_1_reserved0_MASK 0xfffffffc
-#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_1_reserved0_SHIFT 2
-
-/* SUN_TOP_CTRL :: GENERAL_STATUS_1 :: sdio_1_pad_vddo [01:01] */
-#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_1_sdio_1_pad_vddo_MASK 0x00000002
-#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_1_sdio_1_pad_vddo_SHIFT 1
-
-/* SUN_TOP_CTRL :: GENERAL_STATUS_1 :: sdio_0_pad_vddo [00:00] */
-#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_1_sdio_0_pad_vddo_MASK 0x00000001
-#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_1_sdio_0_pad_vddo_SHIFT 0
-
-/***************************************************************************
- *GENERAL_STATUS_2 - General status register 2
- ***************************************************************************/
-/* SUN_TOP_CTRL :: GENERAL_STATUS_2 :: reserved0 [31:02] */
-#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_2_reserved0_MASK 0xfffffffc
-#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_2_reserved0_SHIFT 2
-
-/* SUN_TOP_CTRL :: GENERAL_STATUS_2 :: general_status2_1 [01:01] */
-#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_2_general_status2_1_MASK 0x00000002
-#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_2_general_status2_1_SHIFT 1
-
-/* SUN_TOP_CTRL :: GENERAL_STATUS_2 :: general_status2_0 [00:00] */
-#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_2_general_status2_0_MASK 0x00000001
-#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_2_general_status2_0_SHIFT 0
-
-/***************************************************************************
- *GENERAL_CTRL_NO_SCAN_0 - General control register without scan 0
- ***************************************************************************/
-/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: reserved0 [31:18] */
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_reserved0_MASK 0xfffc0000
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_reserved0_SHIFT 18
-
-/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: mtsif_0_pad_amp_en [17:17] */
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_mtsif_0_pad_amp_en_MASK 0x00020000
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_mtsif_0_pad_amp_en_SHIFT 17
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_mtsif_0_pad_amp_en_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: mtsif_0_pad_sel_gmii [16:16] */
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_mtsif_0_pad_sel_gmii_MASK 0x00010000
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_mtsif_0_pad_sel_gmii_SHIFT 16
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_mtsif_0_pad_sel_gmii_DEFAULT 0x00000001
-
-/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: mtsif_0_pad_modehv [15:15] */
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_mtsif_0_pad_modehv_MASK 0x00008000
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_mtsif_0_pad_modehv_SHIFT 15
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_mtsif_0_pad_modehv_DEFAULT 0x00000001
-
-/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: mtsif_0_pad_sel [14:12] */
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_mtsif_0_pad_sel_MASK 0x00007000
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_mtsif_0_pad_sel_SHIFT 12
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_mtsif_0_pad_sel_DEFAULT 0x00000003
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_mtsif_0_pad_sel_DRIVE_2MA 0
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_mtsif_0_pad_sel_DRIVE_4MA 1
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_mtsif_0_pad_sel_DRIVE_6MA 2
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_mtsif_0_pad_sel_DRIVE_8MA 3
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_mtsif_0_pad_sel_DRIVE_10MA 4
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_mtsif_0_pad_sel_DRIVE_12MA 5
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_mtsif_0_pad_sel_DRIVE_14MA 6
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_mtsif_0_pad_sel_DRIVE_16MA 7
-
-/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: rgmii_1_pad_amp_en [11:11] */
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_rgmii_1_pad_amp_en_MASK 0x00000800
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_rgmii_1_pad_amp_en_SHIFT 11
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_rgmii_1_pad_amp_en_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: rgmii_1_pad_sel_gmii [10:10] */
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_rgmii_1_pad_sel_gmii_MASK 0x00000400
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_rgmii_1_pad_sel_gmii_SHIFT 10
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_rgmii_1_pad_sel_gmii_DEFAULT 0x00000001
-
-/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: rgmii_1_pad_modehv [09:09] */
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_rgmii_1_pad_modehv_MASK 0x00000200
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_rgmii_1_pad_modehv_SHIFT 9
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_rgmii_1_pad_modehv_DEFAULT 0x00000001
-
-/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: rgmii_1_pad_sel [08:06] */
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_rgmii_1_pad_sel_MASK 0x000001c0
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_rgmii_1_pad_sel_SHIFT 6
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_rgmii_1_pad_sel_DEFAULT 0x00000003
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_rgmii_1_pad_sel_DRIVE_2MA 0
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_rgmii_1_pad_sel_DRIVE_4MA 1
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_rgmii_1_pad_sel_DRIVE_6MA 2
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_rgmii_1_pad_sel_DRIVE_8MA 3
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_rgmii_1_pad_sel_DRIVE_10MA 4
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_rgmii_1_pad_sel_DRIVE_12MA 5
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_rgmii_1_pad_sel_DRIVE_14MA 6
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_rgmii_1_pad_sel_DRIVE_16MA 7
-
-/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: rgmii_0_pad_amp_en [05:05] */
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_rgmii_0_pad_amp_en_MASK 0x00000020
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_rgmii_0_pad_amp_en_SHIFT 5
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_rgmii_0_pad_amp_en_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: rgmii_0_pad_sel_gmii [04:04] */
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_rgmii_0_pad_sel_gmii_MASK 0x00000010
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_rgmii_0_pad_sel_gmii_SHIFT 4
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_rgmii_0_pad_sel_gmii_DEFAULT 0x00000001
-
-/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: rgmii_0_pad_modehv [03:03] */
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_rgmii_0_pad_modehv_MASK 0x00000008
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_rgmii_0_pad_modehv_SHIFT 3
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_rgmii_0_pad_modehv_DEFAULT 0x00000001
-
-/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: rgmii_0_pad_sel [02:00] */
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_rgmii_0_pad_sel_MASK 0x00000007
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_rgmii_0_pad_sel_SHIFT 0
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_rgmii_0_pad_sel_DEFAULT 0x00000003
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_rgmii_0_pad_sel_DRIVE_2MA 0
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_rgmii_0_pad_sel_DRIVE_4MA 1
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_rgmii_0_pad_sel_DRIVE_6MA 2
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_rgmii_0_pad_sel_DRIVE_8MA 3
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_rgmii_0_pad_sel_DRIVE_10MA 4
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_rgmii_0_pad_sel_DRIVE_12MA 5
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_rgmii_0_pad_sel_DRIVE_14MA 6
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_rgmii_0_pad_sel_DRIVE_16MA 7
-
-/***************************************************************************
- *GENERAL_CTRL_NO_SCAN_1 - General control register without scan 1
- ***************************************************************************/
-/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_1 :: reserved0 [31:28] */
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_reserved0_MASK 0xf0000000
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_reserved0_SHIFT 28
-
-/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_1 :: pad_mode_gpio_057 [27:27] */
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_057_MASK 0x08000000
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_057_SHIFT 27
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_057_DEFAULT 0x00000001
-
-/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_1 :: pad_mode_gpio_056 [26:26] */
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_056_MASK 0x04000000
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_056_SHIFT 26
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_056_DEFAULT 0x00000001
-
-/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_1 :: pad_mode_gpio_055 [25:25] */
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_055_MASK 0x02000000
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_055_SHIFT 25
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_055_DEFAULT 0x00000001
-
-/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_1 :: pad_mode_gpio_054 [24:24] */
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_054_MASK 0x01000000
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_054_SHIFT 24
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_054_DEFAULT 0x00000001
-
-/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_1 :: pad_mode_gpio_053 [23:23] */
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_053_MASK 0x00800000
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_053_SHIFT 23
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_053_DEFAULT 0x00000001
-
-/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_1 :: pad_mode_gpio_052 [22:22] */
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_052_MASK 0x00400000
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_052_SHIFT 22
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_052_DEFAULT 0x00000001
-
-/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_1 :: pad_mode_gpio_051 [21:21] */
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_051_MASK 0x00200000
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_051_SHIFT 21
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_051_DEFAULT 0x00000001
-
-/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_1 :: pad_mode_gpio_050 [20:20] */
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_050_MASK 0x00100000
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_050_SHIFT 20
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_050_DEFAULT 0x00000001
-
-/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_1 :: pad_mode_gpio_049 [19:19] */
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_049_MASK 0x00080000
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_049_SHIFT 19
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_049_DEFAULT 0x00000001
-
-/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_1 :: pad_mode_gpio_048 [18:18] */
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_048_MASK 0x00040000
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_048_SHIFT 18
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_048_DEFAULT 0x00000001
-
-/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_1 :: pad_mode_gpio_047 [17:17] */
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_047_MASK 0x00020000
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_047_SHIFT 17
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_047_DEFAULT 0x00000001
-
-/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_1 :: pad_mode_gpio_046 [16:16] */
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_046_MASK 0x00010000
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_046_SHIFT 16
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_046_DEFAULT 0x00000001
-
-/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_1 :: pad_mode_gpio_045 [15:15] */
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_045_MASK 0x00008000
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_045_SHIFT 15
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_045_DEFAULT 0x00000001
-
-/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_1 :: pad_mode_gpio_044 [14:14] */
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_044_MASK 0x00004000
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_044_SHIFT 14
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_044_DEFAULT 0x00000001
-
-/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_1 :: pad_mode_gpio_043 [13:13] */
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_043_MASK 0x00002000
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_043_SHIFT 13
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_043_DEFAULT 0x00000001
-
-/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_1 :: pad_mode_gpio_042 [12:12] */
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_042_MASK 0x00001000
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_042_SHIFT 12
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_042_DEFAULT 0x00000001
-
-/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_1 :: pad_mode_gpio_041 [11:11] */
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_041_MASK 0x00000800
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_041_SHIFT 11
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_041_DEFAULT 0x00000001
-
-/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_1 :: pad_mode_gpio_040 [10:10] */
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_040_MASK 0x00000400
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_040_SHIFT 10
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_040_DEFAULT 0x00000001
-
-/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_1 :: pad_mode_gpio_039 [09:09] */
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_039_MASK 0x00000200
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_039_SHIFT 9
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_039_DEFAULT 0x00000001
-
-/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_1 :: pad_mode_gpio_038 [08:08] */
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_038_MASK 0x00000100
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_038_SHIFT 8
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_038_DEFAULT 0x00000001
-
-/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_1 :: pad_mode_gpio_037 [07:07] */
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_037_MASK 0x00000080
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_037_SHIFT 7
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_037_DEFAULT 0x00000001
-
-/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_1 :: pad_mode_gpio_036 [06:06] */
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_036_MASK 0x00000040
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_036_SHIFT 6
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_036_DEFAULT 0x00000001
-
-/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_1 :: pad_mode_gpio_035 [05:05] */
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_035_MASK 0x00000020
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_035_SHIFT 5
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_035_DEFAULT 0x00000001
-
-/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_1 :: pad_mode_gpio_034 [04:04] */
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_034_MASK 0x00000010
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_034_SHIFT 4
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_034_DEFAULT 0x00000001
-
-/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_1 :: pad_mode_gpio_033 [03:03] */
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_033_MASK 0x00000008
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_033_SHIFT 3
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_033_DEFAULT 0x00000001
-
-/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_1 :: pad_mode_gpio_032 [02:02] */
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_032_MASK 0x00000004
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_032_SHIFT 2
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_032_DEFAULT 0x00000001
-
-/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_1 :: pad_mode_gpio_031 [01:01] */
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_031_MASK 0x00000002
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_031_SHIFT 1
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_031_DEFAULT 0x00000001
-
-/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_1 :: pad_mode_gpio_030 [00:00] */
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_030_MASK 0x00000001
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_030_SHIFT 0
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_030_DEFAULT 0x00000001
-
-/***************************************************************************
- *GENERAL_CTRL_NO_SCAN_2 - General control register without scan 2
- ***************************************************************************/
-/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_2 :: reserved0 [31:30] */
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_reserved0_MASK 0xc0000000
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_reserved0_SHIFT 30
-
-/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_2 :: sdio_1_pad_slew [29:29] */
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_sdio_1_pad_slew_MASK 0x20000000
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_sdio_1_pad_slew_SHIFT 29
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_sdio_1_pad_slew_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_2 :: sdio_0_pad_slew [28:28] */
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_sdio_0_pad_slew_MASK 0x10000000
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_sdio_0_pad_slew_SHIFT 28
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_sdio_0_pad_slew_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_2 :: emmc_pad_slew [27:27] */
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_emmc_pad_slew_MASK 0x08000000
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_emmc_pad_slew_SHIFT 27
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_emmc_pad_slew_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_2 :: emmc_pad_sel [26:24] */
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_emmc_pad_sel_MASK 0x07000000
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_emmc_pad_sel_SHIFT 24
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_emmc_pad_sel_DEFAULT 0x00000003
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_emmc_pad_sel_DRIVE_2MA 0
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_emmc_pad_sel_DRIVE_4MA 1
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_emmc_pad_sel_DRIVE_6MA 2
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_emmc_pad_sel_DRIVE_8MA 3
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_emmc_pad_sel_DRIVE_10MA 4
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_emmc_pad_sel_DRIVE_12MA 5
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_emmc_pad_sel_DRIVE_14MA 6
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_emmc_pad_sel_DRIVE_16MA 7
-
-/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_2 :: bspi_pad_src [23:23] */
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_bspi_pad_src_MASK 0x00800000
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_bspi_pad_src_SHIFT 23
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_bspi_pad_src_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_2 :: bspi_pad_sel [22:20] */
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_bspi_pad_sel_MASK 0x00700000
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_bspi_pad_sel_SHIFT 20
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_bspi_pad_sel_DEFAULT 0x00000003
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_bspi_pad_sel_DRIVE_2MA 0
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_bspi_pad_sel_DRIVE_4MA 1
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_bspi_pad_sel_DRIVE_6MA 2
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_bspi_pad_sel_DRIVE_8MA 3
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_bspi_pad_sel_DRIVE_10MA 4
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_bspi_pad_sel_DRIVE_12MA 5
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_bspi_pad_sel_DRIVE_14MA 6
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_bspi_pad_sel_DRIVE_16MA 7
-
-/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_2 :: ebi_4_pad_src [19:19] */
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_4_pad_src_MASK 0x00080000
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_4_pad_src_SHIFT 19
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_4_pad_src_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_2 :: ebi_4_pad_sel [18:16] */
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_4_pad_sel_MASK 0x00070000
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_4_pad_sel_SHIFT 16
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_4_pad_sel_DEFAULT 0x00000003
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_4_pad_sel_DRIVE_2MA 0
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_4_pad_sel_DRIVE_4MA 1
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_4_pad_sel_DRIVE_6MA 2
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_4_pad_sel_DRIVE_8MA 3
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_4_pad_sel_DRIVE_10MA 4
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_4_pad_sel_DRIVE_12MA 5
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_4_pad_sel_DRIVE_14MA 6
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_4_pad_sel_DRIVE_16MA 7
-
-/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_2 :: ebi_3_pad_src [15:15] */
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_3_pad_src_MASK 0x00008000
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_3_pad_src_SHIFT 15
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_3_pad_src_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_2 :: ebi_3_pad_sel [14:12] */
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_3_pad_sel_MASK 0x00007000
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_3_pad_sel_SHIFT 12
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_3_pad_sel_DEFAULT 0x00000003
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_3_pad_sel_DRIVE_2MA 0
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_3_pad_sel_DRIVE_4MA 1
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_3_pad_sel_DRIVE_6MA 2
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_3_pad_sel_DRIVE_8MA 3
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_3_pad_sel_DRIVE_10MA 4
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_3_pad_sel_DRIVE_12MA 5
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_3_pad_sel_DRIVE_14MA 6
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_3_pad_sel_DRIVE_16MA 7
-
-/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_2 :: ebi_2_pad_src [11:11] */
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_2_pad_src_MASK 0x00000800
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_2_pad_src_SHIFT 11
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_2_pad_src_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_2 :: ebi_2_pad_sel [10:08] */
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_2_pad_sel_MASK 0x00000700
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_2_pad_sel_SHIFT 8
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_2_pad_sel_DEFAULT 0x00000003
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_2_pad_sel_DRIVE_2MA 0
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_2_pad_sel_DRIVE_4MA 1
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_2_pad_sel_DRIVE_6MA 2
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_2_pad_sel_DRIVE_8MA 3
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_2_pad_sel_DRIVE_10MA 4
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_2_pad_sel_DRIVE_12MA 5
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_2_pad_sel_DRIVE_14MA 6
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_2_pad_sel_DRIVE_16MA 7
-
-/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_2 :: ebi_1_pad_src [07:07] */
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_1_pad_src_MASK 0x00000080
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_1_pad_src_SHIFT 7
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_1_pad_src_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_2 :: ebi_1_pad_sel [06:04] */
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_1_pad_sel_MASK 0x00000070
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_1_pad_sel_SHIFT 4
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_1_pad_sel_DEFAULT 0x00000003
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_1_pad_sel_DRIVE_2MA 0
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_1_pad_sel_DRIVE_4MA 1
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_1_pad_sel_DRIVE_6MA 2
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_1_pad_sel_DRIVE_8MA 3
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_1_pad_sel_DRIVE_10MA 4
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_1_pad_sel_DRIVE_12MA 5
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_1_pad_sel_DRIVE_14MA 6
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_1_pad_sel_DRIVE_16MA 7
-
-/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_2 :: ebi_0_pad_src [03:03] */
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_0_pad_src_MASK 0x00000008
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_0_pad_src_SHIFT 3
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_0_pad_src_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_2 :: ebi_0_pad_sel [02:00] */
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_0_pad_sel_MASK 0x00000007
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_0_pad_sel_SHIFT 0
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_0_pad_sel_DEFAULT 0x00000003
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_0_pad_sel_DRIVE_2MA 0
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_0_pad_sel_DRIVE_4MA 1
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_0_pad_sel_DRIVE_6MA 2
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_0_pad_sel_DRIVE_8MA 3
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_0_pad_sel_DRIVE_10MA 4
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_0_pad_sel_DRIVE_12MA 5
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_0_pad_sel_DRIVE_14MA 6
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_0_pad_sel_DRIVE_16MA 7
-
-/***************************************************************************
- *GENERAL_CTRL_NO_SCAN_3 - General control register without scan 3
- ***************************************************************************/
-/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_3 :: reserved0 [31:02] */
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_reserved0_MASK 0xfffffffc
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_reserved0_SHIFT 2
-
-/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_3 :: general_ctrl_no_scan3_1 [01:01] */
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_general_ctrl_no_scan3_1_MASK 0x00000002
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_general_ctrl_no_scan3_1_SHIFT 1
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_general_ctrl_no_scan3_1_DEFAULT 0x00000001
-
-/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_3 :: general_ctrl_no_scan3_0 [00:00] */
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_general_ctrl_no_scan3_0_MASK 0x00000001
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_general_ctrl_no_scan3_0_SHIFT 0
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_general_ctrl_no_scan3_0_DEFAULT 0x00000000
-
-/***************************************************************************
- *GENERAL_CTRL_NO_SCAN_4 - General control register without scan 4
- ***************************************************************************/
-/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_4 :: reserved0 [31:02] */
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_4_reserved0_MASK 0xfffffffc
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_4_reserved0_SHIFT 2
-
-/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_4 :: general_ctrl_no_scan4_1 [01:01] */
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_4_general_ctrl_no_scan4_1_MASK 0x00000002
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_4_general_ctrl_no_scan4_1_SHIFT 1
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_4_general_ctrl_no_scan4_1_DEFAULT 0x00000001
-
-/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_4 :: general_ctrl_no_scan4_0 [00:00] */
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_4_general_ctrl_no_scan4_0_MASK 0x00000001
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_4_general_ctrl_no_scan4_0_SHIFT 0
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_4_general_ctrl_no_scan4_0_DEFAULT 0x00000000
-
-/***************************************************************************
- *GENERAL_CTRL_NO_SCAN_5 - General control register without scan 5
- ***************************************************************************/
-/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_5 :: reserved0 [31:08] */
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_reserved0_MASK 0xffffff00
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_reserved0_SHIFT 8
-
-/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_5 :: egphy_test_pin_mux_sel [07:07] */
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_egphy_test_pin_mux_sel_MASK 0x00000080
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_egphy_test_pin_mux_sel_SHIFT 7
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_egphy_test_pin_mux_sel_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_5 :: test_thp_hys_en [06:06] */
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_test_thp_hys_en_MASK 0x00000040
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_test_thp_hys_en_SHIFT 6
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_test_thp_hys_en_DEFAULT 0x00000001
-
-/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_5 :: test_thp_oeb [05:05] */
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_test_thp_oeb_MASK 0x00000020
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_test_thp_oeb_SHIFT 5
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_test_thp_oeb_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_5 :: test_thp_do [04:04] */
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_test_thp_do_MASK 0x00000010
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_test_thp_do_SHIFT 4
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_test_thp_do_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_5 :: test_drive_src [03:03] */
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_test_drive_src_MASK 0x00000008
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_test_drive_src_SHIFT 3
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_test_drive_src_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_5 :: test_drive_sel [02:00] */
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_test_drive_sel_MASK 0x00000007
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_test_drive_sel_SHIFT 0
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_test_drive_sel_DEFAULT 0x00000003
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_test_drive_sel_DRIVE_2MA 0
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_test_drive_sel_DRIVE_4MA 1
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_test_drive_sel_DRIVE_6MA 2
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_test_drive_sel_DRIVE_8MA 3
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_test_drive_sel_DRIVE_10MA 4
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_test_drive_sel_DRIVE_12MA 5
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_test_drive_sel_DRIVE_14MA 6
-#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_test_drive_sel_DRIVE_16MA 7
-
-/***************************************************************************
- *GENERAL_STATUS_3 - General status register 3
- ***************************************************************************/
-/* SUN_TOP_CTRL :: GENERAL_STATUS_3 :: cpu_system_counter [31:00] */
-#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_3_cpu_system_counter_MASK 0xffffffff
-#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_3_cpu_system_counter_SHIFT 0
-
-/***************************************************************************
- *GENERAL_STATUS_4 - General status register 4
- ***************************************************************************/
-/* SUN_TOP_CTRL :: GENERAL_STATUS_4 :: cpu_system_counter [31:00] */
-#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_4_cpu_system_counter_MASK 0xffffffff
-#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_4_cpu_system_counter_SHIFT 0
-
-/***************************************************************************
- *PIN_MUX_CTRL_0 - Pinmux control register 0
- ***************************************************************************/
-/* SUN_TOP_CTRL :: PIN_MUX_CTRL_0 :: ebi_data_07 [31:28] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_ebi_data_07_MASK 0xf0000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_ebi_data_07_SHIFT 28
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_ebi_data_07_DEFAULT 0x00000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_ebi_data_07_EBI_DATA_07 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_ebi_data_07_TP_IN_07 1
-
-/* SUN_TOP_CTRL :: PIN_MUX_CTRL_0 :: ebi_data_06 [27:24] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_ebi_data_06_MASK 0x0f000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_ebi_data_06_SHIFT 24
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_ebi_data_06_DEFAULT 0x00000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_ebi_data_06_EBI_DATA_06 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_ebi_data_06_TP_IN_06 1
-
-/* SUN_TOP_CTRL :: PIN_MUX_CTRL_0 :: ebi_data_05 [23:20] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_ebi_data_05_MASK 0x00f00000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_ebi_data_05_SHIFT 20
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_ebi_data_05_DEFAULT 0x00000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_ebi_data_05_EBI_DATA_05 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_ebi_data_05_TP_IN_05 1
-
-/* SUN_TOP_CTRL :: PIN_MUX_CTRL_0 :: ebi_data_04 [19:16] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_ebi_data_04_MASK 0x000f0000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_ebi_data_04_SHIFT 16
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_ebi_data_04_DEFAULT 0x00000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_ebi_data_04_EBI_DATA_04 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_ebi_data_04_TP_IN_04 1
-
-/* SUN_TOP_CTRL :: PIN_MUX_CTRL_0 :: ebi_data_03 [15:12] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_ebi_data_03_MASK 0x0000f000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_ebi_data_03_SHIFT 12
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_ebi_data_03_DEFAULT 0x00000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_ebi_data_03_EBI_DATA_03 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_ebi_data_03_TP_IN_03 1
-
-/* SUN_TOP_CTRL :: PIN_MUX_CTRL_0 :: ebi_data_02 [11:08] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_ebi_data_02_MASK 0x00000f00
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_ebi_data_02_SHIFT 8
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_ebi_data_02_DEFAULT 0x00000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_ebi_data_02_EBI_DATA_02 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_ebi_data_02_TP_IN_02 1
-
-/* SUN_TOP_CTRL :: PIN_MUX_CTRL_0 :: ebi_data_01 [07:04] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_ebi_data_01_MASK 0x000000f0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_ebi_data_01_SHIFT 4
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_ebi_data_01_DEFAULT 0x00000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_ebi_data_01_EBI_DATA_01 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_ebi_data_01_TP_IN_01 1
-
-/* SUN_TOP_CTRL :: PIN_MUX_CTRL_0 :: ebi_data_00 [03:00] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_ebi_data_00_MASK 0x0000000f
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_ebi_data_00_SHIFT 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_ebi_data_00_DEFAULT 0x00000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_ebi_data_00_EBI_DATA_00 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_ebi_data_00_TP_IN_00 1
-
-/***************************************************************************
- *PIN_MUX_CTRL_1 - Pinmux control register 1
- ***************************************************************************/
-/* SUN_TOP_CTRL :: PIN_MUX_CTRL_1 :: ebi_we0b [31:28] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_ebi_we0b_MASK 0xf0000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_ebi_we0b_SHIFT 28
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_ebi_we0b_DEFAULT 0x00000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_ebi_we0b_EBI_WE0B 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_ebi_we0b_TP_IN_17 1
-
-/* SUN_TOP_CTRL :: PIN_MUX_CTRL_1 :: ebi_rwb [27:24] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_ebi_rwb_MASK 0x0f000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_ebi_rwb_SHIFT 24
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_ebi_rwb_DEFAULT 0x00000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_ebi_rwb_EBI_RWB 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_ebi_rwb_TP_IN_16 1
-
-/* SUN_TOP_CTRL :: PIN_MUX_CTRL_1 :: ebi_cs5b [23:20] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_ebi_cs5b_MASK 0x00f00000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_ebi_cs5b_SHIFT 20
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_ebi_cs5b_DEFAULT 0x00000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_ebi_cs5b_EBI_CS5B 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_ebi_cs5b_TP_IN_15 1
-
-/* SUN_TOP_CTRL :: PIN_MUX_CTRL_1 :: ebi_cs4b [19:16] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_ebi_cs4b_MASK 0x000f0000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_ebi_cs4b_SHIFT 16
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_ebi_cs4b_DEFAULT 0x00000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_ebi_cs4b_EBI_CS4B 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_ebi_cs4b_TP_IN_14 1
-
-/* SUN_TOP_CTRL :: PIN_MUX_CTRL_1 :: ebi_cs3b [15:12] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_ebi_cs3b_MASK 0x0000f000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_ebi_cs3b_SHIFT 12
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_ebi_cs3b_DEFAULT 0x00000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_ebi_cs3b_EBI_CS3B 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_ebi_cs3b_TP_IN_13 1
-
-/* SUN_TOP_CTRL :: PIN_MUX_CTRL_1 :: ebi_cs2b [11:08] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_ebi_cs2b_MASK 0x00000f00
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_ebi_cs2b_SHIFT 8
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_ebi_cs2b_DEFAULT 0x00000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_ebi_cs2b_EBI_CS2B 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_ebi_cs2b_TP_IN_11 1
-
-/* SUN_TOP_CTRL :: PIN_MUX_CTRL_1 :: ebi_cs1b [07:04] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_ebi_cs1b_MASK 0x000000f0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_ebi_cs1b_SHIFT 4
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_ebi_cs1b_DEFAULT 0x00000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_ebi_cs1b_EBI_CS1B 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_ebi_cs1b_TP_IN_09 1
-
-/* SUN_TOP_CTRL :: PIN_MUX_CTRL_1 :: ebi_cs0b [03:00] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_ebi_cs0b_MASK 0x0000000f
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_ebi_cs0b_SHIFT 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_ebi_cs0b_DEFAULT 0x00000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_ebi_cs0b_EBI_CS0B 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_ebi_cs0b_TP_IN_08 1
-
-/***************************************************************************
- *PIN_MUX_CTRL_2 - Pinmux control register 2
- ***************************************************************************/
-/* SUN_TOP_CTRL :: PIN_MUX_CTRL_2 :: gpio_002 [31:28] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_002_MASK 0xf0000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_002_SHIFT 28
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_002_DEFAULT 0x00000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_002_GPIO_002 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_002_EBI_DATA_10 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_002_SD_CARD1_DAT0 2
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_002_UART_RXD_1 3
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_002_LED_LD_10 4
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_002_CPU_TRACE_DATA6 5
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_002_TP_IN_24 6
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_002_PM_GPIO_002 7
-
-/* SUN_TOP_CTRL :: PIN_MUX_CTRL_2 :: gpio_001 [27:24] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_001_MASK 0x0f000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_001_SHIFT 24
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_001_DEFAULT 0x00000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_001_GPIO_001 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_001_EBI_DATA_09 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_001_SD_CARD1_CLK 2
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_001_UART_TXD_0 3
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_001_LED_LD_9 4
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_001_CPU_TRACE_DATA5 5
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_001_ALT_TP_OUT_02 6
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_001_PM_GPIO_001 7
-
-/* SUN_TOP_CTRL :: PIN_MUX_CTRL_2 :: gpio_000 [23:20] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_000_MASK 0x00f00000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_000_SHIFT 20
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_000_DEFAULT 0x00000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_000_GPIO_000 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_000_EBI_DATA_08 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_000_SD_CARD1_CMD 2
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_000_UART_RXD_0 3
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_000_LED_LD_8 4
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_000_CPU_TRACE_DATA4 5
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_000_TP_IN_23 6
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_000_PM_GPIO_000 7
-
-/* SUN_TOP_CTRL :: PIN_MUX_CTRL_2 :: ebi_nand_rbb [19:16] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_ebi_nand_rbb_MASK 0x000f0000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_ebi_nand_rbb_SHIFT 16
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_ebi_nand_rbb_DEFAULT 0x00000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_ebi_nand_rbb_EBI_NAND_RBB 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_ebi_nand_rbb_TP_IN_22 1
-
-/* SUN_TOP_CTRL :: PIN_MUX_CTRL_2 :: ebi_dsb [15:12] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_ebi_dsb_MASK 0x0000f000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_ebi_dsb_SHIFT 12
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_ebi_dsb_DEFAULT 0x00000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_ebi_dsb_EBI_DSB 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_ebi_dsb_TP_IN_21 1
-
-/* SUN_TOP_CTRL :: PIN_MUX_CTRL_2 :: ebi_tsb [11:08] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_ebi_tsb_MASK 0x00000f00
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_ebi_tsb_SHIFT 8
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_ebi_tsb_DEFAULT 0x00000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_ebi_tsb_EBI_TSB 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_ebi_tsb_TP_IN_20 1
-
-/* SUN_TOP_CTRL :: PIN_MUX_CTRL_2 :: ebi_rdb [07:04] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_ebi_rdb_MASK 0x000000f0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_ebi_rdb_SHIFT 4
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_ebi_rdb_DEFAULT 0x00000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_ebi_rdb_EBI_RDB 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_ebi_rdb_TP_IN_19 1
-
-/* SUN_TOP_CTRL :: PIN_MUX_CTRL_2 :: ebi_we1b [03:00] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_ebi_we1b_MASK 0x0000000f
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_ebi_we1b_SHIFT 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_ebi_we1b_DEFAULT 0x00000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_ebi_we1b_EBI_WE1B 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_ebi_we1b_TP_IN_18 1
-
-/***************************************************************************
- *PIN_MUX_CTRL_3 - Pinmux control register 3
- ***************************************************************************/
-/* SUN_TOP_CTRL :: PIN_MUX_CTRL_3 :: gpio_010 [31:28] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_010_MASK 0xf0000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_010_SHIFT 28
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_010_DEFAULT 0x00000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_010_GPIO_010 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_010_EBI_ADDR_04 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_010_SD_CARD1_LED 2
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_010_SPI_M_SS1B 3
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_010_PWM3 4
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_010_CPU_TRACE_DATA14 5
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_010_ALT_TP_IN_00 6
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_010_PM_GPIO_010 7
-
-/* SUN_TOP_CTRL :: PIN_MUX_CTRL_3 :: gpio_009 [27:24] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_009_MASK 0x0f000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_009_SHIFT 24
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_009_DEFAULT 0x00000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_009_GPIO_009 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_009_EBI_ADDR_03 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_009_SD_CARD1_PWR0 2
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_009_SPI_M_SS0B 3
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_009_PWM0 4
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_009_CPU_TRACE_DATA13 5
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_009_TP_IN_31 6
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_009_PM_GPIO_009 7
-
-/* SUN_TOP_CTRL :: PIN_MUX_CTRL_3 :: gpio_008 [23:20] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_008_MASK 0x00f00000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_008_SHIFT 20
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_008_DEFAULT 0x00000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_008_GPIO_008 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_008_EBI_WAITB 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_008_SD_CARD1_WPROT 2
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_008_SPI_M_MOSI 3
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_008_PWM1 4
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_008_CPU_TRACE_DATA12 5
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_008_TP_IN_28 6
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_008_PM_GPIO_008 7
-
-/* SUN_TOP_CTRL :: PIN_MUX_CTRL_3 :: gpio_007 [19:16] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_007_MASK 0x000f0000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_007_SHIFT 16
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_007_DEFAULT 0x00000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_007_GPIO_007 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_007_EBI_DATA_15 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_007_SD_CARD1_CLK_IN 2
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_007_SPI_M_MISO 3
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_007_LED_LD_15 4
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_007_CPU_TRACE_DATA11 5
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_007_TP_IN_27 6
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_007_PM_GPIO_007 7
-
-/* SUN_TOP_CTRL :: PIN_MUX_CTRL_3 :: gpio_006 [15:12] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_006_MASK 0x0000f000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_006_SHIFT 12
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_006_DEFAULT 0x00000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_006_GPIO_006 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_006_EBI_DATA_14 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_006_SD_CARD1_PRES 2
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_006_SPI_M_SCK 3
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_006_LED_LD_14 4
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_006_CPU_TRACE_DATA10 5
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_006_TP_IN_26 6
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_006_PM_GPIO_006 7
-
-/* SUN_TOP_CTRL :: PIN_MUX_CTRL_3 :: gpio_005 [11:08] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_005_MASK 0x00000f00
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_005_SHIFT 8
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_005_DEFAULT 0x00000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_005_GPIO_005 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_005_EBI_DATA_13 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_005_SD_CARD1_DAT3 2
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_005_UART_TXD_2 3
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_005_LED_LD_13 4
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_005_CPU_TRACE_DATA9 5
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_005_VEC_VSYNC 6
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_005_ALT_TP_OUT_04 7
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_005_PM_GPIO_005 8
-
-/* SUN_TOP_CTRL :: PIN_MUX_CTRL_3 :: gpio_004 [07:04] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_004_MASK 0x000000f0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_004_SHIFT 4
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_004_DEFAULT 0x00000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_004_GPIO_004 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_004_EBI_DATA_12 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_004_SD_CARD1_DAT2 2
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_004_UART_RXD_2 3
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_004_LED_LD_12 4
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_004_CPU_TRACE_DATA8 5
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_004_VEC_HSYNC 6
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_004_TP_IN_25 7
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_004_PM_GPIO_004 8
-
-/* SUN_TOP_CTRL :: PIN_MUX_CTRL_3 :: gpio_003 [03:00] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_003_MASK 0x0000000f
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_003_SHIFT 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_003_DEFAULT 0x00000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_003_GPIO_003 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_003_EBI_DATA_11 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_003_SD_CARD1_DAT1 2
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_003_UART_TXD_1 3
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_003_LED_LD_11 4
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_003_CPU_TRACE_DATA7 5
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_003_IR_IN1 6
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_003_ALT_TP_OUT_03 7
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_003_PM_GPIO_003 8
-
-/***************************************************************************
- *PIN_MUX_CTRL_4 - Pinmux control register 4
- ***************************************************************************/
-/* SUN_TOP_CTRL :: PIN_MUX_CTRL_4 :: gpio_018 [31:28] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_018_MASK 0xf0000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_018_SHIFT 28
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_018_DEFAULT 0x00000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_018_GPIO_018 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_018_MTSIF1_CLK 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_018_RGMII_B_RX_CLK 2
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_018_PM_GPIO_018 3
-
-/* SUN_TOP_CTRL :: PIN_MUX_CTRL_4 :: gpio_017 [27:24] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_017_MASK 0x0f000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_017_SHIFT 24
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_017_DEFAULT 0x00000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_017_GPIO_017 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_017_EBI_ADDR_11 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_017_MTSIF_ATS_INC 2
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_017_PM_GPIO_017 4
-
-/* SUN_TOP_CTRL :: PIN_MUX_CTRL_4 :: gpio_016 [23:20] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_016_MASK 0x00f00000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_016_SHIFT 20
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_016_DEFAULT 0x00000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_016_GPIO_016 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_016_EBI_ADDR_10 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_016_PKT_VALID0 2
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_016_TP_OUT_27 3
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_016_PM_GPIO_016 4
-
-/* SUN_TOP_CTRL :: PIN_MUX_CTRL_4 :: gpio_015 [19:16] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_015_MASK 0x000f0000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_015_SHIFT 16
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_015_DEFAULT 0x00000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_015_GPIO_015 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_015_EBI_ADDR_09 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_015_PKT_ERROR0 2
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_015_CHIP2POD_SCTL1 3
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_015_TP_OUT_31 4
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_015_PM_GPIO_015 5
-
-/* SUN_TOP_CTRL :: PIN_MUX_CTRL_4 :: gpio_014 [15:12] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_014_MASK 0x0000f000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_014_SHIFT 12
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_014_DEFAULT 0x00000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_014_GPIO_014 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_014_EBI_ADDR_08 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_014_PKT_SYNC0 2
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_014_CHIP2POD_SDO1 3
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_014_TP_OUT_30 4
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_014_PM_GPIO_014 5
-
-/* SUN_TOP_CTRL :: PIN_MUX_CTRL_4 :: gpio_013 [11:08] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_013_MASK 0x00000f00
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_013_SHIFT 8
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_013_DEFAULT 0x00000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_013_GPIO_013 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_013_EBI_ADDR_07 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_013_PKT_DATA0 2
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_013_POD2CHIP_SDI1 3
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_013_ALT_TP_IN_02 4
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_013_PM_GPIO_013 5
-
-/* SUN_TOP_CTRL :: PIN_MUX_CTRL_4 :: gpio_012 [07:04] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_012_MASK 0x000000f0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_012_SHIFT 4
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_012_DEFAULT 0x00000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_012_GPIO_012 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_012_EBI_ADDR_06 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_012_PKT_CLK0 2
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_012_CHIP2POD_SCLK1 3
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_012_ALT_TP_IN_01 4
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_012_PM_GPIO_012 5
-
-/* SUN_TOP_CTRL :: PIN_MUX_CTRL_4 :: gpio_011 [03:00] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_011_MASK 0x0000000f
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_011_SHIFT 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_011_DEFAULT 0x00000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_011_GPIO_011 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_011_EBI_ADDR_05 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_011_SD_CARD1_VOLT 2
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_011_PWM2 3
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_011_CPU_TRACE_DATA15 4
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_011_ALT_TP_OUT_10 5
-
-/***************************************************************************
- *PIN_MUX_CTRL_5 - Pinmux control register 5
- ***************************************************************************/
-/* SUN_TOP_CTRL :: PIN_MUX_CTRL_5 :: gpio_026 [31:28] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_026_MASK 0xf0000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_026_SHIFT 28
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_026_DEFAULT 0x00000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_026_GPIO_026 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_026_MTSIF1_DATA5 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_026_RGMII_B_TXD_00 2
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_026_PM_GPIO_026 3
-
-/* SUN_TOP_CTRL :: PIN_MUX_CTRL_5 :: gpio_025 [27:24] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_025_MASK 0x0f000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_025_SHIFT 24
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_025_DEFAULT 0x00000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_025_GPIO_025 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_025_MTSIF1_DATA4 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_025_RGMII_B_TX_EN_CTL 2
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_025_PM_GPIO_025 3
-
-/* SUN_TOP_CTRL :: PIN_MUX_CTRL_5 :: gpio_024 [23:20] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_024_MASK 0x00f00000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_024_SHIFT 20
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_024_DEFAULT 0x00000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_024_GPIO_024 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_024_MTSIF1_DATA3 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_024_RGMII_B_TX_CLK 2
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_024_PM_GPIO_024 3
-
-/* SUN_TOP_CTRL :: PIN_MUX_CTRL_5 :: gpio_023 [19:16] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_023_MASK 0x000f0000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_023_SHIFT 16
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_023_DEFAULT 0x00000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_023_GPIO_023 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_023_MTSIF1_DATA2 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_023_RGMII_B_RXD_03 2
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_023_PM_GPIO_023 3
-
-/* SUN_TOP_CTRL :: PIN_MUX_CTRL_5 :: gpio_022 [15:12] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_022_MASK 0x0000f000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_022_SHIFT 12
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_022_DEFAULT 0x00000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_022_GPIO_022 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_022_MTSIF1_VALID 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_022_RGMII_B_RXD_02 2
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_022_PM_GPIO_022 3
-
-/* SUN_TOP_CTRL :: PIN_MUX_CTRL_5 :: gpio_021 [11:08] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_021_MASK 0x00000f00
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_021_SHIFT 8
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_021_DEFAULT 0x00000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_021_GPIO_021 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_021_MTSIF1_DATA1 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_021_RGMII_B_RXD_01 2
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_021_PM_GPIO_021 3
-
-/* SUN_TOP_CTRL :: PIN_MUX_CTRL_5 :: gpio_020 [07:04] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_020_MASK 0x000000f0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_020_SHIFT 4
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_020_DEFAULT 0x00000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_020_GPIO_020 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_020_MTSIF1_SYNC 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_020_RGMII_B_RXD_00 2
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_020_PM_GPIO_020 3
-
-/* SUN_TOP_CTRL :: PIN_MUX_CTRL_5 :: gpio_019 [03:00] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_019_MASK 0x0000000f
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_019_SHIFT 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_019_DEFAULT 0x00000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_019_GPIO_019 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_019_MTSIF1_DATA0 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_019_RGMII_B_RX_EN_CTL 2
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_019_PM_GPIO_019 3
-
-/***************************************************************************
- *PIN_MUX_CTRL_6 - Pinmux control register 6
- ***************************************************************************/
-/* SUN_TOP_CTRL :: PIN_MUX_CTRL_6 :: gpio_034 [31:28] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_034_MASK 0xf0000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_034_SHIFT 28
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_034_DEFAULT 0x00000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_034_GPIO_034 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_034_CHIP2POD_SDO0 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_034_SPI_M_MOSI 2
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_034_EBI_ADDR_00 3
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_034_VEC_HSYNC 4
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_034_ALT_TP_IN_06 5
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_034_PM_GPIO_034 6
-
-/* SUN_TOP_CTRL :: PIN_MUX_CTRL_6 :: gpio_033 [27:24] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_033_MASK 0x0f000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_033_SHIFT 24
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_033_DEFAULT 0x00000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_033_GPIO_033 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_033_POD2CHIP_SDI0 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_033_SPI_M_MISO 2
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_033_ALT_TP_IN_05 3
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_033_PM_GPIO_033 4
-
-/* SUN_TOP_CTRL :: PIN_MUX_CTRL_6 :: gpio_032 [23:20] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_032_MASK 0x00f00000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_032_SHIFT 20
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_032_DEFAULT 0x00000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_032_GPIO_032 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_032_CHIP2POD_SCLK0 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_032_SPI_M_SCK 2
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_032_EBI_ADDR_01 3
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_032_ALT_TP_IN_04 4
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_032_PM_GPIO_032 5
-
-/* SUN_TOP_CTRL :: PIN_MUX_CTRL_6 :: gpio_031 [19:16] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_031_MASK 0x000f0000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_031_SHIFT 16
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_031_DEFAULT 0x00000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_031_GPIO_031 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_031_CHIP2POD_MCLKO 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_031_RMXP_CLK 2
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_031_EBI_ADDR_15 3
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_031_ALT_TP_IN_03 4
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_031_PM_GPIO_031 5
-
-/* SUN_TOP_CTRL :: PIN_MUX_CTRL_6 :: gpio_030 [15:12] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_030_MASK 0x0000f000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_030_SHIFT 12
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_030_DEFAULT 0x00000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_030_GPIO_030 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_030_POD2CHIP_MCLKI 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_030_PPKT_CLK 2
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_030_EBI_ADDR_14 3
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_030_PM_GPIO_030 4
-
-/* SUN_TOP_CTRL :: PIN_MUX_CTRL_6 :: gpio_029 [11:08] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_029_MASK 0x00000f00
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_029_SHIFT 8
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_029_DEFAULT 0x00000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_029_GPIO_029 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_029_PWM0 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_029_RGMII_B_TXD_03 2
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_029_IR_IN1 3
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_029_PM_GPIO_029 4
-
-/* SUN_TOP_CTRL :: PIN_MUX_CTRL_6 :: gpio_028 [07:04] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_028_MASK 0x000000f0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_028_SHIFT 4
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_028_DEFAULT 0x00000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_028_GPIO_028 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_028_MTSIF1_DATA7 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_028_RGMII_B_TXD_02 2
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_028_PM_GPIO_028 3
-
-/* SUN_TOP_CTRL :: PIN_MUX_CTRL_6 :: gpio_027 [03:00] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_027_MASK 0x0000000f
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_027_SHIFT 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_027_DEFAULT 0x00000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_027_GPIO_027 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_027_MTSIF1_DATA6 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_027_RGMII_B_TXD_01 2
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_027_PM_GPIO_027 3
-
-/***************************************************************************
- *PIN_MUX_CTRL_7 - Pinmux control register 7
- ***************************************************************************/
-/* SUN_TOP_CTRL :: PIN_MUX_CTRL_7 :: gpio_042 [31:28] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_042_MASK 0xf0000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_042_SHIFT 28
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_042_DEFAULT 0x00000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_042_GPIO_042 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_042_POD2CHIP_MDI4 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_042_PPKT_DATA4 2
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_042_UART_TXD_2 3
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_042_ALT_TP_OUT_13 4
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_042_PM_GPIO_042 5
-
-/* SUN_TOP_CTRL :: PIN_MUX_CTRL_7 :: gpio_041 [27:24] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_041_MASK 0x0f000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_041_SHIFT 24
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_041_DEFAULT 0x00000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_041_GPIO_041 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_041_POD2CHIP_MDI3 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_041_PPKT_DATA3 2
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_041_UART_RXD_2 3
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_041_ALT_TP_IN_11 4
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_041_PM_GPIO_041 5
-
-/* SUN_TOP_CTRL :: PIN_MUX_CTRL_7 :: gpio_040 [23:20] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_040_MASK 0x00f00000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_040_SHIFT 20
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_040_DEFAULT 0x00000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_040_GPIO_040 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_040_POD2CHIP_MDI2 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_040_PPKT_DATA2 2
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_040_UART_TXD_1 3
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_040_ALT_TP_OUT_12 4
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_040_PM_GPIO_040 5
-
-/* SUN_TOP_CTRL :: PIN_MUX_CTRL_7 :: gpio_039 [19:16] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_039_MASK 0x000f0000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_039_SHIFT 16
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_039_DEFAULT 0x00000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_039_GPIO_039 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_039_POD2CHIP_MDI1 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_039_PPKT_DATA1 2
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_039_UART_RXD_1 3
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_039_ALT_TP_IN_10 4
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_039_PM_GPIO_039 5
-
-/* SUN_TOP_CTRL :: PIN_MUX_CTRL_7 :: gpio_038 [15:12] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_038_MASK 0x0000f000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_038_SHIFT 12
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_038_DEFAULT 0x00000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_038_GPIO_038 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_038_POD2CHIP_MDI0 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_038_PPKT_DATA0 2
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_038_UART_TXD_0 3
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_038_ALT_TP_OUT_11 4
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_038_PM_GPIO_038 5
-
-/* SUN_TOP_CTRL :: PIN_MUX_CTRL_7 :: gpio_037 [11:08] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_037_MASK 0x00000f00
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_037_SHIFT 8
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_037_DEFAULT 0x00000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_037_GPIO_037 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_037_POD2CHIP_MIVAL 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_037_PPKT_VALID 2
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_037_UART_RXD_0 3
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_037_ALT_TP_IN_09 4
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_037_PM_GPIO_037 5
-
-/* SUN_TOP_CTRL :: PIN_MUX_CTRL_7 :: gpio_036 [07:04] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_036_MASK 0x000000f0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_036_SHIFT 4
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_036_DEFAULT 0x00000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_036_GPIO_036 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_036_POD2CHIP_MISTRT 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_036_PPKT_SYNC 2
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_036_ALT_TP_IN_08 3
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_036_PM_GPIO_036 4
-
-/* SUN_TOP_CTRL :: PIN_MUX_CTRL_7 :: gpio_035 [03:00] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_035_MASK 0x0000000f
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_035_SHIFT 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_035_DEFAULT 0x00000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_035_GPIO_035 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_035_CHIP2POD_SCTL0 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_035_SPI_M_SS0B 2
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_035_EBI_ADDR_02 3
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_035_VEC_VSYNC 4
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_035_ALT_TP_IN_07 5
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_035_PM_GPIO_035 6
-
-/***************************************************************************
- *PIN_MUX_CTRL_8 - Pinmux control register 8
- ***************************************************************************/
-/* SUN_TOP_CTRL :: PIN_MUX_CTRL_8 :: gpio_050 [31:28] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_050_MASK 0xf0000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_050_SHIFT 28
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_050_DEFAULT 0x00000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_050_GPIO_050 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_050_CHIP2POD_MDO1 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_050_RMXP_DATA1 2
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_050_EBI_ADDR_19 3
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_050_SC1_IO 4
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_050_ALT_TP_IN_25 5
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_050_PM_GPIO_050 6
-
-/* SUN_TOP_CTRL :: PIN_MUX_CTRL_8 :: gpio_049 [27:24] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_049_MASK 0x0f000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_049_SHIFT 24
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_049_DEFAULT 0x00000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_049_GPIO_049 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_049_CHIP2POD_MDO0 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_049_RMXP_DATA0 2
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_049_EBI_ADDR_18 3
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_049_SC1_RST 4
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_049_ALT_TP_IN_24 5
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_049_PM_GPIO_049 6
-
-/* SUN_TOP_CTRL :: PIN_MUX_CTRL_8 :: gpio_048 [23:20] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_048_MASK 0x00f00000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_048_SHIFT 20
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_048_DEFAULT 0x00000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_048_GPIO_048 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_048_CHIP2POD_MOSTRT 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_048_RMXP_SYNC 2
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_048_EBI_ADDR_17 3
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_048_SC1_CLK 4
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_048_ALT_TP_IN_23 5
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_048_PM_GPIO_048 6
-
-/* SUN_TOP_CTRL :: PIN_MUX_CTRL_8 :: gpio_047 [19:16] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_047_MASK 0x000f0000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_047_SHIFT 16
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_047_DEFAULT 0x00000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_047_GPIO_047 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_047_CHIP2POD_MOVAL 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_047_RMXP_VALID 2
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_047_EBI_ADDR_16 3
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_047_SC1_VCC 4
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_047_ALT_TP_IN_22 5
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_047_PM_GPIO_047 6
-
-/* SUN_TOP_CTRL :: PIN_MUX_CTRL_8 :: gpio_046 [15:12] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_046_MASK 0x0000f000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_046_SHIFT 12
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_046_DEFAULT 0x00000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_046_GPIO_046 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_046_POD2CHIP_MICLK 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_046_PPKT_CLK 2
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_046_EBI_ADDR_13 3
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_046_POD2CHIP_MCLKI 4
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_046_ALT_TP_IN_21 5
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_046_PM_GPIO_046 6
-
-/* SUN_TOP_CTRL :: PIN_MUX_CTRL_8 :: gpio_045 [11:08] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_045_MASK 0x00000f00
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_045_SHIFT 8
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_045_DEFAULT 0x00000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_045_GPIO_045 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_045_POD2CHIP_MDI7 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_045_PPKT_DATA7 2
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_045_ALT_TP_IN_20 3
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_045_PM_GPIO_045 4
-
-/* SUN_TOP_CTRL :: PIN_MUX_CTRL_8 :: gpio_044 [07:04] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_044_MASK 0x000000f0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_044_SHIFT 4
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_044_DEFAULT 0x00000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_044_GPIO_044 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_044_POD2CHIP_MDI6 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_044_PPKT_DATA6 2
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_044_ALT_TP_IN_19 3
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_044_PM_GPIO_044 4
-
-/* SUN_TOP_CTRL :: PIN_MUX_CTRL_8 :: gpio_043 [03:00] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_043_MASK 0x0000000f
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_043_SHIFT 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_043_DEFAULT 0x00000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_043_GPIO_043 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_043_POD2CHIP_MDI5 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_043_PPKT_DATA5 2
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_043_ALT_TP_IN_18 3
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_043_PM_GPIO_043 4
-
-/***************************************************************************
- *PIN_MUX_CTRL_9 - Pinmux control register 9
- ***************************************************************************/
-/* SUN_TOP_CTRL :: PIN_MUX_CTRL_9 :: gpio_058 [31:28] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_058_MASK 0xf0000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_058_SHIFT 28
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_058_DEFAULT 0x00000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_058_GPIO_058 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_058_SC0_VCC 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_058_TEST_THP 2
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_058_TP_OUT_17 3
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_058_PM_GPIO_058 4
-
-/* SUN_TOP_CTRL :: PIN_MUX_CTRL_9 :: gpio_057 [27:24] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_057_MASK 0x0f000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_057_SHIFT 24
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_057_DEFAULT 0x00000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_057_GPIO_057 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_057_CHIP2POD_MOCLK 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_057_RMXP_CLK 2
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_057_EBI_ADDR_12 3
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_057_CHIP2POD_MCLKO 4
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_057_PM_GPIO_057 5
-
-/* SUN_TOP_CTRL :: PIN_MUX_CTRL_9 :: gpio_056 [23:20] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_056_MASK 0x00f00000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_056_SHIFT 20
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_056_DEFAULT 0x00000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_056_GPIO_056 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_056_CHIP2POD_MDO7 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_056_RMXP_DATA7 2
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_056_EBI_ADDR_25 3
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_056_PM_GPIO_056 4
-
-/* SUN_TOP_CTRL :: PIN_MUX_CTRL_9 :: gpio_055 [19:16] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_055_MASK 0x000f0000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_055_SHIFT 16
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_055_DEFAULT 0x00000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_055_GPIO_055 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_055_CHIP2POD_MDO6 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_055_RMXP_DATA6 2
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_055_EBI_ADDR_24 3
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_055_ALT_TP_IN_30 4
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_055_PM_GPIO_055 5
-
-/* SUN_TOP_CTRL :: PIN_MUX_CTRL_9 :: gpio_054 [15:12] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_054_MASK 0x0000f000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_054_SHIFT 12
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_054_DEFAULT 0x00000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_054_GPIO_054 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_054_CHIP2POD_MDO5 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_054_RMXP_DATA5 2
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_054_EBI_ADDR_23 3
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_054_SC1_VPP 4
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_054_ALT_TP_IN_29 5
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_054_PM_GPIO_054 6
-
-/* SUN_TOP_CTRL :: PIN_MUX_CTRL_9 :: gpio_053 [11:08] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_053_MASK 0x00000f00
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_053_SHIFT 8
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_053_DEFAULT 0x00000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_053_GPIO_053 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_053_CHIP2POD_MDO4 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_053_RMXP_DATA4 2
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_053_EBI_ADDR_22 3
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_053_SC1_AUX2 4
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_053_ALT_TP_IN_28 5
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_053_PM_GPIO_053 6
-
-/* SUN_TOP_CTRL :: PIN_MUX_CTRL_9 :: gpio_052 [07:04] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_052_MASK 0x000000f0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_052_SHIFT 4
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_052_DEFAULT 0x00000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_052_GPIO_052 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_052_CHIP2POD_MDO3 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_052_RMXP_DATA3 2
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_052_EBI_ADDR_21 3
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_052_SC1_AUX1 4
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_052_ALT_TP_IN_27 5
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_052_PM_GPIO_052 6
-
-/* SUN_TOP_CTRL :: PIN_MUX_CTRL_9 :: gpio_051 [03:00] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_051_MASK 0x0000000f
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_051_SHIFT 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_051_DEFAULT 0x00000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_051_GPIO_051 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_051_CHIP2POD_MDO2 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_051_RMXP_DATA2 2
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_051_EBI_ADDR_20 3
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_051_SC1_PRES 4
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_051_ALT_TP_IN_26 5
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_051_PM_GPIO_051 6
-
-/***************************************************************************
- *PIN_MUX_CTRL_10 - Pinmux control register 10
- ***************************************************************************/
-/* SUN_TOP_CTRL :: PIN_MUX_CTRL_10 :: gpio_066 [31:28] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_066_MASK 0xf0000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_066_SHIFT 28
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_066_DEFAULT 0x00000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_066_GPIO_066 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_066_MTSIF0_CLK 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_066_PKT_CLK2 2
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_066_UART_CTS_0 3
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_066_EXT_IRQB_0 4
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_066_PM_GPIO_066 5
-
-/* SUN_TOP_CTRL :: PIN_MUX_CTRL_10 :: gpio_065 [27:24] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_065_MASK 0x0f000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_065_SHIFT 24
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_065_DEFAULT 0x00000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_065_GPIO_065 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_065_SC0_VPP 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_065_I2S_LR0_OUT 2
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_065_I2S_LR0_IN 3
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_065_TP_OUT_24 4
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_065_PM_GPIO_065 5
-
-/* SUN_TOP_CTRL :: PIN_MUX_CTRL_10 :: gpio_064 [23:20] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_064_MASK 0x00f00000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_064_SHIFT 20
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_064_DEFAULT 0x00000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_064_GPIO_064 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_064_SC0_AUX2 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_064_I2S_DATA0_OUT 2
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_064_I2S_DATA0_IN 3
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_064_TP_OUT_23 4
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_064_PM_GPIO_064 5
-
-/* SUN_TOP_CTRL :: PIN_MUX_CTRL_10 :: gpio_063 [19:16] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_063_MASK 0x000f0000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_063_SHIFT 16
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_063_DEFAULT 0x00000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_063_GPIO_063 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_063_SC0_AUX1 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_063_I2S_CLK0_OUT 2
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_063_I2S_CLK0_IN 3
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_063_TP_OUT_22 4
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_063_PM_GPIO_063 5
-
-/* SUN_TOP_CTRL :: PIN_MUX_CTRL_10 :: gpio_062 [15:12] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_062_MASK 0x0000f000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_062_SHIFT 12
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_062_DEFAULT 0x00000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_062_GPIO_062 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_062_SC0_PRES 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_062_TP_OUT_21 2
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_062_PM_GPIO_062 3
-
-/* SUN_TOP_CTRL :: PIN_MUX_CTRL_10 :: gpio_061 [11:08] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_061_MASK 0x00000f00
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_061_SHIFT 8
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_061_DEFAULT 0x00000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_061_GPIO_061 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_061_SC0_IO 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_061_IR_IN1 2
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_061_TP_OUT_20 3
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_061_PM_GPIO_061 4
-
-/* SUN_TOP_CTRL :: PIN_MUX_CTRL_10 :: gpio_060 [07:04] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_060_MASK 0x000000f0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_060_SHIFT 4
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_060_DEFAULT 0x00000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_060_GPIO_060 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_060_SC0_RST 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_060_TP_OUT_19 2
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_060_PM_GPIO_060 3
-
-/* SUN_TOP_CTRL :: PIN_MUX_CTRL_10 :: gpio_059 [03:00] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_059_MASK 0x0000000f
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_059_SHIFT 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_059_DEFAULT 0x00000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_059_GPIO_059 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_059_SC0_CLK 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_059_TP_OUT_18 2
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_059_PM_GPIO_059 3
-
-/***************************************************************************
- *PIN_MUX_CTRL_11 - Pinmux control register 11
- ***************************************************************************/
-/* SUN_TOP_CTRL :: PIN_MUX_CTRL_11 :: gpio_074 [31:28] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_074_MASK 0xf0000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_074_SHIFT 28
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_074_DEFAULT 0x00000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_074_GPIO_074 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_074_MTSIF0_DATA5 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_074_UART_RXD_2 3
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_074_ALT_TP_IN_14 4
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_074_PM_GPIO_074 5
-
-/* SUN_TOP_CTRL :: PIN_MUX_CTRL_11 :: gpio_073 [27:24] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_073_MASK 0x0f000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_073_SHIFT 24
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_073_DEFAULT 0x00000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_073_GPIO_073 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_073_MTSIF0_DATA4 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_073_UART_TXD_1 3
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_073_ALT_TP_OUT_14 4
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_073_PM_GPIO_073 5
-
-/* SUN_TOP_CTRL :: PIN_MUX_CTRL_11 :: gpio_072 [23:20] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_072_MASK 0x00f00000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_072_SHIFT 20
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_072_DEFAULT 0x00000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_072_GPIO_072 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_072_MTSIF0_DATA3 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_072_UART_RXD_1 3
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_072_EXT_IRQB_5 4
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_072_ALT_TP_IN_13 5
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_072_PM_GPIO_072 6
-
-/* SUN_TOP_CTRL :: PIN_MUX_CTRL_11 :: gpio_071 [19:16] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_071_MASK 0x000f0000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_071_SHIFT 16
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_071_DEFAULT 0x00000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_071_GPIO_071 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_071_MTSIF0_DATA2 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_071_UART_RTS_1 3
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_071_EXT_IRQB_4 4
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_071_PM_GPIO_071 5
-
-/* SUN_TOP_CTRL :: PIN_MUX_CTRL_11 :: gpio_070 [15:12] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_070_MASK 0x0000f000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_070_SHIFT 12
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_070_DEFAULT 0x00000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_070_GPIO_070 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_070_MTSIF0_VALID 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_070_PKT_VALID2 2
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_070_UART_CTS_1 3
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_070_EXT_IRQB_3 4
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_070_PM_GPIO_070 5
-
-/* SUN_TOP_CTRL :: PIN_MUX_CTRL_11 :: gpio_069 [11:08] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_069_MASK 0x00000f00
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_069_SHIFT 8
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_069_DEFAULT 0x00000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_069_GPIO_069 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_069_MTSIF0_DATA1 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_069_PKT_ERROR2 2
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_069_UART_TXD_0 3
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_069_IR_IN1 4
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_069_ALT_TP_OUT_19 5
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_069_PM_GPIO_069 6
-
-/* SUN_TOP_CTRL :: PIN_MUX_CTRL_11 :: gpio_068 [07:04] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_068_MASK 0x000000f0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_068_SHIFT 4
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_068_DEFAULT 0x00000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_068_GPIO_068 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_068_MTSIF0_SYNC 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_068_PKT_SYNC2 2
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_068_UART_RXD_0 3
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_068_EXT_IRQB_2 4
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_068_ALT_TP_IN_12 5
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_068_PM_GPIO_068 6
-
-/* SUN_TOP_CTRL :: PIN_MUX_CTRL_11 :: gpio_067 [03:00] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_067_MASK 0x0000000f
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_067_SHIFT 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_067_DEFAULT 0x00000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_067_GPIO_067 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_067_MTSIF0_DATA0 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_067_PKT_DATA2 2
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_067_UART_RTS_0 3
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_067_EXT_IRQB_1 4
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_067_PM_GPIO_067 5
-
-/***************************************************************************
- *PIN_MUX_CTRL_12 - Pinmux control register 12
- ***************************************************************************/
-/* SUN_TOP_CTRL :: PIN_MUX_CTRL_12 :: gpio_082 [31:28] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_082_MASK 0xf0000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_082_SHIFT 28
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_082_DEFAULT 0x00000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_082_GPIO_082 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_082_RGMII_A_RXD_01 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_082_PKT_ERROR0_ALT 2
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_082_VO0_656_3 3
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_082_UART_RTS_0 4
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_082_ALT_TP_OUT_26 5
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_082_PM_GPIO_082 6
-
-/* SUN_TOP_CTRL :: PIN_MUX_CTRL_12 :: gpio_081 [27:24] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_081_MASK 0x0f000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_081_SHIFT 24
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_081_DEFAULT 0x00000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_081_GPIO_081 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_081_RGMII_A_RXD_00 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_081_PKT_SYNC0_ALT 2
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_081_VO0_656_2 3
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_081_UART_CTS_0 4
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_081_ALT_TP_OUT_25 5
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_081_PM_GPIO_081 6
-
-/* SUN_TOP_CTRL :: PIN_MUX_CTRL_12 :: gpio_080 [23:20] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_080_MASK 0x00f00000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_080_SHIFT 20
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_080_DEFAULT 0x00000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_080_GPIO_080 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_080_RGMII_A_RX_EN_CTL 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_080_PKT_DATA0_ALT 2
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_080_VO0_656_1 3
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_080_ALT_TP_OUT_24 4
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_080_PM_GPIO_080 5
-
-/* SUN_TOP_CTRL :: PIN_MUX_CTRL_12 :: gpio_079 [19:16] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_079_MASK 0x000f0000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_079_SHIFT 16
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_079_DEFAULT 0x00000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_079_GPIO_079 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_079_RGMII_A_RX_CLK 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_079_PKT_CLK0_ALT 2
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_079_VO0_656_0 3
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_079_IR_IN1 4
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_079_ALT_TP_OUT_23 5
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_079_PM_GPIO_079 6
-
-/* SUN_TOP_CTRL :: PIN_MUX_CTRL_12 :: gpio_078 [15:12] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_078_MASK 0x0000f000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_078_SHIFT 12
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_078_DEFAULT 0x00000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_078_GPIO_078 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_078_MTSIF_ATS_RST 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_078_ALT_TP_OUT_22 2
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_078_PM_GPIO_078 3
-
-/* SUN_TOP_CTRL :: PIN_MUX_CTRL_12 :: gpio_077 [11:08] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_077_MASK 0x00000f00
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_077_SHIFT 8
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_077_DEFAULT 0x00000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_077_GPIO_077 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_077_MTSIF_ATS_INC 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_077_UART_RTS_2 2
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_077_ALT_TP_OUT_21 3
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_077_PM_GPIO_077 4
-
-/* SUN_TOP_CTRL :: PIN_MUX_CTRL_12 :: gpio_076 [07:04] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_076_MASK 0x000000f0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_076_SHIFT 4
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_076_DEFAULT 0x00000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_076_GPIO_076 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_076_MTSIF0_DATA7 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_076_UART_CTS_2 2
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_076_ALT_TP_OUT_20 3
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_076_PM_GPIO_076 4
-
-/* SUN_TOP_CTRL :: PIN_MUX_CTRL_12 :: gpio_075 [03:00] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_075_MASK 0x0000000f
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_075_SHIFT 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_075_DEFAULT 0x00000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_075_GPIO_075 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_075_MTSIF0_DATA6 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_075_UART_TXD_2 3
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_075_ALT_TP_OUT_15 4
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_075_PM_GPIO_075 5
-
-/***************************************************************************
- *PIN_MUX_CTRL_13 - Pinmux control register 13
- ***************************************************************************/
-/* SUN_TOP_CTRL :: PIN_MUX_CTRL_13 :: gpio_090 [31:28] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_090_MASK 0xf0000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_090_SHIFT 28
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_090_DEFAULT 0x00000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_090_GPIO_090 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_090_RGMII_A_TXD_03 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_090_VEC_VSYNC 2
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_090_UART_RTS_2 3
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_090_PM_GPIO_090 4
-
-/* SUN_TOP_CTRL :: PIN_MUX_CTRL_13 :: gpio_089 [27:24] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_089_MASK 0x0f000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_089_SHIFT 24
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_089_DEFAULT 0x00000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_089_GPIO_089 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_089_RGMII_A_TXD_02 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_089_VEC_HSYNC 2
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_089_TTX0_REQ 3
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_089_UART_CTS_2 4
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_089_PM_GPIO_089 5
-
-/* SUN_TOP_CTRL :: PIN_MUX_CTRL_13 :: gpio_088 [23:20] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_088_MASK 0x00f00000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_088_SHIFT 20
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_088_DEFAULT 0x00000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_088_GPIO_088 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_088_RGMII_A_TXD_01 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_088_PKT_VALID1 2
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_088_TTX0_DATA 3
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_088_UART_TXD_2 4
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_088_ALT_TP_OUT_17 5
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_088_PM_GPIO_088 6
-
-/* SUN_TOP_CTRL :: PIN_MUX_CTRL_13 :: gpio_087 [19:16] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_087_MASK 0x000f0000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_087_SHIFT 16
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_087_DEFAULT 0x00000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_087_GPIO_087 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_087_RGMII_A_TXD_00 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_087_PKT_ERROR1 2
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_087_VO0_656_CLK 3
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_087_UART_RXD_2 4
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_087_ALT_TP_IN_16 5
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_087_PM_GPIO_087 6
-
-/* SUN_TOP_CTRL :: PIN_MUX_CTRL_13 :: gpio_086 [15:12] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_086_MASK 0x0000f000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_086_SHIFT 12
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_086_DEFAULT 0x00000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_086_GPIO_086 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_086_RGMII_A_TX_EN_CTL 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_086_PKT_SYNC1 2
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_086_VO0_656_7 3
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_086_UART_RTS_1 4
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_086_PM_GPIO_086 5
-
-/* SUN_TOP_CTRL :: PIN_MUX_CTRL_13 :: gpio_085 [11:08] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_085_MASK 0x00000f00
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_085_SHIFT 8
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_085_DEFAULT 0x00000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_085_GPIO_085 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_085_RGMII_A_TX_CLK 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_085_PKT_DATA1 2
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_085_VO0_656_6 3
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_085_UART_CTS_1 4
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_085_PM_GPIO_085 5
-
-/* SUN_TOP_CTRL :: PIN_MUX_CTRL_13 :: gpio_084 [07:04] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_084_MASK 0x000000f0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_084_SHIFT 4
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_084_DEFAULT 0x00000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_084_GPIO_084 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_084_RGMII_A_RXD_03 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_084_PKT_CLK1 2
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_084_VO0_656_5 3
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_084_UART_TXD_1 4
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_084_ALT_TP_OUT_16 5
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_084_PM_GPIO_084 6
-
-/* SUN_TOP_CTRL :: PIN_MUX_CTRL_13 :: gpio_083 [03:00] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_083_MASK 0x0000000f
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_083_SHIFT 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_083_DEFAULT 0x00000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_083_GPIO_083 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_083_RGMII_A_RXD_02 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_083_PKT_VALID0_ALT 2
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_083_VO0_656_4 3
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_083_UART_RXD_1 4
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_083_ALT_TP_IN_15 5
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_083_PM_GPIO_083 6
-
-/***************************************************************************
- *PIN_MUX_CTRL_14 - Pinmux control register 14
- ***************************************************************************/
-/* SUN_TOP_CTRL :: PIN_MUX_CTRL_14 :: gpio_098 [31:28] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_098_MASK 0xf0000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_098_SHIFT 28
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_098_DEFAULT 0x00000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_098_GPIO_098 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_098_SD_CARD0_CMD 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_098_PKT_CLK1_ALT 2
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_098_UART_CTS_0 3
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_098_EXT_IRQB_5 4
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_098_TP_OUT_25 5
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_098_PM_GPIO_098 6
-
-/* SUN_TOP_CTRL :: PIN_MUX_CTRL_14 :: gpio_097 [27:24] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_097_MASK 0x0f000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_097_SHIFT 24
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_097_DEFAULT 0x00000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_097_GPIO_097 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_097_MII_A_COL 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_097_MII_B_COL 2
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_097_SPI_M_SS1B 3
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_097_RMX_PAUSE0 4
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_097_ALT_TP_OUT_31 5
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_097_PM_GPIO_097 6
-
-/* SUN_TOP_CTRL :: PIN_MUX_CTRL_14 :: gpio_096 [23:20] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_096_MASK 0x00f00000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_096_SHIFT 20
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_096_DEFAULT 0x00000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_096_GPIO_096 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_096_MII_A_CRS 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_096_MII_B_CRS 2
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_096_SPI_M_MISO 3
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_096_RMX_VALID0 4
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_096_ALT_TP_OUT_30 5
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_096_PM_GPIO_096 6
-
-/* SUN_TOP_CTRL :: PIN_MUX_CTRL_14 :: gpio_095 [19:16] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_095_MASK 0x000f0000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_095_SHIFT 16
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_095_DEFAULT 0x00000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_095_GPIO_095 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_095_RGMIIA_IRQ 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_095_SPI_M_SCK 2
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_095_I2S_LR0_OUT 3
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_095_RMX_SYNC0 4
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_095_ALT_TP_OUT_29 5
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_095_PM_GPIO_095 6
-
-/* SUN_TOP_CTRL :: PIN_MUX_CTRL_14 :: gpio_094 [15:12] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_094_MASK 0x0000f000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_094_SHIFT 12
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_094_DEFAULT 0x00000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_094_GPIO_094 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_094_MII_A_TX_ERR 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_094_MII_B_TX_ERR 2
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_094_SPI_M_SS0B 3
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_094_I2S_DATA0_OUT 4
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_094_RMX_DATA0 5
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_094_ENET0_ACTIVITY 6
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_094_ALT_TP_OUT_28 7
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_094_PM_GPIO_094 8
-
-/* SUN_TOP_CTRL :: PIN_MUX_CTRL_14 :: gpio_093 [11:08] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_093_MASK 0x00000f00
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_093_SHIFT 8
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_093_DEFAULT 0x00000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_093_GPIO_093 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_093_MII_A_RX_ERR 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_093_MII_B_RX_ERR 2
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_093_SPI_M_MOSI 3
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_093_I2S_CLK0_OUT 4
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_093_RMX_CLK0 5
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_093_ENET0_LINK 6
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_093_ALT_TP_OUT_27 7
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_093_PM_GPIO_093 8
-
-/* SUN_TOP_CTRL :: PIN_MUX_CTRL_14 :: gpio_092 [07:04] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_092_MASK 0x000000f0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_092_SHIFT 4
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_092_DEFAULT 0x00000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_092_GPIO_092 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_092_RGMII_A_MDC 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_092_UART_TXD_0 2
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_092_ALT_TP_OUT_18 3
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_092_PM_GPIO_092 4
-
-/* SUN_TOP_CTRL :: PIN_MUX_CTRL_14 :: gpio_091 [03:00] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_091_MASK 0x0000000f
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_091_SHIFT 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_091_DEFAULT 0x00000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_091_GPIO_091 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_091_RGMII_A_MDIO 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_091_UART_RXD_0 2
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_091_ALT_TP_IN_17 3
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_091_PM_GPIO_091 4
-
-/***************************************************************************
- *PIN_MUX_CTRL_15 - Pinmux control register 15
- ***************************************************************************/
-/* SUN_TOP_CTRL :: PIN_MUX_CTRL_15 :: gpio_106 [31:28] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_106_MASK 0xf0000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_106_SHIFT 28
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_106_DEFAULT 0x00000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_106_GPIO_106 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_106_SD_CARD0_CLK_IN 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_106_RMX_SYNC1 2
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_106_UART_CTS_2 3
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_106_PWM0 4
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_106_TP_OUT_04 5
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_106_PM_GPIO_106 6
-
-/* SUN_TOP_CTRL :: PIN_MUX_CTRL_15 :: gpio_105 [27:24] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_105_MASK 0x0f000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_105_SHIFT 24
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_105_DEFAULT 0x00000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_105_GPIO_105 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_105_SD_CARD0_LED 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_105_RMX_DATA1 2
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_105_UART_TXD_2 3
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_105_PWM1 4
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_105_AUD_FS_CLK0 5
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_105_SC_CLK_OUT 6
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_105_ALT_TP_OUT_06 7
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_105_PM_GPIO_105 8
-
-/* SUN_TOP_CTRL :: PIN_MUX_CTRL_15 :: gpio_104 [23:20] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_104_MASK 0x00f00000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_104_SHIFT 20
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_104_DEFAULT 0x00000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_104_GPIO_104 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_104_SD_CARD0_PRES 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_104_RMX_CLK1 2
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_104_UART_RXD_2 3
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_104_IR_IN1 4
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_104_TP_IN_29 5
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_104_PM_GPIO_104 6
-
-/* SUN_TOP_CTRL :: PIN_MUX_CTRL_15 :: gpio_103 [19:16] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_103_MASK 0x000f0000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_103_SHIFT 16
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_103_DEFAULT 0x00000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_103_GPIO_103 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_103_SD_CARD0_DAT3 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_103_UART_RTS_1 2
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_103_EXT_IRQB_4 3
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_103_CPU_TRACE_DATA3 4
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_103_TP_OUT_29 5
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_103_PM_GPIO_103 6
-
-/* SUN_TOP_CTRL :: PIN_MUX_CTRL_15 :: gpio_102 [15:12] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_102_MASK 0x0000f000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_102_SHIFT 12
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_102_DEFAULT 0x00000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_102_GPIO_102 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_102_SD_CARD0_DAT2 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_102_PKT_VALID1_ALT 2
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_102_UART_CTS_1 3
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_102_EXT_IRQB_3 4
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_102_CPU_TRACE_DATA2 5
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_102_TP_OUT_28 6
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_102_PM_GPIO_102 7
-
-/* SUN_TOP_CTRL :: PIN_MUX_CTRL_15 :: gpio_101 [11:08] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_101_MASK 0x00000f00
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_101_SHIFT 8
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_101_DEFAULT 0x00000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_101_GPIO_101 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_101_SD_CARD0_DAT1 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_101_PKT_ERROR1_ALT 2
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_101_UART_TXD_1 3
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_101_EXT_IRQB_2 4
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_101_CPU_TRACE_DATA1 5
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_101_ALT_TP_OUT_05 6
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_101_PM_GPIO_101 7
-
-/* SUN_TOP_CTRL :: PIN_MUX_CTRL_15 :: gpio_100 [07:04] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_100_MASK 0x000000f0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_100_SHIFT 4
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_100_DEFAULT 0x00000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_100_GPIO_100 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_100_SD_CARD0_DAT0 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_100_PKT_SYNC1_ALT 2
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_100_UART_RXD_1 3
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_100_EXT_IRQB_1 4
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_100_CPU_TRACE_DATA0 5
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_100_TP_IN_30 6
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_100_PM_GPIO_100 7
-
-/* SUN_TOP_CTRL :: PIN_MUX_CTRL_15 :: gpio_099 [03:00] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_099_MASK 0x0000000f
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_099_SHIFT 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_099_DEFAULT 0x00000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_099_GPIO_099 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_099_SD_CARD0_CLK 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_099_PKT_DATA1_ALT 2
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_099_UART_RTS_0 3
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_099_EXT_IRQB_0 4
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_099_CPU_TRACE_CLK 5
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_099_TP_OUT_26 6
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_099_PM_GPIO_099 7
-
-/***************************************************************************
- *PIN_MUX_CTRL_16 - Pinmux control register 16
- ***************************************************************************/
-/* SUN_TOP_CTRL :: PIN_MUX_CTRL_16 :: sgpio_02 [31:28] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_sgpio_02_MASK 0xf0000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_sgpio_02_SHIFT 28
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_sgpio_02_DEFAULT 0x00000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_sgpio_02_SGPIO_02 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_sgpio_02_BSC_M5_SCL 1
-
-/* SUN_TOP_CTRL :: PIN_MUX_CTRL_16 :: sgpio_01 [27:24] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_sgpio_01_MASK 0x0f000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_sgpio_01_SHIFT 24
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_sgpio_01_DEFAULT 0x00000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_sgpio_01_SGPIO_01 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_sgpio_01_BSC_M4_SDA 1
-
-/* SUN_TOP_CTRL :: PIN_MUX_CTRL_16 :: sgpio_00 [23:20] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_sgpio_00_MASK 0x00f00000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_sgpio_00_SHIFT 20
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_sgpio_00_DEFAULT 0x00000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_sgpio_00_SGPIO_00 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_sgpio_00_BSC_M4_SCL 1
-
-/* SUN_TOP_CTRL :: PIN_MUX_CTRL_16 :: gpio_111 [19:16] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_111_MASK 0x000f0000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_111_SHIFT 16
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_111_DEFAULT 0x00000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_111_GPIO_111 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_111_UART_RXD_0 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_111_EXT_SC_CLK 2
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_111_AUD_FS_CLK0 3
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_111_SPI_S_SS0B 4
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_111_ALT_TP_IN_31 5
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_111_PM_GPIO_111 6
-
-/* SUN_TOP_CTRL :: PIN_MUX_CTRL_16 :: gpio_110 [15:12] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_110_MASK 0x0000f000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_110_SHIFT 12
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_110_DEFAULT 0x00000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_110_GPIO_110 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_110_UART_TXD_0 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_110_SC_CLK_OUT 2
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_110_IR_INT 3
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_110_SPI_S_MISO 4
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_110_ALT_TP_OUT_07 5
-
-/* SUN_TOP_CTRL :: PIN_MUX_CTRL_16 :: gpio_109 [11:08] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_109_MASK 0x00000f00
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_109_SHIFT 8
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_109_DEFAULT 0x00000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_109_GPIO_109 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_109_SD_CARD0_VOLT 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_109_ALT_TP_OUT_09 2
-
-/* SUN_TOP_CTRL :: PIN_MUX_CTRL_16 :: gpio_108 [07:04] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_108_MASK 0x000000f0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_108_SHIFT 4
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_108_DEFAULT 0x00000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_108_GPIO_108 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_108_SD_CARD0_PWR0 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_108_RMX_VALID1 2
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_108_PWM2 3
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_108_ALT_TP_OUT_08 4
-
-/* SUN_TOP_CTRL :: PIN_MUX_CTRL_16 :: gpio_107 [03:00] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_107_MASK 0x0000000f
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_107_SHIFT 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_107_DEFAULT 0x00000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_107_GPIO_107 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_107_SD_CARD0_WPROT 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_107_RMX_PAUSE1 2
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_107_UART_RTS_2 3
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_107_PWM3 4
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_107_TP_OUT_05 5
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_107_PM_GPIO_107 6
-
-/***************************************************************************
- *PIN_MUX_CTRL_17 - Pinmux control register 17
- ***************************************************************************/
-/* SUN_TOP_CTRL :: PIN_MUX_CTRL_17 :: reserved0 [31:20] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_reserved0_MASK 0xfff00000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_reserved0_SHIFT 20
-
-/* SUN_TOP_CTRL :: PIN_MUX_CTRL_17 :: byp_clk_1 [19:16] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_byp_clk_1_MASK 0x000f0000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_byp_clk_1_SHIFT 16
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_byp_clk_1_DEFAULT 0x00000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_byp_clk_1_BYP_CLK_1 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_byp_clk_1_OBSRV_CLK_1 1
-
-/* SUN_TOP_CTRL :: PIN_MUX_CTRL_17 :: byp_clk_0 [15:12] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_byp_clk_0_MASK 0x0000f000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_byp_clk_0_SHIFT 12
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_byp_clk_0_DEFAULT 0x00000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_byp_clk_0_BYP_CLK_0 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_byp_clk_0_OBSRV_CLK_0 1
-
-/* SUN_TOP_CTRL :: PIN_MUX_CTRL_17 :: sgpio_05 [11:08] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_sgpio_05_MASK 0x00000f00
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_sgpio_05_SHIFT 8
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_sgpio_05_DEFAULT 0x00000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_sgpio_05_SGPIO_05 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_sgpio_05_MOCA_BSC_SDA 1
-
-/* SUN_TOP_CTRL :: PIN_MUX_CTRL_17 :: sgpio_04 [07:04] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_sgpio_04_MASK 0x000000f0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_sgpio_04_SHIFT 4
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_sgpio_04_DEFAULT 0x00000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_sgpio_04_SGPIO_04 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_sgpio_04_MOCA_BSC_SCL 1
-
-/* SUN_TOP_CTRL :: PIN_MUX_CTRL_17 :: sgpio_03 [03:00] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_sgpio_03_MASK 0x0000000f
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_sgpio_03_SHIFT 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_sgpio_03_DEFAULT 0x00000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_sgpio_03_SGPIO_03 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_sgpio_03_BSC_M5_SDA 1
-
-/***************************************************************************
- *PIN_MUX_PAD_CTRL_0 - Pad pull-up/pull-down control register 0
- ***************************************************************************/
-/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_0 :: spare_pad_ctrl_0 [31:30] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_spare_pad_ctrl_0_MASK 0xc0000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_spare_pad_ctrl_0_SHIFT 30
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_spare_pad_ctrl_0_DEFAULT 0x00000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_spare_pad_ctrl_0_PULL_NONE 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_spare_pad_ctrl_0_PULL_DOWN 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_spare_pad_ctrl_0_PULL_UP 2
-
-/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_0 :: emmc_cmd_pad_ctrl [29:28] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_emmc_cmd_pad_ctrl_MASK 0x30000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_emmc_cmd_pad_ctrl_SHIFT 28
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_emmc_cmd_pad_ctrl_DEFAULT 0x00000002
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_emmc_cmd_pad_ctrl_PULL_NONE 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_emmc_cmd_pad_ctrl_PULL_DOWN 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_emmc_cmd_pad_ctrl_PULL_UP 2
-
-/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_0 :: sf_wpb_pad_ctrl [27:26] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_sf_wpb_pad_ctrl_MASK 0x0c000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_sf_wpb_pad_ctrl_SHIFT 26
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_sf_wpb_pad_ctrl_DEFAULT 0x00000002
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_sf_wpb_pad_ctrl_PULL_NONE 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_sf_wpb_pad_ctrl_PULL_DOWN 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_sf_wpb_pad_ctrl_PULL_UP 2
-
-/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_0 :: sf_holdb_pad_ctrl [25:24] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_sf_holdb_pad_ctrl_MASK 0x03000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_sf_holdb_pad_ctrl_SHIFT 24
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_sf_holdb_pad_ctrl_DEFAULT 0x00000002
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_sf_holdb_pad_ctrl_PULL_NONE 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_sf_holdb_pad_ctrl_PULL_DOWN 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_sf_holdb_pad_ctrl_PULL_UP 2
-
-/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_0 :: sf_mosi_pad_ctrl [23:22] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_sf_mosi_pad_ctrl_MASK 0x00c00000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_sf_mosi_pad_ctrl_SHIFT 22
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_sf_mosi_pad_ctrl_DEFAULT 0x00000002
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_sf_mosi_pad_ctrl_PULL_NONE 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_sf_mosi_pad_ctrl_PULL_DOWN 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_sf_mosi_pad_ctrl_PULL_UP 2
-
-/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_0 :: sf_miso_pad_ctrl [21:20] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_sf_miso_pad_ctrl_MASK 0x00300000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_sf_miso_pad_ctrl_SHIFT 20
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_sf_miso_pad_ctrl_DEFAULT 0x00000002
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_sf_miso_pad_ctrl_PULL_NONE 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_sf_miso_pad_ctrl_PULL_DOWN 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_sf_miso_pad_ctrl_PULL_UP 2
-
-/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_0 :: sf_sck_pad_ctrl [19:18] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_sf_sck_pad_ctrl_MASK 0x000c0000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_sf_sck_pad_ctrl_SHIFT 18
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_sf_sck_pad_ctrl_DEFAULT 0x00000002
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_sf_sck_pad_ctrl_PULL_NONE 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_sf_sck_pad_ctrl_PULL_DOWN 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_sf_sck_pad_ctrl_PULL_UP 2
-
-/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_0 :: reserved0 [17:06] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_reserved0_MASK 0x0003ffc0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_reserved0_SHIFT 6
-
-/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_0 :: pcie_clkreqb_pad_ctrl [05:04] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_pcie_clkreqb_pad_ctrl_MASK 0x00000030
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_pcie_clkreqb_pad_ctrl_SHIFT 4
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_pcie_clkreqb_pad_ctrl_DEFAULT 0x00000002
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_pcie_clkreqb_pad_ctrl_PULL_NONE 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_pcie_clkreqb_pad_ctrl_PULL_DOWN 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_pcie_clkreqb_pad_ctrl_PULL_UP 2
-
-/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_0 :: pcie_rstb_pad_ctrl [03:02] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_pcie_rstb_pad_ctrl_MASK 0x0000000c
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_pcie_rstb_pad_ctrl_SHIFT 2
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_pcie_rstb_pad_ctrl_DEFAULT 0x00000001
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_pcie_rstb_pad_ctrl_PULL_NONE 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_pcie_rstb_pad_ctrl_PULL_DOWN 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_pcie_rstb_pad_ctrl_PULL_UP 2
-
-/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_0 :: reserved1 [01:00] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_reserved1_MASK 0x00000003
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_reserved1_SHIFT 0
-
-/***************************************************************************
- *PIN_MUX_PAD_CTRL_1 - Pad pull-up/pull-down control register 1
- ***************************************************************************/
-/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_1 :: spare_pad_ctrl_1 [31:30] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_spare_pad_ctrl_1_MASK 0xc0000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_spare_pad_ctrl_1_SHIFT 30
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_spare_pad_ctrl_1_DEFAULT 0x00000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_spare_pad_ctrl_1_PULL_NONE 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_spare_pad_ctrl_1_PULL_DOWN 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_spare_pad_ctrl_1_PULL_UP 2
-
-/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_1 :: ebi_cs5b_pad_ctrl [29:28] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_ebi_cs5b_pad_ctrl_MASK 0x30000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_ebi_cs5b_pad_ctrl_SHIFT 28
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_ebi_cs5b_pad_ctrl_DEFAULT 0x00000002
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_ebi_cs5b_pad_ctrl_PULL_NONE 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_ebi_cs5b_pad_ctrl_PULL_DOWN 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_ebi_cs5b_pad_ctrl_PULL_UP 2
-
-/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_1 :: ebi_cs4b_pad_ctrl [27:26] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_ebi_cs4b_pad_ctrl_MASK 0x0c000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_ebi_cs4b_pad_ctrl_SHIFT 26
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_ebi_cs4b_pad_ctrl_DEFAULT 0x00000002
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_ebi_cs4b_pad_ctrl_PULL_NONE 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_ebi_cs4b_pad_ctrl_PULL_DOWN 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_ebi_cs4b_pad_ctrl_PULL_UP 2
-
-/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_1 :: ebi_cs3b_pad_ctrl [25:24] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_ebi_cs3b_pad_ctrl_MASK 0x03000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_ebi_cs3b_pad_ctrl_SHIFT 24
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_ebi_cs3b_pad_ctrl_DEFAULT 0x00000002
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_ebi_cs3b_pad_ctrl_PULL_NONE 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_ebi_cs3b_pad_ctrl_PULL_DOWN 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_ebi_cs3b_pad_ctrl_PULL_UP 2
-
-/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_1 :: ebi_cs2b_pad_ctrl [23:22] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_ebi_cs2b_pad_ctrl_MASK 0x00c00000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_ebi_cs2b_pad_ctrl_SHIFT 22
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_ebi_cs2b_pad_ctrl_DEFAULT 0x00000002
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_ebi_cs2b_pad_ctrl_PULL_NONE 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_ebi_cs2b_pad_ctrl_PULL_DOWN 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_ebi_cs2b_pad_ctrl_PULL_UP 2
-
-/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_1 :: ebi_cs1b_pad_ctrl [21:20] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_ebi_cs1b_pad_ctrl_MASK 0x00300000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_ebi_cs1b_pad_ctrl_SHIFT 20
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_ebi_cs1b_pad_ctrl_DEFAULT 0x00000002
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_ebi_cs1b_pad_ctrl_PULL_NONE 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_ebi_cs1b_pad_ctrl_PULL_DOWN 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_ebi_cs1b_pad_ctrl_PULL_UP 2
-
-/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_1 :: ebi_cs0b_pad_ctrl [19:18] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_ebi_cs0b_pad_ctrl_MASK 0x000c0000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_ebi_cs0b_pad_ctrl_SHIFT 18
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_ebi_cs0b_pad_ctrl_DEFAULT 0x00000002
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_ebi_cs0b_pad_ctrl_PULL_NONE 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_ebi_cs0b_pad_ctrl_PULL_DOWN 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_ebi_cs0b_pad_ctrl_PULL_UP 2
-
-/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_1 :: ebi_data_07_pad_ctrl [17:16] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_ebi_data_07_pad_ctrl_MASK 0x00030000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_ebi_data_07_pad_ctrl_SHIFT 16
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_ebi_data_07_pad_ctrl_DEFAULT 0x00000002
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_ebi_data_07_pad_ctrl_PULL_NONE 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_ebi_data_07_pad_ctrl_PULL_DOWN 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_ebi_data_07_pad_ctrl_PULL_UP 2
-
-/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_1 :: ebi_data_06_pad_ctrl [15:14] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_ebi_data_06_pad_ctrl_MASK 0x0000c000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_ebi_data_06_pad_ctrl_SHIFT 14
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_ebi_data_06_pad_ctrl_DEFAULT 0x00000002
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_ebi_data_06_pad_ctrl_PULL_NONE 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_ebi_data_06_pad_ctrl_PULL_DOWN 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_ebi_data_06_pad_ctrl_PULL_UP 2
-
-/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_1 :: ebi_data_05_pad_ctrl [13:12] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_ebi_data_05_pad_ctrl_MASK 0x00003000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_ebi_data_05_pad_ctrl_SHIFT 12
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_ebi_data_05_pad_ctrl_DEFAULT 0x00000002
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_ebi_data_05_pad_ctrl_PULL_NONE 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_ebi_data_05_pad_ctrl_PULL_DOWN 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_ebi_data_05_pad_ctrl_PULL_UP 2
-
-/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_1 :: ebi_data_04_pad_ctrl [11:10] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_ebi_data_04_pad_ctrl_MASK 0x00000c00
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_ebi_data_04_pad_ctrl_SHIFT 10
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_ebi_data_04_pad_ctrl_DEFAULT 0x00000002
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_ebi_data_04_pad_ctrl_PULL_NONE 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_ebi_data_04_pad_ctrl_PULL_DOWN 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_ebi_data_04_pad_ctrl_PULL_UP 2
-
-/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_1 :: ebi_data_03_pad_ctrl [09:08] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_ebi_data_03_pad_ctrl_MASK 0x00000300
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_ebi_data_03_pad_ctrl_SHIFT 8
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_ebi_data_03_pad_ctrl_DEFAULT 0x00000002
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_ebi_data_03_pad_ctrl_PULL_NONE 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_ebi_data_03_pad_ctrl_PULL_DOWN 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_ebi_data_03_pad_ctrl_PULL_UP 2
-
-/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_1 :: ebi_data_02_pad_ctrl [07:06] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_ebi_data_02_pad_ctrl_MASK 0x000000c0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_ebi_data_02_pad_ctrl_SHIFT 6
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_ebi_data_02_pad_ctrl_DEFAULT 0x00000002
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_ebi_data_02_pad_ctrl_PULL_NONE 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_ebi_data_02_pad_ctrl_PULL_DOWN 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_ebi_data_02_pad_ctrl_PULL_UP 2
-
-/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_1 :: ebi_data_01_pad_ctrl [05:04] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_ebi_data_01_pad_ctrl_MASK 0x00000030
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_ebi_data_01_pad_ctrl_SHIFT 4
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_ebi_data_01_pad_ctrl_DEFAULT 0x00000002
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_ebi_data_01_pad_ctrl_PULL_NONE 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_ebi_data_01_pad_ctrl_PULL_DOWN 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_ebi_data_01_pad_ctrl_PULL_UP 2
-
-/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_1 :: ebi_data_00_pad_ctrl [03:02] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_ebi_data_00_pad_ctrl_MASK 0x0000000c
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_ebi_data_00_pad_ctrl_SHIFT 2
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_ebi_data_00_pad_ctrl_DEFAULT 0x00000002
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_ebi_data_00_pad_ctrl_PULL_NONE 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_ebi_data_00_pad_ctrl_PULL_DOWN 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_ebi_data_00_pad_ctrl_PULL_UP 2
-
-/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_1 :: emmc_clk_pad_ctrl [01:00] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_emmc_clk_pad_ctrl_MASK 0x00000003
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_emmc_clk_pad_ctrl_SHIFT 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_emmc_clk_pad_ctrl_DEFAULT 0x00000002
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_emmc_clk_pad_ctrl_PULL_NONE 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_emmc_clk_pad_ctrl_PULL_DOWN 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_emmc_clk_pad_ctrl_PULL_UP 2
-
-/***************************************************************************
- *PIN_MUX_PAD_CTRL_2 - Pad pull-up/pull-down control register 2
- ***************************************************************************/
-/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_2 :: spare_pad_ctrl_2 [31:30] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_spare_pad_ctrl_2_MASK 0xc0000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_spare_pad_ctrl_2_SHIFT 30
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_spare_pad_ctrl_2_DEFAULT 0x00000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_spare_pad_ctrl_2_PULL_NONE 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_spare_pad_ctrl_2_PULL_DOWN 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_spare_pad_ctrl_2_PULL_UP 2
-
-/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_2 :: gpio_005_pad_ctrl [29:28] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_005_pad_ctrl_MASK 0x30000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_005_pad_ctrl_SHIFT 28
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_005_pad_ctrl_DEFAULT 0x00000001
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_005_pad_ctrl_PULL_NONE 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_005_pad_ctrl_PULL_DOWN 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_005_pad_ctrl_PULL_UP 2
-
-/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_2 :: gpio_004_pad_ctrl [27:26] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_004_pad_ctrl_MASK 0x0c000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_004_pad_ctrl_SHIFT 26
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_004_pad_ctrl_DEFAULT 0x00000001
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_004_pad_ctrl_PULL_NONE 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_004_pad_ctrl_PULL_DOWN 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_004_pad_ctrl_PULL_UP 2
-
-/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_2 :: gpio_003_pad_ctrl [25:24] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_003_pad_ctrl_MASK 0x03000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_003_pad_ctrl_SHIFT 24
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_003_pad_ctrl_DEFAULT 0x00000001
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_003_pad_ctrl_PULL_NONE 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_003_pad_ctrl_PULL_DOWN 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_003_pad_ctrl_PULL_UP 2
-
-/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_2 :: gpio_002_pad_ctrl [23:22] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_002_pad_ctrl_MASK 0x00c00000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_002_pad_ctrl_SHIFT 22
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_002_pad_ctrl_DEFAULT 0x00000001
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_002_pad_ctrl_PULL_NONE 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_002_pad_ctrl_PULL_DOWN 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_002_pad_ctrl_PULL_UP 2
-
-/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_2 :: gpio_001_pad_ctrl [21:20] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_001_pad_ctrl_MASK 0x00300000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_001_pad_ctrl_SHIFT 20
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_001_pad_ctrl_DEFAULT 0x00000001
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_001_pad_ctrl_PULL_NONE 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_001_pad_ctrl_PULL_DOWN 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_001_pad_ctrl_PULL_UP 2
-
-/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_2 :: gpio_000_pad_ctrl [19:18] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_000_pad_ctrl_MASK 0x000c0000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_000_pad_ctrl_SHIFT 18
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_000_pad_ctrl_DEFAULT 0x00000001
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_000_pad_ctrl_PULL_NONE 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_000_pad_ctrl_PULL_DOWN 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_000_pad_ctrl_PULL_UP 2
-
-/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_2 :: ebi_nand_dqs_pad_ctrl [17:16] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_ebi_nand_dqs_pad_ctrl_MASK 0x00030000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_ebi_nand_dqs_pad_ctrl_SHIFT 16
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_ebi_nand_dqs_pad_ctrl_DEFAULT 0x00000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_ebi_nand_dqs_pad_ctrl_PULL_NONE 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_ebi_nand_dqs_pad_ctrl_PULL_DOWN 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_ebi_nand_dqs_pad_ctrl_PULL_UP 2
-
-/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_2 :: ebi_nand_wpb_pad_ctrl [15:14] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_ebi_nand_wpb_pad_ctrl_MASK 0x0000c000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_ebi_nand_wpb_pad_ctrl_SHIFT 14
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_ebi_nand_wpb_pad_ctrl_DEFAULT 0x00000001
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_ebi_nand_wpb_pad_ctrl_PULL_NONE 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_ebi_nand_wpb_pad_ctrl_PULL_DOWN 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_ebi_nand_wpb_pad_ctrl_PULL_UP 2
-
-/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_2 :: ebi_nand_rbb_pad_ctrl [13:12] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_ebi_nand_rbb_pad_ctrl_MASK 0x00003000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_ebi_nand_rbb_pad_ctrl_SHIFT 12
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_ebi_nand_rbb_pad_ctrl_DEFAULT 0x00000002
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_ebi_nand_rbb_pad_ctrl_PULL_NONE 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_ebi_nand_rbb_pad_ctrl_PULL_DOWN 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_ebi_nand_rbb_pad_ctrl_PULL_UP 2
-
-/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_2 :: ebi_dsb_pad_ctrl [11:10] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_ebi_dsb_pad_ctrl_MASK 0x00000c00
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_ebi_dsb_pad_ctrl_SHIFT 10
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_ebi_dsb_pad_ctrl_DEFAULT 0x00000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_ebi_dsb_pad_ctrl_PULL_NONE 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_ebi_dsb_pad_ctrl_PULL_DOWN 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_ebi_dsb_pad_ctrl_PULL_UP 2
-
-/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_2 :: ebi_tsb_pad_ctrl [09:08] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_ebi_tsb_pad_ctrl_MASK 0x00000300
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_ebi_tsb_pad_ctrl_SHIFT 8
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_ebi_tsb_pad_ctrl_DEFAULT 0x00000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_ebi_tsb_pad_ctrl_PULL_NONE 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_ebi_tsb_pad_ctrl_PULL_DOWN 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_ebi_tsb_pad_ctrl_PULL_UP 2
-
-/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_2 :: ebi_rdb_pad_ctrl [07:06] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_ebi_rdb_pad_ctrl_MASK 0x000000c0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_ebi_rdb_pad_ctrl_SHIFT 6
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_ebi_rdb_pad_ctrl_DEFAULT 0x00000002
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_ebi_rdb_pad_ctrl_PULL_NONE 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_ebi_rdb_pad_ctrl_PULL_DOWN 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_ebi_rdb_pad_ctrl_PULL_UP 2
-
-/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_2 :: ebi_we1b_pad_ctrl [05:04] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_ebi_we1b_pad_ctrl_MASK 0x00000030
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_ebi_we1b_pad_ctrl_SHIFT 4
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_ebi_we1b_pad_ctrl_DEFAULT 0x00000002
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_ebi_we1b_pad_ctrl_PULL_NONE 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_ebi_we1b_pad_ctrl_PULL_DOWN 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_ebi_we1b_pad_ctrl_PULL_UP 2
-
-/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_2 :: ebi_we0b_pad_ctrl [03:02] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_ebi_we0b_pad_ctrl_MASK 0x0000000c
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_ebi_we0b_pad_ctrl_SHIFT 2
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_ebi_we0b_pad_ctrl_DEFAULT 0x00000002
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_ebi_we0b_pad_ctrl_PULL_NONE 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_ebi_we0b_pad_ctrl_PULL_DOWN 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_ebi_we0b_pad_ctrl_PULL_UP 2
-
-/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_2 :: ebi_rwb_pad_ctrl [01:00] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_ebi_rwb_pad_ctrl_MASK 0x00000003
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_ebi_rwb_pad_ctrl_SHIFT 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_ebi_rwb_pad_ctrl_DEFAULT 0x00000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_ebi_rwb_pad_ctrl_PULL_NONE 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_ebi_rwb_pad_ctrl_PULL_DOWN 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_ebi_rwb_pad_ctrl_PULL_UP 2
-
-/***************************************************************************
- *PIN_MUX_PAD_CTRL_3 - Pad pull-up/pull-down control register 3
- ***************************************************************************/
-/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_3 :: spare_pad_ctrl_3 [31:30] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_spare_pad_ctrl_3_MASK 0xc0000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_spare_pad_ctrl_3_SHIFT 30
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_spare_pad_ctrl_3_DEFAULT 0x00000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_spare_pad_ctrl_3_PULL_NONE 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_spare_pad_ctrl_3_PULL_DOWN 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_spare_pad_ctrl_3_PULL_UP 2
-
-/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_3 :: gpio_020_pad_ctrl [29:28] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_020_pad_ctrl_MASK 0x30000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_020_pad_ctrl_SHIFT 28
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_020_pad_ctrl_DEFAULT 0x00000001
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_020_pad_ctrl_PULL_NONE 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_020_pad_ctrl_PULL_DOWN 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_020_pad_ctrl_PULL_UP 2
-
-/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_3 :: gpio_019_pad_ctrl [27:26] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_019_pad_ctrl_MASK 0x0c000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_019_pad_ctrl_SHIFT 26
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_019_pad_ctrl_DEFAULT 0x00000001
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_019_pad_ctrl_PULL_NONE 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_019_pad_ctrl_PULL_DOWN 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_019_pad_ctrl_PULL_UP 2
-
-/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_3 :: gpio_018_pad_ctrl [25:24] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_018_pad_ctrl_MASK 0x03000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_018_pad_ctrl_SHIFT 24
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_018_pad_ctrl_DEFAULT 0x00000001
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_018_pad_ctrl_PULL_NONE 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_018_pad_ctrl_PULL_DOWN 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_018_pad_ctrl_PULL_UP 2
-
-/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_3 :: gpio_017_pad_ctrl [23:22] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_017_pad_ctrl_MASK 0x00c00000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_017_pad_ctrl_SHIFT 22
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_017_pad_ctrl_DEFAULT 0x00000001
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_017_pad_ctrl_PULL_NONE 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_017_pad_ctrl_PULL_DOWN 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_017_pad_ctrl_PULL_UP 2
-
-/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_3 :: gpio_016_pad_ctrl [21:20] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_016_pad_ctrl_MASK 0x00300000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_016_pad_ctrl_SHIFT 20
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_016_pad_ctrl_DEFAULT 0x00000001
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_016_pad_ctrl_PULL_NONE 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_016_pad_ctrl_PULL_DOWN 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_016_pad_ctrl_PULL_UP 2
-
-/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_3 :: gpio_015_pad_ctrl [19:18] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_015_pad_ctrl_MASK 0x000c0000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_015_pad_ctrl_SHIFT 18
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_015_pad_ctrl_DEFAULT 0x00000001
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_015_pad_ctrl_PULL_NONE 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_015_pad_ctrl_PULL_DOWN 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_015_pad_ctrl_PULL_UP 2
-
-/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_3 :: gpio_014_pad_ctrl [17:16] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_014_pad_ctrl_MASK 0x00030000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_014_pad_ctrl_SHIFT 16
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_014_pad_ctrl_DEFAULT 0x00000001
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_014_pad_ctrl_PULL_NONE 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_014_pad_ctrl_PULL_DOWN 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_014_pad_ctrl_PULL_UP 2
-
-/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_3 :: gpio_013_pad_ctrl [15:14] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_013_pad_ctrl_MASK 0x0000c000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_013_pad_ctrl_SHIFT 14
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_013_pad_ctrl_DEFAULT 0x00000001
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_013_pad_ctrl_PULL_NONE 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_013_pad_ctrl_PULL_DOWN 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_013_pad_ctrl_PULL_UP 2
-
-/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_3 :: gpio_012_pad_ctrl [13:12] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_012_pad_ctrl_MASK 0x00003000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_012_pad_ctrl_SHIFT 12
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_012_pad_ctrl_DEFAULT 0x00000001
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_012_pad_ctrl_PULL_NONE 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_012_pad_ctrl_PULL_DOWN 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_012_pad_ctrl_PULL_UP 2
-
-/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_3 :: reserved0 [11:10] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_reserved0_MASK 0x00000c00
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_reserved0_SHIFT 10
-
-/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_3 :: gpio_010_pad_ctrl [09:08] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_010_pad_ctrl_MASK 0x00000300
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_010_pad_ctrl_SHIFT 8
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_010_pad_ctrl_DEFAULT 0x00000001
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_010_pad_ctrl_PULL_NONE 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_010_pad_ctrl_PULL_DOWN 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_010_pad_ctrl_PULL_UP 2
-
-/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_3 :: gpio_009_pad_ctrl [07:06] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_009_pad_ctrl_MASK 0x000000c0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_009_pad_ctrl_SHIFT 6
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_009_pad_ctrl_DEFAULT 0x00000001
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_009_pad_ctrl_PULL_NONE 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_009_pad_ctrl_PULL_DOWN 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_009_pad_ctrl_PULL_UP 2
-
-/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_3 :: gpio_008_pad_ctrl [05:04] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_008_pad_ctrl_MASK 0x00000030
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_008_pad_ctrl_SHIFT 4
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_008_pad_ctrl_DEFAULT 0x00000001
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_008_pad_ctrl_PULL_NONE 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_008_pad_ctrl_PULL_DOWN 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_008_pad_ctrl_PULL_UP 2
-
-/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_3 :: gpio_007_pad_ctrl [03:02] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_007_pad_ctrl_MASK 0x0000000c
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_007_pad_ctrl_SHIFT 2
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_007_pad_ctrl_DEFAULT 0x00000001
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_007_pad_ctrl_PULL_NONE 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_007_pad_ctrl_PULL_DOWN 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_007_pad_ctrl_PULL_UP 2
-
-/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_3 :: gpio_006_pad_ctrl [01:00] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_006_pad_ctrl_MASK 0x00000003
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_006_pad_ctrl_SHIFT 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_006_pad_ctrl_DEFAULT 0x00000001
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_006_pad_ctrl_PULL_NONE 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_006_pad_ctrl_PULL_DOWN 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_006_pad_ctrl_PULL_UP 2
-
-/***************************************************************************
- *PIN_MUX_PAD_CTRL_4 - Pad pull-up/pull-down control register 4
- ***************************************************************************/
-/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_4 :: spare_pad_ctrl_4 [31:30] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_spare_pad_ctrl_4_MASK 0xc0000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_spare_pad_ctrl_4_SHIFT 30
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_spare_pad_ctrl_4_DEFAULT 0x00000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_spare_pad_ctrl_4_PULL_NONE 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_spare_pad_ctrl_4_PULL_DOWN 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_spare_pad_ctrl_4_PULL_UP 2
-
-/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_4 :: gpio_035_pad_ctrl [29:28] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_035_pad_ctrl_MASK 0x30000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_035_pad_ctrl_SHIFT 28
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_035_pad_ctrl_DEFAULT 0x00000001
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_035_pad_ctrl_PULL_NONE 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_035_pad_ctrl_PULL_DOWN 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_035_pad_ctrl_PULL_UP 2
-
-/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_4 :: gpio_034_pad_ctrl [27:26] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_034_pad_ctrl_MASK 0x0c000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_034_pad_ctrl_SHIFT 26
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_034_pad_ctrl_DEFAULT 0x00000001
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_034_pad_ctrl_PULL_NONE 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_034_pad_ctrl_PULL_DOWN 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_034_pad_ctrl_PULL_UP 2
-
-/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_4 :: gpio_033_pad_ctrl [25:24] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_033_pad_ctrl_MASK 0x03000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_033_pad_ctrl_SHIFT 24
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_033_pad_ctrl_DEFAULT 0x00000001
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_033_pad_ctrl_PULL_NONE 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_033_pad_ctrl_PULL_DOWN 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_033_pad_ctrl_PULL_UP 2
-
-/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_4 :: gpio_032_pad_ctrl [23:22] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_032_pad_ctrl_MASK 0x00c00000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_032_pad_ctrl_SHIFT 22
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_032_pad_ctrl_DEFAULT 0x00000001
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_032_pad_ctrl_PULL_NONE 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_032_pad_ctrl_PULL_DOWN 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_032_pad_ctrl_PULL_UP 2
-
-/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_4 :: gpio_031_pad_ctrl [21:20] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_031_pad_ctrl_MASK 0x00300000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_031_pad_ctrl_SHIFT 20
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_031_pad_ctrl_DEFAULT 0x00000001
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_031_pad_ctrl_PULL_NONE 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_031_pad_ctrl_PULL_DOWN 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_031_pad_ctrl_PULL_UP 2
-
-/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_4 :: gpio_030_pad_ctrl [19:18] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_030_pad_ctrl_MASK 0x000c0000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_030_pad_ctrl_SHIFT 18
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_030_pad_ctrl_DEFAULT 0x00000001
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_030_pad_ctrl_PULL_NONE 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_030_pad_ctrl_PULL_DOWN 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_030_pad_ctrl_PULL_UP 2
-
-/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_4 :: gpio_029_pad_ctrl [17:16] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_029_pad_ctrl_MASK 0x00030000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_029_pad_ctrl_SHIFT 16
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_029_pad_ctrl_DEFAULT 0x00000001
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_029_pad_ctrl_PULL_NONE 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_029_pad_ctrl_PULL_DOWN 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_029_pad_ctrl_PULL_UP 2
-
-/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_4 :: gpio_028_pad_ctrl [15:14] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_028_pad_ctrl_MASK 0x0000c000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_028_pad_ctrl_SHIFT 14
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_028_pad_ctrl_DEFAULT 0x00000001
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_028_pad_ctrl_PULL_NONE 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_028_pad_ctrl_PULL_DOWN 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_028_pad_ctrl_PULL_UP 2
-
-/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_4 :: gpio_027_pad_ctrl [13:12] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_027_pad_ctrl_MASK 0x00003000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_027_pad_ctrl_SHIFT 12
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_027_pad_ctrl_DEFAULT 0x00000001
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_027_pad_ctrl_PULL_NONE 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_027_pad_ctrl_PULL_DOWN 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_027_pad_ctrl_PULL_UP 2
-
-/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_4 :: gpio_026_pad_ctrl [11:10] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_026_pad_ctrl_MASK 0x00000c00
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_026_pad_ctrl_SHIFT 10
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_026_pad_ctrl_DEFAULT 0x00000001
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_026_pad_ctrl_PULL_NONE 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_026_pad_ctrl_PULL_DOWN 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_026_pad_ctrl_PULL_UP 2
-
-/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_4 :: gpio_025_pad_ctrl [09:08] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_025_pad_ctrl_MASK 0x00000300
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_025_pad_ctrl_SHIFT 8
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_025_pad_ctrl_DEFAULT 0x00000001
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_025_pad_ctrl_PULL_NONE 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_025_pad_ctrl_PULL_DOWN 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_025_pad_ctrl_PULL_UP 2
-
-/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_4 :: gpio_024_pad_ctrl [07:06] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_024_pad_ctrl_MASK 0x000000c0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_024_pad_ctrl_SHIFT 6
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_024_pad_ctrl_DEFAULT 0x00000001
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_024_pad_ctrl_PULL_NONE 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_024_pad_ctrl_PULL_DOWN 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_024_pad_ctrl_PULL_UP 2
-
-/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_4 :: gpio_023_pad_ctrl [05:04] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_023_pad_ctrl_MASK 0x00000030
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_023_pad_ctrl_SHIFT 4
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_023_pad_ctrl_DEFAULT 0x00000001
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_023_pad_ctrl_PULL_NONE 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_023_pad_ctrl_PULL_DOWN 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_023_pad_ctrl_PULL_UP 2
-
-/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_4 :: gpio_022_pad_ctrl [03:02] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_022_pad_ctrl_MASK 0x0000000c
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_022_pad_ctrl_SHIFT 2
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_022_pad_ctrl_DEFAULT 0x00000001
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_022_pad_ctrl_PULL_NONE 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_022_pad_ctrl_PULL_DOWN 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_022_pad_ctrl_PULL_UP 2
-
-/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_4 :: gpio_021_pad_ctrl [01:00] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_021_pad_ctrl_MASK 0x00000003
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_021_pad_ctrl_SHIFT 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_021_pad_ctrl_DEFAULT 0x00000001
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_021_pad_ctrl_PULL_NONE 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_021_pad_ctrl_PULL_DOWN 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_021_pad_ctrl_PULL_UP 2
-
-/***************************************************************************
- *PIN_MUX_PAD_CTRL_5 - Pad pull-up/pull-down control register 5
- ***************************************************************************/
-/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_5 :: spare_pad_ctrl_5 [31:30] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_spare_pad_ctrl_5_MASK 0xc0000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_spare_pad_ctrl_5_SHIFT 30
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_spare_pad_ctrl_5_DEFAULT 0x00000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_spare_pad_ctrl_5_PULL_NONE 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_spare_pad_ctrl_5_PULL_DOWN 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_spare_pad_ctrl_5_PULL_UP 2
-
-/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_5 :: gpio_050_pad_ctrl [29:28] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_050_pad_ctrl_MASK 0x30000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_050_pad_ctrl_SHIFT 28
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_050_pad_ctrl_DEFAULT 0x00000001
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_050_pad_ctrl_PULL_NONE 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_050_pad_ctrl_PULL_DOWN 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_050_pad_ctrl_PULL_UP 2
-
-/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_5 :: gpio_049_pad_ctrl [27:26] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_049_pad_ctrl_MASK 0x0c000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_049_pad_ctrl_SHIFT 26
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_049_pad_ctrl_DEFAULT 0x00000001
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_049_pad_ctrl_PULL_NONE 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_049_pad_ctrl_PULL_DOWN 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_049_pad_ctrl_PULL_UP 2
-
-/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_5 :: gpio_048_pad_ctrl [25:24] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_048_pad_ctrl_MASK 0x03000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_048_pad_ctrl_SHIFT 24
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_048_pad_ctrl_DEFAULT 0x00000001
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_048_pad_ctrl_PULL_NONE 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_048_pad_ctrl_PULL_DOWN 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_048_pad_ctrl_PULL_UP 2
-
-/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_5 :: gpio_047_pad_ctrl [23:22] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_047_pad_ctrl_MASK 0x00c00000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_047_pad_ctrl_SHIFT 22
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_047_pad_ctrl_DEFAULT 0x00000001
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_047_pad_ctrl_PULL_NONE 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_047_pad_ctrl_PULL_DOWN 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_047_pad_ctrl_PULL_UP 2
-
-/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_5 :: gpio_046_pad_ctrl [21:20] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_046_pad_ctrl_MASK 0x00300000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_046_pad_ctrl_SHIFT 20
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_046_pad_ctrl_DEFAULT 0x00000001
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_046_pad_ctrl_PULL_NONE 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_046_pad_ctrl_PULL_DOWN 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_046_pad_ctrl_PULL_UP 2
-
-/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_5 :: gpio_045_pad_ctrl [19:18] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_045_pad_ctrl_MASK 0x000c0000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_045_pad_ctrl_SHIFT 18
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_045_pad_ctrl_DEFAULT 0x00000001
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_045_pad_ctrl_PULL_NONE 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_045_pad_ctrl_PULL_DOWN 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_045_pad_ctrl_PULL_UP 2
-
-/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_5 :: gpio_044_pad_ctrl [17:16] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_044_pad_ctrl_MASK 0x00030000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_044_pad_ctrl_SHIFT 16
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_044_pad_ctrl_DEFAULT 0x00000001
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_044_pad_ctrl_PULL_NONE 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_044_pad_ctrl_PULL_DOWN 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_044_pad_ctrl_PULL_UP 2
-
-/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_5 :: gpio_043_pad_ctrl [15:14] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_043_pad_ctrl_MASK 0x0000c000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_043_pad_ctrl_SHIFT 14
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_043_pad_ctrl_DEFAULT 0x00000001
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_043_pad_ctrl_PULL_NONE 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_043_pad_ctrl_PULL_DOWN 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_043_pad_ctrl_PULL_UP 2
-
-/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_5 :: gpio_042_pad_ctrl [13:12] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_042_pad_ctrl_MASK 0x00003000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_042_pad_ctrl_SHIFT 12
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_042_pad_ctrl_DEFAULT 0x00000001
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_042_pad_ctrl_PULL_NONE 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_042_pad_ctrl_PULL_DOWN 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_042_pad_ctrl_PULL_UP 2
-
-/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_5 :: gpio_041_pad_ctrl [11:10] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_041_pad_ctrl_MASK 0x00000c00
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_041_pad_ctrl_SHIFT 10
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_041_pad_ctrl_DEFAULT 0x00000001
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_041_pad_ctrl_PULL_NONE 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_041_pad_ctrl_PULL_DOWN 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_041_pad_ctrl_PULL_UP 2
-
-/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_5 :: gpio_040_pad_ctrl [09:08] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_040_pad_ctrl_MASK 0x00000300
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_040_pad_ctrl_SHIFT 8
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_040_pad_ctrl_DEFAULT 0x00000001
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_040_pad_ctrl_PULL_NONE 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_040_pad_ctrl_PULL_DOWN 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_040_pad_ctrl_PULL_UP 2
-
-/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_5 :: gpio_039_pad_ctrl [07:06] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_039_pad_ctrl_MASK 0x000000c0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_039_pad_ctrl_SHIFT 6
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_039_pad_ctrl_DEFAULT 0x00000001
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_039_pad_ctrl_PULL_NONE 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_039_pad_ctrl_PULL_DOWN 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_039_pad_ctrl_PULL_UP 2
-
-/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_5 :: gpio_038_pad_ctrl [05:04] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_038_pad_ctrl_MASK 0x00000030
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_038_pad_ctrl_SHIFT 4
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_038_pad_ctrl_DEFAULT 0x00000001
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_038_pad_ctrl_PULL_NONE 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_038_pad_ctrl_PULL_DOWN 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_038_pad_ctrl_PULL_UP 2
-
-/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_5 :: gpio_037_pad_ctrl [03:02] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_037_pad_ctrl_MASK 0x0000000c
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_037_pad_ctrl_SHIFT 2
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_037_pad_ctrl_DEFAULT 0x00000001
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_037_pad_ctrl_PULL_NONE 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_037_pad_ctrl_PULL_DOWN 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_037_pad_ctrl_PULL_UP 2
-
-/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_5 :: gpio_036_pad_ctrl [01:00] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_036_pad_ctrl_MASK 0x00000003
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_036_pad_ctrl_SHIFT 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_036_pad_ctrl_DEFAULT 0x00000001
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_036_pad_ctrl_PULL_NONE 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_036_pad_ctrl_PULL_DOWN 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_036_pad_ctrl_PULL_UP 2
-
-/***************************************************************************
- *PIN_MUX_PAD_CTRL_6 - Pad pull-up/pull-down control register 6
- ***************************************************************************/
-/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_6 :: spare_pad_ctrl_6 [31:30] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_spare_pad_ctrl_6_MASK 0xc0000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_spare_pad_ctrl_6_SHIFT 30
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_spare_pad_ctrl_6_DEFAULT 0x00000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_spare_pad_ctrl_6_PULL_NONE 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_spare_pad_ctrl_6_PULL_DOWN 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_spare_pad_ctrl_6_PULL_UP 2
-
-/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_6 :: gpio_065_pad_ctrl [29:28] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_065_pad_ctrl_MASK 0x30000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_065_pad_ctrl_SHIFT 28
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_065_pad_ctrl_DEFAULT 0x00000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_065_pad_ctrl_PULL_NONE 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_065_pad_ctrl_PULL_DOWN 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_065_pad_ctrl_PULL_UP 2
-
-/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_6 :: gpio_064_pad_ctrl [27:26] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_064_pad_ctrl_MASK 0x0c000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_064_pad_ctrl_SHIFT 26
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_064_pad_ctrl_DEFAULT 0x00000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_064_pad_ctrl_PULL_NONE 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_064_pad_ctrl_PULL_DOWN 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_064_pad_ctrl_PULL_UP 2
-
-/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_6 :: gpio_063_pad_ctrl [25:24] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_063_pad_ctrl_MASK 0x03000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_063_pad_ctrl_SHIFT 24
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_063_pad_ctrl_DEFAULT 0x00000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_063_pad_ctrl_PULL_NONE 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_063_pad_ctrl_PULL_DOWN 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_063_pad_ctrl_PULL_UP 2
-
-/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_6 :: gpio_062_pad_ctrl [23:22] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_062_pad_ctrl_MASK 0x00c00000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_062_pad_ctrl_SHIFT 22
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_062_pad_ctrl_DEFAULT 0x00000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_062_pad_ctrl_PULL_NONE 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_062_pad_ctrl_PULL_DOWN 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_062_pad_ctrl_PULL_UP 2
-
-/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_6 :: gpio_061_pad_ctrl [21:20] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_061_pad_ctrl_MASK 0x00300000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_061_pad_ctrl_SHIFT 20
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_061_pad_ctrl_DEFAULT 0x00000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_061_pad_ctrl_PULL_NONE 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_061_pad_ctrl_PULL_DOWN 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_061_pad_ctrl_PULL_UP 2
-
-/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_6 :: gpio_060_pad_ctrl [19:18] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_060_pad_ctrl_MASK 0x000c0000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_060_pad_ctrl_SHIFT 18
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_060_pad_ctrl_DEFAULT 0x00000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_060_pad_ctrl_PULL_NONE 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_060_pad_ctrl_PULL_DOWN 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_060_pad_ctrl_PULL_UP 2
-
-/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_6 :: gpio_059_pad_ctrl [17:16] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_059_pad_ctrl_MASK 0x00030000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_059_pad_ctrl_SHIFT 16
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_059_pad_ctrl_DEFAULT 0x00000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_059_pad_ctrl_PULL_NONE 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_059_pad_ctrl_PULL_DOWN 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_059_pad_ctrl_PULL_UP 2
-
-/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_6 :: gpio_058_pad_ctrl [15:14] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_058_pad_ctrl_MASK 0x0000c000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_058_pad_ctrl_SHIFT 14
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_058_pad_ctrl_DEFAULT 0x00000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_058_pad_ctrl_PULL_NONE 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_058_pad_ctrl_PULL_DOWN 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_058_pad_ctrl_PULL_UP 2
-
-/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_6 :: gpio_057_pad_ctrl [13:12] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_057_pad_ctrl_MASK 0x00003000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_057_pad_ctrl_SHIFT 12
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_057_pad_ctrl_DEFAULT 0x00000001
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_057_pad_ctrl_PULL_NONE 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_057_pad_ctrl_PULL_DOWN 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_057_pad_ctrl_PULL_UP 2
-
-/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_6 :: gpio_056_pad_ctrl [11:10] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_056_pad_ctrl_MASK 0x00000c00
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_056_pad_ctrl_SHIFT 10
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_056_pad_ctrl_DEFAULT 0x00000001
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_056_pad_ctrl_PULL_NONE 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_056_pad_ctrl_PULL_DOWN 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_056_pad_ctrl_PULL_UP 2
-
-/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_6 :: gpio_055_pad_ctrl [09:08] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_055_pad_ctrl_MASK 0x00000300
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_055_pad_ctrl_SHIFT 8
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_055_pad_ctrl_DEFAULT 0x00000001
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_055_pad_ctrl_PULL_NONE 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_055_pad_ctrl_PULL_DOWN 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_055_pad_ctrl_PULL_UP 2
-
-/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_6 :: gpio_054_pad_ctrl [07:06] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_054_pad_ctrl_MASK 0x000000c0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_054_pad_ctrl_SHIFT 6
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_054_pad_ctrl_DEFAULT 0x00000001
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_054_pad_ctrl_PULL_NONE 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_054_pad_ctrl_PULL_DOWN 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_054_pad_ctrl_PULL_UP 2
-
-/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_6 :: gpio_053_pad_ctrl [05:04] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_053_pad_ctrl_MASK 0x00000030
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_053_pad_ctrl_SHIFT 4
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_053_pad_ctrl_DEFAULT 0x00000001
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_053_pad_ctrl_PULL_NONE 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_053_pad_ctrl_PULL_DOWN 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_053_pad_ctrl_PULL_UP 2
-
-/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_6 :: gpio_052_pad_ctrl [03:02] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_052_pad_ctrl_MASK 0x0000000c
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_052_pad_ctrl_SHIFT 2
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_052_pad_ctrl_DEFAULT 0x00000001
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_052_pad_ctrl_PULL_NONE 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_052_pad_ctrl_PULL_DOWN 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_052_pad_ctrl_PULL_UP 2
-
-/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_6 :: gpio_051_pad_ctrl [01:00] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_051_pad_ctrl_MASK 0x00000003
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_051_pad_ctrl_SHIFT 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_051_pad_ctrl_DEFAULT 0x00000001
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_051_pad_ctrl_PULL_NONE 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_051_pad_ctrl_PULL_DOWN 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_051_pad_ctrl_PULL_UP 2
-
-/***************************************************************************
- *PIN_MUX_PAD_CTRL_7 - Pad pull-up/pull-down control register 7
- ***************************************************************************/
-/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_7 :: spare_pad_ctrl_7 [31:30] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_spare_pad_ctrl_7_MASK 0xc0000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_spare_pad_ctrl_7_SHIFT 30
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_spare_pad_ctrl_7_DEFAULT 0x00000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_spare_pad_ctrl_7_PULL_NONE 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_spare_pad_ctrl_7_PULL_DOWN 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_spare_pad_ctrl_7_PULL_UP 2
-
-/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_7 :: gpio_080_pad_ctrl [29:28] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_080_pad_ctrl_MASK 0x30000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_080_pad_ctrl_SHIFT 28
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_080_pad_ctrl_DEFAULT 0x00000001
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_080_pad_ctrl_PULL_NONE 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_080_pad_ctrl_PULL_DOWN 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_080_pad_ctrl_PULL_UP 2
-
-/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_7 :: gpio_079_pad_ctrl [27:26] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_079_pad_ctrl_MASK 0x0c000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_079_pad_ctrl_SHIFT 26
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_079_pad_ctrl_DEFAULT 0x00000001
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_079_pad_ctrl_PULL_NONE 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_079_pad_ctrl_PULL_DOWN 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_079_pad_ctrl_PULL_UP 2
-
-/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_7 :: gpio_078_pad_ctrl [25:24] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_078_pad_ctrl_MASK 0x03000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_078_pad_ctrl_SHIFT 24
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_078_pad_ctrl_DEFAULT 0x00000001
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_078_pad_ctrl_PULL_NONE 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_078_pad_ctrl_PULL_DOWN 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_078_pad_ctrl_PULL_UP 2
-
-/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_7 :: gpio_077_pad_ctrl [23:22] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_077_pad_ctrl_MASK 0x00c00000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_077_pad_ctrl_SHIFT 22
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_077_pad_ctrl_DEFAULT 0x00000001
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_077_pad_ctrl_PULL_NONE 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_077_pad_ctrl_PULL_DOWN 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_077_pad_ctrl_PULL_UP 2
-
-/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_7 :: gpio_076_pad_ctrl [21:20] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_076_pad_ctrl_MASK 0x00300000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_076_pad_ctrl_SHIFT 20
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_076_pad_ctrl_DEFAULT 0x00000001
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_076_pad_ctrl_PULL_NONE 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_076_pad_ctrl_PULL_DOWN 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_076_pad_ctrl_PULL_UP 2
-
-/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_7 :: gpio_075_pad_ctrl [19:18] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_075_pad_ctrl_MASK 0x000c0000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_075_pad_ctrl_SHIFT 18
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_075_pad_ctrl_DEFAULT 0x00000001
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_075_pad_ctrl_PULL_NONE 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_075_pad_ctrl_PULL_DOWN 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_075_pad_ctrl_PULL_UP 2
-
-/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_7 :: gpio_074_pad_ctrl [17:16] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_074_pad_ctrl_MASK 0x00030000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_074_pad_ctrl_SHIFT 16
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_074_pad_ctrl_DEFAULT 0x00000001
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_074_pad_ctrl_PULL_NONE 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_074_pad_ctrl_PULL_DOWN 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_074_pad_ctrl_PULL_UP 2
-
-/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_7 :: gpio_073_pad_ctrl [15:14] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_073_pad_ctrl_MASK 0x0000c000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_073_pad_ctrl_SHIFT 14
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_073_pad_ctrl_DEFAULT 0x00000001
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_073_pad_ctrl_PULL_NONE 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_073_pad_ctrl_PULL_DOWN 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_073_pad_ctrl_PULL_UP 2
-
-/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_7 :: gpio_072_pad_ctrl [13:12] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_072_pad_ctrl_MASK 0x00003000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_072_pad_ctrl_SHIFT 12
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_072_pad_ctrl_DEFAULT 0x00000001
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_072_pad_ctrl_PULL_NONE 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_072_pad_ctrl_PULL_DOWN 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_072_pad_ctrl_PULL_UP 2
-
-/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_7 :: gpio_071_pad_ctrl [11:10] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_071_pad_ctrl_MASK 0x00000c00
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_071_pad_ctrl_SHIFT 10
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_071_pad_ctrl_DEFAULT 0x00000001
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_071_pad_ctrl_PULL_NONE 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_071_pad_ctrl_PULL_DOWN 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_071_pad_ctrl_PULL_UP 2
-
-/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_7 :: gpio_070_pad_ctrl [09:08] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_070_pad_ctrl_MASK 0x00000300
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_070_pad_ctrl_SHIFT 8
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_070_pad_ctrl_DEFAULT 0x00000001
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_070_pad_ctrl_PULL_NONE 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_070_pad_ctrl_PULL_DOWN 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_070_pad_ctrl_PULL_UP 2
-
-/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_7 :: gpio_069_pad_ctrl [07:06] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_069_pad_ctrl_MASK 0x000000c0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_069_pad_ctrl_SHIFT 6
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_069_pad_ctrl_DEFAULT 0x00000001
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_069_pad_ctrl_PULL_NONE 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_069_pad_ctrl_PULL_DOWN 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_069_pad_ctrl_PULL_UP 2
-
-/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_7 :: gpio_068_pad_ctrl [05:04] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_068_pad_ctrl_MASK 0x00000030
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_068_pad_ctrl_SHIFT 4
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_068_pad_ctrl_DEFAULT 0x00000001
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_068_pad_ctrl_PULL_NONE 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_068_pad_ctrl_PULL_DOWN 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_068_pad_ctrl_PULL_UP 2
-
-/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_7 :: gpio_067_pad_ctrl [03:02] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_067_pad_ctrl_MASK 0x0000000c
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_067_pad_ctrl_SHIFT 2
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_067_pad_ctrl_DEFAULT 0x00000001
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_067_pad_ctrl_PULL_NONE 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_067_pad_ctrl_PULL_DOWN 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_067_pad_ctrl_PULL_UP 2
-
-/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_7 :: gpio_066_pad_ctrl [01:00] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_066_pad_ctrl_MASK 0x00000003
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_066_pad_ctrl_SHIFT 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_066_pad_ctrl_DEFAULT 0x00000001
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_066_pad_ctrl_PULL_NONE 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_066_pad_ctrl_PULL_DOWN 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_066_pad_ctrl_PULL_UP 2
-
-/***************************************************************************
- *PIN_MUX_PAD_CTRL_8 - Pad pull-up/pull-down control register 8
- ***************************************************************************/
-/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_8 :: spare_pad_ctrl_8 [31:30] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_spare_pad_ctrl_8_MASK 0xc0000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_spare_pad_ctrl_8_SHIFT 30
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_spare_pad_ctrl_8_DEFAULT 0x00000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_spare_pad_ctrl_8_PULL_NONE 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_spare_pad_ctrl_8_PULL_DOWN 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_spare_pad_ctrl_8_PULL_UP 2
-
-/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_8 :: gpio_095_pad_ctrl [29:28] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_095_pad_ctrl_MASK 0x30000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_095_pad_ctrl_SHIFT 28
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_095_pad_ctrl_DEFAULT 0x00000001
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_095_pad_ctrl_PULL_NONE 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_095_pad_ctrl_PULL_DOWN 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_095_pad_ctrl_PULL_UP 2
-
-/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_8 :: gpio_094_pad_ctrl [27:26] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_094_pad_ctrl_MASK 0x0c000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_094_pad_ctrl_SHIFT 26
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_094_pad_ctrl_DEFAULT 0x00000001
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_094_pad_ctrl_PULL_NONE 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_094_pad_ctrl_PULL_DOWN 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_094_pad_ctrl_PULL_UP 2
-
-/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_8 :: gpio_093_pad_ctrl [25:24] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_093_pad_ctrl_MASK 0x03000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_093_pad_ctrl_SHIFT 24
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_093_pad_ctrl_DEFAULT 0x00000001
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_093_pad_ctrl_PULL_NONE 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_093_pad_ctrl_PULL_DOWN 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_093_pad_ctrl_PULL_UP 2
-
-/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_8 :: gpio_092_pad_ctrl [23:22] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_092_pad_ctrl_MASK 0x00c00000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_092_pad_ctrl_SHIFT 22
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_092_pad_ctrl_DEFAULT 0x00000001
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_092_pad_ctrl_PULL_NONE 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_092_pad_ctrl_PULL_DOWN 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_092_pad_ctrl_PULL_UP 2
-
-/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_8 :: gpio_091_pad_ctrl [21:20] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_091_pad_ctrl_MASK 0x00300000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_091_pad_ctrl_SHIFT 20
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_091_pad_ctrl_DEFAULT 0x00000001
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_091_pad_ctrl_PULL_NONE 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_091_pad_ctrl_PULL_DOWN 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_091_pad_ctrl_PULL_UP 2
-
-/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_8 :: gpio_090_pad_ctrl [19:18] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_090_pad_ctrl_MASK 0x000c0000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_090_pad_ctrl_SHIFT 18
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_090_pad_ctrl_DEFAULT 0x00000001
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_090_pad_ctrl_PULL_NONE 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_090_pad_ctrl_PULL_DOWN 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_090_pad_ctrl_PULL_UP 2
-
-/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_8 :: gpio_089_pad_ctrl [17:16] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_089_pad_ctrl_MASK 0x00030000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_089_pad_ctrl_SHIFT 16
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_089_pad_ctrl_DEFAULT 0x00000001
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_089_pad_ctrl_PULL_NONE 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_089_pad_ctrl_PULL_DOWN 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_089_pad_ctrl_PULL_UP 2
-
-/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_8 :: gpio_088_pad_ctrl [15:14] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_088_pad_ctrl_MASK 0x0000c000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_088_pad_ctrl_SHIFT 14
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_088_pad_ctrl_DEFAULT 0x00000001
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_088_pad_ctrl_PULL_NONE 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_088_pad_ctrl_PULL_DOWN 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_088_pad_ctrl_PULL_UP 2
-
-/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_8 :: gpio_087_pad_ctrl [13:12] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_087_pad_ctrl_MASK 0x00003000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_087_pad_ctrl_SHIFT 12
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_087_pad_ctrl_DEFAULT 0x00000001
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_087_pad_ctrl_PULL_NONE 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_087_pad_ctrl_PULL_DOWN 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_087_pad_ctrl_PULL_UP 2
-
-/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_8 :: gpio_086_pad_ctrl [11:10] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_086_pad_ctrl_MASK 0x00000c00
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_086_pad_ctrl_SHIFT 10
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_086_pad_ctrl_DEFAULT 0x00000001
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_086_pad_ctrl_PULL_NONE 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_086_pad_ctrl_PULL_DOWN 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_086_pad_ctrl_PULL_UP 2
-
-/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_8 :: gpio_085_pad_ctrl [09:08] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_085_pad_ctrl_MASK 0x00000300
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_085_pad_ctrl_SHIFT 8
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_085_pad_ctrl_DEFAULT 0x00000001
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_085_pad_ctrl_PULL_NONE 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_085_pad_ctrl_PULL_DOWN 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_085_pad_ctrl_PULL_UP 2
-
-/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_8 :: gpio_084_pad_ctrl [07:06] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_084_pad_ctrl_MASK 0x000000c0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_084_pad_ctrl_SHIFT 6
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_084_pad_ctrl_DEFAULT 0x00000001
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_084_pad_ctrl_PULL_NONE 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_084_pad_ctrl_PULL_DOWN 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_084_pad_ctrl_PULL_UP 2
-
-/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_8 :: gpio_083_pad_ctrl [05:04] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_083_pad_ctrl_MASK 0x00000030
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_083_pad_ctrl_SHIFT 4
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_083_pad_ctrl_DEFAULT 0x00000001
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_083_pad_ctrl_PULL_NONE 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_083_pad_ctrl_PULL_DOWN 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_083_pad_ctrl_PULL_UP 2
-
-/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_8 :: gpio_082_pad_ctrl [03:02] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_082_pad_ctrl_MASK 0x0000000c
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_082_pad_ctrl_SHIFT 2
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_082_pad_ctrl_DEFAULT 0x00000001
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_082_pad_ctrl_PULL_NONE 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_082_pad_ctrl_PULL_DOWN 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_082_pad_ctrl_PULL_UP 2
-
-/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_8 :: gpio_081_pad_ctrl [01:00] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_081_pad_ctrl_MASK 0x00000003
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_081_pad_ctrl_SHIFT 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_081_pad_ctrl_DEFAULT 0x00000001
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_081_pad_ctrl_PULL_NONE 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_081_pad_ctrl_PULL_DOWN 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_081_pad_ctrl_PULL_UP 2
-
-/***************************************************************************
- *PIN_MUX_PAD_CTRL_9 - Pad pull-up/pull-down control register 9
- ***************************************************************************/
-/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_9 :: spare_pad_ctrl_9 [31:30] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_spare_pad_ctrl_9_MASK 0xc0000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_spare_pad_ctrl_9_SHIFT 30
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_spare_pad_ctrl_9_DEFAULT 0x00000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_spare_pad_ctrl_9_PULL_NONE 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_spare_pad_ctrl_9_PULL_DOWN 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_spare_pad_ctrl_9_PULL_UP 2
-
-/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_9 :: reserved0 [29:24] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_reserved0_MASK 0x3f000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_reserved0_SHIFT 24
-
-/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_9 :: gpio_107_pad_ctrl [23:22] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_107_pad_ctrl_MASK 0x00c00000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_107_pad_ctrl_SHIFT 22
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_107_pad_ctrl_DEFAULT 0x00000001
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_107_pad_ctrl_PULL_NONE 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_107_pad_ctrl_PULL_DOWN 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_107_pad_ctrl_PULL_UP 2
-
-/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_9 :: gpio_106_pad_ctrl [21:20] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_106_pad_ctrl_MASK 0x00300000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_106_pad_ctrl_SHIFT 20
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_106_pad_ctrl_DEFAULT 0x00000001
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_106_pad_ctrl_PULL_NONE 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_106_pad_ctrl_PULL_DOWN 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_106_pad_ctrl_PULL_UP 2
-
-/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_9 :: gpio_105_pad_ctrl [19:18] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_105_pad_ctrl_MASK 0x000c0000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_105_pad_ctrl_SHIFT 18
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_105_pad_ctrl_DEFAULT 0x00000001
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_105_pad_ctrl_PULL_NONE 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_105_pad_ctrl_PULL_DOWN 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_105_pad_ctrl_PULL_UP 2
-
-/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_9 :: gpio_104_pad_ctrl [17:16] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_104_pad_ctrl_MASK 0x00030000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_104_pad_ctrl_SHIFT 16
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_104_pad_ctrl_DEFAULT 0x00000001
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_104_pad_ctrl_PULL_NONE 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_104_pad_ctrl_PULL_DOWN 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_104_pad_ctrl_PULL_UP 2
-
-/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_9 :: gpio_103_pad_ctrl [15:14] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_103_pad_ctrl_MASK 0x0000c000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_103_pad_ctrl_SHIFT 14
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_103_pad_ctrl_DEFAULT 0x00000001
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_103_pad_ctrl_PULL_NONE 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_103_pad_ctrl_PULL_DOWN 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_103_pad_ctrl_PULL_UP 2
-
-/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_9 :: gpio_102_pad_ctrl [13:12] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_102_pad_ctrl_MASK 0x00003000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_102_pad_ctrl_SHIFT 12
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_102_pad_ctrl_DEFAULT 0x00000001
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_102_pad_ctrl_PULL_NONE 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_102_pad_ctrl_PULL_DOWN 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_102_pad_ctrl_PULL_UP 2
-
-/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_9 :: gpio_101_pad_ctrl [11:10] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_101_pad_ctrl_MASK 0x00000c00
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_101_pad_ctrl_SHIFT 10
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_101_pad_ctrl_DEFAULT 0x00000001
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_101_pad_ctrl_PULL_NONE 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_101_pad_ctrl_PULL_DOWN 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_101_pad_ctrl_PULL_UP 2
-
-/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_9 :: gpio_100_pad_ctrl [09:08] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_100_pad_ctrl_MASK 0x00000300
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_100_pad_ctrl_SHIFT 8
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_100_pad_ctrl_DEFAULT 0x00000001
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_100_pad_ctrl_PULL_NONE 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_100_pad_ctrl_PULL_DOWN 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_100_pad_ctrl_PULL_UP 2
-
-/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_9 :: gpio_099_pad_ctrl [07:06] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_099_pad_ctrl_MASK 0x000000c0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_099_pad_ctrl_SHIFT 6
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_099_pad_ctrl_DEFAULT 0x00000001
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_099_pad_ctrl_PULL_NONE 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_099_pad_ctrl_PULL_DOWN 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_099_pad_ctrl_PULL_UP 2
-
-/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_9 :: gpio_098_pad_ctrl [05:04] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_098_pad_ctrl_MASK 0x00000030
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_098_pad_ctrl_SHIFT 4
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_098_pad_ctrl_DEFAULT 0x00000001
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_098_pad_ctrl_PULL_NONE 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_098_pad_ctrl_PULL_DOWN 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_098_pad_ctrl_PULL_UP 2
-
-/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_9 :: gpio_097_pad_ctrl [03:02] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_097_pad_ctrl_MASK 0x0000000c
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_097_pad_ctrl_SHIFT 2
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_097_pad_ctrl_DEFAULT 0x00000001
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_097_pad_ctrl_PULL_NONE 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_097_pad_ctrl_PULL_DOWN 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_097_pad_ctrl_PULL_UP 2
-
-/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_9 :: gpio_096_pad_ctrl [01:00] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_096_pad_ctrl_MASK 0x00000003
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_096_pad_ctrl_SHIFT 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_096_pad_ctrl_DEFAULT 0x00000001
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_096_pad_ctrl_PULL_NONE 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_096_pad_ctrl_PULL_DOWN 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_096_pad_ctrl_PULL_UP 2
-
-/***************************************************************************
- *PIN_MUX_PAD_CTRL_10 - Pad pull-up/pull-down control register 10
- ***************************************************************************/
-/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_10 :: spare_pad_ctrl_10 [31:30] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_spare_pad_ctrl_10_MASK 0xc0000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_spare_pad_ctrl_10_SHIFT 30
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_spare_pad_ctrl_10_DEFAULT 0x00000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_spare_pad_ctrl_10_PULL_NONE 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_spare_pad_ctrl_10_PULL_DOWN 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_spare_pad_ctrl_10_PULL_UP 2
-
-/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_10 :: reserved0 [29:02] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_reserved0_MASK 0x3ffffffc
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_reserved0_SHIFT 2
-
-/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_10 :: gpio_111_pad_ctrl [01:00] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_111_pad_ctrl_MASK 0x00000003
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_111_pad_ctrl_SHIFT 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_111_pad_ctrl_DEFAULT 0x00000001
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_111_pad_ctrl_PULL_NONE 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_111_pad_ctrl_PULL_DOWN 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_111_pad_ctrl_PULL_UP 2
-
-/***************************************************************************
- *PIN_MUX_PAD_CTRL_11 - Pad pull-up/pull-down control register 11
- ***************************************************************************/
-/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_11 :: reserved0 [31:22] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11_reserved0_MASK 0xffc00000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11_reserved0_SHIFT 22
-
-/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_11 :: spare_pad_ctrl_11 [21:20] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11_spare_pad_ctrl_11_MASK 0x00300000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11_spare_pad_ctrl_11_SHIFT 20
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11_spare_pad_ctrl_11_DEFAULT 0x00000000
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11_spare_pad_ctrl_11_PULL_NONE 0
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11_spare_pad_ctrl_11_PULL_DOWN 1
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11_spare_pad_ctrl_11_PULL_UP 2
-
-/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_11 :: reserved1 [19:00] */
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11_reserved1_MASK 0x000fffff
-#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11_reserved1_SHIFT 0
-
-/***************************************************************************
- *BYP_CLK_UNSELECT_0 - Bypass clock unselect register 0
- ***************************************************************************/
-/* SUN_TOP_CTRL :: BYP_CLK_UNSELECT_0 :: reserved0 [31:16] */
-#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_reserved0_MASK 0xffff0000
-#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_reserved0_SHIFT 16
-
-/* SUN_TOP_CTRL :: BYP_CLK_UNSELECT_0 :: unsel_byp_clk_on_byp_clk_15 [15:15] */
-#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_byp_clk_15_MASK 0x00008000
-#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_byp_clk_15_SHIFT 15
-#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_byp_clk_15_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: BYP_CLK_UNSELECT_0 :: unsel_byp_clk_on_byp_clk_14 [14:14] */
-#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_byp_clk_14_MASK 0x00004000
-#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_byp_clk_14_SHIFT 14
-#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_byp_clk_14_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: BYP_CLK_UNSELECT_0 :: unsel_byp_clk_on_byp_clk_13 [13:13] */
-#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_byp_clk_13_MASK 0x00002000
-#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_byp_clk_13_SHIFT 13
-#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_byp_clk_13_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: BYP_CLK_UNSELECT_0 :: unsel_byp_clk_on_byp_clk_12 [12:12] */
-#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_byp_clk_12_MASK 0x00001000
-#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_byp_clk_12_SHIFT 12
-#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_byp_clk_12_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: BYP_CLK_UNSELECT_0 :: unsel_byp_clk_on_byp_clk_11 [11:11] */
-#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_byp_clk_11_MASK 0x00000800
-#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_byp_clk_11_SHIFT 11
-#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_byp_clk_11_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: BYP_CLK_UNSELECT_0 :: unsel_byp_clk_on_byp_clk_10 [10:10] */
-#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_byp_clk_10_MASK 0x00000400
-#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_byp_clk_10_SHIFT 10
-#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_byp_clk_10_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: BYP_CLK_UNSELECT_0 :: unsel_byp_clk_on_byp_clk_9 [09:09] */
-#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_byp_clk_9_MASK 0x00000200
-#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_byp_clk_9_SHIFT 9
-#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_byp_clk_9_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: BYP_CLK_UNSELECT_0 :: unsel_byp_clk_on_byp_clk_8 [08:08] */
-#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_byp_clk_8_MASK 0x00000100
-#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_byp_clk_8_SHIFT 8
-#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_byp_clk_8_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: BYP_CLK_UNSELECT_0 :: unsel_byp_clk_on_byp_clk_7 [07:07] */
-#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_byp_clk_7_MASK 0x00000080
-#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_byp_clk_7_SHIFT 7
-#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_byp_clk_7_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: BYP_CLK_UNSELECT_0 :: unsel_byp_clk_on_byp_clk_6 [06:06] */
-#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_byp_clk_6_MASK 0x00000040
-#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_byp_clk_6_SHIFT 6
-#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_byp_clk_6_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: BYP_CLK_UNSELECT_0 :: unsel_byp_clk_on_byp_clk_5 [05:05] */
-#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_byp_clk_5_MASK 0x00000020
-#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_byp_clk_5_SHIFT 5
-#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_byp_clk_5_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: BYP_CLK_UNSELECT_0 :: unsel_byp_clk_on_byp_clk_4 [04:04] */
-#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_byp_clk_4_MASK 0x00000010
-#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_byp_clk_4_SHIFT 4
-#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_byp_clk_4_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: BYP_CLK_UNSELECT_0 :: unsel_byp_clk_on_byp_clk_3 [03:03] */
-#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_byp_clk_3_MASK 0x00000008
-#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_byp_clk_3_SHIFT 3
-#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_byp_clk_3_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: BYP_CLK_UNSELECT_0 :: unsel_byp_clk_on_byp_clk_2 [02:02] */
-#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_byp_clk_2_MASK 0x00000004
-#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_byp_clk_2_SHIFT 2
-#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_byp_clk_2_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: BYP_CLK_UNSELECT_0 :: unsel_byp_clk_on_byp_clk_1 [01:01] */
-#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_byp_clk_1_MASK 0x00000002
-#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_byp_clk_1_SHIFT 1
-#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_byp_clk_1_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: BYP_CLK_UNSELECT_0 :: unsel_byp_clk_on_byp_clk_0 [00:00] */
-#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_byp_clk_0_MASK 0x00000001
-#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_byp_clk_0_SHIFT 0
-#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_byp_clk_0_DEFAULT 0x00000000
-
-/***************************************************************************
- *RESET_CTRL - Reset control
- ***************************************************************************/
-/* SUN_TOP_CTRL :: RESET_CTRL :: reserved0 [31:01] */
-#define BCHP_SUN_TOP_CTRL_RESET_CTRL_reserved0_MASK 0xfffffffe
-#define BCHP_SUN_TOP_CTRL_RESET_CTRL_reserved0_SHIFT 1
-
-/* SUN_TOP_CTRL :: RESET_CTRL :: clear_reset_history [00:00] */
-#define BCHP_SUN_TOP_CTRL_RESET_CTRL_clear_reset_history_MASK 0x00000001
-#define BCHP_SUN_TOP_CTRL_RESET_CTRL_clear_reset_history_SHIFT 0
-#define BCHP_SUN_TOP_CTRL_RESET_CTRL_clear_reset_history_DEFAULT 0x00000000
-
-/***************************************************************************
- *RESET_SOURCE_ENABLE - Reset source enable
- ***************************************************************************/
-/* SUN_TOP_CTRL :: RESET_SOURCE_ENABLE :: reserved0 [31:10] */
-#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_reserved0_MASK 0xfffffc00
-#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_reserved0_SHIFT 10
-
-/* SUN_TOP_CTRL :: RESET_SOURCE_ENABLE :: aux_chip_level_reset_1_en_lock [09:09] */
-#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_level_reset_1_en_lock_MASK 0x00000200
-#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_level_reset_1_en_lock_SHIFT 9
-#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_level_reset_1_en_lock_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: RESET_SOURCE_ENABLE :: aux_chip_level_reset_1_enable [08:08] */
-#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_level_reset_1_enable_MASK 0x00000100
-#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_level_reset_1_enable_SHIFT 8
-#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_level_reset_1_enable_DEFAULT 0x00000001
-
-/* SUN_TOP_CTRL :: RESET_SOURCE_ENABLE :: aux_chip_level_reset_0_en_lock [07:07] */
-#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_level_reset_0_en_lock_MASK 0x00000080
-#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_level_reset_0_en_lock_SHIFT 7
-#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_level_reset_0_en_lock_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: RESET_SOURCE_ENABLE :: aux_chip_level_reset_0_enable [06:06] */
-#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_level_reset_0_enable_MASK 0x00000040
-#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_level_reset_0_enable_SHIFT 6
-#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_level_reset_0_enable_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: RESET_SOURCE_ENABLE :: aux_chip_edge_reset_1_en_lock [05:05] */
-#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_edge_reset_1_en_lock_MASK 0x00000020
-#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_edge_reset_1_en_lock_SHIFT 5
-#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_edge_reset_1_en_lock_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: RESET_SOURCE_ENABLE :: aux_chip_edge_reset_1_enable [04:04] */
-#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_edge_reset_1_enable_MASK 0x00000010
-#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_edge_reset_1_enable_SHIFT 4
-#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_edge_reset_1_enable_DEFAULT 0x00000001
-
-/* SUN_TOP_CTRL :: RESET_SOURCE_ENABLE :: aux_chip_edge_reset_0_en_lock [03:03] */
-#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_edge_reset_0_en_lock_MASK 0x00000008
-#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_edge_reset_0_en_lock_SHIFT 3
-#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_edge_reset_0_en_lock_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: RESET_SOURCE_ENABLE :: aux_chip_edge_reset_0_enable [02:02] */
-#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_edge_reset_0_enable_MASK 0x00000004
-#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_edge_reset_0_enable_SHIFT 2
-#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_edge_reset_0_enable_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: RESET_SOURCE_ENABLE :: sw_master_reset_en_lock [01:01] */
-#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_sw_master_reset_en_lock_MASK 0x00000002
-#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_sw_master_reset_en_lock_SHIFT 1
-#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_sw_master_reset_en_lock_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: RESET_SOURCE_ENABLE :: sw_master_reset_enable [00:00] */
-#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_sw_master_reset_enable_MASK 0x00000001
-#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_sw_master_reset_enable_SHIFT 0
-#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_sw_master_reset_enable_DEFAULT 0x00000000
-
-/***************************************************************************
- *SW_MASTER_RESET - Software master reset
- ***************************************************************************/
-/* SUN_TOP_CTRL :: SW_MASTER_RESET :: reserved0 [31:01] */
-#define BCHP_SUN_TOP_CTRL_SW_MASTER_RESET_reserved0_MASK 0xfffffffe
-#define BCHP_SUN_TOP_CTRL_SW_MASTER_RESET_reserved0_SHIFT 1
-
-/* SUN_TOP_CTRL :: SW_MASTER_RESET :: chip_master_reset [00:00] */
-#define BCHP_SUN_TOP_CTRL_SW_MASTER_RESET_chip_master_reset_MASK 0x00000001
-#define BCHP_SUN_TOP_CTRL_SW_MASTER_RESET_chip_master_reset_SHIFT 0
-#define BCHP_SUN_TOP_CTRL_SW_MASTER_RESET_chip_master_reset_DEFAULT 0x00000000
-
-/***************************************************************************
- *HW_RESET_EXTENSION - Hardware reset extension
- ***************************************************************************/
-/* SUN_TOP_CTRL :: HW_RESET_EXTENSION :: reserved0 [31:28] */
-#define BCHP_SUN_TOP_CTRL_HW_RESET_EXTENSION_reserved0_MASK 0xf0000000
-#define BCHP_SUN_TOP_CTRL_HW_RESET_EXTENSION_reserved0_SHIFT 28
-
-/* SUN_TOP_CTRL :: HW_RESET_EXTENSION :: hw_reset_extension [27:00] */
-#define BCHP_SUN_TOP_CTRL_HW_RESET_EXTENSION_hw_reset_extension_MASK 0x0fffffff
-#define BCHP_SUN_TOP_CTRL_HW_RESET_EXTENSION_hw_reset_extension_SHIFT 0
-#define BCHP_SUN_TOP_CTRL_HW_RESET_EXTENSION_hw_reset_extension_DEFAULT 0x00000000
-
-/***************************************************************************
- *RESET_MONITOR - Reset Monitor
- ***************************************************************************/
-/* SUN_TOP_CTRL :: RESET_MONITOR :: reserved0 [31:08] */
-#define BCHP_SUN_TOP_CTRL_RESET_MONITOR_reserved0_MASK 0xffffff00
-#define BCHP_SUN_TOP_CTRL_RESET_MONITOR_reserved0_SHIFT 8
-
-/* SUN_TOP_CTRL :: RESET_MONITOR :: cpu_sw_init_def_val [07:07] */
-#define BCHP_SUN_TOP_CTRL_RESET_MONITOR_cpu_sw_init_def_val_MASK 0x00000080
-#define BCHP_SUN_TOP_CTRL_RESET_MONITOR_cpu_sw_init_def_val_SHIFT 7
-
-/* SUN_TOP_CTRL :: RESET_MONITOR :: reset_outb_def_val [06:06] */
-#define BCHP_SUN_TOP_CTRL_RESET_MONITOR_reset_outb_def_val_MASK 0x00000040
-#define BCHP_SUN_TOP_CTRL_RESET_MONITOR_reset_outb_def_val_SHIFT 6
-
-/* SUN_TOP_CTRL :: RESET_MONITOR :: hold_cpu_in_reset_monitor [05:05] */
-#define BCHP_SUN_TOP_CTRL_RESET_MONITOR_hold_cpu_in_reset_monitor_MASK 0x00000020
-#define BCHP_SUN_TOP_CTRL_RESET_MONITOR_hold_cpu_in_reset_monitor_SHIFT 5
-
-/* SUN_TOP_CTRL :: RESET_MONITOR :: reset_outb_monitor [04:04] */
-#define BCHP_SUN_TOP_CTRL_RESET_MONITOR_reset_outb_monitor_MASK 0x00000010
-#define BCHP_SUN_TOP_CTRL_RESET_MONITOR_reset_outb_monitor_SHIFT 4
-
-/* SUN_TOP_CTRL :: RESET_MONITOR :: front_panel_reset_monitor [03:03] */
-#define BCHP_SUN_TOP_CTRL_RESET_MONITOR_front_panel_reset_monitor_MASK 0x00000008
-#define BCHP_SUN_TOP_CTRL_RESET_MONITOR_front_panel_reset_monitor_SHIFT 3
-
-/* SUN_TOP_CTRL :: RESET_MONITOR :: reset_ext_mode_monitor [02:02] */
-#define BCHP_SUN_TOP_CTRL_RESET_MONITOR_reset_ext_mode_monitor_MASK 0x00000004
-#define BCHP_SUN_TOP_CTRL_RESET_MONITOR_reset_ext_mode_monitor_SHIFT 2
-
-/* SUN_TOP_CTRL :: RESET_MONITOR :: phase5_reset_timer_monitor [01:01] */
-#define BCHP_SUN_TOP_CTRL_RESET_MONITOR_phase5_reset_timer_monitor_MASK 0x00000002
-#define BCHP_SUN_TOP_CTRL_RESET_MONITOR_phase5_reset_timer_monitor_SHIFT 1
-
-/* SUN_TOP_CTRL :: RESET_MONITOR :: phase4_reset_timer_monitor [00:00] */
-#define BCHP_SUN_TOP_CTRL_RESET_MONITOR_phase4_reset_timer_monitor_MASK 0x00000001
-#define BCHP_SUN_TOP_CTRL_RESET_MONITOR_phase4_reset_timer_monitor_SHIFT 0
-
-/***************************************************************************
- *RESET_HISTORY - Reset history
- ***************************************************************************/
-/* SUN_TOP_CTRL :: RESET_HISTORY :: reserved0 [31:19] */
-#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_reserved0_MASK 0xfff80000
-#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_reserved0_SHIFT 19
-
-/* SUN_TOP_CTRL :: RESET_HISTORY :: aux_chip_level_reset_1 [18:18] */
-#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_aux_chip_level_reset_1_MASK 0x00040000
-#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_aux_chip_level_reset_1_SHIFT 18
-
-/* SUN_TOP_CTRL :: RESET_HISTORY :: aux_chip_level_reset_0 [17:17] */
-#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_aux_chip_level_reset_0_MASK 0x00020000
-#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_aux_chip_level_reset_0_SHIFT 17
-
-/* SUN_TOP_CTRL :: RESET_HISTORY :: aux_chip_edge_reset_1 [16:16] */
-#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_aux_chip_edge_reset_1_MASK 0x00010000
-#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_aux_chip_edge_reset_1_SHIFT 16
-
-/* SUN_TOP_CTRL :: RESET_HISTORY :: aux_chip_edge_reset_0 [15:15] */
-#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_aux_chip_edge_reset_0_MASK 0x00008000
-#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_aux_chip_edge_reset_0_SHIFT 15
-
-/* SUN_TOP_CTRL :: RESET_HISTORY :: undervoltage_0_reset [14:14] */
-#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_undervoltage_0_reset_MASK 0x00004000
-#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_undervoltage_0_reset_SHIFT 14
-
-/* SUN_TOP_CTRL :: RESET_HISTORY :: undervoltage_1_reset [13:13] */
-#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_undervoltage_1_reset_MASK 0x00002000
-#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_undervoltage_1_reset_SHIFT 13
-
-/* SUN_TOP_CTRL :: RESET_HISTORY :: overvoltage_1_reset [12:12] */
-#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_overvoltage_1_reset_MASK 0x00001000
-#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_overvoltage_1_reset_SHIFT 12
-
-/* SUN_TOP_CTRL :: RESET_HISTORY :: overtemp_reset [11:11] */
-#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_overtemp_reset_MASK 0x00000800
-#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_overtemp_reset_SHIFT 11
-
-/* SUN_TOP_CTRL :: RESET_HISTORY :: scpu_ejtag_reset [10:10] */
-#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_scpu_ejtag_reset_MASK 0x00000400
-#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_scpu_ejtag_reset_SHIFT 10
-
-/* SUN_TOP_CTRL :: RESET_HISTORY :: cpu_ejtag_reset [09:09] */
-#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_cpu_ejtag_reset_MASK 0x00000200
-#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_cpu_ejtag_reset_SHIFT 9
-
-/* SUN_TOP_CTRL :: RESET_HISTORY :: security_master_reset [08:08] */
-#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_security_master_reset_MASK 0x00000100
-#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_security_master_reset_SHIFT 8
-
-/* SUN_TOP_CTRL :: RESET_HISTORY :: software_master_reset [07:07] */
-#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_software_master_reset_MASK 0x00000080
-#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_software_master_reset_SHIFT 7
-
-/* SUN_TOP_CTRL :: RESET_HISTORY :: front_panel_4sec_reset [06:06] */
-#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_front_panel_4sec_reset_MASK 0x00000040
-#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_front_panel_4sec_reset_SHIFT 6
-
-/* SUN_TOP_CTRL :: RESET_HISTORY :: pcie_1_hot_boot_reset [05:05] */
-#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_pcie_1_hot_boot_reset_MASK 0x00000020
-#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_pcie_1_hot_boot_reset_SHIFT 5
-
-/* SUN_TOP_CTRL :: RESET_HISTORY :: pcie_0_hot_boot_reset [04:04] */
-#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_pcie_0_hot_boot_reset_MASK 0x00000010
-#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_pcie_0_hot_boot_reset_SHIFT 4
-
-/* SUN_TOP_CTRL :: RESET_HISTORY :: watchdog_timer_reset [03:03] */
-#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_watchdog_timer_reset_MASK 0x00000008
-#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_watchdog_timer_reset_SHIFT 3
-
-/* SUN_TOP_CTRL :: RESET_HISTORY :: smartcard_insert_reset [02:02] */
-#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_smartcard_insert_reset_MASK 0x00000004
-#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_smartcard_insert_reset_SHIFT 2
-
-/* SUN_TOP_CTRL :: RESET_HISTORY :: main_chip_reset_input [01:01] */
-#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_main_chip_reset_input_MASK 0x00000002
-#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_main_chip_reset_input_SHIFT 1
-
-/* SUN_TOP_CTRL :: RESET_HISTORY :: power_on_reset [00:00] */
-#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_power_on_reset_MASK 0x00000001
-#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_power_on_reset_SHIFT 0
-
-/***************************************************************************
- *SW_INIT_0_SET - Software init 0 set
- ***************************************************************************/
-/* SUN_TOP_CTRL :: SW_INIT_0_SET :: rfm_sw_init [31:31] */
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_rfm_sw_init_MASK 0x80000000
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_rfm_sw_init_SHIFT 31
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_rfm_sw_init_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: SW_INIT_0_SET :: not_used_sw_init_30 [30:30] */
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_30_MASK 0x40000000
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_30_SHIFT 30
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_30_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: SW_INIT_0_SET :: sata_sw_init [29:29] */
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_sata_sw_init_MASK 0x20000000
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_sata_sw_init_SHIFT 29
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_sata_sw_init_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: SW_INIT_0_SET :: moca_sw_init [28:28] */
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_moca_sw_init_MASK 0x10000000
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_moca_sw_init_SHIFT 28
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_moca_sw_init_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: SW_INIT_0_SET :: genet1_sw_init [27:27] */
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_genet1_sw_init_MASK 0x08000000
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_genet1_sw_init_SHIFT 27
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_genet1_sw_init_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: SW_INIT_0_SET :: genet0_sw_init [26:26] */
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_genet0_sw_init_MASK 0x04000000
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_genet0_sw_init_SHIFT 26
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_genet0_sw_init_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: SW_INIT_0_SET :: usb1_sw_init [25:25] */
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_usb1_sw_init_MASK 0x02000000
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_usb1_sw_init_SHIFT 25
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_usb1_sw_init_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: SW_INIT_0_SET :: usb0_sw_init [24:24] */
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_usb0_sw_init_MASK 0x01000000
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_usb0_sw_init_SHIFT 24
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_usb0_sw_init_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: SW_INIT_0_SET :: not_used_sw_init_23 [23:23] */
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_23_MASK 0x00800000
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_23_SHIFT 23
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_23_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: SW_INIT_0_SET :: not_used_sw_init_22 [22:22] */
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_22_MASK 0x00400000
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_22_SHIFT 22
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_22_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: SW_INIT_0_SET :: ddr0_sw_init [21:21] */
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_ddr0_sw_init_MASK 0x00200000
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_ddr0_sw_init_SHIFT 21
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_ddr0_sw_init_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: SW_INIT_0_SET :: not_used_sw_init_20 [20:20] */
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_20_MASK 0x00100000
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_20_SHIFT 20
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_20_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: SW_INIT_0_SET :: memc0_sw_init [19:19] */
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_memc0_sw_init_MASK 0x00080000
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_memc0_sw_init_SHIFT 19
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_memc0_sw_init_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: SW_INIT_0_SET :: xpt_sw_init [18:18] */
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_xpt_sw_init_MASK 0x00040000
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_xpt_sw_init_SHIFT 18
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_xpt_sw_init_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: SW_INIT_0_SET :: not_used_sw_init_17 [17:17] */
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_17_MASK 0x00020000
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_17_SHIFT 17
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_17_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: SW_INIT_0_SET :: raaga0_sw_init [16:16] */
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_raaga0_sw_init_MASK 0x00010000
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_raaga0_sw_init_SHIFT 16
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_raaga0_sw_init_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: SW_INIT_0_SET :: aio_sw_init [15:15] */
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_aio_sw_init_MASK 0x00008000
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_aio_sw_init_SHIFT 15
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_aio_sw_init_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: SW_INIT_0_SET :: gfx_sw_init [14:14] */
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_gfx_sw_init_MASK 0x00004000
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_gfx_sw_init_SHIFT 14
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_gfx_sw_init_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: SW_INIT_0_SET :: not_used_sw_init_13 [13:13] */
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_13_MASK 0x00002000
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_13_SHIFT 13
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_13_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: SW_INIT_0_SET :: hvd0_sw_init [12:12] */
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_hvd0_sw_init_MASK 0x00001000
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_hvd0_sw_init_SHIFT 12
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_hvd0_sw_init_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: SW_INIT_0_SET :: dvp_hr_sw_init [11:11] */
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_dvp_hr_sw_init_MASK 0x00000800
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_dvp_hr_sw_init_SHIFT 11
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_dvp_hr_sw_init_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: SW_INIT_0_SET :: dvp_ht0_sw_init [10:10] */
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_dvp_ht0_sw_init_MASK 0x00000400
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_dvp_ht0_sw_init_SHIFT 10
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_dvp_ht0_sw_init_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: SW_INIT_0_SET :: vec_sw_init [09:09] */
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_vec_sw_init_MASK 0x00000200
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_vec_sw_init_SHIFT 9
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_vec_sw_init_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: SW_INIT_0_SET :: bvn_sw_init [08:08] */
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_bvn_sw_init_MASK 0x00000100
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_bvn_sw_init_SHIFT 8
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_bvn_sw_init_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: SW_INIT_0_SET :: not_used_sw_init_7 [07:07] */
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_7_MASK 0x00000080
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_7_SHIFT 7
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_7_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: SW_INIT_0_SET :: ebi_sw_init [06:06] */
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_ebi_sw_init_MASK 0x00000040
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_ebi_sw_init_SHIFT 6
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_ebi_sw_init_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: SW_INIT_0_SET :: pcie0_sw_init [05:05] */
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_pcie0_sw_init_MASK 0x00000020
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_pcie0_sw_init_SHIFT 5
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_pcie0_sw_init_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: SW_INIT_0_SET :: webcpu_start_sw_init [04:04] */
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_webcpu_start_sw_init_MASK 0x00000010
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_webcpu_start_sw_init_SHIFT 4
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_webcpu_start_sw_init_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: SW_INIT_0_SET :: webcpu_sw_init [03:03] */
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_webcpu_sw_init_MASK 0x00000008
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_webcpu_sw_init_SHIFT 3
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_webcpu_sw_init_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: SW_INIT_0_SET :: ext_sys_sw_init [02:02] */
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_ext_sys_sw_init_MASK 0x00000004
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_ext_sys_sw_init_SHIFT 2
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_ext_sys_sw_init_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: SW_INIT_0_SET :: cpu_sw_init [01:01] */
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_cpu_sw_init_MASK 0x00000002
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_cpu_sw_init_SHIFT 1
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_cpu_sw_init_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: SW_INIT_0_SET :: sys_ctrl_sw_init [00:00] */
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_sys_ctrl_sw_init_MASK 0x00000001
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_sys_ctrl_sw_init_SHIFT 0
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_sys_ctrl_sw_init_DEFAULT 0x00000000
-
-/***************************************************************************
- *SW_INIT_0_CLEAR - Software init 0 clear
- ***************************************************************************/
-/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: rfm_sw_init [31:31] */
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_rfm_sw_init_MASK 0x80000000
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_rfm_sw_init_SHIFT 31
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_rfm_sw_init_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: not_used_sw_init_30 [30:30] */
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_30_MASK 0x40000000
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_30_SHIFT 30
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_30_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: sata_sw_init [29:29] */
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_sata_sw_init_MASK 0x20000000
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_sata_sw_init_SHIFT 29
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_sata_sw_init_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: moca_sw_init [28:28] */
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_moca_sw_init_MASK 0x10000000
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_moca_sw_init_SHIFT 28
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_moca_sw_init_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: genet1_sw_init [27:27] */
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_genet1_sw_init_MASK 0x08000000
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_genet1_sw_init_SHIFT 27
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_genet1_sw_init_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: genet0_sw_init [26:26] */
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_genet0_sw_init_MASK 0x04000000
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_genet0_sw_init_SHIFT 26
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_genet0_sw_init_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: usb1_sw_init [25:25] */
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_usb1_sw_init_MASK 0x02000000
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_usb1_sw_init_SHIFT 25
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_usb1_sw_init_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: usb0_sw_init [24:24] */
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_usb0_sw_init_MASK 0x01000000
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_usb0_sw_init_SHIFT 24
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_usb0_sw_init_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: not_used_sw_init_23 [23:23] */
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_23_MASK 0x00800000
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_23_SHIFT 23
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_23_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: not_used_sw_init_22 [22:22] */
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_22_MASK 0x00400000
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_22_SHIFT 22
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_22_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: ddr0_sw_init [21:21] */
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_ddr0_sw_init_MASK 0x00200000
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_ddr0_sw_init_SHIFT 21
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_ddr0_sw_init_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: not_used_sw_init_20 [20:20] */
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_20_MASK 0x00100000
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_20_SHIFT 20
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_20_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: memc0_sw_init [19:19] */
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_memc0_sw_init_MASK 0x00080000
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_memc0_sw_init_SHIFT 19
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_memc0_sw_init_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: xpt_sw_init [18:18] */
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_xpt_sw_init_MASK 0x00040000
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_xpt_sw_init_SHIFT 18
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_xpt_sw_init_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: not_used_sw_init_17 [17:17] */
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_17_MASK 0x00020000
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_17_SHIFT 17
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_17_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: raaga0_sw_init [16:16] */
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_raaga0_sw_init_MASK 0x00010000
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_raaga0_sw_init_SHIFT 16
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_raaga0_sw_init_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: aio_sw_init [15:15] */
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_aio_sw_init_MASK 0x00008000
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_aio_sw_init_SHIFT 15
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_aio_sw_init_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: gfx_sw_init [14:14] */
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_gfx_sw_init_MASK 0x00004000
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_gfx_sw_init_SHIFT 14
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_gfx_sw_init_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: not_used_sw_init_13 [13:13] */
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_13_MASK 0x00002000
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_13_SHIFT 13
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_13_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: hvd0_sw_init [12:12] */
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_hvd0_sw_init_MASK 0x00001000
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_hvd0_sw_init_SHIFT 12
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_hvd0_sw_init_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: dvp_hr_sw_init [11:11] */
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_dvp_hr_sw_init_MASK 0x00000800
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_dvp_hr_sw_init_SHIFT 11
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_dvp_hr_sw_init_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: dvp_ht0_sw_init [10:10] */
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_dvp_ht0_sw_init_MASK 0x00000400
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_dvp_ht0_sw_init_SHIFT 10
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_dvp_ht0_sw_init_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: vec_sw_init [09:09] */
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_vec_sw_init_MASK 0x00000200
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_vec_sw_init_SHIFT 9
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_vec_sw_init_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: bvn_sw_init [08:08] */
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_bvn_sw_init_MASK 0x00000100
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_bvn_sw_init_SHIFT 8
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_bvn_sw_init_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: not_used_sw_init_7 [07:07] */
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_7_MASK 0x00000080
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_7_SHIFT 7
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_7_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: ebi_sw_init [06:06] */
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_ebi_sw_init_MASK 0x00000040
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_ebi_sw_init_SHIFT 6
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_ebi_sw_init_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: pcie0_sw_init [05:05] */
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_pcie0_sw_init_MASK 0x00000020
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_pcie0_sw_init_SHIFT 5
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_pcie0_sw_init_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: webcpu_start_sw_init [04:04] */
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_webcpu_start_sw_init_MASK 0x00000010
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_webcpu_start_sw_init_SHIFT 4
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_webcpu_start_sw_init_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: webcpu_sw_init [03:03] */
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_webcpu_sw_init_MASK 0x00000008
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_webcpu_sw_init_SHIFT 3
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_webcpu_sw_init_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: ext_sys_sw_init [02:02] */
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_ext_sys_sw_init_MASK 0x00000004
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_ext_sys_sw_init_SHIFT 2
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_ext_sys_sw_init_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: cpu_sw_init [01:01] */
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_cpu_sw_init_MASK 0x00000002
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_cpu_sw_init_SHIFT 1
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_cpu_sw_init_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: sys_ctrl_sw_init [00:00] */
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_sys_ctrl_sw_init_MASK 0x00000001
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_sys_ctrl_sw_init_SHIFT 0
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_sys_ctrl_sw_init_DEFAULT 0x00000000
-
-/***************************************************************************
- *SW_INIT_0_STATUS - Software init 0 status
- ***************************************************************************/
-/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: rfm_sw_init [31:31] */
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_rfm_sw_init_MASK 0x80000000
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_rfm_sw_init_SHIFT 31
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_rfm_sw_init_DEFAULT 0x00000001
-
-/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: not_used_sw_init_30 [30:30] */
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_30_MASK 0x40000000
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_30_SHIFT 30
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_30_DEFAULT 0x00000001
-
-/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: sata_sw_init [29:29] */
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_sata_sw_init_MASK 0x20000000
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_sata_sw_init_SHIFT 29
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_sata_sw_init_DEFAULT 0x00000001
-
-/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: moca_sw_init [28:28] */
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_moca_sw_init_MASK 0x10000000
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_moca_sw_init_SHIFT 28
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_moca_sw_init_DEFAULT 0x00000001
-
-/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: genet1_sw_init [27:27] */
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_genet1_sw_init_MASK 0x08000000
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_genet1_sw_init_SHIFT 27
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_genet1_sw_init_DEFAULT 0x00000001
-
-/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: genet0_sw_init [26:26] */
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_genet0_sw_init_MASK 0x04000000
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_genet0_sw_init_SHIFT 26
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_genet0_sw_init_DEFAULT 0x00000001
-
-/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: usb1_sw_init [25:25] */
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_usb1_sw_init_MASK 0x02000000
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_usb1_sw_init_SHIFT 25
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_usb1_sw_init_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: usb0_sw_init [24:24] */
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_usb0_sw_init_MASK 0x01000000
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_usb0_sw_init_SHIFT 24
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_usb0_sw_init_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: not_used_sw_init_23 [23:23] */
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_23_MASK 0x00800000
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_23_SHIFT 23
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_23_DEFAULT 0x00000001
-
-/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: not_used_sw_init_22 [22:22] */
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_22_MASK 0x00400000
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_22_SHIFT 22
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_22_DEFAULT 0x00000001
-
-/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: ddr0_sw_init [21:21] */
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_ddr0_sw_init_MASK 0x00200000
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_ddr0_sw_init_SHIFT 21
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_ddr0_sw_init_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: not_used_sw_init_20 [20:20] */
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_20_MASK 0x00100000
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_20_SHIFT 20
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_20_DEFAULT 0x00000001
-
-/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: memc0_sw_init [19:19] */
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_memc0_sw_init_MASK 0x00080000
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_memc0_sw_init_SHIFT 19
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_memc0_sw_init_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: xpt_sw_init [18:18] */
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_xpt_sw_init_MASK 0x00040000
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_xpt_sw_init_SHIFT 18
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_xpt_sw_init_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: not_used_sw_init_17 [17:17] */
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_17_MASK 0x00020000
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_17_SHIFT 17
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_17_DEFAULT 0x00000001
-
-/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: raaga0_sw_init [16:16] */
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_raaga0_sw_init_MASK 0x00010000
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_raaga0_sw_init_SHIFT 16
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_raaga0_sw_init_DEFAULT 0x00000001
-
-/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: aio_sw_init [15:15] */
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_aio_sw_init_MASK 0x00008000
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_aio_sw_init_SHIFT 15
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_aio_sw_init_DEFAULT 0x00000001
-
-/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: gfx_sw_init [14:14] */
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_gfx_sw_init_MASK 0x00004000
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_gfx_sw_init_SHIFT 14
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_gfx_sw_init_DEFAULT 0x00000001
-
-/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: not_used_sw_init_13 [13:13] */
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_13_MASK 0x00002000
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_13_SHIFT 13
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_13_DEFAULT 0x00000001
-
-/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: hvd0_sw_init [12:12] */
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_hvd0_sw_init_MASK 0x00001000
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_hvd0_sw_init_SHIFT 12
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_hvd0_sw_init_DEFAULT 0x00000001
-
-/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: dvp_hr_sw_init [11:11] */
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_dvp_hr_sw_init_MASK 0x00000800
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_dvp_hr_sw_init_SHIFT 11
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_dvp_hr_sw_init_DEFAULT 0x00000001
-
-/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: dvp_ht0_sw_init [10:10] */
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_dvp_ht0_sw_init_MASK 0x00000400
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_dvp_ht0_sw_init_SHIFT 10
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_dvp_ht0_sw_init_DEFAULT 0x00000001
-
-/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: vec_sw_init [09:09] */
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_vec_sw_init_MASK 0x00000200
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_vec_sw_init_SHIFT 9
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_vec_sw_init_DEFAULT 0x00000001
-
-/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: bvn_sw_init [08:08] */
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_bvn_sw_init_MASK 0x00000100
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_bvn_sw_init_SHIFT 8
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_bvn_sw_init_DEFAULT 0x00000001
-
-/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: not_used_sw_init_7 [07:07] */
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_7_MASK 0x00000080
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_7_SHIFT 7
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_7_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: ebi_sw_init [06:06] */
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_ebi_sw_init_MASK 0x00000040
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_ebi_sw_init_SHIFT 6
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_ebi_sw_init_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: pcie0_sw_init [05:05] */
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_pcie0_sw_init_MASK 0x00000020
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_pcie0_sw_init_SHIFT 5
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_pcie0_sw_init_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: webcpu_start_sw_init [04:04] */
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_webcpu_start_sw_init_MASK 0x00000010
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_webcpu_start_sw_init_SHIFT 4
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_webcpu_start_sw_init_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: webcpu_sw_init [03:03] */
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_webcpu_sw_init_MASK 0x00000008
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_webcpu_sw_init_SHIFT 3
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_webcpu_sw_init_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: ext_sys_sw_init [02:02] */
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_ext_sys_sw_init_MASK 0x00000004
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_ext_sys_sw_init_SHIFT 2
-
-/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: cpu_sw_init [01:01] */
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_cpu_sw_init_MASK 0x00000002
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_cpu_sw_init_SHIFT 1
-
-/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: sys_ctrl_sw_init [00:00] */
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_sys_ctrl_sw_init_MASK 0x00000001
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_sys_ctrl_sw_init_SHIFT 0
-#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_sys_ctrl_sw_init_DEFAULT 0x00000000
-
-/***************************************************************************
- *SEC_SW_INIT_0_MONITOR - Security software init 0 monitor
- ***************************************************************************/
-/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: rfm_sw_init [31:31] */
-#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_rfm_sw_init_MASK 0x80000000
-#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_rfm_sw_init_SHIFT 31
-
-/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: not_used_sw_init_30 [30:30] */
-#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_not_used_sw_init_30_MASK 0x40000000
-#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_not_used_sw_init_30_SHIFT 30
-
-/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: sata_sw_init [29:29] */
-#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_sata_sw_init_MASK 0x20000000
-#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_sata_sw_init_SHIFT 29
-
-/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: moca_sw_init [28:28] */
-#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_moca_sw_init_MASK 0x10000000
-#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_moca_sw_init_SHIFT 28
-
-/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: genet1_sw_init [27:27] */
-#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_genet1_sw_init_MASK 0x08000000
-#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_genet1_sw_init_SHIFT 27
-
-/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: genet0_sw_init [26:26] */
-#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_genet0_sw_init_MASK 0x04000000
-#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_genet0_sw_init_SHIFT 26
-
-/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: usb1_sw_init [25:25] */
-#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_usb1_sw_init_MASK 0x02000000
-#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_usb1_sw_init_SHIFT 25
-
-/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: usb0_sw_init [24:24] */
-#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_usb0_sw_init_MASK 0x01000000
-#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_usb0_sw_init_SHIFT 24
-
-/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: not_used_sw_init_23 [23:23] */
-#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_not_used_sw_init_23_MASK 0x00800000
-#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_not_used_sw_init_23_SHIFT 23
-
-/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: not_used_sw_init_22 [22:22] */
-#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_not_used_sw_init_22_MASK 0x00400000
-#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_not_used_sw_init_22_SHIFT 22
-
-/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: ddr0_sw_init [21:21] */
-#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_ddr0_sw_init_MASK 0x00200000
-#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_ddr0_sw_init_SHIFT 21
-
-/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: not_used_sw_init_20 [20:20] */
-#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_not_used_sw_init_20_MASK 0x00100000
-#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_not_used_sw_init_20_SHIFT 20
-
-/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: memc0_sw_init [19:19] */
-#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_memc0_sw_init_MASK 0x00080000
-#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_memc0_sw_init_SHIFT 19
-
-/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: xpt_sw_init [18:18] */
-#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_xpt_sw_init_MASK 0x00040000
-#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_xpt_sw_init_SHIFT 18
-
-/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: not_used_sw_init_17 [17:17] */
-#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_not_used_sw_init_17_MASK 0x00020000
-#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_not_used_sw_init_17_SHIFT 17
-
-/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: raaga0_sw_init [16:16] */
-#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_raaga0_sw_init_MASK 0x00010000
-#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_raaga0_sw_init_SHIFT 16
-
-/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: aio_sw_init [15:15] */
-#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_aio_sw_init_MASK 0x00008000
-#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_aio_sw_init_SHIFT 15
-
-/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: gfx_sw_init [14:14] */
-#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_gfx_sw_init_MASK 0x00004000
-#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_gfx_sw_init_SHIFT 14
-
-/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: not_used_sw_init_13 [13:13] */
-#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_not_used_sw_init_13_MASK 0x00002000
-#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_not_used_sw_init_13_SHIFT 13
-
-/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: hvd0_sw_init [12:12] */
-#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_hvd0_sw_init_MASK 0x00001000
-#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_hvd0_sw_init_SHIFT 12
-
-/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: dvp_hr_sw_init [11:11] */
-#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_dvp_hr_sw_init_MASK 0x00000800
-#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_dvp_hr_sw_init_SHIFT 11
-
-/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: dvp_ht0_sw_init [10:10] */
-#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_dvp_ht0_sw_init_MASK 0x00000400
-#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_dvp_ht0_sw_init_SHIFT 10
-
-/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: vec_sw_init [09:09] */
-#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_vec_sw_init_MASK 0x00000200
-#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_vec_sw_init_SHIFT 9
-
-/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: bvn_sw_init [08:08] */
-#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_bvn_sw_init_MASK 0x00000100
-#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_bvn_sw_init_SHIFT 8
-
-/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: not_used_sw_init_7 [07:07] */
-#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_not_used_sw_init_7_MASK 0x00000080
-#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_not_used_sw_init_7_SHIFT 7
-
-/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: ebi_sw_init [06:06] */
-#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_ebi_sw_init_MASK 0x00000040
-#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_ebi_sw_init_SHIFT 6
-
-/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: pcie0_sw_init [05:05] */
-#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_pcie0_sw_init_MASK 0x00000020
-#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_pcie0_sw_init_SHIFT 5
-
-/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: webcpu_start_sw_init [04:04] */
-#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_webcpu_start_sw_init_MASK 0x00000010
-#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_webcpu_start_sw_init_SHIFT 4
-
-/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: webcpu_sw_init [03:03] */
-#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_webcpu_sw_init_MASK 0x00000008
-#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_webcpu_sw_init_SHIFT 3
-
-/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: ext_sys_sw_init [02:02] */
-#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_ext_sys_sw_init_MASK 0x00000004
-#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_ext_sys_sw_init_SHIFT 2
-
-/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: cpu_sw_init [01:01] */
-#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_cpu_sw_init_MASK 0x00000002
-#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_cpu_sw_init_SHIFT 1
-
-/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: sys_ctrl_sw_init [00:00] */
-#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_sys_ctrl_sw_init_MASK 0x00000001
-#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_sys_ctrl_sw_init_SHIFT 0
-
-/***************************************************************************
- *TEST_CONFIG_SW_INIT_0_MONITOR - Test configuration software init 0 monitor
- ***************************************************************************/
-/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: rfm_sw_init [31:31] */
-#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_rfm_sw_init_MASK 0x80000000
-#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_rfm_sw_init_SHIFT 31
-
-/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: not_used_sw_init_30 [30:30] */
-#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_not_used_sw_init_30_MASK 0x40000000
-#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_not_used_sw_init_30_SHIFT 30
-
-/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: sata_sw_init [29:29] */
-#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_sata_sw_init_MASK 0x20000000
-#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_sata_sw_init_SHIFT 29
-
-/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: moca_sw_init [28:28] */
-#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_moca_sw_init_MASK 0x10000000
-#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_moca_sw_init_SHIFT 28
-
-/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: genet1_sw_init [27:27] */
-#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_genet1_sw_init_MASK 0x08000000
-#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_genet1_sw_init_SHIFT 27
-
-/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: genet0_sw_init [26:26] */
-#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_genet0_sw_init_MASK 0x04000000
-#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_genet0_sw_init_SHIFT 26
-
-/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: usb1_sw_init [25:25] */
-#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_usb1_sw_init_MASK 0x02000000
-#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_usb1_sw_init_SHIFT 25
-
-/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: usb0_sw_init [24:24] */
-#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_usb0_sw_init_MASK 0x01000000
-#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_usb0_sw_init_SHIFT 24
-
-/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: not_used_sw_init_23 [23:23] */
-#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_not_used_sw_init_23_MASK 0x00800000
-#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_not_used_sw_init_23_SHIFT 23
-
-/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: not_used_sw_init_22 [22:22] */
-#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_not_used_sw_init_22_MASK 0x00400000
-#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_not_used_sw_init_22_SHIFT 22
-
-/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: ddr0_sw_init [21:21] */
-#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_ddr0_sw_init_MASK 0x00200000
-#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_ddr0_sw_init_SHIFT 21
-
-/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: not_used_sw_init_20 [20:20] */
-#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_not_used_sw_init_20_MASK 0x00100000
-#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_not_used_sw_init_20_SHIFT 20
-
-/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: memc0_sw_init [19:19] */
-#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_memc0_sw_init_MASK 0x00080000
-#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_memc0_sw_init_SHIFT 19
-
-/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: xpt_sw_init [18:18] */
-#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_xpt_sw_init_MASK 0x00040000
-#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_xpt_sw_init_SHIFT 18
-
-/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: not_used_sw_init_17 [17:17] */
-#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_not_used_sw_init_17_MASK 0x00020000
-#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_not_used_sw_init_17_SHIFT 17
-
-/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: raaga0_sw_init [16:16] */
-#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_raaga0_sw_init_MASK 0x00010000
-#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_raaga0_sw_init_SHIFT 16
-
-/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: aio_sw_init [15:15] */
-#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_aio_sw_init_MASK 0x00008000
-#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_aio_sw_init_SHIFT 15
-
-/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: gfx_sw_init [14:14] */
-#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_gfx_sw_init_MASK 0x00004000
-#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_gfx_sw_init_SHIFT 14
-
-/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: not_used_sw_init_13 [13:13] */
-#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_not_used_sw_init_13_MASK 0x00002000
-#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_not_used_sw_init_13_SHIFT 13
-
-/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: hvd0_sw_init [12:12] */
-#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_hvd0_sw_init_MASK 0x00001000
-#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_hvd0_sw_init_SHIFT 12
-
-/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: dvp_hr_sw_init [11:11] */
-#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_dvp_hr_sw_init_MASK 0x00000800
-#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_dvp_hr_sw_init_SHIFT 11
-
-/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: dvp_ht0_sw_init [10:10] */
-#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_dvp_ht0_sw_init_MASK 0x00000400
-#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_dvp_ht0_sw_init_SHIFT 10
-
-/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: vec_sw_init [09:09] */
-#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_vec_sw_init_MASK 0x00000200
-#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_vec_sw_init_SHIFT 9
-
-/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: bvn_sw_init [08:08] */
-#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_bvn_sw_init_MASK 0x00000100
-#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_bvn_sw_init_SHIFT 8
-
-/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: not_used_sw_init_7 [07:07] */
-#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_not_used_sw_init_7_MASK 0x00000080
-#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_not_used_sw_init_7_SHIFT 7
-
-/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: ebi_sw_init [06:06] */
-#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_ebi_sw_init_MASK 0x00000040
-#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_ebi_sw_init_SHIFT 6
-
-/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: pcie0_sw_init [05:05] */
-#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_pcie0_sw_init_MASK 0x00000020
-#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_pcie0_sw_init_SHIFT 5
-
-/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: webcpu_start_sw_init [04:04] */
-#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_webcpu_start_sw_init_MASK 0x00000010
-#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_webcpu_start_sw_init_SHIFT 4
-
-/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: webcpu_sw_init [03:03] */
-#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_webcpu_sw_init_MASK 0x00000008
-#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_webcpu_sw_init_SHIFT 3
-
-/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: ext_sys_sw_init [02:02] */
-#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_ext_sys_sw_init_MASK 0x00000004
-#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_ext_sys_sw_init_SHIFT 2
-
-/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: cpu_sw_init [01:01] */
-#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_cpu_sw_init_MASK 0x00000002
-#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_cpu_sw_init_SHIFT 1
-
-/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: sys_ctrl_sw_init [00:00] */
-#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_sys_ctrl_sw_init_MASK 0x00000001
-#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_sys_ctrl_sw_init_SHIFT 0
-
-/***************************************************************************
- *FINAL_SW_INIT_0_MONITOR - Final software init 0 monitor
- ***************************************************************************/
-/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: rfm_sw_init [31:31] */
-#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_rfm_sw_init_MASK 0x80000000
-#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_rfm_sw_init_SHIFT 31
-
-/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: not_used_sw_init_30 [30:30] */
-#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_not_used_sw_init_30_MASK 0x40000000
-#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_not_used_sw_init_30_SHIFT 30
-
-/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: sata_sw_init [29:29] */
-#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_sata_sw_init_MASK 0x20000000
-#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_sata_sw_init_SHIFT 29
-
-/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: moca_sw_init [28:28] */
-#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_moca_sw_init_MASK 0x10000000
-#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_moca_sw_init_SHIFT 28
-
-/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: genet1_sw_init [27:27] */
-#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_genet1_sw_init_MASK 0x08000000
-#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_genet1_sw_init_SHIFT 27
-
-/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: genet0_sw_init [26:26] */
-#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_genet0_sw_init_MASK 0x04000000
-#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_genet0_sw_init_SHIFT 26
-
-/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: usb1_sw_init [25:25] */
-#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_usb1_sw_init_MASK 0x02000000
-#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_usb1_sw_init_SHIFT 25
-
-/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: usb0_sw_init [24:24] */
-#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_usb0_sw_init_MASK 0x01000000
-#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_usb0_sw_init_SHIFT 24
-
-/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: not_used_sw_init_23 [23:23] */
-#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_not_used_sw_init_23_MASK 0x00800000
-#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_not_used_sw_init_23_SHIFT 23
-
-/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: not_used_sw_init_22 [22:22] */
-#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_not_used_sw_init_22_MASK 0x00400000
-#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_not_used_sw_init_22_SHIFT 22
-
-/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: ddr0_sw_init [21:21] */
-#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_ddr0_sw_init_MASK 0x00200000
-#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_ddr0_sw_init_SHIFT 21
-
-/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: not_used_sw_init_20 [20:20] */
-#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_not_used_sw_init_20_MASK 0x00100000
-#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_not_used_sw_init_20_SHIFT 20
-
-/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: memc0_sw_init [19:19] */
-#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_memc0_sw_init_MASK 0x00080000
-#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_memc0_sw_init_SHIFT 19
-
-/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: xpt_sw_init [18:18] */
-#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_xpt_sw_init_MASK 0x00040000
-#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_xpt_sw_init_SHIFT 18
-
-/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: not_used_sw_init_17 [17:17] */
-#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_not_used_sw_init_17_MASK 0x00020000
-#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_not_used_sw_init_17_SHIFT 17
-
-/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: raaga0_sw_init [16:16] */
-#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_raaga0_sw_init_MASK 0x00010000
-#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_raaga0_sw_init_SHIFT 16
-
-/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: aio_sw_init [15:15] */
-#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_aio_sw_init_MASK 0x00008000
-#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_aio_sw_init_SHIFT 15
-
-/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: gfx_sw_init [14:14] */
-#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_gfx_sw_init_MASK 0x00004000
-#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_gfx_sw_init_SHIFT 14
-
-/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: not_used_sw_init_13 [13:13] */
-#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_not_used_sw_init_13_MASK 0x00002000
-#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_not_used_sw_init_13_SHIFT 13
-
-/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: hvd0_sw_init [12:12] */
-#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_hvd0_sw_init_MASK 0x00001000
-#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_hvd0_sw_init_SHIFT 12
-
-/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: dvp_hr_sw_init [11:11] */
-#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_dvp_hr_sw_init_MASK 0x00000800
-#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_dvp_hr_sw_init_SHIFT 11
-
-/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: dvp_ht0_sw_init [10:10] */
-#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_dvp_ht0_sw_init_MASK 0x00000400
-#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_dvp_ht0_sw_init_SHIFT 10
-
-/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: vec_sw_init [09:09] */
-#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_vec_sw_init_MASK 0x00000200
-#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_vec_sw_init_SHIFT 9
-
-/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: bvn_sw_init [08:08] */
-#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_bvn_sw_init_MASK 0x00000100
-#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_bvn_sw_init_SHIFT 8
-
-/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: not_used_sw_init_7 [07:07] */
-#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_not_used_sw_init_7_MASK 0x00000080
-#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_not_used_sw_init_7_SHIFT 7
-
-/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: ebi_sw_init [06:06] */
-#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_ebi_sw_init_MASK 0x00000040
-#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_ebi_sw_init_SHIFT 6
-
-/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: pcie0_sw_init [05:05] */
-#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_pcie0_sw_init_MASK 0x00000020
-#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_pcie0_sw_init_SHIFT 5
-
-/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: webcpu_start_sw_init [04:04] */
-#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_webcpu_start_sw_init_MASK 0x00000010
-#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_webcpu_start_sw_init_SHIFT 4
-
-/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: webcpu_sw_init [03:03] */
-#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_webcpu_sw_init_MASK 0x00000008
-#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_webcpu_sw_init_SHIFT 3
-
-/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: ext_sys_sw_init [02:02] */
-#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_ext_sys_sw_init_MASK 0x00000004
-#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_ext_sys_sw_init_SHIFT 2
-
-/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: cpu_sw_init [01:01] */
-#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_cpu_sw_init_MASK 0x00000002
-#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_cpu_sw_init_SHIFT 1
-
-/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: sys_ctrl_sw_init [00:00] */
-#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_sys_ctrl_sw_init_MASK 0x00000001
-#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_sys_ctrl_sw_init_SHIFT 0
-
-/***************************************************************************
- *SW_INIT_1_SET - Software init 1 set
- ***************************************************************************/
-/* SUN_TOP_CTRL :: SW_INIT_1_SET :: reserved0 [31:08] */
-#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_reserved0_MASK 0xffffff00
-#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_reserved0_SHIFT 8
-
-/* SUN_TOP_CTRL :: SW_INIT_1_SET :: spare1_sw_init [07:07] */
-#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_spare1_sw_init_MASK 0x00000080
-#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_spare1_sw_init_SHIFT 7
-#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_spare1_sw_init_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: SW_INIT_1_SET :: spare0_sw_init [06:06] */
-#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_spare0_sw_init_MASK 0x00000040
-#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_spare0_sw_init_SHIFT 6
-#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_spare0_sw_init_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: SW_INIT_1_SET :: dvp_ht1_sw_init [05:05] */
-#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_dvp_ht1_sw_init_MASK 0x00000020
-#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_dvp_ht1_sw_init_SHIFT 5
-#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_dvp_ht1_sw_init_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: SW_INIT_1_SET :: gphy_sw_init [04:04] */
-#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_gphy_sw_init_MASK 0x00000010
-#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_gphy_sw_init_SHIFT 4
-#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_gphy_sw_init_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: SW_INIT_1_SET :: m2mc1_sw_init [03:03] */
-#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_m2mc1_sw_init_MASK 0x00000008
-#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_m2mc1_sw_init_SHIFT 3
-#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_m2mc1_sw_init_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: SW_INIT_1_SET :: v3d_top_sw_init [02:02] */
-#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_v3d_top_sw_init_MASK 0x00000004
-#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_v3d_top_sw_init_SHIFT 2
-#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_v3d_top_sw_init_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: SW_INIT_1_SET :: vice20_sw_init [01:01] */
-#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_vice20_sw_init_MASK 0x00000002
-#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_vice20_sw_init_SHIFT 1
-#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_vice20_sw_init_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: SW_INIT_1_SET :: sid_sw_init [00:00] */
-#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_sid_sw_init_MASK 0x00000001
-#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_sid_sw_init_SHIFT 0
-#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_sid_sw_init_DEFAULT 0x00000000
-
-/***************************************************************************
- *SW_INIT_1_CLEAR - Software init 1 clear
- ***************************************************************************/
-/* SUN_TOP_CTRL :: SW_INIT_1_CLEAR :: reserved0 [31:08] */
-#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_reserved0_MASK 0xffffff00
-#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_reserved0_SHIFT 8
-
-/* SUN_TOP_CTRL :: SW_INIT_1_CLEAR :: spare1_sw_init [07:07] */
-#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_spare1_sw_init_MASK 0x00000080
-#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_spare1_sw_init_SHIFT 7
-#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_spare1_sw_init_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: SW_INIT_1_CLEAR :: spare0_sw_init [06:06] */
-#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_spare0_sw_init_MASK 0x00000040
-#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_spare0_sw_init_SHIFT 6
-#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_spare0_sw_init_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: SW_INIT_1_CLEAR :: dvp_ht1_sw_init [05:05] */
-#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_dvp_ht1_sw_init_MASK 0x00000020
-#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_dvp_ht1_sw_init_SHIFT 5
-#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_dvp_ht1_sw_init_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: SW_INIT_1_CLEAR :: gphy_sw_init [04:04] */
-#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_gphy_sw_init_MASK 0x00000010
-#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_gphy_sw_init_SHIFT 4
-#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_gphy_sw_init_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: SW_INIT_1_CLEAR :: m2mc1_sw_init [03:03] */
-#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_m2mc1_sw_init_MASK 0x00000008
-#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_m2mc1_sw_init_SHIFT 3
-#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_m2mc1_sw_init_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: SW_INIT_1_CLEAR :: v3d_top_sw_init [02:02] */
-#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_v3d_top_sw_init_MASK 0x00000004
-#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_v3d_top_sw_init_SHIFT 2
-#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_v3d_top_sw_init_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: SW_INIT_1_CLEAR :: vice20_sw_init [01:01] */
-#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_vice20_sw_init_MASK 0x00000002
-#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_vice20_sw_init_SHIFT 1
-#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_vice20_sw_init_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: SW_INIT_1_CLEAR :: sid_sw_init [00:00] */
-#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_sid_sw_init_MASK 0x00000001
-#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_sid_sw_init_SHIFT 0
-#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_sid_sw_init_DEFAULT 0x00000000
-
-/***************************************************************************
- *SW_INIT_1_STATUS - Software init 1 status
- ***************************************************************************/
-/* SUN_TOP_CTRL :: SW_INIT_1_STATUS :: reserved0 [31:08] */
-#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_reserved0_MASK 0xffffff00
-#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_reserved0_SHIFT 8
-
-/* SUN_TOP_CTRL :: SW_INIT_1_STATUS :: spare1_sw_init [07:07] */
-#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_spare1_sw_init_MASK 0x00000080
-#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_spare1_sw_init_SHIFT 7
-#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_spare1_sw_init_DEFAULT 0x00000001
-
-/* SUN_TOP_CTRL :: SW_INIT_1_STATUS :: spare0_sw_init [06:06] */
-#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_spare0_sw_init_MASK 0x00000040
-#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_spare0_sw_init_SHIFT 6
-#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_spare0_sw_init_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: SW_INIT_1_STATUS :: dvp_ht1_sw_init [05:05] */
-#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_dvp_ht1_sw_init_MASK 0x00000020
-#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_dvp_ht1_sw_init_SHIFT 5
-#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_dvp_ht1_sw_init_DEFAULT 0x00000001
-
-/* SUN_TOP_CTRL :: SW_INIT_1_STATUS :: gphy_sw_init [04:04] */
-#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_gphy_sw_init_MASK 0x00000010
-#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_gphy_sw_init_SHIFT 4
-#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_gphy_sw_init_DEFAULT 0x00000001
-
-/* SUN_TOP_CTRL :: SW_INIT_1_STATUS :: m2mc1_sw_init [03:03] */
-#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_m2mc1_sw_init_MASK 0x00000008
-#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_m2mc1_sw_init_SHIFT 3
-#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_m2mc1_sw_init_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: SW_INIT_1_STATUS :: v3d_top_sw_init [02:02] */
-#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_v3d_top_sw_init_MASK 0x00000004
-#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_v3d_top_sw_init_SHIFT 2
-#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_v3d_top_sw_init_DEFAULT 0x00000001
-
-/* SUN_TOP_CTRL :: SW_INIT_1_STATUS :: vice20_sw_init [01:01] */
-#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_vice20_sw_init_MASK 0x00000002
-#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_vice20_sw_init_SHIFT 1
-#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_vice20_sw_init_DEFAULT 0x00000001
-
-/* SUN_TOP_CTRL :: SW_INIT_1_STATUS :: sid_sw_init [00:00] */
-#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_sid_sw_init_MASK 0x00000001
-#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_sid_sw_init_SHIFT 0
-#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_sid_sw_init_DEFAULT 0x00000001
-
-/***************************************************************************
- *SEC_SW_INIT_1_MONITOR - Security software init 1 monitor
- ***************************************************************************/
-/* SUN_TOP_CTRL :: SEC_SW_INIT_1_MONITOR :: reserved0 [31:08] */
-#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_reserved0_MASK 0xffffff00
-#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_reserved0_SHIFT 8
-
-/* SUN_TOP_CTRL :: SEC_SW_INIT_1_MONITOR :: spare1_sw_init [07:07] */
-#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_spare1_sw_init_MASK 0x00000080
-#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_spare1_sw_init_SHIFT 7
-
-/* SUN_TOP_CTRL :: SEC_SW_INIT_1_MONITOR :: spare0_sw_init [06:06] */
-#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_spare0_sw_init_MASK 0x00000040
-#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_spare0_sw_init_SHIFT 6
-
-/* SUN_TOP_CTRL :: SEC_SW_INIT_1_MONITOR :: dvp_ht1_sw_init [05:05] */
-#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_dvp_ht1_sw_init_MASK 0x00000020
-#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_dvp_ht1_sw_init_SHIFT 5
-
-/* SUN_TOP_CTRL :: SEC_SW_INIT_1_MONITOR :: gphy_sw_init [04:04] */
-#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_gphy_sw_init_MASK 0x00000010
-#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_gphy_sw_init_SHIFT 4
-
-/* SUN_TOP_CTRL :: SEC_SW_INIT_1_MONITOR :: m2mc1_sw_init [03:03] */
-#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_m2mc1_sw_init_MASK 0x00000008
-#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_m2mc1_sw_init_SHIFT 3
-
-/* SUN_TOP_CTRL :: SEC_SW_INIT_1_MONITOR :: v3d_top_sw_init [02:02] */
-#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_v3d_top_sw_init_MASK 0x00000004
-#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_v3d_top_sw_init_SHIFT 2
-
-/* SUN_TOP_CTRL :: SEC_SW_INIT_1_MONITOR :: vice20_sw_init [01:01] */
-#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_vice20_sw_init_MASK 0x00000002
-#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_vice20_sw_init_SHIFT 1
-
-/* SUN_TOP_CTRL :: SEC_SW_INIT_1_MONITOR :: sid_sw_init [00:00] */
-#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_sid_sw_init_MASK 0x00000001
-#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_sid_sw_init_SHIFT 0
-
-/***************************************************************************
- *TEST_CONFIG_SW_INIT_1_MONITOR - Test configuration software init 1 monitor
- ***************************************************************************/
-/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_1_MONITOR :: reserved0 [31:08] */
-#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_reserved0_MASK 0xffffff00
-#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_reserved0_SHIFT 8
-
-/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_1_MONITOR :: spare1_sw_init [07:07] */
-#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_spare1_sw_init_MASK 0x00000080
-#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_spare1_sw_init_SHIFT 7
-
-/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_1_MONITOR :: spare0_sw_init [06:06] */
-#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_spare0_sw_init_MASK 0x00000040
-#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_spare0_sw_init_SHIFT 6
-
-/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_1_MONITOR :: dvp_ht1_sw_init [05:05] */
-#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_dvp_ht1_sw_init_MASK 0x00000020
-#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_dvp_ht1_sw_init_SHIFT 5
-
-/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_1_MONITOR :: gphy_sw_init [04:04] */
-#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_gphy_sw_init_MASK 0x00000010
-#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_gphy_sw_init_SHIFT 4
-
-/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_1_MONITOR :: m2mc1_sw_init [03:03] */
-#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_m2mc1_sw_init_MASK 0x00000008
-#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_m2mc1_sw_init_SHIFT 3
-
-/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_1_MONITOR :: v3d_top_sw_init [02:02] */
-#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_v3d_top_sw_init_MASK 0x00000004
-#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_v3d_top_sw_init_SHIFT 2
-
-/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_1_MONITOR :: vice20_sw_init [01:01] */
-#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_vice20_sw_init_MASK 0x00000002
-#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_vice20_sw_init_SHIFT 1
-
-/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_1_MONITOR :: sid_sw_init [00:00] */
-#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_sid_sw_init_MASK 0x00000001
-#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_sid_sw_init_SHIFT 0
-
-/***************************************************************************
- *FINAL_SW_INIT_1_MONITOR - Final software init 1 monitor
- ***************************************************************************/
-/* SUN_TOP_CTRL :: FINAL_SW_INIT_1_MONITOR :: reserved0 [31:08] */
-#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_reserved0_MASK 0xffffff00
-#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_reserved0_SHIFT 8
-
-/* SUN_TOP_CTRL :: FINAL_SW_INIT_1_MONITOR :: spare1_sw_init [07:07] */
-#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_spare1_sw_init_MASK 0x00000080
-#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_spare1_sw_init_SHIFT 7
-
-/* SUN_TOP_CTRL :: FINAL_SW_INIT_1_MONITOR :: spare0_sw_init [06:06] */
-#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_spare0_sw_init_MASK 0x00000040
-#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_spare0_sw_init_SHIFT 6
-
-/* SUN_TOP_CTRL :: FINAL_SW_INIT_1_MONITOR :: dvp_ht1_sw_init [05:05] */
-#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_dvp_ht1_sw_init_MASK 0x00000020
-#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_dvp_ht1_sw_init_SHIFT 5
-
-/* SUN_TOP_CTRL :: FINAL_SW_INIT_1_MONITOR :: gphy_sw_init [04:04] */
-#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_gphy_sw_init_MASK 0x00000010
-#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_gphy_sw_init_SHIFT 4
-
-/* SUN_TOP_CTRL :: FINAL_SW_INIT_1_MONITOR :: m2mc1_sw_init [03:03] */
-#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_m2mc1_sw_init_MASK 0x00000008
-#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_m2mc1_sw_init_SHIFT 3
-
-/* SUN_TOP_CTRL :: FINAL_SW_INIT_1_MONITOR :: v3d_top_sw_init [02:02] */
-#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_v3d_top_sw_init_MASK 0x00000004
-#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_v3d_top_sw_init_SHIFT 2
-
-/* SUN_TOP_CTRL :: FINAL_SW_INIT_1_MONITOR :: vice20_sw_init [01:01] */
-#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_vice20_sw_init_MASK 0x00000002
-#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_vice20_sw_init_SHIFT 1
-
-/* SUN_TOP_CTRL :: FINAL_SW_INIT_1_MONITOR :: sid_sw_init [00:00] */
-#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_sid_sw_init_MASK 0x00000001
-#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_sid_sw_init_SHIFT 0
-
-/***************************************************************************
- *SW_INIT_ONE_SHOT_TRIGGER - Software init one-shot trigger
- ***************************************************************************/
-/* SUN_TOP_CTRL :: SW_INIT_ONE_SHOT_TRIGGER :: reserved0 [31:02] */
-#define BCHP_SUN_TOP_CTRL_SW_INIT_ONE_SHOT_TRIGGER_reserved0_MASK 0xfffffffc
-#define BCHP_SUN_TOP_CTRL_SW_INIT_ONE_SHOT_TRIGGER_reserved0_SHIFT 2
-
-/* SUN_TOP_CTRL :: SW_INIT_ONE_SHOT_TRIGGER :: trigger_one_shot_1 [01:01] */
-#define BCHP_SUN_TOP_CTRL_SW_INIT_ONE_SHOT_TRIGGER_trigger_one_shot_1_MASK 0x00000002
-#define BCHP_SUN_TOP_CTRL_SW_INIT_ONE_SHOT_TRIGGER_trigger_one_shot_1_SHIFT 1
-#define BCHP_SUN_TOP_CTRL_SW_INIT_ONE_SHOT_TRIGGER_trigger_one_shot_1_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: SW_INIT_ONE_SHOT_TRIGGER :: trigger_one_shot_0 [00:00] */
-#define BCHP_SUN_TOP_CTRL_SW_INIT_ONE_SHOT_TRIGGER_trigger_one_shot_0_MASK 0x00000001
-#define BCHP_SUN_TOP_CTRL_SW_INIT_ONE_SHOT_TRIGGER_trigger_one_shot_0_SHIFT 0
-#define BCHP_SUN_TOP_CTRL_SW_INIT_ONE_SHOT_TRIGGER_trigger_one_shot_0_DEFAULT 0x00000000
-
-/***************************************************************************
- *ONE_SHOT_0_SW_INIT_WIDTH - One-shot 0 width
- ***************************************************************************/
-/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_WIDTH :: reserved0 [31:28] */
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_WIDTH_reserved0_MASK 0xf0000000
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_WIDTH_reserved0_SHIFT 28
-
-/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_WIDTH :: one_shot_0_width [27:00] */
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_WIDTH_one_shot_0_width_MASK 0x0fffffff
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_WIDTH_one_shot_0_width_SHIFT 0
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_WIDTH_one_shot_0_width_DEFAULT 0x00000000
-
-/***************************************************************************
- *ONE_SHOT_0_SW_INIT_0_MASK - One-shot 0 mask for software init 0
- ***************************************************************************/
-/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: rfm_sw_init [31:31] */
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_rfm_sw_init_MASK 0x80000000
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_rfm_sw_init_SHIFT 31
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_rfm_sw_init_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: not_used_sw_init_30 [30:30] */
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_30_MASK 0x40000000
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_30_SHIFT 30
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_30_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: sata_sw_init [29:29] */
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_sata_sw_init_MASK 0x20000000
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_sata_sw_init_SHIFT 29
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_sata_sw_init_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: moca_sw_init [28:28] */
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_moca_sw_init_MASK 0x10000000
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_moca_sw_init_SHIFT 28
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_moca_sw_init_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: genet1_sw_init [27:27] */
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_genet1_sw_init_MASK 0x08000000
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_genet1_sw_init_SHIFT 27
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_genet1_sw_init_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: genet0_sw_init [26:26] */
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_genet0_sw_init_MASK 0x04000000
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_genet0_sw_init_SHIFT 26
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_genet0_sw_init_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: usb1_sw_init [25:25] */
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_usb1_sw_init_MASK 0x02000000
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_usb1_sw_init_SHIFT 25
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_usb1_sw_init_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: usb0_sw_init [24:24] */
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_usb0_sw_init_MASK 0x01000000
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_usb0_sw_init_SHIFT 24
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_usb0_sw_init_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: not_used_sw_init_23 [23:23] */
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_23_MASK 0x00800000
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_23_SHIFT 23
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_23_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: not_used_sw_init_22 [22:22] */
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_22_MASK 0x00400000
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_22_SHIFT 22
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_22_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: ddr0_sw_init [21:21] */
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_ddr0_sw_init_MASK 0x00200000
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_ddr0_sw_init_SHIFT 21
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_ddr0_sw_init_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: not_used_sw_init_20 [20:20] */
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_20_MASK 0x00100000
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_20_SHIFT 20
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_20_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: memc0_sw_init [19:19] */
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_memc0_sw_init_MASK 0x00080000
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_memc0_sw_init_SHIFT 19
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_memc0_sw_init_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: xpt_sw_init [18:18] */
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_xpt_sw_init_MASK 0x00040000
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_xpt_sw_init_SHIFT 18
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_xpt_sw_init_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: not_used_sw_init_17 [17:17] */
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_17_MASK 0x00020000
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_17_SHIFT 17
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_17_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: raaga0_sw_init [16:16] */
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_raaga0_sw_init_MASK 0x00010000
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_raaga0_sw_init_SHIFT 16
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_raaga0_sw_init_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: aio_sw_init [15:15] */
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_aio_sw_init_MASK 0x00008000
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_aio_sw_init_SHIFT 15
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_aio_sw_init_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: gfx_sw_init [14:14] */
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_gfx_sw_init_MASK 0x00004000
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_gfx_sw_init_SHIFT 14
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_gfx_sw_init_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: not_used_sw_init_13 [13:13] */
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_13_MASK 0x00002000
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_13_SHIFT 13
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_13_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: hvd0_sw_init [12:12] */
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_hvd0_sw_init_MASK 0x00001000
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_hvd0_sw_init_SHIFT 12
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_hvd0_sw_init_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: dvp_hr_sw_init [11:11] */
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_dvp_hr_sw_init_MASK 0x00000800
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_dvp_hr_sw_init_SHIFT 11
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_dvp_hr_sw_init_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: dvp_ht0_sw_init [10:10] */
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_dvp_ht0_sw_init_MASK 0x00000400
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_dvp_ht0_sw_init_SHIFT 10
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_dvp_ht0_sw_init_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: vec_sw_init [09:09] */
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_vec_sw_init_MASK 0x00000200
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_vec_sw_init_SHIFT 9
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_vec_sw_init_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: bvn_sw_init [08:08] */
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_bvn_sw_init_MASK 0x00000100
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_bvn_sw_init_SHIFT 8
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_bvn_sw_init_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: not_used_sw_init_7 [07:07] */
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_7_MASK 0x00000080
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_7_SHIFT 7
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_7_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: ebi_sw_init [06:06] */
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_ebi_sw_init_MASK 0x00000040
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_ebi_sw_init_SHIFT 6
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_ebi_sw_init_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: pcie0_sw_init [05:05] */
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_pcie0_sw_init_MASK 0x00000020
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_pcie0_sw_init_SHIFT 5
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_pcie0_sw_init_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: webcpu_start_sw_init [04:04] */
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_webcpu_start_sw_init_MASK 0x00000010
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_webcpu_start_sw_init_SHIFT 4
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_webcpu_start_sw_init_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: webcpu_sw_init [03:03] */
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_webcpu_sw_init_MASK 0x00000008
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_webcpu_sw_init_SHIFT 3
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_webcpu_sw_init_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: ext_sys_sw_init [02:02] */
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_ext_sys_sw_init_MASK 0x00000004
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_ext_sys_sw_init_SHIFT 2
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_ext_sys_sw_init_DEFAULT 0x00000001
-
-/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: cpu_sw_init [01:01] */
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_cpu_sw_init_MASK 0x00000002
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_cpu_sw_init_SHIFT 1
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_cpu_sw_init_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: sys_ctrl_sw_init [00:00] */
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_sys_ctrl_sw_init_MASK 0x00000001
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_sys_ctrl_sw_init_SHIFT 0
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_sys_ctrl_sw_init_DEFAULT 0x00000000
-
-/***************************************************************************
- *ONE_SHOT_0_SW_INIT_1_MASK - One-shot 0 mask for software init 1
- ***************************************************************************/
-/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_1_MASK :: reserved0 [31:08] */
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_reserved0_MASK 0xffffff00
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_reserved0_SHIFT 8
-
-/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_1_MASK :: spare1_sw_init [07:07] */
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_spare1_sw_init_MASK 0x00000080
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_spare1_sw_init_SHIFT 7
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_spare1_sw_init_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_1_MASK :: spare0_sw_init [06:06] */
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_spare0_sw_init_MASK 0x00000040
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_spare0_sw_init_SHIFT 6
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_spare0_sw_init_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_1_MASK :: dvp_ht1_sw_init [05:05] */
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_dvp_ht1_sw_init_MASK 0x00000020
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_dvp_ht1_sw_init_SHIFT 5
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_dvp_ht1_sw_init_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_1_MASK :: gphy_sw_init [04:04] */
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_gphy_sw_init_MASK 0x00000010
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_gphy_sw_init_SHIFT 4
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_gphy_sw_init_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_1_MASK :: m2mc1_sw_init [03:03] */
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_m2mc1_sw_init_MASK 0x00000008
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_m2mc1_sw_init_SHIFT 3
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_m2mc1_sw_init_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_1_MASK :: v3d_top_sw_init [02:02] */
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_v3d_top_sw_init_MASK 0x00000004
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_v3d_top_sw_init_SHIFT 2
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_v3d_top_sw_init_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_1_MASK :: vice20_sw_init [01:01] */
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_vice20_sw_init_MASK 0x00000002
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_vice20_sw_init_SHIFT 1
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_vice20_sw_init_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_1_MASK :: sid_sw_init [00:00] */
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_sid_sw_init_MASK 0x00000001
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_sid_sw_init_SHIFT 0
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_sid_sw_init_DEFAULT 0x00000000
-
-/***************************************************************************
- *ONE_SHOT_1_SW_INIT_WIDTH - One-shot 1 width
- ***************************************************************************/
-/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_WIDTH :: reserved0 [31:28] */
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_WIDTH_reserved0_MASK 0xf0000000
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_WIDTH_reserved0_SHIFT 28
-
-/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_WIDTH :: one_shot_1_width [27:00] */
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_WIDTH_one_shot_1_width_MASK 0x0fffffff
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_WIDTH_one_shot_1_width_SHIFT 0
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_WIDTH_one_shot_1_width_DEFAULT 0x00000000
-
-/***************************************************************************
- *ONE_SHOT_1_SW_INIT_0_MASK - One-shot 1 mask for software init 0
- ***************************************************************************/
-/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: rfm_sw_init [31:31] */
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_rfm_sw_init_MASK 0x80000000
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_rfm_sw_init_SHIFT 31
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_rfm_sw_init_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: not_used_sw_init_30 [30:30] */
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_30_MASK 0x40000000
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_30_SHIFT 30
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_30_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: sata_sw_init [29:29] */
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_sata_sw_init_MASK 0x20000000
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_sata_sw_init_SHIFT 29
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_sata_sw_init_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: moca_sw_init [28:28] */
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_moca_sw_init_MASK 0x10000000
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_moca_sw_init_SHIFT 28
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_moca_sw_init_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: genet1_sw_init [27:27] */
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_genet1_sw_init_MASK 0x08000000
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_genet1_sw_init_SHIFT 27
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_genet1_sw_init_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: genet0_sw_init [26:26] */
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_genet0_sw_init_MASK 0x04000000
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_genet0_sw_init_SHIFT 26
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_genet0_sw_init_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: usb1_sw_init [25:25] */
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_usb1_sw_init_MASK 0x02000000
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_usb1_sw_init_SHIFT 25
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_usb1_sw_init_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: usb0_sw_init [24:24] */
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_usb0_sw_init_MASK 0x01000000
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_usb0_sw_init_SHIFT 24
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_usb0_sw_init_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: not_used_sw_init_23 [23:23] */
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_23_MASK 0x00800000
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_23_SHIFT 23
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_23_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: not_used_sw_init_22 [22:22] */
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_22_MASK 0x00400000
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_22_SHIFT 22
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_22_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: ddr0_sw_init [21:21] */
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_ddr0_sw_init_MASK 0x00200000
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_ddr0_sw_init_SHIFT 21
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_ddr0_sw_init_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: not_used_sw_init_20 [20:20] */
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_20_MASK 0x00100000
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_20_SHIFT 20
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_20_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: memc0_sw_init [19:19] */
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_memc0_sw_init_MASK 0x00080000
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_memc0_sw_init_SHIFT 19
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_memc0_sw_init_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: xpt_sw_init [18:18] */
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_xpt_sw_init_MASK 0x00040000
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_xpt_sw_init_SHIFT 18
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_xpt_sw_init_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: not_used_sw_init_17 [17:17] */
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_17_MASK 0x00020000
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_17_SHIFT 17
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_17_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: raaga0_sw_init [16:16] */
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_raaga0_sw_init_MASK 0x00010000
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_raaga0_sw_init_SHIFT 16
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_raaga0_sw_init_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: aio_sw_init [15:15] */
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_aio_sw_init_MASK 0x00008000
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_aio_sw_init_SHIFT 15
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_aio_sw_init_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: gfx_sw_init [14:14] */
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_gfx_sw_init_MASK 0x00004000
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_gfx_sw_init_SHIFT 14
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_gfx_sw_init_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: not_used_sw_init_13 [13:13] */
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_13_MASK 0x00002000
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_13_SHIFT 13
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_13_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: hvd0_sw_init [12:12] */
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_hvd0_sw_init_MASK 0x00001000
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_hvd0_sw_init_SHIFT 12
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_hvd0_sw_init_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: dvp_hr_sw_init [11:11] */
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_dvp_hr_sw_init_MASK 0x00000800
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_dvp_hr_sw_init_SHIFT 11
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_dvp_hr_sw_init_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: dvp_ht0_sw_init [10:10] */
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_dvp_ht0_sw_init_MASK 0x00000400
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_dvp_ht0_sw_init_SHIFT 10
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_dvp_ht0_sw_init_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: vec_sw_init [09:09] */
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_vec_sw_init_MASK 0x00000200
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_vec_sw_init_SHIFT 9
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_vec_sw_init_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: bvn_sw_init [08:08] */
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_bvn_sw_init_MASK 0x00000100
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_bvn_sw_init_SHIFT 8
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_bvn_sw_init_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: not_used_sw_init_7 [07:07] */
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_7_MASK 0x00000080
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_7_SHIFT 7
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_7_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: ebi_sw_init [06:06] */
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_ebi_sw_init_MASK 0x00000040
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_ebi_sw_init_SHIFT 6
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_ebi_sw_init_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: pcie0_sw_init [05:05] */
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_pcie0_sw_init_MASK 0x00000020
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_pcie0_sw_init_SHIFT 5
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_pcie0_sw_init_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: webcpu_start_sw_init [04:04] */
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_webcpu_start_sw_init_MASK 0x00000010
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_webcpu_start_sw_init_SHIFT 4
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_webcpu_start_sw_init_DEFAULT 0x00000001
-
-/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: webcpu_sw_init [03:03] */
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_webcpu_sw_init_MASK 0x00000008
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_webcpu_sw_init_SHIFT 3
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_webcpu_sw_init_DEFAULT 0x00000001
-
-/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: ext_sys_sw_init [02:02] */
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_ext_sys_sw_init_MASK 0x00000004
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_ext_sys_sw_init_SHIFT 2
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_ext_sys_sw_init_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: cpu_sw_init [01:01] */
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_cpu_sw_init_MASK 0x00000002
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_cpu_sw_init_SHIFT 1
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_cpu_sw_init_DEFAULT 0x00000001
-
-/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: sys_ctrl_sw_init [00:00] */
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_sys_ctrl_sw_init_MASK 0x00000001
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_sys_ctrl_sw_init_SHIFT 0
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_sys_ctrl_sw_init_DEFAULT 0x00000000
-
-/***************************************************************************
- *ONE_SHOT_1_SW_INIT_1_MASK - One-shot 1 mask for software init 1
- ***************************************************************************/
-/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_1_MASK :: reserved0 [31:08] */
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_reserved0_MASK 0xffffff00
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_reserved0_SHIFT 8
-
-/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_1_MASK :: spare1_sw_init [07:07] */
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_spare1_sw_init_MASK 0x00000080
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_spare1_sw_init_SHIFT 7
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_spare1_sw_init_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_1_MASK :: spare0_sw_init [06:06] */
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_spare0_sw_init_MASK 0x00000040
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_spare0_sw_init_SHIFT 6
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_spare0_sw_init_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_1_MASK :: dvp_ht1_sw_init [05:05] */
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_dvp_ht1_sw_init_MASK 0x00000020
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_dvp_ht1_sw_init_SHIFT 5
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_dvp_ht1_sw_init_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_1_MASK :: gphy_sw_init [04:04] */
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_gphy_sw_init_MASK 0x00000010
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_gphy_sw_init_SHIFT 4
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_gphy_sw_init_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_1_MASK :: m2mc1_sw_init [03:03] */
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_m2mc1_sw_init_MASK 0x00000008
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_m2mc1_sw_init_SHIFT 3
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_m2mc1_sw_init_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_1_MASK :: v3d_top_sw_init [02:02] */
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_v3d_top_sw_init_MASK 0x00000004
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_v3d_top_sw_init_SHIFT 2
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_v3d_top_sw_init_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_1_MASK :: vice20_sw_init [01:01] */
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_vice20_sw_init_MASK 0x00000002
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_vice20_sw_init_SHIFT 1
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_vice20_sw_init_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_1_MASK :: sid_sw_init [00:00] */
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_sid_sw_init_MASK 0x00000001
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_sid_sw_init_SHIFT 0
-#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_sid_sw_init_DEFAULT 0x00000000
-
-/***************************************************************************
- *UNCLEARED_SCRATCH - Scratch register
- ***************************************************************************/
-/* SUN_TOP_CTRL :: UNCLEARED_SCRATCH :: uncleared_scratch [31:00] */
-#define BCHP_SUN_TOP_CTRL_UNCLEARED_SCRATCH_uncleared_scratch_MASK 0xffffffff
-#define BCHP_SUN_TOP_CTRL_UNCLEARED_SCRATCH_uncleared_scratch_SHIFT 0
-#define BCHP_SUN_TOP_CTRL_UNCLEARED_SCRATCH_uncleared_scratch_DEFAULT 0x00000000
-
-/***************************************************************************
- *SPARE_CTRL - Spare control bits reserved for future use
- ***************************************************************************/
-/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_31 [31:31] */
-#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_31_MASK 0x80000000
-#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_31_SHIFT 31
-#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_31_DEFAULT 0x00000001
-
-/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_30 [30:30] */
-#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_30_MASK 0x40000000
-#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_30_SHIFT 30
-#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_30_DEFAULT 0x00000001
-
-/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_29 [29:29] */
-#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_29_MASK 0x20000000
-#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_29_SHIFT 29
-#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_29_DEFAULT 0x00000001
-
-/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_28 [28:28] */
-#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_28_MASK 0x10000000
-#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_28_SHIFT 28
-#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_28_DEFAULT 0x00000001
-
-/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_27 [27:27] */
-#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_27_MASK 0x08000000
-#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_27_SHIFT 27
-#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_27_DEFAULT 0x00000001
-
-/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_26 [26:26] */
-#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_26_MASK 0x04000000
-#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_26_SHIFT 26
-#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_26_DEFAULT 0x00000001
-
-/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_25 [25:25] */
-#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_25_MASK 0x02000000
-#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_25_SHIFT 25
-#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_25_DEFAULT 0x00000001
-
-/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_24 [24:24] */
-#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_24_MASK 0x01000000
-#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_24_SHIFT 24
-#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_24_DEFAULT 0x00000001
-
-/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_23 [23:23] */
-#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_23_MASK 0x00800000
-#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_23_SHIFT 23
-#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_23_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_22 [22:22] */
-#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_22_MASK 0x00400000
-#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_22_SHIFT 22
-#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_22_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_21 [21:21] */
-#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_21_MASK 0x00200000
-#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_21_SHIFT 21
-#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_21_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_20 [20:20] */
-#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_20_MASK 0x00100000
-#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_20_SHIFT 20
-#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_20_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_19 [19:19] */
-#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_19_MASK 0x00080000
-#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_19_SHIFT 19
-#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_19_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_18 [18:18] */
-#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_18_MASK 0x00040000
-#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_18_SHIFT 18
-#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_18_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_17 [17:17] */
-#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_17_MASK 0x00020000
-#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_17_SHIFT 17
-#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_17_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_16 [16:16] */
-#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_16_MASK 0x00010000
-#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_16_SHIFT 16
-#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_16_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_15 [15:15] */
-#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_15_MASK 0x00008000
-#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_15_SHIFT 15
-#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_15_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_14 [14:14] */
-#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_14_MASK 0x00004000
-#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_14_SHIFT 14
-#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_14_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_13 [13:13] */
-#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_13_MASK 0x00002000
-#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_13_SHIFT 13
-#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_13_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_12 [12:12] */
-#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_12_MASK 0x00001000
-#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_12_SHIFT 12
-#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_12_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_11 [11:11] */
-#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_11_MASK 0x00000800
-#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_11_SHIFT 11
-#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_11_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_10 [10:10] */
-#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_10_MASK 0x00000400
-#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_10_SHIFT 10
-#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_10_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_09 [09:09] */
-#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_09_MASK 0x00000200
-#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_09_SHIFT 9
-#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_09_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_08 [08:08] */
-#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_08_MASK 0x00000100
-#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_08_SHIFT 8
-#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_08_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_07 [07:07] */
-#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_07_MASK 0x00000080
-#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_07_SHIFT 7
-#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_07_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_06 [06:06] */
-#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_06_MASK 0x00000040
-#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_06_SHIFT 6
-#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_06_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_05 [05:05] */
-#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_05_MASK 0x00000020
-#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_05_SHIFT 5
-#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_05_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_04 [04:04] */
-#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_04_MASK 0x00000010
-#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_04_SHIFT 4
-#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_04_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_03 [03:03] */
-#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_03_MASK 0x00000008
-#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_03_SHIFT 3
-#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_03_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_02 [02:02] */
-#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_02_MASK 0x00000004
-#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_02_SHIFT 2
-#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_02_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_01 [01:01] */
-#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_01_MASK 0x00000002
-#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_01_SHIFT 1
-#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_01_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_00 [00:00] */
-#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_00_MASK 0x00000001
-#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_00_SHIFT 0
-#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_00_DEFAULT 0x00000000
-
-/***************************************************************************
- *TEST_PORT_CTRL - Test port control
- ***************************************************************************/
-/* SUN_TOP_CTRL :: TEST_PORT_CTRL :: sys_ctrl_local_tp_out_sel [31:28] */
-#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sys_ctrl_local_tp_out_sel_MASK 0xf0000000
-#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sys_ctrl_local_tp_out_sel_SHIFT 28
-#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sys_ctrl_local_tp_out_sel_DEFAULT 0x00000000
-#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sys_ctrl_local_tp_out_sel_SEMAPHORE_0 0
-#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sys_ctrl_local_tp_out_sel_SEMAPHORE_1 1
-#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sys_ctrl_local_tp_out_sel_UNUSED_02 2
-#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sys_ctrl_local_tp_out_sel_MISC_TEST 3
-#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sys_ctrl_local_tp_out_sel_SSP 4
-#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sys_ctrl_local_tp_out_sel_TP_OUT_POKE_REG 5
-#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sys_ctrl_local_tp_out_sel_TP_IN 6
-#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sys_ctrl_local_tp_out_sel_UNUSED_07 7
-#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sys_ctrl_local_tp_out_sel_UNUSED_08 8
-#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sys_ctrl_local_tp_out_sel_UNUSED_09 9
-#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sys_ctrl_local_tp_out_sel_UNUSED_10 10
-#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sys_ctrl_local_tp_out_sel_UNUSED_11 11
-#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sys_ctrl_local_tp_out_sel_UPG_TP_OUT 12
-#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sys_ctrl_local_tp_out_sel_AVS_TP_OUT 13
-#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sys_ctrl_local_tp_out_sel_ICID_TP_OUT 14
-#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sys_ctrl_local_tp_out_sel_TOP_AUX_TP_OUT 15
-
-/* SUN_TOP_CTRL :: TEST_PORT_CTRL :: reserved0 [27:10] */
-#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_reserved0_MASK 0x0ffffc00
-#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_reserved0_SHIFT 10
-
-/* SUN_TOP_CTRL :: TEST_PORT_CTRL :: tp_in_source_select [09:09] */
-#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_tp_in_source_select_MASK 0x00000200
-#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_tp_in_source_select_SHIFT 9
-#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_tp_in_source_select_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: TEST_PORT_CTRL :: tp_select [08:07] */
-#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_tp_select_MASK 0x00000180
-#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_tp_select_SHIFT 7
-#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_tp_select_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: TEST_PORT_CTRL :: encoded_tp_enable [06:00] */
-#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_MASK 0x0000007f
-#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_SHIFT 0
-#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_DEFAULT 0x0000007f
-#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_GENET0 0
-#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_SATA 1
-#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_SCPU 2
-#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_CPU 3
-#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_SYS 16
-#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_CLK 17
-#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_AON 18
-#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_HIF 20
-#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_BSP 21
-#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_VEC 25
-#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_HVD0 27
-#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_AIO 30
-#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_RAAGA0 31
-#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_XPT 33
-#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_MEMC0 35
-#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_GENET1 42
-#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_PCIE 44
-#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_USB0 45
-#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_USB1 46
-#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_MOCA 47
-#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_RFM 49
-#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_V3D_TOP 54
-
-/***************************************************************************
- *TEST_PORT_OUT_PEEK - Testport peek register
- ***************************************************************************/
-/* SUN_TOP_CTRL :: TEST_PORT_OUT_PEEK :: test_port_out_peek_value [31:00] */
-#define BCHP_SUN_TOP_CTRL_TEST_PORT_OUT_PEEK_test_port_out_peek_value_MASK 0xffffffff
-#define BCHP_SUN_TOP_CTRL_TEST_PORT_OUT_PEEK_test_port_out_peek_value_SHIFT 0
-
-/***************************************************************************
- *TEST_PORT_OUT_POKE - Testport poke register
- ***************************************************************************/
-/* SUN_TOP_CTRL :: TEST_PORT_OUT_POKE :: test_port_out_poke_value [31:00] */
-#define BCHP_SUN_TOP_CTRL_TEST_PORT_OUT_POKE_test_port_out_poke_value_MASK 0xffffffff
-#define BCHP_SUN_TOP_CTRL_TEST_PORT_OUT_POKE_test_port_out_poke_value_SHIFT 0
-#define BCHP_SUN_TOP_CTRL_TEST_PORT_OUT_POKE_test_port_out_poke_value_DEFAULT 0x00000000
-
-/***************************************************************************
- *TEST_PORT_IN_PEEK - Testport peek register
- ***************************************************************************/
-/* SUN_TOP_CTRL :: TEST_PORT_IN_PEEK :: test_port_in_peek_value [31:00] */
-#define BCHP_SUN_TOP_CTRL_TEST_PORT_IN_PEEK_test_port_in_peek_value_MASK 0xffffffff
-#define BCHP_SUN_TOP_CTRL_TEST_PORT_IN_PEEK_test_port_in_peek_value_SHIFT 0
-
-/***************************************************************************
- *TEST_PORT_IN_POKE - Testport poke register
- ***************************************************************************/
-/* SUN_TOP_CTRL :: TEST_PORT_IN_POKE :: test_port_in_poke_value [31:00] */
-#define BCHP_SUN_TOP_CTRL_TEST_PORT_IN_POKE_test_port_in_poke_value_MASK 0xffffffff
-#define BCHP_SUN_TOP_CTRL_TEST_PORT_IN_POKE_test_port_in_poke_value_SHIFT 0
-#define BCHP_SUN_TOP_CTRL_TEST_PORT_IN_POKE_test_port_in_poke_value_DEFAULT 0x00000000
-
-/***************************************************************************
- *EJTAG_INPUT_EN - EJTAG input bus enables
- ***************************************************************************/
-/* SUN_TOP_CTRL :: EJTAG_INPUT_EN :: reserved0 [31:11] */
-#define BCHP_SUN_TOP_CTRL_EJTAG_INPUT_EN_reserved0_MASK 0xfffff800
-#define BCHP_SUN_TOP_CTRL_EJTAG_INPUT_EN_reserved0_SHIFT 11
-
-/* SUN_TOP_CTRL :: EJTAG_INPUT_EN :: reserved_for_padding1 [10:09] */
-#define BCHP_SUN_TOP_CTRL_EJTAG_INPUT_EN_reserved_for_padding1_MASK 0x00000600
-#define BCHP_SUN_TOP_CTRL_EJTAG_INPUT_EN_reserved_for_padding1_SHIFT 9
-
-/* SUN_TOP_CTRL :: EJTAG_INPUT_EN :: ejtag_input_enable [08:00] */
-#define BCHP_SUN_TOP_CTRL_EJTAG_INPUT_EN_ejtag_input_enable_MASK 0x000001ff
-#define BCHP_SUN_TOP_CTRL_EJTAG_INPUT_EN_ejtag_input_enable_SHIFT 0
-#define BCHP_SUN_TOP_CTRL_EJTAG_INPUT_EN_ejtag_input_enable_DEFAULT 0x00000002
-#define BCHP_SUN_TOP_CTRL_EJTAG_INPUT_EN_ejtag_input_enable_DO_NOT_USE_CPU_ONE_HOT 1
-#define BCHP_SUN_TOP_CTRL_EJTAG_INPUT_EN_ejtag_input_enable_MAIN_CPU_ONE_HOT 2
-#define BCHP_SUN_TOP_CTRL_EJTAG_INPUT_EN_ejtag_input_enable_MOCA0_CPU_ONE_HOT 4
-#define BCHP_SUN_TOP_CTRL_EJTAG_INPUT_EN_ejtag_input_enable_MOCA1_CPU_ONE_HOT 8
-#define BCHP_SUN_TOP_CTRL_EJTAG_INPUT_EN_ejtag_input_enable_VICE20_ARC0_CPU_ONE_HOT 16
-#define BCHP_SUN_TOP_CTRL_EJTAG_INPUT_EN_ejtag_input_enable_VICE20_ARC1_CPU_ONE_HOT 32
-#define BCHP_SUN_TOP_CTRL_EJTAG_INPUT_EN_ejtag_input_enable_AVS_CPU_ONE_HOT 64
-#define BCHP_SUN_TOP_CTRL_EJTAG_INPUT_EN_ejtag_input_enable_SCPU_CPU_ONE_HOT 128
-#define BCHP_SUN_TOP_CTRL_EJTAG_INPUT_EN_ejtag_input_enable_BSP_CPU_ONE_HOT 256
-
-/***************************************************************************
- *EJTAG_OUTPUT_SEL - EJTAG output select
- ***************************************************************************/
-/* SUN_TOP_CTRL :: EJTAG_OUTPUT_SEL :: reserved0 [31:04] */
-#define BCHP_SUN_TOP_CTRL_EJTAG_OUTPUT_SEL_reserved0_MASK 0xfffffff0
-#define BCHP_SUN_TOP_CTRL_EJTAG_OUTPUT_SEL_reserved0_SHIFT 4
-
-/* SUN_TOP_CTRL :: EJTAG_OUTPUT_SEL :: ejtag_output_sel [03:00] */
-#define BCHP_SUN_TOP_CTRL_EJTAG_OUTPUT_SEL_ejtag_output_sel_MASK 0x0000000f
-#define BCHP_SUN_TOP_CTRL_EJTAG_OUTPUT_SEL_ejtag_output_sel_SHIFT 0
-#define BCHP_SUN_TOP_CTRL_EJTAG_OUTPUT_SEL_ejtag_output_sel_DEFAULT 0x00000001
-#define BCHP_SUN_TOP_CTRL_EJTAG_OUTPUT_SEL_ejtag_output_sel_DO_NOT_USE_CPU 0
-#define BCHP_SUN_TOP_CTRL_EJTAG_OUTPUT_SEL_ejtag_output_sel_MAIN_CPU 1
-#define BCHP_SUN_TOP_CTRL_EJTAG_OUTPUT_SEL_ejtag_output_sel_MOCA0_CPU 2
-#define BCHP_SUN_TOP_CTRL_EJTAG_OUTPUT_SEL_ejtag_output_sel_MOCA1_CPU 3
-#define BCHP_SUN_TOP_CTRL_EJTAG_OUTPUT_SEL_ejtag_output_sel_VICE20_ARC0_CPU 4
-#define BCHP_SUN_TOP_CTRL_EJTAG_OUTPUT_SEL_ejtag_output_sel_VICE20_ARC1_CPU 5
-#define BCHP_SUN_TOP_CTRL_EJTAG_OUTPUT_SEL_ejtag_output_sel_AVS_CPU 6
-#define BCHP_SUN_TOP_CTRL_EJTAG_OUTPUT_SEL_ejtag_output_sel_SCPU_CPU 7
-#define BCHP_SUN_TOP_CTRL_EJTAG_OUTPUT_SEL_ejtag_output_sel_BSP_CPU 8
-
-/***************************************************************************
- *VTRAP_CTRL - VTRAP Control
- ***************************************************************************/
-/* SUN_TOP_CTRL :: VTRAP_CTRL :: reserved0 [31:23] */
-#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_reserved0_MASK 0xff800000
-#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_reserved0_SHIFT 23
-
-/* SUN_TOP_CTRL :: VTRAP_CTRL :: vtrap_enable_max_1_threshold [22:22] */
-#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_enable_max_1_threshold_MASK 0x00400000
-#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_enable_max_1_threshold_SHIFT 22
-#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_enable_max_1_threshold_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: VTRAP_CTRL :: vtrap_enable_min_1_threshold [21:21] */
-#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_enable_min_1_threshold_MASK 0x00200000
-#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_enable_min_1_threshold_SHIFT 21
-#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_enable_min_1_threshold_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: VTRAP_CTRL :: vtrap_enable_min_0_threshold [20:20] */
-#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_enable_min_0_threshold_MASK 0x00100000
-#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_enable_min_0_threshold_SHIFT 20
-#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_enable_min_0_threshold_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: VTRAP_CTRL :: vtrap_enable_warning_1_threshold [19:19] */
-#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_enable_warning_1_threshold_MASK 0x00080000
-#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_enable_warning_1_threshold_SHIFT 19
-#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_enable_warning_1_threshold_DEFAULT 0x00000001
-
-/* SUN_TOP_CTRL :: VTRAP_CTRL :: vtrap_enable_warning_0_threshold [18:18] */
-#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_enable_warning_0_threshold_MASK 0x00040000
-#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_enable_warning_0_threshold_SHIFT 18
-#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_enable_warning_0_threshold_DEFAULT 0x00000001
-
-/* SUN_TOP_CTRL :: VTRAP_CTRL :: vtrap_vddcmon_test_trim_code [17:05] */
-#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_vddcmon_test_trim_code_MASK 0x0003ffe0
-#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_vddcmon_test_trim_code_SHIFT 5
-#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_vddcmon_test_trim_code_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: VTRAP_CTRL :: vtrap_threshold_warning_1_status_clear [04:04] */
-#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_threshold_warning_1_status_clear_MASK 0x00000010
-#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_threshold_warning_1_status_clear_SHIFT 4
-#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_threshold_warning_1_status_clear_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: VTRAP_CTRL :: vtrap_threshold_warning_0_status_clear [03:03] */
-#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_threshold_warning_0_status_clear_MASK 0x00000008
-#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_threshold_warning_0_status_clear_SHIFT 3
-#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_threshold_warning_0_status_clear_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: VTRAP_CTRL :: vtrap_threshold_min_1_status_clear [02:02] */
-#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_threshold_min_1_status_clear_MASK 0x00000004
-#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_threshold_min_1_status_clear_SHIFT 2
-#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_threshold_min_1_status_clear_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: VTRAP_CTRL :: vtrap_threshold_min_0_status_clear [01:01] */
-#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_threshold_min_0_status_clear_MASK 0x00000002
-#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_threshold_min_0_status_clear_SHIFT 1
-#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_threshold_min_0_status_clear_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: VTRAP_CTRL :: vtrap_threshold_max_1_status_clear [00:00] */
-#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_threshold_max_1_status_clear_MASK 0x00000001
-#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_threshold_max_1_status_clear_SHIFT 0
-#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_threshold_max_1_status_clear_DEFAULT 0x00000000
-
-/***************************************************************************
- *VTRAP_STATUS - VTRAP Status
- ***************************************************************************/
-/* SUN_TOP_CTRL :: VTRAP_STATUS :: reserved0 [31:05] */
-#define BCHP_SUN_TOP_CTRL_VTRAP_STATUS_reserved0_MASK 0xffffffe0
-#define BCHP_SUN_TOP_CTRL_VTRAP_STATUS_reserved0_SHIFT 5
-
-/* SUN_TOP_CTRL :: VTRAP_STATUS :: vtrap_threshold_warning_1_status [04:04] */
-#define BCHP_SUN_TOP_CTRL_VTRAP_STATUS_vtrap_threshold_warning_1_status_MASK 0x00000010
-#define BCHP_SUN_TOP_CTRL_VTRAP_STATUS_vtrap_threshold_warning_1_status_SHIFT 4
-#define BCHP_SUN_TOP_CTRL_VTRAP_STATUS_vtrap_threshold_warning_1_status_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: VTRAP_STATUS :: vtrap_threshold_warning_0_status [03:03] */
-#define BCHP_SUN_TOP_CTRL_VTRAP_STATUS_vtrap_threshold_warning_0_status_MASK 0x00000008
-#define BCHP_SUN_TOP_CTRL_VTRAP_STATUS_vtrap_threshold_warning_0_status_SHIFT 3
-#define BCHP_SUN_TOP_CTRL_VTRAP_STATUS_vtrap_threshold_warning_0_status_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: VTRAP_STATUS :: vtrap_threshold_min_1_status [02:02] */
-#define BCHP_SUN_TOP_CTRL_VTRAP_STATUS_vtrap_threshold_min_1_status_MASK 0x00000004
-#define BCHP_SUN_TOP_CTRL_VTRAP_STATUS_vtrap_threshold_min_1_status_SHIFT 2
-#define BCHP_SUN_TOP_CTRL_VTRAP_STATUS_vtrap_threshold_min_1_status_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: VTRAP_STATUS :: vtrap_threshold_min_0_status [01:01] */
-#define BCHP_SUN_TOP_CTRL_VTRAP_STATUS_vtrap_threshold_min_0_status_MASK 0x00000002
-#define BCHP_SUN_TOP_CTRL_VTRAP_STATUS_vtrap_threshold_min_0_status_SHIFT 1
-#define BCHP_SUN_TOP_CTRL_VTRAP_STATUS_vtrap_threshold_min_0_status_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: VTRAP_STATUS :: vtrap_threshold_max_1_status [00:00] */
-#define BCHP_SUN_TOP_CTRL_VTRAP_STATUS_vtrap_threshold_max_1_status_MASK 0x00000001
-#define BCHP_SUN_TOP_CTRL_VTRAP_STATUS_vtrap_threshold_max_1_status_SHIFT 0
-#define BCHP_SUN_TOP_CTRL_VTRAP_STATUS_vtrap_threshold_max_1_status_DEFAULT 0x00000000
-
-/***************************************************************************
- *UART_ROUTER_SEL_0 - UART Router select 0
- ***************************************************************************/
-/* SUN_TOP_CTRL :: UART_ROUTER_SEL_0 :: reserved0 [31:30] */
-#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_reserved0_MASK 0xc0000000
-#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_reserved0_SHIFT 30
-
-/* SUN_TOP_CTRL :: UART_ROUTER_SEL_0 :: port_5_cpu_sel [29:25] */
-#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_5_cpu_sel_MASK 0x3e000000
-#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_5_cpu_sel_SHIFT 25
-#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_5_cpu_sel_DEFAULT 0x00000000
-#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_5_cpu_sel_NO_CPU 0
-#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_5_cpu_sel_AUDIO_FP0 1
-#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_5_cpu_sel_HVD0_OL 2
-#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_5_cpu_sel_HVD0_IL 3
-#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_5_cpu_sel_SID 4
-#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_5_cpu_sel_VICE20_ARC0 5
-#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_5_cpu_sel_VICE20_ARC1 6
-#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_5_cpu_sel_AVS_TOP 7
-#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_5_cpu_sel_SCPU 8
-
-/* SUN_TOP_CTRL :: UART_ROUTER_SEL_0 :: port_4_cpu_sel [24:20] */
-#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_4_cpu_sel_MASK 0x01f00000
-#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_4_cpu_sel_SHIFT 20
-#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_4_cpu_sel_DEFAULT 0x00000000
-#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_4_cpu_sel_NO_CPU 0
-#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_4_cpu_sel_AUDIO_FP0 1
-#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_4_cpu_sel_HVD0_OL 2
-#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_4_cpu_sel_HVD0_IL 3
-#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_4_cpu_sel_SID 4
-#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_4_cpu_sel_VICE20_ARC0 5
-#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_4_cpu_sel_VICE20_ARC1 6
-#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_4_cpu_sel_AVS_TOP 7
-#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_4_cpu_sel_SCPU 8
-
-/* SUN_TOP_CTRL :: UART_ROUTER_SEL_0 :: port_3_cpu_sel [19:15] */
-#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_3_cpu_sel_MASK 0x000f8000
-#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_3_cpu_sel_SHIFT 15
-#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_3_cpu_sel_DEFAULT 0x00000000
-#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_3_cpu_sel_NO_CPU 0
-#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_3_cpu_sel_AUDIO_FP0 1
-#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_3_cpu_sel_HVD0_OL 2
-#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_3_cpu_sel_HVD0_IL 3
-#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_3_cpu_sel_SID 4
-#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_3_cpu_sel_VICE20_ARC0 5
-#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_3_cpu_sel_VICE20_ARC1 6
-#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_3_cpu_sel_AVS_TOP 7
-#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_3_cpu_sel_SCPU 8
-
-/* SUN_TOP_CTRL :: UART_ROUTER_SEL_0 :: port_2_cpu_sel [14:10] */
-#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_2_cpu_sel_MASK 0x00007c00
-#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_2_cpu_sel_SHIFT 10
-#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_2_cpu_sel_DEFAULT 0x00000000
-#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_2_cpu_sel_NO_CPU 0
-#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_2_cpu_sel_AUDIO_FP0 1
-#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_2_cpu_sel_HVD0_OL 2
-#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_2_cpu_sel_HVD0_IL 3
-#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_2_cpu_sel_SID 4
-#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_2_cpu_sel_VICE20_ARC0 5
-#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_2_cpu_sel_VICE20_ARC1 6
-#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_2_cpu_sel_AVS_TOP 7
-#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_2_cpu_sel_SCPU 8
-
-/* SUN_TOP_CTRL :: UART_ROUTER_SEL_0 :: port_1_cpu_sel [09:05] */
-#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_1_cpu_sel_MASK 0x000003e0
-#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_1_cpu_sel_SHIFT 5
-#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_1_cpu_sel_DEFAULT 0x00000000
-#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_1_cpu_sel_NO_CPU 0
-#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_1_cpu_sel_AUDIO_FP0 1
-#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_1_cpu_sel_HVD0_OL 2
-#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_1_cpu_sel_HVD0_IL 3
-#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_1_cpu_sel_SID 4
-#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_1_cpu_sel_VICE20_ARC0 5
-#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_1_cpu_sel_VICE20_ARC1 6
-#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_1_cpu_sel_AVS_TOP 7
-#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_1_cpu_sel_SCPU 8
-
-/* SUN_TOP_CTRL :: UART_ROUTER_SEL_0 :: port_0_cpu_sel [04:00] */
-#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_0_cpu_sel_MASK 0x0000001f
-#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_0_cpu_sel_SHIFT 0
-#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_0_cpu_sel_DEFAULT 0x00000000
-#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_0_cpu_sel_NO_CPU 0
-#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_0_cpu_sel_AUDIO_FP0 1
-#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_0_cpu_sel_HVD0_OL 2
-#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_0_cpu_sel_HVD0_IL 3
-#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_0_cpu_sel_SID 4
-#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_0_cpu_sel_VICE20_ARC0 5
-#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_0_cpu_sel_VICE20_ARC1 6
-#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_0_cpu_sel_AVS_TOP 7
-#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_0_cpu_sel_SCPU 8
-
-/***************************************************************************
- *UART_ROUTER_SEL_1 - UART Router select 1
- ***************************************************************************/
-/* SUN_TOP_CTRL :: UART_ROUTER_SEL_1 :: reserved0 [31:30] */
-#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_reserved0_MASK 0xc0000000
-#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_reserved0_SHIFT 30
-
-/* SUN_TOP_CTRL :: UART_ROUTER_SEL_1 :: port_11_cpu_sel [29:25] */
-#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_11_cpu_sel_MASK 0x3e000000
-#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_11_cpu_sel_SHIFT 25
-#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_11_cpu_sel_DEFAULT 0x00000000
-#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_11_cpu_sel_NO_CPU 0
-#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_11_cpu_sel_AUDIO_FP0 1
-#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_11_cpu_sel_HVD0_OL 2
-#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_11_cpu_sel_HVD0_IL 3
-#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_11_cpu_sel_SID 4
-#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_11_cpu_sel_VICE20_ARC0 5
-#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_11_cpu_sel_VICE20_ARC1 6
-#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_11_cpu_sel_AVS_TOP 7
-#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_11_cpu_sel_SCPU 8
-
-/* SUN_TOP_CTRL :: UART_ROUTER_SEL_1 :: port_10_cpu_sel [24:20] */
-#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_10_cpu_sel_MASK 0x01f00000
-#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_10_cpu_sel_SHIFT 20
-#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_10_cpu_sel_DEFAULT 0x00000000
-#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_10_cpu_sel_NO_CPU 0
-#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_10_cpu_sel_AUDIO_FP0 1
-#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_10_cpu_sel_HVD0_OL 2
-#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_10_cpu_sel_HVD0_IL 3
-#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_10_cpu_sel_SID 4
-#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_10_cpu_sel_VICE20_ARC0 5
-#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_10_cpu_sel_VICE20_ARC1 6
-#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_10_cpu_sel_AVS_TOP 7
-#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_10_cpu_sel_SCPU 8
-
-/* SUN_TOP_CTRL :: UART_ROUTER_SEL_1 :: port_9_cpu_sel [19:15] */
-#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_9_cpu_sel_MASK 0x000f8000
-#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_9_cpu_sel_SHIFT 15
-#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_9_cpu_sel_DEFAULT 0x00000000
-#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_9_cpu_sel_NO_CPU 0
-#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_9_cpu_sel_AUDIO_FP0 1
-#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_9_cpu_sel_HVD0_OL 2
-#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_9_cpu_sel_HVD0_IL 3
-#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_9_cpu_sel_SID 4
-#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_9_cpu_sel_VICE20_ARC0 5
-#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_9_cpu_sel_VICE20_ARC1 6
-#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_9_cpu_sel_AVS_TOP 7
-#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_9_cpu_sel_SCPU 8
-
-/* SUN_TOP_CTRL :: UART_ROUTER_SEL_1 :: port_8_cpu_sel [14:10] */
-#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_8_cpu_sel_MASK 0x00007c00
-#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_8_cpu_sel_SHIFT 10
-#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_8_cpu_sel_DEFAULT 0x00000000
-#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_8_cpu_sel_NO_CPU 0
-#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_8_cpu_sel_AUDIO_FP0 1
-#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_8_cpu_sel_HVD0_OL 2
-#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_8_cpu_sel_HVD0_IL 3
-#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_8_cpu_sel_SID 4
-#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_8_cpu_sel_VICE20_ARC0 5
-#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_8_cpu_sel_VICE20_ARC1 6
-#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_8_cpu_sel_AVS_TOP 7
-#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_8_cpu_sel_SCPU 8
-
-/* SUN_TOP_CTRL :: UART_ROUTER_SEL_1 :: port_7_cpu_sel [09:05] */
-#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_7_cpu_sel_MASK 0x000003e0
-#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_7_cpu_sel_SHIFT 5
-#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_7_cpu_sel_DEFAULT 0x00000000
-#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_7_cpu_sel_NO_CPU 0
-#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_7_cpu_sel_AUDIO_FP0 1
-#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_7_cpu_sel_HVD0_OL 2
-#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_7_cpu_sel_HVD0_IL 3
-#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_7_cpu_sel_SID 4
-#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_7_cpu_sel_VICE20_ARC0 5
-#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_7_cpu_sel_VICE20_ARC1 6
-#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_7_cpu_sel_AVS_TOP 7
-#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_7_cpu_sel_SCPU 8
-
-/* SUN_TOP_CTRL :: UART_ROUTER_SEL_1 :: port_6_cpu_sel [04:00] */
-#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_6_cpu_sel_MASK 0x0000001f
-#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_6_cpu_sel_SHIFT 0
-#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_6_cpu_sel_DEFAULT 0x00000000
-#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_6_cpu_sel_NO_CPU 0
-#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_6_cpu_sel_AUDIO_FP0 1
-#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_6_cpu_sel_HVD0_OL 2
-#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_6_cpu_sel_HVD0_IL 3
-#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_6_cpu_sel_SID 4
-#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_6_cpu_sel_VICE20_ARC0 5
-#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_6_cpu_sel_VICE20_ARC1 6
-#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_6_cpu_sel_AVS_TOP 7
-#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_6_cpu_sel_SCPU 8
-
-/***************************************************************************
- *SSP_CONFIG - Serial Slave Port configuration register
- ***************************************************************************/
-/* SUN_TOP_CTRL :: SSP_CONFIG :: reserved0 [31:11] */
-#define BCHP_SUN_TOP_CTRL_SSP_CONFIG_reserved0_MASK 0xfffff800
-#define BCHP_SUN_TOP_CTRL_SSP_CONFIG_reserved0_SHIFT 11
-
-/* SUN_TOP_CTRL :: SSP_CONFIG :: serial_adr_cfg [10:07] */
-#define BCHP_SUN_TOP_CTRL_SSP_CONFIG_serial_adr_cfg_MASK 0x00000780
-#define BCHP_SUN_TOP_CTRL_SSP_CONFIG_serial_adr_cfg_SHIFT 7
-#define BCHP_SUN_TOP_CTRL_SSP_CONFIG_serial_adr_cfg_DEFAULT 0x00000004
-
-/* SUN_TOP_CTRL :: SSP_CONFIG :: probe_mux_sel [06:03] */
-#define BCHP_SUN_TOP_CTRL_SSP_CONFIG_probe_mux_sel_MASK 0x00000078
-#define BCHP_SUN_TOP_CTRL_SSP_CONFIG_probe_mux_sel_SHIFT 3
-#define BCHP_SUN_TOP_CTRL_SSP_CONFIG_probe_mux_sel_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: SSP_CONFIG :: dly_disable [02:02] */
-#define BCHP_SUN_TOP_CTRL_SSP_CONFIG_dly_disable_MASK 0x00000004
-#define BCHP_SUN_TOP_CTRL_SSP_CONFIG_dly_disable_SHIFT 2
-#define BCHP_SUN_TOP_CTRL_SSP_CONFIG_dly_disable_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: SSP_CONFIG :: spi_mode [01:01] */
-#define BCHP_SUN_TOP_CTRL_SSP_CONFIG_spi_mode_MASK 0x00000002
-#define BCHP_SUN_TOP_CTRL_SSP_CONFIG_spi_mode_SHIFT 1
-
-/* SUN_TOP_CTRL :: SSP_CONFIG :: ssp_module_enable [00:00] */
-#define BCHP_SUN_TOP_CTRL_SSP_CONFIG_ssp_module_enable_MASK 0x00000001
-#define BCHP_SUN_TOP_CTRL_SSP_CONFIG_ssp_module_enable_SHIFT 0
-#define BCHP_SUN_TOP_CTRL_SSP_CONFIG_ssp_module_enable_DEFAULT 0x00000001
-
-/***************************************************************************
- *SERS_REV - SERS Revision Register
- ***************************************************************************/
-/* SUN_TOP_CTRL :: SERS_REV :: reserved0 [31:16] */
-#define BCHP_SUN_TOP_CTRL_SERS_REV_reserved0_MASK 0xffff0000
-#define BCHP_SUN_TOP_CTRL_SERS_REV_reserved0_SHIFT 16
-
-/* SUN_TOP_CTRL :: SERS_REV :: reserved_for_eco1 [15:08] */
-#define BCHP_SUN_TOP_CTRL_SERS_REV_reserved_for_eco1_MASK 0x0000ff00
-#define BCHP_SUN_TOP_CTRL_SERS_REV_reserved_for_eco1_SHIFT 8
-#define BCHP_SUN_TOP_CTRL_SERS_REV_reserved_for_eco1_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: SERS_REV :: BLOCK_SERS_REVISION [07:00] */
-#define BCHP_SUN_TOP_CTRL_SERS_REV_BLOCK_SERS_REVISION_MASK 0x000000ff
-#define BCHP_SUN_TOP_CTRL_SERS_REV_BLOCK_SERS_REVISION_SHIFT 0
-#define BCHP_SUN_TOP_CTRL_SERS_REV_BLOCK_SERS_REVISION_DEFAULT 0x00000000
-
-/***************************************************************************
- *SERS_CFG - SERS Configuration Register
- ***************************************************************************/
-/* SUN_TOP_CTRL :: SERS_CFG :: reserved_for_eco0 [31:29] */
-#define BCHP_SUN_TOP_CTRL_SERS_CFG_reserved_for_eco0_MASK 0xe0000000
-#define BCHP_SUN_TOP_CTRL_SERS_CFG_reserved_for_eco0_SHIFT 29
-#define BCHP_SUN_TOP_CTRL_SERS_CFG_reserved_for_eco0_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: SERS_CFG :: CMD_MODE [28:28] */
-#define BCHP_SUN_TOP_CTRL_SERS_CFG_CMD_MODE_MASK 0x10000000
-#define BCHP_SUN_TOP_CTRL_SERS_CFG_CMD_MODE_SHIFT 28
-#define BCHP_SUN_TOP_CTRL_SERS_CFG_CMD_MODE_DEFAULT 0x00000001
-#define BCHP_SUN_TOP_CTRL_SERS_CFG_CMD_MODE_mapped_buffer_mode 0
-#define BCHP_SUN_TOP_CTRL_SERS_CFG_CMD_MODE_cmd_fifo_mode 1
-
-/* SUN_TOP_CTRL :: SERS_CFG :: Little_Endian [27:27] */
-#define BCHP_SUN_TOP_CTRL_SERS_CFG_Little_Endian_MASK 0x08000000
-#define BCHP_SUN_TOP_CTRL_SERS_CFG_Little_Endian_SHIFT 27
-#define BCHP_SUN_TOP_CTRL_SERS_CFG_Little_Endian_DEFAULT 0x00000000
-
-/* union - case mapped_buffer_mode [26:08] */
-/* SUN_TOP_CTRL :: SERS_CFG :: mapped_buffer_mode :: W_PKT_OFFSET_4 [26:22] */
-#define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_W_PKT_OFFSET_4_MASK 0x07c00000
-#define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_W_PKT_OFFSET_4_SHIFT 22
-
-/* SUN_TOP_CTRL :: SERS_CFG :: mapped_buffer_mode :: W_PKT_OFFSET_3 [21:17] */
-#define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_W_PKT_OFFSET_3_MASK 0x003e0000
-#define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_W_PKT_OFFSET_3_SHIFT 17
-
-/* SUN_TOP_CTRL :: SERS_CFG :: mapped_buffer_mode :: W_PKT_OFFSET_2 [16:12] */
-#define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_W_PKT_OFFSET_2_MASK 0x0001f000
-#define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_W_PKT_OFFSET_2_SHIFT 12
-
-/* SUN_TOP_CTRL :: SERS_CFG :: mapped_buffer_mode :: DATA_CHG_IRQ_ONLY_4 [11:11] */
-#define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_DATA_CHG_IRQ_ONLY_4_MASK 0x00000800
-#define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_DATA_CHG_IRQ_ONLY_4_SHIFT 11
-#define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_DATA_CHG_IRQ_ONLY_4_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: SERS_CFG :: mapped_buffer_mode :: DATA_CHG_IRQ_ONLY_3 [10:10] */
-#define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_DATA_CHG_IRQ_ONLY_3_MASK 0x00000400
-#define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_DATA_CHG_IRQ_ONLY_3_SHIFT 10
-#define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_DATA_CHG_IRQ_ONLY_3_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: SERS_CFG :: mapped_buffer_mode :: DATA_CHG_IRQ_ONLY_2 [09:09] */
-#define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_DATA_CHG_IRQ_ONLY_2_MASK 0x00000200
-#define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_DATA_CHG_IRQ_ONLY_2_SHIFT 9
-#define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_DATA_CHG_IRQ_ONLY_2_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: SERS_CFG :: mapped_buffer_mode :: DATA_CHG_IRQ_ONLY_1 [08:08] */
-#define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_DATA_CHG_IRQ_ONLY_1_MASK 0x00000100
-#define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_DATA_CHG_IRQ_ONLY_1_SHIFT 8
-#define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_DATA_CHG_IRQ_ONLY_1_DEFAULT 0x00000000
-
-/* union - case cmd_fifo_mode [26:08] */
-/* SUN_TOP_CTRL :: SERS_CFG :: cmd_fifo_mode :: CMD_W_PTR [26:22] */
-#define BCHP_SUN_TOP_CTRL_SERS_CFG_cmd_fifo_mode_CMD_W_PTR_MASK 0x07c00000
-#define BCHP_SUN_TOP_CTRL_SERS_CFG_cmd_fifo_mode_CMD_W_PTR_SHIFT 22
-#define BCHP_SUN_TOP_CTRL_SERS_CFG_cmd_fifo_mode_CMD_W_PTR_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: SERS_CFG :: cmd_fifo_mode :: CMD_R_PTR [21:17] */
-#define BCHP_SUN_TOP_CTRL_SERS_CFG_cmd_fifo_mode_CMD_R_PTR_MASK 0x003e0000
-#define BCHP_SUN_TOP_CTRL_SERS_CFG_cmd_fifo_mode_CMD_R_PTR_SHIFT 17
-#define BCHP_SUN_TOP_CTRL_SERS_CFG_cmd_fifo_mode_CMD_R_PTR_DEFAULT 0x0000001f
-
-/* SUN_TOP_CTRL :: SERS_CFG :: cmd_fifo_mode :: FIFO_THRESHOLD [16:12] */
-#define BCHP_SUN_TOP_CTRL_SERS_CFG_cmd_fifo_mode_FIFO_THRESHOLD_MASK 0x0001f000
-#define BCHP_SUN_TOP_CTRL_SERS_CFG_cmd_fifo_mode_FIFO_THRESHOLD_SHIFT 12
-#define BCHP_SUN_TOP_CTRL_SERS_CFG_cmd_fifo_mode_FIFO_THRESHOLD_DEFAULT 0x00000010
-
-/* SUN_TOP_CTRL :: SERS_CFG :: cmd_fifo_mode :: NOT_USED [11:10] */
-#define BCHP_SUN_TOP_CTRL_SERS_CFG_cmd_fifo_mode_NOT_USED_MASK 0x00000c00
-#define BCHP_SUN_TOP_CTRL_SERS_CFG_cmd_fifo_mode_NOT_USED_SHIFT 10
-#define BCHP_SUN_TOP_CTRL_SERS_CFG_cmd_fifo_mode_NOT_USED_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: SERS_CFG :: cmd_fifo_mode :: CMD_FIFO_OV [09:09] */
-#define BCHP_SUN_TOP_CTRL_SERS_CFG_cmd_fifo_mode_CMD_FIFO_OV_MASK 0x00000200
-#define BCHP_SUN_TOP_CTRL_SERS_CFG_cmd_fifo_mode_CMD_FIFO_OV_SHIFT 9
-#define BCHP_SUN_TOP_CTRL_SERS_CFG_cmd_fifo_mode_CMD_FIFO_OV_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: SERS_CFG :: cmd_fifo_mode :: DROP_CMDS [08:08] */
-#define BCHP_SUN_TOP_CTRL_SERS_CFG_cmd_fifo_mode_DROP_CMDS_MASK 0x00000100
-#define BCHP_SUN_TOP_CTRL_SERS_CFG_cmd_fifo_mode_DROP_CMDS_SHIFT 8
-#define BCHP_SUN_TOP_CTRL_SERS_CFG_cmd_fifo_mode_DROP_CMDS_DEFAULT 0x00000001
-
-/* SUN_TOP_CTRL :: SERS_CFG :: SER_ADR [07:01] */
-#define BCHP_SUN_TOP_CTRL_SERS_CFG_SER_ADR_MASK 0x000000fe
-#define BCHP_SUN_TOP_CTRL_SERS_CFG_SER_ADR_SHIFT 1
-#define BCHP_SUN_TOP_CTRL_SERS_CFG_SER_ADR_DEFAULT 0x00000000
-
-/* SUN_TOP_CTRL :: SERS_CFG :: SOFT_SER_ADR [00:00] */
-#define BCHP_SUN_TOP_CTRL_SERS_CFG_SOFT_SER_ADR_MASK 0x00000001
-#define BCHP_SUN_TOP_CTRL_SERS_CFG_SOFT_SER_ADR_SHIFT 0
-#define BCHP_SUN_TOP_CTRL_SERS_CFG_SOFT_SER_ADR_DEFAULT 0x00000000
-
-/***************************************************************************
- *SERS_CMD_BUF_%i - Host Serial Write Command Buffer
- ***************************************************************************/
-#define BCHP_SUN_TOP_CTRL_SERS_CMD_BUF_i_ARRAY_BASE 0x00404428
-#define BCHP_SUN_TOP_CTRL_SERS_CMD_BUF_i_ARRAY_START 0
-#define BCHP_SUN_TOP_CTRL_SERS_CMD_BUF_i_ARRAY_END 7
-#define BCHP_SUN_TOP_CTRL_SERS_CMD_BUF_i_ARRAY_ELEMENT_SIZE 32
-
-/***************************************************************************
- *SERS_CMD_BUF_%i - Host Serial Write Command Buffer
- ***************************************************************************/
-/* SUN_TOP_CTRL :: SERS_CMD_BUF_i :: SERS_CMD_BUF [31:00] */
-#define BCHP_SUN_TOP_CTRL_SERS_CMD_BUF_i_SERS_CMD_BUF_MASK 0xffffffff
-#define BCHP_SUN_TOP_CTRL_SERS_CMD_BUF_i_SERS_CMD_BUF_SHIFT 0
-
-
-/***************************************************************************
- *SERS_STAT_BUF_%i - Host Serial Read Status Buffer
- ***************************************************************************/
-#define BCHP_SUN_TOP_CTRL_SERS_STAT_BUF_i_ARRAY_BASE 0x00404448
-#define BCHP_SUN_TOP_CTRL_SERS_STAT_BUF_i_ARRAY_START 0
-#define BCHP_SUN_TOP_CTRL_SERS_STAT_BUF_i_ARRAY_END 1
-#define BCHP_SUN_TOP_CTRL_SERS_STAT_BUF_i_ARRAY_ELEMENT_SIZE 32
-
-/***************************************************************************
- *SERS_STAT_BUF_%i - Host Serial Read Status Buffer
- ***************************************************************************/
-/* SUN_TOP_CTRL :: SERS_STAT_BUF_i :: SERS_STAT_BUF [31:00] */
-#define BCHP_SUN_TOP_CTRL_SERS_STAT_BUF_i_SERS_STAT_BUF_MASK 0xffffffff
-#define BCHP_SUN_TOP_CTRL_SERS_STAT_BUF_i_SERS_STAT_BUF_SHIFT 0
-
-
-/***************************************************************************
- *RO_TEST_BLOCK_SEL - Block select for RO testmode
- ***************************************************************************/
-/* SUN_TOP_CTRL :: RO_TEST_BLOCK_SEL :: reserved0 [31:18] */
-#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_reserved0_MASK 0xfffc0000
-#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_reserved0_SHIFT 18
-
-/* SUN_TOP_CTRL :: RO_TEST_BLOCK_SEL :: ro_test_sub_block_select [17:14] */
-#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_sub_block_select_MASK 0x0003c000
-#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_sub_block_select_SHIFT 14
-#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_sub_block_select_DEFAULT 0x00000000
-#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_sub_block_select_STANDARD_VT_CMOS 0
-#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_sub_block_select_SUPER_HVT_CMOS 1
-#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_sub_block_select_SUPER_LVT_CMOS 2
-#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_sub_block_select_STANDARD_VT_NMOS 3
-#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_sub_block_select_SUPER_HVT_NMOS 4
-#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_sub_block_select_SUPER_LVT_NMOS 5
-#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_sub_block_select_STANDARD_VT_PMOS 6
-#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_sub_block_select_SUPER_HVT_PMOS 7
-#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_sub_block_select_SUPER_LVT_PMOS 8
-#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_sub_block_select_IO_CMOS 9
-#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_sub_block_select_IO_NMOS 10
-#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_sub_block_select_IO_PMOS 11
-
-/* SUN_TOP_CTRL :: RO_TEST_BLOCK_SEL :: ro_test_sub_block_en [13:02] */
-#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_sub_block_en_MASK 0x00003ffc
-#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_sub_block_en_SHIFT 2
-#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_sub_block_en_DEFAULT 0x00000000
-#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_sub_block_en_DISABLE_RO 0
-#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_sub_block_en_STANDARD_VT_CMOS_ONE_HOT 1
-#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_sub_block_en_SUPER_HVT_CMOS_ONE_HOT 2
-#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_sub_block_en_SUPER_LVT_CMOS_ONE_HOT 4
-#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_sub_block_en_STANDARD_VT_NMOS_ONE_HOT 8
-#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_sub_block_en_SUPER_HVT_NMOS_ONE_HOT 16
-#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_sub_block_en_SUPER_LVT_NMOS_ONE_HOT 32
-#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_sub_block_en_STANDARD_VT_PMOS_ONE_HOT 64
-#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_sub_block_en_SUPER_HVT_PMOS_ONE_HOT 128
-#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_sub_block_en_SUPER_LVT_PMOS_ONE_HOT 256
-#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_sub_block_en_IO_CMOS_ONE_HOT 512
-#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_sub_block_en_IO_NMOS_ONE_HOT 1024
-#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_sub_block_en_IO_PMOS_ONE_HOT 2048
-
-/* SUN_TOP_CTRL :: RO_TEST_BLOCK_SEL :: ro_test_block_select [01:00] */
-#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_block_select_MASK 0x00000003
-#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_block_select_SHIFT 0
-#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_block_select_DEFAULT 0x00000000
-#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_block_select_DO_NOT_USE_RO_TEST_ID 0
-#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_block_select_PROD_OSC0_RO_TEST_ID 1
-#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_block_select_PROD_OSC1_RO_TEST_ID 2
-#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_block_select_UNUSED_3_RO_TEST_ID 3
-
-/***************************************************************************
- *TEST_CONFIGURATION - Test configuration
- ***************************************************************************/
-/* SUN_TOP_CTRL :: TEST_CONFIGURATION :: reserved0 [31:04] */
-#define BCHP_SUN_TOP_CTRL_TEST_CONFIGURATION_reserved0_MASK 0xfffffff0
-#define BCHP_SUN_TOP_CTRL_TEST_CONFIGURATION_reserved0_SHIFT 4
-
-/* SUN_TOP_CTRL :: TEST_CONFIGURATION :: test_configuration [03:00] */
-#define BCHP_SUN_TOP_CTRL_TEST_CONFIGURATION_test_configuration_MASK 0x0000000f
-#define BCHP_SUN_TOP_CTRL_TEST_CONFIGURATION_test_configuration_SHIFT 0
-#define BCHP_SUN_TOP_CTRL_TEST_CONFIGURATION_test_configuration_DEFAULT 0x00000000
-
-#endif /* #ifndef BCHP_SUN_TOP_CTRL_H__ */
-
-/* End of File */
diff --git a/include/linux/brcmstb/7439a0/bchp_usb_ctrl.h b/include/linux/brcmstb/7439a0/bchp_usb_ctrl.h
deleted file mode 100644
index fd5562c..0000000
--- a/include/linux/brcmstb/7439a0/bchp_usb_ctrl.h
+++ /dev/null
@@ -1,1296 +0,0 @@
-/***************************************************************************
- * Copyright (c) 1999-2014, Broadcom Corporation
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
- *
- * Module Description:
- * DO NOT EDIT THIS FILE DIRECTLY
- *
- * This module was generated magically with RDB from a source description
- * file. You must edit the source file for changes to be made to this file.
- *
- *
- * Date: Generated on Wed Sep 3 14:30:55 2014
- * Full Compile MD5 Checksum edbc259d5ef948d04693ec04bc4d44b4
- * (minus title and desc)
- * MD5 Checksum de2524c7728bb833dc65ac44b70daaa5
- *
- * Compiled with: RDB Utility combo_header.pl
- * RDB Parser 3.0
- * unknown unknown
- * Perl Interpreter 5.008005
- * Operating System linux
- *
- * Revision History:
- *
- * $brcm_Log: $
- *
- ***************************************************************************/
-
-#ifndef BCHP_USB_CTRL_H__
-#define BCHP_USB_CTRL_H__
-
-/***************************************************************************
- *USB_CTRL - USB Control Registers
- ***************************************************************************/
-#define BCHP_USB_CTRL_SETUP 0x00480200 /* Setup Register */
-#define BCHP_USB_CTRL_PLL_CTL 0x00480204 /* PLL Control Register */
-#define BCHP_USB_CTRL_FLADJ_VALUE 0x00480208 /* Frame Adjust Value */
-#define BCHP_USB_CTRL_EBRIDGE 0x0048020c /* Control Register for EHCI Bridge */
-#define BCHP_USB_CTRL_OBRIDGE 0x00480210 /* Control Register for OHCI Bridge */
-#define BCHP_USB_CTRL_MDIO 0x00480214 /* MDIO Interface Programming Register */
-#define BCHP_USB_CTRL_MDIO2 0x00480218 /* MDIO Interface Read Register */
-#define BCHP_USB_CTRL_TEST_PORT_CTL 0x0048021c /* Test Port Control Register */
-#define BCHP_USB_CTRL_USB_SIMCTL 0x00480220 /* Simulation Register */
-#define BCHP_USB_CTRL_USB_TESTCTL 0x00480224 /* Throutput Test Control */
-#define BCHP_USB_CTRL_USB_TESTMON 0x00480228 /* Throughput Test Monitor */
-#define BCHP_USB_CTRL_UTMI_CTL_1 0x0048022c /* UTMI Control Register */
-#define BCHP_USB_CTRL_UTMI_CTL_2 0x00480230 /* UTMI Control 2 Register */
-#define BCHP_USB_CTRL_USB_PM 0x00480234 /* Power Management Register */
-#define BCHP_USB_CTRL_OHCI_ADDR_EXT 0x00480238 /* OHCI ADDRESS Extension */
-#define BCHP_USB_CTRL_USB_PM_STATUS 0x0048023c /* usb20 Power Management Status */
-#define BCHP_USB_CTRL_PLL_LDO_CTL 0x00480240 /* 28NM USBPHY LDO Control */
-#define BCHP_USB_CTRL_PLL_LDO_PLLBIAS 0x00480244 /* 28NM USBPHY PLLBIAS Control */
-#define BCHP_USB_CTRL_PLL_AFE_BG_CNTL 0x00480248 /* 28NM USBPHY AFE Bandgap Control */
-#define BCHP_USB_CTRL_AFE_USBIO_TST 0x0048024c /* 28NM USBPHY AFE Bandgap Control */
-#define BCHP_USB_CTRL_PLL_NDIV_FRAC 0x00480250 /* PLL Feedback Divider Control Register */
-#define BCHP_USB_CTRL_SPARE2 0x00480254 /* Spare2 Register for future use */
-#define BCHP_USB_CTRL_SPARE3 0x00480258 /* Spare1 Register for future use */
-#define BCHP_USB_CTRL_SPARE4 0x0048025c /* Spare1 Register for future use */
-#define BCHP_USB_CTRL_USB30_CTL1 0x00480260 /* USB30 CONTROL Register 1 */
-#define BCHP_USB_CTRL_USB30_CTL2 0x00480264 /* USB30 CONTROL Register 2 */
-#define BCHP_USB_CTRL_USB30_CTL3 0x00480268 /* USB30 CONTROL Register 3 */
-#define BCHP_USB_CTRL_USB30_CTL4 0x0048026c /* USB30 CONTROL Register 4 */
-#define BCHP_USB_CTRL_USB30_PCTL 0x00480270 /* USB30 PORT CONTROL Register */
-#define BCHP_USB_CTRL_USB30_CTL5 0x00480274 /* USB30 CONTROL Register 5 */
-#define BCHP_USB_CTRL_SPARE5 0x00480278 /* Spare1 Register for future use */
-#define BCHP_USB_CTRL_SPARE6 0x0048027c /* Spare2 Register for future use */
-
-/***************************************************************************
- *SETUP - Setup Register
- ***************************************************************************/
-/* USB_CTRL :: SETUP :: OC_DISABLE [31:28] */
-#define BCHP_USB_CTRL_SETUP_OC_DISABLE_MASK 0xf0000000
-#define BCHP_USB_CTRL_SETUP_OC_DISABLE_SHIFT 28
-#define BCHP_USB_CTRL_SETUP_OC_DISABLE_DEFAULT 0x00000000
-
-/* USB_CTRL :: SETUP :: SRAM_CS_DIS [27:25] */
-#define BCHP_USB_CTRL_SETUP_SRAM_CS_DIS_MASK 0x0e000000
-#define BCHP_USB_CTRL_SETUP_SRAM_CS_DIS_SHIFT 25
-#define BCHP_USB_CTRL_SETUP_SRAM_CS_DIS_DEFAULT 0x00000000
-
-/* USB_CTRL :: SETUP :: SETUP_SPARE [24:19] */
-#define BCHP_USB_CTRL_SETUP_SETUP_SPARE_MASK 0x01f80000
-#define BCHP_USB_CTRL_SETUP_SETUP_SPARE_SHIFT 19
-#define BCHP_USB_CTRL_SETUP_SETUP_SPARE_DEFAULT 0x00000000
-
-/* USB_CTRL :: SETUP :: ohci_susp_lgcy [18:18] */
-#define BCHP_USB_CTRL_SETUP_ohci_susp_lgcy_MASK 0x00040000
-#define BCHP_USB_CTRL_SETUP_ohci_susp_lgcy_SHIFT 18
-#define BCHP_USB_CTRL_SETUP_ohci_susp_lgcy_DEFAULT 0x00000000
-
-/* USB_CTRL :: SETUP :: ss_ulpi_pp2vbus [17:17] */
-#define BCHP_USB_CTRL_SETUP_ss_ulpi_pp2vbus_MASK 0x00020000
-#define BCHP_USB_CTRL_SETUP_ss_ulpi_pp2vbus_SHIFT 17
-#define BCHP_USB_CTRL_SETUP_ss_ulpi_pp2vbus_DEFAULT 0x00000000
-
-/* USB_CTRL :: SETUP :: ss_ehci64bit_en [16:16] */
-#define BCHP_USB_CTRL_SETUP_ss_ehci64bit_en_MASK 0x00010000
-#define BCHP_USB_CTRL_SETUP_ss_ehci64bit_en_SHIFT 16
-#define BCHP_USB_CTRL_SETUP_ss_ehci64bit_en_DEFAULT 0x00000000
-
-/* USB_CTRL :: SETUP :: scb2_en [15:15] */
-#define BCHP_USB_CTRL_SETUP_scb2_en_MASK 0x00008000
-#define BCHP_USB_CTRL_SETUP_scb2_en_SHIFT 15
-#define BCHP_USB_CTRL_SETUP_scb2_en_DEFAULT 0x00000000
-
-/* USB_CTRL :: SETUP :: scb1_en [14:14] */
-#define BCHP_USB_CTRL_SETUP_scb1_en_MASK 0x00004000
-#define BCHP_USB_CTRL_SETUP_scb1_en_SHIFT 14
-#define BCHP_USB_CTRL_SETUP_scb1_en_DEFAULT 0x00000000
-
-/* USB_CTRL :: SETUP :: scb_client_swap [13:13] */
-#define BCHP_USB_CTRL_SETUP_scb_client_swap_MASK 0x00002000
-#define BCHP_USB_CTRL_SETUP_scb_client_swap_SHIFT 13
-#define BCHP_USB_CTRL_SETUP_scb_client_swap_DEFAULT 0x00000000
-
-/* USB_CTRL :: SETUP :: async_expire_dis [12:12] */
-#define BCHP_USB_CTRL_SETUP_async_expire_dis_MASK 0x00001000
-#define BCHP_USB_CTRL_SETUP_async_expire_dis_SHIFT 12
-#define BCHP_USB_CTRL_SETUP_async_expire_dis_DEFAULT 0x00000000
-
-/* USB_CTRL :: SETUP :: SETUP_SPARE1 [11:10] */
-#define BCHP_USB_CTRL_SETUP_SETUP_SPARE1_MASK 0x00000c00
-#define BCHP_USB_CTRL_SETUP_SETUP_SPARE1_SHIFT 10
-#define BCHP_USB_CTRL_SETUP_SETUP_SPARE1_DEFAULT 0x00000000
-
-/* USB_CTRL :: SETUP :: soft_shutdown [09:09] */
-#define BCHP_USB_CTRL_SETUP_soft_shutdown_MASK 0x00000200
-#define BCHP_USB_CTRL_SETUP_soft_shutdown_SHIFT 9
-#define BCHP_USB_CTRL_SETUP_soft_shutdown_DEFAULT 0x00000000
-
-/* USB_CTRL :: SETUP :: utmi_bkward_en [08:08] */
-#define BCHP_USB_CTRL_SETUP_utmi_bkward_en_MASK 0x00000100
-#define BCHP_USB_CTRL_SETUP_utmi_bkward_en_SHIFT 8
-#define BCHP_USB_CTRL_SETUP_utmi_bkward_en_DEFAULT 0x00000000
-
-/* USB_CTRL :: SETUP :: utmi_pls_en [07:07] */
-#define BCHP_USB_CTRL_SETUP_utmi_pls_en_MASK 0x00000080
-#define BCHP_USB_CTRL_SETUP_utmi_pls_en_SHIFT 7
-#define BCHP_USB_CTRL_SETUP_utmi_pls_en_DEFAULT 0x00000000
-
-/* USB_CTRL :: SETUP :: soft_reset [06:06] */
-#define BCHP_USB_CTRL_SETUP_soft_reset_MASK 0x00000040
-#define BCHP_USB_CTRL_SETUP_soft_reset_SHIFT 6
-#define BCHP_USB_CTRL_SETUP_soft_reset_DEFAULT 0x00000000
-
-/* USB_CTRL :: SETUP :: IPP [05:05] */
-#define BCHP_USB_CTRL_SETUP_IPP_MASK 0x00000020
-#define BCHP_USB_CTRL_SETUP_IPP_SHIFT 5
-#define BCHP_USB_CTRL_SETUP_IPP_DEFAULT 0x00000000
-
-/* USB_CTRL :: SETUP :: IOC [04:04] */
-#define BCHP_USB_CTRL_SETUP_IOC_MASK 0x00000010
-#define BCHP_USB_CTRL_SETUP_IOC_SHIFT 4
-#define BCHP_USB_CTRL_SETUP_IOC_DEFAULT 0x00000000
-
-/* USB_CTRL :: SETUP :: WABO [03:03] */
-#define BCHP_USB_CTRL_SETUP_WABO_MASK 0x00000008
-#define BCHP_USB_CTRL_SETUP_WABO_SHIFT 3
-#define BCHP_USB_CTRL_SETUP_WABO_DEFAULT 0x00000000
-
-/* USB_CTRL :: SETUP :: FNBO [02:02] */
-#define BCHP_USB_CTRL_SETUP_FNBO_MASK 0x00000004
-#define BCHP_USB_CTRL_SETUP_FNBO_SHIFT 2
-#define BCHP_USB_CTRL_SETUP_FNBO_DEFAULT 0x00000000
-
-/* USB_CTRL :: SETUP :: FNHW [01:01] */
-#define BCHP_USB_CTRL_SETUP_FNHW_MASK 0x00000002
-#define BCHP_USB_CTRL_SETUP_FNHW_SHIFT 1
-#define BCHP_USB_CTRL_SETUP_FNHW_DEFAULT 0x00000000
-
-/* USB_CTRL :: SETUP :: BABO [00:00] */
-#define BCHP_USB_CTRL_SETUP_BABO_MASK 0x00000001
-#define BCHP_USB_CTRL_SETUP_BABO_SHIFT 0
-#define BCHP_USB_CTRL_SETUP_BABO_DEFAULT 0x00000000
-
-/***************************************************************************
- *PLL_CTL - PLL Control Register
- ***************************************************************************/
-/* USB_CTRL :: PLL_CTL :: PLL_IDDQ_PWRDN [31:31] */
-#define BCHP_USB_CTRL_PLL_CTL_PLL_IDDQ_PWRDN_MASK 0x80000000
-#define BCHP_USB_CTRL_PLL_CTL_PLL_IDDQ_PWRDN_SHIFT 31
-#define BCHP_USB_CTRL_PLL_CTL_PLL_IDDQ_PWRDN_DEFAULT 0x00000001
-
-/* USB_CTRL :: PLL_CTL :: PLL_RESETB [30:30] */
-#define BCHP_USB_CTRL_PLL_CTL_PLL_RESETB_MASK 0x40000000
-#define BCHP_USB_CTRL_PLL_CTL_PLL_RESETB_SHIFT 30
-#define BCHP_USB_CTRL_PLL_CTL_PLL_RESETB_DEFAULT 0x00000001
-
-/* USB_CTRL :: PLL_CTL :: PHYPLL_BYP [29:29] */
-#define BCHP_USB_CTRL_PLL_CTL_PHYPLL_BYP_MASK 0x20000000
-#define BCHP_USB_CTRL_PLL_CTL_PHYPLL_BYP_SHIFT 29
-#define BCHP_USB_CTRL_PLL_CTL_PHYPLL_BYP_DEFAULT 0x00000000
-
-/* USB_CTRL :: PLL_CTL :: PLL_PWRDWNB [28:28] */
-#define BCHP_USB_CTRL_PLL_CTL_PLL_PWRDWNB_MASK 0x10000000
-#define BCHP_USB_CTRL_PLL_CTL_PLL_PWRDWNB_SHIFT 28
-#define BCHP_USB_CTRL_PLL_CTL_PLL_PWRDWNB_DEFAULT 0x00000001
-
-/* USB_CTRL :: PLL_CTL :: PLL_SUSPEND_EN [27:27] */
-#define BCHP_USB_CTRL_PLL_CTL_PLL_SUSPEND_EN_MASK 0x08000000
-#define BCHP_USB_CTRL_PLL_CTL_PLL_SUSPEND_EN_SHIFT 27
-#define BCHP_USB_CTRL_PLL_CTL_PLL_SUSPEND_EN_DEFAULT 0x00000000
-
-/* USB_CTRL :: PLL_CTL :: PLL_Ka [26:24] */
-#define BCHP_USB_CTRL_PLL_CTL_PLL_Ka_MASK 0x07000000
-#define BCHP_USB_CTRL_PLL_CTL_PLL_Ka_SHIFT 24
-#define BCHP_USB_CTRL_PLL_CTL_PLL_Ka_DEFAULT 0x00000000
-
-/* USB_CTRL :: PLL_CTL :: PLLCTL_SPARE3 [23:23] */
-#define BCHP_USB_CTRL_PLL_CTL_PLLCTL_SPARE3_MASK 0x00800000
-#define BCHP_USB_CTRL_PLL_CTL_PLLCTL_SPARE3_SHIFT 23
-#define BCHP_USB_CTRL_PLL_CTL_PLLCTL_SPARE3_DEFAULT 0x00000000
-
-/* USB_CTRL :: PLL_CTL :: PLL_Ki [22:20] */
-#define BCHP_USB_CTRL_PLL_CTL_PLL_Ki_MASK 0x00700000
-#define BCHP_USB_CTRL_PLL_CTL_PLL_Ki_SHIFT 20
-#define BCHP_USB_CTRL_PLL_CTL_PLL_Ki_DEFAULT 0x00000004
-
-/* USB_CTRL :: PLL_CTL :: PLL_Kp [19:16] */
-#define BCHP_USB_CTRL_PLL_CTL_PLL_Kp_MASK 0x000f0000
-#define BCHP_USB_CTRL_PLL_CTL_PLL_Kp_SHIFT 16
-#define BCHP_USB_CTRL_PLL_CTL_PLL_Kp_DEFAULT 0x0000000a
-
-/* USB_CTRL :: PLL_CTL :: PLL_pdiv [15:12] */
-#define BCHP_USB_CTRL_PLL_CTL_PLL_pdiv_MASK 0x0000f000
-#define BCHP_USB_CTRL_PLL_CTL_PLL_pdiv_SHIFT 12
-#define BCHP_USB_CTRL_PLL_CTL_PLL_pdiv_DEFAULT 0x00000001
-
-/* USB_CTRL :: PLL_CTL :: PLLCTL_SPARE1 [11:10] */
-#define BCHP_USB_CTRL_PLL_CTL_PLLCTL_SPARE1_MASK 0x00000c00
-#define BCHP_USB_CTRL_PLL_CTL_PLLCTL_SPARE1_SHIFT 10
-#define BCHP_USB_CTRL_PLL_CTL_PLLCTL_SPARE1_DEFAULT 0x00000000
-
-/* USB_CTRL :: PLL_CTL :: PLL_ndiv [09:00] */
-#define BCHP_USB_CTRL_PLL_CTL_PLL_ndiv_MASK 0x000003ff
-#define BCHP_USB_CTRL_PLL_CTL_PLL_ndiv_SHIFT 0
-#define BCHP_USB_CTRL_PLL_CTL_PLL_ndiv_DEFAULT 0x00000020
-
-/***************************************************************************
- *FLADJ_VALUE - Frame Adjust Value
- ***************************************************************************/
-/* USB_CTRL :: FLADJ_VALUE :: FLADJ_VAL [31:00] */
-#define BCHP_USB_CTRL_FLADJ_VALUE_FLADJ_VAL_MASK 0xffffffff
-#define BCHP_USB_CTRL_FLADJ_VALUE_FLADJ_VAL_SHIFT 0
-#define BCHP_USB_CTRL_FLADJ_VALUE_FLADJ_VAL_DEFAULT 0x000c0020
-
-/***************************************************************************
- *EBRIDGE - Control Register for EHCI Bridge
- ***************************************************************************/
-/* USB_CTRL :: EBRIDGE :: EBR_SOFT_RESET [31:31] */
-#define BCHP_USB_CTRL_EBRIDGE_EBR_SOFT_RESET_MASK 0x80000000
-#define BCHP_USB_CTRL_EBRIDGE_EBR_SOFT_RESET_SHIFT 31
-#define BCHP_USB_CTRL_EBRIDGE_EBR_SOFT_RESET_DEFAULT 0x00000000
-
-/* USB_CTRL :: EBRIDGE :: ebrff_reset [30:30] */
-#define BCHP_USB_CTRL_EBRIDGE_ebrff_reset_MASK 0x40000000
-#define BCHP_USB_CTRL_EBRIDGE_ebrff_reset_SHIFT 30
-#define BCHP_USB_CTRL_EBRIDGE_ebrff_reset_DEFAULT 0x00000000
-
-/* USB_CTRL :: EBRIDGE :: ebr_wrgwordcnt_sel [29:29] */
-#define BCHP_USB_CTRL_EBRIDGE_ebr_wrgwordcnt_sel_MASK 0x20000000
-#define BCHP_USB_CTRL_EBRIDGE_ebr_wrgwordcnt_sel_SHIFT 29
-#define BCHP_USB_CTRL_EBRIDGE_ebr_wrgwordcnt_sel_DEFAULT 0x00000000
-
-/* USB_CTRL :: EBRIDGE :: ebr_size_sel [28:28] */
-#define BCHP_USB_CTRL_EBRIDGE_ebr_size_sel_MASK 0x10000000
-#define BCHP_USB_CTRL_EBRIDGE_ebr_size_sel_SHIFT 28
-#define BCHP_USB_CTRL_EBRIDGE_ebr_size_sel_DEFAULT 0x00000000
-
-/* USB_CTRL :: EBRIDGE :: EBR_SPARE [27:17] */
-#define BCHP_USB_CTRL_EBRIDGE_EBR_SPARE_MASK 0x0ffe0000
-#define BCHP_USB_CTRL_EBRIDGE_EBR_SPARE_SHIFT 17
-#define BCHP_USB_CTRL_EBRIDGE_EBR_SPARE_DEFAULT 0x00000000
-
-/* USB_CTRL :: EBRIDGE :: EBR_RD_THRESH [16:12] */
-#define BCHP_USB_CTRL_EBRIDGE_EBR_RD_THRESH_MASK 0x0001f000
-#define BCHP_USB_CTRL_EBRIDGE_EBR_RD_THRESH_SHIFT 12
-#define BCHP_USB_CTRL_EBRIDGE_EBR_RD_THRESH_DEFAULT 0x00000002
-
-/* USB_CTRL :: EBRIDGE :: EBR_SCB_SIZE [11:07] */
-#define BCHP_USB_CTRL_EBRIDGE_EBR_SCB_SIZE_MASK 0x00000f80
-#define BCHP_USB_CTRL_EBRIDGE_EBR_SCB_SIZE_SHIFT 7
-#define BCHP_USB_CTRL_EBRIDGE_EBR_SCB_SIZE_DEFAULT 0x00000004
-
-/* USB_CTRL :: EBRIDGE :: EBR_MISC [06:01] */
-#define BCHP_USB_CTRL_EBRIDGE_EBR_MISC_MASK 0x0000007e
-#define BCHP_USB_CTRL_EBRIDGE_EBR_MISC_SHIFT 1
-#define BCHP_USB_CTRL_EBRIDGE_EBR_MISC_DEFAULT 0x00000000
-
-/* USB_CTRL :: EBRIDGE :: EBR_SEQ_EN [00:00] */
-#define BCHP_USB_CTRL_EBRIDGE_EBR_SEQ_EN_MASK 0x00000001
-#define BCHP_USB_CTRL_EBRIDGE_EBR_SEQ_EN_SHIFT 0
-#define BCHP_USB_CTRL_EBRIDGE_EBR_SEQ_EN_DEFAULT 0x00000000
-
-/***************************************************************************
- *OBRIDGE - Control Register for OHCI Bridge
- ***************************************************************************/
-/* USB_CTRL :: OBRIDGE :: OBR_SOFT_RESET [31:31] */
-#define BCHP_USB_CTRL_OBRIDGE_OBR_SOFT_RESET_MASK 0x80000000
-#define BCHP_USB_CTRL_OBRIDGE_OBR_SOFT_RESET_SHIFT 31
-#define BCHP_USB_CTRL_OBRIDGE_OBR_SOFT_RESET_DEFAULT 0x00000000
-
-/* USB_CTRL :: OBRIDGE :: obrff_reset [30:30] */
-#define BCHP_USB_CTRL_OBRIDGE_obrff_reset_MASK 0x40000000
-#define BCHP_USB_CTRL_OBRIDGE_obrff_reset_SHIFT 30
-#define BCHP_USB_CTRL_OBRIDGE_obrff_reset_DEFAULT 0x00000000
-
-/* USB_CTRL :: OBRIDGE :: obr_wrgwordcnt_sel [29:29] */
-#define BCHP_USB_CTRL_OBRIDGE_obr_wrgwordcnt_sel_MASK 0x20000000
-#define BCHP_USB_CTRL_OBRIDGE_obr_wrgwordcnt_sel_SHIFT 29
-#define BCHP_USB_CTRL_OBRIDGE_obr_wrgwordcnt_sel_DEFAULT 0x00000000
-
-/* USB_CTRL :: OBRIDGE :: obr_size_sel [28:28] */
-#define BCHP_USB_CTRL_OBRIDGE_obr_size_sel_MASK 0x10000000
-#define BCHP_USB_CTRL_OBRIDGE_obr_size_sel_SHIFT 28
-#define BCHP_USB_CTRL_OBRIDGE_obr_size_sel_DEFAULT 0x00000000
-
-/* USB_CTRL :: OBRIDGE :: OBR_SPARE [27:17] */
-#define BCHP_USB_CTRL_OBRIDGE_OBR_SPARE_MASK 0x0ffe0000
-#define BCHP_USB_CTRL_OBRIDGE_OBR_SPARE_SHIFT 17
-#define BCHP_USB_CTRL_OBRIDGE_OBR_SPARE_DEFAULT 0x00000000
-
-/* USB_CTRL :: OBRIDGE :: OBR_RD_THRESH [16:12] */
-#define BCHP_USB_CTRL_OBRIDGE_OBR_RD_THRESH_MASK 0x0001f000
-#define BCHP_USB_CTRL_OBRIDGE_OBR_RD_THRESH_SHIFT 12
-#define BCHP_USB_CTRL_OBRIDGE_OBR_RD_THRESH_DEFAULT 0x00000002
-
-/* USB_CTRL :: OBRIDGE :: OBR_SCB_SIZE [11:07] */
-#define BCHP_USB_CTRL_OBRIDGE_OBR_SCB_SIZE_MASK 0x00000f80
-#define BCHP_USB_CTRL_OBRIDGE_OBR_SCB_SIZE_SHIFT 7
-#define BCHP_USB_CTRL_OBRIDGE_OBR_SCB_SIZE_DEFAULT 0x00000004
-
-/* USB_CTRL :: OBRIDGE :: OBR_MISC [06:01] */
-#define BCHP_USB_CTRL_OBRIDGE_OBR_MISC_MASK 0x0000007e
-#define BCHP_USB_CTRL_OBRIDGE_OBR_MISC_SHIFT 1
-#define BCHP_USB_CTRL_OBRIDGE_OBR_MISC_DEFAULT 0x00000000
-
-/* USB_CTRL :: OBRIDGE :: OBR_SEQ_EN [00:00] */
-#define BCHP_USB_CTRL_OBRIDGE_OBR_SEQ_EN_MASK 0x00000001
-#define BCHP_USB_CTRL_OBRIDGE_OBR_SEQ_EN_SHIFT 0
-#define BCHP_USB_CTRL_OBRIDGE_OBR_SEQ_EN_DEFAULT 0x00000000
-
-/***************************************************************************
- *MDIO - MDIO Interface Programming Register
- ***************************************************************************/
-/* USB_CTRL :: MDIO :: MDIO_PHY_SEL [31:31] */
-#define BCHP_USB_CTRL_MDIO_MDIO_PHY_SEL_MASK 0x80000000
-#define BCHP_USB_CTRL_MDIO_MDIO_PHY_SEL_SHIFT 31
-#define BCHP_USB_CTRL_MDIO_MDIO_PHY_SEL_DEFAULT 0x00000000
-
-/* USB_CTRL :: MDIO :: MDIO_SPARE [30:26] */
-#define BCHP_USB_CTRL_MDIO_MDIO_SPARE_MASK 0x7c000000
-#define BCHP_USB_CTRL_MDIO_MDIO_SPARE_SHIFT 26
-#define BCHP_USB_CTRL_MDIO_MDIO_SPARE_DEFAULT 0x00000000
-
-/* USB_CTRL :: MDIO :: WR_START [25:25] */
-#define BCHP_USB_CTRL_MDIO_WR_START_MASK 0x02000000
-#define BCHP_USB_CTRL_MDIO_WR_START_SHIFT 25
-#define BCHP_USB_CTRL_MDIO_WR_START_DEFAULT 0x00000000
-
-/* USB_CTRL :: MDIO :: RD_START [24:24] */
-#define BCHP_USB_CTRL_MDIO_RD_START_MASK 0x01000000
-#define BCHP_USB_CTRL_MDIO_RD_START_SHIFT 24
-#define BCHP_USB_CTRL_MDIO_RD_START_DEFAULT 0x00000000
-
-/* USB_CTRL :: MDIO :: MDIO_ADDR [23:16] */
-#define BCHP_USB_CTRL_MDIO_MDIO_ADDR_MASK 0x00ff0000
-#define BCHP_USB_CTRL_MDIO_MDIO_ADDR_SHIFT 16
-#define BCHP_USB_CTRL_MDIO_MDIO_ADDR_DEFAULT 0x00000000
-
-/* USB_CTRL :: MDIO :: MDIO_DATA [15:00] */
-#define BCHP_USB_CTRL_MDIO_MDIO_DATA_MASK 0x0000ffff
-#define BCHP_USB_CTRL_MDIO_MDIO_DATA_SHIFT 0
-#define BCHP_USB_CTRL_MDIO_MDIO_DATA_DEFAULT 0x00000000
-
-/***************************************************************************
- *MDIO2 - MDIO Interface Read Register
- ***************************************************************************/
-/* USB_CTRL :: MDIO2 :: SYNOPSIS_CORE_ID [31:16] */
-#define BCHP_USB_CTRL_MDIO2_SYNOPSIS_CORE_ID_MASK 0xffff0000
-#define BCHP_USB_CTRL_MDIO2_SYNOPSIS_CORE_ID_SHIFT 16
-#define BCHP_USB_CTRL_MDIO2_SYNOPSIS_CORE_ID_DEFAULT 0x0000296a
-
-/* USB_CTRL :: MDIO2 :: MDIO_RD_DATA [15:00] */
-#define BCHP_USB_CTRL_MDIO2_MDIO_RD_DATA_MASK 0x0000ffff
-#define BCHP_USB_CTRL_MDIO2_MDIO_RD_DATA_SHIFT 0
-#define BCHP_USB_CTRL_MDIO2_MDIO_RD_DATA_DEFAULT 0x00000000
-
-/***************************************************************************
- *TEST_PORT_CTL - Test Port Control Register
- ***************************************************************************/
-/* USB_CTRL :: TEST_PORT_CTL :: TP_EN [31:31] */
-#define BCHP_USB_CTRL_TEST_PORT_CTL_TP_EN_MASK 0x80000000
-#define BCHP_USB_CTRL_TEST_PORT_CTL_TP_EN_SHIFT 31
-#define BCHP_USB_CTRL_TEST_PORT_CTL_TP_EN_DEFAULT 0x00000000
-
-/* USB_CTRL :: TEST_PORT_CTL :: TPCTL_SPARE [30:28] */
-#define BCHP_USB_CTRL_TEST_PORT_CTL_TPCTL_SPARE_MASK 0x70000000
-#define BCHP_USB_CTRL_TEST_PORT_CTL_TPCTL_SPARE_SHIFT 28
-#define BCHP_USB_CTRL_TEST_PORT_CTL_TPCTL_SPARE_DEFAULT 0x00000000
-
-/* USB_CTRL :: TEST_PORT_CTL :: scb2_wr_data_sel [27:27] */
-#define BCHP_USB_CTRL_TEST_PORT_CTL_scb2_wr_data_sel_MASK 0x08000000
-#define BCHP_USB_CTRL_TEST_PORT_CTL_scb2_wr_data_sel_SHIFT 27
-#define BCHP_USB_CTRL_TEST_PORT_CTL_scb2_wr_data_sel_DEFAULT 0x00000000
-
-/* USB_CTRL :: TEST_PORT_CTL :: scb1_wr_data_sel [26:26] */
-#define BCHP_USB_CTRL_TEST_PORT_CTL_scb1_wr_data_sel_MASK 0x04000000
-#define BCHP_USB_CTRL_TEST_PORT_CTL_scb1_wr_data_sel_SHIFT 26
-#define BCHP_USB_CTRL_TEST_PORT_CTL_scb1_wr_data_sel_DEFAULT 0x00000000
-
-/* USB_CTRL :: TEST_PORT_CTL :: scb0_wr_data_sel [25:25] */
-#define BCHP_USB_CTRL_TEST_PORT_CTL_scb0_wr_data_sel_MASK 0x02000000
-#define BCHP_USB_CTRL_TEST_PORT_CTL_scb0_wr_data_sel_SHIFT 25
-#define BCHP_USB_CTRL_TEST_PORT_CTL_scb0_wr_data_sel_DEFAULT 0x00000000
-
-/* USB_CTRL :: TEST_PORT_CTL :: testclk_sel [24:23] */
-#define BCHP_USB_CTRL_TEST_PORT_CTL_testclk_sel_MASK 0x01800000
-#define BCHP_USB_CTRL_TEST_PORT_CTL_testclk_sel_SHIFT 23
-#define BCHP_USB_CTRL_TEST_PORT_CTL_testclk_sel_DEFAULT 0x00000000
-
-/* USB_CTRL :: TEST_PORT_CTL :: pwrflt_testsel [22:21] */
-#define BCHP_USB_CTRL_TEST_PORT_CTL_pwrflt_testsel_MASK 0x00600000
-#define BCHP_USB_CTRL_TEST_PORT_CTL_pwrflt_testsel_SHIFT 21
-#define BCHP_USB_CTRL_TEST_PORT_CTL_pwrflt_testsel_DEFAULT 0x00000000
-
-/* USB_CTRL :: TEST_PORT_CTL :: pwrflt1_oe [20:20] */
-#define BCHP_USB_CTRL_TEST_PORT_CTL_pwrflt1_oe_MASK 0x00100000
-#define BCHP_USB_CTRL_TEST_PORT_CTL_pwrflt1_oe_SHIFT 20
-#define BCHP_USB_CTRL_TEST_PORT_CTL_pwrflt1_oe_DEFAULT 0x00000000
-
-/* USB_CTRL :: TEST_PORT_CTL :: pwrflt0_oe [19:19] */
-#define BCHP_USB_CTRL_TEST_PORT_CTL_pwrflt0_oe_MASK 0x00080000
-#define BCHP_USB_CTRL_TEST_PORT_CTL_pwrflt0_oe_SHIFT 19
-#define BCHP_USB_CTRL_TEST_PORT_CTL_pwrflt0_oe_DEFAULT 0x00000000
-
-/* USB_CTRL :: TEST_PORT_CTL :: pwron1_testsel [18:18] */
-#define BCHP_USB_CTRL_TEST_PORT_CTL_pwron1_testsel_MASK 0x00040000
-#define BCHP_USB_CTRL_TEST_PORT_CTL_pwron1_testsel_SHIFT 18
-#define BCHP_USB_CTRL_TEST_PORT_CTL_pwron1_testsel_DEFAULT 0x00000000
-
-/* USB_CTRL :: TEST_PORT_CTL :: pwron0_testsel [17:17] */
-#define BCHP_USB_CTRL_TEST_PORT_CTL_pwron0_testsel_MASK 0x00020000
-#define BCHP_USB_CTRL_TEST_PORT_CTL_pwron0_testsel_SHIFT 17
-#define BCHP_USB_CTRL_TEST_PORT_CTL_pwron0_testsel_DEFAULT 0x00000000
-
-/* USB_CTRL :: TEST_PORT_CTL :: tpin_sel [16:16] */
-#define BCHP_USB_CTRL_TEST_PORT_CTL_tpin_sel_MASK 0x00010000
-#define BCHP_USB_CTRL_TEST_PORT_CTL_tpin_sel_SHIFT 16
-#define BCHP_USB_CTRL_TEST_PORT_CTL_tpin_sel_DEFAULT 0x00000000
-
-/* USB_CTRL :: TEST_PORT_CTL :: UTMI_TP_SEL [15:08] */
-#define BCHP_USB_CTRL_TEST_PORT_CTL_UTMI_TP_SEL_MASK 0x0000ff00
-#define BCHP_USB_CTRL_TEST_PORT_CTL_UTMI_TP_SEL_SHIFT 8
-#define BCHP_USB_CTRL_TEST_PORT_CTL_UTMI_TP_SEL_DEFAULT 0x00000000
-
-/* USB_CTRL :: TEST_PORT_CTL :: TPOUT_SEL [07:00] */
-#define BCHP_USB_CTRL_TEST_PORT_CTL_TPOUT_SEL_MASK 0x000000ff
-#define BCHP_USB_CTRL_TEST_PORT_CTL_TPOUT_SEL_SHIFT 0
-#define BCHP_USB_CTRL_TEST_PORT_CTL_TPOUT_SEL_DEFAULT 0x00000000
-
-/***************************************************************************
- *USB_SIMCTL - Simulation Register
- ***************************************************************************/
-/* USB_CTRL :: USB_SIMCTL :: sim_mode_en [31:31] */
-#define BCHP_USB_CTRL_USB_SIMCTL_sim_mode_en_MASK 0x80000000
-#define BCHP_USB_CTRL_USB_SIMCTL_sim_mode_en_SHIFT 31
-#define BCHP_USB_CTRL_USB_SIMCTL_sim_mode_en_DEFAULT 0x00000000
-
-/* USB_CTRL :: USB_SIMCTL :: scale_down_en [30:30] */
-#define BCHP_USB_CTRL_USB_SIMCTL_scale_down_en_MASK 0x40000000
-#define BCHP_USB_CTRL_USB_SIMCTL_scale_down_en_SHIFT 30
-#define BCHP_USB_CTRL_USB_SIMCTL_scale_down_en_DEFAULT 0x00000000
-
-/* USB_CTRL :: USB_SIMCTL :: otg_scale_down_en [29:28] */
-#define BCHP_USB_CTRL_USB_SIMCTL_otg_scale_down_en_MASK 0x30000000
-#define BCHP_USB_CTRL_USB_SIMCTL_otg_scale_down_en_SHIFT 28
-#define BCHP_USB_CTRL_USB_SIMCTL_otg_scale_down_en_DEFAULT 0x00000000
-
-/* USB_CTRL :: USB_SIMCTL :: intr_test [27:27] */
-#define BCHP_USB_CTRL_USB_SIMCTL_intr_test_MASK 0x08000000
-#define BCHP_USB_CTRL_USB_SIMCTL_intr_test_SHIFT 27
-#define BCHP_USB_CTRL_USB_SIMCTL_intr_test_DEFAULT 0x00000000
-
-/* USB_CTRL :: USB_SIMCTL :: AUTOPPD_ON_OVERCUR_EN [26:26] */
-#define BCHP_USB_CTRL_USB_SIMCTL_AUTOPPD_ON_OVERCUR_EN_MASK 0x04000000
-#define BCHP_USB_CTRL_USB_SIMCTL_AUTOPPD_ON_OVERCUR_EN_SHIFT 26
-#define BCHP_USB_CTRL_USB_SIMCTL_AUTOPPD_ON_OVERCUR_EN_DEFAULT 0x00000000
-
-/* USB_CTRL :: USB_SIMCTL :: SIMCTL_SPARE [25:05] */
-#define BCHP_USB_CTRL_USB_SIMCTL_SIMCTL_SPARE_MASK 0x03ffffe0
-#define BCHP_USB_CTRL_USB_SIMCTL_SIMCTL_SPARE_SHIFT 5
-#define BCHP_USB_CTRL_USB_SIMCTL_SIMCTL_SPARE_DEFAULT 0x00000000
-
-/* USB_CTRL :: USB_SIMCTL :: rel_270a_comp [04:04] */
-#define BCHP_USB_CTRL_USB_SIMCTL_rel_270a_comp_MASK 0x00000010
-#define BCHP_USB_CTRL_USB_SIMCTL_rel_270a_comp_SHIFT 4
-#define BCHP_USB_CTRL_USB_SIMCTL_rel_270a_comp_DEFAULT 0x00000001
-
-/* USB_CTRL :: USB_SIMCTL :: SIMCTL_SPARE1 [03:00] */
-#define BCHP_USB_CTRL_USB_SIMCTL_SIMCTL_SPARE1_MASK 0x0000000f
-#define BCHP_USB_CTRL_USB_SIMCTL_SIMCTL_SPARE1_SHIFT 0
-#define BCHP_USB_CTRL_USB_SIMCTL_SIMCTL_SPARE1_DEFAULT 0x00000000
-
-/***************************************************************************
- *USB_TESTCTL - Throutput Test Control
- ***************************************************************************/
-/* USB_CTRL :: USB_TESTCTL :: TESTCTL_SPARE2 [31:23] */
-#define BCHP_USB_CTRL_USB_TESTCTL_TESTCTL_SPARE2_MASK 0xff800000
-#define BCHP_USB_CTRL_USB_TESTCTL_TESTCTL_SPARE2_SHIFT 23
-#define BCHP_USB_CTRL_USB_TESTCTL_TESTCTL_SPARE2_DEFAULT 0x00000000
-
-/* USB_CTRL :: USB_TESTCTL :: CONTROLLER_SEL [22:21] */
-#define BCHP_USB_CTRL_USB_TESTCTL_CONTROLLER_SEL_MASK 0x00600000
-#define BCHP_USB_CTRL_USB_TESTCTL_CONTROLLER_SEL_SHIFT 21
-#define BCHP_USB_CTRL_USB_TESTCTL_CONTROLLER_SEL_DEFAULT 0x00000000
-
-/* USB_CTRL :: USB_TESTCTL :: DCNT_EN [20:20] */
-#define BCHP_USB_CTRL_USB_TESTCTL_DCNT_EN_MASK 0x00100000
-#define BCHP_USB_CTRL_USB_TESTCTL_DCNT_EN_SHIFT 20
-#define BCHP_USB_CTRL_USB_TESTCTL_DCNT_EN_DEFAULT 0x00000000
-
-/* USB_CTRL :: USB_TESTCTL :: SPEED_SEL [19:19] */
-#define BCHP_USB_CTRL_USB_TESTCTL_SPEED_SEL_MASK 0x00080000
-#define BCHP_USB_CTRL_USB_TESTCTL_SPEED_SEL_SHIFT 19
-#define BCHP_USB_CTRL_USB_TESTCTL_SPEED_SEL_DEFAULT 0x00000000
-
-/* USB_CTRL :: USB_TESTCTL :: DCNT_SEL [18:16] */
-#define BCHP_USB_CTRL_USB_TESTCTL_DCNT_SEL_MASK 0x00070000
-#define BCHP_USB_CTRL_USB_TESTCTL_DCNT_SEL_SHIFT 16
-#define BCHP_USB_CTRL_USB_TESTCTL_DCNT_SEL_DEFAULT 0x00000000
-
-/* USB_CTRL :: USB_TESTCTL :: TESTCTL_SPARE1 [15:10] */
-#define BCHP_USB_CTRL_USB_TESTCTL_TESTCTL_SPARE1_MASK 0x0000fc00
-#define BCHP_USB_CTRL_USB_TESTCTL_TESTCTL_SPARE1_SHIFT 10
-#define BCHP_USB_CTRL_USB_TESTCTL_TESTCTL_SPARE1_DEFAULT 0x00000000
-
-/* USB_CTRL :: USB_TESTCTL :: MSEC_PRESCALER [09:00] */
-#define BCHP_USB_CTRL_USB_TESTCTL_MSEC_PRESCALER_MASK 0x000003ff
-#define BCHP_USB_CTRL_USB_TESTCTL_MSEC_PRESCALER_SHIFT 0
-#define BCHP_USB_CTRL_USB_TESTCTL_MSEC_PRESCALER_DEFAULT 0x00000000
-
-/***************************************************************************
- *USB_TESTMON - Throughput Test Monitor
- ***************************************************************************/
-/* USB_CTRL :: USB_TESTMON :: TESTMON_STAT [31:00] */
-#define BCHP_USB_CTRL_USB_TESTMON_TESTMON_STAT_MASK 0xffffffff
-#define BCHP_USB_CTRL_USB_TESTMON_TESTMON_STAT_SHIFT 0
-
-/***************************************************************************
- *UTMI_CTL_1 - UTMI Control Register
- ***************************************************************************/
-/* USB_CTRL :: UTMI_CTL_1 :: USB11_TX_OEB_P1 [31:31] */
-#define BCHP_USB_CTRL_UTMI_CTL_1_USB11_TX_OEB_P1_MASK 0x80000000
-#define BCHP_USB_CTRL_UTMI_CTL_1_USB11_TX_OEB_P1_SHIFT 31
-#define BCHP_USB_CTRL_UTMI_CTL_1_USB11_TX_OEB_P1_DEFAULT 0x00000000
-
-/* USB_CTRL :: UTMI_CTL_1 :: SYNC_DET_LENG_P1 [30:28] */
-#define BCHP_USB_CTRL_UTMI_CTL_1_SYNC_DET_LENG_P1_MASK 0x70000000
-#define BCHP_USB_CTRL_UTMI_CTL_1_SYNC_DET_LENG_P1_SHIFT 28
-#define BCHP_USB_CTRL_UTMI_CTL_1_SYNC_DET_LENG_P1_DEFAULT 0x00000000
-
-/* USB_CTRL :: UTMI_CTL_1 :: POWER_UP_FSM_EN_P1 [27:27] */
-#define BCHP_USB_CTRL_UTMI_CTL_1_POWER_UP_FSM_EN_P1_MASK 0x08000000
-#define BCHP_USB_CTRL_UTMI_CTL_1_POWER_UP_FSM_EN_P1_SHIFT 27
-#define BCHP_USB_CTRL_UTMI_CTL_1_POWER_UP_FSM_EN_P1_DEFAULT 0x00000001
-
-/* USB_CTRL :: UTMI_CTL_1 :: NO_R45_CALIB_P1 [26:26] */
-#define BCHP_USB_CTRL_UTMI_CTL_1_NO_R45_CALIB_P1_MASK 0x04000000
-#define BCHP_USB_CTRL_UTMI_CTL_1_NO_R45_CALIB_P1_SHIFT 26
-#define BCHP_USB_CTRL_UTMI_CTL_1_NO_R45_CALIB_P1_DEFAULT 0x00000000
-
-/* USB_CTRL :: UTMI_CTL_1 :: BC10_ACTIVE_IDLE_PU_P1 [25:25] */
-#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_ACTIVE_IDLE_PU_P1_MASK 0x02000000
-#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_ACTIVE_IDLE_PU_P1_SHIFT 25
-#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_ACTIVE_IDLE_PU_P1_DEFAULT 0x00000000
-
-/* USB_CTRL :: UTMI_CTL_1 :: POWER_UP_FSM_SPEED_P1 [24:24] */
-#define BCHP_USB_CTRL_UTMI_CTL_1_POWER_UP_FSM_SPEED_P1_MASK 0x01000000
-#define BCHP_USB_CTRL_UTMI_CTL_1_POWER_UP_FSM_SPEED_P1_SHIFT 24
-#define BCHP_USB_CTRL_UTMI_CTL_1_POWER_UP_FSM_SPEED_P1_DEFAULT 0x00000000
-
-/* USB_CTRL :: UTMI_CTL_1 :: BC10_DM_PU_P1 [23:23] */
-#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_DM_PU_P1_MASK 0x00800000
-#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_DM_PU_P1_SHIFT 23
-#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_DM_PU_P1_DEFAULT 0x00000000
-
-/* USB_CTRL :: UTMI_CTL_1 :: BC10_DP_PU_P1 [22:22] */
-#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_DP_PU_P1_MASK 0x00400000
-#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_DP_PU_P1_SHIFT 22
-#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_DP_PU_P1_DEFAULT 0x00000000
-
-/* USB_CTRL :: UTMI_CTL_1 :: BC10_DM_PD_P1 [21:21] */
-#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_DM_PD_P1_MASK 0x00200000
-#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_DM_PD_P1_SHIFT 21
-#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_DM_PD_P1_DEFAULT 0x00000000
-
-/* USB_CTRL :: UTMI_CTL_1 :: BC10_DP_PD_P1 [20:20] */
-#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_DP_PD_P1_MASK 0x00100000
-#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_DP_PD_P1_SHIFT 20
-#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_DP_PD_P1_DEFAULT 0x00000000
-
-/* USB_CTRL :: UTMI_CTL_1 :: PHY_MODE_P1 [19:18] */
-#define BCHP_USB_CTRL_UTMI_CTL_1_PHY_MODE_P1_MASK 0x000c0000
-#define BCHP_USB_CTRL_UTMI_CTL_1_PHY_MODE_P1_SHIFT 18
-#define BCHP_USB_CTRL_UTMI_CTL_1_PHY_MODE_P1_DEFAULT 0x00000000
-
-/* USB_CTRL :: UTMI_CTL_1 :: UTMI_SOFT_RESETB_P1 [17:17] */
-#define BCHP_USB_CTRL_UTMI_CTL_1_UTMI_SOFT_RESETB_P1_MASK 0x00020000
-#define BCHP_USB_CTRL_UTMI_CTL_1_UTMI_SOFT_RESETB_P1_SHIFT 17
-#define BCHP_USB_CTRL_UTMI_CTL_1_UTMI_SOFT_RESETB_P1_DEFAULT 0x00000001
-
-/* USB_CTRL :: UTMI_CTL_1 :: AFE_NON_DRIVING_P1 [16:16] */
-#define BCHP_USB_CTRL_UTMI_CTL_1_AFE_NON_DRIVING_P1_MASK 0x00010000
-#define BCHP_USB_CTRL_UTMI_CTL_1_AFE_NON_DRIVING_P1_SHIFT 16
-#define BCHP_USB_CTRL_UTMI_CTL_1_AFE_NON_DRIVING_P1_DEFAULT 0x00000000
-
-/* USB_CTRL :: UTMI_CTL_1 :: USB11_TX_OEB [15:15] */
-#define BCHP_USB_CTRL_UTMI_CTL_1_USB11_TX_OEB_MASK 0x00008000
-#define BCHP_USB_CTRL_UTMI_CTL_1_USB11_TX_OEB_SHIFT 15
-#define BCHP_USB_CTRL_UTMI_CTL_1_USB11_TX_OEB_DEFAULT 0x00000000
-
-/* USB_CTRL :: UTMI_CTL_1 :: SYNC_DET_LENG [14:12] */
-#define BCHP_USB_CTRL_UTMI_CTL_1_SYNC_DET_LENG_MASK 0x00007000
-#define BCHP_USB_CTRL_UTMI_CTL_1_SYNC_DET_LENG_SHIFT 12
-#define BCHP_USB_CTRL_UTMI_CTL_1_SYNC_DET_LENG_DEFAULT 0x00000000
-
-/* USB_CTRL :: UTMI_CTL_1 :: POWER_UP_FSM_EN [11:11] */
-#define BCHP_USB_CTRL_UTMI_CTL_1_POWER_UP_FSM_EN_MASK 0x00000800
-#define BCHP_USB_CTRL_UTMI_CTL_1_POWER_UP_FSM_EN_SHIFT 11
-#define BCHP_USB_CTRL_UTMI_CTL_1_POWER_UP_FSM_EN_DEFAULT 0x00000001
-
-/* USB_CTRL :: UTMI_CTL_1 :: NO_R45_CALIB [10:10] */
-#define BCHP_USB_CTRL_UTMI_CTL_1_NO_R45_CALIB_MASK 0x00000400
-#define BCHP_USB_CTRL_UTMI_CTL_1_NO_R45_CALIB_SHIFT 10
-#define BCHP_USB_CTRL_UTMI_CTL_1_NO_R45_CALIB_DEFAULT 0x00000000
-
-/* USB_CTRL :: UTMI_CTL_1 :: BC10_ACTIVE_IDLE_PU [09:09] */
-#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_ACTIVE_IDLE_PU_MASK 0x00000200
-#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_ACTIVE_IDLE_PU_SHIFT 9
-#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_ACTIVE_IDLE_PU_DEFAULT 0x00000000
-
-/* USB_CTRL :: UTMI_CTL_1 :: POWER_UP_FSM_SPEED [08:08] */
-#define BCHP_USB_CTRL_UTMI_CTL_1_POWER_UP_FSM_SPEED_MASK 0x00000100
-#define BCHP_USB_CTRL_UTMI_CTL_1_POWER_UP_FSM_SPEED_SHIFT 8
-#define BCHP_USB_CTRL_UTMI_CTL_1_POWER_UP_FSM_SPEED_DEFAULT 0x00000000
-
-/* USB_CTRL :: UTMI_CTL_1 :: BC10_DM_PU [07:07] */
-#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_DM_PU_MASK 0x00000080
-#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_DM_PU_SHIFT 7
-#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_DM_PU_DEFAULT 0x00000000
-
-/* USB_CTRL :: UTMI_CTL_1 :: BC10_DP_PU [06:06] */
-#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_DP_PU_MASK 0x00000040
-#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_DP_PU_SHIFT 6
-#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_DP_PU_DEFAULT 0x00000000
-
-/* USB_CTRL :: UTMI_CTL_1 :: BC10_DM_PD [05:05] */
-#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_DM_PD_MASK 0x00000020
-#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_DM_PD_SHIFT 5
-#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_DM_PD_DEFAULT 0x00000000
-
-/* USB_CTRL :: UTMI_CTL_1 :: BC10_DP_PD [04:04] */
-#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_DP_PD_MASK 0x00000010
-#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_DP_PD_SHIFT 4
-#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_DP_PD_DEFAULT 0x00000000
-
-/* USB_CTRL :: UTMI_CTL_1 :: PHY_MODE [03:02] */
-#define BCHP_USB_CTRL_UTMI_CTL_1_PHY_MODE_MASK 0x0000000c
-#define BCHP_USB_CTRL_UTMI_CTL_1_PHY_MODE_SHIFT 2
-#define BCHP_USB_CTRL_UTMI_CTL_1_PHY_MODE_DEFAULT 0x00000000
-
-/* USB_CTRL :: UTMI_CTL_1 :: UTMI_SOFT_RESETB [01:01] */
-#define BCHP_USB_CTRL_UTMI_CTL_1_UTMI_SOFT_RESETB_MASK 0x00000002
-#define BCHP_USB_CTRL_UTMI_CTL_1_UTMI_SOFT_RESETB_SHIFT 1
-#define BCHP_USB_CTRL_UTMI_CTL_1_UTMI_SOFT_RESETB_DEFAULT 0x00000001
-
-/* USB_CTRL :: UTMI_CTL_1 :: AFE_NON_DRIVING [00:00] */
-#define BCHP_USB_CTRL_UTMI_CTL_1_AFE_NON_DRIVING_MASK 0x00000001
-#define BCHP_USB_CTRL_UTMI_CTL_1_AFE_NON_DRIVING_SHIFT 0
-#define BCHP_USB_CTRL_UTMI_CTL_1_AFE_NON_DRIVING_DEFAULT 0x00000000
-
-/***************************************************************************
- *UTMI_CTL_2 - UTMI Control 2 Register
- ***************************************************************************/
-/* USB_CTRL :: UTMI_CTL_2 :: UTMICTL2_SPARE [31:00] */
-#define BCHP_USB_CTRL_UTMI_CTL_2_UTMICTL2_SPARE_MASK 0xffffffff
-#define BCHP_USB_CTRL_UTMI_CTL_2_UTMICTL2_SPARE_SHIFT 0
-#define BCHP_USB_CTRL_UTMI_CTL_2_UTMICTL2_SPARE_DEFAULT 0x00000000
-
-/***************************************************************************
- *USB_PM - Power Management Register
- ***************************************************************************/
-/* USB_CTRL :: USB_PM :: ehci_rmtwkup_override [31:31] */
-#define BCHP_USB_CTRL_USB_PM_ehci_rmtwkup_override_MASK 0x80000000
-#define BCHP_USB_CTRL_USB_PM_ehci_rmtwkup_override_SHIFT 31
-#define BCHP_USB_CTRL_USB_PM_ehci_rmtwkup_override_DEFAULT 0x00000000
-
-/* USB_CTRL :: USB_PM :: ohci_rmtwkup_override [30:30] */
-#define BCHP_USB_CTRL_USB_PM_ohci_rmtwkup_override_MASK 0x40000000
-#define BCHP_USB_CTRL_USB_PM_ohci_rmtwkup_override_SHIFT 30
-#define BCHP_USB_CTRL_USB_PM_ohci_rmtwkup_override_DEFAULT 0x00000000
-
-/* USB_CTRL :: USB_PM :: USB_PM_SPARE [29:05] */
-#define BCHP_USB_CTRL_USB_PM_USB_PM_SPARE_MASK 0x3fffffe0
-#define BCHP_USB_CTRL_USB_PM_USB_PM_SPARE_SHIFT 5
-#define BCHP_USB_CTRL_USB_PM_USB_PM_SPARE_DEFAULT 0x00000000
-
-/* USB_CTRL :: USB_PM :: xhc_pme_en [04:04] */
-#define BCHP_USB_CTRL_USB_PM_xhc_pme_en_MASK 0x00000010
-#define BCHP_USB_CTRL_USB_PM_xhc_pme_en_SHIFT 4
-#define BCHP_USB_CTRL_USB_PM_xhc_pme_en_DEFAULT 0x00000000
-
-/* USB_CTRL :: USB_PM :: S2_discon_intr_en [03:03] */
-#define BCHP_USB_CTRL_USB_PM_S2_discon_intr_en_MASK 0x00000008
-#define BCHP_USB_CTRL_USB_PM_S2_discon_intr_en_SHIFT 3
-#define BCHP_USB_CTRL_USB_PM_S2_discon_intr_en_DEFAULT 0x00000000
-
-/* USB_CTRL :: USB_PM :: S0_discon_intr_en [02:02] */
-#define BCHP_USB_CTRL_USB_PM_S0_discon_intr_en_MASK 0x00000004
-#define BCHP_USB_CTRL_USB_PM_S0_discon_intr_en_SHIFT 2
-#define BCHP_USB_CTRL_USB_PM_S0_discon_intr_en_DEFAULT 0x00000000
-
-/* USB_CTRL :: USB_PM :: con_intr_en [01:01] */
-#define BCHP_USB_CTRL_USB_PM_con_intr_en_MASK 0x00000002
-#define BCHP_USB_CTRL_USB_PM_con_intr_en_SHIFT 1
-#define BCHP_USB_CTRL_USB_PM_con_intr_en_DEFAULT 0x00000000
-
-/* USB_CTRL :: USB_PM :: rmtwkup_en [00:00] */
-#define BCHP_USB_CTRL_USB_PM_rmtwkup_en_MASK 0x00000001
-#define BCHP_USB_CTRL_USB_PM_rmtwkup_en_SHIFT 0
-#define BCHP_USB_CTRL_USB_PM_rmtwkup_en_DEFAULT 0x00000000
-
-/***************************************************************************
- *OHCI_ADDR_EXT - OHCI ADDRESS Extension
- ***************************************************************************/
-/* USB_CTRL :: OHCI_ADDR_EXT :: OHCI_ADDR_SPARE [31:08] */
-#define BCHP_USB_CTRL_OHCI_ADDR_EXT_OHCI_ADDR_SPARE_MASK 0xffffff00
-#define BCHP_USB_CTRL_OHCI_ADDR_EXT_OHCI_ADDR_SPARE_SHIFT 8
-#define BCHP_USB_CTRL_OHCI_ADDR_EXT_OHCI_ADDR_SPARE_DEFAULT 0x00000000
-
-/* USB_CTRL :: OHCI_ADDR_EXT :: OHCI_ADDR_EXT [07:00] */
-#define BCHP_USB_CTRL_OHCI_ADDR_EXT_OHCI_ADDR_EXT_MASK 0x000000ff
-#define BCHP_USB_CTRL_OHCI_ADDR_EXT_OHCI_ADDR_EXT_SHIFT 0
-#define BCHP_USB_CTRL_OHCI_ADDR_EXT_OHCI_ADDR_EXT_DEFAULT 0x00000000
-
-/***************************************************************************
- *USB_PM_STATUS - usb20 Power Management Status
- ***************************************************************************/
-/* USB_CTRL :: USB_PM_STATUS :: SPARE1_BITS [31:08] */
-#define BCHP_USB_CTRL_USB_PM_STATUS_SPARE1_BITS_MASK 0xffffff00
-#define BCHP_USB_CTRL_USB_PM_STATUS_SPARE1_BITS_SHIFT 8
-#define BCHP_USB_CTRL_USB_PM_STATUS_SPARE1_BITS_DEFAULT 0x00000000
-
-/* USB_CTRL :: USB_PM_STATUS :: PM_STATUS [07:00] */
-#define BCHP_USB_CTRL_USB_PM_STATUS_PM_STATUS_MASK 0x000000ff
-#define BCHP_USB_CTRL_USB_PM_STATUS_PM_STATUS_SHIFT 0
-
-/***************************************************************************
- *PLL_LDO_CTL - 28NM USBPHY LDO Control
- ***************************************************************************/
-/* USB_CTRL :: PLL_LDO_CTL :: AFE_PLL_LDO_CNTL [31:16] */
-#define BCHP_USB_CTRL_PLL_LDO_CTL_AFE_PLL_LDO_CNTL_MASK 0xffff0000
-#define BCHP_USB_CTRL_PLL_LDO_CTL_AFE_PLL_LDO_CNTL_SHIFT 16
-#define BCHP_USB_CTRL_PLL_LDO_CTL_AFE_PLL_LDO_CNTL_DEFAULT 0x00000000
-
-/* USB_CTRL :: PLL_LDO_CTL :: DFE_LDO_CNTL [15:12] */
-#define BCHP_USB_CTRL_PLL_LDO_CTL_DFE_LDO_CNTL_MASK 0x0000f000
-#define BCHP_USB_CTRL_PLL_LDO_CTL_DFE_LDO_CNTL_SHIFT 12
-#define BCHP_USB_CTRL_PLL_LDO_CTL_DFE_LDO_CNTL_DEFAULT 0x00000000
-
-/* USB_CTRL :: PLL_LDO_CTL :: AFE_LDO_CNTL [11:08] */
-#define BCHP_USB_CTRL_PLL_LDO_CTL_AFE_LDO_CNTL_MASK 0x00000f00
-#define BCHP_USB_CTRL_PLL_LDO_CTL_AFE_LDO_CNTL_SHIFT 8
-#define BCHP_USB_CTRL_PLL_LDO_CTL_AFE_LDO_CNTL_DEFAULT 0x00000000
-
-/* USB_CTRL :: PLL_LDO_CTL :: AFE_LDO_SPARE [07:03] */
-#define BCHP_USB_CTRL_PLL_LDO_CTL_AFE_LDO_SPARE_MASK 0x000000f8
-#define BCHP_USB_CTRL_PLL_LDO_CTL_AFE_LDO_SPARE_SHIFT 3
-#define BCHP_USB_CTRL_PLL_LDO_CTL_AFE_LDO_SPARE_DEFAULT 0x00000000
-
-/* USB_CTRL :: PLL_LDO_CTL :: AFE_CORERDY_VDDC [02:02] */
-#define BCHP_USB_CTRL_PLL_LDO_CTL_AFE_CORERDY_VDDC_MASK 0x00000004
-#define BCHP_USB_CTRL_PLL_LDO_CTL_AFE_CORERDY_VDDC_SHIFT 2
-#define BCHP_USB_CTRL_PLL_LDO_CTL_AFE_CORERDY_VDDC_DEFAULT 0x00000001
-
-/* USB_CTRL :: PLL_LDO_CTL :: AFE_LDO_PWRDWNB [01:01] */
-#define BCHP_USB_CTRL_PLL_LDO_CTL_AFE_LDO_PWRDWNB_MASK 0x00000002
-#define BCHP_USB_CTRL_PLL_LDO_CTL_AFE_LDO_PWRDWNB_SHIFT 1
-#define BCHP_USB_CTRL_PLL_LDO_CTL_AFE_LDO_PWRDWNB_DEFAULT 0x00000001
-
-/* USB_CTRL :: PLL_LDO_CTL :: AFE_BG_PWRDWNB [00:00] */
-#define BCHP_USB_CTRL_PLL_LDO_CTL_AFE_BG_PWRDWNB_MASK 0x00000001
-#define BCHP_USB_CTRL_PLL_LDO_CTL_AFE_BG_PWRDWNB_SHIFT 0
-#define BCHP_USB_CTRL_PLL_LDO_CTL_AFE_BG_PWRDWNB_DEFAULT 0x00000001
-
-/***************************************************************************
- *PLL_LDO_PLLBIAS - 28NM USBPHY PLLBIAS Control
- ***************************************************************************/
-/* USB_CTRL :: PLL_LDO_PLLBIAS :: PLLBIAS_SPARE [31:18] */
-#define BCHP_USB_CTRL_PLL_LDO_PLLBIAS_PLLBIAS_SPARE_MASK 0xfffc0000
-#define BCHP_USB_CTRL_PLL_LDO_PLLBIAS_PLLBIAS_SPARE_SHIFT 18
-#define BCHP_USB_CTRL_PLL_LDO_PLLBIAS_PLLBIAS_SPARE_DEFAULT 0x00000000
-
-/* USB_CTRL :: PLL_LDO_PLLBIAS :: AFE_PLLBIAS_TESTMODE [17:00] */
-#define BCHP_USB_CTRL_PLL_LDO_PLLBIAS_AFE_PLLBIAS_TESTMODE_MASK 0x0003ffff
-#define BCHP_USB_CTRL_PLL_LDO_PLLBIAS_AFE_PLLBIAS_TESTMODE_SHIFT 0
-#define BCHP_USB_CTRL_PLL_LDO_PLLBIAS_AFE_PLLBIAS_TESTMODE_DEFAULT 0x00000000
-
-/***************************************************************************
- *PLL_AFE_BG_CNTL - 28NM USBPHY AFE Bandgap Control
- ***************************************************************************/
-/* USB_CTRL :: PLL_AFE_BG_CNTL :: PLL_AFE_BG_SPARE [31:17] */
-#define BCHP_USB_CTRL_PLL_AFE_BG_CNTL_PLL_AFE_BG_SPARE_MASK 0xfffe0000
-#define BCHP_USB_CTRL_PLL_AFE_BG_CNTL_PLL_AFE_BG_SPARE_SHIFT 17
-#define BCHP_USB_CTRL_PLL_AFE_BG_CNTL_PLL_AFE_BG_SPARE_DEFAULT 0x00000000
-
-/* USB_CTRL :: PLL_AFE_BG_CNTL :: AFE_BG_PRGM [16:12] */
-#define BCHP_USB_CTRL_PLL_AFE_BG_CNTL_AFE_BG_PRGM_MASK 0x0001f000
-#define BCHP_USB_CTRL_PLL_AFE_BG_CNTL_AFE_BG_PRGM_SHIFT 12
-#define BCHP_USB_CTRL_PLL_AFE_BG_CNTL_AFE_BG_PRGM_DEFAULT 0x00000000
-
-/* USB_CTRL :: PLL_AFE_BG_CNTL :: AFE_BG_VREF0P7_AFE_PRGM [11:08] */
-#define BCHP_USB_CTRL_PLL_AFE_BG_CNTL_AFE_BG_VREF0P7_AFE_PRGM_MASK 0x00000f00
-#define BCHP_USB_CTRL_PLL_AFE_BG_CNTL_AFE_BG_VREF0P7_AFE_PRGM_SHIFT 8
-#define BCHP_USB_CTRL_PLL_AFE_BG_CNTL_AFE_BG_VREF0P7_AFE_PRGM_DEFAULT 0x00000000
-
-/* USB_CTRL :: PLL_AFE_BG_CNTL :: AFE_BG_VREF0P7_DFE_PRGM [07:04] */
-#define BCHP_USB_CTRL_PLL_AFE_BG_CNTL_AFE_BG_VREF0P7_DFE_PRGM_MASK 0x000000f0
-#define BCHP_USB_CTRL_PLL_AFE_BG_CNTL_AFE_BG_VREF0P7_DFE_PRGM_SHIFT 4
-#define BCHP_USB_CTRL_PLL_AFE_BG_CNTL_AFE_BG_VREF0P7_DFE_PRGM_DEFAULT 0x00000000
-
-/* USB_CTRL :: PLL_AFE_BG_CNTL :: AFE_BG_VREF1P0_TRIM [03:00] */
-#define BCHP_USB_CTRL_PLL_AFE_BG_CNTL_AFE_BG_VREF1P0_TRIM_MASK 0x0000000f
-#define BCHP_USB_CTRL_PLL_AFE_BG_CNTL_AFE_BG_VREF1P0_TRIM_SHIFT 0
-#define BCHP_USB_CTRL_PLL_AFE_BG_CNTL_AFE_BG_VREF1P0_TRIM_DEFAULT 0x00000000
-
-/***************************************************************************
- *AFE_USBIO_TST - 28NM USBPHY AFE Bandgap Control
- ***************************************************************************/
-/* USB_CTRL :: AFE_USBIO_TST :: ANALOG_TESTMODE [31:31] */
-#define BCHP_USB_CTRL_AFE_USBIO_TST_ANALOG_TESTMODE_MASK 0x80000000
-#define BCHP_USB_CTRL_AFE_USBIO_TST_ANALOG_TESTMODE_SHIFT 31
-#define BCHP_USB_CTRL_AFE_USBIO_TST_ANALOG_TESTMODE_DEFAULT 0x00000000
-
-/* USB_CTRL :: AFE_USBIO_TST :: PHY_ISO [30:30] */
-#define BCHP_USB_CTRL_AFE_USBIO_TST_PHY_ISO_MASK 0x40000000
-#define BCHP_USB_CTRL_AFE_USBIO_TST_PHY_ISO_SHIFT 30
-#define BCHP_USB_CTRL_AFE_USBIO_TST_PHY_ISO_DEFAULT 0x00000000
-
-/* USB_CTRL :: AFE_USBIO_TST :: AFE_USBIO_TST_SPARE [29:16] */
-#define BCHP_USB_CTRL_AFE_USBIO_TST_AFE_USBIO_TST_SPARE_MASK 0x3fff0000
-#define BCHP_USB_CTRL_AFE_USBIO_TST_AFE_USBIO_TST_SPARE_SHIFT 16
-#define BCHP_USB_CTRL_AFE_USBIO_TST_AFE_USBIO_TST_SPARE_DEFAULT 0x00000000
-
-/* USB_CTRL :: AFE_USBIO_TST :: AFE_USBIO_TST_P2 [15:08] */
-#define BCHP_USB_CTRL_AFE_USBIO_TST_AFE_USBIO_TST_P2_MASK 0x0000ff00
-#define BCHP_USB_CTRL_AFE_USBIO_TST_AFE_USBIO_TST_P2_SHIFT 8
-#define BCHP_USB_CTRL_AFE_USBIO_TST_AFE_USBIO_TST_P2_DEFAULT 0x00000000
-
-/* USB_CTRL :: AFE_USBIO_TST :: AFE_USBIO_TST_P1 [07:00] */
-#define BCHP_USB_CTRL_AFE_USBIO_TST_AFE_USBIO_TST_P1_MASK 0x000000ff
-#define BCHP_USB_CTRL_AFE_USBIO_TST_AFE_USBIO_TST_P1_SHIFT 0
-#define BCHP_USB_CTRL_AFE_USBIO_TST_AFE_USBIO_TST_P1_DEFAULT 0x00000000
-
-/***************************************************************************
- *PLL_NDIV_FRAC - PLL Feedback Divider Control Register
- ***************************************************************************/
-/* USB_CTRL :: PLL_NDIV_FRAC :: PLL_NDIV_FRAC_SPARE2 [31:20] */
-#define BCHP_USB_CTRL_PLL_NDIV_FRAC_PLL_NDIV_FRAC_SPARE2_MASK 0xfff00000
-#define BCHP_USB_CTRL_PLL_NDIV_FRAC_PLL_NDIV_FRAC_SPARE2_SHIFT 20
-#define BCHP_USB_CTRL_PLL_NDIV_FRAC_PLL_NDIV_FRAC_SPARE2_DEFAULT 0x00000000
-
-/* USB_CTRL :: PLL_NDIV_FRAC :: pll_ndiv_frac [19:00] */
-#define BCHP_USB_CTRL_PLL_NDIV_FRAC_pll_ndiv_frac_MASK 0x000fffff
-#define BCHP_USB_CTRL_PLL_NDIV_FRAC_pll_ndiv_frac_SHIFT 0
-#define BCHP_USB_CTRL_PLL_NDIV_FRAC_pll_ndiv_frac_DEFAULT 0x00000000
-
-/***************************************************************************
- *SPARE2 - Spare2 Register for future use
- ***************************************************************************/
-/* USB_CTRL :: SPARE2 :: SPARE2_BITS [31:00] */
-#define BCHP_USB_CTRL_SPARE2_SPARE2_BITS_MASK 0xffffffff
-#define BCHP_USB_CTRL_SPARE2_SPARE2_BITS_SHIFT 0
-#define BCHP_USB_CTRL_SPARE2_SPARE2_BITS_DEFAULT 0x00000000
-
-/***************************************************************************
- *SPARE3 - Spare1 Register for future use
- ***************************************************************************/
-/* USB_CTRL :: SPARE3 :: SPARE3_BITS [31:00] */
-#define BCHP_USB_CTRL_SPARE3_SPARE3_BITS_MASK 0xffffffff
-#define BCHP_USB_CTRL_SPARE3_SPARE3_BITS_SHIFT 0
-#define BCHP_USB_CTRL_SPARE3_SPARE3_BITS_DEFAULT 0x00000000
-
-/***************************************************************************
- *SPARE4 - Spare1 Register for future use
- ***************************************************************************/
-/* USB_CTRL :: SPARE4 :: SPARE4_BITS [31:00] */
-#define BCHP_USB_CTRL_SPARE4_SPARE4_BITS_MASK 0xffffffff
-#define BCHP_USB_CTRL_SPARE4_SPARE4_BITS_SHIFT 0
-#define BCHP_USB_CTRL_SPARE4_SPARE4_BITS_DEFAULT 0x00000000
-
-/***************************************************************************
- *USB30_CTL1 - USB30 CONTROL Register 1
- ***************************************************************************/
-/* USB_CTRL :: USB30_CTL1 :: usb3_oc_dis [31:30] */
-#define BCHP_USB_CTRL_USB30_CTL1_usb3_oc_dis_MASK 0xc0000000
-#define BCHP_USB_CTRL_USB30_CTL1_usb3_oc_dis_SHIFT 30
-#define BCHP_USB_CTRL_USB30_CTL1_usb3_oc_dis_DEFAULT 0x00000000
-
-/* USB_CTRL :: USB30_CTL1 :: usb3_ipp [29:29] */
-#define BCHP_USB_CTRL_USB30_CTL1_usb3_ipp_MASK 0x20000000
-#define BCHP_USB_CTRL_USB30_CTL1_usb3_ipp_SHIFT 29
-#define BCHP_USB_CTRL_USB30_CTL1_usb3_ipp_DEFAULT 0x00000000
-
-/* USB_CTRL :: USB30_CTL1 :: usb3_ioc [28:28] */
-#define BCHP_USB_CTRL_USB30_CTL1_usb3_ioc_MASK 0x10000000
-#define BCHP_USB_CTRL_USB30_CTL1_usb3_ioc_SHIFT 28
-#define BCHP_USB_CTRL_USB30_CTL1_usb3_ioc_DEFAULT 0x00000000
-
-/* USB_CTRL :: USB30_CTL1 :: usb3_pwron_sel [27:26] */
-#define BCHP_USB_CTRL_USB30_CTL1_usb3_pwron_sel_MASK 0x0c000000
-#define BCHP_USB_CTRL_USB30_CTL1_usb3_pwron_sel_SHIFT 26
-#define BCHP_USB_CTRL_USB30_CTL1_usb3_pwron_sel_DEFAULT 0x00000000
-
-/* USB_CTRL :: USB30_CTL1 :: usb3_pwron_force [25:25] */
-#define BCHP_USB_CTRL_USB30_CTL1_usb3_pwron_force_MASK 0x02000000
-#define BCHP_USB_CTRL_USB30_CTL1_usb3_pwron_force_SHIFT 25
-#define BCHP_USB_CTRL_USB30_CTL1_usb3_pwron_force_DEFAULT 0x00000000
-
-/* USB_CTRL :: USB30_CTL1 :: usb3_pwron_force_val [24:24] */
-#define BCHP_USB_CTRL_USB30_CTL1_usb3_pwron_force_val_MASK 0x01000000
-#define BCHP_USB_CTRL_USB30_CTL1_usb3_pwron_force_val_SHIFT 24
-#define BCHP_USB_CTRL_USB30_CTL1_usb3_pwron_force_val_DEFAULT 0x00000000
-
-/* USB_CTRL :: USB30_CTL1 :: usb30_ctl1_spare2 [23:20] */
-#define BCHP_USB_CTRL_USB30_CTL1_usb30_ctl1_spare2_MASK 0x00f00000
-#define BCHP_USB_CTRL_USB30_CTL1_usb30_ctl1_spare2_SHIFT 20
-#define BCHP_USB_CTRL_USB30_CTL1_usb30_ctl1_spare2_DEFAULT 0x00000000
-
-/* USB_CTRL :: USB30_CTL1 :: mdio_resetb [19:19] */
-#define BCHP_USB_CTRL_USB30_CTL1_mdio_resetb_MASK 0x00080000
-#define BCHP_USB_CTRL_USB30_CTL1_mdio_resetb_SHIFT 19
-#define BCHP_USB_CTRL_USB30_CTL1_mdio_resetb_DEFAULT 0x00000001
-
-/* USB_CTRL :: USB30_CTL1 :: aux_resetb [18:18] */
-#define BCHP_USB_CTRL_USB30_CTL1_aux_resetb_MASK 0x00040000
-#define BCHP_USB_CTRL_USB30_CTL1_aux_resetb_SHIFT 18
-#define BCHP_USB_CTRL_USB30_CTL1_aux_resetb_DEFAULT 0x00000000
-
-/* USB_CTRL :: USB30_CTL1 :: xhc_soft_resetb [17:17] */
-#define BCHP_USB_CTRL_USB30_CTL1_xhc_soft_resetb_MASK 0x00020000
-#define BCHP_USB_CTRL_USB30_CTL1_xhc_soft_resetb_SHIFT 17
-#define BCHP_USB_CTRL_USB30_CTL1_xhc_soft_resetb_DEFAULT 0x00000000
-
-/* USB_CTRL :: USB30_CTL1 :: phy3_resetb [16:16] */
-#define BCHP_USB_CTRL_USB30_CTL1_phy3_resetb_MASK 0x00010000
-#define BCHP_USB_CTRL_USB30_CTL1_phy3_resetb_SHIFT 16
-#define BCHP_USB_CTRL_USB30_CTL1_phy3_resetb_DEFAULT 0x00000001
-
-/* USB_CTRL :: USB30_CTL1 :: usb30_ctl1_spare1 [15:07] */
-#define BCHP_USB_CTRL_USB30_CTL1_usb30_ctl1_spare1_MASK 0x0000ff80
-#define BCHP_USB_CTRL_USB30_CTL1_usb30_ctl1_spare1_SHIFT 7
-#define BCHP_USB_CTRL_USB30_CTL1_usb30_ctl1_spare1_DEFAULT 0x00000000
-
-/* USB_CTRL :: USB30_CTL1 :: phy3_standalonemode [06:06] */
-#define BCHP_USB_CTRL_USB30_CTL1_phy3_standalonemode_MASK 0x00000040
-#define BCHP_USB_CTRL_USB30_CTL1_phy3_standalonemode_SHIFT 6
-#define BCHP_USB_CTRL_USB30_CTL1_phy3_standalonemode_DEFAULT 0x00000000
-
-/* USB_CTRL :: USB30_CTL1 :: phy3_phy_iso [05:05] */
-#define BCHP_USB_CTRL_USB30_CTL1_phy3_phy_iso_MASK 0x00000020
-#define BCHP_USB_CTRL_USB30_CTL1_phy3_phy_iso_SHIFT 5
-#define BCHP_USB_CTRL_USB30_CTL1_phy3_phy_iso_DEFAULT 0x00000000
-
-/* USB_CTRL :: USB30_CTL1 :: phy3_pll_seq_start [04:04] */
-#define BCHP_USB_CTRL_USB30_CTL1_phy3_pll_seq_start_MASK 0x00000010
-#define BCHP_USB_CTRL_USB30_CTL1_phy3_pll_seq_start_SHIFT 4
-#define BCHP_USB_CTRL_USB30_CTL1_phy3_pll_seq_start_DEFAULT 0x00000000
-
-/* USB_CTRL :: USB30_CTL1 :: phy3_pll_refclk_sel [03:01] */
-#define BCHP_USB_CTRL_USB30_CTL1_phy3_pll_refclk_sel_MASK 0x0000000e
-#define BCHP_USB_CTRL_USB30_CTL1_phy3_pll_refclk_sel_SHIFT 1
-#define BCHP_USB_CTRL_USB30_CTL1_phy3_pll_refclk_sel_DEFAULT 0x00000004
-
-/* USB_CTRL :: USB30_CTL1 :: phy3_pll_auxclk_sel [00:00] */
-#define BCHP_USB_CTRL_USB30_CTL1_phy3_pll_auxclk_sel_MASK 0x00000001
-#define BCHP_USB_CTRL_USB30_CTL1_phy3_pll_auxclk_sel_SHIFT 0
-#define BCHP_USB_CTRL_USB30_CTL1_phy3_pll_auxclk_sel_DEFAULT 0x00000000
-
-/***************************************************************************
- *USB30_CTL2 - USB30 CONTROL Register 2
- ***************************************************************************/
-/* USB_CTRL :: USB30_CTL2 :: usb30_ctl2_spare2 [31:30] */
-#define BCHP_USB_CTRL_USB30_CTL2_usb30_ctl2_spare2_MASK 0xc0000000
-#define BCHP_USB_CTRL_USB30_CTL2_usb30_ctl2_spare2_SHIFT 30
-#define BCHP_USB_CTRL_USB30_CTL2_usb30_ctl2_spare2_DEFAULT 0x00000000
-
-/* USB_CTRL :: USB30_CTL2 :: xhci_max_scb_size [29:24] */
-#define BCHP_USB_CTRL_USB30_CTL2_xhci_max_scb_size_MASK 0x3f000000
-#define BCHP_USB_CTRL_USB30_CTL2_xhci_max_scb_size_SHIFT 24
-#define BCHP_USB_CTRL_USB30_CTL2_xhci_max_scb_size_DEFAULT 0x00000020
-
-/* USB_CTRL :: USB30_CTL2 :: xhci_wrfifo_thrshld [23:16] */
-#define BCHP_USB_CTRL_USB30_CTL2_xhci_wrfifo_thrshld_MASK 0x00ff0000
-#define BCHP_USB_CTRL_USB30_CTL2_xhci_wrfifo_thrshld_SHIFT 16
-#define BCHP_USB_CTRL_USB30_CTL2_xhci_wrfifo_thrshld_DEFAULT 0x00000000
-
-/* USB_CTRL :: USB30_CTL2 :: xhci_rdfifo_thrshld [15:08] */
-#define BCHP_USB_CTRL_USB30_CTL2_xhci_rdfifo_thrshld_MASK 0x0000ff00
-#define BCHP_USB_CTRL_USB30_CTL2_xhci_rdfifo_thrshld_SHIFT 8
-#define BCHP_USB_CTRL_USB30_CTL2_xhci_rdfifo_thrshld_DEFAULT 0x00000000
-
-/* USB_CTRL :: USB30_CTL2 :: usb30_ctl2_spare1 [07:03] */
-#define BCHP_USB_CTRL_USB30_CTL2_usb30_ctl2_spare1_MASK 0x000000f8
-#define BCHP_USB_CTRL_USB30_CTL2_usb30_ctl2_spare1_SHIFT 3
-#define BCHP_USB_CTRL_USB30_CTL2_usb30_ctl2_spare1_DEFAULT 0x00000000
-
-/* USB_CTRL :: USB30_CTL2 :: xhci_cntl_client_en [02:02] */
-#define BCHP_USB_CTRL_USB30_CTL2_xhci_cntl_client_en_MASK 0x00000004
-#define BCHP_USB_CTRL_USB30_CTL2_xhci_cntl_client_en_SHIFT 2
-#define BCHP_USB_CTRL_USB30_CTL2_xhci_cntl_client_en_DEFAULT 0x00000001
-
-/* USB_CTRL :: USB30_CTL2 :: xhci_swap_mode [01:00] */
-#define BCHP_USB_CTRL_USB30_CTL2_xhci_swap_mode_MASK 0x00000003
-#define BCHP_USB_CTRL_USB30_CTL2_xhci_swap_mode_SHIFT 0
-#define BCHP_USB_CTRL_USB30_CTL2_xhci_swap_mode_DEFAULT 0x00000000
-
-/***************************************************************************
- *USB30_CTL3 - USB30 CONTROL Register 3
- ***************************************************************************/
-/* USB_CTRL :: USB30_CTL3 :: usb30_ctl3_spare2 [31:30] */
-#define BCHP_USB_CTRL_USB30_CTL3_usb30_ctl3_spare2_MASK 0xc0000000
-#define BCHP_USB_CTRL_USB30_CTL3_usb30_ctl3_spare2_SHIFT 30
-#define BCHP_USB_CTRL_USB30_CTL3_usb30_ctl3_spare2_DEFAULT 0x00000000
-
-/* USB_CTRL :: USB30_CTL3 :: phy3_pipe_txdeemph_en_p1 [29:29] */
-#define BCHP_USB_CTRL_USB30_CTL3_phy3_pipe_txdeemph_en_p1_MASK 0x20000000
-#define BCHP_USB_CTRL_USB30_CTL3_phy3_pipe_txdeemph_en_p1_SHIFT 29
-#define BCHP_USB_CTRL_USB30_CTL3_phy3_pipe_txdeemph_en_p1_DEFAULT 0x00000000
-
-/* USB_CTRL :: USB30_CTL3 :: phy3_pipe_txdeemph_p1 [28:24] */
-#define BCHP_USB_CTRL_USB30_CTL3_phy3_pipe_txdeemph_p1_MASK 0x1f000000
-#define BCHP_USB_CTRL_USB30_CTL3_phy3_pipe_txdeemph_p1_SHIFT 24
-#define BCHP_USB_CTRL_USB30_CTL3_phy3_pipe_txdeemph_p1_DEFAULT 0x00000009
-
-/* USB_CTRL :: USB30_CTL3 :: phy3_pipe_txmargin_p1 [23:20] */
-#define BCHP_USB_CTRL_USB30_CTL3_phy3_pipe_txmargin_p1_MASK 0x00f00000
-#define BCHP_USB_CTRL_USB30_CTL3_phy3_pipe_txmargin_p1_SHIFT 20
-#define BCHP_USB_CTRL_USB30_CTL3_phy3_pipe_txmargin_p1_DEFAULT 0x00000007
-
-/* USB_CTRL :: USB30_CTL3 :: phy3_rxebufmode_p1 [19:19] */
-#define BCHP_USB_CTRL_USB30_CTL3_phy3_rxebufmode_p1_MASK 0x00080000
-#define BCHP_USB_CTRL_USB30_CTL3_phy3_rxebufmode_p1_SHIFT 19
-#define BCHP_USB_CTRL_USB30_CTL3_phy3_rxebufmode_p1_DEFAULT 0x00000000
-
-/* USB_CTRL :: USB30_CTL3 :: phy3_pipe_txmargin_en_p1 [18:18] */
-#define BCHP_USB_CTRL_USB30_CTL3_phy3_pipe_txmargin_en_p1_MASK 0x00040000
-#define BCHP_USB_CTRL_USB30_CTL3_phy3_pipe_txmargin_en_p1_SHIFT 18
-#define BCHP_USB_CTRL_USB30_CTL3_phy3_pipe_txmargin_en_p1_DEFAULT 0x00000000
-
-/* USB_CTRL :: USB30_CTL3 :: phy3_pipe_txswing_p1 [17:17] */
-#define BCHP_USB_CTRL_USB30_CTL3_phy3_pipe_txswing_p1_MASK 0x00020000
-#define BCHP_USB_CTRL_USB30_CTL3_phy3_pipe_txswing_p1_SHIFT 17
-#define BCHP_USB_CTRL_USB30_CTL3_phy3_pipe_txswing_p1_DEFAULT 0x00000000
-
-/* USB_CTRL :: USB30_CTL3 :: phy3_mode_p1 [16:16] */
-#define BCHP_USB_CTRL_USB30_CTL3_phy3_mode_p1_MASK 0x00010000
-#define BCHP_USB_CTRL_USB30_CTL3_phy3_mode_p1_SHIFT 16
-#define BCHP_USB_CTRL_USB30_CTL3_phy3_mode_p1_DEFAULT 0x00000001
-
-/* USB_CTRL :: USB30_CTL3 :: usb30_ctl3_spare1 [15:14] */
-#define BCHP_USB_CTRL_USB30_CTL3_usb30_ctl3_spare1_MASK 0x0000c000
-#define BCHP_USB_CTRL_USB30_CTL3_usb30_ctl3_spare1_SHIFT 14
-#define BCHP_USB_CTRL_USB30_CTL3_usb30_ctl3_spare1_DEFAULT 0x00000000
-
-/* USB_CTRL :: USB30_CTL3 :: phy3_pipe_txdeemph_en [13:13] */
-#define BCHP_USB_CTRL_USB30_CTL3_phy3_pipe_txdeemph_en_MASK 0x00002000
-#define BCHP_USB_CTRL_USB30_CTL3_phy3_pipe_txdeemph_en_SHIFT 13
-#define BCHP_USB_CTRL_USB30_CTL3_phy3_pipe_txdeemph_en_DEFAULT 0x00000000
-
-/* USB_CTRL :: USB30_CTL3 :: phy3_pipe_txdeemph [12:08] */
-#define BCHP_USB_CTRL_USB30_CTL3_phy3_pipe_txdeemph_MASK 0x00001f00
-#define BCHP_USB_CTRL_USB30_CTL3_phy3_pipe_txdeemph_SHIFT 8
-#define BCHP_USB_CTRL_USB30_CTL3_phy3_pipe_txdeemph_DEFAULT 0x00000009
-
-/* USB_CTRL :: USB30_CTL3 :: phy3_pipe_txmargin [07:04] */
-#define BCHP_USB_CTRL_USB30_CTL3_phy3_pipe_txmargin_MASK 0x000000f0
-#define BCHP_USB_CTRL_USB30_CTL3_phy3_pipe_txmargin_SHIFT 4
-#define BCHP_USB_CTRL_USB30_CTL3_phy3_pipe_txmargin_DEFAULT 0x00000007
-
-/* USB_CTRL :: USB30_CTL3 :: phy3_rxebufmode [03:03] */
-#define BCHP_USB_CTRL_USB30_CTL3_phy3_rxebufmode_MASK 0x00000008
-#define BCHP_USB_CTRL_USB30_CTL3_phy3_rxebufmode_SHIFT 3
-#define BCHP_USB_CTRL_USB30_CTL3_phy3_rxebufmode_DEFAULT 0x00000000
-
-/* USB_CTRL :: USB30_CTL3 :: phy3_pipe_txmargin_en [02:02] */
-#define BCHP_USB_CTRL_USB30_CTL3_phy3_pipe_txmargin_en_MASK 0x00000004
-#define BCHP_USB_CTRL_USB30_CTL3_phy3_pipe_txmargin_en_SHIFT 2
-#define BCHP_USB_CTRL_USB30_CTL3_phy3_pipe_txmargin_en_DEFAULT 0x00000000
-
-/* USB_CTRL :: USB30_CTL3 :: phy3_pipe_txswing [01:01] */
-#define BCHP_USB_CTRL_USB30_CTL3_phy3_pipe_txswing_MASK 0x00000002
-#define BCHP_USB_CTRL_USB30_CTL3_phy3_pipe_txswing_SHIFT 1
-#define BCHP_USB_CTRL_USB30_CTL3_phy3_pipe_txswing_DEFAULT 0x00000000
-
-/* USB_CTRL :: USB30_CTL3 :: phy3_mode [00:00] */
-#define BCHP_USB_CTRL_USB30_CTL3_phy3_mode_MASK 0x00000001
-#define BCHP_USB_CTRL_USB30_CTL3_phy3_mode_SHIFT 0
-#define BCHP_USB_CTRL_USB30_CTL3_phy3_mode_DEFAULT 0x00000001
-
-/***************************************************************************
- *USB30_CTL4 - USB30 CONTROL Register 4
- ***************************************************************************/
-/* USB_CTRL :: USB30_CTL4 :: usb30_ctl4_spare1 [31:24] */
-#define BCHP_USB_CTRL_USB30_CTL4_usb30_ctl4_spare1_MASK 0xff000000
-#define BCHP_USB_CTRL_USB30_CTL4_usb30_ctl4_spare1_SHIFT 24
-#define BCHP_USB_CTRL_USB30_CTL4_usb30_ctl4_spare1_DEFAULT 0x00000000
-
-/* USB_CTRL :: USB30_CTL4 :: phy3_tpout_sel [23:16] */
-#define BCHP_USB_CTRL_USB30_CTL4_phy3_tpout_sel_MASK 0x00ff0000
-#define BCHP_USB_CTRL_USB30_CTL4_phy3_tpout_sel_SHIFT 16
-#define BCHP_USB_CTRL_USB30_CTL4_phy3_tpout_sel_DEFAULT 0x00000000
-
-/* USB_CTRL :: USB30_CTL4 :: xhci_tpout_sel [15:00] */
-#define BCHP_USB_CTRL_USB30_CTL4_xhci_tpout_sel_MASK 0x0000ffff
-#define BCHP_USB_CTRL_USB30_CTL4_xhci_tpout_sel_SHIFT 0
-#define BCHP_USB_CTRL_USB30_CTL4_xhci_tpout_sel_DEFAULT 0x00000000
-
-/***************************************************************************
- *USB30_PCTL - USB30 PORT CONTROL Register
- ***************************************************************************/
-/* USB_CTRL :: USB30_PCTL :: USB3_PCTL_SPARE2 [31:29] */
-#define BCHP_USB_CTRL_USB30_PCTL_USB3_PCTL_SPARE2_MASK 0xe0000000
-#define BCHP_USB_CTRL_USB30_PCTL_USB3_PCTL_SPARE2_SHIFT 29
-#define BCHP_USB_CTRL_USB30_PCTL_USB3_PCTL_SPARE2_DEFAULT 0x00000000
-
-/* USB_CTRL :: USB30_PCTL :: PHY3_BYP_CLKMUX_P1 [28:28] */
-#define BCHP_USB_CTRL_USB30_PCTL_PHY3_BYP_CLKMUX_P1_MASK 0x10000000
-#define BCHP_USB_CTRL_USB30_PCTL_PHY3_BYP_CLKMUX_P1_SHIFT 28
-#define BCHP_USB_CTRL_USB30_PCTL_PHY3_BYP_CLKMUX_P1_DEFAULT 0x00000001
-
-/* USB_CTRL :: USB30_PCTL :: PHY3_PIPE_PWRDWN_OVERRIDE_EN_P1 [27:27] */
-#define BCHP_USB_CTRL_USB30_PCTL_PHY3_PIPE_PWRDWN_OVERRIDE_EN_P1_MASK 0x08000000
-#define BCHP_USB_CTRL_USB30_PCTL_PHY3_PIPE_PWRDWN_OVERRIDE_EN_P1_SHIFT 27
-#define BCHP_USB_CTRL_USB30_PCTL_PHY3_PIPE_PWRDWN_OVERRIDE_EN_P1_DEFAULT 0x00000000
-
-/* USB_CTRL :: USB30_PCTL :: PHY3_PIPE_PWRDWN_OVERRIDE_VALUE_P1 [26:25] */
-#define BCHP_USB_CTRL_USB30_PCTL_PHY3_PIPE_PWRDWN_OVERRIDE_VALUE_P1_MASK 0x06000000
-#define BCHP_USB_CTRL_USB30_PCTL_PHY3_PIPE_PWRDWN_OVERRIDE_VALUE_P1_SHIFT 25
-#define BCHP_USB_CTRL_USB30_PCTL_PHY3_PIPE_PWRDWN_OVERRIDE_VALUE_P1_DEFAULT 0x00000000
-
-/* USB_CTRL :: USB30_PCTL :: PHY3_TX_RxDetOut_OVERRIDE_P1 [24:24] */
-#define BCHP_USB_CTRL_USB30_PCTL_PHY3_TX_RxDetOut_OVERRIDE_P1_MASK 0x01000000
-#define BCHP_USB_CTRL_USB30_PCTL_PHY3_TX_RxDetOut_OVERRIDE_P1_SHIFT 24
-#define BCHP_USB_CTRL_USB30_PCTL_PHY3_TX_RxDetOut_OVERRIDE_P1_DEFAULT 0x00000000
-
-/* USB_CTRL :: USB30_PCTL :: PHY3_TX_ElecIdle_OVERRIDE_P1 [23:23] */
-#define BCHP_USB_CTRL_USB30_PCTL_PHY3_TX_ElecIdle_OVERRIDE_P1_MASK 0x00800000
-#define BCHP_USB_CTRL_USB30_PCTL_PHY3_TX_ElecIdle_OVERRIDE_P1_SHIFT 23
-#define BCHP_USB_CTRL_USB30_PCTL_PHY3_TX_ElecIdle_OVERRIDE_P1_DEFAULT 0x00000000
-
-/* USB_CTRL :: USB30_PCTL :: PHY3_TX_RxDetReq_OVERRIDE_P1 [22:22] */
-#define BCHP_USB_CTRL_USB30_PCTL_PHY3_TX_RxDetReq_OVERRIDE_P1_MASK 0x00400000
-#define BCHP_USB_CTRL_USB30_PCTL_PHY3_TX_RxDetReq_OVERRIDE_P1_SHIFT 22
-#define BCHP_USB_CTRL_USB30_PCTL_PHY3_TX_RxDetReq_OVERRIDE_P1_DEFAULT 0x00000000
-
-/* USB_CTRL :: USB30_PCTL :: PHY3_TX_PD_OVERRIDE_P1 [21:21] */
-#define BCHP_USB_CTRL_USB30_PCTL_PHY3_TX_PD_OVERRIDE_P1_MASK 0x00200000
-#define BCHP_USB_CTRL_USB30_PCTL_PHY3_TX_PD_OVERRIDE_P1_SHIFT 21
-#define BCHP_USB_CTRL_USB30_PCTL_PHY3_TX_PD_OVERRIDE_P1_DEFAULT 0x00000000
-
-/* USB_CTRL :: USB30_PCTL :: PHY3_RX_PD_OVERRIDE_P1 [20:20] */
-#define BCHP_USB_CTRL_USB30_PCTL_PHY3_RX_PD_OVERRIDE_P1_MASK 0x00100000
-#define BCHP_USB_CTRL_USB30_PCTL_PHY3_RX_PD_OVERRIDE_P1_SHIFT 20
-#define BCHP_USB_CTRL_USB30_PCTL_PHY3_RX_PD_OVERRIDE_P1_DEFAULT 0x00000000
-
-/* USB_CTRL :: USB30_PCTL :: PHY3_MODE_P1 [19:18] */
-#define BCHP_USB_CTRL_USB30_PCTL_PHY3_MODE_P1_MASK 0x000c0000
-#define BCHP_USB_CTRL_USB30_PCTL_PHY3_MODE_P1_SHIFT 18
-#define BCHP_USB_CTRL_USB30_PCTL_PHY3_MODE_P1_DEFAULT 0x00000000
-
-/* USB_CTRL :: USB30_PCTL :: PHY3_SOFT_RESETB_P1 [17:17] */
-#define BCHP_USB_CTRL_USB30_PCTL_PHY3_SOFT_RESETB_P1_MASK 0x00020000
-#define BCHP_USB_CTRL_USB30_PCTL_PHY3_SOFT_RESETB_P1_SHIFT 17
-#define BCHP_USB_CTRL_USB30_PCTL_PHY3_SOFT_RESETB_P1_DEFAULT 0x00000001
-
-/* USB_CTRL :: USB30_PCTL :: PHY3_AFE_NON_DRIVING_P1 [16:16] */
-#define BCHP_USB_CTRL_USB30_PCTL_PHY3_AFE_NON_DRIVING_P1_MASK 0x00010000
-#define BCHP_USB_CTRL_USB30_PCTL_PHY3_AFE_NON_DRIVING_P1_SHIFT 16
-#define BCHP_USB_CTRL_USB30_PCTL_PHY3_AFE_NON_DRIVING_P1_DEFAULT 0x00000000
-
-/* USB_CTRL :: USB30_PCTL :: PHY3_IDDQ_OVERRIDE [15:15] */
-#define BCHP_USB_CTRL_USB30_PCTL_PHY3_IDDQ_OVERRIDE_MASK 0x00008000
-#define BCHP_USB_CTRL_USB30_PCTL_PHY3_IDDQ_OVERRIDE_SHIFT 15
-#define BCHP_USB_CTRL_USB30_PCTL_PHY3_IDDQ_OVERRIDE_DEFAULT 0x00000000
-
-/* USB_CTRL :: USB30_PCTL :: USB3_PCTL_SPARE1 [14:13] */
-#define BCHP_USB_CTRL_USB30_PCTL_USB3_PCTL_SPARE1_MASK 0x00006000
-#define BCHP_USB_CTRL_USB30_PCTL_USB3_PCTL_SPARE1_SHIFT 13
-#define BCHP_USB_CTRL_USB30_PCTL_USB3_PCTL_SPARE1_DEFAULT 0x00000000
-
-/* USB_CTRL :: USB30_PCTL :: PHY3_BYP_CLKMUX [12:12] */
-#define BCHP_USB_CTRL_USB30_PCTL_PHY3_BYP_CLKMUX_MASK 0x00001000
-#define BCHP_USB_CTRL_USB30_PCTL_PHY3_BYP_CLKMUX_SHIFT 12
-#define BCHP_USB_CTRL_USB30_PCTL_PHY3_BYP_CLKMUX_DEFAULT 0x00000001
-
-/* USB_CTRL :: USB30_PCTL :: PHY3_PIPE_PWRDWN_OVERRIDE_EN [11:11] */
-#define BCHP_USB_CTRL_USB30_PCTL_PHY3_PIPE_PWRDWN_OVERRIDE_EN_MASK 0x00000800
-#define BCHP_USB_CTRL_USB30_PCTL_PHY3_PIPE_PWRDWN_OVERRIDE_EN_SHIFT 11
-#define BCHP_USB_CTRL_USB30_PCTL_PHY3_PIPE_PWRDWN_OVERRIDE_EN_DEFAULT 0x00000000
-
-/* USB_CTRL :: USB30_PCTL :: PHY3_PIPE_PWRDWN_OVERRIDE_VALUE [10:09] */
-#define BCHP_USB_CTRL_USB30_PCTL_PHY3_PIPE_PWRDWN_OVERRIDE_VALUE_MASK 0x00000600
-#define BCHP_USB_CTRL_USB30_PCTL_PHY3_PIPE_PWRDWN_OVERRIDE_VALUE_SHIFT 9
-#define BCHP_USB_CTRL_USB30_PCTL_PHY3_PIPE_PWRDWN_OVERRIDE_VALUE_DEFAULT 0x00000000
-
-/* USB_CTRL :: USB30_PCTL :: PHY3_TX_RxDetOut_OVERRIDE [08:08] */
-#define BCHP_USB_CTRL_USB30_PCTL_PHY3_TX_RxDetOut_OVERRIDE_MASK 0x00000100
-#define BCHP_USB_CTRL_USB30_PCTL_PHY3_TX_RxDetOut_OVERRIDE_SHIFT 8
-#define BCHP_USB_CTRL_USB30_PCTL_PHY3_TX_RxDetOut_OVERRIDE_DEFAULT 0x00000000
-
-/* USB_CTRL :: USB30_PCTL :: PHY3_TX_ElecIdle_OVERRIDE [07:07] */
-#define BCHP_USB_CTRL_USB30_PCTL_PHY3_TX_ElecIdle_OVERRIDE_MASK 0x00000080
-#define BCHP_USB_CTRL_USB30_PCTL_PHY3_TX_ElecIdle_OVERRIDE_SHIFT 7
-#define BCHP_USB_CTRL_USB30_PCTL_PHY3_TX_ElecIdle_OVERRIDE_DEFAULT 0x00000000
-
-/* USB_CTRL :: USB30_PCTL :: PHY3_TX_RxDetReq_OVERRIDE [06:06] */
-#define BCHP_USB_CTRL_USB30_PCTL_PHY3_TX_RxDetReq_OVERRIDE_MASK 0x00000040
-#define BCHP_USB_CTRL_USB30_PCTL_PHY3_TX_RxDetReq_OVERRIDE_SHIFT 6
-#define BCHP_USB_CTRL_USB30_PCTL_PHY3_TX_RxDetReq_OVERRIDE_DEFAULT 0x00000000
-
-/* USB_CTRL :: USB30_PCTL :: PHY3_TX_PD_OVERRIDE [05:05] */
-#define BCHP_USB_CTRL_USB30_PCTL_PHY3_TX_PD_OVERRIDE_MASK 0x00000020
-#define BCHP_USB_CTRL_USB30_PCTL_PHY3_TX_PD_OVERRIDE_SHIFT 5
-#define BCHP_USB_CTRL_USB30_PCTL_PHY3_TX_PD_OVERRIDE_DEFAULT 0x00000000
-
-/* USB_CTRL :: USB30_PCTL :: PHY3_RX_PD_OVERRIDE [04:04] */
-#define BCHP_USB_CTRL_USB30_PCTL_PHY3_RX_PD_OVERRIDE_MASK 0x00000010
-#define BCHP_USB_CTRL_USB30_PCTL_PHY3_RX_PD_OVERRIDE_SHIFT 4
-#define BCHP_USB_CTRL_USB30_PCTL_PHY3_RX_PD_OVERRIDE_DEFAULT 0x00000000
-
-/* USB_CTRL :: USB30_PCTL :: PHY3_MODE [03:02] */
-#define BCHP_USB_CTRL_USB30_PCTL_PHY3_MODE_MASK 0x0000000c
-#define BCHP_USB_CTRL_USB30_PCTL_PHY3_MODE_SHIFT 2
-#define BCHP_USB_CTRL_USB30_PCTL_PHY3_MODE_DEFAULT 0x00000000
-
-/* USB_CTRL :: USB30_PCTL :: PHY3_SOFT_RESETB [01:01] */
-#define BCHP_USB_CTRL_USB30_PCTL_PHY3_SOFT_RESETB_MASK 0x00000002
-#define BCHP_USB_CTRL_USB30_PCTL_PHY3_SOFT_RESETB_SHIFT 1
-#define BCHP_USB_CTRL_USB30_PCTL_PHY3_SOFT_RESETB_DEFAULT 0x00000001
-
-/* USB_CTRL :: USB30_PCTL :: PHY3_AFE_NON_DRIVING [00:00] */
-#define BCHP_USB_CTRL_USB30_PCTL_PHY3_AFE_NON_DRIVING_MASK 0x00000001
-#define BCHP_USB_CTRL_USB30_PCTL_PHY3_AFE_NON_DRIVING_SHIFT 0
-#define BCHP_USB_CTRL_USB30_PCTL_PHY3_AFE_NON_DRIVING_DEFAULT 0x00000000
-
-/***************************************************************************
- *USB30_CTL5 - USB30 CONTROL Register 5
- ***************************************************************************/
-/* USB_CTRL :: USB30_CTL5 :: USB30_CTL5 [31:00] */
-#define BCHP_USB_CTRL_USB30_CTL5_USB30_CTL5_MASK 0xffffffff
-#define BCHP_USB_CTRL_USB30_CTL5_USB30_CTL5_SHIFT 0
-#define BCHP_USB_CTRL_USB30_CTL5_USB30_CTL5_DEFAULT 0x00000000
-
-/***************************************************************************
- *SPARE5 - Spare1 Register for future use
- ***************************************************************************/
-/* USB_CTRL :: SPARE5 :: SPARE5_BITS [31:00] */
-#define BCHP_USB_CTRL_SPARE5_SPARE5_BITS_MASK 0xffffffff
-#define BCHP_USB_CTRL_SPARE5_SPARE5_BITS_SHIFT 0
-#define BCHP_USB_CTRL_SPARE5_SPARE5_BITS_DEFAULT 0x00000000
-
-/***************************************************************************
- *SPARE6 - Spare2 Register for future use
- ***************************************************************************/
-/* USB_CTRL :: SPARE6 :: SPARE6_BITS [31:00] */
-#define BCHP_USB_CTRL_SPARE6_SPARE6_BITS_MASK 0xffffffff
-#define BCHP_USB_CTRL_SPARE6_SPARE6_BITS_SHIFT 0
-#define BCHP_USB_CTRL_SPARE6_SPARE6_BITS_DEFAULT 0x00000000
-
-#endif /* #ifndef BCHP_USB_CTRL_H__ */
-
-/* End of File */
diff --git a/include/linux/brcmstb/bmem.h b/include/linux/brcmstb/bmem.h
new file mode 100644
index 0000000..129a4de
--- /dev/null
+++ b/include/linux/brcmstb/bmem.h
@@ -0,0 +1,34 @@
+/*
+ * Copyright © 2015 Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License, version 2, as
+ * published by the Free Software Foundation (the "GPL").
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ * General Public License for more details.
+ *
+ * A copy of the GPL is available at
+ * http://www.broadcom.com/licenses/GPLv2.php or from the Free Software
+ * Foundation at https://www.gnu.org/licenses/ .
+ */
+
+#ifndef _LINUX_BRCMSTB_BMEM_H
+#define _LINUX_BRCMSTB_BMEM_H
+
+int bmem_find_region(phys_addr_t addr, phys_addr_t size);
+int bmem_get_page(struct mm_struct *mm, struct vm_area_struct *vma,
+ unsigned long start, struct page **page);
+int bmem_region_info(int idx, phys_addr_t *addr, phys_addr_t *size);
+
+/* Below functions are for calling during initialization and may need stubs */
+
+#ifdef CONFIG_BRCMSTB_BMEM
+void __init bmem_reserve(void);
+#else
+static inline void bmem_reserve(void) {}
+#endif
+
+#endif /* _LINUX_BRCMSTB_BMEM_H */
diff --git a/include/linux/brcmstb/brcmstb.h b/include/linux/brcmstb/brcmstb.h
index b668fc4..77bd939 100644
--- a/include/linux/brcmstb/brcmstb.h
+++ b/include/linux/brcmstb/brcmstb.h
@@ -1,5 +1,5 @@
/*
- * Copyright (C) 2009 Broadcom Corporation
+ * Copyright © 2009-2015 Broadcom Corporation
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
@@ -10,19 +10,31 @@
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ * A copy of the GPL is available at
+ * http://www.broadcom.com/licenses/GPLv2.php or from the Free Software
+ * Foundation at https://www.gnu.org/licenses/ .
+ */
+
+/*
+ * **********************
+ * READ ME BEFORE EDITING
+ * **********************
+ *
+ * If you update this file, make sure to bump BRCMSTB_H_VERSION if there is an
+ * API change!
*/
#ifndef _ASM_BRCMSTB_BRCMSTB_H
#define _ASM_BRCMSTB_BRCMSTB_H
+#define BRCMSTB_H_VERSION 2
+
#if !defined(__ASSEMBLY__)
#include <linux/types.h>
#include <linux/smp.h>
#include <linux/device.h>
+#include <linux/brcmstb/memory_api.h>
#if defined(CONFIG_MIPS)
#include <linux/brcmstb/brcmapi.h>
@@ -311,54 +323,6 @@
#include <linux/brcmstb/7364a0/bchp_xpt_security_ns.h>
#include <linux/brcmstb/7364a0/bchp_xpt_security_ns_intr2_0.h>
-#elif defined(CONFIG_BCM7366B0)
-#include <linux/brcmstb/7366b0/bchp_aon_ctrl.h>
-#include <linux/brcmstb/7366b0/bchp_aon_pin_ctrl.h>
-#include <linux/brcmstb/7366b0/bchp_aon_pm_l2.h>
-#include <linux/brcmstb/7366b0/bchp_bspi.h>
-#include <linux/brcmstb/7366b0/bchp_bspi_raf.h>
-#include <linux/brcmstb/7366b0/bchp_clkgen.h>
-#include <linux/brcmstb/7366b0/bchp_common.h>
-#include <linux/brcmstb/7366b0/bchp_ddr34_phy_byte_lane_0_0.h>
-#include <linux/brcmstb/7366b0/bchp_ddr34_phy_byte_lane_1_0.h>
-#include <linux/brcmstb/7366b0/bchp_ddr34_phy_byte_lane_2_0.h>
-#include <linux/brcmstb/7366b0/bchp_ddr34_phy_byte_lane_3_0.h>
-#include <linux/brcmstb/7366b0/bchp_ddr34_phy_control_regs_0.h>
-#include <linux/brcmstb/7366b0/bchp_ebi.h>
-#include <linux/brcmstb/7366b0/bchp_gio.h>
-#include <linux/brcmstb/7366b0/bchp_gio_aon.h>
-#include <linux/brcmstb/7366b0/bchp_hif_continuation.h>
-#include <linux/brcmstb/7366b0/bchp_hif_cpubiuctrl.h>
-#include <linux/brcmstb/7366b0/bchp_hif_intr2.h>
-#include <linux/brcmstb/7366b0/bchp_hif_mspi.h>
-#include <linux/brcmstb/7366b0/bchp_hif_spi_intr2.h>
-#include <linux/brcmstb/7366b0/bchp_hif_top_ctrl.h>
-#include <linux/brcmstb/7366b0/bchp_irq0.h>
-#include <linux/brcmstb/7366b0/bchp_irq1.h>
-#include <linux/brcmstb/7366b0/bchp_memc_ddr_0.h>
-#include <linux/brcmstb/7366b0/bchp_moca_hostmisc.h>
-#include <linux/brcmstb/7366b0/bchp_nand.h>
-#include <linux/brcmstb/7366b0/bchp_pcie_0_dma.h>
-#include <linux/brcmstb/7366b0/bchp_pcie_0_ext_cfg.h>
-#include <linux/brcmstb/7366b0/bchp_pcie_0_intr2.h>
-#include <linux/brcmstb/7366b0/bchp_pcie_0_misc.h>
-#include <linux/brcmstb/7366b0/bchp_pcie_0_misc_perst.h>
-#include <linux/brcmstb/7366b0/bchp_pcie_0_rc_cfg_pcie.h>
-#include <linux/brcmstb/7366b0/bchp_pcie_0_rc_cfg_type1.h>
-#include <linux/brcmstb/7366b0/bchp_pcie_0_rc_cfg_vendor.h>
-#include <linux/brcmstb/7366b0/bchp_pcie_0_rgr1.h>
-#include <linux/brcmstb/7366b0/bchp_sdio_0_cfg.h>
-#include <linux/brcmstb/7366b0/bchp_shimphy_addr_cntl_0.h>
-#include <linux/brcmstb/7366b0/bchp_sun_top_ctrl.h>
-#include <linux/brcmstb/7366b0/bchp_usb_ctrl.h>
-#include <linux/brcmstb/7366b0/bchp_xpt_bus_if.h>
-#include <linux/brcmstb/7366b0/bchp_xpt_fe.h>
-#include <linux/brcmstb/7366b0/bchp_xpt_memdma_mcpb.h>
-#include <linux/brcmstb/7366b0/bchp_xpt_memdma_mcpb_ch0.h>
-#include <linux/brcmstb/7366b0/bchp_xpt_pmu.h>
-#include <linux/brcmstb/7366b0/bchp_xpt_security_ns.h>
-#include <linux/brcmstb/7366b0/bchp_xpt_security_ns_intr2_0.h>
-
#elif defined(CONFIG_BCM7366C0)
#include <linux/brcmstb/7366c0/bchp_aon_ctrl.h>
#include <linux/brcmstb/7366c0/bchp_aon_pin_ctrl.h>
@@ -446,6 +410,7 @@
#include <linux/brcmstb/74371a0/bchp_shimphy_addr_cntl_0.h>
#include <linux/brcmstb/74371a0/bchp_sun_top_ctrl.h>
#include <linux/brcmstb/74371a0/bchp_usb_ctrl.h>
+#include <linux/brcmstb/74371a0/bchp_usb_xhci_ec.h>
#elif defined(CONFIG_BCM7439A0)
#include <linux/brcmstb/7439a0/bchp_aon_ctrl.h>
@@ -601,21 +566,6 @@
#endif
-/* Kernel will program WKTMR to expire in 1 second */
-#define BRCM_STANDBY_TEST 0x01
-/* Wait 120s before entering standby, to allow registers to be read */
-#define BRCM_STANDBY_DELAY 0x02
-/* Show UART output at each step */
-#define BRCM_STANDBY_VERBOSE 0x04
-/* Don't enter standby - just delay for 5s then return */
-#define BRCM_STANDBY_NO_SLEEP 0x08
-/* Don't shut down MIPS PLL */
-#define BRCM_STANDBY_MIPS_PLL_ON 0x10
-/* Don't shut down DDR PLL */
-#define BRCM_STANDBY_DDR_PLL_ON 0x20
-
-#define UPGTMR_FREQ 27000000
-
/***********************************************************************
* Register access macros - sample usage:
*
@@ -666,36 +616,6 @@
} while (0)
/***********************************************************************
- * Platform features (based on bond options or bootloader settings)
- ***********************************************************************/
-
-extern int brcm_sata_enabled;
-extern int brcm_pcie_enabled;
-extern int brcm_docsis_platform;
-extern int brcm_moca_enabled;
-extern int brcm_usb_enabled;
-
-#ifdef CONFIG_BRCM_SLOW_TVM_CLOCK
-#define BRCM_BASE_BAUD_TVM (54000000 / 16)
-#else
-#define BRCM_BASE_BAUD_TVM (216000000 / 16)
-#endif
-
-#define BRCM_BASE_BAUD_STB (81000000 / 16)
-#define BRCM_BASE_BAUD_PCU (192000000 / 16)
-extern unsigned long brcm_base_baud0;
-extern unsigned long brcm_base_baud;
-
-#define CFE_STRING_SIZE 64
-
-extern char brcm_cfe_boardname[CFE_STRING_SIZE];
-
-extern unsigned long brcm_moca_i2c_base;
-extern unsigned long brcm_moca_rf_band;
-
-#define BRCM_PCI_SLOTS 16
-
-/***********************************************************************
* HIF L2 IRQ controller - shared by EDU, SDIO
***********************************************************************/
@@ -757,128 +677,14 @@
#endif
-#define __BMIPS_GET_CBR() ((unsigned long)BMIPS_GET_CBR())
-
-asmlinkage void brcm_upper_tlb_setup(void);
-void board_pinmux_setup(void);
-void board_get_ram_size(unsigned long *dram0_mb, unsigned long *dram1_mb);
-void brcm_wraparound_check(void);
-
-void ebi_restore_settings(void);
-
-void brcmstb_cpu_setup(void);
-void bchip_sata3_init(void);
-void bchip_usb_init(void);
-void bchip_moca_init(void);
-void bchip_check_compat(void);
-void bchip_set_features(void);
-void bchip_early_setup(void);
-void brcm_machine_restart(const char *command);
-void brcm_machine_halt(void);
-char *brcmstb_pcibios_setup(char *str);
-
-void __cpuinit bmips_start_cpu_cores(void);
-
-void cfe_die(char *fmt, ...);
-
-ssize_t brcm_pm_show_cpu_div(struct device *dev,
- struct device_attribute *attr, char *buf);
-ssize_t brcm_pm_store_cpu_div(struct device *dev,
- struct device_attribute *attr, const char *buf, size_t count);
-ssize_t brcm_pm_show_cpu_pll(struct device *dev,
- struct device_attribute *attr, char *buf);
-ssize_t brcm_pm_store_cpu_pll(struct device *dev,
- struct device_attribute *attr, const char *buf, size_t count);
-
-ssize_t brcm_pm_show_usb_power(struct device *dev,
- struct device_attribute *attr, char *buf);
-ssize_t brcm_pm_store_usb_power(struct device *dev,
- struct device_attribute *attr, const char *buf, size_t count);
-ssize_t brcm_pm_show_sata_power(struct device *dev,
- struct device_attribute *attr, char *buf);
-ssize_t brcm_pm_store_sata_power(struct device *dev,
- struct device_attribute *attr, const char *buf, size_t count);
-ssize_t brcm_pm_show_ddr_timeout(struct device *dev,
- struct device_attribute *attr, char *buf);
-ssize_t brcm_pm_store_ddr_timeout(struct device *dev,
- struct device_attribute *attr, const char *buf, size_t count);
-ssize_t brcm_pm_show_standby_flags(struct device *dev,
- struct device_attribute *attr, char *buf);
-ssize_t brcm_pm_store_standby_flags(struct device *dev,
- struct device_attribute *attr, const char *buf, size_t count);
-ssize_t brcm_pm_show_standby_timeout(struct device *dev,
- struct device_attribute *attr, char *buf);
-ssize_t brcm_pm_store_standby_timeout(struct device *dev,
- struct device_attribute *attr, const char *buf, size_t count);
-ssize_t brcm_pm_show_memc1_power(struct device *dev,
- struct device_attribute *attr, char *buf);
-ssize_t brcm_pm_store_memc1_power(struct device *dev,
- struct device_attribute *attr, const char *buf, size_t count);
-ssize_t brcm_pm_show_halt_mode(struct device *dev,
- struct device_attribute *attr, char *buf);
-ssize_t brcm_pm_store_halt_mode(struct device *dev,
- struct device_attribute *attr, const char *buf, size_t count);
-ssize_t brcm_pm_show_time_at_wakeup(struct device *dev,
- struct device_attribute *attr, char *buf);
-
-#ifdef BCHP_PM_L2_CPU_STATUS
-#define TIMER_INTR_MASK BCHP_PM_L2_CPU_STATUS_TIMER_INTR_MASK
-#ifdef BCHP_PM_L2_CPU_STATUS_WOL_ENET_MASK
-#define WOL_ENET_MASK BCHP_PM_L2_CPU_STATUS_WOL_ENET_MASK
-#elif defined(BCHP_PM_L2_CPU_STATUS_WOL_MPD_MASK)
-#define WOL_ENET_MASK (BCHP_PM_L2_CPU_STATUS_WOL_MPD_MASK | \
- BCHP_PM_L2_CPU_STATUS_WOL_HFB_MASK)
-#else
-#define WOL_ENET_MASK (0)
-#endif
-#ifdef BCHP_PM_L2_CPU_STATUS_WOL_MOCA_MASK
-#define WOL_MOCA_MASK BCHP_PM_L2_CPU_STATUS_WOL_MOCA_MASK
-#else
-#define WOL_MOCA_MASK (0)
-#endif
-#else
-#define TIMER_INTR_MASK BCHP_AON_PM_L2_CPU_STATUS_TIMER_INTR_MASK
-#define WOL_ENET_MASK BCHP_AON_PM_L2_CPU_STATUS_WOL_ENET_MASK
-#ifdef BCHP_AON_PM_L2_CPU_STATUS_WOL_MOCA_MASK
-#define WOL_MOCA_MASK BCHP_AON_PM_L2_CPU_STATUS_WOL_MOCA_MASK
-#else
-#ifdef CONFIG_BCM7231B0
-#define WOL_MOCA_MASK BCHP_AON_PM_L2_CPU_STATUS_WOL_ENET1_MASK
-#else
-#define WOL_MOCA_MASK (0)
-#endif
-#endif
-#endif
-
-/* NMI / TP1 reset vector */
-extern char brcm_reset_nmi_vec[];
-extern char brcm_reset_nmi_vec_end[];
-
-/* TP1 warm restart interrupt vector */
-extern char brcm_tp1_int_vec[];
-extern char brcm_tp1_int_vec_end[];
-
-extern atomic_t brcm_unaligned_fp_count;
-extern atomic_t brcm_rdhwr_count; /* excludes rdhwr fastpath */
-
-extern unsigned long brcm_cpu_khz;
-extern unsigned long brcm_adj_cpu_khz;
-
-#if defined(CONFIG_BRCMSTB_USE_MEGA_BARRIER)
-extern void brcmstb_mega_barrier(void);
-#endif
-
-/* BCMGENET device tree properties */
-#define BRCM_PHY_ID_AUTO 0x100
-#define BRCM_PHY_ID_NONE 0x101
-
-#define BRCM_PHY_TYPE_INT 1
-#define BRCM_PHY_TYPE_EXT_MII 2
-#define BRCM_PHY_TYPE_EXT_RVMII 3
-#define BRCM_PHY_TYPE_EXT_RGMII 4
-#define BRCM_PHY_TYPE_EXT_RGMII_IBS 5
-#define BRCM_PHY_TYPE_EXT_RGMII_NO_ID 6
-#define BRCM_PHY_TYPE_MOCA 7
+/*
+ * Exclude a given memory range from the MAC authentication process during S3
+ * suspend/resume. Ranges are reset after each MAC (i.e., after each S3
+ * suspend/resume cycle). Returns non-zero on error.
+ */
+int brcmstb_pm_mem_exclude(phys_addr_t addr, size_t len);
+/* So users can determine whether the kernel provides this API */
+#define BRCMSTB_HAS_PM_MEM_EXCLUDE
#endif /* !defined(__ASSEMBLY__) */
diff --git a/include/linux/brcmstb/cma_driver.h b/include/linux/brcmstb/cma_driver.h
index 83cb700..25d0ba6 100644
--- a/include/linux/brcmstb/cma_driver.h
+++ b/include/linux/brcmstb/cma_driver.h
@@ -49,6 +49,7 @@
int memc;
};
+
/*
* Note to kernel module / driver developers:
* This interface is subject to change!
@@ -67,4 +68,14 @@
int cma_dev_kva_unmap(const void *kva);
int cma_drvr_is_ready(void);
+/* Below functions are for calling during initialization and may need stubs */
+
+#ifdef CONFIG_BRCMSTB_CMA
+void __init cma_reserve(void);
+void __init cma_register(void);
+#else
+static inline void cma_reserve(void) {}
+static inline void cma_register(void) {}
+#endif
+
#endif /* __CMA_DRIVER_H__ */
diff --git a/include/linux/brcmstb/memory_api.h b/include/linux/brcmstb/memory_api.h
new file mode 100644
index 0000000..115ec7e
--- /dev/null
+++ b/include/linux/brcmstb/memory_api.h
@@ -0,0 +1,94 @@
+/*
+ * Copyright © 2015 Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License, version 2, as
+ * published by the Free Software Foundation (the "GPL").
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ * General Public License for more details.
+ *
+ * A copy of the GPL is available at
+ * http://www.broadcom.com/licenses/GPLv2.php or from the Free Software
+ * Foundation at https://www.gnu.org/licenses/ .
+ */
+
+#ifndef _BRCMSTB_MEMORY_API_H
+#define _BRCMSTB_MEMORY_API_H
+
+/*
+ * Memory API that must be supplied for Broadcom STB middleware.
+ *
+ * **********************
+ * READ ME BEFORE EDITING
+ * **********************
+ *
+ * If you update this file, make sure to bump BRCMSTB_H_VERSION
+ * in brcmstb.h if there is an API change!
+ */
+
+#define MAX_BRCMSTB_RANGE 8
+#define MAX_BRCMSTB_MEMC 3
+#define MAX_BRCMSTB_RESERVED_RANGE 16
+
+struct brcmstb_range {
+ u64 addr;
+ u64 size; /* 0 means no region */
+};
+
+struct brcmstb_memory {
+ struct {
+ struct brcmstb_range range[MAX_BRCMSTB_RANGE];
+ int count;
+ } memc[MAX_BRCMSTB_MEMC];
+ /* fixed map space */
+ struct {
+ struct brcmstb_range range[MAX_BRCMSTB_RANGE];
+ int count;
+ } lowmem;
+ /* bmem carveout regions */
+ struct {
+ struct brcmstb_range range[MAX_BRCMSTB_RANGE];
+ int count;
+ } bmem;
+ /* CMA carveout regions */
+ struct {
+ struct brcmstb_range range[MAX_BRCMSTB_RANGE];
+ int count;
+ } cma;
+ /* regions that nexus cannot recommend for bmem or CMA */
+ struct {
+ struct brcmstb_range range[MAX_BRCMSTB_RESERVED_RANGE];
+ int count;
+ } reserved;
+};
+
+int brcmstb_memory_get(struct brcmstb_memory *mem);
+int brcmstb_memory_phys_addr_to_memc(phys_addr_t pa);
+
+/* Below functions are for calling during initialization and may need stubs */
+
+int __init brcmstb_memory_get_default_reserve(int bank_nr,
+ phys_addr_t *pstart, phys_addr_t *psize);
+
+#ifdef CONFIG_BRCMSTB_MEMORY_API
+void __init brcmstb_memory_reserve(void);
+#else
+static inline void brcmstb_memory_reserve(void) {};
+#endif
+
+/* The following relate to the default reservation scheme */
+
+enum brcmstb_reserve_type {
+ BRCMSTB_RESERVE_BMEM,
+ BRCMSTB_RESERVE_CMA,
+};
+
+/* Determines what type of memory reservation will be used w/o CLI params */
+extern const enum brcmstb_reserve_type brcmstb_default_reserve;
+/* Should be set to true by any CLI option that overrides default reserve */
+extern bool brcmstb_memory_override_defaults;
+
+#endif /* _BRCMSTB_MEMORY_API_H */
diff --git a/include/linux/clk-provider.h b/include/linux/clk-provider.h
index 095a0e2..1edfd2a 100644
--- a/include/linux/clk-provider.h
+++ b/include/linux/clk-provider.h
@@ -333,6 +333,88 @@
spinlock_t *lock);
void of_divider_clk_setup(struct device_node *node);
+struct clk_mult_table {
+ unsigned int val;
+ unsigned int mult;
+};
+
+/**
+ * struct clk_multiplier - adjustable multiplier clock
+ *
+ * @hw: handle between common and hardware-specific interfaces
+ * @reg: register containing the multiplier
+ * @shift: shift to the multiplier bit field
+ * @width: width of the multiplier bit field
+ * @table: array of value/multiplier pairs, last entry should have mult = 0
+ * @lock: register lock
+ *
+ * Clock with an adjustable multiplier affecting its output frequency.
+ * Implements .recalc_rate, .set_rate and .round_rate
+ *
+ * Flags:
+ * CLK_MULTIPLIER_ONE_BASED - by default the muliplier is the value read from
+ * the register plus one. If CLK_MULTIPLIER_ONE_BASED is set then the
+ * multiplier is the raw value read from the register, with the value of
+ * zero considered invalid, unless CLK_MULTIPLIER_ALLOW_ZERO is set.
+ * CLK_MULTIPLIER_POWER_OF_TWO - clock muliplier is 2 raised to the value
+ * read from the hardware register
+ * CLK_MULTIPLIER_ALLOW_ZERO - Allow zero mulipliers. For multipliers which
+ * have CLK_MULTIPLIER_ONE_BASED set, it is possible to end up with a zero
+ * muliplier. Some hardware implementations gracefully handle this case
+ * and allow a zero muliplier by not modifying their input clock
+ * (multiply by one / bypass).
+ * CLK_MULTIPLIER_HIWORD_MASK - The multiplier settings are only in lower 16-bit
+ * of this register, and mask of multiplier bits are in higher 16-bit of
+ * this register. While setting the multiplier bits, higher 16-bit should
+ * also be updated to indicate changing multiplier bits.
+ * CLK_MULTIPLIER_READ_ONLY - The multiplier settings are preconfigured and
+ * should not be changed by the clock framework.
+ * CLK_MULTIPLIER_MAX_AT_ZERO - For multipliers which are like
+ * CLK_MULTIPLIER_ONE_BASED except when the value read from the register
+ * is zero, the multiplier is 2^width of the field.
+ */
+struct clk_multiplier {
+ struct clk_hw hw;
+ void __iomem *reg;
+ u8 shift;
+ u8 width;
+ u8 flags;
+ const struct clk_mult_table *table;
+ spinlock_t *lock;
+};
+
+#define CLK_MULTIPLIER_ONE_BASED BIT(0)
+#define CLK_MULTIPLIER_POWER_OF_TWO BIT(1)
+#define CLK_MULTIPLIER_ALLOW_ZERO BIT(2)
+#define CLK_MULTIPLIER_HIWORD_MASK BIT(3)
+#define CLK_MULTIPLIER_READ_ONLY BIT(4)
+#define CLK_MULTIPLIER_MAX_MULT_AT_ZERO BIT(5)
+
+extern const struct clk_ops clk_multiplier_ops;
+extern const struct clk_ops clk_multiplier_ro_ops;
+
+unsigned long multiplier_recalc_rate(struct clk_hw *hw,
+ unsigned long parent_rate, unsigned int val,
+ const struct clk_mult_table *table, unsigned long flags);
+long multiplier_round_rate(struct clk_hw *hw, unsigned long rate,
+ unsigned long *prate, const struct clk_mult_table *table,
+ u8 width, unsigned long flags);
+int multiplier_get_val(unsigned long rate, unsigned long parent_rate,
+ const struct clk_mult_table *table, u8 width,
+ unsigned long flags);
+struct clk *clk_register_multiplier(struct device *dev, const char *name,
+ const char *parent_name, unsigned long flags,
+ void __iomem *reg, u8 shift, u8 width,
+ u8 clk_multiplier_flags, spinlock_t *lock);
+struct clk *clk_register_multiplier_table(struct device *dev, const char *name,
+ const char *parent_name, unsigned long flags,
+ void __iomem *reg, u8 shift, u8 width,
+ u8 clk_multiplier_flags, const struct clk_mult_table *table,
+ spinlock_t *lock);
+void clk_unregister_multiplier(struct clk *clk);
+void of_multiplier_clk_setup(struct device_node *node);
+
+
/**
* struct clk_mux - multiplexer clock
*
diff --git a/include/linux/cma.h b/include/linux/cma.h
new file mode 100644
index 0000000..b9d6512
--- /dev/null
+++ b/include/linux/cma.h
@@ -0,0 +1,37 @@
+#ifndef __CMA_H__
+#define __CMA_H__
+
+/*
+ * There is always at least global CMA area and a few optional
+ * areas configured in kernel .config.
+ */
+#ifdef CONFIG_CMA_AREAS
+#define MAX_CMA_AREAS (1 + CONFIG_CMA_AREAS)
+
+#else
+#define MAX_CMA_AREAS (0)
+
+#endif
+
+struct cma {
+ unsigned long base_pfn;
+ unsigned long count;
+ unsigned long *bitmap;
+ unsigned int order_per_bit; /* Order of pages represented by one bit */
+ struct mutex lock;
+};
+
+extern unsigned long totalcma_pages;
+extern phys_addr_t cma_get_base(struct cma *cma);
+extern unsigned long cma_get_size(struct cma *cma);
+
+extern int __init cma_declare_contiguous(phys_addr_t base,
+ phys_addr_t size, phys_addr_t limit,
+ phys_addr_t alignment, unsigned int order_per_bit,
+ bool fixed, struct cma **res_cma);
+extern int cma_init_reserved_mem(phys_addr_t base,
+ phys_addr_t size, int order_per_bit,
+ struct cma **res_cma);
+extern struct page *cma_alloc(struct cma *cma, int count, unsigned int align);
+extern bool cma_release(struct cma *cma, struct page *pages, int count);
+#endif
diff --git a/include/linux/dma-contiguous.h b/include/linux/dma-contiguous.h
index ed8916f..569bbd0 100644
--- a/include/linux/dma-contiguous.h
+++ b/include/linux/dma-contiguous.h
@@ -53,23 +53,13 @@
#ifdef __KERNEL__
-struct cma {
- unsigned long base_pfn;
- unsigned long count;
- unsigned long *bitmap;
-};
+#include <linux/device.h>
+struct cma;
struct page;
-struct device;
#ifdef CONFIG_DMA_CMA
-/*
- * There is always at least global CMA area and a few optional device
- * private areas configured in kernel .config.
- */
-#define MAX_CMA_AREAS (1 + CONFIG_CMA_AREAS)
-
extern struct cma *dma_contiguous_default_area;
static inline struct cma *dev_get_cma_area(struct device *dev)
@@ -93,7 +83,8 @@
void dma_contiguous_reserve(phys_addr_t addr_limit);
int __init dma_contiguous_reserve_area(phys_addr_t size, phys_addr_t base,
- phys_addr_t limit, struct cma **res_cma);
+ phys_addr_t limit, struct cma **res_cma,
+ bool fixed);
/**
* dma_declare_contiguous() - reserve area for contiguous memory handling
@@ -113,7 +104,7 @@
{
struct cma *cma;
int ret;
- ret = dma_contiguous_reserve_area(size, base, limit, &cma);
+ ret = dma_contiguous_reserve_area(size, base, limit, &cma, true);
if (ret == 0)
dev_set_cma_area(dev, cma);
@@ -127,8 +118,6 @@
#else
-#define MAX_CMA_AREAS (0)
-
static inline struct cma *dev_get_cma_area(struct device *dev)
{
return NULL;
@@ -141,7 +130,9 @@
static inline void dma_contiguous_reserve(phys_addr_t limit) { }
static inline int dma_contiguous_reserve_area(phys_addr_t size, phys_addr_t base,
- phys_addr_t limit, struct cma **res_cma) {
+ phys_addr_t limit, struct cma **res_cma,
+ bool fixed)
+{
return -ENOSYS;
}
diff --git a/include/linux/gfp.h b/include/linux/gfp.h
index 39b81dc..f65b732 100644
--- a/include/linux/gfp.h
+++ b/include/linux/gfp.h
@@ -415,8 +415,15 @@
extern void free_contig_range(unsigned long pfn, unsigned nr_pages);
/* CMA stuff */
+extern void adjust_managed_cma_page_count(struct zone *zone, long count);
extern void init_cma_reserved_pageblock(struct page *page);
+static inline void adjust_total_cma_page_count(struct zone *zone, long count)
+{
+ zone->total_cma_pages += count;
+ adjust_managed_cma_page_count(zone, count);
+}
+
#endif
#endif /* __LINUX_GFP_H */
diff --git a/include/linux/gpio.h b/include/linux/gpio.h
index b581b13..85aa5d0 100644
--- a/include/linux/gpio.h
+++ b/include/linux/gpio.h
@@ -3,7 +3,7 @@
#include <linux/errno.h>
-/* see Documentation/gpio.txt */
+/* see Documentation/gpio/gpio-legacy.txt */
/* make these flag values available regardless of GPIO kconfig options */
#define GPIOF_DIR_OUT (0 << 0)
diff --git a/include/linux/gpio/consumer.h b/include/linux/gpio/consumer.h
index 7a8144f..bed128e 100644
--- a/include/linux/gpio/consumer.h
+++ b/include/linux/gpio/consumer.h
@@ -5,7 +5,6 @@
#include <linux/kernel.h>
struct device;
-struct gpio_chip;
/**
* Opaque descriptor for a GPIO. These are obtained using gpiod_get() and are
@@ -36,6 +35,7 @@
int gpiod_get_direction(const struct gpio_desc *desc);
int gpiod_direction_input(struct gpio_desc *desc);
int gpiod_direction_output(struct gpio_desc *desc, int value);
+int gpiod_direction_output_raw(struct gpio_desc *desc, int value);
/* Value get/set from non-sleeping context */
int gpiod_get_value(const struct gpio_desc *desc);
@@ -59,7 +59,6 @@
/* Convert between the old gpio_ and new gpiod_ interfaces */
struct gpio_desc *gpio_to_desc(unsigned gpio);
int desc_to_gpio(const struct gpio_desc *desc);
-struct gpio_chip *gpiod_to_chip(const struct gpio_desc *desc);
#else /* CONFIG_GPIOLIB */
@@ -121,6 +120,12 @@
WARN_ON(1);
return -ENOSYS;
}
+static inline int gpiod_direction_output_raw(struct gpio_desc *desc, int value)
+{
+ /* GPIO can never have been requested */
+ WARN_ON(1);
+ return -ENOSYS;
+}
static inline int gpiod_get_value(const struct gpio_desc *desc)
@@ -207,12 +212,6 @@
WARN_ON(1);
return -EINVAL;
}
-static inline struct gpio_chip *gpiod_to_chip(const struct gpio_desc *desc)
-{
- /* GPIO can never have been requested */
- WARN_ON(1);
- return ERR_PTR(-ENODEV);
-}
#endif /* CONFIG_GPIOLIB */
diff --git a/include/linux/gpio/driver.h b/include/linux/gpio/driver.h
index a3e181e..4fcd609 100644
--- a/include/linux/gpio/driver.h
+++ b/include/linux/gpio/driver.h
@@ -3,6 +3,9 @@
#include <linux/types.h>
#include <linux/module.h>
+#include <linux/irq.h>
+#include <linux/irqchip/chained_irq.h>
+#include <linux/irqdomain.h>
struct device;
struct gpio_desc;
@@ -10,6 +13,8 @@
struct device_node;
struct seq_file;
+#ifdef CONFIG_GPIOLIB
+
/**
* struct gpio_chip - abstract a GPIO controller
* @label: for diagnostics
@@ -46,7 +51,10 @@
* format specifier for an unsigned int. It is substituted by the actual
* number of the gpio.
* @can_sleep: flag must be set iff get()/set() methods sleep, as they
- * must while accessing GPIO expander chips over I2C or SPI
+ * must while accessing GPIO expander chips over I2C or SPI. This
+ * implies that if the chip supports IRQs, these IRQs need to be threaded
+ * as the chip access may sleep when e.g. reading out the IRQ status
+ * registers.
* @exported: flags if the gpiochip is exported for use from sysfs. Private.
*
* A gpio_chip can help platforms abstract various sources of GPIOs so
@@ -95,6 +103,18 @@
bool can_sleep;
bool exported;
+#ifdef CONFIG_GPIOLIB_IRQCHIP
+ /*
+ * With CONFIG_GPIOLIB_IRQCHIP we get an irqchip inside the gpiolib
+ * to handle IRQs for most practical cases.
+ */
+ struct irq_chip *irqchip;
+ struct irq_domain *irqdomain;
+ unsigned int irq_base;
+ irq_flow_handler_t irq_handler;
+ unsigned int irq_default_type;
+#endif
+
#if defined(CONFIG_OF_GPIO)
/*
* If CONFIG_OF is enabled, then all GPIO controllers described in the
@@ -129,6 +149,11 @@
int gpiod_lock_as_irq(struct gpio_desc *desc);
void gpiod_unlock_as_irq(struct gpio_desc *desc);
+struct gpio_chip *gpiod_to_chip(const struct gpio_desc *desc);
+
+struct gpio_desc *gpiochip_get_desc(struct gpio_chip *chip,
+ u16 hwnum);
+
enum gpio_lookup_flags {
GPIO_ACTIVE_HIGH = (0 << 0),
GPIO_ACTIVE_LOW = (1 << 0),
@@ -183,4 +208,30 @@
void gpiod_add_lookup_table(struct gpiod_lookup_table *table);
+#ifdef CONFIG_GPIOLIB_IRQCHIP
+
+void gpiochip_set_chained_irqchip(struct gpio_chip *gpiochip,
+ struct irq_chip *irqchip,
+ int parent_irq,
+ irq_flow_handler_t parent_handler);
+
+int gpiochip_irqchip_add(struct gpio_chip *gpiochip,
+ struct irq_chip *irqchip,
+ unsigned int first_irq,
+ irq_flow_handler_t handler,
+ unsigned int type);
+
+#endif /* CONFIG_GPIOLIB_IRQCHIP */
+
+#else /* CONFIG_GPIOLIB */
+
+static inline struct gpio_chip *gpiod_to_chip(const struct gpio_desc *desc)
+{
+ /* GPIO can never have been requested */
+ WARN_ON(1);
+ return ERR_PTR(-ENODEV);
+}
+
+#endif /* CONFIG_GPIOLIB */
+
#endif
diff --git a/include/linux/irq.h b/include/linux/irq.h
index ef1ac9f..256a006 100644
--- a/include/linux/irq.h
+++ b/include/linux/irq.h
@@ -303,6 +303,10 @@
* @irq_pm_shutdown: function called from core code on shutdown once per chip
* @irq_calc_mask: Optional function to set irq_data.mask for special cases
* @irq_print_chip: optional to print special chip info in show_interrupts
+ * @irq_request_resources: optional to request resources before calling
+ * any other callback related to this irq
+ * @irq_release_resources: optional to release resources acquired with
+ * irq_request_resources
* @flags: chip specific flags
*/
struct irq_chip {
@@ -336,6 +340,8 @@
void (*irq_calc_mask)(struct irq_data *data);
void (*irq_print_chip)(struct irq_data *data, struct seq_file *p);
+ int (*irq_request_resources)(struct irq_data *data);
+ void (*irq_release_resources)(struct irq_data *data);
unsigned long flags;
};
diff --git a/include/linux/memblock.h b/include/linux/memblock.h
index 1ef6636..59f6be0 100644
--- a/include/linux/memblock.h
+++ b/include/linux/memblock.h
@@ -221,6 +221,8 @@
#define MEMBLOCK_ALLOC_ANYWHERE (~(phys_addr_t)0)
#define MEMBLOCK_ALLOC_ACCESSIBLE 0
+phys_addr_t __init memblock_alloc_range(phys_addr_t size, phys_addr_t align,
+ phys_addr_t start, phys_addr_t end);
phys_addr_t memblock_alloc_base(phys_addr_t size, phys_addr_t align,
phys_addr_t max_addr);
phys_addr_t __memblock_alloc_base(phys_addr_t size, phys_addr_t align,
diff --git a/include/linux/mmc/host.h b/include/linux/mmc/host.h
index 99f5709..16ccf43 100644
--- a/include/linux/mmc/host.h
+++ b/include/linux/mmc/host.h
@@ -264,7 +264,6 @@
u32 caps2; /* More host capabilities */
#define MMC_CAP2_BOOTPART_NOACC (1 << 0) /* Boot partition no access */
-#define MMC_CAP2_CACHE_CTRL (1 << 1) /* Allow cache control */
#define MMC_CAP2_FULL_PWR_CYCLE (1 << 2) /* Can do full power cycle */
#define MMC_CAP2_NO_MULTI_READ (1 << 3) /* Multiblock reads don't work */
#define MMC_CAP2_NO_SLEEP_CMD (1 << 4) /* Don't allow sleep command */
diff --git a/include/linux/mmzone.h b/include/linux/mmzone.h
index 1884353..003bf3a 100644
--- a/include/linux/mmzone.h
+++ b/include/linux/mmzone.h
@@ -78,10 +78,15 @@
#define NR_MIGRATETYPE_BITS (PB_migrate_end - PB_migrate + 1)
#define MIGRATETYPE_MASK ((1UL << NR_MIGRATETYPE_BITS) - 1)
-static inline int get_pageblock_migratetype(struct page *page)
+#define get_pageblock_migratetype(page) \
+ get_pfnblock_flags_mask(page, page_to_pfn(page), \
+ PB_migrate_end, MIGRATETYPE_MASK)
+
+static inline int get_pfnblock_migratetype(struct page *page, unsigned long pfn)
{
BUILD_BUG_ON(PB_migrate_end - PB_migrate != 2);
- return get_pageblock_flags_mask(page, PB_migrate_end, MIGRATETYPE_MASK);
+ return get_pfnblock_flags_mask(page, pfn, PB_migrate_end,
+ MIGRATETYPE_MASK);
}
struct free_area {
@@ -391,6 +396,21 @@
int compact_order_failed;
#endif
+#ifdef CONFIG_CMA
+ unsigned long total_cma_pages;
+ unsigned long managed_cma_pages;
+ /*
+ * Number of allocation attempt on each normal/cma type
+ * without switching type. max_try_(normal/cma) maintain
+ * pre-calculated counter and replenish nr_try_(normal/cma)
+ * with each of them whenever both of them are 0.
+ */
+ int nr_try_normal;
+ int nr_try_cma;
+ int max_try_normal;
+ int max_try_cma;
+#endif
+
ZONE_PADDING(_pad1_)
/* Fields commonly accessed by the page reclaim scanner */
@@ -500,6 +520,15 @@
*/
int nr_migrate_reserve_block;
+#ifdef CONFIG_MEMORY_ISOLATION
+ /*
+ * Number of isolated pageblock. It is used to solve incorrect
+ * freepage counting problem due to racy retrieving migratetype
+ * of pageblock. Protected by zone->lock.
+ */
+ unsigned long nr_isolate_pageblock;
+#endif
+
/*
* rarely used fields:
*/
diff --git a/include/linux/netdevice.h b/include/linux/netdevice.h
index cf0acdf..6ed5775 100644
--- a/include/linux/netdevice.h
+++ b/include/linux/netdevice.h
@@ -56,6 +56,8 @@
struct phy_device;
/* 802.11 specific */
struct wireless_dev;
+
+struct net_bridge;
/* source back-compat hooks */
#define SET_ETHTOOL_OPS(netdev,ops) \
( (netdev)->ethtool_ops = (ops) )
@@ -1034,6 +1036,13 @@
__be16 proto, u16 vid);
int (*ndo_vlan_rx_kill_vid)(struct net_device *dev,
__be16 proto, u16 vid);
+ void (*ndo_br_join)(struct net_device *dev,
+ struct net_bridge *br);
+ void (*ndo_br_leave)(struct net_device *dev,
+ struct net_bridge *br);
+ void (*ndo_br_set_stp_state)(struct net_device *dev,
+ struct net_bridge *br,
+ unsigned int state);
#ifdef CONFIG_NET_POLL_CONTROLLER
void (*ndo_poll_controller)(struct net_device *dev);
int (*ndo_netpoll_setup)(struct net_device *dev,
diff --git a/include/linux/of.h b/include/linux/of.h
index 3f8144d..ddd1774 100644
--- a/include/linux/of.h
+++ b/include/linux/of.h
@@ -198,6 +198,8 @@
extern struct property *of_find_property(const struct device_node *np,
const char *name,
int *lenp);
+extern int of_property_count_elems_of_size(const struct device_node *np,
+ const char *propname, int elem_size);
extern int of_property_read_u32_index(const struct device_node *np,
const char *propname,
u32 index, u32 *out_value);
@@ -388,6 +390,12 @@
return NULL;
}
+static inline int of_property_count_elems_of_size(const struct device_node *np,
+ const char *propname, int elem_size)
+{
+ return -ENOSYS;
+}
+
static inline int of_property_read_u32_index(const struct device_node *np,
const char *propname, u32 index, u32 *out_value)
{
@@ -592,6 +600,74 @@
}
/**
+ * of_property_count_u8_elems - Count the number of u8 elements in a property
+ *
+ * @np: device node from which the property value is to be read.
+ * @propname: name of the property to be searched.
+ *
+ * Search for a property in a device node and count the number of u8 elements
+ * in it. Returns number of elements on sucess, -EINVAL if the property does
+ * not exist or its length does not match a multiple of u8 and -ENODATA if the
+ * property does not have a value.
+ */
+static inline int of_property_count_u8_elems(const struct device_node *np,
+ const char *propname)
+{
+ return of_property_count_elems_of_size(np, propname, sizeof(u8));
+}
+
+/**
+ * of_property_count_u16_elems - Count the number of u16 elements in a property
+ *
+ * @np: device node from which the property value is to be read.
+ * @propname: name of the property to be searched.
+ *
+ * Search for a property in a device node and count the number of u16 elements
+ * in it. Returns number of elements on sucess, -EINVAL if the property does
+ * not exist or its length does not match a multiple of u16 and -ENODATA if the
+ * property does not have a value.
+ */
+static inline int of_property_count_u16_elems(const struct device_node *np,
+ const char *propname)
+{
+ return of_property_count_elems_of_size(np, propname, sizeof(u16));
+}
+
+/**
+ * of_property_count_u32_elems - Count the number of u32 elements in a property
+ *
+ * @np: device node from which the property value is to be read.
+ * @propname: name of the property to be searched.
+ *
+ * Search for a property in a device node and count the number of u32 elements
+ * in it. Returns number of elements on sucess, -EINVAL if the property does
+ * not exist or its length does not match a multiple of u32 and -ENODATA if the
+ * property does not have a value.
+ */
+static inline int of_property_count_u32_elems(const struct device_node *np,
+ const char *propname)
+{
+ return of_property_count_elems_of_size(np, propname, sizeof(u32));
+}
+
+/**
+ * of_property_count_u64_elems - Count the number of u64 elements in a property
+ *
+ * @np: device node from which the property value is to be read.
+ * @propname: name of the property to be searched.
+ *
+ * Search for a property in a device node and count the number of u64 elements
+ * in it. Returns number of elements on sucess, -EINVAL if the property does
+ * not exist or its length does not match a multiple of u64 and -ENODATA if the
+ * property does not have a value.
+ */
+static inline int of_property_count_u64_elems(const struct device_node *np,
+ const char *propname)
+{
+ return of_property_count_elems_of_size(np, propname, sizeof(u64));
+}
+
+/**
* of_property_read_bool - Findfrom a property
* @np: device node from which the property value is to be read.
* @propname: name of the property to be searched.
diff --git a/include/linux/of_mdio.h b/include/linux/of_mdio.h
index 6fe8464..77a6e32 100644
--- a/include/linux/of_mdio.h
+++ b/include/linux/of_mdio.h
@@ -67,4 +67,19 @@
}
#endif /* CONFIG_OF */
+#if defined(CONFIG_OF) && defined(CONFIG_FIXED_PHY)
+extern int of_phy_register_fixed_link(struct device_node *np);
+extern bool of_phy_is_fixed_link(struct device_node *np);
+#else
+static inline int of_phy_register_fixed_link(struct device_node *np)
+{
+ return -ENOSYS;
+}
+static inline bool of_phy_is_fixed_link(struct device_node *np)
+{
+ return false;
+}
+#endif
+
+
#endif /* __LINUX_OF_MDIO_H */
diff --git a/include/linux/of_reserved_mem.h b/include/linux/of_reserved_mem.h
index 89226ed..4c81b84 100644
--- a/include/linux/of_reserved_mem.h
+++ b/include/linux/of_reserved_mem.h
@@ -1,21 +1,53 @@
#ifndef __OF_RESERVED_MEM_H
#define __OF_RESERVED_MEM_H
+struct device;
+struct of_phandle_args;
+struct reserved_mem_ops;
+
struct reserved_mem {
const char *name;
unsigned long fdt_node;
+ const struct reserved_mem_ops *ops;
phys_addr_t base;
phys_addr_t size;
+ void *priv;
};
+struct reserved_mem_ops {
+ void (*device_init)(struct reserved_mem *rmem,
+ struct device *dev);
+ void (*device_release)(struct reserved_mem *rmem,
+ struct device *dev);
+};
+
+typedef int (*reservedmem_of_init_fn)(struct reserved_mem *rmem);
+
+
#ifdef CONFIG_OF_RESERVED_MEM
void fdt_init_reserved_mem(void);
void fdt_reserved_mem_save_node(unsigned long node, const char *uname,
phys_addr_t base, phys_addr_t size);
+
+#define RESERVEDMEM_OF_DECLARE(name, compat, init) \
+ static const struct of_device_id __reservedmem_of_table_##name \
+ __used __section(__reservedmem_of_table) \
+ = { .compatible = compat, \
+ .data = (init == (reservedmem_of_init_fn)NULL) ? \
+ init : init }
+
#else
static inline void fdt_init_reserved_mem(void) { }
static inline void fdt_reserved_mem_save_node(unsigned long node,
const char *uname, phys_addr_t base, phys_addr_t size) { }
+
+#define RESERVEDMEM_OF_DECLARE(name, compat, init) \
+ static const struct of_device_id __reservedmem_of_table_##name \
+ __attribute__((unused)) \
+ = { .compatible = compat, \
+ .data = (init == (reservedmem_of_init_fn)NULL) ? \
+ init : init }
+
#endif
#endif /* __OF_RESERVED_MEM_H */
diff --git a/include/linux/page-isolation.h b/include/linux/page-isolation.h
index 3fff8e7..2dc1e16 100644
--- a/include/linux/page-isolation.h
+++ b/include/linux/page-isolation.h
@@ -2,6 +2,10 @@
#define __LINUX_PAGEISOLATION_H
#ifdef CONFIG_MEMORY_ISOLATION
+static inline bool has_isolate_pageblock(struct zone *zone)
+{
+ return zone->nr_isolate_pageblock;
+}
static inline bool is_migrate_isolate_page(struct page *page)
{
return get_pageblock_migratetype(page) == MIGRATE_ISOLATE;
@@ -11,6 +15,10 @@
return migratetype == MIGRATE_ISOLATE;
}
#else
+static inline bool has_isolate_pageblock(struct zone *zone)
+{
+ return false;
+}
static inline bool is_migrate_isolate_page(struct page *page)
{
return false;
diff --git a/include/linux/pageblock-flags.h b/include/linux/pageblock-flags.h
index c08730c..2baeee1 100644
--- a/include/linux/pageblock-flags.h
+++ b/include/linux/pageblock-flags.h
@@ -65,33 +65,26 @@
/* Forward declaration */
struct page;
-unsigned long get_pageblock_flags_mask(struct page *page,
+unsigned long get_pfnblock_flags_mask(struct page *page,
+ unsigned long pfn,
unsigned long end_bitidx,
unsigned long mask);
-void set_pageblock_flags_mask(struct page *page,
+
+void set_pfnblock_flags_mask(struct page *page,
unsigned long flags,
+ unsigned long pfn,
unsigned long end_bitidx,
unsigned long mask);
/* Declarations for getting and setting flags. See mm/page_alloc.c */
-static inline unsigned long get_pageblock_flags_group(struct page *page,
- int start_bitidx, int end_bitidx)
-{
- unsigned long nr_flag_bits = end_bitidx - start_bitidx + 1;
- unsigned long mask = (1 << nr_flag_bits) - 1;
-
- return get_pageblock_flags_mask(page, end_bitidx, mask);
-}
-
-static inline void set_pageblock_flags_group(struct page *page,
- unsigned long flags,
- int start_bitidx, int end_bitidx)
-{
- unsigned long nr_flag_bits = end_bitidx - start_bitidx + 1;
- unsigned long mask = (1 << nr_flag_bits) - 1;
-
- set_pageblock_flags_mask(page, flags, end_bitidx, mask);
-}
+#define get_pageblock_flags_group(page, start_bitidx, end_bitidx) \
+ get_pfnblock_flags_mask(page, page_to_pfn(page), \
+ end_bitidx, \
+ (1 << (end_bitidx - start_bitidx + 1)) - 1)
+#define set_pageblock_flags_group(page, flags, start_bitidx, end_bitidx) \
+ set_pfnblock_flags_mask(page, flags, page_to_pfn(page), \
+ end_bitidx, \
+ (1 << (end_bitidx - start_bitidx + 1)) - 1)
#ifdef CONFIG_COMPACTION
#define get_pageblock_skip(page) \
diff --git a/include/linux/phy.h b/include/linux/phy.h
index 97b4ca2..9f36068 100644
--- a/include/linux/phy.h
+++ b/include/linux/phy.h
@@ -74,6 +74,7 @@
PHY_INTERFACE_MODE_RTBI,
PHY_INTERFACE_MODE_SMII,
PHY_INTERFACE_MODE_XGMII,
+ PHY_INTERFACE_MODE_MOCA,
} phy_interface_t;
@@ -133,6 +134,9 @@
/* PHY addresses to be ignored when probing */
u32 phy_mask;
+ /* PHY addresses to ignore the TA/read failure */
+ u32 phy_ignore_ta_mask;
+
/*
* Pointer to an array of interrupts, each PHY's
* interrupt at the index matching its address
@@ -272,6 +276,7 @@
* c45_ids: 802.3-c45 Device Identifers if is_c45.
* is_c45: Set to true if this phy uses clause 45 addressing.
* is_internal: Set to true if this phy is internal to a MAC.
+ * suspended: Set to true if this phy has been suspended successfully.
* state: state of the PHY for management purposes
* dev_flags: Device-specific flags used by the PHY driver.
* addr: Bus address of PHY
@@ -308,6 +313,7 @@
struct phy_c45_device_ids c45_ids;
bool is_c45;
bool is_internal;
+ bool suspended;
enum phy_state state;
diff --git a/include/linux/phy_fixed.h b/include/linux/phy_fixed.h
index 509d8f5..ae612ac 100644
--- a/include/linux/phy_fixed.h
+++ b/include/linux/phy_fixed.h
@@ -9,15 +9,31 @@
int asym_pause;
};
+struct device_node;
+
#ifdef CONFIG_FIXED_PHY
extern int fixed_phy_add(unsigned int irq, int phy_id,
struct fixed_phy_status *status);
+extern int fixed_phy_register(unsigned int irq,
+ struct fixed_phy_status *status,
+ struct device_node *np);
+extern void fixed_phy_del(int phy_addr);
#else
static inline int fixed_phy_add(unsigned int irq, int phy_id,
struct fixed_phy_status *status)
{
return -ENODEV;
}
+static inline int fixed_phy_register(unsigned int irq,
+ struct fixed_phy_status *status,
+ struct device_node *np)
+{
+ return -ENODEV;
+}
+static inline int fixed_phy_del(int phy_addr)
+{
+ return -ENODEV;
+}
#endif /* CONFIG_FIXED_PHY */
/*
diff --git a/include/linux/serial_core.h b/include/linux/serial_core.h
index a855077..f729be9 100644
--- a/include/linux/serial_core.h
+++ b/include/linux/serial_core.h
@@ -169,7 +169,6 @@
#define UPF_BUGGY_UART ((__force upf_t) (1 << 14))
#define UPF_NO_TXEN_TEST ((__force upf_t) (1 << 15))
#define UPF_MAGIC_MULTIPLIER ((__force upf_t) (1 << 16))
-#define UPF_SAFER_LCR_WRITES ((__force upf_t) (1 << 17))
/* Port has hardware-assisted h/w flow control (iow, auto-RTS *not* auto-CTS) */
#define UPF_HARD_FLOW ((__force upf_t) (1 << 21))
/* Port has hardware-assisted s/w flow control */
diff --git a/include/linux/thermal.h b/include/linux/thermal.h
index f7e11c7..bd9c1b5 100644
--- a/include/linux/thermal.h
+++ b/include/linux/thermal.h
@@ -38,7 +38,7 @@
#define THERMAL_CSTATE_INVALID -1UL
/* No upper/lower limit requirement */
-#define THERMAL_NO_LIMIT THERMAL_CSTATE_INVALID
+#define THERMAL_NO_LIMIT ((u32)~0)
/* Unit conversion macros */
#define KELVIN_TO_CELSIUS(t) (long)(((long)t-2732 >= 0) ? \
@@ -112,6 +112,7 @@
int (*unbind) (struct thermal_zone_device *,
struct thermal_cooling_device *);
int (*get_temp) (struct thermal_zone_device *, unsigned long *);
+ int (*set_trips) (struct thermal_zone_device *, unsigned long, unsigned long);
int (*get_mode) (struct thermal_zone_device *,
enum thermal_device_mode *);
int (*set_mode) (struct thermal_zone_device *,
@@ -158,6 +159,42 @@
char name[THERMAL_NAME_LENGTH];
};
+/**
+ * struct thermal_zone_device - structure for a thermal zone
+ * @id: unique id number for each thermal zone
+ * @type: the thermal zone device type
+ * @device: &struct device for this thermal zone
+ * @trip_temp_attrs: attributes for trip points for sysfs: trip temperature
+ * @trip_type_attrs: attributes for trip points for sysfs: trip type
+ * @trip_hyst_attrs: attributes for trip points for sysfs: trip hysteresis
+ * @devdata: private pointer for device private data
+ * @trips: number of trip points the thermal zone supports
+ * @passive_delay: number of milliseconds to wait between polls when
+ * performing passive cooling. Currenty only used by the
+ * step-wise governor
+ * @polling_delay: number of milliseconds to wait between polls when
+ * checking whether trip points have been crossed (0 for
+ * interrupt driven systems)
+ * @temperature: current temperature. This is only for core code,
+ * drivers should use thermal_zone_get_temp() to get the
+ * current temperature
+ * @last_temperature: previous temperature read
+ * @emul_temperature: emulated temperature when using CONFIG_THERMAL_EMULATION
+ * @passive: 1 if you've crossed a passive trip point, 0 otherwise.
+ * Currenty only used by the step-wise governor.
+ * @forced_passive: If > 0, temperature at which to switch on all ACPI
+ * processor cooling devices. Currently only used by the
+ * step-wise governor.
+ * @ops: operations this &thermal_zone_device supports
+ * @tzp: thermal zone parameters
+ * @governor: pointer to the governor for this thermal zone
+ * @thermal_instances: list of &struct thermal_instance of this thermal zone
+ * @idr: &struct idr to generate unique id for this zone's cooling
+ * devices
+ * @lock: lock to protect thermal_instances list
+ * @node: node in thermal_tz_list (in thermal_core.c)
+ * @poll_queue: delayed work for polling
+ */
struct thermal_zone_device {
int id;
char type[THERMAL_NAME_LENGTH];
@@ -172,19 +209,27 @@
int temperature;
int last_temperature;
int emul_temperature;
+ int prev_low_trip;
+ int prev_high_trip;
int passive;
unsigned int forced_passive;
- struct thermal_zone_device_ops *ops;
+ const struct thermal_zone_device_ops *ops;
const struct thermal_zone_params *tzp;
struct thermal_governor *governor;
struct list_head thermal_instances;
struct idr idr;
- struct mutex lock; /* protect thermal_instances list */
+ struct mutex lock;
struct list_head node;
struct delayed_work poll_queue;
};
-/* Structure that holds thermal governor information */
+/**
+ * struct thermal_governor - structure that holds thermal governor information
+ * @name: name of the governor
+ * @throttle: callback called for every trip point even if temperature is
+ * below the trip point temperature
+ * @governor_list: node in thermal_governor_list (in thermal_core.c)
+ */
struct thermal_governor {
char name[THERMAL_NAME_LENGTH];
int (*throttle)(struct thermal_zone_device *tz, int trip);
@@ -243,19 +288,50 @@
enum events event;
};
+/**
+ * struct thermal_zone_of_device_ops - scallbacks for handling DT based zones
+ *
+ * Mandatory:
+ * @get_temp: a pointer to a function that reads the sensor temperature.
+ *
+ * Optional:
+ * @get_trend: a pointer to a function that reads the sensor temperature trend.
+ * @set_emul_temp: a pointer to a function that sets sensor emulated
+ * temperature.
+ */
+struct thermal_zone_of_device_ops {
+ int (*get_temp)(void *, long *);
+ int (*set_trips)(void *, unsigned long, unsigned long);
+ int (*get_trend)(void *, int trend, enum thermal_trend *);
+ int (*set_emul_temp)(void *, unsigned long);
+};
+
+/**
+ * struct thermal_trip - representation of a point in temperature domain
+ * @np: pointer to struct device_node that this trip point was created from
+ * @temperature: temperature value in miliCelsius
+ * @hysteresis: relative hysteresis in miliCelsius
+ * @type: trip point type
+ */
+
+struct thermal_trip {
+ struct device_node *np;
+ unsigned long int temperature;
+ unsigned long int hysteresis;
+ enum thermal_trip_type type;
+};
+
/* Function declarations */
#ifdef CONFIG_THERMAL_OF
struct thermal_zone_device *
-thermal_zone_of_sensor_register(struct device *dev, int id,
- void *data, int (*get_temp)(void *, long *),
- int (*get_trend)(void *, long *));
+thermal_zone_of_sensor_register(struct device *dev, int id, void *data,
+ const struct thermal_zone_of_device_ops *ops);
void thermal_zone_of_sensor_unregister(struct device *dev,
struct thermal_zone_device *tz);
#else
static inline struct thermal_zone_device *
-thermal_zone_of_sensor_register(struct device *dev, int id,
- void *data, int (*get_temp)(void *, long *),
- int (*get_trend)(void *, long *))
+thermal_zone_of_sensor_register(struct device *dev, int id, void *data,
+ const struct thermal_zone_of_device_ops *ops)
{
return NULL;
}
@@ -267,8 +343,10 @@
}
#endif
+
+#if IS_ENABLED(CONFIG_THERMAL)
struct thermal_zone_device *thermal_zone_device_register(const char *, int, int,
- void *, struct thermal_zone_device_ops *,
+ void *, const struct thermal_zone_device_ops *,
const struct thermal_zone_params *, int, int);
void thermal_zone_device_unregister(struct thermal_zone_device *);
@@ -277,6 +355,7 @@
unsigned long, unsigned long);
int thermal_zone_unbind_cooling_device(struct thermal_zone_device *, int,
struct thermal_cooling_device *);
+void thermal_zone_device_update_temp(struct thermal_zone_device *, long);
void thermal_zone_device_update(struct thermal_zone_device *);
struct thermal_cooling_device *thermal_cooling_device_register(char *, void *,
@@ -293,8 +372,61 @@
struct thermal_cooling_device *, int);
void thermal_cdev_update(struct thermal_cooling_device *);
void thermal_notify_framework(struct thermal_zone_device *, int);
+#else
+static inline struct thermal_zone_device *thermal_zone_device_register(
+ const char *type, int trips, int mask, void *devdata,
+ const struct thermal_zone_device_ops *ops,
+ const struct thermal_zone_params *tzp,
+ int passive_delay, int polling_delay)
+{ return ERR_PTR(-ENODEV); }
+static inline void thermal_zone_device_unregister(
+ struct thermal_zone_device *tz)
+{ }
+static inline int thermal_zone_bind_cooling_device(
+ struct thermal_zone_device *tz, int trip,
+ struct thermal_cooling_device *cdev,
+ unsigned long upper, unsigned long lower)
+{ return -ENODEV; }
+static inline int thermal_zone_unbind_cooling_device(
+ struct thermal_zone_device *tz, int trip,
+ struct thermal_cooling_device *cdev)
+{ return -ENODEV; }
+static inline void thermal_zone_device_update_temp(
+ struct thermal_zone_device *tz, long temp)
+{ }
+static inline void thermal_zone_device_update(struct thermal_zone_device *tz)
+{ }
+static inline struct thermal_cooling_device *
+thermal_cooling_device_register(char *type, void *devdata,
+ const struct thermal_cooling_device_ops *ops)
+{ return ERR_PTR(-ENODEV); }
+static inline struct thermal_cooling_device *
+thermal_of_cooling_device_register(struct device_node *np,
+ char *type, void *devdata, const struct thermal_cooling_device_ops *ops)
+{ return ERR_PTR(-ENODEV); }
+static inline void thermal_cooling_device_unregister(
+ struct thermal_cooling_device *cdev)
+{ }
+static inline struct thermal_zone_device *thermal_zone_get_zone_by_name(
+ const char *name)
+{ return ERR_PTR(-ENODEV); }
+static inline int thermal_zone_get_temp(
+ struct thermal_zone_device *tz, unsigned long *temp)
+{ return -ENODEV; }
+static inline int get_tz_trend(struct thermal_zone_device *tz, int trip)
+{ return -ENODEV; }
+static inline struct thermal_instance *
+get_thermal_instance(struct thermal_zone_device *tz,
+ struct thermal_cooling_device *cdev, int trip)
+{ return ERR_PTR(-ENODEV); }
+static inline void thermal_cdev_update(struct thermal_cooling_device *cdev)
+{ }
+static inline void thermal_notify_framework(struct thermal_zone_device *tz,
+ int trip)
+{ }
+#endif /* CONFIG_THERMAL */
-#ifdef CONFIG_NET
+#if defined(CONFIG_NET) && IS_ENABLED(CONFIG_THERMAL)
extern int thermal_generate_netlink_event(struct thermal_zone_device *tz,
enum events event);
#else
diff --git a/include/net/dsa.h b/include/net/dsa.h
index 3c22902..e73a515 100644
--- a/include/net/dsa.h
+++ b/include/net/dsa.h
@@ -226,6 +226,14 @@
struct ethtool_eee *e);
int (*get_eee)(struct dsa_switch *ds, int port,
struct ethtool_eee *e);
+
+ /*
+ * Bridging support
+ */
+ void (*br_join)(struct dsa_switch *ds, int port, u32 br_port_mask);
+ void (*br_leave)(struct dsa_switch *ds, int port, u32 br_port_mask);
+ void (*br_set_stp_state)(struct dsa_switch *ds, int port,
+ unsigned int state);
};
void register_switch_driver(struct dsa_switch_driver *type);
diff --git a/include/soc/brcmstb/common.h b/include/soc/brcmstb/common.h
new file mode 100644
index 0000000..b881839
--- /dev/null
+++ b/include/soc/brcmstb/common.h
@@ -0,0 +1,25 @@
+/*
+ * Copyright © 2014 NVIDIA Corporation
+ * Copyright © 2015 Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef __SOC_BRCMSTB_COMMON_H__
+#define __SOC_BRCMSTB_COMMON_H__
+
+bool soc_is_brcmstb(void);
+
+#ifdef CONFIG_PM
+int brcmstb_regsave_init(void);
+#else
+
+static inline int brcmstb_regsave_init(void)
+{
+ return 0;
+}
+#endif /* CONFIG_PM */
+
+#endif /* __SOC_BRCMSTB_COMMON_H__ */
diff --git a/include/trace/events/thermal.h b/include/trace/events/thermal.h
new file mode 100644
index 0000000..0f4f95d
--- /dev/null
+++ b/include/trace/events/thermal.h
@@ -0,0 +1,83 @@
+#undef TRACE_SYSTEM
+#define TRACE_SYSTEM thermal
+
+#if !defined(_TRACE_THERMAL_H) || defined(TRACE_HEADER_MULTI_READ)
+#define _TRACE_THERMAL_H
+
+#include <linux/thermal.h>
+#include <linux/tracepoint.h>
+
+TRACE_EVENT(thermal_temperature,
+
+ TP_PROTO(struct thermal_zone_device *tz),
+
+ TP_ARGS(tz),
+
+ TP_STRUCT__entry(
+ __string(thermal_zone, tz->type)
+ __field(int, id)
+ __field(int, temp_prev)
+ __field(int, temp)
+ ),
+
+ TP_fast_assign(
+ __assign_str(thermal_zone, tz->type);
+ __entry->id = tz->id;
+ __entry->temp_prev = tz->last_temperature;
+ __entry->temp = tz->temperature;
+ ),
+
+ TP_printk("thermal_zone=%s id=%d temp_prev=%d temp=%d",
+ __get_str(thermal_zone), __entry->id, __entry->temp_prev,
+ __entry->temp)
+);
+
+TRACE_EVENT(cdev_update,
+
+ TP_PROTO(struct thermal_cooling_device *cdev, unsigned long target),
+
+ TP_ARGS(cdev, target),
+
+ TP_STRUCT__entry(
+ __string(type, cdev->type)
+ __field(unsigned long, target)
+ ),
+
+ TP_fast_assign(
+ __assign_str(type, cdev->type);
+ __entry->target = target;
+ ),
+
+ TP_printk("type=%s target=%lu", __get_str(type), __entry->target)
+);
+
+TRACE_EVENT(thermal_zone_trip,
+
+ TP_PROTO(struct thermal_zone_device *tz, int trip,
+ enum thermal_trip_type trip_type),
+
+ TP_ARGS(tz, trip, trip_type),
+
+ TP_STRUCT__entry(
+ __string(thermal_zone, tz->type)
+ __field(int, id)
+ __field(int, trip)
+ __field(enum thermal_trip_type, trip_type)
+ ),
+
+ TP_fast_assign(
+ __assign_str(thermal_zone, tz->type);
+ __entry->id = tz->id;
+ __entry->trip = trip;
+ __entry->trip_type = trip_type;
+ ),
+
+ TP_printk("thermal_zone=%s id=%d trip=%d trip_type=%d",
+ __get_str(thermal_zone), __entry->id, __entry->trip,
+ __entry->trip_type)
+);
+
+#endif /* _TRACE_THERMAL_H */
+
+/* This part must be outside protection */
+#include <trace/define_trace.h>
diff --git a/include/uapi/linux/Kbuild b/include/uapi/linux/Kbuild
index 3ce25b5..d530ca7 100644
--- a/include/uapi/linux/Kbuild
+++ b/include/uapi/linux/Kbuild
@@ -1,5 +1,6 @@
# UAPI Header export list
header-y += byteorder/
+header-y += brcmstb/
header-y += can/
header-y += caif/
header-y += dvb/
diff --git a/include/uapi/linux/brcmstb/Kbuild b/include/uapi/linux/brcmstb/Kbuild
new file mode 100644
index 0000000..3895dd0
--- /dev/null
+++ b/include/uapi/linux/brcmstb/Kbuild
@@ -0,0 +1,2 @@
+# UAPI Header export list
+header-y += cma_driver.h
diff --git a/include/uapi/linux/serial_core.h b/include/uapi/linux/serial_core.h
index 966d163..b47dba2 100644
--- a/include/uapi/linux/serial_core.h
+++ b/include/uapi/linux/serial_core.h
@@ -54,8 +54,7 @@
#define PORT_ALTR_16550_F32 26 /* Altera 16550 UART with 32 FIFOs */
#define PORT_ALTR_16550_F64 27 /* Altera 16550 UART with 64 FIFOs */
#define PORT_ALTR_16550_F128 28 /* Altera 16550 UART with 128 FIFOs */
-#define PORT_BRCM_BUGGY_DW 29 /* Broadcom buggy DW UART */
-#define PORT_MAX_8250 29 /* max port ID */
+#define PORT_MAX_8250 28 /* max port ID */
/*
* ARM specific type numbers. These are not currently guaranteed
diff --git a/kernel/irq/manage.c b/kernel/irq/manage.c
index ebb8a9e..3a43291 100644
--- a/kernel/irq/manage.c
+++ b/kernel/irq/manage.c
@@ -891,6 +891,23 @@
}
}
+static int irq_request_resources(struct irq_desc *desc)
+{
+ struct irq_data *d = &desc->irq_data;
+ struct irq_chip *c = d->chip;
+
+ return c->irq_request_resources ? c->irq_request_resources(d) : 0;
+}
+
+static void irq_release_resources(struct irq_desc *desc)
+{
+ struct irq_data *d = &desc->irq_data;
+ struct irq_chip *c = d->chip;
+
+ if (c->irq_release_resources)
+ c->irq_release_resources(d);
+}
+
/*
* Internal function to register an irqaction - typically used to
* allocate special interrupts that are part of the architecture.
@@ -1086,6 +1103,13 @@
}
if (!shared) {
+ ret = irq_request_resources(desc);
+ if (ret) {
+ pr_err("Failed to request resources for %s (irq %d) on irqchip %s\n",
+ new->name, irq, desc->irq_data.chip->name);
+ goto out_mask;
+ }
+
init_waitqueue_head(&desc->wait_for_threads);
/* Setup the type (level, edge polarity) if configured: */
@@ -1256,8 +1280,10 @@
*action_ptr = action->next;
/* If this was the last handler, shut down the IRQ line: */
- if (!desc->action)
+ if (!desc->action) {
irq_shutdown(desc);
+ irq_release_resources(desc);
+ }
#ifdef CONFIG_SMP
/* make sure affinity_hint is cleaned up */
diff --git a/kernel/power/suspend.c b/kernel/power/suspend.c
index 5455d5c..de6befe 100644
--- a/kernel/power/suspend.c
+++ b/kernel/power/suspend.c
@@ -26,6 +26,7 @@
#include <linux/syscore_ops.h>
#include <linux/ftrace.h>
#include <trace/events/power.h>
+#include <linux/moduleparam.h>
#include "power.h"
@@ -103,12 +104,20 @@
}
EXPORT_SYMBOL_GPL(suspend_valid_only_mem);
+#ifdef CONFIG_PM_DEBUG
+static unsigned int pm_test_delay = 5;
+module_param(pm_test_delay, uint, 0644);
+MODULE_PARM_DESC(pm_test_delay,
+ "Number of seconds to wait before resuming from suspend test");
+#endif
+
static int suspend_test(int level)
{
#ifdef CONFIG_PM_DEBUG
if (pm_test_level == level) {
- printk(KERN_INFO "suspend debug: Waiting for 5 seconds.\n");
- mdelay(5000);
+ printk(KERN_INFO "suspend debug: Waiting for %d second(s).\n",
+ pm_test_delay);
+ mdelay(pm_test_delay * 1000);
return 1;
}
#endif /* !CONFIG_PM_DEBUG */
diff --git a/lib/show_mem.c b/lib/show_mem.c
index 0922579..5803eac 100644
--- a/lib/show_mem.c
+++ b/lib/show_mem.c
@@ -8,6 +8,7 @@
#include <linux/mm.h>
#include <linux/nmi.h>
#include <linux/quicklist.h>
+#include <linux/cma.h>
void show_mem(unsigned int filter)
{
@@ -38,7 +39,12 @@
printk("%lu pages RAM\n", total);
printk("%lu pages HighMem/MovableOnly\n", highmem);
+#ifdef CONFIG_CMA
+ printk("%lu pages reserved\n", (reserved - totalcma_pages));
+ printk("%lu pages cma reserved\n", totalcma_pages);
+#else
printk("%lu pages reserved\n", reserved);
+#endif
#ifdef CONFIG_QUICKLIST
printk("%lu pages in pagetable cache\n",
quicklist_total_size());
diff --git a/mm/Kconfig b/mm/Kconfig
index 0862816..bda0400 100644
--- a/mm/Kconfig
+++ b/mm/Kconfig
@@ -514,6 +514,17 @@
processing calls such as dma_alloc_from_contiguous().
This option does not affect warning and error messages.
+config CMA_AREAS
+ int "Maximum count of the CMA areas"
+ depends on CMA
+ default 7
+ help
+ CMA allows to create CMA areas for particular purpose, mainly,
+ used as device private area. This parameter sets the maximum
+ number of CMA area in the system.
+
+ If unsure, leave the default value "7".
+
config ZBUD
tristate
default n
diff --git a/mm/Makefile b/mm/Makefile
index c561f1f..2bad2e0 100644
--- a/mm/Makefile
+++ b/mm/Makefile
@@ -61,3 +61,4 @@
obj-$(CONFIG_MEMORY_ISOLATION) += page_isolation.o
obj-$(CONFIG_ZBUD) += zbud.o
obj-$(CONFIG_ZSMALLOC) += zsmalloc.o
+obj-$(CONFIG_CMA) += cma.o
diff --git a/mm/cma.c b/mm/cma.c
new file mode 100644
index 0000000..1e810f0
--- /dev/null
+++ b/mm/cma.c
@@ -0,0 +1,429 @@
+/*
+ * Contiguous Memory Allocator
+ *
+ * Copyright (c) 2010-2011 by Samsung Electronics.
+ * Copyright IBM Corporation, 2013
+ * Copyright LG Electronics Inc., 2014
+ * Written by:
+ * Marek Szyprowski <m.szyprowski@samsung.com>
+ * Michal Nazarewicz <mina86@mina86.com>
+ * Aneesh Kumar K.V <aneesh.kumar@linux.vnet.ibm.com>
+ * Joonsoo Kim <iamjoonsoo.kim@lge.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License or (at your optional) any later version of the license.
+ */
+
+#define pr_fmt(fmt) "cma: " fmt
+
+#ifdef CONFIG_CMA_DEBUG
+#ifndef DEBUG
+# define DEBUG
+#endif
+#endif
+
+#include <linux/memblock.h>
+#include <linux/err.h>
+#include <linux/mm.h>
+#include <linux/mutex.h>
+#include <linux/sizes.h>
+#include <linux/slab.h>
+#include <linux/log2.h>
+#include <linux/cma.h>
+#include <linux/highmem.h>
+
+static struct cma cma_areas[MAX_CMA_AREAS];
+static unsigned cma_area_count;
+static DEFINE_MUTEX(cma_mutex);
+
+phys_addr_t cma_get_base(struct cma *cma)
+{
+ return PFN_PHYS(cma->base_pfn);
+}
+
+unsigned long cma_get_size(struct cma *cma)
+{
+ return cma->count << PAGE_SHIFT;
+}
+
+static unsigned long cma_bitmap_aligned_mask(struct cma *cma, int align_order)
+{
+ if (align_order <= cma->order_per_bit)
+ return 0;
+ return (1UL << (align_order - cma->order_per_bit)) - 1;
+}
+
+/*
+ * Find a PFN aligned to the specified order and return an offset represented in
+ * order_per_bits.
+ */
+static unsigned long cma_bitmap_aligned_offset(struct cma *cma, int align_order)
+{
+ if (align_order <= cma->order_per_bit)
+ return 0;
+
+ return (ALIGN(cma->base_pfn, (1UL << align_order))
+ - cma->base_pfn) >> cma->order_per_bit;
+}
+
+static unsigned long cma_bitmap_maxno(struct cma *cma)
+{
+ return cma->count >> cma->order_per_bit;
+}
+
+static unsigned long cma_bitmap_pages_to_bits(struct cma *cma,
+ unsigned long pages)
+{
+ return ALIGN(pages, 1UL << cma->order_per_bit) >> cma->order_per_bit;
+}
+
+static void cma_clear_bitmap(struct cma *cma, unsigned long pfn, int count)
+{
+ unsigned long bitmap_no, bitmap_count;
+
+ bitmap_no = (pfn - cma->base_pfn) >> cma->order_per_bit;
+ bitmap_count = cma_bitmap_pages_to_bits(cma, count);
+
+ mutex_lock(&cma->lock);
+ bitmap_clear(cma->bitmap, bitmap_no, bitmap_count);
+ mutex_unlock(&cma->lock);
+}
+
+static int __init cma_activate_area(struct cma *cma)
+{
+ int bitmap_size = BITS_TO_LONGS(cma_bitmap_maxno(cma)) * sizeof(long);
+ unsigned long base_pfn = cma->base_pfn, pfn = base_pfn;
+ unsigned i = cma->count >> pageblock_order;
+ struct zone *zone;
+
+ cma->bitmap = kzalloc(bitmap_size, GFP_KERNEL);
+
+ if (!cma->bitmap)
+ return -ENOMEM;
+
+ WARN_ON_ONCE(!pfn_valid(pfn));
+ zone = page_zone(pfn_to_page(pfn));
+
+ do {
+ unsigned j;
+
+ base_pfn = pfn;
+ for (j = pageblock_nr_pages; j; --j, pfn++) {
+ WARN_ON_ONCE(!pfn_valid(pfn));
+ /*
+ * alloc_contig_range requires the pfn range
+ * specified to be in the same zone. Make this
+ * simple by forcing the entire CMA resv range
+ * to be in the same zone.
+ */
+ if (page_zone(pfn_to_page(pfn)) != zone)
+ goto err;
+ }
+ init_cma_reserved_pageblock(pfn_to_page(base_pfn));
+ } while (--i);
+ adjust_total_cma_page_count(zone, cma->count);
+
+ mutex_init(&cma->lock);
+ return 0;
+
+err:
+ kfree(cma->bitmap);
+ cma->count = 0;
+ return -EINVAL;
+}
+
+static int __init cma_init_reserved_areas(void)
+{
+ int i;
+
+ for (i = 0; i < cma_area_count; i++) {
+ int ret = cma_activate_area(&cma_areas[i]);
+
+ if (ret)
+ return ret;
+ }
+
+ return 0;
+}
+core_initcall(cma_init_reserved_areas);
+
+/**
+ * cma_init_reserved_mem() - create custom contiguous area from reserved memory
+ * @base: Base address of the reserved area
+ * @size: Size of the reserved area (in bytes),
+ * @order_per_bit: Order of pages represented by one bit on bitmap.
+ * @res_cma: Pointer to store the created cma region.
+ *
+ * This function creates custom contiguous area from already reserved memory.
+ */
+int __init cma_init_reserved_mem(phys_addr_t base, phys_addr_t size,
+ int order_per_bit, struct cma **res_cma)
+{
+ struct cma *cma;
+ phys_addr_t alignment;
+
+ /* Sanity checks */
+ if (cma_area_count == ARRAY_SIZE(cma_areas)) {
+ pr_err("Not enough slots for CMA reserved regions!\n");
+ return -ENOSPC;
+ }
+
+ if (!size || !memblock_is_region_reserved(base, size))
+ return -EINVAL;
+
+ /* ensure minimal alignment requied by mm core */
+ alignment = PAGE_SIZE << max(MAX_ORDER - 1, pageblock_order);
+
+ /* alignment should be aligned with order_per_bit */
+ if (!IS_ALIGNED(alignment >> PAGE_SHIFT, 1 << order_per_bit))
+ return -EINVAL;
+
+ if (ALIGN(base, alignment) != base || ALIGN(size, alignment) != size)
+ return -EINVAL;
+
+ /*
+ * Each reserved area must be initialised later, when more kernel
+ * subsystems (like slab allocator) are available.
+ */
+ cma = &cma_areas[cma_area_count];
+ cma->base_pfn = PFN_DOWN(base);
+ cma->count = size >> PAGE_SHIFT;
+ cma->order_per_bit = order_per_bit;
+ *res_cma = cma;
+ cma_area_count++;
+
+ return 0;
+}
+
+/**
+ * cma_declare_contiguous() - reserve custom contiguous area
+ * @base: Base address of the reserved area optional, use 0 for any
+ * @size: Size of the reserved area (in bytes),
+ * @limit: End address of the reserved memory (optional, 0 for any).
+ * @alignment: Alignment for the CMA area, should be power of 2 or zero
+ * @order_per_bit: Order of pages represented by one bit on bitmap.
+ * @fixed: hint about where to place the reserved area
+ * @res_cma: Pointer to store the created cma region.
+ *
+ * This function reserves memory from early allocator. It should be
+ * called by arch specific code once the early allocator (memblock or bootmem)
+ * has been activated and all other subsystems have already allocated/reserved
+ * memory. This function allows to create custom reserved areas.
+ *
+ * If @fixed is true, reserve contiguous area at exactly @base. If false,
+ * reserve in range from @base to @limit.
+ */
+int __init cma_declare_contiguous(phys_addr_t base,
+ phys_addr_t size, phys_addr_t limit,
+ phys_addr_t alignment, unsigned int order_per_bit,
+ bool fixed, struct cma **res_cma)
+{
+ phys_addr_t memblock_end = memblock_end_of_DRAM();
+ phys_addr_t highmem_start = __pa(high_memory);
+ int ret = 0;
+
+ pr_debug("%s(size %pa, base %pa, limit %pa alignment %pa)\n",
+ __func__, &size, &base, &limit, &alignment);
+
+ if (cma_area_count == ARRAY_SIZE(cma_areas)) {
+ pr_err("Not enough slots for CMA reserved regions!\n");
+ return -ENOSPC;
+ }
+
+ if (!size)
+ return -EINVAL;
+
+ if (alignment && !is_power_of_2(alignment))
+ return -EINVAL;
+
+ /*
+ * Sanitise input arguments.
+ * Pages both ends in CMA area could be merged into adjacent unmovable
+ * migratetype page by page allocator's buddy algorithm. In the case,
+ * you couldn't get a contiguous memory, which is not what we want.
+ */
+ alignment = max(alignment,
+ (phys_addr_t)PAGE_SIZE << max(MAX_ORDER - 1, pageblock_order));
+ base = ALIGN(base, alignment);
+ size = ALIGN(size, alignment);
+ limit &= ~(alignment - 1);
+
+ if (!base)
+ fixed = false;
+
+ /* size should be aligned with order_per_bit */
+ if (!IS_ALIGNED(size >> PAGE_SHIFT, 1 << order_per_bit))
+ return -EINVAL;
+
+ /*
+ * If allocating at a fixed base the request region must not cross the
+ * low/high memory boundary.
+ */
+ if (fixed && base < highmem_start && base + size > highmem_start) {
+ ret = -EINVAL;
+ pr_err("Region at %pa defined on low/high memory boundary (%pa)\n",
+ &base, &highmem_start);
+ goto err;
+ }
+
+ /*
+ * If the limit is unspecified or above the memblock end, its effective
+ * value will be the memblock end. Set it explicitly to simplify further
+ * checks.
+ */
+ if (limit == 0 || limit > memblock_end)
+ limit = memblock_end;
+
+ /* Reserve memory */
+ if (fixed) {
+ if (memblock_is_region_reserved(base, size) ||
+ memblock_reserve(base, size) < 0) {
+ ret = -EBUSY;
+ goto err;
+ }
+ } else {
+ phys_addr_t addr = 0;
+
+ /*
+ * All pages in the reserved area must come from the same zone.
+ * If the requested region crosses the low/high memory boundary,
+ * try allocating from high memory first and fall back to low
+ * memory in case of failure.
+ */
+ if (base < highmem_start && limit > highmem_start) {
+ addr = memblock_alloc_range(size, alignment,
+ highmem_start, limit);
+ limit = highmem_start;
+ }
+
+ if (!addr) {
+ addr = memblock_alloc_range(size, alignment, base,
+ limit);
+ if (!addr) {
+ ret = -ENOMEM;
+ goto err;
+ }
+ }
+
+ base = addr;
+ }
+
+ ret = cma_init_reserved_mem(base, size, order_per_bit, res_cma);
+ if (ret)
+ goto err;
+
+ totalcma_pages += (size / PAGE_SIZE);
+ pr_info("Reserved %ld MiB at %pa\n", (unsigned long)size / SZ_1M,
+ &base);
+ return 0;
+
+err:
+ pr_err("Failed to reserve %ld MiB\n", (unsigned long)size / SZ_1M);
+ return ret;
+}
+
+/**
+ * cma_alloc() - allocate pages from contiguous area
+ * @cma: Contiguous memory region for which the allocation is performed.
+ * @count: Requested number of pages.
+ * @align: Requested alignment of pages (in PAGE_SIZE order).
+ *
+ * This function allocates part of contiguous memory on specific
+ * contiguous memory area.
+ */
+struct page *cma_alloc(struct cma *cma, int count, unsigned int align)
+{
+ unsigned long mask, offset, pfn, start = 0;
+ unsigned long bitmap_maxno, bitmap_no, bitmap_count;
+ struct page *page = NULL;
+ int ret;
+
+ if (!cma || !cma->count)
+ return NULL;
+
+ pr_debug("%s(cma %p, count %d, align %d)\n", __func__, (void *)cma,
+ count, align);
+
+ if (!count)
+ return NULL;
+
+ mask = cma_bitmap_aligned_mask(cma, align);
+ offset = cma_bitmap_aligned_offset(cma, align);
+ bitmap_maxno = cma_bitmap_maxno(cma);
+ bitmap_count = cma_bitmap_pages_to_bits(cma, count);
+
+ for (;;) {
+ mutex_lock(&cma->lock);
+ bitmap_no = bitmap_find_next_zero_area_off(cma->bitmap,
+ bitmap_maxno, start, bitmap_count, mask,
+ offset);
+ if (bitmap_no >= bitmap_maxno) {
+ mutex_unlock(&cma->lock);
+ break;
+ }
+ bitmap_set(cma->bitmap, bitmap_no, bitmap_count);
+ /*
+ * It's safe to drop the lock here. We've marked this region for
+ * our exclusive use. If the migration fails we will take the
+ * lock again and unmark it.
+ */
+ mutex_unlock(&cma->lock);
+
+ pfn = cma->base_pfn + (bitmap_no << cma->order_per_bit);
+ mutex_lock(&cma_mutex);
+ ret = alloc_contig_range(pfn, pfn + count, MIGRATE_CMA);
+ mutex_unlock(&cma_mutex);
+ if (ret == 0) {
+ page = pfn_to_page(pfn);
+ adjust_managed_cma_page_count(page_zone(page), -count);
+ break;
+ }
+
+ cma_clear_bitmap(cma, pfn, count);
+ if (ret != -EBUSY)
+ break;
+
+ pr_debug("%s(): memory range at %p is busy, retrying\n",
+ __func__, pfn_to_page(pfn));
+ /* try again with a bit different memory target */
+ start = bitmap_no + mask + 1;
+ }
+
+ pr_debug("%s(): returned %p\n", __func__, page);
+ return page;
+}
+
+/**
+ * cma_release() - release allocated pages
+ * @cma: Contiguous memory region for which the allocation is performed.
+ * @pages: Allocated pages.
+ * @count: Number of allocated pages.
+ *
+ * This function releases memory allocated by alloc_cma().
+ * It returns false when provided pages do not belong to contiguous area and
+ * true otherwise.
+ */
+bool cma_release(struct cma *cma, struct page *pages, int count)
+{
+ unsigned long pfn;
+
+ if (!cma || !pages)
+ return false;
+
+ pr_debug("%s(page %p)\n", __func__, (void *)pages);
+
+ pfn = page_to_pfn(pages);
+
+ if (pfn < cma->base_pfn || pfn >= cma->base_pfn + cma->count)
+ return false;
+
+ VM_BUG_ON(pfn + count > cma->base_pfn + cma->count);
+
+ free_contig_range(pfn, count);
+ adjust_managed_cma_page_count(page_zone(pages), count);
+ cma_clear_bitmap(cma, pfn, count);
+
+ return true;
+}
diff --git a/mm/internal.h b/mm/internal.h
index 1a8a0d4..660c434 100644
--- a/mm/internal.h
+++ b/mm/internal.h
@@ -108,6 +108,31 @@
/*
* in mm/page_alloc.c
*/
+
+/*
+ * Locate the struct page for both the matching buddy in our
+ * pair (buddy1) and the combined O(n+1) page they form (page).
+ *
+ * 1) Any buddy B1 will have an order O twin B2 which satisfies
+ * the following equation:
+ * B2 = B1 ^ (1 << O)
+ * For example, if the starting buddy (buddy2) is #8 its order
+ * 1 buddy is #10:
+ * B2 = 8 ^ (1 << 1) = 8 ^ 2 = 10
+ *
+ * 2) Any buddy B will have an order O+1 parent P which
+ * satisfies the following equation:
+ * P = B & ~(1 << O)
+ *
+ * Assumption: *_mem_map is contiguous at least up to MAX_ORDER
+ */
+static inline unsigned long
+__find_buddy_index(unsigned long page_idx, unsigned int order)
+{
+ return page_idx ^ (1 << order);
+}
+
+extern int __isolate_free_page(struct page *page, unsigned int order);
extern void __free_pages_bootmem(struct page *page, unsigned int order);
extern void prep_compound_page(struct page *page, unsigned long order);
#ifdef CONFIG_MEMORY_FAILURE
diff --git a/mm/memblock.c b/mm/memblock.c
index 0739dc1..dfee4aa 100644
--- a/mm/memblock.c
+++ b/mm/memblock.c
@@ -974,22 +974,35 @@
}
#endif /* CONFIG_HAVE_MEMBLOCK_NODE_MAP */
-static phys_addr_t __init memblock_alloc_base_nid(phys_addr_t size,
- phys_addr_t align, phys_addr_t max_addr,
- int nid)
+static phys_addr_t __init memblock_alloc_range_nid(phys_addr_t size,
+ phys_addr_t align, phys_addr_t start,
+ phys_addr_t end, int nid)
{
phys_addr_t found;
if (!align)
align = SMP_CACHE_BYTES;
- found = memblock_find_in_range_node(size, align, 0, max_addr, nid);
+ found = memblock_find_in_range_node(size, align, start, end, nid);
if (found && !memblock_reserve(found, size))
return found;
return 0;
}
+phys_addr_t __init memblock_alloc_range(phys_addr_t size, phys_addr_t align,
+ phys_addr_t start, phys_addr_t end)
+{
+ return memblock_alloc_range_nid(size, align, start, end, NUMA_NO_NODE);
+}
+
+static phys_addr_t __init memblock_alloc_base_nid(phys_addr_t size,
+ phys_addr_t align, phys_addr_t max_addr,
+ int nid)
+{
+ return memblock_alloc_range_nid(size, align, 0, max_addr, nid);
+}
+
phys_addr_t __init memblock_alloc_nid(phys_addr_t size, phys_addr_t align, int nid)
{
return memblock_alloc_base_nid(size, align, MEMBLOCK_ALLOC_ACCESSIBLE, nid);
diff --git a/mm/memory.c b/mm/memory.c
index a3568c7..41e7e6f 100644
--- a/mm/memory.c
+++ b/mm/memory.c
@@ -62,6 +62,7 @@
#include <linux/dma-debug.h>
#ifdef CONFIG_BRCMSTB
#include <linux/brcmstb/cma_driver.h>
+#include <linux/brcmstb/bmem.h>
#endif
#include <asm/io.h>
@@ -1646,17 +1647,30 @@
}
#if defined(CONFIG_BRCMSTB)
-static int cma_get_page(struct mm_struct *mm, struct vm_area_struct *vma,
+/*
+ * Special handling for __get_user_pages() on BMEM or CMA reserved memory:
+ *
+ * 1) Override the VM_IO | VM_PFNMAP sanity checks
+ * 2) No cache flushes (this is explicitly under application control)
+ * 3) vm_normal_page() does not work on these regions
+ * 4) Don't need to worry about any kinds of faults; pages are always present
+ *
+ * The vanilla kernel behavior was to prohibit O_DIRECT operations on our
+ * BMEM or CMA regions, but direct I/O is absolutely required for PVR and
+ * video playback from SATA/USB.
+ */
+static int brcmstb_get_page(struct mm_struct *mm, struct vm_area_struct *vma,
unsigned long start, struct page **page)
{
-#if defined(CONFIG_CMA)
+#if defined(CONFIG_BRCMSTB_BMEM) || defined(CONFIG_BRCMSTB_CMA)
const unsigned long pg = start & PAGE_MASK;
int ret = -EFAULT;
pgd_t *pgd;
pud_t *pud;
pmd_t *pmd;
pte_t *pte;
- struct page *tmp_page;
+ struct page *tmp_page __maybe_unused;
+ unsigned long pfn;
pgd = pgd_offset(mm, pg);
BUG_ON(pgd_none(*pgd));
@@ -1668,16 +1682,23 @@
return ret;
pte = pte_offset_map(pmd, pg);
- if (!pte)
- return ret;
-
if (pte_none(*pte))
goto out;
- tmp_page = pte_page(*pte);
+ pfn = pte_pfn(*pte);
+ if (!pfn_valid(pfn))
+ goto out;
+
+ tmp_page = pfn_to_page(pfn);
if (!tmp_page)
goto out;
+#ifdef CONFIG_BRCMSTB_BMEM
+ if (likely(bmem_find_region(pfn << PAGE_SHIFT, PAGE_SIZE) >= 0))
+ goto found_page;
+#endif
+
+#ifdef CONFIG_CMA
if (!page_count(tmp_page))
goto out;
@@ -1685,8 +1706,10 @@
goto out;
if (get_pageblock_migratetype(tmp_page) != MIGRATE_CMA)
- goto out;
+ goto found_page;
+#endif
+found_page:
if (page) {
*page = tmp_page;
get_page(*page);
@@ -1698,9 +1721,9 @@
return ret;
#else
return -ENOSYS;
-#endif
+#endif /* defined(CONFIG_BRCMSTB_BMEM) || defined(CONFIG_BRCMSTB_CMA) */
}
-#endif
+#endif /* defined(CONFIG_BRCMSTB) */
/**
* __get_user_pages() - pin user pages in memory
@@ -1841,9 +1864,9 @@
}
#ifdef CONFIG_BRCMSTB
- /* handle direct I/O on CMA regions */
- if (vma && !cma_get_page(mm, vma, start,
- pages ? &pages[i] : NULL)) {
+ /* handle direct I/O on CMA or BMEM regions */
+ if (vma && (!brcmstb_get_page(mm, vma, start,
+ pages ? &pages[i] : NULL))) {
if (vmas)
vmas[i] = vma;
i++;
diff --git a/mm/page_alloc.c b/mm/page_alloc.c
index 4b25829..15ee981 100644
--- a/mm/page_alloc.c
+++ b/mm/page_alloc.c
@@ -111,6 +111,7 @@
unsigned long totalram_pages __read_mostly;
unsigned long totalreserve_pages __read_mostly;
+unsigned long totalcma_pages __read_mostly;
/*
* When calculating the number of globally allowed dirty pages, there
* is a certain number of per-zone reserves that should not be
@@ -465,29 +466,6 @@
}
/*
- * Locate the struct page for both the matching buddy in our
- * pair (buddy1) and the combined O(n+1) page they form (page).
- *
- * 1) Any buddy B1 will have an order O twin B2 which satisfies
- * the following equation:
- * B2 = B1 ^ (1 << O)
- * For example, if the starting buddy (buddy2) is #8 its order
- * 1 buddy is #10:
- * B2 = 8 ^ (1 << 1) = 8 ^ 2 = 10
- *
- * 2) Any buddy B will have an order O+1 parent P which
- * satisfies the following equation:
- * P = B & ~(1 << O)
- *
- * Assumption: *_mem_map is contiguous at least up to MAX_ORDER
- */
-static inline unsigned long
-__find_buddy_index(unsigned long page_idx, unsigned int order)
-{
- return page_idx ^ (1 << order);
-}
-
-/*
* This function checks whether a page is free && is the buddy
* we can do coalesce a page and its buddy if
* (a) the buddy is not in a hole &&
@@ -549,6 +527,7 @@
*/
static inline void __free_one_page(struct page *page,
+ unsigned long pfn,
struct zone *zone, unsigned int order,
int migratetype)
{
@@ -556,6 +535,7 @@
unsigned long combined_idx;
unsigned long uninitialized_var(buddy_idx);
struct page *buddy;
+ int max_order = MAX_ORDER;
VM_BUG_ON(!zone_is_initialized(zone));
@@ -564,13 +544,24 @@
return;
VM_BUG_ON(migratetype == -1);
+ if (is_migrate_isolate(migratetype)) {
+ /*
+ * We restrict max order of merging to prevent merge
+ * between freepages on isolate pageblock and normal
+ * pageblock. Without this, pageblock isolation
+ * could cause incorrect freepage accounting.
+ */
+ max_order = min(MAX_ORDER, pageblock_order + 1);
+ } else {
+ __mod_zone_freepage_state(zone, 1 << order, migratetype);
+ }
- page_idx = page_to_pfn(page) & ((1 << MAX_ORDER) - 1);
+ page_idx = pfn & ((1 << max_order) - 1);
VM_BUG_ON_PAGE(page_idx & ((1 << order) - 1), page);
VM_BUG_ON_PAGE(bad_range(zone, page), page);
- while (order < MAX_ORDER-1) {
+ while (order < max_order - 1) {
buddy_idx = __find_buddy_index(page_idx, order);
buddy = page + (buddy_idx - page_idx);
if (!page_is_buddy(page, buddy, order))
@@ -699,28 +690,30 @@
/* must delete as __free_one_page list manipulates */
list_del(&page->lru);
mt = get_freepage_migratetype(page);
+ if (unlikely(has_isolate_pageblock(zone)))
+ mt = get_pageblock_migratetype(page);
+
/* MIGRATE_MOVABLE list may include MIGRATE_RESERVEs */
- __free_one_page(page, zone, 0, mt);
+ __free_one_page(page, page_to_pfn(page), zone, 0, mt);
trace_mm_page_pcpu_drain(page, 0, mt);
- if (likely(!is_migrate_isolate_page(page))) {
- __mod_zone_page_state(zone, NR_FREE_PAGES, 1);
- if (is_migrate_cma(mt))
- __mod_zone_page_state(zone, NR_FREE_CMA_PAGES, 1);
- }
} while (--to_free && --batch_free && !list_empty(list));
}
spin_unlock(&zone->lock);
}
-static void free_one_page(struct zone *zone, struct page *page, int order,
+static void free_one_page(struct zone *zone,
+ struct page *page, unsigned long pfn,
+ int order,
int migratetype)
{
spin_lock(&zone->lock);
zone->pages_scanned = 0;
- __free_one_page(page, zone, order, migratetype);
- if (unlikely(!is_migrate_isolate(migratetype)))
- __mod_zone_freepage_state(zone, 1 << order, migratetype);
+ if (unlikely(has_isolate_pageblock(zone) ||
+ is_migrate_isolate(migratetype))) {
+ migratetype = get_pfnblock_migratetype(page, pfn);
+ }
+ __free_one_page(page, pfn, zone, order, migratetype);
spin_unlock(&zone->lock);
}
@@ -755,15 +748,16 @@
{
unsigned long flags;
int migratetype;
+ unsigned long pfn = page_to_pfn(page);
if (!free_pages_prepare(page, order))
return;
local_irq_save(flags);
__count_vm_events(PGFREE, 1 << order);
- migratetype = get_pageblock_migratetype(page);
+ migratetype = get_pfnblock_migratetype(page, pfn);
set_freepage_migratetype(page, migratetype);
- free_one_page(page_zone(page), page, order, migratetype);
+ free_one_page(page_zone(page), page, pfn, order, migratetype);
local_irq_restore(flags);
}
@@ -788,6 +782,62 @@
}
#ifdef CONFIG_CMA
+void adjust_managed_cma_page_count(struct zone *zone, long count)
+{
+ unsigned long flags;
+ unsigned long total, cma, normal;
+
+ spin_lock_irqsave(&zone->lock, flags);
+ zone->managed_cma_pages += count;
+
+ total = zone->managed_pages;
+ cma = zone->managed_cma_pages;
+ normal = total - zone->total_cma_pages;
+
+ /* No cma pages, so do only normal allocation */
+ if (cma == 0) {
+ zone->max_try_normal = pageblock_nr_pages;
+ zone->max_try_cma = 0;
+ goto out;
+ }
+
+ /* No movable pages, so only do CMA allocation */
+ if (normal == 0) {
+ zone->max_try_cma = pageblock_nr_pages;
+ zone->max_try_normal = 0;
+ goto out;
+ }
+
+ /*
+ * We want to consume cma pages with well balanced ratio so that
+ * we have consumed enough cma pages before the reclaim. For this
+ * purpose, we can use the ratio, normal : cma. And we doesn't
+ * want to switch too frequently, because it prevent allocated pages
+ * from beging successive and it is bad for some sorts of devices.
+ * I choose pageblock_nr_pages for the minimum amount of successive
+ * allocation because it is the size of a huge page and fragmentation
+ * avoidance is implemented based on this size.
+ *
+ * To meet above criteria, I derive following equation.
+ *
+ * if (normal > cma) then; normal : cma = X : pageblock_nr_pages
+ * else (normal <= cma) then; normal : cma = pageblock_nr_pages : X
+ */
+ if (normal > cma) {
+ zone->max_try_normal = normal * pageblock_nr_pages / cma;
+ zone->max_try_cma = pageblock_nr_pages;
+ } else {
+ zone->max_try_normal = pageblock_nr_pages;
+ zone->max_try_cma = cma * pageblock_nr_pages / normal;
+ }
+
+out:
+ zone->nr_try_normal = zone->max_try_normal;
+ zone->nr_try_cma = zone->max_try_cma;
+
+ spin_unlock_irqrestore(&zone->lock, flags);
+}
+
/* Free whole pageblock and set its migration type to MIGRATE_CMA. */
void __init init_cma_reserved_pageblock(struct page *page)
{
@@ -1157,6 +1207,52 @@
return NULL;
}
+#ifdef CONFIG_CMA
+static inline int __choose_rmqueue_migratetype(struct zone *zone, unsigned int order)
+{
+ bool retried = false;
+
+retry:
+ if (zone->nr_try_normal > 0) {
+ zone->nr_try_normal -= 1 << order;
+ return MIGRATE_MOVABLE;
+ }
+
+ if (zone->nr_try_cma > 0) {
+ zone->nr_try_cma -= 1 << order;
+ return MIGRATE_CMA;
+ }
+
+ /* Reset counter */
+ zone->nr_try_normal = zone->max_try_normal;
+ zone->nr_try_cma = zone->max_try_cma;
+
+ if (!retried) {
+ retried = true;
+ goto retry;
+ }
+
+ zone->nr_try_normal -= 1 << order;
+ return MIGRATE_MOVABLE;
+}
+
+static inline int choose_rmqueue_migratetype(struct zone *zone,
+ unsigned int order, int migratetype)
+{
+ if (migratetype == MIGRATE_MOVABLE && zone->managed_cma_pages)
+ return __choose_rmqueue_migratetype(zone, order);
+
+ return migratetype;
+}
+
+#else
+static inline int choose_rmqueue_migratetype(struct zone *zone,
+ unsigned int order, int migratetype)
+{
+ return migratetype;
+}
+#endif
+
/*
* Do the hard work of removing an element from the buddy allocator.
* Call me with the zone->lock already held.
@@ -1166,10 +1262,17 @@
{
struct page *page;
-retry_reserve:
+ migratetype = choose_rmqueue_migratetype(zone, order, migratetype);
+
+retry:
page = __rmqueue_smallest(zone, order, migratetype);
if (unlikely(!page) && migratetype != MIGRATE_RESERVE) {
+ if (is_migrate_cma(migratetype)) {
+ migratetype = MIGRATE_MOVABLE;
+ goto retry;
+ }
+
page = __rmqueue_fallback(zone, order, migratetype);
/*
@@ -1179,7 +1282,7 @@
*/
if (!page) {
migratetype = MIGRATE_RESERVE;
- goto retry_reserve;
+ goto retry;
}
}
@@ -1381,12 +1484,13 @@
struct zone *zone = page_zone(page);
struct per_cpu_pages *pcp;
unsigned long flags;
+ unsigned long pfn = page_to_pfn(page);
int migratetype;
if (!free_pages_prepare(page, 0))
return;
- migratetype = get_pageblock_migratetype(page);
+ migratetype = get_pfnblock_migratetype(page, pfn);
set_freepage_migratetype(page, migratetype);
local_irq_save(flags);
__count_vm_event(PGFREE);
@@ -1400,7 +1504,7 @@
*/
if (migratetype >= MIGRATE_PCPTYPES) {
if (unlikely(is_migrate_isolate(migratetype))) {
- free_one_page(zone, page, 0, migratetype);
+ free_one_page(zone, page, pfn, 0, migratetype);
goto out;
}
migratetype = MIGRATE_MOVABLE;
@@ -1464,7 +1568,7 @@
}
EXPORT_SYMBOL_GPL(split_page);
-static int __isolate_free_page(struct page *page, unsigned int order)
+int __isolate_free_page(struct page *page, unsigned int order)
{
unsigned long watermark;
struct zone *zone;
@@ -5469,7 +5573,7 @@
printk("Memory: %luK/%luK available "
"(%luK kernel code, %luK rwdata, %luK rodata, "
- "%luK init, %luK bss, %luK reserved"
+ "%luK init, %luK bss, %luK reserved, %luK cma-reserved"
#ifdef CONFIG_HIGHMEM
", %luK highmem"
#endif
@@ -5477,7 +5581,8 @@
nr_free_pages() << (PAGE_SHIFT-10), physpages << (PAGE_SHIFT-10),
codesize >> 10, datasize >> 10, rosize >> 10,
(init_data_size + init_code_size) >> 10, bss_size >> 10,
- (physpages - totalram_pages) << (PAGE_SHIFT-10),
+ (physpages - totalram_pages - totalcma_pages) << (PAGE_SHIFT-10),
+ totalcma_pages << (PAGE_SHIFT-10),
#ifdef CONFIG_HIGHMEM
totalhigh_pages << (PAGE_SHIFT-10),
#endif
@@ -6041,17 +6146,16 @@
* @end_bitidx: The last bit of interest
* returns pageblock_bits flags
*/
-unsigned long get_pageblock_flags_mask(struct page *page,
+unsigned long get_pfnblock_flags_mask(struct page *page, unsigned long pfn,
unsigned long end_bitidx,
unsigned long mask)
{
struct zone *zone;
unsigned long *bitmap;
- unsigned long pfn, bitidx, word_bitidx;
+ unsigned long bitidx, word_bitidx;
unsigned long word;
zone = page_zone(page);
- pfn = page_to_pfn(page);
bitmap = get_pageblock_bitmap(zone, pfn);
bitidx = pfn_to_bitidx(zone, pfn);
word_bitidx = bitidx / BITS_PER_LONG;
@@ -6063,25 +6167,25 @@
}
/**
- * set_pageblock_flags_mask - Set the requested group of flags for a pageblock_nr_pages block of pages
+ * set_pfnblock_flags_mask - Set the requested group of flags for a pageblock_nr_pages block of pages
* @page: The page within the block of interest
* @start_bitidx: The first bit of interest
* @end_bitidx: The last bit of interest
* @flags: The flags to set
*/
-void set_pageblock_flags_mask(struct page *page, unsigned long flags,
+void set_pfnblock_flags_mask(struct page *page, unsigned long flags,
+ unsigned long pfn,
unsigned long end_bitidx,
unsigned long mask)
{
struct zone *zone;
unsigned long *bitmap;
- unsigned long pfn, bitidx, word_bitidx;
+ unsigned long bitidx, word_bitidx;
unsigned long old_word, word;
BUILD_BUG_ON(NR_PAGEBLOCK_BITS != 4);
zone = page_zone(page);
- pfn = page_to_pfn(page);
bitmap = get_pageblock_bitmap(zone, pfn);
bitidx = pfn_to_bitidx(zone, pfn);
word_bitidx = bitidx / BITS_PER_LONG;
@@ -6229,7 +6333,6 @@
/* This function is based on compact_zone() from compaction.c. */
unsigned long nr_reclaimed;
unsigned long pfn = start;
- unsigned int tries = 0;
int ret = 0;
migrate_prep();
@@ -6248,10 +6351,6 @@
ret = -EINTR;
break;
}
- tries = 0;
- } else if (++tries == 5) {
- ret = ret < 0 ? ret : -EBUSY;
- break;
}
nr_reclaimed = reclaim_clean_pages_from_list(cc->zone,
@@ -6260,6 +6359,10 @@
ret = migrate_pages(&cc->migratepages, alloc_migrate_target,
NULL, 0, cc->mode, MR_CMA);
+ if (ret) {
+ ret = ret < 0 ? ret : -EBUSY;
+ break;
+ }
}
if (ret < 0) {
putback_movable_pages(&cc->migratepages);
@@ -6369,13 +6472,12 @@
/* Make sure the range is really isolated. */
if (test_pages_isolated(outer_start, end, false)) {
- pr_warn("alloc_contig_range test_pages_isolated(%lx, %lx) failed\n",
- outer_start, end);
+ pr_info("%s: [%lx, %lx) PFNs busy\n",
+ __func__, outer_start, end);
ret = -EBUSY;
goto done;
}
-
/* Grab isolated pages from freelists. */
outer_end = isolate_freepages_range(&cc, outer_start, end);
if (!outer_end) {
diff --git a/mm/page_isolation.c b/mm/page_isolation.c
index d1473b2..c8778f7 100644
--- a/mm/page_isolation.c
+++ b/mm/page_isolation.c
@@ -60,6 +60,7 @@
int migratetype = get_pageblock_migratetype(page);
set_pageblock_migratetype(page, MIGRATE_ISOLATE);
+ zone->nr_isolate_pageblock++;
nr_pages = move_freepages_block(zone, page, MIGRATE_ISOLATE);
__mod_zone_freepage_state(zone, -nr_pages, migratetype);
@@ -75,16 +76,54 @@
{
struct zone *zone;
unsigned long flags, nr_pages;
+ struct page *isolated_page = NULL;
+ unsigned int order;
+ unsigned long page_idx, buddy_idx;
+ struct page *buddy;
zone = page_zone(page);
spin_lock_irqsave(&zone->lock, flags);
if (get_pageblock_migratetype(page) != MIGRATE_ISOLATE)
goto out;
- nr_pages = move_freepages_block(zone, page, migratetype);
- __mod_zone_freepage_state(zone, nr_pages, migratetype);
+
+ /*
+ * Because freepage with more than pageblock_order on isolated
+ * pageblock is restricted to merge due to freepage counting problem,
+ * it is possible that there is free buddy page.
+ * move_freepages_block() doesn't care of merge so we need other
+ * approach in order to merge them. Isolation and free will make
+ * these pages to be merged.
+ */
+ if (PageBuddy(page)) {
+ order = page_order(page);
+ if (order >= pageblock_order) {
+ page_idx = page_to_pfn(page) & ((1 << MAX_ORDER) - 1);
+ buddy_idx = __find_buddy_index(page_idx, order);
+ buddy = page + (buddy_idx - page_idx);
+
+ if (!is_migrate_isolate_page(buddy)) {
+ __isolate_free_page(page, order);
+ set_page_refcounted(page);
+ isolated_page = page;
+ }
+ }
+ }
+
+ /*
+ * If we isolate freepage with more than pageblock_order, there
+ * should be no freepage in the range, so we could avoid costly
+ * pageblock scanning for freepage moving.
+ */
+ if (!isolated_page) {
+ nr_pages = move_freepages_block(zone, page, migratetype);
+ __mod_zone_freepage_state(zone, nr_pages, migratetype);
+ }
set_pageblock_migratetype(page, migratetype);
+ zone->nr_isolate_pageblock--;
out:
spin_unlock_irqrestore(&zone->lock, flags);
+ if (isolated_page)
+ __free_pages(isolated_page, order);
}
static inline struct page *
diff --git a/net/bridge/br_if.c b/net/bridge/br_if.c
index 4352540..b97c4f9 100644
--- a/net/bridge/br_if.c
+++ b/net/bridge/br_if.c
@@ -139,6 +139,9 @@
br_stp_disable_port(p);
spin_unlock_bh(&br->lock);
+ if (dev->netdev_ops->ndo_br_leave)
+ dev->netdev_ops->ndo_br_leave(dev, br);
+
br_ifinfo_notify(RTM_DELLINK, p);
nbp_vlan_flush(p);
@@ -226,7 +229,7 @@
p->port_no = index;
p->flags = BR_LEARNING | BR_FLOOD;
br_init_port(p);
- p->state = BR_STATE_DISABLED;
+ br_set_state(p, BR_STATE_DISABLED);
br_stp_port_timer_init(p);
br_multicast_add_port(p);
@@ -396,6 +399,9 @@
spin_lock_bh(&br->lock);
changed_addr = br_stp_recalculate_bridge_id(br);
+ if (dev->netdev_ops->ndo_br_join)
+ dev->netdev_ops->ndo_br_join(dev, br);
+
if (netif_running(dev) && netif_oper_up(dev) &&
(br->dev->flags & IFF_UP))
br_stp_enable_port(p);
diff --git a/net/bridge/br_netlink.c b/net/bridge/br_netlink.c
index e8844d9..fa41b97 100644
--- a/net/bridge/br_netlink.c
+++ b/net/bridge/br_netlink.c
@@ -305,7 +305,7 @@
(!netif_oper_up(p->dev) && state != BR_STATE_DISABLED))
return -ENETDOWN;
- p->state = state;
+ br_set_state(p, state);
br_log_state(p);
br_port_state_selection(p->br);
return 0;
diff --git a/net/bridge/br_private.h b/net/bridge/br_private.h
index 4acfc3e..b5a4796 100644
--- a/net/bridge/br_private.h
+++ b/net/bridge/br_private.h
@@ -737,6 +737,7 @@
/* br_stp.c */
void br_log_state(const struct net_bridge_port *p);
+void br_set_state(struct net_bridge_port *p, unsigned int state);
struct net_bridge_port *br_get_port(struct net_bridge *br, u16 port_no);
void br_init_port(struct net_bridge_port *p);
void br_become_designated_port(struct net_bridge_port *p);
diff --git a/net/bridge/br_stp.c b/net/bridge/br_stp.c
index 3c86f05..2b09a29 100644
--- a/net/bridge/br_stp.c
+++ b/net/bridge/br_stp.c
@@ -36,6 +36,15 @@
br_port_state_names[p->state]);
}
+void br_set_state(struct net_bridge_port *p, unsigned int state)
+{
+ struct net_device *dev = p->dev;
+
+ p->state = state;
+ if (dev->netdev_ops->ndo_br_set_stp_state)
+ dev->netdev_ops->ndo_br_set_stp_state(dev, p->br, state);
+}
+
/* called under bridge lock */
struct net_bridge_port *br_get_port(struct net_bridge *br, u16 port_no)
{
@@ -107,7 +116,7 @@
br_notice(br, "port %u(%s) tried to become root port (blocked)",
(unsigned int) p->port_no, p->dev->name);
- p->state = BR_STATE_LISTENING;
+ br_set_state(p, BR_STATE_LISTENING);
br_log_state(p);
br_ifinfo_notify(RTM_NEWLINK, p);
@@ -387,7 +396,7 @@
p->state == BR_STATE_LEARNING)
br_topology_change_detection(p->br);
- p->state = BR_STATE_BLOCKING;
+ br_set_state(p, BR_STATE_BLOCKING);
br_log_state(p);
br_ifinfo_notify(RTM_NEWLINK, p);
@@ -404,13 +413,13 @@
return;
if (br->stp_enabled == BR_NO_STP || br->forward_delay == 0) {
- p->state = BR_STATE_FORWARDING;
+ br_set_state(p, BR_STATE_FORWARDING);
br_topology_change_detection(br);
del_timer(&p->forward_delay_timer);
} else if (br->stp_enabled == BR_KERNEL_STP)
- p->state = BR_STATE_LISTENING;
+ br_set_state(p, BR_STATE_LISTENING);
else
- p->state = BR_STATE_LEARNING;
+ br_set_state(p, BR_STATE_LEARNING);
br_multicast_enable_port(p);
br_log_state(p);
diff --git a/net/bridge/br_stp_if.c b/net/bridge/br_stp_if.c
index 189ba1e..4114687 100644
--- a/net/bridge/br_stp_if.c
+++ b/net/bridge/br_stp_if.c
@@ -37,7 +37,7 @@
{
p->port_id = br_make_port_id(p->priority, p->port_no);
br_become_designated_port(p);
- p->state = BR_STATE_BLOCKING;
+ br_set_state(p, BR_STATE_BLOCKING);
p->topology_change_ack = 0;
p->config_pending = 0;
}
@@ -100,7 +100,7 @@
wasroot = br_is_root_bridge(br);
br_become_designated_port(p);
- p->state = BR_STATE_DISABLED;
+ br_set_state(p, BR_STATE_DISABLED);
p->topology_change_ack = 0;
p->config_pending = 0;
diff --git a/net/bridge/br_stp_timer.c b/net/bridge/br_stp_timer.c
index 558c46d..4fcaa67 100644
--- a/net/bridge/br_stp_timer.c
+++ b/net/bridge/br_stp_timer.c
@@ -87,11 +87,11 @@
(unsigned int) p->port_no, p->dev->name);
spin_lock(&br->lock);
if (p->state == BR_STATE_LISTENING) {
- p->state = BR_STATE_LEARNING;
+ br_set_state(p, BR_STATE_LEARNING);
mod_timer(&p->forward_delay_timer,
jiffies + br->forward_delay);
} else if (p->state == BR_STATE_LEARNING) {
- p->state = BR_STATE_FORWARDING;
+ br_set_state(p, BR_STATE_FORWARDING);
if (br_is_designated_for_some_port(br))
br_topology_change_detection(br);
netif_carrier_on(br->dev);
diff --git a/net/dsa/dsa.c b/net/dsa/dsa.c
index 17b6152..3cb46cd 100644
--- a/net/dsa/dsa.c
+++ b/net/dsa/dsa.c
@@ -212,6 +212,7 @@
{
}
+#ifdef CONFIG_PM_SLEEP
static int dsa_switch_suspend(struct dsa_switch *ds)
{
int i, ret = 0;
@@ -254,6 +255,7 @@
return 0;
}
+#endif
/* link polling *************************************************************/
diff --git a/net/dsa/dsa_priv.h b/net/dsa/dsa_priv.h
index 556debc..2adc2b5 100644
--- a/net/dsa/dsa_priv.h
+++ b/net/dsa/dsa_priv.h
@@ -37,6 +37,8 @@
int old_link;
int old_pause;
int old_duplex;
+
+ struct net_bridge *bridge_dev;
};
/* dsa.c */
diff --git a/net/dsa/slave.c b/net/dsa/slave.c
index db80e8c..4fa4509 100644
--- a/net/dsa/slave.c
+++ b/net/dsa/slave.c
@@ -14,6 +14,7 @@
#include <linux/phy.h>
#include <linux/of_net.h>
#include <linux/of_mdio.h>
+#include <linux/if_bridge.h>
#include "dsa_priv.h"
/* slave mii_bus handling ***************************************************/
@@ -59,11 +60,18 @@
return 0;
}
+static inline bool dsa_port_is_bridged(struct dsa_slave_priv *p)
+{
+ return !!p->bridge_dev;
+}
+
static int dsa_slave_open(struct net_device *dev)
{
struct dsa_slave_priv *p = netdev_priv(dev);
struct net_device *master = p->parent->dst->master_netdev;
struct dsa_switch *ds = p->parent;
+ u8 stp_state = dsa_port_is_bridged(p) ?
+ BR_STATE_BLOCKING : BR_STATE_FORWARDING;
int err;
if (!(master->flags & IFF_UP))
@@ -92,6 +100,9 @@
goto clear_promisc;
}
+ if (ds->drv->br_set_stp_state)
+ ds->drv->br_set_stp_state(ds, p->port, stp_state);
+
if (p->phy)
phy_start(p->phy);
@@ -132,6 +143,9 @@
if (ds->drv->port_disable)
ds->drv->port_disable(ds, p->port);
+ if (ds->drv->br_set_stp_state)
+ ds->drv->br_set_stp_state(ds, p->port, BR_STATE_DISABLED);
+
return 0;
}
@@ -193,6 +207,71 @@
return -EOPNOTSUPP;
}
+/* Return a bitmask of all ports being currently bridged. Note that on
+ * leave, the mask will still return the bitmask of ports currently bridged,
+ * prior to port removal, and this is exactly what we want.
+ */
+static u32 dsa_slave_br_port_mask(struct dsa_switch *ds, struct net_bridge *br)
+{
+ struct dsa_slave_priv *p;
+ unsigned int port;
+ u32 mask = 0;
+
+ for (port = 0; port < DSA_MAX_PORTS; port++) {
+ if (!((1 << port) & ds->phys_port_mask))
+ continue;
+
+ p = netdev_priv(ds->ports[port]);
+
+ if ((ds->ports[port]->priv_flags & IFF_BRIDGE_PORT) &&
+ (p->bridge_dev == br))
+ mask |= 1 << port;
+ }
+
+ return mask;
+}
+
+static void dsa_slave_br_join(struct net_device *dev, struct net_bridge *br)
+{
+ struct dsa_slave_priv *p = netdev_priv(dev);
+ struct dsa_switch *ds = p->parent;
+
+ p->bridge_dev = br;
+
+ if (ds->drv->br_join)
+ ds->drv->br_join(ds, p->port,
+ dsa_slave_br_port_mask(ds, br));
+}
+
+static void dsa_slave_br_leave(struct net_device *dev, struct net_bridge *br)
+{
+ struct dsa_slave_priv *p = netdev_priv(dev);
+ struct dsa_switch *ds = p->parent;
+
+ if (ds->drv->br_leave)
+ ds->drv->br_leave(ds, p->port,
+ dsa_slave_br_port_mask(ds, p->bridge_dev));
+
+ p->bridge_dev = NULL;
+
+ /* Port left the bridge, put in BR_STATE_DISABLED by the bridge layer,
+ * so allow it to be in BR_STATE_FORWARDING to be kept functional
+ */
+ if (ds->drv->br_set_stp_state)
+ ds->drv->br_set_stp_state(ds, p->port, BR_STATE_FORWARDING);
+}
+
+static void dsa_slave_br_set_stp_state(struct net_device *dev,
+ struct net_bridge *br,
+ unsigned int state)
+{
+ struct dsa_slave_priv *p = netdev_priv(dev);
+ struct dsa_switch *ds = p->parent;
+
+ if (ds->drv->br_set_stp_state)
+ ds->drv->br_set_stp_state(ds, p->port, state);
+}
+
/* ethtool operations *******************************************************/
static int
@@ -383,6 +462,9 @@
.ndo_set_rx_mode = dsa_slave_set_rx_mode,
.ndo_set_mac_address = dsa_slave_set_mac_address,
.ndo_do_ioctl = dsa_slave_ioctl,
+ .ndo_br_join = dsa_slave_br_join,
+ .ndo_br_leave = dsa_slave_br_leave,
+ .ndo_br_set_stp_state = dsa_slave_br_set_stp_state,
};
#endif
#ifdef CONFIG_NET_DSA_TAG_DSA
@@ -395,6 +477,9 @@
.ndo_set_rx_mode = dsa_slave_set_rx_mode,
.ndo_set_mac_address = dsa_slave_set_mac_address,
.ndo_do_ioctl = dsa_slave_ioctl,
+ .ndo_br_join = dsa_slave_br_join,
+ .ndo_br_leave = dsa_slave_br_leave,
+ .ndo_br_set_stp_state = dsa_slave_br_set_stp_state,
};
#endif
#ifdef CONFIG_NET_DSA_TAG_EDSA
@@ -407,6 +492,9 @@
.ndo_set_rx_mode = dsa_slave_set_rx_mode,
.ndo_set_mac_address = dsa_slave_set_mac_address,
.ndo_do_ioctl = dsa_slave_ioctl,
+ .ndo_br_join = dsa_slave_br_join,
+ .ndo_br_leave = dsa_slave_br_leave,
+ .ndo_br_set_stp_state = dsa_slave_br_set_stp_state,
};
#endif
#ifdef CONFIG_NET_DSA_TAG_TRAILER
@@ -419,6 +507,9 @@
.ndo_set_rx_mode = dsa_slave_set_rx_mode,
.ndo_set_mac_address = dsa_slave_set_mac_address,
.ndo_do_ioctl = dsa_slave_ioctl,
+ .ndo_br_join = dsa_slave_br_join,
+ .ndo_br_leave = dsa_slave_br_leave,
+ .ndo_br_set_stp_state = dsa_slave_br_set_stp_state,
};
#endif
@@ -441,6 +532,9 @@
.ndo_set_rx_mode = dsa_slave_set_rx_mode,
.ndo_set_mac_address = dsa_slave_set_mac_address,
.ndo_do_ioctl = dsa_slave_ioctl,
+ .ndo_br_join = dsa_slave_br_join,
+ .ndo_br_leave = dsa_slave_br_leave,
+ .ndo_br_set_stp_state = dsa_slave_br_set_stp_state,
};
static void dsa_slave_adjust_link(struct net_device *dev)
@@ -489,16 +583,32 @@
{
struct dsa_switch *ds = p->parent;
struct dsa_chip_data *cd = ds->pd;
- struct device_node *phy_dn;
+ struct device_node *phy_dn, *port_dn;
+ bool phy_is_fixed = false;
u32 phy_flags = 0;
u32 phy_addr;
+ int ret;
- p->phy_interface = of_get_phy_mode(cd->port_dn[p->port]);
+ port_dn = cd->port_dn[p->port];
+ p->phy_interface = of_get_phy_mode(port_dn);
+
+ phy_dn = of_parse_phandle(port_dn, "phy-handle", 0);
+ if (of_phy_is_fixed_link(port_dn)) {
+ /* In the case of a fixed PHY, the DT node associated
+ * to the fixed PHY is the Port DT node
+ */
+ ret = of_phy_register_fixed_link(port_dn);
+ if (ret) {
+ pr_err("failed to register fixed PHY\n");
+ return;
+ }
+ phy_dn = port_dn;
+ phy_is_fixed = true;
+ }
if (ds->drv->get_phy_flags)
phy_flags = ds->drv->get_phy_flags(ds, p->port);
- phy_dn = of_parse_phandle(cd->port_dn[p->port], "phy-handle", 0);
if (phy_dn) {
/* Allow the switch driver to intercept PHY registers accesses
* to address 0 and 0x1e to workaround the lack of MDIO bus
@@ -506,8 +616,9 @@
* a problem with Broadcom switches that have a hard-coded
* pseudo-PHY address 30d.
*/
- if (of_device_is_compatible(phy_dn, "brcm,bcm53101") ||
- of_device_is_compatible(phy_dn, "brcm,bcm53125")) {
+ if ((of_device_is_compatible(phy_dn, "brcm,bcm53101") ||
+ of_device_is_compatible(phy_dn, "brcm,bcm53125")) &&
+ of_machine_is_compatible("brcm,bcm7445d0")) {
if (of_property_read_u32(phy_dn, "reg", &phy_addr))
phy_addr = 0;
@@ -525,15 +636,11 @@
p->phy = of_phy_connect(slave_dev, phy_dn,
dsa_slave_adjust_link, phy_flags,
p->phy_interface);
- } else {
- p->phy = of_phy_connect_fixed_link(slave_dev,
- dsa_slave_adjust_link,
- p->phy_interface);
- if (p->phy)
- fixed_phy_set_link_update(p->phy,
- dsa_slave_fixed_link_update);
}
+ if (p->phy && phy_is_fixed)
+ fixed_phy_set_link_update(p->phy, dsa_slave_fixed_link_update);
+
/* We could not connect to a designated PHY, so use the switch internal
* MDIO bus instead
*/
diff --git a/scripts/.gitignore b/scripts/.gitignore
index fb070fa..3a2f6da 100644
--- a/scripts/.gitignore
+++ b/scripts/.gitignore
@@ -11,3 +11,4 @@
docproc
sortextable
asn1_compiler
+*.pyc
diff --git a/scripts/analyze_oom.py b/scripts/analyze_oom.py
new file mode 100755
index 0000000..1ee0495
--- /dev/null
+++ b/scripts/analyze_oom.py
@@ -0,0 +1,203 @@
+#!/usr/bin/env python
+"""
+analyze-oom.py
+
+Gives a rudimentary analysis of an OOM oops log. Only analyzes the first OOM
+message seen in the provided input.
+
+Usage: analyze-oom.py <oopslog>
+ cat <oopslog> | analyze-oom.py
+"""
+# Copyright 2015 Broadcom Corporation
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License, version 2, as
+# published by the Free Software Foundation (the "GPL").
+#
+# This program is distributed in the hope that it will be useful, but
+# WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+# General Public License for more details.
+#
+# A copy of the GPL is available at
+# http://www.broadcom.com/licenses/GPLv2.php or
+# http://www.gnu.org/licenses/licenses.html
+#
+# Authors:
+# Gregory Fong <gregory@broadcom.com>
+
+
+from __future__ import print_function
+from decode_gfpmask import gen_flags_dict, get_flag_names
+import fileinput
+import re
+import sys
+
+
+def main():
+ if len(sys.argv) > 1 and sys.argv[1] == "-h":
+ print(__doc__)
+ sys.exit(0)
+
+ d_gfp = gen_flags_dict()
+
+ gfp_mask = None
+ order = None
+ free_kB = None
+ min_kB = None
+ free_cma_kB = None
+ free_highmem_kB = None
+ min_highmem_kB = None
+ free_highmem_cma_kB = None
+ lowmem_reserve = None
+
+ req_input_vars = ['gfp_mask', 'order', 'free_kB', 'min_kB',
+ 'lowmem_reserve']
+
+ # TODO: use actual PAGE_SIZE
+ PAGE_SIZE = 4096
+ PAGE_SIZE_kB = PAGE_SIZE / 1024
+
+ for line in fileinput.input():
+ line = line.rstrip()
+ if gfp_mask is None:
+ m = re.search("((?<=oom-killer: gfp_mask=)0x\w+),", line)
+ if (m):
+ gfp_mask = int(m.group(1), 16)
+ if order is None:
+ m = re.search("(?<=oom-killer: ).*order=(\d+),", line)
+ if (m):
+ order = int(m.group(1))
+ if free_kB is None:
+ m = re.search("((?<=Normal free:)\d+)kB", line)
+ if (m):
+ free_kB = int(m.group(1))
+ if min_kB is None:
+ m = re.search("(?<=Normal ).*min:(\d+)kB", line)
+ if (m):
+ min_kB = int(m.group(1))
+ if free_cma_kB is None:
+ m = re.search("(?<=Normal free:).*((?<=free_cma:)\d+)kB", line)
+ if (m):
+ free_cma_kB = int(m.group(1))
+ if free_highmem_kB is None:
+ m = re.search("((?<=HighMem free:)\d+)kB", line)
+ if (m):
+ free_highmem_kB = int(m.group(1))
+ if min_highmem_kB is None:
+ m = re.search("(?<=HighMem ).*min:(\d+)kB", line)
+ if (m):
+ min_highmem_kB = int(m.group(1))
+ if free_highmem_cma_kB is None:
+ m = re.search("(?<=HighMem free:).*((?<=free_cma:)\d+)kB", line)
+ if (m):
+ free_highmem_cma_kB = int(m.group(1))
+ if lowmem_reserve is None:
+ m = re.search("(?<=lowmem_reserve\[\]: 0 )(\d+)", line)
+ if (m):
+ lowmem_reserve = int(m.group(1))
+
+ if any([eval(x) is None for x in req_input_vars]):
+ print("Error: Missing {} in input log".format(x))
+ sys.exit(1)
+
+ gfp_flag_names = get_flag_names(d_gfp, gfp_mask)
+ has_cma = (free_cma_kB is not None) or \
+ (free_highmem_cma_kB is not None)
+ highmem = '___GFP_HIGHMEM' in gfp_flag_names
+ lowmem_reserve_kB = lowmem_reserve * PAGE_SIZE_kB
+ # assume page group by mobility enabled (see include/linux/gfp.h)
+ unmovable = not any(x in gfp_flag_names for x in
+ ['___GFP_MOVABLE', '___GFP_RECLAIMABLE'])
+
+ print("gfp_flags: 0x{:x}".format(gfp_mask))
+ print("Decoded gfp_flags: {}".format(" | ".join(gfp_flag_names)))
+
+ my_free_kB_calc = str(free_kB) # for building up calculation
+
+ print("Free mem in ZONE_NORMAL: {:d} kB.".format(free_kB))
+
+ if free_highmem_kB:
+ print("Free mem in ZONE_HIGHMEM: {:d} kB.".format(free_highmem_kB))
+ my_free_kB_calc += " + " + str(free_highmem_kB)
+
+ if unmovable and has_cma:
+ print("Migrate type is MIGRATE_UNMOVABLE, cannot use CMA pages")
+ print("Portion of ZONE_NORMAL which is CMA: {:d} kB."
+ .format(free_cma_kB))
+ free_kB -= free_cma_kB
+ my_free_kB_calc += " - " + str(free_cma_kB)
+ if free_highmem_cma_kB:
+ free_highmem_kB -= free_highmem_cma_kB
+ my_free_kB_calc += " - " + str(free_highmem_cma_kB)
+ print("Portion of ZONE_HIGHMEM which is CMA: {:d} kB."
+ .format(free_highmem_cma_kB))
+
+ my_free_kB = free_kB + free_highmem_kB
+
+ print("Total free: {} = {:d} kB.".format(my_free_kB_calc, my_free_kB))
+
+ my_min_kB = min_kB
+ my_min_kB_calc = str(min_kB)
+ if highmem and min_highmem_kB:
+ my_min_kB += min_highmem_kB
+ my_min_kB_calc += " + " + str(min_highmem_kB)
+
+ print("Minimum RAM allowed: {} = {} kB".format(my_min_kB_calc, my_min_kB))
+
+ if highmem and lowmem_reserve_kB:
+ print("__GFP_HIGHMEM was set, must also exclude lowmem_reserve: {} kB"
+ .format(lowmem_reserve_kB))
+
+ print()
+ print("Did we have enough memory?")
+
+ had_enough_memory_lhs = my_free_kB - (PAGE_SIZE_kB << order)
+ calc_lhs = str(my_free_kB) + " - " + str(PAGE_SIZE_kB << order)
+ calcstr_lhs = "my_free_kB - (PAGE_SIZE_kB << order)"
+ had_enough_memory_rhs = my_min_kB
+ calc_rhs = str(my_min_kB)
+ calcstr_rhs = "my_min_kB"
+ if highmem:
+ had_enough_memory_rhs += lowmem_reserve_kB
+ calc_rhs += " + " + str(lowmem_reserve_kB)
+ calcstr_rhs += " + lowmem_reserve_kB"
+ print("Test: {} > {}".format(calcstr_lhs, calcstr_rhs))
+ print(" {} > {}".format(calc_lhs, calc_rhs))
+ had_enough_memory = had_enough_memory_lhs > had_enough_memory_rhs
+
+ if had_enough_memory:
+ print("*Yes*, had enough memory at time of OOM.")
+ else:
+ print("*No*, not enough memory at time of OOM.")
+
+ print()
+ print("Possible causes of OOM:")
+ if had_enough_memory:
+ print("- Allocation order was {}.".format(order),
+ "Check freelist for that order and higher in the Mem-info.")
+ if (unmovable and has_cma):
+ print(" Note that this allocation is NOT allowed to use CMA",
+ "pages (marked 'C').")
+ if highmem and free_highmem_kB:
+ # TODO: check whether this was caused by having enough memory
+ # in the sum of highmem and lowmem but not in either one
+ pass
+ # TODO: more sophisticated analysis of allocation order
+ # that looks at freelist. Maybe something like
+ # if > 90% of free pages are in order 0 and order 1 blocks
+ # and this is a higher-order allocation:
+ # Report that this might be a core MM bug causing excessive
+ # fragmentation, please report to STB Linux team
+ else:
+ print("- If this took some time to fail, could be a memory leak in a",
+ "kernel module.")
+ if (highmem):
+ print("- lowmem_reserve might be too high. Try tweaking",
+ "/proc/sys/vm/lowmem_reserve_ratio.")
+ if (unmovable and has_cma):
+ print("- May not have enough lowmem outside of a CMA region.",
+ "You may need to decrease the size of a region in lowmem.")
+
+if __name__ == "__main__":
+ main()
diff --git a/scripts/decode_gfpmask.py b/scripts/decode_gfpmask.py
new file mode 100755
index 0000000..cb86861
--- /dev/null
+++ b/scripts/decode_gfpmask.py
@@ -0,0 +1,75 @@
+#!/usr/bin/env python
+"""
+decode-gfpmask.py
+
+Decodes the input GFP flags into their names.
+
+Usage: decode-gfpmask.py <gfpflags in hex>
+"""
+# Copyright 2015 Broadcom Corporation
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License, version 2, as
+# published by the Free Software Foundation (the "GPL").
+#
+# This program is distributed in the hope that it will be useful, but
+# WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+# General Public License for more details.
+#
+# A copy of the GPL is available at
+# http://www.broadcom.com/licenses/GPLv2.php or
+# http://www.gnu.org/licenses/licenses.html
+#
+# Authors:
+# Gregory Fong <gregory@broadcom.com>
+
+
+from __future__ import print_function
+import re
+import os.path
+import sys
+
+
+def gen_flags_dict():
+ """Returns a dictionary, keys are GFP flag values and the values are the
+ names"""
+
+ linuxpath = os.path.dirname(os.path.dirname(os.path.realpath(__file__)))
+
+ d_gfp = {}
+ with open(os.path.join(linuxpath, "include/linux/gfp.h")) as f:
+ for line in f:
+ line = line.rstrip()
+ m = re.search("((?<=define )___GFP_\S+)\s+(0x\S+u)", line)
+ if m:
+ d_gfp[int(m.group(2)[:-1], 16)] = m.group(1)
+ return d_gfp
+
+
+def get_flag_names(d_gfp, flags):
+ """Returns list of encoded 'flags' by looking them up in d_gfp"""
+ i = 1
+ flaglist = []
+ while flags > 0:
+ if flags & 1:
+ flaglist.append(d_gfp[i])
+ flags >>= 1
+ i <<= 1
+ return flaglist
+
+
+def main():
+ if len(sys.argv) != 2:
+ print(__doc__)
+ sys.exit(1)
+ if sys.argv[1] == "-h":
+ print(__doc__)
+ sys.exit(0)
+ flags = int(sys.argv[1], 16)
+ d_gfp = gen_flags_dict()
+ print(" | ".join(get_flag_names(d_gfp, flags)))
+
+
+if __name__ == "__main__":
+ main()
diff --git a/scripts/kconfig/menu.c b/scripts/kconfig/menu.c
index db1512a..8622462 100644
--- a/scripts/kconfig/menu.c
+++ b/scripts/kconfig/menu.c
@@ -598,18 +598,6 @@
}
/*
- * get property of type P_SYMBOL
- */
-static struct property *get_symbol_prop(struct symbol *sym)
-{
- struct property *prop = NULL;
-
- for_all_properties(sym, prop, P_SYMBOL)
- break;
- return prop;
-}
-
-/*
* head is optional and may be NULL
*/
void get_symbol_str(struct gstr *r, struct symbol *sym,
@@ -634,15 +622,22 @@
for_all_prompts(sym, prop)
get_prompt_str(r, prop, head);
- prop = get_symbol_prop(sym);
- if (prop) {
- str_printf(r, _(" Defined at %s:%d\n"), prop->menu->file->name,
+ hit = false;
+ for_all_properties(sym, prop, P_SYMBOL) {
+ if (!hit) {
+ str_append(r, " Defined at ");
+ hit = true;
+ } else
+ str_append(r, ", ");
+ str_printf(r, _("%s:%d"), prop->menu->file->name,
prop->menu->lineno);
- if (!expr_is_yes(prop->visible.expr)) {
- str_append(r, _(" Depends on: "));
- expr_gstr_print(prop->visible.expr, r);
- str_append(r, "\n");
- }
+ }
+ if (hit)
+ str_append(r, "\n");
+ if (!expr_is_yes(sym->dir_dep.expr)) {
+ str_append(r, _(" Depends on: "));
+ expr_gstr_print(sym->dir_dep.expr, r);
+ str_append(r, "\n");
}
hit = false;
diff --git a/scripts/setlocalversion b/scripts/setlocalversion
index 63d91e2..9e97364 100755
--- a/scripts/setlocalversion
+++ b/scripts/setlocalversion
@@ -45,6 +45,8 @@
# Check for git and a git repo.
if test -z "$(git rev-parse --show-cdup 2>/dev/null)" &&
head=`git rev-parse --verify --short HEAD 2>/dev/null`; then
+ # Update the index
+ git update-index -q --refresh
# If we are at a tagged commit (like "v2.6.30-rc6"), we ignore
# it, because this version is defined in the top level Makefile.
diff --git a/tools/testing/brcmstb/memory-api/.gitignore b/tools/testing/brcmstb/memory-api/.gitignore
new file mode 100644
index 0000000..fae10b2
--- /dev/null
+++ b/tools/testing/brcmstb/memory-api/.gitignore
@@ -0,0 +1 @@
+Module.symvers
diff --git a/tools/testing/brcmstb/memory-api/Kbuild b/tools/testing/brcmstb/memory-api/Kbuild
new file mode 100644
index 0000000..011a4b3
--- /dev/null
+++ b/tools/testing/brcmstb/memory-api/Kbuild
@@ -0,0 +1 @@
+obj-m := test-memory-api.o
diff --git a/tools/testing/brcmstb/memory-api/Makefile b/tools/testing/brcmstb/memory-api/Makefile
new file mode 100644
index 0000000..2af0a13
--- /dev/null
+++ b/tools/testing/brcmstb/memory-api/Makefile
@@ -0,0 +1,17 @@
+ifneq ($(KERNELRELEASE),)
+# kbuild part of makefile
+include Kbuild
+
+else
+# normal makefile
+ifeq ($(KDIR),)
+ $(error Please set KDIR to point to your kernel build directory)
+endif
+
+default:
+ $(MAKE) -C $(KDIR) M=$$PWD
+
+clean:
+ $(MAKE) -C $(KDIR) M=$$PWD clean
+
+endif
diff --git a/tools/testing/brcmstb/memory-api/README b/tools/testing/brcmstb/memory-api/README
new file mode 100644
index 0000000..dee6d18
--- /dev/null
+++ b/tools/testing/brcmstb/memory-api/README
@@ -0,0 +1,7 @@
+Quick start: first build your kernel. Then from this directory, run
+
+ make KDIR=$PWD/../../../..
+
+Copy over the resulting module to the machine you're testing and run
+
+ insmod test-memory-api.ko
diff --git a/tools/testing/brcmstb/memory-api/test-memory-api.c b/tools/testing/brcmstb/memory-api/test-memory-api.c
new file mode 100644
index 0000000..f27ff98
--- /dev/null
+++ b/tools/testing/brcmstb/memory-api/test-memory-api.c
@@ -0,0 +1,91 @@
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/sizes.h>
+#include <linux/brcmstb/memory_api.h>
+
+static struct brcmstb_memory bm;
+
+static int __init test_init(void)
+{
+ struct brcmstb_range *range;
+ int ret;
+ int i, j;
+
+ ret = brcmstb_memory_get(&bm);
+ if (ret) {
+ pr_err("could not get memory struct\n");
+ return ret;
+ }
+
+ /* print ranges */
+ pr_info("Range info:\n");
+ for (i = 0; i < MAX_BRCMSTB_MEMC; ++i) {
+ pr_info(" memc%d\n", i);
+ for (j = 0; j < bm.memc[i].count; ++j) {
+ if (j >= MAX_BRCMSTB_RANGE) {
+ pr_warn(" Need to increase MAX_BRCMSTB_RANGE!\n");
+ break;
+ }
+ range = &bm.memc[i].range[j];
+ pr_info(" %llu MiB at %#016llx\n",
+ range->size / SZ_1M, range->addr);
+ }
+ }
+
+ pr_info("lowmem info:\n");
+ for (i = 0; i < bm.lowmem.count; ++i) {
+ if (i >= MAX_BRCMSTB_RANGE) {
+ pr_warn(" Need to increase MAX_BRCMSTB_RANGE!\n");
+ break;
+ }
+ range = &bm.lowmem.range[i];
+ pr_info(" %llu MiB at %#016llx\n",
+ range->size / SZ_1M, range->addr);
+ }
+
+ pr_info("bmem info:\n");
+ for (i = 0; i < bm.bmem.count; ++i) {
+ if (i >= MAX_BRCMSTB_RANGE) {
+ pr_warn(" Need to increase MAX_BRCMSTB_RANGE!\n");
+ break;
+ }
+ range = &bm.bmem.range[i];
+ pr_info(" %llu MiB at %#016llx\n",
+ range->size / SZ_1M, range->addr);
+ }
+
+ pr_info("cma info:\n");
+ for (i = 0; i < bm.cma.count; ++i) {
+ if (i >= MAX_BRCMSTB_RANGE) {
+ pr_warn(" Need to increase MAX_BRCMSTB_RANGE!\n");
+ break;
+ }
+ range = &bm.cma.range[i];
+ pr_info(" %llu MiB at %#016llx\n",
+ range->size / SZ_1M, range->addr);
+ }
+
+ pr_info("reserved info:\n");
+ for (i = 0; i < bm.reserved.count; ++i) {
+ if (i >= MAX_BRCMSTB_RESERVED_RANGE) {
+ pr_warn(" Need to increase MAX_BRCMSTB_RESERVED_RANGE!\n");
+ break;
+ }
+ range = &bm.reserved.range[i];
+ pr_info(" %#016llx-%#016llx\n",
+ range->addr, range->addr + range->size);
+ }
+
+ return -EINVAL;
+}
+
+static void __exit test_exit(void)
+{
+ pr_info("Goodbye world\n");
+}
+
+module_init(test_init);
+module_exit(test_exit);
+MODULE_LICENSE("GPL");
+MODULE_AUTHOR("Gregory Fong (Broadcom Corporation)");
+
diff --git a/tools/thermal/tmon/.gitignore b/tools/thermal/tmon/.gitignore
new file mode 100644
index 0000000..9c7e038
--- /dev/null
+++ b/tools/thermal/tmon/.gitignore
@@ -0,0 +1 @@
+tmon
diff --git a/tools/thermal/tmon/Makefile b/tools/thermal/tmon/Makefile
index 4473211..926532b 100644
--- a/tools/thermal/tmon/Makefile
+++ b/tools/thermal/tmon/Makefile
@@ -2,8 +2,8 @@
BINDIR=usr/bin
WARNFLAGS=-Wall -Wshadow -W -Wformat -Wimplicit-function-declaration -Wimplicit-int
-CFLAGS= -O1 ${WARNFLAGS} -fstack-protector
-CC=gcc
+CFLAGS+= -O1 ${WARNFLAGS} -fstack-protector
+CC?=gcc
CFLAGS+=-D VERSION=\"$(VERSION)\"
LDFLAGS+=
@@ -16,12 +16,18 @@
CONFIG_FILE=
CONFIG_PATH=
+TMON_LIBS=-lm -lpanel -lpthread
+ifeq ($(USE_NCURSESW),1)
+TMON_LIBS += -lncursesw
+else
+TMON_LIBS += -lncurses
+endif
OBJS = tmon.o tui.o sysfs.o pid.o
OBJS +=
tmon: $(OBJS) Makefile tmon.h
- $(CC) ${CFLAGS} $(LDFLAGS) $(OBJS) -o $(TARGET) -lm -lpanel -lncursesw -lpthread
+ $(CC) ${CFLAGS} $(LDFLAGS) $(OBJS) -o $(TARGET) $(TMON_LIBS)
valgrind: tmon
sudo valgrind -v --track-origins=yes --tool=memcheck --leak-check=yes --show-reachable=yes --num-callers=20 --track-fds=yes ./$(TARGET) 1> /dev/null
diff --git a/tools/thermal/tmon/makefile b/tools/thermal/tmon/makefile
new file mode 100644
index 0000000..05d7d09
--- /dev/null
+++ b/tools/thermal/tmon/makefile
@@ -0,0 +1,22 @@
+include $(ROOTDIR)/config.arch
+
+LDFLAGS += -L$(ROOTDIR)/lib/ncurses/lib/
+CFLAGS += -I$(ROOTDIR)/lib/ncurses/include/
+
+export CC CFLAGS LDFLAGS
+
+all:
+ $(MAKE) -f Makefile
+
+all-% install-% clean-% distclean-%:
+ $(MAKE) -f Makefile $@
+
+clean:
+ $(MAKE) -f Makefile $(COMMON_MAKEARGS) clean
+
+distclean: clean
+ -$(MAKE) -f Makefile $(COMMON_MAKEARGS) distclean
+
+romfs:
+ $(STRIP) tmon
+ $(ROMFSINST) tmon /bin/tmon
diff --git a/tools/thermal/tmon/tmon.c b/tools/thermal/tmon/tmon.c
index b30f531..1402304 100644
--- a/tools/thermal/tmon/tmon.c
+++ b/tools/thermal/tmon/tmon.c
@@ -64,6 +64,7 @@
printf(" -h, --help show this help message\n");
printf(" -l, --log log data to /var/tmp/tmon.log\n");
printf(" -t, --time-interval sampling time interval, > 1 sec.\n");
+ printf(" -T, --target-temp initial target temperature\n");
printf(" -v, --version show version\n");
printf(" -z, --zone target thermal zone id\n");
@@ -195,6 +196,7 @@
{ "control", 1, NULL, 'c' },
{ "daemon", 0, NULL, 'd' },
{ "time-interval", 1, NULL, 't' },
+ { "target-temp", 1, NULL, 'T' },
{ "log", 0, NULL, 'l' },
{ "help", 0, NULL, 'h' },
{ "version", 0, NULL, 'v' },
@@ -207,7 +209,7 @@
{
int err = 0;
int id2 = 0, c;
- double yk = 0.0; /* controller output */
+ double yk = 0.0, temp; /* controller output */
int target_tz_index;
if (geteuid() != 0) {
@@ -215,7 +217,7 @@
exit(EXIT_FAILURE);
}
- while ((c = getopt_long(argc, argv, "c:dlht:vgz:", opts, &id2)) != -1) {
+ while ((c = getopt_long(argc, argv, "c:dlht:T:vgz:", opts, &id2)) != -1) {
switch (c) {
case 'c':
no_control = 0;
@@ -230,6 +232,14 @@
if (ticktime < 1)
ticktime = 1;
break;
+ case 'T':
+ temp = strtod(optarg, NULL);
+ if (temp < 0) {
+ fprintf(stderr, "error: temperature must be positive\n");
+ return 1;
+ }
+ target_temp_user = temp;
+ break;
case 'l':
printf("Logging data to /var/tmp/tmon.log\n");
logging = 1;
diff --git a/tools/thermal/tmon/tui.c b/tools/thermal/tmon/tui.c
index 89f8ef0..36e1f86 100644
--- a/tools/thermal/tmon/tui.c
+++ b/tools/thermal/tmon/tui.c
@@ -30,6 +30,18 @@
#include "tmon.h"
+#define min(x, y) ({ \
+ typeof(x) _min1 = (x); \
+ typeof(y) _min2 = (y); \
+ (void) (&_min1 == &_min2); \
+ _min1 < _min2 ? _min1 : _min2; })
+
+#define max(x, y) ({ \
+ typeof(x) _max1 = (x); \
+ typeof(y) _max2 = (y); \
+ (void) (&_max1 == &_max2); \
+ _max1 > _max2 ? _max1 : _max2; })
+
static PANEL *data_panel;
static PANEL *dialogue_panel;
static PANEL *top;
@@ -98,6 +110,18 @@
wrefresh(status_bar_window);
}
+/* wrap at 5 */
+#define DIAG_DEV_ROWS 5
+/*
+ * list cooling devices + "set temp" entry; wraps after 5 rows, if they fit
+ */
+static int diag_dev_rows(void)
+{
+ int entries = ptdata.nr_cooling_dev + 1;
+ int rows = max(DIAG_DEV_ROWS, (entries + 1) / 2);
+ return min(rows, entries);
+}
+
void setup_windows(void)
{
int y_begin = 1;
@@ -122,7 +146,7 @@
* dialogue window is a pop-up, when needed it lays on top of cdev win
*/
- dialogue_window = subwin(stdscr, ptdata.nr_cooling_dev+5, maxx-50,
+ dialogue_window = subwin(stdscr, diag_dev_rows() + 5, maxx-50,
DIAG_Y, DIAG_X);
thermal_data_window = subwin(stdscr, ptdata.nr_tz_sensor *
@@ -258,21 +282,23 @@
}
const char DIAG_TITLE[] = "[ TUNABLES ]";
-#define DIAG_DEV_ROWS 5
void show_dialogue(void)
{
int j, x = 0, y = 0;
+ int rows, cols;
WINDOW *w = dialogue_window;
if (tui_disabled || !w)
return;
+ getmaxyx(w, rows, cols);
+
werase(w);
box(w, 0, 0);
mvwprintw(w, 0, maxx/4, DIAG_TITLE);
/* list all the available tunables */
for (j = 0; j <= ptdata.nr_cooling_dev; j++) {
- y = j % DIAG_DEV_ROWS;
+ y = j % diag_dev_rows();
if (y == 0 && j != 0)
x += 20;
if (j == ptdata.nr_cooling_dev)
@@ -283,12 +309,10 @@
ptdata.cdi[j].type, ptdata.cdi[j].instance);
}
wattron(w, A_BOLD);
- mvwprintw(w, DIAG_DEV_ROWS+1, 1, "Enter Choice [A-Z]?");
+ mvwprintw(w, diag_dev_rows()+1, 1, "Enter Choice [A-Z]?");
wattroff(w, A_BOLD);
- /* y size of dialogue win is nr cdev + 5, so print legend
- * at the bottom line
- */
- mvwprintw(w, ptdata.nr_cooling_dev+3, 1,
+ /* print legend at the bottom line */
+ mvwprintw(w, rows - 2, 1,
"Legend: A=Active, P=Passive, C=Critical");
wrefresh(dialogue_window);
@@ -437,7 +461,7 @@
snprintf(buf, sizeof(buf), "New Value for %.10s-%2d: ",
ptdata.cdi[cdev_id].type,
ptdata.cdi[cdev_id].instance);
- write_dialogue_win(buf, DIAG_DEV_ROWS+2, 2);
+ write_dialogue_win(buf, diag_dev_rows() + 2, 2);
handle_input_val(cdev_id);
} else {
snprintf(buf, sizeof(buf), "Invalid selection %d", ch);
